From: Lothar Waßmann Date: Mon, 24 Aug 2015 11:45:51 +0000 (+0200) Subject: Merge branch 'karo-tx-uboot' into kc-merge X-Git-Tag: KARO-TX6-2015-09-18~4034 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=3d5920a31bb846249385e1ca5c086662c39bc44e;hp=71441b628c8258d5681b43929b99e9c3110f09ae Merge branch 'karo-tx-uboot' into kc-merge Conflicts: board/karo/common/mmc.c board/karo/tx6/Makefile board/karo/tx6/pmic.c board/karo/tx6/pmic.h board/karo/tx6/tx6qdl.c boards.cfg include/configs/tx6.h --- diff --git a/.gitignore b/.gitignore index 7b59233ebd..2cba50167e 100644 --- a/.gitignore +++ b/.gitignore @@ -5,18 +5,24 @@ # # Normal rules # - -*.rej -*.orig -*.a +.* *.o +*.o.* +*.a +*.s *.su -*~ +*.mod.c +*.i +*.lst +*.order +*.elf *.swp -*.patch *.bin +*.patch *.cfgtmp -*.dts.tmp + +# host programs on Cygwin +*.exe # Build tree /build-* @@ -24,43 +30,30 @@ # # Top-level generic files # - -/MLO +/MLO* /SPL /System.map -/u-boot -/u-boot.hex -/u-boot.imx -/u-boot-with-spl.imx -/u-boot-with-nand-spl.imx -/u-boot.map -/u-boot.srec -/u-boot.ldr -/u-boot.ldr.hex -/u-boot.ldr.srec -/u-boot.img -/u-boot.kwb -/u-boot.sha1 -/u-boot.dis -/u-boot.lds -/u-boot.ubl -/u-boot.ais -/u-boot.dtb -/u-boot.sb -/u-boot.bd -/u-boot.geany +/u-boot* +/boards.cfg # -# Generated files +# git files that we don't want to ignore even it they are dot-files # +!.gitignore +!.mailmap -*.depend* +# +# Generated files +# /LOG -/errlog -/reloc_off +/spl/ +/tpl/ +# +# Generated include files +# +/include/config/ /include/generated/ -asm-offsets.s # stgit generated dirs patches-* @@ -88,5 +81,6 @@ GRTAGS GSYMS GTAGS -# spl ais files -/spl/*.ais +*.orig +*~ +\#*# diff --git a/.mailmap b/.mailmap new file mode 100644 index 0000000000..e1c666334a --- /dev/null +++ b/.mailmap @@ -0,0 +1,27 @@ +# +# This list is used by git-shortlog to fix a few botched name translations +# in the git archive, either because the author's full name was messed up +# and/or not always written the same way, making contributions from the +# same person appearing not to be so or badly displayed. +# +# This file can be modified by hand or updated by the following command: +# scripts/mailmapper > tmp; mv tmp .mailmap +# + +Allen Martin +Andreas Bießmann +Aneesh V +Dirk Behme +Fabio Estevam +Jagannadha Sutradharudu Teki <402jagan@gmail.com> +Markus Klotzbuecher +Prabhakar Kushwaha +Rajeshwari Shinde +Sandeep Paulraj +Shaohui Xie +Stefan Roese +Stefano Babic +TsiChung Liew +Wolfgang Denk +York Sun +Łukasz Majewski diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 0000000000..90f0fd7615 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,150 @@ +# Copyright Roger Meier +# SPDX-License-Identifier: GPL-2.0+ + +# build U-Boot on Travis CI - https://travis-ci.org/ + +language: c + +cache: + - apt + +install: + # install U-Boot build dependencies + - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev gcc-arm-linux-gnueabi gcc-arm-linux-gnueabihf + # install latest device tree compiler + - git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc + - make -j4 -C /tmp/dtc + # prepare buildman environment + - export BUILDMAN_ROOT="root:" + - export BUILDMAN_MIPS="mips:" + - export BUILDMAN_PPC="ppc:" + - echo -e "[toolchain]\\n${BUILDMAN_ROOT} /\n" > ~/.buildman + - echo -e "${BUILDMAN_MIPS} /opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/" >> ~/.buildman + - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/" >> ~/.buildman + - export BUILDMAN_ALIAS="x86:" + - echo -e "[toolchain-alias]\\n${BUILDMAN_ALIAS} i386" >> ~/.buildman + - cat ~/.buildman + +env: + global: + - PATH=/tmp/dtc:$PATH + - BUILD_DIR=build + - CROSS_COMPILE="" + - HOSTCC="cc" + - HOSTCXX="c++" + - TEST_CONFIG_CMD="" + +before_script: + # install toolchains based on INSTALL_TOOLCHAIN} variable + - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi + - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi + - if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/mips/eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh ; fi + - if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then sh eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh -y ; fi + +script: + # the execution sequence for each test + - echo ${TEST_CONFIG_CMD} + - ${TEST_CONFIG_CMD} + - echo ${TEST_CMD} + - ${TEST_CMD} + +matrix: + include: + # we need to build by vendor due to 50min time limit for builds + # each env setting here is a dedicated build + - env: + - TEST_CMD="./MAKEALL -a arm -v atmel" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a arm -v denx" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a arm -v freescale" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a arm -v siemens" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a arm -v ti" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CONFIG_CMD="make sandbox_defconfig" + TEST_CMD="make -j4" + HOSTCC = "gcc" + HOSTCXX = "g++" + - env: + - TEST_CONFIG_CMD="make sandbox_defconfig" + TEST_CMD="make -j4" + HOSTCC = "clang" + HOSTCXX = "clang++" + - env: + - TEST_CMD="./MAKEALL -a mips" + INSTALL_TOOLCHAIN="mips" + CROSS_COMPILE="/opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/mips-linux-" + - env: + - TEST_CMD="tools/buildman/buildman --list-error-boards atmel" + - env: + - TEST_CMD="tools/buildman/buildman --list-error-boards denx" + - env: + - TEST_CMD="tools/buildman/buildman --list-error-boards freescale arm" + - env: + - TEST_CMD="tools/buildman/buildman --list-error-boards siemens" + - env: + - TEST_CMD="tools/buildman/buildman --list-error-boards ti" + - env: + - TEST_CMD="tools/buildman/buildman mips" + INSTALL_TOOLCHAIN="mips" + - env: + - TEST_CMD="tools/buildman/buildman mpc5xx" + INSTALL_TOOLCHAIN="ppc" + - env: + - TEST_CMD="tools/buildman/buildman mpc8xx" + INSTALL_TOOLCHAIN="ppc" + - env: + - TEST_CMD="tools/buildman/buildman mpc5xxx" + INSTALL_TOOLCHAIN="ppc" + - env: + - TEST_CMD="tools/buildman/buildman mpc512x" + INSTALL_TOOLCHAIN="ppc" + - env: + - TEST_CMD="tools/buildman/buildman mpc824x" + INSTALL_TOOLCHAIN="ppc" + - env: + - TEST_CMD="tools/buildman/buildman mpc8260" + INSTALL_TOOLCHAIN="ppc" + - env: + - TEST_CMD="tools/buildman/buildman mpc83xx" + INSTALL_TOOLCHAIN="ppc" + - env: + - TEST_CMD="tools/buildman/buildman mpc85xx" + INSTALL_TOOLCHAIN="ppc" + - env: + - TEST_CMD="tools/buildman/buildman mpc86xx" + INSTALL_TOOLCHAIN="ppc" + + - env: + - TEST_CMD="tools/buildman/buildman --list-error-boards sandbox x86" + + # QA jobs for code analytics + # static code analysis with cppcheck (we can add --enable=all later) + - env: + - TEST_CMD="cppcheck --force --quiet --inline-suppr ." + # search for TODO within source tree + - env: + - TEST_CMD="grep -r TODO ." + # search for FIXME within source tree + - env: + - TEST_CMD="grep -r FIXME ." + # search for HACK within source tree and ignore HACKKIT board + - env: + - TEST_CMD="grep -r HACK . | grep -v HACKKIT" + script: + - grep -r HACK . | grep -v HACKKIT + # some statistics about the code base + - env: + - TEST_CMD="sloccount ." + +notifications: + email: false + +# TODO make it perfect ;-r diff --git a/CREDITS b/CREDITS deleted file mode 100644 index 3b657e9005..0000000000 --- a/CREDITS +++ /dev/null @@ -1,540 +0,0 @@ -# -# Parts of the development effort for this project have been -# sponsored by SIEMENS AG, Austria. Thanks to SIEMENS for -# supporting an Open Source project! -# -# -# This is at least a partial credits-file of individual people that -# have contributed to the U-Boot project. It is sorted by name and -# formatted to allow easy grepping and beautification by scripts. -# The fields are: name (N), email (E), web-address (W), PGP key ID -# and fingerprint (P), description (D), and snail-mail address (S). -# Thanks, -# -# Wolfgang Denk -#---------- - -N: Dr. Bruno Achauer -E: bruno@exet-ag.de -D: Support for NetBSD (both as host and target system) - -N: Guillaume Alexandre -E: guillaume.alexandre@gespac.ch -D: Add PCIPPC6 configuration - -N: Pantelis Antoniou -E: panto@intracom.gr -D: NETVIA & NETPHONE board support, ARTOS support. -D: Support for Silicon Turnkey eXpress XTc - -N: Pierre Aubert -E: -D: Support for RPXClassic board - -N: Yuli Barcohen -E: yuli@arabellasw.com -D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards. -D: Support for Zephyr Engineering ZPC.1900 board. -D: Support for Interphase iSPAN boards. -D: Support for Analogue&Micro Adder boards. -D: Support for Analogue&Micro Rattler boards. -W: http://www.arabellasw.com - -N: Jerry van Baren -E: -D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test. - -N: Pavel Bartusek -E: -D: Reiserfs support -W: http://www.elinos.com - -N: Andre Beaudin -E: -D: PCMCIA, Ethernet, TFTP - -N: Jon Benediktsson -E: jonb@marel.is -D: Support for Marel V37 board - -N: Raphael Bossek -E: raphael.bossek@solutions4linux.de -D: 8xxrom-0.3.0 - -N: Cliff Brake -E: cliff.brake@gmail.com -D: Port to Vibren PXA255 IDP platform -W: http://www.vibren.com -W: http://bec-systems.com - -N: Rick Bronson -E: rick@efn.org -D: Atmel AT91RM9200DK and NAND support - -N: David Brown -E: DBrown03@harris.com -D: Extensions to 8xxrom-0.3.0 - -N: Oliver Brown -E: obrown@adventnetworks.com -D: Port to the gw8260 board - -N: Jonathan De Bruyne -E: jonathan.debruyne@siemens.atea.be -D: Port to Siemens IAD210 board - -N: Ken Chou -E: kchou@ieee.org -D: Support for A3000 SBC board - -N: Conn Clark -E: clark@esteem.com -D: ESTEEM192E support - -N: Magnus Damm -E: damm@opensource.se -D: 8xxrom - -N: Richard Danter -E: richard.danter@windriver.com -D: Support for Wind River PPMC 7xx/74xx boards - -N: George G. Davis -E: gdavis@mvista.com -D: Board ports for ADS GraphicsClient+ and Intel Assabet - -N: Arun Dharankar -E: ADharankar@ATTBI.Com -D: threads / scheduler example code - -N: K?ri Dav??sson -E: kd@flaga.is -D: FLAGA DM Support - -N: Wolfgang Denk -E: wd@denx.de -D: U-Boot initial version, continuing maintenance, ARMBoot merge -W: http://www.denx.de - -N: Dan A. Dickey -E: ddickey@charter.net -D: FADS Support - -N: James F. Dougherty -E: jfd@GigabitNetworks.COM -D: Port to the MOUSSE board - -N: Mike Dunn -E: mikedunn@newsguy.com -D: Palmtreo680 board, docg4 nand flash driver - -N: Dave Ellis -E: DGE@sixnetio.com -D: EEPROM Speedup, SXNI855T port - -N: Daniel Engstr?m -E: daniel@omicron.se -D: x86 port, Support for sc520_cdp board - -N: Hayden Fraser -E: Hayden.Fraser@freescale.com -D: Support for ColdFire MCF5253 -W: www.freescale.com - -N: Dr. Wolfgang Grandegger -E: wg@denx.de -D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards -W: www.denx.de - -N: Peter Figuli -E: peposh@etc.sk -D: Support for WEP EP250 (PXA) board - -N: Thomas Frieden -E: ThomasF@hyperion-entertainment.com -D: Support for AmigaOne - -N: Paul Gortmaker -E: paul.gortmaker@windriver.com -D: Support for WRS SBC8347/8349 boards - -N: Frank Gottschling -E: fgottschling@eltec.de -D: Support for ELTEC MHPC/ELPPC boards, cfb-console, i8042, SMI LynxEM -W: www.eltec.de - -N: Marius Groeger -E: mgroeger@sysgo.de -D: MBX Support, board specific function interface, EST SBC8260 support; initial support for StrongARM (LART), ARM720TDMI (implementa A7) -W: www.elinos.com - -N: Kirk Haderlie -E: khaderlie@vividimage.com -D: Added TFTP to 8xxrom (-> 0.3.1) - -N: Chris Hallinan -E: clh@net1plus.com -D: DHCP Support - -N: Anne-Sophie Harnois -E: Anne-Sophie.Harnois@nextream.fr -D: Port to Walnut405 board - -N: Andreas Heppel -E: aheppel@sysgo.de -D: CPU Support for MPC 75x - -N: Josh Huber -E: huber@alum.wpi.edu -D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series. -W: http://www.mclx.com/ - -H: Stuart Hughes -E: stuarth@lineo.com -D: Port to MPC8260ADS board - -H: Rich Ireland -E: r.ireland@computer.org -D: FPGA device configuration driver - -H: Mark Jackson -E: mpfj@mimc.co.uk -D: Port to MIMC200 board - -N: Gary Jennejohn -E: garyj@jennejohn.org -D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB" -W: www.denx.de - -N: Murray Jensen -E: Murray.Jensen@csiro.au -D: Initial 8260 support; GDB support -D: Port to Cogent+Hymod boards; Hymod Board Database - -N: Yoo. Jonghoon -E: yooth@ipone.co.kr -D: Added port to the RPXlite board - -N: Mark Jonas -E: mark.jonas@freescale.com -D: Support for Freescale Total5200 platform -W: http://www.mobilegt.com/ - -N: Mark Jonas -E: mark.jonas@de.bosch.com -D: Support for MPR2 board - -N: Sam Song -E: samsongshu@yahoo.com.cn -D: Port to the RPXlite_DW board - -N: Brad Kemp -E: Brad.Kemp@seranoa.com -D: Port to Windriver ppmc8260 board - -N: Sangmoon Kim -E: dogoil@etinsys.com -D: Support for debris board -D: Support for KVME080 board - -N: Frederick W. Klatt -E: fred.klatt@windriver.com -D: Support for Wind River SBC8540/SBC8560 boards - -N: Thomas Koeller -E: tkoeller@gmx.net -D: Port to Motorola Sandpoint 3 (MPC8240) - -N: Raghu Krishnaprasad -E: Raghu.Krishnaprasad@fci.com -D: Support for Adder-II MPC852T evaluation board -W: http://www.forcecomputers.com - -N: Sergey Kubushyn -E: ksi@koi8.net -D: Support for various TI DaVinci based boards. - -N: Bernhard Kuhn -E: bkuhn@metrowerks.com -D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards - -N: Prakash Kumar -E: prakash@embedx.com -D Support for Intrinsyc CERF PXA250 board. - -N: Thomas Lange -E: thomas@corelatus.se -D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes - -N: The LEOX team -E: team@leox.org -D: Support for LEOX boards, DS164x RTC -W: http://www.leox.org - -N: TsiChung Liew -E: Tsi-Chung.Liew@freescale.com -D: Support for ColdFire MCF523x, MCF532x, MCF5445x, MCF547x_8x -W: www.freescale.com - -N: Leif Lindholm -E: leif.lindholm@i3micro.com -D: Support for AMD dbau1550 board. - -N: Stephan Linz -E: linz@li-pro.net -D: Support for Nios Stratix Development Kit (DK-1S10) -D: Support for SSV ADNP/ESC1 (Nios Cyclone) -W: http://www.li-pro.net - -N: Dave Liu -E: daveliu@freescale.com -D: Support for MPC8315, MPC832x, MPC8360, MPC837x -W: www.freescale.com - -N: Raymond Lo -E: lo@routefree.com -D: Support for DOS partitions - -N: James MacAulay -E: james.macaulay@amirix.com -D: Suppport for Amirix AP1000 -W: www.amirix.com - -N: Dan Malek -E: dan@embeddedalley.com -D: FADSROM, the grandfather of all of this -D: Support for Silicon Turnkey eXpress XTc - -N: Andrea "llandre" Marson -E: andrea.marson@dave-tech.it -D: Port to PPChameleonEVB board -W: www.dave-tech.it - -N: Reinhard Meyer -E: r.meyer@emk-elektronik.de -D: Port to EMK TOP860 Module - -N: Jay Monkman -E: jtm@smoothsmoothie.com -D: EST SBC8260 support - -N: Frank Morauf -E: frank.morauf@salzbrenner.com -D: Support for Embedded Planet RPX Super Board - -N: David M?ller -E: d.mueller@elsoft.ch -D: Support for Samsung ARM920T SMDK2410 eval board - -N: Scott McNutt -E: smcnutt@psyent.com -D: Support for Altera Nios-32 CPU -D: Support for Altera Nios-II CPU -D: Support for Nios Cyclone Development Kit (DK-1C20) -W: http://www.psyent.com - -N: Rolf Offermanns -E: rof@sysgo.de -D: Initial support for SSV-DNP1110, SMC91111 driver -W: www.elinos.com - -N: John Otken -E: jotken@softadvances.com -D: Support for AMCC Luan 440SP board - -N: Tolunay Orkun -E: torkun@nextio.com -D: Support for Cogent CSB272 & CSB472 boards - -N: Keith Outwater -E: keith_outwater@mvis.com -D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC) - -N: Frank Panno -E: fpanno@delphintech.com -D: Support for Embedded Planet EP8260 Board - -N: Denis Peter -E: d.peter@mpl.ch -D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ... -D: Support for PIP405 board -D: Support for MIP405 board - -N: Dave Peverley -E: dpeverley@mpc-data.co.uk -W: http://www.mpc-data.co.uk -D: OMAP730 P2 board support - -N: Bill Pitts -E: wlp@mindspring.com -D: BedBug embedded debugger code - -N: Daniel Poirot -E: dan.poirot@windriver.com -D: Support for the Wind River sbc405, sbc8240 board -W: http://www.windriver.com - -N: Stelian Pop -E: stelian@popies.net -D: Atmel AT91CAP9ADK support - -N: Ricardo Ribalda Delgado -E: ricardo.ribalda@uam.es -D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval -D: Virtex ppc440 generic architecture -D: Virtex ppc405 generic architecture -W: http://www.ii.uam.es/~rribalda - -N: Stefan Roese -E: sr@denx.de -D: AMCC PPC4xx Support -W: http://www.denx.de - -N: Erwin Rol -E: erwin@muffin.org -D: boot support for RTEMS - -N: Paul Ruhland -E: pruhland@rochester.rr.com -D: Port to Logic Zoom LH7A40x SDK board(s) - -N: Neil Russell -E: caret@c-side.com -D: Author of LiMon-1.4.2, which contributed some ideas - -N: Travis B. Sawyer -E: travis.sawyer@sandburst.com -D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea) - -N: Paolo Scaffardi -E: arsenio@tin.it -D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more - -N: Andre Schwarz -E: andre.schwarz@matrix-vision.de -D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR) - -N: Robert Schwebel -E: r.schwebel@pengutronix.de -D: Support for csb226 and innokom boards (PXA2xx) - -N: Aaron Sells -E: sellsa@embeddedplanet.com -D: Support for EP82xxM - -N: Art Shipkowski -E: art@videon-central.com -D: Support for NetSilicon NS7520 -D: Support for ColdFire MCF5275 - -N: Jeremy C. Andrus -E: jeremy@jeremya.com -D: ColdFire MCF5249 initialization code -W: jeremya.com - -N: Michal Simek -E: monstr@monstr.eu -D: Support for Microblaze, ML401, XUPV2P board -W: www.monstr.eu - -N: Yasushi Shoji -E: yashi@atmark-techno.com -D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board - -N: Kurt Stremerch -E: kurt@exys.be -D: Support for Exys XSEngine board - -N: Andrea Scian -E: andrea.scian@dave-tech.it -D: Port to B2 board -W: www.dave-tech.it - -N: Timur Tabi -E: timur@freescale.com -D: Support for MPC8349E-mITX -W: www.freescale.com - -N: Rob Taylor -E: robt@flyingpig.com -D: Port to MBX860T and Sandpoint8240 - -N: Erik Theisen -E: etheisen@mindspring.com -D: MBX8xx and many other patches - -N: Jim Thompson -E: jim@musenki.com -D: Support for MUSENKI board - -N: Rune Torgersen -E: -D: Support for Motorola MPC8266ADS board - -N: Greg Ungerer -E: greg.ungerer@opengear.com -D: Support for ks8695 CPU, and OpenGear cmXXXX boards - -N: David Updegraff -E: dave@cray.com -D: Port to Cray L1 board; DHCP vendor extensions - -N: Christian Vejlbo -E: christian.vejlbo@tellabs.com -D: FADS860T ethernet support - -N: Robert Whaley -E: rwhaley@applieddata.net -D: Port to ARM PXA27x adsvix SBC - -N: Martin Winistoerfer -E: martinwinistoerfer@gmx.ch -D: Port to MPC555/556 microcontrollers and support for cmi board - -N: David Wu -E: support@arcturusnetworks.com -D: Mercury Security EP2500 -W: http://www.arcturusnetworks.com - -N: Ming-Len Wu -E: minglen_wu@techware.com.tw -D: Motorola MX1ADS board support -W: http://www.techware.com.tw/ - -N: Xianghua Xiao -E: x.xiao@motorola.com -D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards. - -N: John Zhan -E: zhanz@sinovee.com -D: Support for SinoVee Microsystems SC8xx SBC - -N: Alex Zuepke -E: azu@sysgo.de -D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM -W: www.elinos.com - -N: Nobuhiro Iwamatsu -E: iwamatsu@nigauri.org -D: Support for SuperH, MS7750SE01 and MS7722SE01 boards. -W: http://www.nigauri.org/~iwamatsu/ - -N: Alan Lu -E: alnalu001@gmail.com -D: Support for Artila M-501 starter kit -W: http://www.artila.com/ - -N: Kimmo Leppala -E: kimmo.leppala@sysart.fi -D: Support for Artila M-501 starter kit -W: http://www.sysart.fi/ - -N: Timo Tuunainen -E: timo.tuunainen@sysart.fi -D: Support for Artila M-501 starter kit -W: http://www.sysart.fi/ - -N: Philip Balister -E: philip@opensdr.com -D: Port to Lyrtech SFFSDR development board. -W: www.opensdr.com diff --git a/Kbuild b/Kbuild new file mode 100644 index 0000000000..ef97787bf4 --- /dev/null +++ b/Kbuild @@ -0,0 +1,88 @@ +# +# Kbuild for top-level directory of U-Boot +# This file takes care of the following: +# 1) Generate generic-asm-offsets.h +# 2) Generate asm-offsets.h + +##### +# 1) Generate generic-asm-offsets.h + +generic-offsets-file := include/generated/generic-asm-offsets.h + +always := $(generic-offsets-file) +targets := $(generic-offsets-file) lib/asm-offsets.s + +quiet_cmd_generic-offsets = GEN $@ +define cmd_generic-offsets + (set -e; \ + echo "#ifndef __GENERIC_ASM_OFFSETS_H__"; \ + echo "#define __GENERIC_ASM_OFFSETS_H__"; \ + echo "/*"; \ + echo " * DO NOT MODIFY."; \ + echo " *"; \ + echo " * This file was generated by Kbuild"; \ + echo " *"; \ + echo " */"; \ + echo ""; \ + sed -ne $(sed-y) $<; \ + echo ""; \ + echo "#endif" ) > $@ +endef + +# We use internal kbuild rules to avoid the "is up to date" message from make +lib/asm-offsets.s: lib/asm-offsets.c FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cc_s_c) + +$(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild + $(Q)mkdir -p $(dir $@) + $(call cmd,generic-offsets) + +##### +# 2) Generate asm-offsets.h +# + +ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),) +offsets-file := include/generated/asm-offsets.h +endif + +always += $(offsets-file) +targets += $(offsets-file) +targets += arch/$(ARCH)/lib/asm-offsets.s + + +# Default sed regexp - multiline due to syntax constraints +define sed-y + "s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \ + /^->/{s:->#\(.*\):/* \1 */:; \ + s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \ + s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ + s:->::; p;}" +endef + +CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY + +quiet_cmd_offsets = GEN $@ +define cmd_offsets + (set -e; \ + echo "#ifndef __ASM_OFFSETS_H__"; \ + echo "#define __ASM_OFFSETS_H__"; \ + echo "/*"; \ + echo " * DO NOT MODIFY."; \ + echo " *"; \ + echo " * This file was generated by Kbuild"; \ + echo " *"; \ + echo " */"; \ + echo ""; \ + sed -ne $(sed-y) $<; \ + echo ""; \ + echo "#endif" ) > $@ +endef + +# We use internal kbuild rules to avoid the "is up to date" message from make +arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cc_s_c) + +$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild + $(call cmd,offsets) diff --git a/Kconfig b/Kconfig new file mode 100644 index 0000000000..861622664f --- /dev/null +++ b/Kconfig @@ -0,0 +1,168 @@ +# +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.txt. +# +mainmenu "U-Boot $UBOOTVERSION Configuration" + +config UBOOTVERSION + string + option env="UBOOTVERSION" + +config KCONFIG_OBJDIR + string + option env="KCONFIG_OBJDIR" + +menu "General setup" + +config LOCALVERSION + string "Local version - append to U-Boot release" + depends on !SPL_BUILD + help + Append an extra string to the end of your U-Boot version. + This will show up on your boot log, for example. + The string you set here will be appended after the contents of + any files with a filename matching localversion* in your + object and source tree, in that order. Your total string can + be a maximum of 64 characters. + +config LOCALVERSION_AUTO + bool "Automatically append version information to the version string" + depends on !SPL_BUILD + default y + help + This will try to automatically determine if the current tree is a + release tree by looking for git tags that belong to the current + top of tree revision. + + A string of the format -gxxxxxxxx will be added to the localversion + if a git-based tree is found. The string generated by this will be + appended after any matching localversion* files, and after the value + set in CONFIG_LOCALVERSION. + + (The actual string used here is the first eight characters produced + by running the command: + + $ git rev-parse --verify HEAD + + which is done within the script "scripts/setlocalversion".) + +config CC_OPTIMIZE_FOR_SIZE + bool "Optimize for size" + depends on !SPL_BUILD + default y + help + Enabling this option will pass "-Os" instead of "-O2" to gcc + resulting in a smaller U-Boot image. + + This option is enabled by default for U-Boot. + +menuconfig EXPERT + bool "Configure standard U-Boot features (expert users)" + help + This option allows certain base U-Boot options and settings + to be disabled or tweaked. This is for specialized + environments which can tolerate a "non-standard" U-Boot. + Only use this if you really know what you are doing. + +endmenu # General setup + +menu "Boot images" + +config SPL_BUILD + bool + default y if $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl" + +config TPL_BUILD + bool + depends on $KCONFIG_OBJDIR="tpl" + default y + +config SUPPORT_SPL + bool + +config SUPPORT_TPL + bool + +config SPL + bool + depends on SUPPORT_SPL + prompt "Enable SPL" if !SPL_BUILD + default y if SPL_BUILD + help + If you want to build SPL as well as the normal image, say Y. + +config TPL + bool + depends on SPL && SUPPORT_TPL + prompt "Enable TPL" if !SPL_BUILD + default y if TPL_BUILD + default n + help + If you want to build TPL as well as the normal image and SPL, say Y. + +config FIT + bool "Support Flattened Image Tree" + depends on !SPL_BUILD + help + This option allows to boot the new uImage structrure, + Flattened Image Tree. FIT is formally a FDT, which can include + images of various types (kernel, FDT blob, ramdisk, etc.) + in a single blob. To boot this new uImage structure, + pass the the address of the blob to the "bootm" command. + +config FIT_VERBOSE + bool "Display verbose messages on FIT boot" + depends on FIT + +config FIT_SIGNATURE + bool "Enable signature verification of FIT uImages" + depends on FIT + select RSA + help + This option enables signature verification of FIT uImages, + using a hash signed and verified using RSA. + See doc/uImage.FIT/signature.txt for more details. + +config SYS_EXTRA_OPTIONS + string "Extra Options (DEPRECATED)" + depends on !SPL_BUILD + help + The old configuration infrastructure (= mkconfig + boards.cfg) + provided the extra options field. If you have something like + "HAS_BAR,BAZ=64", the optional options + #define CONFIG_HAS + #define CONFIG_BAZ 64 + will be defined in include/config.h. + This option was prepared for the smooth migration from the old + configuration to Kconfig. Since this option will be removed sometime, + new boards should not use this option. + +config SYS_TEXT_BASE + depends on SPARC + hex "Text Base" + help + TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture + +config SYS_CLK_FREQ + depends on ARC + int "CPU clock frequency" + help + TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture + +endmenu # Boot images + +source "arch/Kconfig" + +source "common/Kconfig" + +source "disk/Kconfig" + +source "dts/Kconfig" + +source "net/Kconfig" + +source "drivers/Kconfig" + +source "fs/Kconfig" + +source "lib/Kconfig" diff --git a/Licenses/README b/Licenses/README index b1a59cc22f..fe6dadcc7d 100644 --- a/Licenses/README +++ b/Licenses/README @@ -37,16 +37,33 @@ replaced by a single line: SPDX-License-Identifier: GPL-2.0+ +Ideally, the license terms of all files in the source tree should be +defined by such License Identifiers; in no case a file can contain +more than one such License Identifier list. + +If a "SPDX-License-Identifier:" line references more than one Unique +License Identifier, then this means that the respective file can be +used under the terms of either of these licenses, i. e. with + + SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + +you can chose between GPL-2.0+ and BSD-3-Clause licensing. + We use the SPDX Unique License Identifiers here; these are available at [2]. [1] http://spdx.org/ [2] http://spdx.org/licenses/ -Full name SPDX Identifier OSI Approved File name URI +Full name SPDX Identifier OSI Approved File name URI ======================================================================================================================================= -GNU General Public License v2.0 only GPL-2.0 Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt -GNU General Public License v2.0 or later GPL-2.0+ Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt -GNU Library General Public License v2 or later LGPL-2.0+ Y lgpl-2.0.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt -GNU Lesser General Public License v2.1 or later LGPL-2.1+ Y lgpl-2.1.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt -eCos license version 2.0 eCos-2.0 eCos-2.0.txt http://www.gnu.org/licenses/ecos-license.html +GNU General Public License v2.0 only GPL-2.0 Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt +GNU General Public License v2.0 or later GPL-2.0+ Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt +GNU Library General Public License v2 or later LGPL-2.0+ Y lgpl-2.0.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt +GNU Lesser General Public License v2.1 or later LGPL-2.1+ Y lgpl-2.1.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt +eCos license version 2.0 eCos-2.0 eCos-2.0.txt http://www.gnu.org/licenses/ecos-license.html +BSD 2-Clause License BSD-2-Clause Y bsd-2-clause.txt http://spdx.org/licenses/BSD-2-Clause +BSD 3-clause "New" or "Revised" License BSD-3-Clause Y bsd-3-clause.txt http://spdx.org/licenses/BSD-3-Clause#licenseText +IBM PIBS (PowerPC Initialization and IBM-pibs ibm-pibs.txt + Boot Software) license +ISC License ISC Y isc.txt https://spdx.org/licenses/ISC diff --git a/Licenses/bsd-2-clause.txt b/Licenses/bsd-2-clause.txt new file mode 100644 index 0000000000..af697645fe --- /dev/null +++ b/Licenses/bsd-2-clause.txt @@ -0,0 +1,25 @@ +Redistribution and use in source and binary forms, with or +without modification, are permitted provided that the following +conditions are met: + +1. Redistributions of source code must retain the above + copyright notice, this list of conditions and the following + disclaimer. +2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/Licenses/bsd-3-clause.txt b/Licenses/bsd-3-clause.txt new file mode 100644 index 0000000000..aac5e2a803 --- /dev/null +++ b/Licenses/bsd-3-clause.txt @@ -0,0 +1,24 @@ +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions, and the following disclaimer, + without modification. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The names of the above-listed copyright holders may not be used + to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/Licenses/ibm-pibs.txt b/Licenses/ibm-pibs.txt new file mode 100644 index 0000000000..4cd7523647 --- /dev/null +++ b/Licenses/ibm-pibs.txt @@ -0,0 +1,17 @@ +This source code has been made available to you by IBM on an AS-IS +basis. Anyone receiving this source is licensed under IBM +copyrights to use it in any way he or she deems fit, including +copying it, modifying it, compiling it, and redistributing it either +with or without modifications. No license under IBM patents or +patent applications is to be implied by the copyright license. + +Any user of this software should understand that IBM cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work +must include the IBM copyright notice, this paragraph, and the +preceding two paragraphs in the transferred software. + +COPYRIGHT I B M CORPORATION 1995 +LICENSED MATERIAL - PROGRAM PROPERTY OF I B M diff --git a/Licenses/isc.txt b/Licenses/isc.txt new file mode 100644 index 0000000000..4b7c2ba25b --- /dev/null +++ b/Licenses/isc.txt @@ -0,0 +1,17 @@ +ISC License: +Copyright (c) 2004-2010 by Internet Systems Consortium, Inc. ("ISC") +Copyright (c) 1995-2003 by Internet Software Consortium + +Permission to use, copy, modify, and/or distribute this software +for any purpose with or without fee is hereby granted, +provided that the above copyright notice and this permission notice +appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE +FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. diff --git a/MAINTAINERS b/MAINTAINERS index c6fd555298..1f7735922d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1,1391 +1,425 @@ -######################################################################### -# # -# Regular Maintainers for U-Boot board support: # -# # -# For any board without permanent maintainer, please contact # -# Wolfgang Denk # -# and Cc: the mailing list. # -# # -# Note: lists sorted by Maintainer Name # -# Note: These are the maintainers for specific *boards*. The # -# custodians for general architectures and subsystems can # -# be found here -- http://www.denx.de/wiki/U-Boot/Custodians # -# # -######################################################################### - - -######################################################################### -# PowerPC Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Poonam Aggrwal - - P2020RDB P2020 - - BSC9131RDB BSC9131 - -Naveen Burmi - - BSC9132QDS BSC9132 - -Greg Allen - - UTX8245 MPC8245 - -Pantelis Antoniou - - NETVIA MPC8xx - -Reinhard Arlt - - cpci5200 MPC5200 - mecp5123 MPC5121 - mecp5200 MPC5200 - pf5200 MPC5200 - - caddy2 MPC8349 - vme8349 MPC8349 - - CPCI750 PPC750FX/GX - -Peter Barada - - omap3_logic ARM ARMV7 (Logic OMAP35xx/DM37xx) - -Yuli Barcohen - - Adder MPC87x/MPC852T - ep8248 MPC8248 - ISPAN MPC8260 - MPC8260ADS MPC826x/MPC827x/MPC8280 - Rattler MPC8248 - ZPC1900 MPC8265 - -Michael Barkowski - - MPC8323ERDB MPC8323 - -Jerry Van Baren - - sacsng MPC8260 - -Oliver Brown - - gw8260 MPC8260 - -Holger Brunck - - kmeter1 MPC8360 - kmcoge5ne MPC8360 - mgcoge MPC8247 - mgcoge3ne MPC8247 - suvd3 MPC8321 - tuge1 MPC8321 - tuxx1 MPC8321 - -Conn Clark - - ESTEEM192E MPC8xx - -Jason Cooper - - dreamplug ARM926EJS (Kirkwood SoC) - -Joe D'Abbraccio - - MPC837xERDB MPC837x - -Kári Davíðsson - - FLAGADM MPC823 - -Torsten Demke - - eXalion MPC824x - -Wolfgang Denk - - IceCube_5200 MPC5200 - - ARIA MPC5121e - - FPS850L MPC850 - FPS860L MPC860 - ICU862 MPC862 - IP860 MPC860 - IVML24 MPC860 - IVML24_128 MPC860 - IVML24_256 MPC860 - IVMS8 MPC860 - IVMS8_128 MPC860 - IVMS8_256 MPC860 - LWMON MPC823 - R360MPI MPC823 - RRvision MPC823 - SM850 MPC850 - SPD823TS MPC823 - TQM823L MPC823 - TQM823L_LCD MPC823 - TQM850L MPC850 - TQM855L MPC855 - TQM860L MPC860 - TQM860L_FEC MPC860 - hermes MPC860 - lwmon MPC823 - - CU824 MPC8240 - Sandpoint8240 MPC8240 - - ATC MPC8250 - PM825 MPC8250 - - TQM8255 MPC8255 - - CPU86 MPC8260 - PM826 MPC8260 - TQM8260 MPC8260 - - P3G4 MPC7410 - -Phil Edworthy - - rsk7264 SH7264 - -egnite GmbH - - ethernut5 ARM926EJS (AT91SAM9XE SoC) - -Dirk Eibach - - controlcenterd P1022 - devconcenter PPC460EX - dlvision PPC405EP - dlvision-10g PPC405EP - gdppc440etx PPC440EP/GR - intip PPC460EX - io PPC405EP - io64 PPC405EX - iocon PPC405EP - neo PPC405EP - -Dave Ellis - - SXNI855T MPC8xx - -Thomas Frieden - - AmigaOneG3SE MPC7xx - -Matthias Fuchs - - APC405 PPC405GP - AR405 PPC405GP - ASH405 PPC405EP - CANBT PPC405CR - CPCI2DP PPC405GP - CPCI405 PPC405GP - CPCI4052 PPC405GP - CPCI405AB PPC405GP - CPCI405DT PPC405GP - CPCIISER4 PPC405GP - DP405 PPC405EP - DU405 PPC405GP - DU440 PPC440EPx - G2000 PPC405EP - HH405 PPC405EP - HUB405 PPC405EP - OCRTC PPC405GP - ORSG PPC405GP - PCI405 PPC405GP - PLU405 PPC405EP - PMC405 PPC405GP - PMC405DE PPC405EP - PMC440 PPC440EPx - VOH405 PPC405EP - VOM405 PPC405EP - WUH405 PPC405EP - CMS700 PPC405EP - -Siddarth Gore - - guruplug ARM926EJS (Kirkwood SoC) - -Paul Gortmaker - - sbc8349 MPC8349 - sbc8548 MPC8548 - sbc8641d MPC8641D - -Frank Gottschling - - MHPC MPC8xx - -Wolfgang Grandegger - - ipek01 MPC5200 - - PN62 MPC8240 - IPHASE4539 MPC8260 - -Anatolij Gustschin - - ac14xx MPC5121e - O2D MPC5200 - O2D300 MPC5200 - O2DNT2 MPC5200 - O2I MPC5200 - O2MNT MPC5200 - O3DNT MPC5200 - -Rob Herring - - highbank highbank - -Klaus Heydeck - - KUP4K MPC855 - KUP4X MPC859 - -Gabriel Huau - - mini2440 s3c2440 - -Gary Jennejohn - - quad100hd PPC405EP - -Murray Jensen - - cogent_mpc8xx MPC8xx - - cogent_mpc8260 MPC8260 - hymod MPC8260 - -Larry Johnson - - korat PPC440EPx - -Feng Kan - - redwood PPC4xx - -Brad Kemp - - ppmc8260 MPC8260 - -Sangmoon Kim - - debris MPC8245 - KVME080 MPC8245 - -The LEOX team - - ELPT860 MPC860T - -Guennadi Liakhovetski - - linkstation MPC8241 - -Dave Liu - - MPC8315ERDB MPC8315 - MPC832XEMDS MPC832x - MPC8360EMDS MPC8360 - MPC837XEMDS MPC837x - -Nye Liu - - ZUMA MPC7xx_74xx - -Kumar Gala - - MPC8540ADS MPC8540 - MPC8560ADS MPC8560 - MPC8541CDS MPC8541 - MPC8555CDS MPC8555 - - MPC8641HPCN MPC8641D - -Ron Madrid - - SIMPC8313 MPC8313 - -Dan Malek - - stxgp3 MPC85xx - stxssa MPC85xx - stxxtc MPC8xx - -Ryan Mallon - - snapper9260 ARM926EJS (AT91SAM9260 SoC) - snapper9g20 ARM926EJS (AT91SAM9G20 SoC) - -Andrea "llandre" Marson - - PPChameleonEVB PPC405EP - -Tirumala Marri - - bluestone APM821XX - -Reinhard Meyer - - TOP860 MPC860T - TOP5200 MPC5200 - TOP9000 ARM926EJS (AT91SAM9xxx SoC) - -Kyle Moffett - - HWW1U1A P2020 - -Tolunay Orkun - - csb272 PPC405GP - csb472 PPC405GP - -John Otken - - luan PPC440SP - taihu PPC405EP - -Keith Outwater - - GEN860T MPC860T - GEN860T_SC MPC860T - -Frank Panno - - ep8260 MPC8260 - -Chan-Taek Park - - tnetv107x_evm tnetv107x - -Denis Peter - - MIP405 PPC4xx - PIP405 PPC4xx - -Werner Pfister - digsy_mtc mpc5200 - digsy_mtc_rev5 mpc5200 - -Kim Phillips - - MPC8349EMDS MPC8349 - -Sergei Poselenov - - a4m072 MPC5200 - -Sudhakar Rajashekhara - - da850evm ARM926EJS (DA850/OMAP-L138) - -Ricardo Ribalda - - ml507 PPC440x5 - v5fx30teval PPC440x5 - xilinx-ppc405-generic PPC405 - xilinx-ppc440-generic PPC440x5 - -Stefan Roese - - a3m071 MPC5200 - a4m2k MPC5200 - - P3M7448 MPC7448 - - uc100 MPC857 - - acadia PPC405EZ - alpr PPC440GX - bamboo PPC440EP - bunbinga PPC405EP - canyonlands PPC460EX - ebony PPC440GP - glacier PPC460GT - haleakala PPC405EXr - icon PPC440SPe - katmai PPC440SPe - kilauea PPC405EX - lwmon5 PPC440EPx - makalu PPC405EX - ocotea PPC440GX - p3p440 PPC440GP - pcs440ep PPC440EP - rainier PPC440GRx - sequoia PPC440EPx - sycamore PPC405GPr - t3corp PPC460GT - taishan PPC440GX - walnut PPC405GP - yellowstone PPC440GR - yosemite PPC440EP - zeus PPC405EP - - P3M750 PPC750FX/GX/GL - -Yusdi Santoso - - HIDDEN_DRAGON MPC8241/MPC8245 - -Travis Sawyer (travis.sawyer@sandburst.com> - - KAREF PPC440GX - METROBOX PPC440GX - -Georg Schardt - - fx12mm PPC405 - -Heiko Schocher - - cam_enc_4xx davinci/ARM926EJS - charon MPC5200 - ids8247 MPC8247 - jupiter MPC5200 - kmsupx5 MPC8321 - mucmc52 MPC5200 - muas3001 MPC8270 - municse MPC5200 - sc3 PPC405GP - uc101 MPC5200 - ve8313 MPC8313 - -Andre Schwarz - - mergerbox MPC8377 - mvbc_p MPC5200 - mvblm7 MPC8343 - mvsmr MPC5200 - -Jon Smirl - - pcm030 MPC5200 - -Ira W. Snyder - - P2020COME P2020 - -Timur Tabi - - MPC8349E-mITX MPC8349 - MPC8349E-mITX-GP MPC8349 - P1022DS P1022 - -Erik Theisen - - W7OLMC PPC4xx - W7OLMG PPC4xx - -Jim Thompson - - MUSENKI MPC8245/8241 - Sandpoint8245 MPC8245 - -Rune Torgersen - - MPC8266ADS MPC8266 - -Peter Tyser - - xpedite1000 PPC440GX - xpedite5170 MPC8640 - xpedite5200 MPC8548 - xpedite5370 MPC8572 - xpedite5500 P2020 - -David Updegraff - - CRAYL1 PPC4xx - -Anton Vorontsov - - MPC8360ERDK MPC8360 - -Josef Wagner - - CPC45 MPC8245 - PM520 MPC5200 - -Michael Weiss - - PDM360NG MPC5121e - -Stephen Williams - - JSE PPC405GPr - -Ilya Yanok - - mpc8308_p1m MPC8308 - MPC8308RDB MPC8308 - -Roy Zang - - mpc7448hpc2 MPC7448 - P1023RDS P1023 - -John Zhan - - svm_sc8xx MPC8xx - -Detlev Zundel - - inka4x0 MPC5200 - -------------------------------------------------------------------------- - -Unknown / orphaned boards: - - ADS860 MPC8xx - FADS823 MPC8xx - FADS850SAR MPC8xx - FADS860T MPC8xx - GENIETV MPC8xx - MBX MPC8xx - MBX860T MPC8xx - NX823 MPC8xx - RPXClassic MPC8xx - RPXlite MPC8xx - - MOUSSE MPC824x - - RPXsuper MPC8260 - rsdproto MPC8260 - - EVB64260 MPC7xx_74xx - EVB64260_750CX MPC750CX [Eran Man ] - - versatile ARM926EJ-S - -######################################################################### -# ARM Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Albert ARIBAUD - - edminiv2 ARM926EJS (Orion5x SoC) - -Raphael Assenat - - eco5pk ARM ARMV7 (AM35x SoC) - -Stefano Babic - - ea20 davinci - flea3 i.MX35 - mt_ventoux omap3 - mx35pdk i.MX35 - mx51evk i.MX51 - polaris xscale/pxa - trizepsiv xscale/pxa - twister omap3 - vision2 i.MX51 - woodburn i.MX35 - -Lukasz Dalek - - h2200 xscale/pxa - -Jason Liu - - mx53evk i.MX53 - mx53loco i.MX53 - mx6qarm2 i.MX6Q - mx6qsabrelite i.MX6Q - -Enric Balletbo i Serra - - igep0020 ARM ARMV7 (OMAP3xx SoC) - igep0030 ARM ARMV7 (OMAP3xx SoC) - igep0032 ARM ARMV7 (OMAP3xx SoC) - igep0033 ARM ARMV7 (AM33xx Soc) - -Eric Benard - - cpuat91 ARM920T - cpu9260 ARM926EJS (AT91SAM9260 SoC) - cpu9G20 ARM926EJS (AT91SAM9G20 SoC) - -Ajay Bhargav - - gplugd ARM926EJS (ARMADA100 88AP168 SoC) - -Rishi Bhattacharya - - omap5912osk ARM926EJS - -Andreas Bießmann - - at91rm9200ek at91rm9200 - -Cliff Brake - - pxa255_idp xscale/pxa - -Rick Bronson - - AT91RM9200DK at91rm9200 - -Luca Ceresoli - - dig297 ARM ARMV7 (OMAP3530 SoC) - -Po-Yu Chuang - - a320evb FA526 (ARM920T-like) (a320 SoC) - -Eric Cooper - - dockstar ARM926EJS (Kirkwood SoC) - -Wolfgang Denk - imx27lite i.MX27 - qong i.MX31 - -Mike Dunn - palmtreo680 pxa270 - -Kristoffer Ericson - - jornada SA1110 - -Fabio Estevam - - mx25pdk i.MX25 - mx28evk i.MX28 - mx31pdk i.MX31 - mx53ard i.MX53 - mx53smd i.MX53 - mx6sabresd i.MX6Q/DL - mx6qsabreauto i.MX6Q - wandboard i.MX6DL/S/Q - mx6slevk i.MX6SL - -Daniel Gorsulowski - - meesc ARM926EJS (AT91SAM9263 SoC) - otc570 ARM926EJS (AT91SAM9263 SoC) - -Bo Shen - at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) - at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC) - -Simon Guinot - - inetspace_v2 ARM926EJS (Kirkwood SoC) - netspace_v2 ARM926EJS (Kirkwood SoC) - netspace_max_v2 ARM926EJS (Kirkwood SoC) - net2big_v2 ARM926EJS (Kirkwood SoC) - -Igor Grinberg - - cm_t35 ARM ARMV7 (OMAP3xx Soc) - -Stefan Herbrechtsmeier - - dns325 ARM926EJS (Kirkwood SoC) - -Lauri Hintsala - - apx4devkit i.MX28 - -Vaibhav Hiremath - - am3517_evm ARM ARMV7 (AM35x SoC) - -Markus Hubig - - STAMP9G20 ARM926EJS - -Grazvydas Ignotas - - omap3_pandora ARM ARMV7 (OMAP3xx SoC) - -Ilko Iliev - - PM9261 AT91SAM9261 - PM9263 AT91SAM9263 - PM9G45 ARM926EJS (AT91SAM9G45 SoC) - -Michael Jones - - omap3_mvblx ARM ARMV7 (OMAP3xx SoC) - -Matthias Kaehlcke - edb9301 ARM920T (EP9301) - edb9302 ARM920T (EP9302) - edb9302a ARM920T (EP9302) - edb9307 ARM920T (EP9307) - edb9307a ARM920T (EP9307) - edb9312 ARM920T (EP9312) - edb9315 ARM920T (EP9315) - edb9315a ARM920T (EP9315) - -Nishant Kamat - - omap1610h2 ARM926EJS - -Minkyu Kang - - SMDKC100 ARM ARMV7 (S5PC100 SoC) - s5p_goni ARM ARMV7 (S5PC110 SoC) - s5pc210_universal ARM ARMV7 (EXYNOS4210 SoC) - -Chander Kashyap - - origen ARM ARMV7 (EXYNOS4210 SoC) - SMDKV310 ARM ARMV7 (EXYNOS4210 SoC) - SMDK5250 ARM ARMV7 (EXYNOS5250 SoC) - -Lukasz Majewski - - trats ARM ARMV7 (EXYNOS4210 SoC) - -Torsten Koschorrek - scb9328 ARM920T (i.MXL) - -Sergey Kubushyn - - DV-EVM ARM926EJS - SONATA ARM926EJS - SCHMOOGIE ARM926EJS - -Vipin Kumar - - spear300 ARM926EJS (spear300 Soc) - spear310 ARM926EJS (spear310 Soc) - spear320 ARM926EJS (spear320 Soc) - spear600 ARM926EJS (spear600 Soc) - -Sergey Lapin - - afeb9260 ARM926EJS (AT91SAM9260 SoC) - -Valentin Longchamp - - km_kirkwood ARM926EJS (Kirkwood SoC) - kmnusa ARM926EJS (Kirkwood SoC) - mgcoge3un ARM926EJS (Kirkwood SoC) - kmcoge5un ARM926EJS (Kirkwood SoC) - portl2 ARM926EJS (Kirkwood SoC) - -Nishanth Menon - - omap3_sdp3430 ARM ARMV7 (OMAP3xx SoC) - omap3_zoom1 ARM ARMV7 (OMAP3xx SoC) - -David Müller - - smdk2410 ARM920T - VCMA9 ARM920T - -Eric Millbrandt - - galaxy5200 mpc5200 - -Nagendra T S - - am3517_crane ARM ARMV7 (AM35x SoC) - -Dinh Nguyen -Chin Liang See - - socfpga socfpga_cyclone5 - -Sandeep Paulraj - - davinci_dm355evm ARM926EJS - davinci_dm355leopard ARM926EJS - davinci_dm365evm ARM926EJS - davinci_dm6467evm ARM926EJS - -Helmut Raiger - - tt01 i.MX31 - -Linus Walleij - integratorap various - integratorcp various - -Luka Perkov - - ib62x0 ARM926EJS - iconnect ARM926EJS - -Dave Peverley - - omap730p2 ARM926EJS - -Lars Poeschel - pcm051 ARM ARMV7 (AM33xx Soc) - -Mathieu Poirier - - snowball ARM ARMV7 (u8500 SoC) - -Stelian Pop - - at91sam9260ek ARM926EJS (AT91SAM9260 SoC) - at91sam9261ek ARM926EJS (AT91SAM9261 SoC) - at91sam9263ek ARM926EJS (AT91SAM9263 SoC) - at91sam9rlek ARM926EJS (AT91SAM9RL SoC) - -Matt Porter - - ti814x_evm ARM ARMV7 (TI814x Soc) - -Dave Purdy - - pogo_e02 ARM926EJS (Kirkwood SoC) - -Sricharan R - - omap4_panda ARM ARMV7 (OMAP4xx SoC) - omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC) - omap5_evm ARM ARMV7 (OMAP5xx Soc) - -Suriyan Ramasami - - goflexhome ARM926EJS (Kirkwood SoC) - -Thierry Reding - - plutux Tegra20 (ARM7 & A9 Dual Core) - medcom-wide Tegra20 (ARM7 & A9 Dual Core) - tec Tegra20 (ARM7 & A9 Dual Core) - -Christian Riesch -Manfred Rudigier - - calimain ARM926EJS (AM1808 SoC) - -Tom Rini - - am335x_evm ARM ARMV7 (AM33xx Soc) - omap3_beagle ARM ARMV7 (OMAP3xx SoC) - omap3_evm ARM ARMV7 (OMAP3xx SoC) - -Tom Rix - - omap3_zoom2 ARM ARMV7 (OMAP3xx SoC) - -John Rigby - - tx25 i.MX25 - -Stefan Roese - - x600 ARM926EJS (spear600 Soc) - - titanium i.MX6Q - - pdnb3 xscale/ixp - scpu xscale/ixp - -Alessandro Rubini -Nomadik Linux Team - - nhk8815 ARM926EJS (Nomadik 8815 Soc) - -Steve Sakoman - - omap3_overo ARM ARMV7 (OMAP3xx SoC) - -Leo Sartre - - cgtqmx6qeval i.MX6Q - -Jens Scharsig - - eb_cpux9k2 ARM920T (AT91RM9200 SoC) - vl_ma2sc ARM926EJS (AT91SAM9263 SoC) - -Heiko Schocher - - enbw_cmc ARM926EJS (AM1808 SoC) - magnesium i.MX27 - -Michael Schwingen - - actux1 xscale/ixp - actux2 xscale/ixp - actux3 xscale/ixp - actux4 xscale/ixp - dvlhost xscale/ixp - -Matt Sealey - - efikamx i.MX51 - efikasb i.MX51 - -Bo Shen - at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC) - sama5d3xek ARMV7 (SAMA5D31, D33, D34, D35 SoC) - -Rajeshwari Shinde - - snow ARM ARMV7 (EXYNOS5250 SoC) - -Michal Simek - - zynq ARM ARMV7 (Zynq SoC) - -Lucas Stach - - colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core) - -Nick Thompson - - da830evm ARM926EJS (DA830/OMAP-L137) - -Albin Tonnerre - - sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC) - tny_a9260 ARM926EJS (AT91SAM9260 SoC) - tny_a9g20 ARM926EJS (AT91SAM9G20 SoC) - -Greg Ungerer - - cm4008 ks8695p - cm4116 ks8695p - cm4148 ks8695p - -Marek Vasut - - balloon3 xscale/pxa - colibri_pxa270 xscale/pxa - palmld xscale/pxa - palmtc xscale/pxa - vpac270 xscale/pxa - zipitz2 xscale/pxa - mx23_olinuxino i.MX23 - m28evk i.MX28 - sc_sps_1 i.MX28 - m53evk i.MX53 - -Hugo Villeneuve - - SFFSDR ARM926EJS - -Lokesh Vutla - - dra7xx_evm ARM ARMV7 (DRA7xx Soc) - -Matt Waddel - - vexpress_ca9x4 ARM ARMV7 (Quad Core) - vexpress_ca5x2 ARM ARMV7 (Dual Core) - -Otavio Salvador - - mx23evk i.MX23 - -Prafulla Wadaskar - - aspenite ARM926EJS (ARMADA100 88AP168 SoC) - mv88f6281gtw_ge ARM926EJS (Kirkwood SoC) - openrd_base ARM926EJS (Kirkwood SoC) - rd6281a ARM926EJS (Kirkwood SoC) - sheevaplug ARM926EJS (Kirkwood SoC) - -Michael Walle - - lschlv2 ARM926EJS (Kirkwood SoC) - lsxhl ARM926EJS (Kirkwood SoC) - -Tom Warren - - harmony Tegra20 (ARM7 & A9 Dual Core) - seaboard Tegra20 (ARM7 & A9 Dual Core) - cardhu Tegra30 (ARM7 & A9 Quad Core) - dalmore Tegra114 (ARM7 & A15 Quad Core) - -Tom Warren -Stephen Warren - - ventana Tegra20 (ARM7 & A9 Dual Core) - paz00 Tegra20 (ARM7 & A9 Dual Core) - trimslice Tegra20 (ARM7 & A9 Dual Core) - whistler Tegra20 (ARM7 & A9 Dual Core) - beaver Tegra30 (ARM7 & A9 Quad Core) - -Stephen Warren - - rpi_b BCM2835 (ARM1176) - -Thomas Weber - - devkit8000 ARM ARMV7 (OMAP3530 SoC) - tricorder ARM ARMV7 (OMAP3503 SoC) - -Lei Wen - - dkb ARM926EJS (PANTHEON 88AP920 SOC) - -Matthias Weisser - - jadecpu ARM926EJS (MB86R01 SoC) - zmx25 ARM926EJS (imx25 SoC) - -Josh Wu - at91sam9n12ek ARM926EJS (AT91SAM9N12 SoC) - -Ilya Yanok - - mcx ARM ARMV7 (AM35x SoC) - -Syed Mohammed Khasim -Sughosh Ganu - - hawkboard ARM926EJS (OMAP-L138) - -Vladimir Zapolskiy - - devkit3250 lpc32xx - -Nobuhiro Iwamatsu -Tetsuyuki Kobayashi - - kzm9g SH73A0 (RMOBILE SoC) - -Nobuhiro Iwamatsu - - armadillo-800eva R8A7740 (RMOBILE SoC) - -Pali Rohár - - nokia_rx51 ARM ARMV7 (OMAP34xx SoC) - -Eric Nelson - nitrogen6dl i.MX6DL 1GB - nitrogen6dl2g i.MX6DL 2GB - nitrogen6q i.MX6Q/6D 1GB - nitrogen6q2g i.MX6Q/6D 2GB - nitrogen6s i.MX6S 512MB - nitrogen6s1g i.MX6S 1GB - -Alison Wang - - vf610twr VF610 - -Sergey Yanovich - - lp8x4x xscale/pxa - -------------------------------------------------------------------------- - -Unknown / orphaned boards: - Board CPU Last known maintainer / Comment -......................................................................... - - omap1510inn ARM925T Kshitij Gupta - - lubbock xscale/pxa Kyle Harris / dead address - - imx31_phycore_eet i.MX31 Guennadi Liakhovetski / resigned - mx31ads i.MX31 Guennadi Liakhovetski / resigned - -######################################################################### -# x86 Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Simon Glass - - chromebook-x86 Coreboot runs first, then U-Boot - Supports Intel Sandy Bridge / Ivy Bridge so far - - Chromebooks for x86, including: - Samsung Series 5 Chromebook - Acer AC700 Chromebook - Acer C7 Chromebook - Samsung Chromebook 550 - HP Pavillion Chromebook - Acer C710 Chromebook - Chromebook Pixel - -######################################################################### -# MIPS Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Wolfgang Denk - - incaip MIPS32 4Kc - -Vlad Lungu - qemu_mips MIPS32 - -Stefan Roese - - vct_xxx MIPS32 4Kc - -------------------------------------------------------------------------- - -Unknown / orphaned boards: - Board CPU Last known maintainer / Comment -......................................................................... - - dbau1x00 MIPS32 Au1000 Thomas Lange - -######################################################################### -# Nios-II Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Scott McNutt - - PCI5441 Nios-II - PK1C20 Nios-II - nios2-generic Nios-II - -######################################################################### -# MicroBlaze Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Michal Simek - - microblaze-generic MicroBlaze - -######################################################################### -# Coldfire Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Hayden Fraser - - M5253EVBE mcf52x2 - -Matthias Fuchs - - TASREG MCF5249 - -Jens Scharsig - - eb_cpu5282 mfc5282 - -TsiChung Liew - - M52277EVB mcf5227x - M5235EVB mcf52x2 - M5253DEMO mcf52x2 - M53017EVB mcf532x - M5329EVB mcf532x - M5373EVB mcf532x - M54455EVB mcf5445x - M5475EVB mcf547x_8x - M5485EVB mcf547x_8x - -Wolfgang Wegner - - astro_mcf5373l MCF5373L - -######################################################################### -# AVR32 Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Andreas Bießmann - grasshopper AT32AP7000 - atngw100mkii AT32AP7000 - -Hans-Christian Egtvedt - - FAVR-32-EZKIT AT32AP7000 - -Mark Jackson - - MIMC200 AT32AP7000 - -Alex Raimondi -Julien May - - HAMMERHEAD AT32AP7000 - -Haavard Skinnemoen - - ATSTK1000 AT32AP7xxx - ATSTK1002 AT32AP7000 - ATSTK1003 AT32AP7001 - ATSTK1004 AT32AP7002 - ATSTK1006 AT32AP7000 - ATNGW100 AT32AP7000 - -######################################################################### -# SuperH Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Yusuke Goda - - MIGO-R SH7722 - -Nobuhiro Iwamatsu - - - MS7750SE SH7750 - MS7722SE SH7722 - R7780MP SH7780 - R2DPlus SH7751R - SH7763RDP SH7763 - RSK7203 SH7203 - AP325RXA SH7723 - SHMIN SH7706 - ECOVEC SH7724 - R0P7734 SH7734 - AP_SH4A_4A SH7734 - -Mark Jonas - - mpr2 SH7720 - -Yoshihiro Shimoda - - MS7720SE SH7720 - R0P77520000RZ SH7752 - R0P77570030RL SH7757 - R0P77850011RL SH7785 - -######################################################################### -# Blackfin Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Sonic Zhang -Blackfin Team - - BF506F-EZKIT BF506 - BF518F-EZBRD BF518 - BF526-EZBRD BF526 - BF527-AD7160-EVAL BF527 - BF527-EZKIT BF527 - BF527-EZKIT-V2 BF527 - BF527-SDP BF527 - BF533-EZKIT BF533 - BF533-STAMP BF533 - BF537-PNAV BF537 - BF537-STAMP BF537 - BF538F-EZKIT BF538 - BF548-EZKIT BF548 - BF561-EZKIT BF561 - BF609-EZKIT BF609 - -M.Hasewinkel (MHA) - - dnp5370 BF537 - -Brent Kandetzki - - IP04 BF532 - -Peter Meerwald - - bct-brettl2 BF536 - -I-SYST Micromodule - - IBF-DSP561 BF561 - -Wojtek Skulski -Wojtek Skulski -Benjamin Matthews - - BlackStamp BF533 - BlackVME BF561 - -Martin Strubel - - BF537-minotaur BF537 - BF537-srv1 BF537 - -Bluetechnix Tinyboards - - CM-BF527 BF527 - CM-BF533 BF533 - CM-BF537E BF537 - CM-BF537U BF537 - CM-BF548 BF548 - CM-BF561 BF561 - TCM-BF518 BF518 - TCM-BF537 BF537 - -Valentin Yakovenkov -Anton Shurpin - - BF561-ACVILON BF561 - -Haitao Zhang -Chong Huang - - bf525-ucr2 BF525 - -Dimitar Penev - - BR4 Appliance BF537 - PR1 Appliance BF537 - -######################################################################### -# NDS32 Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Andes - - ADP-AG101 N1213 (AG101 SoC) - ADP-AG101P N1213 (AG101P XC5 FPGA) - ADP-AG102 N1213f (AG102 SoC with FPU) - -######################################################################### -# OpenRISC Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Stefan Kristiansson - - openrisc-generic OpenRISC - -######################################################################### -# Sandbox: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Simon Glass - - sandbox sandbox - -######################################################################### -# End of MAINTAINERS list # -######################################################################### +Descriptions of section entries: + + P: Person (obsolete) + M: Mail patches to: FullName + L: Mailing list that is relevant to this area + W: Web-page with status/info + Q: Patchwork web based patch tracking system site + T: SCM tree type and location. + Type is one of: git, hg, quilt, stgit, topgit + S: Status, one of the following: + Supported: Someone is actually paid to look after this. + Maintained: Someone actually looks after it. + Odd Fixes: It has a maintainer but they don't have time to do + much other than throw the odd patch in. See below.. + Orphan: No current maintainer [but maybe you could take the + role as you write your new code]. + Obsolete: Old code. Something tagged obsolete generally means + it has been replaced by a better system and you + should be using that. + F: Files and directories with wildcard patterns. + A trailing slash includes all files and subdirectory files. + F: drivers/net/ all files in and below drivers/net + F: drivers/net/* all files in drivers/net, but not below + F: */net/* all files in "any top level directory"/net + One pattern per line. Multiple F: lines acceptable. + N: Files and directories with regex patterns. + N: [^a-z]tegra all files whose path contains the word tegra + One pattern per line. Multiple N: lines acceptable. + scripts/get_maintainer.pl has different behavior for files that + match F: pattern and matches of N: patterns. By default, + get_maintainer will not look at git log history when an F: pattern + match occurs. When an N: match occurs, git log history is used + to also notify the people that have git commit signatures. + X: Files and directories that are NOT maintained, same rules as F: + Files exclusions are tested before file matches. + Can be useful for excluding a specific subdirectory, for instance: + F: net/ + X: net/ipv6/ + matches all files in and below net excluding net/ipv6/ + K: Keyword perl extended regex pattern to match content in a + patch or file. For instance: + K: of_get_profile + matches patches or files that contain "of_get_profile" + K: \b(printk|pr_(info|err))\b + matches patches or files that contain one or more of the words + printk, pr_info or pr_err + One regex pattern per line. Multiple K: lines acceptable. + +Note: For the hard of thinking, this list is meant to remain in alphabetical +order. If you could add yourselves to it in alphabetical order that would be +so much easier [Ed] + +Maintainers List (try to look for most precise areas first) + + ----------------------------------- +ARC +M: Alexey Brodkin +S: Maintained +T: git git://git.denx.de/u-boot-arc.git +F: arch/arc/ + +ARM +M: Albert Aribaud +S: Maintained +T: git git://git.denx.de/u-boot-arm.git +F: arch/arm/ + +ARM ALTERA SOCFPGA +M: Marek Vasut +S: Maintainted +T: git git://git.denx.de/u-boot-socfpga.git +F: arch/arm/cpu/armv7/socfpga/ +F: board/altera/socfpga/ + +ARM ATMEL AT91 +M: Andreas Bießmann +S: Maintained +T: git git://git.denx.de/u-boot-atmel.git +F: arch/arm/cpu/armv7/at91/ +F: arch/arm/cpu/at91-common/ +F: arch/arm/include/asm/arch-at91/ + +ARM FREESCALE IMX +M: Stefano Babic +S: Maintained +T: git git://git.denx.de/u-boot-imx.git +F: arch/arm/cpu/arm1136/mx*/ +F: arch/arm/cpu/arm926ejs/mx*/ +F: arch/arm/cpu/arm926ejs/imx/ +F: arch/arm/cpu/armv7/mx*/ +F: arch/arm/cpu/armv7/vf610/ +F: arch/arm/cpu/imx-common/ +F: arch/arm/include/asm/arch-imx/ +F: arch/arm/include/asm/arch-mx*/ +F: arch/arm/include/asm/arch-vf610/ +F: arch/arm/include/asm/imx-common/ + +ARM MARVELL KIRKWOOD +M: Prafulla Wadaskar +M: Luka Perkov +S: Maintained +T: git git://git.denx.de/u-boot-marvell.git +F: arch/arm/cpu/arm926ejs/kirkwood/ +F: arch/arm/include/asm/arch-kirkwood/ + +ARM MARVELL PXA +M: Marek Vasut +S: Maintained +T: git git://git.denx.de/u-boot-pxa.git +F: arch/arm/cpu/pxa/ +F: arch/arm/include/asm/arch-pxa/ + +ARM SAMSUNG +M: Minkyu Kang +S: Maintained +T: git git://git.denx.de/u-boot-samsung.git +F: arch/arm/cpu/arm920t/s3c24x0/ +F: arch/arm/cpu/armv7/exynos/ +F: arch/arm/cpu/armv7/s5pc1xx/ +F: arch/arm/cpu/armv7/s5p-common/ +F: arch/arm/include/asm/arch-exynos/ +F: arch/arm/include/asm/arch-s3c24x0/ +F: arch/arm/include/asm/arch-s5pc1xx/ + +ARM STM SPEAR +M: Vipin Kumar +S: Maintained +T: git git://git.denx.de/u-boot-stm.git +F: arch/arm/cpu/arm926ejs/spear/ +F: arch/arm/include/asm/arch-spear/ + +ARM STM STV0991 +M: Vikas Manocha +S: Maintained +F: arch/arm/cpu/armv7/stv0991/ +F: arch/arm/include/asm/arch-stv0991/ + +ARM SUNXI +M: Ian Campbell +M: Hans De Goede +S: Maintained +T: git git://git.denx.de/u-boot-sunxi.git +F: arch/arm/cpu/armv7/sunxi/ +F: arch/arm/include/asm/arch-sunxi/ + +ARM TEGRA +M: Tom Warren +S: Maintained +T: git git://git.denx.de/u-boot-tegra.git +F: arch/arm/cpu/arm720t/tegra*/ +F: arch/arm/cpu/armv7/tegra*/ +F: arch/arm/cpu/tegra*/ +F: arch/arm/include/asm/arch-tegra*/ + +ARM TI +M: Tom Rini +S: Maintained +T: git git://git.denx.de/u-boot-ti.git +F: arch/arm/cpu/arm926ejs/davinci/ +F: arch/arm/cpu/arm926ejs/omap/ +F: arch/arm/cpu/armv7/omap*/ +F: arch/arm/include/asm/arch-davinci/ +F: arch/arm/include/asm/arch-omap*/ +F: arch/arm/include/asm/ti-common/ + +ARM UNIPHIER +M: Masahiro Yamada +S: Maintained +T: git git://git.denx.de/u-boot-uniphier.git +F: arch/arm/cpu/armv7/uniphier/ +F: arch/arm/include/asm/arch-uniphier/ +F: configs/ph1_*_defconfig +F: drivers/serial/serial_uniphier.c + +ARM ZYNQ +M: Michal Simek +S: Maintained +F: arch/arm/cpu/armv7/zynq/ +F: arch/arm/include/asm/arch-zynq/ + +AVR32 +M: Andreas Bießmann +S: Maintained +T: git git://git.denx.de/u-boot-avr32.git +F: arch/avr32/ + +BLACKFIN +M: Sonic Zhang +S: Maintained +T: git git://git.denx.de/u-boot-blackfin.git +F: arch/blackfin/ + +BUILDMAN +M: Simon Glass +S: Maintained +F: tools/buildman/ + +CFI FLASH +M: Stefan Roese +S: Maintained +T: git git://git.denx.de/u-boot-cfi-flash.git +F: drivers/mtd/cfi_flash.c +F: drivers/mtd/jedec_flash.c + +COLDFIRE +M: Huan Wang +M: Angelo Dureghello +S: Maintained +T: git git://git.denx.de/u-boot-coldfire.git +F: arch/m68k/ + +DFU +M: Lukasz Majewski +S: Maintained +T: git git://git.denx.de/u-boot-dfu.git +F: drivers/dfu/ + +DRIVER MODEL +M: Simon Glass +S: Maintained +F: drivers/core/ +F: include/dm/ +F: test/dm/ + +FLATTENED DEVICE TREE +M: Simon Glass +S: Maintained +T: git git://git.denx.de/u-boot-fdt.git +F: lib/fdtdec* +F: lib/libfdt/ +F: include/fdt* +F: include/libfdt* +F. common/cmd_fdt.c +F: common/fdt_support.c + +FREEBSD +M: Rafal Jaworowski +S: Maintained +T: git git://git.denx.de/u-boot-freebsd.git + +FREESCALE QORIQ +M: York Sun +S: Maintained +T: git git://git.denx.de/u-boot-fsl-qoriq.git + +I2C +M: Heiko Schocher +S: Maintained +T: git git://git.denx.de/u-boot-i2c.git +F: drivers/i2c/ + +MICROBLAZE +M: Michal Simek +S: Maintained +T: git git://git.denx.de/u-boot-microblaze.git +F: arch/microblaze/ + +MIPS +M: Daniel Schwierzeck +S: Maintained +T: git git://git.denx.de/u-boot-mips.git +F: arch/mips/ + +MMC +M: Pantelis Antoniou +S: Maintained +T: git git://git.denx.de/u-boot-mmc.git +F: drivers/mmc/ + +OPENRISC +M: Stefan Kristiansson +S: Maintained +F: arch/openrisc/ + +PATMAN +M: Simon Glass +S: Maintained +F: tools/patman/ + +POWERPC +M: Wolfgang Denk +S: Maintained +F: arch/powerpc/ + +POWERPC MPC5XXX +M: Wolfgang Denk +S: Maintained +T: git git://git.denx.de/u-boot-mpc5xxx.git +F: arch/powerpc/cpu/mpc5*/ + +POWERPC MPC8XX +M: Wolfgang Denk +S: Maintained +T: git git://git.denx.de/u-boot-mpc8xx.git +F: arch/powerpc/cpu/mpc8xx/ + +POWERPC MPC82XX +M: Wolfgang Denk +S: Maintained +T: git git://git.denx.de/u-boot-mpc82xx.git +F: arch/powerpc/cpu/mpc82*/ + +POWERPC MPC83XX +M: Kim Phillips +S: Maintained +T: git git://git.denx.de/u-boot-mpc83xx.git +F: arch/powerpc/cpu/mpc83xx/ +F: arch/powerpc/include/asm/arch-mpc83xx/ + +POWERPC MPC85XX +M: York Sun +S: Maintained +T: git git://git.denx.de/u-boot-mpc85xx.git +F: arch/powerpc/cpu/mpc85xx/ + +POWERPC MPC86XX +M: York Sun +S: Maintained +T: git git://git.denx.de/u-boot-mpc86xx.git +F: arch/powerpc/cpu/mpc86xx/ + +POWERPC PPC4XX +M: Stefan Roese +S: Maintained +T: git git://git.denx.de/u-boot-ppc4xx.git +F: arch/powerpc/cpu/ppc4xx/ + +NETWORK +M: Joe Hershberger +S: Maintained +T: git git://git.denx.de/u-boot-net.git +F: drivers/net/ + +NAND FLASH +M: Scott Wood +S: Maintained +T: git git://git.denx.de/u-boot-nand-flash.git +F: drivers/mtd/nand/ + +NDS32 +M: Macpaul Lin +S: Maintained +T: git git://git.denx.de/u-boot-nds32.git +F: arch/nds32/ + +NIOS +M: Thomas Chou +S: Maintained +T: git git://git.denx.de/u-boot-nios.git +F: arch/nios2/ + +ONENAND +M: Lukasz Majewski +S: Maintained +T: git git://git.denx.de/u-boot-onenand.git +F: drivers/mtd/onenand/ + +SANDBOX +M: Simon Glass +S: Maintained +F: arch/sandbox/ + +SH +M: Nobuhiro Iwamatsu +S: Maintained +T: git git://git.denx.de/u-boot-sh.git +F: arch/sh/ + +SPARC +M: Daniel Hellstrom +S: Maintained +T: git git://git.denx.de/u-boot-sparc.git +F: arch/sparc/ + +SPI +M: Jagannadha Sutradharudu Teki +S: Maintained +T: git git://git.denx.de/u-boot-spi.git +F: drivers/mtd/spi/ +F: drivers/spi/ +F: include/spi* + +TESTING +M: Detlev Zundel +S: Maintained +T: git git://git.denx.de/u-boot-testing.git + +TQ GROUP +M: Martin Krause +S: Maintained +T: git git://git.denx.de/u-boot-tq-group.git + +UBI +M: Kyungmin Park +M: Heiko Schocher +S: Maintained +T: git git://git.denx.de/u-boot-ubi.git +F: drivers/mtd/ubi/ + +USB +M: Marek Vasut +S: Maintained +T: git git://git.denx.de/u-boot-usb.git +F: drivers/usb/ + +VIDEO +M: Anatolij Gustschin +S: Maintained +T: git git://git.denx.de/u-boot-video.git +F: drivers/video/ + +X86 +M: Simon Glass +S: Maintained +T: git git://git.denx.de/u-boot-x86.git +F: arch/x86/ + +THE REST +M: Tom Rini +L: u-boot@lists.denx.de +Q: http://patchwork.ozlabs.org/project/uboot/list/ +S: Maintained +T: git git://git.denx.de/u-boot.git +F: * +F: */ diff --git a/MAKEALL b/MAKEALL index bed99dea05..c5f665f4d1 100755 --- a/MAKEALL +++ b/MAKEALL @@ -18,6 +18,7 @@ usage() -c CPU, --cpu CPU Build all boards with cpu CPU -v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR -s SOC, --soc SOC Build all boards with soc SOC + -b BOARD, --board BOARD Build all boards with board name BOARD -l, --list List all targets to be built -m, --maintainers List all targets and maintainer email -M, --mails List all targets and all affilated emails @@ -38,8 +39,8 @@ usage() BUILD_NCPUS number of parallel make jobs (default: auto) CROSS_COMPILE cross-compiler toolchain prefix (default: "") CROSS_COMPILE_ cross-compiler toolchain prefix for - architecture "ARCH". Substitute "ARCH" for any - supported architecture (default: "") + architecture "ARCH". Substitute "ARCH" for any + supported architecture (default: "") MAKEALL_LOGDIR output all logs to here (default: ./LOG/) BUILD_DIR output build directory (default: ./) BUILD_NBUILDS number of parallel targets (default: 1) @@ -59,8 +60,8 @@ usage() exit ${ret} } -SHORT_OPTS="ha:c:v:s:lmMCnr" -LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check,continue,rebuild-errors" +SHORT_OPTS="ha:c:v:s:b:lmMCnr" +LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors" # Option processing based on util-linux-2.13/getopt-parse.bash @@ -106,9 +107,9 @@ while true ; do -s|--soc) # echo "Option SoC: argument \`$2'" if [ "$opt_s" ] ; then - opt_s="${opt_s%)} || \$6 == \"$2\" || \$6 ~ /$2/)" + opt_s="${opt_s%)} || \$4 == \"$2\" || \$4 ~ /$2/)" else - opt_s="(\$6 == \"$2\" || \$6 ~ /$2/)" + opt_s="(\$4 == \"$2\" || \$4 ~ /$2/)" fi SELECTED='y' shift 2 ;; @@ -121,6 +122,17 @@ while true ; do fi SELECTED='y' shift 2 ;; + -b|--board) + # echo "Option BOARD: argument \`$2'" + if [ "$opt_b" ] ; then + opt_b="${opt_b%)} || \$6 == \"$2\" || \$7 == \"$2\")" + else + # We need to check the 7th field too + # for boards whose 6th field is "-" + opt_b="(\$6 == \"$2\" || \$7 == \"$2\")" + fi + SELECTED='y' + shift 2 ;; -C|--check) CHECK='C=1' shift ;; @@ -150,17 +162,29 @@ while true ; do echo "Internal error!" >&2 ; exit 1 ;; esac done + +GNU_MAKE=$(scripts/show-gnu-make) || { + echo "GNU Make not found" >&2 + exit 1 +} + # echo "Remaining arguments:" # for arg do echo '--> '"\`$arg'" ; done +tools/genboardscfg.py || { + echo "Failed to generate boards.cfg" >&2 + exit 1 +} + FILTER="\$1 !~ /^#/" [ "$opt_a" ] && FILTER="${FILTER} && $opt_a" [ "$opt_c" ] && FILTER="${FILTER} && $opt_c" [ "$opt_s" ] && FILTER="${FILTER} && $opt_s" [ "$opt_v" ] && FILTER="${FILTER} && $opt_v" +[ "$opt_b" ] && FILTER="${FILTER} && $opt_b" if [ "$SELECTED" ] ; then - SELECTED=$(awk '('"$FILTER"') { print $1 }' boards.cfg) + SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg) # Make sure some boards from boards.cfg are actually found if [ -z "$SELECTED" ] ; then @@ -224,86 +248,72 @@ OLDEST_IDX=1 RC=0 # Helper funcs for parsing boards.cfg -boards_by_field() +targets_by_field() { - FS="[ \t]+" - [ -n "$3" ] && FS="$3" - awk \ - -v field="$1" \ - -v select="$2" \ - -F "$FS" \ - '($1 !~ /^#/ && $field == select) { print $1 }' \ - boards.cfg + field=$1 + regexp=$2 + + awk '($1 !~ /^#/ && $'"$field"' ~ /^'"$regexp"'$/) { print $7 }' \ + boards.cfg } -boards_by_arch() { boards_by_field 2 "$@" ; } -boards_by_cpu() { boards_by_field 3 "$@" "[: \t]+" ; } -boards_by_soc() { boards_by_field 6 "$@" ; } + +targets_by_arch() { targets_by_field 2 "$@" ; } +targets_by_cpu() { targets_by_field 3 "$@" ; targets_by_field 3 "$@:.*" ; } +targets_by_soc() { targets_by_field 4 "$@" ; } ######################################################################### ## MPC5xx Systems ######################################################################### -LIST_5xx="$(boards_by_cpu mpc5xx)" +LIST_5xx="$(targets_by_cpu mpc5xx)" ######################################################################### ## MPC5xxx Systems ######################################################################### -LIST_5xxx="$(boards_by_cpu mpc5xxx)" +LIST_5xxx="$(targets_by_cpu mpc5xxx)" ######################################################################### ## MPC512x Systems ######################################################################### -LIST_512x="$(boards_by_cpu mpc512x)" +LIST_512x="$(targets_by_cpu mpc512x)" ######################################################################### ## MPC8xx Systems ######################################################################### -LIST_8xx="$(boards_by_cpu mpc8xx)" +LIST_8xx="$(targets_by_cpu mpc8xx)" ######################################################################### ## PPC4xx Systems ######################################################################### -LIST_4xx="$(boards_by_cpu ppc4xx)" - -######################################################################### -## MPC824x Systems -######################################################################### - -LIST_824x="$(boards_by_cpu mpc824x)" +LIST_4xx="$(targets_by_cpu ppc4xx)" ######################################################################### ## MPC8260 Systems (includes 8250, 8255 etc.) ######################################################################### -LIST_8260="$(boards_by_cpu mpc8260)" +LIST_8260="$(targets_by_cpu mpc8260)" ######################################################################### ## MPC83xx Systems (includes 8349, etc.) ######################################################################### -LIST_83xx="$(boards_by_cpu mpc83xx)" +LIST_83xx="$(targets_by_cpu mpc83xx)" ######################################################################### ## MPC85xx Systems (includes 8540, 8560 etc.) ######################################################################### -LIST_85xx="$(boards_by_cpu mpc85xx)" +LIST_85xx="$(targets_by_cpu mpc85xx)" ######################################################################### ## MPC86xx Systems ######################################################################### -LIST_86xx="$(boards_by_cpu mpc86xx)" - -######################################################################### -## 74xx/7xx Systems -######################################################################### - -LIST_74xx_7xx="$(boards_by_cpu 74xx_7xx)" +LIST_86xx="$(targets_by_cpu mpc86xx)" ######################################################################### ## PowerPC groups @@ -326,7 +336,6 @@ LIST_powerpc=" \ ${LIST_85xx} \ ${LIST_86xx} \ ${LIST_4xx} \ - ${LIST_74xx_7xx}\ " # Alias "ppc" -> "powerpc" to not break compatibility with older scripts @@ -339,175 +348,146 @@ LIST_ppc=" \ ## StrongARM Systems ######################################################################### -LIST_SA="$(boards_by_cpu sa1100)" +LIST_SA="$(targets_by_cpu sa1100)" ######################################################################### ## ARM7 Systems ######################################################################### -LIST_ARM7="$(boards_by_cpu arm720t)" +LIST_ARM7="$(targets_by_cpu arm720t)" ######################################################################### ## ARM9 Systems ######################################################################### -LIST_ARM9="$(boards_by_cpu arm920t) \ - $(boards_by_cpu arm926ejs) \ - $(boards_by_cpu arm925t) \ - $(boards_by_cpu arm946es) \ +LIST_ARM9="$(targets_by_cpu arm920t) \ + $(targets_by_cpu arm926ejs) \ + $(targets_by_cpu arm946es) \ " ######################################################################### ## ARM11 Systems ######################################################################### -LIST_ARM11="$(boards_by_cpu arm1136) \ - $(boards_by_cpu arm1176) \ +LIST_ARM11="$(targets_by_cpu arm1136) \ + $(targets_by_cpu arm1176) \ " ######################################################################### ## ARMV7 Systems ######################################################################### -LIST_ARMV7="$(boards_by_cpu armv7)" +LIST_ARMV7="$(targets_by_cpu armv7)" + +######################################################################### +## ARMV8 Systems +######################################################################### + +LIST_ARMV8="$(targets_by_cpu armv8)" ######################################################################### ## AT91 Systems ######################################################################### -LIST_at91="$(boards_by_soc at91)" +LIST_at91="$(targets_by_soc at91)" ######################################################################### ## Xscale Systems ######################################################################### -LIST_pxa="$(boards_by_cpu pxa)" - -LIST_ixp="$(boards_by_cpu ixp)" +LIST_pxa="$(targets_by_cpu pxa)" ######################################################################### ## SPEAr Systems ######################################################################### -LIST_spear="$(boards_by_soc spear)" +LIST_spear="$(targets_by_soc spear)" ######################################################################### ## ARM groups ######################################################################### -LIST_arm="$(boards_by_arch arm)" +LIST_arm="$(targets_by_arch arm | \ + for ARMV8_TARGET in $LIST_ARMV8; \ + do sed "/$ARMV8_TARGET/d"; \ + done) \ +" ######################################################################### ## MIPS Systems (default = big endian) ######################################################################### -LIST_mips4kc=" \ - incaip \ - incaip_100MHz \ - incaip_133MHz \ - incaip_150MHz \ - qemu_mips \ - vct_platinum \ - vct_platinum_small \ - vct_platinum_onenand \ - vct_platinum_onenand_small \ - vct_platinumavc \ - vct_platinumavc_small \ - vct_platinumavc_onenand \ - vct_platinumavc_onenand_small \ - vct_premium \ - vct_premium_small \ - vct_premium_onenand \ - vct_premium_onenand_small \ -" - -LIST_au1xx0=" \ - dbau1000 \ - dbau1100 \ - dbau1500 \ - dbau1550 \ -" - -LIST_mips=" \ - ${LIST_mips4kc} \ - ${LIST_mips5kc} \ - ${LIST_au1xx0} \ -" - -######################################################################### -## MIPS Systems (little endian) -######################################################################### +LIST_mips="$(targets_by_arch mips)" -LIST_au1xx0_el=" \ - dbau1550_el \ - pb1000 \ -" -LIST_mips_el=" \ - ${LIST_au1xx0_el} \ -" ######################################################################### ## OpenRISC Systems ######################################################################### -LIST_openrisc="$(boards_by_arch openrisc)" +LIST_openrisc="$(targets_by_arch openrisc)" ######################################################################### ## x86 Systems ######################################################################### -LIST_x86="$(boards_by_arch x86)" +LIST_x86="$(targets_by_arch x86)" ######################################################################### ## Nios-II Systems ######################################################################### -LIST_nios2="$(boards_by_arch nios2)" +LIST_nios2="$(targets_by_arch nios2)" ######################################################################### ## MicroBlaze Systems ######################################################################### -LIST_microblaze="$(boards_by_arch microblaze)" +LIST_microblaze="$(targets_by_arch microblaze)" ######################################################################### ## ColdFire Systems ######################################################################### -LIST_m68k="$(boards_by_arch m68k)" +LIST_m68k="$(targets_by_arch m68k)" LIST_coldfire=${LIST_m68k} ######################################################################### ## AVR32 Systems ######################################################################### -LIST_avr32="$(boards_by_arch avr32)" +LIST_avr32="$(targets_by_arch avr32)" ######################################################################### ## Blackfin Systems ######################################################################### -LIST_blackfin="$(boards_by_arch blackfin)" +LIST_blackfin="$(targets_by_arch blackfin)" ######################################################################### ## SH Systems ######################################################################### -LIST_sh2="$(boards_by_cpu sh2)" -LIST_sh3="$(boards_by_cpu sh3)" -LIST_sh4="$(boards_by_cpu sh4)" +LIST_sh2="$(targets_by_cpu sh2)" +LIST_sh3="$(targets_by_cpu sh3)" +LIST_sh4="$(targets_by_cpu sh4)" -LIST_sh="$(boards_by_arch sh)" +LIST_sh="$(targets_by_arch sh)" ######################################################################### ## SPARC Systems ######################################################################### -LIST_sparc="$(boards_by_arch sparc)" +LIST_sparc="$(targets_by_arch sparc)" ######################################################################### ## NDS32 Systems ######################################################################### -LIST_nds32="$(boards_by_arch nds32)" +LIST_nds32="$(targets_by_arch nds32)" + +######################################################################### +## ARC Systems +######################################################################### + +LIST_arc="$(targets_by_arch arc)" #----------------------------------------------------------------------- @@ -519,63 +499,60 @@ get_target_location() { local vendor="" # Automatic mode - local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg` - + local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg` if [ -z "${line}" ] ; then echo "" ; return ; fi set ${line} - # add default board name if needed - [ $# = 3 ] && set ${line} ${1} - - CONFIG_NAME="${1%_config}" + CONFIG_NAME="${7%_defconfig}" - [ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}" + [ "${BOARD_NAME}" ] || BOARD_NAME="${7%_defconfig}" - if [ "$4" = "-" ] ; then - board=${BOARD_NAME} - else - board="$4" + if [ $# -gt 5 ]; then + if [ "$6" = "-" ] ; then + board=${BOARD_NAME} + else + board="$6" + fi fi [ $# -gt 4 ] && [ "$5" != "-" ] && vendor="$5" - [ $# -gt 6 ] && [ "$7" != "-" ] && { - tmp="${7%:*}" + [ $# -gt 6 ] && [ "$8" != "-" ] && { + tmp="${8%:*}" if [ "$tmp" ] ; then CONFIG_NAME="$tmp" fi } # Assign board directory to BOARDIR variable - if [ -z "${vendor}" ] ; then + if [ "${vendor}" == "-" ] ; then BOARDDIR=${board} else BOARDDIR=${vendor}/${board} fi - echo "${CONFIG_NAME}:${BOARDDIR}" + echo "${CONFIG_NAME}:${BOARDDIR}:${BOARD_NAME}" } get_target_maintainers() { - local name=`echo $1 | cut -d : -f 1` + local name=`echo $1 | cut -d : -f 3` - if ! grep -qsi "[[:blank:]]${name}[[:blank:]]" MAINTAINERS ; then + local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg` + if [ -z "${line}" ]; then echo "" return ; fi - local line=`tac MAINTAINERS | grep -ni "[[:blank:]]${name}[[:blank:]]" | cut -d : -f 1` - local mail=`tac MAINTAINERS | tail -n +${line} | \ - sed -n ":start /.*@.*/ { b mail } ; n ; b start ; :mail /.*@.*/ { p ; n ; b mail } ; q" | \ - sed "s/^.*.*$//"` - echo "$mail" + local mails=`echo ${line} | cut -d ' ' -f 9- | sed -e 's/[^<]*.*[^>]*$//'` + [ "$mails" == "-" ] && mails="" + echo "$mails" } get_target_arch() { local target=$1 # Automatic mode - local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg` + local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg` if [ -z "${line}" ] ; then echo "" ; return ; fi @@ -651,20 +628,24 @@ build_target() { output_dir="${OUTPUT_PREFIX}" fi - export BUILD_DIR="${output_dir}" - target_arch=$(get_target_arch ${target}) eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'` if [ "${cross_toolchain}" ] ; then - MAKE="make CROSS_COMPILE=${cross_toolchain}" + MAKE="$GNU_MAKE CROSS_COMPILE=${cross_toolchain}" elif [ "${CROSS_COMPILE}" ] ; then - MAKE="make CROSS_COMPILE=${CROSS_COMPILE}" + MAKE="$GNU_MAKE CROSS_COMPILE=${CROSS_COMPILE}" else - MAKE=make + MAKE=$GNU_MAKE fi - ${MAKE} distclean >/dev/null - ${MAKE} -s ${target}_config + if [ "${output_dir}" != "." ] ; then + MAKE="${MAKE} O=${output_dir}" + fi + + ${MAKE} mrproper >/dev/null + + echo "Building ${target} board..." + ${MAKE} -s ${target}_defconfig >/dev/null ${MAKE} ${JOBS} ${CHECK} all \ >${LOG_DIR}/$target.MAKELOG 2> ${LOG_DIR}/$target.ERR @@ -677,7 +658,7 @@ build_target() { if [ $BUILD_MANY == 1 ] ; then trap - TERM - ${MAKE} -s tidy + ${MAKE} -s clean if [ -s ${LOG_DIR}/${target}.ERR ] ; then cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target} diff --git a/Makefile b/Makefile index 261bde92ef..d8b73076a4 100644 --- a/Makefile +++ b/Makefile @@ -1,19 +1,223 @@ +VERSION = 2015 +PATCHLEVEL = 04 +SUBLEVEL = +EXTRAVERSION = -rc1 +NAME = + +# *DOCUMENTATION* +# To see a list of typical targets execute "make help" +# More info can be located in ./README +# Comments in this file are targeted only to the developer, do not +# expect to learn how to build the kernel reading this file. + +# Do not use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour); +MAKEFLAGS += -rR + +# Avoid funny character set dependencies +unexport LC_ALL +LC_COLLATE=C +LC_NUMERIC=C +export LC_COLLATE LC_NUMERIC + +# Avoid interference with shell env settings +unexport GREP_OPTIONS + +# We are using a recursive build, so we need to do a little thinking +# to get the ordering right. +# +# Most importantly: sub-Makefiles should only ever modify files in +# their own directory. If in some directory we have a dependency on +# a file in another dir (which doesn't happen often, but it's often +# unavoidable when linking the built-in.o targets which finally +# turn into vmlinux), we will call a sub make in that other dir, and +# after that we are sure that everything which is in that other dir +# is now up to date. +# +# The only cases where we need to modify files which have global +# effects are thus separated out and done before the recursive +# descending is started. They are now explicitly listed as the +# prepare rule. + +# Beautify output +# --------------------------------------------------------------------------- +# +# Normally, we echo the whole command before executing it. By making +# that echo $($(quiet)$(cmd)), we now have the possibility to set +# $(quiet) to choose other forms of output instead, e.g. +# +# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@ +# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< +# +# If $(quiet) is empty, the whole command will be printed. +# If it is set to "quiet_", only the short version will be printed. +# If it is set to "silent_", nothing will be printed at all, since +# the variable $(silent_cmd_cc_o_c) doesn't exist. +# +# A simple variant is to prefix commands with $(Q) - that's useful +# for commands that shall be hidden in non-verbose mode. # -# (C) Copyright 2000-2013 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# $(Q)ln $@ :< # -# SPDX-License-Identifier: GPL-2.0+ +# If KBUILD_VERBOSE equals 0 then the above command will be hidden. +# If KBUILD_VERBOSE equals 1 then the above command is displayed. # +# To put more focus on warnings, be less verbose as default +# Use 'make V=1' to see the full commands -VERSION = 2013 -PATCHLEVEL = 07 -SUBLEVEL = -EXTRAVERSION = -ifneq "$(SUBLEVEL)" "" -U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) +ifeq ("$(origin V)", "command line") + KBUILD_VERBOSE = $(V) +endif +ifndef KBUILD_VERBOSE + KBUILD_VERBOSE = 0 +endif + +ifeq ($(KBUILD_VERBOSE),1) + quiet = + Q = +else + quiet=quiet_ + Q = @ +endif + +# If the user is running make -s (silent mode), suppress echoing of +# commands + +ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4 +ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),) + quiet=silent_ +endif +else # make-3.8x +ifneq ($(filter s% -s%,$(MAKEFLAGS)),) + quiet=silent_ +endif +endif + +export quiet Q KBUILD_VERBOSE + +# kbuild supports saving output files in a separate directory. +# To locate output files in a separate directory two syntaxes are supported. +# In both cases the working directory must be the root of the kernel src. +# 1) O= +# Use "make O=dir/to/store/output/files/" +# +# 2) Set KBUILD_OUTPUT +# Set the environment variable KBUILD_OUTPUT to point to the directory +# where the output files shall be placed. +# export KBUILD_OUTPUT=dir/to/store/output/files/ +# make +# +# The O= assignment takes precedence over the KBUILD_OUTPUT environment +# variable. + +# KBUILD_SRC is set on invocation of make in OBJ directory +# KBUILD_SRC is not intended to be used by the regular user (for now) +ifeq ($(KBUILD_SRC),) + +# OK, Make called in directory where kernel src resides +# Do we want to locate output files in a separate directory? +ifeq ("$(origin O)", "command line") + KBUILD_OUTPUT := $(O) +endif + +# That's our default target when none is given on the command line +PHONY := _all +_all: + +# Cancel implicit rules on top Makefile +$(CURDIR)/Makefile Makefile: ; + +ifneq ($(KBUILD_OUTPUT),) +# Invoke a second make in the output directory, passing relevant variables +# check that the output directory actually exists +saved-output := $(KBUILD_OUTPUT) +KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \ + && /bin/pwd) +$(if $(KBUILD_OUTPUT),, \ + $(error failed to create output directory "$(saved-output)")) + +PHONY += $(MAKECMDGOALS) sub-make + +$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make + @: + +sub-make: FORCE + $(Q)$(MAKE) -C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR) \ + -f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS)) + +# Leave processing to above invocation of make +skip-makefile := 1 +endif # ifneq ($(KBUILD_OUTPUT),) +endif # ifeq ($(KBUILD_SRC),) + +# We process the rest of the Makefile if this is the final invocation of make +ifeq ($(skip-makefile),) + +# Do not print "Entering directory ...", +# but we want to display it when entering to the output directory +# so that IDEs/editors are able to understand relative filenames. +MAKEFLAGS += --no-print-directory + +# Call a source code checker (by default, "sparse") as part of the +# C compilation. +# +# Use 'make C=1' to enable checking of only re-compiled files. +# Use 'make C=2' to enable checking of *all* source files, regardless +# of whether they are re-compiled or not. +# +# See the file "Documentation/sparse.txt" for more details, including +# where to get the "sparse" utility. + +ifeq ("$(origin C)", "command line") + KBUILD_CHECKSRC = $(C) +endif +ifndef KBUILD_CHECKSRC + KBUILD_CHECKSRC = 0 +endif + +# Use make M=dir to specify directory of external module to build +# Old syntax make ... SUBDIRS=$PWD is still supported +# Setting the environment variable KBUILD_EXTMOD take precedence +ifdef SUBDIRS + KBUILD_EXTMOD ?= $(SUBDIRS) +endif + +ifeq ("$(origin M)", "command line") + KBUILD_EXTMOD := $(M) +endif + +# If building an external module we do not care about the all: rule +# but instead _all depend on modules +PHONY += all +ifeq ($(KBUILD_EXTMOD),) +_all: all +else +_all: modules +endif + +ifeq ($(KBUILD_SRC),) + # building in the source tree + srctree := . else -U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION) + ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR))) + # building in a subdirectory of the source tree + srctree := .. + else + srctree := $(KBUILD_SRC) + endif endif +objtree := . +src := $(srctree) +obj := $(objtree) + +VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD)) + +export srctree objtree VPATH + +# Make sure CDPATH settings don't interfere +unexport CDPATH + +######################################################################### HOSTARCH := $(shell uname -m | \ sed -e s/i.86/x86/ \ @@ -30,350 +234,450 @@ HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \ export HOSTARCH HOSTOS -# Deal with colliding definitions from tcsh etc. -VENDOR= - ######################################################################### -# Allow for silent builds -ifeq (,$(findstring s,$(MAKEFLAGS))) -XECHO = echo -else -XECHO = : + +# set default to nothing for native builds +ifeq ($(HOSTARCH),$(ARCH)) +CROSS_COMPILE ?= endif -######################################################################### -# -# U-boot build supports producing a object files to the separate external -# directory. Two use cases are supported: -# -# 1) Add O= to the make command line -# 'make O=/tmp/build all' -# -# 2) Set environement variable BUILD_DIR to point to the desired location -# 'export BUILD_DIR=/tmp/build' -# 'make' -# -# The second approach can also be used with a MAKEALL script -# 'export BUILD_DIR=/tmp/build' -# './MAKEALL' -# -# Command line 'O=' setting overrides BUILD_DIR environent variable. -# -# When none of the above methods is used the local build is performed and -# the object files are placed in the source directory. -# +KCONFIG_CONFIG ?= .config +export KCONFIG_CONFIG -ifdef O -ifeq ("$(origin O)", "command line") -BUILD_DIR := $(O) -endif +# SHELL used by kbuild +CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) + +HOSTCC = cc +HOSTCXX = c++ +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer +HOSTCXXFLAGS = -O2 + +ifeq ($(HOSTOS),cygwin) +HOSTCFLAGS += -ansi endif -# Call a source code checker (by default, "sparse") as part of the -# C compilation. +# Mac OS X / Darwin's C preprocessor is Apple specific. It +# generates numerous errors and warnings. We want to bypass it +# and use GNU C's cpp. To do this we pass the -traditional-cpp +# option to the compiler. Note that the -traditional-cpp flag +# DOES NOT have the same semantics as GNU C's flag, all it does +# is invoke the GNU preprocessor in stock ANSI/ISO C fashion. # -# Use 'make C=1' to enable checking of re-compiled files. +# Apple's linker is similar, thanks to the new 2 stage linking +# multiple symbol definitions are treated as errors, hence the +# -multiply_defined suppress option to turn off this error. # -# See the linux kernel file "Documentation/sparse.txt" for more details, -# including where to get the "sparse" utility. - -ifdef C -ifeq ("$(origin C)", "command line") -CHECKSRC := $(C) +ifeq ($(HOSTOS),darwin) +# get major and minor product version (e.g. '10' and '6' for Snow Leopard) +DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.') +DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.') + +os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \ + $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) + +# Snow Leopards build environment has no longer restrictions as described above +HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc") +HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") +HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") endif + +# Decide whether to build built-in, modular, or both. +# Normally, just do built-in. + +KBUILD_MODULES := +KBUILD_BUILTIN := 1 + +# If we have only "make modules", don't compile built-in objects. +# When we're building modules with modversions, we need to consider +# the built-in objects during the descend as well, in order to +# make sure the checksums are up to date before we record them. + +ifeq ($(MAKECMDGOALS),modules) + KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1) endif -ifndef CHECKSRC - CHECKSRC = 0 -endif -export CHECKSRC -ifneq ($(BUILD_DIR),) -saved-output := $(BUILD_DIR) +# If we have "make modules", compile modules +# in addition to whatever we do anyway. +# Just "make" or "make all" shall build modules as well -# Attempt to create an output directory. -$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}) +# U-Boot does not need modules +#ifneq ($(filter all _all modules,$(MAKECMDGOALS)),) +# KBUILD_MODULES := 1 +#endif -# Verify if it was successful. -BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd) -$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist)) -endif # ifneq ($(BUILD_DIR),) +#ifeq ($(MAKECMDGOALS),) +# KBUILD_MODULES := 1 +#endif -OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR)) -SPLTREE := $(OBJTREE)/spl -SRCTREE := $(CURDIR) -TOPDIR := $(SRCTREE) -LNDIR := $(OBJTREE) -export TOPDIR SRCTREE OBJTREE SPLTREE +export KBUILD_MODULES KBUILD_BUILTIN +export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD -MKCONFIG := $(SRCTREE)/mkconfig -export MKCONFIG +# Look for make include files relative to root of kernel src +MAKEFLAGS += --include-dir=$(srctree) -ifneq ($(OBJTREE),$(SRCTREE)) -REMOTE_BUILD := 1 -export REMOTE_BUILD -endif +# We need some generic definitions (do not try to remake the file). +$(srctree)/scripts/Kbuild.include: ; +include $(srctree)/scripts/Kbuild.include -# $(obj) and (src) are defined in config.mk but here in main Makefile -# we also need them before config.mk is included which is the case for -# some targets like unconfig, clean, clobber, distclean, etc. -ifneq ($(OBJTREE),$(SRCTREE)) -obj := $(OBJTREE)/ -src := $(SRCTREE)/ +# Make variables (CC, etc...) + +AS = $(CROSS_COMPILE)as +# Always use GNU ld +ifneq ($(shell $(CROSS_COMPILE)ld.bfd -v 2> /dev/null),) +LD = $(CROSS_COMPILE)ld.bfd else -obj := -src := +LD = $(CROSS_COMPILE)ld +endif +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +LDR = $(CROSS_COMPILE)ldr +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +AWK = awk +PERL = perl +PYTHON = python +DTC = dtc +CHECK = sparse + +CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ + -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF) + +KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__ + +KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ + -Wno-format-security \ + -fno-builtin -ffreestanding +KBUILD_AFLAGS := -D__ASSEMBLY__ + +# Read UBOOTRELEASE from include/config/uboot.release (if it exists) +UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) +UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) + +export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION +export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR +export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC +export CPP AR NM LDR STRIP OBJCOPY OBJDUMP +export MAKE AWK PERL PYTHON +export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS + +export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS +export KBUILD_CFLAGS KBUILD_AFLAGS + +# When compiling out-of-tree modules, put MODVERDIR in the module +# tree rather than in the kernel tree. The kernel tree might +# even be read-only. +export MODVERDIR := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/).tmp_versions + +# Files to ignore in find ... statements + +export RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o \ + -name CVS -o -name .pc -o -name .hg -o -name .git \) \ + -prune -o +export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \ + --exclude CVS --exclude .pc --exclude .hg --exclude .git + +# =========================================================================== +# Rules shared between *config targets and build targets + +# Basic helpers built in scripts/ +PHONY += scripts_basic +scripts_basic: + $(Q)$(MAKE) $(build)=scripts/basic + $(Q)rm -f .tmp_quiet_recordmcount + +# To avoid any implicit rule to kick in, define an empty command. +scripts/basic/%: scripts_basic ; + +PHONY += outputmakefile +# outputmakefile generates a Makefile in the output directory, if using a +# separate output directory. This allows convenient use of make in the +# output directory. +outputmakefile: +ifneq ($(KBUILD_SRC),) + $(Q)ln -fsn $(srctree) source + $(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile \ + $(srctree) $(objtree) $(VERSION) $(PATCHLEVEL) endif -export obj src -TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h -VERSION_FILE = $(obj)include/generated/version_autogenerated.h +# To make sure we do not include .config for any of the *config targets +# catch them early, and hand them over to scripts/kconfig/Makefile +# It is allowed to specify more targets when calling make, including +# mixing *config targets and build targets. +# For example 'make oldconfig all'. +# Detect when mixed targets is specified, and make a second invocation +# of make so .config is not included in this case either (for *config). -# Make sure CDPATH settings don't interfere -unexport CDPATH +version_h := include/generated/version_autogenerated.h +timestamp_h := include/generated/timestamp_autogenerated.h -######################################################################### +no-dot-config-targets := clean clobber mrproper distclean \ + help %docs check% coccicheck \ + ubootversion backup -# The "tools" are needed early, so put this first -# Don't include stuff already done in $(LIBS) -# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC -# is "yes"), so compile examples after U-Boot is compiled. -SUBDIR_TOOLS = tools -SUBDIR_EXAMPLES = examples/standalone examples/api -SUBDIRS = $(SUBDIR_TOOLS) +config-targets := 0 +mixed-targets := 0 +dot-config := 1 + +ifneq ($(filter $(no-dot-config-targets), $(MAKECMDGOALS)),) + ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),) + dot-config := 0 + endif +endif -.PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE) +ifeq ($(KBUILD_EXTMOD),) + ifneq ($(filter config %config,$(MAKECMDGOALS)),) + config-targets := 1 + ifneq ($(filter-out config %config,$(MAKECMDGOALS)),) + mixed-targets := 1 + endif + endif +endif -ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) +ifeq ($(mixed-targets),1) +# =========================================================================== +# We're called with mixed targets (*config and build targets). +# Handle them one by one. -# Include autoconf.mk before config.mk so that the config options are available -# to all top level build files. We need the dummy all: target to prevent the -# dependency target in autoconf.mk.dep from being the default. -all: -sinclude $(obj)include/autoconf.mk.dep -sinclude $(obj)include/autoconf.mk +PHONY += $(MAKECMDGOALS) __build_one_by_one -ifndef CONFIG_SANDBOX -SUBDIRS += $(SUBDIR_EXAMPLES) -endif +$(filter-out __build_one_by_one, $(MAKECMDGOALS)): __build_one_by_one + @: -# load ARCH, BOARD, and CPU configuration -include $(obj)include/config.mk -export ARCH CPU BOARD VENDOR SOC +__build_one_by_one: + $(Q)set -e; \ + for i in $(MAKECMDGOALS); do \ + $(MAKE) -f $(srctree)/Makefile $$i; \ + done -# set default to nothing for native builds -ifeq ($(HOSTARCH),$(ARCH)) -CROSS_COMPILE ?= -endif +else +ifeq ($(config-targets),1) +# =========================================================================== +# *config targets only - make sure prerequisites are updated, and descend +# in scripts/kconfig to make the *config target -# load other configuration -include $(TOPDIR)/config.mk +KBUILD_DEFCONFIG := sandbox_defconfig +export KBUILD_DEFCONFIG KBUILD_KCONFIG -# Targets which don't build the source code -NON_BUILD_TARGETS = backup clean clobber distclean mkproper tidy unconfig +config: scripts_basic outputmakefile FORCE + +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@ -# Only do the generic board check when actually building, not configuring -ifeq ($(filter $(NON_BUILD_TARGETS),$(MAKECMDGOALS)),) -ifeq ($(findstring _config,$(MAKECMDGOALS)),) -$(CHECK_GENERIC_BOARD) -endif +%config: scripts_basic outputmakefile FORCE + +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@ + +else +# =========================================================================== +# Build targets only - this includes vmlinux, arch specific targets, clean +# targets and others. In general all targets except *config targets. + +ifeq ($(dot-config),1) +# Read in config +-include include/config/auto.conf + +# Read in dependencies to all Kconfig* files, make sure to run +# oldconfig if changes are detected. +-include include/config/auto.conf.cmd + +# To avoid any implicit rule to kick in, define an empty command +$(KCONFIG_CONFIG) include/config/auto.conf.cmd: ; + +# If .config is newer than include/config/auto.conf, someone tinkered +# with it and forgot to run make oldconfig. +# if auto.conf.cmd is missing then we are probably in a cleaned tree so +# we execute the config step to be sure to catch updated Kconfig files +include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd + $(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig + +-include include/autoconf.mk +-include include/autoconf.mk.dep + +# We want to include arch/$(ARCH)/config.mk only when include/config/auto.conf +# is up-to-date. When we switch to a different board configuration, old CONFIG +# macros are still remaining in include/config/auto.conf. Without the following +# gimmick, wrong config.mk would be included leading nasty warnings/errors. +autoconf_is_current := $(if $(wildcard $(KCONFIG_CONFIG)),$(shell find . \ + -path ./include/config/auto.conf -newer $(KCONFIG_CONFIG))) +ifneq ($(autoconf_is_current),) +include $(srctree)/config.mk +include $(srctree)/arch/$(ARCH)/Makefile endif # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use # that (or fail if absent). Otherwise, search for a linker script in a # standard location. -LDSCRIPT_MAKEFILE_DIR = $(dir $(LDSCRIPT)) - ifndef LDSCRIPT - #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug + #LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds.debug ifdef CONFIG_SYS_LDSCRIPT # need to strip off double quotes - LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) + LDSCRIPT := $(srctree)/$(CONFIG_SYS_LDSCRIPT:"%"=%) endif endif # If there is no specified link script, we look in a number of places for it ifndef LDSCRIPT - ifeq ($(CONFIG_NAND_U_BOOT),y) - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds - ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds - endif - endif - ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds - endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds + LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds - # We don't expect a Makefile here - LDSCRIPT_MAKEFILE_DIR = + LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot.lds endif ifeq ($(wildcard $(LDSCRIPT)),) -$(error could not find linker script) + LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot.lds endif endif -######################################################################### -# U-Boot objects....order is important (i.e. start must be first) +else +# Dummy target needed, because used as prerequisite +include/config/auto.conf: ; +endif # $(dot-config) -OBJS = $(CPUDIR)/start.o -ifeq ($(CPU),ppc4xx) -OBJS += $(CPUDIR)/resetvec.o -endif -ifeq ($(CPU),mpc85xx) -OBJS += $(CPUDIR)/resetvec.o -endif - -OBJS := $(addprefix $(obj),$(OBJS)) - -HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n) - -LIBS-y += lib/libgeneric.o -LIBS-y += lib/rsa/librsa.o -LIBS-y += lib/lzma/liblzma.o -LIBS-y += lib/lzo/liblzo.o -LIBS-y += lib/zlib/libz.o -LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o -LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o -LIBS-y += $(CPUDIR)/lib$(CPU).o -ifdef SOC -LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o -endif -ifeq ($(CPU),ixp) -LIBS-y += drivers/net/npe/libnpe.o -endif -LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o -LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o -LIBS-y += fs/libfs.o \ - fs/cbfs/libcbfs.o \ - fs/cramfs/libcramfs.o \ - fs/ext4/libext4fs.o \ - fs/fat/libfat.o \ - fs/fdos/libfdos.o \ - fs/jffs2/libjffs2.o \ - fs/reiserfs/libreiserfs.o \ - fs/sandbox/libsandboxfs.o \ - fs/ubifs/libubifs.o \ - fs/yaffs2/libyaffs2.o \ - fs/zfs/libzfs.o -LIBS-y += net/libnet.o -LIBS-y += disk/libdisk.o -LIBS-y += drivers/bios_emulator/libatibiosemu.o -LIBS-y += drivers/block/libblock.o -LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o -LIBS-y += drivers/crypto/libcrypto.o -LIBS-y += drivers/dma/libdma.o -LIBS-y += drivers/fpga/libfpga.o -LIBS-y += drivers/gpio/libgpio.o -LIBS-y += drivers/hwmon/libhwmon.o -LIBS-y += drivers/i2c/libi2c.o -LIBS-y += drivers/input/libinput.o -LIBS-y += drivers/misc/libmisc.o -LIBS-y += drivers/mmc/libmmc.o -LIBS-y += drivers/mtd/libmtd.o -LIBS-y += drivers/mtd/nand/libnand.o -LIBS-y += drivers/mtd/onenand/libonenand.o -LIBS-y += drivers/mtd/ubi/libubi.o -LIBS-y += drivers/mtd/spi/libspi_flash.o -LIBS-y += drivers/net/libnet.o -LIBS-y += drivers/net/phy/libphy.o -LIBS-y += drivers/pci/libpci.o -LIBS-y += drivers/pcmcia/libpcmcia.o -LIBS-y += drivers/power/libpower.o \ - drivers/power/fuel_gauge/libfuel_gauge.o \ - drivers/power/pmic/libpmic.o \ - drivers/power/battery/libbattery.o -LIBS-y += drivers/spi/libspi.o -LIBS-y += drivers/dfu/libdfu.o -ifeq ($(CPU),mpc83xx) -LIBS-y += drivers/qe/libqe.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif -ifeq ($(CPU),mpc85xx) -LIBS-y += drivers/qe/libqe.o -LIBS-y += drivers/net/fm/libfm.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif -ifeq ($(CPU),mpc86xx) -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif -LIBS-y += drivers/rtc/librtc.o -LIBS-y += drivers/serial/libserial.o -LIBS-y += drivers/sound/libsound.o -LIBS-y += drivers/tpm/libtpm.o -LIBS-y += drivers/twserial/libtws.o -LIBS-y += drivers/usb/eth/libusb_eth.o -LIBS-y += drivers/usb/gadget/libusb_gadget.o -LIBS-y += drivers/usb/host/libusb_host.o -LIBS-y += drivers/usb/musb/libusb_musb.o -LIBS-y += drivers/usb/musb-new/libusb_musb-new.o -LIBS-y += drivers/usb/phy/libusb_phy.o -LIBS-y += drivers/usb/ulpi/libusb_ulpi.o -LIBS-y += drivers/video/libvideo.o -LIBS-y += drivers/watchdog/libwatchdog.o -LIBS-y += common/libcommon.o -LIBS-y += lib/libfdt/libfdt.o -LIBS-y += api/libapi.o -LIBS-y += post/libpost.o -LIBS-y += test/libtest.o - -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) -LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -endif - -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) -LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o -endif - -ifeq ($(SOC),s5pc1xx) -LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o -endif -ifeq ($(SOC),exynos) -LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o +ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE +KBUILD_CFLAGS += -Os +else +KBUILD_CFLAGS += -O2 endif -ifneq ($(CONFIG_TEGRA),) -LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o -LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o -LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o + +ifdef BUILD_TAG +KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' endif -LIBS := $(addprefix $(obj),$(sort $(LIBS-y))) -.PHONY : $(LIBS) +KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) -LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o -LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) +KBUILD_CFLAGS += -g +# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g +# option to the assembler. +KBUILD_AFLAGS += -g -# Add GCC lib -ifdef USE_PRIVATE_LIBGCC -ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") -PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/libgcc.o -else -PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc +# Report stack usage if supported +ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-stack-usage.sh $(CC)),y) + KBUILD_CFLAGS += -fstack-usage endif + +KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral) + +# turn jbsr into jsr for m68k +ifeq ($(ARCH),m68k) +ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4) +KBUILD_AFLAGS += -Wa,-gstabs,-S +endif +endif + +# Prohibit date/time macros, which would make the build non-deterministic +KBUILD_CFLAGS += $(call cc-option,-Werror=date-time) + +ifneq ($(CONFIG_SYS_TEXT_BASE),) +KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) +endif + +export CONFIG_SYS_TEXT_BASE + +include $(srctree)/scripts/Makefile.extrawarn + +# Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments +KBUILD_CPPFLAGS += $(KCPPFLAGS) +KBUILD_AFLAGS += $(KAFLAGS) +KBUILD_CFLAGS += $(KCFLAGS) + +# Use UBOOTINCLUDE when you must reference the include/ directory. +# Needed to be compatible with the O= option +UBOOTINCLUDE := \ + -Iinclude \ + $(if $(KBUILD_SRC), -I$(srctree)/include) \ + -I$(srctree)/arch/$(ARCH)/include \ + -include $(srctree)/include/linux/kconfig.h + +NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include) +CHECKFLAGS += $(NOSTDINC_FLAGS) + +# FIX ME +cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \ + $(NOSTDINC_FLAGS) +c_flags := $(KBUILD_CFLAGS) $(cpp_flags) + +######################################################################### +# U-Boot objects....order is important (i.e. start must be first) + +HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n) + +libs-y += lib/ +libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ +libs-$(CONFIG_OF_EMBED) += dts/ +libs-y += fs/ +libs-y += net/ +libs-y += disk/ +libs-y += drivers/ +libs-y += drivers/dma/ +libs-y += drivers/gpio/ +libs-y += drivers/i2c/ +libs-y += drivers/mmc/ +libs-y += drivers/mtd/ +libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/ +libs-y += drivers/mtd/onenand/ +libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/ +libs-y += drivers/mtd/spi/ +libs-y += drivers/net/ +libs-y += drivers/net/phy/ +libs-y += drivers/pci/ +libs-y += drivers/power/ \ + drivers/power/fuel_gauge/ \ + drivers/power/mfd/ \ + drivers/power/pmic/ \ + drivers/power/battery/ +libs-y += drivers/spi/ +libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ +libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ +libs-y += drivers/serial/ +libs-y += drivers/usb/eth/ +libs-y += drivers/usb/gadget/ +libs-y += drivers/usb/host/ +libs-y += drivers/usb/musb/ +libs-y += drivers/usb/musb-new/ +libs-y += drivers/usb/phy/ +libs-y += drivers/usb/ulpi/ +libs-y += common/ +libs-$(CONFIG_API) += api/ +libs-$(CONFIG_HAS_POST) += post/ +libs-y += test/ +libs-y += test/dm/ + +libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/) + +libs-y := $(sort $(libs-y)) + +u-boot-dirs := $(patsubst %/,%,$(filter %/, $(libs-y))) tools examples + +u-boot-alldirs := $(sort $(u-boot-dirs) $(patsubst %/,%,$(filter %/, $(libs-)))) + +libs-y := $(patsubst %/, %/built-in.o, $(libs-y)) + +u-boot-init := $(head-y) +u-boot-main := $(libs-y) + + +# Add GCC lib +ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) +PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a else -PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc +PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc endif PLATFORM_LIBS += $(PLATFORM_LIBGCC) export PLATFORM_LIBS +export PLATFORM_LIBGCC # Special flags for CPP when processing the linker script. # Pass the version down so we can handle backwards compatibility # on the fly. LDPPFLAGS += \ - -include $(TOPDIR)/include/u-boot/u-boot.lds.h \ + -include $(srctree)/include/u-boot/u-boot.lds.h \ -DCPUDIR=$(CPUDIR) \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -__OBJS := $(subst $(obj),,$(OBJS)) -__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) - ######################################################################### ######################################################################### @@ -392,55 +696,150 @@ else BOARD_SIZE_CHECK = endif +# Statically apply RELA-style relocations (currently arm64 only) +ifneq ($(CONFIG_STATIC_RELA),) +# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base +DO_STATIC_RELA = \ + start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \ + end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \ + tools/relocate-rela $(2) $(3) $$start $$end +else +DO_STATIC_RELA = +endif + # Always append ALL so that arch config.mk's can add custom ones -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map +ALL-y += u-boot.srec u-boot.bin System.map binary_size_check -ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin -ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin -ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin -ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin +ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin +ifeq ($(CONFIG_SPL_FSL_PBL),y) +ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin +else +ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl +endif +ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img +ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin +ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin +ifeq ($(CONFIG_SPL_FRAMEWORK),y) +ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img +endif +ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb ifneq ($(CONFIG_SPL_TARGET),) -ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET)) +ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif +ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf + +# We can't do this yet due to the need for binary blobs +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) +ifeq ($(CONFIG_SPL),y) ifeq ($(CONFIG_OF_SEPARATE),y) -ALL-y += $(obj)u-boot-dtb-tegra.bin +ALL-y += u-boot-dtb-tegra.bin else -ALL-y += $(obj)u-boot-nodtb-tegra.bin +ALL-y += u-boot-nodtb-tegra.bin +endif endif endif -all: $(ALL-y) $(SUBDIR_EXAMPLES) +# Add optional build target if defined in board/cpu/soc headers +ifneq ($(CONFIG_BUILD_TARGET),) +ALL-y += $(CONFIG_BUILD_TARGET:"%"=%) +endif -$(obj)u-boot.dtb: checkdtc $(obj)u-boot - $(MAKE) -C dts binary - mv $(obj)dts/dt.dtb $@ +LDFLAGS_u-boot += $(LDFLAGS_FINAL) +ifneq ($(CONFIG_SYS_TEXT_BASE),) +LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) +endif -$(obj)u-boot-dtb.bin: $(obj)u-boot.bin $(obj)u-boot.dtb - cat $^ >$@ +quiet_cmd_objcopy = OBJCOPY $@ +cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ -$(obj)u-boot.hex: $(obj)u-boot - $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) -$(obj)u-boot.srec: $(obj)u-boot - $(OBJCOPY) -O srec $< $@ +quiet_cmd_cat = CAT $@ +cmd_cat = cat $(filter-out $(PHONY), $^) > $@ -$(obj)u-boot.bin: $(obj)u-boot - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - $(BOARD_SIZE_CHECK) +append = cat $(filter-out $< $(PHONY), $^) >> $@ + +quiet_cmd_pad_cat = CAT $@ +cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@ + +all: $(ALL-y) +ifneq ($(CONFIG_SYS_GENERIC_BOARD),y) + @echo "===================== WARNING ======================" + @echo "Please convert this board to generic board." + @echo "Otherwise it will be removed by the end of 2014." + @echo "See doc/README.generic-board for further information" + @echo "====================================================" +endif +ifeq ($(CONFIG_DM_I2C_COMPAT),y) + @echo "===================== WARNING ======================" + @echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove" + @echo "(possibly in a subsequent patch in your series)" + @echo "before sending patches to the mailing list." + @echo "====================================================" +endif + +PHONY += dtbs +dtbs dts/dt.dtb: checkdtc u-boot + $(Q)$(MAKE) $(build)=dts dtbs + +u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE + $(call if_changed,cat) + +%.imx: %.bin + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ + +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ -$(obj)u-boot.ldr: $(obj)u-boot +u-boot.dtb: dts/dt.dtb + $(call cmd,copy) + +OBJCOPYFLAGS_u-boot.hex := -O ihex + +OBJCOPYFLAGS_u-boot.srec := -O srec + +u-boot.hex u-boot.srec: u-boot FORCE + $(call if_changed,objcopy) + +OBJCOPYFLAGS_u-boot.bin := -O binary \ + $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec) + +binary_size_check: u-boot.bin FORCE + @file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \ + map_size=$(shell cat u-boot.map | \ + awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \ + | sed 's/0X//g' \ + | bc); \ + if [ "" != "$$map_size" ]; then \ + if test $$map_size -ne $$file_size; then \ + echo "u-boot.map shows a binary size of $$map_size" >&2 ; \ + echo " but u-boot.bin shows $$file_size" >&2 ; \ + exit 1; \ + fi \ + fi + +u-boot.bin: u-boot FORCE + $(call if_changed,objcopy) + $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE)) + $(BOARD_SIZE_CHECK) + +u-boot.ldr: u-boot $(CREATE_LDR_ENV) - $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) + $(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) -$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr - $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary +OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex -$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr - $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary +OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec + +u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE + $(call if_changed,objcopy) # # U-Boot entry point, needed for booting of full-blown U-Boot @@ -450,67 +849,74 @@ ifndef CONFIG_SYS_UBOOT_START CONFIG_SYS_UBOOT_START := 0 endif -$(obj)u-boot.img: $(obj)u-boot.bin - $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ - -O u-boot -a $(CONFIG_SYS_TEXT_BASE) \ - -e $(CONFIG_SYS_UBOOT_START) \ - -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ - sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ - -d $< $@ +MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" + +MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ + -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -$(obj)u-boot.imx: $(obj)u-boot.bin depend - $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx +MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage -$(obj)u-boot.kwb: $(obj)u-boot.bin - $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ - -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ +u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE + $(call if_changed,mkimage) -$(obj)u-boot.pbl: $(obj)u-boot.bin - $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ - -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ - -d $< $@ +MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) -$(obj)u-boot.sha1: $(obj)u-boot.bin - $(obj)tools/ubsha1 $(obj)u-boot.bin +u-boot-dtb.img: u-boot-dtb.bin FORCE + $(call if_changed,mkimage) -$(obj)u-boot.dis: $(obj)u-boot +u-boot.sha1: u-boot.bin + tools/ubsha1 u-boot.bin + +u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ +ifdef CONFIG_TPL +SPL_PAYLOAD := tpl/u-boot-with-tpl.bin +else +SPL_PAYLOAD := u-boot.bin +endif + +OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) +u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE + $(call if_changed,pad_cat) +OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_TPL_PAD_TO) +tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE + $(call if_changed,pad_cat) -$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ - -I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin - cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ - rm $(obj)spl/u-boot-spl-pad.bin +SPL: spl/u-boot-spl.bin FORCE + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ -$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \ - $(OBJTREE)/u-boot-with-spl.imx +u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ -$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \ - $(OBJTREE)/u-boot-with-nand-spl.imx +MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE) -$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin - $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ - -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl +u-boot.ubl: u-boot-with-spl.bin FORCE + $(call if_changed,mkimage) -$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - $(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \ - -T aisimage \ - -e $(CONFIG_SPL_TEXT_BASE) \ - -d $(obj)spl/u-boot-spl.bin \ - $(obj)spl/u-boot-spl.ais - $(OBJCOPY) ${OBJCFLAGS} -I binary \ - --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \ - $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais - cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \ - $(obj)u-boot.ais +MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \ + $(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \ + -T aisimage -e $(CONFIG_SPL_TEXT_BASE) +spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) +OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) +u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE + $(call if_changed,pad_cat) -$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb - $(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb +u-boot-signed.sb: u-boot.bin spl/u-boot-spl.bin + $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot-signed.sb +u-boot.sb: u-boot.bin spl/u-boot-spl.bin elftosb + $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb + +elftosb: + $(MAKE) -C $(KBUILD_SRC)/tools/elftosb all # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. # Both images are created using mkimage (crc etc), so that the ROM @@ -518,128 +924,304 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb # SPL image (with mkimage header) and not the binary. Otherwise the resulting image # which is loaded/copied by the ROM bootloader to SRAM doesn't fit. # The resulting image containing both U-Boot images is called u-boot.spr -$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin - $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ - -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \ - -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img - tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \ - of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null - dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \ - conv=notrunc 2>/dev/null - cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@ +MKIMAGEFLAGS_u-boot-spl.img = -A $(ARCH) -T firmware -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER +spl/u-boot-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0xff +u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE + $(call if_changed,pad_cat) + +MKIMAGEFLAGS_u-boot-spl.gph = -A $(ARCH) -T gpimage -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n SPL +spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0 +u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE + $(call if_changed,pad_cat) + +MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot +u-boot-nand.gph: u-boot.bin FORCE + $(call if_changed,mkimage) + @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@ + +# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including +# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in +# the middle. +ifneq ($(CONFIG_X86_RESET_VECTOR),) +rom: u-boot.rom FORCE + +IFDTOOL=$(objtree)/tools/ifdtool +IFDTOOL_FLAGS = -f 0:$(objtree)/u-boot.dtb +IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1) +IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin +IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin + +ifneq ($(CONFIG_HAVE_INTEL_ME),) +IFDTOOL_ME_FLAGS = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin +IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin +endif + +ifneq ($(CONFIG_HAVE_MRC),) +IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin +endif + +ifneq ($(CONFIG_HAVE_FSP),) +IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE) +endif + +ifneq ($(CONFIG_HAVE_CMC),) +IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE) +endif + +ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) +IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE) +endif + +quiet_cmd_ifdtool = IFDTOOL $@ +cmd_ifdtool = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp; +ifneq ($(CONFIG_HAVE_INTEL_ME),) +cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp; +endif +cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp; +cmd_ifdtool += mv u-boot.tmp $@ + +u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin + $(call if_changed,ifdtool) + +OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec +u-boot-x86-16bit.bin: u-boot FORCE + $(call if_changed,objcopy) +endif + +ifneq ($(CONFIG_SUNXI),) +OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \ + u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE + $(call if_changed,pad_cat) +endif ifneq ($(CONFIG_TEGRA),) -$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin - cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ - rm $(obj)spl/u-boot-spl-pad.bin +OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) +u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE + $(call if_changed,pad_cat) ifeq ($(CONFIG_OF_SEPARATE),y) -$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb - cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@ +u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin dts/dt.dtb FORCE + $(call if_changed,cat) endif endif -$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@ +u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE + $(call if_changed,cat) + +#Add a target to create boot binary having SPL binary in PBI format +#concatenated with u-boot binary. It is need by PowerPC SoC having +#internal SRAM <= 512KB. +MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage \ + -A $(ARCH) -a $(CONFIG_SPL_TEXT_BASE) + +spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +ifeq ($(ARCH),arm) +UBOOT_BINLOAD := u-boot.img +else +UBOOT_BINLOAD := u-boot.bin +endif + +OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0xff + +u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE + $(call if_changed,pad_cat) # PPC4xx needs the SPL at the end of the image, since the reset vector # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target # and need to introduce a new build target with the full blown U-Boot # at the start padded up to the start of the SPL image. And then concat # the SPL image to the end. -$(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_UBOOT_PAD_TO) \ - of=$(obj)u-boot-pad.img 2>/dev/null - dd if=$(obj)u-boot.img of=$(obj)u-boot-pad.img \ - conv=notrunc 2>/dev/null - cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@ - -ifeq ($(CONFIG_SANDBOX),y) -GEN_UBOOT = \ - cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ - -Wl,--start-group $(__LIBS) -Wl,--end-group \ - $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot -else -GEN_UBOOT = \ - cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ - $(__OBJS) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ - -Map u-boot.map -o u-boot -endif -$(obj)u-boot: depend \ - $(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds - $(GEN_UBOOT) +OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \ + --pad-to=$(CONFIG_UBOOT_PAD_TO) --gap-fill=0xff +u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE + $(call if_changed,pad_cat) + +# Create a new ELF from a raw binary file. This is useful for arm64 +# where static relocation needs to be performed on the raw binary, +# but certain simulators only accept an ELF file (but don't do the +# relocation). +# FIXME refactor dts/Makefile to share target/arch detection +u-boot.elf: u-boot.bin + @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \ + $< u-boot-elf.o + @$(LD) u-boot-elf.o -o $@ \ + --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ + -Ttext=$(CONFIG_SYS_TEXT_BASE) + +# Rule to link u-boot +# May be overridden by arch/$(ARCH)/config.mk +quiet_cmd_u-boot__ ?= LD $@ + cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \ + -T u-boot.lds $(u-boot-init) \ + --start-group $(u-boot-main) --end-group \ + $(PLATFORM_LIBS) -Map u-boot.map + +quiet_cmd_smap = GEN common/system_map.o +cmd_smap = \ + smap=`$(call SYSTEM_MAP,u-boot) | \ + awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ + $(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \ + -c $(srctree)/common/system_map.c -o common/system_map.o + +u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds + $(call if_changed,u-boot__) ifeq ($(CONFIG_KALLSYMS),y) - smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \ - awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ - $(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \ - -c common/system_map.c -o $(obj)common/system_map.o - $(GEN_UBOOT) $(obj)common/system_map.o + $(call cmd,smap) + $(call cmd,u-boot__) common/system_map.o endif -$(OBJS): depend - $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)) +# The actual objects are generated when descending, +# make sure no implicit rule kicks in +$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ; -$(LIBS): depend $(SUBDIR_TOOLS) - $(MAKE) -C $(dir $(subst $(obj),,$@)) +# Handle descending into subdirectories listed in $(vmlinux-dirs) +# Preset locale variables to speed up the build process. Limit locale +# tweaks to this spot to avoid wrong language settings when running +# make menuconfig etc. +# Error messages still appears in the original language -$(LIBBOARD): depend $(LIBS) - $(MAKE) -C $(dir $(subst $(obj),,$@)) +PHONY += $(u-boot-dirs) +$(u-boot-dirs): prepare scripts + $(Q)$(MAKE) $(build)=$@ -$(SUBDIRS): depend - $(MAKE) -C $@ all +tools: prepare +# The "tools" are needed early +$(filter-out tools, $(u-boot-dirs)): tools +# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC +# is "yes"), so compile examples after U-Boot is compiled. +examples: $(filter-out examples, $(u-boot-dirs)) + +define filechk_uboot.release + echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" +endef + +# Store (new) UBOOTRELEASE string in include/config/uboot.release +include/config/uboot.release: include/config/auto.conf FORCE + $(call filechk,uboot.release) + + +# Things we need to do before we recursively start building the kernel +# or the modules are listed in "prepare". +# A multi level approach is used. prepareN is processed before prepareN-1. +# archprepare is used in arch Makefiles and when processed asm symlink, +# version.h and scripts_basic is processed / created. + +# Listed in dependency order +PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3 + +# prepare3 is used to check if we are building in a separate output directory, +# and if so do: +# 1) Check that make has not been executed in the kernel src $(srctree) +prepare3: include/config/uboot.release +ifneq ($(KBUILD_SRC),) + @$(kecho) ' Using $(srctree) as source for U-Boot' + $(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \ + echo >&2 " $(srctree) is not clean, please run 'make mrproper'"; \ + echo >&2 " in the '$(srctree)' directory.";\ + /bin/false; \ + fi; +endif -$(SUBDIR_EXAMPLES): $(obj)u-boot +# prepare2 creates a makefile if using a separate output directory +prepare2: prepare3 outputmakefile -$(LDSCRIPT): depend - $(MAKE) -C $(dir $@) $(notdir $@) +prepare1: prepare2 $(version_h) $(timestamp_h) \ + include/config/auto.conf +ifeq ($(__HAVE_ARCH_GENERIC_BOARD),) +ifeq ($(CONFIG_SYS_GENERIC_BOARD),y) + @echo >&2 " Your architecture does not support generic board." + @echo >&2 " Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file." + @/bin/false +endif +endif +ifeq ($(wildcard $(LDSCRIPT)),) + @echo >&2 " Could not find linker script." + @/bin/false +endif -$(obj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@ +archprepare: prepare1 scripts_basic -nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend - $(MAKE) -C nand_spl/board/$(BOARDDIR) all +prepare0: archprepare FORCE + $(Q)$(MAKE) $(build)=. -$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin +# All the preparing.. +prepare: prepare0 -$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend - $(MAKE) -C spl all +# Generate some files +# --------------------------------------------------------------------------- -updater: - $(MAKE) -C tools/updater all -elftosb: - $(MAKE) -C $(SUBDIR_TOOLS)/elftosb all +define filechk_version.h + (echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \ + echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \ + echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \ + echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; ) +endef -# Explicitly make _depend in subdirs containing multiple targets to prevent -# parallel sub-makes creating .depend files simultaneously. -depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \ - $(obj)include/autoconf.mk \ - $(obj)include/generated/generic-asm-offsets.h \ - $(obj)include/generated/asm-offsets.h - for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \ - $(MAKE) -C $$dir _depend ; done +define filechk_timestamp.h + (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ + LC_ALL=C date +'#define U_BOOT_TIME "%T"') +endef -TAG_SUBDIRS = $(SUBDIRS) -TAG_SUBDIRS += $(dir $(__LIBS)) -TAG_SUBDIRS += include +$(version_h): include/config/uboot.release FORCE + $(call filechk,version.h) + +$(timestamp_h): $(srctree)/Makefile FORCE + $(call filechk,timestamp.h) + +# --------------------------------------------------------------------------- + +PHONY += depend dep +depend dep: + @echo '*** Warning: make $@ is unnecessary now.' + +# --------------------------------------------------------------------------- +quiet_cmd_cpp_lds = LDS $@ +cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ + -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $< + +u-boot.lds: $(LDSCRIPT) prepare FORCE + $(call if_changed_dep,cpp_lds) + +spl/u-boot-spl.bin: spl/u-boot-spl + @: +spl/u-boot-spl: tools prepare + $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all + +spl/sunxi-spl.bin: spl/u-boot-spl + @: + +tpl/u-boot-tpl.bin: tools prepare + $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all + +TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include) FIND := find FINDFLAGS := -L -checkstack: - $(CROSS_COMPILE)objdump -d $(obj)u-boot \ - `$(FIND) $(obj) -name u-boot-spl -print` | \ - perl $(src)tools/checkstack.pl $(ARCH) - tags ctags: - ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ + ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ -name '*.[chS]' -print` etags: - etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ + etags -a -o etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ -name '*.[chS]' -print` cscope: $(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \ @@ -650,25 +1232,8 @@ SYSTEM_MAP = \ $(NM) $1 | \ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ LC_ALL=C sort -$(obj)System.map: $(obj)u-boot - @$(call SYSTEM_MAP,$<) > $(obj)System.map - -checkthumb: - @if test $(call cc-version) -lt 0404; then \ - echo -n '*** Your GCC does not produce working '; \ - echo 'binaries in THUMB mode.'; \ - echo '*** Your board is configured for THUMB mode.'; \ - false; \ - fi - -# GCC 3.x is reported to have problems generating the type of relocation -# that U-Boot wants. -# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html -checkgcc4: - @if test $(call cc-version) -lt 0400; then \ - echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \ - false; \ - fi +System.map: u-boot + @$(call SYSTEM_MAP,$<) > $@ checkdtc: @if test $(call dtc-version) -lt 0104; then \ @@ -676,103 +1241,30 @@ checkdtc: false; \ fi -# -# Auto-generate the autoconf.mk file (which is included by all makefiles) -# -# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep. -# the dep file is only include in this top level makefile to determine when -# to regenerate the autoconf.mk file. -$(obj)include/autoconf.mk.dep: $(obj)include/config.h include/common.h - @$(XECHO) Generating $@ ; \ - set -e ; \ - : Generate the dependancies ; \ - $(CC) -x c -DDO_DEPS_ONLY -M $(CFLAGS) $(CPPFLAGS) \ - -MQ $(obj)include/autoconf.mk include/common.h > $@ - -$(obj)include/autoconf.mk: $(obj)include/config.h - @$(XECHO) Generating $@ ; \ - set -e ; \ - : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \ - sed -n -f tools/scripts/define2mk.sed > $@.tmp && \ - mv $@.tmp $@ - -$(obj)include/generated/generic-asm-offsets.h: $(obj)include/autoconf.mk.dep \ - $(obj)lib/asm-offsets.s - @$(XECHO) Generating $@ - tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@ - -$(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \ - $(src)lib/asm-offsets.c - @mkdir -p $(obj)lib - $(CC) -DDO_DEPS_ONLY \ - $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ - -o $@ $(src)lib/asm-offsets.c -c -S - -$(obj)include/generated/asm-offsets.h: $(obj)include/autoconf.mk.dep \ - $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s - @$(XECHO) Generating $@ - tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@ - -$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/autoconf.mk.dep - @mkdir -p $(obj)$(CPUDIR)/$(SOC) - if [ -f $(src)$(CPUDIR)/$(SOC)/asm-offsets.c ];then \ - $(CC) -DDO_DEPS_ONLY \ - $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ - -o $@ $(src)$(CPUDIR)/$(SOC)/asm-offsets.c -c -S; \ - else \ - touch $@; \ +######################################################################### + +# ARM relocations should all be R_ARM_RELATIVE (32-bit) or +# R_AARCH64_RELATIVE (64-bit). +checkarmreloc: u-boot + @RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \ + grep R_A | sort -u`"; \ + if test "$$RELOC" != "R_ARM_RELATIVE" -a \ + "$$RELOC" != "R_AARCH64_RELATIVE"; then \ + echo "$< contains unexpected relocations: $$RELOC"; \ + false; \ fi -######################################################################### -else # !config.mk -all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ -$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ -$(filter-out tools,$(SUBDIRS)) \ -updater depend dep tags ctags etags cscope $(obj)System.map: - @echo "System not configured - see README" >&2 - @ exit 1 - -tools: $(VERSION_FILE) $(TIMESTAMP_FILE) - $(MAKE) -C $@ all -endif # config.mk - -# ARM relocations should all be R_ARM_RELATIVE. -checkarmreloc: $(obj)u-boot - @if test "R_ARM_RELATIVE" != \ - "`$(CROSS_COMPILE)readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \ - then echo "$< contains relocations other than \ - R_ARM_RELATIVE"; false; fi - -$(VERSION_FILE): - @mkdir -p $(dir $(VERSION_FILE)) - @( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \ - printf '#define PLAIN_VERSION "%s%s"\n' \ - "$(U_BOOT_VERSION)" "$${localvers}" ; \ - printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \ - "$(U_BOOT_VERSION)" "$${localvers}" ; \ - ) > $@.tmp - @( printf '#define CC_VERSION_STRING "%s"\n' \ - '$(shell $(CC) --version | head -n 1)' )>> $@.tmp - @( printf '#define LD_VERSION_STRING "%s"\n' \ - '$(shell $(LD) -v | head -n 1)' )>> $@.tmp - @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ - -$(TIMESTAMP_FILE): - @mkdir -p $(dir $(TIMESTAMP_FILE)) - @LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@.tmp - @LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@.tmp - @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ - -easylogo env gdb: - $(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION} -gdbtools: gdb - -xmldocs pdfdocs psdocs htmldocs mandocs: tools/kernel-doc/docproc - $(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) -C doc/DocBook/ $@ - -tools-all: easylogo env gdb $(VERSION_FILE) $(TIMESTAMP_FILE) - $(MAKE) -C tools HOST_TOOLS_ALL=y +env: scripts_basic + $(Q)$(MAKE) $(build)=tools/$@ + +tools-only: scripts_basic $(version_h) $(timestamp_h) + $(Q)$(MAKE) $(build)=tools + +tools-all: export HOST_TOOLS_ALL=y +tools-all: env tools ; + +cross_tools: export CROSS_BUILD_TOOLS=y +cross_tools: tools ; .PHONY : CHANGELOG CHANGELOG: @@ -783,114 +1275,232 @@ include/license.h: tools/bin2header COPYING cat COPYING | gzip -9 -c | ./tools/bin2header license_gzip > include/license.h ######################################################################### -unconfig: - @rm -f $(obj)include/config.h $(obj)include/config.mk \ - $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \ - $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep +### +# Cleaning is done on three levels. +# make clean Delete most generated files +# Leave enough to build external modules +# make mrproper Delete the current configuration, and all generated files +# make distclean Remove editor backup files, patch leftover files and the like + +# Directories & files removed with 'make clean' +CLEAN_DIRS += $(MODVERDIR) \ + $(foreach d, spl tpl, $(patsubst %,$d/%, \ + $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) -%_config:: unconfig - @$(MKCONFIG) -A $(@:_config=) +CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ + boot* u-boot* MLO* SPL System.map -sinclude $(obj).boards.depend -$(obj).boards.depend: boards.cfg - @awk '(NF && $$1 !~ /^#/) { print $$1 ": " $$1 "_config; $$(MAKE)" }' $< > $@ +# Directories & files removed with 'make mrproper' +MRPROPER_DIRS += include/config include/generated spl tpl \ + .tmp_objdiff +MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \ + ctags etags TAGS cscope* GPATH GTAGS GRTAGS GSYMS +# clean - Delete most, but leave enough to build external modules # -# Functions to generate common board directory names +clean: rm-dirs := $(CLEAN_DIRS) +clean: rm-files := $(CLEAN_FILES) + +clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f)) + +clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook) + +PHONY += $(clean-dirs) clean archclean +$(clean-dirs): + $(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@) + +# TODO: Do not use *.cfgtmp +clean: $(clean-dirs) + $(call cmd,rmdirs) + $(call cmd,rmfiles) + @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ + \( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \ + -o -name '*.ko.*' -o -name '*.su' -o -name '*.cfgtmp' \ + -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ + -o -name '*.symtypes' -o -name 'modules.order' \ + -o -name modules.builtin -o -name '.tmp_*.o.*' \ + -o -name '*.gcno' \) -type f -print | xargs rm -f + +# mrproper - Delete all generated files, including .config # -lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/') -ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/') +mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS)) +mrproper: rm-files := $(wildcard $(MRPROPER_FILES)) +mrproper-dirs := $(addprefix _mrproper_,scripts) -######################################################################### -######################################################################### +PHONY += $(mrproper-dirs) mrproper archmrproper +$(mrproper-dirs): + $(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@) -clean: - @rm -f $(obj)examples/standalone/82559_eeprom \ - $(obj)examples/standalone/atmel_df_pow2 \ - $(obj)examples/standalone/eepro100_eeprom \ - $(obj)examples/standalone/hello_world \ - $(obj)examples/standalone/interrupt \ - $(obj)examples/standalone/mem_to_mem_idma2intr \ - $(obj)examples/standalone/sched \ - $(obj)examples/standalone/smc911{11,x}_eeprom \ - $(obj)examples/standalone/test_burst \ - $(obj)examples/standalone/timer - @rm -f $(obj)examples/api/demo{,.bin} - @rm -f $(obj)tools/bmp_logo $(obj)tools/easylogo/easylogo \ - $(obj)tools/env/{fw_printenv,fw_setenv} \ - $(obj)tools/envcrc \ - $(obj)tools/gdb/{astest,gdbcont,gdbsend} \ - $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ - $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \ - $(obj)tools/mk{smdk5250,}spl \ - $(obj)tools/mxsboot \ - $(obj)tools/ncb $(obj)tools/ubsha1 \ - $(obj)tools/kernel-doc/docproc \ - $(obj)tools/proftool - @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \ - $(obj)board/matrix_vision/*/bootscript.img \ - $(obj)board/voiceblue/eeprom \ - $(obj)u-boot.lds \ - $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \ - $(obj)arch/blackfin/cpu/init.{lds,elf} - @rm -f $(obj)include/bmp_logo.h - @rm -f $(obj)include/bmp_logo_data.h - @rm -f $(obj)lib/asm-offsets.s - @rm -f $(obj)include/generated/asm-offsets.h - @rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s - @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE) - @$(MAKE) -s -C doc/DocBook/ cleandocs - @find $(OBJTREE) -type f \ - \( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \ - -o -name '*.o' -o -name '*.a' -o -name '*.exe' \ - -o -name '*.cfgtmp' \) -print \ - | xargs rm -f - -# Removes everything not needed for testing u-boot -tidy: clean - @find $(OBJTREE) -type f \( -name '*.depend*' \) -print | xargs rm -f - -clobber: tidy - @find $(OBJTREE) -type f \( -name '*.srec' \ - -o -name '*.bin' -o -name u-boot.img \) \ - -print0 | xargs -0 rm -f - @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \ - $(obj)cscope.* $(obj)*.*~ - @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y) - @rm -f $(obj)u-boot.kwb - @rm -f $(obj)u-boot.pbl - @rm -f $(obj)u-boot.imx - @rm -f $(obj)u-boot-with-spl.imx - @rm -f $(obj)u-boot-with-nand-spl.imx - @rm -f $(obj)u-boot.ubl - @rm -f $(obj)u-boot.ais - @rm -f $(obj)u-boot.dtb - @rm -f $(obj)u-boot.sb - @rm -f $(obj)u-boot.bd - @rm -f $(obj)u-boot.spr - @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map} - @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} - @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} - @rm -f $(obj)spl/u-boot-spl.lds - @rm -f $(obj)MLO MLO.byteswap - @rm -f $(obj)SPL - @rm -f $(obj)tools/xway-swap-bytes - @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c - @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c - @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm - @rm -fr $(obj)include/generated - @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f - @rm -f $(obj)dts/*.tmp - @rm -f $(obj)spl/u-boot-spl{,-pad}.ais - -mrproper \ -distclean: clobber unconfig -ifneq ($(OBJTREE),$(SRCTREE)) - rm -rf $(obj)* -endif +mrproper: clean $(mrproper-dirs) + $(call cmd,rmdirs) + $(call cmd,rmfiles) + @rm -f arch/*/include/asm/arch + +# distclean +# +PHONY += distclean + +distclean: mrproper + @find $(srctree) $(RCS_FIND_IGNORE) \ + \( -name '*.orig' -o -name '*.rej' -o -name '*~' \ + -o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \ + -o -name '.*.rej' -o -name '*%' -o -name 'core' \ + -o -name '*.pyc' \) \ + -type f -print | xargs rm -f + @rm -f boards.cfg backup: - F=`basename $(TOPDIR)` ; cd .. ; \ + F=`basename $(srctree)` ; cd .. ; \ gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F -######################################################################### +help: + @echo 'Cleaning targets:' + @echo ' clean - Remove most generated files but keep the config' + @echo ' mrproper - Remove all generated files + config + various backup files' + @echo ' distclean - mrproper + remove editor backup and patch files' + @echo '' + @echo 'Configuration targets:' + @$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help + @echo '' + @echo 'Other generic targets:' + @echo ' all - Build all necessary images depending on configuration' + @echo '* u-boot - Build the bare u-boot' + @echo ' dir/ - Build all files in dir and below' + @echo ' dir/file.[oisS] - Build specified target only' + @echo ' dir/file.lst - Build specified mixed source/assembly target only' + @echo ' (requires a recent binutils and recent build (System.map))' + @echo ' tags/ctags - Generate ctags file for editors' + @echo ' etags - Generate etags file for editors' + @echo ' cscope - Generate cscope index' + @echo ' ubootrelease - Output the release version string (use with make -s)' + @echo ' ubootversion - Output the version stored in Makefile (use with make -s)' + @echo '' + @echo 'Static analysers' + @echo ' checkstack - Generate a list of stack hogs' + @echo '' + @echo 'Documentation targets:' + @$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp + @echo '' + @echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build' + @echo ' make V=2 [targets] 2 => give reason for rebuild of target' + @echo ' make O=dir [targets] Locate all output files in "dir", including .config' + @echo ' make C=1 [targets] Check all c source with $$CHECK (sparse by default)' + @echo ' make C=2 [targets] Force check of all c source with $$CHECK' + @echo ' make RECORDMCOUNT_WARN=1 [targets] Warn about ignored mcount sections' + @echo ' make W=n [targets] Enable extra gcc checks, n=1,2,3 where' + @echo ' 1: warnings which may be relevant and do not occur too often' + @echo ' 2: warnings which occur quite often but may still be relevant' + @echo ' 3: more obscure warnings, can most likely be ignored' + @echo ' Multiple levels can be combined with W=12 or W=123' + @echo '' + @echo 'Execute "make" or "make all" to build all targets marked with [*] ' + @echo 'For further info see the ./README file' + + +# Documentation targets +# --------------------------------------------------------------------------- +%docs: scripts_basic FORCE + $(Q)$(MAKE) $(build)=scripts build_docproc + $(Q)$(MAKE) $(build)=doc/DocBook $@ + +# Dummies... +PHONY += prepare scripts +prepare: ; +scripts: ; + +endif #ifeq ($(config-targets),1) +endif #ifeq ($(mixed-targets),1) + +PHONY += checkstack ubootrelease ubootversion + +checkstack: + $(OBJDUMP) -d u-boot $$(find . -name u-boot-spl) | \ + $(PERL) $(src)/scripts/checkstack.pl $(ARCH) + +ubootrelease: + @echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" + +ubootversion: + @echo $(UBOOTVERSION) + +# Single targets +# --------------------------------------------------------------------------- +# Single targets are compatible with: +# - build with mixed source and output +# - build with separate output dir 'make O=...' +# - external modules +# +# target-dir => where to store outputfile +# build-dir => directory in kernel source tree to use + +ifeq ($(KBUILD_EXTMOD),) + build-dir = $(patsubst %/,%,$(dir $@)) + target-dir = $(dir $@) +else + zap-slash=$(filter-out .,$(patsubst %/,%,$(dir $@))) + build-dir = $(KBUILD_EXTMOD)$(if $(zap-slash),/$(zap-slash)) + target-dir = $(if $(KBUILD_EXTMOD),$(dir $<),$(dir $@)) +endif + +%.s: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.i: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.o: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.lst: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.s: %.S prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.o: %.S prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.symtypes: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) + +# Modules +/: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) +%/: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) +%.ko: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) $(@:.ko=.o) + $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost + +# FIXME Should go into a make.lib or something +# =========================================================================== + +quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs))) + cmd_rmdirs = rm -rf $(rm-dirs) + +quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files))) + cmd_rmfiles = rm -f $(rm-files) + +# read all saved command lines + +targets := $(wildcard $(sort $(targets))) +cmd_files := $(wildcard .*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + $(cmd_files): ; # Do not try to update included dependency files + include $(cmd_files) +endif + +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir +# Usage: +# $(Q)$(MAKE) $(clean)=dir +clean := -f $(srctree)/scripts/Makefile.clean obj + +endif # skip-makefile + +PHONY += FORCE +FORCE: + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable so we can use it in if_changed and friends. +.PHONY: $(PHONY) diff --git a/README b/README index 06c09c5c47..a435c8b2fa 100644 --- a/README +++ b/README @@ -35,7 +35,7 @@ Makefile have been tested to some extent and can be considered "working". In fact, many of them are used in production systems. In case of problems see the CHANGELOG and CREDITS files to find out -who contributed the specific port. The MAINTAINERS file lists board +who contributed the specific port. The boards.cfg file lists board maintainers. Note: There is no CHANGELOG file in the actual U-Boot source tree; @@ -132,6 +132,10 @@ Directory Hierarchy: ==================== /arch Architecture specific files + /arc Files generic to ARC architecture + /cpu CPU specific files + /arc700 Files specific to ARC 700 CPUs + /lib Architecture specific library files /arm Files generic to ARM architecture /cpu CPU specific files /arm720t Files specific to ARM 720 CPUs @@ -139,12 +143,9 @@ Directory Hierarchy: /at91 Files specific to Atmel AT91RM9200 CPU /imx Files specific to Freescale MC9328 i.MX CPUs /s3c24x0 Files specific to Samsung S3C24X0 CPUs - /arm925t Files specific to ARM 925 CPUs /arm926ejs Files specific to ARM 926 CPUs /arm1136 Files specific to ARM 1136 CPUs - /ixp Files specific to Intel XScale IXP CPUs /pxa Files specific to Intel XScale PXA CPUs - /s3c44b0 Files specific to Samsung S3C44B0 CPUs /sa1100 Files specific to Intel StrongARM SA1100 CPUs /lib Architecture specific library files /avr32 Files generic to AVR32 architecture @@ -153,9 +154,6 @@ Directory Hierarchy: /blackfin Files generic to Analog Devices Blackfin architecture /cpu CPU specific files /lib Architecture specific library files - /x86 Files generic to x86 architecture - /cpu CPU specific files - /lib Architecture specific library files /m68k Files generic to m68k architecture /cpu CPU specific files /mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs @@ -170,7 +168,7 @@ Directory Hierarchy: /mips Files generic to MIPS architecture /cpu CPU specific files /mips32 Files specific to MIPS32 CPUs - /xburst Files specific to Ingenic XBurst CPUs + /mips64 Files specific to MIPS64 CPUs /lib Architecture specific library files /nds32 Files generic to NDS32 architecture /cpu CPU specific files @@ -179,13 +177,14 @@ Directory Hierarchy: /nios2 Files generic to Altera NIOS2 architecture /cpu CPU specific files /lib Architecture specific library files + /openrisc Files generic to OpenRISC architecture + /cpu CPU specific files + /lib Architecture specific library files /powerpc Files generic to PowerPC architecture /cpu CPU specific files - /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs /mpc5xx Files specific to Freescale MPC5xx CPUs /mpc5xxx Files specific to Freescale MPC5xxx CPUs /mpc8xx Files specific to Freescale MPC8xx CPUs - /mpc824x Files specific to Freescale MPC824x CPUs /mpc8260 Files specific to Freescale MPC8260 CPUs /mpc85xx Files specific to Freescale MPC85xx CPUs /ppc4xx Files specific to AMCC PowerPC 4xx CPUs @@ -201,12 +200,16 @@ Directory Hierarchy: /leon2 Files specific to Gaisler LEON2 SPARC CPU /leon3 Files specific to Gaisler LEON3 SPARC CPU /lib Architecture specific library files + /x86 Files generic to x86 architecture + /cpu CPU specific files + /lib Architecture specific library files /api Machine/arch independent API for external apps /board Board dependent files /common Misc architecture independent functions /disk Code for disk drive partition handling /doc Documentation (don't expect too much) /drivers Commonly used device drivers +/dts Contains Makefile for building internal U-Boot fdt. /examples Example code for standalone applications, etc. /fs Filesystem code (cramfs, ext2, jffs2, etc.) /include Header Files @@ -216,7 +219,7 @@ Directory Hierarchy: /lzo Library files to support LZO decompression /net Networking code /post Power On Self Test -/rtc Real Time Clock drivers +/spl Secondary Program Loader framework /tools Tools to build S-Record or U-Boot images, etc. Software Configuration: @@ -247,18 +250,29 @@ Selection of Processor Architecture and Board Type: --------------------------------------------------- For all supported boards there are ready-to-use default -configurations available; just type "make _config". +configurations available; just type "make _defconfig". Example: For a TQM823L module type: cd u-boot - make TQM823L_config + make TQM823L_defconfig For the Cogent platform, you need to specify the CPU type as well; -e.g. "make cogent_mpc8xx_config". And also configure the cogent +e.g. "make cogent_mpc8xx_defconfig". And also configure the cogent directory according to the instructions in cogent/README. +Sandbox Environment: +-------------------- + +U-Boot can be built natively to run on a Linux host using the 'sandbox' +board. This allows feature development which is not board- or architecture- +specific to be undertaken on a native platform. The sandbox is also used to +run some of U-Boot's tests. + +See board/sandbox/README.sandbox for more details. + + Configuration Options: ---------------------- @@ -305,23 +319,11 @@ The following options need to be configured: the LCD display every second with a "rotator" |\-/|\-/ -- Board flavour: (if CONFIG_MPC8260ADS is defined) - CONFIG_ADSTYPE - Possible values are: - CONFIG_SYS_8260ADS - original MPC8260ADS - CONFIG_SYS_8266ADS - MPC8266ADS - CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR - CONFIG_SYS_8272ADS - MPC8272ADS - - Marvell Family Member CONFIG_SYS_MVFS - define it if you want to enable multiple fs option at one time for marvell soc family -- MPC824X Family Member (if CONFIG_MPC824X is defined) - Define exactly one of - CONFIG_MPC8240, CONFIG_MPC8245 - - 8xx CPU Options: (if using an MPC8xx CPU) CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if get_gclk_freq() cannot work @@ -399,26 +401,153 @@ The following options need to be configured: CONFIG_A003399_NOR_WORKAROUND Enables a workaround for IFC erratum A003399. It is only - requred during NOR boot. + required during NOR boot. + + CONFIG_A008044_WORKAROUND + Enables a workaround for T1040/T1042 erratum A008044. It is only + required during NAND boot and valid for Rev 1.0 SoC revision CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. + CONFIG_SYS_FSL_DSP_DDR_ADDR + This value denotes start offset of DDR memory which is + connected exclusively to the DSP cores. + CONFIG_SYS_FSL_DSP_M2_RAM_ADDR This value denotes start offset of M2 memory which is directly connected to the DSP core. + CONFIG_SYS_FSL_DSP_M3_RAM_ADDR + This value denotes start offset of M3 memory which is directly + connected to the DSP core. + CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. + CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + Single Source Clock is clocking mode present in some of FSL SoC's. + In this mode, a single differential clock is used to supply + clocks to the sysclock, ddrclock and usbclock. + + CONFIG_SYS_CPC_REINIT_F + This CONFIG is defined when the CPC is configured as SRAM at the + time of U-boot entry and is required to be re-initialized. + + CONFIG_DEEP_SLEEP + Indicates this SoC supports deep sleep feature. If deep sleep is + supported, core will start to execute uboot when wakes up. + - Generic CPU options: + CONFIG_SYS_GENERIC_GLOBAL_DATA + Defines global data is initialized in generic board board_init_f(). + If this macro is defined, global data is created and cleared in + generic board board_init_f(). Without this macro, architecture/board + should initialize global data before calling board_init_f(). + CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN Defines the endianess of the CPU. Implementation of those values is arch specific. + CONFIG_SYS_FSL_DDR + Freescale DDR driver in use. This type of DDR controller is + found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core + SoCs. + + CONFIG_SYS_FSL_DDR_ADDR + Freescale DDR memory-mapped register base. + + CONFIG_SYS_FSL_DDR_EMU + Specify emulator support for DDR. Some DDR features such as + deskew training are not available. + + CONFIG_SYS_FSL_DDRC_GEN1 + Freescale DDR1 controller. + + CONFIG_SYS_FSL_DDRC_GEN2 + Freescale DDR2 controller. + + CONFIG_SYS_FSL_DDRC_GEN3 + Freescale DDR3 controller. + + CONFIG_SYS_FSL_DDRC_GEN4 + Freescale DDR4 controller. + + CONFIG_SYS_FSL_DDRC_ARM_GEN3 + Freescale DDR3 controller for ARM-based SoCs. + + CONFIG_SYS_FSL_DDR1 + Board config to use DDR1. It can be enabled for SoCs with + Freescale DDR1 or DDR2 controllers, depending on the board + implemetation. + + CONFIG_SYS_FSL_DDR2 + Board config to use DDR2. It can be eanbeld for SoCs with + Freescale DDR2 or DDR3 controllers, depending on the board + implementation. + + CONFIG_SYS_FSL_DDR3 + Board config to use DDR3. It can be enabled for SoCs with + Freescale DDR3 or DDR3L controllers. + + CONFIG_SYS_FSL_DDR3L + Board config to use DDR3L. It can be enabled for SoCs with + DDR3L controllers. + + CONFIG_SYS_FSL_DDR4 + Board config to use DDR4. It can be enabled for SoCs with + DDR4 controllers. + + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + + CONFIG_SYS_FSL_IFC_LE + Defines the IFC controller register space as Little Endian + + CONFIG_SYS_FSL_PBL_PBI + It enables addition of RCW (Power on reset configuration) in built image. + Please refer doc/README.pblimage for more details + + CONFIG_SYS_FSL_PBL_RCW + It adds PBI(pre-boot instructions) commands in u-boot build image. + PBI commands can be used to configure SoC before it starts the execution. + Please refer doc/README.pblimage for more details + + CONFIG_SPL_FSL_PBL + It adds a target to create boot binary having SPL binary in PBI format + concatenated with u-boot binary. + + CONFIG_SYS_FSL_DDR_BE + Defines the DDR controller register space as Big Endian + + CONFIG_SYS_FSL_DDR_LE + Defines the DDR controller register space as Little Endian + + CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY + Physical address from the view of DDR controllers. It is the + same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + it could be different for ARM SoCs. + + CONFIG_SYS_FSL_DDR_INTLV_256B + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape + SoCs with ARM core. + + CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS + Number of controllers used as main memory. + + CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS + Number of controllers used for other than main memory. + + CONFIG_SYS_FSL_SEC_BE + Defines the SEC controller register space as Big Endian + + CONFIG_SYS_FSL_SEC_LE + Defines the SEC controller register space as Little Endian + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO @@ -483,6 +612,8 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 + CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the @@ -490,12 +621,119 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply! -- CPU timer options: - CONFIG_SYS_HZ +- Driver Model + Driver model is a new framework for devices in U-Boot + introduced in early 2014. U-Boot is being progressively + moved over to this. It offers a consistent device structure, + supports grouping devices into classes and has built-in + handling of platform data and device tree. + + To enable transition to driver model in a relatively + painful fashion, each subsystem can be independently + switched between the legacy/ad-hoc approach and the new + driver model using the options below. Also, many uclass + interfaces include compatibility features which may be + removed once the conversion of that subsystem is complete. + As a result, the API provided by the subsystem may in fact + not change with driver model. + + See doc/driver-model/README.txt for more information. + + CONFIG_DM + + Enable driver model. This brings in the core support, + including scanning of platform data on start-up. If + CONFIG_OF_CONTROL is enabled, the device tree will be + scanned also when available. + + CONFIG_CMD_DM + + Enable driver model test commands. These allow you to print + out the driver model tree and the uclasses. + + CONFIG_DM_DEMO + + Enable some demo devices and the 'demo' command. These are + really only useful for playing around while trying to + understand driver model in sandbox. + + CONFIG_SPL_DM + + Enable driver model in SPL. You will need to provide a + suitable malloc() implementation. If you are not using the + full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you + must provide CONFIG_SYS_MALLOC_F_LEN to set the size. + In most cases driver model will only allocate a few uclasses + and devices in SPL, so 1KB should be enable. See + CONFIG_SYS_MALLOC_F_LEN for more details on how to enable + it. + + CONFIG_DM_SERIAL + + Enable driver model for serial. This replaces + drivers/serial/serial.c with the serial uclass, which + implements serial_putc() etc. The uclass interface is + defined in include/serial.h. + + CONFIG_DM_GPIO + + Enable driver model for GPIO access. The standard GPIO + interface (gpio_get_value(), etc.) is then implemented by + the GPIO uclass. Drivers provide methods to query the + particular GPIOs that they provide. The uclass interface + is defined in include/asm-generic/gpio.h. + + CONFIG_DM_SPI + + Enable driver model for SPI. The SPI slave interface + (spi_setup_slave(), spi_xfer(), etc.) is then implemented by + the SPI uclass. Drivers provide methods to access the SPI + buses that they control. The uclass interface is defined in + include/spi.h. The existing spi_slave structure is attached + as 'parent data' to every slave on each bus. Slaves + typically use driver-private data instead of extending the + spi_slave structure. + + CONFIG_DM_SPI_FLASH + + Enable driver model for SPI flash. This SPI flash interface + (spi_flash_probe(), spi_flash_write(), etc.) is then + implemented by the SPI flash uclass. There is one standard + SPI flash driver which knows how to probe most chips + supported by U-Boot. The uclass interface is defined in + include/spi_flash.h, but is currently fully compatible + with the old interface to avoid confusion and duplication + during the transition parent. SPI and SPI flash must be + enabled together (it is not possible to use driver model + for one and not the other). + + CONFIG_DM_CROS_EC + + Enable driver model for the Chrome OS EC interface. This + allows the cros_ec SPI driver to operate with CONFIG_DM_SPI + but otherwise makes few changes. Since cros_ec also supports + I2C and LPC (which don't support driver model yet), a full + conversion is not yet possible. + + + ** Code size options: The following options are enabled by + default except in SPL. Enable them explicitly to get these + features in SPL. + + CONFIG_DM_WARN + + Enable the dm_warn() function. This can use up quite a bit + of space for its strings. + + CONFIG_DM_STDIO + + Enable registering a serial device with the stdio library. + + CONFIG_DM_DEVICE_REMOVE + + Enable removing of devices. - The frequency of the timer returned by get_timer(). - get_timer() must operate in milliseconds and this CONFIG - option must be set to 1000. - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ @@ -513,7 +751,7 @@ The following options need to be configured: CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] - When transferring memsize parameter to linux, some versions + When transferring memsize parameter to Linux, some versions expect it to be in bytes, others in MB. Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. @@ -543,6 +781,13 @@ The following options need to be configured: Board code has addition modification that it wants to make to the flat device tree before handing it off to the kernel + CONFIG_OF_SYSTEM_SETUP + + Other code has addition modification that it wants to make + to the flat device tree before handing it off to the kernel. + This causes ft_system_setup() to be called before booting + the kernel. + CONFIG_OF_BOOT_CPU This define fills in the correct boot CPU in the boot @@ -628,6 +873,10 @@ The following options need to be configured: boot loader that has already initialized the UART. Define this variable to flush the UART at init time. + CONFIG_SERIAL_HW_FLOW_CONTROL + + Define this variable to enable hw flow control in serial driver. + Current user of this option is drivers/serial/nsl16550.c driver - Console Interface: Depending on board, define exactly one serial port @@ -691,6 +940,11 @@ The following options need to be configured: the "silent" environment variable. See doc/README.silent for more information. + CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default + is 0x00. + CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default + is 0xa0. + - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in @@ -765,6 +1019,22 @@ The following options need to be configured: as a convenience, when switching between booting from RAM and NFS. +- Bootcount: + CONFIG_BOOTCOUNT_LIMIT + Implements a mechanism for detecting a repeating reboot + cycle, see: + http://www.denx.de/wiki/view/DULG/UBootBootCountLimit + + CONFIG_BOOTCOUNT_ENV + If no softreset save registers are found on the hardware + "bootcount" is stored in the environment. To prevent a + saveenv on all reboots, the environment variable + "upgrade_available" is used. If "upgrade_available" is + 0, "bootcount" is always 0, if "upgrade_available" is + 1 "bootcount" is incremented in the environment. + So the Userspace Applikation must set the "upgrade_available" + and "bootcount" variable to 0, if a boot was successfully. + - Pre-Boot Commands: CONFIG_PREBOOT @@ -806,13 +1076,16 @@ The following options need to be configured: The default command configuration includes all commands except those marked below with a "*". + CONFIG_CMD_AES AES 128 CBC encrypt/decrypt CONFIG_CMD_ASKENV * ask for env variable CONFIG_CMD_BDI bdinfo CONFIG_CMD_BEDBUG * Include BedBug Debugger CONFIG_CMD_BMP * BMP support CONFIG_CMD_BSP * Board specific commands CONFIG_CMD_BOOTD bootd + CONFIG_CMD_BOOTI * ARM64 Linux kernel Image support CONFIG_CMD_CACHE * icache, dcache + CONFIG_CMD_CLK * clock command support CONFIG_CMD_CONSOLE coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for RTC, date/time... @@ -829,13 +1102,16 @@ The following options need to be configured: CONFIG_CMD_ELF * bootelf, bootvx CONFIG_CMD_ENV_CALLBACK * display details about env callbacks CONFIG_CMD_ENV_FLAGS * display details about env flags + CONFIG_CMD_ENV_EXISTS * check existence of env variable CONFIG_CMD_EXPORTENV * export the environment CONFIG_CMD_EXT2 * ext2 command support CONFIG_CMD_EXT4 * ext4 command support + CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls) + that work for multiple fs types + CONFIG_CMD_FS_UUID * Look up a filesystem UUID CONFIG_CMD_SAVEENV saveenv CONFIG_CMD_FDC * Floppy Disk Support CONFIG_CMD_FAT * FAT command support - CONFIG_CMD_FDOS * Dos diskette Support CONFIG_CMD_FLASH flinfo, erase, protect CONFIG_CMD_FPGA FPGA device initialization support CONFIG_CMD_FUSE * Device fuse support @@ -850,6 +1126,7 @@ The following options need to be configured: CONFIG_CMD_IMLS List all images found in NOR flash CONFIG_CMD_IMLS_NAND * List all images found in NAND flash CONFIG_CMD_IMMAP * IMMR dump support + CONFIG_CMD_IOTRACE * I/O tracing for debugging CONFIG_CMD_IMPORTENV * import an environment CONFIG_CMD_INI * import data from an ini file into the env CONFIG_CMD_IRQ * irqinfo @@ -905,7 +1182,7 @@ The following options need to be configured: CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_MFSL * Microblaze FSL support CONFIG_CMD_XIMG Load part of Multi Image - + CONFIG_CMD_UUID * Generate random UUID or GUID string EXAMPLE: If you want all functions except of network support you can write: @@ -930,10 +1207,10 @@ The following options need to be configured: - Regular expression support: CONFIG_REGEX - If this variable is defined, U-Boot is linked against - the SLRE (Super Light Regular Expression) library, - which adds regex support to some commands, as for - example "env grep" and "setexpr". + If this variable is defined, U-Boot is linked against + the SLRE (Super Light Regular Expression) library, + which adds regex support to some commands, as for + example "env grep" and "setexpr". - Device tree: CONFIG_OF_CONTROL @@ -1001,6 +1278,7 @@ The following options need to be configured: CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC + CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC @@ -1013,7 +1291,6 @@ The following options need to be configured: - GPIO Support: CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO - CONFIG_PCA953X_INFO - enable pca953x info command The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of @@ -1022,6 +1299,28 @@ The following options need to be configured: Note that if the GPIO device uses I2C, then the I2C interface must also be configured. See I2C Support, below. +- I/O tracing: + When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O + accesses and can checksum them or write a list of them out + to memory. See the 'iotrace' command for details. This is + useful for testing device drivers since it can confirm that + the driver behaves the same way before and after a code + change. Currently this is supported on sandbox and arm. To + add support for your architecture, add '#include ' + to the bottom of arch//include/asm/io.h and test. + + Example output from the 'iotrace stats' command is below. + Note that if the trace buffer is exhausted, the checksum will + still continue to operate. + + iotrace is enabled + Start: 10000000 (buffer start address) + Size: 00010000 (buffer size) + Offset: 00000120 (current buffer offset) + Output: 10000120 (start + offset) + Count: 00000018 (number of trace records) + CRC32: 9526fb66 (CRC32 of all trace records) + - Timestamp Support: When CONFIG_TIMESTAMP is selected, the timestamp @@ -1082,8 +1381,8 @@ The following options need to be configured: devices. CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) - The environment variable 'scsidevs' is set to the number of - SCSI devices found during the last scan. + The environment variable 'scsidevs' is set to the number of + SCSI devices found during the last scan. - NETWORK Support (PCI): CONFIG_E1000 @@ -1205,6 +1504,10 @@ The following options need to be configured: CONFIG_SH_ETHER_CACHE_WRITEBACK If this option is set, the driver enables cache flush. +- PWM Support: + CONFIG_PWM_IMX + Support for PWM modul on the imx6. + - TPM Support: CONFIG_TPM Support TPM devices. @@ -1275,8 +1578,8 @@ The following options need to be configured: CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset. - CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum - interval for usb hub power-on delay.(minimum 100msec) + CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2 + HW module registers. - USB Device: Define the below if you wish to use the USB console. @@ -1377,6 +1680,16 @@ The following options need to be configured: CONFIG_SH_MMCIF_CLK Define the clock frequency for MMCIF + CONFIG_GENERIC_MMC + Enable the generic MMC driver + + CONFIG_SUPPORT_EMMC_BOOT + Enable some additional features of the eMMC boot partitions. + + CONFIG_SUPPORT_EMMC_RPMB + Enable the commands for reading, writing and programming the + key for the Replay Protection Memory Block partition in eMMC. + - USB Device Firmware Update (DFU) class support: CONFIG_DFU_FUNCTION This enables the USB portion of the DFU USB class @@ -1393,6 +1706,12 @@ The following options need to be configured: CONFIG_DFU_NAND This enables support for exposing NAND devices via DFU. + CONFIG_DFU_RAM + This enables support for exposing RAM via DFU. + Note: DFU spec refer to non-volatile memory usage, but + allow usages beyond the scope of spec - here RAM usage, + one that would help mostly the developer. + CONFIG_SYS_DFU_DATA_BUF_SIZE Dfu transfer uses a buffer before writing data to the raw storage device. Make the size (in bytes) of this buffer @@ -1406,6 +1725,57 @@ The following options need to be configured: this to the maximum filesize (in bytes) for the buffer. Default is 4 MiB if undefined. + DFU_DEFAULT_POLL_TIMEOUT + Poll timeout [ms], is the timeout a device can send to the + host. The host must wait for this timeout before sending + a subsequent DFU_GET_STATUS request to the device. + + DFU_MANIFEST_POLL_TIMEOUT + Poll timeout [ms], which the device sends to the host when + entering dfuMANIFEST state. Host waits this timeout, before + sending again an USB request to the device. + +- USB Device Android Fastboot support: + CONFIG_CMD_FASTBOOT + This enables the command "fastboot" which enables the Android + fastboot mode for the platform's USB device. Fastboot is a USB + protocol for downloading images, flashing and device control + used on Android devices. + See doc/README.android-fastboot for more information. + + CONFIG_ANDROID_BOOT_IMAGE + This enables support for booting images which use the Android + image format header. + + CONFIG_USB_FASTBOOT_BUF_ADDR + The fastboot protocol requires a large memory buffer for + downloads. Define this to the starting RAM address to use for + downloaded images. + + CONFIG_USB_FASTBOOT_BUF_SIZE + The fastboot protocol requires a large memory buffer for + downloads. This buffer should be as large as possible for a + platform. Define this to the size available RAM for fastboot. + + CONFIG_FASTBOOT_FLASH + The fastboot protocol includes a "flash" command for writing + the downloaded image to a non-volatile storage device. Define + this to enable the "fastboot flash" command. + + CONFIG_FASTBOOT_FLASH_MMC_DEV + The fastboot "flash" command requires additional information + regarding the non-volatile storage device. Define this to + the eMMC device that fastboot should use to store the image. + + CONFIG_FASTBOOT_GPT_NAME + The fastboot "flash" command supports writing the downloaded + image to the Protective MBR and the Primary GUID Partition + Table. (Additionally, this downloaded image is post-processed + to generate and write the Backup GUID Partition Table.) + This occurs when the specified "partition name" on the + "fastboot flash" command line matches this value. + Default is GPT_ENTRY_NAME (currently "gpt") if undefined. + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV @@ -1440,6 +1810,12 @@ CBFS (Coreboot Filesystem) support filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls and cbfsload. +- FAT(File Allocation Table) filesystem cluster size: + CONFIG_FS_FAT_MAX_CLUSTSIZE + + Define the max cluster size for fat operations else + a default value of 65536 will be defined. + - Keyboard Support: CONFIG_ISA_KEYBOARD @@ -1585,7 +1961,7 @@ CBFS (Coreboot Filesystem) support CONFIG_LCD_ALIGNMENT - Normally the LCD is page-aligned (tyically 4KB). If this is + Normally the LCD is page-aligned (typically 4KB). If this is defined then the LCD will be aligned to this value instead. For ARM it is sometimes useful to use MMU_SECTION_SIZE here, since it is cheaper to change data cache settings on @@ -1622,7 +1998,7 @@ CBFS (Coreboot Filesystem) support If this option is set, then U-Boot will prevent the environment variable "splashimage" from being set to a problematic address - (see README.displaying-bmps and README.arm-unaligned-accesses). + (see README.displaying-bmps). This option is useful for targets where, due to alignment restrictions, an improperly aligned BMP image will cause a data abort. If you think you will not have problems with unaligned @@ -1661,13 +2037,17 @@ CBFS (Coreboot Filesystem) support can be displayed via the splashscreen support or the bmp command. -- Do compresssing for memory range: +- Do compressing for memory range: CONFIG_CMD_ZIP If this option is set, it would use zlib deflate method to compress the specified memory at its best effort. - Compression support: + CONFIG_GZIP + + Enabled by default to support gzip compressed images. + CONFIG_BZIP2 If this option is set, support for bzip2 compressed @@ -1701,6 +2081,11 @@ CBFS (Coreboot Filesystem) support then calculate the amount of needed dynamic memory (ensuring the appropriate CONFIG_SYS_MALLOC_LEN value). + CONFIG_LZO + + If this option is set, support for LZO compressed images + is included. + - MII/PHY support: CONFIG_PHY_ADDR @@ -1804,6 +2189,24 @@ CBFS (Coreboot Filesystem) support 4th and following BOOTP requests: delay 0 ... 8 sec + CONFIG_BOOTP_ID_CACHE_SIZE + + BOOTP packets are uniquely identified using a 32-bit ID. The + server will copy the ID from client requests to responses and + U-Boot will use this to determine if it is the destination of + an incoming response. Some servers will check that addresses + aren't in use before handing them out (usually using an ARP + ping) and therefore take up to a few hundred milliseconds to + respond. Network congestion may also influence the time it + takes for a response to make it back to the client. If that + time is too long, U-Boot will retransmit requests. In order + to allow earlier responses to still be accepted after these + retransmissions, U-Boot's BOOTP client keeps a small cache of + IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this + cache. The default is to keep IDs for up to four outstanding + requests. Increasing this will allow U-Boot to accept offers + from a BOOTP client in networks with unusually high latency. + - BOOTP Random transaction ID: CONFIG_BOOTP_RANDOM_ID @@ -1933,6 +2336,21 @@ CBFS (Coreboot Filesystem) support kernel). Defining CONFIG_STATUS_LED enables this feature in U-Boot. + Additional options: + + CONFIG_GPIO_LED + The status LED can be connected to a GPIO pin. + In such cases, the gpio_led driver can be used as a + status LED backend implementation. Define CONFIG_GPIO_LED + to include the gpio_led driver in the U-Boot binary. + + CONFIG_GPIO_LED_INVERTED_TABLE + Some GPIO connected LEDs may have inverted polarity in which + case the GPIO high value corresponds to LED off state and + GPIO low value corresponds to LED on state. + In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined + with a list of GPIO LEDs that have inverted polarity. + - CAN Support: CONFIG_CAN_DRIVER Defining CONFIG_CAN_DRIVER enables CAN driver support @@ -1969,26 +2387,108 @@ CBFS (Coreboot Filesystem) support offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first bus. - - If your board supports a second fsl i2c bus, define + - If your board supports a second fsl i2c bus, define CONFIG_SYS_FSL_I2C2_OFFSET for the register offset CONFIG_SYS_FSL_I2C2_SPEED for the speed and CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the second bus. - drivers/i2c/tegra_i2c.c: - - activate this driver with CONFIG_SYS_I2C_TEGRA - - This driver adds 4 i2c buses with a fix speed from - 100000 and the slave addr 0! + - activate this driver with CONFIG_SYS_I2C_TEGRA + - This driver adds 4 i2c buses with a fix speed from + 100000 and the slave addr 0! - drivers/i2c/ppc4xx_i2c.c - activate this driver with CONFIG_SYS_I2C_PPC4XX - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0 - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1 + - drivers/i2c/i2c_mxc.c + - activate this driver with CONFIG_SYS_I2C_MXC + - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED + - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE + - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED + - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE + - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED + - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE + If those defines are not set, default value is 100000 + for speed, and 0 for slave. + + - drivers/i2c/rcar_i2c.c: + - activate this driver with CONFIG_SYS_I2C_RCAR + - This driver adds 4 i2c buses + + - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0 + - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0 + - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1 + - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1 + - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2 + - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2 + - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3 + - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3 + - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses + + - drivers/i2c/sh_i2c.c: + - activate this driver with CONFIG_SYS_I2C_SH + - This driver adds from 2 to 5 i2c buses + + - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0 + - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0 + - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1 + - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1 + - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2 + - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2 + - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3 + - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 + - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 + - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 + - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5 + - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 + - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses + + - drivers/i2c/omap24xx_i2c.c + - activate this driver with CONFIG_SYS_I2C_OMAP24XX + - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0 + - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0 + - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1 + - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1 + - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2 + - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2 + - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3 + - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3 + - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 + - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 + + - drivers/i2c/zynq_i2c.c + - activate this driver with CONFIG_SYS_I2C_ZYNQ + - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting + - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr + + - drivers/i2c/s3c24x0_i2c.c: + - activate this driver with CONFIG_SYS_I2C_S3C24X0 + - This driver adds i2c buses (11 for Exynos5250, Exynos5420 + 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung) + with a fix speed from 100000 and the slave addr 0! + + - drivers/i2c/ihs_i2c.c + - activate this driver with CONFIG_SYS_I2C_IHS + - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0 + - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0 + - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0 + - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1 + - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1 + - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1 + - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2 + - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2 + - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2 + - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3 + - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3 + - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3 + additional defines: CONFIG_SYS_NUM_I2C_BUSES - Hold the number of i2c busses you want to use. If you + Hold the number of i2c buses you want to use. If you don't use/have i2c muxes on your i2c bus, this is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can omit this define. @@ -2004,7 +2504,7 @@ CBFS (Coreboot Filesystem) support define. CONFIG_SYS_I2C_BUSES - hold a list of busses you want to use, only used if + hold a list of buses you want to use, only used if CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and CONFIG_SYS_NUM_I2C_BUSES = 9: @@ -2279,6 +2779,10 @@ CBFS (Coreboot Filesystem) support Enables the driver for the SPI controllers on i.MX and MXC SoCs. Currently i.MX31/35/51 are supported. + CONFIG_SYS_SPI_MXC_WAIT + Timeout for waiting until spi transfer completed. + default: (CONFIG_SYS_HZ/100) /* 10 ms */ + - FPGA Support: CONFIG_FPGA Enables FPGA subsystem. @@ -2297,6 +2801,19 @@ CBFS (Coreboot Filesystem) support Specify the number of FPGA devices to support. + CONFIG_CMD_FPGA_LOADMK + + Enable support for fpga loadmk command + + CONFIG_CMD_FPGA_LOADP + + Enable support for fpga loadp command - load partial bitstream + + CONFIG_CMD_FPGA_LOADBP + + Enable support for fpga loadbp command - load partial bitstream + (Xilinx only) + CONFIG_SYS_FPGA_PROG_FEEDBACK Enable printing of hash marks during FPGA configuration. @@ -2325,14 +2842,14 @@ CBFS (Coreboot Filesystem) support CONFIG_SYS_FPGA_WAIT_INIT - Maximum time to wait for the INIT_B line to deassert - after PROB_B has been deasserted during a Virtex II + Maximum time to wait for the INIT_B line to de-assert + after PROB_B has been de-asserted during a Virtex II FPGA configuration sequence. The default time is 500 ms. CONFIG_SYS_FPGA_WAIT_BUSY - Maximum time to wait for BUSY to deassert during + Maximum time to wait for BUSY to de-assert during Virtex II FPGA configuration. The default is 5 ms. CONFIG_SYS_FPGA_WAIT_CONFIG @@ -2341,6 +2858,14 @@ CBFS (Coreboot Filesystem) support 200 ms. - Configuration Management: + CONFIG_BUILD_TARGET + + Some SoCs need special image types (e.g. U-Boot binary + with a special header) as build targets. By defining + CONFIG_BUILD_TARGET in the SoC / board header, this + special image will be automatically built upon calling + make / MAKEALL. + CONFIG_IDENT_STRING If defined, this string will be added to the U-Boot @@ -2449,22 +2974,6 @@ CBFS (Coreboot Filesystem) support Enable auto completion of commands using TAB. - Note that this feature has NOT been implemented yet - for the "hush" shell. - - - CONFIG_SYS_HUSH_PARSER - - Define this variable to enable the "hush" shell (from - Busybox) as command line interpreter, thus enabling - powerful command line syntax like - if...then...else...fi conditionals or `&&' and '||' - constructs ("shell scripts"). - - If undefined, you get the old, much simpler behaviour - with a somewhat smaller memory footprint. - - CONFIG_SYS_PROMPT_HUSH_PS2 This defines the secondary prompt string, which is @@ -2492,11 +3001,11 @@ CBFS (Coreboot Filesystem) support of the backslashes before semicolons and special symbols. -- Commandline Editing and History: +- Command Line Editing and History: CONFIG_CMDLINE_EDITING Enable editing and History functions for interactive - commandline input operations + command line input operations - Default Environment: CONFIG_EXTRA_ENV_SETTINGS @@ -2547,7 +3056,7 @@ CBFS (Coreboot Filesystem) support CONFIG_DELAY_ENVIRONMENT Normally the environment is loaded when the board is - intialised so that it is available to U-Boot. This inhibits + initialised so that it is available to U-Boot. This inhibits that so that the environment is not available until explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL this is instead controlled by the value of @@ -2589,6 +3098,23 @@ CBFS (Coreboot Filesystem) support Define this option to use the Bank addr/Extended addr support on SPI flashes which has size > 16Mbytes. + CONFIG_SF_DUAL_FLASH Dual flash memories + + Define this option to use dual flash support where two flash + memories can be connected with a given cs line. + Currently Xilinx Zynq qspi supports these type of connections. + + CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + enable the W#/Vpp signal to disable writing to the status + register on ST MICRON flashes like the N25Q128. + The status register write enable/disable bit, combined with + the W#/VPP signal provides hardware data protection for the + device as follows: When the enable/disable bit is set to 1, + and the W#/VPP signal is driven LOW, the status register + nonvolatile bits become read-only and the WRITE STATUS REGISTER + operation will not execute. The only way to exit this + hardware-protected mode is to drive W#/VPP HIGH. + - SystemACE Support: CONFIG_SYSTEMACE @@ -2640,15 +3166,55 @@ CBFS (Coreboot Filesystem) support Note: There is also a sha1sum command, which should perhaps be deprecated in favour of 'hash sha1'. +- Freescale i.MX specific commands: + CONFIG_CMD_HDMIDETECT + This enables 'hdmidet' command which returns true if an + HDMI monitor is detected. This command is i.MX 6 specific. + + CONFIG_CMD_BMODE + This enables the 'bmode' (bootmode) command for forcing + a boot from specific media. + + This is useful for forcing the ROM's usb downloader to + activate upon a watchdog reset which is nice when iterating + on U-Boot. Using the reset button or running bmode normal + will set it back to normal. This command currently + supports i.MX53 and i.MX6. + - Signing support: CONFIG_RSA This enables the RSA algorithm used for FIT image verification - in U-Boot. See doc/uImage/signature for more information. + in U-Boot. See doc/uImage.FIT/signature.txt for more information. - The signing part is build into mkimage regardless of this - option. + The Modular Exponentiation algorithm in RSA is implemented using + driver model. So CONFIG_DM needs to be enabled by default for this + library to function. + The signing part is build into mkimage regardless of this + option. The software based modular exponentiation is built into + mkimage irrespective of this option. + +- bootcount support: + CONFIG_BOOTCOUNT_LIMIT + + This enables the bootcounter support, see: + http://www.denx.de/wiki/DULG/UBootBootCountLimit + + CONFIG_AT91SAM9XE + enable special bootcounter support on at91sam9xe based boards. + CONFIG_BLACKFIN + enable special bootcounter support on blackfin based boards. + CONFIG_SOC_DA8XX + enable special bootcounter support on da850 based boards. + CONFIG_BOOTCOUNT_RAM + enable support for the bootcounter in RAM + CONFIG_BOOTCOUNT_I2C + enable support for the bootcounter on an i2c (like RTC) device. + CONFIG_SYS_I2C_RTC_ADDR = i2c chip address + CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for + the bootcounter. + CONFIG_BOOTCOUNT_ALEN = address len - Show boot progress: CONFIG_SHOW_BOOT_PROGRESS @@ -2863,6 +3429,19 @@ FIT uImage format: -150 common/cmd_nand.c Incorrect FIT image format 151 common/cmd_nand.c FIT image format OK +- legacy image format: + CONFIG_IMAGE_FORMAT_LEGACY + enables the legacy image format support in U-Boot. + + Default: + enabled if CONFIG_FIT_SIGNATURE is not defined. + + CONFIG_DISABLE_IMAGE_LEGACY + disable the legacy image format + + This define is introduced, as the legacy image format is + enabled per default for backward compatibility. + - FIT image support: CONFIG_FIT Enable support for the FIT uImage format. @@ -2879,6 +3458,16 @@ FIT uImage format: using a hash signed and verified using RSA. See doc/uImage.FIT/signature.txt for more details. + WARNING: When relying on signed FIT images with required + signature check the legacy image format is default + disabled. If a board need legacy image format support + enable this through CONFIG_IMAGE_FORMAT_LEGACY + + CONFIG_FIT_DISABLE_SHA256 + Supporting SHA256 hashes has quite an impact on binary size. + For constrained systems sha256 hash support can be disabled + with this option. + - Standalone program support: CONFIG_STANDALONE_LOAD_ADDR @@ -2920,6 +3509,9 @@ FIT uImage format: Adds the MTD partitioning infrastructure from the Linux kernel. Needed for UBI support. + CONFIG_MTD_NAND_VERIFY_WRITE + verify if the written data is correct reread. + - UBI support CONFIG_CMD_UBI @@ -2933,6 +3525,64 @@ FIT uImage format: Make the verbose messages from UBI stop printing. This leaves warnings and errors enabled. + + CONFIG_MTD_UBI_WL_THRESHOLD + This parameter defines the maximum difference between the highest + erase counter value and the lowest erase counter value of eraseblocks + of UBI devices. When this threshold is exceeded, UBI starts performing + wear leveling by means of moving data from eraseblock with low erase + counter to eraseblocks with high erase counter. + + The default value should be OK for SLC NAND flashes, NOR flashes and + other flashes which have eraseblock life-cycle 100000 or more. + However, in case of MLC NAND flashes which typically have eraseblock + life-cycle less than 10000, the threshold should be lessened (e.g., + to 128 or 256, although it does not have to be power of 2). + + default: 4096 + + CONFIG_MTD_UBI_BEB_LIMIT + This option specifies the maximum bad physical eraseblocks UBI + expects on the MTD device (per 1024 eraseblocks). If the + underlying flash does not admit of bad eraseblocks (e.g. NOR + flash), this value is ignored. + + NAND datasheets often specify the minimum and maximum NVM + (Number of Valid Blocks) for the flashes' endurance lifetime. + The maximum expected bad eraseblocks per 1024 eraseblocks + then can be calculated as "1024 * (1 - MinNVB / MaxNVB)", + which gives 20 for most NANDs (MaxNVB is basically the total + count of eraseblocks on the chip). + + To put it differently, if this value is 20, UBI will try to + reserve about 1.9% of physical eraseblocks for bad blocks + handling. And that will be 1.9% of eraseblocks on the entire + NAND chip, not just the MTD partition UBI attaches. This means + that if you have, say, a NAND flash chip admits maximum 40 bad + eraseblocks, and it is split on two MTD partitions of the same + size, UBI will reserve 40 eraseblocks when attaching a + partition. + + default: 20 + + CONFIG_MTD_UBI_FASTMAP + Fastmap is a mechanism which allows attaching an UBI device + in nearly constant time. Instead of scanning the whole MTD device it + only has to locate a checkpoint (called fastmap) on the device. + The on-flash fastmap contains all information needed to attach + the device. Using fastmap makes only sense on large devices where + attaching by scanning takes long. UBI will not automatically install + a fastmap on old images, but you can set the UBI parameter + CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT to 1 if you want so. Please note + that fastmap-enabled images are still usable with UBI implementations + without fastmap support. On typical flash devices the whole fastmap + fits into one PEB. UBI will reserve PEBs to hold two fastmaps. + + CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT + Set this parameter to enable fastmap automatically on images + without a fastmap. + default: 0 + - UBIFS support CONFIG_CMD_UBIFS @@ -3002,6 +3652,10 @@ FIT uImage format: supports MMC, NAND and YMODEM loading of U-Boot and NAND NAND loading of the Linux Kernel. + CONFIG_SPL_OS_BOOT + Enable booting directly to an OS from SPL. + See also: doc/README.falcon + CONFIG_SPL_DISPLAY_PRINT For ARM, enable an optional function to print more information about the running system. @@ -3026,10 +3680,13 @@ FIT uImage format: CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS, - CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION - Address, size and partition on the MMC to load U-Boot from + Address and partition on the MMC to load U-Boot from when the MMC is being used in raw mode. + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION + Partition on the MMC to load U-Boot from when the MMC is being + used in raw mode + CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR Sector to load kernel uImage from when MMC is being used in raw mode (for Falcon mode) @@ -3040,19 +3697,26 @@ FIT uImage format: parameters from when MMC is being used in raw mode (for falcon mode) + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION + Partition on the MMC to load U-Boot from when the MMC is being + used in fs mode + CONFIG_SPL_FAT_SUPPORT Support for fs/fat/libfat.o in SPL binary - CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME - Filename to read to load U-Boot when reading from FAT + CONFIG_SPL_EXT_SUPPORT + Support for EXT filesystem in SPL binary + + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME + Filename to read to load U-Boot when reading from filesystem - CONFIG_SPL_FAT_LOAD_KERNEL_NAME + CONFIG_SPL_FS_LOAD_KERNEL_NAME Filename to read to load kernel uImage when reading - from FAT (for Falcon mode) + from filesystem (for Falcon mode) - CONFIG_SPL_FAT_LOAD_ARGS_NAME + CONFIG_SPL_FS_LOAD_ARGS_NAME Filename to read to load kernel argument parameters - when reading from FAT (for Falcon mode) + when reading from filesystem (for Falcon mode) CONFIG_SPL_MPC83XX_WAIT_FOR_NAND Set this for NAND SPL on PPC mpc83xx targets, so that @@ -3060,6 +3724,9 @@ FIT uImage format: continuing (the hardware starts execution after just loading the first page rather than the full 4K). + CONFIG_SPL_SKIP_RELOCATE + Avoid SPL relocation + CONFIG_SPL_NAND_BASE Include nand_base.c in the SPL. Requires CONFIG_SPL_NAND_DRIVERS. @@ -3074,6 +3741,22 @@ FIT uImage format: Support for NAND boot using simple NAND drivers that expose the cmd_ctrl() interface. + CONFIG_SPL_MTD_SUPPORT + Support for the MTD subsystem within SPL. Useful for + environment on NAND support within SPL. + + CONFIG_SPL_NAND_RAW_ONLY + Support to boot only raw u-boot.bin images. Use this only + if you need to save space. + + CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT + Set for the SPL on PPC mpc8xxx targets, support for + drivers/ddr/fsl/libddr.o in SPL binary. + + CONFIG_SPL_COMMON_INIT_DDR + Set for common ddr init with serial presence detect in + SPL binary. + CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, @@ -3082,6 +3765,9 @@ FIT uImage format: Defines the size and behavior of the NAND that SPL uses to read U-Boot + CONFIG_SPL_NAND_BOOT + Add support NAND boot + CONFIG_SYS_NAND_U_BOOT_OFFS Location in NAND to read U-Boot from @@ -3096,7 +3782,7 @@ FIT uImage format: CONFIG_SYS_NAND_HW_ECC_OOBFIRST Define this if you need to first read the OOB and then the - data. This is used for example on davinci plattforms. + data. This is used, for example, on davinci platforms. CONFIG_SPL_OMAP3_ID_NAND Support for an OMAP3-specific set of functions to return the @@ -3143,6 +3829,17 @@ FIT uImage format: option to re-enable it. This will affect the output of the bootm command when booting a FIT image. +- TPL framework + CONFIG_TPL + Enable building of TPL globally. + + CONFIG_TPL_PAD_TO + Image offset to which the TPL should be padded before appending + the TPL payload. By default, this is defined as + CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined. + CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL + payload without any padding, or >= CONFIG_SPL_MAX_SIZE. + Modem Support: -------------- @@ -3208,6 +3905,9 @@ typically in board_init_f() and board_init_r(). Configuration Settings: ----------------------- +- CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit. + Optionally it can be defined to support 64-bit memory commands. + - CONFIG_SYS_LONGHELP: Defined when you want long help messages included; undefine this when you're short of memory. @@ -3305,6 +4005,46 @@ Configuration Settings: - CONFIG_SYS_MALLOC_LEN: Size of DRAM reserved for malloc() use. +- CONFIG_SYS_MALLOC_F_LEN + Size of the malloc() pool for use before relocation. If + this is defined, then a very simple malloc() implementation + will become available before relocation. The address is just + below the global data, and the stack is moved down to make + space. + + This feature allocates regions with increasing addresses + within the region. calloc() is supported, but realloc() + is not available. free() is supported but does nothing. + The memory will be freed (or in fact just forgotten) when + U-Boot relocates itself. + + Pre-relocation malloc() is only supported on ARM and sandbox + at present but is fairly easy to enable for other archs. + +- CONFIG_SYS_MALLOC_SIMPLE + Provides a simple and small malloc() and calloc() for those + boards which do not use the full malloc in SPL (which is + enabled with CONFIG_SYS_SPL_MALLOC_START). + +- CONFIG_SYS_NONCACHED_MEMORY: + Size of non-cached memory area. This area of memory will be + typically located right below the malloc() area and mapped + uncached in the MMU. This is useful for drivers that would + otherwise require a lot of explicit cache maintenance. For + some drivers it's also impossible to properly maintain the + cache. For example if the regions that need to be flushed + are not a multiple of the cache-line size, *and* padding + cannot be allocated between the regions to align them (i.e. + if the HW requires a contiguous array of regions, and the + size of each region is not cache-aligned), then a flush of + one region may result in overwriting data that hardware has + written to another region in the same cache-line. This can + happen for example in network drivers where descriptors for + buffers are typically smaller than the CPU cache-line (e.g. + 16 bytes vs. 32 or 64 bytes). + + Non-cached memory is only supported on 32-bit ARM at present. + - CONFIG_SYS_BOOTM_LEN: Normally compressed uImages are limited to an uncompressed size of 8 MBytes. If this is not enough, @@ -3316,7 +4056,7 @@ Configuration Settings: the Linux kernel; all data that must be processed by the Linux kernel (bd_info, boot arguments, FDT blob if used) must be put below this limit, unless "bootm_low" - enviroment variable is defined and non-zero. In such case + environment variable is defined and non-zero. In such case all data for the Linux kernel must be between "bootm_low" and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment variable "bootm_mapsize" will override the value of @@ -3429,15 +4169,15 @@ Configuration Settings: - CONFIG_ENV_FLAGS_LIST_DEFAULT - CONFIG_ENV_FLAGS_LIST_STATIC - Enable validation of the values given to enviroment variables when + Enable validation of the values given to environment variables when calling env set. Variables can be restricted to only decimal, hexadecimal, or boolean. If CONFIG_CMD_NET is also defined, the variables can also be restricted to IP address or MAC address. The format of the list is: type_attribute = [s|d|x|b|i|m] - access_atribute = [a|r|o|c] - attributes = type_attribute[access_atribute] + access_attribute = [a|r|o|c] + attributes = type_attribute[access_attribute] entry = variable_name[:attributes] list = entry[,list] @@ -3457,7 +4197,7 @@ Configuration Settings: - CONFIG_ENV_FLAGS_LIST_DEFAULT Define this to a list (string) to define the ".flags" - envirnoment variable in the default or embedded environment. + environment variable in the default or embedded environment. - CONFIG_ENV_FLAGS_LIST_STATIC Define this to a list (string) to define validation that @@ -3480,16 +4220,15 @@ Configuration Settings: its config.mk file). If you find problems enabling this option on your board please report the problem and send patches! -- CONFIG_SYS_SYM_OFFSETS - This is set by architectures that use offsets for link symbols - instead of absolute values. So bss_start is obtained using an - offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than - directly. You should not need to touch this setting. - - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only) This is set by OMAP boards for the max time that reset should be asserted. See doc/README.omap-reset-time for details on how - the value can be calulated on a given board. + the value can be calculated on a given board. + +- CONFIG_USE_STDINT + If stdint.h is available with your toolchain you can define this + option to enable it. You can provide option 'USE_STDINT=1' when + building U-Boot to enable this. The following definitions that deal with the placement and management of environment data (variable area); in general, we support the @@ -3585,7 +4324,7 @@ accordingly! provision. BE CAREFUL! The first access to the environment happens quite early -in U-Boot initalization (when we try to get the setting of for the +in U-Boot initialization (when we try to get the setting of for the console baudrate). You *MUST* have mapped your NVRAM area then, or U-Boot will hang. @@ -3664,6 +4403,43 @@ to save the current settings. environment area within the total memory of your DataFlash placed at the specified address. +- CONFIG_ENV_IS_IN_SPI_FLASH: + + Define this if you have a SPI Flash memory device which you + want to use for the environment. + + - CONFIG_ENV_OFFSET: + - CONFIG_ENV_SIZE: + + These two #defines specify the offset and size of the + environment area within the SPI Flash. CONFIG_ENV_OFFSET must be + aligned to an erase sector boundary. + + - CONFIG_ENV_SECT_SIZE: + + Define the SPI flash's sector size. + + - CONFIG_ENV_OFFSET_REDUND (optional): + + This setting describes a second storage area of CONFIG_ENV_SIZE + size used to hold a redundant copy of the environment data, so + that there is a valid backup copy in case there is a power failure + during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be + aligned to an erase sector boundary. + + - CONFIG_ENV_SPI_BUS (optional): + - CONFIG_ENV_SPI_CS (optional): + + Define the SPI bus and chip select. If not defined they will be 0. + + - CONFIG_ENV_SPI_MAX_HZ (optional): + + Define the SPI max work clock. If not defined then use 1MHz. + + - CONFIG_ENV_SPI_MODE (optional): + + Define the SPI work mode. If not defined then use SPI_MODE_3. + - CONFIG_ENV_IS_IN_REMOTE: Define this if you have a remote memory space which you @@ -3751,6 +4527,37 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface. You will probably want to define these to avoid a really noisy system when storing the env in UBI. +- CONFIG_ENV_IS_IN_FAT: + Define this if you want to use the FAT file system for the environment. + + - FAT_ENV_INTERFACE: + + Define this to a string that is the name of the block device. + + - FAT_ENV_DEV_AND_PART: + + Define this to a string to specify the partition of the device. It can + be as following: + + "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1) + - "D:P": device D partition P. Error occurs if device D has no + partition table. + - "D:0": device D. + - "D" or "D:": device D partition 1 if device D has partition + table, or the whole device D if has no partition + table. + - "D:auto": first partition in device D with bootable flag set. + If none, first valid partition in device D. If no + partition table then means device D. + + - FAT_ENV_FILE: + + It's a string of the FAT file name. This file use to store the + environment. + + - CONFIG_FAT_WRITE: + This should be defined. Otherwise it cannot save the environment file. + - CONFIG_ENV_IS_IN_MMC: Define this if you have an MMC device which you want to use for the @@ -3854,6 +4661,11 @@ use the "saveenv" command to store a valid environment. later, once stdio is running and output goes to the LCD, if present. +- CONFIG_BOARD_SIZE_LIMIT: + Maximum size of the U-Boot image. When defined, the + build system checks that the actual size does not + exceed it. + Low Level (hardware related) configuration options: --------------------------------------------------- @@ -3927,7 +4739,7 @@ Low Level (hardware related) configuration options: if CONFIG_SYS_FDC_HW_INIT is defined, then the function fdc_hw_init() is called at the beginning of the FDC setup. fdc_hw_init() must be provided by the board - source code. It is used to make hardware dependant + source code. It is used to make hardware-dependent initializations. - CONFIG_IDE_AHB: @@ -3936,7 +4748,7 @@ Low Level (hardware related) configuration options: When software is doing ATA command and data transfer to IDE devices through IDE-AHB controller, some additional registers accessing to these kind of IDE-AHB controller - is requierd. + is required. - CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're @@ -4049,7 +4861,7 @@ Low Level (hardware related) configuration options: required. - CONFIG_PCI_ENUM_ONLY - Only scan through and get the devices on the busses. + Only scan through and get the devices on the buses. Don't do any setup work, presumably because someone or something has already done it, and we don't need to do it a second time. Useful for platforms that are pre-booted @@ -4180,6 +4992,11 @@ Low Level (hardware related) configuration options: that is executed before the actual U-Boot. E.g. when compiling a NAND SPL. +- CONFIG_TPL_BUILD + Modifies the behaviour of start.S when compiling a loader + that is executed after the SPL and before the actual U-Boot. + It is loaded by the SPL. + - CONFIG_SYS_MPC85XX_NO_RESETVEC Only for 85xx systems. If this variable is specified, the section .resetvec is not kept and the section .bootpg is placed in the @@ -4209,6 +5026,14 @@ Low Level (hardware related) configuration options: NOTE : currently only supported on AM335x platforms. +- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC: + Enables the RTC32K OSC on AM33xx based plattforms + +- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE + Option to disable subpage write in NAND driver + driver that uses this: + drivers/mtd/nand/davinci_nand.c + Freescale QE/FMAN Firmware Support: ----------------------------------- @@ -4218,8 +5043,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros are used to identify the storage device (NOR flash, SPI, etc) and the address within that device. -- CONFIG_SYS_QE_FMAN_FW_ADDR - The address in the storage device where the firmware is located. The +- CONFIG_SYS_FMAN_FW_ADDR + The address in the storage device where the FMAN microcode is located. The + meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_QE_FW_ADDR + The address in the storage device where the QE microcode is located. The meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro is also specified. @@ -4253,6 +5083,33 @@ within that device. window->master inbound window->master LAW->the ucode address in master's memory space. +Freescale Layerscape Management Complex Firmware Support: +--------------------------------------------------------- +The Freescale Layerscape Management Complex (MC) supports the loading of +"firmware". +This firmware often needs to be loaded during U-Boot booting, so macros +are used to identify the storage device (NOR flash, SPI, etc) and the address +within that device. + +- CONFIG_FSL_MC_ENET + Enable the MC driver for Layerscape SoCs. + +- CONFIG_SYS_LS_MC_FW_ADDR + The address in the storage device where the firmware is located. The + meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_LS_MC_FW_LENGTH + The maximum possible size of the firmware. The firmware binary format + has a field that specifies the actual size of the firmware, but it + might not be possible to read any part of the firmware unless some + local storage is allocated to hold the entire firmware first. + +- CONFIG_SYS_LS_MC_FW_IN_NOR + Specifies that MC firmware is located in NOR flash, mapped as + normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the + virtual address in NOR flash. + Building the Software: ====================== @@ -4286,9 +5143,9 @@ U-Boot is intended to be simple to build. After installing the sources you must configure U-Boot for one specific board type. This is done by typing: - make NAME_config + make NAME_defconfig -where "NAME_config" is the name of one of the existing configu- +where "NAME_defconfig" is the name of one of the existing configu- rations; see boards.cfg for supported names. Note: for some board special configuration names may exist; check if @@ -4297,10 +5154,10 @@ Note: for some board special configuration names may exist; check if or with LCD support. You can select such additional "features" when choosing the configuration, i. e. - make TQM823L_config + make TQM823L_defconfig - will configure for a plain TQM823L, i. e. no LCD support - make TQM823L_LCD_config + make TQM823L_LCD_defconfig - will configure for a TQM823L with U-Boot console on LCD etc. @@ -4320,17 +5177,17 @@ this behavior and build U-Boot to some external directory: 1. Add O= to the make command line invocations: make O=/tmp/build distclean - make O=/tmp/build NAME_config + make O=/tmp/build NAME_defconfig make O=/tmp/build all -2. Set environment variable BUILD_DIR to point to the desired location: +2. Set environment variable KBUILD_OUTPUT to point to the desired location: - export BUILD_DIR=/tmp/build + export KBUILD_OUTPUT=/tmp/build make distclean - make NAME_config + make NAME_defconfig make all -Note that the command line "O=" setting overrides the BUILD_DIR environment +Note that the command line "O=" setting overrides the KBUILD_OUTPUT environment variable. @@ -4353,7 +5210,7 @@ steps: your board 3. If you're porting U-Boot to a new CPU, then also create a new directory to hold your CPU specific code. Add any files you need. -4. Run "make _config" with your new name. +4. Run "make _defconfig" with your new name. 5. Type "make", and you should get a working "u-boot.srec" file to be installed on your target system. 6. Debug and solve any problems that might arise. @@ -4626,6 +5483,12 @@ List of environment variables (most likely not complete): npe_ucode - set load address for the NPE microcode + silent_linux - If set then Linux will be told to boot silently, by + changing the console to be empty. If "yes" it will be + made silent. If "no" it will not be made silent. If + unset, then it will be made silent if the U-Boot console + is silent. + tftpsrcport - If this is set, the value is used for TFTP's UDP source port. @@ -4707,7 +5570,7 @@ Callback functions for environment variables: --------------------------------------------- For some environment variables, the behavior of u-boot needs to change -when their values are changed. This functionailty allows functions to +when their values are changed. This functionality allows functions to be associated with arbitrary variables. On creation, overwrite, or deletion, the callback will provide the opportunity for some side effect to happen or for the change to be rejected. @@ -4730,7 +5593,7 @@ Callbacks can also be associated by defining the ".callbacks" variable with the same list format above. Any association in ".callbacks" will override any association in the static list. You can define CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the -".callbacks" envirnoment variable in the default or embedded environment. +".callbacks" environment variable in the default or embedded environment. Command Line Parsing: @@ -4902,6 +5765,11 @@ Information structure as we define in include/asm-/u-boot.h, and make sure that your definition of IMAP_ADDR uses the same value as your U-Boot configuration in CONFIG_SYS_IMMR. +Note that U-Boot now has a driver model, a unified model for drivers. +If you are adding a new driver, plumb it into driver model. If there +is no uclass available, you are encouraged to create one. See +doc/driver-model. + Configuring the Linux kernel: ----------------------------- @@ -4922,7 +5790,7 @@ which was introduced for our predecessor project PPCBoot and uses a Example: - make TQM850L_config + make TQM850L_defconfig make oldconfig make dep make uImage @@ -5042,6 +5910,16 @@ when your kernel is intended to use an initial ramdisk: Load Address: 0x00000000 Entry Point: 0x00000000 +The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i" +option performs the converse operation of the mkimage's second form (the "-d" +option). Given an image built by mkimage, the dumpimage extracts a "data file" +from the image: + + tools/dumpimage -i image -T type -p position data_file + -i ==> extract from the 'image' a specific 'data_file' + -T ==> set image type to 'type' + -p ==> 'position' (starting at 0) of the 'data_file' inside the 'image' + Installing a Linux Image: ------------------------- @@ -5481,7 +6359,7 @@ code for the initialization procedures: * Initialized global data (data segment) is read-only. Do not attempt to write it. -* Do not use any uninitialized global data (or implicitely initialized +* Do not use any uninitialized global data (or implicitly initialized as zero data - BSS segment) at all - this is undefined, initiali- zation is performed later (when relocating to RAM). @@ -5489,7 +6367,7 @@ code for the initialization procedures: that. Having only the stack as writable memory limits means we cannot use -normal global data to share information beween the code. But it +normal global data to share information between the code. But it turned out that the implementation of U-Boot can be greatly simplified by making a global data structure (gd_t) available to all functions. We could pass a pointer to this data as argument to _all_ @@ -5533,15 +6411,17 @@ On ARM, the following registers are used: R0: function argument word/integer result R1-R3: function argument word - R9: GOT pointer - R10: stack limit (used only if stack checking if enabled) + R9: platform specific + R10: stack limit (used only if stack checking is enabled) R11: argument (frame) pointer R12: temporary workspace R13: stack pointer R14: link register R15: program counter - ==> U-Boot will use R8 to hold a pointer to the global data + ==> U-Boot will use R9 to hold a pointer to the global data + + Note: on ARM, only R_ARM_RELATIVE relocations are supported. On Nios II, the ABI is documented here: http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf @@ -5618,7 +6498,7 @@ System Initialization: In the reset configuration, U-Boot starts at the reset entry point (on most PowerPC systems at address 0x00000100). Because of the reset -configuration for CS0# this is a mirror of the onboard Flash memory. +configuration for CS0# this is a mirror of the on board Flash memory. To be able to re-map memory U-Boot then jumps to its link address. To be able to implement the initialization code in C, a (small!) initial stack is set up in the internal Dual Ported RAM (in case CPUs @@ -5734,7 +6614,7 @@ coding style; see the file "Documentation/CodingStyle" and the script Source files originating from a different project (for example the MTD subsystem) are generally exempt from these guidelines and are not -reformated to ease subsequent migration to newer versions of those +reformatted to ease subsequent migration to newer versions of those sources. Please note that U-Boot is implemented in C (and to some small parts in @@ -5778,8 +6658,8 @@ it: * For major contributions, your entry to the CREDITS file -* When you add support for a new board, don't forget to add this - board to the MAINTAINERS file, too. +* When you add support for a new board, don't forget to add a + maintainer e-mail address to the boards.cfg file, too. * If your patch adds new configuration options, don't forget to document these in the README file. diff --git a/api/Makefile b/api/Makefile index 87b8eb2bb8..3c095eedb6 100644 --- a/api/Makefile +++ b/api/Makefile @@ -4,21 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libapi.o - -COBJS-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \ - api_platform-$(ARCH).o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y += api.o api_display.o api_net.o api_storage.o +obj-$(CONFIG_ARM) += api_platform-arm.o +obj-$(CONFIG_PPC) += api_platform-powerpc.o diff --git a/api/api_net.c b/api/api_net.c index 3f52d71171..7b3805e8fd 100644 --- a/api/api_net.c +++ b/api/api_net.c @@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0) +#ifdef CONFIG_CMD_NET static int dev_valid_net(void *cookie) { @@ -85,3 +86,32 @@ int dev_read_net(void *cookie, void *buf, int len) return eth_receive(buf, len); } + +#else + +int dev_open_net(void *cookie) +{ + return API_ENODEV; +} + +int dev_close_net(void *cookie) +{ + return API_ENODEV; +} + +int dev_enum_net(struct device_info *di) +{ + return 0; +} + +int dev_write_net(void *cookie, void *buf, int len) +{ + return API_ENODEV; +} + +int dev_read_net(void *cookie, void *buf, int len) +{ + return API_ENODEV; +} + +#endif diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index eb421d642d..f23f17501f 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si) si->clk_bus = gd->bus_clk; si->clk_cpu = gd->cpu_clk; -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define bi_bar bi_immr_base #elif defined(CONFIG_MPC5xxx) diff --git a/arch/.gitignore b/arch/.gitignore index a1fbe01d57..2714b86ff3 100644 --- a/arch/.gitignore +++ b/arch/.gitignore @@ -1,2 +1 @@ /*/include/asm/arch -/*/include/asm/proc diff --git a/arch/Kconfig b/arch/Kconfig new file mode 100644 index 0000000000..f63cc5a7e9 --- /dev/null +++ b/arch/Kconfig @@ -0,0 +1,131 @@ +choice + prompt "Architecture select" + default SANDBOX + +config ARC + bool "ARC architecture" + +config ARM + bool "ARM architecture" + select HAVE_PRIVATE_LIBGCC + select SUPPORT_OF_CONTROL + +config AVR32 + bool "AVR32 architecture" + +config BLACKFIN + bool "Blackfin architecture" + +config M68K + bool "M68000 architecture" + +config MICROBLAZE + bool "MicroBlaze architecture" + select SUPPORT_OF_CONTROL + +config MIPS + bool "MIPS architecture" + select HAVE_PRIVATE_LIBGCC + +config NDS32 + bool "NDS32 architecture" + +config NIOS2 + bool "Nios II architecture" + +config OPENRISC + bool "OpenRISC architecture" + +config PPC + bool "PowerPC architecture" + select HAVE_PRIVATE_LIBGCC + +config SANDBOX + bool "Sandbox" + select SUPPORT_OF_CONTROL + +config SH + bool "SuperH architecture" + select HAVE_PRIVATE_LIBGCC + +config SPARC + bool "SPARC architecture" + +config X86 + bool "x86 architecture" + select HAVE_PRIVATE_LIBGCC + select SUPPORT_OF_CONTROL + +endchoice + +config SYS_ARCH + string + help + This option should contain the architecture name to build the + appropriate arch/ directory. + All the architectures should specify this option correctly. + +config SYS_CPU + string + help + This option should contain the CPU name to build the correct + arch//cpu/ directory. + + This is optional. For those targets without the CPU directory, + leave this option empty. + +config SYS_SOC + string + help + This option should contain the SoC name to build the directory + arch//cpu//. + + This is optional. For those targets without the SoC directory, + leave this option empty. + +config SYS_VENDOR + string + help + This option should contain the vendor name of the target board. + If it is set and + board//common/Makefile exists, the vendor common + directory is compiled. + If CONFIG_SYS_BOARD is also set, the sources under + board// directory are compiled. + + This is optional. For those targets without the vendor directory, + leave this option empty. + +config SYS_BOARD + string + help + This option should contain the name of the target board. + If it is set, either board// + or board/ directory is compiled depending on + whether CONFIG_SYS_VENDOR is set or not. + + This is optional. For those targets without the board directory, + leave this option empty. + +config SYS_CONFIG_NAME + string + help + This option should contain the base name of board header file. + The header file include/configs/.h + should be included from include/config.h. + +source "arch/arc/Kconfig" +source "arch/arm/Kconfig" +source "arch/avr32/Kconfig" +source "arch/blackfin/Kconfig" +source "arch/m68k/Kconfig" +source "arch/microblaze/Kconfig" +source "arch/mips/Kconfig" +source "arch/nds32/Kconfig" +source "arch/nios2/Kconfig" +source "arch/openrisc/Kconfig" +source "arch/powerpc/Kconfig" +source "arch/sandbox/Kconfig" +source "arch/sh/Kconfig" +source "arch/sparc/Kconfig" +source "arch/x86/Kconfig" diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig new file mode 100644 index 0000000000..c6b1efeb8b --- /dev/null +++ b/arch/arc/Kconfig @@ -0,0 +1,31 @@ +menu "ARC architecture" + depends on ARC + +config SYS_ARCH + default "arc" + +config SYS_CPU + default "arcv1" + +choice + prompt "Target select" + +config TARGET_TB100 + bool "Support tb100" + +config TARGET_ARCANGEL4 + bool "Support arcangel4" + +config TARGET_ARCANGEL4_BE + bool "Support arcangel4-be" + +config TARGET_AXS101 + bool "Support axs101" + +endchoice + +source "board/abilis/tb100/Kconfig" +source "board/synopsys/Kconfig" +source "board/synopsys/axs101/Kconfig" + +endmenu diff --git a/arch/arc/Makefile b/arch/arc/Makefile new file mode 100644 index 0000000000..a59231e70e --- /dev/null +++ b/arch/arc/Makefile @@ -0,0 +1,21 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +libs-y += arch/arc/cpu/$(CPU)/ +libs-y += arch/arc/lib/ + +# MetaWare debugger doesn't support PIE (position-independent executable) +# so the only way to load U-Boot in MDB is to fake it by: +# 1. Reset PIE flag in ELF header +# 2. Strip all debug information from elf +ifdef CONFIG_SYS_LITTLE_ENDIAN + EXEC_TYPE_OFFSET=16 +else + EXEC_TYPE_OFFSET=17 +endif + +mdbtrick: u-boot + $(Q)printf '\x02' | dd of=u-boot bs=1 seek=$(EXEC_TYPE_OFFSET) count=1 \ + conv=notrunc &> /dev/null + $(Q)$(CROSS_COMPILE)strip -g u-boot diff --git a/arch/arc/config.mk b/arch/arc/config.mk new file mode 100644 index 0000000000..5321987a56 --- /dev/null +++ b/arch/arc/config.mk @@ -0,0 +1,37 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SYS_BIG_ENDIAN +CONFIG_SYS_LITTLE_ENDIAN = 1 +endif + +ifdef CONFIG_SYS_LITTLE_ENDIAN +ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc- +endif + +ifdef CONFIG_SYS_BIG_ENDIAN +ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc- +PLATFORM_LDFLAGS += -EB +endif + +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := $(ARC_CROSS_COMPILE) +endif + +ifdef CONFIG_ARC_MMU_VER +CONFIG_MMU = 1 +endif + +PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 + +# Needed for relocation +LDFLAGS_FINAL += -pie + +# Load address for standalone apps +CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 + +# Support generic board on ARC +__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/arc/cpu/arcv1/Makefile b/arch/arc/cpu/arcv1/Makefile new file mode 100644 index 0000000000..3704ebeeae --- /dev/null +++ b/arch/arc/cpu/arcv1/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += start.o diff --git a/arch/arc/cpu/arcv1/config.mk b/arch/arc/cpu/arcv1/config.mk new file mode 100644 index 0000000000..3206ff47e3 --- /dev/null +++ b/arch/arc/cpu/arcv1/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -mA7 diff --git a/arch/arc/cpu/arcv1/start.S b/arch/arc/cpu/arcv1/start.S new file mode 100644 index 0000000000..01cfba4933 --- /dev/null +++ b/arch/arc/cpu/arcv1/start.S @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * Note on the LD/ST addressing modes with address register write-back + * + * LD.a same as LD.aw + * + * LD.a reg1, [reg2, x] => Pre Incr + * Eff Addr for load = [reg2 + x] + * + * LD.ab reg1, [reg2, x] => Post Incr + * Eff Addr for load = [reg2] + */ + +.macro PUSH reg + st.a \reg, [%sp, -4] +.endm + +.macro PUSHAX aux + lr %r9, [\aux] + PUSH %r9 +.endm + +.macro SAVE_R1_TO_R24 + PUSH %r1 + PUSH %r2 + PUSH %r3 + PUSH %r4 + PUSH %r5 + PUSH %r6 + PUSH %r7 + PUSH %r8 + PUSH %r9 + PUSH %r10 + PUSH %r11 + PUSH %r12 + PUSH %r13 + PUSH %r14 + PUSH %r15 + PUSH %r16 + PUSH %r17 + PUSH %r18 + PUSH %r19 + PUSH %r20 + PUSH %r21 + PUSH %r22 + PUSH %r23 + PUSH %r24 +.endm + +.macro SAVE_ALL_SYS + /* saving %r0 to reg->r0 in advance since we read %ecr into it */ + st %r0, [%sp, -8] + lr %r0, [%ecr] /* all stack addressing is manual so far */ + st %r0, [%sp] + st %sp, [%sp, -4] + /* now move %sp to reg->r0 position so we can do "push" automatically */ + sub %sp, %sp, 8 + + SAVE_R1_TO_R24 + PUSH %r25 + PUSH %gp + PUSH %fp + PUSH %blink + PUSHAX %eret + PUSHAX %erstatus + PUSH %lp_count + PUSHAX %lp_end + PUSHAX %lp_start + PUSHAX %erbta +.endm + +.macro SAVE_EXCEPTION_SOURCE +#ifdef CONFIG_MMU + /* If MMU exists exception faulting address is loaded in EFA reg */ + lr %r0, [%efa] +#else + /* Otherwise in ERET (exception return) reg */ + lr %r0, [%eret] +#endif +.endm + +.section .ivt, "ax",@progbits +.align 4 +_ivt: + /* Critical system events */ + j _start /* 0 - 0x000 */ + j memory_error /* 1 - 0x008 */ + j instruction_error /* 2 - 0x010 */ + + /* Device interrupts */ +.rept 29 + j interrupt_handler /* 3:31 - 0x018:0xF8 */ +.endr + /* Exceptions */ + j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ + j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ + j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ + j EV_TLBProtV /* 0x118, Protection Violation (0x23) + or Misaligned Access */ + j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ + j EV_Trap /* 0x128, Trap exception (0x25) */ + j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ + +.text +.globl _start +_start: + /* Setup interrupt vector base that matches "__text_start" */ + sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] + + /* Setup stack pointer */ + mov %sp, CONFIG_SYS_INIT_SP_ADDR + mov %fp, %sp + + /* Clear bss */ + mov %r0, __bss_start + mov %r1, __bss_end + +clear_bss: + st.ab 0, [%r0, 4] + brlt %r0, %r1, clear_bss + + /* Zero the one and only argument of "board_init_f" */ + mov_s %r0, 0 + j board_init_f + +memory_error: + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_memory_error + +instruction_error: + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_instruction_error + +interrupt_handler: + /* Todo - save and restore CPU context when interrupts will be in use */ + bl do_interrupt_handler + rtie + +EV_MachineCheck: + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_machine_check_fault + +EV_TLBMissI: + SAVE_ALL_SYS + mov %r0, %sp + j do_itlb_miss + +EV_TLBMissD: + SAVE_ALL_SYS + mov %r0, %sp + j do_dtlb_miss + +EV_TLBProtV: + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_tlb_prot_violation + +EV_PrivilegeV: + SAVE_ALL_SYS + mov %r0, %sp + j do_privilege_violation + +EV_Trap: + SAVE_ALL_SYS + mov %r0, %sp + j do_trap + +EV_Extension: + SAVE_ALL_SYS + mov %r0, %sp + j do_extension + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r0 = start_addr_sp + * r1 = new__gd + * r2 = relocaddr + */ +.align 4 +.globl relocate_code +relocate_code: + /* + * r0-r12 might be clobbered by C functions + * so we use r13-r16 for storage here + */ + mov %r13, %r0 /* save addr_sp */ + mov %r14, %r1 /* save addr of gd */ + mov %r15, %r2 /* save addr of destination */ + + mov %r16, %r2 /* %r9 - relocation offset */ + sub %r16, %r16, __image_copy_start + +/* Set up the stack */ +stack_setup: + mov %sp, %r13 + mov %fp, %sp + +/* Check if monitor is loaded right in place for relocation */ + mov %r0, __image_copy_start + cmp %r0, %r15 /* skip relocation if code loaded */ + bz do_board_init_r /* in target location already */ + +/* Copy data (__image_copy_start - __image_copy_end) to new location */ + mov %r1, %r15 + mov %r2, __image_copy_end + sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */ + asr %r2, %r2, 2 /* r3 <- amount of words to copy */ + mov %lp_count, %r2 + lp copy_end + ld.ab %r2,[%r0,4] + st.ab %r2,[%r1,4] +copy_end: + +/* Fix relocations related issues */ + bl do_elf_reloc_fixups +#ifndef CONFIG_SYS_ICACHE_OFF + bl invalidate_icache_all +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + bl flush_dcache_all +#endif + +/* Update position of intterupt vector table */ + lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */ + add %r0, %r0, %r16 /* Update address */ + sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */ + +do_board_init_r: +/* Prepare for exection of "board_init_r" in relocated monitor */ + mov %r2, board_init_r /* old address of "board_init_r()" */ + add %r2, %r2, %r16 /* new address of "board_init_r()" */ + mov %r0, %r14 /* 1-st parameter: gd_t */ + mov %r1, %r15 /* 2-nd parameter: dest_addr */ + j [%r2] diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds new file mode 100644 index 0000000000..ccddbf7dc9 --- /dev/null +++ b/arch/arc/cpu/u-boot.lds @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc") +OUTPUT_ARCH(arc) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : { + *(.__text_start) + *(.__image_copy_start) + *(.text*) + } + + . = ALIGN(4); + .text_end : + { + *(.__text_end) + } + + . = ALIGN(1024); + .ivt_start : { + *(.__ivt_start) + } + + .ivt : + { + *(.ivt) + } + + .ivt_end : { + *(.__ivt_end) + } + + . = ALIGN(4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .rel_dyn_start : { + *(.__rel_dyn_start) + } + + .rela.dyn : { + *(.rela.dyn) + } + + .rel_dyn_end : { + *(.__rel_dyn_end) + } + + . = ALIGN(4); + .bss_start : { + *(.__bss_start); + } + + .bss : { + *(.bss*) + } + + .bss_end : { + *(.__bss_end); + } + + . = ALIGN(4); + .image_copy_end : { + *(.__image_copy_end) + *(.__init_end) + } +} diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h new file mode 100644 index 0000000000..8ace87fa0f --- /dev/null +++ b/arch/arc/include/asm/arcregs.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARC_ARCREGS_H +#define _ASM_ARC_ARCREGS_H + +/* + * ARC architecture has additional address space - auxiliary registers. + * These registers are mostly used for configuration purposes. + * These registers are not memory mapped and special commands are used for + * access: "lr"/"sr". + */ + +#define ARC_AUX_IDENTITY 0x04 +#define ARC_AUX_STATUS32 0x0a + +/* Instruction cache related auxiliary registers */ +#define ARC_AUX_IC_IVIC 0x10 +#define ARC_AUX_IC_CTRL 0x11 +#define ARC_AUX_IC_IVIL 0x19 +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_AUX_IC_PTAG 0x1E +#endif +#define ARC_BCR_IC_BUILD 0x77 + +/* Timer related auxiliary registers */ +#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ +#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ +#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ + +#define ARC_AUX_INTR_VEC_BASE 0x25 + +/* Data cache related auxiliary registers */ +#define ARC_AUX_DC_IVDC 0x47 +#define ARC_AUX_DC_CTRL 0x48 + +#define ARC_AUX_DC_IVDL 0x4A +#define ARC_AUX_DC_FLSH 0x4B +#define ARC_AUX_DC_FLDL 0x4C +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_AUX_DC_PTAG 0x5C +#endif +#define ARC_BCR_DC_BUILD 0x72 + +#ifndef __ASSEMBLY__ +/* Accessors for auxiliary registers */ +#define read_aux_reg(reg) __builtin_arc_lr(reg) + +/* gcc builtin sr needs reg param to be long immediate */ +#define write_aux_reg(reg_immed, val) \ + __builtin_arc_sr((unsigned int)val, reg_immed) +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARC_ARCREGS_H */ diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h new file mode 100644 index 0000000000..85721aaee3 --- /dev/null +++ b/arch/arc/include/asm/bitops.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_BITOPS_H +#define __ASM_ARC_BITOPS_H + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __ASM_ARC_BITOPS_H */ diff --git a/arch/arc/include/asm/byteorder.h b/arch/arc/include/asm/byteorder.h new file mode 100644 index 0000000000..2fa9776ca5 --- /dev/null +++ b/arch/arc/include/asm/byteorder.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_BYTEORDER_H +#define __ASM_ARC_BYTEORDER_H + +#include + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) + #define __BYTEORDER_HAS_U64__ + #define __SWAB_64_THRU_32__ +#endif + +#ifdef __LITTLE_ENDIAN__ + #include +#else + #include +#endif /* CONFIG_SYS_BIG_ENDIAN */ + +#endif /* ASM_ARC_BYTEORDER_H */ diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h new file mode 100644 index 0000000000..16e7568ef0 --- /dev/null +++ b/arch/arc/include/asm/cache.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_CACHE_H +#define __ASM_ARC_CACHE_H + +#include + +/* + * The current upper bound for ARC L1 data cache line sizes is 128 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 128 +#endif + +#endif /* __ASM_ARC_CACHE_H */ diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h new file mode 100644 index 0000000000..e5be078c19 --- /dev/null +++ b/arch/arc/include/asm/config.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_CONFIG_H_ +#define __ASM_ARC_CONFIG_H_ + +#define CONFIG_SYS_GENERIC_GLOBAL_DATA +#define CONFIG_SYS_BOOT_RAMDISK_HIGH + +#define CONFIG_LMB + +#endif /*__ASM_ARC_CONFIG_H_ */ diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h new file mode 100644 index 0000000000..4c82b503d9 --- /dev/null +++ b/arch/arc/include/asm/errno.h @@ -0,0 +1 @@ +#include diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h new file mode 100644 index 0000000000..d644e80586 --- /dev/null +++ b/arch/arc/include/asm/global_data.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_GLOBAL_DATA_H +#define __ASM_ARC_GLOBAL_DATA_H + +/* Architecture-specific global data */ +struct arch_global_data { + int running_on_hw; +}; + +#include + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r25") + +#endif /* __ASM_ARC_GLOBAL_DATA_H */ diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h new file mode 100644 index 0000000000..24b7337308 --- /dev/null +++ b/arch/arc/include/asm/io.h @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_IO_H +#define __ASM_ARC_IO_H + +#include +#include + +static inline void sync(void) +{ + /* Not yet implemented */ +} + +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + u8 b; + + __asm__ __volatile__("ldb%U1 %0, %1\n" + : "=r" (b) + : "m" (*(volatile u8 __force *)addr) + : "memory"); + return b; +} + +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + u16 s; + + __asm__ __volatile__("ldw%U1 %0, %1\n" + : "=r" (s) + : "m" (*(volatile u16 __force *)addr) + : "memory"); + return s; +} + +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + u32 w; + + __asm__ __volatile__("ld%U1 %0, %1\n" + : "=r" (w) + : "m" (*(volatile u32 __force *)addr) + : "memory"); + return w; +} + +#define readb __raw_readb + +static inline u16 readw(const volatile void __iomem *addr) +{ + return __le16_to_cpu(__raw_readw(addr)); +} + +static inline u32 readl(const volatile void __iomem *addr) +{ + return __le32_to_cpu(__raw_readl(addr)); +} + +static inline void __raw_writeb(u8 b, volatile void __iomem *addr) +{ + __asm__ __volatile__("stb%U1 %0, %1\n" + : + : "r" (b), "m" (*(volatile u8 __force *)addr) + : "memory"); +} + +static inline void __raw_writew(u16 s, volatile void __iomem *addr) +{ + __asm__ __volatile__("stw%U1 %0, %1\n" + : + : "r" (s), "m" (*(volatile u16 __force *)addr) + : "memory"); +} + +static inline void __raw_writel(u32 w, volatile void __iomem *addr) +{ + __asm__ __volatile__("st%U1 %0, %1\n" + : + : "r" (w), "m" (*(volatile u32 __force *)addr) + : "memory"); +} + +#define writeb __raw_writeb +#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr) +#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr) + +static inline int __raw_readsb(unsigned int addr, void *data, int bytelen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "stb.ab r8, [r1, 1]\n" + : + : "r" (addr), "r" (data), "r" (bytelen) + : "r8"); + return bytelen; +} + +static inline int __raw_readsw(unsigned int addr, void *data, int wordlen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "stw.ab r8, [r1, 2]\n" + : + : "r" (addr), "r" (data), "r" (wordlen) + : "r8"); + return wordlen; +} + +static inline int __raw_readsl(unsigned int addr, void *data, int longlen) +{ + __asm__ __volatile__ ("1:ld.di r8, [r0]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab r8, [r1, 4]\n" + : + : "r" (addr), "r" (data), "r" (longlen) + : "r8"); + return longlen; +} + +static inline int __raw_writesb(unsigned int addr, void *data, int bytelen) +{ + __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (bytelen) + : "r8"); + return bytelen; +} + +static inline int __raw_writesw(unsigned int addr, void *data, int wordlen) +{ + __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (wordlen) + : "r8"); + return wordlen; +} + +static inline int __raw_writesl(unsigned int addr, void *data, int longlen) +{ + __asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n" + "sub.f r2, r2, 1\n" + "bnz.d 1b\n" + "st.ab.di r8, [r0, 0]\n" + : + : "r" (addr), "r" (data), "r" (longlen) + : "r8"); + return longlen; +} + +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) + +/* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +#endif /* __ASM_ARC_IO_H */ diff --git a/arch/arc/include/asm/posix_types.h b/arch/arc/include/asm/posix_types.h new file mode 100644 index 0000000000..51347a48d4 --- /dev/null +++ b/arch/arc/include/asm/posix_types.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_POSIX_TYPES_H +#define __ASM_ARC_POSIX_TYPES_H + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +#ifdef __GNUC__ +typedef __SIZE_TYPE__ __kernel_size_t; +#else +typedef unsigned int __kernel_size_t; +#endif +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +#endif /* __ASM_ARC_POSIX_TYPES_H */ diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h new file mode 100644 index 0000000000..8f73b31c10 --- /dev/null +++ b/arch/arc/include/asm/ptrace.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_PTRACE_H +#define __ASM_ARC_PTRACE_H + +struct pt_regs { + long bta; + long lp_start; + long lp_end; + long lp_count; + long status32; + long ret; + long blink; + long fp; + long r26; /* gp */ + long r25; + long r24; + long r23; + long r22; + long r21; + long r20; + long r19; + long r18; + long r17; + long r16; + long r15; + long r14; + long r13; + long r12; + long r11; + long r10; + long r9; + long r8; + long r7; + long r6; + long r5; + long r4; + long r3; + long r2; + long r1; + long r0; + long sp; + long ecr; +}; + +#endif /* __ASM_ARC_PTRACE_H */ diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h new file mode 100644 index 0000000000..b8f2a859fd --- /dev/null +++ b/arch/arc/include/asm/sections.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_SECTIONS_H +#define __ASM_ARC_SECTIONS_H + +#include + +extern ulong __text_end; +extern ulong __ivt_start; +extern ulong __ivt_end; +extern ulong __image_copy_start; + +#endif /* __ASM_ARC_SECTIONS_H */ diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h new file mode 100644 index 0000000000..909129c333 --- /dev/null +++ b/arch/arc/include/asm/string.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_STRING_H +#define __ASM_ARC_STRING_H + +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMCMP +#define __HAVE_ARCH_STRCHR +#define __HAVE_ARCH_STRCPY +#define __HAVE_ARCH_STRCMP +#define __HAVE_ARCH_STRLEN + +extern void *memset(void *ptr, int, __kernel_size_t); +extern void *memcpy(void *, const void *, __kernel_size_t); +extern void memzero(void *ptr, __kernel_size_t n); +extern int memcmp(const void *, const void *, __kernel_size_t); +extern char *strchr(const char *s, int c); +extern char *strcpy(char *dest, const char *src); +extern int strcmp(const char *cs, const char *ct); +extern __kernel_size_t strlen(const char *); + +#endif /* __ASM_ARC_STRING_H */ diff --git a/arch/arc/include/asm/types.h b/arch/arc/include/asm/types.h new file mode 100644 index 0000000000..24eeb76bd6 --- /dev/null +++ b/arch/arc/include/asm/types.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_TYPES_H +#define __ASM_ARC_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __ASM_ARC_TYPES_H */ diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h new file mode 100644 index 0000000000..0c0e8e661d --- /dev/null +++ b/arch/arc/include/asm/u-boot-arc.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_U_BOOT_ARC_H__ +#define __ASM_ARC_U_BOOT_ARC_H__ + +int arch_early_init_r(void); + +#endif /* __ASM_ARC_U_BOOT_ARC_H__ */ diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h new file mode 100644 index 0000000000..e354edf95d --- /dev/null +++ b/arch/arc/include/asm/u-boot.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_U_BOOT_H__ +#define __ASM_ARC_U_BOOT_H__ + +#include + +/* For image.h:image_check_target_arch() */ +#define IH_ARCH_DEFAULT IH_ARCH_ARC + +#endif /* __ASM_ARC_U_BOOT_H__ */ diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h new file mode 100644 index 0000000000..6cecbbb211 --- /dev/null +++ b/arch/arc/include/asm/unaligned.h @@ -0,0 +1 @@ +#include diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile new file mode 100644 index 0000000000..bae44199a4 --- /dev/null +++ b/arch/arc/lib/Makefile @@ -0,0 +1,22 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cache.o +obj-y += cpu.o +obj-y += interrupts.o +obj-y += sections.o +obj-y += relocate.o +obj-y += strchr-700.o +obj-y += strcmp.o +obj-y += strcpy-700.o +obj-y += strlen.o +obj-y += memcmp.o +obj-y += memcpy-700.o +obj-y += memset.o +obj-y += reset.o +obj-y += timer.o + +obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c new file mode 100644 index 0000000000..d185a50bd3 --- /dev/null +++ b/arch/arc/lib/bootm.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + ulong sp; + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + sp = get_sp(); + debug("## Current stack ends at 0x%08lx ", sp); + + /* adjust sp by 4K to be safe */ + sp -= 4096; + lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp)); +} + +static int cleanup_before_linux(void) +{ + disable_interrupts(); + flush_dcache_all(); + invalidate_icache_all(); + + return 0; +} + +/* Subcommand: PREP */ +static void boot_prep_linux(bootm_headers_t *images) +{ + if (image_setup_linux(images)) + hang(); +} + +/* Subcommand: GO */ +static void boot_jump_linux(bootm_headers_t *images, int flag) +{ + void (*kernel_entry)(int zero, int arch, uint params); + unsigned int r0, r2; + int fake = (flag & BOOTM_STATE_OS_FAKE_GO); + + kernel_entry = (void (*)(int, int, uint))images->ep; + + debug("## Transferring control to Linux (at address %08lx)...\n", + (ulong) kernel_entry); + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + printf("\nStarting kernel ...%s\n\n", fake ? + "(fake run for tracing)" : ""); + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + + cleanup_before_linux(); + + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + r0 = 2; + r2 = (unsigned int)images->ft_addr; + } else { + r0 = 1; + r2 = (unsigned int)getenv("bootargs"); + } + + if (!fake) + kernel_entry(r0, 0, r2); +} + +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + /* No need for those on ARC */ + if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE)) + return -1; + + if (flag & BOOTM_STATE_OS_PREP) { + boot_prep_linux(images); + return 0; + } + + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { + boot_jump_linux(images, flag); + return 0; + } + + boot_prep_linux(images); + boot_jump_linux(images, flag); + return 0; +} diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c new file mode 100644 index 0000000000..fa19a13b7e --- /dev/null +++ b/arch/arc/lib/cache.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/* Bit values in IC_CTRL */ +#define IC_CTRL_CACHE_DISABLE (1 << 0) + +/* Bit values in DC_CTRL */ +#define DC_CTRL_CACHE_DISABLE (1 << 0) +#define DC_CTRL_INV_MODE_FLUSH (1 << 6) +#define DC_CTRL_FLUSH_STATUS (1 << 8) +#define CACHE_VER_NUM_MASK 0xF + +int icache_status(void) +{ + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)) + return 0; + + return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) != + IC_CTRL_CACHE_DISABLE; +} + +void icache_enable(void) +{ + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)) + return; + + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & + ~IC_CTRL_CACHE_DISABLE); +} + +void icache_disable(void) +{ + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)) + return; + + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | + IC_CTRL_CACHE_DISABLE); +} + +void invalidate_icache_all(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + /* Any write to IC_IVIC register triggers invalidation of entire I$ */ + write_aux_reg(ARC_AUX_IC_IVIC, 1); +#endif /* CONFIG_SYS_ICACHE_OFF */ +} + +int dcache_status(void) +{ + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return 0; + + return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) != + DC_CTRL_CACHE_DISABLE; +} + +void dcache_enable(void) +{ + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return; + + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & + ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); +} + +void dcache_disable(void) +{ + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return; + + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | + DC_CTRL_CACHE_DISABLE); +} + +void flush_dcache_all(void) +{ + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return; + + /* Do flush of entire cache */ + write_aux_reg(ARC_AUX_DC_FLSH, 1); + + /* Wait flush end */ + while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) + ; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +static void dcache_flush_line(unsigned addr) +{ +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_DC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_DC_FLDL, addr); + + /* Wait flush end */ + while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) + ; + +#ifndef CONFIG_SYS_ICACHE_OFF + /* + * Invalidate I$ for addresses range just flushed from D$. + * If we try to execute data flushed above it will be valid/correct + */ +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_IC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_IC_IVIL, addr); +#endif /* CONFIG_SYS_ICACHE_OFF */ +} +#endif /* CONFIG_SYS_DCACHE_OFF */ + +void flush_dcache_range(unsigned long start, unsigned long end) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + unsigned int addr; + + start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + + for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) + dcache_flush_line(addr); +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + unsigned int addr; + + start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1)); + + for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { +#if (CONFIG_ARC_MMU_VER > 2) + write_aux_reg(ARC_AUX_DC_PTAG, addr); +#endif + write_aux_reg(ARC_AUX_DC_IVDL, addr); + } +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void invalidate_dcache_all(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */ + write_aux_reg(ARC_AUX_DC_IVDC, 1); +#endif /* CONFIG_SYS_DCACHE_OFF */ +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c new file mode 100644 index 0000000000..50634b860f --- /dev/null +++ b/arch/arc/lib/cpu.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int arch_cpu_init(void) +{ +#ifdef CONFIG_SYS_ICACHE_OFF + icache_disable(); +#else + icache_enable(); + invalidate_icache_all(); +#endif + + flush_dcache_all(); +#ifdef CONFIG_SYS_DCACHE_OFF + dcache_disable(); +#else + dcache_enable(); +#endif + timer_init(); + +/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */ + if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00) + gd->arch.running_on_hw = 0; + else + gd->arch.running_on_hw = 1; + + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int arch_early_init_r(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + return 0; +} diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c new file mode 100644 index 0000000000..d7cab3bb40 --- /dev/null +++ b/arch/arc/lib/interrupts.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* Bit values in STATUS32 */ +#define E1_MASK (1 << 1) /* Level 1 interrupts enable */ +#define E2_MASK (1 << 2) /* Level 2 interrupts enable */ + +int interrupt_init(void) +{ + return 0; +} + +/* + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts(void) +{ + int status = read_aux_reg(ARC_AUX_STATUS32); + int state = (status & (E1_MASK | E2_MASK)) ? 1 : 0; + + status &= ~(E1_MASK | E2_MASK); + /* STATUS32 register is updated indirectly with "FLAG" instruction */ + __asm__("flag %0" : : "r" (status)); + return state; +} + +void enable_interrupts(void) +{ + unsigned int status = read_aux_reg(ARC_AUX_STATUS32); + + status |= E1_MASK | E2_MASK; + /* STATUS32 register is updated indirectly with "FLAG" instruction */ + __asm__("flag %0" : : "r" (status)); +} + +static void print_reg_file(long *reg_rev, int start_num) +{ + unsigned int i; + + /* Print 3 registers per line */ + for (i = start_num; i < start_num + 25; i++) { + printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev); + if (((i + 1) % 3) == 0) + printf("\n"); + + /* Because pt_regs has registers reversed */ + reg_rev--; + } + + /* Add new-line if none was inserted in the end of loop above */ + if (((i + 1) % 3) != 0) + printf("\n"); +} + +void show_regs(struct pt_regs *regs) +{ + printf("ECR:\t0x%08lx\n", regs->ecr); + printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n", + regs->ret, regs->blink, regs->status32); + printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25); + printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta, + regs->sp, regs->fp); + printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start, + regs->lp_end, regs->lp_count); + + print_reg_file(&(regs->r0), 0); +} + +void bad_mode(struct pt_regs *regs) +{ + if (regs) + show_regs(regs); + + panic("Resetting CPU ...\n"); +} + +void do_memory_error(unsigned long address, struct pt_regs *regs) +{ + printf("Memory error exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_instruction_error(unsigned long address, struct pt_regs *regs) +{ + printf("Instruction error exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_machine_check_fault(unsigned long address, struct pt_regs *regs) +{ + printf("Machine check exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_interrupt_handler(void) +{ + printf("Interrupt fired\n"); + bad_mode(0); +} + +void do_itlb_miss(struct pt_regs *regs) +{ + printf("I TLB miss exception\n"); + bad_mode(regs); +} + +void do_dtlb_miss(struct pt_regs *regs) +{ + printf("D TLB miss exception\n"); + bad_mode(regs); +} + +void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs) +{ + printf("TLB protection violation or misaligned access @ 0x%lx\n", + address); + bad_mode(regs); +} + +void do_privilege_violation(struct pt_regs *regs) +{ + printf("Privilege violation exception\n"); + bad_mode(regs); +} + +void do_trap(struct pt_regs *regs) +{ + printf("Trap exception\n"); + bad_mode(regs); +} + +void do_extension(struct pt_regs *regs) +{ + printf("Extension instruction exception\n"); + bad_mode(regs); +} diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S new file mode 100644 index 0000000000..fa5aac5f67 --- /dev/null +++ b/arch/arc/lib/memcmp.S @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef __LITTLE_ENDIAN__ +#define WORD2 r2 +#define SHIFT r3 +#else /* __BIG_ENDIAN__ */ +#define WORD2 r3 +#define SHIFT r2 +#endif /* _ENDIAN__ */ + +.global memcmp +.align 4 +memcmp: + or %r12, %r0, %r1 + asl_s %r12, %r12, 30 + sub %r3, %r2, 1 + brls %r2, %r12, .Lbytewise + ld %r4, [%r0, 0] + ld %r5, [%r1, 0] + lsr.f %lp_count, %r3, 3 + lpne .Loop_end + ld_s WORD2, [%r0, 4] + ld_s %r12, [%r1, 4] + brne %r4, %r5, .Leven + ld.a %r4, [%r0, 8] + ld.a %r5, [%r1, 8] + brne WORD2, %r12, .Lodd +.Loop_end: + asl_s SHIFT, SHIFT, 3 + bhs_s .Last_cmp + brne %r4, %r5, .Leven + ld %r4, [%r0, 4] + ld %r5, [%r1, 4] +#ifdef __LITTLE_ENDIAN__ + nop_s + /* one more load latency cycle */ +.Last_cmp: + xor %r0, %r4, %r5 + bset %r0, %r0, SHIFT + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + b.d .Leven_cmp + and %r1, %r1, 24 +.Leven: + xor %r0, %r4, %r5 + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + /* slow track insn */ + and %r1, %r1, 24 +.Leven_cmp: + asl %r2, %r4, %r1 + asl %r12, %r5, %r1 + lsr_s %r2, %r2, 1 + lsr_s %r12, %r12, 1 + j_s.d [%blink] + sub %r0, %r2, %r12 + .balign 4 +.Lodd: + xor %r0, WORD2, %r12 + sub_s %r1, %r0, 1 + bic_s %r1, %r1, %r0 + norm %r1, %r1 + /* slow track insn */ + and %r1, %r1, 24 + asl_s %r2, %r2, %r1 + asl_s %r12, %r12, %r1 + lsr_s %r2, %r2, 1 + lsr_s %r12, %r12, 1 + j_s.d [%blink] + sub %r0, %r2, %r12 +#else /* __BIG_ENDIAN__ */ +.Last_cmp: + neg_s SHIFT, SHIFT + lsr %r4, %r4, SHIFT + lsr %r5, %r5, SHIFT + /* slow track insn */ +.Leven: + sub.f %r0, %r4, %r5 + mov.ne %r0, 1 + j_s.d [%blink] + bset.cs %r0, %r0, 31 +.Lodd: + cmp_s WORD2, %r12 + + mov_s %r0, 1 + j_s.d [%blink] + bset.cs %r0, %r0, 31 +#endif /* _ENDIAN__ */ + .balign 4 +.Lbytewise: + breq %r2, 0, .Lnil + ldb %r4, [%r0, 0] + ldb %r5, [%r1, 0] + lsr.f %lp_count, %r3 + lpne .Lbyte_end + ldb_s %r3, [%r0, 1] + ldb %r12, [%r1, 1] + brne %r4, %r5, .Lbyte_even + ldb.a %r4, [%r0, 2] + ldb.a %r5, [%r1, 2] + brne %r3, %r12, .Lbyte_odd +.Lbyte_end: + bcc .Lbyte_even + brne %r4, %r5, .Lbyte_even + ldb_s %r3, [%r0, 1] + ldb_s %r12, [%r1, 1] +.Lbyte_odd: + j_s.d [%blink] + sub %r0, %r3, %r12 +.Lbyte_even: + j_s.d [%blink] + sub %r0, %r4, %r5 +.Lnil: + j_s.d [%blink] + mov %r0, 0 diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S new file mode 100644 index 0000000000..51dd73ab8f --- /dev/null +++ b/arch/arc/lib/memcpy-700.S @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.global memcpy +.align 4 +memcpy: + or %r3, %r0, %r1 + asl_s %r3, %r3, 30 + mov_s %r5, %r0 + brls.d %r2, %r3, .Lcopy_bytewise + sub.f %r3, %r2, 1 + ld_s %r12, [%r1, 0] + asr.f %lp_count, %r3, 3 + bbit0.d %r3, 2, .Lnox4 + bmsk_s %r2, %r2, 1 + st.ab %r12, [%r5, 4] + ld.a %r12, [%r1, 4] +.Lnox4: + lppnz .Lendloop + ld_s %r3, [%r1, 4] + st.ab %r12, [%r5, 4] + ld.a %r12, [%r1, 8] + st.ab %r3, [%r5, 4] +.Lendloop: + breq %r2, 0, .Last_store + ld %r3, [%r5, 0] +#ifdef __LITTLE_ENDIAN__ + add3 %r2, -1, %r2 + /* uses long immediate */ + xor_s %r12, %r12, %r3 + bmsk %r12, %r12, %r2 + xor_s %r12, %r12, %r3 +#else /* __BIG_ENDIAN__ */ + sub3 %r2, 31, %r2 + /* uses long immediate */ + xor_s %r3, %r3, %r12 + bmsk %r3, %r3, %r2 + xor_s %r12, %r12, %r3 +#endif /* _ENDIAN__ */ +.Last_store: + j_s.d [%blink] + st %r12, [%r5, 0] + + .balign 4 +.Lcopy_bytewise: + jcs [%blink] + ldb_s %r12, [%r1, 0] + lsr.f %lp_count, %r3 + bhs_s .Lnox1 + stb.ab %r12, [%r5, 1] + ldb.a %r12, [%r1, 1] +.Lnox1: + lppnz .Lendbloop + ldb_s %r3, [%r1, 1] + stb.ab %r12, [%r5, 1] + ldb.a %r12, [%r1, 2] + stb.ab %r3, [%r5, 1] +.Lendbloop: + j_s.d [%blink] + stb %r12, [%r5, 0] diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S new file mode 100644 index 0000000000..017e8af0e8 --- /dev/null +++ b/arch/arc/lib/memset.S @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */ + +.global memset +.align 4 +memset: + mov_s %r4, %r0 + or %r12, %r0, %r2 + bmsk.f %r12, %r12, 1 + extb_s %r1, %r1 + asl %r3, %r1, 8 + beq.d .Laligned + or_s %r1, %r1, %r3 + brls %r2, SMALL, .Ltiny + add %r3, %r2, %r0 + stb %r1, [%r3, -1] + bclr_s %r3, %r3, 0 + stw %r1, [%r3, -2] + bmsk.f %r12, %r0, 1 + add_s %r2, %r2, %r12 + sub.ne %r2, %r2, 4 + stb.ab %r1, [%r4, 1] + and %r4, %r4, -2 + stw.ab %r1, [%r4, 2] + and %r4, %r4, -4 + + .balign 4 +.Laligned: + asl %r3, %r1, 16 + lsr.f %lp_count, %r2, 2 + or_s %r1, %r1, %r3 + lpne .Loop_end + st.ab %r1, [%r4, 4] +.Loop_end: + j_s [%blink] + + .balign 4 +.Ltiny: + mov.f %lp_count, %r2 + lpne .Ltiny_end + stb.ab %r1, [%r4, 1] +.Ltiny_end: + j_s [%blink] + +/* + * memzero: @r0 = mem, @r1 = size_t + * memset: @r0 = mem, @r1 = char, @r2 = size_t + */ + +.global memzero +.align 4 +memzero: + /* adjust bzero args to memset args */ + mov %r2, %r1 + mov %r1, 0 + /* tail call so need to tinker with blink */ + b memset diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c new file mode 100644 index 0000000000..7797782563 --- /dev/null +++ b/arch/arc/lib/relocate.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Base functionality is taken from x86 version with added ARC-specifics + */ +int do_elf_reloc_fixups(void) +{ + Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start); + Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end); + + Elf32_Addr *offset_ptr_rom, *last_offset = NULL; + Elf32_Addr *offset_ptr_ram; + + do { + /* Get the location from the relocation entry */ + offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; + + /* Check that the location of the relocation is in .text */ + if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start && + offset_ptr_rom > last_offset) { + unsigned int val; + /* Switch to the in-RAM version */ + offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom + + gd->reloc_off); + + /* + * Use "memcpy" because target location might be + * 16-bit aligned on ARC so we may need to read + * byte-by-byte. On attempt to read entire word by + * CPU throws an exception + */ + memcpy(&val, offset_ptr_ram, sizeof(int)); + +#ifdef __LITTLE_ENDIAN__ + /* If location in ".text" section swap value */ + if ((unsigned int)offset_ptr_rom < + (unsigned int)&__ivt_end) + val = (val << 16) | (val >> 16); +#endif + + /* Check that the target points into executable */ + if (val >= (unsigned int)&__image_copy_start && val <= + (unsigned int)&__image_copy_end) { + val += gd->reloc_off; +#ifdef __LITTLE_ENDIAN__ + /* If location in ".text" section swap value */ + if ((unsigned int)offset_ptr_rom < + (unsigned int)&__ivt_end) + val = (val << 16) | (val >> 16); +#endif + memcpy(offset_ptr_ram, &val, sizeof(int)); + } + } + last_offset = offset_ptr_rom; + + } while (++re_src < re_end); + + return 0; +} diff --git a/arch/arc/lib/reset.c b/arch/arc/lib/reset.c new file mode 100644 index 0000000000..98ebf1d445 --- /dev/null +++ b/arch/arc/lib/reset.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + printf("Put your restart handler here\n"); + +#ifdef DEBUG + /* Stop debug session here */ + __asm__("brk"); +#endif + return 0; +} diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c new file mode 100644 index 0000000000..a72c6946d5 --- /dev/null +++ b/arch/arc/lib/sections.c @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * For some reason linker sets linker-generated symbols to zero in PIE mode. + * A work-around is substitution of linker-generated symbols with + * compiler-generated symbols which are properly handled by linker in PAE mode. + */ + +char __bss_start[0] __attribute__((section(".__bss_start"))); +char __bss_end[0] __attribute__((section(".__bss_end"))); +char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); +char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); +char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); +char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); +char __text_start[0] __attribute__((section(".__text_start"))); +char __text_end[0] __attribute__((section(".__text_end"))); +char __init_end[0] __attribute__((section(".__init_end"))); +char __ivt_start[0] __attribute__((section(".__ivt_start"))); +char __ivt_end[0] __attribute__((section(".__ivt_end"))); diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S new file mode 100644 index 0000000000..55fcc9fb00 --- /dev/null +++ b/arch/arc/lib/strchr-700.S @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * ARC700 has a relatively long pipeline and branch prediction, so we want + * to avoid branches that are hard to predict. On the other hand, the + * presence of the norm instruction makes it easier to operate on whole + * words branch-free. + */ + +.global strchr +.align 4 +strchr: + extb_s %r1, %r1 + asl %r5, %r1, 8 + bmsk %r2, %r0, 1 + or %r5, %r5, %r1 + mov_s %r3, 0x01010101 + breq.d %r2, %r0, .Laligned + asl %r4, %r5, 16 + sub_s %r0, %r0, %r2 + asl %r7, %r2, 3 + ld_s %r2, [%r0] +#ifdef __LITTLE_ENDIAN__ + asl %r7, %r3, %r7 +#else /* __BIG_ENDIAN__ */ + lsr %r7, %r3, %r7 +#endif /* _ENDIAN__ */ + or %r5, %r5, %r4 + ror %r4, %r3 + sub %r12, %r2, %r7 + bic_s %r12, %r12, %r2 + and %r12, %r12, %r4 + brne.d %r12, 0, .Lfound0_ua + xor %r6, %r2, %r5 + ld.a %r2, [%r0, 4] + sub %r12, %r6, %r7 + bic %r12, %r12, %r6 +#ifdef __LITTLE_ENDIAN__ + and %r7, %r12, %r4 + /* For speed, we want this branch to be unaligned. */ + breq %r7, 0, .Loop + /* Likewise this one */ + b .Lfound_char +#else /* __BIG_ENDIAN__ */ + and %r12, %r12, %r4 + /* For speed, we want this branch to be unaligned. */ + breq %r12, 0, .Loop + lsr_s %r12, %r12, 7 + bic %r2, %r7, %r6 + b.d .Lfound_char_b + and_s %r2, %r2, %r12 +#endif /* _ENDIAN__ */ + /* We require this code address to be unaligned for speed... */ +.Laligned: + ld_s %r2, [%r0] + or %r5, %r5, %r4 + ror %r4, %r3 + /* ... so that this code address is aligned, for itself and ... */ +.Loop: + sub %r12, %r2, %r3 + bic_s %r12, %r12, %r2 + and %r12, %r12, %r4 + brne.d %r12, 0, .Lfound0 + xor %r6, %r2, %r5 + ld.a %r2, [%r0, 4] + sub %r12, %r6, %r3 + bic %r12, %r12, %r6 + and %r7, %r12, %r4 + breq %r7, 0, .Loop + /* + *... so that this branch is unaligned. + * Found searched-for character. + * r0 has already advanced to next word. + */ +#ifdef __LITTLE_ENDIAN__ + /* + * We only need the information about the first matching byte + * (i.e. the least significant matching byte) to be exact, + * hence there is no problem with carry effects. + */ +.Lfound_char: + sub %r3, %r7, 1 + bic %r3, %r3, %r7 + norm %r2, %r3 + sub_s %r0, %r0, 1 + asr_s %r2, %r2, 3 + j.d [%blink] + sub_s %r0, %r0, %r2 + + .balign 4 +.Lfound0_ua: + mov %r3, %r7 +.Lfound0: + sub %r3, %r6, %r3 + bic %r3, %r3, %r6 + and %r2, %r3, %r4 + or_s %r12, %r12, %r2 + sub_s %r3, %r12, 1 + bic_s %r3, %r3, %r12 + norm %r3, %r3 + add_s %r0, %r0, 3 + asr_s %r12, %r3, 3 + asl.f 0, %r2, %r3 + sub_s %r0, %r0, %r12 + j_s.d [%blink] + mov.pl %r0, 0 +#else /* __BIG_ENDIAN__ */ +.Lfound_char: + lsr %r7, %r7, 7 + + bic %r2, %r7, %r6 +.Lfound_char_b: + norm %r2, %r2 + sub_s %r0, %r0, 4 + asr_s %r2, %r2, 3 + j.d [%blink] + add_s %r0, %r0, %r2 + +.Lfound0_ua: + mov_s %r3, %r7 +.Lfound0: + asl_s %r2, %r2, 7 + or %r7, %r6, %r4 + bic_s %r12, %r12, %r2 + sub %r2, %r7, %r3 + or %r2, %r2, %r6 + bic %r12, %r2, %r12 + bic.f %r3, %r4, %r12 + norm %r3, %r3 + + add.pl %r3, %r3, 1 + asr_s %r12, %r3, 3 + asl.f 0, %r2, %r3 + add_s %r0, %r0, %r12 + j_s.d [%blink] + mov.mi %r0, 0 +#endif /* _ENDIAN__ */ diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S new file mode 100644 index 0000000000..8cb7d2f18c --- /dev/null +++ b/arch/arc/lib/strcmp.S @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This is optimized primarily for the ARC700. + * It would be possible to speed up the loops by one cycle / word + * respective one cycle / byte by forcing double source 1 alignment, unrolling + * by a factor of two, and speculatively loading the second word / byte of + * source 1; however, that would increase the overhead for loop setup / finish, + * and strcmp might often terminate early. + */ + +.global strcmp +.align 4 +strcmp: + or %r2, %r0, %r1 + bmsk_s %r2, %r2, 1 + brne %r2, 0, .Lcharloop + mov_s %r12, 0x01010101 + ror %r5, %r12 +.Lwordloop: + ld.ab %r2, [%r0, 4] + ld.ab %r3, [%r1, 4] + nop_s + sub %r4, %r2, %r12 + bic %r4, %r4, %r2 + and %r4, %r4, %r5 + brne %r4, 0, .Lfound0 + breq %r2 ,%r3, .Lwordloop +#ifdef __LITTLE_ENDIAN__ + xor %r0, %r2, %r3 /* mask for difference */ + sub_s %r1, %r0, 1 + bic_s %r0, %r0, %r1 /* mask for least significant difference bit */ + sub %r1, %r5, %r0 + xor %r0, %r5, %r1 /* mask for least significant difference byte */ + and_s %r2, %r2, %r0 + and_s %r3, %r3, %r0 +#endif /* _ENDIAN__ */ + cmp_s %r2, %r3 + mov_s %r0, 1 + j_s.d [%blink] + bset.lo %r0, %r0, 31 + + .balign 4 +#ifdef __LITTLE_ENDIAN__ +.Lfound0: + xor %r0, %r2, %r3 /* mask for difference */ + or %r0, %r0, %r4 /* or in zero indicator */ + sub_s %r1, %r0, 1 + bic_s %r0, %r0, %r1 /* mask for least significant difference bit */ + sub %r1, %r5, %r0 + xor %r0, %r5, %r1 /* mask for least significant difference byte */ + and_s %r2, %r2, %r0 + and_s %r3, %r3, %r0 + sub.f %r0, %r2, %r3 + mov.hi %r0, 1 + j_s.d [%blink] + bset.lo %r0, %r0, 31 +#else /* __BIG_ENDIAN__ */ + /* + * The zero-detection above can mis-detect 0x01 bytes as zeroes + * because of carry-propagateion from a lower significant zero byte. + * We can compensate for this by checking that bit0 is zero. + * This compensation is not necessary in the step where we + * get a low estimate for r2, because in any affected bytes + * we already have 0x00 or 0x01, which will remain unchanged + * when bit 7 is cleared. + */ + .balign 4 +.Lfound0: + lsr %r0, %r4, 8 + lsr_s %r1, %r2 + bic_s %r2, %r2, %r0 /* get low estimate for r2 and get ... */ + bic_s %r0, %r0, %r1 /* */ + or_s %r3, %r3, %r0 /* ... high estimate r3 so that r2 > r3 will */ + cmp_s %r3, %r2 /* ... be independent of trailing garbage */ + or_s %r2, %r2, %r0 /* likewise for r3 > r2 */ + bic_s %r3, %r3, %r0 + rlc %r0, 0 /* r0 := r2 > r3 ? 1 : 0 */ + cmp_s %r2, %r3 + j_s.d [%blink] + bset.lo %r0, %r0, 31 +#endif /* _ENDIAN__ */ + + .balign 4 +.Lcharloop: + ldb.ab %r2,[%r0,1] + ldb.ab %r3,[%r1,1] + nop_s + breq %r2, 0, .Lcmpend + breq %r2, %r3, .Lcharloop +.Lcmpend: + j_s.d [%blink] + sub %r0, %r2, %r3 diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S new file mode 100644 index 0000000000..41bb53e501 --- /dev/null +++ b/arch/arc/lib/strcpy-700.S @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * If dst and src are 4 byte aligned, copy 8 bytes at a time. + * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get + * it 8 byte aligned. Thus, we can do a little read-ahead, without + * dereferencing a cache line that we should not touch. + * Note that short and long instructions have been scheduled to avoid + * branch stalls. + * The beq_s to r3z could be made unaligned & long to avoid a stall + * there, but it is not likely to be taken often, and it would also be likely + * to cost an unaligned mispredict at the next call. + */ + +.global strcpy +.align 4 +strcpy: + or %r2, %r0, %r1 + bmsk_s %r2, %r2, 1 + brne.d %r2, 0, charloop + mov_s %r10, %r0 + ld_s %r3, [%r1, 0] + mov %r8, 0x01010101 + bbit0.d %r1, 2, loop_start + ror %r12, %r8 + sub %r2, %r3, %r8 + bic_s %r2, %r2, %r3 + tst_s %r2,%r12 + bne r3z + mov_s %r4,%r3 + .balign 4 +loop: + ld.a %r3, [%r1, 4] + st.ab %r4, [%r10, 4] +loop_start: + ld.a %r4, [%r1, 4] + sub %r2, %r3, %r8 + bic_s %r2, %r2, %r3 + tst_s %r2, %r12 + bne_s r3z + st.ab %r3, [%r10, 4] + sub %r2, %r4, %r8 + bic %r2, %r2, %r4 + tst %r2, %r12 + beq loop + mov_s %r3, %r4 +#ifdef __LITTLE_ENDIAN__ +r3z: bmsk.f %r1, %r3, 7 + lsr_s %r3, %r3, 8 +#else /* __BIG_ENDIAN__ */ +r3z: lsr.f %r1, %r3, 24 + asl_s %r3, %r3, 8 +#endif /* _ENDIAN__ */ + bne.d r3z + stb.ab %r1, [%r10, 1] + j_s [%blink] + + .balign 4 +charloop: + ldb.ab %r3, [%r1, 1] + brne.d %r3, 0, charloop + stb.ab %r3, [%r10, 1] + j [%blink] diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S new file mode 100644 index 0000000000..666e22c0d5 --- /dev/null +++ b/arch/arc/lib/strlen.S @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.global strlen +.align 4 +strlen: + or %r3, %r0, 7 + ld %r2, [%r3, -7] + ld.a %r6, [%r3, -3] + mov %r4, 0x01010101 + /* uses long immediate */ +#ifdef __LITTLE_ENDIAN__ + asl_s %r1, %r0, 3 + btst_s %r0, 2 + asl %r7, %r4, %r1 + ror %r5, %r4 + sub %r1, %r2, %r7 + bic_s %r1, %r1, %r2 + mov.eq %r7, %r4 + sub %r12, %r6, %r7 + bic %r12, %r12, %r6 + or.eq %r12, %r12, %r1 + and %r12, %r12, %r5 + brne %r12, 0, .Learly_end +#else /* __BIG_ENDIAN__ */ + ror %r5, %r4 + btst_s %r0, 2 + mov_s %r1, 31 + sub3 %r7, %r1, %r0 + sub %r1, %r2, %r4 + bic_s %r1, %r1, %r2 + bmsk %r1, %r1, %r7 + sub %r12, %r6, %r4 + bic %r12, %r12, %r6 + bmsk.ne %r12, %r12, %r7 + or.eq %r12, %r12, %r1 + and %r12, %r12, %r5 + brne %r12, 0, .Learly_end +#endif /* _ENDIAN__ */ + +.Loop: + ld_s %r2, [%r3, 4] + ld.a %r6, [%r3, 8] + /* stall for load result */ + sub %r1, %r2, %r4 + bic_s %r1, %r1, %r2 + sub %r12, %r6, %r4 + bic %r12, %r12, %r6 + or %r12, %r12, %r1 + and %r12, %r12, %r5 + breq %r12, 0, .Loop +.Lend: + and.f %r1, %r1, %r5 + sub.ne %r3, %r3, 4 + mov.eq %r1, %r12 +#ifdef __LITTLE_ENDIAN__ + sub_s %r2, %r1, 1 + bic_s %r2, %r2, %r1 + norm %r1, %r2 + sub_s %r0, %r0, 3 + lsr_s %r1, %r1, 3 + sub %r0, %r3, %r0 + j_s.d [%blink] + sub %r0, %r0, %r1 +#else /* __BIG_ENDIAN__ */ + lsr_s %r1, %r1, 7 + mov.eq %r2, %r6 + bic_s %r1, %r1, %r2 + norm %r1, %r1 + sub %r0, %r3, %r0 + lsr_s %r1, %r1, 3 + j_s.d [%blink] + add %r0, %r0, %r1 +#endif /* _ENDIAN */ +.Learly_end: + b.d .Lend + sub_s.ne %r1, %r1, %r1 diff --git a/arch/arc/lib/timer.c b/arch/arc/lib/timer.c new file mode 100644 index 0000000000..a0acbbc01a --- /dev/null +++ b/arch/arc/lib/timer.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */ + +int timer_init(void) +{ + write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); + /* Set max value for counter/timer */ + write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); + /* Set initial count value and restart counter/timer */ + write_aux_reg(ARC_AUX_TIMER0_CNT, 0); + return 0; +} + +unsigned long timer_read_counter(void) +{ + return read_aux_reg(ARC_AUX_TIMER0_CNT); +} diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig new file mode 100644 index 0000000000..b3297f1547 --- /dev/null +++ b/arch/arm/Kconfig @@ -0,0 +1,1097 @@ +menu "ARM architecture" + depends on ARM + +config SYS_ARCH + default "arm" + +config ARM64 + bool + +config HAS_VBAR + bool + +config CPU_ARM720T + bool + +config CPU_ARM920T + bool + +config CPU_ARM926EJS + bool + +config CPU_ARM946ES + bool + +config CPU_ARM1136 + bool + +config CPU_ARM1176 + bool + select HAS_VBAR + +config CPU_V7 + bool + select HAS_VBAR + +config CPU_PXA + bool + +config CPU_SA1100 + bool + +config SYS_CPU + default "arm720t" if CPU_ARM720T + default "arm920t" if CPU_ARM920T + default "arm926ejs" if CPU_ARM926EJS + default "arm946es" if CPU_ARM946ES + default "arm1136" if CPU_ARM1136 + default "arm1176" if CPU_ARM1176 + default "armv7" if CPU_V7 + default "pxa" if CPU_PXA + default "sa1100" if CPU_SA1100 + default "armv8" if ARM64 + +config SEMIHOSTING + bool "support boot from semihosting" + help + In emulated environments, semihosting is a way for + the hosted environment to call out to the emulator to + retrieve files from the host machine. + +config SOC_AM335X + bool + select CPU_V7 + select OMAP_COMMON + +config SOC_MXS + bool + select CPU_ARM926EJS + +config SOC_MX23 + bool + select SOC_MXS + +config SOC_MX28 + bool + select SOC_MXS + +config SOC_MX5 + bool + select CPU_V7 + +config SOC_MX53 + bool + select SOC_MX5 + +config SOC_MX51 + bool + select SOC_MX5 + +config SOC_MX53 + bool + select SOC_MX5 + +config SOC_MX6 + bool + select CPU_V7 + +config SOC_MX6Q + bool + select SOC_MX6 + +config SOC_MX6DL + bool + select SOC_MX6 + +config SOC_MX6S + bool + select SOC_MX6 + +config SOC_MX6SX + bool + select SOC_MX6 + +config SOC_SAMA5D4 + bool + select CPU_V7 + +choice + prompt "Target select" + +config TARGET_INTEGRATORAP_CM720T + bool "Support integratorap_cm720t" + select CPU_ARM720T + +config TARGET_INTEGRATORAP_CM920T + bool "Support integratorap_cm920t" + select CPU_ARM920T + +config TARGET_INTEGRATORCP_CM920T + bool "Support integratorcp_cm920t" + select CPU_ARM920T + +config TARGET_A320EVB + bool "Support a320evb" + select CPU_ARM920T + +config TARGET_AT91RM9200EK + bool "Support at91rm9200ek" + select CPU_ARM920T + +config TARGET_EB_CPUX9K2 + bool "Support eb_cpux9k2" + select CPU_ARM920T + +config TARGET_CPUAT91 + bool "Support cpuat91" + select CPU_ARM920T + +config TARGET_EDB93XX + bool "Support edb93xx" + select CPU_ARM920T + +config TARGET_SCB9328 + bool "Support scb9328" + select CPU_ARM920T + +config TARGET_CM4008 + bool "Support cm4008" + select CPU_ARM920T + +config TARGET_CM41XX + bool "Support cm41xx" + select CPU_ARM920T + +config TARGET_VCMA9 + bool "Support VCMA9" + select CPU_ARM920T + +config TARGET_SMDK2410 + bool "Support smdk2410" + select CPU_ARM920T + +config TARGET_INTEGRATORAP_CM926EJS + bool "Support integratorap_cm926ejs" + select CPU_ARM926EJS + +config TARGET_INTEGRATORCP_CM926EJS + bool "Support integratorcp_cm926ejs" + select CPU_ARM926EJS + +config TARGET_ASPENITE + bool "Support aspenite" + select CPU_ARM926EJS + +config TARGET_GPLUGD + bool "Support gplugd" + select CPU_ARM926EJS + +config TARGET_AFEB9260 + bool "Support afeb9260" + select CPU_ARM926EJS + +config TARGET_AT91SAM9260EK + bool "Support at91sam9260ek" + select CPU_ARM926EJS + +config TARGET_AT91SAM9261EK + bool "Support at91sam9261ek" + select CPU_ARM926EJS + +config TARGET_AT91SAM9263EK + bool "Support at91sam9263ek" + select CPU_ARM926EJS + +config TARGET_AT91SAM9M10G45EK + bool "Support at91sam9m10g45ek" + select CPU_ARM926EJS + +config TARGET_AT91SAM9N12EK + bool "Support at91sam9n12ek" + select CPU_ARM926EJS + +config TARGET_AT91SAM9RLEK + bool "Support at91sam9rlek" + select CPU_ARM926EJS + +config TARGET_AT91SAM9X5EK + bool "Support at91sam9x5ek" + select CPU_ARM926EJS + +config TARGET_SNAPPER9260 + bool "Support snapper9260" + select CPU_ARM926EJS + +config TARGET_VL_MA2SC + bool "Support vl_ma2sc" + select CPU_ARM926EJS + +config TARGET_SBC35_A9G20 + bool "Support sbc35_a9g20" + select CPU_ARM926EJS + +config TARGET_TNY_A9260 + bool "Support tny_a9260" + select CPU_ARM926EJS + +config TARGET_USB_A9263 + bool "Support usb_a9263" + select CPU_ARM926EJS + +config TARGET_ETHERNUT5 + bool "Support ethernut5" + select CPU_ARM926EJS + +config TARGET_MEESC + bool "Support meesc" + select CPU_ARM926EJS + +config TARGET_OTC570 + bool "Support otc570" + select CPU_ARM926EJS + +config TARGET_CPU9260 + bool "Support cpu9260" + select CPU_ARM926EJS + +config TARGET_PM9261 + bool "Support pm9261" + select CPU_ARM926EJS + +config TARGET_PM9263 + bool "Support pm9263" + select CPU_ARM926EJS + +config TARGET_PM9G45 + bool "Support pm9g45" + select CPU_ARM926EJS + +config TARGET_CORVUS + select SUPPORT_SPL + bool "Support corvus" + select CPU_ARM926EJS + +config TARGET_TAURUS + select SUPPORT_SPL + bool "Support taurus" + select CPU_ARM926EJS + +config TARGET_STAMP9G20 + bool "Support stamp9g20" + select CPU_ARM926EJS + +config ARCH_DAVINCI + bool "TI DaVinci" + select CPU_ARM926EJS + help + Support for TI's DaVinci platform. + +config KIRKWOOD + bool "Marvell Kirkwood" + select CPU_ARM926EJS + +config TARGET_DB_MV784MP_GP + bool "Support db-mv784mp-gp" + select CPU_V7 + +config TARGET_MAXBCM + bool "Support maxbcm" + select CPU_V7 + +config TARGET_DEVKIT3250 + bool "Support devkit3250" + select CPU_ARM926EJS + +config TARGET_JADECPU + bool "Support jadecpu" + select CPU_ARM926EJS + +config TARGET_MX25PDK + bool "Support mx25pdk" + select CPU_ARM926EJS + +config TARGET_TX25 + bool "Support tx25" + select SOC_MX25 + select SUPPORT_SPL + +config TARGET_TX28 + bool "Support tx28" + select SOC_MX28 + select SUPPORT_SPL + +config TARGET_TX48 + bool "Support tx48" + select SOC_AM335X + select SUPPORT_SPL + +config TARGET_TX51 + bool "Support tx51" + select SOC_MX51 + +config TARGET_TX53 + bool "Support tx53" + select SOC_MX53 + +config TARGET_TX6 + bool "Support tx6" + select SOC_MX6 + +config TARGET_TXA5 + bool "Support txA5" + select SOC_SAMA5D4 + +config TARGET_ZMX25 + bool "Support zmx25" + select CPU_ARM926EJS + +config TARGET_APF27 + bool "Support apf27" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_IMX27LITE + bool "Support imx27lite" + select CPU_ARM926EJS + +config TARGET_MAGNESIUM + bool "Support magnesium" + select CPU_ARM926EJS + +config TARGET_APX4DEVKIT + bool "Support apx4devkit" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_XFI3 + bool "Support xfi3" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_M28EVK + bool "Support m28evk" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_MX23EVK + bool "Support mx23evk" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_MX28EVK + bool "Support mx28evk" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_MX23_OLINUXINO + bool "Support mx23_olinuxino" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_BG0900 + bool "Support bg0900" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_SANSA_FUZE_PLUS + bool "Support sansa_fuze_plus" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_SC_SPS_1 + bool "Support sc_sps_1" + select CPU_ARM926EJS + select SUPPORT_SPL + +config ARCH_NOMADIK + bool "ST-Ericsson Nomadik" + select CPU_ARM926EJS + +config ORION5X + bool "Marvell Orion" + select CPU_ARM926EJS + +config TARGET_DKB + bool "Support dkb" + select CPU_ARM926EJS + +config TARGET_SPEAR300 + bool "Support spear300" + select CPU_ARM926EJS + +config TARGET_SPEAR310 + bool "Support spear310" + select CPU_ARM926EJS + +config TARGET_SPEAR320 + bool "Support spear320" + select CPU_ARM926EJS + +config TARGET_SPEAR600 + bool "Support spear600" + select CPU_ARM926EJS + +config TARGET_STV0991 + bool "Support stv0991" + select CPU_V7 + +config TARGET_X600 + bool "Support x600" + select CPU_ARM926EJS + select SUPPORT_SPL + +config ARCH_VERSATILE + bool "ARM Ltd. Versatile family" + select CPU_ARM926EJS + +config TARGET_INTEGRATORCP_CM1136 + bool "Support integratorcp_cm1136" + select CPU_ARM1136 + +config TARGET_IMX31_PHYCORE + bool "Support imx31_phycore" + select CPU_ARM1136 + +config TARGET_QONG + bool "Support qong" + select CPU_ARM1136 + +config TARGET_MX31ADS + bool "Support mx31ads" + select CPU_ARM1136 + +config TARGET_MX31PDK + bool "Support mx31pdk" + select CPU_ARM1136 + select SUPPORT_SPL + +config TARGET_TT01 + bool "Support tt01" + select CPU_ARM1136 + +config TARGET_IMX31_LITEKIT + bool "Support imx31_litekit" + select CPU_ARM1136 + +config TARGET_WOODBURN + bool "Support woodburn" + select CPU_ARM1136 + +config TARGET_WOODBURN_SD + bool "Support woodburn_sd" + select CPU_ARM1136 + select SUPPORT_SPL + +config TARGET_FLEA3 + bool "Support flea3" + select CPU_ARM1136 + +config TARGET_MX35PDK + bool "Support mx35pdk" + select CPU_ARM1136 + +config TARGET_RPI + bool "Support rpi" + select CPU_ARM1176 + +config TARGET_TNETV107X_EVM + bool "Support tnetv107x_evm" + select CPU_ARM1176 + +config TARGET_INTEGRATORAP_CM946ES + bool "Support integratorap_cm946es" + select CPU_ARM946ES + +config TARGET_INTEGRATORCP_CM946ES + bool "Support integratorcp_cm946es" + select CPU_ARM946ES + +config TARGET_VEXPRESS_CA15_TC2 + bool "Support vexpress_ca15_tc2" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + +config TARGET_VEXPRESS_CA5X2 + bool "Support vexpress_ca5x2" + select CPU_V7 + +config TARGET_VEXPRESS_CA9X4 + bool "Support vexpress_ca9x4" + select CPU_V7 + +config TARGET_KWB + bool "Support kwb" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_TSERIES + bool "Support tseries" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_CM_T335 + bool "Support cm_t335" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_PEPPER + bool "Support pepper" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_AM335X_IGEP0033 + bool "Support am335x_igep0033" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_PCM051 + bool "Support pcm051" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_DRACO + bool "Support draco" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_DXR2 + bool "Support dxr2" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_PXM2 + bool "Support pxm2" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_RUT + bool "Support rut" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_PENGWYN + bool "Support pengwyn" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_AM335X_EVM + bool "Support am335x_evm" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_AM43XX_EVM + bool "Support am43xx_evm" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_TI814X_EVM + bool "Support ti814x_evm" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_TI816X_EVM + bool "Support ti816x_evm" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_SAMA5D3_XPLAINED + bool "Support sama5d3_xplained" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_SAMA5D3XEK + bool "Support sama5d3xek" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_SAMA5D4_XPLAINED + bool "Support sama5d4_xplained" + select CPU_V7 + +config TARGET_SAMA5D4EK + bool "Support sama5d4ek" + select CPU_V7 + +config TARGET_BCM28155_AP + bool "Support bcm28155_ap" + select CPU_V7 + +config TARGET_BCMCYGNUS + bool "Support bcmcygnus" + select CPU_V7 + +config TARGET_BCMNSP + bool "Support bcmnsp" + select CPU_V7 + +config ARCH_EXYNOS + bool "Samsung EXYNOS" + select CPU_V7 + +config ARCH_S5PC1XX + bool "Samsung S5PC1XX" + select CPU_V7 + +config ARCH_HIGHBANK + bool "Calxeda Highbank" + select CPU_V7 + +config ARCH_KEYSTONE + bool "TI Keystone" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_M53EVK + bool "Support m53evk" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_IMA3_MX53 + bool "Support ima3-mx53" + select CPU_V7 + +config TARGET_MX51EVK + bool "Support mx51evk" + select CPU_V7 + +config TARGET_MX53ARD + bool "Support mx53ard" + select CPU_V7 + +config TARGET_MX53EVK + bool "Support mx53evk" + select CPU_V7 + +config TARGET_MX53LOCO + bool "Support mx53loco" + select CPU_V7 + +config TARGET_MX53SMD + bool "Support mx53smd" + select CPU_V7 + +config TARGET_MX51_EFIKAMX + bool "Support mx51_efikamx" + select CPU_V7 + +config TARGET_VISION2 + bool "Support vision2" + select CPU_V7 + +config TARGET_UDOO + bool "Support udoo" + select CPU_V7 + +config TARGET_WANDBOARD + bool "Support wandboard" + select CPU_V7 + +config TARGET_TITANIUM + bool "Support titanium" + select CPU_V7 + +config TARGET_NITROGEN6X + bool "Support nitrogen6x" + select CPU_V7 + +config TARGET_CGTQMX6EVAL + bool "Support cgtqmx6eval" + select CPU_V7 + +config TARGET_EMBESTMX6BOARDS + bool "Support embestmx6boards" + select CPU_V7 + +config TARGET_ARISTAINETOS + bool "Support aristainetos" + select CPU_V7 + +config TARGET_MX6QARM2 + bool "Support mx6qarm2" + select CPU_V7 + +config TARGET_MX6QSABREAUTO + bool "Support mx6qsabreauto" + select CPU_V7 + +config TARGET_MX6SABRESD + bool "Support mx6sabresd" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_MX6SLEVK + bool "Support mx6slevk" + select CPU_V7 + +config TARGET_MX6SXSABRESD + bool "Support mx6sxsabresd" + select CPU_V7 + +config TARGET_GW_VENTANA + bool "Support gw_ventana" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_HUMMINGBOARD + bool "Support hummingboard" + select CPU_V7 + +config TARGET_KOSAGI_NOVENA + bool "Support Kosagi Novena" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_TBS2910 + bool "Support tbs2910" + select CPU_V7 + +config TARGET_TQMA6 + bool "TQ Systems TQMa6 board" + select CPU_V7 + +config TARGET_OT1200 + bool "Bachmann OT1200" + select CPU_V7 + +config OMAP34XX + bool "OMAP34XX SoC" + select CPU_V7 + select OMAP_COMMON + +config OMAP44XX + bool "OMAP44XX SoC" + select CPU_V7 + select OMAP_COMMON + select SUPPORT_SPL + +config OMAP54XX + bool "OMAP54XX SoC" + select CPU_V7 + select OMAP_COMMON + select SUPPORT_SPL + +config RMOBILE + bool "Renesas ARM SoCs" + select CPU_V7 + +config TARGET_CM_FX6 + bool "Support cm_fx6" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_SOCFPGA_CYCLONE5 + bool "Support socfpga_cyclone5" + select CPU_V7 + select SUPPORT_SPL + +config ARCH_SUNXI + bool "Support sunxi (Allwinner) SoCs" + +config TARGET_SNOWBALL + bool "Support snowball" + select CPU_V7 + +config TARGET_U8500_HREF + bool "Support u8500_href" + select CPU_V7 + +config TARGET_VF610TWR + bool "Support vf610twr" + select CPU_V7 + +config ZYNQ + bool "Xilinx Zynq Platform" + select CPU_V7 + select SUPPORT_SPL + +config TEGRA + bool "NVIDIA Tegra" + select SUPPORT_SPL + select SPL + select OF_CONTROL if !SPL_BUILD + select CPU_ARM720T if SPL_BUILD + select CPU_V7 if !SPL_BUILD + +config TARGET_VEXPRESS64_AEMV8A + bool "Support vexpress_aemv8a" + select ARM64 + +config TARGET_VEXPRESS64_BASE_FVP + bool "Support Versatile Express ARMv8a FVP BASE model" + select ARM64 + select SEMIHOSTING + +config TARGET_VEXPRESS64_JUNO + bool "Support Versatile Express Juno Development Platform" + select ARM64 + +config TARGET_LS2085A_EMU + bool "Support ls2085a_emu" + select ARM64 + +config TARGET_LS2085A_SIMU + bool "Support ls2085a_simu" + select ARM64 + +config TARGET_LS1021AQDS + bool "Support ls1021aqds" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_LS1021ATWR + bool "Support ls1021atwr" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_BALLOON3 + bool "Support balloon3" + select CPU_PXA + +config TARGET_H2200 + bool "Support h2200" + select CPU_PXA + +config TARGET_PALMLD + bool "Support palmld" + select CPU_PXA + +config TARGET_PALMTC + bool "Support palmtc" + select CPU_PXA + +config TARGET_PALMTREO680 + bool "Support palmtreo680" + select CPU_PXA + select SUPPORT_SPL + +config TARGET_PXA255_IDP + bool "Support pxa255_idp" + select CPU_PXA + +config TARGET_TRIZEPSIV + bool "Support trizepsiv" + select CPU_PXA + +config TARGET_VPAC270 + bool "Support vpac270" + select CPU_PXA + select SUPPORT_SPL + +config TARGET_XAENIAX + bool "Support xaeniax" + select CPU_PXA + +config TARGET_ZIPITZ2 + bool "Support zipitz2" + select CPU_PXA + +config TARGET_LP8X4X + bool "Support lp8x4x" + select CPU_PXA + +config TARGET_COLIBRI_PXA270 + bool "Support colibri_pxa270" + select CPU_PXA + +config TARGET_JORNADA + bool "Support jornada" + select CPU_SA1100 + +config ARCH_UNIPHIER + bool "Panasonic UniPhier platform" + select CPU_V7 + select SUPPORT_SPL + select SPL + select OF_CONTROL if !SPL_BUILD + +endchoice + +source "arch/arm/cpu/arm926ejs/davinci/Kconfig" + +source "arch/arm/cpu/armv7/exynos/Kconfig" + +source "arch/arm/cpu/armv7/highbank/Kconfig" + +source "arch/arm/cpu/armv7/keystone/Kconfig" + +source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig" + +source "arch/arm/cpu/arm926ejs/nomadik/Kconfig" + +source "arch/arm/cpu/armv7/omap3/Kconfig" + +source "arch/arm/cpu/armv7/omap4/Kconfig" + +source "arch/arm/cpu/armv7/omap5/Kconfig" + +source "arch/arm/cpu/arm926ejs/orion5x/Kconfig" + +source "arch/arm/cpu/armv7/rmobile/Kconfig" + +source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" + +source "arch/arm/cpu/armv7/tegra-common/Kconfig" + +source "arch/arm/cpu/armv7/uniphier/Kconfig" + +source "arch/arm/cpu/arm926ejs/versatile/Kconfig" + +source "arch/arm/cpu/armv7/zynq/Kconfig" + +source "arch/arm/cpu/armv7/Kconfig" + +source "board/aristainetos/Kconfig" +source "board/BuR/kwb/Kconfig" +source "board/BuR/tseries/Kconfig" +source "board/BuS/eb_cpux9k2/Kconfig" +source "board/BuS/vl_ma2sc/Kconfig" +source "board/CarMediaLab/flea3/Kconfig" +source "board/Marvell/aspenite/Kconfig" +source "board/Marvell/db-mv784mp-gp/Kconfig" +source "board/Marvell/dkb/Kconfig" +source "board/Marvell/gplugd/Kconfig" +source "board/afeb9260/Kconfig" +source "board/altera/socfpga/Kconfig" +source "board/armadeus/apf27/Kconfig" +source "board/armltd/integrator/Kconfig" +source "board/armltd/vexpress/Kconfig" +source "board/armltd/vexpress64/Kconfig" +source "board/atmel/at91rm9200ek/Kconfig" +source "board/atmel/at91sam9260ek/Kconfig" +source "board/atmel/at91sam9261ek/Kconfig" +source "board/atmel/at91sam9263ek/Kconfig" +source "board/atmel/at91sam9m10g45ek/Kconfig" +source "board/atmel/at91sam9n12ek/Kconfig" +source "board/atmel/at91sam9rlek/Kconfig" +source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d3_xplained/Kconfig" +source "board/atmel/sama5d3xek/Kconfig" +source "board/atmel/sama5d4_xplained/Kconfig" +source "board/atmel/sama5d4ek/Kconfig" +source "board/bachmann/ot1200/Kconfig" +source "board/balloon3/Kconfig" +source "board/barco/titanium/Kconfig" +source "board/bluegiga/apx4devkit/Kconfig" +source "board/bluewater/snapper9260/Kconfig" +source "board/boundary/nitrogen6x/Kconfig" +source "board/broadcom/bcm28155_ap/Kconfig" +source "board/broadcom/bcmcygnus/Kconfig" +source "board/broadcom/bcmnsp/Kconfig" +source "board/calao/sbc35_a9g20/Kconfig" +source "board/calao/tny_a9260/Kconfig" +source "board/calao/usb_a9263/Kconfig" +source "board/cirrus/edb93xx/Kconfig" +source "board/cm4008/Kconfig" +source "board/cm41xx/Kconfig" +source "board/compulab/cm_t335/Kconfig" +source "board/compulab/cm_fx6/Kconfig" +source "board/congatec/cgtqmx6eval/Kconfig" +source "board/creative/xfi3/Kconfig" +source "board/davedenx/qong/Kconfig" +source "board/denx/m28evk/Kconfig" +source "board/denx/m53evk/Kconfig" +source "board/egnite/ethernut5/Kconfig" +source "board/embest/mx6boards/Kconfig" +source "board/esd/meesc/Kconfig" +source "board/esd/otc570/Kconfig" +source "board/esg/ima3-mx53/Kconfig" +source "board/eukrea/cpu9260/Kconfig" +source "board/eukrea/cpuat91/Kconfig" +source "board/faraday/a320evb/Kconfig" +source "board/freescale/ls2085a/Kconfig" +source "board/freescale/ls1021aqds/Kconfig" +source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/mx23evk/Kconfig" +source "board/freescale/mx25pdk/Kconfig" +source "board/freescale/mx28evk/Kconfig" +source "board/freescale/mx31ads/Kconfig" +source "board/freescale/mx31pdk/Kconfig" +source "board/freescale/mx35pdk/Kconfig" +source "board/freescale/mx51evk/Kconfig" +source "board/freescale/mx53ard/Kconfig" +source "board/freescale/mx53evk/Kconfig" +source "board/freescale/mx53loco/Kconfig" +source "board/freescale/mx53smd/Kconfig" +source "board/freescale/mx6qarm2/Kconfig" +source "board/freescale/mx6qsabreauto/Kconfig" +source "board/freescale/mx6sabresd/Kconfig" +source "board/freescale/mx6slevk/Kconfig" +source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/vf610twr/Kconfig" +source "board/gateworks/gw_ventana/Kconfig" +source "board/genesi/mx51_efikamx/Kconfig" +source "board/gumstix/pepper/Kconfig" +source "board/h2200/Kconfig" +source "board/hale/tt01/Kconfig" +source "board/icpdas/lp8x4x/Kconfig" +source "board/imx31_phycore/Kconfig" +source "board/isee/igep0033/Kconfig" +source "board/jornada/Kconfig" +source "board/karo/tx25/Kconfig" +source "board/karo/tx28/Kconfig" +source "board/karo/tx48/Kconfig" +source "board/karo/tx51/Kconfig" +source "board/karo/tx53/Kconfig" +source "board/karo/tx6/Kconfig" +source "board/karo/txa5/Kconfig" +source "board/kosagi/novena/Kconfig" +source "board/logicpd/imx27lite/Kconfig" +source "board/logicpd/imx31_litekit/Kconfig" +source "board/maxbcm/Kconfig" +source "board/mpl/vcma9/Kconfig" +source "board/olimex/mx23_olinuxino/Kconfig" +source "board/palmld/Kconfig" +source "board/palmtc/Kconfig" +source "board/palmtreo680/Kconfig" +source "board/phytec/pcm051/Kconfig" +source "board/ppcag/bg0900/Kconfig" +source "board/pxa255_idp/Kconfig" +source "board/raspberrypi/rpi/Kconfig" +source "board/ronetix/pm9261/Kconfig" +source "board/ronetix/pm9263/Kconfig" +source "board/ronetix/pm9g45/Kconfig" +source "board/samsung/smdk2410/Kconfig" +source "board/sandisk/sansa_fuze_plus/Kconfig" +source "board/scb9328/Kconfig" +source "board/schulercontrol/sc_sps_1/Kconfig" +source "board/siemens/corvus/Kconfig" +source "board/siemens/draco/Kconfig" +source "board/siemens/pxm2/Kconfig" +source "board/siemens/rut/Kconfig" +source "board/siemens/taurus/Kconfig" +source "board/silica/pengwyn/Kconfig" +source "board/solidrun/hummingboard/Kconfig" +source "board/spear/spear300/Kconfig" +source "board/spear/spear310/Kconfig" +source "board/spear/spear320/Kconfig" +source "board/spear/spear600/Kconfig" +source "board/spear/x600/Kconfig" +source "board/st-ericsson/snowball/Kconfig" +source "board/st-ericsson/u8500/Kconfig" +source "board/st/stv0991/Kconfig" +source "board/sunxi/Kconfig" +source "board/syteco/jadecpu/Kconfig" +source "board/syteco/zmx25/Kconfig" +source "board/taskit/stamp9g20/Kconfig" +source "board/tbs/tbs2910/Kconfig" +source "board/ti/am335x/Kconfig" +source "board/ti/am43xx/Kconfig" +source "board/ti/ti814x/Kconfig" +source "board/ti/ti816x/Kconfig" +source "board/ti/tnetv107xevm/Kconfig" +source "board/timll/devkit3250/Kconfig" +source "board/toradex/colibri_pxa270/Kconfig" +source "board/tqc/tqma6/Kconfig" +source "board/trizepsiv/Kconfig" +source "board/ttcontrol/vision2/Kconfig" +source "board/udoo/Kconfig" +source "board/vpac270/Kconfig" +source "board/wandboard/Kconfig" +source "board/woodburn/Kconfig" +source "board/xaeniax/Kconfig" +source "board/zipitz2/Kconfig" + +source "arch/arm/Kconfig.debug" + +endmenu diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug new file mode 100644 index 0000000000..624bcf4682 --- /dev/null +++ b/arch/arm/Kconfig.debug @@ -0,0 +1,64 @@ +menu "ARM debug" + +config DEBUG_LL + bool "Low-level debugging functions" + depends on !ARM64 + help + Say Y here to include definitions of printascii, printch, printhex + in U-Boot. This is helpful if you are debugging code that + executes before the console is initialized. + +choice + prompt "Low-level debugging port" + depends on DEBUG_LL + + config DEBUG_LL_UART_8250 + bool "Low-level debugging via 8250 UART" + help + Say Y here if you wish the debug print routes to direct + their output to an 8250 UART. You can use this option + to provide the parameters for the 8250 UART rather than + selecting one of the platform specific options above if + you know the parameters for the port. + + This option is preferred over the platform specific + options; the platform specific options are deprecated + and will be soon removed. + +endchoice + +config DEBUG_LL_INCLUDE + string + depends on DEBUG_LL + default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 + default "mach/debug-macro.S" + +# Compatibility options for 8250 +config DEBUG_UART_8250 + bool + +config DEBUG_UART_PHYS + hex "Physical base address of debug UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + +# This is not used in U-Boot +config DEBUG_UART_VIRT + hex + default DEBUG_UART_PHYS + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + +config DEBUG_UART_8250_SHIFT + int "Register offset shift for the 8250 debug UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + default 2 + +config DEBUG_UART_8250_WORD + bool "Use 32-bit accesses for 8250 UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + depends on DEBUG_UART_8250_SHIFT >= 2 + +config DEBUG_UART_8250_FLOW_CONTROL + bool "Enable flow control for 8250 UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + +endmenu diff --git a/arch/arm/Makefile b/arch/arm/Makefile new file mode 100644 index 0000000000..c68144fb5f --- /dev/null +++ b/arch/arm/Makefile @@ -0,0 +1,29 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/arm/cpu/$(CPU)/start.o + +ifeq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_SPL_START_S_PATH),) +head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o +endif +endif + +libs-y += arch/arm/cpu/$(CPU)/ +libs-y += arch/arm/cpu/ +libs-y += arch/arm/lib/ + +ifeq ($(CONFIG_SPL_BUILD),y) +ifneq (,$(CONFIG_SOC_MX23)$(CONFIG_SOC_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +libs-y += arch/arm/imx-common/ +endif +else +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) +libs-y += arch/arm/imx-common/ +endif +endif + +ifneq (,$(filter $(SOC), armada-xp kirkwood)) +libs-y += arch/arm/mvebu-common/ +endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index f9908e5ae6..5182949568 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -5,10 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= arm-linux- - ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 else CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 @@ -16,16 +14,21 @@ endif endif LDFLAGS_FINAL += --gc-sections -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \ + -fno-common -ffixed-r9 +PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ + $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) # Support generic board on ARM __HAVE_ARCH_GENERIC_BOARD := y -PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ +PLATFORM_CPPFLAGS += -D__ARM__ # Choose between ARM/Thumb instruction sets ifeq ($(CONFIG_SYS_THUMB_BUILD),y) -PF_CPPFLAGS_ARM := $(call cc-option, -mthumb -mthumb-interwork,\ +AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) +PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \ + $(call cc-option, -mthumb -mthumb-interwork,\ $(call cc-option,-marm,)\ $(call cc-option,-mno-thumb-interwork,)\ ) @@ -36,7 +39,17 @@ endif # Only test once ifneq ($(CONFIG_SPL_BUILD),y) -ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb +ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +archprepare: checkthumb + +checkthumb: + @if test "$(call cc-version)" -lt "0404"; then \ + echo -n '*** Your GCC does not produce working '; \ + echo 'binaries in THUMB mode.'; \ + echo '*** Your board is configured for THUMB mode.'; \ + false; \ + fi +endif endif # Try if EABI is supported, else fall back to old ABI, @@ -64,13 +77,8 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) # times. Also, the prefix needs to be different based on whether # CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry # before adding the correct one. -ifdef CONFIG_SPL_BUILD -PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \ - $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) -else -PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \ - $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) -endif +PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \ + $(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) endif # needed for relocation @@ -94,7 +102,36 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls endif endif -# check that only R_ARM_RELATIVE relocations are generated ifneq ($(CONFIG_SPL_BUILD),y) -ALL-y += checkarmreloc +# Check that only R_ARM_RELATIVE relocations are generated. +ALL-y += checkarmreloc +# The movt / movw can hardcode 16 bit parts of the addresses in the +# instruction. Relocation is not supported for that case, so disable +# such usage by requiring word relocations. +PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) +endif + +# limit ourselves to the sections we want in the .bin. +ifdef CONFIG_ARM64 +OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn +else +OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn +endif + +ifdef CONFIG_OF_EMBED +OBJCOPYFLAGS += -j .dtb.init.rodata +endif + +ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +ALL-y += SPL +endif +else +ifeq ($(CONFIG_OF_SEPARATE),y) +ALL-y += u-boot-dtb.imx +else +ALL-y += u-boot.imx +endif +endif endif diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile new file mode 100644 index 0000000000..35d8d387bd --- /dev/null +++ b/arch/arm/cpu/Makefile @@ -0,0 +1,6 @@ +obj-$(CONFIG_AT91FAMILY) += at91-common/ +obj-$(CONFIG_TEGRA20) += tegra20-common/ +obj-$(CONFIG_TEGRA30) += tegra30-common/ +obj-$(CONFIG_TEGRA114) += tegra114-common/ +obj-$(CONFIG_TEGRA124) += tegra124-common/ +obj-$(CONFIG_TEGRA) += tegra-common/ diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile index cc516f744b..d2b4898832 100644 --- a/arch/arm/cpu/arm1136/Makefile +++ b/arch/arm/cpu/arm1136/Makefile @@ -5,27 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y = start.o +obj-y = cpu.o -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_SOC_MX31) += mx31/ +obj-$(CONFIG_SOC_MX35) += mx35/ diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index 1ef6061365..a82c6cec9c 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -4,24 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) - -ifneq ($(CONFIG_IMX_CONFIG),) -ifdef CONFIG_SPL -ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/SPL -endif -else -ALL-y += $(obj)u-boot.imx -endif -endif diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile index c75adec6e9..9670ed9382 100644 --- a/arch/arm/cpu/arm1136/mx31/Makefile +++ b/arch/arm/cpu/arm1136/mx31/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS += generic.o -COBJS += timer.o -COBJS += devices.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += generic.o +obj-y += timer.o +obj-y += devices.o diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index f111242e53..3a81ce427c 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -7,9 +7,6 @@ #include #include -#include -#include -#include #include #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ @@ -28,57 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * "time" is measured in 1 / CONFIG_SYS_HZ seconds, - * "tick" is internal timer period - */ - -#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= MXC_CLK32; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * MXC_CLK32 + 999999; - do_div(us, 1000000); - return us; -} -#else -/* ~2% error */ -#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / MXC_CLK32) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - do_div(tick, TICK_PER_TIME); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - return time * TICK_PER_TIME; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us += US_PER_TICK - 1; - do_div(us, US_PER_TICK); - return us; -} -#endif - /* The 32768Hz 32-bit timer overruns in 131072 seconds */ int timer_init(void) { @@ -95,53 +41,7 @@ int timer_init(void) return 0; } -unsigned long long get_ticks(void) -{ - ulong now = GPTCNT; /* current tick value */ - - if (now >= gd->arch.lastinc) /* normal mode (non roll) */ - /* move stamp forward with absolut diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - else /* we have rollover of incrementer */ - gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now; - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) +unsigned long timer_read_counter(void) { - return MXC_CLK32; + return GPTCNT; } diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile index ee534a92d3..c533215c3a 100644 --- a/arch/arm/cpu/arm1136/mx35/Makefile +++ b/arch/arm/cpu/arm1136/mx35/Makefile @@ -7,28 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS += generic.o -COBJS += timer.o -COBJS += mx35_sdram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += generic.o +obj-y += timer.o +obj-y += mx35_sdram.o diff --git a/arch/arm/cpu/arm1136/mx35/asm-offsets.c b/arch/arm/cpu/arm1136/mx35/asm-offsets.c deleted file mode 100644 index ebd7575039..0000000000 --- a/arch/arm/cpu/arm1136/mx35/asm-offsets.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - /* Round up to make sure size gives nice stack alignment */ - DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); - DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); - DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); - DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); - DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); - DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); - DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); - DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); - DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); - DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); - DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); - DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); - DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); - DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); - DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); - - /* Multi-Layer AHB Crossbar Switch */ - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); - DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); - - /* AHB <-> IP-Bus Interface */ - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); - DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); - DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); - DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); - DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); - DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); - DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); - DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); - DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); - DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); - - return 0; -} diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index 8d3f92cae9..bc98edda7a 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -531,7 +531,7 @@ u32 spl_boot_mode(void) switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: #ifdef CONFIG_SPL_FAT_SUPPORT - return MMCSD_MODE_FAT; + return MMCSD_MODE_FS; #else return MMCSD_MODE_RAW; #endif diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index cc6166f938..4edf533e2a 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -9,43 +9,17 @@ #include #include -#include #include #include -#include DECLARE_GLOBAL_DATA_PTR; -#define timestamp (gd->arch.tbl) -#define lastinc (gd->arch.lastinc) - /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ #define GPTCR_FRR (1<<9) /* Freerun / restart */ #define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -/* - * "time" is measured in 1 / CONFIG_SYS_HZ seconds, - * "tick" is internal timer period - */ -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); - - return tick; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * MXC_CLK32 + 999999; - do_div(us, 1000000); - - return us; -} - /* * nothing really to do with interrupts, just starts up a counter. * The 32KHz 32-bit timer overruns in 134217 seconds @@ -71,60 +45,3 @@ int timer_init(void) return 0; } - -unsigned long long get_ticks(void) -{ - struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; - ulong now = readl(&gpt->counter); /* current tick value */ - - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timstamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return MXC_CLK32; -} diff --git a/arch/arm/cpu/arm1136/omap24xx/Makefile b/arch/arm/cpu/arm1136/omap24xx/Makefile deleted file mode 100644 index 7d76d96ca5..0000000000 --- a/arch/arm/cpu/arm1136/omap24xx/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS = reset.o - -COBJS = timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm1136/omap24xx/reset.S b/arch/arm/cpu/arm1136/omap24xx/reset.S deleted file mode 100644 index dd0752b289..0000000000 --- a/arch/arm/cpu/arm1136/omap24xx/reset.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * armboot - Startup Code for OMP2420/ARM1136 CPU-core - * - * Copyright (c) 2004 Texas Instruments - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.globl reset_cpu -reset_cpu: - ldr r1, rstctl /* get addr for global reset reg */ - mov r3, #0x2 /* full reset pll+mpu */ - str r3, [r1] /* force reset */ - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PM_RSTCTRL_WKUP diff --git a/arch/arm/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c deleted file mode 100644 index b1eef27dae..0000000000 --- a/arch/arm/cpu/arm1136/omap24xx/timer.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments - * Richard Woodruff - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) -#define TIMER_LOAD_VAL 0 - -/* macro to read the 32 bit timer */ -#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+TCRR) \ - / (TIMER_CLOCK / CONFIG_SYS_HZ) - -DECLARE_GLOBAL_DATA_PTR; - -int timer_init (void) -{ - int32_t val; - - /* Start the counter ticking up */ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ - val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ - - /* reset time */ - gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */ - gd->arch.tbl = 0; /* start "advancing" time stamp */ - - return(0); -} -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay (unsigned long usec) -{ - ulong tmo, tmp; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if ((tmo + tmp + 1) < tmp) { /* if setting this forward will roll */ - /* time stamp, then reset time */ - gd->arch.lastinc = READ_TIMER; /* capture incrementer value */ - gd->arch.tbl = 0; /* start time stamp */ - } else { - tmo += tmp; /* else, set advancing stamp wake up time */ - } - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ - /* move stamp fordward with absoulte diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - } else { - /* we have rollover of incrementer */ - gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ)) - - gd->arch.lastinc) + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = CONFIG_SYS_HZ; - return tbclk; -} diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index bd1e067599..1cfcca9fa6 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -9,54 +9,13 @@ * Copyright (c) 2003 Richard Woodruff * Copyright (c) 2003 Kshitij * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include -.globl _start -_start: b reset -#ifdef CONFIG_SPL_BUILD - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -70,52 +29,7 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -178,196 +92,3 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - ldr sp, _TEXT_BASE /* use 32 words about stack */ - bl hang /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -.global arm1136_cache_flush -arm1136_cache_flush: -#if !defined(CONFIG_SYS_ICACHE_OFF) - mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache -#endif -#if !defined(CONFIG_SYS_DCACHE_OFF) - mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache -#endif - mov pc, lr @ back to caller -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds index bccde73317..97e4a8bc87 100644 --- a/arch/arm/cpu/arm1136/u-boot-spl.lds +++ b/arch/arm/cpu/arm1136/u-boot-spl.lds @@ -22,6 +22,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/arm1136/start.o (.text*) *(.text*) } >.sram @@ -33,7 +34,11 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } .bss : { diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index 5d451a78b6..ead2303373 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -8,27 +8,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y = start.o +obj-y = cpu.o -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_BCM2835) += bcm2835/ +obj-$(CONFIG_TNETV107X) += tnetv107x/ diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile index 135de42d37..0ad36906df 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/cpu/arm1176/bcm2835/Makefile @@ -12,26 +12,5 @@ # GNU General Public License for more details. # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS := lowlevel_init.o -COBJS := init.o reset.o timer.o mbox.o - -SRCS := $(SOBJS:.o=.c) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := lowlevel_init.o +obj-y += init.o reset.o timer.o mbox.o diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk deleted file mode 100644 index b87ce244c3..0000000000 --- a/arch/arm/cpu/arm1176/bcm2835/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2012 Stephen Warren -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# Don't attempt to override the target CPU/ABI options; -# the Raspberry Pi toolchain does the right thing by default. -PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS)) -PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS)) diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/cpu/arm1176/bcm2835/mbox.c index 4daf1e410c..3b17a31eac 100644 --- a/arch/arm/cpu/arm1176/bcm2835/mbox.c +++ b/arch/arm/cpu/arm1176/bcm2835/mbox.c @@ -8,7 +8,7 @@ #include #include -#define TIMEOUT (100 * 1000) /* 100mS in uS */ +#define TIMEOUT 1000 /* ms */ int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv) { diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c index 2edd6711da..017907cfb8 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/cpu/arm1176/bcm2835/timer.c @@ -18,11 +18,6 @@ #include #include -int timer_init(void) -{ - return 0; -} - ulong get_timer_us(ulong base) { struct bcm2835_timer_regs *regs = diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk index 917da030d6..5dc2ebb27b 100644 --- a/arch/arm/cpu/arm1176/config.mk +++ b/arch/arm/cpu/arm1176/config.mk @@ -4,15 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ffd7dd0dcd..0704bdde27 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -22,48 +22,6 @@ #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE #endif -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - -.globl _start -_start: b reset -#ifndef CONFIG_SPL_BUILD - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq -_pad: - .word 0x12345678 /* now 16*4=64 */ -#else - . = _start + 64 -#endif - -.global _end_vect -_end_vect: - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -77,41 +35,7 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ - -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -209,150 +133,3 @@ skip_tcmdisable: c_runtime_cpu_setup: mov pc, lr - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - */ - - .macro bad_save_user_regs - /* carve out a frame on current user stack */ - sub sp, sp, #S_FRAME_SIZE - /* Save user registers (now in svc mode) r0-r12 */ - stmia sp, {r0 - r12} - - ldr r2, IRQ_STACK_START_IN - /* get values for "aborted" pc and cpsr (into parm regs) */ - ldmia r2, {r2 - r3} - /* grab pointer to old stack */ - add r0, sp, #S_FRAME_SIZE - - add r5, sp, #S_SP - mov r1, lr - /* save sp_SVC, lr_SVC, pc, cpsr */ - stmia r5, {r0 - r3} - /* save current stack into r0 (param register) */ - mov r0, sp - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - /* save caller lr in position 0 of saved stack */ - str lr, [r13] - /* get the spsr */ - mrs lr, spsr - /* save spsr in position 1 of saved stack */ - str lr, [r13, #4] - - /* prepare SVC-Mode */ - mov r13, #MODE_SVC - @ msr spsr_c, r13 - /* switch modes, make sure moves will execute */ - msr spsr, r13 - /* capture return pc */ - mov lr, pc - /* jump to next instruction & switch modes. */ - movs pc, lr - .endm - - .macro get_bad_stack_swi - /* space on current stack for scratch reg. */ - sub r13, r13, #4 - /* save R0's value. */ - str r0, [r13] - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - /* save caller lr in position 0 of saved stack */ - str lr, [r0] - /* get the spsr */ - mrs lr, spsr - /* save spsr in position 1 of saved stack */ - str lr, [r0, #4] - /* restore lr */ - ldr lr, [r0] - /* restore r0 */ - ldr r0, [r13] - /* pop stack entry */ - add r13, r13, #4 - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile index 1eb27edbd8..a4c1edfc71 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/Makefile +++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile @@ -2,28 +2,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS += aemif.o clock.o init.o mux.o timer.o -SOBJS += lowlevel_init.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) - -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += aemif.o clock.o init.o mux.o timer.o +obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c index 3708b6f59f..7ba28d329f 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/clock.c +++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c @@ -16,7 +16,7 @@ #define BIT(x) (1 << (x)) #define MAX_PREDIV 64 -#define MAX_POSTDIV 8 +#define MAX_POSTDIV 8UL #define MAX_MULT 512 #define MAX_DIV (MAX_PREDIV * MAX_POSTDIV) @@ -362,7 +362,7 @@ static void init_pll(const struct pll_init_data *data) pllctl_reg_write(data->pll, ctl, tmp); mult = data->pll_freq / fpll; - for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) { + for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) { div = (fpll * mult) / data->pll_freq; if (div < 1 || div > MAX_DIV) continue; diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile index 73e16354d0..9f61ea2516 100644 --- a/arch/arm/cpu/arm720t/Makefile +++ b/arch/arm/cpu/arm720t/Makefile @@ -5,27 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = interrupts.o cpu.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = interrupts.o cpu.o + +obj-$(CONFIG_TEGRA) += tegra-common/ +obj-$(CONFIG_TEGRA20) += tegra20/ +obj-$(CONFIG_TEGRA30) += tegra30/ +obj-$(CONFIG_TEGRA114) += tegra114/ +obj-$(CONFIG_TEGRA124) += tegra124/ diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk index 56b6280d5a..772fb413e8 100644 --- a/arch/arm/cpu/arm720t/config.mk +++ b/arch/arm/cpu/arm720t/config.mk @@ -6,14 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 90170d71ea..e8ba1ae09e 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -7,7 +7,7 @@ * Sysgo Real-Time Solutions, GmbH * Alex Zuepke * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index b6bfacfcfc..01c85be64b 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -4,7 +4,7 @@ * Copyright (c) 2001 Marius Gröger * Copyright (c) 2002 Alex Züpke * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -12,48 +12,6 @@ #include #include -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: .word _undefined_instruction -_software_interrupt: .word _software_interrupt -_prefetch_abort: .word _prefetch_abort -_data_abort: .word _data_abort -_not_used: .word _not_used -_irq: .word _irq -_fiq: .word _fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#else -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ - - .balignl 16,0xdeadbeef - - /* ************************************************************************* * @@ -67,52 +25,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */ ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -165,169 +78,3 @@ cpu_init_crit: mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile index 37ec43f163..a9c2b675ae 100644 --- a/arch/arm/cpu/arm720t/tegra-common/Makefile +++ b/arch/arm/cpu/arm720t/tegra-common/Makefile @@ -7,26 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libtegra-common.o - -COBJS-$(CONFIG_SPL_BUILD) += spl.o -COBJS-y += cpu.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_SPL_BUILD) += spl.o +obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 9294611be8..c6f3b029a1 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -49,57 +49,107 @@ int get_num_cpus(void) * Timing tables for each SOC for all four oscillator options. */ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { - /* T20: 1 GHz */ - /* n, m, p, cpcon */ - {{ 1000, 13, 0, 12}, /* OSC 13M */ - { 625, 12, 0, 8}, /* OSC 19.2M */ - { 1000, 12, 0, 12}, /* OSC 12M */ - { 1000, 26, 0, 12}, /* OSC 26M */ + /* + * T20: 1 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T25: 1.2 GHz */ - {{ 923, 10, 0, 12}, - { 750, 12, 0, 8}, - { 600, 6, 0, 12}, - { 600, 13, 0, 12}, + /* + * T25: 1.2 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T30: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 700, 6, 0, 8}, - { 700, 13, 0, 8}, + /* + * T30: 600 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + }, + /* + * T114: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ }, - /* T114: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 696, 12, 0, 8}, - { 700, 13, 0, 8}, + /* + * T124: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ }, }; -void adjust_pllp_out_freqs(void) +static inline void pllx_set_iddq(void) { +#if defined(CONFIG_TEGRA124) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH]; u32 reg; - /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ - reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */ - reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR - | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR; - writel(reg, &pll->pll_out[0]); - - reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */ - reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR - | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR; - writel(reg, &pll->pll_out[1]); + /* Disable IDDQ */ + reg = readl(&clkrst->crc_pllx_misc3); + reg &= ~PLLX_IDDQ_MASK; + writel(reg, &clkrst->crc_pllx_misc3); + udelay(2); + debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__, + readl(&clkrst->crc_pllx_misc3)); +#endif } int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) { + int chip = tegra_get_chip(); u32 reg; /* If PLLX is already enabled, just return */ @@ -110,31 +160,41 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, debug(" pllx_set_rate entry\n"); + pllx_set_iddq(); + /* Set BYPASS, m, n and p to PLLX_BASE */ reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT); reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT)); writel(reg, &pll->pll_base); /* Set cpcon to PLLX_MISC */ - reg = (cpcon << PLL_CPCON_SHIFT); + if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) + reg = (cpcon << PLL_CPCON_SHIFT); + else + reg = 0; /* Set dccon to PLLX_MISC if freq > 600MHz */ if (divn > 600) reg |= (1 << PLL_DCCON_SHIFT); writel(reg, &pll->pll_misc); - /* Enable PLLX */ - reg = readl(&pll->pll_base); - reg |= PLL_ENABLE_MASK; - /* Disable BYPASS */ + reg = readl(&pll->pll_base); reg &= ~PLL_BYPASS_MASK; writel(reg, &pll->pll_base); + debug("pllx_set_rate: base = 0x%08X\n", reg); /* Set lock_enable to PLLX_MISC */ reg = readl(&pll->pll_misc); reg |= PLL_LOCK_ENABLE_MASK; writel(reg, &pll->pll_misc); + debug("pllx_set_rate: misc = 0x%08X\n", reg); + + /* Enable PLLX last, once it's all configured */ + reg = readl(&pll->pll_base); + reg |= PLL_ENABLE_MASK; + writel(reg, &pll->pll_base); + debug("pllx_set_rate: base final = 0x%08X\n", reg); return 0; } @@ -168,12 +228,6 @@ void init_pllx(void) /* set pllx */ sel = &tegra_pll_x_table[chip_sku][osc]; pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); - - /* adjust PLLP_out1-4 on T3x/T114 */ - if (soc_type >= CHIPID_TEGRA30) { - debug(" init_pllx: adjusting PLLP out freqs\n"); - adjust_pllp_out_freqs(); - } } void enable_cpu_clock(int enable) @@ -295,7 +349,6 @@ void reset_A9_cpu(int reset) void clock_enable_coresight(int enable) { u32 rst, src = 2; - int soc_type; debug("clock_enable_coresight entry\n"); clock_set_enable(PERIPH_ID_CORESIGHT, enable); @@ -304,20 +357,11 @@ void clock_enable_coresight(int enable) if (enable) { /* * Put CoreSight on PLLP_OUT0 and divide it down as per - * PLLP base frequency based on SoC type (T20/T30/T114). + * PLLP base frequency based on SoC type (T20/T30+). * Clock divider request would setup CSITE clock as 144MHz * for PLLP base 216MHz and 204MHz for PLLP base 408MHz */ - - soc_type = tegra_get_chip(); - if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114) - src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000); - else if (soc_type == CHIPID_TEGRA20) - src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); - else - printf("%s: Unknown SoC type %X!\n", - __func__, soc_type); - + src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); /* Unlock the CPU CoreSight interfaces */ @@ -334,8 +378,7 @@ void clock_enable_coresight(int enable) void halt_avp(void) { for (;;) { - writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \ - | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)), - FLOW_CTLR_HALT_COP_EVENTS); + writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29), + FLOW_CTLR_HALT_COP_EVENTS); } } diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h index 60412c7f87..b4ca44fce1 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2011 + * (C) Copyright 2010-2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -11,9 +11,12 @@ #define IO_STABILIZATION_DELAY (1000) #if defined(CONFIG_TEGRA20) -#define NVBL_PLLP_KHZ (216000) -#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) -#define NVBL_PLLP_KHZ (408000) +#define NVBL_PLLP_KHZ 216000 +#define CSITE_KHZ 144000 +#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ + defined(CONFIG_TEGRA124) +#define NVBL_PLLP_KHZ 408000 +#define CSITE_KHZ 204000 #else #error "Unknown Tegra chip!" #endif @@ -68,3 +71,4 @@ int tegra_get_chip(void); int tegra_get_sku_info(void); int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); +void pmic_enable_cpu_vdd(void); diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 5171a8f907..e0f9d5b6b4 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -13,16 +13,18 @@ #include #include #include +#include #include -#include +#include #include "cpu.h" void spl_board_init(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; /* enable JTAG */ - writel(0xC0, &pmt->pmt_cfg_ctl); + writel(0xC0, &apb_misc->cfg_ctl); board_init_uart_f(); diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile b/arch/arm/cpu/arm720t/tegra114/Makefile index 6cf7fe9da9..ea3e55ea62 100644 --- a/arch/arm/cpu/arm720t/tegra114/Makefile +++ b/arch/arm/cpu/arm720t/tegra114/Makefile @@ -17,26 +17,5 @@ # along with this program. If not, see . # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -#COBJS-y += cpu.o t11x.o -COBJS-y += cpu.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +#obj-y += cpu.o t11x.o +obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra114/config.mk b/arch/arm/cpu/arm720t/tegra114/config.mk deleted file mode 100644 index 7947b50fd0..0000000000 --- a/arch/arm/cpu/arm720t/tegra114/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 51ecff794f..5ed3bb9d9a 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -34,8 +34,8 @@ static void enable_cpu_power_rail(void) debug("enable_cpu_power_rail entry\n"); /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ - pinmux_tristate_disable(PINGRP_PWR_I2C_SCL); - pinmux_tristate_disable(PINGRP_PWR_I2C_SDA); + pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); + pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); /* * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), @@ -68,7 +68,7 @@ static void enable_cpu_clocks(void) /* Wait for PLL-X to lock */ do { reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); - } while ((reg & (1 << 27)) == 0); + } while ((reg & PLL_LOCK_MASK) == 0); /* Wait until all clocks are stable */ udelay(PLL_STABILIZATION_DELAY); @@ -126,18 +126,6 @@ void t114_init_clocks(void) /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); - /* - * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run - * at 108 MHz. This is glitch free as only the source is changed, no - * special precaution needed. - */ - val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | - (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clkrst->crc_sclk_brst_pol); - writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); debug("Setting up PLLX\n"); @@ -204,45 +192,43 @@ void t114_init_clocks(void) debug("t114_init_clocks exit\n"); } -static int is_partition_powered(u32 mask) +static bool is_partition_powered(u32 partid) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; /* Get power gate status */ reg = readl(&pmc->pmc_pwrgate_status); - return (reg & mask) == mask; + return !!(reg & (1 << partid)); } -static int is_clamp_enabled(u32 mask) +static bool is_clamp_enabled(u32 partid) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; - /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */ - reg = readl(&pmc->pmc_pwrgate_timer_on); - return (reg & mask) == mask; + /* Get clamp status. */ + reg = readl(&pmc->pmc_clamp_status); + return !!(reg & (1 << partid)); } -static void power_partition(u32 status, u32 partid) +static void power_partition(u32 partid) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid); + debug("%s: part ID = %08X\n", __func__, partid); /* Is the partition already on? */ - if (!is_partition_powered(status)) { + if (!is_partition_powered(partid)) { /* No, toggle the partition power state (OFF -> ON) */ debug("power_partition, toggling state\n"); - clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F); - setbits_le32(&pmc->pmc_pwrgate_toggle, partid); - setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP); + writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); /* Wait for the power to come up */ - while (!is_partition_powered(status)) + while (!is_partition_powered(partid)) ; /* Wait for the clamp status to be cleared */ - while (is_clamp_enabled(status)) + while (is_clamp_enabled(partid)) ; /* Give I/O signals time to stabilize */ @@ -257,13 +243,13 @@ void powerup_cpus(void) /* We boot to the fast cluster */ debug("powerup_cpus entry: G cluster\n"); /* Power up the fast cluster rail partition */ - power_partition(CRAIL, CRAILID); + power_partition(CRAIL); /* Power up the fast cluster non-CPU partition */ - power_partition(C0NC, C0NCID); + power_partition(C0NC); /* Power up the fast cluster CPU0 partition */ - power_partition(CE0, CE0ID); + power_partition(CE0); } void start_cpu(u32 reset_vector) diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile new file mode 100644 index 0000000000..61abf45d3d --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra124/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c new file mode 100644 index 0000000000..6ff6aeb546 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra124/cpu.c @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../tegra-common/cpu.h" + +/* Tegra124-specific CPU init code */ + +static void enable_cpu_power_rail(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + debug("enable_cpu_power_rail entry\n"); + + /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ + pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); + pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); + + pmic_enable_cpu_vdd(); + + /* + * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), + * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h). + */ + writel(0x7C830, &pmc->pmc_cpupwrgood_timer); + + /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */ + clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); + setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); +} + +static void enable_cpu_clocks(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + debug("enable_cpu_clocks entry\n"); + + /* Wait for PLL-X to lock */ + do { + reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); + debug("%s: PLLX base = 0x%08X\n", __func__, reg); + } while ((reg & PLL_LOCK_MASK) == 0); + + debug("%s: PLLX locked, delay for stable clocks\n", __func__); + /* Wait until all clocks are stable */ + udelay(PLL_STABILIZATION_DELAY); + + debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__); + writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); + writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); + + debug("%s: Enabling clock to all CPUs\n", __func__); + /* Enable the clock to all CPUs */ + reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP | + CLR_CPU0_CLK_STP; + writel(reg, &clkrst->crc_clk_cpu_cmplx_clr); + + debug("%s: Enabling main CPU complex clocks\n", __func__); + /* Always enable the main CPU complex clocks */ + clock_enable(PERIPH_ID_CPU); + clock_enable(PERIPH_ID_CPULP); + clock_enable(PERIPH_ID_CPUG); + + debug("%s: Done\n", __func__); +} + +static void remove_cpu_resets(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + debug("remove_cpu_resets entry\n"); + + /* Take the slow and fast partitions out of reset */ + reg = CLR_NONCPURESET; + writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); + writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); + + /* Clear the SW-controlled reset of the slow cluster */ + reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | + CLR_L2RESET | CLR_PRESETDBG; + writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); + + /* Clear the SW-controlled reset of the fast cluster */ + reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | + CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | + CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | + CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 | + CLR_L2RESET | CLR_PRESETDBG; + writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); +} + +/** + * The Tegra124 requires some special clock initialization, including setting up + * the DVC I2C, turning on MSELECT and selecting the G CPU cluster + */ +void tegra124_init_clocks(void) +{ + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + debug("tegra124_init_clocks entry\n"); + + /* Set active CPU cluster to G */ + clrbits_le32(&flow->cluster_control, 1); + + /* Change the oscillator drive strength */ + val = readl(&clkrst->crc_osc_ctrl); + val &= ~OSC_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); + writel(val, &clkrst->crc_osc_ctrl); + + /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */ + val = readl(&pmc->pmc_osc_edpd_over); + val &= ~PMC_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT); + writel(val, &pmc->pmc_osc_edpd_over); + + /* Set HOLD_CKE_LOW_EN to 1 */ + setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN); + + debug("Setting up PLLX\n"); + init_pllx(); + + val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); + writel(val, &clkrst->crc_clk_sys_rate); + + /* Enable clocks to required peripherals. TBD - minimize this list */ + debug("Enabling clocks\n"); + + clock_set_enable(PERIPH_ID_CACHE2, 1); + clock_set_enable(PERIPH_ID_GPIO, 1); + clock_set_enable(PERIPH_ID_TMR, 1); + clock_set_enable(PERIPH_ID_CPU, 1); + clock_set_enable(PERIPH_ID_EMC, 1); + clock_set_enable(PERIPH_ID_I2C5, 1); + clock_set_enable(PERIPH_ID_APBDMA, 1); + clock_set_enable(PERIPH_ID_MEM, 1); + clock_set_enable(PERIPH_ID_CORESIGHT, 1); + clock_set_enable(PERIPH_ID_MSELECT, 1); + clock_set_enable(PERIPH_ID_DVFS, 1); + + /* + * Set MSELECT clock source as PLLP (00), and ask for a clock + * divider that would set the MSELECT clock at 102MHz for a + * PLLP base of 408MHz. + */ + clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, + CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); + + /* Give clock time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); + + /* Give clock time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + /* Take required peripherals out of reset */ + debug("Taking periphs out of reset\n"); + reset_set_enable(PERIPH_ID_CACHE2, 0); + reset_set_enable(PERIPH_ID_GPIO, 0); + reset_set_enable(PERIPH_ID_TMR, 0); + reset_set_enable(PERIPH_ID_COP, 0); + reset_set_enable(PERIPH_ID_EMC, 0); + reset_set_enable(PERIPH_ID_I2C5, 0); + reset_set_enable(PERIPH_ID_APBDMA, 0); + reset_set_enable(PERIPH_ID_MEM, 0); + reset_set_enable(PERIPH_ID_CORESIGHT, 0); + reset_set_enable(PERIPH_ID_MSELECT, 0); + reset_set_enable(PERIPH_ID_DVFS, 0); + + debug("tegra124_init_clocks exit\n"); +} + +static bool is_partition_powered(u32 partid) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + + /* Get power gate status */ + reg = readl(&pmc->pmc_pwrgate_status); + return !!(reg & (1 << partid)); +} + +static void power_partition(u32 partid) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + debug("%s: part ID = %08X\n", __func__, partid); + /* Is the partition already on? */ + if (!is_partition_powered(partid)) { + /* No, toggle the partition power state (OFF -> ON) */ + debug("power_partition, toggling state\n"); + writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); + + /* Wait for the power to come up */ + while (!is_partition_powered(partid)) + ; + + /* Give I/O signals time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + } +} + +void powerup_cpus(void) +{ + debug("powerup_cpus entry\n"); + + /* We boot to the fast cluster */ + debug("powerup_cpus entry: G cluster\n"); + + /* Power up the fast cluster rail partition */ + debug("powerup_cpus: CRAIL\n"); + power_partition(CRAIL); + + /* Power up the fast cluster non-CPU partition */ + debug("powerup_cpus: C0NC\n"); + power_partition(C0NC); + + /* Power up the fast cluster CPU0 partition */ + debug("powerup_cpus: CE0\n"); + power_partition(CE0); + + debug("powerup_cpus: done\n"); +} + +void start_cpu(u32 reset_vector) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + debug("start_cpu entry, reset_vector = %x\n", reset_vector); + + tegra124_init_clocks(); + + /* Set power-gating timer multiplier */ + writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT), + &pmc->pmc_pwrgate_timer_mult); + + enable_cpu_power_rail(); + enable_cpu_clocks(); + clock_enable_coresight(1); + remove_cpu_resets(); + writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); + powerup_cpus(); + debug("start_cpu exit, should continue @ reset_vector\n"); +} diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile index eef5922da7..12243fa9be 100644 --- a/arch/arm/cpu/arm720t/tegra20/Makefile +++ b/arch/arm/cpu/arm720t/tegra20/Makefile @@ -7,25 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y += cpu.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra20/config.mk b/arch/arm/cpu/arm720t/tegra20/config.mk deleted file mode 100644 index e073345223..0000000000 --- a/arch/arm/cpu/arm720t/tegra20/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2010,2011 -# NVIDIA Corporation -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# -USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile index bd969976e9..6ff4c55213 100644 --- a/arch/arm/cpu/arm720t/tegra30/Makefile +++ b/arch/arm/cpu/arm720t/tegra30/Makefile @@ -17,25 +17,4 @@ # along with this program. If not, see . # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y += cpu.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra30/config.mk b/arch/arm/cpu/arm720t/tegra30/config.mk deleted file mode 100644 index 2388c56db7..0000000000 --- a/arch/arm/cpu/arm720t/tegra30/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index e162357484..9003902e3f 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config) writel(config, ®->cnfg); } +#define TPS62366A_I2C_ADDR 0xC0 +#define TPS62366A_SET1_REG 0x01 +#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG) + +#define TPS62361B_I2C_ADDR 0xC0 +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + #define TPS65911_I2C_ADDR 0x5A #define TPS65911_VDDCTRL_OP_REG 0x28 #define TPS65911_VDDCTRL_SR_REG 0x27 -#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) #define I2C_SEND_2_BYTES 0x0A02 @@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void) reg |= CPUPWRREQ_OE; writel(reg, &pmc->pmc_cntrl); + /* Set VDD_CORE to 1.200V. */ +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 + tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES); +#endif +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 + tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES); +#endif + udelay(1000); + /* * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. - * First set VDD to 1.4V, then enable the VDD regulator. + * First set VDD to 1.0125V, then enable the VDD regulator. */ tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2); tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES); @@ -84,18 +103,6 @@ void t30_init_clocks(void) /* Set active CPU cluster to G */ clrbits_le32(flow->cluster_control, 1 << 0); - /* - * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run - * at 108 MHz. This is glitch free as only the source is changed, no - * special precaution needed. - */ - val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | - (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | - (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clkrst->crc_sclk_brst_pol); - writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) | diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 4758f025a0..a72e5de99e 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -5,29 +5,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y = start.o -LIB = $(obj)lib$(CPU).o +obj-y += cpu.o +obj-$(CONFIG_USE_IRQ) += interrupts.o -START = start.o - -COBJS-y += cpu.o -COBJS-$(CONFIG_USE_IRQ) += interrupts.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(if $(filter a320,$(SOC)),y) += a320/ +obj-$(CONFIG_AT91FAMILY) += at91/ +obj-$(CONFIG_EP93XX) += ep93xx/ +obj-$(CONFIG_IMX) += imx/ +obj-$(CONFIG_KS8695) += ks8695/ +obj-$(CONFIG_S3C24X0) += s3c24x0/ diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile index 88c7d9bb71..bbdab588c5 100644 --- a/arch/arm/cpu/arm920t/a320/Makefile +++ b/arch/arm/cpu/arm920t/a320/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS += reset.o -COBJS += timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += reset.o +obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/cpu/arm920t/at91/Makefile index b2b1e56a96..561b4b4cbb 100644 --- a/arch/arm/cpu/arm920t/at91/Makefile +++ b/arch/arm/cpu/arm920t/at91/Makefile @@ -5,30 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS += lowlevel_init.o -COBJS += reset.o -COBJS += timer.o -COBJS += clock.o -COBJS += cpu.o -COBJS += at91rm9200_devices.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += lowlevel_init.o +obj-y += reset.o +obj-y += timer.o +obj-y += clock.o +obj-y += cpu.o +obj-y += at91rm9200_devices.o diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk index 58fd756586..799afff028 100644 --- a/arch/arm/cpu/arm920t/config.mk +++ b/arch/arm/cpu/arm920t/config.mk @@ -5,13 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm920t/ep93xx/Makefile b/arch/arm/cpu/arm920t/ep93xx/Makefile index 7a75c86ae4..638333a484 100644 --- a/arch/arm/cpu/arm920t/ep93xx/Makefile +++ b/arch/arm/cpu/arm920t/ep93xx/Makefile @@ -16,26 +16,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).o - -COBJS = cpu.o led.o speed.o timer.o -SOBJS = lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cpu.o led.o speed.o timer.o +obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S index bf2fa2ac32..cfad206edd 100644 --- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S @@ -2,48 +2,457 @@ * Low-level initialization for EP93xx * * Copyright (C) 2009 Matthias Kaehlcke + * Copyright (C) 2013 + * Sergey Kostanabev fairwaves.ru> * * Copyright (C) 2006 Dominic Rath + * Copyright (C) 2006 Cirrus Logic Inc. + * + * See file CREDITS for list of people who contributed to this + * project. * * SPDX-License-Identifier: GPL-2.0+ */ -#include -#include +#include +#include + +/* +/* Configure the SDRAM based on the supplied settings. + * + * Input: r0 - SDRAM DEVCFG register + * r2 - configuration for SDRAM chips + * Output: none + * Modifies: r3, r4 + */ +ep93xx_sdram_config: + /* Program the SDRAM device configuration register. */ + ldr r3, =SDRAM_BASE +#ifdef CONFIG_EDB93XX_SDCS0 + str r0, [r3, #SDRAM_OFF_DEVCFG0] +#endif +#ifdef CONFIG_EDB93XX_SDCS1 + str r0, [r3, #SDRAM_OFF_DEVCFG1] +#endif +#ifdef CONFIG_EDB93XX_SDCS2 + str r0, [r3, #SDRAM_OFF_DEVCFG2] +#endif +#ifdef CONFIG_EDB93XX_SDCS3 + str r0, [r3, #SDRAM_OFF_DEVCFG3] +#endif + + /* Set the Initialize and MRS bits (issue continuous NOP commands + * (INIT & MRS set)) + */ + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \ + EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \ + EP93XX_SDRAMCTRL_GLOBALCFG_CKE) + str r4, [r3, #SDRAM_OFF_GLCONFIG] + + /* Delay for 200us. */ + mov r4, #0x3000 +delay1: + subs r4, r4, #1 + bne delay1 + + /* Clear the MRS bit to issue a precharge all. */ + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \ + EP93XX_SDRAMCTRL_GLOBALCFG_CKE) + str r4, [r3, #SDRAM_OFF_GLCONFIG] + + /* Temporarily set the refresh timer to 0x10. Make it really low so + * that refresh cycles are generated. + */ + ldr r4, =0x10 + str r4, [r3, #SDRAM_OFF_REFRSHTIMR] + + /* Delay for at least 80 SDRAM clock cycles. */ + mov r4, #80 +delay2: + subs r4, r4, #1 + bne delay2 + + /* Set the refresh timer to the fastest required for any device + * that might be used. Set 9.6 ms refresh time. + */ + ldr r4, =0x01e0 + str r4, [r3, #SDRAM_OFF_REFRSHTIMR] + + /* Select mode register update mode. */ + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \ + EP93XX_SDRAMCTRL_GLOBALCFG_MRS) + str r4, [r3, #SDRAM_OFF_GLCONFIG] + + /* Program the mode register on the SDRAM by performing fake read */ + ldr r4, [r2] + + /* Select normal operating mode. */ + ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE + str r4, [r3, #SDRAM_OFF_GLCONFIG] + + /* Return to the caller. */ + mov pc, lr + +/* + * Test to see if the SDRAM has been configured in a usable mode. + * + * Input: r0 - Test address of SDRAM + * Output: r0 - 0 -- Test OK, -1 -- Failed + * Modifies: r0-r5 + */ +ep93xx_sdram_test: + /* Load the test patterns to be written to SDRAM. */ + ldr r1, =0xf00dface + ldr r2, =0xdeadbeef + ldr r3, =0x08675309 + ldr r4, =0xdeafc0ed + + /* Store the test patterns to SDRAM. */ + stmia r0, {r1-r4} + + /* Load the test patterns from SDRAM one at a time and compare them + * to the actual pattern. + */ + ldr r5, [r0] + cmp r5, r1 + ldreq r5, [r0, #0x0004] + cmpeq r5, r2 + ldreq r5, [r0, #0x0008] + cmpeq r5, r3 + ldreq r5, [r0, #0x000c] + cmpeq r5, r4 + + /* Return -1 if a mismatch was encountered, 0 otherwise. */ + mvnne r0, #0xffffffff + moveq r0, #0x00000000 + + /* Return to the caller. */ + mov pc, lr + +/* + * Determine the size of the SDRAM. Use data=address for the scan. + * + * Input: r0 - Start SDRAM address + * Return: r0 - Single block size + * r1 - Valid block mask + * r2 - Total block count + * Modifies: r0-r5 + */ +ep93xx_sdram_size: + /* Store zero at offset zero. */ + str r0, [r0] + + /* Start checking for an alias at 1MB into SDRAM. */ + ldr r1, =0x00100000 + + /* Store the offset at the current offset. */ +check_block_size: + str r1, [r0, r1] + + /* Read back from zero. */ + ldr r2, [r0] + + /* Stop searching of an alias was found. */ + cmp r1, r2 + beq found_block_size + + /* Advance to the next power of two boundary. */ + mov r1, r1, lsl #1 + + /* Loop back if the size has not reached 256MB. */ + cmp r1, #0x10000000 + bne check_block_size + + /* A full 256MB of memory was found, so return it now. */ + ldr r0, =0x10000000 + ldr r1, =0x00000000 + ldr r2, =0x00000001 + mov pc, lr + + /* An alias was found. See if the first block is 128MB in size. */ +found_block_size: + cmp r1, #0x08000000 + + /* The first block is 128MB, so there is no further memory. Return it + * now. + */ + ldreq r0, =0x08000000 + ldreq r1, =0x00000000 + ldreq r2, =0x00000001 + moveq pc, lr + + /* Save the block size, set the block address bits to zero, and + * initialize the block count to one. + */ + mov r3, r1 + ldr r4, =0x00000000 + ldr r5, =0x00000001 + + /* Look for additional blocks of memory by searching for non-aliases. */ +find_blocks: + /* Store zero back to address zero. It may be overwritten. */ + str r0, [r0] + + /* Advance to the next power of two boundary. */ + mov r1, r1, lsl #1 + + /* Store the offset at the current offset. */ + str r1, [r0, r1] + + /* Read back from zero. */ + ldr r2, [r0] + + /* See if a non-alias was found. */ + cmp r1, r2 + + /* If a non-alias was found, then or in the block address bit and + * multiply the block count by two (since there are two unique + * blocks, one with this bit zero and one with it one). + */ + orrne r4, r4, r1 + movne r5, r5, lsl #1 + + /* Continue searching if there are more address bits to check. */ + cmp r1, #0x08000000 + bne find_blocks + + /* Return the block size, address mask, and count. */ + mov r0, r3 + mov r1, r4 + mov r2, r5 + + /* Return to the caller. */ + mov pc, lr + .globl lowlevel_init lowlevel_init: - /* backup return address */ - ldr r1, =SYSCON_SCRATCH0 - str lr, [r1] - /* Turn on both LEDs */ - bl red_led_on - bl green_led_on + mov r6, lr + + /* Make sure caches are off and invalidated. */ + ldr r0, =0x00000000 + mcr p15, 0, r0, c1, c0, 0 + nop + nop + nop + nop + nop + + /* Turn off the green LED and turn on the red LED. If the red LED + * is left on for too long, the external reset circuit described + * by application note AN258 will cause the system to reset. + */ + ldr r1, =EP93XX_LED_DATA + ldr r0, [r1] + bic r0, r0, #EP93XX_LED_GREEN_ON + orr r0, r0, #EP93XX_LED_RED_ON + str r0, [r1] + + /* Undo the silly static memory controller programming performed + * by the boot rom. + */ + ldr r0, =SMC_BASE + + /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */ + ldr r1, =0x0000fbe0 + + /* Reset EP93XX_OFF_SMCBCR0 */ + ldr r2, [r0] + orr r2, r2, r1 + str r2, [r0] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR1] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR1] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR2] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR2] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR3] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR3] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR6] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR6] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR7] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR7] + + /* Set the PLL1 and processor clock. */ + ldr r0, =SYSCON_BASE +#ifdef CONFIG_EDB9301 + /* 332MHz, giving a 166MHz processor clock. */ + ldr r1, = 0x02b49907 +#else + +#ifdef CONFIG_EDB93XX_INDUSTRIAL + /* 384MHz, giving a 196MHz processor clock. */ + ldr r1, =0x02a4bb38 +#else + /* 400MHz, giving a 200MHz processor clock. */ + ldr r1, =0x02a4e39e +#endif +#endif + str r1, [r0, #SYSCON_OFF_CLKSET1] + + nop + nop + nop + nop + nop + + /* Need to make sure that SDRAM is configured correctly before + * coping the code into it. + */ + +#ifdef CONFIG_EDB93XX_SDCS0 + mov r11, #SDRAM_DEVCFG0_BASE +#endif +#ifdef CONFIG_EDB93XX_SDCS1 + mov r11, #SDRAM_DEVCFG1_BASE +#endif +#ifdef CONFIG_EDB93XX_SDCS2 + mov r11, #SDRAM_DEVCFG2_BASE +#endif +#ifdef CONFIG_EDB93XX_SDCS3 + ldr r0, =SYSCON_BASE + ldr r0, [r0, #SYSCON_OFF_SYSCFG] + ands r0, r0, #SYSCON_SYSCFG_LASDO + moveq r11, #SDRAM_DEVCFG3_ASD0_BASE + movne r11, #SDRAM_DEVCFG3_ASD1_BASE +#endif + /* See Table 13-5 in EP93xx datasheet for more info about DRAM + * register mapping */ + + /* Try a 32-bit wide configuration of SDRAM. */ + ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \ + EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \ + EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \ + EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2) + + /* Set burst count: 4 and CAS: 2 + * Burst mode [A11:A10]; CAS [A16:A14] + */ + orr r2, r11, #0x00008800 + bl ep93xx_sdram_config + + /* Test the SDRAM. */ + mov r0, r11 + bl ep93xx_sdram_test + cmp r0, #0x00000000 + beq ep93xx_sdram_done + + /* Try a 16-bit wide configuration of SDRAM. */ + ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \ + EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \ + EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \ + EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \ + EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH) + + /* Set burst count: 8, CAS: 2, sequential burst + * Accoring to Table 13-3 for 16bit operations mapping must be shifted. + * Burst mode [A10:A9]; CAS [A15:A13] + */ + orr r2, r11, #0x00004600 + bl ep93xx_sdram_config + + /* Test the SDRAM. */ + mov r0, r11 + bl ep93xx_sdram_test + cmp r0, #0x00000000 + beq ep93xx_sdram_done + + /* Turn off the red LED. */ + ldr r0, =EP93XX_LED_DATA + ldr r1, [r0] + bic r1, r1, #EP93XX_LED_RED_ON + str r1, [r0] + + /* There is no SDRAM so flash the green LED. */ +flash_green: + orr r1, r1, #EP93XX_LED_GREEN_ON + str r1, [r0] + ldr r2, =0x00010000 +flash_green_delay_1: + subs r2, r2, #1 + bne flash_green_delay_1 + bic r1, r1, #EP93XX_LED_GREEN_ON + str r1, [r0] + ldr r2, =0x00010000 +flash_green_delay_2: + subs r2, r2, #1 + bne flash_green_delay_2 + orr r1, r1, #EP93XX_LED_GREEN_ON + str r1, [r0] + ldr r2, =0x00010000 +flash_green_delay_3: + subs r2, r2, #1 + bne flash_green_delay_3 + bic r1, r1, #EP93XX_LED_GREEN_ON + str r1, [r0] + ldr r2, =0x00050000 +flash_green_delay_4: + subs r2, r2, #1 + bne flash_green_delay_4 + b flash_green + - /* Configure flash wait states before we switch to the PLL */ - bl flash_cfg +ep93xx_sdram_done: + ldr r1, =EP93XX_LED_DATA + ldr r0, [r1] + bic r0, r0, #EP93XX_LED_RED_ON + str r0, [r1] - /* Set up PLL */ - bl pll_cfg + /* Determine the size of the SDRAM. */ + mov r0, r11 + bl ep93xx_sdram_size - /* Turn off the Green LED and leave the Red LED on */ - bl green_led_off + /* Save the SDRAM characteristics. */ + mov r8, r0 + mov r9, r1 + mov r10, r2 - /* Setup SDRAM */ - bl sdram_cfg + /* Compute total memory size into r1 */ + mul r1, r8, r10 +#ifdef CONFIG_EDB93XX_SDCS0 + ldr r2, [r0, #SDRAM_OFF_DEVCFG0] +#endif +#ifdef CONFIG_EDB93XX_SDCS1 + ldr r2, [r0, #SDRAM_OFF_DEVCFG1] +#endif +#ifdef CONFIG_EDB93XX_SDCS2 + ldr r2, [r0, #SDRAM_OFF_DEVCFG2] +#endif +#ifdef CONFIG_EDB93XX_SDCS3 + ldr r2, [r0, #SDRAM_OFF_DEVCFG3] +#endif - /* Turn on Green LED, Turn off the Red LED */ - bl green_led_on - bl red_led_off + /* Consider small DRAM size as: + * < 32Mb for 32bit bus + * < 64Mb for 16bit bus + */ + tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH + moveq r1, r1, lsr #1 + cmp r1, #0x02000000 - /* FIXME: we use async mode for now */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0xc0000000 - mcr p15, 0, r0, c1, c0, 0 +#if defined(CONFIG_EDB9301) + /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */ + movlt r1, #0x03f0 + movge r1, #0x01e0 +#else + /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */ + movlt r1, #0x0600 + movge r1, #0x2f0 +#endif + str r1, [r0, #SDRAM_OFF_REFRSHTIMR] - /* restore return address */ - ldr r1, =SYSCON_SCRATCH0 - ldr lr, [r1] + /* Save the memory configuration information. */ + orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE + stmia r0, {r8-r11} - mov pc, lr + mov lr, r6 + mov pc, lr diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds deleted file mode 100644 index 4bed4fcdd7..0000000000 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - arch/arm/cpu/arm920t/start.o (.text*) - /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ - . = 0x1000; - LONG(0x53555243) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - __bss_start = .; - .bss : { *(.bss*) } - __bss_end = .; - - _end = .; -} diff --git a/arch/arm/cpu/arm920t/imx/Makefile b/arch/arm/cpu/arm920t/imx/Makefile index c9c85b8740..54ce646d97 100644 --- a/arch/arm/cpu/arm920t/imx/Makefile +++ b/arch/arm/cpu/arm920t/imx/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS += generic.o -COBJS += speed.o -COBJS += timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += generic.o +obj-y += speed.o +obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile index eef053050a..400aa89e99 100644 --- a/arch/arm/cpu/arm920t/ks8695/Makefile +++ b/arch/arm/cpu/arm920t/ks8695/Makefile @@ -5,27 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS = lowlevel_init.o - -COBJS = timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = lowlevel_init.o +obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile index 97175330ec..e44c549ba0 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/Makefile +++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile @@ -5,28 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-$(CONFIG_USE_IRQ) += interrupts.o -COBJS-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o -COBJS-y += speed.o -COBJS-y += timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_USE_IRQ) += interrupts.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o +obj-y += speed.o +obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index a67b659fd0..07404502c8 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -12,36 +12,6 @@ #include #include -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b start_code - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - /* ************************************************************************* * @@ -55,54 +25,9 @@ _fiq: .word fiq ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start + .globl reset -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual start code - */ - -start_code: +reset: /* * set the cpu to SVC32 mode */ @@ -222,166 +147,3 @@ cpu_init_crit: mov lr, ip mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r7, sp, #S_PC - stmdb r7, {sp, lr}^ @ Calling SP, LR - str lr, [r7, #0] @ Save calling PC - mrs r6, spsr - str r6, [r7, #4] @ Save CPSR - str r0, [r7, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - /* return & move spsr_svc into cpsr */ - subs pc, lr, #4 - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/arch/arm/cpu/arm925t/Makefile b/arch/arm/cpu/arm925t/Makefile deleted file mode 100644 index 40d2156f67..0000000000 --- a/arch/arm/cpu/arm925t/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o - -COBJS += cpu.o -COBJS += omap925.o -COBJS += timer.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm925t/config.mk b/arch/arm/cpu/arm925t/config.mk deleted file mode 100644 index 58fd756586..0000000000 --- a/arch/arm/cpu/arm925t/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm925t/cpu.c b/arch/arm/cpu/arm925t/cpu.c deleted file mode 100644 index d0f8e1e5b8..0000000000 --- a/arch/arm/cpu/arm925t/cpu.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code - */ - -#include -#include -#include -#include - -static void cache_flush(void); - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - disable_interrupts (); - - - /* turn off I/D-cache */ - icache_disable(); - dcache_disable(); - /* flush I/D-cache */ - cache_flush(); - - return 0; -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); -} diff --git a/arch/arm/cpu/arm925t/omap925.c b/arch/arm/cpu/arm925t/omap925.c deleted file mode 100644 index c0402d17eb..0000000000 --- a/arch/arm/cpu/arm925t/omap925.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define MIF_CONFIG_REG 0xFFFECC0C -#define FLASH_GLOBAL_CTRL_NWP 1 - -void archflashwp (void *archdata, int wp) -{ - ulong *fgc = (ulong *) MIF_CONFIG_REG; - - if (wp == 1) - *fgc &= ~FLASH_GLOBAL_CTRL_NWP; - else - *fgc |= FLASH_GLOBAL_CTRL_NWP; -} diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S deleted file mode 100644 index 1e765b7024..0000000000 --- a/arch/arm/cpu/arm925t/start.S +++ /dev/null @@ -1,382 +0,0 @@ -/* - * armboot - Startup Code for ARM925 CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1510 from ARM920 code ------ - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * Set up 925T mode - */ - mov r1, #0x81 /* Set ARM925T configuration. */ - mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */ - - /* - * turn off the watchdog, unlock/diable sequence - */ - mov r1, #0xF5 - ldr r0, =WDTIM_MODE - strh r1, [r0] - mov r1, #0xA0 - strh r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /* - * wait for dpll to lock - */ - ldr r0, =CK_DPLL1 - mov r1, #0x10 - strh r1, [r0] -poll1: - ldrh r1, [r0] - ands r1, r1, #0x01 - beq poll1 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - mov pc, lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * Go setup Memory and board specific bits prior to relocation. - */ - mov ip, lr /* perserve link reg across call */ - bl lowlevel_init /* go setup pll,mux,memory */ - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x3 /* dsp_en + arm_rst = global reset */ - strh r3, [r1] /* force reset */ - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl1: - .word 0xfffece10 diff --git a/arch/arm/cpu/arm925t/timer.c b/arch/arm/cpu/arm925t/timer.c deleted file mode 100644 index e56b576b18..0000000000 --- a/arch/arm/cpu/arm925t/timer.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2009 - * 2N Telekomunikace, - * - * (C) Copyright 2003 - * Texas Instruments, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define TIMER_LOAD_VAL 0xffffffff -#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) - -static uint32_t timestamp; -static uint32_t lastdec; - -/* nothing really to do with interrupts, just starts up a counter. */ -int timer_init (void) -{ - /* Start the decrementer ticking down from 0xffffffff */ - __raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); - __raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | - (CONFIG_SYS_PTV << MPUTIM_PTV_BIT), - CONFIG_SYS_TIMERBASE + CNTL_TIMER); - - /* init the timestamp and lastdec value */ - lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / - (TIMER_CLOCK / CONFIG_SYS_HZ); - timestamp = 0; /* start "advancing" time stamp from 0 */ - - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay (unsigned long usec) -{ - int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000; - uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); - - while (tmo > 0) { - now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); - if (last < now) /* count down timer underflow */ - tmo -= TIMER_LOAD_VAL - now + last; - else - tmo -= last - now; - last = now; - } -} - -ulong get_timer_masked (void) -{ - uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / - (TIMER_CLOCK / CONFIG_SYS_HZ); - if (lastdec < now) /* count down timer underflow */ - timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) - - now + lastdec; - else - timestamp += lastdec - now; - lastdec = now; - - return timestamp; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index b4c214c704..f1d6c01d4f 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -5,33 +5,26 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o cache.o +extra-y = start.o +obj-y = cpu.o cache.o ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE -START := +extra-y := endif endif -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_ARMADA100) += armada100/ +obj-$(CONFIG_AT91FAMILY) += at91/ +obj-$(CONFIG_ARCH_DAVINCI) += davinci/ +obj-$(CONFIG_KIRKWOOD) += kirkwood/ +obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/ +obj-$(CONFIG_MB86R0x) += mb86r0x/ +obj-$(CONFIG_SOC_MX25) += mx25/ +obj-$(CONFIG_SOC_MX27) += mx27/ +obj-$(if $(filter mxs,$(SOC)),y) += mxs/ +obj-$(CONFIG_ARCH_NOMADIK) += nomadik/ +obj-$(CONFIG_ORION5X) += orion5x/ +obj-$(CONFIG_PANTHEON) += pantheon/ +obj-$(if $(filter spear,$(SOC)),y) += spear/ +obj-$(CONFIG_ARCH_VERSATILE) += versatile/ diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile index a1a6df0bca..fca98ef42f 100644 --- a/arch/arm/cpu/arm926ejs/armada100/Makefile +++ b/arch/arm/cpu/arm926ejs/armada100/Makefile @@ -6,25 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y = cpu.o timer.o dram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cpu.o timer.o dram.o diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index 9faec912b4..698a28dc5d 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -5,46 +5,25 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-$(CONFIG_AT91CAP9) += at91cap9_devices.o -COBJS-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o -COBJS-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o -COBJS-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o -COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o -COBJS-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o -COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o -COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o -COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o -COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o -COBJS-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o -COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o -COBJS-$(CONFIG_AT91_EFLASH) += eflash.o -COBJS-$(CONFIG_AT91_LED) += led.o -COBJS-y += clock.o -COBJS-y += cpu.o -COBJS-y += reset.o -COBJS-y += timer.o +obj-$(CONFIG_AT91CAP9) += at91cap9_devices.o +obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o +obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o +obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o +obj-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o +obj-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o +obj-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o +obj-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o +obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o +obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o +obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o +obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o +obj-$(CONFIG_AT91_EFLASH) += eflash.o +obj-$(CONFIG_AT91_LED) += led.o +obj-y += clock.o +obj-y += cpu.o +obj-y += reset.o +obj-y += timer.o ifndef CONFIG_SKIP_LOWLEVEL_INIT -SOBJS-y := lowlevel_init.o +obj-y += lowlevel_init.o endif - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index cae4abcdf4..efb53d673f 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -7,9 +7,12 @@ */ #include +#include #include +#include #include #include +#include #include /* @@ -207,3 +210,36 @@ void at91_mci_hw_init(void) #endif } #endif + +void at91_sdram_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); + at91_set_a_periph(AT91_PIO_PORTC, 17, 0); + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); + at91_set_a_periph(AT91_PIO_PORTC, 25, 0); + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); + at91_set_a_periph(AT91_PIO_PORTC, 28, 0); + at91_set_a_periph(AT91_PIO_PORTC, 29, 0); + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); + at91_set_a_periph(AT91_PIO_PORTC, 31, 0); +} + +/* Platform data for the GPIOs */ +static const struct at91_port_platdata at91sam9260_plat[] = { + { ATMEL_BASE_PIOA, "PA" }, + { ATMEL_BASE_PIOB, "PB" }, + { ATMEL_BASE_PIOC, "PC" }, +}; + +U_BOOT_DEVICES(at91sam9260_gpios) = { + { "gpio_at91", &at91sam9260_plat[0] }, + { "gpio_at91", &at91sam9260_plat[1] }, + { "gpio_at91", &at91sam9260_plat[2] }, +}; diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c index 99a39134de..6b51d5f355 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -143,6 +143,31 @@ void at91_spi1_hw_init(unsigned long cs_mask) } #endif +#if defined(CONFIG_GENERIC_ATMEL_MCI) +void at91_mci_hw_init(void) +{ + /* Enable mci clock */ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + writel(1 << ATMEL_ID_MCI1, &pmc->pcer); + + at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */ + +#if defined(CONFIG_ATMEL_MCI_PORTB) + at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */ + at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */ + at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */ + at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */ +#else + at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */ + at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */ +#endif +} +#endif + #ifdef CONFIG_MACB void at91_macb_hw_init(void) { diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 7d7725c4b8..0e6c0da1bd 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -165,3 +165,20 @@ void at91_macb_hw_init(void) #endif } #endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void at91_mci_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */ + + /* Enable clock */ + writel(1 << ATMEL_ID_MCI0, &pmc->pcer); +} +#endif diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 31315b58e4..f363982d03 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -187,3 +187,63 @@ int at91_clock_init(unsigned long main_clock) return 0; } + +#if !defined(AT91_PLL_LOCK_TIMEOUT) +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#endif + +void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { + timeout--; + if (timeout == 0) + break; + } +} +void at91_pllb_init(u32 pllbr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + + writel(pllbr, &pmc->pllbr); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { + timeout--; + if (timeout == 0) + break; + } +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_MASK | + AT91_PMC_MCKR_CSS_MASK); + tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_MASK | + AT91_PMC_MCKR_CSS_MASK); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { + timeout--; + if (timeout == 0) + break; + } +} + +void at91_periph_clk_enable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << id, &pmc->pcer); +} diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c index 3e21cdb2fd..3f39264289 100644 --- a/arch/arm/cpu/arm926ejs/at91/eflash.c +++ b/arch/arm/cpu/arm926ejs/at91/eflash.c @@ -28,7 +28,7 @@ * by u-Boot commands. * * Note: Redundant environment will not work in this flash since - * it does use partial page writes. Make sure the environent spans + * it does use partial page writes. Make sure the environment spans * whole pages! */ diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c index 5dd90487ed..b8d5c785df 100644 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ b/arch/arm/cpu/arm926ejs/at91/led.c @@ -7,43 +7,42 @@ */ #include -#include -#include -#include +#include #include +#include #ifdef CONFIG_RED_LED void red_led_on(void) { - at91_set_gpio_value(CONFIG_RED_LED, 1); + gpio_set_value(CONFIG_RED_LED, 1); } void red_led_off(void) { - at91_set_gpio_value(CONFIG_RED_LED, 0); + gpio_set_value(CONFIG_RED_LED, 0); } #endif #ifdef CONFIG_GREEN_LED void green_led_on(void) { - at91_set_gpio_value(CONFIG_GREEN_LED, 0); + gpio_set_value(CONFIG_GREEN_LED, 0); } void green_led_off(void) { - at91_set_gpio_value(CONFIG_GREEN_LED, 1); + gpio_set_value(CONFIG_GREEN_LED, 1); } #endif #ifdef CONFIG_YELLOW_LED void yellow_led_on(void) { - at91_set_gpio_value(CONFIG_YELLOW_LED, 0); + gpio_set_value(CONFIG_YELLOW_LED, 0); } void yellow_led_off(void) { - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + gpio_set_value(CONFIG_YELLOW_LED, 1); } #endif diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S index 39de2f4904..a9ec81a75c 100644 --- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S @@ -7,7 +7,7 @@ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -26,27 +26,18 @@ #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL #endif -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init .type lowlevel_init,function lowlevel_init: - mov r5, pc /* r5 = POS1 + 4 current */ POS1: + adr r5, POS1 /* r5 = POS1 run time */ ldr r0, =POS1 /* r0 = POS1 compile */ - ldr r2, _TEXT_BASE - sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */ - sub r5, r5, #4 /* r1 = text base - current */ /* memory control configuration 1 */ ldr r0, =SMRDATA ldr r2, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 0: @@ -149,9 +140,6 @@ PLL_setup_end: ldr r0, =SMRDATA1 ldr r2, =SMRDATA2 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 2: diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index e86c2edd3b..8d7873c9af 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -99,7 +99,4 @@ void flush_cache(unsigned long start, unsigned long size) /* * Stub implementations for l2 cache operations */ -void __l2_cache_disable(void) {} - -void l2_cache_disable(void) - __attribute__((weak, alias("__l2_cache_disable"))); +__weak void l2_cache_disable(void) {} diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 917ff7edec..bdb3da183e 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv5te -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) - -ifneq ($(CONFIG_IMX_CONFIG),) -ifdef CONFIG_SPL -ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/SPL -endif -else -ALL-y += $(obj)u-boot.imx -endif -endif diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 174c8d36b2..d1d2a176f6 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -54,7 +54,9 @@ int cleanup_before_linux (void) /* flush I/D-cache */ static void cache_flush (void) { +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long i = 0; asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); +#endif } diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig new file mode 100644 index 0000000000..613f04d8b0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/Kconfig @@ -0,0 +1,78 @@ +if ARCH_DAVINCI + +choice + prompt "DaVinci board select" + +config TARGET_ENBW_CMC + bool "EnBW CMC board" + +config TARGET_IPAM390 + bool "IPAM390 board" + select SUPPORT_SPL + +config TARGET_DA830EVM + bool "DA830 EVM board" + +config TARGET_DA850EVM + bool "DA850 EVM board" + select SUPPORT_SPL + +config TARGET_CAM_ENC_4XX + bool "CAM ENC 4xx board" + select SUPPORT_SPL + +config TARGET_HAWKBOARD + bool "Hawkboard" + select SUPPORT_SPL + +config TARGET_DAVINCI_DM355EVM + bool "DM355 EVM board" + +config TARGET_DAVINCI_DM355LEOPARD + bool "DM355 Leopard board" + +config TARGET_DAVINCI_DM365EVM + bool "DM365 EVM board" + +config TARGET_DAVINCI_DM6467EVM + bool "DM6467 EVM board" + +config TARGET_DAVINCI_DVEVM + bool "DVEVM board" + +config TARGET_EA20 + bool "EA20 board" + +config TARGET_DAVINCI_SCHMOOGIE + bool "Schmoogie board" + +config TARGET_DAVINCI_SFFSDR + bool "SFFSDR board" + +config TARGET_DAVINCI_SONATA + bool "Sonata board" + +config TARGET_CALIMAIN + bool "Calimain board" + +endchoice + +config SYS_SOC + default "davinci" + +source "board/enbw/enbw_cmc/Kconfig" +source "board/ait/cam_enc_4xx/Kconfig" +source "board/Barix/ipam390/Kconfig" +source "board/davinci/da8xxevm/Kconfig" +source "board/davinci/dm355evm/Kconfig" +source "board/davinci/dm355leopard/Kconfig" +source "board/davinci/dm365evm/Kconfig" +source "board/davinci/dm6467evm/Kconfig" +source "board/davinci/dvevm/Kconfig" +source "board/davinci/ea20/Kconfig" +source "board/davinci/schmoogie/Kconfig" +source "board/davinci/sffsdr/Kconfig" +source "board/davinci/sonata/Kconfig" +source "board/omicron/calimain/Kconfig" + +endif diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index b596818fec..7d67191de8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -7,44 +7,22 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o -COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o -COBJS-$(CONFIG_SOC_DM355) += dm355.o -COBJS-$(CONFIG_SOC_DM365) += dm365.o -COBJS-$(CONFIG_SOC_DM644X) += dm644x.o -COBJS-$(CONFIG_SOC_DM646X) += dm646x.o -COBJS-$(CONFIG_SOC_DA830) += da830_pinmux.o -COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o -COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o +obj-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o +obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o +obj-$(CONFIG_SOC_DM355) += dm355.o +obj-$(CONFIG_SOC_DM365) += dm365.o +obj-$(CONFIG_SOC_DM644X) += dm644x.o +obj-$(CONFIG_SOC_DM646X) += dm646x.o +obj-$(CONFIG_SOC_DA830) += da830_pinmux.o +obj-$(CONFIG_SOC_DA850) += da850_pinmux.o +obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o ifdef CONFIG_SPL_BUILD -COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o -COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o -COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o +obj-$(CONFIG_SPL_FRAMEWORK) += spl.o +obj-$(CONFIG_SOC_DM365) += dm365_lowlevel.o +obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o endif ifndef CONFIG_SKIP_LOWLEVEL_INIT -SOBJS += lowlevel_init.o +obj-y += lowlevel_init.o endif - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk index d5c978b446..69e9d5ab21 100644 --- a/arch/arm/cpu/arm926ejs/davinci/config.mk +++ b/arch/arm/cpu/arm926ejs/davinci/config.mk @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # ifndef CONFIG_SPL_BUILD -ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.ais +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais endif diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index f6bf1ef8cb..19730cef8c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include void davinci_enable_uart0(void) @@ -26,7 +26,7 @@ void davinci_enable_uart0(void) } #if defined(CONFIG_SYS_DA850_PLL_INIT) -void da850_waitloop(unsigned long loopcnt) +static void da850_waitloop(unsigned long loopcnt) { unsigned long i; @@ -34,7 +34,7 @@ void da850_waitloop(unsigned long loopcnt) asm(" NOP"); } -int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) +static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) { if (reg == davinci_pllc0_regs) /* Unlock PLL registers. */ @@ -160,7 +160,7 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) #endif /* CONFIG_SYS_DA850_PLL_INIT */ #if defined(CONFIG_SYS_DA850_DDR_INIT) -int da850_ddr_setup(void) +static int da850_ddr_setup(void) { unsigned long tmp; @@ -299,7 +299,11 @@ int arch_cpu_init(void) */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), +#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) + &davinci_uart0_ctrl_regs->pwremu_mgmt); +#else &davinci_uart2_ctrl_regs->pwremu_mgmt); +#endif #if defined(CONFIG_SYS_DA850_DDR_INIT) da850_ddr_setup(); diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c index f603f2fe91..6105f6390c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c @@ -28,6 +28,11 @@ const struct pinmux_config uart0_pins_txrx[] = { { pinmux(3), 2, 5 }, /* UART0_TXD */ }; +const struct pinmux_config uart0_pins_rtscts[] = { + { pinmux(3), 2, 6 }, + { pinmux(3), 2, 7 }, +}; + const struct pinmux_config uart1_pins_txrx[] = { { pinmux(4), 2, 6 }, /* UART1_RXD */ { pinmux(4), 2, 7 }, /* UART1_TXD */ @@ -51,6 +56,7 @@ const struct pinmux_config emac_pins_rmii[] = { { pinmux(14), 8, 5 }, /* RMII_RXD[1] */ { pinmux(14), 8, 6 }, /* RMII_RXD[0] */ { pinmux(14), 8, 7 }, /* RMII_RXER */ + { pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */ { pinmux(15), 8, 1 }, /* RMII_CRS_DV */ }; diff --git a/arch/arm/cpu/arm926ejs/davinci/dm355.c b/arch/arm/cpu/arm926ejs/davinci/dm355.c index 5f85162b8e..f9550a16d3 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm355.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm355.c @@ -19,7 +19,7 @@ void davinci_enable_uart0(void) } -#ifdef CONFIG_DRIVER_DAVINCI_I2C +#ifdef CONFIG_SYS_I2C_DAVINCI void davinci_enable_i2c(void) { lpsc_on(DAVINCI_LPSC_I2C); diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365.c b/arch/arm/cpu/arm926ejs/davinci/dm365.c index 0af2d0236d..f6ca527e74 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm365.c @@ -12,7 +12,7 @@ void davinci_enable_uart0(void) lpsc_on(DAVINCI_LPSC_UART0); } -#ifdef CONFIG_DRIVER_DAVINCI_I2C +#ifdef CONFIG_SYS_I2C_DAVINCI void davinci_enable_i2c(void) { lpsc_on(DAVINCI_LPSC_I2C); diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c index ee096fe721..c8b44988d3 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/cpu/arm926ejs/davinci/dm644x.c index 788e57840f..c58e271e28 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm644x.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm644x.c @@ -47,7 +47,7 @@ void davinci_enable_emac(void) } #endif -#ifdef CONFIG_DRIVER_DAVINCI_I2C +#ifdef CONFIG_SYS_I2C_DAVINCI void davinci_enable_i2c(void) { lpsc_on(DAVINCI_LPSC_I2C); diff --git a/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/cpu/arm926ejs/davinci/dm646x.c index 86a508f6a1..cfea8300de 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm646x.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm646x.c @@ -18,7 +18,7 @@ void davinci_enable_emac(void) } #endif -#ifdef CONFIG_DRIVER_DAVINCI_I2C +#ifdef CONFIG_SYS_I2C_DAVINCI void davinci_enable_i2c(void) { lpsc_on(DAVINCI_DM646X_LPSC_I2C); diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c index 59b304efcb..49349da179 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -34,29 +34,14 @@ void putc(char c) } #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ -void board_init_f(ulong dummy) +void spl_board_init(void) { - /* First, setup our stack pointer. */ - asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); - - /* Second, perform our low-level init. */ #ifdef CONFIG_SOC_DM365 dm36x_lowlevel_init(0); #endif #ifdef CONFIG_SOC_DA8XX arch_cpu_init(); #endif - - /* Third, we clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* Finally, setup gd and move to the next step. */ - gd = &gdata; - board_init_r(NULL, 0); -} - -void spl_board_init(void) -{ preloader_console_init(); } diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c index 8928bbc624..c7d0652e83 100644 --- a/arch/arm/cpu/arm926ejs/davinci/timer.c +++ b/arch/arm/cpu/arm926ejs/davinci/timer.c @@ -18,7 +18,7 @@ * * Copyright (C) 2007 Sergey Kubushyn * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig new file mode 100644 index 0000000000..45c6687d0b --- /dev/null +++ b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig @@ -0,0 +1,88 @@ +if KIRKWOOD + +choice + prompt "Marvell Kirkwood board select" + +config TARGET_OPENRD + bool "Marvell OpenRD Board" + +config TARGET_MV88F6281GTW_GE + bool "MV88f6281GTW_GE Board" + +config TARGET_RD6281A + bool "RD6281A Board" + +config TARGET_DREAMPLUG + bool "DreamPlug Board" + +config TARGET_GURUPLUG + bool "GuruPlug Board" + +config TARGET_SHEEVAPLUG + bool "SheevaPlug Board" + +config TARGET_LSXL + bool "lsxl Board" + +config TARGET_POGO_E02 + bool "pogo_e02 Board" + +config TARGET_DNS325 + bool "dns325 Board" + +config TARGET_ICONNECT + bool "iconnect Board" + +config TARGET_TK71 + bool "TK71 Board" + +config TARGET_KM_KIRKWOOD + bool "KM_KIRKWOOD Board" + +config TARGET_NET2BIG_V2 + bool "LaCie 2Big Network v2 NAS Board" + +config TARGET_NETSPACE_V2 + bool "LaCie netspace_v2 Board" + +config TARGET_WIRELESS_SPACE + bool "LaCie Wireless_space Board" + +config TARGET_IB62X0 + bool "ib62x0 Board" + +config TARGET_DOCKSTAR + bool "Dockstar Board" + +config TARGET_GOFLEXHOME + bool "GoFlex Home Board" + +config TARGET_NAS220 + bool "BlackArmor NAS220" + +endchoice + +config SYS_SOC + default "kirkwood" + +source "board/Marvell/openrd/Kconfig" +source "board/Marvell/mv88f6281gtw_ge/Kconfig" +source "board/Marvell/rd6281a/Kconfig" +source "board/Marvell/dreamplug/Kconfig" +source "board/Marvell/guruplug/Kconfig" +source "board/Marvell/sheevaplug/Kconfig" +source "board/buffalo/lsxl/Kconfig" +source "board/cloudengines/pogo_e02/Kconfig" +source "board/d-link/dns325/Kconfig" +source "board/iomega/iconnect/Kconfig" +source "board/karo/tk71/Kconfig" +source "board/keymile/km_arm/Kconfig" +source "board/LaCie/net2big_v2/Kconfig" +source "board/LaCie/netspace_v2/Kconfig" +source "board/LaCie/wireless_space/Kconfig" +source "board/raidsonic/ib62x0/Kconfig" +source "board/Seagate/dockstar/Kconfig" +source "board/Seagate/goflexhome/Kconfig" +source "board/Seagate/nas220/Kconfig" + +endif diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index 20ccf201b7..df4756e4bd 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile +++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile @@ -6,29 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y = cpu.o -COBJS-y += dram.o -COBJS-y += mpp.o -COBJS-y += timer.o -COBJS-y += cache.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cpu.o +obj-y += cache.o +obj-y += mpp.o diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index cde3172fe3..4c9d3fde47 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -9,13 +9,10 @@ #include #include #include -#include #include #include -#include -#include - -#define BUFLEN 16 +#include +#include void reset_cpu(unsigned long ignored) { @@ -29,31 +26,6 @@ void reset_cpu(unsigned long ignored) while (1) ; } -/* - * Generates Ramdom hex number reading some time varient system registers - * and using md5 algorithm - */ -unsigned char get_random_hex(void) -{ - int i; - u32 inbuf[BUFLEN]; - u8 outbuf[BUFLEN]; - - /* - * in case of 88F6281/88F6282/88F6192 A0, - * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 - * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are - * reserved regs and does not have names at this moment - * (no errata available) - */ - writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); - for (i = 0; i < BUFLEN; i++) { - inbuf[i] = readl(KW_REG_UNDOC_0x1470); - } - md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf); - return outbuf[outbuf[7] % 0x0f]; -} - /* * Window Size * Used with the Base register to set the address window size and location. @@ -139,50 +111,6 @@ int kw_config_adr_windows(void) return 0; } -/* - * kw_config_gpio - GPIO configuration - */ -void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe) -{ - struct kwgpio_registers *gpio0reg = - (struct kwgpio_registers *)KW_GPIO0_BASE; - struct kwgpio_registers *gpio1reg = - (struct kwgpio_registers *)KW_GPIO1_BASE; - - /* Init GPIOS to default values as per board requirement */ - writel(gpp0_oe_val, &gpio0reg->dout); - writel(gpp1_oe_val, &gpio1reg->dout); - writel(gpp0_oe, &gpio0reg->oe); - writel(gpp1_oe, &gpio1reg->oe); -} - -/* - * kw_config_mpp - Multi-Purpose Pins Functionality configuration - * - * Each MPP can be configured to different functionality through - * MPP control register, ref (sec 6.1 of kirkwood h/w specification) - * - * There are maximum 64 Multi-Pourpose Pins on Kirkwood - * Each MPP functionality can be configuration by a 4bit value - * of MPP control reg, the value and associated functionality depends - * upon used SoC varient - */ -int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31, - u32 mpp32_39, u32 mpp40_47, u32 mpp48_55) -{ - u32 *mppreg = (u32 *) KW_MPP_BASE; - - /* program mpp registers */ - writel(mpp0_7, &mppreg[0]); - writel(mpp8_15, &mppreg[1]); - writel(mpp16_23, &mppreg[2]); - writel(mpp24_31, &mppreg[3]); - writel(mpp32_39, &mppreg[4]); - writel(mpp40_47, &mppreg[5]); - writel(mpp48_55, &mppreg[6]); - return 0; -} - /* * SYSRSTn Duration Counter Support * @@ -211,7 +139,7 @@ static void kw_sysrst_action(void) debug("Starting %s process...\n", __FUNCTION__); ret = run_command(s, 0); - if (ret < 0) + if (ret != 0) debug("Error.. %s failed\n", __FUNCTION__); else debug("%s process finished\n", __FUNCTION__); @@ -253,7 +181,7 @@ static void kw_sysrst_check(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - char *rev; + char *rev = "??"; u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; @@ -264,7 +192,13 @@ int print_cpuinfo(void) switch (revid) { case 0: - rev = "Z0"; + if (devid == 0x6281) + rev = "Z0"; + else if (devid == 0x6282) + rev = "A0"; + break; + case 1: + rev = "A1"; break; case 2: rev = "A0"; @@ -273,7 +207,6 @@ int print_cpuinfo(void) rev = "A1"; break; default: - rev = "??"; break; } @@ -302,7 +235,7 @@ int arch_cpu_init(void) /* * Configures the I/O voltage of the pads connected to Egigabit * Ethernet interface to 1.8V - * By defult it is set to 3.3V + * By default it is set to 3.3V */ reg = readl(KW_REG_MPP_OUT_DRV_REG); reg |= (1 << 7); @@ -378,3 +311,11 @@ int cpu_eth_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_MVEBU_MMC +int board_mmc_init(bd_t *bis) +{ + mvebu_mmc_init(bis); + return 0; +} +#endif /* CONFIG_MVEBU_MMC */ diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c deleted file mode 100644 index d73ae47c34..0000000000 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct kw_sdram_bank { - u32 win_bar; - u32 win_sz; -}; - -struct kw_sdram_addr_dec { - struct kw_sdram_bank sdram_bank[4]; -}; - -#define KW_REG_CPUCS_WIN_ENABLE (1 << 0) -#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1) -#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) -#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) - -/* - * kw_sdram_bar - reads SDRAM Base Address Register - */ -u32 kw_sdram_bar(enum memory_bank bank) -{ - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); - u32 result = 0; - u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); - - if ((!enable) || (bank > BANK3)) - return 0; - - result = readl(&base->sdram_bank[bank].win_bar); - return result; -} - -/* - * kw_sdram_bs_set - writes SDRAM Bank size - */ -static void kw_sdram_bs_set(enum memory_bank bank, u32 size) -{ - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); - /* Read current register value */ - u32 reg = readl(&base->sdram_bank[bank].win_sz); - - /* Clear window size */ - reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF); - - /* Set new window size */ - reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24); - - writel(reg, &base->sdram_bank[bank].win_sz); -} - -/* - * kw_sdram_bs - reads SDRAM Bank size - */ -u32 kw_sdram_bs(enum memory_bank bank) -{ - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); - u32 result = 0; - u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); - - if ((!enable) || (bank > BANK3)) - return 0; - result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz); - result += 0x01000000; - return result; -} - -void kw_sdram_size_adjust(enum memory_bank bank) -{ - u32 size; - - /* probe currently equipped RAM size */ - size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank)); - - /* adjust SDRAM window size accordingly */ - kw_sdram_bs_set(bank, size); -} - -#ifndef CONFIG_SYS_BOARD_DRAM_INIT -int dram_init(void) -{ - int i; - - gd->ram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - /* - * It is assumed that all memory banks are consecutive - * and without gaps. - * If the gap is found, ram_size will be reported for - * consecutive memory only - */ - if (gd->bd->bi_dram[i].start != gd->ram_size) - break; - - gd->ram_size += gd->bd->bi_dram[i].size; - - } - - for (; i < CONFIG_NR_DRAM_BANKS; i++) { - /* If above loop terminated prematurely, we need to set - * remaining banks' start address & size as 0. Otherwise other - * u-boot functions and Linux kernel gets wrong values which - * could result in crash */ - gd->bd->bi_dram[i].start = 0; - gd->bd->bi_dram[i].size = 0; - } - - return 0; -} - -/* - * If this function is not defined here, - * board.c alters dram bank zero configuration defined above. - */ -void dram_init_banksize(void) -{ - dram_init(); -} -#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index 0ba6f098cb..7222504ed3 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include static u32 kirkwood_variant(void) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c deleted file mode 100644 index a08f4a1456..0000000000 --- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) Marvell International Ltd. and its affiliates - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define UBOOT_CNTR 0 /* counter to use for uboot timer */ - -/* Timer reload and current value registers */ -struct kwtmr_val { - u32 reload; /* Timer reload reg */ - u32 val; /* Timer value reg */ -}; - -/* Timer registers */ -struct kwtmr_registers { - u32 ctrl; /* Timer control reg */ - u32 pad[3]; - struct kwtmr_val tmr[2]; - u32 wdt_reload; - u32 wdt_val; -}; - -struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE; - -/* - * ARM Timers Registers Map - */ -#define CNTMR_CTRL_REG &kwtmr_regs->ctrl -#define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload -#define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val - -/* - * ARM Timers Control Register - * CPU_TIMERS_CTRL_REG (CTCR) - */ -#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) - -#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) -#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) - -/* - * ARM Timer\Watchdog Reload Register - * CNTMR_RELOAD_REG (TRR) - */ -#define TRG_ARM_TIMER_REL_OFFS 0 -#define TRG_ARM_TIMER_REL_MASK 0xffffffff - -/* - * ARM Timer\Watchdog Register - * CNTMR_VAL_REG (TVRG) - */ -#define TVR_ARM_TIMER_OFFS 0 -#define TVR_ARM_TIMER_MASK 0xffffffff -#define TVR_ARM_TIMER_MAX 0xffffffff -#define TIMER_LOAD_VAL 0xffffffff - -#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \ - (CONFIG_SYS_TCLK / 1000)) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -ulong get_timer_masked(void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; - } - lastdec = now; - - return timestamp; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - uint current; - ulong delayticks; - - current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); - - if (current < delayticks) { - delayticks -= current; - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; - while ((TIMER_LOAD_VAL - delayticks) < - readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; - } else { - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > - (current - delayticks)) ; - } -} - -/* - * init the counter - */ -int timer_init(void) -{ - unsigned int cntmrctrl; - - /* load value into timer */ - writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); - writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); - - /* enable timer in auto reload mode */ - cntmrctrl = readl(CNTMR_CTRL_REG); - cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); - cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); - writel(cntmrctrl, CNTMR_CTRL_REG); - - /* init the timestamp and lastdec value */ - lastdec = READ_TIMER; - timestamp = 0; - - return 0; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile index 603051a64e..314f004eba 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = cpu.o clk.o devices.o timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cpu.o clk.o devices.o timer.o diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile index a780dfe3a2..365892c413 100644 --- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile +++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile @@ -5,27 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = clock.o reset.o timer.o -SOBJS = - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = clock.o reset.o timer.o diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c deleted file mode 100644 index 5fe8fa204b..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - /* ddr2 controller */ - DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); - DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); - DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); - DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); - DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); - DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); - DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); - DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); - DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); - DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); - DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); - DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); - DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); - DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); - DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); - - /* clock reset generator */ - DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); - DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); - DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); - DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); - DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); - DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); - - /* chip control module */ - DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); - - /* external bus interface */ - DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); - DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); - DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); - DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); - DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); - DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); - DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); - DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); - DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile index 75a09ff54b..ebc0407ef4 100644 --- a/arch/arm/cpu/arm926ejs/mx25/Makefile +++ b/arch/arm/cpu/arm926ejs/mx25/Makefile @@ -4,25 +4,8 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk +obj-y = generic.o timer.o reset.o -LIB = $(obj)lib$(SOC).o - -COBJS = generic.o timer.o reset.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ifndef CONFIG_SPL_BUILD +obj-y += relocate.o +endif diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c deleted file mode 100644 index 0e2e8bf64e..0000000000 --- a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - /* Clock Control Module */ - DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); - DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); - DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); - DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); - DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); - DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); - - /* Enhanced SDRAM Controller */ - DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); - DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); - DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); - - /* Multi-Layer AHB Crossbar Switch */ - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); - - /* AHB <-> IP-Bus Interface */ - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 4e9c0b5481..8912098573 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -181,7 +181,7 @@ int print_cpuinfo(void) (cpurev & 0xF0) >> 4, (cpurev & 0x0F), ((cpurev & 0x8000) ? " unknown" : ""), strmhz(buf, imx_get_armclk())); - printf("Reset cause: %s\n\n", get_reset_cause()); + printf("Reset cause: %s\n", get_reset_cause()); return 0; } #endif diff --git a/arch/arm/cpu/arm926ejs/mx25/relocate.S b/arch/arm/cpu/arm926ejs/mx25/relocate.S new file mode 100644 index 0000000000..8ebb81fc40 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx25/relocate.S @@ -0,0 +1,23 @@ +/* + * relocate - i.MX25-specific vector relocation + * + * Copyright (c) 2013 Albert ARIBAUD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* + * The i.MX25 SoC is very specific with respect to exceptions: it + * does not provide RAM at the high vectors address (0xFFFF0000), + * thus only the low address (0x00000000) is useable; but that is + * in ROM, so let's avoid relocating the vectors. + */ + .section .text.relocate_vectors,"ax",%progbits + +ENTRY(relocate_vectors) + + bx lr + +ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 42b6076c1f..7f19791736 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -21,65 +21,8 @@ */ #include -#include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp (gd->arch.tbl) -#define lastinc (gd->arch.lastinc) - -/* - * "time" is measured in 1 / CONFIG_SYS_HZ seconds, - * "tick" is internal timer period - */ -#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= MXC_CLK32; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * MXC_CLK32 + 999999; - do_div(us, 1000000); - return us; -} -#else -/* ~2% error */ -#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / MXC_CLK32) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - do_div(tick, TICK_PER_TIME); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - return time * TICK_PER_TIME; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us += US_PER_TICK - 1; - do_div(us, US_PER_TICK); - return us; -} -#endif /* nothing really to do with interrupts, just starts up a counter. */ /* The 32KHz 32-bit timer overruns in 134217 seconds */ @@ -104,63 +47,3 @@ int timer_init(void) return 0; } - -unsigned long long get_ticks(void) -{ - struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; - ulong now = readl(&gpt->counter); /* current tick value */ - - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timstamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; - - tbclk = MXC_CLK32; - return tbclk; -} diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile index 53ffaf2856..0edf1445fe 100644 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ b/arch/arm/cpu/arm926ejs/mx27/Makefile @@ -4,25 +4,8 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk +obj-y = generic.o reset.o timer.o -LIB = $(obj)lib$(SOC).o - -COBJS = generic.o reset.o timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ifndef CONFIG_SPL_BUILD +obj-y += relocate.o +endif diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c deleted file mode 100644 index 8db2a67f37..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); - DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); - - DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); - DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); - DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); - DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); - DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); - DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); - DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); - - DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); - DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); - DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); - DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); - DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S new file mode 100644 index 0000000000..0c4b272889 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S @@ -0,0 +1,51 @@ +/* + * relocate - i.MX27-specific vector relocation + * + * Copyright (c) 2013 Albert ARIBAUD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * The i.MX27 SoC is very specific with respect to exceptions: it + * does not provide RAM at the high vectors address (0xFFFF0000), + * thus only the low address (0x00000000) is useable; but that is + * in ROM. Therefore, vectors cannot be changed at all. + * + * However, these ROM-based vectors actually just perform indirect + * calls through pointers located in RAM at SoC-specific addresses, + * as follows: + * + * Offset Exception Use by ROM code + * 0x00000000 reset indirect branch to [0x00000014] + * 0x00000004 undefined instruction indirect branch to [0xfffffef0] + * 0x00000008 software interrupt indirect branch to [0xfffffef4] + * 0x0000000c prefetch abort indirect branch to [0xfffffef8] + * 0x00000010 data abort indirect branch to [0xfffffefc] + * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 + * 0x00000018 IRQ indirect branch to [0xffffff00] + * 0x0000001c FIQ indirect branch to [0xffffff04] + * + * In order to initialize exceptions on i.MX27, we must copy U-Boot's + * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 + * taking care not to copy vectors number 5 (reserved exception). + */ + + .section .text.relocate_vectors,"ax",%progbits + +ENTRY(relocate_vectors) + + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + ldr r1, =32 /* size of vector table */ + add r0, r0, r1 /* skip to indirect table */ + ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ + ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ + stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ + + bx lr + +ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index b29227e5fe..e80867ed60 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -5,40 +5,89 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-$(CONFIG_SPL_BUILD) := start.o -LIB = $(obj)lib$(SOC).o - -COBJS = clock.o mxs.o iomux.o timer.o +obj-y = clock.o mxs.o iomux.o timer.o ifdef CONFIG_SPL_BUILD -COBJS += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o +obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif -SRCS := $(START:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -START := $(addprefix $(obj),$(START)) +# Specify the target for use in elftosb call +MKIMAGE_TARGET-$(CONFIG_SOC_MX23) = mxsimage.mx23.cfg +MKIMAGE_TARGET-$(CONFIG_SOC_MX28) = mxsimage.mx28.cfg -all: $(obj).depend $(LIB) +# Generate HAB-capable IVT +# +# Note on computing the post-IVT size field value for the U-Boot binary. +# The value is the result of adding the following: +# -> The size of U-Boot binary aligned to 64B (u-boot.bin) +# -> The size of IVT block aligned to 64B (u-boot.ivt) +# -> The size of U-Boot signature (u-boot.sig), 3904 B +# -> The 64B hole in front of U-Boot binary for 'struct mxs_spl_data' passing +# +quiet_cmd_mkivt_mxs = MXSIVT $@ +cmd_mkivt_mxs = \ + sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \ + echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \ + tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \ + sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@ -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) +# Align binary to 64B +quiet_cmd_mkalign_mxs = MXSALGN $@ +cmd_mkalign_mxs = \ + dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \ + mv $@ $^ -# Specify the target for use in elftosb call -ELFTOSB_TARGET-$(CONFIG_MX23) = imx23 -ELFTOSB_TARGET-$(CONFIG_MX28) = imx28 +# Assemble the CSF file +quiet_cmd_mkcsfreq_mxs = MXSCSFR $@ +cmd_mkcsfreq_mxs = \ + ivt=$(word 1,$^) ; \ + bin=$(word 2,$^) ; \ + csf=$(word 3,$^) ; \ + sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \ + sed '/^\#\#Blocks/ d' > $@ ; \ + echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \ + echo " $3 0x0 0x40 \"$$ivt\"" >> $@ + +# Sign files +quiet_cmd_mkcst_mxs = MXSCST $@ +cmd_mkcst_mxs = cst -o $@ < $^ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +spl/u-boot-spl.ivt: spl/u-boot-spl.bin + $(call if_changed,mkalign_mxs) + $(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\ + 0x00008000,0x00008040) + +u-boot.ivt: u-boot.bin + $(call if_changed,mkalign_mxs) + $(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\ + 0x40001000,0x40001040) + +spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf + $(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000) + +u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf + $(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000) -$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd - sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@ +%.sig: %.csf + $(call if_changed,mkcst_mxs) -$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot $(OBJTREE)/spl/u-boot-spl $(OBJTREE)/u-boot.bd - $(TOPDIR)/tools/elftosb/bld/linux/elftosb -V -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb +quiet_cmd_mkimage_mxs = MKIMAGE $@ +cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) -######################################################################### +#u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE +# $(call if_changed,mkimage_mxs) +ELFTOSB_TARGET-$(CONFIG_SOC_MX23) = imx23 +ELFTOSB_TARGET-$(CONFIG_SOC_MX28) = imx28 -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +u-boot.bd: $(KBUILD_SRC)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd + sed "s@OBJTREE@$(objtree)@g" $^ > $@ -sinclude $(obj).depend +u-boot.sb: u-boot spl/u-boot-spl $(objtree)/u-boot.bd $(KBUILD_SRC)/tools/elftosb/bld/linux/elftosb + $(KBUILD_SRC)/tools/elftosb/bld/linux/elftosb -V -zf $(ELFTOSB_TARGET-y) -c u-boot.bd -o u-boot.sb -######################################################################### +u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE + $(call if_changed,mkimage_mxs) diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 4d0cc04583..6217c61b84 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -28,9 +28,9 @@ #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000) -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define MXC_SSPCLK_MAX MXC_SSPCLK0 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define MXC_SSPCLK_MAX MXC_SSPCLK3 #endif @@ -137,10 +137,10 @@ static uint32_t mxs_get_emiclk(void) static uint32_t mxs_get_gpmiclk(void) { -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) uint8_t *reg = &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) uint8_t *reg = &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]; #endif @@ -334,9 +334,9 @@ void mxs_set_lcdclk(uint32_t freq) if (freq == 0) return; -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr); -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr); #endif @@ -382,7 +382,7 @@ void mxs_set_lcdclk(uint32_t freq) k_best /= 1000; -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) writeb(CLKCTRL_FRAC_CLKGATE, &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]); writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), @@ -398,7 +398,7 @@ void mxs_set_lcdclk(uint32_t freq) while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY) ; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) writeb(CLKCTRL_FRAC_CLKGATE, &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]); writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), @@ -459,7 +459,7 @@ uint32_t mxc_get_clock(enum mxc_clock clk) return XTAL_FREQ_KHZ * 1000; case MXC_SSP0_CLK: return mxs_get_sspclk(MXC_SSPCLK0); -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 case MXC_SSP1_CLK: return mxs_get_sspclk(MXC_SSPCLK1); case MXC_SSP2_CLK: diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 2e6be06fd4..9285f2f6a0 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -14,14 +14,14 @@ #include #include -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define DRIVE_OFFSET 0x200 #define PULL_OFFSET 0x400 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define DRIVE_OFFSET 0x300 #define PULL_OFFSET 0x600 #else -#error "Please select CONFIG_MX23 or CONFIG_MX28" +#error "Please select CONFIG_SOC_MX23 or CONFIG_SOC_MX28" #endif /* diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 6f09f627ae..b451c66ee4 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -108,11 +108,11 @@ void enable_caches(void) */ void mx28_fixup_vt(uint32_t start_addr) { - /* ldr pc, [pc, #0x18] */ /* Jumptable location is 0x0 */ uint32_t *vt = (uint32_t *)0x20; uint32_t cr = get_cr(); + /* cppcheck-suppress nullPointer */ memcpy(vt, (void *)start_addr + 0x20, 32); set_cr(cr & ~CR_V); } @@ -246,7 +246,7 @@ int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* * Initializes on-chip ethernet controllers. */ -#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET) +#if defined(CONFIG_SOC_MX28) && defined(CONFIG_CMD_NET) int cpu_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg new file mode 100644 index 0000000000..83953daf28 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg @@ -0,0 +1,11 @@ +DISPLAYPROGRESS +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x1000 spl/u-boot-spl.bin + LOAD 0x8000 spl/u-boot-spl.ivt + LOAD 0x8040 spl/u-boot-spl.sig + CALL HAB 0x8000 0x0 + LOAD 0x40002000 u-boot.bin + LOAD 0x40001000 u-boot.ivt + LOAD 0x40001040 u-boot.sig + CALL HAB 0x40001000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg new file mode 100644 index 0000000000..e7028092a2 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -0,0 +1,7 @@ +DISPLAYPROGRESS +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x1000 spl/u-boot-spl.bin + CALL 0x1000 0x0 + LOAD 0x40002000 u-boot.bin + CALL 0x40002000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg new file mode 100644 index 0000000000..3f7bf59924 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -0,0 +1,9 @@ +DISPLAYPROGRESS +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x1000 spl/u-boot-spl.bin + LOAD IVT 0x8000 0x1000 + CALL HAB 0x8000 0x0 + LOAD 0x40002000 u-boot.bin + LOAD IVT 0x8000 0x40002000 + CALL HAB 0x8000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 74bc009dc5..aa8af0f2d8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -13,9 +13,16 @@ #include #include #include +#include #include "mxs_init.h" +DECLARE_GLOBAL_DATA_PTR; +static gd_t gdata __section(".data"); +#ifdef CONFIG_SPL_SERIAL_SUPPORT +static bd_t bdata __section(".data"); +#endif + /* * This delay function is intended to be used only in early stage of boot, where * clock are not set up yet. The timer used here is reset on every boot and @@ -38,14 +45,14 @@ void early_delay(int delay) #define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) static const iomux_cfg_t iomux_boot[] = { -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, @@ -64,7 +71,7 @@ static uint8_t mxs_get_bootmode_index(void) /* Setup IOMUX of bootmode pads to GPIO */ mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) /* Setup bootmode pins as GPIO input */ gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0); gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1); @@ -78,7 +85,7 @@ static uint8_t mxs_get_bootmode_index(void) bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) /* Setup bootmode pins as GPIO input */ gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); @@ -105,14 +112,45 @@ static uint8_t mxs_get_bootmode_index(void) return i; } -void mxs_common_spl_init(const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size) +static void mxs_spl_fixup_vectors(void) +{ + /* + * Copy our vector table to 0x0, since due to HAB, we cannot + * be loaded to 0x0. We want to have working vectoring though, + * thus this fixup. Our vectoring table is PIC, so copying is + * fine. + */ + extern uint32_t _start; + + /* cppcheck-suppress nullPointer */ + memcpy(0x0, &_start, 0x60); +} + +static void mxs_spl_console_init(void) +{ +#ifdef CONFIG_SPL_SERIAL_SUPPORT + gd->bd = &bdata; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#endif +} + +void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, + const iomux_cfg_t *iomux_setup, + const unsigned int iomux_size) { struct mxs_spl_data *data = (struct mxs_spl_data *) ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); uint8_t bootmode = mxs_get_bootmode_index(); + gd = &gdata; + + mxs_spl_fixup_vectors(); mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); + + mxs_spl_console_init(); + mxs_power_init(); mxs_mem_init(); diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 44cf84d5a9..93689a18a5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -20,7 +20,7 @@ static uint32_t dram_vals[] = { /* * i.MX28 DDR2 at 200MHz */ -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -73,7 +73,7 @@ static uint32_t dram_vals[] = { /* * i.MX23 DDR at 133MHz */ -#elif defined(CONFIG_MX23) +#elif defined(CONFIG_SOC_MX23) 0x01010001, 0x00010100, 0x01000101, 0x00000001, 0x00000101, 0x00000000, 0x00010000, 0x01000001, 0x00000000, 0x00000001, 0x07000200, 0x00070202, @@ -94,7 +94,7 @@ __weak void mxs_adjust_memory_params(uint32_t *dram_vals) { } -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 static void initialize_dram_values(void) { int i; @@ -138,10 +138,10 @@ static void mxs_mem_init_clock(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ const unsigned char divider = 33; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ const unsigned char divider = 21; #endif @@ -204,7 +204,7 @@ static void mxs_mem_setup_cpu_and_hbus(void) &clkctrl_regs->hw_clkctrl_clkseq_clr); } -void data_abort_memdetect_handler(void) +static void data_abort_memdetect_handler(void) { asm volatile("subs pc, lr, #4"); } @@ -235,15 +235,20 @@ uint32_t mxs_mem_get_size(void) return sz; } -#ifdef CONFIG_MX23 +#ifdef CONFIG_SOC_MX23 static void mx23_mem_setup_vddmem(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; + /* We must wait before and after disabling the current limiter! */ + early_delay(10000); + clrbits_le32(&power_regs->hw_power_vddmemctrl, POWER_VDDMEMCTRL_ENABLE_ILIMIT); + early_delay(10000); + } static void mx23_mem_init(void) @@ -270,7 +275,13 @@ static void mx23_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); - early_delay(20000); + + /* Wait for EMI_STAT bit DRAM_HALTED */ + for (;;) { + if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1))) + break; + early_delay(1000); + } /* Adjust EMI port priority. */ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); @@ -281,7 +292,7 @@ static void mx23_mem_init(void) } #endif -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 static void mx28_mem_init(void) { struct mxs_pinctrl_regs *pinctrl_regs = @@ -318,9 +329,9 @@ void mxs_mem_init(void) mxs_mem_init_clock(); -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) mx23_mem_init(); -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) mx28_mem_init(); #endif diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index ff4ff13dd9..8fc08afbca 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -74,6 +74,13 @@ static const int fixed_batt_supply; static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE; +/** + * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL + * + * This function switches the CPU core clock from PLL to 24MHz XTAL + * oscilator. This is necessary if the PLL is being reconfigured to + * prevent crash of the CPU core. + */ static void mxs_power_clock2xtal(void) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -84,6 +91,13 @@ static void mxs_power_clock2xtal(void) &clkctrl_regs->hw_clkctrl_clkseq_set); } +/** + * mxs_power_clock2pll() - Switch CPU core clock source to PLL + * + * This function switches the CPU core clock from 24MHz XTAL oscilator + * to PLL. This can only be called once the PLL has re-locked and once + * the PLL is stable after reconfiguration. + */ static void mxs_power_clock2pll(void) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -110,17 +124,23 @@ static int mxs_power_wait_rtc_stat(u32 mask) return !!(readl(&rtc_regs->hw_rtc_stat) & mask); } +/** + * mxs_power_set_auto_restart() - Set the auto-restart bit + * + * This function ungates the RTC block and sets the AUTO_RESTART + * bit to work around a design bug on MX28EVK Rev. A . + */ static int mxs_power_set_auto_restart(int on) { struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE; - /* - * Due to the hardware design bug of mx28 EVK-A - * we need to set the AUTO_RESTART bit. - */ if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0)) return 1; + /* Do nothing if flag already set */ + if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) + return 0; + if ((!(readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0) return 0; @@ -137,6 +157,14 @@ static int mxs_power_set_auto_restart(int on) return 0; } +/** + * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter + * + * This function configures the VDDIO, VDDA and VDDD linear regulators output + * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching + * converter. This is the recommended setting for the case where we use both + * linear regulators and DC-DC converter to power the VDDIO rail. + */ static void mxs_power_set_linreg(void) { /* Set linear regulator 25mV below switching converter */ @@ -153,6 +181,11 @@ static void mxs_power_set_linreg(void) POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); } +/** + * mxs_get_batt_volt() - Measure battery input voltage + * + * This function retrieves the battery input voltage and returns it. + */ static int mxs_get_batt_volt(void) { uint32_t volt = readl(&power_regs->hw_power_battmonitor); @@ -163,11 +196,24 @@ static int mxs_get_batt_volt(void) return volt; } +/** + * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot + * + * This function checks if the battery input voltage is higher than 3.6V and + * therefore allows the system to successfully boot using this power source. + */ static int mxs_is_batt_ready(void) { return (mxs_get_batt_volt() >= 3600); } +/** + * mxs_is_batt_good() - Test if battery is operational at all + * + * This function starts recharging the battery and tests if the input current + * provided by the 5V input recharging the battery is also sufficient to power + * the DC-DC converter. + */ static int mxs_is_batt_good(void) { uint32_t volt = mxs_get_batt_volt(); @@ -193,19 +239,28 @@ static int mxs_is_batt_good(void) volt = mxs_get_batt_volt(); - if (volt >= 3500) - return 0; - - if (volt >= 2400) - return 1; - writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, &power_regs->hw_power_charge_clr); writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); + if (volt >= 3500) { + return 0; + } + if (volt >= 2400) { + return 1; + } return 0; } +/** + * mxs_power_setup_5v_detect() - Start the 5V input detection comparator + * + * This function enables the 5V detection comparator and sets the 5V valid + * threshold to 4.4V . We use 4.4V threshold here to make sure that even + * under high load, the voltage drop on the 5V input won't be so critical + * to cause undervolt on the 4P2 linear regulator supplying the DC-DC + * converter and thus making the system crash. + */ static void mxs_power_setup_5v_detect(void) { /* Start 5V detection */ @@ -215,6 +270,12 @@ static void mxs_power_setup_5v_detect(void) POWER_5VCTRL_PWRUP_VBUS_CMPS); } +/** + * mxs_src_power_init() - Preconfigure the power block + * + * This function configures reasonable values for the DC-DC control loop + * and battery monitor. + */ static void mxs_src_power_init(void) { /* Improve efficieny and reduce transient ripple */ @@ -251,6 +312,12 @@ static void mxs_src_power_init(void) } } +/** + * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator + * + * This function configures the necessary parameters for the 4P2 linear + * regulator to supply the DC-DC converter from 5V input. + */ static void mxs_power_init_4p2_params(void) { /* Setup 4P2 parameters */ @@ -272,6 +339,12 @@ static void mxs_power_init_4p2_params(void) 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } +/** + * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2 + * @xfer: Select if the input shall be enabled or disabled + * + * This function enables or disables the 4P2 input into the DC-DC converter. + */ static void mxs_enable_4p2_dcdc_input(int xfer) { uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; @@ -366,6 +439,12 @@ static void mxs_enable_4p2_dcdc_input(int xfer) POWER_CTRL_ENIRQ_VDD5V_DROOP); } +/** + * mxs_power_init_4p2_regulator() - Start the 4P2 regulator + * + * This function enables the 4P2 regulator and switches the DC-DC converter + * to use the 4P2 input. + */ static void mxs_power_init_4p2_regulator(void) { uint32_t tmp, tmp2; @@ -408,7 +487,7 @@ static void mxs_power_init_4p2_regulator(void) * We then check the brownout status. If the brownout status is false, * the voltage is already close to the target voltage of 4.2V so we * can go ahead and set the 4P2 current limit to our max target limit. - * If the brownout status is true, we need to ramp us the current limit + * If the brownout status is true, we need to ramp up the current limit * so that we don't cause large inrush current issues. We step up the * current limit until the brownout status is false or until we've * reached our maximum defined 4p2 current limit. @@ -448,6 +527,12 @@ static void mxs_power_init_4p2_regulator(void) writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); } +/** + * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source + * + * This function configures the DC-DC converter to be supplied from the 4P2 + * linear regulator. + */ static void mxs_power_init_dcdc_4p2_source(void) { if (!(readl(&power_regs->hw_power_dcdc4p2) & @@ -467,6 +552,12 @@ static void mxs_power_init_dcdc_4p2_source(void) } } +/** + * mxs_power_enable_4p2() - Power up the 4P2 regulator + * + * This function drives the process of powering up the 4P2 linear regulator + * and switching the DC-DC converter input over to the 4P2 linear regulator. + */ static void mxs_power_enable_4p2(void) { uint32_t vdddctrl, vddactrl, vddioctrl; @@ -524,6 +615,14 @@ static void mxs_power_enable_4p2(void) &power_regs->hw_power_charge_clr); } +/** + * mxs_boot_valid_5v() - Boot from 5V supply + * + * This function configures the power block to boot from valid 5V input. + * This is called only if the 5V is reliable and can properly supply the + * CPU. This function proceeds to configure the 4P2 converter to be supplied + * from the 5V input. + */ static void mxs_boot_valid_5v(void) { /* @@ -544,6 +643,11 @@ static void mxs_boot_valid_5v(void) mxs_power_enable_4p2(); } +/** + * mxs_powerdown() - Shut down the system + * + * This function powers down the CPU completely. + */ static void mxs_powerdown(void) { writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); @@ -551,6 +655,12 @@ static void mxs_powerdown(void) &power_regs->hw_power_reset); } +/** + * mxs_batt_boot() - Configure the power block to boot from battery input + * + * This function configures the power block to boot from the battery voltage + * supply. + */ static void mxs_batt_boot(void) { clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); @@ -590,8 +700,18 @@ static void mxs_batt_boot(void) clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + + mxs_power_enable_4p2(); } +/** + * mxs_handle_5v_conflict() - Test if the 5V input is reliable + * + * This function tests if the 5V input can reliably supply the system. If it + * can, then proceed to configuring the system to boot from 5V source, otherwise + * try booting from battery supply. If we can not boot from battery supply + * either, shut down the system. + */ static void mxs_handle_5v_conflict(void) { uint32_t tmp; @@ -604,8 +724,8 @@ static void mxs_handle_5v_conflict(void) if (tmp & POWER_STS_VDDIO_BO) { /* - * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes - * unreliable + * If VDDIO has a brownout, then the VDD5V_GT_VDDIO + * becomes unreliable */ mxs_powerdown(); break; @@ -626,6 +746,12 @@ static void mxs_handle_5v_conflict(void) } } +/** + * mxs_5v_boot() - Configure the power block to boot from 5V input + * + * This function handles configuration of the power block when supplied by + * a 5V input. + */ static void mxs_5v_boot(void) { /* @@ -646,12 +772,17 @@ static void mxs_5v_boot(void) mxs_handle_5v_conflict(); } +/** + * mxs_init_batt_bo() - Configure battery brownout threshold + * + * This function configures the battery input brownout threshold. The value + * at which the battery brownout happens is configured to 3.0V in the code. + */ static void mxs_fixed_batt_boot(void) { writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_PWDN_5VBRNOUT | POWER_5VCTRL_ENABLE_DCDC | POWER_5VCTRL_ILIMIT_EQ_ZERO | POWER_5VCTRL_PWDN_5VBRNOUT | @@ -687,6 +818,12 @@ static void mxs_init_batt_bo(void) writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); } +/** + * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter + * + * This function turns off the VDDD linear regulator and therefore makes + * the VDDD rail be supplied only by the DC-DC converter. + */ static void mxs_switch_vddd_to_dcdc_source(void) { clrsetbits_le32(&power_regs->hw_power_vdddctrl, @@ -698,6 +835,15 @@ static void mxs_switch_vddd_to_dcdc_source(void) POWER_VDDDCTRL_DISABLE_STEPPING); } +/** + * mxs_power_configure_power_source() - Configure power block source + * + * This function is the core of the power configuration logic. The function + * selects the power block input source and configures the whole power block + * accordingly. After the configuration is complete and the system is stable + * again, the function switches the CPU clock source back to PLL. Finally, + * the function switches the voltage rails to DC-DC converter. + */ static void mxs_power_configure_power_source(void) { struct mxs_lradc_regs *lradc_regs = @@ -734,13 +880,22 @@ static void mxs_power_configure_power_source(void) mxs_switch_vddd_to_dcdc_source(); -#ifdef CONFIG_MX23 +#ifdef CONFIG_SOC_MX23 /* Fire up the VDDMEM LinReg now that we're all set. */ writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT, &power_regs->hw_power_vddmemctrl); #endif } +/** + * mxs_enable_output_rail_protection() - Enable power rail protection + * + * This function enables overload protection on the power rails. This is + * triggered if the power rails' voltage drops rapidly due to overload and + * in such case, the supply to the powerrail is cut-off, protecting the + * CPU from damage. Note that under such condition, the system will likely + * crash or misbehave. + */ static void mxs_enable_output_rail_protection(void) { writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | @@ -756,6 +911,13 @@ static void mxs_enable_output_rail_protection(void) POWER_VDDIOCTRL_PWDN_BRNOUT); } +/** + * mxs_get_vddio_power_source_off() - Get VDDIO rail power source + * + * This function tests if the VDDIO rail is supplied by linear regulator + * or by the DC-DC converter. Returns 1 if powered by linear regulator, + * returns 0 if powered by the DC-DC converter. + */ static int mxs_get_vddio_power_source_off(void) { uint32_t tmp; @@ -784,6 +946,13 @@ static int mxs_get_vddio_power_source_off(void) return 0; } +/** + * mxs_get_vddd_power_source_off() - Get VDDD rail power source + * + * This function tests if the VDDD rail is supplied by linear regulator + * or by the DC-DC converter. Returns 1 if powered by linear regulator, + * returns 0 if powered by the DC-DC converter. + */ static int mxs_get_vddd_power_source_off(void) { uint32_t tmp; @@ -853,13 +1022,15 @@ struct mxs_vddx_cfg { uint32_t bo_enirq; uint32_t bo_offset_mask; uint32_t bo_offset_offset; + uint16_t bo_min_mV; + uint16_t bo_max_mV; }; #define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n static const struct mxs_vddx_cfg mxs_vddio_cfg = { .reg = POWER_REG(hw_power_vddioctrl), -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) .step_mV = 25, #else .step_mV = 50, @@ -872,6 +1043,8 @@ static const struct mxs_vddx_cfg mxs_vddio_cfg = { .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO, .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK, .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET, + .bo_min_mV = 2700, + .bo_max_mV = 3475, }; static const struct mxs_vddx_cfg mxs_vddd_cfg = { @@ -885,12 +1058,14 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = { .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO, .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK, .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET, + .bo_min_mV = 800, + .bo_max_mV = 1475, }; static const struct mxs_vddx_cfg mxs_vdda_cfg = { .reg = POWER_REG(hw_power_vddactrl), - .step_mV = 50, - .lowest_mV = 2800, + .step_mV = 25, + .lowest_mV = 1800, .highest_mV = 3600, .powered_by_linreg = mxs_get_vdda_power_source_off, .trg_mask = POWER_VDDACTRL_TRG_MASK, @@ -898,9 +1073,11 @@ static const struct mxs_vddx_cfg mxs_vdda_cfg = { .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO, .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK, .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET, + .bo_min_mV = 1400, + .bo_max_mV = 2175, }; -#ifdef CONFIG_MX23 +#ifdef CONFIG_SOC_MX23 static const struct mxs_vddx_cfg mxs_vddmem_cfg = { .reg = POWER_REG(hw_power_vddmemctrl), .step_mV = 50, @@ -915,19 +1092,39 @@ static const struct mxs_vddx_cfg mxs_vddmem_cfg = { }; #endif +/** + * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail + * @cfg: Configuration data of the DC-DC converter rail + * @new_target: New target voltage of the DC-DC converter rail + * @new_brownout: New brownout trigger voltage + * + * This function configures the output voltage on the DC-DC converter rail. + * The rail is selected by the @cfg argument. The new voltage target is + * selected by the @new_target and the voltage is specified in mV. The + * new brownout value is selected by the @new_brownout argument and the + * value is also in mV. + */ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, - uint32_t new_target, uint32_t new_brownout) + uint32_t new_target, uint32_t bo_offset) { uint32_t cur_target, diff, bo_int = 0; int powered_by_linreg = 0; int adjust_up; - if (new_target < cfg->lowest_mV) + if (new_target < cfg->lowest_mV) { new_target = cfg->lowest_mV; - if (new_target > cfg->highest_mV) + } + if (new_target > cfg->highest_mV) { new_target = cfg->highest_mV; + } - new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV); + if (new_target - bo_offset < cfg->bo_min_mV) { + bo_offset = new_target - cfg->bo_min_mV; + } else if (new_target - bo_offset > cfg->bo_max_mV) { + bo_offset = new_target - cfg->bo_max_mV; + } + + bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV); cur_target = readl(cfg->reg); cur_target &= cfg->trg_mask; @@ -940,8 +1137,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, if (adjust_up && cfg->bo_irq) { if (powered_by_linreg) { - bo_int = readl(cfg->reg); - clrbits_le32(cfg->reg, cfg->bo_enirq); + bo_int = readl(&power_regs->hw_power_ctrl); + writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr); } setbits_le32(cfg->reg, cfg->bo_offset_mask); } @@ -982,14 +1179,23 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, if (adjust_up && powered_by_linreg) { writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr); if (bo_int & cfg->bo_enirq) - setbits_le32(cfg->reg, cfg->bo_enirq); + writel(cfg->bo_enirq, + &power_regs->hw_power_ctrl_set); } clrsetbits_le32(cfg->reg, cfg->bo_offset_mask, - new_brownout << cfg->bo_offset_offset); + bo_offset << cfg->bo_offset_offset); } } +/** + * mxs_setup_batt_detect() - Start the battery voltage measurement logic + * + * This function starts and configures the LRADC block. This allows the + * power initialization code to measure battery voltage and based on this + * knowledge, decide whether to boot at all, boot from battery or boot + * from 5V input. + */ static void mxs_setup_batt_detect(void) { mxs_lradc_init(); @@ -997,9 +1203,17 @@ static void mxs_setup_batt_detect(void) early_delay(10); } +/** + * mxs_ungate_power() - Ungate the POWER block + * + * This function ungates clock to the power block. In case the power block + * was still gated at this point, it will not be possible to configure the + * block and therefore the power initialization would fail. This function + * is only needed on i.MX233, on i.MX28 the power block is always ungated. + */ static void mxs_ungate_power(void) { -#ifdef CONFIG_MX23 +#ifdef CONFIG_SOC_MX23 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr); #endif } @@ -1010,6 +1224,12 @@ static void mxs_ungate_power(void) #define auto_restart 0 #endif +/** + * mxs_power_init() - The power block init main function + * + * This function calls all the power block initialization functions in + * proper sequence to start the power block. + */ void mxs_power_init(void) { mxs_ungate_power(); @@ -1031,7 +1251,7 @@ void mxs_power_init(void) mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL); mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL); mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL); -#ifdef CONFIG_MX23 +#ifdef CONFIG_SOC_MX23 mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL); setbits_le32(&power_regs->hw_power_vddmemctrl, @@ -1053,6 +1273,12 @@ void mxs_power_init(void) } #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT +/** + * mxs_power_wait_pswitch() - Wait for power switch to be pressed + * + * This function waits until the power-switch was pressed to start booting + * the board. + */ void mxs_power_wait_pswitch(void) { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index c6098d9821..9b60436539 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -24,67 +24,6 @@ #include #include -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: - .word _undefined_instruction -_software_interrupt: - .word _software_interrupt -_prefetch_abort: - .word _prefetch_abort -_data_abort: - .word _data_abort -_not_used: - .word _not_used -_irq: - .word _irq -_fiq: - .word _fiq -#else -/* - * Vector table, located at address 0x20. - * This table allows the code running AFTER SPL, the U-Boot, to install it's - * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, - * including it's interrupt vectoring table and the table at 0x0 is still the - * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table - * is still used. - */ -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq -#endif /* CONFIG_SPL_BUILD */ - .balignl 16, 0xdeadbeef - /* ************************************************************************* * @@ -98,93 +37,61 @@ _fiq: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#ifdef CONFIG_SPL_TEXT_BASE - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: -#ifdef IRAM_BASE_ADDR - .word IRAM_BASE_ADDR + 0x20 -#else - .word 0x0badc0de -#endif - -/* - * the actual reset code - */ - + .globl reset reset: + /* + * If the CPU is configured in "Wait JTAG connection mode", the stack + * pointer is not configured and is zero. This will cause crash when + * trying to push data onto stack right below here. Load the SP and make + * it point to the end of OCRAM if the SP is zero. + */ + cmp sp, #0x00000000 + ldreq sp, =CONFIG_SYS_INIT_SP_ADDR + /* * Store all registers on old stack pointer, this will allow us later to * return to the BootROM and let the BootROM load U-Boot into RAM. + * + * WARNING: Register r0 and r1 are used by the BootROM to pass data + * to the called code. Register r0 will contain arbitrary + * data that are set in the BootStream. In case this code + * was started with CALL instruction, register r1 will contain + * pointer to the return value this function can then set. + * The code below MUST NOT CHANGE register r0 and r1 ! */ push {r0-r12,r14} - /* save control register c1 */ - mrc p15, 0, r0, c1, c0, 0 - push {r0} + /* Save control register c1 */ + mrc p15, 0, r2, c1, c0, 0 + push {r2} - /* - * set the cpu to SVC32 mode and store old CPSR register content - */ - mrs r0,cpsr - push {r0} - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 + /* Set the cpu to SVC32 mode and store old CPSR register content. */ + mrs r2, cpsr + push {r2} + bic r2, r2, #0x1f + orr r2, r2, #0xd3 + msr cpsr, r2 bl board_init_ll + /* Restore BootROM's CPU mode (especially FIQ). */ + pop {r2} + msr cpsr,r2 + /* - * restore bootrom's cpu mode (especially FIQ) + * Restore c1 register. Especially set exception vector location + * back to BootROM space which is required by bootrom for USB boot. */ - pop {r0} - msr cpsr,r0 + pop {r2} + mcr p15, 0, r2, c1, c0, 0 + + pop {r0-r12,r14} /* - * restore c1 register - * (especially set exception vector location back to - * bootrom space which is required by bootrom for USB boot) + * In case this code was started by the CALL instruction, the register + * r0 is examined by the BootROM after this code returns. The value in + * r0 must be set to 0 to indicate successful return. */ - pop {r0} - mcr p15, 0, r0, c1, c0, 0 + mov r0, #0 - pop {r0-r12,r14} bx lr - diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 12789327cc..f4514f3145 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -7,7 +7,7 @@ * Based on code from LTIB: * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -16,9 +16,9 @@ #include /* Maximum fixed count */ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMER_LOAD_VAL 0xffff -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMER_LOAD_VAL 0xffffffff #endif @@ -63,9 +63,9 @@ int timer_init(void) mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); /* Set fixed_count to 0 */ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) writel(0, &timrot_regs->hw_timrot_timcount0); -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) writel(0, &timrot_regs->hw_timrot_fixed_count0); #endif @@ -74,31 +74,36 @@ int timer_init(void) TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL, &timrot_regs->hw_timrot_timctrl0); +#ifndef DEBUG_TIMER_WRAP /* Set fixed_count to maximum value */ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0); -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); #endif - -#ifndef DEBUG_TIMER_WRAP - /* Set fixed_count to maximum value */ - writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); -#else +#else /* DEBUG_TIMER_WRAP */ /* Set fixed_count so that the counter will wrap after 20 seconds */ +#if defined(CONFIG_SOC_MX23) + writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0); +#elif defined(CONFIG_SOC_MX28) writel(20 * MXS_INCREMENTER_HZ, &timrot_regs->hw_timrot_fixed_count0); +#endif gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ; /* Make the usec counter roll over 30 seconds after startup */ writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS); -#endif +#endif /* DEBUG_TIMER_WRAP */ writel(TIMROT_TIMCTRLn_UPDATE, &timrot_regs->hw_timrot_timctrl0_clr); #ifdef DEBUG_TIMER_WRAP - /* Set fixed_count to maximal value for subsequent loads */ + /* Set fixed_count to maximum value for subsequent loads */ +#if defined(CONFIG_SOC_MX23) + writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0); +#elif defined(CONFIG_SOC_MX28) writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); #endif +#endif /* DEBUG_TIMER_WRAP */ gd->arch.timer_rate_hz = MXS_INCREMENTER_HZ; gd->arch.tbl = TIMER_START; gd->arch.tbu = 0; @@ -116,16 +121,18 @@ unsigned long long get_ticks(void) struct mxs_timrot_regs *timrot_regs = (struct mxs_timrot_regs *)MXS_TIMROT_BASE; unsigned long now; -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) /* Upper bits are the valid ones. */ now = readl(&timrot_regs->hw_timrot_timcount0) >> TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET; -#else +#elif defined(CONFIG_SOC_MX28) /* The timer is counting down, so subtract the register value from * the counter period length (implicitly 2^32) to get an incrementing * timestamp */ now = -readl(&timrot_regs->hw_timrot_running_count0); +#else +#error "Don't know how to read timrot_regs" #endif ulong inc = now - gd->arch.lastinc; diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd index 8b6c30e8e9..3a51879d5e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd @@ -4,8 +4,8 @@ options { } sources { - u_boot_spl="OBJTREE/spl/u-boot-spl.bin"; - u_boot="OBJTREE/u-boot.bin"; + u_boot_spl="spl/u-boot-spl.bin"; + u_boot="u-boot.bin"; } section (0) { diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 40bcc3132f..bf2ac13056 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -16,11 +16,12 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; + . = CONFIG_SPL_TEXT_BASE; . = ALIGN(4); .text : { + *(.vectors) arch/arm/cpu/arm926ejs/mxs/start.o (.text*) *(.text*) } @@ -49,13 +50,20 @@ SECTIONS __bss_end = .; } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/cpu/arm926ejs/nomadik/Kconfig new file mode 100644 index 0000000000..265f336469 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/nomadik/Kconfig @@ -0,0 +1,16 @@ +if ARCH_NOMADIK + +choice + prompt "Nomadik board select" + +config NOMADIK_NHK8815 + bool "ST 8815 Nomadik Hardware Kit" + +endchoice + +config SYS_SOC + default "nomadik" + +source "board/st/nhk8815/Kconfig" + +endif diff --git a/arch/arm/cpu/arm926ejs/nomadik/Makefile b/arch/arm/cpu/arm926ejs/nomadik/Makefile index 8896b0b106..cdf1345d58 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/Makefile +++ b/arch/arm/cpu/arm926ejs/nomadik/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = timer.o gpio.o -SOBJS = reset.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = timer.o gpio.o +obj-y += reset.o diff --git a/arch/arm/cpu/arm926ejs/omap/Makefile b/arch/arm/cpu/arm926ejs/omap/Makefile index b519477c11..add923276c 100644 --- a/arch/arm/cpu/arm926ejs/omap/Makefile +++ b/arch/arm/cpu/arm926ejs/omap/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = timer.o cpuinfo.o -SOBJS = reset.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = timer.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o +obj-y += reset.o diff --git a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c index 02332eee0e..587d99a2bb 100644 --- a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c +++ b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c @@ -13,7 +13,7 @@ #include #include -#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) +#if defined(CONFIG_OMAP) #define omap_readw(x) *(volatile unsigned short *)(x) #define omap_readl(x) *(volatile unsigned long *)(x) @@ -239,4 +239,4 @@ int print_cpuinfo (void) return 0; } -#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */ +#endif /* #if defined(CONFIG_OMAP) */ diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c index 3e660347ee..b9715656c8 100644 --- a/arch/arm/cpu/arm926ejs/omap/timer.c +++ b/arch/arm/cpu/arm926ejs/omap/timer.c @@ -16,7 +16,7 @@ * (C) Copyright 2004 * Philippe Robin, ARM Ltd. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/cpu/arm926ejs/orion5x/Kconfig new file mode 100644 index 0000000000..5a542629c7 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/Kconfig @@ -0,0 +1,16 @@ +if ORION5X + +choice + prompt "Marvell Orion board select" + +config TARGET_EDMINIV2 + bool "LaCie Ethernet Disk mini V2" + +endchoice + +config SYS_SOC + default "orion5x" + +source "board/LaCie/edminiv2/Kconfig" + +endif diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile index 8f36dc0a6d..546ebcb52e 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/Makefile +++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile @@ -9,31 +9,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y = cpu.o -COBJS-y += dram.o -COBJS-y += timer.o +obj-y = cpu.o +obj-y += dram.o +obj-y += timer.o ifndef CONFIG_SKIP_LOWLEVEL_INIT -SOBJS := lowlevel_init.o +obj-y += lowlevel_init.o endif - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index b55c5f0943..f88db3b1f9 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -15,7 +15,6 @@ #include #include #include -#include #define BUFLEN 16 diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile index fb6bf63eed..988341f8fb 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/Makefile +++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile @@ -6,25 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y = cpu.o timer.o dram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cpu.o timer.o dram.o diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index 3006cd61e5..3f190bc0c0 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -5,37 +5,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y := cpu.o \ +obj-y := cpu.o \ reset.o \ timer.o ifdef CONFIG_SPL_BUILD -COBJS-y += spl.o spl_boot.o -COBJS-$(CONFIG_SPEAR600) += spear600.o -COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o -COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o -COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o -COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o +obj-y += spl.o spl_boot.o +obj-$(CONFIG_SPEAR600) += spear600.o +obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o +obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o +obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o +obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o endif -SRCS := $(START:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-$(CONFIG_SPL_BUILD) := start.o diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 3757ffb2c2..697e0945d7 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -38,7 +38,7 @@ int arch_cpu_init(void) #if defined(CONFIG_DW_UDC) periph1_clken |= MISC_USBDENB; #endif -#if defined(CONFIG_DW_I2C) +#if defined(CONFIG_SYS_I2C_DW) periph1_clken |= MISC_I2CENB; #endif #if defined(CONFIG_ST_SMI) diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c index fe52d8904a..6474e9d554 100644 --- a/arch/arm/cpu/arm926ejs/spear/spear600.c +++ b/arch/arm/cpu/arm926ejs/spear/spear600.c @@ -3,7 +3,7 @@ * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c index 3e7766f655..c846d758c9 100644 --- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c @@ -4,7 +4,7 @@ * * Copyright (C) 2012 Stefan Roese * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c index cc45ab7016..3d6ad04abf 100644 --- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2009 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c index 4097f03c2d..105b3058fb 100644 --- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2009 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c index c17442ed67..00b6b29276 100644 --- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2009 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c index 935ac941a2..a406c3e8c6 100644 --- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2009 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S index 7dbd5dbf99..290ac2e561 100644 --- a/arch/arm/cpu/arm926ejs/spear/start.S +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -17,29 +17,6 @@ #include -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: -_software_interrupt: -_prefetch_abort: -_data_abort: -_not_used: -_irq: -_fiq: - .word infinite_loop - -infinite_loop: - b infinite_loop - /* ************************************************************************* * @@ -53,9 +30,7 @@ infinite_loop: ************************************************************************* */ -/* - * the actual reset code - */ + .globl reset reset: /* diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index 4927736b9b..c7ee19912f 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -21,6 +21,7 @@ SECTIONS . = ALIGN(4); .text : { + *(.vectors) arch/arm/cpu/arm926ejs/spear/start.o (.text*) *(.text*) } @@ -49,13 +50,20 @@ SECTIONS __bss_end = .; } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 79e3e8ab63..8eb249475e 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -20,75 +20,6 @@ #include #include -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG -.globl _start -_start: -.globl _NOR_BOOT_CFG -_NOR_BOOT_CFG: - .word CONFIG_SYS_DV_NOR_BOOT_CFG - b reset -#else -.globl _start -_start: - b reset -#endif -#ifdef CONFIG_SPL_BUILD -/* No exception handlers in preloader */ - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang -/* pad to 64 byte boundary */ - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - -#endif /* CONFIG_SPL_BUILD */ - .balignl 16,0xdeadbeef - - /* ************************************************************************* * @@ -102,56 +33,7 @@ _fiq: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: -#ifdef IRAM_BASE_ADDR - .word IRAM_BASE_ADDR + 0x20 -#else - .word 0x0badc0de -#endif - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -228,189 +110,3 @@ flush_dcache: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - @ space on current stack for scratch reg. - sub r13, r13, #4 - str r0, [r13] - ldr r0, IRQ_STACK_START_IN @ get our mode stack - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - ldr sp, _TEXT_BASE /* switch to abort stack */ -1: - bl 1b /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/cpu/arm926ejs/versatile/Kconfig new file mode 100644 index 0000000000..d2e76f4afc --- /dev/null +++ b/arch/arm/cpu/arm926ejs/versatile/Kconfig @@ -0,0 +1,15 @@ +if ARCH_VERSATILE + +config SYS_BOARD + default "versatile" + +config SYS_VENDOR + default "armltd" + +config SYS_SOC + default "versatile" + +config SYS_CONFIG_NAME + default "versatile" + +endif diff --git a/arch/arm/cpu/arm926ejs/versatile/Makefile b/arch/arm/cpu/arm926ejs/versatile/Makefile index d4659f9ce8..907f5161a8 100644 --- a/arch/arm/cpu/arm926ejs/versatile/Makefile +++ b/arch/arm/cpu/arm926ejs/versatile/Makefile @@ -5,27 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = timer.o -SOBJS = reset.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = timer.o +obj-y += reset.o diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c index 54361622b4..5d694d85ef 100644 --- a/arch/arm/cpu/arm926ejs/versatile/timer.c +++ b/arch/arm/cpu/arm926ejs/versatile/timer.c @@ -16,21 +16,11 @@ * (C) Copyright 2004 * Philippe Robin, ARM Ltd. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include -#define TIMER_LOAD_VAL 0xffffffff - -/* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - #define TIMER_ENABLE (1 << 7) #define TIMER_MODE_MSK (1 << 6) #define TIMER_MODE_FR (0 << 6) @@ -69,112 +59,6 @@ int timer_init (void) *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; - /* init the timestamp and lastdec value */ - reset_timer_masked(); - return 0; } -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay (unsigned long usec) -{ - ulong tmo, tmp; - - if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - }else{ /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ - reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ - else - tmo += tmp; /* else, set advancing stamp wake up time */ - - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (lastdec >= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ - } else { /* we have overflow of the count down timer */ - /* nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll and cause problems. - */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; -} diff --git a/arch/arm/cpu/arm946es/Makefile b/arch/arm/cpu/arm946es/Makefile index 87e6c65c7b..a44bddc2fb 100644 --- a/arch/arm/cpu/arm946es/Makefile +++ b/arch/arm/cpu/arm946es/Makefile @@ -5,28 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y = start.o -LIB = $(obj)lib$(CPU).o - -START = start.o - -COBJS = cpu.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cpu.o diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk index 1e41c11686..438668d6ff 100644 --- a/arch/arm/cpu/arm946es/config.mk +++ b/arch/arm/cpu/arm946es/config.mk @@ -5,13 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index aa499cc677..e20e5a89aa 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -6,7 +6,7 @@ * (C) Copyright 2002 * Gary Jennejohn, DENX Software Engineering, * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -16,6 +16,7 @@ #include #include #include +#include static void cache_flush(void); @@ -51,3 +52,15 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); } + +#ifndef CONFIG_INTEGRATOR + +__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +{ + writew(0x0, 0xfffece10); + writew(0x8, 0xfffece10); + for (;;) + ; +} + +#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index e16b088141..41123716a7 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -19,45 +19,6 @@ #include #include -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -_vectors_end: - /* ************************************************************************* * @@ -71,52 +32,7 @@ _vectors_end: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -183,189 +99,3 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -# ifdef CONFIG_INTEGRATOR - - /* Satisfied by general board level routine */ - -#else - - .align 5 -.globl reset_cpu -reset_cpu: - - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever - -rstctl1: - .word 0xfffece10 - -#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/arch/arm/cpu/arm_intcm/Makefile b/arch/arm/cpu/arm_intcm/Makefile deleted file mode 100644 index cc516f744b..0000000000 --- a/arch/arm/cpu/arm_intcm/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk deleted file mode 100644 index 1e41c11686..0000000000 --- a/arch/arm/cpu/arm_intcm/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm_intcm/cpu.c b/arch/arm/cpu/arm_intcm/cpu.c deleted file mode 100644 index 0d00e4b7ae..0000000000 --- a/arch/arm/cpu/arm_intcm/cpu.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code for an unknown cpu - * - hence fairly empty...... - */ - -#include -#include - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - disable_interrupts (); - - /* Since the CM has unknown processor we do not support - * cache operations - */ - - return (0); -} diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S deleted file mode 100644 index 5783df1ef2..0000000000 --- a/arch/arm/cpu/arm_intcm/start.S +++ /dev/null @@ -1,331 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - ************************************************************************* - * - * Jump vector table - * - ************************************************************************* - */ - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - mov pc, lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -cpu_init_crit: - /* arm_int_generic assumes the ARM boot monitor, or user software, - * has initialized the platform - */ - mov pc, lr /* back to my caller */ -#endif -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -.globl undefined_instruction -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -.globl software_interrupt -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -.globl prefetch_abort -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -.globl data_abort -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -.globl not_used -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - .align 5 -.globl irq -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -.globl fiq -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -.globl irq -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -.globl fiq -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig new file mode 100644 index 0000000000..61e7c82459 --- /dev/null +++ b/arch/arm/cpu/armv7/Kconfig @@ -0,0 +1,34 @@ +if CPU_V7 + +config CPU_V7_HAS_NONSEC + bool + +config CPU_V7_HAS_VIRT + bool + +config ARMV7_NONSEC + boolean "Enable support for booting in non-secure mode" if EXPERT + depends on CPU_V7_HAS_NONSEC + default y + ---help--- + Say Y here to enable support for booting in non-secure / SVC mode. + +config ARMV7_BOOT_SEC_DEFAULT + boolean "Boot in secure mode by default" if EXPERT + depends on ARMV7_NONSEC + default n + ---help--- + Say Y here to boot in secure mode by default even if non-secure mode + is supported. This option is useful to boot kernels which do not + suppport booting in non-secure mode. Only set this if you need it. + This can be overriden at run-time by setting the bootm_boot_mode env. + variable to "sec" or "nonsec". + +config ARMV7_VIRT + boolean "Enable support for hardware virtualization" if EXPERT + depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC + default y + ---help--- + Say Y here to boot in hypervisor (HYP) mode when booting non-secure. + +endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 2ba88d0a96..21d63e1a91 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -5,35 +5,61 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y := start.o -LIB = $(obj)lib$(CPU).o +obj-y += cache_v7.o -START := start.o +obj-y += cpu.o +obj-y += syslib.o -COBJS += cache_v7.o - -COBJS += cpu.o -COBJS += syslib.o - -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),) -SOBJS += lowlevel_init.o +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_SOC_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) +ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) +obj-y += lowlevel_init.o +endif endif -SRCS := $(START:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) +ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) +obj-y += nonsec_virt.o +obj-y += virt-v7.o +obj-y += virt-dt.o +endif -######################################################################### +ifneq ($(CONFIG_ARMV7_PSCI),) +obj-y += psci.o +endif -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +obj-$(CONFIG_IPROC) += iproc-common/ +obj-$(CONFIG_KONA) += kona-common/ +obj-$(CONFIG_OMAP_COMMON) += omap-common/ +obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o +obj-$(CONFIG_TEGRA) += tegra-common/ -sinclude $(obj).depend +ifneq (,$(filter s5pc1xx exynos,$(SOC))) +obj-y += s5p-common/ +endif -######################################################################### +obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ +obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/ +obj-$(CONFIG_AT91FAMILY) += at91/ +obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ +obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ +obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ +obj-$(CONFIG_ARCH_EXYNOS) += exynos/ +obj-$(CONFIG_ARCH_HIGHBANK) += highbank/ +obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ +obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ +obj-$(if $(filter mx5,$(SOC)),y) += mx5/ +obj-$(CONFIG_SOC_MX6) += mx6/ +obj-$(CONFIG_OMAP34XX) += omap3/ +obj-$(CONFIG_OMAP44XX) += omap4/ +obj-$(CONFIG_OMAP54XX) += omap5/ +obj-$(CONFIG_RMOBILE) += rmobile/ +obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/ +obj-$(CONFIG_SOCFPGA) += socfpga/ +obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ +obj-$(CONFIG_TEGRA20) += tegra20/ +obj-$(CONFIG_U8500) += u8500/ +obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ +obj-$(CONFIG_SOC_VF610) += vf610/ +obj-$(CONFIG_ZYNQ) += zynq/ diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 2db1d410c9..aae3f096b2 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -4,40 +4,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-$(CONFIG_AM33XX) += clock_am33xx.o -COBJS-$(CONFIG_TI814X) += clock_ti814x.o -COBJS += sys_info.o -COBJS += mem.o -COBJS += ddr.o -COBJS += emif4.o -COBJS += board.o -COBJS += mux.o -COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o -COBJS-$(CONFIG_NAND_AM33XX) += elm.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_AM33XX) += clock_am33xx.o +obj-$(CONFIG_TI814X) += clock_ti814x.o +obj-$(CONFIG_AM43XX) += clock_am43xx.o + +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) +obj-y += clock.o +endif + +obj-$(CONFIG_TI816X) += clock_ti816x.o +obj-y += sys_info.o +obj-y += ddr.o +obj-y += emif4.o +obj-y += board.o +obj-y += mux.o diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 032d28c1cb..64322b828a 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -9,7 +9,9 @@ */ #include +#include #include +#include #include #include #include @@ -27,74 +29,85 @@ #include #include #include +#include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -static const struct gpio_bank gpio_bank_am33xx[4] = { +#ifdef CONFIG_DM_GPIO +static const struct omap_gpio_platdata am33xx_gpio[] = { + { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, + { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, +#ifdef CONFIG_AM43XX + { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX }, +#endif +}; + +U_BOOT_DEVICES(am33xx_gpios) = { + { "gpio_omap", &am33xx_gpio[0] }, + { "gpio_omap", &am33xx_gpio[1] }, + { "gpio_omap", &am33xx_gpio[2] }, + { "gpio_omap", &am33xx_gpio[3] }, +#ifdef CONFIG_AM43XX + { "gpio_omap", &am33xx_gpio[4] }, + { "gpio_omap", &am33xx_gpio[5] }, +#endif +}; + +# ifndef CONFIG_OF_CONTROL +/* + * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove + * the CONFIGs. At the same time, we should move this to the board files. + */ +static const struct ns16550_platdata am33xx_serial[] = { + { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK }, +# ifdef CONFIG_SYS_NS16550_COM2 + { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK }, +# ifdef CONFIG_SYS_NS16550_COM3 + { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK }, +# endif +# endif +}; + +U_BOOT_DEVICES(am33xx_uarts) = { + { "serial_omap", &am33xx_serial[0] }, +# ifdef CONFIG_SYS_NS16550_COM2 + { "serial_omap", &am33xx_serial[1] }, +# ifdef CONFIG_SYS_NS16550_COM3 + { "serial_omap", &am33xx_serial[2] }, + { "serial_omap", &am33xx_serial[3] }, + { "serial_omap", &am33xx_serial[4] }, + { "serial_omap", &am33xx_serial[5] }, +# endif +# endif +}; +# endif + +#else + +static const struct gpio_bank gpio_bank_am33xx[] = { { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, +#ifdef CONFIG_AM43XX + { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX }, +#endif }; const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; -#ifdef CONFIG_HW_WATCHDOG -void hw_watchdog_reset(void) -{ - struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - static int trg __attribute__((section(".data"))); - - switch (trg) { - case 0: - case 1: - if (readl(&wdtimer->wdtwwps) & (1 << 4)) - return; - writel(trg ? 0x5555 : 0xaaaa, &wdtimer->wdtwspr); - break; - case 2: - if (readl(&wdtimer->wdtwwps) & (1 << 2)) - return; - /* 10 sec timeout */ - writel(-32768 * 10, &wdtimer->wdtwldr); - - if (readl(&wdtimer->wdtwwps) & (1 << 0)) - return; - /* prescaler = 1 */ - writel(0, &wdtimer->wdtwclr); - break; - - case 3: - case 4: - /* enable watchdog */ - if (readl(&wdtimer->wdtwwps) & (1 << 4)) - return; - writel((trg & 1) ? 0xBBBB : 0x4444, &wdtimer->wdtwspr); - break; - - default: - /* retrigger watchdog */ - if (readl(&wdtimer->wdtwwps) & (1 << 3)) - return; - - writel(trg, &wdtimer->wdtwtgr); - trg ^= 0x2; - return; - } - trg++; -} -#endif - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} #endif #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) @@ -112,12 +125,6 @@ int __cpu_mmc_init(bd_t *bis) int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__cpu_mmc_init"))); #endif -void setup_clocks_for_console(void) -{ - /* Not yet implemented */ - return; -} - /* AM33XX has two MUSB controllers which can be host or gadget */ #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \ (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) @@ -198,28 +205,49 @@ int arch_misc_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD -void rtc32k_enable(void) +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +/* + * In the case of non-SPL based booting we'll want to call these + * functions a tiny bit later as it will require gd to be set and cleared + * and that's not true in s_init in this case so we cannot do it there. + */ +int board_early_init_f(void) { - struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; + prcm_init(); + set_mux_conf_regs(); + + return 0; +} + +/* + * This function is the place to do per-board things such as ramp up the + * MPU clock frequency. + */ +__weak void am33xx_spl_board_init(void) +{ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) +static void rtc32k_enable(void) +{ + struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; /* * Unlock the RTC's registers. For more details please see the * RTC_SS section of the TRM. In order to unlock we need to * write these specific values (keys) in this order. */ - writel(0x83e70b13, &rtc->kick0r); - writel(0x95a4f1e0, &rtc->kick1r); + writel(RTC_KICK0R_WE, &rtc->kick0r); + writel(RTC_KICK1R_WE, &rtc->kick1r); /* Enable the RTC 32K OSC by setting bits 3 and 6. */ writel((1 << 3) | (1 << 6), &rtc->osc); } +#endif -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -void uart_soft_reset(void) +static void uart_soft_reset(void) { struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; u32 regval; @@ -236,4 +264,45 @@ void uart_soft_reset(void) regval |= UART_SMART_IDLE_EN; writel(regval, &uart_base->uartsyscfg); } + +static void watchdog_disable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} + +void s_init(void) +{ + /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + enable_norboot_pin_mux(); +#endif + watchdog_disable(); + set_uart_mux_conf(); + setup_clocks_for_console(); + uart_soft_reset(); +#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT) + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#endif +#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) + /* Enable RTC32K clock */ + rtc32k_enable(); +#endif +#ifdef CONFIG_SPL_BUILD + board_early_init_f(); + sdram_init(); +#endif +} #endif diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c new file mode 100644 index 0000000000..ec7d46838b --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -0,0 +1,188 @@ +/* + * clock.c + * + * Clock initialization for AM33XX boards. + * Derived from OMAP4 boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static void setup_post_dividers(const struct dpll_regs *dpll_regs, + const struct dpll_params *params) +{ + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, dpll_regs->cm_div_m3_dpll); + if (params->m4 >= 0) + writel(params->m4, dpll_regs->cm_div_m4_dpll); + if (params->m5 >= 0) + writel(params->m5, dpll_regs->cm_div_m5_dpll); + if (params->m6 >= 0) + writel(params->m6, dpll_regs->cm_div_m6_dpll); +} + +static inline void do_lock_dpll(const struct dpll_regs *dpll_regs) +{ + clrsetbits_le32(dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_lock(const struct dpll_regs *dpll_regs) +{ + if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, + (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("DPLL locking failed for 0x%x\n", + dpll_regs->cm_clkmode_dpll); + hang(); + } +} + +static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs) +{ + clrsetbits_le32(dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_bypass(const struct dpll_regs *dpll_regs) +{ + if (!wait_on_value(ST_DPLL_CLK_MASK, 0, + (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("Bypassing DPLL failed 0x%x\n", + dpll_regs->cm_clkmode_dpll); + } +} + +static void bypass_dpll(const struct dpll_regs *dpll_regs) +{ + do_bypass_dpll(dpll_regs); + wait_for_bypass(dpll_regs); +} + +void do_setup_dpll(const struct dpll_regs *dpll_regs, + const struct dpll_params *params) +{ + u32 temp; + + if (!params) + return; + + temp = readl(dpll_regs->cm_clksel_dpll); + + bypass_dpll(dpll_regs); + + /* Set M & N */ + temp &= ~CM_CLKSEL_DPLL_M_MASK; + temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; + + temp &= ~CM_CLKSEL_DPLL_N_MASK; + temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; + + writel(temp, dpll_regs->cm_clksel_dpll); + + setup_post_dividers(dpll_regs, params); + + /* Wait till the DPLL locks */ + do_lock_dpll(dpll_regs); + wait_for_lock(dpll_regs); +} + +static void setup_dplls(void) +{ + const struct dpll_params *params; + + params = get_dpll_core_params(); + do_setup_dpll(&dpll_core_regs, params); + + params = get_dpll_mpu_params(); + do_setup_dpll(&dpll_mpu_regs, params); + + params = get_dpll_per_params(); + do_setup_dpll(&dpll_per_regs, params); + writel(0x300, &cmwkup->clkdcoldodpllper); + + params = get_dpll_ddr_params(); + do_setup_dpll(&dpll_ddr_regs, params); +} + +static inline void wait_for_clk_enable(u32 *clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + u32 bound = LDELAY; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock enable failed for 0x%p idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Enable clock module - %p\n", clkctrl_addr); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Enable clock domain - %p\n", clkctrl_reg); +} + +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_explicit_en, u8 wait_for_enable) +{ + u32 i, max = 100; + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains[i]; i++) { + enable_clock_domain(clk_domains[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { + enable_clock_module(clk_modules_explicit_en[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; +} + +/* + * Before scaling up the clocks we need to have the PMIC scale up the + * voltages first. This will be dependent on which PMIC is in use + * and in some cases we may not be scaling things up at all and thus not + * need to do anything here. + */ +__weak void scale_vcores(void) +{ +} + +void prcm_init() +{ + enable_basic_clocks(); + scale_vcores(); + setup_dplls(); +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index c05d115735..23cd9a9fe9 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -32,16 +32,15 @@ #define CLK_MODE_SEL 0x7 #define DPLL_CLKDCOLDO_GATE_CTRL 0x300 - #define OSC (V_OSCK/1000000) #define MPUPLL_M CONFIG_SYS_MPUCLK -#define MPUPLL_N (OSC-1) +#define MPUPLL_N (OSC - 1) #define MPUPLL_M2 1 /* Core PLL Fdll = 1 GHZ, */ #define COREPLL_M 1000 -#define COREPLL_N (OSC-1) +#define COREPLL_N (OSC - 1) #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ @@ -53,143 +52,158 @@ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below */ #define PERPLL_M 960 -#define PERPLL_N (OSC-1) +#define PERPLL_N (OSC - 1) #define PERPLL_M2 5 /* DDR Freq is 266 MHZ for now */ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ #define DDRPLL_M 266 -#define DDRPLL_N (OSC-1) +#define DDRPLL_N (OSC - 1) #define DDRPLL_M2 1 -const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; -const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; -const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; -const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; +struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC; + +const struct dpll_regs dpll_mpu_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x88, + .cm_idlest_dpll = CM_WKUP + 0x20, + .cm_clksel_dpll = CM_WKUP + 0x2C, + .cm_div_m2_dpll = CM_WKUP + 0xA8, +}; + +const struct dpll_regs dpll_core_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x90, + .cm_idlest_dpll = CM_WKUP + 0x5C, + .cm_clksel_dpll = CM_WKUP + 0x68, + .cm_div_m4_dpll = CM_WKUP + 0x80, + .cm_div_m5_dpll = CM_WKUP + 0x84, + .cm_div_m6_dpll = CM_WKUP + 0xD8, +}; + +const struct dpll_regs dpll_per_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x8C, + .cm_idlest_dpll = CM_WKUP + 0x70, + .cm_clksel_dpll = CM_WKUP + 0x9C, + .cm_div_m2_dpll = CM_WKUP + 0xAC, +}; -#ifdef CONFIG_SPL_BUILD -#define enable_clk(reg, val) __enable_clk(#reg, ®, val) +const struct dpll_regs dpll_ddr_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x94, + .cm_idlest_dpll = CM_WKUP + 0x34, + .cm_clksel_dpll = CM_WKUP + 0x40, + .cm_div_m2_dpll = CM_WKUP + 0xA0, +}; -static void __enable_clk(const char *name, const void *reg, u32 mask) +struct dpll_params dpll_mpu_opp100 = { + CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_core_opp100 = { + 1000, OSC-1, -1, -1, 10, 8, 4}; +const struct dpll_params dpll_mpu = { + MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_core = { + 50, OSC-1, -1, -1, 1, 1, 1}; +const struct dpll_params dpll_per = { + 960, OSC-1, 5, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_mpu_params(void) { - unsigned long timeout = 10000000; - - writel(mask, reg); - while (readl(reg) != mask) - /* poor man's timeout, since timers not initialized */ - if (timeout-- == 0) - /* no error message, since console not yet available */ - break; + return &dpll_mpu; } -static void enable_interface_clocks(void) +const struct dpll_params *get_dpll_core_params(void) { - /* Enable all the Interconnect Modules */ - enable_clk(cmper->l3clkctrl, PRCM_MOD_EN); - enable_clk(cmper->l4lsclkctrl, PRCM_MOD_EN); - enable_clk(cmper->l4fwclkctrl, PRCM_MOD_EN); - enable_clk(cmwkup->wkl4wkclkctrl, PRCM_MOD_EN); - enable_clk(cmper->l3instrclkctrl, PRCM_MOD_EN); - enable_clk(cmper->l4hsclkctrl, PRCM_MOD_EN); -#ifdef CONFIG_HW_WATCHDOG - enable_clk(cmwkup->wdtimer1ctrl, PRCM_MOD_EN); -#endif - /* GPIO0 */ - enable_clk(cmwkup->wkgpio0clkctrl, PRCM_MOD_EN); + return &dpll_core; } -/* - * Force power domain wake up transition - * Ensure that the corresponding interface clock is active before - * using the peripheral - */ -static void power_domain_wkup_transition(void) +const struct dpll_params *get_dpll_per_params(void) { - writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl); + return &dpll_per; } -/* - * Enable the peripheral clock for required peripherals - */ -static void enable_per_clocks(void) +void setup_clocks_for_console(void) { - /* Enable the control module though RBL would have done it*/ - enable_clk(cmwkup->wkctrlclkctrl, PRCM_MOD_EN); - /* Enable the timer2 clock */ - enable_clk(cmper->timer2clkctrl, PRCM_MOD_EN); - /* Select the Master osc 24 MHZ as Timer2 clock source */ - writel(0x1, &cmdpll->clktimer2clk); - -#ifdef CONFIG_SYS_NS16550_COM1 - /* UART0 */ - enable_clk(cmwkup->wkup_uart0ctrl, PRCM_MOD_EN); -#endif -#ifdef CONFIG_SYS_NS16550_COM2 - enable_clk(cmper->uart1clkctrl, PRCM_MOD_EN); -#endif -#ifdef CONFIG_SYS_NS16550_COM3 - enable_clk(cmper->uart2clkctrl, PRCM_MOD_EN); -#endif -#ifdef CONFIG_SYS_NS16550_COM4 - enable_clk(cmper->uart3clkctrl, PRCM_MOD_EN); -#endif -#ifdef CONFIG_SYS_NS16550_COM5 - enable_clk(cmper->uart4clkctrl, PRCM_MOD_EN); -#endif -#ifdef CONFIG_SYS_NS16550_COM6 - enable_clk(cmper->uart5clkctrl, PRCM_MOD_EN); -#endif - /* GPMC */ - enable_clk(cmper->gpmcclkctrl, PRCM_MOD_EN); - - /* ELM */ - enable_clk(cmper->elmclkctrl, PRCM_MOD_EN); - - /* Ethernet */ - enable_clk(cmper->cpswclkstctrl, PRCM_MOD_EN); - enable_clk(cmper->cpgmac0clkctrl, PRCM_MOD_EN); - - /* MMC */ -#ifdef CONFIG_OMAP_MMC_DEV_0 - enable_clk(cmper->mmc0clkctrl, PRCM_MOD_EN); -#endif -#ifdef CONFIG_OMAP_MMC_DEV_1 - enable_clk(cmper->mmc1clkctrl, PRCM_MOD_EN); -#endif - /* LCD */ - enable_clk(cmper->lcdclkctrl, PRCM_MOD_EN); - - /* MMC1 */ - writel(PRCM_MOD_EN, &cmper->mmc1clkctrl); - while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN) - ; - - /* i2c0 */ - enable_clk(cmwkup->wkup_i2c0ctrl, PRCM_MOD_EN); - - /* GPIO1-3 */ - enable_clk(cmper->gpio1clkctrl, PRCM_MOD_EN); - enable_clk(cmper->gpio2clkctrl, PRCM_MOD_EN); - enable_clk(cmper->gpio3clkctrl, PRCM_MOD_EN); - - /* i2c1 */ - enable_clk(cmper->i2c1clkctrl, PRCM_MOD_EN); - - /* spi0 */ - enable_clk(cmper->spi0clkctrl, PRCM_MOD_EN); + clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + clrsetbits_le32(&cmwkup->wkup_uart0ctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart1clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart2clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart3clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart4clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart5clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} - /* rtc */ - enable_clk(cmrtc->rtcclkctrl, PRCM_MOD_EN); +void enable_basic_clocks(void) +{ + u32 *const clk_domains[] = { + &cmper->l3clkstctrl, + &cmper->l4fwclkstctrl, + &cmper->l3sclkstctrl, + &cmper->l4lsclkstctrl, + &cmwkup->wkclkstctrl, + &cmper->emiffwclkctrl, + &cmrtc->clkstctrl, + 0 + }; + + u32 *const clk_modules_explicit_en[] = { + &cmper->l3clkctrl, + &cmper->l4lsclkctrl, + &cmper->l4fwclkctrl, + &cmwkup->wkl4wkclkctrl, + &cmper->l3instrclkctrl, + &cmper->l4hsclkctrl, + &cmwkup->wkgpio0clkctrl, + &cmwkup->wkctrlclkctrl, + &cmper->timer2clkctrl, + &cmper->gpmcclkctrl, + &cmper->elmclkctrl, + &cmper->mmc0clkctrl, + &cmper->mmc1clkctrl, + &cmwkup->wkup_i2c0ctrl, + &cmper->gpio1clkctrl, + &cmper->gpio2clkctrl, + &cmper->gpio3clkctrl, + &cmper->i2c1clkctrl, + &cmper->cpgmac0clkctrl, + &cmper->spi0clkctrl, + &cmrtc->rtcclkctrl, + &cmper->usb0clkctrl, + &cmper->emiffwclkctrl, + &cmper->emifclkctrl, + 0 + }; + + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); - /* usb0 */ - enable_clk(cmper->usb0clkctrl, PRCM_MOD_EN); + /* Select the Master osc 24 MHZ as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); } -#endif /* CONFIG_SPL_BUILD */ - void mpu_pll_config_val(int mpull_m) { u32 clkmode, clksel, div_m2; @@ -375,39 +389,6 @@ void ddr_pll_config(unsigned int ddrpll_m) ; } -#ifdef CONFIG_SPL_BUILD -void enable_emif_clocks(void) -{ - /* Enable the EMIF_FW Functional clock */ - writel(PRCM_MOD_EN, &cmper->emiffwclkctrl); - /* Enable EMIF0 Clock */ - writel(PRCM_MOD_EN, &cmper->emifclkctrl); - /* Poll if module is functional */ - while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN) - ; -} - -/* - * Configure the PLL/PRCM for necessary peripherals - */ -void pll_init() -{ - mpu_pll_config(); - core_pll_config(); - per_pll_config(); - disp_pll_config(); - - /* Enable the required interconnect clocks */ - enable_interface_clocks(); - - /* Power domain wake up transition */ - power_domain_wkup_transition(); - - /* Enable the required peripherals */ - enable_per_clocks(); -} -#endif - #define M(mn) (((mn) & CLK_SEL_MASK) >> CLK_SEL_SHIFT) #define N(mn) ((mn) & CLK_DIV2_MASK) diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c new file mode 100644 index 0000000000..31188c85bc --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -0,0 +1,121 @@ +/* + * clock_am43xx.c + * + * clocks for AM43XX based boards + * Derived from AM33XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; + +const struct dpll_regs dpll_mpu_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x560, + .cm_idlest_dpll = CM_WKUP + 0x564, + .cm_clksel_dpll = CM_WKUP + 0x56c, + .cm_div_m2_dpll = CM_WKUP + 0x570, +}; + +const struct dpll_regs dpll_core_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x520, + .cm_idlest_dpll = CM_WKUP + 0x524, + .cm_clksel_dpll = CM_WKUP + 0x52C, + .cm_div_m4_dpll = CM_WKUP + 0x538, + .cm_div_m5_dpll = CM_WKUP + 0x53C, + .cm_div_m6_dpll = CM_WKUP + 0x540, +}; + +const struct dpll_regs dpll_per_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x5E0, + .cm_idlest_dpll = CM_WKUP + 0x5E4, + .cm_clksel_dpll = CM_WKUP + 0x5EC, + .cm_div_m2_dpll = CM_WKUP + 0x5F0, +}; + +const struct dpll_regs dpll_ddr_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x5A0, + .cm_idlest_dpll = CM_WKUP + 0x5A4, + .cm_clksel_dpll = CM_WKUP + 0x5AC, + .cm_div_m2_dpll = CM_WKUP + 0x5B0, + .cm_div_m4_dpll = CM_WKUP + 0x5B8, +}; + +void setup_clocks_for_console(void) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + + /* Do not add any spl_debug prints in this function */ + clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + /* Enable UART0 */ + clrsetbits_le32(&cmwkup->wkup_uart0ctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(&cmwkup->wkup_uart0ctrl); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + } +} + +void enable_basic_clocks(void) +{ + u32 *const clk_domains[] = { + &cmper->l3clkstctrl, + &cmper->l3sclkstctrl, + &cmper->l4lsclkstctrl, + &cmwkup->wkclkstctrl, + &cmper->emifclkstctrl, + 0 + }; + + u32 *const clk_modules_explicit_en[] = { + &cmper->l3clkctrl, + &cmper->l4lsclkctrl, + &cmper->l4fwclkctrl, + &cmwkup->wkl4wkclkctrl, + &cmper->l3instrclkctrl, + &cmper->l4hsclkctrl, + &cmwkup->wkgpio0clkctrl, + &cmwkup->wkctrlclkctrl, + &cmper->timer2clkctrl, + &cmper->gpmcclkctrl, + &cmper->elmclkctrl, + &cmper->mmc0clkctrl, + &cmper->mmc1clkctrl, + &cmwkup->wkup_i2c0ctrl, + &cmper->gpio1clkctrl, + &cmper->gpio2clkctrl, + &cmper->gpio3clkctrl, + &cmper->gpio4clkctrl, + &cmper->gpio5clkctrl, + &cmper->i2c1clkctrl, + &cmper->cpgmac0clkctrl, + &cmper->emiffwclkctrl, + &cmper->emifclkctrl, + &cmper->otfaemifclkctrl, + &cmper->qspiclkctrl, + 0 + }; + + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + + /* Select the Master osc clk as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index 658772bbe3..9b5a47b018 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -100,103 +100,8 @@ struct ad_pll { #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) -/* PRCM */ #define ENET_CLKCTRL_CMPL 0x30000 -#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) - -struct cm_def { - unsigned int resv0[2]; - unsigned int l3fastclkstctrl; - unsigned int resv1[1]; - unsigned int pciclkstctrl; - unsigned int resv2[1]; - unsigned int ducaticlkstctrl; - unsigned int resv3[1]; - unsigned int emif0clkctrl; - unsigned int emif1clkctrl; - unsigned int dmmclkctrl; - unsigned int fwclkctrl; - unsigned int resv4[10]; - unsigned int usbclkctrl; - unsigned int resv5[1]; - unsigned int sataclkctrl; - unsigned int resv6[4]; - unsigned int ducaticlkctrl; - unsigned int pciclkctrl; -}; - -#define CM_ALWON_BASE (PRCM_BASE + 0x1400) - -struct cm_alwon { - unsigned int l3slowclkstctrl; - unsigned int ethclkstctrl; - unsigned int l3medclkstctrl; - unsigned int mmu_clkstctrl; - unsigned int mmucfg_clkstctrl; - unsigned int ocmc0clkstctrl; - unsigned int vcpclkstctrl; - unsigned int mpuclkstctrl; - unsigned int sysclk4clkstctrl; - unsigned int sysclk5clkstctrl; - unsigned int sysclk6clkstctrl; - unsigned int rtcclkstctrl; - unsigned int l3fastclkstctrl; - unsigned int resv0[67]; - unsigned int mcasp0clkctrl; - unsigned int mcasp1clkctrl; - unsigned int mcasp2clkctrl; - unsigned int mcbspclkctrl; - unsigned int uart0clkctrl; - unsigned int uart1clkctrl; - unsigned int uart2clkctrl; - unsigned int gpio0clkctrl; - unsigned int gpio1clkctrl; - unsigned int i2c0clkctrl; - unsigned int i2c1clkctrl; - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; - unsigned int wdtimerclkctrl; - unsigned int spiclkctrl; - unsigned int mailboxclkctrl; - unsigned int spinboxclkctrl; - unsigned int mmudataclkctrl; - unsigned int resv2[2]; - unsigned int mmucfgclkctrl; - unsigned int resv3[2]; - unsigned int ocmc0clkctrl; - unsigned int vcpclkctrl; - unsigned int resv4[2]; - unsigned int controlclkctrl; - unsigned int resv5[2]; - unsigned int gpmcclkctrl; - unsigned int ethernet0clkctrl; - unsigned int ethernet1clkctrl; - unsigned int mpuclkctrl; - unsigned int debugssclkctrl; - unsigned int l3clkctrl; - unsigned int l4hsclkctrl; - unsigned int l4lsclkctrl; - unsigned int rtcclkctrl; - unsigned int tpccclkctrl; - unsigned int tptc0clkctrl; - unsigned int tptc1clkctrl; - unsigned int tptc2clkctrl; - unsigned int tptc3clkctrl; - unsigned int resv7[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -}; - #define SATA_PLL_BASE (CTRL_BASE + 0x0720) struct sata_pll { @@ -264,11 +169,6 @@ const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; */ static void enable_per_clocks(void) { - /* UART0 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; - /* HSMMC1 */ writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) @@ -282,6 +182,12 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) ; + + /* RTC clocks */ + writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); + while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) + ; } /* @@ -305,11 +211,8 @@ static u32 pll_dco_freq_sel(u32 clkout_dco) static u32 pll_sigma_delta_val(u32 clkout_dco) { u32 sig_val = 0; - float frac_div; - frac_div = (float) clkout_dco / 250; - frac_div = frac_div + 0.90; - sig_val = (int)frac_div; + sig_val = (clkout_dco + 225) / 250; sig_val = sig_val << 24; return sig_val; @@ -455,8 +358,6 @@ void sata_pll_config(void) ; } -void enable_emif_clocks(void) {}; - void enable_dmm_clocks(void) { writel(PRCM_MOD_EN, &cmdef->fwclkctrl); @@ -477,13 +378,19 @@ void enable_dmm_clocks(void) ; } +void setup_clocks_for_console(void) +{ + unlock_pll_control_mmr(); + /* UART0 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; +} /* * Configure the PLL/PRCM for necessary peripherals */ -void pll_init() +void prcm_init(void) { - unlock_pll_control_mmr(); - /* Enable the control module */ writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c new file mode 100644 index 0000000000..ace4a5afef --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c @@ -0,0 +1,445 @@ +/* + * clock_ti816x.c + * + * Clocks for TI816X based boards + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * Based on TI-PSP-04.00.02.14 : + * + * Copyright (C) 2009, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define CM_PLL_BASE (CTRL_BASE + 0x0400) + +/* Main PLL */ +#define MAIN_N 64 +#define MAIN_P 0x1 +#define MAIN_INTFREQ1 0x8 +#define MAIN_FRACFREQ1 0x800000 +#define MAIN_MDIV1 0x2 +#define MAIN_INTFREQ2 0xE +#define MAIN_FRACFREQ2 0x0 +#define MAIN_MDIV2 0x1 +#define MAIN_INTFREQ3 0x8 +#define MAIN_FRACFREQ3 0xAAAAB0 +#define MAIN_MDIV3 0x3 +#define MAIN_INTFREQ4 0x9 +#define MAIN_FRACFREQ4 0x55554F +#define MAIN_MDIV4 0x3 +#define MAIN_INTFREQ5 0x9 +#define MAIN_FRACFREQ5 0x374BC6 +#define MAIN_MDIV5 0xC +#define MAIN_MDIV6 0x48 +#define MAIN_MDIV7 0x4 + +/* DDR PLL */ +#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x4 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x3 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ +#define DDR_N 50 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x9 +#define DDR_FRACFREQ2 0x0 +#define DDR_MDIV2 0x19 +#define DDR_INTFREQ3 0x13 +#define DDR_FRACFREQ3 0x800000 +#define DDR_MDIV3 0x2 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +#define CONTROL_STATUS (CTRL_BASE + 0x40) +#define DDR_RCD (CTRL_BASE + 0x070C) +#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) +#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) +#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) + +#define INTCPS_SYSCONFIG 0x48200010 +#define CM_SYSCLK10_CLKSEL 0x48180324 + +struct cm_pll { + unsigned int mainpll_ctrl; /* offset 0x400 */ + unsigned int mainpll_pwd; + unsigned int mainpll_freq1; + unsigned int mainpll_div1; + unsigned int mainpll_freq2; + unsigned int mainpll_div2; + unsigned int mainpll_freq3; + unsigned int mainpll_div3; + unsigned int mainpll_freq4; + unsigned int mainpll_div4; + unsigned int mainpll_freq5; + unsigned int mainpll_div5; + unsigned int resv0[1]; + unsigned int mainpll_div6; + unsigned int resv1[1]; + unsigned int mainpll_div7; + unsigned int ddrpll_ctrl; /* offset 0x440 */ + unsigned int ddrpll_pwd; + unsigned int resv2[1]; + unsigned int ddrpll_div1; + unsigned int ddrpll_freq2; + unsigned int ddrpll_div2; + unsigned int ddrpll_freq3; + unsigned int ddrpll_div3; + unsigned int ddrpll_freq4; + unsigned int ddrpll_div4; + unsigned int ddrpll_freq5; + unsigned int ddrpll_div5; + unsigned int videopll_ctrl; /* offset 0x470 */ + unsigned int videopll_pwd; + unsigned int videopll_freq1; + unsigned int videopll_div1; + unsigned int videopll_freq2; + unsigned int videopll_div2; + unsigned int videopll_freq3; + unsigned int videopll_div3; + unsigned int resv3[4]; + unsigned int audiopll_ctrl; /* offset 0x4A0 */ + unsigned int audiopll_pwd; + unsigned int resv4[2]; + unsigned int audiopll_freq2; + unsigned int audiopll_div2; + unsigned int audiopll_freq3; + unsigned int audiopll_div3; + unsigned int audiopll_freq4; + unsigned int audiopll_div4; + unsigned int audiopll_freq5; + unsigned int audiopll_div5; +}; + +const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; +const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; +const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + +void enable_dmm_clocks(void) +{ + writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); + writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); + writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); + + /* Wait for clocks to be active */ + while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) + ; + /* Wait for emif0 to be fully functional, including OCP */ + while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) + ; + /* Wait for emif1 to be fully functional, including OCP */ + while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) + ; + + writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); + /* Wait for dmm to be fully functional, including OCP */ + while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) + ; + + /* Enable Tiled Access */ + writel(0x80000000, DMM_PAT_BASE_ADDR); +} + +/* assume delay is aprox at least 1us */ +static void ddr_delay(int d) +{ + int i; + + /* + * read a control register. + * this is a bit more delay and cannot be optimized by the compiler + * assuming one read takes 200 cycles and A8 is runing 1 GHz + * somewhat conservative setting + */ + for (i = 0; i < 50*d; i++) + readl(CONTROL_STATUS); +} + +static void main_pll_init_ti816x(void) +{ + u32 main_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + main_pll_ctrl |= BIT(2); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Enable PLL by setting BIT3 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFF7; + main_pll_ctrl |= BIT(3); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFF; + main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Power up clock1-7 */ + writel(0x0, &cmpll->mainpll_pwd); + + /* Program the freq and divider values for clock1-7 */ + writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), + &cmpll->mainpll_freq1); + writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), + &cmpll->mainpll_freq2); + writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), + &cmpll->mainpll_freq3); + writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), + &cmpll->mainpll_freq4); + writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), + &cmpll->mainpll_freq5); + writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); + + writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); + + writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Put the PLL in normal mode, disable bypass */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); +} + +static void ddr_pll_bypass_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFFB; + ddr_pll_ctrl |= BIT(2); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); +} + +static void ddr_pll_init_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + /* Enable PLL by setting BIT3 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFF7; + ddr_pll_ctrl |= BIT(3); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFF; + ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + ddr_delay(10); + + /* Power up clock1-5 */ + writel(0x0, &cmpll->ddrpll_pwd); + + /* Program the freq and divider values for clock1-3 */ + writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), + &cmpll->ddrpll_freq2); + writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); + writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + ddr_delay(1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + + ddr_delay(5); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Power up RCD */ + writel(BIT(0), DDR_RCD); +} + +static void peripheral_enable(void) +{ + /* Wake-up the l3_slow clock */ + writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); + + /* + * Note on Timers: + * There are 8 timers(0-7) out of which timer 0 is a secure timer. + * Timer 0 mux should not be changed + * + * To access the timer registers we need the to be + * enabled which is what we do in the first step + */ + + /* Enable timer1 */ + writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); + /* Select timer1 clock to be CLKIN (27MHz) */ + writel(BIT(1), CM_TIMER1_CLKSEL); + + /* Wait for timer1 to be ON-ACTIVE */ + while (((readl(&cmalwon->l3slowclkstctrl) + & (0x80000<<1))>>20) != 1) + ; + /* Wait for timer1 to be enabled */ + while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) + ; + /* Active posted mode */ + writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); + while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) + ; + /* Start timer1 */ + writel(BIT(0), (DM_TIMER1_BASE + 0x38)); + + /* eFuse */ + writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); + while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) + ; + + /* Enable gpio0 */ + writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); + while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) + ; + writel((BIT(8)), &cmalwon->gpio0clkctrl); + + /* Enable spi */ + writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); + while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) + ; + + /* Enable i2c0 */ + writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); + while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) + ; + + /* Enable ethernet0 */ + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + + /* Enable hsmmc */ + writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); + while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) + ; +} + +void setup_clocks_for_console(void) +{ + /* Fix ROM code bug - from TI-PSP-04.00.02.14 */ + writel(0x0, CM_SYSCLK10_CLKSEL); + + ddr_pll_bypass_ti816x(); + + /* Enable uart0-2 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); + while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); + while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) + ; + while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) + ; +} + +void prcm_init(void) +{ + /* Enable the control */ + writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + + main_pll_init_ti816x(); + ddr_pll_init_ti816x(); + + /* + * With clk freqs setup to desired values, + * enable the required peripherals + */ + peripheral_enable(); +} diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk index 8e3668f781..5294d16708 100644 --- a/arch/arm/cpu/armv7/am33xx/config.mk +++ b/arch/arm/cpu/armv7/am33xx/config.mk @@ -4,8 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/MLO -ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap +ALL-y += MLO +ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 11cbac441c..07a88c2ed4 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -39,27 +39,137 @@ static struct ddr_data_regs *ddr_data_reg[2] = { static struct ddr_cmdtctrl *ioctrl_reg = (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR; +static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) +{ + u32 mr; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + + mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; +} + +static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) +{ + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); +} + +static void configure_mr(int nr, u32 cs) +{ + u32 mr_addr; + + while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(nr, cs, LPDDR2_MR10, 0x56); + + set_mr(nr, cs, LPDDR2_MR1, 0x43); + set_mr(nr, cs, LPDDR2_MR2, 0x2); + + mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; + set_mr(nr, cs, mr_addr, 0x2); +} + +/* + * Configure EMIF4D5 registers and MR registers For details about these magic + * values please see the EMIF registers section of the TRM. + */ +void config_sdram_emif4d5(const struct emif_regs *regs, int nr) +{ + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); + + writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_win, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_win); + writel(regs->emif_rd_wr_lvl_rmp_ctl, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + writel(regs->emif_rd_wr_exec_thresh, + &emif_reg[nr]->emif_rd_wr_exec_thresh); + + /* + * for most SOCs these registers won't need to be changed so only + * write to these registers if someone explicitly has set the + * register's value. + */ + if(regs->emif_cos_config) { + writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map); + writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map); + writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map); + writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config); + } + + /* + * Sequence to ensure that the PHY is in a known state prior to + * startting hardware leveling. Also acts as to latch some state from + * the EMIF into the PHY. + */ + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + + clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, + EMIF_REG_INITREF_DIS_MASK); + + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + + /* Perform hardware leveling. */ + udelay(1000); + writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | + 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | + 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + + writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + + /* Enable read leveling */ + writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + + /* + * Enable full read and write leveling. Wait for read and write + * leveling bit to clear RDWRLVLFULL_START bit 31 + */ + while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0) + ; + + /* Check the timeout register to see if leveling is complete */ + if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0) + puts("DDR3 H/W leveling incomplete with errors\n"); + + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) { + configure_mr(nr, 0); + configure_mr(nr, 1); + } +} + /** * Configure SDRAM */ void config_sdram(const struct emif_regs *regs, int nr) { if (regs->zq_config) { - /* - * A value of 0x2800 for the REF CTRL will give us - * about 570us for a delay, which will be long enough - * to configure things. - */ - writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); - writel(regs->sdram_config, &cstat->emif_sdram_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); } /** @@ -75,15 +185,82 @@ void set_sdram_timings(const struct emif_regs *regs, int nr) writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); } +/* + * Configure EXT PHY registers for hardware leveling + */ +static void ext_phy_settings(const struct emif_regs *regs, int nr) +{ + /* + * Enable hardware leveling on the EMIF. For details about these + * magic values please see the EMIF registers section of the TRM. + */ + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw); + writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23); + writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw); + writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24); + writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw); + writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25); + writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); + writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + + /* + * Sequence to ensure that the PHY is again in a known state after + * hardware leveling. + */ + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); +} + /** * Configure DDR PHY */ void config_ddr_phy(const struct emif_regs *regs, int nr) { + /* + * Disable initialization and refreshes for now until we + * finish programming EMIF regs. + * Also set time between rising edge of DDR_RESET to rising + * edge of DDR_CKE to > 500us per memory spec. + */ +#ifndef CONFIG_AM43XX + setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, + EMIF_REG_INITREF_DIS_MASK); +#endif + if (regs->zq_config) + writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); + + if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) + ext_phy_settings(regs, nr); } /** @@ -91,16 +268,16 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) */ void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { + if (!cmd) + return; + writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); - writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff); writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); - writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff); writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); - writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff); writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); } @@ -111,6 +288,9 @@ void config_ddr_data(const struct ddr_data *data, int nr) { int i; + if (!data) + return; + for (i = 0; i < DDR_DATA_REGS_NR; i++) { writel(data->datardsratio0, &(ddr_data_reg[nr]+i)->dt0rdsratio0); @@ -124,18 +304,23 @@ void config_ddr_data(const struct ddr_data *data, int nr) &(ddr_data_reg[nr]+i)->dt0fwsratio0); writel(data->datawrsratio0, &(ddr_data_reg[nr]+i)->dt0wrsratio0); - writel(data->datauserank0delay, - &(ddr_data_reg[nr]+i)->dt0rdelays0); - writel(data->datadldiff0, - &(ddr_data_reg[nr]+i)->dt0dldiff0); } } -void config_io_ctrl(unsigned long val) +void config_io_ctrl(const struct ctrl_ioregs *ioregs) { - writel(val, &ioctrl_reg->cm0ioctl); - writel(val, &ioctrl_reg->cm1ioctl); - writel(val, &ioctrl_reg->cm2ioctl); - writel(val, &ioctrl_reg->dt0ioctl); - writel(val, &ioctrl_reg->dt1ioctl); + if (!ioregs) + return; + + writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); + writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); + writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); + writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); + writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); +#ifdef CONFIG_AM43XX + writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); + writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); + writel(ioregs->emif_sdram_config_ext, + &ioctrl_reg->emif_sdram_config_ext); +#endif } diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c deleted file mode 100644 index b0b05f4c85..0000000000 --- a/arch/arm/cpu/armv7/am33xx/elm.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2010-2011 Texas Instruments, - * Mansoor Ahamed - * - * BCH Error Location Module (ELM) support. - * - * NOTE: - * 1. Supports only continuous mode. Dont see need for page mode in uboot - * 2. Supports only syndrome polynomial 0. i.e. poly local variable is - * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial - * sets in uboot - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#define ELM_DEFAULT_POLY 0 - -/* make sure this variable does not end up in bss - * because that would corrupt the relocation section - * that is overlayed with the bss section - */ -static struct elm *elm_cfg __attribute__((section(".data"))); - -/** - * elm_load_syndromes - Load BCH syndromes based on nibble selection - * @syndrome: BCH syndrome - * @nibbles: - * @poly: Syndrome Polynomial set to use - * - * Load BCH syndromes based on nibble selection - */ -static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) -{ - u32 val; - struct syndrome *sf = &elm_cfg->syndrome_fragments[poly]; - - /* reg 0 */ - val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) | - (syndrome[3] << 24); - writel(val, &sf->syndrome_fragment_x[0]); - - /* reg 1 */ - val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) | - (syndrome[7] << 24); - writel(val, &sf->syndrome_fragment_x[1]); - - /* BCH 8-bit with 26 nibbles (4*8=32) */ - if (nibbles > 13) { - /* reg 2 */ - val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | - (syndrome[11] << 24); - writel(val, &sf->syndrome_fragment_x[2]); - - /* reg 3 */ - val = syndrome[12] | (syndrome[13] << 8) | (syndrome[14] << 16) | - (syndrome[15] << 24); - writel(val, &sf->syndrome_fragment_x[3]); - } - - /* BCH 16-bit with 52 nibbles (7*8=56) */ - if (nibbles > 26) { - /* reg 4 */ - val = syndrome[16] | (syndrome[17] << 8) | (syndrome[18] << 16) | - (syndrome[19] << 24); - writel(val, &sf->syndrome_fragment_x[4]); - - /* reg 5 */ - val = syndrome[20] | (syndrome[21] << 8) | (syndrome[22] << 16) | - (syndrome[23] << 24); - writel(val, &sf->syndrome_fragment_x[5]); - - /* reg 6 */ - val = syndrome[24] | (syndrome[25] << 8) | (syndrome[26] << 16) | - (syndrome[27] << 24); - writel(val, &sf->syndrome_fragment_x[6]); - } -} - -/** - * elm_check_error - Check for BCH errors and return error locations - * @syndrome: BCH syndrome - * @nibbles: - * @error_count: Returns number of errrors in the syndrome - * @error_locations: Returns error locations (in decimal) in this array - * - * Check the provided syndrome for BCH errors and return error count - * and locations in the array passed. Returns -1 if error is not correctable, - * else returns 0 - */ -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, - u32 *error_locations) -{ - u8 poly = ELM_DEFAULT_POLY; - s8 i; - u32 location_status; - - elm_load_syndromes(syndrome, nibbles, poly); - - /* start processing */ - writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) - | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID), - &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); - - /* wait for processing to complete */ - while (!(readl(&elm_cfg->irqstatus) & (0x1 << poly))); - /* clear status */ - writel((readl(&elm_cfg->irqstatus) & ~(0x1 << poly)), - &elm_cfg->irqstatus); - - /* check if correctable */ - location_status = readl(&elm_cfg->error_location[poly].location_status); - if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) - return -1; - - /* get error count */ - *error_count = readl(&elm_cfg->error_location[poly].location_status) & - ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; - - for (i = 0; i < *error_count; i++) - error_locations[i] = - readl(&elm_cfg->error_location[poly].error_location_x[i]); - - return 0; -} - - -/** - * elm_config - Configure ELM module - * @level: 4 / 8 / 16 bit BCH - * - * Configure ELM module based on BCH level. - * Set mode as continuous mode. - * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used. - * Also, the mode is set only for syndrome 0 - */ -int elm_config(enum bch_level level) -{ - u32 val; - u8 poly = ELM_DEFAULT_POLY; - u32 buffer_size = 0x7FF; - - /* config size and level */ - val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK; - val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) & - ELM_LOCATION_CONFIG_ECC_SIZE_MASK); - writel(val, &elm_cfg->location_config); - - /* config continous mode */ - /* enable interrupt generation for syndrome polynomial set */ - writel((readl(&elm_cfg->irqenable) | (0x1 << poly)), - &elm_cfg->irqenable); - /* set continuous mode for the syndrome polynomial set */ - writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)), - &elm_cfg->page_ctrl); - - return 0; -} - -/** - * elm_reset - Do a soft reset of ELM - * - * Perform a soft reset of ELM and return after reset is done. - */ -void elm_reset(void) -{ - /* initiate reset */ - writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET), - &elm_cfg->sysconfig); - - /* wait for reset complete and normal operation */ - while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) != - ELM_SYSSTATUS_RESETDONE) - ; -} - -/** - * elm_init - Initialize ELM module - * - * Initialize ELM support. Currently it does only base address init - * and ELM reset. - */ -void elm_init(void) -{ - elm_cfg = (struct elm *)ELM_BASE; - elm_reset(); -} diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index ad7b70f93a..9cf816c89a 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -21,6 +21,10 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + sdram_init(); +#endif + /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CONFIG_SYS_SDRAM_BASE, @@ -35,16 +39,26 @@ void dram_init_banksize(void) } -#ifdef CONFIG_SPL_BUILD +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_TI81XX static struct dmm_lisa_map_regs *hw_lisa_map_regs = (struct dmm_lisa_map_regs *)DMM_BASE; +#endif +#ifndef CONFIG_TI816X static struct vtp_reg *vtpreg[2] = { (struct vtp_reg *)VTP0_CTRL_ADDR, (struct vtp_reg *)VTP1_CTRL_ADDR}; +#endif #ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif +#ifdef CONFIG_AM43XX +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +static struct cm_device_inst *cm_device = + (struct cm_device_inst *)CM_DEVICE_INST; +#endif +#ifdef CONFIG_TI81XX void config_dmm(const struct dmm_lisa_map_regs *regs) { enable_dmm_clocks(); @@ -59,7 +73,9 @@ void config_dmm(const struct dmm_lisa_map_regs *regs) writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); } +#endif +#ifndef CONFIG_TI816X static void config_vtp(int nr) { writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, @@ -74,27 +90,50 @@ static void config_vtp(int nr) VTP_CTRL_READY) ; } +#endif + +void __weak ddr_pll_config(unsigned int ddrpll_m) +{ +} -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) { - enable_emif_clocks(); ddr_pll_config(pll); +#ifndef CONFIG_TI816X config_vtp(nr); +#endif config_cmd_ctrl(ctrl, nr); config_ddr_data(data, nr); #ifdef CONFIG_AM33XX - config_io_ctrl(ioctrl); + config_io_ctrl(ioregs); + + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); + +#endif +#ifdef CONFIG_AM43XX + writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); + while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0) + ; + + config_io_ctrl(ioregs); /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); + + /* Allow EMIF to control DDR_RESET */ + writel(0x00000000, &ddrctrl->ddrioctrl); #endif /* Program EMIF instance */ config_ddr_phy(regs, nr); set_sdram_timings(regs, nr); - config_sdram(regs, nr); + if (get_emif_rev(EMIF1_BASE) == EMIF_4D5) + config_sdram_emif4d5(regs, nr); + else + config_sdram(regs, nr); } #endif diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c deleted file mode 100644 index b1a1329f86..0000000000 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, - * - * Author : - * Mansoor Ahamed - * - * Initial Code from: - * Manikandan Pillai - * Richard Woodruff - * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_CMD_NAND) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -#endif - - -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); - sdelay(2000); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* putting a blanket check on GPMC based on ZeBu for now */ - struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; -#ifdef CONFIG_CMD_NAND - const u32 *gpmc_config = NULL; - u32 base = 0; - u32 size = 0; -#endif - /* global settings */ - writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000100, &gpmc_cfg->irqstatus); - writel(0x00000100, &gpmc_cfg->irqenable); - writel(0x00000012, &gpmc_cfg->config); - /* - * Disable the GPMC0 config set by ROM code - */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - -#ifdef CONFIG_CMD_NAND - gpmc_config = gpmc_m_nand; - - base = PISMO1_NAND_BASE; - size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif -} diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index ab327c8656..9d18aaac44 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; @@ -50,11 +52,11 @@ u32 get_cpu_type(void) /** * get_board_rev() - setup to pass kernel board revision information - * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + * returns: 0 for the ATAG REVISION tag value. */ -u32 get_board_rev(void) +u32 __weak get_board_rev(void) { - return BOARD_REV_ID; + return 0; } /** @@ -124,3 +126,59 @@ int print_cpuinfo(void) return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_AM33XX +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev) +{ + int sil_rev; + + sil_rev = readl(&cdev->deviceid) >> 28; + + if (sil_rev == 1) + /* PG 2.0, efuse may not be set. */ + return MPUPLL_M_800; + else if (sil_rev >= 2) { + /* Check what the efuse says our max speed is. */ + int efuse_arm_mpu_max_freq; + efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma); + switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) { + case AM335X_ZCZ_1000: + return MPUPLL_M_1000; + case AM335X_ZCZ_800: + return MPUPLL_M_800; + case AM335X_ZCZ_720: + return MPUPLL_M_720; + case AM335X_ZCZ_600: + case AM335X_ZCE_600: + return MPUPLL_M_600; + case AM335X_ZCZ_300: + case AM335X_ZCE_300: + return MPUPLL_M_300; + } + } + + /* PG 1.0 or otherwise unknown, use the PG1.0 max */ + return MPUPLL_M_720; +} + +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) +{ + /* For PG2.1 and later, we have one set of values. */ + if (sil_rev >= 2) { + switch (frequency) { + case MPUPLL_M_1000: + return TPS65910_OP_REG_SEL_1_3_2_5; + case MPUPLL_M_800: + return TPS65910_OP_REG_SEL_1_2_6; + case MPUPLL_M_720: + return TPS65910_OP_REG_SEL_1_2_0; + case MPUPLL_M_600: + case MPUPLL_M_300: + return TPS65910_OP_REG_SEL_1_1_3; + } + } + + /* Default to PG1.0/PG2.0 values. */ + return TPS65910_OP_REG_SEL_1_1_3; +} +#endif diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds index 9302856a95..07cf267878 100644 --- a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds @@ -22,6 +22,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/armv7/start.o (.text) *(.text*) } >.sram @@ -38,7 +39,11 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } >.sram .bss : { diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c new file mode 100644 index 0000000000..0588e2baef --- /dev/null +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int timer_init(void) +{ + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ; + + return 0; +} + +unsigned long long get_ticks(void) +{ + ulong nowl, nowu; + + asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (nowl), "=r" (nowu)); + + gd->arch.tbl = nowl; + gd->arch.tbu = nowu; + + return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; +} + + +ulong get_timer(ulong base) +{ + return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base; +} + +void __udelay(unsigned long usec) +{ + unsigned long long endtime; + + endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz, + 1000UL); + + endtime += get_ticks(); + + while (get_ticks() < endtime) + ; +} + +ulong get_tbclk(void) +{ + return gd->arch.timer_rate_hz; +} diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile b/arch/arm/cpu/armv7/armada-xp/Makefile new file mode 100644 index 0000000000..885dcee2e1 --- /dev/null +++ b/arch/arm/cpu/armv7/armada-xp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o diff --git a/arch/arm/cpu/armv7/armada-xp/cpu.c b/arch/arm/cpu/armv7/armada-xp/cpu.c new file mode 100644 index 0000000000..1cf70a9f5d --- /dev/null +++ b/arch/arm/cpu/armv7/armada-xp/cpu.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +static struct mbus_win windows[] = { + /* PCIE MEM address space */ + { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM }, + + /* PCIE IO address space */ + { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO }, + + /* SPI */ + { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, + CPU_ATTR_SPIFLASH }, + + /* NOR */ + { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, + CPU_ATTR_BOOTROM }, +}; + +void reset_cpu(unsigned long ignored) +{ + struct mvebu_system_registers *reg = + (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; + + writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); + writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); + while (1) + ; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; + u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; + + puts("SoC: "); + + switch (devid) { + case SOC_MV78460_ID: + puts("MV78460-"); + break; + default: + puts("Unknown-"); + break; + } + + switch (revid) { + case 1: + puts("A0\n"); + break; + case 2: + puts("B0\n"); + break; + default: + puts("??\n"); + break; + } + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +/* + * This function initialize Controller DRAM Fastpath windows. + * It takes the CS size information from the 0x1500 scratch registers + * and sets the correct windows sizes and base addresses accordingly. + * + * These values are set in the scratch registers by the Marvell + * DDR3 training code, which is executed by the BootROM before the + * main payload (U-Boot) is executed. This training code is currently + * only available in the Marvell U-Boot version. It needs to be + * ported to mainline U-Boot SPL at some point. + */ +static void update_sdram_window_sizes(void) +{ + u64 base = 0; + u32 size, temp; + int i; + + for (i = 0; i < SDRAM_MAX_CS; i++) { + size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; + if (size != 0) { + size |= ~(SDRAM_ADDR_MASK); + + /* Set Base Address */ + temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); + writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); + + /* + * Check if out of max window size and resize + * the window + */ + temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & + ~(SDRAM_ADDR_MASK)) | 1; + temp |= (size & SDRAM_ADDR_MASK); + writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); + + base += ((u64)size + 1); + } else { + /* + * Disable window if not used, otherwise this + * leads to overlapping enabled windows with + * pretty strange results + */ + clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); + } + } +} + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + /* Linux expects the internal registers to be at 0xf1000000 */ + writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); + + /* + * We need to call mvebu_mbus_probe() before calling + * update_sdram_window_sizes() as it disables all previously + * configured mbus windows and then configures them as + * required for U-Boot. Calling update_sdram_window_sizes() + * without this configuration will not work, as the internal + * registers can't be accessed reliably because of potenial + * double mapping. + * After updating the SDRAM access windows we need to call + * mvebu_mbus_probe() again, as this now correctly configures + * the SDRAM areas that are later used by the MVEBU drivers + * (e.g. USB, NETA). + */ + + /* + * First disable all windows + */ + mvebu_mbus_probe(NULL, 0); + + /* + * Now the SDRAM access windows can be reconfigured using + * the information in the SDRAM scratch pad registers + */ + update_sdram_window_sizes(); + + /* + * Finally the mbus windows can be configured with the + * updated SDRAM sizes + */ + mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +/* + * SOC specific misc init + */ +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + /* Nothing yet, perhaps we need something here later */ + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ + +#ifdef CONFIG_MVNETA +int cpu_eth_init(bd_t *bis) +{ + mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0); + mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1); + mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2); + mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3); + + return 0; +} +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile index 90b9bd68d7..f4f35a4bc1 100644 --- a/arch/arm/cpu/armv7/at91/Makefile +++ b/arch/arm/cpu/armv7/at91/Makefile @@ -8,29 +8,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-$(CONFIG_SAMA5D3) += sama5d3_devices.o -COBJS-y += clock.o -COBJS-y += cpu.o -COBJS-y += reset.o -COBJS-y += timer.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o +obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o +obj-y += clock.o +obj-y += cpu.o +obj-y += reset.o +obj-y += timer.o diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c index 1588e0c8ea..2cdddb2504 100644 --- a/arch/arm/cpu/armv7/at91/clock.c +++ b/arch/arm/cpu/armv7/at91/clock.c @@ -111,12 +111,57 @@ int at91_clock_init(unsigned long main_clock) return 0; } +void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) + ; +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_CSS_MASK | + AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); + tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK | + AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; +} + void at91_periph_clk_enable(int id) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 regval; + + if (id > AT91_PMC_PCR_PID_MASK) + return; + + regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id; + + writel(regval, &pmc->pcr); +} + +void at91_periph_clk_disable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 regval; + + if (id > AT91_PMC_PCR_PID_MASK) + return; + + regval = AT91_PMC_PCR_CMD_WRITE | id; - if (id > 31) - writel(1 << (id - 32), &pmc->pcer1); - else - writel(1 << id, &pmc->pcer); + writel(regval, &pmc->pcr); } diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk new file mode 100644 index 0000000000..db6030880f --- /dev/null +++ b/arch/arm/cpu/armv7/at91/config.mk @@ -0,0 +1,8 @@ +# +# Copyright (C) 2014, Andreas Bießmann +# +# SPDX-License-Identifier: GPL-2.0+ +# +ifndef CONFIG_SPL_BUILD +ALL-y += u-boot.img +endif diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c index 2fbf60d542..8d86f97e3d 100644 --- a/arch/arm/cpu/armv7/at91/cpu.c +++ b/arch/arm/cpu/armv7/at91/cpu.c @@ -61,6 +61,8 @@ int print_cpuinfo(void) void enable_caches(void) { + icache_enable(); + dcache_enable(); } unsigned int get_chip_id(void) diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c index 4a3fca56a1..78ecfc882a 100644 --- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c +++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c @@ -15,7 +15,7 @@ unsigned int has_emac() { - return cpu_is_sama5d31() || cpu_is_sama5d35(); + return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36(); } unsigned int has_gmac() @@ -42,6 +42,8 @@ char *get_cpu_name() return "SAMA5D34"; case ARCH_EXID_SAMA5D35: return "SAMA5D35"; + case ARCH_EXID_SAMA5D36: + return "SAMA5D36"; default: return "Unknown CPU type"; } @@ -82,7 +84,7 @@ void at91_seriald_hw_init(void) at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SYS); + at91_periph_clk_enable(ATMEL_ID_DBGU); } #if defined(CONFIG_ATMEL_SPI) @@ -144,6 +146,30 @@ void at91_macb_hw_init(void) /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_EMAC); } + +void at91_gmac_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ + + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ + + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC); +} #endif #ifdef CONFIG_LCD @@ -178,3 +204,15 @@ void at91_lcd_hw_init(void) at91_periph_clk_enable(ATMEL_ID_LCDC); } #endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable UPLL clock */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + /* Enable UDPHS clock */ + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c new file mode 100644 index 0000000000..7469825565 --- /dev/null +++ b/arch/arm/cpu/armv7/at91/sama5d4_devices.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2014 Atmel + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama5d4()) + switch (extension_id) { + case ARCH_EXID_SAMA5D41: + return "SAMA5D41"; + case ARCH_EXID_SAMA5D42: + return "SAMA5D42"; + case ARCH_EXID_SAMA5D43: + return "SAMA5D43"; + case ARCH_EXID_SAMA5D44: + return "SAMA5D44"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type"; +} + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable UPLL clock */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + /* Enable UDPHS clock */ + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c index 3808aedc79..19bf80ba7e 100644 --- a/arch/arm/cpu/armv7/at91/timer.c +++ b/arch/arm/cpu/armv7/at91/timer.c @@ -60,12 +60,13 @@ int timer_init(void) at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; /* Enable PITC Clock */ - at91_periph_clk_enable(ATMEL_ID_SYS); + at91_periph_clk_enable(ATMEL_ID_PIT); /* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); - gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; + gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; + gd->arch.tbu = 0; gd->arch.tbl = 0; diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile new file mode 100644 index 0000000000..f24aeb3826 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2013 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += clk-core.o +obj-y += clk-bcm281xx.o +obj-y += clk-sdio.o +obj-y += clk-bsc.o +obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o +obj-y += clk-usb-otg.o diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c new file mode 100644 index 0000000000..7e25255230 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -0,0 +1,573 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * + * bcm281xx-specific clock tables + * + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +#define CLOCK_1K 1000 +#define CLOCK_1M (CLOCK_1K * 1000) + +/* declare a reference clock */ +#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ +static struct refclk clk_name = { \ + .clk = { \ + .name = #clk_name, \ + .parent = clk_parent, \ + .rate = clk_rate, \ + .div = clk_div, \ + .ops = &ref_clk_ops, \ + }, \ +} + +/* + * Reference clocks + */ + +/* Declare a list of reference clocks */ +DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1); +DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1); +DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1); +DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0); +DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); +DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); +DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); +DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0); +DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); +DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); +DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); + +struct refclk_lkup { + struct refclk *procclk; + const char *name; +}; + +/* Lookup table for string to clk tranlation */ +#define MKSTR(x) {&x, #x} +static struct refclk_lkup refclk_str_tbl[] = { + MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m), + MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m), + MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m), + MKSTR(var_52m), MKSTR(var_13m), +}; + +int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]); + +/* convert ref clock string to clock structure pointer */ +struct refclk *refclk_str_to_clk(const char *name) +{ + int i; + struct refclk_lkup *tblp = refclk_str_tbl; + for (i = 0; i < refclk_entries; i++, tblp++) { + if (!(strcmp(name, tblp->name))) + return tblp->procclk; + } + return NULL; +} + +/* frequency tables indexed by freq_id */ +unsigned long master_axi_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M, + 156 * CLOCK_1M, + 208 * CLOCK_1M, + 312 * CLOCK_1M, + 312 * CLOCK_1M +}; + +unsigned long master_ahb_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M, + 104 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M +}; + +unsigned long slave_axi_freq_tbl[8] = { + 26 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M, + 104 * CLOCK_1M, + 156 * CLOCK_1M, + 156 * CLOCK_1M +}; + +unsigned long slave_apb_freq_tbl[8] = { + 26 * CLOCK_1M, + 26 * CLOCK_1M, + 39 * CLOCK_1M, + 52 * CLOCK_1M, + 52 * CLOCK_1M, + 78 * CLOCK_1M +}; + +unsigned long esub_freq_tbl[8] = { + 78 * CLOCK_1M, + 156 * CLOCK_1M, + 156 * CLOCK_1M, + 156 * CLOCK_1M, + 208 * CLOCK_1M, + 208 * CLOCK_1M, + 208 * CLOCK_1M +}; + +static struct bus_clk_data bsc1_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1), +}; + +static struct bus_clk_data bsc2_apb_data = { + .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1), +}; + +static struct bus_clk_data bsc3_apb_data = { + .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1), +}; + +/* * Master CCU clocks */ +static struct peri_clk_data sdio1_data = { + .gate = HW_SW_GATE(0x0358, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a28, 0, 3), + .div = DIVIDER(0x0a28, 4, 14), + .trig = TRIGGER(0x0afc, 9), +}; + +static struct peri_clk_data sdio2_data = { + .gate = HW_SW_GATE(0x035c, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a2c, 0, 3), + .div = DIVIDER(0x0a2c, 4, 14), + .trig = TRIGGER(0x0afc, 10), +}; + +static struct peri_clk_data sdio3_data = { + .gate = HW_SW_GATE(0x0364, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a34, 0, 3), + .div = DIVIDER(0x0a34, 4, 14), + .trig = TRIGGER(0x0afc, 12), +}; + +static struct peri_clk_data sdio4_data = { + .gate = HW_SW_GATE(0x0360, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_52m", + "ref_52m", + "var_96m", + "ref_96m"), + .sel = SELECTOR(0x0a30, 0, 3), + .div = DIVIDER(0x0a30, 4, 14), + .trig = TRIGGER(0x0afc, 11), +}; + +static struct peri_clk_data sdio1_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0358, 20, 4), +}; + +static struct peri_clk_data sdio2_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x035c, 20, 4), +}; + +static struct peri_clk_data sdio3_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0364, 20, 4), +}; + +static struct peri_clk_data sdio4_sleep_data = { + .clocks = CLOCKS("ref_32k"), + .gate = SW_ONLY_GATE(0x0360, 20, 4), +}; + +static struct bus_clk_data usb_otg_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1), +}; + +static struct bus_clk_data sdio1_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1), +}; + +static struct bus_clk_data sdio2_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1), +}; + +static struct bus_clk_data sdio3_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1), +}; + +static struct bus_clk_data sdio4_ahb_data = { + .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1), +}; + +/* * Slave CCU clocks */ +static struct peri_clk_data bsc1_data = { + .gate = HW_SW_GATE(0x0458, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a64, 0, 3), + .trig = TRIGGER(0x0afc, 23), +}; + +static struct peri_clk_data bsc2_data = { + .gate = HW_SW_GATE(0x045c, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a68, 0, 3), + .trig = TRIGGER(0x0afc, 24), +}; + +static struct peri_clk_data bsc3_data = { + .gate = HW_SW_GATE(0x0484, 18, 2, 3), + .clocks = CLOCKS("ref_crystal", + "var_104m", + "ref_104m", + "var_13m", + "ref_13m"), + .sel = SELECTOR(0x0a84, 0, 3), + .trig = TRIGGER(0x0b00, 2), +}; + +/* + * CCU clocks + */ + +static struct ccu_clock kpm_ccu_clk = { + .clk = { + .name = "kpm_ccu_clk", + .ops = &ccu_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .num_policy_masks = 1, + .policy_freq_offset = 0x00000008, + .freq_bit_shift = 8, + .policy_ctl_offset = 0x0000000c, + .policy0_mask_offset = 0x00000010, + .policy1_mask_offset = 0x00000014, + .policy2_mask_offset = 0x00000018, + .policy3_mask_offset = 0x0000001c, + .lvm_en_offset = 0x00000034, + .freq_id = 2, + .freq_tbl = master_axi_freq_tbl, +}; + +static struct ccu_clock kps_ccu_clk = { + .clk = { + .name = "kps_ccu_clk", + .ops = &ccu_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .num_policy_masks = 2, + .policy_freq_offset = 0x00000008, + .freq_bit_shift = 8, + .policy_ctl_offset = 0x0000000c, + .policy0_mask_offset = 0x00000010, + .policy1_mask_offset = 0x00000014, + .policy2_mask_offset = 0x00000018, + .policy3_mask_offset = 0x0000001c, + .policy0_mask2_offset = 0x00000048, + .policy1_mask2_offset = 0x0000004c, + .policy2_mask2_offset = 0x00000050, + .policy3_mask2_offset = 0x00000054, + .lvm_en_offset = 0x00000034, + .freq_id = 2, + .freq_tbl = slave_axi_freq_tbl, +}; + +#ifdef CONFIG_BCM_SF2_ETH +static struct ccu_clock esub_ccu_clk = { + .clk = { + .name = "esub_ccu_clk", + .ops = &ccu_clk_ops, + .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR, + }, + .num_policy_masks = 1, + .policy_freq_offset = 0x00000008, + .freq_bit_shift = 8, + .policy_ctl_offset = 0x0000000c, + .policy0_mask_offset = 0x00000010, + .policy1_mask_offset = 0x00000014, + .policy2_mask_offset = 0x00000018, + .policy3_mask_offset = 0x0000001c, + .lvm_en_offset = 0x00000034, + .freq_id = 2, + .freq_tbl = esub_freq_tbl, +}; +#endif + +/* + * Bus clocks + */ + +/* KPM bus clocks */ +static struct bus_clock usb_otg_ahb_clk = { + .clk = { + .name = "usb_otg_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &usb_otg_ahb_data, +}; + +static struct bus_clock sdio1_ahb_clk = { + .clk = { + .name = "sdio1_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio1_ahb_data, +}; + +static struct bus_clock sdio2_ahb_clk = { + .clk = { + .name = "sdio2_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio2_ahb_data, +}; + +static struct bus_clock sdio3_ahb_clk = { + .clk = { + .name = "sdio3_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio3_ahb_data, +}; + +static struct bus_clock sdio4_ahb_clk = { + .clk = { + .name = "sdio4_ahb_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .freq_tbl = master_ahb_freq_tbl, + .data = &sdio4_ahb_data, +}; + +static struct bus_clock bsc1_apb_clk = { + .clk = { + .name = "bsc1_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc1_apb_data, +}; + +static struct bus_clock bsc2_apb_clk = { + .clk = { + .name = "bsc2_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc2_apb_data, +}; + +static struct bus_clock bsc3_apb_clk = { + .clk = { + .name = "bsc3_apb_clk", + .parent = &kps_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .freq_tbl = slave_apb_freq_tbl, + .data = &bsc3_apb_data, +}; + +/* KPM peripheral */ +static struct peri_clock sdio1_clk = { + .clk = { + .name = "sdio1_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio1_data, +}; + +static struct peri_clock sdio2_clk = { + .clk = { + .name = "sdio2_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio2_data, +}; + +static struct peri_clock sdio3_clk = { + .clk = { + .name = "sdio3_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio3_data, +}; + +static struct peri_clock sdio4_clk = { + .clk = { + .name = "sdio4_clk", + .parent = &ref_52m.clk, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio4_data, +}; + +static struct peri_clock sdio1_sleep_clk = { + .clk = { + .name = "sdio1_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio1_sleep_data, +}; + +static struct peri_clock sdio2_sleep_clk = { + .clk = { + .name = "sdio2_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio2_sleep_data, +}; + +static struct peri_clock sdio3_sleep_clk = { + .clk = { + .name = "sdio3_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio3_sleep_data, +}; + +static struct peri_clock sdio4_sleep_clk = { + .clk = { + .name = "sdio4_sleep_clk", + .parent = &kpm_ccu_clk.clk, + .ops = &bus_clk_ops, + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, + }, + .data = &sdio4_sleep_data, +}; + +/* KPS peripheral clock */ +static struct peri_clock bsc1_clk = { + .clk = { + .name = "bsc1_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc1_data, +}; + +static struct peri_clock bsc2_clk = { + .clk = { + .name = "bsc2_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc2_data, +}; + +static struct peri_clock bsc3_clk = { + .clk = { + .name = "bsc3_clk", + .parent = &ref_13m.clk, + .rate = 13 * CLOCK_1M, + .div = 1, + .ops = &peri_clk_ops, + .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, + }, + .data = &bsc3_data, +}; + +/* public table for registering clocks */ +struct clk_lookup arch_clk_tbl[] = { + /* Peripheral clocks */ + CLK_LK(sdio1), + CLK_LK(sdio2), + CLK_LK(sdio3), + CLK_LK(sdio4), + CLK_LK(sdio1_sleep), + CLK_LK(sdio2_sleep), + CLK_LK(sdio3_sleep), + CLK_LK(sdio4_sleep), + CLK_LK(bsc1), + CLK_LK(bsc2), + CLK_LK(bsc3), + /* Bus clocks */ + CLK_LK(usb_otg_ahb), + CLK_LK(sdio1_ahb), + CLK_LK(sdio2_ahb), + CLK_LK(sdio3_ahb), + CLK_LK(sdio4_ahb), + CLK_LK(bsc1_apb), + CLK_LK(bsc2_apb), + CLK_LK(bsc3_apb), +#ifdef CONFIG_BCM_SF2_ETH + CLK_LK(esub_ccu), +#endif +}; + +/* public array size */ +unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl); diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c new file mode 100644 index 0000000000..ba55d0aeb1 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c @@ -0,0 +1,52 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +/* Enable appropriate clocks for a BSC/I2C port */ +int clk_bsc_enable(void *base) +{ + int ret; + char *bscstr, *apbstr; + + switch ((u32) base) { + case PMU_BSC_BASE_ADDR: + /* PMU clock is always enabled */ + return 0; + case BSC1_BASE_ADDR: + bscstr = "bsc1_clk"; + apbstr = "bsc1_apb_clk"; + break; + case BSC2_BASE_ADDR: + bscstr = "bsc2_clk"; + apbstr = "bsc2_apb_clk"; + break; + case BSC3_BASE_ADDR: + bscstr = "bsc3_clk"; + apbstr = "bsc3_apb_clk"; + break; + default: + printf("%s: base 0x%p not found\n", __func__, base); + return -EINVAL; + } + + /* Note that the bus clock must be enabled first */ + + ret = clk_get_and_enable(apbstr); + if (ret) + return ret; + + ret = clk_get_and_enable(bscstr); + if (ret) + return ret; + + return 0; +} diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c new file mode 100644 index 0000000000..d4425835a1 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -0,0 +1,513 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * + * bcm281xx architecture clock framework + * + */ + +#include +#include +#include +#include +#include +#include +#include "clk-core.h" + +#define CLK_WR_ACCESS_PASSWORD 0x00a5a501 +#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ +#define POLICY_CTL_GO 1 /* Load and refresh policy masks */ +#define POLICY_CTL_GO_ATL 4 /* Active Load */ + +/* Helper function */ +int clk_get_and_enable(char *clkstr) +{ + int ret = 0; + struct clk *c; + + debug("%s: %s\n", __func__, clkstr); + + c = clk_get(clkstr); + if (c) { + ret = clk_enable(c); + if (ret) + return ret; + } else { + printf("%s: Couldn't find %s\n", __func__, clkstr); + return -EINVAL; + } + return ret; +} + +/* + * Poll a register in a CCU's address space, returning when the + * specified bit in that register's value is set (or clear). Delay + * a microsecond after each read of the register. Returns true if + * successful, or false if we gave up trying. + * + * Caller must ensure the CCU lock is held. + */ +#define CLK_GATE_DELAY_USEC 2000 +static inline int wait_bit(void *base, u32 offset, u32 bit, bool want) +{ + unsigned int tries; + u32 bit_mask = 1 << bit; + + for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) { + u32 val; + bool bit_val; + + val = readl(base + offset); + bit_val = (val & bit_mask) ? 1 : 0; + if (bit_val == want) + return 0; /* success */ + udelay(1); + } + + debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n", + __func__, base + offset, bit, want); + + return -ETIMEDOUT; +} + +/* Enable a peripheral clock */ +static int peri_clk_enable(struct clk *c, int enable) +{ + int ret = 0; + u32 reg; + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + struct bcm_clk_gate *gate = &cd->gate; + void *base = (void *)c->ccu_clk_mgr_base; + + + debug("%s: %s\n", __func__, c->name); + + clk_get_rate(c); /* Make sure rate and sel are filled in */ + + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + if (enable) { + debug("%s %s set rate %lu div %lu sel %d parent %lu\n", + __func__, c->name, c->rate, c->div, c->sel, + c->parent->rate); + + /* + * clkgate - only software controllable gates are + * supported by u-boot which includes all clocks + * that matter. This avoids bringing in a lot of extra + * complexity as done in the kernel framework. + */ + if (gate_exists(gate)) { + reg = readl(base + cd->gate.offset); + reg |= (1 << cd->gate.en_bit); + writel(reg, base + cd->gate.offset); + } + + /* div and pll select */ + if (divider_exists(&cd->div)) { + reg = readl(base + cd->div.offset); + bitfield_replace(reg, cd->div.shift, cd->div.width, + c->div - 1); + writel(reg, base + cd->div.offset); + } + + /* frequency selector */ + if (selector_exists(&cd->sel)) { + reg = readl(base + cd->sel.offset); + bitfield_replace(reg, cd->sel.shift, cd->sel.width, + c->sel); + writel(reg, base + cd->sel.offset); + } + + /* trigger */ + if (trigger_exists(&cd->trig)) { + writel((1 << cd->trig.bit), base + cd->trig.offset); + + /* wait for trigger status bit to go to 0 */ + ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0); + if (ret) + return ret; + } + + /* wait for running (status_bit = 1) */ + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); + if (ret) + return ret; + } else { + debug("%s disable clock %s\n", __func__, c->name); + + /* clkgate */ + reg = readl(base + cd->gate.offset); + reg &= ~(1 << cd->gate.en_bit); + writel(reg, base + cd->gate.offset); + + /* wait for stop (status_bit = 0) */ + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); + } + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Set the rate of a peripheral clock */ +static int peri_clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret = 0; + int i; + unsigned long diff; + unsigned long new_rate = 0, div = 1; + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + const char **clock; + + debug("%s: %s\n", __func__, c->name); + diff = rate; + + i = 0; + for (clock = cd->clocks; *clock; clock++, i++) { + struct refclk *ref = refclk_str_to_clk(*clock); + if (!ref) { + printf("%s: Lookup of %s failed\n", __func__, *clock); + return -EINVAL; + } + + /* round to the new rate */ + div = ref->clk.rate / rate; + if (div == 0) + div = 1; + + new_rate = ref->clk.rate / div; + + /* get the min diff */ + if (abs(new_rate - rate) < diff) { + diff = abs(new_rate - rate); + c->sel = i; + c->parent = &ref->clk; + c->rate = new_rate; + c->div = div; + } + } + + debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__, + c->name, c->rate, c->div, c->sel, c->parent->rate); + return ret; +} + +/* Get the rate of a peripheral clock */ +static unsigned long peri_clk_get_rate(struct clk *c) +{ + struct peri_clock *peri_clk = to_peri_clk(c); + struct peri_clk_data *cd = peri_clk->data; + void *base = (void *)c->ccu_clk_mgr_base; + int div = 1; + const char **clock; + struct refclk *ref; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + if (selector_exists(&cd->sel)) { + reg = readl(base + cd->sel.offset); + c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); + } else { + /* + * For peri clocks that don't have a selector, the single + * reference clock will always exist at index 0. + */ + c->sel = 0; + } + + if (divider_exists(&cd->div)) { + reg = readl(base + cd->div.offset); + div = bitfield_extract(reg, cd->div.shift, cd->div.width); + div += 1; + } + + clock = cd->clocks; + ref = refclk_str_to_clk(clock[c->sel]); + if (!ref) { + printf("%s: Can't lookup %s\n", __func__, clock[c->sel]); + return 0; + } + + c->parent = &ref->clk; + c->div = div; + c->rate = c->parent->rate / c->div; + debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__, + c->parent->rate, div, c->sel, c->rate); + + return c->rate; +} + +/* Peripheral clock operations */ +struct clk_ops peri_clk_ops = { + .enable = peri_clk_enable, + .set_rate = peri_clk_set_rate, + .get_rate = peri_clk_get_rate, +}; + +/* Enable a CCU clock */ +static int ccu_clk_enable(struct clk *c, int enable) +{ + struct ccu_clock *ccu_clk = to_ccu_clk(c); + void *base = (void *)c->ccu_clk_mgr_base; + int ret = 0; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + if (!enable) + return -EINVAL; /* CCU clock cannot shutdown */ + + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + /* config enable for policy engine */ + writel(1, base + ccu_clk->lvm_en_offset); + + /* wait for bit to go to 0 */ + ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0); + if (ret) + return ret; + + /* freq ID */ + if (!ccu_clk->freq_bit_shift) + ccu_clk->freq_bit_shift = 8; + + /* Set frequency id for each of the 4 policies */ + reg = ccu_clk->freq_id | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) | + (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3)); + writel(reg, base + ccu_clk->policy_freq_offset); + + /* enable all clock mask */ + writel(0x7fffffff, base + ccu_clk->policy0_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy1_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy2_mask_offset); + writel(0x7fffffff, base + ccu_clk->policy3_mask_offset); + + if (ccu_clk->num_policy_masks == 2) { + writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset); + writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset); + } + + /* start policy engine */ + reg = readl(base + ccu_clk->policy_ctl_offset); + reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL); + writel(reg, base + ccu_clk->policy_ctl_offset); + + /* wait till started */ + ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0); + if (ret) + return ret; + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Get the CCU clock rate */ +static unsigned long ccu_clk_get_rate(struct clk *c) +{ + struct ccu_clock *ccu_clk = to_ccu_clk(c); + debug("%s: %s\n", __func__, c->name); + c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id]; + return c->rate; +} + +/* CCU clock operations */ +struct clk_ops ccu_clk_ops = { + .enable = ccu_clk_enable, + .get_rate = ccu_clk_get_rate, +}; + +/* Enable a bus clock */ +static int bus_clk_enable(struct clk *c, int enable) +{ + struct bus_clock *bus_clk = to_bus_clk(c); + struct bus_clk_data *cd = bus_clk->data; + void *base = (void *)c->ccu_clk_mgr_base; + int ret = 0; + u32 reg; + + debug("%s: %s\n", __func__, c->name); + /* enable access */ + writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); + + /* enable gating */ + reg = readl(base + cd->gate.offset); + if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) + debug("%s already %s\n", c->name, + enable ? "enabled" : "disabled"); + else { + int want = (enable) ? 1 : 0; + reg |= (1 << cd->gate.hw_sw_sel_bit); + + if (enable) + reg |= (1 << cd->gate.en_bit); + else + reg &= ~(1 << cd->gate.en_bit); + + writel(reg, base + cd->gate.offset); + ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, + want); + if (ret) + return ret; + } + + /* disable access */ + writel(0, base + WR_ACCESS_OFFSET); + + return ret; +} + +/* Get the rate of a bus clock */ +static unsigned long bus_clk_get_rate(struct clk *c) +{ + struct bus_clock *bus_clk = to_bus_clk(c); + struct ccu_clock *ccu_clk; + + debug("%s: %s\n", __func__, c->name); + ccu_clk = to_ccu_clk(c->parent); + + c->rate = bus_clk->freq_tbl[ccu_clk->freq_id]; + c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate; + return c->rate; +} + +/* Bus clock operations */ +struct clk_ops bus_clk_ops = { + .enable = bus_clk_enable, + .get_rate = bus_clk_get_rate, +}; + +/* Enable a reference clock */ +static int ref_clk_enable(struct clk *c, int enable) +{ + debug("%s: %s\n", __func__, c->name); + return 0; +} + +/* Reference clock operations */ +struct clk_ops ref_clk_ops = { + .enable = ref_clk_enable, +}; + +/* + * clk.h implementation follows + */ + +/* Initialize the clock framework */ +int clk_init(void) +{ + debug("%s:\n", __func__); + return 0; +} + +/* Get a clock handle, give a name string */ +struct clk *clk_get(const char *con_id) +{ + int i; + struct clk_lookup *clk_tblp; + + debug("%s: %s\n", __func__, con_id); + + clk_tblp = arch_clk_tbl; + for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) { + if (clk_tblp->con_id) { + if (!con_id || strcmp(clk_tblp->con_id, con_id)) + continue; + return clk_tblp->clk; + } + } + return NULL; +} + +/* Enable a clock */ +int clk_enable(struct clk *c) +{ + int ret = 0; + + debug("%s: %s\n", __func__, c->name); + if (!c->ops || !c->ops->enable) + return -1; + + /* enable parent clock first */ + if (c->parent) + ret = clk_enable(c->parent); + + if (ret) + return ret; + + if (!c->use_cnt) { + c->use_cnt++; + ret = c->ops->enable(c, 1); + } + + return ret; +} + +/* Disable a clock */ +void clk_disable(struct clk *c) +{ + debug("%s: %s\n", __func__, c->name); + if (!c->ops || !c->ops->enable) + return; + + if (c->use_cnt) { + c->use_cnt--; + c->ops->enable(c, 0); + } + + /* disable parent */ + if (c->parent) + clk_disable(c->parent); +} + +/* Get the clock rate */ +unsigned long clk_get_rate(struct clk *c) +{ + unsigned long rate; + + debug("%s: %s\n", __func__, c->name); + if (!c || !c->ops || !c->ops->get_rate) + return 0; + + rate = c->ops->get_rate(c); + debug("%s: rate = %ld\n", __func__, rate); + return rate; +} + +/* Set the clock rate */ +int clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret; + + debug("%s: %s rate=%ld\n", __func__, c->name, rate); + if (!c || !c->ops || !c->ops->set_rate) + return -EINVAL; + + if (c->use_cnt) + return -EINVAL; + + ret = c->ops->set_rate(c, rate); + + return ret; +} + +/* Not required for this arch */ +/* +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); +struct clk *clk_get_parent(struct clk *clk); +*/ diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/arch/arm/cpu/armv7/bcm281xx/clk-core.h new file mode 100644 index 0000000000..4a694d7fe7 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.h @@ -0,0 +1,491 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifdef CONFIG_CLK_DEBUG +#undef writel +#undef readl +static inline void writel(u32 val, void *addr) +{ + printf("Write [0x%p] = 0x%08x\n", addr, val); + *(u32 *)addr = val; +} + +static inline u32 readl(void *addr) +{ + u32 val = *(u32 *)addr; + printf("Read [0x%p] = 0x%08x\n", addr, val); + return val; +} +#endif + +struct clk; + +struct clk_lookup { + const char *dev_id; + const char *con_id; + struct clk *clk; +}; + +extern struct clk_lookup arch_clk_tbl[]; +extern unsigned int arch_clk_tbl_array_size; + +/** + * struct clk_ops - standard clock operations + * @enable: enable/disable clock, see clk_enable() and clk_disable() + * @set_rate: set the clock rate, see clk_set_rate(). + * @get_rate: get the clock rate, see clk_get_rate(). + * @round_rate: round a given clock rate, see clk_round_rate(). + * @set_parent: set the clock's parent, see clk_set_parent(). + * + * Group the common clock implementations together so that we + * don't have to keep setting the same fiels again. We leave + * enable in struct clk. + * + */ +struct clk_ops { + int (*enable) (struct clk *c, int enable); + int (*set_rate) (struct clk *c, unsigned long rate); + unsigned long (*get_rate) (struct clk *c); + unsigned long (*round_rate) (struct clk *c, unsigned long rate); + int (*set_parent) (struct clk *c, struct clk *parent); +}; + +struct clk { + struct clk *parent; + const char *name; + int use_cnt; + unsigned long rate; /* in HZ */ + + /* programmable divider. 0 means fixed ratio to parent clock */ + unsigned long div; + + struct clk_src *src; + struct clk_ops *ops; + + unsigned long ccu_clk_mgr_base; + int sel; +}; + +struct refclk *refclk_str_to_clk(const char *name); + +/* The common clock framework uses u8 to represent a parent index */ +#define PARENT_COUNT_MAX ((u32)U8_MAX) + +#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ +#define BAD_CLK_NAME ((const char *)-1) + +#define BAD_SCALED_DIV_VALUE U64_MAX + +/* + * Utility macros for object flag management. If possible, flags + * should be defined such that 0 is the desired default value. + */ +#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag +#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) +#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) +#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) +#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) + +/* Clock field state tests */ + +#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) +#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) +#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) +#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) +#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) +#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) + +#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) + +#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) +#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) +#define divider_has_fraction(div) (!divider_is_fixed(div) && \ + (div)->frac_width > 0) + +#define selector_exists(sel) ((sel)->width != 0) +#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) + +/* Clock type, used to tell common block what it's part of */ +enum bcm_clk_type { + bcm_clk_none, /* undefined clock type */ + bcm_clk_bus, + bcm_clk_core, + bcm_clk_peri +}; + +/* + * Gating control and status is managed by a 32-bit gate register. + * + * There are several types of gating available: + * - (no gate) + * A clock with no gate is assumed to be always enabled. + * - hardware-only gating (auto-gating) + * Enabling or disabling clocks with this type of gate is + * managed automatically by the hardware. Such clocks can be + * considered by the software to be enabled. The current status + * of auto-gated clocks can be read from the gate status bit. + * - software-only gating + * Auto-gating is not available for this type of clock. + * Instead, software manages whether it's enabled by setting or + * clearing the enable bit. The current gate status of a gate + * under software control can be read from the gate status bit. + * To ensure a change to the gating status is complete, the + * status bit can be polled to verify that the gate has entered + * the desired state. + * - selectable hardware or software gating + * Gating for this type of clock can be configured to be either + * under software or hardware control. Which type is in use is + * determined by the hw_sw_sel bit of the gate register. + */ +struct bcm_clk_gate { + u32 offset; /* gate register offset */ + u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ + u32 en_bit; /* 0: disable; 1: enable */ + u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ + u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ +}; + +/* + * Gate flags: + * HW means this gate can be auto-gated + * SW means the state of this gate can be software controlled + * NO_DISABLE means this gate is (only) enabled if under software control + * SW_MANAGED means the status of this gate is under software control + * ENABLED means this software-managed gate is *supposed* to be enabled + */ +#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ +#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ +#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ +#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ +#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ +#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ + +/* + * Gate initialization macros. + * + * Any gate initially under software control will be enabled. + */ + +/* A hardware/software gate initially under software control */ +#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ + FLAG(GATE, EXISTS), \ + } + +/* A hardware/software gate initially under hardware control */ +#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, EXISTS), \ + } + +/* A hardware-or-enabled gate (enabled if not under hardware control) */ +#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .hw_sw_sel_bit = (_hw_sw_sel_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ + FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ + } + +/* A software-only gate */ +#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .en_bit = (_en_bit), \ + .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ + FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ + } + +/* A hardware-only gate */ +#define HW_ONLY_GATE(_offset, _status_bit) \ + { \ + .offset = (_offset), \ + .status_bit = (_status_bit), \ + .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ + } + +/* + * Each clock can have zero, one, or two dividers which change the + * output rate of the clock. Each divider can be either fixed or + * variable. If there are two dividers, they are the "pre-divider" + * and the "regular" or "downstream" divider. If there is only one, + * there is no pre-divider. + * + * A fixed divider is any non-zero (positive) value, and it + * indicates how the input rate is affected by the divider. + * + * The value of a variable divider is maintained in a sub-field of a + * 32-bit divider register. The position of the field in the + * register is defined by its offset and width. The value recorded + * in this field is always 1 less than the value it represents. + * + * In addition, a variable divider can indicate that some subset + * of its bits represent a "fractional" part of the divider. Such + * bits comprise the low-order portion of the divider field, and can + * be viewed as representing the portion of the divider that lies to + * the right of the decimal point. Most variable dividers have zero + * fractional bits. Variable dividers with non-zero fraction width + * still record a value 1 less than the value they represent; the + * added 1 does *not* affect the low-order bit in this case, it + * affects the bits above the fractional part only. (Often in this + * code a divider field value is distinguished from the value it + * represents by referring to the latter as a "divisor".) + * + * In order to avoid dealing with fractions, divider arithmetic is + * performed using "scaled" values. A scaled value is one that's + * been left-shifted by the fractional width of a divider. Dividing + * a scaled value by a scaled divisor produces the desired quotient + * without loss of precision and without any other special handling + * for fractions. + * + * The recorded value of a variable divider can be modified. To + * modify either divider (or both), a clock must be enabled (i.e., + * using its gate). In addition, a trigger register (described + * below) must be used to commit the change, and polled to verify + * the change is complete. + */ +struct bcm_clk_div { + union { + struct { /* variable divider */ + u32 offset; /* divider register offset */ + u32 shift; /* field shift */ + u32 width; /* field width */ + u32 frac_width; /* field fraction width */ + + u64 scaled_div; /* scaled divider value */ + }; + u32 fixed; /* non-zero fixed divider value */ + }; + u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ +}; + +/* + * Divider flags: + * EXISTS means this divider exists + * FIXED means it is a fixed-rate divider + */ +#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ +#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ + +/* Divider initialization macros */ + +/* A fixed (non-zero) divider */ +#define FIXED_DIVIDER(_value) \ + { \ + .fixed = (_value), \ + .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ + } + +/* A divider with an integral divisor */ +#define DIVIDER(_offset, _shift, _width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .scaled_div = BAD_SCALED_DIV_VALUE, \ + .flags = FLAG(DIV, EXISTS), \ + } + +/* A divider whose divisor has an integer and fractional part */ +#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .frac_width = (_frac_width), \ + .scaled_div = BAD_SCALED_DIV_VALUE, \ + .flags = FLAG(DIV, EXISTS), \ + } + +/* + * Clocks may have multiple "parent" clocks. If there is more than + * one, a selector must be specified to define which of the parent + * clocks is currently in use. The selected clock is indicated in a + * sub-field of a 32-bit selector register. The range of + * representable selector values typically exceeds the number of + * available parent clocks. Occasionally the reset value of a + * selector field is explicitly set to a (specific) value that does + * not correspond to a defined input clock. + * + * We register all known parent clocks with the common clock code + * using a packed array (i.e., no empty slots) of (parent) clock + * names, and refer to them later using indexes into that array. + * We maintain an array of selector values indexed by common clock + * index values in order to map between these common clock indexes + * and the selector values used by the hardware. + * + * Like dividers, a selector can be modified, but to do so a clock + * must be enabled, and a trigger must be used to commit the change. + */ +struct bcm_clk_sel { + u32 offset; /* selector register offset */ + u32 shift; /* field shift */ + u32 width; /* field width */ + + u32 parent_count; /* number of entries in parent_sel[] */ + u32 *parent_sel; /* array of parent selector values */ + u8 clk_index; /* current selected index in parent_sel[] */ +}; + +/* Selector initialization macro */ +#define SELECTOR(_offset, _shift, _width) \ + { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + .clk_index = BAD_CLK_INDEX, \ + } + +/* + * Making changes to a variable divider or a selector for a clock + * requires the use of a trigger. A trigger is defined by a single + * bit within a register. To signal a change, a 1 is written into + * that bit. To determine when the change has been completed, that + * trigger bit is polled; the read value will be 1 while the change + * is in progress, and 0 when it is complete. + * + * Occasionally a clock will have more than one trigger. In this + * case, the "pre-trigger" will be used when changing a clock's + * selector and/or its pre-divider. + */ +struct bcm_clk_trig { + u32 offset; /* trigger register offset */ + u32 bit; /* trigger bit */ + u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ +}; + +/* + * Trigger flags: + * EXISTS means this trigger exists + */ +#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ + +/* Trigger initialization macro */ +#define TRIGGER(_offset, _bit) \ + { \ + .offset = (_offset), \ + .bit = (_bit), \ + .flags = FLAG(TRIG, EXISTS), \ + } + +struct bus_clk_data { + struct bcm_clk_gate gate; +}; + +struct core_clk_data { + struct bcm_clk_gate gate; +}; + +struct peri_clk_data { + struct bcm_clk_gate gate; + struct bcm_clk_trig pre_trig; + struct bcm_clk_div pre_div; + struct bcm_clk_trig trig; + struct bcm_clk_div div; + struct bcm_clk_sel sel; + const char *clocks[]; /* must be last; use CLOCKS() to declare */ +}; +#define CLOCKS(...) { __VA_ARGS__, NULL, } +#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ + +struct refclk { + struct clk clk; +}; + +struct peri_clock { + struct clk clk; + struct peri_clk_data *data; +}; + +struct ccu_clock { + struct clk clk; + + int num_policy_masks; + unsigned long policy_freq_offset; + int freq_bit_shift; /* 8 for most CCUs */ + unsigned long policy_ctl_offset; + unsigned long policy0_mask_offset; + unsigned long policy1_mask_offset; + unsigned long policy2_mask_offset; + unsigned long policy3_mask_offset; + unsigned long policy0_mask2_offset; + unsigned long policy1_mask2_offset; + unsigned long policy2_mask2_offset; + unsigned long policy3_mask2_offset; + unsigned long lvm_en_offset; + + int freq_id; + unsigned long *freq_tbl; +}; + +struct bus_clock { + struct clk clk; + struct bus_clk_data *data; + unsigned long *freq_tbl; +}; + +struct ref_clock { + struct clk clk; +}; + +static inline int is_same_clock(struct clk *a, struct clk *b) +{ + return (a == b); +} + +#define to_clk(p) (&((p)->clk)) +#define name_to_clk(name) (&((name##_clk).clk)) +/* declare a struct clk_lookup */ +#define CLK_LK(name) \ +{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),} + +static inline struct refclk *to_refclk(struct clk *clock) +{ + return container_of(clock, struct refclk, clk); +} + +static inline struct peri_clock *to_peri_clk(struct clk *clock) +{ + return container_of(clock, struct peri_clock, clk); +} + +static inline struct ccu_clock *to_ccu_clk(struct clk *clock) +{ + return container_of(clock, struct ccu_clock, clk); +} + +static inline struct bus_clock *to_bus_clk(struct clk *clock) +{ + return container_of(clock, struct bus_clock, clk); +} + +static inline struct ref_clock *to_ref_clk(struct clk *clock) +{ + return container_of(clock, struct ref_clock, clk); +} + +extern struct clk_ops peri_clk_ops; +extern struct clk_ops ccu_clk_ops; +extern struct clk_ops bus_clk_ops; +extern struct clk_ops ref_clk_ops; + +extern int clk_get_and_enable(char *clkstr); diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c new file mode 100644 index 0000000000..b0b92b9df7 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c @@ -0,0 +1,143 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR +#define WR_ACCESS_PASSWORD 0xA5A500 + +#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00) + +#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58) +#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000 +#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001 + +#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38) +#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001 + +#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04) +#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300 +#define ESW_SYS_DIV_DIV_MASK 0x0000001C +#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100 +#define ESW_SYS_DIV_DIV_SELECT 0x4 +#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001 + +#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04) +#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C +#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040 +#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0 +#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001 + +#define PLL_MAX_RETRY 100 + +/* Enable appropriate clocks for Ethernet */ +int clk_eth_enable(void) +{ + int rc = -1; + int retry_count = 0; + rc = clk_get_and_enable("esub_ccu_clk"); + + /* Enable Access to CCU registers */ + writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR); + + writel(readl(PLLE_POST_RESETB_ADDR) & + ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, + PLLE_POST_RESETB_ADDR); + + /* Take PLL out of reset and put into normal mode */ + writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, + PLLE_RESETB_ADDR); + + /* Wait for PLL lock */ + rc = -1; + while (retry_count < PLL_MAX_RETRY) { + udelay(100); + if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { + rc = 0; + break; + } + retry_count++; + } + + if (rc == -1) { + printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n", + __func__); + return -1; + } + + writel(readl(PLLE_POST_RESETB_ADDR) | + PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, + PLLE_POST_RESETB_ADDR); + + /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ + writel((readl(ESW_SYS_DIV_ADDR) & + ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) | + ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT, + ESW_SYS_DIV_ADDR); + + writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, + ESW_SYS_DIV_ADDR); + + /* Wait for trigger complete */ + rc = -1; + retry_count = 0; + while (retry_count < PLL_MAX_RETRY) { + udelay(100); + if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { + rc = 0; + break; + } + retry_count++; + } + + if (rc == -1) { + printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n", + __func__); + return -1; + } + + /* switch Esub AXI clock to 208MHz */ + writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & + ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK | + ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK | + ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) | + ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT | + ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK, + ESUB_AXI_DIV_DEBUG_ADDR); + + writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | + ESUB_AXI_DIV_DEBUG_TRIGGER_MASK, + ESUB_AXI_DIV_DEBUG_ADDR); + + /* Wait for trigger complete */ + rc = -1; + retry_count = 0; + while (retry_count < PLL_MAX_RETRY) { + udelay(100); + if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & + ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) { + rc = 0; + break; + } + retry_count++; + } + + if (rc == -1) { + printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n", + __func__); + return -1; + } + + /* Disable Access to CCU registers */ + writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR); + + return rc; +} diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c new file mode 100644 index 0000000000..49badcbaa7 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c @@ -0,0 +1,73 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "clk-core.h" + +/* Enable appropriate clocks for an SDIO port */ +int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) +{ + int ret; + struct clk *c; + + char *clkstr; + char *slpstr; + char *ahbstr; + + switch ((u32) base) { + case CONFIG_SYS_SDIO_BASE0: + clkstr = CONFIG_SYS_SDIO0 "_clk"; + ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO0 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE1: + clkstr = CONFIG_SYS_SDIO1 "_clk"; + ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO1 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE2: + clkstr = CONFIG_SYS_SDIO2 "_clk"; + ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO2 "_sleep_clk"; + break; + case CONFIG_SYS_SDIO_BASE3: + clkstr = CONFIG_SYS_SDIO3 "_clk"; + ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk"; + slpstr = CONFIG_SYS_SDIO3 "_sleep_clk"; + break; + default: + printf("%s: base 0x%p not found\n", __func__, base); + return -EINVAL; + } + + ret = clk_get_and_enable(ahbstr); + if (ret) + return ret; + + ret = clk_get_and_enable(slpstr); + if (ret) + return ret; + + c = clk_get(clkstr); + if (c) { + ret = clk_set_rate(c, rate); + if (ret) + return ret; + + ret = clk_enable(c); + if (ret) + return ret; + } else { + printf("%s: Couldn't find %s\n", __func__, clkstr); + return -EINVAL; + } + *actual_ratep = rate; + return 0; +} diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file mode 100644 index 0000000000..1d7c5af76d --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c @@ -0,0 +1,27 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "clk-core.h" + +/* Enable appropriate clocks for the USB OTG port */ +int clk_usb_otg_enable(void *base) +{ + char *ahbstr; + + switch ((u32) base) { + case HSOTG_BASE_ADDR: + ahbstr = "usb_otg_ahb_clk"; + break; + default: + printf("%s: base 0x%p not found\n", __func__, base); + return -EINVAL; + } + + return clk_get_and_enable(ahbstr); +} diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c new file mode 100644 index 0000000000..3beb0ed9c7 --- /dev/null +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -0,0 +1,27 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define EN_MASK 0x08000000 /* Enable timer */ +#define SRSTEN_MASK 0x04000000 /* Enable soft reset */ +#define CLKS_SHIFT 20 /* Clock period shift */ +#define LD_SHIFT 0 /* Reload value shift */ + +void reset_cpu(ulong ignored) +{ + /* + * Set WD enable, RST enable, + * 3.9 msec clock period (8), reload value (8*3.9ms) + */ + u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT); + writel(reg, SECWD2_BASE_ADDR); + + while (1) + ; /* loop forever till reset */ +} diff --git a/arch/arm/cpu/armv7/bcmcygnus/Makefile b/arch/arm/cpu/armv7/bcmcygnus/Makefile new file mode 100644 index 0000000000..04afcf9aef --- /dev/null +++ b/arch/arm/cpu/armv7/bcmcygnus/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c new file mode 100644 index 0000000000..53ecc0ce0d --- /dev/null +++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CRMU_MAIL_BOX1 0x03024028 +#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF + +void reset_cpu(ulong ignored) +{ + /* Send soft reset command via Mailbox. */ + writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1); + + while (1) + ; /* loop forever till reset */ +} diff --git a/arch/arm/cpu/armv7/bcmnsp/Makefile b/arch/arm/cpu/armv7/bcmnsp/Makefile new file mode 100644 index 0000000000..04afcf9aef --- /dev/null +++ b/arch/arm/cpu/armv7/bcmnsp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c new file mode 100644 index 0000000000..d79d9aa344 --- /dev/null +++ b/arch/arm/cpu/armv7/bcmnsp/reset.c @@ -0,0 +1,19 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CRU_RESET_OFFSET 0x1803F184 + +void reset_cpu(ulong ignored) +{ + /* Reset the cpu by setting software reset request bit */ + writel(0x1, CRU_RESET_OFFSET); + + while (1) + ; /* loop forever till reset */ +} diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index f7865bc389..8ebe9b0303 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -21,7 +21,8 @@ * to get size details from Current Cache Size ID Register(CCSIDR) */ static void set_csselr(u32 level, u32 type) -{ u32 csselr = level << 1 | type; +{ + u32 csselr = level << 1 | type; /* Write to Cache Size Selection Register(CSSELR) */ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); @@ -49,7 +50,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -73,7 +75,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -134,7 +137,6 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation) static void v7_maint_dcache_all(u32 operation) { u32 level, cache_type, level_start_bit = 0; - u32 clidr = get_clidr(); for (level = 0; level < 7; level++) { @@ -147,8 +149,7 @@ static void v7_maint_dcache_all(u32 operation) } } -static void v7_dcache_clean_inval_range(u32 start, - u32 stop, u32 line_len) +static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) { u32 mva; @@ -258,7 +259,6 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop); @@ -355,41 +355,10 @@ void invalidate_icache_all(void) } #endif -/* - * Stub implementations for outer cache operations - */ -void __v7_outer_cache_enable(void) -{ -} -void v7_outer_cache_enable(void) - __attribute__((weak, alias("__v7_outer_cache_enable"))); - -void __v7_outer_cache_disable(void) -{ -} -void v7_outer_cache_disable(void) - __attribute__((weak, alias("__v7_outer_cache_disable"))); - -void __v7_outer_cache_flush_all(void) -{ -} -void v7_outer_cache_flush_all(void) - __attribute__((weak, alias("__v7_outer_cache_flush_all"))); - -void __v7_outer_cache_inval_all(void) -{ -} -void v7_outer_cache_inval_all(void) - __attribute__((weak, alias("__v7_outer_cache_inval_all"))); - -void __v7_outer_cache_flush_range(u32 start, u32 end) -{ -} -void v7_outer_cache_flush_range(u32 start, u32 end) - __attribute__((weak, alias("__v7_outer_cache_flush_range"))); - -void __v7_outer_cache_inval_range(u32 start, u32 end) -{ -} -void v7_outer_cache_inval_range(u32 start, u32 end) - __attribute__((weak, alias("__v7_outer_cache_inval_range"))); +/* Stub implementations for outer cache operations */ +__weak void v7_outer_cache_enable(void) {} +__weak void v7_outer_cache_disable(void) {} +__weak void v7_outer_cache_flush_all(void) {} +__weak void v7_outer_cache_inval_all(void) {} +__weak void v7_outer_cache_flush_range(u32 start, u32 end) {} +__weak void v7_outer_cache_inval_range(u32 start, u32 end) {} diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index ca4a9e72c0..6c82c3b537 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -4,31 +4,15 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # If armv7-a is not supported by GCC fall-back to armv5, which is # supported by more tool-chains PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) - -# SEE README.arm-unaligned-accesses +# On supported platforms we set the bit which causes us to trap on unaligned +# memory access. This is the opposite of what the compiler expects to be +# the default so we must pass in -mno-unaligned-access so that it is aware +# of our decision. PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) -PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED) - -ifneq ($(CONFIG_IMX_CONFIG),) -ifdef CONFIG_SPL -ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/SPL -endif -else -ALL-y += $(obj)u-boot.imx -endif -endif +PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED) diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index a5794c6cdb..f381d2ff98 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -62,7 +62,7 @@ int cleanup_before_linux(void) * After D-cache is flushed and before it is disabled there may * be some new valid entries brought into the cache. We are sure * that these lines are not dirty and will not affect our execution. - * (because unwinding the call-stack and setting a bit in CP15 SCTRL + * (because unwinding the call-stack and setting a bit in CP15 SCTLR * is all we did during this. We have not pushed anything on to the * stack. Neither have we affected any static data) * So just invalidate the entire d-cache again to avoid coherency diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig new file mode 100644 index 0000000000..7fcb5d2094 --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -0,0 +1,78 @@ +if ARCH_EXYNOS + +choice + prompt "EXYNOS board select" + +config TARGET_SMDKV310 + select SUPPORT_SPL + bool "Exynos4210 SMDKV310 board" + select OF_CONTROL if !SPL_BUILD + +config TARGET_TRATS + bool "Exynos4210 Trats board" + +config TARGET_S5PC210_UNIVERSAL + bool "EXYNOS4210 Universal C210 board" + +config TARGET_ORIGEN + bool "Exynos4412 Origen board" + select SUPPORT_SPL + +config TARGET_TRATS2 + bool "Exynos4412 Trat2 board" + +config TARGET_ODROID + bool "Exynos4412 Odroid board" + +config TARGET_ODROID_XU3 + bool "Exynos5422 Odroid board" + select OF_CONTROL + +config TARGET_ARNDALE + bool "Exynos5250 Arndale board" + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + +config TARGET_SMDK5250 + bool "SMDK5250 board" + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + +config TARGET_SNOW + bool "Snow board" + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + +config TARGET_SMDK5420 + bool "SMDK5420 board" + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + +config TARGET_PEACH_PI + bool "Peach Pi board" + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + +config TARGET_PEACH_PIT + bool "Peach Pit board" + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + +endchoice + +config SYS_SOC + default "exynos" + +source "board/samsung/smdkv310/Kconfig" +source "board/samsung/trats/Kconfig" +source "board/samsung/universal_c210/Kconfig" +source "board/samsung/origen/Kconfig" +source "board/samsung/trats2/Kconfig" +source "board/samsung/odroid/Kconfig" +source "board/samsung/arndale/Kconfig" +source "board/samsung/smdk5250/Kconfig" +source "board/samsung/smdk5420/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index eb1633fcfe..e207bd6af0 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -5,34 +5,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y += clock.o power.o soc.o system.o pinmux.o tzpc.o +obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o ifdef CONFIG_SPL_BUILD -COBJS-$(CONFIG_EXYNOS5) += clock_init_exynos5.o -COBJS-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o -COBJS-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o -COBJS-y += spl_boot.o -COBJS-y += lowlevel_init.o +obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o +obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o +obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o +obj-y += spl_boot.o +obj-y += lowlevel_init.o endif - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 0cb1a61aa1..b31c13b14b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,7 +26,7 @@ struct clk_bit_info { }; /* src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { +static struct clk_bit_info clk_bit_info[] = { {0, 0, -1}, {4, 4, -1}, {8, 8, -1}, @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) * VPLL_CON: MIDV [24:16] * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || + pllreg == SPLL) mask = 0x3ff; else mask = 0x1ff; @@ -96,7 +97,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) freq = CONFIG_SYS_CLK_FREQ; - if (pllreg == EPLL) { + if (pllreg == EPLL || pllreg == RPLL) { k = k & 0xffff; /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s))); @@ -117,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250()) + else if (proid_is_exynos5250() || proid_is_exynos5420() + || proid_is_exynos5800()) div = PLL_DIV_65536; else return 0; @@ -282,6 +284,9 @@ static unsigned long exynos5_get_periph_rate(int peripheral) src = readl(&clk->src_peric0); div = readl(&clk->div_peric3); break; + case PERIPH_ID_I2S0: + src = readl(&clk->src_mau); + div = readl(&clk->div_mau); case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: src = readl(&clk->src_peric1); @@ -359,6 +364,46 @@ unsigned long clock_get_periph_rate(int peripheral) return 0; } +/* exynos5420: return pll clock frequency */ +static unsigned long exynos5420_get_pll_clk(int pllreg) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + case BPLL: + r = readl(&clk->bpll_con0); + break; + case RPLL: + r = readl(&clk->rpll_con0); + k = readl(&clk->rpll_con1); + break; + case SPLL: + r = readl(&clk->spll_con0); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + /* exynos4: return ARM clock frequency */ static unsigned long exynos4_get_arm_clk(void) { @@ -482,6 +527,27 @@ static unsigned long exynos4x12_get_pwm_clk(void) return pclk; } +/* exynos5420: return pwm clock frequency */ +static unsigned long exynos5420_get_pwm_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int ratio; + + /* + * CLK_DIV_PERIC0 + * PWM_RATIO [31:28] + */ + ratio = readl(&clk->div_peric0); + ratio = (ratio >> 28) & 0xf; + sclk = get_pll_clk(MPLL); + + pclk = sclk / (ratio + 1); + + return pclk; +} + /* exynos4: return uart clock frequency */ static unsigned long exynos4_get_uart_clk(int dev_index) { @@ -621,6 +687,53 @@ static unsigned long exynos5_get_uart_clk(int dev_index) return uclk; } +/* exynos5420: return uart clock frequency */ +static unsigned long exynos5420_get_uart_clk(int dev_index) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_PERIC0 + * UART0_SEL [6:4] + * UART1_SEL [10:8] + * UART2_SEL [14:12] + * UART3_SEL [18:16] + * generalised calculation as follows + * sel = (sel >> ((dev_index * 4) + 4)) & mask; + */ + sel = readl(&clk->src_peric0); + sel = (sel >> ((dev_index * 4) + 4)) & 0x7; + + if (sel == 0x3) + sclk = get_pll_clk(MPLL); + else if (sel == 0x6) + sclk = get_pll_clk(EPLL); + else if (sel == 0x7) + sclk = get_pll_clk(RPLL); + else + return 0; + + /* + * CLK_DIV_PERIC0 + * UART0_RATIO [11:8] + * UART1_RATIO [15:12] + * UART2_RATIO [19:16] + * UART3_RATIO [23:20] + * generalised calculation as follows + * ratio = (ratio >> ((dev_index * 4) + 8)) & mask; + */ + ratio = readl(&clk->div_peric0); + ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf; + + uclk = sclk / (ratio + 1); + + return uclk; +} + static unsigned long exynos4_get_mmc_clk(int dev_index) { struct exynos4_clock *clk = @@ -715,13 +828,55 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) return uclk; } +static unsigned long exynos5420_get_mmc_clk(int dev_index) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel, ratio; + + /* + * CLK_SRC_FSYS + * MMC0_SEL [10:8] + * MMC1_SEL [14:12] + * MMC2_SEL [18:16] + * generalised calculation as follows + * sel = (sel >> ((dev_index * 4) + 8)) & mask + */ + sel = readl(&clk->src_fsys); + sel = (sel >> ((dev_index * 4) + 8)) & 0x7; + + if (sel == 0x3) + sclk = get_pll_clk(MPLL); + else if (sel == 0x4) + sclk = get_pll_clk(SPLL); + else if (sel == 0x6) + sclk = get_pll_clk(EPLL); + else + return 0; + + /* + * CLK_DIV_FSYS1 + * MMC0_RATIO [9:0] + * MMC1_RATIO [19:10] + * MMC2_RATIO [29:20] + * generalised calculation as follows + * ratio = (ratio >> (dev_index * 10)) & mask + */ + ratio = readl(&clk->div_fsys1); + ratio = (ratio >> (dev_index * 10)) & 0x3ff; + + uclk = (sclk / (ratio + 1)); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int addr; - unsigned int val; + unsigned int addr, clear_bit, set_bit; /* * CLK_DIV_FSYS1 @@ -729,31 +884,34 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) * CLK_DIV_FSYS2 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] * CLK_DIV_FSYS3 - * MMC4_PRE_RATIO [15:8] + * MMC4_RATIO [3:0] */ if (dev_index < 2) { addr = (unsigned int)&clk->div_fsys1; - } else if (dev_index == 4) { + clear_bit = MASK_PRE_RATIO(dev_index); + set_bit = SET_PRE_RATIO(dev_index, div); + } else if (dev_index == 4) { addr = (unsigned int)&clk->div_fsys3; dev_index -= 4; + /* MMC4 is controlled with the MMC4_RATIO value */ + clear_bit = MASK_RATIO(dev_index); + set_bit = SET_RATIO(dev_index, div); } else { addr = (unsigned int)&clk->div_fsys2; dev_index -= 2; + clear_bit = MASK_PRE_RATIO(dev_index); + set_bit = SET_PRE_RATIO(dev_index, div); } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, clear_bit, set_bit); } -/* exynos4x12: set the mmc clock */ -static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) +/* exynos5: set the mmc clock */ +static void exynos5_set_mmc_clk(int dev_index, unsigned int div) { - struct exynos4x12_clock *clk = - (struct exynos4x12_clock *)samsung_get_base_clock(); + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -768,37 +926,28 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos5: set the mmc clock */ -static void exynos5_set_mmc_clk(int dev_index, unsigned int div) +static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) { - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; + unsigned int shift; /* * CLK_DIV_FSYS1 - * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] - * CLK_DIV_FSYS2 - * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + * MMC0_RATIO [9:0] + * MMC1_RATIO [19:10] + * MMC2_RATIO [29:20] */ - if (dev_index < 2) { - addr = (unsigned int)&clk->div_fsys1; - } else { - addr = (unsigned int)&clk->div_fsys2; - dev_index -= 2; - } + addr = (unsigned int)&clk->div_fsys1; + shift = dev_index * 10; - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); } /* get_lcd_clk: return lcd clock frequency */ @@ -885,11 +1034,44 @@ static unsigned long exynos5_get_lcd_clk(void) return pclk; } +static unsigned long exynos5420_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + sel = readl(&clk->src_disp10); + sel &= (1 << 4); + + if (sel) + sclk = get_pll_clk(SPLL); + else + sclk = get_pll_clk(RPLL); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10); + ratio = ratio & 0xf; + + pclk = sclk / (ratio + 1); + + return pclk; +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -901,9 +1083,7 @@ void exynos4_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -913,10 +1093,7 @@ void exynos4_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); /* * CLK_GATE_IP_LCD0 @@ -928,9 +1105,7 @@ void exynos4_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 0); /* * CLK_DIV_LCD0 @@ -942,16 +1117,13 @@ void exynos4_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x1; - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); } void exynos5_set_lcd_clk(void) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -963,9 +1135,7 @@ void exynos5_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -975,10 +1145,7 @@ void exynos5_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_disp1_0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_disp1_0); + clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); /* * CLK_GATE_IP_LCD0 @@ -990,9 +1157,7 @@ void exynos5_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_disp1); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_disp1); + setbits_le32(&clk->gate_ip_disp1, 1 << 0); /* * CLK_DIV_LCD0 @@ -1004,16 +1169,40 @@ void exynos5_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x0; - writel(cfg, &clk->div_disp1_0); + clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); +} + +void exynos5420_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + cfg = readl(&clk->src_disp10); + cfg &= ~(0x1 << 4); + cfg |= (0 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + cfg = readl(&clk->div_disp10); + cfg &= ~(0xf << 0); + cfg |= (0 << 0); + writel(cfg, &clk->div_disp10); } void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_SRC_LCD0 @@ -1023,10 +1212,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_SEL [12:15] * set mipi0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf << 12); - cfg |= (0x6 << 12); - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); /* * CLK_SRC_MASK_LCD0 @@ -1036,9 +1222,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_MASK [12] * set src mask mipi0 0x1: Unmask */ - cfg = readl(&clk->src_mask_lcd0); - cfg |= (0x1 << 12); - writel(cfg, &clk->src_mask_lcd0); + setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); /* * CLK_GATE_IP_LCD0 @@ -1050,9 +1234,7 @@ void exynos4_set_mipi_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for MIPI0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 3; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 3); /* * CLK_DIV_LCD0 @@ -1064,9 +1246,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_PRE_RATIO [23:20] * set mipi ratio */ - cfg &= ~(0xf << 16); - cfg |= (0x1 << 16); - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); } /* @@ -1146,17 +1326,29 @@ int exynos5_set_epll_clk(unsigned long rate) return 0; } -void exynos5_set_i2s_clk_source(void) +int exynos5_set_i2s_clk_source(unsigned int i2s_id) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - - clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, - (CLK_SRC_SCLK_EPLL)); + unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass(); + + if (i2s_id == 0) { + setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL); + clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK, + (CLK_SRC_SCLK_EPLL)); + setbits_le32(audio_ass, AUDIO_CLKMUX_ASS); + } else if (i2s_id == 1) { + clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, + (CLK_SRC_SCLK_EPLL)); + } else { + return -1; + } + return 0; } int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, - unsigned int dst_frq) + unsigned int dst_frq, + unsigned int i2s_id) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); @@ -1169,13 +1361,27 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, } div = (src_frq / dst_frq); - if (div > AUDIO_1_RATIO_MASK) { - debug("%s: Frequency ratio is out of range\n", __func__); - debug("src frq = %d des frq = %d ", src_frq, dst_frq); + if (i2s_id == 0) { + if (div > AUDIO_0_RATIO_MASK) { + debug("%s: Frequency ratio is out of range\n", + __func__); + debug("src frq = %d des frq = %d ", src_frq, dst_frq); + return -1; + } + clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK, + (div & AUDIO_0_RATIO_MASK)); + } else if(i2s_id == 1) { + if (div > AUDIO_1_RATIO_MASK) { + debug("%s: Frequency ratio is out of range\n", + __func__); + debug("src frq = %d des frq = %d ", src_frq, dst_frq); + return -1; + } + clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, + (div & AUDIO_1_RATIO_MASK)); + } else { return -1; } - clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, - (div & AUDIO_1_RATIO_MASK)); return 0; } @@ -1219,8 +1425,8 @@ static int clock_calc_best_scalar(unsigned int main_scaler_bits, return 1; for (i = 1; i <= loops; i++) { - const unsigned int effective_div = max(min(input_rate / i / - target_rate, cap), 1); + const unsigned int effective_div = + max(min(input_rate / i / target_rate, cap), 1U); const unsigned int effective_rate = input_rate / i / effective_div; const int error = target_rate - effective_rate; @@ -1295,6 +1501,71 @@ static int exynos5_set_spi_clk(enum periph_id periph_id, return 0; } +static int exynos5420_set_spi_clk(enum periph_id periph_id, + unsigned int rate) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + int main; + unsigned int fine; + unsigned shift, pre_shift; + unsigned div_mask = 0xf, pre_div_mask = 0xff; + u32 *reg; + u32 *pre_reg; + + main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); + if (main < 0) { + debug("%s: Cannot set clock rate for periph %d", + __func__, periph_id); + return -1; + } + main = main - 1; + fine = fine - 1; + + switch (periph_id) { + case PERIPH_ID_SPI0: + reg = &clk->div_peric1; + shift = 20; + pre_reg = &clk->div_peric4; + pre_shift = 8; + break; + case PERIPH_ID_SPI1: + reg = &clk->div_peric1; + shift = 24; + pre_reg = &clk->div_peric4; + pre_shift = 16; + break; + case PERIPH_ID_SPI2: + reg = &clk->div_peric1; + shift = 28; + pre_reg = &clk->div_peric4; + pre_shift = 24; + break; + case PERIPH_ID_SPI3: + reg = &clk->div_isp1; + shift = 16; + pre_reg = &clk->div_isp1; + pre_shift = 0; + break; + case PERIPH_ID_SPI4: + reg = &clk->div_isp1; + shift = 20; + pre_reg = &clk->div_isp1; + pre_shift = 8; + break; + default: + debug("%s: Unsupported peripheral ID %d\n", __func__, + periph_id); + return -1; + } + + clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift); + clrsetbits_le32(pre_reg, pre_div_mask << pre_shift, + (fine & pre_div_mask) << pre_shift); + + return 0; +} + static unsigned long exynos4_get_i2c_clk(void) { struct exynos4_clock *clk = @@ -1312,9 +1583,11 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos5420_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); - else { + } else { if (proid_is_exynos4412()) return exynos4x12_get_pll_clk(pllreg); return exynos4_get_pll_clk(pllreg); @@ -1346,9 +1619,11 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); - else { + } else { if (proid_is_exynos4412()) return exynos4x12_get_pwm_clk(); return exynos4_get_pwm_clk(); @@ -1357,9 +1632,11 @@ unsigned long get_pwm_clk(void) unsigned long get_uart_clk(int dev_index) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos5420_get_uart_clk(dev_index); return exynos5_get_uart_clk(dev_index); - else { + } else { if (proid_is_exynos4412()) return exynos4x12_get_uart_clk(dev_index); return exynos4_get_uart_clk(dev_index); @@ -1368,19 +1645,23 @@ unsigned long get_uart_clk(int dev_index) unsigned long get_mmc_clk(int dev_index) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos5420_get_mmc_clk(dev_index); return exynos5_get_mmc_clk(dev_index); - else + } else { return exynos4_get_mmc_clk(dev_index); + } } void set_mmc_clk(int dev_index, unsigned int div) { - if (cpu_is_exynos5()) - exynos5_set_mmc_clk(dev_index, div); - else { - if (proid_is_exynos4412()) - exynos4x12_set_mmc_clk(dev_index, div); + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + exynos5420_set_mmc_clk(dev_index, div); + else + exynos5_set_mmc_clk(dev_index, div); + } else { exynos4_set_mmc_clk(dev_index, div); } } @@ -1389,16 +1670,24 @@ unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); - else - return exynos5_get_lcd_clk(); + else { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos5420_get_lcd_clk(); + else + return exynos5_get_lcd_clk(); + } } void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk(); - else - exynos5_set_lcd_clk(); + else { + if (proid_is_exynos5250()) + exynos5_set_lcd_clk(); + else if (proid_is_exynos5420() || proid_is_exynos5800()) + exynos5420_set_lcd_clk(); + } } void set_mipi_clk(void) @@ -1409,25 +1698,30 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); - else + } else { return 0; + } } -int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, + unsigned int i2s_id) { - if (cpu_is_exynos5()) - return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq); + return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id); else return 0; } -void set_i2s_clk_source(void) +int set_i2s_clk_source(unsigned int i2s_id) { if (cpu_is_exynos5()) - exynos5_set_i2s_clk_source(); + return exynos5_set_i2s_clk_source(i2s_id); + else + return 0; } int set_epll_clk(unsigned long rate) diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index c28ff3ab14..fce502f45a 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -10,7 +10,11 @@ #define __EXYNOS_CLOCK_INIT_H enum { +#ifdef CONFIG_EXYNOS5420 + MEM_TIMINGS_MSR_COUNT = 5, +#else MEM_TIMINGS_MSR_COUNT = 4, +#endif }; /* These are the ratio's for configuring ARM clock */ @@ -59,6 +63,21 @@ struct mem_timings { unsigned bpll_mdiv; unsigned bpll_pdiv; unsigned bpll_sdiv; + unsigned kpll_mdiv; + unsigned kpll_pdiv; + unsigned kpll_sdiv; + unsigned dpll_mdiv; + unsigned dpll_pdiv; + unsigned dpll_sdiv; + unsigned ipll_mdiv; + unsigned ipll_pdiv; + unsigned ipll_sdiv; + unsigned spll_mdiv; + unsigned spll_pdiv; + unsigned spll_sdiv; + unsigned rpll_mdiv; + unsigned rpll_pdiv; + unsigned rpll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; @@ -115,6 +134,7 @@ struct mem_timings { uint8_t send_zq_init; /* 1 to send this command */ unsigned impedance; /* drive strength impedeance */ uint8_t gate_leveling_enable; /* check gate leveling is enabled */ + uint8_t read_leveling_enable; /* check h/w read leveling is enabled */ }; /** diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index a24c2f3875..0aff3d0d0c 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -24,6 +24,24 @@ DECLARE_GLOBAL_DATA_PTR; struct arm_clk_ratios arm_clk_ratios[] = { +#ifdef CONFIG_EXYNOS5420 + { + .arm_freq_mhz = 900, + + .apll_mdiv = 0x96, + .apll_pdiv = 0x2, + .apll_sdiv = 0x1, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x6, + .atb_ratio = 0x6, + .periph_ratio = 0x7, + .acp_ratio = 0x0, + .cpud_ratio = 0x2, + .arm_ratio = 0x0, + } +#else { .arm_freq_mhz = 600, @@ -115,8 +133,137 @@ struct arm_clk_ratios arm_clk_ratios[] = { .cpud_ratio = 0x3, .arm_ratio = 0x0, } +#endif }; + struct mem_timings mem_timings[] = { +#ifdef CONFIG_EXYNOS5420 + { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + + /* MPLL @800MHz*/ + .mpll_mdiv = 0xc8, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x1, + /* CPLL @666MHz */ + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x1, + /* EPLL @600MHz */ + .epll_mdiv = 0x64, + .epll_pdiv = 0x2, + .epll_sdiv = 0x1, + /* VPLL @430MHz */ + .vpll_mdiv = 0xd7, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + /* BPLL @800MHz */ + .bpll_mdiv = 0xc8, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x1, + /* KPLL @600MHz */ + .kpll_mdiv = 0x190, + .kpll_pdiv = 0x4, + .kpll_sdiv = 0x2, + /* DPLL @600MHz */ + .dpll_mdiv = 0x190, + .dpll_pdiv = 0x4, + .dpll_sdiv = 0x2, + /* IPLL @370MHz */ + .ipll_mdiv = 0xb9, + .ipll_pdiv = 0x3, + .ipll_sdiv = 0x2, + /* SPLL @400MHz */ + .spll_mdiv = 0xc8, + .spll_pdiv = 0x3, + .spll_sdiv = 0x2, + /* RPLL @70.5Mhz */ + .rpll_mdiv = 0x5E, + .rpll_pdiv = 0x2, + .rpll_sdiv = 0x4, + + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010046, 0x00000d70, + 0x00000c70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x6836650f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a26, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_DISABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT | + DMC_MEMCONFIGX_CHIP_COL_10 | + DMC_MEMCONFIGX_CHIP_ROW_15 | + DMC_MEMCONFIGX_CHIP_BANK_8, + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 1, + .chips_per_channel = 1, + .chips_to_configure = 1, + .send_zq_init = 1, + .gate_leveling_enable = 1, + .read_leveling_enable = 0, + } +#else { .mem_manuf = MEM_MANUF_ELPIDA, .mem_type = DDR_MODE_DDR3, @@ -324,6 +471,7 @@ struct mem_timings mem_timings[] = { .impedance = IMP_OUTPUT_DRV_40_OHM, .gate_leveling_enable = 1, } +#endif }; /** @@ -399,7 +547,7 @@ struct mem_timings *clock_get_mem_timings(void) return NULL; } -void system_clock_init() +static void exynos5250_system_clock_init(void) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); @@ -436,19 +584,13 @@ void system_clock_init() } while ((val | MUX_BPLL_SEL_MASK) != val); /* PLL locktime */ - writel(APLL_LOCK_VAL, &clk->apll_lock); - - writel(MPLL_LOCK_VAL, &clk->mpll_lock); - - writel(BPLL_LOCK_VAL, &clk->bpll_lock); - - writel(CPLL_LOCK_VAL, &clk->cpll_lock); - - writel(GPLL_LOCK_VAL, &clk->gpll_lock); - - writel(EPLL_LOCK_VAL, &clk->epll_lock); - - writel(VPLL_LOCK_VAL, &clk->vpll_lock); + writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock); + writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock); + writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock); + writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); + writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock); + writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock); + writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock); writel(CLK_REG_DISABLE, &clk->pll_div2_sel); @@ -640,6 +782,201 @@ void system_clock_init() writel(val, &clk->div_fsys2); } +static void exynos5420_system_clock_init(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + struct mem_timings *mem; + struct arm_clk_ratios *arm_clk_ratio; + u32 val; + + mem = clock_get_mem_timings(); + arm_clk_ratio = get_arm_ratios(); + + /* PLL locktime */ + writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock); + writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock); + writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock); + writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); + writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock); + writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock); + writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock); + writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); + writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); + writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock); + writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock); + + setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK); + + writel(0, &clk->src_top6); + + writel(0, &clk->src_cdrex); + writel(SRC_KFC_HPM_SEL, &clk->src_kfc); + writel(HPM_RATIO, &clk->div_cpu1); + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); + + /* switch A15 clock source to OSC clock before changing APLL */ + clrbits_le32(&clk->src_cpu, APLL_FOUT); + + /* Set APLL */ + writel(APLL_CON1_VAL, &clk->apll_con1); + val = set_pll(arm_clk_ratio->apll_mdiv, + arm_clk_ratio->apll_pdiv, + arm_clk_ratio->apll_sdiv); + writel(val, &clk->apll_con0); + while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0) + ; + + /* now it is safe to switch to APLL */ + setbits_le32(&clk->src_cpu, APLL_FOUT); + + writel(SRC_KFC_HPM_SEL, &clk->src_kfc); + writel(CLK_DIV_KFC_VAL, &clk->div_kfc0); + + /* switch A7 clock source to OSC clock before changing KPLL */ + clrbits_le32(&clk->src_kfc, KPLL_FOUT); + + /* Set KPLL*/ + writel(KPLL_CON1_VAL, &clk->kpll_con1); + val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv); + writel(val, &clk->kpll_con0); + while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0) + ; + + /* now it is safe to switch to KPLL */ + setbits_le32(&clk->src_kfc, KPLL_FOUT); + + /* Set MPLL */ + writel(MPLL_CON1_VAL, &clk->mpll_con1); + val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); + writel(val, &clk->mpll_con0); + while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set DPLL */ + writel(DPLL_CON1_VAL, &clk->dpll_con1); + val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv); + writel(val, &clk->dpll_con0); + while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set EPLL */ + writel(EPLL_CON2_VAL, &clk->epll_con2); + writel(EPLL_CON1_VAL, &clk->epll_con1); + val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); + writel(val, &clk->epll_con0); + while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0) + ; + + /* Set CPLL */ + writel(CPLL_CON1_VAL, &clk->cpll_con1); + val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); + writel(val, &clk->cpll_con0); + while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set IPLL */ + writel(IPLL_CON1_VAL, &clk->ipll_con1); + val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv); + writel(val, &clk->ipll_con0); + while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0) + ; + + /* Set VPLL */ + writel(VPLL_CON1_VAL, &clk->vpll_con1); + val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); + writel(val, &clk->vpll_con0); + while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set BPLL */ + writel(BPLL_CON1_VAL, &clk->bpll_con1); + val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); + writel(val, &clk->bpll_con0); + while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set SPLL */ + writel(SPLL_CON1_VAL, &clk->spll_con1); + val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv); + writel(val, &clk->spll_con0); + while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) + ; + + /* Set RPLL */ + writel(RPLL_CON2_VAL, &clk->rpll_con2); + writel(RPLL_CON1_VAL, &clk->rpll_con1); + val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv); + writel(val, &clk->rpll_con0); + while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0) + ; + + writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); + writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1); + + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + writel(CLK_SRC_TOP2_VAL, &clk->src_top2); + writel(CLK_SRC_TOP7_VAL, &clk->src_top7); + + writel(CLK_DIV_TOP0_VAL, &clk->div_top0); + writel(CLK_DIV_TOP1_VAL, &clk->div_top1); + writel(CLK_DIV_TOP2_VAL, &clk->div_top2); + + writel(0, &clk->src_top10); + writel(0, &clk->src_top11); + writel(0, &clk->src_top12); + + writel(CLK_SRC_TOP3_VAL, &clk->src_top3); + writel(CLK_SRC_TOP4_VAL, &clk->src_top4); + writel(CLK_SRC_TOP5_VAL, &clk->src_top5); + + /* DISP1 BLK CLK SELECTION */ + writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10); + writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10); + + /* AUDIO BLK */ + writel(AUDIO0_SEL_EPLL, &clk->src_mau); + writel(DIV_MAU_VAL, &clk->div_mau); + + /* FSYS */ + writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); + writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); + writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); + writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); + + writel(CLK_SRC_ISP_VAL, &clk->src_isp); + writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); + writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); + + writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); + writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); + + writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); + writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); + writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); + writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); + writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4); + + writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1); + + writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio); + writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio); + writel(CLK_DIV_G2D, &clk->div_g2d); + + writel(CLK_SRC_TOP6_VAL, &clk->src_top6); + writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex); + writel(CLK_SRC_KFC_VAL, &clk->src_kfc); +} + +void system_clock_init(void) +{ + if (proid_is_exynos5420() || proid_is_exynos5800()) + exynos5420_system_clock_init(); + else + exynos5250_system_clock_init(); +} + void clock_init_dp_clock(void) { struct exynos5_clock *clk = diff --git a/arch/arm/cpu/armv7/exynos/config.mk b/arch/arm/cpu/armv7/exynos/config.mk new file mode 100644 index 0000000000..ee0d2dab7b --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) Albert ARIBAUD +# +# SPDX-License-Identifier: GPL-2.0+ +# + +SPL_OBJCFLAGS += -j .machine_param diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c index 53cfe6edb1..9b6ee69f46 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_common.c +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c @@ -1,5 +1,5 @@ /* - * Mem setup common file for different types of DDR present on SMDK5250 boards. + * Mem setup common file for different types of DDR present on Exynos boards. * * Copyright (C) 2012 Samsung Electronics * @@ -15,9 +15,9 @@ #define ZQ_INIT_TIMEOUT 10000 -int dmc_config_zq(struct mem_timings *mem, - struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl) +int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16, + uint32_t *phy1_con16, uint32_t *phy0_con17, + uint32_t *phy1_con17) { unsigned long val = 0; int i; @@ -31,19 +31,19 @@ int dmc_config_zq(struct mem_timings *mem, val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; val |= ZQ_CLK_DIV_EN; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + writel(val, phy0_con16); + writel(val, phy1_con16); /* Disable termination */ if (mem->zq_mode_noterm) val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + writel(val, phy0_con16); + writel(val, phy1_con16); /* ZQ_MANUAL_START: Enable */ val |= ZQ_MANUAL_STR; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + writel(val, phy0_con16); + writel(val, phy1_con16); /* ZQ_MANUAL_START: Disable */ val &= ~ZQ_MANUAL_STR; @@ -53,47 +53,47 @@ int dmc_config_zq(struct mem_timings *mem, * we are looping for the ZQ_init to complete. */ i = ZQ_INIT_TIMEOUT; - while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { sdelay(100); i--; } if (!i) return -1; - writel(val, &phy0_ctrl->phy_con16); + writel(val, phy0_con16); i = ZQ_INIT_TIMEOUT; - while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { sdelay(100); i--; } if (!i) return -1; - writel(val, &phy1_ctrl->phy_con16); + writel(val, phy1_con16); return 0; } -void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) +void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) { unsigned long val; if (mode == DDR_MODE_DDR3) { val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; - writel(val, &dmc->phycontrol0); + writel(val, phycontrol0); } /* Update DLL Information: Force DLL Resyncronization */ - val = readl(&dmc->phycontrol0); + val = readl(phycontrol0); val |= FP_RSYNC; - writel(val, &dmc->phycontrol0); + writel(val, phycontrol0); /* Reset Force DLL Resyncronization */ - val = readl(&dmc->phycontrol0); + val = readl(phycontrol0); val &= ~FP_RSYNC; - writel(val, &dmc->phycontrol0); + writel(val, phycontrol0); } -void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) +void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd) { int channel, chip; @@ -107,7 +107,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* Sending NOP command */ - writel(DIRECT_CMD_NOP | mask, &dmc->directcmd); + writel(DIRECT_CMD_NOP | mask, directcmd); /* * TODO(alim.akhtar@samsung.com): Do we need these @@ -119,14 +119,14 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + directcmd); sdelay(0x10000); } if (mem->send_zq_init) { /* Sending ZQINIT command */ writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + directcmd); sdelay(10000); } @@ -134,7 +134,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) } } -void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) +void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd) { int channel, chip; @@ -146,20 +146,12 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* PALL (all banks precharge) CMD */ - writel(DIRECT_CMD_PALL | mask, &dmc->directcmd); + writel(DIRECT_CMD_PALL | mask, directcmd); sdelay(0x10000); } } } -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) -{ - writel(mem->memconfig, &dmc->memconfig0); - writel(mem->memconfig, &dmc->memconfig1); - writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0); - writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); -} - void mem_ctrl_init(int reset) { struct spl_machine_param *param = spl_get_machine_params(); @@ -170,7 +162,7 @@ void mem_ctrl_init(int reset) /* If there are any other memory variant, add their init call below */ if (param->mem_type == DDR_MODE_DDR3) { - ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset); + ret = ddr3_mem_ctrl_init(mem, reset); if (ret) { /* will hang if failed to init memory control */ while (1) diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 5f5914ede8..7c0b12ae51 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -1,22 +1,29 @@ /* - * DDR3 mem setup file for SMDK5250 board based on EXYNOS5 + * DDR3 mem setup file for board based on EXYNOS5 * * Copyright (C) 2012 Samsung Electronics * * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include #include #include +#include #include "common_setup.h" #include "exynos5_setup.h" #include "clock_init.h" -#define RDLVL_COMPLETE_TIMEOUT 10000 +#define TIMEOUT_US 10000 +#define NUM_BYTE_LANES 4 +#define DEFAULT_DQS 8 +#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) +#ifdef CONFIG_EXYNOS5250 static void reset_phy_ctrl(void) { struct exynos5_clock *clk = @@ -26,8 +33,7 @@ static void reset_phy_ctrl(void) writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); } -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset) +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -57,7 +63,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val, &phy1_ctrl->phy_con42); /* ZQ Calibration */ - if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl)) + if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, + &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17)) return SETUP_ERR_ZQ_CALIBRATION_FAILURE; /* DQ Signal */ @@ -68,7 +75,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), &dmc->concontrol); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); /* DQS Signal */ writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); @@ -93,7 +100,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), &phy1_ctrl->phy_con12); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), &dmc->concontrol); @@ -124,10 +131,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(mem->timing_power, &dmc->timingpower); /* Send PALL command */ - dmc_config_prech(mem, dmc); + dmc_config_prech(mem, &dmc->directcmd); /* Send NOP, MRS and ZQINIT commands */ - dmc_config_mrs(mem, dmc); + dmc_config_mrs(mem, &dmc->directcmd); if (mem->gate_leveling_enable) { val = PHY_CON0_RESET_VAL; @@ -174,7 +181,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val, &phy1_ctrl->phy_con1); writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config); - i = RDLVL_COMPLETE_TIMEOUT; + i = TIMEOUT_US; while ((readl(&dmc->phystatus) & (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { @@ -202,11 +209,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val, &phy0_ctrl->phy_con12); writel(val, &phy1_ctrl->phy_con12); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); } /* Send PALL command */ - dmc_config_prech(mem, dmc); + dmc_config_prech(mem, &dmc->directcmd); writel(mem->memcontrol, &dmc->memcontrol); @@ -215,3 +222,645 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); return 0; } +#endif + +#ifdef CONFIG_EXYNOS5420 +/** + * RAM address to use in the test. + * + * We'll use 4 words at this address and 4 at this address + 0x80 (Ares + * interleaves channels every 128 bytes). This will allow us to evaluate all of + * the chips in a 1 chip per channel (2GB) system and half the chips in a 2 + * chip per channel (4GB) system. We can't test the 2nd chip since we need to + * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't + * critical because the 1st and 2nd chip have very similar timings (they'd + * better have similar timings, since there's only a single adjustment that is + * shared by both chips). + */ +const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; + +/* Test pattern with which RAM will be tested */ +static const unsigned int test_pattern[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0xf0f0f0f0, + 0x0f0f0f0f, +}; + +/** + * This function is a test vector for sw read leveling, + * it compares the read data with the written data. + * + * @param ch DMC channel number + * @param byte_lane which DQS byte offset, + * possible values are 0,1,2,3 + * @return TRUE if memory was good, FALSE if not. + */ +static bool dmc_valid_window_test_vector(int ch, int byte_lane) +{ + unsigned int read_data; + unsigned int mask; + int i; + + mask = 0xFF << (8 * byte_lane); + + for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { + read_data = readl(test_addr + i * 4 + ch * 0x80); + if ((read_data & mask) != (test_pattern[i] & mask)) + return false; + } + + return true; +} + +/** + * This function returns current read offset value. + * + * @param phy_ctrl pointer to the current phy controller + */ +static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control + *phy_ctrl) +{ + return readl(&phy_ctrl->phy_con4); +} + +/** + * This function performs resync, so that slave DLL is updated. + * + * @param phy_ctrl pointer to the current phy controller + */ +static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl) +{ + setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); + clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); +} + +/** + * This function sets read offset value register with 'offset'. + * + * ...we also call call ddr_phy_set_do_resync(). + * + * @param phy_ctrl pointer to the current phy controller + * @param offset offset to read DQS + */ +static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl, + unsigned int offset) +{ + writel(offset, &phy_ctrl->phy_con4); + ddr_phy_set_do_resync(phy_ctrl); +} + +/** + * Convert a 2s complement byte to a byte with a sign bit. + * + * NOTE: you shouldn't use normal math on the number returned by this function. + * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted + * to do math and get the average of 10 and -10 (should be 0): + * 0x8a + 0xa = 0x94 (-108) + * 0x94 / 2 = 0xca (-54) + * ...and 0xca = sign bit plus 0x4a, or -74 + * + * Also note that you lose the ability to represent -128 since there are two + * representations of 0. + * + * @param b The byte to convert in two's complement. + * @return The 7-bit value + sign bit. + */ + +unsigned char make_signed_byte(signed char b) +{ + if (b < 0) + return 0x80 | -b; + else + return b; +} + +/** + * Test various shifts starting at 'start' and going to 'end'. + * + * For each byte lane, we'll walk through shift starting at 'start' and going + * to 'end' (inclusive). When we are finally able to read the test pattern + * we'll store the value in the results array. + * + * @param phy_ctrl pointer to the current phy controller + * @param ch channel number + * @param start the start shift. -127 to 127 + * @param end the end shift. -127 to 127 + * @param results we'll store results for each byte lane. + */ + +void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, + int start, int end, int results[NUM_BYTE_LANES]) +{ + int incr = (start < end) ? 1 : -1; + int byte_lane; + + for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { + int shift; + + dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); + results[byte_lane] = DEFAULT_DQS; + + for (shift = start; shift != (end + incr); shift += incr) { + unsigned int byte_offsetr; + unsigned int offsetr; + + byte_offsetr = make_signed_byte(shift); + + offsetr = dmc_get_read_offset_value(phy_ctrl); + offsetr &= ~(0xFF << (8 * byte_lane)); + offsetr |= (byte_offsetr << (8 * byte_lane)); + dmc_set_read_offset_value(phy_ctrl, offsetr); + + if (dmc_valid_window_test_vector(ch, byte_lane)) { + results[byte_lane] = shift; + break; + } + } + } +} + +/** + * This function performs SW read leveling to compensate DQ-DQS skew at + * receiver it first finds the optimal read offset value on each DQS + * then applies the value to PHY. + * + * Read offset value has its min margin and max margin. If read offset + * value exceeds its min or max margin, read data will have corruption. + * To avoid this we are doing sw read leveling. + * + * SW read leveling is: + * 1> Finding offset value's left_limit and right_limit + * 2> and calculate its center value + * 3> finally programs that center value to PHY + * 4> then PHY gets its optimal offset value. + * + * @param phy_ctrl pointer to the current phy controller + * @param ch channel number + * @param coarse_lock_val The coarse lock value read from PHY_CON13. + * (0 - 0x7f) + */ +static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl, + int ch, unsigned int coarse_lock_val) +{ + unsigned int offsetr_cent; + int byte_lane; + int left_limit; + int right_limit; + int left[NUM_BYTE_LANES]; + int right[NUM_BYTE_LANES]; + int i; + + /* Fill the memory with test patterns */ + for (i = 0; i < ARRAY_SIZE(test_pattern); i++) + writel(test_pattern[i], test_addr + i * 4 + ch * 0x80); + + /* Figure out the limits we'll test with; keep -127 < limit < 127 */ + left_limit = DEFAULT_DQS - coarse_lock_val; + right_limit = DEFAULT_DQS + coarse_lock_val; + if (right_limit > 127) + right_limit = 127; + + /* Fill in the location where reads were OK from left and right */ + test_shifts(phy_ctrl, ch, left_limit, right_limit, left); + test_shifts(phy_ctrl, ch, right_limit, left_limit, right); + + /* Make a final value by taking the center between the left and right */ + offsetr_cent = 0; + for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { + int temp_center; + unsigned int vmwc; + + temp_center = (left[byte_lane] + right[byte_lane]) / 2; + vmwc = make_signed_byte(temp_center); + offsetr_cent |= vmwc << (8 * byte_lane); + } + dmc_set_read_offset_value(phy_ctrl, offsetr_cent); +} + +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + struct exynos5420_power *power = + (struct exynos5420_power *)samsung_get_base_power(); + struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl; + struct exynos5420_dmc *drex0, *drex1; + struct exynos5420_tzasc *tzasc0, *tzasc1; + struct exynos5_power *pmu; + uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; + uint32_t lock0_info, lock1_info; + int chip; + int i; + + phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy(); + phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy() + + DMC_OFFSET); + drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl(); + drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl() + + DMC_OFFSET); + tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc(); + tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc() + + DMC_OFFSET); + pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; + + if (CONFIG_NR_DRAM_BANKS > 4) { + /* Need both controllers. */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2; + mem->chips_per_channel = 2; + mem->chips_to_configure = 2; + } else { + /* 2GB requires a single controller */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1; + } + + /* Enable PAUSE for DREX */ + setbits_le32(&clk->pause, ENABLE_BIT); + + /* Enable BYPASS mode */ + setbits_le32(&clk->bpll_con1, BYPASS_EN); + + writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex); + do { + val = readl(&clk->mux_stat_cdrex); + val &= BPLL_SEL_MASK; + } while (val != FOUTBPLL); + + clrbits_le32(&clk->bpll_con1, BYPASS_EN); + + /* Specify the DDR memory type as DDR3 */ + val = readl(&phy0_ctrl->phy_con0); + val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); + val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); + writel(val, &phy0_ctrl->phy_con0); + + val = readl(&phy1_ctrl->phy_con0); + val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); + val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); + writel(val, &phy1_ctrl->phy_con0); + + /* Set Read Latency and Burst Length for PHY0 and PHY1 */ + val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | + (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); + writel(val, &phy0_ctrl->phy_con42); + writel(val, &phy1_ctrl->phy_con42); + + val = readl(&phy0_ctrl->phy_con26); + val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); + val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); + writel(val, &phy0_ctrl->phy_con26); + + val = readl(&phy1_ctrl->phy_con26); + val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); + val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); + writel(val, &phy1_ctrl->phy_con26); + + /* + * Set Driver strength for CK, CKE, CS & CA to 0x7 + * Set Driver strength for Data Slice 0~3 to 0x7 + */ + val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) | + (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); + val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | + (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET); + writel(val, &phy0_ctrl->phy_con39); + writel(val, &phy1_ctrl->phy_con39); + + /* ZQ Calibration */ + if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, + &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17)) + return SETUP_ERR_ZQ_CALIBRATION_FAILURE; + + clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN); + clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN); + + /* DQ Signal */ + val = readl(&phy0_ctrl->phy_con14); + val |= mem->phy0_pulld_dqs; + writel(val, &phy0_ctrl->phy_con14); + val = readl(&phy1_ctrl->phy_con14); + val |= mem->phy1_pulld_dqs; + writel(val, &phy1_ctrl->phy_con14); + + val = MEM_TERM_EN | PHY_TERM_EN; + writel(val, &drex0->phycontrol0); + writel(val, &drex1->phycontrol0); + + writel(mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &drex0->concontrol); + writel(mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &drex1->concontrol); + + do { + val = readl(&drex0->phystatus); + } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); + do { + val = readl(&drex1->phystatus); + } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); + + clrbits_le32(&drex0->concontrol, DFI_INIT_START); + clrbits_le32(&drex1->concontrol, DFI_INIT_START); + + update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); + update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); + + /* + * Set Base Address: + * 0x2000_0000 ~ 0x5FFF_FFFF + * 0x6000_0000 ~ 0x9FFF_FFFF + */ + /* MEMBASECONFIG0 */ + val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) | + DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK); + writel(val, &tzasc0->membaseconfig0); + writel(val, &tzasc1->membaseconfig0); + + /* MEMBASECONFIG1 */ + val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) | + DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK); + writel(val, &tzasc0->membaseconfig1); + writel(val, &tzasc1->membaseconfig1); + + /* + * Memory Channel Inteleaving Size + * Ares Channel interleaving = 128 bytes + */ + /* MEMCONFIG0/1 */ + writel(mem->memconfig, &tzasc0->memconfig0); + writel(mem->memconfig, &tzasc1->memconfig0); + writel(mem->memconfig, &tzasc0->memconfig1); + writel(mem->memconfig, &tzasc1->memconfig1); + + /* Precharge Configuration */ + writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, + &drex0->prechconfig0); + writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, + &drex1->prechconfig0); + + /* + * TimingRow, TimingData, TimingPower and Timingaref + * values as per Memory AC parameters + */ + writel(mem->timing_ref, &drex0->timingref); + writel(mem->timing_ref, &drex1->timingref); + writel(mem->timing_row, &drex0->timingrow0); + writel(mem->timing_row, &drex1->timingrow0); + writel(mem->timing_data, &drex0->timingdata0); + writel(mem->timing_data, &drex1->timingdata0); + writel(mem->timing_power, &drex0->timingpower0); + writel(mem->timing_power, &drex1->timingpower0); + + if (reset) { + /* + * Send NOP, MRS and ZQINIT commands + * Sending MRS command will reset the DRAM. We should not be + * reseting the DRAM after resume, this will lead to memory + * corruption as DRAM content is lost after DRAM reset + */ + dmc_config_mrs(mem, &drex0->directcmd); + dmc_config_mrs(mem, &drex1->directcmd); + } + + /* + * Get PHY_CON13 from both phys. Gate CLKM around reading since + * PHY_CON13 is glitchy when CLKM is running. We're paranoid and + * wait until we get a "fine lock", though a coarse lock is probably + * OK (we only use the coarse numbers below). We try to gate the + * clock for as short a time as possible in case SDRAM is somehow + * sensitive. sdelay(10) in the loop is arbitrary to make sure + * there is some time for PHY_CON13 to get updated. In practice + * no delay appears to be needed. + */ + val = readl(&clk->gate_bus_cdrex); + while (true) { + writel(val & ~0x1, &clk->gate_bus_cdrex); + lock0_info = readl(&phy0_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + while (true) { + writel(val & ~0x2, &clk->gate_bus_cdrex); + lock1_info = readl(&phy1_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + + if (!reset) { + /* + * During Suspend-Resume & S/W-Reset, as soon as PMU releases + * pad retention, CKE goes high. This causes memory contents + * not to be retained during DRAM initialization. Therfore, + * there is a new control register(0x100431e8[28]) which lets us + * release pad retention and retain the memory content until the + * initialization is complete. + */ + writel(PAD_RETENTION_DRAM_COREBLK_VAL, + &power->pad_retention_dram_coreblk_option); + do { + val = readl(&power->pad_retention_dram_status); + } while (val != 0x1); + + /* + * CKE PAD retention disables DRAM self-refresh mode. + * Send auto refresh command for DRAM refresh. + */ + for (i = 0; i < 128; i++) { + for (chip = 0; chip < mem->chips_to_configure; chip++) { + writel(DIRECT_CMD_REFA | + (chip << DIRECT_CMD_CHIP_SHIFT), + &drex0->directcmd); + writel(DIRECT_CMD_REFA | + (chip << DIRECT_CMD_CHIP_SHIFT), + &drex1->directcmd); + } + } + } + + if (mem->gate_leveling_enable) { + writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0); + writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0); + + setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN); + setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN); + + val = PHY_CON2_RESET_VAL; + val |= INIT_DESKEW_EN; + writel(val, &phy0_ctrl->phy_con2); + writel(val, &phy1_ctrl->phy_con2); + + val = readl(&phy0_ctrl->phy_con1); + val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); + writel(val, &phy0_ctrl->phy_con1); + + val = readl(&phy1_ctrl->phy_con1); + val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); + writel(val, &phy1_ctrl->phy_con1); + + n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_r = readl(&phy0_ctrl->phy_con12); + n_lock_r &= ~CTRL_DLL_ON; + n_lock_r |= n_lock_w_phy0; + writel(n_lock_r, &phy0_ctrl->phy_con12); + + n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_r = readl(&phy1_ctrl->phy_con12); + n_lock_r &= ~CTRL_DLL_ON; + n_lock_r |= n_lock_w_phy1; + writel(n_lock_r, &phy1_ctrl->phy_con12); + + val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; + for (chip = 0; chip < mem->chips_to_configure; chip++) { + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex0->directcmd); + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex1->directcmd); + } + + setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN); + setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN); + + setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE); + setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE); + + val = readl(&phy0_ctrl->phy_con1); + val &= ~(CTRL_GATEDURADJ_MASK); + writel(val, &phy0_ctrl->phy_con1); + + val = readl(&phy1_ctrl->phy_con1); + val &= ~(CTRL_GATEDURADJ_MASK); + writel(val, &phy1_ctrl->phy_con1); + + writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config); + i = TIMEOUT_US; + while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) != + RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take to + * timeout + */ + sdelay(100); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config); + + writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config); + i = TIMEOUT_US; + while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) != + RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take to + * timeout + */ + sdelay(100); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config); + + writel(0, &phy0_ctrl->phy_con14); + writel(0, &phy1_ctrl->phy_con14); + + val = (0x3 << DIRECT_CMD_BANK_SHIFT); + for (chip = 0; chip < mem->chips_to_configure; chip++) { + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex0->directcmd); + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex1->directcmd); + } + + /* Common Settings for Leveling */ + val = PHY_CON12_RESET_VAL; + writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12); + writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12); + + setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN); + setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN); + } + + /* + * Do software read leveling + * + * Do this before we turn on auto refresh since the auto refresh can + * be in conflict with the resync operation that's part of setting + * read leveling. + */ + if (!reset) { + /* restore calibrated value after resume */ + dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1)); + dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2)); + } else { + software_find_read_offset(phy0_ctrl, 0, + CTRL_LOCK_COARSE(lock0_info)); + software_find_read_offset(phy1_ctrl, 1, + CTRL_LOCK_COARSE(lock1_info)); + /* save calibrated value to restore after resume */ + writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1); + writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2); + } + + /* Send PALL command */ + dmc_config_prech(mem, &drex0->directcmd); + dmc_config_prech(mem, &drex1->directcmd); + + writel(mem->memcontrol, &drex0->memcontrol); + writel(mem->memcontrol, &drex1->memcontrol); + + /* + * Set DMC Concontrol: Enable auto-refresh counter, provide + * read data fetch cycles and enable DREX auto set powerdown + * for input buffer of I/O in none read memory state. + */ + writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| + DMC_CONCONTROL_IO_PD_CON(0x2), + &drex0->concontrol); + writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| + DMC_CONCONTROL_IO_PD_CON(0x2), + &drex1->concontrol); + + /* + * Enable Clock Gating Control for DMC + * this saves around 25 mw dmc power as compared to the power + * consumption without these bits enabled + */ + setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); + setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); + + /* + * As per Exynos5800 UM ver 0.00 section 17.13.2.1 + * CONCONTROL register bit 3 [update_mode], Exynos5800 does not + * support the PHY initiated update. And it is recommended to set + * this field to 1'b1 during initialization + * + * When we apply PHY-initiated mode, DLL lock value is determined + * once at DMC init time and not updated later when we change the MIF + * voltage based on ASV group in kernel. Applying MC-initiated mode + * makes sure that DLL tracing is ON so that silicon is able to + * compensate the voltage variation. + */ + val = readl(&drex0->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex0->concontrol); + val = readl(&drex1->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex1->concontrol); + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 696b386759..2eea48a0cc 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -12,42 +12,16 @@ #include #include -/* APLL_CON1 */ -#define APLL_CON1_VAL (0x00203800) - -/* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x00203800) - -/* CPLL_CON1 */ -#define CPLL_CON1_VAL (0x00203800) - -/* GPLL_CON1 */ -#define GPLL_CON1_VAL (0x00203800) - -/* EPLL_CON1, CON2 */ -#define EPLL_CON1_VAL 0x00000000 -#define EPLL_CON2_VAL 0x00000080 - -/* VPLL_CON1, CON2 */ -#define VPLL_CON1_VAL 0x00000000 -#define VPLL_CON2_VAL 0x00000080 +#define NOT_AVAILABLE 0 +#define DATA_MASK 0xFFFFF -/* BPLL_CON1 */ -#define BPLL_CON1_VAL 0x00203800 +#define ENABLE_BIT 0x1 +#define DISABLE_BIT 0x0 +#define CA_SWAP_EN (1 << 0) /* Set PLL */ #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) -/* CLK_SRC_CPU */ -/* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 0 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 - -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ - | (MUX_CPU_SEL << 16) \ - | (MUX_APLL_SEL)) - /* MEMCONTROL register bit fields */ #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0) #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1) @@ -78,6 +52,7 @@ /* MEMCONFIG0 register bit fields */ #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12) #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8) #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4) #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4) @@ -90,6 +65,17 @@ DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \ ) +/* + * As we use channel interleaving, therefore value of the base address + * register must be set as half of the bus base address + * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so + * we need to set half 0x10 to the membaseconfigx registers + * see exynos5420 UM section 17.17.3.21 for more. + */ +#define DMC_CHIP_BASE_0 0x10 +#define DMC_CHIP_BASE_1 0x50 +#define DMC_CHIP_MASK 0x7C0 + #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80) @@ -113,29 +99,24 @@ /* COJCONTROL register bit fields */ #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3) +#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3) #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5) +#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5) #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8) #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8) #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12) #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) -/* CLK_DIV_CPU0_VAL */ -#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ - | (APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (ACP_RATIO << 8) \ - | (CPUD_RATIO << 4) \ - | (ARM_RATIO)) +#define DMC_CONCONTROL_VAL 0x1FFF2101 +#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \ + | DMC_CONCONTROL_AREF_EN_ENABLE \ + | DMC_CONCONTROL_IO_PD_CON_ENABLE -/* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x66666 -#define CLK_DIV_FSYS0_VAL 0x0BB00000 +#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6) -/* CLK_DIV_CPU1 */ +/* CLK_DIV_CPU1 */ #define HPM_RATIO 0x2 #define COPY_RATIO 0x0 @@ -164,10 +145,371 @@ /* CLK_DIV_SYSLFT */ #define CLK_DIV_SYSLFT_VAL 0x00000311 +#define MUX_APLL_SEL_MASK (1 << 0) +#define MUX_MPLL_SEL_MASK (1 << 8) +#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) +#define MUX_CPLL_SEL_MASK (1 << 8) +#define MUX_EPLL_SEL_MASK (1 << 12) +#define MUX_VPLL_SEL_MASK (1 << 16) +#define MUX_GPLL_SEL_MASK (1 << 28) +#define MUX_BPLL_SEL_MASK (1 << 0) +#define MUX_HPM_SEL_MASK (1 << 20) +#define HPM_SEL_SCLK_MPLL (1 << 21) +#define PLL_LOCKED (1 << 29) +#define APLL_CON0_LOCKED (1 << 29) +#define MPLL_CON0_LOCKED (1 << 29) +#define BPLL_CON0_LOCKED (1 << 29) +#define CPLL_CON0_LOCKED (1 << 29) +#define EPLL_CON0_LOCKED (1 << 29) +#define GPLL_CON0_LOCKED (1 << 29) +#define VPLL_CON0_LOCKED (1 << 29) +#define CLK_REG_DISABLE 0x0 +#define TOP2_VAL 0x0110000 + +/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ +#define SPI0_ISP_SEL 6 +#define SPI1_ISP_SEL 6 +#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ + | (SPI0_ISP_SEL << 0) + +/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ +#define SPI0_ISP_RATIO 0xf +#define SPI1_ISP_RATIO 0xf +#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \ + | (SPI0_ISP_RATIO << 0) + +/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO_MASK 0xf +#define MMC2_RATIO_VAL 0x3 +#define MMC2_RATIO_OFFSET 0 + +#define MMC2_PRE_RATIO_MASK 0xff +#define MMC2_PRE_RATIO_VAL 0x9 +#define MMC2_PRE_RATIO_OFFSET 8 + +#define MMC3_RATIO_MASK 0xf +#define MMC3_RATIO_VAL 0x1 +#define MMC3_RATIO_OFFSET 16 + +#define MMC3_PRE_RATIO_MASK 0xff +#define MMC3_PRE_RATIO_VAL 0x0 +#define MMC3_PRE_RATIO_OFFSET 24 + +/* CLK_SRC_LEX */ +#define CLK_SRC_LEX_VAL 0x0 + +/* CLK_DIV_LEX */ +#define CLK_DIV_LEX_VAL 0x10 + +/* CLK_DIV_R0X */ +#define CLK_DIV_R0X_VAL 0x10 + +/* CLK_DIV_L0X */ +#define CLK_DIV_R1X_VAL 0x10 + +/* CLK_DIV_ISP2 */ +#define CLK_DIV_ISP2_VAL 0x1 + +/* CLK_SRC_KFC */ +#define SRC_KFC_HPM_SEL (1 << 15) + +/* CLK_SRC_KFC */ +#define CLK_SRC_KFC_VAL 0x00008001 + +/* CLK_DIV_KFC */ +#define CLK_DIV_KFC_VAL 0x03300110 + +/* CLK_DIV2_RATIO */ +#define CLK_DIV2_RATIO 0x10111150 + +/* CLK_DIV4_RATIO */ +#define CLK_DIV4_RATIO 0x00000003 + +/* CLK_DIV_G2D */ +#define CLK_DIV_G2D 0x00000010 + +/* + * DIV_DISP1_0 + * For DP, divisor should be 2 + */ +#define CLK_DIV_DISP1_0_FIMD1 (2 << 0) + +/* CLK_GATE_IP_DISP1 */ +#define CLK_GATE_DP1_ALLOW (1 << 4) + +/* AUDIO CLK SEL */ +#define AUDIO0_SEL_EPLL (0x6 << 28) +#define AUDIO0_RATIO 0x5 +#define PCM0_RATIO 0x3 +#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20) + +/* CLK_SRC_CDREX */ +#define MUX_MCLK_CDR_MSPLL (1 << 4) +#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) +#define BPLL_SEL_MASK 0x7 +#define FOUTBPLL 2 + +#define DDR3PHY_CTRL_PHY_RESET (1 << 0) +#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) + +#define PHY_CON0_RESET_VAL 0x17020a40 +#define P0_CMD_EN (1 << 14) +#define BYTE_RDLVL_EN (1 << 13) +#define CTRL_SHGATE (1 << 8) + +#define PHY_CON1_RESET_VAL 0x09210100 +#define RDLVL_PASS_ADJ_VAL 0x6 +#define RDLVL_PASS_ADJ_OFFSET 16 +#define CTRL_GATEDURADJ_MASK (0xf << 20) +#define READ_LEVELLING_DDR3 0x0100 + +#define PHY_CON2_RESET_VAL 0x00010004 +#define INIT_DESKEW_EN (1 << 6) +#define DLL_DESKEW_EN (1 << 12) +#define RDLVL_GATE_EN (1 << 24) +#define RDLVL_EN (1 << 25) +#define RDLVL_INCR_ADJ (0x1 << 16) + +/* DREX_PAUSE */ +#define DREX_PAUSE_EN (1 << 0) + +#define BYPASS_EN (1 << 22) + +/* MEMMORY VAL */ +#define PHY_CON0_VAL 0x17021A00 + +#define PHY_CON12_RESET_VAL 0x10100070 +#define PHY_CON12_VAL 0x10107F50 +#define CTRL_START (1 << 6) +#define CTRL_DLL_ON (1 << 5) +#define CTRL_LOCK_COARSE_OFFSET 10 +#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET) +#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \ + CTRL_LOCK_COARSE_OFFSET) +#define CTRL_FORCE_MASK (0x7F << 8) +#define CTRL_FINE_LOCKED 0x7 + +#define CTRL_OFFSETD_RESET_VAL 0x8 +#define CTRL_OFFSETD_VAL 0x7F + +#define CTRL_OFFSETR0 0x7F +#define CTRL_OFFSETR1 0x7F +#define CTRL_OFFSETR2 0x7F +#define CTRL_OFFSETR3 0x7F +#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \ + CTRL_OFFSETR1 << 8 | \ + CTRL_OFFSETR2 << 16 | \ + CTRL_OFFSETR3 << 24) +#define PHY_CON4_RESET_VAL 0x08080808 + +#define CTRL_OFFSETW0 0x7F +#define CTRL_OFFSETW1 0x7F +#define CTRL_OFFSETW2 0x7F +#define CTRL_OFFSETW3 0x7F +#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \ + CTRL_OFFSETW1 << 8 | \ + CTRL_OFFSETW2 << 16 | \ + CTRL_OFFSETW3 << 24) +#define PHY_CON6_RESET_VAL 0x08080808 + +#define PHY_CON14_RESET_VAL 0x001F0000 +#define CTRL_PULLD_DQS 0xF +#define CTRL_PULLD_DQS_OFFSET 0 + +/* ZQ Configurations */ +#define PHY_CON16_RESET_VAL 0x08000304 + +#define ZQ_CLK_EN (1 << 27) +#define ZQ_CLK_DIV_EN (1 << 18) +#define ZQ_MANUAL_STR (1 << 1) +#define ZQ_DONE (1 << 0) +#define ZQ_MODE_DDS_OFFSET 24 + +#define CTRL_RDLVL_GATE_ENABLE 1 +#define CTRL_RDLVL_GATE_DISABLE 0 +#define CTRL_RDLVL_DATA_ENABLE 2 + +/* Direct Command */ +#define DIRECT_CMD_NOP 0x07000000 +#define DIRECT_CMD_PALL 0x01000000 +#define DIRECT_CMD_ZQINIT 0x0a000000 +#define DIRECT_CMD_CHANNEL_SHIFT 28 +#define DIRECT_CMD_CHIP_SHIFT 20 +#define DIRECT_CMD_BANK_SHIFT 16 +#define DIRECT_CMD_REFA (5 << 24) +#define DIRECT_CMD_MRS1 0x71C00 +#define DIRECT_CMD_MRS2 0x10BFC +#define DIRECT_CMD_MRS3 0x0050C +#define DIRECT_CMD_MRS4 0x00868 +#define DIRECT_CMD_MRS5 0x00C04 + +/* Drive Strength */ +#define IMPEDANCE_48_OHM 4 +#define IMPEDANCE_40_OHM 5 +#define IMPEDANCE_34_OHM 6 +#define IMPEDANCE_30_OHM 7 +#define PHY_CON39_VAL_48_OHM 0x09240924 +#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D +#define PHY_CON39_VAL_34_OHM 0x0DB60DB6 +#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF + +#define CTRL_BSTLEN_OFFSET 8 +#define CTRL_RDLAT_OFFSET 0 + +#define CMD_DEFAULT_LPDDR3 0xF +#define CMD_DEFUALT_OFFSET 0 +#define T_WRDATA_EN 0x7 +#define T_WRDATA_EN_DDR3 0x8 +#define T_WRDATA_EN_OFFSET 16 +#define T_WRDATA_EN_MASK 0x1f + +#define PHY_CON31_VAL 0x0C183060 +#define PHY_CON32_VAL 0x60C18306 +#define PHY_CON33_VAL 0x00000030 + +#define PHY_CON31_RESET_VAL 0x0 +#define PHY_CON32_RESET_VAL 0x0 +#define PHY_CON33_RESET_VAL 0x0 + +#define SL_DLL_DYN_CON_EN (1 << 1) +#define FP_RESYNC (1 << 3) +#define CTRL_START (1 << 6) + +#define DMC_AREF_EN (1 << 5) +#define DMC_CONCONTROL_EMPTY (1 << 8) +#define DFI_INIT_START (1 << 28) + +#define DMC_MEMCONTROL_VAL 0x00312700 +#define CLK_STOP_EN (1 << 0) +#define DPWRDN_EN (1 << 1) +#define DSREF_EN (1 << 5) + +#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0 +#define MEMBASECONFIG_CHIP_MASK_OFFSET 0 +#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20 +#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40 +#define CHIP_BASE_OFFSET 16 + +#define MEMCONFIG_VAL 0x1323 +#define PRECHCONFIG_DEFAULT_VAL 0xFF000000 +#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF + +#define TIMINGAREF_VAL 0x5d +#define TIMINGROW_VAL 0x345A8692 +#define TIMINGDATA_VAL 0x3630065C +#define TIMINGPOWER_VAL 0x50380336 +#define DFI_INIT_COMPLETE (1 << 3) + +#define BRBRSVCONTROL_VAL 0x00000033 +#define BRBRSVCONFIG_VAL 0x88778877 + +/* Clock Gating Control (CGCONTROL) register */ +#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */ +#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */ +#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */ +#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */ +#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \ + BUSIF_WR_CG_EN | BUSIF_RD_CG_EN) + +/* DMC PHY Control0 register */ +#define PHY_CONTROL0_RESET_VAL 0x0 +#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ +#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ +#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ +#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ + +/* Driver strength for CK, CKE, CS & CA */ +#define IMP_OUTPUT_DRV_40_OHM 0x5 +#define IMP_OUTPUT_DRV_30_OHM 0x7 +#define DA_3_DS_OFFSET 25 +#define DA_2_DS_OFFSET 22 +#define DA_1_DS_OFFSET 19 +#define DA_0_DS_OFFSET 16 +#define CA_CK_DRVR_DS_OFFSET 9 +#define CA_CKE_DRVR_DS_OFFSET 6 +#define CA_CS_DRVR_DS_OFFSET 3 +#define CA_ADR_DRVR_DS_OFFSET 0 + +#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 +#define PHY_CON42_CTRL_RDLAT_SHIFT 0 + +/* + * Definitions that differ with SoC's. + * Below is the part defining macros for Exynos5250. + * Else part introduces macros for Exynos5420. + */ +#ifndef CONFIG_EXYNOS5420 + +/* APLL_CON1 */ +#define APLL_CON1_VAL (0x00203800) + +/* MPLL_CON1 */ +#define MPLL_CON1_VAL (0x00203800) + +/* CPLL_CON1 */ +#define CPLL_CON1_VAL (0x00203800) + +/* DPLL_CON1 */ +#define DPLL_CON1_VAL (NOT_AVAILABLE) + +/* GPLL_CON1 */ +#define GPLL_CON1_VAL (0x00203800) + +/* EPLL_CON1, CON2 */ +#define EPLL_CON1_VAL 0x00000000 +#define EPLL_CON2_VAL 0x00000080 + +/* VPLL_CON1, CON2 */ +#define VPLL_CON1_VAL 0x00000000 +#define VPLL_CON2_VAL 0x00000080 + +/* RPLL_CON1, CON2 */ +#define RPLL_CON1_VAL NOT_AVAILABLE +#define RPLL_CON2_VAL NOT_AVAILABLE + +/* BPLL_CON1 */ +#define BPLL_CON1_VAL 0x00203800 + +/* SPLL_CON1 */ +#define SPLL_CON1_VAL NOT_AVAILABLE + +/* IPLL_CON1 */ +#define IPLL_CON1_VAL NOT_AVAILABLE + +/* KPLL_CON1 */ +#define KPLL_CON1_VAL NOT_AVAILABLE + +/* CLK_SRC_ISP */ +#define CLK_SRC_ISP_VAL NOT_AVAILABLE +#define CLK_DIV_ISP0_VAL 0x31 +#define CLK_DIV_ISP1_VAL 0x0 + +/* CLK_FSYS */ +#define CLK_SRC_FSYS0_VAL 0x66666 +#define CLK_DIV_FSYS0_VAL 0x0BB00000 +#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE +#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE + +/* CLK_SRC_CPU */ +/* 0 = MOUTAPLL, 1 = SCLKMPLL */ +#define MUX_HPM_SEL 0 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1 + +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ + | (MUX_CPU_SEL << 16) \ + | (MUX_APLL_SEL)) + /* CLK_SRC_CDREX */ #define CLK_SRC_CDREX_VAL 0x1 /* CLK_DIV_CDREX */ +#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE +#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE + +/* CLK_DIV_CPU0_VAL */ +#define CLK_DIV_CPU0_VAL NOT_AVAILABLE + #define MCLK_CDREX2_RATIO 0x0 #define ACLK_EFCON_RATIO 0x1 #define MCLK_DPHY_RATIO 0x1 @@ -247,6 +589,11 @@ | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) +#define CLK_SRC_TOP4_VAL NOT_AVAILABLE +#define CLK_SRC_TOP5_VAL NOT_AVAILABLE +#define CLK_SRC_TOP6_VAL NOT_AVAILABLE +#define CLK_SRC_TOP7_VAL NOT_AVAILABLE + /* CLK_DIV_TOP0 */ #define ACLK_300_DISP1_RATIO 0x2 #define ACLK_400_G3D_RATIO 0x0 @@ -279,40 +626,11 @@ | (ACLK_400_IOP_RATIO << 16) \ | (ACLK_300_GSCL_RATIO << 12)) -/* APLL_LOCK */ -#define APLL_LOCK_VAL (0x546) -/* MPLL_LOCK */ -#define MPLL_LOCK_VAL (0x546) -/* CPLL_LOCK */ -#define CPLL_LOCK_VAL (0x546) -/* GPLL_LOCK */ -#define GPLL_LOCK_VAL (0x546) -/* EPLL_LOCK */ -#define EPLL_LOCK_VAL (0x3A98) -/* VPLL_LOCK */ -#define VPLL_LOCK_VAL (0x3A98) -/* BPLL_LOCK */ -#define BPLL_LOCK_VAL (0x546) +#define CLK_DIV_TOP2_VAL NOT_AVAILABLE -#define MUX_APLL_SEL_MASK (1 << 0) -#define MUX_MPLL_SEL_MASK (1 << 8) -#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) -#define MUX_CPLL_SEL_MASK (1 << 8) -#define MUX_EPLL_SEL_MASK (1 << 12) -#define MUX_VPLL_SEL_MASK (1 << 16) -#define MUX_GPLL_SEL_MASK (1 << 28) -#define MUX_BPLL_SEL_MASK (1 << 0) -#define MUX_HPM_SEL_MASK (1 << 20) -#define HPM_SEL_SCLK_MPLL (1 << 21) -#define APLL_CON0_LOCKED (1 << 29) -#define MPLL_CON0_LOCKED (1 << 29) -#define BPLL_CON0_LOCKED (1 << 29) -#define CPLL_CON0_LOCKED (1 << 29) -#define EPLL_CON0_LOCKED (1 << 29) -#define GPLL_CON0_LOCKED (1 << 29) -#define VPLL_CON0_LOCKED (1 << 29) -#define CLK_REG_DISABLE 0x0 -#define TOP2_VAL 0x0110000 +/* PLL Lock Value Factor */ +#define PLL_LOCK_FACTOR 250 +#define PLL_X_LOCK_FACTOR 3000 /* CLK_SRC_PERIC0 */ #define PWM_SEL 6 @@ -336,18 +654,6 @@ | (SPI1_SEL << 20) \ | (SPI0_SEL << 16)) -/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ -#define SPI0_ISP_SEL 6 -#define SPI1_ISP_SEL 6 -#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ - | (SPI0_ISP_SEL << 0) - -/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ -#define SPI0_ISP_RATIO 0xf -#define SPI1_ISP_RATIO 0xf -#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \ - | (SPI0_ISP_RATIO << 0) - /* CLK_DIV_PERIL0 */ #define UART5_RATIO 7 #define UART4_RATIO 7 @@ -380,105 +686,201 @@ #define PWM_RATIO 8 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) -/* CLK_DIV_FSYS2 */ -#define MMC2_RATIO_MASK 0xf -#define MMC2_RATIO_VAL 0x3 -#define MMC2_RATIO_OFFSET 0 -#define MMC2_PRE_RATIO_MASK 0xff -#define MMC2_PRE_RATIO_VAL 0x9 -#define MMC2_PRE_RATIO_OFFSET 8 +/* CLK_DIV_PERIC4 */ +#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE -#define MMC3_RATIO_MASK 0xf -#define MMC3_RATIO_VAL 0x1 -#define MMC3_RATIO_OFFSET 16 +/* CLK_SRC_DISP1_0 */ +#define CLK_SRC_DISP1_0_VAL 0x6 +#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE -#define MMC3_PRE_RATIO_MASK 0xff -#define MMC3_PRE_RATIO_VAL 0x0 -#define MMC3_PRE_RATIO_OFFSET 24 +#define APLL_FOUT (1 << 0) +#define KPLL_FOUT NOT_AVAILABLE -/* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE -/* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#else +#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 -/* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +/* APLL_CON1 */ +#define APLL_CON1_VAL (0x0020F300) -/* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +/* MPLL_CON1 */ +#define MPLL_CON1_VAL (0x0020F300) -/* CLK_DIV_ISP0 */ -#define CLK_DIV_ISP0_VAL 0x31 -/* CLK_DIV_ISP1 */ -#define CLK_DIV_ISP1_VAL 0x0 +/* CPLL_CON1 */ +#define CPLL_CON1_VAL 0x0020f300 -/* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +/* DPLL_CON1 */ +#define DPLL_CON1_VAL (0x0020F300) -/* CLK_SRC_DISP1_0 */ -#define CLK_SRC_DISP1_0_VAL 0x6 +/* GPLL_CON1 */ +#define GPLL_CON1_VAL (NOT_AVAILABLE) -/* - * DIV_DISP1_0 - * For DP, divisor should be 2 - */ -#define CLK_DIV_DISP1_0_FIMD1 (2 << 0) -/* CLK_GATE_IP_DISP1 */ -#define CLK_GATE_DP1_ALLOW (1 << 4) +/* EPLL_CON1, CON2 */ +#define EPLL_CON1_VAL 0x00000000 +#define EPLL_CON2_VAL 0x00000080 -#define DDR3PHY_CTRL_PHY_RESET (1 << 0) -#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) +/* VPLL_CON1, CON2 */ +#define VPLL_CON1_VAL 0x0020f300 +#define VPLL_CON2_VAL NOT_AVAILABLE -#define PHY_CON0_RESET_VAL 0x17020a40 -#define P0_CMD_EN (1 << 14) -#define BYTE_RDLVL_EN (1 << 13) -#define CTRL_SHGATE (1 << 8) +/* RPLL_CON1, CON2 */ +#define RPLL_CON1_VAL 0x00000000 +#define RPLL_CON2_VAL 0x00000080 -#define PHY_CON1_RESET_VAL 0x09210100 -#define CTRL_GATEDURADJ_MASK (0xf << 20) +/* BPLL_CON1 */ +#define BPLL_CON1_VAL 0x0020f300 -#define PHY_CON2_RESET_VAL 0x00010004 -#define INIT_DESKEW_EN (1 << 6) -#define RDLVL_GATE_EN (1 << 24) +/* SPLL_CON1 */ +#define SPLL_CON1_VAL 0x0020f300 -/*ZQ Configurations */ -#define PHY_CON16_RESET_VAL 0x08000304 +/* IPLL_CON1 */ +#define IPLL_CON1_VAL 0x00000080 -#define ZQ_CLK_DIV_EN (1 << 18) -#define ZQ_MANUAL_STR (1 << 1) -#define ZQ_DONE (1 << 0) +/* KPLL_CON1 */ +#define KPLL_CON1_VAL 0x200000 -#define CTRL_RDLVL_GATE_ENABLE 1 -#define CTRL_RDLVL_GATE_DISABLE 1 +/* CLK_SRC_ISP */ +#define CLK_SRC_ISP_VAL 0x33366000 +#define CLK_DIV_ISP0_VAL 0x13131300 +#define CLK_DIV_ISP1_VAL 0xbb110202 -/* Direct Command */ -#define DIRECT_CMD_NOP 0x07000000 -#define DIRECT_CMD_PALL 0x01000000 -#define DIRECT_CMD_ZQINIT 0x0a000000 -#define DIRECT_CMD_CHANNEL_SHIFT 28 -#define DIRECT_CMD_CHIP_SHIFT 20 -/* DMC PHY Control0 register */ -#define PHY_CONTROL0_RESET_VAL 0x0 -#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ -#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ -#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ -#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ +/* CLK_FSYS */ +#define CLK_SRC_FSYS0_VAL 0x33033300 +#define CLK_DIV_FSYS0_VAL 0x0 +#define CLK_DIV_FSYS1_VAL 0x04f13c4f +#define CLK_DIV_FSYS2_VAL 0x041d0000 + +/* CLK_SRC_CPU */ +/* 0 = MOUTAPLL, 1 = SCLKMPLL */ +#define MUX_HPM_SEL 1 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1 -/* Driver strength for CK, CKE, CS & CA */ -#define IMP_OUTPUT_DRV_40_OHM 0x5 -#define IMP_OUTPUT_DRV_30_OHM 0x7 -#define CA_CK_DRVR_DS_OFFSET 9 -#define CA_CKE_DRVR_DS_OFFSET 6 -#define CA_CS_DRVR_DS_OFFSET 3 -#define CA_ADR_DRVR_DS_OFFSET 0 +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ + | (MUX_CPU_SEL << 16) \ + | (MUX_APLL_SEL)) -#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 -#define PHY_CON42_CTRL_RDLAT_SHIFT 0 +/* CLK_SRC_CDREX */ +#define CLK_SRC_CDREX_VAL 0x00000011 + +/* CLK_DIV_CDREX */ +#define CLK_DIV_CDREX0_VAL 0x30010100 +#define CLK_DIV_CDREX1_VAL 0x300 + +#define CLK_DIV_CDREX_VAL 0x17010100 + +/* CLK_DIV_CPU0_VAL */ +#define CLK_DIV_CPU0_VAL 0x01440020 + +/* CLK_SRC_TOP */ +#define CLK_SRC_TOP0_VAL 0x12221222 +#define CLK_SRC_TOP1_VAL 0x00100200 +#define CLK_SRC_TOP2_VAL 0x11101000 +#define CLK_SRC_TOP3_VAL 0x11111111 +#define CLK_SRC_TOP4_VAL 0x11110111 +#define CLK_SRC_TOP5_VAL 0x11111101 +#define CLK_SRC_TOP6_VAL 0x11110111 +#define CLK_SRC_TOP7_VAL 0x00022200 + +/* CLK_DIV_TOP */ +#define CLK_DIV_TOP0_VAL 0x23712311 +#define CLK_DIV_TOP1_VAL 0x13100B00 +#define CLK_DIV_TOP2_VAL 0x11101100 + +/* PLL Lock Value Factor */ +#define PLL_LOCK_FACTOR 200 +#define PLL_X_LOCK_FACTOR 3000 + +/* CLK_SRC_PERIC0 */ +#define SPDIF_SEL 1 +#define PWM_SEL 3 +#define UART4_SEL 3 +#define UART3_SEL 3 +#define UART2_SEL 3 +#define UART1_SEL 3 +#define UART0_SEL 3 +/* SRC_CLOCK = SCLK_RPLL */ +#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \ + | (PWM_SEL << 24) \ + | (UART4_SEL << 20) \ + | (UART3_SEL << 16) \ + | (UART2_SEL << 12) \ + | (UART1_SEL << 8) \ + | (UART0_SEL << 4)) + +/* CLK_SRC_PERIC1 */ +/* SRC_CLOCK = SCLK_EPLL */ +#define SPI0_SEL 6 +#define SPI1_SEL 6 +#define SPI2_SEL 6 +#define AUDIO0_SEL 6 +#define AUDIO1_SEL 6 +#define AUDIO2_SEL 6 +#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \ + | (SPI1_SEL << 24) \ + | (SPI0_SEL << 20) \ + | (AUDIO2_SEL << 16) \ + | (AUDIO2_SEL << 12) \ + | (AUDIO2_SEL << 8)) + +/* CLK_DIV_PERIC0 */ +#define PWM_RATIO 8 +#define UART4_RATIO 9 +#define UART3_RATIO 9 +#define UART2_RATIO 9 +#define UART1_RATIO 9 +#define UART0_RATIO 9 + +#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \ + | (UART4_RATIO << 24) \ + | (UART3_RATIO << 20) \ + | (UART2_RATIO << 16) \ + | (UART1_RATIO << 12) \ + | (UART0_RATIO << 8)) +/* CLK_DIV_PERIC1 */ +#define SPI2_RATIO 0x1 +#define SPI1_RATIO 0x1 +#define SPI0_RATIO 0x1 +#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \ + | (SPI1_RATIO << 24) \ + | (SPI0_RATIO << 20)) + +/* CLK_DIV_PERIC2 */ +#define PCM2_RATIO 0x3 +#define PCM1_RATIO 0x3 +#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \ + | (PCM1_RATIO << 16)) + +/* CLK_DIV_PERIC3 */ +#define AUDIO2_RATIO 0x5 +#define AUDIO1_RATIO 0x5 +#define AUDIO0_RATIO 0x5 +#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \ + | (AUDIO1_RATIO << 24) \ + | (AUDIO0_RATIO << 20)) + +/* CLK_DIV_PERIC4 */ +#define SPI2_PRE_RATIO 0x2 +#define SPI1_PRE_RATIO 0x2 +#define SPI0_PRE_RATIO 0x2 +#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \ + | (SPI1_PRE_RATIO << 16) \ + | (SPI0_PRE_RATIO << 8)) + +/* CLK_SRC_DISP1_0 */ +#define CLK_SRC_DISP1_0_VAL 0x10666600 +#define CLK_DIV_DISP1_0_VAL 0x01050211 + +#define APLL_FOUT (1 << 0) +#define KPLL_FOUT (1 << 0) + +#define CLK_DIV_CPERI1_VAL 0x3f3f0000 +#endif struct mem_timings; @@ -490,62 +892,53 @@ enum { }; /* - * Memory variant specific initialization code + * Memory variant specific initialization code for DDR3 * - * @param mem Memory timings for this memory type. - * @param mem_iv_size Memory interleaving size is a configurable parameter - * which the DMC uses to decide how to split a memory - * chunk into smaller chunks to support concurrent - * accesses; may vary across boards. + * @param mem Memory timings for this memory type. * @param reset Reset DDR PHY during initialization. * @return 0 if ok, SETUP_ERR_... if there is a problem */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset); +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset); + +/* Memory variant specific initialization code for LPDDR3 */ +void lpddr3_mem_ctrl_init(void); /* * Configure ZQ I/O interface * * @param mem Memory timings for this memory type. - * @param phy0_ctrl Pointer to struct containing PHY0 control reg - * @param phy1_ctrl Pointer to struct containing PHY1 control reg + * @param phy0_con16 Register address for dmc_phy0->phy_con16 + * @param phy1_con16 Register address for dmc_phy1->phy_con16 + * @param phy0_con17 Register address for dmc_phy0->phy_con17 + * @param phy1_con17 Register address for dmc_phy1->phy_con17 * @return 0 if ok, -1 on error */ -int dmc_config_zq(struct mem_timings *mem, - struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl); - +int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16, + uint32_t *phy1_con16, uint32_t *phy0_con17, + uint32_t *phy1_con17); /* * Send NOP and MRS/EMRS Direct commands * * @param mem Memory timings for this memory type. - * @param dmc Pointer to struct of DMC registers + * @param directcmd Register address for dmc_phy->directcmd */ -void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc); +void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd); /* * Send PALL Direct commands * * @param mem Memory timings for this memory type. - * @param dmc Pointer to struct of DMC registers - */ -void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc); - -/* - * Configure the memconfig and membaseconfig registers - * - * @param mem Memory timings for this memory type. - * @param exynos5_dmc Pointer to struct of DMC registers + * @param directcmd Register address for dmc_phy->directcmd */ -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc); +void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd); /* * Reset the DLL. This function is common between DDR3 and LPDDR2. * However, the reset value is different. So we are passing a flag * ddr_mode to distinguish between LPDDR2 and DDR3. * - * @param exynos5_dmc Pointer to struct of DMC registers + * @param phycontrol0 Register address for dmc_phy->phycontrol0 * @param ddr_mode Type of DDR memory */ -void update_reset_dll(struct exynos5_dmc *, enum ddr_mode); +void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode); #endif diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index 11fe5b8d04..83e1dcfc1e 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -39,6 +39,7 @@ enum { DO_CLOCKS = 1 << 1, DO_MEM_RESET = 1 << 2, DO_UART = 1 << 3, + DO_POWER = 1 << 4, }; int do_lowlevel_init(void) @@ -60,9 +61,12 @@ int do_lowlevel_init(void) break; default: /* This is a normal boot (not a wake from sleep) */ - actions = DO_CLOCKS | DO_MEM_RESET; + actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER; } + if (actions & DO_POWER) + set_ps_hold_ctrl(); + if (actions & DO_CLOCKS) { system_clock_init(); mem_ctrl_init(actions & DO_MEM_RESET); diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 1b05ebfd7a..be43e224fa 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -7,95 +7,187 @@ #include #include -#include +#include #include #include static void exynos5_uart_config(int peripheral) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->d0; - start = 0; + start = EXYNOS5_GPIO_D00; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5_GPIO_A10; + count = 4; + break; + case PERIPH_ID_UART3: + start = EXYNOS5_GPIO_A14; + count = 2; + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + for (i = start; i < start + count; i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + +static void exynos5420_uart_config(int peripheral) +{ + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + start = EXYNOS5420_GPIO_A00; + count = 4; + break; + case PERIPH_ID_UART1: + start = EXYNOS5420_GPIO_A04; + count = 4; + break; + case PERIPH_ID_UART2: + start = EXYNOS5420_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5420_GPIO_A14; count = 2; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; } + for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static int exynos5_mmc_config(int peripheral, int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank, *bank_ext; - int i, start = 0, gpio_func = 0; + int i, start, start_ext, gpio_func = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio1->c0; - bank_ext = &gpio1->c1; - start = 0; - gpio_func = GPIO_FUNC(0x2); + start = EXYNOS5_GPIO_C00; + start_ext = EXYNOS5_GPIO_C10; + gpio_func = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c2; - bank_ext = NULL; + start = EXYNOS5_GPIO_C20; + start_ext = 0; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c3; - bank_ext = &gpio1->c4; - start = 3; - gpio_func = GPIO_FUNC(0x3); + start = EXYNOS5_GPIO_C30; + start_ext = EXYNOS5_GPIO_C43; + gpio_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c4; - bank_ext = NULL; + start = EXYNOS5_GPIO_C40; + start_ext = 0; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, gpio_func); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = start; i < (start + 2); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + + return 0; +} + +static int exynos5420_mmc_config(int peripheral, int flags) +{ + int i, start = 0, start_ext = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + start = EXYNOS5420_GPIO_C00; + start_ext = EXYNOS5420_GPIO_C30; + break; + case PERIPH_ID_SDMMC1: + start = EXYNOS5420_GPIO_C10; + start_ext = EXYNOS5420_GPIO_D14; + break; + case PERIPH_ID_SDMMC2: + start = EXYNOS5420_GPIO_C20; + start_ext = 0; + break; + default: + start = 0; + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + } + + for (i = start; i < (start + 3); i++) { + /* + * MMC0 is intended to be used for eMMC. The + * card detect pin is used as a VDDEN signal to + * power on the eMMC. The 5420 iROM makes + * this same assumption. + */ + if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { +#ifndef CONFIG_SPL_BUILD + gpio_request(i, "sdmmc0_vdden"); +#endif + gpio_set_value(i, 1); + gpio_cfg_pin(i, S5P_GPIO_OUTPUT); + } else { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -103,8 +195,6 @@ static int exynos5_mmc_config(int peripheral, int flags) static void exynos5_sromc_config(int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); int i; /* @@ -122,13 +212,13 @@ static void exynos5_sromc_config(int flags) * GPY1[2] SROM_WAIT(2) * GPY1[3] EBI_DATA_RDn(2) */ - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), - GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK), + S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2)); for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2)); /* * EBI: 8 Addrss Lines @@ -163,55 +253,112 @@ static void exynos5_sromc_config(int flags) * GPY6[7] EBI_DATA[15](2) */ for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP); } } static void exynos5_i2c_config(int peripheral, int flags) { + int func01, func23; + + /* High-Speed I2C */ + if (flags & PINMUX_FLAG_HS_MODE) { + func01 = 4; + func23 = 4; + } else { + func01 = 2; + func23 = 3; + } - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + switch (peripheral) { + case PERIPH_ID_I2C0: + gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01)); + gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01)); + break; + case PERIPH_ID_I2C1: + gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01)); + gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01)); + break; + case PERIPH_ID_I2C2: + gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23)); + gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23)); + break; + case PERIPH_ID_I2C3: + gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23)); + gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23)); + break; + case PERIPH_ID_I2C4: + gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3)); + break; + } +} +static void exynos5420_i2c_config(int peripheral) +{ switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C8: + gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C9: + gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C10: + gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2)); break; } } @@ -219,53 +366,95 @@ static void exynos5_i2c_config(int peripheral, int flags) static void exynos5_i2s_config(int peripheral) { int i; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); + switch (peripheral) { + case PERIPH_ID_I2S0: + for (i = 0; i < 5; i++) + gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02)); + break; + case PERIPH_ID_I2S1: + for (i = 0; i < 5; i++) + gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02)); + break; + } } void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct exynos5_gpio_part2 *gpio2 = - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A20; break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A24; break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + cfg = S5P_GPIO_FUNC(0x5); + pin = EXYNOS5_GPIO_B11; break; case PERIPH_ID_SPI3: - bank = &gpio2->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_F10; break; case PERIPH_ID_SPI4: for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); } break; } if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); + } +} + +void exynos5420_spi_config(int peripheral) +{ + int cfg, pin, i; + + switch (peripheral) { + case PERIPH_ID_SPI0: + pin = EXYNOS5420_GPIO_A20; + cfg = S5P_GPIO_FUNC(0x2); + break; + case PERIPH_ID_SPI1: + pin = EXYNOS5420_GPIO_A24; + cfg = S5P_GPIO_FUNC(0x2); + break; + case PERIPH_ID_SPI2: + pin = EXYNOS5420_GPIO_B11; + cfg = S5P_GPIO_FUNC(0x5); + break; + case PERIPH_ID_SPI3: + pin = EXYNOS5420_GPIO_F10; + cfg = S5P_GPIO_FUNC(0x2); + break; + case PERIPH_ID_SPI4: + cfg = 0; + pin = 0; + break; + default: + cfg = 0; + pin = 0; + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + gpio_cfg_pin(i, cfg); + } else { + for (i = 0; i < 2; i++) { + gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i, + S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i, + S5P_GPIO_FUNC(0x4)); + } } } @@ -296,6 +485,7 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C7: exynos5_i2c_config(peripheral, flags); break; + case PERIPH_ID_I2S0: case PERIPH_ID_I2S1: exynos5_i2s_config(peripheral); break; @@ -314,78 +504,126 @@ static int exynos5_pinmux_config(int peripheral, int flags) return 0; } -static void exynos4_i2c_config(int peripheral, int flags) +static int exynos5420_pinmux_config(int peripheral, int flags) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos5420_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos5420_mmc_config(peripheral, flags); + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5420_spi_config(peripheral); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + case PERIPH_ID_I2C8: + case PERIPH_ID_I2C9: + case PERIPH_ID_I2C10: + exynos5420_i2c_config(peripheral); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} +static void exynos4_i2c_config(int peripheral, int flags) +{ switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3)); break; } } static int exynos4_mmc_config(int peripheral, int flags) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start = 0, start_ext = 0; + unsigned int func, ext_func; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio2->k0; - bank_ext = &gpio2->k1; + start = EXYNOS4_GPIO_K00; + start_ext = EXYNOS4_GPIO_K13; + func = S5P_GPIO_FUNC(0x2); + ext_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC2: - bank = &gpio2->k2; - bank_ext = &gpio2->k3; + start = EXYNOS4_GPIO_K20; + start_ext = EXYNOS4_GPIO_K33; + func = S5P_GPIO_FUNC(0x2); + ext_func = S5P_GPIO_FUNC(0x3); + break; + case PERIPH_ID_SDMMC4: + start = EXYNOS4_GPIO_K00; + start_ext = EXYNOS4_GPIO_K13; + func = S5P_GPIO_FUNC(0x3); + ext_func = S5P_GPIO_FUNC(0x4); break; default: return -1; } - for (i = 0; i < 7; i++) { - if (i == 2) + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) continue; - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_cfg_pin(i, func); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } + /* SDMMC2 do not use 8bit mode at exynos4 */ if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i < 7; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, ext_func); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } @@ -394,38 +632,149 @@ static int exynos4_mmc_config(int peripheral, int flags) static void exynos4_uart_config(int peripheral) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS4_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS4_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS4_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS4_GPIO_A14; count = 2; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; } - for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } + +static void exynos4x12_i2c_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_I2C0: + gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3)); + break; + } +} + +static int exynos4x12_mmc_config(int peripheral, int flags) +{ + int i, start = 0, start_ext = 0; + unsigned int func, ext_func; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + start = EXYNOS4X12_GPIO_K00; + start_ext = EXYNOS4X12_GPIO_K13; + func = S5P_GPIO_FUNC(0x2); + ext_func = S5P_GPIO_FUNC(0x3); + break; + case PERIPH_ID_SDMMC2: + start = EXYNOS4X12_GPIO_K20; + start_ext = EXYNOS4X12_GPIO_K33; + func = S5P_GPIO_FUNC(0x2); + ext_func = S5P_GPIO_FUNC(0x3); + break; + case PERIPH_ID_SDMMC4: + start = EXYNOS4X12_GPIO_K00; + start_ext = EXYNOS4X12_GPIO_K13; + func = S5P_GPIO_FUNC(0x3); + ext_func = S5P_GPIO_FUNC(0x4); + break; + default: + return -1; + } + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) + continue; + gpio_cfg_pin(i, func); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, ext_func); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + } + + return 0; +} + +static void exynos4x12_uart_config(int peripheral) +{ + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + start = EXYNOS4X12_GPIO_A00; + count = 4; + break; + case PERIPH_ID_UART1: + start = EXYNOS4X12_GPIO_A04; + count = 4; + break; + case PERIPH_ID_UART2: + start = EXYNOS4X12_GPIO_A10; + count = 4; + break; + case PERIPH_ID_UART3: + start = EXYNOS4X12_GPIO_A14; + count = 2; + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + static int exynos4_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -447,11 +796,46 @@ static int exynos4_pinmux_config(int peripheral, int flags) break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC4: return exynos4_mmc_config(peripheral, flags); case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC3: + debug("SDMMC device %d not implemented\n", peripheral); + return -1; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + +static int exynos4x12_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos4x12_uart_config(peripheral); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4x12_i2c_config(peripheral, flags); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC4: - printf("SDMMC device %d not implemented\n", peripheral); + return exynos4x12_mmc_config(peripheral, flags); + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC3: + debug("SDMMC device %d not implemented\n", peripheral); return -1; default: debug("%s: invalid peripheral %d", __func__, peripheral); @@ -463,17 +847,39 @@ static int exynos4_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { - if (cpu_is_exynos5()) - return exynos5_pinmux_config(peripheral, flags); - else if (cpu_is_exynos4()) - return exynos4_pinmux_config(peripheral, flags); - else { - debug("pinmux functionality not supported\n"); - return -1; + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos5420_pinmux_config(peripheral, flags); + else if (proid_is_exynos5250()) + return exynos5_pinmux_config(peripheral, flags); + } else if (cpu_is_exynos4()) { + if (proid_is_exynos4412()) + return exynos4x12_pinmux_config(peripheral, flags); + else + return exynos4_pinmux_config(peripheral, flags); } + + debug("pinmux functionality not supported\n"); + + return -1; } #ifdef CONFIG_OF_CONTROL +static int exynos4_pinmux_decode_periph_id(const void *blob, int node) +{ + int err; + u32 cell[3]; + + err = fdtdec_get_int_array(blob, node, "interrupts", cell, + ARRAY_SIZE(cell)); + if (err) { + debug(" invalid peripheral id\n"); + return PERIPH_ID_NONE; + } + + return cell[1]; +} + static int exynos5_pinmux_decode_periph_id(const void *blob, int node) { int err; @@ -484,19 +890,16 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node) if (err) return PERIPH_ID_NONE; - /* check for invalid peripheral id */ - if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0)) - return cell[1]; - - debug(" invalid peripheral id\n"); - return PERIPH_ID_NONE; + return cell[1]; } int pinmux_decode_periph_id(const void *blob, int node) { if (cpu_is_exynos5()) return exynos5_pinmux_decode_periph_id(blob, node); - else - return PERIPH_ID_NONE; + else if (cpu_is_exynos4()) + return exynos4_pinmux_decode_periph_id(blob, node); + + return PERIPH_ID_NONE; } #endif diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index 517e804f34..1520d642c5 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -53,10 +53,59 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable) } } +void exynos4412_set_usbhost_phy_ctrl(unsigned int enable) +{ + struct exynos4412_power *power = + (struct exynos4412_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + void set_usbhost_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) exynos5_set_usbhost_phy_ctrl(enable); + else if (cpu_is_exynos4()) + if (proid_is_exynos4412()) + exynos4412_set_usbhost_phy_ctrl(enable); +} + +static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBDRD_PHY */ + setbits_le32(&power->usbdrd_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + } else { + /* Disabling USBDRD_PHY */ + clrbits_le32(&power->usbdrd_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + } +} + +void set_usbdrd_phy_ctrl(unsigned int enable) +{ + if (cpu_is_exynos5()) + exynos5_set_usbdrd_phy_ctrl(enable); } static void exynos5_dp_phy_control(unsigned int enable) @@ -90,6 +139,12 @@ static void exynos5_set_ps_hold_ctrl(void) EXYNOS_PS_HOLD_CONTROL_DATA_HIGH); } +/* + * Set ps_hold data driving value high + * This enables the machine to stay powered on + * after the initial power-on condition goes away + * (e.g. power button). + */ void set_ps_hold_ctrl(void) { if (cpu_is_exynos5()) @@ -174,3 +229,10 @@ void power_exit_wakeup(void) else exynos4_power_exit_wakeup(); } + +unsigned int get_boot_mode(void) +{ + unsigned int om_pin = samsung_get_base_power(); + + return readl(om_pin) & OM_PIN_MASK; +} diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index 3651c00859..bc237c969f 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -4,20 +4,22 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include -#include +#include +#include #include #include #include +#include +#include #include #include +#include #include "common_setup.h" #include "clock_init.h" DECLARE_GLOBAL_DATA_PTR; -#define OM_STAT (0x1f << 1) /* Index into irom ptr table */ enum index { @@ -59,6 +61,121 @@ static int config_branch_prediction(int set_cr_z) } #endif +#ifdef CONFIG_SPI_BOOTING +static void spi_rx_tx(struct exynos_spi *regs, int todo, + void *dinp, void const *doutp, int i) +{ + uint *rxp = (uint *)(dinp + (i * (32 * 1024))); + int rx_lvl, tx_lvl; + uint out_bytes, in_bytes; + + out_bytes = todo; + in_bytes = todo; + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + + while (in_bytes) { + uint32_t spi_sts; + int temp; + + spi_sts = readl(®s->spi_sts); + rx_lvl = ((spi_sts >> 15) & 0x7f); + tx_lvl = ((spi_sts >> 6) & 0x7f); + while (tx_lvl < 32 && out_bytes) { + temp = 0xffffffff; + writel(temp, ®s->tx_data); + out_bytes -= 4; + tx_lvl += 4; + } + while (rx_lvl >= 4 && in_bytes) { + temp = readl(®s->rx_data); + if (rxp) + *rxp++ = temp; + in_bytes -= 4; + rx_lvl -= 4; + } + } +} + +/* + * Copy uboot from spi flash to RAM + * + * @parma uboot_size size of u-boot to copy + * @param uboot_addr address in u-boot to copy + */ +static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) +{ + int upto, todo; + int i, timeout = 100; + struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE; + + set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* set the spi1 GPIO */ + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + + /* set pktcnt and enable it */ + writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + /* set FB_CLK_SEL */ + writel(SPI_FB_DELAY_180, ®s->fb_clk); + /* set CH_WIDTH and BUS_WIDTH as word */ + setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + + /* clear rx and tx channel if set priveously */ + clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + + setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN | + SPI_RX_BYTE_SWAP | + SPI_RX_HWORD_SWAP); + + /* do a soft reset */ + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + + /* now set rx and tx channel ON */ + setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + + /* Send read instruction (0x3h) followed by a 24 bit addr */ + writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data); + + /* waiting for TX done */ + while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) { + if (!timeout) { + debug("SPI TIMEOUT\n"); + break; + } + timeout--; + } + + for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { + todo = min(uboot_size - upto, (unsigned int)(1 << 15)); + spi_rx_tx(regs, todo, (void *)(uboot_addr), + (void *)(SPI_FLASH_UBOOT_POS), i); + } + + setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + + /* + * Let put controller mode to BYTE as + * SPI driver does not support WORD mode yet + */ + clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + writel(0, ®s->swap_cfg); + + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); +} +#endif + /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -66,19 +183,28 @@ static int config_branch_prediction(int set_cr_z) */ void copy_uboot_to_ram(void) { - enum boot_mode bootmode = BOOT_MODE_OM; + unsigned int bootmode = BOOT_MODE_OM; u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL; u32 offset = 0, size = 0; +#ifdef CONFIG_SPI_BOOTING + struct spl_machine_param *param = spl_get_machine_params(); +#endif #ifdef CONFIG_SUPPORT_EMMC_BOOT u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); void (*end_bootop_from_emmc)(void); #endif #ifdef CONFIG_USB_BOOTING - u32 (*usb_copy)(void); int is_cr_z_set; unsigned int sec_boot_check; + /* + * Note that older hardware (before Exynos5800) does not expect any + * arguments, but it does not hurt to pass them, so a common function + * prototype is used. + */ + u32 (*usb_copy)(u32 num_of_block, u32 *dst); + /* Read iRAM location to check for secondary USB boot mode */ sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) @@ -86,17 +212,16 @@ void copy_uboot_to_ram(void) #endif if (bootmode == BOOT_MODE_OM) - bootmode = readl(samsung_get_base_power()) & OM_STAT; + bootmode = get_boot_mode(); switch (bootmode) { #ifdef CONFIG_SPI_BOOTING case BOOT_MODE_SERIAL: - offset = SPI_FLASH_UBOOT_POS; - size = CONFIG_BL2_SIZE; - copy_bl2 = get_irom_func(SPI_INDEX); + /* Customised function to copy u-boot from SF */ + exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE); break; #endif - case BOOT_MODE_MMC: + case BOOT_MODE_SD: offset = BL2_START_OFFSET; size = BL2_SIZE_BLOC_COUNT; copy_bl2 = get_irom_func(MMC_INDEX); @@ -121,7 +246,7 @@ void copy_uboot_to_ram(void) */ is_cr_z_set = config_branch_prediction(0); usb_copy = get_irom_func(USB_INDEX); - usb_copy(); + usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE); config_branch_prediction(is_cr_z_set); break; #endif diff --git a/arch/arm/cpu/armv7/highbank/Kconfig b/arch/arm/cpu/armv7/highbank/Kconfig new file mode 100644 index 0000000000..0e73c04142 --- /dev/null +++ b/arch/arm/cpu/armv7/highbank/Kconfig @@ -0,0 +1,12 @@ +if ARCH_HIGHBANK + +config SYS_BOARD + default "highbank" + +config SYS_SOC + default "highbank" + +config SYS_CONFIG_NAME + default "highbank" + +endif diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile index 22e3b72c8b..876099d9a1 100644 --- a/arch/arm/cpu/armv7/highbank/Makefile +++ b/arch/arm/cpu/armv7/highbank/Makefile @@ -5,26 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS := timer.o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := timer.o diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index 792a828cbf..d56bf21133 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -7,18 +7,12 @@ */ #include -#include -#include /* for size_t */ -#include /* for NULL */ #include #include #undef SYSTIMER_BASE #define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */ -#define SYSTIMER_RATE 150000000 -static ulong timestamp; -static ulong lastinc; static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE; /* @@ -29,89 +23,12 @@ int timer_init(void) /* * Setup timer0 */ + writel(0, &systimer_base->timer0control); writel(SYSTIMER_RELOAD, &systimer_base->timer0load); writel(SYSTIMER_RELOAD, &systimer_base->timer0value); - writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control); - - reset_timer_masked(); + writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256, + &systimer_base->timer0control); return 0; } - -#define TICK_PER_TIME ((SYSTIMER_RATE + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) -#define NS_PER_TICK (1000000000 / SYSTIMER_RATE) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - do_div(tick, TICK_PER_TIME); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - return time * TICK_PER_TIME; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - unsigned long long tick = us * 1000; - tick += NS_PER_TICK - 1; - do_div(tick, NS_PER_TICK); - return tick; -} - -unsigned long long get_ticks(void) -{ - ulong now = ~readl(&systimer_base->timer0value); - - if (now >= lastinc) /* normal mode (non roll) */ - /* move stamp forward with absolut diff ticks */ - timestamp += (now - lastinc); - else /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - lastinc = now; - return timestamp; -} - -/* - * Delay x useconds AND preserve advance timstamp value - * assumes timer is ticking at 1 msec - */ -void __udelay(ulong usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void reset_timer_masked(void) -{ - lastinc = ~readl(&systimer_base->timer0value); - timestamp = 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/armv7/iproc-common/Makefile b/arch/arm/cpu/armv7/iproc-common/Makefile new file mode 100644 index 0000000000..c071a17e1f --- /dev/null +++ b/arch/arm/cpu/armv7/iproc-common/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += armpll.o +obj-y += hwinit-common.o +obj-y += timer.o diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c new file mode 100644 index 0000000000..49b61bf08c --- /dev/null +++ b/arch/arm/cpu/armv7/iproc-common/armpll.c @@ -0,0 +1,170 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define NELEMS(x) (sizeof(x) / sizeof(x[0])) + +struct armpll_parameters { + unsigned int mode; + unsigned int ndiv_int; + unsigned int ndiv_frac; + unsigned int pdiv; + unsigned int freqid; +}; + +struct armpll_parameters armpll_clk_tab[] = { + { 25, 64, 1, 1, 0}, + { 100, 64, 1, 1, 2}, + { 400, 64, 1, 1, 6}, + { 448, 71, 713050, 1, 6}, + { 500, 80, 1, 1, 6}, + { 560, 89, 629145, 1, 6}, + { 600, 96, 1, 1, 6}, + { 800, 64, 1, 1, 7}, + { 896, 71, 713050, 1, 7}, + { 1000, 80, 1, 1, 7}, + { 1100, 88, 1, 1, 7}, + { 1120, 89, 629145, 1, 7}, + { 1200, 96, 1, 1, 7}, +}; + +uint32_t armpll_config(uint32_t clkmhz) +{ + uint32_t freqid; + uint32_t ndiv_frac; + uint32_t pll; + uint32_t status = 1; + uint32_t timeout_countdown; + int i; + + for (i = 0; i < NELEMS(armpll_clk_tab); i++) { + if (armpll_clk_tab[i].mode == clkmhz) { + status = 0; + break; + } + } + + if (status) { + printf("Error: Clock configuration not supported\n"); + goto armpll_config_done; + } + + /* Enable write access */ + writel(IPROC_REG_WRITE_ACCESS, IHOST_PROC_CLK_WR_ACCESS); + + if (clkmhz == 25) + freqid = 0; + else + freqid = 2; + + /* Bypass ARM clock and run on sysclk */ + writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE | + freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R | + freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R | + freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R | + freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R, + IHOST_PROC_CLK_POLICY_FREQ); + + writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO | + 1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC, + IHOST_PROC_CLK_POLICY_CTL); + + /* Poll CCU until operation complete */ + timeout_countdown = 0x100000; + while (readl(IHOST_PROC_CLK_POLICY_CTL) & + (1 << IHOST_PROC_CLK_POLICY_CTL__GO)) { + timeout_countdown--; + if (timeout_countdown == 0) { + printf("CCU polling timedout\n"); + status = 1; + goto armpll_config_done; + } + } + + if (clkmhz == 25 || clkmhz == 100) { + status = 0; + goto armpll_config_done; + } + + /* Now it is safe to program the PLL */ + pll = readl(IHOST_PROC_CLK_PLLARMB); + pll &= ~((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1); + ndiv_frac = + ((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1) & + (armpll_clk_tab[i].ndiv_frac << + IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R); + pll |= ndiv_frac; + writel(pll, IHOST_PROC_CLK_PLLARMB); + + writel(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK | + armpll_clk_tab[i].ndiv_int << + IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R | + armpll_clk_tab[i].pdiv << + IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R | + 1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB, + IHOST_PROC_CLK_PLLARMA); + + /* Poll ARM PLL Lock until operation complete */ + timeout_countdown = 0x100000; + while (readl(IHOST_PROC_CLK_PLLARMA) & + (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK)) { + timeout_countdown--; + if (timeout_countdown == 0) { + printf("ARM PLL lock failed\n"); + status = 1; + goto armpll_config_done; + } + } + + pll = readl(IHOST_PROC_CLK_PLLARMA); + pll |= (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB); + writel(pll, IHOST_PROC_CLK_PLLARMA); + + /* Set the policy */ + writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE | + armpll_clk_tab[i].freqid << + IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R | + armpll_clk_tab[i].freqid << + IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R | + armpll_clk_tab[i].freqid << + IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R | + armpll_clk_tab[i+4].freqid << + IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R, + IHOST_PROC_CLK_POLICY_FREQ); + + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE0_CLKGATE); + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE1_CLKGATE); + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_SWITCH_CLKGATE); + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_PERIPH_CLKGATE); + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_APB0_CLKGATE); + + writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO | + 1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC, + IHOST_PROC_CLK_POLICY_CTL); + + /* Poll CCU until operation complete */ + timeout_countdown = 0x100000; + while (readl(IHOST_PROC_CLK_POLICY_CTL) & + (1 << IHOST_PROC_CLK_POLICY_CTL__GO)) { + timeout_countdown--; + if (timeout_countdown == 0) { + printf("CCU polling failed\n"); + status = 1; + goto armpll_config_done; + } + } + + status = 0; +armpll_config_done: + /* Disable access to PLL registers */ + writel(0, IHOST_PROC_CLK_WR_ACCESS); + + return status; +} diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c new file mode 100644 index 0000000000..7131524215 --- /dev/null +++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c @@ -0,0 +1,15 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/iproc-common/timer.c b/arch/arm/cpu/armv7/iproc-common/timer.c new file mode 100644 index 0000000000..373d8ec251 --- /dev/null +++ b/arch/arm/cpu/armv7/iproc-common/timer.c @@ -0,0 +1,130 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static inline uint64_t timer_global_read(void) +{ + uint64_t cur_tick; + uint32_t count_h; + uint32_t count_l; + + do { + count_h = readl(IPROC_PERIPH_GLB_TIM_REG_BASE + + TIMER_GLB_HI_OFFSET); + count_l = readl(IPROC_PERIPH_GLB_TIM_REG_BASE + + TIMER_GLB_LOW_OFFSET); + cur_tick = readl(IPROC_PERIPH_GLB_TIM_REG_BASE + + TIMER_GLB_HI_OFFSET); + } while (cur_tick != count_h); + + return (cur_tick << 32) + count_l; +} + +void timer_global_init(void) +{ + writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET); + writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_LOW_OFFSET); + writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_HI_OFFSET); + writel(TIMER_GLB_TIM_CTRL_TIM_EN, + IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET); +} + +int timer_init(void) +{ + timer_global_init(); + return 0; +} + +unsigned long get_timer(unsigned long base) +{ + uint64_t count; + uint64_t ret; + uint64_t tim_clk; + uint64_t periph_clk; + + count = timer_global_read(); + + /* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per msec */ + periph_clk = 500000; + tim_clk = lldiv(periph_clk, + (((readl(IPROC_PERIPH_GLB_TIM_REG_BASE + + TIMER_GLB_CTRL_OFFSET) & + TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1)); + + ret = lldiv(count, (uint32_t)tim_clk); + + /* returns msec */ + return ret - base; +} + +void __udelay(unsigned long usec) +{ + uint64_t cur_tick, end_tick; + uint64_t tim_clk; + uint64_t periph_clk; + + /* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per usec */ + periph_clk = 500; + + tim_clk = lldiv(periph_clk, + (((readl(IPROC_PERIPH_GLB_TIM_REG_BASE + + TIMER_GLB_CTRL_OFFSET) & + TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1)); + + cur_tick = timer_global_read(); + + end_tick = tim_clk; + end_tick *= usec; + end_tick += cur_tick; + + do { + cur_tick = timer_global_read(); + + } while (cur_tick < end_tick); +} + +void timer_systick_init(uint32_t tick_ms) +{ + /* Disable timer and clear interrupt status*/ + writel(0, IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET); + writel(TIMER_PVT_TIM_INT_STATUS_SET, + IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET); + writel((PLL_AXI_CLK/1000) * tick_ms, + IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_LOAD_OFFSET); + writel(TIMER_PVT_TIM_CTRL_INT_EN | + TIMER_PVT_TIM_CTRL_AUTO_RELD | + TIMER_PVT_TIM_CTRL_TIM_EN, + IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET); +} + +void timer_systick_isr(void *data) +{ + writel(TIMER_PVT_TIM_INT_STATUS_SET, + IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value in msec. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This is used in conjuction with get_ticks, which returns msec as ticks. + * Here we just return ticks/sec = msec/sec = 1000 + */ +ulong get_tbclk(void) +{ + return 1000; +} diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig new file mode 100644 index 0000000000..134ae87fe1 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/Kconfig @@ -0,0 +1,22 @@ +if ARCH_KEYSTONE + +choice + prompt "TI Keystone board select" + +config TARGET_K2HK_EVM + bool "TI Keystone 2 Kepler/Hawking EVM" + +config TARGET_K2E_EVM + bool "TI Keystone 2 Edison EVM" + +config TARGET_K2L_EVM + bool "TI Keystone 2 Lamar EVM" + +endchoice + +config SYS_SOC + default "keystone" + +source "board/ti/ks2_evm/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile new file mode 100644 index 0000000000..ed030db2c8 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -0,0 +1,18 @@ +# +# (C) Copyright 2012-2014 +# Texas Instruments Incorporated, +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += init.o +obj-y += psc.o +obj-y += clock.o +obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o +obj-$(CONFIG_SOC_K2E) += clock-k2e.o +obj-$(CONFIG_SOC_K2L) += clock-k2l.o +obj-y += cmd_clock.o +obj-y += cmd_mon.o +obj-y += msmc.o +obj-y += ddr3.o cmd_ddr3.o +obj-y += keystone.o diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c new file mode 100644 index 0000000000..31f66613ef --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c @@ -0,0 +1,117 @@ +/* + * Keystone2: get clk rate for K2E + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, +}; + +int dev_speeds[] = { + SPD800, + SPD850, + SPD1000, + SPD1250, + SPD1350, + SPD1400, + SPD1500, + SPD1400, + SPD1350, + SPD1250, + SPD1000, + SPD850, + SPD800 +}; + +/** + * pll_freq_get - get pll frequency + * Fout = Fref * NF(mult) / NR(prediv) / OD + * @pll: pll identifier + */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(KS2_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = KS2_PASSPLLCTL0; + break; + case DDR3_PLL: + ret = external_clk[ddr3_clk]; + reg = KS2_DDR3APLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c new file mode 100644 index 0000000000..1591960795 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c @@ -0,0 +1,145 @@ +/* + * Keystone2: get clk rate for K2HK + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, + [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, + [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, +}; + +int dev_speeds[] = { + SPD800, + SPD1000, + SPD1200, + SPD800, + SPD800, + SPD800, + SPD800, + SPD800, + SPD1200, + SPD1000, + SPD800, + SPD800, + SPD800, +}; + +int arm_speeds[] = { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD800, + SPD1400, + SPD1350, + SPD1200, + SPD1000, + SPD800, + SPD800, + SPD800, +}; + +/** + * pll_freq_get - get pll frequency + * Fout = Fref * NF(mult) / NR(prediv) / OD + * @pll: pll identifier + */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(KS2_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = KS2_PASSPLLCTL0; + break; + case TETRIS_PLL: + ret = external_clk[tetris_clk]; + reg = KS2_ARMPLLCTL0; + break; + case DDR3A_PLL: + ret = external_clk[ddr3a_clk]; + reg = KS2_DDR3APLLCTL0; + break; + case DDR3B_PLL: + ret = external_clk[ddr3b_clk]; + reg = KS2_DDR3BPLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); + case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL); + case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/cpu/armv7/keystone/clock-k2l.c new file mode 100644 index 0000000000..1c5e4d54d8 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock-k2l.c @@ -0,0 +1,138 @@ +/* + * Keystone2: get clk rate for K2L + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, + [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, +}; + +int dev_speeds[] = { + SPD800, + SPD1000, + SPD1200, + SPD800, + SPD800, + SPD800, + SPD800, + SPD800, + SPD1200, + SPD1000, + SPD800, + SPD800, + SPD800, +}; + +int arm_speeds[] = { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD800, + SPD1400, + SPD1350, + SPD1200, + SPD1000, + SPD800, + SPD800, + SPD800, +}; + +/** + * pll_freq_get - get pll frequency + * Fout = Fref * NF(mult) / NR(prediv) / OD + * @pll: pll identifier + */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(KS2_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = KS2_PASSPLLCTL0; + break; + case TETRIS_PLL: + ret = external_clk[tetris_clk]; + reg = KS2_ARMPLLCTL0; + break; + case DDR3_PLL: + ret = external_clk[ddr3_clk]; + reg = KS2_DDR3APLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); + case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c new file mode 100644 index 0000000000..d13fbc1a4b --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -0,0 +1,272 @@ +/* + * Keystone2: pll initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define MAX_SPEEDS 13 + +static void wait_for_completion(const struct pll_init_data *data) +{ + int i; + for (i = 0; i < 100; i++) { + sdelay(450); + if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0) + break; + } +} + +void init_pll(const struct pll_init_data *data) +{ + u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj; + + pllm = data->pll_m - 1; + plld = (data->pll_d - 1) & PLL_DIV_MASK; + pllod = (data->pll_od - 1) & PLL_CLKOD_MASK; + + if (data->pll == MAIN_PLL) { + /* The requered delay before main PLL configuration */ + sdelay(210000); + + tmp = pllctl_reg_read(data->pll, secctl); + + if (tmp & (PLLCTL_BYPASS)) { + setbits_le32(keystone_pll_regs[data->pll].reg1, + BIT(MAIN_ENSAT_OFFSET)); + + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | + PLLCTL_PLLENSRC); + sdelay(340); + + pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS); + pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN); + sdelay(21000); + + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN); + } else { + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | + PLLCTL_PLLENSRC); + sdelay(340); + } + + pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); + + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLLM_MULT_HI_SMASK, (pllm << 6)); + + /* Set the BWADJ (12 bit field) */ + tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */ + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLL_BWADJ_LO_SMASK, + (tmp_ctl << PLL_BWADJ_LO_SHIFT)); + clrsetbits_le32(keystone_pll_regs[data->pll].reg1, + PLL_BWADJ_HI_MASK, + (tmp_ctl >> 8)); + + /* + * Set the pll divider (6 bit field) * + * PLLD[5:0] is located in MAINPLLCTL0 + */ + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLL_DIV_MASK, plld); + + /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */ + pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK, + (pllod << PLL_CLKOD_SHIFT)); + wait_for_completion(data); + + pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1); + pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2); + pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3); + pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4); + pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5); + + pllctl_reg_setbits(data->pll, alnctl, 0x1f); + + /* + * Set GOSET bit in PLLCMD to initiate the GO operation + * to change the divide + */ + pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO); + sdelay(1500); /* wait for the phase adj */ + wait_for_completion(data); + + /* Reset PLL */ + pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST); + sdelay(21000); /* Wait for a minimum of 7 us*/ + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST); + sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ + + pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS); + + tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); + +#ifndef CONFIG_SOC_K2E + } else if (data->pll == TETRIS_PLL) { + bwadj = pllm >> 1; + /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ + setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); + /* + * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass) + * only applicable for Kepler + */ + clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); + /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */ + setbits_le32(keystone_pll_regs[data->pll].reg1 , + PLL_PLLRST | PLLCTL_ENSAT); + + /* + * 3 Program PLLM and PLLD in PLLCTL0 register + * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in + * PLLCTL1 register. BWADJ value must be set + * to ((PLLM + 1) >> 1) – 1) + */ + tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) | + (pllm << 6) | + (plld & PLL_DIV_MASK) | + (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS; + __raw_writel(tmp, keystone_pll_regs[data->pll].reg0); + + /* Set BWADJ[11:8] bits */ + tmp = __raw_readl(keystone_pll_regs[data->pll].reg1); + tmp &= ~(PLL_BWADJ_HI_MASK); + tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); + /* + * 5 Wait for at least 5 us based on the reference + * clock (PLL reset time) + */ + sdelay(21000); /* Wait for a minimum of 7 us*/ + + /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */ + clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST); + /* + * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1) + * (PLL lock time) + */ + sdelay(105000); + /* 8 disable bypass */ + clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); + /* + * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass) + * only applicable for Kepler + */ + setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); +#endif + } else { + setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT); + /* + * process keeps state of Bypass bit while programming + * all other DDR PLL settings + */ + tmp = __raw_readl(keystone_pll_regs[data->pll].reg0); + tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */ + + /* + * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0, + * bypass disabled + */ + bwadj = pllm >> 1; + tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) | + (pllm << PLL_MULT_SHIFT) | + (plld & PLL_DIV_MASK) | + (pllod << PLL_CLKOD_SHIFT); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg0); + + /* Set BWADJ[11:8] bits */ + tmp = __raw_readl(keystone_pll_regs[data->pll].reg1); + tmp &= ~(PLL_BWADJ_HI_MASK); + tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK); + + __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); + + /* Reset bit: bit 14 for both DDR3 & PASS PLL */ + tmp = PLL_PLLRST; + /* Set RESET bit = 1 */ + setbits_le32(keystone_pll_regs[data->pll].reg1, tmp); + /* Wait for a minimum of 7 us*/ + sdelay(21000); + /* Clear RESET bit */ + clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp); + sdelay(105000); + + /* clear BYPASS (Enable PLL Mode) */ + clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); + sdelay(21000); /* Wait for a minimum of 7 us*/ + } + + /* + * This is required to provide a delay between multiple + * consequent PPL configurations + */ + sdelay(210000); +} + +void init_plls(int num_pll, struct pll_init_data *config) +{ + int i; + + for (i = 0; i < num_pll; i++) + init_pll(&config[i]); +} + +static int get_max_speed(u32 val, int *speeds) +{ + int j; + + if (!val) + return speeds[0]; + + for (j = 1; j < MAX_SPEEDS; j++) { + if (val == 1) + return speeds[j]; + val >>= 1; + } + + return SPD800; +} + +#ifdef CONFIG_SOC_K2HK +static u32 read_efuse_bootrom(void) +{ + return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) : + __raw_readl(KS2_REV1_DEVSPEED); +} +#else +static inline u32 read_efuse_bootrom(void) +{ + return __raw_readl(KS2_EFUSE_BOOTROM); +} +#endif + +inline int get_max_dev_speed(void) +{ + return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds); +} + +#ifndef CONFIG_SOC_K2E +inline int get_max_arm_speed(void) +{ + return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds); +} +#endif + +void pass_pll_pa_clk_enable(void) +{ + u32 reg; + + reg = readl(keystone_pll_regs[PASS_PLL].reg1); + + reg |= PLLCTL_PAPLL; + writel(reg, keystone_pll_regs[PASS_PLL].reg1); + + /* wait till clock is enabled */ + sdelay(15000); +} diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c new file mode 100644 index 0000000000..af1b701e82 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c @@ -0,0 +1,135 @@ +/* + * keystone2: commands for clocks + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +struct pll_init_data cmd_pll_data = { + .pll = MAIN_PLL, + .pll_m = 16, + .pll_d = 1, + .pll_od = 2, +}; + +int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 5) + goto pll_cmd_usage; + + if (strncmp(argv[1], "pa", 2) == 0) + cmd_pll_data.pll = PASS_PLL; +#ifndef CONFIG_SOC_K2E + else if (strncmp(argv[1], "arm", 3) == 0) + cmd_pll_data.pll = TETRIS_PLL; +#endif +#ifdef CONFIG_SOC_K2HK + else if (strncmp(argv[1], "ddr3a", 5) == 0) + cmd_pll_data.pll = DDR3A_PLL; + else if (strncmp(argv[1], "ddr3b", 5) == 0) + cmd_pll_data.pll = DDR3B_PLL; +#else + else if (strncmp(argv[1], "ddr3", 4) == 0) + cmd_pll_data.pll = DDR3_PLL; +#endif + else + goto pll_cmd_usage; + + cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10); + cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10); + cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10); + + printf("Trying to set pll %d; mult %d; div %d; OD %d\n", + cmd_pll_data.pll, cmd_pll_data.pll_m, + cmd_pll_data.pll_d, cmd_pll_data.pll_od); + init_pll(&cmd_pll_data); + + return 0; + +pll_cmd_usage: + return cmd_usage(cmdtp); +} + +U_BOOT_CMD( + pllset, 5, 0, do_pll_cmd, + "set pll multiplier and pre divider", + PLLSET_CMD_LIST "
\n" +); + +int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int clk; + unsigned int freq; + + if (argc != 2) + goto getclk_cmd_usage; + + clk = simple_strtoul(argv[1], NULL, 10); + + freq = clk_get_rate(clk); + printf("clock index [%d] - frequency %u\n", clk, freq); + return 0; + +getclk_cmd_usage: + return cmd_usage(cmdtp); +} + +U_BOOT_CMD( + getclk, 2, 0, do_getclk_cmd, + "get clock rate", + "\n" + "The indexes for clocks:\n" + CLOCK_INDEXES_LIST +); + +int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int psc_module; + int res; + + if (argc != 3) + goto psc_cmd_usage; + + psc_module = simple_strtoul(argv[1], NULL, 10); + if (strcmp(argv[2], "en") == 0) { + res = psc_enable_module(psc_module); + printf("psc_enable_module(%d) - %s\n", psc_module, + (res) ? "ERROR" : "OK"); + return 0; + } + + if (strcmp(argv[2], "di") == 0) { + res = psc_disable_module(psc_module); + printf("psc_disable_module(%d) - %s\n", psc_module, + (res) ? "ERROR" : "OK"); + return 0; + } + + if (strcmp(argv[2], "domain") == 0) { + res = psc_disable_domain(psc_module); + printf("psc_disable_domain(%d) - %s\n", psc_module, + (res) ? "ERROR" : "OK"); + return 0; + } + +psc_cmd_usage: + return cmd_usage(cmdtp); +} + +U_BOOT_CMD( + psc, 3, 0, do_psc_cmd, + "", + " \n" + "Intended to control Power and Sleep Controller (PSC) domains and\n" + "modules. The module or domain index exectly corresponds to ones\n" + "listed in official TRM. For instance, to enable MSMC RAM clock\n" + "domain use command: psc 14 en.\n" +); diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c new file mode 100644 index 0000000000..ea78ad8fd5 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c @@ -0,0 +1,248 @@ +/* + * Keystone2: DDR3 test commands + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE + +#define DDR_REMAP_ADDR 0x80000000 +#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17) + +#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \ + CONFIG_STACKSIZE) >> 17) - 2) + +#define DDR_TEST_BURST_SIZE 1024 + +static int ddr_memory_test(u32 start_address, u32 end_address, int quick) +{ + u32 index_start, value, index; + + index_start = start_address; + + while (1) { + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) + __raw_writel(index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) { + value = __raw_readl(index); + if (value != index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readl(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + if (quick) + continue; + + /* Write a pattern for complementary values */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) + __raw_writel((u32)~index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) { + value = __raw_readl(index); + if (value != ~index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readl(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 2) + __raw_writew((u16)index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 2) { + value = __raw_readw(index); + if (value != (u16)index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readw(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 1) + __raw_writeb((u8)index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 1) { + value = __raw_readb(index); + if (value != (u8)index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readb(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + } + + puts("ddr memory test PASSED!\n"); + return 0; +} + +static int ddr_memory_compare(u32 address1, u32 address2, u32 size) +{ + u32 index, value, index2, value2; + + for (index = address1, index2 = address2; + index < address1 + size; + index += 4, index2 += 4) { + value = __raw_readl(index); + value2 = __raw_readl(index2); + + if (value != value2) { + printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n", + index, value, index2, value2); + + return -1; + } + } + + puts("ddr memory compare PASSED!\n"); + return 0; +} + +static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err) +{ + u32 value1, value2, value3; + + puts("Disabling DDR ECC ...\n"); + ddr3_disable_ecc(base); + + value1 = __raw_readl(address); + value2 = value1 ^ ecc_err; + __raw_writel(value2, address); + + value3 = __raw_readl(address); + printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n", + address, value1, value2, ecc_err, value3); + + __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16), + base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); + + puts("Enabling DDR ECC ...\n"); + ddr3_enable_ecc(base, 1); + + value1 = __raw_readl(address); + printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1); + + ddr3_check_ecc_int(base); + return 0; +} + +static int do_ddr_test(cmd_tbl_t *cmdtp, + int flag, int argc, char * const argv[]) +{ + u32 start_addr, end_addr, size, ecc_err; + + if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) { + if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) { + puts("ECC RMW isn't supported for this SOC\n"); + return 1; + } + + start_addr = simple_strtoul(argv[2], NULL, 16); + ecc_err = simple_strtoul(argv[3], NULL, 16); + + if ((start_addr < CONFIG_SYS_SDRAM_BASE) || + (start_addr > (CONFIG_SYS_SDRAM_BASE + + CONFIG_MAX_RAM_BANK_SIZE - 1))) { + puts("Invalid address!\n"); + return cmd_usage(cmdtp); + } + + ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE, + start_addr, ecc_err); + return 0; + } + + if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) || + ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0)))) + return cmd_usage(cmdtp); + + start_addr = simple_strtoul(argv[2], NULL, 16); + end_addr = simple_strtoul(argv[3], NULL, 16); + + if ((start_addr < CONFIG_SYS_SDRAM_BASE) || + (start_addr > (CONFIG_SYS_SDRAM_BASE + + CONFIG_MAX_RAM_BANK_SIZE - 1)) || + (end_addr < CONFIG_SYS_SDRAM_BASE) || + (end_addr > (CONFIG_SYS_SDRAM_BASE + + CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) { + puts("Invalid start or end address!\n"); + return cmd_usage(cmdtp); + } + + puts("Please wait ...\n"); + if (argc == 5) { + size = simple_strtoul(argv[4], NULL, 16); + ddr_memory_compare(start_addr, end_addr, size); + } else { + ddr_memory_test(start_addr, end_addr, 0); + } + + return 0; +} + +U_BOOT_CMD(ddr, 5, 1, do_ddr_test, + "DDR3 test", + "test - test DDR from start\n" + " address to end address\n" + "ddr compare -\n" + " compare DDR data of (size) bytes from start address to end\n" + " address\n" + "ddr ecc_err - generate bit errors\n" + " in DDR data at , the command will read a 32-bit data\n" + " from , and write (data ^ bit_err) back to \n" +); diff --git a/arch/arm/cpu/armv7/keystone/cmd_mon.c b/arch/arm/cpu/armv7/keystone/cmd_mon.c new file mode 100644 index 0000000000..f9f58a37df --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/cmd_mon.c @@ -0,0 +1,131 @@ +/* + * K2HK: secure kernel command file + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +asm(".arch_extension sec\n\t"); + +static int mon_install(u32 addr, u32 dpsc, u32 freq) +{ + int result; + + __asm__ __volatile__ ( + "stmfd r13!, {lr}\n" + "mov r0, %1\n" + "mov r1, %2\n" + "mov r2, %3\n" + "blx r0\n" + "ldmfd r13!, {lr}\n" + : "=&r" (result) + : "r" (addr), "r" (dpsc), "r" (freq) + : "cc", "r0", "r1", "r2", "memory"); + return result; +} + +static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 addr, dpsc_base = 0x1E80000, freq; + int rcode = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + freq = clk_get_rate(sys_clk0_6_clk); + + addr = simple_strtoul(argv[1], NULL, 16); + + rcode = mon_install(addr, dpsc_base, freq); + printf("## installed monitor, freq [%d], status %d\n", + freq, rcode); + + return 0; +} + +U_BOOT_CMD(mon_install, 2, 0, do_mon_install, + "Install boot kernel at 'addr'", + "" +); + +static void core_spin(void) +{ + while (1) + ; /* forever */; +} + +int mon_power_on(int core_id, void *ep) +{ + int result; + + asm volatile ( + "stmfd r13!, {lr}\n" + "mov r1, %1\n" + "mov r2, %2\n" + "mov r0, #0\n" + "smc #0\n" + "ldmfd r13!, {lr}\n" + : "=&r" (result) + : "r" (core_id), "r" (ep) + : "cc", "r0", "r1", "r2", "memory"); + return result; +} + +int mon_power_off(int core_id) +{ + int result; + + asm volatile ( + "stmfd r13!, {lr}\n" + "mov r1, %1\n" + "mov r0, #1\n" + "smc #1\n" + "ldmfd r13!, {lr}\n" + : "=&r" (result) + : "r" (core_id) + : "cc", "r0", "r1", "memory"); + return result; +} + +int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int rcode = 0, core_id, on; + void (*fn)(void); + + fn = core_spin; + + if (argc < 3) + return CMD_RET_USAGE; + + core_id = simple_strtoul(argv[1], NULL, 16); + on = simple_strtoul(argv[2], NULL, 16); + + if (on) + rcode = mon_power_on(core_id, fn); + else + rcode = mon_power_off(core_id); + + if (on) { + if (!rcode) + printf("core %d powered on successfully\n", core_id); + else + printf("core %d power on failure\n", core_id); + } else { + printf("core %d powered off successfully\n", core_id); + } + + return 0; +} + +U_BOOT_CMD(mon_power, 3, 0, do_mon_power, + "Power On/Off secondary core", + "mon_power \n" + "- coreid (1-3) and oper (1 - ON, 0 - OFF)\n" + "" +); diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c new file mode 100644 index 0000000000..923906afb5 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -0,0 +1,407 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include + +#define DDR3_EDMA_BLK_SIZE_SHIFT 10 +#define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT) +#define DDR3_EDMA_BCNT 0x8000 +#define DDR3_EDMA_CCNT 1 +#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT) +#define DDR3_EDMA_SLOT_NUM 1 + +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) +{ + unsigned int tmp; + + while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) + & 0x00000001) != 0x00000001) + ; + + __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); + + tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); + tmp &= ~(phy_cfg->pgcr1_mask); + tmp |= phy_cfg->pgcr1_val; + __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); + + __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); + __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); + __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); + __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); + + tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); + tmp &= ~(phy_cfg->dcr_mask); + tmp |= phy_cfg->dcr_val; + __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); + + __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); + __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); + __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); + __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); + __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); + __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); + __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); + __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); + + __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); + __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET); + __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET); + + __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET); + while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) + ; + + __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); + while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) + ; +} + +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) +{ + __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); + __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); + __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET); + __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET); + __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET); + __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); + __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); +} + +int ddr3_ecc_support_rmw(u32 base) +{ + u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); + + /* Check the DDR3 controller ID reg if the controllers + supports ECC RMW or not */ + if (value == 0x40461C02) + return 1; + + return 0; +} + +static void ddr3_ecc_config(u32 base, u32 value) +{ + u32 data; + + __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET); + udelay(100000); /* delay required to synchronize across clock domains */ + + if (value & KS2_DDR3_ECC_EN) { + /* Clear the 1-bit error count */ + data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); + __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); + + /* enable the ECC interrupt */ + __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | + KS2_DDR3_WR_ECC_ERR_SYS, + base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET); + + /* Clear the ECC error interrupt status */ + __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | + KS2_DDR3_WR_ECC_ERR_SYS, + base + KS2_DDR3_ECC_INT_STATUS_OFFSET); + } +} + +static void ddr3_reset_data(u32 base, u32 ddr3_size) +{ + u32 mpax[2]; + u32 seg_num; + u32 seg, blks, dst, edma_blks; + struct edma3_slot_config slot; + struct edma3_channel_config edma_channel; + u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, }; + + /* Setup an edma to copy the 1k block to the entire DDR */ + puts("\nClear entire DDR3 memory to enable ECC\n"); + + /* save the SES MPAX regs */ + msmc_get_ses_mpax(8, 0, mpax); + + /* setup edma slot 1 configuration */ + slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB | + EDMA3_SLOPT_COMP_CODE(0) | + EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC; + slot.bcnt = DDR3_EDMA_BCNT; + slot.acnt = DDR3_EDMA_BLK_SIZE; + slot.ccnt = DDR3_EDMA_CCNT; + slot.src_bidx = 0; + slot.dst_bidx = DDR3_EDMA_BLK_SIZE; + slot.src_cidx = 0; + slot.dst_cidx = 0; + slot.link = EDMA3_PARSET_NULL_LINK; + slot.bcntrld = 0; + edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot); + + /* configure quik edma channel */ + edma_channel.slot = DDR3_EDMA_SLOT_NUM; + edma_channel.chnum = 0; + edma_channel.complete_code = 0; + /* event trigger after dst update */ + edma_channel.trigger_slot_word = EDMA3_TWORD(dst); + qedma3_start(KS2_EDMA0_BASE, &edma_channel); + + /* DDR3 size in segments (4KB seg size) */ + seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT); + + for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) { + /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF + access slave interface so that edma driver can access */ + msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT, + KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G); + + if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM) + edma_blks = KS2_MSMC_MAP_SEG_NUM << + (KS2_MSMC_SEG_SIZE_SHIFT + - DDR3_EDMA_BLK_SIZE_SHIFT); + else + edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT + - DDR3_EDMA_BLK_SIZE_SHIFT); + + /* Use edma driver to scrub 2GB DDR memory */ + for (dst = base, blks = 0; blks < edma_blks; + blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) { + edma3_set_src_addr(KS2_EDMA0_BASE, + edma_channel.slot, (u32)edma_src); + edma3_set_dest_addr(KS2_EDMA0_BASE, + edma_channel.slot, (u32)dst); + + while (edma3_check_for_transfer(KS2_EDMA0_BASE, + &edma_channel)) + udelay(10); + } + } + + qedma3_stop(KS2_EDMA0_BASE, &edma_channel); + + /* restore the SES MPAX regs */ + msmc_set_ses_mpax(8, 0, mpax); +} + +static void ddr3_ecc_init_range(u32 base) +{ + u32 ecc_val = KS2_DDR3_ECC_EN; + u32 rmw = ddr3_ecc_support_rmw(base); + + if (rmw) + ecc_val |= KS2_DDR3_ECC_RMW_EN; + + __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); + + ddr3_ecc_config(base, ecc_val); +} + +void ddr3_enable_ecc(u32 base, int test) +{ + u32 ecc_val = KS2_DDR3_ECC_ENABLE; + u32 rmw = ddr3_ecc_support_rmw(base); + + if (test) + ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN; + + if (!rmw) { + if (!test) + /* by default, disable ecc when rmw = 0 and no + ecc test */ + ecc_val = 0; + } else { + ecc_val |= KS2_DDR3_ECC_RMW_EN; + } + + ddr3_ecc_config(base, ecc_val); +} + +void ddr3_disable_ecc(u32 base) +{ + ddr3_ecc_config(base, 0); +} + +#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) +static void cic_init(u32 base) +{ + /* Disable CIC global interrupts */ + __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE); + + /* Set to normal mode, no nesting, no priority hold */ + __raw_writel(0, base + KS2_CIC_CTRL); + __raw_writel(0, base + KS2_CIC_HOST_CTRL); + + /* Enable CIC global interrupts */ + __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE); +} + +static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) +{ + /* Map the system interrupt to a CIC channel */ + __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num); + + /* Enable CIC system interrupt */ + __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET); + + /* Enable CIC Host interrupt */ + __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET); +} + +static void ddr3_map_ecc_cic2_irq(u32 base) +{ + cic_init(base); + cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM, + KS2_CIC2_DDR3_ECC_IRQ_NUM); +} +#endif + +void ddr3_init_ecc(u32 base) +{ + u32 ddr3_size; + + if (!ddr3_ecc_support_rmw(base)) { + ddr3_disable_ecc(base); + return; + } + + ddr3_ecc_init_range(base); + ddr3_size = ddr3_get_size(); + ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); + + /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ +#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) + ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE); +#endif + ddr3_enable_ecc(base, 0); +} + +void ddr3_check_ecc_int(u32 base) +{ + char *env; + int ecc_test = 0; + u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); + + env = getenv("ecc_test"); + if (env) + ecc_test = simple_strtol(env, NULL, 0); + + if (value & KS2_DDR3_WR_ECC_ERR_SYS) + puts("DDR3 ECC write error interrupted\n"); + + if (value & KS2_DDR3_2B_ECC_ERR_SYS) { + puts("DDR3 ECC 2-bit error interrupted\n"); + + if (!ecc_test) { + puts("Reseting the device ...\n"); + reset_cpu(0); + } + } + + value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); + if (value) { + printf("1-bit ECC err count: 0x%x\n", value); + value = __raw_readl(base + + KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET); + printf("1-bit ECC err address log: 0x%x\n", value); + } +} + +void ddr3_reset_ddrphy(void) +{ + u32 tmp; + + /* Assert DDR3A PHY reset */ + tmp = readl(KS2_DDR3APLLCTL1); + tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; + writel(tmp, KS2_DDR3APLLCTL1); + + /* wait 10us to catch the reset */ + udelay(10); + + /* Release DDR3A PHY reset */ + tmp = readl(KS2_DDR3APLLCTL1); + tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; + __raw_writel(tmp, KS2_DDR3APLLCTL1); +} + +#ifdef CONFIG_SOC_K2HK +/** + * ddr3_reset_workaround - reset workaround in case if leveling error + * detected for PG 1.0 and 1.1 k2hk SoCs + */ +void ddr3_err_reset_workaround(void) +{ + unsigned int tmp; + unsigned int tmp_a; + unsigned int tmp_b; + + /* + * Check for PGSR0 error bits of DDR3 PHY. + * Check for WLERR, QSGERR, WLAERR, + * RDERR, WDERR, REERR, WEERR error to see if they are set or not + */ + tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); + tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); + + if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) { + printf("DDR Leveling Error Detected!\n"); + printf("DDR3A PGSR0 = 0x%x\n", tmp_a); + printf("DDR3B PGSR0 = 0x%x\n", tmp_b); + + /* + * Write Keys to KICK registers to enable writes to registers + * in boot config space + */ + __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); + __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); + + /* + * Move DDR3A Module out of reset isolation by setting + * MDCTL23[12] = 0 + */ + tmp_a = __raw_readl(KS2_PSC_BASE + + PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); + + tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0); + __raw_writel(tmp_a, KS2_PSC_BASE + + PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); + + /* + * Move DDR3B Module out of reset isolation by setting + * MDCTL24[12] = 0 + */ + tmp_b = __raw_readl(KS2_PSC_BASE + + PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); + tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0); + __raw_writel(tmp_b, KS2_PSC_BASE + + PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); + + /* + * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes + * to RSTCTRL and RSTCFG + */ + tmp = __raw_readl(KS2_RSTCTRL); + tmp &= KS2_RSTCTRL_MASK; + tmp |= KS2_RSTCTRL_KEY; + __raw_writel(tmp, KS2_RSTCTRL); + + /* + * Set PLL Controller to drive hard reset on SW trigger by + * setting RSTCFG[13] = 0 + */ + tmp = __raw_readl(KS2_RSTCTRL_RSCFG); + tmp &= ~KS2_RSTYPE_PLL_SOFT; + __raw_writel(tmp, KS2_RSTCTRL_RSCFG); + + reset_cpu(0); + } +} +#endif diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c new file mode 100644 index 0000000000..c96845c4e2 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -0,0 +1,151 @@ +/* + * Keystone2: Architecture initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_PCI_PORTS 2 +enum pci_mode { + ENDPOINT, + LEGACY_ENDPOINT, + ROOTCOMPLEX, +}; + +#define DEVCFG_MODE_MASK (BIT(2) | BIT(1)) +#define DEVCFG_MODE_SHIFT 1 + +void chip_configuration_unlock(void) +{ + __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); + __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); +} + +#ifdef CONFIG_SOC_K2L +void osr_init(void) +{ + u32 i; + u32 j; + u32 val; + u32 base = KS2_OSR_CFG_BASE; + u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS]; + + /* Enable the OSR clock domain */ + psc_enable_module(KS2_LPSC_OSR); + + /* Disable OSR ECC check for all the ram banks */ + for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) { + val = i | KS2_OSR_ECC_VEC_TRIG_RD | + (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH); + + writel(val , base + KS2_OSR_ECC_VEC); + + /** + * wait till read is done. + * Print should be added after earlyprintk support is added. + */ + for (j = 0; j < 10000; j++) { + val = readl(base + KS2_OSR_ECC_VEC); + if (val & KS2_OSR_ECC_VEC_RD_DONE) + break; + } + + ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^ + KS2_OSR_ECC_CTRL_CHK; + + writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4); + writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL); + } + + /* Reset OSR memory to all zeros */ + for (i = 0; i < KS2_OSR_SIZE; i += 4) + writel(0, KS2_OSR_DATA_BASE + i); + + /* Enable OSR ECC check for all the ram banks */ + for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) + writel(ecc_ctrl[i] | + KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL); +} +#endif + +/* Function to set up PCIe mode */ +static void config_pcie_mode(int pcie_port, enum pci_mode mode) +{ + u32 val = __raw_readl(KS2_DEVCFG); + + if (pcie_port >= MAX_PCI_PORTS) + return; + + /** + * each pci port has two bits for mode and it starts at + * bit 1. So use port number to get the right bit position. + */ + pcie_port <<= 1; + val &= ~(DEVCFG_MODE_MASK << pcie_port); + val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port); + __raw_writel(val, KS2_DEVCFG); +} + +int arch_cpu_init(void) +{ + chip_configuration_unlock(); + icache_enable(); + + msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS); + msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP); + msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP); + msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0); + + /* Initialize the PCIe-0 to work as Root Complex */ + config_pcie_mode(0, ROOTCOMPLEX); +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1); + /* Initialize the PCIe-1 to work as Root Complex */ + config_pcie_mode(1, ROOTCOMPLEX); +#endif +#ifdef CONFIG_SOC_K2L + osr_init(); +#endif + + /* + * just initialise the COM2 port so that TI specific + * UART register PWREMU_MGMT is initialized. Linux UART + * driver doesn't handle this. + */ + NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + + return 0; +} + +void reset_cpu(ulong addr) +{ + volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL); + u32 tmp; + + tmp = *rstctrl & KS2_RSTCTRL_MASK; + *rstctrl = tmp | KS2_RSTCTRL_KEY; + + *rstctrl &= KS2_RSTCTRL_SWRST; + + for (;;) + ; +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +#endif +} diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c new file mode 100644 index 0000000000..11a9357db4 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/keystone.c @@ -0,0 +1,87 @@ +/* + * Keystone EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/** + * cpu_to_bus - swap bytes of the 32-bit data if the device is BE + * @ptr - array of data + * @length - lenght of data array + */ +int cpu_to_bus(u32 *ptr, u32 length) +{ + u32 i; + + if (!(readl(KS2_DEVSTAT) & 0x1)) + for (i = 0; i < length; i++, ptr++) + *ptr = cpu_to_be32(*ptr); + + return 0; +} + +static int turn_off_myself(void) +{ + printf("Turning off ourselves\r\n"); + mon_power_off(0); + + psc_disable_module(KS2_LPSC_TETRIS); + psc_disable_domain(KS2_TETRIS_PWR_DOMAIN); + + asm volatile ("isb\n" + "dsb\n" + "wfi\n"); + + printf("What! Should not see that\n"); + return 0; +} + +static void turn_off_all_dsps(int num_dsps) +{ + int i; + + for (i = 0; i < num_dsps; i++) { + if (psc_disable_module(i + KS2_LPSC_GEM_0)) + printf("Cannot disable module for #%d DSP", i); + + if (psc_disable_domain(i + 8)) + printf("Cannot disable domain for #%d DSP", i); + } +} + +int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return turn_off_myself(); +} + +U_BOOT_CMD( + killme, 1, 0, do_killme_cmd, + "turn off main ARM core", + "turn off main ARM core. Should not live after that :(\n" +); + +int misc_init_r(void) +{ + char *env; + long ks2_debug = 0; + + env = getenv("ks2_debug"); + + if (env) + ks2_debug = simple_strtol(env, NULL, 0); + + if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0) + turn_off_all_dsps(KS2_NUM_DSPS); + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c new file mode 100644 index 0000000000..7899141d54 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/msmc.c @@ -0,0 +1,94 @@ +/* + * MSMC controller utilities + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct mpax { + u32 mpaxl; + u32 mpaxh; +}; + +struct msms_regs { + u32 pid; + u32 _res_04; + u32 smcerrar; + u32 smcerrxr; + u32 smedcc; + u32 smcea; + u32 smsecc; + u32 smpfar; + u32 smpfxr; + u32 smpfr; + u32 smpfcr; + u32 _res_2c; + u32 sbndc[8]; + u32 sbndm; + u32 sbnde; + u32 _res_58; + u32 cfglck; + u32 cfgulck; + u32 cfglckstat; + u32 sms_mpax_lck; + u32 sms_mpax_ulck; + u32 sms_mpax_lckstat; + u32 ses_mpax_lck; + u32 ses_mpax_ulck; + u32 ses_mpax_lckstat; + u32 smestat; + u32 smirstat; + u32 smirc; + u32 smiestat; + u32 smiec; + u32 _res_94_c0[12]; + u32 smncerrar; + u32 smncerrxr; + u32 smncea; + u32 _res_d0_1fc[76]; + struct mpax sms[16][8]; + struct mpax ses[16][8]; +}; + + +void msmc_share_all_segments(int priv_id) +{ + struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; + int j; + + for (j = 0; j < 8; j++) { + msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful; + msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful; + } +} + +void msmc_map_ses_segment(int priv_id, int ses_pair, + u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size) +{ + struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; + + msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 | + (size & 0x1f) | 0x80; + msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f; +} + +void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax) +{ + struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; + + *mpax++ = msmc->ses[priv_id][ses_pair].mpaxl; + *mpax = msmc->ses[priv_id][ses_pair].mpaxh; +} + +void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax) +{ + struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; + + msmc->ses[priv_id][ses_pair].mpaxl = *mpax++; + msmc->ses[priv_id][ses_pair].mpaxh = *mpax; +} diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c new file mode 100644 index 0000000000..237e776e87 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/psc.c @@ -0,0 +1,227 @@ +/* + * Keystone: PSC configuration module + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int psc_delay(void) +{ + udelay(10); + return 10; +} + +/* + * FUNCTION PURPOSE: Wait for end of transitional state + * + * DESCRIPTION: Polls pstat for the selected domain and waits for transitions + * to be complete. + * + * Since this is boot loader code it is *ASSUMED* that interrupts + * are disabled and no other core is mucking around with the psc + * at the same time. + * + * Returns 0 when the domain is free. Returns -1 if a timeout + * occurred waiting for the completion. + */ +int psc_wait(u32 domain_num) +{ + u32 retry; + u32 ptstat; + + /* + * Do nothing if the power domain is in transition. This should never + * happen since the boot code is the only software accesses psc. + * It's still remotely possible that the hardware state machines + * initiate transitions. + * Don't trap if the domain (or a module in this domain) is + * stuck in transition. + */ + retry = 0; + + do { + ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT); + ptstat = ptstat & (1 << domain_num); + } while ((ptstat != 0) && ((retry += psc_delay()) < + PSC_PTSTAT_TIMEOUT_LIMIT)); + + if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT) + return -1; + + return 0; +} + +u32 psc_get_domain_num(u32 mod_num) +{ + u32 domain_num; + + /* Get the power domain associated with the module number */ + domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); + domain_num = PSC_REG_MDCFG_GET_PD(domain_num); + + return domain_num; +} + +/* + * FUNCTION PURPOSE: Power up/down a module + * + * DESCRIPTION: Powers up/down the requested module and the associated power + * domain if required. No action is taken it the module is + * already powered up/down. + * + * This only controls modules. The domain in which the module + * resides will be left in the power on state. Multiple modules + * can exist in a power domain, so powering down the domain based + * on a single module is not done. + * + * Returns 0 on success, -1 if the module can't be powered up, or + * if there is a timeout waiting for the transition. + */ +int psc_set_state(u32 mod_num, u32 state) +{ + u32 domain_num; + u32 pdctl; + u32 mdctl; + u32 ptcmd; + u32 reset_iso; + u32 v; + + /* + * Get the power domain associated with the module number, and reset + * isolation functionality + */ + v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); + domain_num = PSC_REG_MDCFG_GET_PD(v); + reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v); + + /* Wait for the status of the domain/module to be non-transitional */ + if (psc_wait(domain_num) != 0) + return -1; + + /* + * Perform configuration even if the current status matches the + * existing state + * + * Set the next state of the power domain to on. It's OK if the domain + * is always on. This code will not ever power down a domain, so no + * change is made if the new state is power down. + */ + if (state == PSC_REG_VAL_MDCTL_NEXT_ON) { + pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); + pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, + PSC_REG_VAL_PDCTL_NEXT_ON); + __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); + } + + /* Set the next state for the module to enabled/disabled */ + mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state); + mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso); + __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + + /* Trigger the enable */ + ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); + ptcmd |= (u32)(1< + +/* + * These weak functions are available to kona architectures that don't + * require clock enables from the driver code. + */ +int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) +{ + return 0; +} + +int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep) +{ + return 0; +} + +int __weak clk_usb_otg_enable(void *base) +{ + return 0; +} diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c new file mode 100644 index 0000000000..2b3a84051c --- /dev/null +++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c @@ -0,0 +1,16 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/kona-common/s_init.c b/arch/arm/cpu/armv7/kona-common/s_init.c new file mode 100644 index 0000000000..6066a73c54 --- /dev/null +++ b/arch/arm/cpu/armv7/kona-common/s_init.c @@ -0,0 +1,12 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Early system init. Currently empty. + */ +void s_init(void) +{ +} diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index cf477a978f..d71c84fae5 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -26,11 +26,11 @@ ENTRY(lowlevel_init) #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #ifdef CONFIG_SPL_BUILD - ldr r8, =gdata + ldr r9, =gdata #else - sub sp, #GD_SIZE + sub sp, sp, #GD_SIZE bic sp, sp, #7 - mov r8, sp + mov r9, sp #endif /* * Save the old lr(passed in ip) and the current lr to stack diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile new file mode 100644 index 0000000000..2e6a20757f --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -0,0 +1,14 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += clock.o +obj-y += timer.o +obj-y += fsl_epu.o + +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o +obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c new file mode 100644 index 0000000000..8f80c6175f --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -0,0 +1,130 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#endif + +void get_sys_info(struct sys_info *sys_info) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#ifdef CONFIG_FSL_IFC + struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + u32 ccr; +#endif + struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR); + unsigned int cpu; + const u8 core_cplx_pll[6] = { + [0] = 0, /* CC1 PPL / 1 */ + [1] = 0, /* CC1 PPL / 2 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 1, /* CC2 PPL / 2 */ + }; + + const u8 core_cplx_pll_div[6] = { + [0] = 1, /* CC1 PPL / 1 */ + [1] = 2, /* CC1 PPL / 2 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 2, /* CC2 PPL / 2 */ + }; + + uint i; + uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + + sys_info->freq_systembus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#else + sys_info->freq_ddrbus = sysclk; +#endif + + sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> + RCWSR0_SYS_PLL_RAT_SHIFT) & RCWSR0_SYS_PLL_RAT_MASK; + sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >> + RCWSR0_MEM_PLL_RAT_SHIFT) & RCWSR0_MEM_PLL_RAT_MASK; + + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; + if (ratio[i] > 4) + freq_c_pll[i] = sysclk * ratio[i]; + else + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; + } + + for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) { + u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + & 0xf; + u32 cplx_pll = core_cplx_pll[c_pll_sel]; + + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } + +#if defined(CONFIG_FSL_IFC) + ccr = in_be32(&ifc_regs->ifc_ccr); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; + + sys_info->freq_localbus = sys_info->freq_systembus / ccr; +#endif +} + +int get_clocks(void) +{ + struct sys_info sys_info; + + get_sys_info(&sys_info); + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus * 2; + +#if defined(CONFIG_FSL_ESDHC) + gd->arch.sdhc_clk = gd->bus_clk; +#endif + + return 0; +} + +ulong get_bus_freq(ulong dummy) +{ + return gd->bus_clk; +} + +ulong get_ddr_freq(ulong dummy) +{ + return gd->mem_clk; +} + +int get_serial_clock(void) +{ + return gd->bus_clk / 2; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_I2C_CLK: + return get_bus_freq(0) / 2; + case MXC_ESDHC_CLK: + return get_bus_freq(0); + case MXC_DSPI_CLK: + return get_bus_freq(0) / 2; + case MXC_UART_CLK: + return get_bus_freq(0) / 2; + default: + printf("Unsupported clock\n"); + } + return 0; +} diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c new file mode 100644 index 0000000000..ce2d92f5a6 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -0,0 +1,137 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "fsl_epu.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + char buf1[32], buf2[32]; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major, minor, ver, i; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + minor = SVR_MIN(svr); + + puts("CPU: Freescale LayerScape "); + + ver = SVR_SOC_VER(svr); + switch (ver) { + case SOC_VER_SLS1020: + puts("SLS1020"); + break; + case SOC_VER_LS1020: + puts("LS1020"); + break; + case SOC_VER_LS1021: + puts("LS1021"); + break; + case SOC_VER_LS1022: + puts("LS1022"); + break; + default: + puts("Unknown"); + break; + } + + if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020)) + puts("E"); + + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); + + puts("Clock Configuration:"); + + printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk)); + printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk)); + printf("DDR:%-4s MHz (%s MT/s data rate), ", + strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk)); + puts("\n"); + + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + return 0; +} +#endif + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +#ifdef CONFIG_FSL_ESDHC +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + +int cpu_eth_init(bd_t *bis) +{ +#ifdef CONFIG_TSEC_ENET + tsec_standard_init(bis); +#endif + + return 0; +} + +int arch_cpu_init(void) +{ + void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + + /* + * After wakeup from deep sleep, Clear EPU registers + * as early as possible to prevent from possible issue. + * It's also safe to clear at normal boot. + */ + fsl_epu_clean(epu_base); + + return 0; +} + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Set the address at which the secondary core starts from.*/ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->scratchrw[0], addr); +} + +/* Release the secondary core from holdoff state and kick it */ +void smp_kick_all_cpus(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->brrl, 0x2); +} +#endif diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c new file mode 100644 index 0000000000..71a175392f --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -0,0 +1,185 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_FSL_ESDHC +#include +#endif +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void ft_fixup_enet_phy_connect_type(void *fdt) +{ + struct eth_device *dev; + struct tsec_private *priv; + const char *enet_path, *phy_path; + char enet[16]; + char phy[16]; + int phy_node; + int i = 0; + int enet_id = 0; + uint32_t ph; + + while ((dev = eth_get_dev_by_index(i++)) != NULL) { + if (strstr(dev->name, "eTSEC1")) + enet_id = 0; + else if (strstr(dev->name, "eTSEC2")) + enet_id = 1; + else if (strstr(dev->name, "eTSEC3")) + enet_id = 2; + else + continue; + + priv = dev->priv; + if (priv->flags & TSEC_SGMII) + continue; + + sprintf(enet, "ethernet%d", enet_id); + enet_path = fdt_get_alias(fdt, enet); + if (!enet_path) + continue; + + sprintf(phy, "enet%d_rgmii_phy", enet_id); + phy_path = fdt_get_alias(fdt, phy); + if (!phy_path) + continue; + + phy_node = fdt_path_offset(fdt, phy_path); + if (phy_node < 0) + continue; + + ph = fdt_create_phandle(fdt, phy_node); + if (ph) + do_fixup_by_path_u32(fdt, enet_path, + "phy-handle", ph, 1); + + do_fixup_by_path(fdt, enet_path, "phy-connection-type", + phy_string_for_interface( + PHY_INTERFACE_MODE_RGMII_ID), + sizeof(phy_string_for_interface( + PHY_INTERFACE_MODE_RGMII_ID)), + 1); + } +} + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + int off; + int val; + const char *sysclk_path; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr; + svr = in_be32(&gur->svr); + + unsigned long busclk = get_bus_freq(0); + + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(svr)) + fdt_fixup_crypto_node(blob, 0); +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 + else { + ccsr_sec_t __iomem *sec; + + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); + } +#endif + + fdt_fixup_ethernet(blob); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + val = gd->cpu_clk; + fdt_setprop(blob, off, "clock-frequency", &val, 4); + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + do_fixup_by_prop_u32(blob, "device_type", "soc", + 4, "bus-frequency", busclk, 1); + + ft_fixup_enet_phy_connect_type(blob); + +#ifdef CONFIG_SYS_NS16550 + do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); +#endif + + sysclk_path = fdt_get_alias(blob, "sysclk"); + if (sysclk_path) + do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency", + CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + +#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT) +#define UBOOT_HEAD_LEN 0x1000 + /* + * Reserved memory in SD boot deep sleep case. + * Second stage uboot binary and malloc space should be reserved. + * If the memory they occupied has not been reserved, then this + * space would be used by kernel and overwritten in uboot when + * deep sleep resume, which cause deep sleep failed. + * Since second uboot binary has a head, that space need to be + * reserved either(assuming its size is less than 0x1000). + */ + off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN, + CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE + + UBOOT_HEAD_LEN); + if (off < 0) + printf("Failed to reserve memory for SD boot deep sleep: %s\n", + fdt_strerror(off)); +#endif + +#if defined(CONFIG_FSL_ESDHC) + fdt_fixup_esdhc(blob, bd); +#endif + + /* + * platform bus clock = system bus clock/2 + * Here busclk = system bus clock + * We are using the platform bus clock as 1588 Timer reference + * clock source select + */ + do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer", + "timer-frequency", busclk / 2, 1); + + /* + * clock-freq should change to clock-frequency and + * flexcan-v1.0 should change to p1010-flexcan respectively + * in the future. + */ + do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", + "clock_freq", busclk / 2, 1); + + do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", + "clock-frequency", busclk / 2, 1); + + do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", + "clock-frequency", busclk / 2, 1); + +#ifdef CONFIG_QSPI_BOOT + off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, + CONFIG_SYS_IFC_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +#else + off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, + QSPI0_BASE_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); + off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, + DSPI1_BASE_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +#endif +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c new file mode 100644 index 0000000000..6212640d14 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -0,0 +1,57 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "fsl_epu.h" + +/** + * fsl_epu_clean - Clear EPU registers + */ +void fsl_epu_clean(void *epu_base) +{ + u32 offset; + + /* follow the exact sequence to clear the registers */ + /* Clear EPACRn */ + for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPEVTCRn */ + for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPGCR */ + out_be32(epu_base + EPGCR, 0); + + /* Clear EPSMCRn */ + for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCCRn */ + for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCMPRn */ + for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCTRn */ + for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPIMCRn */ + for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPXTRIGCRn */ + out_be32(epu_base + EPXTRIGCR, 0); + + /* Clear EPECRn */ + for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE) + out_be32(epu_base + offset, 0); +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h new file mode 100644 index 0000000000..d658aad2ea --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h @@ -0,0 +1,68 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_EPU_H +#define __FSL_EPU_H + +#include + +#define FSL_STRIDE_4B 4 +#define FSL_STRIDE_8B 8 + +/* Block offsets */ +#define EPU_BLOCK_OFFSET 0x00000000 + +/* EPGCR (Event Processor Global Control Register) */ +#define EPGCR 0x000 + +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */ +#define EPEVTCR0 0x050 +#define EPEVTCR9 0x074 +#define EPEVTCR_STRIDE FSL_STRIDE_4B + +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ +#define EPXTRIGCR 0x090 + +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */ +#define EPIMCR0 0x100 +#define EPIMCR31 0x17C +#define EPIMCR_STRIDE FSL_STRIDE_4B + +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */ +#define EPSMCR0 0x200 +#define EPSMCR15 0x278 +#define EPSMCR_STRIDE FSL_STRIDE_8B + +/* EPECR0-15 (Event Processor Event Control Registers) */ +#define EPECR0 0x300 +#define EPECR15 0x33C +#define EPECR_STRIDE FSL_STRIDE_4B + +/* EPACR0-15 (Event Processor Action Control Registers) */ +#define EPACR0 0x400 +#define EPACR15 0x43C +#define EPACR_STRIDE FSL_STRIDE_4B + +/* EPCCRi0-15 (Event Processor Counter Control Registers) */ +#define EPCCR0 0x800 +#define EPCCR15 0x83C +#define EPCCR31 0x87C +#define EPCCR_STRIDE FSL_STRIDE_4B + +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */ +#define EPCMPR0 0x900 +#define EPCMPR15 0x93C +#define EPCMPR31 0x97C +#define EPCMPR_STRIDE FSL_STRIDE_4B + +/* EPCTR0-31 (Event Processor Counter Register) */ +#define EPCTR0 0xA00 +#define EPCTR31 0xA7C +#define EPCTR_STRIDE FSL_STRIDE_4B + +void fsl_epu_clean(void *epu_base); + +#endif diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c new file mode 100644 index 0000000000..9b78acb25a --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -0,0 +1,120 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "fsl_ls1_serdes.h" + +#ifdef CONFIG_SYS_FSL_SRDS_1 +static u64 serdes1_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 +static u64 serdes2_prtcl_map; +#endif + +int is_serdes_configured(enum srds_prtcl device) +{ + u64 ret = 0; + +#ifdef CONFIG_SYS_FSL_SRDS_1 + ret |= (1ULL << device) & serdes1_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + ret |= (1ULL << device) & serdes2_prtcl_map; +#endif + + return !!ret; +} + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg = in_be32(&gur->rcwsr[4]); + int i; + + switch (sd) { +#ifdef CONFIG_SYS_FSL_SRDS_1 + case FSL_SRDS_1: + cfg &= RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + break; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + case FSL_SRDS_2: + cfg &= RCWSR4_SRDS2_PRTCL_MASK; + cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT; + break; +#endif + default: + printf("invalid SerDes%d\n", sd); + break; + } + /* Is serdes enabled at all? */ + if (unlikely(cfg == 0)) + return -ENODEV; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(sd, cfg, i) == device) + return i; + } + + return -ENODEV; +} + +u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u64 serdes_prtcl_map = 0; + u32 cfg; + int lane; + + cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; + cfg >>= sd_prctl_shift; + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); + + serdes_prtcl_map |= (1ULL << lane_prtcl); + } + + return serdes_prtcl_map; +} + +void fsl_serdes_init(void) +{ +#ifdef CONFIG_SYS_FSL_SRDS_1 + serdes1_prtcl_map = serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_SERDES_ADDR, + RCWSR4_SRDS1_PRTCL_MASK, + RCWSR4_SRDS1_PRTCL_SHIFT); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes2_prtcl_map = serdes_init(FSL_SRDS_2, + CONFIG_SYS_FSL_SERDES_ADDR + + FSL_SRDS_2 * 0x1000, + RCWSR4_SRDS2_PRTCL_MASK, + RCWSR4_SRDS2_PRTCL_SHIFT); +#endif +} + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + default: + return "100"; + } +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h new file mode 100644 index 0000000000..834aa532bf --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h @@ -0,0 +1,12 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS1_SERDES_H +#define __FSL_LS1_SERDES_H + +int is_serdes_prtcl_valid(int serdes, u32 prtcl); +int serdes_lane_enabled(int lane); +#endif /* __FSL_LS1_SERDES_H */ diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c new file mode 100644 index 0000000000..cc53910bbb --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c @@ -0,0 +1,41 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x10] = {PCIE1, SATA1, PCIE2, PCIE2}, + [0x20] = {PCIE1, SGMII_TSEC1, PCIE2, SGMII_TSEC2}, + [0x30] = {PCIE1, SATA1, SGMII_TSEC1, SGMII_TSEC2}, + [0x40] = {PCIE1, PCIE1, SATA1, SGMII_TSEC2}, + [0x50] = {PCIE1, PCIE1, PCIE2, SGMII_TSEC2}, + [0x60] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x70] = {PCIE1, SATA1, PCIE2, SGMII_TSEC2}, + [0x80] = {PCIE2, PCIE2, PCIE2, PCIE2}, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c new file mode 100644 index 0000000000..1dfbf54802 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif + return BOOT_DEVICE_NAND; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + case BOOT_DEVICE_NAND: + return 0; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c new file mode 100644 index 0000000000..11b17b2c74 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -0,0 +1,127 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * This function is intended for SHORT delays only. + * It will overflow at around 10 seconds @ 400MHz, + * or 20 seconds @ 200MHz. + */ +unsigned long usec2ticks(unsigned long usec) +{ + ulong ticks; + + if (usec < 1000) + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + else + ticks = ((usec / 10) * (get_tbclk() / 100000)); + + return ticks; +} + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + unsigned long freq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + tick *= CONFIG_SYS_HZ; + do_div(tick, freq); + + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long usec) +{ + unsigned long freq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + usec = usec * freq + 999999; + do_div(usec, 1000000); + + return usec; +} + +int timer_init(void) +{ + struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; + unsigned long ctrl, val, freq; + + /* Enable System Counter */ + writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); + + freq = GENERIC_TIMER_CLK; + asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + /* Set PL1 Physical Timer Ctrl */ + ctrl = ARCH_TIMER_CTRL_ENABLE; + asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); + + /* Set PL1 Physical Comp Value */ + val = TIMER_COMP_VAL; + asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val)); + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +unsigned long long get_ticks(void) +{ + unsigned long long now; + + asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now)); + + gd->arch.tbl = (unsigned long)(now & 0xffffffff); + gd->arch.tbu = (unsigned long)(now >> 32); + + return now; +} + +unsigned long get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +unsigned long get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* delay x useconds and preserve advance timstamp value */ +void __udelay(unsigned long usec) +{ + unsigned long long start; + unsigned long tmo; + + start = get_ticks(); /* get current timestamp */ + tmo = us_to_tick(usec); /* convert usecs to ticks */ + + while ((get_ticks() - start) < tmo) + ; /* loop till time has passed */ +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +unsigned long get_tbclk(void) +{ + unsigned long freq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + return freq; +} diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile index 7c86ae3ea5..93b5378b6b 100644 --- a/arch/arm/cpu/armv7/mx5/Makefile +++ b/arch/arm/cpu/armv7/mx5/Makefile @@ -7,26 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := soc.o clock.o +obj-y += lowlevel_init.o -LIB = $(obj)lib$(SOC).o - -COBJS = soc.o clock.o -SOBJS = lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_SECURE_BOOT) += hab.o diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c deleted file mode 100644 index ddb1898f36..0000000000 --- a/arch/arm/cpu/armv7/mx5/asm-offsets.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include - -int main(void) -{ - - /* Round up to make sure size gives nice stack alignment */ - DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); - DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); - DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); - DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); - DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); - DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); - DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); - DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); - DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); - DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); - DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); - DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); - DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); - DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); - DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); - DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); - DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); - DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); - DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); - DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); - DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); - DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); - DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); - DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); - DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); - DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); - DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); - DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); - DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); - DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); - DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); - DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); - DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); - DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); -#if defined(CONFIG_MX53) - DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); -#endif - - /* DPLL */ - DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); - DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); - DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); - DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); - DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); - DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); - DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); - DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); - - return 0; -} diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index fe2f86f2d8..ed6072fdc7 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -20,7 +20,7 @@ enum pll_clocks { PLL1_CLOCK = 0, PLL2_CLOCK, PLL3_CLOCK, -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 PLL4_CLOCK, #endif PLL_CLOCKS, @@ -30,7 +30,7 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR, #endif }; @@ -174,7 +174,7 @@ void set_usboh3_clk(void) MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1)); } -void enable_usboh3_clk(unsigned char enable) +void enable_usboh3_clk(bool enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; @@ -243,7 +243,7 @@ void ipu_di_clk_disable(int di) } } -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 void ldb_clk_enable(int ldb) { switch (ldb) { @@ -277,15 +277,15 @@ void ldb_clk_disable(int ldb) } #endif -#ifdef CONFIG_I2C_MXC +#ifdef CONFIG_SYS_I2C_MXC /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { u32 mask; -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) if (i2c_num > 1) -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) if (i2c_num > 2) #endif return -EINVAL; @@ -304,8 +304,8 @@ void set_usb_phy_clk(void) clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); } -#if defined(CONFIG_MX51) -void enable_usb_phy1_clk(unsigned char enable) +#if defined(CONFIG_SOC_MX51) +void enable_usb_phy1_clk(bool enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; @@ -314,12 +314,12 @@ void enable_usb_phy1_clk(unsigned char enable) MXC_CCM_CCGR2_USB_PHY(cg)); } -void enable_usb_phy2_clk(unsigned char enable) +void enable_usb_phy2_clk(bool enable) { /* i.MX51 has a single USB PHY clock, so do nothing here. */ } -#elif defined(CONFIG_MX53) -void enable_usb_phy1_clk(unsigned char enable) +#elif defined(CONFIG_SOC_MX53) +void enable_usb_phy1_clk(bool enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; @@ -328,7 +328,7 @@ void enable_usb_phy1_clk(unsigned char enable) MXC_CCM_CCGR4_USB_PHY1(cg)); } -void enable_usb_phy2_clk(unsigned char enable) +void enable_usb_phy2_clk(bool enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; @@ -393,7 +393,7 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) return ret; } -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 /* * This function returns the Frequency Pre-Multiplier clock. */ @@ -420,9 +420,9 @@ static u32 get_lp_apm(void) u32 ccsr = readl(&mxc_ccm->ccsr); if (ccsr & MXC_CCM_CCSR_LP_APM) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) ret_val = get_fpm(); -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); #endif else @@ -644,7 +644,7 @@ static u32 get_ddr_clk(void) u32 ret_val = 0; u32 cbcmr = readl(&mxc_ccm->cbcmr); u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 u32 cbcdr = readl(&mxc_ccm->cbcdr); if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) { u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr); @@ -878,7 +878,7 @@ static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) /* Switch back */ __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr); break; -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 case PLL4_CLOCK: /* Switch to pll4 bypass clock */ __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr); @@ -981,6 +981,18 @@ void enable_nfc_clk(unsigned char enable) MXC_CCM_CCGR5_EMI_ENFC(cg)); } +#ifdef CONFIG_FSL_IIM +void enable_efuse_prog_supply(bool enable) +{ + if (enable) + setbits_le32(&mxc_ccm->cgpr, + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); + else + clrbits_le32(&mxc_ccm->cgpr, + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); +} +#endif + /* Config main_bus_clock for periphs */ static int config_periph_clk(u32 ref, u32 freq) { @@ -1107,7 +1119,7 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) return 0; } -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 /* * The clock for the external interface can be set to use internal clock * if fuse bank 4, row 3, bit 2 is set. @@ -1154,7 +1166,7 @@ static int do_mx5_showclocks(void) pr_clk_val(PLL2, freq); freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); pr_clk_val(PLL3, freq); -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); pr_clk_val(PLL4, freq); #endif diff --git a/arch/arm/cpu/armv7/mx5/hab.c b/arch/arm/cpu/armv7/mx5/hab.c new file mode 100644 index 0000000000..8d5949f24a --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/hab.c @@ -0,0 +1,348 @@ +/* + * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +HAB_FUNC(entry, hab_status_t) +HAB_FUNC(exit, hab_status_t) +HAB_FUNC5(authenticate_image, void *, uint8_t, size_t, void **, size_t *, hab_loader_callback_f_t) +HAB_FUNC2(report_status, hab_status_t, hab_config_t *, hab_state_t *) +HAB_FUNC4(report_event, hab_status_t, hab_status_t, uint32_t, uint8_t *, size_t *) +HAB_FUNC3(check_target, hab_status_t, uint8_t, const void *, size_t) +HAB_FUNC3(assert, hab_status_t, uint8_t, const void *, size_t) + +struct mx53_ivt { + u32 header; + u32 app_start_addr; + u32 rsrvd1; + void *dcd_ptr; + struct mx53_boot_data *boot_data; + void *self; + void *csf; + u32 rsrvd2; +}; + +struct mx53_boot_data { + void *start; + u32 length; + u32 plugin; +}; + +#define IVT_SIZE 0x20 +#define ALIGN_SIZE 0x400 +#define CSF_PAD_SIZE 0x2000 + +/* + * +------------+ 0x0 (DDR_UIMAGE_START) - + * | Header | | + * +------------+ 0x40 | + * | | | + * | | | + * | | | + * | | | + * | Image Data | | + * . | | + * . | > Stuff to be authenticated ----+ + * . | | | + * | | | | + * | | | | + * +------------+ | | + * | | | | + * | Fill Data | | | + * | | | | + * +------------+ Align to ALIGN_SIZE | | + * | IVT | | | + * +------------+ + IVT_SIZE - | + * | | | + * | CSF DATA | <---------------------------------------------------------+ + * | | + * +------------+ + * | | + * | Fill Data | + * | | + * +------------+ + CSF_PAD_SIZE + */ + +static inline int read_fuse(unsigned bank, unsigned row) +{ + struct iim_regs *iim_regs = (void *)IMX_IIM_BASE; + u32 *fuses; + + if (bank > ARRAY_SIZE(iim_regs->bank)) + return -EINVAL; + fuses = iim_regs->bank[bank].fuse_regs; + + debug("Reading fuse bank %u row %u @ %p\n", bank, row, &fuses[row]); + return readl(&fuses[row]); +} + +static bool is_hab_enabled(void) +{ +#ifdef DEBUG + static int first = 1; + + if (first) { + debug("rvt_base=%p\n", hab_rvt_base()); + debug("hab_rvt_entry=%p\n", hab_rvt_entry_p); + debug("hab_rvt_exit=%p\n", hab_rvt_exit_p); + debug("hab_rvt_check_target=%p\n", hab_rvt_check_target_p); + debug("hab_rvt_authenticate_image=%p\n", hab_rvt_authenticate_image_p); + debug("hab_rvt_report_event=%p\n", hab_rvt_report_event_p); + debug("hab_rvt_report_status=%p\n", hab_rvt_report_status_p); + debug("hab_rvt_assert=%p\n", hab_rvt_assert_p); + first = 0; + } +#endif + return read_fuse(0, 4) & (1 << 1); +} + +static void mx53_hab_display_event(uint8_t *event_data, size_t bytes) +{ + uint32_t i; + + if (!(event_data && bytes > 0)) + return; + + for (i = 0; i < bytes; i++) { + if (i == 0) + printf("\t0x%02x", event_data[i]); + else if ((i % 8) == 0) + printf("\n\t0x%02x", event_data[i]); + else + printf(" 0x%02x", event_data[i]); + } +} + +static inline void mx53_hab_pr_fuse_val(unsigned bank, unsigned row) +{ + printf(" %02x", read_fuse(bank, row)); +} + +static inline void mx53_hab_dump_srk_hash(void) +{ + int i; + + printf("SRK hash:\n\t"); + mx53_hab_pr_fuse_val(1, 1); + for (i = 1; i <= 31; i++) { + if (i % 8 == 0) + printf("\n\t"); + mx53_hab_pr_fuse_val(3, i); + } + printf("\n"); +} + +int get_hab_status(void) +{ + static uint32_t last_hab_event __attribute__((section(".data"))); + uint32_t index = last_hab_event; /* Loop index */ + uint8_t event_data[128]; /* Event data buffer */ + size_t bytes = sizeof(event_data); /* Event size in bytes */ + enum hab_config config; + enum hab_state state; + int ret; + int hab_debug = getenv_yesno("hab_debug") == 1; + + if (hab_debug) { + if (is_hab_enabled()) { + printf("Secure boot enabled\n\t"); + } else { + printf("Secure boot disabled\n"); + } + mx53_hab_dump_srk_hash(); + } + + /* Check HAB status */ + config = state = 0; /* ROM code assumes short enums! */ + ret = hab_rvt_report_status(&config, &state); + if (hab_debug || ret != HAB_SUCCESS) + printf("HAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + if (ret != HAB_SUCCESS) { + /* Display HAB Error events */ + while (hab_rvt_report_event(HAB_STS_ANY, index, event_data, + &bytes) == HAB_SUCCESS) { + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + mx53_hab_display_event(event_data, bytes); + puts("\n"); + bytes = sizeof(event_data); + index++; + } + ret = index - last_hab_event; + last_hab_event = index; + } else { + /* Display message if no HAB events are found */ + if (hab_debug) + puts("No HAB Events Found!\n"); + ret = 0; + } + return ret; +} + +static inline hab_status_t hab_init(void) +{ + hab_status_t ret; + + ret = hab_rvt_entry(); + debug("hab_rvt_entry() returned %02x\n", ret); + if (ret != HAB_SUCCESS) { + printf("hab entry function failed: %02x\n", ret); + } + + return ret; +} + +static inline hab_status_t hab_exit(void) +{ + hab_status_t ret; + + ret = hab_rvt_exit(); + if (ret != HAB_SUCCESS) + printf("hab exit function failed: %02x\n", ret); + + return ret; +} + +static hab_status_t hab_check_target(hab_target_t type, uint32_t addr, size_t len) +{ + hab_status_t ret; + + ret = hab_init(); + if (ret != HAB_SUCCESS) + return ret; + + ret = hab_rvt_check_target(type, (void *)addr, len); + if (ret != HAB_SUCCESS) { + printf("check_target(0x%08x, 0x%08x) failed: %d\n", + addr, len, ret); + return ret; + } + ret = hab_exit(); + + if (ret == HAB_SUCCESS && get_hab_status() > 0) { + return HAB_FAILURE; + } + return ret; +} + +static hab_status_t hab_assert(uint32_t type, uint32_t addr, size_t len) +{ + hab_status_t ret; + + ret = hab_init(); + if (ret != HAB_SUCCESS) + return ret; + + ret = hab_rvt_assert(type, (void *)addr, len); + if (ret != HAB_SUCCESS) { + printf("assert(0x%08x, 0x%08x) failed: %d\n", + addr, len, ret); + return ret; + } + ret = hab_exit(); + + if (ret == HAB_SUCCESS && get_hab_status() > 0) { + return HAB_FAILURE; + } + return ret; +} + +static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 1) + return CMD_RET_USAGE; + + get_hab_status(); + + return CMD_RET_SUCCESS; +} + +static int do_hab_check_target(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + hab_target_t type = HAB_TGT_MEMORY; + uint32_t addr; + size_t len; + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + len = simple_strtoul(argv[2], NULL, 16); + if (argc > 3) { + switch (argv[3][0]) { + case 'p': + case 'P': + type = HAB_TGT_PERIPHERAL; + break; + case 'm': + case 'M': + type = HAB_TGT_MEMORY; + break; + default: + printf("Invalid type '%s'\n", argv[3]); + return CMD_RET_USAGE; + } + } + if (hab_check_target(type, addr, len) != HAB_SUCCESS) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_hab_assert(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + uint32_t type = 0; + uint32_t addr; + size_t len; + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + len = simple_strtoul(argv[2], NULL, 16); + if (argc > 3) { + type = simple_strtoul(argv[3], NULL, 16); + } + + if (hab_assert(type, addr, len) != HAB_SUCCESS) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, + "display HAB status", + "" + ); + +U_BOOT_CMD( + hab_check_target, 4, 0, do_hab_check_target, + "verify an address range via HAB", + "addr len [type]\n" + "\t\taddr -\taddress to verify\n" + "\t\tlen -\tlength of addr range to verify\n" + ); + +U_BOOT_CMD( + hab_assert, 4, 0, do_hab_assert, + "Test an assertion against the HAB audit log", + "addr len [type]\n" + "\t\taddr -\taddress to verify\n" + "\t\tlen -\tlength of addr range to verify\n" + ); diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index d6edb3f155..6273b7aac8 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -31,12 +31,12 @@ /* reconfigure L2 cache aux control reg */ ldr r0, =0xC0 | /* tag RAM */ \ - 0x4 | /* data RAM */ \ - 1 << 24 | /* disable write allocate delay */ \ - 1 << 23 | /* disable write allocate combine */ \ - 1 << 22 /* disable write allocate */ + 0x4 | /* data RAM */ \ + 1 << 24 | /* disable write allocate delay */ \ + 1 << 23 | /* disable write allocate combine */ \ + 1 << 22 /* disable write allocate */ -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 @@ -45,6 +45,12 @@ #endif mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #2 + mcr 15, 0, r0, c1, c0, 1 + .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. @@ -70,7 +76,7 @@ /* M4IF setup */ .macro init_m4if -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 /* VPU and IPU given higher priority (0x4) * IPU accesses with ID=0x1 given highest priority (=0xA) */ @@ -157,7 +163,7 @@ setup_pll_func: .macro init_clock ldr r0, =CCM_BASE_ADDR -#if defined (CONFIG_MX51) +#if defined (CONFIG_SOC_MX51) /* Gate off clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] @@ -270,7 +276,7 @@ setup_pll_func: mov r1, #0x000A0000 add r1, r1, #0x00000F0 str r1, [r0, #CLKCTL_CCOSR] -#else /* CONFIG_MX53 */ +#else /* CONFIG_SOC_MX53 */ /* Gate off clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] @@ -297,19 +303,20 @@ setup_pll_func: #error Unsupported CONFIG_SYS_CPU_CLK value #endif - setup_pll PLL3_BASE_ADDR, 400 + setup_pll PLL3_BASE_ADDR, 400 #ifndef CONFIG_TX53 - /* Switch peripheral to PLL3 */ - ldr r1, =0x00015154 - str r1, [r0, #CLKCTL_CBCMR] - ldr r1, =0x02898945 - str r1, [r0, #CLKCTL_CBCDR] - /* make sure change is effective */ + /* Switch peripheral to PLL3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00015154 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x02898945 + str r1, [r0, #CLKCTL_CBCDR] + /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] tst r1, #0x7f - bne 1b + bne 1b - setup_pll PLL2_BASE_ADDR, 400 + setup_pll PLL2_BASE_ADDR, 400 /* Switch peripheral to PLL2 */ ldr r1, =0x00888945 @@ -329,6 +336,8 @@ setup_pll_func: tst r1, #0x7f bne 1b + setup_pll PLL3_BASE_ADDR, 216 + setup_pll PLL4_BASE_ADDR, 455 #else /* CONFIG_TX53 */ @@ -403,21 +412,15 @@ setup_pll_func: str r1, [r0, #CLKCTL_CCGR6] str r1, [r0, #CLKCTL_CCGR7] - mov r1, #0x00000 - str r1, [r0, #CLKCTL_CCDR] - - /* for cko - for ARM div by 8 */ - mov r1, #0x000A0000 - add r1, r1, #0x00000F0 - str r1, [r0, #CLKCTL_CCOSR] + mov r1, #0x00000 + str r1, [r0, #CLKCTL_CCDR] -#endif /* CONFIG_MX53 */ -.endm + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] -.macro setup_wdog - ldr r0, =WDOG1_BASE_ADDR - mov r1, #0x30 - strh r1, [r0] +#endif /* CONFIG_SOC_MX53 */ .endm ENTRY(lowlevel_init) @@ -458,7 +461,7 @@ W_DP_800: .word DP_OP_800 .word DP_MFD_800 .word DP_MFN_800 #endif -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) W_DP_665: .word DP_OP_665 .word DP_MFD_665 .word DP_MFN_665 diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 978f8499ec..30b90e9d28 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -16,7 +16,7 @@ #include #include -#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53)) +#if !(defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)) #error "CPU_TYPE not defined" #endif @@ -39,14 +39,14 @@ void hw_watchdog_reset(void) u32 get_cpu_rev(void) { -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 int system_rev = 0x51000; #else int system_rev = 0x53000; #endif int reg = __raw_readl(ROM_SI_REV); -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) switch (reg) { case 0x02: system_rev |= CHIP_REV_1_1; @@ -106,49 +106,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) #endif -void set_chipselect_size(int const cs_size) -{ - unsigned int reg; - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - reg = readl(&iomuxc_regs->gpr1); - - switch (cs_size) { - case CS0_128: - reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ - reg |= 0x5; - break; - case CS0_64M_CS1_64M: - reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ - reg |= 0x1B; - break; - case CS0_64M_CS1_32M_CS2_32M: - reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ - reg |= 0x4B; - break; - case CS0_32M_CS1_32M_CS2_32M_CS3_32M: - reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ - reg |= 0x249; - break; - default: - printf("Unknown chip select size: %d\n", cs_size); - break; - } - - writel(reg, &iomuxc_regs->gpr1); -} - -void cpu_cache_initialization(void) -{ - printf("Enabling L2 cache\n"); - asm volatile( - "mrc 15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #0x2\n" - "mcr 15, 0, r0, c1, c0, 1\n" - : : : "r0", "memory" - ); -} - -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 void boot_mode_apply(unsigned cfg_val) { writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr); diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index c5e98582d0..bf6effc939 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -7,25 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = soc.o clock.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := soc.o clock.o +obj-$(CONFIG_SPL_BUILD) += ddr.o +obj-$(CONFIG_SECURE_BOOT) += hab.o +obj-$(CONFIG_MP) += mp.o diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 8a494b48e8..7f67941e17 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -14,7 +15,7 @@ enum pll_clocks { PLL_ARM, /* PLL1: ARM PLL */ - PLL_BUS, /* PLL2: System Bus PLL*/ + PLL_528, /* PLL2: System Bus PLL*/ PLL_USBOTG, /* PLL3: OTG USB PLL */ PLL_AUDIO, /* PLL4: Audio PLL */ PLL_VIDEO, /* PLL5: Video PLL */ @@ -33,7 +34,7 @@ int clk_enable(struct clk *clk) if (!clk) return 0; if (clk->usecount == 0) { -debug("%s: Enabling %s clock\n", __func__, clk->name); + debug("%s: Enabling %s clock\n", __func__, clk->name); ret = clk->enable(clk); if (ret) return ret; @@ -51,7 +52,7 @@ void clk_disable(struct clk *clk) assert(clk->usecount > 0); if (!(--clk->usecount)) { if (clk->disable) { -debug("%s: Disabling %s clock\n", __func__, clk->name); + debug("%s: Disabling %s clock\n", __func__, clk->name); clk->disable(clk); } } @@ -129,6 +130,35 @@ void enable_ocotp_clk(unsigned char enable) } #endif +#ifdef CONFIG_NAND_MXS +void setup_gpmi_io_clk(u32 cfg) +{ + /* Disable clocks per ERR007177 from MX6 errata */ + clrbits_le32(&imx_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + clrsetbits_le32(&imx_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + cfg); + + setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + setbits_le32(&imx_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); +} +#endif + void enable_usboh3_clk(unsigned char enable) { u32 reg; @@ -142,7 +172,68 @@ void enable_usboh3_clk(unsigned char enable) } -#ifdef CONFIG_I2C_MXC +#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX) +void enable_enet_clk(unsigned char enable) +{ + u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK; + + if (enable) + setbits_le32(&imx_ccm->CCGR1, mask); + else + clrbits_le32(&imx_ccm->CCGR1, mask); +} +#endif + +#ifdef CONFIG_MXC_UART +void enable_uart_clk(unsigned char enable) +{ + u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; + + if (enable) + setbits_le32(&imx_ccm->CCGR5, mask); + else + clrbits_le32(&imx_ccm->CCGR5, mask); +} +#endif + +#ifdef CONFIG_SPI +/* spi_num can be from 0 - 4 */ +int enable_cspi_clock(unsigned char enable, unsigned spi_num) +{ + u32 mask; + + if (spi_num > 4) + return -EINVAL; + + mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2); + if (enable) + setbits_le32(&imx_ccm->CCGR1, mask); + else + clrbits_le32(&imx_ccm->CCGR1, mask); + + return 0; +} +#endif + +#ifdef CONFIG_MMC +int enable_usdhc_clk(unsigned char enable, unsigned bus_num) +{ + u32 mask; + + if (bus_num > 3) + return -EINVAL; + + mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2); + if (enable) + setbits_le32(&imx_ccm->CCGR6, mask); + else + clrbits_le32(&imx_ccm->CCGR6, mask); + + return 0; +} +#endif + +#ifdef CONFIG_SYS_I2C_MXC /* i2c_num can be from 0 - 2 */ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { @@ -164,6 +255,24 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) } #endif +/* spi_num can be from 0 - SPI_MAX_NUM */ +int enable_spi_clk(unsigned char enable, unsigned spi_num) +{ + u32 reg; + u32 mask; + + if (spi_num > SPI_MAX_NUM) + return -EINVAL; + + mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1); + reg = __raw_readl(&imx_ccm->CCGR1); + if (enable) + reg |= mask; + else + reg &= ~mask; + __raw_writel(reg, &imx_ccm->CCGR1); + return 0; +} static u32 decode_pll(enum pll_clocks pll, u32 infreq) { u32 div; @@ -177,18 +286,18 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) div &= BM_ANADIG_PLL_ARM_DIV_SELECT; return infreq * div / 2; - case PLL_BUS: + case PLL_528: div = __raw_readl(&anatop->pll_528); - if (div & BM_ANADIG_PLL_SYS_BYPASS) + if (div & BM_ANADIG_PLL_528_BYPASS) return infreq; - div &= BM_ANADIG_PLL_SYS_DIV_SELECT; + div &= BM_ANADIG_PLL_528_DIV_SELECT; return infreq * (20 + div * 2); case PLL_USBOTG: div = __raw_readl(&anatop->usb1_pll_480_ctrl); - if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS) + if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS) return infreq; - div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; + div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT; return infreq * (20 + div * 2); case PLL_AUDIO: @@ -211,12 +320,12 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) return infreq; div &= BM_ANADIG_PLL_ENET_DIV_SELECT; - return (div == 3 ? 125000000 : 25000000 * div * 2); + return 25000000 * (div + (div >> 1) + 1); case PLL_USB2: div = __raw_readl(&anatop->usb2_pll_480_ctrl); - if (div & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS) + if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS) return infreq; - div &= BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT; + div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT; return infreq * (20 + div * 2); case PLL_MLB: @@ -228,6 +337,33 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) } return 0; } +static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) +{ + u32 div; + u64 freq; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + + switch (pll) { + case PLL_528: + if (pfd_num == 3) { + /* No PFD3 on PLL2 */ + return 0; + } + div = __raw_readl(&anatop->pfd_528); + freq = (u64)decode_pll(PLL_528, MXC_HCLK); + break; + case PLL_USBOTG: + div = __raw_readl(&anatop->pfd_480); + freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); + break; + default: + /* No PFD on other PLL */ + return 0; + } + + return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> + ANATOP_PFD_FRAC_SHIFT(pfd_num)); +} static u32 get_mcu_main_clk(void) { @@ -267,16 +403,17 @@ u32 get_periph_clk(void) switch (reg) { case 0: - freq = decode_pll(PLL_BUS, MXC_HCLK); + freq = decode_pll(PLL_528, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_528, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_528, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_528, 2) / 2; break; } } @@ -300,6 +437,10 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf; reg = __raw_readl(&imx_ccm->cscmr1); +#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX)) + if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) + return MXC_HCLK; /* OSC 24Mhz */ +#endif perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; return get_ipg_clk() / (perclk_podf + 1); @@ -308,9 +449,9 @@ static u32 get_ipg_per_clk(void) static u32 get_uart_clk(void) { u32 reg, uart_podf; - u32 freq = PLL3_80M; + u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); -#ifdef CONFIG_MX6SL +#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX)) if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) freq = MXC_HCLK; #endif @@ -328,7 +469,7 @@ static u32 get_cspi_clk(void) reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - return PLL3_60M / (cspi_podf + 1); + return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); } static u32 get_axi_clk(void) @@ -341,9 +482,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 2); else - root_freq = PLL3_PFD1_FREQ; + root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); } else root_freq = get_periph_clk(); @@ -352,13 +493,13 @@ static u32 get_axi_clk(void) static u32 get_emi_slow_clk(void) { - u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0; + u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0; cscmr1 = __raw_readl(&imx_ccm->cscmr1); emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; - emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; - emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; + emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; + emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET; switch (emi_clk_sel) { case 0: @@ -368,14 +509,14 @@ static u32 get_emi_slow_clk(void) root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); break; case 2: - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 2); break; case 3: - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 0); break; } - return root_freq / (emi_slow_pof + 1); + return root_freq / (emi_slow_podf + 1); } static u32 get_nfc_clk(void) @@ -389,16 +530,16 @@ static u32 get_nfc_clk(void) switch (nfc_clk_sel) { case 0: - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 0); break; case 1: - root_freq = decode_pll(PLL_BUS, MXC_HCLK); + root_freq = decode_pll(PLL_528, MXC_HCLK); break; case 2: root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); break; case 3: - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 2); break; } @@ -429,23 +570,23 @@ static int set_nfc_clk(u32 ref, u32 freq_khz) switch (nfc_clk_sel) { case 0: - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 0); break; case 1: - root_freq = decode_pll(PLL_BUS, MXC_HCLK); + root_freq = decode_pll(PLL_528, MXC_HCLK); break; case 2: root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); break; case 3: - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 2); break; } if (root_freq < freq) continue; - podf = min(DIV_ROUND_UP(root_freq, freq), 1 << 6); - pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8); + podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6); + pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U); act_freq = root_freq / pred / podf; err = (freq - act_freq) * 100 / freq; debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n", @@ -476,7 +617,7 @@ static int set_nfc_clk(u32 ref, u32 freq_khz) return 0; } -#ifdef CONFIG_MX6SL +#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX)) static u32 get_mmdc_ch0_clk(void) { u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); @@ -489,16 +630,17 @@ static u32 get_mmdc_ch0_clk(void) switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) { case 0: - freq = decode_pll(PLL_BUS, MXC_HCLK); + freq = decode_pll(PLL_528, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_528, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_528, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_528, 2) / 2; } return freq / (podf + 1); @@ -515,6 +657,114 @@ static u32 get_mmdc_ch0_clk(void) } #endif +#ifdef CONFIG_SOC_MX6SX +/* qspi_num can be from 0 - 1 */ +void enable_qspi_clk(int qspi_num) +{ + u32 reg = 0; + /* Enable QuadSPI clock */ + switch (qspi_num) { + case 0: + /* disable the clock gate */ + clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); + + /* set 50M : (50 = 396 / 2 / 4) */ + reg = readl(&imx_ccm->cscmr1); + reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | + MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); + reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | + (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); + writel(reg, &imx_ccm->cscmr1); + + /* enable the clock gate */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); + break; + case 1: + /* + * disable the clock gate + * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, + * disable both of them. + */ + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + + /* set 50M : (50 = 396 / 2 / 4) */ + reg = readl(&imx_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); + reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); + writel(reg, &imx_ccm->cs2cdr); + + /*enable the clock gate*/ + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + break; + default: + break; + } +} +#endif + +#ifdef CONFIG_FEC_MXC +int enable_fec_anatop_clock(enum enet_freq freq) +{ + u32 reg = 0; + s32 timeout = 100000; + + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + if (freq < ENET_25MHZ || freq > ENET_125MHZ) + return -EINVAL; + + reg = readl(&anatop->pll_enet); + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; + reg |= freq; + + if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || + (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { + reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; + writel(reg, &anatop->pll_enet); + while (timeout--) { + if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) + break; + } + if (timeout < 0) + return -ETIMEDOUT; + } + + /* Enable FEC clock */ + reg |= BM_ANADIG_PLL_ENET_ENABLE; + reg &= ~BM_ANADIG_PLL_ENET_BYPASS; + writel(reg, &anatop->pll_enet); + +#ifdef CONFIG_SOC_MX6SX + /* + * Set enet ahb clock to 200MHz + * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB + */ + reg = readl(&imx_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK + | MXC_CCM_CHSCCDR_ENET_PODF_MASK + | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK); + /* PLL2 PFD2 */ + reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET); + /* Div = 2*/ + reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET); + reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET); + writel(reg, &imx_ccm->chsccdr); + + /* Enable enet system clock */ + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_ENET_MASK; + writel(reg, &imx_ccm->CCGR3); +#endif + return 0; +} +#endif + static u32 get_usdhc_clk(u32 port) { u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; @@ -551,9 +801,9 @@ static u32 get_usdhc_clk(u32 port) } if (clk_sel) - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 0); else - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_528, 2); return root_freq / (usdhc_podf + 1); } @@ -565,19 +815,14 @@ u32 imx_get_uartclk(void) u32 imx_get_fecclk(void) { - return decode_pll(PLL_ENET, MXC_HCLK); + return mxc_get_clock(MXC_IPG_CLK); } -int enable_sata_clock(void) +static int enable_enet_pll(uint32_t en) { u32 reg; s32 timeout = 100000; - /* Enable sata clock */ - reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ - reg |= MXC_CCM_CCGR5_SATA_MASK; - writel(reg, &imx_ccm->CCGR5); - /* Enable PLLs */ reg = readl(&anatop->pll_enet); reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; @@ -591,10 +836,150 @@ int enable_sata_clock(void) return -EIO; reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet); - reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; + reg |= en; writel(reg, &anatop->pll_enet); + return 0; +} + +#ifndef CONFIG_SOC_MX6SX +static void ungate_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; - return 0 ; + /* Enable SATA clock. */ + setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} +#endif + +static void ungate_pcie_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable PCIe clock. */ + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); +} + +#ifndef CONFIG_SOC_MX6SX +int enable_sata_clock(void) +{ + ungate_sata_clock(); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); +} + +void disable_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} +#endif + +int enable_pcie_clock(void) +{ + struct anatop_regs *anatop_regs = + (struct anatop_regs *)ANATOP_BASE_ADDR; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 lvds1_clk_sel; + + /* + * Here be dragons! + * + * The register ANATOP_MISC1 is not documented in the Freescale + * MX6RM. The register that is mapped in the ANATOP space and + * marked as ANATOP_MISC1 is actually documented in the PMU section + * of the datasheet as PMU_MISC1. + * + * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on + * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important + * for PCI express link that is clocked from the i.MX6. + */ +#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb + + if (is_cpu_type(MXC_CPU_MX6SX)) + lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF; + else + lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF; + + clrsetbits_le32(&anatop_regs->ana_misc1, + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel); + + /* PCIe reference clock sourced from AXI. */ + clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); + + /* Party time! Ungate the clock to the PCIe. */ +#ifndef CONFIG_SOC_MX6SX + ungate_sata_clock(); +#endif + ungate_pcie_clock(); + + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | + BM_ANADIG_PLL_ENET_ENABLE_PCIE); +} + +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable) +{ + u32 reg; + + /* CG4 ~ CG6, CAAM clocks */ + reg = __raw_readl(&imx_ccm->CCGR0); + if (enable) + reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); + else + reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); + __raw_writel(reg, &imx_ccm->CCGR0); + + /* EMI slow clk */ + reg = __raw_readl(&imx_ccm->CCGR6); + if (enable) + reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; + else + reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; + __raw_writel(reg, &imx_ccm->CCGR6); +} +#endif + +static void enable_pll3(void) +{ + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + /* make sure pll3 is enabled */ + if ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) { + /* enable pll's power */ + writel(BM_ANADIG_USB_PLL_480_CTRL_POWER, + &anatop->usb1_pll_480_ctrl_set); + writel(0x80, &anatop->ana_misc2_clr); + /* wait for pll lock */ + while ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) + ; + /* disable bypass */ + writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS, + &anatop->usb1_pll_480_ctrl_clr); + /* enable pll output */ + writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE, + &anatop->usb1_pll_480_ctrl_set); + } +} + +void enable_thermal_clk(void) +{ + enable_pll3(); } void ipu_clk_enable(void) @@ -725,9 +1110,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_ahb_clk(); case MXC_NFC_CLK: return get_nfc_clk(); + default: + printf("Unsupported MXC CLK: %d\n", clk); } - return -1; + return 0; } static inline int gcd(int m, int n) @@ -891,7 +1278,7 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) static void do_mx6_showclocks(void) { print_pll(PLL_ARM); - print_pll(PLL_BUS); + print_pll(PLL_528); print_pll(PLL_USBOTG); print_pll(PLL_AUDIO); print_pll(PLL_VIDEO); @@ -959,7 +1346,7 @@ int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) case MXC_ARM_CLK: if (argc > 3) return CMD_RET_USAGE; - ref = CONFIG_SYS_MX6_HCLK; + ref = MXC_HCLK; break; case MXC_NFC_CLK: @@ -992,6 +1379,16 @@ int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) return CMD_RET_FAILURE; } +#ifndef CONFIG_SOC_MX6SX +void enable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; + writel(reg, &mxc_ccm->CCGR3); +} +#endif /***************************************************/ U_BOOT_CMD( diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c new file mode 100644 index 0000000000..8661afac69 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -0,0 +1,491 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D) +/* Configure MX6DQ mmdc iomux */ +void mx6dq_dram_iocfg(unsigned width, + const struct mx6dq_iomux_ddr_regs *ddr, + const struct mx6dq_iomux_grp_regs *grp) +{ + volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux; + volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux; + + mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE; + mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE; + + /* DDR IO Type */ + mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; + mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; + + /* Clock */ + mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; + mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; + + /* Address */ + mx6_ddr_iomux->dram_cas = ddr->dram_cas; + mx6_ddr_iomux->dram_ras = ddr->dram_ras; + mx6_grp_iomux->grp_addds = grp->grp_addds; + + /* Control */ + mx6_ddr_iomux->dram_reset = ddr->dram_reset; + mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; + mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; + mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; + mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; + mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; + mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; + + /* Data Strobes */ + mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; + mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; + mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; + if (width >= 32) { + mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; + mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; + mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; + mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; + mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; + } + + /* Data */ + mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; + mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; + mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; + if (width >= 32) { + mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; + mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; + } + if (width >= 64) { + mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; + mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; + mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; + mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; + } + mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; + mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; + if (width >= 32) { + mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; + mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; + mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; + mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; + mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; + } +} +#endif + +#if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) +/* Configure MX6SDL mmdc iomux */ +void mx6sdl_dram_iocfg(unsigned width, + const struct mx6sdl_iomux_ddr_regs *ddr, + const struct mx6sdl_iomux_grp_regs *grp) +{ + volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux; + volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux; + + mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE; + mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE; + + /* DDR IO Type */ + mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; + mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; + + /* Clock */ + mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; + mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; + + /* Address */ + mx6_ddr_iomux->dram_cas = ddr->dram_cas; + mx6_ddr_iomux->dram_ras = ddr->dram_ras; + mx6_grp_iomux->grp_addds = grp->grp_addds; + + /* Control */ + mx6_ddr_iomux->dram_reset = ddr->dram_reset; + mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; + mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; + mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; + mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; + mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; + mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; + + /* Data Strobes */ + mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; + mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; + mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; + if (width >= 32) { + mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; + mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; + mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; + mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; + mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; + } + + /* Data */ + mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; + mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; + mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; + if (width >= 32) { + mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; + mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; + } + if (width >= 64) { + mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; + mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; + mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; + mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; + } + mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; + mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; + if (width >= 32) { + mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; + mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; + mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; + mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; + mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; + } +} +#endif + +/* + * Configure mx6 mmdc registers based on: + * - board-specific memory configuration + * - board-specific calibration data + * - ddr3 chip details + * + * The various calculations here are derived from the Freescale + * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC + * configuration registers based on memory system and memory chip parameters. + * + * The defaults here are those which were specified in the spreadsheet. + * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM + * section titled MMDC initialization + */ +#define MR(val, ba, cmd, cs1) \ + ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) +void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, + const struct mx6_mmdc_calibration *calib, + const struct mx6_ddr3_cfg *ddr3_cfg) +{ + volatile struct mmdc_p_regs *mmdc0; + volatile struct mmdc_p_regs *mmdc1; + u32 val; + u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; + u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; + u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ + u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; + u16 cs0_end; + u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ + u8 coladdr; + int clkper; /* clock period in picoseconds */ + int clock; /* clock freq in mHz */ + int cs; + + mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; + mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; + + /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */ + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + clock = 528; + tcwl = 4; + } + /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */ + else { + clock = 400; + tcwl = 3; + } + clkper = (1000 * 1000) / clock; /* pico seconds */ + todtlon = tcwl; + taxpd = tcwl; + tanpd = tcwl; + + switch (ddr3_cfg->density) { + case 1: /* 1Gb per chip */ + trfc = DIV_ROUND_UP(110000, clkper) - 1; + txs = DIV_ROUND_UP(120000, clkper) - 1; + break; + case 2: /* 2Gb per chip */ + trfc = DIV_ROUND_UP(160000, clkper) - 1; + txs = DIV_ROUND_UP(170000, clkper) - 1; + break; + case 4: /* 4Gb per chip */ + trfc = DIV_ROUND_UP(260000, clkper) - 1; + txs = DIV_ROUND_UP(270000, clkper) - 1; + break; + case 8: /* 8Gb per chip */ + trfc = DIV_ROUND_UP(350000, clkper) - 1; + txs = DIV_ROUND_UP(360000, clkper) - 1; + break; + default: + /* invalid density */ + puts("invalid chip density\n"); + hang(); + break; + } + txpr = txs; + + switch (ddr3_cfg->mem_speed) { + case 800: + txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; + tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; + if (ddr3_cfg->pagesz == 1) { + tfaw = DIV_ROUND_UP(40000, clkper) - 1; + trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(50000, clkper) - 1; + trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; + } + break; + case 1066: + txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; + tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1; + if (ddr3_cfg->pagesz == 1) { + tfaw = DIV_ROUND_UP(37500, clkper) - 1; + trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(50000, clkper) - 1; + trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; + } + break; + case 1333: + txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1; + tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1; + if (ddr3_cfg->pagesz == 1) { + tfaw = DIV_ROUND_UP(30000, clkper) - 1; + trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(45000, clkper) - 1; + trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; + } + break; + case 1600: + txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1; + tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1; + if (ddr3_cfg->pagesz == 1) { + tfaw = DIV_ROUND_UP(30000, clkper) - 1; + trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(40000, clkper) - 1; + trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; + } + break; + default: + puts("invalid memory speed\n"); + hang(); + break; + } + txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1; + tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper); + taonpd = DIV_ROUND_UP(2000, clkper) - 1; + tcksrx = tcksre; + taofpd = taonpd; + twr = DIV_ROUND_UP(15000, clkper) - 1; + tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1; + trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1; + tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1; + tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3; + trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1; + twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1; + trcd = trp; + trtp = twtr; + cs0_end = 4 * sysinfo->cs_density - 1; + + debug("density:%d Gb (%d Gb per chip)\n", + sysinfo->cs_density, ddr3_cfg->density); + debug("clock: %dMHz (%d ps)\n", clock, clkper); + debug("memspd:%d\n", ddr3_cfg->mem_speed); + debug("tcke=%d\n", tcke); + debug("tcksrx=%d\n", tcksrx); + debug("tcksre=%d\n", tcksre); + debug("taofpd=%d\n", taofpd); + debug("taonpd=%d\n", taonpd); + debug("todtlon=%d\n", todtlon); + debug("tanpd=%d\n", tanpd); + debug("taxpd=%d\n", taxpd); + debug("trfc=%d\n", trfc); + debug("txs=%d\n", txs); + debug("txp=%d\n", txp); + debug("txpdll=%d\n", txpdll); + debug("tfaw=%d\n", tfaw); + debug("tcl=%d\n", tcl); + debug("trcd=%d\n", trcd); + debug("trp=%d\n", trp); + debug("trc=%d\n", trc); + debug("tras=%d\n", tras); + debug("twr=%d\n", twr); + debug("tmrd=%d\n", tmrd); + debug("tcwl=%d\n", tcwl); + debug("tdllk=%d\n", tdllk); + debug("trtp=%d\n", trtp); + debug("twtr=%d\n", twtr); + debug("trrd=%d\n", trrd); + debug("txpr=%d\n", txpr); + debug("cs0_end=%d\n", cs0_end); + debug("ncs=%d\n", sysinfo->ncs); + debug("Rtt_wr=%d\n", sysinfo->rtt_wr); + debug("Rtt_nom=%d\n", sysinfo->rtt_nom); + debug("SRT=%d\n", ddr3_cfg->SRT); + debug("tcl=%d\n", tcl); + debug("twr=%d\n", twr); + + /* + * board-specific configuration: + * These values are determined empirically and vary per board layout + * see: + * appnote, ddr3 spreadsheet + */ + mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; + mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1; + mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0; + mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; + mmdc0->mprddlctl = calib->p0_mprddlctl; + mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; + if (sysinfo->dsize > 1) { + mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0; + mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1; + mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0; + mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1; + mmdc1->mprddlctl = calib->p1_mprddlctl; + mmdc1->mpwrdlctl = calib->p1_mpwrdlctl; + } + + /* Read data DQ Byte0-3 delay */ + mmdc0->mprddqby0dl = 0x33333333; + mmdc0->mprddqby1dl = 0x33333333; + if (sysinfo->dsize > 0) { + mmdc0->mprddqby2dl = 0x33333333; + mmdc0->mprddqby3dl = 0x33333333; + } + + if (sysinfo->dsize > 1) { + mmdc1->mprddqby0dl = 0x33333333; + mmdc1->mprddqby1dl = 0x33333333; + mmdc1->mprddqby2dl = 0x33333333; + mmdc1->mprddqby3dl = 0x33333333; + } + + /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ + val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227; + mmdc0->mpodtctrl = val; + if (sysinfo->dsize > 1) + mmdc1->mpodtctrl = val; + + /* complete calibration */ + val = (1 << 11); /* Force measurement on delay-lines */ + mmdc0->mpmur0 = val; + if (sysinfo->dsize > 1) + mmdc1->mpmur0 = val; + + /* Step 1: configuration request */ + mmdc0->mdscr = (u32)(1 << 15); /* config request */ + + /* Step 2: Timing configuration */ + mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) | + (txpdll << 9) | (tfaw << 4) | tcl; + mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) | + (tras << 16) | (1 << 15) /* trpa */ | + (twr << 9) | (tmrd << 5) | tcwl; + mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; + mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | + (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4); + mmdc0->mdasp = cs0_end; /* CS addressing */ + + /* Step 3: Configure DDR type */ + mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) | + (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) | + (sysinfo->ralat << 6); + + /* Step 4: Configure delay while leaving reset */ + mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) | + (sysinfo->rst_to_cke << 0); + + /* Step 5: Configure DDR physical parameters (density and burst len) */ + coladdr = ddr3_cfg->coladdr; + if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ + coladdr += 4; + else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ + coladdr += 1; + mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */ + (coladdr - 9) << 20 | /* COL */ + (1 << 19) | /* Burst Length = 8 for DDR3 */ + (sysinfo->dsize << 16); /* DDR data bus size */ + + /* Step 6: Perform ZQ calibration */ + val = 0xa1390001; /* one-time HW ZQ calib */ + mmdc0->mpzqhwctrl = val; + if (sysinfo->dsize > 1) + mmdc1->mpzqhwctrl = val; + + /* Step 7: Enable MMDC with desired chip select */ + mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ + ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ + + /* Step 8: Write Mode Registers to Init DDR3 devices */ + for (cs = 0; cs < sysinfo->ncs; cs++) { + /* MR2 */ + val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 | + ((tcwl - 3) & 3) << 3; + mmdc0->mdscr = MR(val, 2, 3, cs); + /* MR3 */ + mmdc0->mdscr = MR(0, 3, 3, cs); + /* MR1 */ + val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 | + ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6; + mmdc0->mdscr = MR(val, 1, 3, cs); + /* MR0 */ + val = ((tcl - 1) << 4) | /* CAS */ + (1 << 8) | /* DLL Reset */ + ((twr - 3) << 9); /* Write Recovery */ + mmdc0->mdscr = MR(val, 0, 3, cs); + /* ZQ calibration */ + val = (1 << 10); + mmdc0->mdscr = MR(val, 0, 4, cs); + } + + /* Step 10: Power down control and self-refresh */ + mmdc0->mdpdc = (tcke & 0x7) << 16 | + 5 << 12 | /* PWDT_1: 256 cycles */ + 5 << 8 | /* PWDT_0: 256 cycles */ + 1 << 7 | /* SLOW_PD */ + 1 << 6 | /* BOTH_CS_PD */ + (tcksrx & 0x7) << 3 | + (tcksre & 0x7); + mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ + + /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ + val = 0xa1390003; + mmdc0->mpzqhwctrl = val; + if (sysinfo->dsize > 1) + mmdc1->mpzqhwctrl = val; + + /* Step 12: Configure and activate periodic refresh */ + mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ + (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ + + /* Step 13: Deassert config request - init complete */ + mmdc0->mdscr = 0x00000000; + + /* wait for auto-ZQ calibration to complete */ + mdelay(1); +} diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c new file mode 100644 index 0000000000..757096d356 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +HAB_FUNC(entry, hab_status_t) +HAB_FUNC(exit, hab_status_t) +HAB_FUNC5(authenticate_image, void *, uint8_t, size_t, void **, size_t *, hab_loader_callback_f_t) +//HAB_FUNC1(run_dcd, hab_status_t, const uint8_t *) +HAB_FUNC2(run_csf, hab_status_t, const uint8_t *, uint8_t) +HAB_FUNC2(report_status, hab_status_t, hab_config_t *, hab_state_t *) +HAB_FUNC4(report_event, hab_status_t, hab_status_t, uint32_t, uint8_t *, size_t *) +HAB_FUNC3(check_target, hab_status_t, uint8_t, const void *, size_t) +HAB_FUNC3(assert, hab_status_t, uint8_t, const void *, size_t) + +struct mx6_ivt { + u32 header; + u32 entry; + u32 rsrvd1; + void *dcd; + struct mx6_boot_data *boot_data; + void *self; + void *csf; + u32 rsrvd2; +}; + +struct mx6_boot_data { + void *start; + u32 length; + u32 plugin; +}; + +#define IVT_SIZE 0x20 +#define ALIGN_SIZE 0x400 +#define CSF_PAD_SIZE 0x2000 +#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 +#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 +#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 + +/* + * +------------+ 0x0 (DDR_UIMAGE_START) - + * | Header | | + * +------------+ 0x40 | + * | | | + * | | | + * | | | + * | | | + * | Image Data | | + * . | | + * . | > Stuff to be authenticated ----+ + * . | | | + * | | | | + * | | | | + * +------------+ | | + * | | | | + * | Fill Data | | | + * | | | | + * +------------+ Align to ALIGN_SIZE | | + * | IVT | | | + * +------------+ + IVT_SIZE - | + * | | | + * | CSF DATA | <---------------------------------------------------------+ + * | | + * +------------+ + * | | + * | Fill Data | + * | | + * +------------+ + CSF_PAD_SIZE + */ + +static bool is_hab_enabled(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + uint32_t reg = readl(&fuse->cfg5); + static int first = 1; + + if (first) { + debug("rvt_base=%p\n", hab_rvt_base()); + debug("hab_rvt_entry=%p\n", hab_rvt_entry_p); + debug("hab_rvt_exit=%p\n", hab_rvt_exit_p); + debug("hab_rvt_check_target=%p\n", hab_rvt_check_target_p); + debug("hab_rvt_authenticate_image=%p\n", hab_rvt_authenticate_image_p); + debug("hab_rvt_report_event=%p\n", hab_rvt_report_event_p); + debug("hab_rvt_report_status=%p\n", hab_rvt_report_status_p); + debug("hab_rvt_assert=%p\n", hab_rvt_assert_p); + first = 0; + } + return (reg & 0x2) == 0x2; +} + +static void display_event(uint8_t *event_data, size_t bytes) +{ + uint32_t i; + + if (!(event_data && bytes > 0)) + return; + + for (i = 0; i < bytes; i++) { + if (i == 0) + printf("\t0x%02x", event_data[i]); + else if ((i % 8) == 0) + printf("\n\t0x%02x", event_data[i]); + else + printf(" 0x%02x", event_data[i]); + } +} + +int get_hab_status(void) +{ + static uint32_t last_hab_event __attribute__((section(".data"))); + uint32_t index = last_hab_event; /* Loop index */ + uint8_t event_data[128]; /* Event data buffer */ + size_t bytes = sizeof(event_data); /* Event size in bytes */ + enum hab_config config; + enum hab_state state; + int ret; + + if (is_hab_enabled()) + puts("Secure boot enabled\n"); + else + puts("Secure boot disabled\n"); + + /* Check HAB status */ + config = state = 0; /* ROM code assumes short enums! */ + ret = hab_rvt_report_status(&config, &state); + printf("HAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + if (ret != HAB_SUCCESS) { + /* Display HAB Error events */ + while (hab_rvt_report_event(HAB_STS_ANY, index, event_data, + &bytes) == HAB_SUCCESS) { + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + display_event(event_data, bytes); + puts("\n"); + bytes = sizeof(event_data); + index++; + } + ret = index - last_hab_event; + last_hab_event = index; + } else { + /* Display message if no HAB events are found */ + puts("No HAB Events Found!\n"); + ret = 0; + } + return ret; +} + +static inline hab_status_t hab_init(void) +{ + hab_status_t ret; + + if (!is_hab_enabled()) { + puts("hab fuse not enabled\n"); + return HAB_FAILURE; + } + + hab_caam_clock_enable(1); + + ret = hab_rvt_entry(); + debug("hab_rvt_entry() returned %02x\n", ret); + if (ret != HAB_SUCCESS) { + printf("hab entry function failed: %02x\n", ret); + hab_caam_clock_enable(0); + } + + return ret; +} + +static inline hab_status_t hab_exit(void) +{ + hab_status_t ret; + + ret = hab_rvt_exit(); + if (ret != HAB_SUCCESS) + printf("hab exit function failed: %02x\n", ret); + + hab_caam_clock_enable(0); + + return ret; +} + +static hab_status_t hab_check_target(hab_target_t type, uint32_t addr, size_t len) +{ + hab_status_t ret; + + ret = hab_init(); + if (ret != HAB_SUCCESS) + return ret; + + ret = hab_rvt_check_target(type, (void *)addr, len); + if (ret != HAB_SUCCESS) { + printf("check_target(0x%08x, 0x%08x) failed: %d\n", + addr, len, ret); + return ret; + } + ret = hab_exit(); + + if (ret == HAB_SUCCESS && get_hab_status() > 0) { + return HAB_FAILURE; + } + return ret; +} + +static hab_status_t hab_assert(uint32_t type, uint32_t addr, size_t len) +{ + hab_status_t ret; + + ret = hab_init(); + if (ret != HAB_SUCCESS) + return ret; + + ret = hab_rvt_assert(type, (void *)addr, len); + if (ret != HAB_SUCCESS) { + printf("assert(0x%08x, 0x%08x) failed: %d\n", + addr, len, ret); + return ret; + } + ret = hab_exit(); + + if (ret == HAB_SUCCESS && get_hab_status() > 0) { + return HAB_FAILURE; + } + return ret; +} + +static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 1) + return CMD_RET_USAGE; + + get_hab_status(); + + return CMD_RET_SUCCESS; +} + +static int do_hab_check_target(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + hab_target_t type = HAB_TGT_ANY; + uint32_t addr; + size_t len; + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + len = simple_strtoul(argv[2], NULL, 16); + if (argc > 3) { + switch (argv[3][0]) { + case 'p': + case 'P': + type = HAB_TGT_PERIPHERAL; + break; + case 'm': + case 'M': + type = HAB_TGT_MEMORY; + break; + case 'a': + case 'A': + break; + default: + printf("Invalid type '%s'\n", argv[3]); + return CMD_RET_USAGE; + } + } + if (hab_check_target(type, addr, len) != HAB_SUCCESS) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_hab_assert(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + uint32_t type = 0; + uint32_t addr; + size_t len; + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + len = simple_strtoul(argv[2], NULL, 16); + if (argc > 3) { + type = simple_strtoul(argv[3], NULL, 16); + } + + if (hab_assert(type, addr, len) != HAB_SUCCESS) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, + "display HAB status", + "" + ); + +U_BOOT_CMD( + hab_check_target, 4, 0, do_hab_check_target, + "verify an address range via HAB", + "addr len [type]\n" + "\t\taddr -\taddress to verify\n" + "\t\tlen -\tlength of addr range to verify\n" + ); + +U_BOOT_CMD( + hab_assert, 4, 0, do_hab_assert, + "Test an assertion against the HAB audit log", + "addr len [type]\n" + "\t\taddr -\taddress to verify\n" + "\t\tlen -\tlength of addr range to verify\n" + ); diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c new file mode 100644 index 0000000000..9f034d6e13 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/mp.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2014 + * Gabriel Huau + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define MAX_CPUS 4 +static struct src *src = (struct src *)SRC_BASE_ADDR; + +static uint32_t cpu_reset_mask[MAX_CPUS] = { + 0, /* We don't really want to modify the cpu0 */ + SRC_SCR_CORE_1_RESET_MASK, + SRC_SCR_CORE_2_RESET_MASK, + SRC_SCR_CORE_3_RESET_MASK +}; + +static uint32_t cpu_ctrl_mask[MAX_CPUS] = { + 0, /* We don't really want to modify the cpu0 */ + SRC_SCR_CORE_1_ENABLE_MASK, + SRC_SCR_CORE_2_ENABLE_MASK, + SRC_SCR_CORE_3_ENABLE_MASK +}; + +int cpu_reset(int nr) +{ + /* Software reset of the CPU N */ + src->scr |= cpu_reset_mask[nr]; + return 0; +} + +int cpu_status(int nr) +{ + printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr])); + return 0; +} + +int cpu_release(int nr, int argc, char *const argv[]) +{ + uint32_t boot_addr; + + boot_addr = simple_strtoul(argv[0], NULL, 16); + + switch (nr) { + case 1: + src->gpr3 = boot_addr; + break; + case 2: + src->gpr5 = boot_addr; + break; + case 3: + src->gpr7 = boot_addr; + break; + default: + return 1; + } + + /* CPU N is ready to start */ + src->scr |= cpu_ctrl_mask[nr]; + + return 0; +} + +int is_core_valid(unsigned int core) +{ + uint32_t nr_cores = get_nr_cpus(); + + if (core > nr_cores) + return 0; + + return 1; +} + +int cpu_disable(int nr) +{ + /* Disable the CPU N */ + src->scr &= ~cpu_ctrl_mask[nr]; + return 0; +} diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 6ca4a1ee7d..63d50c1abd 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,23 +8,29 @@ */ #include +#include +#include #include +#include +#include +#include +#include +#include #include #include #include #include #include #include +#include #include #include #include -#include -#ifdef CONFIG_VIDEO_IPUV3 -#include -#endif DECLARE_GLOBAL_DATA_PTR; +#define __data __attribute__((section(".data"))) + #ifdef CONFIG_MX6_TEMPERATURE_MIN #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN #else @@ -43,7 +49,11 @@ DECLARE_GLOBAL_DATA_PTR; #define TEMP_AVG_COUNT 5 #define TEMP_WARN_THRESHOLD 5 -#define __data __attribute__((section(".data"))) +enum ldo_reg { + LDO_ARM, + LDO_SOC, + LDO_PU, +}; struct scu_regs { u32 ctrl; @@ -53,27 +63,24 @@ struct scu_regs { u32 fpga_rev; }; -#ifdef CONFIG_HW_WATCHDOG -#define wdog_base ((void *)WDOG1_BASE_ADDR) -#define WDOG_WCR 0x00 -#define WCR_WDE (1 << 2) -#define WDOG_WSR 0x02 +#if defined(CONFIG_IMX6_THERMAL) +static const struct imx_thermal_plat imx6_thermal_plat = { + .regs = (void *)ANATOP_BASE_ADDR, + .fuse_bank = 1, + .fuse_word = 6, +}; -void hw_watchdog_reset(void) -{ - if (readw(wdog_base + WDOG_WCR) & WCR_WDE) { - static u16 __data toggle = 0xaaaa; - static int __data first = 1; +U_BOOT_DEVICE(imx6_thermal) = { + .name = "imx_thermal", + .platdata = &imx6_thermal_plat, +}; +#endif - if (first) { - printf("Watchdog active\n"); - first = 0; - } - writew(toggle, wdog_base + WDOG_WSR); - toggle ^= 0xffff; - } +u32 get_nr_cpus(void) +{ + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + return readl(&scu->config) & 3; } -#endif u32 get_cpu_rev(void) { @@ -83,14 +90,19 @@ u32 get_cpu_rev(void) if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); if (type == MXC_CPU_MX6DL) { - struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; - if (!cfg) type = MXC_CPU_MX6SOLO; } + + if (type == MXC_CPU_MX6Q) { + if (cfg == 1) + type = MXC_CPU_MX6D; + } + } reg &= 0xff; /* mx6 silicon revision */ return (type << 12) | (reg + 0x10); @@ -104,6 +116,9 @@ u32 __weak get_board_rev(void) if (type == MXC_CPU_MX6SOLO) cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); + if (type == MXC_CPU_MX6D) + cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); + return cpurev; } #endif @@ -111,9 +126,15 @@ u32 __weak get_board_rev(void) void init_aips(void) { struct aipstz_regs *aips1, *aips2; +#ifdef CONFIG_SOC_MX6SX + struct aipstz_regs *aips3; +#endif aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; +#ifdef CONFIG_SOC_MX6SX + aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; +#endif /* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -139,20 +160,54 @@ void init_aips(void) writel(0x00000000, &aips2->opacr2); writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); + +#ifdef CONFIG_SOC_MX6SX + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips3->mprot0); + writel(0x77777777, &aips3->mprot1); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips3->opacr0); + writel(0x00000000, &aips3->opacr1); + writel(0x00000000, &aips3->opacr2); + writel(0x00000000, &aips3->opacr3); + writel(0x00000000, &aips3->opacr4); +#endif +} + +static void clear_ldo_ramp(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg; + + /* ROM may modify LDO ramp up time according to fuse setting, so in + * order to be in the safe side we neeed to reset these settings to + * match the reset value: 0'b00 + */ + reg = readl(&anatop->ana_misc2); + reg &= ~(0x3f << 24); + writel(reg, &anatop->ana_misc2); } /* - * Set the VDDSOC + * Set the PMU_REG_CORE register * - * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set - * them to the specified millivolt level. + * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. * Possible values are from 0.725V to 1.450V in steps of * 0.025V (25mV). */ -static void set_vddsoc(u32 mv) +static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - u32 val, reg = readl(&anatop->reg_core); + u32 val, step, old, reg = readl(&anatop->reg_core); + u8 shift; if (mv < 725) val = 0x00; /* Power gated off */ @@ -161,12 +216,37 @@ static void set_vddsoc(u32 mv) else val = (mv - 700) / 25; + clear_ldo_ramp(); + + switch (ldo) { + case LDO_SOC: + shift = 18; + break; + case LDO_PU: + shift = 9; + break; + case LDO_ARM: + shift = 0; + break; + default: + return -EINVAL; + } + + old = (reg & (0x1F << shift)) >> shift; + step = abs(val - old); + if (step == 0) + return 0; + + reg = (reg & ~(0x1F << shift)) | (val << shift); + writel(reg, &anatop->reg_core); + /* - * Mask out the REG_CORE[22:18] bits (REG2_TRIG) - * and set them to the calculated value (0.7V + val * 0.25V) + * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per + * step */ - reg = (reg & ~(0x1F << 18)) | (val << 18); - writel(reg, &anatop->reg_core); + udelay(3 * step); + + return 0; } static u32 __data thermal_calib; @@ -350,12 +430,57 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } -#ifdef CONFIG_ARCH_CPU_INIT +static void set_ahb_rate(u32 val) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg, div; + + div = get_periph_clk() / val - 1; + reg = readl(&mxc_ccm->cbcdr); + + writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | + (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); +} + +static void clear_mmdc_ch_mask(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Clear MMDC channel mask */ + writel(0, &mxc_ccm->ccdr); +} + +#ifdef CONFIG_SOC_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif + int arch_cpu_init(void) { init_aips(); - set_vddsoc(1200); /* Set VDDSOC to 1.2V */ + /* Need to clear MMDC_CHx_MASK to make warm reset work. */ + clear_mmdc_ch_mask(); + + /* + * When low freq boot is enabled, ROM will not set AHB + * freq, so we need to ensure AHB freq is 132MHz in such + * scenario. + */ + if (mxc_get_clock(MXC_ARM_CLK) == 396000000) + set_ahb_rate(132000000); + + /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_SOC_MX6SL) + set_preclk_from_osc(); +#endif imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ @@ -367,15 +492,39 @@ int arch_cpu_init(void) timer_init(); mxs_dma_init(); #endif + + return 0; +} + +int board_postclk_init(void) +{ + set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ + return 0; } -#endif #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + enum dcache_option option = DCACHE_WRITETHROUGH; +#else + enum dcache_option option = DCACHE_WRITEBACK; +#endif + + /* Avoid random hang when download by usb */ + invalidate_dcache_all(); + /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); + + /* Enable caching on OCRAM and ROM */ + mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, + ROMCP_ARB_END_ADDR, + option); + mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, + IRAM_SIZE, + option); } #endif @@ -414,18 +563,18 @@ void boot_mode_apply(unsigned cfg_val) /* * cfg_val will be used for * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] - * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] - * to SBMR1, which will determine the boot device. + * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] + * instead of SBMR1 to determine the boot device. */ const struct boot_mode soc_boot_modes[] = { {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, /* reserved value should start rom usb */ {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, - {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, - {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, - {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, - {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, + {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, + {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, + {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, + {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, /* 4 bit bus width */ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, @@ -436,4 +585,144 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 mask480; + u32 mask528; + u32 reg, periph1, periph2; + + if (is_cpu_type(MXC_CPU_MX6SX)) + return; + + /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs + * to make sure PFD is working right, otherwise, PFDs may + * not output clock after reset, MX6DL and MX6SL have added 396M pfd + * workaround in ROM code, as bus clock need it + */ + + mask480 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(2) | + ANATOP_PFD_CLKGATE_MASK(3); + mask528 = ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(3); + + reg = readl(&ccm->cbcmr); + periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); + periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); + + /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ + if ((periph2 != 0x2) && (periph1 != 0x2)) + mask528 |= ANATOP_PFD_CLKGATE_MASK(0); + + if ((periph2 != 0x1) && (periph1 != 0x1) && + (periph2 != 0x3) && (periph1 != 0x3)) + mask528 |= ANATOP_PFD_CLKGATE_MASK(2); + + writel(mask480, &anatop->pfd_480_set); + writel(mask528, &anatop->pfd_528_set); + writel(mask480, &anatop->pfd_480_clr); + writel(mask528, &anatop->pfd_528_clr); +} + +#ifdef CONFIG_IMX_HDMI +void imx_enable_hdmi_phy(void) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +void imx_setup_hdmi(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + int reg; + + /* Turn on HDMI PHY clock */ + reg = readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| + MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_PODF_DIVIDE_BY_3 + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + |(CHSCCDR_IPU_PRE_CLK_540M_PFD + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 +void v7_outer_cache_enable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + unsigned int val; + +#if defined CONFIG_SOC_MX6SL + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + val = readl(&iomux->gpr[11]); + if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { + /* L2 cache configured as OCRAM, reset it */ + val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; + writel(val, &iomux->gpr[11]); + } +#endif + + /* Must disable the L2 before changing the latency parameters */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x132, &pl310->pl310_tag_latency_ctrl); + writel(0x132, &pl310->pl310_data_latency_ctrl); + + val = readl(&pl310->pl310_prefetch_ctrl); + + /* Turn on the L2 I/D prefetch */ + val |= 0x30000000; + + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + +#ifndef CONFIG_SOC_MX6Q + val |= 0x40800000; +#endif + writel(val, &pl310->pl310_prefetch_ctrl); + + val = readl(&pl310->pl310_power_ctrl); + val |= L2X0_DYNAMIC_CLK_GATING_EN; + val |= L2X0_STNDBY_MODE_EN; + writel(val, &pl310->pl310_power_ctrl); + + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } +#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S new file mode 100644 index 0000000000..30d81db8b8 --- /dev/null +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -0,0 +1,205 @@ +/* + * code for switching cores into non-secure state and into HYP mode + * + * Copyright (c) 2013 Andre Przywara + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +.arch_extension sec +.arch_extension virt + + .pushsection ._secure.text, "ax" + + .align 5 +/* the vector table for secure state and HYP mode */ +_monitor_vectors: + .word 0 /* reset */ + .word 0 /* undef */ + adr pc, _secure_monitor + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + +.macro is_cpu_virt_capable tmp + mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1 + and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits + cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT) +.endm + +/* + * secure monitor handler + * U-boot calls this "software interrupt" in start.S + * This is executed on a "smc" instruction, we use a "smc #0" to switch + * to non-secure state. + * r0, r1, r2: passed to the callee + * ip: target PC + */ +_secure_monitor: +#ifdef CONFIG_ARMV7_PSCI + ldr r5, =_psci_vectors @ Switch to the next monitor + mcr p15, 0, r5, c12, c0, 1 + isb + + @ Obtain a secure stack, and configure the PSCI backend + bl psci_arch_init +#endif + + mrc p15, 0, r5, c1, c1, 0 @ read SCR + bic r5, r5, #0x4a @ clear IRQ, EA, nET bits + orr r5, r5, #0x31 @ enable NS, AW, FW bits + @ FIQ preserved for secure mode + mov r6, #SVC_MODE @ default mode is SVC + is_cpu_virt_capable r4 +#ifdef CONFIG_ARMV7_VIRT + orreq r5, r5, #0x100 @ allow HVC instruction + moveq r6, #HYP_MODE @ Enter the kernel as HYP +#endif + + mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) + isb + + bne 1f + + @ Reset CNTVOFF to 0 before leaving monitor mode + mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1 + ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits + movne r4, #0 + mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero +1: + mov lr, ip + mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F + tst lr, #1 @ Check for Thumb PC + orrne ip, ip, #T_BIT @ Set T if Thumb + orr ip, ip, r6 @ Slot target mode in + msr spsr_cxfs, ip @ Set full SPSR + movs pc, lr @ ERET to non-secure + +ENTRY(_do_nonsec_entry) + mov ip, r0 + mov r0, r1 + mov r1, r2 + mov r2, r3 + smc #0 +ENDPROC(_do_nonsec_entry) + +.macro get_cbar_addr addr +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS +#else + mrc p15, 4, \addr, c15, c0, 0 @ read CBAR + bfc \addr, #0, #15 @ clear reserved bits +#endif +.endm + +.macro get_gicd_addr addr + get_cbar_addr \addr + add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset +.endm + +.macro get_gicc_addr addr, tmp + get_cbar_addr \addr + is_cpu_virt_capable \tmp + movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 + moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 + add \addr, \addr, \tmp +.endm + +#ifndef CONFIG_ARMV7_PSCI +/* + * Secondary CPUs start here and call the code for the core specific parts + * of the non-secure and HYP mode transition. The GIC distributor specific + * code has already been executed by a C function before. + * Then they go back to wfi and wait to be woken up by the kernel again. + */ +ENTRY(_smp_pen) + cpsid i + cpsid f + + bl _nonsec_init + + adr r0, _smp_pen @ do not use this address again + b smp_waitloop @ wait for IPIs, board specific +ENDPROC(_smp_pen) +#endif + +/* + * Switch a core to non-secure state. + * + * 1. initialize the GIC per-core interface + * 2. allow coprocessor access in non-secure modes + * + * Called from smp_pen by secondary cores and directly by the BSP. + * Do not assume that the stack is available and only use registers + * r0-r3 and r12. + * + * PERIPHBASE is used to get the GIC address. This could be 40 bits long, + * though, but we check this in C before calling this function. + */ +ENTRY(_nonsec_init) + get_gicd_addr r3 + + mvn r1, #0 @ all bits to 1 + str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts + + get_gicc_addr r3, r1 + + mov r1, #3 @ Enable both groups + str r1, [r3, #GICC_CTLR] @ and clear all other bits + mov r1, #0xff + str r1, [r3, #GICC_PMR] @ set priority mask register + + mrc p15, 0, r0, c1, c1, 2 + movw r1, #0x3fff + movt r1, #0x0004 + orr r0, r0, r1 + mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec + +/* The CNTFRQ register of the generic timer needs to be + * programmed in secure state. Some primary bootloaders / firmware + * omit this, so if the frequency is provided in the configuration, + * we do this here instead. + * But first check if we have the generic timer. + */ +#ifdef CONFIG_TIMER_CLK_FREQ + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits + cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) + ldreq r1, =CONFIG_TIMER_CLK_FREQ + mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ +#endif + + adr r1, _monitor_vectors + mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors + isb + + mov r0, r3 @ return GICC address + bx lr +ENDPROC(_nonsec_init) + +#ifdef CONFIG_SMP_PEN_ADDR +/* void __weak smp_waitloop(unsigned previous_address); */ +ENTRY(smp_waitloop) + wfi + ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address + ldr r1, [r1] +#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN + rev r1, r1 +#endif + cmp r0, r1 @ make sure we dont execute this code + beq smp_waitloop @ again (due to a spurious wakeup) + mov r0, r1 + b _do_nonsec_entry +ENDPROC(smp_waitloop) +.weak smp_waitloop +#endif + + .popsection diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 98f29d466b..7695e16d36 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -5,46 +5,30 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libomap-common.o - -COBJS := reset.o -COBJS += timer.o -COBJS += utils.o +obj-y := reset.o +obj-y += timer.o +obj-y += utils.o ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) -COBJS += hwinit-common.o -COBJS += clocks-common.o -COBJS += emif-common.o -COBJS += vc.o -COBJS += abb.o +obj-y += hwinit-common.o +obj-y += clocks-common.o +obj-y += emif-common.o +obj-y += vc.o +obj-y += abb.o endif -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) -COBJS += boot-common.o -SOBJS += lowlevel_init.o +ifneq ($(CONFIG_OMAP54XX),) +obj-y += pipe3-phy.o +obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o endif -ifndef CONFIG_SPL_BUILD -ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) -COBJS += mem-common.o +ifeq ($(CONFIG_SYS_DCACHE_OFF),) +obj-y += omap-cache.o endif -endif - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +ifeq ($(CONFIG_OMAP34XX),) +obj-y += boot-common.o +obj-y += lowlevel_init.o +endif -######################################################################### +obj-y += mem-common.o diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c index a46783fae2..a0add6643e 100644 --- a/arch/arm/cpu/armv7/omap-common/abb.c +++ b/arch/arm/cpu/armv7/omap-common/abb.c @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -47,9 +48,9 @@ static void abb_setup_timings(u32 setup) */ /* calculate SR2_WTCNT_VALUE */ - sys_rate = DIV_ROUND(V_OSCK, 1000000); - clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); - sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); + sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000); + clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); + sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); setbits_le32(setup, sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1)); diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index ad383872c5..ab4a070f97 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -9,11 +9,14 @@ */ #include +#include #include #include #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -32,15 +35,27 @@ void save_omap_boot_params(void) * used. But it not correct to assume that romcode structure * encoding would be same as u-boot. So use the defined offsets. */ - gd->arch.omap_boot_params.omap_bootdevice = boot_device = - *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + +#if defined(BOOT_DEVICE_NAND_I2C) + /* + * Re-map NAND&I2C boot-device to the "normal" NAND boot-device. + * Otherwise the SPL boot IF can't handle this device correctly. + * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens + * Draco leads to this boot-device passed to SPL from the BootROM. + */ + if (boot_device == BOOT_DEVICE_NAND_I2C) + boot_device = BOOT_DEVICE_NAND; +#endif + gd->arch.omap_boot_params.omap_bootdevice = boot_device; gd->arch.omap_boot_params.ch_flags = *((u8 *)(rom_params + CH_FLAGS_OFFSET)); if ((boot_device >= MMC_BOOT_DEVICES_START) && (boot_device <= MMC_BOOT_DEVICES_END)) { -#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) +#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \ + !defined(CONFIG_AM43XX) if ((omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { gd->arch.omap_boot_params.omap_bootmode = @@ -54,6 +69,17 @@ void save_omap_boot_params(void) *((u32 *)(dev_data + BOOT_MODE_OFFSET)); } } + +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + /* + * We get different values for QSPI_1 and QSPI_4 being used, but + * don't actually care about this difference. Rather than + * mangle the later code, if we're coming in as QSPI_4 just + * change to the QSPI_1 value. + */ + if (gd->arch.omap_boot_params.omap_bootdevice == 11) + gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI; +#endif } #ifdef CONFIG_SPL_BUILD @@ -64,17 +90,44 @@ u32 spl_boot_device(void) u32 spl_boot_mode(void) { - return gd->arch.omap_boot_params.omap_bootmode; + u32 val = gd->arch.omap_boot_params.omap_bootmode; + + if (val == MMCSD_MODE_RAW) + return MMCSD_MODE_RAW; + else if (val == MMCSD_MODE_FS) + return MMCSD_MODE_FS; + else +#ifdef CONFIG_SUPPORT_EMMC_BOOT + return MMCSD_MODE_EMMCBOOT; +#else + return MMCSD_MODE_UNDEFINED; +#endif } void spl_board_init(void) { + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ + save_omap_boot_params(); + + /* Prepare console output */ + preloader_console_init(); + #ifdef CONFIG_SPL_NAND_SUPPORT gpmc_init(); #endif #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif +#ifdef CONFIG_AM33XX + am33xx_spl_board_init(); +#endif } int board_mmc_init(bd_t *bis) @@ -102,3 +155,10 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry((u32 *)&gd->arch.omap_boot_params); } #endif + +#ifdef CONFIG_SCSI_AHCI_PLAT +void arch_preboot_os(void) +{ + ahci_reset(DWC_AHSATA_BASE); +} +#endif diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 20fa678f9b..03674e609f 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -196,6 +196,18 @@ static const struct dpll_params *get_ddr_dpll_params return &dpll_data->ddr[sysclk_ind]; } +#ifdef CONFIG_DRIVER_TI_CPSW +static const struct dpll_params *get_gmac_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->gmac) + return NULL; + return &dpll_data->gmac[sysclk_ind]; +} +#endif + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { @@ -327,7 +339,7 @@ void configure_mpu_dpll(void) debug("MPU DPLL locked\n"); } -#ifdef CONFIG_USB_EHCI_OMAP +#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) static void setup_usb_dpll(void) { const struct dpll_params *params; @@ -392,62 +404,19 @@ static void setup_dplls(void) /* MPU dpll */ configure_mpu_dpll(); -#ifdef CONFIG_USB_EHCI_OMAP +#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) setup_usb_dpll(); #endif params = get_ddr_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, params, DPLL_LOCK, "ddr"); -} - -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL -static void setup_non_essential_dplls(void) -{ - u32 abe_ref_clk; - const struct dpll_params *params; - - /* IVA */ - clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, - CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - - params = get_iva_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); - /* Configure ABE dpll */ - params = get_abe_dpll_params(*dplls_data); -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; - - if (omap_revision() == DRA752_ES1_0) - /* Select the sys clk for dpll_abe */ - clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel, - CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK, - CM_ABE_PLL_SYS_CLKSEL_SYSCLK2); -#else - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; - /* - * We need to enable some additional options to achieve - * 196.608MHz from 32768 Hz - */ - setbits_le32((*prcm)->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| - CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| - CM_CLKMODE_DPLL_LPMODE_EN_MASK| - CM_CLKMODE_DPLL_REGM4XEN_MASK); - /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_RAMP_RATE_MASK, - 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); +#ifdef CONFIG_DRIVER_TI_CPSW + params = get_gmac_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, + DPLL_LOCK, "gmac"); #endif - - /* Select the right reference clk */ - clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel, - CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, - abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); - /* Lock the dpll */ - do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); } -#endif u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) { @@ -468,12 +437,15 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) { u32 offset_code; u32 offset = volt_mv; +#ifndef CONFIG_DRA7XX int ret = 0; +#endif if (!volt_mv) return; pmic->pmic_bus_init(); +#ifndef CONFIG_DRA7XX /* See if we can first get the GPIO if needed */ if (pmic->gpio_en) ret = gpio_request(pmic->gpio, "PMIC_GPIO"); @@ -487,7 +459,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) /* Pull the GPIO low to select SET0 register, while we program SET1 */ if (pmic->gpio_en) gpio_direction_output(pmic->gpio, 0); - +#endif /* convert to uV for better accuracy in the calculations */ offset *= 1000; @@ -498,9 +470,10 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) printf("Scaling voltage failed for 0x%x\n", vcore_reg); - +#ifndef CONFIG_DRA7XX if (pmic->gpio_en) gpio_direction_output(pmic->gpio, 1); +#endif } static u32 optimize_vcore_voltage(struct volts const *v) @@ -536,13 +509,79 @@ static u32 optimize_vcore_voltage(struct volts const *v) } /* - * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva - * We set the maximum voltages allowed here because Smart-Reflex is not - * enabled in bootloader. Voltage initialization in the kernel will set - * these to the nominal values after enabling Smart-Reflex + * Setup the voltages for the main SoC core power domains. + * We start with the maximum voltages allowed here, as set in the corresponding + * vcores_data struct, and then scale (usually down) to the fused values that + * are retrieved from the SoC. The scaling happens only if the efuse.reg fields + * are initialised. + * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is + * compiled conditionally. Note that the new code writes the scaled (or zeroed) + * values back to the vcores_data struct for eventual reuse. Zero values mean + * that the corresponding rails are not controlled separately, and are not sent + * to the PMIC. */ void scale_vcores(struct vcores_data const *vcores) { +#if defined(CONFIG_DRA7XX) + int i; + struct volts *pv = (struct volts *)vcores; + struct volts *px; + + for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) { + debug("%d -> ", pv->value); + if (pv->value) { + /* Handle non-empty members only */ + pv->value = optimize_vcore_voltage(pv); + px = (struct volts *)vcores; + while (px < pv) { + /* + * Scan already handled non-empty members to see + * if we have a group and find the max voltage, + * which is set to the first occurance of the + * particular SMPS; the other group voltages are + * zeroed. + */ + if (px->value) { + if ((pv->pmic->i2c_slave_addr == + px->pmic->i2c_slave_addr) && + (pv->addr == px->addr)) { + /* Same PMIC, same SMPS */ + if (pv->value > px->value) + px->value = pv->value; + + pv->value = 0; + } + } + px++; + } + } + debug("%d\n", pv->value); + pv++; + } + + debug("cor: %d\n", vcores->core.value); + do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic); + debug("mpu: %d\n", vcores->mpu.value); + do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic); + /* Configure MPU ABB LDO after scale */ + abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2, + (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, + (*prcm)->prm_abbldo_mpu_setup, + (*prcm)->prm_abbldo_mpu_ctrl, + (*prcm)->prm_irqstatus_mpu_2, + OMAP_ABB_MPU_TXDONE_MASK, + OMAP_ABB_FAST_OPP); + + /* The .mm member is not used for the DRA7xx */ + + debug("gpu: %d\n", vcores->gpu.value); + do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic); + debug("eve: %d\n", vcores->eve.value); + do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic); + debug("iva: %d\n", vcores->iva.value); + do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic); + /* Might need udelay(1000) here if debug is enabled to see all prints */ +#else u32 val; val = optimize_vcore_voltage(&vcores->core); @@ -571,13 +610,7 @@ void scale_vcores(struct vcores_data const *vcores) val = optimize_vcore_voltage(&vcores->iva); do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); - - if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { - /* Configure LDO SRAM "magic" bits */ - writel(2, (*prcm)->prm_sldo_core_setup); - writel(2, (*prcm)->prm_sldo_mpu_setup); - writel(2, (*prcm)->prm_sldo_mm_setup); - } +#endif } static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) @@ -749,10 +782,6 @@ void prcm_init(void) timer_init(); scale_vcores(*omap_vcores); setup_dplls(); -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL - setup_non_essential_dplls(); - enable_non_essential_clocks(); -#endif setup_warmreset_time(); break; default: @@ -768,7 +797,8 @@ void gpi2c_init(void) static int gpi2c = 1; if (gpi2c) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); gpi2c = 0; } } diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index ece365507c..e601ba1886 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -50,20 +50,6 @@ inline u32 emif_num(u32 base) return 0; } -/* - * Get SDRAM type connected to EMIF. - * Assuming similar SDRAM parts are connected to both EMIF's - * which is typically the case. So it is sufficient to get - * SDRAM type from EMIF1. - */ -u32 emif_sdram_type() -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - return (readl(&emif->emif_sdram_config) & - EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; -} - static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { u32 mr; @@ -153,7 +139,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) * un-locked frequency & default RL */ writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); do_ext_phy_settings(base, regs); @@ -193,8 +179,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - if ((omap_revision() >= OMAP5430_ES1_0) || - (omap_revision() == DRA752_ES1_0)) { + if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -206,7 +191,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) } } -static void ddr3_leveling(u32 base, const struct emif_regs *regs) +static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -217,47 +202,50 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) /* * Set invert_clkout (if activated)--DDR_PHYCTRL_1 - * Invert clock adds an additional half cycle delay on the command - * interface. The additional half cycle, is usually meant to enable - * leveling in the situation that DQS is later than CK on the board.It - * also helps provide some additional margin for leveling. + * Invert clock adds an additional half cycle delay on the + * command interface. The additional half cycle, is usually + * meant to enable leveling in the situation that DQS is later + * than CK on the board.It also helps provide some additional + * margin for leveling. */ - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + writel(regs->emif_ddr_phy_ctlr_1, + &emif->emif_ddr_phy_ctrl_1); + + writel(regs->emif_ddr_phy_ctlr_1, + &emif->emif_ddr_phy_ctrl_1_shdw); __udelay(130); writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) - & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); /* Launch Full leveling */ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); /* Wait till full leveling is complete */ readl(&emif->emif_rd_wr_lvl_ctl); - __udelay(130); + __udelay(130); /* Read data eye leveling no of samples */ config_data_eye_leveling_samples(base); - /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */ - writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl); + /* + * Launch 8 incremental WR_LVL- to compensate for + * PHY limitation. + */ + writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, + &emif->emif_rd_wr_lvl_ctl); + __udelay(130); /* Launch Incremental leveling */ writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); - __udelay(130); + __udelay(130); } -static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs) +static void ddr3_leveling(u32 base, const struct emif_regs *regs) { - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - config_data_eye_leveling_samples(base); - - writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); - writel(regs->sdram_config, &emif->emif_sdram_config); + if (is_omap54xx()) + omap5_ddr3_leveling(base, regs); } static void ddr3_init(u32 base, const struct emif_regs *regs) @@ -270,9 +258,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) * defined, contents of mode Registers must be fully initialized. * H/W takes care of this initialization */ - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); /* Update timing registers */ @@ -283,15 +268,24 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - do_ext_phy_settings(base, regs); + /* + * The same sequence should work on OMAP5432 as well. But strange that + * it is not working + */ + if (is_dra7xx()) { + do_ext_phy_settings(base, regs); + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + } else { + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + do_ext_phy_settings(base, regs); + } /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - if (omap_revision() == DRA752_ES1_0) - ddr3_sw_leveling(base, regs); - else - ddr3_leveling(base, regs); + ddr3_leveling(base, regs); } #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS @@ -1079,10 +1073,7 @@ static void do_sdram_init(u32 base) if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { set_lpmode_selfrefresh(base); emif_reset_phy(base); - if (omap_revision() == DRA752_ES1_0) - ddr3_sw_leveling(base, regs); - else - ddr3_leveling(base, regs); + ddr3_leveling(base, regs); } /* Write to the shadow registers */ @@ -1235,13 +1226,50 @@ void dmm_init(u32 base) emif1_enabled = 1; emif2_enabled = 1; break; - } else if (valid == 1) { + } + + if (valid == 1) emif1_enabled = 1; - } else if (valid == 2) { + + if (valid == 2) emif2_enabled = 1; - } + } +} + +static void do_bug0039_workaround(u32 base) +{ + u32 val, i, clkctrl; + struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; + const struct read_write_regs *bug_00339_regs; + u32 iterations; + u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; + u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; + + if (is_dra7xx()) + phy_status_base++; + + bug_00339_regs = get_bug_regs(&iterations); + + /* Put EMIF in to idle */ + clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); + __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); + + /* Copy the phy status registers in to phy ctrl shadow registers */ + for (i = 0; i < iterations; i++) { + val = __raw_readl(phy_status_base + + bug_00339_regs[i].read_reg - 1); + + __raw_writel(val, phy_ctrl_base + + ((bug_00339_regs[i].write_reg - 1) << 1)); + + __raw_writel(val, phy_ctrl_base + + (bug_00339_regs[i].write_reg << 1) - 1); } + /* Disable leveling */ + writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); + + __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); } /* @@ -1319,5 +1347,13 @@ void sdram_init(void) debug("get_ram_size() successful"); } + if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && + (!in_sdram && !warm_reset()) && (!is_dra7xx())) { + if (emif1_enabled) + do_bug0039_workaround(EMIF1_BASE); + if (emif2_enabled) + do_bug0039_workaround(EMIF2_BASE); + } + debug("< #include #include -#include +#include #include #include #include -#include #include -#define ARMV7_DCACHE_WRITEBACK 0xe -#define ARMV7_DOMAIN_CLIENT 1 -#define ARMV7_DOMAIN_MASK (0x3 << 0) - DECLARE_GLOBAL_DATA_PTR; void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) @@ -43,16 +38,10 @@ static void set_mux_conf_regs(void) set_muxconf_regs_essential(); break; case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: set_muxconf_regs_essential(); -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; } } @@ -122,19 +111,12 @@ int arch_cpu_init(void) */ void s_init(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif init_omap_revision(); hw_data_init(); #ifdef CONFIG_SPL_BUILD - if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) + if (warm_reset() && + (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0))) force_emif_self_refresh(); #endif watchdog_init(); @@ -143,13 +125,13 @@ void s_init(void) srcomp_enable(); setup_clocks_for_console(); - gd = &gdata; - - preloader_console_init(); do_io_settings(); #endif prcm_init(); #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_BOARD_EARLY_INIT_F + board_early_init_f(); +#endif /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); #endif @@ -191,7 +173,7 @@ u32 omap_sdram_size(void) { u32 section, i, valid; u64 sdram_start = 0, sdram_end = 0, addr, - size, total_size = 0, trap_size = 0; + size, total_size = 0, trap_size = 0, trap_start = 0; for (i = 0; i < 4; i++) { section = __raw_readl(DMM_BASE + i*4); @@ -200,8 +182,8 @@ u32 omap_sdram_size(void) addr = section & EMIF_SYS_ADDR_MASK; /* See if the address is valid */ - if ((addr >= DRAM_ADDR_SPACE_START) && - (addr < DRAM_ADDR_SPACE_END)) { + if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { size = ((section & EMIF_SYS_SIZE_MASK) >> EMIF_SYS_SIZE_SHIFT); size = 1 << size; @@ -214,12 +196,15 @@ u32 omap_sdram_size(void) sdram_end = addr + size; } else { trap_size = size; + trap_start = addr; } - } - } - total_size = (sdram_end - sdram_start) - (trap_size); + + if ((trap_start >= sdram_start) && (trap_start < sdram_end)) + total_size = (sdram_end - sdram_start) - (trap_size); + else + total_size = sdram_end - sdram_start; return total_size; } @@ -254,6 +239,7 @@ u32 get_device_type(void) (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; } +#if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information */ @@ -264,39 +250,4 @@ int print_cpuinfo(void) return 0; } -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} - -void dram_bank_mmu_setup(int bank) -{ - bd_t *bd = gd->bd; - int i; - - u32 start = bd->bi_dram[bank].start >> 20; - u32 size = bd->bi_dram[bank].size >> 20; - u32 end = start + size; - - debug("%s: bank: %d\n", __func__, bank); - for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); - -} - -void arm_init_domains(void) -{ - u32 reg; - - reg = get_dacr(); - /* - * Set DOMAIN to client access so that all permissions - * set in pagetables are validated by the mmu. - */ - reg &= ~ARMV7_DOMAIN_MASK; - reg |= ARMV7_DOMAIN_CLIENT; - set_dacr(reg); -} #endif diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index afc1bc185e..fc4290c3c4 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -2,31 +2,143 @@ * (C) Copyright 2010 * Texas Instruments, * - * Steve Sakoman + * Author : + * Mansoor Ahamed + * + * Initial Code from: + * Manikandan Pillai + * Richard Woodruff + * Syed Mohammed Khasim * * SPDX-License-Identifier: GPL-2.0+ */ +#include +#include #include +#include #include +#include +#include struct gpmc *gpmc_cfg; +#if defined(CONFIG_OMAP34XX) +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in guessing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(u32 cs) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); + + writel(0x0, addr + 0x400); /* clear pos A */ + writel(pattern, addr); /* pattern to pos B */ + writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = readl(addr + 0x400); /* get pos A value */ + val2 = readl(addr); /* get val2 */ + writel(0x0, addr + 0x400); /* clear pos A */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ + return 0; + else + return 1; +} +#endif + +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + /* Enable the config */ + writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), &cs->config7); + sdelay(2000); +} + /***************************************************** * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). * This code can only be executed from SRAM or SDRAM. *****************************************************/ void gpmc_init(void) { + /* putting a blanket check on GPMC based on ZeBu for now */ gpmc_cfg = (struct gpmc *)GPMC_BASE; +#if defined(CONFIG_NOR) +/* configure GPMC for NOR */ + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; + u32 base = CONFIG_SYS_FLASH_BASE; + u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + /* min 16MB */ GPMC_SIZE_16M))); +#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) +/* configure GPMC for NAND */ + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; + u32 base = CONFIG_SYS_NAND_BASE; + u32 size = GPMC_SIZE_16M; +#elif defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, + 0 + }; + u32 size = GPMC_SIZE_128M; + u32 base = CONFIG_SYS_ONENAND_BASE; +#else + const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; + u32 size = 0; + u32 base = 0; +#endif /* global settings */ - writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ - writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ - + writel(0x00000008, &gpmc_cfg->sysconfig); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); + /* disable timeout, set a safe reset value */ + writel(0x00001ff0, &gpmc_cfg->timeout_control); +#ifdef CONFIG_NOR + writel(0x00000200, &gpmc_cfg->config); +#else + writel(0x00000012, &gpmc_cfg->config); +#endif /* * Disable the GPMC0 config set by ROM code - * It conflicts with our MPDB (both at 0x08000000) */ writel(0, &gpmc_cfg->cs[0].config7); + sdelay(1000); + /* enable chip-select specific configurations */ + if (base != 0) + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c new file mode 100644 index 0000000000..579bebf93f --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -0,0 +1,56 @@ +/* + * + * Common functions for OMAP4/5 based boards + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Author : + * Aneesh V + * Steve Sakoman + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c new file mode 100644 index 0000000000..b71d769410 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c @@ -0,0 +1,231 @@ +/* + * TI PIPE3 PHY + * + * (C) Copyright 2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "pipe3-phy.h" + +/* PLLCTRL Registers */ +#define PLL_STATUS 0x00000004 +#define PLL_GO 0x00000008 +#define PLL_CONFIGURATION1 0x0000000C +#define PLL_CONFIGURATION2 0x00000010 +#define PLL_CONFIGURATION3 0x00000014 +#define PLL_CONFIGURATION4 0x00000020 + +#define PLL_REGM_MASK 0x001FFE00 +#define PLL_REGM_SHIFT 9 +#define PLL_REGM_F_MASK 0x0003FFFF +#define PLL_REGM_F_SHIFT 0 +#define PLL_REGN_MASK 0x000001FE +#define PLL_REGN_SHIFT 1 +#define PLL_SELFREQDCO_MASK 0x0000000E +#define PLL_SELFREQDCO_SHIFT 1 +#define PLL_SD_MASK 0x0003FC00 +#define PLL_SD_SHIFT 10 +#define SET_PLL_GO 0x1 +#define PLL_TICOPWDN BIT(16) +#define PLL_LDOPWDN BIT(15) +#define PLL_LOCK 0x2 +#define PLL_IDLE 0x1 + +/* PHY POWER CONTROL Register */ +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE + +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 + +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 + + +#define PLL_IDLE_TIME 100 /* in milliseconds */ +#define PLL_LOCK_TIME 100 /* in milliseconds */ + +static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) +{ + return __raw_readl(addr + offset); +} + +static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, + u32 data) +{ + __raw_writel(data, addr + offset); +} + +static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 + *pipe3) +{ + u32 rate; + struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; + + rate = get_sys_clk_freq(); + + for (; dpll_map->rate; dpll_map++) { + if (rate == dpll_map->rate) + return &dpll_map->params; + } + + printf("%s: No DPLL configuration for %u Hz SYS CLK\n", + __func__, rate); + return NULL; +} + + +static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) +{ + u32 val; + int timeout = PLL_LOCK_TIME; + + do { + mdelay(1); + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (val & PLL_LOCK) + break; + } while (--timeout); + + if (!(val & PLL_LOCK)) { + printf("%s: DPLL failed to lock\n", __func__); + return -EBUSY; + } + + return 0; +} + +static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) +{ + u32 val; + struct pipe3_dpll_params *dpll_params; + + dpll_params = omap_pipe3_get_dpll_params(phy); + if (!dpll_params) { + printf("%s: Invalid DPLL parameters\n", __func__); + return -EINVAL; + } + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGN_MASK; + val |= dpll_params->n << PLL_REGN_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val &= ~PLL_SELFREQDCO_MASK; + val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGM_MASK; + val |= dpll_params->m << PLL_REGM_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); + val &= ~PLL_REGM_F_MASK; + val |= dpll_params->mf << PLL_REGM_F_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); + val &= ~PLL_SD_MASK; + val |= dpll_params->sd << PLL_SD_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); + + omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); + + return omap_pipe3_wait_lock(phy); +} + +static void omap_control_phy_power(struct omap_pipe3 *phy, int on) +{ + u32 val, rate; + + val = readl(phy->power_reg); + + rate = get_sys_clk_freq(); + rate = rate/1000000; + + if (on) { + val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + val |= rate << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; + } else { + val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + } + + writel(val, phy->power_reg); +} + +int phy_pipe3_power_on(struct omap_pipe3 *phy) +{ + int ret; + u32 val; + + /* Program the DPLL only if not locked */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (!(val & PLL_LOCK)) { + ret = omap_pipe3_dpll_program(phy); + if (ret) + return ret; + } else { + /* else just bring it out of IDLE mode */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + if (val & PLL_IDLE) { + val &= ~PLL_IDLE; + omap_pipe3_writel(phy->pll_ctrl_base, + PLL_CONFIGURATION2, val); + ret = omap_pipe3_wait_lock(phy); + if (ret) + return ret; + } + } + + /* Power up the PHY */ + omap_control_phy_power(phy, 1); + + return 0; +} + +int phy_pipe3_power_off(struct omap_pipe3 *phy) +{ + u32 val; + int timeout = PLL_IDLE_TIME; + + /* Power down the PHY */ + omap_control_phy_power(phy, 0); + + /* Put DPLL in IDLE mode */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val |= PLL_IDLE; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + /* wait for LDO and Oscillator to power down */ + do { + mdelay(1); + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) + break; + } while (--timeout); + + if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { + printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", + __func__, val); + return -EBUSY; + } + + return 0; +} + diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h new file mode 100644 index 0000000000..441f49a3f9 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h @@ -0,0 +1,36 @@ +/* + * TI PIPE3 PHY + * + * (C) Copyright 2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_PIPE3_PHY_H +#define __OMAP_PIPE3_PHY_H + +struct pipe3_dpll_params { + u16 m; + u8 n; + u8 freq:3; + u8 sd; + u32 mf; +}; + +struct pipe3_dpll_map { + unsigned long rate; + struct pipe3_dpll_params params; +}; + +struct omap_pipe3 { + void __iomem *pll_ctrl_base; + void __iomem *power_reg; + struct pipe3_dpll_map *dpll_map; +}; + + +int phy_pipe3_power_on(struct omap_pipe3 *phy); +int phy_pipe3_power_off(struct omap_pipe3 *pipe3); + +#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c new file mode 100644 index 0000000000..d18bc50c5a --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -0,0 +1,93 @@ +/* + * TI SATA platform driver + * + * (C) Copyright 2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "pipe3-phy.h" + +static struct pipe3_dpll_map dpll_map_sata[] = { + {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ + {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ + {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ + {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ + {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ + {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ + { }, /* Terminator */ +}; + +struct omap_pipe3 sata_phy = { + .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, + /* .power_reg is updated at runtime */ + .dpll_map = dpll_map_sata, +}; + +int init_sata(int dev) +{ + int ret; + u32 val; + + u32 const clk_domains_sata[] = { + 0 + }; + + u32 const clk_modules_hw_auto_sata[] = { + (*prcm)->cm_l3init_ocp2scp3_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_sata[] = { + (*prcm)->cm_l3init_sata_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_sata, + clk_modules_hw_auto_sata, + clk_modules_explicit_en_sata, + 0); + + /* Enable optional functional clock for SATA */ + setbits_le32((*prcm)->cm_l3init_sata_clkctrl, + SATA_CLKCTRL_OPTFCLKEN_MASK); + + sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; + + /* Power up the PHY */ + phy_pipe3_power_on(&sata_phy); + + /* Enable SATA module, No Idle, No Standby */ + val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; + writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); + + ret = ahci_init(DWC_AHSATA_BASE); + + return ret; +} + +int reset_sata(int dev) +{ + return 0; +} + +/* On OMAP platforms SATA provides the SCSI subsystem */ +void scsi_init(void) +{ + init_sata(0); + scsi_scan(1); +} + +void scsi_bus_reset(void) +{ + ahci_reset(DWC_AHSATA_BASE); + ahci_init(DWC_AHSATA_BASE); +} diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 5e93b343e6..ccd0c8352e 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -22,6 +22,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sram @@ -32,9 +33,18 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } >.sram + . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } .bss : { diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c index aabf2bd613..1696c2dbda 100644 --- a/arch/arm/cpu/armv7/omap-common/utils.c +++ b/arch/arm/cpu/armv7/omap-common/utils.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include static void do_cancel_out(u32 *num, u32 *den, u32 factor) { while (1) { @@ -39,3 +40,23 @@ void cancel_out(u32 *num, u32 *den, u32 den_limit) *den = (*den + 1) / 2; } } + +void __weak usb_fake_mac_from_die_id(u32 *id) +{ + uint8_t device_mac[6]; + + if (!getenv("usbethaddr")) { + /* + * create a fake MAC address from the processor ID code. + * first byte is 0x02 to signify locally administered. + */ + device_mac[0] = 0x02; + device_mac[1] = id[3] & 0xff; + device_mac[2] = id[2] & 0xff; + device_mac[3] = id[1] & 0xff; + device_mac[4] = id[0] & 0xff; + device_mac[5] = (id[0] >> 8) & 0xff; + + eth_setenv_enetaddr("usbethaddr", device_mac); + } +} diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig new file mode 100644 index 0000000000..a029379a4f --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -0,0 +1,122 @@ +if OMAP34XX + +choice + prompt "OMAP3 board select" + +config TARGET_AM3517_EVM + bool "AM3517 EVM" + select SUPPORT_SPL + +config TARGET_MT_VENTOUX + bool "TeeJet Mt.Ventoux" + select SUPPORT_SPL + +config TARGET_OMAP3_SDP3430 + bool "TI OMAP3430 SDP" + +config TARGET_OMAP3_BEAGLE + bool "TI OMAP3 BeagleBoard" + select SUPPORT_SPL + +config TARGET_CM_T35 + bool "CompuLab CM-T3530 and CM-T3730 boards" + select SUPPORT_SPL + +config TARGET_CM_T3517 + bool "CompuLab CM-T3517 boards" + +config TARGET_DEVKIT8000 + bool "TimLL OMAP3 Devkit8000" + select SUPPORT_SPL + +config TARGET_OMAP3_EVM + bool "TI OMAP3 EVM" + select SUPPORT_SPL + +config TARGET_OMAP3_EVM_QUICK_MMC + bool "TI OMAP3 EVM Quick MMC" + select SUPPORT_SPL + +config TARGET_OMAP3_EVM_QUICK_NAND + bool "TI OMAP3 EVM Quick NAND" + select SUPPORT_SPL + +config TARGET_OMAP3_IGEP00X0 + bool "IGEP" + select SUPPORT_SPL + +config TARGET_OMAP3_OVERO + bool "OMAP35xx Gumstix Overo" + select SUPPORT_SPL + +config TARGET_OMAP3_ZOOM1 + bool "TI Zoom1" + +config TARGET_AM3517_CRANE + bool "am3517_crane" + select SUPPORT_SPL + +config TARGET_OMAP3_PANDORA + bool "OMAP3 Pandora" + +config TARGET_ECO5PK + bool "ECO5PK" + select SUPPORT_SPL + +config TARGET_DIG297 + bool "DIG297" + +config TARGET_TRICORDER + bool "Tricorder" + select SUPPORT_SPL + +config TARGET_MCX + bool "MCX" + select SUPPORT_SPL + +config TARGET_OMAP3_LOGIC + bool "OMAP3 Logic" + +config TARGET_OMAP3_MVBLX + bool "OMAP3 MVBLX" + +config TARGET_NOKIA_RX51 + bool "Nokia RX51" + +config TARGET_TAO3530 + bool "TAO3530" + select SUPPORT_SPL + +config TARGET_TWISTER + bool "Twister" + select SUPPORT_SPL + +endchoice + +config SYS_SOC + default "omap3" + +source "board/logicpd/am3517evm/Kconfig" +source "board/teejet/mt_ventoux/Kconfig" +source "board/ti/sdp3430/Kconfig" +source "board/ti/beagle/Kconfig" +source "board/compulab/cm_t35/Kconfig" +source "board/compulab/cm_t3517/Kconfig" +source "board/timll/devkit8000/Kconfig" +source "board/ti/evm/Kconfig" +source "board/isee/igep00x0/Kconfig" +source "board/overo/Kconfig" +source "board/logicpd/zoom1/Kconfig" +source "board/ti/am3517crane/Kconfig" +source "board/pandora/Kconfig" +source "board/8dtech/eco5pk/Kconfig" +source "board/comelit/dig297/Kconfig" +source "board/corscience/tricorder/Kconfig" +source "board/htkw/mcx/Kconfig" +source "board/logicpd/omap3som/Kconfig" +source "board/matrix_vision/mvblx/Kconfig" +source "board/nokia/rx51/Kconfig" +source "board/technexion/tao3530/Kconfig" +source "board/technexion/twister/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index f070c18196..cf86046353 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -5,38 +5,16 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := lowlevel_init.o -LIB = $(obj)lib$(SOC).o - -SOBJS := lowlevel_init.o - -COBJS += board.o -COBJS += clock.o -COBJS += mem.o -COBJS += sys_info.o +obj-y += board.o +obj-y += clock.o +obj-y += sys_info.o ifdef CONFIG_SPL_BUILD -COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o +obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o endif -COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o -COBJS-$(CONFIG_EMIF4) += emif4.o -COBJS-$(CONFIG_SDRC) += sdrc.o -COBJS-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_DRIVER_TI_EMAC) += emac.o +obj-$(CONFIG_EMIF4) += emif4.o +obj-$(CONFIG_SDRC) += sdrc.o +obj-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o diff --git a/arch/arm/cpu/armv7/omap3/am35x_musb.c b/arch/arm/cpu/armv7/omap3/am35x_musb.c index 9a31f8a1d1..74dd105eb6 100644 --- a/arch/arm/cpu/armv7/omap3/am35x_musb.c +++ b/arch/arm/cpu/armv7/omap3/am35x_musb.c @@ -59,4 +59,3 @@ void am35x_musb_clear_irq(void) 0, USBOTGSS_INT_CLR); readl(&am35x_scm_general_regs->lvl_intr_clr); } - diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7d1f8d9d2c..90d6ae7bb5 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -17,13 +17,15 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include #include #include #include #include #include #include -#include +#include #include #include #include @@ -38,6 +40,27 @@ static void omap3_setup_aux_cr(void); static void omap3_invalidate_l2_cache_secure(void); #endif +#ifdef CONFIG_DM_GPIO +static const struct omap_gpio_platdata omap34xx_gpio[] = { + { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, + { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, + { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, +}; + +U_BOOT_DEVICES(am33xx_gpios) = { + { "gpio_omap", &omap34xx_gpio[0] }, + { "gpio_omap", &omap34xx_gpio[1] }, + { "gpio_omap", &omap34xx_gpio[2] }, + { "gpio_omap", &omap34xx_gpio[3] }, + { "gpio_omap", &omap34xx_gpio[4] }, + { "gpio_omap", &omap34xx_gpio[5] }, +}; + +#else + static const struct gpio_bank gpio_bank_34xx[6] = { { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, @@ -49,6 +72,8 @@ static const struct gpio_bank gpio_bank_34xx[6] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; +#endif + #ifdef CONFIG_SPL_BUILD /* * We use static variables because global data is not ready yet. @@ -65,7 +90,7 @@ u32 spl_boot_mode(void) case BOOT_DEVICE_MMC2: return MMCSD_MODE_RAW; case BOOT_DEVICE_MMC1: - return MMCSD_MODE_FAT; + return MMCSD_MODE_FS; break; default: puts("spl: ERROR: unknown device - can't select boot mode\n"); @@ -94,11 +119,12 @@ int board_mmc_init(bd_t *bis) void spl_board_init(void) { + preloader_console_init(); #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) gpmc_init(); #endif #ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif } #endif /* CONFIG_SPL_BUILD */ @@ -147,7 +173,7 @@ void secure_unlock_mem(void) * configure secure registers and exit secure world * general use. *****************************************************************************/ -void secureworld_exit() +void secureworld_exit(void) { unsigned long i; @@ -178,7 +204,7 @@ void secureworld_exit() * Description: If chip is GP/EMU(special) type, unlock the SRAM for * general use. *****************************************************************************/ -void try_unlock_memory() +void try_unlock_memory(void) { int mode; int in_sdram = is_running_in_sdram(); @@ -239,14 +265,6 @@ void s_init(void) ehci_clocks_enable(); #endif -#ifdef CONFIG_SPL_BUILD - gd = &gdata; - - preloader_console_init(); - - timer_init(); -#endif - if (!in_sdram) mem_init(); } @@ -266,7 +284,7 @@ int __weak misc_init_r(void) * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog *****************************************************************************/ -void wait_for_command_complete(struct watchdog *wd_base) +static void wait_for_command_complete(struct watchdog *wd_base) { int pending = 1; do { @@ -290,8 +308,8 @@ void watchdog_init(void) * should not be running and does not generate a PRCM reset. */ - sr32(&prcm_base->fclken_wkup, 5, 1, 1); - sr32(&prcm_base->iclken_wkup, 5, 1, 1); + setbits_le32(&prcm_base->fclken_wkup, 0x20); + setbits_le32(&prcm_base->iclken_wkup, 0x20); wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); writel(WD_UNLOCK1, &wd2_base->wspr); @@ -478,11 +496,3 @@ void omap3_outer_cache_disable(void) omap3_update_aux_cr(0, 0x2); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 3acbc9c864..006969e780 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -132,9 +132,9 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index) if (xip_safe) { /* * CORE DPLL - * sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS); + clrsetbits_le32(&prcm_base->clken_pll, + 0x00000007, PLL_FAST_RELOCK_BYPASS); wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); @@ -144,37 +144,50 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index) */ /* CM_CLKSEL1_EMU[DIV_DPLL3] */ - sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ; - sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2); + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x001F0000, (CORE_M3X2 + 1) << 16) ; + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x001F0000, CORE_M3X2 << 16); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ - sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2); + clrsetbits_le32(&prcm_base->clksel1_pll, + 0xF8000000, ptr->m2 << 27); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ - sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m); + clrsetbits_le32(&prcm_base->clksel1_pll, + 0x07FF0000, ptr->m << 16); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ - sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n); + clrsetbits_le32(&prcm_base->clksel1_pll, + 0x00007F00, ptr->n << 8); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ - sr32(&prcm_base->clksel1_pll, 6, 1, 0); + clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); /* SSI */ - sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV); + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000F00, CORE_SSI_DIV << 8); /* FSUSB */ - sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV); + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000030, CORE_FUSB_DIV << 4); /* L4 */ - sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV); + clrsetbits_le32(&prcm_base->clksel_core, + 0x0000000C, CORE_L4_DIV << 2); /* L3 */ - sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000003, CORE_L3_DIV); /* GFX */ - sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); + clrsetbits_le32(&prcm_base->clksel_gfx, + 0x00000007, GFX_DIV); /* RESET MGR */ - sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); + clrsetbits_le32(&prcm_base->clksel_wkup, + 0x00000006, WKUP_RSM << 1); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ - sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); + clrsetbits_le32(&prcm_base->clken_pll, + 0x000000F0, ptr->fsel << 4); /* LOCK MODE */ - sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); + clrsetbits_le32(&prcm_base->clken_pll, + 0x00000007, PLL_LOCK); wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, LDELAY); @@ -183,33 +196,32 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index) * if running from flash, jump to small relocated code * area in SRAM. */ - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); - sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); + clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ - sr32(&p0, 4, 4, ptr->fsel); + clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); p1 = readl(&prcm_base->clksel1_pll); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ - sr32(&p1, 27, 5, ptr->m2); + clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ - sr32(&p1, 16, 11, ptr->m); + clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ - sr32(&p1, 8, 7, ptr->n); + clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ - sr32(&p1, 6, 1, 0); + clrbits_le32(&p1, 0x00000040); p2 = readl(&prcm_base->clksel_core); /* SSI */ - sr32(&p2, 8, 4, CORE_SSI_DIV); + clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); /* FSUSB */ - sr32(&p2, 4, 2, CORE_FUSB_DIV); + clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); /* L4 */ - sr32(&p2, 2, 2, CORE_L4_DIV); + clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); /* L3 */ - sr32(&p2, 0, 2, CORE_L3_DIV); + clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); p3 = (u32)&prcm_base->idlest_ckgen; @@ -226,7 +238,7 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index) ptr = ptr + clk_index; /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ - sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); + clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); /* @@ -235,33 +247,38 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index) * and then the actual divisor value */ /* M6 */ - sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1)); - sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x1F000000, (PER_M6X2 + 1) << 24); + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x1F000000, PER_M6X2 << 24); /* M5 */ - sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1)); - sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); + clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1)); + clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2); /* M4 */ - sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1)); - sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); + clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1)); + clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2); /* M3 */ - sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1)); - sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); + clrsetbits_le32(&prcm_base->clksel_dss, + 0x00001F00, (PER_M3X2 + 1) << 8); + clrsetbits_le32(&prcm_base->clksel_dss, + 0x00001F00, PER_M3X2 << 8); /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ - sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1)); - sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2); + clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1)); + clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); /* Workaround end */ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */ - sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m); + clrsetbits_le32(&prcm_base->clksel2_pll, + 0x0007FF00, ptr->m << 8); /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ - sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n); + clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */ - sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel); + clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20); /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ - sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); + clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); } @@ -274,13 +291,18 @@ static void dpll5_init_34xx(u32 sil_index, u32 clk_index) ptr = ptr + clk_index; /* PER2 DPLL (DPLL5) */ - sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP); + clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); - sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */ - sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */ - sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/ - sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */ - sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */ + /* set M2 (usbtll_fck) */ + clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); + /* set m (11-bit multiplier) */ + clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); + /* set n (7-bit divider)*/ + clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); + /* FREQSEL */ + clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4); + /* lock mode */ + clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); } @@ -295,16 +317,20 @@ static void mpu_init_34xx(u32 sil_index, u32 clk_index) /* MPU DPLL (unlocked already) */ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ - sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2); + clrsetbits_le32(&prcm_base->clksel2_pll_mpu, + 0x0000001F, ptr->m2); /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ - sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m); + clrsetbits_le32(&prcm_base->clksel1_pll_mpu, + 0x0007FF00, ptr->m << 8); /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ - sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n); + clrsetbits_le32(&prcm_base->clksel1_pll_mpu, + 0x0000007F, ptr->n); /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */ - sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel); + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x000000F0, ptr->fsel << 4); } static void iva_init_34xx(u32 sil_index, u32 clk_index) @@ -317,23 +343,29 @@ static void iva_init_34xx(u32 sil_index, u32 clk_index) /* IVA DPLL */ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ - sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP); + clrsetbits_le32(&prcm_base->clken_pll_iva2, + 0x00000007, PLL_STOP); wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ - sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2); + clrsetbits_le32(&prcm_base->clksel2_pll_iva2, + 0x0000001F, ptr->m2); /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ - sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m); + clrsetbits_le32(&prcm_base->clksel1_pll_iva2, + 0x0007FF00, ptr->m << 8); /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ - sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n); + clrsetbits_le32(&prcm_base->clksel1_pll_iva2, + 0x0000007F, ptr->n); /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */ - sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel); + clrsetbits_le32(&prcm_base->clken_pll_iva2, + 0x000000F0, ptr->fsel << 4); /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ - sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK); + clrsetbits_le32(&prcm_base->clken_pll_iva2, + 0x00000007, PLL_LOCK); wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); } @@ -358,41 +390,54 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index) /* CORE DPLL */ /* Select relock bypass: CM_CLKEN_PLL[0:2] */ - sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS); + clrsetbits_le32(&prcm_base->clken_pll, + 0x00000007, PLL_FAST_RELOCK_BYPASS); wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); /* CM_CLKSEL1_EMU[DIV_DPLL3] */ - sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2); + clrsetbits_le32(&prcm_base->clksel1_emu, + 0x001F0000, CORE_M3X2 << 16); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ - sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2); + clrsetbits_le32(&prcm_base->clksel1_pll, + 0xF8000000, ptr->m2 << 27); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ - sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m); + clrsetbits_le32(&prcm_base->clksel1_pll, + 0x07FF0000, ptr->m << 16); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ - sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n); + clrsetbits_le32(&prcm_base->clksel1_pll, + 0x00007F00, ptr->n << 8); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ - sr32(&prcm_base->clksel1_pll, 6, 1, 0); + clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); /* SSI */ - sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV); + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000F00, CORE_SSI_DIV << 8); /* FSUSB */ - sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV); + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000030, CORE_FUSB_DIV << 4); /* L4 */ - sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV); + clrsetbits_le32(&prcm_base->clksel_core, + 0x0000000C, CORE_L4_DIV << 2); /* L3 */ - sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); + clrsetbits_le32(&prcm_base->clksel_core, + 0x00000003, CORE_L3_DIV); /* GFX */ - sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X); + clrsetbits_le32(&prcm_base->clksel_gfx, + 0x00000007, GFX_DIV_36X); /* RESET MGR */ - sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); + clrsetbits_le32(&prcm_base->clksel_wkup, + 0x00000006, WKUP_RSM << 1); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ - sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); + clrsetbits_le32(&prcm_base->clken_pll, + 0x000000F0, ptr->fsel << 4); /* LOCK MODE */ - sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); + clrsetbits_le32(&prcm_base->clken_pll, + 0x00000007, PLL_LOCK); wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, LDELAY); @@ -401,33 +446,32 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index) * if running from flash, jump to small relocated code * area in SRAM. */ - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); - sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); + clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ - sr32(&p0, 4, 4, ptr->fsel); + clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); p1 = readl(&prcm_base->clksel1_pll); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ - sr32(&p1, 27, 5, ptr->m2); + clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ - sr32(&p1, 16, 11, ptr->m); + clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ - sr32(&p1, 8, 7, ptr->n); + clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ - sr32(&p1, 6, 1, 0); + clrbits_le32(&p1, 0x00000040); p2 = readl(&prcm_base->clksel_core); /* SSI */ - sr32(&p2, 8, 4, CORE_SSI_DIV); + clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); /* FSUSB */ - sr32(&p2, 4, 2, CORE_FUSB_DIV); + clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); /* L4 */ - sr32(&p2, 2, 2, CORE_L4_DIV); + clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); /* L3 */ - sr32(&p2, 0, 2, CORE_L3_DIV); + clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); p3 = (u32)&prcm_base->idlest_ckgen; @@ -446,38 +490,60 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index) ptr += clk_index; /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ - sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); + clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */ - sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6); + clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24); /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */ - sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5); + clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5); /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */ - sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4); + clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4); /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */ - sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3); + clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8); /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ - sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2); + clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */ - sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m); + clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8); /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ - sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n); + clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */ - sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div); + clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12); /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ - sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); + clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); } +static void dpll5_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr = ptr + clk_index; + + /* PER2 DPLL (DPLL5) */ + clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); + wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); + /* set M2 (usbtll_fck) */ + clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); + /* set m (11-bit multiplier) */ + clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); + /* set n (7-bit divider)*/ + clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); + /* lock mode */ + clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); + wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); +} + static void mpu_init_36xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; @@ -489,13 +555,13 @@ static void mpu_init_36xx(u32 sil_index, u32 clk_index) /* MPU DPLL (unlocked already */ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ - sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2); + clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2); /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ - sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m); + clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8); /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ - sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n); + clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n); } static void iva_init_36xx(u32 sil_index, u32 clk_index) @@ -508,20 +574,20 @@ static void iva_init_36xx(u32 sil_index, u32 clk_index) /* IVA DPLL */ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ - sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP); + clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP); wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ - sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2); + clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2); /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ - sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m); + clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8); /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ - sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n); + clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n); /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ - sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK); + clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK); wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); } @@ -545,16 +611,16 @@ void prcm_init(void) get_sys_clkin_sel(osc_clk, &sys_clkin_sel); /* set input crystal speed */ - sr32(&prm_base->clksel, 0, 3, sys_clkin_sel); + clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); /* If the input clock is greater than 19.2M always divide/2 */ if (sys_clkin_sel > 2) { /* input clock divider */ - sr32(&prm_base->clksrc_ctrl, 6, 2, 2); + clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6); clk_index = sys_clkin_sel / 2; } else { /* input clock divider */ - sr32(&prm_base->clksrc_ctrl, 6, 2, 1); + clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6); clk_index = sys_clkin_sel; } @@ -571,23 +637,26 @@ void prcm_init(void) * input divider to /1 as it should never set to /6.5 * in this case. */ - if (sys_clkin_sel != 1) /* 13 MHz */ + if (sys_clkin_sel != 1) { /* 13 MHz */ /* Bit 8: DPLL4_CLKINP_DIV */ - sr32(&prm_base->clksrc_ctrl, 8, 1, 0); + clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100); + } /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x00000007, PLL_LOW_POWER_BYPASS); wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY); dpll3_init_36xx(0, clk_index); dpll4_init_36xx(0, clk_index); - dpll5_init_34xx(0, clk_index); + dpll5_init_36xx(0, clk_index); iva_init_36xx(0, clk_index); mpu_init_36xx(0, clk_index); /* Lock MPU DPLL to set frequency */ - sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x00000007, PLL_LOCK); wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY); } else { @@ -604,7 +673,8 @@ void prcm_init(void) sil_index = 1; /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x00000007, PLL_LOW_POWER_BYPASS); wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY); @@ -617,14 +687,15 @@ void prcm_init(void) mpu_init_34xx(sil_index, clk_index); /* Lock MPU DPLL to set frequency */ - sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); + clrsetbits_le32(&prcm_base->clken_pll_mpu, + 0x00000007, PLL_LOCK); wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY); } /* Set up GPTimers to sys_clk source only */ - sr32(&prcm_base->clksel_per, 0, 8, 0xff); - sr32(&prcm_base->clksel_wkup, 0, 1, 1); + setbits_le32(&prcm_base->clksel_per, 0x000000FF); + setbits_le32(&prcm_base->clksel_wkup, 1); sdelay(5000); } @@ -637,16 +708,16 @@ void ehci_clocks_enable(void) struct prcm *prcm_base = (struct prcm *)PRCM_BASE; /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ - sr32(&prcm_base->iclken_usbhost, 0, 1, 1); + setbits_le32(&prcm_base->iclken_usbhost, 1); /* * Enable USBHOST_48M_FCLK (USBHOST_FCLK1) * and USBHOST_120M_FCLK (USBHOST_FCLK2) */ - sr32(&prcm_base->fclken_usbhost, 0, 2, 3); + setbits_le32(&prcm_base->fclken_usbhost, 0x00000003); /* Enable USBTTL_ICLK */ - sr32(&prcm_base->iclken3_core, 2, 1, 1); + setbits_le32(&prcm_base->iclken3_core, 0x00000004); /* Enable USBTTL_FCLK */ - sr32(&prcm_base->fclken3_core, 2, 1, 1); + setbits_le32(&prcm_base->fclken3_core, 0x00000004); } /****************************************************************************** @@ -657,65 +728,72 @@ void per_clocks_enable(void) struct prcm *prcm_base = (struct prcm *)PRCM_BASE; /* Enable GP2 timer. */ - sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */ + setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */ + setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */ + setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */ + + /* Enable GP9 timer. */ + setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */ + setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */ + setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */ #ifdef CONFIG_SYS_NS16550 /* Enable UART1 clocks */ - sr32(&prcm_base->fclken1_core, 13, 1, 0x1); - sr32(&prcm_base->iclken1_core, 13, 1, 0x1); + setbits_le32(&prcm_base->fclken1_core, 0x00002000); + setbits_le32(&prcm_base->iclken1_core, 0x00002000); + + /* Enable UART2 clocks */ + setbits_le32(&prcm_base->fclken1_core, 0x00004000); + setbits_le32(&prcm_base->iclken1_core, 0x00004000); /* UART 3 Clocks */ - sr32(&prcm_base->fclken_per, 11, 1, 0x1); - sr32(&prcm_base->iclken_per, 11, 1, 0x1); + setbits_le32(&prcm_base->fclken_per, 0x00000800); + setbits_le32(&prcm_base->iclken_per, 0x00000800); #endif #ifdef CONFIG_OMAP3_GPIO_2 - sr32(&prcm_base->fclken_per, 13, 1, 1); - sr32(&prcm_base->iclken_per, 13, 1, 1); + setbits_le32(&prcm_base->fclken_per, 0x00002000); + setbits_le32(&prcm_base->iclken_per, 0x00002000); #endif #ifdef CONFIG_OMAP3_GPIO_3 - sr32(&prcm_base->fclken_per, 14, 1, 1); - sr32(&prcm_base->iclken_per, 14, 1, 1); + setbits_le32(&prcm_base->fclken_per, 0x00004000); + setbits_le32(&prcm_base->iclken_per, 0x00004000); #endif #ifdef CONFIG_OMAP3_GPIO_4 - sr32(&prcm_base->fclken_per, 15, 1, 1); - sr32(&prcm_base->iclken_per, 15, 1, 1); + setbits_le32(&prcm_base->fclken_per, 0x00008000); + setbits_le32(&prcm_base->iclken_per, 0x00008000); #endif #ifdef CONFIG_OMAP3_GPIO_5 - sr32(&prcm_base->fclken_per, 16, 1, 1); - sr32(&prcm_base->iclken_per, 16, 1, 1); + setbits_le32(&prcm_base->fclken_per, 0x00010000); + setbits_le32(&prcm_base->iclken_per, 0x00010000); #endif #ifdef CONFIG_OMAP3_GPIO_6 - sr32(&prcm_base->fclken_per, 17, 1, 1); - sr32(&prcm_base->iclken_per, 17, 1, 1); + setbits_le32(&prcm_base->fclken_per, 0x00020000); + setbits_le32(&prcm_base->iclken_per, 0x00020000); #endif -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX /* Turn on all 3 I2C clocks */ - sr32(&prcm_base->fclken1_core, 15, 3, 0x7); - sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */ + setbits_le32(&prcm_base->fclken1_core, 0x00038000); + setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */ #endif /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - sr32(&prcm_base->iclken_wkup, 2, 1, 0x1); + setbits_le32(&prcm_base->iclken_wkup, 0x00000004); if (get_cpu_family() != CPU_AM35XX) - sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON); - - sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON); - sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON); - sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON); - sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON); - sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON); - sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON); - sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON); + out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON); + + out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON); + out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON); + out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON); + out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON); + out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON); + out_le32(&prcm_base->fclken_dss, FCK_DSS_ON); + out_le32(&prcm_base->iclken_dss, ICK_DSS_ON); if (get_cpu_family() != CPU_AM35XX) { - sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON); - sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON); + out_le32(&prcm_base->fclken_cam, FCK_CAM_ON); + out_le32(&prcm_base->iclken_cam, ICK_CAM_ON); } - sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON); - sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON); sdelay(1000); } diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk index 1d6a57c66c..ad44d63840 100644 --- a/arch/arm/cpu/armv7/omap3/config.mk +++ b/arch/arm/cpu/armv7/omap3/config.mk @@ -9,7 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/MLO +ALL-y += MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c index 6c7330a0ca..a2aadc9816 100644 --- a/arch/arm/cpu/armv7/omap3/emif4.c +++ b/arch/arm/cpu/armv7/omap3/emif4.c @@ -61,7 +61,7 @@ u32 get_sdr_cs_offset(u32 cs) * - Init the emif4 module for DDR access * - Early init routines, called from flash or SRAM. */ -void do_emif4_init(void) +static void do_emif4_init(void) { unsigned int regval; /* Set the DDR PHY parameters in PHY ctrl registers */ diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index bdf74ea3c3..78577b1d1c 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -17,9 +17,6 @@ #include #include -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - #ifdef CONFIG_SPL_BUILD ENTRY(save_boot_params) ldr r4, =omap3_boot_device @@ -69,15 +66,13 @@ ENDPROC(do_omap3_emu_romcode_call) *************************************************************************/ ENTRY(cpy_clk_code) /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ + adr r0, go_to_speed /* copy from start of go_to_speed... */ + adr r2, lowlevel_init /* ... up to start of low_level_init */ next2: ldmia r0!, {r3 - r10} /* copy from source address [r0] */ stmia r1!, {r3 - r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ - bne next2 + blo next2 mov pc, lr /* back to caller */ ENDPROC(cpy_clk_code) @@ -464,6 +459,19 @@ per_36x_dpll_param: .word 26000, 432, 12, 9, 16, 9, 4, 3, 1 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1 +per2_36x_dpll_param: +/* 12MHz */ +.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12 +/* 13MHz */ +.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13 +/* 19.2MHz */ +.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2 +/* 26MHz */ +.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26 +/* 38.4MHz */ +.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4 + + ENTRY(get_36x_mpu_dpll_param) adr r0, mpu_36x_dpll_param mov pc, lr @@ -483,3 +491,8 @@ ENTRY(get_36x_per_dpll_param) adr r0, per_36x_dpll_param mov pc, lr ENDPROC(get_36x_per_dpll_param) + +ENTRY(get_36x_per2_dpll_param) + adr r0, per2_36x_dpll_param + mov pc, lr +ENDPROC(get_36x_per2_dpll_param) diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c deleted file mode 100644 index 1832affa5b..0000000000 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * - * Author : - * Manikandan Pillai - * - * Initial Code from: - * Richard Woodruff - * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -struct gpmc *gpmc_cfg; - -#if defined(CONFIG_CMD_NAND) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -#endif /* CONFIG_CMD_NAND */ - -#if defined(CONFIG_CMD_ONENAND) -static const u32 gpmc_onenand[GPMC_MAX_REG] = { - ONENAND_GPMC_CONFIG1, - ONENAND_GPMC_CONFIG2, - ONENAND_GPMC_CONFIG3, - ONENAND_GPMC_CONFIG4, - ONENAND_GPMC_CONFIG5, - ONENAND_GPMC_CONFIG6, 0 -}; -#endif /* CONFIG_CMD_ONENAND */ - -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in guessing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(u32 cs) -{ - u32 val1, val2, addr; - u32 pattern = 0x12345678; - - addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); - - writel(0x0, addr + 0x400); /* clear pos A */ - writel(pattern, addr); /* pattern to pos B */ - writel(0x0, addr + 4); /* remove pattern off the bus */ - val1 = readl(addr + 0x400); /* get pos A value */ - val2 = readl(addr); /* get val2 */ - writel(0x0, addr + 0x400); /* clear pos A */ - - if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ - return 0; - else - return 1; -} - -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - - /* - * Enable the config. size is the CS size and goes in - * bits 11:8. We set bit 6 to enable this CS and the base - * address goes into bits 5:0. - */ - writel((size << 8) | (GPMC_CS_ENABLE << 6) | - ((base >> 24) & GPMC_BASEADDR_MASK), - &cs->config7); - sdelay(2000); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* putting a blanket check on GPMC based on ZeBu for now */ - gpmc_cfg = (struct gpmc *)GPMC_BASE; -#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND) - const u32 *gpmc_config = NULL; - u32 base = 0; - u32 size = 0; -#endif - u32 config = 0; - - /* global settings */ - writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ - writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ - - config = readl(&gpmc_cfg->config); - config &= (~0xf00); - writel(config, &gpmc_cfg->config); - - /* - * Disable the GPMC0 config set by ROM code - * It conflicts with our MPDB (both at 0x08000000) - */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - -#if defined(CONFIG_CMD_NAND) /* CS 0 */ - gpmc_config = gpmc_m_nand; - - base = PISMO1_NAND_BASE; - size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif - -#if defined(CONFIG_CMD_ONENAND) - gpmc_config = gpmc_onenand; - base = PISMO1_ONEN_BASE; - size = PISMO1_ONEN_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif -} diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 7a291318ab..4f15ac9cb5 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -135,6 +135,9 @@ void do_sdrc_init(u32 cs, u32 early) sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; + /* set some default timings */ + timings.sharing = SDRC_SHARING; + /* * When called in the early context this may be SPL and we will * need to set all of the timings. This ends up being board @@ -145,6 +148,7 @@ void do_sdrc_init(u32 cs, u32 early) * setup CS1. */ #ifdef CONFIG_SPL_BUILD + /* set/modify board-specific timings */ get_board_mem_timings(&timings); #endif if (early) { @@ -155,7 +159,7 @@ void do_sdrc_init(u32 cs, u32 early) writel(0, &sdrc_base->sysconfig); /* setup sdrc to ball mux */ - writel(SDRC_SHARING, &sdrc_base->sharing); + writel(timings.sharing, &sdrc_base->sharing); /* Disable Power Down of CKE because of 1 CKE on combo part */ writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 9a3303f708..bbb65bbe72 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -16,6 +16,8 @@ #include #include /* get mem tables */ #include +#include + #include #include @@ -40,12 +42,24 @@ static char *rev_s_37xx[CPU_37XX_MAX_REV] = { "1.2"}; #endif /* CONFIG_DISPLAY_CPUINFO */ +/***************************************************************** + * get_dieid(u32 *id) - read die ID + *****************************************************************/ +void get_dieid(u32 *id) +{ + struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; + + id[3] = readl(&id_base->die_id_0); + id[2] = readl(&id_base->die_id_1); + id[1] = readl(&id_base->die_id_2); + id[0] = readl(&id_base->die_id_3); +} + /***************************************************************** * dieid_num_r(void) - read and set die ID *****************************************************************/ void dieid_num_r(void) { - struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; char *uid_s, die_id[34]; u32 id[4]; @@ -54,10 +68,7 @@ void dieid_num_r(void) uid_s = getenv("dieid#"); if (uid_s == NULL) { - id[3] = readl(&id_base->die_id_0); - id[2] = readl(&id_base->die_id_1); - id[1] = readl(&id_base->die_id_2); - id[0] = readl(&id_base->die_id_3); + get_dieid(id); sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]); setenv("dieid#", die_id); uid_s = die_id; @@ -193,7 +204,7 @@ u32 __weak get_board_rev(void) /******************************************************** * get_base(); get upper addr of current execution *******************************************************/ -u32 get_base(void) +static u32 get_base(void) { u32 val; @@ -342,9 +353,9 @@ int print_cpuinfo (void) } if (CPU_OMAP36XX == get_cpu_family()) - printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", - cpu_family_s, cpu_s, sec_s, - rev_s_37xx[get_cpu_rev()], max_clk); + printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n", + cpu_family_s, cpu_s, sec_s, + rev_s_37xx[get_cpu_rev()], max_clk); else printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", cpu_family_s, cpu_s, sec_s, diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig new file mode 100644 index 0000000000..eccf897258 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/Kconfig @@ -0,0 +1,24 @@ +if OMAP44XX + +choice + prompt "OMAP4 board select" + +config TARGET_DUOVERO + bool "OMAP4430 Gumstix Duovero" + +config TARGET_OMAP4_PANDA + bool "TI OMAP4 PandaBoard" + +config TARGET_OMAP4_SDP4430 + bool "TI OMAP4 SDP4430" + +endchoice + +config SYS_SOC + default "omap4" + +source "board/gumstix/duovero/Kconfig" +source "board/ti/panda/Kconfig" +source "board/ti/sdp4430/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index fc6e2ddd0a..76a032a2d9 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -5,29 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS += sdram_elpida.o -COBJS += hwinit.o -COBJS += emif.o -COBJS += prcm-regs.o -COBJS += hw_data.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += sdram_elpida.o +obj-y += hwinit.o +obj-y += emif.o +obj-y += prcm-regs.o +obj-y += hw_data.o diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk index 1d6a57c66c..ad44d63840 100644 --- a/arch/arm/cpu/armv7/omap4/config.mk +++ b/arch/arm/cpu/armv7/omap4/config.mk @@ -9,7 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/MLO +ALL-y += MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 310df5a6e2..029533c851 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -50,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { /* * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency */ static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -76,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { }; /* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ @@ -170,6 +172,20 @@ struct dplls omap4430_dplls_es1 = { .ddr = NULL }; +struct dplls omap4430_dplls_es20 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct dplls omap4430_dplls = { .mpu = mpu_dpll_params_1200mhz, .core = core_dpll_params_1600mhz, @@ -198,6 +214,20 @@ struct dplls omap4460_dplls = { .ddr = NULL }; +struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct pmic_data twl6030_4430es1 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, .step = 12660, /* 12.66 mV represented in uV */ @@ -208,6 +238,7 @@ struct pmic_data twl6030_4430es1 = { .pmic_write = omap_vc_bypass_send_value, }; +/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ struct pmic_data twl6030 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, .step = 12660, /* 12.66 mV represented in uV */ @@ -271,6 +302,24 @@ struct vcores_data omap4460_volts = { .mm.pmic = &twl6030, }; +/* + * Take closest integer part of the mV value corresponding to a TWL6032 SMPS + * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. + */ +struct vcores_data omap4470_volts = { + .mpu.value = 1202, + .mpu.addr = SMPS_REG_ADDR_SMPS1, + .mpu.pmic = &twl6030, + + .core.value = 1126, + .core.addr = SMPS_REG_ADDR_SMPS2, + .core.pmic = &twl6030, + + .mm.value = 1139, + .mm.addr = SMPS_REG_ADDR_SMPS5, + .mm.pmic = &twl6030, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -364,91 +413,6 @@ void enable_basic_uboot_clocks(void) 1); } -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - (*prcm)->cm_l4per_mcbsp4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} - void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -463,6 +427,10 @@ void hw_data_init(void) break; case OMAP4430_ES2_0: + *dplls_data = &omap4430_dplls_es20; + *omap_vcores = &omap4430_volts; + break; + case OMAP4430_ES2_1: case OMAP4430_ES2_2: case OMAP4430_ES2_3: @@ -476,6 +444,11 @@ void hw_data_init(void) *omap_vcores = &omap4460_volts; break; + case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + default: printf("\n INVALID OMAP REVISION "); } diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 4da0fc0ad5..db16548fac 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include @@ -138,6 +138,9 @@ void init_omap_revision(void) break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: *omap_si_rev = OMAP4460_ES1_1; break; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index d76dde719a..4462c72c7a 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -32,7 +32,7 @@ #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { +const struct emif_regs emif_regs_elpida_200_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, .ref_ctrl = 0x0000030c, @@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { .emif_ddr_phy_ctlr_1 = 0x049ff808 }; -static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { +const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .sdram_config_init = 0x80000eb1, .sdram_config = 0x80001ab1, .ref_ctrl = 0x000005cd, @@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 }; +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, @@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_elpida_380_mhz_1cs; else if (omap4_rev == OMAP4430_ES2_0) *regs = &emif_regs_elpida_200_mhz_2cs; - else + else if (omap4_rev < OMAP4470_ES1_0) *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); @@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = { .manufacturer = LPDDR2_MANUFACTURER_ELPIDA }; +static const struct lpddr2_device_details elpida_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, struct lpddr2_device_details *lpddr2_dev_details) { u32 omap_rev = omap_revision(); /* EMIF1 & EMIF2 have identical configuration */ - if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) { - /* Nothing connected on CS1 for ES1.0 */ + if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) + && (cs == CS1)) { + /* Nothing connected on CS1 for 4430/4470 ES1.0 */ return NULL; - } else { - /* In all other cases Elpida 2G device */ + } else if (omap_rev < OMAP4470_ES1_0) { + /* In all other 4430/4460 cases Elpida 2G device */ *lpddr2_dev_details = elpida_2G_S4_details; - return lpddr2_dev_details; + } else { + /* 4470: 4G device */ + *lpddr2_dev_details = elpida_4G_S4_details; } + return lpddr2_dev_details; } struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, @@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr, /* Identical devices on EMIF1 & EMIF2 */ *cs0_device_timings = &elpida_2G_S4_timings; - if (omap_rev == OMAP4430_ES1_0) + if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) *cs1_device_timings = NULL; else *cs1_device_timings = &elpida_2G_S4_timings; @@ -290,3 +317,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) { *regs = &mr_regs; } + +__weak const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + return 0; +} diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig new file mode 100644 index 0000000000..aca862d2b2 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -0,0 +1,28 @@ +if OMAP54XX + +choice + prompt "OMAP5 board select" + +config TARGET_CM_T54 + bool "CompuLab CM-T54" + +config TARGET_OMAP5_UEVM + bool "TI OMAP5 uEVM board" + +config TARGET_DRA7XX_EVM + bool "TI DRA7XX" + +config TARGET_BEAGLE_X15 + bool "BeagleBoard X15" + +endchoice + +config SYS_SOC + default "omap5" + +source "board/compulab/cm_t54/Kconfig" +source "board/ti/omap5_uevm/Kconfig" +source "board/ti/dra7xx/Kconfig" +source "board/ti/beagle_x15/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index 168302dd3b..64c68791f1 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -5,30 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS += hwinit.o -COBJS += emif.o -COBJS += sdram.o -COBJS += prcm-regs.o -COBJS += hw_data.o -COBJS += abb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += hwinit.o +obj-y += emif.o +obj-y += sdram.o +obj-y += prcm-regs.o +obj-y += hw_data.o +obj-y += abb.o diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c index 31b679516f..3bf88979e5 100644 --- a/arch/arm/cpu/armv7/omap5/abb.c +++ b/arch/arm/cpu/armv7/omap5/abb.c @@ -28,18 +28,25 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) { u32 vset; + u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; + u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK; + if (!is_omap54xx()) { + /* DRA7 */ + fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK; + fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK; + } /* * ABB parameters must be properly fused * otherwise ABB should be disabled */ vset = readl(fuse); - if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK)) + if (!(vset & fuse_enable_mask)) return -1; /* prepare VSET value for LDOVBB mux register */ - vset &= OMAP5_ABB_FUSE_VSET_MASK; - vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1; + vset &= fuse_vset_mask; + vset >>= ffs(fuse_vset_mask) - 1; vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk index 2673af9668..ef2725affa 100644 --- a/arch/arm/cpu/armv7/omap5/config.mk +++ b/arch/arm/cpu/armv7/omap5/config.mk @@ -7,7 +7,7 @@ # ifdef CONFIG_SPL_BUILD -ALL-y += $(OBJTREE)/MLO +ALL-y += MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ea3554d97d..b9734fea8f 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -39,17 +39,6 @@ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */ -static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { - {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - /* OPP NOM FREQUENCY for ES1.0 */ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -83,6 +72,7 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ @@ -169,13 +159,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { }; static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ - {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ - {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ + {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ + {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ + {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { @@ -237,6 +227,16 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; +static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { + {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ @@ -247,6 +247,16 @@ static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; +static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { + {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ + {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -262,7 +272,7 @@ struct dplls omap5_dplls_es1 = { }; struct dplls omap5_dplls_es2 = { - .mpu = mpu_dpll_params_1100mhz, + .mpu = mpu_dpll_params_1ghz, .core = core_dpll_params_2128mhz_ddr532_es2, .per = per_dpll_params_768mhz_es2, .iva = iva_dpll_params_2330mhz, @@ -283,6 +293,18 @@ struct dplls dra7xx_dplls = { .iva = iva_dpll_params_2330mhz_dra7xx, .usb = usb_dpll_params_1920mhz, .ddr = ddr_dpll_params_2128mhz, + .gmac = gmac_dpll_params_2000mhz, +}; + +struct dplls dra72x_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_dra7xx, + .per = per_dpll_params_768mhz_dra7xx, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_2664mhz, + .gmac = gmac_dpll_params_2000mhz, }; struct pmic_data palmas = { @@ -298,6 +320,7 @@ struct pmic_data palmas = { .pmic_write = omap_vc_bypass_send_value, }; +/* The TPS659038 and TPS65917 are software-compatible, use common struct */ struct pmic_data tps659038 = { .base_offset = PALMAS_SMPS_BASE_VOLT_UV, .step = 10000, /* 10 mV represented in uV */ @@ -343,31 +366,67 @@ struct vcores_data dra752_volts = { .mpu.value = VDD_MPU_DRA752, .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, .eve.value = VDD_EVE_DRA752, .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, + .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, .gpu.value = VDD_GPU_DRA752, .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, .gpu.pmic = &tps659038, .core.value = VDD_CORE_DRA752, .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, + .core.addr = TPS659038_REG_ADDR_SMPS7, .core.pmic = &tps659038, .iva.value = VDD_IVA_DRA752, .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, + .iva.addr = TPS659038_REG_ADDR_SMPS8, + .iva.pmic = &tps659038, +}; + +struct vcores_data dra722_volts = { + .mpu.value = VDD_MPU_DRA72x, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS65917_REG_ADDR_SMPS1, + .mpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA72x, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS65917_REG_ADDR_SMPS2, + .core.pmic = &tps659038, + + /* + * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x + * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. + */ + .gpu.value = VDD_GPU_DRA72x, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS65917_REG_ADDR_SMPS3, + .gpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA72x, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS65917_REG_ADDR_SMPS3, + .eve.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA72x, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS65917_REG_ADDR_SMPS3, .iva.pmic = &tps659038, }; @@ -382,6 +441,9 @@ void enable_basic_clocks(void) (*prcm)->cm_l3init_clkstctrl, (*prcm)->cm_memif_clkstctrl, (*prcm)->cm_l4cfg_clkstctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_clkstctrl, +#endif 0 }; @@ -409,6 +471,13 @@ void enable_basic_clocks(void) (*prcm)->cm_wkup_wdtimer2_clkctrl, (*prcm)->cm_l4per_uart3_clkctrl, (*prcm)->cm_l4per_i2c1_clkctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_gmac_clkctrl, +#endif + +#ifdef CONFIG_TI_QSPI + (*prcm)->cm_l4per_qspi_clkctrl, +#endif 0 }; @@ -437,6 +506,10 @@ void enable_basic_clocks(void) clk_modules_explicit_en_essential, 1); +#ifdef CONFIG_TI_QSPI + setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); +#endif + /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); @@ -465,101 +538,12 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l3init_fsusb_clkctrl, 0 }; - do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, 1); } -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_mpu_m3_mpu_m3_clkctrl, - (*prcm)->cm_ivahd_ivahd_clkctrl, - (*prcm)->cm_ivahd_sl2_clkctrl, - (*prcm)->cm_dsp_dsp_clkctrl, - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} - const struct ctrl_ioregs ioregs_omap5430 = { .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, @@ -576,6 +560,7 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = { .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, }; const struct ctrl_ioregs ioregs_omap5432_es2 = { @@ -586,20 +571,34 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = { .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, }; const struct ctrl_ioregs ioregs_dra7xx_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x80808080, - .ctrl_ddrio_0 = 0xbae8c631, - .ctrl_ddrio_1 = 0xb46318d8, + .ctrl_ddrio_0 = 0xA2084210, + .ctrl_ddrio_1 = 0x84210840, + .ctrl_ddrio_2 = 0x84210000, + .ctrl_emif_sdram_config_ext = 0x0001C1A7, + .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_ddr_ctrl_ext_0 = 0xA2000000, +}; + +const struct ctrl_ioregs ioregs_dra72x_es1 = { + .ctrl_ddrch = 0x40404040, + .ctrl_lpddr2ch = 0x40404040, + .ctrl_ddr3ch = 0x60606080, + .ctrl_ddrio_0 = 0xA2084210, + .ctrl_ddrio_1 = 0x84210840, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0xb2c00000, + .ctrl_emif_sdram_config_ext = 0x0001C1A7, + .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, }; -void hw_data_init(void) +void __weak hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -622,12 +621,20 @@ void hw_data_init(void) break; case DRA752_ES1_0: + case DRA752_ES1_1: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; *omap_vcores = &dra752_volts; *ctrl = &dra7xx_ctrl; break; + case DRA722_ES1_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra72x_dplls; + *omap_vcores = &dra722_volts; + *ctrl = &dra7xx_ctrl; + break; + default: printf("\n INVALID OMAP REVISION "); } @@ -649,8 +656,12 @@ void get_ioregs(const struct ctrl_ioregs **regs) *regs = &ioregs_omap5432_es2; break; case DRA752_ES1_0: + case DRA752_ES1_1: *regs = &ioregs_dra7xx_es1; break; + case DRA722_ES1_0: + *regs = &ioregs_dra72x_es1; + break; default: printf("\n INVALID OMAP REVISION "); diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 1065891ae1..a8a474a88b 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include @@ -168,12 +168,6 @@ void do_io_settings(void) io_settings_lpddr2(); else io_settings_ddr3(); - - /* Efuse settings */ - writel(EFUSE_1, (*ctrl)->control_efuse_1); - writel(EFUSE_2, (*ctrl)->control_efuse_2); - writel(EFUSE_3, (*ctrl)->control_efuse_3); - writel(EFUSE_4, (*ctrl)->control_efuse_4); } static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { @@ -297,13 +291,17 @@ void srcomp_enable(void) void config_data_eye_leveling_samples(u32 emif_base) { + const struct ctrl_ioregs *ioregs; + + get_ioregs(&ioregs); + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ if (emif_base == EMIF1_BASE) - writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - (*ctrl)->control_emif1_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif1_sdram_config_ext); else if (emif_base == EMIF2_BASE) - writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - (*ctrl)->control_emif2_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif2_sdram_config_ext); } void init_omap_revision(void) @@ -335,6 +333,12 @@ void init_omap_revision(void) case DRA752_CONTROL_ID_CODE_ES1_0: *omap_si_rev = DRA752_ES1_0; break; + case DRA752_CONTROL_ID_CODE_ES1_1: + *omap_si_rev = DRA752_ES1_1; + break; + case DRA722_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA722_ES1_0; + break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 54d8c2b689..0745d424e2 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = { .cm_l3init_hsusbotg_clkctrl = 0x4a009360, .cm_l3init_hsusbtll_clkctrl = 0x4a009368, .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_sata_clkctrl = 0x4a009388, .cm_l3init_fsusb_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009400, @@ -286,12 +288,6 @@ struct prcm_regs const omap5_es1_prcm = { .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, - .prm_sldo_core_setup = 0x4ae07bc4, - .prm_sldo_core_ctrl = 0x4ae07bc8, - .prm_sldo_mpu_setup = 0x4ae07bcc, - .prm_sldo_mpu_ctrl = 0x4ae07bd0, - .prm_sldo_mm_setup = 0x4ae07bd4, - .prm_sldo_mm_ctrl = 0x4ae07bd8, /* SCRM stuff, used by some boards */ .scrm_auxclk0 = 0x4ae0a310, @@ -301,6 +297,8 @@ struct prcm_regs const omap5_es1_prcm = { struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, + .control_phy_power_usb = 0x4A002370, + .control_phy_power_sata = 0x4A002374, .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, @@ -378,6 +376,12 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_phy_power_usb = 0x4A002370, + .control_phy_power_sata = 0x4A002374, + .control_core_mac_id_0_lo = 0x4A002514, + .control_core_mac_id_0_hi = 0x4A002518, + .control_core_mac_id_1_lo = 0x4A00251C, + .control_core_mac_id_1_hi = 0x4A002520, .control_core_mmr_lock1 = 0x4A002540, .control_core_mmr_lock2 = 0x4A002544, .control_core_mmr_lock3 = 0x4A002548, @@ -429,11 +433,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_code_latch = 0x4A002E84, .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, + .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, .control_port_emif2_sdram_config = 0x4AE0C118, .control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158, .control_padconf_mode = 0x4AE0C5A0, .control_xtal_oscillator = 0x4AE0C5A4, .control_i2c_2 = 0x4AE0C5A8, @@ -442,10 +448,10 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_wkup_control_spare_r = 0x4AE0C5B4, .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, .control_srcomp_east_side_wkup = 0x4AE0C5BC, - .control_efuse_1 = 0x4AE0C5C0, - .control_efuse_2 = 0x4AE0C5C4, - .control_efuse_3 = 0x4AE0C5C8, - .control_efuse_4 = 0x4AE0C5CC, + .control_efuse_1 = 0x4AE0C5C8, + .control_efuse_2 = 0x4AE0C5CC, + .control_efuse_3 = 0x4AE0C5D0, + .control_efuse_4 = 0x4AE0C5D4, .control_efuse_13 = 0x4AE0C5F0, }; @@ -528,8 +534,6 @@ struct prcm_regs const omap5_es2_prcm = { .cm1_abe_timer8_clkctrl = 0x4a004580, .cm1_abe_wdt3_clkctrl = 0x4a004588, - - /* cm2.ckgen */ .cm_clksel_mpu_m3_iss_root = 0x4a008100, .cm_clksel_usb_60mhz = 0x4a008104, @@ -571,6 +575,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_div_m2_dpll_unipro = 0x4a0081d0, .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640, .cm_coreaon_bandgap_clkctrl = 0x4a008648, .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, @@ -700,8 +705,11 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_hsusbotg_clkctrl = 0x4a009660, .cm_l3init_hsusbtll_clkctrl = 0x4a009668, .cm_l3init_p1500_clkctrl = 0x4a009678, + .cm_l3init_sata_clkctrl = 0x4a009688, .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, + .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0, /* prm irqstatus regs */ .prm_irqstatus_mpu_2 = 0x4ae06014, @@ -731,12 +739,6 @@ struct prcm_regs const omap5_es2_prcm = { .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, - .prm_sldo_core_setup = 0x4ae07cc4, - .prm_sldo_core_ctrl = 0x4ae07cc8, - .prm_sldo_mpu_setup = 0x4ae07ccc, - .prm_sldo_mpu_ctrl = 0x4ae07cd0, - .prm_sldo_mm_setup = 0x4ae07cd4, - .prm_sldo_mm_ctrl = 0x4ae07cd8, .prm_abbldo_mpu_setup = 0x4ae07cdc, .prm_abbldo_mpu_ctrl = 0x4ae07ce0, @@ -798,6 +800,9 @@ struct prcm_regs const dra7xx_prcm = { .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, + .cm_clkmode_dpll_gmac = 0x4a0052a8, + .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640, + .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, /* cm1.mpu */ .cm_mpu_mpu_clkctrl = 0x4a005320, @@ -806,6 +811,9 @@ struct prcm_regs const dra7xx_prcm = { .cm_dsp_clkstctrl = 0x4a005400, .cm_dsp_dsp_clkctrl = 0x4a005420, + /* prm irqstatus regs */ + .prm_irqstatus_mpu_2 = 0x4ae06014, + /* cm2.ckgen */ .cm_clksel_usb_60mhz = 0x4a008104, .cm_clkmode_dpll_per = 0x4a008140, @@ -895,7 +903,12 @@ struct prcm_regs const dra7xx_prcm = { .cm_l3init_hsusbhost_clkctrl = 0x4a009340, .cm_l3init_hsusbotg_clkctrl = 0x4a009348, .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_l3init_sata_clkctrl = 0x4a009388, + .cm_gmac_clkstctrl = 0x4a0093c0, + .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, + .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009700, @@ -926,6 +939,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_l4per_gpio8_clkctrl = 0x4a009818, .cm_l4per_mmcsd3_clkctrl = 0x4a009820, .cm_l4per_mmcsd4_clkctrl = 0x4a009828, + .cm_l4per_qspi_clkctrl = 0x4a009838, .cm_l4per_uart1_clkctrl = 0x4a009840, .cm_l4per_uart2_clkctrl = 0x4a009848, .cm_l4per_uart3_clkctrl = 0x4a009850, @@ -961,4 +975,7 @@ struct prcm_regs const dra7xx_prcm = { .prm_vc_val_bypass = 0x4ae07da0, .prm_vc_cfg_i2c_mode = 0x4ae07db4, .prm_vc_cfg_i2c_clk = 0x4ae07db8, + + .prm_abbldo_mpu_setup = 0x4AE07DDC, + .prm_abbldo_mpu_ctrl = 0x4AE07DE0, }; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index e65c1160e2..7d8cec08c2 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -145,18 +145,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, + .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E20400A, + .emif_ddr_phy_ctlr_1_init = 0x0E24400A, .emif_ddr_phy_ctlr_1 = 0x0E24400A, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_3 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_4 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB, + .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB, + .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB, + .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -169,18 +169,42 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, + .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0020400A, + .emif_ddr_phy_ctlr_1_init = 0x0E24400A, .emif_ddr_phy_ctlr_1 = 0x0E24400A, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_3 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_4 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_5 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB, + .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB, + .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB, + .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61851AB2, + .sdram_config = 0x61851AB2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400A, + .emif_ddr_phy_ctlr_1 = 0x0024400A, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, + .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, + .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -229,6 +253,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { .is_ma_present = 0x1 }; +/* + * DRA722 EVM EMIF1 CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { switch (omap_revision()) { @@ -245,6 +280,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_ddr3_532_mhz_1cs_es2; break; case DRA752_ES1_0: + case DRA752_ES1_1: switch (emif_nr) { case 1: *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; @@ -254,6 +290,9 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) break; } break; + case DRA722_ES1_0: + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; + break; default: *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } @@ -273,8 +312,12 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; break; case DRA752_ES1_0: - default: + case DRA752_ES1_1: *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; + break; + case DRA722_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_2G_x_2; } } @@ -306,7 +349,7 @@ void emif_get_device_details(u32 emif_nr, #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ -const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ext_phy_ctrl_const_base[] = { 0x01004010, 0x00001004, 0x04010040, @@ -329,7 +372,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x0 }; -const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ddr3_ext_phy_ctrl_const_base_es1[] = { 0x01004010, 0x00001004, 0x04010040, @@ -352,7 +395,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x0 }; -const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { 0x50D4350D, 0x00000D43, 0x04010040, @@ -376,51 +419,90 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { }; const u32 -dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = { - 0x009E009E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, +dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { + 0x00BB00BB, + 0x00440044, + 0x00440044, + 0x00440044, + 0x00440044, + 0x00440044, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + 0x0, 0x0, - 0x600020, + 0x0, + 0x0, + 0x0 +}; + +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { + 0x00BB00BB, + 0x00440044, + 0x00440044, + 0x00440044, + 0x00440044, + 0x00440044, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00000000, + 0x00600020, 0x40010080, - 0x8102040 + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; const u32 -dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = { - 0x009D009D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, +dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { + 0x00A400A4, + 0x00390039, + 0x00320032, + 0x00320032, + 0x00320032, + 0x00440044, + 0x00550055, + 0x00550055, + 0x00550055, + 0x00550055, + 0x007F007F, + 0x004D004D, + 0x00430043, + 0x00560056, + 0x00540054, + 0x00600060, 0x0, - 0x600020, + 0x00600020, 0x40010080, - 0x8102040 + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; const struct lpddr2_mr_regs mr_regs = { @@ -431,27 +513,43 @@ const struct lpddr2_mr_regs mr_regs = { .mr16 = MR16_REF_FULL_ARRAY }; -static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs) +void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, + const u32 **regs, + u32 *size) { switch (omap_revision()) { case OMAP5430_ES1_0: case OMAP5430_ES2_0: *regs = ext_phy_ctrl_const_base; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base); break; case OMAP5432_ES1_0: *regs = ddr3_ext_phy_ctrl_const_base_es1; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1); break; case OMAP5432_ES2_0: *regs = ddr3_ext_phy_ctrl_const_base_es2; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); break; case DRA752_ES1_0: - if (emif_nr == 1) + case DRA752_ES1_1: + if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; - else + *size = + ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1); + } else { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; + *size = + ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2); + } + break; + case DRA722_ES1_0: + *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; + *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); break; default: *regs = ddr3_ext_phy_ctrl_const_base_es2; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); } } @@ -468,6 +566,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) u32 emif_nr; const u32 *ext_phy_ctrl_const_regs; u32 i = 0; + u32 size; emif_nr = (base == EMIF1_BASE) ? 1 : 2; @@ -487,8 +586,10 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) * external phy 6-24 registers do not change with * ddr frequency */ - emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs); - for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + emif_get_ext_phy_ctrl_const_regs(emif_nr, + &ext_phy_ctrl_const_regs, &size); + + for (i = 0; i < size; i++) { writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); /* Update shadow registers */ @@ -545,6 +646,76 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = { .min_tck = &min_tck, }; +/* + * List of status registers to be controlled back to control registers + * after initial leveling + * readreg, writereg + */ +const struct read_write_regs omap5_bug_00339_regs[] = { + { 8, 5 }, + { 9, 6 }, + { 10, 7 }, + { 14, 8 }, + { 15, 9 }, + { 16, 10 }, + { 11, 2 }, + { 12, 3 }, + { 13, 4 }, + { 17, 11 }, + { 18, 12 }, + { 19, 13 }, +}; + +const struct read_write_regs dra_bug_00339_regs[] = { + { 7, 7 }, + { 8, 8 }, + { 9, 9 }, + { 10, 10 }, + { 11, 11 }, + { 12, 2 }, + { 13, 3 }, + { 14, 4 }, + { 15, 5 }, + { 16, 6 }, + { 17, 12 }, + { 18, 13 }, + { 19, 14 }, + { 20, 15 }, + { 21, 16 }, + { 22, 17 }, + { 23, 18 }, + { 24, 19 }, + { 25, 20 }, + { 26, 21} +}; + +const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + const struct read_write_regs *bug_00339_regs_ptr = NULL; + + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + bug_00339_regs_ptr = omap5_bug_00339_regs; + *iterations = sizeof(omap5_bug_00339_regs)/ + sizeof(omap5_bug_00339_regs[0]); + break; + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA722_ES1_0: + bug_00339_regs_ptr = dra_bug_00339_regs; + *iterations = sizeof(dra_bug_00339_regs)/ + sizeof(dra_bug_00339_regs[0]); + break; + default: + printf("\n Error: UnKnown SOC"); + } + + return bug_00339_regs_ptr; +} + void emif_get_device_timings_sdp(u32 emif_nr, const struct lpddr2_device_timings **cs0_device_timings, const struct lpddr2_device_timings **cs1_device_timings) diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S new file mode 100644 index 0000000000..bf11a34e54 --- /dev/null +++ b/arch/arm/cpu/armv7/psci.S @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2013,2014 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + .globl _psci_vectors +_psci_vectors: + b default_psci_vector @ reset + b default_psci_vector @ undef + b _smc_psci @ smc + b default_psci_vector @ pabort + b default_psci_vector @ dabort + b default_psci_vector @ hyp + b default_psci_vector @ irq + b psci_fiq_enter @ fiq + +ENTRY(psci_fiq_enter) + movs pc, lr +ENDPROC(psci_fiq_enter) +.weak psci_fiq_enter + +ENTRY(default_psci_vector) + movs pc, lr +ENDPROC(default_psci_vector) +.weak default_psci_vector + +ENTRY(psci_cpu_suspend) +ENTRY(psci_cpu_off) +ENTRY(psci_cpu_on) +ENTRY(psci_migrate) + mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) + mov pc, lr +ENDPROC(psci_migrate) +ENDPROC(psci_cpu_on) +ENDPROC(psci_cpu_off) +ENDPROC(psci_cpu_suspend) +.weak psci_cpu_suspend +.weak psci_cpu_off +.weak psci_cpu_on +.weak psci_migrate + +_psci_table: + .word ARM_PSCI_FN_CPU_SUSPEND + .word psci_cpu_suspend + .word ARM_PSCI_FN_CPU_OFF + .word psci_cpu_off + .word ARM_PSCI_FN_CPU_ON + .word psci_cpu_on + .word ARM_PSCI_FN_MIGRATE + .word psci_migrate + .word 0 + .word 0 + +_smc_psci: + push {r4-r7,lr} + + @ Switch to secure + mrc p15, 0, r7, c1, c1, 0 + bic r4, r7, #1 + mcr p15, 0, r4, c1, c1, 0 + isb + + adr r4, _psci_table +1: ldr r5, [r4] @ Load PSCI function ID + ldr r6, [r4, #4] @ Load target PC + cmp r5, #0 @ If reach the end, bail out + moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid) + beq 2f + cmp r0, r5 @ If not matching, try next entry + addne r4, r4, #8 + bne 1b + + blx r6 @ Execute PSCI function + + @ Switch back to non-secure +2: mcr p15, 0, r7, c1, c1, 0 + + pop {r4-r7, lr} + movs pc, lr @ Return to the kernel + + .popsection diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig new file mode 100644 index 0000000000..6d94199de8 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -0,0 +1,41 @@ +if RMOBILE + +choice + prompt "Renesus ARM SoCs board select" + +config TARGET_ARMADILLO_800EVA + bool "armadillo 800 eva board" + +config TARGET_GOSE + bool "Gose board" + +config TARGET_KOELSCH + bool "Koelsch board" + +config TARGET_LAGER + bool "Lager board" + +config TARGET_KZM9G + bool "KZM9D board" + +config TARGET_ALT + bool "Alt board" + +endchoice + +config SYS_SOC + default "rmobile" + +config RMOBILE_EXTRAM_BOOT + bool "Enable boot from RAM" + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER + default n + +source "board/atmark-techno/armadillo-800eva/Kconfig" +source "board/renesas/gose/Kconfig" +source "board/renesas/koelsch/Kconfig" +source "board/renesas/lager/Kconfig" +source "board/kmc/kzm9g/Kconfig" +source "board/renesas/alt/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index 3168e979f2..647e426d0b 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -5,45 +5,15 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS = lowlevel_init.o -COBJS-y += cpu_info.o -COBJS-y += emac.o - -COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o -COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o -COBJS-$(CONFIG_R8A7740) += cpu_info-r8a7740.o -COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o -COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o -COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o -COBJS_LN-$(CONFIG_TMU_TIMER) += sh_timer.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -# from arch/sh/lib/ directory -$(obj)sh_timer.c: - @rm -f $(obj)sh_timer.c - ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### - +obj-y = cpu_info.o +obj-y += emac.o + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o +obj-$(CONFIG_GLOBAL_TIMER) += timer.o +obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o +obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o +obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o +obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o +obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o +obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o +obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk deleted file mode 100644 index 4f01610868..0000000000 --- a/arch/arm/cpu/armv7/rmobile/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -# Make ARMv5 to allow more compilers to work, even though its v7a. -PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c new file mode 100644 index 0000000000..42ee30fbe7 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c @@ -0,0 +1,26 @@ +/* + * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include +#include + +#define PRR 0xFF000044 + +u32 rmobile_get_cpu_type(void) +{ + return (readl(PRR) & 0x00007F00) >> 8; +} + +u32 rmobile_get_cpu_rev_integer(void) +{ + return ((readl(PRR) & 0x000000F0) >> 4) + 1; +} + +u32 rmobile_get_cpu_rev_fraction(void) +{ + return readl(PRR) & 0x0000000F; +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index 07a33fb2ae..d47c47c07e 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -44,25 +44,32 @@ static u32 __rmobile_get_cpu_rev_fraction(void) u32 rmobile_get_cpu_rev_fraction(void) __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction"))); +/* CPU infomation table */ +static const struct { + u16 cpu_type; + u8 cpu_name[10]; +} rmobile_cpuinfo[] = { + { 0x37, "SH73A0" }, + { 0x40, "R8A7740" }, + { 0x45, "R8A7790" }, + { 0x47, "R8A7791" }, + { 0x4B, "R8A7793" }, + { 0x4C, "R8A7794" }, + { 0x0, "CPU" }, +}; + int print_cpuinfo(void) { - switch (rmobile_get_cpu_type()) { - case 0x37: - printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; - case 0x40: - printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; - - default: - printf("CPU: Renesas Electronics CPU rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; + int i = 0; + u32 cpu_type = rmobile_get_cpu_type(); + for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) { + if (rmobile_cpuinfo[i].cpu_type == cpu_type) { + printf("CPU: Renesas Electronics %s rev %d.%d\n", + rmobile_cpuinfo[i].cpu_name, + rmobile_get_cpu_rev_integer(), + rmobile_get_cpu_rev_fraction()); + break; + } } return 0; } diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S index ff18d9694c..0d654403ee 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S @@ -2,7 +2,7 @@ * Copyright (C) 2012 Nobuhiro Iwamatsu * Copyright (C) 2012 Renesas Solutions Corp. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S new file mode 100644 index 0000000000..d47546a11d --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -0,0 +1,79 @@ +/* + * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S + * This file is lager low level initialize. + * + * Copyright (C) 2013, 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +ENTRY(lowlevel_init) + mrc p15, 0, r4, c0, c0, 5 /* mpidr */ + orr r4, r4, r4, lsr #6 + and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ + + b do_lowlevel_init + + .pool + +/* + * CPU ID #1-#3 come here + */ + .align 4 +do_cpu_waiting: + ldr r1, =0xe6180000 /* sysc */ +1: ldr r0, [r1, #0x20] /* sbar */ + tst r0, r0 + beq 1b + bx r0 + +/* + * Only CPU ID #0 comes here + */ + .align 4 +do_lowlevel_init: + ldr r2, =0xFF000044 /* PRR */ + ldr r1, [r2] + and r1, r1, #0x7F00 + lsrs r1, r1, #8 + cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ + beq _exit_init_l2_a15 + + /* surpress wfe if ca15 */ + tst r4, #4 + mrceq p15, 0, r0, c1, c0, 1 /* actlr */ + orreq r0, r0, #(1<<7) + mcreq p15, 0, r0, c1, c0, 1 + + /* and set l2 latency */ + mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */ + and r0, r0, #0xf00 + lsr r0, r0, #8 + tst r0, #1 /* only need for cluster 0 */ + bne _exit_init_l2_a15 + + mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */ + and r1, r0, #7 + cmp r1, #3 /* has already been set up */ + bicne r0, r0, #0xe7 + orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ +#if defined(CONFIG_R8A7790) + orrne r0, r0, #0x20 /* L2CTLR[5] */ +#endif + mcrne p15, 1, r0, c9, c0, 2 +_exit_init_l2_a15: + ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) + sub sp, r3, #4 + str lr, [sp] + + /* initialize system */ + bl s_init + + ldr lr, [sp] + mov pc, lr + nop +ENDPROC(lowlevel_init) + .ltorg diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c new file mode 100644 index 0000000000..1259062a64 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c @@ -0,0 +1,829 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c + * This file is r8a7790 processor support - PFC hardware block. + * + * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Magnus Damm + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Kuninori Morimoto + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include "pfc-r8a7790.h" + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, + FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, + FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, + FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, + FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, + FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, + FN_IP3_14_12, FN_IP3_17_15, + + /* GPSR1 */ + FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, + FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, + FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, + FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, + FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, + FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, + + /* GPSR2 */ + FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, + FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, + FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, + FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, + FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, + FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, + FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, + + /* GPSR3 */ + FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, + FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, + FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, + FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, + FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, + FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, + FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, + + /* GPSR4 */ + FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, + FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, + FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, + FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, + FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, + FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, + FN_IP14_15_12, FN_IP14_18_16, + + /* GPSR5 */ + FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, + FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, + FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, + FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, + FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, + FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, + FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, + + /* IPSR0 - IPSR5 */ + /* IPSR6 */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, + FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, + FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, + FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, + FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, + FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, + FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, + FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, + + /* IPSR7 */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, + FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, + FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, + FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, + FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, + FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, + FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, + FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, + FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, + FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, + FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + + /* IPSR8 - IPSR16 */ + + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFB1_4, + FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, + FN_SEL_VI3_0, FN_SEL_VI3_1, + FN_SEL_VI2_0, FN_SEL_VI2_1, + FN_SEL_VI1_0, FN_SEL_VI1_1, + FN_SEL_VI0_0, FN_SEL_VI0_1, + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, + FN_SEL_LBS_0, FN_SEL_LBS_1, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, + + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, + FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, + FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, + DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, + SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, + INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, + ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, + TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, + SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, + STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, + SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, + STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, + SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, + RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, + TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, + RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, + STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, + ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, + STP_IVCXO27_1_B_MARK, HRX0_F_MARK, + + ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, + SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, + RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, + ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, + HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, + SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, + STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, + ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, + TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, + SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, + GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, + STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, + PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, + PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, + AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, + ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, + VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, + MII_RXD2_MARK, + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_IPSR_DATA(IP6_2_0, DACK0), + PINMUX_IPSR_DATA(IP6_2_0, IRQ0), + PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP6_8_6, DACK1), + PINMUX_IPSR_DATA(IP6_8_6, IRQ1), + PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_13_11, DACK2), + PINMUX_IPSR_DATA(IP6_13_11, IRQ2), + PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), + PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), + PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), + PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), + PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), + PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), + + PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), + PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), + PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), + PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), + PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), + PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), + PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), + PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_18_16, PWM0), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), + PINMUX_IPSR_DATA(IP7_24_22, PWM2), + PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), + PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), + PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), + PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), + PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), + +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + /*IPSR0 - IPSR5*/ + /*IPSR6*/ + GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N), + GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B), + GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB), + GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B), + GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B), + GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B), + GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2), + GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B), + GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV), + GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D), + GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E), + GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B), + GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E), + GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0), + GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C), + GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1), + GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B), + GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G), + GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E), + GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E), + GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E), + GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F), + + /*IPSR7*/ + GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E), + GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1), + GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G), + GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN), + GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC), + GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0), + GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C), + GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC), + GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C), + GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B), + GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1), + GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C), + GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0), + GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C), + GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C), + GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1), + GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N), + GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2), + /*IPSR8 - IPSR16*/ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP3_17_15, + GP_0_30_FN, FN_IP3_14_12, + GP_0_29_FN, FN_IP3_11_8, + GP_0_28_FN, FN_IP3_7_4, + GP_0_27_FN, FN_IP3_3_0, + GP_0_26_FN, FN_IP2_28_26, + GP_0_25_FN, FN_IP2_25_22, + GP_0_24_FN, FN_IP2_21_18, + GP_0_23_FN, FN_IP2_17_15, + GP_0_22_FN, FN_IP2_14_12, + GP_0_21_FN, FN_IP2_11_9, + GP_0_20_FN, FN_IP2_8_6, + GP_0_19_FN, FN_IP2_5_3, + GP_0_18_FN, FN_IP2_2_0, + GP_0_17_FN, FN_IP1_29_28, + GP_0_16_FN, FN_IP1_27_26, + GP_0_15_FN, FN_IP1_25_22, + GP_0_14_FN, FN_IP1_21_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_12, + GP_0_11_FN, FN_IP1_11_8, + GP_0_10_FN, FN_IP1_7_4, + GP_0_9_FN, FN_IP1_3_0, + GP_0_8_FN, FN_IP0_30_27, + GP_0_7_FN, FN_IP0_26_23, + GP_0_6_FN, FN_IP0_22_20, + GP_0_5_FN, FN_IP0_19_16, + GP_0_4_FN, FN_IP0_15_12, + GP_0_3_FN, FN_IP0_11_9, + GP_0_2_FN, FN_IP0_8_6, + GP_0_1_FN, FN_IP0_5_3, + GP_0_0_FN, FN_IP0_2_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_FN, FN_IP6_13_11, + GP_1_28_FN, FN_IP6_10_9, + GP_1_27_FN, FN_IP6_8_6, + GP_1_26_FN, FN_IP6_5_3, + GP_1_25_FN, FN_IP6_2_0, + GP_1_24_FN, FN_IP5_29_27, + GP_1_23_FN, FN_IP5_26_24, + GP_1_22_FN, FN_IP5_23_21, + GP_1_21_FN, FN_IP5_20_18, + GP_1_20_FN, FN_IP5_17_15, + GP_1_19_FN, FN_IP5_14_13, + GP_1_18_FN, FN_IP5_12_10, + GP_1_17_FN, FN_IP5_9_6, + GP_1_16_FN, FN_IP5_5_3, + GP_1_15_FN, FN_IP5_2_0, + GP_1_14_FN, FN_IP4_29_27, + GP_1_13_FN, FN_IP4_26_24, + GP_1_12_FN, FN_IP4_23_21, + GP_1_11_FN, FN_IP4_20_18, + GP_1_10_FN, FN_IP4_17_15, + GP_1_9_FN, FN_IP4_14_12, + GP_1_8_FN, FN_IP4_11_9, + GP_1_7_FN, FN_IP4_8_6, + GP_1_6_FN, FN_IP4_5_3, + GP_1_5_FN, FN_IP4_2_0, + GP_1_4_FN, FN_IP3_31_29, + GP_1_3_FN, FN_IP3_28_26, + GP_1_2_FN, FN_IP3_25_23, + GP_1_1_FN, FN_IP3_22_20, + GP_1_0_FN, FN_IP3_19_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_FN, FN_IP7_15_13, + GP_2_28_FN, FN_IP7_12_10, + GP_2_27_FN, FN_IP7_9_8, + GP_2_26_FN, FN_IP7_7_6, + GP_2_25_FN, FN_IP7_5_3, + GP_2_24_FN, FN_IP7_2_0, + GP_2_23_FN, FN_IP6_31_29, + GP_2_22_FN, FN_IP6_28_26, + GP_2_21_FN, FN_IP6_25_23, + GP_2_20_FN, FN_IP6_22_20, + GP_2_19_FN, FN_IP6_19_17, + GP_2_18_FN, FN_IP6_16_14, + GP_2_17_FN, FN_VI1_DATA7_VI1_B7, + GP_2_16_FN, FN_IP8_27, + GP_2_15_FN, FN_IP8_26, + GP_2_14_FN, FN_IP8_25_24, + GP_2_13_FN, FN_IP8_23_22, + GP_2_12_FN, FN_IP8_21_20, + GP_2_11_FN, FN_IP8_19_18, + GP_2_10_FN, FN_IP8_17_16, + GP_2_9_FN, FN_IP8_15_14, + GP_2_8_FN, FN_IP8_13_12, + GP_2_7_FN, FN_IP8_11_10, + GP_2_6_FN, FN_IP8_9_8, + GP_2_5_FN, FN_IP8_7_6, + GP_2_4_FN, FN_IP8_5_4, + GP_2_3_FN, FN_IP8_3_2, + GP_2_2_FN, FN_IP8_1_0, + GP_2_1_FN, FN_IP7_30_29, + GP_2_0_FN, FN_IP7_28_27 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP11_21_18, + GP_3_30_FN, FN_IP11_17_15, + GP_3_29_FN, FN_IP11_14_13, + GP_3_28_FN, FN_IP11_12_11, + GP_3_27_FN, FN_IP11_10_9, + GP_3_26_FN, FN_IP11_8_7, + GP_3_25_FN, FN_IP11_6_5, + GP_3_24_FN, FN_IP11_4, + GP_3_23_FN, FN_IP11_3_0, + GP_3_22_FN, FN_IP10_29_26, + GP_3_21_FN, FN_IP10_25_23, + GP_3_20_FN, FN_IP10_22_19, + GP_3_19_FN, FN_IP10_18_15, + GP_3_18_FN, FN_IP10_14_11, + GP_3_17_FN, FN_IP10_10_7, + GP_3_16_FN, FN_IP10_6_4, + GP_3_15_FN, FN_IP10_3_0, + GP_3_14_FN, FN_IP9_31_28, + GP_3_13_FN, FN_IP9_27_26, + GP_3_12_FN, FN_IP9_25_24, + GP_3_11_FN, FN_IP9_23_22, + GP_3_10_FN, FN_IP9_21_20, + GP_3_9_FN, FN_IP9_19_18, + GP_3_8_FN, FN_IP9_17_16, + GP_3_7_FN, FN_IP9_15_12, + GP_3_6_FN, FN_IP9_11_8, + GP_3_5_FN, FN_IP9_7_6, + GP_3_4_FN, FN_IP9_5_4, + GP_3_3_FN, FN_IP9_3_2, + GP_3_2_FN, FN_IP9_1_0, + GP_3_1_FN, FN_IP8_30_29, + GP_3_0_FN, FN_IP8_28 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP14_18_16, + GP_4_30_FN, FN_IP14_15_12, + GP_4_29_FN, FN_IP14_11_9, + GP_4_28_FN, FN_IP14_8_6, + GP_4_27_FN, FN_IP14_5_3, + GP_4_26_FN, FN_IP14_2_0, + GP_4_25_FN, FN_IP13_30_29, + GP_4_24_FN, FN_IP13_28_26, + GP_4_23_FN, FN_IP13_25_23, + GP_4_22_FN, FN_IP13_22_19, + GP_4_21_FN, FN_IP13_18_16, + GP_4_20_FN, FN_IP13_15_13, + GP_4_19_FN, FN_IP13_12_10, + GP_4_18_FN, FN_IP13_9_7, + GP_4_17_FN, FN_IP13_6_3, + GP_4_16_FN, FN_IP13_2_0, + GP_4_15_FN, FN_IP12_30_28, + GP_4_14_FN, FN_IP12_27_25, + GP_4_13_FN, FN_IP12_24_23, + GP_4_12_FN, FN_IP12_22_20, + GP_4_11_FN, FN_IP12_19_17, + GP_4_10_FN, FN_IP12_16_14, + GP_4_9_FN, FN_IP12_13_11, + GP_4_8_FN, FN_IP12_10_8, + GP_4_7_FN, FN_IP12_7_6, + GP_4_6_FN, FN_IP12_5_4, + GP_4_5_FN, FN_IP12_3_2, + GP_4_4_FN, FN_IP12_1_0, + GP_4_3_FN, FN_IP11_31_30, + GP_4_2_FN, FN_IP11_29_27, + GP_4_1_FN, FN_IP11_26_24, + GP_4_0_FN, FN_IP11_23_22 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP7_24_22, + GP_5_30_FN, FN_IP7_21_19, + GP_5_29_FN, FN_IP7_18_16, + GP_5_28_FN, FN_DU_DOTCLKIN2, + GP_5_27_FN, FN_IP7_26_25, + GP_5_26_FN, FN_DU_DOTCLKIN0, + GP_5_25_FN, FN_AVS2, + GP_5_24_FN, FN_AVS1, + GP_5_23_FN, FN_USB2_OVC, + GP_5_22_FN, FN_USB2_PWEN, + GP_5_21_FN, FN_IP16_7, + GP_5_20_FN, FN_IP16_6, + GP_5_19_FN, FN_USB0_OVC_VBUS, + GP_5_18_FN, FN_USB0_PWEN, + GP_5_17_FN, FN_IP16_5_3, + GP_5_16_FN, FN_IP16_2_0, + GP_5_15_FN, FN_IP15_29_28, + GP_5_14_FN, FN_IP15_27_26, + GP_5_13_FN, FN_IP15_25_23, + GP_5_12_FN, FN_IP15_22_20, + GP_5_11_FN, FN_IP15_19_18, + GP_5_10_FN, FN_IP15_17_16, + GP_5_9_FN, FN_IP15_15_14, + GP_5_8_FN, FN_IP15_13_12, + GP_5_7_FN, FN_IP15_11_9, + GP_5_6_FN, FN_IP15_8_6, + GP_5_5_FN, FN_IP15_5_3, + GP_5_4_FN, FN_IP15_2_0, + GP_5_3_FN, FN_IP14_30_28, + GP_5_2_FN, FN_IP14_27_25, + GP_5_1_FN, FN_IP14_24_22, + GP_5_0_FN, FN_IP14_21_19 } + }, + + /*IPSR0 - IPSR5*/ + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + /* IP6_31_29 [3] */ + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, + /* IP6_28_26 [3] */ + FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, + /* IP6_25_23 [3] */ + FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, + /* IP6_22_20 [3] */ + FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, + FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, + /* IP6_19_17 [3] */ + FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, + FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, + /* IP6_16_14 [3] */ + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, 0, + /* IP6_13_11 [3] */ + FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + /* IP6_10_9 [2] */ + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, + /* IP6_8_6 [3] */ + FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, + FN_SSI_SDATA8_C, 0, 0, 0, + /* IP6_5_3 [3] */ + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, + /* IP6_2_0 [3] */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + /* IP7_28_27 [2] */ + FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + /* IP7_26_25 [2] */ + FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, + /* IP7_24_22 [3] */ + FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, + 0, 0, 0, + /* IP7_21_19 [3] */ + FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, + FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, + /* IP7_18_16 [3] */ + FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, 0, 0, 0, + /* IP7_15_13 [3] */ + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, + /* IP7_12_10 [3] */ + FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, + FN_GLO_SCLK_C, 0, 0, 0, + /* IP7_9_8 [2] */ + FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, + /* IP7_7_6 [2] */ + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, + /* IP7_5_3 [3] */ + FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + 0, 0, 0, + /* IP7_2_0 [3] */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + }, + /*IPSR8 - IPSR16*/ + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_IN, GP_1_29_OUT, + GP_1_28_IN, GP_1_28_OUT, + GP_1_27_IN, GP_1_27_OUT, + GP_1_26_IN, GP_1_26_OUT, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_IN, GP_2_29_OUT, + GP_2_28_IN, GP_2_28_OUT, + GP_2_27_IN, GP_2_27_OUT, + GP_2_26_IN, GP_2_26_OUT, + GP_2_25_IN, GP_2_25_OUT, + GP_2_24_IN, GP_2_24_OUT, + GP_2_23_IN, GP_2_23_OUT, + GP_2_22_IN, GP_2_22_OUT, + GP_2_21_IN, GP_2_21_OUT, + GP_2_20_IN, GP_2_20_OUT, + GP_2_19_IN, GP_2_19_OUT, + GP_2_18_IN, GP_2_18_OUT, + GP_2_17_IN, GP_2_17_OUT, + GP_2_16_IN, GP_2_16_OUT, + GP_2_15_IN, GP_2_15_OUT, + GP_2_14_IN, GP_2_14_OUT, + GP_2_13_IN, GP_2_13_OUT, + GP_2_12_IN, GP_2_12_OUT, + GP_2_11_IN, GP_2_11_OUT, + GP_2_10_IN, GP_2_10_OUT, + GP_2_9_IN, GP_2_9_OUT, + GP_2_8_IN, GP_2_8_OUT, + GP_2_7_IN, GP_2_7_OUT, + GP_2_6_IN, GP_2_6_OUT, + GP_2_5_IN, GP_2_5_OUT, + GP_2_4_IN, GP_2_4_OUT, + GP_2_3_IN, GP_2_3_OUT, + GP_2_2_IN, GP_2_2_OUT, + GP_2_1_IN, GP_2_1_OUT, + GP_2_0_IN, GP_2_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, GP_1_29_DATA, GP_1_28_DATA, + GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { + 0, 0, GP_2_29_DATA, GP_2_28_DATA, + GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA, + GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA, + GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA, + GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, + GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, + GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, + GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } + }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, + { }, +}; + +static struct pinmux_info r8a7790_pinmux_info = { + .name = "r8a7790_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7790_pinmux_init(void) +{ + register_pinmux(&r8a7790_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h new file mode 100644 index 0000000000..a13317be0b --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h @@ -0,0 +1,92 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __PFC_R8A7790_H__ +#define __PFC_R8A7790_H__ + +#include +#include + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT2(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) + +#if defined(CONFIG_R8A7790) +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) \ +/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT1(fn, pfx##_1_, sfx), \ + CPU_32_PORT2(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx) + +#elif defined(CONFIG_R8A7791) +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) + +/* + * GP_0_0_DATA -> GP_7_25_DATA + * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31] + * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31]) + */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT1(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx), \ + CPU_32_PORT(fn, pfx##_6_, sfx), \ + CPU_32_PORT1(fn, pfx##_7_, sfx) +#else +#error "NO support" +#endif + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +#endif /* __PFC_R8A7790_H__ */ diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c new file mode 100644 index 0000000000..46d6e60c15 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c @@ -0,0 +1,1117 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include "pfc-r8a7790.h" + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, + FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, + FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, + FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, + FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, + FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, + + /* GPSR1 */ + FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, + FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, + FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, + FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, + FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, + FN_IP3_21_20, + + /* GPSR2 */ + FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, + FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, + FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, + FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, + FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, + FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, + FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, + FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, + FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, + FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, + FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, + FN_IP9_18_17, + + /* GPSR4 */ + FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, + FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2, + FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5, + FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, + FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, + FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, + FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, + + /* GPSR5 */ + FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, + FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, + FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, + FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, + FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, + FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, + + /* GPSR6 */ + FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, + FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23, + FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, + FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, + FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, + FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, + + /* GPSR7 */ + FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, + FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, + FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, + FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, + FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, + FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, + + /* IPSR0 - IPSR10 */ + + /* IPSR11 */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, + FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, + FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, + FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, + FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, + FN_VI1_DATA7, FN_AVB_MDC, + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, + + /* IPSR12 */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + + /* IPSR13 */ + /* MOD_SEL */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_QSP_0, FN_SEL_QSP_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, + FN_SEL_HSCIF1_4, + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, + + /* MOD_SEL2 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF0_4, + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, + FN_SEL_SIM_0, FN_SEL_SIM_1, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + + /* MOD_SEL3 */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_MMC_0, FN_SEL_MMC_1, + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, + + /* MOD_SEL4 */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, + FN_SEL_RAD_0, FN_SEL_RAD_1, + FN_SEL_RCN_0, FN_SEL_RCN_1, + FN_SEL_RSP_0, FN_SEL_RSP_1, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, + FN_SEL_SCIF2_4, + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, + FN_SEL_SOF2_4, + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + EX_CS0_N_MARK, RD_N_MARK, + + AUDIO_CLKA_MARK, + + VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK, + VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK, + VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, + + /* IPSR0 IPSR10 */ + /* IPSR11 */ + VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, + VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, + VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, + SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, + VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, + TX4_B_MARK, SCIFA4_TXD_B_MARK, + VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, + RX4_B_MARK, SCIFA4_RXD_B_MARK, + VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, + VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, + VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, + VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, + VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, + VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, + VI1_DATA7_MARK, AVB_MDC_MARK, + ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, + ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, + + /* IPSR12 */ + ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, + ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, + ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, + SCL2_D_MARK, MSIOF1_RXD_E_MARK, + ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, + SDA2_D_MARK, MSIOF1_SCK_E_MARK, + ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, + CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, + ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, + CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, + ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, + ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, + ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, + ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, + STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, + ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, + STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, + ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, + + /* IPSR13 */ + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + /* OTHER IPSR0 - IPSR10 */ + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), + PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), + PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_27, AVB_MDC), + PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), + PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), + + /* IPSR12 */ + PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), + PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), + PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), + PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), + PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), + PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), + PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), + PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), + PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), + PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), + PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), + + /* IPSR13 - IPSR16 */ +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + /* OTHER, IPSR0 - IPSR10 */ + /* IPSR11 */ + GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B), + GPIO_FN(RX0_C), GPIO_FN(SDA1_D), + GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7), + GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B), + GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B), + GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E), + GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D), + GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B), + GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B), + GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B), + GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B), + GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B), + GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B), + GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4), + GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5), + GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6), + GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7), + GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER), + GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO), + GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV), + GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC), + GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC), + GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C), + GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C), + + /* IPSR12 */ + GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7), + GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7), + GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C), + GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E), + GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C), + GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E), + GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B), + GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E), + GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B), + GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E), + GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3), + GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B), + GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C), + GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C), + GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C), + GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D), + GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C), + GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D), + GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C), + + /* IPSR13 - IPSR16 */ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP1_22_20, + GP_0_30_FN, FN_IP1_19_17, + GP_0_29_FN, FN_IP1_16_14, + GP_0_28_FN, FN_IP1_13_11, + GP_0_27_FN, FN_IP1_10_8, + GP_0_26_FN, FN_IP1_7_6, + GP_0_25_FN, FN_IP1_5_4, + GP_0_24_FN, FN_IP1_3_2, + GP_0_23_FN, FN_IP1_1_0, + GP_0_22_FN, FN_IP0_30_29, + GP_0_21_FN, FN_IP0_28_27, + GP_0_20_FN, FN_IP0_26_25, + GP_0_19_FN, FN_IP0_24_23, + GP_0_18_FN, FN_IP0_22_21, + GP_0_17_FN, FN_IP0_20_19, + GP_0_16_FN, FN_IP0_18_16, + GP_0_15_FN, FN_IP0_15, + GP_0_14_FN, FN_IP0_14, + GP_0_13_FN, FN_IP0_13, + GP_0_12_FN, FN_IP0_12, + GP_0_11_FN, FN_IP0_11, + GP_0_10_FN, FN_IP0_10, + GP_0_9_FN, FN_IP0_9, + GP_0_8_FN, FN_IP0_8, + GP_0_7_FN, FN_IP0_7, + GP_0_6_FN, FN_IP0_6, + GP_0_5_FN, FN_IP0_5, + GP_0_4_FN, FN_IP0_4, + GP_0_3_FN, FN_IP0_3, + GP_0_2_FN, FN_IP0_2, + GP_0_1_FN, FN_IP0_1, + GP_0_0_FN, FN_IP0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_IP3_21_20, + GP_1_24_FN, FN_IP3_19_18, + GP_1_23_FN, FN_IP3_17_16, + GP_1_22_FN, FN_IP3_15_14, + GP_1_21_FN, FN_IP3_13_12, + GP_1_20_FN, FN_IP3_11_9, + GP_1_19_FN, FN_RD_N, + GP_1_18_FN, FN_IP3_8_6, + GP_1_17_FN, FN_IP3_5_3, + GP_1_16_FN, FN_IP3_2_0, + GP_1_15_FN, FN_IP2_29_27, + GP_1_14_FN, FN_IP2_26_25, + GP_1_13_FN, FN_IP2_24_23, + GP_1_12_FN, FN_EX_CS0_N, + GP_1_11_FN, FN_IP2_22_21, + GP_1_10_FN, FN_IP2_20_19, + GP_1_9_FN, FN_IP2_18_16, + GP_1_8_FN, FN_IP2_15_13, + GP_1_7_FN, FN_IP2_12_10, + GP_1_6_FN, FN_IP2_9_7, + GP_1_5_FN, FN_IP2_6_5, + GP_1_4_FN, FN_IP2_4_3, + GP_1_3_FN, FN_IP2_2_0, + GP_1_2_FN, FN_IP1_31_29, + GP_1_1_FN, FN_IP1_28_26, + GP_1_0_FN, FN_IP1_25_23, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_3, + GP_2_29_FN, FN_IP6_2_0, + GP_2_28_FN, FN_AUDIO_CLKA, + GP_2_27_FN, FN_IP5_31_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_24, + GP_2_24_FN, FN_IP5_23_22, + GP_2_23_FN, FN_IP5_21_20, + GP_2_22_FN, FN_IP5_19_17, + GP_2_21_FN, FN_IP5_16_15, + GP_2_20_FN, FN_IP5_14_12, + GP_2_19_FN, FN_IP5_11_9, + GP_2_18_FN, FN_IP5_8_6, + GP_2_17_FN, FN_IP5_5_3, + GP_2_16_FN, FN_IP5_2_0, + GP_2_15_FN, FN_IP4_30_28, + GP_2_14_FN, FN_IP4_27_26, + GP_2_13_FN, FN_IP4_25_24, + GP_2_12_FN, FN_IP4_23_22, + GP_2_11_FN, FN_IP4_21, + GP_2_10_FN, FN_IP4_20, + GP_2_9_FN, FN_IP4_19, + GP_2_8_FN, FN_IP4_18_16, + GP_2_7_FN, FN_IP4_15_13, + GP_2_6_FN, FN_IP4_12_10, + GP_2_5_FN, FN_IP4_9_8, + GP_2_4_FN, FN_IP4_7_5, + GP_2_3_FN, FN_IP4_4_2, + GP_2_2_FN, FN_IP4_1_0, + GP_2_1_FN, FN_IP3_30_28, + GP_2_0_FN, FN_IP3_27_25 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP9_18_17, + GP_3_30_FN, FN_IP9_16, + GP_3_29_FN, FN_IP9_15_13, + GP_3_28_FN, FN_IP9_12, + GP_3_27_FN, FN_IP9_11, + GP_3_26_FN, FN_IP9_10_8, + GP_3_25_FN, FN_IP9_7, + GP_3_24_FN, FN_IP9_6, + GP_3_23_FN, FN_IP9_5_3, + GP_3_22_FN, FN_IP9_2_0, + GP_3_21_FN, FN_IP8_30_28, + GP_3_20_FN, FN_IP8_27_26, + GP_3_19_FN, FN_IP8_25_24, + GP_3_18_FN, FN_IP8_23_21, + GP_3_17_FN, FN_IP8_20_18, + GP_3_16_FN, FN_IP8_17_15, + GP_3_15_FN, FN_IP8_14_12, + GP_3_14_FN, FN_IP8_11_9, + GP_3_13_FN, FN_IP8_8_6, + GP_3_12_FN, FN_IP8_5_3, + GP_3_11_FN, FN_IP8_2_0, + GP_3_10_FN, FN_IP7_29_27, + GP_3_9_FN, FN_IP7_26_24, + GP_3_8_FN, FN_IP7_23_21, + GP_3_7_FN, FN_IP7_20_19, + GP_3_6_FN, FN_IP7_18_17, + GP_3_5_FN, FN_IP7_16_15, + GP_3_4_FN, FN_IP7_14_13, + GP_3_3_FN, FN_IP7_12_11, + GP_3_2_FN, FN_IP7_10_9, + GP_3_1_FN, FN_IP7_8_6, + GP_3_0_FN, FN_IP7_5_3 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP15_5_4, + GP_4_30_FN, FN_IP15_3_2, + GP_4_29_FN, FN_IP15_1_0, + GP_4_28_FN, FN_IP11_8_6, + GP_4_27_FN, FN_IP11_5_3, + GP_4_26_FN, FN_IP11_2_0, + GP_4_25_FN, FN_IP10_31_29, + GP_4_24_FN, FN_IP10_28_27, + GP_4_23_FN, FN_IP10_26_25, + GP_4_22_FN, FN_IP10_24_22, + GP_4_21_FN, FN_IP10_21_19, + GP_4_20_FN, FN_IP10_18_17, + GP_4_19_FN, FN_IP10_16_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_31_29, + GP_4_12_FN, FN_VI0_DATA0_VI0_B7, + GP_4_11_FN, FN_VI0_DATA0_VI0_B6, + GP_4_10_FN, FN_VI0_DATA0_VI0_B5, + GP_4_9_FN, FN_VI0_DATA0_VI0_B4, + GP_4_8_FN, FN_IP9_28_27, + GP_4_7_FN, FN_VI0_DATA0_VI0_B2, + GP_4_6_FN, FN_VI0_DATA0_VI0_B1, + GP_4_5_FN, FN_VI0_DATA0_VI0_B0, + GP_4_4_FN, FN_IP9_26_25, + GP_4_3_FN, FN_IP9_24_23, + GP_4_2_FN, FN_IP9_22_21, + GP_4_1_FN, FN_IP9_20_19, + GP_4_0_FN, FN_VI0_CLK } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP3_24_22, + GP_5_30_FN, FN_IP13_9_7, + GP_5_29_FN, FN_IP13_6_5, + GP_5_28_FN, FN_IP13_4_3, + GP_5_27_FN, FN_IP13_2_0, + GP_5_26_FN, FN_IP12_29_27, + GP_5_25_FN, FN_IP12_26_24, + GP_5_24_FN, FN_IP12_23_22, + GP_5_23_FN, FN_IP12_21_20, + GP_5_22_FN, FN_IP12_19_18, + GP_5_21_FN, FN_IP12_17_16, + GP_5_20_FN, FN_IP12_15_13, + GP_5_19_FN, FN_IP12_12_10, + GP_5_18_FN, FN_IP12_9_7, + GP_5_17_FN, FN_IP12_6_4, + GP_5_16_FN, FN_IP12_3_2, + GP_5_15_FN, FN_IP12_1_0, + GP_5_14_FN, FN_IP11_31_30, + GP_5_13_FN, FN_IP11_29_28, + GP_5_12_FN, FN_IP11_27, + GP_5_11_FN, FN_IP11_26, + GP_5_10_FN, FN_IP11_25, + GP_5_9_FN, FN_IP11_24, + GP_5_8_FN, FN_IP11_23, + GP_5_7_FN, FN_IP11_22, + GP_5_6_FN, FN_IP11_21, + GP_5_5_FN, FN_IP11_20, + GP_5_4_FN, FN_IP11_19, + GP_5_3_FN, FN_IP11_18_17, + GP_5_2_FN, FN_IP11_16_15, + GP_5_1_FN, FN_IP11_14_12, + GP_5_0_FN, FN_IP11_11_9 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + GP_6_29_FN, FN_IP14_31_29, + GP_6_28_FN, FN_IP14_28_26, + GP_6_27_FN, FN_IP14_25_23, + GP_6_26_FN, FN_IP14_22_20, + GP_6_25_FN, FN_IP14_19_17, + GP_6_24_FN, FN_IP14_16_14, + GP_6_23_FN, FN_IP14_13_11, + GP_6_22_FN, FN_IP14_10_8, + GP_6_21_FN, FN_IP14_7, + GP_6_20_FN, FN_IP14_6, + GP_6_19_FN, FN_IP14_5, + GP_6_18_FN, FN_IP14_4, + GP_6_17_FN, FN_IP14_3, + GP_6_16_FN, FN_IP14_2, + GP_6_15_FN, FN_IP14_1_0, + GP_6_14_FN, FN_IP13_30_28, + GP_6_13_FN, FN_IP13_27, + GP_6_12_FN, FN_IP13_26, + GP_6_11_FN, FN_IP13_25, + GP_6_10_FN, FN_IP13_24_23, + GP_6_9_FN, FN_IP13_22, + 0, 0, + GP_6_7_FN, FN_IP13_21_19, + GP_6_6_FN, FN_IP13_18_16, + GP_6_5_FN, FN_IP13_15, + GP_6_4_FN, FN_IP13_14, + GP_6_3_FN, FN_IP13_13, + GP_6_2_FN, FN_IP13_12, + GP_6_1_FN, FN_IP13_11, + GP_6_0_FN, FN_IP13_10 } + }, + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_FN, FN_USB1_PWEN, + GP_7_24_FN, FN_USB0_OVC, + GP_7_23_FN, FN_USB0_PWEN, + GP_7_22_FN, FN_IP15_14_12, + GP_7_21_FN, FN_IP15_11_9, + GP_7_20_FN, FN_IP15_8_6, + GP_7_19_FN, FN_IP7_2_0, + GP_7_18_FN, FN_IP6_29_27, + GP_7_17_FN, FN_IP6_26_24, + GP_7_16_FN, FN_IP6_23_21, + GP_7_15_FN, FN_IP6_20_19, + GP_7_14_FN, FN_IP6_18_16, + GP_7_13_FN, FN_IP6_15_14, + GP_7_12_FN, FN_IP6_13_12, + GP_7_11_FN, FN_IP6_11_10, + GP_7_10_FN, FN_IP6_9_8, + GP_7_9_FN, FN_IP16_11_10, + GP_7_8_FN, FN_IP16_9_8, + GP_7_7_FN, FN_IP16_7_6, + GP_7_6_FN, FN_IP16_5_3, + GP_7_5_FN, FN_IP16_2_0, + GP_7_4_FN, FN_IP15_29_27, + GP_7_3_FN, FN_IP15_26_24, + GP_7_2_FN, FN_IP15_23_21, + GP_7_1_FN, FN_IP15_20_18, + GP_7_0_FN, FN_IP15_17_15 } + }, + /* IPSR0 - IPSR10 */ + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 3, 3, 3, 3, 3) { + /* IP11_31_30 [2] */ + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, + /* IP11_29_28 [2] */ + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, + /* IP11_27 [1] */ + FN_VI1_DATA7, FN_AVB_MDC, + /* IP11_26 [1] */ + FN_VI1_DATA6, FN_AVB_MAGIC, + /* IP11_25 [1] */ + FN_VI1_DATA5, FN_AVB_RX_DV, + /* IP11_24 [1] */ + FN_VI1_DATA4, FN_AVB_MDIO, + /* IP11_23 [1] */ + FN_VI1_DATA3, FN_AVB_RX_ER, + /* IP11_22 [1] */ + FN_VI1_DATA2, FN_AVB_RXD7, + /* IP11_21 [1] */ + FN_VI1_DATA1, FN_AVB_RXD6, + /* IP11_20 [1] */ + FN_VI1_DATA0, FN_AVB_RXD5, + /* IP11_19 [1] */ + FN_VI1_CLK, FN_AVB_RXD4, + /* IP11_18_17 [2] */ + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, + /* IP11_16_15 [2] */ + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, + /* IP11_14_12 [3] */ + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, + FN_RX4_B, FN_SCIFA4_RXD_B, + 0, 0, 0, + /* IP11_11_9 [3] */ + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, + FN_TX4_B, FN_SCIFA4_TXD_B, + 0, 0, 0, + /* IP11_8_6 [3] */ + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, + /* IP11_5_3 [3] */ + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + 0, 0, 0, + /* IP11_2_0 [3] */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + /* IP12_31_30 [2] */ + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + 0, 0, 0, + /* IP12_26_24 [3] */ + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + 0, 0, 0, + /* IP12_23_22 [2] */ + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, + /* IP12_21_20 [2] */ + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, + /* IP12_19_18 [2] */ + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, + /* IP12_17_16 [2] */ + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + /* IP12_15_13 [3] */ + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + 0, 0, 0, + /* IP12_12_10 [3] */ + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + 0, 0, 0, + /* IP12_9_7 [3] */ + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, + FN_SDA2_D, FN_MSIOF1_SCK_E, + 0, 0, 0, + /* IP12_6_4 [3] */ + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + 0, 0, 0, + /* IP12_3_2 [2] */ + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + /* IP12_1_0 [2] */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } + }, + + /* IPSR13 - IPSR16 */ + + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, + 3, 2, 2, 2, 1, 2, 2, 2) { + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, + FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, + FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + 0, 0, 0, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* SEL_SCFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_QSP [1] */ + FN_SEL_QSP_0, FN_SEL_QSP_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_HSCIF1 [3] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, + FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_VI1 [2] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_TMU [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_LBS [2] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF0 [2] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 3, 2, 1, 1, 2, 2, + 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + /* SEL_SCIF0 [3] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, + FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF [1] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + /* SEL_CAN0 [3] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + 0, 0, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_ADG [1] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, + FN_SEL_FM_3, FN_SEL_FM_4, + 0, 0, 0, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, + /* SEL_SCIFA3 [2] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, + /* SEL_SIM [1] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 2, 2, 2, 2, 2, + 1, 1, 2, 2, 3, 2, 2, 2, 1) { + /* SEL_HSCIF2 [2] */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + /* SEL_CANCLK [2] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + /* SEL_IIC8 [2] */ + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, + /* SEL_IIC7 [2] */ + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, + /* SEL_IIC4 [2] */ + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, + /* SEL_IIC3 [2] */ + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + /* SEL_SCIF3 [2] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_MMC [1] */ + FN_SEL_MMC_0, FN_SEL_MMC_1, + /* SEL_SCIF5 [1] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [2] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + /* SEL_IIC1 [3] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + 0, 0, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, + 3, 2, 2, 1, 1, 1, 1, 3, 2, + 2, 3, 1, 1, 1, 2, 2, 2, 2) { + /* SEL_SOF1 [3] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + 0, 0, 0, + /* SEL_HSCIF0 [2] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, + /* SEL_DIS [2] */ + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIF2 [3] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_SOF2 [3] */ + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, + FN_SEL_SOF2_3, FN_SEL_SOF2_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI0 [1] */ + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + /* SEL_SSP [2] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } }, + { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_IN, GP_7_25_OUT, + GP_7_24_IN, GP_7_24_OUT, + GP_7_23_IN, GP_7_23_OUT, + GP_7_22_IN, GP_7_22_OUT, + GP_7_21_IN, GP_7_21_OUT, + GP_7_20_IN, GP_7_20_OUT, + GP_7_19_IN, GP_7_19_OUT, + GP_7_18_IN, GP_7_18_OUT, + GP_7_17_IN, GP_7_17_OUT, + GP_7_16_IN, GP_7_16_OUT, + GP_7_15_IN, GP_7_15_OUT, + GP_7_14_IN, GP_7_14_OUT, + GP_7_13_IN, GP_7_13_OUT, + GP_7_12_IN, GP_7_12_OUT, + GP_7_11_IN, GP_7_11_OUT, + GP_7_10_IN, GP_7_10_OUT, + GP_7_9_IN, GP_7_9_OUT, + GP_7_8_IN, GP_7_8_OUT, + GP_7_7_IN, GP_7_7_OUT, + GP_7_6_IN, GP_7_6_OUT, + GP_7_5_IN, GP_7_5_OUT, + GP_7_4_IN, GP_7_4_OUT, + GP_7_3_IN, GP_7_3_OUT, + GP_7_2_IN, GP_7_2_OUT, + GP_7_1_IN, GP_7_1_OUT, + GP_7_0_IN, GP_7_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + 0, 0, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } }, + { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { + 0, 0, 0, 0, + 0, 0, GP_7_25_DATA, GP_7_24_DATA, + GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA, + GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA, + GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA, + GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA, + GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA, + GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7791_pinmux_info = { + .name = "r8a7791_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7791_pinmux_init(void) +{ + register_pinmux(&r8a7791_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c new file mode 100644 index 0000000000..03c27ad7fe --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c @@ -0,0 +1,1926 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) + +/* + * GP_0_0_DATA -> GP_7_25_DATA + * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31] + * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31]) + */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT1(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx), \ + CPU_32_PORT(fn, pfx##_6_, sfx), \ + CPU_32_PORT1(fn, pfx##_7_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, + FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, + FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, + FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, + FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, + FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, + + /* GPSR1 */ + FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, + FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, + FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, + FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, + FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, + FN_IP3_21_20, + + /* GPSR2 */ + FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, + FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, + FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, + FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, + FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, + FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, + FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, + FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, + FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, + FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, + FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, + FN_IP9_18_17, + + /* GPSR4 */ + FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, + FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2, + FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5, + FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, + FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, + FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, + FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, + + /* GPSR5 */ + FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, + FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, + FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, + FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, + FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, + FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, + + /* GPSR6 */ + FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, + FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23, + FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, + FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, + FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, + FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, + + /* GPSR7 */ + FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, + FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, + FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, + FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, + FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, + FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, + + /* IPSR 0 -5 */ + + /* IPSR6 */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, + FN_SCIF_CLK, FN_BPFCLK_E, + FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, + FN_SCIFA2_RXD, FN_FMIN_E, + FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, + FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, + FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, + FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, + FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, + FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E, + FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, + FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, + + /* IPSR7 - IPSR10 */ + + /* IPSR11 */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, + FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, + FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, + FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, + FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, + FN_VI1_DATA7, FN_AVB_MDC, + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, + + /* IPSR12 */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + + /* IPSR13 */ + FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, + FN_ADICLK_B, FN_MSIOF0_SS1_C, + FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, + FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, + FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, + FN_ADICHS2_B, FN_MSIOF0_TXD_C, + FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B, + FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B, + FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B, + FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, + FN_SCIFA5_TXD_B, FN_TX3_C, + FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, + FN_SCIFA5_RXD_B, FN_RX3_C, + FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, + FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, + FN_SD1_DATA3, FN_IERX_B, + FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, + + /* IPSR14 */ + FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, + FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD, + FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1, + FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, + FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, + FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, + FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, + FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, + FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, + FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, + FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, + FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, + FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, + FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, + + /* IPSR15 */ + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, + FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, + FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, + FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, + FN_PWM5_B, FN_SCIFA3_TXD_C, + FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, + FN_VI1_G6_B, FN_SCIFA3_RXD_C, + FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, + FN_VI1_G7_B, FN_SCIFA3_SCK_C, + FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C, + FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C, + FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK, + FN_TCLK2, FN_VI1_DATA3_C, + FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C, + FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, + + /* IPSR16 */ + FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, + FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, + FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, + FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, + + /* MOD_SEL */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_QSP_0, FN_SEL_QSP_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, + FN_SEL_HSCIF1_4, + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, + + /* MOD_SEL2 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF0_4, + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, + FN_SEL_SIM_0, FN_SEL_SIM_1, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + + /* MOD_SEL3 */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_MMC_0, FN_SEL_MMC_1, + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, + + /* MOD_SEL4 */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, + FN_SEL_RAD_0, FN_SEL_RAD_1, + FN_SEL_RCN_0, FN_SEL_RCN_1, + FN_SEL_RSP_0, FN_SEL_RSP_1, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, + FN_SEL_SCIF2_4, + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, + FN_SEL_SOF2_4, + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + EX_CS0_N_MARK, RD_N_MARK, + + AUDIO_CLKA_MARK, + + VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK, + VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK, + VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, + + /* IPSR0 - 5 */ + + /* IPSR6 */ + AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, + SCIF_CLK_MARK, BPFCLK_E_MARK, + AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, + SCIFA2_RXD_MARK, FMIN_E_MARK, + AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, + IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, + IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, + IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, + IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK, + MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, + IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK, + IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, + SDA1_E_MARK, MSIOF2_SYNC_E_MARK, + IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, + GPS_CLK_C_MARK, GPS_CLK_D_MARK, + IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, + GPS_SIGN_C_MARK, GPS_SIGN_D_MARK, + + /* IPSR7 - 10 */ + + /* IPSR11 */ + VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, + VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, + VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, + SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, + VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, + TX4_B_MARK, SCIFA4_TXD_B_MARK, + VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, + RX4_B_MARK, SCIFA4_RXD_B_MARK, + VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, + VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, + VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, + VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, + VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, + VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, + VI1_DATA7_MARK, AVB_MDC_MARK, + ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, + ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, + + /* IPSR12 */ + ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, + ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, + ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, + SCL2_D_MARK, MSIOF1_RXD_E_MARK, + ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, + SDA2_D_MARK, MSIOF1_SCK_E_MARK, + ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, + CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, + ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, + CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, + ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, + ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, + ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, + ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, + STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, + ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, + STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, + ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, + + /* IPSR13 */ + STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, + ADICLK_B_MARK, MSIOF0_SS1_C_MARK, + STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK, + STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK, + STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK, + ADICHS2_B_MARK, MSIOF0_TXD_C_MARK, + SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK, + SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK, + SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK, + SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK, + SCIFA5_TXD_B_MARK, TX3_C_MARK, + SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK, + SCIFA5_RXD_B_MARK, RX3_C_MARK, + SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, + SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, + SD1_DATA3_MARK, IERX_B_MARK, + SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK, + + /* IPSR14 */ + SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK, + SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK, + SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK, + SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK, + SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK, + SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK, + MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, + VI1_CLK_C_MARK, VI1_G0_B_MARK, + MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, + VI1_CLKENB_C_MARK, VI1_G1_B_MARK, + MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, + MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, + MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, + VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK, + MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, + VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK, + + /* IPSR15 */ + SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, + SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK, + SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK, + GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, + PWM5_B_MARK, SCIFA3_TXD_C_MARK, + GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK, + VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, + GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK, + VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, + HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK, + TCLK1_MARK, VI1_DATA1_C_MARK, + HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK, + HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK, + TCLK2_MARK, VI1_DATA3_C_MARK, + HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK, + CAN0_RX_B_MARK, VI1_DATA4_C_MARK, + HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK, + CAN0_TX_B_MARK, VI1_DATA5_C_MARK, + + /* IPSR16 */ + HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK, + GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, + HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, + GLO_SS_C_MARK, VI1_DATA7_C_MARK, + HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK, + HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, + HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N), + PINMUX_DATA(RD_N_MARK, FN_RD_N), + PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), + PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK), + PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0), + PINMUX_DATA(VI0_DATA0_VI0_B1_MARK, FN_VI0_DATA0_VI0_B1), + PINMUX_DATA(VI0_DATA0_VI0_B2_MARK, FN_VI0_DATA0_VI0_B2), + PINMUX_DATA(VI0_DATA0_VI0_B4_MARK, FN_VI0_DATA0_VI0_B4), + PINMUX_DATA(VI0_DATA0_VI0_B5_MARK, FN_VI0_DATA0_VI0_B5), + PINMUX_DATA(VI0_DATA0_VI0_B6_MARK, FN_VI0_DATA0_VI0_B6), + PINMUX_DATA(VI0_DATA0_VI0_B7_MARK, FN_VI0_DATA0_VI0_B7), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), + PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), + + /* IPSR0 - 5 */ + + /* IPSR6 */ + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4), + PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT), + PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_DATA(IP6_9_8, IRQ0), + PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N), + PINMUX_IPSR_DATA(IP6_11_10, IRQ1), + PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N), + PINMUX_IPSR_DATA(IP6_13_12, IRQ2), + PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N), + PINMUX_IPSR_DATA(IP6_15_14, IRQ3), + PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2), + PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP6_18_16, IRQ4), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP6_20_19, IRQ5), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_23_21, IRQ6), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_26_24, IRQ7), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP6_29_27, IRQ8), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), + + /* IPSR7 - 10 */ + + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), + PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), + PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_27, AVB_MDC), + PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), + PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), + + /* IPSR12 */ + PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), + PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), + PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), + PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), + PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), + PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), + PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), + PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), + PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), + PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), + PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), + + /* IPSR13 */ + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_6_5, AVB_COL), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK), + PINMUX_IPSR_DATA(IP13_9_7, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), + PINMUX_IPSR_DATA(IP13_10, SD0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_11, SD0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_12, SD0_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_13, SD0_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_14, SD0_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_15, SD0_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_18_16, SD0_CD), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2), + PINMUX_IPSR_DATA(IP13_21_19, SD0_WP), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_DATA(IP13_22, SD1_CMD), + PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_DATA(IP13_25, SD1_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_26, SD1_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_27, SD1_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_30_28, SD1_CD), + PINMUX_IPSR_DATA(IP13_30_28, PWM0), + PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0), + PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2), + + /* IPSR14 */ + PINMUX_IPSR_DATA(IP14_1_0, SD1_WP), + PINMUX_IPSR_DATA(IP14_1_0, PWM1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2), + PINMUX_IPSR_DATA(IP14_2, SD2_CLK), + PINMUX_IPSR_DATA(IP14_2, MMC_CLK), + PINMUX_IPSR_DATA(IP14_3, SD2_CMD), + PINMUX_IPSR_DATA(IP14_3, MMC_CMD), + PINMUX_IPSR_DATA(IP14_4, SD2_DATA0), + PINMUX_IPSR_DATA(IP14_4, MMC_D0), + PINMUX_IPSR_DATA(IP14_5, SD2_DATA1), + PINMUX_IPSR_DATA(IP14_5, MMC_D1), + PINMUX_IPSR_DATA(IP14_6, SD2_DATA2), + PINMUX_IPSR_DATA(IP14_6, MMC_D2), + PINMUX_IPSR_DATA(IP14_7, SD2_DATA3), + PINMUX_IPSR_DATA(IP14_7, MMC_D3), + PINMUX_IPSR_DATA(IP14_10_8, SD2_CD), + PINMUX_IPSR_DATA(IP14_10_8, MMC_D4), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_DATA(IP14_13_11, SD2_WP), + PINMUX_IPSR_DATA(IP14_13_11, MMC_D5), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2), + PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2), + PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B), + + /* IPSR15 */ + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP15_8_6, PWM5_B), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_DATA(IP15_11_9, PWM5), + PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_DATA(IP15_14_12, PWM6), + PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_DATA(IP15_23_21, TCLK2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), + + /* IPSR16 */ + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_7_6, MLB_CK), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), + PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N), + PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT), + PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + GPIO_FN(EX_CS0_N), GPIO_FN(RD_N), GPIO_FN(AUDIO_CLKA), + GPIO_FN(VI0_CLK), GPIO_FN(VI0_DATA0_VI0_B0), + GPIO_FN(VI0_DATA0_VI0_B1), GPIO_FN(VI0_DATA0_VI0_B2), + GPIO_FN(VI0_DATA0_VI0_B4), GPIO_FN(VI0_DATA0_VI0_B5), + GPIO_FN(VI0_DATA0_VI0_B6), GPIO_FN(VI0_DATA0_VI0_B7), + GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN), + + /* IPSR0 - 5 */ + + /* IPSR6 */ + GPIO_FN(AUDIO_CLKB), GPIO_FN(STP_OPWM_0_B), GPIO_FN(MSIOF1_SCK_B), + GPIO_FN(SCIF_CLK), GPIO_FN(BPFCLK_E), + GPIO_FN(AUDIO_CLKC), GPIO_FN(SCIFB0_SCK_C), + GPIO_FN(MSIOF1_SYNC_B), GPIO_FN(RX2), + GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN_E), + GPIO_FN(AUDIO_CLKOUT), GPIO_FN(MSIOF1_SS1_B), + GPIO_FN(TX2), GPIO_FN(SCIFA2_TXD), + GPIO_FN(IRQ0), GPIO_FN(SCIFB1_RXD_D), GPIO_FN(INTC_IRQ0_N), + GPIO_FN(IRQ1), GPIO_FN(SCIFB1_SCK_C), GPIO_FN(INTC_IRQ1_N), + GPIO_FN(IRQ2), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(INTC_IRQ2_N), + GPIO_FN(IRQ3), GPIO_FN(SCL4_C), + GPIO_FN(MSIOF2_TXD_E), GPIO_FN(INTC_IRQ3_N), + GPIO_FN(IRQ4), GPIO_FN(HRX1_C), GPIO_FN(SDA4_C), + GPIO_FN(MSIOF2_RXD_E), GPIO_FN(INTC_IRQ4_N), + GPIO_FN(IRQ5), GPIO_FN(HTX1_C), GPIO_FN(SCL1_E), GPIO_FN(MSIOF2_SCK_E), + GPIO_FN(IRQ6), GPIO_FN(HSCK1_C), GPIO_FN(MSIOF1_SS2_B), + GPIO_FN(SDA1_E), GPIO_FN(MSIOF2_SYNC_E), + GPIO_FN(IRQ7), GPIO_FN(HCTS1_N_C), GPIO_FN(MSIOF1_TXD_B), + GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), + GPIO_FN(IRQ8), GPIO_FN(HRTS1_N_C), GPIO_FN(MSIOF1_RXD_B), + GPIO_FN(GPS_SIGN_C), GPIO_FN(GPS_SIGN_D), + + /* IPSR7 - 10 */ + + /* IPSR11 */ + GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B), + GPIO_FN(RX0_C), GPIO_FN(SDA1_D), + GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7), + GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B), + GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B), + GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E), + GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D), + GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B), + GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B), + GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B), + GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B), + GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B), + GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B), + GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4), + GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5), + GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6), + GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7), + GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER), + GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO), + GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV), + GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC), + GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC), + GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C), + GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C), + + /* IPSR12 */ + GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7), + GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7), + GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C), + GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E), + GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C), + GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E), + GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B), + GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E), + GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B), + GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E), + GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3), + GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B), + GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C), + GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C), + GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C), + GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D), + GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C), + GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D), + GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C), + + /* IPSR13 */ + GPIO_FN(STP_ISD_0), GPIO_FN(AVB_TX_ER), GPIO_FN(SCIFB2_SCK_C), + GPIO_FN(ADICLK_B), GPIO_FN(MSIOF0_SS1_C), + GPIO_FN(STP_ISEN_0), GPIO_FN(AVB_TX_CLK), + GPIO_FN(ADICHS0_B), GPIO_FN(MSIOF0_SS2_C), + GPIO_FN(STP_ISSYNC_0), GPIO_FN(AVB_COL), + GPIO_FN(ADICHS1_B), GPIO_FN(MSIOF0_RXD_C), + GPIO_FN(STP_OPWM_0), GPIO_FN(AVB_GTX_CLK), GPIO_FN(PWM0_B), + GPIO_FN(ADICHS2_B), GPIO_FN(MSIOF0_TXD_C), + GPIO_FN(SD0_CLK), GPIO_FN(SPCLK_B), + GPIO_FN(SD0_CMD), GPIO_FN(MOSI_IO0_B), + GPIO_FN(SD0_DATA0), GPIO_FN(MISO_IO1_B), + GPIO_FN(SD0_DATA1), GPIO_FN(IO2_B), + GPIO_FN(SD0_DATA2), GPIO_FN(IO3_B), GPIO_FN(SD0_DATA3), GPIO_FN(SSL_B), + GPIO_FN(SD0_CD), GPIO_FN(MMC_D6_B), + GPIO_FN(SIM0_RST_B), GPIO_FN(CAN0_RX_F), + GPIO_FN(SCIFA5_TXD_B), GPIO_FN(TX3_C), + GPIO_FN(SD0_WP), GPIO_FN(MMC_D7_B), + GPIO_FN(SIM0_D_B), GPIO_FN(CAN0_TX_F), + GPIO_FN(SCIFA5_RXD_B), GPIO_FN(RX3_C), + GPIO_FN(SD1_CMD), GPIO_FN(REMOCON_B), + GPIO_FN(SD1_DATA0), GPIO_FN(SPEEDIN_B), + GPIO_FN(SD1_DATA1), GPIO_FN(IETX_B), + GPIO_FN(SD1_DATA2), GPIO_FN(IECLK_B), + GPIO_FN(SD1_DATA3), GPIO_FN(IERX_B), + GPIO_FN(SD1_CD), GPIO_FN(PWM0), GPIO_FN(TPU_TO0), GPIO_FN(SCL1_C), + + /* IPSR14 */ + GPIO_FN(SD1_WP), GPIO_FN(PWM1_B), GPIO_FN(SDA1_C), + GPIO_FN(SD2_CLK), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CMD), GPIO_FN(MMC_CMD), + GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D0), + GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D1), + GPIO_FN(SD2_DATA2), GPIO_FN(MMC_D2), + GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D3), + GPIO_FN(SD2_CD), GPIO_FN(MMC_D4), GPIO_FN(SCL8_C), + GPIO_FN(TX5_B), GPIO_FN(SCIFA5_TXD_C), + GPIO_FN(SD2_WP), GPIO_FN(MMC_D5), GPIO_FN(SDA8_C), + GPIO_FN(RX5_B), GPIO_FN(SCIFA5_RXD_C), + GPIO_FN(MSIOF0_SCK), GPIO_FN(RX2_C), GPIO_FN(ADIDATA), + GPIO_FN(VI1_CLK_C), GPIO_FN(VI1_G0_B), + GPIO_FN(MSIOF0_SYNC), GPIO_FN(TX2_C), GPIO_FN(ADICS_SAMP), + GPIO_FN(VI1_CLKENB_C), GPIO_FN(VI1_G1_B), + GPIO_FN(MSIOF0_TXD), GPIO_FN(ADICLK), + GPIO_FN(VI1_FIELD_C), GPIO_FN(VI1_G2_B), + GPIO_FN(MSIOF0_RXD), GPIO_FN(ADICHS0), + GPIO_FN(VI1_DATA0_C), GPIO_FN(VI1_G3_B), + GPIO_FN(MSIOF0_SS1), GPIO_FN(MMC_D6), GPIO_FN(ADICHS1), GPIO_FN(TX0_E), + GPIO_FN(VI1_HSYNC_N_C), GPIO_FN(SCL7_C), GPIO_FN(VI1_G4_B), + GPIO_FN(MSIOF0_SS2), GPIO_FN(MMC_D7), GPIO_FN(ADICHS2), GPIO_FN(RX0_E), + GPIO_FN(VI1_VSYNC_N_C), GPIO_FN(SDA7_C), GPIO_FN(VI1_G5_B), + + /* IPSR15 */ + GPIO_FN(SIM0_RST), GPIO_FN(IETX), GPIO_FN(CAN1_TX_D), + GPIO_FN(SIM0_CLK), GPIO_FN(IECLK), GPIO_FN(CAN_CLK_C), + GPIO_FN(SIM0_D), GPIO_FN(IERX), GPIO_FN(CAN1_RX_D), + GPIO_FN(GPS_CLK), GPIO_FN(DU1_DOTCLKIN_C), GPIO_FN(AUDIO_CLKB_B), + GPIO_FN(PWM5_B), GPIO_FN(SCIFA3_TXD_C), + GPIO_FN(GPS_SIGN), GPIO_FN(TX4_C), + GPIO_FN(SCIFA4_TXD_C), GPIO_FN(PWM5), + GPIO_FN(VI1_G6_B), GPIO_FN(SCIFA3_RXD_C), + GPIO_FN(GPS_MAG), GPIO_FN(RX4_C), GPIO_FN(SCIFA4_RXD_C), GPIO_FN(PWM6), + GPIO_FN(VI1_G7_B), GPIO_FN(SCIFA3_SCK_C), + GPIO_FN(HCTS0_N), GPIO_FN(SCIFB0_CTS_N), GPIO_FN(GLO_I0_C), + GPIO_FN(TCLK1), GPIO_FN(VI1_DATA1_C), + GPIO_FN(HRTS0_N), GPIO_FN(SCIFB0_RTS_N), + GPIO_FN(GLO_I1_C), GPIO_FN(VI1_DATA2_C), + GPIO_FN(HSCK0), GPIO_FN(SCIFB0_SCK), + GPIO_FN(GLO_Q0_C), GPIO_FN(CAN_CLK), + GPIO_FN(TCLK2), GPIO_FN(VI1_DATA3_C), + GPIO_FN(HRX0), GPIO_FN(SCIFB0_RXD), GPIO_FN(GLO_Q1_C), + GPIO_FN(CAN0_RX_B), GPIO_FN(VI1_DATA4_C), + GPIO_FN(HTX0), GPIO_FN(SCIFB0_TXD), GPIO_FN(GLO_SCLK_C), + GPIO_FN(CAN0_TX_B), GPIO_FN(VI1_DATA5_C), + + /* IPSR16 */ + GPIO_FN(HRX1), GPIO_FN(SCIFB1_RXD), GPIO_FN(VI1_R0_B), + GPIO_FN(GLO_SDATA_C), GPIO_FN(VI1_DATA6_C), + GPIO_FN(HTX1), GPIO_FN(SCIFB1_TXD), GPIO_FN(VI1_R1_B), + GPIO_FN(GLO_SS_C), GPIO_FN(VI1_DATA7_C), + GPIO_FN(HSCK1), GPIO_FN(SCIFB1_SCK), + GPIO_FN(MLB_CK), GPIO_FN(GLO_RFON_C), + GPIO_FN(HCTS1_N), GPIO_FN(SCIFB1_CTS_N), + GPIO_FN(MLB_SIG), GPIO_FN(CAN1_TX_B), + GPIO_FN(HRTS1_N), GPIO_FN(SCIFB1_RTS_N), + GPIO_FN(MLB_DAT), GPIO_FN(CAN1_RX_B), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP1_22_20, + GP_0_30_FN, FN_IP1_19_17, + GP_0_29_FN, FN_IP1_16_14, + GP_0_28_FN, FN_IP1_13_11, + GP_0_27_FN, FN_IP1_10_8, + GP_0_26_FN, FN_IP1_7_6, + GP_0_25_FN, FN_IP1_5_4, + GP_0_24_FN, FN_IP1_3_2, + GP_0_23_FN, FN_IP1_1_0, + GP_0_22_FN, FN_IP0_30_29, + GP_0_21_FN, FN_IP0_28_27, + GP_0_20_FN, FN_IP0_26_25, + GP_0_19_FN, FN_IP0_24_23, + GP_0_18_FN, FN_IP0_22_21, + GP_0_17_FN, FN_IP0_20_19, + GP_0_16_FN, FN_IP0_18_16, + GP_0_15_FN, FN_IP0_15, + GP_0_14_FN, FN_IP0_14, + GP_0_13_FN, FN_IP0_13, + GP_0_12_FN, FN_IP0_12, + GP_0_11_FN, FN_IP0_11, + GP_0_10_FN, FN_IP0_10, + GP_0_9_FN, FN_IP0_9, + GP_0_8_FN, FN_IP0_8, + GP_0_7_FN, FN_IP0_7, + GP_0_6_FN, FN_IP0_6, + GP_0_5_FN, FN_IP0_5, + GP_0_4_FN, FN_IP0_4, + GP_0_3_FN, FN_IP0_3, + GP_0_2_FN, FN_IP0_2, + GP_0_1_FN, FN_IP0_1, + GP_0_0_FN, FN_IP0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_IP3_21_20, + GP_1_24_FN, FN_IP3_19_18, + GP_1_23_FN, FN_IP3_17_16, + GP_1_22_FN, FN_IP3_15_14, + GP_1_21_FN, FN_IP3_13_12, + GP_1_20_FN, FN_IP3_11_9, + GP_1_19_FN, FN_RD_N, + GP_1_18_FN, FN_IP3_8_6, + GP_1_17_FN, FN_IP3_5_3, + GP_1_16_FN, FN_IP3_2_0, + GP_1_15_FN, FN_IP2_29_27, + GP_1_14_FN, FN_IP2_26_25, + GP_1_13_FN, FN_IP2_24_23, + GP_1_12_FN, FN_EX_CS0_N, + GP_1_11_FN, FN_IP2_22_21, + GP_1_10_FN, FN_IP2_20_19, + GP_1_9_FN, FN_IP2_18_16, + GP_1_8_FN, FN_IP2_15_13, + GP_1_7_FN, FN_IP2_12_10, + GP_1_6_FN, FN_IP2_9_7, + GP_1_5_FN, FN_IP2_6_5, + GP_1_4_FN, FN_IP2_4_3, + GP_1_3_FN, FN_IP2_2_0, + GP_1_2_FN, FN_IP1_31_29, + GP_1_1_FN, FN_IP1_28_26, + GP_1_0_FN, FN_IP1_25_23, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_3, + GP_2_29_FN, FN_IP6_2_0, + GP_2_28_FN, FN_AUDIO_CLKA, + GP_2_27_FN, FN_IP5_31_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_24, + GP_2_24_FN, FN_IP5_23_22, + GP_2_23_FN, FN_IP5_21_20, + GP_2_22_FN, FN_IP5_19_17, + GP_2_21_FN, FN_IP5_16_15, + GP_2_20_FN, FN_IP5_14_12, + GP_2_19_FN, FN_IP5_11_9, + GP_2_18_FN, FN_IP5_8_6, + GP_2_17_FN, FN_IP5_5_3, + GP_2_16_FN, FN_IP5_2_0, + GP_2_15_FN, FN_IP4_30_28, + GP_2_14_FN, FN_IP4_27_26, + GP_2_13_FN, FN_IP4_25_24, + GP_2_12_FN, FN_IP4_23_22, + GP_2_11_FN, FN_IP4_21, + GP_2_10_FN, FN_IP4_20, + GP_2_9_FN, FN_IP4_19, + GP_2_8_FN, FN_IP4_18_16, + GP_2_7_FN, FN_IP4_15_13, + GP_2_6_FN, FN_IP4_12_10, + GP_2_5_FN, FN_IP4_9_8, + GP_2_4_FN, FN_IP4_7_5, + GP_2_3_FN, FN_IP4_4_2, + GP_2_2_FN, FN_IP4_1_0, + GP_2_1_FN, FN_IP3_30_28, + GP_2_0_FN, FN_IP3_27_25 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP9_18_17, + GP_3_30_FN, FN_IP9_16, + GP_3_29_FN, FN_IP9_15_13, + GP_3_28_FN, FN_IP9_12, + GP_3_27_FN, FN_IP9_11, + GP_3_26_FN, FN_IP9_10_8, + GP_3_25_FN, FN_IP9_7, + GP_3_24_FN, FN_IP9_6, + GP_3_23_FN, FN_IP9_5_3, + GP_3_22_FN, FN_IP9_2_0, + GP_3_21_FN, FN_IP8_30_28, + GP_3_20_FN, FN_IP8_27_26, + GP_3_19_FN, FN_IP8_25_24, + GP_3_18_FN, FN_IP8_23_21, + GP_3_17_FN, FN_IP8_20_18, + GP_3_16_FN, FN_IP8_17_15, + GP_3_15_FN, FN_IP8_14_12, + GP_3_14_FN, FN_IP8_11_9, + GP_3_13_FN, FN_IP8_8_6, + GP_3_12_FN, FN_IP8_5_3, + GP_3_11_FN, FN_IP8_2_0, + GP_3_10_FN, FN_IP7_29_27, + GP_3_9_FN, FN_IP7_26_24, + GP_3_8_FN, FN_IP7_23_21, + GP_3_7_FN, FN_IP7_20_19, + GP_3_6_FN, FN_IP7_18_17, + GP_3_5_FN, FN_IP7_16_15, + GP_3_4_FN, FN_IP7_14_13, + GP_3_3_FN, FN_IP7_12_11, + GP_3_2_FN, FN_IP7_10_9, + GP_3_1_FN, FN_IP7_8_6, + GP_3_0_FN, FN_IP7_5_3 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP15_5_4, + GP_4_30_FN, FN_IP15_3_2, + GP_4_29_FN, FN_IP15_1_0, + GP_4_28_FN, FN_IP11_8_6, + GP_4_27_FN, FN_IP11_5_3, + GP_4_26_FN, FN_IP11_2_0, + GP_4_25_FN, FN_IP10_31_29, + GP_4_24_FN, FN_IP10_28_27, + GP_4_23_FN, FN_IP10_26_25, + GP_4_22_FN, FN_IP10_24_22, + GP_4_21_FN, FN_IP10_21_19, + GP_4_20_FN, FN_IP10_18_17, + GP_4_19_FN, FN_IP10_16_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_31_29, + GP_4_12_FN, FN_VI0_DATA0_VI0_B7, + GP_4_11_FN, FN_VI0_DATA0_VI0_B6, + GP_4_10_FN, FN_VI0_DATA0_VI0_B5, + GP_4_9_FN, FN_VI0_DATA0_VI0_B4, + GP_4_8_FN, FN_IP9_28_27, + GP_4_7_FN, FN_VI0_DATA0_VI0_B2, + GP_4_6_FN, FN_VI0_DATA0_VI0_B1, + GP_4_5_FN, FN_VI0_DATA0_VI0_B0, + GP_4_4_FN, FN_IP9_26_25, + GP_4_3_FN, FN_IP9_24_23, + GP_4_2_FN, FN_IP9_22_21, + GP_4_1_FN, FN_IP9_20_19, + GP_4_0_FN, FN_VI0_CLK } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP3_24_22, + GP_5_30_FN, FN_IP13_9_7, + GP_5_29_FN, FN_IP13_6_5, + GP_5_28_FN, FN_IP13_4_3, + GP_5_27_FN, FN_IP13_2_0, + GP_5_26_FN, FN_IP12_29_27, + GP_5_25_FN, FN_IP12_26_24, + GP_5_24_FN, FN_IP12_23_22, + GP_5_23_FN, FN_IP12_21_20, + GP_5_22_FN, FN_IP12_19_18, + GP_5_21_FN, FN_IP12_17_16, + GP_5_20_FN, FN_IP12_15_13, + GP_5_19_FN, FN_IP12_12_10, + GP_5_18_FN, FN_IP12_9_7, + GP_5_17_FN, FN_IP12_6_4, + GP_5_16_FN, FN_IP12_3_2, + GP_5_15_FN, FN_IP12_1_0, + GP_5_14_FN, FN_IP11_31_30, + GP_5_13_FN, FN_IP11_29_28, + GP_5_12_FN, FN_IP11_27, + GP_5_11_FN, FN_IP11_26, + GP_5_10_FN, FN_IP11_25, + GP_5_9_FN, FN_IP11_24, + GP_5_8_FN, FN_IP11_23, + GP_5_7_FN, FN_IP11_22, + GP_5_6_FN, FN_IP11_21, + GP_5_5_FN, FN_IP11_20, + GP_5_4_FN, FN_IP11_19, + GP_5_3_FN, FN_IP11_18_17, + GP_5_2_FN, FN_IP11_16_15, + GP_5_1_FN, FN_IP11_14_12, + GP_5_0_FN, FN_IP11_11_9 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + GP_6_29_FN, FN_IP14_31_29, + GP_6_28_FN, FN_IP14_28_26, + GP_6_27_FN, FN_IP14_25_23, + GP_6_26_FN, FN_IP14_22_20, + GP_6_25_FN, FN_IP14_19_17, + GP_6_24_FN, FN_IP14_16_14, + GP_6_23_FN, FN_IP14_13_11, + GP_6_22_FN, FN_IP14_10_8, + GP_6_21_FN, FN_IP14_7, + GP_6_20_FN, FN_IP14_6, + GP_6_19_FN, FN_IP14_5, + GP_6_18_FN, FN_IP14_4, + GP_6_17_FN, FN_IP14_3, + GP_6_16_FN, FN_IP14_2, + GP_6_15_FN, FN_IP14_1_0, + GP_6_14_FN, FN_IP13_30_28, + GP_6_13_FN, FN_IP13_27, + GP_6_12_FN, FN_IP13_26, + GP_6_11_FN, FN_IP13_25, + GP_6_10_FN, FN_IP13_24_23, + GP_6_9_FN, FN_IP13_22, + 0, 0, + GP_6_7_FN, FN_IP13_21_19, + GP_6_6_FN, FN_IP13_18_16, + GP_6_5_FN, FN_IP13_15, + GP_6_4_FN, FN_IP13_14, + GP_6_3_FN, FN_IP13_13, + GP_6_2_FN, FN_IP13_12, + GP_6_1_FN, FN_IP13_11, + GP_6_0_FN, FN_IP13_10 } + }, + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_FN, FN_USB1_PWEN, + GP_7_24_FN, FN_USB0_OVC, + GP_7_23_FN, FN_USB0_PWEN, + GP_7_22_FN, FN_IP15_14_12, + GP_7_21_FN, FN_IP15_11_9, + GP_7_20_FN, FN_IP15_8_6, + GP_7_19_FN, FN_IP7_2_0, + GP_7_18_FN, FN_IP6_29_27, + GP_7_17_FN, FN_IP6_26_24, + GP_7_16_FN, FN_IP6_23_21, + GP_7_15_FN, FN_IP6_20_19, + GP_7_14_FN, FN_IP6_18_16, + GP_7_13_FN, FN_IP6_15_14, + GP_7_12_FN, FN_IP6_13_12, + GP_7_11_FN, FN_IP6_11_10, + GP_7_10_FN, FN_IP6_9_8, + GP_7_9_FN, FN_IP16_11_10, + GP_7_8_FN, FN_IP16_9_8, + GP_7_7_FN, FN_IP16_7_6, + GP_7_6_FN, FN_IP16_5_3, + GP_7_5_FN, FN_IP16_2_0, + GP_7_4_FN, FN_IP15_29_27, + GP_7_3_FN, FN_IP15_26_24, + GP_7_2_FN, FN_IP15_23_21, + GP_7_1_FN, FN_IP15_20_18, + GP_7_0_FN, FN_IP15_17_15 } + }, + + /* IPSR0 - 5 */ + + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) { + /* IP6_31_30 [2] */ + 0, 0, 0, 0, + /* IP6_29_27 [3] */ + FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, + FN_GPS_SIGN_C, FN_GPS_SIGN_D, + 0, 0, 0, + /* IP6_26_24 [3] */ + FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, + FN_GPS_CLK_C, FN_GPS_CLK_D, + 0, 0, 0, + /* IP6_23_21 [3] */ + FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, + FN_SDA1_E, FN_MSIOF2_SYNC_E, + 0, 0, 0, + /* IP6_20_19 [2] */ + FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, + /* IP6_18_16 [3] */ + FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + 0, 0, 0, + /* IP6_15_14 [2] */ + FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + /* IP6_13_12 [2] */ + FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, + /* IP6_11_10 [2] */ + FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, + /* IP6_9_8 [2] */ + FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, + /* IP6_7_6 [2] */ + FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, + /* IP6_5_3 [3] */ + FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, + FN_SCIFA2_RXD, FN_FMIN_E, + 0, 0, + /* IP6_2_0 [3] */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, + FN_SCIF_CLK, 0, FN_BPFCLK_E, + 0, 0, } + }, + + /* IPSR7 - 10 */ + + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 3, 3, 3, 3, 3) { + /* IP11_31_30 [2] */ + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, + /* IP11_29_28 [2] */ + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, + /* IP11_27 [1] */ + FN_VI1_DATA7, FN_AVB_MDC, + /* IP11_26 [1] */ + FN_VI1_DATA6, FN_AVB_MAGIC, + /* IP11_25 [1] */ + FN_VI1_DATA5, FN_AVB_RX_DV, + /* IP11_24 [1] */ + FN_VI1_DATA4, FN_AVB_MDIO, + /* IP11_23 [1] */ + FN_VI1_DATA3, FN_AVB_RX_ER, + /* IP11_22 [1] */ + FN_VI1_DATA2, FN_AVB_RXD7, + /* IP11_21 [1] */ + FN_VI1_DATA1, FN_AVB_RXD6, + /* IP11_20 [1] */ + FN_VI1_DATA0, FN_AVB_RXD5, + /* IP11_19 [1] */ + FN_VI1_CLK, FN_AVB_RXD4, + /* IP11_18_17 [2] */ + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, + /* IP11_16_15 [2] */ + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, + /* IP11_14_12 [3] */ + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, + FN_RX4_B, FN_SCIFA4_RXD_B, + 0, 0, 0, + /* IP11_11_9 [3] */ + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, + FN_TX4_B, FN_SCIFA4_TXD_B, + 0, 0, 0, + /* IP11_8_6 [3] */ + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, + /* IP11_5_3 [3] */ + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + 0, 0, 0, + /* IP11_2_0 [3] */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + /* IP12_31_30 [2] */ + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + 0, 0, 0, + /* IP12_26_24 [3] */ + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + 0, 0, 0, + /* IP12_23_22 [2] */ + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, + /* IP12_21_20 [2] */ + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, + /* IP12_19_18 [2] */ + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, + /* IP12_17_16 [2] */ + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + /* IP12_15_13 [3] */ + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + 0, 0, 0, + /* IP12_12_10 [3] */ + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + 0, 0, 0, + /* IP12_9_7 [3] */ + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, + FN_SDA2_D, FN_MSIOF1_SCK_E, + 0, 0, 0, + /* IP12_6_4 [3] */ + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + 0, 0, 0, + /* IP12_3_2 [2] */ + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + /* IP12_1_0 [2] */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, + 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, + 3, 2, 2, 3) { + /* IP13_31 [1] */ + 0, 0, + /* IP13_30_28 [3] */ + FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, + 0, 0, 0, 0, + /* IP13_27 [1] */ + FN_SD1_DATA3, FN_IERX_B, + /* IP13_26 [1] */ + FN_SD1_DATA2, FN_IECLK_B, + /* IP13_25 [1] */ + FN_SD1_DATA1, FN_IETX_B, + /* IP13_24_23 [2] */ + FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0, + /* IP13_22 [1] */ + FN_SD1_CMD, FN_REMOCON_B, + /* IP13_21_19 [3] */ + FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, + FN_SCIFA5_RXD_B, FN_RX3_C, + 0, 0, + /* IP13_18_16 [3] */ + FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, + FN_SCIFA5_TXD_B, FN_TX3_C, + 0, 0, + /* IP13_15 [1] */ + FN_SD0_DATA3, FN_SSL_B, + /* IP13_14 [1] */ + FN_SD0_DATA2, FN_IO3_B, + /* IP13_13 [1] */ + FN_SD0_DATA1, FN_IO2_B, + /* IP13_12 [1] */ + FN_SD0_DATA0, FN_MISO_IO1_B, + /* IP13_11 [1] */ + FN_SD0_CMD, FN_MOSI_IO0_B, + /* IP13_10 [1] */ + FN_SD0_CLK, FN_SPCLK_B, + /* IP13_9_7 [3] */ + FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, + FN_ADICHS2_B, FN_MSIOF0_TXD_C, + 0, 0, 0, + /* IP13_6_5 [2] */ + FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, + /* IP13_4_3 [2] */ + FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, + /* IP13_2_0 [3] */ + FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, + FN_ADICLK_B, FN_MSIOF0_SS1_C, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, + 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { + /* IP14_31_29 [3] */ + FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, + FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0, + /* IP14_28_26 [3] */ + FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, + FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0, + /* IP14_25_23 [3] */ + FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B, + 0, 0, 0, + /* IP14_22_20 [3] */ + FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B, + 0, 0, 0, + /* IP14_19_17 [3] */ + FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0, + FN_VI1_CLKENB_C, FN_VI1_G1_B, + 0, 0, + /* IP14_16_14 [3] */ + FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0, + FN_VI1_CLK_C, FN_VI1_G0_B, + 0, 0, + /* IP14_13_11 [3] */ + FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, + 0, 0, 0, + /* IP14_10_8 [3] */ + FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, + 0, 0, 0, + /* IP14_7 [1] */ + FN_SD2_DATA3, FN_MMC_D3, + /* IP14_6 [1] */ + FN_SD2_DATA2, FN_MMC_D2, + /* IP14_5 [1] */ + FN_SD2_DATA1, FN_MMC_D1, + /* IP14_4 [1] */ + FN_SD2_DATA0, FN_MMC_D0, + /* IP14_3 [1] */ + FN_SD2_CMD, FN_MMC_CMD, + /* IP14_2 [1] */ + FN_SD2_CLK, FN_MMC_CLK, + /* IP14_1_0 [2] */ + FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { + /* IP15_31_30 [2] */ + 0, 0, 0, 0, + /* IP15_29_27 [3] */ + FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C, + FN_CAN0_TX_B, FN_VI1_DATA5_C, + 0, 0, + /* IP15_26_24 [3] */ + FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C, + FN_CAN0_RX_B, FN_VI1_DATA4_C, + 0, 0, + /* IP15_23_21 [3] */ + FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK, + FN_TCLK2, FN_VI1_DATA3_C, 0, + /* IP15_20_18 [3] */ + FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C, + 0, 0, 0, + /* IP15_17_15 [3] */ + FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C, + FN_TCLK1, FN_VI1_DATA1_C, + 0, 0, + /* IP15_14_12 [3] */ + FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, + FN_VI1_G7_B, FN_SCIFA3_SCK_C, + 0, 0, + /* IP15_11_9 [3] */ + FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, + FN_VI1_G6_B, FN_SCIFA3_RXD_C, + 0, 0, + /* IP15_8_6 [3] */ + FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, + FN_PWM5_B, FN_SCIFA3_TXD_C, + 0, 0, 0, + /* IP15_5_4 [2] */ + FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0, + /* IP15_3_2 [2] */ + FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, + /* IP15_1_0 [2] */ + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, + 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) { + /* IP16_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_19_16 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_15_12 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_11_10 [2] */ + FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, + /* IP16_9_8 [2] */ + FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, + /* IP16_7_6 [2] */ + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, + /* IP16_5_3 [3] */ + FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, + FN_GLO_SS_C, FN_VI1_DATA7_C, + 0, 0, 0, + /* IP16_2_0 [3] */ + FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, + FN_GLO_SDATA_C, FN_VI1_DATA6_C, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, + 3, 2, 2, 2, 1, 2, 2, 2) { + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, + FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, + FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + 0, 0, 0, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* SEL_SCFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_QSP [1] */ + FN_SEL_QSP_0, FN_SEL_QSP_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_HSCIF1 [3] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, + FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_VI1 [2] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_TMU [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_LBS [2] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF0 [2] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 3, 2, 1, 1, 2, 2, + 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + /* SEL_SCIF0 [3] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, + FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF [1] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + /* SEL_CAN0 [3] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + 0, 0, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_ADG [1] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, + FN_SEL_FM_3, FN_SEL_FM_4, + 0, 0, 0, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, + /* SEL_SCIFA3 [2] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, + /* SEL_SIM [1] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 2, 2, 2, 2, 2, + 1, 1, 2, 2, 3, 2, 2, 2, 1) { + /* SEL_HSCIF2 [2] */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + /* SEL_CANCLK [2] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + /* SEL_IIC8 [2] */ + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, + /* SEL_IIC7 [2] */ + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, + /* SEL_IIC4 [2] */ + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, + /* SEL_IIC3 [2] */ + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + /* SEL_SCIF3 [2] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_MMC [1] */ + FN_SEL_MMC_0, FN_SEL_MMC_1, + /* SEL_SCIF5 [1] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [2] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + /* SEL_IIC1 [3] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + 0, 0, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, + 3, 2, 2, 1, 1, 1, 1, 3, 2, + 2, 3, 1, 1, 1, 2, 2, 2, 2) { + /* SEL_SOF1 [3] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + 0, 0, 0, + /* SEL_HSCIF0 [2] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, + /* SEL_DIS [2] */ + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIF2 [3] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_SOF2 [3] */ + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, + FN_SEL_SOF2_3, FN_SEL_SOF2_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI0 [1] */ + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + /* SEL_SSP [2] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } }, + { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_IN, GP_7_25_OUT, + GP_7_24_IN, GP_7_24_OUT, + GP_7_23_IN, GP_7_23_OUT, + GP_7_22_IN, GP_7_22_OUT, + GP_7_21_IN, GP_7_21_OUT, + GP_7_20_IN, GP_7_20_OUT, + GP_7_19_IN, GP_7_19_OUT, + GP_7_18_IN, GP_7_18_OUT, + GP_7_17_IN, GP_7_17_OUT, + GP_7_16_IN, GP_7_16_OUT, + GP_7_15_IN, GP_7_15_OUT, + GP_7_14_IN, GP_7_14_OUT, + GP_7_13_IN, GP_7_13_OUT, + GP_7_12_IN, GP_7_12_OUT, + GP_7_11_IN, GP_7_11_OUT, + GP_7_10_IN, GP_7_10_OUT, + GP_7_9_IN, GP_7_9_OUT, + GP_7_8_IN, GP_7_8_OUT, + GP_7_7_IN, GP_7_7_OUT, + GP_7_6_IN, GP_7_6_OUT, + GP_7_5_IN, GP_7_5_OUT, + GP_7_4_IN, GP_7_4_OUT, + GP_7_3_IN, GP_7_3_OUT, + GP_7_2_IN, GP_7_2_OUT, + GP_7_1_IN, GP_7_1_OUT, + GP_7_0_IN, GP_7_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + 0, 0, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } }, + { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { + 0, 0, 0, 0, + 0, 0, GP_7_25_DATA, GP_7_24_DATA, + GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA, + GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA, + GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA, + GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA, + GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA, + GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7793_pinmux_info = { + .name = "r8a7793_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_CAN1_RX_B, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7793_pinmux_init(void) +{ + register_pinmux(&r8a7793_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c new file mode 100644 index 0000000000..e123663333 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c @@ -0,0 +1,1513 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c + * This file is r8a7794 processor support - PFC hardware block. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_26_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) + +#define CPU_28_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \ + PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx) + +/* + * GP_0_0_DATA -> GP_6_25_DATA + * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31] + * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28], + * GP6[29]),GP6[30],GP6[31]) + */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_26_PORT(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_28_PORT(fn, pfx##_5_, sfx), \ + CPU_26_PORT(fn, pfx##_6_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, + FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, + FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, + FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, + FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, + FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, + FN_IP2_17_16, + + /* GPSR1 */ + FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, + FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, + FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, + FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, + FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, + + /* GPSR2 */ + FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, + FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, + FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, + FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, + FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, + FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, + FN_IP6_5_4, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, + FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, + FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, + FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, + FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, + FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, + FN_IP8_22_20, + + /* GPSR4 */ + FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, + FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, + FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, + FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, + FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, + FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, + + /* GPSR5 */ + FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, + FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, + FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, + FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, + FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, + FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, + + /* GPSR6 */ + FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, + FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, + FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, + FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, + FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, + FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, + FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, + FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, + FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, + FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, + FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, + FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, + FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, + FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, + FN_ADIDATA, FN_AD_DI, + + /* IPSR7 */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, + FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, + FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, + FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, + FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, + FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, + FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, + FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, + FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, + + /* IPSR8 */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, + FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, + FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, + FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, + FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, + FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, + FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, + FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, + FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, + FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, + FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, + FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, + FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, + FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, + FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, + FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, + FN_ADICLK_B, FN_AD_CLK_B, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + /* MOD_SEL */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, + FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, + FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, + FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, + FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, + FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, + FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, + FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, + FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, + FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, + FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, + + /* MOD_SEL2 */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, + FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, + FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, + FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, + FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, + FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, + FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, + FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, + FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, + FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, + FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, + FN_SEL_RDS_2, FN_SEL_RDS_3, + + /* MOD_SEL3 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, + FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, + FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, + FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, + FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, + FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, + FN_SEL_SSI9_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, + + SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, + SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, + + SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, + SD1_DATA2_MARK, SD1_DATA3_MARK, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, + DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, + CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, + AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, + VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, + AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, + VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, + AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, + I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, + VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, + AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, + IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, + I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, + VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, + ADIDATA_MARK, AD_DI_MARK, + + /* IPSR7 */ + ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, + AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, + MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, + AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, + CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, + ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, + AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, + MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, + ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, + SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, + IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, + VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, + SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, + AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, + SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, + DREQ0_N_MARK, SCIFB1_RXD_MARK, + + /* IPSR8 */ + ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, + AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, + I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, + HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, + AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, + SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, + HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, + AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, + HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, + I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, + AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, + SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, + CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, + DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, + I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, + TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, + I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, + FMCLK_C_MARK, RDS_CLK_MARK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, + CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, + DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, + SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, + SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, + DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, + SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, + CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, + DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, + DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, + AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, + MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, + PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, + ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, + PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(A2_MARK, FN_A2), + PINMUX_DATA(WE0_N_MARK, FN_WE0_N), + PINMUX_DATA(WE1_N_MARK, FN_WE1_N), + PINMUX_DATA(DACK0_MARK, FN_DACK0), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), + PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), + PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), + PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK), + PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD), + PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0), + PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1), + PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2), + PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3), + PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD), + PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP), + PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), + PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD), + PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0), + PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1), + PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), + PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE), + PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28), + PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE), + PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29), + PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP), + PINMUX_IPSR_DATA(IP6_5_4, QPOLA), + PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30), + PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE), + PINMUX_IPSR_DATA(IP6_7_6, QPOLB), + PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31), + PINMUX_IPSR_DATA(IP6_8, VI0_CLK), + PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK), + PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0), + PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV), + PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1), + PINMUX_IPSR_DATA(IP6_10, AVB_RXD0), + PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP6_11, AVB_RXD1), + PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP6_12, AVB_RXD2), + PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP6_13, AVB_RXD3), + PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP6_14, AVB_RXD4), + PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6), + PINMUX_IPSR_DATA(IP6_15, AVB_RXD5), + PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), + PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), + PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), + PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), + PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), + PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), + PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), + + /* IPSR7 */ + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), + PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_DATA(IP7_31, DREQ0_N), + PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), + + /* IPSR8 */ + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), + PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), + PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_19_17, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), + PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), + PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_28_26, IRQ5), + PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), + PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), + PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_DATA(IP11_20_18, IRQ8), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), + PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), + PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), + PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), + PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0), + GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN), + GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD), + GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2), + GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP), + GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0), + GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3), + + /* + * From IPSR0 to IPSR5 have been removed because they does not use + */ + + /* IPSR6 */ + GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), + GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), + GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP), + GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), + GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK), + GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV), + GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2), + GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2), + GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5), + GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5), + GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB), + GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C), + GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA), + GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER), + GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C), + GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N), + GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B), + GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0), + GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK), + GPIO_FN(ADIDATA), GPIO_FN(AD_DI), + + /* IPSR7 */ + GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B), + GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP), + GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2), + GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1), + GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3), + GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2), + GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1), + GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D), + GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5), + GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4), + GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6), + GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B), + GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C), + GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B), + GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C), + GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B), + GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B), + GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0), + GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E), + GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N), + GPIO_FN(SCIFB1_RXD), + + /* IPSR8 */ + GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B), + GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B), + GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C), + GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B), + GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C), + GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B), + GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D), + GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B), + GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D), + GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B), + GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS), + GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C), + GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK), + GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA), + GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK), + GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL), + GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0), + GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B), + GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5), + GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D), + GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD), + GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B), + GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK), + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C), + GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5), + GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1), + GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B), + GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13), + GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C), + GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14), + GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C), + GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15), + GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C), + GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B), + GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7), + GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D), + GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129), + GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B), + GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129), + GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B), + GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B), + GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B), + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP2_17_16, + GP_0_30_FN, FN_IP2_15_14, + GP_0_29_FN, FN_IP2_13_12, + GP_0_28_FN, FN_IP2_11_10, + GP_0_27_FN, FN_IP2_9_8, + GP_0_26_FN, FN_IP2_7_6, + GP_0_25_FN, FN_IP2_5_4, + GP_0_24_FN, FN_IP2_3_2, + GP_0_23_FN, FN_IP2_1_0, + GP_0_22_FN, FN_IP1_31_30, + GP_0_21_FN, FN_IP1_29_28, + GP_0_20_FN, FN_IP1_27, + GP_0_19_FN, FN_IP1_26, + GP_0_18_FN, FN_A2, + GP_0_17_FN, FN_IP1_24, + GP_0_16_FN, FN_IP1_23_22, + GP_0_15_FN, FN_IP1_21_20, + GP_0_14_FN, FN_IP1_19_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_13, + GP_0_11_FN, FN_IP1_12_11, + GP_0_10_FN, FN_IP1_10_8, + GP_0_9_FN, FN_IP1_7_6, + GP_0_8_FN, FN_IP1_5_4, + GP_0_7_FN, FN_IP1_3_2, + GP_0_6_FN, FN_IP1_1_0, + GP_0_5_FN, FN_IP0_31_30, + GP_0_4_FN, FN_IP0_29_28, + GP_0_3_FN, FN_IP0_27_26, + GP_0_2_FN, FN_IP0_25, + GP_0_1_FN, FN_IP0_24, + GP_0_0_FN, FN_IP0_23_22, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_DACK0, + GP_1_24_FN, FN_IP7_31, + GP_1_23_FN, FN_IP4_1_0, + GP_1_22_FN, FN_WE1_N, + GP_1_21_FN, FN_WE0_N, + GP_1_20_FN, FN_IP3_31, + GP_1_19_FN, FN_IP3_30, + GP_1_18_FN, FN_IP3_29_27, + GP_1_17_FN, FN_IP3_26_24, + GP_1_16_FN, FN_IP3_23_21, + GP_1_15_FN, FN_IP3_20_18, + GP_1_14_FN, FN_IP3_17_15, + GP_1_13_FN, FN_IP3_14_13, + GP_1_12_FN, FN_IP3_12, + GP_1_11_FN, FN_IP3_11, + GP_1_10_FN, FN_IP3_10, + GP_1_9_FN, FN_IP3_9_8, + GP_1_8_FN, FN_IP3_7_6, + GP_1_7_FN, FN_IP3_5_4, + GP_1_6_FN, FN_IP3_3_2, + GP_1_5_FN, FN_IP3_1_0, + GP_1_4_FN, FN_IP2_31_30, + GP_1_3_FN, FN_IP2_29_27, + GP_1_2_FN, FN_IP2_26_24, + GP_1_1_FN, FN_IP2_23_21, + GP_1_0_FN, FN_IP2_20_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_4, + GP_2_29_FN, FN_IP6_3_2, + GP_2_28_FN, FN_IP6_1_0, + GP_2_27_FN, FN_IP5_31_30, + GP_2_26_FN, FN_IP5_29_28, + GP_2_25_FN, FN_IP5_27_26, + GP_2_24_FN, FN_IP5_25_24, + GP_2_23_FN, FN_IP5_23_22, + GP_2_22_FN, FN_IP5_21_20, + GP_2_21_FN, FN_IP5_19_18, + GP_2_20_FN, FN_IP5_17_16, + GP_2_19_FN, FN_IP5_15_14, + GP_2_18_FN, FN_IP5_13_12, + GP_2_17_FN, FN_IP5_11_9, + GP_2_16_FN, FN_IP5_8_6, + GP_2_15_FN, FN_IP5_5_4, + GP_2_14_FN, FN_IP5_3_2, + GP_2_13_FN, FN_IP5_1_0, + GP_2_12_FN, FN_IP4_31_30, + GP_2_11_FN, FN_IP4_29_28, + GP_2_10_FN, FN_IP4_27_26, + GP_2_9_FN, FN_IP4_25_23, + GP_2_8_FN, FN_IP4_22_20, + GP_2_7_FN, FN_IP4_19_18, + GP_2_6_FN, FN_IP4_17_16, + GP_2_5_FN, FN_IP4_15_14, + GP_2_4_FN, FN_IP4_13_12, + GP_2_3_FN, FN_IP4_11_10, + GP_2_2_FN, FN_IP4_9_8, + GP_2_1_FN, FN_IP4_7_5, + GP_2_0_FN, FN_IP4_4_2 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP8_22_20, + GP_3_30_FN, FN_IP8_19_17, + GP_3_29_FN, FN_IP8_16_15, + GP_3_28_FN, FN_IP8_14_12, + GP_3_27_FN, FN_IP8_11_9, + GP_3_26_FN, FN_IP8_8_6, + GP_3_25_FN, FN_IP8_5_3, + GP_3_24_FN, FN_IP8_2_0, + GP_3_23_FN, FN_IP7_29_27, + GP_3_22_FN, FN_IP7_26_24, + GP_3_21_FN, FN_IP7_23_21, + GP_3_20_FN, FN_IP7_20_18, + GP_3_19_FN, FN_IP7_17_15, + GP_3_18_FN, FN_IP7_14_12, + GP_3_17_FN, FN_IP7_11_9, + GP_3_16_FN, FN_IP7_8_6, + GP_3_15_FN, FN_IP7_5_3, + GP_3_14_FN, FN_IP7_2_0, + GP_3_13_FN, FN_IP6_31_29, + GP_3_12_FN, FN_IP6_28_26, + GP_3_11_FN, FN_IP6_25_23, + GP_3_10_FN, FN_IP6_22_20, + GP_3_9_FN, FN_IP6_19_17, + GP_3_8_FN, FN_IP6_16, + GP_3_7_FN, FN_IP6_15, + GP_3_6_FN, FN_IP6_14, + GP_3_5_FN, FN_IP6_13, + GP_3_4_FN, FN_IP6_12, + GP_3_3_FN, FN_IP6_11, + GP_3_2_FN, FN_IP6_10, + GP_3_1_FN, FN_IP6_9, + GP_3_0_FN, FN_IP6_8 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP11_17_16, + GP_4_30_FN, FN_IP11_15_14, + GP_4_29_FN, FN_IP11_13_11, + GP_4_28_FN, FN_IP11_10_8, + GP_4_27_FN, FN_IP11_7_6, + GP_4_26_FN, FN_IP11_5_3, + GP_4_25_FN, FN_IP11_2_0, + GP_4_24_FN, FN_IP10_31_30, + GP_4_23_FN, FN_IP10_29_27, + GP_4_22_FN, FN_IP10_26_24, + GP_4_21_FN, FN_IP10_23_21, + GP_4_20_FN, FN_IP10_20_18, + GP_4_19_FN, FN_IP10_17_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_30_28, + GP_4_12_FN, FN_IP9_27_25, + GP_4_11_FN, FN_IP9_24_22, + GP_4_10_FN, FN_IP9_21_19, + GP_4_9_FN, FN_IP9_18_17, + GP_4_8_FN, FN_IP9_16_15, + GP_4_7_FN, FN_IP9_14_12, + GP_4_6_FN, FN_IP9_11_9, + GP_4_5_FN, FN_IP9_8_6, + GP_4_4_FN, FN_IP9_5_3, + GP_4_3_FN, FN_IP9_2_0, + GP_4_2_FN, FN_IP8_31_29, + GP_4_1_FN, FN_IP8_28_26, + GP_4_0_FN, FN_IP8_25_23 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_27_FN, FN_USB1_OVC, + GP_5_26_FN, FN_USB1_PWEN, + GP_5_25_FN, FN_USB0_OVC, + GP_5_24_FN, FN_USB0_PWEN, + GP_5_23_FN, FN_IP13_26_24, + GP_5_22_FN, FN_IP13_23_21, + GP_5_21_FN, FN_IP13_20_18, + GP_5_20_FN, FN_IP13_17_15, + GP_5_19_FN, FN_IP13_14_12, + GP_5_18_FN, FN_IP13_11_9, + GP_5_17_FN, FN_IP13_8_6, + GP_5_16_FN, FN_IP13_5_3, + GP_5_15_FN, FN_IP13_2_0, + GP_5_14_FN, FN_IP12_29_27, + GP_5_13_FN, FN_IP12_26_24, + GP_5_12_FN, FN_IP12_23_21, + GP_5_11_FN, FN_IP12_20_18, + GP_5_10_FN, FN_IP12_17_15, + GP_5_9_FN, FN_IP12_14_13, + GP_5_8_FN, FN_IP12_12_11, + GP_5_7_FN, FN_IP12_10_9, + GP_5_6_FN, FN_IP12_8_6, + GP_5_5_FN, FN_IP12_5_3, + GP_5_4_FN, FN_IP12_2_0, + GP_5_3_FN, FN_IP11_29_27, + GP_5_2_FN, FN_IP11_26_24, + GP_5_1_FN, FN_IP11_23_21, + GP_5_0_FN, FN_IP11_20_18 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_25_FN, FN_IP0_21_20, + GP_6_24_FN, FN_IP0_19_18, + GP_6_23_FN, FN_IP0_17, + GP_6_22_FN, FN_IP0_16, + GP_6_21_FN, FN_IP0_15, + GP_6_20_FN, FN_IP0_14, + GP_6_19_FN, FN_IP0_13, + GP_6_18_FN, FN_IP0_12, + GP_6_17_FN, FN_IP0_11, + GP_6_16_FN, FN_IP0_10, + GP_6_15_FN, FN_IP0_9_8, + GP_6_14_FN, FN_IP0_0, + GP_6_13_FN, FN_SD1_DATA3, + GP_6_12_FN, FN_SD1_DATA2, + GP_6_11_FN, FN_SD1_DATA1, + GP_6_10_FN, FN_SD1_DATA0, + GP_6_9_FN, FN_SD1_CMD, + GP_6_8_FN, FN_SD1_CLK, + GP_6_7_FN, FN_SD0_WP, + GP_6_6_FN, FN_SD0_CD, + GP_6_5_FN, FN_SD0_DATA3, + GP_6_4_FN, FN_SD0_DATA2, + GP_6_3_FN, FN_SD0_DATA1, + GP_6_2_FN, FN_SD0_DATA0, + GP_6_1_FN, FN_SD0_CMD, + GP_6_0_FN, FN_SD0_CLK } + }, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 2, 2) { + /* IP6_31_29 [3] */ + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, + FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, + /* IP6_28_26 [3] */ + FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, + FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, + /* IP6_25_23 [3] */ + FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, + FN_AVB_COL, 0, 0, 0, + /* IP6_22_20 [3] */ + FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, + FN_AVB_RX_ER, 0, 0, 0, + /* IP6_19_17 [3] */ + FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, + FN_AVB_RXD7, 0, 0, 0, + /* IP6_16 [1] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, + /* IP6_15 [1] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, + /* IP6_14 [1] */ + FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, + /* IP6_13 [1] */ + FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, + /* IP6_12 [1] */ + FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, + /* IP6_11 [1] */ + FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, + /* IP6_10 [1] */ + FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, + /* IP6_9 [1] */ + FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, + /* IP6_8 [1] */ + FN_VI0_CLK, FN_AVB_RX_CLK, + /* IP6_7_6 [2] */ + FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, + /* IP6_5_4 [2] */ + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, + /* IP6_3_2 [2] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + /* IP6_1_0 [2] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP7_31 [1] */ + FN_DREQ0_N, FN_SCIFB1_RXD, + /* IP7_30 [1] */ + 0, 0, + /* IP7_29_27 [3] */ + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, + FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, + /* IP7_26_24 [3] */ + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, + FN_SSI_SCK6_B, 0, 0, 0, + /* IP7_23_21 [3] */ + FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, + FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, + /* IP7_20_18 [3] */ + FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, + FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, + /* IP7_17_15 [3] */ + FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, + FN_SSI_SCK5_B, 0, 0, 0, + /* IP7_14_12 [3] */ + FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, 0, 0, + /* IP7_11_9 [3] */ + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, + FN_AVB_TXD3, FN_ADICHS1, 0, 0, + /* IP7_8_6 [3] */ + FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, + FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, + /* IP7_5_3 [3] */ + FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, + FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, + /* IP7_2_0 [3] */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, + FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { + /* IP8_31_29 [3] */ + FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, + FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + /* IP8_28_26 [3] */ + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, + FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, + /* IP8_25_23 [3] */ + FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, + FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, + /* IP8_22_20 [3] */ + FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, + FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, + /* IP8_19_17 [3] */ + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, + FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, + /* IP8_16_15 [2] */ + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + /* IP8_14_12 [3] */ + FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, + FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, + /* IP8_11_9 [3] */ + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, + /* IP8_8_6 [3] */ + FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, + FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, + /* IP8_5_3 [3] */ + FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, + FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, + /* IP8_2_0 [3] */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, + FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } + }, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { + /* IP11_31_30 [2] */ + 0, 0, 0, 0, + /* IP11_29_27 [3] */ + FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, + FN_AD_CLK_B, 0, 0, 0, + /* IP11_26_24 [3] */ + FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, + FN_AD_DO_B, 0, 0, 0, + /* IP11_23_21 [3] */ + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, 0, 0, + /* IP11_20_18 [3] */ + FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, + FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, + /* IP11_17_16 [2] */ + FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, + /* IP11_15_14 [2] */ + FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, + /* IP11_13_11 [3] */ + FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, + /* IP11_10_8 [3] */ + FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, + FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, + /* IP11_7_6 [2] */ + FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_CAN_DEBUGOUT13, + /* IP11_5_3 [3] */ + FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, + FN_CAN_DEBUGOUT12, 0, 0, 0, + /* IP11_2_0 [3] */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, 0, 0, 0, } + }, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, + 2, 1) { + /* SEL_ADG [2] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_CAN [2] */ + FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, + /* SEL_DARC [3] */ + FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, + FN_SEL_DARC_4, 0, 0, 0, + /* SEL_DR0 [1] */ + FN_SEL_DR0_0, FN_SEL_DR0_1, + /* SEL_DR1 [1] */ + FN_SEL_DR1_0, FN_SEL_DR1_1, + /* SEL_DR2 [1] */ + FN_SEL_DR2_0, FN_SEL_DR2_1, + /* SEL_DR3 [1] */ + FN_SEL_DR3_0, FN_SEL_DR3_1, + /* SEL_ETH [1] */ + FN_SEL_ETH_0, FN_SEL_ETH_1, + /* SLE_FSN [1] */ + FN_SEL_FSN_0, FN_SEL_FSN_1, + /* SEL_IC200 [3] */ + FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, + FN_SEL_I2C00_4, 0, 0, 0, + /* SEL_I2C01 [3] */ + FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, + FN_SEL_I2C01_4, 0, 0, 0, + /* SEL_I2C02 [3] */ + FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, + FN_SEL_I2C02_4, 0, 0, 0, + /* SEL_I2C03 [3] */ + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, 0, 0, 0, + /* SEL_I2C04 [3] */ + FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, + FN_SEL_I2C04_4, 0, 0, 0, + /* SEL_IIC00 [2] */ + FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, + /* SEL_AVB [1] */ + FN_SEL_AVB_0, FN_SEL_AVB_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, + 2, 2, 2, 1, 1, 2) { + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_MSI1 [1] */ + FN_SEL_MSI1_0, FN_SEL_MSI1_1, + /* SEL_MSI2 [1] */ + FN_SEL_MSI2_0, FN_SEL_MSI2_1, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIFA0 [2] */ + FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, + FN_SEL_SCIFA0_3, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIFA3 [1] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA4_3, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_SCIFA5_3, + /* SEL_SPDM [1] */ + FN_SEL_SPDM_0, FN_SEL_SPDM_1, + /* SEL_TMU [1] */ + FN_SEL_TMU_0, FN_SEL_TMU_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* SEL_HSCIF0 [1] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_RDS [2] */ + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + /* SEL_SCIF0 [2] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, + /* SEL_SCIF2 [2] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, + /* SEL_SCIF3 [1] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + /* SEL_SCIF4 [3] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, 0, 0, 0, + /* SEL_SCIF5 [2] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI2 [1] */ + FN_SEL_SSI2_0, FN_SEL_SSI2_1, + /* SEL_SSI4 [1] */ + FN_SEL_SSI4_0, FN_SEL_SSI4_1, + /* SEL_SSI5 [1] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_27_IN, GP_5_27_OUT, + GP_5_26_IN, GP_5_26_OUT, + GP_5_25_IN, GP_5_25_OUT, + GP_5_24_IN, GP_5_24_OUT, + GP_5_23_IN, GP_5_23_OUT, + GP_5_22_IN, GP_5_22_OUT, + GP_5_21_IN, GP_5_21_OUT, + GP_5_20_IN, GP_5_20_OUT, + GP_5_19_IN, GP_5_19_OUT, + GP_5_18_IN, GP_5_18_OUT, + GP_5_17_IN, GP_5_17_OUT, + GP_5_16_IN, GP_5_16_OUT, + GP_5_15_IN, GP_5_15_OUT, + GP_5_14_IN, GP_5_14_OUT, + GP_5_13_IN, GP_5_13_OUT, + GP_5_12_IN, GP_5_12_OUT, + GP_5_11_IN, GP_5_11_OUT, + GP_5_10_IN, GP_5_10_OUT, + GP_5_9_IN, GP_5_9_OUT, + GP_5_8_IN, GP_5_8_OUT, + GP_5_7_IN, GP_5_7_OUT, + GP_5_6_IN, GP_5_6_OUT, + GP_5_5_IN, GP_5_5_OUT, + GP_5_4_IN, GP_5_4_OUT, + GP_5_3_IN, GP_5_3_OUT, + GP_5_2_IN, GP_5_2_OUT, + GP_5_1_IN, GP_5_1_OUT, + GP_5_0_IN, GP_5_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_25_IN, GP_6_25_OUT, + GP_6_24_IN, GP_6_24_OUT, + GP_6_23_IN, GP_6_23_OUT, + GP_6_22_IN, GP_6_22_OUT, + GP_6_21_IN, GP_6_21_OUT, + GP_6_20_IN, GP_6_20_OUT, + GP_6_19_IN, GP_6_19_OUT, + GP_6_18_IN, GP_6_18_OUT, + GP_6_17_IN, GP_6_17_OUT, + GP_6_16_IN, GP_6_16_OUT, + GP_6_15_IN, GP_6_15_OUT, + GP_6_14_IN, GP_6_14_OUT, + GP_6_13_IN, GP_6_13_OUT, + GP_6_12_IN, GP_6_12_OUT, + GP_6_11_IN, GP_6_11_OUT, + GP_6_10_IN, GP_6_10_OUT, + GP_6_9_IN, GP_6_9_OUT, + GP_6_8_IN, GP_6_8_OUT, + GP_6_7_IN, GP_6_7_OUT, + GP_6_6_IN, GP_6_6_OUT, + GP_6_5_IN, GP_6_5_OUT, + GP_6_4_IN, GP_6_4_OUT, + GP_6_3_IN, GP_6_3_OUT, + GP_6_2_IN, GP_6_2_OUT, + GP_6_1_IN, GP_6_1_OUT, + GP_6_0_IN, GP_6_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + 0, 0, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { + 0, 0, 0, 0, + GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA, + GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, + GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, + GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, + GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, + GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, + GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } + }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { + 0, 0, 0, 0, + 0, 0, GP_6_25_DATA, GP_6_24_DATA, + GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA, + GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA, + GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA, + GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA, + GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA, + GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7794_pinmux_info = { + .name = "r8a7794_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_AD_CLK_B, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7794_pinmux_init(void) +{ + register_pinmux(&r8a7794_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/cpu/armv7/rmobile/timer.c index 72e0c12545..04700e7d34 100644 --- a/arch/arm/cpu/armv7/rmobile/timer.c +++ b/arch/arm/cpu/armv7/rmobile/timer.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -38,13 +39,16 @@ static u64 get_time_us(void) u64 timer = get_cpu_global_timer(); timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); - timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK); + do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); return timer; } static ulong get_time_ms(void) { - return (ulong)(get_time_us() / 1000); + u64 us = get_time_us(); + + do_div(us, 1000); + return us; } int timer_init(void) diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index fd7290caa3..f571d8a0e0 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -5,30 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libs5p-common.o - -COBJS-y += cpu_info.o +obj-y += cpu_info.o ifndef CONFIG_SPL_BUILD -COBJS-y += timer.o -COBJS-y += sromc.o -COBJS-$(CONFIG_PWM) += pwm.o +obj-y += timer.o +obj-y += sromc.o +obj-$(CONFIG_PWM) += pwm.o endif - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 47aa9cccbf..b8805c8d43 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -3,7 +3,7 @@ * * Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 5b87a081c8..949abb1c8f 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -4,7 +4,7 @@ * Inki Dae * Minkyu Kang * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig new file mode 100644 index 0000000000..628813423f --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -0,0 +1,22 @@ +if ARCH_S5PC1XX + +choice + prompt "S5PC1XX board select" + +config TARGET_S5P_GONI + bool "S5P Goni board" + select OF_CONTROL if !SPL_BUILD + +config TARGET_SMDKC100 + bool "Support smdkc100 board" + select OF_CONTROL if !SPL_BUILD + +endchoice + +config SYS_SOC + default "s5pc1xx" + +source "board/samsung/goni/Kconfig" +source "board/samsung/smdkc100/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile index 09fed66bfd..9f43ded1d9 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Makefile +++ b/arch/arm/cpu/armv7/s5pc1xx/Makefile @@ -8,28 +8,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y = cache.o +obj-y += reset.o -LIB = $(obj)lib$(SOC).o - -SOBJS = cache.o -SOBJS += reset.o - -COBJS += clock.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += clock.o diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S deleted file mode 100644 index 3089592eb1..0000000000 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Minkyu Kang - * - * based on arch/arm/cpu/armv7/omap3/cache.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.align 5 - -#include - -#ifndef CONFIG_SYS_L2CACHE_OFF -ENTRY(v7_outer_cache_enable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_enable) - -ENTRY(v7_outer_cache_disable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_disable) -#endif diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/cpu/armv7/s5pc1xx/cache.c new file mode 100644 index 0000000000..51af2990c2 --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Minkyu Kang + * Robert Baldyga + * + * based on arch/arm/cpu/armv7/omap3/cache.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + dcache_enable(); +} + +void disable_caches(void) +{ + dcache_disable(); +} +#endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "orr r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} + +void v7_outer_cache_disable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "bic r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} +#endif diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3b48ac9b2b..8b6e108c42 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -7,29 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS := lowlevel_init.o -COBJS-y := misc.o timer.o -COBJS-$(CONFIG_SPL_BUILD) += spl.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := lowlevel_init.o +obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ + fpga_manager.o +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c new file mode 100644 index 0000000000..fa3b93a257 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -0,0 +1,560 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; + +static void cm_wait_for_lock(uint32_t mask) +{ + register uint32_t inter_val; + uint32_t retry = 0; + do { + inter_val = readl(&clock_manager_base->inter) & mask; + if (inter_val == mask) + retry++; + else + retry = 0; + if (retry >= 10) + break; + } while (1); +} + +/* function to poll in the fsm busy bit */ +static void cm_wait_for_fsm(void) +{ + while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) + ; +} + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void cm_write_bypass(uint32_t val) +{ + writel(val, &clock_manager_base->bypass); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static void cm_write_ctrl(uint32_t val) +{ + writel(val, &clock_manager_base->ctrl); + cm_wait_for_fsm(); +} + +/* function to write a clock register that has phase information */ +static void cm_write_with_phase(uint32_t value, + uint32_t reg_address, uint32_t mask) +{ + /* poll until phase is zero */ + while (readl(reg_address) & mask) + ; + + writel(value, reg_address); + + while (readl(reg_address) & mask) + ; +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + * + * Start by being paranoid and gate all sw managed clocks + * Put all plls in bypass + * Put all plls VCO registers back to reset value (bandgap power down). + * Put peripheral and main pll src to reset value to avoid glitch. + * Delay 5 us. + * Deassert bandgap power down and set numerator and denominator + * Start 7 us timer. + * set internal dividers + * Wait for 7 us timer. + * Enable plls + * Set external dividers while plls are locking + * Wait for pll lock + * Assert/deassert outreset all. + * Take all pll's out of bypass + * Clear safe mode + * set source main and peripheral clocks + * Ungate clocks + */ + +void cm_basic_init(const cm_config_t *cfg) +{ + uint32_t start, timeout; + + /* Start by being paranoid and gate all sw managed clocks */ + + /* + * We need to disable nandclk + * and then do another apb access before disabling + * gatting off the rest of the periperal clocks. + */ + writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & + readl(&clock_manager_base->per_pll.en), + &clock_manager_base->per_pll.en); + + /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ + writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | + CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | + CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, + &clock_manager_base->main_pll.en); + + writel(0, &clock_manager_base->sdr_pll.en); + + /* now we can gate off the rest of the peripheral clocks */ + writel(0, &clock_manager_base->per_pll.en); + + /* Put all plls in bypass */ + cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | + CLKMGR_BYPASS_MAINPLL); + + /* Put all plls VCO registers back to reset value. */ + writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->main_pll.vco); + writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->per_pll.vco); + writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->sdr_pll.vco); + + /* + * The clocks to the flash devices and the L4_MAIN clocks can + * glitch when coming out of safe mode if their source values + * are different from their reset value. So the trick it to + * put them back to their reset state, and change input + * after exiting safe mode but before ungating the clocks. + */ + writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, + &clock_manager_base->per_pll.src); + writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, + &clock_manager_base->main_pll.l4src); + + /* read back for the required 5 us delay. */ + readl(&clock_manager_base->main_pll.vco); + readl(&clock_manager_base->per_pll.vco); + readl(&clock_manager_base->sdr_pll.vco); + + + /* + * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN + * with numerator and denominator. + */ + writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); + writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); + writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); + + /* + * Time starts here + * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) + */ + start = get_timer(0); + /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ + timeout = 7; + + /* main mpu */ + writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); + + /* main main clock */ + writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); + + /* main for dbg */ + writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); + + /* main for cfgs2fuser0clk */ + writel(cfg->cfg2fuser0clk, + &clock_manager_base->main_pll.cfgs2fuser0clk); + + /* Peri emac0 50 MHz default to RMII */ + writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); + + /* Peri emac1 50 MHz default to RMII */ + writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); + + /* Peri QSPI */ + writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); + + writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); + + /* Peri pernandsdmmcclk */ + writel(cfg->mainnandsdmmcclk, + &clock_manager_base->main_pll.mainnandsdmmcclk); + + writel(cfg->pernandsdmmcclk, + &clock_manager_base->per_pll.pernandsdmmcclk); + + /* Peri perbaseclk */ + writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); + + /* Peri s2fuser1clk */ + writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); + + /* 7 us must have elapsed before we can enable the VCO */ + while (get_timer(start) < timeout) + ; + + /* Enable vco */ + /* main pll vco */ + writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->main_pll.vco); + + /* periferal pll */ + writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->per_pll.vco); + + /* sdram pll vco */ + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->sdr_pll.vco); + + /* L3 MP and L3 SP */ + writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); + + writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); + + writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); + + /* L4 MP, L4 SP, can0, and can1 */ + writel(cfg->perdiv, &clock_manager_base->per_pll.div); + + writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); + +#define LOCKED_MASK \ + (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ + CLKMGR_INTER_PERPLLLOCKED_MASK | \ + CLKMGR_INTER_MAINPLLLOCKED_MASK) + + cm_wait_for_lock(LOCKED_MASK); + + /* write the sdram clock counters before toggling outreset all */ + writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, + &clock_manager_base->sdr_pll.ddrdqsclk); + + writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, + &clock_manager_base->sdr_pll.ddr2xdqsclk); + + writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, + &clock_manager_base->sdr_pll.ddrdqclk); + + writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, + &clock_manager_base->sdr_pll.s2fuser2clk); + + /* + * after locking, but before taking out of bypass + * assert/deassert outresetall + */ + uint32_t mainvco = readl(&clock_manager_base->main_pll.vco); + + /* assert main outresetall */ + writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->main_pll.vco); + + uint32_t periphvco = readl(&clock_manager_base->per_pll.vco); + + /* assert pheriph outresetall */ + writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->per_pll.vco); + + /* assert sdram outresetall */ + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, + &clock_manager_base->sdr_pll.vco); + + /* deassert main outresetall */ + writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->main_pll.vco); + + /* deassert pheriph outresetall */ + writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->per_pll.vco); + + /* deassert sdram outresetall */ + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->sdr_pll.vco); + + /* + * now that we've toggled outreset all, all the clocks + * are aligned nicely; so we can change any phase. + */ + cm_write_with_phase(cfg->ddrdqsclk, + (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk, + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); + + /* SDRAM DDR2XDQSCLK */ + cm_write_with_phase(cfg->ddr2xdqsclk, + (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk, + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); + + cm_write_with_phase(cfg->ddrdqclk, + (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk, + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); + + cm_write_with_phase(cfg->s2fuser2clk, + (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk, + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); + + /* Take all three PLLs out of bypass when safe mode is cleared. */ + cm_write_bypass(0); + + /* clear safe mode */ + cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); + + /* + * now that safe mode is clear with clocks gated + * it safe to change the source mux for the flashes the the L4_MAIN + */ + writel(cfg->persrc, &clock_manager_base->per_pll.src); + writel(cfg->l4src, &clock_manager_base->main_pll.l4src); + + /* Now ungate non-hw-managed clocks */ + writel(~0, &clock_manager_base->main_pll.en); + writel(~0, &clock_manager_base->per_pll.en); + writel(~0, &clock_manager_base->sdr_pll.en); + + /* Clear the loss of lock bits (write 1 to clear) */ + writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK, + &clock_manager_base->inter); +} + +static unsigned int cm_get_main_vco_clk_hz(void) +{ + uint32_t reg, clock; + + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ; + clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1; + + return clock; +} + +static unsigned int cm_get_per_vco_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> + CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1; + + return clock; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + uint32_t reg, clock; + + clock = cm_get_main_vco_clk_hz(); + + /* get the MPU clock */ + reg = readl(&clock_manager_base->altera.mpuclk); + clock /= (reg + 1); + reg = readl(&clock_manager_base->main_pll.mpuclk); + clock /= (reg + 1); + return clock; +} + +unsigned long cm_get_sdram_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify SDRAM PLL clock source */ + reg = readl(&clock_manager_base->sdr_pll.vco); + reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ; + + /* get the SDRAM VCO clock */ + reg = readl(&clock_manager_base->sdr_pll.vco); + clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; + + /* get the SDRAM (DDR_DQS) clock */ + reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); + reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; + clock /= (reg + 1); + + return clock; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of L4 SP clock */ + reg = readl(&clock_manager_base->main_pll.l4src); + reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; + + if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { + clock = cm_get_main_vco_clk_hz(); + + /* get the clock prior L4 SP divider (main clk) */ + reg = readl(&clock_manager_base->altera.mainclk); + clock /= (reg + 1); + reg = readl(&clock_manager_base->main_pll.mainclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { + clock = cm_get_per_vco_clk_hz(); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + } + + /* get the L4 SP clock which supplied to UART */ + reg = readl(&clock_manager_base->main_pll.maindiv); + reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; + clock = clock / (1 << reg); + + return clock; +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of MMC clock */ + reg = readl(&clock_manager_base->per_pll.src); + reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; + + if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { + clock = cm_get_main_vco_clk_hz(); + + /* get the SDMMC clock */ + reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { + clock = cm_get_per_vco_clk_hz(); + + /* get the SDMMC clock */ + reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); + clock /= (reg + 1); + } + + /* further divide by 4 as we have fixed divider at wrapper */ + clock /= 4; + return clock; +} + +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of QSPI clock */ + reg = readl(&clock_manager_base->per_pll.src); + reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; + + if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { + clock = cm_get_main_vco_clk_hz(); + + /* get the qspi clock */ + reg = readl(&clock_manager_base->main_pll.mainqspiclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { + clock = cm_get_per_vco_clk_hz(); + + /* get the qspi clock */ + reg = readl(&clock_manager_base->per_pll.perqspiclk); + clock /= (reg + 1); + } + + return clock; +} + +unsigned int cm_get_spi_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + clock = cm_get_per_vco_clk_hz(); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + + return clock; +} + +static void cm_print_clock_quick_summary(void) +{ + printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); + printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000); + printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000); + printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000); + printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000); + printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000); + printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); + printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); +} + +int set_cpu_clk_info(void) +{ + /* Calculate the clock frequencies required for drivers */ + cm_get_l4_sp_clk_hz(); + cm_get_mmc_controller_clk_hz(); + + gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; + gd->bd->bi_dsp_freq = 0; + gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; + + return 0; +} + +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cm_print_clock_quick_summary(); + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk index d33ab7d62f..2a99c72aeb 100644 --- a/arch/arm/cpu/armv7/socfpga/config.mk +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -4,5 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # ifndef CONFIG_SPL_BUILD -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif + +# Added for handoff support +PLATFORM_RELFLAGS += -Iboard/$(VENDOR)/$(BOARD) diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c b/arch/arm/cpu/armv7/socfpga/fpga_manager.c new file mode 100644 index 0000000000..43fd2fedee --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/fpga_manager.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * This file contains only support functions used also by the SoCFPGA + * platform code, the real meat is located in drivers/fpga/socfpga.c . + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Timeout count */ +#define FPGA_TIMEOUT_CNT 0x1000000 + +static struct socfpga_fpga_manager *fpgamgr_regs = + (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; + +/* Check whether FPGA Init_Done signal is high */ +static int is_fpgamgr_initdone_high(void) +{ + unsigned long val; + + val = readl(&fpgamgr_regs->gpio_ext_porta); + return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK; +} + +/* Get the FPGA mode */ +int fpgamgr_get_mode(void) +{ + unsigned long val; + + val = readl(&fpgamgr_regs->stat); + return val & FPGAMGRREGS_STAT_MODE_MASK; +} + +/* Check whether FPGA is ready to be accessed */ +int fpgamgr_test_fpga_ready(void) +{ + /* Check for init done signal */ + if (!is_fpgamgr_initdone_high()) + return 0; + + /* Check again to avoid false glitches */ + if (!is_fpgamgr_initdone_high()) + return 0; + + if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE) + return 0; + + return 1; +} + +/* Poll until FPGA is ready to be accessed or timeout occurred */ +int fpgamgr_poll_fpga_ready(void) +{ + unsigned long i; + + /* If FPGA is blank, wait till WD invoke warm reset */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + /* check for init done signal */ + if (!is_fpgamgr_initdone_high()) + continue; + /* check again to avoid false glitches */ + if (!is_fpgamgr_initdone_high()) + continue; + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c new file mode 100644 index 0000000000..0be643c817 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Default state from cold reset is FREEZE_ALL; the global + * flag is set to TRUE to indicate the IO banks are frozen + */ +static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM] + = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN, + FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN}; + +/* Freeze HPS IOs */ +void sys_mgr_frzctrl_freeze_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_value; + u32 reg_cfg_mask; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Freeze channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset = (u32)( + &freeze_controller_base->vioctrl + channel_id); + + /* + * Assert active low enrnsl, plniotri + * and niotri signals + */ + reg_cfg_mask = + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * Assert active low bhniotri signal and de-assert + * active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; + } + + /* Freeze channel 3 */ + /* + * Assert active low enrnsl, plniotri and + * niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * assert active low bhniotri & nfrzdrv signals, + * de-assert active high csrdone and assert + * active high frzreg and nfrzdrv signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK; + reg_value + = (reg_value & ~reg_cfg_mask) + | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK + | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * assert active high reinit signal and de-assert + * active high pllbiasen signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value + = (reg_value & + ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK) + | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; +} + +/* Unfreeze/Thaw HPS IOs */ +void sys_mgr_frzctrl_thaw_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_cfg_mask; + u32 reg_value; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Thaw channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset + = (u32)(&freeze_controller_base->vioctrl + channel_id); + + /* + * Assert active low bhniotri signal and + * de-assert active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low plniotri and niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(ioctrl_reg_offset, + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; + } + + /* Thaw channel 3 */ + /* de-assert active high reinit signal */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Note: Delay for 40ns at min + * assert active high pllbiasen signals + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); + + /* + * Delay 1000 intosc. intosc is based on eosc1 + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 1000 = 20us + */ + udelay(20); + + /* + * de-assert active low bhniotri signals, + * assert active high csrdone and nfrzdrv signal + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value = (reg_value + | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK) + & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * Delay 33 intosc + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 33 = 660ns ~= 1us + */ + udelay(1); + + /* de-assert active low plniotri and niotri signals */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + + setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * Note: Delay for 40ns at min + * de-assert active high frzreg signal + */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK); + + /* + * Note: Delay for 40ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; +} diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S index 1caaa2759f..afed773c63 100644 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -7,26 +7,6 @@ #include #include -/* Save the parameter pass in by previous boot loader */ -.global save_boot_params -save_boot_params: - /* save the parameter here */ - - /* - * Setup stack for exception, which is located - * at the end of on-chip RAM. We don't expect exception prior to - * relocation and if that happens, we won't worry -- it will overide - * global data region as the code will goto reset. After relocation, - * this region won't be used by other part of program. - * Hence it is safe. - */ - ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) - ldr r1, =IRQ_STACK_START_IN - str r0, [r1] - - bx lr - - /* Set up the platform, once the cpu has been initialized */ .globl lowlevel_init lowlevel_init: diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 66edb3c20f..7873c38e2b 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -6,38 +6,284 @@ #include #include +#include +#include +#include +#include #include +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; +static struct nic301_registers *nic301_regs = + (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; +static struct scu_registers *scu_regs = + (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + return 0; +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} /* - * Write the reset manager register to cause reset + * DesignWare Ethernet initialization */ -void reset_cpu(ulong addr) +#ifdef CONFIG_DESIGNWARE_ETH +int cpu_eth_init(bd_t *bis) { - /* request a warm reset */ - writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); +#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS + const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; +#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS + const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; +#else +#error "Incorrect CONFIG_EMAC_BASE value!" +#endif + + /* Initialize EMAC. This needs to be done at least once per boot. */ + /* - * infinite loop here as watchdog will trigger and reset - * the processor + * Putting the EMAC controller to reset when configuring the PHY + * interface select at System Manager */ - while (1) - ; + socfpga_emac_reset(1); + + /* Clearing emac0 PHY interface select to 0 */ + clrbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); + + /* configure to PHY interface select choosed */ + setbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); + + /* Release the EMAC controller from reset */ + socfpga_emac_reset(0); + + /* initialize and register the emac */ + return designware_initialize(CONFIG_EMAC_BASE, + CONFIG_PHY_INTERFACE_MODE); } +#endif +#ifdef CONFIG_DWMMC /* - * Release peripherals from reset based on handoff + * Initializes MMC controllers. + * to override, implement board_mmc_init() */ -void reset_deassert_peripherals_handoff(void) +int cpu_mmc_init(bd_t *bis) { - writel(0, &reset_manager_base->per_mod_reset); + return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, + CONFIG_HPS_SDMMC_BUSWIDTH, 0); } +#endif -int dram_init(void) +#if defined(CONFIG_DISPLAY_CPUINFO) +/* + * Print CPU information + */ +int print_cpuinfo(void) { - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + puts("CPU: Altera SoCFPGA Platform\n"); + return 0; +} +#endif + +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ +defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_FPGA +/* + * FPGA programming support for SoC FPGA Cyclone V + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_SoCFPGA, + /* Interface type */ + fast_passive_parallel, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + +/* add device descriptor to FPGA device table */ +static void socfpga_fpga_add(void) +{ + int i; + fpga_init(); + for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) + fpga_add(fpga_altera, &altera_fpga[i]); +} +#else +static inline void socfpga_fpga_add(void) {} +#endif + +int arch_cpu_init(void) +{ +#ifdef CONFIG_HW_WATCHDOG + /* + * In case the watchdog is enabled, make sure to (re-)configure it + * so that the defined timeout is valid. Otherwise the SPL (Perloader) + * timeout value is still active which might too short for Linux + * booting. + */ + hw_watchdog_init(); +#else + /* + * If the HW watchdog is NOT enabled, make sure it is not running, + * for example because it was enabled in the preloader. This might + * trigger a watchdog-triggered reboot of Linux kernel later. + */ + socfpga_watchdog_reset(); +#endif + return 0; } + +/* + * Convert all NIC-301 AMBA slaves from secure to non-secure + */ +static void socfpga_nic301_slave_ns(void) +{ + writel(0x1, &nic301_regs->lwhps2fpgaregs); + writel(0x1, &nic301_regs->hps2fpgaregs); + writel(0x1, &nic301_regs->acp); + writel(0x1, &nic301_regs->rom); + writel(0x1, &nic301_regs->ocram); + writel(0x1, &nic301_regs->sdrdata); +} + +static uint32_t iswgrp_handoff[8]; + +int arch_early_init_r(void) +{ + int i; + for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ + iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); + + socfpga_bridges_reset(1); + socfpga_nic301_slave_ns(); + + /* + * Private components security: + * U-Boot : configure private timer, global timer and cpu component + * access as non secure for kernel stage (as required by Linux) + */ + setbits_le32(&scu_regs->sacr, 0xfff); + + /* Configure the L2 controller to make SDRAM start at 0 */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET + writel(0x2, &nic301_regs->remap); +#else + writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + writel(0x1, &pl310->pl310_addr_filter_start); +#endif + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_spim_enable(); +#endif + + return 0; +} + +static void socfpga_sdram_apply_static_cfg(void) +{ + const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; + const uint32_t applymask = 0x8; + uint32_t val = readl(staticcfg) | applymask; + + /* + * SDRAM staticcfg register specific: + * When applying the register setting, the CPU must not access + * SDRAM. Luckily for us, we can abuse i-cache here to help us + * circumvent the SDRAM access issue. The idea is to make sure + * that the code is in one full i-cache line by branching past + * it and back. Once it is in the i-cache, we execute the core + * of the code and apply the register settings. + * + * The code below uses 7 instructions, while the Cortex-A9 has + * 32-byte cachelines, thus the limit is 8 instructions total. + */ + asm volatile( + ".align 5 \n" + " b 2f \n" + "1: str %0, [%1] \n" + " dsb \n" + " isb \n" + " b 3f \n" + "2: b 1b \n" + "3: nop \n" + : : "r"(val), "r"(staticcfg) : "memory", "cc"); +} + +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ + writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); + socfpga_sdram_apply_static_cfg(); + writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[1], &nic301_regs->remap); + break; + case 'd': /* Disable */ + writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); + socfpga_sdram_apply_static_cfg(); + writel(0, &reset_manager_base->brg_mod_reset); + writel(1, &nic301_regs->remap); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +); diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c new file mode 100644 index 0000000000..25921e76c4 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */ +void socfpga_watchdog_reset(void) +{ + /* assert reset for watchdog */ + setbits_le32(&reset_manager_base->per_mod_reset, + 1 << RSTMGR_PERMODRST_L4WD0_LSB); + + /* deassert watchdog from reset (watchdog in not running state) */ + clrbits_le32(&reset_manager_base->per_mod_reset, + 1 << RSTMGR_PERMODRST_L4WD0_LSB); +} + +/* + * Write the reset manager register to cause reset + */ +void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), + &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +void socfpga_bridges_reset(int enable) +{ + /* For SoCFPGA-VT, this is NOP. */ +} +#else + +#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 +#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 +#define L3REGS_REMAP_OCRAM_MASK 0x01 + +void socfpga_bridges_reset(int enable) +{ + const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | + L3REGS_REMAP_HPS2FPGA_MASK | + L3REGS_REMAP_OCRAM_MASK; + + if (enable) { + /* brdmodrst */ + writel(0xffffffff, &reset_manager_base->brg_mod_reset); + } else { + /* Check signal from FPGA. */ + if (fpgamgr_poll_fpga_ready()) { + /* FPGA not ready. Wait for watchdog timeout. */ + printf("%s: fpga not ready, hanging.\n", __func__); + hang(); + } + + /* brdmodrst */ + writel(0, &reset_manager_base->brg_mod_reset); + + /* Remap the bridges into memory map */ + writel(l3mask, SOCFPGA_L3REGS_ADDRESS); + } +} +#endif + +/* Change the reset state for EMAC 0 and EMAC 1 */ +void socfpga_emac_reset(int enable) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + if (enable) { + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); + } else { +#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS) + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); +#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS) + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); +#endif + } +} + +/* SPI Master enable (its held in reset by the preloader) */ +void socfpga_spim_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | + (1 << RSTMGR_PERMODRST_SPIM1_LSB)); +} diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c new file mode 100644 index 0000000000..a820b1b1bf --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_scan_manager *scan_manager_base = + (void *)(SOCFPGA_SCANMGR_ADDRESS); +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Function to check IO scan chain engine status and wait if the engine is + * is active. Poll the IO scan chain engine till maximum iteration reached. + */ +static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter) +{ + uint32_t scanmgr_status; + + scanmgr_status = readl(&scan_manager_base->stat); + + /* Poll the engine until the scan engine is inactive */ + while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) || + (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) { + max_iter--; + if (max_iter > 0) + scanmgr_status = readl(&scan_manager_base->stat); + else + return 0; + } + return 1; +} + +/* Program HPS IO Scan Chain */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain) +{ + uint16_t tdi_tdo_header; + uint32_t io_program_iter; + uint32_t io_scan_chain_data_residual; + uint32_t residual; + uint32_t i; + uint32_t index = 0; + + /* + * De-assert reinit if the IO scan chain is intended for HIO. In + * this, its the chain 3. + */ + if (io_scan_chain_id == 3) + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Check if the scan chain engine is inactive and the + * WFIFO is empty before enabling the IO scan chain + */ + if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY)) + return 1; + + /* + * Enable IO Scan chain based on scan chain id + * Note: only one chain can be enabled at a time + */ + setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + + /* + * Calculate number of iteration needed for full 128-bit (4 x32-bits) + * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits + */ + io_program_iter = io_scan_chain_len_in_bits >> + IO_SCAN_CHAIN_128BIT_SHIFT; + io_scan_chain_data_residual = io_scan_chain_len_in_bits & + IO_SCAN_CHAIN_128BIT_MASK; + + /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + (TDI_TDO_MAX_PAYLOAD << TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* Program IO scan chain in 128-bit iteration */ + for (i = 0; i < io_program_iter; i++) { + /* write TDI_TDO packet header to scan manager */ + writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte); + + /* calculate array index. Multiply by 4 as write 4 x 32bits */ + index = i * 4; + + /* write 4 successive 32-bit IO scan chain data into WFIFO */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 1], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 2], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 3], + &scan_manager_base->fifo_quad_byte); + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY)) + goto error; + } + + /* Calculate array index for final TDI_TDO packet */ + index = io_program_iter * 4; + + /* Final TDI_TDO packet if any */ + if (io_scan_chain_data_residual) { + /* + * Calculate number of quad bytes FIFO write + * needed for the final TDI_TDO packet + */ + io_program_iter = io_scan_chain_data_residual >> + IO_SCAN_CHAIN_32BIT_SHIFT; + + /* + * Construct TDI_TDO packet for remaining IO + * scan chain (2 bytes) + */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + ((io_scan_chain_data_residual - 1) << + TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* + * Program the last part of IO scan chain write TDI_TDO packet + * header (2 bytes) to scan manager + */ + writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte); + + for (i = 0; i < io_program_iter; i++) { + /* + * write remaining scan chain data into scan + * manager WFIFO with 4 bytes write + */ + writel(iocsr_scan_chain[index + i], + &scan_manager_base->fifo_quad_byte); + } + + index += io_program_iter; + residual = io_scan_chain_data_residual & + IO_SCAN_CHAIN_32BIT_MASK; + + if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) { + /* + * write the last 4B scan chain data + * into scan manager WFIFO + */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifo_quad_byte); + } else { + /* + * write the remaining 1 - 3 bytes scan chain + * data into scan manager WFIFO byte by byte + * to prevent JTAG engine shifting unused data + * from the FIFO and mistaken the data as a + * valid command (even though unused bits are + * set to 0, but just to prevent hardware + * glitch) + */ + for (i = 0; i < residual; i += 8) { + writel(((iocsr_scan_chain[index] >> i) + & IO_SCAN_CHAIN_BYTE_MASK), + &scan_manager_base->fifo_single_byte); + } + } + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY)) + goto error; + } + + /* Disable IO Scan chain when configuration done*/ + clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + return 0; + +error: + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + return 1; +} + +int scan_mgr_configure_iocsr(void) +{ + int status = 0; + + /* configure the IOCSR through scan chain */ + status |= scan_mgr_io_scan_chain_prg(0, + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table); + status |= scan_mgr_io_scan_chain_prg(1, + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table); + status |= scan_mgr_io_scan_chain_prg(2, + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table); + status |= scan_mgr_io_scan_chain_prg(3, + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table); + return status; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 2b9be28c21..bd9f338301 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -12,9 +12,38 @@ #include #include #include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; +#define MAIN_VCO_BASE ( \ + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \ + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \ + ) + +#define PERI_VCO_BASE ( \ + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \ + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \ + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \ + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \ + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \ + ) + +#define SDR_VCO_BASE ( \ + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \ + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \ + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \ + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \ + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ + ) + u32 spl_boot_device(void) { return BOOT_DEVICE_RAM; @@ -25,9 +54,116 @@ u32 spl_boot_device(void) */ void spl_board_init(void) { +#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + cm_config_t cm_default_cfg = { + /* main group */ + MAIN_VCO_BASE, + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT << + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT << + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT << + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT << + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT << + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT << + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK << + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK << + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK << + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP << + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP << + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET), + + /* peripheral group */ + PERI_VCO_BASE, + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT << + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT << + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT << + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT << + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT << + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT << + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK << + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK << + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK << + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK << + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET), + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK << + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET), + (CONFIG_HPS_PERPLLGRP_SRC_QSPI << + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) | + (CONFIG_HPS_PERPLLGRP_SRC_NAND << + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) | + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC << + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET), + + /* sdram pll group */ + SDR_VCO_BASE, + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE << + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT << + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE << + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT << + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE << + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT << + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE << + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), + + }; + + debug("Freezing all I/O banks\n"); + /* freeze all IO banks */ + sys_mgr_frzctrl_freeze_req(); + + debug("Reconfigure Clock Manager\n"); + /* reconfigure the PLLs */ + cm_basic_init(&cm_default_cfg); + + /* configure the IOCSR / IO buffer settings */ + if (scan_mgr_configure_iocsr()) + hang(); + + /* configure the pin muxing through system manager */ + sysmgr_pinmux_init(); +#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ + /* de-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); + debug("Unfreezing/Thaw all I/O banks\n"); + /* unfreeze / thaw all IO banks */ + sys_mgr_frzctrl_thaw_req(); + /* enable console uart printing */ preloader_console_init(); } diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c new file mode 100644 index 0000000000..11f7badbf2 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. + * The value is not wrote to SYSMGR.FPGAINTF.MODULE but + * CONFIG_SYSMGR_ISWGRP_HANDOFF. + */ +static void populate_sysmgr_fpgaintf_module(void) +{ + uint32_t handoff_val = 0; + + /* ISWGRP_HANDOFF_FPGAINTF */ + writel(0, &sysmgr_regs->iswgrp_handoff[2]); + + /* Enable the signal for those HPS peripherals that use FPGA. */ + if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_NAND; + if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC1; + if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SDMMC; + if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC0; + if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM0; + if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM1; + + /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE + based on pinmux setting */ + setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val); + + handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]); + if (fpgamgr_test_fpga_ready()) { + /* Enable the required signals only */ + writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module); + } +} + +/* + * Configure all the pin muxes + */ +void sysmgr_pinmux_init(void) +{ + uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0]; + int i; + + for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) { + writel(sys_mgr_init_table[i], regs); + regs += sizeof(regs); + } + + populate_sysmgr_fpgaintf_module(); +} diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c index 09f6f14200..253cde39d1 100644 --- a/arch/arm/cpu/armv7/socfpga/timer.c +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -8,7 +8,7 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; +#define TIMER_LOAD_VAL 0xFFFFFFFF static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; @@ -22,73 +22,3 @@ int timer_init(void) writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); return 0; } - -static u32 read_timer(void) -{ - return readl(&timer_base->curr_val); -} - -/* - * Delay x useconds - */ -void __udelay(unsigned long usec) -{ - unsigned long now, last; - /* - * get the tmo value based on timer clock speed - * tmo = delay required / period of timer clock - */ - long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000; - - last = read_timer(); - while (tmo > 0) { - now = read_timer(); - if (last >= now) - /* normal mode (non roll) */ - tmo -= last - now; - else - /* we have overflow of the count down timer */ - tmo -= TIMER_LOAD_VAL - last + now; - last = now; - } -} - -/* - * Get the timer value - */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* - * Timer : get the time difference - * Unit of tick is based on the CONFIG_SYS_HZ - */ -ulong get_timer_masked(void) -{ - /* current tick value */ - ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); - if (gd->arch.lastinc >= now) { - /* normal mode (non roll) */ - /* move stamp forward with absolute diff ticks */ - gd->arch.tbl += gd->arch.lastinc - now; - } else { - /* we have overflow of the count down timer */ - gd->arch.tbl += TIMER_LOAD_VAL - gd->arch.lastinc + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* - * Reset the timer - */ -void reset_timer(void) -{ - /* capture current decrementer value time */ - gd->arch.lastinc = read_timer() / - (CONFIG_TIMER_CLOCK_KHZ / CONFIG_SYS_HZ); - /* start "advancing" time stamp from 0 */ - gd->arch.tbl = 0; -} diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds index a7c9c9d281..569fa418f4 100644 --- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds @@ -16,6 +16,7 @@ SECTIONS . = ALIGN(4); .text : { + *(.vectors) arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sdram @@ -28,7 +29,11 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } .bss : { . = ALIGN(4); @@ -37,13 +42,4 @@ SECTIONS . = ALIGN(4); __bss_end = .; } >.sdram - - . = ALIGN(8); - __malloc_start = .; - . = . + CONFIG_SPL_MALLOC_SIZE; - __malloc_end = .; - - . = . + CONFIG_SPL_STACK_SIZE; - . = ALIGN(8); - __stack_start = .; } diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index b88d3d82da..70048c10ae 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -10,7 +10,7 @@ * Copyright (c) 2003 Kshitij * Copyright (c) 2006-2008 Syed Mohammed Khasim * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -19,39 +19,6 @@ #include #include -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: .word _undefined_instruction -_software_interrupt: .word _software_interrupt -_prefetch_abort: .word _prefetch_abort -_data_abort: .word _data_abort -_not_used: .word _not_used -_irq: .word _irq -_fiq: .word _fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#else -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ - -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /************************************************************************* * * Startup Code (reset vector) @@ -63,49 +30,7 @@ _end_vect: * *************************************************************************/ -.globl _TEXT_BASE -_TEXT_BASE: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: -#ifdef IRAM_BASE_ADDR - .word IRAM_BASE_ADDR + 0x20 -#else - .word 0x0badc0de -#endif - -/* - * the actual reset code - */ + .globl reset reset: bl save_boot_params @@ -127,10 +52,10 @@ reset: * Continue to use ROM code vector only in OMAP4 spl) */ #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) - /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ - mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register + /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register bic r0, #CR_V @ V = 0 - mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register + mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register /* Set vector address in CP15 VBAR register */ ldr r0, =_start @@ -156,12 +81,6 @@ ENTRY(c_runtime_cpu_setup) mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB #endif -/* - * Move vector table - */ - /* Set vector address in CP15 VBAR register */ - ldr r0, =_start - mcr p15, 0, r0, c12, c0, 0 @Set VBAR bx lr @@ -221,7 +140,7 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c1, c0, 0 @ write system control register #endif -#ifdef CONFIG_ARM_ERRATA_742230 +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register @@ -238,6 +157,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) @@ -261,195 +185,3 @@ ENTRY(cpu_init_crit) b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current - @ user stack - stmia sp, {r0 - r12} @ Save user registers (now in - @ svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort - @ stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc - @ and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 - @ (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! - @ a reserved stack spot would - @ be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into - @ cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter - @ in banked mode) - - str lr, [r13] @ save caller lr in position 0 - @ of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of - @ saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure - @ moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & - @ switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for - @ scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - @ spots for abort stack - str lr, [r0] @ save caller lr in position 0 - @ of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of - @ saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effective fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif /* CONFIG_USE_IRQ */ -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/stv0991/Makefile b/arch/arm/cpu/armv7/stv0991/Makefile new file mode 100644 index 0000000000..95641d345f --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := timer.o clock.o pinmux.o reset.o +obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c new file mode 100644 index 0000000000..70b8a8d984 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/clock.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); + +void enable_pll1(void) +{ + /* pll1 already configured for 1000Mhz, just need to enable it */ + writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), + &stv0991_cgu_regs->pll1_ctrl); +} + +void clock_setup(int peripheral) +{ + switch (peripheral) { + case UART_CLOCK_CFG: + writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq); + break; + case ETH_CLOCK_CFG: + enable_pll1(); + writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq); + + /* Clock selection for ethernet tx_clk & rx_clk*/ + writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK) + | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl); + + break; + default: + break; + } +} diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S new file mode 100644 index 0000000000..6dafba35e2 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2014 stmicroelectronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +ENTRY(lowlevel_init) + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c new file mode 100644 index 0000000000..1d086a235d --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/pinmux.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static struct stv0991_creg *const stv0991_creg = \ + (struct stv0991_creg *)CREG_BASE_ADDR; + +int stv0991_pinmux_config(int peripheral) +{ + switch (peripheral) { + case UART_GPIOC_30_31: + /* SSDA/SSCL pad muxing to UART Rx/Dx */ + writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | + CFG_GPIOC_31_UART_RX, + &stv0991_creg->mux12); + writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | + CFG_GPIOC_30_UART_TX, + &stv0991_creg->mux12); + /* SSDA/SSCL pad config to push pull*/ + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | + CFG_GPIOC_31_MODE_PP, + &stv0991_creg->cfg_pad6); + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | + CFG_GPIOC_30_MODE_HIGH, + &stv0991_creg->cfg_pad6); + break; + case UART_GPIOB_16_17: + /* ethernet rx_6/7 to UART Rx/Dx */ + writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | + CFG_GPIOB_17_UART_RX, + &stv0991_creg->mux7); + writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | + CFG_GPIOB_16_UART_TX, + &stv0991_creg->mux7); + break; + case ETH_GPIOB_10_31_C_0_4: + writel(readl(&stv0991_creg->mux6) & 0x000000FF, + &stv0991_creg->mux6); + writel(0x00000000, &stv0991_creg->mux7); + writel(0x00000000, &stv0991_creg->mux8); + writel(readl(&stv0991_creg->mux9) & 0xFFF00000, + &stv0991_creg->mux9); + /* Ethernet Voltage configuration to 1.8V*/ + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | + ETH_VDD_CFG, &stv0991_creg->vdd_pad1); + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | + ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1); + + break; + default: + break; + } + return 0; +} diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c new file mode 100644 index 0000000000..3384b329af --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/reset.c @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +void reset_cpu(ulong ignored) +{ + puts("System is going to reboot ...\n"); + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + /* Setting bit 1 of the WDRU unit will reset the SoC */ + writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1); + + /* system will restart */ + while (1) + ; +} diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c new file mode 100644 index 0000000000..8654b8b686 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); + +#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) +#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ) + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp gd->arch.tbl +#define lastdec gd->arch.lastinc + +int timer_init(void) +{ + /* Timer1 clock configuration */ + writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq); + writel(readl(&stv0991_cgu_regs->cgu_enable_2) | + TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2); + + /* Stop the timer */ + writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); + writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc); + /* Configure timer for auto-reload */ + writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD, + &gpt1_regs_ptr->cr1); + + /* load value for free running */ + writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr); + + /* start timer */ + writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, + &gpt1_regs_ptr->cr1); + + /* Reset the timer */ + lastdec = READ_TIMER(); + timestamp = 0; + + return 0; +} + +/* + * timer without interrupts + */ +ulong get_timer(ulong base) +{ + return (get_timer_masked() / GPT_RESOLUTION) - base; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100); + ulong rndoff; + + rndoff = (usec % 10) ? 1 : 0; + + /* tenudelcnt timer tick gives 10 microsecconds delay */ + tmo = ((usec / 10) + rndoff) * tenudelcnt; + + while ((ulong) (get_timer_masked() - start) < tmo) + ; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + GPT_FREE_RUNNING - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_STV0991_HZ; +} diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile new file mode 100644 index 0000000000..48db7442f4 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 Henrik Nordstrom +# +# Based on some other Makefile +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += timer.o +obj-y += board.o +obj-y += clock.o +obj-y += cpu_info.o +obj-y += pinmux.o +obj-y += usbc.o +obj-$(CONFIG_MACH_SUN6I) += prcm.o +obj-$(CONFIG_MACH_SUN8I) += prcm.o +obj-$(CONFIG_MACH_SUN9I) += prcm.o +obj-$(CONFIG_MACH_SUN6I) += p2wi.o +obj-$(CONFIG_MACH_SUN8I) += rsb.o +obj-$(CONFIG_MACH_SUN9I) += rsb.o +obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o +obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o +obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o + +ifndef CONFIG_SPL_BUILD +ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif +endif + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o +obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o +ifdef CONFIG_SPL_FEL +obj-y += start.o +endif +endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c new file mode 100644 index 0000000000..6e28bcd040 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Some init for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_SPL_BUILD +#include +#endif +#include +#include +#include +#include +#include +#include + +#include + +static int gpio_init(void) +{ +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); +#endif + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPF(4), 1); +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); + sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); +#else +#error Unsupported console port number. Please fix pin mux settings in board.c +#endif + + return 0; +} + +void s_init(void) +{ +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + /* Magic (undocmented) value taken from boot0, without this DRAM + * access gets messed up (seems cache related) */ + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); +#endif +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \ + defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I) + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #1 << 6\n" + "mcr p15, 0, r0, c1, c0, 1\n"); +#endif + + clock_init(); + timer_init(); + gpio_init(); + i2c_init_board(); +} + +#ifdef CONFIG_SPL_BUILD +/* The sunxi internal brom will try to loader external bootloader + * from mmc0, nand flash, mmc2. + * Unfortunately we can't check how SPL was loaded so assume + * it's always the first SD/MMC controller + */ +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +/* No confirmation data available in SPL yet. Hardcode bootmode */ +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_RAW; +} + +void board_init_f(ulong dummy) +{ + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + /* Needed early by sunxi_board_init if PMU is enabled */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + sunxi_board_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} +#endif + +void reset_cpu(ulong addr) +{ +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + static const struct sunxi_wdog *wdog = + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* Set the watchdog for its shortest interval (.5s) and wait */ + writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); + + while (1) { + /* sun5i sometimes gets stuck without this */ + writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); + } +#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */ + static const struct sunxi_wdog *wdog = + ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* Set the watchdog for its shortest interval (.5s) and wait */ + writel(WDT_CFG_RESET, &wdog->cfg); + writel(WDT_MODE_EN, &wdog->mode); + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); +#endif +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#ifdef CONFIG_CMD_NET +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + __maybe_unused int rc; + +#ifdef CONFIG_MACPWR + gpio_direction_output(CONFIG_MACPWR, 1); + mdelay(200); +#endif + +#ifdef CONFIG_SUNXI_EMAC + rc = sunxi_emac_initialize(bis); + if (rc < 0) { + printf("sunxi: failed to initialize emac\n"); + return rc; + } +#endif + +#ifdef CONFIG_SUNXI_GMAC + rc = sunxi_gmac_initialize(bis); + if (rc < 0) { + printf("sunxi: failed to initialize gmac\n"); + return rc; + } +#endif + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c new file mode 100644 index 0000000000..47fb70ff7c --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int clock_init(void) +{ +#ifdef CONFIG_SPL_BUILD + clock_init_safe(); +#endif + clock_init_uart(); + + return 0; +} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c new file mode 100644 index 0000000000..49f4032e9c --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -0,0 +1,229 @@ +/* + * sun4i, sun5i and sun7i specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set safe defaults until PMU is configured */ + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); + sdelay(200); + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); +#ifdef CONFIG_MACH_SUN7I + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); +#endif + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); +#ifdef CONFIG_SUNXI_AHCI + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); +#endif +} +#endif + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb1 */ + writel(APB1_CLK_SRC_OSC24M| + APB1_CLK_RATE_N_1| + APB1_CLK_RATE_M(1), + &ccm->apb1_clk_div_cfg); + + /* open the clock for uart */ + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1)); +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 2) + return -1; + + /* set the apb clock gate for twi */ + if (state) + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port)); + else + clrbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port)); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ + 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ + 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ + 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \ + 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \ + (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \ + 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \ + (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \ + (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \ + 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \ + 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \ + (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT) + +static struct { + u32 pll1_cfg; + unsigned int freq; +} pll1_para[] = { + /* This array must be ordered by frequency. */ + { PLL1_CFG(16, 0, 0, 0), 384000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(31, 1, 0, 0), 1488000000}, + /* Final catchall entry */ + { PLL1_CFG(31, 1, 0, 0), ~0}, +}; + +void clock_set_pll1(unsigned int hz) +{ + int i = 0; + int axi, ahb, apb0; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Find target frequency */ + while (pll1_para[i].freq < hz) + i++; + + hz = pll1_para[i].freq; + + /* Calculate system clock divisors */ + axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ + ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ + apb0 = 2; /* Max 150MHz */ + + printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); + + /* Map divisors to register values */ + axi = axi - 1; + if (ahb > 4) + ahb = 3; + else if (ahb > 2) + ahb = 2; + else if (ahb > 1) + ahb = 1; + else + ahb = 0; + + apb0 = apb0 - 1; + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); + + /* Configure sys clock divisors */ + writel(axi << AXI_DIV_SHIFT | + ahb << AHB_DIV_SHIFT | + apb0 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + + /* Configure PLL1 at the desired frequency */ + writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(axi << AXI_DIV_SHIFT | + ahb << AHB_DIV_SHIFT | + apb0 << APB0_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); +} +#endif + +void clock_set_pll3(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (clk == 0) { + clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); + return; + } + + /* PLL3 rate = 3000000 * m */ + writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | + CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); +} + +unsigned int clock_get_pll5p(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll5_cfg); + int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT); + int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1; + int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT); + return (24000000 * n * k) >> p; +} + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; + return 24000000 * n * k / 2; +} + +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) +{ + int pll = clock_get_pll5p(); + int div = 1; + + while ((pll / div) > hz) + div++; + + writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P | + CCM_DE_CTRL_M(div), clk_cfg); +} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c new file mode 100644 index 0000000000..e2a78676b1 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -0,0 +1,193 @@ +/* + * sun6i specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* Set PLL ldo voltage without this PLL6 does not work properly */ + clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, + PRCM_PLL_CTRL_LDO_KEY); + clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, + PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); + clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); + + clock_set_pll1(408000000); + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); + + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + + writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); + writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); +} +#endif + +void clock_init_uart(void) +{ +#if CONFIG_CONS_INDEX < 5 + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb2 */ + writel(APB2_CLK_SRC_OSC24M| + APB2_CLK_RATE_N_1| + APB2_CLK_RATE_M(1), + &ccm->apb2_div); + + /* open the clock for uart */ + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* deassert uart reset */ + setbits_le32(&ccm->apb2_reset_cfg, + 1 << (APB2_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); +#else + /* enable R_PIO and R_UART clocks, and de-assert resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); +#endif +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 3) + return -1; + + /* set the apb clock gate for twi */ + if (state) + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port)); + else + clrbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port)); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + int k = 1; + int m = 1; + + if (clk > 1152000000) { + k = 2; + } else if (clk > 768000000) { + k = 3; + m = 2; + } + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_3 << AXI_DIV_SHIFT | + ATB_DIV_2 << ATB_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + + /* + * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) + * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m + */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | + CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_3 << AXI_DIV_SHIFT | + ATB_DIV_2 << ATB_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); +} +#endif + +void clock_set_pll3(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ + + if (clk == 0) { + clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); + return; + } + + /* PLL3 rate = 24000000 * n / m */ + writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | + CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), + &ccm->pll3_cfg); +} + +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int max_n = 32; + int k = 1, m = 2; + + if (sigma_delta_enable) + writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); + + /* PLL5 rate = 24000000 * n * k / m */ + if (clk > 24000000 * k * max_n / m) { + m = 1; + if (clk > 24000000 * k * max_n / m) + k = 2; + } + writel(CCM_PLL5_CTRL_EN | + (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | + CCM_PLL5_CTRL_UPD | + CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); + + udelay(5500); +} + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; + int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; + return 24000000 * n * k / 2; +} + +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) +{ + int pll = clock_get_pll6() * 2; + int div = 1; + + while ((pll / div) > hz) + div++; + + writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), + clk_cfg); +} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c new file mode 100644 index 0000000000..27179ba19c --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c @@ -0,0 +1,68 @@ +/* + * sun9i specific clock code + * + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* open the clock for uart */ + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + /* deassert uart reset */ + setbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* Dup with clock_init_safe(), drop once sun9i SPL support lands */ + writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg); +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 4) + return -1; + + /* set the apb reset and clock gate for twi */ + if (state) { + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); + setbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_UART_SHIFT + port)); + } else { + clrbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_UART_SHIFT + port)); + clrbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); + } + + return 0; +} + +unsigned int clock_get_pll4_periph0(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll4_periph0_cfg); + int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT); + int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT); + int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1; + const int k = 1; + + return ((24000000 * n * k) >> p) / m; +} diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk new file mode 100644 index 0000000000..00f5ffc683 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/config.mk @@ -0,0 +1,8 @@ +# Build a combined spl + u-boot image +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SPL_FEL +ALL-y += u-boot-sunxi-with-spl.bin +endif +endif +endif diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c new file mode 100644 index 0000000000..b6cb9dea64 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_MACH_SUN6I +int sunxi_get_ss_bonding_id(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + static int bonding_id = -1; + + if (bonding_id != -1) + return bonding_id; + + /* Enable Security System */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); + + bonding_id = readl(SUNXI_SS_BASE); + bonding_id = (bonding_id >> 16) & 0x7; + + /* Disable Security System again */ + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); + clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); + + return bonding_id; +} +#endif + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ +#ifdef CONFIG_MACH_SUN4I + puts("CPU: Allwinner A10 (SUN4I)\n"); +#elif defined CONFIG_MACH_SUN5I + u32 val = readl(SUNXI_SID_BASE + 0x08); + switch ((val >> 12) & 0xf) { + case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break; + case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break; + case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; + default: puts("CPU: Allwinner A1X (SUN5I)\n"); + } +#elif defined CONFIG_MACH_SUN6I + switch (sunxi_get_ss_bonding_id()) { + case SUNXI_SS_BOND_ID_A31: + puts("CPU: Allwinner A31 (SUN6I)\n"); + break; + case SUNXI_SS_BOND_ID_A31S: + puts("CPU: Allwinner A31s (SUN6I)\n"); + break; + default: + printf("CPU: Allwinner A31? (SUN6I, id: %d)\n", + sunxi_get_ss_bonding_id()); + } +#elif defined CONFIG_MACH_SUN7I + puts("CPU: Allwinner A20 (SUN7I)\n"); +#elif defined CONFIG_MACH_SUN8I + puts("CPU: Allwinner A23 (SUN8I)\n"); +#else +#warning Please update cpu_info.c with correct CPU information + puts("CPU: SUNXI Family\n"); +#endif + return 0; +} +#endif + +int sunxi_get_sid(unsigned int *sid) +{ +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I +#ifdef CONFIG_AXP221_POWER + return axp221_get_sid(sid); +#else + return -ENODEV; +#endif +#else + int i; + + for (i = 0; i< 4; i++) + sid[i] = readl(SUNXI_SID_BASE + 4 * i); + + return 0; +#endif +} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c new file mode 100644 index 0000000000..c736fa3b47 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -0,0 +1,737 @@ +/* + * sunxi DRAM controller initialization + * (C) Copyright 2012 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c + * and earlier U-Boot Allwiner A10 SPL work + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Unfortunately the only documentation we have on the sun7i DRAM + * controller is Allwinner boot0 + boot1 code, and that code uses + * magic numbers & shifts with no explanations. Hence this code is + * rather undocumented and full of magic. + */ + +#include +#include +#include +#include +#include +#include + +#define CPU_CFG_CHIP_VER(n) ((n) << 6) +#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3) +#define CPU_CFG_CHIP_REV_A 0x0 +#define CPU_CFG_CHIP_REV_C1 0x1 +#define CPU_CFG_CHIP_REV_C2 0x2 +#define CPU_CFG_CHIP_REV_B 0x3 + +/* + * Wait up to 1s for mask to be clear in given reg. + */ +static inline void await_bits_clear(u32 *reg, u32 mask) +{ + mctl_await_completion(reg, mask, 0); +} + +/* + * Wait up to 1s for mask to be set in given reg. + */ +static inline void await_bits_set(u32 *reg, u32 mask) +{ + mctl_await_completion(reg, mask, mask); +} + +/* + * This performs the external DRAM reset by driving the RESET pin low and + * then high again. According to the DDR3 spec, the RESET pin needs to be + * kept low for at least 200 us. + */ +static void mctl_ddr3_reset(void) +{ + struct sunxi_dram_reg *dram = + (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + +#ifdef CONFIG_MACH_SUN4I + struct sunxi_timer_reg *timer = + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + u32 reg_val; + + writel(0, &timer->cpu_cfg); + reg_val = readl(&timer->cpu_cfg); + + if ((reg_val & CPU_CFG_CHIP_VER_MASK) != + CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) { + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(200); + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + } else +#endif + { + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(200); + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + } + /* After the RESET pin is de-asserted, the DDR3 spec requires to wait + * for additional 500 us before driving the CKE pin (Clock Enable) + * high. The duration of this delay can be configured in the SDR_IDCR + * (Initialization Delay Configuration Register) and applied + * automatically by the DRAM controller during the DDR3 initialization + * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and + * can't provide sufficient delay at DRAM clock frequencies higher than + * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to + * 533 MHz according to the datasheet). Additionally, there is no + * official documentation for the SDR_IDCR register anywhere, and + * there is always a chance that we are interpreting it wrong. + * Better be safe than sorry, so add an explicit delay here. */ + udelay(500); +} + +static void mctl_set_drive(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + +#ifdef CONFIG_MACH_SUN7I + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), +#else + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), +#endif + DRAM_MCR_MODE_EN(0x3) | + 0xffc); +} + +static void mctl_itm_disable(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); +} + +static void mctl_itm_enable(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); +} + +static void mctl_itm_reset(void) +{ + mctl_itm_disable(); + udelay(1); /* ITM reset needs a bit of delay */ + mctl_itm_enable(); + udelay(1); +} + +static void mctl_enable_dll0(u32 phase) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + ((phase >> 16) & 0x3f) << 6); + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); + udelay(2); + + clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); + udelay(22); + + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); + udelay(22); +} + +/* Get the number of DDR byte lanes */ +static u32 mctl_get_number_of_lanes(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) == + DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT)) + return 4; + else + return 2; +} + +/* + * Note: This differs from pm/standby in that it checks the bus width + */ +static void mctl_enable_dllx(u32 phase) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 i, number_of_lanes; + + number_of_lanes = mctl_get_number_of_lanes(); + + for (i = 1; i <= number_of_lanes; i++) { + clrsetbits_le32(&dram->dllcr[i], 0xf << 14, + (phase & 0xf) << 14); + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, + DRAM_DLLCR_DISABLE); + phase >>= 4; + } + udelay(2); + + for (i = 1; i <= number_of_lanes; i++) + clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | + DRAM_DLLCR_DISABLE); + udelay(22); + + for (i = 1; i <= number_of_lanes; i++) + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, + DRAM_DLLCR_NRESET); + udelay(22); +} + +static u32 hpcr_value[32] = { +#ifdef CONFIG_MACH_SUN5I + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0, + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0x0301, 0 +#endif +#ifdef CONFIG_MACH_SUN4I + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x5031, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x1031, 0x0301, 0x0301, 0x0731 +#endif +#ifdef CONFIG_MACH_SUN7I + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0x0301, 0x0301, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x0001, 0x1031, 0, 0x1031 + /* last row differs from boot0 source table + * 0x1031, 0x0301, 0x0301, 0x0731 + * but boot0 code skips #28 and #30, and sets #29 and #31 to the + * value from #28 entry (0x1031) + */ +#endif +}; + +static void mctl_configure_hostport(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 i; + + for (i = 0; i < 32; i++) + writel(hpcr_value[i], &dram->hpcr[i]); +} + +static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) +{ + u32 reg_val; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + u32 pll5p_clk, pll6x_clk; + u32 pll5p_div, pll6x_div; + u32 pll5p_rate, pll6x_rate; + + /* setup DRAM PLL */ + reg_val = readl(&ccm->pll5_cfg); + reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ + reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ + reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ + reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ +#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT + /* Old kernels are hardcoded to P=1 (divide by 2) */ + reg_val |= CCM_PLL5_CTRL_P(1); +#endif + if (clk >= 540 && clk < 552) { + /* dram = 540MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); + } else if (clk >= 512 && clk < 528) { + /* dram = 512MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); + } else if (clk >= 496 && clk < 504) { + /* dram = 496MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); + } else if (clk >= 468 && clk < 480) { + /* dram = 468MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); + } else if (clk >= 396 && clk < 408) { + /* dram = 396MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); + } else { + /* any other frequency that is a multiple of 24 */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); + } + reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */ + reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */ + writel(reg_val, &ccm->pll5_cfg); + udelay(5500); + + setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); + +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) + /* reset GPS */ + clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); + udelay(1); + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); +#endif + + /* setup MBUS clock */ + if (!mbus_clk) + mbus_clk = 300; + + /* PLL5P and PLL6 are the potential clock sources for MBUS */ + pll6x_clk = clock_get_pll6() / 1000000; +#ifdef CONFIG_MACH_SUN7I + pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ +#endif + pll5p_clk = clock_get_pll5p() / 1000000; + pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk); + pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk); + pll6x_rate = pll6x_clk / pll6x_div; + pll5p_rate = pll5p_clk / pll5p_div; + + if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) { + /* use PLL6 as the MBUS clock source */ + reg_val = CCM_MBUS_CTRL_GATE | + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) | + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div)); + } else if (pll5p_div <= 16) { + /* use PLL5P as the MBUS clock source */ + reg_val = CCM_MBUS_CTRL_GATE | + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) | + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div)); + } else { + panic("Bad mbus_clk\n"); + } + writel(reg_val, &ccm->mbus_clk_cfg); + + /* + * open DRAMC AHB & DLL register clock + * close it first + */ +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); +#else + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); +#endif + udelay(22); + + /* then open it */ +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); +#else + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); +#endif + udelay(22); +} + +/* + * The data from rslrX and rdgrX registers (X=rank) is stored + * in a single 32-bit value using the following format: + * bits [31:26] - DQS gating system latency for byte lane 3 + * bits [25:24] - DQS gating phase select for byte lane 3 + * bits [23:18] - DQS gating system latency for byte lane 2 + * bits [17:16] - DQS gating phase select for byte lane 2 + * bits [15:10] - DQS gating system latency for byte lane 1 + * bits [ 9:8 ] - DQS gating phase select for byte lane 1 + * bits [ 7:2 ] - DQS gating system latency for byte lane 0 + * bits [ 1:0 ] - DQS gating phase select for byte lane 0 + */ +static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 lane, number_of_lanes = mctl_get_number_of_lanes(); + /* rank0 gating system latency (3 bits per lane: cycles) */ + u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1); + /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */ + u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1); + for (lane = 0; lane < number_of_lanes; lane++) { + u32 tmp = dqs_gating_delay >> (lane * 8); + slr &= ~(7 << (lane * 3)); + slr |= ((tmp >> 2) & 7) << (lane * 3); + dgr &= ~(3 << (lane * 2)); + dgr |= (tmp & 3) << (lane * 2); + } + writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1); + writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1); +} + +static int dramc_scan_readpipe(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + + /* data training trigger */ + clrbits_le32(&dram->csr, DRAM_CSR_FAILED); + setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); + + /* check whether data training process has completed */ + await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING); + + /* check data training result */ + reg_val = readl(&dram->csr); + if (reg_val & DRAM_CSR_FAILED) + return -1; + + return 0; +} + +static void dramc_clock_output_en(u32 on) +{ +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + if (on) + setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); + else + clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); +#endif +#ifdef CONFIG_MACH_SUN4I + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + if (on) + setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); + else + clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); +#endif +} + +/* tRFC in nanoseconds for different densities (from the DDR3 spec) */ +static const u16 tRFC_DDR3_table[6] = { + /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */ + 90, 90, 110, 160, 300, 350 +}; + +static void dramc_set_autorefresh_cycle(u32 clk, u32 density) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 tRFC, tREFI; + + tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000; + tREFI = (7987 * clk) >> 10; /* <= 7.8us */ + + writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr); +} + +/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */ +static u32 ddr3_write_recovery(u32 clk) +{ + u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */ + u32 twr_ck = (twr_ns * clk + 999) / 1000; + if (twr_ck < 5) + return 1; + else if (twr_ck <= 8) + return twr_ck - 4; + else if (twr_ck <= 10) + return 5; + else + return 6; +} + +/* + * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this + * means that DRAM is currently in self-refresh mode and retaining the old + * data. Since we have no idea what to do in this situation yet, just set this + * register to 0 and initialize DRAM in the same way as on any normal reboot + * (discarding whatever was stored there). + * + * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic + * value for this write operation to have any effect. On sun5i hadware this + * magic value is not necessary. And on sun4i hardware the writes to this + * register seem to have no effect at all. + */ +static void mctl_disable_power_save(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + writel(0x16510000, &dram->ppwrsctl); +} + +/* + * After the DRAM is powered up or reset, the DDR3 spec requires to wait at + * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct + * (SDR_IDCR) register appears to configure this delay, which gets applied + * right at the time when the DRAM initialization is activated in the + * 'mctl_ddr3_initialize' function. + */ +static void mctl_set_cke_delay(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + /* The CKE delay is represented in DRAM clock cycles, multiplied by N + * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to + * the maximum possible value 0x1ffff, just like in the Allwinner's + * boot0 bootloader. The resulting delay value is somewhere between + * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i + * with 360 MHz DRAM clock speed). */ + setbits_le32(&dram->idcr, 0x1ffff); +} + +/* + * This triggers the DRAM initialization. It performs sending the mode registers + * to the DRAM among other things. Very likely the ZQCL command is also getting + * executed (to do the initial impedance calibration on the DRAM side of the + * wire). The memory controller and the PHY must be already configured before + * calling this function. + */ +static void mctl_ddr3_initialize(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + setbits_le32(&dram->ccr, DRAM_CCR_INIT); + await_bits_clear(&dram->ccr, DRAM_CCR_INIT); +} + +/* + * Perform impedance calibration on the DRAM controller side of the wire. + */ +static void mctl_set_impedance(u32 zq, u32 odt_en) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF; + +#ifndef CONFIG_MACH_SUN7I + /* Appears that some kind of automatically initiated default + * ZQ calibration is already in progress at this point on sun4i/sun5i + * hardware, but not on sun7i. So it is reasonable to wait for its + * completion before doing anything else. */ + await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE); +#endif + + /* ZQ calibration is not really useful unless ODT is enabled */ + if (!odt_en) + return; + +#ifdef CONFIG_MACH_SUN7I + /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock + * unless bit 24 is set in SDR_ZQCR1. Not much is known about the + * SDR_ZQCR1 register, but there are hints indicating that it might + * be related to periodic impedance re-calibration. This particular + * magic value is borrowed from the Allwinner boot0 bootloader, and + * using it helps to avoid troubles */ + writel((1 << 24) | (1 << 1), &dram->zqcr1); +#endif + + /* Needed at least for sun5i, because it does not self clear there */ + clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); + + if (zdata) { + /* Set the user supplied impedance data */ + reg_val = DRAM_ZQCR0_ZDEN | zdata; + writel(reg_val, &dram->zqcr0); + /* no need to wait, this takes effect immediately */ + } else { + /* Do the calibration using the external resistor */ + reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog); + writel(reg_val, &dram->zqcr0); + /* Wait for the new impedance configuration to settle */ + await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE); + } + + /* Needed at least for sun5i, because it does not self clear there */ + clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); + + /* Set I/O configure register */ + writel(DRAM_IOCR_ODT_EN(odt_en), &dram->iocr); +} + +static unsigned long dramc_init_helper(struct dram_para *para) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + u32 density; + int ret_val; + + /* + * only single rank DDR3 is supported by this code even though the + * hardware can theoretically support DDR2 and up to two ranks + */ + if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1) + return 0; + + /* setup DRAM relative clock */ + mctl_setup_dram_clock(para->clock, para->mbus_clock); + + /* Disable any pad power save control */ + mctl_disable_power_save(); + + mctl_set_drive(); + + /* dram clock off */ + dramc_clock_output_en(0); + +#ifdef CONFIG_MACH_SUN4I + /* select dram controller 1 */ + writel(DRAM_CSEL_MAGIC, &dram->csel); +#endif + + mctl_itm_disable(); + mctl_enable_dll0(para->tpr3); + + /* configure external DRAM */ + reg_val = DRAM_DCR_TYPE_DDR3; + reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3); + + if (para->density == 256) + density = DRAM_DCR_CHIP_DENSITY_256M; + else if (para->density == 512) + density = DRAM_DCR_CHIP_DENSITY_512M; + else if (para->density == 1024) + density = DRAM_DCR_CHIP_DENSITY_1024M; + else if (para->density == 2048) + density = DRAM_DCR_CHIP_DENSITY_2048M; + else if (para->density == 4096) + density = DRAM_DCR_CHIP_DENSITY_4096M; + else if (para->density == 8192) + density = DRAM_DCR_CHIP_DENSITY_8192M; + else + density = DRAM_DCR_CHIP_DENSITY_256M; + + reg_val |= DRAM_DCR_CHIP_DENSITY(density); + reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1); + reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1); + reg_val |= DRAM_DCR_CMD_RANK_ALL; + reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); + writel(reg_val, &dram->dcr); + + dramc_clock_output_en(1); + + mctl_set_impedance(para->zq, para->odt_en); + + mctl_set_cke_delay(); + + mctl_ddr3_reset(); + + udelay(1); + + await_bits_clear(&dram->ccr, DRAM_CCR_INIT); + + mctl_enable_dllx(para->tpr3); + + /* set refresh period */ + dramc_set_autorefresh_cycle(para->clock, density); + + /* set timing parameters */ + writel(para->tpr0, &dram->tpr0); + writel(para->tpr1, &dram->tpr1); + writel(para->tpr2, &dram->tpr2); + + reg_val = DRAM_MR_BURST_LENGTH(0x0); +#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)) + reg_val |= DRAM_MR_POWER_DOWN; +#endif + reg_val |= DRAM_MR_CAS_LAT(para->cas - 4); + reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock)); + writel(reg_val, &dram->mr); + + writel(para->emr1, &dram->emr); + writel(para->emr2, &dram->emr2); + writel(para->emr3, &dram->emr3); + + /* disable drift compensation and set passive DQS window mode */ + clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); + +#ifdef CONFIG_MACH_SUN7I + /* Command rate timing mode 2T & 1T */ + if (para->tpr4 & 0x1) + setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); +#endif + /* initialize external DRAM */ + mctl_ddr3_initialize(); + + /* scan read pipe value */ + mctl_itm_enable(); + + /* Hardware DQS gate training */ + ret_val = dramc_scan_readpipe(); + + if (ret_val < 0) + return 0; + + /* allow to override the DQS training results with a custom delay */ + if (para->dqs_gating_delay) + mctl_set_dqs_gating_delay(0, para->dqs_gating_delay); + + /* set the DQS gating window type */ + if (para->active_windowing) + clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); + else + setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); + + mctl_itm_reset(); + + /* configure all host port */ + mctl_configure_hostport(); + + return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); +} + +unsigned long dramc_init(struct dram_para *para) +{ + unsigned long dram_size, actual_density; + + /* If the dram configuration is not provided, use a default */ + if (!para) + return 0; + + /* if everything is known, then autodetection is not necessary */ + if (para->io_width && para->bus_width && para->density) + return dramc_init_helper(para); + + /* try to autodetect the DRAM bus width and density */ + para->io_width = 16; + para->bus_width = 32; +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) + /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */ + para->density = 4096; +#else + /* all A0-A15 address lines on A20, which allow density 8192 */ + para->density = 8192; +#endif + + dram_size = dramc_init_helper(para); + if (!dram_size) { + /* if 32-bit bus width failed, try 16-bit bus width instead */ + para->bus_width = 16; + dram_size = dramc_init_helper(para); + if (!dram_size) { + /* if 16-bit bus width also failed, then bail out */ + return dram_size; + } + } + + /* check if we need to adjust the density */ + actual_density = (dram_size >> 17) * para->io_width / para->bus_width; + + if (actual_density != para->density) { + /* update the density and re-initialize DRAM again */ + para->density = actual_density; + dram_size = dramc_init_helper(para); + } + + return dram_size; +} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c new file mode 100644 index 0000000000..5dbbf6186f --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -0,0 +1,411 @@ +/* + * Sun6i platform dram controller init. + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000) + +struct dram_sun6i_para { + u8 bus_width; + u8 chan; + u8 rank; + u8 rows; + u16 page_size; +}; + +static void mctl_sys_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int dram_clk_div = 2; + + clock_set_pll5(DRAM_CLK * dram_clk_div, false); + + clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, + CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | + CCM_DRAMCLK_CFG_UPD); + mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg); + + /* deassert mctl reset */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + + /* enable mctl clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); +} + +static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para) +{ + struct sunxi_mctl_phy_reg *mctl_phy; + + if (ch_index == 0) + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + else + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + + /* disable + reset dlls */ + writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr); + } + udelay(2); + + /* enable + reset dlls */ + writel(0, &mctl_phy->acdllcr); + writel(0, &mctl_phy->dx0dllcr); + writel(0, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(0, &mctl_phy->dx2dllcr); + writel(0, &mctl_phy->dx3dllcr); + } + udelay(22); + + /* enable and release reset of dlls */ + writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr); + } + udelay(22); +} + +static bool mctl_rank_detect(u32 *gsr0, int rank) +{ + const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; + const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; + + mctl_await_completion(gsr0, done, done); + mctl_await_completion(gsr0 + 0x10, done, done); + + return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err); +} + +static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg *mctl_ctl; + struct sunxi_mctl_phy_reg *mctl_phy; + + if (ch_index == 0) { + mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + } else { + mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE; + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + } + + writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd); + mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0); + + /* PHY initialization */ + writel(MCTL_PGCR, &mctl_phy->pgcr); + writel(MCTL_MR0, &mctl_phy->mr0); + writel(MCTL_MR1, &mctl_phy->mr1); + writel(MCTL_MR2, &mctl_phy->mr2); + writel(MCTL_MR3, &mctl_phy->mr3); + + writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST, + &mctl_phy->ptr0); + + writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); + writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); + + writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) | + (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) | + (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0), + &mctl_phy->dtpr0); + + writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) | + (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) | + ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) | + (MCTL_TAOND << 0), &mctl_phy->dtpr1); + + writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) | + (MCTL_TEXSR << 0), &mctl_phy->dtpr2); + + writel(1, &mctl_ctl->dfitphyupdtype0); + writel(MCTL_DCR_DDR3, &mctl_phy->dcr); + writel(MCTL_DSGCR, &mctl_phy->dsgcr); + writel(MCTL_DXCCR, &mctl_phy->dxccr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr); + + mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03); + + writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1); + + setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); + writel(MCTL_PIR_STEP1, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f); + + /* rank detect */ + if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) { + para->rank = 1; + clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK); + } + + /* + * channel detect, check channel 1 dx0 and dx1 have rank 0, if not + * assume nothing is connected to channel 1. + */ + if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) { + para->chan = 1; + clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); + return; + } + + /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */ + if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) { + para->bus_width = 16; + para->page_size = 2048; + setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); + setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); + clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN); + clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN); + } + + setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); + writel(MCTL_PIR_STEP2, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11); + + if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK) + panic("Training error initialising DRAM\n"); + + /* Move to configure state */ + writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl); + mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01); + + /* Set number of clks per micro-second */ + writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u); + /* Set number of clks per 100 nano-seconds */ + writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n); + /* Set memory timing registers */ + writel(MCTL_TREFI, &mctl_ctl->trefi); + writel(MCTL_TMRD, &mctl_ctl->tmrd); + writel(MCTL_TRFC, &mctl_ctl->trfc); + writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp); + writel(MCTL_TRTW, &mctl_ctl->trtw); + writel(MCTL_TAL, &mctl_ctl->tal); + writel(MCTL_TCL, &mctl_ctl->tcl); + writel(MCTL_TCWL, &mctl_ctl->tcwl); + writel(MCTL_TRAS, &mctl_ctl->tras); + writel(MCTL_TRC, &mctl_ctl->trc); + writel(MCTL_TRCD, &mctl_ctl->trcd); + writel(MCTL_TRRD, &mctl_ctl->trrd); + writel(MCTL_TRTP, &mctl_ctl->trtp); + writel(MCTL_TWR, &mctl_ctl->twr); + writel(MCTL_TWTR, &mctl_ctl->twtr); + writel(MCTL_TEXSR, &mctl_ctl->texsr); + writel(MCTL_TXP, &mctl_ctl->txp); + writel(MCTL_TXPDLL, &mctl_ctl->txpdll); + writel(MCTL_TZQCS, &mctl_ctl->tzqcs); + writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi); + writel(MCTL_TDQS, &mctl_ctl->tdqs); + writel(MCTL_TCKSRE, &mctl_ctl->tcksre); + writel(MCTL_TCKSRX, &mctl_ctl->tcksrx); + writel(MCTL_TCKE, &mctl_ctl->tcke); + writel(MCTL_TMOD, &mctl_ctl->tmod); + writel(MCTL_TRSTL, &mctl_ctl->trstl); + writel(MCTL_TZQCL, &mctl_ctl->tzqcl); + writel(MCTL_TMRR, &mctl_ctl->tmrr); + writel(MCTL_TCKESR, &mctl_ctl->tckesr); + writel(MCTL_TDPD, &mctl_ctl->tdpd); + + /* Unknown magic performed by boot0 */ + setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); + clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f); + + /* Select 16/32-bits mode for MCTL */ + if (para->bus_width == 16) + setbits_le32(&mctl_ctl->ppcfg, 1); + + /* Set DFI timing registers */ + writel(MCTL_TCWL, &mctl_ctl->dfitphywrl); + writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden); + writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl); + writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0); + + writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg); + + /* DFI update configuration register */ + writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg); + + /* Move to access state */ + writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl); + mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03); +} + +static void mctl_com_init(struct dram_sun6i_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy1 = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 | + ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | + MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | + MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); + + /* Unknown magic performed by boot0 */ + setbits_le32(&mctl_com->dbgcr, (1 << 6)); + + if (para->chan == 1) { + /* Shutdown channel 1 */ + setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); + setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE); + clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE); + /* + * CH0 ?? this is what boot0 does. Leave as is until we can + * confirm this. + */ + setbits_le32(&prcm->vdd_sys_pwroff, + PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF); + } +} + +static void mctl_port_cfg(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable DRAM AXI clock for CPU access */ + setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM); + + /* Bunch of magic writes performed by boot0 */ + writel(0x00400302, &mctl_com->rmcr[0]); + writel(0x01000307, &mctl_com->rmcr[1]); + writel(0x00400302, &mctl_com->rmcr[2]); + writel(0x01000307, &mctl_com->rmcr[3]); + writel(0x01000307, &mctl_com->rmcr[4]); + writel(0x01000303, &mctl_com->rmcr[6]); + writel(0x01000303, &mctl_com->mmcr[0]); + writel(0x00400310, &mctl_com->mmcr[1]); + writel(0x01000307, &mctl_com->mmcr[2]); + writel(0x01000303, &mctl_com->mmcr[3]); + writel(0x01800303, &mctl_com->mmcr[4]); + writel(0x01800303, &mctl_com->mmcr[5]); + writel(0x01800303, &mctl_com->mmcr[6]); + writel(0x01800303, &mctl_com->mmcr[7]); + writel(0x01000303, &mctl_com->mmcr[8]); + writel(0x00000002, &mctl_com->mmcr[15]); + writel(0x00000310, &mctl_com->mbagcr[0]); + writel(0x00400310, &mctl_com->mbagcr[1]); + writel(0x00400310, &mctl_com->mbagcr[2]); + writel(0x00000307, &mctl_com->mbagcr[3]); + writel(0x00000317, &mctl_com->mbagcr[4]); + writel(0x00000307, &mctl_com->mbagcr[5]); +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + u32 offset; + int bank, bus, columns; + + /* Set initial parameters, these get modified by the autodetect code */ + struct dram_sun6i_para para = { + .bus_width = 32, + .chan = 2, + .rank = 2, + .page_size = 4096, + .rows = 16, + }; + + /* A31s only has one channel */ + if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S) + para.chan = 1; + + mctl_sys_init(); + + mctl_dll_init(0, ¶); + setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); + + if (para.chan == 2) { + mctl_dll_init(1, ¶); + setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); + } + + setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN); + + mctl_channel_init(0, ¶); + if (para.chan == 2) + mctl_channel_init(1, ¶); + + mctl_com_init(¶); + mctl_port_cfg(); + + /* + * Change to 1 ch / sequence / 8192 byte pages / 16 rows / + * 8 bit banks / 1 rank mode. + */ + clrsetbits_le32(&mctl_com->cr, + MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK | + MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, + MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE | + MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) | + MCTL_CR_BANK(1) | MCTL_CR_RANK(1)); + + /* Detect and set page size */ + for (columns = 7; columns < 20; columns++) { + if (mctl_mem_matches(1 << columns)) + break; + } + bus = (para.bus_width == 32) ? 2 : 1; + columns -= bus; + para.page_size = (1 << columns) * (bus << 1); + clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK, + MCTL_CR_PAGE_SIZE(para.page_size)); + + /* Detect and set rows */ + for (para.rows = 11; para.rows < 16; para.rows++) { + offset = 1 << (para.rows + columns + bus); + if (mctl_mem_matches(offset)) + break; + } + clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, + MCTL_CR_ROW(para.rows)); + + /* Detect bank size */ + offset = 1 << (para.rows + columns + bus + 2); + bank = mctl_mem_matches(offset) ? 0 : 1; + + /* Restore interleave, chan and rank values, set bank size */ + clrsetbits_le32(&mctl_com->cr, + MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE | + MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, + MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) | + MCTL_CR_RANK(para.rank)); + + return 1 << (para.rank + para.rows + bank + columns + para.chan + bus); +} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c new file mode 100644 index 0000000000..3d7964d1af --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c @@ -0,0 +1,345 @@ +/* + * Sun8i platform dram controller init. + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Note this code uses a lot of magic hex values, that is because this code + * simply replays the init sequence as done by the Allwinner boot0 code, so + * we do not know what these values mean. There are no symbolic constants for + * these magic values, since we do not know how to name them and making up + * names for them is not useful. + * + * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one + * found in the TI Keystone2 documentation: + * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf + * "Table4-2 DDR3 PHY Registers" + * This may be used as a (possible) reference for future work / cleanups. + */ + +#include +#include +#include +#include +#include +#include + +static const struct dram_para dram_para = { + .clock = CONFIG_DRAM_CLK, + .type = 3, + .zq = CONFIG_DRAM_ZQ, + .odt_en = 1, + .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ + .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ + .mr0 = 6736, + .mr1 = 4, + .mr2 = 16, + .mr3 = 0, + /* tpr0 - 10 contain timing constants or-ed together in u32 vals */ + .tpr0 = 0x2ab83def, + .tpr1 = 0x18082356, + .tpr2 = 0x00034156, + .tpr3 = 0x448c5533, + .tpr4 = 0x08010d00, + .tpr5 = 0x0340b20f, + .tpr6 = 0x20d118cc, + .tpr7 = 0x14062485, + .tpr8 = 0x220d1d52, + .tpr9 = 0x1e078c22, + .tpr10 = 0x3c, + .tpr11 = 0, /* not used */ + .tpr12 = 0, /* not used */ + .tpr13 = 0x30000, +}; + +static void mctl_sys_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable pll5, note the divide by 2 is deliberate! */ + clock_set_pll5(dram_para.clock * 1000000 / 2, + dram_para.tpr13 & 0x40000); + + /* deassert ahb mctl reset */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + + /* enable ahb mctl clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); +} + +static void mctl_apply_odt_correction(u32 *reg, int correction) +{ + int val; + + val = (readl(reg) >> 8) & 0xff; + val += correction; + + /* clamp */ + if (val < 0) + val = 0; + else if (val > 255) + val = 255; + + clrsetbits_le32(reg, 0xff00, val << 8); +} + +static void mctl_init(u32 *bus_width) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + int correction; + + if (dram_para.tpr13 & 0x20) + writel(0x40b, &mctl_phy->dcr); + else + writel(0x1000040b, &mctl_phy->dcr); + + if (dram_para.clock >= 480) + writel(0x5c000, &mctl_phy->dllgcr); + else + writel(0xdc000, &mctl_phy->dllgcr); + + writel(0x0a003e3f, &mctl_phy->pgcr0); + writel(0x03008421, &mctl_phy->pgcr1); + + writel(dram_para.mr0, &mctl_phy->mr0); + writel(dram_para.mr1, &mctl_phy->mr1); + writel(dram_para.mr2, &mctl_phy->mr2); + writel(dram_para.mr3, &mctl_phy->mr3); + + if (!(dram_para.tpr13 & 0x10000)) { + clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000); + clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000); + } + + /* + * All the masking and shifting below converts what I assume are DDR + * timing constants from Allwinner dram_para tpr format to the actual + * timing registers format. + */ + + writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2); + writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3); + writel((dram_para.tpr0 & 0x3ff00000) >> 2 | + (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4); + + writel(dram_para.tpr3, &mctl_phy->dtpr0); + writel(dram_para.tpr4, &mctl_phy->dtpr2); + + writel(0x01000081, &mctl_phy->dtcr); + + if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) { + clrbits_le32(&mctl_phy->dx0gcr, 0x600); + clrbits_le32(&mctl_phy->dx1gcr, 0x600); + } + if (dram_para.clock <= 240) { + writel(0, &mctl_phy->odtcr); + writel(0, &mctl_ctl->odtmap); + } + + writel(((dram_para.tpr5 & 0x0f00) << 12) | + ((dram_para.tpr5 & 0x00f8) << 9) | + ((dram_para.tpr5 & 0x0007) << 8), + &mctl_ctl->rfshctl0); + + writel(((dram_para.tpr5 & 0x0003f000) << 12) | + ((dram_para.tpr5 & 0x00fc0000) >> 2) | + ((dram_para.tpr5 & 0x3f000000) >> 16) | + ((dram_para.tpr6 & 0x0000003f) >> 0), + &mctl_ctl->dramtmg0); + + writel(((dram_para.tpr6 & 0x000007c0) << 10) | + ((dram_para.tpr6 & 0x0000f800) >> 3) | + ((dram_para.tpr6 & 0x003f0000) >> 16), + &mctl_ctl->dramtmg1); + + writel(((dram_para.tpr6 & 0x0fc00000) << 2) | + ((dram_para.tpr7 & 0x0000001f) << 16) | + ((dram_para.tpr7 & 0x000003e0) << 3) | + ((dram_para.tpr7 & 0x0000fc00) >> 10), + &mctl_ctl->dramtmg2); + + writel(((dram_para.tpr7 & 0x03ff0000) >> 16) | + ((dram_para.tpr6 & 0xf0000000) >> 16), + &mctl_ctl->dramtmg3); + + writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) | + ((dram_para.tpr8 & 0x00000007) << 16) | + ((dram_para.tpr8 & 0x00000038) << 5) | + ((dram_para.tpr8 & 0x000003c0) >> 6), + &mctl_ctl->dramtmg4); + + writel(((dram_para.tpr8 & 0x00003c00) << 14) | + ((dram_para.tpr8 & 0x0003c000) << 2) | + ((dram_para.tpr8 & 0x00fc0000) >> 10) | + ((dram_para.tpr8 & 0x0f000000) >> 24), + &mctl_ctl->dramtmg5); + + writel(0x00000008, &mctl_ctl->dramtmg8); + + writel(((dram_para.tpr8 & 0xf0000000) >> 4) | + ((dram_para.tpr9 & 0x00007c00) << 6) | + ((dram_para.tpr9 & 0x000003e0) << 3) | + ((dram_para.tpr9 & 0x0000001f) >> 0), + &mctl_ctl->pitmg0); + + setbits_le32(&mctl_ctl->pitmg1, 0x80000); + + writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001, + &mctl_ctl->sched); + + writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); + writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); + + writel(0x00000000, &mctl_ctl->pimisc); + writel(0x80000000, &mctl_ctl->upd0); + + writel(((dram_para.tpr9 & 0xffc00000) >> 22) | + ((dram_para.tpr10 & 0x00000fff) << 16), + &mctl_ctl->rfshtmg); + + if (dram_para.tpr13 & 0x20) + writel(0x01040001, &mctl_ctl->mstr); + else + writel(0x01040401, &mctl_ctl->mstr); + + if (!(dram_para.tpr13 & 0x20000)) { + writel(0x00000002, &mctl_ctl->pwrctl); + writel(0x00008001, &mctl_ctl->pwrtmg); + } + + writel(0x00000001, &mctl_ctl->rfshctl3); + writel(0x00000001, &mctl_ctl->pimisc); + + /* deassert dram_clk_cfg reset */ + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + + setbits_le32(&mctl_com->ccr, 0x80000); + + /* zq stuff */ + writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1); + + writel(0x00000003, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09); + + writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2); + writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); + + /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */ + writel(0x000005f3, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03); + + if (readl(&mctl_phy->dx1gsr0) & 0x1000000) { + *bus_width = 8; + writel(0, &mctl_phy->dx1gcr); + writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); + writel(0x5f3, &mctl_phy->pir); + udelay(10000); + setbits_le32(&mctl_ctl->mstr, 0x1000); + } else + *bus_width = 16; + + correction = (dram_para.odt_en >> 8) & 0xff; + if (correction) { + if (dram_para.odt_en & 0x80000000) + correction = -correction; + + mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction); + mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction); + } + + mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); + + writel(0x08003e3f, &mctl_phy->pgcr0); + writel(0x00000000, &mctl_ctl->rfshctl3); +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + const u32 columns = 13; + u32 bus, bus_width, offset, page_size, rows; + + mctl_sys_init(); + mctl_init(&bus_width); + + if (bus_width == 16) { + page_size = 8; + bus = 1; + } else { + page_size = 7; + bus = 0; + } + + if (!(dram_para.tpr13 & 0x80000000)) { + /* Detect and set rows */ + writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size), + &mctl_com->cr); + setbits_le32(&mctl_com->swonr, 0x0003ffff); + for (rows = 11; rows < 16; rows++) { + offset = 1 << (rows + columns + bus); + if (mctl_mem_matches(offset)) + break; + } + clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, + MCTL_CR_ROW(rows)); + } else { + rows = (dram_para.para1 >> 16) & 0xff; + writel(((dram_para.para2 & 0x000000f0) << 11) | + ((rows - 1) << 4) | + ((dram_para.para1 & 0x0f000000) >> 22) | + 0x31000 | MCTL_CR_PAGE_SIZE(page_size), + &mctl_com->cr); + setbits_le32(&mctl_com->swonr, 0x0003ffff); + } + + /* Setup DRAM master priority? If this is left out things still work */ + writel(0x00000008, &mctl_com->mcr0_0); + writel(0x0001000d, &mctl_com->mcr1_0); + writel(0x00000004, &mctl_com->mcr0_1); + writel(0x00000080, &mctl_com->mcr1_1); + writel(0x00000004, &mctl_com->mcr0_2); + writel(0x00000019, &mctl_com->mcr1_2); + writel(0x00000004, &mctl_com->mcr0_3); + writel(0x00000080, &mctl_com->mcr1_3); + writel(0x00000004, &mctl_com->mcr0_4); + writel(0x01010040, &mctl_com->mcr1_4); + writel(0x00000004, &mctl_com->mcr0_5); + writel(0x0001002f, &mctl_com->mcr1_5); + writel(0x00000004, &mctl_com->mcr0_6); + writel(0x00010020, &mctl_com->mcr1_6); + writel(0x00000004, &mctl_com->mcr0_7); + writel(0x00010020, &mctl_com->mcr1_7); + writel(0x00000008, &mctl_com->mcr0_8); + writel(0x00000001, &mctl_com->mcr1_8); + writel(0x00000008, &mctl_com->mcr0_9); + writel(0x00000005, &mctl_com->mcr1_9); + writel(0x00000008, &mctl_com->mcr0_10); + writel(0x00000003, &mctl_com->mcr1_10); + writel(0x00000008, &mctl_com->mcr0_11); + writel(0x00000005, &mctl_com->mcr1_11); + writel(0x00000008, &mctl_com->mcr0_12); + writel(0x00000003, &mctl_com->mcr1_12); + writel(0x00000008, &mctl_com->mcr0_13); + writel(0x00000004, &mctl_com->mcr1_13); + writel(0x00000008, &mctl_com->mcr0_14); + writel(0x00000002, &mctl_com->mcr1_14); + writel(0x00000008, &mctl_com->mcr0_15); + writel(0x00000003, &mctl_com->mcr1_15); + writel(0x00010138, &mctl_com->bwcr); + + return 1 << (rows + columns + bus); +} diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c new file mode 100644 index 0000000000..26a9cfc68b --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/p2wi.c @@ -0,0 +1,117 @@ +/* + * Sunxi A31 Power Management Unit + * + * (C) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work + * + * (C) Copyright 2006-2013 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void p2wi_init(void) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + + /* Enable p2wi and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); + + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); + + /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ + writel(P2WI_CTRL_RESET, &p2wi->ctrl); + sdelay(0x100); + writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), + &p2wi->cc); +} + +int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + unsigned long tmo = timer_get_us() + 1000000; + + writel(P2WI_PM_DEV_ADDR(slave_addr) | + P2WI_PM_CTRL_ADDR(ctrl_reg) | + P2WI_PM_INIT_DATA(init_data) | + P2WI_PM_INIT_SEND, + &p2wi->pm); + + while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return 0; +} + +static int p2wi_await_trans(void) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + unsigned long tmo = timer_get_us() + 1000000; + int ret; + u8 reg; + + while (1) { + reg = readl(&p2wi->status); + if (reg & P2WI_STAT_TRANS_ERR) { + ret = -EIO; + break; + } + if (reg & P2WI_STAT_TRANS_DONE) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(reg, &p2wi->status); /* Clear status bits */ + return ret; +} + +int p2wi_read(const u8 addr, u8 *data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + int ret; + + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); + writel(P2WI_DATA_NUM_BYTES(1) | + P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes); + writel(P2WI_STAT_TRANS_DONE, &p2wi->status); + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); + + ret = p2wi_await_trans(); + + *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK; + return ret; +} + +int p2wi_write(const u8 addr, u8 data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); + writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); + writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes); + writel(P2WI_STAT_TRANS_DONE, &p2wi->status); + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); + + return p2wi_await_trans(); +} diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c new file mode 100644 index 0000000000..b026f78ca5 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/pinmux.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) +{ + u32 index = GPIO_CFG_INDEX(bank_offset); + u32 offset = GPIO_CFG_OFFSET(bank_offset); + + clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); +} + +void sunxi_gpio_set_cfgpin(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + sunxi_gpio_set_cfgbank(pio, pin, val); +} + +int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) +{ + u32 index = GPIO_CFG_INDEX(bank_offset); + u32 offset = GPIO_CFG_OFFSET(bank_offset); + u32 cfg; + + cfg = readl(&pio->cfg[0] + index); + cfg >>= offset; + + return cfg & 0xf; +} + +int sunxi_gpio_get_cfgpin(u32 pin) +{ + u32 bank = GPIO_BANK(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + return sunxi_gpio_get_cfgbank(pio, pin); +} + +int sunxi_gpio_set_drv(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_DRV_INDEX(pin); + u32 offset = GPIO_DRV_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); + + return 0; +} + +int sunxi_gpio_set_pull(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_PULL_INDEX(pin); + u32 offset = GPIO_PULL_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); + + return 0; +} diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c new file mode 100644 index 0000000000..19b4938dc9 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/prcm.c @@ -0,0 +1,35 @@ +/* + * Sunxi A31 Power Management Unit + * + * (C) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * + * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work + * + * (C) Copyright 2006-2013 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* APB0 clock gate and reset bit offsets are the same. */ +void prcm_apb0_enable(u32 flags) +{ + struct sunxi_prcm_reg *prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* open the clock for module */ + setbits_le32(&prcm->apb0_gate, flags); + + /* deassert reset for module */ + setbits_le32(&prcm->apb0_reset, flags); +} diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S new file mode 100644 index 0000000000..5be497b7be --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -0,0 +1,333 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * Based on code by Carl van Schaik . + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +/* + * Memory layout: + * + * SECURE_RAM to text_end : + * ._secure_text section + * text_end to ALIGN_PAGE(text_end): + * nothing + * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000) + * 1kB of stack per CPU (4 CPUs max). + */ + + .pushsection ._secure.text, "ax" + + .arch_extension sec + +#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000) +#define TEN_MS (10 * ONE_MS) +#define GICD_BASE 0x1c81000 +#define GICC_BASE 0x1c82000 + +.macro timer_wait reg, ticks + @ Program CNTP_TVAL + movw \reg, #(\ticks & 0xffff) + movt \reg, #(\ticks >> 16) + mcr p15, 0, \reg, c14, c2, 0 + isb + @ Enable physical timer, mask interrupt + mov \reg, #3 + mcr p15, 0, \reg, c14, c2, 1 + @ Poll physical timer until ISTATUS is on +1: isb + mrc p15, 0, \reg, c14, c2, 1 + ands \reg, \reg, #4 + bne 1b + @ Disable timer + mov \reg, #0 + mcr p15, 0, \reg, c14, c2, 1 + isb +.endm + +.globl psci_fiq_enter +psci_fiq_enter: + push {r0-r12} + + @ Switch to secure + mrc p15, 0, r7, c1, c1, 0 + bic r8, r7, #1 + mcr p15, 0, r8, c1, c1, 0 + isb + + @ Validate reason based on IAR and acknowledge + movw r8, #(GICC_BASE & 0xffff) + movt r8, #(GICC_BASE >> 16) + ldr r9, [r8, #GICC_IAR] + movw r10, #0x3ff + movt r10, #0 + cmp r9, r10 @ skip spurious interrupt 1023 + beq out + movw r10, #0x3fe @ ...and 1022 + cmp r9, r10 + beq out + str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt + dsb + + @ Compute CPU number + lsr r9, r9, #10 + and r9, r9, #0xf + + movw r8, #(SUN7I_CPUCFG_BASE & 0xffff) + movt r8, #(SUN7I_CPUCFG_BASE >> 16) + + @ Wait for the core to enter WFI + lsl r11, r9, #6 @ x64 + add r11, r11, r8 + +1: ldr r10, [r11, #0x48] + tst r10, #(1 << 2) + bne 2f + timer_wait r10, ONE_MS + b 1b + + @ Reset CPU +2: mov r10, #0 + str r10, [r11, #0x40] + + @ Lock CPU + mov r10, #1 + lsl r9, r10, r9 @ r9 is now CPU mask + ldr r10, [r8, #0x1e4] + bic r10, r10, r9 + str r10, [r8, #0x1e4] + + @ Set power gating + ldr r10, [r8, #0x1b4] + orr r10, r10, #1 + str r10, [r8, #0x1b4] + timer_wait r10, ONE_MS + + @ Activate power clamp + mov r10, #1 +1: str r10, [r8, #0x1b0] + lsl r10, r10, #1 + orr r10, r10, #1 + tst r10, #0x100 + beq 1b + + @ Restore security level +out: mcr p15, 0, r7, c1, c1, 0 + + pop {r0-r12} + subs pc, lr, #4 + + @ r1 = target CPU + @ r2 = target PC +.globl psci_cpu_on +psci_cpu_on: + adr r0, _target_pc + str r2, [r0] + dsb + + movw r0, #(SUN7I_CPUCFG_BASE & 0xffff) + movt r0, #(SUN7I_CPUCFG_BASE >> 16) + + @ CPU mask + and r1, r1, #3 @ only care about first cluster + mov r4, #1 + lsl r4, r4, r1 + + adr r6, _sunxi_cpu_entry + str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) + + @ Assert reset on target CPU + mov r6, #0 + lsl r5, r1, #6 @ 64 bytes per CPU + add r5, r5, #0x40 @ Offset from base + add r5, r5, r0 @ CPU control block + str r6, [r5] @ Reset CPU + + @ l1 invalidate + ldr r6, [r0, #0x184] + bic r6, r6, r4 + str r6, [r0, #0x184] + + @ Lock CPU + ldr r6, [r0, #0x1e4] + bic r6, r6, r4 + str r6, [r0, #0x1e4] + + @ Release power clamp + movw r6, #0x1ff + movt r6, #0 +1: lsrs r6, r6, #1 + str r6, [r0, #0x1b0] + bne 1b + + timer_wait r1, TEN_MS + + @ Clear power gating + ldr r6, [r0, #0x1b4] + bic r6, r6, #1 + str r6, [r0, #0x1b4] + + @ Deassert reset on target CPU + mov r6, #3 + str r6, [r5] + + @ Unlock CPU + ldr r6, [r0, #0x1e4] + orr r6, r6, r4 + str r6, [r0, #0x1e4] + + mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS + mov pc, lr + +_target_pc: + .word 0 + +/* Imported from Linux kernel */ +v7_flush_dcache_all: + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +flush_levels: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mrs r9, cpsr @ make cssr&csidr read atomic + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + msr cpsr_c, r9 + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop1: + mov r9, r7 @ create working copy of max index +loop2: + orr r11, r10, r4, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r9, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the index + bge loop2 + subs r4, r4, #1 @ decrement the way + bge loop1 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt flush_levels +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb st + isb + bx lr + +_sunxi_cpu_entry: + @ Set SMP bit + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + isb + + bl _nonsec_init + bl psci_arch_init + + adr r0, _target_pc + ldr r0, [r0] + b _do_nonsec_entry + +.globl psci_cpu_off +psci_cpu_off: + mrc p15, 0, r0, c1, c0, 0 @ SCTLR + bic r0, r0, #(1 << 2) @ Clear C bit + mcr p15, 0, r0, c1, c0, 0 @ SCTLR + isb + dsb + + bl v7_flush_dcache_all + + clrex @ Why??? + + mrc p15, 0, r0, c1, c0, 1 @ ACTLR + bic r0, r0, #(1 << 6) @ Clear SMP bit + mcr p15, 0, r0, c1, c0, 1 @ ACTLR + isb + dsb + + @ Ask CPU0 to pull the rug... + movw r0, #(GICD_BASE & 0xffff) + movt r0, #(GICD_BASE >> 16) + movw r1, #15 @ SGI15 + movt r1, #1 @ Target is CPU0 + str r1, [r0, #GICD_SGIR] + dsb + +1: wfi + b 1b + +.globl psci_arch_init +psci_arch_init: + movw r4, #(GICD_BASE & 0xffff) + movt r4, #(GICD_BASE >> 16) + + ldr r5, [r4, #GICD_IGROUPRn] + bic r5, r5, #(1 << 15) @ SGI15 as Group-0 + str r5, [r4, #GICD_IGROUPRn] + + mov r5, #0 @ Set SGI15 priority to 0 + strb r5, [r4, #(GICD_IPRIORITYRn + 15)] + + add r4, r4, #0x1000 @ GICC address + + mov r5, #0xff + str r5, [r4, #GICC_PMR] @ Be cool with non-secure + + ldr r5, [r4, #GICC_CTLR] + orr r5, r5, #(1 << 3) @ Switch FIQEn on + str r5, [r4, #GICC_CTLR] + + mrc p15, 0, r5, c1, c1, 0 @ Read SCR + orr r5, r5, #4 @ Enable FIQ in monitor mode + bic r5, r5, #1 @ Secure mode + mcr p15, 0, r5, c1, c1, 0 @ Write SCR + isb + + mrc p15, 0, r4, c0, c0, 5 @ MPIDR + and r4, r4, #3 @ cpu number in cluster + mov r5, #0x400 @ 1kB of stack per CPU + mul r4, r4, r5 + + adr r5, text_end @ end of text + add r5, r5, #0x2000 @ Skip two pages + lsr r5, r5, #12 @ Align to start of page + lsl r5, r5, #12 + sub sp, r5, r4 @ here's our stack! + + bx lr + +text_end: + .popsection diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c new file mode 100644 index 0000000000..b00befb301 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/rsb.c @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2014 Hans de Goede + * + * Based on allwinner u-boot sources rsb code which is: + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * lixiang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static int rsb_set_device_mode(void); + +static void rsb_cfg_io(void) +{ +#ifdef CONFIG_MACH_SUN8I + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA); + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); + sunxi_gpio_set_pull(SUNXI_GPL(1), 1); + sunxi_gpio_set_drv(SUNXI_GPL(0), 2); + sunxi_gpio_set_drv(SUNXI_GPL(1), 2); +#elif defined CONFIG_MACH_SUN9I + sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA); + sunxi_gpio_set_pull(SUNXI_GPN(0), 1); + sunxi_gpio_set_pull(SUNXI_GPN(1), 1); + sunxi_gpio_set_drv(SUNXI_GPN(0), 2); + sunxi_gpio_set_drv(SUNXI_GPN(1), 2); +#else +#error unsupported MACH_SUNXI +#endif +} + +static void rsb_set_clk(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + u32 div = 0; + u32 cd_odly = 0; + + /* Source is Hosc24M, set RSB clk to 3Mhz */ + div = 24000000 / 3000000 / 2 - 1; + cd_odly = div >> 1; + if (!cd_odly) + cd_odly = 1; + + writel((cd_odly << 8) | div, &rsb->ccr); +} + +int rsb_init(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + rsb_cfg_io(); + + /* Enable RSB and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); + rsb_set_clk(); + + return rsb_set_device_mode(); +} + +static int rsb_await_trans(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + unsigned long tmo = timer_get_us() + 1000000; + u32 stat; + int ret; + + while (1) { + stat = readl(&rsb->stat); + if (stat & RSB_STAT_LBSY_INT) { + ret = -EBUSY; + break; + } + if (stat & RSB_STAT_TERR_INT) { + ret = -EIO; + break; + } + if (stat & RSB_STAT_TOVER_INT) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(stat, &rsb->stat); /* Clear status bits */ + + return ret; +} + +static int rsb_set_device_mode(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + unsigned long tmo = timer_get_us() + 1000000; + + writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA, + &rsb->dmcr); + + while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return rsb_await_trans(); +} + +static int rsb_do_trans(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS); + return rsb_await_trans(); +} + +int rsb_set_device_address(u16 device_addr, u16 runtime_addr) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | + RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr); + writel(RSB_CMD_SET_RTSADDR, &rsb->cmd); + + return rsb_do_trans(); +} + +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); + writel(reg_addr, &rsb->addr); + writel(data, &rsb->data); + writel(RSB_CMD_BYTE_WRITE, &rsb->cmd); + + return rsb_do_trans(); +} + +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + int ret; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); + writel(reg_addr, &rsb->addr); + writel(RSB_CMD_BYTE_READ, &rsb->cmd); + + ret = rsb_do_trans(); + if (ret) + return ret; + + *data = readl(&rsb->data) & 0xff; + + return 0; +} diff --git a/arch/arm/cpu/armv7/sunxi/start.c b/arch/arm/cpu/armv7/sunxi/start.c new file mode 100644 index 0000000000..6b392fa835 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/start.c @@ -0,0 +1 @@ +/* Intentionally empty. Only needed to get FEL SPL link line right */ diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/cpu/armv7/sunxi/timer.c new file mode 100644 index 0000000000..36263896d8 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/timer.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TIMER_MODE (0x0 << 7) /* continuous mode */ +#define TIMER_DIV (0x0 << 4) /* pre scale 1 */ +#define TIMER_SRC (0x1 << 2) /* osc24m */ +#define TIMER_RELOAD (0x1 << 1) /* reload internal value */ +#define TIMER_EN (0x1 << 0) /* enable timer */ + +#define TIMER_CLOCK (24 * 1000 * 1000) +#define COUNT_TO_USEC(x) ((x) / 24) +#define USEC_TO_COUNT(x) ((x) * 24) +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) + +#define TIMER_LOAD_VAL 0xffffffff + +#define TIMER_NUM 0 /* we use timer 0 */ + +/* read the 32-bit timer */ +static ulong read_timer(void) +{ + struct sunxi_timer_reg *timers = + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + struct sunxi_timer *timer = &timers->timer[TIMER_NUM]; + + /* + * The hardware timer counts down, therefore we invert to + * produce an incrementing timer. + */ + return ~readl(&timer->val); +} + +/* init timer register */ +int timer_init(void) +{ + struct sunxi_timer_reg *timers = + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + struct sunxi_timer *timer = &timers->timer[TIMER_NUM]; + writel(TIMER_LOAD_VAL, &timer->inter); + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN, + &timer->ctl); + + return 0; +} + +/* timer without interrupts */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = TICKS_TO_HZ(read_timer()); + + if (now >= gd->arch.lastinc) /* normal (non rollover) */ + gd->arch.tbl += (now - gd->arch.lastinc); + else { + /* rollover */ + gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) + - gd->arch.lastinc) + now; + } + gd->arch.lastinc = now; + + return gd->arch.tbl; +} + +/* delay x useconds */ +void __udelay(unsigned long usec) +{ + long tmo = USEC_TO_COUNT(usec); + ulong now, last = read_timer(); + + while (tmo > 0) { + now = read_timer(); + if (now > last) /* normal (non rollover) */ + tmo -= now - last; + else /* rollover */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds new file mode 100644 index 0000000000..928b7c19e0 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2013 + * Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(s_init) +SECTIONS +{ + . = 0x00002000; + + . = ALIGN(4); + .text : + { + *(.text.s_init) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + . = .; + + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + . = ALIGN(4); + .note.gnu.build-id : + { + *(.note.gnu.build-id) + } + _end = .; + + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.note*) } +} diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds new file mode 100644 index 0000000000..53f0cbd2b7 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Based on omap-common/u-boot-spl.lds: + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } > .sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .sram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .sdram +} diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c new file mode 100644 index 0000000000..14de9f98bd --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/usbc.c @@ -0,0 +1,272 @@ +/* + * Sunxi usb-controller code shared between the ehci and musb controllers + * + * Copyright (C) 2014 Roman Byshko + * + * Roman Byshko + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_AXP152_POWER +#include +#endif +#ifdef CONFIG_AXP209_POWER +#include +#endif +#ifdef CONFIG_AXP221_POWER +#include +#endif + +#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 +#define SUNXI_USB_CSR 0x404 +#define SUNXI_USB_PASSBY_EN 1 + +#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) +#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9) +#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) +#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) + +static struct sunxi_usbc_hcd { + struct usb_hcd *hcd; + int usb_rst_mask; + int ahb_clk_mask; + int gpio_vbus; + int irq; + int id; +} sunxi_usbc_hcd[] = { + { + .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK, + .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB0, +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + .irq = 71, +#else + .irq = 38, +#endif + .id = 0, + }, + { + .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, + .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + .irq = 72, +#else + .irq = 39, +#endif + .id = 1, + }, +#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) + { + .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, + .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1, +#ifdef CONFIG_MACH_SUN6I + .irq = 74, +#else + .irq = 40, +#endif + .id = 2, + } +#endif +}; + +static int enabled_hcd_count; + +static bool use_axp_drivebus(int index) +{ + return index == 0 && + strcmp(CONFIG_USB0_VBUS_PIN, "axp_drivebus") == 0; +} + +void *sunxi_usbc_get_io_base(int index) +{ + switch (index) { + case 0: + return (void *)SUNXI_USB0_BASE; + case 1: + return (void *)SUNXI_USB1_BASE; + case 2: + return (void *)SUNXI_USB2_BASE; + default: + return NULL; + } +} + +static int get_vbus_gpio(int index) +{ + if (use_axp_drivebus(index)) + return -1; + + switch (index) { + case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN); + case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN); + case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN); + } + return -1; +} + +static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr, + int data, int len) +{ + int j = 0, usbc_bit = 0; + void *dest = sunxi_usbc_get_io_base(0) + SUNXI_USB_CSR; + + usbc_bit = 1 << (sunxi_usbc->id * 2); + for (j = 0; j < len; j++) { + /* set the bit address to be written */ + clrbits_le32(dest, 0xff << 8); + setbits_le32(dest, (addr + j) << 8); + + clrbits_le32(dest, usbc_bit); + /* set data bit */ + if (data & 0x1) + setbits_le32(dest, 1 << 7); + else + clrbits_le32(dest, 1 << 7); + + setbits_le32(dest, usbc_bit); + + clrbits_le32(dest, usbc_bit); + + data >>= 1; + } +} + +static void sunxi_usb_phy_init(struct sunxi_usbc_hcd *sunxi_usbc) +{ + /* The following comments are machine + * translated from Chinese, you have been warned! + */ + + /* Regulation 45 ohms */ + if (sunxi_usbc->id == 0) + usb_phy_write(sunxi_usbc, 0x0c, 0x01, 1); + + /* adjust PHY's magnitude and rate */ + usb_phy_write(sunxi_usbc, 0x20, 0x14, 5); + + /* threshold adjustment disconnect */ +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I + usb_phy_write(sunxi_usbc, 0x2a, 3, 2); +#else + usb_phy_write(sunxi_usbc, 0x2a, 2, 2); +#endif + + return; +} + +static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable) +{ + unsigned long bits = 0; + void *addr = sunxi_usbc_get_io_base(sunxi_usbc->id) + + SUNXI_USB_PMU_IRQ_ENABLE; + + bits = SUNXI_EHCI_AHB_ICHR8_EN | + SUNXI_EHCI_AHB_INCR4_BURST_EN | + SUNXI_EHCI_AHB_INCRX_ALIGN_EN | + SUNXI_EHCI_ULPI_BYPASS_EN; + + if (enable) + setbits_le32(addr, bits); + else + clrbits_le32(addr, bits); + + return; +} + +int sunxi_usbc_request_resources(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + + sunxi_usbc->gpio_vbus = get_vbus_gpio(index); + if (sunxi_usbc->gpio_vbus != -1) + return gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus"); + + return 0; +} + +int sunxi_usbc_free_resources(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + + if (sunxi_usbc->gpio_vbus != -1) + return gpio_free(sunxi_usbc->gpio_vbus); + + return 0; +} + +void sunxi_usbc_enable(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable common PHY only once */ + if (enabled_hcd_count == 0) + setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + + setbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask); + setbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask); +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + setbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask); +#endif + + sunxi_usb_phy_init(sunxi_usbc); + + if (sunxi_usbc->id != 0) + sunxi_usb_passby(sunxi_usbc, SUNXI_USB_PASSBY_EN); + + enabled_hcd_count++; +} + +void sunxi_usbc_disable(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (sunxi_usbc->id != 0) + sunxi_usb_passby(sunxi_usbc, !SUNXI_USB_PASSBY_EN); + +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask); +#endif + clrbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask); + clrbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask); + + /* disable common PHY only once, for the last enabled hcd */ + if (enabled_hcd_count == 1) + clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + + enabled_hcd_count--; +} + +void sunxi_usbc_vbus_enable(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + +#ifdef AXP_DRIVEBUS + if (use_axp_drivebus(index)) + axp_drivebus_enable(); +#endif + if (sunxi_usbc->gpio_vbus != -1) + gpio_direction_output(sunxi_usbc->gpio_vbus, 1); +} + +void sunxi_usbc_vbus_disable(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + +#ifdef AXP_DRIVEBUS + if (use_axp_drivebus(index)) + axp_drivebus_disable(); +#endif + if (sunxi_usbc->gpio_vbus != -1) + gpio_direction_output(sunxi_usbc->gpio_vbus, 0); +} diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c index caf9fbc155..4ae259606c 100644 --- a/arch/arm/cpu/armv7/syslib.c +++ b/arch/arm/cpu/armv7/syslib.c @@ -24,19 +24,6 @@ void sdelay(unsigned long loops) "bne 1b":"=r" (loops):"0"(loops)); } -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = readl((u32)addr) & ~(msk << start_bit); - tmp |= value << start_bit; - writel(tmp, (u32)addr); -} - /********************************************************************* * wait_on_value() - common routine to allow waiting for changes in * volatile regs. diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig new file mode 100644 index 0000000000..1446452c23 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -0,0 +1,28 @@ +if TEGRA + +choice + prompt "Tegra SoC select" + +config TEGRA20 + bool "Tegra20 family" + +config TEGRA30 + bool "Tegra30 family" + +config TEGRA114 + bool "Tegra114 family" + +config TEGRA124 + bool "Tegra124 family" + +endchoice + +config USE_PRIVATE_LIBGCC + default y if SPL_BUILD + +source "arch/arm/cpu/armv7/tegra20/Kconfig" +source "arch/arm/cpu/armv7/tegra30/Kconfig" +source "arch/arm/cpu/armv7/tegra114/Kconfig" +source "arch/arm/cpu/armv7/tegra124/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile b/arch/arm/cpu/armv7/tegra-common/Makefile index d97542d89d..463c260f18 100644 --- a/arch/arm/cpu/armv7/tegra-common/Makefile +++ b/arch/arm/cpu/armv7/tegra-common/Makefile @@ -7,26 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libtegra-common.o - -COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o diff --git a/arch/arm/cpu/armv7/tegra114/Kconfig b/arch/arm/cpu/armv7/tegra114/Kconfig new file mode 100644 index 0000000000..31012bc770 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra114/Kconfig @@ -0,0 +1,16 @@ +if TEGRA114 + +choice + prompt "Tegra114 board select" + +config TARGET_DALMORE + bool "NVIDIA Tegra114 Dalmore evaluation board" + +endchoice + +config SYS_SOC + default "tegra114" + +source "board/nvidia/dalmore/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/tegra114/Makefile b/arch/arm/cpu/armv7/tegra114/Makefile deleted file mode 100644 index eb98c8ea17..0000000000 --- a/arch/arm/cpu/armv7/tegra114/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/cpu/armv7/tegra124/Kconfig new file mode 100644 index 0000000000..88f627c932 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra124/Kconfig @@ -0,0 +1,30 @@ +if TEGRA124 + +choice + prompt "Tegra124 board select" + +config TARGET_JETSON_TK1 + bool "NVIDIA Tegra124 Jetson TK1 board" + +config TARGET_NYAN_BIG + bool "Google/NVIDIA Nyan-big Chrombook" + help + Nyan Big is a Tegra124 clamshell board that is very similar + to venice2, but it has a different panel, the sdcard CD and WP + sense are flipped, and it has a different revision of the AS3722 + PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN + (13.3-inch HD, NVIDIA Tegra K1, 2GB). + +config TARGET_VENICE2 + bool "NVIDIA Tegra124 Venice2" + +endchoice + +config SYS_SOC + default "tegra124" + +source "board/nvidia/jetson-tk1/Kconfig" +source "board/nvidia/nyan-big/Kconfig" +source "board/nvidia/venice2/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/tegra20/Kconfig b/arch/arm/cpu/armv7/tegra20/Kconfig new file mode 100644 index 0000000000..a354e2ad1f --- /dev/null +++ b/arch/arm/cpu/armv7/tegra20/Kconfig @@ -0,0 +1,52 @@ +if TEGRA20 + +choice + prompt "Tegra20 board select" + +config TARGET_HARMONY + bool "NVIDIA Tegra20 Harmony evaluation board" + +config TARGET_MEDCOM_WIDE + bool "Avionic Design Medcom-Wide board" + +config TARGET_PAZ00 + bool "Paz00 board" + +config TARGET_PLUTUX + bool "Avionic Design Plutux board" + +config TARGET_SEABOARD + bool "NVIDIA Seaboard" + +config TARGET_TEC + bool "Avionic Design Tamonten Evaluation Carrier" + +config TARGET_TRIMSLICE + bool "Compulab TrimSlice board" + +config TARGET_VENTANA + bool "NVIDIA Tegra20 Ventana evaluation board" + +config TARGET_WHISTLER + bool "NVIDIA Tegra20 Whistler evaluation board" + +config TARGET_COLIBRI_T20_IRIS + bool "Toradex Colibri T20 board" + +endchoice + +config SYS_SOC + default "tegra20" + +source "board/nvidia/harmony/Kconfig" +source "board/avionic-design/medcom-wide/Kconfig" +source "board/compal/paz00/Kconfig" +source "board/avionic-design/plutux/Kconfig" +source "board/nvidia/seaboard/Kconfig" +source "board/avionic-design/tec/Kconfig" +source "board/compulab/trimslice/Kconfig" +source "board/nvidia/ventana/Kconfig" +source "board/nvidia/whistler/Kconfig" +source "board/toradex/colibri_t20_iris/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile index 4ee8e5baf3..9b4295c72d 100644 --- a/arch/arm/cpu/armv7/tegra20/Makefile +++ b/arch/arm/cpu/armv7/tegra20/Makefile @@ -7,27 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-$(CONFIG_PWM_TEGRA) += pwm.o -COBJS-$(CONFIG_VIDEO_TEGRA) += display.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_PWM_TEGRA) += pwm.o +obj-$(CONFIG_VIDEO_TEGRA) += display.o diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c index 488f0c639d..61efed6464 100644 --- a/arch/arm/cpu/armv7/tegra20/display.c +++ b/arch/arm/cpu/armv7/tegra20/display.c @@ -45,8 +45,8 @@ static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) writel(0, &dc->win.h_initial_dda); writel(0, &dc->win.v_initial_dda); - h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1); - v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1); + h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U); + v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U); val = h_dda << H_DDA_INC_SHIFT; val |= v_dda << V_DDA_INC_SHIFT; @@ -194,7 +194,8 @@ static void rgb_enable(struct dc_com_reg *com) writel(rgb_sel_tab[i], &com->pin_output_sel[i]); } -int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config) +static int setup_window(struct disp_ctl_win *win, + struct fdt_disp_config *config) { win->x = 0; win->y = 0; @@ -328,7 +329,7 @@ static int tegra_display_decode_config(const void *blob, rgb = fdt_subnode_offset(blob, node, "rgb"); config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); - if (!config->panel_node < 0) { + if (config->panel_node < 0) { debug("%s: Cannot find panel information\n", __func__); return -1; } diff --git a/arch/arm/cpu/armv7/tegra30/Kconfig b/arch/arm/cpu/armv7/tegra30/Kconfig new file mode 100644 index 0000000000..3abdc7ba17 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra30/Kconfig @@ -0,0 +1,32 @@ +if TEGRA30 + +choice + prompt "Tegra30 board select" + +config TARGET_APALIS_T30 + bool "Toradex Apalis T30 board" + +config TARGET_BEAVER + bool "NVIDIA Tegra30 Beaver evaluation board" + +config TARGET_CARDHU + bool "NVIDIA Tegra30 Cardhu evaluation board" + +config TARGET_COLIBRI_T30 + bool "Toradex Colibri T30 board" + +config TARGET_TEC_NG + bool "Avionic Design TEC-NG board" + +endchoice + +config SYS_SOC + default "tegra30" + +source "board/toradex/apalis_t30/Kconfig" +source "board/nvidia/beaver/Kconfig" +source "board/nvidia/cardhu/Kconfig" +source "board/toradex/colibri_t30/Kconfig" +source "board/avionic-design/tec-ng/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile deleted file mode 100644 index 04adb52994..0000000000 --- a/arch/arm/cpu/armv7/tegra30/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile index 3d7a592008..fad9d4ae3a 100644 --- a/arch/arm/cpu/armv7/u8500/Makefile +++ b/arch/arm/cpu/armv7/u8500/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = timer.o clock.o prcmu.o cpu.o -SOBJS = lowlevel.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := timer.o clock.o prcmu.o cpu.o +obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig new file mode 100644 index 0000000000..0556e4b350 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -0,0 +1,94 @@ +menu "Panasonic UniPhier platform" + depends on ARCH_UNIPHIER + +config SYS_SOC + default "uniphier" + +config SYS_CONFIG_NAME + default "uniphier" + +config UNIPHIER_SMP + bool + +choice + prompt "UniPhier SoC select" + +config MACH_PH1_PRO4 + bool "PH1-Pro4" + select UNIPHIER_SMP + +config MACH_PH1_LD4 + bool "PH1-LD4" + +config MACH_PH1_SLD8 + bool "PH1-sLD8" + +endchoice + +choice + prompt "UniPhier Support Card select" + optional + +config PFC_MICRO_SUPPORT_CARD + bool "Support card with PFC CPLD" + help + This option provides support for the expansion board with PFC + original address mapping. + + Say Y to use the on-board UART, Ether, LED devices. + +config DCC_MICRO_SUPPORT_CARD + bool "Support card with DCC CPLD" + help + This option provides support for the expansion board with DCC- + arranged address mapping that is compatible with legacy UniPhier + reference boards. + + Say Y to use the on-board UART, Ether, LED devices. + +endchoice + +config CMD_PINMON + bool "Enable boot mode pins monitor command" + depends on !SPL_BUILD + default y + help + The command "pinmon" shows the state of the boot mode pins. + The boot mode pins are latched when the system reset is deasserted + and determine which device the system should load a boot image from. + +config SOC_INIT + bool + default SPL_BUILD + +config DRAM_INIT + bool + default SPL_BUILD + +config CMD_DDRPHY_DUMP + bool "Enable dump command of DDR PHY parameters" + depends on !SPL_BUILD + help + The command "ddrphy" shows the resulting parameters of DDR PHY + training; it is useful for the evaluation of DDR PHY training. + +choice + prompt "DDR3 Frequency select" + depends on DRAM_INIT + +config DDR_FREQ_1600 + bool "DDR3 1600" + depends on MACH_PH1_PRO4 || MACH_PH1_LD4 + +config DDR_FREQ_1333 + bool "DDR3 1333" + depends on MACH_PH1_LD4 || MACH_PH1_SLD8 + +endchoice + +config DDR_FREQ + int + default 1333 if DDR_FREQ_1333 + default 1600 if DDR_FREQ_1600 + +endmenu diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile new file mode 100644 index 0000000000..05462320b5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -0,0 +1,27 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +obj-y += timer.o +obj-y += reset.o +obj-y += cache_uniphier.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o +obj-y += dram_init.o +obj-$(CONFIG_DRAM_INIT) += ddrphy_training.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o +obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o +obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o +obj-$(CONFIG_UNIPHIER_SMP) += smp.o +obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o +obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o + +obj-y += board_common.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o + +obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/ +obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/ +obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/ diff --git a/arch/arm/cpu/armv7/uniphier/board_common.c b/arch/arm/cpu/armv7/uniphier/board_common.c new file mode 100644 index 0000000000..3fb26c6d84 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/board_common.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + led_write(U, B, O, O); + + return 0; +} + +#if CONFIG_NR_DRAM_BANKS >= 2 +void dram_init_banksize(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE; + gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE; + gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE; +} +#endif diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c new file mode 100644 index 0000000000..cb7e04fc36 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int board_early_init_r(void) +{ + uniphier_board_late_init(); + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/cpu/armv7/uniphier/board_late_init.c new file mode 100644 index 0000000000..0622a1e16e --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/board_late_init.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include <../drivers/mtd/nand/denali.h> + +static void nand_denali_wp_disable(void) +{ +#ifdef CONFIG_NAND_DENALI + /* + * Since the boot rom enables the write protection for NAND boot mode, + * it must be disabled somewhere for "nand write", "nand erase", etc. + * The workaround is here to not disturb the Denali NAND controller + * driver just for a really SoC-specific thing. + */ + void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + + writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT); +#endif +} + +int board_late_init(void) +{ + puts("MODE: "); + + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: + printf("eMMC Boot\n"); + setenv("bootmode", "emmcboot"); + break; + case BOOT_DEVICE_NAND: + printf("NAND Boot\n"); + setenv("bootmode", "nandboot"); + nand_denali_wp_disable(); + break; + case BOOT_DEVICE_NOR: + printf("NOR Boot\n"); + setenv("bootmode", "norboot"); + break; + default: + printf("Unsupported Boot Mode\n"); + return -1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c new file mode 100644 index 0000000000..89e44bb95b --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void __weak bcu_init(void) +{ +}; +void sbc_init(void); +void sg_init(void); +void pll_init(void); +void pin_init(void); +void clkrst_init(void); + +int board_postclk_init(void) +{ +#ifdef CONFIG_SOC_INIT + bcu_init(); + + sbc_init(); + + sg_init(); + + uniphier_board_reset(); + + pll_init(); + + uniphier_board_init(); + + led_write(B, 1, , ); + + clkrst_init(); + + led_write(B, 2, , ); +#endif + pin_init(); + + led_write(B, 3, , ); + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file mode 100644 index 0000000000..e47f977fe5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifdef CONFIG_UNIPHIER_L2CACHE_ON +static void uniphier_cache_maint_all(u32 operation) +{ + /* try until the command is successfully set */ + do { + writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM); + } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE)); + + /* wait until the operation is completed */ + while (readl(SSCOLPQS) != SSCOLPQS_EF) + ; + + /* clear the complete notification flag */ + writel(SSCOLPQS_EF, SSCOLPQS); + + writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ + readl(SSCOPE); /* need a read back to confirm */ +} + +void v7_outer_cache_flush_all(void) +{ + uniphier_cache_maint_all(SSCOQM_CM_WB_INV); +} + +void v7_outer_cache_inval_all(void) +{ + uniphier_cache_maint_all(SSCOQM_CM_INV); +} + +static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation) +{ + /* try until the command is successfully set */ + do { + writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM); + writel(start, SSCOQAD); + writel(size, SSCOQSZ); + + } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE)); + + /* wait until the operation is completed */ + while (readl(SSCOLPQS) != SSCOLPQS_EF) + ; + + /* clear the complete notification flag */ + writel(SSCOLPQS_EF, SSCOLPQS); +} + +static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) +{ + u32 size; + + /* + * If start address is not aligned to cache-line, + * do cache operation for the first cache-line + */ + start = start & ~(SSC_LINE_SIZE - 1); + + if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) { + /* this means cache operation for all range */ + uniphier_cache_maint_all(operation); + return; + } + + /* + * If end address is not aligned to cache-line, + * do cache operation for the last cache-line + */ + size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1); + + while (size) { + u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ? + SSC_RANGE_OP_MAX_SIZE : size; + __uniphier_cache_maint_range(start, chunk_size, operation); + + start += chunk_size; + size -= chunk_size; + } + + writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ + readl(SSCOPE); /* need a read back to confirm */ +} + +void v7_outer_cache_flush_range(u32 start, u32 end) +{ + uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV); +} + +void v7_outer_cache_inval_range(u32 start, u32 end) +{ + uniphier_cache_maint_range(start, end, SSCOQM_CM_INV); +} + +void v7_outer_cache_enable(void) +{ + u32 tmp; + tmp = readl(SSCC); + tmp |= SSCC_ON; + writel(tmp, SSCC); +} +#endif + +void v7_outer_cache_disable(void) +{ + u32 tmp; + tmp = readl(SSCC); + tmp &= ~SSCC_ON; + writel(tmp, SSCC); +} + +void wakeup_secondary(void); + +void enable_caches(void) +{ + uint32_t reg; + +#ifdef CONFIG_UNIPHIER_SMP + /* + * The secondary CPU must move to DDR, + * before L2 disable. + * On SPL, the Page Table is located on the L2. + */ + wakeup_secondary(); +#endif + /* + * UniPhier SoCs must use L2 cache for init stack pointer. + * We disable L2 and L1 in this order. + * If CONFIG_SYS_DCACHE_OFF is not defined, + * caches are enabled again with a new page table. + */ + + /* L2 disable */ + v7_outer_cache_disable(); + + /* L1 disable */ + reg = get_cr(); + reg &= ~(CR_C | CR_M); + set_cr(reg); + +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} diff --git a/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c b/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c new file mode 100644 index 0000000000..431d9010f1 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* Select either decimal or hexadecimal */ +#if 1 +#define PRINTF_FORMAT "%2d" +#else +#define PRINTF_FORMAT "%02x" +#endif +/* field separator */ +#define FS " " + +static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index) +{ + return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f; +} + +static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *)) +{ + int ch, p, dx; + struct ddrphy __iomem *phy; + + for (ch = 0; ch < NR_DDRCH; ch++) { + for (p = 0; p < NR_DDRPHY_PER_CH; p++) { + phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p); + + for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + printf("CH%dP%dDX%d:", ch, p, dx); + (*callback)(&phy->dx[dx]); + printf("\n"); + } + } + } +} + +static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + + for (i = 0; i < 10; i++) + printf(FS PRINTF_FORMAT, read_bdl(dx, i)); + + printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff); +} + +void wbdl_dump(void) +{ + printf("\n--- Write Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); + + dump_loop(&__wbdl_dump); +} + +static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + + for (i = 15; i < 24; i++) + printf(FS PRINTF_FORMAT, read_bdl(dx, i)); + + printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff); +} + +void rbdl_dump(void) +{ + printf("\n--- Read Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n"); + + dump_loop(&__rbdl_dump); +} + +static void __wld_dump(struct ddrphy_datx8 __iomem *dx) +{ + int rank; + u32 lcdlr0 = readl(&dx->lcdlr[0]); + u32 gtr = readl(&dx->gtr); + + for (rank = 0; rank < 4; rank++) { + u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ + u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ + + printf(FS PRINTF_FORMAT "%sT", wld, + wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1"); + } +} + +void wld_dump(void) +{ + printf("\n--- Write Leveling Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__wld_dump); +} + +static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx) +{ + int rank; + u32 lcdlr2 = readl(&dx->lcdlr[2]); + u32 gtr = readl(&dx->gtr); + + for (rank = 0; rank < 4; rank++) { + u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ + u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ + + printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl); + } +} + +void dqsgd_dump(void) +{ + printf("\n--- DQS Gating Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__dqsgd_dump); +} + +static void __mdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + u32 mdl = readl(&dx->mdlr); + for (i = 0; i < 3; i++) + printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); +} + +void mdl_dump(void) +{ + printf("\n--- Master Delay Line ---\n"); + printf(" IPRD TPRD MDLD\n"); + + dump_loop(&__mdl_dump); +} + +#define REG_DUMP(x) \ + { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \ + p - (u32 *)phy, #x, p, readl(p)); } + +void reg_dump(void) +{ + int ch, p; + struct ddrphy __iomem *phy; + + printf("\n--- DDR PHY registers ---\n"); + + for (ch = 0; ch < NR_DDRCH; ch++) { + for (p = 0; p < NR_DDRPHY_PER_CH; p++) { + printf("== Ch%d, PHY%d ==\n", ch, p); + printf(" No: Name : Address : Data\n"); + + phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p); + + REG_DUMP(ridr); + REG_DUMP(pir); + REG_DUMP(pgcr[0]); + REG_DUMP(pgcr[1]); + REG_DUMP(pgsr[0]); + REG_DUMP(pgsr[1]); + REG_DUMP(pllcr); + REG_DUMP(ptr[0]); + REG_DUMP(ptr[1]); + REG_DUMP(ptr[2]); + REG_DUMP(ptr[3]); + REG_DUMP(ptr[4]); + REG_DUMP(acmdlr); + REG_DUMP(acbdlr); + REG_DUMP(dxccr); + REG_DUMP(dsgcr); + REG_DUMP(dcr); + REG_DUMP(dtpr[0]); + REG_DUMP(dtpr[1]); + REG_DUMP(dtpr[2]); + REG_DUMP(mr0); + REG_DUMP(mr1); + REG_DUMP(mr2); + REG_DUMP(mr3); + REG_DUMP(dx[0].gcr); + REG_DUMP(dx[0].gtr); + REG_DUMP(dx[1].gcr); + REG_DUMP(dx[1].gtr); + } + } +} + +static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd = argv[1]; + + if (argc == 1) + cmd = "all"; + + if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all")) + wbdl_dump(); + + if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all")) + rbdl_dump(); + + if (!strcmp(cmd, "wld") || !strcmp(cmd, "all")) + wld_dump(); + + if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all")) + dqsgd_dump(); + + if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all")) + mdl_dump(); + + if (!strcmp(cmd, "reg") || !strcmp(cmd, "all")) + reg_dump(); + + return 0; +} + +U_BOOT_CMD( + ddr, 2, 1, do_ddr, + "UniPhier DDR PHY parameters dumper", + "- dump all of the followings\n" + "ddr wbdl - dump Write Bit Delay\n" + "ddr rbdl - dump Read Bit Delay\n" + "ddr wld - dump Write Leveling\n" + "ddr dqsgd - dump DQS Gating Delay\n" + "ddr mdl - dump Master Delay Line\n" + "ddr reg - dump registers\n" +); diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c new file mode 100644 index 0000000000..3561b40a33 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct boot_device_info *table; + u32 mode_sel, n = 0; + + mode_sel = get_boot_mode_sel(); + + printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); + + puts("Boot Mode Pin:\n"); + + for (table = boot_device_table; strlen(table->info); table++) { + printf(" %c %02x %s\n", n == mode_sel ? '*' : ' ', n, + table->info); + n++; + } + + return 0; +} + +U_BOOT_CMD( + pinmon, 1, 1, do_pinmon, + "pin monitor", + "" +); diff --git a/arch/arm/cpu/armv7/uniphier/cpu_info.c b/arch/arm/cpu/armv7/uniphier/cpu_info.c new file mode 100644 index 0000000000..86d079ad56 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/cpu_info.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int print_cpuinfo(void) +{ + u32 revision, type, model, rev, required_model = 1, required_rev = 1; + + revision = readl(SG_REVISION); + type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT; + model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT; + rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT; + + puts("CPU: "); + + switch (type) { + case 0x25: + puts("PH1-sLD3 (MN2WS0220)"); + required_model = 2; + break; + case 0x26: + puts("PH1-LD4 (MN2WS0250)"); + required_rev = 2; + break; + case 0x28: + puts("PH1-Pro4 (MN2WS0230)"); + break; + case 0x29: + puts("PH1-sLD8 (MN2WS0270)"); + break; + default: + printf("Unknown Processor ID (0x%x)\n", revision); + return -1; + } + + if (model > 1) + printf(" model %d", model); + + printf(" (rev. %d)\n", rev); + + if (model < required_model) { + printf("Sorry, this model is not supported.\n"); + printf("Required model is %d.", required_model); + return -1; + } else if (rev < required_rev) { + printf("Sorry, this revision is not supported.\n"); + printf("Required revision is %d.", required_rev); + return -1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/ddrphy_training.c b/arch/arm/cpu/armv7/uniphier/ddrphy_training.c new file mode 100644 index 0000000000..cc8b8ad648 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ddrphy_training.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) +{ + int dx; + u32 __iomem tmp, *p; + + for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + p = &phy->dx[dx].gcr; + + tmp = readl(p); + /* Specify the rank that should be write leveled */ + tmp &= ~DXGCR_WLRKEN_MASK; + tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK; + writel(tmp, p); + } + + p = &phy->dtcr; + + tmp = readl(p); + /* Specify the rank used during data bit deskew and eye centering */ + tmp &= ~DTCR_DTRANK_MASK; + tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK; + /* Use Multi-Purpose Register for DQS gate training */ + tmp |= DTCR_DTMPR; + /* Specify the rank enabled for data-training */ + tmp &= ~DTCR_RNKEN_MASK; + tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; + writel(tmp, p); +} + +struct ddrphy_init_sequence { + char *description; + u32 init_flag; + u32 done_flag; + u32 err_flag; +}; + +static struct ddrphy_init_sequence init_sequence[] = { + { + "DRAM Initialization", + PIR_DRAMRST | PIR_DRAMINIT, + PGSR0_DIDONE, + PGSR0_DIERR + }, + { + "Write Leveling", + PIR_WL, + PGSR0_WLDONE, + PGSR0_WLERR + }, + { + "Read DQS Gate Training", + PIR_QSGATE, + PGSR0_QSGDONE, + PGSR0_QSGERR + }, + { + "Write Leveling Adjustment", + PIR_WLADJ, + PGSR0_WLADONE, + PGSR0_WLAERR + }, + { + "Read Bit Deskew", + PIR_RDDSKW, + PGSR0_RDDONE, + PGSR0_RDERR + }, + { + "Write Bit Deskew", + PIR_WRDSKW, + PGSR0_WDDONE, + PGSR0_WDERR + }, + { + "Read Eye Training", + PIR_RDEYE, + PGSR0_REDONE, + PGSR0_REERR + }, + { + "Write Eye Training", + PIR_WREYE, + PGSR0_WEDONE, + PGSR0_WEERR + } +}; + +int ddrphy_training(struct ddrphy __iomem *phy) +{ + int i; + u32 pgsr0; + u32 init_flag = PIR_INIT; + u32 done_flag = PGSR0_IDONE; + int timeout = 50000; /* 50 msec is long enough */ +#ifdef DISPLAY_ELAPSED_TIME + ulong start = get_timer(0); +#endif + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + init_flag |= init_sequence[i].init_flag; + done_flag |= init_sequence[i].done_flag; + } + + writel(init_flag, &phy->pir); + + do { + if (--timeout < 0) { +#ifndef CONFIG_SPL_BUILD + printf("%s: error: timeout during DDR training\n", + __func__); +#endif + return -1; + } + udelay(1); + pgsr0 = readl(&phy->pgsr[0]); + } while ((pgsr0 & done_flag) != done_flag); + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + if (pgsr0 & init_sequence[i].err_flag) { +#ifndef CONFIG_SPL_BUILD + printf("%s: error: %s failed\n", __func__, + init_sequence[i].description); +#endif + return -1; + } + } + +#ifdef DISPLAY_ELAPSED_TIME + printf("%s: info: elapsed time %ld msec\n", get_timer(start)); +#endif + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c new file mode 100644 index 0000000000..7de657b7af --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/dram_init.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int umc_init(void); +void enable_dpll_ssc(void); + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + +#ifdef CONFIG_DRAM_INIT + led_write(B, 4, , ); + + { + int res; + + res = umc_init(); + if (res < 0) + return res; + } + led_write(B, 5, , ); + + enable_dpll_ssc(); +#endif + + led_write(B, 6, , ); + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.S b/arch/arm/cpu/armv7/uniphier/init_page_table.S new file mode 100644 index 0000000000..2638bcd779 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/init_page_table.S @@ -0,0 +1,26 @@ +#include +#include + +/* page table */ +#define NR_SECTIONS 4096 +#define SECTION_SHIFT 20 +#define DEVICE 0x00002002 /* Non-shareable Device */ +#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ + +#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT)) +#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT)) + + .section ".rodata" + .align 14 +ENTRY(init_page_table) + section = 0 + .rept NR_SECTIONS + .if section == TEXT_SECTION || section == STACK_SECTION + attr = NORMAL + .else + attr = DEVICE + .endif + .word (section << SECTION_SHIFT) | attr + section = section + 1 + .endr +END(init_page_table) diff --git a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file mode 100644 index 0000000000..c208ab67a1 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +ENTRY(lowlevel_init) + mov r8, lr @ persevere link reg across call + + /* + * The UniPhier Boot ROM loads SPL code to the L2 cache. + * But CPUs can only do instruction fetch now because start.S has + * cleared C and M bits. + * First we need to turn on MMU and Dcache again to get back + * data access to L2. + */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache + mcr p15, 0, r0, c1, c0, 0 + +#ifdef CONFIG_DEBUG_LL + bl setup_lowlevel_debug +#endif + + /* + * Now we are using the page table embedded in the Boot ROM. + * It is not handy since it is not a straight mapped table for sLD3. + * What we need to do next is to switch over to the page table in SPL. + */ + ldr r3, =init_page_table @ page table must be 16KB aligned + + /* Disable MMU and Dcache before switching Page Table */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache + mcr p15, 0, r0, c1, c0, 0 + + bl enable_mmu + +#ifdef CONFIG_UNIPHIER_SMP + /* + * ACTLR (Auxiliary Control Register) for Cortex-A9 + * bit[9] Parity on + * bit[8] Alloc in one way + * bit[7] EXCL (Exclusive cache bit) + * bit[6] SMP + * bit[3] Write full line of zeros mode + * bit[2] L1 Prefetch enable + * bit[1] L2 prefetch enable + * bit[0] FW (Cache and TLB maintenance broadcast) + */ + mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register) + orr r0, r0, #0x41 @ enable SMP, FW bit + mcr p15, 0, r0, c1, c0, 1 + + /* branch by CPU ID */ + mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register) + and r0, r0, #0x3 + cmp r0, #0x0 + beq primary_cpu + ldr r1, =ROM_BOOT_ROMRSV2 + mov r0, #0 + str r0, [r1] +0: wfe + ldr r0, [r1] + cmp r0, #0 + beq 0b + bx r0 @ r0: entry point of U-Boot main for the secondary CPU +primary_cpu: + ldr r1, =ROM_BOOT_ROMRSV2 + ldr r0, =_start @ entry for the secondary CPU + str r0, [r1] + ldr r0, [r1] @ make sure str is complete before sev + sev @ kick the sedoncary CPU + mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register + bfc r1, #0, #13 @ clear bit 12-0 + mov r0, #-1 + str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register + mov r0, #1 @ SCU enable + str r0, [r1, #SCU_CTRL] @ SCU Control Register +#endif + + bl setup_init_ram @ RAM area for temporary stack pointer + + mov lr, r8 @ restore link + mov pc, lr @ back to my caller +ENDPROC(lowlevel_init) + +ENTRY(enable_mmu) + mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register) + bic r0, r0, #0x37 + orr r0, r0, #0x20 @ disable TTBR1 + mcr p15, 0, r0, c2, c0, 2 + + orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA + mcr p15, 0, r0, c2, c0, 0 @ TTBR0 + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + + mov r0, #-1 @ manager for all domains (No permission check) + mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register) + + dsb + isb + /* + * MMU on: + * TLBs was already invalidated in "../start.S" + * So, we don't need to invalidate it here. + */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable + mcr p15, 0, r0, c1, c0, 0 + + mov pc, lr +ENDPROC(enable_mmu) + +#include + +#define BOOT_RAM_SIZE (SSC_WAY_SIZE) +#define BOOT_WAY_BITS (0x00000100) /* way 8 */ + +ENTRY(setup_init_ram) + /* + * Touch to zero for the boot way + */ +0: + /* + * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order + */ + ldr r0, = 0x00408006 @ touch to zero with address range + ldr r1, = SSCOQM + str r0, [r1] + ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address + ldr r1, = SSCOQAD + str r0, [r1] + ldr r0, = BOOT_RAM_SIZE + ldr r1, = SSCOQSZ + str r0, [r1] + ldr r0, = BOOT_WAY_BITS + ldr r1, = SSCOQWN + str r0, [r1] + ldr r1, = SSCOPPQSEF + ldr r0, [r1] + cmp r0, #0 @ check if the command is successfully set + bne 0b @ try again if an error occurres + + ldr r1, = SSCOLPQS +1: + ldr r0, [r1] + cmp r0, #0x4 + bne 1b @ wait until the operation is completed + str r0, [r1] @ clear the complete notification flag + + mov pc, lr +ENDPROC(setup_init_ram) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile new file mode 100644 index 0000000000..0752906121 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -0,0 +1,12 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o +obj-y += boot-mode.o +obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file mode 100644 index 0000000000..85f37f299b --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +void bcu_init(void) +{ + int shift; + + writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ + writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ + + /* Specify DDR channel */ + shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; + writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c new file mode 100644 index 0000000000..27d772e8cb --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int checkboard(void) +{ + puts("Board: PH1-LD4 Board\n"); + + return check_support_card(); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c new file mode 100644 index 0000000000..d359b56291 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c @@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c new file mode 100644 index 0000000000..18965a94c5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 + | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC + | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c new file mode 100644 index 0000000000..60fc5ad6ea --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8253c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a82dbc0, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000800, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S new file mode 100644 index 0000000000..c0778a0abb --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S @@ -0,0 +1,29 @@ +/* + * On-chip UART initializaion for low-level debugging + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define UART_CLK 36864000 +#include + +ENTRY(setup_lowlevel_debug) + init_debug_uart r0, r1, r2 + + /* UART Port 0 */ + set_pinsel 85, 1, r0, r1 + set_pinsel 88, 1, r0, r1 + + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] + + mov pc, lr +ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c new file mode 100644 index 0000000000..a7429402f3 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void pin_init(void) +{ + u32 tmp; + + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ + sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ + + sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ + sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ + + sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ + sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */ + sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */ + sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */ + sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */ + sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */ + sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */ + sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */ + sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */ + sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */ + sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */ + sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */ + sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */ + sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */ + sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */ + sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */ + sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */ + /* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */ +#endif + + tmp = readl(SG_IECTRL); + tmp |= 0x41; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c new file mode 100644 index 0000000000..9d51299308 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define UART_MASTER_CLK 36864000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file mode 100644 index 0000000000..b83582fee7 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#undef DPLL_SSC_RATE_1PER + +static void dpll_init(void) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT (DPLLCTRL.bit[29:20]) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x000f0000; +#if CONFIG_DDR_FREQ == 1600 + tmp |= 0x000c0000; +#elif CONFIG_DDR_FREQ == 1333 + tmp |= 0x000d0000; +#else +# error "Unknown frequency" +#endif + +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~SC_DPLLCTRL_SSC_RATE; +#else + tmp |= SC_DPLLCTRL_SSC_RATE; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); +} + +static void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c new file mode 100644 index 0000000000..837b2a891b --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c @@ -0,0 +1 @@ +#include "../ph1-pro4/pll_spectrum.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c new file mode 100644 index 0000000000..4839c943c7 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + +#if !defined(CONFIG_SPL_BUILD) + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); +#endif + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + /* base address regsiters */ + writel(0x0000bc01, SBBASE0); + writel(0x0400bc01, SBBASE1); + writel(0x0800bf01, SBBASE3); + +#if !defined(CONFIG_SPL_BUILD) + /* enable access to sub memory when boot swap is on */ + sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ +#endif + sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c new file mode 100644 index 0000000000..2cc5df608f --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void sg_init(void) +{ + u32 tmp; + + /* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE + tmp |= SG_MEMCONF_SPARSEMEM; +#endif + writel(tmp, SG_MEMCONF); + + /* Input ports must be enabled before deasserting reset of cores */ + tmp = readl(SG_IECTRL); + tmp |= 0x1; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c new file mode 100644 index 0000000000..bbc3dcb3da --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + if (freq == 1333) { + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x000FF0FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + } else if (freq == 1600) { + writel(0x36BB0F17, dramcont + UMC_CMDCTLA); + writel(0x18C6AA24, dramcont + UMC_CMDCTLB); + writel(0x5101387F, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x2F030D3F, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x43030D3F, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + } + + writel(0x00000006, dramcont + UMC_DRMMR1); + + if (freq == 1333) + writel(0x00000290, dramcont + UMC_DRMMR2); + else if (freq == 1600) + writel(0x00000298, dramcont + UMC_DRMMR2); + + writel(0x00000800, dramcont + UMC_DRMMR3); + + if (freq == 1333) { + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + } else if (freq == 1600) { + if (size == 1) + writel(0x002B0617, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x003F0617, dramcont + UMC_SPCCTLA); + + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + } + + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ + (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ + CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 +/* OK */ +#else +#error Unsupported DDR configuration. +#endif diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile new file mode 100644 index 0000000000..8206e2a354 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -0,0 +1,11 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o +obj-y += boot-mode.o +obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o +obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c new file mode 100644 index 0000000000..325a4f6160 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int checkboard(void) +{ + puts("Board: PH1-Pro4 Board\n"); + + return check_support_card(); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file mode 100644 index 0000000000..33bccff2a5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, ""} +}; + +u32 get_boot_mode_sel(void) +{ + return (readl(SG_PINMON0) >> 1) & 0x1f; +} + +u32 spl_boot_device(void) +{ + u32 boot_mode; + + if (boot_is_swapped()) + return BOOT_DEVICE_NOR; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c new file mode 100644 index 0000000000..18965a94c5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 + | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC + | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c new file mode 100644 index 0000000000..c5d1f606cf --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000000, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S new file mode 100644 index 0000000000..a793b7c118 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S @@ -0,0 +1,39 @@ +/* + * On-chip UART initializaion for low-level debugging + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define UART_CLK 73728000 +#include + +ENTRY(setup_lowlevel_debug) + ldr r0, =SC_CLKCTRL + ldr r1, [r0] + orr r1, r1, #SC_CLKCTRL_CLK_PERI + str r1, [r0] + + init_debug_uart r0, r1, r2 + + /* UART Port 0 */ + set_pinsel 127, 0, r0, r1 + set_pinsel 128, 0, r0, r1 + + ldr r0, =SG_LOADPINCTRL + mov r1, #1 + str r1, [r0] + + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] + + mov pc, lr +ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c new file mode 100644 index 0000000000..4e3d47615b --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ + sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ + sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ + sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ + sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ + sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ + sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */ + sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */ + sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */ + sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */ + sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */ + sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */ + sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */ + sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */ + sg_set_pinsel(48, 0); /* NFALE -> NFALE */ + sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */ + sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */ + sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */ + sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */ + sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */ + sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c new file mode 100644 index 0000000000..31ee2a2100 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define UART_MASTER_CLK 73728000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c new file mode 100644 index 0000000000..1db90f88a0 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#undef DPLL_SSC_RATE_1PER + +static void dpll_init(void) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT ( DPLLCTRL.bit[29:20] ) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~(0x000f0000); +#if CONFIG_DDR_FREQ == 1600 + tmp |= 0x000c0000; +#elif CONFIG_DDR_FREQ == 1333 + tmp |= 0x000d0000; +#else +# error "Unsupported frequency" +#endif + + /* + * Set Moduration rate + * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) + */ +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~0x00008000; +#else + tmp |= 0x00008000; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); +} + +static void stop_mpll(void) +{ + u32 tmp; + + tmp = readl(SC_MPLLOSCCTL); + + if (!(tmp & SC_MPLLOSCCTL_MPLLST)) + return; /* already stopped */ + + tmp &= ~SC_MPLLOSCCTL_MPLLEN; + writel(tmp, SC_MPLLOSCCTL); + + while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST) + ; +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + /* Set VPLL27A & VPLL27B */ + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + +#if defined(CONFIG_MACH_PH1_PRO4) + /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) + return; +#endif + + /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Unset VPLA_K_LD and VPLB_K_LD bit */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set VPLA_M and VPLB_M to 0x20 */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { + /* Set VPLA_K and VPLB_K for AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* wait 1 usec */ + udelay(1); + + /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Unset VPLA_SNRST and VPLB_SNRST bit */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + stop_mpll(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 1 usec in vpll_init() so 1 usec can be saved here. + */ + udelay(499); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c new file mode 100644 index 0000000000..4538d1af44 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void enable_dpll_ssc(void) +{ + u32 tmp; + + tmp = readl(SC_DPLLCTRL); + tmp |= SC_DPLLCTRL_SSC_EN; + writel(tmp, SC_DPLLCTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c new file mode 100644 index 0000000000..3c82a1aca4 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void sbc_init(void) +{ +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * + * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank + * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x3effffff: memory bank (31MB) + * 0x03f00000-0x3fffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } +#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +#if !defined(CONFIG_SPL_BUILD) + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); +#endif + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + writel(0x0000bc01, SBBASE0); /* boot memory */ + writel(0x0400bc01, SBBASE1); /* sub memory */ + writel(0x0800bf01, SBBASE3); /* peripherals */ + +#if !defined(CONFIG_SPL_BUILD) + sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ +#endif + sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ + writel(0x00000001, SG_LOADPINCTRL); + +#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c new file mode 100644 index 0000000000..b7c4b10969 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void sg_init(void) +{ + u32 tmp; + + /* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE + tmp |= SG_MEMCONF_SPARSEMEM; +#endif + writel(tmp, SG_MEMCONF); + + /* Input ports must be enabled before deasserting reset of cores */ + tmp = readl(SG_IECTRL); + tmp |= 1 << 6; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c new file mode 100644 index 0000000000..2d1bde6f13 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000001, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x07ffffff, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + + writel(0x03010100, ssif_base + UMC_HDMCHSEL); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DVCCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */ + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_HDMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_HDDRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_GIORST); + writel(0x00000001, ssif_base + UMC_HD2RST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_DVCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_VPERST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + writel(0x66bb0f17, dramcont + UMC_CMDCTLA); + writel(0x18c6aa44, dramcont + UMC_CMDCTLB); + writel(0x5101387f, dramcont + UMC_INITCTLA); + writel(0x43030d3f, dramcont + UMC_INITCTLB); + writel(0x00ff00ff, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000298, dramcont + UMC_DRMMR2); + writel(0x00000000, dramcont + UMC_DRMMR3); + writel(0x003f0617, dramcont + UMC_SPCCTLA); + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); + writel(0x04060802, dramcont + UMC_WDATACTL_D0); + writel(0x04060802, dramcont + UMC_WDATACTL_D1); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x0000000f, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00000000, dramcont + 0x0060); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00010000, dramcont + UMC_SPCSETD); + writel(0x80000020, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000103, dramcont0 + UMC_DIOCTLA); + + ddrphy_init(phy0_1, freq, size_ch0); + + ddrphy_prepare_training(phy0_1, 1); + ddrphy_training(phy0_1); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 0); + ddrphy_training(phy1_0); + + writel(0x00000103, dramcont1 + UMC_DIOCTLA); + + ddrphy_init(phy1_1, freq, size_ch1); + + ddrphy_prepare_training(phy1_1, 1); + ddrphy_training(phy1_1); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ + (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ + ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ + (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1)) +/* OK */ +#else + #error Unsupported DDR configuration. +#endif diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile new file mode 100644 index 0000000000..0752906121 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -0,0 +1,12 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o +obj-y += boot-mode.o +obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c new file mode 100644 index 0000000000..69b172e4e7 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/bcu_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c new file mode 100644 index 0000000000..15dc289c01 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int checkboard(void) +{ + puts("Board: PH1-sLD8 Board\n"); + + return check_support_card(); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c new file mode 100644 index 0000000000..d359b56291 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c @@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c new file mode 100644 index 0000000000..18965a94c5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 + | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC + | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c new file mode 100644 index 0000000000..a5eafef9a8 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, &phy->mr3); +#else + writel(0x00000800, &phy->mr3); +#endif + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S new file mode 100644 index 0000000000..a413e5fd8a --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S @@ -0,0 +1,29 @@ +/* + * On-chip UART initializaion for low-level debugging + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define UART_CLK 80000000 +#include + +ENTRY(setup_lowlevel_debug) + init_debug_uart r0, r1, r2 + + /* UART Port 0 */ + set_pinsel 70, 3, r0, r1 + set_pinsel 71, 3, r0, r1 + + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] + + mov pc, lr +ENDPROC(setup_lowlevel_debug) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c new file mode 100644 index 0000000000..2b6403f88f --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ + sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ + + sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ + + sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ + sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */ + sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */ + sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */ + sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */ + sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */ + sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */ + sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */ + sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */ + sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */ + sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */ + sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */ + sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */ + sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */ + sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */ + sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */ + sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */ + /* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */ +#endif +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c new file mode 100644 index 0000000000..ea0691dd67 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define UART_MASTER_CLK 80000000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file mode 100644 index 0000000000..4b82700f44 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static void dpll_init(void) +{ + u32 tmp; + /* + * Set DPLL SSC parameters for DPLLCTRL3 + * [23] DIVN_TEST 0x1 + * [22:16] DIVN 0x50 + * [10] FREFSEL_TEST 0x1 + * [9:8] FREFSEL 0x2 + * [4] ICPD_TEST 0x1 + * [3:0] ICPD 0xb + */ + tmp = readl(SC_DPLLCTRL3); + tmp &= ~0x00ff0717; + tmp |= 0x00d0061b; + writel(tmp, SC_DPLLCTRL3); + + /* + * Set DPLL SSC parameters for DPLLCTRL + * <-1%> <-2%> + * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) + * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x3ff07fff; +#ifdef CONFIG_DPLL_SSC_RATE_1PER + tmp |= 0x084018bf; +#else + tmp |= 0x084031a6; +#endif + writel(tmp, SC_DPLLCTRL); + + /* + * Set DPLL SSC parameters for DPLLCTRL2 + * [31:29] SSC_STEP 0 + * [27] SSC_REG_REF 1 + * [26:20] SSC_M 79 (0x4f) + * [19:0] SSC_K 964689 (0xeb851) + */ + tmp = readl(SC_DPLLCTRL2); + tmp &= ~0xefffffff; + tmp |= 0x0cfeb851; + writel(tmp, SC_DPLLCTRL2); +} + +static void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c new file mode 100644 index 0000000000..9b8c4855e5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c @@ -0,0 +1 @@ +#include "../ph1-ld4/pll_spectrum.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c new file mode 100644 index 0000000000..5efee9c505 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + +#if !defined(CONFIG_SPL_BUILD) + /* XECS0 : dummy */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); +#endif + /* XECS1 : boot memory (always boot swap = on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + + /* XECS4 : sub memory */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44); + + /* XECS5 : peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54); + + /* base address regsiters */ + writel(0x0000bc01, SBBASE0); /* boot memory */ + writel(0x0900bfff, SBBASE1); /* dummy */ + writel(0x0400bc01, SBBASE4); /* sub memory */ + writel(0x0800bf01, SBBASE5); /* peripherals */ + + sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */ + sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */ + + /* dummy read to assure write process */ + readl(SG_PINCTRL(33)); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c new file mode 100644 index 0000000000..a808289a56 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/sg_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c new file mode 100644 index 0000000000..2fbc73ab03 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ +#ifdef CONFIG_DDR_STANDARD + writel(0x55990b11, dramcont + UMC_CMDCTLA); + writel(0x16958944, dramcont + UMC_CMDCTLB); +#else + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); +#endif + + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000290, dramcont + UMC_DRMMR2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, dramcont + UMC_DRMMR3); +#else + writel(0x00000800, dramcont + UMC_DRMMR3); +#endif + + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000004f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000077, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ + (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ + CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 +/* OK */ +#else +#error Unsupported DDR configuration. +#endif diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c new file mode 100644 index 0000000000..50d1fed647 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/reset.c @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void reset_cpu(unsigned long ignored) +{ + u32 tmp; + + writel(5, SC_IRQTIMSET); /* default value */ + + tmp = readl(SC_SLFRSTSEL); + tmp &= ~0x3; /* mask [1:0] */ + tmp |= 0x0; /* XRST reboot */ + writel(tmp, SC_SLFRSTSEL); + + tmp = readl(SC_SLFRSTCTL); + tmp |= 0x1; + writel(tmp, SC_SLFRSTCTL); +} diff --git a/arch/arm/cpu/armv7/uniphier/smp.S b/arch/arm/cpu/armv7/uniphier/smp.S new file mode 100644 index 0000000000..25ba981cea --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/smp.S @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2013 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* Entry point of U-Boot main program for the secondary CPU */ +LENTRY(secondary_entry) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable + mcr p15, 0, r0, c1, c0, 0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + dsb + led_write(C,0,,) + ldr r1, =ROM_BOOT_ROMRSV2 + mov r0, #0 + str r0, [r1] +0: wfe + ldr r4, [r1] @ r4: entry point for secondary CPUs + cmp r4, #0 + beq 0b + led_write(C, P, U, 1) + bx r4 @ secondary CPUs jump to linux +ENDPROC(secondary_entry) + +ENTRY(wakeup_secondary) + ldr r1, =ROM_BOOT_ROMRSV2 +0: ldr r0, [r1] + cmp r0, #0 + bne 0b + + /* set entry address and send event to the secondary CPU */ + ldr r0, =secondary_entry + str r0, [r1] + ldr r0, [r1] @ make sure store is complete + mov r0, #0x100 +0: subs r0, r0, #1 @ I don't know the reason, but without this wait + bne 0b @ fails to wake up the secondary CPU + sev + + /* wait until the secondary CPU reach to secondary_entry */ +0: ldr r0, [r1] + cmp r0, #0 + bne 0b + bx lr +ENDPROC(wakeup_secondary) diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/cpu/armv7/uniphier/spl.c new file mode 100644 index 0000000000..40d28adaf3 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/spl.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +void spl_board_init(void) +{ +#if defined(CONFIG_BOARD_POSTCLK_INIT) + board_postclk_init(); +#endif + dram_init(); +} diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/cpu/armv7/uniphier/support_card.c new file mode 100644 index 0000000000..443224c451 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/support_card.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) + +#define PFC_MICRO_SUPPORT_CARD_RESET \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034) +#define PFC_MICRO_SUPPORT_CARD_REVISION \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0) +/* + * 0: reset deassert, 1: reset + * + * bit[0]: LAN, I2C, LED + * bit[1]: UART + */ +void support_card_reset_deassert(void) +{ + writel(0, PFC_MICRO_SUPPORT_CARD_RESET); +} + +void support_card_reset(void) +{ + writel(3, PFC_MICRO_SUPPORT_CARD_RESET); +} + +static int support_card_show_revision(void) +{ + u32 revision; + + revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION); + printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf); + return 0; +} +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) + +#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300) +#define DCC_MICRO_SUPPORT_CARD_RESET_UART \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304) +#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308) +#define DCC_MICRO_SUPPORT_CARD_REVISION \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0) + +void support_card_reset_deassert(void) +{ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */ +} + +void support_card_reset(void) +{ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */ +} + +static int support_card_show_revision(void) +{ + u32 revision; + + revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION); + + if (revision >= 0x67) { + printf("(DCC CPLD version 3.%d.%d)\n", + revision >> 4, revision & 0xf); + return 0; + } else { + printf("(DCC CPLD unknown version)\n"); + return -1; + } +} +#endif + +int check_support_card(void) +{ + printf("SC: Micro Support Card "); + return support_card_show_revision(); +} + +void support_card_init(void) +{ + /* + * After power on, we need to keep the LAN controller in reset state + * for a while. (200 usec) + * Fortunatelly, enough wait time is already inserted in pll_init() + * function. So we do not have to wait here. + */ + support_card_reset_deassert(); +} + +#if defined(CONFIG_SMC911X) +#include + +int board_eth_init(bd_t *bis) +{ + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +} +#endif + +#if !defined(CONFIG_SYS_NO_FLASH) + +#include +#include + +struct memory_bank { + phys_addr_t base; + unsigned long size; +}; + +static int mem_is_flash(const struct memory_bank *mem) +{ + const int loop = 128; + u32 *scratch_addr; + u32 saved_value; + int ret = 1; + int i; + + /* just in case, use the tail of the memory bank */ + scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, + sizeof(u32) * loop, MAP_NOCACHE); + + for (i = 0; i < loop; i++, scratch_addr++) { + saved_value = readl(scratch_addr); + writel(~saved_value, scratch_addr); + if (readl(scratch_addr) != saved_value) { + /* We assume no memory or SRAM here. */ + writel(saved_value, scratch_addr); + ret = 0; + break; + } + } + + unmap_physmem(scratch_addr, MAP_NOCACHE); + + return ret; +} + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) + /* {address, size} */ +static const struct memory_bank memory_banks_boot_swap_off[] = { + {0x02000000, 0x01f00000}, +}; + +static const struct memory_bank memory_banks_boot_swap_on[] = { + {0x00000000, 0x01f00000}, +}; +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +static const struct memory_bank memory_banks_boot_swap_off[] = { + {0x04000000, 0x02000000}, +}; + +static const struct memory_bank memory_banks_boot_swap_on[] = { + {0x00000000, 0x02000000}, + {0x04000000, 0x02000000}, +}; +#endif + +static const struct memory_bank +*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; + +phys_addr_t cfi_flash_bank_addr(int i) +{ + return flash_banks_list[i]->base; +} + +unsigned long cfi_flash_bank_size(int i) +{ + return flash_banks_list[i]->size; +} + +static void detect_num_flash_banks(void) +{ + const struct memory_bank *memory_bank, *end; + + cfi_flash_num_flash_banks = 0; + + if (boot_is_swapped()) { + memory_bank = memory_banks_boot_swap_on; + end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on); + } else { + memory_bank = memory_banks_boot_swap_off; + end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off); + } + + for (; memory_bank < end; memory_bank++) { + if (cfi_flash_num_flash_banks >= + CONFIG_SYS_MAX_FLASH_BANKS_DETECT) + break; + + if (mem_is_flash(memory_bank)) { + flash_banks_list[cfi_flash_num_flash_banks] = + memory_bank; + + debug("flash bank found: base = 0x%lx, size = 0x%lx\n", + memory_bank->base, memory_bank->size); + cfi_flash_num_flash_banks++; + } + } + + debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); +} +#else /* ONFIG_SYS_NO_FLASH */ +void detect_num_flash_banks(void) +{ +}; +#endif /* ONFIG_SYS_NO_FLASH */ + +void support_card_late_init(void) +{ + detect_num_flash_banks(); +} diff --git a/arch/arm/cpu/armv7/uniphier/timer.c b/arch/arm/cpu/armv7/uniphier/timer.c new file mode 100644 index 0000000000..6edc0842a9 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/timer.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ +#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) + +static void *get_global_timer_base(void) +{ + void *val; + + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory"); + + return val + GLOBAL_TIMER_OFFSET; +} + +unsigned long timer_read_counter(void) +{ + /* + * ARM 64bit Global Timer is too much for our purpose. + * We use only lower 32 bit of the timer counter. + */ + return readl(get_global_timer_base() + GTIMER_CNT_L); +} + +int timer_init(void) +{ + /* enable timer */ + writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL); + + return 0; +} diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile index 7d3c454d59..68cb756d67 100644 --- a/arch/arm/cpu/armv7/vf610/Makefile +++ b/arch/arm/cpu/armv7/vf610/Makefile @@ -4,26 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS += generic.o -COBJS += timer.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += generic.o +obj-y += timer.o diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index a26d63ebe0..92aaad9415 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -265,20 +265,21 @@ static char *get_reset_cause(void) cause = readl(&src_regs->srsr); writel(cause, &src_regs->srsr); - cause &= 0xff; - switch (cause) { - case 0x08: - return "WDOG"; - case 0x20: + if (cause & SRC_SRSR_POR_RST) + return "POWER ON RESET"; + else if (cause & SRC_SRSR_WDOG_A5) + return "WDOG A5"; + else if (cause & SRC_SRSR_WDOG_M4) + return "WDOG M4"; + else if (cause & SRC_SRSR_JTAG_RST) return "JTAG HIGH-Z"; - case 0x80: + else if (cause & SRC_SRSR_SW_RST) + return "SW RESET"; + else if (cause & SRC_SRSR_RESETB) return "EXTERNAL RESET"; - case 0xfd: - return "POR"; - default: + else return "unknown reset"; - } } int print_cpuinfo(void) diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c new file mode 100644 index 0000000000..ad19e4c47c --- /dev/null +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int fdt_psci(void *fdt) +{ +#ifdef CONFIG_ARMV7_PSCI + int nodeoff; + int tmp; + + nodeoff = fdt_path_offset(fdt, "/cpus"); + if (nodeoff < 0) { + printf("couldn't find /cpus\n"); + return nodeoff; + } + + /* add 'enable-method = "psci"' to each cpu node */ + for (tmp = fdt_first_subnode(fdt, nodeoff); + tmp >= 0; + tmp = fdt_next_subnode(fdt, tmp)) { + const struct fdt_property *prop; + int len; + + prop = fdt_get_property(fdt, tmp, "device_type", &len); + if (!prop) + continue; + if (len < 4) + continue; + if (strcmp(prop->data, "cpu")) + continue; + + fdt_setprop_string(fdt, tmp, "enable-method", "psci"); + } + + nodeoff = fdt_path_offset(fdt, "/psci"); + if (nodeoff < 0) { + nodeoff = fdt_path_offset(fdt, "/"); + if (nodeoff < 0) + return nodeoff; + + nodeoff = fdt_add_subnode(fdt, nodeoff, "psci"); + if (nodeoff < 0) + return nodeoff; + } + + tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci"); + if (tmp) + return tmp; + tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc"); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE); + if (tmp) + return tmp; +#endif + return 0; +} + +int armv7_update_dt(void *fdt) +{ + if (!armv7_boot_nonsec()) + return 0; +#ifndef CONFIG_ARMV7_SECURE_BASE + /* secure code lives in RAM, keep it alive */ + fdt_add_mem_rsv(fdt, (unsigned long)__secure_start, + __secure_end - __secure_start); +#endif + + return fdt_psci(fdt); +} diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c new file mode 100644 index 0000000000..b69fd37c18 --- /dev/null +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2013 + * Andre Przywara, Linaro + * + * Routines to transition ARMv7 processors from secure into non-secure state + * and from non-secure SVC into HYP mode + * needed to enable ARMv7 virtualization for current hypervisors + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static unsigned int read_id_pfr1(void) +{ + unsigned int reg; + + asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); + return reg; +} + +static unsigned long get_gicd_base_address(void) +{ +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; +#else + unsigned periphbase; + + /* get the GIC base address from the CBAR register */ + asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); + + /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to + * encode this). Bail out here since we cannot access this without + * enabling paging. + */ + if ((periphbase & 0xff) != 0) { + printf("nonsec: PERIPHBASE is above 4 GB, no access.\n"); + return -1; + } + + return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; +#endif +} + +static void relocate_secure_section(void) +{ +#ifdef CONFIG_ARMV7_SECURE_BASE + size_t sz = __secure_end - __secure_start; + + memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); + flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, + CONFIG_ARMV7_SECURE_BASE + sz + 1); + invalidate_icache_all(); +#endif +} + +static void kick_secondary_cpus_gic(unsigned long gicdaddr) +{ + /* kick all CPUs (except this one) by writing to GICD_SGIR */ + writel(1U << 24, gicdaddr + GICD_SGIR); +} + +void __weak smp_kick_all_cpus(void) +{ + unsigned long gic_dist_addr; + + gic_dist_addr = get_gicd_base_address(); + if (gic_dist_addr == -1) + return; + + kick_secondary_cpus_gic(gic_dist_addr); +} + +int armv7_init_nonsec(void) +{ + unsigned int reg; + unsigned itlinesnr, i; + unsigned long gic_dist_addr; + + /* check whether the CPU supports the security extensions */ + reg = read_id_pfr1(); + if ((reg & 0xF0) == 0) { + printf("nonsec: Security extensions not implemented.\n"); + return -1; + } + + /* the SCR register will be set directly in the monitor mode handler, + * according to the spec one should not tinker with it in secure state + * in SVC mode. Do not try to read it once in non-secure state, + * any access to it will trap. + */ + + gic_dist_addr = get_gicd_base_address(); + if (gic_dist_addr == -1) + return -1; + + /* enable the GIC distributor */ + writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, + gic_dist_addr + GICD_CTLR); + + /* TYPER[4:0] contains an encoded number of available interrupts */ + itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f; + + /* set all bits in the GIC group registers to one to allow access + * from non-secure state. The first 32 interrupts are private per + * CPU and will be set later when enabling the GIC for each core + */ + for (i = 1; i <= itlinesnr; i++) + writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); + +#ifndef CONFIG_ARMV7_PSCI + smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); + smp_kick_all_cpus(); +#endif + + /* call the non-sec switching code on this CPU also */ + relocate_secure_section(); + secure_ram_addr(_nonsec_init)(); + return 0; +} diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig new file mode 100644 index 0000000000..3a52535ce0 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/Kconfig @@ -0,0 +1,39 @@ +if ZYNQ + +choice + prompt "Xilinx Zynq board select" + +config TARGET_ZYNQ_ZED + bool "Zynq ZedBoard" + +config TARGET_ZYNQ_MICROZED + bool "Zynq MicroZed" + +config TARGET_ZYNQ_ZC70X + bool "Zynq ZC702/ZC706 Board" + +config TARGET_ZYNQ_ZC770 + bool "Zynq ZC770 Board" + +config TARGET_ZYNQ_ZYBO + bool "Zynq Zybo Board" + +endchoice + +config SYS_BOARD + default "zynq" + +config SYS_VENDOR + default "xilinx" + +config SYS_SOC + default "zynq" + +config SYS_CONFIG_NAME + default "zynq_zed" if TARGET_ZYNQ_ZED + default "zynq_microzed" if TARGET_ZYNQ_MICROZED + default "zynq_zc70x" if TARGET_ZYNQ_ZC70X + default "zynq_zc770" if TARGET_ZYNQ_ZC770 + default "zynq_zybo" if TARGET_ZYNQ_ZYBO + +endif diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile index e5494f7489..901f2ce4cb 100644 --- a/arch/arm/cpu/armv7/zynq/Makefile +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -8,29 +8,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y := timer.o -COBJS-y += cpu.o -COBJS-y += slcr.o - -COBJS := $(COBJS-y) - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := timer.o +obj-y += cpu.o +obj-y += ddrc.o +obj-y += slcr.o +obj-y += clk.o +obj-y += lowlevel_init.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c new file mode 100644 index 0000000000..d2885dc2b9 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/clk.c @@ -0,0 +1,664 @@ +/* + * Copyright (C) 2013 Soren Brinkmann + * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +/* Board oscillator frequency */ +#ifndef CONFIG_ZYNQ_PS_CLK_FREQ +# define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL +#endif + +/* Register bitfield defines */ +#define PLLCTRL_FBDIV_MASK 0x7f000 +#define PLLCTRL_FBDIV_SHIFT 12 +#define PLLCTRL_BPFORCE_MASK (1 << 4) +#define PLLCTRL_PWRDWN_MASK 2 +#define PLLCTRL_PWRDWN_SHIFT 1 +#define PLLCTRL_RESET_MASK 1 +#define PLLCTRL_RESET_SHIFT 0 + +#define ZYNQ_CLK_MAXDIV 0x3f +#define CLK_CTRL_DIV1_SHIFT 20 +#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT) +#define CLK_CTRL_DIV0_SHIFT 8 +#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) +#define CLK_CTRL_SRCSEL_SHIFT 4 +#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT) + +#define CLK_CTRL_DIV2X_SHIFT 26 +#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT) +#define CLK_CTRL_DIV3X_SHIFT 20 +#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT) + +#define ZYNQ_CLKMUX_SEL_0 0 +#define ZYNQ_CLKMUX_SEL_1 1 +#define ZYNQ_CLKMUX_SEL_2 2 +#define ZYNQ_CLKMUX_SEL_3 3 + +DECLARE_GLOBAL_DATA_PTR; + +struct clk; + +/** + * struct clk_ops: + * @set_rate: Function pointer to set_rate() implementation + * @get_rate: Function pointer to get_rate() implementation + */ +struct clk_ops { + int (*set_rate)(struct clk *clk, unsigned long rate); + unsigned long (*get_rate)(struct clk *clk); +}; + +/** + * struct clk: + * @name: Clock name + * @frequency: Currenct frequency + * @parent: Parent clock + * @flags: Clock flags + * @reg: Clock control register + * @ops: Clock operations + */ +struct clk { + char *name; + unsigned long frequency; + enum zynq_clk parent; + unsigned int flags; + u32 *reg; + struct clk_ops ops; +}; +#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1 + +static struct clk clks[clk_max]; + +/** + * __zynq_clk_cpu_get_parent() - Decode clock multiplexer + * @srcsel: Mux select value + * Returns the clock identifier associated with the selected mux input. + */ +static int __zynq_clk_cpu_get_parent(unsigned int srcsel) +{ + unsigned int ret; + + switch (srcsel) { + case ZYNQ_CLKMUX_SEL_0: + case ZYNQ_CLKMUX_SEL_1: + ret = armpll_clk; + break; + case ZYNQ_CLKMUX_SEL_2: + ret = ddrpll_clk; + break; + case ZYNQ_CLKMUX_SEL_3: + ret = iopll_clk; + break; + default: + ret = armpll_clk; + break; + } + + return ret; +} + +/** + * ddr2x_get_rate() - Get clock rate of DDR2x clock + * @clk: Clock handle + * Returns the current clock rate of @clk. + */ +static unsigned long ddr2x_get_rate(struct clk *clk) +{ + u32 clk_ctrl = readl(clk->reg); + u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT; + + return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div); +} + +/** + * ddr3x_get_rate() - Get clock rate of DDR3x clock + * @clk: Clock handle + * Returns the current clock rate of @clk. + */ +static unsigned long ddr3x_get_rate(struct clk *clk) +{ + u32 clk_ctrl = readl(clk->reg); + u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT; + + return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div); +} + +static void init_ddr_clocks(void) +{ + u32 div0, div1; + unsigned long prate = zynq_clk_get_rate(ddrpll_clk); + u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); + + /* DDR2x */ + clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl; + clks[ddr2x_clk].parent = ddrpll_clk; + clks[ddr2x_clk].name = "ddr_2x"; + clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]); + clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate; + + /* DDR3x */ + clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl; + clks[ddr3x_clk].parent = ddrpll_clk; + clks[ddr3x_clk].name = "ddr_3x"; + clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]); + clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate; + + /* DCI */ + clk_ctrl = readl(&slcr_base->dci_clk_ctrl); + div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; + clks[dci_clk].reg = &slcr_base->dci_clk_ctrl; + clks[dci_clk].parent = ddrpll_clk; + clks[dci_clk].frequency = DIV_ROUND_CLOSEST( + DIV_ROUND_CLOSEST(prate, div0), div1); + clks[dci_clk].name = "dci"; + + gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000; +} + +static void init_cpu_clocks(void) +{ + int clk_621; + u32 reg, div, srcsel; + enum zynq_clk parent; + + reg = readl(&slcr_base->arm_clk_ctrl); + clk_621 = readl(&slcr_base->clk_621_true) & 1; + div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + parent = __zynq_clk_cpu_get_parent(srcsel); + + /* cpu clocks */ + clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl; + clks[cpu_6or4x_clk].parent = parent; + clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST( + zynq_clk_get_rate(parent), div); + clks[cpu_6or4x_clk].name = "cpu_6or4x"; + + clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl; + clks[cpu_3or2x_clk].parent = cpu_6or4x_clk; + clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2; + clks[cpu_3or2x_clk].name = "cpu_3or2x"; + + clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl; + clks[cpu_2x_clk].parent = cpu_6or4x_clk; + clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / + (2 + clk_621); + clks[cpu_2x_clk].name = "cpu_2x"; + + clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl; + clks[cpu_1x_clk].parent = cpu_6or4x_clk; + clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / + (4 + 2 * clk_621); + clks[cpu_1x_clk].name = "cpu_1x"; +} + +/** + * periph_calc_two_divs() - Calculate clock dividers + * @cur_rate: Current clock rate + * @tgt_rate: Target clock rate + * @prate: Parent clock rate + * @div0: First divider (output) + * @div1: Second divider (output) + * Returns the actual clock rate possible. + * + * Calculates clock dividers for clocks with two 6-bit dividers. + */ +static unsigned long periph_calc_two_divs(unsigned long cur_rate, + unsigned long tgt_rate, unsigned long prate, u32 *div0, + u32 *div1) +{ + long err, best_err = (long)(~0UL >> 1); + unsigned long rate, best_rate = 0; + u32 d0, d1; + + for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) { + for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) { + rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0), + d1); + err = abs(rate - tgt_rate); + + if (err < best_err) { + *div0 = d0; + *div1 = d1; + best_err = err; + best_rate = rate; + } + } + } + + return best_rate; +} + +/** + * zynq_clk_periph_set_rate() - Set clock rate + * @clk: Handle of the peripheral clock + * @rate: New clock rate + * Sets the clock frequency of @clk to @rate. Returns zero on success. + */ +static int zynq_clk_periph_set_rate(struct clk *clk, + unsigned long rate) +{ + u32 ctrl, div0 = 0, div1 = 0; + unsigned long prate, new_rate, cur_rate = clk->frequency; + + ctrl = readl(clk->reg); + prate = zynq_clk_get_rate(clk->parent); + ctrl &= ~CLK_CTRL_DIV0_MASK; + + if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) { + ctrl &= ~CLK_CTRL_DIV1_MASK; + new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0, + &div1); + ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; + } else { + div0 = DIV_ROUND_CLOSEST(prate, rate); + div0 &= ZYNQ_CLK_MAXDIV; + new_rate = DIV_ROUND_CLOSEST(rate, div0); + } + + /* write new divs to hardware */ + ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; + writel(ctrl, clk->reg); + + /* update frequency in clk framework */ + clk->frequency = new_rate; + + return 0; +} + +/** + * zynq_clk_periph_get_rate() - Get clock rate + * @clk: Handle of the peripheral clock + * Returns the current clock rate of @clk. + */ +static unsigned long zynq_clk_periph_get_rate(struct clk *clk) +{ + u32 clk_ctrl = readl(clk->reg); + u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + u32 div1 = 1; + + if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) + div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; + + /* a register value of zero == division by 1 */ + if (!div0) + div0 = 1; + if (!div1) + div1 = 1; + + return + DIV_ROUND_CLOSEST( + DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0), + div1); +} + +/** + * __zynq_clk_periph_get_parent() - Decode clock multiplexer + * @srcsel: Mux select value + * Returns the clock identifier associated with the selected mux input. + */ +static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel) +{ + switch (srcsel) { + case ZYNQ_CLKMUX_SEL_0: + case ZYNQ_CLKMUX_SEL_1: + return iopll_clk; + case ZYNQ_CLKMUX_SEL_2: + return armpll_clk; + case ZYNQ_CLKMUX_SEL_3: + return ddrpll_clk; + default: + return 0; + } +} + +/** + * zynq_clk_periph_get_parent() - Decode clock multiplexer + * @clk: Clock handle + * Returns the clock identifier associated with the selected mux input. + */ +static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk) +{ + u32 clk_ctrl = readl(clk->reg); + u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + + return __zynq_clk_periph_get_parent(srcsel); +} + +/** + * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework + * @clk: Pointer to struct clk for the clock + * @ctrl: Clock control register + * @name: PLL name + * @two_divs: Indicates whether the clock features one or two dividers + */ +static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name, + bool two_divs) +{ + clk->name = name; + clk->reg = ctrl; + if (two_divs) + clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS; + clk->parent = zynq_clk_periph_get_parent(clk); + clk->frequency = zynq_clk_periph_get_rate(clk); + clk->ops.get_rate = zynq_clk_periph_get_rate; + clk->ops.set_rate = zynq_clk_periph_set_rate; + + return 0; +} + +static void init_periph_clocks(void) +{ + zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl, + "gem0", 1); + zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl, + "gem1", 1); + + zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl, + "smc", 0); + + zynq_clk_register_periph_clk(&clks[lqspi_clk], + &slcr_base->lqspi_clk_ctrl, "lqspi", 0); + + zynq_clk_register_periph_clk(&clks[sdio0_clk], + &slcr_base->sdio_clk_ctrl, "sdio0", 0); + zynq_clk_register_periph_clk(&clks[sdio1_clk], + &slcr_base->sdio_clk_ctrl, "sdio1", 0); + + zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl, + "spi0", 0); + zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl, + "spi1", 0); + + zynq_clk_register_periph_clk(&clks[uart0_clk], + &slcr_base->uart_clk_ctrl, "uart0", 0); + zynq_clk_register_periph_clk(&clks[uart1_clk], + &slcr_base->uart_clk_ctrl, "uart1", 0); + + zynq_clk_register_periph_clk(&clks[dbg_trc_clk], + &slcr_base->dbg_clk_ctrl, "dbg_trc", 0); + zynq_clk_register_periph_clk(&clks[dbg_apb_clk], + &slcr_base->dbg_clk_ctrl, "dbg_apb", 0); + + zynq_clk_register_periph_clk(&clks[pcap_clk], + &slcr_base->pcap_clk_ctrl, "pcap", 0); + + zynq_clk_register_periph_clk(&clks[fclk0_clk], + &slcr_base->fpga0_clk_ctrl, "fclk0", 1); + zynq_clk_register_periph_clk(&clks[fclk1_clk], + &slcr_base->fpga1_clk_ctrl, "fclk1", 1); + zynq_clk_register_periph_clk(&clks[fclk2_clk], + &slcr_base->fpga2_clk_ctrl, "fclk2", 1); + zynq_clk_register_periph_clk(&clks[fclk3_clk], + &slcr_base->fpga3_clk_ctrl, "fclk3", 1); +} + +/** + * zynq_clk_register_aper_clk() - Set up a APER clock with the framework + * @clk: Pointer to struct clk for the clock + * @ctrl: Clock control register + * @name: PLL name + */ +static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name) +{ + clk->name = name; + clk->reg = ctrl; + clk->parent = cpu_1x_clk; + clk->frequency = zynq_clk_get_rate(clk->parent); +} + +static void init_aper_clocks(void) +{ + zynq_clk_register_aper_clk(&clks[usb0_aper_clk], + &slcr_base->aper_clk_ctrl, "usb0_aper"); + zynq_clk_register_aper_clk(&clks[usb1_aper_clk], + &slcr_base->aper_clk_ctrl, "usb1_aper"); + + zynq_clk_register_aper_clk(&clks[gem0_aper_clk], + &slcr_base->aper_clk_ctrl, "gem0_aper"); + zynq_clk_register_aper_clk(&clks[gem1_aper_clk], + &slcr_base->aper_clk_ctrl, "gem1_aper"); + + zynq_clk_register_aper_clk(&clks[sdio0_aper_clk], + &slcr_base->aper_clk_ctrl, "sdio0_aper"); + zynq_clk_register_aper_clk(&clks[sdio1_aper_clk], + &slcr_base->aper_clk_ctrl, "sdio1_aper"); + + zynq_clk_register_aper_clk(&clks[spi0_aper_clk], + &slcr_base->aper_clk_ctrl, "spi0_aper"); + zynq_clk_register_aper_clk(&clks[spi1_aper_clk], + &slcr_base->aper_clk_ctrl, "spi1_aper"); + + zynq_clk_register_aper_clk(&clks[can0_aper_clk], + &slcr_base->aper_clk_ctrl, "can0_aper"); + zynq_clk_register_aper_clk(&clks[can1_aper_clk], + &slcr_base->aper_clk_ctrl, "can1_aper"); + + zynq_clk_register_aper_clk(&clks[i2c0_aper_clk], + &slcr_base->aper_clk_ctrl, "i2c0_aper"); + zynq_clk_register_aper_clk(&clks[i2c1_aper_clk], + &slcr_base->aper_clk_ctrl, "i2c1_aper"); + + zynq_clk_register_aper_clk(&clks[uart0_aper_clk], + &slcr_base->aper_clk_ctrl, "uart0_aper"); + zynq_clk_register_aper_clk(&clks[uart1_aper_clk], + &slcr_base->aper_clk_ctrl, "uart1_aper"); + + zynq_clk_register_aper_clk(&clks[gpio_aper_clk], + &slcr_base->aper_clk_ctrl, "gpio_aper"); + + zynq_clk_register_aper_clk(&clks[lqspi_aper_clk], + &slcr_base->aper_clk_ctrl, "lqspi_aper"); + + zynq_clk_register_aper_clk(&clks[smc_aper_clk], + &slcr_base->aper_clk_ctrl, "smc_aper"); +} + +/** + * __zynq_clk_pll_get_rate() - Get PLL rate + * @addr: Address of the PLL's control register + * Returns the current PLL output rate. + */ +static unsigned long __zynq_clk_pll_get_rate(u32 *addr) +{ + u32 reg, mul, bypass; + + reg = readl(addr); + bypass = reg & PLLCTRL_BPFORCE_MASK; + if (bypass) + mul = 1; + else + mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; + + return CONFIG_ZYNQ_PS_CLK_FREQ * mul; +} + +/** + * zynq_clk_pll_get_rate() - Get PLL rate + * @pll: Handle of the PLL + * Returns the current clock rate of @pll. + */ +static unsigned long zynq_clk_pll_get_rate(struct clk *pll) +{ + return __zynq_clk_pll_get_rate(pll->reg); +} + +/** + * zynq_clk_register_pll() - Set up a PLL with the framework + * @clk: Pointer to struct clk for the PLL + * @ctrl: PLL control register + * @name: PLL name + * @prate: PLL input clock rate + */ +static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name, + unsigned long prate) +{ + clk->name = name; + clk->reg = ctrl; + clk->frequency = zynq_clk_pll_get_rate(clk); + clk->ops.get_rate = zynq_clk_pll_get_rate; +} + +/** + * clkid_2_register() - Get clock control register + * @id: Clock identifier of one of the PLLs + * Returns the address of the requested PLL's control register. + */ +static u32 *clkid_2_register(enum zynq_clk id) +{ + switch (id) { + case armpll_clk: + return &slcr_base->arm_pll_ctrl; + case ddrpll_clk: + return &slcr_base->ddr_pll_ctrl; + case iopll_clk: + return &slcr_base->io_pll_ctrl; + default: + return &slcr_base->io_pll_ctrl; + } +} + +/* API */ +/** + * zynq_clk_early_init() - Early init for the clock framework + * + * This function is called from before relocation and sets up the CPU clock + * frequency in the global data struct. + */ +void zynq_clk_early_init(void) +{ + u32 reg = readl(&slcr_base->arm_clk_ctrl); + u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel); + u32 *pllreg = clkid_2_register(parent); + unsigned long prate = __zynq_clk_pll_get_rate(pllreg); + + if (!div) + div = 1; + + gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div); +} + +/** + * get_uart_clk() - Get UART input frequency + * @dev_index: UART ID + * Returns UART input clock frequency in Hz. + * + * Compared to zynq_clk_get_rate() this function is designed to work before + * relocation and can be called when the serial UART is set up. + */ +unsigned long get_uart_clk(int dev_index) +{ + u32 reg = readl(&slcr_base->uart_clk_ctrl); + u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel); + u32 *pllreg = clkid_2_register(parent); + unsigned long prate = __zynq_clk_pll_get_rate(pllreg); + + if (!div) + div = 1; + + return DIV_ROUND_CLOSEST(prate, div); +} + +/** + * set_cpu_clk_info() - Initialize clock framework + * Always returns zero. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl, + "armpll", CONFIG_ZYNQ_PS_CLK_FREQ); + zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl, + "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ); + zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl, + "iopll", CONFIG_ZYNQ_PS_CLK_FREQ); + + init_ddr_clocks(); + init_cpu_clocks(); + init_periph_clocks(); + init_aper_clocks(); + + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + gd->bd->bi_dsp_freq = 0; + + return 0; +} + +/** + * zynq_clk_get_rate() - Get clock rate + * @clk: Clock identifier + * Returns the current clock rate of @clk on success or zero for an invalid + * clock id. + */ +unsigned long zynq_clk_get_rate(enum zynq_clk clk) +{ + if (clk < 0 || clk >= clk_max) + return 0; + + return clks[clk].frequency; +} + +/** + * zynq_clk_set_rate() - Set clock rate + * @clk: Clock identifier + * @rate: Requested clock rate + * Passes on the return value from the clock's set_rate() function or negative + * errno. + */ +int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate) +{ + if (clk < 0 || clk >= clk_max) + return -ENODEV; + + if (clks[clk].ops.set_rate) + return clks[clk].ops.set_rate(&clks[clk], rate); + + return -ENXIO; +} + +/** + * zynq_clk_get_name() - Get clock name + * @clk: Clock identifier + * Returns the name of @clk. + */ +const char *zynq_clk_get_name(enum zynq_clk clk) +{ + return clks[clk].name; +} + +/** + * soc_clk_dump() - Print clock frequencies + * Returns zero on success + * + * Implementation for the clk dump command. + */ +int soc_clk_dump(void) +{ + int i; + + printf("clk\t\tfrequency\n"); + for (i = 0; i < clk_max; i++) { + const char *name = zynq_clk_get_name(i); + if (name) + printf("%10s%20lu\n", name, zynq_clk_get_rate(i)); + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/zynq/config.mk b/arch/arm/cpu/armv7/zynq/config.mk new file mode 100644 index 0000000000..778a377e8a --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 +# +# Allow NEON instructions (needed for lowlevel_init.S with GNU toolchain) +PLATFORM_RELFLAGS += -mfpu=neon diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 4367d1afac..914b1feb68 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -2,35 +2,53 @@ * Copyright (C) 2012 Michal Simek * Copyright (C) 2012 Xilinx, Inc. All rights reserved. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include #include #include -void lowlevel_init(void) +#define ZYNQ_SILICON_VER_MASK 0xF0000000 +#define ZYNQ_SILICON_VER_SHIFT 28 + +int arch_cpu_init(void) { zynq_slcr_unlock(); - /* remap DDR to zero, FILTERSTART */ - writel(0, &scu_base->filter_start); - +#ifndef CONFIG_SPL_BUILD /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); +#if (CONFIG_SYS_SDRAM_BASE == 0) + /* remap DDR to zero, FILTERSTART */ + writel(0, &scu_base->filter_start); + /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ writel(0x1F, &slcr_base->ocm_cfg); /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ writel(0x0, &slcr_base->fpga_rst_ctrl); - /* TZ_DDR_RAM, Set DDR trust zone non-secure */ - writel(0xFFFFFFFF, &slcr_base->trust_zone); /* Set urgent bits with register */ writel(0x0, &slcr_base->ddr_urgent_sel); /* Urgent write, ports S2/S3 */ writel(0xC, &slcr_base->ddr_urgent); - +#endif +#endif + zynq_clk_early_init(); zynq_slcr_lock(); + + return 0; +} + +unsigned int zynq_get_silicon_version(void) +{ + unsigned int ver; + + ver = (readl(&devcfg_base->mctrl) & + ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT; + + return ver; } void reset_cpu(ulong addr) @@ -39,3 +57,11 @@ void reset_cpu(ulong addr) while (1) ; } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c new file mode 100644 index 0000000000..5b20accbcb --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 - 2013 Michal Simek + * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Control regsiter bitfield definitions */ +#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC +#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2 +#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1 + +/* ECC scrub regsiter definitions */ +#define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7 +#define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4 + +void zynq_ddrc_init(void) +{ + u32 width, ecctype; + + width = readl(&ddrc_base->ddrc_ctrl); + width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >> + ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT; + ecctype = (readl(&ddrc_base->ecc_scrub) & + ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK); + + /* ECC is enabled when memory is in 16bit mode and it is enabled */ + if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && + (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { + puts("ECC enabled "); + /* + * Clear the first 1MB because it is not initialized from + * first stage bootloader. To get ECC to work all memory has + * been initialized by writing any value. + */ + /* cppcheck-suppress nullPointer */ + memset((void *)0, 0, 1 * 1024 * 1024); + + gd->ram_size /= 2; + } else { + puts("ECC disabled "); + } +} diff --git a/arch/arm/cpu/armv7/zynq/lowlevel_init.S b/arch/arm/cpu/armv7/zynq/lowlevel_init.S new file mode 100644 index 0000000000..6d714b711c --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/lowlevel_init.S @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +ENTRY(lowlevel_init) + + /* Enable the the VFP */ + mrc p15, 0, r1, c1, c0, 2 + orr r1, r1, #(0x3 << 20) + orr r1, r1, #(0x3 << 20) + mcr p15, 0, r1, c1, c0, 2 + isb + fmrx r1, FPEXC + orr r1,r1, #(1<<30) + fmxr FPEXC, r1 + + /* Move back to caller */ + mov pc, lr + +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index e5fe992982..2521589c07 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -8,25 +8,75 @@ #include #include #include +#include +#include #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D +#define SLCR_USB_L1_SEL 0x04 + #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const int usb0_pins[] = { + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 +}; + +static const int usb1_pins[] = { + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51 +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { + { + "usb0", + usb0_pins, + ARRAY_SIZE(usb0_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, + { + "usb1", + usb1_pins, + ARRAY_SIZE(usb1_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, +}; + static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) { - if (!slcr_lock) + if (!slcr_lock) { writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); + slcr_lock = 1; + } } void zynq_slcr_unlock(void) { - if (slcr_lock) + if (slcr_lock) { writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); + slcr_lock = 0; + } } /* Reset the entire system */ @@ -50,8 +100,10 @@ void zynq_slcr_cpu_reset(void) } /* Setup clk for network */ -void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) +void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) { + int ret; + zynq_slcr_unlock(); if (gem_id > 1) { @@ -59,18 +111,18 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) goto out; } + ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate); + if (ret) + goto out; + if (gem_id) { - /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ - writel(clk, &slcr_base->gem1_clk_ctrl); /* Configure GEM_RCLK_CTRL */ - writel(rclk, &slcr_base->gem1_rclk_ctrl); + writel(1, &slcr_base->gem1_rclk_ctrl); } else { - /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ - writel(clk, &slcr_base->gem0_clk_ctrl); /* Configure GEM_RCLK_CTRL */ - writel(rclk, &slcr_base->gem0_rclk_ctrl); + writel(1, &slcr_base->gem0_rclk_ctrl); } - + udelay(100000); out: zynq_slcr_lock(); } @@ -79,8 +131,8 @@ void zynq_slcr_devcfg_disable(void) { zynq_slcr_unlock(); - /* Disable AXI interface */ - writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); + /* Disable AXI interface by asserting FPGA resets */ + writel(0xF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ writel(0xA, &slcr_base->lvl_shftr_en); @@ -95,14 +147,50 @@ void zynq_slcr_devcfg_enable(void) /* Set Level Shifters DT618760 */ writel(0xF, &slcr_base->lvl_shftr_en); - /* Disable AXI interface */ + /* Enable AXI interface by de-asserting FPGA resets */ writel(0x0, &slcr_base->fpga_rst_ctrl); zynq_slcr_lock(); } +u32 zynq_slcr_get_boot_mode(void) +{ + /* Get the bootmode register value */ + return readl(&slcr_base->boot_mode); +} + u32 zynq_slcr_get_idcode(void) { return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> SLCR_IDCODE_SHIFT; } + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c new file mode 100644 index 0000000000..b80c35794a --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2014 Xilinx, Inc. Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong dummy) +{ + ps7_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + preloader_console_init(); + arch_cpu_init(); + board_init_r(NULL, 0); +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + board_init(); +} +#endif + +u32 spl_boot_device(void) +{ + u32 mode; + + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { +#ifdef CONFIG_SPL_SPI_SUPPORT + case ZYNQ_BM_QSPI: + puts("qspi boot\n"); + mode = BOOT_DEVICE_SPI; + break; +#endif + case ZYNQ_BM_NAND: + mode = BOOT_DEVICE_NAND; + break; + case ZYNQ_BM_NOR: + mode = BOOT_DEVICE_NOR; + break; +#ifdef CONFIG_SPL_MMC_SUPPORT + case ZYNQ_BM_SD: + puts("mmc boot\n"); + mode = BOOT_DEVICE_MMC1; + break; +#endif + case ZYNQ_BM_JTAG: + mode = BOOT_DEVICE_RAM; + break; + default: + puts("Unsupported boot mode selected\n"); + hang(); + } + + return mode; +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_FS; +} +#endif + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* boot linux */ + return 0; +} +#endif + +__weak void ps7_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/ps7_init.c, if it exists. + */ +} diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c index 0133565299..303dbcfcea 100644 --- a/arch/arm/cpu/armv7/zynq/timer.c +++ b/arch/arm/cpu/armv7/zynq/timer.c @@ -22,13 +22,14 @@ * Sysgo Real-Time Solutions, GmbH * Alex Zuepke * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -48,7 +49,6 @@ static struct scu_timer *timer_base = #define TIMER_LOAD_VAL 0xFFFFFFFF #define TIMER_PRESCALE 255 -#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE) int timer_init(void) { @@ -56,8 +56,10 @@ int timer_init(void) (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) | SCUTIMER_CONTROL_ENABLE_MASK; + gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1); + /* Load the timer counter register */ - writel(0xFFFFFFFF, &timer_base->counter); + writel(0xFFFFFFFF, &timer_base->load); /* * Start the A9Timer device @@ -69,7 +71,7 @@ int timer_init(void) /* Reset time */ gd->arch.lastinc = readl(&timer_base->counter) / - (TIMER_TICK_HZ / CONFIG_SYS_HZ); + (gd->arch.timer_rate_hz / CONFIG_SYS_HZ); gd->arch.tbl = 0; return 0; @@ -83,14 +85,15 @@ ulong get_timer_masked(void) { ulong now; - now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ); + now = readl(&timer_base->counter) / + (gd->arch.timer_rate_hz / CONFIG_SYS_HZ); if (gd->arch.lastinc >= now) { /* Normal mode */ gd->arch.tbl += gd->arch.lastinc - now; } else { /* We have an overflow ... */ - gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now; + gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now + 1; } gd->arch.lastinc = now; @@ -107,8 +110,8 @@ void __udelay(unsigned long usec) if (usec == 0) return; - countticks = (u32) (((unsigned long long) TIMER_TICK_HZ * usec) / - 1000000); + countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec), + 1000000); /* decrementing timer */ timeend = readl(&timer_base->counter) - countticks; diff --git a/arch/arm/cpu/armv7/zynq/u-boot-spl.lds b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds new file mode 100644 index 0000000000..0f2f756f83 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2014 Xilinx, Inc. Michal Simek + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + __image_copy_start = .; + *(.vectors) + CPUDIR/start.o (.text*) + *(.text*) + } > .sram + + . = ALIGN(4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } > .sram + + . = ALIGN(4); + .data : { + *(.data*) + } > .sram + + . = ALIGN(4); + + . = .; + + __image_copy_end = .; + + _end = .; + + /* Move BSS section to RAM because of FAT */ + .bss (NOLOAD) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .sdram + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds new file mode 100644 index 0000000000..4dc9bb0102 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /* + * Zynq needs to discard these sections because the user + * is expected to pass this image on to tools for boot.bin + * generation that require them to be dropped. + */ + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynbss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } +} diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile new file mode 100644 index 0000000000..0c102230ae --- /dev/null +++ b/arch/arm/cpu/armv8/Makefile @@ -0,0 +1,18 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y := start.o + +obj-y += cpu.o +obj-y += generic_timer.o +obj-y += cache_v8.o +obj-y += exceptions.o +obj-y += cache.o +obj-y += tlb.o +obj-y += transition.o + +obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S new file mode 100644 index 0000000000..9c6e8243bb --- /dev/null +++ b/arch/arm/cpu/armv8/cache.S @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * This file is based on sample code from ARMv8 ARM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * void __asm_flush_dcache_level(level) + * + * clean and invalidate one level cache. + * + * x0: cache level + * x1: 0 flush & invalidate, 1 invalidate only + * x2~x9: clobbered + */ +ENTRY(__asm_flush_dcache_level) + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ + and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ + mov x3, #0x3ff + and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ + clz w5, w3 /* bit position of #ways */ + mov x4, #0x7fff + and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ + /* x12 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ + /* x4 <- number of cache sets - 1 */ + /* x5 <- bit position of #ways */ + +loop_set: + mov x6, x3 /* x6 <- working copy of #ways */ +loop_way: + lsl x7, x6, x5 + orr x9, x12, x7 /* map way and level to cisw value */ + lsl x7, x4, x2 + orr x9, x9, x7 /* map set number to cisw value */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ + b.ge loop_way + subs x4, x4, #1 /* decrement the set */ + b.ge loop_set + + ret +ENDPROC(__asm_flush_dcache_level) + +/* + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 flush & invalidate, 1 invalidate only + * + * clean and invalidate all data cache by SET/WAY. + */ +ENTRY(__asm_dcache_all) + mov x1, x0 + dsb sy + mrs x10, clidr_el1 /* read clidr_el1 */ + lsr x11, x10, #24 + and x11, x11, #0x7 /* x11 <- loc */ + cbz x11, finished /* if loc is 0, exit */ + mov x15, lr + mov x0, #0 /* start flush at cache level 0 */ + /* x0 <- cache level */ + /* x10 <- clidr_el1 */ + /* x11 <- loc */ + /* x15 <- return address */ + +loop_level: + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 + b.lt skip /* skip if no cache or icache */ + bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */ +skip: + add x0, x0, #1 /* increment cache level */ + cmp x11, x0 + b.gt loop_level + + mov x0, #0 + msr csselr_el1, x0 /* restore csselr_el1 */ + dsb sy + isb + mov lr, x15 + +finished: + ret +ENDPROC(__asm_dcache_all) + +ENTRY(__asm_flush_dcache_all) + mov x16, lr + mov x0, #0 + bl __asm_dcache_all + mov lr, x16 + ret +ENDPROC(__asm_flush_dcache_all) + +ENTRY(__asm_invalidate_dcache_all) + mov x16, lr + mov x0, #0xffff + bl __asm_dcache_all + mov lr, x16 + ret +ENDPROC(__asm_invalidate_dcache_all) + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +ENTRY(__asm_flush_dcache_range) + mrs x3, ctr_el0 + lsr x3, x3, #16 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc civac, x0 /* clean & invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__asm_flush_dcache_range) + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ +ENTRY(__asm_invalidate_icache_all) + ic ialluis + isb sy + ret +ENDPROC(__asm_invalidate_icache_all) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c new file mode 100644 index 0000000000..9dbcdf22af --- /dev/null +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -0,0 +1,231 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DCACHE_OFF +void set_pgtable_section(u64 *page_table, u64 index, u64 section, + u64 memory_type) +{ + u64 value; + + value = section | PMD_TYPE_SECT | PMD_SECT_AF; + value |= PMD_ATTRINDX(memory_type); + page_table[index] = value; +} + +/* to activate the MMU we need to set up virtual memory */ +static void mmu_setup(void) +{ + int i, j, el; + bd_t *bd = gd->bd; + u64 *page_table = (u64 *)gd->arch.tlb_addr; + + /* Setup an identity-mapping for all spaces */ + for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { + set_pgtable_section(page_table, i, i << SECTION_SHIFT, + MT_DEVICE_NGNRNE); + } + + /* Setup an identity-mapping for all RAM space */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + ulong start = bd->bi_dram[i].start; + ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size; + for (j = start >> SECTION_SHIFT; + j < end >> SECTION_SHIFT; j++) { + set_pgtable_section(page_table, j, j << SECTION_SHIFT, + MT_NORMAL); + } + } + + /* load TTBR0 */ + el = current_el(); + if (el == 1) { + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL1_IPS_BITS, + MEMORY_ATTRIBUTES); + } else if (el == 2) { + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL2_IPS_BITS, + MEMORY_ATTRIBUTES); + } else { + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL3_IPS_BITS, + MEMORY_ATTRIBUTES); + } + /* enable the mmu */ + set_sctlr(get_sctlr() | CR_M); +} + +/* + * Performs a invalidation of the entire data cache at all levels + */ +void invalidate_dcache_all(void) +{ + __asm_invalidate_dcache_all(); +} + +void __weak flush_l3_cache(void) +{ +} + +/* + * Performs a clean & invalidation of the entire data cache at all levels + */ +void flush_dcache_all(void) +{ + __asm_flush_dcache_all(); + flush_l3_cache(); +} + +/* + * Invalidates range in all levels of D-cache/unified cache + */ +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + __asm_flush_dcache_range(start, stop); +} + +/* + * Flush range(clean & invalidate) from all levels of D-cache/unified cache + */ +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + __asm_flush_dcache_range(start, stop); +} + +void dcache_enable(void) +{ + /* The data cache is not active unless the mmu is enabled */ + if (!(get_sctlr() & CR_M)) { + invalidate_dcache_all(); + __asm_invalidate_tlb_all(); + mmu_setup(); + } + + set_sctlr(get_sctlr() | CR_C); +} + +void dcache_disable(void) +{ + uint32_t sctlr; + + sctlr = get_sctlr(); + + /* if cache isn't enabled no need to disable */ + if (!(sctlr & CR_C)) + return; + + set_sctlr(sctlr & ~(CR_C|CR_M)); + + flush_dcache_all(); + __asm_invalidate_tlb_all(); +} + +int dcache_status(void) +{ + return (get_sctlr() & CR_C) != 0; +} + +#else /* CONFIG_SYS_DCACHE_OFF */ + +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +int dcache_status(void) +{ + return 0; +} + +#endif /* CONFIG_SYS_DCACHE_OFF */ + +#ifndef CONFIG_SYS_ICACHE_OFF + +void icache_enable(void) +{ + __asm_invalidate_icache_all(); + set_sctlr(get_sctlr() | CR_I); +} + +void icache_disable(void) +{ + set_sctlr(get_sctlr() & ~CR_I); +} + +int icache_status(void) +{ + return (get_sctlr() & CR_I) != 0; +} + +void invalidate_icache_all(void) +{ + __asm_invalidate_icache_all(); +} + +#else /* CONFIG_SYS_ICACHE_OFF */ + +void icache_enable(void) +{ +} + +void icache_disable(void) +{ +} + +int icache_status(void) +{ + return 0; +} + +void invalidate_icache_all(void) +{ +} + +#endif /* CONFIG_SYS_ICACHE_OFF */ + +/* + * Enable dCache & iCache, whether cache is actually enabled + * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF + */ +void __weak enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + +/* + * Flush range from all levels of d-cache/unified-cache + */ +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk new file mode 100644 index 0000000000..f5b95591af --- /dev/null +++ b/arch/arm/cpu/armv8/config.mk @@ -0,0 +1,12 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# SPDX-License-Identifier: GPL-2.0+ +# +PLATFORM_RELFLAGS += -fno-common -ffixed-x18 + +PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a) +PF_NO_UNALIGNED := $(call cc-option, -mstrict-align) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8) +PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED) diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c new file mode 100644 index 0000000000..e06c3cc04d --- /dev/null +++ b/arch/arm/cpu/armv8/cpu.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int cleanup_before_linux(void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * disable interrupt and turn off caches etc ... + */ + disable_interrupts(); + + /* + * Turn off I-cache and invalidate it + */ + icache_disable(); + invalidate_icache_all(); + + /* + * turn off D-cache + * dcache_disable() in turn flushes the d-cache and disables MMU + */ + dcache_disable(); + invalidate_dcache_all(); + + return 0; +} diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S new file mode 100644 index 0000000000..b91a1b662f --- /dev/null +++ b/arch/arm/cpu/armv8/exceptions.S @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* + * Enter Exception. + * This will save the processor state that is ELR/X0~X30 + * to the stack frame. + */ +.macro exception_entry + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + stp x17, x18, [sp, #-16]! + stp x15, x16, [sp, #-16]! + stp x13, x14, [sp, #-16]! + stp x11, x12, [sp, #-16]! + stp x9, x10, [sp, #-16]! + stp x7, x8, [sp, #-16]! + stp x5, x6, [sp, #-16]! + stp x3, x4, [sp, #-16]! + stp x1, x2, [sp, #-16]! + + /* Could be running at EL3/EL2/EL1 */ + switch_el x11, 3f, 2f, 1f +3: mrs x1, esr_el3 + mrs x2, elr_el3 + b 0f +2: mrs x1, esr_el2 + mrs x2, elr_el2 + b 0f +1: mrs x1, esr_el1 + mrs x2, elr_el1 +0: + stp x2, x0, [sp, #-16]! + mov x0, sp +.endm + +/* + * Exception vectors. + */ + .align 11 + .globl vectors +vectors: + .align 7 + b _do_bad_sync /* Current EL Synchronous Thread */ + + .align 7 + b _do_bad_irq /* Current EL IRQ Thread */ + + .align 7 + b _do_bad_fiq /* Current EL FIQ Thread */ + + .align 7 + b _do_bad_error /* Current EL Error Thread */ + + .align 7 + b _do_sync /* Current EL Synchronous Handler */ + + .align 7 + b _do_irq /* Current EL IRQ Handler */ + + .align 7 + b _do_fiq /* Current EL FIQ Handler */ + + .align 7 + b _do_error /* Current EL Error Handler */ + + +_do_bad_sync: + exception_entry + bl do_bad_sync + +_do_bad_irq: + exception_entry + bl do_bad_irq + +_do_bad_fiq: + exception_entry + bl do_bad_fiq + +_do_bad_error: + exception_entry + bl do_bad_error + +_do_sync: + exception_entry + bl do_sync + +_do_irq: + exception_entry + bl do_irq + +_do_fiq: + exception_entry + bl do_fiq + +_do_error: + exception_entry + bl do_error diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile new file mode 100644 index 0000000000..f920eebc56 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2014, Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += lowlevel.o +obj-y += speed.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README new file mode 100644 index 0000000000..cc47466112 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -0,0 +1,10 @@ +# +# Copyright 2014 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Freescale LayerScape with Chassis Generation 3 + +This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, +for example LS2085A. diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c new file mode 100644 index 0000000000..47b947f44f --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -0,0 +1,449 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "cpu.h" +#include "mp.h" +#include "speed.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DCACHE_OFF +/* + * To start MMU before DDR is available, we create MMU table in SRAM. + * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three + * levels of translation tables here to cover 40-bit address space. + * We use 4KB granule size, with 40 bits physical address, T0SZ=24 + * Level 0 IA[39], table address @0 + * Level 1 IA[31:30], table address @01000, 0x2000 + * Level 2 IA[29:21], table address @0x3000 + */ + +#define SECTION_SHIFT_L0 39UL +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000UL +#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) +#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) +#define CONFIG_SYS_IFC_BASE 0x30000000 +#define CONFIG_SYS_IFC_SIZE 0x10000000 +#define CONFIG_SYS_IFC_BASE2 0x500000000 +#define CONFIG_SYS_IFC_SIZE2 0x100000000 +#define TCR_EL2_PS_40BIT (2 << 16) +#define LSCH3_VA_BITS (40) +#define LSCH3_TCR (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT | \ + TCR_SHARED_NON | \ + TCR_ORGN_NC | \ + TCR_IRGN_NC | \ + TCR_T0SZ(LSCH3_VA_BITS)) + +/* + * Final MMU + * Let's start from the same layout as early MMU and modify as needed. + * IFC regions will be cache-inhibit. + */ +#define FINAL_QBMAN_CACHED_MEM 0x818000000UL +#define FINAL_QBMAN_CACHED_SIZE 0x4000000 + + +static inline void early_mmu_setup(void) +{ + int el; + u64 i; + u64 section_l1t0, section_l1t1, section_l2; + u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; + u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); + u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); + u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); + + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0 to cache_inhibit, covering 0 to 512GB + * set level 1 table 1 to cache enabled, covering 512GB to 1TB + * set level 2 table to cache-inhibit, covering 0 to 1GB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + section_l2 = 0; + for (i = 0; i < 512; i++) { + set_pgtable_section(level1_table_0, i, section_l1t0, + MT_DEVICE_NGNRNE); + set_pgtable_section(level1_table_1, i, section_l1t1, + MT_NORMAL); + set_pgtable_section(level2_table, i, section_l2, + MT_DEVICE_NGNRNE); + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + section_l2 += BLOCK_SIZE_L2; + } + + level1_table_0[0] = + (u64)level2_table | PMD_TYPE_TABLE; + level1_table_0[1] = + 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_DEVICE_NGNRNE); + level1_table_0[2] = + 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_NORMAL); + level1_table_0[3] = + 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_NORMAL); + + /* Rewrite table to enable cache */ + set_pgtable_section(level2_table, + CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, + CONFIG_SYS_FSL_OCRAM_BASE, + MT_NORMAL); + for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2; + i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE) + >> SECTION_SHIFT_L2; i++) { + section_l2 = i << SECTION_SHIFT_L2; + set_pgtable_section(level2_table, i, + section_l2, MT_NORMAL); + } + + el = current_el(); + set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES); + set_sctlr(get_sctlr() | CR_M); +} + +/* + * This final tale looks similar to early table, but different in detail. + * These tables are in regular memory. Cache on IFC is disabled. One sub table + * is added to enable cache for QBMan. + */ +static inline void final_mmu_setup(void) +{ + int el; + u64 i, tbl_base, tbl_limit, section_base; + u64 section_l1t0, section_l1t1, section_l2; + u64 *level0_table = (u64 *)gd->arch.tlb_addr; + u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000); + u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000); + u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000); + u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000); + + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0 to cache_inhibit, covering 0 to 512GB + * set level 1 table 1 to cache enabled, covering 512GB to 1TB + * set level 2 table 0 to cache-inhibit, covering 0 to 1GB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + section_l2 = 0; + for (i = 0; i < 512; i++) { + set_pgtable_section(level1_table_0, i, section_l1t0, + MT_DEVICE_NGNRNE); + set_pgtable_section(level1_table_1, i, section_l1t1, + MT_NORMAL); + set_pgtable_section(level2_table_0, i, section_l2, + MT_DEVICE_NGNRNE); + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + section_l2 += BLOCK_SIZE_L2; + } + + level1_table_0[0] = + (u64)level2_table_0 | PMD_TYPE_TABLE; + level1_table_0[2] = + 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_NORMAL); + level1_table_0[3] = + 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_NORMAL); + + /* Rewrite table to enable cache */ + set_pgtable_section(level2_table_0, + CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, + CONFIG_SYS_FSL_OCRAM_BASE, + MT_NORMAL); + + /* + * Fill in other part of tables if cache is needed + * If finer granularity than 1GB is needed, sub table + * should be created. + */ + section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1); + i = section_base >> SECTION_SHIFT_L1; + level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE; + section_l2 = section_base; + for (i = 0; i < 512; i++) { + set_pgtable_section(level2_table_1, i, section_l2, + MT_DEVICE_NGNRNE); + section_l2 += BLOCK_SIZE_L2; + } + tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); + tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) & + (BLOCK_SIZE_L1 - 1); + for (i = tbl_base >> SECTION_SHIFT_L2; + i < tbl_limit >> SECTION_SHIFT_L2; i++) { + section_l2 = section_base + (i << SECTION_SHIFT_L2); + set_pgtable_section(level2_table_1, i, + section_l2, MT_NORMAL); + } + + /* flush new MMU table */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + /* point TTBR to the new table */ + el = current_el(); + asm volatile("dsb sy"); + if (el == 1) { + asm volatile("msr ttbr0_el1, %0" + : : "r" ((u64)level0_table) : "memory"); + } else if (el == 2) { + asm volatile("msr ttbr0_el2, %0" + : : "r" ((u64)level0_table) : "memory"); + } else if (el == 3) { + asm volatile("msr ttbr0_el3, %0" + : : "r" ((u64)level0_table) : "memory"); + } else { + hang(); + } + asm volatile("isb"); + + /* + * MMU is already enabled, just need to invalidate TLB to load the + * new table. The new table is compatible with the current table, if + * MMU somehow walks through the new table before invalidation TLB, + * it still works. So we don't need to turn off MMU here. + */ +} + +int arch_cpu_init(void) +{ + icache_enable(); + __asm_invalidate_dcache_all(); + __asm_invalidate_tlb_all(); + early_mmu_setup(); + set_sctlr(get_sctlr() | CR_C); + return 0; +} + +/* + * flush_l3_cache + * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power + * state, by writing to HP-F P-state request register. + * Fixme: This function should moved to a common file if other SoCs also use + * the same Dickens. + */ +#define HNF0_PSTATE_REQ 0x04200010 +#define HNF1_PSTATE_REQ 0x04210010 +#define HNF2_PSTATE_REQ 0x04220010 +#define HNF3_PSTATE_REQ 0x04230010 +#define HNF4_PSTATE_REQ 0x04240010 +#define HNF5_PSTATE_REQ 0x04250010 +#define HNF6_PSTATE_REQ 0x04260010 +#define HNF7_PSTATE_REQ 0x04270010 +#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC) +#define HNFPSTAT_FAM 0x3 +#define HNFPSTAT_SFONLY 0x01 + +static void hnf_pstate_req(u64 *ptr, u64 state) +{ + int timeout = 1000; + out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3)); + ptr++; + /* checking if the transition is completed */ + while (timeout > 0) { + if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3)) + break; + udelay(100); + timeout--; + } +} + +void flush_l3_cache(void) +{ + hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM); +} + +/* + * This function is called from lib/board.c. + * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. + * There is no need to disable d-cache for this operation. + */ +void enable_caches(void) +{ + final_mmu_setup(); + __asm_invalidate_tlb_all(); +} +#endif + +static inline u32 initiator_type(u32 cluster, int init_id) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; + u32 type = in_le32(&gur->tp_ityp[idx]); + + if (type & TP_ITYP_AV) + return type; + + return 0; +} + +u32 cpu_mask(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster, type, mask = 0; + + do { + int j; + cluster = in_le32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type) { + if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) + mask |= 1 << count; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return mask; +} + +/* + * Return the number of cores on this SOC. + */ +int cpu_numcores(void) +{ + return hweight32(cpu_mask()); +} + +int fsl_qoriq_core_to_cluster(unsigned int core) +{ + struct ccsr_gur __iomem *gur = + (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster; + + do { + int j; + cluster = in_le32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + if (initiator_type(cluster, j)) { + if (count == core) + return i; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return -1; /* cannot identify the cluster */ +} + +u32 fsl_qoriq_core_to_type(unsigned int core) +{ + struct ccsr_gur __iomem *gur = + (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster, type; + + do { + int j; + cluster = in_le32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type) { + if (count == core) + return type; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return -1; /* cannot identify the cluster */ +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + struct sys_info sysinfo; + char buf[32]; + unsigned int i, core; + u32 type; + + get_sys_info(&sysinfo); + puts("Clock Configuration:"); + for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { + if (!(i % 3)) + puts("\n "); + type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); + printf("CPU%d(%s):%-4s MHz ", core, + type == TY_ITYP_VER_A7 ? "A7 " : + (type == TY_ITYP_VER_A53 ? "A53" : + (type == TY_ITYP_VER_A57 ? "A57" : " ")), + strmhz(buf, sysinfo.freq_processor[core])); + } + printf("\n Bus: %-4s MHz ", + strmhz(buf, sysinfo.freq_systembus)); + printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); + puts("\n"); + + return 0; +} +#endif + +int cpu_eth_init(bd_t *bis) +{ + int error = 0; + +#ifdef CONFIG_FSL_MC_ENET + error = mc_init(bis); +#endif + return error; +} + + +int arch_early_init_r(void) +{ + int rv; + rv = fsl_lsch3_wake_seconday_cores(); + + if (rv) + printf("Did not wake secondary cores\n"); + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h new file mode 100644 index 0000000000..2e3312b99b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h @@ -0,0 +1,8 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int fsl_qoriq_core_to_cluster(unsigned int core); +u32 cpu_mask(void); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c new file mode 100644 index 0000000000..e392eb9149 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -0,0 +1,58 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "mp.h" + +#ifdef CONFIG_MP +void ft_fixup_cpu(void *blob) +{ + int off; + __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr(); + fdt32_t *reg; + int addr_cells; + u64 val; + size_t *boot_code_size = &(__secondary_boot_code_size); + + off = fdt_path_offset(blob, "/cpus"); + if (off < 0) { + puts("couldn't find /cpus node\n"); + return; + } + of_bus_default_count_cells(blob, off, &addr_cells, NULL); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); + if (reg) { + val = spin_tbl_addr; + val += id_to_core(of_read_number(reg, addr_cells)) + * SPIN_TABLE_ELEM_SIZE; + val = cpu_to_fdt64(val); + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } else { + puts("Warning: found cpu node without reg property\n"); + } + off = fdt_node_offset_by_prop_value(blob, off, "device_type", + "cpu", 4); + } + + fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, + *boot_code_size); +} +#endif + +void ft_cpu_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_MP + ft_fixup_cpu(blob); +#endif +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S new file mode 100644 index 0000000000..2a88aab283 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Extracted from armv8/start.S + */ + +#include +#include +#include +#include +#include "mp.h" + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + + /* Set the SMMU page size in the sACR register */ + ldr x1, =SMMU_BASE + ldr w0, [x1, #0x10] + orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */ + str w0, [x1, #0x10] + + /* Initialize GIC Secure Bank Status */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#ifdef CONFIG_GICV3 + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + + branch_if_master x0, x1, 2f + + ldr x0, =secondary_boot_func + blr x0 +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) + + /* Keep literals not used by the secondary boot code outside it */ + .ltorg + + /* Using 64 bit alignment since the spin table is accessed as data */ + .align 4 + .global secondary_boot_code + /* Secondary Boot Code starts here */ +secondary_boot_code: + .global __spin_table +__spin_table: + .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE + + .align 2 +ENTRY(secondary_boot_func) + /* + * MPIDR_EL1 Fields: + * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) + * MPIDR[7:2] = AFF0_RES + * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3) + * MPIDR[23:16] = AFF2_CLUSTERID + * MPIDR[24] = MT + * MPIDR[29:25] = RES0 + * MPIDR[30] = U + * MPIDR[31] = ME + * MPIDR[39:32] = AFF3 + * + * Linear Processor ID (LPID) calculation from MPIDR_EL1: + * (We only use AFF0_CPUID and AFF1_CLUSTERID for now + * until AFF2_CLUSTERID and AFF3 have non-zero values) + * + * LPID = MPIDR[15:8] | MPIDR[1:0] + */ + mrs x0, mpidr_el1 + ubfm x1, x0, #8, #15 + ubfm x2, x0, #0, #1 + orr x10, x2, x1, lsl #2 /* x10 has LPID */ + ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */ + /* + * offset of the spin table element for this core from start of spin + * table (each elem is padded to 64 bytes) + */ + lsl x1, x10, #6 + ldr x0, =__spin_table + /* physical address of this cpus spin table element */ + add x11, x1, x0 + + str x9, [x11, #16] /* LPID */ + mov x4, #1 + str x4, [x11, #8] /* STATUS */ + dsb sy +#if defined(CONFIG_GICV3) + gic_wait_for_interrupt_m x0 +#elif defined(CONFIG_GICV2) + ldr x0, =GICC_BASE + gic_wait_for_interrupt_m x0, w1 +#endif + + bl secondary_switch_to_el2 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + bl secondary_switch_to_el1 +#endif + +slave_cpu: + wfe + ldr x0, [x11] + cbz x0, slave_cpu +#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 + mrs x1, sctlr_el2 +#else + mrs x1, sctlr_el1 +#endif + tbz x1, #25, cpu_is_le + rev x0, x0 /* BE to LE conversion */ +cpu_is_le: + br x0 /* branch to the given address */ +ENDPROC(secondary_boot_func) + +ENTRY(secondary_switch_to_el2) + switch_el x0, 1f, 0f, 0f +0: ret +1: armv8_switch_to_el2_m x0 +ENDPROC(secondary_switch_to_el2) + +ENTRY(secondary_switch_to_el1) + switch_el x0, 0f, 1f, 0f +0: ret +1: armv8_switch_to_el1_m x0, x1 +ENDPROC(secondary_switch_to_el1) + + /* Ensure that the literals used by the secondary boot code are + * assembled within it (this is required so that we can protect + * this area with a single memreserve region + */ + .ltorg + + /* 64 bit alignment for elements accessed as data */ + .align 4 + .globl __secondary_boot_code_size + .type __secondary_boot_code_size, %object + /* Secondary Boot Code ends here */ +__secondary_boot_code_size: + .quad .-secondary_boot_code diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c new file mode 100644 index 0000000000..94998bf37b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c @@ -0,0 +1,168 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "mp.h" + +DECLARE_GLOBAL_DATA_PTR; + +void *get_spin_tbl_addr(void) +{ + return &__spin_table; +} + +phys_addr_t determine_mp_bootpg(void) +{ + return (phys_addr_t)&secondary_boot_code; +} + +int fsl_lsch3_wake_seconday_cores(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); + u32 cores, cpu_up_mask = 1; + int i, timeout = 10; + u64 *table = get_spin_tbl_addr(); + + cores = cpu_mask(); + /* Clear spin table so that secondary processors + * observe the correct value after waking up from wfe. + */ + memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); + flush_dcache_range((unsigned long)table, + (unsigned long)table + + (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); + + printf("Waking secondary cores to start from %lx\n", gd->relocaddr); + out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); + out_le32(&gur->bootlocptrl, (u32)gd->relocaddr); + out_le32(&gur->scratchrw[6], 1); + asm volatile("dsb st" : : : "memory"); + rst->brrl = cores; + asm volatile("dsb st" : : : "memory"); + + /* This is needed as a precautionary measure. + * If some code before this has accidentally released the secondary + * cores then the pre-bootloader code will trap them in a "wfe" unless + * the scratchrw[6] is set. In this case we need a sev here to get these + * cores moving again. + */ + asm volatile("sev"); + + while (timeout--) { + flush_dcache_range((unsigned long)table, (unsigned long)table + + CONFIG_MAX_CPUS * 64); + for (i = 1; i < CONFIG_MAX_CPUS; i++) { + if (table[i * WORDS_PER_SPIN_TABLE_ENTRY + + SPIN_TABLE_ELEM_STATUS_IDX]) + cpu_up_mask |= 1 << i; + } + if (hweight32(cpu_up_mask) == hweight32(cores)) + break; + udelay(10); + } + if (timeout <= 0) { + printf("Not all cores (0x%x) are up (0x%x)\n", + cores, cpu_up_mask); + return 1; + } + printf("All (%d) cores are up.\n", hweight32(cores)); + + return 0; +} + +int is_core_valid(unsigned int core) +{ + return !!((1 << core) & cpu_mask()); +} + +int cpu_reset(int nr) +{ + puts("Feature is not implemented.\n"); + + return 0; +} + +int cpu_disable(int nr) +{ + puts("Feature is not implemented.\n"); + + return 0; +} + +int core_to_pos(int nr) +{ + u32 cores = cpu_mask(); + int i, count = 0; + + if (nr == 0) { + return 0; + } else if (nr >= hweight32(cores)) { + puts("Not a valid core number.\n"); + return -1; + } + + for (i = 1; i < 32; i++) { + if (is_core_valid(i)) { + count++; + if (count == nr) + break; + } + } + + return count; +} + +int cpu_status(int nr) +{ + u64 *table; + int pos; + + if (nr == 0) { + table = (u64 *)get_spin_tbl_addr(); + printf("table base @ 0x%p\n", table); + } else { + pos = core_to_pos(nr); + if (pos < 0) + return -1; + table = (u64 *)get_spin_tbl_addr() + pos * + WORDS_PER_SPIN_TABLE_ENTRY; + printf("table @ 0x%p\n", table); + printf(" addr - 0x%016llx\n", + table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); + printf(" status - 0x%016llx\n", + table[SPIN_TABLE_ELEM_STATUS_IDX]); + printf(" lpid - 0x%016llx\n", + table[SPIN_TABLE_ELEM_LPID_IDX]); + } + + return 0; +} + +int cpu_release(int nr, int argc, char * const argv[]) +{ + u64 boot_addr; + u64 *table = (u64 *)get_spin_tbl_addr(); + int pos; + + pos = core_to_pos(nr); + if (pos <= 0) + return -1; + + table += pos * WORDS_PER_SPIN_TABLE_ENTRY; + boot_addr = simple_strtoull(argv[0], NULL, 16); + table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; + flush_dcache_range((unsigned long)table, + (unsigned long)table + SPIN_TABLE_ELEM_SIZE); + asm volatile("dsb st"); + smp_kick_all_cpus(); /* only those with entry addr set will run */ + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h new file mode 100644 index 0000000000..06ac0bcf36 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_CH3_MP_H +#define _FSL_CH3_MP_H + +/* +* Each spin table element is defined as +* struct { +* uint64_t entry_addr; +* uint64_t status; +* uint64_t lpid; +* }; +* we pad this struct to 64 bytes so each entry is in its own cacheline +* the actual spin table is an array of these structures +*/ +#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 +#define SPIN_TABLE_ELEM_STATUS_IDX 1 +#define SPIN_TABLE_ELEM_LPID_IDX 2 +#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ +#define SPIN_TABLE_ELEM_SIZE 64 + +#define id_to_core(x) ((x & 3) | (x >> 6)) +#ifndef __ASSEMBLY__ +extern u64 __spin_table[]; +extern u64 *secondary_boot_code; +extern size_t __secondary_boot_code_size; +int fsl_lsch3_wake_seconday_cores(void); +void *get_spin_tbl_addr(void); +phys_addr_t determine_mp_bootpg(void); +void secondary_boot_func(void); +#endif +#endif /* _FSL_CH3_MP_H */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c new file mode 100644 index 0000000000..dc4a34bce5 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -0,0 +1,176 @@ +/* + * Copyright 2014, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived from arch/power/cpu/mpc85xx/speed.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 +#endif + + +void get_sys_info(struct sys_info *sys_info) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#ifdef CONFIG_FSL_IFC + struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + u32 ccr; +#endif + struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { + (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR), + (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR) + }; + struct ccsr_clk_ctrl __iomem *clk_ctrl = + (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR); + unsigned int cpu; + const u8 core_cplx_pll[16] = { + [0] = 0, /* CC1 PPL / 1 */ + [1] = 0, /* CC1 PPL / 2 */ + [2] = 0, /* CC1 PPL / 4 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 1, /* CC2 PPL / 2 */ + [6] = 1, /* CC2 PPL / 4 */ + [8] = 2, /* CC3 PPL / 1 */ + [9] = 2, /* CC3 PPL / 2 */ + [10] = 2, /* CC3 PPL / 4 */ + [12] = 3, /* CC4 PPL / 1 */ + [13] = 3, /* CC4 PPL / 2 */ + [14] = 3, /* CC4 PPL / 4 */ + }; + + const u8 core_cplx_pll_div[16] = { + [0] = 1, /* CC1 PPL / 1 */ + [1] = 2, /* CC1 PPL / 2 */ + [2] = 4, /* CC1 PPL / 4 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 2, /* CC2 PPL / 2 */ + [6] = 4, /* CC2 PPL / 4 */ + [8] = 1, /* CC3 PPL / 1 */ + [9] = 2, /* CC3 PPL / 2 */ + [10] = 4, /* CC3 PPL / 4 */ + [12] = 1, /* CC4 PPL / 1 */ + [13] = 2, /* CC4 PPL / 2 */ + [14] = 4, /* CC4 PPL / 4 */ + }; + + uint i, cluster; + uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; + u32 c_pll_sel, cplx_pll; + void *offset; + + sys_info->freq_systembus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#else + sys_info->freq_ddrbus = sysclk; +#endif + + sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; + sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; + + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + /* + * fixme: prefer to combine the following into one line, but + * cannot pass compiling without warning about in_le32. + */ + offset = (void *)((size_t)clk_grp[i/3] + + offsetof(struct ccsr_clk_cluster_group, + pllngsr[i%3].gsr)); + ratio[i] = (in_le32(offset) >> 1) & 0x3f; + if (ratio[i] > 4) + freq_c_pll[i] = sysclk * ratio[i]; + else + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; + } + + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + cluster = fsl_qoriq_core_to_cluster(cpu); + c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27) + & 0xf; + cplx_pll = core_cplx_pll[c_pll_sel]; + cplx_pll += cc_group[cluster] - 1; + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } + +#if defined(CONFIG_FSL_IFC) + ccr = in_le32(&ifc_regs->ifc_ccr); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; + + sys_info->freq_localbus = sys_info->freq_systembus / ccr; +#endif +} + + +int get_clocks(void) +{ + struct sys_info sys_info; + get_sys_info(&sys_info); + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + +#if defined(CONFIG_FSL_ESDHC) + gd->arch.sdhc_clk = gd->bus_clk / 2; +#endif /* defined(CONFIG_FSL_ESDHC) */ + + if (gd->cpu_clk != 0) + return 0; + else + return 1; +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq(ulong dummy) +{ + if (!gd->bus_clk) + get_clocks(); + + return gd->bus_clk; +} + +/******************************************** + * get_ddr_freq + * return ddr bus freq in Hz + *********************************************/ +ulong get_ddr_freq(ulong dummy) +{ + if (!gd->mem_clk) + get_clocks(); + + return gd->mem_clk; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_I2C_CLK: + return get_bus_freq(0) / 2; + default: + printf("Unsupported clock\n"); + } + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h new file mode 100644 index 0000000000..15af5b9f91 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.h @@ -0,0 +1,7 @@ +/* + * Copyright 2014, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void get_sys_info(struct sys_info *sys_info); diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c new file mode 100644 index 0000000000..223b95e210 --- /dev/null +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * Generic timer implementation of get_tbclk() + */ +unsigned long get_tbclk(void) +{ + unsigned long cntfrq; + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); + return cntfrq; +} + +/* + * Generic timer implementation of timer_read_counter() + */ +unsigned long timer_read_counter(void) +{ + unsigned long cntpct; + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + return cntpct; +} diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S new file mode 100644 index 0000000000..4b11aa4f22 --- /dev/null +++ b/arch/arm/cpu/armv8/start.S @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/************************************************************************* + * + * Startup Code (reset vector) + * + *************************************************************************/ + +.globl _start +_start: + b reset + + .align 3 + +.globl _TEXT_BASE +_TEXT_BASE: + .quad CONFIG_SYS_TEXT_BASE + +/* + * These are defined in the linker script. + */ +.globl _end_ofs +_end_ofs: + .quad _end - _start + +.globl _bss_start_ofs +_bss_start_ofs: + .quad __bss_start - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .quad __bss_end - _start + +reset: + /* + * Could be EL3/EL2/EL1, Initial State: + * Little Endian, MMU Disabled, i/dCache Disabled + */ + adr x0, vectors + switch_el x1, 3f, 2f, 1f +3: msr vbar_el3, x0 + mrs x0, scr_el3 + orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ + msr scr_el3, x0 + msr cptr_el3, xzr /* Enable FP/SIMD */ + ldr x0, =COUNTER_FREQUENCY + msr cntfrq_el0, x0 /* Initialize CNTFRQ */ + b 0f +2: msr vbar_el2, x0 + mov x0, #0x33ff + msr cptr_el2, x0 /* Enable FP/SIMD */ + b 0f +1: msr vbar_el1, x0 + mov x0, #3 << 20 + msr cpacr_el1, x0 /* Enable FP/SIMD */ +0: + + /* + * Cache/BPB/TLB Invalidate + * i-cache is invalidated before enabled in icache_enable() + * tlb is invalidated before mmu is enabled in dcache_enable() + * d-cache is invalidated before enabled in dcache_enable() + */ + + /* Processor specific initialization */ + bl lowlevel_init + + branch_if_master x0, x1, master_cpu + + /* + * Slave CPUs + */ +slave_cpu: + wfe + ldr x1, =CPU_RELEASE_ADDR + ldr x0, [x1] + cbz x0, slave_cpu + br x0 /* branch to the given address */ + + /* + * Master CPU + */ +master_cpu: + bl _main + +/*-----------------------------------------------------------------------*/ + +WEAK(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + + branch_if_master x0, x1, 2f + + /* + * Slave should wait for master clearing spin table. + * This sync prevent salves observing incorrect + * value of spin table and jumping to wrong place. + */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* + * All slaves will enter EL2 and optionally EL1. + */ + bl armv8_switch_to_el2 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + bl armv8_switch_to_el1 +#endif + +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) + +WEAK(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ + mov x29, lr /* Save LR */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + ldr x0, =GICD_BASE + bl gic_kick_secondary_cpus +#endif + mov lr, x29 /* Restore LR */ + ret +ENDPROC(smp_kick_all_cpus) + +/*-----------------------------------------------------------------------*/ + +ENTRY(c_runtime_cpu_setup) + /* Relocate vBAR */ + adr x0, vectors + switch_el x1, 3f, 2f, 1f +3: msr vbar_el3, x0 + b 0f +2: msr vbar_el2, x0 + b 0f +1: msr vbar_el1, x0 +0: + + ret +ENDPROC(c_runtime_cpu_setup) diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S new file mode 100644 index 0000000000..f840b04df5 --- /dev/null +++ b/arch/arm/cpu/armv8/tlb.S @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * void __asm_invalidate_tlb_all(void) + * + * invalidate all tlb entries. + */ +ENTRY(__asm_invalidate_tlb_all) + switch_el x9, 3f, 2f, 1f +3: tlbi alle3 + dsb sy + isb + b 0f +2: tlbi alle2 + dsb sy + isb + b 0f +1: tlbi vmalle1 + dsb sy + isb +0: + ret +ENDPROC(__asm_invalidate_tlb_all) diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S new file mode 100644 index 0000000000..ade1cdead8 --- /dev/null +++ b/arch/arm/cpu/armv8/transition.S @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +ENTRY(armv8_switch_to_el2) + switch_el x0, 1f, 0f, 0f +0: ret +1: armv8_switch_to_el2_m x0 +ENDPROC(armv8_switch_to_el2) + +ENTRY(armv8_switch_to_el1) + switch_el x0, 0f, 1f, 0f +0: ret +1: armv8_switch_to_el1_m x0, x1 +ENDPROC(armv8_switch_to_el1) diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds new file mode 100644 index 0000000000..4c12222370 --- /dev/null +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(8); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(8); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(8); + .data : { + *(.data*) + } + + . = ALIGN(8); + + . = .; + + . = ALIGN(8); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(8); + + .image_copy_end : + { + *(.__image_copy_end) + } + + . = ALIGN(8); + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rela.dyn : { + *(.rela*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + . = ALIGN(8); + + .bss_start : { + KEEP(*(.__bss_start)); + } + + .bss : { + *(.bss*) + . = ALIGN(8); + } + + .bss_end : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile new file mode 100644 index 0000000000..89e15775fb --- /dev/null +++ b/arch/arm/cpu/at91-common/Makefile @@ -0,0 +1,17 @@ +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2013 Atmel Corporation +# Bo Shen +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o +ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o +obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o +obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o +obj-y += spl.o +endif diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c new file mode 100644 index 0000000000..44798e612c --- /dev/null +++ b/arch/arm/cpu/at91-common/mpddrc.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static inline void atmel_mpddr_op(int mode, u32 ram_address) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + + writel(mode, &mpddr->mr); + writel(0, ram_address); +} + +static int ddr2_decodtype_is_seq(u32 cr) +{ +#if defined(CONFIG_SAMA5D3) + if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) + return 0; +#endif + return 1; +} + +int ddr2_init(const unsigned int ram_address, + const struct atmel_mpddr *mpddr_value) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + u32 ba_off, cr; + + /* Compute bank offset according to NC in configuration register */ + ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; + if (ddr2_decodtype_is_seq(mpddr_value->cr)) + ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; + + ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; + + /* Program the memory device type into the memory device register */ + writel(mpddr_value->md, &mpddr->md); + + /* Program the configuration register */ + writel(mpddr_value->cr, &mpddr->cr); + + /* Program the timing register */ + writel(mpddr_value->tpr0, &mpddr->tpr0); + writel(mpddr_value->tpr1, &mpddr->tpr1); + writel(mpddr_value->tpr2, &mpddr->tpr2); + + /* Issue a NOP command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* A 200 us is provided to precede any signal toggle */ + udelay(200); + + /* Issue a NOP command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* Issue an all banks precharge command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); + + /* Issue an extended mode register set(EMRS2) to choose operation */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x2 << ba_off)); + + /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x3 << ba_off)); + + /* + * Issue an extended mode register set(EMRS1) to enable DLL and + * program D.I.C (output driver impedance control) + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* Enable DLL reset */ + cr = readl(&mpddr->cr); + writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); + + /* A mode register set(MRS) cycle is issued to reset DLL */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + + /* Issue an all banks precharge command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); + + /* Two auto-refresh (CBR) cycles are provided */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); + + /* Disable DLL reset */ + cr = readl(&mpddr->cr); + writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr); + + /* A mode register set (MRS) cycle is issued to disable DLL reset */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + + /* Set OCD calibration in default state */ + cr = readl(&mpddr->cr); + writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); + + /* + * An extended mode register set (EMRS1) cycle is issued + * to OCD default value + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* OCD calibration mode exit */ + cr = readl(&mpddr->cr); + writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); + + /* + * An extended mode register set (EMRS1) cycle is issued + * to enable OCD exit + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* A nornal mode command is provided */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); + + /* Perform a write access to any DDR2-SDRAM address */ + writel(0, ram_address); + + /* Write the refresh rate */ + writel(mpddr_value->rtr, &mpddr->rtr); + + return 0; +} diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c new file mode 100644 index 0000000000..2cba7169e4 --- /dev/null +++ b/arch/arm/cpu/at91-common/phy.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2012 + * Markus Hubig + * IMKO GmbH + * + * Copyright (C) 2013 DENX Software Engineering, hs@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +void at91_phy_reset(void) +{ + unsigned long erstl; + unsigned long start = get_timer(0); + unsigned long const timeout = 1000; /* 1000ms */ + at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* + * Need to reset PHY -> 500ms reset + * Reset PHY by pulling the NRST line for 500ms to low. To do so + * disable user reset for low level on NRST pin and poll the NRST + * level in reset status register. + */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end of hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { + /* avoid shutdown by watchdog */ + WATCHDOG_RESET(); + mdelay(10); + + /* timeout for not getting stuck in an endless loop */ + if (get_timer(start) >= timeout) { + puts("*** ERROR: Timeout waiting for PHY reset!\n"); + break; + } + }; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); +} diff --git a/arch/arm/cpu/at91-common/sdram.c b/arch/arm/cpu/at91-common/sdram.c new file mode 100644 index 0000000000..5758b066e4 --- /dev/null +++ b/arch/arm/cpu/at91-common/sdram.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) +{ + struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; + unsigned int i; + + /* SDRAM feature must be in the configuration register */ + writel(p->cr, ®->cr); + + /* The SDRAM memory type must be set in the Memory Device Register */ + writel(p->mdr, ®->mdr); + + /* + * The minimum pause of 200 us is provided to precede any single + * toggle + */ + for (i = 0; i < 1000; i++) + ; + + /* A NOP command is issued to the SDRAM devices */ + writel(AT91_SDRAMC_MODE_NOP, ®->mr); + writel(0x00000000, sdram_address); + + /* An All Banks Precharge command is issued to the SDRAM devices */ + writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); + writel(0x00000000, sdram_address); + + for (i = 0; i < 10000; i++) + ; + + /* Eight auto-refresh cycles are provided */ + for (i = 0; i < 8; i++) { + writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); + writel(0x00000001 + i, sdram_address + 4 + 4 * i); + } + + /* + * A Mode Register set (MRS) cyscle is issued to program the + * SDRAM parameters(TCSR, PASR, DS) + */ + writel(AT91_SDRAMC_MODE_LMR, ®->mr); + writel(0xcafedede, sdram_address + 0x24); + + /* + * The application must go into Normal Mode, setting Mode + * to 0 in the Mode Register and perform a write access at + * any location in the SDRAM. + */ + writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); + writel(0x00000000, sdram_address); /* Perform Normal mode */ + + /* + * Write the refresh rate into the count field in the SDRAMC + * Refresh Timer Rgister. + */ + writel(p->tr, ®->tr); + + return 0; +} diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c new file mode 100644 index 0000000000..6473320097 --- /dev/null +++ b/arch/arm/cpu/at91-common/spl.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +void at91_disable_wdt(void) +{ + struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; + + writel(AT91_WDT_MR_WDDIS, &wdt->mr); +} + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SYS_USE_MMC + return BOOT_DEVICE_MMC1; +#elif CONFIG_SYS_USE_NANDFLASH + return BOOT_DEVICE_NAND; +#elif CONFIG_SYS_USE_SERIALFLASH + return BOOT_DEVICE_SPI; +#endif + return BOOT_DEVICE_NONE; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { +#ifdef CONFIG_SYS_USE_MMC + case BOOT_DEVICE_MMC1: + return MMCSD_MODE_FS; + break; +#endif + case BOOT_DEVICE_NONE: + default: + hang(); + } +} diff --git a/arch/arm/cpu/at91-common/spl_at91.c b/arch/arm/cpu/at91-common/spl_at91.c new file mode 100644 index 0000000000..89f588be45 --- /dev/null +++ b/arch/arm/cpu/at91-common/spl_at91.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2014 DENX Software Engineering + * Heiko Schocher + * + * Based on: + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void enable_ext_reset(void) +{ + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + + writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); +} + +void lowlevel_clock_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { + /* Enable Main Oscillator */ + writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); + + /* Wait until Main Oscillator is stable */ + while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) + ; + } + + /* After stabilization, switch to Main Oscillator */ + if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { + unsigned long tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_CSS; + tmp |= AT91_PMC_CSS_MAIN; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp &= ~AT91_PMC_PRES; + tmp |= AT91_PMC_PRES_1; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + } + + return; +} + +void __weak matrix_init(void) +{ +} + +void __weak at91_spl_board_init(void) +{ +} + +void spl_board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + lowlevel_clock_init(); + at91_disable_wdt(); + + /* + * At this stage the main oscillator is supposed to be enabled + * PCK = MCK = MOSC + */ + writel(0x00, &pmc->pllicpr); + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + at91_plla_init(CONFIG_SYS_AT91_PLLA); + + /* PCK = PLLA = 2 * MCK */ + at91_mck_init(CONFIG_SYS_MCKR); + + /* Switch MCK on PLLA output */ + at91_mck_init(CONFIG_SYS_MCKR_CSS); + +#if defined(CONFIG_SYS_AT91_PLLB) + /* Configure PLLB */ + at91_pllb_init(CONFIG_SYS_AT91_PLLB); +#endif + + /* Enable External Reset */ + enable_ext_reset(); + + /* Initialize matrix */ + matrix_init(); + + gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; + /* + * init timer long enough for using in spl. + */ + timer_init(); + + /* enable clocks for all PIOs */ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + /* init console */ + at91_seriald_hw_init(); + preloader_console_init(); + + mem_init(); + + at91_spl_board_init(); +} diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/cpu/at91-common/spl_atmel.c new file mode 100644 index 0000000000..7297530e7d --- /dev/null +++ b/arch/arm/cpu/at91-common/spl_atmel.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void switch_to_main_crystal_osc(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff); + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_MOSCEN; + tmp |= AT91_PMC_MOR_OSCOUNT(8); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) + ; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_OSCBYPASS; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + + tmp = readl(&pmc->mor); + tmp |= AT91_PMC_MOR_MOSCSEL; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + + while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS)) + ; + + /* Wait until MAINRDY field is set to make sure main clock is stable */ + while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY)) + ; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_MOSCRCEN; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); +} + +void s_init(void) +{ + switch_to_main_crystal_osc(); + + /* disable watchdog */ + at91_disable_wdt(); + + /* PMC configuration */ + at91_pmc_init(); + + at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + + timer_init(); + + board_early_init_f(); + + preloader_console_init(); + + mem_init(); +} diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/cpu/at91-common/u-boot-spl.lds new file mode 100644 index 0000000000..eccca43a42 --- /dev/null +++ b/arch/arm/cpu/at91-common/u-boot-spl.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/armv7/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + + .end : + { + *(.__end) + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile deleted file mode 100644 index 788598ec78..0000000000 --- a/arch/arm/cpu/ixp/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o - -COBJS-y += cpu.o -COBJS-$(CONFIG_USE_IRQ) += interrupts.o -COBJS-y += timer.o - -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk deleted file mode 100644 index 0f12f8b1c7..0000000000 --- a/arch/arm/cpu/ixp/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# SPDX-License-Identifier: GPL-2.0+ -# - -BIG_ENDIAN = y - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian - -PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 - -PLATFORM_LDFLAGS += -EB -USE_PRIVATE_LIBGCC = yes - -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c deleted file mode 100644 index 4387c18d3d..0000000000 --- a/arch/arm/cpu/ixp/cpu.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code - */ - -#include -#include -#include -#include -#include - -static void cache_flush(void); - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) -{ - unsigned long id; - int speed = 0; - - asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id)); - - puts("CPU: Intel IXP425 at "); - switch ((id & 0x000003f0) >> 4) { - case 0x1c: - speed = 533; - break; - - case 0x1d: - speed = 400; - break; - - case 0x1f: - speed = 266; - break; - } - - if (speed) - printf("%d MHz\n", speed); - else - puts("unknown revision\n"); - - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - disable_interrupts (); - - /* turn off I-cache */ - icache_disable(); - dcache_disable(); - - /* flush I-cache */ - cache_flush(); - - return 0; -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -/* FIXME */ -/* -void pci_init(void) -{ - return; -} -*/ - -int cpu_eth_init(bd_t *bis) -{ -#ifdef CONFIG_IXP4XX_NPE - npe_initialize(bis); -#endif - return 0; -} diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c deleted file mode 100644 index 7694c6a6cc..0000000000 --- a/arch/arm/cpu/ixp/interrupts.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct _irq_handler { - void *m_data; - void (*m_func)( void *data); -}; - -static struct _irq_handler IRQ_HANDLER[N_IRQS]; - -static void default_isr(void *data) -{ - printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n", - (int)data, *IXP425_ICIP, *IXP425_ICIH); -} - -static int next_irq(void) -{ - return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1); -} - -void do_irq (struct pt_regs *pt_regs) -{ - int irq = next_irq(); - - IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); -} - -void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data) -{ - if (irq >= N_IRQS || !handle_irq) - return; - - IRQ_HANDLER[irq].m_data = data; - IRQ_HANDLER[irq].m_func = handle_irq; -} - -int arch_interrupt_init (void) -{ - int i; - - /* install default interrupt handlers */ - for (i = 0; i < N_IRQS; i++) - irq_install_handler(i, default_isr, (void *)i); - - /* configure interrupts for IRQ mode */ - *IXP425_ICLR = 0x00000000; - - return (0); -} diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S deleted file mode 100644 index 1362234b2a..0000000000 --- a/arch/arm/cpu/ixp/start.S +++ /dev/null @@ -1,430 +0,0 @@ -/* vi: set ts=8 sw=8 noet: */ -/* - * u-boot - Startup Code for XScale IXP - * - * Copyright (C) 2003 Kyle Harris - * - * Based on startup code example contained in the - * Intel IXP4xx Programmer's Guide and past u-boot Start.S - * samples. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define MMU_Control_M 0x001 /* Enable MMU */ -#define MMU_Control_A 0x002 /* Enable address alignment faults */ -#define MMU_Control_C 0x004 /* Enable cache */ -#define MMU_Control_W 0x008 /* Enable write-buffer */ -#define MMU_Control_P 0x010 /* Compatability: 32 bit code */ -#define MMU_Control_D 0x020 /* Compatability: 32 bit data */ -#define MMU_Control_L 0x040 /* Compatability: */ -#define MMU_Control_B 0x080 /* Enable Big-Endian */ -#define MMU_Control_S 0x100 /* Enable system protection */ -#define MMU_Control_R 0x200 /* Enable ROM protection */ -#define MMU_Control_I 0x1000 /* Enable Instruction cache */ -#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ -#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) - - -/* - * Macro definitions - */ - /* Delay a bit */ - .macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc - .endm - - /* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -.globl _start -_start: - ldr pc, _reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_reset: .word reset -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * - relocate armboot to ram - * - setup stack - * - jump to second stage - */ - -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* disable mmu, set big-endian */ - mov r0, #0xf8 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - /* invalidate I & D caches & BTB */ - mcr p15, 0, r0, c7, c7, 0 - CPWAIT r0 - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* drain write and fill buffers */ - mcr p15, 0, r0, c7, c10, 4 - CPWAIT r0 - - /* disable write buffer coalescing */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 1 - CPWAIT r0 - - /* set EXP CS0 to the optimum timing */ - ldr r1, =CONFIG_SYS_EXP_CS0 - ldr r2, =IXP425_EXP_CS0 - str r1, [r2] - - /* make sure flash is visible at 0 */ - mov r1, #CONFIG_SYS_SDR_CONFIG - ldr r2, =IXP425_SDR_CONFIG - str r1, [r2] - - /* disable refresh cycles */ - mov r1, #0 - ldr r3, =IXP425_SDR_REFRESH - str r1, [r3] - - /* send nop command */ - mov r1, #3 - ldr r4, =IXP425_SDR_IR - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* set SDRAM internal refresh val */ - ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT - str r1, [r3] - DELAY_FOR 0x4000, r0 - - /* send precharge-all command to close all open banks */ - mov r1, #2 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* provide 8 auto-refresh cycles */ - mov r1, #4 - mov r5, #8 -111: str r1, [r4] - DELAY_FOR 0x100, r0 - subs r5, r5, #1 - bne 111b - - /* set mode register in sdram */ - mov r1, #CONFIG_SYS_SDR_MODE_CONFIG - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* send normal operation command */ - mov r1, #6 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* invalidate I & D caches & BTB */ - mcr p15, 0, r0, c7, c7, 0 - CPWAIT r0 - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* drain write and fill buffers */ - mcr p15, 0, r0, c7, c10, 4 - CPWAIT r0 - - /* remove flash mirror at 0x00000000 */ - ldr r2, =IXP425_EXP_CFG0 - ldr r1, [r2] - bic r1, r1, #0x80000000 - str r1, [r2] - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* enable I cache */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #MMU_Control_I - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - mrs r0,cpsr /* set the cpu to SVC32 mode */ - bic r0,r0,#0x1f /* (superviser mode, M=10011) */ - orr r0,r0,#0x13 - msr cpsr,r0 - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - bx lr - -/****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ -/****************************************************************************/ - -/* IRQ stack frame */ - -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 - - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ - mov r0, sp - .endm - - - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - - -/****************************************************************************/ -/* */ -/* exception handlers */ -/* */ -/****************************************************************************/ - - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -/****************************************************************************/ -/* */ -/* Reset function: Use Watchdog to reset */ -/* */ -/****************************************************************************/ - - .align 5 -.globl reset_cpu - -reset_cpu: - ldr r1, =0x482e - ldr r2, =IXP425_OSWK - str r1, [r2] - ldr r1, =0x0fff - ldr r2, =IXP425_OSWT - str r1, [r2] - ldr r1, =0x5 - ldr r2, =IXP425_OSWE - str r1, [r2] - b reset_endless - -reset_endless: - b reset_endless diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c deleted file mode 100644 index 38e2e2879c..0000000000 --- a/arch/arm/cpu/ixp/timer.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2010 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a - * 33.333MHz crystal). - */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_IXP425_TIMER_CLK); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= CONFIG_IXP425_TIMER_CLK; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * CONFIG_IXP425_TIMER_CLK + 999999; - do_div(us, 1000000); - return us; -} - -unsigned long long get_ticks(void) -{ - ulong now = readl(IXP425_OSTS_B); - - if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) { - /* rollover of timestamp timer register */ - gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1; - writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); - } else { - /* move stamp forward with absolut diff ticks */ - gd->arch.timestamp += (now - gd->arch.lastinc); - } - gd->arch.lastinc = now; - return gd->arch.timestamp; -} - - -void reset_timer_masked(void) -{ - /* capture current timestamp counter */ - gd->arch.lastinc = readl(IXP425_OSTS_B); - /* start "advancing" time stamp from 0 */ - gd->arch.timestamp = 0; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - - tmp = get_ticks() + us_to_tick(usec); - - while (get_ticks() < tmp) - ; -} - -int timer_init(void) -{ - writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); - return 0; -} diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds deleted file mode 100644 index c8d2e126ae..0000000000 --- a/arch/arm/cpu/ixp/u-boot.lds +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile index c84186a67c..8cd475e3a4 100644 --- a/arch/arm/cpu/pxa/Makefile +++ b/arch/arm/cpu/pxa/Makefile @@ -5,35 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y = start.o -LIB = $(obj)lib$(CPU).o +obj-$(CONFIG_CPU_PXA25X) += pxa2xx.o +obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o -START = start.o - -COBJS-$(CONFIG_CPU_PXA25X) = pxa2xx.o -COBJS-$(CONFIG_CPU_PXA27X) = pxa2xx.o - -COBJS-y += cpuinfo.o - -COBJS = $(COBJS-y) -COBJS += timer.o -COBJS += usb.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += cpuinfo.o +obj-y += timer.o +obj-y += usb.o diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index 535bca3e9f..525f5d33b7 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -6,13 +6,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -mcpu=xscale -# ========================================================================= + # -# Supply options according to compiler version +# !WARNING! +# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from +# really small OneNAND memories where the mmap'd window is only 1KiB big. The +# .text.0 contains only the bare minimum needed to load the real SPL into SRAM. +# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd, +# they are not discarded. # -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +#ifdef CONFIG_SPL_BUILD +OBJCOPYFLAGS += -j .text.0 -j .text.1 +#endif diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c index 9d16079956..17d8be5b5b 100644 --- a/arch/arm/cpu/pxa/cpuinfo.c +++ b/arch/arm/cpu/pxa/cpuinfo.c @@ -11,6 +11,12 @@ #include #include +#ifdef CONFIG_CPU_PXA25X +#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) +#error "Init SP address must be set to 0xfffff800 for PXA250" +#endif +#endif + #define CPU_MASK_PXA_PRODID 0x000003f0 #define CPU_MASK_PXA_REVID 0x0000000f diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index c9a7d45392..7e861e26db 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -279,6 +279,7 @@ void reset_cpu(ulong ignored) tmp = readl(OSCR); tmp += 0x1000; writel(tmp, OSMR3); + writel(MDREFR_SLFRSH, MDREFR); for (;;) ; diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 303ca84d46..c77d51e6d8 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -16,61 +16,13 @@ * Copyright (C) 2004 Texas Instruments * Copyright (C) 2010 Marek Vasut * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include -#ifdef CONFIG_CPU_PXA25X -#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) -#error "Init SP address must be set to 0xfffff800 for PXA250" -#endif -#endif - -.globl _start -_start: b reset -#ifdef CONFIG_SPL_BUILD - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -84,52 +36,7 @@ _end_vect: ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -200,191 +107,6 @@ cpu_init_crit: mov pc, lr /* back to my caller */ #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - ldr sp, _TEXT_BASE /* use 32 words about stack */ - bl hang /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -#endif /* CONFIG_SPL_BUILD */ - - /* * Enable MMU to use DCache as DRAM. * diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index 78d9f32745..c4717de6a9 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -28,12 +28,12 @@ DECLARE_GLOBAL_DATA_PTR; static unsigned long long tick_to_time(unsigned long long tick) { - return tick * CONFIG_SYS_HZ / TIMER_FREQ_HZ; + return lldiv(tick * CONFIG_SYS_HZ, TIMER_FREQ_HZ); } static unsigned long long us_to_tick(unsigned long long us) { - return (us * TIMER_FREQ_HZ) / 1000000; + return lldiv(us * TIMER_FREQ_HZ, 1000000); } int timer_init(void) diff --git a/arch/arm/cpu/s3c44b0/Makefile b/arch/arm/cpu/s3c44b0/Makefile deleted file mode 100644 index 39fdbf86c9..0000000000 --- a/arch/arm/cpu/s3c44b0/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o - -COBJS += cache.o -COBJS += cpu.o -COBJS += timer.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/s3c44b0/cache.c b/arch/arm/cpu/s3c44b0/cache.c deleted file mode 100644 index aeee02d85d..0000000000 --- a/arch/arm/cpu/s3c44b0/cache.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -static void s3c44b0_flush_cache(void) -{ - volatile int i; - /* flush cycle */ - for(i=0x10002000;i<0x10004800;i+=16) - { - *((int *)i)=0x0; - } -} - -void icache_enable (void) -{ - ulong reg; - - s3c44b0_flush_cache(); - - /* - Init cache - Non-cacheable area (everything outside RAM) - 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; - - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; -} - -void icache_disable (void) -{ - ulong reg; - - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; -} - -int icache_status (void) -{ - return 0; -} - -void dcache_enable (void) -{ - icache_enable(); -} - -void dcache_disable (void) -{ - icache_disable(); -} - -int dcache_status (void) -{ - return dcache_status(); -} diff --git a/arch/arm/cpu/s3c44b0/config.mk b/arch/arm/cpu/s3c44b0/config.mk deleted file mode 100644 index b902ca36a8..0000000000 --- a/arch/arm/cpu/s3c44b0/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/s3c44b0/cpu.c b/arch/arm/cpu/s3c44b0/cpu.c deleted file mode 100644 index fa931503a0..0000000000 --- a/arch/arm/cpu/s3c44b0/cpu.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * S3C44B0 CPU specific code - */ - -#include -#include -#include - -int arch_cpu_init (void) -{ - icache_enable(); - - return 0; -} - -int cleanup_before_linux (void) -{ - /* - cache memory should be enabled before calling - Linux to make the kernel uncompression faster - */ - icache_enable(); - - disable_interrupts (); - - return 0; -} - -void reset_cpu (ulong addr) -{ - /* - reset the cpu using watchdog - */ - - /* Disable the watchdog.*/ - WTCON&=~(1<<5); - - /* set the timeout value to a short time... */ - WTCNT = 0x1; - - /* Enable the watchdog. */ - WTCON|=1; - WTCON|=(1<<5); - - while(1) { - /*NOP*/ - } -} diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S deleted file mode 100644 index 6a59592f4c..0000000000 --- a/arch/arm/cpu/s3c44b0/start.S +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Startup Code for S3C44B0 CPU-core - * - * (C) Copyright 2004 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Jump vector table - */ - - -.globl _start -_start: b reset - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate u-boot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - bl lowlevel_init -#endif - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - bx lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -#define INTCON (0x01c00000+0x200000) -#define INTMSK (0x01c00000+0x20000c) -#define LOCKTIME (0x01c00000+0x18000c) -#define PLLCON (0x01c00000+0x180000) -#define CLKCON (0x01c00000+0x180004) -#define WTCON (0x01c00000+0x130000) -cpu_init_crit: - /* disable watch dog */ - ldr r0, =WTCON - ldr r1, =0x0 - str r1, [r0] - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - ldr r1,=INTMSK - ldr r0, =0x03fffeff - str r0, [r1] - - ldr r1, =INTCON - ldr r0, =0x05 - str r0, [r1] - - /* Set Clock Control Register */ - ldr r1, =LOCKTIME - ldrb r0, =800 - strb r0, [r1] - - ldr r1, =PLLCON - -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - - str r0, [r1] - - ldr r1,=CLKCON - ldr r0, =0x7ff8 - str r0, [r1] - - mov pc, lr - - -/*************************************************/ -/* interrupt vectors */ -/*************************************************/ -real_vectors: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/*************************************************/ - -undefined_instruction: - mov r6, #3 - b reset - -software_interrupt: - mov r6, #4 - b reset - -prefetch_abort: - mov r6, #5 - b reset - -data_abort: - mov r6, #6 - b reset - -not_used: - /* we *should* never reach this */ - mov r6, #7 - b reset - -irq: - mov r6, #8 - b reset - -fiq: - mov r6, #9 - b reset diff --git a/arch/arm/cpu/s3c44b0/timer.c b/arch/arm/cpu/s3c44b0/timer.c deleted file mode 100644 index f25af7a390..0000000000 --- a/arch/arm/cpu/s3c44b0/timer.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* we always count down the max. */ -#define TIMER_LOAD_VAL 0xffff - -/* macro to read the 16 bit timer */ -#define READ_TIMER (TCNTO1 & 0xffff) - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ NOT supported -#endif - -static ulong timestamp; -static ulong lastdec; - -int timer_init (void) -{ - TCFG0 = 0x000000E9; - TCFG1 = 0x00000004; - TCON = 0x00000900; - TCNTB1 = TIMER_LOAD_VAL; - TCMPB1 = 0; - TCON = 0x00000B00; - TCON = 0x00000900; - - - lastdec = TCNTB1 = TIMER_LOAD_VAL; - timestamp = 0; - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void __udelay (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 8; - - tmo += get_timer (0); - - while (get_timer_masked () < tmo) - /*NOP*/; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 8; - } else { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*8); - } - - endtime = get_timer(0) + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} diff --git a/arch/arm/cpu/sa1100/Makefile b/arch/arm/cpu/sa1100/Makefile index c84b7b975e..85a0d28f4b 100644 --- a/arch/arm/cpu/sa1100/Makefile +++ b/arch/arm/cpu/sa1100/Makefile @@ -5,29 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y = start.o -LIB = $(obj)lib$(CPU).o - -START = start.o - -COBJS += cpu.o -COBJS += timer.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += cpu.o +obj-y += timer.o diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk index 576f685c58..3afa685b3f 100644 --- a/arch/arm/cpu/sa1100/config.mk +++ b/arch/arm/cpu/sa1100/config.mk @@ -6,13 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c index 6651898de2..4c9752a1c8 100644 --- a/arch/arm/cpu/sa1100/cpu.c +++ b/arch/arm/cpu/sa1100/cpu.c @@ -17,6 +17,7 @@ #include #include #include +#include #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; @@ -52,3 +53,16 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } + +#define RST_BASE 0x90030000 +#define RSRR 0x00 +#define RCSR 0x04 + +__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +{ + /* repeat endlessly */ + while (1) { + writel(0, RST_BASE + RCSR); + writel(1, RST_BASE + RSRR); + } +} diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 27bcda598c..78e0cb8868 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -13,36 +13,6 @@ #include #include -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - /* ************************************************************************* * @@ -56,52 +26,7 @@ _fiq: .word fiq ************************************************************************* */ -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -199,177 +124,3 @@ cpu_init_crit: mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r0, RST_BASE - mov r1, #0x0 @ set bit 3-0 ... - str r1, [r0, #RCSR] @ ... to clear in RCSR - mov r1, #0x1 - str r1, [r0, #RSRR] @ and perform reset - b reset_cpu @ silly, but repeat endlessly diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c index 4b981e46e7..0a0006b426 100644 --- a/arch/arm/cpu/sa1100/timer.c +++ b/arch/arm/cpu/sa1100/timer.c @@ -13,11 +13,6 @@ #include #include -int timer_init (void) -{ - return 0; -} - ulong get_timer (ulong base) { return get_timer_masked (); diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index 1b6cdf71a5..a78869ee23 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -7,26 +7,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libcputegra-common.o - -SOBJS += lowlevel_init.o -COBJS-y += ap.o board.o sys_info.o timer.o clock.o cache.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += ap.o +obj-y += board.o +obj-y += cache.o +obj-y += clock.o +obj-y += lowlevel_init.o +obj-y += pinmux-common.o +obj-y += powergate.o +obj-y += xusb-padctl.o +obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o +obj-$(CONFIG_TEGRA124) += vpr.o diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 6fb11cb5c4..a17dfd1e22 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -1,5 +1,5 @@ /* -* (C) Copyright 2010-2011 +* (C) Copyright 2010-2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -27,7 +27,7 @@ int tegra_get_chip(void) /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for - * Tegra30, and 0x35 for T114. + * Tegra30, 0x35 for T114, and 0x40 for Tegra124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; debug("%s: CHIPID is 0x%02X\n", __func__, rev); @@ -71,6 +71,8 @@ int tegra_get_chip_sku(void) switch (sku_id) { case SKU_ID_T33: case SKU_ID_T30: + case SKU_ID_TM30MQS_P_A3: + default: return TEGRA_SOC_T30; } break; @@ -78,10 +80,19 @@ int tegra_get_chip_sku(void) switch (sku_id) { case SKU_ID_T114_ENG: case SKU_ID_T114_1: + default: return TEGRA_SOC_T114; } break; + case CHIPID_TEGRA124: + switch (sku_id) { + case SKU_ID_T124_ENG: + default: + return TEGRA_SOC_T124; + } + break; } + /* unknown chip/sku id */ printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", __func__, chip_id, sku_id); @@ -116,8 +127,8 @@ static u32 get_odmdata(void) * ODMDATA is stored in the BCT in IRAM by the BootROM. * The BCT start and size are stored in the BIT in IRAM. * Read the data @ bct_start + (bct_size - 12). This works - * on T20 and T30 BCTs, which are locked down. If this changes - * in new chips (T114, etc.), we can revisit this algorithm. + * on BCTs for currently supported SoCs, which are locked down. + * If this changes in new chips, we can revisit this algorithm. */ u32 bct_start, odmdata; @@ -152,4 +163,7 @@ void s_init(void) /* init the cache */ config_cache(); + + /* init vpr */ + config_vpr(); } diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c index d9cbda8a74..b6a84a5774 100644 --- a/arch/arm/cpu/tegra-common/board.c +++ b/arch/arm/cpu/tegra-common/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -27,50 +28,27 @@ enum { UART_COUNT = 5, }; -/* - * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0, - * so we are using this value to identify memory size. - */ - +/* Read the RAM size directly from the memory controller */ unsigned int query_sdram_size(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - u32 reg; - - reg = readl(&pmc->pmc_scratch20); - debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg); + struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; + u32 size_mb; + size_mb = readl(&mc->mc_emem_cfg); #if defined(CONFIG_TEGRA20) - /* bits 30:28 in OdmData are used for RAM size on T20 */ - reg &= 0x70000000; - - switch ((reg) >> 28) { - case 1: - return 0x10000000; /* 256 MB */ - case 0: - case 2: - default: - return 0x20000000; /* 512 MB */ - case 3: - return 0x40000000; /* 1GB */ - } -#else /* Tegra30/Tegra114 */ - /* bits 31:28 in OdmData are used for RAM size on T30 */ - switch ((reg) >> 28) { - case 0: - case 1: - default: - return 0x10000000; /* 256 MB */ - case 2: - return 0x20000000; /* 512 MB */ - case 3: - return 0x30000000; /* 768 MB */ - case 4: - return 0x40000000; /* 1GB */ - case 8: - return 0x7ff00000; /* 2GB - 1MB */ - } + debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb); + size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024); +#else + debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb); + size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024); #endif + +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) + /* External memory limited to 2047 MB due to IROM/HI-VEC */ + if (size_mb == SZ_2G) size_mb -= SZ_1M; +#endif + + return size_mb; } int dram_init(void) @@ -109,12 +87,18 @@ static int uart_configs[] = { -1, -1, -1, -#else /* Tegra114 */ +#elif defined(CONFIG_TEGRA114) -1, -1, -1, FUNCMUX_UART4_GMI, /* UARTD */ -1, +#else /* Tegra124 */ + FUNCMUX_UART1_KBC, /* UARTA */ + -1, + -1, + FUNCMUX_UART4_GPIO, /* UARTD */ + -1, #endif }; diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c index 48e9319c75..94f5bce90e 100644 --- a/arch/arm/cpu/tegra-common/cache.c +++ b/arch/arm/cpu/tegra-common/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,8 +23,6 @@ void config_cache(void) { - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; u32 reg = 0; /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ @@ -33,10 +31,10 @@ void config_cache(void) "orr r0, r0, #0x41\n" "mcr p15, 0, r0, c1, c0, 1\n"); - /* Currently, only T114 needs this L2 cache change to boot Linux */ - reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); - if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) + /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ + if (tegra_get_chip() < CHIPID_TEGRA114) return; + /* * Systems with an architectural L2 cache must not use the PL310. * Config L2CTLR here for a data RAM latency of 3 cycles. diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 268fb912b5..11c7435505 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, value = readl(reg); - value &= ~OUT_CLK_SOURCE_MASK; - value |= source << OUT_CLK_SOURCE_SHIFT; + value &= ~OUT_CLK_SOURCE_31_30_MASK; + value |= source << OUT_CLK_SOURCE_31_30_SHIFT; value &= ~OUT_CLK_DIVISOR_MASK; value |= divisor << OUT_CLK_DIVISOR_SHIFT; @@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source) { u32 *reg = get_periph_source_reg(periph_id); - clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, - source << OUT_CLK_SOURCE_SHIFT); + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, + source << OUT_CLK_SOURCE_31_30_SHIFT); } /** @@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, /* work out the source clock and set it */ if (source < 0) return -1; - if (mux_bits == 4) { - clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, - source << OUT_CLK_SOURCE4_SHIFT); - } else { - clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, - source << OUT_CLK_SOURCE_SHIFT); + + switch (mux_bits) { + case MASK_BITS_31_30: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, + source << OUT_CLK_SOURCE_31_30_SHIFT); + break; + + case MASK_BITS_31_29: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, + source << OUT_CLK_SOURCE_31_29_SHIFT); + break; + + case MASK_BITS_31_28: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, + source << OUT_CLK_SOURCE_31_28_SHIFT); + break; + + default: + return -1; } + udelay(2); return 0; } @@ -561,3 +575,95 @@ void clock_init(void) /* Do any special system timer/TSC setup */ arch_timer_init(); } + +static void set_avp_clock_source(u32 src) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | + (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | + (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | + (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | + (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); + writel(val, &clkrst->crc_sclk_brst_pol); + udelay(3); +} + +/* + * This function is useful on Tegra30, and any later SoCs that have compatible + * PLLP configuration registers. + */ +void tegra30_set_up_pllp(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + /* + * Based on the Tegra TRM, the system clock (which is the AVP clock) can + * run up to 275MHz. On power on, the default sytem clock source is set + * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to + * 408MHz which is beyond system clock's upper limit. + * + * The fix is to set the system clock to CLK_M before initializing PLLP, + * and then switch back to PLLP_OUT4, which has an appropriate divider + * configured, after PLLP has been configured + */ + set_avp_clock_source(SCLK_SOURCE_CLKM); + + /* + * PLLP output frequency set to 408Mhz + * PLLC output frequency set to 228Mhz + */ + switch (clock_get_osc_freq()) { + case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ + clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); + break; + + case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ + clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); + break; + + case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); + break; + case CLOCK_OSC_FREQ_19_2: + default: + /* + * These are not supported. It is too early to print a + * message and the UART likely won't work anyway due to the + * oscillator being wrong. + */ + break; + } + + /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ + + /* OUT1, 2 */ + /* Assert RSTN before enable */ + reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); + /* Set divisor and reenable */ + reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) + | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS + | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) + | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); + + /* OUT3, 4 */ + /* Assert RSTN before enable */ + reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + /* Set divisor and reenable */ + reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) + | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) + | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + + set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4); +} diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c new file mode 100644 index 0000000000..6e3ab0c14c --- /dev/null +++ b/arch/arm/cpu/tegra-common/pinmux-common.c @@ -0,0 +1,527 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* return 1 if a pingrp is in range */ +#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT)) + +/* return 1 if a pmux_func is in range */ +#define pmux_func_isvalid(func) \ + (((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) + +/* return 1 if a pin_pupd_is in range */ +#define pmux_pin_pupd_isvalid(pupd) \ + (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP)) + +/* return 1 if a pin_tristate_is in range */ +#define pmux_pin_tristate_isvalid(tristate) \ + (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE)) + +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +/* return 1 if a pin_io_is in range */ +#define pmux_pin_io_isvalid(io) \ + (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT)) + +/* return 1 if a pin_lock is in range */ +#define pmux_pin_lock_isvalid(lock) \ + (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE)) + +/* return 1 if a pin_od is in range */ +#define pmux_pin_od_isvalid(od) \ + (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE)) + +/* return 1 if a pin_ioreset_is in range */ +#define pmux_pin_ioreset_isvalid(ioreset) \ + (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \ + ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) + +#ifdef TEGRA_PMX_HAS_RCV_SEL +/* return 1 if a pin_rcv_sel_is in range */ +#define pmux_pin_rcv_sel_isvalid(rcv_sel) \ + (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \ + ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) +#endif /* TEGRA_PMX_HAS_RCV_SEL */ +#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ + +#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset)) + +#if defined(CONFIG_TEGRA20) + +#define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4)) +#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2) + +#define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4)) +#define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2) + +#define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4)) +#define TRI_SHIFT(grp) ((grp) % 32) + +#else + +#define REG(pin) _R(0x3000 + ((pin) * 4)) + +#define MUX_REG(pin) REG(pin) +#define MUX_SHIFT(pin) 0 + +#define PULL_REG(pin) REG(pin) +#define PULL_SHIFT(pin) 2 + +#define TRI_REG(pin) REG(pin) +#define TRI_SHIFT(pin) 4 + +#endif /* CONFIG_TEGRA20 */ + +#define DRV_REG(group) _R(0x868 + ((group) * 4)) + +#define IO_SHIFT 5 +#define OD_SHIFT 6 +#define LOCK_SHIFT 7 +#define IO_RESET_SHIFT 8 +#define RCV_SEL_SHIFT 9 + +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +/* This register/field only exists on Tegra114 and later */ +#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40 +#define CLAMP_INPUTS_WHEN_TRISTATED 1 + +void pinmux_set_tristate_input_clamping(void) +{ + u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); + u32 val; + + val = readl(reg); + val |= CLAMP_INPUTS_WHEN_TRISTATED; + writel(val, reg); +} +#endif + +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) +{ + u32 *reg = MUX_REG(pin); + int i, mux = -1; + u32 val; + + if (func == PMUX_FUNC_DEFAULT) + return; + + /* Error check on pin and func */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_func_isvalid(func)); + + if (func >= PMUX_FUNC_RSVD1) { + mux = (func - PMUX_FUNC_RSVD1) & 3; + } else { + /* Search for the appropriate function */ + for (i = 0; i < 4; i++) { + if (tegra_soc_pingroups[pin].funcs[i] == func) { + mux = i; + break; + } + } + } + assert(mux != -1); + + val = readl(reg); + val &= ~(3 << MUX_SHIFT(pin)); + val |= (mux << MUX_SHIFT(pin)); + writel(val, reg); +} + +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd) +{ + u32 *reg = PULL_REG(pin); + u32 val; + + /* Error check on pin and pupd */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_pupd_isvalid(pupd)); + + val = readl(reg); + val &= ~(3 << PULL_SHIFT(pin)); + val |= (pupd << PULL_SHIFT(pin)); + writel(val, reg); +} + +static void pinmux_set_tristate(enum pmux_pingrp pin, int tri) +{ + u32 *reg = TRI_REG(pin); + u32 val; + + /* Error check on pin */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_tristate_isvalid(tri)); + + val = readl(reg); + if (tri == PMUX_TRI_TRISTATE) + val |= (1 << TRI_SHIFT(pin)); + else + val &= ~(1 << TRI_SHIFT(pin)); + writel(val, reg); +} + +void pinmux_tristate_enable(enum pmux_pingrp pin) +{ + pinmux_set_tristate(pin, PMUX_TRI_TRISTATE); +} + +void pinmux_tristate_disable(enum pmux_pingrp pin) +{ + pinmux_set_tristate(pin, PMUX_TRI_NORMAL); +} + +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io) +{ + u32 *reg = REG(pin); + u32 val; + + if (io == PMUX_PIN_NONE) + return; + + /* Error check on pin and io */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_io_isvalid(io)); + + val = readl(reg); + if (io == PMUX_PIN_INPUT) + val |= (io & 1) << IO_SHIFT; + else + val &= ~(1 << IO_SHIFT); + writel(val, reg); +} + +static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock) +{ + u32 *reg = REG(pin); + u32 val; + + if (lock == PMUX_PIN_LOCK_DEFAULT) + return; + + /* Error check on pin and lock */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_lock_isvalid(lock)); + + val = readl(reg); + if (lock == PMUX_PIN_LOCK_ENABLE) { + val |= (1 << LOCK_SHIFT); + } else { + if (val & (1 << LOCK_SHIFT)) + printf("%s: Cannot clear LOCK bit!\n", __func__); + val &= ~(1 << LOCK_SHIFT); + } + writel(val, reg); + + return; +} + +static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) +{ + u32 *reg = REG(pin); + u32 val; + + if (od == PMUX_PIN_OD_DEFAULT) + return; + + /* Error check on pin and od */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_od_isvalid(od)); + + val = readl(reg); + if (od == PMUX_PIN_OD_ENABLE) + val |= (1 << OD_SHIFT); + else + val &= ~(1 << OD_SHIFT); + writel(val, reg); + + return; +} + +static void pinmux_set_ioreset(enum pmux_pingrp pin, + enum pmux_pin_ioreset ioreset) +{ + u32 *reg = REG(pin); + u32 val; + + if (ioreset == PMUX_PIN_IO_RESET_DEFAULT) + return; + + /* Error check on pin and ioreset */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_ioreset_isvalid(ioreset)); + + val = readl(reg); + if (ioreset == PMUX_PIN_IO_RESET_ENABLE) + val |= (1 << IO_RESET_SHIFT); + else + val &= ~(1 << IO_RESET_SHIFT); + writel(val, reg); + + return; +} + +#ifdef TEGRA_PMX_HAS_RCV_SEL +static void pinmux_set_rcv_sel(enum pmux_pingrp pin, + enum pmux_pin_rcv_sel rcv_sel) +{ + u32 *reg = REG(pin); + u32 val; + + if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT) + return; + + /* Error check on pin and rcv_sel */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_rcv_sel_isvalid(rcv_sel)); + + val = readl(reg); + if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH) + val |= (1 << RCV_SEL_SHIFT); + else + val &= ~(1 << RCV_SEL_SHIFT); + writel(val, reg); + + return; +} +#endif /* TEGRA_PMX_HAS_RCV_SEL */ +#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ + +static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) +{ + enum pmux_pingrp pin = config->pingrp; + + pinmux_set_func(pin, config->func); + pinmux_set_pullupdown(pin, config->pull); + pinmux_set_tristate(pin, config->tristate); +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC + pinmux_set_io(pin, config->io); + pinmux_set_lock(pin, config->lock); + pinmux_set_od(pin, config->od); + pinmux_set_ioreset(pin, config->ioreset); +#ifdef TEGRA_PMX_HAS_RCV_SEL + pinmux_set_rcv_sel(pin, config->rcv_sel); +#endif +#endif +} + +void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, + int len) +{ + int i; + + for (i = 0; i < len; i++) + pinmux_config_pingrp(&config[i]); +} + +#ifdef TEGRA_PMX_HAS_DRVGRPS + +#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT)) + +#define pmux_slw_isvalid(slw) \ + (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX)) + +#define pmux_drv_isvalid(drv) \ + (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX)) + +#define pmux_lpmd_isvalid(lpm) \ + (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X)) + +#define pmux_schmt_isvalid(schmt) \ + (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE)) + +#define pmux_hsm_isvalid(hsm) \ + (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) + +#define HSM_SHIFT 2 +#define SCHMT_SHIFT 3 +#define LPMD_SHIFT 4 +#define LPMD_MASK (3 << LPMD_SHIFT) +#define DRVDN_SHIFT 12 +#define DRVDN_MASK (0x7F << DRVDN_SHIFT) +#define DRVUP_SHIFT 20 +#define DRVUP_MASK (0x7F << DRVUP_SHIFT) +#define SLWR_SHIFT 28 +#define SLWR_MASK (3 << SLWR_SHIFT) +#define SLWF_SHIFT 30 +#define SLWF_MASK (3 << SLWF_SHIFT) + +static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf) +{ + u32 *reg = DRV_REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (slwf == PMUX_SLWF_NONE) + return; + + /* Error check on pad and slwf */ + assert(pmux_drvgrp_isvalid(grp)); + assert(pmux_slw_isvalid(slwf)); + + val = readl(reg); + val &= ~SLWF_MASK; + val |= (slwf << SLWF_SHIFT); + writel(val, reg); + + return; +} + +static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr) +{ + u32 *reg = DRV_REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (slwr == PMUX_SLWR_NONE) + return; + + /* Error check on pad and slwr */ + assert(pmux_drvgrp_isvalid(grp)); + assert(pmux_slw_isvalid(slwr)); + + val = readl(reg); + val &= ~SLWR_MASK; + val |= (slwr << SLWR_SHIFT); + writel(val, reg); + + return; +} + +static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup) +{ + u32 *reg = DRV_REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (drvup == PMUX_DRVUP_NONE) + return; + + /* Error check on pad and drvup */ + assert(pmux_drvgrp_isvalid(grp)); + assert(pmux_drv_isvalid(drvup)); + + val = readl(reg); + val &= ~DRVUP_MASK; + val |= (drvup << DRVUP_SHIFT); + writel(val, reg); + + return; +} + +static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn) +{ + u32 *reg = DRV_REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (drvdn == PMUX_DRVDN_NONE) + return; + + /* Error check on pad and drvdn */ + assert(pmux_drvgrp_isvalid(grp)); + assert(pmux_drv_isvalid(drvdn)); + + val = readl(reg); + val &= ~DRVDN_MASK; + val |= (drvdn << DRVDN_SHIFT); + writel(val, reg); + + return; +} + +static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd) +{ + u32 *reg = DRV_REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (lpmd == PMUX_LPMD_NONE) + return; + + /* Error check pad and lpmd value */ + assert(pmux_drvgrp_isvalid(grp)); + assert(pmux_lpmd_isvalid(lpmd)); + + val = readl(reg); + val &= ~LPMD_MASK; + val |= (lpmd << LPMD_SHIFT); + writel(val, reg); + + return; +} + +static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt) +{ + u32 *reg = DRV_REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (schmt == PMUX_SCHMT_NONE) + return; + + /* Error check pad */ + assert(pmux_drvgrp_isvalid(grp)); + assert(pmux_schmt_isvalid(schmt)); + + val = readl(reg); + if (schmt == PMUX_SCHMT_ENABLE) + val |= (1 << SCHMT_SHIFT); + else + val &= ~(1 << SCHMT_SHIFT); + writel(val, reg); + + return; +} + +static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm) +{ + u32 *reg = DRV_REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (hsm == PMUX_HSM_NONE) + return; + + /* Error check pad */ + assert(pmux_drvgrp_isvalid(grp)); + assert(pmux_hsm_isvalid(hsm)); + + val = readl(reg); + if (hsm == PMUX_HSM_ENABLE) + val |= (1 << HSM_SHIFT); + else + val &= ~(1 << HSM_SHIFT); + writel(val, reg); + + return; +} + +static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config) +{ + enum pmux_drvgrp grp = config->drvgrp; + + pinmux_set_drvup_slwf(grp, config->slwf); + pinmux_set_drvdn_slwr(grp, config->slwr); + pinmux_set_drvup(grp, config->drvup); + pinmux_set_drvdn(grp, config->drvdn); + pinmux_set_lpmd(grp, config->lpmd); + pinmux_set_schmt(grp, config->schmt); + pinmux_set_hsm(grp, config->hsm); +} + +void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, + int len) +{ + int i; + + for (i = 0; i < len; i++) + pinmux_config_drvgrp(&config[i]); +} +#endif /* TEGRA_PMX_HAS_DRVGRPS */ diff --git a/arch/arm/cpu/tegra-common/powergate.c b/arch/arm/cpu/tegra-common/powergate.c new file mode 100644 index 0000000000..439cff36b9 --- /dev/null +++ b/arch/arm/cpu/tegra-common/powergate.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include +#include + +#include +#include + +#define PWRGATE_TOGGLE 0x30 +#define PWRGATE_TOGGLE_START (1 << 8) + +#define REMOVE_CLAMPING 0x34 + +#define PWRGATE_STATUS 0x38 + +static int tegra_powergate_set(enum tegra_powergate id, bool state) +{ + u32 value, mask = state ? (1 << id) : 0, old_mask; + unsigned long start, timeout = 25; + + value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); + old_mask = value & (1 << id); + + if (mask == old_mask) + return 0; + + writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE); + + start = get_timer(0); + + while (get_timer(start) < timeout) { + value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); + if ((value & (1 << id)) == mask) + return 0; + } + + return -ETIMEDOUT; +} + +static int tegra_powergate_power_on(enum tegra_powergate id) +{ + return tegra_powergate_set(id, true); +} + +int tegra_powergate_power_off(enum tegra_powergate id) +{ + return tegra_powergate_set(id, false); +} + +static int tegra_powergate_remove_clamping(enum tegra_powergate id) +{ + unsigned long value; + + /* + * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC + * partitions reversed. This was originally introduced on Tegra20 but + * has since been carried forward for backwards-compatibility. + */ + if (id == TEGRA_POWERGATE_VDEC) + value = 1 << TEGRA_POWERGATE_PCIE; + else if (id == TEGRA_POWERGATE_PCIE) + value = 1 << TEGRA_POWERGATE_VDEC; + else + value = 1 << id; + + writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING); + + return 0; +} + +int tegra_powergate_sequence_power_up(enum tegra_powergate id, + enum periph_id periph) +{ + int err; + + reset_set_enable(periph, 1); + + err = tegra_powergate_power_on(id); + if (err < 0) + return err; + + clock_enable(periph); + + udelay(10); + + err = tegra_powergate_remove_clamping(id); + if (err < 0) + return err; + + udelay(10); + + reset_set_enable(periph, 0); + + return 0; +} diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c index dc8a2e4d31..5933c35ddd 100644 --- a/arch/arm/cpu/tegra-common/sys_info.c +++ b/arch/arm/cpu/tegra-common/sys_info.c @@ -8,8 +8,7 @@ #include #include -#ifdef CONFIG_DISPLAY_CPUINFO -void upstring(char *s) +static void upstring(char *s) { while (*s) { *s = toupper(*s); @@ -30,4 +29,3 @@ int print_cpuinfo(void) /* TBD: Add printf of major/minor rev info, stepping, etc. */ return 0; } -#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/tegra-common/timer.c b/arch/arm/cpu/tegra-common/timer.c deleted file mode 100644 index d0f783e660..0000000000 --- a/arch/arm/cpu/tegra-common/timer.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * - * (C) Copyright 2008 - * Texas Instruments - * - * Richard Woodruff - * Syed Moahmmed Khasim - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* counter runs at 1MHz */ -#define TIMER_CLK 1000000 -#define TIMER_LOAD_VAL 0xffffffff - -/* timer without interrupts */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds */ -void __udelay(unsigned long usec) -{ - long tmo = usec * (TIMER_CLK / 1000) / 1000; - unsigned long now, last = timer_get_us(); - - while (tmo > 0) { - now = timer_get_us(); - if (last > now) /* count up timer overflow */ - tmo -= TIMER_LOAD_VAL - last + now; - else - tmo -= now - last; - last = now; - } -} - -ulong get_timer_masked(void) -{ - ulong now; - - /* current tick value */ - now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ); - - if (now >= gd->arch.lastinc) /* normal mode (non roll) */ - /* move stamp forward with absolute diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - else /* we have rollover of incrementer */ - gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ)) - - gd->arch.lastinc) + now; - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} - -unsigned long timer_get_us(void) -{ - struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE; - - return readl(&timer_base->cntr_1us); -} diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c new file mode 100644 index 0000000000..f695811c9b --- /dev/null +++ b/arch/arm/cpu/tegra-common/vpr.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Tegra vpr routines */ + +#include +#include +#include +#include + +/* Configures VPR. Right now, all we do is turn it off. */ +void config_vpr(void) +{ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + + /* Turn VPR off */ + writel(0, &mc->mc_video_protect_size_mb); + writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, + &mc->mc_video_protect_reg_ctrl); + /* read back to ensure the write went through */ + readl(&mc->mc_video_protect_reg_ctrl); +} diff --git a/arch/arm/cpu/tegra-common/xusb-padctl.c b/arch/arm/cpu/tegra-common/xusb-padctl.c new file mode 100644 index 0000000000..65f8d2ea96 --- /dev/null +++ b/arch/arm/cpu/tegra-common/xusb-padctl.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include + +struct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type) +{ + return NULL; +} + +int __weak tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) +{ + return -ENOSYS; +} + +int __weak tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) +{ + return -ENOSYS; +} + +int __weak tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) +{ + return -ENOSYS; +} + +int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) +{ + return -ENOSYS; +} + +void __weak tegra_xusb_padctl_init(const void *fdt) +{ +} diff --git a/arch/arm/cpu/tegra114-common/Makefile b/arch/arm/cpu/tegra114-common/Makefile index 5b53a71ba3..d959b575ce 100644 --- a/arch/arm/cpu/tegra114-common/Makefile +++ b/arch/arm/cpu/tegra114-common/Makefile @@ -17,25 +17,4 @@ # along with this program. If not, see . # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC)-common.o - -COBJS-y += clock.o funcmux.o pinmux.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += clock.o funcmux.o pinmux.o diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 5c4305a418..d5194e11b5 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -61,12 +61,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. @@ -109,7 +103,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { MASK_BITS_31_29}, { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_29_28} + MASK_BITS_31_28} }; /* @@ -610,26 +604,24 @@ void clock_early_init(void) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + tegra30_set_up_pllp(); + /* - * PLLP output frequency set to 408Mhz * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz */ switch (clock_get_osc_freq()) { case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); break; case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); break; case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); break; diff --git a/arch/arm/cpu/tegra114-common/funcmux.c b/arch/arm/cpu/tegra114-common/funcmux.c index 5af755034d..52441c71e6 100644 --- a/arch/arm/cpu/tegra114-common/funcmux.c +++ b/arch/arm/cpu/tegra114-common/funcmux.c @@ -29,20 +29,24 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_UART4: switch (config) { case FUNCMUX_UART4_GMI: - pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD); - - pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT); - pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT); - pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT); - pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT); - - pinmux_tristate_disable(PINGRP_GMI_A16); - pinmux_tristate_disable(PINGRP_GMI_A17); - pinmux_tristate_disable(PINGRP_GMI_A18); - pinmux_tristate_disable(PINGRP_GMI_A19); + pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7, + PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0, + PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1, + PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7, + PMUX_FUNC_UARTD); + + pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT); + + pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1); + pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7); break; } break; diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c index 4983a05090..3e5acb93ce 100644 --- a/arch/arm/cpu/tegra114-common/pinmux.c +++ b/arch/arm/cpu/tegra114-common/pinmux.c @@ -1,112 +1,57 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0+ */ -/* Tegra114 pin multiplexing functions */ - #include #include -#include #include -struct tegra_pingroup_desc { - const char *name; - enum pmux_func funcs[4]; - enum pmux_func func_safe; - enum pmux_vddio vddio; - enum pmux_pin_io io; -}; - -#define PMUX_MUXCTL_SHIFT 0 -#define PMUX_PULL_SHIFT 2 -#define PMUX_TRISTATE_SHIFT 4 -#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT) -#define PMUX_IO_SHIFT 5 -#define PMUX_OD_SHIFT 6 -#define PMUX_LOCK_SHIFT 7 -#define PMUX_IO_RESET_SHIFT 8 -#define PMUX_RCV_SEL_SHIFT 9 - -#define PGRP_HSM_SHIFT 2 -#define PGRP_SCHMT_SHIFT 3 -#define PGRP_LPMD_SHIFT 4 -#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT) -#define PGRP_DRVDN_SHIFT 12 -#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT) -#define PGRP_DRVUP_SHIFT 20 -#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT) -#define PGRP_SLWR_SHIFT 28 -#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT) -#define PGRP_SLWF_SHIFT 30 -#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT) - -/* Convenient macro for defining pin group properties */ -#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ - { \ - .vddio = PMUX_VDDIO_ ## vdd, \ - .funcs = { \ - PMUX_FUNC_ ## f0, \ - PMUX_FUNC_ ## f1, \ - PMUX_FUNC_ ## f2, \ - PMUX_FUNC_ ## f3, \ - }, \ - .func_safe = PMUX_FUNC_RSVD1, \ - .io = PMUX_PIN_ ## iod, \ +#define PIN(pin, f0, f1, f2, f3) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + PMUX_FUNC_##f2, \ + PMUX_FUNC_##f3, \ + }, \ } -/* Input and output pins */ -#define PINI(pg_name, vdd, f0, f1, f2, f3) \ - PIN(pg_name, vdd, f0, f1, f2, f3, INPUT) -#define PINO(pg_name, vdd, f0, f1, f2, f3) \ - PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT) - -/* A pin group number which is not used */ -#define PIN_RESERVED \ - PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE) +#define PIN_RESERVED {} -const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { - /* NAME VDD f0 f1 f2 f3 */ - PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI), - PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI), - PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI), - PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI), - PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI), - PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI), - PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI), - PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI), - PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI), - PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI), - PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI), - PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI), - PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB), - PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB), - PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB), - PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB), - PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4), - PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4), - PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA), - PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA), - PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA), - PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA), - PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA), - PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */ +static const struct pmux_pingrp_desc tegra114_pingroups[] = { + /* pin, f0, f1, f2, f3 */ + /* Offset 0x3000 */ + PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI), + PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI), + PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI), + PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI), + PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB), + PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB), + PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, DISPLAYB), + PIN(DAP3_SCLK_PP3, I2S2, SPI5, DISPLAYA, DISPLAYB), + PIN(PV0, USB, RSVD2, RSVD3, RSVD4), + PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4), + PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4), + PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA), + PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA), + PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA), + PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA), + PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA), + PIN_RESERVED, PIN_RESERVED, - PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4), - PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */ + /* Offset 0x3068 */ + PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4), + PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4), PIN_RESERVED, PIN_RESERVED, PIN_RESERVED, @@ -146,11 +91,11 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PIN_RESERVED, PIN_RESERVED, PIN_RESERVED, - PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4), - PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */ PIN_RESERVED, + /* Offset 0x3110 */ + PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4), + PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4), + PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4), PIN_RESERVED, PIN_RESERVED, PIN_RESERVED, @@ -167,574 +112,182 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PIN_RESERVED, PIN_RESERVED, PIN_RESERVED, - PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4), - PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4), - PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4), - PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4), - PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4), - PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4), - PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4), - PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA), - PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4), - PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4), - PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4), - PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB), - PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB), - PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB), - PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB), - PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4), - PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4), - PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4), - PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4), - PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4), - PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4), - PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4), - PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4), - PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT), - PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE), - PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV), - PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE), - PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE), - PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB), - PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC), - PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE), - PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT), - PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE), - PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4), - PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2), - PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4), - PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4), - PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4), - PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV), - PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS), - PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS), - PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB), - PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4), - PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4), - PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV), - PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV), - PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT), - PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE), - PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE), - PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE), - PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4), - PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC), - PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE), - PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4), - PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4), - PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4), - PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), - PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), - PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), - PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), - PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), - PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), - PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), - PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), - PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), - PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), - PIN_RESERVED, /* Reserved by t114: 0x3280 */ - PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4), - PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4), - PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3), - PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4), - PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4), - PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4), - PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4), - PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4), - PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4), - PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4), - PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4), - PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4), - PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4), - PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4), - PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4), - PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4), - PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC), - PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB), - PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB), - PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB), - PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB), - PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA), - PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA), - PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA), - PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA), - PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */ - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL), - PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL), - PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4), - PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA), - PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA), - PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4), - PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4), - PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4), - PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4), - PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4), - PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4), - PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4), - PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4), - PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4), - PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4), - PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4), - PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4), - PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4), - PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4), - PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4), - PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4), - PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4), - PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4), - PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4), - PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4), - PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4), - PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4), - PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4), - PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4), - PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4), - PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4), - PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2), - PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4), - PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4), - PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4), - PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */ - PIN_RESERVED, - PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3), - PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3), - PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3), - PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3), - PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3), - PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3), - PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */ - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC), - PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA), - PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4), - PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1), - PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1), - PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4), - PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4), - PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4), - PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, /* Reserved by t114: 0x3404 */ - PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N), + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x3164 */ + PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4), + PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4), + PIN(UART2_RTS_N_PJ6, UARTA, UARTB, RSVD3, SPI4), + PIN(UART2_CTS_N_PJ5, UARTA, UARTB, RSVD3, SPI4), + PIN(UART3_TXD_PW6, UARTC, RSVD2, RSVD3, SPI4), + PIN(UART3_RXD_PW7, UARTC, RSVD2, RSVD3, SPI4), + PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4), + PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, DISPLAYA), + PIN(PU0, OWR, UARTA, RSVD3, RSVD4), + PIN(PU1, RSVD1, UARTA, RSVD3, RSVD4), + PIN(PU2, RSVD1, UARTA, RSVD3, RSVD4), + PIN(PU3, PWM0, UARTA, DISPLAYA, DISPLAYB), + PIN(PU4, PWM1, UARTA, DISPLAYA, DISPLAYB), + PIN(PU5, PWM2, UARTA, DISPLAYA, DISPLAYB), + PIN(PU6, PWM3, UARTA, USB, DISPLAYB), + PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4), + PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4), + PIN(DAP4_FS_PP4, I2S3, RSVD2, DTV, RSVD4), + PIN(DAP4_DIN_PP5, I2S3, RSVD2, RSVD3, RSVD4), + PIN(DAP4_DOUT_PP6, I2S3, RSVD2, DTV, RSVD4), + PIN(DAP4_SCLK_PP7, I2S3, RSVD2, RSVD3, RSVD4), + PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4), + PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4), + PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT), + PIN(GMI_IORDY_PI5, SDMMC2, RSVD2, GMI, TRACE), + PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV), + PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE), + PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE), + PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB), + PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC), + PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE), + PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT), + PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE), + PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4), + PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, SDMMC2), + PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, SPI4), + PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, SPI4), + PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, SPI4), + PIN(GMI_AD8_PH0, PWM0, NAND, GMI, DTV), + PIN(GMI_AD9_PH1, PWM1, NAND, GMI, CLDVFS), + PIN(GMI_AD10_PH2, PWM2, NAND, GMI, CLDVFS), + PIN(GMI_AD11_PH3, PWM3, NAND, GMI, USB), + PIN(GMI_AD12_PH4, SDMMC2, NAND, GMI, RSVD4), + PIN(GMI_AD13_PH5, SDMMC2, NAND, GMI, RSVD4), + PIN(GMI_AD14_PH6, SDMMC2, NAND, GMI, DTV), + PIN(GMI_AD15_PH7, SDMMC2, NAND, GMI, DTV), + PIN(GMI_A16_PJ7, UARTD, TRACE, GMI, GMI_ALT), + PIN(GMI_A17_PB0, UARTD, RSVD2, GMI, TRACE), + PIN(GMI_A18_PB1, UARTD, RSVD2, GMI, TRACE), + PIN(GMI_A19_PK7, UARTD, SPI4, GMI, TRACE), + PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, SPI4), + PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, SOC), + PIN(GMI_DQS_P_PJ3, SDMMC2, NAND, GMI, TRACE), + PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4), + PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4), + PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4), + PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4), + PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4), + PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4), + PIN_RESERVED, + /* Offset 0x3284 */ + PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, RSVD4), + PIN(PCC1, I2S4, RSVD2, RSVD3, RSVD4), + PIN(PBB0, I2S4, VI, VI_ALT1, VI_ALT3), + PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, RSVD4), + PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, RSVD4), + PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, RSVD4), + PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, RSVD4), + PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, RSVD4), + PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, RSVD4), + PIN(PBB7, I2S4, RSVD2, RSVD3, RSVD4), + PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4), + PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4), + PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4), + PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW3_PR3, KBC, DISPLAYA, RSVD3, DISPLAYB), + PIN(KB_ROW4_PR4, KBC, DISPLAYA, SPI2, DISPLAYB), + PIN(KB_ROW5_PR5, KBC, DISPLAYA, SPI2, DISPLAYB), + PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB), + PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA), + PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA), + PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA), + PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA), + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x32fc */ + PIN(KB_COL0_PQ0, KBC, USB, SPI2, EMC_DLL), + PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, EMC_DLL), + PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4), + PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA), + PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA), + PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4), + PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, RSVD4), + PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, RSVD4), + PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4), + PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4), + PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4), + PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4), + PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4), + PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4), + PIN(OWR, OWR, RSVD2, RSVD3, RSVD4), + PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4), + PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4), + PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, RSVD4), + PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4), + PIN(CLK1_REQ_PEE2, DAP, DAP1, RSVD3, RSVD4), + PIN(CLK1_OUT_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4), + PIN(SPDIF_IN_PK6, SPDIF, USB, RSVD3, RSVD4), + PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, RSVD4), + PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, RSVD4), + PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, RSVD4), + PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, RSVD4), + PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, RSVD4), + PIN(DVFS_PWM_PX0, SPI6, CLDVFS, RSVD3, RSVD4), + PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, RSVD3, RSVD4), + PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, RSVD3, RSVD4), + PIN(DVFS_CLK_PX2, SPI6, CLDVFS, RSVD3, RSVD4), + PIN(GPIO_X4_AUD_PX4, RSVD1, SPI1, SPI2, DAP2), + PIN(GPIO_X5_AUD_PX5, RSVD1, SPI1, SPI2, RSVD4), + PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, RSVD4), + PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4), + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x3390 */ + PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3), + PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3), + PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3), + PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3), + PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3), + PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3), + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x33e0 */ + PIN(HDMI_CEC_PEE3, CEC, SDMMC3, RSVD3, SOC), + PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA), + PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4), + PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1), + PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1), + PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4), + PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4), + PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4), + PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4), + PIN(GMI_CLK_LB, SDMMC2, NAND, GMI, RSVD4), + PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N), }; - -void pinmux_set_tristate(enum pmux_pingrp pin, int enable) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *tri = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin */ - assert(pmux_pingrp_isvalid(pin)); - - reg = readl(tri); - if (enable) - reg |= PMUX_TRISTATE_MASK; - else - reg &= ~PMUX_TRISTATE_MASK; - writel(reg, tri); -} - -void pinmux_tristate_enable(enum pmux_pingrp pin) -{ - pinmux_set_tristate(pin, 1); -} - -void pinmux_tristate_disable(enum pmux_pingrp pin) -{ - pinmux_set_tristate(pin, 0); -} - -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pull = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and pupd */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_pupd_isvalid(pupd)); - - reg = readl(pull); - reg &= ~(0x3 << PMUX_PULL_SHIFT); - reg |= (pupd << PMUX_PULL_SHIFT); - writel(reg, pull); -} - -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *muxctl = &pmt->pmt_ctl[pin]; - int i, mux = -1; - u32 reg; - - /* Error check on pin and func */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_func_isvalid(func)); - - /* Handle special values */ - if (func == PMUX_FUNC_SAFE) - func = tegra_soc_pingroups[pin].func_safe; - - if (func & PMUX_FUNC_RSVD1) { - mux = func & 0x3; - } else { - /* Search for the appropriate function */ - for (i = 0; i < 4; i++) { - if (tegra_soc_pingroups[pin].funcs[i] == func) { - mux = i; - break; - } - } - } - assert(mux != -1); - - reg = readl(muxctl); - reg &= ~(0x3 << PMUX_MUXCTL_SHIFT); - reg |= (mux << PMUX_MUXCTL_SHIFT); - writel(reg, muxctl); - -} - -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_io = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and io */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_io_isvalid(io)); - - reg = readl(pin_io); - reg &= ~(0x1 << PMUX_IO_SHIFT); - reg |= (io & 0x1) << PMUX_IO_SHIFT; - writel(reg, pin_io); -} - -static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_lock = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and lock */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_lock_isvalid(lock)); - - if (lock == PMUX_PIN_LOCK_DEFAULT) - return 0; - - reg = readl(pin_lock); - reg &= ~(0x1 << PMUX_LOCK_SHIFT); - if (lock == PMUX_PIN_LOCK_ENABLE) - reg |= (0x1 << PMUX_LOCK_SHIFT); - else { - /* lock == DISABLE, which isn't possible */ - printf("%s: Warning: lock == %d, DISABLE is not allowed!\n", - __func__, lock); - } - writel(reg, pin_lock); - - return 0; -} - -static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_od = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and od */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_od_isvalid(od)); - - if (od == PMUX_PIN_OD_DEFAULT) - return 0; - - reg = readl(pin_od); - reg &= ~(0x1 << PMUX_OD_SHIFT); - if (od == PMUX_PIN_OD_ENABLE) - reg |= (0x1 << PMUX_OD_SHIFT); - writel(reg, pin_od); - - return 0; -} - -static int pinmux_set_ioreset(enum pmux_pingrp pin, - enum pmux_pin_ioreset ioreset) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_ioreset = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and ioreset */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_ioreset_isvalid(ioreset)); - - if (ioreset == PMUX_PIN_IO_RESET_DEFAULT) - return 0; - - reg = readl(pin_ioreset); - reg &= ~(0x1 << PMUX_IO_RESET_SHIFT); - if (ioreset == PMUX_PIN_IO_RESET_ENABLE) - reg |= (0x1 << PMUX_IO_RESET_SHIFT); - writel(reg, pin_ioreset); - - return 0; -} - -static int pinmux_set_rcv_sel(enum pmux_pingrp pin, - enum pmux_pin_rcv_sel rcv_sel) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_rcv_sel = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and rcv_sel */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_rcv_sel_isvalid(rcv_sel)); - - if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT) - return 0; - - reg = readl(pin_rcv_sel); - reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT); - if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH) - reg |= (0x1 << PMUX_RCV_SEL_SHIFT); - writel(reg, pin_rcv_sel); - - return 0; -} - -void pinmux_config_pingroup(struct pingroup_config *config) -{ - enum pmux_pingrp pin = config->pingroup; - - pinmux_set_func(pin, config->func); - pinmux_set_pullupdown(pin, config->pull); - pinmux_set_tristate(pin, config->tristate); - pinmux_set_io(pin, config->io); - pinmux_set_lock(pin, config->lock); - pinmux_set_od(pin, config->od); - pinmux_set_ioreset(pin, config->ioreset); - pinmux_set_rcv_sel(pin, config->rcv_sel); -} - -void pinmux_config_table(struct pingroup_config *config, int len) -{ - int i; - - for (i = 0; i < len; i++) - pinmux_config_pingroup(&config[i]); -} - -static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_slwf = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check on pad and slwf */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_slw_isvalid(slwf)); - - /* NONE means unspecified/do not change/use POR value */ - if (slwf == PGRP_SLWF_NONE) - return 0; - - reg = readl(pad_slwf); - reg &= ~PGRP_SLWF_MASK; - reg |= (slwf << PGRP_SLWF_SHIFT); - writel(reg, pad_slwf); - - return 0; -} - -static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_slwr = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check on pad and slwr */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_slw_isvalid(slwr)); - - /* NONE means unspecified/do not change/use POR value */ - if (slwr == PGRP_SLWR_NONE) - return 0; - - reg = readl(pad_slwr); - reg &= ~PGRP_SLWR_MASK; - reg |= (slwr << PGRP_SLWR_SHIFT); - writel(reg, pad_slwr); - - return 0; -} - -static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_drvup = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check on pad and drvup */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_drv_isvalid(drvup)); - - /* NONE means unspecified/do not change/use POR value */ - if (drvup == PGRP_DRVUP_NONE) - return 0; - - reg = readl(pad_drvup); - reg &= ~PGRP_DRVUP_MASK; - reg |= (drvup << PGRP_DRVUP_SHIFT); - writel(reg, pad_drvup); - - return 0; -} - -static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_drvdn = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check on pad and drvdn */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_drv_isvalid(drvdn)); - - /* NONE means unspecified/do not change/use POR value */ - if (drvdn == PGRP_DRVDN_NONE) - return 0; - - reg = readl(pad_drvdn); - reg &= ~PGRP_DRVDN_MASK; - reg |= (drvdn << PGRP_DRVDN_SHIFT); - writel(reg, pad_drvdn); - - return 0; -} - -static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_lpmd = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check pad and lpmd value */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_lpmd_isvalid(lpmd)); - - /* NONE means unspecified/do not change/use POR value */ - if (lpmd == PGRP_LPMD_NONE) - return 0; - - reg = readl(pad_lpmd); - reg &= ~PGRP_LPMD_MASK; - reg |= (lpmd << PGRP_LPMD_SHIFT); - writel(reg, pad_lpmd); - - return 0; -} - -static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_schmt = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check pad */ - assert(pmux_padgrp_isvalid(pad)); - - /* NONE means unspecified/do not change/use POR value */ - if (schmt == PGRP_SCHMT_NONE) - return 0; - - reg = readl(pad_schmt); - reg &= ~(1 << PGRP_SCHMT_SHIFT); - if (schmt == PGRP_SCHMT_ENABLE) - reg |= (0x1 << PGRP_SCHMT_SHIFT); - writel(reg, pad_schmt); - - return 0; -} -static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_hsm = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check pad */ - assert(pmux_padgrp_isvalid(pad)); - - /* NONE means unspecified/do not change/use POR value */ - if (hsm == PGRP_HSM_NONE) - return 0; - - reg = readl(pad_hsm); - reg &= ~(1 << PGRP_HSM_SHIFT); - if (hsm == PGRP_HSM_ENABLE) - reg |= (0x1 << PGRP_HSM_SHIFT); - writel(reg, pad_hsm); - - return 0; -} - -void padctrl_config_pingroup(struct padctrl_config *config) -{ - enum pdrive_pingrp pad = config->padgrp; - - padgrp_set_drvup_slwf(pad, config->slwf); - padgrp_set_drvdn_slwr(pad, config->slwr); - padgrp_set_drvup(pad, config->drvup); - padgrp_set_drvdn(pad, config->drvdn); - padgrp_set_lpmd(pad, config->lpmd); - padgrp_set_schmt(pad, config->schmt); - padgrp_set_hsm(pad, config->hsm); -} - -void padgrp_config_table(struct padctrl_config *config, int len) -{ - int i; - - for (i = 0; i < len; i++) - padctrl_config_pingroup(&config[i]); -} +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups; diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile new file mode 100644 index 0000000000..7b59fb1216 --- /dev/null +++ b/arch/arm/cpu/tegra124-common/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clock.o +obj-y += funcmux.o +obj-y += pinmux.o +obj-y += xusb-padctl.o diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c new file mode 100644 index 0000000000..fc8bd194dd --- /dev/null +++ b/arch/arm/cpu/tegra124-common/clock.c @@ -0,0 +1,935 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 Clock control functions */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Clock types that we can use as a source. The Tegra124 has muxes for the + * peripheral clocks, and in most cases there are four options for the clock + * source. This gives us a clock 'type' and exploits what commonality exists + * in the device. + * + * Letters are obvious, except for T which means CLK_M, and S which means the + * clock derived from 32KHz. Beware that CLK_M (also called OSC in the + * datasheet) and PLL_M are different things. The former is the basic + * clock supplied to the SOC from an external oscillator. The latter is the + * memory clock PLL. + * + * See definitions in clock_id in the header file. + */ +enum clock_type_id { + CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ + CLOCK_TYPE_MCPA, /* and so on */ + CLOCK_TYPE_MCPT, + CLOCK_TYPE_PCM, + CLOCK_TYPE_PCMT, + CLOCK_TYPE_PDCT, + CLOCK_TYPE_ACPT, + CLOCK_TYPE_ASPTE, + CLOCK_TYPE_PMDACD2T, + CLOCK_TYPE_PCST, + + CLOCK_TYPE_PC2CC3M, + CLOCK_TYPE_PC2CC3S_T, + CLOCK_TYPE_PC2CC3M_T, + CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ + CLOCK_TYPE_MC2CC3P_A, + CLOCK_TYPE_M, + CLOCK_TYPE_MCPTM2C2C3, + CLOCK_TYPE_PC2CC3T_S, + CLOCK_TYPE_AC2CC3P_TS2, + + CLOCK_TYPE_COUNT, + CLOCK_TYPE_NONE = -1, /* invalid clock type */ +}; + +enum { + CLOCK_MAX_MUX = 8 /* number of source options for each clock */ +}; + +/* + * Clock source mux for each clock type. This just converts our enum into + * a list of mux sources for use by the code. + * + * Note: + * The extra column in each clock source array is used to store the mask + * bits in its register for the source. + */ +#define CLK(x) CLOCK_ID_ ## x +static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { + { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), + CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), + CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_28}, + + /* Additional clock types on Tegra114+ */ + /* CLOCK_TYPE_PC2CC3M */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3S_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_MC2CC3P_A */ + { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_M */ + { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + /* CLOCK_TYPE_MCPTM2C2C3 */ + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3T_S */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_AC2CC3P_TS2 */ + { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), + MASK_BITS_31_29}, +}; + +/* + * Clock type for each peripheral clock source. We put the name in each + * record just so it is easy to match things up + */ +#define TYPE(name, type) type +static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { + /* 0x00 */ + TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), + TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), + + /* 0x08 */ + TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), + TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), + + /* 0x10 */ + TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_16h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_17h, CLOCK_TYPE_NONE), + + /* 0x18 */ + TYPE(PERIPHC_18h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), + + /* 0x20 */ + TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), + TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), + + /* 0x28 */ + TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), + + /* 0x30 */ + TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), + + /* 0x38 */ + TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), + + /* 0x40 */ + TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */ + TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), + TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), + + /* 0x48 */ + TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), + + /* 0x50 */ + TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), + TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), + TYPE(PERIPHC_52h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), + + /* 0x58 */ + TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE), + + /* 0x60 */ + TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE), + + /* 0x68 */ + TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE), + TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE), + TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE), + TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE), + TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE), + + /* 0x70 */ + TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE), + TYPE(PERIPHC_72h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_73h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_74h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_75h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16), + + /* 0x78 */ + TYPE(PERIPHC_78h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3), + TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE), + TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE), + TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE), +}; + +/* + * This array translates a periph_id to a periphc_internal_id + * + * Not present/matched up: + * uint vi_sensor; _VI_SENSOR_0, 0x1A8 + * SPDIF - which is both 0x08 and 0x0c + * + */ +#define NONE(name) (-1) +#define OFFSET(name, value) PERIPHC_ ## name +static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { + /* Low word: 31:0 */ + NONE(CPU), + NONE(COP), + NONE(TRIGSYS), + NONE(ISPB), + NONE(RESERVED4), + NONE(TMR), + PERIPHC_UART1, + PERIPHC_UART2, /* and vfir 0x68 */ + + /* 8 */ + NONE(GPIO), + PERIPHC_SDMMC2, + PERIPHC_SPDIF_IN, + PERIPHC_I2S1, + PERIPHC_I2C1, + NONE(RESERVED13), + PERIPHC_SDMMC1, + PERIPHC_SDMMC4, + + /* 16 */ + NONE(TCW), + PERIPHC_PWM, + PERIPHC_I2S2, + NONE(RESERVED19), + PERIPHC_VI, + NONE(RESERVED21), + NONE(USBD), + NONE(ISP), + + /* 24 */ + NONE(RESERVED24), + NONE(RESERVED25), + PERIPHC_DISP2, + PERIPHC_DISP1, + PERIPHC_HOST1X, + NONE(VCP), + PERIPHC_I2S0, + NONE(CACHE2), + + /* Middle word: 63:32 */ + NONE(MEM), + NONE(AHBDMA), + NONE(APBDMA), + NONE(RESERVED35), + NONE(RESERVED36), + NONE(STAT_MON), + NONE(RESERVED38), + NONE(FUSE), + + /* 40 */ + NONE(KFUSE), + PERIPHC_SBC1, /* SBCx = SPIx */ + PERIPHC_NOR, + NONE(RESERVED43), + PERIPHC_SBC2, + NONE(XIO), + PERIPHC_SBC3, + PERIPHC_I2C5, + + /* 48 */ + NONE(DSI), + NONE(RESERVED49), + PERIPHC_HSI, + PERIPHC_HDMI, + NONE(CSI), + NONE(RESERVED53), + PERIPHC_I2C2, + PERIPHC_UART3, + + /* 56 */ + NONE(MIPI_CAL), + PERIPHC_EMC, + NONE(USB2), + NONE(USB3), + NONE(RESERVED60), + PERIPHC_VDE, + NONE(BSEA), + NONE(BSEV), + + /* Upper word 95:64 */ + NONE(RESERVED64), + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_I2C3, + PERIPHC_SBC4, + PERIPHC_SDMMC3, + NONE(PCIE), + PERIPHC_OWR, + + /* 72 */ + NONE(AFI), + PERIPHC_CSITE, + NONE(PCIEXCLK), + NONE(AVPUCQ), + NONE(LA), + NONE(TRACECLKIN), + NONE(SOC_THERM), + NONE(DTV), + + /* 80 */ + NONE(RESERVED80), + PERIPHC_I2CSLOW, + NONE(DSIB), + PERIPHC_TSEC, + NONE(RESERVED84), + NONE(RESERVED85), + NONE(RESERVED86), + NONE(EMUCIF), + + /* 88 */ + NONE(RESERVED88), + NONE(XUSB_HOST), + NONE(RESERVED90), + PERIPHC_MSENC, + NONE(RESERVED92), + NONE(RESERVED93), + NONE(RESERVED94), + NONE(XUSB_DEV), + + /* V word: 31:0 */ + NONE(CPUG), + NONE(CPULP), + NONE(V_RESERVED2), + PERIPHC_MSELECT, + NONE(V_RESERVED4), + PERIPHC_I2S3, + PERIPHC_I2S4, + PERIPHC_I2C4, + + /* 104 */ + PERIPHC_SBC5, + PERIPHC_SBC6, + PERIPHC_AUDIO, + NONE(APBIF), + PERIPHC_DAM0, + PERIPHC_DAM1, + PERIPHC_DAM2, + PERIPHC_HDA2CODEC2X, + + /* 112 */ + NONE(ATOMICS), + NONE(V_RESERVED17), + NONE(V_RESERVED18), + NONE(V_RESERVED19), + NONE(V_RESERVED20), + NONE(V_RESERVED21), + NONE(V_RESERVED22), + PERIPHC_ACTMON, + + /* 120 */ + NONE(EXTPERIPH1), + NONE(EXTPERIPH2), + NONE(EXTPERIPH3), + NONE(OOB), + PERIPHC_SATA, + PERIPHC_HDA, + NONE(TZRAM), + NONE(SE), + + /* W word: 31:0 */ + NONE(HDA2HDMICODEC), + NONE(SATACOLD), + NONE(W_RESERVED2), + NONE(W_RESERVED3), + NONE(W_RESERVED4), + NONE(W_RESERVED5), + NONE(W_RESERVED6), + NONE(W_RESERVED7), + + /* 136 */ + NONE(CEC), + NONE(W_RESERVED9), + NONE(W_RESERVED10), + NONE(W_RESERVED11), + NONE(W_RESERVED12), + NONE(W_RESERVED13), + NONE(XUSB_PADCTL), + NONE(W_RESERVED15), + + /* 144 */ + NONE(W_RESERVED16), + NONE(W_RESERVED17), + NONE(W_RESERVED18), + NONE(W_RESERVED19), + NONE(W_RESERVED20), + NONE(ENTROPY), + NONE(DDS), + NONE(W_RESERVED23), + + /* 152 */ + NONE(DP2), + NONE(AMX0), + NONE(ADX0), + NONE(DVFS), + NONE(XUSB_SS), + NONE(W_RESERVED29), + NONE(W_RESERVED30), + NONE(W_RESERVED31), + + /* X word: 31:0 */ + NONE(SPARE), + NONE(X_RESERVED1), + NONE(X_RESERVED2), + NONE(X_RESERVED3), + NONE(CAM_MCLK), + NONE(CAM_MCLK2), + PERIPHC_I2C6, + NONE(X_RESERVED7), + + /* 168 */ + NONE(X_RESERVED8), + NONE(X_RESERVED9), + NONE(X_RESERVED10), + NONE(VIM2_CLK), + NONE(X_RESERVED12), + NONE(X_RESERVED13), + NONE(EMC_DLL), + NONE(X_RESERVED15), + + /* 176 */ + NONE(HDMI_AUDIO), + NONE(CLK72MHZ), + NONE(VIC), + NONE(X_RESERVED19), + NONE(ADX1), + NONE(DPAUX), + NONE(SOR0), + NONE(X_RESERVED23), + + /* 184 */ + NONE(GPU), + NONE(AMX1), + NONE(X_RESERVED26), + NONE(X_RESERVED27), + NONE(X_RESERVED28), + NONE(X_RESERVED29), + NONE(X_RESERVED30), + NONE(X_RESERVED31), +}; + +/* + * Get the oscillator frequency, from the corresponding hardware configuration + * field. Note that Tegra30+ support 3 new higher freqs, but we map back + * to the old T20 freqs. Support for the higher oscillators is TBD. + */ +enum clock_osc_freq clock_get_osc_freq(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + reg = readl(&clkrst->crc_osc_ctrl); + reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + + if (reg & 1) /* one of the newer freqs */ + printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg); + + return reg >> 2; /* Map to most common (T20) freqs */ +} + +/* Returns a pointer to the clock source register for a peripheral */ +u32 *get_periph_source_reg(enum periph_id periph_id) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + enum periphc_internal_id internal_id; + + /* Coresight is a special case */ + if (periph_id == PERIPH_ID_CSI) + return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; + + assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); + internal_id = periph_id_to_internal_id[periph_id]; + assert(internal_id != -1); + if (internal_id >= PERIPHC_VW_FIRST) { + internal_id -= PERIPHC_VW_FIRST; + return &clkrst->crc_clk_src_vw[internal_id]; + } else { + return &clkrst->crc_clk_src[internal_id]; + } +} + +/** + * Given a peripheral ID and the required source clock, this returns which + * value should be programmed into the source mux for that peripheral. + * + * There is special code here to handle the one source type with 5 sources. + * + * @param periph_id peripheral to start + * @param source PLL id of required parent clock + * @param mux_bits Set to number of bits in mux register: 2 or 4 + * @param divider_bits Set to number of divider bits (8 or 16) + * @return mux value (0-4, or -1 if not found) + */ +int get_periph_clock_source(enum periph_id periph_id, + enum clock_id parent, int *mux_bits, int *divider_bits) +{ + enum clock_type_id type; + enum periphc_internal_id internal_id; + int mux; + + assert(clock_periph_id_isvalid(periph_id)); + + internal_id = periph_id_to_internal_id[periph_id]; + assert(periphc_internal_id_isvalid(internal_id)); + + type = clock_periph_type[internal_id]; + assert(clock_type_id_isvalid(type)); + + *mux_bits = clock_source[type][CLOCK_MAX_MUX]; + + if (type == CLOCK_TYPE_PC2CC3M_T16) + *divider_bits = 16; + else + *divider_bits = 8; + + for (mux = 0; mux < CLOCK_MAX_MUX; mux++) + if (clock_source[type][mux] == parent) + return mux; + + /* if we get here, either us or the caller has made a mistake */ + printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, + parent); + return -1; +} + +void clock_set_enable(enum periph_id periph_id, int enable) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 *clk; + u32 reg; + + /* Enable/disable the clock to this peripheral */ + assert(clock_periph_id_isvalid(periph_id)); + if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) + clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; + else + clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; + reg = readl(clk); + if (enable) + reg |= PERIPH_MASK(periph_id); + else + reg &= ~PERIPH_MASK(periph_id); + writel(reg, clk); +} + +void reset_set_enable(enum periph_id periph_id, int enable) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 *reset; + u32 reg; + + /* Enable/disable reset to the peripheral */ + assert(clock_periph_id_isvalid(periph_id)); + if (periph_id < PERIPH_ID_VW_FIRST) + reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; + else + reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; + reg = readl(reset); + if (enable) + reg |= PERIPH_MASK(periph_id); + else + reg &= ~PERIPH_MASK(periph_id); + writel(reg, reset); +} + +#ifdef CONFIG_OF_CONTROL +/* + * Convert a device tree clock ID to our peripheral ID. They are mostly + * the same but we are very cautious so we check that a valid clock ID is + * provided. + * + * @param clk_id Clock ID according to tegra124 device tree binding + * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid + */ +enum periph_id clk_id_to_periph_id(int clk_id) +{ + if (clk_id > PERIPH_ID_COUNT) + return PERIPH_ID_NONE; + + switch (clk_id) { + case PERIPH_ID_RESERVED4: + case PERIPH_ID_RESERVED25: + case PERIPH_ID_RESERVED35: + case PERIPH_ID_RESERVED36: + case PERIPH_ID_RESERVED38: + case PERIPH_ID_RESERVED43: + case PERIPH_ID_RESERVED49: + case PERIPH_ID_RESERVED53: + case PERIPH_ID_RESERVED64: + case PERIPH_ID_RESERVED84: + case PERIPH_ID_RESERVED85: + case PERIPH_ID_RESERVED86: + case PERIPH_ID_RESERVED88: + case PERIPH_ID_RESERVED90: + case PERIPH_ID_RESERVED92: + case PERIPH_ID_RESERVED93: + case PERIPH_ID_RESERVED94: + case PERIPH_ID_V_RESERVED2: + case PERIPH_ID_V_RESERVED4: + case PERIPH_ID_V_RESERVED17: + case PERIPH_ID_V_RESERVED18: + case PERIPH_ID_V_RESERVED19: + case PERIPH_ID_V_RESERVED20: + case PERIPH_ID_V_RESERVED21: + case PERIPH_ID_V_RESERVED22: + case PERIPH_ID_W_RESERVED2: + case PERIPH_ID_W_RESERVED3: + case PERIPH_ID_W_RESERVED4: + case PERIPH_ID_W_RESERVED5: + case PERIPH_ID_W_RESERVED6: + case PERIPH_ID_W_RESERVED7: + case PERIPH_ID_W_RESERVED9: + case PERIPH_ID_W_RESERVED10: + case PERIPH_ID_W_RESERVED11: + case PERIPH_ID_W_RESERVED12: + case PERIPH_ID_W_RESERVED13: + case PERIPH_ID_W_RESERVED15: + case PERIPH_ID_W_RESERVED16: + case PERIPH_ID_W_RESERVED17: + case PERIPH_ID_W_RESERVED18: + case PERIPH_ID_W_RESERVED19: + case PERIPH_ID_W_RESERVED20: + case PERIPH_ID_W_RESERVED23: + case PERIPH_ID_W_RESERVED29: + case PERIPH_ID_W_RESERVED30: + case PERIPH_ID_W_RESERVED31: + return PERIPH_ID_NONE; + default: + return clk_id; + } +} +#endif /* CONFIG_OF_CONTROL */ + +void clock_early_init(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + tegra30_set_up_pllp(); + + /* + * PLLC output frequency set to 600Mhz + * PLLD output frequency set to 925Mhz + */ + switch (clock_get_osc_freq()) { + case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); + break; + + case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); + break; + + case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); + break; + case CLOCK_OSC_FREQ_19_2: + default: + /* + * These are not supported. It is too early to print a + * message and the UART likely won't work anyway due to the + * oscillator being wrong. + */ + break; + } + + /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */ + writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); + + /* PLLC_MISC: Set LOCK_ENABLE */ + writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc); + udelay(2); + + /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */ + writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); + udelay(2); +} + +void arch_timer_init(void) +{ + struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; + u32 freq, val; + + freq = clock_get_rate(CLOCK_ID_OSC); + debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + + /* ARM CNTFRQ */ + asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); + + /* Only Tegra114+ has the System Counter regs */ + debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); + writel(freq, &sysctr->cntfid0); + + val = readl(&sysctr->cntcr); + val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; + writel(val, &sysctr->cntcr); + debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); +} + +#define PLLE_SS_CNTL 0x68 +#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) +#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) +#define PLLE_SS_CNTL_SSCINVERT (1 << 15) +#define PLLE_SS_CNTL_SSCCENTER (1 << 14) +#define PLLE_SS_CNTL_SSCBYP (1 << 12) +#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) +#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) +#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) + +#define PLLE_BASE 0x0e8 +#define PLLE_BASE_ENABLE (1 << 30) +#define PLLE_BASE_LOCK_OVERRIDE (1 << 29) +#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) +#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) +#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) + +#define PLLE_MISC 0x0ec +#define PLLE_MISC_IDDQ_SWCTL (1 << 14) +#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) +#define PLLE_MISC_PTS (1 << 8) +#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4) +#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) + +#define PLLE_AUX 0x48c +#define PLLE_AUX_SEQ_ENABLE (1 << 24) +#define PLLE_AUX_ENABLE_SWCTL (1 << 4) + +int tegra_plle_enable(void) +{ + unsigned int m = 1, n = 200, cpcon = 13; + u32 value; + + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value &= ~PLLE_BASE_LOCK_OVERRIDE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); + value |= PLLE_AUX_ENABLE_SWCTL; + value &= ~PLLE_AUX_SEQ_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); + + udelay(1); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value |= PLLE_MISC_IDDQ_SWCTL; + value &= ~PLLE_MISC_IDDQ_OVERRIDE; + value |= PLLE_MISC_LOCK_ENABLE; + value |= PLLE_MISC_PTS; + value |= PLLE_MISC_VREG_BG_CTRL(3); + value |= PLLE_MISC_VREG_CTRL(2); + writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); + + udelay(5); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | + PLLE_SS_CNTL_BYPASS_SS; + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value &= ~PLLE_BASE_PLDIV_CML(0xf); + value &= ~PLLE_BASE_NDIV(0xff); + value &= ~PLLE_BASE_MDIV(0xff); + value |= PLLE_BASE_PLDIV_CML(cpcon); + value |= PLLE_BASE_NDIV(n); + value |= PLLE_BASE_MDIV(m); + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + udelay(1); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value |= PLLE_BASE_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + /* wait for lock */ + udelay(300); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value &= ~PLLE_SS_CNTL_SSCINVERT; + value &= ~PLLE_SS_CNTL_SSCCENTER; + + value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); + value &= ~PLLE_SS_CNTL_SSCINC(0xff); + value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); + + value |= PLLE_SS_CNTL_SSCINCINTR(0x20); + value |= PLLE_SS_CNTL_SSCINC(0x01); + value |= PLLE_SS_CNTL_SSCMAX(0x25); + + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value &= ~PLLE_SS_CNTL_SSCBYP; + value &= ~PLLE_SS_CNTL_BYPASS_SS; + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + udelay(1); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value &= ~PLLE_SS_CNTL_INTERP_RESET; + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + udelay(1); + + return 0; +} diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c new file mode 100644 index 0000000000..cced787e6b --- /dev/null +++ b/arch/arm/cpu/tegra124-common/funcmux.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 high-level function multiplexing */ + +#include +#include +#include +#include + +int funcmux_select(enum periph_id id, int config) +{ + int bad_config = config != FUNCMUX_DEFAULT; + + switch (id) { + case PERIPH_ID_UART4: + switch (config) { + case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */ + pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD); + + pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT); + + pinmux_tristate_disable(PMUX_PINGRP_PJ7); + pinmux_tristate_disable(PMUX_PINGRP_PB0); + pinmux_tristate_disable(PMUX_PINGRP_PB1); + pinmux_tristate_disable(PMUX_PINGRP_PK7); + break; + } + break; + + case PERIPH_ID_UART1: + switch (config) { + case FUNCMUX_UART1_KBC: + pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1, + PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2, + PMUX_FUNC_UARTA); + + pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT); + + pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1); + pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2); + break; + } + break; + + /* Add other periph IDs here as needed */ + + default: + debug("%s: invalid periph_id %d", __func__, id); + return -1; + } + + if (bad_config) { + debug("%s: invalid config %d for periph_id %d", __func__, + config, id); + return -1; + } + return 0; +} diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c new file mode 100644 index 0000000000..c6685eaae1 --- /dev/null +++ b/arch/arm/cpu/tegra124-common/pinmux.c @@ -0,0 +1,306 @@ +/* + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define PIN(pin, f0, f1, f2, f3) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + PMUX_FUNC_##f2, \ + PMUX_FUNC_##f3, \ + }, \ + } + +#define PIN_RESERVED {} + +static const struct pmux_pingrp_desc tegra124_pingroups[] = { + /* pin, f0, f1, f2, f3 */ + /* Offset 0x3000 */ + PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI), + PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI), + PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI), + PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI), + PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB), + PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB), + PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, RSVD4), + PIN(DAP3_SCLK_PP3, I2S2, SPI5, RSVD3, DISPLAYB), + PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4), + PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4), + PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4), + PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA), + PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA), + PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA), + PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA), + PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA), + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x3068 */ + PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4), + PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x3110 */ + PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4), + PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4), + PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x3164 */ + PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4), + PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4), + PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4), + PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4), + PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, SPI4), + PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, SPI4), + PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI), + PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, GMI), + PIN(PU0, OWR, UARTA, GMI, RSVD4), + PIN(PU1, RSVD1, UARTA, GMI, RSVD4), + PIN(PU2, RSVD1, UARTA, GMI, RSVD4), + PIN(PU3, PWM0, UARTA, GMI, DISPLAYB), + PIN(PU4, PWM1, UARTA, GMI, DISPLAYB), + PIN(PU5, PWM2, UARTA, GMI, DISPLAYB), + PIN(PU6, PWM3, UARTA, RSVD3, GMI), + PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4), + PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4), + PIN(DAP4_FS_PP4, I2S3, GMI, DTV, RSVD4), + PIN(DAP4_DIN_PP5, I2S3, GMI, RSVD3, RSVD4), + PIN(DAP4_DOUT_PP6, I2S3, GMI, DTV, RSVD4), + PIN(DAP4_SCLK_PP7, I2S3, GMI, RSVD3, RSVD4), + PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4), + PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4), + PIN(PC7, RSVD1, RSVD2, GMI, GMI_ALT), + PIN(PI5, SDMMC2, RSVD2, GMI, RSVD4), + PIN(PI7, RSVD1, TRACE, GMI, DTV), + PIN(PK0, RSVD1, SDMMC3, GMI, SOC), + PIN(PK1, SDMMC2, TRACE, GMI, RSVD4), + PIN(PJ0, RSVD1, RSVD2, GMI, USB), + PIN(PJ2, RSVD1, RSVD2, GMI, SOC), + PIN(PK3, SDMMC2, TRACE, GMI, CCLA), + PIN(PK4, SDMMC2, RSVD2, GMI, GMI_ALT), + PIN(PK2, RSVD1, RSVD2, GMI, RSVD4), + PIN(PI3, RSVD1, RSVD2, GMI, SPI4), + PIN(PI6, RSVD1, RSVD2, GMI, SDMMC2), + PIN(PG0, RSVD1, RSVD2, GMI, RSVD4), + PIN(PG1, RSVD1, RSVD2, GMI, RSVD4), + PIN(PG2, RSVD1, TRACE, GMI, RSVD4), + PIN(PG3, RSVD1, TRACE, GMI, RSVD4), + PIN(PG4, RSVD1, TMDS, GMI, SPI4), + PIN(PG5, RSVD1, RSVD2, GMI, SPI4), + PIN(PG6, RSVD1, RSVD2, GMI, SPI4), + PIN(PG7, RSVD1, RSVD2, GMI, SPI4), + PIN(PH0, PWM0, TRACE, GMI, DTV), + PIN(PH1, PWM1, TMDS, GMI, DISPLAYA), + PIN(PH2, PWM2, TMDS, GMI, CLDVFS), + PIN(PH3, PWM3, SPI4, GMI, CLDVFS), + PIN(PH4, SDMMC2, RSVD2, GMI, RSVD4), + PIN(PH5, SDMMC2, RSVD2, GMI, RSVD4), + PIN(PH6, SDMMC2, TRACE, GMI, DTV), + PIN(PH7, SDMMC2, TRACE, GMI, DTV), + PIN(PJ7, UARTD, RSVD2, GMI, GMI_ALT), + PIN(PB0, UARTD, RSVD2, GMI, RSVD4), + PIN(PB1, UARTD, RSVD2, GMI, RSVD4), + PIN(PK7, UARTD, RSVD2, GMI, RSVD4), + PIN(PI0, RSVD1, RSVD2, GMI, RSVD4), + PIN(PI1, RSVD1, RSVD2, GMI, RSVD4), + PIN(PI2, SDMMC2, TRACE, GMI, RSVD4), + PIN(PI4, SPI4, TRACE, GMI, DISPLAYA), + PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4), + PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4), + PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4), + PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4), + PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, RSVD3, RSVD4), + PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4), + PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4), + PIN_RESERVED, + /* Offset 0x3284 */ + PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC2), + PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC2), + PIN(PBB0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT), + PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC2), + PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC2), + PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC2), + PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC2), + PIN(PBB5, VGP5, DISPLAYA, RSVD3, SDMMC2), + PIN(PBB6, I2S4, RSVD2, DISPLAYB, SDMMC2), + PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC2), + PIN(PCC2, I2S4, RSVD2, SDMMC3, SDMMC2), + PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4), + PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4), + PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW3_PR3, KBC, DISPLAYA, SYS, DISPLAYB), + PIN(KB_ROW4_PR4, KBC, DISPLAYA, RSVD3, DISPLAYB), + PIN(KB_ROW5_PR5, KBC, DISPLAYA, RSVD3, DISPLAYB), + PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB), + PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA), + PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA), + PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA), + PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA), + PIN(KB_ROW11_PS3, KBC, RSVD2, RSVD3, IRDA), + PIN(KB_ROW12_PS4, KBC, RSVD2, RSVD3, IRDA), + PIN(KB_ROW13_PS5, KBC, RSVD2, SPI2, RSVD4), + PIN(KB_ROW14_PS6, KBC, RSVD2, SPI2, RSVD4), + PIN(KB_ROW15_PS7, KBC, SOC, RSVD3, RSVD4), + PIN(KB_COL0_PQ0, KBC, RSVD2, SPI2, RSVD4), + PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, RSVD4), + PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4), + PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA), + PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA), + PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC3, RSVD4), + PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, UARTD), + PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, UARTD), + PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4), + PIN_RESERVED, + /* Offset 0x3324 */ + PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4), + PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4), + PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4), + PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4), + PIN(OWR, OWR, RSVD2, RSVD3, RSVD4), + PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4), + PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4), + PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SATA), + PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4), + PIN(DAP_MCLK1_REQ_PEE2, DAP, DAP1, SATA, RSVD4), + PIN(DAP_MCLK1_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4), + PIN(SPDIF_IN_PK6, SPDIF, RSVD2, RSVD3, I2C3), + PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, I2C3), + PIN(DAP2_FS_PA2, I2S1, HDA, GMI, RSVD4), + PIN(DAP2_DIN_PA4, I2S1, HDA, GMI, RSVD4), + PIN(DAP2_DOUT_PA5, I2S1, HDA, GMI, RSVD4), + PIN(DAP2_SCLK_PA3, I2S1, HDA, GMI, RSVD4), + PIN(DVFS_PWM_PX0, SPI6, CLDVFS, GMI, RSVD4), + PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, GMI, RSVD4), + PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, GMI, RSVD4), + PIN(DVFS_CLK_PX2, SPI6, CLDVFS, GMI, RSVD4), + PIN(GPIO_X4_AUD_PX4, GMI, SPI1, SPI2, DAP2), + PIN(GPIO_X5_AUD_PX5, GMI, SPI1, SPI2, RSVD4), + PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, GMI), + PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4), + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x3390 */ + PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3), + PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3), + PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3), + PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3), + PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3), + PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3), + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x33bc */ + PIN(PEX_L0_RST_N_PDD1, PE0, RSVD2, RSVD3, RSVD4), + PIN(PEX_L0_CLKREQ_N_PDD2, PE0, RSVD2, RSVD3, RSVD4), + PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, + /* Offset 0x33cc */ + PIN(PEX_L1_RST_N_PDD5, PE1, RSVD2, RSVD3, RSVD4), + PIN(PEX_L1_CLKREQ_N_PDD6, PE1, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x33e0 */ + PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4), + PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA), + PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4), + PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1), + PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1), + PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4), + PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4), + PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4), + PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4), + PIN(GMI_CLK_LB, SDMMC2, RSVD2, GMI, RSVD4), + PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N), + PIN(KB_ROW16_PT0, KBC, RSVD2, RSVD3, UARTC), + PIN(KB_ROW17_PT1, KBC, RSVD2, RSVD3, UARTC), + PIN(USB_VBUS_EN2_PFF1, USB, RSVD2, RSVD3, RSVD4), + PIN(PFF2, SATA, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + /* Offset 0x3430 */ + PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4), +}; +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups; diff --git a/arch/arm/cpu/tegra124-common/xusb-padctl.c b/arch/arm/cpu/tegra124-common/xusb-padctl.c new file mode 100644 index 0000000000..43af883f2c --- /dev/null +++ b/arch/arm/cpu/tegra124-common/xusb-padctl.c @@ -0,0 +1,716 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt + +#include +#include +#include +#include + +#include + +#include +#include + +#include + +#define XUSB_PADCTL_ELPG_PROGRAM 0x01c +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) + +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) + +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) + +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) + +#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 +#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) +#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) + +enum tegra124_function { + TEGRA124_FUNC_SNPS, + TEGRA124_FUNC_XUSB, + TEGRA124_FUNC_UART, + TEGRA124_FUNC_PCIE, + TEGRA124_FUNC_USB3, + TEGRA124_FUNC_SATA, + TEGRA124_FUNC_RSVD, +}; + +static const char *const tegra124_functions[] = { + "snps", + "xusb", + "uart", + "pcie", + "usb3", + "sata", + "rsvd", +}; + +static const unsigned int tegra124_otg_functions[] = { + TEGRA124_FUNC_SNPS, + TEGRA124_FUNC_XUSB, + TEGRA124_FUNC_UART, + TEGRA124_FUNC_RSVD, +}; + +static const unsigned int tegra124_usb_functions[] = { + TEGRA124_FUNC_SNPS, + TEGRA124_FUNC_XUSB, +}; + +static const unsigned int tegra124_pci_functions[] = { + TEGRA124_FUNC_PCIE, + TEGRA124_FUNC_USB3, + TEGRA124_FUNC_SATA, + TEGRA124_FUNC_RSVD, +}; + +struct tegra_xusb_padctl_lane { + const char *name; + + unsigned int offset; + unsigned int shift; + unsigned int mask; + unsigned int iddq; + + const unsigned int *funcs; + unsigned int num_funcs; +}; + +#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ + { \ + .name = _name, \ + .offset = _offset, \ + .shift = _shift, \ + .mask = _mask, \ + .iddq = _iddq, \ + .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \ + .funcs = tegra124_##_funcs##_functions, \ + } + +static const struct tegra_xusb_padctl_lane tegra124_lanes[] = { + TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg), + TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg), + TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg), + TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb), + TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), + TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), + TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci), + TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci), + TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci), + TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci), + TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci), + TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci), +}; + +struct tegra_xusb_phy_ops { + int (*prepare)(struct tegra_xusb_phy *phy); + int (*enable)(struct tegra_xusb_phy *phy); + int (*disable)(struct tegra_xusb_phy *phy); + int (*unprepare)(struct tegra_xusb_phy *phy); +}; + +struct tegra_xusb_phy { + const struct tegra_xusb_phy_ops *ops; + + struct tegra_xusb_padctl *padctl; +}; + +struct tegra_xusb_padctl_pin { + const struct tegra_xusb_padctl_lane *lane; + + unsigned int func; + int iddq; +}; + +#define MAX_GROUPS 3 +#define MAX_PINS 6 + +struct tegra_xusb_padctl_group { + const char *name; + + const char *pins[MAX_PINS]; + unsigned int num_pins; + + const char *func; + int iddq; +}; + +struct tegra_xusb_padctl_config { + const char *name; + + struct tegra_xusb_padctl_group groups[MAX_GROUPS]; + unsigned int num_groups; +}; + +struct tegra_xusb_padctl { + struct fdt_resource regs; + + unsigned int enable; + + struct tegra_xusb_phy phys[2]; + + const struct tegra_xusb_padctl_lane *lanes; + unsigned int num_lanes; + + const char *const *functions; + unsigned int num_functions; + + struct tegra_xusb_padctl_config config; +}; + +static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, + unsigned long offset) +{ + return readl(padctl->regs.start + offset); +} + +static inline void padctl_writel(struct tegra_xusb_padctl *padctl, + u32 value, unsigned long offset) +{ + writel(value, padctl->regs.start + offset); +} + +static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) +{ + u32 value; + + if (padctl->enable++ > 0) + return 0; + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + udelay(100); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + udelay(100); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + return 0; +} + +static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) +{ + u32 value; + + if (padctl->enable == 0) { + error("tegra-xusb-padctl: unbalanced enable/disable"); + return 0; + } + + if (--padctl->enable > 0) + return 0; + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + udelay(100); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + udelay(100); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + return 0; +} + +static int phy_prepare(struct tegra_xusb_phy *phy) +{ + return tegra_xusb_padctl_enable(phy->padctl); +} + +static int phy_unprepare(struct tegra_xusb_phy *phy) +{ + return tegra_xusb_padctl_disable(phy->padctl); +} + +static int pcie_phy_enable(struct tegra_xusb_phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy->padctl; + int err = -ETIMEDOUT; + unsigned long start; + u32 value; + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); + value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN | + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN | + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + + start = get_timer(0); + + while (get_timer(start) < 50) { + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) { + err = 0; + break; + } + } + + return err; +} + +static int pcie_phy_disable(struct tegra_xusb_phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy->padctl; + u32 value; + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); + + return 0; +} + +static int sata_phy_enable(struct tegra_xusb_phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy->padctl; + int err = -ETIMEDOUT; + unsigned long start; + u32 value; + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; + value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; + value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + start = get_timer(0); + + while (get_timer(start) < 50) { + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) { + err = 0; + break; + } + } + + return err; +} + +static int sata_phy_disable(struct tegra_xusb_phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy->padctl; + u32 value; + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; + value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); + value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; + value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); + + return 0; +} + +static const struct tegra_xusb_phy_ops pcie_phy_ops = { + .prepare = phy_prepare, + .enable = pcie_phy_enable, + .disable = pcie_phy_disable, + .unprepare = phy_unprepare, +}; + +static const struct tegra_xusb_phy_ops sata_phy_ops = { + .prepare = phy_prepare, + .enable = sata_phy_enable, + .disable = sata_phy_disable, + .unprepare = phy_unprepare, +}; + +static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { + .phys = { + [0] = { + .ops = &pcie_phy_ops, + }, + [1] = { + .ops = &sata_phy_ops, + }, + }, +}; + +static const struct tegra_xusb_padctl_lane * +tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name) +{ + unsigned int i; + + for (i = 0; i < padctl->num_lanes; i++) + if (strcmp(name, padctl->lanes[i].name) == 0) + return &padctl->lanes[i]; + + return NULL; +} + +static int +tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, + struct tegra_xusb_padctl_group *group, + const void *fdt, int node) +{ + unsigned int i; + int len, err; + + group->name = fdt_get_name(fdt, node, &len); + + len = fdt_count_strings(fdt, node, "nvidia,lanes"); + if (len < 0) { + error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" property"); + return -EINVAL; + } + + group->num_pins = len; + + for (i = 0; i < group->num_pins; i++) { + err = fdt_get_string_index(fdt, node, "nvidia,lanes", i, + &group->pins[i]); + if (err < 0) { + error("tegra-xusb-padctl: failed to read string from \"nvidia,lanes\" property"); + return -EINVAL; + } + } + + group->num_pins = len; + + err = fdt_get_string(fdt, node, "nvidia,function", &group->func); + if (err < 0) { + error("tegra-xusb-padctl: failed to parse \"nvidia,func\" property"); + return -EINVAL; + } + + group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1); + + return 0; +} + +static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl, + const char *name) +{ + unsigned int i; + + for (i = 0; i < padctl->num_functions; i++) + if (strcmp(name, padctl->functions[i]) == 0) + return i; + + return -ENOENT; +} + +static int +tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl, + const struct tegra_xusb_padctl_lane *lane, + const char *name) +{ + unsigned int i; + int func; + + func = tegra_xusb_padctl_find_function(padctl, name); + if (func < 0) + return func; + + for (i = 0; i < lane->num_funcs; i++) + if (lane->funcs[i] == func) + return i; + + return -ENOENT; +} + +static int +tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl, + const struct tegra_xusb_padctl_group *group) +{ + unsigned int i; + + for (i = 0; i < group->num_pins; i++) { + const struct tegra_xusb_padctl_lane *lane; + unsigned int func; + u32 value; + + lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); + if (!lane) { + error("tegra-xusb-padctl: no lane for pin %s", + group->pins[i]); + continue; + } + + func = tegra_xusb_padctl_lane_find_function(padctl, lane, + group->func); + if (func < 0) { + error("tegra-xusb-padctl: function %s invalid for lane %s: %d", + group->func, lane->name, func); + continue; + } + + value = padctl_readl(padctl, lane->offset); + + /* set pin function */ + value &= ~(lane->mask << lane->shift); + value |= func << lane->shift; + + /* + * Set IDDQ if supported on the lane and specified in the + * configuration. + */ + if (lane->iddq > 0 && group->iddq >= 0) { + if (group->iddq != 0) + value &= ~(1 << lane->iddq); + else + value |= 1 << lane->iddq; + } + + padctl_writel(padctl, value, lane->offset); + } + + return 0; +} + +static int +tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, + struct tegra_xusb_padctl_config *config) +{ + unsigned int i; + + for (i = 0; i < config->num_groups; i++) { + const struct tegra_xusb_padctl_group *group; + int err; + + group = &config->groups[i]; + + err = tegra_xusb_padctl_group_apply(padctl, group); + if (err < 0) { + error("tegra-xusb-padctl: failed to apply group %s: %d", + group->name, err); + continue; + } + } + + return 0; +} + +static int +tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, + struct tegra_xusb_padctl_config *config, + const void *fdt, int node) +{ + int subnode; + + config->name = fdt_get_name(fdt, node, NULL); + + fdt_for_each_subnode(fdt, subnode, node) { + struct tegra_xusb_padctl_group *group; + int err; + + group = &config->groups[config->num_groups]; + + err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt, + subnode); + if (err < 0) { + error("tegra-xusb-padctl: failed to parse group %s", + group->name); + return err; + } + + config->num_groups++; + } + + return 0; +} + +static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, + const void *fdt, int node) +{ + int subnode, err; + + err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); + if (err < 0) { + error("tegra-xusb-padctl: registers not found"); + return err; + } + + fdt_for_each_subnode(fdt, subnode, node) { + struct tegra_xusb_padctl_config *config = &padctl->config; + + err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt, + subnode); + if (err < 0) { + error("tegra-xusb-padctl: failed to parse entry %s: %d", + config->name, err); + continue; + } + } + + return 0; +} + +static int process_nodes(const void *fdt, int nodes[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) { + enum fdt_compat_id id; + int err; + + if (!fdtdec_get_is_enabled(fdt, nodes[i])) + continue; + + id = fdtdec_lookup(fdt, nodes[i]); + switch (id) { + case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL: + break; + + default: + error("tegra-xusb-padctl: unsupported compatible: %s", + fdtdec_get_compatible(id)); + continue; + } + + padctl->num_lanes = ARRAY_SIZE(tegra124_lanes); + padctl->lanes = tegra124_lanes; + + padctl->num_functions = ARRAY_SIZE(tegra124_functions); + padctl->functions = tegra124_functions; + + err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]); + if (err < 0) { + error("tegra-xusb-padctl: failed to parse DT: %d", + err); + continue; + } + + /* deassert XUSB padctl reset */ + reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0); + + err = tegra_xusb_padctl_config_apply(padctl, &padctl->config); + if (err < 0) { + error("tegra-xusb-padctl: failed to apply pinmux: %d", + err); + continue; + } + + /* only a single instance is supported */ + break; + } + + return 0; +} + +struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type) +{ + struct tegra_xusb_phy *phy = NULL; + + switch (type) { + case TEGRA_XUSB_PADCTL_PCIE: + phy = &padctl->phys[0]; + phy->padctl = padctl; + break; + + case TEGRA_XUSB_PADCTL_SATA: + phy = &padctl->phys[1]; + phy->padctl = padctl; + break; + } + + return phy; +} + +int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->prepare) + return phy->ops->prepare(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->enable) + return phy->ops->enable(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->disable) + return phy->ops->disable(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->unprepare) + return phy->ops->unprepare(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +void tegra_xusb_padctl_init(const void *fdt) +{ + int count, nodes[1]; + + count = fdtdec_find_aliases_for_id(fdt, "padctl", + COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, + nodes, ARRAY_SIZE(nodes)); + if (process_nodes(fdt, nodes, count)) + return; +} diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 175387fd65..0e4b3fc1dd 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -7,32 +7,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t - -LIB = $(obj)lib$(SOC)-common.o - -COBJS-y += clock.o funcmux.o pinmux.o -COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o -COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o -COBJS-$(CONFIG_TEGRA_PMU) += pmu.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +CFLAGS_warmboot_avp.o += -march=armv4t -######################################################################### +obj-y += clock.o funcmux.o pinmux.o +obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o +obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +obj-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c index 34124f9bba..7b9e10cd93 100644 --- a/arch/arm/cpu/tegra20-common/clock.c +++ b/arch/arm/cpu/tegra20-common/clock.c @@ -7,6 +7,7 @@ /* Tegra20 Clock control functions */ #include +#include #include #include #include @@ -332,7 +333,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 0x48 */ NONE(AFI), NONE(CORESIGHT), - NONE(RESERVED74), + NONE(PCIEXCLK), NONE(AVPUCQ), NONE(RESERVED76), NONE(RESERVED77), @@ -412,9 +413,9 @@ int get_periph_clock_source(enum periph_id periph_id, * with its 16-bit divisor */ if (type == CLOCK_TYPE_PCXTS) - *mux_bits = 4; + *mux_bits = MASK_BITS_31_28; else - *mux_bits = 2; + *mux_bits = MASK_BITS_31_30; if (type == CLOCK_TYPE_PCMT16) *divider_bits = 16; else @@ -494,7 +495,7 @@ enum periph_id clk_id_to_periph_id(int clk_id) case PERIPH_ID_RESERVED30: case PERIPH_ID_RESERVED35: case PERIPH_ID_RESERVED56: - case PERIPH_ID_RESERVED74: + case PERIPH_ID_PCIEXCLK: case PERIPH_ID_RESERVED76: case PERIPH_ID_RESERVED77: case PERIPH_ID_RESERVED78: @@ -548,3 +549,139 @@ void clock_early_init(void) void arch_timer_init(void) { } + +#define PMC_SATA_PWRGT 0x1ac +#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5) +#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4) + +#define PLLE_SS_CNTL 0x68 +#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24) +#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) +#define PLLE_SS_CNTL_SSCBYP (1 << 12) +#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) +#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) +#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) + +#define PLLE_BASE 0x0e8 +#define PLLE_BASE_ENABLE_CML (1 << 31) +#define PLLE_BASE_ENABLE (1 << 30) +#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) +#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16) +#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) +#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) + +#define PLLE_MISC 0x0ec +#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) +#define PLLE_MISC_PLL_READY (1 << 15) +#define PLLE_MISC_LOCK (1 << 11) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) +#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2) + +static int tegra_plle_train(void) +{ + unsigned int timeout = 2000; + unsigned long value; + + value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); + value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; + writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); + + value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); + value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; + writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); + + value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); + value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; + writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); + + do { + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + if (value & PLLE_MISC_PLL_READY) + break; + + udelay(100); + } while (--timeout); + + if (timeout == 0) { + error("timeout waiting for PLLE to become ready"); + return -ETIMEDOUT; + } + + return 0; +} + +int tegra_plle_enable(void) +{ + unsigned int timeout = 1000; + u32 value; + int err; + + /* disable PLLE clock */ + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value &= ~PLLE_BASE_ENABLE_CML; + value &= ~PLLE_BASE_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + /* clear lock enable and setup field */ + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value &= ~PLLE_MISC_LOCK_ENABLE; + value &= ~PLLE_MISC_SETUP_BASE(0xffff); + value &= ~PLLE_MISC_SETUP_EXT(0x3); + writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + if ((value & PLLE_MISC_PLL_READY) == 0) { + err = tegra_plle_train(); + if (err < 0) { + error("failed to train PLLE: %d", err); + return err; + } + } + + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value |= PLLE_MISC_SETUP_BASE(0x7); + value |= PLLE_MISC_LOCK_ENABLE; + value |= PLLE_MISC_SETUP_EXT(0); + writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | + PLLE_SS_CNTL_BYPASS_SS; + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + do { + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + if (value & PLLE_MISC_LOCK) + break; + + udelay(2); + } while (--timeout); + + if (timeout == 0) { + error("timeout waiting for PLLE to lock"); + return -ETIMEDOUT; + } + + udelay(50); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f); + value |= PLLE_SS_CNTL_SSCINCINTRV(0x18); + + value &= ~PLLE_SS_CNTL_SSCINC(0xff); + value |= PLLE_SS_CNTL_SSCINC(0x01); + + value &= ~PLLE_SS_CNTL_SSCBYP; + value &= ~PLLE_SS_CNTL_INTERP_RESET; + value &= ~PLLE_SS_CNTL_BYPASS_SS; + + value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); + value |= PLLE_SS_CNTL_SSCMAX(0x24); + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + return 0; +} diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c index 8209f7661a..ec95d7ceb1 100644 --- a/arch/arm/cpu/tegra20-common/crypto.c +++ b/arch/arm/cpu/tegra20-common/crypto.c @@ -19,74 +19,6 @@ enum security_op { SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */ }; -static void debug_print_vector(char *name, u32 num_bytes, u8 *data) -{ - u32 i; - - debug("%s [%d] @0x%08x", name, num_bytes, (u32)data); - for (i = 0; i < num_bytes; i++) { - if (i % 16 == 0) - debug(" = "); - debug("%02x", data[i]); - if ((i+1) % 16 != 0) - debug(" "); - } - debug("\n"); -} - -/** - * Apply chain data to the destination using EOR - * - * Each array is of length AES_AES_KEY_LENGTH. - * - * \param cbc_chain_data Chain data - * \param src Source data - * \param dst Destination data, which is modified here - */ -static void apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst) -{ - int i; - - for (i = 0; i < 16; i++) - *dst++ = *src++ ^ *cbc_chain_data++; -} - -/** - * Encrypt some data with AES. - * - * \param key_schedule Expanded key to use - * \param src Source data to encrypt - * \param dst Destination buffer - * \param num_aes_blocks Number of AES blocks to encrypt - */ -static void encrypt_object(u8 *key_schedule, u8 *src, u8 *dst, - u32 num_aes_blocks) -{ - u8 tmp_data[AES_KEY_LENGTH]; - u8 *cbc_chain_data; - u32 i; - - cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ - - for (i = 0; i < num_aes_blocks; i++) { - debug("encrypt_object: block %d of %d\n", i, num_aes_blocks); - debug_print_vector("AES Src", AES_KEY_LENGTH, src); - - /* Apply the chain data */ - apply_cbc_chain_data(cbc_chain_data, src, tmp_data); - debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data); - - /* encrypt the AES block */ - aes_encrypt(tmp_data, key_schedule, dst); - debug_print_vector("AES Dst", AES_KEY_LENGTH, dst); - - /* Update pointers for next loop. */ - cbc_chain_data = dst; - src += AES_KEY_LENGTH; - dst += AES_KEY_LENGTH; - } -} - /** * Shift a vector left by one bit * @@ -129,39 +61,31 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, for (i = 0; i < AES_KEY_LENGTH; i++) tmp_data[i] = 0; - encrypt_object(key_schedule, tmp_data, left, 1); - debug_print_vector("AES(key, nonce)", AES_KEY_LENGTH, left); + aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1); left_shift_vector(left, k1, sizeof(left)); - debug_print_vector("L", AES_KEY_LENGTH, left); if ((left[0] >> 7) != 0) /* get MSB of L */ k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB; - debug_print_vector("K1", AES_KEY_LENGTH, k1); /* compute the AES-CMAC value */ for (i = 0; i < num_aes_blocks; i++) { /* Apply the chain data */ - apply_cbc_chain_data(cbc_chain_data, src, tmp_data); + aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data); /* for the final block, XOR K1 into the IV */ if (i == num_aes_blocks - 1) - apply_cbc_chain_data(tmp_data, k1, tmp_data); + aes_apply_cbc_chain_data(tmp_data, k1, tmp_data); /* encrypt the AES block */ aes_encrypt(tmp_data, key_schedule, dst); debug("sign_obj: block %d of %d\n", i, num_aes_blocks); - debug_print_vector("AES-CMAC Src", AES_KEY_LENGTH, src); - debug_print_vector("AES-CMAC Xor", AES_KEY_LENGTH, tmp_data); - debug_print_vector("AES-CMAC Dst", AES_KEY_LENGTH, dst); /* Update pointers for next loop. */ cbc_chain_data = dst; src += AES_KEY_LENGTH; } - - debug_print_vector("AES-CMAC Hash", AES_KEY_LENGTH, dst); } /** @@ -180,7 +104,6 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, u8 key_schedule[AES_EXPAND_KEY_LENGTH]; debug("encrypt_and_sign: length = %d\n", length); - debug_print_vector("AES key", AES_KEY_LENGTH, key); /* * The only need for a key is for signing/checksum purposes, so @@ -193,7 +116,7 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, if (oper & SECURITY_ENCRYPT) { /* Perform this in place, resulting in src being encrypted. */ debug("encrypt_and_sign: begin encryption\n"); - encrypt_object(key_schedule, src, src, num_aes_blocks); + aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks); debug("encrypt_and_sign: end encryption\n"); } diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c index 934e395955..ed2462ab0f 100644 --- a/arch/arm/cpu/tegra20-common/emc.c +++ b/arch/arm/cpu/tegra20-common/emc.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c index 1931908199..0df4a0738d 100644 --- a/arch/arm/cpu/tegra20-common/funcmux.c +++ b/arch/arm/cpu/tegra20-common/funcmux.c @@ -14,9 +14,9 @@ * The PINMUX macro is used to set up pinmux tables. */ #define PINMUX(grp, mux, pupd, tri) \ - {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri} + {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri} -static const struct pingroup_config disp1_default[] = { +static const struct pmux_pingrp_config disp1_default[] = { PINMUX(LDI, DISPA, NORMAL, NORMAL), PINMUX(LHP0, DISPA, NORMAL, NORMAL), PINMUX(LHP1, DISPA, NORMAL, NORMAL), @@ -42,26 +42,26 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_UART1: switch (config) { case FUNCMUX_UART1_IRRX_IRTX: - pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PINGRP_IRRX); - pinmux_tristate_disable(PINGRP_IRTX); + pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_IRRX); + pinmux_tristate_disable(PMUX_PINGRP_IRTX); break; case FUNCMUX_UART1_UAA_UAB: - pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PINGRP_UAA); - pinmux_tristate_disable(PINGRP_UAB); + pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_UAA); + pinmux_tristate_disable(PMUX_PINGRP_UAB); bad_config = 0; break; case FUNCMUX_UART1_GPU: - pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PINGRP_GPU); + pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_GPU); bad_config = 0; break; case FUNCMUX_UART1_SDIO1: - pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PINGRP_SDIO1); + pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_SDIO1); bad_config = 0; break; } @@ -77,53 +77,53 @@ int funcmux_select(enum periph_id id, int config) * state the group to avoid driving any signal onto it * until we know what's connected. */ - pinmux_tristate_enable(PINGRP_SDB); - pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3); + pinmux_tristate_enable(PMUX_PINGRP_SDB); + pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); } break; case PERIPH_ID_UART2: if (config == FUNCMUX_UART2_UAD) { - pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB); - pinmux_tristate_disable(PINGRP_UAD); + pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB); + pinmux_tristate_disable(PMUX_PINGRP_UAD); } break; case PERIPH_ID_UART4: if (config == FUNCMUX_UART4_GMC) { - pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); - pinmux_tristate_disable(PINGRP_GMC); + pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD); + pinmux_tristate_disable(PMUX_PINGRP_GMC); } break; case PERIPH_ID_DVC_I2C: /* there is only one selection, pinmux_config is ignored */ if (config == FUNCMUX_DVC_I2CP) { - pinmux_set_func(PINGRP_I2CP, PMUX_FUNC_I2C); - pinmux_tristate_disable(PINGRP_I2CP); + pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C); + pinmux_tristate_disable(PMUX_PINGRP_I2CP); } break; case PERIPH_ID_I2C1: /* support pinmux_config of 0 for now, */ if (config == FUNCMUX_I2C1_RM) { - pinmux_set_func(PINGRP_RM, PMUX_FUNC_I2C); - pinmux_tristate_disable(PINGRP_RM); + pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C); + pinmux_tristate_disable(PMUX_PINGRP_RM); } break; case PERIPH_ID_I2C2: /* I2C2 */ switch (config) { case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */ - pinmux_set_func(PINGRP_DDC, PMUX_FUNC_I2C2); + pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2); /* PTA to HDMI */ - pinmux_set_func(PINGRP_PTA, PMUX_FUNC_HDMI); - pinmux_tristate_disable(PINGRP_DDC); + pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI); + pinmux_tristate_disable(PMUX_PINGRP_DDC); break; case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */ - pinmux_set_func(PINGRP_PTA, PMUX_FUNC_I2C2); + pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2); /* set DDC_SEL to RSVDx (RSVD2 works for now) */ - pinmux_set_func(PINGRP_DDC, PMUX_FUNC_RSVD2); - pinmux_tristate_disable(PINGRP_PTA); + pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2); + pinmux_tristate_disable(PMUX_PINGRP_PTA); bad_config = 0; break; } @@ -131,50 +131,50 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_I2C3: /* I2C3 */ /* support pinmux_config of 0 for now */ if (config == FUNCMUX_I2C3_DTF) { - pinmux_set_func(PINGRP_DTF, PMUX_FUNC_I2C3); - pinmux_tristate_disable(PINGRP_DTF); + pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3); + pinmux_tristate_disable(PMUX_PINGRP_DTF); } break; case PERIPH_ID_SDMMC1: if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) { - pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PINGRP_SDIO1); + pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); + pinmux_tristate_disable(PMUX_PINGRP_SDIO1); } break; case PERIPH_ID_SDMMC2: if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) { - pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2); - pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2); + pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2); + pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2); - pinmux_tristate_disable(PINGRP_DTA); - pinmux_tristate_disable(PINGRP_DTD); + pinmux_tristate_disable(PMUX_PINGRP_DTA); + pinmux_tristate_disable(PMUX_PINGRP_DTD); } break; case PERIPH_ID_SDMMC3: switch (config) { case FUNCMUX_SDMMC3_SDB_SLXA_8BIT: - pinmux_set_func(PINGRP_SLXA, PMUX_FUNC_SDIO3); - pinmux_set_func(PINGRP_SLXC, PMUX_FUNC_SDIO3); - pinmux_set_func(PINGRP_SLXD, PMUX_FUNC_SDIO3); - pinmux_set_func(PINGRP_SLXK, PMUX_FUNC_SDIO3); - - pinmux_tristate_disable(PINGRP_SLXA); - pinmux_tristate_disable(PINGRP_SLXC); - pinmux_tristate_disable(PINGRP_SLXD); - pinmux_tristate_disable(PINGRP_SLXK); + pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3); + + pinmux_tristate_disable(PMUX_PINGRP_SLXA); + pinmux_tristate_disable(PMUX_PINGRP_SLXC); + pinmux_tristate_disable(PMUX_PINGRP_SLXD); + pinmux_tristate_disable(PMUX_PINGRP_SLXK); /* fall through */ case FUNCMUX_SDMMC3_SDB_4BIT: - pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3); - pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3); - pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3); + pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3); - pinmux_tristate_disable(PINGRP_SDB); - pinmux_tristate_disable(PINGRP_SDC); - pinmux_tristate_disable(PINGRP_SDD); + pinmux_tristate_disable(PMUX_PINGRP_SDB); + pinmux_tristate_disable(PMUX_PINGRP_SDC); + pinmux_tristate_disable(PMUX_PINGRP_SDD); bad_config = 0; break; } @@ -183,24 +183,24 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_SDMMC4: switch (config) { case FUNCMUX_SDMMC4_ATC_ATD_8BIT: - pinmux_set_func(PINGRP_ATC, PMUX_FUNC_SDIO4); - pinmux_set_func(PINGRP_ATD, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4); - pinmux_tristate_disable(PINGRP_ATC); - pinmux_tristate_disable(PINGRP_ATD); + pinmux_tristate_disable(PMUX_PINGRP_ATC); + pinmux_tristate_disable(PMUX_PINGRP_ATD); break; case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT: - pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); - pinmux_tristate_disable(PINGRP_GME); + pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); + pinmux_tristate_disable(PMUX_PINGRP_GME); /* fall through */ case FUNCMUX_SDMMC4_ATB_GMA_4_BIT: - pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); - pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); - pinmux_tristate_disable(PINGRP_ATB); - pinmux_tristate_disable(PINGRP_GMA); + pinmux_tristate_disable(PMUX_PINGRP_ATB); + pinmux_tristate_disable(PMUX_PINGRP_GMA); bad_config = 0; break; } @@ -208,9 +208,10 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_KBC: if (config == FUNCMUX_DEFAULT) { - enum pmux_pingrp grp[] = {PINGRP_KBCA, PINGRP_KBCB, - PINGRP_KBCC, PINGRP_KBCD, PINGRP_KBCE, - PINGRP_KBCF}; + enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA, + PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC, + PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE, + PMUX_PINGRP_KBCF}; int i; for (i = 0; i < ARRAY_SIZE(grp); i++) { @@ -223,44 +224,44 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_USB2: if (config == FUNCMUX_USB2_ULPI) { - pinmux_set_func(PINGRP_UAA, PMUX_FUNC_ULPI); - pinmux_set_func(PINGRP_UAB, PMUX_FUNC_ULPI); - pinmux_set_func(PINGRP_UDA, PMUX_FUNC_ULPI); + pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI); + pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI); + pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI); - pinmux_tristate_disable(PINGRP_UAA); - pinmux_tristate_disable(PINGRP_UAB); - pinmux_tristate_disable(PINGRP_UDA); + pinmux_tristate_disable(PMUX_PINGRP_UAA); + pinmux_tristate_disable(PMUX_PINGRP_UAB); + pinmux_tristate_disable(PMUX_PINGRP_UDA); } break; case PERIPH_ID_SPI1: if (config == FUNCMUX_SPI1_GMC_GMD) { - pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); - pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); + pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH); + pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH); - pinmux_tristate_disable(PINGRP_GMC); - pinmux_tristate_disable(PINGRP_GMD); + pinmux_tristate_disable(PMUX_PINGRP_GMC); + pinmux_tristate_disable(PMUX_PINGRP_GMD); } break; case PERIPH_ID_NDFLASH: switch (config) { case FUNCMUX_NDFLASH_ATC: - pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND); - pinmux_tristate_disable(PINGRP_ATC); + pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND); + pinmux_tristate_disable(PMUX_PINGRP_ATC); break; case FUNCMUX_NDFLASH_KBC_8_BIT: - pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND); - pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND); - pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND); - pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND); - pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND); - - pinmux_tristate_disable(PINGRP_KBCA); - pinmux_tristate_disable(PINGRP_KBCC); - pinmux_tristate_disable(PINGRP_KBCD); - pinmux_tristate_disable(PINGRP_KBCE); - pinmux_tristate_disable(PINGRP_KBCF); + pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); + + pinmux_tristate_disable(PMUX_PINGRP_KBCA); + pinmux_tristate_disable(PMUX_PINGRP_KBCC); + pinmux_tristate_disable(PMUX_PINGRP_KBCD); + pinmux_tristate_disable(PMUX_PINGRP_KBCE); + pinmux_tristate_disable(PMUX_PINGRP_KBCF); bad_config = 0; break; @@ -270,13 +271,13 @@ int funcmux_select(enum periph_id id, int config) if (config == FUNCMUX_DEFAULT) { int i; - for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) { + for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) { pinmux_set_func(i, PMUX_FUNC_DISPA); pinmux_tristate_disable(i); pinmux_set_pullupdown(i, PMUX_PULL_NORMAL); } - pinmux_config_table(disp1_default, - ARRAY_SIZE(disp1_default)); + pinmux_config_pingrp_table(disp1_default, + ARRAY_SIZE(disp1_default)); } break; diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c index a65e991519..e484f991bf 100644 --- a/arch/arm/cpu/tegra20-common/pinmux.c +++ b/arch/arm/cpu/tegra20-common/pinmux.c @@ -8,10 +8,8 @@ #include #include -#include #include - /* * This defines the order of the pin mux control bits in the registers. For * some reason there is no correspendence between the tristate, pin mux and @@ -256,302 +254,172 @@ enum pmux_pullid { PUCTL_NONE = -1 }; -struct tegra_pingroup_desc { - const char *name; - enum pmux_func funcs[4]; - enum pmux_func func_safe; - enum pmux_vddio vddio; - enum pmux_ctlid ctl_id; - enum pmux_pullid pull_id; -}; - - -/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */ -#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5) - -/* Mask value for a tristate (within TRISTATE_REG(id)) */ -#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f)) - -/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */ -#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4) - -/* Converts a PUCTL id to a shift position */ -#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f) - -/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */ -#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4) - -/* Converts a MUXCTL id to a shift position */ -#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f) - /* Convenient macro for defining pin group properties */ -#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \ +#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \ { \ - .vddio = PMUX_VDDIO_ ## vdd, \ .funcs = { \ - PMUX_FUNC_ ## f0, \ - PMUX_FUNC_ ## f1, \ - PMUX_FUNC_ ## f2, \ - PMUX_FUNC_ ## f3, \ + PMUX_FUNC_ ## f0, \ + PMUX_FUNC_ ## f1, \ + PMUX_FUNC_ ## f2, \ + PMUX_FUNC_ ## f3, \ }, \ - .func_safe = PMUX_FUNC_ ## f_safe, \ .ctl_id = mux, \ .pull_id = pupd \ } /* A normal pin group where the mux name and pull-up name match */ -#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \ - PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \ - MUXCTL_ ## pg_name, PUCTL_ ## pg_name) +#define PIN(pingrp, f0, f1, f2, f3) \ + PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp) /* A pin group where the pull-up name doesn't have a 1-1 mapping */ -#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \ - PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \ - MUXCTL_ ## pg_name, PUCTL_ ## pupd) +#define PINP(pingrp, f0, f1, f2, f3, pupd) \ + PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd) /* A pin group number which is not used */ #define PIN_RESERVED \ - PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE) - -const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { - PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE), - PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE), - PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE), - PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE), - PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC), - PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC), - PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, - PLLC_OUT1), - PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1), - - PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2), - PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3), - PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4), - PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4), - PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1), - PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1), - PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1), - PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1), - - PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, - GPSLXAU), - PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE), - PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4), - PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB), - PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB), - PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC), - PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC), - PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE), - - PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4), - PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4), - PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC), - PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC), - PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3), - PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4), - PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2), - PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR), - - PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI), - PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC), - PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM), + PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4) + +#define DRVGRP(drvgrp) \ + PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE) + +static const struct pmux_pingrp_desc tegra20_pingroups[] = { + PIN(ATA, IDE, NAND, GMI, RSVD4), + PIN(ATB, IDE, NAND, GMI, SDIO4), + PIN(ATC, IDE, NAND, GMI, SDIO4), + PIN(ATD, IDE, NAND, GMI, SDIO4), + PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC), + PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4), + PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK), + PIN(DAP1, DAP1, RSVD2, GMI, SDIO2), + + PIN(DAP2, DAP2, TWC, RSVD3, GMI), + PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4), + PIN(DAP4, DAP4, RSVD2, GMI, RSVD4), + PIN(DTA, RSVD1, SDIO2, VI, RSVD4), + PIN(DTB, RSVD1, RSVD2, VI, SPI1), + PIN(DTC, RSVD1, RSVD2, VI, RSVD4), + PIN(DTD, RSVD1, SDIO2, VI, RSVD4), + PIN(DTE, RSVD1, RSVD2, VI, SPI1), + + PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU), + PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4), + PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4), + PIN(IRTX, UARTA, UARTB, GMI, SPI4), + PIN(IRRX, UARTA, UARTB, GMI, SPI4), + PIN(KBCB, KBC, NAND, SDIO2, MIO), + PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL), + PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE), + + PIN(PTA, I2C2, HDMI, GMI, RSVD4), + PIN(RM, I2C, RSVD2, RSVD3, RSVD4), + PIN(KBCE, KBC, NAND, OWR, RSVD4), + PIN(KBCF, KBC, NAND, TRACE, MIO), + PIN(GMA, UARTE, SPI3, GMI, SDIO4), + PIN(GMC, UARTD, SPI4, GMI, SFLASH), + PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA), + PIN(OWC, OWR, RSVD2, RSVD3, RSVD4), + + PIN(GME, RSVD1, DAP5, GMI, SDIO4), + PIN(SDC, PWM, TWC, SDIO3, SPI3), + PIN(SDD, UARTA, PWM, SDIO3, SPI3), PIN_RESERVED, - PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP), - PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4), - PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4), - PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE), - - PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2), - PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2), - PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI), - PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI), - PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI), - PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI), - PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI), - PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4), - - PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT), - PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT), - PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS), - PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS), - PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4), - PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF), - PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4), - PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4), + PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP), + PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2), + PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2), + PIN(SLXK, PCIE, SPI4, SDIO3, SPI2), + + PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2), + PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2), + PIN(SPIA, SPI1, SPI2, SPI3, GMI), + PIN(SPIB, SPI1, SPI2, SPI3, GMI), + PIN(SPIC, SPI1, SPI2, SPI3, GMI), + PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI), + PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI), + PIN(SPIF, SPI3, SPI1, SPI2, RSVD4), + + PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C), + PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C), + PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI), + PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI), + PIN(UAC, OWR, RSVD2, RSVD3, RSVD4), + PIN(UAD, UARTB, SPDIF, UARTA, SPI4), + PIN(UCA, UARTC, RSVD2, GMI, RSVD4), + PIN(UCB, UARTC, PWM, GMI, RSVD4), PIN_RESERVED, - PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE), - PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC), + PIN(ATE, IDE, NAND, GMI, RSVD4), + PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL), PIN_RESERVED, PIN_RESERVED, - PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI), - PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI), - PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4), + PIN(GMB, IDE, NAND, GMI, GMI_INT), + PIN(GMD, RSVD1, NAND, GMI, SFLASH), + PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4), /* 64 */ - PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - - PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - - PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17), - PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17), - PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20), - PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18), - PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18), - PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC), - PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20), - PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC), - - PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC), - PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC), - PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC), - PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC), - PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS), - PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS), - PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS), - PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS), + PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17), + + PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17), + + PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17), + PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17), + PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20), + PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18), + PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18), + PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC), + PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20), + PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC), + + PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC), + PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC), + PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC), + PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC), + PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS), + PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS), + PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS), + PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS), /* 96 */ - PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC), - PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS), - PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS), - PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS), - PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS), - PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS), - PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22), - PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC), - - PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22), + PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC), + PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS), + PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS), + PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS), + PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS), + PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS), + PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22), + PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC), + + PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22), PIN_RESERVED, - PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC), - PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK), - PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4), - PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2), - PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD), - PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE), + PIN(KBCD, KBC, NAND, SDIO2, MIO), + PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4), + PIN(DTF, I2C3, RSVD2, VI, RSVD4), + PIN(UDA, SPI1, RSVD2, UARTD, ULPI), + PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4), + PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE), /* these pin groups only have pullup and pull down control */ - PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), - PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), - PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), - PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), - PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), - PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), - PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), - PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), - PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE, - PUCTL_NONE), + DRVGRP(CK32), + DRVGRP(DDRC), + DRVGRP(PMCA), + DRVGRP(PMCB), + DRVGRP(PMCC), + DRVGRP(PMCD), + DRVGRP(PMCE), + DRVGRP(XM2C), + DRVGRP(XM2D), }; - -void pinmux_set_tristate(enum pmux_pingrp pin, int enable) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)]; - u32 reg; - - reg = readl(tri); - if (enable) - reg |= TRISTATE_MASK(pin); - else - reg &= ~TRISTATE_MASK(pin); - writel(reg, tri); -} - -void pinmux_tristate_enable(enum pmux_pingrp pin) -{ - pinmux_set_tristate(pin, 1); -} - -void pinmux_tristate_disable(enum pmux_pingrp pin) -{ - pinmux_set_tristate(pin, 0); -} - -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id; - u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)]; - u32 mask_bit; - u32 reg; - mask_bit = PULL_SHIFT(pull_id); - - reg = readl(pull); - reg &= ~(0x3 << mask_bit); - reg |= pupd << mask_bit; - writel(reg, pull); -} - -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id; - u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)]; - u32 mask_bit; - int i, mux = -1; - u32 reg; - - assert(pmux_func_isvalid(func)); - - /* Handle special values */ - if (func >= PMUX_FUNC_RSVD1) { - mux = (func - PMUX_FUNC_RSVD1) & 0x3; - } else { - /* Search for the appropriate function */ - for (i = 0; i < 4; i++) { - if (tegra_soc_pingroups[pin].funcs[i] == func) { - mux = i; - break; - } - } - } - assert(mux != -1); - - mask_bit = MUXCTL_SHIFT(mux_id); - reg = readl(muxctl); - reg &= ~(0x3 << mask_bit); - reg |= mux << mask_bit; - writel(reg, muxctl); -} - -void pinmux_config_pingroup(const struct pingroup_config *config) -{ - enum pmux_pingrp pin = config->pingroup; - - pinmux_set_func(pin, config->func); - pinmux_set_pullupdown(pin, config->pull); - pinmux_set_tristate(pin, config->tristate); -} - -void pinmux_config_table(const struct pingroup_config *config, int len) -{ - int i; - - for (i = 0; i < len; i++) - pinmux_config_pingroup(&config[i]); -} +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups; diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c index c595f70e93..a774246a27 100644 --- a/arch/arm/cpu/tegra20-common/pmu.c +++ b/arch/arm/cpu/tegra20-common/pmu.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -23,9 +24,13 @@ #define VDD_TRANSITION_STEP 0x06 /* 150mv */ #define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */ +#define PMI_I2C_ADDRESS 0x34 /* chip requires this address */ + int pmu_set_nominal(void) { - int core, cpu, bus; + struct udevice *bus, *dev; + int core, cpu; + int ret; /* by default, the table has been filled with T25 settings */ switch (tegra_get_chip_sku()) { @@ -42,12 +47,18 @@ int pmu_set_nominal(void) return -1; } - bus = tegra_i2c_get_dvc_bus_num(); - if (bus == -1) { + ret = tegra_i2c_get_dvc_bus(&bus); + if (ret) { debug("%s: Cannot find DVC I2C bus\n", __func__); - return -1; + return ret; } - tps6586x_init(bus); + ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev); + if (ret) { + debug("%s: Cannot find DVC I2C chip\n", __func__); + return ret; + } + + tps6586x_init(dev); tps6586x_set_pwm_mode(TPS6586X_PWM_SM1); return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP, VDD_TRANSITION_RATE, VDD_RELATION); diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c index 8beba53fc3..5fdc4bbb50 100644 --- a/arch/arm/cpu/tegra20-common/warmboot.c +++ b/arch/arm/cpu/tegra20-common/warmboot.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -122,7 +123,8 @@ int warmboot_save_sdram_params(void) { u32 ram_code; struct sdram_params sdram; - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct apb_misc_gp_ctlr *gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; @@ -135,8 +137,8 @@ int warmboot_save_sdram_params(void) union fbio_spare_reg fbio_spare; /* get ram code that is used as index to array sdram_params in BCT */ - ram_code = (readl(&pmt->pmt_strap_opt_a) >> - STRAP_OPT_A_RAM_CODE_SHIFT) & 3; + ram_code = (readl(&apb_misc->strapping_opt_a) >> + STRAP_OPT_A_RAM_CODE_SHIFT) & 3; memcpy(&sdram, (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code), sizeof(sdram)); diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index b910f7844b..27ce5f480f 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -21,7 +22,8 @@ void wb_start(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; struct clk_rst_ctlr *clkrst = @@ -33,7 +35,7 @@ void wb_start(void) u32 reg; /* enable JTAG & TBE */ - writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl); + writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl); /* Are we running where we're supposed to be? */ asm volatile ( diff --git a/arch/arm/cpu/tegra30-common/Makefile b/arch/arm/cpu/tegra30-common/Makefile index 75fef32b0d..d2d616e8a4 100644 --- a/arch/arm/cpu/tegra30-common/Makefile +++ b/arch/arm/cpu/tegra30-common/Makefile @@ -17,28 +17,4 @@ # along with this program. If not, see . # -include $(TOPDIR)/config.mk - -# The AVP is ARMv4T architecture so we must use special compiler -# flags for any startup files it might use. - -LIB = $(obj)lib$(SOC)-common.o - -COBJS-y += clock.o funcmux.o pinmux.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += clock.o funcmux.o pinmux.o diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c index 74bd22be1a..0eb0f0ade3 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/cpu/tegra30-common/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,6 +17,7 @@ /* Tegra30 Clock control functions */ #include +#include #include #include #include @@ -60,12 +61,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. @@ -108,7 +103,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { MASK_BITS_31_29}, { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_29_28} + MASK_BITS_31_28} }; /* @@ -569,6 +564,7 @@ enum periph_id clk_id_to_periph_id(int clk_id) case PERIPH_ID_RESERVED43: case PERIPH_ID_RESERVED45: case PERIPH_ID_RESERVED56: + case PERIPH_ID_PCIEXCLK: case PERIPH_ID_RESERVED76: case PERIPH_ID_RESERVED77: case PERIPH_ID_RESERVED78: @@ -587,36 +583,162 @@ enum periph_id clk_id_to_periph_id(int clk_id) void clock_early_init(void) { - /* - * PLLP output frequency set to 408Mhz - * PLLC output frequency set to 228Mhz - */ - switch (clock_get_osc_freq()) { - case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); - break; - - case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); - break; - - case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ - clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); - break; - case CLOCK_OSC_FREQ_19_2: - default: - /* - * These are not supported. It is too early to print a - * message and the UART likely won't work anyway due to the - * oscillator being wrong. - */ - break; - } + tegra30_set_up_pllp(); } void arch_timer_init(void) { } + +#define PMC_SATA_PWRGT 0x1ac +#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5) +#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4) + +#define PLLE_SS_CNTL 0x68 +#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24) +#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) +#define PLLE_SS_CNTL_SSCBYP (1 << 12) +#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) +#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) +#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) + +#define PLLE_BASE 0x0e8 +#define PLLE_BASE_ENABLE_CML (1 << 31) +#define PLLE_BASE_ENABLE (1 << 30) +#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) +#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16) +#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) +#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) + +#define PLLE_MISC 0x0ec +#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) +#define PLLE_MISC_PLL_READY (1 << 15) +#define PLLE_MISC_LOCK (1 << 11) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) +#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2) + +static int tegra_plle_train(void) +{ + unsigned int timeout = 2000; + unsigned long value; + + value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); + value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; + writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); + + value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); + value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; + writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); + + value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); + value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE; + writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); + + do { + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + if (value & PLLE_MISC_PLL_READY) + break; + + udelay(100); + } while (--timeout); + + if (timeout == 0) { + error("timeout waiting for PLLE to become ready"); + return -ETIMEDOUT; + } + + return 0; +} + +int tegra_plle_enable(void) +{ + unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000; + u32 value; + int err; + + /* disable PLLE clock */ + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value &= ~PLLE_BASE_ENABLE_CML; + value &= ~PLLE_BASE_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + /* clear lock enable and setup field */ + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value &= ~PLLE_MISC_LOCK_ENABLE; + value &= ~PLLE_MISC_SETUP_BASE(0xffff); + value &= ~PLLE_MISC_SETUP_EXT(0x3); + writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + if ((value & PLLE_MISC_PLL_READY) == 0) { + err = tegra_plle_train(); + if (err < 0) { + error("failed to train PLLE: %d", err); + return err; + } + } + + /* configure PLLE */ + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + + value &= ~PLLE_BASE_PLDIV_CML(0x0f); + value |= PLLE_BASE_PLDIV_CML(cpcon); + + value &= ~PLLE_BASE_PLDIV(0x3f); + value |= PLLE_BASE_PLDIV(p); + + value &= ~PLLE_BASE_NDIV(0xff); + value |= PLLE_BASE_NDIV(n); + + value &= ~PLLE_BASE_MDIV(0xff); + value |= PLLE_BASE_MDIV(m); + + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value |= PLLE_MISC_SETUP_BASE(0x7); + value |= PLLE_MISC_LOCK_ENABLE; + value |= PLLE_MISC_SETUP_EXT(0); + writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | + PLLE_SS_CNTL_BYPASS_SS; + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + do { + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + if (value & PLLE_MISC_LOCK) + break; + + udelay(2); + } while (--timeout); + + if (timeout == 0) { + error("timeout waiting for PLLE to lock"); + return -ETIMEDOUT; + } + + udelay(50); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f); + value |= PLLE_SS_CNTL_SSCINCINTRV(0x18); + + value &= ~PLLE_SS_CNTL_SSCINC(0xff); + value |= PLLE_SS_CNTL_SSCINC(0x01); + + value &= ~PLLE_SS_CNTL_SSCBYP; + value &= ~PLLE_SS_CNTL_INTERP_RESET; + value &= ~PLLE_SS_CNTL_BYPASS_SS; + + value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); + value |= PLLE_SS_CNTL_SSCMAX(0x24); + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + return 0; +} diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/cpu/tegra30-common/funcmux.c index e24c57efbd..409335ce1d 100644 --- a/arch/arm/cpu/tegra30-common/funcmux.c +++ b/arch/arm/cpu/tegra30-common/funcmux.c @@ -29,14 +29,18 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_UART1: switch (config) { case FUNCMUX_UART1_ULPI: - pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PINGRP_ULPI_DATA0); - pinmux_tristate_disable(PINGRP_ULPI_DATA1); - pinmux_tristate_disable(PINGRP_ULPI_DATA2); - pinmux_tristate_disable(PINGRP_ULPI_DATA3); + pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1); + pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2); + pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3); + pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4); break; } break; diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c index eecf0580bc..7eb05743b4 100644 --- a/arch/arm/cpu/tegra30-common/pinmux.c +++ b/arch/arm/cpu/tegra30-common/pinmux.c @@ -1,694 +1,276 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0+ */ -/* Tegra30 pin multiplexing functions */ - #include #include -#include #include -struct tegra_pingroup_desc { - const char *name; - enum pmux_func funcs[4]; - enum pmux_func func_safe; - enum pmux_vddio vddio; - enum pmux_pin_io io; -}; - -#define PMUX_MUXCTL_SHIFT 0 -#define PMUX_PULL_SHIFT 2 -#define PMUX_TRISTATE_SHIFT 4 -#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT) -#define PMUX_IO_SHIFT 5 -#define PMUX_OD_SHIFT 6 -#define PMUX_LOCK_SHIFT 7 -#define PMUX_IO_RESET_SHIFT 8 - -#define PGRP_HSM_SHIFT 2 -#define PGRP_SCHMT_SHIFT 3 -#define PGRP_LPMD_SHIFT 4 -#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT) -#define PGRP_DRVDN_SHIFT 12 -#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT) -#define PGRP_DRVUP_SHIFT 20 -#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT) -#define PGRP_SLWR_SHIFT 28 -#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT) -#define PGRP_SLWF_SHIFT 30 -#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT) - -/* Convenient macro for defining pin group properties */ -#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ - { \ - .vddio = PMUX_VDDIO_ ## vdd, \ - .funcs = { \ - PMUX_FUNC_ ## f0, \ - PMUX_FUNC_ ## f1, \ - PMUX_FUNC_ ## f2, \ - PMUX_FUNC_ ## f3, \ - }, \ - .func_safe = PMUX_FUNC_RSVD1, \ - .io = PMUX_PIN_ ## iod, \ +#define PIN(pin, f0, f1, f2, f3) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + PMUX_FUNC_##f2, \ + PMUX_FUNC_##f3, \ + }, \ } -/* Input and output pins */ -#define PINI(pg_name, vdd, f0, f1, f2, f3) \ - PIN(pg_name, vdd, f0, f1, f2, f3, INPUT) -#define PINO(pg_name, vdd, f0, f1, f2, f3) \ - PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT) - -const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { - /* NAME VDD f0 f1 f2 f3 */ - PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI), - PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI), - PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI), - PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI), - PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI), - PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI), - PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI), - PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI), - PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI), - PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI), - PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI), - PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI), - PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB), - PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB), - PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB), - PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB), - PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA), - PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA), - PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA), - PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA), - PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA), - PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA), - PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4), - PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4), - PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4), - PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4), - PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP), - PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4), - PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP), - PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP), - PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4), - PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP), - PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP), - PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4), - PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4), - PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4), - PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4), - PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4), - PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4), - PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4), - PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4), - PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4), - PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4), - PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4), - PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4), - PINI(VI_MCLK, VI, VI, VI, VI, VI), - PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4), - PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4), - PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4), - PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4), - PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4), - PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4), - PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4), - PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4), - PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4), - PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4), - PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4), - PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4), - PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4), - PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4), - PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4), - PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4), - PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4), - PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4), - PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4), - PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4), - PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4), - PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4), - PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4), - PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4), - PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4), - PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT), - PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV), - PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV), - PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT), - PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA), - PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT), - PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4), - PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4), - PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4), - PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4), - PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT), - PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV), - PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV), - PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4), - PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4), - PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4), - PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4), - PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4), - PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4), - PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4), - PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4), - PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4), - PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4), - PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4), - PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4), - PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4), - PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4), - PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4), - PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4), - PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4), - PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4), - PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4), - PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4), - PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4), - PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4), - PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4), - PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4), - PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4), - PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4), - PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4), - PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4), - PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4), - PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4), - PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4), - PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4), - PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4), - PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4), - PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4), - PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR), - PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO), - PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST), - PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST), - PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4), - PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4), - PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4), - PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4), - PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO), - PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO), - PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4), - PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4), - PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4), - PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4), - PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4), - PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4), - PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4), - PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2), - PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2), - PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2), - PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2), - PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4), - PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4), - PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2), - PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2), - PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI), - PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI), - PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI), - PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI), - PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI), - PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI), - PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI), - PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI), - PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI), - PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI), - PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI), - PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4), - PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1), - PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1), - PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3), - PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2), - PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3), - PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3), - PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3), - PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3), - PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2), - PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2), - PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2), - PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2), - PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4), - PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4), +#define PIN_RESERVED {} + +static const struct pmux_pingrp_desc tegra30_pingroups[] = { + /* pin, f0, f1, f2, f3 */ + /* Offset 0x3000 */ + PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI), + PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI), + PIN(ULPI_CLK_PY0, SPI1, RSVD2, UARTD, ULPI), + PIN(ULPI_DIR_PY1, SPI1, RSVD2, UARTD, ULPI), + PIN(ULPI_NXT_PY2, SPI1, RSVD2, UARTD, ULPI), + PIN(ULPI_STP_PY3, SPI1, RSVD2, UARTD, ULPI), + PIN(DAP3_FS_PP0, I2S2, RSVD2, DISPLAYA, DISPLAYB), + PIN(DAP3_DIN_PP1, I2S2, RSVD2, DISPLAYA, DISPLAYB), + PIN(DAP3_DOUT_PP2, I2S2, RSVD2, DISPLAYA, DISPLAYB), + PIN(DAP3_SCLK_PP3, I2S2, RSVD2, DISPLAYA, DISPLAYB), + PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4), + PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4), + PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA), + PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA), + PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA), + PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA), + PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA), + PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA), + PIN(PV2, OWR, RSVD2, RSVD3, RSVD4), + PIN(PV3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4), + PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4), + PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4), + PIN(LCD_PWR1_PC1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_PWR2_PC6, DISPLAYA, DISPLAYB, SPI5, HDCP), + PIN(LCD_SDIN_PZ2, DISPLAYA, DISPLAYB, SPI5, RSVD4), + PIN(LCD_SDOUT_PN5, DISPLAYA, DISPLAYB, SPI5, HDCP), + PIN(LCD_WR_N_PZ3, DISPLAYA, DISPLAYB, SPI5, HDCP), + PIN(LCD_CS0_N_PN4, DISPLAYA, DISPLAYB, SPI5, RSVD4), + PIN(LCD_DC0_PN6, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_SCK_PZ4, DISPLAYA, DISPLAYB, SPI5, HDCP), + PIN(LCD_PWR0_PB2, DISPLAYA, DISPLAYB, SPI5, HDCP), + PIN(LCD_PCLK_PB3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_DE_PJ1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_HSYNC_PJ3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_VSYNC_PJ4, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D0_PE0, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D1_PE1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D2_PE2, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D3_PE3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D4_PE4, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D5_PE5, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D6_PE6, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D7_PE7, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D8_PF0, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D9_PF1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D10_PF2, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D11_PF3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D12_PF4, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D13_PF5, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D14_PF6, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D15_PF7, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D16_PM0, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D17_PM1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D18_PM2, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D19_PM3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D20_PM4, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D21_PM5, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D22_PM6, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_D23_PM7, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_CS1_N_PW0, DISPLAYA, DISPLAYB, SPI5, RSVD4), + PIN(LCD_M1_PW1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(LCD_DC1_PD2, DISPLAYA, DISPLAYB, RSVD3, RSVD4), + PIN(HDMI_INT_PN7, HDMI, RSVD2, RSVD3, RSVD4), + PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4), + PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4), + PIN(CRT_HSYNC_PV6, CRT, RSVD2, RSVD3, RSVD4), + PIN(CRT_VSYNC_PV7, CRT, RSVD2, RSVD3, RSVD4), + PIN(VI_D0_PT4, DDR, RSVD2, VI, RSVD4), + PIN(VI_D1_PD5, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D2_PL0, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D3_PL1, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D4_PL2, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D5_PL3, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D6_PL4, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D7_PL5, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D8_PL6, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D9_PL7, DDR, SDMMC2, VI, RSVD4), + PIN(VI_D10_PT2, DDR, RSVD2, VI, RSVD4), + PIN(VI_D11_PT3, DDR, RSVD2, VI, RSVD4), + PIN(VI_PCLK_PT0, RSVD1, SDMMC2, VI, RSVD4), + PIN(VI_MCLK_PT1, VI, VI_ALT1, VI_ALT2, VI_ALT3), + PIN(VI_VSYNC_PD6, DDR, RSVD2, VI, RSVD4), + PIN(VI_HSYNC_PD7, DDR, RSVD2, VI, RSVD4), + PIN(UART2_RXD_PC3, UARTB, SPDIF, UARTA, SPI4), + PIN(UART2_TXD_PC2, UARTB, SPDIF, UARTA, SPI4), + PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4), + PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4), + PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, RSVD4), + PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, RSVD4), + PIN(UART3_CTS_N_PA1, UARTC, RSVD2, GMI, RSVD4), + PIN(UART3_RTS_N_PC0, UARTC, PWM0, GMI, RSVD4), + PIN(PU0, OWR, UARTA, GMI, RSVD4), + PIN(PU1, RSVD1, UARTA, GMI, RSVD4), + PIN(PU2, RSVD1, UARTA, GMI, RSVD4), + PIN(PU3, PWM0, UARTA, GMI, RSVD4), + PIN(PU4, PWM1, UARTA, GMI, RSVD4), + PIN(PU5, PWM2, UARTA, GMI, RSVD4), + PIN(PU6, PWM3, UARTA, GMI, RSVD4), + PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4), + PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4), + PIN(DAP4_FS_PP4, I2S3, RSVD2, GMI, RSVD4), + PIN(DAP4_DIN_PP5, I2S3, RSVD2, GMI, RSVD4), + PIN(DAP4_DOUT_PP6, I2S3, RSVD2, GMI, RSVD4), + PIN(DAP4_SCLK_PP7, I2S3, RSVD2, GMI, RSVD4), + PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4), + PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4), + PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT), + PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV), + PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV), + PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT), + PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SATA), + PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, GMI_ALT), + PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD8_PH0, PWM0, NAND, GMI, RSVD4), + PIN(GMI_AD9_PH1, PWM1, NAND, GMI, RSVD4), + PIN(GMI_AD10_PH2, PWM2, NAND, GMI, RSVD4), + PIN(GMI_AD11_PH3, PWM3, NAND, GMI, RSVD4), + PIN(GMI_AD12_PH4, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD13_PH5, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD14_PH6, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_AD15_PH7, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_A16_PJ7, UARTD, SPI4, GMI, GMI_ALT), + PIN(GMI_A17_PB0, UARTD, SPI4, GMI, DTV), + PIN(GMI_A18_PB1, UARTD, SPI4, GMI, DTV), + PIN(GMI_A19_PK7, UARTD, SPI4, GMI, RSVD4), + PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_DQS_PI2, RSVD1, NAND, GMI, RSVD4), + PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4), + PIN(GEN2_I2C_SCL_PT5, I2C2, HDCP, GMI, RSVD4), + PIN(GEN2_I2C_SDA_PT6, I2C2, HDCP, GMI, RSVD4), + PIN(SDMMC4_CLK_PCC4, INVALID, NAND, GMI, SDMMC4), + PIN(SDMMC4_CMD_PT7, I2C3, NAND, GMI, SDMMC4), + PIN(SDMMC4_DAT0_PAA0, UARTE, SPI3, GMI, SDMMC4), + PIN(SDMMC4_DAT1_PAA1, UARTE, SPI3, GMI, SDMMC4), + PIN(SDMMC4_DAT2_PAA2, UARTE, SPI3, GMI, SDMMC4), + PIN(SDMMC4_DAT3_PAA3, UARTE, SPI3, GMI, SDMMC4), + PIN(SDMMC4_DAT4_PAA4, I2C3, I2S4, GMI, SDMMC4), + PIN(SDMMC4_DAT5_PAA5, VGP3, I2S4, GMI, SDMMC4), + PIN(SDMMC4_DAT6_PAA6, VGP4, I2S4, GMI, SDMMC4), + PIN(SDMMC4_DAT7_PAA7, VGP5, I2S4, GMI, SDMMC4), + PIN(SDMMC4_RST_N_PCC3, VGP6, RSVD2, RSVD3, SDMMC4), + PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC4), + PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC4), + PIN(PBB0, I2S4, RSVD2, RSVD3, SDMMC4), + PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC4), + PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC4), + PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC4), + PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC4), + PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, SDMMC4), + PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, SDMMC4), + PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC4), + PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4), + PIN(JTAG_RTCK_PU7, RTCK, RSVD2, RSVD3, RSVD4), + PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4), + PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4), + PIN(KB_ROW0_PR0, KBC, NAND, RSVD3, RSVD4), + PIN(KB_ROW1_PR1, KBC, NAND, RSVD3, RSVD4), + PIN(KB_ROW2_PR2, KBC, NAND, RSVD3, RSVD4), + PIN(KB_ROW3_PR3, KBC, NAND, RSVD3, INVALID), + PIN(KB_ROW4_PR4, KBC, NAND, TRACE, RSVD4), + PIN(KB_ROW5_PR5, KBC, NAND, TRACE, OWR), + PIN(KB_ROW6_PR6, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW7_PR7, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW8_PS0, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW9_PS1, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW10_PS2, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW11_PS3, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW12_PS4, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW13_PS5, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW14_PS6, KBC, NAND, SDMMC2, MIO), + PIN(KB_ROW15_PS7, KBC, NAND, SDMMC2, MIO), + PIN(KB_COL0_PQ0, KBC, NAND, TRACE, TEST), + PIN(KB_COL1_PQ1, KBC, NAND, TRACE, TEST), + PIN(KB_COL2_PQ2, KBC, NAND, TRACE, RSVD4), + PIN(KB_COL3_PQ3, KBC, NAND, TRACE, RSVD4), + PIN(KB_COL4_PQ4, KBC, NAND, TRACE, RSVD4), + PIN(KB_COL5_PQ5, KBC, NAND, TRACE, RSVD4), + PIN(KB_COL6_PQ6, KBC, NAND, TRACE, MIO), + PIN(KB_COL7_PQ7, KBC, NAND, TRACE, MIO), + PIN(CLK_32K_OUT_PA0, BLINK, RSVD2, RSVD3, RSVD4), + PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4), + PIN(CORE_PWR_REQ, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4), + PIN(CPU_PWR_REQ, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4), + PIN(PWR_INT_N, PWR_INT_N, RSVD2, RSVD3, RSVD4), + PIN(CLK_32K_IN, CLK_32K_IN, RSVD2, RSVD3, RSVD4), + PIN(OWR, OWR, CEC, RSVD3, RSVD4), + PIN(DAP1_FS_PN0, I2S0, HDA, GMI, SDMMC2), + PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, SDMMC2), + PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SDMMC2), + PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, SDMMC2), + PIN(CLK1_REQ_PEE2, DAP, HDA, RSVD3, RSVD4), + PIN(CLK1_OUT_PW4, EXTPERIPH1, RSVD2, RSVD3, RSVD4), + PIN(SPDIF_IN_PK6, SPDIF, HDA, I2C1, SDMMC2), + PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, I2C1, SDMMC2), + PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, GMI), + PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, GMI), + PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, GMI), + PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, GMI), + PIN(SPI2_MOSI_PX0, SPI6, SPI2, SPI3, GMI), + PIN(SPI2_MISO_PX1, SPI6, SPI2, SPI3, GMI), + PIN(SPI2_CS0_N_PX3, SPI6, SPI2, SPI3, GMI), + PIN(SPI2_SCK_PX2, SPI6, SPI2, SPI3, GMI), + PIN(SPI1_MOSI_PX4, SPI2, SPI1, SPI2_ALT, GMI), + PIN(SPI1_SCK_PX5, SPI2, SPI1, SPI2_ALT, GMI), + PIN(SPI1_CS0_N_PX6, SPI2, SPI1, SPI2_ALT, GMI), + PIN(SPI1_MISO_PX7, SPI3, SPI1, SPI2_ALT, RSVD4), + PIN(SPI2_CS1_N_PW2, SPI3, SPI2, SPI2_ALT, I2C1), + PIN(SPI2_CS2_N_PW3, SPI3, SPI2, SPI2_ALT, I2C1), + PIN(SDMMC3_CLK_PA6, UARTA, PWM2, SDMMC3, SPI3), + PIN(SDMMC3_CMD_PA7, UARTA, PWM3, SDMMC3, SPI2), + PIN(SDMMC3_DAT0_PB7, RSVD1, RSVD2, SDMMC3, SPI3), + PIN(SDMMC3_DAT1_PB6, RSVD1, RSVD2, SDMMC3, SPI3), + PIN(SDMMC3_DAT2_PB5, RSVD1, PWM1, SDMMC3, SPI3), + PIN(SDMMC3_DAT3_PB4, RSVD1, PWM0, SDMMC3, SPI3), + PIN(SDMMC3_DAT4_PD1, PWM1, SPI4, SDMMC3, SPI2), + PIN(SDMMC3_DAT5_PD0, PWM0, SPI4, SDMMC3, SPI2), + PIN(SDMMC3_DAT6_PD3, SPDIF, SPI4, SDMMC3, SPI2), + PIN(SDMMC3_DAT7_PD4, SPDIF, SPI4, SDMMC3, SPI2), + PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4), + PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4), + PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4), }; - -void pinmux_set_tristate(enum pmux_pingrp pin, int enable) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *tri = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin */ - assert(pmux_pingrp_isvalid(pin)); - - reg = readl(tri); - if (enable) - reg |= PMUX_TRISTATE_MASK; - else - reg &= ~PMUX_TRISTATE_MASK; - writel(reg, tri); -} - -void pinmux_tristate_enable(enum pmux_pingrp pin) -{ - pinmux_set_tristate(pin, 1); -} - -void pinmux_tristate_disable(enum pmux_pingrp pin) -{ - pinmux_set_tristate(pin, 0); -} - -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pull = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and pupd */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_pupd_isvalid(pupd)); - - reg = readl(pull); - reg &= ~(0x3 << PMUX_PULL_SHIFT); - reg |= (pupd << PMUX_PULL_SHIFT); - writel(reg, pull); -} - -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *muxctl = &pmt->pmt_ctl[pin]; - int i, mux = -1; - u32 reg; - - /* Error check on pin and func */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_func_isvalid(func)); - - /* Handle special values */ - if (func == PMUX_FUNC_SAFE) - func = tegra_soc_pingroups[pin].func_safe; - - if (func & PMUX_FUNC_RSVD1) { - mux = func & 0x3; - } else { - /* Search for the appropriate function */ - for (i = 0; i < 4; i++) { - if (tegra_soc_pingroups[pin].funcs[i] == func) { - mux = i; - break; - } - } - } - assert(mux != -1); - - reg = readl(muxctl); - reg &= ~(0x3 << PMUX_MUXCTL_SHIFT); - reg |= (mux << PMUX_MUXCTL_SHIFT); - writel(reg, muxctl); - -} - -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_io = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and io */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_io_isvalid(io)); - - reg = readl(pin_io); - reg &= ~(0x1 << PMUX_IO_SHIFT); - reg |= (io & 0x1) << PMUX_IO_SHIFT; - writel(reg, pin_io); -} - -static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_lock = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and lock */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_lock_isvalid(lock)); - - if (lock == PMUX_PIN_LOCK_DEFAULT) - return 0; - - reg = readl(pin_lock); - reg &= ~(0x1 << PMUX_LOCK_SHIFT); - if (lock == PMUX_PIN_LOCK_ENABLE) - reg |= (0x1 << PMUX_LOCK_SHIFT); - else { - /* lock == DISABLE, which isn't possible */ - printf("%s: Warning: lock == %d, DISABLE is not allowed!\n", - __func__, lock); - } - writel(reg, pin_lock); - - return 0; -} - -static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_od = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and od */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_od_isvalid(od)); - - if (od == PMUX_PIN_OD_DEFAULT) - return 0; - - reg = readl(pin_od); - reg &= ~(0x1 << PMUX_OD_SHIFT); - if (od == PMUX_PIN_OD_ENABLE) - reg |= (0x1 << PMUX_OD_SHIFT); - writel(reg, pin_od); - - return 0; -} - -static int pinmux_set_ioreset(enum pmux_pingrp pin, - enum pmux_pin_ioreset ioreset) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pin_ioreset = &pmt->pmt_ctl[pin]; - u32 reg; - - /* Error check on pin and ioreset */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_ioreset_isvalid(ioreset)); - - if (ioreset == PMUX_PIN_IO_RESET_DEFAULT) - return 0; - - reg = readl(pin_ioreset); - reg &= ~(0x1 << PMUX_IO_RESET_SHIFT); - if (ioreset == PMUX_PIN_IO_RESET_ENABLE) - reg |= (0x1 << PMUX_IO_RESET_SHIFT); - writel(reg, pin_ioreset); - - return 0; -} - -void pinmux_config_pingroup(struct pingroup_config *config) -{ - enum pmux_pingrp pin = config->pingroup; - - pinmux_set_func(pin, config->func); - pinmux_set_pullupdown(pin, config->pull); - pinmux_set_tristate(pin, config->tristate); - pinmux_set_io(pin, config->io); - pinmux_set_lock(pin, config->lock); - pinmux_set_od(pin, config->od); - pinmux_set_ioreset(pin, config->ioreset); -} - -void pinmux_config_table(struct pingroup_config *config, int len) -{ - int i; - - for (i = 0; i < len; i++) - pinmux_config_pingroup(&config[i]); -} - -static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, - int slwf) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_slwf = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check on pad and slwf */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_slw_isvalid(slwf)); - - /* NONE means unspecified/do not change/use POR value */ - if (slwf == PGRP_SLWF_NONE) - return 0; - - reg = readl(pad_slwf); - reg &= ~PGRP_SLWF_MASK; - reg |= (slwf << PGRP_SLWF_SHIFT); - writel(reg, pad_slwf); - - return 0; -} - -static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_slwr = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check on pad and slwr */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_slw_isvalid(slwr)); - - /* NONE means unspecified/do not change/use POR value */ - if (slwr == PGRP_SLWR_NONE) - return 0; - - reg = readl(pad_slwr); - reg &= ~PGRP_SLWR_MASK; - reg |= (slwr << PGRP_SLWR_SHIFT); - writel(reg, pad_slwr); - - return 0; -} - -static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_drvup = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check on pad and drvup */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_drv_isvalid(drvup)); - - /* NONE means unspecified/do not change/use POR value */ - if (drvup == PGRP_DRVUP_NONE) - return 0; - - reg = readl(pad_drvup); - reg &= ~PGRP_DRVUP_MASK; - reg |= (drvup << PGRP_DRVUP_SHIFT); - writel(reg, pad_drvup); - - return 0; -} - -static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_drvdn = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check on pad and drvdn */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_drv_isvalid(drvdn)); - - /* NONE means unspecified/do not change/use POR value */ - if (drvdn == PGRP_DRVDN_NONE) - return 0; - - reg = readl(pad_drvdn); - reg &= ~PGRP_DRVDN_MASK; - reg |= (drvdn << PGRP_DRVDN_SHIFT); - writel(reg, pad_drvdn); - - return 0; -} - -static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_lpmd = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check pad and lpmd value */ - assert(pmux_padgrp_isvalid(pad)); - assert(pmux_pad_lpmd_isvalid(lpmd)); - - /* NONE means unspecified/do not change/use POR value */ - if (lpmd == PGRP_LPMD_NONE) - return 0; - - reg = readl(pad_lpmd); - reg &= ~PGRP_LPMD_MASK; - reg |= (lpmd << PGRP_LPMD_SHIFT); - writel(reg, pad_lpmd); - - return 0; -} - -static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_schmt = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check pad */ - assert(pmux_padgrp_isvalid(pad)); - - reg = readl(pad_schmt); - reg &= ~(1 << PGRP_SCHMT_SHIFT); - if (schmt == PGRP_SCHMT_ENABLE) - reg |= (0x1 << PGRP_SCHMT_SHIFT); - writel(reg, pad_schmt); - - return 0; -} -static int padgrp_set_hsm(enum pdrive_pingrp pad, - enum pgrp_hsm hsm) -{ - struct pmux_tri_ctlr *pmt = - (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - u32 *pad_hsm = &pmt->pmt_drive[pad]; - u32 reg; - - /* Error check pad */ - assert(pmux_padgrp_isvalid(pad)); - - reg = readl(pad_hsm); - reg &= ~(1 << PGRP_HSM_SHIFT); - if (hsm == PGRP_HSM_ENABLE) - reg |= (0x1 << PGRP_HSM_SHIFT); - writel(reg, pad_hsm); - - return 0; -} - -void padctrl_config_pingroup(struct padctrl_config *config) -{ - enum pdrive_pingrp pad = config->padgrp; - - padgrp_set_drvup_slwf(pad, config->slwf); - padgrp_set_drvdn_slwr(pad, config->slwr); - padgrp_set_drvup(pad, config->drvup); - padgrp_set_drvdn(pad, config->drvdn); - padgrp_set_lpmd(pad, config->lpmd); - padgrp_set_schmt(pad, config->schmt); - padgrp_set_hsm(pad, config->hsm); -} - -void padgrp_config_table(struct padctrl_config *config, int len) -{ - int i; - - for (i = 0; i < len; i++) - padctrl_config_pingroup(&config[i]); -} +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups; diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 36cc54a292..a8be204038 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -18,6 +18,7 @@ SECTIONS .text : { __image_copy_start = .; + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } @@ -31,8 +32,18 @@ SECTIONS } . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } . = .; +#ifdef CONFIG_SPL_DM + .u_boot_list : { + KEEP(*(SORT(.u_boot_list_*_driver_*))); + KEEP(*(SORT(.u_boot_list_*_uclass_*))); + } +#endif + . = ALIGN(4); __image_copy_end = .; @@ -42,7 +53,12 @@ SECTIONS __rel_dyn_end = .; } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; @@ -51,12 +67,15 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } #if defined(CONFIG_SPL_MAX_SIZE) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 490aed2e0d..7336162d80 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -7,6 +7,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) @@ -18,10 +20,39 @@ SECTIONS .text : { *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI) + +#ifndef CONFIG_ARMV7_SECURE_BASE +#define CONFIG_ARMV7_SECURE_BASE +#endif + + .__secure_start : { + . = ALIGN(0x1000); + *(.__secure_start) + } + + .secure_text CONFIG_ARMV7_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + . = LOADADDR(.__secure_start) + + SIZEOF(.__secure_start) + + SIZEOF(.secure_text); + + __secure_end_lma = .; + .__secure_end : AT(__secure_end_lma) { + *(.__secure_end) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } @@ -60,7 +91,12 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; /* * Deprecated: this MMU section is used by pxa at present but @@ -91,10 +127,14 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu.hash : { *(.gnu.hash) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } } diff --git a/arch/arm/dts/.gitignore b/arch/arm/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/arm/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile new file mode 100644 index 0000000000..fac16cc384 --- /dev/null +++ b/arch/arm/dts/Makefile @@ -0,0 +1,62 @@ +dtb-$(CONFIG_MACH_SUN7I) += sun7i-a20-pcduino3.dtb +dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb +dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb +dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ + exynos4210-universal_c210.dtb \ + exynos4210-trats.dtb \ + exynos4412-trats2.dtb \ + exynos4412-odroid.dtb + +dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ + exynos5250-snow.dtb \ + exynos5250-smdk5250.dtb \ + exynos5420-smdk5420.dtb \ + exynos5420-peach-pit.dtb \ + exynos5800-peach-pi.dtb \ + exynos5422-odroidxu3.dtb +dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ + tegra20-medcom-wide.dtb \ + tegra20-paz00.dtb \ + tegra20-plutux.dtb \ + tegra20-seaboard.dtb \ + tegra20-tec.dtb \ + tegra20-trimslice.dtb \ + tegra20-ventana.dtb \ + tegra20-whistler.dtb \ + tegra20-colibri_t20_iris.dtb \ + tegra30-apalis.dtb \ + tegra30-beaver.dtb \ + tegra30-cardhu.dtb \ + tegra30-colibri.dtb \ + tegra30-tec-ng.dtb \ + tegra114-dalmore.dtb \ + tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ + tegra124-venice2.dtb +dtb-$(CONFIG_ARCH_UNIPHIER) += \ + uniphier-ph1-sld3-ref.dtb \ + uniphier-ph1-pro4-ref.dtb \ + uniphier-ph1-ld4-ref.dtb \ + uniphier-ph1-sld8-ref.dtb +dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ + zynq-zc706.dtb \ + zynq-zed.dtb \ + zynq-zybo.dtb \ + zynq-microzed.dtb \ + zynq-zc770-xm010.dtb \ + zynq-zc770-xm012.dtb \ + zynq-zc770-xm013.dtb +dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb + +dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi new file mode 100644 index 0000000000..e70b4d1f1f --- /dev/null +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + model = "TI AM335x BeagleBone"; + compatible = "ti,am335x-bone", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + am33xx_pinmux: pinmux@44e10800 { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + }; + + ocp { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; + }; + + musb: usb@47400000 { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; + }; + + i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + }; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led@2 { + label = "beaglebone:green:heartbeat"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@3 { + label = "beaglebone:green:mmc0"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-always-on; + }; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts new file mode 100644 index 0000000000..197cadf72d --- /dev/null +++ b/arch/arm/dts/am335x-boneblack.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index edee62f338..f9c5da9c7f 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -8,10 +8,14 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include +#include + +#include "skeleton.dtsi" / { compatible = "ti,am33xx"; + interrupt-parent = <&intc>; aliases { serial0 = &uart0; @@ -20,11 +24,36 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; + d_can0 = &dcan0; + d_can1 = &dcan1; + usb0 = &usb0; + usb1 = &usb1; + phy0 = &usb0_phy; + phy1 = &usb1_phy; }; cpus { + #address-cells = <1>; + #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; + + /* + * To consider voltage drop between PMIC and SoC, + * tolerance value is reduced to 2% from 4% and + * voltage value is increased as a precaution. + */ + operating-points = < + /* kHz uV */ + 720000 1285000 + 600000 1225000 + 500000 1125000 + 275000 1125000 + >; + voltage-tolerance = <2>; /* 2 percentage */ + clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; @@ -40,6 +69,15 @@ }; }; + am33xx_pinmux: pinmux@44e10800 { + compatible = "pinctrl-single"; + reg = <0x44e10800 0x0238>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; + /* * XXX: Use a flat representation of the AM33XX interconnect. * The real AM33XX interconnect network is quite complex.Since @@ -69,90 +107,543 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x44e07000 0x1000>; + interrupts = <96>; }; - gpio1: gpio@4804C000 { + gpio1: gpio@4804c000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x4804c000 0x1000>; + interrupts = <98>; }; - gpio2: gpio@481AC000 { + gpio2: gpio@481ac000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x481ac000 0x1000>; + interrupts = <32>; }; - gpio3: gpio@481AE000 { + gpio3: gpio@481ae000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x481ae000 0x1000>; + interrupts = <62>; }; - uart0: serial@44E09000 { + uart0: serial@44e09000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; + reg = <0x44e09000 0x2000>; + interrupts = <72>; + status = "disabled"; }; uart1: serial@48022000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; + reg = <0x48022000 0x2000>; + interrupts = <73>; + status = "disabled"; }; uart2: serial@48024000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; + reg = <0x48024000 0x2000>; + interrupts = <74>; + status = "disabled"; }; - uart3: serial@481A6000 { + uart3: serial@481a6000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; + reg = <0x481a6000 0x2000>; + interrupts = <44>; + status = "disabled"; }; - uart4: serial@481A8000 { + uart4: serial@481a8000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; + reg = <0x481a8000 0x2000>; + interrupts = <45>; + status = "disabled"; }; - uart5: serial@481AA000 { + uart5: serial@481aa000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; + reg = <0x481aa000 0x2000>; + interrupts = <46>; + status = "disabled"; }; - i2c0: i2c@44E0B000 { + i2c0: i2c@44e0b000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; + reg = <0x44e0b000 0x1000>; + interrupts = <70>; + status = "disabled"; }; - i2c1: i2c@4802A000 { + i2c1: i2c@4802a000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; + reg = <0x4802a000 0x1000>; + interrupts = <71>; + status = "disabled"; }; - i2c2: i2c@4819C000 { + i2c2: i2c@4819c000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; + reg = <0x4819c000 0x1000>; + interrupts = <30>; + status = "disabled"; + }; + + wdt2: wdt@44e35000 { + compatible = "ti,omap3-wdt"; + ti,hwmods = "wd_timer2"; + reg = <0x44e35000 0x1000>; + interrupts = <91>; + }; + + dcan0: d_can@481cc000 { + compatible = "bosch,d_can"; + ti,hwmods = "d_can0"; + reg = <0x481cc000 0x2000 + 0x44e10644 0x4>; + interrupts = <52>; + status = "disabled"; + }; + + dcan1: d_can@481d0000 { + compatible = "bosch,d_can"; + ti,hwmods = "d_can1"; + reg = <0x481d0000 0x2000 + 0x44e10644 0x4>; + interrupts = <55>; + status = "disabled"; + }; + + timer1: timer@44e31000 { + compatible = "ti,am335x-timer-1ms"; + reg = <0x44e31000 0x400>; + interrupts = <67>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@48040000 { + compatible = "ti,am335x-timer"; + reg = <0x48040000 0x400>; + interrupts = <68>; + ti,hwmods = "timer2"; + }; + + timer3: timer@48042000 { + compatible = "ti,am335x-timer"; + reg = <0x48042000 0x400>; + interrupts = <69>; + ti,hwmods = "timer3"; + }; + + timer4: timer@48044000 { + compatible = "ti,am335x-timer"; + reg = <0x48044000 0x400>; + interrupts = <92>; + ti,hwmods = "timer4"; + ti,timer-pwm; + }; + + timer5: timer@48046000 { + compatible = "ti,am335x-timer"; + reg = <0x48046000 0x400>; + interrupts = <93>; + ti,hwmods = "timer5"; + ti,timer-pwm; + }; + + timer6: timer@48048000 { + compatible = "ti,am335x-timer"; + reg = <0x48048000 0x400>; + interrupts = <94>; + ti,hwmods = "timer6"; + ti,timer-pwm; + }; + + timer7: timer@4804a000 { + compatible = "ti,am335x-timer"; + reg = <0x4804a000 0x400>; + interrupts = <95>; + ti,hwmods = "timer7"; + ti,timer-pwm; + }; + + rtc@44e3e000 { + compatible = "ti,da830-rtc"; + reg = <0x44e3e000 0x1000>; + interrupts = <75 + 76>; + ti,hwmods = "rtc"; + }; + + spi0: spi@48030000 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x48030000 0x400>; + interrupts = <65>; + ti,spi-num-cs = <2>; + ti,hwmods = "spi0"; + status = "disabled"; + }; + + spi1: spi@481a0000 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x481a0000 0x400>; + interrupts = <125>; + ti,spi-num-cs = <2>; + ti,hwmods = "spi1"; + status = "disabled"; + }; + + usb: usb@47400000 { + compatible = "ti,am33xx-usb"; + reg = <0x47400000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + ti,hwmods = "usb_otg_hs"; + status = "disabled"; + + ctrl_mod: control@44e10000 { + compatible = "ti,am335x-usb-ctrl-module"; + reg = <0x44e10620 0x10 + 0x44e10648 0x4>; + reg-names = "phy_ctrl", "wakeup"; + status = "disabled"; + }; + + usb0_phy: usb-phy@47401300 { + compatible = "ti,am335x-usb-phy"; + reg = <0x47401300 0x100>; + reg-names = "phy"; + status = "disabled"; + ti,ctrl_mod = <&ctrl_mod>; + }; + + usb0: usb@47401000 { + compatible = "ti,musb-am33xx"; + status = "disabled"; + reg = <0x47401400 0x400 + 0x47401000 0x200>; + reg-names = "mc", "control"; + + interrupts = <18>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb0_phy>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + usb1_phy: usb-phy@47401b00 { + compatible = "ti,am335x-usb-phy"; + reg = <0x47401b00 0x100>; + reg-names = "phy"; + status = "disabled"; + ti,ctrl_mod = <&ctrl_mod>; + }; + + usb1: usb@47401800 { + compatible = "ti,musb-am33xx"; + status = "disabled"; + reg = <0x47401c00 0x400 + 0x47401800 0x200>; + reg-names = "mc", "control"; + interrupts = <19>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb1_phy>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@07402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + #dma-channels = <30>; + #dma-requests = <256>; + status = "disabled"; + }; + }; + + epwmss0: epwmss@48300000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48300000 0x10>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48300100 0x48300100 0x80 /* ECAP */ + 0x48300180 0x48300180 0x80 /* EQEP */ + 0x48300200 0x48300200 0x80>; /* EHRPWM */ + + ecap0: ecap@48300100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48300100 0x80>; + ti,hwmods = "ecap0"; + status = "disabled"; + }; + + ehrpwm0: ehrpwm@48300200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x80>; + ti,hwmods = "ehrpwm0"; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48302000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48302000 0x10>; + ti,hwmods = "epwmss1"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48302100 0x48302100 0x80 /* ECAP */ + 0x48302180 0x48302180 0x80 /* EQEP */ + 0x48302200 0x48302200 0x80>; /* EHRPWM */ + + ecap1: ecap@48302100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48302100 0x80>; + ti,hwmods = "ecap1"; + status = "disabled"; + }; + + ehrpwm1: ehrpwm@48302200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48302200 0x80>; + ti,hwmods = "ehrpwm1"; + status = "disabled"; + }; + }; + + epwmss2: epwmss@48304000 { + compatible = "ti,am33xx-pwmss"; + reg = <0x48304000 0x10>; + ti,hwmods = "epwmss2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48304100 0x48304100 0x80 /* ECAP */ + 0x48304180 0x48304180 0x80 /* EQEP */ + 0x48304200 0x48304200 0x80>; /* EHRPWM */ + + ecap2: ecap@48304100 { + compatible = "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48304100 0x80>; + ti,hwmods = "ecap2"; + status = "disabled"; + }; + + ehrpwm2: ehrpwm@48304200 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48304200 0x80>; + ti,hwmods = "ehrpwm2"; + status = "disabled"; + }; + }; + + mac: ethernet@4a100000 { + compatible = "ti,cpsw"; + ti,hwmods = "cpgmac0"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + no_bd_ram = <0>; + rx_descs = <64>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0x4a100000 0x800 + 0x4a101200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + /* + * c0_rx_thresh_pend + * c0_rx_pend + * c0_tx_pend + * c0_misc_pend + */ + interrupts = <40 41 42 43>; + ranges; + + davinci_mdio: mdio@4a101000 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + reg = <0x4a101000 0x100>; + }; + + cpsw_emac0: slave@4a100200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@4a100300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + ocmcram: ocmcram@40300000 { + compatible = "ti,am3352-ocmcram"; + reg = <0x40300000 0x10000>; + ti,hwmods = "ocmcram"; + }; + + wkup_m3: wkup_m3@44d00000 { + compatible = "ti,am3353-wkup-m3"; + reg = <0x44d00000 0x4000 /* M3 UMEM */ + 0x44d80000 0x2000>; /* M3 DMEM */ + ti,hwmods = "wkup_m3"; + }; + + elm: elm@48080000 { + compatible = "ti,am3352-elm"; + reg = <0x48080000 0x2000>; + interrupts = <4>; + ti,hwmods = "elm"; + status = "disabled"; + }; + + tscadc: tscadc@44e0d000 { + compatible = "ti,am3359-tscadc"; + reg = <0x44e0d000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <16>; + ti,hwmods = "adc_tsc"; + status = "disabled"; + + tsc { + compatible = "ti,am3359-tsc"; + }; + am335x_adc: adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; }; }; }; diff --git a/arch/arm/dts/cros-ec-keyboard.dtsi b/arch/arm/dts/cros-ec-keyboard.dtsi new file mode 100644 index 0000000000..9c7fb0acae --- /dev/null +++ b/arch/arm/dts/cros-ec-keyboard.dtsi @@ -0,0 +1,105 @@ +/* + * Keyboard dts fragment for devices that use cros-ec-keyboard + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; +}; diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi new file mode 100644 index 0000000000..7de227cc01 --- /dev/null +++ b/arch/arm/dts/exynos4.dtsi @@ -0,0 +1,154 @@ +/* + * Samsung's Exynos4 SoC common device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "skeleton.dtsi" + +/ { + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x10440000 0x1000>; + }; + + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x3c>; + id = <0>; + }; + + serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x3c>; + id = <1>; + }; + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x3c>; + id = <2>; + }; + + serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x3c>; + id = <3>; + }; + + serial@13840000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13840000 0x3c>; + id = <4>; + }; + + i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 56 0>; + }; + + i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <1 57 0>; + }; + + i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <2 58 0>; + }; + + i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <3 59 0>; + }; + + i2c@138a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138a0000 0x100>; + interrupts = <4 60 0>; + }; + + i2c@138b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138b0000 0x100>; + interrupts = <5 61 0>; + }; + + i2c@138c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138c0000 0x100>; + interrupts = <6 62 0>; + }; + + i2c@138d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138d0000 0x100>; + interrupts = <7 63 0>; + }; + + sdhci@12510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12510000 0x1000>; + interrupts = <0 75 0>; + }; + + sdhci@12520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12520000 0x1000>; + interrupts = <0 76 0>; + }; + + sdhci@12530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12530000 0x1000>; + interrupts = <0 77 0>; + }; + + sdhci@12540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12540000 0x1000>; + interrupts = <0 78 0>; + }; + + dwmmc@12550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-dwmmc"; + reg = <0x12550000 0x1000>; + interrupts = <0 131 0>; + }; + +}; diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts new file mode 100644 index 0000000000..3f87761584 --- /dev/null +++ b/arch/arm/dts/exynos4210-origen.dts @@ -0,0 +1,45 @@ +/* + * Samsung's Exynos4210 based Origen board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "skeleton.dtsi" +#include "exynos4210.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210"; + + chosen { + bootargs =""; + }; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc2 = "sdhci@12530000"; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpk2 2 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi new file mode 100644 index 0000000000..f9b61ba8e8 --- /dev/null +++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi @@ -0,0 +1,27 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos4210-pinctrl"; + }; + + pinctrl_1: pinctrl@11000000 { + #address-cells = <1>; + #size-cells = <0>; + gpx0: gpx0 { + reg = <0xc00>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos4210-pinctrl.dtsi b/arch/arm/dts/exynos4210-pinctrl.dtsi new file mode 100644 index 0000000000..bda17f79f4 --- /dev/null +++ b/arch/arm/dts/exynos4210-pinctrl.dtsi @@ -0,0 +1,304 @@ +/* + * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2011-2012 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11400000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe3: gpe3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe4: gpe4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@11000000 { + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/exynos4210-smdkv310.dts b/arch/arm/dts/exynos4210-smdkv310.dts new file mode 100644 index 0000000000..00cad0447d --- /dev/null +++ b/arch/arm/dts/exynos4210-smdkv310.dts @@ -0,0 +1,21 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos4.dtsi" + +/ { + model = "Samsung SMDKV310 on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + }; + +}; diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts new file mode 100644 index 0000000000..36d02df3b0 --- /dev/null +++ b/arch/arm/dts/exynos4210-trats.dts @@ -0,0 +1,120 @@ +/* + * Samsung's Exynos4210 based Trats board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos4210.dtsi" + +/ { + model = "Samsung Trats based on Exynos4210"; + compatible = "samsung,trats", "samsung,exynos4210"; + + config { + samsung,dsim-device-name = "s6e8ax0"; + }; + + aliases { + i2c0 = "/i2c@13860000"; + i2c1 = "/i2c@13870000"; + i2c2 = "/i2c@13880000"; + i2c3 = "/i2c@13890000"; + i2c4 = "/i2c@138a0000"; + i2c5 = "/i2c@138b0000"; + i2c6 = "/i2c@138c0000"; + i2c7 = "/i2c@138d0000"; + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <720>; + samsung,vl-row = <1280>; + samsung,vl-width = <720>; + samsung,vl-height = <1280>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <5>; + samsung,vl-hbpd = <10>; + samsung,vl-hfpd = <10>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <1>; + samsung,vl-vfpd = <13>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,power-on-delay = <30>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <1>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; + + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpk0 2 0>; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpx3 4 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts new file mode 100644 index 0000000000..16948c9342 --- /dev/null +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -0,0 +1,96 @@ +/* + * Samsung's Exynos4210 based Universal C210 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos4210.dtsi" + +/ { + model = "Samsung Universal C210 based on Exynos4210 rev0"; + compatible = "samsung,universal_c210", "samsung,exynos4210"; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpk0 2 0>; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpx3 4 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + soft-spi { + compatible = "u-boot,soft-spi"; + cs-gpio = <&gpy4 3 0>; + sclk-gpio = <&gpy3 1 0>; + mosi-gpio = <&gpy3 3 0>; + miso-gpio = <&gpy3 0 0>; + spi-delay-us = <1>; + #address-cells = <1>; + #size-cells = <0>; + cs@0 { + }; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <480>; + samsung,vl-row = <800>; + samsung,vl-width = <480>; + samsung,vl-height = <800>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <2>; + samsung,vl-hbpd = <16>; + samsung,vl-hfpd = <16>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <8>; + samsung,vl-vfpd = <8>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,pclk_name = <1>; + samsung,sclk_div = <1>; + + samsung,winid = <0>; + samsung,power-on-delay = <10000>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <0>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; +}; diff --git a/arch/arm/dts/exynos4210.dtsi b/arch/arm/dts/exynos4210.dtsi new file mode 100644 index 0000000000..634a5c1dd2 --- /dev/null +++ b/arch/arm/dts/exynos4210.dtsi @@ -0,0 +1,156 @@ +/* + * Samsung's Exynos4210 SoC device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos4.dtsi" +#include "exynos4210-pinctrl.dtsi" +#include "exynos4210-pinctrl-uboot.dtsi" + +/ { + compatible = "samsung,exynos4210"; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + }; + + pd_lcd1: lcd1-power-domain@10023CA0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + }; + + gic: interrupt-controller@10490000 { + cpu-offset = <0x8000>; + }; + + combiner: interrupt-controller@10440000 { + samsung,combiner-nr = <16>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + }; + + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; + clocks = <&clock 3>, <&clock 344>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &gic 0 69 0>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 0 42 0>, + <5 &gic 0 48 0>; + }; + }; + + clock: clock-controller@10030000 { + compatible = "samsung,exynos4210-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x03860000 0x1000>; + }; + + tmu@100C0000 { + compatible = "samsung,exynos4210-tmu"; + interrupt-parent = <&combiner>; + reg = <0x100C0000 0x100>; + interrupts = <2 4>; + clocks = <&clock 383>; + clock-names = "tmu_apbif"; + status = "disabled"; + }; + + g2d@12800000 { + compatible = "samsung,s5pv210-g2d"; + reg = <0x12800000 0x1000>; + interrupts = <0 89 0>; + clocks = <&clock 177>, <&clock 277>; + clock-names = "sclk_fimg2d", "fimg2d"; + status = "disabled"; + }; + + camera { + clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + + fimc_0: fimc@11800000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; + }; + + fimc_1: fimc@11810000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; + }; + + fimc_2: fimc@11820000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,lcd-wb; + }; + + fimc_3: fimc@11830000 { + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,lcd-wb; + }; + }; +}; diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts new file mode 100644 index 0000000000..00a2917596 --- /dev/null +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -0,0 +1,88 @@ +/* + * Odroid-U3/X2 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos4412.dtsi" + +/ { + model = "Odroid based on Exynos4412"; + compatible = "samsung,odroid", "samsung,exynos4412"; + + aliases { + i2c0 = "/i2c@13860000"; + i2c1 = "/i2c@13870000"; + i2c2 = "/i2c@13880000"; + i2c3 = "/i2c@13890000"; + i2c4 = "/i2c@138a0000"; + i2c5 = "/i2c@138b0000"; + i2c6 = "/i2c@138c0000"; + i2c7 = "/i2c@138d0000"; + serial0 = "/serial@13800000"; + console = "/serial@13810000"; + mmc2 = "sdhci@12530000"; + mmc4 = "dwmmc@12550000"; + }; + + i2c@13860000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + max77686_pmic@09 { + compatible = "maxim,max77686_pmic"; + interrupts = <7 0>; + reg = <0x09 0 0>; + #clock-cells = <1>; + }; + }; + + serial@13810000 { + status = "okay"; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpk2 2 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + dwmmc@12550000 { + samsung,bus-width = <8>; + samsung,timing = <2 1 0>; + samsung,removable = <0>; + fifoth_val = <0x203f0040>; + bus_hz = <400000000>; + div = <0x3>; + index = <4>; + }; + + ehci@12580000 { + compatible = "samsung,exynos-ehci"; + reg = <0x12580000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + phy { + compatible = "samsung,exynos-usb-phy"; + reg = <0x125B0000 0x100>; + }; + }; +}; diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts new file mode 100644 index 0000000000..dd238df13f --- /dev/null +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -0,0 +1,446 @@ +/* + * Samsung's Exynos4412 based Trats2 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos4412.dtsi" + +/ { + model = "Samsung Trats2 based on Exynos4412"; + compatible = "samsung,trats2", "samsung,exynos4412"; + + config { + samsung,dsim-device-name = "s6e8ax0"; + }; + + aliases { + i2c0 = "/i2c@13860000"; + i2c1 = "/i2c@13870000"; + i2c2 = "/i2c@13880000"; + i2c3 = "/i2c@13890000"; + i2c4 = "/i2c@138a0000"; + i2c5 = "/i2c@138b0000"; + i2c6 = "/i2c@138c0000"; + i2c7 = "/i2c@138d0000"; + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + mmc4 = "dwmmc@12550000"; + }; + + i2c@138d0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + max77686_pmic@09 { + compatible = "maxim,max77686_pmic"; + interrupts = <7 0>; + reg = <0x09 0 0>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "VALIVE_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo2_reg: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "VM1M2_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo3_reg: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo4_reg: ldo4 { + regulator-compatible = "LDO4"; + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo5_reg: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo6_reg: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "VMPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo7_reg: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "VPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo8_reg: ldo8 { + regulator-compatible = "LDO8"; + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-mem-off; + }; + + ldo9_reg: ldo9 { + regulator-compatible = "LDO9"; + regulator-name = "CAM_ISP_MIPI_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-mem-idle; + }; + + ldo10_reg: ldo10 { + regulator-compatible = "LDO10"; + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-off; + }; + + ldo11_reg: ldo11 { + regulator-compatible = "LDO11"; + regulator-name = "VABB1_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo12_reg: ldo12 { + regulator-compatible = "LDO12"; + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-mem-off; + }; + + ldo13_reg: ldo13 { + regulator-compatible = "LDO13"; + regulator-name = "NFC_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo14_reg: ldo14 { + regulator-compatible = "LDO14"; + regulator-name = "VABB2_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo15_reg: ldo15 { + regulator-compatible = "LDO15"; + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-mem-off; + }; + + ldo16_reg: ldo16 { + regulator-compatible = "LDO16"; + regulator-name = "VHSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-off; + }; + + ldo17_reg: ldo17 { + regulator-compatible = "LDO17"; + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-mem-idle; + }; + + ldo18_reg: ldo18 { + regulator-compatible = "LDO18"; + regulator-name = "CAM_ISP_SEN_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo19_reg: ldo19 { + regulator-compatible = "LDO19"; + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo20_reg: ldo20 { + regulator-compatible = "LDO20"; + regulator-name = "VDDQ_PRE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo21_reg: ldo21 { + regulator-compatible = "LDO21"; + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-mem-idle; + }; + + ldo22_reg: ldo22 { + regulator-compatible = "LDO22"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo23_reg: ldo23 { + regulator-compatible = "LDO23"; + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-mem-idle; + }; + + ldo24_reg: ldo24 { + regulator-compatible = "LDO24"; + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo25_reg: ldo25 { + regulator-compatible = "LDO25"; + regulator-name = "LCD_VCC_3.3V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-mem-idle; + }; + + ldo26_reg: ldo26 { + regulator-compatible = "LDO26"; + regulator-name = "MOTOR_VCC_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-mem-idle; + }; + + buck1_reg: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck2_reg: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck3_reg: buck3 { + regulator-compatible = "BUCK3"; + regulator-name = "vdd_int"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck4_reg: buck4 { + regulator-compatible = "BUCK4"; + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-mem-off; + }; + + buck5_reg: buck5 { + regulator-compatible = "BUCK5"; + regulator-name = "VMEM_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck6_reg: buck6 { + regulator-compatible = "BUCK6"; + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: buck7 { + regulator-compatible = "BUCK7"; + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: buck8 { + regulator-compatible = "BUCK8"; + regulator-name = "VMEM_VDDF_3.0V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-mem-off; + }; + + buck9_reg: buck9 { + regulator-compatible = "BUCK9"; + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-mem-off; + }; + }; + }; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <720>; + samsung,vl-row = <1280>; + samsung,vl-width = <720>; + samsung,vl-height = <1280>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <5>; + samsung,vl-hbpd = <10>; + samsung,vl-hfpd = <10>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <1>; + samsung,vl-vfpd = <13>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <0>; + samsung,power-on-delay = <30>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <1>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; + + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpk0 4 0>; + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpk2 2 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + dwmmc@12550000 { + samsung,bus-width = <8>; + samsung,timing = <2 1 0>; + pwr-gpios = <&gpk0 4 0>; + fifoth_val = <0x203f0040>; + bus_hz = <400000000>; + div = <0x3>; + index = <4>; + }; +}; diff --git a/arch/arm/dts/exynos4412.dtsi b/arch/arm/dts/exynos4412.dtsi new file mode 100644 index 0000000000..87b339c739 --- /dev/null +++ b/arch/arm/dts/exynos4412.dtsi @@ -0,0 +1,38 @@ +/* + * Samsung's Exynos4412 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4412"; + + gic: interrupt-controller@10490000 { + cpu-offset = <0x4000>; + }; + + interrupt-controller@10440000 { + samsung,combiner-nr = <20>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; + }; + +}; diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi new file mode 100644 index 0000000000..c41d07b65f --- /dev/null +++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi @@ -0,0 +1,43 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + gpf0: gpf0 { + reg = <0x180>; + }; + gpj0: gpj0 { + reg = <0x240>; + }; + }; + + pinctrl_1: pinctrl@11000000 { + #address-cells = <1>; + #size-cells = <0>; + gpk0: gpk0 { + reg = <0x40>; + }; + gpm0: gpm0 { + reg = <0x260>; + }; + gpx0: gpx0 { + reg = <0xc00>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + + pinctrl_3: pinctrl@106E0000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos4x12-pinctrl.dtsi b/arch/arm/dts/exynos4x12-pinctrl.dtsi new file mode 100644 index 0000000000..23061351ff --- /dev/null +++ b/arch/arm/dts/exynos4x12-pinctrl.dtsi @@ -0,0 +1,344 @@ +/* + * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11400000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@11000000 { + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@106E0000 { + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/dts/exynos4x12.dtsi b/arch/arm/dts/exynos4x12.dtsi new file mode 100644 index 0000000000..5d58c6eedc --- /dev/null +++ b/arch/arm/dts/exynos4x12.dtsi @@ -0,0 +1,115 @@ +/* + * Samsung's Exynos4x12 SoCs device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as +` * published by the Free Software Foundation. +*/ + +#include "exynos4.dtsi" +#include "exynos4x12-pinctrl.dtsi" +#include "exynos4x12-pinctrl-uboot.dtsi" + +/ { + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + mshc0 = &mshc_0; + }; + + pd_isp: isp-power-domain@10023CA0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + }; + + clock: clock-controller@10030000 { + compatible = "samsung,exynos4412-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + + mct@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>; + clocks = <&clock 3>, <&clock 344>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &combiner 12 5>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 1 12 0>; + }; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x03860000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 0>; + }; + + pinctrl_3: pinctrl@106E0000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x106E0000 0x1000>; + interrupts = <0 72 0>; + }; + + g2d@10800000 { + compatible = "samsung,exynos4212-g2d"; + reg = <0x10800000 0x1000>; + interrupts = <0 89 0>; + clocks = <&clock 177>, <&clock 277>; + clock-names = "sclk_fimg2d", "fimg2d"; + status = "disabled"; + }; + + mshc_0: mmc@12550000 { + compatible = "samsung,exynos4412-dw-mshc"; + reg = <0x12550000 0x1000>; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <0x80>; + clocks = <&clock 301>, <&clock 149>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi new file mode 100644 index 0000000000..238acb80a2 --- /dev/null +++ b/arch/arm/dts/exynos5.dtsi @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors + * SAMSUNG EXYNOS5 SoC device tree source + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "skeleton.dtsi" +#include + +/ { + compatible = "samsung,exynos5"; + + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + sromc@12250000 { + compatible = "samsung,exynos-sromc"; + reg = <0x12250000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + i2c@12c60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C60000 0x100>; + interrupts = <0 56 0>; + }; + + i2c@12c70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C70000 0x100>; + interrupts = <0 57 0>; + }; + + i2c@12c80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C80000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@12c90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C90000 0x100>; + interrupts = <0 59 0>; + }; + + spi@12d20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d20000 0x30>; + interrupts = <0 68 0>; + }; + + spi@12d30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d30000 0x30>; + interrupts = <0 69 0>; + }; + + spi@12d40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d40000 0x30>; + clock-frequency = <50000000>; + interrupts = <0 70 0>; + }; + + spi@131a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x131a0000 0x30>; + interrupts = <0 129 0>; + }; + + spi@131b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x131b0000 0x30>; + interrupts = <0 130 0>; + }; + + ehci@12110000 { + compatible = "samsung,exynos-ehci"; + reg = <0x12110000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos-usb-phy"; + reg = <0x12130000 0x100>; + }; + }; + + tmu@10060000 { + compatible = "samsung,exynos-tmu"; + reg = <0x10060000 0x10000>; + }; + + fimd@14400000 { + compatible = "samsung,exynos-fimd"; + reg = <0x14400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + dp@145b0000 { + compatible = "samsung,exynos5-dp"; + reg = <0x145b0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + xhci0: xhci@12000000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12000000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12100000 0x100>; + }; + }; + + mmc@12200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-dwmmc"; + reg = <0x12200000 0x1000>; + interrupts = <0 75 0>; + }; + + mmc@12210000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-dwmmc"; + reg = <0x12210000 0x1000>; + interrupts = <0 76 0>; + }; + + mmc@12220000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-dwmmc"; + reg = <0x12220000 0x1000>; + interrupts = <0 77 0>; + }; + + mmc@12230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-dwmmc"; + reg = <0x12230000 0x1000>; + interrupts = <0 78 0>; + }; + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + id = <0>; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + id = <1>; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + id = <2>; + }; + + serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + interrupts = <0 54 0>; + u-boot,dm-pre-reloc; + id = <3>; + }; +}; diff --git a/arch/arm/dts/exynos5250-arndale.dts b/arch/arm/dts/exynos5250-arndale.dts new file mode 100644 index 0000000000..21c0a214ea --- /dev/null +++ b/arch/arm/dts/exynos5250-arndale.dts @@ -0,0 +1,47 @@ +/* + * SAMSUNG Arndale board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +/dts-v1/; +#include "exynos5250.dtsi" + +/ { + model = "SAMSUNG Arndale board based on EXYNOS5250"; + compatible = "samsung,arndale", "samsung,exynos5250"; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + serial0 = "/serial@12C20000"; + console = "/serial@12C20000"; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + }; + + mmc@12230000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi new file mode 100644 index 0000000000..7edb0ca290 --- /dev/null +++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi @@ -0,0 +1,40 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + pinctrl_0: pinctrl@11400000 { + #address-cells = <1>; + #size-cells = <0>; + gpc4: gpc4 { + reg = <0x2e0>; + }; + gpx0: gpx0 { + reg = <0xc00>; + }; + }; + + pinctrl_1: pinctrl@13400000 { + #address-cells = <1>; + #size-cells = <0>; + }; + + pinctrl_2: pinctrl@10d10000 { + #address-cells = <1>; + #size-cells = <0>; + gpv2: gpv2 { + reg = <0x060>; + }; + gpv4: gpv4 { + reg = <0xc0>; + }; + }; + + pinctrl_3: pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos5250-pinctrl.dtsi b/arch/arm/dts/exynos5250-pinctrl.dtsi new file mode 100644 index 0000000000..67755a1e08 --- /dev/null +++ b/arch/arm/dts/exynos5250-pinctrl.dtsi @@ -0,0 +1,331 @@ +/* + * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11400000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@13400000 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@10d10000 { + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; +}; diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts similarity index 91% rename from board/samsung/dts/exynos5250-smdk5250.dts rename to arch/arm/dts/exynos5250-smdk5250.dts index 1e94c7f82c..9273562bc5 100644 --- a/board/samsung/dts/exynos5250-smdk5250.dts +++ b/arch/arm/dts/exynos5250-smdk5250.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "exynos5250.dtsi" +#include "exynos5250.dtsi" / { model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; @@ -36,6 +36,7 @@ mmc3 = "/mmc@12230000"; serial0 = "/serial@12C30000"; console = "/serial@12C30000"; + i2s = "/sound@3830000"; }; sromc@12250000 { @@ -49,16 +50,14 @@ }; }; - sound@12d60000 { - samsung,i2s-epll-clock-frequency = <192000000>; - samsung,i2s-sampling-rate = <48000>; - samsung,i2s-bits-per-sample = <16>; - samsung,i2s-channels = <2>; - samsung,i2s-lr-clk-framesize = <256>; - samsung,i2s-bit-clk-framesize = <32>; + sound@3830000 { samsung,codec-type = "wm8994"; }; + sound@12d60000 { + status = "disabled"; + }; + i2c@12c70000 { soundcodec@1a { reg = <0x1a>; @@ -145,4 +144,8 @@ mmc@12230000 { status = "disabled"; }; + + ehci@12110000 { + samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; }; diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts new file mode 100644 index 0000000000..7d8be69d73 --- /dev/null +++ b/arch/arm/dts/exynos5250-snow.dts @@ -0,0 +1,200 @@ +/* + * SAMSUNG Snow board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5250.dtsi" + +/ { + model = "Google Snow"; + compatible = "google,snow", "samsung,exynos5250"; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + mmc0 = "/mmc@12200000"; + mmc1 = "/mmc@12210000"; + mmc2 = "/mmc@12220000"; + mmc3 = "/mmc@12230000"; + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + i2s = "/sound@3830000"; + }; + + i2c4: i2c@12ca0000 { + cros-ec@1e { + reg = <0x1e>; + compatible = "google,cros-ec"; + i2c-max-frequency = <100000>; + u-boot,i2c-offset-len = <0>; + ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; + }; + + power-regulator@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + }; + }; + + spi@12d30000 { + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + compatible = "spi-flash"; + reg = <0>; + }; + }; + + spi@131b0000 { + spi-max-frequency = <1000000>; + spi-deactivate-delay = <100>; + cros_ec: cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-max-frequency = <5000000>; + ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; + optimise-flash-write; + status = "disabled"; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98095"; + codec-enable-gpio = <&gpx1 7 GPIO_ACTIVE_HIGH>; + }; + + sound@12d60000 { + status = "disabled"; + }; + + i2c@12cd0000 { + soundcodec@22 { + reg = <0x22>; + compatible = "maxim,max98095-codec"; + }; + + ptn3460-bridge@20 { + compatible = "nxp,ptn3460"; + reg = <0x20>; + /* + * TODO(sjg@chromium.org): Use GPIOs here + * powerdown-gpio = <&gpy2 5 0>; + * reset-gpio = <&gpx1 5 0>; + * edid-emulation = <5>; + * pinctrl-names = "default"; + * pinctrl-0 = <&ptn3460_gpios>; + */ + }; + }; + + i2c@12c60000 { + pmic@9 { + reg = <0x9>; + compatible = "maxim,max77686_pmic"; + }; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; + + ehci@12110000 { + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1366>; + samsung,vl-row = <768>; + samsung,vl-width = <1366>; + samsung,vl-height = <768>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-hsp; + samsung,vl-vsp; + + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <5>; + samsung,vl-vbpd = <14>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <0>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; + +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index 4fff5e3694..ccbafe9b07 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -1,64 +1,50 @@ /* + * (C) Copyright 2012 SAMSUNG Electronics * SAMSUNG EXYNOS5250 SoC device tree source * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. - * EXYNOS5250 based board files can include this file and provide - * values for board specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, - * additional nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + * SPDX-License-Identifier: GPL-2.0+ + */ -/include/ "skeleton.dtsi" +#include "exynos5.dtsi" +#include "exynos5250-pinctrl.dtsi" +#include "exynos5250-pinctrl-uboot.dtsi" / { - compatible = "samsung,exynos5250"; - - sromc@12250000 { - compatible = "samsung,exynos-sromc"; - reg = <0x12250000 0x20>; - #address-cells = <1>; - #size-cells = <0>; + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 46 0>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; }; - i2c@12c60000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; + pinctrl_1: pinctrl@13400000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; }; - i2c@12c70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; + pinctrl_2: pinctrl@10d10000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x10d10000 0x1000>; + interrupts = <0 50 0>; }; - i2c@12c80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - }; - - i2c@12c90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; + pinctrl_3: pinctrl@03860000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; }; i2c@12ca0000 { @@ -93,143 +79,41 @@ interrupts = <0 63 0>; }; - sound@12d60000 { + sound@3830000 { compatible = "samsung,exynos-sound"; - reg = <0x12d60000 0x20>; - }; - - spi@12d20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d20000 0x30>; - interrupts = <0 68 0>; + reg = <0x3830000 0x50>; + samsung,i2s-epll-clock-frequency = <192000000>; + samsung,i2s-sampling-rate = <48000>; + samsung,i2s-bits-per-sample = <16>; + samsung,i2s-channels = <2>; + samsung,i2s-lr-clk-framesize = <256>; + samsung,i2s-bit-clk-framesize = <32>; + samsung,i2s-id = <0>; }; - spi@12d30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d30000 0x30>; - interrupts = <0 69 0>; + sound@12d60000 { + compatible = "samsung,exynos-sound"; + reg = <0x12d60000 0x20>; + samsung,i2s-epll-clock-frequency = <192000000>; + samsung,i2s-sampling-rate = <48000>; + samsung,i2s-bits-per-sample = <16>; + samsung,i2s-channels = <2>; + samsung,i2s-lr-clk-framesize = <256>; + samsung,i2s-bit-clk-framesize = <32>; + samsung,i2s-id = <1>; }; - spi@12d40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d40000 0x30>; - clock-frequency = <50000000>; - interrupts = <0 70 0>; - }; - spi@131a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x131a0000 0x30>; - interrupts = <0 129 0>; - }; - - spi@131b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x131b0000 0x30>; - interrupts = <0 130 0>; - }; - - ehci@12110000 { - compatible = "samsung,exynos-ehci"; - reg = <0x12110000 0x100>; + xhci@12000000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12000000 0x10000>; #address-cells = <1>; #size-cells = <1>; phy { - compatible = "samsung,exynos-usb-phy"; - reg = <0x12130000 0x100>; + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12100000 0x100>; }; }; - tmu@10060000 { - compatible = "samsung,exynos-tmu"; - reg = <0x10060000 0x10000>; - }; - - fimd@14400000 { - compatible = "samsung,exynos-fimd"; - reg = <0x14400000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - dp@145b0000 { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - mmc@12200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - }; - - mmc@12210000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; - }; - - mmc@12220000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; - }; - - mmc@12230000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12230000 0x1000>; - interrupts = <0 78 0>; - }; - - serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - id = <0>; - }; - - serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; - id = <1>; - }; - - serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; - id = <2>; - }; - - serial@12C30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; - id = <3>; - }; - - gpio: gpio { - }; }; diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts new file mode 100644 index 0000000000..b801de9787 --- /dev/null +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -0,0 +1,160 @@ +/* + * SAMSUNG/GOOGLE Peach-Pit board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "Samsung/Google Peach Pit board based on Exynos5420"; + + compatible = "google,pit-rev#", "google,pit", + "google,peach", "samsung,exynos5420", "samsung,exynos5"; + + config { + google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; + hwid = "PIT TEST A-A 7848"; + lazy-init = <1>; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + pmic = "/i2c@12ca0000"; + }; + + dmc { + mem-manuf = "samsung"; + mem-type = "ddr3"; + clock-frequency = <800000000>; + arm-frequency = <900000000>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* MAX77802 is on i2c bus 4 */ + i2c@12ca0000 { + clock-frequency = <400000>; + power-regulator@9 { + compatible = "maxim,max77802-pmic"; + reg = <0x9>; + }; + }; + + i2c@12cd0000 { /* i2c7 */ + clock-frequency = <100000>; + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98090-codec"; + }; + + edp-lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98090"; + }; + + i2c@12e10000 { /* i2c9 */ + clock-frequency = <400000>; + tpm@20 { + compatible = "infineon,slb9645-tpm"; + reg = <0x20>; + }; + }; + + spi@12d30000 { /* spi1 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + compatible = "spi-flash"; + reg = <0>; + + /* + * A region for the kernel to store a panic event + * which the firmware will add to the log. + */ + elog-panic-event-offset = <0x01e00000 0x100000>; + + elog-shrink-size = <0x400>; + elog-full-threshold = <0xc00>; + }; + }; + + spi@12d40000 { /* spi2 */ + spi-max-frequency = <4000000>; + spi-deactivate-delay = <200>; + cros_ec: cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + spi-frame-header = <0xec>; + ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + }; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; + }; + + xhci@12400000 { + samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1366>; + samsung,vl-row = <768>; + samsung,vl-width = <1366>; + samsung,vl-height = <768>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <40>; + samsung,vl-hfpd = <40>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <10>; + samsung,vl-vfpd = <12>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts new file mode 100644 index 0000000000..6855027389 --- /dev/null +++ b/arch/arm/dts/exynos5420-smdk5420.dts @@ -0,0 +1,148 @@ +/* + * SAMSUNG SMDK5420 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "SAMSUNG SMDK5420 board based on EXYNOS5420"; + compatible = "samsung,smdk5420", "samsung,exynos5"; + + config { + hwid = "smdk5420 TEST A-A 9382"; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* s2mps11 is on i2c bus 4 */ + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + pmic@66 { + reg = <0x66>; + compatible = "samsung,s2mps11-pmic"; + }; + }; + + spi@12d20000 { /* spi0 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + }; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <2560>; + samsung,vl-row = <1600>; + samsung,vl-width = <2560>; + samsung,vl-height = <1600>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <37>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; + + sound@3830000 { + samsung,codec-type = "wm8994"; + }; + + i2c@12c70000 { + soundcodec@1a { + reg = <0x1a>; + compatible = "wolfson,wm8994-codec"; + }; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; + + fimd@14400000 { + /* sysmmu is not used in U-Boot */ + samsung,disable-sysmmu; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; + + dmc { + mem-type = "ddr3"; + }; + + xhci1: xhci@12400000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12500000 0x100>; + }; + }; +}; diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000000..8f4663733c --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,49 @@ +/* + * Odroid XU3 device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "Odroid XU3 based on EXYNOS5422"; + compatible = "samsung,odroidxu3", "samsung,exynos5"; + + aliases { + serial0 = "/serial@12C00000"; + console = "/serial@12C20000"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000 + 0x80000000 0x10000000 + 0x90000000 0x10000000 + 0xa0000000 0x10000000 + 0xb0000000 0xea00000>; + }; + + ehci@12110000 { + samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; + + serial@12C20000 { + status="okay"; + }; + + mmc@12200000 { + fifoth_val = <0x201f0020>; + }; + + mmc@12220000 { + fifoth_val = <0x201f0020>; + }; +}; diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi new file mode 100644 index 0000000000..5a86211d4a --- /dev/null +++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi @@ -0,0 +1,40 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/{ + /* + * Replicate the ordering of arch/arm/include/asm/arch-exynos/gpio.h + * TODO(sjg@chromium.org): This ordering ceases to matter once GPIO + * numbers are not needed in U-Boot for exynos. + */ + pinctrl@14010000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@13400000 { + #address-cells = <1>; + #size-cells = <0>; + gpy7 { + }; + + gpx0 { + reg = <0xc00>; + }; + }; + pinctrl@13410000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@14000000 { + #address-cells = <1>; + #size-cells = <0>; + }; + pinctrl@03860000 { + #address-cells = <1>; + #size-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/exynos54xx-pinctrl.dtsi b/arch/arm/dts/exynos54xx-pinctrl.dtsi new file mode 100644 index 0000000000..775d956a5f --- /dev/null +++ b/arch/arm/dts/exynos54xx-pinctrl.dtsi @@ -0,0 +1,305 @@ +/* + * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos54xx-pinctrl-uboot.dtsi" + +/ { + pinctrl@13400000 { + gpy7: gpy7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@13410000 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + }; + + pinctrl@14000000 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@14010000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi new file mode 100644 index 0000000000..916cf3a5b6 --- /dev/null +++ b/arch/arm/dts/exynos54xx.dtsi @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2013 SAMSUNG Electronics + * SAMSUNG EXYNOS5420 SoC device tree source + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "exynos5.dtsi" +#include "exynos54xx-pinctrl.dtsi" + +/ { + config { + machine-arch-id = <4151>; + }; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + i2c8 = "/i2c@12e00000"; + i2c9 = "/i2c@12e10000"; + i2c10 = "/i2c@12e20000"; + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + mmc0 = "/mmc@12200000"; + mmc1 = "/mmc@12210000"; + mmc2 = "/mmc@12220000"; + xhci0 = "/xhci@12000000"; + xhci1 = "/xhci@12400000"; + }; + + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CA0000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@12cb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CB0000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@12cc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CC0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@12cd0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CD0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@12e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E00000 0x100>; + interrupts = <0 87 0>; + }; + + i2c@12e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E10000 0x100>; + interrupts = <0 88 0>; + }; + + i2c@12e20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E20000 0x100>; + interrupts = <0 203 0>; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; + + fimdm0_sysmmu@0x14640000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x14640000 0x100>; + }; + + fimdm1_sysmmu@0x14680000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x14680000 0x100>; + }; + + pinctrl_0: pinctrl@13400000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_1: pinctrl@13410000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13410000 0x1000>; + interrupts = <0 78 0>; + }; + + pinctrl_2: pinctrl@14000000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14000000 0x1000>; + interrupts = <0 46 0>; + }; + + pinctrl_3: pinctrl@14010000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14010000 0x1000>; + interrupts = <0 50 0>; + }; + + pinctrl_4: pinctrl@03860000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; + }; + + fimd@14400000 { + /* sysmmu is not used in U-Boot */ + samsung,disable-sysmmu; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; + + dmc { + mem-type = "ddr3"; + }; + + xhci1: xhci@12400000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12500000 0x100>; + }; + }; +}; diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts new file mode 100644 index 0000000000..e4bc100995 --- /dev/null +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -0,0 +1,154 @@ +/* + * SAMSUNG/GOOGLE Peach-Pit board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "Samsung/Google Peach Pi board based on Exynos5800"; + + compatible = "google,pit-rev#", "google,pit", + "google,peach", "samsung,exynos5800", "samsung,exynos5"; + + config { + google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; + hwid = "PIT TEST A-A 7848"; + lazy-init = <1>; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + pmic = "/i2c@12ca0000"; + }; + + dmc { + mem-manuf = "samsung"; + mem-type = "ddr3"; + clock-frequency = <800000000>; + arm-frequency = <900000000>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* MAX77802 is on i2c bus 4 */ + i2c@12ca0000 { + clock-frequency = <400000>; + power-regulator@9 { + compatible = "maxim,max77802-pmic"; + reg = <0x9>; + }; + }; + + i2c@12cd0000 { /* i2c7 */ + clock-frequency = <100000>; + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98090-codec"; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98090"; + }; + + i2c@12e10000 { /* i2c9 */ + clock-frequency = <400000>; + tpm@20 { + compatible = "infineon,slb9645-tpm"; + reg = <0x20>; + }; + }; + + spi@12d30000 { /* spi1 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + + /* + * A region for the kernel to store a panic event + * which the firmware will add to the log. + */ + elog-panic-event-offset = <0x01e00000 0x100000>; + + elog-shrink-size = <0x400>; + elog-full-threshold = <0xc00>; + }; + }; + + spi@12d40000 { /* spi2 */ + spi-max-frequency = <4000000>; + spi-deactivate-delay = <200>; + cros_ec: cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + spi-frame-header = <0xec>; + ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + }; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; + }; + + xhci@12400000 { + samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1920>; + samsung,vl-row = <1080>; + samsung,vl-width = <1920>; + samsung,vl-height = <1080>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <80>; + samsung,vl-hbpd = <172>; + samsung,vl-hfpd = <60>; + samsung,vl-vspw = <10>; + samsung,vl-vbpd = <25>; + samsung,vl-vfpd = <10>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/include/dt-bindings b/arch/arm/dts/include/dt-bindings new file mode 120000 index 0000000000..0cecb3d080 --- /dev/null +++ b/arch/arm/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings \ No newline at end of file diff --git a/arch/arm/dts/s5pc100-pinctrl.dtsi b/arch/arm/dts/s5pc100-pinctrl.dtsi new file mode 100644 index 0000000000..bd9f97c97b --- /dev/null +++ b/arch/arm/dts/s5pc100-pinctrl.dtsi @@ -0,0 +1,180 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/ { + pinctrl@e0300000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc: gpc { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd: gpd { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpi: gpi { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj3: gpj3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl3: gpl3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl4: gpl4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph2: gph2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph3: gph3 { + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/s5pc110-pinctrl.dtsi b/arch/arm/dts/s5pc110-pinctrl.dtsi new file mode 100644 index 0000000000..d21b6ab756 --- /dev/null +++ b/arch/arm/dts/s5pc110-pinctrl.dtsi @@ -0,0 +1,273 @@ +/* + * U-Boot additions to enable a generic Exynos GPIO driver + * + * Copyright (c) 2014 Google, Inc + */ + +/ { + pinctrl@e0200000 { + #address-cells = <1>; + #size-cells = <0>; + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpi: gpi { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj3: gpj3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp01: gpmp01 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp02: gpmp02 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp03: gpmp03 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp04: gpmp04 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp05: gpmp05 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp06: gpmp06 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp07: gpmp07 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp10: gpmp10 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp11: gpmp11 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp12: gpmp12 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp13: gpmp13 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp14: gpmp14 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp15: gpmp15 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp16: gpmp16 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp17: gpmp17 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp18: gpmp18 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp20: gpmp20 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp21: gpmp21 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp22: gpmp22 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp23: gpmp23 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp24: gpmp24 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp25: gpmp25 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp26: gpmp26 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp27: gpmp27 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpmp28: gpmp28 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph0: gph0 { + reg = <0xc00>; + gpio-controller; + #gpio-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph2: gph2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gph3: gph3 { + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts new file mode 100644 index 0000000000..7bbfe591cd --- /dev/null +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -0,0 +1,35 @@ +/* + * Samsung's S5PC110-based Goni board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" +#include "s5pc110-pinctrl.dtsi" + +/ { + model = "Samsung Goni based on S5PC110"; + compatible = "samsung,goni", "samsung,s5pc110"; + + aliases { + serial2 = "/serial@e2900800"; + console = "/serial@e2900800"; + pinctrl0 = &pinctrl0; + }; + + pinctrl0: pinctrl@e0200000 { + compatible = "samsung,s5pc110-pinctrl"; + reg = <0xe0200000 0x1000>; + }; + + serial@e2900800 { + compatible = "samsung,exynos4210-uart"; + reg = <0xe2900800 0x400>; + id = <2>; + }; + +}; diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts new file mode 100644 index 0000000000..95f15ed48d --- /dev/null +++ b/arch/arm/dts/s5pc1xx-smdkc100.dts @@ -0,0 +1,36 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" +#include "s5pc100-pinctrl.dtsi" + +/ { + model = "Samsung SMDKC100 based on S5PC100"; + compatible = "samsung,smdkc100", "samsung,s5pc100"; + + aliases { + serial0 = "/serial@ec000000"; + console = "/serial@ec000000"; + pinctrl0 = &pinctrl0; + }; + + pinctrl0: pinctrl@e0300000 { + compatible = "samsung,s5pc100-pinctrl"; + reg = <0xe0200000 0x1000>; + }; + + serial@ec000000 { + compatible = "samsung,exynos4210-uart"; + reg = <0xec000000 0x100>; + interrupts = <0 51 0>; + id = <0>; + }; + +}; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi new file mode 100644 index 0000000000..bf791c5dde --- /dev/null +++ b/arch/arm/dts/socfpga.dtsi @@ -0,0 +1,787 @@ +/* + * Copyright (C) 2012 Altera + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "skeleton.dtsi" +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@fffed000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffed000 0x1000>, + <0xfffec100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffe01000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffe01000 0x1000>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + status = "disabled"; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + reg = <0x40>; + + mpuclk: mpuclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe0 0 9>; + reg = <0x48>; + }; + + mainclk: mainclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe4 0 9>; + reg = <0x4C>; + }; + + dbg_base_clk: dbg_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe8 0 9>; + reg = <0x50>; + }; + + main_qspi_clk: main_qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x54>; + }; + + main_nand_sdmmc_clk: main_nand_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x58>; + }; + + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x5C>; + }; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; + reg = <0x80>; + + emac0_clk: emac0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x88>; + }; + + emac1_clk: emac1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x8C>; + }; + + per_qspi_clk: per_qsi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x90>; + }; + + per_nand_mmc_clk: per_nand_mmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x94>; + }; + + per_base_clk: per_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x98>; + }; + + h2f_usr1_clk: h2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x9C>; + }; + }; + + sdram_pll: sdram_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; + reg = <0xC0>; + + ddr_dqs_clk: ddr_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xC8>; + }; + + ddr_2x_dqs_clk: ddr_2x_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xCC>; + }; + + ddr_dq_clk: ddr_dq_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD0>; + }; + + h2f_usr2_clk: h2f_usr2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD4>; + }; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mainclk>; + fixed-divider = <1>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + h2f_user0_clk: h2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + h2f_user1_clk: h2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + clk-phase = <0 135>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; + }; + }; + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac0_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 2>; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac1_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + gpio0: gpio@ff708000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff708000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 164 4>; + }; + }; + + gpio1: gpio@ff709000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff709000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 165 4>; + }; + }; + + gpio2: gpio@ff70a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff70a000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 166 4>; + }; + }; + + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + + L2: l2-cache@fffef000 { + compatible = "arm,pl310-cache"; + reg = <0xfffef000 0x1000>; + interrupts = <0 38 0x04>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; + }; + + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + + qspi: spi@ff705000 { + compatible = "cadence,qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + ext-decoder = <0>; /* external decoder */ + num-cs = <4>; + fifo-depth = <128>; + bus-num = <2>; + status = "disabled"; + }; + + spi0: spi@fff00000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff00000 0x1000>; + interrupts = <0 154 4>; + num-cs = <4>; + bus-num = <0>; + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&per_base_clk>; + status = "disabled"; + }; + + spi1: spi@fff01000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff01000 0x1000>; + interrupts = <0 156 4>; + num-cs = <4>; + bus-num = <1>; + tx-dma-channel = <&pdma 20>; + rx-dma-channel = <&pdma 21>; + clocks = <&per_base_clk>; + status = "disabled"; + }; + + /* Local timer */ + timer@fffec600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfffec600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc08000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 167 4>; + reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer1: timer1@ffc09000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 168 4>; + reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 169 4>; + reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + timer3: timer3@ffd01000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x1000>; + interrupts = <0 162 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + uart1: serial1@ffc03000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc03000 0x1000>; + interrupts = <0 163 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd02000 { + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd03000 { + compatible = "snps,dw-wdt"; + reg = <0xffd03000 0x1000>; + interrupts = <0 172 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi new file mode 100644 index 0000000000..234a901205 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: dwmmc0@ff704000 { + num-slots = <1>; + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + ethernet@ff702000 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + status = "okay"; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts new file mode 100644 index 0000000000..ea30483e52 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "EBV SOCrates"; + compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts new file mode 100644 index 0000000000..f7cc8e7a09 --- /dev/null +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts @@ -0,0 +1,177 @@ +/* + * Copyright 2014 Zoltan HERPAI + * Zoltan HERPAI + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "LinkSprite pcDuino3"; + compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; + + chosen { + stdout-path = &uart0; + }; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + ahci_pwr_pin_a: ahci_pwr_pin@0 { + allwinner,pins = "PH2"; + }; + + led_pins_pcduino3: led_pins@0 { + allwinner,pins = "PH15", "PH16"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + key_pins_pcduino3: key_pins@0 { + allwinner,pins = "PH17", "PH18", "PH19"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_pcduino3>; + + tx { + label = "pcduino3:green:tx"; + gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; + }; + + rx { + label = "pcduino3:green:rx"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_pcduino3>; + #address-cells = <1>; + #size-cells = <0>; + button@0 { + label = "Key Back"; + linux,code = ; + gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; + }; + button@1 { + label = "Key Home"; + linux,code = ; + gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; + }; + button@2 { + label = "Key Menu"; + linux,code = ; + gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; + + reg_ahci_5v: ahci-5v { + gpio = <&pio 7 2 0>; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi new file mode 100644 index 0000000000..4011628c73 --- /dev/null +++ b/arch/arm/dts/sun7i-a20.dtsi @@ -0,0 +1,988 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + ethernet0 = &gmac; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + interrupts = <0 120 4>, + <0 121 4>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + pll4: clk@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-pll4-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + + pll5: clk@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + + pll8: clk@01c20040 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-pll4-clk"; + reg = <0x01c20040 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8"; + }; + + cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; + clock-output-names = "cpu"; + }; + + axi: axi@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb: ahb@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>; + clock-output-names = "ahb"; + }; + + ahb_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun7i-a20-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-output-names = "ahb_usb0", "ahb_ehci0", + "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", + "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", + "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", + "ahb_nand", "ahb_sdram", "ahb_ace", + "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", + "ahb_spi2", "ahb_spi3", "ahb_sata", + "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", + "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", + "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", + "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", + "ahb_de_fe1", "ahb_gmac", "ahb_mp", + "ahb_mali"; + }; + + apb0: apb0@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + clock-output-names = "apb0"; + }; + + apb0_gates: clk@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun7i-a20-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-output-names = "apb0_codec", "apb0_spdif", + "apb0_ac97", "apb0_iis0", "apb0_iis1", + "apb0_pio", "apb0_ir0", "apb0_ir1", + "apb0_iis2", "apb0_keypad"; + }; + + apb1_mux: apb1_mux@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1_mux"; + }; + + apb1: apb1@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&apb1_mux>; + clock-output-names = "apb1"; + }; + + apb1_gates: clk@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun7i-a20-apb1-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_i2c3", "apb1_can", + "apb1_scr", "apb1_ps20", "apb1_ps21", + "apb1_i2c4", "apb1_uart0", "apb1_uart1", + "apb1_uart2", "apb1_uart3", "apb1_uart4", + "apb1_uart5", "apb1_uart6", "apb1_uart7"; + }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk@01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc3"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + pata_clk: clk@01c200ac { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200ac 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "pata"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + ir1_clk: clk@01c200b4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200b4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir1"; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + }; + + spi3_clk: clk@01c200d4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200d4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi3"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; + clock-output-names = "mbus"; + }; + + /* + * The following two are dummy clocks, placeholders used in the gmac_tx + * clock. The gmac driver will choose one parent depending on the PHY + * interface mode, using clk_set_rate auto-reparenting. + * The actual TX clock rate is not controlled by the gmac_tx clock. + */ + mii_phy_tx_clk: clk@2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: clk@3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@01c20164 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c20164 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + + /* + * Dummy clock used by output clocks + */ + osc24M_32k: clk@1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <750>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc24M_32k"; + }; + + clk_out_a: clk@01c201f0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f0 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_a"; + }; + + clk_out_b: clk@01c201f4 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f4 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_b"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nmi_intc: interrupt-controller@01c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = <0 0 4>; + }; + + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <0 10 4>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <0 11 4>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac: ethernet@01c0b000 { + compatible = "allwinner,sun4i-a10-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <0 55 4>; + clocks = <&ahb_gates 17>; + status = "disabled"; + }; + + mdio@01c0b080 { + compatible = "allwinner,sun4i-a10-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 32 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 33 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 34 4>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 35 4>; + status = "disabled"; + }; + + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun7i-a20-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; + reg-names = "phy_ctrl", "pmu1", "pmu2"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>, <&usb_clk 2>; + reset-names = "usb1_reset", "usb2_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <0 39 4>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <0 64 4>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <0 12 4>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@01c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <0 56 4>; + clocks = <&pll6 0>, <&ahb_gates 25>; + status = "disabled"; + }; + + ehci1: usb@01c1c000 { + compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <0 40 4>; + clocks = <&ahb_gates 3>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1c400 { + compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <0 65 4>; + clocks = <&usb_clk 7>, <&ahb_gates 4>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + spi3: spi@01c1f000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <0 50 4>; + clocks = <&ahb_gates 23>, <&spi3_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun7i-a20-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <0 28 4>; + clocks = <&apb0_gates 5>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #size-cells = <0>; + #gpio-cells = <3>; + + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PB22", "PB23"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart2_pins_a: uart2@0 { + allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,function = "uart2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart6_pins_a: uart6@0 { + allwinner,pins = "PI12", "PI13"; + allwinner,function = "uart6"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart7_pins_a: uart7@0 { + allwinner,pins = "PI20", "PI21"; + allwinner,function = "uart7"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB18", "PB19"; + allwinner,function = "i2c1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB20", "PB21"; + allwinner,function = "i2c2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + emac_pins_a: emac0@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "emac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + clk_out_a_pins_a: clk_out_a@0 { + allwinner,pins = "PI12"; + allwinner,function = "clk_out_a"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + clk_out_b_pins_a: clk_out_b@0 { + allwinner,pins = "PI13"; + allwinner,function = "clk_out_b"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_pins_mii_a: gmac_mii@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "gmac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_pins_rgmii_a: gmac_rgmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA10", + "PA11", "PA12", "PA13", + "PA15", "PA16"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + allwinner,drive = <3>; + allwinner,pull = <0>; + }; + + spi1_pins_a: spi1@0 { + allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,function = "spi1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + spi2_pins_a: spi2@0 { + allwinner,pins = "PC19", "PC20", "PC21", "PC22"; + allwinner,function = "spi2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc3_pins_a: mmc3@0 { + allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; + allwinner,function = "mmc3"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + ir0_pins_a: ir0@0 { + allwinner,pins = "PB3","PB4"; + allwinner,function = "ir0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + ir1_pins_a: ir1@0 { + allwinner,pins = "PB22","PB23"; + allwinner,function = "ir1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <0 22 4>, + <0 23 4>, + <0 24 4>, + <0 25 4>, + <0 67 4>, + <0 68 4>; + clocks = <&osc24M>; + }; + + wdt: watchdog@01c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + + rtc: rtc@01c20d00 { + compatible = "allwinner,sun7i-a20-rtc"; + reg = <0x01c20d00 0x20>; + interrupts = <0 24 4>; + }; + + pwm: pwm@01c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir0: ir@01c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 6>, <&ir0_clk>; + clock-names = "apb", "ir"; + interrupts = <0 5 4>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + ir1: ir@01c21c00 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 7>, <&ir1_clk>; + clock-names = "apb", "ir"; + interrupts = <0 6 4>; + reg = <0x01c21c00 0x40>; + status = "disabled"; + }; + + sid: eeprom@01c23800 { + compatible = "allwinner,sun7i-a20-sid"; + reg = <0x01c23800 0x200>; + }; + + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-a10-ts"; + reg = <0x01c25000 0x100>; + interrupts = <0 29 4>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <0 1 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 16>; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <0 2 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 17>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <0 3 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 18>; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <0 4 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 19>; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <0 17 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 20>; + status = "disabled"; + }; + + uart5: serial@01c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <0 18 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 21>; + status = "disabled"; + }; + + uart6: serial@01c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = <0 19 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 22>; + status = "disabled"; + }; + + uart7: serial@01c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = <0 20 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 23>; + status = "disabled"; + }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <0 7 4>; + clocks = <&apb1_gates 0>; + clock-frequency = <100000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <0 8 4>; + clocks = <&apb1_gates 1>; + clock-frequency = <100000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <0 9 4>; + clocks = <&apb1_gates 2>; + clock-frequency = <100000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@01c2b800 { + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = <0 88 4>; + clocks = <&apb1_gates 3>; + clock-frequency = <100000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@01c2c000 { + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + reg = <0x01c2c000 0x400>; + interrupts = <0 89 4>; + clocks = <&apb1_gates 15>; + clock-frequency = <100000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac: ethernet@01c50000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x01c50000 0x10000>; + interrupts = <0 85 4>; + interrupt-names = "macirq"; + clocks = <&ahb_gates 49>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + hstimer@01c60000 { + compatible = "allwinner,sun7i-a20-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <0 81 4>, + <0 82 4>, + <0 83 4>, + <0 84 4>; + clocks = <&ahb_gates 28>; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; + }; +}; diff --git a/arch/arm/dts/sunxi-common-regulators.dtsi b/arch/arm/dts/sunxi-common-regulators.dtsi new file mode 100644 index 0000000000..3d021efd1a --- /dev/null +++ b/arch/arm/dts/sunxi-common-regulators.dtsi @@ -0,0 +1,89 @@ +/* + * sunxi boards common regulator (ahci target power supply, usb-vbus) code + * + * Copyright 2014 - Hans de Goede + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + soc@01c00000 { + pio: pinctrl@01c20800 { + ahci_pwr_pin_a: ahci_pwr_pin@0 { + allwinner,pins = "PB8"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + usb1_vbus_pin_a: usb1_vbus_pin@0 { + allwinner,pins = "PH6"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + usb2_vbus_pin_a: usb2_vbus_pin@0 { + allwinner,pins = "PH3"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + }; + + reg_ahci_5v: ahci-5v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&ahci_pwr_pin_a>; + regulator-name = "ahci-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 1 8 0>; + status = "disabled"; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_a>; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 6 0>; + status = "disabled"; + }; + + reg_usb2_vbus: usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_pin_a>; + regulator-name = "usb2-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 3 0>; + status = "disabled"; + }; + + reg_vcc3v0: vcc3v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts similarity index 86% rename from board/nvidia/dts/tegra114-dalmore.dts rename to arch/arm/dts/tegra114-dalmore.dts index 435c01e9f6..51ff266d76 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/arch/arm/dts/tegra114-dalmore.dts @@ -6,6 +6,10 @@ model = "NVIDIA Dalmore"; compatible = "nvidia,dalmore", "nvidia,tegra114"; + chosen { + stdout-path = &uartd; + }; + aliases { i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; @@ -53,7 +57,7 @@ }; sdhci@78000400 { - cd-gpios = <&gpio 170 1>; /* gpio PV2 */ + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; bus-width = <4>; status = "okay"; }; @@ -64,8 +68,7 @@ }; usb@7d008000 { - /* SPDIF_IN: USB_VBUS_EN1 */ - nvidia,vbus-gpio = <&gpio 86 0>; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; status = "okay"; }; }; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 626cc3c982..88bdc49045 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -1,3 +1,7 @@ +#include +#include +#include + #include "skeleton.dtsi" / { @@ -46,17 +50,17 @@ 0 143 0x04>; }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04>; + interrupts = , + , + , + , + , + , + , + ; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; @@ -113,6 +117,58 @@ status = "disabled"; }; + uarta: serial@70006000 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; @@ -139,7 +195,7 @@ spi@7000d800 { compatible = "nvidia,tegra114-spi"; - reg = <0x7000d480 0x200>; + reg = <0x7000d800 0x200>; interrupts = <0 83 0x04>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts new file mode 100644 index 0000000000..e7b66d81a4 --- /dev/null +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -0,0 +1,468 @@ +/dts-v1/; + +#include "tegra124.dtsi" + +/ { + model = "NVIDIA Jetson TK1"; + compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0400"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000da00"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + pcie-controller@01003000 { + status = "okay"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-supply = <&vdd_3v3_lp0>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + vddio-pex-ctl-supply = <&vdd_3v3_lp0>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* Expansion PWR_I2C_*, on-board components */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1_2_4_7 { + pins = "gpio1", "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_5_6 { + pins = "gpio3", "gpio5", "gpio6"; + bias-high-impedance; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + avdd_1v05_run: ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.05V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + ldo4 { + regulator-name = "+2.8V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+3.3V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + i2c@7000d100 { + status = "okay"; + clock-frequency = <400000>; + }; + + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + padctl@7009f000 { + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + + padctl_default: pinmux { + usb3 { + nvidia,lanes = "pcie-0", "pcie-1"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; + + pcie { + nvidia,lanes = "pcie-2", "pcie-3", + "pcie-4"; + nvidia,function = "pcie"; + nvidia,iddq = <0>; + }; + + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; + }; + }; + }; + + sdhci@700b0400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + }; + + usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+USB0_VBUS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + /* Molex power connector */ + vdd_5v0_sata: regulator@13 { + compatible = "regulator-fixed"; + reg = <13>; + regulator-name = "+5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_12v0_sata: regulator@14 { + compatible = "regulator-fixed"; + reg = <14>; + regulator-name = "+12V_SATA"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + }; +}; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts new file mode 100644 index 0000000000..c1f35a07bd --- /dev/null +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -0,0 +1,365 @@ +/dts-v1/; + +#include +#include "tegra124.dtsi" + +/ { + model = "Acer Chromebook 13 CB5-311"; + compatible = "google,nyan-big", "nvidia,tegra124"; + + aliases { + console = &uarta; + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + i2c5 = "/i2c@7000d100"; + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0400"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000da00"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d008000"; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; + + serial@70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + }; + }; + + spi@7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = ; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@70030000 { + status = "okay"; + }; + + sdhci@700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + non-removable; + }; + + sdhci@700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + }; + + sdhci@700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + ahub@70300000 { + i2s@70301100 { + status = "okay"; + }; + }; + + usb@7d000000 { /* Rear external USB port. */ + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + usb@7d004000 { /* Internal webcam. */ + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + }; + + usb@7d008000 { /* Left external USB port. */ + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = ; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <30>; + gpio-key,wakeup; + }; + }; + + panel: panel { + compatible = "auo,b133xtn01"; + + backlight = <&backlight>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090"; + nvidia,model = "Acer Chromebook 13"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts new file mode 100644 index 0000000000..9e93cf90c7 --- /dev/null +++ b/arch/arm/dts/tegra124-venice2.dts @@ -0,0 +1,96 @@ +/dts-v1/; + +#include "tegra124.dtsi" + +/ { + model = "NVIDIA Venice2"; + compatible = "nvidia,venice2", "nvidia,tegra124"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + i2c5 = "/i2c@7000d100"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0400"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000da00"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d100 { + status = "okay"; + clock-frequency = <400000>; + }; + + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + sdhci@700b0400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + }; + + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + }; + + usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi new file mode 100644 index 0000000000..9fa141d8fe --- /dev/null +++ b/arch/arm/dts/tegra124.dtsi @@ -0,0 +1,522 @@ +#include +#include +#include +#include +#include + +#include "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra124"; + interrupt-parent = <&gic>; + + pcie-controller@01003000 { + compatible = "nvidia,tegra124-pcie"; + device_type = "pci"; + reg = <0x01003000 0x00000800 /* PADS registers */ + 0x01003800 0x00000800 /* AFI registers */ + 0x02000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_PLL_E>, + <&tegra_car TEGRA124_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; + phy-names = "pcie"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + + gic: interrupt-controller@50041000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50041000 0x1000>, + <0x50042000 0x2000>, + <0x50044000 0x2000>, + <0x50046000 0x2000>; + interrupts = ; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + apbdma: dma@60020000 { + compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; + reg = <0x60020000 0x1400>; + interrupts = <0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04 + 0 128 0x04 + 0 129 0x04 + 0 130 0x04 + 0 131 0x04 + 0 132 0x04 + 0 133 0x04 + 0 134 0x04 + 0 135 0x04 + 0 136 0x04 + 0 137 0x04 + 0 138 0x04 + 0 139 0x04 + 0 140 0x04 + 0 141 0x04 + 0 142 0x04 + 0 143 0x04>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 12>; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <0 84 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 54>; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <0 92 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 67>; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = <0 120 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 103>; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 47>; + status = "disabled"; + }; + + i2c@7000d100 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d100 0x100>; + interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 47>; + status = "disabled"; + }; + + uarta: serial@70006000 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uarte: serial@70006400 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pwm: pwm@7000a000 { + compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA124_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + spi@7000d400 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = <0 59 0x04>; + nvidia,dma-request-selector = <&apbdma 15>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 41>; + }; + + spi@7000d600 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 44>; + }; + + spi@7000d800 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d800 0x200>; + interrupts = <0 83 0x04>; + nvidia,dma-request-selector = <&apbdma 17>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 46>; + }; + + spi@7000da00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = <0 93 0x04>; + nvidia,dma-request-selector = <&apbdma 18>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 68>; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = <0 94 0x04>; + nvidia,dma-request-selector = <&apbdma 27>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 104>; + }; + + spi@7000de00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = <0 79 0x04>; + nvidia,dma-request-selector = <&apbdma 28>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 105>; + }; + + padctl: padctl@7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x7009f000 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + #phy-cells = <1>; + }; + + sdhci@700b0000 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = <0 14 0x04>; + clocks = <&tegra_car 14>; + status = "disabled"; + }; + + sdhci@700b0200 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0200 0x200>; + interrupts = <0 15 0x04>; + clocks = <&tegra_car 9>; + status = "disabled"; + }; + + sdhci@700b0400 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0400 0x200>; + interrupts = <0 19 0x04>; + clocks = <&tegra_car 69>; + status = "disabled"; + }; + + sdhci@700b0600 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0600 0x200>; + interrupts = <0 31 0x04>; + clocks = <&tegra_car 15>; + status = "disabled"; + }; + + ahub@70300000 { + compatible = "nvidia,tegra124-ahub"; + reg = <0x70300000 0x200>, + <0x70300800 0x800>, + <0x70300200 0x600>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, + <&tegra_car TEGRA124_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 185>, /* amx1 */ + <&tegra_car 154>, /* adx */ + <&tegra_car 180>, /* adx1 */ + <&tegra_car 186>, /* afc0 */ + <&tegra_car 187>, /* afc1 */ + <&tegra_car 188>, /* afc2 */ + <&tegra_car 189>, /* afc3 */ + <&tegra_car 190>, /* afc4 */ + <&tegra_car 191>; /* afc5 */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif", "amx", "amx1", "adx", "adx1", + "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70301000 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301000 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA124_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70301100 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301100 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA124_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70301200 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301200 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA124_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70301300 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301300 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA124_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70301400 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301400 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA124_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; + }; + + usb@7d000000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = < 52 >; + phy_type = "utmi"; + clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + status = "disabled"; + }; + + usb@7d004000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d004000 0x4000>; + interrupts = < 53 >; + phy_type = "hsic"; + clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = < 129 >; + phy_type = "utmi"; + clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri_t20_iris.dts new file mode 100644 index 0000000000..3131b9201b --- /dev/null +++ b/arch/arm/dts/tegra20-colibri_t20_iris.dts @@ -0,0 +1,49 @@ +/dts-v1/; + +#include "tegra20.dtsi" + +/ { + model = "Toradex Colibri T20"; + compatible = "toradex,t20", "nvidia,tegra20"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + usb2 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; + }; + + usb@c5000000 { + dr_mode = "otg"; + }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; + }; + + usb@c5008000 { + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + nvidia,width = <8>; + nvidia,timing = <15 100 25 80 25 10 15 10 100>; + + nand@0 { + reg = <0>; + compatible = "nand-flash"; + }; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts new file mode 100644 index 0000000000..e6e42295e2 --- /dev/null +++ b/arch/arm/dts/tegra20-harmony.dts @@ -0,0 +1,113 @@ +/dts-v1/; + +#include "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra20 Harmony evaluation board"; + compatible = "nvidia,harmony", "nvidia,tegra20"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000200"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + host1x { + status = "okay"; + dc@54200000 { + status = "okay"; + rgb { + status = "okay"; + nvidia,panel = <&lcd_panel>; + }; + }; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>; + }; + + sdhci@c8000200 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + bus-width = <8>; + }; + + lcd_panel: panel { + clock = <42430000>; + xres = <1024>; + yres = <600>; + left-margin = <138>; + right-margin = <34>; + hsync-len = <136>; + lower-margin = <4>; + upper-margin = <21>; + vsync-len = <4>; + hsync-active-high; + vsyncx-active-high; + nvidia,bits-per-pixel = <16>; + nvidia,pwm = <&pwm 0 0>; + nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5) + GPIO_ACTIVE_HIGH>; + nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) + GPIO_ACTIVE_HIGH>; + nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) + GPIO_ACTIVE_HIGH>; + nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) + GPIO_ACTIVE_HIGH>; + nvidia,panel-timings = <0 0 200 0 0>; + }; +}; diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts similarity index 78% rename from board/avionic-design/dts/tegra20-medcom-wide.dts rename to arch/arm/dts/tegra20-medcom-wide.dts index a9a07f9bcd..b6b57abdef 100644 --- a/board/avionic-design/dts/tegra20-medcom-wide.dts +++ b/arch/arm/dts/tegra20-medcom-wide.dts @@ -6,6 +6,10 @@ model = "Avionic Design Medcom-Wide"; compatible = "ad,medcom-wide", "nvidia,tegra20"; + chosen { + stdout-path = &uartd; + }; + aliases { usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; @@ -69,9 +73,12 @@ nvidia,bits-per-pixel = <16>; nvidia,pwm = <&pwm 0 500000>; - nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */ - nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ - nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ + nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5) + GPIO_ACTIVE_HIGH>; + nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) + GPIO_ACTIVE_HIGH>; + nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) + GPIO_ACTIVE_HIGH>; nvidia,panel-timings = <0 0 0 0>; }; }; diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts new file mode 100644 index 0000000000..16381c3a4c --- /dev/null +++ b/arch/arm/dts/tegra20-paz00.dts @@ -0,0 +1,99 @@ +/dts-v1/; + +#include "tegra20.dtsi" + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000000"; + }; + + memory { + reg = <0x00000000 0x20000000>; + }; + + host1x { + status = "okay"; + dc@54200000 { + status = "okay"; + rgb { + status = "okay"; + nvidia,panel = <&lcd_panel>; + }; + }; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; + + sdhci@c8000000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; + + lcd_panel: panel { + /* PAZ00 has 1024x600 */ + clock = <54030000>; + xres = <1024>; + yres = <600>; + right-margin = <160>; + left-margin = <24>; + hsync-len = <136>; + upper-margin = <3>; + lower-margin = <61>; + vsync-len = <6>; + hsync-active-high; + nvidia,bits-per-pixel = <16>; + nvidia,pwm = <&pwm 0 0>; + nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4) + GPIO_ACTIVE_HIGH>; + nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6) + GPIO_ACTIVE_HIGH>; + nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) + GPIO_ACTIVE_HIGH>; + nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4) + GPIO_ACTIVE_HIGH>; + nvidia,panel-timings = <400 4 203 17 15>; + }; +}; diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts similarity index 93% rename from board/avionic-design/dts/tegra20-plutux.dts rename to arch/arm/dts/tegra20-plutux.dts index 20016f29bb..e5562a9ca5 100644 --- a/board/avionic-design/dts/tegra20-plutux.dts +++ b/arch/arm/dts/tegra20-plutux.dts @@ -6,6 +6,10 @@ model = "Avionic Design Plutux"; compatible = "ad,plutux", "nvidia,tegra20"; + chosen { + stdout-path = &uartd; + }; + aliases { usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts similarity index 87% rename from board/nvidia/dts/tegra20-seaboard.dts rename to arch/arm/dts/tegra20-seaboard.dts index c0e2e1e5fd..10f399284a 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -10,6 +10,10 @@ bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; }; + chosen { + stdout-path = &uartd; + }; + aliases { /* This defines the order of our ports */ usb0 = "/usb@c5008000"; @@ -61,7 +65,7 @@ }; nand-controller@70008000 { - nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ + nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; nvidia,width = <8>; nvidia,timing = <26 100 20 80 20 10 12 10 70>; nand@0 { @@ -147,7 +151,7 @@ }; usb@c5000000 { - nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; dr_mode = "otg"; }; @@ -157,9 +161,9 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; @@ -182,10 +186,14 @@ hsync-active-high; nvidia,bits-per-pixel = <16>; nvidia,pwm = <&pwm 2 0>; - nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */ - nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ - nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ - nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */ + nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4) + GPIO_ACTIVE_HIGH>; + nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) + GPIO_ACTIVE_HIGH>; + nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) + GPIO_ACTIVE_HIGH>; + nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) + GPIO_ACTIVE_HIGH>; nvidia,panel-timings = <400 4 203 17 15>; }; }; diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/arch/arm/dts/tegra20-tamonten.dtsi similarity index 97% rename from board/avionic-design/dts/tegra20-tamonten.dtsi rename to arch/arm/dts/tegra20-tamonten.dtsi index f379622c94..78449e6133 100644 --- a/board/avionic-design/dts/tegra20-tamonten.dtsi +++ b/arch/arm/dts/tegra20-tamonten.dtsi @@ -14,7 +14,8 @@ pll-supply = <&hdmi_pll_reg>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; }; }; @@ -280,7 +281,7 @@ }; nand-controller@70008000 { - nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ + nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; nvidia,width = <8>; nvidia,timing = <26 100 20 80 20 10 12 10 70>; @@ -476,8 +477,8 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; diff --git a/board/avionic-design/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts similarity index 78% rename from board/avionic-design/dts/tegra20-tec.dts rename to arch/arm/dts/tegra20-tec.dts index 4c1b08d768..94ba6dc2d4 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/arch/arm/dts/tegra20-tec.dts @@ -6,6 +6,10 @@ model = "Avionic Design Tamonten Evaluation Carrier"; compatible = "ad,tec", "nvidia,tegra20"; + chosen { + stdout-path = &uartd; + }; + aliases { usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; @@ -69,9 +73,12 @@ nvidia,bits-per-pixel = <16>; nvidia,pwm = <&pwm 0 500000>; - nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */ - nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ - nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ + nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5) + GPIO_ACTIVE_HIGH>; + nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) + GPIO_ACTIVE_HIGH>; + nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) + GPIO_ACTIVE_HIGH>; nvidia,panel-timings = <0 0 0 0>; }; }; diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts new file mode 100644 index 0000000000..27b118f212 --- /dev/null +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -0,0 +1,138 @@ +/dts-v1/; + +#include "tegra20.dtsi" + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000000"; + spi0 = "/spi@7000c380"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + spi@7000c380 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + pcie-controller@80003000 { + status = "okay"; + + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + pci@1,0 { + status = "okay"; + }; + }; + + usb@c5000000 { + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + }; + + usb@c5004000 { + status = "disabled"; + }; + + sdhci@c8000000 { + status = "okay"; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_vdd_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + hdmi_pll_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vbus_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; + + pci_clk_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "pci_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pci_vdd_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "pci_vdd"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + }; + +}; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts new file mode 100644 index 0000000000..939e567d13 --- /dev/null +++ b/arch/arm/dts/tegra20-ventana.dts @@ -0,0 +1,99 @@ +/dts-v1/; + +#include "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra20 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + host1x { + status = "okay"; + dc@54200000 { + status = "okay"; + rgb { + status = "okay"; + nvidia,panel = <&lcd_panel>; + }; + }; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; + + sdhci@c8000400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; + + lcd_panel: panel { + clock = <72072000>; + xres = <1366>; + yres = <768>; + left-margin = <58>; + right-margin = <58>; + hsync-len = <58>; + lower-margin = <4>; + upper-margin = <4>; + vsync-len = <4>; + hsync-active-high; + vsync-active-high; + nvidia,bits-per-pixel = <16>; + nvidia,pwm = <&pwm 2 0>; + nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4) + GPIO_ACTIVE_HIGH>; + nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) + GPIO_ACTIVE_HIGH>; + nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) + GPIO_ACTIVE_HIGH>; + nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) + GPIO_ACTIVE_HIGH>; + nvidia,panel-timings = <0 0 200 0 0>; + }; +}; diff --git a/board/nvidia/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts similarity index 91% rename from board/nvidia/dts/tegra20-whistler.dts rename to arch/arm/dts/tegra20-whistler.dts index eb92264f9d..c4a28eb427 100644 --- a/board/nvidia/dts/tegra20-whistler.dts +++ b/arch/arm/dts/tegra20-whistler.dts @@ -6,6 +6,10 @@ model = "NVIDIA Tegra20 Whistler evaluation board"; compatible = "nvidia,whistler", "nvidia,tegra20"; + chosen { + stdout-path = &uarta; + }; + aliases { i2c0 = "/i2c@7000d000"; usb0 = "/usb@c5008000"; @@ -62,7 +66,7 @@ sdhci@c8000400 { status = "okay"; - wp-gpios = <&gpio 173 0>; /* gpio PV5 */ + wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; bus-width = <8>; }; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 3805750581..b8c8a92301 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -1,3 +1,7 @@ +#include +#include +#include + #include "skeleton.dtsi" / { @@ -139,10 +143,18 @@ gpio: gpio@6000d000 { compatible = "nvidia,tegra20-gpio"; - reg = < 0x6000d000 0x1000 >; - interrupts = < 64 65 66 67 87 119 121 >; + reg = <0x6000d000 0x1000>; + interrupts = , + , + , + , + , + , + ; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; }; pinmux: pinmux@70000000 { @@ -178,39 +190,69 @@ dma-channel = < 1 >; }; - serial@70006000 { + uarta: serial@70006000 { compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = < 68 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; }; - serial@70006040 { + uartb: serial@70006040 { compatible = "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = < 69 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; }; - serial@70006200 { + uartc: serial@70006200 { compatible = "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = < 78 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; }; - serial@70006300 { + uartd: serial@70006300 { compatible = "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = < 122 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; }; - serial@70006400 { + uarte: serial@70006400 { compatible = "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = < 123 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; }; nand: nand-controller@70008000 { @@ -290,6 +332,65 @@ reg = <0x7000f400 0x200>; }; + pcie-controller@80003000 { + compatible = "nvidia,tegra20-pcie"; + device_type = "pci"; + reg = <0x80003000 0x00000800 /* PADS registers */ + 0x80003800 0x00000200 /* AFI registers */ + 0x90000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ + 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ + 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA20_CLK_PEX>, + <&tegra_car TEGRA20_CLK_AFI>, + <&tegra_car TEGRA20_CLK_PCIE_XCLK>, + <&tegra_car TEGRA20_CLK_PLL_E>; + clock-names = "pex", "afi", "pcie_xclk", "pll_e"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts new file mode 100644 index 0000000000..15db0f275b --- /dev/null +++ b/arch/arm/dts/tegra30-apalis.dts @@ -0,0 +1,304 @@ +/dts-v1/; + +#include "tegra30.dtsi" + +/ { + model = "Toradex Apalis T30"; + compatible = "toradex,apalis_t30", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c500"; + i2c3 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000400"; + sdhci2 = "/sdhci@78000000"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d004000"; + usb2 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + pcie-controller@00003000 { + status = "okay"; + avdd-pexa-supply = <&vdd2_reg>; + vdd-pexa-supply = <&vdd2_reg>; + avdd-pexb-supply = <&vdd2_reg>; + vdd-pexb-supply = <&vdd2_reg>; + avdd-pex-pll-supply = <&vdd2_reg>; + avdd-plle-supply = <&ldo6_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + hvdd-pex-supply = <&sys_3v3_reg>; + + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* GEN2_I2C: unused */ + + /* + * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on + * carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&sys_3v3_reg>; + vcc2-supply = <&sys_3v3_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&sys_3v3_reg>; + vcc5-supply = <&sys_3v3_reg>; + vcc6-supply = <&vio_reg>; + vcc7-supply = <&charge_pump_5v0_reg>; + vccio-supply = <&sys_3v3_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + /* SW1: +V1.35_VDDIO_DDR */ + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + /* SW2: +V1.05 */ + vdd2_reg: vdd2 { + regulator-name = + "vdd_pexa,vdd_pexb,vdd_sata"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* SW CTRL: +V1.0_VDD_CPU */ + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + /* SWIO: +V1.8 */ + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO1: unused */ + + /* + * EN_+V3.3 switching via FET: + * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN + * see also v3_3 fixed supply + */ + ldo2_reg: ldo2 { + regulator-name = "en_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* +V1.2_CSI */ + ldo3_reg: ldo3 { + regulator-name = + "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + /* +V1.2_VDD_RTC */ + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* + * +V2.8_AVDD_VDAC: + * only required for analog RGB + */ + ldo5_reg: ldo5 { + regulator-name = "avdd_vdac"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + /* + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V + * but LDO6 can't set voltage in 50mV + * granularity + */ + ldo6_reg: ldo6 { + regulator-name = "avdd_plle"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + /* +V1.2_AVDD_PLL */ + ldo7_reg: ldo7 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* +V1.0_VDD_DDR_HS */ + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + }; + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI4: CAN2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI5: Apalis SPI2 */ + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI6: CAN1 */ + spi@7000de00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + sdhci@78000000 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + }; + + sdhci@78000400 { + status = "okay"; + bus-width = <8>; + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + phy_type = "utmi"; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ + usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + sys_3v3_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + charge_pump_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts new file mode 100644 index 0000000000..ae836363ab --- /dev/null +++ b/arch/arm/dts/tegra30-beaver.dts @@ -0,0 +1,334 @@ +/dts-v1/; + +#include "tegra30.dtsi" + +/ { + model = "NVIDIA Beaver"; + compatible = "nvidia,beaver", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000000"; + spi0 = "/spi@7000da00"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x7ff00000>; + }; + + pcie-controller@00003000 { + status = "okay"; + + avdd-pexa-supply = <&ldo1_reg>; + vdd-pexa-supply = <&ldo1_reg>; + avdd-pexb-supply = <&ldo1_reg>; + vdd-pexb-supply = <&ldo1_reg>; + avdd-pex-pll-supply = <&ldo1_reg>; + avdd-plle-supply = <&ldo1_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + hvdd-pex-supply = <&sys_3v3_pexs_reg>; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + nvidia,num-lanes = <2>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v_in_reg>; + vcc2-supply = <&vdd_5v_in_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v_in_reg>; + vcc5-supply = <&vdd_5v_in_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v_in_reg>; + vccio-supply = <&vdd_5v_in_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@1 { + compatible = "winbond,w25q32"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + }; + + usb@7d008000 { + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v_in_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v_in"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + chargepump_5v_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "chargepump_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + ddr_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + vdd_5v_sata_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_5v_sata"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + usb1_vbus_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; + + usb3_vbus_reg: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; + + sys_3v3_reg: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "sys_3v3,vdd_3v3_alw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; + + sys_3v3_pexs_reg: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "sys_3v3_pexs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_5v0_hdmi: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+VDD_5V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&sys_3v3_reg>; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts new file mode 100644 index 0000000000..23ca141df2 --- /dev/null +++ b/arch/arm/dts/tegra30-cardhu.dts @@ -0,0 +1,439 @@ +/dts-v1/; + +#include "tegra30.dtsi" + +/ { + model = "NVIDIA Cardhu"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000000"; + spi0 = "/spi@7000da00"; + usb0 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + pcie-controller@00003000 { + status = "okay"; + + /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ + avdd-pexb-supply = <&ldo1_reg>; + vdd-pexb-supply = <&ldo1_reg>; + avdd-pex-pll-supply = <&ldo1_reg>; + hvdd-pex-supply = <&pex_hvdd_3v3_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + avdd-plle-supply = <&ldo2_reg>; + + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_ac_bat_reg>; + vcc2-supply = <&vdd_ac_bat_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_ac_bat_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_ac_bat_reg>; + vccio-supply = <&vdd_ac_bat_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d008000 { + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + cam_1v8_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "cam_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vio_reg>; + }; + + cp_5v_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + emmc_3v3_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "emmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + modem_3v3_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "modem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + }; + + pex_hvdd_3v3_reg: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "pex_hvdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam1_ldo_reg: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "vdd_cam1_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam2_ldo_reg: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vdd_cam2_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam3_ldo_reg: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "vdd_cam3_ldo"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_com_reg: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "vdd_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_pnl1_reg: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "vdd_pnl1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_vid_reg: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "ddr"; + reg = <100>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + }; + + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + }; + + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + reg = <104>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + }; + + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + reg = <105>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; + }; + + vdd_bl2_reg: regulator@106 { + compatible = "regulator-fixed"; + reg = <106>; + regulator-name = "vdd_bl2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts new file mode 100644 index 0000000000..6cd1902f11 --- /dev/null +++ b/arch/arm/dts/tegra30-colibri.dts @@ -0,0 +1,94 @@ +/dts-v1/; + +#include "tegra30.dtsi" + +/ { + model = "Toradex Colibri T30"; + compatible = "toradex,colibri_t30", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000200"; + spi0 = "/spi@7000d400"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d004000"; /* on module only, for ASIX */ + usb2 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* GEN2_I2C: unused */ + + /* CAM_I2C: unused */ + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* SPI1: Colibri SSP */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + sdhci@78000200 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + /* EHCI instance 1: USB2_DP/N -> AX88772B */ + usb@7d004000 { + status = "okay"; + phy_type = "utmi"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ + usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi new file mode 100644 index 0000000000..8eff627f3d --- /dev/null +++ b/arch/arm/dts/tegra30-tamonten.dtsi @@ -0,0 +1,73 @@ +#include "tegra30.dtsi" + +/ { + model = "Avionic Design Tamonten NG"; + compatible = "ad,tamonten-ng", "nvidia,tegra30"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = "/i2c@7000c000"; + i2c1 = "/i2c@7000c700"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000d000"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000400"; + sdhci2 = "/sdhci@78000000"; + usb0 = "/usb@7d008000"; + }; + + /* GEN1 */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* GEN2 */ + i2c@7000c400 { + clock-frequency = <100000>; + }; + + /* CAM */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* DDC */ + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* PWR */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* SD slot on the base board */ + sdhci@78000400 { + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + /* EMMC on the COM module */ + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d008000 { + status = "okay"; + }; + +}; diff --git a/arch/arm/dts/tegra30-tec-ng.dts b/arch/arm/dts/tegra30-tec-ng.dts new file mode 100644 index 0000000000..e924acc35c --- /dev/null +++ b/arch/arm/dts/tegra30-tec-ng.dts @@ -0,0 +1,22 @@ +/dts-v1/; + +#include "tegra30-tamonten.dtsi" + +/ { + model = "Avionic Design Tamonten™ NG Evaluation Carrier"; + compatible = "ad,tec-ng", "nvidia,tegra30"; + + aliases { + i2c0 = "/i2c@7000c400"; + }; + + /* GEN2 */ + i2c@7000c400 { + status = "okay"; + }; + + /* SD card slot */ + sdhci@78000400 { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index fee1c36efb..5ea7e347f3 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -1,7 +1,94 @@ +#include +#include +#include + #include "skeleton.dtsi" / { compatible = "nvidia,tegra30"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x50041000 0x1000 + 0x50040100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + pcie-controller@00003000 { + compatible = "nvidia,tegra30-pcie"; + device_type = "pci"; + reg = <0x00003000 0x00000800 /* PADS registers */ + 0x00003800 0x00000200 /* AFI registers */ + 0x10000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ + 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA30_CLK_PCIE>, + <&tegra_car TEGRA30_CLK_AFI>, + <&tegra_car TEGRA30_CLK_PCIEX>, + <&tegra_car TEGRA30_CLK_PLL_E>, + <&tegra_car TEGRA30_CLK_CML0>; + clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; tegra_car: clock { compatible = "nvidia,tegra30-car"; @@ -47,17 +134,17 @@ clocks = <&tegra_car 34>; }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04>; + interrupts = , + , + , + , + , + , + , + ; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; @@ -119,6 +206,71 @@ status = "disabled"; }; + uarta: serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uarte: serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi new file mode 100644 index 0000000000..a63272422d --- /dev/null +++ b/arch/arm/dts/tps65217.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65217.pdf + */ + +&tps { + compatible = "ti,tps65217"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "dcdc1"; + }; + + dcdc2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "dcdc2"; + }; + + dcdc3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "dcdc3"; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-compatible = "ldo1"; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo2"; + }; + + ldo3_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo3"; + }; + + ldo4_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo4"; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts new file mode 100644 index 0000000000..6855878c29 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -0,0 +1,61 @@ +/* + * Device Tree Source for UniPhier PH1-LD4 Reference Board + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ph1-ld4.dtsi" + +/ { + model = "Panasonic UniPhier PH1-LD4 Reference Board"; + compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + eeprom { + compatible = "i2c-eeprom"; + reg = <0x50>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi new file mode 100644 index 0000000000..2a3dd73ead --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for UniPhier PH1-LD4 SoC + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "panasonic,ph1-ld4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@54006800 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x20>; + clock-frequency = <36864000>; + }; + + uart1: serial@54006900 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x20>; + clock-frequency = <36864000>; + }; + + uart2: serial@54006a00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x20>; + clock-frequency = <36864000>; + }; + + uart3: serial@54006b00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x20>; + clock-frequency = <36864000>; + }; + + i2c0: i2c@58400000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58400000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@58480000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58480000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@58500000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58500000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@58580000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58580000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + usb0: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + }; + + usb1: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + }; + + usb2: usb@5a820100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + }; + + nand: nand@68000000 { + compatible = "denali,denali-nand-dt"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts new file mode 100644 index 0000000000..1227b628d1 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -0,0 +1,63 @@ +/* + * Device Tree Source for UniPhier PH1-Pro4 Reference Board + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ph1-pro4.dtsi" + +/ { + model = "Panasonic UniPhier PH1-Pro4 Reference Board"; + compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + eeprom { + compatible = "i2c-eeprom"; + reg = <0x50>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi new file mode 100644 index 0000000000..49e375e8d2 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -0,0 +1,140 @@ +/* + * Device Tree Source for UniPhier PH1-Pro4 SoC + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "panasonic,ph1-pro4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@54006800 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x20>; + clock-frequency = <73728000>; + }; + + uart1: serial@54006900 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x20>; + clock-frequency = <73728000>; + }; + + uart2: serial@54006a00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x20>; + clock-frequency = <73728000>; + }; + + uart3: serial@54006b00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x20>; + clock-frequency = <73728000>; + }; + + i2c0: i2c@58780000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58780000 0x80>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@58781000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58781000 0x80>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@58782000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58782000 0x80>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@58783000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58783000 0x80>; + clock-frequency = <100000>; + status = "disabled"; + }; + + /* i2c4 does not exist */ + + i2c5: i2c@58785000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58785000 0x80>; + clock-frequency = <400000>; + status = "ok"; + }; + + i2c6: i2c@58786000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58786000 0x80>; + clock-frequency = <400000>; + status = "ok"; + }; + + usb0: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + }; + + usb1: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + }; + + nand: nand@68000000 { + compatible = "denali,denali-nand-dt"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts new file mode 100644 index 0000000000..fefc592589 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -0,0 +1,60 @@ +/* + * Device Tree Source for UniPhier PH1-sLD3 Reference Board + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ph1-sld3.dtsi" + +/ { + model = "Panasonic UniPhier PH1-sLD3 Reference Board"; + compatible = "panasonic,ph1-sld3-ref", "panasonic,ph1-sld3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + eeprom { + compatible = "i2c-eeprom"; + reg = <0x50>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi new file mode 100644 index 0000000000..f5529d2e6e --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -0,0 +1,125 @@ +/* + * Device Tree Source for UniPhier PH1-sLD3 SoC + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "panasonic,ph1-sld3"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@54006800 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x20>; + clock-frequency = <36864000>; + }; + + uart1: serial@54006900 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x20>; + clock-frequency = <36864000>; + }; + + uart2: serial@54006a00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x20>; + clock-frequency = <36864000>; + }; + + i2c0: i2c@58400000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58400000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@58480000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58480000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@58500000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58500000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@58580000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58580000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + usb0: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + }; + + usb1: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + }; + + usb2: usb@5a820100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + }; + + usb3: usb@5a830100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a830100 0x100>; + }; + + nand: nand@f8000000 { + compatible = "denali,denali-nand-dt"; + reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts new file mode 100644 index 0000000000..9b6d95c480 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -0,0 +1,61 @@ +/* + * Device Tree Source for UniPhier PH1-sLD8 Reference Board + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ph1-sld8.dtsi" + +/ { + model = "Panasonic UniPhier PH1-sLD8 Reference Board"; + compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + eeprom { + compatible = "i2c-eeprom"; + reg = <0x50>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi new file mode 100644 index 0000000000..0ea76e59fc --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for UniPhier PH1-sLD8 SoC + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "panasonic,ph1-sld8"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@54006800 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x20>; + clock-frequency = <80000000>; + }; + + uart1: serial@54006900 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x20>; + clock-frequency = <80000000>; + }; + + uart2: serial@54006a00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x20>; + clock-frequency = <80000000>; + }; + + uart3: serial@54006b00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x20>; + clock-frequency = <80000000>; + }; + + i2c0: i2c@58400000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58400000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@58480000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58480000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@58500000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58500000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@58580000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58580000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + usb0: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + }; + + usb1: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + }; + + usb2: usb@5a820100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + }; + + nand: nand@68000000 { + compatible = "denali,denali-nand-dt"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi new file mode 100644 index 0000000000..2d076f194e --- /dev/null +++ b/arch/arm/dts/zynq-7000.dtsi @@ -0,0 +1,207 @@ +/* + * Xilinx Zynq 7000 DTSI + * Describes the hardware common to all Zynq 7000-based boards. + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/include/ "skeleton.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + clocks = <&clkc 3>; + clock-latency = <1000>; + operating-points = < + /* kHz uV */ + 666667 1000000 + 333334 1000000 + 222223 1000000 + >; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + clocks = <&clkc 3>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 5 4>, <0 6 4>; + interrupt-parent = <&intc>; + reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + i2c0: zynq-i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 38>; + interrupt-parent = <&intc>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: zynq-i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 39>; + interrupt-parent = <&intc>; + interrupts = <0 48 4>; + reg = <0xe0005000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0000000 0x1000>; + interrupts = <0 27 4>; + }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + }; + + gem0: ethernet@e000b000 { + compatible = "cdns,gem"; + reg = <0xe000b000 0x4000>; + status = "disabled"; + interrupts = <0 22 4>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + gem1: ethernet@e000c000 { + compatible = "cdns,gem"; + reg = <0xe000c000 0x4000>; + status = "disabled"; + interrupts = <0 45 4>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + sdhci0: ps7-sdhci@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + interrupt-parent = <&intc>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + } ; + + sdhci1: ps7-sdhci@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 22>, <&clkc 33>; + interrupt-parent = <&intc>; + interrupts = <0 47 4>; + reg = <0xe0101000 0x1000>; + } ; + + slcr: slcr@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon"; + reg = <0xF8000000 0x1000>; + ranges; + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + fclk-enable = <0>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + }; + + global_timer: timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <1 11 0x301>; + interrupt-parent = <&intc>; + clocks = <&clkc 4>; + }; + + ttc0: ttc0@f8001000 { + interrupt-parent = <&intc>; + interrupts = < 0 10 4 0 11 4 0 12 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8001000 0x1000>; + }; + + ttc1: ttc1@f8002000 { + interrupt-parent = <&intc>; + interrupts = < 0 37 4 0 38 4 0 39 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8002000 0x1000>; + }; + scutimer: scutimer@f8f00600 { + interrupt-parent = <&intc>; + interrupts = < 1 13 0x301 >; + compatible = "arm,cortex-a9-twd-timer"; + reg = < 0xf8f00600 0x20 >; + clocks = <&clkc 4>; + } ; + }; +}; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts new file mode 100644 index 0000000000..c373a2cc31 --- /dev/null +++ b/arch/arm/dts/zynq-microzed.dts @@ -0,0 +1,23 @@ +/* + * Xilinx MicroZED board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq MicroZED Board"; + compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts new file mode 100644 index 0000000000..4fa0b00b31 --- /dev/null +++ b/arch/arm/dts/zynq-zc702.dts @@ -0,0 +1,23 @@ +/* + * Xilinx ZC702 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC702 Board"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts new file mode 100644 index 0000000000..2a80195757 --- /dev/null +++ b/arch/arm/dts/zynq-zc706.dts @@ -0,0 +1,23 @@ +/* + * Xilinx ZC706 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC706 Board"; + compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts new file mode 100644 index 0000000000..5e66174977 --- /dev/null +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -0,0 +1,23 @@ +/* + * Xilinx ZC770 XM010 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM010 Board"; + compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts new file mode 100644 index 0000000000..127a6619c6 --- /dev/null +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -0,0 +1,23 @@ +/* + * Xilinx ZC770 XM012 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM012 Board"; + compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts new file mode 100644 index 0000000000..c61c7e7592 --- /dev/null +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -0,0 +1,23 @@ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM013 Board"; + compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts new file mode 100644 index 0000000000..70cc8a6c0d --- /dev/null +++ b/arch/arm/dts/zynq-zed.dts @@ -0,0 +1,23 @@ +/* + * Xilinx ZED board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZED Board"; + compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x20000000>; + }; +}; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts new file mode 100644 index 0000000000..20e0386777 --- /dev/null +++ b/arch/arm/dts/zynq-zybo.dts @@ -0,0 +1,23 @@ +/* + * Digilent ZYBO board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZYBO Board"; + compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x20000000>; + }; +}; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 727a052806..25a9d4ce12 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -7,73 +7,76 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libimx-common.o - ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610)) -COBJS-y = iomux-v3.o +obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) -COBJS-y += timer.o cpu.o speed.o -COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o +obj-y += timer.o cpu.o speed.o +obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) -COBJS-y += misc.o +obj-y += misc.o +obj-$(CONFIG_SPL_BUILD) += spl.o +endif +ifeq ($(SOC),$(filter $(SOC),mx6)) +obj-$(CONFIG_CMD_SATA) += sata.o +obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o +endif +obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o +obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o + +quiet_cmd_cpp_cfg = CFGS $@ + cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $< + +IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp + +$(IMX_CONFIG): %.cfgtmp: % FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cpp_cfg) + +MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \ + -e $(CONFIG_SYS_TEXT_BASE) + +u-boot.imx: u-boot.bin $(IMX_CONFIG) FORCE + $(call if_changed,mkimage) + +ifeq ($(CONFIG_OF_SEPARATE),y) +MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \ + -e $(CONFIG_SYS_TEXT_BASE) + +u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) FORCE + $(call if_changed,mkimage) endif -COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o -COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o -COBJS := $(sort $(COBJS-y)) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp: $(OBJTREE)/%.cfgtmp : $(SRCTREE)/% - mkdir -p $(dir $@) - $(CC) -E -x c $< $(CPPFLAGS) -o $@ - -$(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp - $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \ - -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ - -$(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp - $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \ - -e $(CONFIG_SPL_TEXT_BASE) -d $< $@ - -$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ - -I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx - $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ - -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \ - $(OBJTREE)/u-boot.uim - cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim > $@ - rm $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim - -$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin - (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \ - dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | \ - cat - $< > $(OBJTREE)/spl/u-boot-nand-spl.imx - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ - -I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \ - $(OBJTREE)/spl/u-boot-nand-spl-pad.imx - rm $(OBJTREE)/spl/u-boot-nand-spl.imx - $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ - -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \ - $(OBJTREE)/u-boot.uim - cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim > $@ - rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### + +MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \ + -e $(CONFIG_SPL_TEXT_BASE) + +SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE + $(call if_changed,mkimage) + +MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ + -e $(CONFIG_SYS_TEXT_BASE) -C none + +u-boot.uim: u-boot.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS += -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) +append = cat $(filter-out $< $(PHONY), $^) >> $@ + +quiet_cmd_pad_cat = CAT $@ +cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@ + +u-boot-with-spl.imx: SPL u-boot.uim FORCE + $(call if_changed,pad_cat) + +u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE + $(call if_changed,pad_cat) + +quiet_cmd_u-boot-nand-spl_imx = GEN $@ +cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \ + dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@ + +spl/u-boot-nand-spl.imx: SPL FORCE + $(call if_changed,u-boot-nand-spl_imx) + +targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx) diff --git a/arch/arm/imx-common/cmd_hdmidet.c b/arch/arm/imx-common/cmd_hdmidet.c index d6ec7c4691..e9fd9553cf 100644 --- a/arch/arm/imx-common/cmd_hdmidet.c +++ b/arch/arm/imx-common/cmd_hdmidet.c @@ -11,8 +11,7 @@ static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg = readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; - return (reg&HDMI_PHY_HPD) ? 0 : 1; + return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1; } U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet, diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index c847a838f0..b915a0014f 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -7,13 +7,18 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include +#include #include #include #include #include #include #include +#include +#include +#include #ifdef CONFIG_FSL_ESDHC #include @@ -48,15 +53,16 @@ char *get_reset_cause(void) } } -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) -#if defined(CONFIG_MX53) -#define MEMCTL_BASE ESDCTL_BASE_ADDR; +#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) +#if defined(CONFIG_SOC_MX53) +#define MEMCTL_BASE ESDCTL_BASE_ADDR #else -#define MEMCTL_BASE MMDC_P0_BASE_ADDR; +#define MEMCTL_BASE MMDC_P0_BASE_ADDR #endif static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; static const unsigned char bank_lookup[] = {3, 2}; +/* these MMDC registers are common to the IMX53 and IMX6 */ struct esd_mmdc_regs { uint32_t ctl; uint32_t pdc; @@ -65,15 +71,6 @@ struct esd_mmdc_regs { uint32_t cfg1; uint32_t cfg2; uint32_t misc; - uint32_t scr; - uint32_t ref; - uint32_t rsvd1; - uint32_t rsvd2; - uint32_t rwd; - uint32_t or; - uint32_t mrr; - uint32_t cfg3lp; - uint32_t mr4; }; #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) @@ -82,6 +79,12 @@ struct esd_mmdc_regs { #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) +/* + * imx_ddr_size - return size in bytes of DRAM according MMDC config + * The MMDC MDCTL register holds the number of bits for row, col, and data + * width and the MMDC MDMISC register holds the number of banks. Combine + * all these bits to determine the meme size the MMDC has been configured for + */ unsigned imx_ddr_size(void) { struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; @@ -94,6 +97,11 @@ unsigned imx_ddr_size(void) bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; bits += ESD_MMDC_CTL_GET_WIDTH(ctl); bits += ESD_MMDC_CTL_GET_CS1(ctl); + + /* The MX6 can do only 3840 MiB of DRAM */ + if (bits == 32) + return 0xf0000000; + return 1 << bits; } #endif @@ -105,12 +113,16 @@ const char *get_imx_type(u32 imxtype) switch (imxtype) { case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ + case MXC_CPU_MX6D: + return "6D"; /* Dual-core version of the mx6 */ case MXC_CPU_MX6DL: return "6DL"; /* Dual Lite version of the mx6 */ case MXC_CPU_MX6SOLO: return "6SOLO"; /* Solo version of the mx6 */ case MXC_CPU_MX6SL: return "6SL"; /* Solo-Lite version of the mx6 */ + case MXC_CPU_MX6SX: + return "6SX"; /* SoloX version of the mx6 */ case MXC_CPU_MX51: return "51"; case MXC_CPU_MX53: @@ -124,6 +136,11 @@ int print_cpuinfo(void) { u32 cpurev; +#if defined(CONFIG_SOC_MX6) && defined(CONFIG_IMX6_THERMAL) + struct udevice *thermal_dev; + int cpu_tmp, ret; +#endif + cpurev = get_cpu_rev(); printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", @@ -131,6 +148,21 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); + +#if defined(CONFIG_SOC_MX6) && defined(CONFIG_IMX6_THERMAL) + ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); + if (!ret) { + ret = thermal_get_temp(thermal_dev, &cpu_tmp); + + if (!ret) + printf("CPU: Temperature %d C\n", cpu_tmp); + else + printf("CPU: Temperature: invalid sensor data\n"); + } else { + printf("CPU: Temperature: Can't find sensor device\n"); + } +#endif + printf("Reset cause: %s\n", get_reset_cause()); return 0; } @@ -169,3 +201,48 @@ u32 get_ahb_clk(void) return get_periph_clk() / (ahb_podf + 1); } + +void arch_preboot_os(void) +{ +#if defined(CONFIG_CMD_SATA) + sata_stop(); +#if defined(CONFIG_SOC_MX6) + disable_sata_clock(); +#endif +#endif +#if defined(CONFIG_VIDEO_IPUV3) + /* disable video before launching O/S */ + ipuv3_fb_shutdown(); +#endif +} + +void set_chipselect_size(int const cs_size) +{ + unsigned int reg; + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + reg = readl(&iomuxc_regs->gpr[1]); + + switch (cs_size) { + case CS0_128: + reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ + reg |= 0x5; + break; + case CS0_64M_CS1_64M: + reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ + reg |= 0x1B; + break; + case CS0_64M_CS1_32M_CS2_32M: + reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ + reg |= 0x4B; + break; + case CS0_32M_CS1_32M_CS2_32M_CS3_32M: + reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ + reg |= 0x249; + break; + default: + printf("Unknown chip select size: %d\n", cs_size); + break; + } + + writel(reg, &iomuxc_regs->gpr[1]); +} diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c index a58087399c..1a632e7203 100644 --- a/arch/arm/imx-common/i2c-mxv7.c +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -69,15 +70,45 @@ static void * const i2c_bases[] = { }; /* i2c_index can be from 0 - 2 */ -void setup_i2c(unsigned i2c_index, int speed, int slave_addr, - struct i2c_pads_info *p) +int setup_i2c(unsigned i2c_index, int speed, int slave_addr, + struct i2c_pads_info *p) { + char name[9]; + int ret; + if (i2c_index >= ARRAY_SIZE(i2c_bases)) - return; + return -EINVAL; + + snprintf(name, sizeof(name), "i2c_sda%01d", i2c_index); + ret = gpio_request(p->sda.gp, name); + if (ret) + return ret; + + snprintf(name, sizeof(name), "i2c_scl%01d", i2c_index); + ret = gpio_request(p->scl.gp, name); + if (ret) + goto err_req; + /* Enable i2c clock */ - enable_i2c_clk(1, i2c_index); + ret = enable_i2c_clk(1, i2c_index); + if (ret) + goto err_clk; + /* Make sure bus is idle */ - force_idle_bus(p); + ret = force_idle_bus(p); + if (ret) + goto err_idle; + bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr, force_idle_bus, p); + + return 0; + +err_idle: +err_clk: + gpio_free(p->scl.gp); +err_req: + gpio_free(p->sda.gp); + + return ret; } diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index fe43d872dd..9ec1a3cf9e 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -11,6 +11,9 @@ #include #include #include +#if !defined(CONFIG_SOC_MX25) && !defined(CONFIG_SOC_VF610) +#include +#endif #include static void *base = (void *)IOMUXC_BASE_ADDR; @@ -30,6 +33,19 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; +#if defined CONFIG_SOC_MX6SL + /* Check whether LVE bit needs to be set */ + if (pad_ctrl & PAD_CTL_LVE) { + pad_ctrl &= ~PAD_CTL_LVE; + pad_ctrl |= PAD_CTL_LVE_BIT; + } +#endif +#ifdef DEBUG + printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n", + i, pad, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl, + pad & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input); +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); @@ -46,28 +62,33 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #endif } +/* configures a list of pads within declared with IOMUX_PADS macro */ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count) { iomux_v3_cfg_t const *p = pad_list; + int stride; int i; - for (i = 0; i < count; i++) { -#ifdef DEBUG - u32 mux_ctrl_ofs = (*p & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; - u32 mux_mode = (*p & MUX_MODE_MASK) >> MUX_MODE_SHIFT; - u32 sel_input_ofs = - (*p & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; - u32 sel_input = - (*p & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; - u32 pad_ctrl_ofs = - (*p & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; - u32 pad_ctrl = (*p & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; - - printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n", - i, *p, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl, - *p & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input); +#if defined(CONFIG_SOC_MX6QDL) + stride = 2; + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + p += 1; +#else + stride = 1; #endif - imx_iomux_v3_setup_pad(*p++); + for (i = 0; i < count; i++) { + imx_iomux_v3_setup_pad(*p); + p += stride; } } + +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value) +{ + u32 reg = readl(base + group * 4); + + reg &= ~(((1 << num_bits) - 1) << start_bit); + reg |= value << start_bit; + writel(reg, base + group * 4); +} diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c index dbecf4e434..12256a38eb 100644 --- a/arch/arm/imx-common/misc.c +++ b/arch/arm/imx-common/misc.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c new file mode 100644 index 0000000000..d174a463f8 --- /dev/null +++ b/arch/arm/imx-common/sata.c @@ -0,0 +1,38 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int setup_sata(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + return 1; + + ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3< + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_SOC_MX6) +/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */ +u32 spl_boot_device(void) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28); + unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1); + + /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */ + switch ((reg & 0x000000FF) >> 4) { + /* EIM: See 8.5.1, Table 8-9 */ + case 0x0: + /* BOOT_CFG1[3]: NOR/OneNAND Selection */ + if ((reg & 0x00000008) >> 3) + return BOOT_DEVICE_ONENAND; + else + return BOOT_DEVICE_NOR; + break; + /* SATA: See 8.5.4, Table 8-20 */ + case 0x2: + return BOOT_DEVICE_SATA; + /* Serial ROM: See 8.5.5.1, Table 8-22 */ + case 0x3: + /* BOOT_CFG4[2:0] */ + switch ((reg & 0x07000000) >> 24) { + case 0x0 ... 0x4: + return BOOT_DEVICE_SPI; + case 0x5 ... 0x7: + return BOOT_DEVICE_I2C; + } + break; + /* SD/eSD: 8.5.3, Table 8-15 */ + case 0x4: + case 0x5: + return BOOT_DEVICE_MMC1; + /* MMC/eMMC: 8.5.3 */ + case 0x6: + case 0x7: + return BOOT_DEVICE_MMC1; + /* NAND Flash: 8.5.2 */ + case 0x8 ... 0xf: + return BOOT_DEVICE_NAND; + } + return BOOT_DEVICE_NONE; +} +#endif + +#if defined(CONFIG_SPL_MMC_SUPPORT) +/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + /* for MMC return either RAW or FAT mode */ + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: +#if defined(CONFIG_SPL_FAT_SUPPORT) + return MMCSD_MODE_FS; +#elif defined(CONFIG_SUPPORT_EMMC_BOOT) + return MMCSD_MODE_EMMCBOOT; +#else + return MMCSD_MODE_RAW; +#endif + break; + default: + puts("spl: ERROR: unsupported device\n"); + hang(); + } +} +#endif diff --git a/arch/arm/imx-common/spl_sd.cfg b/arch/arm/imx-common/spl_sd.cfg new file mode 100644 index 0000000000..5fc3e8af38 --- /dev/null +++ b/arch/arm/imx-common/spl_sd.cfg @@ -0,0 +1,8 @@ +/* + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +IMAGE_VERSION 2 +BOOT_FROM sd diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index 92712a6de5..b1f51611d5 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -12,6 +12,7 @@ #include #include #include +#include /* General purpose timers registers */ struct mxc_gpt { @@ -26,31 +27,68 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; /* General purpose timers bitfields */ #define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */ #define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */ +#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */ +#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */ +#define GPTCR_CLKSOURCE_MASK (0x7 << 6) #define GPTCR_TEN 1 /* Timer enable */ +#define GPTPR_PRESCALER24M_SHIFT 12 +#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT) + DECLARE_GLOBAL_DATA_PTR; +static inline int gpt_has_clk_source_osc(void) +{ +#if defined(CONFIG_SOC_MX6) + if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && + (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) + return 1; + + return 0; +#else + return 0; +#endif +} + +static inline ulong gpt_get_clk(void) +{ +#ifdef CONFIG_MXC_GPT_HCLK + if (gpt_has_clk_source_osc()) + return MXC_HCLK >> 3; + else + return mxc_get_clock(MXC_IPG_PERCLK); +#else + return MXC_CLK32; +#endif +} static inline unsigned long long tick_to_time(unsigned long long tick) { + ulong gpt_clk = gpt_get_clk(); + tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); + do_div(tick, gpt_clk); + return tick; } -static inline unsigned long time_to_tick(unsigned long time) +static inline unsigned long long time_to_tick(unsigned long time) { unsigned long long ticks = (unsigned long long)time; - ticks *= MXC_CLK32; + ticks *= gpt_get_clk(); do_div(ticks, CONFIG_SYS_HZ); return ticks; } static inline unsigned long long us_to_tick(unsigned long long usec) { - usec = usec * MXC_CLK32 + 999999; + ulong gpt_clk = gpt_get_clk(); + + usec = usec * gpt_clk + 999999; do_div(usec, 1000000); return usec; @@ -67,16 +105,36 @@ int timer_init(void) for (i = 0; i < 100; i++) __raw_writel(0, &cur_gpt->control); - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ - - /* Freerun Mode, PERCLK1 input */ i = __raw_readl(&cur_gpt->control); - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); + i &= ~GPTCR_CLKSOURCE_MASK; + +#ifdef CONFIG_MXC_GPT_HCLK + if (gpt_has_clk_source_osc()) { + i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; + + /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */ + if (is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO) || + is_cpu_type(MXC_CPU_MX6SX)) { + i |= GPTCR_24MEN; + + /* Produce 3Mhz clock */ + __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT), + &cur_gpt->prescaler); + } + } else { + i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN; + } +#else + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ + i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; +#endif + __raw_writel(i, &cur_gpt->control); gd->arch.tbl = __raw_readl(&cur_gpt->counter); gd->arch.tbu = 0; - gd->arch.timer_rate_hz = MXC_CLK32; + gd->arch.timer_rate_hz = gpt_get_clk(); return 0; } @@ -95,17 +153,10 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ - /* - * LW: get_ticks() returns a long long with the top 32 bits always ZERO! - * Thus the calculation above is not true. - * A 64bit timer value would only make sense if it was - * consistently used throughout the code. Thus also the parameter - * to get_timer() and its return value would need to be 64bit wide! - */ return tick_to_time(get_ticks()); } @@ -137,5 +188,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return gd->arch.timer_rate_hz; + return gpt_get_clk(); } diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c new file mode 100644 index 0000000000..46f8a1e1dc --- /dev/null +++ b/arch/arm/imx-common/video.c @@ -0,0 +1,66 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + + if (!panel) { + for (i = 0; i < display_count; i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect && dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } + } else { + for (i = 0; i < display_count; i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + + if (i < display_count) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + if (displays[i].enable) + displays[i].enable(displays + i); + + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_IMX_HDMI +#include +#include +int detect_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; +} +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 44c1e5dab8..4af6b57e42 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,4 +13,104 @@ #include +#ifdef CONFIG_TI81XX +#include +#endif + +#define LDELAY 1000000 + +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 +#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F + +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4; + s8 m5; + s8 m6; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_dpll; + u32 cm_div_m5_dpll; + u32 cm_div_m6_dpll; +}; + +extern const struct dpll_regs dpll_mpu_regs; +extern const struct dpll_regs dpll_core_regs; +extern const struct dpll_regs dpll_per_regs; +extern const struct dpll_regs dpll_ddr_regs; + +extern struct cm_wkuppll *const cmwkup; + +const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); +const struct dpll_params *get_dpll_ddr_params(void); +void scale_vcores(void); +void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); +void prcm_init(void); +void enable_basic_clocks(void); +void do_enable_clocks(u32 *const *, u32 *const *, u8); + #endif diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h new file mode 100644 index 0000000000..f0699229a3 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -0,0 +1,142 @@ +/* + * ti81xx.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef _CLOCK_TI81XX_H_ +#define _CLOCK_TI81XX_H_ + +#define PRCM_MOD_EN 0x2 + +#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) +#define CM_ALWON_BASE (PRCM_BASE + 0x1400) + +struct cm_def { + unsigned int resv0[2]; + unsigned int l3fastclkstctrl; + unsigned int resv1[1]; + unsigned int pciclkstctrl; + unsigned int resv2[1]; + unsigned int ducaticlkstctrl; + unsigned int resv3[1]; + unsigned int emif0clkctrl; + unsigned int emif1clkctrl; + unsigned int dmmclkctrl; + unsigned int fwclkctrl; + unsigned int resv4[10]; + unsigned int usbclkctrl; + unsigned int resv5[1]; + unsigned int sataclkctrl; + unsigned int resv6[4]; + unsigned int ducaticlkctrl; + unsigned int pciclkctrl; +}; + +struct cm_alwon { + unsigned int l3slowclkstctrl; + unsigned int ethclkstctrl; + unsigned int l3medclkstctrl; + unsigned int mmu_clkstctrl; + unsigned int mmucfg_clkstctrl; + unsigned int ocmc0clkstctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkstctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkstctrl; +#endif + unsigned int mpuclkstctrl; + unsigned int sysclk4clkstctrl; + unsigned int sysclk5clkstctrl; + unsigned int sysclk6clkstctrl; + unsigned int rtcclkstctrl; + unsigned int l3fastclkstctrl; + unsigned int resv0[67]; + unsigned int mcasp0clkctrl; + unsigned int mcasp1clkctrl; + unsigned int mcasp2clkctrl; + unsigned int mcbspclkctrl; + unsigned int uart0clkctrl; + unsigned int uart1clkctrl; + unsigned int uart2clkctrl; + unsigned int gpio0clkctrl; + unsigned int gpio1clkctrl; + unsigned int i2c0clkctrl; + unsigned int i2c1clkctrl; +#if defined(CONFIG_TI814X) + unsigned int mcasp345clkctrl; + unsigned int atlclkctrl; + unsigned int mlbclkctrl; + unsigned int pataclkctrl; + unsigned int resv1[1]; + unsigned int uart3clkctrl; + unsigned int uart4clkctrl; + unsigned int uart5clkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv1[1]; + unsigned int timer1clkctrl; + unsigned int timer2clkctrl; + unsigned int timer3clkctrl; + unsigned int timer4clkctrl; + unsigned int timer5clkctrl; + unsigned int timer6clkctrl; + unsigned int timer7clkctrl; +#endif + unsigned int wdtimerclkctrl; + unsigned int spiclkctrl; + unsigned int mailboxclkctrl; + unsigned int spinboxclkctrl; + unsigned int mmudataclkctrl; + unsigned int resv2[2]; + unsigned int mmucfgclkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv3[2]; +#elif defined(CONFIG_TI816X) + unsigned int resv3[1]; + unsigned int sdioclkctrl; +#endif + unsigned int ocmc0clkctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkctrl; +#endif + unsigned int resv4[2]; + unsigned int controlclkctrl; + unsigned int resv5[2]; + unsigned int gpmcclkctrl; + unsigned int ethernet0clkctrl; + unsigned int ethernet1clkctrl; + unsigned int mpuclkctrl; +#if defined(CONFIG_TI814X) + unsigned int debugssclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv6[1]; +#endif + unsigned int l3clkctrl; + unsigned int l4hsclkctrl; + unsigned int l4lsclkctrl; + unsigned int rtcclkctrl; + unsigned int tpccclkctrl; + unsigned int tptc0clkctrl; + unsigned int tptc1clkctrl; + unsigned int tptc2clkctrl; + unsigned int tptc3clkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv6[4]; + unsigned int dcan01clkctrl; + unsigned int mmchs0clkctrl; + unsigned int mmchs1clkctrl; + unsigned int mmchs2clkctrl; + unsigned int custefuseclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int sr0clkctrl; + unsigned int sr1clkctrl; +#endif +}; + +#endif /* _CLOCK_TI81XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 29b0964bdf..5657f1846a 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -11,17 +11,32 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ +/* MAIN PLL Fdll supported frequencies */ +#define MPUPLL_M_1000 1000 +#define MPUPLL_M_800 800 +#define MPUPLL_M_720 720 +#define MPUPLL_M_600 600 +#define MPUPLL_M_550 550 +#define MPUPLL_M_300 300 + /* MAIN PLL Fdll = 550 MHz, by default */ #ifndef CONFIG_SYS_MPUCLK -#define CONFIG_SYS_MPUCLK 550 +#define CONFIG_SYS_MPUCLK MPUPLL_M_550 #endif #define DISPPLL_M 200 #define DISPPLL_N (OSC - 1) #define DISPPLL_M2 1 -extern void pll_init(void); -extern void enable_emif_clocks(void); +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +#define CM_DLL_CTRL_NO_OVERRIDE 0x0 +#define CM_DLL_READYST 0x4 + extern void enable_dmm_clocks(void); +extern const struct dpll_params dpll_core_opp100; +extern struct dpll_params dpll_mpu_opp100; #endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 0319269b58..3f1da852e5 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -26,7 +26,17 @@ #define TCLR_PRE BIT(5) /* Pre-scaler enable */ #define TCLR_PTV_SHIFT 2 /* Pre-scaler shift value */ #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ +#define TCLR_CE BIT(6) /* compare mode enable */ +#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */ +#define TCLR_TCM BIT(8) /* edge detection of input pin*/ +#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */ +#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/ +#define TCLR_CAPTMODE BIT(13) /* capture mode */ +#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */ +#define TCFG_RESET BIT(0) /* software reset */ +#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ +#define TCFG_IDLEMOD_SHIFT (2) /* power management */ /* device type */ #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) #define TST_DEVICE 0x0 @@ -38,84 +48,57 @@ #define AM335X 0xB944 #define TI81XX 0xB81E #define DEVICE_ID (CTRL_BASE + 0x0600) +#define DEVICE_ID_MASK 0x1FFF + +/* MPU max frequencies */ +#define AM335X_ZCZ_300 0x1FEF +#define AM335X_ZCZ_600 0x1FAF +#define AM335X_ZCZ_720 0x1F2F +#define AM335X_ZCZ_800 0x1E2F +#define AM335X_ZCZ_1000 0x1C2F +#define AM335X_ZCE_300 0x1FDF +#define AM335X_ZCE_600 0x1F9F /* This gives the status of the boot mode pins on the evm */ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2) | \ BIT(3) | BIT(4)) -/* Reset control */ -#ifdef CONFIG_AM33XX -#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) -#elif defined(CONFIG_TI814X) -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#endif -#define PRM_RSTST (PRM_RSTCTRL + 8) #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 +/* + * Watchdog: + * Using the prescaler, the OMAP watchdog could go for many + * months before firing. These limits work without scaling, + * with the 60 second default assumed by most tools and docs. + */ +#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ +#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ +#define TIMER_MARGIN_MIN 1 + +#define PTV 0 /* prescale */ +#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<clkseldpll##p), \ @@ -349,7 +593,6 @@ void init_timer(void); unsigned long __clk_get_rate(u32 m_n, u32 div_m2); -unsigned long lcdc_clk_rate(void); unsigned long mpu_clk_rate(void); #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index d8e9ee62aa..719f3e2290 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -22,7 +22,11 @@ #define VTP_CTRL_FILTER(n) (((n) << VTP_CTRL_FILTER_SHIFT) & VTP_CTRL_FILTER_MASK) #define VTP_CTRL_START_EN (0x1 << 0) #define PHY_DLL_LOCK_DIFF 0x0 +#ifdef CONFIG_AM43XX +#define DDR_CKE_CTRL_NORMAL 0x3 +#else #define DDR_CKE_CTRL_NORMAL 0x1 +#endif #define PHY_EN_DYN_PWRDN (0x1 << 20) /* Micron MT47H128M16RT-25E */ @@ -32,27 +36,20 @@ #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a -#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 #define MT47H128M16RT25E_RATIO 0x80 -#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_RD_DQS 0x12 -#define MT47H128M16RT25E_WR_DQS 0x00 -#define MT47H128M16RT25E_PHY_WRLVL 0x00 -#define MT47H128M16RT25E_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 -#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B /* Micron MT41J128M16JT-125 */ -#define MT41J128MJT125_EMIF_READ_LATENCY 0x06 +#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B #define MT41J128MJT125_EMIF_TIM2 0x26337FDA #define MT41J128MJT125_EMIF_TIM3 0x501F830F #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 #define MT41J128MJT125_EMIF_SDREF 0x0000093B #define MT41J128MJT125_ZQ_CFG 0x50074BE4 -#define MT41J128MJT125_DLL_LOCK_DIFF 0x1 #define MT41J128MJT125_RATIO 0x40 #define MT41J128MJT125_INVERT_CLKOUT 0x1 #define MT41J128MJT125_RD_DQS 0x3B @@ -61,15 +58,36 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41K128M16JT-187E */ +#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 +#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB +#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA +#define MT41K128MJT187E_EMIF_TIM3 0x501F830F +#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 +#define MT41K128MJT187E_EMIF_SDREF 0x0000093B +#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 +#define MT41K128MJT187E_RATIO 0x40 +#define MT41K128MJT187E_INVERT_CLKOUT 0x1 +#define MT41K128MJT187E_RD_DQS 0x3B +#define MT41K128MJT187E_WR_DQS 0x85 +#define MT41K128MJT187E_PHY_WR_DATA 0xC1 +#define MT41K128MJT187E_PHY_FIFO_WE 0x100 +#define MT41K128MJT187E_IOCTRL_VALUE 0x18B + +/* Micron MT41J64M16JT-125 */ +#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 + +/* Micron MT41J256M16JT-125 */ +#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 + /* Micron MT41J256M8HX-15E */ -#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 +#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 -#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1 #define MT41J256M8HX15E_RATIO 0x40 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 #define MT41J256M8HX15E_RD_DQS 0x3B @@ -86,7 +104,6 @@ #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 -#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1 #define MT41K256M16HA125E_RATIO 0x80 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 #define MT41K256M16HA125E_RD_DQS 0x38 @@ -96,14 +113,13 @@ #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B /* Micron MT41J512M8RH-125 on EVM v1.5 */ -#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06 +#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 -#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1 #define MT41J512M8RH125_RATIO 0x80 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 #define MT41J512M8RH125_RD_DQS 0x3B @@ -113,22 +129,37 @@ #define MT41J512M8RH125_IOCTRL_VALUE 0x18B /* Samsung K4B2G1646E-BIH9 */ -#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06 -#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B -#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A -#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F -#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2 -#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 +#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B +#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA +#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF +#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 +#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 -#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1 -#define K4B2G1646EBIH9_RATIO 0x40 -#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1 -#define K4B2G1646EBIH9_RD_DQS 0x3B -#define K4B2G1646EBIH9_WR_DQS 0x85 -#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100 -#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1 +#define K4B2G1646EBIH9_RATIO 0x80 +#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 +#define K4B2G1646EBIH9_RD_DQS 0x35 +#define K4B2G1646EBIH9_WR_DQS 0x3A +#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 +#define K4B2G1646EBIH9_PHY_WR_DATA 0x76 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B +#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 +#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 + +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84 + /** * Configure DMM */ @@ -138,6 +169,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs); * Configure SDRAM */ void config_sdram(const struct emif_regs *regs, int nr); +void config_sdram_emif4d5(const struct emif_regs *regs, int nr); /** * Set SDRAM timings @@ -152,18 +184,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr); struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv1[2]; - unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int resv1[3]; unsigned int cm0iclkout; /* offset 0x02C */ unsigned int resv2[8]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[2]; - unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int resv3[3]; unsigned int cm1iclkout; /* offset 0x060 */ unsigned int resv4[8]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[2]; - unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int resv5[3]; unsigned int cm2iclkout; /* offset 0x094 */ unsigned int resv6[3]; }; @@ -195,37 +224,43 @@ struct ddr_data_regs { * correspond to DATA1 registers defined here. */ struct ddr_regs { - unsigned int resv0[7]; - unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv0[3]; + unsigned int cm0config; /* offset 0x00C */ + unsigned int cm0configclk; /* offset 0x010 */ unsigned int resv1[2]; - unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv2[3]; unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv2[8]; + unsigned int resv3[4]; + unsigned int cm1config; /* offset 0x040 */ + unsigned int cm1configclk; /* offset 0x044 */ + unsigned int resv4[2]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[2]; - unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int resv5[3]; unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv4[8]; + unsigned int resv6[4]; + unsigned int cm2config; /* offset 0x074 */ + unsigned int cm2configclk; /* offset 0x078 */ + unsigned int resv7[2]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[2]; - unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int resv8[3]; unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv6[12]; + unsigned int resv9[12]; unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int resv7[4]; + unsigned int resv10[4]; unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int resv8[4]; + unsigned int resv11[4]; unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int resv9; + unsigned int resv12; unsigned int dt0wimode0; /* offset 0x0F8 */ unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int resv10; + unsigned int resv13; unsigned int dt0gimode0; /* offset 0x104 */ unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int resv11[4]; + unsigned int resv14[4]; unsigned int dt0dqoffset; /* offset 0x11C */ unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int resv12[4]; + unsigned int resv15[4]; unsigned int dt0rdelays0; /* offset 0x134 */ unsigned int dt0dldiff0; /* offset 0x138 */ }; @@ -237,17 +272,14 @@ struct cmd_control { unsigned long cmd0csratio; unsigned long cmd0csforce; unsigned long cmd0csdelay; - unsigned long cmd0dldiff; unsigned long cmd0iclkout; unsigned long cmd1csratio; unsigned long cmd1csforce; unsigned long cmd1csdelay; - unsigned long cmd1dldiff; unsigned long cmd1iclkout; unsigned long cmd2csratio; unsigned long cmd2csforce; unsigned long cmd2csdelay; - unsigned long cmd2dldiff; unsigned long cmd2iclkout; }; @@ -261,8 +293,6 @@ struct ddr_data { unsigned long datagiratio0; unsigned long datafwsratio0; unsigned long datawrsratio0; - unsigned long datauserank0delay; - unsigned long datadldiff0; }; /** @@ -285,12 +315,27 @@ struct ddr_cmdtctrl { unsigned int resv2[12]; unsigned int dt0ioctl; unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int resv3[4]; + unsigned int emif_sdram_config_ext; +}; + +struct ctrl_ioregs { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int emif_sdram_config_ext; }; /** * Configure DDR io control registers */ -void config_io_ctrl(unsigned long val); +void config_io_ctrl(const struct ctrl_ioregs *ioregs); struct ddr_ctrl { unsigned int ddrioctrl; @@ -298,8 +343,9 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/arch/arm/include/asm/arch-am33xx/elm.h deleted file mode 100644 index 45454eaf0f..0000000000 --- a/arch/arm/include/asm/arch-am33xx/elm.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2010-2011 Texas Instruments, - * Mansoor Ahamed - * - * Derived from work done by Rohit Choraria for omap3 - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_ELM_H -#define __ASM_ARCH_ELM_H -/* - * ELM Module Registers - */ - -/* ELM registers bit fields */ -#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) -#define ELM_SYSCONFIG_SOFTRESET (0x2) -#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) -#define ELM_SYSSTATUS_RESETDONE (0x1) -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) -#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) -#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) -#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) -#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) -#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) - -#ifndef __ASSEMBLY__ - -enum bch_level { - BCH_4_BIT = 0, - BCH_8_BIT, - BCH_16_BIT -}; - - -/* BCH syndrome registers */ -struct syndrome { - u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ - u8 res1[36]; /* 0x41c */ -}; - -/* BCH error status & location register */ -struct location { - u32 location_status; /* 0x800 */ - u8 res1[124]; /* 0x804 */ - u32 error_location_x[16]; /* 0x880.... */ - u8 res2[64]; /* 0x8c0 */ -}; - -/* BCH ELM register map - do not try to allocate memmory for this structure. - * We have used plenty of reserved variables to fill the slots in the ELM - * register memory map. - * Directly initialize the struct pointer to ELM base address. - */ -struct elm { - u32 rev; /* 0x000 */ - u8 res1[12]; /* 0x004 */ - u32 sysconfig; /* 0x010 */ - u32 sysstatus; /* 0x014 */ - u32 irqstatus; /* 0x018 */ - u32 irqenable; /* 0x01c */ - u32 location_config; /* 0x020 */ - u8 res2[92]; /* 0x024 */ - u32 page_ctrl; /* 0x080 */ - u8 res3[892]; /* 0x084 */ - struct syndrome syndrome_fragments[8]; /* 0x400 */ - u8 res4[512]; /* 0x600 */ - struct location error_location[8]; /* 0x800 */ -}; - -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, - u32 *error_locations); -int elm_config(enum bch_level level); -void elm_reset(void); -void elm_init(void); -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_ELM_H */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h index 00af799516..3f6365e9e8 100644 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -12,7 +12,19 @@ #define AM33XX_GPIO1_BASE 0x4804C000 #define AM33XX_GPIO2_BASE 0x481AC000 #define AM33XX_GPIO3_BASE 0x481AE000 +#define AM33XX_GPIO4_BASE 0x48320000 +#define AM33XX_GPIO5_BASE 0x48322000 #define AM33XX_GPIO_NR(bank, pin) (((bank) << 5) | (pin)) +/* GPIO CTRL register */ +#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 +#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) +#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK + +/* GPIO OUTPUT ENABLE register */ +#define GPIO_OE_ENABLE(x) (1 << x) + +/* GPIO SETDATAOUT register */ +#define GPIO_SETDATAOUT(x) (1 << x) #endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 02f5f8a8d2..dd950e5ac4 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -15,8 +15,12 @@ #include #ifdef CONFIG_AM33XX #include +#elif defined(CONFIG_TI816X) +#include #elif defined(CONFIG_TI814X) #include +#elif defined(CONFIG_AM43XX) +#include #endif /* @@ -44,38 +48,18 @@ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000 -/* PLL related registers */ -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 -#define CM_DPLL 0x44E00500 -#define CM_DEVICE 0x44E00700 -#define CM_RTC 0x44E00800 -#define CM_CEFUSE 0x44E00A00 -#define PRM_DEVICE 0x44E00F00 - -/* VTP Base address */ -#define VTP1_CTRL_ADDR 0x48140E10 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 /* UART */ #define DEFAULT_UART_BASE UART0_BASE -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - /* GPMC Base address */ #define GPMC_BASE 0x50000000 /* CPSW Config space */ #define CPSW_BASE 0x4A100000 -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - +int clk_get(int clk); #endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 432f0c7644..d1aed58503 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -28,19 +28,44 @@ /* PRCM Base Address */ #define PRCM_BASE 0x44E00000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800 + +#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) +#define PRM_RSTST (PRM_RSTCTRL + 8) /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 +#define PRM_DEVICE_INST 0x44E00F00 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 2 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A101000 /* RTC base address */ #define RTC_BASE 0x44E3E000 +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + +/* LCD Controller */ +#define LCD_CNTL_BASE 0x4830E000 + +/* PWMSS */ +#define PWMSS0_BASE 0x48300000 +#define AM33XX_ECAP0_BASE 0x48300100 + #endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h new file mode 100644 index 0000000000..29e3816c1a --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -0,0 +1,89 @@ +/* + * hardware_am43xx.h + * + * AM43xx hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AM43XX_HARDWARE_AM43XX_H +#define __AM43XX_HARDWARE_AM43XX_H + +/* Module base addresses */ + +/* L3 Fast Configuration Bandwidth Limiter Base Address */ +#define L3F_CFG_BWLIMITER 0x44005200 + +/* UART Base Address */ +#define UART0_BASE 0x44E09000 + +/* GPIO Base address */ +#define GPIO2_BASE 0x481AC000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44DF0000 +#define CM_WKUP 0x44DF2800 +#define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44DF8500 + +#define PRM_RSTCTRL (PRCM_BASE + 0x4000) +#define PRM_RSTST (PRM_RSTCTRL + 4) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 + +/* USB CTRL Base Address */ +#define USB1_CTRL 0x44e10628 +#define USB1_CTRL_CM_PWRDN BIT(0) +#define USB1_CTRL_OTG_PWRDN BIT(1) + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 +#define DDR_DATA_REGS_NR 2 + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A101000 + +/* RTC base address */ +#define RTC_BASE 0x44E3E000 + +/* USB Clock Control */ +#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) +#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) +#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) + +#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) +#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) +#define USBPHYOCPSCP_MODULE_EN (1 << 1) +#define CM_DEVICE_INST 0x44df4100 +#define PRM_DEVICE_INST 0x44df4000 + +/* Control status register */ +#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 +#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) +#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 +#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) +#define CTRL_SYSBOOT_15_14_SHIFT 22 + +#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 +#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 + +#define NUM_CRYSTAL_FREQ 0x4 + +#endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 451d935b1d..4509a237df 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -25,22 +25,37 @@ /* PRCM Base Address */ #define PRCM_BASE 0x48180000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) /* PLL Subsystem Base Address */ #define PLL_SUBSYS_BASE 0x481C5000 /* VTP Base address */ #define VTP0_CTRL_ADDR 0x48140E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x47C0C400 #define DDR_PHY_DATA_ADDR 0x47C0C4C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 4 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A100800 /* RTC base address */ #define RTC_BASE 0x480C0000 +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + #endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h new file mode 100644 index 0000000000..3c680649ab --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -0,0 +1,61 @@ +/* + * hardware_ti816x.h + * + * TI816x hardware specific header + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * Based on TI-PSP-04.00.02.14 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_TI816X_H +#define __AM33XX_HARDWARE_TI816X_H + +/* UART */ +#define UART0_BASE 0x48020000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 + +/* Watchdog Timer */ +#define WDT_BASE 0x480C2000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48198358 +#define VTP1_CTRL_ADDR 0x4819A358 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x48198000 +#define DDR_PHY_DATA_ADDR 0x481980C8 +#define DDR_PHY_CMD_ADDR2 0x4819A000 +#define DDR_PHY_DATA_ADDR2 0x4819A0C8 +#define DDR_DATA_REGS_NR 4 + + +#define DDRPHY_0_CONFIG_BASE 0x48198000 +#define DDRPHY_1_CONFIG_BASE 0x4819A000 +#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ + DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index 8bfa53f41b..8642c8f872 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _I2C_H_ -#define _I2C_H_ +#ifndef _I2C_AM33XX_H_ +#define _I2C_AM33XX_H_ #define I2C_BASE1 0x44E0B000 #define I2C_BASE2 0x4802A000 @@ -62,4 +62,4 @@ struct i2c { #define I2C_IP_CLK 48000000 #define I2C_INTERNAL_SAMPLING_CLK 12000000 -#endif /* _I2C_H_ */ +#endif /* _I2C_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index aef4e82fc7..b2412b56e1 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -30,6 +30,7 @@ * * Currently valid part Names are (PART): * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL */ #define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 @@ -45,23 +46,19 @@ #define M_NAND_GPMC_CONFIG6 0x16000f80 #define M_NAND_GPMC_CONFIG7 0x00000008 +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ #define GPMC_MAX_REG 7 -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 #define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE -#define PISMO1_NAND_SIZE GPMC_SIZE_256M #endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index ae6e5339cf..4274eba6d2 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -28,6 +28,9 @@ #if defined(CONFIG_TI814X) #undef MMC_CLOCK_REFERENCE #define MMC_CLOCK_REFERENCE 192 /* MHz */ +#elif defined(CONFIG_TI816X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 48 /* MHz */ #endif #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 1c6b65f4a0..d8bf87258b 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -23,6 +23,10 @@ #include #elif defined(CONFIG_TI814X) #include +#elif defined(CONFIG_TI816X) +#include +#elif defined(CONFIG_AM43XX) +#include #endif struct module_pin_mux { @@ -32,7 +36,7 @@ struct module_pin_mux { /* Pad control register offset */ #define PAD_CTRL_BASE 0x800 -#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ +#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\ (PAD_CTRL_BASE))->x) /* diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h new file mode 100644 index 0000000000..98fc2b50da --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -0,0 +1,187 @@ +/* + * mux_am43xx.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MUX_AM43XX_H_ +#define _MUX_AM43XX_H_ + +#include +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 19) +#define RXACTIVE (0x1 << 18) +#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ +#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; +}; + +#endif /* _MUX_AM43XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h new file mode 100644 index 0000000000..e4e5a48ad6 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h @@ -0,0 +1,363 @@ +/* + * mux_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI816X_H_ +#define _MUX_TI816X_H_ + +#include +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) /* used for Readability */ + + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; + int pincntl271; + int pincntl272; + int pincntl273; + int pincntl274; + int pincntl275; + int pincntl276; + int pincntl277; + int pincntl278; + int pincntl279; + int pincntl280; + int pincntl281; + int pincntl282; + int pincntl283; + int pincntl284; + int pincntl285; + int pincntl286; + int pincntl287; + int pincntl288; + int pincntl289; + int pincntl290; + int pincntl291; + int pincntl292; + int pincntl293; + int pincntl294; + int pincntl295; + int pincntl296; + int pincntl297; + int pincntl298; + int pincntl299; + int pincntl300; + int pincntl301; + int pincntl302; + int pincntl303; + int pincntl304; + int pincntl305; + int pincntl306; + int pincntl307; + int pincntl308; + int pincntl309; + int pincntl310; + int pincntl311; + int pincntl312; + int pincntl313; + int pincntl314; + int pincntl315; + int pincntl316; + int pincntl317; + int pincntl318; + int pincntl319; + int pincntl320; + int pincntl321; + int pincntl322; + int pincntl323; +}; + +#endif /* endif _MUX_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 66c61e54f4..e5c0b0d08f 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -15,18 +15,22 @@ #ifndef _OMAP_H_ #define _OMAP_H_ -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 -#elif defined(CONFIG_TI814X) +#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800 +#elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define SRAM_SCRATCH_SPACE_ADDR 0x4031B800 +#elif defined(CONFIG_AM43XX) +#define NON_SECURE_SRAM_START 0x402F0400 +#define NON_SECURE_SRAM_END 0x40340000 +#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC +#define AM4372_BOARD_VERSION_START SRAM_SCRATCH_SPACE_ADDR + 0xD +#define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14 +#define QSPI_BASE 0x47900000 #endif #endif diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h deleted file mode 100644 index 00ad1d0672..0000000000 --- a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */ -#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\ - .eccbytes = 32,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33},\ - .oobfree = {\ - {.offset = 34,\ - .length = 30 } } \ -} - -#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ - .eccbytes = 56,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\ - 52, 53, 54, 55, 56, 57},\ - .oobfree = {\ - {.offset = 58,\ - .length = 6 } } \ -} - -#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\ - .eccbytes = 104,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\ - 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\ - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\ - 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\ - 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\ - 100, 101, 102, 103, 104, 105},\ - .oobfree = {\ - {.offset = 106,\ - .length = 8 } } \ -} -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index e428512b17..e756418a59 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -5,11 +5,28 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ +#if defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_MMC2 5 +#define BOOT_DEVICE_UART 0x43 +#elif defined(CONFIG_AM43XX) +#define BOOT_DEVICE_NOR 1 +#define BOOT_DEVICE_NAND 5 +#define BOOT_DEVICE_MMC1 7 +#define BOOT_DEVICE_MMC2 8 +#define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_USB 13 +#define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_CPGMAC 71 +#else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 -#ifdef CONFIG_AM33XX +#define BOOT_DEVICE_NAND_I2C 6 +#if defined(CONFIG_AM33XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #elif defined(CONFIG_TI814X) @@ -20,12 +37,20 @@ #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 +#endif #define BOOT_DEVICE_MMC2_2 0xFF -#ifdef CONFIG_AM33XX -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#elif defined(CONFIG_TI814X) +#if defined(CONFIG_AM33XX) +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#elif defined(CONFIG_AM43XX) +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#ifdef CONFIG_SPL_USB_SUPPORT +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB +#else +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#endif +#elif defined(CONFIG_TI81XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 #endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 1424f90bfa..7eacf27a93 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -10,16 +10,13 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ - -#define BOARD_REV_ID 0x0 +#include +#include +#include u32 get_cpu_rev(void); u32 get_sysboot_value(void); -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void); -#endif - extern struct ctrl_stat *cstat; u32 get_device_type(void); void save_omap_boot_params(void); @@ -35,6 +32,14 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size); void omap_nand_switch_ecc(uint32_t, uint32_t); -void rtc32k_enable(void); -void uart_soft_reset(void); +void set_uart_mux_conf(void); +void set_mux_conf_regs(void); +void sdram_init(void); +u32 wait_on_value(u32, u32, void *, u32); +#ifdef CONFIG_NOR_BOOT +void enable_norboot_pin_mux(void); +#endif +void am33xx_spl_board_init(void); +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); #endif diff --git a/arch/arm/include/asm/arch-armada-xp/config.h b/arch/arm/include/asm/arch-armada-xp/config.h new file mode 100644 index 0000000000..00ee775a45 --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/config.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor + * Written-by: Lei Wen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file should be included in board config header file. + * + * It supports common definitions for Armada XP platforms + */ + +#ifndef _ARMADA_XP_CONFIG_H +#define _ARMADA_XP_CONFIG_H + +#include + +#define MV88F78X60 /* for the DDR training bin_hdr code */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * By default kwbimage.cfg from board specific folder is used + * If for some board, different configuration file need to be used, + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file + */ +#ifndef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#endif /* CONFIG_SYS_KWD_CONFIG */ + +/* Add target to build it automatically upon "make" */ +#define CONFIG_BUILD_TARGET "u-boot.kwb" + +/* end of 16M scrubbed by training in bootrom */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 +#define CONFIG_NR_DRAM_BANKS_MAX 2 + +#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE + +/* + * SPI Flash configuration + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS 0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_PHYLIB +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#endif /* CONFIG_CMD_NET */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#ifndef CONFIG_SYS_I2C_SOFT +#define CONFIG_I2C_MVTWSI +#endif +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#endif /* _ARMADA_XP_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/include/asm/arch-armada-xp/cpu.h new file mode 100644 index 0000000000..6b60c21ceb --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/cpu.h @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARMADA_XP_CPU_H +#define _ARMADA_XP_CPU_H + +#include + +#ifndef __ASSEMBLY__ + +#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) +#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum cpu_winen { + CPU_WIN_DISABLE, + CPU_WIN_ENABLE +}; + +enum cpu_target { + CPU_TARGET_DRAM = 0x0, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, + CPU_TARGET_ETH23 = 0x3, + CPU_TARGET_PCIE02 = 0x4, + CPU_TARGET_ETH01 = 0x7, + CPU_TARGET_PCIE13 = 0x8, + CPU_TARGET_SASRAM = 0x9, + CPU_TARGET_NAND = 0xd, +}; + +enum cpu_attrib { + CPU_ATTR_SASRAM = 0x01, + CPU_ATTR_DRAM_CS0 = 0x0e, + CPU_ATTR_DRAM_CS1 = 0x0d, + CPU_ATTR_DRAM_CS2 = 0x0b, + CPU_ATTR_DRAM_CS3 = 0x07, + CPU_ATTR_NANDFLASH = 0x2f, + CPU_ATTR_SPIFLASH = 0x1e, + CPU_ATTR_BOOTROM = 0x1d, + CPU_ATTR_PCIE_IO = 0xe0, + CPU_ATTR_PCIE_MEM = 0xe8, + CPU_ATTR_DEV_CS0 = 0x3e, + CPU_ATTR_DEV_CS1 = 0x3d, + CPU_ATTR_DEV_CS2 = 0x3b, + CPU_ATTR_DEV_CS3 = 0x37, +}; + +/* + * Default Device Address MAP BAR values + */ +#define DEFADR_PCI_MEM 0x90000000 +#define DEFADR_PCI_IO 0xC0000000 +#define DEFADR_SPIF 0xF4000000 +#define DEFADR_BOOTROM 0xF8000000 + +struct mbus_win { + u32 base; + u32 size; + u8 target; + u8 attr; +}; + +/* + * System registers + * Ref: Datasheet sec:A.28 + */ +struct mvebu_system_registers { + u8 pad1[0x60]; + u32 rstoutn_mask; /* 0x60 */ + u32 sys_soft_rst; /* 0x64 */ +}; + +/* + * GPIO Registers + * Ref: Datasheet sec:A.19 + */ +struct kwgpio_registers { + u32 dout; + u32 oe; + u32 blink_en; + u32 din_pol; + u32 din; + u32 irq_cause; + u32 irq_mask; + u32 irq_level; +}; + +/* + * functions + */ +unsigned int mvebu_sdram_bar(enum memory_bank bank); +unsigned int mvebu_sdram_bs(enum memory_bank bank); +void mvebu_sdram_size_adjust(enum memory_bank bank); +int mvebu_mbus_probe(struct mbus_win windows[], int count); +#endif /* __ASSEMBLY__ */ +#endif /* _ARMADA_XP_CPU_H */ diff --git a/arch/arm/include/asm/arch-armada-xp/soc.h b/arch/arm/include/asm/arch-armada-xp/soc.h new file mode 100644 index 0000000000..963e7ac5b7 --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/soc.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Header file for the Marvell's Feroceon CPU core. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_ARMADA_XP_H +#define _ASM_ARCH_ARMADA_XP_H + +#define SOC_MV78460_ID 0x7846 + +/* TCLK Core Clock definition */ +#ifndef CONFIG_SYS_TCLK +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#endif + +/* SOC specific definations */ +#define INTREG_BASE 0xd0000000 +#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) +#define SOC_REGS_PHY_BASE 0xf1000000 +#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) + +#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) +#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) +#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) +#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000)) +#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100)) +#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) +#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) +#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) +#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) +#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) +#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) +#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) +#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) +#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) +#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) +#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) +#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) +#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) + +#define SDRAM_MAX_CS 4 +#define SDRAM_ADDR_MASK 0xFF000000 + +/* Armada XP GbE controller has 4 ports */ +#define MAX_MVNETA_DEVS 4 + +/* Kirkwood CPU memory windows */ +#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA +#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE +#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE + +#endif /* _ASM_ARCH_ARMADA_XP_H */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index 532411e1c3..e062da18b1 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -16,7 +16,6 @@ #define _ARMD1_CONFIG_H #include -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ /* default Dcache Line length for armada100 */ #define CONFIG_SYS_CACHELINE_SIZE 32 diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h index b86ab691f2..a0412bd340 100644 --- a/arch/arm/include/asm/arch-armv7/systimer.h +++ b/arch/arm/include/asm/arch-armv7/systimer.h @@ -14,6 +14,8 @@ #define SYSTIMER_RELOAD 0xFFFFFFFF #define SYSTIMER_EN (1 << 7) #define SYSTIMER_32BIT (1 << 1) +#define SYSTIMER_PRESC_16 (1 << 2) +#define SYSTIMER_PRESC_256 (1 << 3) struct systimer { u32 timer0load; /* 0x00 */ diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index d6597023c6..912e55c8de 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -10,6 +10,7 @@ #define AT91_COMMON_H void at91_can_hw_init(void); +void at91_gmac_hw_init(void); void at91_macb_hw_init(void); void at91_mci_hw_init(void); void at91_serial0_hw_init(void); @@ -18,7 +19,19 @@ void at91_serial2_hw_init(void); void at91_seriald_hw_init(void); void at91_spi0_hw_init(unsigned long cs_mask); void at91_spi1_hw_init(unsigned long cs_mask); +void at91_udp_hw_init(void); void at91_uhp_hw_init(void); void at91_lcd_hw_init(void); +void at91_plla_init(u32 pllar); +void at91_pllb_init(u32 pllar); +void at91_mck_init(u32 mckr); +void at91_pmc_init(void); +void mem_init(void); +void at91_phy_reset(void); +void at91_sdram_hw_init(void); +void at91_mck_init(u32 mckr); +void at91_spl_board_init(void); +void at91_disable_wdt(void); +void matrix_init(void); #endif /* AT91_COMMON_H */ diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 676f024e47..50464ffe8e 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -151,37 +151,4 @@ int at91_get_pio_value(unsigned port, unsigned pin); #define AT91_PIO_PORTD 0x3 #define AT91_PIO_PORTE 0x4 -#ifdef CONFIG_AT91_LEGACY - -#define PIO_PER 0x00 /* Enable Register */ -#define PIO_PDR 0x04 /* Disable Register */ -#define PIO_PSR 0x08 /* Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Register */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pull-up Status Register */ -#define PIO_ASR 0x70 /* Peripheral A Select Register */ -#define PIO_BSR 0x74 /* Peripheral B Select Register */ -#define PIO_ABSR 0x78 /* AB Status Register */ -#define PIO_OWER 0xa0 /* Output Write Enable Register */ -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ -#define PIO_OWSR 0xa8 /* Output Write Status Register */ -#endif - #endif diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h index d314b062bf..56724f15e7 100644 --- a/arch/arm/include/asm/arch-at91/at91_pit.h +++ b/arch/arm/include/asm/arch-at91/at91_pit.h @@ -25,20 +25,4 @@ typedef struct at91_pit { #define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff) #define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK) -#ifdef CONFIG_AT91_LEGACY - -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ - -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ - -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ - -#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index 003920cd84..53b5b2e0fb 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -14,13 +14,15 @@ #ifndef AT91_PMC_H #define AT91_PMC_H +#ifdef __ASSEMBLY__ + #define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20) #define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28) #define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c) #define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30) #define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68) -#ifndef __ASSEMBLY__ +#else #include @@ -52,7 +54,7 @@ typedef struct at91_pmc { u32 reserved5[21]; u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ -#ifdef CONFIG_SAMA5D3 +#ifdef CPU_HAS_PCR u32 reserved6[8]; u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */ u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */ @@ -68,12 +70,19 @@ typedef struct at91_pmc { #define AT91_PMC_MOR_MOSCEN 0x01 #define AT91_PMC_MOR_OSCBYPASS 0x02 +#define AT91_PMC_MOR_MOSCRCEN 0x08 #define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) +#define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16) +#define AT91_PMC_MOR_MOSCSEL (1 << 24) #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) #define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) +#else #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) +#endif #define AT91_PMC_PLLAR_29 0x20000000 #define AT91_PMC_PLLBR_USBDIV_1 0x00000000 #define AT91_PMC_PLLBR_USBDIV_2 0x10000000 @@ -88,7 +97,7 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 -#ifdef CONFIG_SAMA5D3 +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) #define AT91_PMC_MCKR_PRES_1 0x00000000 #define AT91_PMC_MCKR_PRES_2 0x00000010 #define AT91_PMC_MCKR_PRES_4 0x00000020 @@ -117,15 +126,18 @@ typedef struct at91_pmc { #else #define AT91_PMC_MCKR_MDIV_1 0x00000000 #define AT91_PMC_MCKR_MDIV_2 0x00000100 -#ifdef CONFIG_SAMA5D3 +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) #define AT91_PMC_MCKR_MDIV_3 0x00000300 #endif #define AT91_PMC_MCKR_MDIV_4 0x00000200 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 #endif -#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 -#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 +#define AT91_PMC_MCKR_PLLADIV_MASK 0x00003000 +#define AT91_PMC_MCKR_PLLADIV_1 0x00000000 +#define AT91_PMC_MCKR_PLLADIV_2 0x00001000 + +#define AT91_PMC_MCKR_H32MXDIV 0x01000000 #define AT91_PMC_IXR_MOSCS 0x00000001 #define AT91_PMC_IXR_LOCKA 0x00000002 @@ -136,13 +148,11 @@ typedef struct at91_pmc { #define AT91_PMC_IXR_PCKRDY1 0x00000200 #define AT91_PMC_IXR_PCKRDY2 0x00000400 #define AT91_PMC_IXR_PCKRDY3 0x00000800 +#define AT91_PMC_IXR_MOSCSELS 0x00010000 -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ - -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ -#endif +#define AT91_PMC_PCR_PID_MASK (0x3f) +#define AT91_PMC_PCR_CMD_WRITE (0x1 << 12) +#define AT91_PMC_PCR_EN (0x1 << 28) #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ @@ -159,34 +169,18 @@ typedef struct at91_pmc { #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ -#endif - #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ -#endif #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ -#endif + #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ -#endif + #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ @@ -198,9 +192,6 @@ typedef struct at91_pmc { #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ -#endif #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ #define AT91_PMC_CSS_SLOW (0 << 0) #define AT91_PMC_CSS_MAIN (1 << 0) @@ -228,21 +219,13 @@ typedef struct at91_pmc { #define AT91_PMC_PDIV_1 (0 << 12) #define AT91_PMC_PDIV_2 (1 << 12) -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */ -#endif #define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ #define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ +#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */ +#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */ #define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */ #define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ - -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ -#endif #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ @@ -253,13 +236,6 @@ typedef struct at91_pmc { #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ -#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ -#endif #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ -#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h index 423cf515d9..a9423428e7 100644 --- a/arch/arm/include/asm/arch-at91/at91_rstc.h +++ b/arch/arm/include/asm/arch-at91/at91_rstc.h @@ -38,4 +38,11 @@ typedef struct at91_rstc { #define AT91_RSTC_SR_NRSTL 0x00010000 +#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ +#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) +#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) +#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) +#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) +#define AT91_RSTC_RSTTYP_USER (4 << 8) + #endif diff --git a/arch/arm/include/asm/arch-at91/at91_shdwn.h b/arch/arm/include/asm/arch-at91/at91_shdwn.h deleted file mode 100644 index 18d9ea690e..0000000000 --- a/arch/arm/include/asm/arch-at91/at91_shdwn.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Shutdown Controller - * Based on AT91SAM9XE datasheet - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_SHDWN_H -#define AT91_SHDWN_H - -#ifndef __ASSEMBLY__ - -struct at91_shdwn { - u32 cr; /* Control Rer. WO */ - u32 mr; /* Mode Register RW 0x00000003 */ - u32 sr; /* Status Register RO 0x00000000 */ -}; - -#endif /* __ASSEMBLY__ */ - -#define AT91_SHDW_CR_KEY 0xa5000000 -#define AT91_SHDW_CR_SHDW 0x00000001 - -#define AT91_SHDW_MR_RTTWKEN 0x00010000 -#define AT91_SHDW_MR_CPTWK0 0x000000f0 -#define AT91_SHDW_MR_WKMODE0H2L 0x00000002 -#define AT91_SHDW_MR_WKMODE0L2H 0x00000001 - -#define AT91_SHDW_SR_RTTWK 0x00010000 -#define AT91_SHDW_SR_WAKEUP0 0x00000001 - -#endif diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h index f44cf67849..b18665b62c 100644 --- a/arch/arm/include/asm/arch-at91/at91_spi.h +++ b/arch/arm/include/asm/arch-at91/at91_spi.h @@ -118,6 +118,6 @@ typedef struct at91_spi { #define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */ -#endif /* CONFIG_AT91_LEGACY */ +#endif /* CONFIG_ATMEL_LEGACY */ #endif diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h index f0f4ed154a..0644bbf3c6 100644 --- a/arch/arm/include/asm/arch-at91/at91_wdt.h +++ b/arch/arm/include/asm/arch-at91/at91_wdt.h @@ -40,25 +40,4 @@ typedef struct at91_wdt { #define AT91_WDT_MR_WDDBGHLT 0x10000000 #define AT91_WDT_MR_WDIDLEHLT 0x20000000 -#ifdef CONFIG_AT91_LEGACY - -#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ -#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ -#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ -#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ -#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ -#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ -#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ -#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ -#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ -#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ - -#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ -#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ -#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ - -#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h index 7ac5bc1e7a..63870bc65d 100644 --- a/arch/arm/include/asm/arch-at91/at91cap9.h +++ b/arch/arm/include/asm/arch-at91/at91cap9.h @@ -55,75 +55,6 @@ #define AT91_RSTC_BASE 0xfffffd00 #define AT91_PIT_BASE 0xfffffd30 -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91CAP9_BASE_UDPHS 0xfff78000 -#define AT91CAP9_BASE_TCB0 0xfff7c000 -#define AT91CAP9_BASE_TC0 0xfff7c000 -#define AT91CAP9_BASE_TC1 0xfff7c040 -#define AT91CAP9_BASE_TC2 0xfff7c080 -#define AT91CAP9_BASE_MCI0 0xfff80000 -#define AT91CAP9_BASE_MCI1 0xfff84000 -#define AT91CAP9_BASE_TWI 0xfff88000 -#define AT91CAP9_BASE_US0 0xfff8c000 -#define AT91CAP9_BASE_US1 0xfff90000 -#define AT91CAP9_BASE_US2 0xfff94000 -#define AT91CAP9_BASE_SSC0 0xfff98000 -#define AT91CAP9_BASE_SSC1 0xfff9c000 -#define AT91CAP9_BASE_AC97C 0xfffa0000 -#define AT91CAP9_BASE_SPI0 0xfffa4000 -#define AT91CAP9_BASE_SPI1 0xfffa8000 -#define AT91CAP9_BASE_CAN 0xfffac000 -#define AT91CAP9_BASE_PWMC 0xfffb8000 -#define AT91CAP9_BASE_EMAC 0xfffbc000 -#define AT91CAP9_BASE_ADC 0xfffc0000 -#define AT91CAP9_BASE_ISI 0xfffc4000 -#define AT91_BASE_SYS 0xffffe200 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) -#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_USART0 AT91CAP9_BASE_US0 -#define AT91_USART1 AT91CAP9_BASE_US1 -#define AT91_USART2 AT91CAP9_BASE_US2 - -/* - * SCKCR flags - */ -#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ -#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ -#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ -#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ -#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) -#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3) - -#endif /* CONFIG_AT91_LEGACY */ /* * Internal Memory. */ diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/include/asm/arch-at91/at91rm9200.h index 25bb071e91..d177bdcae5 100644 --- a/arch/arm/include/asm/arch-at91/at91rm9200.h +++ b/arch/arm/include/asm/arch-at91/at91rm9200.h @@ -7,7 +7,6 @@ #define __AT91RM9200_H__ #define CONFIG_AT91FAMILY /* it's a member of AT91 family */ -#define CONFIG_ARM920T /* it's an ARM920T Core */ #define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */ #define CONFIG_AT91_GPIO /* and require always gpio features */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index 2e902eef3e..8950d67409 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -21,7 +21,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* @@ -95,6 +94,7 @@ #define ATMEL_BASE_SDRAMC 0xffffea00 #define ATMEL_BASE_SMC 0xffffec00 #define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_CCFG 0xffffef14 #define ATMEL_BASE_AIC 0xfffff000 #define ATMEL_BASE_DBGU 0xfffff200 #define ATMEL_BASE_PIOA 0xfffff400 @@ -136,9 +136,11 @@ /* * Other misc defines */ +#ifndef CONFIG_DM_GPIO #define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP #define ATMEL_BASE_PIO ATMEL_BASE_PIOA +#endif +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* * SoC specific defines diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h index 4755fa10bb..dc61f48f52 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h @@ -61,5 +61,10 @@ struct at91_matrix { #define AT91_MATRIX_DBPUC (1 << 8) #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_IOSR_SEL (1 << 17) + +/* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) +#define AT91_MATRIX_SLOT_CYCLE_(x) (x << 0) #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index f7ad11349a..6dfcf4c0c8 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -21,7 +21,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index 3206af8c3e..64a3888e22 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -17,7 +17,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h index 5c98cc70d3..3a076c6b80 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h @@ -25,6 +25,21 @@ #define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) #define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) +#else +struct sdramc_reg { + u32 mr; + u32 tr; + u32 cr; + u32 lpr; + u32 ier; + u32 idr; + u32 imr; + u32 isr; + u32 mdr; +}; + +int sdramc_initialize(unsigned int sdram_address, + const struct sdramc_reg *p); #endif /* SDRAM Controller (SDRAMC) registers */ @@ -62,11 +77,17 @@ #define AT91_SDRAMC_DBW_32 (0 << 7) #define AT91_SDRAMC_DBW_16 (1 << 7) #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ +#define AT91_SDRAMC_TWR_VAL(x) (x << 8) #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRC_VAL(x) (x << 12) #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRP_VAL(x) (x << 16) #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ +#define AT91_SDRAMC_TRCD_VAL(x) (x << 20) #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TRAS_VAL(x) (x << 24) #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ +#define AT91_SDRAMC_TXSR_VAL(x) (x << 28) #define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ @@ -93,5 +114,4 @@ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h index ec5d79735e..d29e98e711 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_smc.h @@ -73,64 +73,4 @@ typedef struct at91_smc { #define AT91_SMC_MODE_PS_16 0x20000000 #define AT91_SMC_MODE_PS_32 0x30000000 -#ifdef CONFIG_AT91_LEGACY - -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#endif - -#endif #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 9cbfc277bd..6df8cdb56d 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -15,7 +15,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h index 00b6aa469f..3a8e6d62ce 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl.h +++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h @@ -17,7 +17,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index fcc6fdc219..36a5cdf476 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -12,6 +12,8 @@ #ifndef __AT91SAM9X5_H__ #define __AT91SAM9X5_H__ +#define CONFIG_AT91FAMILY /* it's a member of AT91 family */ + /* * Peripheral identifiers/interrupts. */ @@ -161,6 +163,12 @@ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP #define ATMEL_ID_UHP ATMEL_ID_UHPHS +/* + * PMECC table in ROM + */ +#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 + /* * at91sam9x5 specific prototypes */ diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h new file mode 100644 index 0000000000..130a85abee --- /dev/null +++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_MPDDRC_H__ +#define __ATMEL_MPDDRC_H__ + +/* + * Only define the needed register in mpddr + * If other register needed, will add them later + */ +struct atmel_mpddr { + u32 mr; + u32 rtr; + u32 cr; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 reserved[2]; + u32 md; +}; + +int ddr2_init(const unsigned int ram_address, + const struct atmel_mpddr *mpddr); + +/* Bit field in mode register */ +#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 +#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 +#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 +#define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 +#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 +#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 +#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 +#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 + +/* Bit field in configuration register */ +#define ATMEL_MPDDRC_CR_NC_MASK 0x3 +#define ATMEL_MPDDRC_CR_NC_COL_9 0x0 +#define ATMEL_MPDDRC_CR_NC_COL_10 0x1 +#define ATMEL_MPDDRC_CR_NC_COL_11 0x2 +#define ATMEL_MPDDRC_CR_NC_COL_12 0x3 +#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) +#define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) +#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) +#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) +#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) +#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) +#define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) +#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) +#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) +#define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) +#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) +#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) + +/* Bit field in timing parameter 0 register */ +#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 +#define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 +#define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 +#define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 +#define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 +#define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 +#define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 +#define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 +#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 +#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 +#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 +#define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf + +/* Bit field in timing parameter 1 register */ +#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 +#define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f +#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 +#define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff +#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 +#define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff +#define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 +#define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf + +/* Bit field in timing parameter 2 register */ +#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 +#define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf +#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 +#define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf +#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 +#define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf +#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 +#define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 +#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 +#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf + +/* Bit field in Memory Device Register */ +#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 +#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 +#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) +#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) +#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) + +#endif diff --git a/arch/arm/include/asm/arch-at91/atmel_serial.h b/arch/arm/include/asm/arch-at91/atmel_serial.h new file mode 100644 index 0000000000..5bc094b355 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/atmel_serial.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ATMEL_SERIAL_H +#define _ATMEL_SERIAL_H + +/* Information about a serial port */ +struct atmel_serial_platdata { + uint32_t base_addr; +}; + +#endif diff --git a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h new file mode 100644 index 0000000000..38b5012fce --- /dev/null +++ b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2005-2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_USBA_UDC_H__ +#define __ATMEL_USBA_UDC_H__ + +#include + +#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ + [idx] = { \ + .name = nam, \ + .index = idx, \ + .fifo_size = maxpkt, \ + .nr_banks = maxbk, \ + .can_dma = dma, \ + .can_isoc = isoc, \ + } + +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9X5) +static struct usba_ep_data usba_udc_ep[] = { + EP("ep0", 0, 64, 1, 0, 0), + EP("ep1", 1, 1024, 2, 1, 1), + EP("ep2", 2, 1024, 2, 1, 1), + EP("ep3", 3, 1024, 3, 1, 0), + EP("ep4", 4, 1024, 3, 1, 0), + EP("ep5", 5, 1024, 3, 1, 1), + EP("ep6", 6, 1024, 3, 1, 1), +}; +#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +static struct usba_ep_data usba_udc_ep[] = { + EP("ep0", 0, 64, 1, 0, 0), + EP("ep1", 1, 1024, 3, 1, 0), + EP("ep2", 2, 1024, 3, 1, 0), + EP("ep3", 3, 1024, 2, 1, 0), + EP("ep4", 4, 1024, 2, 1, 0), + EP("ep5", 5, 1024, 2, 1, 0), + EP("ep6", 6, 1024, 2, 1, 0), + EP("ep7", 7, 1024, 2, 1, 0), + EP("ep8", 8, 1024, 2, 0, 0), + EP("ep9", 9, 1024, 2, 0, 0), + EP("ep10", 10, 1024, 2, 0, 0), + EP("ep11", 11, 1024, 2, 0, 0), + EP("ep12", 12, 1024, 2, 0, 0), + EP("ep13", 13, 1024, 2, 0, 0), + EP("ep14", 14, 1024, 2, 0, 0), + EP("ep15", 15, 1024, 2, 0, 0), +}; +#else +# error "NO usba_udc_ep defined" +#endif + +#undef EP + +struct usba_platform_data pdata = { + .num_ep = ARRAY_SIZE(usba_udc_ep), + .ep = usba_udc_ep, +}; + +#endif diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h index ce9e28f11c..1d45e2dc11 100644 --- a/arch/arm/include/asm/arch-at91/clk.h +++ b/arch/arm/include/asm/arch-at91/clk.h @@ -10,6 +10,7 @@ #define __ASM_ARM_ARCH_CLK_H__ #include +#include #include static inline unsigned long get_cpu_clk_rate(void) @@ -48,14 +49,34 @@ static inline u32 get_pllb_init(void) return gd->arch.at91_pllb_usb_init; } +#ifdef CPU_HAS_H32MXDIV +static inline unsigned int get_h32mxdiv(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV; +} +#else +static inline unsigned int get_h32mxdiv(void) +{ + return 0; +} +#endif + static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } static inline unsigned long get_usart_clk_rate(unsigned int dev_id) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) @@ -65,19 +86,37 @@ static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) static inline unsigned long get_spi_clk_rate(unsigned int dev_id) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } static inline unsigned long get_twi_clk_rate(unsigned int dev_id) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } static inline unsigned long get_mci_clk_rate(void) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); +} + +static inline unsigned long get_pit_clk_rate(void) +{ + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } int at91_clock_init(unsigned long main_clock); void at91_periph_clk_enable(int id); +void at91_periph_clk_disable(int id); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h index 0700427fa4..fd3743f6ac 100644 --- a/arch/arm/include/asm/arch-at91/gpio.h +++ b/arch/arm/include/asm/arch-at91/gpio.h @@ -16,7 +16,7 @@ #ifdef CONFIG_ATMEL_LEGACY -#define PIN_BASE 32 +#define PIN_BASE 0 #define MAX_GPIO_BANKS 5 @@ -203,7 +203,7 @@ static inline void *pin_to_controller(unsigned pin) { pin -= PIN_BASE; pin /= 32; - return (void *)(at91_pios[pin]); + return at91_pios[pin]; } static inline unsigned pin_to_mask(unsigned pin) @@ -214,21 +214,51 @@ static inline unsigned pin_to_mask(unsigned pin) /* The following macros are need for backward compatibility */ #define at91_set_GPIO_periph(x, y) \ - at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y) + at91_set_pio_periph(((x) - PIN_BASE) / 32, (x) % 32, y) #define at91_set_A_periph(x, y) \ - at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) + at91_set_a_periph(((x) - PIN_BASE) / 32, (x) % 32, y) #define at91_set_B_periph(x, y) \ - at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y) + at91_set_b_periph(((x) - PIN_BASE) / 32, (x) % 32, y) #define at91_set_gpio_output(x, y) \ - at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) + at91_set_pio_output(((x) - PIN_BASE) / 32, (x) % 32, y) #define at91_set_gpio_input(x, y) \ - at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y) + at91_set_pio_input(((x) - PIN_BASE) / 32, (x) % 32, y) #define at91_set_gpio_value(x, y) \ - at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y) + at91_set_pio_value(((x) - PIN_BASE) / 32, (x) % 32, y) #define at91_get_gpio_value(x) \ - at91_get_pio_value((x - PIN_BASE) / 32,(x % 32)) + at91_get_pio_value(((x) - PIN_BASE) / 32, (x) % 32) #else -#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) -#define at91_get_gpio_value(x) at91_get_pio_value(x) -#endif +#define at91_set_gpio_value(x, y) at91_set_pio_value(at91_gpio_to_port(x), \ + at91_gpio_to_pin(x), y) +#define at91_get_gpio_value(x) at91_get_pio_value(at91_gpio_to_port(x), \ + at91_gpio_to_pin(x)) #endif + +#define GPIO_PIOA_BASE 0 +#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) +#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) +#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) +#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) +#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) +#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) +#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) +#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) + +static inline unsigned at91_gpio_to_port(unsigned gpio) +{ + return gpio / 32; +} + +static inline unsigned at91_gpio_to_pin(unsigned gpio) +{ + return gpio % 32; +} + +/* Platform data for each GPIO port */ +struct at91_port_platdata { + uint32_t base_addr; + const char *bank_name; +}; + +#endif /* __ASM_ARCH_AT91_GPIO_H */ diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index a63f974060..bf0a1bd6a3 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -25,10 +25,10 @@ # include #elif defined(CONFIG_AT91CAP9) # include -#elif defined(CONFIG_AT91X40) -# include #elif defined(CONFIG_SAMA5D3) # include +#elif defined(CONFIG_SAMA5D4) +# include #else # error "Unsupported AT91 processor" #endif diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h index 49bd335102..227ba80825 100644 --- a/arch/arm/include/asm/arch-at91/sama5d3.h +++ b/arch/arm/include/asm/arch-at91/sama5d3.h @@ -16,7 +16,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARMV7 /* ARM A5 Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* @@ -79,6 +78,7 @@ #define ARCH_EXID_SAMA5D33 0x00414300 #define ARCH_EXID_SAMA5D34 0x00414301 #define ARCH_EXID_SAMA5D35 0x00584300 +#define ARCH_EXID_SAMA5D36 0x00004301 #define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3) #define cpu_is_sama5d31() (cpu_is_sama5d3() && \ @@ -89,6 +89,8 @@ (get_extension_chip_id() == ARCH_EXID_SAMA5D34)) #define cpu_is_sama5d35() (cpu_is_sama5d3() && \ (get_extension_chip_id() == ARCH_EXID_SAMA5D35)) +#define cpu_is_sama5d36() (cpu_is_sama5d3() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D36)) /* * User Peripherals physical base addresses. @@ -120,7 +122,7 @@ #define ATMEL_BASE_USART3 0xf8024000 #define ATMEL_BASE_UART1 0xf8028000 #define ATMEL_BASE_EMAC 0xf802c000 -#define ATMEL_BASE_UDHPS 0xf8030000 +#define ATMEL_BASE_UDPHS 0xf8030000 #define ATMEL_BASE_SHA 0xf8034000 #define ATMEL_BASE_AES 0xf8038000 #define ATMEL_BASE_TDES 0xf803c000 @@ -185,14 +187,13 @@ #define ATMEL_PIO_PORTS 5 #define CPU_HAS_PIO3 #define PIO_SCDR_DIV 0x3fff +#define CPU_HAS_PCR /* * PMECC table in ROM */ #define ATMEL_PMECC_INDEX_OFFSET_512 0x10000 #define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000 -#define ATMEL_PMECC_ALPHA_OFFSET_512 0x10000 -#define ATMEL_PMECC_ALPHA_OFFSET_1024 0x18000 /* * SAMA5D3 specific prototypes diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/include/asm/arch-at91/sama5d3_smc.h index c060894f14..a859b6db9b 100644 --- a/arch/arm/include/asm/arch-at91/sama5d3_smc.h +++ b/arch/arm/include/asm/arch-at91/sama5d3_smc.h @@ -14,10 +14,10 @@ #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600) #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604) #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608) -#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x60C) +#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c) +#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610) #else struct at91_cs { - u32 reserved[96]; u32 setup; /* 0x600 SMC Setup Register */ u32 pulse; /* 0x604 SMC Pulse Register */ u32 cycle; /* 0x608 SMC Cycle Register */ @@ -26,6 +26,7 @@ struct at91_cs { }; struct at91_smc { + u32 reserved[384]; struct at91_cs cs[4]; }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-at91/sama5d4.h b/arch/arm/include/asm/arch-at91/sama5d4.h new file mode 100644 index 0000000000..d85156816f --- /dev/null +++ b/arch/arm/include/asm/arch-at91/sama5d4.h @@ -0,0 +1,206 @@ +/* + * Chip-specific header file for the SAMA5D4 SoC + * + * Copyright (C) 2014 Atmel + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SAMA5D4_H +#define __SAMA5D4_H + +/* + * defines to be used in other places + */ +#define CONFIG_AT91FAMILY /* It's a member of AT91 */ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* FIQ Interrupt */ +#define ATMEL_ID_SYS 1 /* System Controller */ +#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */ +#define ATMEL_ID_PIT 3 /* Periodic Interval Timer */ +#define ATMEL_ID_WDT 4 /* Watchdog timer */ +#define ATMEL_ID_PIOD 5 /* Parallel I/O Controller D */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_DMA0 8 /* DMA Controller 0 */ +#define ATMEL_ID_ICM 9 /* Integrity Check Monitor */ +#define ATMEL_ID_PKCC 10 /* Public Key Crypto Controller */ +#define ATMEL_ID_AES 12 /* Advanced Encryption Standard */ +#define ATMEL_ID_AESB 13 /* AES Bridge*/ +#define ATMEL_ID_TDES 14 /* Triple Data Encryption Standard */ +#define ATMEL_ID_SHA 15 /* SHA Signature */ +#define ATMEL_ID_MPDDRC 16 /* MPDDR controller */ +#define ATMEL_ID_MATRIX1 17 /* H32MX, 32-bit AHB Matrix */ +#define ATMEL_ID_MATRIX0 18 /* H64MX, 64-bit AHB Matrix */ +#define ATMEL_ID_VDEC 19 /* Video Decoder */ +#define ATMEL_ID_SBM 20 /* Secure Box Module */ +#define ATMEL_ID_SMC 22 /* Multi-bit ECC interrupt */ +#define ATMEL_ID_PIOA 23 /* Parallel I/O Controller A */ +#define ATMEL_ID_PIOB 24 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 25 /* Parallel I/O Controller C */ +#define ATMEL_ID_PIOE 26 /* Parallel I/O Controller E */ +#define ATMEL_ID_UART0 27 /* UART 0 */ +#define ATMEL_ID_UART1 28 /* UART 1 */ +#define ATMEL_ID_USART2 29 /* USART 2 */ +#define ATMEL_ID_USART3 30 /* USART 3 */ +#define ATMEL_ID_USART4 31 /* USART 4 */ +#define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */ +#define ATMEL_ID_TWI1 33 /* Two-Wire Interface 1 */ +#define ATMEL_ID_TWI2 34 /* Two-Wire Interface 2 */ +#define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */ +#define ATMEL_ID_MCI1 36 /* High Speed Multimedia Card Interface 1 */ +#define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 38 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SPI2 39 /* Serial Peripheral Interface 2 */ +#define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */ +#define ATMEL_ID_TC1 41 /* Timer Counter 1 (ch. 3, 4, 5) */ +#define ATMEL_ID_TC2 42 /* Timer Counter 2 (ch. 6, 7, 8) */ +#define ATMEL_ID_PWMC 43 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_ADC 44 /* Touch Screen ADC Controller */ +#define ATMEL_ID_DBGU 45 /* Debug Unit Interrupt */ +#define ATMEL_ID_UHPHS 46 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 47 /* USB Device High Speed */ +#define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */ +#define ATMEL_ID_SSC1 49 /* Synchronous Serial Controller 1 */ +#define ATMEL_ID_XDMAC1 50 /* DMA Controller 1 */ +#define ATMEL_ID_LCDC 51 /* LCD Controller */ +#define ATMEL_ID_ISI 52 /* Image Sensor Interface */ +#define ATMEL_ID_TRNG 53 /* True Random Number Generator */ +#define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */ +#define ATMEL_ID_GMAC1 55 /* Ethernet MAC 1 */ +#define ATMEL_ID_IRQ 56 /* IRQ Interrupt ID */ +#define ATMEL_ID_SFC 57 /* Fuse Controller */ +#define ATMEL_ID_SECURAM 59 /* Secured RAM */ +#define ATMEL_ID_SMD 61 /* SMD Soft Modem */ +#define ATMEL_ID_TWI3 62 /* Two-Wire Interface 3 */ +#define ATMEL_ID_CATB 63 /* Capacitive Touch Controller */ +#define ATMEL_ID_SFR 64 /* Special Funcion Register */ +#define ATMEL_ID_AIC 65 /* Advanced Interrupt Controller */ +#define ATMEL_ID_SAIC 66 /* Secured Advanced Interrupt Controller */ +#define ATMEL_ID_L2CC 67 /* L2 Cache Controller */ + +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_LCDC 0xf0000000 +#define ATMEL_BASE_DMAC1 0xf0004000 +#define ATMEL_BASE_ISI 0xf0008000 +#define ATMEL_BASE_PKCC 0xf000C000 +#define ATMEL_BASE_MPDDRC 0xf0010000 +#define ATMEL_BASE_DMAC0 0xf0014000 +#define ATMEL_BASE_PMC 0xf0018000 +#define ATMEL_BASE_MATRIX0 0xf001c000 +#define ATMEL_BASE_AESB 0xf0020000 +/* Reserved: 0xf0024000 - 0xf8000000 */ +#define ATMEL_BASE_MCI0 0xf8000000 +#define ATMEL_BASE_UART0 0xf8004000 +#define ATMEL_BASE_SSC0 0xf8008000 +#define ATMEL_BASE_PWMC 0xf800c000 +#define ATMEL_BASE_SPI0 0xf8010000 +#define ATMEL_BASE_TWI0 0xf8014000 +#define ATMEL_BASE_TWI1 0xf8018000 +#define ATMEL_BASE_TC0 0xf801c000 +#define ATMEL_BASE_GMAC0 0xf8020000 +#define ATMEL_BASE_TWI2 0xf8024000 +#define ATMEL_BASE_SFR 0xf8028000 +#define ATMEL_BASE_USART0 0xf802c000 +#define ATMEL_BASE_USART1 0xf8030000 +/* Reserved: 0xf8034000 - 0xfc000000 */ +#define ATMEL_BASE_MCI1 0xfc000000 +#define ATMEL_BASE_UART1 0xfc004000 +#define ATMEL_BASE_USART2 0xfc008000 +#define ATMEL_BASE_USART3 0xfc00c000 +#define ATMEL_BASE_USART4 0xfc010000 +#define ATMEL_BASE_SSC1 0xfc014000 +#define ATMEL_BASE_SPI1 0xfc018000 +#define ATMEL_BASE_SPI2 0xfc01c000 +#define ATMEL_BASE_TC1 0xfc020000 +#define ATMEL_BASE_TC2 0xfc024000 +#define ATMEL_BASE_GMAC1 0xfc028000 +#define ATMEL_BASE_UDPHS 0xfc02c000 +#define ATMEL_BASE_TRNG 0xfc030000 +#define ATMEL_BASE_ADC 0xfc034000 +#define ATMEL_BASE_TWI3 0xfc038000 + +#define ATMEL_BASE_SMC 0xfc05c000 +#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070) +#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500) + +#define ATMEL_BASE_PIOD 0xfc068000 +#define ATMEL_BASE_RSTC 0xfc068600 +#define ATMEL_BASE_PIT 0xfc068630 +#define ATMEL_BASE_WDT 0xfc068640 + +#define ATMEL_BASE_DBGU 0xfc069000 +#define ATMEL_BASE_PIOA 0xfc06a000 +#define ATMEL_BASE_PIOB 0xfc06b000 +#define ATMEL_BASE_PIOC 0xfc06c000 +#define ATMEL_BASE_PIOE 0xfc06d000 +#define ATMEL_BASE_AIC 0xfc06e000 + +/* + * Internal Memory. + */ +#define ATMEL_BASE_ROM 0x00000000 /* Internal ROM base address */ +#define ATMEL_BASE_NFC 0x00100000 /* NFC SRAM */ +#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */ +#define ATMEL_BASE_VDEC 0x00300000 /* Video Decoder Controller */ +#define ATMEL_BASE_UDPHS_FIFO 0x00400000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00600000 /* USB Host controller (EHCI) */ +#define ATMEL_BASE_AXI 0x00700000 +#define ATMEL_BASE_DAP 0x00800000 +#define ATMEL_BASE_SMD 0x00900000 + +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_DDRCS 0x20000000 +#define ATMEL_BASE_CS1 0x60000000 +#define ATMEL_BASE_CS2 0x70000000 +#define ATMEL_BASE_CS3 0x80000000 + +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 5 +#define CPU_HAS_PIO3 +#define PIO_SCDR_DIV 0x3fff +#define CPU_HAS_PCR +#define CPU_HAS_H32MXDIV + +/* sama5d4 series chip id definitions */ +#define ARCH_ID_SAMA5D4 0x8a5c07c0 +#define ARCH_EXID_SAMA5D41 0x00000001 +#define ARCH_EXID_SAMA5D42 0x00000002 +#define ARCH_EXID_SAMA5D43 0x00000003 +#define ARCH_EXID_SAMA5D44 0x00000004 + +#define cpu_is_sama5d4() (get_chip_id() == ARCH_ID_SAMA5D4) +#define cpu_is_sama5d41() (cpu_is_sama5d4() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D41)) +#define cpu_is_sama5d42() (cpu_is_sama5d4() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D42)) +#define cpu_is_sama5d43() (cpu_is_sama5d4() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D43)) +#define cpu_is_sama5d44() (cpu_is_sama5d4() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D44)) + +/* + * No PMECC Galois table in ROM + */ +#define NO_GALOIS_TABLE_IN_ROM + +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +unsigned int has_lcdc(void); +char *get_cpu_name(void); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-bcm281xx/gpio.h b/arch/arm/include/asm/arch-bcm281xx/gpio.h new file mode 100644 index 0000000000..1b40a96ad4 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/gpio.h @@ -0,0 +1,15 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM281XX_GPIO_H +#define __ARCH_BCM281XX_GPIO_H + +/* + * Empty file - cmd_gpio.c requires this. The implementation + * is in drivers/gpio/kona_gpio.c instead of inlined here. + */ + +#endif diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h new file mode 100644 index 0000000000..93ebf3429a --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h @@ -0,0 +1,30 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM281XX_SYSMAP_H + +#define BSC1_BASE_ADDR 0x3e016000 +#define BSC2_BASE_ADDR 0x3e017000 +#define BSC3_BASE_ADDR 0x3e018000 +#define DWDMA_AHB_BASE_ADDR 0x38100000 +#define ESUB_CLK_BASE_ADDR 0x38000000 +#define ESW_CONTRL_BASE_ADDR 0x38200000 +#define GPIO2_BASE_ADDR 0x35003000 +#define HSOTG_BASE_ADDR 0x3f120000 +#define HSOTG_CTRL_BASE_ADDR 0x3f130000 +#define KONA_MST_CLK_BASE_ADDR 0x3f001000 +#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 +#define PMU_BSC_BASE_ADDR 0x3500d000 +#define PWRMGR_BASE_ADDR 0x35010000 +#define SDIO1_BASE_ADDR 0x3f180000 +#define SDIO2_BASE_ADDR 0x3f190000 +#define SDIO3_BASE_ADDR 0x3f1a0000 +#define SDIO4_BASE_ADDR 0x3f1b0000 +#define SECWD_BASE_ADDR 0x3500c000 +#define SECWD2_BASE_ADDR 0x35002f40 +#define TIMER_BASE_ADDR 0x3e00d000 + +#endif diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h index 9a49b6e05e..db42896201 100644 --- a/arch/arm/include/asm/arch-bcm2835/gpio.h +++ b/arch/arm/include/asm/arch-bcm2835/gpio.h @@ -52,4 +52,13 @@ struct bcm2835_gpio_regs { u32 gppudclk[2]; }; +/** + * struct bcm2835_gpio_platdata - GPIO platform description + * + * @base: Base address of GPIO controller + */ +struct bcm2835_gpio_platdata { + unsigned long base; +}; + #endif /* _BCM2835_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 24abe57959..88d2ec11a7 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -119,6 +119,54 @@ struct bcm2835_mbox_tag_hdr { * }; */ +#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 + +/* + * 0x2..0xf from: + * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 + * 0x10, 0x11 from swarren's testing + */ +#define BCM2835_BOARD_REV_B_I2C0_2 0x2 +#define BCM2835_BOARD_REV_B_I2C0_3 0x3 +#define BCM2835_BOARD_REV_B_I2C1_4 0x4 +#define BCM2835_BOARD_REV_B_I2C1_5 0x5 +#define BCM2835_BOARD_REV_B_I2C1_6 0x6 +#define BCM2835_BOARD_REV_A_7 0x7 +#define BCM2835_BOARD_REV_A_8 0x8 +#define BCM2835_BOARD_REV_A_9 0x9 +#define BCM2835_BOARD_REV_B_REV2_d 0xd +#define BCM2835_BOARD_REV_B_REV2_e 0xe +#define BCM2835_BOARD_REV_B_REV2_f 0xf +#define BCM2835_BOARD_REV_B_PLUS 0x10 +#define BCM2835_BOARD_REV_CM 0x11 +#define BCM2835_BOARD_REV_A_PLUS 0x12 + +struct bcm2835_mbox_tag_get_board_rev { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + u32 rev; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003 + +struct bcm2835_mbox_tag_get_mac_address { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + u8 mac[6]; + u8 pad[2]; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 struct bcm2835_mbox_tag_get_arm_mem { @@ -133,6 +181,54 @@ struct bcm2835_mbox_tag_get_arm_mem { } body; }; +#define BCM2835_MBOX_POWER_DEVID_SDHCI 0 +#define BCM2835_MBOX_POWER_DEVID_UART0 1 +#define BCM2835_MBOX_POWER_DEVID_UART1 2 +#define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 +#define BCM2835_MBOX_POWER_DEVID_I2C0 4 +#define BCM2835_MBOX_POWER_DEVID_I2C1 5 +#define BCM2835_MBOX_POWER_DEVID_I2C2 6 +#define BCM2835_MBOX_POWER_DEVID_SPI 7 +#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 + +#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0) +/* Device doesn't exist */ +#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) + +#define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 + +struct bcm2835_mbox_tag_get_power_state { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 device_id; + } req; + struct { + u32 device_id; + u32 state; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 + +#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) +#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) + +struct bcm2835_mbox_tag_set_power_state { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 device_id; + u32 state; + } req; + struct { + u32 device_id; + u32 state; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 #define BCM2835_MBOX_CLOCK_ID_EMMC 1 @@ -350,6 +446,7 @@ struct bcm2835_mbox_tag_overscan { u32 top; u32 bottom; u32 left; + u32 right; } resp; } body; }; diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h new file mode 100644 index 0000000000..5354637cf0 --- /dev/null +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -0,0 +1,25 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_CONFIGS_H +#define __ARCH_CONFIGS_H + +#include + +/* uArchitecture specifics */ + +/* Serial Info */ +/* Post pad 3 bytes after each reg addr */ +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_NS16550_CLK 100000000 +#define CONFIG_SYS_NS16550_CLK_DIV 54 +#define CONFIG_SERIAL_MULTI +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 0x18023000 + +#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h new file mode 100644 index 0000000000..786deaeece --- /dev/null +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -0,0 +1,22 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_CONFIGS_H +#define __ARCH_CONFIGS_H + +#include + +/* uArchitecture specifics */ + +/* Serial Info */ +/* no padding */ +#define CONFIG_SYS_NS16550_REG_SIZE 1 + +#define CONFIG_SYS_NS16550_CLK 0x03b9aca0 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 0x18000300 + +#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h index 7f9c3f6bce..45a325c123 100644 --- a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h +++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h @@ -26,11 +26,8 @@ extern const int lpsc_size; #define dv_maskbits(addr, val) \ writel((readl(addr) & val), addr) -void da850_waitloop(unsigned long loopcnt); -int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult); void da850_lpc_transition(unsigned char pscnum, unsigned char module, unsigned char domain, unsigned char state); -int da850_ddr_setup(void); void da850_psc_init(void); void da850_pinmux_ctl(unsigned long offset, unsigned long mask, unsigned long value); diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h deleted file mode 100644 index 7e19cfeed4..0000000000 --- a/arch/arm/include/asm/arch-davinci/emif_defs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include - -struct davinci_emif_regs { - u_int32_t ercsr; - u_int32_t awccr; - u_int32_t sdbcr; - u_int32_t sdrcr; - u_int32_t ab1cr; - u_int32_t ab2cr; - u_int32_t ab3cr; - u_int32_t ab4cr; - u_int32_t sdtimr; - u_int32_t ddrsr; - u_int32_t ddrphycr; - u_int32_t ddrphysr; - u_int32_t totar; - u_int32_t totactr; - u_int32_t ddrphyid_rev; - u_int32_t sdsretr; - u_int32_t eirr; - u_int32_t eimr; - u_int32_t eimsr; - u_int32_t eimcr; - u_int32_t ioctrlr; - u_int32_t iostatr; - u_int8_t rsvd0[8]; - u_int32_t nandfcr; - u_int32_t nandfsr; - u_int8_t rsvd1[8]; - u_int32_t nandfecc[4]; - u_int8_t rsvd2[60]; - u_int32_t nand4biteccload; - u_int32_t nand4bitecc[4]; - u_int32_t nanderradd1; - u_int32_t nanderradd2; - u_int32_t nanderrval1; - u_int32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) -#define DAVINCI_NANDFCR_CS2NAND (1 << 0) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) (n << 26) -#define DAVINCI_ABCR_WSTROBE(n) (n << 20) -#define DAVINCI_ABCR_WHOLD(n) (n << 17) -#define DAVINCI_ABCR_RSETUP(n) (n << 13) -#define DAVINCI_ABCR_RSTROBE(n) (n << 7) -#define DAVINCI_ABCR_RHOLD(n) (n << 4) -#define DAVINCI_ABCR_TA(n) (n << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 05ecc78768..a4eb0bd89b 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -15,7 +15,7 @@ #define __ASM_ARCH_HARDWARE_H #include -#include +#include #define REG(addr) (*(volatile unsigned int *)(addr)) #define REG_P(addr) ((volatile unsigned int *)(addr)) @@ -478,8 +478,9 @@ struct davinci_syscfg_regs { dv_reg rsvd[13]; dv_reg kick0; dv_reg kick1; - dv_reg rsvd1[53]; + dv_reg rsvd1[52]; dv_reg mstpri[3]; + dv_reg rsvd2; dv_reg pinmux[20]; dv_reg suspsrc; dv_reg chipsig; @@ -596,7 +597,6 @@ static inline enum davinci_clk_ids get_async3_src(void) #if defined(CONFIG_SOC_DM365) #include #include -#include #include #include #include @@ -613,42 +613,4 @@ static inline enum davinci_clk_ids get_async3_src(void) #endif -struct davinci_rtc { - dv_reg second; - dv_reg minutes; - dv_reg hours; - dv_reg day; - dv_reg month; /* 0x10 */ - dv_reg year; - dv_reg dotw; - dv_reg resv1; - dv_reg alarmsecond; /* 0x20 */ - dv_reg alarmminute; - dv_reg alarmhour; - dv_reg alarmday; - dv_reg alarmmonth; /* 0x30 */ - dv_reg alarmyear; - dv_reg resv2[2]; - dv_reg ctrl; /* 0x40 */ - dv_reg status; - dv_reg irq; - dv_reg complsb; - dv_reg compmsb; /* 0x50 */ - dv_reg osc; - dv_reg resv3[2]; - dv_reg scratch0; /* 0x60 */ - dv_reg scratch1; - dv_reg scratch2; - dv_reg kick0r; - dv_reg kick1r; /* 0x70 */ -}; - -#define RTC_STATE_BUSY 0x01 -#define RTC_STATE_RUN 0x02 - -#define RTC_KICK0R_WE 0x83e70b13 -#define RTC_KICK1R_WE 0x95a4f1e0 - -#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) - #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-davinci/i2c_defs.h b/arch/arm/include/asm/arch-davinci/i2c_defs.h index c388dc0024..06da8947b4 100644 --- a/arch/arm/include/asm/arch-davinci/i2c_defs.h +++ b/arch/arm/include/asm/arch-davinci/i2c_defs.h @@ -1,16 +1,13 @@ /* - * (C) Copyright 2004 + * (C) Copyright 2004-2014 * Texas Instruments, * * Some changes copyright (C) 2007 Sergey Kubushyn * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _DAVINCI_I2C_H_ -#define _DAVINCI_I2C_H_ - -#define I2C_WRITE 0 -#define I2C_READ 1 +#ifndef _I2C_DEFS_H_ +#define _I2C_DEFS_H_ #ifndef CONFIG_SOC_DA8XX #define I2C_BASE 0x01c21000 @@ -18,66 +15,4 @@ #define I2C_BASE 0x01c22000 #endif -#define I2C_OA (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_SCLL (I2C_BASE + 0x0c) -#define I2C_SCLH (I2C_BASE + 0x10) -#define I2C_CNT (I2C_BASE + 0x14) -#define I2C_DRR (I2C_BASE + 0x18) -#define I2C_SA (I2C_BASE + 0x1c) -#define I2C_DXR (I2C_BASE + 0x20) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_IV (I2C_BASE + 0x28) -#define I2C_PSC (I2C_BASE + 0x30) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ -#define I2C_INTCODE_SCD 6 /* Stop condition detect */ - - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 5) /* I2C module enable */ -#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ -#define I2C_CON_FREE (1 << 14) /* Free run on emulation */ - -#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ - #endif diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h deleted file mode 100644 index dee1c6f814..0000000000 --- a/arch/arm/include/asm/arch-davinci/nand_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts shamelesly stolen from Linux Kernel source tree. - * - * ------------------------------------------------------------ - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include - -#ifdef CONFIG_SOC_DM646X -#define MASK_CLE 0x80000 -#define MASK_ALE 0x40000 -#else -#define MASK_CLE 0x10 -#define MASK_ALE 0x08 -#endif - -#ifdef CONFIG_SYS_NAND_MASK_CLE -#undef MASK_CLE -#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE -#endif -#ifdef CONFIG_SYS_NAND_MASK_ALE -#undef MASK_ALE -#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE -#endif - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h index 4d45799a66..2d82af554b 100644 --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -23,12 +23,13 @@ extern const struct pinmux_config spi1_pins_scs0[1]; /* UART pin muxer settings */ extern const struct pinmux_config uart0_pins_txrx[2]; +extern const struct pinmux_config uart0_pins_rtscts[2]; extern const struct pinmux_config uart1_pins_txrx[2]; extern const struct pinmux_config uart2_pins_txrx[2]; extern const struct pinmux_config uart2_pins_rtscts[2]; /* EMAC pin muxer settings*/ -extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_rmii[8]; extern const struct pinmux_config emac_pins_rmii_clk_source[1]; extern const struct pinmux_config emac_pins_mii[15]; extern const struct pinmux_config emac_pins_mdio[2]; diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h index 3e9e6065c7..9aa3f4ab27 100644 --- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h +++ b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h @@ -151,6 +151,7 @@ struct davinci_mmc { uint host_caps; /* Host capabilities */ uint voltages; /* Host supported voltages */ uint version; /* MMC Controller version */ + struct mmc_config cfg; }; enum { diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h deleted file mode 100644 index 5aa5d2d019..0000000000 --- a/arch/arm/include/asm/arch-davinci/spl.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ - -#define BOOT_DEVICE_NAND 1 -#define BOOT_DEVICE_SPI 2 -#define BOOT_DEVICE_MMC1 3 -#define BOOT_DEVICE_MMC2 4 /* dummy */ -#define BOOT_DEVICE_MMC2_2 5 /* dummy */ - -#endif diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h index 9e7f2f3480..330493b606 100644 --- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h +++ b/arch/arm/include/asm/arch-ep93xx/ep93xx.h @@ -1,6 +1,9 @@ /* * Cirrus Logic EP93xx register definitions. * + * Copyright (C) 2013 + * Sergey Kostanbaev fairwaves.ru> + * * Copyright (C) 2009 * Matthias Kaehlcke * @@ -287,6 +290,20 @@ struct sdram_regs { #define SDRAM_DEVCFG_CASLAT_2 0x00010000 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 +#define SDRAM_OFF_GLCONFIG 0x0004 +#define SDRAM_OFF_REFRSHTIMR 0x0008 + +#define SDRAM_OFF_DEVCFG0 0x0010 +#define SDRAM_OFF_DEVCFG1 0x0014 +#define SDRAM_OFF_DEVCFG2 0x0018 +#define SDRAM_OFF_DEVCFG3 0x001C + +#define SDRAM_DEVCFG0_BASE 0xC0000000 +#define SDRAM_DEVCFG1_BASE 0xD0000000 +#define SDRAM_DEVCFG2_BASE 0xE0000000 +#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000 +#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000 + #define GLCONFIG_INIT (1 << 0) #define GLCONFIG_MRS (1 << 1) #define GLCONFIG_SMEMBUSY (1 << 5) @@ -295,6 +312,43 @@ struct sdram_regs { #define GLCONFIG_CLKSHUTDOWN (1 << 30) #define GLCONFIG_CKE (1 << 31) +#define EP93XX_SDRAMCTRL 0x80060000 +#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001 +#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002 +#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020 +#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040 +#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000 + +#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF + +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004 + +#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004 +#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008 +#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010 +#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020 +#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040 +#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000 +#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000 +#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000 + /* * 0x80070000 - 0x8007FFFF: Reserved */ @@ -324,6 +378,13 @@ struct smc_regs { }; #endif +#define EP93XX_OFF_SMCBCR0 0x00 +#define EP93XX_OFF_SMCBCR1 0x04 +#define EP93XX_OFF_SMCBCR2 0x08 +#define EP93XX_OFF_SMCBCR3 0x0C +#define EP93XX_OFF_SMCBCR6 0x18 +#define EP93XX_OFF_SMCBCR7 0x1C + #define SMC_BCR_IDCY_SHIFT 0 #define SMC_BCR_WST1_SHIFT 5 #define SMC_BCR_BLE (1 << 10) @@ -445,6 +506,14 @@ struct gpio_regs { }; #endif +#define EP93XX_LED_DATA 0x80840020 +#define EP93XX_LED_GREEN_ON 0x0001 +#define EP93XX_LED_RED_ON 0x0002 + +#define EP93XX_LED_DDR 0x80840024 +#define EP93XX_LED_GREEN_ENABLE 0x0001 +#define EP93XX_LED_RED_ENABLE 0x00020000 + /* * 0x80850000 - 0x8087FFFF: Reserved */ @@ -519,6 +588,9 @@ struct gpio_regs { #define SYSCON_OFFSET 0x930000 #define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) +/* Security */ +#define SECURITY_EXTENSIONID 0x80832714 + #ifndef __ASSEMBLY__ struct syscon_regs { uint32_t pwrsts; @@ -553,7 +625,11 @@ struct syscon_regs { #define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) #endif +#define SYSCON_OFF_CLKSET1 0x0020 +#define SYSCON_OFF_SYSCFG 0x009c + #define SYSCON_PWRCNT_UART_BAUD (1 << 29) +#define SYSCON_PWRCNT_USH_EN (1 << 28) #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 @@ -571,6 +647,8 @@ struct syscon_regs { #define SYSCON_CHIPID_REV_MASK 0xF0000000 #define SYSCON_DEVICECFG_SWRST (1 << 31) +#define SYSCON_SYSCFG_LASDO 0x00000020 + /* * 0x80930000 - 0x8093FFFF: Watchdog Timer */ @@ -580,3 +658,10 @@ struct syscon_regs { /* * 0x80950000 - 0x9000FFFF: Reserved */ + +/* + * During low_level init we store memory layout in memory at specific location + */ +#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000 +#define UBOOT_MEMORYCNF_BANK_MASK 0x2004 +#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008 diff --git a/arch/arm/include/asm/arch-exynos/board.h b/arch/arm/include/asm/arch-exynos/board.h new file mode 100644 index 0000000000..1b1cd0dd9e --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/board.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2013 Samsung Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EXYNOS_BOARD_H +#define _EXYNOS_BOARD_H + +/* + * Exynos baord specific changes for + * board_init + */ +int exynos_init(void); + +/* + * Exynos board specific changes for + * board_early_init_f + */ +int exynos_early_init_f(void); + +/* + * Exynos board specific changes for + * board_power_init + */ +int exynos_power_init(void); + +#endif /* EXYNOS_BOARD_H */ diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 71075bd533..db24dc0e89 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -14,6 +14,13 @@ #define HPLL 3 #define VPLL 4 #define BPLL 5 +#define RPLL 6 +#define SPLL 7 + +#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) +#define MASK_RATIO(x) (0xf << (x << 4)) +#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8)) +#define SET_RATIO(x, y) ((y & 0xf) << (x << 4)) enum pll_src_bit { EXYNOS_SRC_MPLL = 6, @@ -31,8 +38,9 @@ void set_mmc_clk(int dev_index, unsigned int div); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void); -void set_i2s_clk_source(void); -int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); +int set_i2s_clk_source(unsigned int i2s_id); +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, + unsigned int i2s_id); int set_epll_clk(unsigned long rate); int set_spi_clk(int periph_id, unsigned int rate); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 2b97b9a042..8259b92b8e 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -858,6 +858,500 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; +struct exynos5420_clock { + unsigned int apll_lock; /* 0x10010000 */ + unsigned char res1[0xfc]; + unsigned int apll_con0; + unsigned int apll_con1; + unsigned char res2[0xf8]; + unsigned int src_cpu; + unsigned char res3[0x1fc]; + unsigned int mux_stat_cpu; + unsigned char res4[0xfc]; + unsigned int div_cpu0; /* 0x10010500 */ + unsigned int div_cpu1; + unsigned char res5[0xf8]; + unsigned int div_stat_cpu0; + unsigned int div_stat_cpu1; + unsigned char res6[0xf8]; + unsigned int gate_bus_cpu; + unsigned char res7[0xfc]; + unsigned int gate_sclk_cpu; + unsigned char res8[0x1fc]; + unsigned int clkout_cmu_cpu; /* 0x10010a00 */ + unsigned int clkout_cmu_cpu_div_stat; + unsigned char res9[0x5f8]; + unsigned int armclk_stopctrl; + unsigned char res10[0x4]; + unsigned int arm_ema_ctrl; + unsigned int arm_ema_status; + unsigned char res11[0x10]; + unsigned int pwr_ctrl; + unsigned int pwr_ctrl2; + unsigned char res12[0xd8]; + unsigned int apll_con0_l8; /* 0x1001100 */ + unsigned int apll_con0_l7; + unsigned int apll_con0_l6; + unsigned int apll_con0_l5; + unsigned int apll_con0_l4; + unsigned int apll_con0_l3; + unsigned int apll_con0_l2; + unsigned int apll_con0_l1; + unsigned int iem_control; + unsigned char res13[0xdc]; + unsigned int apll_con1_l8; /* 0x10011200 */ + unsigned int apll_con1_l7; + unsigned int apll_con1_l6; + unsigned int apll_con1_l5; + unsigned int apll_con1_l4; + unsigned int apll_con1_l3; + unsigned int apll_con1_l2; + unsigned int apll_con1_l1; + unsigned char res14[0xe0]; + unsigned int clkdiv_iem_l8; + unsigned int clkdiv_iem_l7; /* 0x10011304 */ + unsigned int clkdiv_iem_l6; + unsigned int clkdiv_iem_l5; + unsigned int clkdiv_iem_l4; + unsigned int clkdiv_iem_l3; + unsigned int clkdiv_iem_l2; + unsigned int clkdiv_iem_l1; + unsigned char res15[0xe0]; + unsigned int l2_status; + unsigned char res16[0x0c]; + unsigned int cpu_status; /* 0x10011410 */ + unsigned char res17[0x0c]; + unsigned int ptm_status; + unsigned char res18[0xbdc]; + unsigned int cmu_cpu_spare0; + unsigned int cmu_cpu_spare1; + unsigned int cmu_cpu_spare2; + unsigned int cmu_cpu_spare3; + unsigned int cmu_cpu_spare4; + unsigned char res19[0x1fdc]; + unsigned int cmu_cpu_version; + unsigned char res20[0x20c]; + unsigned int src_cperi0; /* 0x10014200 */ + unsigned int src_cperi1; + unsigned char res21[0xf8]; + unsigned int src_mask_cperi; + unsigned char res22[0x100]; + unsigned int mux_stat_cperi1; + unsigned char res23[0xfc]; + unsigned int div_cperi1; + unsigned char res24[0xfc]; + unsigned int div_stat_cperi1; + unsigned char res25[0xf8]; + unsigned int gate_bus_cperi0; /* 0x10014700 */ + unsigned int gate_bus_cperi1; + unsigned char res26[0xf8]; + unsigned int gate_sclk_cperi; + unsigned char res27[0xfc]; + unsigned int gate_ip_cperi; + unsigned char res28[0xfc]; + unsigned int clkout_cmu_cperi; + unsigned int clkout_cmu_cperi_div_stat; + unsigned char res29[0x5f8]; + unsigned int dcgidx_map0; /* 0x10015000 */ + unsigned int dcgidx_map1; + unsigned int dcgidx_map2; + unsigned char res30[0x14]; + unsigned int dcgperf_map0; + unsigned int dcgperf_map1; + unsigned char res31[0x18]; + unsigned int dvcidx_map; + unsigned char res32[0x1c]; + unsigned int freq_cpu; + unsigned int freq_dpm; + unsigned char res33[0x18]; + unsigned int dvsemclk_en; /* 0x10015080 */ + unsigned int maxperf; + unsigned char res34[0x2e78]; + unsigned int cmu_cperi_spare0; + unsigned int cmu_cperi_spare1; + unsigned int cmu_cperi_spare2; + unsigned int cmu_cperi_spare3; + unsigned int cmu_cperi_spare4; + unsigned int cmu_cperi_spare5; + unsigned int cmu_cperi_spare6; + unsigned int cmu_cperi_spare7; + unsigned int cmu_cperi_spare8; + unsigned char res35[0xcc]; + unsigned int cmu_cperi_version; /* 0x10017ff0 */ + unsigned char res36[0x50c]; + unsigned int div_g2d; + unsigned char res37[0xfc]; + unsigned int div_stat_g2d; + unsigned char res38[0xfc]; + unsigned int gate_bus_g2d; + unsigned char res39[0xfc]; + unsigned int gate_ip_g2d; + unsigned char res40[0x1fc]; + unsigned int clkout_cmu_g2d; + unsigned int clkout_cmu_g2d_div_stat; /* 0x10018a04 */ + unsigned char res41[0xf8]; + unsigned int cmu_g2d_spare0; + unsigned int cmu_g2d_spare1; + unsigned int cmu_g2d_spare2; + unsigned int cmu_g2d_spare3; + unsigned int cmu_g2d_spare4; + unsigned char res42[0x34dc]; + unsigned int cmu_g2d_version; + unsigned char res43[0x30c]; + unsigned int div_cmu_isp0; + unsigned int div_cmu_isp1; + unsigned int div_isp2; /* 0x1001c308 */ + unsigned char res44[0xf4]; + unsigned int div_stat_cmu_isp0; + unsigned int div_stat_cmu_isp1; + unsigned int div_stat_isp2; + unsigned char res45[0x2f4]; + unsigned int gate_bus_isp0; + unsigned int gate_bus_isp1; + unsigned int gate_bus_isp2; + unsigned int gate_bus_isp3; + unsigned char res46[0xf0]; + unsigned int gate_ip_isp0; + unsigned int gate_ip_isp1; + unsigned char res47[0xf8]; + unsigned int gate_sclk_isp; + unsigned char res48[0x0c]; + unsigned int mcuisp_pwr_ctrl; /* 0x1001c910 */ + unsigned char res49[0x0ec]; + unsigned int clkout_cmu_isp; + unsigned int clkout_cmu_isp_div_stat; + unsigned char res50[0xf8]; + unsigned int cmu_isp_spare0; + unsigned int cmu_isp_spare1; + unsigned int cmu_isp_spare2; + unsigned int cmu_isp_spare3; + unsigned char res51[0x34e0]; + unsigned int cmu_isp_version; + unsigned char res52[0x2c]; + unsigned int cpll_lock; /* 10020020 */ + unsigned char res53[0xc]; + unsigned int dpll_lock; + unsigned char res54[0xc]; + unsigned int epll_lock; + unsigned char res55[0xc]; + unsigned int rpll_lock; + unsigned char res56[0xc]; + unsigned int ipll_lock; + unsigned char res57[0xc]; + unsigned int spll_lock; + unsigned char res58[0xc]; + unsigned int vpll_lock; + unsigned char res59[0xc]; + unsigned int mpll_lock; + unsigned char res60[0x8c]; + unsigned int cpll_con0; /* 10020120 */ + unsigned int cpll_con1; + unsigned int dpll_con0; + unsigned int dpll_con1; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int epll_con2; + unsigned char res601[0x4]; + unsigned int rpll_con0; + unsigned int rpll_con1; + unsigned int rpll_con2; + unsigned char res602[0x4]; + unsigned int ipll_con0; + unsigned int ipll_con1; + unsigned char res61[0x8]; + unsigned int spll_con0; + unsigned int spll_con1; + unsigned char res62[0x8]; + unsigned int vpll_con0; + unsigned int vpll_con1; + unsigned char res63[0x8]; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res64[0x78]; + unsigned int src_top0; /* 0x10020200 */ + unsigned int src_top1; + unsigned int src_top2; + unsigned int src_top3; + unsigned int src_top4; + unsigned int src_top5; + unsigned int src_top6; + unsigned int src_top7; + unsigned char res65[0xc]; + unsigned int src_disp10; /* 0x1002022c */ + unsigned char res66[0x10]; + unsigned int src_mau; + unsigned int src_fsys; + unsigned char res67[0x8]; + unsigned int src_peric0; + unsigned int src_peric1; + unsigned char res68[0x18]; + unsigned int src_isp; + unsigned char res69[0x0c]; + unsigned int src_top10; + unsigned int src_top11; + unsigned int src_top12; + unsigned char res70[0x74]; + unsigned int src_mask_top0; + unsigned int src_mask_top1; + unsigned int src_mask_top2; + unsigned char res71[0x10]; + unsigned int src_mask_top7; + unsigned char res72[0xc]; + unsigned int src_mask_disp10; /* 0x1002032c */ + unsigned char res73[0x4]; + unsigned int src_mask_mau; + unsigned char res74[0x8]; + unsigned int src_mask_fsys; + unsigned char res75[0xc]; + unsigned int src_mask_peric0; + unsigned int src_mask_peric1; + unsigned char res76[0x18]; + unsigned int src_mask_isp; + unsigned char res77[0x8c]; + unsigned int mux_stat_top0; /* 0x10020400 */ + unsigned int mux_stat_top1; + unsigned int mux_stat_top2; + unsigned int mux_stat_top3; + unsigned int mux_stat_top4; + unsigned int mux_stat_top5; + unsigned int mux_stat_top6; + unsigned int mux_stat_top7; + unsigned char res78[0x60]; + unsigned int mux_stat_top10; + unsigned int mux_stat_top11; + unsigned int mux_stat_top12; + unsigned char res79[0x74]; + unsigned int div_top0; /* 0x10020500 */ + unsigned int div_top1; + unsigned int div_top2; + unsigned char res80[0x20]; + unsigned int div_disp10; + unsigned char res81[0x14]; + unsigned int div_mau; + unsigned int div_fsys0; + unsigned int div_fsys1; + unsigned int div_fsys2; + unsigned char res82[0x4]; + unsigned int div_peric0; + unsigned int div_peric1; + unsigned int div_peric2; + unsigned int div_peric3; + unsigned int div_peric4; /* 0x10020568 */ + unsigned char res83[0x14]; + unsigned int div_isp0; + unsigned int div_isp1; + unsigned char res84[0x8]; + unsigned int clkdiv2_ratio; + unsigned char res850[0xc]; + unsigned int clkdiv4_ratio; + unsigned char res85[0x5c]; + unsigned int div_stat_top0; + unsigned int div_stat_top1; + unsigned int div_stat_top2; + unsigned char res86[0x20]; + unsigned int div_stat_disp10; + unsigned char res87[0x14]; + unsigned int div_stat_mau; /* 0x10020644 */ + unsigned int div_stat_fsys0; + unsigned int div_stat_fsys1; + unsigned int div_stat_fsys2; + unsigned char res88[0x4]; + unsigned int div_stat_peric0; + unsigned int div_stat_peric1; + unsigned int div_stat_peric2; + unsigned int div_stat_peric3; + unsigned int div_stat_peric4; + unsigned char res89[0x14]; + unsigned int div_stat_isp0; + unsigned int div_stat_isp1; + unsigned char res90[0x8]; + unsigned int clkdiv2_stat0; + unsigned char res91[0xc]; + unsigned int clkdiv4_stat; + unsigned char res92[0x5c]; + unsigned int gate_bus_top; /* 0x10020700 */ + unsigned char res93[0xc]; + unsigned int gate_bus_gscl0; + unsigned char res94[0xc]; + unsigned int gate_bus_gscl1; + unsigned char res95[0x4]; + unsigned int gate_bus_disp1; + unsigned char res96[0x4]; + unsigned int gate_bus_wcore; + unsigned int gate_bus_mfc; + unsigned int gate_bus_g3d; + unsigned int gate_bus_gen; + unsigned int gate_bus_fsys0; + unsigned int gate_bus_fsys1; + unsigned int gate_bus_fsys2; + unsigned int gate_bus_mscl; + unsigned int gate_bus_peric; + unsigned int gate_bus_peric1; + unsigned char res97[0x8]; + unsigned int gate_bus_peris0; + unsigned int gate_bus_peris1; /* 0x10020764 */ + unsigned char res98[0x8]; + unsigned int gate_bus_noc; + unsigned char res99[0xac]; + unsigned int gate_top_sclk_gscl; + unsigned char res1000[0x4]; + unsigned int gate_top_sclk_disp1; + unsigned char res100[0x10]; + unsigned int gate_top_sclk_mau; + unsigned int gate_top_sclk_fsys; + unsigned char res101[0xc]; + unsigned int gate_top_sclk_peric; + unsigned char res102[0xc]; + unsigned int gate_top_sclk_cperi; + unsigned char res103[0xc]; + unsigned int gate_top_sclk_isp; + unsigned char res104[0x9c]; + unsigned int gate_ip_gscl0; + unsigned char res105[0xc]; + unsigned int gate_ip_gscl1; + unsigned char res106[0x4]; + unsigned int gate_ip_disp1; + unsigned int gate_ip_mfc; + unsigned int gate_ip_g3d; + unsigned int gate_ip_gen; /* 0x10020934 */ + unsigned char res107[0xc]; + unsigned int gate_ip_fsys; + unsigned char res108[0x8]; + unsigned int gate_ip_peric; + unsigned char res109[0xc]; + unsigned int gate_ip_peris; + unsigned char res110[0xc]; + unsigned int gate_ip_mscl; + unsigned char res111[0xc]; + unsigned int gate_ip_block; + unsigned char res112[0xc]; + unsigned int bypass; + unsigned char res113[0x6c]; + unsigned int clkout_cmu_top; + unsigned int clkout_cmu_top_div_stat; + unsigned char res114[0xf8]; + unsigned int clkout_top_spare0; + unsigned int clkout_top_spare1; + unsigned int clkout_top_spare2; + unsigned int clkout_top_spare3; + unsigned char res115[0x34e0]; + unsigned int clkout_top_version; + unsigned char res116[0xc01c]; + unsigned int bpll_lock; /* 0x10030010 */ + unsigned char res117[0xfc]; + unsigned int bpll_con0; + unsigned int bpll_con1; + unsigned char res118[0xe8]; + unsigned int src_cdrex; + unsigned char res119[0x1fc]; + unsigned int mux_stat_cdrex; + unsigned char res120[0xfc]; + unsigned int div_cdrex0; + unsigned int div_cdrex1; + unsigned char res121[0xf8]; + unsigned int div_stat_cdrex; + unsigned char res1211[0xfc]; + unsigned int gate_bus_cdrex; + unsigned int gate_bus_cdrex1; + unsigned char res122[0x1f8]; + unsigned int gate_ip_cdrex; + unsigned char res123[0x10]; + unsigned int dmc_freq_ctrl; /* 0x10030914 */ + unsigned char res124[0x4]; + unsigned int pause; + unsigned int ddrphy_lock_ctrl; + unsigned char res125[0xdc]; + unsigned int clkout_cmu_cdrex; + unsigned int clkout_cmu_cdrex_div_stat; + unsigned char res126[0x8]; + unsigned int lpddr3phy_ctrl; + unsigned int lpddr3phy_con0; + unsigned int lpddr3phy_con1; + unsigned int lpddr3phy_con2; + unsigned int lpddr3phy_con3; + unsigned int lpddr3phy_con4; + unsigned int lpddr3phy_con5; /* 0x10030a28 */ + unsigned int pll_div2_sel; + unsigned char res127[0xd0]; + unsigned int cmu_cdrex_spare0; + unsigned int cmu_cdrex_spare1; + unsigned int cmu_cdrex_spare2; + unsigned int cmu_cdrex_spare3; + unsigned int cmu_cdrex_spare4; + unsigned char res128[0x34dc]; + unsigned int cmu_cdrex_version; /* 0x10033ff0 */ + unsigned char res129[0x400c]; + unsigned int kpll_lock; + unsigned char res130[0xfc]; + unsigned int kpll_con0; + unsigned int kpll_con1; + unsigned char res131[0xf8]; + unsigned int src_kfc; + unsigned char res132[0x1fc]; + unsigned int mux_stat_kfc; /* 0x10038400 */ + unsigned char res133[0xfc]; + unsigned int div_kfc0; + unsigned char res134[0xfc]; + unsigned int div_stat_kfc0; + unsigned char res135[0xfc]; + unsigned int gate_bus_cpu_kfc; + unsigned char res136[0xfc]; + unsigned int gate_sclk_cpu_kfc; + unsigned char res137[0x1fc]; + unsigned int clkout_cmu_kfc; + unsigned int clkout_cmu_kfc_div_stat; /* 0x10038a04 */ + unsigned char res138[0x5f8]; + unsigned int armclk_stopctrl_kfc; + unsigned char res139[0x4]; + unsigned int armclk_ema_ctrl_kfc; + unsigned int armclk_ema_status_kfc; + unsigned char res140[0x10]; + unsigned int pwr_ctrl_kfc; + unsigned int pwr_ctrl2_kfc; + unsigned char res141[0xd8]; + unsigned int kpll_con0_l8; + unsigned int kpll_con0_l7; + unsigned int kpll_con0_l6; + unsigned int kpll_con0_l5; + unsigned int kpll_con0_l4; + unsigned int kpll_con0_l3; + unsigned int kpll_con0_l2; + unsigned int kpll_con0_l1; + unsigned int iem_control_kfc; /* 0x10039120 */ + unsigned char res142[0xdc]; + unsigned int kpll_con1_l8; + unsigned int kpll_con1_l7; + unsigned int kpll_con1_l6; + unsigned int kpll_con1_l5; + unsigned int kpll_con1_l4; + unsigned int kpll_con1_l3; + unsigned int kpll_con1_l2; + unsigned int kpll_con1_l1; + unsigned char res143[0xe0]; + unsigned int clkdiv_iem_l8_kfc; /* 0x10039300 */ + unsigned int clkdiv_iem_l7_kfc; + unsigned int clkdiv_iem_l6_kfc; + unsigned int clkdiv_iem_l5_kfc; + unsigned int clkdiv_iem_l4_kfc; + unsigned int clkdiv_iem_l3_kfc; + unsigned int clkdiv_iem_l2_kfc; + unsigned int clkdiv_iem_l1_kfc; + unsigned char res144[0xe0]; + unsigned int l2_status_kfc; + unsigned char res145[0xc]; + unsigned int cpu_status_kfc; /* 0x10039410 */ + unsigned char res146[0xc]; + unsigned int ptm_status_kfc; + unsigned char res147[0xbdc]; + unsigned int cmu_kfc_spare0; + unsigned int cmu_kfc_spare1; + unsigned int cmu_kfc_spare2; + unsigned int cmu_kfc_spare3; + unsigned int cmu_kfc_spare4; + unsigned char res148[0x1fdc]; + unsigned int cmu_kfc_version; /* 0x1003bff0 */ +}; + /* structure for epll configuration used in audio clock configuration */ struct set_epll_con_val { unsigned int freq_out; /* frequency out */ @@ -876,8 +1370,12 @@ struct set_epll_con_val { #define AUDIO_0_RATIO_MASK 0x0f #define AUDIO_1_RATIO_MASK 0x0f +#define AUDIO0_SEL_MASK 0xf #define AUDIO1_SEL_MASK 0xf + #define CLK_SRC_SCLK_EPLL 0x7 +#define CLK_SRC_MOUT_EPLL (1<<12) +#define AUDIO_CLKMUX_ASS (1<<0) /* CON0 bit-fields */ #define EPLL_CON0_MDIV_MASK 0x1ff diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index cb924fba8b..29674ad4da 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -25,9 +25,12 @@ #define EXYNOS4_SYSTIMER_BASE 0x10050000 #define EXYNOS4_WATCHDOG_BASE 0x10060000 #define EXYNOS4_TZPC_BASE 0x10110000 -#define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_DMC_CTRL_BASE 0x10400000 +#define EXYNOS4_MIU_BASE 0x10600000 +#define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ +#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 @@ -48,8 +51,11 @@ #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE /* EXYNOS4X12 */ #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 @@ -64,8 +70,16 @@ #define EXYNOS4X12_TZPC_BASE 0x10110000 #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 +#define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART2_0 0x11000000 +#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ +#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ +#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ +#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ +#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */ #define EXYNOS4X12_FIMD_BASE 0x11C00000 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 #define EXYNOS4X12_USBOTG_BASE 0x12480000 @@ -83,13 +97,17 @@ #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE -/* EXYNOS5 Common*/ +/* EXYNOS5 */ #define EXYNOS5_I2C_SPACING 0x10000 -#define EXYNOS5_GPIO_PART4_BASE 0x03860000 +#define EXYNOS5_AUDIOSS_BASE 0x03810000 +#define EXYNOS5_GPIO_PART8_BASE 0x03860000 #define EXYNOS5_PRO_ID 0x10000000 #define EXYNOS5_CLOCK_BASE 0x10010000 #define EXYNOS5_POWER_BASE 0x10040000 @@ -97,12 +115,18 @@ #define EXYNOS5_SYSREG_BASE 0x10050000 #define EXYNOS5_TZPC_BASE 0x10100000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5_ACE_SFR_BASE 0x10830000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY_BASE 0x10C00000 -#define EXYNOS5_GPIO_PART3_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART5_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART6_BASE 0x10D10060 +#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 +#define EXYNOS5_GPIO_PART2_BASE 0x114002E0 +#define EXYNOS5_GPIO_PART3_BASE 0x11400C00 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 +#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000 +#define EXYNOS5_USB3PHY_BASE 0x12100000 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 #define EXYNOS5_USBPHY_BASE 0x12130000 #define EXYNOS5_USBOTG_BASE 0x12140000 @@ -114,12 +138,53 @@ #define EXYNOS5_I2S_BASE 0x12D60000 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5_GPIO_PART4_BASE 0x13400000 #define EXYNOS5_FIMD_BASE 0x14400000 #define EXYNOS5_DP_BASE 0x145B0000 #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE + +/* EXYNOS5420 */ +#define EXYNOS5420_AUDIOSS_BASE 0x03810000 +#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 +#define EXYNOS5420_PRO_ID 0x10000000 +#define EXYNOS5420_CLOCK_BASE 0x10010000 +#define EXYNOS5420_POWER_BASE 0x10040000 +#define EXYNOS5420_SWRESET 0x10040400 +#define EXYNOS5420_SYSREG_BASE 0x10050000 +#define EXYNOS5420_TZPC_BASE 0x100E0000 +#define EXYNOS5420_WATCHDOG_BASE 0x101D0000 +#define EXYNOS5420_ACE_SFR_BASE 0x10830000 +#define EXYNOS5420_DMC_PHY_BASE 0x10C00000 +#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000 +#define EXYNOS5420_DMC_TZASC_BASE 0x10D40000 +#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000 +#define EXYNOS5420_MMC_BASE 0x12200000 +#define EXYNOS5420_SROMC_BASE 0x12250000 +#define EXYNOS5420_UART_BASE 0x12C00000 +#define EXYNOS5420_I2C_BASE 0x12C60000 +#define EXYNOS5420_I2C_8910_BASE 0x12E00000 +#define EXYNOS5420_SPI_BASE 0x12D20000 +#define EXYNOS5420_I2S_BASE 0x12D60000 +#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 +#define EXYNOS5420_SPI_ISP_BASE 0x131A0000 +#define EXYNOS5420_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 +#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART5_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART1_BASE 0x14010000 +#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 +#define EXYNOS5420_DP_BASE 0x145B0000 + +#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE #ifndef __ASSEMBLY__ #include @@ -134,9 +199,11 @@ static inline int s5p_get_cpu_rev(void) static inline void s5p_set_cpu_id(void) { - unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12; + unsigned int pro_id = readl(EXYNOS4_PRO_ID); + unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12; + unsigned int cpu_rev = pro_id & 0x000000FF; - switch (pro_id) { + switch (cpu_id) { case 0x200: /* Exynos4210 EVT0 */ s5p_cpu_id = 0x4210; @@ -145,15 +212,28 @@ static inline void s5p_set_cpu_id(void) case 0x210: /* Exynos4210 EVT1 */ s5p_cpu_id = 0x4210; + s5p_cpu_rev = cpu_rev; break; case 0x412: /* Exynos4412 */ s5p_cpu_id = 0x4412; + s5p_cpu_rev = cpu_rev; break; case 0x520: /* Exynos5250 */ s5p_cpu_id = 0x5250; break; + case 0x420: + /* Exynos5420 */ + s5p_cpu_id = 0x5420; + break; + case 0x422: + /* + * Exynos5800 is a variant of Exynos5420 + * and has product id 0x5422 + */ + s5p_cpu_id = 0x5800; + break; } } @@ -181,6 +261,8 @@ static inline int __attribute__((no_instrument_function)) \ IS_EXYNOS_TYPE(exynos4210, 0x4210) IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) +IS_EXYNOS_TYPE(exynos5420, 0x5420) +IS_EXYNOS_TYPE(exynos5800, 0x5800) #define SAMSUNG_BASE(device, base) \ static inline unsigned int __attribute__((no_instrument_function)) \ @@ -191,6 +273,8 @@ static inline unsigned int __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ + if (proid_is_exynos5420() || proid_is_exynos5800()) \ + return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ return 0; \ @@ -217,7 +301,9 @@ SAMSUNG_BASE(swreset, SWRESET) SAMSUNG_BASE(timer, PWMTIMER_BASE) SAMSUNG_BASE(uart, UART_BASE) SAMSUNG_BASE(usb_phy, USBPHY_BASE) +SAMSUNG_BASE(usb3_phy, USB3PHY_BASE) SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) +SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE) SAMSUNG_BASE(usb_otg, USBOTG_BASE) SAMSUNG_BASE(watchdog, WATCHDOG_BASE) SAMSUNG_BASE(power, POWER_BASE) @@ -226,6 +312,8 @@ SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) SAMSUNG_BASE(tzpc, TZPC_BASE) SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE) SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE) +SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE) +SAMSUNG_BASE(audio_ass, AUDIOSS_BASE) #endif #endif /* _EXYNOS4_CPU_H */ diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index f65c676cc5..4990a1af39 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -205,6 +205,127 @@ struct exynos5_dmc { unsigned int pmcnt3_ppc_a; }; +struct exynos5420_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int cgcontrol; + unsigned char res500[0x4]; + unsigned int directcmd; + unsigned int prechconfig0; + unsigned int phycontrol0; + unsigned int prechconfig1; + unsigned char res1[0x8]; + unsigned int pwrdnconfig; + unsigned int timingpzq; + unsigned int timingref; + unsigned int timingrow0; + unsigned int timingdata0; + unsigned int timingpower0; + unsigned int phystatus; + unsigned int etctiming; + unsigned int chipstatus; + unsigned char res3[0x8]; + unsigned int mrstatus; + unsigned char res4[0x8]; + unsigned int qoscontrol0; + unsigned char resr5[0x4]; + unsigned int qoscontrol1; + unsigned char res6[0x4]; + unsigned int qoscontrol2; + unsigned char res7[0x4]; + unsigned int qoscontrol3; + unsigned char res8[0x4]; + unsigned int qoscontrol4; + unsigned char res9[0x4]; + unsigned int qoscontrol5; + unsigned char res10[0x4]; + unsigned int qoscontrol6; + unsigned char res11[0x4]; + unsigned int qoscontrol7; + unsigned char res12[0x4]; + unsigned int qoscontrol8; + unsigned char res13[0x4]; + unsigned int qoscontrol9; + unsigned char res14[0x4]; + unsigned int qoscontrol10; + unsigned char res15[0x4]; + unsigned int qoscontrol11; + unsigned char res16[0x4]; + unsigned int qoscontrol12; + unsigned char res17[0x4]; + unsigned int qoscontrol13; + unsigned char res18[0x4]; + unsigned int qoscontrol14; + unsigned char res19[0x4]; + unsigned int qoscontrol15; + unsigned char res20[0x4]; + unsigned int timing_set_sw; + unsigned int timingrow1; + unsigned int timingdata1; + unsigned int timingpower1; + unsigned char res300[0x4]; + unsigned int wrtra_config; + unsigned int rdlvl_config; + unsigned char res21[0x4]; + unsigned int brbrsvcontrol; + unsigned int brbrsvconfig; + unsigned int brbqosconfig; + unsigned char res301[0x14]; + unsigned int wrlvl_config0; + unsigned int wrlvl_config1; + unsigned int wrlvl_status; + unsigned char res23[0x4]; + unsigned int ppcclockon; + unsigned int perevconfig0; + unsigned int perevconfig1; + unsigned int perevconfig2; + unsigned int perevconfig3; + unsigned char res24[0xc]; + unsigned int control_io_rdata; + unsigned char res240[0xc]; + unsigned int cacal_config0; + unsigned int cacal_config1; + unsigned int cacal_status; + unsigned char res302[0xa4]; + unsigned int bp_control0; + unsigned int bp_config0_r; + unsigned int bp_config0_w; + unsigned char res303[0x4]; + unsigned int bp_control1; + unsigned int bp_config1_r; + unsigned int bp_config1_w; + unsigned char res304[0x4]; + unsigned int bp_control2; + unsigned int bp_config2_r; + unsigned int bp_config2_w; + unsigned char res305[0x4]; + unsigned int bp_control3; + unsigned int bp_config3_r; + unsigned int bp_config3_w; + unsigned char res306[0xddb4]; + unsigned int pmnc_ppc; + unsigned char res25[0xc]; + unsigned int cntens_ppc; + unsigned char res26[0xc]; + unsigned int cntenc_ppc; + unsigned char res27[0xc]; + unsigned int intens_ppc; + unsigned char res28[0xc]; + unsigned int intenc_ppc; + unsigned char res29[0xc]; + unsigned int flag_ppc; + unsigned char res30[0xac]; + unsigned int ccnt_ppc; + unsigned char res31[0xc]; + unsigned int pmcnt0_ppc; + unsigned char res32[0xc]; + unsigned int pmcnt1_ppc; + unsigned char res33[0xc]; + unsigned int pmcnt2_ppc; + unsigned char res34[0xc]; + unsigned int pmcnt3_ppc; +}; + struct exynos5_phy_control { unsigned int phy_con0; unsigned int phy_con1; @@ -252,6 +373,61 @@ struct exynos5_phy_control { unsigned int phy_con42; }; +struct exynos5420_phy_control { + unsigned int phy_con0; + unsigned int phy_con1; + unsigned int phy_con2; + unsigned int phy_con3; + unsigned int phy_con4; + unsigned int phy_con5; + unsigned int phy_con6; + unsigned char res2[0x4]; + unsigned int phy_con8; + unsigned char res5[0x4]; + unsigned int phy_con10; + unsigned int phy_con11; + unsigned int phy_con12; + unsigned int phy_con13; + unsigned int phy_con14; + unsigned int phy_con15; + unsigned int phy_con16; + unsigned char res4[0x4]; + unsigned int phy_con17; + unsigned int phy_con18; + unsigned int phy_con19; + unsigned int phy_con20; + unsigned int phy_con21; + unsigned int phy_con22; + unsigned int phy_con23; + unsigned int phy_con24; + unsigned int phy_con25; + unsigned int phy_con26; + unsigned int phy_con27; + unsigned int phy_con28; + unsigned int phy_con29; + unsigned int phy_con30; + unsigned int phy_con31; + unsigned int phy_con32; + unsigned int phy_con33; + unsigned int phy_con34; + unsigned char res6[0x8]; + unsigned int phy_con37; + unsigned char res7[0x4]; + unsigned int phy_con39; + unsigned int phy_con40; + unsigned int phy_con41; + unsigned int phy_con42; +}; + +struct exynos5420_tzasc { + unsigned char res1[0xf00]; + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned char res2[0x8]; + unsigned int memconfig0; + unsigned int memconfig1; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3, @@ -274,6 +450,7 @@ enum mem_manuf { #define CONCONTROL_RD_FETCH_SHIFT 12 #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) #define CONCONTROL_AREF_EN_SHIFT 5 +#define CONCONTROL_UPDATE_MODE (1 << 3) /* PRECHCONFIG register field */ #define PRECHCONFIG_TP_CNT_SHIFT 24 @@ -286,10 +463,14 @@ enum mem_manuf { #define PHY_CON0_T_WRRDCMD_SHIFT 17 #define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) #define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 +#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 /* PHY_CON1 register fields */ #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 +/* PHY_CON4 rgister fields */ +#define PHY_CON10_CTRL_OFFSETR3 (1 << 24) + /* PHY_CON12 register fields */ #define PHY_CON12_CTRL_START_POINT_SHIFT 24 #define PHY_CON12_CTRL_INC_SHIFT 16 diff --git a/arch/arm/include/asm/arch-exynos/dp.h b/arch/arm/include/asm/arch-exynos/dp.h index 19f313c8c9..0ec58e94ce 100644 --- a/arch/arm/include/asm/arch-exynos/dp.h +++ b/arch/arm/include/asm/arch-exynos/dp.h @@ -3,7 +3,7 @@ * * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_ARM_ARCH_DP_H_ diff --git a/arch/arm/include/asm/arch-exynos/dp_info.h b/arch/arm/include/asm/arch-exynos/dp_info.h index 8c523099c9..3f6750a6b2 100644 --- a/arch/arm/include/asm/arch-exynos/dp_info.h +++ b/arch/arm/include/asm/arch-exynos/dp_info.h @@ -3,7 +3,7 @@ * * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _DP_INFO_H diff --git a/arch/arm/include/asm/arch-exynos/dsim.h b/arch/arm/include/asm/arch-exynos/dsim.h index 889e7d009a..86ff4da4d8 100644 --- a/arch/arm/include/asm/arch-exynos/dsim.h +++ b/arch/arm/include/asm/arch-exynos/dsim.h @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_ARM_ARCH_DSIM_H_ diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index b9eca765cd..a7ca12c477 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -6,14 +6,27 @@ */ #define DWMCI_CLKSEL 0x09C -#define DWMCI_SHIFT_0 0x0 -#define DWMCI_SHIFT_1 0x1 -#define DWMCI_SHIFT_2 0x2 -#define DWMCI_SHIFT_3 0x3 #define DWMCI_SET_SAMPLE_CLK(x) (x) #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) +#define EMMCP_MPSBEGIN0 0x1200 +#define EMMCP_SEND0 0x1204 +#define EMMCP_CTRL0 0x120C + +#define MPSCTRL_SECURE_READ_BIT (0x1<<7) +#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6) +#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5) +#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4) +#define MPSCTRL_USE_FUSE_KEY (0x1<<3) +#define MPSCTRL_ECB_MODE (0x1<<2) +#define MPSCTRL_ENCRYPTION (0x1<<1) +#define MPSCTRL_VALID (0x1<<0) + +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h index d79f25c0c3..3800fa9044 100644 --- a/arch/arm/include/asm/arch-exynos/ehci.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -12,6 +12,13 @@ #define CLK_24MHZ 5 +#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0) +#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6) +#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9) +#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12) +#define RSTCON_HOSTPHY_SWRST (0xf << 3) +#define RSTCON_SWRST (0x1 << 0) + #define HOST_CTRL0_PHYSWRSTALL (1 << 31) #define HOST_CTRL0_COMMONON_N (1 << 9) #define HOST_CTRL0_SIDDQ (1 << 6) @@ -29,6 +36,20 @@ #define EHCICTRL_ENAINCR8 (1 << 27) #define EHCICTRL_ENAINCR16 (1 << 26) +#define HSIC_CTRL_REFCLKSEL (0x2) +#define HSIC_CTRL_REFCLKSEL_MASK (0x3) +#define HSIC_CTRL_REFCLKSEL_SHIFT (23) + +#define HSIC_CTRL_REFCLKDIV_12 (0x24) +#define HSIC_CTRL_REFCLKDIV_MASK (0x7f) +#define HSIC_CTRL_REFCLKDIV_SHIFT (16) + +#define HSIC_CTRL_SIDDQ (0x1 << 6) +#define HSIC_CTRL_FORCESLEEP (0x1 << 5) +#define HSIC_CTRL_FORCESUSPEND (0x1 << 4) +#define HSIC_CTRL_UTMISWRST (0x1 << 2) +#define HSIC_CTRL_PHYSWRST (0x1 << 0) + /* Register map for PHY control */ struct exynos_usb_phy { unsigned int usbphyctrl0; @@ -47,6 +68,12 @@ struct exynos_usb_phy { unsigned int usbotgtune; }; +struct exynos4412_usb_phy { + unsigned int usbphyctrl; + unsigned int usbphyclk; + unsigned int usbphyrstcon; +}; + /* Switch on the VBUS power. */ int board_usb_vbus_init(void); diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index e955811262..9699954a7d 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -19,303 +19,1530 @@ struct s5p_gpio_bank { unsigned char res1[8]; }; -struct exynos4_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank e2; - struct s5p_gpio_bank e3; - struct s5p_gpio_bank e4; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; -}; +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 -struct exynos4_gpio_part2 { - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[80]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum exynos4_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS4_GPIO_A00, /* 0 */ + EXYNOS4_GPIO_A01, + EXYNOS4_GPIO_A02, + EXYNOS4_GPIO_A03, + EXYNOS4_GPIO_A04, + EXYNOS4_GPIO_A05, + EXYNOS4_GPIO_A06, + EXYNOS4_GPIO_A07, + EXYNOS4_GPIO_A10, /* 8 */ + EXYNOS4_GPIO_A11, + EXYNOS4_GPIO_A12, + EXYNOS4_GPIO_A13, + EXYNOS4_GPIO_A14, + EXYNOS4_GPIO_A15, + EXYNOS4_GPIO_A16, + EXYNOS4_GPIO_A17, + EXYNOS4_GPIO_B0, /* 16 0x10 */ + EXYNOS4_GPIO_B1, + EXYNOS4_GPIO_B2, + EXYNOS4_GPIO_B3, + EXYNOS4_GPIO_B4, + EXYNOS4_GPIO_B5, + EXYNOS4_GPIO_B6, + EXYNOS4_GPIO_B7, + EXYNOS4_GPIO_C00, /* 24 0x18 */ + EXYNOS4_GPIO_C01, + EXYNOS4_GPIO_C02, + EXYNOS4_GPIO_C03, + EXYNOS4_GPIO_C04, + EXYNOS4_GPIO_C05, + EXYNOS4_GPIO_C06, + EXYNOS4_GPIO_C07, + EXYNOS4_GPIO_C10, /* 32 0x20*/ + EXYNOS4_GPIO_C11, + EXYNOS4_GPIO_C12, + EXYNOS4_GPIO_C13, + EXYNOS4_GPIO_C14, + EXYNOS4_GPIO_C15, + EXYNOS4_GPIO_C16, + EXYNOS4_GPIO_C17, + EXYNOS4_GPIO_D00, /* 40 0x28 */ + EXYNOS4_GPIO_D01, + EXYNOS4_GPIO_D02, + EXYNOS4_GPIO_D03, + EXYNOS4_GPIO_D04, + EXYNOS4_GPIO_D05, + EXYNOS4_GPIO_D06, + EXYNOS4_GPIO_D07, + EXYNOS4_GPIO_D10, /* 48 0x30 */ + EXYNOS4_GPIO_D11, + EXYNOS4_GPIO_D12, + EXYNOS4_GPIO_D13, + EXYNOS4_GPIO_D14, + EXYNOS4_GPIO_D15, + EXYNOS4_GPIO_D16, + EXYNOS4_GPIO_D17, + EXYNOS4_GPIO_E00, /* 56 0x38 */ + EXYNOS4_GPIO_E01, + EXYNOS4_GPIO_E02, + EXYNOS4_GPIO_E03, + EXYNOS4_GPIO_E04, + EXYNOS4_GPIO_E05, + EXYNOS4_GPIO_E06, + EXYNOS4_GPIO_E07, + EXYNOS4_GPIO_E10, /* 64 0x40 */ + EXYNOS4_GPIO_E11, + EXYNOS4_GPIO_E12, + EXYNOS4_GPIO_E13, + EXYNOS4_GPIO_E14, + EXYNOS4_GPIO_E15, + EXYNOS4_GPIO_E16, + EXYNOS4_GPIO_E17, + EXYNOS4_GPIO_E20, /* 72 0x48 */ + EXYNOS4_GPIO_E21, + EXYNOS4_GPIO_E22, + EXYNOS4_GPIO_E23, + EXYNOS4_GPIO_E24, + EXYNOS4_GPIO_E25, + EXYNOS4_GPIO_E26, + EXYNOS4_GPIO_E27, + EXYNOS4_GPIO_E30, /* 80 0x50 */ + EXYNOS4_GPIO_E31, + EXYNOS4_GPIO_E32, + EXYNOS4_GPIO_E33, + EXYNOS4_GPIO_E34, + EXYNOS4_GPIO_E35, + EXYNOS4_GPIO_E36, + EXYNOS4_GPIO_E37, + EXYNOS4_GPIO_E40, /* 88 0x58 */ + EXYNOS4_GPIO_E41, + EXYNOS4_GPIO_E42, + EXYNOS4_GPIO_E43, + EXYNOS4_GPIO_E44, + EXYNOS4_GPIO_E45, + EXYNOS4_GPIO_E46, + EXYNOS4_GPIO_E47, + EXYNOS4_GPIO_F00, /* 96 0x60 */ + EXYNOS4_GPIO_F01, + EXYNOS4_GPIO_F02, + EXYNOS4_GPIO_F03, + EXYNOS4_GPIO_F04, + EXYNOS4_GPIO_F05, + EXYNOS4_GPIO_F06, + EXYNOS4_GPIO_F07, + EXYNOS4_GPIO_F10, /* 104 0x68 */ + EXYNOS4_GPIO_F11, + EXYNOS4_GPIO_F12, + EXYNOS4_GPIO_F13, + EXYNOS4_GPIO_F14, + EXYNOS4_GPIO_F15, + EXYNOS4_GPIO_F16, + EXYNOS4_GPIO_F17, + EXYNOS4_GPIO_F20, /* 112 0x70 */ + EXYNOS4_GPIO_F21, + EXYNOS4_GPIO_F22, + EXYNOS4_GPIO_F23, + EXYNOS4_GPIO_F24, + EXYNOS4_GPIO_F25, + EXYNOS4_GPIO_F26, + EXYNOS4_GPIO_F27, + EXYNOS4_GPIO_F30, /* 120 0x78 */ + EXYNOS4_GPIO_F31, + EXYNOS4_GPIO_F32, + EXYNOS4_GPIO_F33, + EXYNOS4_GPIO_F34, + EXYNOS4_GPIO_F35, + EXYNOS4_GPIO_F36, + EXYNOS4_GPIO_F37, -struct exynos4_gpio_part3 { - struct s5p_gpio_bank z; -}; + /* GPIO_PART2_STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_1, /* 128 0x80 */ + EXYNOS4_GPIO_J00 = EXYNOS4_GPIO_MAX_PORT_PART_1, + EXYNOS4_GPIO_J01, + EXYNOS4_GPIO_J02, + EXYNOS4_GPIO_J03, + EXYNOS4_GPIO_J04, + EXYNOS4_GPIO_J05, + EXYNOS4_GPIO_J06, + EXYNOS4_GPIO_J07, + EXYNOS4_GPIO_J10, /* 136 0x88 */ + EXYNOS4_GPIO_J11, + EXYNOS4_GPIO_J12, + EXYNOS4_GPIO_J13, + EXYNOS4_GPIO_J14, + EXYNOS4_GPIO_J15, + EXYNOS4_GPIO_J16, + EXYNOS4_GPIO_J17, + EXYNOS4_GPIO_K00, /* 144 0x90 */ + EXYNOS4_GPIO_K01, + EXYNOS4_GPIO_K02, + EXYNOS4_GPIO_K03, + EXYNOS4_GPIO_K04, + EXYNOS4_GPIO_K05, + EXYNOS4_GPIO_K06, + EXYNOS4_GPIO_K07, + EXYNOS4_GPIO_K10, /* 152 0x98 */ + EXYNOS4_GPIO_K11, + EXYNOS4_GPIO_K12, + EXYNOS4_GPIO_K13, + EXYNOS4_GPIO_K14, + EXYNOS4_GPIO_K15, + EXYNOS4_GPIO_K16, + EXYNOS4_GPIO_K17, + EXYNOS4_GPIO_K20, /* 160 0xA0 */ + EXYNOS4_GPIO_K21, + EXYNOS4_GPIO_K22, + EXYNOS4_GPIO_K23, + EXYNOS4_GPIO_K24, + EXYNOS4_GPIO_K25, + EXYNOS4_GPIO_K26, + EXYNOS4_GPIO_K27, + EXYNOS4_GPIO_K30, /* 168 0xA8 */ + EXYNOS4_GPIO_K31, + EXYNOS4_GPIO_K32, + EXYNOS4_GPIO_K33, + EXYNOS4_GPIO_K34, + EXYNOS4_GPIO_K35, + EXYNOS4_GPIO_K36, + EXYNOS4_GPIO_K37, + EXYNOS4_GPIO_L00, /* 176 0xB0 */ + EXYNOS4_GPIO_L01, + EXYNOS4_GPIO_L02, + EXYNOS4_GPIO_L03, + EXYNOS4_GPIO_L04, + EXYNOS4_GPIO_L05, + EXYNOS4_GPIO_L06, + EXYNOS4_GPIO_L07, + EXYNOS4_GPIO_L10, /* 184 0xB8 */ + EXYNOS4_GPIO_L11, + EXYNOS4_GPIO_L12, + EXYNOS4_GPIO_L13, + EXYNOS4_GPIO_L14, + EXYNOS4_GPIO_L15, + EXYNOS4_GPIO_L16, + EXYNOS4_GPIO_L17, + EXYNOS4_GPIO_L20, /* 192 0xC0 */ + EXYNOS4_GPIO_L21, + EXYNOS4_GPIO_L22, + EXYNOS4_GPIO_L23, + EXYNOS4_GPIO_L24, + EXYNOS4_GPIO_L25, + EXYNOS4_GPIO_L26, + EXYNOS4_GPIO_L27, + EXYNOS4_GPIO_Y00, /* 200 0xC8 */ + EXYNOS4_GPIO_Y01, + EXYNOS4_GPIO_Y02, + EXYNOS4_GPIO_Y03, + EXYNOS4_GPIO_Y04, + EXYNOS4_GPIO_Y05, + EXYNOS4_GPIO_Y06, + EXYNOS4_GPIO_Y07, + EXYNOS4_GPIO_Y10, /* 208 0xD0 */ + EXYNOS4_GPIO_Y11, + EXYNOS4_GPIO_Y12, + EXYNOS4_GPIO_Y13, + EXYNOS4_GPIO_Y14, + EXYNOS4_GPIO_Y15, + EXYNOS4_GPIO_Y16, + EXYNOS4_GPIO_Y17, + EXYNOS4_GPIO_Y20, /* 216 0xD8 */ + EXYNOS4_GPIO_Y21, + EXYNOS4_GPIO_Y22, + EXYNOS4_GPIO_Y23, + EXYNOS4_GPIO_Y24, + EXYNOS4_GPIO_Y25, + EXYNOS4_GPIO_Y26, + EXYNOS4_GPIO_Y27, + EXYNOS4_GPIO_Y30, /* 224 0xE0 */ + EXYNOS4_GPIO_Y31, + EXYNOS4_GPIO_Y32, + EXYNOS4_GPIO_Y33, + EXYNOS4_GPIO_Y34, + EXYNOS4_GPIO_Y35, + EXYNOS4_GPIO_Y36, + EXYNOS4_GPIO_Y37, + EXYNOS4_GPIO_Y40, /* 232 0xE8 */ + EXYNOS4_GPIO_Y41, + EXYNOS4_GPIO_Y42, + EXYNOS4_GPIO_Y43, + EXYNOS4_GPIO_Y44, + EXYNOS4_GPIO_Y45, + EXYNOS4_GPIO_Y46, + EXYNOS4_GPIO_Y47, + EXYNOS4_GPIO_Y50, /* 240 0xF0 */ + EXYNOS4_GPIO_Y51, + EXYNOS4_GPIO_Y52, + EXYNOS4_GPIO_Y53, + EXYNOS4_GPIO_Y54, + EXYNOS4_GPIO_Y55, + EXYNOS4_GPIO_Y56, + EXYNOS4_GPIO_Y57, + EXYNOS4_GPIO_Y60, /* 248 0xF8 */ + EXYNOS4_GPIO_Y61, + EXYNOS4_GPIO_Y62, + EXYNOS4_GPIO_Y63, + EXYNOS4_GPIO_Y64, + EXYNOS4_GPIO_Y65, + EXYNOS4_GPIO_Y66, + EXYNOS4_GPIO_Y67, -struct exynos4x12_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank res1[0x5]; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank res2[0x2]; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; -}; + /* GPIO_PART2_1 STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */ + EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0, + EXYNOS4_GPIO_X01, + EXYNOS4_GPIO_X02, + EXYNOS4_GPIO_X03, + EXYNOS4_GPIO_X04, + EXYNOS4_GPIO_X05, + EXYNOS4_GPIO_X06, + EXYNOS4_GPIO_X07, + EXYNOS4_GPIO_X10, /* 264 0x108 */ + EXYNOS4_GPIO_X11, + EXYNOS4_GPIO_X12, + EXYNOS4_GPIO_X13, + EXYNOS4_GPIO_X14, + EXYNOS4_GPIO_X15, + EXYNOS4_GPIO_X16, + EXYNOS4_GPIO_X17, + EXYNOS4_GPIO_X20, /* 272 0x110 */ + EXYNOS4_GPIO_X21, + EXYNOS4_GPIO_X22, + EXYNOS4_GPIO_X23, + EXYNOS4_GPIO_X24, + EXYNOS4_GPIO_X25, + EXYNOS4_GPIO_X26, + EXYNOS4_GPIO_X27, + EXYNOS4_GPIO_X30, /* 280 0x118 */ + EXYNOS4_GPIO_X31, + EXYNOS4_GPIO_X32, + EXYNOS4_GPIO_X33, + EXYNOS4_GPIO_X34, + EXYNOS4_GPIO_X35, + EXYNOS4_GPIO_X36, + EXYNOS4_GPIO_X37, -struct exynos4x12_gpio_part2 { - struct s5p_gpio_bank res1[0x2]; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res2[0x3]; - struct s5p_gpio_bank m0; - struct s5p_gpio_bank m1; - struct s5p_gpio_bank m2; - struct s5p_gpio_bank m3; - struct s5p_gpio_bank m4; - struct s5p_gpio_bank res3[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; + /* GPIO_PART3_STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */ + EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1, + EXYNOS4_GPIO_Z1, + EXYNOS4_GPIO_Z2, + EXYNOS4_GPIO_Z3, + EXYNOS4_GPIO_Z4, + EXYNOS4_GPIO_Z5, + EXYNOS4_GPIO_Z6, + EXYNOS4_GPIO_Z7, + + EXYNOS4_GPIO_MAX_PORT }; -struct exynos4x12_gpio_part3 { - struct s5p_gpio_bank z; +enum exynos4X12_gpio_pin { + /* EXYNOS4X12_GPIO_PART1_0 starts here */ + EXYNOS4X12_GPIO_A00, /* 0 */ + EXYNOS4X12_GPIO_A01, + EXYNOS4X12_GPIO_A02, + EXYNOS4X12_GPIO_A03, + EXYNOS4X12_GPIO_A04, + EXYNOS4X12_GPIO_A05, + EXYNOS4X12_GPIO_A06, + EXYNOS4X12_GPIO_A07, + EXYNOS4X12_GPIO_A10, /* 8 */ + EXYNOS4X12_GPIO_A11, + EXYNOS4X12_GPIO_A12, + EXYNOS4X12_GPIO_A13, + EXYNOS4X12_GPIO_A14, + EXYNOS4X12_GPIO_A15, + EXYNOS4X12_GPIO_A16, + EXYNOS4X12_GPIO_A17, + EXYNOS4X12_GPIO_B0, /* 16 0x10 */ + EXYNOS4X12_GPIO_B1, + EXYNOS4X12_GPIO_B2, + EXYNOS4X12_GPIO_B3, + EXYNOS4X12_GPIO_B4, + EXYNOS4X12_GPIO_B5, + EXYNOS4X12_GPIO_B6, + EXYNOS4X12_GPIO_B7, + EXYNOS4X12_GPIO_C00, /* 24 0x18 */ + EXYNOS4X12_GPIO_C01, + EXYNOS4X12_GPIO_C02, + EXYNOS4X12_GPIO_C03, + EXYNOS4X12_GPIO_C04, + EXYNOS4X12_GPIO_C05, + EXYNOS4X12_GPIO_C06, + EXYNOS4X12_GPIO_C07, + EXYNOS4X12_GPIO_C10, /* 32 0x20 */ + EXYNOS4X12_GPIO_C11, + EXYNOS4X12_GPIO_C12, + EXYNOS4X12_GPIO_C13, + EXYNOS4X12_GPIO_C14, + EXYNOS4X12_GPIO_C15, + EXYNOS4X12_GPIO_C16, + EXYNOS4X12_GPIO_C17, + EXYNOS4X12_GPIO_D00, /* 40 0x28 */ + EXYNOS4X12_GPIO_D01, + EXYNOS4X12_GPIO_D02, + EXYNOS4X12_GPIO_D03, + EXYNOS4X12_GPIO_D04, + EXYNOS4X12_GPIO_D05, + EXYNOS4X12_GPIO_D06, + EXYNOS4X12_GPIO_D07, + EXYNOS4X12_GPIO_D10, /* 48 0x30 */ + EXYNOS4X12_GPIO_D11, + EXYNOS4X12_GPIO_D12, + EXYNOS4X12_GPIO_D13, + EXYNOS4X12_GPIO_D14, + EXYNOS4X12_GPIO_D15, + EXYNOS4X12_GPIO_D16, + EXYNOS4X12_GPIO_D17, + EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */ + /* EXYNOS4X12_GPIO_PART1_1 starts here */ + EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, + EXYNOS4X12_GPIO_F01, + EXYNOS4X12_GPIO_F02, + EXYNOS4X12_GPIO_F03, + EXYNOS4X12_GPIO_F04, + EXYNOS4X12_GPIO_F05, + EXYNOS4X12_GPIO_F06, + EXYNOS4X12_GPIO_F07, + EXYNOS4X12_GPIO_F10, /* 64 0x40 */ + EXYNOS4X12_GPIO_F11, + EXYNOS4X12_GPIO_F12, + EXYNOS4X12_GPIO_F13, + EXYNOS4X12_GPIO_F14, + EXYNOS4X12_GPIO_F15, + EXYNOS4X12_GPIO_F16, + EXYNOS4X12_GPIO_F17, + EXYNOS4X12_GPIO_F20, /* 72 0x48 */ + EXYNOS4X12_GPIO_F21, + EXYNOS4X12_GPIO_F22, + EXYNOS4X12_GPIO_F23, + EXYNOS4X12_GPIO_F24, + EXYNOS4X12_GPIO_F25, + EXYNOS4X12_GPIO_F26, + EXYNOS4X12_GPIO_F27, + EXYNOS4X12_GPIO_F30, /* 80 0x50 */ + EXYNOS4X12_GPIO_F31, + EXYNOS4X12_GPIO_F32, + EXYNOS4X12_GPIO_F33, + EXYNOS4X12_GPIO_F34, + EXYNOS4X12_GPIO_F35, + EXYNOS4X12_GPIO_F36, + EXYNOS4X12_GPIO_F37, + EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */ + /* EXYNOS4X12_GPIO_PART1_2 starts here */ + EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, + EXYNOS4X12_GPIO_J01, + EXYNOS4X12_GPIO_J02, + EXYNOS4X12_GPIO_J03, + EXYNOS4X12_GPIO_J04, + EXYNOS4X12_GPIO_J05, + EXYNOS4X12_GPIO_J06, + EXYNOS4X12_GPIO_J07, + EXYNOS4X12_GPIO_J10, /* 96 0x60 */ + EXYNOS4X12_GPIO_J11, + EXYNOS4X12_GPIO_J12, + EXYNOS4X12_GPIO_J13, + EXYNOS4X12_GPIO_J14, + EXYNOS4X12_GPIO_J15, + EXYNOS4X12_GPIO_J16, + EXYNOS4X12_GPIO_J17, + + /** + * EXYNOS4X12_GPIO_PART2_0 is not used + * EXYNOS4X12_GPIO_PART2_1 starts here + */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */ + EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, + EXYNOS4X12_GPIO_K01, + EXYNOS4X12_GPIO_K02, + EXYNOS4X12_GPIO_K03, + EXYNOS4X12_GPIO_K04, + EXYNOS4X12_GPIO_K05, + EXYNOS4X12_GPIO_K06, + EXYNOS4X12_GPIO_K07, + EXYNOS4X12_GPIO_K10, /* 112 0x70 */ + EXYNOS4X12_GPIO_K11, + EXYNOS4X12_GPIO_K12, + EXYNOS4X12_GPIO_K13, + EXYNOS4X12_GPIO_K14, + EXYNOS4X12_GPIO_K15, + EXYNOS4X12_GPIO_K16, + EXYNOS4X12_GPIO_K17, + EXYNOS4X12_GPIO_K20, /* 120 0x78 */ + EXYNOS4X12_GPIO_K21, + EXYNOS4X12_GPIO_K22, + EXYNOS4X12_GPIO_K23, + EXYNOS4X12_GPIO_K24, + EXYNOS4X12_GPIO_K25, + EXYNOS4X12_GPIO_K26, + EXYNOS4X12_GPIO_K27, + EXYNOS4X12_GPIO_K30, /* 128 0x80 */ + EXYNOS4X12_GPIO_K31, + EXYNOS4X12_GPIO_K32, + EXYNOS4X12_GPIO_K33, + EXYNOS4X12_GPIO_K34, + EXYNOS4X12_GPIO_K35, + EXYNOS4X12_GPIO_K36, + EXYNOS4X12_GPIO_K37, + EXYNOS4X12_GPIO_L00, /* 136 0x88 */ + EXYNOS4X12_GPIO_L01, + EXYNOS4X12_GPIO_L02, + EXYNOS4X12_GPIO_L03, + EXYNOS4X12_GPIO_L04, + EXYNOS4X12_GPIO_L05, + EXYNOS4X12_GPIO_L06, + EXYNOS4X12_GPIO_L07, + EXYNOS4X12_GPIO_L10, /* 144 0x90 */ + EXYNOS4X12_GPIO_L11, + EXYNOS4X12_GPIO_L12, + EXYNOS4X12_GPIO_L13, + EXYNOS4X12_GPIO_L14, + EXYNOS4X12_GPIO_L15, + EXYNOS4X12_GPIO_L16, + EXYNOS4X12_GPIO_L17, + EXYNOS4X12_GPIO_L20, /* 152 0x98 */ + EXYNOS4X12_GPIO_L21, + EXYNOS4X12_GPIO_L22, + EXYNOS4X12_GPIO_L23, + EXYNOS4X12_GPIO_L24, + EXYNOS4X12_GPIO_L25, + EXYNOS4X12_GPIO_L26, + EXYNOS4X12_GPIO_L27, + EXYNOS4X12_GPIO_Y00, /* 160 0xa0 */ + EXYNOS4X12_GPIO_Y01, + EXYNOS4X12_GPIO_Y02, + EXYNOS4X12_GPIO_Y03, + EXYNOS4X12_GPIO_Y04, + EXYNOS4X12_GPIO_Y05, + EXYNOS4X12_GPIO_Y06, + EXYNOS4X12_GPIO_Y07, + EXYNOS4X12_GPIO_Y10, /* 168 0xa8 */ + EXYNOS4X12_GPIO_Y11, + EXYNOS4X12_GPIO_Y12, + EXYNOS4X12_GPIO_Y13, + EXYNOS4X12_GPIO_Y14, + EXYNOS4X12_GPIO_Y15, + EXYNOS4X12_GPIO_Y16, + EXYNOS4X12_GPIO_Y17, + EXYNOS4X12_GPIO_Y20, /* 176 0xb0 */ + EXYNOS4X12_GPIO_Y21, + EXYNOS4X12_GPIO_Y22, + EXYNOS4X12_GPIO_Y23, + EXYNOS4X12_GPIO_Y24, + EXYNOS4X12_GPIO_Y25, + EXYNOS4X12_GPIO_Y26, + EXYNOS4X12_GPIO_Y27, + EXYNOS4X12_GPIO_Y30, /* 184 0xb8 */ + EXYNOS4X12_GPIO_Y31, + EXYNOS4X12_GPIO_Y32, + EXYNOS4X12_GPIO_Y33, + EXYNOS4X12_GPIO_Y34, + EXYNOS4X12_GPIO_Y35, + EXYNOS4X12_GPIO_Y36, + EXYNOS4X12_GPIO_Y37, + EXYNOS4X12_GPIO_Y40, /* 192 0xc0 */ + EXYNOS4X12_GPIO_Y41, + EXYNOS4X12_GPIO_Y42, + EXYNOS4X12_GPIO_Y43, + EXYNOS4X12_GPIO_Y44, + EXYNOS4X12_GPIO_Y45, + EXYNOS4X12_GPIO_Y46, + EXYNOS4X12_GPIO_Y47, + EXYNOS4X12_GPIO_Y50, /* 200 0xc8 */ + EXYNOS4X12_GPIO_Y51, + EXYNOS4X12_GPIO_Y52, + EXYNOS4X12_GPIO_Y53, + EXYNOS4X12_GPIO_Y54, + EXYNOS4X12_GPIO_Y55, + EXYNOS4X12_GPIO_Y56, + EXYNOS4X12_GPIO_Y57, + EXYNOS4X12_GPIO_Y60, /* 208 0xd0 */ + EXYNOS4X12_GPIO_Y61, + EXYNOS4X12_GPIO_Y62, + EXYNOS4X12_GPIO_Y63, + EXYNOS4X12_GPIO_Y64, + EXYNOS4X12_GPIO_Y65, + EXYNOS4X12_GPIO_Y66, + EXYNOS4X12_GPIO_Y67, + EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */ + /* EXYNOS4X12_GPIO_PART2_2 starts here */ + EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, + EXYNOS4X12_GPIO_M01, + EXYNOS4X12_GPIO_M02, + EXYNOS4X12_GPIO_M03, + EXYNOS4X12_GPIO_M04, + EXYNOS4X12_GPIO_M05, + EXYNOS4X12_GPIO_M06, + EXYNOS4X12_GPIO_M07, + EXYNOS4X12_GPIO_M10, /* 224 0xe0 */ + EXYNOS4X12_GPIO_M11, + EXYNOS4X12_GPIO_M12, + EXYNOS4X12_GPIO_M13, + EXYNOS4X12_GPIO_M14, + EXYNOS4X12_GPIO_M15, + EXYNOS4X12_GPIO_M16, + EXYNOS4X12_GPIO_M17, + EXYNOS4X12_GPIO_M20, /* 232 0xe8 */ + EXYNOS4X12_GPIO_M21, + EXYNOS4X12_GPIO_M22, + EXYNOS4X12_GPIO_M23, + EXYNOS4X12_GPIO_M24, + EXYNOS4X12_GPIO_M25, + EXYNOS4X12_GPIO_M26, + EXYNOS4X12_GPIO_M27, + EXYNOS4X12_GPIO_M30, /* 240 0xf0 */ + EXYNOS4X12_GPIO_M31, + EXYNOS4X12_GPIO_M32, + EXYNOS4X12_GPIO_M33, + EXYNOS4X12_GPIO_M34, + EXYNOS4X12_GPIO_M35, + EXYNOS4X12_GPIO_M36, + EXYNOS4X12_GPIO_M37, + EXYNOS4X12_GPIO_M40, /* 248 0xf8 */ + EXYNOS4X12_GPIO_M41, + EXYNOS4X12_GPIO_M42, + EXYNOS4X12_GPIO_M43, + EXYNOS4X12_GPIO_M44, + EXYNOS4X12_GPIO_M45, + EXYNOS4X12_GPIO_M46, + EXYNOS4X12_GPIO_M47, + EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */ + /* EXYNOS4X12_GPIO_PART2_3 starts here */ + EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, + EXYNOS4X12_GPIO_X01, + EXYNOS4X12_GPIO_X02, + EXYNOS4X12_GPIO_X03, + EXYNOS4X12_GPIO_X04, + EXYNOS4X12_GPIO_X05, + EXYNOS4X12_GPIO_X06, + EXYNOS4X12_GPIO_X07, + EXYNOS4X12_GPIO_X10, /* 264 0x108 */ + EXYNOS4X12_GPIO_X11, + EXYNOS4X12_GPIO_X12, + EXYNOS4X12_GPIO_X13, + EXYNOS4X12_GPIO_X14, + EXYNOS4X12_GPIO_X15, + EXYNOS4X12_GPIO_X16, + EXYNOS4X12_GPIO_X17, + EXYNOS4X12_GPIO_X20, /* 272 0x110 */ + EXYNOS4X12_GPIO_X21, + EXYNOS4X12_GPIO_X22, + EXYNOS4X12_GPIO_X23, + EXYNOS4X12_GPIO_X24, + EXYNOS4X12_GPIO_X25, + EXYNOS4X12_GPIO_X26, + EXYNOS4X12_GPIO_X27, + EXYNOS4X12_GPIO_X30, /* 280 0x118 */ + EXYNOS4X12_GPIO_X31, + EXYNOS4X12_GPIO_X32, + EXYNOS4X12_GPIO_X33, + EXYNOS4X12_GPIO_X34, + EXYNOS4X12_GPIO_X35, + EXYNOS4X12_GPIO_X36, + EXYNOS4X12_GPIO_X37, + + /* EXYNOS4X12_GPIO_PART3 starts here */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */ + EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, + EXYNOS4X12_GPIO_Z1, + EXYNOS4X12_GPIO_Z2, + EXYNOS4X12_GPIO_Z3, + EXYNOS4X12_GPIO_Z4, + EXYNOS4X12_GPIO_Z5, + EXYNOS4X12_GPIO_Z6, + EXYNOS4X12_GPIO_Z7, + + /* EXYNOS4X12_GPIO_PART4 starts here */ + EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ + EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, + EXYNOS4X12_GPIO_V01, + EXYNOS4X12_GPIO_V02, + EXYNOS4X12_GPIO_V03, + EXYNOS4X12_GPIO_V04, + EXYNOS4X12_GPIO_V05, + EXYNOS4X12_GPIO_V06, + EXYNOS4X12_GPIO_V07, + EXYNOS4X12_GPIO_V10, /* 304 0x130 */ + EXYNOS4X12_GPIO_V11, + EXYNOS4X12_GPIO_V12, + EXYNOS4X12_GPIO_V13, + EXYNOS4X12_GPIO_V14, + EXYNOS4X12_GPIO_V15, + EXYNOS4X12_GPIO_V16, + EXYNOS4X12_GPIO_V17, + EXYNOS4X12_GPIO_V20, /* 312 0x138 */ + EXYNOS4X12_GPIO_V21, + EXYNOS4X12_GPIO_V22, + EXYNOS4X12_GPIO_V23, + EXYNOS4X12_GPIO_V24, + EXYNOS4X12_GPIO_V25, + EXYNOS4X12_GPIO_V26, + EXYNOS4X12_GPIO_V27, + EXYNOS4X12_GPIO_V30, /* 320 0x140 */ + EXYNOS4X12_GPIO_V31, + EXYNOS4X12_GPIO_V32, + EXYNOS4X12_GPIO_V33, + EXYNOS4X12_GPIO_V34, + EXYNOS4X12_GPIO_V35, + EXYNOS4X12_GPIO_V36, + EXYNOS4X12_GPIO_V37, + EXYNOS4X12_GPIO_V40, /* 328 0x148 */ + EXYNOS4X12_GPIO_V41, + EXYNOS4X12_GPIO_V42, + EXYNOS4X12_GPIO_V43, + EXYNOS4X12_GPIO_V44, + EXYNOS4X12_GPIO_V45, + EXYNOS4X12_GPIO_V46, + EXYNOS4X12_GPIO_V47, + + EXYNOS4X12_GPIO_MAX_PORT }; -struct exynos4x12_gpio_part4 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; +enum exynos5_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS5_GPIO_A00, /* 0 */ + EXYNOS5_GPIO_A01, + EXYNOS5_GPIO_A02, + EXYNOS5_GPIO_A03, + EXYNOS5_GPIO_A04, + EXYNOS5_GPIO_A05, + EXYNOS5_GPIO_A06, + EXYNOS5_GPIO_A07, + EXYNOS5_GPIO_A10, /* 8 */ + EXYNOS5_GPIO_A11, + EXYNOS5_GPIO_A12, + EXYNOS5_GPIO_A13, + EXYNOS5_GPIO_A14, + EXYNOS5_GPIO_A15, + EXYNOS5_GPIO_A16, + EXYNOS5_GPIO_A17, + EXYNOS5_GPIO_A20, /* 16 0x10 */ + EXYNOS5_GPIO_A21, + EXYNOS5_GPIO_A22, + EXYNOS5_GPIO_A23, + EXYNOS5_GPIO_A24, + EXYNOS5_GPIO_A25, + EXYNOS5_GPIO_A26, + EXYNOS5_GPIO_A27, + EXYNOS5_GPIO_B00, /* 24 0x18 */ + EXYNOS5_GPIO_B01, + EXYNOS5_GPIO_B02, + EXYNOS5_GPIO_B03, + EXYNOS5_GPIO_B04, + EXYNOS5_GPIO_B05, + EXYNOS5_GPIO_B06, + EXYNOS5_GPIO_B07, + EXYNOS5_GPIO_B10, /* 32 0x20 */ + EXYNOS5_GPIO_B11, + EXYNOS5_GPIO_B12, + EXYNOS5_GPIO_B13, + EXYNOS5_GPIO_B14, + EXYNOS5_GPIO_B15, + EXYNOS5_GPIO_B16, + EXYNOS5_GPIO_B17, + EXYNOS5_GPIO_B20, /* 40 0x28 */ + EXYNOS5_GPIO_B21, + EXYNOS5_GPIO_B22, + EXYNOS5_GPIO_B23, + EXYNOS5_GPIO_B24, + EXYNOS5_GPIO_B25, + EXYNOS5_GPIO_B26, + EXYNOS5_GPIO_B27, + EXYNOS5_GPIO_B30, /* 48 0x39 */ + EXYNOS5_GPIO_B31, + EXYNOS5_GPIO_B32, + EXYNOS5_GPIO_B33, + EXYNOS5_GPIO_B34, + EXYNOS5_GPIO_B35, + EXYNOS5_GPIO_B36, + EXYNOS5_GPIO_B37, + EXYNOS5_GPIO_C00, /* 56 0x38 */ + EXYNOS5_GPIO_C01, + EXYNOS5_GPIO_C02, + EXYNOS5_GPIO_C03, + EXYNOS5_GPIO_C04, + EXYNOS5_GPIO_C05, + EXYNOS5_GPIO_C06, + EXYNOS5_GPIO_C07, + EXYNOS5_GPIO_C10, /* 64 0x40 */ + EXYNOS5_GPIO_C11, + EXYNOS5_GPIO_C12, + EXYNOS5_GPIO_C13, + EXYNOS5_GPIO_C14, + EXYNOS5_GPIO_C15, + EXYNOS5_GPIO_C16, + EXYNOS5_GPIO_C17, + EXYNOS5_GPIO_C20, /* 72 0x48 */ + EXYNOS5_GPIO_C21, + EXYNOS5_GPIO_C22, + EXYNOS5_GPIO_C23, + EXYNOS5_GPIO_C24, + EXYNOS5_GPIO_C25, + EXYNOS5_GPIO_C26, + EXYNOS5_GPIO_C27, + EXYNOS5_GPIO_C30, /* 80 0x50 */ + EXYNOS5_GPIO_C31, + EXYNOS5_GPIO_C32, + EXYNOS5_GPIO_C33, + EXYNOS5_GPIO_C34, + EXYNOS5_GPIO_C35, + EXYNOS5_GPIO_C36, + EXYNOS5_GPIO_C37, + EXYNOS5_GPIO_D00, /* 88 0x58 */ + EXYNOS5_GPIO_D01, + EXYNOS5_GPIO_D02, + EXYNOS5_GPIO_D03, + EXYNOS5_GPIO_D04, + EXYNOS5_GPIO_D05, + EXYNOS5_GPIO_D06, + EXYNOS5_GPIO_D07, + EXYNOS5_GPIO_D10, /* 96 0x60 */ + EXYNOS5_GPIO_D11, + EXYNOS5_GPIO_D12, + EXYNOS5_GPIO_D13, + EXYNOS5_GPIO_D14, + EXYNOS5_GPIO_D15, + EXYNOS5_GPIO_D16, + EXYNOS5_GPIO_D17, + EXYNOS5_GPIO_Y00, /* 104 0x68 */ + EXYNOS5_GPIO_Y01, + EXYNOS5_GPIO_Y02, + EXYNOS5_GPIO_Y03, + EXYNOS5_GPIO_Y04, + EXYNOS5_GPIO_Y05, + EXYNOS5_GPIO_Y06, + EXYNOS5_GPIO_Y07, + EXYNOS5_GPIO_Y10, /* 112 0x70 */ + EXYNOS5_GPIO_Y11, + EXYNOS5_GPIO_Y12, + EXYNOS5_GPIO_Y13, + EXYNOS5_GPIO_Y14, + EXYNOS5_GPIO_Y15, + EXYNOS5_GPIO_Y16, + EXYNOS5_GPIO_Y17, + EXYNOS5_GPIO_Y20, /* 120 0x78 */ + EXYNOS5_GPIO_Y21, + EXYNOS5_GPIO_Y22, + EXYNOS5_GPIO_Y23, + EXYNOS5_GPIO_Y24, + EXYNOS5_GPIO_Y25, + EXYNOS5_GPIO_Y26, + EXYNOS5_GPIO_Y27, + EXYNOS5_GPIO_Y30, /* 128 0x80 */ + EXYNOS5_GPIO_Y31, + EXYNOS5_GPIO_Y32, + EXYNOS5_GPIO_Y33, + EXYNOS5_GPIO_Y34, + EXYNOS5_GPIO_Y35, + EXYNOS5_GPIO_Y36, + EXYNOS5_GPIO_Y37, + EXYNOS5_GPIO_Y40, /* 136 0x88 */ + EXYNOS5_GPIO_Y41, + EXYNOS5_GPIO_Y42, + EXYNOS5_GPIO_Y43, + EXYNOS5_GPIO_Y44, + EXYNOS5_GPIO_Y45, + EXYNOS5_GPIO_Y46, + EXYNOS5_GPIO_Y47, + EXYNOS5_GPIO_Y50, /* 144 0x90 */ + EXYNOS5_GPIO_Y51, + EXYNOS5_GPIO_Y52, + EXYNOS5_GPIO_Y53, + EXYNOS5_GPIO_Y54, + EXYNOS5_GPIO_Y55, + EXYNOS5_GPIO_Y56, + EXYNOS5_GPIO_Y57, + EXYNOS5_GPIO_Y60, /* 152 0x98 */ + EXYNOS5_GPIO_Y61, + EXYNOS5_GPIO_Y62, + EXYNOS5_GPIO_Y63, + EXYNOS5_GPIO_Y64, + EXYNOS5_GPIO_Y65, + EXYNOS5_GPIO_Y66, + EXYNOS5_GPIO_Y67, + + /* GPIO_PART2_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_1, /* 160 0xa0 */ + EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1, + EXYNOS5_GPIO_C41, + EXYNOS5_GPIO_C42, + EXYNOS5_GPIO_C43, + EXYNOS5_GPIO_C44, + EXYNOS5_GPIO_C45, + EXYNOS5_GPIO_C46, + EXYNOS5_GPIO_C47, + + /* GPIO_PART3_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_2, /* 168 0xa8 */ + EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2, + EXYNOS5_GPIO_X01, + EXYNOS5_GPIO_X02, + EXYNOS5_GPIO_X03, + EXYNOS5_GPIO_X04, + EXYNOS5_GPIO_X05, + EXYNOS5_GPIO_X06, + EXYNOS5_GPIO_X07, + EXYNOS5_GPIO_X10, /* 176 0xb0 */ + EXYNOS5_GPIO_X11, + EXYNOS5_GPIO_X12, + EXYNOS5_GPIO_X13, + EXYNOS5_GPIO_X14, + EXYNOS5_GPIO_X15, + EXYNOS5_GPIO_X16, + EXYNOS5_GPIO_X17, + EXYNOS5_GPIO_X20, /* 184 0xb8 */ + EXYNOS5_GPIO_X21, + EXYNOS5_GPIO_X22, + EXYNOS5_GPIO_X23, + EXYNOS5_GPIO_X24, + EXYNOS5_GPIO_X25, + EXYNOS5_GPIO_X26, + EXYNOS5_GPIO_X27, + EXYNOS5_GPIO_X30, /* 192 0xc0 */ + EXYNOS5_GPIO_X31, + EXYNOS5_GPIO_X32, + EXYNOS5_GPIO_X33, + EXYNOS5_GPIO_X34, + EXYNOS5_GPIO_X35, + EXYNOS5_GPIO_X36, + EXYNOS5_GPIO_X37, + + /* GPIO_PART4_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_3, /* 200 0xc8 */ + EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3, + EXYNOS5_GPIO_E01, + EXYNOS5_GPIO_E02, + EXYNOS5_GPIO_E03, + EXYNOS5_GPIO_E04, + EXYNOS5_GPIO_E05, + EXYNOS5_GPIO_E06, + EXYNOS5_GPIO_E07, + EXYNOS5_GPIO_E10, /* 208 0xd0 */ + EXYNOS5_GPIO_E11, + EXYNOS5_GPIO_E12, + EXYNOS5_GPIO_E13, + EXYNOS5_GPIO_E14, + EXYNOS5_GPIO_E15, + EXYNOS5_GPIO_E16, + EXYNOS5_GPIO_E17, + EXYNOS5_GPIO_F00, /* 216 0xd8 */ + EXYNOS5_GPIO_F01, + EXYNOS5_GPIO_F02, + EXYNOS5_GPIO_F03, + EXYNOS5_GPIO_F04, + EXYNOS5_GPIO_F05, + EXYNOS5_GPIO_F06, + EXYNOS5_GPIO_F07, + EXYNOS5_GPIO_F10, /* 224 0xe0 */ + EXYNOS5_GPIO_F11, + EXYNOS5_GPIO_F12, + EXYNOS5_GPIO_F13, + EXYNOS5_GPIO_F14, + EXYNOS5_GPIO_F15, + EXYNOS5_GPIO_F16, + EXYNOS5_GPIO_F17, + EXYNOS5_GPIO_G00, /* 232 0xe8 */ + EXYNOS5_GPIO_G01, + EXYNOS5_GPIO_G02, + EXYNOS5_GPIO_G03, + EXYNOS5_GPIO_G04, + EXYNOS5_GPIO_G05, + EXYNOS5_GPIO_G06, + EXYNOS5_GPIO_G07, + EXYNOS5_GPIO_G10, /* 240 0xf0 */ + EXYNOS5_GPIO_G11, + EXYNOS5_GPIO_G12, + EXYNOS5_GPIO_G13, + EXYNOS5_GPIO_G14, + EXYNOS5_GPIO_G15, + EXYNOS5_GPIO_G16, + EXYNOS5_GPIO_G17, + EXYNOS5_GPIO_G20, /* 248 0xf8 */ + EXYNOS5_GPIO_G21, + EXYNOS5_GPIO_G22, + EXYNOS5_GPIO_G23, + EXYNOS5_GPIO_G24, + EXYNOS5_GPIO_G25, + EXYNOS5_GPIO_G26, + EXYNOS5_GPIO_G27, + EXYNOS5_GPIO_H00, /* 256 0x100 */ + EXYNOS5_GPIO_H01, + EXYNOS5_GPIO_H02, + EXYNOS5_GPIO_H03, + EXYNOS5_GPIO_H04, + EXYNOS5_GPIO_H05, + EXYNOS5_GPIO_H06, + EXYNOS5_GPIO_H07, + EXYNOS5_GPIO_H10, /* 264 0x108 */ + EXYNOS5_GPIO_H11, + EXYNOS5_GPIO_H12, + EXYNOS5_GPIO_H13, + EXYNOS5_GPIO_H14, + EXYNOS5_GPIO_H15, + EXYNOS5_GPIO_H16, + EXYNOS5_GPIO_H17, + + /* GPIO_PART4_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_4, /* 272 0x110 */ + EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4, + EXYNOS5_GPIO_V01, + EXYNOS5_GPIO_V02, + EXYNOS5_GPIO_V03, + EXYNOS5_GPIO_V04, + EXYNOS5_GPIO_V05, + EXYNOS5_GPIO_V06, + EXYNOS5_GPIO_V07, + EXYNOS5_GPIO_V10, /* 280 0x118 */ + EXYNOS5_GPIO_V11, + EXYNOS5_GPIO_V12, + EXYNOS5_GPIO_V13, + EXYNOS5_GPIO_V14, + EXYNOS5_GPIO_V15, + EXYNOS5_GPIO_V16, + EXYNOS5_GPIO_V17, + + /* GPIO_PART5_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_5, /* 288 0x120 */ + EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5, + EXYNOS5_GPIO_V21, + EXYNOS5_GPIO_V22, + EXYNOS5_GPIO_V23, + EXYNOS5_GPIO_V24, + EXYNOS5_GPIO_V25, + EXYNOS5_GPIO_V26, + EXYNOS5_GPIO_V27, + EXYNOS5_GPIO_V30, /* 296 0x128 */ + EXYNOS5_GPIO_V31, + EXYNOS5_GPIO_V32, + EXYNOS5_GPIO_V33, + EXYNOS5_GPIO_V34, + EXYNOS5_GPIO_V35, + EXYNOS5_GPIO_V36, + EXYNOS5_GPIO_V37, + + /* GPIO_PART6_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_6, /* 304 0x130 */ + EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6, + EXYNOS5_GPIO_V41, + EXYNOS5_GPIO_V42, + EXYNOS5_GPIO_V43, + EXYNOS5_GPIO_V44, + EXYNOS5_GPIO_V45, + EXYNOS5_GPIO_V46, + EXYNOS5_GPIO_V47, + + /* GPIO_PART7_STARTS */ /* 312 0x138 */ + EXYNOS5_GPIO_MAX_PORT_PART_7, + EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7, + EXYNOS5_GPIO_Z1, + EXYNOS5_GPIO_Z2, + EXYNOS5_GPIO_Z3, + EXYNOS5_GPIO_Z4, + EXYNOS5_GPIO_Z5, + EXYNOS5_GPIO_Z6, + EXYNOS5_GPIO_MAX_PORT }; -struct exynos5_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[0x3]; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank res2[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; +enum exynos5420_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS5420_GPIO_A00, /* 0 */ + EXYNOS5420_GPIO_A01, + EXYNOS5420_GPIO_A02, + EXYNOS5420_GPIO_A03, + EXYNOS5420_GPIO_A04, + EXYNOS5420_GPIO_A05, + EXYNOS5420_GPIO_A06, + EXYNOS5420_GPIO_A07, + EXYNOS5420_GPIO_A10, /* 8 */ + EXYNOS5420_GPIO_A11, + EXYNOS5420_GPIO_A12, + EXYNOS5420_GPIO_A13, + EXYNOS5420_GPIO_A14, + EXYNOS5420_GPIO_A15, + EXYNOS5420_GPIO_A16, + EXYNOS5420_GPIO_A17, + EXYNOS5420_GPIO_A20, /* 16 0x10 */ + EXYNOS5420_GPIO_A21, + EXYNOS5420_GPIO_A22, + EXYNOS5420_GPIO_A23, + EXYNOS5420_GPIO_A24, + EXYNOS5420_GPIO_A25, + EXYNOS5420_GPIO_A26, + EXYNOS5420_GPIO_A27, + EXYNOS5420_GPIO_B00, /* 24 0x18 */ + EXYNOS5420_GPIO_B01, + EXYNOS5420_GPIO_B02, + EXYNOS5420_GPIO_B03, + EXYNOS5420_GPIO_B04, + EXYNOS5420_GPIO_B05, + EXYNOS5420_GPIO_B06, + EXYNOS5420_GPIO_B07, + EXYNOS5420_GPIO_B10, /* 32 0x20 */ + EXYNOS5420_GPIO_B11, + EXYNOS5420_GPIO_B12, + EXYNOS5420_GPIO_B13, + EXYNOS5420_GPIO_B14, + EXYNOS5420_GPIO_B15, + EXYNOS5420_GPIO_B16, + EXYNOS5420_GPIO_B17, + EXYNOS5420_GPIO_B20, /* 40 0x28 */ + EXYNOS5420_GPIO_B21, + EXYNOS5420_GPIO_B22, + EXYNOS5420_GPIO_B23, + EXYNOS5420_GPIO_B24, + EXYNOS5420_GPIO_B25, + EXYNOS5420_GPIO_B26, + EXYNOS5420_GPIO_B27, + EXYNOS5420_GPIO_B30, /* 48 0x30 */ + EXYNOS5420_GPIO_B31, + EXYNOS5420_GPIO_B32, + EXYNOS5420_GPIO_B33, + EXYNOS5420_GPIO_B34, + EXYNOS5420_GPIO_B35, + EXYNOS5420_GPIO_B36, + EXYNOS5420_GPIO_B37, + EXYNOS5420_GPIO_B40, /* 56 0x38 */ + EXYNOS5420_GPIO_B41, + EXYNOS5420_GPIO_B42, + EXYNOS5420_GPIO_B43, + EXYNOS5420_GPIO_B44, + EXYNOS5420_GPIO_B45, + EXYNOS5420_GPIO_B46, + EXYNOS5420_GPIO_B47, + EXYNOS5420_GPIO_H00, /* 64 0x40 */ + EXYNOS5420_GPIO_H01, + EXYNOS5420_GPIO_H02, + EXYNOS5420_GPIO_H03, + EXYNOS5420_GPIO_H04, + EXYNOS5420_GPIO_H05, + EXYNOS5420_GPIO_H06, + EXYNOS5420_GPIO_H07, + + /* GPIO PART 2 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */ + EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1, + EXYNOS5420_GPIO_Y71, + EXYNOS5420_GPIO_Y72, + EXYNOS5420_GPIO_Y73, + EXYNOS5420_GPIO_Y74, + EXYNOS5420_GPIO_Y75, + EXYNOS5420_GPIO_Y76, + EXYNOS5420_GPIO_Y77, + + /* GPIO PART 3 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */ + EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, + EXYNOS5420_GPIO_X01, + EXYNOS5420_GPIO_X02, + EXYNOS5420_GPIO_X03, + EXYNOS5420_GPIO_X04, + EXYNOS5420_GPIO_X05, + EXYNOS5420_GPIO_X06, + EXYNOS5420_GPIO_X07, + EXYNOS5420_GPIO_X10, /* 88 0x58 */ + EXYNOS5420_GPIO_X11, + EXYNOS5420_GPIO_X12, + EXYNOS5420_GPIO_X13, + EXYNOS5420_GPIO_X14, + EXYNOS5420_GPIO_X15, + EXYNOS5420_GPIO_X16, + EXYNOS5420_GPIO_X17, + EXYNOS5420_GPIO_X20, /* 96 0x60 */ + EXYNOS5420_GPIO_X21, + EXYNOS5420_GPIO_X22, + EXYNOS5420_GPIO_X23, + EXYNOS5420_GPIO_X24, + EXYNOS5420_GPIO_X25, + EXYNOS5420_GPIO_X26, + EXYNOS5420_GPIO_X27, + EXYNOS5420_GPIO_X30, /* 104 0x68 */ + EXYNOS5420_GPIO_X31, + EXYNOS5420_GPIO_X32, + EXYNOS5420_GPIO_X33, + EXYNOS5420_GPIO_X34, + EXYNOS5420_GPIO_X35, + EXYNOS5420_GPIO_X36, + EXYNOS5420_GPIO_X37, + + /* GPIO PART 4 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */ + EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_C01, + EXYNOS5420_GPIO_C02, + EXYNOS5420_GPIO_C03, + EXYNOS5420_GPIO_C04, + EXYNOS5420_GPIO_C05, + EXYNOS5420_GPIO_C06, + EXYNOS5420_GPIO_C07, + EXYNOS5420_GPIO_C10, /* 120 0x78 */ + EXYNOS5420_GPIO_C11, + EXYNOS5420_GPIO_C12, + EXYNOS5420_GPIO_C13, + EXYNOS5420_GPIO_C14, + EXYNOS5420_GPIO_C15, + EXYNOS5420_GPIO_C16, + EXYNOS5420_GPIO_C17, + EXYNOS5420_GPIO_C20, /* 128 0x80 */ + EXYNOS5420_GPIO_C21, + EXYNOS5420_GPIO_C22, + EXYNOS5420_GPIO_C23, + EXYNOS5420_GPIO_C24, + EXYNOS5420_GPIO_C25, + EXYNOS5420_GPIO_C26, + EXYNOS5420_GPIO_C27, + EXYNOS5420_GPIO_C30, /* 136 0x88 */ + EXYNOS5420_GPIO_C31, + EXYNOS5420_GPIO_C32, + EXYNOS5420_GPIO_C33, + EXYNOS5420_GPIO_C34, + EXYNOS5420_GPIO_C35, + EXYNOS5420_GPIO_C36, + EXYNOS5420_GPIO_C37, + EXYNOS5420_GPIO_C40, /* 144 0x90 */ + EXYNOS5420_GPIO_C41, + EXYNOS5420_GPIO_C42, + EXYNOS5420_GPIO_C43, + EXYNOS5420_GPIO_C44, + EXYNOS5420_GPIO_C45, + EXYNOS5420_GPIO_C46, + EXYNOS5420_GPIO_C47, + EXYNOS5420_GPIO_D10, /* 152 0x98 */ + EXYNOS5420_GPIO_D11, + EXYNOS5420_GPIO_D12, + EXYNOS5420_GPIO_D13, + EXYNOS5420_GPIO_D14, + EXYNOS5420_GPIO_D15, + EXYNOS5420_GPIO_D16, + EXYNOS5420_GPIO_D17, + EXYNOS5420_GPIO_Y00, /* 160 0xa0 */ + EXYNOS5420_GPIO_Y01, + EXYNOS5420_GPIO_Y02, + EXYNOS5420_GPIO_Y03, + EXYNOS5420_GPIO_Y04, + EXYNOS5420_GPIO_Y05, + EXYNOS5420_GPIO_Y06, + EXYNOS5420_GPIO_Y07, + EXYNOS5420_GPIO_Y10, /* 168 0xa8 */ + EXYNOS5420_GPIO_Y11, + EXYNOS5420_GPIO_Y12, + EXYNOS5420_GPIO_Y13, + EXYNOS5420_GPIO_Y14, + EXYNOS5420_GPIO_Y15, + EXYNOS5420_GPIO_Y16, + EXYNOS5420_GPIO_Y17, + EXYNOS5420_GPIO_Y20, /* 176 0xb0 */ + EXYNOS5420_GPIO_Y21, + EXYNOS5420_GPIO_Y22, + EXYNOS5420_GPIO_Y23, + EXYNOS5420_GPIO_Y24, + EXYNOS5420_GPIO_Y25, + EXYNOS5420_GPIO_Y26, + EXYNOS5420_GPIO_Y27, + EXYNOS5420_GPIO_Y30, /* 184 0xb8 */ + EXYNOS5420_GPIO_Y31, + EXYNOS5420_GPIO_Y32, + EXYNOS5420_GPIO_Y33, + EXYNOS5420_GPIO_Y34, + EXYNOS5420_GPIO_Y35, + EXYNOS5420_GPIO_Y36, + EXYNOS5420_GPIO_Y37, + EXYNOS5420_GPIO_Y40, /* 192 0xc0 */ + EXYNOS5420_GPIO_Y41, + EXYNOS5420_GPIO_Y42, + EXYNOS5420_GPIO_Y43, + EXYNOS5420_GPIO_Y44, + EXYNOS5420_GPIO_Y45, + EXYNOS5420_GPIO_Y46, + EXYNOS5420_GPIO_Y47, + EXYNOS5420_GPIO_Y50, /* 200 0xc8 */ + EXYNOS5420_GPIO_Y51, + EXYNOS5420_GPIO_Y52, + EXYNOS5420_GPIO_Y53, + EXYNOS5420_GPIO_Y54, + EXYNOS5420_GPIO_Y55, + EXYNOS5420_GPIO_Y56, + EXYNOS5420_GPIO_Y57, + EXYNOS5420_GPIO_Y60, /* 208 0xd0 */ + EXYNOS5420_GPIO_Y61, + EXYNOS5420_GPIO_Y62, + EXYNOS5420_GPIO_Y63, + EXYNOS5420_GPIO_Y64, + EXYNOS5420_GPIO_Y65, + EXYNOS5420_GPIO_Y66, + EXYNOS5420_GPIO_Y67, + + /* GPIO_PART5_STARTS */ + EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */ + EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4, + EXYNOS5420_GPIO_E01, + EXYNOS5420_GPIO_E02, + EXYNOS5420_GPIO_E03, + EXYNOS5420_GPIO_E04, + EXYNOS5420_GPIO_E05, + EXYNOS5420_GPIO_E06, + EXYNOS5420_GPIO_E07, + EXYNOS5420_GPIO_E10, /* 224 0xe0 */ + EXYNOS5420_GPIO_E11, + EXYNOS5420_GPIO_E12, + EXYNOS5420_GPIO_E13, + EXYNOS5420_GPIO_E14, + EXYNOS5420_GPIO_E15, + EXYNOS5420_GPIO_E16, + EXYNOS5420_GPIO_E17, + EXYNOS5420_GPIO_F00, /* 232 0xe8 */ + EXYNOS5420_GPIO_F01, + EXYNOS5420_GPIO_F02, + EXYNOS5420_GPIO_F03, + EXYNOS5420_GPIO_F04, + EXYNOS5420_GPIO_F05, + EXYNOS5420_GPIO_F06, + EXYNOS5420_GPIO_F07, + EXYNOS5420_GPIO_F10, /* 240 0xf0 */ + EXYNOS5420_GPIO_F11, + EXYNOS5420_GPIO_F12, + EXYNOS5420_GPIO_F13, + EXYNOS5420_GPIO_F14, + EXYNOS5420_GPIO_F15, + EXYNOS5420_GPIO_F16, + EXYNOS5420_GPIO_F17, + EXYNOS5420_GPIO_G00, /* 248 0xf8 */ + EXYNOS5420_GPIO_G01, + EXYNOS5420_GPIO_G02, + EXYNOS5420_GPIO_G03, + EXYNOS5420_GPIO_G04, + EXYNOS5420_GPIO_G05, + EXYNOS5420_GPIO_G06, + EXYNOS5420_GPIO_G07, + EXYNOS5420_GPIO_G10, /* 256 0x100 */ + EXYNOS5420_GPIO_G11, + EXYNOS5420_GPIO_G12, + EXYNOS5420_GPIO_G13, + EXYNOS5420_GPIO_G14, + EXYNOS5420_GPIO_G15, + EXYNOS5420_GPIO_G16, + EXYNOS5420_GPIO_G17, + EXYNOS5420_GPIO_G20, /* 264 0x108 */ + EXYNOS5420_GPIO_G21, + EXYNOS5420_GPIO_G22, + EXYNOS5420_GPIO_G23, + EXYNOS5420_GPIO_G24, + EXYNOS5420_GPIO_G25, + EXYNOS5420_GPIO_G26, + EXYNOS5420_GPIO_G27, + EXYNOS5420_GPIO_J40, /* 272 0x110 */ + EXYNOS5420_GPIO_J41, + EXYNOS5420_GPIO_J42, + EXYNOS5420_GPIO_J43, + EXYNOS5420_GPIO_J44, + EXYNOS5420_GPIO_J45, + EXYNOS5420_GPIO_J46, + EXYNOS5420_GPIO_J47, + + /* GPIO_PART6_STARTS */ + EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */ + EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5, + EXYNOS5420_GPIO_Z1, + EXYNOS5420_GPIO_Z2, + EXYNOS5420_GPIO_Z3, + EXYNOS5420_GPIO_Z4, + EXYNOS5420_GPIO_Z5, + EXYNOS5420_GPIO_Z6, + EXYNOS5420_GPIO_MAX_PORT }; -struct exynos5_gpio_part2 { - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ }; -struct exynos5_gpio_part3 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; +#define EXYNOS4_GPIO_NUM_PARTS 4 +static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { + { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 }, + { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 }, + { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 }, + { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT }, }; -struct exynos5_gpio_part4 { - struct s5p_gpio_bank z; +#define EXYNOS4X12_GPIO_NUM_PARTS 8 +static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = { + { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 }, + { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 }, + { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 }, + { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 }, + { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 }, + { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 }, + { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, + { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT }, }; -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +#define EXYNOS5_GPIO_NUM_PARTS 8 +static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = { + { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 }, + { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 }, + { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 }, + { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 }, + { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT }, +}; -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 +#define EXYNOS5420_GPIO_NUM_PARTS 6 +static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { + { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 }, + { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 }, + { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT }, +}; -#define exynos4_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \ - EXYNOS4_GPIO_PART1_BASE)->bank)) \ - - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \ - EXYNOS4_GPIO_PART2_BASE)->bank)) \ - - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) - -#define exynos4x12_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ - EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4x12_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ - EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) - -#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4x12_gpio_part3_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ - EXYNOS4X12_GPIO_PART3_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) - -#define exynos5_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ - EXYNOS5_GPIO_PART1_BASE)->bank)) \ - - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \ - EXYNOS5_GPIO_PART2_BASE)->bank)) \ - - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX) - -#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part3_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \ - EXYNOS5_GPIO_PART3_BASE)->bank)) \ - - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) - -static inline unsigned int s5p_gpio_base(int nr) +static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return EXYNOS5_GPIO_PART1_BASE; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART2_BASE; + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos5420_gpio_data; else - return EXYNOS5_GPIO_PART3_BASE; - + return exynos5_gpio_data; } else if (cpu_is_exynos4()) { - if (nr < EXYNOS4_GPIO_PART1_MAX) - return EXYNOS4_GPIO_PART1_BASE; + if (proid_is_exynos4412()) + return exynos4x12_gpio_data; else - return EXYNOS4_GPIO_PART2_BASE; + return exynos4_gpio_data; } - return 0; + return NULL; } -static inline unsigned int s5p_gpio_part_max(int nr) +static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART1_MAX; + if (proid_is_exynos5420() || proid_is_exynos5800()) + return EXYNOS5420_GPIO_NUM_PARTS; else - return EXYNOS5_GPIO_PART2_MAX; - + return EXYNOS5_GPIO_NUM_PARTS; } else if (cpu_is_exynos4()) { - if (nr < EXYNOS4_GPIO_PART1_MAX) - return 0; + if (proid_is_exynos4412()) + return EXYNOS4X12_GPIO_NUM_PARTS; else - return EXYNOS4_GPIO_PART1_MAX; + return EXYNOS4_GPIO_NUM_PARTS; } return 0; } + +/* + * This structure helps mapping symbolic GPIO names into indices from + * exynos5_gpio_pin/exynos5420_gpio_pin enums. + * + * By convention, symbolic GPIO name is defined as follows: + * + * g[p], where + * p is optional + * - a single character bank name, as defined by the SOC + * - a single digit set number + * - bit number within the set (in 0..7 range). + * + * essentially form an octal number of the GPIO pin within the bank + * space. On the 5420 architecture some banks' sets do not start not from zero + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and + * maintain flat number space withoout holes, those banks use offsets to be + * deducted from the pin number. + */ +struct gpio_name_num_table { + char bank; /* bank name symbol */ + unsigned int bank_size; /* total number of pins in the bank */ + char bank_offset; /* offset of the first bank's pin */ + unsigned int base; /* index of the first bank's pin in the enum */ +}; + +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } +static const struct gpio_name_num_table exynos4_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS4_GPIO_A00, EXYNOS4_GPIO_B0, 0), + GPIO_ENTRY('b', EXYNOS4_GPIO_B0, EXYNOS4_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS4_GPIO_C00, EXYNOS4_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS4_GPIO_D00, EXYNOS4_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS4_GPIO_E00, EXYNOS4_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS4_GPIO_F00, EXYNOS4_GPIO_J00, 0), + GPIO_ENTRY('j', EXYNOS4_GPIO_J00, EXYNOS4_GPIO_K00, 0), + GPIO_ENTRY('k', EXYNOS4_GPIO_K00, EXYNOS4_GPIO_L00, 0), + GPIO_ENTRY('l', EXYNOS4_GPIO_L00, EXYNOS4_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS4_GPIO_Y00, EXYNOS4_GPIO_X00, 0), + GPIO_ENTRY('x', EXYNOS4_GPIO_X00, EXYNOS4_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS4_GPIO_Z0, EXYNOS4_GPIO_MAX_PORT, 0), + { 0 } +}; + +static const struct gpio_name_num_table exynos4x12_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS4X12_GPIO_A00, EXYNOS4X12_GPIO_B0, 0), + GPIO_ENTRY('b', EXYNOS4X12_GPIO_B0, EXYNOS4X12_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS4X12_GPIO_C00, EXYNOS4X12_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS4X12_GPIO_D00, EXYNOS4X12_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS4X12_GPIO_F00, EXYNOS4X12_GPIO_J00, 0), + GPIO_ENTRY('j', EXYNOS4X12_GPIO_J00, EXYNOS4X12_GPIO_K00, 0), + GPIO_ENTRY('k', EXYNOS4X12_GPIO_K00, EXYNOS4X12_GPIO_L00, 0), + GPIO_ENTRY('l', EXYNOS4X12_GPIO_L00, EXYNOS4X12_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS4X12_GPIO_Y00, EXYNOS4X12_GPIO_M00, 0), + GPIO_ENTRY('m', EXYNOS4X12_GPIO_M00, EXYNOS4X12_GPIO_X00, 0), + GPIO_ENTRY('x', EXYNOS4X12_GPIO_X00, EXYNOS4X12_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS4X12_GPIO_Z0, EXYNOS4X12_GPIO_V00, 0), + GPIO_ENTRY('v', EXYNOS4X12_GPIO_V00, EXYNOS4X12_GPIO_MAX_PORT, 0), + { 0 } +}; + +static const struct gpio_name_num_table exynos5_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0), + GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0), + GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0), + { 0 } +}; + +static const struct gpio_name_num_table exynos5420_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0), + GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010), + GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040), + GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0), + { 0 } +}; + +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); +void gpio_set_rate(int gpio, int mode); +int s5p_gpio_get_pin(unsigned gpio); #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x3 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x3 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h index 613b9b7a37..4a4a7a00b7 100644 --- a/arch/arm/include/asm/arch-exynos/i2s-regs.h +++ b/arch/arm/include/asm/arch-exynos/i2s-regs.h @@ -8,10 +8,12 @@ #ifndef __I2S_REGS_H__ #define __I2S_REGS_H__ +#define CON_RESET (1 << 31) #define CON_TXFIFO_FULL (1 << 8) #define CON_TXCH_PAUSE (1 << 4) #define CON_ACTIVE (1 << 0) +#define MOD_OP_CLK (3 << 30) #define MOD_BLCP_SHIFT 24 #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) @@ -24,6 +26,7 @@ #define MOD_BLC_MASK (3 << 13) #define MOD_SLAVE (1 << 11) +#define MOD_RCLKSRC (0 << 10) #define MOD_MASK (3 << 8) #define MOD_LR_LLOW (0 << 7) #define MOD_LR_RLOW (1 << 7) @@ -47,4 +50,7 @@ #define FIC_TXFLUSH (1 << 15) #define FIC_RXFLUSH (1 << 7) +#define PSREN (1 << 15) +#define PSVAL (3 << 8) + #endif /* __I2S_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h index 8916d9d16b..50e5c258a9 100644 --- a/arch/arm/include/asm/arch-exynos/mipi_dsim.h +++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _DSIM_H @@ -12,6 +12,7 @@ #include #include +#include #define PANEL_NAME_SIZE (32) @@ -291,7 +292,7 @@ struct exynos_platform_mipi_dsim { */ struct mipi_dsim_master_ops { int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id, - unsigned int data0, unsigned int data1); + const unsigned char *data0, unsigned int data1); int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id, unsigned int data0, unsigned int data1); int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim); @@ -368,8 +369,12 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev); void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd); +void exynos_init_dsim_platform_data(vidinfo_t *vid); /* panel driver init based on mipi dsi interface */ void s6e8ax0_init(void); +#ifdef CONFIG_OF_CONTROL +extern int mipi_power(void); +#endif #endif /* _DSIM_H */ diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 96610b88f4..0fb6461c08 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -8,6 +8,8 @@ #ifndef __ASM_ARCH_MMC_H_ #define __ASM_ARCH_MMC_H_ +#define S5P_MMC_DEV_OFFSET 0x10000 + #define SDHCI_CONTROL2 0x80 #define SDHCI_CONTROL3 0x84 #define SDHCI_CONTROL4 0x8C @@ -51,11 +53,20 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) +#define SDHCI_MAX_HOSTS 4 + int s5p_sdhci_init(u32 regbase, int index, int bus_width); -static inline unsigned int s5p_mmc_init(int index, int bus_width) +static inline int s5p_mmc_init(int index, int bus_width) { - unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + unsigned int base = samsung_get_base_mmc() + + (S5P_MMC_DEV_OFFSET * index); + return s5p_sdhci_init(base, index, bus_width); } + +#ifdef CONFIG_OF_CONTROL +int exynos_mmc_init(const void *blob); +#endif + #endif diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 9952155986..5c1c3d4a93 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -34,6 +34,9 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, + PERIPH_ID_I2C8 = 87, + PERIPH_ID_I2C9, + PERIPH_ID_I2S0 = 98, PERIPH_ID_I2S1 = 99, /* Since following peripherals do @@ -50,8 +53,8 @@ enum periph_id { PERIPH_ID_PWM2, PERIPH_ID_PWM3, PERIPH_ID_PWM4, + PERIPH_ID_I2C10 = 203, - PERIPH_ID_COUNT, PERIPH_ID_NONE = -1, }; diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h index 0b91ef658c..d0ae7575da 100644 --- a/arch/arm/include/asm/arch-exynos/pinmux.h +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -23,6 +23,9 @@ enum { /* Flags for SROM controller */ PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ + + /* Flags for I2C */ + PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */ }; /** diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 3241327016..3f97b31aea 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -16,7 +16,7 @@ struct exynos4_power { unsigned int gnss_rtc_out_ctrl; unsigned char res2[0x1ec]; unsigned int system_power_down_ctrl; - unsigned char res3[0x1]; + unsigned int res3; unsigned int system_power_down_option; unsigned char res4[0x1f4]; unsigned int swreset; @@ -210,6 +210,13 @@ struct exynos4_power { unsigned int gps_alive_option; }; +struct exynos4412_power { + unsigned char res1[0x0704]; + unsigned int usbhost_phy_control; + unsigned int hsic1_phy_control; + unsigned int hsic2_phy_control; +}; + struct exynos5_power { unsigned int om_stat; unsigned char res1[0x18]; @@ -831,8 +838,866 @@ struct exynos5_power { unsigned int cmu_reset_mau_option; unsigned char res163[0x24]; }; + +struct exynos5420_power { + unsigned int om_stat; + unsigned int lpi_mask0; + unsigned int lpi_mask1; + unsigned char res1[0x10]; + unsigned int rtc_clko_sel; + unsigned char res2[0x1e0]; + unsigned int central_seq_configuration; + unsigned int central_seq_status; + unsigned int central_seq_option; + unsigned char res3[0x14]; + unsigned int seq_transition0; + unsigned int seq_transition1; + unsigned int seq_transition2; + unsigned int seq_transition3; + unsigned int seq_transition4; + unsigned int seq_transition5; + unsigned int seq_transition6; + unsigned int seq_transition7; + unsigned int central_seq_coreblk_configuration; + unsigned int central_seq_coreblk_status; + unsigned int central_seq_coreblk_option; + unsigned char res4[0x14]; + unsigned int seq_coreblk_transition0; + unsigned int seq_coreblk_transition1; + unsigned int seq_coreblk_transition2; + unsigned int seq_coreblk_transition3; + unsigned int seq_coreblk_transition4; + unsigned int seq_coreblk_transition5; + unsigned int seq_coreblk_transition6; + unsigned int seq_coreblk_transition7; + unsigned char res5[0x180]; + unsigned int swreset; + unsigned int rst_stat; + unsigned int automatic_wdt_reset_disable; + unsigned int mask_wdt_reset_request; + unsigned int mask_wreset_request; + unsigned char res6[0xec]; + unsigned int reset_sequencer_configuration; + unsigned int reset_sequencer_status; + unsigned int reset_sequencer_option; + unsigned char res7[0xf4]; + unsigned int wakeup_stat; + unsigned int eint_wakeup_mask; + unsigned int wakeup_mask; + unsigned int wakeup_interrupt; + unsigned char res8[0x10]; + unsigned int wakeup_stat_coreblk; + unsigned int eint_wakeup_mask_coreblk; + unsigned int wakeup_mask_coreblk; + unsigned int wakeup_interrupt_coreblk; + unsigned char res9[0xd0]; + unsigned int hdmi_phy_control; + unsigned int usbdev_phy_control; + unsigned int usbdev1_phy_control; + unsigned int usbhost_phy_control; + unsigned char res104[0x4]; + unsigned int mipi_phy0_control; + unsigned int mipi_phy1_control; + unsigned int mipi_phy2_control; + unsigned int adc_phy_control; + unsigned int mtcadc_phy_control; + unsigned int dptx_phy_control; + unsigned char res10[0xd4]; + unsigned int inform0; + unsigned int inform1; + unsigned int inform2; + unsigned int inform3; + unsigned int sysip_dat0; + unsigned int sysip_dat1; + unsigned int sysip_dat2; + unsigned int sysip_dat3; + unsigned char res11[0xe0]; + unsigned int pmu_spare0; + unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */ + unsigned int pmu_spare2; /* Store PHY1_CON4 for read leveling */ + unsigned int pmu_spare3; + unsigned char res12[0x4]; + unsigned int cg_status0; + unsigned int cg_status1; + unsigned int cg_status2; + unsigned int cg_status3; + unsigned int cg_status4; + unsigned char res200[0x58]; + unsigned int irom_data_reg0; + unsigned int irom_data_reg1; + unsigned int irom_data_reg2; + unsigned int irom_data_reg3; + unsigned char res13[0x70]; + unsigned int pmu_debug; + unsigned char res14[0x5fc]; + unsigned int arm_core0_sys_pwr_reg; + unsigned char res500[0xc]; + unsigned int arm_core1_sys_pwr_reg; + unsigned char res501[0xc]; + unsigned int arm_core2_sys_pwr_reg; + unsigned char res502[0xc]; + unsigned int arm_core3_sys_pwr_reg; + unsigned char res503[0xc]; + unsigned int kfc_core0_sys_pwr_reg; + unsigned char res504[0xc]; + unsigned int kfc_core1_sys_pwr_reg; + unsigned char res505[0xc]; + unsigned int kfc_core2_sys_pwr_reg; + unsigned char res506[0xc]; + unsigned int kfc_core3_sys_pwr_reg; + unsigned char res507[0x1c]; + unsigned int isp_arm_sys_pwr_reg; + unsigned char res18[0xc]; + unsigned int arm_common_sys_pwr_reg; + unsigned char res508[0xc]; + unsigned int kfc_common_sys_pwr_reg; + unsigned char res19[0xc]; + unsigned int arm_l2_sys_pwr_reg; + unsigned char res509[0xc]; + unsigned int kfc_l2_sys_pwr_reg; + unsigned char res20[0xc]; + unsigned int cmu_cpu_aclkstop_sys_pwr_reg; + unsigned int cmu_cpu_sclkstop_sys_pwr_reg; + unsigned char res510[0x8]; + unsigned int cmu_kfc_aclkstop_sys_pwr_reg; + unsigned char res511[0xc]; + unsigned int cmu_aclkstop_sys_pwr_reg; + unsigned int cmu_sclkstop_sys_pwr_reg; + unsigned char res21[0x4]; + unsigned int cmu_reset_sys_pwr_reg; + unsigned char res22[0x10]; + unsigned int cmu_aclkstop_coreblk_sys_pwr_reg; + unsigned int cmu_sclkstop_coreblk_sys_pwr_reg; + unsigned char res23[0x4]; + unsigned int cmu_reset_coreblk_sys_pwr_reg; + unsigned int dram_freq_down_sys_pwr_reg; + unsigned int ddrphy_dlloff_sys_pwr_reg; + unsigned int ddrphy_dlllock_sys_pwr_reg; + unsigned char res25[0x4]; + unsigned int apll_sysclk_sys_pwr_reg; + unsigned int mpll_sysclk_sys_pwr_reg; + unsigned int vpll_sysclk_sys_pwr_reg; + unsigned int epll_sysclk_sys_pwr_reg; + unsigned int bpll_sysclk_sys_pwr_reg; + unsigned int cpll_sysclk_sys_pwr_reg; + unsigned int dpll_sysclk_sys_pwr_reg; + unsigned int ipll_sysclk_sys_pwr_reg; + unsigned int kpll_sysclk_sys_pwr_reg; + unsigned int mplluser_sysclk_sys_pwr_reg; + unsigned char res512[0x8]; + unsigned int bplluser_sysclk_sys_pwr_reg; + unsigned int rpll_sysclk_sys_pwr_reg; + unsigned int spll_sysclk_sys_pwr_reg; + unsigned char res26[0x4]; + unsigned int top_bus_sys_pwr_reg; + unsigned int top_retention_sys_pwr_reg; + unsigned int top_pwr_sys_pwr_reg; + unsigned char res29[0x4]; + unsigned int top_bus_coreblk_sys_pwr_reg; + unsigned int top_retention_coreblk_sys_pwr_reg; + unsigned int top_pwr_coreblk_sys_pwr_reg; + unsigned char res30[0x4]; + unsigned int logic_reset_sys_pwr_reg; + unsigned int oscclk_gate_sys_pwr_reg; + unsigned char res31[0x8]; + unsigned int logic_reset_coreblk_sys_pwr_reg; + unsigned int oscclk_gate_coreblk_sys_pwr_reg; + unsigned int intram_mem_sys_pwr_reg; + unsigned int introm_mem_sys_pwr_reg; + unsigned char res32[0x44]; + unsigned int pad_retention_mau_sys_pwr_reg; + unsigned int pad_retention_jtag_sys_pwr_reg; + unsigned char res36[0x4]; + unsigned int pad_retention_dram_sys_pwr_reg; + unsigned int pad_retention_uart_sys_pwr_reg; + unsigned int pad_retention_mmca_sys_pwr_reg; + unsigned int pad_retention_mmcb_sys_pwr_reg; + unsigned int pad_retention_mmcc_sys_pwr_reg; + unsigned int pad_retention_hsi_sys_pwr_reg; + unsigned int pad_retention_ebia_sys_pwr_reg; + unsigned int pad_retention_ebib_sys_pwr_reg; + unsigned int pad_retention_spi_sys_pwr_reg; + unsigned int pad_retention_dram_coreblk_sys_pwr_reg; + unsigned char res28[0x8]; + unsigned int pad_isolation_sys_pwr_reg; + unsigned char res37[0xc]; + unsigned int pad_isolation_coreblk_sys_pwr_reg; + unsigned char res38[0xc]; + unsigned int pad_alv_sel_sys_pwr_reg; + unsigned char res39[0x1c]; + unsigned int xusbxti_sys_pwr_reg; + unsigned int xxti_sys_pwr_reg; + unsigned char res40[0x38]; + unsigned int ext_regulator_sys_pwr_reg; + unsigned char res41[0x3c]; + unsigned int gpio_mode_sys_pwr_reg; + unsigned char res42[0x1c]; + unsigned int gpio_mode_coreblk_sys_pwr_reg; + unsigned char res43[0x1c]; + unsigned int gpio_mode_mau_sys_pwr_reg; + unsigned int top_asb_reset_sys_pwr_reg; + unsigned int top_asb_isolation_sys_pwr_reg; + unsigned char res44[0xb4]; + unsigned int gscl_sys_pwr_reg; + unsigned int isp_sys_pwr_reg; + unsigned int mfc_sys_pwr_reg; + unsigned int g3d_sys_pwr_reg; + unsigned int disp1_sys_pwr_reg; + unsigned int mau_sys_pwr_reg; + unsigned int g2d_sys_pwr_reg; + unsigned int msc_sys_pwr_reg; + unsigned int fsys_sys_pwr_reg; + unsigned int fsys2_sys_pwr_reg; + unsigned int psgen_sys_pwr_reg; + unsigned int peric_sys_pwr_reg; + unsigned int wcore_sys_pwr_reg; + unsigned char res46[0x4c]; + unsigned int cmu_clkstop_gscl_sys_pwr_reg; + unsigned int cmu_clkstop_isp_sys_pwr_reg; + unsigned int cmu_clkstop_mfc_sys_pwr_reg; + unsigned int cmu_clkstop_g3d_sys_pwr_reg; + unsigned int cmu_clkstop_disp1_sys_pwr_reg; + unsigned int cmu_clkstop_mau_sys_pwr_reg; + unsigned int cmu_clkstop_g2d_sys_pwr_reg; + unsigned int cmu_clkstop_msc_sys_pwr_reg; + unsigned int cmu_clkstop_fsys_sys_pwr_reg; + unsigned int cmu_clkstop_fsys2_sys_pwr_reg; + unsigned int cmu_clkstop_psgen_sys_pwr_reg; + unsigned int cmu_clkstop_peric_sys_pwr_reg; + unsigned int cmu_clkstop_wcore_sys_pwr_reg; + unsigned char res48[0x8]; + unsigned int cmu_sysclk_toppwr_sys_pwr_reg; + unsigned int cmu_sysclk_gscl_sys_pwr_reg; + unsigned int cmu_sysclk_isp_sys_pwr_reg; + unsigned int cmu_sysclk_mfc_sys_pwr_reg; + unsigned int cmu_sysclk_g3d_sys_pwr_reg; + unsigned int cmu_sysclk_disp1_sys_pwr_reg; + unsigned int cmu_sysclk_mau_sys_pwr_reg; + unsigned int cmu_sysclk_g2d_sys_pwr_reg; + unsigned int cmu_sysclk_msc_sys_pwr_reg; + unsigned int cmu_sysclk_fsys_sys_pwr_reg; + unsigned int cmu_sysclk_fsys2_sys_pwr_reg; + unsigned int cmu_sysclk_psgen_sys_pwr_reg; + unsigned int cmu_sysclk_peric_sys_pwr_reg; + unsigned int cmu_sysclk_wcore_sys_pwr_reg; + unsigned int cmu_sysclk_coreblk_toppwr_sys_pwr_reg; + unsigned char res50[0x78]; + unsigned int cmu_reset_fsys2_sys_pwr_reg; + unsigned int cmu_reset_psgen_sys_pwr_reg; + unsigned int cmu_reset_peric_sys_pwr_reg; + unsigned int cmu_reset_wcore_sys_pwr_reg; + unsigned int cmu_reset_gscl_sys_pwr_reg; + unsigned int cmu_reset_isp_sys_pwr_reg; + unsigned int cmu_reset_mfc_sys_pwr_reg; + unsigned int cmu_reset_g3d_sys_pwr_reg; + unsigned int cmu_reset_disp1_sys_pwr_reg; + unsigned int cmu_reset_mau_sys_pwr_reg; + unsigned int cmu_reset_g2d_sys_pwr_reg; + unsigned int cmu_reset_msc_sys_pwr_reg; + unsigned int cmu_reset_fsys_sys_pwr_reg; + unsigned char res52[0xa5c]; + unsigned int arm_core0_configuration; + unsigned int arm_core0_status; + unsigned int arm_core0_option; + unsigned char res53[0x14]; + unsigned int dis_irq_arm_core0_local_configuration; + unsigned int dis_irq_arm_core0_local_status; + unsigned int dis_irq_arm_core0_local_option; + unsigned char res54[0x14]; + unsigned int dis_irq_arm_core0_central_configuration; + unsigned int dis_irq_arm_core0_central_status; + unsigned int dis_irq_arm_core0_central_option; + unsigned char res55[0x34]; + unsigned int arm_core1_configuration; + unsigned int arm_core1_status; + unsigned int arm_core1_option; + unsigned char res56[0x14]; + unsigned int dis_irq_arm_core1_local_configuration; + unsigned int dis_irq_arm_core1_local_status; + unsigned int dis_irq_arm_core1_local_option; + unsigned char res57[0x14]; + unsigned int dis_irq_arm_core1_central_configuration; + unsigned int dis_irq_arm_core1_central_status; + unsigned int dis_irq_arm_core1_central_option; + unsigned char res600[0x34]; + unsigned int arm_core2_configuration; + unsigned int arm_core2_status; + unsigned int arm_core2_option; + unsigned char res601[0x14]; + unsigned int dis_irq_arm_core2_local_configuration; + unsigned int dis_irq_arm_core2_local_status; + unsigned int dis_irq_arm_core2_local_option; + unsigned char res602[0x14]; + unsigned int dis_irq_arm_core2_central_configuration; + unsigned int dis_irq_arm_core2_central_status; + unsigned int dis_irq_arm_core2_central_option; + unsigned char res603[0x34]; + unsigned int arm_core3_configuration; + unsigned int arm_core3_status; + unsigned int arm_core3_option; + unsigned char res900[0x14]; + unsigned int dis_irq_arm_core3_local_configuration; + unsigned int dis_irq_arm_core3_local_status; + unsigned int dis_irq_arm_core3_local_option; + unsigned char res901[0x14]; + unsigned int dis_irq_arm_core3_central_configuration; + unsigned int dis_irq_arm_core3_central_status; + unsigned int dis_irq_arm_core3_central_option; + unsigned char res604[0x34]; + unsigned int kfc_core0_configuration; + unsigned int kfc_core0_status; + unsigned int kfc_core0_option; + unsigned char res605[0x14]; + unsigned int dis_irq_kfc_core0_local_configuration; + unsigned int dis_irq_kfc_core0_local_status; + unsigned int dis_irq_kfc_core0_local_option; + unsigned char res606[0x14]; + unsigned int dis_irq_kfc_core0_central_configuration; + unsigned int dis_irq_kfc_core0_central_status; + unsigned int dis_irq_kfc_core0_central_option; + unsigned char res607[0x34]; + unsigned int kfc_core1_configuration; + unsigned int kfc_core1_status; + unsigned int kfc_core1_option; + unsigned char res608[0x14]; + unsigned int dis_irq_kfc_core1_local_configuration; + unsigned int dis_irq_kfc_core1_local_status; + unsigned int dis_irq_kfc_core1_local_option; + unsigned char res609[0x14]; + unsigned int dis_irq_kfc_core1_central_configuration; + unsigned int dis_irq_kfc_core1_central_status; + unsigned int dis_irq_kfc_core1_central_option; + unsigned char res610[0x34]; + unsigned int kfc_core2_configuration; + unsigned int kfc_core2_status; + unsigned int kfc_core2_option; + unsigned char res611[0x14]; + unsigned int dis_irq_kfc_core2_local_configuration; + unsigned int dis_irq_kfc_core2_local_status; + unsigned int dis_irq_kfc_core2_local_option; + unsigned char res612[0x14]; + unsigned int dis_irq_kfc_core2_central_configuration; + unsigned int dis_irq_kfc_core2_central_status; + unsigned int dis_irq_kfc_core2_central_option; + unsigned char res613[0x34]; + unsigned int kfc_core3_configuration; + unsigned int kfc_core3_status; + unsigned int kfc_core3_option; + unsigned char res614[0x14]; + unsigned int dis_irq_kfc_core3_local_configuration; + unsigned int dis_irq_kfc_core3_local_status; + unsigned int dis_irq_kfc_core3_local_option; + unsigned char res615[0x14]; + unsigned int dis_irq_kfc_core3_central_configuration; + unsigned int dis_irq_kfc_core3_central_status; + unsigned int dis_irq_kfc_core3_central_option; + unsigned char res61[0xb4]; + unsigned int isp_arm_configuration; + unsigned int isp_arm_status; + unsigned int isp_arm_option; + unsigned char res62[0x14]; + unsigned int dis_irq_isp_arm_local_configuration; + unsigned int dis_irq_isp_arm_local_status; + unsigned int dis_irq_isp_arm_local_option; + unsigned char res63[0x14]; + unsigned int dis_irq_isp_arm_central_configuration; + unsigned int dis_irq_isp_arm_central_status; + unsigned int dis_irq_isp_arm_central_option; + unsigned char res64[0x34]; + unsigned int arm_common_configuration; + unsigned int arm_common_status; + unsigned int arm_common_option; + unsigned char res616[0x74]; + unsigned int kfc_common_configuration; + unsigned int kfc_common_status; + unsigned int kfc_common_option; + unsigned char res65[0x74]; + unsigned int arm_l2_configuration; + unsigned int arm_l2_status; + unsigned int arm_l2_option; + unsigned char res617[0x74]; + unsigned int kfc_l2_configuration; + unsigned int kfc_l2_status; + unsigned int kfc_l2_option; + unsigned char res66[0x74]; + unsigned int cmu_cpu_aclkstop_configuration; + unsigned int cmu_cpu_aclkstop_status; + unsigned int cmu_cpu_aclkstop_option; + unsigned char res67[0x14]; + unsigned int cmu_cpu_sclkstop_configuration; + unsigned int cmu_cpu_sclkstop_status; + unsigned int cmu_cpu_sclkstop_option; + unsigned char res618[0x4]; + unsigned int cmu_kfc_aclkstop_configuration; + unsigned int cmu_kfc_aclkstop_status; + unsigned int cmu_kfc_aclkstop_option; + unsigned char res619[0xc4]; + unsigned int cmu_aclkstop_configuration; + unsigned int cmu_aclkstop_status; + unsigned int cmu_aclkstop_option; + unsigned char res620[0x14]; + unsigned int cmu_sclkstop_configuration; + unsigned int cmu_sclkstop_status; + unsigned int cmu_sclkstop_option; + unsigned char res68[0x34]; + unsigned int cmu_reset_configuration; + unsigned int cmu_reset_status; + unsigned int cmu_reset_option; + unsigned char res69[0x94]; + unsigned int cmu_aclkstop_coreblk_configuration; + unsigned int cmu_aclkstop_coreblk_status; + unsigned int cmu_aclkstop_coreblk_option; + unsigned char res70[0x14]; + unsigned int cmu_sclkstop_coreblk_configuration; + unsigned int cmu_sclkstop_coreblk_status; + unsigned int cmu_sclkstop_coreblk_option; + unsigned char res71[0x34]; + unsigned int cmu_reset_coreblk_configuration; + unsigned int cmu_reset_coreblk_status; + unsigned int cmu_reset_coreblk_option; + unsigned char res621[0x14]; + unsigned int dram_freq_down_configuration; + unsigned int dram_freq_down_status; + unsigned int dram_freq_down_option; + unsigned char res622[0x14]; + unsigned int ddrphy_dlloff_configuration; + unsigned int ddrphy_dlloff_status; + unsigned int ddrphy_dlloff_option; + unsigned char res72[0x14]; + unsigned int ddrphy_dlllock_configuration; + unsigned int ddrphy_dlllock_status; + unsigned int ddrphy_dlllock_option; + unsigned char res73[0x34]; + unsigned int apll_sysclk_configuration; + unsigned int apll_sysclk_status; + unsigned int apll_sysclk_option; + unsigned char res74[0x18]; + unsigned int mpll_sysclk_status; + unsigned int mpll_sysclk_option; + unsigned char res75[0x14]; + unsigned int vpll_sysclk_configuration; + unsigned int vpll_sysclk_status; + unsigned int vpll_sysclk_option; + unsigned char res76[0x14]; + unsigned int epll_sysclk_configuration; + unsigned int epll_sysclk_status; + unsigned int epll_sysclk_option; + unsigned char res77[0x14]; + unsigned int bpll_sysclk_configuration; + unsigned int bpll_sysclk_status; + unsigned int bpll_sysclk_option; + unsigned char res78[0x14]; + unsigned int cpll_sysclk_configuration; + unsigned int cpll_sysclk_status; + unsigned int cpll_sysclk_option; + unsigned char res79[0x14]; + unsigned int dpll_sysclk_configuration; + unsigned int dpll_sysclk_status; + unsigned int dpll_sysclk_option; + unsigned char res700[0x14]; + unsigned int ipll_sysclk_configuration; + unsigned int ipll_sysclk_status; + unsigned int ipll_sysclk_option; + unsigned char res903[0x14]; + unsigned int kpll_sysclk_configuration; + unsigned int kpll_sysclk_status; + unsigned int kpll_sysclk_option; + unsigned char res80[0x14]; + unsigned int mplluser_sysclk_configuration; + unsigned int mplluser_sysclk_status; + unsigned int mplluser_sysclk_option; + unsigned char res81[0x54]; + unsigned int bplluser_sysclk_configuration; + unsigned int bplluser_sysclk_status; + unsigned int bplluser_sysclk_option; + unsigned char res701[0x14]; + unsigned int rplluser_sysclk_configuration; + unsigned int rplluser_sysclk_status; + unsigned int rplluser_sysclk_option; + unsigned char res702[0x14]; + unsigned int splluser_sysclk_configuration; + unsigned int splluser_sysclk_status; + unsigned int splluser_sysclk_option; + unsigned char res82[0x34]; + unsigned int top_bus_configuration; + unsigned int top_bus_status; + unsigned int top_bus_option; + unsigned char res83[0x14]; + unsigned int top_retention_configuration; + unsigned int top_retention_status; + unsigned int top_retention_option; + unsigned char res84[0x14]; + unsigned int top_pwr_configuration; + unsigned int top_pwr_status; + unsigned int top_pwr_option; + unsigned char res85[0x34]; + unsigned int top_bus_coreblk_configuration; + unsigned int top_bus_coreblk_status; + unsigned int top_bus_coreblk_option; + unsigned char res86[0x14]; + unsigned int top_retention_coreblk_configuration; + unsigned int top_retention_coreblk_status; + unsigned int top_retention_coreblk_option; + unsigned char res87[0x14]; + unsigned int top_pwr_coreblk_configuration; + unsigned int top_pwr_coreblk_status; + unsigned int top_pwr_coreblk_option; + unsigned char res88[0x34]; + unsigned int logic_reset_configuration; + unsigned int logic_reset_status; + unsigned int logic_reset_option; + unsigned char res89[0x14]; + unsigned int oscclk_gate_configuration; + unsigned int oscclk_gate_status; + unsigned int oscclk_gate_option; + unsigned char res90[0x54]; + unsigned int logic_reset_coreblk_configuration; + unsigned int logic_reset_coreblk_status; + unsigned int logic_reset_coreblk_option; + unsigned char res91[0x14]; + unsigned int oscclk_gate_coreblk_configuration; + unsigned int oscclk_gate_coreblk_status; + unsigned int oscclk_gate_coreblk_option; + unsigned char res99[0x174]; + unsigned int intram_mem_configuration; + unsigned int intram_mem_status; + unsigned int intram_mem_option; + unsigned char res100[0x14]; + unsigned int introm_mem_configuration; + unsigned int introm_mem_status; + unsigned int introm_mem_option; + unsigned char res101[0xb4]; + unsigned int pad_retention_dram_configuration; + unsigned int pad_retention_dram_status; + unsigned int pad_retention_dram_option; + unsigned char res106[0x14]; + unsigned int pad_retention_mau_configuration; + unsigned int pad_retention_mau_status; + unsigned int pad_retention_mau_option; + unsigned char res107[0x14]; + unsigned int pad_retention_jtag_configuration; + unsigned int pad_retention_jtag_status; + unsigned int pad_retention_jtag_option; + unsigned char res92[0x74]; + unsigned int pad_retention_dram_configuration_2; + unsigned int pad_retention_dram_status_2; + unsigned int pad_retention_dram_option_2; + unsigned char res111[0x14]; + unsigned int pad_retention_uart_configuration; + unsigned int pad_retention_uart_status; + unsigned int pad_retention_uart_option; + unsigned char res112[0x14]; + unsigned int pad_retention_mmca_configuration; + unsigned int pad_retention_mmca_status; + unsigned int pad_retention_mmca_option; + unsigned char res113[0x14]; + unsigned int pad_retention_mmcb_configuration; + unsigned int pad_retention_mmcb_status; + unsigned int pad_retention_mmcb_option; + unsigned char res93[0x14]; + unsigned int pad_retention_mmcc_configuration; + unsigned int pad_retention_mmcc_status; + unsigned int pad_retention_mmcc_option; + unsigned char res94[0x14]; + unsigned int pad_retention_hsi_configuration; + unsigned int pad_retention_hsi_status; + unsigned int pad_retention_hsi_option; + unsigned char res114[0x14]; + unsigned int pad_retention_ebia_configuration; + unsigned int pad_retention_ebia_status; + unsigned int pad_retention_ebia_option; + unsigned char res115[0x14]; + unsigned int pad_retention_ebib_configuration; + unsigned int pad_retention_ebib_status; + unsigned int pad_retention_ebib_option; + unsigned char res116[0x14]; + unsigned int pad_retention_spi_configuration; + unsigned int pad_retention_spi_status; + unsigned int pad_retention_spi_option; + unsigned char res117[0x14]; + unsigned int pad_retention_dram_coreblk_configuration; + unsigned int pad_retention_dram_coreblk_status; + unsigned int pad_retention_dram_coreblk_option; + unsigned char res118[0x14]; + unsigned int pad_isolation_configuration; + unsigned int pad_isolation_status; + unsigned int pad_isolation_option; + unsigned char res119[0x74]; + unsigned int pad_isolation_coreblk_configuration; + unsigned int pad_isolation_coreblk_status; + unsigned int pad_isolation_coreblk_option; + unsigned char res120[0x74]; + unsigned int pad_alv_sel_configuration; + unsigned int pad_alv_sel_status; + unsigned int pad_alv_sel_option0; + unsigned int ps_hold_control; + unsigned char res130[0xf0]; + unsigned int xusbxti_configuration; + unsigned int xusbxti_status; + unsigned int xusbxti_option; + unsigned char res910[0x10]; + unsigned int xusbxti_duration3; + unsigned int xxti_configuration; + unsigned int xxti_status; + unsigned int xxti_option; + unsigned char res131[0x10]; + unsigned int xxti_duration3; + unsigned char res132[0x1c0]; + unsigned int ext_regulator_configuration; + unsigned int ext_regulator_status; + unsigned int ext_regulator_option; + unsigned char res133[0x10]; + unsigned int ext_regulator_duration3; + unsigned char res134[0x1e0]; + unsigned int gpio_mode_configuration; + unsigned int gpio_mode_status; + unsigned int gpio_mode_option; + unsigned char res135[0xf4]; + unsigned int gpio_mode_coreblk_configuration; + unsigned int gpio_mode_coreblk_status; + unsigned int gpio_mode_coreblk_option; + unsigned char res136[0xd4]; + unsigned int gpio_mode_mau_configuration; + unsigned int gpio_mode_mau_status; + unsigned int gpio_mode_mau_option; + unsigned char res137[0x14]; + unsigned int top_asb_reset_configuration; + unsigned int top_asb_reset_status; + unsigned int top_asb_reset_option; + unsigned char res138[0x14]; + unsigned int top_asb_isolation_configuration; + unsigned int top_asb_isolation_status; + unsigned int top_asb_isolation_option; + unsigned char res139[0x5d4]; + unsigned int gscl_configuration; + unsigned int gscl_status; + unsigned int gscl_option; + unsigned char res140[0x14]; + unsigned int isp_configuration; + unsigned int isp_status; + unsigned int isp_option; + unsigned char res141[0x34]; + unsigned int mfc_configuration; + unsigned int mfc_status; + unsigned int mfc_option; + unsigned char res142[0x14]; + unsigned int g3d_configuration; + unsigned int g3d_status; + unsigned int g3d_option; + unsigned char res143[0x34]; + unsigned int disp1_configuration; + unsigned int disp1_status; + unsigned int disp1_option; + unsigned char res144[0x14]; + unsigned int mau_configuration; + unsigned int mau_status; + unsigned int mau_option; + unsigned char res800[0x14]; + unsigned int g2d_configuration; + unsigned int g2d_status; + unsigned int g2d_option; + unsigned char res801[0x14]; + unsigned int msc_configuration; + unsigned int msc_status; + unsigned int msc_option; + unsigned char res802[0x14]; + unsigned int fsys_configuration; + unsigned int fsys_status; + unsigned int fsys_option; + unsigned char res803[0x14]; + unsigned int fsys2_configuration; + unsigned int fsys2_status; + unsigned int fsys2_option; + unsigned char res804[0x14]; + unsigned int psgen_configuration; + unsigned int psgen_status; + unsigned int psgen_option; + unsigned char res805[0x14]; + unsigned int peric_configuration; + unsigned int peric_status; + unsigned int peric_option; + unsigned char res806[0x14]; + unsigned int wcore_configuration; + unsigned int wcore_status; + unsigned int wcore_option; + unsigned char res145[0x234]; + unsigned int cmu_clkstop_gscl_configuration; + unsigned int cmu_clkstop_gscl_status; + unsigned int cmu_clkstop_gscl_option; + unsigned char res146[0x14]; + unsigned int cmu_clkstop_isp_configuration; + unsigned int cmu_clkstop_isp_status; + unsigned int cmu_clkstop_isp_option; + unsigned char res147[0x34]; + unsigned int cmu_clkstop_mfc_configuration; + unsigned int cmu_clkstop_mfc_status; + unsigned int cmu_clkstop_mfc_option; + unsigned char res148[0x14]; + unsigned int cmu_clkstop_g3d_configuration; + unsigned int cmu_clkstop_g3d_status; + unsigned int cmu_clkstop_g3d_option; + unsigned char res149[0x34]; + unsigned int cmu_clkstop_disp1_configuration; + unsigned int cmu_clkstop_disp1_status; + unsigned int cmu_clkstop_disp1_option; + unsigned char res150[0x14]; + unsigned int cmu_clkstop_mau_configuration; + unsigned int cmu_clkstop_mau_status; + unsigned int cmu_clkstop_mau_option; + unsigned char res807[0x14]; + unsigned int cmu_clkstop_g2d_configuration; + unsigned int cmu_clkstop_g2d_status; + unsigned int cmu_clkstop_g2d_option; + unsigned char res808[0x14]; + unsigned int cmu_clkstop_msc_configuration; + unsigned int cmu_clkstop_msc_status; + unsigned int cmu_clkstop_msc_option; + unsigned char res809[0x14]; + unsigned int cmu_clkstop_fsys_configuration; + unsigned int cmu_clkstop_fsys_status; + unsigned int cmu_clkstop_fsys_option; + unsigned char res810[0x14]; + unsigned int cmu_clkstop_fsys2_configuration; + unsigned int cmu_clkstop_fsys2_status; + unsigned int cmu_clkstop_fsys2_option; + unsigned char res811[0x14]; + unsigned int cmu_clkstop_psgen_configuration; + unsigned int cmu_clkstop_psgen_status; + unsigned int cmu_clkstop_psgen_option; + unsigned char res812[0x14]; + unsigned int cmu_clkstop_peric_configuration; + unsigned int cmu_clkstop_peric_status; + unsigned int cmu_clkstop_peric_option; + unsigned char res813[0x14]; + unsigned int cmu_clkstop_wcore_configuration; + unsigned int cmu_clkstop_wcore_status; + unsigned int cmu_clkstop_wcore_option; + unsigned char res151[0x14]; + unsigned int cmu_sysclk_toppwr_configuration; + unsigned int cmu_sysclk_toppwr_status; + unsigned int cmu_sysclk_toppwr_option; + unsigned char res920[0x18]; + unsigned int cmu_sysclk_gscl_status; + unsigned int cmu_sysclk_gscl_option; + unsigned char res152[0x18]; + unsigned int cmu_sysclk_isp_status; + unsigned int cmu_sysclk_isp_option; + unsigned char res153[0x38]; + unsigned int cmu_sysclk_mfc_status; + unsigned int cmu_sysclk_mfc_option; + unsigned char res154[0x18]; + unsigned int cmu_sysclk_g3d_status; + unsigned int cmu_sysclk_g3d_option; + unsigned char res155[0x38]; + unsigned int cmu_sysclk_disp1_status; + unsigned int cmu_sysclk_disp1_option; + unsigned char res156[0x18]; + unsigned int cmu_sysclk_mau_status; + unsigned int cmu_sysclk_mau_option; + unsigned char res814[0x18]; + unsigned int cmu_sysclk_g2d_status; + unsigned int cmu_sysclk_g2d_option; + unsigned char res815[0x18]; + unsigned int cmu_sysclk_msc_status; + unsigned int cmu_sysclk_msc_option; + unsigned char res922[0x18]; + unsigned int cmu_sysclk_fsys_status; + unsigned int cmu_sysclk_fsys_option; + unsigned char res816[0x18]; + unsigned int cmu_sysclk_fsys2_status; + unsigned int cmu_sysclk_fsys2_option; + unsigned char res817[0x18]; + unsigned int cmu_sysclk_psgen_status; + unsigned int cmu_sysclk_psgen_option; + unsigned char res950[0x18]; + unsigned int cmu_sysclk_peric_status; + unsigned int cmu_sysclk_peric_option; + unsigned char res818[0x18]; + unsigned int cmu_sysclk_wcore_status; + unsigned int cmu_sysclk_wcore_option; + unsigned char res819[0x18]; + unsigned int cmu_sysclk_coreblk_toppwr_status; + unsigned int cmu_sysclk_coreblk_toppwr_option; + unsigned char res157[0x414]; + unsigned int cmu_reset_gscl_configuration; + unsigned int cmu_reset_gscl_status; + unsigned int cmu_reset_gscl_option; + unsigned char res158[0x14]; + unsigned int cmu_reset_isp_configuration; + unsigned int cmu_reset_isp_status; + unsigned int cmu_reset_isp_option; + unsigned char res159[0x34]; + unsigned int cmu_reset_mfc_configuration; + unsigned int cmu_reset_mfc_status; + unsigned int cmu_reset_mfc_option; + unsigned char res160[0x14]; + unsigned int cmu_reset_g3d_configuration; + unsigned int cmu_reset_g3d_status; + unsigned int cmu_reset_g3d_option; + unsigned char res161[0x34]; + unsigned int cmu_reset_disp1_configuration; + unsigned int cmu_reset_disp1_status; + unsigned int cmu_reset_disp1_option; + unsigned char res162[0x14]; + unsigned int cmu_reset_mau_configuration; + unsigned int cmu_reset_mau_status; + unsigned int cmu_reset_mau_option; + unsigned char res163[0x14]; + unsigned int version_info; + unsigned int i2s_bypass; + unsigned int kfc_swreset_mask_from_eagle; + unsigned char res164[0xf4]; + unsigned int cmu_reset_g2d_configuration; + unsigned int cmu_reset_g2d_status; + unsigned int cmu_reset_g2d_option; + unsigned char res165[0x14]; + unsigned int cmu_reset_msc_configuration; + unsigned int cmu_reset_msc_status; + unsigned int cmu_reset_msc_option; + unsigned char res166[0x14]; + unsigned int cmu_reset_fsys_configuration; + unsigned int cmu_reset_fsys_status; + unsigned int cmu_reset_fsys_option; + unsigned char res167[0x14]; + unsigned int cmu_reset_fsys2_configuration; + unsigned int cmu_reset_fsys2_status; + unsigned int cmu_reset_fsys2_option; + unsigned char res168[0x14]; + unsigned int cmu_reset_psgen_configuration; + unsigned int cmu_reset_psgen_status; + unsigned int cmu_reset_psgen_option; + unsigned char res169[0x14]; + unsigned int cmu_reset_peric_configuration; + unsigned int cmu_reset_peric_status; + unsigned int cmu_reset_peric_option; + unsigned char res170[0x14]; + unsigned int cmu_reset_wcore_configuration; + unsigned int cmu_reset_wcore_status; + unsigned int cmu_reset_wcore_option; +}; #endif /* __ASSEMBLY__ */ +#define OM_PIN_BITS 0x1f +#define OM_PIN_SHIFT 0x1 +#define OM_PIN_MASK (OM_PIN_BITS << OM_PIN_SHIFT) + +enum { + /* + * Assign the OM pin values for respective boot modes. + * Exynos4 does not support spi boot and the mmc boot OM + * pin values are the same across Exynos4 and Exynos5. + */ + BOOT_MODE_SD = 4, /* SD_CH2 | USB */ + BOOT_MODE_EMMC = 8, /* EMMC4.4 | USB */ + BOOT_MODE_EMMC_SD = 40, /* EMMC4.4 | SD_CH2 */ + BOOT_MODE_SERIAL = 20, + /* Boot based on Operating Mode pin settings */ + BOOT_MODE_OM = 32, + BOOT_MODE_USB, /* Boot using USB download */ +}; + +unsigned int get_boot_mode(void); + void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); #define EXYNOS_MIPI_PHY_ENABLE (1 << 0) @@ -847,6 +1712,11 @@ void set_hw_thermal_trip(void); #define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) #define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) +void set_usbdrd_phy_ctrl(unsigned int enable); + +#define POWER_USB_DRD_PHY_CTRL_EN (1 << 0) +#define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0) + void set_dp_phy_ctrl(unsigned int enable); #define EXYNOS_DP_PHY_ENABLE (1 << 0) @@ -884,4 +1754,5 @@ uint32_t get_reset_status(void); /* Read the resume function and call it */ void power_exit_wakeup(void); + #endif diff --git a/arch/arm/include/asm/arch-exynos/pwm_backlight.h b/arch/arm/include/asm/arch-exynos/pwm_backlight.h index 2dd7be8d3b..4f54fa737d 100644 --- a/arch/arm/include/asm/arch-exynos/pwm_backlight.h +++ b/arch/arm/include/asm/arch-exynos/pwm_backlight.h @@ -3,7 +3,7 @@ * * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PWM_BACKLIGHT_H_ diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h index fb23aa69c2..0ba931b7e3 100644 --- a/arch/arm/include/asm/arch-exynos/spi.h +++ b/arch/arm/include/asm/arch-exynos/spi.h @@ -22,7 +22,7 @@ struct exynos_spi { unsigned int rx_data; /* 0x1c */ unsigned int pkt_cnt; /* 0x20 */ unsigned char reserved2[4]; - unsigned char reserved3[4]; + unsigned int swap_cfg; /* 0x28 */ unsigned int fb_clk; /* 0x2c */ unsigned char padding[0xffd0]; }; @@ -30,6 +30,7 @@ struct exynos_spi { #define EXYNOS_SPI_MAX_FREQ 50000000 #define SPI_TIMEOUT_MS 10 +#define SF_READ_DATA_CMD 0x3 /* SPI_CHCFG */ #define SPI_CH_HS_EN (1 << 6) @@ -62,5 +63,14 @@ struct exynos_spi { /* Packet Count */ #define SPI_PACKET_CNT_EN (1 << 16) +/* Swap config */ +#define SPI_TX_SWAP_EN (1 << 0) +#define SPI_TX_BYTE_SWAP (1 << 2) +#define SPI_TX_HWORD_SWAP (1 << 3) +#define SPI_TX_BYTE_SWAP (1 << 2) +#define SPI_RX_SWAP_EN (1 << 4) +#define SPI_RX_BYTE_SWAP (1 << 6) +#define SPI_RX_HWORD_SWAP (1 << 7) + #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/arch-exynos/spl.h b/arch/arm/include/asm/arch-exynos/spl.h index b1d68c3d21..cdcb2bc7ad 100644 --- a/arch/arm/include/asm/arch-exynos/spl.h +++ b/arch/arm/include/asm/arch-exynos/spl.h @@ -8,20 +8,7 @@ #define __ASM_ARCH_EXYNOS_SPL_H__ #include - -enum boot_mode { - /* - * Assign the OM pin values for respective boot modes. - * Exynos4 does not support spi boot and the mmc boot OM - * pin values are the same across Exynos4 and Exynos5. - */ - BOOT_MODE_MMC = 4, - BOOT_MODE_EMMC = 8, /* EMMC4.4 */ - BOOT_MODE_SERIAL = 20, - /* Boot based on Operating Mode pin settings */ - BOOT_MODE_OM = 32, - BOOT_MODE_USB, /* Boot using USB download */ -}; +#include #ifndef __ASSEMBLY__ /* Parameters of early board initialization in SPL */ @@ -62,7 +49,7 @@ struct spl_machine_param { * table only for mmc boot. */ u32 uboot_size; - enum boot_mode boot_source; /* Boot device */ + unsigned boot_source; /* Boot device */ unsigned frequency_mhz; /* Frequency of memory in MHz */ unsigned arm_freq_mhz; /* ARM Frequency in MHz */ u32 serial_base; /* Serial base address */ diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index d13af94495..518cc8182b 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -39,5 +39,6 @@ struct exynos5_sysreg { void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); +int exynos_lcd_early_init(const void *blob); #endif /* _EXYNOS4_SYSTEM_H */ diff --git a/arch/arm/include/asm/arch-exynos/xhci-exynos.h b/arch/arm/include/asm/arch-exynos/xhci-exynos.h new file mode 100644 index 0000000000..92b90a462c --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/xhci-exynos.h @@ -0,0 +1,88 @@ +/* Copyright (c) 2012 Samsung Electronics Co. Ltd + * + * Exynos Phy register definitions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_XHCI_EXYNOS_H_ +#define _ASM_ARCH_XHCI_EXYNOS_H_ + +/* Phy register MACRO definitions */ + +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) + +#define PHYUTMI_OTGDISABLE (1 << 6) +#define PHYUTMI_FORCESUSPEND (1 << 1) +#define PHYUTMI_FORCESLEEP (1 << 0) + +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) +#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) + +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) +#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) + +#define PHYCLKRST_SSC_EN (0x1 << 20) +#define PHYCLKRST_REF_SSP_EN (0x1 << 19) +#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) + +#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) + +#define PHYCLKRST_FSEL_MASK (0x3f << 5) +#define PHYCLKRST_FSEL(_x) ((_x) << 5) +#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) +#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) +#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) +#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) + +#define PHYCLKRST_RETENABLEN (0x1 << 4) + +#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) + +#define PHYCLKRST_PORTRESET (0x1 << 1) +#define PHYCLKRST_COMMONONN (0x1 << 0) + +#define PHYPARAM0_REF_USE_PAD (0x1 << 31) +#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) +#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) + +#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) +#define PHYPARAM1_PCS_TXDEEMPH (0x1c) + +#define PHYTEST_POWERDOWN_SSP (0x1 << 3) +#define PHYTEST_POWERDOWN_HSP (0x1 << 2) + +#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) + +#define FSEL_CLKSEL_24M (0x5) + +/* XHCI PHY register structure */ +struct exynos_usb3_phy { + unsigned int reserve1; + unsigned int link_system; + unsigned int phy_utmi; + unsigned int phy_pipe; + unsigned int phy_clk_rst; + unsigned int phy_reg0; + unsigned int phy_reg1; + unsigned int phy_param0; + unsigned int phy_param1; + unsigned int phy_term; + unsigned int phy_test; + unsigned int phy_adp; + unsigned int phy_batchg; + unsigned int phy_resume; + unsigned int reserve2[3]; + unsigned int link_port; +}; + +#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-lsch3/clock.h new file mode 100644 index 0000000000..831af0bda3 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/clock.h @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_ +#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_ + +#include + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_BUS_CLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_I2C_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h new file mode 100644 index 0000000000..da551e8839 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -0,0 +1,71 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ +#define _ASM_ARMV8_FSL_LSCH3_CONFIG_ + +#include +#define CONFIG_MP +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) +#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) +#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) +#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 +#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ + 0x18A0) + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06100000 + +/* SMMU Defintions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* DDR */ +#define CONFIG_SYS_FSL_DDR_LE +#define CONFIG_VERY_BIG_RAM +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#else +#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ +#endif +#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ +#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 + + +/* IFC */ +#define CONFIG_SYS_FSL_IFC_LE + +#ifdef CONFIG_LS2085A +#define CONFIG_MAX_CPUS 16 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#else +#error SoC not defined +#endif + +#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h new file mode 100644 index 0000000000..f23a78c62d --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h @@ -0,0 +1,9 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_ +#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_ +#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h new file mode 100644 index 0000000000..ee1d6512d9 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -0,0 +1,151 @@ +/* + * LayerScape Internal Memory Map + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_FSL_LSCH3_IMMAP_H +#define __ARCH_FSL_LSCH3_IMMAP_H_ + +/* This is chassis generation 3 */ + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; + unsigned long freq_qe; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_QBMAN + unsigned long freq_qman; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freq_pme; +#endif +}; + +/* Global Utilities Block */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; /* General-purpose POR configuration 2 */ + u32 dcfg_fusesr; /* Fuse status register */ + u32 gpporcr3; + u32 gpporcr4; + u8 res_034[0x70-0x34]; + u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u32 devdisr7; /* Device disable control 7 */ + u8 res_08c[0x90-0x8c]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_098[0xa0-0x98]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u32 mvr; /* Manufacturing version */ + u8 res_0ac[0x100-0xac]; + u32 rcwsr[32]; /* Reset control word status */ + +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f + u8 res_180[0x200-0x180]; + u32 scratchrw[32]; /* Scratch Read/Write */ + u8 res_280[0x300-0x280]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 bootlocptrl; /* Boot location pointer low-order addr */ + u32 bootlocptrh; /* Boot location pointer high-order addr */ + u8 res_408[0x500-0x408]; + u8 res_500[0x740-0x500]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[3]; /* Core Cluster n Topology Register */ + u8 res_858[0x1000-0x858]; +}; + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 + +#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 + +struct ccsr_clk_cluster_group { + struct { + u8 res_00[0x10]; + u32 csr; + u8 res_14[0x20-0x14]; + } hwncsr[3]; + u8 res_60[0x80-0x60]; + struct { + u32 gsr; + u8 res_84[0xa0-0x84]; + } pllngsr[3]; + u8 res_e0[0x100-0xe0]; +}; + +struct ccsr_clk_ctrl { + struct { + u32 csr; /* core cluster n clock control status */ + u8 res_04[0x20-0x04]; + } clkcncsr[8]; +}; + +struct ccsr_reset { + u32 rstcr; /* 0x000 */ + u32 rstcrsp; /* 0x004 */ + u8 res_008[0x10-0x08]; /* 0x008 */ + u32 rstrqmr1; /* 0x010 */ + u32 rstrqmr2; /* 0x014 */ + u32 rstrqsr1; /* 0x018 */ + u32 rstrqsr2; /* 0x01c */ + u32 rstrqwdtmrl; /* 0x020 */ + u32 rstrqwdtmru; /* 0x024 */ + u8 res_028[0x30-0x28]; /* 0x028 */ + u32 rstrqwdtsrl; /* 0x030 */ + u32 rstrqwdtsru; /* 0x034 */ + u8 res_038[0x60-0x38]; /* 0x038 */ + u32 brrl; /* 0x060 */ + u32 brru; /* 0x064 */ + u8 res_068[0x80-0x68]; /* 0x068 */ + u32 pirset; /* 0x080 */ + u32 pirclr; /* 0x084 */ + u8 res_088[0x90-0x88]; /* 0x088 */ + u32 brcorenbr; /* 0x090 */ + u8 res_094[0x100-0x94]; /* 0x094 */ + u32 rcw_reqr; /* 0x100 */ + u32 rcw_completion; /* 0x104 */ + u8 res_108[0x110-0x108]; /* 0x108 */ + u32 pbi_reqr; /* 0x110 */ + u32 pbi_completion; /* 0x114 */ + u8 res_118[0xa00-0x118]; /* 0x118 */ + u32 qmbm_warmrst; /* 0xa00 */ + u32 soc_warmrst; /* 0xa04 */ + u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ + u32 ip_rev1; /* 0xbf8 */ + u32 ip_rev2; /* 0xbfc */ +}; +#endif /* __ARCH_FSL_LSCH3_IMMAP_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h new file mode 100644 index 0000000000..8f005353b4 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ +#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h new file mode 100644 index 0000000000..254136e228 --- /dev/null +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SX 0x62 +#define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6D 0x64 +#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ + +#define CS0_128 0 +#define CS0_64M_CS1_64M 1 +#define CS0_64M_CS1_32M_CS2_32M 2 +#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h deleted file mode 100644 index c2e9c82049..0000000000 --- a/arch/arm/include/asm/arch-ixp/ixp425.h +++ /dev/null @@ -1,548 +0,0 @@ -/* - * include/asm-arm/arch-ixp425/ixp425.h - * - * Register definitions for IXP425 - * - * Copyright (C) 2002 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef _ASM_ARM_IXP425_H_ -#define _ASM_ARM_IXP425_H_ - -#define BIT(x) (1<<(x)) - -/* FIXME: Only this does work for u-boot... find out why... [RS] */ -#define UBOOT_REG_FIX 1 -#ifdef UBOOT_REG_FIX -# undef io_p2v -# undef __REG -# ifndef __ASSEMBLY__ -# define io_p2v(PhAdd) (PhAdd) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# endif -#endif /* UBOOT_REG_FIX */ - -/* - * - * IXP425 Memory map: - * - * Phy Phy Size Map Size Virt Description - * ========================================================================= - * - * 0x00000000 0x10000000 SDRAM 1 - * - * 0x10000000 0x10000000 SDRAM 2 - * - * 0x20000000 0x10000000 SDRAM 3 - * - * 0x30000000 0x10000000 SDRAM 4 - * - * The above four are aliases to the same memory location (0x00000000) - * - * 0x48000000 0x4000000 PCI Memory - * - * 0x50000000 0x10000000 Not Mapped EXP BUS - * - * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr - * - * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG - * - * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG - * - * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL - * - * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG - */ - -/* - * SDRAM - */ -#define IXP425_SDRAM_BASE (0x00000000) -#define IXP425_SDRAM_BASE_ALT (0x10000000) - - -/* - * PCI Configuration space - */ -#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000) -#define IXP425_PCI_CFG_REGION_SIZE (0x00001000) - -/* - * Expansion BUS Configuration registers - */ -#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000) -#define IXP425_EXP_CFG_REGION_SIZE (0x00001000) - -/* - * Peripheral space - */ -#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000) -#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000) - -/* - * SDRAM configuration registers - */ -#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000) - -/* - * Q Manager space .. not static mapped - */ -#define IXP425_QMGR_BASE_PHYS (0x60000000) -#define IXP425_QMGR_REGION_SIZE (0x00004000) - -/* - * Expansion BUS - * - * Expansion Bus 'lives' at either base1 or base 2 depending on the value of - * Exp Bus config registers: - * - * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero, - * and The expansion bus to IXP425_EXP_BUS_BASE2 - */ -#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000) -#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000) - -#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS - -#define IXP425_EXP_BUS_REGION_SIZE (0x08000000) -#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000) - -#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000) -#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000) -#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000) -#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000) -#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000) -#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000) -#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000) -#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000) - -#define IXP425_FLASH_WRITABLE (0x2) -#define IXP425_FLASH_DEFAULT (0xbcd23c40) -#define IXP425_FLASH_WRITE (0xbcd23c42) - -#define IXP425_EXP_CS0_OFFSET 0x00 -#define IXP425_EXP_CS1_OFFSET 0x04 -#define IXP425_EXP_CS2_OFFSET 0x08 -#define IXP425_EXP_CS3_OFFSET 0x0C -#define IXP425_EXP_CS4_OFFSET 0x10 -#define IXP425_EXP_CS5_OFFSET 0x14 -#define IXP425_EXP_CS6_OFFSET 0x18 -#define IXP425_EXP_CS7_OFFSET 0x1C -#define IXP425_EXP_CFG0_OFFSET 0x20 -#define IXP425_EXP_CFG1_OFFSET 0x24 -#define IXP425_EXP_CFG2_OFFSET 0x28 -#define IXP425_EXP_CFG3_OFFSET 0x2C - -/* - * Expansion Bus Controller registers. - */ -#ifndef __ASSEMBLY__ -#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x))) -#else -#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x)) -#endif - -#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET) -#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET) -#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET) -#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET) -#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET) -#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET) -#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET) -#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET) - -#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET) -#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET) -#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET) -#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET) - -/* - * SDRAM Controller registers. - */ -#define IXP425_SDR_CONFIG_OFFSET 0x00 -#define IXP425_SDR_REFRESH_OFFSET 0x04 -#define IXP425_SDR_IR_OFFSET 0x08 - -#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) - -#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) -#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) -#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) - -/* - * UART registers - */ -#define IXP425_UART1 0 -#define IXP425_UART2 0x1000 - -#define IXP425_UART_RBR_OFFSET 0x00 -#define IXP425_UART_THR_OFFSET 0x00 -#define IXP425_UART_DLL_OFFSET 0x00 -#define IXP425_UART_IER_OFFSET 0x04 -#define IXP425_UART_DLH_OFFSET 0x04 -#define IXP425_UART_IIR_OFFSET 0x08 -#define IXP425_UART_FCR_OFFSET 0x00 -#define IXP425_UART_LCR_OFFSET 0x0c -#define IXP425_UART_MCR_OFFSET 0x10 -#define IXP425_UART_LSR_OFFSET 0x14 -#define IXP425_UART_MSR_OFFSET 0x18 -#define IXP425_UART_SPR_OFFSET 0x1c -#define IXP425_UART_ISR_OFFSET 0x20 - -#define IXP425_UART_CFG_BASE_PHYS (0xc8000000) - -#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET) -#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET) -#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET) -#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET) -#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET) -#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET) -#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET) -#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET) -#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET) -#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET) -#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET) -#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET) -#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET) - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) */ -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS -/* - * Peripheral Space Registers - */ -#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000) -#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000) -#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000) -#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000) -#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000) -#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000) -#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000) -#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000) -#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000) -#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000) -#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000) -#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000) - -/* - * UART Register Definitions , Offsets only as there are 2 UARTS. - * IXP425_UART1_BASE , IXP425_UART2_BASE. - */ - -#undef UART_NO_RX_INTERRUPT - -#define IXP425_UART_XTAL 14745600 - -/* - * Constants to make it easy to access Interrupt Controller registers - */ -#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */ -#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */ -#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ -#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */ -#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */ -#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */ -#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ -#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ - -#define N_IRQS 32 -#define IXP425_TIMER_2_IRQ 11 - -/* - * Interrupt Controller Register Definitions. - */ -#ifndef __ASSEMBLY__ -#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x))) -#else -#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x)) -#endif - -#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET) -#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET) -#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET) -#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET) -#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET) -#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET) -#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET) -#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET) - -/* - * Constants to make it easy to access GPIO registers - */ -#define IXP425_GPIO_GPOUTR_OFFSET 0x00 -#define IXP425_GPIO_GPOER_OFFSET 0x04 -#define IXP425_GPIO_GPINR_OFFSET 0x08 -#define IXP425_GPIO_GPISR_OFFSET 0x0C -#define IXP425_GPIO_GPIT1R_OFFSET 0x10 -#define IXP425_GPIO_GPIT2R_OFFSET 0x14 -#define IXP425_GPIO_GPCLKR_OFFSET 0x18 -#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C - -/* - * GPIO Register Definitions. - * [Only perform 32bit reads/writes] - */ -#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x))) - -#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET) -#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET) -#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET) -#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET) -#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET) -#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET) -#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) -#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) - -#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \ - IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R) - -/* - * Macros to make it easy to access the GPIO registers - */ -#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line)) -#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line)) -#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line)) -#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line)) -#define GPIO_INT_ACT_LOW_SET(line) \ - *IXP425_GPIO_GPITR(line) = \ - (*IXP425_GPIO_GPITR(line) & \ - ~(0x7 << (((line) & 0x7) * 3))) | \ - (0x1 << (((line) & 0x7) * 3)) \ - -/* - * Constants to make it easy to access Timer Control/Status registers - */ -#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */ -#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ -#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ -#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ -#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ -#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */ -#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */ -#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */ -#define IXP425_OSST_OFFSET 0x20 /* Timer Status */ - -/* - * Operating System Timer Register Definitions. - */ - -#ifndef __ASSEMBLY__ -#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x))) -#else -#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) -#endif - -/* _B to avoid collision: also defined in npe/include/... */ -#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET) -#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) -#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) -#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) -#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET) -#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET) -#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET) -#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET) -#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET) - -/* - * Timer register values and bit definitions - */ -#define IXP425_OST_ENABLE BIT(0) -#define IXP425_OST_ONE_SHOT BIT(1) -/* Low order bits of reload value ignored */ -#define IXP425_OST_RELOAD_MASK (0x3) -#define IXP425_OST_DISABLED (0x0) -#define IXP425_OSST_TIMER_1_PEND BIT(0) -#define IXP425_OSST_TIMER_2_PEND BIT(1) -#define IXP425_OSST_TIMER_TS_PEND BIT(2) -#define IXP425_OSST_TIMER_WDOG_PEND BIT(3) -#define IXP425_OSST_TIMER_WARM_RESET BIT(4) - -/* - * Constants to make it easy to access PCI Control/Status registers - */ -#define PCI_NP_AD_OFFSET 0x00 -#define PCI_NP_CBE_OFFSET 0x04 -#define PCI_NP_WDATA_OFFSET 0x08 -#define PCI_NP_RDATA_OFFSET 0x0c -#define PCI_CRP_AD_CBE_OFFSET 0x10 -#define PCI_CRP_WDATA_OFFSET 0x14 -#define PCI_CRP_RDATA_OFFSET 0x18 -#define PCI_CSR_OFFSET 0x1c -#define PCI_ISR_OFFSET 0x20 -#define PCI_INTEN_OFFSET 0x24 -#define PCI_DMACTRL_OFFSET 0x28 -#define PCI_AHBMEMBASE_OFFSET 0x2c -#define PCI_AHBIOBASE_OFFSET 0x30 -#define PCI_PCIMEMBASE_OFFSET 0x34 -#define PCI_AHBDOORBELL_OFFSET 0x38 -#define PCI_PCIDOORBELL_OFFSET 0x3C -#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 -#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 -#define PCI_ATPDMA0_LENADDR_OFFSET 0x48 -#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C -#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 -#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 - -/* - * PCI Control/Status Registers - */ -#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x))) - -#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET) -#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET) -#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET) -#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET) -#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) -#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET) -#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET) -#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET) -#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET) -#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET) -#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET) -#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET) -#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET) -#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET) -#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET) -#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET) -#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) -#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) -#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) -#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) -#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) -#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) - -/* - * PCI register values and bit definitions - */ - -/* CSR bit definitions */ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) - -/* ISR (Interrupt status) Register bit definitions */ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) - -/* INTEN (Interrupt Enable) Register bit definitions */ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) - -/* - * Shift value for byte enable on NP cmd/byte enable register - */ -#define IXP425_PCI_NP_CBE_BESL 4 - -/* - * PCI commands supported by NP access unit - */ -#define NP_CMD_IOREAD 0x2 -#define NP_CMD_IOWRITE 0x3 -#define NP_CMD_CONFIGREAD 0xa -#define NP_CMD_CONFIGWRITE 0xb -#define NP_CMD_MEMREAD 0x6 -#define NP_CMD_MEMWRITE 0x7 - -#if 0 -#ifndef __ASSEMBLY__ -extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data); -extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data); -extern void ixp425_pci_init(void *); -#endif -#endif - -/* - * Constants for CRP access into local config space - */ -#define CRP_AD_CBE_BESL 20 -#define CRP_AD_CBE_WRITE BIT(16) - -/* - * Clock Speed Definitions. - */ -#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ - - -#endif diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h deleted file mode 100644 index 8e16a11293..0000000000 --- a/arch/arm/include/asm/arch-ixp/ixp425pci.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * IXP PCI Init - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _IXP425PCI_H -#define _IXP425PCI_H - -#define OK 0 -#define ERROR -1 - -struct pci_controller; -extern void pci_ixp_init(struct pci_controller *hose); - -/* Mask definitions*/ -#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f - -#define PCI_NP_CBE_BESL (4) -#define PCI_NP_AD_FUNCSL (8) - -/*Register addressing definitions for PCI controller configuration - and status registers*/ - -#define PCI_CSR_BASE (0xC0000000) -/* -#define PCI_NP_AD_OFFSET (0x00) -#define PCI_NP_CBE_OFFSET (0x04) -#define PCI_NP_WDATA_OFFSET (0x08) -#define PCI_NP_RDATA_OFFSET (0x0C) -#define PCI_CRP_OFFSET (0x10) -#define PCI_CRP_WDATA_OFFSET (0x14) -#define PCI_CRP_RDATA_OFFSET (0x18) -#define PCI_CSR_OFFSET (0x1C) -#define PCI_ISR_OFFSET (0x20) -#define PCI_INTEN_OFFSET (0x24) -#define PCI_DMACTRL_OFFSET (0x28) -#define PCI_AHBMEMBASE_OFFSET (0x2C) -#define PCI_AHBIOBASE_OFFSET (0x30) -#define PCI_PCIMEMBASE_OFFSET (0x34) -#define PCI_AHBDOORBELL_OFFSET (0x38) -#define PCI_PCIDOORBELL_OFFSET (0x3C) -#define PCI_ATPDMA0_AHBADDR (0x40) -#define PCI_ATPDMA0_PCIADDR (0x44) -#define PCI_ATPDMA0_LENADDR (0x48) -#define PCI_ATPDMA1_AHBADDR (0x4C) -#define PCI_ATPDMA1_PCIADDR (0x50) -#define PCI_ATPDMA1_LENADDR (0x54) -#define PCI_PTADMA0_AHBADDR (0x58) -#define PCI_PTADMA0_PCIADDR (0x5C) -#define PCI_PTADMA0_LENADDR (0x60) -#define PCI_PTADMA1_AHBADDR (0x64) -#define PCI_PTADMA1_PCIADDR (0x68) -#define PCI_PTADMA1_LENADDR (0x6C) -*/ -/*Non prefetch registers bit definitions*/ -/* -#define NP_CMD_INTACK (0x0) -#define NP_CMD_SPECIAL (0x1) -#define NP_CMD_IOREAD (0x2) -#define NP_CMD_IOWRITE (0x3) -#define NP_CMD_MEMREAD (0x6) -#define NP_CMD_MEMWRITE (0x7) -#define NP_CMD_CONFIGREAD (0xa) -#define NP_CMD_CONFIGWRITE (0xb) -*/ - -/*Configuration Port register bit definitions*/ -#define PCI_CRP_WRITE BIT(16) - -/*ISR (Interrupt status) Register bit definitions*/ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) - -/*INTEN (Interrupt Enable) Register bit definitions*/ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) - -/*PCI configuration regs.*/ - -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDOR_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - -#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ -#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ -#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ -#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ -#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ -#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ -#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ -#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ -#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ -#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ - - -/*CSR Register bit definitions*/ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) - -/*Configuration command bit definitions*/ -#define PCI_CFG_CMD_IOAE BIT(0) -#define PCI_CFG_CMD_MAE BIT(1) -#define PCI_CFG_CMD_BME BIT(2) -#define PCI_CFG_CMD_MWIE BIT(4) -#define PCI_CFG_CMD_SER BIT(8) -#define PCI_CFG_CMD_FBBE BIT(9) -#define PCI_CFG_CMD_MDPE BIT(24) -#define PCI_CFG_CMD_STA BIT(27) -#define PCI_CFG_CMD_RTA BIT(28) -#define PCI_CFG_CMD_RMA BIT(29) -#define PCI_CFG_CMD_SSE BIT(30) -#define PCI_CFG_CMD_DPE BIT(31) - -/*DMACTRL DMA Control and status Register*/ -#define PCI_DMACTRL_APDCEN BIT(0) -#define PCI_DMACTRL_APDC0 BIT(4) -#define PCI_DMACTRL_APDE0 BIT(5) -#define PCI_DMACTRL_APDC1 BIT(6) -#define PCI_DMACTRL_APDE1 BIT(7) -#define PCI_DMACTRL_PADCEN BIT(8) -#define PCI_DMACTRL_PADC0 BIT(12) -#define PCI_DMACTRL_PADE0 BIT(13) -#define PCI_DMACTRL_PADC1 BIT(14) -#define PCI_DMACTRL_PADE1 BIT(15) - -#endif diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h new file mode 100644 index 0000000000..d013b830ed --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h @@ -0,0 +1,85 @@ +/* + * K2E: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2E_H +#define __ASM_ARCH_CLOCK_K2E_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + ddr3_clk, + mcm_clk, + pcie_clk, + sgmii_clk, + xgmii_clk, + usb_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, ddr3_pll_clk)\ + CLK(3, sys_clk0_clk)\ + CLK(4, sys_clk0_1_clk)\ + CLK(5, sys_clk0_2_clk)\ + CLK(6, sys_clk0_3_clk)\ + CLK(7, sys_clk0_4_clk)\ + CLK(8, sys_clk0_6_clk)\ + CLK(9, sys_clk0_8_clk)\ + CLK(10, sys_clk0_12_clk)\ + CLK(11, sys_clk0_24_clk)\ + CLK(12, sys_clk1_clk)\ + CLK(13, sys_clk1_3_clk)\ + CLK(14, sys_clk1_4_clk)\ + CLK(15, sys_clk1_6_clk)\ + CLK(16, sys_clk1_12_clk)\ + CLK(17, sys_clk2_clk)\ + CLK(18, sys_clk3_clk) + +#define PLLSET_CMD_LIST "" + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + DDR3_PLL, +}; + +enum { + SPD800, + SPD850, + SPD1000, + SPD1250, + SPD1350, + SPD1400, + SPD1500, + SPD_RSV +}; + +#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_850 {CORE_PLL, 17, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} +#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} +#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} +#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2} +#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2} +#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2} +#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h new file mode 100644 index 0000000000..f28d5f0c4e --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h @@ -0,0 +1,103 @@ +/* + * K2HK: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2HK_H +#define __ASM_ARCH_CLOCK_K2HK_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + tetris_clk, + ddr3a_clk, + ddr3b_clk, + mcm_clk, + pcie_clk, + sgmii_srio_clk, + xgmii_clk, + usb_clk, + rp1_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, tetris_pll_clk)\ + CLK(3, ddr3a_pll_clk)\ + CLK(4, ddr3b_pll_clk)\ + CLK(5, sys_clk0_clk)\ + CLK(6, sys_clk0_1_clk)\ + CLK(7, sys_clk0_2_clk)\ + CLK(8, sys_clk0_3_clk)\ + CLK(9, sys_clk0_4_clk)\ + CLK(10, sys_clk0_6_clk)\ + CLK(11, sys_clk0_8_clk)\ + CLK(12, sys_clk0_12_clk)\ + CLK(13, sys_clk0_24_clk)\ + CLK(14, sys_clk1_clk)\ + CLK(15, sys_clk1_3_clk)\ + CLK(16, sys_clk1_4_clk)\ + CLK(17, sys_clk1_6_clk)\ + CLK(18, sys_clk1_12_clk)\ + CLK(19, sys_clk2_clk)\ + CLK(20, sys_clk3_clk) + +#define PLLSET_CMD_LIST "" + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + TETRIS_PLL, + DDR3A_PLL, + DDR3B_PLL, +}; + +enum { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD_RSV +}; + +#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} +#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_999 {CORE_PLL, 122, 15, 1} +#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} +#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} +#define CORE_PLL_1200 {CORE_PLL, 625, 32, 2} +#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} +#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} +#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} +#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2} +#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2} +#define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1} +#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2} +#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2} +#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2} +#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2} +#define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1} +#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1} +#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1} +#define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1} +#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1} +#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1} +#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2} +#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4} +#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} +#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h new file mode 100644 index 0000000000..bb9a5c4dcf --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h @@ -0,0 +1,95 @@ +/* + * K2L: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2L_H +#define __ASM_ARCH_CLOCK_K2L_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + tetris_clk, + ddr3_clk, + pcie_clk, + sgmii_clk, + usb_clk, + rp1_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, tetris_pll_clk)\ + CLK(3, ddr3_pll_clk)\ + CLK(4, sys_clk0_clk)\ + CLK(5, sys_clk0_1_clk)\ + CLK(6, sys_clk0_2_clk)\ + CLK(7, sys_clk0_3_clk)\ + CLK(8, sys_clk0_4_clk)\ + CLK(9, sys_clk0_6_clk)\ + CLK(10, sys_clk0_8_clk)\ + CLK(11, sys_clk0_12_clk)\ + CLK(12, sys_clk0_24_clk)\ + CLK(13, sys_clk1_clk)\ + CLK(14, sys_clk1_3_clk)\ + CLK(15, sys_clk1_4_clk)\ + CLK(16, sys_clk1_6_clk)\ + CLK(17, sys_clk1_12_clk)\ + CLK(18, sys_clk2_clk)\ + CLK(19, sys_clk3_clk)\ + +#define PLLSET_CMD_LIST "" + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + TETRIS_PLL, + DDR3_PLL, +}; + +enum { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD_RSV +}; + +#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} +#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} +#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} +#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2} +#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} +#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} +#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} +#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} +#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2} +#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2} +#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2} +#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2} +#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2} +#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2} +#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2} +#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2} +#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2} +#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h new file mode 100644 index 0000000000..9f6cfb265f --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -0,0 +1,66 @@ +/* + * keystone2: common clock header file + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_SOC_K2HK +#include +#endif + +#ifdef CONFIG_SOC_K2E +#include +#endif + +#ifdef CONFIG_SOC_K2L +#include +#endif + +#define MAIN_PLL CORE_PLL + +#include + +#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, +#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" +#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) + +enum clk_e { + CLK_LIST(GENERATE_ENUM) +}; + +struct keystone_pll_regs { + u32 reg0; + u32 reg1; +}; + +/* PLL configuration data */ +struct pll_init_data { + int pll; + int pll_m; /* PLL Multiplier */ + int pll_d; /* PLL divider */ + int pll_od; /* PLL output divider */ +}; + +extern const struct keystone_pll_regs keystone_pll_regs[]; +extern int dev_speeds[]; +extern int arm_speeds[]; + +void init_plls(int num_pll, struct pll_init_data *config); +void init_pll(const struct pll_init_data *data); +unsigned long clk_get_rate(unsigned int clk); +unsigned long clk_round_rate(unsigned int clk, unsigned long hz); +int clk_set_rate(unsigned int clk, unsigned long hz); +void pass_pll_pa_clk_enable(void); +int get_max_dev_speed(void); +int get_max_arm_speed(void); + +#endif +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h new file mode 100644 index 0000000000..85a046b89a --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock_defs.h @@ -0,0 +1,111 @@ +/* + * keystone2: common pll clock definitions + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLOCK_DEFS_H_ +#define _CLOCK_DEFS_H_ + +#include + +#define BIT(x) (1 << (x)) + +/* PLL Control Registers */ +struct pllctl_regs { + u32 ctl; /* 00 */ + u32 ocsel; /* 04 */ + u32 secctl; /* 08 */ + u32 resv0; + u32 mult; /* 10 */ + u32 prediv; /* 14 */ + u32 div1; /* 18 */ + u32 div2; /* 1c */ + u32 div3; /* 20 */ + u32 oscdiv1; /* 24 */ + u32 resv1; /* 28 */ + u32 bpdiv; /* 2c */ + u32 wakeup; /* 30 */ + u32 resv2; + u32 cmd; /* 38 */ + u32 stat; /* 3c */ + u32 alnctl; /* 40 */ + u32 dchange; /* 44 */ + u32 cken; /* 48 */ + u32 ckstat; /* 4c */ + u32 systat; /* 50 */ + u32 ckctl; /* 54 */ + u32 resv3[2]; + u32 div4; /* 60 */ + u32 div5; /* 64 */ + u32 div6; /* 68 */ + u32 div7; /* 6c */ + u32 div8; /* 70 */ + u32 div9; /* 74 */ + u32 div10; /* 78 */ + u32 div11; /* 7c */ + u32 div12; /* 80 */ +}; + +static struct pllctl_regs *pllctl_regs[] = { + (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100) +}; + +#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) +#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) +#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) + +#define pllctl_reg_rmw(pll, reg, mask, val) \ + pllctl_reg_write(pll, reg, \ + (pllctl_reg_read(pll, reg) & ~(mask)) | val) + +#define pllctl_reg_setbits(pll, reg, mask) \ + pllctl_reg_rmw(pll, reg, 0, mask) + +#define pllctl_reg_clrbits(pll, reg, mask) \ + pllctl_reg_rmw(pll, reg, mask, 0) + +#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) + +/* PLLCTL Bits */ +#define PLLCTL_BYPASS BIT(23) +#define PLL_PLLRST BIT(14) +#define PLLCTL_PAPLL BIT(13) +#define PLLCTL_CLKMODE BIT(8) +#define PLLCTL_PLLSELB BIT(7) +#define PLLCTL_ENSAT BIT(6) +#define PLLCTL_PLLENSRC BIT(5) +#define PLLCTL_PLLDIS BIT(4) +#define PLLCTL_PLLRST BIT(3) +#define PLLCTL_PLLPWRDN BIT(1) +#define PLLCTL_PLLEN BIT(0) +#define PLLSTAT_GO BIT(0) + +#define MAIN_ENSAT_OFFSET 6 + +#define PLLDIV_ENABLE BIT(15) + +#define PLL_DIV_MASK 0x3f +#define PLL_MULT_MASK 0x1fff +#define PLL_MULT_SHIFT 6 +#define PLLM_MULT_HI_MASK 0x7f +#define PLLM_MULT_HI_SHIFT 12 +#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT) +#define PLLM_MULT_LO_MASK 0x3f +#define PLL_CLKOD_MASK 0xf +#define PLL_CLKOD_SHIFT 19 +#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT) +#define PLL_BWADJ_LO_MASK 0xff +#define PLL_BWADJ_LO_SHIFT 24 +#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) +#define PLL_BWADJ_HI_MASK 0xf + +#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) +#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) +#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) + +#endif /* _CLOCK_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h new file mode 100644 index 0000000000..b044d6f18f --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -0,0 +1,63 @@ +/* + * DDR3 + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DDR3_H_ +#define _DDR3_H_ + +#include + +struct ddr3_phy_config { + unsigned int pllcr; + unsigned int pgcr1_mask; + unsigned int pgcr1_val; + unsigned int ptr0; + unsigned int ptr1; + unsigned int ptr2; + unsigned int ptr3; + unsigned int ptr4; + unsigned int dcr_mask; + unsigned int dcr_val; + unsigned int dtpr0; + unsigned int dtpr1; + unsigned int dtpr2; + unsigned int mr0; + unsigned int mr1; + unsigned int mr2; + unsigned int dtcr; + unsigned int pgcr2; + unsigned int zq0cr1; + unsigned int zq1cr1; + unsigned int zq2cr1; + unsigned int pir_v1; + unsigned int pir_v2; +}; + +struct ddr3_emif_config { + unsigned int sdcfg; + unsigned int sdtim1; + unsigned int sdtim2; + unsigned int sdtim3; + unsigned int sdtim4; + unsigned int zqcfg; + unsigned int sdrfc; +}; + +void ddr3_init(void); +int ddr3_get_size(void); +void ddr3_reset_ddrphy(void); +void ddr3_init_ecc(u32 base); +void ddr3_disable_ecc(u32 base); +void ddr3_check_ecc_int(u32 base); +int ddr3_ecc_support_rmw(u32 base); +void ddr3_err_reset_workaround(void); +void ddr3_enable_ecc(u32 base, int test); +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h new file mode 100644 index 0000000000..df499957e5 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -0,0 +1,65 @@ +/* + * K2E: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2E_H +#define __ASM_ARCH_HARDWARE_K2E_H + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x24000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD_RST 0 +#define KS2_LPSC_USB_1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_PCIE_1 27 +#define KS2_LPSC_XGE 50 + +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 13 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ + +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02324000 +#define KS2_LANES_PER_SGMII_SERDES 4 + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 1 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 +#define KS2_NETCP_PDMA_TX_BASE 0x24187000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x24188000 +#define KS2_NETCP_PDMA_RX_CH_NUM 91 +#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 + +/* NETCP */ +#define KS2_NETCP_BASE 0x24000000 + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h new file mode 100644 index 0000000000..195c0d3003 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -0,0 +1,106 @@ +/* + * K2HK: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2HK_H +#define __ASM_ARCH_HARDWARE_K2HK_H + +#define KS2_ARM_PLL_EN BIT(13) + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x02000000 + +/* PLL control registers */ +#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) +#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD 0 +#define KS2_LPSC_DUMMY1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_SRIO 11 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_GEM_1 16 +#define KS2_LPSC_GEM_2 17 +#define KS2_LPSC_GEM_3 18 +#define KS2_LPSC_GEM_4 19 +#define KS2_LPSC_GEM_5 20 +#define KS2_LPSC_GEM_6 21 +#define KS2_LPSC_GEM_7 22 +#define KS2_LPSC_EMIF4F_DDR3A 23 +#define KS2_LPSC_EMIF4F_DDR3B 24 +#define KS2_LPSC_TAC 25 +#define KS2_LPSC_RAC 26 +#define KS2_LPSC_RAC_1 27 +#define KS2_LPSC_FFTC_A 28 +#define KS2_LPSC_FFTC_B 29 +#define KS2_LPSC_FFTC_C 30 +#define KS2_LPSC_FFTC_D 31 +#define KS2_LPSC_FFTC_E 32 +#define KS2_LPSC_FFTC_F 33 +#define KS2_LPSC_AI2 34 +#define KS2_LPSC_TCP3D_0 35 +#define KS2_LPSC_TCP3D_1 36 +#define KS2_LPSC_TCP3D_2 37 +#define KS2_LPSC_TCP3D_3 38 +#define KS2_LPSC_VCP2X4_A 39 +#define KS2_LPSC_CP2X4_B 40 +#define KS2_LPSC_VCP2X4_C 41 +#define KS2_LPSC_VCP2X4_D 42 +#define KS2_LPSC_VCP2X4_E 43 +#define KS2_LPSC_VCP2X4_F 44 +#define KS2_LPSC_VCP2X4_G 45 +#define KS2_LPSC_VCP2X4_H 46 +#define KS2_LPSC_BCP 47 +#define KS2_LPSC_DXB 48 +#define KS2_LPSC_VUSR1 49 +#define KS2_LPSC_XGE 50 +#define KS2_LPSC_ARM_SREFLEX 51 + +/* DDR3B definitions */ +#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 +#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 +#define KS2_DDR3B_DDRPHYC 0x02328000 + +#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 + channel 29 */ + +/* SGMII SerDes */ +#define KS2_LANES_PER_SGMII_SERDES 4 + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 8 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000 +#define KS2_NETCP_PDMA_TX_BASE 0x02004400 +#define KS2_NETCP_PDMA_TX_CH_NUM 9 +#define KS2_NETCP_PDMA_RX_BASE 0x02004800 +#define KS2_NETCP_PDMA_RX_CH_NUM 26 +#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 32 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 648 + +/* NETCP */ +#define KS2_NETCP_BASE 0x02000000 + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h new file mode 100644 index 0000000000..4f1197ea92 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h @@ -0,0 +1,108 @@ +/* + * K2L: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2L_H +#define __ASM_ARCH_HARDWARE_K2L_H + +#define KS2_ARM_PLL_EN BIT(13) + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x26000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD 0 +#define KS2_LPSC_DFE_IQN_SYS 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE0 10 +#define KS2_LPSC_PCIE1 11 +#define KS2_LPSC_JESD_MISC 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_GEM_1 16 +#define KS2_LPSC_GEM_2 17 +#define KS2_LPSC_GEM_3 18 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_TAC 25 +#define KS2_LPSC_RAC 26 +#define KS2_LPSC_DDUC4X_CFR2X_BB 27 +#define KS2_LPSC_FFTC_A 28 +#define KS2_LPSC_OSR 34 +#define KS2_LPSC_TCP3D_0 35 +#define KS2_LPSC_TCP3D_1 37 +#define KS2_LPSC_VCP2X4_A 39 +#define KS2_LPSC_VCP2X4_B 40 +#define KS2_LPSC_VCP2X4_C 41 +#define KS2_LPSC_VCP2X4_D 42 +#define KS2_LPSC_BCP 47 +#define KS2_LPSC_DPD4X 48 +#define KS2_LPSC_FFTC_B 49 +#define KS2_LPSC_IQN_AIL 50 + +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 14 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 +#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D + +/* OSR */ +#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */ +#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */ +#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */ +#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */ + +/* OSR ECC Vector register */ +#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */ +#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */ + +#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */ +#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */ + +/* OSR ECC control register */ +#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */ +#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */ +#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */ + +/* Number of OSR RAM banks */ +#define KS2_OSR_NUM_RAM_BANKS 4 + +/* OSR memory size */ +#define KS2_OSR_SIZE 0x100000 + +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02320000 +#define KS2_LANES_PER_SGMII_SERDES 2 + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 4 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000 +#define KS2_NETCP_PDMA_TX_BASE 0x26187000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x26188000 +#define KS2_NETCP_PDMA_RX_CH_NUM 91 +#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 + +/* NETCP */ +#define KS2_NETCP_BASE 0x26000000 + +#endif /* __ASM_ARCH_HARDWARE_K2L_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h new file mode 100644 index 0000000000..16cbcee12b --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -0,0 +1,290 @@ +/* + * Keystone2: Common SoC definitions, structures etc. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +#ifndef __ASSEMBLY__ + +#include +#include + +#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr)) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#endif + +#define BIT(x) (1 << (x)) + +#define KS2_DDRPHY_PIR_OFFSET 0x04 +#define KS2_DDRPHY_PGCR0_OFFSET 0x08 +#define KS2_DDRPHY_PGCR1_OFFSET 0x0C +#define KS2_DDRPHY_PGSR0_OFFSET 0x10 +#define KS2_DDRPHY_PGSR1_OFFSET 0x14 +#define KS2_DDRPHY_PLLCR_OFFSET 0x18 +#define KS2_DDRPHY_PTR0_OFFSET 0x1C +#define KS2_DDRPHY_PTR1_OFFSET 0x20 +#define KS2_DDRPHY_PTR2_OFFSET 0x24 +#define KS2_DDRPHY_PTR3_OFFSET 0x28 +#define KS2_DDRPHY_PTR4_OFFSET 0x2C +#define KS2_DDRPHY_DCR_OFFSET 0x44 + +#define KS2_DDRPHY_DTPR0_OFFSET 0x48 +#define KS2_DDRPHY_DTPR1_OFFSET 0x4C +#define KS2_DDRPHY_DTPR2_OFFSET 0x50 + +#define KS2_DDRPHY_MR0_OFFSET 0x54 +#define KS2_DDRPHY_MR1_OFFSET 0x58 +#define KS2_DDRPHY_MR2_OFFSET 0x5C +#define KS2_DDRPHY_DTCR_OFFSET 0x68 +#define KS2_DDRPHY_PGCR2_OFFSET 0x8C + +#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184 +#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194 +#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4 +#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4 + +#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0 + +#define IODDRM_MASK 0x00000180 +#define ZCKSEL_MASK 0x01800000 +#define CL_MASK 0x00000072 +#define WR_MASK 0x00000E00 +#define BL_MASK 0x00000003 +#define RRMODE_MASK 0x00040000 +#define UDIMM_MASK 0x20000000 +#define BYTEMASK_MASK 0x0003FC00 +#define MPRDQ_MASK 0x00000080 +#define PDQ_MASK 0x00000070 +#define NOSRA_MASK 0x08000000 +#define ECC_MASK 0x00000001 + +/* DDR3 definitions */ +#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 +#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 +#define KS2_DDR3A_DDRPHYC 0x02329000 + +#define KS2_DDR3_MIDR_OFFSET 0x00 +#define KS2_DDR3_STATUS_OFFSET 0x04 +#define KS2_DDR3_SDCFG_OFFSET 0x08 +#define KS2_DDR3_SDRFC_OFFSET 0x10 +#define KS2_DDR3_SDTIM1_OFFSET 0x18 +#define KS2_DDR3_SDTIM2_OFFSET 0x1C +#define KS2_DDR3_SDTIM3_OFFSET 0x20 +#define KS2_DDR3_SDTIM4_OFFSET 0x28 +#define KS2_DDR3_PMCTL_OFFSET 0x38 +#define KS2_DDR3_ZQCFG_OFFSET 0xC8 + +#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 + +/* DDR3 ECC */ +#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC +#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4 +#define KS2_DDR3_ECC_CTRL_OFFSET 0x110 +#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114 +#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130 +#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C + +/* DDR3 ECC Interrupt Status register */ +#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5) +#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4) +#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3) + +/* DDR3 ECC Control register */ +#define KS2_DDR3_ECC_EN BIT(31) +#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30) +#define KS2_DDR3_ECC_VERIFY_EN BIT(29) +#define KS2_DDR3_ECC_RMW_EN BIT(28) +#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0) + +#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \ + KS2_DDR3_ECC_ADDR_RNG_PROT | \ + KS2_DDR3_ECC_VERIFY_EN) + +/* EDMA */ +#define KS2_EDMA0_BASE 0x02700000 + +/* EDMA3 register offsets */ +#define KS2_EDMA_QCHMAP0 0x0200 +#define KS2_EDMA_IPR 0x1068 +#define KS2_EDMA_ICR 0x1070 +#define KS2_EDMA_QEECR 0x1088 +#define KS2_EDMA_QEESR 0x108c +#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x)) + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_BASE 0x02608000 + +/* Chip Interrupt Controller register offsets */ +#define KS2_CIC_CTRL 0x04 +#define KS2_CIC_HOST_CTRL 0x0C +#define KS2_CIC_GLOBAL_ENABLE 0x10 +#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28 +#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34 +#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2)) + +#define KS2_UART0_BASE 0x02530c00 +#define KS2_UART1_BASE 0x02531000 + +/* Boot Config */ +#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) +#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) +#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c) + +/* PSC */ +#define KS2_PSC_BASE 0x02350000 +#define KS2_LPSC_GEM_0 15 +#define KS2_LPSC_TETRIS 52 +#define KS2_TETRIS_PWR_DOMAIN 31 + +/* Chip configuration unlock codes and registers */ +#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) +#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) +#define KS2_KICK0_MAGIC 0x83e70b13 +#define KS2_KICK1_MAGIC 0x95a4f1e0 + +/* PLL control registers */ +#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) +#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) +#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) +#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) +#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) +#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) +#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) + +#define KS2_PLL_CNTRL_BASE 0x02310000 +#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4) +#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec) +#define KS2_RSTCTRL_KEY 0x5a69 +#define KS2_RSTCTRL_MASK 0xffff0000 +#define KS2_RSTCTRL_SWRST 0xfffe0000 +#define KS2_RSTYPE_PLL_SOFT BIT(13) + +/* SPI */ +#define KS2_SPI0_BASE 0x21000400 +#define KS2_SPI1_BASE 0x21000600 +#define KS2_SPI2_BASE 0x21000800 +#define KS2_SPI_BASE KS2_SPI0_BASE + +/* AEMIF */ +#define KS2_AEMIF_CNTRL_BASE 0x21000a00 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + +/* Flag from ks2_debug options to check if DSPs need to stay ON */ +#define DBG_LEAVE_DSPS_ON 0x1 + +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc00000 +#define KS2_MSMC_DATA_BASE 0x0c000000 +#define KS2_MSMC_SEGMENT_TETRIS 8 +#define KS2_MSMC_SEGMENT_NETCP 9 +#define KS2_MSMC_SEGMENT_QM_PDSP 10 +#define KS2_MSMC_SEGMENT_PCIE0 11 + +/* MSMC segment size shift bits */ +#define KS2_MSMC_SEG_SIZE_SHIFT 12 +#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) +#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ + KS2_MSMC_SEG_SIZE_SHIFT) + +/* Device speed */ +#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98) +#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90) +#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) + +/* Queue manager */ +#define KS2_QM_BASE_ADDRESS 0x23a80000 +#define KS2_QM_CONF_BASE 0x02a02000 +#define KS2_QM_DESC_SETUP_BASE 0x02a03000 +#define KS2_QM_STATUS_RAM_BASE 0x02a06000 +#define KS2_QM_INTD_CONF_BASE 0x02a0c000 +#define KS2_QM_PDSP1_CMD_BASE 0x02a20000 +#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000 +#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000 +#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000 +#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 +#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 +#define KS2_QM_LINK_RAM_BASE 0x00100000 +#define KS2_QM_REGION_NUM 64 +#define KS2_QM_QPOOL_NUM 4000 + +/* USB */ +#define KS2_USB_SS_BASE 0x02680000 +#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000) +#define KS2_DEV_USB_PHY_BASE 0x02620738 +#define KS2_USB_PHY_CFG_BASE 0x02630000 + +#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) + +/* SGMII SerDes */ +#define KS2_SGMII_SERDES_BASE 0x0232a000 + +#ifdef CONFIG_SOC_K2HK +#include +#endif + +#ifdef CONFIG_SOC_K2E +#include +#endif + +#ifdef CONFIG_SOC_K2L +#include +#endif + +#ifndef __ASSEMBLY__ +static inline int cpu_is_k2hk(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb981) ? 1 : 0; +} + +static inline int cpu_is_k2e(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a6) ? 1 : 0; +} + +static inline int cpu_is_k2l(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a7) ? 1 : 0; +} + +static inline int cpu_revision(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int rev = (jtag_id >> 28) & 0xf; + + return rev; +} + +int cpu_to_bus(u32 *ptr, u32 length); +void sdelay(unsigned long); + +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/i2c_defs.h b/arch/arm/include/asm/arch-keystone/i2c_defs.h new file mode 100644 index 0000000000..d4256526cc --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/i2c_defs.h @@ -0,0 +1,17 @@ +/* + * keystone: i2c driver definitions + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _I2C_DEFS_H_ +#define _I2C_DEFS_H_ + +#define I2C0_BASE 0x02530000 +#define I2C1_BASE 0x02530400 +#define I2C2_BASE 0x02530800 +#define I2C_BASE I2C0_BASE + +#endif diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/include/asm/arch-keystone/mon.h new file mode 100644 index 0000000000..33a28764bc --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/mon.h @@ -0,0 +1,15 @@ +/* + * K2HK: secure kernel command header file + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MON_H_ +#define _MON_H_ + +int mon_power_off(int core_id); + +#endif diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h new file mode 100644 index 0000000000..083f5ba052 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/msmc.h @@ -0,0 +1,45 @@ +/* + * MSMC controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MSMC_H_ +#define _MSMC_H_ + +#include + +enum mpax_seg_size { + MPAX_SEG_4K = 0x0b, + MPAX_SEG_8K, + MPAX_SEG_16K, + MPAX_SEG_32K, + MPAX_SEG_64K, + MPAX_SEG_128K, + MPAX_SEG_256K, + MPAX_SEG_512K, + MPAX_SEG_1M, + MPAX_SEG_2M, + MPAX_SEG_4M, + MPAX_SEG_8M, + MPAX_SEG_16M, + MPAX_SEG_32M, + MPAX_SEG_64M, + MPAX_SEG_128M, + MPAX_SEG_256M, + MPAX_SEG_512M, + MPAX_SEG_1G, + MPAX_SEG_2G, + MPAX_SEG_4G +}; + +void msmc_share_all_segments(int priv_id); +void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax); +void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax); +void msmc_map_ses_segment(int priv_id, int ses_pair, + u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size); + +#endif diff --git a/arch/arm/include/asm/arch-keystone/psc_defs.h b/arch/arm/include/asm/arch-keystone/psc_defs.h new file mode 100644 index 0000000000..70d22cf217 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/psc_defs.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _PSC_DEFS_H_ +#define _PSC_DEFS_H_ + +#include + +/* + * FILE PURPOSE: Local Power Sleep Controller definitions + * + * FILE NAME: psc_defs.h + * + * DESCRIPTION: Provides local definitions for the power saver controller + * + */ + +/* Register offsets */ +#define PSC_REG_PTCMD 0x120 +#define PSC_REG_PSTAT 0x128 +#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) +#define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) +#define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) +#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) +#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) + +#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \ + (u32)1)) << ((u32)y))) + +#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y) +#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \ + ((((u32)f) << (y)) & BOOTBITMASK(x, y)) + +/* PDCTL */ +#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0) +#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12) + +/* PDSTAT */ +#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0) + +/* MDCFG */ +#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16) +#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14) + +/* MDCTL */ +#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0) +#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8) +#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) +#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \ + 12, 12) + +/* MDSTAT */ +#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0) +#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) +#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9) + +/* PDCTL states */ +#define PSC_REG_VAL_PDCTL_NEXT_ON 1 +#define PSC_REG_VAL_PDCTL_NEXT_OFF 0 + +#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0 + +/* MDCTL states */ +#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0 +#define PSC_REG_VAL_MDCTL_NEXT_OFF 2 +#define PSC_REG_VAL_MDCTL_NEXT_ON 3 + +/* MDSTAT states */ +#define PSC_REG_VAL_MDSTAT_STATE_ON 3 +#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24 +#define PSC_REG_VAL_MDSTAT_STATE_OFF 2 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22 + +/* + * Timeout limit on checking PTSTAT. This is the number of times the + * wait function will be called before giving up. + */ +#define PSC_PTSTAT_TIMEOUT_LIMIT 100 + +u32 psc_get_domain_num(u32 mod_num); +int psc_enable_module(u32 mod_num); +int psc_disable_module(u32 mod_num); +int psc_disable_domain(u32 domain_num); + +#endif /* _PSC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/include/asm/arch-keystone/xhci-keystone.h new file mode 100644 index 0000000000..3aab4e045f --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/xhci-keystone.h @@ -0,0 +1,21 @@ +/* + * USB 3.0 DRD Controller + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define USB3_PHY_REF_SSP_EN BIT(29) +#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16) + +/* KEYSTONE2 XHCI PHY register structure */ +struct keystone_xhci_phy { + unsigned int phy_utmi; /* ctl0 */ + unsigned int phy_pipe; /* ctl1 */ + unsigned int phy_param_ctrl_1; /* ctl2 */ + unsigned int phy_param_ctrl_2; /* ctl3 */ + unsigned int phy_clock; /* ctl4 */ + unsigned int phy_pll; /* ctl5 */ +}; diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 197703b838..e77ac400d8 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -23,8 +23,7 @@ #error "SOC Name not defined" #endif /* CONFIG_KW88F6281 */ -#include -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#include #define CONFIG_SYS_CACHELINE_SIZE 32 /* default Dcache Line length for kirkwood */ #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ @@ -38,7 +37,7 @@ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file */ #ifndef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg #endif /* CONFIG_SYS_KWD_CONFIG */ /* Kirkwood has 2k of Security SRAM, use it for SP */ @@ -129,7 +128,8 @@ */ #ifdef CONFIG_CMD_I2C #ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI #endif #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index 97daa403ce..926d347110 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -140,11 +140,11 @@ struct kwgpio_registers { * functions */ unsigned char get_random_hex(void); -unsigned int kw_sdram_bar(enum memory_bank bank); -unsigned int kw_sdram_bs(enum memory_bank bank); -void kw_sdram_size_adjust(enum memory_bank bank); +unsigned int mvebu_sdram_bar(enum memory_bank bank); +unsigned int mvebu_sdram_bs(enum memory_bank bank); +void mvebu_sdram_size_adjust(enum memory_bank bank); int kw_config_adr_windows(void); -void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, +void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, unsigned int mpp16_23, unsigned int mpp24_31, diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h index 5f4d786085..aa8c5da36d 100644 --- a/arch/arm/include/asm/arch-kirkwood/gpio.h +++ b/arch/arm/include/asm/arch-kirkwood/gpio.h @@ -21,14 +21,14 @@ #define GPIO_MAX 50 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) -#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00) -#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04) -#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08) -#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) -#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10) -#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14) -#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18) -#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) +#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) +#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) +#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) /* * Kirkwood-specific GPIO API diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h deleted file mode 100644 index bc207f536c..0000000000 --- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Header file for the Marvell's Feroceon CPU core. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_KIRKWOOD_H -#define _ASM_ARCH_KIRKWOOD_H - -#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) - -/* SOC specific definations */ -#define INTREG_BASE 0xd0000000 -#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) -#define KW_OFFSET_REG (INTREG_BASE + 0x20080) - -/* undocumented registers */ -#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) -#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) - -#define KW_TWSI_BASE (KW_REGISTER(0x11000)) -#define KW_UART0_BASE (KW_REGISTER(0x12000)) -#define KW_UART1_BASE (KW_REGISTER(0x12100)) -#define KW_MPP_BASE (KW_REGISTER(0x10000)) -#define KW_GPIO0_BASE (KW_REGISTER(0x10100)) -#define KW_GPIO1_BASE (KW_REGISTER(0x10140)) -#define KW_RTC_BASE (KW_REGISTER(0x10300)) -#define KW_NANDF_BASE (KW_REGISTER(0x10418)) -#define KW_SPI_BASE (KW_REGISTER(0x10600)) -#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) -#define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) -#define KW_TIMER_BASE (KW_REGISTER(0x20300)) -#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) -#define KW_USB20_BASE (KW_REGISTER(0x50000)) -#define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) -#define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) -#define KW_SATA_BASE (KW_REGISTER(0x80000)) - -/* Kirkwood Sata controller has two ports */ -#define KW_SATA_PORT0_OFFSET 0x2000 -#define KW_SATA_PORT1_OFFSET 0x4000 - -/* Kirkwood GbE controller has two ports */ -#define MAX_MVGBE_DEVS 2 -#define MVGBE0_BASE KW_EGIGA0_BASE -#define MVGBE1_BASE KW_EGIGA1_BASE - -/* Kirkwood USB Host controller */ -#define MVUSB0_BASE KW_USB20_BASE -#define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0 -#define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1 -#define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2 -#define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3 - -/* Kirkwood CPU memory windows */ -#define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA -#define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE -#define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE - -#if defined (CONFIG_KW88F6281) -#include -#elif defined (CONFIG_KW88F6192) -#include -#else -#error "SOC Name not defined" -#endif /* CONFIG_KW88F6281 */ -#endif /* CONFIG_FEROCEON_88FR131 */ -#endif /* _ASM_ARCH_KIRKWOOD_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/include/asm/arch-kirkwood/soc.h new file mode 100644 index 0000000000..58ed71b186 --- /dev/null +++ b/arch/arm/include/asm/arch-kirkwood/soc.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Header file for the Marvell's Feroceon CPU core. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_KIRKWOOD_H +#define _ASM_ARCH_KIRKWOOD_H + +#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) + +/* SOC specific definations */ +#define INTREG_BASE 0xd0000000 +#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) +#define KW_OFFSET_REG (INTREG_BASE + 0x20080) + +/* undocumented registers */ +#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) +#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) + +#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500)) +#define KW_TWSI_BASE (KW_REGISTER(0x11000)) +#define KW_UART0_BASE (KW_REGISTER(0x12000)) +#define KW_UART1_BASE (KW_REGISTER(0x12100)) +#define KW_MPP_BASE (KW_REGISTER(0x10000)) +#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100)) +#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140)) +#define KW_RTC_BASE (KW_REGISTER(0x10300)) +#define KW_NANDF_BASE (KW_REGISTER(0x10418)) +#define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) +#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) +#define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) +#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) +#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) +#define KW_USB20_BASE (KW_REGISTER(0x50000)) +#define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) +#define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) +#define KW_SATA_BASE (KW_REGISTER(0x80000)) +#define KW_SDIO_BASE (KW_REGISTER(0x90000)) + +/* Kirkwood Sata controller has two ports */ +#define KW_SATA_PORT0_OFFSET 0x2000 +#define KW_SATA_PORT1_OFFSET 0x4000 + +/* Kirkwood GbE controller has two ports */ +#define MAX_MVGBE_DEVS 2 +#define MVGBE0_BASE KW_EGIGA0_BASE +#define MVGBE1_BASE KW_EGIGA1_BASE + +/* Kirkwood USB Host controller */ +#define MVUSB0_BASE KW_USB20_BASE +#define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0 +#define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1 +#define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2 +#define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3 + +/* Kirkwood CPU memory windows */ +#define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA +#define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE +#define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE + +#if defined (CONFIG_KW88F6281) +#include +#elif defined (CONFIG_KW88F6192) +#include +#else +#error "SOC Name not defined" +#endif /* CONFIG_KW88F6281 */ +#endif /* CONFIG_FEROCEON_88FR131 */ +#endif /* _ASM_ARCH_KIRKWOOD_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h deleted file mode 100644 index b1cf614ca9..0000000000 --- a/arch/arm/include/asm/arch-kirkwood/spi.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Derived from drivers/spi/mpc8xxx_spi.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __KW_SPI_H__ -#define __KW_SPI_H__ - -/* SPI Registers on kirkwood SOC */ -struct kwspi_registers { - u32 ctrl; /* 0x10600 */ - u32 cfg; /* 0x10604 */ - u32 dout; /* 0x10608 */ - u32 din; /* 0x1060c */ - u32 irq_cause; /* 0x10610 */ - u32 irq_mask; /* 0x10614 */ -}; - -/* They are used to define CONFIG_SYS_KW_SPI_MPP - * each of the below #defines selects which mpp is - * configured for each SPI signal in spi_claim_bus - * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) - * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) - * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) - */ -#define MOSI_MPP6 (1 << 0) -#define SCK_MPP10 (1 << 1) -#define MISO_MPP11 (1 << 2) - -#define KWSPI_CLKPRESCL_MASK 0x1f -#define KWSPI_CLKPRESCL_MIN 0x12 -#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ -#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ -#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ -#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ -#define KWSPI_XFERLEN_1BYTE 0 -#define KWSPI_XFERLEN_2BYTE (1 << 5) -#define KWSPI_XFERLEN_MASK (1 << 5) -#define KWSPI_ADRLEN_1BYTE 0 -#define KWSPI_ADRLEN_2BYTE 1 << 8 -#define KWSPI_ADRLEN_3BYTE 2 << 8 -#define KWSPI_ADRLEN_4BYTE 3 << 8 -#define KWSPI_ADRLEN_MASK 3 << 8 -#define KWSPI_TIMEOUT 10000 - -#endif /* __KW_SPI_H__ */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index a46baf249c..8f6426bc1b 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -10,14 +10,10 @@ #define _LPC32XX_CONFIG_H /* Basic CPU architecture */ -#define CONFIG_ARM926EJS #define CONFIG_ARCH_CPU_INIT #define CONFIG_NR_DRAM_BANKS_MAX 2 -/* 1KHz clock tick */ -#define CONFIG_SYS_HZ 1000 - /* UART configuration */ #if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) #define CONFIG_SYS_NS16550_SERIAL diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h new file mode 100644 index 0000000000..fd36bb0a50 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/clock.h @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_LS102XA_CLOCK_H_ +#define __ASM_ARCH_LS102XA_CLOCK_H_ + +#include + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_I2C_CLK, + MXC_DSPI_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h new file mode 100644 index 0000000000..c58abdb38f --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -0,0 +1,109 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV7_LS102XA_CONFIG_ +#define _ASM_ARMV7_LS102XA_CONFIG_ + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define OCRAM_BASE_ADDR 0x10000000 +#define OCRAM_SIZE 0x00020000 +#define OCRAM_BASE_S_ADDR 0x10010000 +#define OCRAM_S_SIZE 0x00010000 + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 + +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) + +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) +#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) +#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) +#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) +#define CONFIG_SYS_LS102XA_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) + +#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 +#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 +#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 +#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 +#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + +#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) + +#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) + +#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) +#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) + +#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) + +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + +#ifdef CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR_BE +#define CONFIG_VERY_BIG_RAM +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#else +#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 +#endif +#define CONFIG_SYS_FSL_DDR +#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#endif + +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_WDOG_BE +#define CONFIG_SYS_FSL_DSPI_BE +#define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_LE + +#define DCU_LAYER_MAX_NUM 16 + +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +#define CONFIG_SYS_FSL_SRDS_1 + +#ifdef CONFIG_SOC_LS102XA +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FSL_ERRATUM_A008378 +#else +#error SoC not defined +#endif + +#define FSL_IFC_COMPAT "fsl,ifc" +#define FSL_QSPI_COMPAT "fsl,ls1-qspi" +#define FSL_DSPI_COMPAT "fsl,vf610-dspi" + +#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h new file mode 100644 index 0000000000..3a92f5a7b4 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include + +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + SATA1, + SGMII_TSEC1, + SGMII_TSEC2, +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); +const char *serdes_clock_to_string(u32 clock); + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); + +#endif /* __FSL_SERDES_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h new file mode 100644 index 0000000000..b7044362d3 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes via , so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_LS102XA_GPIO_H_ +#define __ASM_ARCH_LS102XA_GPIO_H_ + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h new file mode 100644 index 0000000000..f70d568d46 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -0,0 +1,505 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_LS102XA_IMMAP_H_ +#define __ASM_ARCH_LS102XA_IMMAP_H_ + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) +#define SVR_MIN(svr) (((svr) >> 0) & 0xf) +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) + +#define SOC_VER_SLS1020 0x00 +#define SOC_VER_LS1020 0x10 +#define SOC_VER_LS1021 0x11 +#define SOC_VER_LS1022 0x12 + +#define CCSR_BRR_OFFSET 0xe4 +#define CCSR_SCRATCHRW1_OFFSET 0x200 + +#define RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define RCWSR0_MEM_PLL_RAT_MASK 0x3f + +#define RCWSR4_SRDS1_PRTCL_SHIFT 24 +#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 + +#define TIMER_COMP_VAL 0xffffffff +#define ARCH_TIMER_CTRL_ENABLE (1 << 0) +#define SYS_COUNTER_CTRL_ENABLE (1 << 24) + +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 + +#define DCFG_DCSR_PORCR1 0 + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; +}; + +/* Device Configuration and Pin Control */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_02c[0x70-0x2c]; + u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u8 res_084[0x94-0x84]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_09c[0xa4-0x9c]; + u32 svr; /* System version */ + u8 res_0a8[0xb0-0xa8]; + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ + u8 res_0b8[0xc0-0xb8]; + u32 rstrqmr1; /* Reset request mask */ + u8 res_0c4[0xc8-0xc4]; + u32 rstrqsr1; /* Reset request status */ + u8 res_0cc[0xd4-0xcc]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res_0d8[0xdc-0xd8]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res_0e0[0xe4-0xe0]; + u32 brrl; /* Boot release */ + u8 res_0e8[0x100-0xe8]; + u32 rcwsr[16]; /* Reset control word status */ + u8 res_140[0x200-0x140]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res_210[0x300-0x210]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 crstsr; + u8 res_404[0x550-0x404]; + u32 sataliodnr; + u8 res_554[0x604-0x554]; + u32 pamubypenr; + u32 dmacr1; + u8 res_60c[0x740-0x60c]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[1]; /* Core Cluster n Topology Register */ + u8 res_848[0xe60-0x848]; + u32 ddrclkdr; + u8 res_e60[0xe68-0xe64]; + u32 ifcclkdr; + u8 res_e68[0xe80-0xe6c]; + u32 sdhcpcr; +}; + +#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f +#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 +#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 +#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 +#define SCFG_PIXCLKCR_PXCKEN 0x80000000 +#define SCFG_QSPI_CLKSEL 0xc0100000 + +/* Supplemental Configuration Unit */ +struct ccsr_scfg { + u32 dpslpcr; + u32 resv0[2]; + u32 etsecclkdpslpcr; + u32 resv1[5]; + u32 fuseovrdcr; + u32 pixclkcr; + u32 resv2[5]; + u32 spimsicr; + u32 resv3[6]; + u32 pex1pmwrcr; + u32 pex1pmrdsr; + u32 resv4[3]; + u32 usb3prm1cr; + u32 usb4prm2cr; + u32 pex1rdmsgpldlsbsr; + u32 pex1rdmsgpldmsbsr; + u32 pex2rdmsgpldlsbsr; + u32 pex2rdmsgpldmsbsr; + u32 pex1rdmmsgrqsr; + u32 pex2rdmmsgrqsr; + u32 spimsiclrcr; + u32 pex1mscportsr; + u32 pex2mscportsr; + u32 pex2pmwrcr; + u32 resv5[24]; + u32 mac1_streamid; + u32 mac2_streamid; + u32 mac3_streamid; + u32 pex1_streamid; + u32 pex2_streamid; + u32 dma_streamid; + u32 sata_streamid; + u32 usb3_streamid; + u32 qe_streamid; + u32 sdhc_streamid; + u32 adma_streamid; + u32 letechsftrstcr; + u32 core0_sft_rst; + u32 core1_sft_rst; + u32 resv6[1]; + u32 usb_hi_addr; + u32 etsecclkadjcr; + u32 sai_clk; + u32 resv7[1]; + u32 dcu_streamid; + u32 usb2_streamid; + u32 ftm_reset; + u32 altcbar; + u32 qspi_cfg; + u32 pmcintecr; + u32 pmcintlecr; + u32 pmcintsr; + u32 qos1; + u32 qos2; + u32 qos3; + u32 cci_cfg; + u32 resv8[1]; + u32 etsecdmamcr; + u32 usb3prm3cr; + u32 resv9[1]; + u32 debug_streamid; + u32 resv10[5]; + u32 snpcnfgcr; + u32 resv11[1]; + u32 intpcr; + u32 resv12[20]; + u32 scfgrevcr; + u32 coresrencr; + u32 pex2pmrdsr; + u32 ddrc1cr; + u32 ddrc2cr; + u32 ddrc3cr; + u32 ddrc4cr; + u32 ddrgcr; + u32 resv13[120]; + u32 qeioclkcr; + u32 etsecmcr; + u32 sdhciovserlcr; + u32 resv14[61]; + u32 sparecr[8]; +}; + +/* Clocking */ +struct ccsr_clk { + struct { + u32 clkcncsr; /* core cluster n clock control status */ + u8 res_004[0x1c]; + } clkcsr[2]; + u8 res_040[0x7c0]; /* 0x100 */ + struct { + u32 pllcngsr; + u8 res_804[0x1c]; + } pllcgsr[2]; + u8 res_840[0x1c0]; + u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ + u8 res_a04[0x1fc]; + u32 pllpgsr; /* 0xc00 Platform PLL General Status */ + u8 res_c04[0x1c]; + u32 plldgsr; /* 0xc20 DDR PLL General Status */ + u8 res_c24[0x3dc]; +}; + +/* System Counter */ +struct sctr_regs { + u32 cntcr; + u32 cntsr; + u32 cntcv1; + u32 cntcv2; + u32 resv1[4]; + u32 cntfid0; + u32 cntfid1; + u32 resv2[1002]; + u32 counterid[12]; +}; + +#define MAX_SERDES 1 +#define SRDS_MAX_LANES 4 +#define SRDS_MAX_BANK 2 + +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 +#define SRDS_RSTCTL_SWRST 0x10000000 +#define SRDS_RSTCTL_SDEN 0x00000020 +#define SRDS_RSTCTL_SDRST_B 0x00000040 +#define SRDS_RSTCTL_PLLRST_B 0x00000080 +#define SRDS_PLLCR0_POFF 0x80000000 +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 +#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 +#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 +#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 +#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_PLL_LCK 0x00800000 +#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 +#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 +#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 +#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 +#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 +#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 + +struct ccsr_serdes { + struct { + u32 rstctl; /* Reset Control Register */ + + u32 pllcr0; /* PLL Control Register 0 */ + + u32 pllcr1; /* PLL Control Register 1 */ + u32 res_0c; /* 0x00c */ + u32 pllcr3; + u32 pllcr4; + u8 res_18[0x20-0x18]; + } bank[2]; + u8 res_40[0x90-0x40]; + u32 srdstcalcr; /* 0x90 TX Calibration Control */ + u8 res_94[0xa0-0x94]; + u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ + u8 res_a4[0xb0-0xa4]; + u32 srdsgr0; /* 0xb0 General Register 0 */ + u8 res_b4[0xe0-0xb4]; + u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ + u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ + u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ + u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ + u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ + u8 res_f4[0x100-0xf4]; + struct { + u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u8 res_104[0x120-0x104]; + } srdslnpssr[4]; + u8 res_180[0x300-0x180]; + u32 srdspexeqcr; + u32 srdspexeqpcr[11]; + u8 res_330[0x400-0x330]; + u32 srdspexapcr; + u8 res_404[0x440-0x404]; + u32 srdspexbpcr; + u8 res_444[0x800-0x444]; + struct { + u32 gcr0; /* 0x800 General Control Register 0 */ + u32 gcr1; /* 0x804 General Control Register 1 */ + u32 gcr2; /* 0x808 General Control Register 2 */ + u32 sscr0; + u32 recr0; /* 0x810 Receive Equalization Control */ + u32 recr1; + u32 tecr0; /* 0x818 Transmit Equalization Control */ + u32 sscr1; + u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ + u8 res_824[0x83c-0x824]; + u32 tcsr3; + } lane[4]; /* Lane A, B, C, D, E, F, G, H */ + u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ +}; + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 + +/* DDR memory controller registers */ +struct ccsr_ddr { + u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ + u32 resv1[1]; + u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ + u32 resv2[1]; + u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ + u32 resv3[1]; + u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ + u32 resv4[25]; + u32 cs0_config; /* Chip Select Configuration */ + u32 cs1_config; /* Chip Select Configuration */ + u32 cs2_config; /* Chip Select Configuration */ + u32 cs3_config; /* Chip Select Configuration */ + u32 resv5[12]; + u32 cs0_config_2; /* Chip Select Configuration 2 */ + u32 cs1_config_2; /* Chip Select Configuration 2 */ + u32 cs2_config_2; /* Chip Select Configuration 2 */ + u32 cs3_config_2; /* Chip Select Configuration 2 */ + u32 resv6[12]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ + u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ + u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ + u32 sdram_data_init; /* SDRAM Data initialization */ + u32 resv7[1]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u32 resv8[5]; + u32 init_addr; /* training init addr */ + u32 init_ext_addr; /* training init extended addr */ + u32 resv9[4]; + u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ + u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ + u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ + u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ + u32 ddr_zq_cntl; /* ZQ calibration control*/ + u32 ddr_wrlvl_cntl; /* write leveling control*/ + u32 resv10[1]; + u32 ddr_sr_cntr; /* self refresvh counter */ + u32 ddr_sdram_rcw_1; /* Control Words 1 */ + u32 ddr_sdram_rcw_2; /* Control Words 2 */ + u32 resv11[2]; + u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ + u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ + u32 resv12[2]; + u32 ddr_sdram_rcw_3; /* Control Words 3 */ + u32 ddr_sdram_rcw_4; /* Control Words 4 */ + u32 ddr_sdram_rcw_5; /* Control Words 5 */ + u32 ddr_sdram_rcw_6; /* Control Words 6 */ + u32 resv13[20]; + u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ + u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ + u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ + u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ + u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ + u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ + u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ + u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ + u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ + u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ + u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ + u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ + u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ + u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ + u32 resv14[4]; + u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ + u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ + u32 resv15[2]; + u32 sdram_cfg_3; /* SDRAM Control Configuration 3 */ + u32 resv16[15]; + u32 deskew_cntl; /* SDRAM Deskew Control */ + u32 resv17[545]; + u32 ddr_dsr1; /* Debug Status 1 */ + u32 ddr_dsr2; /* Debug Status 2 */ + u32 ddr_cdr1; /* Control Driver 1 */ + u32 ddr_cdr2; /* Control Driver 2 */ + u32 resv18[50]; + u32 ip_rev1; /* IP Block Revision 1 */ + u32 ip_rev2; /* IP Block Revision 2 */ + u32 eor; /* Enhanced Optimization Register */ + u32 resv19[63]; + u32 mtcr; /* Memory Test Control Register */ + u32 resv20[7]; + u32 mtp1; /* Memory Test Pattern 1 */ + u32 mtp2; /* Memory Test Pattern 2 */ + u32 mtp3; /* Memory Test Pattern 3 */ + u32 mtp4; /* Memory Test Pattern 4 */ + u32 mtp5; /* Memory Test Pattern 5 */ + u32 mtp6; /* Memory Test Pattern 6 */ + u32 mtp7; /* Memory Test Pattern 7 */ + u32 mtp8; /* Memory Test Pattern 8 */ + u32 mtp9; /* Memory Test Pattern 9 */ + u32 mtp10; /* Memory Test Pattern 10 */ + u32 resv21[6]; + u32 ddr_mt_st_ext_addr; /* Memory Test Start Extended Address */ + u32 ddr_mt_st_addr; /* Memory Test Start Address */ + u32 ddr_mt_end_ext_addr; /* Memory Test End Extended Address */ + u32 ddr_mt_end_addr; /* Memory Test End Address */ + u32 resv22[36]; + u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ + u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ + u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ + u32 resv23[5]; + u32 capture_data_hi; /* Data Path Read Capture High */ + u32 capture_data_lo; /* Data Path Read Capture Low */ + u32 capture_ecc; /* Data Path Read Capture ECC */ + u32 resv24[5]; + u32 err_detect; /* Error Detect */ + u32 err_disable; /* Error Disable */ + u32 err_int_en; + u32 capture_attributes; /* Error Attrs Capture */ + u32 capture_address; /* Error Addr Capture */ + u32 capture_ext_address; /* Error Extended Addr Capture */ + u32 err_sbe; /* Single-Bit ECC Error Management */ + u32 resv25[105]; +}; + +#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 +#define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 + +/* CCI-400 registers */ +struct ccsr_cci400 { + u32 ctrl_ord; /* Control Override */ + u32 spec_ctrl; /* Speculation Control */ + u32 secure_access; /* Secure Access */ + u32 status; /* Status */ + u32 impr_err; /* Imprecise Error */ + u8 res_14[0x100 - 0x14]; + u32 pmcr; /* Performance Monitor Control */ + u8 res_104[0xfd0 - 0x104]; + u32 pid[8]; /* Peripheral ID */ + u32 cid[4]; /* Component ID */ + struct { + u32 snoop_ctrl; /* Snoop Control */ + u32 sha_ord; /* Shareable Override */ + u8 res_1008[0x1100 - 0x1008]; + u32 rc_qos_ord; /* read channel QoS Value Override */ + u32 wc_qos_ord; /* read channel QoS Value Override */ + u8 res_1108[0x110c - 0x1108]; + u32 qos_ctrl; /* QoS Control */ + u32 max_ot; /* Max OT */ + u8 res_1114[0x1130 - 0x1114]; + u32 target_lat; /* Target Latency */ + u32 latency_regu; /* Latency Regulation */ + u32 qos_range; /* QoS Range */ + u8 res_113c[0x2000 - 0x113c]; + } slave[5]; /* Slave Interface */ + u8 res_6000[0x9004 - 0x6000]; + u32 cycle_counter; /* Cycle counter */ + u32 count_ctrl; /* Count Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_9010[0xa000 - 0x9010]; + struct { + u32 event_select; /* Event Select */ + u32 event_count; /* Event Count */ + u32 counter_ctrl; /* Counter Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_a010[0xb000 - 0xa010]; + } pcounter[4]; /* Performance Counter */ + u8 res_e004[0x10000 - 0xe004]; +}; +#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h new file mode 100644 index 0000000000..f9cd75b021 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/imx-regs.h @@ -0,0 +1,53 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#ifdef CONFIG_LPUART_32B_REG +struct lpuart_fsl { + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#else +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; +#endif + +#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h new file mode 100644 index 0000000000..abd70fc706 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -0,0 +1,17 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_STREAM_ID_H_ +#define __FSL_LS102XA_STREAM_ID_H_ + +struct smmu_stream_id { + uint16_t offset; + uint16_t stream_id; + char dev_name[32]; +}; + +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h new file mode 100644 index 0000000000..b53f69951a --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_NS_ACCESS_H_ +#define __FSL_NS_ACCESS_H_ + +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, + CSU_S_SUP_R = 0x02, + CSU_S_SUP_W = 0x20, + CSU_S_SUP_RW = 0x22, + CSU_S_USER_R = 0x01, + CSU_S_USER_W = 0x10, + CSU_S_USER_RW = 0x11, + CSU_ALL_RW = 0xff, +}; + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB3, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI2 = 40, + CSU_CSLX_DSPI1, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_2D_ACE, + CSU_CSLX_IFC, + CSU_CSLX_I2C1, + CSU_CSLX_USB2, + CSU_CSLX_I2C3, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_RESERVED0, + CSU_CSLX_ETSEC1, + CSU_CSLX_SEC5_5, + CSU_CSLX_ETSEC3, + CSU_CSLX_ETSEC2, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_ASRC, + CSU_CSLX_SPDIF, + CSU_CSLX_FLEXCAN2, + CSU_CSLX_FLEXCAN1, + CSU_CSLX_FLEXCAN4 = 80, + CSU_CSLX_FLEXCAN3, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, + CSU_CSLX_FTM2, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_COP_DCSR, + CSU_CSLX_EPU, + CSU_CSLX_GDI, + CSU_CSLX_DDI, + CSU_CSLX_RESERVED1, + CSU_CSLX_USB3_PHY = 117, + CSU_CSLX_RESERVED2, + CSU_CSLX_MAX, +}; + +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num); + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h new file mode 100644 index 0000000000..26e4ea134b --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/spl.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONENAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10 + +#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h index c0e3f206cd..42a52bc36c 100644 --- a/arch/arm/include/asm/arch-mb86r0x/hardware.h +++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h @@ -9,7 +9,7 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include +#include #include #endif diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h new file mode 100644 index 0000000000..e512dcec16 --- /dev/null +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Derived from drivers/spi/mpc8xxx_spi.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KW_SPI_H__ +#define __KW_SPI_H__ + +/* SPI Registers on kirkwood SOC */ +struct kwspi_registers { + u32 ctrl; /* 0x10600 */ + u32 cfg; /* 0x10604 */ + u32 dout; /* 0x10608 */ + u32 din; /* 0x1060c */ + u32 irq_cause; /* 0x10610 */ + u32 irq_mask; /* 0x10614 */ +}; + +/* They are used to define CONFIG_SYS_KW_SPI_MPP + * each of the below #defines selects which mpp is + * configured for each SPI signal in spi_claim_bus + * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) + * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) + * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) + */ +#define MOSI_MPP6 (1 << 0) +#define SCK_MPP10 (1 << 1) +#define MISO_MPP11 (1 << 2) + +#define KWSPI_CLKPRESCL_MASK 0x1f +#define KWSPI_CLKPRESCL_MIN 0x12 +#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ +#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ +#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ +#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ +#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ +#define KWSPI_XFERLEN_1BYTE 0 +#define KWSPI_XFERLEN_2BYTE (1 << 5) +#define KWSPI_XFERLEN_MASK (1 << 5) +#define KWSPI_ADRLEN_1BYTE 0 +#define KWSPI_ADRLEN_2BYTE (1 << 8) +#define KWSPI_ADRLEN_3BYTE (2 << 8) +#define KWSPI_ADRLEN_4BYTE (3 << 8) +#define KWSPI_ADRLEN_MASK (3 << 8) +#define KWSPI_TIMEOUT 10000 + +#endif /* __KW_SPI_H__ */ diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index a17f828342..3dffa4a396 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -161,6 +161,126 @@ struct aips_regs { u32 mpr_0_7; u32 mpr_8_15; }; +/* LCD controller registers */ +struct lcdc_regs { + u32 lssar; /* Screen Start Address */ + u32 lsr; /* Size */ + u32 lvpwr; /* Virtual Page Width */ + u32 lcpr; /* Cursor Position */ + u32 lcwhb; /* Cursor Width Height and Blink */ + u32 lccmr; /* Color Cursor Mapping */ + u32 lpcr; /* Panel Configuration */ + u32 lhcr; /* Horizontal Configuration */ + u32 lvcr; /* Vertical Configuration */ + u32 lpor; /* Panning Offset */ + u32 lscr; /* Sharp Configuration */ + u32 lpccr; /* PWM Contrast Control */ + u32 ldcr; /* DMA Control */ + u32 lrmcr; /* Refresh Mode Control */ + u32 licr; /* Interrupt Configuration */ + u32 lier; /* Interrupt Enable */ + u32 lisr; /* Interrupt Status */ + u32 res0[3]; + u32 lgwsar; /* Graphic Window Start Address */ + u32 lgwsr; /* Graphic Window Size */ + u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ + u32 lgwpor; /* Graphic Window Panning Offset */ + u32 lgwpr; /* Graphic Window Position */ + u32 lgwcr; /* Graphic Window Control */ + u32 lgwdcr; /* Graphic Window DMA Control */ + u32 res1[5]; + u32 lauscr; /* AUS Mode Control */ + u32 lausccr; /* AUS mode Cursor Control */ + u32 res2[31 + 64*7]; + u32 bglut; /* Background Lookup Table */ + u32 gwlut; /* Graphic Window Lookup Table */ +}; + +/* Wireless External Interface Module Registers */ +struct weim_regs { + u32 cscr0u; /* Chip Select 0 Upper Register */ + u32 cscr0l; /* Chip Select 0 Lower Register */ + u32 cscr0a; /* Chip Select 0 Addition Register */ + u32 pad0; + u32 cscr1u; /* Chip Select 1 Upper Register */ + u32 cscr1l; /* Chip Select 1 Lower Register */ + u32 cscr1a; /* Chip Select 1 Addition Register */ + u32 pad1; + u32 cscr2u; /* Chip Select 2 Upper Register */ + u32 cscr2l; /* Chip Select 2 Lower Register */ + u32 cscr2a; /* Chip Select 2 Addition Register */ + u32 pad2; + u32 cscr3u; /* Chip Select 3 Upper Register */ + u32 cscr3l; /* Chip Select 3 Lower Register */ + u32 cscr3a; /* Chip Select 3 Addition Register */ + u32 pad3; + u32 cscr4u; /* Chip Select 4 Upper Register */ + u32 cscr4l; /* Chip Select 4 Lower Register */ + u32 cscr4a; /* Chip Select 4 Addition Register */ + u32 pad4; + u32 cscr5u; /* Chip Select 5 Upper Register */ + u32 cscr5l; /* Chip Select 5 Lower Register */ + u32 cscr5a; /* Chip Select 5 Addition Register */ + u32 pad5; + u32 wcr; /* WEIM Configuration Register */ +}; + +/* Multi-Master Memory Interface */ +struct m3if_regs { + u32 ctl; /* Control Register */ + u32 wcfg0; /* Watermark Configuration Register 0 */ + u32 wcfg1; /* Watermark Configuration Register1 */ + u32 wcfg2; /* Watermark Configuration Register2 */ + u32 wcfg3; /* Watermark Configuration Register 3 */ + u32 wcfg4; /* Watermark Configuration Register 4 */ + u32 wcfg5; /* Watermark Configuration Register 5 */ + u32 wcfg6; /* Watermark Configuration Register 6 */ + u32 wcfg7; /* Watermark Configuration Register 7 */ + u32 wcsr; /* Watermark Control and Status Register */ + u32 scfg0; /* Snooping Configuration Register 0 */ + u32 scfg1; /* Snooping Configuration Register 1 */ + u32 scfg2; /* Snooping Configuration Register 2 */ + u32 ssr0; /* Snooping Status Register 0 */ + u32 ssr1; /* Snooping Status Register 1 */ + u32 res0; + u32 mlwe0; /* Master Lock WEIM CS0 Register */ + u32 mlwe1; /* Master Lock WEIM CS1 Register */ + u32 mlwe2; /* Master Lock WEIM CS2 Register */ + u32 mlwe3; /* Master Lock WEIM CS3 Register */ + u32 mlwe4; /* Master Lock WEIM CS4 Register */ + u32 mlwe5; /* Master Lock WEIM CS5 Register */ +}; + +/* Pulse width modulation */ +struct pwm_regs { + u32 cr; /* Control Register */ + u32 sr; /* Status Register */ + u32 ir; /* Interrupt Register */ + u32 sar; /* Sample Register */ + u32 pr; /* Period Register */ + u32 cnr; /* Counter Register */ +}; + +/* Enhanced Periodic Interrupt Timer */ +struct epit_regs { + u32 cr; /* Control register */ + u32 sr; /* Status register */ + u32 lr; /* Load register */ + u32 cmpr; /* Compare register */ + u32 cnr; /* Counter register */ +}; + +/* CSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 intr; + u32 dma; + u32 stat; + u32 period; + u32 test; +}; #endif @@ -289,6 +409,8 @@ struct aips_regs { #define CCM_PERCLK_MASK 0x3f #define CCM_RCSR_NF_16BIT_SEL (1 << 14) #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) +#define CCM_CRDR_BT_UART_SRC_SHIFT 29 +#define CCM_CRDR_BT_UART_SRC_MASK 7 /* ESDRAM Controller register bitfields */ #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) @@ -345,12 +467,65 @@ struct aips_regs { #define WSR_UNLOCK1 0x5555 #define WSR_UNLOCK2 0xAAAA +/* MAX bits */ +#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) + +/* M3IF bits */ +#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) + +/* WEIM bits */ +/* 13 fields of the upper CS control register */ +#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \ + (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \ + (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + /* Names used in GPIO driver */ #define GPIO1_BASE_ADDR IMX_GPIO1_BASE #define GPIO2_BASE_ADDR IMX_GPIO2_BASE #define GPIO3_BASE_ADDR IMX_GPIO3_BASE #define GPIO4_BASE_ADDR IMX_GPIO4_BASE +/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + IMX_CSPI1_BASE, \ + IMX_CSPI2_BASE, \ + IMX_CSPI3_BASE + #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 #define CHIP_REV_1_2 0x12 diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index a27145ba28..92c847e44a 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -169,7 +169,7 @@ struct iim_regs { struct fuse_bank { u32 fuse_regs[0x20]; u32 fuse_rsvd[0xe0]; - } bank[1]; + } bank[2]; }; struct fuse_bank0_regs { @@ -209,9 +209,13 @@ struct fuse_bank0_regs { #define IIM_BASE_ADDR IMX_IIM_BASE #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) +#define IMX_NFC_BASE (0xD8000000) #define IMX_ESD_BASE (0xD8001000) #define IMX_WEIM_BASE (0xD8002000) +#define NFC_BASE_ADDR IMX_NFC_BASE + + /* FMCR System Control bit definition*/ #define UART4_RXD_CTL (1 << 25) #define UART4_RTS_CTL (1 << 24) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index f23350e5c2..71ebd243d7 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -909,9 +909,19 @@ struct esdc_regs { #define MXC_CSPIPERIOD_32KHZ (1 << 15) #define MAX_SPI_BYTES 4 + #define MXC_SPI_BASE_ADDRESSES \ 0x43fa4000, \ 0x50010000, \ 0x53f84000, +/* + * Generic timer support + */ +#ifdef CONFIG_MX31_CLK32 +#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 +#else +#define CONFIG_SYS_TIMER_RATE 32768 +#endif + #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index b5300291a9..28a47ed44d 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -372,4 +372,16 @@ struct aips_regs { #define CCM_RCSR_NF_16BIT_SEL (1 << 14) #endif + +/* + * Generic timer support + */ +#ifdef CONFIG_MX35_CLK32 +#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32 +#else +#define CONFIG_SYS_TIMER_RATE 32768 +#endif + +#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36) + #endif /* __ASM_ARCH_MX35_H */ diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h deleted file mode 100644 index f87c137c98..0000000000 --- a/arch/arm/include/asm/arch-mx35/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 7 -#define BOOT_DEVICE_NOR 8 -#define BOOT_DEVICE_I2C 9 -#define BOOT_DEVICE_SPI 10 - -#endif diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 47f4c0e276..18b18b0dc7 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -97,18 +97,19 @@ unsigned int mxc_get_clock(enum mxc_clock clk); int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk); int adjust_core_voltage(u32 freq); void set_usb_phy_clk(void); -void enable_usb_phy1_clk(unsigned char enable); -void enable_usb_phy2_clk(unsigned char enable); +void enable_usb_phy1_clk(bool enable); +void enable_usb_phy2_clk(bool enable); void set_usboh3_clk(void); -void enable_usboh3_clk(unsigned char enable); +void enable_usboh3_clk(bool enable); void mxc_set_sata_internal_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_nfc_clk(unsigned char enable); +void enable_efuse_prog_supply(bool enable); void ipu_clk_enable(void); void ipu_clk_disable(void); void ipu_di_clk_enable(int di); void ipu_di_clk_disable(int di); -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 void ldb_clk_enable(int ldb); void ldb_clk_disable(int ldb); #else @@ -118,6 +119,6 @@ static inline void ldb_clk_enable(int ldb) static inline void ldb_clk_disable(int ldb) { } -#endif /* CONFIG_MX53 */ +#endif /* CONFIG_SOC_MX53 */ #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index 824d851804..f62bf224f2 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -60,7 +60,7 @@ struct mxc_ccm_reg { u32 CCGR4; u32 CCGR5; u32 CCGR6; /* 0x0080 */ -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 u32 CCGR7; /* 0x0084 */ #endif u32 cmeor; @@ -68,12 +68,12 @@ struct mxc_ccm_reg { /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (0x1 << 12) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCR_FPM_MULT (0x1 << 11) #endif #define MXC_CCM_CCR_CAMP2_EN (0x1 << 10) #define MXC_CCM_CCR_CAMP1_EN (0x1 << 9) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCR_FPM_EN (0x1 << 8) #endif #define MXC_CCM_CCR_OSCNT_OFFSET 0 @@ -82,9 +82,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF) /* Define the bits in register CCSR */ -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCSR_LP_APM (0x1 << 9) -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) #define MXC_CCM_CCSR_LP_APM (0x1 << 10) #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) #endif @@ -305,6 +305,9 @@ struct mxc_ccm_reg { /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21) +/* Define the bits in register CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) + /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 #define MXC_CCM_CCGR_CG_OFF 0x0 @@ -366,12 +369,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) #define MXC_CCM_CCGR1_I2C2_OFFSET 20 #define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 #define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 #define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) #define MXC_CCM_CCGR1_I2C3_OFFSET 22 #define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) #endif @@ -382,7 +385,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR1_SCC_OFFSET 30 #define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 #define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) #endif @@ -452,12 +455,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR4_PATA_OFFSET 0 #define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 #define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 #define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) #define MXC_CCM_CCGR4_SATA_OFFSET 2 #define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 @@ -500,10 +503,10 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) #define MXC_CCM_CCGR5_IPU_OFFSET 10 #define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 #define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) #define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 #define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) #endif @@ -521,14 +524,14 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) #define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 #define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 #define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) #endif #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 #define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) -#if defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX53) #define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 #define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) #define MXC_CCM_CCGR6_OCRAM_OFFSET 2 @@ -536,12 +539,12 @@ struct mxc_ccm_reg { #endif #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 #define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 #define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) #define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 #define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) #define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 #define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) #endif @@ -551,7 +554,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) #define MXC_CCM_CCGR6_GPU2D_OFFSET 14 #define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) -#if defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX53) #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 #define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 diff --git a/arch/arm/include/asm/arch-mx5/hab.h b/arch/arm/include/asm/arch-mx5/hab.h new file mode 100644 index 0000000000..c71f664114 --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/hab.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + * +*/ + +#ifndef __ARCH_MX5_HAB_H +#define __ARCH_MX5_HAB_H + +#ifdef CONFIG_SECURE_BOOT + +#include + +int get_hab_status(void); + +/* -------- start of HAB API updates ------------*/ +/* The following are taken from HAB4 SIS */ + +/* Status definitions */ +typedef enum hab_status { + HAB_STS_ANY = 0x00, + HAB_FAILURE = 0x33, + HAB_WARNING = 0x69, + HAB_SUCCESS = 0xf0 +} hab_status_t; + +/* Security Configuration definitions */ +typedef enum hab_config { + HAB_CFG_RETURN = 0x33, /**< Field Return IC */ + HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */ + HAB_CFG_CLOSED = 0xcc /**< Secure IC */ +} hab_config_t; + +/* State definitions */ +typedef enum hab_state { + HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */ + HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */ + HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */ + HAB_STATE_TRUSTED = 0x99, /**< Trusted state */ + HAB_STATE_SECURE = 0xaa, /**< Secure state */ + HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */ + HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */ + HAB_STATE_NONE = 0xf0, /**< No security state machine */ + HAB_STATE_MAX +} hab_state_t; + +typedef enum hab_target { + HAB_TGT_MEMORY = 0x0f, /* Check memory white list */ + HAB_TGT_PERIPHERAL = 0xf0, /* Check peripheral white list*/ +} hab_target_t; + +enum HAB_FUNC_OFFSETS { + HAB_RVT_HEADER, + HAB_RVT_ENTRY, + HAB_RVT_EXIT, + HAB_RVT_CHECK_TARGET, + HAB_RVT_AUTHENTICATE_IMAGE, + HAB_RVT_RUN_DCD, + HAB_RVT_RUN_CSF, + HAB_RVT_ASSERT, + HAB_RVT_REPORT_EVENT, + HAB_RVT_REPORT_STATUS, + HAB_RVT_FAILSAFE, +}; + +/* Function prototype description */ +typedef hab_status_t hab_rvt_entry_t(void); + +typedef hab_status_t hab_rvt_exit_t(void); + +typedef hab_status_t hab_rvt_check_target_t(hab_target_t, const void *, + size_t); + +typedef hab_status_t hab_loader_callback_f_t(void**, size_t*, const void*); +typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, + void **, size_t *, hab_loader_callback_f_t); + +typedef hab_status_t hab_rvt_assert_t(uint32_t, const void *, + size_t); + +typedef hab_status_t hab_rvt_report_event_t(hab_status_t, uint32_t, + uint8_t* , size_t*); + +typedef hab_status_t hab_rvt_report_status_t(enum hab_config *, + enum hab_state *); + +typedef void hapi_clock_init_t(void); + +#define HAB_RVT_BASE 0x00000094 + +static inline void **hab_rvt_base(void) +{ + uint32_t *base = (void *)0x94; + + if ((*base & 0xff0000ff) != cpu_to_be32(0xdd000040)) { + printf("Invalid RVT @ %p\n", base); + hang(); + } + return (void **)base; +} + +#define HAB_CID_ROM 0 /**< ROM Caller ID */ +#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ +/* ----------- end of HAB API updates ------------*/ + +#define hab_rvt_entry_p \ + ((hab_rvt_entry_t *)hab_rvt_base()[HAB_RVT_ENTRY]) + +#define hab_rvt_exit_p \ + ((hab_rvt_exit_t *)hab_rvt_base()[HAB_RVT_EXIT]) + +#define hab_rvt_check_target_p \ + ((hab_rvt_check_target_t*)hab_rvt_base()[HAB_RVT_CHECK_TARGET]) + +#define hab_rvt_authenticate_image_p \ + ((hab_rvt_authenticate_image_t *)hab_rvt_base()[HAB_RVT_AUTHENTICATE_IMAGE]) + +#define hab_rvt_assert_p \ + ((hab_rvt_assert_t*)hab_rvt_base()[HAB_RVT_ASSERT]) + +#define hab_rvt_report_event_p \ + ((hab_rvt_report_event_t*)hab_rvt_base()[HAB_RVT_REPORT_EVENT]) + +#define hab_rvt_report_status_p \ + ((hab_rvt_report_status_t*)hab_rvt_base()[HAB_RVT_REPORT_STATUS]) + +#define HAB_FUNC(n, rt) \ +static inline rt hab_rvt_##n(void) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(); \ +} \ + +#define HAB_FUNC2(n, rt, t1, t2) \ +static inline rt hab_rvt_##n(t1 p1, t2 p2) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1, p2); \ +} + +#define HAB_FUNC3(n, rt, t1, t2, t3) \ +static inline rt hab_rvt_##n(t1 p1, t2 p2, t3 p3) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1, p2, p3); \ +} + +#define HAB_FUNC4(n, rt, t1, t2, t3, t4) \ +static inline rt hab_rvt_##n(t1 p1, t2 p2, t3 p3, t4 p4) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1, p2, p3, p4); \ +} + +#define HAB_FUNC5(n, rt, t1, t2, t3, t4, t5) \ +static inline rt hab_rvt_##n(t1 p1, t2 p2, t3 p3, t4 p4, t5 p5) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1, p2, p3, p4, p5); \ +} + +#else /* CONFIG_SECURE_BOOT */ + +static inline int get_hab_status(void) +{ + return 0; +} + +#endif /* CONFIG_SECURE_BOOT */ +#endif /* __ARCH_MX5_HAB_H */ diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d9a7018a00..6335c07daf 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,7 +9,7 @@ #define ARCH_MXC -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 #define SPBA0_BASE_ADDR 0x70000000 @@ -19,7 +19,7 @@ #define CSD1_BASE_ADDR 0xA0000000 #define NFC_BASE_ADDR_AXI 0xCFFF0000 #define CS1_BASE_ADDR 0xB8000000 -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) #define IPU_SOC_BASE_ADDR 0x00000000 #define SPBA0_BASE_ADDR 0x50000000 #define AIPS1_BASE_ADDR 0x53F00000 @@ -76,7 +76,7 @@ #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) -#if defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX53) #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) @@ -89,7 +89,7 @@ #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) #endif #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) @@ -122,7 +122,7 @@ #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) -#if defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX53) #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) #endif @@ -200,21 +200,6 @@ */ #define WBED 1 -/* - * WEIM WCR - */ -#define BCM 1 -#define GBCD(x) (((x) & 0x3) << 1) -#define INTEN (1 << 4) -#define INTPOL (1 << 5) -#define WDOG_EN (1 << 8) -#define WDOG_LIMIT(x) (((x) & 0x3) << 9) - -#define CS0_128 0 -#define CS0_64M_CS1_64M 1 -#define CS0_64M_CS1_32M_CS2_32M 2 -#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 - /* * CSPI register definitions */ @@ -238,9 +223,10 @@ #define MXC_CSPICTRL_CHAN 18 /* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL 4 -#define MXC_CSPICON_PHA 0 -#define MXC_CSPICON_SSPOL 12 +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #define MXC_SPI_BASE_ADDRESSES \ CSPI1_BASE_ADDR, \ CSPI2_BASE_ADDR, \ @@ -367,7 +353,7 @@ struct clkctl { u32 ccgr4; u32 ccgr5; u32 ccgr6; -#if defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX53) u32 ccgr7; #endif u32 cmeor; @@ -431,21 +417,18 @@ struct weim { u32 ear; }; -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) struct iomuxc { - u32 gpr0; - u32 gpr1; + u32 gpr[2]; u32 omux0; u32 omux1; u32 omux2; u32 omux3; u32 omux4; }; -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) struct iomuxc { - u32 gpr0; - u32 gpr1; - u32 gpr2; + u32 gpr[3]; u32 omux0; u32 omux1; u32 omux2; @@ -514,9 +497,9 @@ struct iim_regs { struct fuse_bank { u32 fuse_regs[0x20]; u32 fuse_rsvd[0xe0]; -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) } bank[4]; -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) } bank[5]; #endif }; @@ -525,9 +508,9 @@ struct fuse_bank0_regs { u32 fuse0_7[8]; u32 uid[8]; u32 fuse16_23[8]; -#if defined(CONFIG_MX51) +#if defined(CONFIG_SOC_MX51) u32 imei[8]; -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) u32 gp[8]; #endif }; @@ -538,7 +521,7 @@ struct fuse_bank1_regs { u32 fuse15_31[0x11]; }; -#if defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX53) struct fuse_bank4_regs { u32 fuse0_4[5]; u32 gp[3]; diff --git a/arch/arm/include/asm/arch-mx5/spl.h b/arch/arm/include/asm/arch-mx5/spl.h deleted file mode 100644 index 20c6cae938..0000000000 --- a/arch/arm/include/asm/arch-mx5/spl.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2013 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_SPL_H__ -#define __ASM_ARCH_SPL_H__ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_NAND 1 - -#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index b164ec4f4e..4a6ba21bd6 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -8,12 +8,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 +#include "../arch-imx/cpu.h" #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index a50a40e046..1b6c140c20 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -42,6 +42,12 @@ enum mxc_clock { MXC_I2C_CLK, }; +enum enet_freq { + ENET_25MHZ, + ENET_50MHZ, + ENET_100MHZ, + ENET_125MHZ, +}; struct clk { const char *name; @@ -93,10 +99,23 @@ u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk); +void setup_gpmi_io_clk(u32 cfg); +void hab_caam_clock_enable(unsigned char enable); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); +void enable_uart_clk(unsigned char enable); +int enable_cspi_clock(unsigned char enable, unsigned spi_num); +int enable_usdhc_clk(unsigned char enable, unsigned bus_num); int enable_sata_clock(void); +void disable_sata_clock(void); +int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +int enable_spi_clk(unsigned char enable, unsigned spi_num); +void enable_ipu_clock(void); +int enable_fec_anatop_clock(enum enet_freq freq); +void enable_enet_clk(unsigned char enable); +void enable_qspi_clk(int qspi_num); +void enable_thermal_clk(void); void ipu_clk_enable(void); void ipu_clk_disable(void); void ipu_di_clk_enable(int di); @@ -105,5 +124,4 @@ void ldb_clk_enable(int ldb); void ldb_clk_disable(int ldb); void ocotp_clk_enable(void); void ocotp_clk_disable(void); - #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index e090f4baab..ce465c6179 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -56,50 +56,6 @@ struct mxc_ccm_reg { u32 CCGR7; u32 cmeor; }; - -struct anatop_regs { - mxs_reg_32(pll_arm); /* 0x000 */ - mxs_reg_32(usb1_pll_480_ctrl); /* 0x010 */ - mxs_reg_32(usb2_pll_480_ctrl); /* 0x020 */ - mxs_reg_32(pll_528); /* 0x030 */ - reg_32(pll_528_ss); /* 0x040 */ - reg_32(pll_528_num); /* 0x050 */ - reg_32(pll_528_denom); /* 0x060 */ - mxs_reg_32(pll_audio); /* 0x070 */ - reg_32(pll_audio_num); /* 0x080 */ - reg_32(pll_audio_denom); /* 0x090 */ - mxs_reg_32(pll_video); /* 0x0a0 */ - reg_32(pll_video_num); /* 0x0b0 */ - reg_32(pll_video_denom); /* 0x0c0 */ - mxs_reg_32(pll_mlb); /* 0x0d0 */ - mxs_reg_32(pll_enet); /* 0x0e0 */ - mxs_reg_32(pfd_480); /* 0x0f0 */ - mxs_reg_32(pfd_528); /* 0x100 */ - mxs_reg_32(reg_1p1); /* 0x110 */ - mxs_reg_32(reg_3p0); /* 0x120 */ - mxs_reg_32(reg_2p5); /* 0x130 */ - mxs_reg_32(reg_core); /* 0x140 */ - mxs_reg_32(ana_misc0); /* 0x150 */ - mxs_reg_32(ana_misc1); /* 0x160 */ - mxs_reg_32(ana_misc2); /* 0x170 */ - mxs_reg_32(tempsense0); /* 0x180 */ - mxs_reg_32(tempsense1); /* 0x190 */ - mxs_reg_32(usb1_vbus_detect); /* 0x1a0 */ - mxs_reg_32(usb1_chrg_detect); /* 0x1b0 */ - mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */ - mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */ - mxs_reg_32(usb1_loopback); /* 0x1e0 */ - mxs_reg_32(usb1_misc); /* 0x1f0 */ - mxs_reg_32(usb2_vbus_detect); /* 0x200 */ - mxs_reg_32(usb2_chrg_detect); /* 0x210 */ - mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */ - mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */ - mxs_reg_32(usb2_loopback); /* 0x240 */ - mxs_reg_32(usb2_misc); /* 0x250 */ - reg_32(digprog); /* 0x260 */ - reg_32(rsrvd); /* 0x270 */ - reg_32(digprog_sololite); /* 0x280 */ -}; #endif /* Define the bits in register CCR */ @@ -109,7 +65,11 @@ struct anatop_regs { #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET) #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) -#define MXC_CCM_CCR_OSCNT_MASK (0xFF << MXC_CCM_CCR_OSCNT_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCR_OSCNT_MASK 0x7F +#else +#define MXC_CCM_CCR_OSCNT_MASK 0xFF +#endif #define MXC_CCM_CCR_OSCNT_OFFSET 0 /* Define the bits in register CCDR */ @@ -142,8 +102,10 @@ struct anatop_regs { #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 +#endif #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET) #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET) @@ -169,28 +131,40 @@ struct anatop_regs { #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 +#endif #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) +#endif #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) +#endif /* Define the bits in register CSCMR1 */ #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) +#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 +#else #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 +#endif #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 +/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) @@ -203,20 +177,41 @@ struct anatop_regs { #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 +#endif +#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX)) +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET) +#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 +#endif #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) /* Define the bits in register CSCMR2 */ +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET) +#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 +#endif #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET) #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET) +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 +#else #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 +#endif /* Define the bits in register CSCDR1 */ +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 +#endif #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) @@ -225,15 +220,20 @@ struct anatop_regs { #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) -#ifdef CONFIG_MX6SL +#endif +#ifdef CONFIG_SOC_MX6SL #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET) #else #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET) +#endif #endif #define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 @@ -241,6 +241,8 @@ struct anatop_regs { /* Define the bits in register CS1CDR */ #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET) +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) @@ -251,6 +253,17 @@ struct anatop_regs { #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 /* Define the bits in register CS2CDR */ +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET) +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET) +#else #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) @@ -260,6 +273,7 @@ struct anatop_regs { #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) +#endif #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) @@ -270,13 +284,16 @@ struct anatop_regs { #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 /* Define the bits in register CDCDR */ +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 -#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) +#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET) +#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28 +#endif #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) @@ -287,29 +304,50 @@ struct anatop_regs { #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 /* Define the bits in register CHSCCDR */ -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET) +#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 +#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET) +#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 +#else +#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 +#endif + +#define CHSCCDR_CLK_SEL_LDB_DI0 3 +#define CHSCCDR_PODF_DIVIDE_BY_3 2 +#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET) +/* All IPU2_DI1 are LCDIF1 on MX6SX */ +#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET) +/* All IPU2_DI0 are LCDIF2 on MX6SX */ +#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3 @@ -329,7 +367,9 @@ struct anatop_regs { /* Define the bits in register CDHIPR */ #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) +#endif #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) @@ -338,14 +378,18 @@ struct anatop_regs { /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) +#endif #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) -#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) +#endif +#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET) #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 @@ -353,15 +397,19 @@ struct anatop_regs { #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) #define MXC_CCM_CLPCR_SBYOS (1 << 6) #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) +#endif #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET) #define MXC_CCM_CLPCR_LPM_OFFSET 0 /* Define the bits in register CISR */ #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) +#endif #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) @@ -372,11 +420,13 @@ struct anatop_regs { /* Define the bits in register CIMR */ #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) +#endif #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) +#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0) @@ -387,6 +437,7 @@ struct anatop_regs { #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET) +#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET) #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 @@ -394,6 +445,7 @@ struct anatop_regs { #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 /* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) @@ -429,8 +481,13 @@ struct anatop_regs { #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 +#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) +#else #define MXC_CCM_CCGR0_DTCP_OFFSET 28 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) +#endif #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) @@ -442,27 +499,48 @@ struct anatop_regs { #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) +#endif #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 +#define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) +#endif #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) +#endif #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 +#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) +#define MXC_CCM_CCGR1_CANFD_OFFSET 30 +#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) +#endif +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) +#else +#define MXC_CCM_CCGR2_CSI_OFFSET 2 +#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) +#endif +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) +#endif #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 @@ -481,17 +559,33 @@ struct anatop_regs { #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR2_LCD_OFFSET 28 +#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) +#define MXC_CCM_CCGR2_PXP_OFFSET 30 +#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) +#else #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) +#endif +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR3_M4_OFFSET 2 +#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) +#define MXC_CCM_CCGR3_ENET_OFFSET 4 +#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) +#define MXC_CCM_CCGR3_QSPI_OFFSET 14 +#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) +#else #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) +#endif #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 @@ -500,29 +594,43 @@ struct anatop_regs { #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR3_QSPI1_OFFSET 14 +#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) +#else #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) +#endif #define MXC_CCM_CCGR3_MLB_OFFSET 18 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) +#endif #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) +#endif #define MXC_CCM_CCGR4_PCIE_OFFSET 0 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 +#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) +#else #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) +#endif #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 @@ -546,8 +654,10 @@ struct anatop_regs { #define MXC_CCM_CCGR5_ROM_OFFSET 0 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) +#ifndef CONFIG_SOC_MX6SX #define MXC_CCM_CCGR5_SATA_OFFSET 4 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) +#endif #define MXC_CCM_CCGR5_SDMA_OFFSET 6 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) #define MXC_CCM_CCGR5_SPBA_OFFSET 12 @@ -564,6 +674,12 @@ struct anatop_regs { #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR5_SAI1_OFFSET 20 +#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) +#define MXC_CCM_CCGR5_SAI2_OFFSET 30 +#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) +#endif #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) @@ -611,12 +727,13 @@ struct anatop_regs { #define BM_ANADIG_PLL_ARM_BYPASS (1 << 16) #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14 #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) -#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \ - (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0) -#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1) -#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2) -#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3) +#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \ + BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR 0x3 #define BM_ANADIG_PLL_ARM_ENABLE (1 << 13) #define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12) #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11) @@ -626,94 +743,41 @@ struct anatop_regs { #define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7) #define BP_ANADIG_PLL_ARM_DIV_SELECT 0 #define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT) -#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \ - (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \ +#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \ BM_ANADIG_PLL_ARM_DIV_SELECT) -#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31) -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16) -#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ - (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \ - BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(0) -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(1) -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(2) -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(3) -#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13) -#define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12) -#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11) -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10) -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9) -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8) -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7) -#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6) -#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 -#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) -#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ - (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \ - BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) -#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 -#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) -#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ - (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \ - BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) - -#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31) -#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16) -#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14 -#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ - (((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) & \ - BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(0) -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1) -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2) -#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3) -#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13) -#define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12) -#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11) -#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10) -#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9) -#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8) -#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7) -#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6) -#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2 -#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) -#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \ - (((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) & \ - BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0) -#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0 -#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) -#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \ - (((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) & \ - BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) - -#define BM_ANADIG_PLL_SYS_LOCK (1 << 31) -#define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19) -#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18) -#define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17) -#define BM_ANADIG_PLL_SYS_BYPASS (1 << 16) -#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) -#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ - (((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_SYS_ENABLE (1 << 13) -#define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12) -#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11) -#define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10) -#define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9) -#define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8) -#define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7) -#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 -#define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT) -#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ - (((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT) +#define BM_ANADIG_PLL_528_CTRL_LOCK (1 << 31) +#define BM_ANADIG_PLL_528_PFD_OFFSET_EN (1 << 18) +#define BM_ANADIG_PLL_528_DITHER_ENABLE (1 << 17) +#define BM_ANADIG_PLL_528_CTRL_BYPASS (1 << 16) +#define BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) & \ + BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_528_CTRL_ENABLE (1 << 13) +#define BM_ANADIG_PLL_528_CTRL_POWER (1 << 12) +#define BM_ANADIG_PLL_528_CTRL_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_528_CTRL_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_528_CTRL_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_528_CTRL_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_528_CTRL_HALF_LF (1 << 7) +#define BM_ANADIG_PLL_528_CTRL_EN_USB_CLKS (1 << 6) +#define BP_ANADIG_PLL_528_CTRL_CONTROL0 2 +#define BM_ANADIG_PLL_528_CTRL_CONTROL0 (0x7 << BP_ANADIG_PLL_528_CTRL_CONTROL0) +#define BF_ANADIG_PLL_528_CTRL_CONTROL0(v) \ + (((v) << BP_ANADIG_PLL_528_CTRL_CONTROL0) & \ + BM_ANADIG_PLL_528_CTRL_CONTROL0) +#define BP_ANADIG_PLL_528_CTRL_DIV_SELECT 0 +#define BM_ANADIG_PLL_528_CTRL_DIV_SELECT (0x3 << BP_ANADIG_PLL_528_CTRL_DIV_SELECT) +#define BF_ANADIG_PLL_528_CTRL_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_528_CTRL_DIV_SELECT) & \ + BM_ANADIG_PLL_528_CTRL_DIV_SELECT) #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31) #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21) @@ -726,7 +790,7 @@ struct anatop_regs { #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16) #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) -#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ +#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 @@ -741,32 +805,37 @@ struct anatop_regs { #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7) #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT) -#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ - (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) +#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \ + BM_ANADIG_PLL_AUDIO_DIV_SELECT) #define BP_ANADIG_PLL_AUDIO_NUM_A 0 -#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ - (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A) +#define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A) +#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \ + BM_ANADIG_PLL_AUDIO_NUM_A) #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 -#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ - (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B) +#define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B) +#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \ + BM_ANADIG_PLL_AUDIO_DENOM_B) #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31) #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21) #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ - (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) +#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & \ + BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17) #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16) #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) -#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ - (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \ + BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 @@ -780,41 +849,49 @@ struct anatop_regs { #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7) #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT) -#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ - (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) +#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \ + BM_ANADIG_PLL_VIDEO_DIV_SELECT) #define BP_ANADIG_PLL_VIDEO_NUM_A 0 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A) -#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ - (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A) +#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \ + BM_ANADIG_PLL_VIDEO_NUM_A) #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B) -#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ - (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B) +#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \ + BM_ANADIG_PLL_VIDEO_DENOM_B) #define BM_ANADIG_PLL_MLB_LOCK (1 << 31) #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26 #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) -#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \ - (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) +#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \ + (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \ + BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23 #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) -#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \ - (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) +#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \ + (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \ + BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20 #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) -#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \ - (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG) +#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \ + (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \ + BM_ANADIG_PLL_MLB_VDDD_DLY_CFG) #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17 #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) -#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \ - (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG) +#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \ + (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \ + BM_ANADIG_PLL_MLB_VDDA_DLY_CFG) #define BM_ANADIG_PLL_MLB_BYPASS (1 << 16) #define BP_ANADIG_PLL_MLB_PHASE_SEL 12 #define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL) -#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \ - (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL) +#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \ + (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \ + BM_ANADIG_PLL_MLB_PHASE_SEL) #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11) #define BM_ANADIG_PLL_ENET_LOCK (1 << 31) @@ -825,8 +902,9 @@ struct anatop_regs { #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16) #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) -#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ - (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \ + BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 @@ -840,145 +918,438 @@ struct anatop_regs { #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7) #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT) -#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ - (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT) +#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \ + BM_ANADIG_PLL_ENET_DIV_SELECT) #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31) #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30) #define BP_ANADIG_PFD_480_PFD3_FRAC 24 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC) #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ - (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & BM_ANADIG_PFD_480_PFD3_FRAC) + (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \ + BM_ANADIG_PFD_480_PFD3_FRAC) #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26 #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) -#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \ - (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) +#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \ + (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \ + BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25) #define BP_ANADIG_ANA_MISC0_ANAMUX 21 #define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX) -#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \ - (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & BM_ANADIG_ANA_MISC0_ANAMUX) +#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \ + (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \ + BM_ANADIG_ANA_MISC0_ANAMUX) #define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20) #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18 #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \ - (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) + (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \ + BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17) -#define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16) -#define BP_ANADIG_ANA_MISC0_OSC_I 14 -#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000 -#define BF_ANADIG_ANA_MISC0_OSC_I(v) \ - (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & BM_ANADIG_ANA_MISC0_OSC_I) +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16) +#define BP_ANADIG_ANA_MISC0_OSC_I 14 +#define BM_ANADIG_ANA_MISC0_OSC_I (0x3 << BP_ANADIG_ANA_MISC0_OSC_I) +#define BF_ANADIG_ANA_MISC0_OSC_I(v) \ + (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \ + BM_ANADIG_ANA_MISC0_OSC_I) #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13) -#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12) +#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12) #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8 -#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300 +#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \ - (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) -#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7) + (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \ + BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7) #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) -#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \ - (((v) << BM_ANADIG_ANA_MISC0_REFTOP_VBGUP) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ) -#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3) -#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2) -#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1) +#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \ + (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \ + BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ) +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3) +#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2) +#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1) #define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0) -#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31) -#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000 -#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000 +#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31) +#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30) +#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO (1 << 29) #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13) -#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) -#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11) -#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11) +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5 -#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0 -#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \ - (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) +#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) +#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \ + (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \ + BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0 -#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F -#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \ - (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) - -#define BP_ANADIG_ANA_MISC2_CONTROL3 30 -#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000 -#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \ - (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & BM_ANADIG_ANA_MISC2_CONTROL3) +#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) +#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \ + (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \ + BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) + +#define BP_ANADIG_ANA_MISC2_CONTROL3 30 +#define BM_ANADIG_ANA_MISC2_CONTROL3 (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3) +#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \ + (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \ + BM_ANADIG_ANA_MISC2_CONTROL3) #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28 -#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000 -#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \ - (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME) +#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) +#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \ + BM_ANADIG_ANA_MISC2_REG2_STEP_TIME) #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26 -#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000 -#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \ - (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME) +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) +#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \ + BM_ANADIG_ANA_MISC2_REG1_STEP_TIME) #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24 -#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000 -#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \ - (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME) -#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000 -#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000 -#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21) +#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) +#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \ + BM_ANADIG_ANA_MISC2_REG0_STEP_TIME) +#define BM_ANADIG_ANA_MISC2_CONTROL2 (1 << 23) +#define BM_ANADIG_ANA_MISC2_REG2_OK (1 << 22) +#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21) #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19) #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16 -#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000 -#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \ - (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET) -#define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15) -#define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14) +#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) +#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \ + BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET) +#define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15) +#define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14) #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13) -#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11) +#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11) #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8 -#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700 -#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \ - (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET) +#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET +#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \ + BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET) #define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7) #define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6) #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5) #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3) #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0 #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) -#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \ - (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET) - -#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 -#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) -#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \ - (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE) -#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 -#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) -#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \ - (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) -#define BM_ANADIG_TEMPSENSE0_TEST (1 << 6) -#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 -#define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ) +#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \ + BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET) + +#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 +#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) +#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \ + (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \ + BM_ANADIG_TEMPSENSE0_ALARM_VALUE) +#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 +#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) +#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \ + (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \ + BM_ANADIG_TEMPSENSE0_TEMP_VALUE) +#define BM_ANADIG_TEMPSENSE0_TEST (1 << 6) +#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 +#define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ) #define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \ - (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & BM_ANADIG_TEMPSENSE0_VBGADJ) -#define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2) -#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1) -#define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0) - -#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 -#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) -#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \ - (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) - -#ifdef CONFIG_MX6Q -#define PLL2_PFD0_FREQ 352000000 -#define PLL2_PFD1_FREQ 594000000 + (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \ + BM_ANADIG_TEMPSENSE0_VBGADJ) +#define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2) +#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1) +#define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0) + +#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 +#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) +#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \ + (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \ + BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) + +#define MXC_CCM_CCGR6_USBOH3_OFFSET 0 +#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) +#define MXC_CCM_CCGR6_USDHC1_OFFSET 2 +#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) +#define MXC_CCM_CCGR6_USDHC2_OFFSET 4 +#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) +#define MXC_CCM_CCGR6_USDHC3_OFFSET 6 +#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) +#define MXC_CCM_CCGR6_USDHC4_OFFSET 8 +#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) +#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 +#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) +#ifdef CONFIG_SOC_MX6SX +#define MXC_CCM_CCGR6_PWM8_OFFSET 16 +#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) +#define MXC_CCM_CCGR6_VADC_OFFSET 20 +#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) +#define MXC_CCM_CCGR6_GIS_OFFSET 22 +#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) +#define MXC_CCM_CCGR6_I2C4_OFFSET 24 +#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) +#define MXC_CCM_CCGR6_PWM5_OFFSET 26 +#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) +#define MXC_CCM_CCGR6_PWM6_OFFSET 28 +#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) +#define MXC_CCM_CCGR6_PWM7_OFFSET 30 +#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) #else -#define PLL2_PFD0_FREQ 306580000 -#define PLL2_PFD1_FREQ 528000000 -#endif -#define PLL2_PFD2_FREQ 396000000 -#define PLL2_PFD2_DIV_FREQ (PLL2_PFD2_FREQ / 2) -#define PLL3_PFD0_FREQ 720000000 -#define PLL3_PFD1_FREQ 540000000 -#define PLL3_PFD2_FREQ 508200000 -#define PLL3_PFD3_FREQ 454700000 -#define PLL3_80M 80000000 -#define PLL3_60M 60000000 +#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 +#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) +#endif + +#define BM_ANADIG_USB_PLL_480_CTRL_LOCK (1 << 31) +#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS (1 << 16) +#define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC 14 +#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) & \ + BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_USB_PLL_480_CTRL_ENABLE (1 << 13) +#define BM_ANADIG_USB_PLL_480_CTRL_POWER (1 << 12) +#define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP (1 << 10) +#define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP (1 << 9) +#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF (1 << 8) +#define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF (1 << 7) +#define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS (1 << 6) +#define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0 2 +#define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) +#define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v) \ + (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \ + BM_ANADIG_USB_PLL_480_CTRL_CONTROL0) +#define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT 0 +#define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) +#define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v) \ + (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \ + BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) + +#define BM_ANADIG_PLL_528_LOCK (1 << 31) +#define BM_ANADIG_PLL_528_PLL_SEL (1 << 19) +#define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18) +#define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17) +#define BM_ANADIG_PLL_528_BYPASS (1 << 16) +#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \ + BM_ANADIG_PLL_528_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_528_ENABLE (1 << 13) +#define BM_ANADIG_PLL_528_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_528_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_528_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_528_DIV_SELECT 0 +#define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT) +#define BF_ANADIG_PLL_528_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \ + BM_ANADIG_PLL_528_DIV_SELECT) + +#define BP_ANADIG_PLL_528_SS_STOP 16 +#define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP) +#define BF_ANADIG_PLL_528_SS_STOP(v) \ + (((v) << BP_ANADIG_PLL_528_SS_STOP) & \ + BM_ANADIG_PLL_528_SS_STOP) +#define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15) +#define BP_ANADIG_PLL_528_SS_STEP 0 +#define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP) +#define BF_ANADIG_PLL_528_SS_STEP(v) \ + (((v) << BP_ANADIG_PLL_528_SS_STEP) & \ + BM_ANADIG_PLL_528_SS_STEP) + +#define BP_ANADIG_PLL_528_NUM_A 0 +#define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A) +#define BF_ANADIG_PLL_528_NUM_A(v) \ + (((v) << BP_ANADIG_PLL_528_NUM_A) & \ + BM_ANADIG_PLL_528_NUM_A) + +#define BP_ANADIG_PLL_528_DENOM_B 0 +#define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B) +#define BF_ANADIG_PLL_528_DENOM_B(v) \ + (((v) << BP_ANADIG_PLL_528_DENOM_B) & \ + BM_ANADIG_PLL_528_DENOM_B) + +#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31) +#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21) +#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 +#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) +#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \ + BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) +#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) +#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17) +#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16) +#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \ + BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13) +#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 +#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT) +#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \ + BM_ANADIG_PLL_AUDIO_DIV_SELECT) + +#define BP_ANADIG_PLL_AUDIO_NUM_A 0 +#define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A) +#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \ + BM_ANADIG_PLL_AUDIO_NUM_A) + +#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 +#define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B) +#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \ + BM_ANADIG_PLL_AUDIO_DENOM_B) + +#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31) +#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21) +#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 +#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) +#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \ + BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) +#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) +#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17) +#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16) +#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \ + BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13) +#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 +#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT) +#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \ + BM_ANADIG_PLL_VIDEO_DIV_SELECT) + +#define BP_ANADIG_PLL_VIDEO_NUM_A 0 +#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A) +#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \ + BM_ANADIG_PLL_VIDEO_NUM_A) + +#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 +#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B) +#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \ + BM_ANADIG_PLL_VIDEO_DENOM_B) + +#define BM_ANADIG_PLL_ENET_LOCK (1 << 31) +#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21) +#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20) +#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19) +#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18) +#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17) +#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16) +#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \ + BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13) +#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 +#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT) +#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \ + BM_ANADIG_PLL_ENET_DIV_SELECT) + +#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31) +#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30) +#define BP_ANADIG_PFD_480_PFD3_FRAC 24 +#define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC) +#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ + (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \ + BM_ANADIG_PFD_480_PFD3_FRAC) +#define BM_ANADIG_PFD_480_PFD2_CLKGATE (1 << 23) +#define BM_ANADIG_PFD_480_PFD2_STABLE (1 << 22) +#define BP_ANADIG_PFD_480_PFD2_FRAC 16 +#define BM_ANADIG_PFD_480_PFD2_FRAC (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC) +#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ + (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \ + BM_ANADIG_PFD_480_PFD2_FRAC) +#define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15) +#define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14) +#define BP_ANADIG_PFD_480_PFD1_FRAC 8 +#define BM_ANADIG_PFD_480_PFD1_FRAC (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC) +#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ + (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \ + BM_ANADIG_PFD_480_PFD1_FRAC) +#define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7) +#define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6) +#define BP_ANADIG_PFD_480_PFD0_FRAC 0 +#define BM_ANADIG_PFD_480_PFD0_FRAC (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC) +#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ + (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \ + BM_ANADIG_PFD_480_PFD0_FRAC) + +#define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31) +#define BM_ANADIG_PFD_528_PFD3_STABLE (1 << 30) +#define BP_ANADIG_PFD_528_PFD3_FRAC 24 +#define BM_ANADIG_PFD_528_PFD3_FRAC (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC) +#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ + (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \ + BM_ANADIG_PFD_528_PFD3_FRAC) +#define BM_ANADIG_PFD_528_PFD2_CLKGATE (1 << 23) +#define BM_ANADIG_PFD_528_PFD2_STABLE (1 << 22) +#define BP_ANADIG_PFD_528_PFD2_FRAC 16 +#define BM_ANADIG_PFD_528_PFD2_FRAC (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC) +#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ + (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \ + BM_ANADIG_PFD_528_PFD2_FRAC) +#define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15) +#define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14) +#define BP_ANADIG_PFD_528_PFD1_FRAC 8 +#define BM_ANADIG_PFD_528_PFD1_FRAC (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC) +#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ + (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \ + BM_ANADIG_PFD_528_PFD1_FRAC) +#define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7) +#define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6) +#define BP_ANADIG_PFD_528_PFD0_FRAC 0 +#define BM_ANADIG_PFD_528_PFD0_FRAC (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC) +#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ + (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \ + BM_ANADIG_PFD_528_PFD0_FRAC) #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h new file mode 100644 index 0000000000..e85651632e --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/hab.h @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + * +*/ + +#ifndef __ARCH_MX6_HAB_H +#define __ARCH_MX6_HAB_H + +#ifdef CONFIG_SECURE_BOOT + +#include +#include + +int get_hab_status(void); + +/* -------- start of HAB API updates ------------*/ +/* The following are taken from HAB4 SIS */ + +/* Status definitions */ +typedef enum hab_status { + HAB_STS_ANY = 0x00, + HAB_FAILURE = 0x33, + HAB_WARNING = 0x69, + HAB_SUCCESS = 0xf0 +} hab_status_t; + +/* Security Configuration definitions */ +typedef enum hab_config { + HAB_CFG_RETURN = 0x33, /**< Field Return IC */ + HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */ + HAB_CFG_CLOSED = 0xcc /**< Secure IC */ +} hab_config_t; + +/* State definitions */ +typedef enum hab_state { + HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */ + HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */ + HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */ + HAB_STATE_TRUSTED = 0x99, /**< Trusted state */ + HAB_STATE_SECURE = 0xaa, /**< Secure state */ + HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */ + HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */ + HAB_STATE_NONE = 0xf0, /**< No security state machine */ + HAB_STATE_MAX +} hab_state_t; + +typedef enum hab_target { + HAB_TGT_MEMORY = 0x0f, /* Check memory white list */ + HAB_TGT_PERIPHERAL = 0xf0, /* Check peripheral white list*/ + HAB_TGT_ANY = 0x55, /**< Check memory & peripheral white list */ +} hab_target_t; + +enum HAB_FUNC_OFFSETS { + HAB_RVT_HEADER, + HAB_RVT_ENTRY, + HAB_RVT_EXIT, + HAB_RVT_CHECK_TARGET, + HAB_RVT_AUTHENTICATE_IMAGE, + HAB_RVT_RUN_DCD, + HAB_RVT_RUN_CSF, + HAB_RVT_ASSERT, + HAB_RVT_REPORT_EVENT, + HAB_RVT_REPORT_STATUS, + HAB_RVT_FAILSAFE, +}; + +/* Function prototype description */ +typedef hab_status_t hab_rvt_entry_t(void); + +typedef hab_status_t hab_rvt_exit_t(void); + +typedef hab_status_t hab_rvt_check_target_t(hab_target_t, const void *, + size_t); + +typedef hab_status_t hab_loader_callback_f_t(void**, size_t*, const void*); +typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, + void **, size_t *, hab_loader_callback_f_t); + +typedef hab_status_t hab_rvt_run_dcd_t(const uint8_t *dcd); + +typedef hab_status_t hab_rvt_run_csf_t(const uint8_t *csf, uint8_t cid); + +typedef hab_status_t hab_rvt_assert_t(uint32_t, const void *, + size_t); + +typedef hab_status_t hab_rvt_report_event_t(hab_status_t, uint32_t, + uint8_t* , size_t*); + +typedef hab_status_t hab_rvt_report_status_t(enum hab_config *, + enum hab_state *); + +typedef void hapi_clock_init_t(void); + +#ifdef CONFIG_SOC_MX6SX +#define HAB_RVT_BASE 0x00000100 +#else +#define HAB_RVT_BASE 0x00000094 +#endif + +static inline void **hab_rvt_base(void) +{ + uint32_t *base; + + if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && + soc_rev() >= CHIP_REV_1_5) || + (is_cpu_type(MXC_CPU_MX6DL) && soc_rev() >= CHIP_REV_1_2) || + is_cpu_type(MXC_CPU_MX6SOLO)) + base = (void *)0x98; + else + base = (void *)0x94; + if ((*base & 0xff0000ff) != cpu_to_be32(0xdd000041)) { + printf("Invalid RVT @ %p\n", base); + return NULL; + } + return (void **)base; +} + +#define HAB_CID_ROM 0 /**< ROM Caller ID */ +#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ +/* ----------- end of HAB API updates ------------*/ + +#define hab_rvt_entry_p \ + ((hab_rvt_entry_t *)hab_rvt_base()[HAB_RVT_ENTRY]) + +#define hab_rvt_exit_p \ + ((hab_rvt_exit_t *)hab_rvt_base()[HAB_RVT_EXIT]) + +#define hab_rvt_check_target_p \ + ((hab_rvt_check_target_t*)hab_rvt_base()[HAB_RVT_CHECK_TARGET]) + +#define hab_rvt_authenticate_image_p \ + ((hab_rvt_authenticate_image_t *)hab_rvt_base()[HAB_RVT_AUTHENTICATE_IMAGE]) + +#define hab_rvt_run_dcd_p \ + ((hab_rvt_run_dcd_t*)hab_rvt_base()[HAB_RVT_RUN_DCD]) + +#define hab_rvt_run_csf_p \ + ((hab_rvt_run_csf_t*)hab_rvt_base()[HAB_RVT_RUN_CSF]) + +#define hab_rvt_assert_p \ + ((hab_rvt_assert_t*)hab_rvt_base()[HAB_RVT_ASSERT]) + +#define hab_rvt_report_event_p \ + ((hab_rvt_report_event_t*)hab_rvt_base()[HAB_RVT_REPORT_EVENT]) + +#define hab_rvt_report_status_p \ + ((hab_rvt_report_status_t*)hab_rvt_base()[HAB_RVT_REPORT_STATUS]) + +#define HAB_FUNC(n, rt) \ +static inline rt hab_rvt_##n(void) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(); \ +} \ + +#define HAB_FUNC1(n, rt, t1) \ +static inline rt hab_rvt_##n(t1 p1) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1); \ +} + +#define HAB_FUNC2(n, rt, t1, t2) \ +static inline rt hab_rvt_##n(t1 p1, t2 p2) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1, p2); \ +} + +#define HAB_FUNC3(n, rt, t1, t2, t3) \ +static inline rt hab_rvt_##n(t1 p1, t2 p2, t3 p3) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1, p2, p3); \ +} + +#define HAB_FUNC4(n, rt, t1, t2, t3, t4) \ +static inline rt hab_rvt_##n(t1 p1, t2 p2, t3 p3, t4 p4) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1, p2, p3, p4); \ +} + +#define HAB_FUNC5(n, rt, t1, t2, t3, t4, t5) \ +static inline rt hab_rvt_##n(t1 p1, t2 p2, t3 p3, t4 p4, t5 p5) \ +{ \ + if (hab_rvt_base() == NULL) \ + return (rt)-1; \ + return hab_rvt_##n##_p(p1, p2, p3, p4, p5); \ +} + +#else /* CONFIG_SECURE_BOOT */ + +static inline int get_hab_status(void) +{ + return 0; +} + +#endif /* CONFIG_SECURE_BOOT */ +#endif /* __ARCH_MX6_HAB_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 669463526a..6fbc4412ac 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -11,14 +11,29 @@ #define ARCH_MXC +#define CONFIG_SYS_CACHELINE_SIZE 64 + #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF -#ifdef CONFIG_MX6SL +#ifdef CONFIG_SOC_MX6SL #define GPU_2D_ARB_BASE_ADDR 0x02200000 #define GPU_2D_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 #define OPENVG_ARB_END_ADDR 0x02207FFF +#elif defined(CONFIG_SOC_MX6SX) +#define CAAM_ARB_BASE_ADDR 0x00100000 +#define CAAM_ARB_END_ADDR 0x00107FFF +#define GPU_ARB_BASE_ADDR 0x01800000 +#define GPU_ARB_END_ADDR 0x01803FFF +#define APBH_DMA_ARB_BASE_ADDR 0x01804000 +#define APBH_DMA_ARB_END_ADDR 0x0180BFFF +#define M4_BOOTROM_BASE_ADDR 0x007F8000 + +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + #else #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00103FFF @@ -32,36 +47,58 @@ #define GPU_2D_ARB_END_ADDR 0x00137FFF #define DTCP_ARB_BASE_ADDR 0x00138000 #define DTCP_ARB_END_ADDR 0x0013BFFF -#endif /* CONFIG_MX6SL */ +#endif /* CONFIG_SOC_MX6SL */ #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* GPV - PL301 configuration ports */ -#ifdef CONFIG_MX6SL +#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX)) #define GPV2_BASE_ADDR 0x00D00000 #else #define GPV2_BASE_ADDR 0x00200000 #endif +#ifdef CONFIG_SOC_MX6SX +#define GPV3_BASE_ADDR 0x00E00000 +#define GPV4_BASE_ADDR 0x00F00000 +#define GPV5_BASE_ADDR 0x01000000 +#define GPV6_BASE_ADDR 0x01100000 +#define PCIE_ARB_BASE_ADDR 0x08000000 +#define PCIE_ARB_END_ADDR 0x08FFFFFF + +#else #define GPV3_BASE_ADDR 0x00300000 #define GPV4_BASE_ADDR 0x00800000 +#define PCIE_ARB_BASE_ADDR 0x01000000 +#define PCIE_ARB_END_ADDR 0x01FFFFFF +#endif + #define IRAM_BASE_ADDR 0x00900000 #define SCU_BASE_ADDR 0x00A00000 #define IC_INTERFACES_BASE_ADDR 0x00A00100 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 +#define L2_PL310_BASE 0x00A02000 #define GPV0_BASE_ADDR 0x00B00000 #define GPV1_BASE_ADDR 0x00C00000 -#define PCIE_ARB_BASE_ADDR 0x01000000 -#define PCIE_ARB_END_ADDR 0x01FFFFFF #define AIPS1_ARB_BASE_ADDR 0x02000000 #define AIPS1_ARB_END_ADDR 0x020FFFFF #define AIPS2_ARB_BASE_ADDR 0x02100000 #define AIPS2_ARB_END_ADDR 0x021FFFFF +#ifdef CONFIG_SOC_MX6SX +#define AIPS3_BASE_ADDR 0x02200000 +#define AIPS3_END_ADDR 0x022FFFFF +#define WEIM_ARB_BASE_ADDR 0x50000000 +#define WEIM_ARB_END_ADDR 0x57FFFFFF +#define QSPI0_AMBA_BASE 0x60000000 +#define QSPI0_AMBA_END 0x6FFFFFFF +#define QSPI1_AMBA_BASE 0x70000000 +#define QSPI1_AMBA_END 0x7FFFFFFF +#else #define SATA_ARB_BASE_ADDR 0x02200000 #define SATA_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 @@ -74,8 +111,9 @@ #define IPU2_ARB_END_ADDR 0x02BFFFFF #define WEIM_ARB_BASE_ADDR 0x08000000 #define WEIM_ARB_END_ADDR 0x0FFFFFFF +#endif -#ifdef CONFIG_MX6SL +#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX)) #define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF #define MMDC1_ARB_BASE_ADDR 0xC0000000 @@ -87,8 +125,10 @@ #define MMDC1_ARB_END_ADDR 0xFFFFFFFF #endif +#ifndef CONFIG_SOC_MX6SX #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR #define IPU_SOC_OFFSET 0x00200000 +#endif /* Defines for Blocks connected via AIPS (SkyBlue) */ #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR @@ -101,7 +141,7 @@ #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) -#ifdef CONFIG_MX6SL +#ifdef CONFIG_SOC_MX6SL #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) @@ -111,7 +151,9 @@ #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) #else +#ifndef CONFIG_SOC_MX6SX #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#endif #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) @@ -120,8 +162,10 @@ #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) #endif +#ifndef CONFIG_SOC_MX6SX #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) +#endif #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) @@ -152,10 +196,17 @@ #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) -#ifdef CONFIG_MX6SL +#ifdef CONFIG_SOC_MX6SL #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#elif defined(CONFIG_SOC_MX6SX) +#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) #else #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) @@ -166,16 +217,11 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) -#ifdef CONFIG_MX6SL -#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) -#else -#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) -#endif +#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) +#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) -#ifdef CONFIG_MX6SL +#ifdef CONFIG_SOC_MX6SL #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #else #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) @@ -190,8 +236,10 @@ #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) -#ifdef CONFIG_MX6SL +#ifdef CONFIG_SOC_MX6SL #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#elif defined(CONFIG_SOC_MX6SX) +#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #else #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #endif @@ -201,13 +249,27 @@ #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#ifdef CONFIG_SOC_MX6SX +#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#else #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#endif #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) +#ifdef CONFIG_SOC_MX6SX +#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#else #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#endif #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#ifdef CONFIG_SOC_MX6SX +#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#else #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#endif #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) @@ -215,14 +277,98 @@ #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +#ifdef CONFIG_SOC_MX6SX +#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) +#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) +#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) +#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) +#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) +#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) +#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) +#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) +#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) +#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) +#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) +#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) +#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) +#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) +#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) +#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) +#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) +#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) +#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) +#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) +#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#endif + #define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_5 0x15 +#ifndef CONFIG_SOC_MX6SX #define IRAM_SIZE 0x00040000 +#else +#define IRAM_SIZE 0x00020000 +#endif #define IMX_IIM_BASE OCOTP_BASE_ADDR #define FEC_QUIRK_ENET_MAC #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include +#define SRC_SCR_CORE_1_RESET_OFFSET 14 +#define SRC_SCR_CORE_1_RESET_MASK (1 << SRC_SCR_CORE_1_RESET_OFFSET) +#define SRC_SCR_CORE_2_RESET_OFFSET 15 +#define SRC_SCR_CORE_2_RESET_MASK (1 << SRC_SCR_CORE_2_RESET_OFFSET) +#define SRC_SCR_CORE_3_RESET_OFFSET 16 +#define SRC_SCR_CORE_3_RESET_MASK (1 << SRC_SCR_CORE_3_RESET_OFFSET) +#define SRC_SCR_CORE_1_ENABLE_OFFSET 22 +#define SRC_SCR_CORE_1_ENABLE_MASK (1 << SRC_SCR_CORE_1_ENABLE_OFFSET) +#define SRC_SCR_CORE_2_ENABLE_OFFSET 23 +#define SRC_SCR_CORE_2_ENABLE_MASK (1 << SRC_SCR_CORE_2_ENABLE_OFFSET) +#define SRC_SCR_CORE_3_ENABLE_OFFSET 24 +#define SRC_SCR_CORE_3_ENABLE_MASK (1 << SRC_SCR_CORE_3_ENABLE_OFFSET) + +/* WEIM registers */ +struct weim { + u32 cs0gcr1; + u32 cs0gcr2; + u32 cs0rcr1; + u32 cs0rcr2; + u32 cs0wcr1; + u32 cs0wcr2; + + u32 cs1gcr1; + u32 cs1gcr2; + u32 cs1rcr1; + u32 cs1rcr2; + u32 cs1wcr1; + u32 cs1wcr2; + + u32 cs2gcr1; + u32 cs2gcr2; + u32 cs2rcr1; + u32 cs2rcr2; + u32 cs2wcr1; + u32 cs2wcr2; + + u32 cs3gcr1; + u32 cs3gcr2; + u32 cs3rcr1; + u32 cs3rcr2; + u32 cs3wcr1; + u32 cs3wcr2; + + u32 unused[12]; + + u32 wcr; + u32 wiar; + u32 ear; +}; + /* System Reset Controller (SRC) */ struct src { u32 scr; @@ -244,6 +390,12 @@ struct src { u32 gpr10; }; +/* GPR1 bitfields */ +#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 +#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) +#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 +#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) + /* GPR3 bitfields */ #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 #define IOMUXC_GPR3_GPU_DBG_MASK (3< + +#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \ + prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc) + +#ifdef CONFIG_SOC_MX6QDL +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc), #include "mx6q_pins.h" -#else -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#undef MX6_PAD_DECL +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc), #include "mx6dl_pins.h" -#else -#if defined(CONFIG_MX6SL) +}; +#elif defined(CONFIG_SOC_MX6Q) +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6q_pins.h" +}; +#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6dl_pins.h" +}; +#elif defined(CONFIG_SOC_MX6SL) #include "mx6sl_pins.h" +#elif defined(CONFIG_SOC_MX6SX) +#include "mx6sx_pins.h" #else #error "Please select cpu" -#endif /* CONFIG_MX6SL */ -#endif /* CONFIG_MX6DL or CONFIG_MX6S */ -#endif /* CONFIG_MX6Q */ +#endif /* CONFIG_SOC_MX6Q */ #endif /*__ASM_ARCH_MX6_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h index 1eb4b3c8b3..b241b12a48 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h @@ -6,8 +6,8 @@ #ifndef __ASM_ARCH_MX6DLS_DDR_H__ #define __ASM_ARCH_MX6DLS_DDR_H__ -#ifndef CONFIG_MX6DL -#ifndef CONFIG_MX6S +#ifndef CONFIG_SOC_MX6DL +#ifndef CONFIG_SOC_MX6S #error "wrong CPU" #endif #endif diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index bf959f97a2..1a9604e710 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -7,1664 +7,1074 @@ #ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__ #define __ASM_ARCH_MX6_MX6DL_PINS_H__ -#include +MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0360, 0x004C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0360, 0x004C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0360, 0x004C, 2, 0x07F8, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0360, 0x004C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0360, 0x004C, 3, 0x08FC, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0360, 0x004C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0360, 0x004C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0364, 0x0050, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0364, 0x0050, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0364, 0x0050, 2, 0x0800, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0364, 0x0050, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0364, 0x0050, 3, 0x08FC, 1, 0) +MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0364, 0x0050, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0364, 0x0050, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0368, 0x0054, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0368, 0x0054, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0368, 0x0054, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0368, 0x0054, 3, 0x0914, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0368, 0x0054, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0368, 0x0054, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x036C, 0x0058, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x036C, 0x0058, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x036C, 0x0058, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x036C, 0x0058, 3, 0x0914, 1, 0) +MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x036C, 0x0058, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x036C, 0x0058, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0370, 0x005C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0370, 0x005C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0370, 0x005C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0370, 0x005C, 3, 0x091C, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0370, 0x005C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0370, 0x005C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0374, 0x0060, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0374, 0x0060, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0374, 0x0060, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0374, 0x0060, 3, 0x091C, 1, 0) +MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0374, 0x0060, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0374, 0x0060, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0378, 0x0064, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0378, 0x0064, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0378, 0x0064, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0378, 0x0064, 3, 0x0910, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0378, 0x0064, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0378, 0x0064, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x037C, 0x0068, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x037C, 0x0068, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x037C, 0x0068, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x037C, 0x0068, 3, 0x0910, 1, 0) +MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x037C, 0x0068, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x037C, 0x0068, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0380, 0x006C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0380, 0x006C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0380, 0x006C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0380, 0x006C, 3, 0x0918, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0380, 0x006C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0380, 0x006C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0384, 0x0070, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0384, 0x0070, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0384, 0x0070, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0384, 0x0070, 3, 0x0918, 1, 0) +MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0384, 0x0070, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0388, 0x0074, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0388, 0x0074, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0388, 0x0074, 2, 0x07D8, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0388, 0x0074, 3, 0x08C0, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0388, 0x0074, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0388, 0x0074, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0388, 0x0074, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x038C, 0x0078, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x038C, 0x0078, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x038C, 0x0078, 2, 0x07E0, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x038C, 0x0078, 3, 0x08CC, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x038C, 0x0078, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x038C, 0x0078, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x038C, 0x0078, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0390, 0x007C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0390, 0x007C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0390, 0x007C, 2, 0x07DC, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0390, 0x007C, 3, 0x08C4, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0390, 0x007C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0390, 0x007C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0390, 0x007C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0394, 0x0080, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0394, 0x0080, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0394, 0x0080, 2, 0x07E4, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0394, 0x0080, 3, 0x08D0, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0394, 0x0080, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0394, 0x0080, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0394, 0x0080, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0398, 0x0084, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0398, 0x0084, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0398, 0x0084, 2, 0x07F4, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0398, 0x0084, 3, 0x08C8, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0398, 0x0084, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0398, 0x0084, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x039C, 0x0088, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x039C, 0x0088, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x039C, 0x0088, 2, 0x07FC, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x039C, 0x0088, 3, 0x08D4, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x039C, 0x0088, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x039C, 0x0088, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x03A0, 0x008C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x03A0, 0x008C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x03A0, 0x008C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x03A0, 0x008C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x03A4, 0x0090, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x03A4, 0x0090, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x03A4, 0x0090, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x03A4, 0x0090, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x03A8, 0x0094, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x03A8, 0x0094, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x03A8, 0x0094, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x03AC, 0x0098, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x03AC, 0x0098, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x03AC, 0x0098, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x03AC, 0x0098, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK, 0x03B0, 0x009C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x03B0, 0x009C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN, 0x03B0, 0x009C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE, 0x03B4, 0x00A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__LCD_RD_E, 0x03B4, 0x00A0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC, 0x03B8, 0x00A4, 1, 0x08D8, 0, 0) +MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__LCD_RS, 0x03B8, 0x00A4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__LCD_CS, 0x03BC, 0x00A8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN4__LCD_BUSY, 0x03C0, 0x00AC, 1, 0x08D8, 1, 0) +MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x03C0, 0x00AC, 3, 0x092C, 0, 0) +MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__LCD_RESET, 0x03C0, 0x00AC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10, 0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13, 0x03D8, 0x00C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x03D8, 0x00C4, 3, 0x07BC, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x03DC, 0x00C8, 3, 0x07B8, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x03E0, 0x00CC, 2, 0x07E8, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x03E0, 0x00CC, 3, 0x0804, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x03E4, 0x00D0, 2, 0x07FC, 1, 0) +MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x03E4, 0x00D0, 3, 0x07C0, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x03E4, 0x00D0, 4, 0x08E8, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x03E8, 0x00D4, 2, 0x07F8, 1, 0) +MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x03E8, 0x00D4, 3, 0x07B4, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x03E8, 0x00D4, 4, 0x08EC, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x03EC, 0x00D8, 2, 0x0800, 1, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x03EC, 0x00D8, 3, 0x07C4, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x03EC, 0x00D8, 4, 0x07A4, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x03F0, 0x00DC, 2, 0x07F4, 1, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x03F0, 0x00DC, 3, 0x07B0, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x03F0, 0x00DC, 4, 0x07A0, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x03F4, 0x00E0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x03F8, 0x00E4, 2, 0x07D8, 1, 0) +MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x03F8, 0x00E4, 3, 0x07A8, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x03FC, 0x00E8, 2, 0x07E0, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x03FC, 0x00E8, 3, 0x079C, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22, 0x0400, 0x00EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x0400, 0x00EC, 2, 0x07DC, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x0400, 0x00EC, 3, 0x07AC, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x0400, 0x00EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23, 0x0404, 0x00F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x0404, 0x00F0, 2, 0x07E4, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x0404, 0x00F0, 3, 0x0798, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x0404, 0x00F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03, 0x0408, 0x00F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0408, 0x00F4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0408, 0x00F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04, 0x040C, 0x00F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x040C, 0x00F8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x040C, 0x00F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05, 0x0410, 0x00FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0410, 0x00FC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0410, 0x00FC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0410, 0x00FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06, 0x0414, 0x0100, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x0414, 0x0100, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x0414, 0x0100, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x0414, 0x0100, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07, 0x0418, 0x0104, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x0418, 0x0104, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x0418, 0x0104, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08, 0x041C, 0x0108, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x041C, 0x0108, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x041C, 0x0108, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x041C, 0x0108, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09, 0x0420, 0x010C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x0420, 0x010C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x0420, 0x010C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x0420, 0x010C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x04E0, 0x0110, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x04E0, 0x0110, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK, 0x04E0, 0x0110, 2, 0x08B8, 0, 0) +MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x04E0, 0x0110, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x04E0, 0x0110, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EPDC_DATA00, 0x04E0, 0x0110, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x04E4, 0x0114, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x04E4, 0x0114, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12, 0x04E4, 0x0114, 2, 0x0890, 0, 0) +MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x04E4, 0x0114, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x04E4, 0x0114, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT, 0x04E4, 0x0114, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x04E8, 0x0118, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x04E8, 0x0118, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13, 0x04E8, 0x0118, 2, 0x0894, 0, 0) +MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x04E8, 0x0118, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x04E8, 0x0118, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0, 0x04E8, 0x0118, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x04EC, 0x011C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x04EC, 0x011C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14, 0x04EC, 0x011C, 2, 0x0898, 0, 0) +MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x04EC, 0x011C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x04EC, 0x011C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1, 0x04EC, 0x011C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x04F0, 0x0120, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x04F0, 0x0120, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15, 0x04F0, 0x0120, 2, 0x089C, 0, 0) +MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x04F0, 0x0120, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x04F0, 0x0120, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2, 0x04F0, 0x0120, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x04F4, 0x0124, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x04F4, 0x0124, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16, 0x04F4, 0x0124, 2, 0x08A0, 0, 0) +MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x04F4, 0x0124, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x04F4, 0x0124, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EPDC_GDCLK, 0x04F4, 0x0124, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x04F8, 0x0128, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x04F8, 0x0128, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17, 0x04F8, 0x0128, 2, 0x08A4, 0, 0) +MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x04F8, 0x0128, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x04F8, 0x0128, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EPDC_GDSP, 0x04F8, 0x0128, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x04FC, 0x012C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x04FC, 0x012C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18, 0x04FC, 0x012C, 2, 0x08A8, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x04FC, 0x012C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x04FC, 0x012C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x04FC, 0x012C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EPDC_GDOE, 0x04FC, 0x012C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x0500, 0x0130, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x0500, 0x0130, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19, 0x0500, 0x0130, 2, 0x08AC, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x0500, 0x0130, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x0500, 0x0130, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x0500, 0x0130, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EPDC_GDRL, 0x0500, 0x0130, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x0504, 0x0134, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x0504, 0x0134, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x0504, 0x0134, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x0504, 0x0134, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x0504, 0x0134, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x0504, 0x0134, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x0504, 0x0134, 6, 0x085C, 0, 0) +MX6_PAD_DECL(EIM_A25__EPDC_DATA15, 0x0504, 0x0134, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN, 0x0504, 0x0134, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x0508, 0x0138, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x0508, 0x0138, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x0508, 0x0138, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9, 0x0508, 0x0138, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x050C, 0x013C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x050C, 0x013C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x050C, 0x013C, 2, 0x07F4, 2, 0) +MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x050C, 0x013C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EPDC_DATA06, 0x050C, 0x013C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0510, 0x0140, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0510, 0x0140, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0510, 0x0140, 2, 0x07FC, 2, 0) +MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0510, 0x0140, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EPDC_DATA08, 0x0510, 0x0140, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x0514, 0x0144, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x0514, 0x0144, 1, 0x07D8, 2, 0) +MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x0514, 0x0144, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18, 0x0514, 0x0144, 3, 0x08A8, 1, 0) +MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x0514, 0x0144, 4, 0x0864, 0, 0) +MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x0514, 0x0144, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0) +MX6_PAD_DECL(EIM_D16__EPDC_DATA10, 0x0514, 0x0144, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x0518, 0x0148, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x0518, 0x0148, 1, 0x07DC, 2, 0) +MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x0518, 0x0148, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK, 0x0518, 0x0148, 3, 0x08B8, 1, 0) +MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x0518, 0x0148, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x0518, 0x0148, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0) +MX6_PAD_DECL(EIM_D17__EPDC_VCOM0, 0x0518, 0x0148, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x051C, 0x014C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x051C, 0x014C, 1, 0x07E0, 2, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x051C, 0x014C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17, 0x051C, 0x014C, 3, 0x08A4, 1, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x051C, 0x014C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x051C, 0x014C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0) +MX6_PAD_DECL(EIM_D18__EPDC_VCOM1, 0x051C, 0x014C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x0520, 0x0150, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x0520, 0x0150, 1, 0x07E8, 1, 0) +MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x0520, 0x0150, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16, 0x0520, 0x0150, 3, 0x08A0, 1, 0) +MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x0520, 0x0150, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x0520, 0x0150, 4, 0x08F8, 0, 0) +MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x0520, 0x0150, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x0520, 0x0150, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPDC_DATA12, 0x0520, 0x0150, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x0524, 0x0154, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x0524, 0x0154, 1, 0x0808, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x0524, 0x0154, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15, 0x0524, 0x0154, 3, 0x089C, 1, 0) +MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x0524, 0x0154, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x0524, 0x0154, 4, 0x08F8, 1, 0) +MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x0524, 0x0154, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x0524, 0x0154, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x0528, 0x0158, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x0528, 0x0158, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x0528, 0x0158, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11, 0x0528, 0x0158, 3, 0x088C, 0, 0) +MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x0528, 0x0158, 4, 0x0920, 0, 0) +MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x0528, 0x0158, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0) +MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x0528, 0x0158, 7, 0x08F0, 0, 0) +MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x052C, 0x015C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x052C, 0x015C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x052C, 0x015C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10, 0x052C, 0x015C, 3, 0x0888, 0, 0) +MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x052C, 0x015C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x052C, 0x015C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x052C, 0x015C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__EPDC_SDCE6, 0x052C, 0x015C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x0530, 0x0160, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x0530, 0x0160, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x0530, 0x0160, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x0530, 0x0160, 2, 0x0908, 0, 0) +MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x0530, 0x0160, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN, 0x0530, 0x0160, 4, 0x08B0, 0, 0) +MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x0530, 0x0160, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x0530, 0x0160, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x0530, 0x0160, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EPDC_DATA11, 0x0530, 0x0160, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x0534, 0x0164, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x0534, 0x0164, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x0534, 0x0164, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x0534, 0x0164, 2, 0x090C, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x0534, 0x0164, 3, 0x07EC, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x0534, 0x0164, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x0534, 0x0164, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x0534, 0x0164, 6, 0x07BC, 1, 0) +MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x0534, 0x0164, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EPDC_SDCE7, 0x0534, 0x0164, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x0538, 0x0168, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x0538, 0x0168, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x0538, 0x0168, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x0538, 0x0168, 2, 0x090C, 1, 0) +MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x0538, 0x0168, 3, 0x07F0, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x0538, 0x0168, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x0538, 0x0168, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x0538, 0x0168, 6, 0x07B8, 1, 0) +MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x0538, 0x0168, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EPDC_SDCE8, 0x0538, 0x0168, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x053C, 0x016C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x053C, 0x016C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x053C, 0x016C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14, 0x053C, 0x016C, 3, 0x0898, 1, 0) +MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x053C, 0x016C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x053C, 0x016C, 4, 0x0904, 0, 0) +MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x053C, 0x016C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x053C, 0x016C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x053C, 0x016C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EPDC_SDOED, 0x053C, 0x016C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x0540, 0x0170, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x0540, 0x0170, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x0540, 0x0170, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13, 0x0540, 0x0170, 3, 0x0894, 1, 0) +MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x0540, 0x0170, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x0540, 0x0170, 4, 0x0904, 1, 0) +MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x0540, 0x0170, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x0540, 0x0170, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x0540, 0x0170, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EPDC_SDOE, 0x0540, 0x0170, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x0544, 0x0174, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0) +MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x0544, 0x0174, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12, 0x0544, 0x0174, 3, 0x0890, 1, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x0544, 0x0174, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x0544, 0x0174, 4, 0x0900, 0, 0) +MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x0544, 0x0174, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x0544, 0x0174, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x0544, 0x0174, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3, 0x0544, 0x0174, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x0548, 0x0178, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x0548, 0x0178, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x0548, 0x0178, 2, 0x0808, 1, 0) +MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x0548, 0x0178, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x0548, 0x0178, 4, 0x0900, 1, 0) +MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x0548, 0x0178, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC, 0x0548, 0x0178, 6, 0x08BC, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x0548, 0x0178, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE, 0x0548, 0x0178, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x054C, 0x017C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x054C, 0x017C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x054C, 0x017C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x054C, 0x017C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x054C, 0x017C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x054C, 0x017C, 4, 0x0908, 1, 0) +MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x054C, 0x017C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x054C, 0x017C, 6, 0x0924, 0, 0) +MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ, 0x054C, 0x017C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x0550, 0x0180, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x0550, 0x0180, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x0550, 0x0180, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x0550, 0x0180, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x0550, 0x0180, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x0550, 0x0180, 4, 0x0908, 2, 0) +MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x0550, 0x0180, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x0550, 0x0180, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P, 0x0550, 0x0180, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN, 0x0550, 0x0180, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0554, 0x0184, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0554, 0x0184, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09, 0x0554, 0x0184, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0554, 0x0184, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0554, 0x0184, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N, 0x0554, 0x0184, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x0558, 0x0188, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x0558, 0x0188, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08, 0x0558, 0x0188, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x0558, 0x0188, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x0558, 0x0188, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EPDC_SDLE, 0x0558, 0x0188, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x055C, 0x018C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x055C, 0x018C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN, 0x055C, 0x018C, 2, 0x08B0, 1, 0) +MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x055C, 0x018C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x055C, 0x018C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EPDC_DATA01, 0x055C, 0x018C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0560, 0x0190, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0560, 0x0190, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC, 0x0560, 0x0190, 2, 0x08B4, 0, 0) +MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0560, 0x0190, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0560, 0x0190, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EPDC_DATA03, 0x0560, 0x0190, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0564, 0x0194, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0564, 0x0194, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC, 0x0564, 0x0194, 2, 0x08BC, 1, 0) +MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0564, 0x0194, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0564, 0x0194, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EPDC_DATA02, 0x0564, 0x0194, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x0568, 0x0198, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x0568, 0x0198, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x0568, 0x0198, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x0568, 0x0198, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EPDC_DATA13, 0x0568, 0x0198, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x056C, 0x019C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x056C, 0x019C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x056C, 0x019C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x056C, 0x019C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EPDC_DATA14, 0x056C, 0x019C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0570, 0x01A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0570, 0x01A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0570, 0x01A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0570, 0x01A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0570, 0x01A0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EPDC_DATA09, 0x0570, 0x01A0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0574, 0x01A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0574, 0x01A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07, 0x0574, 0x01A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0574, 0x01A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0574, 0x01A4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EPDC_BDR0, 0x0574, 0x01A4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0578, 0x01A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0578, 0x01A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06, 0x0578, 0x01A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0578, 0x01A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0578, 0x01A8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EPDC_BDR1, 0x0578, 0x01A8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x057C, 0x01AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x057C, 0x01AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05, 0x057C, 0x01AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x057C, 0x01AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x057C, 0x01AC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0, 0x057C, 0x01AC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x0580, 0x01B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x0580, 0x01B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04, 0x0580, 0x01B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x0580, 0x01B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x0580, 0x01B0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1, 0x0580, 0x01B0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0584, 0x01B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0584, 0x01B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03, 0x0584, 0x01B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0584, 0x01B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0584, 0x01B4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2, 0x0584, 0x01B4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0588, 0x01B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0588, 0x01B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02, 0x0588, 0x01B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0588, 0x01B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0588, 0x01B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3, 0x0588, 0x01B8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x058C, 0x01BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x058C, 0x01BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01, 0x058C, 0x01BC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x058C, 0x01BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x058C, 0x01BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4, 0x058C, 0x01BC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x0590, 0x01C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x0590, 0x01C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00, 0x0590, 0x01C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x0590, 0x01C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x0590, 0x01C0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5, 0x0590, 0x01C0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0594, 0x01C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0594, 0x01C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11, 0x0594, 0x01C4, 2, 0x088C, 1, 0) +MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0594, 0x01C4, 4, 0x07D4, 0, 0) +MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0594, 0x01C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0594, 0x01C4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM, 0x0594, 0x01C4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0598, 0x01C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0598, 0x01C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10, 0x0598, 0x01C8, 2, 0x0888, 1, 0) +MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0598, 0x01C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0598, 0x01C8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR, 0x0598, 0x01C8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x059C, 0x01CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x059C, 0x01CC, 1, 0x07E4, 2, 0) +MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19, 0x059C, 0x01CC, 3, 0x08AC, 1, 0) +MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x059C, 0x01CC, 4, 0x0860, 0, 0) +MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x059C, 0x01CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0) +MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x059C, 0x01CC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__EPDC_DATA05, 0x059C, 0x01CC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x05A0, 0x01D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x05A0, 0x01D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x05A0, 0x01D0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x05A0, 0x01D0, 2, 0x0908, 3, 0) +MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x05A0, 0x01D0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC, 0x05A0, 0x01D0, 4, 0x08B4, 1, 0) +MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x05A0, 0x01D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x05A0, 0x01D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x05A0, 0x01D0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0, 0x05A0, 0x01D0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN, 0x05A0, 0x01D0, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x05A4, 0x01D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x05A4, 0x01D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x05A4, 0x01D4, 2, 0x0804, 1, 0) +MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x05A4, 0x01D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x05A4, 0x01D4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EPDC_DATA04, 0x05A4, 0x01D4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x05A8, 0x01D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x05A8, 0x01D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x05A8, 0x01D8, 2, 0x07F8, 2, 0) +MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x05A8, 0x01D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ, 0x05A8, 0x01D8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EIM_RW, 0x05AC, 0x01DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x05AC, 0x01DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x05AC, 0x01DC, 2, 0x0800, 2, 0) +MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x05AC, 0x01DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x05AC, 0x01DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EPDC_DATA07, 0x05AC, 0x01DC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x05B0, 0x01E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x05B0, 0x01E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x05B0, 0x01E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x05B0, 0x01E0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x05B4, 0x01E4, 1, 0x0828, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x05B4, 0x01E4, 2, 0x0840, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x05B4, 0x01E4, 3, 0x08F4, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x05B4, 0x01E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x05B8, 0x01E8, 0, 0x08E0, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x05B8, 0x01E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x05B8, 0x01E8, 2, 0x0858, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x05B8, 0x01E8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x05B8, 0x01E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x05BC, 0x01EC, 1, 0x0810, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x05BC, 0x01EC, 2, 0x083C, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x05BC, 0x01EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x05BC, 0x01EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x05BC, 0x01EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x05C0, 0x01F0, 2, 0x082C, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x05C0, 0x01F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x05C0, 0x01F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x05C4, 0x01F4, 0, 0x0790, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x05C4, 0x01F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x05C4, 0x01F4, 2, 0x0834, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x05C4, 0x01F4, 3, 0x08F0, 1, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x05C4, 0x01F4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x05C4, 0x01F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x05C8, 0x01F8, 1, 0x0818, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x05C8, 0x01F8, 2, 0x0838, 0, 0) +MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x05CC, 0x01FC, 0, 0x08E4, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x05CC, 0x01FC, 1, 0x081C, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x05CC, 0x01FC, 2, 0x0830, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x05D0, 0x0200, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x05D0, 0x0200, 2, 0x0850, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x05D0, 0x0200, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL, 0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x05D4, 0x0204, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x05D4, 0x0204, 2, 0x0854, 0, 0) +MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x05D4, 0x0204, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x05D8, 0x0208, 0, 0x08DC, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x05D8, 0x0208, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x05D8, 0x0208, 2, 0x084C, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x05D8, 0x0208, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x05D8, 0x0208, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__I2C4_SDA, 0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0) +MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05DC, 0x020C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05DC, 0x020C, 2, 0x08C0, 1, 0) +MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05DC, 0x020C, 3, 0x0794, 0, 0) +MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05DC, 0x020C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05DC, 0x020C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05DC, 0x020C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05E0, 0x0210, 0, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05E0, 0x0210, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05E0, 0x0210, 2, 0x08CC, 1, 0) +MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05E0, 0x0210, 3, 0x0790, 1, 0) +MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05E0, 0x0210, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05E0, 0x0210, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x05E4, 0x0214, 0, 0x0850, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0) +MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x05E4, 0x0214, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x05E4, 0x0214, 4, 0x08F0, 2, 0) +MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x05E4, 0x0214, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0) +MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x05E4, 0x0214, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x05E8, 0x0218, 0, 0x0844, 0, 0) +MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x05E8, 0x0218, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x05E8, 0x0218, 2, 0x07D4, 1, 0) +MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x05E8, 0x0218, 3, 0x08E8, 1, 0) +MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x05E8, 0x0218, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x05E8, 0x0218, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x05EC, 0x021C, 0, 0x0848, 0, 0) +MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x05EC, 0x021C, 1, 0x0814, 0, 0) +MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x05EC, 0x021C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x05EC, 0x021C, 3, 0x08EC, 1, 0) +MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x05EC, 0x021C, 4, 0x0794, 1, 0) +MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x05EC, 0x021C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x05EC, 0x021C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x05F0, 0x0220, 0, 0x08C0, 2, 0) +MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x05F0, 0x0220, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x05F0, 0x0220, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x05F0, 0x0220, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x05F0, 0x0220, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x05F0, 0x0220, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x05F0, 0x0220, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x05F4, 0x0224, 0, 0x0830, 1, 0) +MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x05F4, 0x0224, 2, 0x08D0, 1, 0) +MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x05F4, 0x0224, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__SD2_WP, 0x05F4, 0x0224, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x05F4, 0x0224, 7, 0x08E0, 1, 0) +MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05F8, 0x0228, 0, 0x0834, 1, 0) +MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0) +MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05F8, 0x0228, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05F8, 0x0228, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05F8, 0x0228, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05F8, 0x0228, 6, 0x0924, 1, 0) +MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05F8, 0x0228, 7, 0x08DC, 1, 0) +MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x05FC, 0x022C, 0, 0x0838, 1, 0) +MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x05FC, 0x022C, 2, 0x08C8, 1, 0) +MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x05FC, 0x022C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x05FC, 0x022C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x0600, 0x0230, 0, 0x084C, 1, 0) +MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x0600, 0x0230, 2, 0x08D4, 1, 0) +MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x0600, 0x0230, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x0600, 0x0230, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0) +MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x0600, 0x0230, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0604, 0x0234, 0, 0x0840, 1, 0) +MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0) +MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0604, 0x0234, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0604, 0x0234, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0604, 0x0234, 7, 0x08E4, 1, 0) +MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0608, 0x0238, 0, 0x0854, 1, 0) +MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0608, 0x0238, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0608, 0x0238, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0608, 0x0238, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0608, 0x0238, 4, 0x0904, 2, 0) +MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0608, 0x0238, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0608, 0x0238, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0608, 0x0238, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__I2C4_SCL, 0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0) +MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x060C, 0x023C, 0, 0x0858, 1, 0) +MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x060C, 0x023C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x060C, 0x023C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x060C, 0x023C, 3, 0x07C8, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x060C, 0x023C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x060C, 0x023C, 4, 0x0904, 3, 0) +MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x060C, 0x023C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x060C, 0x023C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x060C, 0x023C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__I2C4_SDA, 0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0) +MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x0610, 0x0240, 0, 0x082C, 1, 0) +MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x0610, 0x0240, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x0610, 0x0240, 2, 0x08C4, 1, 0) +MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x0610, 0x0240, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x0610, 0x0240, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x0610, 0x0240, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__SD1_WP, 0x0610, 0x0240, 6, 0x092C, 1, 0) +MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x062C, 0x0244, 0, 0x07D8, 3, 0) +MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x062C, 0x0244, 1, 0x0824, 0, 0) +MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x062C, 0x0244, 2, 0x07C0, 1, 0) +MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x062C, 0x0244, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x062C, 0x0244, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x062C, 0x0244, 4, 0x0914, 2, 0) +MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x062C, 0x0244, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x062C, 0x0244, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x0630, 0x0248, 0, 0x07DC, 3, 0) +MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x0630, 0x0248, 1, 0x0810, 1, 0) +MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x0630, 0x0248, 2, 0x07C4, 1, 0) +MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x0630, 0x0248, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x0630, 0x0248, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x0630, 0x0248, 4, 0x091C, 2, 0) +MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x0630, 0x0248, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x0630, 0x0248, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x0634, 0x024C, 0, 0x07E8, 2, 0) +MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x0634, 0x024C, 1, 0x0820, 0, 0) +MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x0634, 0x024C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x0634, 0x024C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x0634, 0x024C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x0634, 0x024C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x0634, 0x024C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x0638, 0x0250, 0, 0x07F0, 1, 0) +MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x0638, 0x0250, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x0638, 0x0250, 2, 0x0860, 1, 0) +MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x0638, 0x0250, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0) +MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x0638, 0x0250, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x0638, 0x0250, 6, 0x08F0, 3, 0) +MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x063C, 0x0254, 0, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x063C, 0x0254, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x063C, 0x0254, 2, 0x0920, 1, 0) +MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x063C, 0x0254, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x063C, 0x0254, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x063C, 0x0254, 4, 0x0918, 2, 0) +MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x063C, 0x0254, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x0640, 0x0258, 0, 0x07E0, 3, 0) +MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x0640, 0x0258, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x0640, 0x0258, 2, 0x07B4, 1, 0) +MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x0640, 0x0258, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x0640, 0x0258, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x0640, 0x0258, 4, 0x0914, 3, 0) +MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x0640, 0x0258, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x0640, 0x0258, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x0644, 0x025C, 0, 0x07E4, 3, 0) +MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x0644, 0x025C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x0644, 0x025C, 2, 0x07B0, 1, 0) +MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x0644, 0x025C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x0644, 0x025C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x0644, 0x025C, 4, 0x091C, 3, 0) +MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x0644, 0x025C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x0644, 0x025C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x0648, 0x0260, 0, 0x07EC, 1, 0) +MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x0648, 0x0260, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x0648, 0x0260, 2, 0x07C8, 1, 0) +MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x0648, 0x0260, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x0648, 0x0260, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x0648, 0x0260, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x0648, 0x0260, 6, 0x085C, 1, 0) +MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x064C, 0x0264, 1, 0x0794, 2, 0) +MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x064C, 0x0264, 2, 0x0864, 1, 0) +MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x064C, 0x0264, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0) +MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x064C, 0x0264, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x064C, 0x0264, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x0650, 0x0268, 0, 0x07CC, 0, 0) +MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x0650, 0x0268, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x0650, 0x0268, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x0650, 0x0268, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x0650, 0x0268, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x0650, 0x0268, 4, 0x0918, 3, 0) +MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x0650, 0x0268, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x0654, 0x026C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x0654, 0x026C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x0654, 0x026C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x0658, 0x0270, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x0658, 0x0270, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x065C, 0x0274, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x065C, 0x0274, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x0660, 0x0278, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x0660, 0x0278, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x0660, 0x0278, 2, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x0660, 0x0278, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x0664, 0x027C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x0664, 0x027C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x0664, 0x027C, 2, 0x0844, 1, 0) +MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x0664, 0x027C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x0664, 0x027C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x0664, 0x027C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x0668, 0x0280, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x0668, 0x0280, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x0668, 0x0280, 2, 0x0848, 1, 0) +MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x0668, 0x0280, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x0668, 0x0280, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__I2C4_SDA, 0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0) +MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x066C, 0x0284, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x066C, 0x0284, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x066C, 0x0284, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x0670, 0x0288, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x0670, 0x0288, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x0670, 0x0288, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x0674, 0x028C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x0674, 0x028C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x0674, 0x028C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x0678, 0x0290, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x0678, 0x0290, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x0678, 0x0290, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x067C, 0x0294, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x067C, 0x0294, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x067C, 0x0294, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x0680, 0x0298, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x0680, 0x0298, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x0680, 0x0298, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x0684, 0x029C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x0684, 0x029C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x0684, 0x029C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0688, 0x02A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0688, 0x02A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0688, 0x02A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x068C, 0x02A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x068C, 0x02A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x0690, 0x02A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x0690, 0x02A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL, 0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0) +MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0694, 0x02AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0694, 0x02AC, 1, 0x0818, 1, 0) +MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0694, 0x02AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x0698, 0x02B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x0698, 0x02B0, 1, 0x081C, 1, 0) +MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x0698, 0x02B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x069C, 0x02B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x069C, 0x02B4, 1, 0x0820, 1, 0) +MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x069C, 0x02B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x06A0, 0x02B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x06A0, 0x02B8, 1, 0x0824, 1, 0) +MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x06A4, 0x02BC, 1, 0x0828, 1, 0) +MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) +MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x06A8, 0x02C0, 1, 0x0814, 1, 0) +MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x06B0, 0x02C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) +MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0) +MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x06C0, 0x02D8, 2, 0x08F4, 1, 0) +MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x06C0, 0x02D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x06C4, 0x02DC, 0, 0x0928, 1, 0) +MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x06C4, 0x02DC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x06C8, 0x02E0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x06C8, 0x02E0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x06CC, 0x02E4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x06D0, 0x02E8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x06D4, 0x02EC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x06D8, 0x02F0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x06D8, 0x02F0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x06DC, 0x02F4, 0, 0x0930, 1, 0) +MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x06DC, 0x02F4, 2, 0x08C0, 3, 0) +MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x06DC, 0x02F4, 3, 0x07A4, 1, 0) +MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x06E0, 0x02F8, 2, 0x08CC, 2, 0) +MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x06E0, 0x02F8, 3, 0x07A0, 1, 0) +MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x06E4, 0x02FC, 3, 0x0798, 1, 0) +MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x06E4, 0x02FC, 4, 0x08D4, 2, 0) +MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x06E4, 0x02FC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x06E8, 0x0300, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x06E8, 0x0300, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x06E8, 0x0300, 3, 0x07AC, 1, 0) +MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x06E8, 0x0300, 4, 0x08C8, 2, 0) +MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x06E8, 0x0300, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x06EC, 0x0304, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x06EC, 0x0304, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x06EC, 0x0304, 3, 0x079C, 1, 0) +MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x06EC, 0x0304, 4, 0x08D0, 2, 0) +MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x06EC, 0x0304, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x06F0, 0x0308, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x06F0, 0x0308, 2, 0x08C4, 2, 0) +MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x06F0, 0x0308, 3, 0x07A8, 1, 0) +MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x06F0, 0x0308, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06F4, 0x030C, 0, 0x0934, 1, 0) +MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06F4, 0x030C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06F4, 0x030C, 1, 0x0900, 2, 0) +MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06F4, 0x030C, 2, 0x07C8, 2, 0) +MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06F4, 0x030C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06F8, 0x0310, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06F8, 0x0310, 1, 0x0900, 3, 0) +MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06F8, 0x0310, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06F8, 0x0310, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06FC, 0x0314, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06FC, 0x0314, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06FC, 0x0314, 1, 0x08F8, 2, 0) +MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06FC, 0x0314, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06FC, 0x0314, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x0700, 0x0318, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x0700, 0x0318, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x0700, 0x0318, 1, 0x08F8, 3, 0) +MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x0700, 0x0318, 2, 0x07CC, 1, 0) +MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x0700, 0x0318, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x0704, 0x031C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x0704, 0x031C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x0708, 0x0320, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x0708, 0x0320, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x0708, 0x0320, 1, 0x0908, 4, 0) +MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x0708, 0x0320, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x070C, 0x0324, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x070C, 0x0324, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x070C, 0x0324, 1, 0x0904, 4, 0) +MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x070C, 0x0324, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0710, 0x0328, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0710, 0x0328, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0710, 0x0328, 1, 0x0904, 5, 0) +MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0710, 0x0328, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0714, 0x032C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0714, 0x032C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0714, 0x032C, 1, 0x08FC, 2, 0) +MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0714, 0x032C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0718, 0x0330, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0718, 0x0330, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0718, 0x0330, 1, 0x08FC, 3, 0) +MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0718, 0x0330, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x071C, 0x0334, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x071C, 0x0334, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x071C, 0x0334, 1, 0x0908, 5, 0) +MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x071C, 0x0334, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x0720, 0x0338, 0, 0x0938, 1, 0) +MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x0720, 0x0338, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x0720, 0x0338, 2, 0x090C, 2, 0) +MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x0720, 0x0338, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x0724, 0x033C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x0724, 0x033C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x0724, 0x033C, 2, 0x090C, 3, 0) +MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x0724, 0x033C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0728, 0x0340, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0728, 0x0340, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0728, 0x0340, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x072C, 0x0344, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x072C, 0x0344, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x072C, 0x0344, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x0730, 0x0348, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x0730, 0x0348, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0734, 0x034C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0734, 0x034C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0738, 0x0350, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0738, 0x0350, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0738, 0x0350, 2, 0x0904, 6, 0) +MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0738, 0x0350, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x073C, 0x0354, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x073C, 0x0354, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x073C, 0x0354, 2, 0x0900, 4, 0) +MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x073C, 0x0354, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x0740, 0x0358, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x0740, 0x0358, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x0740, 0x0358, 2, 0x0900, 5, 0) +MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x0740, 0x0358, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0744, 0x035C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0744, 0x035C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0744, 0x035C, 2, 0x0904, 7, 0) +MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0744, 0x035C, 5, 0x0000, 0, 0) -enum { - MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_RXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), - MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__SIMBA_TRACE_7 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), - MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__SIMBA_TRACE_8 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 = IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), - MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__SIMBA_TRACE_9 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 = IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_TXD = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), - MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__SIMBA_TRACE_10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 = IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_RXD = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), - MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__SIMBA_TRACE_11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 = IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_TXD = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), - MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__SIMBA_TRACE_12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 = IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), - MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__SIMBA_TRACE_13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 = IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_RTS = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), - MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__SIMBA_TRACE_14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 = IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), - MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__SIMBA_TRACE_15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 = IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_RTS = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), - MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 = IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0), - MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), - MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__SIMBA_TRACE_1 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0), - MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), - MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__SIMBA_TRACE_2 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0), - MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), - MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__SIMBA_TRACE_3 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0), - MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), - MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__SIMBA_TRACE_4 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0), - MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), - MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0), - MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__SIMBA_TRACE_5 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0), - MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), - MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0), - MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__SIMBA_TRACE_6 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 = IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__SIMBA_TRCLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__SIMBA_TRCTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__SIMBA_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 = IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__SIMBA_TRACE_0 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__LCDIF_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN15__LCDIF_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 = IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__LCDIF_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__LCDIF_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), - MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__LCDIF_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__LCDIF_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), - MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), - MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__LCDIF_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__LCDIF_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__LCDIF_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21 = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__LCDIF_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__LCDIF_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__LCDIF_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__LCDIF_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), - MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__LCDIF_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0), - MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__LCDIF_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__LCDIF_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__LCDIF_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__LCDIF_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__LCDIF_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__LCDIF_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), - MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__LCDIF_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0), - MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), - MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__LCDIF_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0), - MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), - MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__LCDIF_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0), - MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), - MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__LCDIF_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 = IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__LCDIF_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 = IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15 = IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__LCDIF_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16 = IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__LCDIF_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17 = IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__LCDIF_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 = IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__LCDIF_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__LCDIF_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0430, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x0434, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0438, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x043C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0440, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0444, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0448, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x044C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0450, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0454, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0458, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x047C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0480, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0484, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x0488, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x048C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0490, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x0494, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0498, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x049C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x04A0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x04A4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x04A8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x04AC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x04B0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x04B4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x04B8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x04BC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x04C0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x04C4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x04C8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x04CC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x04D0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0), - MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 = IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EPDC_SDDO_0 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_CSI1_D_12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), - MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 = IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EPDC_PWRSTAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_CSI1_D_13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), - MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 = IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EPDC_PWRCTRL_0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_CSI1_D_14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), - MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 = IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EPDC_PWRCTRL_1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_CSI1_D_15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), - MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 = IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EPDC_PWRCTRL_2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_CSI1_D_16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), - MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 = IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__EPDC_GDCLK = IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_CSI1_D_17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), - MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__EPDC_GDSP = IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_CSI1_D_18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3 = IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_CSI1_D_19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2 = IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A24__EPDC_GDRL = IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0), - MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0 = IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EPDC_SDDO_15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EPDC_SDCE_9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0), - MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 = IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EPDC_SDDO_6 = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0), - MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 = IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EPDC_SDDO_8 = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU1_CSI1_D_18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), - MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0), - MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0), - MX6_PAD_EIM_D16__TPSMP_HTRANS_0 = IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__EPDC_SDDO_10 = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0), - MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0), - MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1 = IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D17__EPDC_VCOM_0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU1_CSI1_D_17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), - MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0), - MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2 = IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D18__EPDC_VCOM_1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU1_CSI1_D_16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), - MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D19__UART1_RTS = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), - MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP = IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPDC_SDDO_12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0), - MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU1_CSI1_D_15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), - MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), - MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D20__TPSMP_HTRANS_1 = IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_CSI1_D_11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), - MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), - MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), - MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0), - MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_CSI1_D_10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), - MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE = IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D22__EPDC_SDCE_6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_RTS = IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0), - MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EPDC_SDDO_11 = IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_RXD = IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0), - MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0), - MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), - MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EPDC_SDCE_7 = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_TXD = IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0), - MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0), - MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), - MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EPDC_SDCE_8 = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI1_D_14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), - MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_RXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0), - MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__EPDC_SDOED = IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI1_D_13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), - MX6_PAD_EIM_D27__UART2_TXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), - MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__EPDC_SDOE = IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), - MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_CSI1_D_12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), - MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D28__UART2_RTS = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), - MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EPDC_PWRCTRL_3 = IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0), - MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EPDC_PWRWAKE = IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_RTS = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), - MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), - MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0 = IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), - MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1 = IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EPDC_SDCLK = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_CSI1_D_9 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 = IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EPDC_SDCLKN = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_CSI1_D_8 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 = IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EPDC_SDLE = IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0), - MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 = IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EPDC_SDDO_1 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC = IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0), - MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 = IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EPDC_SDDO_3 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0), - MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 = IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EPDC_SDDO_2 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0), - MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 = IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EPDC_SDDO_13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 = IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EPDC_SDDO_14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 = IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EPDC_SDDO_9 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_CSI1_D_7 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 = IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EPDC_BDR_0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_CSI1_D_6 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 = IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ = IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EPDC_BDR_1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_CSI1_D_5 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 = IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EPDC_SDCE_0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_CSI1_D_4 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 = IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EPDC_SDCE_1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_CSI1_D_3 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 = IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EPDC_SDCE_2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_CSI1_D_2 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 = IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EPDC_SDCE_3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_CSI1_D_1 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 = IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EPDC_SDCE_4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_CSI1_D_0 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 = IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EPDC_SDCE_5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_CSI1_D_11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), - MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 = IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), - MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EPDC_PWRCOM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_CSI1_D_10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), - MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 = IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__EPDC_SDSHR = IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0), - MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0), - MX6_PAD_EIM_EB2__IPU1_CSI1_D_19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), - MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0), - MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0), - MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__EPDC_SDDO_5 = IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0), - MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC = IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0), - MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EPDC_SDCE_0 = IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_ACLK_FREERUN = IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0), - MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EPDC_SDDO_4 = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0), - MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 = IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EPDC_PWRIRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0), - MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 = IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EPDC_SDDO_7 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0), - MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), - MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD = IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), - MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0), - MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), - MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0), - MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), - MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH = IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ANATOP_USBOTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), - MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD = IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), - MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), - MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), - MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__I2C4_SCL = IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), - MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), - MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__I2C4_SDA = IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), - MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), - MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), - MX6_PAD_GPIO_1__USBOTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), - MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), - MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0), - MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0), - MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0), - MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0), - MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0), - MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0), - MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0), - MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0), - MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), - MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), - MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), - MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), - MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), - MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), - MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0), - MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), - MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), - MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), - MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), - MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0), - MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), - MX6_PAD_GPIO_5__SIMBA_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0), - MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0), - MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), - MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0), - MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_RXD = IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0), - MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_7__I2C4_SCL = IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0), - MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0), - MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0), - MX6_PAD_GPIO_8__UART2_TXD = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0), - MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_8__I2C4_SDA = IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0), - MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0), - MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), - MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x061C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x0620, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0), - MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), - MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), - MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_RXD = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), - MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0), - MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0), - MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), - MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_RXD = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), - MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1 = IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0), - MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), - MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3 = IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0), - MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0), - MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), - MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), - MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5 = IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), - MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), - MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 = IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7 = IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0), - MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), - MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_TXD = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), - MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0 = IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0), - MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), - MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_TXD = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), - MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2 = IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), - MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0), - MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4 = IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), - MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0), - MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), - MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6 = IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_RTS = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), - MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 = IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 = IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0), - MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 = IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 = IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 = IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 = IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USDHC3_CLKI = IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, 0), - MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 = IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 = IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 = IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 = IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USDHC3_CLKO = IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 = IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 = IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USDHC1_CLKO = IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 = IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT = IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC1_CLKI = IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, 0), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), - MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__USDHC2_CLKO = IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), - MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 = IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__USDHC2_CLKI = IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, 0), - MX6_PAD_NANDF_CS3__I2C4_SDA = IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0), - MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 = IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 = IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 = IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 = IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USDHC4_CLKI = IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, 0), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USDHC4_CLKO = IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__I2C4_SCL = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0), - MX6_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), - MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), - MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), - MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), - MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE_START = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), - MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0), - MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), - MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), - MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS = IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 = IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), - MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), - MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), - MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), - MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), - MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), - MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), - MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), - MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), - MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), - MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), - MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), - MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), - MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), - MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0), - MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0), - MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_RTS = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0), - MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_RTS = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0), - MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0), - MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0), - MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_RTS = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0), - MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_TXD = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0), - MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_RXD = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0), - MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 = IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_TXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), - MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_RXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0), - MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0), - MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), - MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), - MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), - MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0), - MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_RXD = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0), - MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_TXD = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0), - MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0), - MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_RTS = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0), - MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_RXD = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0), - MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), -}; #endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h index 0aa94cffe5..25e895335e 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h @@ -6,7 +6,7 @@ #ifndef __ASM_ARCH_MX6Q_DDR_H__ #define __ASM_ARCH_MX6Q_DDR_H__ -#ifndef CONFIG_MX6Q +#ifndef CONFIG_SOC_MX6Q #error "wrong CPU" #endif diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index a23fb3364c..a8456a284a 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -9,1623 +9,1028 @@ #ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__ #define __ASM_ARCH_MX6_MX6Q_PINS_H__ -#include - -enum { - MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), - MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), - MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), - MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), - MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), - MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), - MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), - MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), - MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), - MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), - MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), - MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), - MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), - MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), - MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), - MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), - MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), - MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), - MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0), - MX6_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), - MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), - MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), - MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), - MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), - MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), - MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), - MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), - MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), - MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), - MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), - MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), - MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), - MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), - MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), - MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), - MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), - MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), - MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), - MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), - MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), - MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0), - MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), - MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), - MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), - MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), - MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), - MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), - MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), - MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), - MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), - MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), - MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), - MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), - MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), - MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), - MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), - MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), - MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), - MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), - MX6_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), - MX6_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), - MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), - MX6_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), - MX6_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), - MX6_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), - MX6_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), - MX6_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), - MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), - MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), - MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), - MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), - MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), - MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), - MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), - MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), - MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), - MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), - MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), - MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0), - MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), - MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), - MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), - MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), - MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), - MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), - MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), - MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), - MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), - MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), - MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), - MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), - MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), - MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), - MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), - MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), - MX6_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), - MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), - MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), - MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), - MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), - MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0), - MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), - MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), - MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), - MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), - MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), - MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), - MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), - MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), - MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), - MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), - MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), - MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), - MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), - MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), - MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), - MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), - MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), - MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), - MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), - MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), - MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), - MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), - MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), - MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), - MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), - MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), - MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), - MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), - MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), - MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), - MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), - MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), - MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), - MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), - MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), - MX6_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), - MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), - MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), - MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), - MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), - MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), - MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), - MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), - MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), - MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), - MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), - MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), - MX6_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), - MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), - MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), - MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), - MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), - MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), - MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0), - MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), - MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0), - MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), - MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), - MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), - MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), - MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), - MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), - MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), - MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), - MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), - MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), - MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), - MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), - MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), - MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), - MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), - MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), - MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), - MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), - MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), - MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), - MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), - MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), - MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), - MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), - MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), - MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), - MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), - MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), - MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), - MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), - MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), - MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), - MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), - MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), - MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), - MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), - MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), - MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), - MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), - MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), - MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), - MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), - MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), - MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), - MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), - MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), - MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), - MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), - MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), - MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), - MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), - MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), - MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), - MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), - MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), - MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), - MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), - MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), - MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), - MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), - MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), - MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), - MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), - MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), - MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), - MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), - MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0), -}; +MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x0360, 0x004C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0, 0x0360, 0x004C, 1, 0x0834, 0, 0) +MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x0360, 0x004C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x0360, 0x004C, 3, 0x07C8, 0, 0) +MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x0360, 0x004C, 4, 0x08F0, 0, 0) +MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x0360, 0x004C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x0364, 0x0050, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1, 0x0364, 0x0050, 1, 0x0838, 0, 0) +MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x0364, 0x0050, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x0364, 0x0050, 3, 0x07B8, 0, 0) +MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x0364, 0x0050, 4, 0x08F8, 0, 0) +MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x0364, 0x0050, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x0368, 0x0054, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO, 0x0368, 0x0054, 1, 0x082C, 0, 0) +MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x0368, 0x0054, 3, 0x07B4, 0, 0) +MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x0368, 0x0054, 4, 0x08FC, 0, 0) +MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x0368, 0x0054, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x0368, 0x0054, 6, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x036C, 0x0058, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x036C, 0x0058, 2, 0x0918, 0, 0) +MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x036C, 0x0058, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x036C, 0x0058, 7, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x0370, 0x005C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x0370, 0x005C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x0374, 0x0060, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x0374, 0x0060, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x0378, 0x0064, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x0378, 0x0064, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x037C, 0x0068, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x037C, 0x0068, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x0380, 0x006C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x0380, 0x006C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0384, 0x0070, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0, 0) +MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0384, 0x0070, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x0388, 0x0074, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x0388, 0x0074, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0) +MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x038C, 0x0078, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0, 0) +MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x038C, 0x0078, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x0390, 0x007C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0, 0) +MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x0390, 0x007C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x0394, 0x0080, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0, 0) +MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x0394, 0x0080, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x0398, 0x0084, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0, 0) +MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x0398, 0x0084, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x039C, 0x0088, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x039C, 0x0088, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x039C, 0x0088, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x039C, 0x0088, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x039C, 0x0088, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x039C, 0x0088, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x039C, 0x0088, 6, 0x088C, 0, 0) +MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x03A0, 0x008C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x03A0, 0x008C, 1, 0x0800, 0, 0) +MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19, 0x03A0, 0x008C, 3, 0x08D4, 0, 0) +MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x03A0, 0x008C, 4, 0x0890, 0, 0) +MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x03A0, 0x008C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x03A0, 0x008C, 22, 0x08A0, 0, 0) +MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x03A0, 0x008C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x03A4, 0x0090, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x03A4, 0x0090, 1, 0x07F4, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x03A4, 0x0090, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18, 0x03A4, 0x0090, 3, 0x08D0, 0, 0) +MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x03A4, 0x0090, 4, 0x0894, 0, 0) +MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x03A4, 0x0090, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x03A4, 0x0090, 22, 0x08A4, 0, 0) +MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x03A8, 0x0094, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x03A8, 0x0094, 1, 0x07F8, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x03A8, 0x0094, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK, 0x03A8, 0x0094, 3, 0x08E0, 0, 0) +MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x03A8, 0x0094, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x03A8, 0x0094, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x03A8, 0x0094, 22, 0x08A8, 0, 0) +MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x03AC, 0x0098, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x03AC, 0x0098, 1, 0x07FC, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x03AC, 0x0098, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17, 0x03AC, 0x0098, 3, 0x08CC, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x03AC, 0x0098, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x03AC, 0x0098, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x03AC, 0x0098, 22, 0x08AC, 0, 0) +MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x03B0, 0x009C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x03B0, 0x009C, 1, 0x0804, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x03B0, 0x009C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16, 0x03B0, 0x009C, 3, 0x08C8, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x03B0, 0x009C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x03B0, 0x009C, 4, 0x091C, 0, 0) +MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x03B0, 0x009C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x03B0, 0x009C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x03B4, 0x00A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x03B4, 0x00A0, 1, 0x0824, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15, 0x03B4, 0x00A0, 3, 0x08C4, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x03B4, 0x00A0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x03B4, 0x00A0, 4, 0x091C, 1, 0) +MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x03B4, 0x00A0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x03B8, 0x00A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x03B8, 0x00A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11, 0x03B8, 0x00A4, 3, 0x08B4, 0, 0) +MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x03B8, 0x00A4, 4, 0x0944, 0, 0) +MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x03B8, 0x00A4, 22, 0x0898, 0, 0) +MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x03B8, 0x00A4, 7, 0x0914, 0, 0) +MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x03BC, 0x00A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10, 0x03BC, 0x00A8, 3, 0x08B0, 0, 0) +MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x03BC, 0x00A8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x03BC, 0x00A8, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x03C0, 0x00AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x03C0, 0x00AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x03C0, 0x00AC, 2, 0x092C, 0, 0) +MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x03C0, 0x00AC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN, 0x03C0, 0x00AC, 4, 0x08D8, 0, 0) +MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x03C0, 0x00AC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x03C0, 0x00AC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x03C4, 0x00B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x03C4, 0x00B0, 2, 0x092C, 1, 0) +MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x03C4, 0x00B0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC, 0x03C4, 0x00B0, 4, 0x08DC, 0, 0) +MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x03C4, 0x00B0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x03C4, 0x00B0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x03C8, 0x00B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x03C8, 0x00B4, 2, 0x0930, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x03C8, 0x00B4, 3, 0x0808, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x03C8, 0x00B4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x03C8, 0x00B4, 6, 0x07D8, 0, 0) +MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x03C8, 0x00B4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x03CC, 0x00B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x03CC, 0x00B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x03CC, 0x00B8, 2, 0x0930, 1, 0) +MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x03CC, 0x00B8, 3, 0x080C, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x03CC, 0x00B8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x03CC, 0x00B8, 6, 0x07D4, 0, 0) +MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x03CC, 0x00B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x03D0, 0x00BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x03D0, 0x00BC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14, 0x03D0, 0x00BC, 3, 0x08C0, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x03D0, 0x00BC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x03D0, 0x00BC, 4, 0x0928, 0, 0) +MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x03D0, 0x00BC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x03D0, 0x00BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x03D4, 0x00C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x03D4, 0x00C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13, 0x03D4, 0x00C0, 3, 0x08BC, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x03D4, 0x00C0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x03D4, 0x00C0, 4, 0x0928, 1, 0) +MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x03D4, 0x00C0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x03D4, 0x00C0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x03D8, 0x00C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x03D8, 0x00C4, 17, 0x089C, 0, 0) +MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x03D8, 0x00C4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12, 0x03D8, 0x00C4, 3, 0x08B8, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x03D8, 0x00C4, 4, 0x0924, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x03D8, 0x00C4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x03D8, 0x00C4, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x03D8, 0x00C4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x03DC, 0x00C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x03DC, 0x00C8, 2, 0x0824, 1, 0) +MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x03DC, 0x00C8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x03DC, 0x00C8, 4, 0x0924, 1, 0) +MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC, 0x03DC, 0x00C8, 6, 0x08E4, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x03DC, 0x00C8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x03E0, 0x00CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x03E0, 0x00CC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x03E0, 0x00CC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x03E0, 0x00CC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x03E0, 0x00CC, 4, 0x092C, 2, 0) +MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x03E0, 0x00CC, 6, 0x0948, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x03E4, 0x00D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x03E4, 0x00D0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x03E4, 0x00D0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x03E4, 0x00D0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x03E4, 0x00D0, 4, 0x092C, 3, 0) +MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x03E4, 0x00D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x03E8, 0x00D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19, 0x03E8, 0x00D4, 2, 0x08D4, 1, 0) +MX6_PAD_DECL(EIM_A24__IPU2_SISG2, 0x03E8, 0x00D4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x03E8, 0x00D4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x03E8, 0x00D4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x03EC, 0x00D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18, 0x03EC, 0x00D8, 2, 0x08D0, 1, 0) +MX6_PAD_DECL(EIM_A23__IPU2_SISG3, 0x03EC, 0x00D8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x03EC, 0x00D8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x03F0, 0x00DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17, 0x03F0, 0x00DC, 2, 0x08CC, 1, 0) +MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16, 0x03F4, 0x00E0, 2, 0x08C8, 1, 0) +MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x03F4, 0x00E0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x03F8, 0x00E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15, 0x03F8, 0x00E4, 2, 0x08C4, 1, 0) +MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x03F8, 0x00E4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x03FC, 0x00E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14, 0x03FC, 0x00E8, 2, 0x08C0, 1, 0) +MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x03FC, 0x00E8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x0400, 0x00EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x0400, 0x00EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13, 0x0400, 0x00EC, 2, 0x08BC, 1, 0) +MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x0400, 0x00EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x0400, 0x00EC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x0404, 0x00F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x0404, 0x00F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12, 0x0404, 0x00F0, 2, 0x08B8, 1, 0) +MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x0404, 0x00F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x0404, 0x00F0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x0408, 0x00F4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x0408, 0x00F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK, 0x0408, 0x00F4, 2, 0x08E0, 1, 0) +MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x0408, 0x00F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x0408, 0x00F4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x040C, 0x00F8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x040C, 0x00F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x040C, 0x00F8, 2, 0x0810, 0, 0) +MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x040C, 0x00F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0410, 0x00FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0410, 0x00FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0410, 0x00FC, 2, 0x0818, 0, 0) +MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0410, 0x00FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x0414, 0x0100, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x0414, 0x0100, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x0414, 0x0100, 2, 0x0814, 0, 0) +MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x0414, 0x0100, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x0418, 0x0104, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x0418, 0x0104, 2, 0x081C, 0, 0) +MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x0418, 0x0104, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x0418, 0x0104, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x041C, 0x0108, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x041C, 0x0108, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x041C, 0x0108, 2, 0x0820, 0, 0) +MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x041C, 0x0108, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x041C, 0x0108, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0420, 0x010C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0420, 0x010C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11, 0x0420, 0x010C, 2, 0x08B4, 1, 0) +MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0420, 0x010C, 4, 0x07F0, 0, 0) +MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0420, 0x010C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0420, 0x010C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0424, 0x0110, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0424, 0x0110, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10, 0x0424, 0x0110, 2, 0x08B0, 1, 0) +MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0424, 0x0110, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0424, 0x0110, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0428, 0x0114, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0428, 0x0114, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09, 0x0428, 0x0114, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0428, 0x0114, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0428, 0x0114, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x042C, 0x0118, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x042C, 0x0118, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08, 0x042C, 0x0118, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x042C, 0x0118, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x042C, 0x0118, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0430, 0x011C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0430, 0x011C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07, 0x0430, 0x011C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0430, 0x011C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0430, 0x011C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0434, 0x0120, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0434, 0x0120, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06, 0x0434, 0x0120, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0434, 0x0120, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0434, 0x0120, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x0438, 0x0124, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x0438, 0x0124, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05, 0x0438, 0x0124, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x0438, 0x0124, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x0438, 0x0124, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x043C, 0x0128, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x043C, 0x0128, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04, 0x043C, 0x0128, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x043C, 0x0128, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x043C, 0x0128, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0440, 0x012C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0440, 0x012C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03, 0x0440, 0x012C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0440, 0x012C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0440, 0x012C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0444, 0x0130, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0444, 0x0130, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02, 0x0444, 0x0130, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0444, 0x0130, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0444, 0x0130, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x0448, 0x0134, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x0448, 0x0134, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01, 0x0448, 0x0134, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x0448, 0x0134, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x0448, 0x0134, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x044C, 0x0138, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x044C, 0x0138, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00, 0x044C, 0x0138, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x044C, 0x0138, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x044C, 0x0138, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x0450, 0x013C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x0450, 0x013C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN, 0x0450, 0x013C, 2, 0x08D8, 1, 0) +MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x0450, 0x013C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x0450, 0x013C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0454, 0x0140, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0454, 0x0140, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC, 0x0454, 0x0140, 2, 0x08DC, 1, 0) +MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0454, 0x0140, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0454, 0x0140, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0458, 0x0144, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0458, 0x0144, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC, 0x0458, 0x0144, 2, 0x08E4, 1, 0) +MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0458, 0x0144, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0458, 0x0144, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x045C, 0x0148, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x045C, 0x0148, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x045C, 0x0148, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x045C, 0x0148, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x0460, 0x014C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x0460, 0x014C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x0460, 0x014C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x0460, 0x014C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0464, 0x0150, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0464, 0x0150, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0464, 0x0150, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0464, 0x0150, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0464, 0x0150, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x0468, 0x0154, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x0468, 0x0154, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x0468, 0x0154, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x0468, 0x0154, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x046C, 0x0158, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x046C, 0x0158, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x0470, 0x015C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x0474, 0x0160, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x0474, 0x0160, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02, 0x0478, 0x0164, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x0478, 0x0164, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x0478, 0x0164, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03, 0x047C, 0x0168, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x047C, 0x0168, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x047C, 0x0168, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x0480, 0x016C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04, 0x0480, 0x016C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x0480, 0x016C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x0480, 0x016C, 3, 0x094C, 0, 0) +MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00, 0x0484, 0x0170, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x0484, 0x0170, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x0484, 0x0170, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01, 0x0488, 0x0174, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x0488, 0x0174, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x0488, 0x0174, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02, 0x048C, 0x0178, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x048C, 0x0178, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x048C, 0x0178, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03, 0x0490, 0x017C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0490, 0x017C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0490, 0x017C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04, 0x0494, 0x0180, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x0494, 0x0180, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x0494, 0x0180, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05, 0x0498, 0x0184, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0498, 0x0184, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0498, 0x0184, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0498, 0x0184, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06, 0x049C, 0x0188, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x049C, 0x0188, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x049C, 0x0188, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x049C, 0x0188, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07, 0x04A0, 0x018C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x04A0, 0x018C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x04A0, 0x018C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08, 0x04A4, 0x0190, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x04A4, 0x0190, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x04A4, 0x0190, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x04A4, 0x0190, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09, 0x04A8, 0x0194, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x04A8, 0x0194, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x04A8, 0x0194, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x04A8, 0x0194, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10, 0x04AC, 0x0198, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x04AC, 0x0198, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11, 0x04B0, 0x019C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x04B0, 0x019C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12, 0x04B4, 0x01A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x04B4, 0x01A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13, 0x04B8, 0x01A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x04B8, 0x01A4, 3, 0x07D8, 1, 0) +MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x04B8, 0x01A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14, 0x04BC, 0x01A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x04BC, 0x01A8, 3, 0x07D4, 1, 0) +MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x04BC, 0x01A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15, 0x04C0, 0x01AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x04C0, 0x01AC, 2, 0x0804, 1, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x04C0, 0x01AC, 3, 0x0820, 1, 0) +MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x04C0, 0x01AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16, 0x04C4, 0x01B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x04C4, 0x01B0, 2, 0x0818, 1, 0) +MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x04C4, 0x01B0, 3, 0x07DC, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x04C4, 0x01B0, 4, 0x090C, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x04C4, 0x01B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17, 0x04C8, 0x01B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x04C8, 0x01B4, 2, 0x0814, 1, 0) +MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x04C8, 0x01B4, 3, 0x07D0, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x04C8, 0x01B4, 4, 0x0910, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x04C8, 0x01B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18, 0x04CC, 0x01B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x04CC, 0x01B8, 2, 0x081C, 1, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x04CC, 0x01B8, 3, 0x07E0, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x04CC, 0x01B8, 4, 0x07C0, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x04CC, 0x01B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x04CC, 0x01B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19, 0x04D0, 0x01BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x04D0, 0x01BC, 2, 0x0810, 1, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x04D0, 0x01BC, 3, 0x07CC, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x04D0, 0x01BC, 4, 0x07BC, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x04D0, 0x01BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x04D0, 0x01BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20, 0x04D4, 0x01C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x04D4, 0x01C0, 2, 0x07F4, 1, 0) +MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x04D4, 0x01C0, 3, 0x07C4, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x04D4, 0x01C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21, 0x04D8, 0x01C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x04D8, 0x01C4, 2, 0x07FC, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x04D8, 0x01C4, 3, 0x07B8, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x04D8, 0x01C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22, 0x04DC, 0x01C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x04DC, 0x01C8, 2, 0x07F8, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x04DC, 0x01C8, 3, 0x07C8, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x04DC, 0x01C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23, 0x04E0, 0x01CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x04E0, 0x01CC, 2, 0x0800, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x04E0, 0x01CC, 3, 0x07B4, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x04E0, 0x01CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x04E4, 0x01D0, 2, 0x086C, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x04E4, 0x01D0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x04E4, 0x01D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x04E4, 0x01D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x04E8, 0x01D4, 2, 0x085C, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x04E8, 0x01D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x04EC, 0x01D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x04EC, 0x01D8, 2, 0x0864, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x04EC, 0x01D8, 3, 0x0914, 1, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x04EC, 0x01D8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x04EC, 0x01D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x04F0, 0x01DC, 1, 0x0858, 1, 0) +MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x04F0, 0x01DC, 2, 0x0870, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x04F0, 0x01DC, 3, 0x0918, 1, 0) +MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x04F0, 0x01DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x04F4, 0x01E0, 0, 0x0908, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x04F4, 0x01E0, 1, 0x084C, 1, 0) +MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x04F4, 0x01E0, 2, 0x0860, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x04F4, 0x01E0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x04F4, 0x01E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x04F8, 0x01E4, 1, 0x0848, 1, 0) +MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x04F8, 0x01E4, 2, 0x0868, 0, 0) +MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x04F8, 0x01E4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x04F8, 0x01E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x04FC, 0x01E8, 2, 0x0880, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x04FC, 0x01E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x0500, 0x01EC, 0, 0x0900, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x0500, 0x01EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x0500, 0x01EC, 2, 0x087C, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x0500, 0x01EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x0500, 0x01EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x0504, 0x01F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x0504, 0x01F0, 2, 0x0884, 0, 0) +MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x0504, 0x01F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x0508, 0x01F4, 0, 0x0904, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x0508, 0x01F4, 2, 0x0888, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x0508, 0x01F4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x0508, 0x01F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x05C8, 0x01F8, 0, 0x07F4, 2, 0) +MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x05C8, 0x01F8, 1, 0x0854, 1, 0) +MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x05C8, 0x01F8, 2, 0x07DC, 1, 0) +MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x05C8, 0x01F8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x05C8, 0x01F8, 4, 0x0938, 0, 0) +MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x05C8, 0x01F8, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x05CC, 0x01FC, 0, 0x07FC, 2, 0) +MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x05CC, 0x01FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x05CC, 0x01FC, 2, 0x07D0, 1, 0) +MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x05CC, 0x01FC, 4, 0x0938, 1, 0) +MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x05CC, 0x01FC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x05D0, 0x0200, 0, 0x07F8, 2, 0) +MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x05D0, 0x0200, 1, 0x0840, 1, 0) +MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x05D0, 0x0200, 2, 0x07E0, 1, 0) +MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x05D0, 0x0200, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x05D0, 0x0200, 4, 0x0940, 0, 0) +MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x05D0, 0x0200, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x05D0, 0x0200, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x05D4, 0x0204, 0, 0x0800, 2, 0) +MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x05D4, 0x0204, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x05D4, 0x0204, 2, 0x07CC, 1, 0) +MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x05D4, 0x0204, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x05D4, 0x0204, 4, 0x0940, 1, 0) +MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x05D4, 0x0204, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x05D4, 0x0204, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x05D8, 0x0208, 0, 0x0804, 2, 0) +MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x05D8, 0x0208, 1, 0x0850, 1, 0) +MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x05D8, 0x0208, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x05D8, 0x0208, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x05D8, 0x0208, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x05D8, 0x0208, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x05DC, 0x020C, 0, 0x0808, 1, 0) +MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x05DC, 0x020C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x05DC, 0x020C, 2, 0x07E4, 0, 0) +MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x05DC, 0x020C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x05DC, 0x020C, 6, 0x088C, 1, 0) +MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x05E0, 0x0210, 0, 0x080C, 1, 0) +MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x05E0, 0x0210, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x05E0, 0x0210, 2, 0x0890, 1, 0) +MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x05E0, 0x0210, 20, 0x08A0, 1, 0) +MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x05E0, 0x0210, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x05E0, 0x0210, 6, 0x0914, 2, 0) +MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x05E4, 0x0214, 1, 0x07B0, 0, 0) +MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x05E4, 0x0214, 2, 0x0894, 1, 0) +MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x05E4, 0x0214, 20, 0x08A4, 1, 0) +MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x05E4, 0x0214, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x05E4, 0x0214, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x05E8, 0x0218, 0, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x05E8, 0x0218, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x05E8, 0x0218, 2, 0x0944, 1, 0) +MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x05E8, 0x0218, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x05E8, 0x0218, 4, 0x093C, 0, 0) +MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x05E8, 0x0218, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x05EC, 0x021C, 0, 0x07E8, 0, 0) +MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x05EC, 0x021C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x05EC, 0x021C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x05EC, 0x021C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x05EC, 0x021C, 4, 0x093C, 1, 0) +MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x05EC, 0x021C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05F0, 0x0220, 0, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05F0, 0x0220, 2, 0x08E8, 0, 0) +MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05F0, 0x0220, 3, 0x07B0, 1, 0) +MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05F0, 0x0220, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05F0, 0x0220, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05F0, 0x0220, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05F0, 0x0220, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05F4, 0x0224, 0, 0x086C, 1, 0) +MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05F4, 0x0224, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05F4, 0x0224, 2, 0x08F4, 0, 0) +MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05F4, 0x0224, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05F4, 0x0224, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05F4, 0x0224, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05F4, 0x0224, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x05F8, 0x0228, 0, 0x085C, 1, 0) +MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x05F8, 0x0228, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x05F8, 0x0228, 2, 0x08EC, 0, 0) +MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x05F8, 0x0228, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x05F8, 0x0228, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x05F8, 0x0228, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__SD1_WP, 0x05F8, 0x0228, 6, 0x094C, 1, 0) +MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05FC, 0x022C, 0, 0x0864, 1, 0) +MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05FC, 0x022C, 18, 0x08A8, 1, 0) +MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05FC, 0x022C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05FC, 0x022C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05FC, 0x022C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05FC, 0x022C, 6, 0x0948, 1, 0) +MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05FC, 0x022C, 7, 0x0900, 1, 0) +MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0600, 0x0230, 0, 0x0870, 1, 0) +MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0600, 0x0230, 18, 0x08AC, 1, 0) +MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0600, 0x0230, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0600, 0x0230, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0600, 0x0230, 7, 0x0908, 1, 0) +MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x0604, 0x0234, 0, 0x0860, 1, 0) +MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x0604, 0x0234, 2, 0x08F8, 1, 0) +MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x0604, 0x0234, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__SD2_WP, 0x0604, 0x0234, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x0604, 0x0234, 7, 0x0904, 1, 0) +MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x0608, 0x0238, 0, 0x0868, 1, 0) +MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x0608, 0x0238, 2, 0x08F0, 1, 0) +MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x0608, 0x0238, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x0608, 0x0238, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x060C, 0x023C, 0, 0x087C, 1, 0) +MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x060C, 0x023C, 2, 0x08FC, 1, 0) +MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x060C, 0x023C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x060C, 0x023C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x060C, 0x023C, 22, 0x08A8, 2, 0) +MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x060C, 0x023C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0610, 0x0240, 0, 0x0884, 1, 0) +MX6_PAD_DECL(GPIO_7__ECSPI5_RDY, 0x0610, 0x0240, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0610, 0x0240, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0610, 0x0240, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0610, 0x0240, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0610, 0x0240, 4, 0x0928, 2, 0) +MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0610, 0x0240, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0610, 0x0240, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0610, 0x0240, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x0614, 0x0244, 0, 0x0888, 1, 0) +MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x0614, 0x0244, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x0614, 0x0244, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x0614, 0x0244, 3, 0x07E4, 1, 0) +MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x0614, 0x0244, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x0614, 0x0244, 4, 0x0928, 3, 0) +MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x0614, 0x0244, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x0614, 0x0244, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x0618, 0x0248, 0, 0x0880, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x0618, 0x0248, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x0618, 0x0248, 4, 0x0914, 3, 0) +MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x0618, 0x0248, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x0618, 0x0248, 22, 0x08AC, 2, 0) +MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x0618, 0x0248, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x061C, 0x024C, 0, 0x0874, 0, 0) +MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x061C, 0x024C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x061C, 0x024C, 2, 0x07F0, 1, 0) +MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x061C, 0x024C, 3, 0x090C, 1, 0) +MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x061C, 0x024C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x061C, 0x024C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x0620, 0x0250, 0, 0x0878, 0, 0) +MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x0620, 0x0250, 1, 0x0844, 1, 0) +MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x0620, 0x0250, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x0620, 0x0250, 3, 0x0910, 1, 0) +MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x0620, 0x0250, 4, 0x07B0, 2, 0) +MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x0620, 0x0250, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x0620, 0x0250, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x0624, 0x0254, 0, 0x08E8, 1, 0) +MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x0624, 0x0254, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x0624, 0x0254, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x0624, 0x0254, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x0624, 0x0254, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x0624, 0x0254, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x0624, 0x0254, 6, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x0628, 0x0258, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x0628, 0x0258, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x062C, 0x025C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x062C, 0x025C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x062C, 0x025C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x062C, 0x025C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x0630, 0x0260, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x0630, 0x0260, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x0630, 0x0260, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x0634, 0x0264, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x0634, 0x0264, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x0634, 0x0264, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0638, 0x0268, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0638, 0x0268, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0638, 0x0268, 2, 0x07F4, 3, 0) +MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0638, 0x0268, 3, 0x08E8, 2, 0) +MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0638, 0x0268, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0638, 0x0268, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0638, 0x0268, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x063C, 0x026C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x063C, 0x026C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x063C, 0x026C, 2, 0x07FC, 3, 0) +MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x063C, 0x026C, 3, 0x08F4, 1, 0) +MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x063C, 0x026C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x063C, 0x026C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x063C, 0x026C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0640, 0x0270, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0640, 0x0270, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0640, 0x0270, 2, 0x07F8, 3, 0) +MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0640, 0x0270, 3, 0x08EC, 1, 0) +MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0640, 0x0270, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0640, 0x0270, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0640, 0x0270, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0644, 0x0274, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0644, 0x0274, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0644, 0x0274, 2, 0x0800, 3, 0) +MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0644, 0x0274, 3, 0x08F8, 2, 0) +MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0644, 0x0274, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0644, 0x0274, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0644, 0x0274, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0648, 0x0278, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0648, 0x0278, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0648, 0x0278, 2, 0x0810, 2, 0) +MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0648, 0x0278, 3, 0x08F0, 2, 0) +MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0648, 0x0278, 20, 0x089C, 1, 0) +MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0648, 0x0278, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0648, 0x0278, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x064C, 0x027C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x064C, 0x027C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x064C, 0x027C, 2, 0x0818, 2, 0) +MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x064C, 0x027C, 3, 0x08FC, 2, 0) +MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x064C, 0x027C, 20, 0x0898, 1, 0) +MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x064C, 0x027C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x064C, 0x027C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0650, 0x0280, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0650, 0x0280, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0650, 0x0280, 2, 0x0814, 2, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0650, 0x0280, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0650, 0x0280, 3, 0x0920, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0650, 0x0280, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0650, 0x0280, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0654, 0x0284, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0654, 0x0284, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0654, 0x0284, 2, 0x081C, 2, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0654, 0x0284, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0654, 0x0284, 3, 0x0920, 1, 0) +MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0654, 0x0284, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0654, 0x0284, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0658, 0x0288, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0658, 0x0288, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0658, 0x0288, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0658, 0x0288, 3, 0x0938, 2, 0) +MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0658, 0x0288, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0658, 0x0288, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x065C, 0x028C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x065C, 0x028C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x065C, 0x028C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x065C, 0x028C, 3, 0x0938, 3, 0) +MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x065C, 0x028C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x065C, 0x028C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0660, 0x0290, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0660, 0x0290, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0660, 0x0290, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0660, 0x0290, 3, 0x0940, 2, 0) +MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0660, 0x0290, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0660, 0x0290, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0664, 0x0294, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0664, 0x0294, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0664, 0x0294, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0664, 0x0294, 3, 0x0940, 3, 0) +MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0664, 0x0294, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0664, 0x0294, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0668, 0x0298, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0668, 0x0298, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0668, 0x0298, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0668, 0x0298, 3, 0x0934, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0668, 0x0298, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0668, 0x0298, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x066C, 0x029C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x066C, 0x029C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x066C, 0x029C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x066C, 0x029C, 3, 0x0934, 1, 0) +MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x066C, 0x029C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x066C, 0x029C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0670, 0x02A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0670, 0x02A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0670, 0x02A0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0670, 0x02A0, 3, 0x093C, 2, 0) +MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0670, 0x02A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0670, 0x02A0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0674, 0x02A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0674, 0x02A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0674, 0x02A4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0674, 0x02A4, 3, 0x093C, 3, 0) +MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0674, 0x02A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0690, 0x02A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0690, 0x02A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0690, 0x02A8, 1, 0x0920, 2, 0) +MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0690, 0x02A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0694, 0x02AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0694, 0x02AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0694, 0x02AC, 1, 0x0920, 3, 0) +MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0694, 0x02AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0698, 0x02B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0698, 0x02B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0698, 0x02B0, 1, 0x0928, 4, 0) +MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0698, 0x02B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0) +MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0) +MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06A4, 0x02BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06A4, 0x02BC, 1, 0x0924, 3, 0) +MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06A4, 0x02BC, 2, 0x07E4, 2, 0) +MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06A8, 0x02C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06A8, 0x02C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06A8, 0x02C0, 1, 0x091C, 2, 0) +MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06A8, 0x02C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x06AC, 0x02C4, 1, 0x091C, 3, 0) +MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x06AC, 0x02C4, 2, 0x07E8, 1, 0) +MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x06B4, 0x02CC, 1, 0x092C, 4, 0) +MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x06B8, 0x02D0, 1, 0x092C, 5, 0) +MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5, 0x06C4, 0x02DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x06C8, 0x02E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01, 0x06C8, 0x02E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x06D0, 0x02E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x06D4, 0x02EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x06D4, 0x02EC, 2, 0x0874, 1, 0) +MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x06D8, 0x02F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0) +MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0) +MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x06E0, 0x02F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x06E0, 0x02F8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x06E0, 0x02F8, 2, 0x0930, 3, 0) +MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x06E4, 0x02FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x06E8, 0x0300, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x06E8, 0x0300, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x06E8, 0x0300, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x06EC, 0x0304, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x06EC, 0x0304, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x06EC, 0x0304, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x06F0, 0x0308, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x06F0, 0x0308, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x06F0, 0x0308, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x06F4, 0x030C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x06F4, 0x030C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x06F4, 0x030C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x06F8, 0x0310, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x06F8, 0x0310, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x06F8, 0x0310, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x06FC, 0x0314, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x06FC, 0x0314, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x06FC, 0x0314, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0700, 0x0318, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0700, 0x0318, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0700, 0x0318, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0704, 0x031C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0704, 0x031C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0704, 0x031C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x0708, 0x0320, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x0708, 0x0320, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x0708, 0x0320, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x070C, 0x0324, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x070C, 0x0324, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x070C, 0x0324, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0710, 0x0328, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0710, 0x0328, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0714, 0x032C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0714, 0x032C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0714, 0x032C, 2, 0x0928, 6, 0) +MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0714, 0x032C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x0718, 0x0330, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x0718, 0x0330, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x0718, 0x0330, 2, 0x0924, 4, 0) +MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x0718, 0x0330, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x071C, 0x0334, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x071C, 0x0334, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x071C, 0x0334, 2, 0x0924, 5, 0) +MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x071C, 0x0334, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0720, 0x0338, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0720, 0x0338, 2, 0x0928, 7, 0) +MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0720, 0x0338, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x0724, 0x033C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0, 0x0724, 0x033C, 1, 0x0834, 1, 0) +MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x0724, 0x033C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x0724, 0x033C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x0724, 0x033C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x0728, 0x0340, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO, 0x0728, 0x0340, 1, 0x082C, 1, 0) +MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x0728, 0x0340, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x0728, 0x0340, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x072C, 0x0344, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2, 0x072C, 0x0344, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x072C, 0x0344, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0) +MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x0730, 0x0348, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x0734, 0x034C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1, 0x0734, 0x034C, 1, 0x0838, 1, 0) +MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x0734, 0x034C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x0734, 0x034C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x0734, 0x034C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x0734, 0x034C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x0734, 0x034C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK, 0x0738, 0x0350, 1, 0x0828, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x0738, 0x0350, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x0738, 0x0350, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0) +MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0) +MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0) +MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0) +MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0) +MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0) +MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x0740, 0x0358, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x0744, 0x035C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3, 0x0744, 0x035C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x0744, 0x035C, 2, 0x08EC, 2, 0) +MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x0744, 0x035C, 3, 0x07C4, 1, 0) +MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x0744, 0x035C, 5, 0x0000, 0, 0) #endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index b39a354f39..9ded3d851c 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -10,13 +10,53 @@ #include enum { + MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0), + MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), + MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0), MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), + + MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0), + MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0), + MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0), + MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0), + MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0), + MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0), + MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0), + MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0), + MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), + MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h new file mode 100644 index 0000000000..150138d255 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX6SX_DDR_H__ +#define __ASM_ARCH_MX6SX_DDR_H__ + +#ifndef CONFIG_SOC_MX6SX +#error "wrong CPU" +#endif + +#define MX6_IOM_DRAM_DQM0 0x020e02ec +#define MX6_IOM_DRAM_DQM1 0x020e02f0 +#define MX6_IOM_DRAM_DQM2 0x020e02f4 +#define MX6_IOM_DRAM_DQM3 0x020e02f8 + +#define MX6_IOM_DRAM_RAS 0x020e02fc +#define MX6_IOM_DRAM_CAS 0x020e0300 +#define MX6_IOM_DRAM_SDODT0 0x020e0310 +#define MX6_IOM_DRAM_SDODT1 0x020e0314 +#define MX6_IOM_DRAM_SDBA2 0x020e0320 +#define MX6_IOM_DRAM_SDCKE0 0x020e0324 +#define MX6_IOM_DRAM_SDCKE1 0x020e0328 +#define MX6_IOM_DRAM_SDCLK_0 0x020e032c +#define MX6_IOM_DRAM_RESET 0x020e0340 + +#define MX6_IOM_DRAM_SDQS0 0x020e0330 +#define MX6_IOM_DRAM_SDQS1 0x020e0334 +#define MX6_IOM_DRAM_SDQS2 0x020e0338 +#define MX6_IOM_DRAM_SDQS3 0x020e033c + +#define MX6_IOM_GRP_ADDDS 0x020e05f4 +#define MX6_IOM_DDRMODE_CTL 0x020e05f8 +#define MX6_IOM_GRP_DDRPKE 0x020e05fc +#define MX6_IOM_GRP_DDRMODE 0x020e0608 +#define MX6_IOM_GRP_B0DS 0x020e060c +#define MX6_IOM_GRP_B1DS 0x020e0610 +#define MX6_IOM_GRP_CTLDS 0x020e0614 +#define MX6_IOM_GRP_DDR_TYPE 0x020e0618 +#define MX6_IOM_GRP_B2DS 0x020e061c +#define MX6_IOM_GRP_B3DS 0x020e0620 + +#endif /*__ASM_ARCH_MX6SX_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h new file mode 100644 index 0000000000..7c6c1e844d --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -0,0 +1,1675 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX6_MX6_PINS_H__ +#define __ASM_ARCH_MX6_MX6_PINS_H__ + +#include + +enum { + MX6_PAD_GPIO1_IO00__I2C1_SCL = IOMUX_PAD(0x035C, 0x0014, IOMUX_CONFIG_SION | 0, 0x07A8, 1, 0), + MX6_PAD_GPIO1_IO00__USDHC1_VSELECT = IOMUX_PAD(0x035C, 0x0014, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SPDIF_LOCK = IOMUX_PAD(0x035C, 0x0014, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__CCM_WAIT = IOMUX_PAD(0x035C, 0x0014, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__WDOG1_WDOG_ANY = IOMUX_PAD(0x035C, 0x0014, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__GPIO1_IO_0 = IOMUX_PAD(0x035C, 0x0014, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 = IOMUX_PAD(0x035C, 0x0014, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__PHY_DTB_1 = IOMUX_PAD(0x035C, 0x0014, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO01__I2C1_SDA = IOMUX_PAD(0x0360, 0x0018, IOMUX_CONFIG_SION | 0, 0x07AC, 1, 0), + MX6_PAD_GPIO1_IO01__USDHC1_RESET_B = IOMUX_PAD(0x0360, 0x0018, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SPDIF_SR_CLK = IOMUX_PAD(0x0360, 0x0018, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__CCM_STOP = IOMUX_PAD(0x0360, 0x0018, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__WDOG3_WDOG_B = IOMUX_PAD(0x0360, 0x0018, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__GPIO1_IO_1 = IOMUX_PAD(0x0360, 0x0018, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL = IOMUX_PAD(0x0360, 0x0018, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__PHY_DTB_0 = IOMUX_PAD(0x0360, 0x0018, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO02__I2C2_SCL = IOMUX_PAD(0x0364, 0x001C, IOMUX_CONFIG_SION | 0, 0x07B0, 1, 0), + MX6_PAD_GPIO1_IO02__USDHC1_CD_B = IOMUX_PAD(0x0364, 0x001C, 1, 0x0864, 1, 0), + MX6_PAD_GPIO1_IO02__CSI2_MCLK = IOMUX_PAD(0x0364, 0x001C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0364, 0x001C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0364, 0x001C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__GPIO1_IO_2 = IOMUX_PAD(0x0364, 0x001C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__CCM_REF_EN_B = IOMUX_PAD(0x0364, 0x001C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__PHY_TDI = IOMUX_PAD(0x0364, 0x001C, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO03__I2C2_SDA = IOMUX_PAD(0x0368, 0x0020, IOMUX_CONFIG_SION | 0, 0x07B4, 1, 0), + MX6_PAD_GPIO1_IO03__USDHC1_WP = IOMUX_PAD(0x0368, 0x0020, 1, 0x0868, 1, 0), + MX6_PAD_GPIO1_IO03__ENET1_REF_CLK_25M = IOMUX_PAD(0x0368, 0x0020, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK = IOMUX_PAD(0x0368, 0x0020, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__WDOG2_WDOG_B = IOMUX_PAD(0x0368, 0x0020, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__GPIO1_IO_3 = IOMUX_PAD(0x0368, 0x0020, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_PLL3_BYP = IOMUX_PAD(0x0368, 0x0020, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__PHY_TCK = IOMUX_PAD(0x0368, 0x0020, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO04__UART1_TX = IOMUX_PAD(0x036C, 0x0024, 0, 0x0830, 0, 0), + MX6_PAD_GPIO1_IO04__USDHC2_RESET_B = IOMUX_PAD(0x036C, 0x0024, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET1_MDC = IOMUX_PAD(0x036C, 0x0024, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__OSC32K_32K_OUT = IOMUX_PAD(0x036C, 0x0024, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET2_REF_CLK2 = IOMUX_PAD(0x036C, 0x0024, 4, 0x076C, 0, 0), + MX6_PAD_GPIO1_IO04__GPIO1_IO_4 = IOMUX_PAD(0x036C, 0x0024, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__CCM_PLL2_BYP = IOMUX_PAD(0x036C, 0x0024, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__PHY_TMS = IOMUX_PAD(0x036C, 0x0024, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO05__UART1_RX = IOMUX_PAD(0x0370, 0x0028, 0, 0x0830, 1, 0), + MX6_PAD_GPIO1_IO05__USDHC2_VSELECT = IOMUX_PAD(0x0370, 0x0028, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET1_MDIO = IOMUX_PAD(0x0370, 0x0028, 2, 0x0764, 0, 0), + MX6_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0370, 0x0028, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET1_REF_CLK1 = IOMUX_PAD(0x0370, 0x0028, 4, 0x0760, 0, 0), + MX6_PAD_GPIO1_IO05__GPIO1_IO_5 = IOMUX_PAD(0x0370, 0x0028, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__SRC_TESTER_ACK = IOMUX_PAD(0x0370, 0x0028, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__PHY_TDO = IOMUX_PAD(0x0370, 0x0028, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO06__UART2_TX = IOMUX_PAD(0x0374, 0x002C, 0, 0x0838, 0, 0), + MX6_PAD_GPIO1_IO06__USDHC2_CD_B = IOMUX_PAD(0x0374, 0x002C, 1, 0x086C, 1, 0), + MX6_PAD_GPIO1_IO06__ENET2_MDC = IOMUX_PAD(0x0374, 0x002C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CSI1_MCLK = IOMUX_PAD(0x0374, 0x002C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_RTS_B = IOMUX_PAD(0x0374, 0x002C, 4, 0x082C, 0, 0), + MX6_PAD_GPIO1_IO06__GPIO1_IO_6 = IOMUX_PAD(0x0374, 0x002C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__SRC_ANY_PU_RESET = IOMUX_PAD(0x0374, 0x002C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x0374, 0x002C, 7, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO07__UART2_RX = IOMUX_PAD(0x0378, 0x0030, 0, 0x0838, 1, 0), + MX6_PAD_GPIO1_IO07__USDHC2_WP = IOMUX_PAD(0x0378, 0x0030, 1, 0x0870, 1, 0), + MX6_PAD_GPIO1_IO07__ENET2_MDIO = IOMUX_PAD(0x0378, 0x0030, 2, 0x0770, 0, 0), + MX6_PAD_GPIO1_IO07__AUDMUX_MCLK = IOMUX_PAD(0x0378, 0x0030, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__UART1_CTS_B = IOMUX_PAD(0x0378, 0x0030, 4, 0x082C, 1, 0), + MX6_PAD_GPIO1_IO07__GPIO1_IO_7 = IOMUX_PAD(0x0378, 0x0030, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__SRC_EARLY_RESET = IOMUX_PAD(0x0378, 0x0030, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__DCIC2_OUT = IOMUX_PAD(0x0378, 0x0030, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__VDEC_DEBUG_44 = IOMUX_PAD(0x0378, 0x0030, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO08__USB_OTG1_OC = IOMUX_PAD(0x037C, 0x0034, 0, 0x0860, 0, 0), + MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x037C, 0x0034, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x037C, 0x0034, 2, 0x081C, 0, 0), + MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x037C, 0x0034, 3, 0x069C, 1, 0), + MX6_PAD_GPIO1_IO08__UART2_RTS_B = IOMUX_PAD(0x037C, 0x0034, 4, 0x0834, 0, 0), + MX6_PAD_GPIO1_IO08__GPIO1_IO_8 = IOMUX_PAD(0x037C, 0x0034, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SRC_SYSTEM_RESET = IOMUX_PAD(0x037C, 0x0034, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__DCIC1_OUT = IOMUX_PAD(0x037C, 0x0034, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__VDEC_DEBUG_43 = IOMUX_PAD(0x037C, 0x0034, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR = IOMUX_PAD(0x0380, 0x0038, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__WDOG2_WDOG_B = IOMUX_PAD(0x0380, 0x0038, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0380, 0x0038, 2, 0x0820, 0, 0), + MX6_PAD_GPIO1_IO09__CCM_OUT0 = IOMUX_PAD(0x0380, 0x0038, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART2_CTS_B = IOMUX_PAD(0x0380, 0x0038, 4, 0x0834, 1, 0), + MX6_PAD_GPIO1_IO09__GPIO1_IO_9 = IOMUX_PAD(0x0380, 0x0038, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SRC_INT_BOOT = IOMUX_PAD(0x0380, 0x0038, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 = IOMUX_PAD(0x0380, 0x0038, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__VDEC_DEBUG_42 = IOMUX_PAD(0x0380, 0x0038, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID = IOMUX_PAD(0x0384, 0x003C, 0, 0x0624, 0, 0), + MX6_PAD_GPIO1_IO10__SPDIF_EXT_CLK = IOMUX_PAD(0x0384, 0x003C, 1, 0x0828, 0, 0), + MX6_PAD_GPIO1_IO10__PWM1_OUT = IOMUX_PAD(0x0384, 0x003C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__CCM_OUT1 = IOMUX_PAD(0x0384, 0x003C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__CSI1_FIELD = IOMUX_PAD(0x0384, 0x003C, 4, 0x070C, 1, 0), + MX6_PAD_GPIO1_IO10__GPIO1_IO_10 = IOMUX_PAD(0x0384, 0x003C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__CSU_CSU_INT_DEB = IOMUX_PAD(0x0384, 0x003C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 = IOMUX_PAD(0x0384, 0x003C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO10__VDEC_DEBUG_41 = IOMUX_PAD(0x0384, 0x003C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO11__USB_OTG2_OC = IOMUX_PAD(0x0388, 0x0040, 0, 0x085C, 0, 0), + MX6_PAD_GPIO1_IO11__SPDIF_IN = IOMUX_PAD(0x0388, 0x0040, 1, 0x0824, 2, 0), + MX6_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x0388, 0x0040, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__CCM_CLKO1 = IOMUX_PAD(0x0388, 0x0040, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__MLB_DATA = IOMUX_PAD(0x0388, 0x0040, 4, 0x07EC, 0, 0), + MX6_PAD_GPIO1_IO11__GPIO1_IO_11 = IOMUX_PAD(0x0388, 0x0040, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0388, 0x0040, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 = IOMUX_PAD(0x0388, 0x0040, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO11__VDEC_DEBUG_40 = IOMUX_PAD(0x0388, 0x0040, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR = IOMUX_PAD(0x038C, 0x0044, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__SPDIF_OUT = IOMUX_PAD(0x038C, 0x0044, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__PWM3_OUT = IOMUX_PAD(0x038C, 0x0044, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__CCM_CLKO2 = IOMUX_PAD(0x038C, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__MLB_CLK = IOMUX_PAD(0x038C, 0x0044, 4, 0x07E8, 0, 0), + MX6_PAD_GPIO1_IO12__GPIO1_IO_12 = IOMUX_PAD(0x038C, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x038C, 0x0044, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 = IOMUX_PAD(0x038C, 0x0044, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO12__VDEC_DEBUG_39 = IOMUX_PAD(0x038C, 0x0044, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO13__WDOG1_WDOG_ANY = IOMUX_PAD(0x0390, 0x0048, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__ANATOP_OTG2_ID = IOMUX_PAD(0x0390, 0x0048, 1, 0x0628, 0, 0), + MX6_PAD_GPIO1_IO13__PWM4_OUT = IOMUX_PAD(0x0390, 0x0048, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__CCM_OUT2 = IOMUX_PAD(0x0390, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__MLB_SIG = IOMUX_PAD(0x0390, 0x0048, 4, 0x07F0, 0, 0), + MX6_PAD_GPIO1_IO13__GPIO1_IO_13 = IOMUX_PAD(0x0390, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x0390, 0x0048, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 = IOMUX_PAD(0x0390, 0x0048, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO13__VDEC_DEBUG_38 = IOMUX_PAD(0x0390, 0x0048, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA00__CSI1_DATA_2 = IOMUX_PAD(0x0394, 0x004C, 0, 0x06A8, 0, 0), + MX6_PAD_CSI_DATA00__ESAI_TX_CLK = IOMUX_PAD(0x0394, 0x004C, 1, 0x078C, 1, 0), + MX6_PAD_CSI_DATA00__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0394, 0x004C, 2, 0x0684, 1, 0), + MX6_PAD_CSI_DATA00__I2C1_SCL = IOMUX_PAD(0x0394, 0x004C, 3, 0x07A8, 0, 0), + MX6_PAD_CSI_DATA00__UART6_RI_B = IOMUX_PAD(0x0394, 0x004C, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__GPIO1_IO_14 = IOMUX_PAD(0x0394, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__WEIM_DATA_23 = IOMUX_PAD(0x0394, 0x004C, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__SAI1_TX_BCLK = IOMUX_PAD(0x0394, 0x004C, 7, 0x0800, 0, 0), + MX6_PAD_CSI_DATA00__VADC_DATA_4 = IOMUX_PAD(0x0394, 0x004C, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__MMDC_DEBUG_37 = IOMUX_PAD(0x0394, 0x004C, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA01__CSI1_DATA_3 = IOMUX_PAD(0x0398, 0x0050, 0, 0x06AC, 0, 0), + MX6_PAD_CSI_DATA01__ESAI_TX_FS = IOMUX_PAD(0x0398, 0x0050, 1, 0x077C, 1, 0), + MX6_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0398, 0x0050, 2, 0x0688, 1, 0), + MX6_PAD_CSI_DATA01__I2C1_SDA = IOMUX_PAD(0x0398, 0x0050, 3, 0x07AC, 0, 0), + MX6_PAD_CSI_DATA01__UART6_DSR_B = IOMUX_PAD(0x0398, 0x0050, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__GPIO1_IO_15 = IOMUX_PAD(0x0398, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__WEIM_DATA_22 = IOMUX_PAD(0x0398, 0x0050, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x0398, 0x0050, 7, 0x0804, 0, 0), + MX6_PAD_CSI_DATA01__VADC_DATA_5 = IOMUX_PAD(0x0398, 0x0050, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__MMDC_DEBUG_38 = IOMUX_PAD(0x0398, 0x0050, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA02__CSI1_DATA_4 = IOMUX_PAD(0x039C, 0x0054, 0, 0x06B0, 0, 0), + MX6_PAD_CSI_DATA02__ESAI_RX_CLK = IOMUX_PAD(0x039C, 0x0054, 1, 0x0788, 1, 0), + MX6_PAD_CSI_DATA02__AUDMUX_AUD6_RXC = IOMUX_PAD(0x039C, 0x0054, 2, 0x067C, 1, 0), + MX6_PAD_CSI_DATA02__KPP_COL_5 = IOMUX_PAD(0x039C, 0x0054, 3, 0x07C8, 0, 0), + MX6_PAD_CSI_DATA02__UART6_DTR_B = IOMUX_PAD(0x039C, 0x0054, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__GPIO1_IO_16 = IOMUX_PAD(0x039C, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__WEIM_DATA_21 = IOMUX_PAD(0x039C, 0x0054, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__SAI1_RX_BCLK = IOMUX_PAD(0x039C, 0x0054, 7, 0x07F4, 0, 0), + MX6_PAD_CSI_DATA02__VADC_DATA_6 = IOMUX_PAD(0x039C, 0x0054, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__MMDC_DEBUG_39 = IOMUX_PAD(0x039C, 0x0054, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA03__CSI1_DATA_5 = IOMUX_PAD(0x03A0, 0x0058, 0, 0x06B4, 0, 0), + MX6_PAD_CSI_DATA03__ESAI_RX_FS = IOMUX_PAD(0x03A0, 0x0058, 1, 0x0778, 1, 0), + MX6_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x03A0, 0x0058, 2, 0x0680, 1, 0), + MX6_PAD_CSI_DATA03__KPP_ROW_5 = IOMUX_PAD(0x03A0, 0x0058, 3, 0x07D4, 0, 0), + MX6_PAD_CSI_DATA03__UART6_DCD_B = IOMUX_PAD(0x03A0, 0x0058, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__GPIO1_IO_17 = IOMUX_PAD(0x03A0, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__WEIM_DATA_20 = IOMUX_PAD(0x03A0, 0x0058, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__SAI1_RX_SYNC = IOMUX_PAD(0x03A0, 0x0058, 7, 0x07FC, 0, 0), + MX6_PAD_CSI_DATA03__VADC_DATA_7 = IOMUX_PAD(0x03A0, 0x0058, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__MMDC_DEBUG_40 = IOMUX_PAD(0x03A0, 0x0058, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA04__CSI1_DATA_6 = IOMUX_PAD(0x03A4, 0x005C, 0, 0x06B8, 0, 0), + MX6_PAD_CSI_DATA04__ESAI_TX1 = IOMUX_PAD(0x03A4, 0x005C, 1, 0x0794, 1, 0), + MX6_PAD_CSI_DATA04__SPDIF_OUT = IOMUX_PAD(0x03A4, 0x005C, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__KPP_COL_6 = IOMUX_PAD(0x03A4, 0x005C, 3, 0x07CC, 0, 0), + MX6_PAD_CSI_DATA04__UART6_RX = IOMUX_PAD(0x03A4, 0x005C, 4, 0x0858, 0, 0), + MX6_PAD_CSI_DATA04__GPIO1_IO_18 = IOMUX_PAD(0x03A4, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__WEIM_DATA_19 = IOMUX_PAD(0x03A4, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__PWM5_OUT = IOMUX_PAD(0x03A4, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__VADC_DATA_8 = IOMUX_PAD(0x03A4, 0x005C, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__MMDC_DEBUG_41 = IOMUX_PAD(0x03A4, 0x005C, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA05__CSI1_DATA_7 = IOMUX_PAD(0x03A8, 0x0060, 0, 0x06BC, 0, 0), + MX6_PAD_CSI_DATA05__ESAI_TX4_RX1 = IOMUX_PAD(0x03A8, 0x0060, 1, 0x07A0, 1, 0), + MX6_PAD_CSI_DATA05__SPDIF_IN = IOMUX_PAD(0x03A8, 0x0060, 2, 0x0824, 1, 0), + MX6_PAD_CSI_DATA05__KPP_ROW_6 = IOMUX_PAD(0x03A8, 0x0060, 3, 0x07D8, 0, 0), + MX6_PAD_CSI_DATA05__UART6_TX = IOMUX_PAD(0x03A8, 0x0060, 4, 0x0858, 1, 0), + MX6_PAD_CSI_DATA05__GPIO1_IO_19 = IOMUX_PAD(0x03A8, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__WEIM_DATA_18 = IOMUX_PAD(0x03A8, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__PWM6_OUT = IOMUX_PAD(0x03A8, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__VADC_DATA_9 = IOMUX_PAD(0x03A8, 0x0060, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__MMDC_DEBUG_42 = IOMUX_PAD(0x03A8, 0x0060, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA06__CSI1_DATA_8 = IOMUX_PAD(0x03AC, 0x0064, 0, 0x06C0, 0, 0), + MX6_PAD_CSI_DATA06__ESAI_TX2_RX3 = IOMUX_PAD(0x03AC, 0x0064, 1, 0x0798, 1, 0), + MX6_PAD_CSI_DATA06__I2C4_SCL = IOMUX_PAD(0x03AC, 0x0064, 2, 0x07C0, 2, 0), + MX6_PAD_CSI_DATA06__KPP_COL_7 = IOMUX_PAD(0x03AC, 0x0064, 3, 0x07D0, 0, 0), + MX6_PAD_CSI_DATA06__UART6_RTS_B = IOMUX_PAD(0x03AC, 0x0064, 4, 0x0854, 0, 0), + MX6_PAD_CSI_DATA06__GPIO1_IO_20 = IOMUX_PAD(0x03AC, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__WEIM_DATA_17 = IOMUX_PAD(0x03AC, 0x0064, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__DCIC2_OUT = IOMUX_PAD(0x03AC, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__VADC_DATA_10 = IOMUX_PAD(0x03AC, 0x0064, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__MMDC_DEBUG_43 = IOMUX_PAD(0x03AC, 0x0064, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA07__CSI1_DATA_9 = IOMUX_PAD(0x03B0, 0x0068, 0, 0x06C4, 0, 0), + MX6_PAD_CSI_DATA07__ESAI_TX3_RX2 = IOMUX_PAD(0x03B0, 0x0068, 1, 0x079C, 1, 0), + MX6_PAD_CSI_DATA07__I2C4_SDA = IOMUX_PAD(0x03B0, 0x0068, 2, 0x07C4, 2, 0), + MX6_PAD_CSI_DATA07__KPP_ROW_7 = IOMUX_PAD(0x03B0, 0x0068, 3, 0x07DC, 0, 0), + MX6_PAD_CSI_DATA07__UART6_CTS_B = IOMUX_PAD(0x03B0, 0x0068, 4, 0x0854, 1, 0), + MX6_PAD_CSI_DATA07__GPIO1_IO_21 = IOMUX_PAD(0x03B0, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__WEIM_DATA_16 = IOMUX_PAD(0x03B0, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__DCIC1_OUT = IOMUX_PAD(0x03B0, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__VADC_DATA_11 = IOMUX_PAD(0x03B0, 0x0068, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__MMDC_DEBUG_44 = IOMUX_PAD(0x03B0, 0x0068, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_HSYNC__CSI1_HSYNC = IOMUX_PAD(0x03B4, 0x006C, 0, 0x0700, 0, 0), + MX6_PAD_CSI_HSYNC__ESAI_TX0 = IOMUX_PAD(0x03B4, 0x006C, 1, 0x0790, 1, 0), + MX6_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD = IOMUX_PAD(0x03B4, 0x006C, 2, 0x0678, 1, 0), + MX6_PAD_CSI_HSYNC__UART4_RTS_B = IOMUX_PAD(0x03B4, 0x006C, 3, 0x0844, 2, 0), + MX6_PAD_CSI_HSYNC__MQS_LEFT = IOMUX_PAD(0x03B4, 0x006C, 4, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__GPIO1_IO_22 = IOMUX_PAD(0x03B4, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__WEIM_DATA_25 = IOMUX_PAD(0x03B4, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__SAI1_TX_DATA_0 = IOMUX_PAD(0x03B4, 0x006C, 7, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__VADC_DATA_2 = IOMUX_PAD(0x03B4, 0x006C, 8, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__MMDC_DEBUG_35 = IOMUX_PAD(0x03B4, 0x006C, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_MCLK__CSI1_MCLK = IOMUX_PAD(0x03B8, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__ESAI_TX_HF_CLK = IOMUX_PAD(0x03B8, 0x0070, 1, 0x0784, 1, 0), + MX6_PAD_CSI_MCLK__OSC32K_32K_OUT = IOMUX_PAD(0x03B8, 0x0070, 2, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART4_RX = IOMUX_PAD(0x03B8, 0x0070, 3, 0x0848, 2, 0), + MX6_PAD_CSI_MCLK__ANATOP_32K_OUT = IOMUX_PAD(0x03B8, 0x0070, 4, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__GPIO1_IO_23 = IOMUX_PAD(0x03B8, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__WEIM_DATA_26 = IOMUX_PAD(0x03B8, 0x0070, 6, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__CSI1_FIELD = IOMUX_PAD(0x03B8, 0x0070, 7, 0x070C, 0, 0), + MX6_PAD_CSI_MCLK__VADC_DATA_1 = IOMUX_PAD(0x03B8, 0x0070, 8, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__MMDC_DEBUG_34 = IOMUX_PAD(0x03B8, 0x0070, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_PIXCLK__CSI1_PIXCLK = IOMUX_PAD(0x03BC, 0x0074, 0, 0x0704, 0, 0), + MX6_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK = IOMUX_PAD(0x03BC, 0x0074, 1, 0x0780, 1, 0), + MX6_PAD_CSI_PIXCLK__AUDMUX_MCLK = IOMUX_PAD(0x03BC, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__UART4_TX = IOMUX_PAD(0x03BC, 0x0074, 3, 0x0848, 3, 0), + MX6_PAD_CSI_PIXCLK__ANATOP_24M_OUT = IOMUX_PAD(0x03BC, 0x0074, 4, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__GPIO1_IO_24 = IOMUX_PAD(0x03BC, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__WEIM_DATA_27 = IOMUX_PAD(0x03BC, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK = IOMUX_PAD(0x03BC, 0x0074, 7, 0x0784, 2, 0), + MX6_PAD_CSI_PIXCLK__VADC_CLK = IOMUX_PAD(0x03BC, 0x0074, 8, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__MMDC_DEBUG_33 = IOMUX_PAD(0x03BC, 0x0074, 9, 0x0000, 0, 0), + + MX6_PAD_CSI_VSYNC__CSI1_VSYNC = IOMUX_PAD(0x03C0, 0x0078, 0, 0x0708, 0, 0), + MX6_PAD_CSI_VSYNC__ESAI_TX5_RX0 = IOMUX_PAD(0x03C0, 0x0078, 1, 0x07A4, 1, 0), + MX6_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x0078, 2, 0x0674, 1, 0), + MX6_PAD_CSI_VSYNC__UART4_CTS_B = IOMUX_PAD(0x03C0, 0x0078, 3, 0x0844, 3, 0), + MX6_PAD_CSI_VSYNC__MQS_RIGHT = IOMUX_PAD(0x03C0, 0x0078, 4, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__GPIO1_IO_25 = IOMUX_PAD(0x03C0, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__WEIM_DATA_24 = IOMUX_PAD(0x03C0, 0x0078, 6, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__SAI1_RX_DATA_0 = IOMUX_PAD(0x03C0, 0x0078, 7, 0x07F8, 0, 0), + MX6_PAD_CSI_VSYNC__VADC_DATA_3 = IOMUX_PAD(0x03C0, 0x0078, 8, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__MMDC_DEBUG_36 = IOMUX_PAD(0x03C0, 0x0078, 9, 0x0000, 0, 0), + + MX6_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x03C4, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__ENET2_MDC = IOMUX_PAD(0x03C4, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__AUDMUX_AUD4_TXC = IOMUX_PAD(0x03C4, 0x007C, 2, 0x0654, 1, 0), + MX6_PAD_ENET1_COL__UART1_RI_B = IOMUX_PAD(0x03C4, 0x007C, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__SPDIF_EXT_CLK = IOMUX_PAD(0x03C4, 0x007C, 4, 0x0828, 1, 0), + MX6_PAD_ENET1_COL__GPIO2_IO_0 = IOMUX_PAD(0x03C4, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__CSI2_DATA_23 = IOMUX_PAD(0x03C4, 0x007C, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__LCDIF2_DATA_16 = IOMUX_PAD(0x03C4, 0x007C, 7, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__VDEC_DEBUG_37 = IOMUX_PAD(0x03C4, 0x007C, 8, 0x0000, 0, 0), + MX6_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 = IOMUX_PAD(0x03C4, 0x007C, 9, 0x0000, 0, 0), + + MX6_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x03C8, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__ENET2_MDIO = IOMUX_PAD(0x03C8, 0x0080, 1, 0x0770, 1, 0), + MX6_PAD_ENET1_CRS__AUDMUX_AUD4_TXD = IOMUX_PAD(0x03C8, 0x0080, 2, 0x0648, 1, 0), + MX6_PAD_ENET1_CRS__UART1_DCD_B = IOMUX_PAD(0x03C8, 0x0080, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__SPDIF_LOCK = IOMUX_PAD(0x03C8, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__GPIO2_IO_1 = IOMUX_PAD(0x03C8, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__CSI2_DATA_22 = IOMUX_PAD(0x03C8, 0x0080, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__LCDIF2_DATA_17 = IOMUX_PAD(0x03C8, 0x0080, 7, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__VDEC_DEBUG_36 = IOMUX_PAD(0x03C8, 0x0080, 8, 0x0000, 0, 0), + MX6_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 = IOMUX_PAD(0x03C8, 0x0080, 9, 0x0000, 0, 0), + + MX6_PAD_ENET1_MDC__ENET1_MDC = IOMUX_PAD(0x03CC, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__ENET2_MDC = IOMUX_PAD(0x03CC, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x03CC, 0x0084, 2, 0x0638, 1, 0), + MX6_PAD_ENET1_MDC__ANATOP_24M_OUT = IOMUX_PAD(0x03CC, 0x0084, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__EPIT2_OUT = IOMUX_PAD(0x03CC, 0x0084, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__GPIO2_IO_2 = IOMUX_PAD(0x03CC, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__USB_OTG1_PWR = IOMUX_PAD(0x03CC, 0x0084, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_MDC__PWM7_OUT = IOMUX_PAD(0x03CC, 0x0084, 7, 0x0000, 0, 0), + + MX6_PAD_ENET1_MDIO__ENET1_MDIO = IOMUX_PAD(0x03D0, 0x0088, 0, 0x0764, 1, 0), + MX6_PAD_ENET1_MDIO__ENET2_MDIO = IOMUX_PAD(0x03D0, 0x0088, 1, 0x0770, 2, 0), + MX6_PAD_ENET1_MDIO__AUDMUX_MCLK = IOMUX_PAD(0x03D0, 0x0088, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_MDIO__OSC32K_32K_OUT = IOMUX_PAD(0x03D0, 0x0088, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_MDIO__EPIT1_OUT = IOMUX_PAD(0x03D0, 0x0088, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_MDIO__GPIO2_IO_3 = IOMUX_PAD(0x03D0, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_MDIO__USB_OTG1_OC = IOMUX_PAD(0x03D0, 0x0088, 6, 0x0860, 1, 0), + MX6_PAD_ENET1_MDIO__PWM8_OUT = IOMUX_PAD(0x03D0, 0x0088, 7, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x03D4, 0x008C, 0, 0x0768, 0, 0), + MX6_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M = IOMUX_PAD(0x03D4, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x03D4, 0x008C, 2, 0x0658, 1, 0), + MX6_PAD_ENET1_RX_CLK__UART1_DSR_B = IOMUX_PAD(0x03D4, 0x008C, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__SPDIF_OUT = IOMUX_PAD(0x03D4, 0x008C, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__GPIO2_IO_4 = IOMUX_PAD(0x03D4, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__CSI2_DATA_21 = IOMUX_PAD(0x03D4, 0x008C, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 = IOMUX_PAD(0x03D4, 0x008C, 7, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 = IOMUX_PAD(0x03D4, 0x008C, 8, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 = IOMUX_PAD(0x03D4, 0x008C, 9, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x03D8, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x03D8, 0x0090, 1, 0x0760, 1, 0), + MX6_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD = IOMUX_PAD(0x03D8, 0x0090, 2, 0x0644, 1, 0), + MX6_PAD_ENET1_TX_CLK__UART1_DTR_B = IOMUX_PAD(0x03D8, 0x0090, 3, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x03D8, 0x0090, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__GPIO2_IO_5 = IOMUX_PAD(0x03D8, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__CSI2_DATA_20 = IOMUX_PAD(0x03D8, 0x0090, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 = IOMUX_PAD(0x03D8, 0x0090, 7, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 = IOMUX_PAD(0x03D8, 0x0090, 8, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 = IOMUX_PAD(0x03D8, 0x0090, 9, 0x0000, 0, 0), + + MX6_PAD_ENET2_COL__ENET2_COL = IOMUX_PAD(0x03DC, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__ENET1_MDC = IOMUX_PAD(0x03DC, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__AUDMUX_AUD4_RXC = IOMUX_PAD(0x03DC, 0x0094, 2, 0x064C, 1, 0), + MX6_PAD_ENET2_COL__UART1_RX = IOMUX_PAD(0x03DC, 0x0094, 3, 0x0830, 2, 0), + MX6_PAD_ENET2_COL__SPDIF_IN = IOMUX_PAD(0x03DC, 0x0094, 4, 0x0824, 3, 0), + MX6_PAD_ENET2_COL__GPIO2_IO_6 = IOMUX_PAD(0x03DC, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__ANATOP_OTG1_ID = IOMUX_PAD(0x03DC, 0x0094, 6, 0x0624, 1, 0), + MX6_PAD_ENET2_COL__LCDIF2_DATA_20 = IOMUX_PAD(0x03DC, 0x0094, 7, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__VDEC_DEBUG_33 = IOMUX_PAD(0x03DC, 0x0094, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 = IOMUX_PAD(0x03DC, 0x0094, 9, 0x0000, 0, 0), + + MX6_PAD_ENET2_CRS__ENET2_CRS = IOMUX_PAD(0x03E0, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_CRS__ENET1_MDIO = IOMUX_PAD(0x03E0, 0x0098, 1, 0x0764, 2, 0), + MX6_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x03E0, 0x0098, 2, 0x0650, 1, 0), + MX6_PAD_ENET2_CRS__UART1_TX = IOMUX_PAD(0x03E0, 0x0098, 3, 0x0830, 3, 0), + MX6_PAD_ENET2_CRS__MLB_SIG = IOMUX_PAD(0x03E0, 0x0098, 4, 0x07F0, 1, 0), + MX6_PAD_ENET2_CRS__GPIO2_IO_7 = IOMUX_PAD(0x03E0, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_CRS__ANATOP_OTG2_ID = IOMUX_PAD(0x03E0, 0x0098, 6, 0x0628, 1, 0), + MX6_PAD_ENET2_CRS__LCDIF2_DATA_21 = IOMUX_PAD(0x03E0, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_ENET2_CRS__VDEC_DEBUG_32 = IOMUX_PAD(0x03E0, 0x0098, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 = IOMUX_PAD(0x03E0, 0x0098, 9, 0x0000, 0, 0), + + MX6_PAD_ENET2_RX_CLK__ENET2_RX_CLK = IOMUX_PAD(0x03E4, 0x009C, 0, 0x0774, 0, 0), + MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M = IOMUX_PAD(0x03E4, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_CLK__I2C3_SCL = IOMUX_PAD(0x03E4, 0x009C, 2, 0x07B8, 1, 0), + MX6_PAD_ENET2_RX_CLK__UART1_RTS_B = IOMUX_PAD(0x03E4, 0x009C, 3, 0x082C, 2, 0), + MX6_PAD_ENET2_RX_CLK__MLB_DATA = IOMUX_PAD(0x03E4, 0x009C, 4, 0x07EC, 1, 0), + MX6_PAD_ENET2_RX_CLK__GPIO2_IO_8 = IOMUX_PAD(0x03E4, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_CLK__USB_OTG2_OC = IOMUX_PAD(0x03E4, 0x009C, 6, 0x085C, 1, 0), + MX6_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 = IOMUX_PAD(0x03E4, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 = IOMUX_PAD(0x03E4, 0x009C, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 = IOMUX_PAD(0x03E4, 0x009C, 9, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x03E8, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x03E8, 0x00A0, 1, 0x076C, 1, 0), + MX6_PAD_ENET2_TX_CLK__I2C3_SDA = IOMUX_PAD(0x03E8, 0x00A0, 2, 0x07BC, 1, 0), + MX6_PAD_ENET2_TX_CLK__UART1_CTS_B = IOMUX_PAD(0x03E8, 0x00A0, 3, 0x082C, 3, 0), + MX6_PAD_ENET2_TX_CLK__MLB_CLK = IOMUX_PAD(0x03E8, 0x00A0, 4, 0x07E8, 1, 0), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 = IOMUX_PAD(0x03E8, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__USB_OTG2_PWR = IOMUX_PAD(0x03E8, 0x00A0, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 = IOMUX_PAD(0x03E8, 0x00A0, 7, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 = IOMUX_PAD(0x03E8, 0x00A0, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 = IOMUX_PAD(0x03E8, 0x00A0, 9, 0x0000, 0, 0), + + MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x03EC, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__USDHC3_CD_B = IOMUX_PAD(0x03EC, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART6_RTS_B = IOMUX_PAD(0x03EC, 0x00A4, 2, 0x0854, 2, 0), + MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x03EC, 0x00A4, 3, 0x0710, 0, 0), + MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x03EC, 0x00A4, 4, 0x066C, 0, 0), + MX6_PAD_KEY_COL0__GPIO2_IO_10 = IOMUX_PAD(0x03EC, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x03EC, 0x00A4, 6, 0x0820, 1, 0), + MX6_PAD_KEY_COL0__SAI2_TX_BCLK = IOMUX_PAD(0x03EC, 0x00A4, 7, 0x0814, 0, 0), + MX6_PAD_KEY_COL0__VADC_DATA_0 = IOMUX_PAD(0x03EC, 0x00A4, 8, 0x0000, 0, 0), + + MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x03F0, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__USDHC3_RESET_B = IOMUX_PAD(0x03F0, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART6_TX = IOMUX_PAD(0x03F0, 0x00A8, 2, 0x0858, 2, 0), + MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x03F0, 0x00A8, 3, 0x0714, 0, 0), + MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x03F0, 0x00A8, 4, 0x0670, 0, 0), + MX6_PAD_KEY_COL1__GPIO2_IO_11 = IOMUX_PAD(0x03F0, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__USDHC3_RESET = IOMUX_PAD(0x03F0, 0x00A8, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__SAI2_TX_SYNC = IOMUX_PAD(0x03F0, 0x00A8, 7, 0x0818, 0, 0), + + MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x03F4, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USDHC4_CD_B = IOMUX_PAD(0x03F4, 0x00AC, 1, 0x0874, 1, 0), + MX6_PAD_KEY_COL2__UART5_RTS_B = IOMUX_PAD(0x03F4, 0x00AC, 2, 0x084C, 2, 0), + MX6_PAD_KEY_COL2__CAN1_TX = IOMUX_PAD(0x03F4, 0x00AC, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__CANFD_TX1 = IOMUX_PAD(0x03F4, 0x00AC, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__GPIO2_IO_12 = IOMUX_PAD(0x03F4, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__WEIM_DATA_30 = IOMUX_PAD(0x03F4, 0x00AC, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__ECSPI1_RDY = IOMUX_PAD(0x03F4, 0x00AC, 7, 0x0000, 0, 0), + + MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x03F8, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__USDHC4_LCTL = IOMUX_PAD(0x03F8, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__UART5_TX = IOMUX_PAD(0x03F8, 0x00B0, 2, 0x0850, 2, 0), + MX6_PAD_KEY_COL3__CAN2_TX = IOMUX_PAD(0x03F8, 0x00B0, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__CANFD_TX2 = IOMUX_PAD(0x03F8, 0x00B0, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__GPIO2_IO_13 = IOMUX_PAD(0x03F8, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__WEIM_DATA_28 = IOMUX_PAD(0x03F8, 0x00B0, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__ECSPI1_SS2 = IOMUX_PAD(0x03F8, 0x00B0, 7, 0x0000, 0, 0), + + MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0), + MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), + MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__WEIM_CRE = IOMUX_PAD(0x03FC, 0x00B4, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__SAI2_RX_BCLK = IOMUX_PAD(0x03FC, 0x00B4, 7, 0x0808, 0, 0), + + MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0400, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__USDHC3_WP = IOMUX_PAD(0x0400, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART6_CTS_B = IOMUX_PAD(0x0400, 0x00B8, 2, 0x0854, 3, 0), + MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0400, 0x00B8, 3, 0x0718, 0, 0), + MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x0400, 0x00B8, 4, 0x0660, 0, 0), + MX6_PAD_KEY_ROW0__GPIO2_IO_15 = IOMUX_PAD(0x0400, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x0400, 0x00B8, 6, 0x081C, 1, 0), + MX6_PAD_KEY_ROW0__SAI2_TX_DATA_0 = IOMUX_PAD(0x0400, 0x00B8, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__GPU_IDLE = IOMUX_PAD(0x0400, 0x00B8, 8, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0404, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__USDHC4_VSELECT = IOMUX_PAD(0x0404, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART6_RX = IOMUX_PAD(0x0404, 0x00BC, 2, 0x0858, 3, 0), + MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00BC, 3, 0x071C, 0, 0), + MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0404, 0x00BC, 4, 0x065C, 0, 0), + MX6_PAD_KEY_ROW1__GPIO2_IO_16 = IOMUX_PAD(0x0404, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__WEIM_DATA_31 = IOMUX_PAD(0x0404, 0x00BC, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SAI2_RX_DATA_0 = IOMUX_PAD(0x0404, 0x00BC, 7, 0x080C, 0, 0), + MX6_PAD_KEY_ROW1__M4_NMI = IOMUX_PAD(0x0404, 0x00BC, 8, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x0408, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__USDHC4_WP = IOMUX_PAD(0x0408, 0x00C0, 1, 0x0878, 1, 0), + MX6_PAD_KEY_ROW2__UART5_CTS_B = IOMUX_PAD(0x0408, 0x00C0, 2, 0x084C, 3, 0), + MX6_PAD_KEY_ROW2__CAN1_RX = IOMUX_PAD(0x0408, 0x00C0, 3, 0x068C, 1, 0), + MX6_PAD_KEY_ROW2__CANFD_RX1 = IOMUX_PAD(0x0408, 0x00C0, 4, 0x0694, 1, 0), + MX6_PAD_KEY_ROW2__GPIO2_IO_17 = IOMUX_PAD(0x0408, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__WEIM_DATA_29 = IOMUX_PAD(0x0408, 0x00C0, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__ECSPI1_SS3 = IOMUX_PAD(0x0408, 0x00C0, 7, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x040C, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__USDHC3_LCTL = IOMUX_PAD(0x040C, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__UART5_RX = IOMUX_PAD(0x040C, 0x00C4, 2, 0x0850, 3, 0), + MX6_PAD_KEY_ROW3__CAN2_RX = IOMUX_PAD(0x040C, 0x00C4, 3, 0x0690, 1, 0), + MX6_PAD_KEY_ROW3__CANFD_RX2 = IOMUX_PAD(0x040C, 0x00C4, 4, 0x0698, 1, 0), + MX6_PAD_KEY_ROW3__GPIO2_IO_18 = IOMUX_PAD(0x040C, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__WEIM_DTACK_B = IOMUX_PAD(0x040C, 0x00C4, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__ECSPI1_SS1 = IOMUX_PAD(0x040C, 0x00C4, 7, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0), + MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0), + MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), + MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0410, 0x00C8, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__SAI2_RX_SYNC = IOMUX_PAD(0x0410, 0x00C8, 7, 0x0810, 0, 0), + + MX6_PAD_LCD1_CLK__LCDIF1_CLK = IOMUX_PAD(0x0414, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__LCDIF1_WR_RWN = IOMUX_PAD(0x0414, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0414, 0x00CC, 2, 0x0634, 1, 0), + MX6_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0414, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__CSI1_DATA_16 = IOMUX_PAD(0x0414, 0x00CC, 4, 0x06DC, 0, 0), + MX6_PAD_LCD1_CLK__GPIO3_IO_0 = IOMUX_PAD(0x0414, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__USDHC1_WP = IOMUX_PAD(0x0414, 0x00CC, 6, 0x0868, 0, 0), + MX6_PAD_LCD1_CLK__SIM_M_HADDR_16 = IOMUX_PAD(0x0414, 0x00CC, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__VADC_TEST_0 = IOMUX_PAD(0x0414, 0x00CC, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0414, 0x00CC, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 = IOMUX_PAD(0x0418, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__WEIM_CS1_B = IOMUX_PAD(0x0418, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__M4_TRACE_0 = IOMUX_PAD(0x0418, 0x00D0, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__KITTEN_TRACE_0 = IOMUX_PAD(0x0418, 0x00D0, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__CSI1_DATA_20 = IOMUX_PAD(0x0418, 0x00D0, 4, 0x06EC, 0, 0), + MX6_PAD_LCD1_DATA00__GPIO3_IO_1 = IOMUX_PAD(0x0418, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__SRC_BT_CFG_0 = IOMUX_PAD(0x0418, 0x00D0, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__SIM_M_HADDR_21 = IOMUX_PAD(0x0418, 0x00D0, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__VADC_TEST_5 = IOMUX_PAD(0x0418, 0x00D0, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA00__MMDC_DEBUG_5 = IOMUX_PAD(0x0418, 0x00D0, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 = IOMUX_PAD(0x041C, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__WEIM_CS2_B = IOMUX_PAD(0x041C, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__M4_TRACE_1 = IOMUX_PAD(0x041C, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__KITTEN_TRACE_1 = IOMUX_PAD(0x041C, 0x00D4, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__CSI1_DATA_21 = IOMUX_PAD(0x041C, 0x00D4, 4, 0x06F0, 0, 0), + MX6_PAD_LCD1_DATA01__GPIO3_IO_2 = IOMUX_PAD(0x041C, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__SRC_BT_CFG_1 = IOMUX_PAD(0x041C, 0x00D4, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__SIM_M_HADDR_22 = IOMUX_PAD(0x041C, 0x00D4, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__VADC_TEST_6 = IOMUX_PAD(0x041C, 0x00D4, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA01__MMDC_DEBUG_6 = IOMUX_PAD(0x041C, 0x00D4, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 = IOMUX_PAD(0x0420, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__WEIM_CS3_B = IOMUX_PAD(0x0420, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__M4_TRACE_2 = IOMUX_PAD(0x0420, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__KITTEN_TRACE_2 = IOMUX_PAD(0x0420, 0x00D8, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__CSI1_DATA_22 = IOMUX_PAD(0x0420, 0x00D8, 4, 0x06F4, 0, 0), + MX6_PAD_LCD1_DATA02__GPIO3_IO_3 = IOMUX_PAD(0x0420, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__SRC_BT_CFG_2 = IOMUX_PAD(0x0420, 0x00D8, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__SIM_M_HADDR_23 = IOMUX_PAD(0x0420, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__VADC_TEST_7 = IOMUX_PAD(0x0420, 0x00D8, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA02__MMDC_DEBUG_7 = IOMUX_PAD(0x0420, 0x00D8, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 = IOMUX_PAD(0x0424, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 = IOMUX_PAD(0x0424, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__M4_TRACE_3 = IOMUX_PAD(0x0424, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__KITTEN_TRACE_3 = IOMUX_PAD(0x0424, 0x00DC, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__CSI1_DATA_23 = IOMUX_PAD(0x0424, 0x00DC, 4, 0x06F8, 0, 0), + MX6_PAD_LCD1_DATA03__GPIO3_IO_4 = IOMUX_PAD(0x0424, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__SRC_BT_CFG_3 = IOMUX_PAD(0x0424, 0x00DC, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__SIM_M_HADDR_24 = IOMUX_PAD(0x0424, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__VADC_TEST_8 = IOMUX_PAD(0x0424, 0x00DC, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA03__MMDC_DEBUG_8 = IOMUX_PAD(0x0424, 0x00DC, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 = IOMUX_PAD(0x0428, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 = IOMUX_PAD(0x0428, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__KITTEN_TRACE_4 = IOMUX_PAD(0x0428, 0x00E0, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__CSI1_VSYNC = IOMUX_PAD(0x0428, 0x00E0, 4, 0x0708, 1, 0), + MX6_PAD_LCD1_DATA04__GPIO3_IO_5 = IOMUX_PAD(0x0428, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__SRC_BT_CFG_4 = IOMUX_PAD(0x0428, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__SIM_M_HADDR_25 = IOMUX_PAD(0x0428, 0x00E0, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__VADC_TEST_9 = IOMUX_PAD(0x0428, 0x00E0, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA04__MMDC_DEBUG_9 = IOMUX_PAD(0x0428, 0x00E0, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 = IOMUX_PAD(0x042C, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__WEIM_ADDR_26 = IOMUX_PAD(0x042C, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__KITTEN_TRACE_5 = IOMUX_PAD(0x042C, 0x00E4, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__CSI1_HSYNC = IOMUX_PAD(0x042C, 0x00E4, 4, 0x0700, 1, 0), + MX6_PAD_LCD1_DATA05__GPIO3_IO_6 = IOMUX_PAD(0x042C, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__SRC_BT_CFG_5 = IOMUX_PAD(0x042C, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__SIM_M_HADDR_26 = IOMUX_PAD(0x042C, 0x00E4, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__VADC_TEST_10 = IOMUX_PAD(0x042C, 0x00E4, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA05__MMDC_DEBUG_10 = IOMUX_PAD(0x042C, 0x00E4, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 = IOMUX_PAD(0x0430, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__WEIM_EB_B_2 = IOMUX_PAD(0x0430, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__KITTEN_TRACE_6 = IOMUX_PAD(0x0430, 0x00E8, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__CSI1_PIXCLK = IOMUX_PAD(0x0430, 0x00E8, 4, 0x0704, 1, 0), + MX6_PAD_LCD1_DATA06__GPIO3_IO_7 = IOMUX_PAD(0x0430, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__SRC_BT_CFG_6 = IOMUX_PAD(0x0430, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__SIM_M_HADDR_27 = IOMUX_PAD(0x0430, 0x00E8, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__VADC_TEST_11 = IOMUX_PAD(0x0430, 0x00E8, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA06__MMDC_DEBUG_11 = IOMUX_PAD(0x0430, 0x00E8, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 = IOMUX_PAD(0x0434, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__WEIM_EB_B_3 = IOMUX_PAD(0x0434, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__KITTEN_TRACE_7 = IOMUX_PAD(0x0434, 0x00EC, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__CSI1_MCLK = IOMUX_PAD(0x0434, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__GPIO3_IO_8 = IOMUX_PAD(0x0434, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__SRC_BT_CFG_7 = IOMUX_PAD(0x0434, 0x00EC, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__SIM_M_HADDR_28 = IOMUX_PAD(0x0434, 0x00EC, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__VADC_TEST_12 = IOMUX_PAD(0x0434, 0x00EC, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA07__MMDC_DEBUG_12 = IOMUX_PAD(0x0434, 0x00EC, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 = IOMUX_PAD(0x0438, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__WEIM_AD_8 = IOMUX_PAD(0x0438, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__KITTEN_TRACE_8 = IOMUX_PAD(0x0438, 0x00F0, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__CSI1_DATA_9 = IOMUX_PAD(0x0438, 0x00F0, 4, 0x06C4, 1, 0), + MX6_PAD_LCD1_DATA08__GPIO3_IO_9 = IOMUX_PAD(0x0438, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__SRC_BT_CFG_8 = IOMUX_PAD(0x0438, 0x00F0, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__SIM_M_HADDR_29 = IOMUX_PAD(0x0438, 0x00F0, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__VADC_TEST_13 = IOMUX_PAD(0x0438, 0x00F0, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA08__MMDC_DEBUG_13 = IOMUX_PAD(0x0438, 0x00F0, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 = IOMUX_PAD(0x043C, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__WEIM_AD_9 = IOMUX_PAD(0x043C, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__KITTEN_TRACE_9 = IOMUX_PAD(0x043C, 0x00F4, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__CSI1_DATA_8 = IOMUX_PAD(0x043C, 0x00F4, 4, 0x06C0, 1, 0), + MX6_PAD_LCD1_DATA09__GPIO3_IO_10 = IOMUX_PAD(0x043C, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__SRC_BT_CFG_9 = IOMUX_PAD(0x043C, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__SIM_M_HADDR_30 = IOMUX_PAD(0x043C, 0x00F4, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__VADC_TEST_14 = IOMUX_PAD(0x043C, 0x00F4, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA09__MMDC_DEBUG_14 = IOMUX_PAD(0x043C, 0x00F4, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 = IOMUX_PAD(0x0440, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__WEIM_AD_10 = IOMUX_PAD(0x0440, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__KITTEN_TRACE_10 = IOMUX_PAD(0x0440, 0x00F8, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__CSI1_DATA_7 = IOMUX_PAD(0x0440, 0x00F8, 4, 0x06BC, 1, 0), + MX6_PAD_LCD1_DATA10__GPIO3_IO_11 = IOMUX_PAD(0x0440, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0440, 0x00F8, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__SIM_M_HADDR_31 = IOMUX_PAD(0x0440, 0x00F8, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__VADC_TEST_15 = IOMUX_PAD(0x0440, 0x00F8, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA10__MMDC_DEBUG_15 = IOMUX_PAD(0x0440, 0x00F8, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 = IOMUX_PAD(0x0444, 0x00FC, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__WEIM_AD_11 = IOMUX_PAD(0x0444, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__KITTEN_TRACE_11 = IOMUX_PAD(0x0444, 0x00FC, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__CSI1_DATA_6 = IOMUX_PAD(0x0444, 0x00FC, 4, 0x06B8, 1, 0), + MX6_PAD_LCD1_DATA11__GPIO3_IO_12 = IOMUX_PAD(0x0444, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0444, 0x00FC, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__SIM_M_HBURST_0 = IOMUX_PAD(0x0444, 0x00FC, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__VADC_TEST_16 = IOMUX_PAD(0x0444, 0x00FC, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA11__MMDC_DEBUG_16 = IOMUX_PAD(0x0444, 0x00FC, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 = IOMUX_PAD(0x0448, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__WEIM_AD_12 = IOMUX_PAD(0x0448, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__KITTEN_TRACE_12 = IOMUX_PAD(0x0448, 0x0100, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__CSI1_DATA_5 = IOMUX_PAD(0x0448, 0x0100, 4, 0x06B4, 1, 0), + MX6_PAD_LCD1_DATA12__GPIO3_IO_13 = IOMUX_PAD(0x0448, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0448, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__SIM_M_HBURST_1 = IOMUX_PAD(0x0448, 0x0100, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__VADC_TEST_17 = IOMUX_PAD(0x0448, 0x0100, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA12__MMDC_DEBUG_17 = IOMUX_PAD(0x0448, 0x0100, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 = IOMUX_PAD(0x044C, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__WEIM_AD_13 = IOMUX_PAD(0x044C, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__KITTEN_TRACE_13 = IOMUX_PAD(0x044C, 0x0104, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__CSI1_DATA_4 = IOMUX_PAD(0x044C, 0x0104, 4, 0x06B0, 1, 0), + MX6_PAD_LCD1_DATA13__GPIO3_IO_14 = IOMUX_PAD(0x044C, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__SRC_BT_CFG_13 = IOMUX_PAD(0x044C, 0x0104, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__SIM_M_HBURST_2 = IOMUX_PAD(0x044C, 0x0104, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__VADC_TEST_18 = IOMUX_PAD(0x044C, 0x0104, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA13__MMDC_DEBUG_18 = IOMUX_PAD(0x044C, 0x0104, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 = IOMUX_PAD(0x0450, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__WEIM_AD_14 = IOMUX_PAD(0x0450, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__KITTEN_TRACE_14 = IOMUX_PAD(0x0450, 0x0108, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__CSI1_DATA_3 = IOMUX_PAD(0x0450, 0x0108, 4, 0x06AC, 1, 0), + MX6_PAD_LCD1_DATA14__GPIO3_IO_15 = IOMUX_PAD(0x0450, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0450, 0x0108, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__SIM_M_HMASTLOCK = IOMUX_PAD(0x0450, 0x0108, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__VADC_TEST_19 = IOMUX_PAD(0x0450, 0x0108, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA14__MMDC_DEBUG_19 = IOMUX_PAD(0x0450, 0x0108, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 = IOMUX_PAD(0x0454, 0x010C, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__WEIM_AD_15 = IOMUX_PAD(0x0454, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__KITTEN_TRACE_15 = IOMUX_PAD(0x0454, 0x010C, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__CSI1_DATA_2 = IOMUX_PAD(0x0454, 0x010C, 4, 0x06A8, 1, 0), + MX6_PAD_LCD1_DATA15__GPIO3_IO_16 = IOMUX_PAD(0x0454, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0454, 0x010C, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__SIM_M_HPROT_0 = IOMUX_PAD(0x0454, 0x010C, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__VDEC_DEBUG_0 = IOMUX_PAD(0x0454, 0x010C, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA15__MMDC_DEBUG_20 = IOMUX_PAD(0x0454, 0x010C, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 = IOMUX_PAD(0x0458, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 = IOMUX_PAD(0x0458, 0x0110, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__M4_TRACE_CLK = IOMUX_PAD(0x0458, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__KITTEN_TRACE_CLK = IOMUX_PAD(0x0458, 0x0110, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__CSI1_DATA_1 = IOMUX_PAD(0x0458, 0x0110, 4, 0x06A4, 0, 0), + MX6_PAD_LCD1_DATA16__GPIO3_IO_17 = IOMUX_PAD(0x0458, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__SRC_BT_CFG_24 = IOMUX_PAD(0x0458, 0x0110, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__SIM_M_HPROT_1 = IOMUX_PAD(0x0458, 0x0110, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__VDEC_DEBUG_1 = IOMUX_PAD(0x0458, 0x0110, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA16__MMDC_DEBUG_21 = IOMUX_PAD(0x0458, 0x0110, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 = IOMUX_PAD(0x045C, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 = IOMUX_PAD(0x045C, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__KITTEN_TRACE_CTL = IOMUX_PAD(0x045C, 0x0114, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__CSI1_DATA_0 = IOMUX_PAD(0x045C, 0x0114, 4, 0x06A0, 0, 0), + MX6_PAD_LCD1_DATA17__GPIO3_IO_18 = IOMUX_PAD(0x045C, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__SRC_BT_CFG_25 = IOMUX_PAD(0x045C, 0x0114, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__SIM_M_HPROT_2 = IOMUX_PAD(0x045C, 0x0114, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__VDEC_DEBUG_2 = IOMUX_PAD(0x045C, 0x0114, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA17__MMDC_DEBUG_22 = IOMUX_PAD(0x045C, 0x0114, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 = IOMUX_PAD(0x0460, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 = IOMUX_PAD(0x0460, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__M4_EVENTO = IOMUX_PAD(0x0460, 0x0118, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__KITTEN_EVENTO = IOMUX_PAD(0x0460, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__CSI1_DATA_15 = IOMUX_PAD(0x0460, 0x0118, 4, 0x06D8, 0, 0), + MX6_PAD_LCD1_DATA18__GPIO3_IO_19 = IOMUX_PAD(0x0460, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__SRC_BT_CFG_26 = IOMUX_PAD(0x0460, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__SIM_M_HPROT_3 = IOMUX_PAD(0x0460, 0x0118, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__VDEC_DEBUG_3 = IOMUX_PAD(0x0460, 0x0118, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA18__MMDC_DEBUG_23 = IOMUX_PAD(0x0460, 0x0118, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 = IOMUX_PAD(0x0464, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 = IOMUX_PAD(0x0464, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__M4_TRACE_SWO = IOMUX_PAD(0x0464, 0x011C, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__CSI1_DATA_14 = IOMUX_PAD(0x0464, 0x011C, 4, 0x06D4, 0, 0), + MX6_PAD_LCD1_DATA19__GPIO3_IO_20 = IOMUX_PAD(0x0464, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__SRC_BT_CFG_27 = IOMUX_PAD(0x0464, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__SIM_M_HREADYOUT = IOMUX_PAD(0x0464, 0x011C, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__VDEC_DEBUG_4 = IOMUX_PAD(0x0464, 0x011C, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA19__MMDC_DEBUG_24 = IOMUX_PAD(0x0464, 0x011C, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 = IOMUX_PAD(0x0468, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 = IOMUX_PAD(0x0468, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__PWM8_OUT = IOMUX_PAD(0x0468, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0468, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__CSI1_DATA_13 = IOMUX_PAD(0x0468, 0x0120, 4, 0x06D0, 0, 0), + MX6_PAD_LCD1_DATA20__GPIO3_IO_21 = IOMUX_PAD(0x0468, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__SRC_BT_CFG_28 = IOMUX_PAD(0x0468, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__SIM_M_HRESP = IOMUX_PAD(0x0468, 0x0120, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__VDEC_DEBUG_5 = IOMUX_PAD(0x0468, 0x0120, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA20__MMDC_DEBUG_25 = IOMUX_PAD(0x0468, 0x0120, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 = IOMUX_PAD(0x046C, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 = IOMUX_PAD(0x046C, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__PWM7_OUT = IOMUX_PAD(0x046C, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x046C, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__CSI1_DATA_12 = IOMUX_PAD(0x046C, 0x0124, 4, 0x06CC, 0, 0), + MX6_PAD_LCD1_DATA21__GPIO3_IO_22 = IOMUX_PAD(0x046C, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__SRC_BT_CFG_29 = IOMUX_PAD(0x046C, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__SIM_M_HSIZE_0 = IOMUX_PAD(0x046C, 0x0124, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__VDEC_DEBUG_6 = IOMUX_PAD(0x046C, 0x0124, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA21__MMDC_DEBUG_26 = IOMUX_PAD(0x046C, 0x0124, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 = IOMUX_PAD(0x0470, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 = IOMUX_PAD(0x0470, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__PWM6_OUT = IOMUX_PAD(0x0470, 0x0128, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0470, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__CSI1_DATA_11 = IOMUX_PAD(0x0470, 0x0128, 4, 0x06C8, 0, 0), + MX6_PAD_LCD1_DATA22__GPIO3_IO_23 = IOMUX_PAD(0x0470, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__SRC_BT_CFG_30 = IOMUX_PAD(0x0470, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__SIM_M_HSIZE_1 = IOMUX_PAD(0x0470, 0x0128, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__VDEC_DEBUG_7 = IOMUX_PAD(0x0470, 0x0128, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA22__MMDC_DEBUG_27 = IOMUX_PAD(0x0470, 0x0128, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 = IOMUX_PAD(0x0474, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 = IOMUX_PAD(0x0474, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__PWM5_OUT = IOMUX_PAD(0x0474, 0x012C, 2, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0474, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__CSI1_DATA_10 = IOMUX_PAD(0x0474, 0x012C, 4, 0x06FC, 0, 0), + MX6_PAD_LCD1_DATA23__GPIO3_IO_24 = IOMUX_PAD(0x0474, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__SRC_BT_CFG_31 = IOMUX_PAD(0x0474, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__SIM_M_HSIZE_2 = IOMUX_PAD(0x0474, 0x012C, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__VDEC_DEBUG_8 = IOMUX_PAD(0x0474, 0x012C, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_DATA23__MMDC_DEBUG_28 = IOMUX_PAD(0x0474, 0x012C, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE = IOMUX_PAD(0x0478, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__LCDIF1_RD_E = IOMUX_PAD(0x0478, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0478, 0x0130, 2, 0x063C, 1, 0), + MX6_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0478, 0x0130, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__CSI1_DATA_17 = IOMUX_PAD(0x0478, 0x0130, 4, 0x06E0, 0, 0), + MX6_PAD_LCD1_ENABLE__GPIO3_IO_25 = IOMUX_PAD(0x0478, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__USDHC1_CD_B = IOMUX_PAD(0x0478, 0x0130, 6, 0x0864, 0, 0), + MX6_PAD_LCD1_ENABLE__SIM_M_HADDR_17 = IOMUX_PAD(0x0478, 0x0130, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__VADC_TEST_1 = IOMUX_PAD(0x0478, 0x0130, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_ENABLE__MMDC_DEBUG_1 = IOMUX_PAD(0x0478, 0x0130, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC = IOMUX_PAD(0x047C, 0x0134, 0, 0x07E0, 0, 0), + MX6_PAD_LCD1_HSYNC__LCDIF1_RS = IOMUX_PAD(0x047C, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD = IOMUX_PAD(0x047C, 0x0134, 2, 0x0630, 1, 0), + MX6_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x047C, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__CSI1_DATA_18 = IOMUX_PAD(0x047C, 0x0134, 4, 0x06E4, 0, 0), + MX6_PAD_LCD1_HSYNC__GPIO3_IO_26 = IOMUX_PAD(0x047C, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__USDHC2_WP = IOMUX_PAD(0x047C, 0x0134, 6, 0x0870, 0, 0), + MX6_PAD_LCD1_HSYNC__SIM_M_HADDR_18 = IOMUX_PAD(0x047C, 0x0134, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__VADC_TEST_2 = IOMUX_PAD(0x047C, 0x0134, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_HSYNC__MMDC_DEBUG_2 = IOMUX_PAD(0x047C, 0x0134, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_RESET__LCDIF1_RESET = IOMUX_PAD(0x0480, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__LCDIF1_CS = IOMUX_PAD(0x0480, 0x0138, 1, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0480, 0x0138, 2, 0x062C, 1, 0), + MX6_PAD_LCD1_RESET__KITTEN_EVENTI = IOMUX_PAD(0x0480, 0x0138, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__M4_EVENTI = IOMUX_PAD(0x0480, 0x0138, 4, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 = IOMUX_PAD(0x0480, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__CCM_PMIC_RDY = IOMUX_PAD(0x0480, 0x0138, 6, 0x069C, 0, 0), + MX6_PAD_LCD1_RESET__SIM_M_HADDR_20 = IOMUX_PAD(0x0480, 0x0138, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__VADC_TEST_4 = IOMUX_PAD(0x0480, 0x0138, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_RESET__MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x0138, 9, 0x0000, 0, 0), + + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC = IOMUX_PAD(0x0484, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__LCDIF1_BUSY = IOMUX_PAD(0x0484, 0x013C, 1, 0x07E0, 1, 0), + MX6_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0484, 0x013C, 2, 0x0640, 1, 0), + MX6_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0484, 0x013C, 3, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__CSI1_DATA_19 = IOMUX_PAD(0x0484, 0x013C, 4, 0x06E8, 0, 0), + MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 = IOMUX_PAD(0x0484, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__USDHC2_CD_B = IOMUX_PAD(0x0484, 0x013C, 6, 0x086C, 0, 0), + MX6_PAD_LCD1_VSYNC__SIM_M_HADDR_19 = IOMUX_PAD(0x0484, 0x013C, 7, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__VADC_TEST_3 = IOMUX_PAD(0x0484, 0x013C, 8, 0x0000, 0, 0), + MX6_PAD_LCD1_VSYNC__MMDC_DEBUG_3 = IOMUX_PAD(0x0484, 0x013C, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0488, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__I2C3_SDA = IOMUX_PAD(0x0488, 0x0140, 1, 0x07BC, 0, 0), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B = IOMUX_PAD(0x0488, 0x0140, 2, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ECSPI2_SS0 = IOMUX_PAD(0x0488, 0x0140, 3, 0x072C, 0, 0), + MX6_PAD_NAND_ALE__ESAI_TX3_RX2 = IOMUX_PAD(0x0488, 0x0140, 4, 0x079C, 0, 0), + MX6_PAD_NAND_ALE__GPIO4_IO_0 = IOMUX_PAD(0x0488, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__WEIM_CS0_B = IOMUX_PAD(0x0488, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__TPSMP_HDATA_0 = IOMUX_PAD(0x0488, 0x0140, 7, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x0488, 0x0140, 8, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0488, 0x0140, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x048C, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__USDHC2_VSELECT = IOMUX_PAD(0x048C, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 = IOMUX_PAD(0x048C, 0x0144, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC = IOMUX_PAD(0x048C, 0x0144, 3, 0x0654, 0, 0), + MX6_PAD_NAND_CE0_B__ESAI_TX_CLK = IOMUX_PAD(0x048C, 0x0144, 4, 0x078C, 0, 0), + MX6_PAD_NAND_CE0_B__GPIO4_IO_1 = IOMUX_PAD(0x048C, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__WEIM_LBA_B = IOMUX_PAD(0x048C, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__TPSMP_HDATA_3 = IOMUX_PAD(0x048C, 0x0144, 7, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ = IOMUX_PAD(0x048C, 0x0144, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x048C, 0x0144, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0490, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__USDHC3_RESET_B = IOMUX_PAD(0x0490, 0x0148, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 = IOMUX_PAD(0x0490, 0x0148, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0490, 0x0148, 3, 0x0648, 0, 0), + MX6_PAD_NAND_CE1_B__ESAI_TX0 = IOMUX_PAD(0x0490, 0x0148, 4, 0x0790, 0, 0), + MX6_PAD_NAND_CE1_B__GPIO4_IO_2 = IOMUX_PAD(0x0490, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__WEIM_OE = IOMUX_PAD(0x0490, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__TPSMP_HDATA_4 = IOMUX_PAD(0x0490, 0x0148, 7, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0490, 0x0148, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0490, 0x0148, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0494, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__I2C3_SCL = IOMUX_PAD(0x0494, 0x014C, 1, 0x07B8, 0, 0), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK = IOMUX_PAD(0x0494, 0x014C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ECSPI2_SCLK = IOMUX_PAD(0x0494, 0x014C, 3, 0x0720, 0, 0), + MX6_PAD_NAND_CLE__ESAI_TX2_RX3 = IOMUX_PAD(0x0494, 0x014C, 4, 0x0798, 0, 0), + MX6_PAD_NAND_CLE__GPIO4_IO_3 = IOMUX_PAD(0x0494, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__WEIM_BCLK = IOMUX_PAD(0x0494, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__TPSMP_CLK = IOMUX_PAD(0x0494, 0x014C, 7, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x0494, 0x014C, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0494, 0x014C, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0498, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__USDHC1_DATA4 = IOMUX_PAD(0x0498, 0x0150, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 = IOMUX_PAD(0x0498, 0x0150, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ECSPI5_MISO = IOMUX_PAD(0x0498, 0x0150, 3, 0x0754, 0, 0), + MX6_PAD_NAND_DATA00__ESAI_RX_CLK = IOMUX_PAD(0x0498, 0x0150, 4, 0x0788, 0, 0), + MX6_PAD_NAND_DATA00__GPIO4_IO_4 = IOMUX_PAD(0x0498, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__WEIM_AD_0 = IOMUX_PAD(0x0498, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__TPSMP_HDATA_7 = IOMUX_PAD(0x0498, 0x0150, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x0498, 0x0150, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x0498, 0x0150, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x049C, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__USDHC1_DATA5 = IOMUX_PAD(0x049C, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 = IOMUX_PAD(0x049C, 0x0154, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ECSPI5_MOSI = IOMUX_PAD(0x049C, 0x0154, 3, 0x0758, 0, 0), + MX6_PAD_NAND_DATA01__ESAI_RX_FS = IOMUX_PAD(0x049C, 0x0154, 4, 0x0778, 0, 0), + MX6_PAD_NAND_DATA01__GPIO4_IO_5 = IOMUX_PAD(0x049C, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__WEIM_AD_1 = IOMUX_PAD(0x049C, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__TPSMP_HDATA_8 = IOMUX_PAD(0x049C, 0x0154, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD = IOMUX_PAD(0x049C, 0x0154, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x049C, 0x0154, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x04A0, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__USDHC1_DATA6 = IOMUX_PAD(0x04A0, 0x0158, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK = IOMUX_PAD(0x04A0, 0x0158, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ECSPI5_SCLK = IOMUX_PAD(0x04A0, 0x0158, 3, 0x0750, 0, 0), + MX6_PAD_NAND_DATA02__ESAI_TX_HF_CLK = IOMUX_PAD(0x04A0, 0x0158, 4, 0x0784, 0, 0), + MX6_PAD_NAND_DATA02__GPIO4_IO_6 = IOMUX_PAD(0x04A0, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__WEIM_AD_2 = IOMUX_PAD(0x04A0, 0x0158, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__TPSMP_HDATA_9 = IOMUX_PAD(0x04A0, 0x0158, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x04A0, 0x0158, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x04A0, 0x0158, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x04A4, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__USDHC1_DATA7 = IOMUX_PAD(0x04A4, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B = IOMUX_PAD(0x04A4, 0x015C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ECSPI5_SS0 = IOMUX_PAD(0x04A4, 0x015C, 3, 0x075C, 0, 0), + MX6_PAD_NAND_DATA03__ESAI_RX_HF_CLK = IOMUX_PAD(0x04A4, 0x015C, 4, 0x0780, 0, 0), + MX6_PAD_NAND_DATA03__GPIO4_IO_7 = IOMUX_PAD(0x04A4, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__WEIM_AD_3 = IOMUX_PAD(0x04A4, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__TPSMP_HDATA_10 = IOMUX_PAD(0x04A4, 0x015C, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH = IOMUX_PAD(0x04A4, 0x015C, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x04A4, 0x015C, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x04A8, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x04A8, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__QSPI2_B_SS1_B = IOMUX_PAD(0x04A8, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART3_RTS_B = IOMUX_PAD(0x04A8, 0x0160, 3, 0x083C, 0, 0), + MX6_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04A8, 0x0160, 4, 0x0650, 0, 0), + MX6_PAD_NAND_DATA04__GPIO4_IO_8 = IOMUX_PAD(0x04A8, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__WEIM_AD_4 = IOMUX_PAD(0x04A8, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__TPSMP_HDATA_11 = IOMUX_PAD(0x04A8, 0x0160, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH = IOMUX_PAD(0x04A8, 0x0160, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x04A8, 0x0160, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x04AC, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x04AC, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__QSPI2_B_DQS = IOMUX_PAD(0x04AC, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__UART3_CTS_B = IOMUX_PAD(0x04AC, 0x0164, 3, 0x083C, 1, 0), + MX6_PAD_NAND_DATA05__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04AC, 0x0164, 4, 0x064C, 0, 0), + MX6_PAD_NAND_DATA05__GPIO4_IO_9 = IOMUX_PAD(0x04AC, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__WEIM_AD_5 = IOMUX_PAD(0x04AC, 0x0164, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__TPSMP_HDATA_12 = IOMUX_PAD(0x04AC, 0x0164, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x04AC, 0x0164, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x04AC, 0x0164, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x04B0, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x04B0, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__QSPI2_A_SS1_B = IOMUX_PAD(0x04B0, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART3_RX = IOMUX_PAD(0x04B0, 0x0168, 3, 0x0840, 0, 0), + MX6_PAD_NAND_DATA06__PWM3_OUT = IOMUX_PAD(0x04B0, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__GPIO4_IO_10 = IOMUX_PAD(0x04B0, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__WEIM_AD_6 = IOMUX_PAD(0x04B0, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__TPSMP_HDATA_13 = IOMUX_PAD(0x04B0, 0x0168, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD = IOMUX_PAD(0x04B0, 0x0168, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x04B0, 0x0168, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x04B4, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x04B4, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__QSPI2_A_DQS = IOMUX_PAD(0x04B4, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__UART3_TX = IOMUX_PAD(0x04B4, 0x016C, 3, 0x0840, 1, 0), + MX6_PAD_NAND_DATA07__PWM4_OUT = IOMUX_PAD(0x04B4, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__GPIO4_IO_11 = IOMUX_PAD(0x04B4, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__WEIM_AD_7 = IOMUX_PAD(0x04B4, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__TPSMP_HDATA_14 = IOMUX_PAD(0x04B4, 0x016C, 7, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD = IOMUX_PAD(0x04B4, 0x016C, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x04B4, 0x016C, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x04B8, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__USDHC2_RESET_B = IOMUX_PAD(0x04B8, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 = IOMUX_PAD(0x04B8, 0x0170, 2, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04B8, 0x0170, 3, 0x0658, 0, 0), + MX6_PAD_NAND_RE_B__ESAI_TX_FS = IOMUX_PAD(0x04B8, 0x0170, 4, 0x077C, 0, 0), + MX6_PAD_NAND_RE_B__GPIO4_IO_12 = IOMUX_PAD(0x04B8, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__WEIM_RW = IOMUX_PAD(0x04B8, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__TPSMP_HDATA_5 = IOMUX_PAD(0x04B8, 0x0170, 7, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD = IOMUX_PAD(0x04B8, 0x0170, 8, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x04B8, 0x0170, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x04BC, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__USDHC1_VSELECT = IOMUX_PAD(0x04BC, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 = IOMUX_PAD(0x04BC, 0x0174, 2, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x0174, 3, 0x0724, 0, 0), + MX6_PAD_NAND_READY_B__ESAI_TX1 = IOMUX_PAD(0x04BC, 0x0174, 4, 0x0794, 0, 0), + MX6_PAD_NAND_READY_B__GPIO4_IO_13 = IOMUX_PAD(0x04BC, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__WEIM_EB_B_1 = IOMUX_PAD(0x04BC, 0x0174, 6, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__TPSMP_HDATA_2 = IOMUX_PAD(0x04BC, 0x0174, 7, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x04BC, 0x0174, 8, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x04BC, 0x0174, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x04C0, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__USDHC4_VSELECT = IOMUX_PAD(0x04C0, 0x0178, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 = IOMUX_PAD(0x04C0, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04C0, 0x0178, 3, 0x0644, 0, 0), + MX6_PAD_NAND_WE_B__ESAI_TX5_RX0 = IOMUX_PAD(0x04C0, 0x0178, 4, 0x07A4, 0, 0), + MX6_PAD_NAND_WE_B__GPIO4_IO_14 = IOMUX_PAD(0x04C0, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__WEIM_WAIT = IOMUX_PAD(0x04C0, 0x0178, 6, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__TPSMP_HDATA_6 = IOMUX_PAD(0x04C0, 0x0178, 7, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x04C0, 0x0178, 8, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x04C0, 0x0178, 9, 0x0000, 0, 0), + + MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x04C4, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x04C4, 0x017C, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 = IOMUX_PAD(0x04C4, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x017C, 3, 0x0728, 0, 0), + MX6_PAD_NAND_WP_B__ESAI_TX4_RX1 = IOMUX_PAD(0x04C4, 0x017C, 4, 0x07A0, 0, 0), + MX6_PAD_NAND_WP_B__GPIO4_IO_15 = IOMUX_PAD(0x04C4, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__WEIM_EB_B_0 = IOMUX_PAD(0x04C4, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__TPSMP_HDATA_1 = IOMUX_PAD(0x04C4, 0x017C, 7, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x04C4, 0x017C, 8, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x04C4, 0x017C, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 = IOMUX_PAD(0x04C8, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA0__USB_OTG2_OC = IOMUX_PAD(0x04C8, 0x0180, 1, 0x085C, 2, 0), + MX6_PAD_QSPI1A_DATA0__ECSPI1_MOSI = IOMUX_PAD(0x04C8, 0x0180, 2, 0x0718, 1, 0), + MX6_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 = IOMUX_PAD(0x04C8, 0x0180, 3, 0x07A0, 2, 0), + MX6_PAD_QSPI1A_DATA0__CSI1_DATA_14 = IOMUX_PAD(0x04C8, 0x0180, 4, 0x06D4, 1, 0), + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 = IOMUX_PAD(0x04C8, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6 = IOMUX_PAD(0x04C8, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 = IOMUX_PAD(0x04C8, 0x0180, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x04C8, 0x0180, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 = IOMUX_PAD(0x04CC, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID = IOMUX_PAD(0x04CC, 0x0184, 1, 0x0624, 2, 0), + MX6_PAD_QSPI1A_DATA1__ECSPI1_MISO = IOMUX_PAD(0x04CC, 0x0184, 2, 0x0714, 1, 0), + MX6_PAD_QSPI1A_DATA1__ESAI_TX1 = IOMUX_PAD(0x04CC, 0x0184, 3, 0x0794, 2, 0), + MX6_PAD_QSPI1A_DATA1__CSI1_DATA_13 = IOMUX_PAD(0x04CC, 0x0184, 4, 0x06D0, 1, 0), + MX6_PAD_QSPI1A_DATA1__GPIO4_IO_17 = IOMUX_PAD(0x04CC, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5 = IOMUX_PAD(0x04CC, 0x0184, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 = IOMUX_PAD(0x04CC, 0x0184, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x04CC, 0x0184, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 = IOMUX_PAD(0x04D0, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__USB_OTG1_PWR = IOMUX_PAD(0x04D0, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__ECSPI5_SS1 = IOMUX_PAD(0x04D0, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__ESAI_TX_CLK = IOMUX_PAD(0x04D0, 0x0188, 3, 0x078C, 2, 0), + MX6_PAD_QSPI1A_DATA2__CSI1_DATA_12 = IOMUX_PAD(0x04D0, 0x0188, 4, 0x06CC, 1, 0), + MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 = IOMUX_PAD(0x04D0, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4 = IOMUX_PAD(0x04D0, 0x0188, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 = IOMUX_PAD(0x04D0, 0x0188, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x04D0, 0x0188, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 = IOMUX_PAD(0x04D4, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__USB_OTG1_OC = IOMUX_PAD(0x04D4, 0x018C, 1, 0x0860, 2, 0), + MX6_PAD_QSPI1A_DATA3__ECSPI5_SS2 = IOMUX_PAD(0x04D4, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__ESAI_TX0 = IOMUX_PAD(0x04D4, 0x018C, 3, 0x0790, 2, 0), + MX6_PAD_QSPI1A_DATA3__CSI1_DATA_11 = IOMUX_PAD(0x04D4, 0x018C, 4, 0x06C8, 1, 0), + MX6_PAD_QSPI1A_DATA3__GPIO4_IO_19 = IOMUX_PAD(0x04D4, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3 = IOMUX_PAD(0x04D4, 0x018C, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 = IOMUX_PAD(0x04D4, 0x018C, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x04D4, 0x018C, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_DQS__QSPI1_A_DQS = IOMUX_PAD(0x04D8, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__CAN2_TX = IOMUX_PAD(0x04D8, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__CANFD_TX2 = IOMUX_PAD(0x04D8, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__ECSPI5_MOSI = IOMUX_PAD(0x04D8, 0x0190, 3, 0x0758, 1, 0), + MX6_PAD_QSPI1A_DQS__CSI1_DATA_15 = IOMUX_PAD(0x04D8, 0x0190, 4, 0x06D8, 1, 0), + MX6_PAD_QSPI1A_DQS__GPIO4_IO_20 = IOMUX_PAD(0x04D8, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__WEIM_DATA_7 = IOMUX_PAD(0x04D8, 0x0190, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__SIM_M_HADDR_13 = IOMUX_PAD(0x04D8, 0x0190, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x04D8, 0x0190, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK = IOMUX_PAD(0x04DC, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID = IOMUX_PAD(0x04DC, 0x0194, 1, 0x0628, 2, 0), + MX6_PAD_QSPI1A_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x04DC, 0x0194, 2, 0x0710, 1, 0), + MX6_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 = IOMUX_PAD(0x04DC, 0x0194, 3, 0x0798, 2, 0), + MX6_PAD_QSPI1A_SCLK__CSI1_DATA_1 = IOMUX_PAD(0x04DC, 0x0194, 4, 0x06A4, 1, 0), + MX6_PAD_QSPI1A_SCLK__GPIO4_IO_21 = IOMUX_PAD(0x04DC, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0 = IOMUX_PAD(0x04DC, 0x0194, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 = IOMUX_PAD(0x04DC, 0x0194, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x04DC, 0x0194, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B = IOMUX_PAD(0x04E0, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__USB_OTG2_PWR = IOMUX_PAD(0x04E0, 0x0198, 1, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x0198, 2, 0x071C, 1, 0), + MX6_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 = IOMUX_PAD(0x04E0, 0x0198, 3, 0x079C, 2, 0), + MX6_PAD_QSPI1A_SS0_B__CSI1_DATA_0 = IOMUX_PAD(0x04E0, 0x0198, 4, 0x06A0, 1, 0), + MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 = IOMUX_PAD(0x04E0, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1 = IOMUX_PAD(0x04E0, 0x0198, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 = IOMUX_PAD(0x04E0, 0x0198, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x04E0, 0x0198, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B = IOMUX_PAD(0x04E4, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS1_B__CAN1_RX = IOMUX_PAD(0x04E4, 0x019C, 1, 0x068C, 2, 0), + MX6_PAD_QSPI1A_SS1_B__CANFD_RX1 = IOMUX_PAD(0x04E4, 0x019C, 2, 0x0694, 2, 0), + MX6_PAD_QSPI1A_SS1_B__ECSPI5_MISO = IOMUX_PAD(0x04E4, 0x019C, 3, 0x0754, 1, 0), + MX6_PAD_QSPI1A_SS1_B__CSI1_DATA_10 = IOMUX_PAD(0x04E4, 0x019C, 4, 0x06FC, 1, 0), + MX6_PAD_QSPI1A_SS1_B__GPIO4_IO_23 = IOMUX_PAD(0x04E4, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2 = IOMUX_PAD(0x04E4, 0x019C, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 = IOMUX_PAD(0x04E4, 0x019C, 7, 0x0000, 0, 0), + MX6_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x04E4, 0x019C, 9, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 = IOMUX_PAD(0x04E8, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA0__UART3_CTS_B = IOMUX_PAD(0x04E8, 0x01A0, 1, 0x083C, 4, 0), + MX6_PAD_QSPI1B_DATA0__ECSPI3_MOSI = IOMUX_PAD(0x04E8, 0x01A0, 2, 0x0738, 1, 0), + MX6_PAD_QSPI1B_DATA0__ESAI_RX_FS = IOMUX_PAD(0x04E8, 0x01A0, 3, 0x0778, 2, 0), + MX6_PAD_QSPI1B_DATA0__CSI1_DATA_22 = IOMUX_PAD(0x04E8, 0x01A0, 4, 0x06F4, 1, 0), + MX6_PAD_QSPI1B_DATA0__GPIO4_IO_24 = IOMUX_PAD(0x04E8, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14 = IOMUX_PAD(0x04E8, 0x01A0, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 = IOMUX_PAD(0x04E8, 0x01A0, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 = IOMUX_PAD(0x04EC, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA1__UART3_RTS_B = IOMUX_PAD(0x04EC, 0x01A4, 1, 0x083C, 5, 0), + MX6_PAD_QSPI1B_DATA1__ECSPI3_MISO = IOMUX_PAD(0x04EC, 0x01A4, 2, 0x0734, 1, 0), + MX6_PAD_QSPI1B_DATA1__ESAI_RX_CLK = IOMUX_PAD(0x04EC, 0x01A4, 3, 0x0788, 2, 0), + MX6_PAD_QSPI1B_DATA1__CSI1_DATA_21 = IOMUX_PAD(0x04EC, 0x01A4, 4, 0x06F0, 1, 0), + MX6_PAD_QSPI1B_DATA1__GPIO4_IO_25 = IOMUX_PAD(0x04EC, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13 = IOMUX_PAD(0x04EC, 0x01A4, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 = IOMUX_PAD(0x04EC, 0x01A4, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 = IOMUX_PAD(0x04F0, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA2__I2C2_SDA = IOMUX_PAD(0x04F0, 0x01A8, 1, 0x07B4, 2, 0), + MX6_PAD_QSPI1B_DATA2__ECSPI5_RDY = IOMUX_PAD(0x04F0, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 = IOMUX_PAD(0x04F0, 0x01A8, 3, 0x07A4, 2, 0), + MX6_PAD_QSPI1B_DATA2__CSI1_DATA_20 = IOMUX_PAD(0x04F0, 0x01A8, 4, 0x06EC, 1, 0), + MX6_PAD_QSPI1B_DATA2__GPIO4_IO_26 = IOMUX_PAD(0x04F0, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12 = IOMUX_PAD(0x04F0, 0x01A8, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 = IOMUX_PAD(0x04F0, 0x01A8, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 = IOMUX_PAD(0x04F4, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA3__I2C2_SCL = IOMUX_PAD(0x04F4, 0x01AC, 1, 0x07B0, 2, 0), + MX6_PAD_QSPI1B_DATA3__ECSPI5_SS3 = IOMUX_PAD(0x04F4, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA3__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01AC, 3, 0x077C, 2, 0), + MX6_PAD_QSPI1B_DATA3__CSI1_DATA_19 = IOMUX_PAD(0x04F4, 0x01AC, 4, 0x06E8, 1, 0), + MX6_PAD_QSPI1B_DATA3__GPIO4_IO_27 = IOMUX_PAD(0x04F4, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11 = IOMUX_PAD(0x04F4, 0x01AC, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 = IOMUX_PAD(0x04F4, 0x01AC, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_DQS__QSPI1_B_DQS = IOMUX_PAD(0x04F8, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__CAN1_TX = IOMUX_PAD(0x04F8, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__CANFD_TX1 = IOMUX_PAD(0x04F8, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__ECSPI5_SS0 = IOMUX_PAD(0x04F8, 0x01B0, 3, 0x075C, 1, 0), + MX6_PAD_QSPI1B_DQS__CSI1_DATA_23 = IOMUX_PAD(0x04F8, 0x01B0, 4, 0x06F8, 1, 0), + MX6_PAD_QSPI1B_DQS__GPIO4_IO_28 = IOMUX_PAD(0x04F8, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__WEIM_DATA_15 = IOMUX_PAD(0x04F8, 0x01B0, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_DQS__SIM_M_HADDR_15 = IOMUX_PAD(0x04F8, 0x01B0, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK = IOMUX_PAD(0x04FC, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SCLK__UART3_RX = IOMUX_PAD(0x04FC, 0x01B4, 1, 0x0840, 4, 0), + MX6_PAD_QSPI1B_SCLK__ECSPI3_SCLK = IOMUX_PAD(0x04FC, 0x01B4, 2, 0x0730, 1, 0), + MX6_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK = IOMUX_PAD(0x04FC, 0x01B4, 3, 0x0780, 2, 0), + MX6_PAD_QSPI1B_SCLK__CSI1_DATA_16 = IOMUX_PAD(0x04FC, 0x01B4, 4, 0x06DC, 1, 0), + MX6_PAD_QSPI1B_SCLK__GPIO4_IO_29 = IOMUX_PAD(0x04FC, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8 = IOMUX_PAD(0x04FC, 0x01B4, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 = IOMUX_PAD(0x04FC, 0x01B4, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B = IOMUX_PAD(0x0500, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS0_B__UART3_TX = IOMUX_PAD(0x0500, 0x01B8, 1, 0x0840, 5, 0), + MX6_PAD_QSPI1B_SS0_B__ECSPI3_SS0 = IOMUX_PAD(0x0500, 0x01B8, 2, 0x073C, 1, 0), + MX6_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK = IOMUX_PAD(0x0500, 0x01B8, 3, 0x0784, 3, 0), + MX6_PAD_QSPI1B_SS0_B__CSI1_DATA_17 = IOMUX_PAD(0x0500, 0x01B8, 4, 0x06E0, 1, 0), + MX6_PAD_QSPI1B_SS0_B__GPIO4_IO_30 = IOMUX_PAD(0x0500, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9 = IOMUX_PAD(0x0500, 0x01B8, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 = IOMUX_PAD(0x0500, 0x01B8, 7, 0x0000, 0, 0), + + MX6_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B = IOMUX_PAD(0x0504, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS1_B__CAN2_RX = IOMUX_PAD(0x0504, 0x01BC, 1, 0x0690, 2, 0), + MX6_PAD_QSPI1B_SS1_B__CANFD_RX2 = IOMUX_PAD(0x0504, 0x01BC, 2, 0x0698, 2, 0), + MX6_PAD_QSPI1B_SS1_B__ECSPI5_SCLK = IOMUX_PAD(0x0504, 0x01BC, 3, 0x0750, 1, 0), + MX6_PAD_QSPI1B_SS1_B__CSI1_DATA_18 = IOMUX_PAD(0x0504, 0x01BC, 4, 0x06E4, 1, 0), + MX6_PAD_QSPI1B_SS1_B__GPIO4_IO_31 = IOMUX_PAD(0x0504, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10 = IOMUX_PAD(0x0504, 0x01BC, 6, 0x0000, 0, 0), + MX6_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 = IOMUX_PAD(0x0504, 0x01BC, 7, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 = IOMUX_PAD(0x0508, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__GPIO5_IO_0 = IOMUX_PAD(0x0508, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__CSI2_DATA_10 = IOMUX_PAD(0x0508, 0x01C0, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__ANATOP_TESTI_0 = IOMUX_PAD(0x0508, 0x01C0, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER = IOMUX_PAD(0x0508, 0x01C0, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 = IOMUX_PAD(0x0508, 0x01C0, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 = IOMUX_PAD(0x050C, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__GPIO5_IO_1 = IOMUX_PAD(0x050C, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__CSI2_DATA_11 = IOMUX_PAD(0x050C, 0x01C4, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__ANATOP_TESTI_1 = IOMUX_PAD(0x050C, 0x01C4, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER = IOMUX_PAD(0x050C, 0x01C4, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 = IOMUX_PAD(0x050C, 0x01C4, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 = IOMUX_PAD(0x0510, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__GPIO5_IO_2 = IOMUX_PAD(0x0510, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__CSI2_DATA_12 = IOMUX_PAD(0x0510, 0x01C8, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__ANATOP_TESTI_2 = IOMUX_PAD(0x0510, 0x01C8, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER = IOMUX_PAD(0x0510, 0x01C8, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 = IOMUX_PAD(0x0510, 0x01C8, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 = IOMUX_PAD(0x0514, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__GPIO5_IO_3 = IOMUX_PAD(0x0514, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__CSI2_DATA_13 = IOMUX_PAD(0x0514, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__ANATOP_TESTI_3 = IOMUX_PAD(0x0514, 0x01CC, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER = IOMUX_PAD(0x0514, 0x01CC, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 = IOMUX_PAD(0x0514, 0x01CC, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN = IOMUX_PAD(0x0518, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__GPIO5_IO_4 = IOMUX_PAD(0x0518, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__CSI2_DATA_14 = IOMUX_PAD(0x0518, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 = IOMUX_PAD(0x0518, 0x01D0, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER = IOMUX_PAD(0x0518, 0x01D0, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 = IOMUX_PAD(0x0518, 0x01D0, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK = IOMUX_PAD(0x051C, 0x01D4, 0, 0x0768, 1, 0), + MX6_PAD_RGMII1_RXC__ENET1_RX_ER = IOMUX_PAD(0x051C, 0x01D4, 1, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__GPIO5_IO_5 = IOMUX_PAD(0x051C, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__CSI2_DATA_15 = IOMUX_PAD(0x051C, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__ANATOP_TESTO_1 = IOMUX_PAD(0x051C, 0x01D4, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER = IOMUX_PAD(0x051C, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 = IOMUX_PAD(0x051C, 0x01D4, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 = IOMUX_PAD(0x0520, 0x01D8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__SAI2_RX_SYNC = IOMUX_PAD(0x0520, 0x01D8, 2, 0x0810, 1, 0), + MX6_PAD_RGMII1_TD0__GPIO5_IO_6 = IOMUX_PAD(0x0520, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__CSI2_DATA_16 = IOMUX_PAD(0x0520, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__ANATOP_TESTO_2 = IOMUX_PAD(0x0520, 0x01D8, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER = IOMUX_PAD(0x0520, 0x01D8, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 = IOMUX_PAD(0x0520, 0x01D8, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 = IOMUX_PAD(0x0524, 0x01DC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__SAI2_RX_BCLK = IOMUX_PAD(0x0524, 0x01DC, 2, 0x0808, 1, 0), + MX6_PAD_RGMII1_TD1__GPIO5_IO_7 = IOMUX_PAD(0x0524, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__CSI2_DATA_17 = IOMUX_PAD(0x0524, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__ANATOP_TESTO_3 = IOMUX_PAD(0x0524, 0x01DC, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER = IOMUX_PAD(0x0524, 0x01DC, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 = IOMUX_PAD(0x0524, 0x01DC, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 = IOMUX_PAD(0x0528, 0x01E0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__SAI2_TX_SYNC = IOMUX_PAD(0x0528, 0x01E0, 2, 0x0818, 1, 0), + MX6_PAD_RGMII1_TD2__GPIO5_IO_8 = IOMUX_PAD(0x0528, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__CSI2_DATA_18 = IOMUX_PAD(0x0528, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__ANATOP_TESTO_4 = IOMUX_PAD(0x0528, 0x01E0, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER = IOMUX_PAD(0x0528, 0x01E0, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 = IOMUX_PAD(0x0528, 0x01E0, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 = IOMUX_PAD(0x052C, 0x01E4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__SAI2_TX_BCLK = IOMUX_PAD(0x052C, 0x01E4, 2, 0x0814, 1, 0), + MX6_PAD_RGMII1_TD3__GPIO5_IO_9 = IOMUX_PAD(0x052C, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__CSI2_DATA_19 = IOMUX_PAD(0x052C, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__ANATOP_TESTO_5 = IOMUX_PAD(0x052C, 0x01E4, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER = IOMUX_PAD(0x052C, 0x01E4, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 = IOMUX_PAD(0x052C, 0x01E4, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN = IOMUX_PAD(0x0530, 0x01E8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 = IOMUX_PAD(0x0530, 0x01E8, 2, 0x080C, 1, 0), + MX6_PAD_RGMII1_TX_CTL__GPIO5_IO_10 = IOMUX_PAD(0x0530, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__CSI2_DATA_0 = IOMUX_PAD(0x0530, 0x01E8, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 = IOMUX_PAD(0x0530, 0x01E8, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER = IOMUX_PAD(0x0530, 0x01E8, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 = IOMUX_PAD(0x0530, 0x01E8, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x0534, 0x01EC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__ENET1_TX_ER = IOMUX_PAD(0x0534, 0x01EC, 1, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__SAI2_TX_DATA_0 = IOMUX_PAD(0x0534, 0x01EC, 2, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__GPIO5_IO_11 = IOMUX_PAD(0x0534, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__CSI2_DATA_1 = IOMUX_PAD(0x0534, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__ANATOP_TESTO_7 = IOMUX_PAD(0x0534, 0x01EC, 7, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER = IOMUX_PAD(0x0534, 0x01EC, 8, 0x0000, 0, 0), + MX6_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 = IOMUX_PAD(0x0534, 0x01EC, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 = IOMUX_PAD(0x0538, 0x01F0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__PWM4_OUT = IOMUX_PAD(0x0538, 0x01F0, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__GPIO5_IO_12 = IOMUX_PAD(0x0538, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__CSI2_DATA_2 = IOMUX_PAD(0x0538, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__ANATOP_TESTO_8 = IOMUX_PAD(0x0538, 0x01F0, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__VDEC_DEBUG_18 = IOMUX_PAD(0x0538, 0x01F0, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 = IOMUX_PAD(0x0538, 0x01F0, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 = IOMUX_PAD(0x053C, 0x01F4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__PWM3_OUT = IOMUX_PAD(0x053C, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__GPIO5_IO_13 = IOMUX_PAD(0x053C, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__CSI2_DATA_3 = IOMUX_PAD(0x053C, 0x01F4, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__ANATOP_TESTO_9 = IOMUX_PAD(0x053C, 0x01F4, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__VDEC_DEBUG_19 = IOMUX_PAD(0x053C, 0x01F4, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 = IOMUX_PAD(0x053C, 0x01F4, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 = IOMUX_PAD(0x0540, 0x01F8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__PWM2_OUT = IOMUX_PAD(0x0540, 0x01F8, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__GPIO5_IO_14 = IOMUX_PAD(0x0540, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__CSI2_DATA_4 = IOMUX_PAD(0x0540, 0x01F8, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__ANATOP_TESTO_10 = IOMUX_PAD(0x0540, 0x01F8, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__VDEC_DEBUG_20 = IOMUX_PAD(0x0540, 0x01F8, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 = IOMUX_PAD(0x0540, 0x01F8, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 = IOMUX_PAD(0x0544, 0x01FC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__PWM1_OUT = IOMUX_PAD(0x0544, 0x01FC, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__GPIO5_IO_15 = IOMUX_PAD(0x0544, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__CSI2_DATA_5 = IOMUX_PAD(0x0544, 0x01FC, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__ANATOP_TESTO_11 = IOMUX_PAD(0x0544, 0x01FC, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__VDEC_DEBUG_21 = IOMUX_PAD(0x0544, 0x01FC, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 = IOMUX_PAD(0x0544, 0x01FC, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN = IOMUX_PAD(0x0548, 0x0200, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__GPIO5_IO_16 = IOMUX_PAD(0x0548, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__CSI2_DATA_6 = IOMUX_PAD(0x0548, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 = IOMUX_PAD(0x0548, 0x0200, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 = IOMUX_PAD(0x0548, 0x0200, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 = IOMUX_PAD(0x0548, 0x0200, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_RXC__ENET2_RX_CLK = IOMUX_PAD(0x054C, 0x0204, 0, 0x0774, 1, 0), + MX6_PAD_RGMII2_RXC__ENET2_RX_ER = IOMUX_PAD(0x054C, 0x0204, 1, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__GPIO5_IO_17 = IOMUX_PAD(0x054C, 0x0204, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__CSI2_DATA_7 = IOMUX_PAD(0x054C, 0x0204, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__ANATOP_TESTO_13 = IOMUX_PAD(0x054C, 0x0204, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__VDEC_DEBUG_23 = IOMUX_PAD(0x054C, 0x0204, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 = IOMUX_PAD(0x054C, 0x0204, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 = IOMUX_PAD(0x0550, 0x0208, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__SAI1_RX_SYNC = IOMUX_PAD(0x0550, 0x0208, 2, 0x07FC, 1, 0), + MX6_PAD_RGMII2_TD0__PWM8_OUT = IOMUX_PAD(0x0550, 0x0208, 3, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__GPIO5_IO_18 = IOMUX_PAD(0x0550, 0x0208, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__CSI2_DATA_8 = IOMUX_PAD(0x0550, 0x0208, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__ANATOP_TESTO_14 = IOMUX_PAD(0x0550, 0x0208, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__VDEC_DEBUG_24 = IOMUX_PAD(0x0550, 0x0208, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 = IOMUX_PAD(0x0550, 0x0208, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 = IOMUX_PAD(0x0554, 0x020C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__SAI1_RX_BCLK = IOMUX_PAD(0x0554, 0x020C, 2, 0x07F4, 1, 0), + MX6_PAD_RGMII2_TD1__PWM7_OUT = IOMUX_PAD(0x0554, 0x020C, 3, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__GPIO5_IO_19 = IOMUX_PAD(0x0554, 0x020C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__CSI2_DATA_9 = IOMUX_PAD(0x0554, 0x020C, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__ANATOP_TESTO_15 = IOMUX_PAD(0x0554, 0x020C, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__VDEC_DEBUG_25 = IOMUX_PAD(0x0554, 0x020C, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 = IOMUX_PAD(0x0554, 0x020C, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 = IOMUX_PAD(0x0558, 0x0210, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__SAI1_TX_SYNC = IOMUX_PAD(0x0558, 0x0210, 2, 0x0804, 1, 0), + MX6_PAD_RGMII2_TD2__PWM6_OUT = IOMUX_PAD(0x0558, 0x0210, 3, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__GPIO5_IO_20 = IOMUX_PAD(0x0558, 0x0210, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__CSI2_VSYNC = IOMUX_PAD(0x0558, 0x0210, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__SJC_FAIL = IOMUX_PAD(0x0558, 0x0210, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__VDEC_DEBUG_26 = IOMUX_PAD(0x0558, 0x0210, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 = IOMUX_PAD(0x0558, 0x0210, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 = IOMUX_PAD(0x055C, 0x0214, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__SAI1_TX_BCLK = IOMUX_PAD(0x055C, 0x0214, 2, 0x0800, 1, 0), + MX6_PAD_RGMII2_TD3__PWM5_OUT = IOMUX_PAD(0x055C, 0x0214, 3, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__GPIO5_IO_21 = IOMUX_PAD(0x055C, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__CSI2_HSYNC = IOMUX_PAD(0x055C, 0x0214, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__SJC_JTAG_ACT = IOMUX_PAD(0x055C, 0x0214, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__VDEC_DEBUG_27 = IOMUX_PAD(0x055C, 0x0214, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 = IOMUX_PAD(0x055C, 0x0214, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN = IOMUX_PAD(0x0560, 0x0218, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 = IOMUX_PAD(0x0560, 0x0218, 2, 0x07F8, 1, 0), + MX6_PAD_RGMII2_TX_CTL__GPIO5_IO_22 = IOMUX_PAD(0x0560, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__CSI2_FIELD = IOMUX_PAD(0x0560, 0x0218, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__SJC_DE_B = IOMUX_PAD(0x0560, 0x0218, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 = IOMUX_PAD(0x0560, 0x0218, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 = IOMUX_PAD(0x0560, 0x0218, 9, 0x0000, 0, 0), + + MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC = IOMUX_PAD(0x0564, 0x021C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__ENET2_TX_ER = IOMUX_PAD(0x0564, 0x021C, 1, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__SAI1_TX_DATA_0 = IOMUX_PAD(0x0564, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__GPIO5_IO_23 = IOMUX_PAD(0x0564, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__CSI2_PIXCLK = IOMUX_PAD(0x0564, 0x021C, 6, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__SJC_DONE = IOMUX_PAD(0x0564, 0x021C, 7, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__VDEC_DEBUG_29 = IOMUX_PAD(0x0564, 0x021C, 8, 0x0000, 0, 0), + MX6_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 = IOMUX_PAD(0x0564, 0x021C, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0568, 0x0220, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0568, 0x0220, 1, 0x0668, 1, 0), + MX6_PAD_SD1_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x0568, 0x0220, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPT_CLK = IOMUX_PAD(0x0568, 0x0220, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0568, 0x0220, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO6_IO_0 = IOMUX_PAD(0x0568, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x0568, 0x0220, 6, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__CCM_OUT1 = IOMUX_PAD(0x0568, 0x0220, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__VADC_ADC_PROC_CLK = IOMUX_PAD(0x0568, 0x0220, 8, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__MMDC_DEBUG_45 = IOMUX_PAD(0x0568, 0x0220, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x056C, 0x0224, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__AUDMUX_AUD5_RXC = IOMUX_PAD(0x056C, 0x0224, 1, 0x0664, 1, 0), + MX6_PAD_SD1_CMD__WDOG1_WDOG_B = IOMUX_PAD(0x056C, 0x0224, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x056C, 0x0224, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x056C, 0x0224, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO6_IO_1 = IOMUX_PAD(0x056C, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x056C, 0x0224, 6, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__CCM_CLKO1 = IOMUX_PAD(0x056C, 0x0224, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__VADC_EXT_SYSCLK = IOMUX_PAD(0x056C, 0x0224, 8, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__MMDC_DEBUG_46 = IOMUX_PAD(0x056C, 0x0224, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0570, 0x0228, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0570, 0x0228, 1, 0x065C, 1, 0), + MX6_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS = IOMUX_PAD(0x0570, 0x0228, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPT_CAPTURE1 = IOMUX_PAD(0x0570, 0x0228, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__UART2_RX = IOMUX_PAD(0x0570, 0x0228, 4, 0x0838, 2, 0), + MX6_PAD_SD1_DATA0__GPIO6_IO_2 = IOMUX_PAD(0x0570, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0570, 0x0228, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__CCM_OUT2 = IOMUX_PAD(0x0570, 0x0228, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__VADC_CLAMP_UP = IOMUX_PAD(0x0570, 0x0228, 8, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__MMDC_DEBUG_48 = IOMUX_PAD(0x0570, 0x0228, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0574, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__AUDMUX_AUD5_TXC = IOMUX_PAD(0x0574, 0x022C, 1, 0x066C, 1, 0), + MX6_PAD_SD1_DATA1__PWM4_OUT = IOMUX_PAD(0x0574, 0x022C, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPT_CAPTURE2 = IOMUX_PAD(0x0574, 0x022C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__UART2_TX = IOMUX_PAD(0x0574, 0x022C, 4, 0x0838, 3, 0), + MX6_PAD_SD1_DATA1__GPIO6_IO_3 = IOMUX_PAD(0x0574, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0574, 0x022C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__CCM_CLKO2 = IOMUX_PAD(0x0574, 0x022C, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__VADC_CLAMP_DOWN = IOMUX_PAD(0x0574, 0x022C, 8, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__MMDC_DEBUG_47 = IOMUX_PAD(0x0574, 0x022C, 9, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0578, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x0578, 0x0230, 1, 0x0670, 1, 0), + MX6_PAD_SD1_DATA2__PWM3_OUT = IOMUX_PAD(0x0578, 0x0230, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPT_COMPARE2 = IOMUX_PAD(0x0578, 0x0230, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__UART2_CTS_B = IOMUX_PAD(0x0578, 0x0230, 4, 0x0834, 2, 0), + MX6_PAD_SD1_DATA2__GPIO6_IO_4 = IOMUX_PAD(0x0578, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0578, 0x0230, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__CCM_OUT0 = IOMUX_PAD(0x0578, 0x0230, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__VADC_EXT_PD_N = IOMUX_PAD(0x0578, 0x0230, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x057C, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__AUDMUX_AUD5_TXD = IOMUX_PAD(0x057C, 0x0234, 1, 0x0660, 1, 0), + MX6_PAD_SD1_DATA3__AUDMUX_AUD5_RXD = IOMUX_PAD(0x057C, 0x0234, 2, 0x065C, 2, 0), + MX6_PAD_SD1_DATA3__GPT_COMPARE3 = IOMUX_PAD(0x057C, 0x0234, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__UART2_RTS_B = IOMUX_PAD(0x057C, 0x0234, 4, 0x0834, 3, 0), + MX6_PAD_SD1_DATA3__GPIO6_IO_5 = IOMUX_PAD(0x057C, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__ECSPI4_SS1 = IOMUX_PAD(0x057C, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__CCM_PMIC_RDY = IOMUX_PAD(0x057C, 0x0234, 7, 0x069C, 2, 0), + MX6_PAD_SD1_DATA3__VADC_RST_N = IOMUX_PAD(0x057C, 0x0234, 8, 0x0000, 0, 0), + + MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0580, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0580, 0x0238, 1, 0x0680, 2, 0), + MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x0580, 0x0238, 2, 0x07C8, 1, 0), + MX6_PAD_SD2_CLK__ECSPI4_SCLK = IOMUX_PAD(0x0580, 0x0238, 3, 0x0740, 1, 0), + MX6_PAD_SD2_CLK__MLB_SIG = IOMUX_PAD(0x0580, 0x0238, 4, 0x07F0, 2, 0), + MX6_PAD_SD2_CLK__GPIO6_IO_6 = IOMUX_PAD(0x0580, 0x0238, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0580, 0x0238, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__WDOG1_WDOG_ANY = IOMUX_PAD(0x0580, 0x0238, 7, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 = IOMUX_PAD(0x0580, 0x0238, 8, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__MMDC_DEBUG_29 = IOMUX_PAD(0x0580, 0x0238, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0584, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__AUDMUX_AUD6_RXC = IOMUX_PAD(0x0584, 0x023C, 1, 0x067C, 2, 0), + MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0584, 0x023C, 2, 0x07D4, 1, 0), + MX6_PAD_SD2_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0584, 0x023C, 3, 0x0748, 1, 0), + MX6_PAD_SD2_CMD__MLB_CLK = IOMUX_PAD(0x0584, 0x023C, 4, 0x07E8, 2, 0), + MX6_PAD_SD2_CMD__GPIO6_IO_7 = IOMUX_PAD(0x0584, 0x023C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x0584, 0x023C, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__WDOG3_WDOG_B = IOMUX_PAD(0x0584, 0x023C, 7, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 = IOMUX_PAD(0x0584, 0x023C, 8, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__MMDC_DEBUG_30 = IOMUX_PAD(0x0584, 0x023C, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0588, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0588, 0x0240, 1, 0x0674, 2, 0), + MX6_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x0588, 0x0240, 2, 0x07DC, 1, 0), + MX6_PAD_SD2_DATA0__PWM1_OUT = IOMUX_PAD(0x0588, 0x0240, 3, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0588, 0x0240, 4, 0x07C4, 3, 0), + MX6_PAD_SD2_DATA0__GPIO6_IO_8 = IOMUX_PAD(0x0588, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__ECSPI4_SS3 = IOMUX_PAD(0x0588, 0x0240, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__UART4_RX = IOMUX_PAD(0x0588, 0x0240, 7, 0x0848, 4, 0), + MX6_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 = IOMUX_PAD(0x0588, 0x0240, 8, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__MMDC_DEBUG_50 = IOMUX_PAD(0x0588, 0x0240, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x058C, 0x0244, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x058C, 0x0244, 1, 0x0684, 2, 0), + MX6_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x058C, 0x0244, 2, 0x07D0, 1, 0), + MX6_PAD_SD2_DATA1__PWM2_OUT = IOMUX_PAD(0x058C, 0x0244, 3, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x058C, 0x0244, 4, 0x07C0, 3, 0), + MX6_PAD_SD2_DATA1__GPIO6_IO_9 = IOMUX_PAD(0x058C, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__ECSPI4_SS2 = IOMUX_PAD(0x058C, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__UART4_TX = IOMUX_PAD(0x058C, 0x0244, 7, 0x0848, 5, 0), + MX6_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 = IOMUX_PAD(0x058C, 0x0244, 8, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__MMDC_DEBUG_49 = IOMUX_PAD(0x058C, 0x0244, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0590, 0x0248, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0590, 0x0248, 1, 0x0688, 2, 0), + MX6_PAD_SD2_DATA2__KPP_ROW_6 = IOMUX_PAD(0x0590, 0x0248, 2, 0x07D8, 1, 0), + MX6_PAD_SD2_DATA2__ECSPI4_SS0 = IOMUX_PAD(0x0590, 0x0248, 3, 0x074C, 1, 0), + MX6_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x0590, 0x0248, 4, 0x081C, 2, 0), + MX6_PAD_SD2_DATA2__GPIO6_IO_10 = IOMUX_PAD(0x0590, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__SPDIF_OUT = IOMUX_PAD(0x0590, 0x0248, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__UART6_RX = IOMUX_PAD(0x0590, 0x0248, 7, 0x0858, 4, 0), + MX6_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 = IOMUX_PAD(0x0590, 0x0248, 8, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__MMDC_DEBUG_32 = IOMUX_PAD(0x0590, 0x0248, 9, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0594, 0x024C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0594, 0x024C, 1, 0x0678, 2, 0), + MX6_PAD_SD2_DATA3__KPP_COL_6 = IOMUX_PAD(0x0594, 0x024C, 2, 0x07CC, 1, 0), + MX6_PAD_SD2_DATA3__ECSPI4_MISO = IOMUX_PAD(0x0594, 0x024C, 3, 0x0744, 1, 0), + MX6_PAD_SD2_DATA3__MLB_DATA = IOMUX_PAD(0x0594, 0x024C, 4, 0x07EC, 2, 0), + MX6_PAD_SD2_DATA3__GPIO6_IO_11 = IOMUX_PAD(0x0594, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__SPDIF_IN = IOMUX_PAD(0x0594, 0x024C, 6, 0x0824, 4, 0), + MX6_PAD_SD2_DATA3__UART6_TX = IOMUX_PAD(0x0594, 0x024C, 7, 0x0858, 5, 0), + MX6_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 = IOMUX_PAD(0x0594, 0x024C, 8, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__MMDC_DEBUG_31 = IOMUX_PAD(0x0594, 0x024C, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0598, 0x0250, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART4_CTS_B = IOMUX_PAD(0x0598, 0x0250, 1, 0x0844, 0, 0), + MX6_PAD_SD3_CLK__ECSPI4_SCLK = IOMUX_PAD(0x0598, 0x0250, 2, 0x0740, 0, 0), + MX6_PAD_SD3_CLK__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0598, 0x0250, 3, 0x0680, 0, 0), + MX6_PAD_SD3_CLK__LCDIF2_VSYNC = IOMUX_PAD(0x0598, 0x0250, 4, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO7_IO_0 = IOMUX_PAD(0x0598, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__LCDIF2_BUSY = IOMUX_PAD(0x0598, 0x0250, 6, 0x07E4, 0, 0), + MX6_PAD_SD3_CLK__TPSMP_HDATA_29 = IOMUX_PAD(0x0598, 0x0250, 7, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x0598, 0x0250, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x059C, 0x0254, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART4_TX = IOMUX_PAD(0x059C, 0x0254, 1, 0x0848, 0, 0), + MX6_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x059C, 0x0254, 2, 0x0748, 0, 0), + MX6_PAD_SD3_CMD__AUDMUX_AUD6_RXC = IOMUX_PAD(0x059C, 0x0254, 3, 0x067C, 0, 0), + MX6_PAD_SD3_CMD__LCDIF2_HSYNC = IOMUX_PAD(0x059C, 0x0254, 4, 0x07E4, 1, 0), + MX6_PAD_SD3_CMD__GPIO7_IO_1 = IOMUX_PAD(0x059C, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__LCDIF2_RS = IOMUX_PAD(0x059C, 0x0254, 6, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__TPSMP_HDATA_28 = IOMUX_PAD(0x059C, 0x0254, 7, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x059C, 0x0254, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x05A0, 0x0258, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__I2C4_SCL = IOMUX_PAD(0x05A0, 0x0258, 1, 0x07C0, 0, 0), + MX6_PAD_SD3_DATA0__ECSPI2_SS1 = IOMUX_PAD(0x05A0, 0x0258, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x05A0, 0x0258, 3, 0x0674, 0, 0), + MX6_PAD_SD3_DATA0__LCDIF2_DATA_1 = IOMUX_PAD(0x05A0, 0x0258, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__GPIO7_IO_2 = IOMUX_PAD(0x05A0, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__DCIC1_OUT = IOMUX_PAD(0x05A0, 0x0258, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__TPSMP_HDATA_30 = IOMUX_PAD(0x05A0, 0x0258, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__GPU_DEBUG_0 = IOMUX_PAD(0x05A0, 0x0258, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x05A0, 0x0258, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x05A4, 0x025C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__I2C4_SDA = IOMUX_PAD(0x05A4, 0x025C, 1, 0x07C4, 0, 0), + MX6_PAD_SD3_DATA1__ECSPI2_SS2 = IOMUX_PAD(0x05A4, 0x025C, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x05A4, 0x025C, 3, 0x0684, 0, 0), + MX6_PAD_SD3_DATA1__LCDIF2_DATA_0 = IOMUX_PAD(0x05A4, 0x025C, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__GPIO7_IO_3 = IOMUX_PAD(0x05A4, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__DCIC2_OUT = IOMUX_PAD(0x05A4, 0x025C, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__TPSMP_HDATA_31 = IOMUX_PAD(0x05A4, 0x025C, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__GPU_DEBUG_1 = IOMUX_PAD(0x05A4, 0x025C, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x05A4, 0x025C, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x05A8, 0x0260, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__UART4_RTS_B = IOMUX_PAD(0x05A8, 0x0260, 1, 0x0844, 1, 0), + MX6_PAD_SD3_DATA2__ECSPI4_SS0 = IOMUX_PAD(0x05A8, 0x0260, 2, 0x074C, 0, 0), + MX6_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x05A8, 0x0260, 3, 0x0688, 0, 0), + MX6_PAD_SD3_DATA2__LCDIF2_CLK = IOMUX_PAD(0x05A8, 0x0260, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__GPIO7_IO_4 = IOMUX_PAD(0x05A8, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__LCDIF2_WR_RWN = IOMUX_PAD(0x05A8, 0x0260, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__TPSMP_HDATA_26 = IOMUX_PAD(0x05A8, 0x0260, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__GPU_DEBUG_2 = IOMUX_PAD(0x05A8, 0x0260, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x05A8, 0x0260, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x05AC, 0x0264, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__UART4_RX = IOMUX_PAD(0x05AC, 0x0264, 1, 0x0848, 1, 0), + MX6_PAD_SD3_DATA3__ECSPI4_MISO = IOMUX_PAD(0x05AC, 0x0264, 2, 0x0744, 0, 0), + MX6_PAD_SD3_DATA3__AUDMUX_AUD6_TXD = IOMUX_PAD(0x05AC, 0x0264, 3, 0x0678, 0, 0), + MX6_PAD_SD3_DATA3__LCDIF2_ENABLE = IOMUX_PAD(0x05AC, 0x0264, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__GPIO7_IO_5 = IOMUX_PAD(0x05AC, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__LCDIF2_RD_E = IOMUX_PAD(0x05AC, 0x0264, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__TPSMP_HDATA_27 = IOMUX_PAD(0x05AC, 0x0264, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__GPU_DEBUG_3 = IOMUX_PAD(0x05AC, 0x0264, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x05AC, 0x0264, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA4__USDHC3_DATA4 = IOMUX_PAD(0x05B0, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__CAN2_RX = IOMUX_PAD(0x05B0, 0x0268, 1, 0x0690, 0, 0), + MX6_PAD_SD3_DATA4__CANFD_RX2 = IOMUX_PAD(0x05B0, 0x0268, 2, 0x0698, 0, 0), + MX6_PAD_SD3_DATA4__UART3_RX = IOMUX_PAD(0x05B0, 0x0268, 3, 0x0840, 2, 0), + MX6_PAD_SD3_DATA4__LCDIF2_DATA_3 = IOMUX_PAD(0x05B0, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__GPIO7_IO_6 = IOMUX_PAD(0x05B0, 0x0268, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x05B0, 0x0268, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__TPSMP_HTRANS_1 = IOMUX_PAD(0x05B0, 0x0268, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__GPU_DEBUG_4 = IOMUX_PAD(0x05B0, 0x0268, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x05B0, 0x0268, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA5__USDHC3_DATA5 = IOMUX_PAD(0x05B4, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__CAN1_TX = IOMUX_PAD(0x05B4, 0x026C, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__CANFD_TX1 = IOMUX_PAD(0x05B4, 0x026C, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__UART3_TX = IOMUX_PAD(0x05B4, 0x026C, 3, 0x0840, 3, 0), + MX6_PAD_SD3_DATA5__LCDIF2_DATA_2 = IOMUX_PAD(0x05B4, 0x026C, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__GPIO7_IO_7 = IOMUX_PAD(0x05B4, 0x026C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x05B4, 0x026C, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__SIM_M_HWRITE = IOMUX_PAD(0x05B4, 0x026C, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__GPU_DEBUG_5 = IOMUX_PAD(0x05B4, 0x026C, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x05B4, 0x026C, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA6__USDHC3_DATA6 = IOMUX_PAD(0x05B8, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__CAN2_TX = IOMUX_PAD(0x05B8, 0x0270, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__CANFD_TX2 = IOMUX_PAD(0x05B8, 0x0270, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__UART3_RTS_B = IOMUX_PAD(0x05B8, 0x0270, 3, 0x083C, 2, 0), + MX6_PAD_SD3_DATA6__LCDIF2_DATA_4 = IOMUX_PAD(0x05B8, 0x0270, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__GPIO7_IO_8 = IOMUX_PAD(0x05B8, 0x0270, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x05B8, 0x0270, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__TPSMP_HTRANS_0 = IOMUX_PAD(0x05B8, 0x0270, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__GPU_DEBUG_7 = IOMUX_PAD(0x05B8, 0x0270, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x05B8, 0x0270, 9, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA7__USDHC3_DATA7 = IOMUX_PAD(0x05BC, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__CAN1_RX = IOMUX_PAD(0x05BC, 0x0274, 1, 0x068C, 0, 0), + MX6_PAD_SD3_DATA7__CANFD_RX1 = IOMUX_PAD(0x05BC, 0x0274, 2, 0x0694, 0, 0), + MX6_PAD_SD3_DATA7__UART3_CTS_B = IOMUX_PAD(0x05BC, 0x0274, 3, 0x083C, 3, 0), + MX6_PAD_SD3_DATA7__LCDIF2_DATA_5 = IOMUX_PAD(0x05BC, 0x0274, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__GPIO7_IO_9 = IOMUX_PAD(0x05BC, 0x0274, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x05BC, 0x0274, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__TPSMP_HDATA_DIR = IOMUX_PAD(0x05BC, 0x0274, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__GPU_DEBUG_6 = IOMUX_PAD(0x05BC, 0x0274, 8, 0x0000, 0, 0), + MX6_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x05BC, 0x0274, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x05C0, 0x0278, 0, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__RAWNAND_DATA15 = IOMUX_PAD(0x05C0, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__ECSPI2_MISO = IOMUX_PAD(0x05C0, 0x0278, 2, 0x0724, 1, 0), + MX6_PAD_SD4_CLK__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x05C0, 0x0278, 3, 0x0638, 0, 0), + MX6_PAD_SD4_CLK__LCDIF2_DATA_13 = IOMUX_PAD(0x05C0, 0x0278, 4, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__GPIO6_IO_12 = IOMUX_PAD(0x05C0, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__ECSPI3_SS2 = IOMUX_PAD(0x05C0, 0x0278, 6, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__TPSMP_HDATA_20 = IOMUX_PAD(0x05C0, 0x0278, 7, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__VDEC_DEBUG_12 = IOMUX_PAD(0x05C0, 0x0278, 8, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x05C0, 0x0278, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x05C4, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__RAWNAND_DATA14 = IOMUX_PAD(0x05C4, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__ECSPI2_MOSI = IOMUX_PAD(0x05C4, 0x027C, 2, 0x0728, 1, 0), + MX6_PAD_SD4_CMD__AUDMUX_AUD3_RXC = IOMUX_PAD(0x05C4, 0x027C, 3, 0x0634, 0, 0), + MX6_PAD_SD4_CMD__LCDIF2_DATA_14 = IOMUX_PAD(0x05C4, 0x027C, 4, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__GPIO6_IO_13 = IOMUX_PAD(0x05C4, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__ECSPI3_SS1 = IOMUX_PAD(0x05C4, 0x027C, 6, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__TPSMP_HDATA_19 = IOMUX_PAD(0x05C4, 0x027C, 7, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__VDEC_DEBUG_11 = IOMUX_PAD(0x05C4, 0x027C, 8, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x05C4, 0x027C, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA0__USDHC4_DATA0 = IOMUX_PAD(0x05C8, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__RAWNAND_DATA10 = IOMUX_PAD(0x05C8, 0x0280, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__ECSPI2_SS0 = IOMUX_PAD(0x05C8, 0x0280, 2, 0x072C, 1, 0), + MX6_PAD_SD4_DATA0__AUDMUX_AUD3_RXD = IOMUX_PAD(0x05C8, 0x0280, 3, 0x062C, 0, 0), + MX6_PAD_SD4_DATA0__LCDIF2_DATA_12 = IOMUX_PAD(0x05C8, 0x0280, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__GPIO6_IO_14 = IOMUX_PAD(0x05C8, 0x0280, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__ECSPI3_SS3 = IOMUX_PAD(0x05C8, 0x0280, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__TPSMP_HDATA_21 = IOMUX_PAD(0x05C8, 0x0280, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__VDEC_DEBUG_13 = IOMUX_PAD(0x05C8, 0x0280, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA0__SDMA_DEBUG_MODE = IOMUX_PAD(0x05C8, 0x0280, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA1__USDHC4_DATA1 = IOMUX_PAD(0x05CC, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__RAWNAND_DATA11 = IOMUX_PAD(0x05CC, 0x0284, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__ECSPI2_SCLK = IOMUX_PAD(0x05CC, 0x0284, 2, 0x0720, 1, 0), + MX6_PAD_SD4_DATA1__AUDMUX_AUD3_TXC = IOMUX_PAD(0x05CC, 0x0284, 3, 0x063C, 0, 0), + MX6_PAD_SD4_DATA1__LCDIF2_DATA_11 = IOMUX_PAD(0x05CC, 0x0284, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__GPIO6_IO_15 = IOMUX_PAD(0x05CC, 0x0284, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__ECSPI3_RDY = IOMUX_PAD(0x05CC, 0x0284, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__TPSMP_HDATA_22 = IOMUX_PAD(0x05CC, 0x0284, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__VDEC_DEBUG_14 = IOMUX_PAD(0x05CC, 0x0284, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x05CC, 0x0284, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA2__USDHC4_DATA2 = IOMUX_PAD(0x05D0, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__RAWNAND_DATA12 = IOMUX_PAD(0x05D0, 0x0288, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__I2C2_SDA = IOMUX_PAD(0x05D0, 0x0288, 2, 0x07B4, 0, 0), + MX6_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x05D0, 0x0288, 3, 0x0640, 0, 0), + MX6_PAD_SD4_DATA2__LCDIF2_DATA_10 = IOMUX_PAD(0x05D0, 0x0288, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__GPIO6_IO_16 = IOMUX_PAD(0x05D0, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__ECSPI2_SS3 = IOMUX_PAD(0x05D0, 0x0288, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__TPSMP_HDATA_23 = IOMUX_PAD(0x05D0, 0x0288, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__VDEC_DEBUG_15 = IOMUX_PAD(0x05D0, 0x0288, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x05D0, 0x0288, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA3__USDHC4_DATA3 = IOMUX_PAD(0x05D4, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__RAWNAND_DATA13 = IOMUX_PAD(0x05D4, 0x028C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__I2C2_SCL = IOMUX_PAD(0x05D4, 0x028C, 2, 0x07B0, 0, 0), + MX6_PAD_SD4_DATA3__AUDMUX_AUD3_TXD = IOMUX_PAD(0x05D4, 0x028C, 3, 0x0630, 0, 0), + MX6_PAD_SD4_DATA3__LCDIF2_DATA_9 = IOMUX_PAD(0x05D4, 0x028C, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__GPIO6_IO_17 = IOMUX_PAD(0x05D4, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__ECSPI2_RDY = IOMUX_PAD(0x05D4, 0x028C, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__TPSMP_HDATA_24 = IOMUX_PAD(0x05D4, 0x028C, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__VDEC_DEBUG_16 = IOMUX_PAD(0x05D4, 0x028C, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x05D4, 0x028C, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA4__USDHC4_DATA4 = IOMUX_PAD(0x05D8, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__RAWNAND_DATA09 = IOMUX_PAD(0x05D8, 0x0290, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__UART5_RX = IOMUX_PAD(0x05D8, 0x0290, 2, 0x0850, 0, 0), + MX6_PAD_SD4_DATA4__ECSPI3_SCLK = IOMUX_PAD(0x05D8, 0x0290, 3, 0x0730, 0, 0), + MX6_PAD_SD4_DATA4__LCDIF2_DATA_8 = IOMUX_PAD(0x05D8, 0x0290, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__GPIO6_IO_18 = IOMUX_PAD(0x05D8, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__SPDIF_OUT = IOMUX_PAD(0x05D8, 0x0290, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__TPSMP_HDATA_16 = IOMUX_PAD(0x05D8, 0x0290, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__USB_OTG_HOST_MODE = IOMUX_PAD(0x05D8, 0x0290, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x05D8, 0x0290, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA5__USDHC4_DATA5 = IOMUX_PAD(0x05DC, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__RAWNAND_CE2_B = IOMUX_PAD(0x05DC, 0x0294, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__UART5_TX = IOMUX_PAD(0x05DC, 0x0294, 2, 0x0850, 1, 0), + MX6_PAD_SD4_DATA5__ECSPI3_MOSI = IOMUX_PAD(0x05DC, 0x0294, 3, 0x0738, 0, 0), + MX6_PAD_SD4_DATA5__LCDIF2_DATA_7 = IOMUX_PAD(0x05DC, 0x0294, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__GPIO6_IO_19 = IOMUX_PAD(0x05DC, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__SPDIF_IN = IOMUX_PAD(0x05DC, 0x0294, 6, 0x0824, 0, 0), + MX6_PAD_SD4_DATA5__TPSMP_HDATA_17 = IOMUX_PAD(0x05DC, 0x0294, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__VDEC_DEBUG_9 = IOMUX_PAD(0x05DC, 0x0294, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x05DC, 0x0294, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA6__USDHC4_DATA6 = IOMUX_PAD(0x05E0, 0x0298, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__RAWNAND_CE3_B = IOMUX_PAD(0x05E0, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__UART5_RTS_B = IOMUX_PAD(0x05E0, 0x0298, 2, 0x084C, 0, 0), + MX6_PAD_SD4_DATA6__ECSPI3_MISO = IOMUX_PAD(0x05E0, 0x0298, 3, 0x0734, 0, 0), + MX6_PAD_SD4_DATA6__LCDIF2_DATA_6 = IOMUX_PAD(0x05E0, 0x0298, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__GPIO6_IO_20 = IOMUX_PAD(0x05E0, 0x0298, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__USDHC4_WP = IOMUX_PAD(0x05E0, 0x0298, 6, 0x0878, 0, 0), + MX6_PAD_SD4_DATA6__TPSMP_HDATA_18 = IOMUX_PAD(0x05E0, 0x0298, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__VDEC_DEBUG_10 = IOMUX_PAD(0x05E0, 0x0298, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x05E0, 0x0298, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_DATA7__USDHC4_DATA7 = IOMUX_PAD(0x05E4, 0x029C, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__RAWNAND_DATA08 = IOMUX_PAD(0x05E4, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__UART5_CTS_B = IOMUX_PAD(0x05E4, 0x029C, 2, 0x084C, 1, 0), + MX6_PAD_SD4_DATA7__ECSPI3_SS0 = IOMUX_PAD(0x05E4, 0x029C, 3, 0x073C, 0, 0), + MX6_PAD_SD4_DATA7__LCDIF2_DATA_15 = IOMUX_PAD(0x05E4, 0x029C, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__GPIO6_IO_21 = IOMUX_PAD(0x05E4, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__USDHC4_CD_B = IOMUX_PAD(0x05E4, 0x029C, 6, 0x0874, 0, 0), + MX6_PAD_SD4_DATA7__TPSMP_HDATA_15 = IOMUX_PAD(0x05E4, 0x029C, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__USB_OTG_PWR_WAKE = IOMUX_PAD(0x05E4, 0x029C, 8, 0x0000, 0, 0), + MX6_PAD_SD4_DATA7__SDMA_DEBUG_YIELD = IOMUX_PAD(0x05E4, 0x029C, 9, 0x0000, 0, 0), + + MX6_PAD_SD4_RESET_B__USDHC4_RESET_B = IOMUX_PAD(0x05E8, 0x02A0, 0, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__RAWNAND_DQS = IOMUX_PAD(0x05E8, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__USDHC4_RESET = IOMUX_PAD(0x05E8, 0x02A0, 2, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__AUDMUX_MCLK = IOMUX_PAD(0x05E8, 0x02A0, 3, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__LCDIF2_RESET = IOMUX_PAD(0x05E8, 0x02A0, 4, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__GPIO6_IO_22 = IOMUX_PAD(0x05E8, 0x02A0, 5, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__LCDIF2_CS = IOMUX_PAD(0x05E8, 0x02A0, 6, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__TPSMP_HDATA_25 = IOMUX_PAD(0x05E8, 0x02A0, 7, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__VDEC_DEBUG_17 = IOMUX_PAD(0x05E8, 0x02A0, 8, 0x0000, 0, 0), + MX6_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x05E8, 0x02A0, 9, 0x0000, 0, 0), + + MX6_PAD_USB_H_DATA__USB_H_DATA = IOMUX_PAD(0x05EC, 0x02A4, 0, 0x0000, 0, 0), + MX6_PAD_USB_H_DATA__PWM2_OUT = IOMUX_PAD(0x05EC, 0x02A4, 1, 0x0000, 0, 0), + MX6_PAD_USB_H_DATA__ANATOP_24M_OUT = IOMUX_PAD(0x05EC, 0x02A4, 2, 0x0000, 0, 0), + MX6_PAD_USB_H_DATA__I2C4_SDA = IOMUX_PAD(0x05EC, 0x02A4, 3, 0x07C4, 1, 0), + MX6_PAD_USB_H_DATA__WDOG3_WDOG_B = IOMUX_PAD(0x05EC, 0x02A4, 4, 0x0000, 0, 0), + MX6_PAD_USB_H_DATA__GPIO7_IO_10 = IOMUX_PAD(0x05EC, 0x02A4, 5, 0x0000, 0, 0), + + MX6_PAD_USB_H_STROBE__USB_H_STROBE = IOMUX_PAD(0x05F0, 0x02A8, 0, 0x0000, 0, 0), + MX6_PAD_USB_H_STROBE__PWM1_OUT = IOMUX_PAD(0x05F0, 0x02A8, 1, 0x0000, 0, 0), + MX6_PAD_USB_H_STROBE__ANATOP_32K_OUT = IOMUX_PAD(0x05F0, 0x02A8, 2, 0x0000, 0, 0), + MX6_PAD_USB_H_STROBE__I2C4_SCL = IOMUX_PAD(0x05F0, 0x02A8, 3, 0x07C0, 1, 0), + MX6_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x05F0, 0x02A8, 4, 0x0000, 0, 0), + MX6_PAD_USB_H_STROBE__GPIO7_IO_11 = IOMUX_PAD(0x05F0, 0x02A8, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_MX6_ MX6_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h index 561e8ff82a..e5e3eff596 100644 --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h +++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h @@ -9,6 +9,11 @@ #ifndef __MXC_HDMI_H__ #define __MXC_HDMI_H__ +#ifdef CONFIG_IMX_HDMI +void imx_enable_hdmi_phy(void); +void imx_setup_hdmi(void); +#endif + /* * Hdmi controller registers */ @@ -884,6 +889,9 @@ enum { HDMI_PHY_HPD = 0x02, HDMI_PHY_TX_PHY_LOCK = 0x01, +/* Convenience macro RX_SENSE | HPD */ + HDMI_DVI_STAT = 0xF2, + /* PHY_I2CM_SLAVE_ADDR field values */ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index d263560a1a..8e92e8567f 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -9,18 +9,24 @@ #define _SYS_PROTO_H_ #include +#include "../arch-imx/cpu.h" -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 +#define soc_rev() (get_cpu_rev() & 0xFF) +#define is_soc_rev(rev) (soc_rev() - rev) -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +u32 get_nr_cpus(void); u32 get_cpu_rev(void); + +/* returns MXC_CPU_ value */ +#define cpu_type(rev) (((rev) >> 12)&0xff) + +/* both macros return/take MXC_CPU_ constants */ +#define get_cpu_type() (cpu_type(get_cpu_rev())) +#define is_cpu_type(cpu) (get_cpu_type() == cpu) + const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); +void set_chipselect_size(int const); struct mxs_register_32; diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h index d3bc95b824..e52d4133c9 100644 --- a/arch/arm/include/asm/arch-mxs/clock.h +++ b/arch/arm/include/asm/arch-mxs/clock.h @@ -20,7 +20,7 @@ enum mxc_clock { MXC_IO1_CLK, MXC_XTAL_CLK, MXC_SSP0_CLK, -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 MXC_SSP1_CLK, MXC_SSP2_CLK, MXC_SSP3_CLK, @@ -35,7 +35,7 @@ enum mxs_ioclock { enum mxs_sspclock { MXC_SSPCLK0 = 0, -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 MXC_SSPCLK1, MXC_SSPCLK2, MXC_SSPCLK3, diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h index 86914ef742..cc42dddf53 100644 --- a/arch/arm/include/asm/arch-mxs/imx-regs.h +++ b/arch/arm/include/asm/arch-mxs/imx-regs.h @@ -26,12 +26,12 @@ #include #include -#ifdef CONFIG_MX23 +#ifdef CONFIG_SOC_MX23 #include #include #endif -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 #include #include #endif diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h index 3d11491300..4a0ad73d11 100644 --- a/arch/arm/include/asm/arch-mxs/iomux.h +++ b/arch/arm/include/asm/arch-mxs/iomux.h @@ -59,7 +59,7 @@ typedef u32 iomux_cfg_t; #define PAD_16MA 3 #define PAD_1V8 0 -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) #define PAD_3V3 1 #else #define PAD_3V3 0 diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h index 213df514ba..006cf638ec 100644 --- a/arch/arm/include/asm/arch-mxs/regs-base.h +++ b/arch/arm/include/asm/arch-mxs/regs-base.h @@ -18,7 +18,7 @@ /* * Register base addresses for i.MX23 */ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define MXS_ICOLL_BASE 0x80000000 #define MXS_APBH_BASE 0x80004000 #define MXS_ECC8_BASE 0x80008000 @@ -60,7 +60,7 @@ /* * Register base addresses for i.MX28 */ -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define MXS_ICOL_BASE 0x80000000 #define MXS_HSADC_BASE 0x80002000 #define MXS_APBH_BASE 0x80004000 @@ -115,7 +115,7 @@ #define MXS_ENET0_BASE 0x800F0000 #define MXS_ENET1_BASE 0x800F4000 #else -#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28 +#error Unkown SoC. Please set CONFIG_SOC_MX23 or CONFIG_SOC_MX28 #endif #endif /* __MXS_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/arch-mxs/regs-lcdif.h index a845883911..0d0e2d8e75 100644 --- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h +++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h @@ -19,14 +19,14 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_ctrl); /* 0x00 */ mxs_reg_32(hw_lcdif_ctrl1); /* 0x10 */ -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif /* MX23/MX28 */ mxs_reg_32(hw_lcdif_transfer_count); /* 0x20/0x30 */ mxs_reg_32(hw_lcdif_cur_buf); /* 0x30/0x40 */ mxs_reg_32(hw_lcdif_next_buf); /* 0x40/0x50 */ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) reg_32(reserved1); /* 0x50 */ #endif @@ -49,12 +49,12 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_csc_offset); /* 0x160 */ mxs_reg_32(hw_lcdif_csc_limit); /* 0x170 */ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) reg_32(reserved2[3]); /* 0x180-0x1a0 */ #endif /* MX23/MX28 */ mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat); /* 0x1d0/0x1b0 */ @@ -201,10 +201,10 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL1_VSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \ LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 #endif diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h index 464e9e0914..b37e9b1e27 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -15,7 +15,7 @@ #include #ifndef __ASSEMBLY__ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) struct mxs_ssp_regs { mxs_reg_32(hw_ssp_ctrl0); mxs_reg_32(hw_ssp_cmd0); @@ -34,7 +34,7 @@ struct mxs_ssp_regs { mxs_reg_32(hw_ssp_debug); mxs_reg_32(hw_ssp_version); }; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) struct mxs_ssp_regs { mxs_reg_32(hw_ssp_ctrl0); mxs_reg_32(hw_ssp_cmd0); @@ -61,9 +61,9 @@ struct mxs_ssp_regs { static inline int mxs_ssp_bus_id_valid(int bus) { -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) const unsigned int mxs_ssp_chan_count = 2; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) const unsigned int mxs_ssp_chan_count = 4; #endif @@ -78,9 +78,9 @@ static inline int mxs_ssp_bus_id_valid(int bus) static inline int mxs_ssp_clock_by_bus(unsigned int clock) { -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) return 0; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) return clock; #endif } @@ -92,7 +92,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) return (struct mxs_ssp_regs *)MXS_SSP0_BASE; case 1: return (struct mxs_ssp_regs *)MXS_SSP1_BASE; -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 case 2: return (struct mxs_ssp_regs *)MXS_SSP2_BASE; case 3: @@ -124,7 +124,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_CTRL0_GET_RESP (1 << 17) #define SSP_CTRL0_ENABLE (1 << 16) -#ifdef CONFIG_MX23 +#ifdef CONFIG_SOC_MX23 #define SSP_CTRL0_XFER_COUNT_OFFSET 0 #define SSP_CTRL0_XFER_COUNT_MASK 0xffff #endif @@ -136,7 +136,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_CMD0_SLOW_CLKING_EN (1 << 22) #define SSP_CMD0_CONT_CLKING_EN (1 << 21) #define SSP_CMD0_APPEND_8CYC (1 << 20) -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) #define SSP_CMD0_BLOCK_SIZE_OFFSET 16 #define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) @@ -215,7 +215,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_CMD1_CMD_ARG_MASK 0xffffffff #define SSP_CMD1_CMD_ARG_OFFSET 0 -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) #define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff #define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h index 0ee3ec81bb..b5160c9e02 100644 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -18,7 +18,7 @@ struct mxs_timrot_regs { mxs_reg_32(hw_timrot_rotctrl); mxs_reg_32(hw_timrot_rotcount); -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) mxs_reg_32(hw_timrot_timctrl0); mxs_reg_32(hw_timrot_timcount0); mxs_reg_32(hw_timrot_timctrl1); @@ -27,7 +27,7 @@ struct mxs_timrot_regs { mxs_reg_32(hw_timrot_timcount2); mxs_reg_32(hw_timrot_timctrl3); mxs_reg_32(hw_timrot_timcount3); -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) mxs_reg_32(hw_timrot_timctrl0); mxs_reg_32(hw_timrot_running_count0); mxs_reg_32(hw_timrot_fixed_count0); @@ -69,9 +69,9 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) #define TIMROT_ROTCTRL_POLARITY_B (1 << 9) #define TIMROT_ROTCTRL_POLARITY_A (1 << 8) -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) #endif #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 @@ -81,19 +81,19 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) #endif -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf #endif #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 @@ -103,10 +103,10 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 @@ -119,7 +119,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_IRQ (1 << 15) #define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) #define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) #endif #define TIMROT_TIMCTRLn_POLARITY (1 << 8) @@ -139,7 +139,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 #define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 #define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 @@ -147,7 +147,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 @@ -160,23 +160,23 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf #endif -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 #endif -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 #endif -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) #define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff #define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 #endif @@ -189,7 +189,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) @@ -197,7 +197,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) @@ -209,13 +209,13 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) #endif -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_TIMCTRL3_IRQ (1 << 15) #define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) #define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) #endif #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) #define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 #define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h new file mode 100644 index 0000000000..27644e0464 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h @@ -0,0 +1,220 @@ +/* + * Freescale MXS UARTAPP Register Definitions + * + * Copyright (C) 2013 Andreas Wass + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM___MXS_UARTAPP_H +#define __ARCH_ARM___MXS_UARTAPP_H + +#include + +#ifndef __ASSEMBLY__ +struct mxs_uartapp_regs { + mxs_reg_32(hw_uartapp_ctrl0); + mxs_reg_32(hw_uartapp_ctrl1); + mxs_reg_32(hw_uartapp_ctrl2); + mxs_reg_32(hw_uartapp_linectrl); + mxs_reg_32(hw_uartapp_linectrl2); + mxs_reg_32(hw_uartapp_intr); + mxs_reg_32(hw_uartapp_data); + mxs_reg_32(hw_uartapp_stat); + mxs_reg_32(hw_uartapp_debug); + mxs_reg_32(hw_uartapp_version); + mxs_reg_32(hw_uartapp_autobaud); +}; +#endif + +#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) +#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) +#define UARTAPP_CTRL0_RUN_MASK (1 << 29) +#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) +#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) +#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 +#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) +#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF + +#define UARTAPP_CTRL1_RUN_MASK (1 << 28) + +#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF + +#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) +#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) +#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) +#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) +#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) +#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) +#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) +#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) +#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 +#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) + +#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) +#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 +#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) +#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) +#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) +#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) +#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) +#define UARTAPP_CTRL2_RTS_MASK (1 << 11) +#define UARTAPP_CTRL2_DTR_MASK (1 << 10) +#define UARTAPP_CTRL2_RXE_MASK (1 << 9) +#define UARTAPP_CTRL2_TXE_MASK (1 << 8) +#define UARTAPP_CTRL2_LBE_MASK (1 << 7) +#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) + +#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) +#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) +#define UARTAPP_CTRL2_UARTEN_MASK 0x01 + +#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F + +#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) +#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL_BRK_MASK 1 + +#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F + +#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) +#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) + +#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) +#define UARTAPP_INTR_OEIEN_MASK (1 << 26) +#define UARTAPP_INTR_BEIEN_MASK (1 << 25) +#define UARTAPP_INTR_PEIEN_MASK (1 << 24) +#define UARTAPP_INTR_FEIEN_MASK (1 << 23) +#define UARTAPP_INTR_RTIEN_MASK (1 << 22) +#define UARTAPP_INTR_TXIEN_MASK (1 << 21) +#define UARTAPP_INTR_RXIEN_MASK (1 << 20) +#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) +#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) +#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) +#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) + +#define UARTAPP_INTR_ABDIS_MASK (1 << 11) +#define UARTAPP_INTR_OEIS_MASK (1 << 10) +#define UARTAPP_INTR_BEIS_MASK (1 << 9) +#define UARTAPP_INTR_PEIS_MASK (1 << 8) +#define UARTAPP_INTR_FEIS_MASK (1 << 7) +#define UARTAPP_INTR_RTIS_MASK (1 << 6) +#define UARTAPP_INTR_TXIS_MASK (1 << 5) +#define UARTAPP_INTR_RXIS_MASK (1 << 4) +#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) +#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) +#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) +#define UARTAPP_INTR_RIMIS_MASK 0x1 + +#define UARTAPP_DATA_DATA_OFFSET 0 +#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF +#define UARTAPP_STAT_PRESENT_MASK (1 << 31) +#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) +#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) + +#define UARTAPP_STAT_HISPEED_MASK (1 << 30) +#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) +#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) + +#define UARTAPP_STAT_BUSY_MASK (1 << 29) +#define UARTAPP_STAT_CTS_MASK (1 << 28) +#define UARTAPP_STAT_TXFE_MASK (1 << 27) +#define UARTAPP_STAT_RXFF_MASK (1 << 26) +#define UARTAPP_STAT_TXFF_MASK (1 << 25) +#define UARTAPP_STAT_RXFE_MASK (1 << 24) +#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 +#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) + +#define UARTAPP_STAT_OERR_MASK (1 << 19) +#define UARTAPP_STAT_BERR_MASK (1 << 18) +#define UARTAPP_STAT_PERR_MASK (1 << 17) +#define UARTAPP_STAT_FERR_MASK (1 << 16) +#define UARTAPP_STAT_RXCOUNT_OFFSET 0 +#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF + +#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 +#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) + +#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 +#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) + +#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) +#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) +#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) +#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) +#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) +#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 + +#define UARTAPP_VERSION_MAJOR_OFFSET 24 +#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) + +#define UARTAPP_VERSION_MINOR_OFFSET 16 +#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) + +#define UARTAPP_VERSION_STEP_OFFSET 0 +#define UARTAPP_VERSION_STEP_MASK 0xFFFF + +#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 +#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) + +#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 +#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) + +#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) +#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) +#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) +#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) +#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 +#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 3f4c108942..2e86da5946 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -10,7 +10,7 @@ #ifndef __SYS_PROTO_H__ #define __SYS_PROTO_H__ -struct mxs_register_32; +#include int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg, @@ -26,14 +26,15 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); #ifdef CONFIG_SPL_BUILD -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #include -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #include #endif -void mxs_common_spl_init(const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size); +void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, + const iomux_cfg_t *iomux_setup, + const unsigned int iomux_size); #endif struct mxs_pair { @@ -43,17 +44,18 @@ struct mxs_pair { }; static const struct mxs_pair mxs_boot_modes[] = { -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) { 0x00, 0x0f, "USB" }, { 0x01, 0x1f, "I2C, master" }, { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, { 0x04, 0x1f, "NAND" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0" }, { 0x0a, 0x1f, "SSP SD/MMC #1" }, { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) { 0x00, 0x0f, "USB #0" }, { 0x01, 0x1f, "I2C #0, master, 3V3" }, { 0x11, 0x1f, "I2C #0, master, 1V8" }, @@ -63,6 +65,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, { 0x04, 0x1f, "NAND, 3V3" }, { 0x14, 0x1f, "NAND, 1V8" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index da776cf5b8..1912cc9a67 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -27,8 +27,6 @@ #define ICK_DSS_ON 0x00000001 #define FCK_CAM_ON 0x00000001 #define ICK_CAM_ON 0x00000001 -#define FCK_PER_ON 0x0003ffff -#define ICK_PER_ON 0x0003ffff /* Used to index into DPLL parameter tables */ typedef struct { @@ -61,7 +59,6 @@ extern dpll_param *get_36x_mpu_dpll_param(void); extern dpll_param *get_36x_iva_dpll_param(void); extern dpll_param *get_36x_core_dpll_param(void); extern dpll_param *get_36x_per_dpll_param(void); - -extern void *_end_vect, *_start; +extern dpll_param *get_36x_per2_dpll_param(void); #endif diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h index bf7fa00206..df73c4b2eb 100644 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -323,4 +323,26 @@ #define PER_36XX_FSEL_38P4 0x07 #define PER_36XX_M2_38P4 0x09 +/* 36XX PER2 DPLL */ + +#define PER2_36XX_M_12 0x50 +#define PER2_36XX_N_12 0x00 +#define PER2_36XX_M2_12 0x08 + +#define PER2_36XX_M_13 0x1BB +#define PER2_36XX_N_13 0x05 +#define PER2_36XX_M2_13 0x08 + +#define PER2_36XX_M_19P2 0x32 +#define PER2_36XX_N_19P2 0x00 +#define PER2_36XX_M2_19P2 0x08 + +#define PER2_36XX_M_26 0x1BB +#define PER2_36XX_N_26 0x0B +#define PER2_36XX_M2_26 0x08 + +#define PER2_36XX_M_38P4 0x19 +#define PER2_36XX_N_38P4 0x00 +#define PER2_36XX_M2_38P4 0x08 + #endif /* endif _CLOCKS_OMAP3_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 61ec8f24e0..53cc2b098a 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -77,59 +77,7 @@ struct ctrl_id { #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) #ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct bch_res_0_3 { - u32 bch_result_x[4]; -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ - u8 res7[0x1C]; /* fill up to 0x240 */ - struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - -#else /* __ASSEMBLY__ */ +#ifdef __ASSEMBLY__ #define GPMC_CONFIG1 0x00 #define GPMC_CONFIG2 0x04 #define GPMC_CONFIG3 0x08 @@ -150,7 +98,6 @@ extern struct gpmc *gpmc_cfg; #define DEBUG_BASE 0x08000000 /* debug board */ #define NAND_BASE 0x30000000 /* NAND addr */ /* (actual size small port) */ -#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ #define ONENAND_MAP 0x20000000 /* OneNand addr */ /* (actual size small port) */ /* SMS */ diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index ae0babf17c..8bf6b4895f 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -178,10 +178,11 @@ struct venc_regs { #define LCD_INTERFACE_24_BIT 3 /* Polarity */ -#define DSS_IVS (1 << 12) -#define DSS_IHS (1 << 13) -#define DSS_IPC (1 << 14) -#define DSS_IEO (1 << 15) +#define DSS_IVS (1 << 12) +#define DSS_IHS (1 << 13) +#define DSS_IPC (1 << 14) +#define DSS_IEO (1 << 15) +#define DSS_ONOFF (1 << 17) /* GFX format */ #define GFXFORMAT_BITMAP1 (0x0 << 1) diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/arch-omap3/gpio.h index d72f5e50ad..f664c11990 100644 --- a/arch/arm/include/asm/arch-omap3/gpio.h +++ b/arch/arm/include/asm/arch-omap3/gpio.h @@ -2,20 +2,7 @@ * Copyright (c) 2009 Wind River Systems, Inc. * Tom Rix * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * This work is derived from the linux 2.6.27 kernel source * To fetch, use the kernel repository @@ -30,10 +17,6 @@ * * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _GPIO_OMAP3_H #define _GPIO_OMAP3_H diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index bcc22c43e1..3ce270c5c9 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -249,6 +249,49 @@ enum { #define MICRON_RASWIDTH_200 14 #define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) +/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */ +#define SAMSUNG_TDAL_165 5 +#define SAMSUNG_TDPL_165 2 +#define SAMSUNG_TRRD_165 2 +#define SAMSUNG_TRCD_165 3 +#define SAMSUNG_TRP_165 3 +#define SAMSUNG_TRAS_165 7 +#define SAMSUNG_TRC_165 10 +#define SAMSUNG_TRFC_165 12 + +#define SAMSUNG_V_ACTIMA_165 \ + ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \ + SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \ + SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \ + SAMSUNG_TDPL_165, SAMSUNG_TDAL_165) + +#define SAMSUNG_TWTR_165 1 +#define SAMSUNG_TCKE_165 2 +#define SAMSUNG_XSR_165 20 +#define SAMSUNG_TXP_165 5 + +#define SAMSUNG_V_ACTIMB_165 \ + ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \ + SAMSUNG_TXP_165, SAMSUNG_XSR_165) + +#define SAMSUNG_RASWIDTH_165 14 +#define SAMSUNG_V_MCFG_165(size) \ + V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \ + V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \ + V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR + +/* TODO: find which register these were taken from */ + +#define SAMSUNG_BL_165 0x2 +#define SAMSUNG_SIL_165 0x0 +#define SAMSUNG_CASL_165 0x3 +#define SAMSUNG_WBST_165 0x0 +#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \ + (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \ + (SAMSUNG_BL_165)) + +#define SAMSUNG_SHARING 0x00003700 + /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ @@ -344,6 +387,7 @@ enum { * MAP - Map this CS to which address(GPMC address space)- Absolute address * >>24 before being used. */ +#define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 #define GPMC_SIZE_64M 0xC #define GPMC_SIZE_32M 0xE @@ -353,14 +397,6 @@ enum { #define GPMC_CS_ENABLE 0x1 -#define SMNAND_GPMC_CONFIG1 0x00000800 -#define SMNAND_GPMC_CONFIG2 0x00141400 -#define SMNAND_GPMC_CONFIG3 0x00141400 -#define SMNAND_GPMC_CONFIG4 0x0F010F01 -#define SMNAND_GPMC_CONFIG5 0x010C1414 -#define SMNAND_GPMC_CONFIG6 0x1F0F0A80 -#define SMNAND_GPMC_CONFIG7 0x00000C44 - #define M_NAND_GPMC_CONFIG1 0x00001800 #define M_NAND_GPMC_CONFIG2 0x00141400 #define M_NAND_GPMC_CONFIG3 0x00141400 @@ -419,25 +455,22 @@ enum { #define NET_GPMC_CONFIG6 0x00000FCF #define NET_GPMC_CONFIG7 0x00000f6c +/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define NET_LAN9221_GPMC_CONFIG2 0x00060700 +#define NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define NET_LAN9221_GPMC_CONFIG4 0x06000700 +#define NET_LAN9221_GPMC_CONFIG5 0x0006090A +#define NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + + /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ #define GPMC_MAX_REG 7 -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 #define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP #define DBG_MPDB_BASE DEBUG_BASE #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index 0ba621a1b8..9f2896c4b9 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -51,6 +51,7 @@ typedef struct t2 { #define PBIASLITEPWRDNZ0 (1 << 1) #define PBIASSPEEDCTRL0 (1 << 2) #define PBIASLITEPWRDNZ1 (1 << 9) +#define PBIASLITEVMODE0 (1 << 0) #define CTLPROGIO1SPEEDCTRL (1 << 20) diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 2f8320629b..3277b407d1 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -15,6 +15,12 @@ * PTU - Pull type Up * DIS - Pull type selection is inactive * EN - Pull type selection is active + * SB_LOW - Standby mode configuration: Output low-level + * SB_HI - Standby mode configuration: Output high-level + * SB_HIZ - Standby mode configuration: Output hi-impedence + * SB_PD - Standby mode pull-down enabled + * SB_PU - Standby mode pull-up enabled + * WKEN - Wakeup input enabled * M0 - Mode 0 */ @@ -26,6 +32,13 @@ #define EN (1 << 3) #define DIS (0 << 3) +#define SB_LOW (1 << 9) +#define SB_HI (5 << 9) +#define SB_HIZ (2 << 9) +#define SB_PD (1 << 12) +#define SB_PU (3 << 12) +#define WKEN (1 << 14) + #define M0 0 #define M1 1 #define M2 2 @@ -36,8 +49,8 @@ #define M7 7 /* - * To get the actual address the offset has to added - * with OMAP34XX_CTRL_BASE to get the actual address + * To get the actual address the offset has to be added + * to OMAP34XX_CTRL_BASE */ /*SDRC*/ @@ -78,6 +91,33 @@ #define CONTROL_PADCONF_SDRC_DQS1 0x0074 #define CONTROL_PADCONF_SDRC_DQS2 0x0076 #define CONTROL_PADCONF_SDRC_DQS3 0x0078 +#define CONTROL_PADCONF_SDRC_BA0 0x05A0 +#define CONTROL_PADCONF_SDRC_BA1 0x05A2 +#define CONTROL_PADCONF_SDRC_A0 0x05A4 +#define CONTROL_PADCONF_SDRC_A1 0x05A6 +#define CONTROL_PADCONF_SDRC_A2 0x05A8 +#define CONTROL_PADCONF_SDRC_A3 0x05AA +#define CONTROL_PADCONF_SDRC_A4 0x05AC +#define CONTROL_PADCONF_SDRC_A5 0x05AE +#define CONTROL_PADCONF_SDRC_A6 0x05B0 +#define CONTROL_PADCONF_SDRC_A7 0x05B2 +#define CONTROL_PADCONF_SDRC_A8 0x05B4 +#define CONTROL_PADCONF_SDRC_A9 0x05B6 +#define CONTROL_PADCONF_SDRC_A10 0x05B8 +#define CONTROL_PADCONF_SDRC_A11 0x05BA +#define CONTROL_PADCONF_SDRC_A12 0x05BC +#define CONTROL_PADCONF_SDRC_A13 0x05BE +#define CONTROL_PADCONF_SDRC_A14 0x05C0 +#define CONTROL_PADCONF_SDRC_NCS0 0x05C2 +#define CONTROL_PADCONF_SDRC_NCS1 0x05C4 +#define CONTROL_PADCONF_SDRC_NCLK 0x05C6 +#define CONTROL_PADCONF_SDRC_NRAS 0x05C8 +#define CONTROL_PADCONF_SDRC_NCAS 0x05CA +#define CONTROL_PADCONF_SDRC_NWE 0x05CC +#define CONTROL_PADCONF_SDRC_DM0 0x05CE +#define CONTROL_PADCONF_SDRC_DM1 0x05D0 +#define CONTROL_PADCONF_SDRC_DM2 0x05D2 +#define CONTROL_PADCONF_SDRC_DM3 0x05D4 /*GPMC*/ #define CONTROL_PADCONF_GPMC_A1 0x007A #define CONTROL_PADCONF_GPMC_A2 0x007C @@ -89,6 +129,7 @@ #define CONTROL_PADCONF_GPMC_A8 0x0088 #define CONTROL_PADCONF_GPMC_A9 0x008A #define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_A11 0x0264 #define CONTROL_PADCONF_GPMC_D0 0x008E #define CONTROL_PADCONF_GPMC_D1 0x0090 #define CONTROL_PADCONF_GPMC_D2 0x0092 @@ -281,7 +322,7 @@ #define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 #define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A #define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C #define CONTROL_PADCONF_JTAG_TCK 0x0A1E #define CONTROL_PADCONF_JTAG_TMS 0x0A20 #define CONTROL_PADCONF_JTAG_TDI 0x0A22 @@ -323,6 +364,8 @@ #define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 #define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 #define CONTROL_PADCONF_ETK_D15_ES2 0x05FA +#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E +#define CONTROL_PADCONF_JTAG_TDO 0x0A50 /*Die to Die */ #define CONTROL_PADCONF_D2D_MCAD0 0x01E4 #define CONTROL_PADCONF_D2D_MCAD1 0x01E6 @@ -433,6 +476,10 @@ #define CONTROL_PADCONF_SYS_BOOT8 0x0226 /* AM/DM37xx specific */ +#define CONTROL_PADCONF_GPIO112 0x0134 +#define CONTROL_PADCONF_GPIO113 0x0136 +#define CONTROL_PADCONF_GPIO114 0x0138 +#define CONTROL_PADCONF_GPIO115 0x013A #define CONTROL_PADCONF_GPIO127 0x0A54 #define CONTROL_PADCONF_GPIO126 0x0A56 #define CONTROL_PADCONF_GPIO128 0x0A58 @@ -443,7 +490,7 @@ #define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C) #define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6) -#define MUX_VAL(OFFSET,VALUE)\ +#define MUX_VAL(OFFSET, VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); #define CP(x) (CONTROL_PADCONF_##x) diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 7fb549af54..194b93bf56 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -55,6 +55,7 @@ struct control_prog_io { #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) +#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000) /* General Purpose Timers */ #define OMAP34XX_GPT1 0x48318000 @@ -139,13 +140,13 @@ struct gpio { SRAM_OFFSET2) #define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) -#define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ -#define OMAP3_PUBLIC_SRAM_END 0x40210000 +#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */ +#define NON_SECURE_SRAM_END 0x40210000 #define LOW_LEVEL_SRAM_STACK 0x4020FFFC /* scratch area - accessible on both EMU and GP */ -#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA OMAP3_PUBLIC_SRAM_BASE +#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START #define DEBUG_LED1 149 /* gpio */ #define DEBUG_LED2 150 /* gpio */ diff --git a/arch/arm/include/asm/arch-omap3/omap_gpmc.h b/arch/arm/include/asm/arch-omap3/omap_gpmc.h deleted file mode 100644 index bf2321932a..0000000000 --- a/arch/arm/include/asm/arch-omap3/omap_gpmc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -/* - * These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library. - * The OOB layout was first defined by linx kernel in commit - * 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause - * we want to be compatible. - */ -#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ - .eccbytes = 56,\ - .eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\ - 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\ - 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\ - 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\ - .oobfree = {\ - {.offset = 2,\ - .length = 10 } } \ -} - -/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ -#define NET_LAN9221_GPMC_CONFIG1 0x00001000 -#define NET_LAN9221_GPMC_CONFIG2 0x00060700 -#define NET_LAN9221_GPMC_CONFIG3 0x00020201 -#define NET_LAN9221_GPMC_CONFIG4 0x06000700 -#define NET_LAN9221_GPMC_CONFIG5 0x0006090A -#define NET_LAN9221_GPMC_CONFIG6 0x87030000 -#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c - -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h index 2ec319c08a..8350532786 100644 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ b/arch/arm/include/asm/arch-omap3/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 43b54f7cae..bcf92fbe65 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -7,6 +7,8 @@ */ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include +#include typedef struct { u32 mtype; @@ -21,6 +23,7 @@ struct emu_hal_params { /* Board SDRC timing values */ struct board_sdrc_timings { + u32 sharing; u32 mcfg; u32 ctrla; u32 ctrlb; @@ -61,13 +64,14 @@ void secureworld_exit(void); void try_unlock_memory(void); u32 get_boot_type(void); void invalidate_dcache(u32); -void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); +void cancel_out(u32 *num, u32 *den, u32 den_limit); void sdelay(unsigned long); void make_cs1_contiguous(void); void omap_nand_switch_ecc(uint32_t, uint32_t); void power_init_r(void); void dieid_num_r(void); +void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap3_gp_romcode_call(u32 service_id, u32 parameter); u32 warm_reset(void); diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index b2e03d6e1e..f3a682a197 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -149,11 +149,16 @@ /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 -/* SMPS */ +/* PMIC */ #define SMPS_I2C_SLAVE_ADDR 0x12 +/* TWL6030 SMPS */ #define SMPS_REG_ADDR_VCORE1 0x55 #define SMPS_REG_ADDR_VCORE2 0x5B #define SMPS_REG_ADDR_VCORE3 0x61 +/* TWL6032 SMPS */ +#define SMPS_REG_ADDR_SMPS1 0x55 +#define SMPS_REG_ADDR_SMPS2 0x5B +#define SMPS_REG_ADDR_SMPS5 0x49 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 545d9d96ad..f7595ae577 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -12,53 +12,10 @@ #include #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ +#include + #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - struct gptimer { u32 tidr; /* 0x00 r */ u8 res[0xc]; @@ -102,9 +59,6 @@ struct watchdog { #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* GPMC BASE */ -#define GPMC_BASE (OMAP44XX_GPMC_BASE) - /* I2C base */ #define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h index fdf65edab8..72ba1d71a2 100644 --- a/arch/arm/include/asm/arch-omap4/gpio.h +++ b/arch/arm/include/asm/arch-omap4/gpio.h @@ -2,20 +2,7 @@ * Copyright (c) 2009 Wind River Systems, Inc. * Tom Rix * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * This work is derived from the linux 2.6.27 kernel source * To fetch, use the kernel repository @@ -30,10 +17,6 @@ * * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _GPIO_OMAP4_H #define _GPIO_OMAP4_H diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h new file mode 100644 index 0000000000..f7011b4e90 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/hardware.h @@ -0,0 +1,26 @@ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h new file mode 100644 index 0000000000..d2e708bba5 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mem.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * + * Author + * Mansoor Ahamed + * + * Initial Code from: + * Richard Woodruff + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 3823a37f2f..d43dc265cd 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -33,6 +33,10 @@ /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 +#define STD_FUSE_DIE_ID_0 0x4A002200 +#define STD_FUSE_DIE_ID_1 0x4A002208 +#define STD_FUSE_DIE_ID_2 0x4A00220c +#define STD_FUSE_DIE_ID_3 0x4A002210 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F @@ -41,6 +45,7 @@ #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) @@ -55,9 +60,6 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) -/* GPMC */ -#define OMAP44XX_GPMC_BASE 0x50000000 - /* * Hardware Register Details */ @@ -111,7 +113,7 @@ struct s32ktimer { */ #define NON_SECURE_SRAM_START 0x40304000 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4030D000 diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index 551b27df14..fb842a2264 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 39c531632e..e19975efaf 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -12,10 +12,19 @@ #include #include #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; +extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; +extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; +extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; +extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; +extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; struct omap_sysinfo { char *board_string; }; @@ -26,8 +35,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); -void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void set_pl310_ctrl_reg(u32 val); @@ -50,54 +57,4 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void setup_warmreset_time(void); - -static inline u32 running_from_sdram(void) -{ - u32 pc; - asm volatile ("mov %0, pc" : "=r" (pc)); - return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && - (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); -} - -static inline u8 uboot_loaded_by_spl(void) -{ - /* - * u-boot can be running from sdram either because of configuration - * Header or by SPL. If because of CH, then the romcode sets the - * CHSETTINGS executed bit to true in the boot parameter structure that - * it passes to the bootloader.This parameter is stored in the ch_flags - * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a - * mandatory section if CH is present. - */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) - return 0; - else - return running_from_sdram(); -} -/* - * The basic hardware init of OMAP(s_init()) can happen in 4 - * different contexts: - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. Non-XIP U-Boot loaded to SDRAM by SPL - * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * - * This function finds this context. - * Defining as inline may help in compiling out unused functions in SPL - */ -static inline u32 omap_hw_init_context(void) -{ -#ifdef CONFIG_SPL_BUILD - return OMAP_INIT_CONTEXT_SPL; -#else - if (uboot_loaded_by_spl()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; - else if (running_from_sdram()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; - else - return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; -#endif -} - #endif diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 3adfc090fe..f8e5630bcb 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -137,6 +137,9 @@ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) +/* CM_L3INIT_SATA_CLKCTRL */ +#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + /* CM_WKUP_GPTIMER1_CLKCTRL */ #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) @@ -149,6 +152,33 @@ /* CM_L3INIT_USBPHY_CLKCTRL */ #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 +/* CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OPTFCLKEN_FUNC48M_CLK (1 << 15) +#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14) +#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13) +#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12) +#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11) +#define OPTFCLKEN_UTMI_P3_CLK (1 << 10) +#define OPTFCLKEN_UTMI_P2_CLK (1 << 9) +#define OPTFCLKEN_UTMI_P1_CLK (1 << 8) +#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7) +#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6) + +/* CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8) +#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) +#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) + +/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) + +/* CM_L3INIT_USB_OTG_SS_CLKCTRL */ +#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) +#define OPTFCLKEN_REFCLK960M (1 << 8) + +/* CM_L3INIT_OCP2SCP1_CLKCTRL */ +#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) + /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) @@ -175,6 +205,10 @@ /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 +/* CTRL_CORE_SRCOMP_NORTH_SIDE */ +#define USB2PHY_DISCHGDET (1 << 29) +#define USB2PHY_AUTORESUME_EN (1 << 30) + /* SMPS */ #define SMPS_I2C_SLAVE_ADDR 0x12 #define SMPS_REG_ADDR_12_MPU 0x23 @@ -202,13 +236,20 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880 -/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ -#define VDD_MPU_DRA752 1090 +/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */ +#define VDD_MPU_DRA752 1100 #define VDD_EVE_DRA752 1060 #define VDD_GPU_DRA752 1060 -#define VDD_CORE_DRA752 1030 +#define VDD_CORE_DRA752 1060 #define VDD_IVA_DRA752 1060 +/* DRA72x voltage settings in mv for OPP_NOM per DM */ +#define VDD_MPU_DRA72x 1100 +#define VDD_EVE_DRA72x 1060 +#define VDD_GPU_DRA72x 1060 +#define VDD_CORE_DRA72x 1060 +#define VDD_IVA_DRA72x 1060 + /* Efuse register offsets for DRA7xx platform */ #define DRA752_EFUSE_BASE 0x4A002000 #define DRA752_EFUSE_REGBITS 16 @@ -244,11 +285,18 @@ /* TPS659038 */ #define TPS659038_I2C_SLAVE_ADDR 0x58 -#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 -#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B -#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F -#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 -#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 +#define TPS659038_REG_ADDR_SMPS12 0x23 +#define TPS659038_REG_ADDR_SMPS45 0x2B +#define TPS659038_REG_ADDR_SMPS6 0x2F +#define TPS659038_REG_ADDR_SMPS7 0x33 +#define TPS659038_REG_ADDR_SMPS8 0x37 + +/* TPS65917 */ +#define TPS65917_I2C_SLAVE_ADDR 0x58 +#define TPS65917_REG_ADDR_SMPS1 0x23 +#define TPS65917_REG_ADDR_SMPS2 0x27 +#define TPS65917_REG_ADDR_SMPS3 0x2F + /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 @@ -280,7 +328,7 @@ */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define V_OSCK 20000000 /* Clock output from T2 */ #else #define V_OSCK 19200000 /* Clock output from T2 */ @@ -288,6 +336,9 @@ #define V_SCLK V_OSCK +/* CKO buffer control */ +#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) + /* AUXCLKx reg fields */ #define AUXCLK_ENABLE_MASK (1 << 8) #define AUXCLK_SRCSELECT_SHIFT 1 diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 3de5984948..6109b92777 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -14,53 +14,10 @@ #include #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ +#include + #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - struct gptimer { u32 tidr; /* 0x00 r */ u8 res1[0xc]; @@ -99,6 +56,8 @@ struct watchdog { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ +#define BIT(x) (1 << (x)) + #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 @@ -106,9 +65,6 @@ struct watchdog { #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* GPMC BASE */ -#define GPMC_BASE (OMAP54XX_GPMC_BASE) - /* I2C base */ #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) @@ -158,4 +114,8 @@ struct watchdog { #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) #define PRM_RSTST_WARM_RESET_MASK 0x7FEA +/* DRA7XX CPSW Config space */ +#define CPSW_BASE 0x48484000 +#define CPSW_MDIO_BASE 0x48485000 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h new file mode 100644 index 0000000000..63aaa020d2 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/ehci.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com* + * Author: Govindraj R + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EHCI_H +#define _EHCI_H + +#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00) +#define OMAP_UHH_BASE (OMAP54XX_L4_CORE_BASE + 0x64000) +#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000) + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 + +#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) +#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) + +#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ + OMAP_UHH_SYSCONFIG_NOSTDBY) + +#endif /* _EHCI_H */ diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h index 7c82f90360..9dd03c9fa6 100644 --- a/arch/arm/include/asm/arch-omap5/gpio.h +++ b/arch/arm/include/asm/arch-omap5/gpio.h @@ -2,20 +2,7 @@ * Copyright (c) 2009 Wind River Systems, Inc. * Tom Rix * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * This work is derived from the linux 2.6.27 kernel source * To fetch, use the kernel repository @@ -30,10 +17,6 @@ * * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _GPIO_OMAP5_H #define _GPIO_OMAP5_H diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h new file mode 100644 index 0000000000..f7011b4e90 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -0,0 +1,26 @@ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h new file mode 100644 index 0000000000..3e5d655de9 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mem.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * + * Author + * Mansoor Ahamed + * + * Initial Code from: + * Richard Woodruff + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001000 +#define STNOR_GPMC_CONFIG2 0x001f1f00 +#define STNOR_GPMC_CONFIG3 0x001f1f01 +#define STNOR_GPMC_CONFIG4 0x1f011f01 +#define STNOR_GPMC_CONFIG5 0x001d1f1f +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000048 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index d08fcff8b3..e2181598d5 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -23,16 +23,11 @@ #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 #define OMAP54XX_L4_PER_BASE 0x48000000 -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF -#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START -#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END - /* CONTROL ID CODE */ #define CONTROL_CORE_ID_CODE 0x4A002204 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE #else #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE @@ -44,11 +39,14 @@ #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F +#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F +#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) +#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) /* General Purpose Timers */ #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) @@ -58,8 +56,11 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) -/* GPMC */ -#define OMAP54XX_GPMC_BASE 0x50000000 +/* QSPI */ +#define QSPI_BASE 0x4B300000 + +/* SATA */ +#define DWC_AHSATA_BASE 0x4A140000 /* * Hardware Register Details @@ -142,9 +143,9 @@ struct s32ktimer { #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 #define EFUSE_1 0x45145100 @@ -153,14 +154,23 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ -#ifdef CONFIG_DRA7XX +/* + * In all cases, the TRM defines the RAM Memory Map for the processor + * and indicates the area for the downloaded image. We use all of that + * space for download and once up and running may use other parts of the + * map for our needs. We set a scratch space that is at the end of the + * OMAP5 download area, but within the DRA7xx download area (as it is + * much larger) and do not, at this time, make use of the additional + * space. + */ +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ #else #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ #endif -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 @@ -189,9 +199,32 @@ struct s32ktimer { /* ABB efuse masks */ #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) +#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) +/* IO Delay module defines */ +#define CFG_IO_DELAY_BASE 0x4844A000 +#define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C) + +/* CPSW IO Delay registers*/ +#define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C) +#define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758) +#define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764) +#define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770) +#define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C) +#define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C) +#define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC) +#define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0) +#define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94) +#define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88) + +#define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA +#define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB +#define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000 +#define CFG_IO_DELAY_LOCK_MASK 0x400 + #ifndef __ASSEMBLY__ struct srcomp_params { s8 divide_factor; @@ -206,7 +239,13 @@ struct ctrl_ioregs { u32 ctrl_ddrio_1; u32 ctrl_ddrio_2; u32 ctrl_emif_sdram_config_ext; + u32 ctrl_emif_sdram_config_ext_final; u32 ctrl_ddr_ctrl_ext_0; }; + +struct io_delay { + u32 addr; + u32 dly; +}; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h new file mode 100644 index 0000000000..b69165b5ee --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/sata.h @@ -0,0 +1,39 @@ +/* + * SATA Wrapper Register map + * + * (C) Copyright 2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TI_SATA_H +#define _TI_SATA_H + +/* SATA Wrapper module */ +#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100) +/* SATA PHY Module */ +#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800) + +/* SATA Wrapper register offsets */ +#define TI_SATA_SYSCONFIG 0x00 +#define TI_SATA_CDRLOCK 0x04 + +/* Register Set */ +#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16) +#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4) +#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2) + +/* Standby modes */ +#define TI_SATA_STANDBY_FORCE 0x0 +#define TI_SATA_STANDBY_NO (0x1 << 4) +#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4) +#define TI_SATA_STANDBY_SMART (0x2 << 4) + +/* Idle modes */ +#define TI_SATA_IDLE_FORCE 0x0 +#define TI_SATA_IDLE_NO (0x1 << 2) +#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2) +#define TI_SATA_IDLE_SMART (0x2 << 2) + +#endif /* _TI_SATA_H */ diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index fe8b0c01ad..f70799860f 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 @@ -15,6 +15,9 @@ #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SATA 9 +#define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_UART 0x43 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 9e70d48f43..103830319a 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -12,7 +12,9 @@ #include #include #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -31,8 +33,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); -void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void setup_clocks_for_console(void); @@ -57,55 +57,6 @@ void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); void setup_warmreset_time(void); -static inline u32 running_from_sdram(void) -{ - u32 pc; - asm volatile ("mov %0, pc" : "=r" (pc)); - return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) && - (pc < OMAP54XX_DRAM_ADDR_SPACE_END)); -} - -static inline u8 uboot_loaded_by_spl(void) -{ - /* - * u-boot can be running from sdram either because of configuration - * Header or by SPL. If because of CH, then the romcode sets the - * CHSETTINGS executed bit to true in the boot parameter structure that - * it passes to the bootloader.This parameter is stored in the ch_flags - * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a - * mandatory section if CH is present. - */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) - return 0; - else - return running_from_sdram(); -} -/* - * The basic hardware init of OMAP(s_init()) can happen in 4 - * different contexts: - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. Non-XIP U-Boot loaded to SDRAM by SPL - * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * - * This function finds this context. - * Defining as inline may help in compiling out unused functions in SPL - */ -static inline u32 omap_hw_init_context(void) -{ -#ifdef CONFIG_SPL_BUILD - return OMAP_INIT_CONTEXT_SPL; -#else - if (uboot_loaded_by_spl()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; - else if (running_from_sdram()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; - else - return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; -#endif -} - static inline u32 div_round_up(u32 num, u32 den) { return (num + den - 1)/den; diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h index fdccd222dd..1eed7b1d56 100644 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ b/arch/arm/include/asm/arch-pantheon/config.h @@ -11,7 +11,6 @@ #include -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ /* default Dcache Line length for pantheon */ #define CONFIG_SYS_CACHELINE_SIZE 32 diff --git a/arch/microblaze/lib/time.c b/arch/arm/include/asm/arch-pantheon/gpio.h similarity index 100% rename from arch/microblaze/lib/time.c rename to arch/arm/include/asm/arch-pantheon/gpio.h diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h index 2397bcef0d..e671c143ac 100644 --- a/arch/arm/include/asm/arch-pxa/hardware.h +++ b/arch/arm/include/asm/arch-pxa/hardware.h @@ -18,7 +18,6 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include #include /* diff --git a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h new file mode 100644 index 0000000000..463654efd3 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2014 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __EHCI_RMOBILE_H__ +#define __EHCI_RMOBILE_H__ + +/* Register offset */ +#define OHCI_OFFSET 0x00 +#define OHCI_SIZE 0x1000 +#define EHCI_OFFSET 0x1000 +#define EHCI_SIZE 0x1000 + +#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) + +/* USBCTR */ +#define DIRPD (1 << 8) +#define PLL_RST (1 << 2) +#define PCICLK_MASK (1 << 1) +#define USBH_RST (1 << 0) + +/* CMND_STS */ +#define SERREN (1 << 8) +#define PERREN (1 << 6) +#define MASTEREN (1 << 2) +#define MEMEN (1 << 1) + +/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ +#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) + +/* AHBPCI_WIN1_CTR */ +#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) +#define AHB_CFG_AHBPCI 0x40000000 +#define AHB_CFG_HOST 0x80000000 + +/* AHBPCI_WIN2_CTR */ +#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) + +/* PCI_INT_ENABLE */ +#define USBH_PMEEN (1 << 19) +#define USBH_INTBEN (1 << 17) +#define USBH_INTAEN (1 << 16) + +/* AHB_BUS_CTR */ +#define SMODE_READY_CTR (1 << 17) +#define SMODE_READ_BURST (1 << 16) +#define MMODE_HBUSREQ (1 << 7) +#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) +#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) +#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) +#define MMODE_WR_INCR (1 << 2) +#define MMODE_BYTE_BURST (1 << 1) +#define MMODE_HTRANS (1 << 0) + +/* PCI_ARBITER_CTR */ +#define PCIBUS_PARK_TIMER 0x00FF0000 +#define PCIBUS_PARK_TIMER_SET 0x00070000 +#define PCIBP_MODE (1 << 12) +#define PCIREQ7 (1 << 7) +#define PCIREQ6 (1 << 6) +#define PCIREQ5 (1 << 5) +#define PCIREQ4 (1 << 4) +#define PCIREQ3 (1 << 3) +#define PCIREQ2 (1 << 2) +#define PCIREQ1 (1 << 1) +#define PCIREQ0 (1 << 0) + +#define SMSTPCR7 0xE615014C +#define SMSTPCR703 (1 << 3) + +/* Init AHB master and slave functions of the host logic */ +#define AHB_BUS_CTR_INIT \ + (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ + MMODE_BYTE_BURST | MMODE_HTRANS) + +#define USBCTR_WIN_SIZE_1GB 0x800 + +/* PCI Configuration Registers */ +#define PCI_CONF_OHCI_OFFSET 0x10000 +#define PCI_CONF_EHCI_OFFSET 0x10100 +struct ahb_pciconf { + u32 vid_did; + u32 cmnd_sts; + u32 rev; + u32 cache_line; + u32 basead; +}; + +/* PCI Configuration Registers for AHB-PCI Bridge Registers */ +#define PCI_CONF_AHBPCI_OFFSET 0x10000 +struct ahbconf_pci_bridge { + u32 vid_did; /* 0x00 */ + u32 cmnd_sts; + u32 revid_cc; + u32 cls_lt_ht_bist; + u32 basead; /* 0x10 */ + u32 win1_basead; + u32 win2_basead; + u32 dummy0[5]; + u32 ssvdi_ssid; /* 0x2C */ + u32 dummy1[4]; + u32 intr_line_pin; +}; + +/* AHB-PCI Bridge PCI Communication Registers */ +#define AHBPCI_OFFSET 0x10800 +struct ahbcom_pci_bridge { + u32 pciahb_win1_ctr; /* 0x00 */ + u32 pciahb_win2_ctr; + u32 pciahb_dct_ctr; + u32 dummy0; + u32 ahbpci_win1_ctr; /* 0x10 */ + u32 ahbpci_win2_ctr; + u32 dummy1; + u32 ahbpci_dct_ctr; + u32 pci_int_enable; /* 0x20 */ + u32 pci_int_status; + u32 dummy2[2]; + u32 ahb_bus_ctr; /* 0x30 */ + u32 usbctr; + u32 dummy3[2]; + u32 pci_arbiter_ctr; /* 0x40 */ + u32 dummy4; + u32 pci_unit_rev; /* 0x48 */ +}; + +struct rmobile_ehci_reg { + u32 hciversion; /* hciversion/caplength */ + u32 hcsparams; /* hcsparams */ + u32 hccparams; /* hccparams */ + u32 hcsp_portroute; /* hcsp_portroute */ + u32 usbcmd; /* usbcmd */ + u32 usbsts; /* usbsts */ + u32 usbintr; /* usbintr */ + u32 frindex; /* frindex */ + u32 ctrldssegment; /* ctrldssegment */ + u32 periodiclistbase; /* periodiclistbase */ + u32 asynclistaddr; /* asynclistaddr */ + u32 dummy[9]; + u32 configflag; /* configflag */ + u32 portsc; /* portsc */ +}; + +#endif /* __EHCI_RMOBILE_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h index 6b5e4ed4eb..93b20af7ea 100644 --- a/arch/arm/include/asm/arch-rmobile/gpio.h +++ b/arch/arm/include/asm/arch-rmobile/gpio.h @@ -7,6 +7,18 @@ void sh73a0_pinmux_init(void); #elif defined(CONFIG_R8A7740) #include "r8a7740-gpio.h" void r8a7740_pinmux_init(void); +#elif defined(CONFIG_R8A7790) +#include "r8a7790-gpio.h" +void r8a7790_pinmux_init(void); +#elif defined(CONFIG_R8A7791) +#include "r8a7791-gpio.h" +void r8a7791_pinmux_init(void); +#elif defined(CONFIG_R8A7793) +#include "r8a7793-gpio.h" +void r8a7793_pinmux_init(void); +#elif defined(CONFIG_R8A7794) +#include "r8a7794-gpio.h" +void r8a7794_pinmux_init(void); #endif #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-rmobile/mmc.h b/arch/arm/include/asm/arch-rmobile/mmc.h new file mode 100644 index 0000000000..4e0fef1198 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/mmc.h @@ -0,0 +1,14 @@ +/* + * Renesas SuperH MMCIF driver. + * + * Copyright (C) 2014 Nobuhiro Iwamatsu + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _RMOBILE_MMC_H_ +#define _RMOBILE_MMC_H_ + +int mmcif_mmc_init(void); + +#endif /* _RMOBILE_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h new file mode 100644 index 0000000000..74b5f1df59 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h @@ -0,0 +1,387 @@ +#ifndef __ASM_R8A7790_GPIO_H__ +#define __ASM_R8A7790_GPIO_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, + GPIO_GP_1_28, GPIO_GP_1_29, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, + + GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS, + GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2, + GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2, + + /* IPSR0 */ + GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5, + GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2, + GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B, + GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4, + GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4, + GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5, + GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5, + GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6, + GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B, + GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C, + GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C, + GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0, + GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0, + + /* IPSR1 */ + GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1, + GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10, + GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2, + GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11, + GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3, + GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3, + GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4, + GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4, + GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N, + GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14, + GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B, + GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6, + GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B, + GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7, + GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4, + + /* IPSR2 */ + GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3, + GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B, + GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1, + GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7, + GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3, + GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4, + GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B, + GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5, + GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B, + GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6, + GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B, + + /* IPSR3 */ + GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0, + GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B, + GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1, + GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B, + GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2, + GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2, + GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B, + GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15, + GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16, + GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N, + GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19, + GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20, + GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4, + + /* IPSR4 */ + GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B, + GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5, + GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2, + GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24, + GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB, + GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6, + GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N, + GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B, + GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B, + GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B, + GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B, + GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK, + GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B, + GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B, + GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2, + + /* IPSR5 */ + GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1, + GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N, + GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N, + GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B, + GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX, + GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2, + GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N, + GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B, + GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N, + GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3, + GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B, + GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK, + GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B, + GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4, + GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B, + GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N, + GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B, + GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N, + GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C, + GPIO_FN_SSI_WS78_B, + + /* IPSR6 */ + GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B, + GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C, + GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B, + GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1, + GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C, + GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B, + GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N, + GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B, + GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B, + GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E, + GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER, + GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C, + GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0, + GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C, + GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1, + GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B, + GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G, + GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E, + GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E, + GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E, + GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F, + + /* IPSR7 */ + GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E, + GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1, + GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F, + GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C, + GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC, + GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0, + GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C, + GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B, + GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0, + GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C, + GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C, + GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C, + GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C, + GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN, + GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK, + GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1, + GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2, + GPIO_FN_MII_RXD2, + + /* IPSR8 */ + GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3, + GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N, + GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N, + GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N, + GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1, + GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER, + GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK, + GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV, + GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D, + GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1, + GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC, + GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO, + GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D, + GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D, + GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5, + GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK, + GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD, + GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B, + + /* IPSR9 */ + GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B, + GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B, + GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B, + GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B, + GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP, + GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B, + GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP, + GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN, + GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B, + GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK, + GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD, + GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B, + GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK, + GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK, + GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2, + GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B, + GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0, + GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6, + GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B, + GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B, + GPIO_FN_VI3_CLK_B, + + /* IPSR10 */ + GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN, + GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D, + GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK, + GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B, + GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D, + GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D, + GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B, + GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B, + GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D, + GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B, + GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA, + GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D, + GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B, + GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK, + GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B, + GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3, + GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B, + GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B, + GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4, + GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0, + GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B, + GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B, + + /* IPSR11 */ + GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN, + GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D, + GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B, + GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD, + GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N, + GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2, + GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3, + GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1, + GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP, + GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C, + GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F, + GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B, + GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B, + GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN, + GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C, + GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B, + GPIO_FN_MOUT0, + + /* IPSR12 */ + GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1, + GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2, + GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5, + GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6, + GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK, + GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34, + GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC, + GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0, + GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK, + GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N, + GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0, + GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1, + GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD, + GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK, + GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS, + GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD, + GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE, + GPIO_FN_CAN_DEBUGOUT4, + + /* IPSR13 */ + GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2, + GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6, + GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C, + GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6, + GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6, + GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4, + GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6, + GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5, + GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1, + GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6, + GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1, + GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7, + GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7, + GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N, + GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11, + GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8, + GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C, + GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9, + GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1, + GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA, + GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14, + + /* IPSR14 */ + GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D, + GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15, + GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0, + GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C, + GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0, + GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1, + GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N, + GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3, + GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C, + GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS, + GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B, + GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1, + GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1, + GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK, + GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK, + GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS, + GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE, + GPIO_FN_HRTS0_N_C, + + /* IPSR15 */ + GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7, + GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN, + GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS, + GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17, + GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0, + GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0, + GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3, + GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4, + GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5, + GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK, + GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0, + GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23, + GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0, + GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1, + GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14, + + /* IPSR16 */ + GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2, + GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B, + GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2, + GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C, + GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC, + GPIO_FN_TCLK1_B, +}; + +#endif /* __ASM_R8A7790_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h new file mode 100644 index 0000000000..748b802546 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h @@ -0,0 +1,41 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7790.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_R8A7790_H +#define __ASM_ARCH_R8A7790_H + +#include "rcar-base.h" + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 +#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0xDB6E9BDF +#define MSTP2_BITS 0x300DA1FC +#define MSTP3_BITS 0xF08CF831 +#define MSTP4_BITS 0x80000184 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x07F30718 +#define MSTP8_BITS 0x01F0FF84 +#define MSTP9_BITS 0xF5979FCF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x00000000 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 + +#define R8A7790_CUT_ES2X 2 +#define IS_R8A7790_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X) + +#endif /* __ASM_ARCH_R8A7790_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h new file mode 100644 index 0000000000..42e82597e7 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h @@ -0,0 +1,438 @@ +#ifndef __ASM_R8A7791_GPIO_H__ +#define __ASM_R8A7791_GPIO_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, + GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, + GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, + GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, + GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, + GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, + + GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, + GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7, + GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11, + GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15, + GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19, + GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23, + GPIO_GP_7_24, GPIO_GP_7_25, + + GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA, + GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0, + GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2, + GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5, + GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7, + GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, + + /* IPSR0 */ + GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5, + GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, + GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, + GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B, + GPIO_FN_SCL0_C, GPIO_FN_PWM2_B, + GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B, + GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B, + GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK, + + /* IPSR1 */ + GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8, + GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0, + GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0, + GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D, + GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D, + GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D, + GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D, + GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN, + GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D, + GPIO_FN_A15, GPIO_FN_BPFCLK_C, + GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B, + GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C, + GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C, + + /* IPSR2 */ + GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C, + GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B, + GPIO_FN_A20, GPIO_FN_SPCLK, + GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0, + GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B, + GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD, + GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B, + GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD, + GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3, + GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD, + GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C, + GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD, + GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1, + GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1, + GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK, + GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC, + GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD, + GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1, + + /* IPSR3 */ + GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N, + GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2, + GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1, + GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B, + GPIO_FN_PWM1, GPIO_FN_TPU_TO1, + GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2, + GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B, + GPIO_FN_PWM2, GPIO_FN_TPU_TO2, + GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B, + GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D, + GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B, + GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B, + GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B, + GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B, + GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3, + GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON, + GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C, + GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B, + GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D, + GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C, + GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C, + GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C, + GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C, + + /* IPSR4 */ + GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B, + GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C, + GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B, + GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D, + GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B, + GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D, + GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B, + GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C, + GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B, + GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E, + GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B, + GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E, + GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B, + GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E, + GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3, + GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D, + GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D, + GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D, + GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C, + GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0, + GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B, + + /* IPSR5 */ + GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0, + GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B, + GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0, + GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B, + GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0, + GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B, + GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK, + GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B, + GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B, + GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B, + GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS, + GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON, + GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B, + GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B, + GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D, + GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D, + GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D, + + /* IPSR6 */ + GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B, + GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E, + GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B, + GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B, + GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD, + GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N, + GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N, + GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N, + GPIO_FN_IRQ3, GPIO_FN_SCL4_C, + GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N, + GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C, + GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N, + GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E, + GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B, + GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E, + GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B, + GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, + GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B, + GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D, + + /* IPSR7 */ + GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D, + GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D, + GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B, + GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B, + GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B, + GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B, + GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B, + GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B, + GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B, + GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B, + GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B, + GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B, + GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B, + GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B, + GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B, + GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B, + GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B, + GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B, + + /* IPSR8 */ + GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11, + GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B, + GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B, + GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B, + GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B, + GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B, + GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B, + GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B, + GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B, + GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B, + GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B, + GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B, + GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B, + GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B, + GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B, + GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B, + GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20, + GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX, + GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3, + GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX, + + /* IPSR9 */ + GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C, + GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD, + GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C, + GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK, + GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS, + GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK, + GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX, + GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4, + GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS, + GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE, + GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B, + GPIO_FN_DU1_DISP, GPIO_FN_QPOLA, + GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B, + GPIO_FN_VI0_CLKENB, GPIO_FN_TX4, + GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D, + GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D, + GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5, + GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D, + GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5, + GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D, + GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B, + GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4, + GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N, + + /* IPSR10 */ + GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4, + GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N, + GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C, + GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N, + GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C, + GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N, + GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C, + GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D, + GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C, + GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E, + GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D, + GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D, + GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D, + GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B, + GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N, + GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B, + GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N, + GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3, + GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C, + GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4, + GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C, + GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B, + GPIO_FN_TX0_C, GPIO_FN_SCL1_D, + + /* IPSR11 */ + GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B, + GPIO_FN_RX0_C, GPIO_FN_SDA1_D, + GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B, + GPIO_FN_TX1_C, GPIO_FN_SCL4_B, + GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E, + GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D, + GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B, + GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B, + GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B, + GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B, + GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B, + GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B, + GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5, + GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6, + GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7, + GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER, + GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO, + GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV, + GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC, + GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC, + GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C, + GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C, + + /* IPSR12 */ + GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7, + GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7, + GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C, + GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E, + GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C, + GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E, + GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B, + GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E, + GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B, + GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E, + GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3, + GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B, + GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C, + GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C, + GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C, + GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D, + GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C, + GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D, + GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C, + + /* IPSR13 */ + GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C, + GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C, + GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK, + GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C, + GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL, + GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C, + GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B, + GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C, + GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B, + GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B, + GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B, + GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B, + GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B, + GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F, + GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C, + GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F, + GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C, + GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B, + GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B, + GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B, + GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B, + GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C, + + /* IPSR14 */ + GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C, + GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD, + GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1, + GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3, + GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C, + GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C, + GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C, + GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C, + GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA, + GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B, + GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP, + GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B, + GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK, + GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B, + GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0, + GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B, + GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E, + GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B, + GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E, + GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B, + + /* IPSR15 */ + GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D, + GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C, + GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D, + GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B, + GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C, + GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5, + GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C, + GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6, + GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C, + GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C, + GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C, + GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N, + GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C, + GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK, + GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C, + GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C, + GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C, + GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C, + GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C, + + /* IPSR16 */ + GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B, + GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C, + GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B, + GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C, + GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C, + GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N, + GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B, + GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N, + GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B, +}; + +#endif /* __ASM_R8A7791_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h new file mode 100644 index 0000000000..1d06b651f4 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h @@ -0,0 +1,76 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7791.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_R8A7791_H +#define __ASM_ARCH_R8A7791_H + +#include "rcar-base.h" +/* + * R-Car (R8A7791) I/O Addresses + */ + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + +#define DBSC3_1_QOS_R0_BASE 0xE67A1000 +#define DBSC3_1_QOS_R1_BASE 0xE67A1100 +#define DBSC3_1_QOS_R2_BASE 0xE67A1200 +#define DBSC3_1_QOS_R3_BASE 0xE67A1300 +#define DBSC3_1_QOS_R4_BASE 0xE67A1400 +#define DBSC3_1_QOS_R5_BASE 0xE67A1500 +#define DBSC3_1_QOS_R6_BASE 0xE67A1600 +#define DBSC3_1_QOS_R7_BASE 0xE67A1700 +#define DBSC3_1_QOS_R8_BASE 0xE67A1800 +#define DBSC3_1_QOS_R9_BASE 0xE67A1900 +#define DBSC3_1_QOS_R10_BASE 0xE67A1A00 +#define DBSC3_1_QOS_R11_BASE 0xE67A1B00 +#define DBSC3_1_QOS_R12_BASE 0xE67A1C00 +#define DBSC3_1_QOS_R13_BASE 0xE67A1D00 +#define DBSC3_1_QOS_R14_BASE 0xE67A1E00 +#define DBSC3_1_QOS_R15_BASE 0xE67A1F00 +#define DBSC3_1_QOS_W0_BASE 0xE67A2000 +#define DBSC3_1_QOS_W1_BASE 0xE67A2100 +#define DBSC3_1_QOS_W2_BASE 0xE67A2200 +#define DBSC3_1_QOS_W3_BASE 0xE67A2300 +#define DBSC3_1_QOS_W4_BASE 0xE67A2400 +#define DBSC3_1_QOS_W5_BASE 0xE67A2500 +#define DBSC3_1_QOS_W6_BASE 0xE67A2600 +#define DBSC3_1_QOS_W7_BASE 0xE67A2700 +#define DBSC3_1_QOS_W8_BASE 0xE67A2800 +#define DBSC3_1_QOS_W9_BASE 0xE67A2900 +#define DBSC3_1_QOS_W10_BASE 0xE67A2A00 +#define DBSC3_1_QOS_W11_BASE 0xE67A2B00 +#define DBSC3_1_QOS_W12_BASE 0xE67A2C00 +#define DBSC3_1_QOS_W13_BASE 0xE67A2D00 +#define DBSC3_1_QOS_W14_BASE 0xE67A2E00 +#define DBSC3_1_QOS_W15_BASE 0xE67A2F00 +#define DBSC3_1_DBADJ2 0xE67A00C8 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0x9B6C9B5A +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xF08CD810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x05BFE618 +#define MSTP8_BITS 0x40C0FE85 +#define MSTP9_BITS 0xFF979FFF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + +#define R8A7791_CUT_ES2X 2 +#define IS_R8A7791_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X) + +#endif /* __ASM_ARCH_R8A7791_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7793-gpio.h new file mode 100644 index 0000000000..f9a29fc144 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7793-gpio.h @@ -0,0 +1,438 @@ +#ifndef __ASM_R8A7793_H__ +#define __ASM_R8A7793_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, + GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, + GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, + GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, + GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, + GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, + + GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, + GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7, + GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11, + GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15, + GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19, + GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23, + GPIO_GP_7_24, GPIO_GP_7_25, + + GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA, + GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0, + GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2, + GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5, + GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7, + GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, + + /* IPSR0 */ + GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5, + GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, + GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, + GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B, + GPIO_FN_SCL0_C, GPIO_FN_PWM2_B, + GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B, + GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B, + GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK, + + /* IPSR1 */ + GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8, + GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0, + GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0, + GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D, + GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D, + GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D, + GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D, + GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN, + GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D, + GPIO_FN_A15, GPIO_FN_BPFCLK_C, + GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B, + GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C, + GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C, + + /* IPSR2 */ + GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C, + GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B, + GPIO_FN_A20, GPIO_FN_SPCLK, + GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0, + GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B, + GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD, + GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B, + GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD, + GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3, + GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD, + GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C, + GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD, + GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1, + GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1, + GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK, + GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC, + GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD, + GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1, + + /* IPSR3 */ + GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N, + GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2, + GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1, + GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B, + GPIO_FN_PWM1, GPIO_FN_TPU_TO1, + GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2, + GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B, + GPIO_FN_PWM2, GPIO_FN_TPU_TO2, + GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B, + GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D, + GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B, + GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B, + GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B, + GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B, + GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3, + GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON, + GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C, + GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B, + GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D, + GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C, + GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C, + GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C, + GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C, + + /* IPSR4 */ + GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B, + GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C, + GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B, + GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D, + GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B, + GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D, + GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B, + GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C, + GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B, + GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E, + GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B, + GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E, + GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B, + GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E, + GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3, + GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D, + GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D, + GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D, + GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C, + GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0, + GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B, + + /* IPSR5 */ + GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0, + GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B, + GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0, + GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B, + GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0, + GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B, + GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK, + GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B, + GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B, + GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B, + GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS, + GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON, + GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B, + GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B, + GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D, + GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D, + GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D, + + /* IPSR6 */ + GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B, + GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E, + GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B, + GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B, + GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD, + GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N, + GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N, + GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N, + GPIO_FN_IRQ3, GPIO_FN_SCL4_C, + GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N, + GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C, + GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N, + GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E, + GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B, + GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E, + GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B, + GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, + GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B, + GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D, + + /* IPSR7 */ + GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D, + GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D, + GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B, + GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B, + GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B, + GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B, + GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B, + GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B, + GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B, + GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B, + GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B, + GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B, + GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B, + GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B, + GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B, + GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B, + GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B, + GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B, + + /* IPSR8 */ + GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11, + GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B, + GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B, + GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B, + GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B, + GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B, + GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B, + GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B, + GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B, + GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B, + GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B, + GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B, + GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B, + GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B, + GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B, + GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B, + GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20, + GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX, + GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3, + GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX, + + /* IPSR9 */ + GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C, + GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD, + GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C, + GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK, + GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS, + GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK, + GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX, + GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4, + GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS, + GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE, + GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B, + GPIO_FN_DU1_DISP, GPIO_FN_QPOLA, + GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B, + GPIO_FN_VI0_CLKENB, GPIO_FN_TX4, + GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D, + GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D, + GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5, + GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D, + GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5, + GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D, + GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B, + GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4, + GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N, + + /* IPSR10 */ + GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4, + GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N, + GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C, + GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N, + GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C, + GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N, + GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C, + GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D, + GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C, + GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E, + GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D, + GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D, + GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D, + GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B, + GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N, + GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B, + GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N, + GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3, + GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C, + GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4, + GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C, + GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B, + GPIO_FN_TX0_C, GPIO_FN_SCL1_D, + + /* IPSR11 */ + GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B, + GPIO_FN_RX0_C, GPIO_FN_SDA1_D, + GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B, + GPIO_FN_TX1_C, GPIO_FN_SCL4_B, + GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E, + GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D, + GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B, + GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B, + GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B, + GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B, + GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B, + GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B, + GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5, + GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6, + GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7, + GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER, + GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO, + GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV, + GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC, + GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC, + GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C, + GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C, + + /* IPSR12 */ + GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7, + GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7, + GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C, + GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E, + GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C, + GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E, + GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B, + GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E, + GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B, + GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E, + GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3, + GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B, + GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C, + GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C, + GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C, + GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D, + GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C, + GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D, + GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C, + + /* IPSR13 */ + GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C, + GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C, + GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK, + GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C, + GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL, + GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C, + GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B, + GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C, + GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B, + GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B, + GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B, + GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B, + GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B, + GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F, + GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C, + GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F, + GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C, + GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B, + GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B, + GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B, + GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B, + GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C, + + /* IPSR14 */ + GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C, + GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD, + GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1, + GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3, + GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C, + GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C, + GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C, + GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C, + GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA, + GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B, + GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP, + GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B, + GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK, + GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B, + GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0, + GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B, + GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E, + GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B, + GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E, + GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B, + + /* IPSR15 */ + GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D, + GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C, + GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D, + GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B, + GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C, + GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5, + GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C, + GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6, + GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C, + GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C, + GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C, + GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N, + GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C, + GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK, + GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C, + GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C, + GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C, + GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C, + GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C, + + /* IPSR16 */ + GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B, + GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C, + GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B, + GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C, + GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C, + GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N, + GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B, + GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N, + GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B, +}; + +#endif /* __ASM_R8A7793_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/include/asm/arch-rmobile/r8a7793.h new file mode 100644 index 0000000000..3efc62a1a9 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7793.h @@ -0,0 +1,82 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7793.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_R8A7793_H +#define __ASM_ARCH_R8A7793_H + +#include "rcar-base.h" + +/* + * R8A7793 I/O Addresses + */ + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + +#define DBSC3_1_QOS_R0_BASE 0xE67A1000 +#define DBSC3_1_QOS_R1_BASE 0xE67A1100 +#define DBSC3_1_QOS_R2_BASE 0xE67A1200 +#define DBSC3_1_QOS_R3_BASE 0xE67A1300 +#define DBSC3_1_QOS_R4_BASE 0xE67A1400 +#define DBSC3_1_QOS_R5_BASE 0xE67A1500 +#define DBSC3_1_QOS_R6_BASE 0xE67A1600 +#define DBSC3_1_QOS_R7_BASE 0xE67A1700 +#define DBSC3_1_QOS_R8_BASE 0xE67A1800 +#define DBSC3_1_QOS_R9_BASE 0xE67A1900 +#define DBSC3_1_QOS_R10_BASE 0xE67A1A00 +#define DBSC3_1_QOS_R11_BASE 0xE67A1B00 +#define DBSC3_1_QOS_R12_BASE 0xE67A1C00 +#define DBSC3_1_QOS_R13_BASE 0xE67A1D00 +#define DBSC3_1_QOS_R14_BASE 0xE67A1E00 +#define DBSC3_1_QOS_R15_BASE 0xE67A1F00 +#define DBSC3_1_QOS_W0_BASE 0xE67A2000 +#define DBSC3_1_QOS_W1_BASE 0xE67A2100 +#define DBSC3_1_QOS_W2_BASE 0xE67A2200 +#define DBSC3_1_QOS_W3_BASE 0xE67A2300 +#define DBSC3_1_QOS_W4_BASE 0xE67A2400 +#define DBSC3_1_QOS_W5_BASE 0xE67A2500 +#define DBSC3_1_QOS_W6_BASE 0xE67A2600 +#define DBSC3_1_QOS_W7_BASE 0xE67A2700 +#define DBSC3_1_QOS_W8_BASE 0xE67A2800 +#define DBSC3_1_QOS_W9_BASE 0xE67A2900 +#define DBSC3_1_QOS_W10_BASE 0xE67A2A00 +#define DBSC3_1_QOS_W11_BASE 0xE67A2B00 +#define DBSC3_1_QOS_W12_BASE 0xE67A2C00 +#define DBSC3_1_QOS_W13_BASE 0xE67A2D00 +#define DBSC3_1_QOS_W14_BASE 0xE67A2E00 +#define DBSC3_1_QOS_W15_BASE 0xE67A2F00 + +#define DBSC3_1_DBADJ2 0xE67A00C8 + +/* + * R8A7793 I/O Product Information + */ + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0x9B6C9B5A +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xF08CD810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x05BFE618 +#define MSTP8_BITS 0x40C0FE85 +#define MSTP9_BITS 0xFF979FFF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + +#define R8A7793_CUT_ES2X 2 +#define IS_R8A7793_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X) + +#endif /* __ASM_ARCH_R8A7793_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h new file mode 100644 index 0000000000..a45a67c4d6 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h @@ -0,0 +1,176 @@ +#ifndef __ASM_R8A7794_H__ +#define __ASM_R8A7794_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, + GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, + GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, + GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, + GPIO_GP_6_24, GPIO_GP_6_25, + + GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0, + GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, + GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD, + GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2, + GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP, + GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0, + GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28, + GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, + GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, + GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK, + GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1, + GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1, + GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4, + GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4, + GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7, + GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL, + GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7, + GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C, + GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N, + GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C, + GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B, + GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN, + GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B, + GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI, + + /* IPSR7 */ + GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B, + GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO, + GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B, + GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK, + GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B, + GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N, + GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B, + GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1, + GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B, + GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2, + GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C, + GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7, + GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6, + GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0, + GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7, + GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1, + GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B, + GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B, + GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B, + GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD, + + /* IPSR8 */ + GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B, + GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B, + GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C, + GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B, + GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C, + GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B, + GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D, + GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D, + GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B, + GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS, + GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C, + GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D, + GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0, + GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL, + GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B, + GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA, + GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B, + GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD, + GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2, + GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C, + GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5, + GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1, + GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B, + GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6, + GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, + GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B, + GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B, + GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78, + GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE, + GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8, + GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N, + GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D, + GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129, + GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B, + GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B, + GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +#endif /* __ASM_R8A7794_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h new file mode 100644 index 0000000000..6d11fa479b --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h @@ -0,0 +1,35 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7794.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_R8A7794_H +#define __ASM_ARCH_R8A7794_H + +#include "rcar-base.h" + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00440801 +#define MSTP1_BITS 0x936899DA +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xE084D810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x40C00044 +#define MSTP7_BITS 0x013FE618 +#define MSTP8_BITS 0x40803C05 +#define MSTP9_BITS 0xFB879FEE +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + +#endif /* __ASM_ARCH_R8A7794_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h new file mode 100644 index 0000000000..d594cd77c1 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -0,0 +1,703 @@ +/* + * arch/arm/include/asm/arch-rmobile/rcar-base.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_RCAR_BASE_H +#define __ASM_ARCH_RCAR_BASE_H + +/* + * R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses + */ +#define RWDT_BASE 0xE6020000 +#define SWDT_BASE 0xE6030000 +#define LBSC_BASE 0xFEC00200 +#define DBSC3_0_BASE 0xE6790000 +#define DBSC3_1_BASE 0xE67A0000 +#define TMU_BASE 0xE61E0000 +#define GPIO5_BASE 0xE6055000 +#define SH_QSPI_BASE 0xE6B10000 + +/* SCIF */ +#define SCIF0_BASE 0xE6E60000 +#define SCIF1_BASE 0xE6E68000 +#define SCIF2_BASE 0xE6E58000 +#define SCIF3_BASE 0xE6EA8000 +#define SCIF4_BASE 0xE6EE0000 +#define SCIF5_BASE 0xE6EE8000 + +/* Module stop status register */ +#define MSTPSR0 0xE6150030 +#define MSTPSR1 0xE6150038 +#define MSTPSR2 0xE6150040 +#define MSTPSR3 0xE6150048 +#define MSTPSR4 0xE615004C +#define MSTPSR5 0xE615003C +#define MSTPSR7 0xE61501C4 +#define MSTPSR8 0xE61509A0 +#define MSTPSR9 0xE61509A4 +#define MSTPSR10 0xE61509A8 +#define MSTPSR11 0xE61509AC + +/* Realtime module stop control register */ +#define RMSTPCR0 0xE6150110 +#define RMSTPCR1 0xE6150114 +#define RMSTPCR2 0xE6150118 +#define RMSTPCR3 0xE615011C +#define RMSTPCR4 0xE6150120 +#define RMSTPCR5 0xE6150124 +#define RMSTPCR7 0xE615012C +#define RMSTPCR8 0xE6150980 +#define RMSTPCR9 0xE6150984 +#define RMSTPCR10 0xE6150988 +#define RMSTPCR11 0xE615098C + +/* System module stop control register */ +#define SMSTPCR0 0xE6150130 +#define SMSTPCR1 0xE6150134 +#define SMSTPCR2 0xE6150138 +#define SMSTPCR3 0xE615013C +#define SMSTPCR4 0xE6150140 +#define SMSTPCR5 0xE6150144 +#define SMSTPCR7 0xE615014C +#define SMSTPCR8 0xE6150990 +#define SMSTPCR9 0xE6150994 +#define SMSTPCR10 0xE6150998 +#define SMSTPCR11 0xE615099C + +/* + * SH-I2C + * Ch2 and ch3 are different address. These are defined + * in the header of each SoCs. + */ +#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 + +/* RCAR-I2C */ +#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 +#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 +#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 +#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 + +#define S3C_BASE 0xE6784000 +#define S3C_INT_BASE 0xE6784A00 +#define S3C_MEDIA_BASE 0xE6784B00 + +#define S3C_QOS_DCACHE_BASE 0xE6784BDC +#define S3C_QOS_CCI0_BASE 0xE6784C00 +#define S3C_QOS_CCI1_BASE 0xE6784C24 +#define S3C_QOS_MXI_BASE 0xE6784C48 +#define S3C_QOS_AXI_BASE 0xE6784C6C + +#define DBSC3_0_QOS_R0_BASE 0xE6791000 +#define DBSC3_0_QOS_R1_BASE 0xE6791100 +#define DBSC3_0_QOS_R2_BASE 0xE6791200 +#define DBSC3_0_QOS_R3_BASE 0xE6791300 +#define DBSC3_0_QOS_R4_BASE 0xE6791400 +#define DBSC3_0_QOS_R5_BASE 0xE6791500 +#define DBSC3_0_QOS_R6_BASE 0xE6791600 +#define DBSC3_0_QOS_R7_BASE 0xE6791700 +#define DBSC3_0_QOS_R8_BASE 0xE6791800 +#define DBSC3_0_QOS_R9_BASE 0xE6791900 +#define DBSC3_0_QOS_R10_BASE 0xE6791A00 +#define DBSC3_0_QOS_R11_BASE 0xE6791B00 +#define DBSC3_0_QOS_R12_BASE 0xE6791C00 +#define DBSC3_0_QOS_R13_BASE 0xE6791D00 +#define DBSC3_0_QOS_R14_BASE 0xE6791E00 +#define DBSC3_0_QOS_R15_BASE 0xE6791F00 +#define DBSC3_0_QOS_W0_BASE 0xE6792000 +#define DBSC3_0_QOS_W1_BASE 0xE6792100 +#define DBSC3_0_QOS_W2_BASE 0xE6792200 +#define DBSC3_0_QOS_W3_BASE 0xE6792300 +#define DBSC3_0_QOS_W4_BASE 0xE6792400 +#define DBSC3_0_QOS_W5_BASE 0xE6792500 +#define DBSC3_0_QOS_W6_BASE 0xE6792600 +#define DBSC3_0_QOS_W7_BASE 0xE6792700 +#define DBSC3_0_QOS_W8_BASE 0xE6792800 +#define DBSC3_0_QOS_W9_BASE 0xE6792900 +#define DBSC3_0_QOS_W10_BASE 0xE6792A00 +#define DBSC3_0_QOS_W11_BASE 0xE6792B00 +#define DBSC3_0_QOS_W12_BASE 0xE6792C00 +#define DBSC3_0_QOS_W13_BASE 0xE6792D00 +#define DBSC3_0_QOS_W14_BASE 0xE6792E00 +#define DBSC3_0_QOS_W15_BASE 0xE6792F00 +#define DBSC3_0_DBADJ2 0xE67900C8 + +#define CCI_400_MAXOT_1 0xF0091110 +#define CCI_400_MAXOT_2 0xF0092110 +#define CCI_400_QOSCNTL_1 0xF009110C +#define CCI_400_QOSCNTL_2 0xF009210C + +#define MXI_BASE 0xFE960000 +#define MXI_QOS_BASE 0xFE960300 + +#define SYS_AXI_SYX64TO128_BASE 0xFF800300 +#define SYS_AXI_AVB_BASE 0xFF800340 +#define SYS_AXI_G2D_BASE 0xFF800540 +#define SYS_AXI_IMP0_BASE 0xFF800580 +#define SYS_AXI_IMP1_BASE 0xFF8005C0 +#define SYS_AXI_IMUX0_BASE 0xFF800600 +#define SYS_AXI_IMUX1_BASE 0xFF800640 +#define SYS_AXI_IMUX2_BASE 0xFF800680 +#define SYS_AXI_LBS_BASE 0xFF8006C0 +#define SYS_AXI_MMUDS_BASE 0xFF800700 +#define SYS_AXI_MMUM_BASE 0xFF800740 +#define SYS_AXI_MMUR_BASE 0xFF800780 +#define SYS_AXI_MMUS0_BASE 0xFF8007C0 +#define SYS_AXI_MMUS1_BASE 0xFF800800 +#define SYS_AXI_MTSB0_BASE 0xFF800880 +#define SYS_AXI_MTSB1_BASE 0xFF8008C0 +#define SYS_AXI_PCI_BASE 0xFF800900 +#define SYS_AXI_RTX_BASE 0xFF800940 +#define SYS_AXI_SDS0_BASE 0xFF800A80 +#define SYS_AXI_SDS1_BASE 0xFF800AC0 +#define SYS_AXI_USB20_BASE 0xFF800C00 +#define SYS_AXI_USB21_BASE 0xFF800C40 +#define SYS_AXI_USB22_BASE 0xFF800C80 +#define SYS_AXI_USB30_BASE 0xFF800CC0 +#define SYS_AXI_AX2M_BASE 0xFF800380 +#define SYS_AXI_CC50_BASE 0xFF8003C0 +#define SYS_AXI_CCI_BASE 0xFF800440 +#define SYS_AXI_CS_BASE 0xFF800480 +#define SYS_AXI_DDM_BASE 0xFF8004C0 +#define SYS_AXI_ETH_BASE 0xFF800500 +#define SYS_AXI_MPXM_BASE 0xFF800840 +#define SYS_AXI_SAT0_BASE 0xFF800980 +#define SYS_AXI_SAT1_BASE 0xFF8009C0 +#define SYS_AXI_SDM0_BASE 0xFF800A00 +#define SYS_AXI_SDM1_BASE 0xFF800A40 +#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */ +#define SYS_AXI_UDM0_BASE 0xFF800B80 +#define SYS_AXI_UDM1_BASE 0xFF800BC0 + +#define RT_AXI_SHX_BASE 0xFF810100 +#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */ +#define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */ +#define RT_AXI_RDS_BASE 0xFF8101C0 +#define RT_AXI_RTX64TO128_BASE 0xFF810200 +#define RT_AXI_STPRO_BASE 0xFF810240 +#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */ + +#define MP_AXI_ADSP_BASE 0xFF820100 +#define MP_AXI_ASDS0_BASE 0xFF8201C0 +#define MP_AXI_ASDS1_BASE 0xFF820200 +#define MP_AXI_MLP_BASE 0xFF820240 +#define MP_AXI_MMUMP_BASE 0xFF820280 +#define MP_AXI_SPU_BASE 0xFF8202C0 +#define MP_AXI_SPUC_BASE 0xFF820300 + +#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 +#define SYS_AXI256_SYX_BASE 0xFF860140 +#define SYS_AXI256_MPX_BASE 0xFF860180 +#define SYS_AXI256_MXI_BASE 0xFF8601C0 + +#define CCI_AXI_MMUS0_BASE 0xFF880100 +#define CCI_AXI_SYX2_BASE 0xFF880140 +#define CCI_AXI_MMUR_BASE 0xFF880180 +#define CCI_AXI_MMUDS_BASE 0xFF8801C0 +#define CCI_AXI_MMUM_BASE 0xFF880200 +#define CCI_AXI_MXI_BASE 0xFF880240 +#define CCI_AXI_MMUS1_BASE 0xFF880280 +#define CCI_AXI_MMUMP_BASE 0xFF8802C0 + +#define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */ +#define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */ +#define MEDIA_AXI_JPR_BASE 0xFE964100 +#define MEDIA_AXI_JPW_BASE 0xFE966100 +#define MEDIA_AXI_GCU0R_BASE 0xFE964140 +#define MEDIA_AXI_GCU0W_BASE 0xFE966140 +#define MEDIA_AXI_GCU1R_BASE 0xFE964180 +#define MEDIA_AXI_GCU1W_BASE 0xFE966180 +#define MEDIA_AXI_TDMR_BASE 0xFE964500 +#define MEDIA_AXI_TDMW_BASE 0xFE966500 +#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 +#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 +#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 +#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 +#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 +#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 +#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 +#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 +#define MEDIA_AXI_VIN0W_BASE 0xFE966900 +#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 +#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 +#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 +#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 +#define MEDIA_AXI_IMSR_BASE 0xFE964D80 +#define MEDIA_AXI_IMSW_BASE 0xFE966D80 +#define MEDIA_AXI_VSP1R_BASE 0xFE965100 +#define MEDIA_AXI_VSP1W_BASE 0xFE967100 +#define MEDIA_AXI_FDP1R_BASE 0xFE965140 +#define MEDIA_AXI_FDP1W_BASE 0xFE967140 +#define MEDIA_AXI_IMRR_BASE 0xFE965180 +#define MEDIA_AXI_IMRW_BASE 0xFE967180 +#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 +#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 +#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 +#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 +#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 +#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 +#define MEDIA_AXI_DU0R_BASE 0xFE965580 +#define MEDIA_AXI_DU0W_BASE 0xFE967580 +#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 +#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 +#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 +#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 +#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 +#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 +#define MEDIA_AXI_VPC0R_BASE 0xFE965980 +#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 +#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 +#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 +#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 +#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 + +#define SYS_AXI_AVBDMSCR 0xFF802000 +#define SYS_AXI_SYX2DMSCR 0xFF802004 +#define SYS_AXI_CC50DMSCR 0xFF802008 +#define SYS_AXI_CC51DMSCR 0xFF80200C +#define SYS_AXI_CCIDMSCR 0xFF802010 +#define SYS_AXI_CSDMSCR 0xFF802014 +#define SYS_AXI_DDMDMSCR 0xFF802018 +#define SYS_AXI_ETHDMSCR 0xFF80201C +#define SYS_AXI_G2DDMSCR 0xFF802020 +#define SYS_AXI_IMP0DMSCR 0xFF802024 +#define SYS_AXI_IMP1DMSCR 0xFF802028 +#define SYS_AXI_LBSDMSCR 0xFF80202C +#define SYS_AXI_MMUDSDMSCR 0xFF802030 +#define SYS_AXI_MMUMXDMSCR 0xFF802034 +#define SYS_AXI_MMURDDMSCR 0xFF802038 +#define SYS_AXI_MMUS0DMSCR 0xFF80203C +#define SYS_AXI_MMUS1DMSCR 0xFF802040 +#define SYS_AXI_MPXDMSCR 0xFF802044 +#define SYS_AXI_MTSB0DMSCR 0xFF802048 +#define SYS_AXI_MTSB1DMSCR 0xFF80204C +#define SYS_AXI_PCIDMSCR 0xFF802050 +#define SYS_AXI_RTXDMSCR 0xFF802054 +#define SYS_AXI_SAT0DMSCR 0xFF802058 +#define SYS_AXI_SAT1DMSCR 0xFF80205C +#define SYS_AXI_SDM0DMSCR 0xFF802060 +#define SYS_AXI_SDM1DMSCR 0xFF802064 +#define SYS_AXI_SDS0DMSCR 0xFF802068 +#define SYS_AXI_SDS1DMSCR 0xFF80206C +#define SYS_AXI_ETRABDMSCR 0xFF802070 +#define SYS_AXI_ETRKFDMSCR 0xFF802074 +#define SYS_AXI_UDM0DMSCR 0xFF802078 +#define SYS_AXI_UDM1DMSCR 0xFF80207C +#define SYS_AXI_USB20DMSCR 0xFF802080 +#define SYS_AXI_USB21DMSCR 0xFF802084 +#define SYS_AXI_USB22DMSCR 0xFF802088 +#define SYS_AXI_USB30DMSCR 0xFF80208C +#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 +#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 +#define SYS_AXI_AVBSLVDMSCR 0xFF802108 +#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C +#define SYS_AXI_ETHSLVDMSCR 0xFF802110 +#define SYS_AXI_GICSLVDMSCR 0xFF802114 +#define SYS_AXI_IMPSLVDMSCR 0xFF802118 +#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C +#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 +#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 +#define SYS_AXI_LBSSLVDMSCR 0xFF802128 +#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C +#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 +#define SYS_AXI_MPXSLVDMSCR 0xFF802134 +#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 +#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C +#define SYS_AXI_MXTSLVDMSCR 0xFF802140 +#define SYS_AXI_PCISLVDMSCR 0xFF802144 +#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 +#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C +#define SYS_AXI_RTXSLVDMSCR 0xFF802150 +#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 +#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C +#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 +#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 +#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 +#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C +#define SYS_AXI_SGXSLVDMSCR 0xFF802180 +#define SYS_AXI_STBSLVDMSCR 0xFF802188 +#define SYS_AXI_STMSLVDMSCR 0xFF80218C +#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 +#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 +#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C +#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 +#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 +#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 +#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC + +#define RT_AXI_CBMDMSCR 0xFF812000 +#define RT_AXI_DBDMSCR 0xFF812004 +#define RT_AXI_RDMDMSCR 0xFF812008 +#define RT_AXI_RDSDMSCR 0xFF81200C +#define RT_AXI_STRDMSCR 0xFF812010 +#define RT_AXI_SY2RTDMSCR 0xFF812014 +#define RT_AXI_CBSSLVDMSCR 0xFF812100 +#define RT_AXI_DBSSLVDMSCR 0xFF812104 +#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 +#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C +#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 +#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 +#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 +#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C +#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 +#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 + +#define MP_AXI_ADSPDMSCR 0xFF822000 +#define MP_AXI_ASDM0DMSCR 0xFF822004 +#define MP_AXI_ASDM1DMSCR 0xFF822008 +#define MP_AXI_ASDS0DMSCR 0xFF82200C +#define MP_AXI_ASDS1DMSCR 0xFF822010 +#define MP_AXI_MLPDMSCR 0xFF822014 +#define MP_AXI_MMUMPDMSCR 0xFF822018 +#define MP_AXI_SPUDMSCR 0xFF82201C +#define MP_AXI_SPUCDMSCR 0xFF822020 +#define MP_AXI_SY2MPDMSCR 0xFF822024 +#define MP_AXI_ADSPSLVDMSCR 0xFF822100 +#define MP_AXI_MLMSLVDMSCR 0xFF822104 +#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 +#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C +#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 +#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 +#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 +#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C +#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 +#define MP_AXI_SPUSLVDMSCR 0xFF822128 +#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C + +#define ADM_AXI_ASDM0DMSCR 0xFF842000 +#define ADM_AXI_ASDM1DMSCR 0xFF842004 +#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 +#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 +#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C + +#define DM_AXI_RDMDMSCR 0xFF852000 +#define DM_AXI_SDM0DMSCR 0xFF852004 +#define DM_AXI_SDM1DMSCR 0xFF852008 +#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 +#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 +#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 +#define DM_AXI_RAP4SLVDMSCR 0xFF85210C +#define DM_AXI_RAP5SLVDMSCR 0xFF852110 +#define DM_AXI_SAP4SLVDMSCR 0xFF852114 +#define DM_AXI_SAP5SLVDMSCR 0xFF852118 +#define DM_AXI_SAP6SLVDMSCR 0xFF85211C +#define DM_AXI_SAP65SLVDMSCR 0xFF852120 +#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 +#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 +#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C +#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 + +#define SYS_AXI256_SYXDMSCR 0xFF862000 +#define SYS_AXI256_MPXDMSCR 0xFF862004 +#define SYS_AXI256_MXIDMSCR 0xFF862008 +#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 +#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 +#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 +#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C +#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 + +#define MXT_SYXDMSCR 0xFF872000 +#define MXT_CMM0SLVDMSCR 0xFF872100 +#define MXT_CMM1SLVDMSCR 0xFF872104 +#define MXT_CMM2SLVDMSCR 0xFF872108 +#define MXT_FDPSLVDMSCR 0xFF87210C +#define MXT_IMRSLVDMSCR 0xFF872110 +#define MXT_VINSLVDMSCR 0xFF872114 +#define MXT_VPC0SLVDMSCR 0xFF872118 +#define MXT_VPC1SLVDMSCR 0xFF87211C +#define MXT_VSP0SLVDMSCR 0xFF872120 +#define MXT_VSP1SLVDMSCR 0xFF872124 +#define MXT_VSPD0SLVDMSCR 0xFF872128 +#define MXT_VSPD1SLVDMSCR 0xFF87212C +#define MXT_MAP1SLVDMSCR 0xFF872130 +#define MXT_MAP2SLVDMSCR 0xFF872134 + +#define CCI_AXI_MMUS0DMSCR 0xFF882000 +#define CCI_AXI_SYX2DMSCR 0xFF882004 +#define CCI_AXI_MMURDMSCR 0xFF882008 +#define CCI_AXI_MMUDSDMSCR 0xFF88200C +#define CCI_AXI_MMUMDMSCR 0xFF882010 +#define CCI_AXI_MXIDMSCR 0xFF882014 +#define CCI_AXI_MMUS1DMSCR 0xFF882018 +#define CCI_AXI_MMUMPDMSCR 0xFF88201C +#define CCI_AXI_DVMDMSCR 0xFF882020 +#define CCI_AXI_CCISLVDMSCR 0xFF882100 + +#define CCI_AXI_IPMMUIDVMCR 0xFF880400 +#define CCI_AXI_IPMMURDVMCR 0xFF880404 +#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 +#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C +#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 +#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 +#define CCI_AXI_AX2ADDRMASK 0xFF88041C + +#define PLL0CR 0xE61500D8 +#define PLL0_STC_MASK 0x7F000000 +#define PLL0_STC_BIT 24 +#define PLLECR 0xE61500D0 +#define PLL0ST 0x100 + +#ifndef __ASSEMBLY__ +#include + +/* RWDT */ +struct rcar_rwdt { + u32 rwtcnt; /* 0x00 */ + u32 rwtcsra; /* 0x04 */ + u16 rwtcsrb; /* 0x08 */ +}; + +/* SWDT */ +struct rcar_swdt { + u32 swtcnt; /* 0x00 */ + u32 swtcsra; /* 0x04 */ + u16 swtcsrb; /* 0x08 */ +}; + +/* LBSC */ +struct rcar_lbsc { + u32 cs0ctrl; + u32 cs1ctrl; + u32 ecs0ctrl; + u32 ecs1ctrl; + u32 ecs2ctrl; + u32 ecs3ctrl; + u32 ecs4ctrl; + u32 ecs5ctrl; + u32 dummy0[4]; /* 0x20 .. 0x2C */ + u32 cswcr0; + u32 cswcr1; + u32 ecswcr0; + u32 ecswcr1; + u32 ecswcr2; + u32 ecswcr3; + u32 ecswcr4; + u32 ecswcr5; + u32 exdmawcr0; + u32 exdmawcr1; + u32 exdmawcr2; + u32 dummy1[9]; /* 0x5C .. 0x7C */ + u32 cspwcr0; + u32 cspwcr1; + u32 ecspwcr0; + u32 ecspwcr1; + u32 ecspwcr2; + u32 ecspwcr3; + u32 ecspwcr4; + u32 ecspwcr5; + u32 exwtsync; + u32 dummy2[3]; /* 0xA4 .. 0xAC */ + u32 cs0bstctl; + u32 cs0btph; + u32 dummy3[2]; /* 0xB8 .. 0xBC */ + u32 cs1gdst; + u32 ecs0gdst; + u32 ecs1gdst; + u32 ecs2gdst; + u32 ecs3gdst; + u32 ecs4gdst; + u32 ecs5gdst; + u32 dummy4[5]; /* 0xDC .. 0xEC */ + u32 exdmaset0; + u32 exdmaset1; + u32 exdmaset2; + u32 dummy5[5]; /* 0xFC .. 0x10C */ + u32 exdmcr0; + u32 exdmcr1; + u32 exdmcr2; + u32 dummy6[5]; /* 0x11C .. 0x12C */ + u32 bcintsr; + u32 bcintcr; + u32 bcintmr; + u32 dummy7; /* 0x13C */ + u32 exbatlv; + u32 exwtsts; + u32 dummy8[14]; /* 0x148 .. 0x17C */ + u32 atacsctrl; + u32 dummy9[15]; /* 0x184 .. 0x1BC */ + u32 exbct; + u32 extct; +}; + +/* DBSC3 */ +struct rcar_dbsc3 { + u32 dummy0[3]; /* 0x00 .. 0x08 */ + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2C */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3C */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4C */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xAC */ + u32 dbbl; + u32 dummy5[3]; /* 0xB4 .. 0xBC */ + u32 dbadj0; + u32 dummy6; /* 0xC4 */ + u32 dbadj2; + u32 dummy7[5]; /* 0xCC .. 0xDC */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dummy8[2]; /* 0xEC .. 0xF0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy9; /* 0xFC */ + u32 dbrnk0; + u32 dummy10[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy11[47]; /* 0x184 ..0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[14]; /* 0x248 .. 0x27C */ + u32 dbpdlck; + u32 dummy13[3]; /* 0x284 .. 0x28C */ + u32 dbpdrga; + u32 dummy14[3]; /* 0x294 .. 0x29C */ + u32 dbpdrgd; + u32 dummy15[24]; /* 0x2A4 .. 0x300 */ + u32 dbbs0cnt1; + u32 dummy16[30]; /* 0x308 .. 0x37C */ + u32 dbwt0cnf0; + u32 dbwt0cnf1; + u32 dbwt0cnf2; + u32 dbwt0cnf3; + u32 dbwt0cnf4; +}; + +/* GPIO */ +struct rcar_gpio { + u32 iointsel; + u32 inoutsel; + u32 outdt; + u32 indt; + u32 intdt; + u32 intclr; + u32 intmsk; + u32 posneg; + u32 edglevel; + u32 filonoff; + u32 intmsks; + u32 mskclrs; + u32 outdtsel; + u32 outdth; + u32 outdtl; + u32 bothedge; +}; + +/* S3C(QoS) */ +struct rcar_s3c { + u32 s3cexcladdmsk; + u32 s3cexclidmsk; + u32 s3cadsplcr; + u32 s3cmaar; + u32 s3carcr11; + u32 s3crorr; + u32 s3cworr; + u32 s3carcr22; + u32 dummy1[2]; /* 0x20 .. 0x24 */ + u32 s3cmctr; + u32 dummy2; /* 0x2C */ + u32 cconf0; + u32 cconf1; + u32 cconf2; + u32 cconf3; +}; + +struct rcar_s3c_qos { + u32 s3cqos0; + u32 s3cqos1; + u32 s3cqos2; + u32 s3cqos3; + u32 s3cqos4; + u32 s3cqos5; + u32 s3cqos6; + u32 s3cqos7; + u32 s3cqos8; +}; + +/* DBSC(QoS) */ +struct rcar_dbsc3_qos { + u32 dblgcnt; + u32 dbtmval0; + u32 dbtmval1; + u32 dbtmval2; + u32 dbtmval3; + u32 dbrqctr; + u32 dbthres0; + u32 dbthres1; + u32 dbthres2; + u32 dummy0; /* 0x24 */ + u32 dblgqon; +}; + +/* MXI(QoS) */ +struct rcar_mxi { + u32 mxsaar0; + u32 mxsaar1; + u32 dummy0[7]; /* 0x08 .. 0x20 */ + u32 mxaxiracr; /* R8a7790 only */ + u32 mxs3cracr; + u32 dummy1[2]; /* 0x2C .. 0x30 */ + u32 mxaxiwacr; /* R8a7790 only */ + u32 mxs3cwacr; + u32 dummy2; /* 0x3C */ + u32 mxrtcr; + u32 mxwtcr; +}; + +struct rcar_mxi_qos { + u32 vspdu0; + u32 vspdu1; + u32 du0; + u32 du1; +}; + +/* AXI(QoS) */ +struct rcar_axi_qos { + u32 qosconf; + u32 qosctset0; + u32 qosctset1; + u32 qosctset2; + u32 qosctset3; + u32 qosreqctr; + u32 qosthres0; + u32 qosthres1; + u32 qosthres2; + u32 qosqon; +}; + +#endif + +#endif /* __ASM_ARCH_RCAR_BASE_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-mstp.h b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h new file mode 100644 index 0000000000..9a564f892c --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h @@ -0,0 +1,109 @@ +/* + * arch/arm/include/asm/arch-rmobile/rcar-mstp.h + * + * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu + * Copyright (C) 2013, 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_RCAR_MSTP_H +#define __ASM_ARCH_RCAR_MSTP_H + +#define mstp_setbits(type, addr, saddr, set) \ + out_##type((saddr), in_##type(addr) | (set)) +#define mstp_clrbits(type, addr, saddr, clear) \ + out_##type((saddr), in_##type(addr) & ~(clear)) +#define mstp_setclrbits(type, addr, set, clear) \ + out_##type((addr), (in_##type(addr) | (set)) & ~(clear)) +#define mstp_setbits_le32(addr, saddr, set) \ + mstp_setbits(le32, addr, saddr, set) +#define mstp_clrbits_le32(addr, saddr, clear) \ + mstp_clrbits(le32, addr, saddr, clear) +#define mstp_setclrbits_le32(addr, set, clear) \ + mstp_setclrbits(le32, addr, set, clear) + +#ifndef CONFIG_SMSTP0_ENA +#define CONFIG_SMSTP0_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP1_ENA +#define CONFIG_SMSTP1_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP2_ENA +#define CONFIG_SMSTP2_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP3_ENA +#define CONFIG_SMSTP3_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP4_ENA +#define CONFIG_SMSTP4_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP5_ENA +#define CONFIG_SMSTP5_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP6_ENA +#define CONFIG_SMSTP6_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP7_ENA +#define CONFIG_SMSTP7_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP8_ENA +#define CONFIG_SMSTP8_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP9_ENA +#define CONFIG_SMSTP9_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP10_ENA +#define CONFIG_SMSTP10_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP11_ENA +#define CONFIG_SMSTP11_ENA 0x00 +#endif + +#ifndef CONFIG_RMSTP0_ENA +#define CONFIG_RMSTP0_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP1_ENA +#define CONFIG_RMSTP1_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP2_ENA +#define CONFIG_RMSTP2_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP3_ENA +#define CONFIG_RMSTP3_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP4_ENA +#define CONFIG_RMSTP4_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP5_ENA +#define CONFIG_RMSTP5_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP6_ENA +#define CONFIG_RMSTP6_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP7_ENA +#define CONFIG_RMSTP7_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP8_ENA +#define CONFIG_RMSTP8_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP9_ENA +#define CONFIG_RMSTP9_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP10_ENA +#define CONFIG_RMSTP10_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP11_ENA +#define CONFIG_RMSTP11_ENA 0x00 +#endif + +struct mstp_ctl { + u32 s_addr; + u32 s_dis; + u32 s_ena; + u32 r_addr; + u32 r_dis; + u32 r_ena; +}; + +#endif /* __ASM_ARCH_RCAR_MSTP_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h index ac175617cd..65ee9eb547 100644 --- a/arch/arm/include/asm/arch-rmobile/rmobile.h +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -6,9 +6,23 @@ #include #elif defined(CONFIG_R8A7740) #include +#elif defined(CONFIG_R8A7790) +#include +#elif defined(CONFIG_R8A7791) +#include +#elif defined(CONFIG_R8A7793) +#include +#elif defined(CONFIG_R8A7794) +#include #else #error "SOC Name not defined" #endif #endif /* CONFIG_RMOBILE */ +#ifndef __ASSEMBLY__ +u32 rmobile_get_cpu_type(void); +u32 rmobile_get_cpu_rev_integer(void); +u32 rmobile_get_cpu_rev_fraction(void); +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h new file mode 100644 index 0000000000..057bf3f8bb --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h @@ -0,0 +1,168 @@ +/* + * drivers/mmc/sh-sdhi.h + * + * SD/MMC driver for Reneas rmobile ARM SoCs + * + * Copyright (C) 2013-2014 Renesas Electronics Corporation + * Copyright (C) 2008-2009 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SH_SDHI_H +#define _SH_SDHI_H + +#define SDHI_CMD (0x0000 >> 1) +#define SDHI_PORTSEL (0x0004 >> 1) +#define SDHI_ARG0 (0x0008 >> 1) +#define SDHI_ARG1 (0x000C >> 1) +#define SDHI_STOP (0x0010 >> 1) +#define SDHI_SECCNT (0x0014 >> 1) +#define SDHI_RSP00 (0x0018 >> 1) +#define SDHI_RSP01 (0x001C >> 1) +#define SDHI_RSP02 (0x0020 >> 1) +#define SDHI_RSP03 (0x0024 >> 1) +#define SDHI_RSP04 (0x0028 >> 1) +#define SDHI_RSP05 (0x002C >> 1) +#define SDHI_RSP06 (0x0030 >> 1) +#define SDHI_RSP07 (0x0034 >> 1) +#define SDHI_INFO1 (0x0038 >> 1) +#define SDHI_INFO2 (0x003C >> 1) +#define SDHI_INFO1_MASK (0x0040 >> 1) +#define SDHI_INFO2_MASK (0x0044 >> 1) +#define SDHI_CLK_CTRL (0x0048 >> 1) +#define SDHI_SIZE (0x004C >> 1) +#define SDHI_OPTION (0x0050 >> 1) +#define SDHI_ERR_STS1 (0x0058 >> 1) +#define SDHI_ERR_STS2 (0x005C >> 1) +#define SDHI_BUF0 (0x0060 >> 1) +#define SDHI_SDIO_MODE (0x0068 >> 1) +#define SDHI_SDIO_INFO1 (0x006C >> 1) +#define SDHI_SDIO_INFO1_MASK (0x0070 >> 1) +#define SDHI_CC_EXT_MODE (0x01B0 >> 1) +#define SDHI_SOFT_RST (0x01C0 >> 1) +#define SDHI_VERSION (0x01C4 >> 1) +#define SDHI_HOST_MODE (0x01C8 >> 1) +#define SDHI_SDIF_MODE (0x01CC >> 1) +#define SDHI_EXT_SWAP (0x01E0 >> 1) +#define SDHI_SD_DMACR (0x0324 >> 1) + +/* SDHI CMD VALUE */ +#define CMD_MASK 0x0000ffff +#define SDHI_APP 0x0040 +#define SDHI_SD_APP_SEND_SCR 0x0073 +#define SDHI_SD_SWITCH 0x1C06 + +/* SDHI_PORTSEL */ +#define USE_1PORT (1 << 8) /* 1 port */ + +/* SDHI_ARG */ +#define ARG0_MASK 0x0000ffff +#define ARG1_MASK 0x0000ffff + +/* SDHI_STOP */ +#define STOP_SEC_ENABLE (1 << 8) + +/* SDHI_INFO1 */ +#define INFO1_RESP_END (1 << 0) +#define INFO1_ACCESS_END (1 << 2) +#define INFO1_CARD_RE (1 << 3) +#define INFO1_CARD_IN (1 << 4) +#define INFO1_ISD0CD (1 << 5) +#define INFO1_WRITE_PRO (1 << 7) +#define INFO1_DATA3_CARD_RE (1 << 8) +#define INFO1_DATA3_CARD_IN (1 << 9) +#define INFO1_DATA3 (1 << 10) + +/* SDHI_INFO2 */ +#define INFO2_CMD_ERROR (1 << 0) +#define INFO2_CRC_ERROR (1 << 1) +#define INFO2_END_ERROR (1 << 2) +#define INFO2_TIMEOUT (1 << 3) +#define INFO2_BUF_ILL_WRITE (1 << 4) +#define INFO2_BUF_ILL_READ (1 << 5) +#define INFO2_RESP_TIMEOUT (1 << 6) +#define INFO2_SDDAT0 (1 << 7) +#define INFO2_BRE_ENABLE (1 << 8) +#define INFO2_BWE_ENABLE (1 << 9) +#define INFO2_CBUSY (1 << 14) +#define INFO2_ILA (1 << 15) +#define INFO2_ALL_ERR (0x807f) + +/* SDHI_INFO1_MASK */ +#define INFO1M_RESP_END (1 << 0) +#define INFO1M_ACCESS_END (1 << 2) +#define INFO1M_CARD_RE (1 << 3) +#define INFO1M_CARD_IN (1 << 4) +#define INFO1M_DATA3_CARD_RE (1 << 8) +#define INFO1M_DATA3_CARD_IN (1 << 9) +#define INFO1M_ALL (0xffff) +#define INFO1M_SET (INFO1M_RESP_END | \ + INFO1M_ACCESS_END | \ + INFO1M_DATA3_CARD_RE | \ + INFO1M_DATA3_CARD_IN) + +/* SDHI_INFO2_MASK */ +#define INFO2M_CMD_ERROR (1 << 0) +#define INFO2M_CRC_ERROR (1 << 1) +#define INFO2M_END_ERROR (1 << 2) +#define INFO2M_TIMEOUT (1 << 3) +#define INFO2M_BUF_ILL_WRITE (1 << 4) +#define INFO2M_BUF_ILL_READ (1 << 5) +#define INFO2M_RESP_TIMEOUT (1 << 6) +#define INFO2M_BRE_ENABLE (1 << 8) +#define INFO2M_BWE_ENABLE (1 << 9) +#define INFO2M_ILA (1 << 15) +#define INFO2M_ALL (0xffff) +#define INFO2M_ALL_ERR (0x807f) + +/* SDHI_CLK_CTRL */ +#define CLK_ENABLE (1 << 8) + +/* SDHI_OPTION */ +#define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */ + +/* SDHI_ERR_STS1 */ +#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \ + (1 << 8) | (1 << 5)) +#define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \ + (1 << 1) | (1 << 0)) + +/* SDHI_ERR_STS2 */ +#define ERR_STS2_RES_TIMEOUT (1 << 0) +#define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1)) +#define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \ + (1 << 3) | (1 << 2) | (1 << 1) | \ + (1 << 0)) + +/* SDHI_SDIO_MODE */ +#define SDIO_MODE_ON (1 << 0) +#define SDIO_MODE_OFF (0 << 0) + +/* SDHI_SDIO_INFO1 */ +#define SDIO_INFO1_IOIRQ (1 << 0) +#define SDIO_INFO1_EXPUB52 (1 << 14) +#define SDIO_INFO1_EXWT (1 << 15) + +/* SDHI_SDIO_INFO1_MASK */ +#define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2)) +#define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \ + (1 << 1) | (1 << 0)) + +/* SDHI_EXT_SWAP */ +#define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */ + +/* SDHI_SOFT_RST */ +#define SOFT_RST_ON (0 << 0) +#define SOFT_RST_OFF (1 << 0) + +#define CLKDEV_SD_DATA 25000000 /* 25 MHz */ +#define CLKDEV_HS_DATA 50000000 /* 50 MHz */ +#define CLKDEV_MMC_DATA 20000000 /* 20MHz */ +#define CLKDEV_INIT 400000 /* 100 - 400 KHz */ + +/* For quirk */ +#define SH_SDHI_QUIRK_16BIT_BUF (1) +int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks); + +#endif /* _SH_SDHI_H */ diff --git a/arch/arm/include/asm/arch-s3c24x0/memory.h b/arch/arm/include/asm/arch-s3c24x0/memory.h index 61d62707c7..d6a787b663 100644 --- a/arch/arm/include/asm/arch-s3c24x0/memory.h +++ b/arch/arm/include/asm/arch-s3c24x0/memory.h @@ -32,9 +32,6 @@ */ #define PHYS_OFFSET (0x0c000000UL) -#include - - /* Modified for S3C2400, by chc, 20010509 */ #define RAM_IN_BANK_0 32*1024*1024 #define RAM_IN_BANK_1 0 diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h index 01fe0f27ef..8773ce30d1 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h @@ -83,9 +83,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; } -static inline struct s3c2410_nand *s3c2410_get_base_nand(void) +static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) { - return (struct s3c2410_nand *)S3C2410_NAND_BASE; + return (struct s3c24x0_nand *)S3C2410_NAND_BASE; } static inline struct s3c24x0_uart @@ -139,9 +139,9 @@ static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; } -static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) +static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void) { - return (struct s3c2410_sdi *)S3C2410_SDI_BASE; + return (struct s3c24x0_sdi *)S3C2410_SDI_BASE; } #endif /*__S3C2410_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h index 15a7cb43d5..7a525f2818 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h @@ -81,9 +81,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; } -static inline struct s3c2440_nand *s3c2440_get_base_nand(void) +static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) { - return (struct s3c2440_nand *)S3C2440_NAND_BASE; + return (struct s3c24x0_nand *)S3C2440_NAND_BASE; } static inline struct s3c24x0_uart @@ -137,9 +137,9 @@ static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; } -static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void) +static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void) { - return (struct s3c2440_sdi *)S3C2440_SDI_BASE; + return (struct s3c24x0_sdi *)S3C2440_SDI_BASE; } #endif /*__S3C2440_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index 86d720c06e..2dae9fc3d7 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -135,34 +135,33 @@ struct s3c24x0_lcd { }; -#ifdef CONFIG_S3C2410 -/* NAND FLASH (see S3C2410 manual chapter 6) */ -struct s3c2410_nand { - u32 nfconf; - u32 nfcmd; - u32 nfaddr; - u32 nfdata; - u32 nfstat; - u32 nfecc; -}; -#endif -#ifdef CONFIG_S3C2440 -/* NAND FLASH (see S3C2440 manual chapter 6) */ -struct s3c2440_nand { +/* NAND FLASH (see manual chapter 6) */ +struct s3c24x0_nand { u32 nfconf; +#ifndef CONFIG_S3C2410 u32 nfcont; +#endif u32 nfcmd; u32 nfaddr; u32 nfdata; +#ifndef CONFIG_S3C2410 u32 nfeccd0; u32 nfeccd1; u32 nfeccd; +#endif u32 nfstat; +#ifdef CONFIG_S3C2410 + u32 nfecc; +#else u32 nfstat0; u32 nfstat1; -}; + u32 nfmecc0; + u32 nfmecc1; + u32 nfsecc; + u32 nfsblk; + u32 nfeblk; #endif - +}; /* UART (see manual chapter 11) */ struct s3c24x0_uart { @@ -675,7 +674,7 @@ struct s3c2400_mmc { /* SD INTERFACE (see S3C2410 manual chapter 19) */ -struct s3c2410_sdi { +struct s3c24x0_sdi { u32 sdicon; u32 sdipre; u32 sdicarg; @@ -691,14 +690,19 @@ struct s3c2410_sdi { u32 sdidcnt; u32 sdidsta; u32 sdifsta; -#ifdef __BIG_ENDIAN - u8 res[3]; - u8 sdidat; +#ifdef CONFIG_S3C2410 + u32 sdidat; + u32 sdiimsk; #else - u8 sdidat; - u8 res[3]; -#endif u32 sdiimsk; + u32 sdidat; +#endif }; +#ifdef CONFIG_CMD_MMC +#include +int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *), + int (*getwp)(struct mmc *)); +#endif + #endif /*__S3C24X0_H__*/ diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h deleted file mode 100644 index 146e265d9a..0000000000 --- a/arch/arm/include/asm/arch-s3c44b0/hardware.h +++ /dev/null @@ -1,281 +0,0 @@ -/********************************************************/ -/* */ -/* Samsung S3C44B0 */ -/* tpu */ -/* */ -/********************************************************/ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#define REGBASE 0x01c00000 -#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) -#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) -#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) - - -/*****************************/ -/* CPU Wrapper Registers */ -/*****************************/ - -#define SYSCFG REGL(0x000000) -#define NCACHBE0 REGL(0x000004) -#define NCACHBE1 REGL(0x000008) -#define SBUSCON REGL(0x040000) - -/************************************/ -/* Memory Controller Registers */ -/************************************/ - -#define BWSCON REGL(0x080000) -#define BANKCON0 REGL(0x080004) -#define BANKCON1 REGL(0x080008) -#define BANKCON2 REGL(0x08000c) -#define BANKCON3 REGL(0x080010) -#define BANKCON4 REGL(0x080014) -#define BANKCON5 REGL(0x080018) -#define BANKCON6 REGL(0x08001c) -#define BANKCON7 REGL(0x080020) -#define REFRESH REGL(0x080024) -#define BANKSIZE REGL(0x080028) -#define MRSRB6 REGL(0x08002c) -#define MRSRB7 REGL(0x080030) - -/*********************/ -/* UART Registers */ -/*********************/ - -#define ULCON0 REGL(0x100000) -#define ULCON1 REGL(0x104000) -#define UCON0 REGL(0x100004) -#define UCON1 REGL(0x104004) -#define UFCON0 REGL(0x100008) -#define UFCON1 REGL(0x104008) -#define UMCON0 REGL(0x10000c) -#define UMCON1 REGL(0x10400c) -#define UTRSTAT0 REGL(0x100010) -#define UTRSTAT1 REGL(0x104010) -#define UERSTAT0 REGL(0x100014) -#define UERSTAT1 REGL(0x104014) -#define UFSTAT0 REGL(0x100018) -#define UFSTAT1 REGL(0x104018) -#define UMSTAT0 REGL(0x10001c) -#define UMSTAT1 REGL(0x10401c) -#define UTXH0 REGB(0x100020) -#define UTXH1 REGB(0x104020) -#define URXH0 REGB(0x100024) -#define URXH1 REGB(0x104024) -#define UBRDIV0 REGL(0x100028) -#define UBRDIV1 REGL(0x104028) - -/*******************/ -/* SIO Registers */ -/*******************/ - -#define SIOCON REGL(0x114000) -#define SIODAT REGL(0x114004) -#define SBRDR REGL(0x114008) -#define ITVCNT REGL(0x11400c) -#define DCNTZ REGL(0x114010) - -/********************/ -/* IIS Registers */ -/********************/ - -#define IISCON REGL(0x118000) -#define IISMOD REGL(0x118004) -#define IISPSR REGL(0x118008) -#define IISFIFCON REGL(0x11800c) -#define IISFIF REGW(0x118010) - -/**************************/ -/* I/O Ports Registers */ -/**************************/ - -#define PCONA REGL(0x120000) -#define PDATA REGL(0x120004) -#define PCONB REGL(0x120008) -#define PDATB REGL(0x12000c) -#define PCONC REGL(0x120010) -#define PDATC REGL(0x120014) -#define PUPC REGL(0x120018) -#define PCOND REGL(0x12001c) -#define PDATD REGL(0x120020) -#define PUPD REGL(0x120024) -#define PCONE REGL(0x120028) -#define PDATE REGL(0x12002c) -#define PUPE REGL(0x120030) -#define PCONF REGL(0x120034) -#define PDATF REGL(0x120038) -#define PUPF REGL(0x12003c) -#define PCONG REGL(0x120040) -#define PDATG REGL(0x120044) -#define PUPG REGL(0x120048) -#define SPUCR REGL(0x12004c) -#define EXTINT REGL(0x120050) -#define EXTINTPND REGL(0x120054) - -/*********************************/ -/* WatchDog Timers Registers */ -/*********************************/ - -#define WTCON REGL(0x130000) -#define WTDAT REGL(0x130004) -#define WTCNT REGL(0x130008) - -/*********************************/ -/* A/D Converter Registers */ -/*********************************/ - -#define ADCCON REGL(0x140000) -#define ADCPSR REGL(0x140004) -#define ADCDAT REGL(0x140008) - -/***************************/ -/* PWM Timer Registers */ -/***************************/ - -#define TCFG0 REGL(0x150000) -#define TCFG1 REGL(0x150004) -#define TCON REGL(0x150008) -#define TCNTB0 REGL(0x15000c) -#define TCMPB0 REGL(0x150010) -#define TCNTO0 REGL(0x150014) -#define TCNTB1 REGL(0x150018) -#define TCMPB1 REGL(0x15001c) -#define TCNTO1 REGL(0x150020) -#define TCNTB2 REGL(0x150024) -#define TCMPB2 REGL(0x150028) -#define TCNTO2 REGL(0x15002c) -#define TCNTB3 REGL(0x150030) -#define TCMPB3 REGL(0x150034) -#define TCNTO3 REGL(0x150038) -#define TCNTB4 REGL(0x15003c) -#define TCMPB4 REGL(0x150040) -#define TCNTO4 REGL(0x150044) -#define TCNTB5 REGL(0x150048) -#define TCNTO5 REGL(0x15004c) - -/*********************/ -/* IIC Registers */ -/*********************/ - -#define IICCON REGL(0x160000) -#define IICSTAT REGL(0x160004) -#define IICADD REGL(0x160008) -#define IICDS REGL(0x16000c) - -/*********************/ -/* RTC Registers */ -/*********************/ - -#define RTCCON REGB(0x170040) -#define RTCALM REGB(0x170050) -#define ALMSEC REGB(0x170054) -#define ALMMIN REGB(0x170058) -#define ALMHOUR REGB(0x17005c) -#define ALMDAY REGB(0x170060) -#define ALMMON REGB(0x170064) -#define ALMYEAR REGB(0x170068) -#define RTCRST REGB(0x17006c) -#define BCDSEC REGB(0x170070) -#define BCDMIN REGB(0x170074) -#define BCDHOUR REGB(0x170078) -#define BCDDAY REGB(0x17007c) -#define BCDDATE REGB(0x170080) -#define BCDMON REGB(0x170084) -#define BCDYEAR REGB(0x170088) -#define TICINT REGB(0x17008c) - -/*********************************/ -/* Clock & Power Registers */ -/*********************************/ - -#define PLLCON REGL(0x180000) -#define CLKCON REGL(0x180004) -#define CLKSLOW REGL(0x180008) -#define LOCKTIME REGL(0x18000c) - -/**************************************/ -/* Interrupt Controller Registers */ -/**************************************/ - -#define INTCON REGL(0x200000) -#define INTPND REGL(0x200004) -#define INTMOD REGL(0x200008) -#define INTMSK REGL(0x20000c) -#define I_PSLV REGL(0x200010) -#define I_PMST REGL(0x200014) -#define I_CSLV REGL(0x200018) -#define I_CMST REGL(0x20001c) -#define I_ISPR REGL(0x200020) -#define I_ISPC REGL(0x200024) -#define F_ISPR REGL(0x200038) -#define F_ISPC REGL(0x20003c) - -/********************************/ -/* LCD Controller Registers */ -/********************************/ - -#define LCDCON1 REGL(0x300000) -#define LCDCON2 REGL(0x300004) -#define LCDSADDR1 REGL(0x300008) -#define LCDSADDR2 REGL(0x30000c) -#define LCDSADDR3 REGL(0x300010) -#define REDLUT REGL(0x300014) -#define GREENLUT REGL(0x300018) -#define BLUELUT REGL(0x30001c) -#define DP1_2 REGL(0x300020) -#define DP4_7 REGL(0x300024) -#define DP3_5 REGL(0x300028) -#define DP2_3 REGL(0x30002c) -#define DP5_7 REGL(0x300030) -#define DP3_4 REGL(0x300034) -#define DP4_5 REGL(0x300038) -#define DP6_7 REGL(0x30003c) -#define LCDCON3 REGL(0x300040) -#define DITHMODE REGL(0x300044) - -/*********************/ -/* DMA Registers */ -/*********************/ - -#define ZDCON0 REGL(0x280000) -#define ZDISRC0 REGL(0x280004) -#define ZDIDES0 REGL(0x280008) -#define ZDICNT0 REGL(0x28000c) -#define ZDCSRC0 REGL(0x280010) -#define ZDCDES0 REGL(0x280014) -#define ZDCCNT0 REGL(0x280018) - -#define ZDCON1 REGL(0x280020) -#define ZDISRC1 REGL(0x280024) -#define ZDIDES1 REGL(0x280028) -#define ZDICNT1 REGL(0x28002c) -#define ZDCSRC1 REGL(0x280030) -#define ZDCDES1 REGL(0x280034) -#define ZDCCNT1 REGL(0x280038) - -#define BDCON0 REGL(0x380000) -#define BDISRC0 REGL(0x380004) -#define BDIDES0 REGL(0x380008) -#define BDICNT0 REGL(0x38000c) -#define BDCSRC0 REGL(0x380010) -#define BDCDES0 REGL(0x380014) -#define BDCCNT0 REGL(0x380018) - -#define BDCON1 REGL(0x380020) -#define BDISRC1 REGL(0x380024) -#define BDIDES1 REGL(0x380028) -#define BDICNT1 REGL(0x38002c) -#define BDCSRC1 REGL(0x380030) -#define BDCDES1 REGL(0x380034) -#define BDCCNT1 REGL(0x380038) - - -#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) -#define INT_ENABLE(n) INTMSK &= ~(1<<(n)) -#define INT_DISABLE(n) INTMSK |= (1<<(n)) - -#define HARD_RESET_NOW() - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index 4fc5a0c3c9..5ae5c87169 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -51,10 +51,17 @@ #include /* CPU detection macros */ extern unsigned int s5p_cpu_id; +extern unsigned int s5p_cpu_rev; + +static inline int s5p_get_cpu_rev(void) +{ + return s5p_cpu_rev; +} static inline void s5p_set_cpu_id(void) { s5p_cpu_id = readl(S5PC100_PRO_ID); + s5p_cpu_rev = s5p_cpu_id & 0x000000FF; s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); } diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index ac60fe6386..2de205e74b 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -19,145 +19,825 @@ struct s5p_gpio_bank { unsigned char res1[8]; }; -struct s5pc100_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c; - struct s5p_gpio_bank d; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank l3; - struct s5p_gpio_bank l4; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum s5pc100_gpio_pin { + S5PC100_GPIO_A00, + S5PC100_GPIO_A01, + S5PC100_GPIO_A02, + S5PC100_GPIO_A03, + S5PC100_GPIO_A04, + S5PC100_GPIO_A05, + S5PC100_GPIO_A06, + S5PC100_GPIO_A07, + S5PC100_GPIO_A10, + S5PC100_GPIO_A11, + S5PC100_GPIO_A12, + S5PC100_GPIO_A13, + S5PC100_GPIO_A14, + S5PC100_GPIO_A15, + S5PC100_GPIO_A16, + S5PC100_GPIO_A17, + S5PC100_GPIO_B0, + S5PC100_GPIO_B1, + S5PC100_GPIO_B2, + S5PC100_GPIO_B3, + S5PC100_GPIO_B4, + S5PC100_GPIO_B5, + S5PC100_GPIO_B6, + S5PC100_GPIO_B7, + S5PC100_GPIO_C0, + S5PC100_GPIO_C1, + S5PC100_GPIO_C2, + S5PC100_GPIO_C3, + S5PC100_GPIO_C4, + S5PC100_GPIO_C5, + S5PC100_GPIO_C6, + S5PC100_GPIO_C7, + S5PC100_GPIO_D0, + S5PC100_GPIO_D1, + S5PC100_GPIO_D2, + S5PC100_GPIO_D3, + S5PC100_GPIO_D4, + S5PC100_GPIO_D5, + S5PC100_GPIO_D6, + S5PC100_GPIO_D7, + S5PC100_GPIO_E00, + S5PC100_GPIO_E01, + S5PC100_GPIO_E02, + S5PC100_GPIO_E03, + S5PC100_GPIO_E04, + S5PC100_GPIO_E05, + S5PC100_GPIO_E06, + S5PC100_GPIO_E07, + S5PC100_GPIO_E10, + S5PC100_GPIO_E11, + S5PC100_GPIO_E12, + S5PC100_GPIO_E13, + S5PC100_GPIO_E14, + S5PC100_GPIO_E15, + S5PC100_GPIO_E16, + S5PC100_GPIO_E17, + S5PC100_GPIO_F00, + S5PC100_GPIO_F01, + S5PC100_GPIO_F02, + S5PC100_GPIO_F03, + S5PC100_GPIO_F04, + S5PC100_GPIO_F05, + S5PC100_GPIO_F06, + S5PC100_GPIO_F07, + S5PC100_GPIO_F10, + S5PC100_GPIO_F11, + S5PC100_GPIO_F12, + S5PC100_GPIO_F13, + S5PC100_GPIO_F14, + S5PC100_GPIO_F15, + S5PC100_GPIO_F16, + S5PC100_GPIO_F17, + S5PC100_GPIO_F20, + S5PC100_GPIO_F21, + S5PC100_GPIO_F22, + S5PC100_GPIO_F23, + S5PC100_GPIO_F24, + S5PC100_GPIO_F25, + S5PC100_GPIO_F26, + S5PC100_GPIO_F27, + S5PC100_GPIO_F30, + S5PC100_GPIO_F31, + S5PC100_GPIO_F32, + S5PC100_GPIO_F33, + S5PC100_GPIO_F34, + S5PC100_GPIO_F35, + S5PC100_GPIO_F36, + S5PC100_GPIO_F37, + S5PC100_GPIO_G00, + S5PC100_GPIO_G01, + S5PC100_GPIO_G02, + S5PC100_GPIO_G03, + S5PC100_GPIO_G04, + S5PC100_GPIO_G05, + S5PC100_GPIO_G06, + S5PC100_GPIO_G07, + S5PC100_GPIO_G10, + S5PC100_GPIO_G11, + S5PC100_GPIO_G12, + S5PC100_GPIO_G13, + S5PC100_GPIO_G14, + S5PC100_GPIO_G15, + S5PC100_GPIO_G16, + S5PC100_GPIO_G17, + S5PC100_GPIO_G20, + S5PC100_GPIO_G21, + S5PC100_GPIO_G22, + S5PC100_GPIO_G23, + S5PC100_GPIO_G24, + S5PC100_GPIO_G25, + S5PC100_GPIO_G26, + S5PC100_GPIO_G27, + S5PC100_GPIO_G30, + S5PC100_GPIO_G31, + S5PC100_GPIO_G32, + S5PC100_GPIO_G33, + S5PC100_GPIO_G34, + S5PC100_GPIO_G35, + S5PC100_GPIO_G36, + S5PC100_GPIO_G37, + S5PC100_GPIO_I0, + S5PC100_GPIO_I1, + S5PC100_GPIO_I2, + S5PC100_GPIO_I3, + S5PC100_GPIO_I4, + S5PC100_GPIO_I5, + S5PC100_GPIO_I6, + S5PC100_GPIO_I7, + S5PC100_GPIO_J00, + S5PC100_GPIO_J01, + S5PC100_GPIO_J02, + S5PC100_GPIO_J03, + S5PC100_GPIO_J04, + S5PC100_GPIO_J05, + S5PC100_GPIO_J06, + S5PC100_GPIO_J07, + S5PC100_GPIO_J10, + S5PC100_GPIO_J11, + S5PC100_GPIO_J12, + S5PC100_GPIO_J13, + S5PC100_GPIO_J14, + S5PC100_GPIO_J15, + S5PC100_GPIO_J16, + S5PC100_GPIO_J17, + S5PC100_GPIO_J20, + S5PC100_GPIO_J21, + S5PC100_GPIO_J22, + S5PC100_GPIO_J23, + S5PC100_GPIO_J24, + S5PC100_GPIO_J25, + S5PC100_GPIO_J26, + S5PC100_GPIO_J27, + S5PC100_GPIO_J30, + S5PC100_GPIO_J31, + S5PC100_GPIO_J32, + S5PC100_GPIO_J33, + S5PC100_GPIO_J34, + S5PC100_GPIO_J35, + S5PC100_GPIO_J36, + S5PC100_GPIO_J37, + S5PC100_GPIO_J40, + S5PC100_GPIO_J41, + S5PC100_GPIO_J42, + S5PC100_GPIO_J43, + S5PC100_GPIO_J44, + S5PC100_GPIO_J45, + S5PC100_GPIO_J46, + S5PC100_GPIO_J47, + S5PC100_GPIO_K00, + S5PC100_GPIO_K01, + S5PC100_GPIO_K02, + S5PC100_GPIO_K03, + S5PC100_GPIO_K04, + S5PC100_GPIO_K05, + S5PC100_GPIO_K06, + S5PC100_GPIO_K07, + S5PC100_GPIO_K10, + S5PC100_GPIO_K11, + S5PC100_GPIO_K12, + S5PC100_GPIO_K13, + S5PC100_GPIO_K14, + S5PC100_GPIO_K15, + S5PC100_GPIO_K16, + S5PC100_GPIO_K17, + S5PC100_GPIO_K20, + S5PC100_GPIO_K21, + S5PC100_GPIO_K22, + S5PC100_GPIO_K23, + S5PC100_GPIO_K24, + S5PC100_GPIO_K25, + S5PC100_GPIO_K26, + S5PC100_GPIO_K27, + S5PC100_GPIO_K30, + S5PC100_GPIO_K31, + S5PC100_GPIO_K32, + S5PC100_GPIO_K33, + S5PC100_GPIO_K34, + S5PC100_GPIO_K35, + S5PC100_GPIO_K36, + S5PC100_GPIO_K37, + S5PC100_GPIO_L00, + S5PC100_GPIO_L01, + S5PC100_GPIO_L02, + S5PC100_GPIO_L03, + S5PC100_GPIO_L04, + S5PC100_GPIO_L05, + S5PC100_GPIO_L06, + S5PC100_GPIO_L07, + S5PC100_GPIO_L10, + S5PC100_GPIO_L11, + S5PC100_GPIO_L12, + S5PC100_GPIO_L13, + S5PC100_GPIO_L14, + S5PC100_GPIO_L15, + S5PC100_GPIO_L16, + S5PC100_GPIO_L17, + S5PC100_GPIO_L20, + S5PC100_GPIO_L21, + S5PC100_GPIO_L22, + S5PC100_GPIO_L23, + S5PC100_GPIO_L24, + S5PC100_GPIO_L25, + S5PC100_GPIO_L26, + S5PC100_GPIO_L27, + S5PC100_GPIO_L30, + S5PC100_GPIO_L31, + S5PC100_GPIO_L32, + S5PC100_GPIO_L33, + S5PC100_GPIO_L34, + S5PC100_GPIO_L35, + S5PC100_GPIO_L36, + S5PC100_GPIO_L37, + S5PC100_GPIO_L40, + S5PC100_GPIO_L41, + S5PC100_GPIO_L42, + S5PC100_GPIO_L43, + S5PC100_GPIO_L44, + S5PC100_GPIO_L45, + S5PC100_GPIO_L46, + S5PC100_GPIO_L47, + S5PC100_GPIO_H00, + S5PC100_GPIO_H01, + S5PC100_GPIO_H02, + S5PC100_GPIO_H03, + S5PC100_GPIO_H04, + S5PC100_GPIO_H05, + S5PC100_GPIO_H06, + S5PC100_GPIO_H07, + S5PC100_GPIO_H10, + S5PC100_GPIO_H11, + S5PC100_GPIO_H12, + S5PC100_GPIO_H13, + S5PC100_GPIO_H14, + S5PC100_GPIO_H15, + S5PC100_GPIO_H16, + S5PC100_GPIO_H17, + S5PC100_GPIO_H20, + S5PC100_GPIO_H21, + S5PC100_GPIO_H22, + S5PC100_GPIO_H23, + S5PC100_GPIO_H24, + S5PC100_GPIO_H25, + S5PC100_GPIO_H26, + S5PC100_GPIO_H27, + S5PC100_GPIO_H30, + S5PC100_GPIO_H31, + S5PC100_GPIO_H32, + S5PC100_GPIO_H33, + S5PC100_GPIO_H34, + S5PC100_GPIO_H35, + S5PC100_GPIO_H36, + S5PC100_GPIO_H37, + + S5PC100_GPIO_MAX_PORT }; -struct s5pc110_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank mp0_1; - struct s5p_gpio_bank mp0_2; - struct s5p_gpio_bank mp0_3; - struct s5p_gpio_bank mp0_4; - struct s5p_gpio_bank mp0_5; - struct s5p_gpio_bank mp0_6; - struct s5p_gpio_bank mp0_7; - struct s5p_gpio_bank mp1_0; - struct s5p_gpio_bank mp1_1; - struct s5p_gpio_bank mp1_2; - struct s5p_gpio_bank mp1_3; - struct s5p_gpio_bank mp1_4; - struct s5p_gpio_bank mp1_5; - struct s5p_gpio_bank mp1_6; - struct s5p_gpio_bank mp1_7; - struct s5p_gpio_bank mp1_8; - struct s5p_gpio_bank mp2_0; - struct s5p_gpio_bank mp2_1; - struct s5p_gpio_bank mp2_2; - struct s5p_gpio_bank mp2_3; - struct s5p_gpio_bank mp2_4; - struct s5p_gpio_bank mp2_5; - struct s5p_gpio_bank mp2_6; - struct s5p_gpio_bank mp2_7; - struct s5p_gpio_bank mp2_8; - struct s5p_gpio_bank res1[48]; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; +enum s5pc110_gpio_pin { + S5PC110_GPIO_A00, + S5PC110_GPIO_A01, + S5PC110_GPIO_A02, + S5PC110_GPIO_A03, + S5PC110_GPIO_A04, + S5PC110_GPIO_A05, + S5PC110_GPIO_A06, + S5PC110_GPIO_A07, + S5PC110_GPIO_A10, + S5PC110_GPIO_A11, + S5PC110_GPIO_A12, + S5PC110_GPIO_A13, + S5PC110_GPIO_A14, + S5PC110_GPIO_A15, + S5PC110_GPIO_A16, + S5PC110_GPIO_A17, + S5PC110_GPIO_B0, + S5PC110_GPIO_B1, + S5PC110_GPIO_B2, + S5PC110_GPIO_B3, + S5PC110_GPIO_B4, + S5PC110_GPIO_B5, + S5PC110_GPIO_B6, + S5PC110_GPIO_B7, + S5PC110_GPIO_C00, + S5PC110_GPIO_C01, + S5PC110_GPIO_C02, + S5PC110_GPIO_C03, + S5PC110_GPIO_C04, + S5PC110_GPIO_C05, + S5PC110_GPIO_C06, + S5PC110_GPIO_C07, + S5PC110_GPIO_C10, + S5PC110_GPIO_C11, + S5PC110_GPIO_C12, + S5PC110_GPIO_C13, + S5PC110_GPIO_C14, + S5PC110_GPIO_C15, + S5PC110_GPIO_C16, + S5PC110_GPIO_C17, + S5PC110_GPIO_D00, + S5PC110_GPIO_D01, + S5PC110_GPIO_D02, + S5PC110_GPIO_D03, + S5PC110_GPIO_D04, + S5PC110_GPIO_D05, + S5PC110_GPIO_D06, + S5PC110_GPIO_D07, + S5PC110_GPIO_D10, + S5PC110_GPIO_D11, + S5PC110_GPIO_D12, + S5PC110_GPIO_D13, + S5PC110_GPIO_D14, + S5PC110_GPIO_D15, + S5PC110_GPIO_D16, + S5PC110_GPIO_D17, + S5PC110_GPIO_E00, + S5PC110_GPIO_E01, + S5PC110_GPIO_E02, + S5PC110_GPIO_E03, + S5PC110_GPIO_E04, + S5PC110_GPIO_E05, + S5PC110_GPIO_E06, + S5PC110_GPIO_E07, + S5PC110_GPIO_E10, + S5PC110_GPIO_E11, + S5PC110_GPIO_E12, + S5PC110_GPIO_E13, + S5PC110_GPIO_E14, + S5PC110_GPIO_E15, + S5PC110_GPIO_E16, + S5PC110_GPIO_E17, + S5PC110_GPIO_F00, + S5PC110_GPIO_F01, + S5PC110_GPIO_F02, + S5PC110_GPIO_F03, + S5PC110_GPIO_F04, + S5PC110_GPIO_F05, + S5PC110_GPIO_F06, + S5PC110_GPIO_F07, + S5PC110_GPIO_F10, + S5PC110_GPIO_F11, + S5PC110_GPIO_F12, + S5PC110_GPIO_F13, + S5PC110_GPIO_F14, + S5PC110_GPIO_F15, + S5PC110_GPIO_F16, + S5PC110_GPIO_F17, + S5PC110_GPIO_F20, + S5PC110_GPIO_F21, + S5PC110_GPIO_F22, + S5PC110_GPIO_F23, + S5PC110_GPIO_F24, + S5PC110_GPIO_F25, + S5PC110_GPIO_F26, + S5PC110_GPIO_F27, + S5PC110_GPIO_F30, + S5PC110_GPIO_F31, + S5PC110_GPIO_F32, + S5PC110_GPIO_F33, + S5PC110_GPIO_F34, + S5PC110_GPIO_F35, + S5PC110_GPIO_F36, + S5PC110_GPIO_F37, + S5PC110_GPIO_G00, + S5PC110_GPIO_G01, + S5PC110_GPIO_G02, + S5PC110_GPIO_G03, + S5PC110_GPIO_G04, + S5PC110_GPIO_G05, + S5PC110_GPIO_G06, + S5PC110_GPIO_G07, + S5PC110_GPIO_G10, + S5PC110_GPIO_G11, + S5PC110_GPIO_G12, + S5PC110_GPIO_G13, + S5PC110_GPIO_G14, + S5PC110_GPIO_G15, + S5PC110_GPIO_G16, + S5PC110_GPIO_G17, + S5PC110_GPIO_G20, + S5PC110_GPIO_G21, + S5PC110_GPIO_G22, + S5PC110_GPIO_G23, + S5PC110_GPIO_G24, + S5PC110_GPIO_G25, + S5PC110_GPIO_G26, + S5PC110_GPIO_G27, + S5PC110_GPIO_G30, + S5PC110_GPIO_G31, + S5PC110_GPIO_G32, + S5PC110_GPIO_G33, + S5PC110_GPIO_G34, + S5PC110_GPIO_G35, + S5PC110_GPIO_G36, + S5PC110_GPIO_G37, + S5PC110_GPIO_I0, + S5PC110_GPIO_I1, + S5PC110_GPIO_I2, + S5PC110_GPIO_I3, + S5PC110_GPIO_I4, + S5PC110_GPIO_I5, + S5PC110_GPIO_I6, + S5PC110_GPIO_I7, + S5PC110_GPIO_J00, + S5PC110_GPIO_J01, + S5PC110_GPIO_J02, + S5PC110_GPIO_J03, + S5PC110_GPIO_J04, + S5PC110_GPIO_J05, + S5PC110_GPIO_J06, + S5PC110_GPIO_J07, + S5PC110_GPIO_J10, + S5PC110_GPIO_J11, + S5PC110_GPIO_J12, + S5PC110_GPIO_J13, + S5PC110_GPIO_J14, + S5PC110_GPIO_J15, + S5PC110_GPIO_J16, + S5PC110_GPIO_J17, + S5PC110_GPIO_J20, + S5PC110_GPIO_J21, + S5PC110_GPIO_J22, + S5PC110_GPIO_J23, + S5PC110_GPIO_J24, + S5PC110_GPIO_J25, + S5PC110_GPIO_J26, + S5PC110_GPIO_J27, + S5PC110_GPIO_J30, + S5PC110_GPIO_J31, + S5PC110_GPIO_J32, + S5PC110_GPIO_J33, + S5PC110_GPIO_J34, + S5PC110_GPIO_J35, + S5PC110_GPIO_J36, + S5PC110_GPIO_J37, + S5PC110_GPIO_J40, + S5PC110_GPIO_J41, + S5PC110_GPIO_J42, + S5PC110_GPIO_J43, + S5PC110_GPIO_J44, + S5PC110_GPIO_J45, + S5PC110_GPIO_J46, + S5PC110_GPIO_J47, + S5PC110_GPIO_MP010, + S5PC110_GPIO_MP011, + S5PC110_GPIO_MP012, + S5PC110_GPIO_MP013, + S5PC110_GPIO_MP014, + S5PC110_GPIO_MP015, + S5PC110_GPIO_MP016, + S5PC110_GPIO_MP017, + S5PC110_GPIO_MP020, + S5PC110_GPIO_MP021, + S5PC110_GPIO_MP022, + S5PC110_GPIO_MP023, + S5PC110_GPIO_MP024, + S5PC110_GPIO_MP025, + S5PC110_GPIO_MP026, + S5PC110_GPIO_MP027, + S5PC110_GPIO_MP030, + S5PC110_GPIO_MP031, + S5PC110_GPIO_MP032, + S5PC110_GPIO_MP033, + S5PC110_GPIO_MP034, + S5PC110_GPIO_MP035, + S5PC110_GPIO_MP036, + S5PC110_GPIO_MP037, + S5PC110_GPIO_MP040, + S5PC110_GPIO_MP041, + S5PC110_GPIO_MP042, + S5PC110_GPIO_MP043, + S5PC110_GPIO_MP044, + S5PC110_GPIO_MP045, + S5PC110_GPIO_MP046, + S5PC110_GPIO_MP047, + S5PC110_GPIO_MP050, + S5PC110_GPIO_MP051, + S5PC110_GPIO_MP052, + S5PC110_GPIO_MP053, + S5PC110_GPIO_MP054, + S5PC110_GPIO_MP055, + S5PC110_GPIO_MP056, + S5PC110_GPIO_MP057, + S5PC110_GPIO_MP060, + S5PC110_GPIO_MP061, + S5PC110_GPIO_MP062, + S5PC110_GPIO_MP063, + S5PC110_GPIO_MP064, + S5PC110_GPIO_MP065, + S5PC110_GPIO_MP066, + S5PC110_GPIO_MP067, + S5PC110_GPIO_MP070, + S5PC110_GPIO_MP071, + S5PC110_GPIO_MP072, + S5PC110_GPIO_MP073, + S5PC110_GPIO_MP074, + S5PC110_GPIO_MP075, + S5PC110_GPIO_MP076, + S5PC110_GPIO_MP077, + S5PC110_GPIO_MP100, + S5PC110_GPIO_MP101, + S5PC110_GPIO_MP102, + S5PC110_GPIO_MP103, + S5PC110_GPIO_MP104, + S5PC110_GPIO_MP105, + S5PC110_GPIO_MP106, + S5PC110_GPIO_MP107, + S5PC110_GPIO_MP110, + S5PC110_GPIO_MP111, + S5PC110_GPIO_MP112, + S5PC110_GPIO_MP113, + S5PC110_GPIO_MP114, + S5PC110_GPIO_MP115, + S5PC110_GPIO_MP116, + S5PC110_GPIO_MP117, + S5PC110_GPIO_MP120, + S5PC110_GPIO_MP121, + S5PC110_GPIO_MP122, + S5PC110_GPIO_MP123, + S5PC110_GPIO_MP124, + S5PC110_GPIO_MP125, + S5PC110_GPIO_MP126, + S5PC110_GPIO_MP127, + S5PC110_GPIO_MP130, + S5PC110_GPIO_MP131, + S5PC110_GPIO_MP132, + S5PC110_GPIO_MP133, + S5PC110_GPIO_MP134, + S5PC110_GPIO_MP135, + S5PC110_GPIO_MP136, + S5PC110_GPIO_MP137, + S5PC110_GPIO_MP140, + S5PC110_GPIO_MP141, + S5PC110_GPIO_MP142, + S5PC110_GPIO_MP143, + S5PC110_GPIO_MP144, + S5PC110_GPIO_MP145, + S5PC110_GPIO_MP146, + S5PC110_GPIO_MP147, + S5PC110_GPIO_MP150, + S5PC110_GPIO_MP151, + S5PC110_GPIO_MP152, + S5PC110_GPIO_MP153, + S5PC110_GPIO_MP154, + S5PC110_GPIO_MP155, + S5PC110_GPIO_MP156, + S5PC110_GPIO_MP157, + S5PC110_GPIO_MP160, + S5PC110_GPIO_MP161, + S5PC110_GPIO_MP162, + S5PC110_GPIO_MP163, + S5PC110_GPIO_MP164, + S5PC110_GPIO_MP165, + S5PC110_GPIO_MP166, + S5PC110_GPIO_MP167, + S5PC110_GPIO_MP170, + S5PC110_GPIO_MP171, + S5PC110_GPIO_MP172, + S5PC110_GPIO_MP173, + S5PC110_GPIO_MP174, + S5PC110_GPIO_MP175, + S5PC110_GPIO_MP176, + S5PC110_GPIO_MP177, + S5PC110_GPIO_MP180, + S5PC110_GPIO_MP181, + S5PC110_GPIO_MP182, + S5PC110_GPIO_MP183, + S5PC110_GPIO_MP184, + S5PC110_GPIO_MP185, + S5PC110_GPIO_MP186, + S5PC110_GPIO_MP187, + S5PC110_GPIO_MP200, + S5PC110_GPIO_MP201, + S5PC110_GPIO_MP202, + S5PC110_GPIO_MP203, + S5PC110_GPIO_MP204, + S5PC110_GPIO_MP205, + S5PC110_GPIO_MP206, + S5PC110_GPIO_MP207, + S5PC110_GPIO_MP210, + S5PC110_GPIO_MP211, + S5PC110_GPIO_MP212, + S5PC110_GPIO_MP213, + S5PC110_GPIO_MP214, + S5PC110_GPIO_MP215, + S5PC110_GPIO_MP216, + S5PC110_GPIO_MP217, + S5PC110_GPIO_MP220, + S5PC110_GPIO_MP221, + S5PC110_GPIO_MP222, + S5PC110_GPIO_MP223, + S5PC110_GPIO_MP224, + S5PC110_GPIO_MP225, + S5PC110_GPIO_MP226, + S5PC110_GPIO_MP227, + S5PC110_GPIO_MP230, + S5PC110_GPIO_MP231, + S5PC110_GPIO_MP232, + S5PC110_GPIO_MP233, + S5PC110_GPIO_MP234, + S5PC110_GPIO_MP235, + S5PC110_GPIO_MP236, + S5PC110_GPIO_MP237, + S5PC110_GPIO_MP240, + S5PC110_GPIO_MP241, + S5PC110_GPIO_MP242, + S5PC110_GPIO_MP243, + S5PC110_GPIO_MP244, + S5PC110_GPIO_MP245, + S5PC110_GPIO_MP246, + S5PC110_GPIO_MP247, + S5PC110_GPIO_MP250, + S5PC110_GPIO_MP251, + S5PC110_GPIO_MP252, + S5PC110_GPIO_MP253, + S5PC110_GPIO_MP254, + S5PC110_GPIO_MP255, + S5PC110_GPIO_MP256, + S5PC110_GPIO_MP257, + S5PC110_GPIO_MP260, + S5PC110_GPIO_MP261, + S5PC110_GPIO_MP262, + S5PC110_GPIO_MP263, + S5PC110_GPIO_MP264, + S5PC110_GPIO_MP265, + S5PC110_GPIO_MP266, + S5PC110_GPIO_MP267, + S5PC110_GPIO_MP270, + S5PC110_GPIO_MP271, + S5PC110_GPIO_MP272, + S5PC110_GPIO_MP273, + S5PC110_GPIO_MP274, + S5PC110_GPIO_MP275, + S5PC110_GPIO_MP276, + S5PC110_GPIO_MP277, + S5PC110_GPIO_MP280, + S5PC110_GPIO_MP281, + S5PC110_GPIO_MP282, + S5PC110_GPIO_MP283, + S5PC110_GPIO_MP284, + S5PC110_GPIO_MP285, + S5PC110_GPIO_MP286, + S5PC110_GPIO_MP287, + S5PC110_GPIO_H00, + S5PC110_GPIO_H01, + S5PC110_GPIO_H02, + S5PC110_GPIO_H03, + S5PC110_GPIO_H04, + S5PC110_GPIO_H05, + S5PC110_GPIO_H06, + S5PC110_GPIO_H07, + S5PC110_GPIO_H10, + S5PC110_GPIO_H11, + S5PC110_GPIO_H12, + S5PC110_GPIO_H13, + S5PC110_GPIO_H14, + S5PC110_GPIO_H15, + S5PC110_GPIO_H16, + S5PC110_GPIO_H17, + S5PC110_GPIO_H20, + S5PC110_GPIO_H21, + S5PC110_GPIO_H22, + S5PC110_GPIO_H23, + S5PC110_GPIO_H24, + S5PC110_GPIO_H25, + S5PC110_GPIO_H26, + S5PC110_GPIO_H27, + S5PC110_GPIO_H30, + S5PC110_GPIO_H31, + S5PC110_GPIO_H32, + S5PC110_GPIO_H33, + S5PC110_GPIO_H34, + S5PC110_GPIO_H35, + S5PC110_GPIO_H36, + S5PC110_GPIO_H37, + + S5PC110_GPIO_MAX_PORT }; -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ +}; -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 +#define S5PC100_GPIO_NUM_PARTS 1 +static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = { + { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT }, +}; -static inline unsigned int s5p_gpio_base(int nr) +#define S5PC110_GPIO_NUM_PARTS 1 +static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = { + { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT }, +}; + +static inline struct gpio_info *get_gpio_data(void) { - return S5PC110_GPIO_BASE; + if (cpu_is_s5pc100()) + return s5pc100_gpio_data; + else if (cpu_is_s5pc110()) + return s5pc110_gpio_data; + + return NULL; } -static inline unsigned int s5p_gpio_part_max(int nr) +static inline unsigned int get_bank_num(void) { + if (cpu_is_s5pc100()) + return S5PC100_GPIO_NUM_PARTS; + else if (cpu_is_s5pc110()) + return S5PC110_GPIO_NUM_PARTS; + return 0; } -#define s5pc110_gpio_get_nr(bank, pin) \ - ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\ - - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) +/* + * This structure helps mapping symbolic GPIO names into indices from + * exynos5_gpio_pin/exynos5420_gpio_pin enums. + * + * By convention, symbolic GPIO name is defined as follows: + * + * g[p], where + * p is optional + * - a single character bank name, as defined by the SOC + * - a single digit set number + * - bit number within the set (in 0..7 range). + * + * essentially form an octal number of the GPIO pin within the bank + * space. On the 5420 architecture some banks' sets do not start not from zero + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and + * maintain flat number space withoout holes, those banks use offsets to be + * deducted from the pin number. + */ +struct gpio_name_num_table { + char bank; /* bank name symbol */ + u8 bank_size; /* total number of pins in the bank */ + char bank_offset; /* offset of the first bank's pin */ + unsigned int base; /* index of the first bank's pin in the enum */ +}; + +#define GPIO_PER_BANK 8 +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } +static const struct gpio_name_num_table s5pc100_gpio_table[] = { + GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0), + GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0), + GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0), + GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0), + GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0), + GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0), + GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0), + GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0), + GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0), + GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0), + GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0), + GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0), + { 0 } +}; + +static const struct gpio_name_num_table s5pc110_gpio_table[] = { + GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0), + GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0), + GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0), + GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0), + GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0), + GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0), + GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0), + GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0), + GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0), + GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0), + { 0 } +}; + +/* functions */ +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); +void gpio_set_rate(int gpio, int mode); +int s5p_gpio_get_pin(unsigned gpio); + +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x2 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index 96610b88f4..dd473c8ecd 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -8,6 +8,8 @@ #ifndef __ASM_ARCH_MMC_H_ #define __ASM_ARCH_MMC_H_ +#define S5P_MMC_DEV_OFFSET 0x100000 + #define SDHCI_CONTROL2 0x80 #define SDHCI_CONTROL3 0x84 #define SDHCI_CONTROL4 0x8C @@ -53,9 +55,11 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width); -static inline unsigned int s5p_mmc_init(int index, int bus_width) +static inline int s5p_mmc_init(int index, int bus_width) { - unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + unsigned int base = samsung_get_base_mmc() + + (S5P_MMC_DEV_OFFSET * index); + return s5p_sdhci_init(base, index, bus_width); } #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/include/asm/arch-s5pc1xx/periph.h new file mode 100644 index 0000000000..5c1c3d4a93 --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/periph.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + PERIPH_ID_UART0 = 51, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_I2C0 = 56, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0 = 68, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0 = 75, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2C8 = 87, + PERIPH_ID_I2C9, + PERIPH_ID_I2S0 = 98, + PERIPH_ID_I2S1 = 99, + + /* Since following peripherals do + * not have shared peripheral interrupts (SPIs) + * they are numbered arbitiraly after the maximum + * SPIs Exynos has (128) + */ + PERIPH_ID_SROMC = 128, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_SDMMC4, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_I2C10 = 203, + + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h new file mode 100644 index 0000000000..0b91ef658c --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +/** + * Decode the peripheral id using the interrpt numbers. + * + * @param blob Device tree blob + * @param node FDT I2C node to find + * @return peripheral id if ok, PERIPH_ID_NONE on error + */ +int pinmux_decode_periph_id(const void *blob, int node); +#endif diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h new file mode 100644 index 0000000000..5449726180 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLOCK_MANAGER_H_ +#define _CLOCK_MANAGER_H_ + +#ifndef __ASSEMBLER__ +/* Clock speed accessors */ +unsigned long cm_get_mpu_clk_hz(void); +unsigned long cm_get_sdram_clk_hz(void); +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +#endif + +typedef struct { + /* main group */ + uint32_t main_vco_base; + uint32_t mpuclk; + uint32_t mainclk; + uint32_t dbgatclk; + uint32_t mainqspiclk; + uint32_t mainnandsdmmcclk; + uint32_t cfg2fuser0clk; + uint32_t maindiv; + uint32_t dbgdiv; + uint32_t tracediv; + uint32_t l4src; + + /* peripheral group */ + uint32_t peri_vco_base; + uint32_t emac0clk; + uint32_t emac1clk; + uint32_t perqspiclk; + uint32_t pernandsdmmcclk; + uint32_t perbaseclk; + uint32_t s2fuser1clk; + uint32_t perdiv; + uint32_t gpiodiv; + uint32_t persrc; + + /* sdram pll group */ + uint32_t sdram_vco_base; + uint32_t ddrdqsclk; + uint32_t ddr2xdqsclk; + uint32_t ddrdqclk; + uint32_t s2fuser2clk; +} cm_config_t; + +extern void cm_basic_init(const cm_config_t *cfg); + +struct socfpga_clock_manager_main_pll { + u32 vco; + u32 misc; + u32 mpuclk; + u32 mainclk; + u32 dbgatclk; + u32 mainqspiclk; + u32 mainnandsdmmcclk; + u32 cfgs2fuser0clk; + u32 en; + u32 maindiv; + u32 dbgdiv; + u32 tracediv; + u32 l4src; + u32 stat; + u32 _pad_0x38_0x40[2]; +}; + +struct socfpga_clock_manager_per_pll { + u32 vco; + u32 misc; + u32 emac0clk; + u32 emac1clk; + u32 perqspiclk; + u32 pernandsdmmcclk; + u32 perbaseclk; + u32 s2fuser1clk; + u32 en; + u32 div; + u32 gpiodiv; + u32 src; + u32 stat; + u32 _pad_0x34_0x40[3]; +}; + +struct socfpga_clock_manager_sdr_pll { + u32 vco; + u32 ctrl; + u32 ddrdqsclk; + u32 ddr2xdqsclk; + u32 ddrdqclk; + u32 s2fuser2clk; + u32 en; + u32 stat; +}; + +struct socfpga_clock_manager_altera { + u32 mpuclk; + u32 mainclk; +}; + +struct socfpga_clock_manager { + u32 ctrl; + u32 bypass; + u32 inter; + u32 intren; + u32 dbctrl; + u32 stat; + u32 _pad_0x18_0x3f[10]; + struct socfpga_clock_manager_main_pll main_pll; + struct socfpga_clock_manager_per_pll per_pll; + struct socfpga_clock_manager_sdr_pll sdr_pll; + struct socfpga_clock_manager_altera altera; + u32 _pad_0xe8_0x200[70]; +}; + +#define CLKMGR_CTRL_SAFEMODE (1 << 0) +#define CLKMGR_CTRL_SAFEMODE_OFFSET 0 + +#define CLKMGR_BYPASS_PERPLLSRC (1 << 4) +#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 +#define CLKMGR_BYPASS_PERPLL (1 << 3) +#define CLKMGR_BYPASS_PERPLL_OFFSET 3 +#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) +#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 +#define CLKMGR_BYPASS_SDRPLL (1 << 1) +#define CLKMGR_BYPASS_SDRPLL_OFFSET 1 +#define CLKMGR_BYPASS_MAINPLL (1 << 0) +#define CLKMGR_BYPASS_MAINPLL_OFFSET 0 + +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 +#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 + +#define CLKMGR_STAT_BUSY (1 << 0) + +/* Main PLL */ +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) +#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d + +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 +#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 +#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 + +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 + +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c + +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 + +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 +#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 + +/* Per PLL */ +#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_VCO_SSRC_EOSC1 0x0 +#define CLKMGR_VCO_SSRC_EOSC2 0x1 +#define CLKMGR_VCO_SSRC_F2S 0x2 + +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 + +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 + +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff + +#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 +#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c +#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 +#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 +#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 +#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 +#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 +#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 +#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 +#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 +#define CLKMGR_QSPI_CLK_SRC_PER 0x2 + +/* SDR PLL */ +#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 + +#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h b/arch/arm/include/asm/arch-socfpga/dwmmc.h new file mode 100644 index 0000000000..945eb646ce --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/dwmmc.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_DWMMC_H_ +#define _SOCFPGA_DWMMC_H_ + +extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); + +#endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/fpga_manager.h b/arch/arm/include/asm/arch-socfpga/fpga_manager.h new file mode 100644 index 0000000000..a077e2284e --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/fpga_manager.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FPGA_MANAGER_H_ +#define _FPGA_MANAGER_H_ + +#include + +struct socfpga_fpga_manager { + /* FPGA Manager Module */ + u32 stat; /* 0x00 */ + u32 ctrl; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; /* 0x10 */ + u32 gpi; + u32 misci; /* 0x18 */ + u32 _pad_0x1c_0x82c[517]; + + /* Configuration Monitor (MON) Registers */ + u32 gpio_inten; /* 0x830 */ + u32 gpio_intmask; + u32 gpio_inttype_level; + u32 gpio_int_polarity; + u32 gpio_intstatus; /* 0x840 */ + u32 gpio_raw_intstatus; + u32 _pad_0x848; + u32 gpio_porta_eoi; + u32 gpio_ext_porta; /* 0x850 */ + u32 _pad_0x854_0x85c[3]; + u32 gpio_1s_sync; /* 0x860 */ + u32 _pad_0x864_0x868[2]; + u32 gpio_ver_id_code; + u32 gpio_config_reg2; /* 0x870 */ + u32 gpio_config_reg1; +}; + +#define FPGAMGRREGS_STAT_MODE_MASK 0x7 +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 +#define FPGAMGRREGS_STAT_MSEL_LSB 3 + +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 +#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 +#define FPGAMGRREGS_CTRL_EN_MASK 0x1 +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 + +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 + +/* FPGA Mode */ +#define FPGAMGRREGS_MODE_FPGAOFF 0x0 +#define FPGAMGRREGS_MODE_RESETPHASE 0x1 +#define FPGAMGRREGS_MODE_CFGPHASE 0x2 +#define FPGAMGRREGS_MODE_INITPHASE 0x3 +#define FPGAMGRREGS_MODE_USERMODE 0x4 +#define FPGAMGRREGS_MODE_UNKNOWN 0x5 + +/* FPGA CD Ratio Value */ +#define CDRATIO_x1 0x0 +#define CDRATIO_x2 0x1 +#define CDRATIO_x4 0x2 +#define CDRATIO_x8 0x3 + +/* SoCFPGA support functions */ +int fpgamgr_test_fpga_ready(void); +int fpgamgr_poll_fpga_ready(void); +int fpgamgr_get_mode(void); + +#endif /* _FPGA_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h new file mode 100644 index 0000000000..f19ad87717 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FREEZE_CONTROLLER_H_ +#define _FREEZE_CONTROLLER_H_ + +struct socfpga_freeze_controller { + u32 vioctrl; + u32 padding[3]; + u32 hioctrl; + u32 src; + u32 hwctrl; +}; + +#define FREEZE_CHANNEL_NUM (4) + +typedef enum { + FREEZE_CTRL_FROZEN = 0, + FREEZE_CTRL_THAWED = 1 +} FREEZE_CTRL_CHAN_STATE; + +#define SYSMGR_FRZCTRL_ADDRESS 0x40 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 +#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 +#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 +#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 + +void sys_mgr_frzctrl_freeze_req(void); +void sys_mgr_frzctrl_thaw_req(void); + +#endif /* _FREEZE_CONTROLLER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/gpio.h b/arch/arm/include/asm/arch-socfpga/gpio.h new file mode 100644 index 0000000000..6c61f188bc --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_GPIO_H +#define _SOCFPGA_GPIO_H + +#endif /* _SOCFPGA_GPIO_H */ diff --git a/arch/arm/include/asm/arch-socfpga/nic301.h b/arch/arm/include/asm/arch-socfpga/nic301.h new file mode 100644 index 0000000000..3c8ab31ffb --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/nic301.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _NIC301_REGISTERS_H_ +#define _NIC301_REGISTERS_H_ + +struct nic301_registers { + u32 remap; /* 0x0 */ + /* Security Register Group */ + u32 _pad_0x4_0x8[1]; + u32 l4main; + u32 l4sp; + u32 l4mp; /* 0x10 */ + u32 l4osc1; + u32 l4spim; + u32 stm; + u32 lwhps2fpgaregs; /* 0x20 */ + u32 _pad_0x24_0x28[1]; + u32 usb1; + u32 nanddata; + u32 _pad_0x30_0x80[20]; + u32 usb0; /* 0x80 */ + u32 nandregs; + u32 qspidata; + u32 fpgamgrdata; + u32 hps2fpgaregs; /* 0x90 */ + u32 acp; + u32 rom; + u32 ocram; + u32 sdrdata; /* 0xA0 */ + u32 _pad_0xa4_0x1fd0[1995]; + /* ID Register Group */ + u32 periph_id_4; /* 0x1FD0 */ + u32 _pad_0x1fd4_0x1fe0[3]; + u32 periph_id_0; /* 0x1FE0 */ + u32 periph_id_1; + u32 periph_id_2; + u32 periph_id_3; + u32 comp_id_0; /* 0x1FF0 */ + u32 comp_id_1; + u32 comp_id_2; + u32 comp_id_3; + u32 _pad_0x2000_0x2008[2]; + /* L4 MAIN */ + u32 l4main_fn_mod_bm_iss; + u32 _pad_0x200c_0x3008[1023]; + /* L4 SP */ + u32 l4sp_fn_mod_bm_iss; + u32 _pad_0x300c_0x4008[1023]; + /* L4 MP */ + u32 l4mp_fn_mod_bm_iss; + u32 _pad_0x400c_0x5008[1023]; + /* L4 OSC1 */ + u32 l4osc_fn_mod_bm_iss; + u32 _pad_0x500c_0x6008[1023]; + /* L4 SPIM */ + u32 l4spim_fn_mod_bm_iss; + u32 _pad_0x600c_0x7008[1023]; + /* STM */ + u32 stm_fn_mod_bm_iss; + u32 _pad_0x700c_0x7108[63]; + u32 stm_fn_mod; + u32 _pad_0x710c_0x8008[959]; + /* LWHPS2FPGA */ + u32 lwhps2fpga_fn_mod_bm_iss; + u32 _pad_0x800c_0x8108[63]; + u32 lwhps2fpga_fn_mod; + u32 _pad_0x810c_0xa008[1983]; + /* USB1 */ + u32 usb1_fn_mod_bm_iss; + u32 _pad_0xa00c_0xa044[14]; + u32 usb1_ahb_cntl; + u32 _pad_0xa048_0xb008[1008]; + /* NANDDATA */ + u32 nanddata_fn_mod_bm_iss; + u32 _pad_0xb00c_0xb108[63]; + u32 nanddata_fn_mod; + u32 _pad_0xb10c_0x20008[21439]; + /* USB0 */ + u32 usb0_fn_mod_bm_iss; + u32 _pad_0x2000c_0x20044[14]; + u32 usb0_ahb_cntl; + u32 _pad_0x20048_0x21008[1008]; + /* NANDREGS */ + u32 nandregs_fn_mod_bm_iss; + u32 _pad_0x2100c_0x21108[63]; + u32 nandregs_fn_mod; + u32 _pad_0x2110c_0x22008[959]; + /* QSPIDATA */ + u32 qspidata_fn_mod_bm_iss; + u32 _pad_0x2200c_0x22044[14]; + u32 qspidata_ahb_cntl; + u32 _pad_0x22048_0x23008[1008]; + /* FPGAMGRDATA */ + u32 fpgamgrdata_fn_mod_bm_iss; + u32 _pad_0x2300c_0x23040[13]; + u32 fpgamgrdata_wr_tidemark; /* 0x23040 */ + u32 _pad_0x23044_0x23108[49]; + u32 fn_mod; + u32 _pad_0x2310c_0x24008[959]; + /* HPS2FPGA */ + u32 hps2fpga_fn_mod_bm_iss; + u32 _pad_0x2400c_0x24040[13]; + u32 hps2fpga_wr_tidemark; /* 0x24040 */ + u32 _pad_0x24044_0x24108[49]; + u32 hps2fpga_fn_mod; + u32 _pad_0x2410c_0x25008[959]; + /* ACP */ + u32 acp_fn_mod_bm_iss; + u32 _pad_0x2500c_0x25108[63]; + u32 acp_fn_mod; + u32 _pad_0x2510c_0x26008[959]; + /* Boot ROM */ + u32 bootrom_fn_mod_bm_iss; + u32 _pad_0x2600c_0x26108[63]; + u32 bootrom_fn_mod; + u32 _pad_0x2610c_0x27008[959]; + /* On-chip RAM */ + u32 ocram_fn_mod_bm_iss; + u32 _pad_0x2700c_0x27040[13]; + u32 ocram_wr_tidemark; /* 0x27040 */ + u32 _pad_0x27044_0x27108[49]; + u32 ocram_fn_mod; + u32 _pad_0x2710c_0x42024[27590]; + /* DAP */ + u32 dap_fn_mod2; + u32 dap_fn_mod_ahb; + u32 _pad_0x4202c_0x42100[53]; + u32 dap_read_qos; /* 0x42100 */ + u32 dap_write_qos; + u32 dap_fn_mod; + u32 _pad_0x4210c_0x43100[1021]; + /* MPU */ + u32 mpu_read_qos; /* 0x43100 */ + u32 mpu_write_qos; + u32 mpu_fn_mod; + u32 _pad_0x4310c_0x44028[967]; + /* SDMMC */ + u32 sdmmc_fn_mod_ahb; + u32 _pad_0x4402c_0x44100[53]; + u32 sdmmc_read_qos; /* 0x44100 */ + u32 sdmmc_write_qos; + u32 sdmmc_fn_mod; + u32 _pad_0x4410c_0x45100[1021]; + /* DMA */ + u32 dma_read_qos; /* 0x45100 */ + u32 dma_write_qos; + u32 dma_fn_mod; + u32 _pad_0x4510c_0x46040[973]; + /* FPGA2HPS */ + u32 fpga2hps_wr_tidemark; /* 0x46040 */ + u32 _pad_0x46044_0x46100[47]; + u32 fpga2hps_read_qos; /* 0x46100 */ + u32 fpga2hps_write_qos; + u32 fpga2hps_fn_mod; + u32 _pad_0x4610c_0x47100[1021]; + /* ETR */ + u32 etr_read_qos; /* 0x47100 */ + u32 etr_write_qos; + u32 etr_fn_mod; + u32 _pad_0x4710c_0x48100[1021]; + /* EMAC0 */ + u32 emac0_read_qos; /* 0x48100 */ + u32 emac0_write_qos; + u32 emac0_fn_mod; + u32 _pad_0x4810c_0x49100[1021]; + /* EMAC1 */ + u32 emac1_read_qos; /* 0x49100 */ + u32 emac1_write_qos; + u32 emac1_fn_mod; + u32 _pad_0x4910c_0x4a028[967]; + /* USB0 */ + u32 usb0_fn_mod_ahb; + u32 _pad_0x4a02c_0x4a100[53]; + u32 usb0_read_qos; /* 0x4A100 */ + u32 usb0_write_qos; + u32 usb0_fn_mod; + u32 _pad_0x4a10c_0x4b100[1021]; + /* NAND */ + u32 nand_read_qos; /* 0x4B100 */ + u32 nand_write_qos; + u32 nand_fn_mod; + u32 _pad_0x4b10c_0x4c028[967]; + /* USB1 */ + u32 usb1_fn_mod_ahb; + u32 _pad_0x4c02c_0x4c100[53]; + u32 usb1_read_qos; /* 0x4C100 */ + u32 usb1_write_qos; + u32 usb1_fn_mod; +}; + +#endif /* _NIC301_REGISTERS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 13d7357702..034135bff4 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,17 +10,33 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_bridges_reset(int enable); + +void socfpga_emac_reset(int enable); +void socfpga_watchdog_reset(void); +void socfpga_spim_enable(void); + struct socfpga_reset_manager { - u32 padding1; + u32 status; u32 ctrl; - u32 padding2; - u32 padding3; + u32 counts; + u32 padding1; u32 mpu_mod_reset; u32 per_mod_reset; u32 per2_mod_reset; u32 brg_mod_reset; }; +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 +#else #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 +#endif + +#define RSTMGR_PERMODRST_EMAC0_LSB 0 +#define RSTMGR_PERMODRST_EMAC1_LSB 1 +#define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_SPIM0_LSB 18 +#define RSTMGR_PERMODRST_SPIM1_LSB 19 #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h new file mode 100644 index 0000000000..1155fd3dec --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SCAN_MANAGER_H_ +#define _SCAN_MANAGER_H_ + +struct socfpga_scan_manager { + u32 stat; + u32 en; + u32 padding[2]; + u32 fifo_single_byte; + u32 fifo_double_byte; + u32 fifo_triple_byte; + u32 fifo_quad_byte; +}; + +/* + * Shift count to get number of IO scan chain data in granularity + * of 128-bit ( N / 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_SHIFT 7 + +/* + * Mask to get residual IO scan chain data in + * granularity of 128-bit ( N mod 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_MASK 0x7F + +/* + * Shift count to get number of IO scan chain + * data in granularity of 32-bit ( N / 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_SHIFT 5 + +/* + * Mask to get residual IO scan chain data in + * granularity of 32-bit ( N mod 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_MASK 0x1F + +/* Byte mask */ +#define IO_SCAN_CHAIN_BYTE_MASK 0xFF + +/* 24-bits (3 bytes) IO scan chain payload definition */ +#define IO_SCAN_CHAIN_PAYLOAD_24BIT 24 + +/* + * Maximum length of TDI_TDO packet payload is 128 bits, + * represented by (length - 1) in TDI_TDO header + */ +#define TDI_TDO_MAX_PAYLOAD 127 + +/* TDI_TDO packet header for IO scan chain program */ +#define TDI_TDO_HEADER_FIRST_BYTE 0x80 + +/* Position of second command byte for TDI_TDO packet */ +#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT 8 + +/* + * Maximum polling loop to wait for IO scan chain engine + * becomes idle to prevent infinite loop + */ +#define SCAN_MAX_DELAY 100 + +#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) +#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) + +/* + * Program HPS IO Scan Chain + * io_scan_chain_id - IO scan chain ID + * io_scan_chain_len_in_bits - IO scan chain length in bits + * iocsr_scan_chain - IO scan chain table + */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain); + +extern const uint32_t iocsr_scan_chain0_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain1_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain2_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain3_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; + +int scan_mgr_configure_iocsr(void); + +#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/scu.h b/arch/arm/include/asm/arch-socfpga/scu.h new file mode 100644 index 0000000000..7a5b07416d --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scu.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOCFPGA_SCU_H__ +#define __SOCFPGA_SCU_H__ + +struct scu_registers { + u32 ctrl; /* 0x00 */ + u32 cfg; + u32 cpsr; + u32 iassr; + u32 _pad_0x10_0x3c[12]; /* 0x10 */ + u32 fsar; /* 0x40 */ + u32 fear; + u32 _pad_0x48_0x50[2]; + u32 acr; /* 0x54 */ + u32 sacr; +}; + +#endif /* __SOCFPGA_SCU_H__ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 1182a133fb..6534283331 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,10 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ -#define SOCFPGA_L3REGS_ADDRESS 0xff800000 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h deleted file mode 100644 index 7e310d5a0c..0000000000 --- a/arch/arm/include/asm/arch-socfpga/spl.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2012 Pavel Machek - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_SPL_H_ -#define _SOCFPGA_SPL_H_ - -/* Symbols from linker script */ -extern char __malloc_start, __malloc_end, __stack_start; - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h new file mode 100644 index 0000000000..071ec4f266 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYSTEM_MANAGER_H_ +#define _SYSTEM_MANAGER_H_ + +#ifndef __ASSEMBLY__ + +void sysmgr_pinmux_init(void); + +/* declaration for handoff table type */ +extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; + +#endif + +struct socfpga_system_manager { + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ + u32 siliconid2; + u32 _pad_0x8_0xf[2]; + u32 wddbg; /* 0x10 */ + u32 bootinfo; + u32 hpsinfo; + u32 parityinj; + /* FPGA Interface Group */ + u32 fpgaintfgrp_gbl; /* 0x20 */ + u32 fpgaintfgrp_indiv; + u32 fpgaintfgrp_module; + u32 _pad_0x2c_0x2f; + /* Scan Manager Group */ + u32 scanmgrgrp_ctrl; /* 0x30 */ + u32 _pad_0x34_0x3f[3]; + /* Freeze Control Group */ + u32 frzctrl_vioctrl; /* 0x40 */ + u32 _pad_0x44_0x4f[3]; + u32 frzctrl_hioctrl; /* 0x50 */ + u32 frzctrl_src; + u32 frzctrl_hwctrl; + u32 _pad_0x5c_0x5f; + /* EMAC Group */ + u32 emacgrp_ctrl; /* 0x60 */ + u32 emacgrp_l3master; + u32 _pad_0x68_0x6f[2]; + /* DMA Controller Group */ + u32 dmagrp_ctrl; /* 0x70 */ + u32 dmagrp_persecurity; + u32 _pad_0x78_0x7f[2]; + /* Preloader (initial software) Group */ + u32 iswgrp_handoff[8]; /* 0x80 */ + u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ + /* Boot ROM Code Register Group */ + u32 romcodegrp_ctrl; /* 0xc0 */ + u32 romcodegrp_cpu1startaddr; + u32 romcodegrp_initswstate; + u32 romcodegrp_initswlastld; + u32 romcodegrp_bootromswstate; /* 0xd0 */ + u32 __pad_0xd4_0xdf[3]; + /* Warm Boot from On-Chip RAM Group */ + u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ + u32 romcodegrp_warmramgrp_datastart; + u32 romcodegrp_warmramgrp_length; + u32 romcodegrp_warmramgrp_execution; + u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ + u32 __pad_0xf4_0xff[3]; + /* Boot ROM Hardware Register Group */ + u32 romhwgrp_ctrl; /* 0x100 */ + u32 _pad_0x104_0x107; + /* SDMMC Controller Group */ + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x110 */ + u32 nandgrp_l3master; + /* USB Controller Group */ + u32 usbgrp_l3master; + u32 _pad_0x11c_0x13f[9]; + /* ECC Management Register Group */ + u32 eccgrp_l2; /* 0x140 */ + u32 eccgrp_ocram; + u32 eccgrp_usb0; + u32 eccgrp_usb1; + u32 eccgrp_emac0; /* 0x150 */ + u32 eccgrp_emac1; + u32 eccgrp_dma; + u32 eccgrp_can0; + u32 eccgrp_can1; /* 0x160 */ + u32 eccgrp_nand; + u32 eccgrp_qspi; + u32 eccgrp_sdmmc; + u32 _pad_0x170_0x3ff[164]; + /* Pin Mux Control Group */ + u32 emacio[20]; /* 0x400 */ + u32 flashio[12]; /* 0x450 */ + u32 generalio[28]; /* 0x480 */ + u32 _pad_0x4f0_0x4ff[4]; + u32 mixed1io[22]; /* 0x500 */ + u32 mixed2io[8]; /* 0x558 */ + u32 gplinmux[23]; /* 0x578 */ + u32 gplmux[71]; /* 0x5d4 */ + u32 nandusefpga; /* 0x6f0 */ + u32 _pad_0x6f4; + u32 rgmii1usefpga; /* 0x6f8 */ + u32 _pad_0x6fc_0x700[2]; + u32 i2c0usefpga; /* 0x704 */ + u32 sdmmcusefpga; /* 0x708 */ + u32 _pad_0x70c_0x710[2]; + u32 rgmii0usefpga; /* 0x714 */ + u32 _pad_0x718_0x720[3]; + u32 i2c3usefpga; /* 0x724 */ + u32 i2c2usefpga; /* 0x728 */ + u32 i2c1usefpga; /* 0x72c */ + u32 spim1usefpga; /* 0x730 */ + u32 _pad_0x734; + u32 spim0usefpga; /* 0x738 */ +}; + +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) +#define SYSMGR_ECC_OCRAM_EN (1 << 0) +#define SYSMGR_ECC_OCRAM_SERR (1 << 3) +#define SYSMGR_ECC_OCRAM_DERR (1 << 4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 +#define SYSMGR_FPGAINTF_SPIM0 (1 << 0) +#define SYSMGR_FPGAINTF_SPIM1 (1 << 1) +#define SYSMGR_FPGAINTF_EMAC0 (1 << 2) +#define SYSMGR_FPGAINTF_EMAC1 (1 << 3) +#define SYSMGR_FPGAINTF_NAND (1 << 4) +#define SYSMGR_FPGAINTF_SDMMC (1 << 5) + +/* FIXME: This is questionable macro. */ +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) + +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 + +#endif /* _SYSTEM_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index f3afd4d065..c6da405cc0 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_NAND_ALE (1 << 17) #if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE 0xD0200000 #define CONFIG_SYS_FSMC_BASE 0xD1800000 #define CONFIG_FSMC_NAND_BASE 0xD2000000 @@ -42,11 +41,9 @@ #define CONFIG_SPEAR_MPMCREGS 100 #elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x94000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x44000000 #undef CONFIG_SYS_NAND_CLE @@ -63,7 +60,6 @@ #define CONFIG_SYS_MACB3_BASE 0xB1800000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE 0xD0180000 #define CONFIG_SYS_FSMC_BASE 0x4C000000 #define CONFIG_SPEAR_EMIBASE 0x40000000 diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h new file mode 100644 index 0000000000..9131ded5eb --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/gpio.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_STV0991_GPIO_H +#define __ASM_ARCH_STV0991_GPIO_H + +enum gpio_direction { + GPIO_DIRECTION_IN, + GPIO_DIRECTION_OUT, +}; + +struct gpio_regs { + u32 data; /* offset 0x0 */ + u32 reserved[0xff]; /* 0x4--0x3fc */ + u32 dir; /* offset 0x400 */ +}; + +#endif /* __ASM_ARCH_STV0991_GPIO_H */ diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h new file mode 100644 index 0000000000..3f6bcaf970 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/hardware.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, STMicroelectronics, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +/* STV0991 */ +#define SRAM0_BASE_ADDR 0x00000000UL +#define SRAM1_BASE_ADDR 0x00068000UL +#define SRAM2_BASE_ADDR 0x000D0000UL +#define SRAM3_BASE_ADDR 0x00138000UL +#define CFS_SRAM0_BASE_ADDR 0x00198000UL +#define CFS_SRAM1_BASE_ADDR 0x001B8000UL +#define FAST_SRAM_BASE_ADDR 0x001D8000UL +#define FLASH_BASE_ADDR 0x40000000UL +#define PL310_BASE_ADDR 0x70000000UL +#define HSAXIM_BASE_ADDR 0x70100000UL +#define IMGSS_BASE_ADDR 0x70200000UL +#define ADC_BASE_ADDR 0x80000000UL +#define GPIOA_BASE_ADDR 0x80001000UL +#define GPIOB_BASE_ADDR 0x80002000UL +#define GPIOC_BASE_ADDR 0x80003000UL +#define HDM_BASE_ADDR 0x80004000UL +#define THSENS_BASE_ADDR 0x80200000UL +#define GPTIMER2_BASE_ADDR 0x80201000UL +#define GPTIMER1_BASE_ADDR 0x80202000UL +#define QSPI_BASE_ADDR 0x80203000UL +#define CGU_BASE_ADDR 0x80204000UL +#define CREG_BASE_ADDR 0x80205000UL +#define PEC_BASE_ADDR 0x80206000UL +#define WDRU_BASE_ADDR 0x80207000UL +#define BSEC_BASE_ADDR 0x80208000UL +#define DAP_ROM_BASE_ADDR 0x80210000UL +#define SOC_CTI_BASE_ADDR 0x80211000UL +#define TPIU_BASE_ADDR 0x80212000UL +#define TMC_ETF_BASE_ADDR 0x80213000UL +#define R4_ETM_BASE_ADDR 0x80214000UL +#define R4_CTI_BASE_ADDR 0x80215000UL +#define R4_DBG_BASE_ADDR 0x80216000UL +#define GMAC_BASE_ADDR 0x80300000UL +#define RNSS_BASE_ADDR 0x80302000UL +#define CRYP_BASE_ADDR 0x80303000UL +#define HASH_BASE_ADDR 0x80304000UL +#define GPDMA_BASE_ADDR 0x80305000UL +#define ISA_BASE_ADDR 0x8032A000UL +#define HCI_BASE_ADDR 0x80400000UL +#define I2C1_BASE_ADDR 0x80401000UL +#define I2C2_BASE_ADDR 0x80402000UL +#define SAI_BASE_ADDR 0x80403000UL +#define USI_BASE_ADDR 0x80404000UL +#define SPI1_BASE_ADDR 0x80405000UL +#define UART_BASE_ADDR 0x80406000UL +#define SPI2_BASE_ADDR 0x80500000UL +#define CAN_BASE_ADDR 0x80501000UL +#define USART1_BASE_ADDR 0x80502000UL +#define USART2_BASE_ADDR 0x80503000UL +#define USART3_BASE_ADDR 0x80504000UL +#define USART4_BASE_ADDR 0x80505000UL +#define USART5_BASE_ADDR 0x80506000UL +#define USART6_BASE_ADDR 0x80507000UL +#define SDI2_BASE_ADDR 0x80600000UL +#define SDI1_BASE_ADDR 0x80601000UL +#define VICA_BASE_ADDR 0x81000000UL +#define VICB_BASE_ADDR 0x81001000UL +#define STM_CHANNELS_BASE_ADDR 0x81100000UL +#define STM_BASE_ADDR 0x81110000UL +#define SROM_BASE_ADDR 0xFFFF0000UL + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h new file mode 100644 index 0000000000..ddcbb57a92 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STV0991_CGU_H +#define _STV0991_CGU_H + +struct stv0991_cgu_regs { + u32 cpu_freq; /* offset 0x0 */ + u32 icn2_freq; /* offset 0x4 */ + u32 dma_freq; /* offset 0x8 */ + u32 isp_freq; /* offset 0xc */ + u32 h264_freq; /* offset 0x10 */ + u32 osif_freq; /* offset 0x14 */ + u32 ren_freq; /* offset 0x18 */ + u32 tim_freq; /* offset 0x1c */ + u32 sai_freq; /* offset 0x20 */ + u32 eth_freq; /* offset 0x24 */ + u32 i2c_freq; /* offset 0x28 */ + u32 spi_freq; /* offset 0x2c */ + u32 uart_freq; /* offset 0x30 */ + u32 qspi_freq; /* offset 0x34 */ + u32 sdio_freq; /* offset 0x38 */ + u32 usi_freq; /* offset 0x3c */ + u32 can_line_freq; /* offset 0x40 */ + u32 debug_freq; /* offset 0x44 */ + u32 trace_freq; /* offset 0x48 */ + u32 stm_freq; /* offset 0x4c */ + u32 eth_ctrl; /* offset 0x50 */ + u32 reserved[3]; /* offset 0x54 */ + u32 osc_ctrl; /* offset 0x60 */ + u32 pll1_ctrl; /* offset 0x64 */ + u32 pll1_freq; /* offset 0x68 */ + u32 pll1_fract; /* offset 0x6c */ + u32 pll1_spread; /* offset 0x70 */ + u32 pll1_status; /* offset 0x74 */ + u32 pll2_ctrl; /* offset 0x78 */ + u32 pll2_freq; /* offset 0x7c */ + u32 pll2_fract; /* offset 0x80 */ + u32 pll2_spread; /* offset 0x84 */ + u32 pll2_status; /* offset 0x88 */ + u32 cgu_enable_1; /* offset 0x8c */ + u32 cgu_enable_2; /* offset 0x90 */ + u32 cgu_isp_pulse; /* offset 0x94 */ + u32 cgu_h264_pulse; /* offset 0x98 */ + u32 cgu_osif_pulse; /* offset 0x9c */ + u32 cgu_ren_pulse; /* offset 0xa0 */ + +}; + +/* CGU Timer */ +#define CLK_TMR_OSC 0 +#define CLK_TMR_MCLK 1 +#define CLK_TMR_PLL1 2 +#define CLK_TMR_PLL2 3 +#define MDIV_SHIFT_TMR 3 +#define DIV_SHIFT_TMR 6 + +#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \ + | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK) + +/* Clock Enable/Disable */ + +#define TIMER1_CLK_EN (1 << 15) + +/* CGU Uart config */ +#define CLK_UART_MCLK 0 +#define CLK_UART_PLL1 1 +#define CLK_UART_PLL2 2 + +#define MDIV_SHIFT_UART 3 +#define DIV_SHIFT_UART 6 + +#define UART_CLK_CFG (4 << DIV_SHIFT_UART \ + | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) + +/* CGU Ethernet clock config */ +#define CLK_ETH_MCLK 0 +#define CLK_ETH_PLL1 1 +#define CLK_ETH_PLL2 2 + +#define MDIV_SHIFT_ETH 3 +#define DIV_SHIFT_ETH 6 +#define DIV_ETH_125 9 +#define DIV_ETH_50 12 +#define DIV_ETH_P2P 15 + +#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \ + | 1 << DIV_ETH_125 \ + | 0 << DIV_SHIFT_ETH \ + | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1) + /* CGU Ethernet control */ + +#define ETH_CLK_TX_EXT_PHY 0 +#define ETH_CLK_TX_125M 1 +#define ETH_CLK_TX_25M 2 +#define ETH_CLK_TX_2M5 3 +#define ETH_CLK_TX_DIS 7 + +#define ETH_CLK_RX_EXT_PHY 0 +#define ETH_CLK_RX_25M 1 +#define ETH_CLK_RX_2M5 2 +#define ETH_CLK_RX_DIS 3 +#define RX_CLK_SHIFT 3 +#define ETH_CLK_MASK ~(0x1F) + +#define ETH_PHY_MODE_GMII 0 +#define ETH_PHY_MODE_RMII 1 +#define ETH_PHY_CLK_DIS 1 + +#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ + | ETH_CLK_TX_EXT_PHY) +#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h new file mode 100644 index 0000000000..c804eb5e4c --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STV0991_CREG_H +#define _STV0991_CREG_H + +struct stv0991_creg { + u32 version; /* offset 0x0 */ + u32 hdpctl; /* offset 0x4 */ + u32 hdpval; /* offset 0x8 */ + u32 hdpgposet; /* offset 0xc */ + u32 hdpgpoclr; /* offset 0x10 */ + u32 hdpgpoval; /* offset 0x14 */ + u32 stm_mux; /* offset 0x18 */ + u32 sysctrl_1; /* offset 0x1c */ + u32 sysctrl_2; /* offset 0x20 */ + u32 sysctrl_3; /* offset 0x24 */ + u32 sysctrl_4; /* offset 0x28 */ + u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ + u32 mux1; /* offset 0x100 */ + u32 mux2; /* offset 0x104 */ + u32 mux3; /* offset 0x108 */ + u32 mux4; /* offset 0x10c */ + u32 mux5; /* offset 0x110 */ + u32 mux6; /* offset 0x114 */ + u32 mux7; /* offset 0x118 */ + u32 mux8; /* offset 0x11c */ + u32 mux9; /* offset 0x120 */ + u32 mux10; /* offset 0x124 */ + u32 mux11; /* offset 0x128 */ + u32 mux12; /* offset 0x12c */ + u32 mux13; /* offset 0x130 */ + u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ + u32 cfg_pad1; /* offset 0x200 */ + u32 cfg_pad2; /* offset 0x204 */ + u32 cfg_pad3; /* offset 0x208 */ + u32 cfg_pad4; /* offset 0x20c */ + u32 cfg_pad5; /* offset 0x210 */ + u32 cfg_pad6; /* offset 0x214 */ + u32 cfg_pad7; /* offset 0x218 */ + u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ + u32 vdd_pad1; /* offset 0x300 */ + u32 vdd_pad2; /* offset 0x304 */ + u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ + u32 vdd_comp1; /* offset 0x400 */ +}; + +/* CREG MUX 12 register */ +#define GPIOC_30_MUX_SHIFT 24 +#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) +#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) + +#define GPIOC_31_MUX_SHIFT 28 +#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) +#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) + +/* CREG MUX 7 register */ +#define GPIOB_16_MUX_SHIFT 0 +#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) +#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) + +#define GPIOB_17_MUX_SHIFT 4 +#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) +#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) + +/* CREG CFG_PAD6 register */ + +#define GPIOC_31_MODE_SHIFT 30 +#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) +#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) +#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) + +#define GPIOC_30_MODE_SHIFT 28 +#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) +#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) +#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) + +/* CREG Ethernet pad config */ + +#define VDD_ETH_PS_1V8 0 +#define VDD_ETH_PS_2V5 2 +#define VDD_ETH_PS_3V3 3 +#define VDD_ETH_PS_MASK 0x3 + +#define VDD_ETH_PS_SHIFT 12 +#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT) + +#define VDD_ETH_M_PS_SHIFT 28 +#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT) + +#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h new file mode 100644 index 0000000000..1151378c5c --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STV0991_DEFS_H__ +#define __STV0991_DEFS_H__ +#include + +extern int stv0991_pinmux_config(enum periph_id); +extern int clock_setup(enum periph_clock); + +#endif + diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h new file mode 100644 index 0000000000..abd7257264 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STV0991_GPT_H +#define _STV0991_GPT_H + +#include + +struct gpt_regs { + u32 cr1; + u32 cr2; + u32 reserved_1; + u32 dier; /* dma_int_en */ + u32 sr; /* status reg */ + u32 egr; /* event gen */ + u32 reserved_2[3]; /* offset 0x18--0x20*/ + u32 cnt; + u32 psc; + u32 arr; +}; + +struct gpt_regs *const gpt1_regs_ptr = + (struct gpt_regs *) GPTIMER1_BASE_ADDR; + +/* Timer control1 register */ +#define GPT_CR1_CEN 0x0001 +#define GPT_MODE_AUTO_RELOAD (1 << 7) + +/* Timer prescalar reg */ +#define GPT_PRESCALER_128 0x128 + +/* Auto reload register for free running config */ +#define GPT_FREE_RUNNING 0xFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_STV0991_HZ 1000 +#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 + +#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h new file mode 100644 index 0000000000..f728c83cb7 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + UART_GPIOC_30_31 = 0, + UART_GPIOB_16_17, + ETH_GPIOB_10_31_C_0_4, + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2S1, +}; + +enum periph_clock { + UART_CLOCK_CFG = 0, + ETH_CLOCK_CFG, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h new file mode 100644 index 0000000000..7e555a237a --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STV0991_WD_RST_H +#define _STV0991_WD_RST_H +#include + +struct stv0991_wd_ru { + u32 wdru_config; + u32 wdru_ctrl1; + u32 wdru_ctrl2; + u32 wdru_tim; + u32 wdru_count; + u32 wdru_stat; + u32 wdru_wrlock; +}; + +struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \ + (struct stv0991_wd_ru *)WDRU_BASE_ADDR; + +/* Watchdog control register */ +#define WDRU_RST_SYS 0x1 + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h new file mode 100644 index 0000000000..3e5d999081 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_H +#define _SUNXI_CLOCK_H + +#include + +#define CLK_GATE_OPEN 0x1 +#define CLK_GATE_CLOSE 0x0 + +/* clock control module regs definition */ +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) +#include +#elif defined(CONFIG_MACH_SUN9I) +#include +#else +#include +#endif + +#ifndef __ASSEMBLY__ +int clock_init(void); +int clock_twi_onoff(int port, int state); +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); +void clock_init_safe(void); +void clock_init_uart(void); +#endif + +#endif /* _SUNXI_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h new file mode 100644 index 0000000000..d297ed0f73 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -0,0 +1,336 @@ +/* + * sun4i, sun5i and sun7i clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN4I_H +#define _SUNXI_CLOCK_SUN4I_H + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_gate; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ + u8 res8[0x4]; + u32 gmac_clk_cfg; /* 0x164 */ +}; + +/* apb1 bit field */ +#define APB1_CLK_SRC_OSC24M (0x0 << 24) +#define APB1_CLK_SRC_PLL6 (0x1 << 24) +#define APB1_CLK_SRC_LOSC (0x2 << 24) +#define APB1_CLK_SRC_MASK (0x3 << 24) +#define APB1_CLK_RATE_N_1 (0x0 << 16) +#define APB1_CLK_RATE_N_2 (0x1 << 16) +#define APB1_CLK_RATE_N_4 (0x2 << 16) +#define APB1_CLK_RATE_N_8 (0x3 << 16) +#define APB1_CLK_RATE_N_MASK (3 << 16) +#define APB1_CLK_RATE_M(m) (((m)-1) << 0) +#define APB1_CLK_RATE_M_MASK (0x1f << 0) + +/* apb1 gate field */ +#define APB1_GATE_UART_SHIFT (16) +#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) +#define APB1_GATE_TWI_SHIFT (0) +#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) + +/* clock divide */ +#define AXI_DIV_SHIFT (0) +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define AHB_DIV_SHIFT (4) +#define AHB_DIV_1 0 +#define AHB_DIV_2 1 +#define AHB_DIV_4 2 +#define AHB_DIV_8 3 +#define APB0_DIV_SHIFT (8) +#define APB0_DIV_1 0 +#define APB0_DIV_2 1 +#define APB0_DIV_4 2 +#define APB0_DIV_8 3 +#define CPU_CLK_SRC_SHIFT (16) +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 + +#define CCM_PLL1_CFG_ENABLE_SHIFT 31 +#define CCM_PLL1_CFG_VCO_RST_SHIFT 30 +#define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26 +#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25 +#define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20 +#define CCM_PLL1_CFG_DIVP_SHIFT 16 +#define CCM_PLL1_CFG_LCK_TMR_SHIFT 13 +#define CCM_PLL1_CFG_FACTOR_N_SHIFT 8 +#define CCM_PLL1_CFG_FACTOR_K_SHIFT 4 +#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3 +#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2 +#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0 + +#define PLL1_CFG_DEFAULT 0xa1005000 + +#define PLL6_CFG_DEFAULT 0xa1009911 + +/* nand clock */ +#define NAND_CLK_SRC_OSC24 0 +#define NAND_CLK_DIV_N 0 +#define NAND_CLK_DIV_M 0 + +/* gps clock */ +#define GPS_SCLK_GATING_OFF 0 +#define GPS_RESET 0 + +/* ahb clock gate bit offset */ +#define AHB_GATE_OFFSET_GPS 26 +#define AHB_GATE_OFFSET_SATA 25 +#define AHB_GATE_OFFSET_PATA 24 +#define AHB_GATE_OFFSET_SPI3 23 +#define AHB_GATE_OFFSET_SPI2 22 +#define AHB_GATE_OFFSET_SPI1 21 +#define AHB_GATE_OFFSET_SPI0 20 +#define AHB_GATE_OFFSET_TS0 18 +#define AHB_GATE_OFFSET_EMAC 17 +#define AHB_GATE_OFFSET_ACE 16 +#define AHB_GATE_OFFSET_DLL 15 +#define AHB_GATE_OFFSET_SDRAM 14 +#define AHB_GATE_OFFSET_NAND 13 +#define AHB_GATE_OFFSET_MS 12 +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_BIST 7 +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 +#define AHB_GATE_OFFSET_USB_OHCI1 4 +#define AHB_GATE_OFFSET_USB_EHCI1 3 +#define AHB_GATE_OFFSET_USB_OHCI0 2 +#define AHB_GATE_OFFSET_USB_EHCI0 1 +#define AHB_GATE_OFFSET_USB0 0 + +/* ahb clock gate bit offset (second register) */ +#define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_DE_FE0 14 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 +#define AHB_GATE_OFFSET_TVE1 3 +#define AHB_GATE_OFFSET_TVE0 2 + +#define CCM_AHB_GATE_GPS (0x1 << 26) +#define CCM_AHB_GATE_SDRAM (0x1 << 14) +#define CCM_AHB_GATE_DLL (0x1 << 15) +#define CCM_AHB_GATE_ACE (0x1 << 16) + +#define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0) +#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15) +#define CCM_PLL3_CTRL_EN (0x1 << 31) + +#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) +#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3) +#define CCM_PLL5_CTRL_M_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2) +#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) +#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) +#define CCM_PLL5_CTRL_K_SHIFT 4 +#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) +#define CCM_PLL5_CTRL_K_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_LDO (0x1 << 7) +#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL5_CTRL_N_SHIFT 8 +#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) +#define CCM_PLL5_CTRL_N_X(n) (n) +#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) +#define CCM_PLL5_CTRL_P_SHIFT 16 +#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) +#define CCM_PLL5_CTRL_P_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_BW (0x1 << 18) +#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) +#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20) +#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f) +#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25) +#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29) +#define CCM_PLL5_CTRL_BYPASS (0x1 << 30) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define CCM_PLL6_CTRL_EN 31 +#define CCM_PLL6_CTRL_BYPASS_EN 30 +#define CCM_PLL6_CTRL_SATA_EN_SHIFT 14 +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) + +#define CCM_GPS_CTRL_RESET (0x1 << 0) +#define CCM_GPS_CTRL_GATE (0x1 << 1) + +#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15) + +#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) +#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) +#define CCM_MBUS_CTRL_M_X(n) ((n) - 1) +#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) +#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) +#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) +#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) +#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) +#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 +#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 +#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 +#define CCM_MBUS_CTRL_GATE (0x1 << 31) + +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_PLL5 (0x2 << 24) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */ +#define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */ +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 +#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 + +#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH0_CTRL_RST (0x1 << 30) +#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) + +#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +/* We leave bit 11 set to 0, so sclk1 == sclk2 */ +#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) +/* Enable / disable both ch1 sclk1 and sclk2 at the same time */ +#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15) + +#define CCM_LVDS_CTRL_RST (1 << 0) + +#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) +#define CCM_HDMI_CTRL_PLL3 (0 << 24) +#define CCM_HDMI_CTRL_PLL7 (1 << 24) +#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) +#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) +/* No separate ddc gate on sun4i, sun5i and sun7i */ +#define CCM_HDMI_CTRL_DDC_GATE 0 +#define CCM_HDMI_CTRL_GATE (0x1 << 31) + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) + +#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) +#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_PHYGATE (0x1 << 8) +/* These 3 are sun6i only, define them as 0 on sun4i */ +#define CCM_USB_CTRL_PHY0_CLK 0 +#define CCM_USB_CTRL_PHY1_CLK 0 +#define CCM_USB_CTRL_PHY2_CLK 0 + +/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ +#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_DE_CTRL_PLL_MASK (3 << 24) +#define CCM_DE_CTRL_PLL3 (0 << 24) +#define CCM_DE_CTRL_PLL7 (1 << 24) +#define CCM_DE_CTRL_PLL5P (2 << 24) +#define CCM_DE_CTRL_RST (1 << 30) +#define CCM_DE_CTRL_GATE (1 << 31) + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll3(unsigned int hz); +unsigned int clock_get_pll5p(void); +unsigned int clock_get_pll6(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h new file mode 100644 index 0000000000..8a803851e4 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -0,0 +1,332 @@ +/* + * sun6i clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN6I_H +#define _SUNXI_CLOCK_SUN6I_H + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 reserved0; + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 reserved1; + u32 pll3_cfg; /* 0x10 pll3 control */ + u32 reserved2; + u32 pll4_cfg; /* 0x18 pll4 control */ + u32 reserved3; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 reserved4; + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 reserved5; + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 reserved6; + u32 pll8_cfg; /* 0x38 pll8 control */ + u32 reserved7; + u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ + u32 pll9_cfg; /* 0x44 pll9 control */ + u32 pll10_cfg; /* 0x48 pll10 control */ + u32 reserved8; + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ + u32 apb2_div; /* 0x58 APB2 divide ratio */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb1_gate; /* 0x68 apb1 module clock gating */ + u32 apb2_gate; /* 0x6c apb2 module clock gating */ + u32 reserved9[4]; + u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ + u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c security system clock control */ + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ + u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ + u32 spi3_clk_cfg; /* 0xac spi3 clock control */ + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/ + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ + u32 reserved10[2]; + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ + u32 reserved11[2]; + u32 usb_clk_cfg; /* 0xcc USB clock control */ + u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */ + u32 reserved12[7]; + u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ + u32 reserved13[2]; + u32 dram_clk_gate; /* 0x100 DRAM module gating */ + u32 be0_clk_cfg; /* 0x104 BE0 module clock */ + u32 be1_clk_cfg; /* 0x108 BE1 module clock */ + u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ + u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ + u32 mp_clk_cfg; /* 0x114 MP module clock */ + u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ + u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ + u32 reserved14[3]; + u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ + u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ + u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ + u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */ + u32 ve_clk_cfg; /* 0x13c VE module clock */ + u32 adda_clk_cfg; /* 0x140 ADDA module clock */ + u32 avs_clk_cfg; /* 0x144 AVS module clock */ + u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ + u32 reserved15; + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ + u32 ps_clk_cfg; /* 0x154 PS module clock */ + u32 mtc_clk_cfg; /* 0x158 MTC module clock */ + u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ + u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ + u32 reserved16; + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ + u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ + u32 reserved17[4]; + u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */ + u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */ + u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */ + u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */ + u32 reserved18[4]; + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ + u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */ + u32 reserved19[21]; + u32 pll_lock; /* 0x200 PLL Lock Time */ + u32 pll1_lock; /* 0x204 PLL1 Lock Time */ + u32 reserved20[6]; + u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */ + u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */ + u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */ + u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */ + u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */ + u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */ + u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */ + u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */ + u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ + u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ + u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ + u32 reserved21[13]; + u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ + u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ + u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ + u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */ + u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */ + u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */ + u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */ + u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */ + u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */ + u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */ + u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */ + u32 reserved22[5]; + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ + u32 reserved23; + u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ + u32 reserved24; + u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ +}; + +/* apb2 bit field */ +#define APB2_CLK_SRC_LOSC (0x0 << 24) +#define APB2_CLK_SRC_OSC24M (0x1 << 24) +#define APB2_CLK_SRC_PLL6 (0x2 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 16) +#define APB2_CLK_RATE_N_2 (0x1 << 16) +#define APB2_CLK_RATE_N_4 (0x2 << 16) +#define APB2_CLK_RATE_N_8 (0x3 << 16) +#define APB2_CLK_RATE_N_MASK (3 << 16) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (0x1f << 0) + +/* apb2 gate field */ +#define APB2_GATE_UART_SHIFT (16) +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) +#define APB2_GATE_TWI_SHIFT (0) +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) + +/* cpu_axi_cfg bits */ +#define AXI_DIV_SHIFT 0 +#define ATB_DIV_SHIFT 8 +#define CPU_CLK_SRC_SHIFT 16 + +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define ATB_DIV_1 0 +#define ATB_DIV_2 1 +#define ATB_DIV_4 2 +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 + +#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) +#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) +#define CCM_PLL1_CTRL_EN (0x1 << 31) + +#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) +#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24) +#define CCM_PLL3_CTRL_EN (0x1 << 31) + +#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) +#define CCM_PLL5_CTRL_UPD (0x1 << 20) +#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ + +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) + +#define AHB1_ABP1_DIV_DEFAULT 0x00002020 + +#define AXI_GATE_OFFSET_DRAM 0 + +/* ahb_gate0 offsets */ +#define AHB_GATE_OFFSET_USB_OHCI1 30 +#define AHB_GATE_OFFSET_USB_OHCI0 29 +#define AHB_GATE_OFFSET_USB_EHCI1 27 +#define AHB_GATE_OFFSET_USB_EHCI0 26 +#define AHB_GATE_OFFSET_USB0 24 +#define AHB_GATE_OFFSET_MCTL 14 +#define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_SS 5 + +/* ahb_gate1 offsets */ +#define AHB_GATE_OFFSET_DRC0 25 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 + +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) +#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +/* There is no global phy clk gate on sun6i, define as 0 */ +#define CCM_USB_CTRL_PHYGATE 0 +#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) +#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) +#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) + +#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ + +#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) +#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) +#define CCM_DRAMCLK_CFG_RST (0x1 << 31) + +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 + +#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24) +/* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */ +#define CCM_LCD_CH0_CTRL_RST 0 +#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) + +#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31) + +#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) +#define CCM_HDMI_CTRL_PLL3 (0 << 24) +#define CCM_HDMI_CTRL_PLL7 (1 << 24) +#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) +#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) +#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30) +#define CCM_HDMI_CTRL_GATE (0x1 << 31) + +#ifndef CONFIG_MACH_SUN8I +#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ +#else +#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */ +#endif + +#define CCM_PLL5_PATTERN 0xd1303333 + +/* ahb_reset0 offsets */ +#define AHB_RESET_OFFSET_GMAC 17 +#define AHB_RESET_OFFSET_MCTL 14 +#define AHB_RESET_OFFSET_MMC3 11 +#define AHB_RESET_OFFSET_MMC2 10 +#define AHB_RESET_OFFSET_MMC1 9 +#define AHB_RESET_OFFSET_MMC0 8 +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) +#define AHB_RESET_OFFSET_SS 5 + +/* ahb_reset1 offsets */ +#define AHB_RESET_OFFSET_DRC0 25 +#define AHB_RESET_OFFSET_DE_BE0 12 +#define AHB_RESET_OFFSET_HDMI 11 +#define AHB_RESET_OFFSET_LCD1 5 +#define AHB_RESET_OFFSET_LCD0 4 + +/* apb2 reset */ +#define APB2_RESET_UART_SHIFT (16) +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) +#define APB2_RESET_TWI_SHIFT (0) +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) + +/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ +#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_DE_CTRL_PLL_MASK (0xf << 24) +#define CCM_DE_CTRL_PLL3 (0 << 24) +#define CCM_DE_CTRL_PLL7 (1 << 24) +#define CCM_DE_CTRL_PLL6_2X (2 << 24) +#define CCM_DE_CTRL_PLL8 (3 << 24) +#define CCM_DE_CTRL_PLL9 (4 << 24) +#define CCM_DE_CTRL_PLL10 (5 << 24) +#define CCM_DE_CTRL_GATE (1 << 31) + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll3(unsigned int hz); +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); +unsigned int clock_get_pll6(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h new file mode 100644 index 0000000000..c506b0a98f --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -0,0 +1,139 @@ +/* + * sun9i clock register definitions + * + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN9I_H +#define _SUNXI_CLOCK_SUN9I_H + +struct sunxi_ccm_reg { + u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ + u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ + u32 pll3_audio_cfg; /* 0x08 audio pll configuration */ + u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */ + u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */ + u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */ + u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */ + u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */ + u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */ + u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */ + u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */ + u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */ + u8 reserved1[0x20]; /* 0x30 */ + u32 cpu_clk_source; /* 0x50 cpu clk source configuration */ + u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */ + u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */ + u32 gtbus_cfg; /* 0x5c gtbus clock configuration */ + u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */ + u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */ + u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */ + u8 reserved2[0x04]; /* 0x6c */ + u32 apb0_cfg; /* 0x70 apb0 clock configuration */ + u32 apb1_cfg; /* 0x74 apb1 clock configuration */ + u32 cci400_cfg; /* 0x78 cci400 clock configuration */ + u8 reserved3[0x04]; /* 0x7c */ + u32 ats_cfg; /* 0x80 ats clock configuration */ + u32 trace_cfg; /* 0x84 trace clock configuration */ + u8 reserved4[0xf8]; /* 0x88 */ + u32 clk_output_a; /* 0x180 clk_output_a */ + u32 clk_output_b; /* 0x184 clk_output_a */ + u8 reserved5[0x278]; /* 0x188 */ + + u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */ + u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */ + u8 reserved6[0x08]; /* 0x408 */ + u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */ + u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */ + u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */ + u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */ + u8 reserved7[0x08]; /* 0x420 */ + u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */ + u32 ss_clk_cfg; /* 0x42c security system clock cfg */ + u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */ + u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */ + u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */ + u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */ + u8 reserved8[0x50]; /* 0x440 */ + u32 de_clk_cfg; /* 0x490 display engine clock configuration */ + u8 reserved9[0x04]; /* 0x494 */ + u32 mp_clk_cfg; /* 0x498 mp clock configuration */ + u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */ + u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */ + u8 reserved10[0x1c]; /* 0x4a4 */ + u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */ + u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */ + u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */ + u32 fd_clk_cfg; /* 0x4cc FD module clock */ + u32 ve_clk_cfg; /* 0x4d0 VE module clock */ + u32 avs_clk_cfg; /* 0x4d4 AVS module clock */ + u8 reserved11[0x18]; /* 0x4d8 */ + u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */ + u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */ + u8 reserved12[0x10]; /* 0x4fc */ + u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */ + u8 reserved13[0x70]; /* 0x510 */ + + u32 ahb_gate0; /* 0x580 AHB0 Gating Register */ + u32 ahb_gate1; /* 0x584 AHB1 Gating Register */ + u32 ahb_gate2; /* 0x588 AHB2 Gating Register */ + u8 reserved14[0x04]; /* 0x58c */ + u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */ + u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */ + u8 reserved15[0x08]; /* 0x598 */ + u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */ + u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ + u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */ + u8 reserved16[0x04]; /* 0x5ac */ + u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */ + u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ +}; + +/* pll4_periph0_cfg */ +#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */ + +#define CCM_PLL4_CTRL_N_SHIFT 8 +#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT) +#define CCM_PLL4_CTRL_P_SHIFT 16 +#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT) +#define CCM_PLL4_CTRL_M_SHIFT 18 +#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT) + +/* sd#_clk_cfg fields */ +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0 << 24) +#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24) +#define CCM_MMC_CTRL_ENABLE (1 << 31) + +/* ahb_gate0 fields */ +/* On sun9i all sdc-s share their ahb gate, so ignore (x) */ +#define AHB_GATE_OFFSET_MMC(x) 8 + +/* apb1_gate fields */ +#define APB1_GATE_UART_SHIFT 16 +#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) +#define APB1_GATE_TWI_SHIFT 0 +#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) + +/* ahb_reset0_cfg fields */ +/* On sun9i all sdc-s share their ahb reset, so ignore (x) */ +#define AHB_RESET_OFFSET_MMC(x) 8 + +/* apb1_reset_cfg fields */ +#define APB1_RESET_UART_SHIFT 16 +#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT) +#define APB1_RESET_TWI_SHIFT 0 +#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) + + +#ifndef __ASSEMBLY__ +unsigned int clock_get_pll4_periph0(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h new file mode 100644 index 0000000000..73583ed445 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_H +#define _SUNXI_CPU_H + +#if defined(CONFIG_MACH_SUN9I) +#include +#else +#include +#endif + +#endif /* _SUNXI_CPU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h new file mode 100644 index 0000000000..dae60696f9 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_SUN4I_H +#define _SUNXI_CPU_SUN4I_H + +#define SUNXI_SRAM_A1_BASE 0x00000000 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ +#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ + +#define SUNXI_SRAMC_BASE 0x01c00000 +#define SUNXI_DRAMC_BASE 0x01c01000 +#define SUNXI_DMA_BASE 0x01c02000 +#define SUNXI_NFC_BASE 0x01c03000 +#define SUNXI_TS_BASE 0x01c04000 +#define SUNXI_SPI0_BASE 0x01c05000 +#define SUNXI_SPI1_BASE 0x01c06000 +#define SUNXI_MS_BASE 0x01c07000 +#define SUNXI_TVD_BASE 0x01c08000 +#define SUNXI_CSI0_BASE 0x01c09000 +#define SUNXI_TVE0_BASE 0x01c0a000 +#define SUNXI_EMAC_BASE 0x01c0b000 +#define SUNXI_LCD0_BASE 0x01c0C000 +#define SUNXI_LCD1_BASE 0x01c0d000 +#define SUNXI_VE_BASE 0x01c0e000 +#define SUNXI_MMC0_BASE 0x01c0f000 +#define SUNXI_MMC1_BASE 0x01c10000 +#define SUNXI_MMC2_BASE 0x01c11000 +#define SUNXI_MMC3_BASE 0x01c12000 +#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I +#define SUNXI_USB0_BASE 0x01c13000 +#define SUNXI_USB1_BASE 0x01c14000 +#endif +#define SUNXI_SS_BASE 0x01c15000 +#define SUNXI_HDMI_BASE 0x01c16000 +#define SUNXI_SPI2_BASE 0x01c17000 +#define SUNXI_SATA_BASE 0x01c18000 +#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I +#define SUNXI_PATA_BASE 0x01c19000 +#define SUNXI_ACE_BASE 0x01c1a000 +#define SUNXI_TVE1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#else +#define SUNXI_USB0_BASE 0x01c19000 +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#endif +#define SUNXI_CSI1_BASE 0x01c1d000 +#define SUNXI_TZASC_BASE 0x01c1e000 +#define SUNXI_SPI3_BASE 0x01c1f000 + +#define SUNXI_CCM_BASE 0x01c20000 +#define SUNXI_INTC_BASE 0x01c20400 +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_TIMER_BASE 0x01c20c00 +#define SUNXI_SPDIF_BASE 0x01c21000 +#define SUNXI_AC97_BASE 0x01c21400 +#define SUNXI_IR0_BASE 0x01c21800 +#define SUNXI_IR1_BASE 0x01c21c00 + +#define SUNXI_IIS_BASE 0x01c22400 +#define SUNXI_LRADC_BASE 0x01c22800 +#define SUNXI_AD_DA_BASE 0x01c22c00 +#define SUNXI_KEYPAD_BASE 0x01c23000 +#define SUNXI_TZPC_BASE 0x01c23400 +#define SUNXI_SID_BASE 0x01c23800 +#define SUNXI_SJTAG_BASE 0x01c23c00 + +#define SUNXI_TP_BASE 0x01c25000 +#define SUNXI_PMU_BASE 0x01c25400 +#define SUN7I_CPUCFG_BASE 0x01c25c00 + +#define SUNXI_UART0_BASE 0x01c28000 +#define SUNXI_UART1_BASE 0x01c28400 +#define SUNXI_UART2_BASE 0x01c28800 +#define SUNXI_UART3_BASE 0x01c28c00 +#define SUNXI_UART4_BASE 0x01c29000 +#define SUNXI_UART5_BASE 0x01c29400 +#define SUNXI_UART6_BASE 0x01c29800 +#define SUNXI_UART7_BASE 0x01c29c00 +#define SUNXI_PS2_0_BASE 0x01c2a000 +#define SUNXI_PS2_1_BASE 0x01c2a400 + +#define SUNXI_TWI0_BASE 0x01c2ac00 +#define SUNXI_TWI1_BASE 0x01c2b000 +#define SUNXI_TWI2_BASE 0x01c2b400 + +#define SUNXI_CAN_BASE 0x01c2bc00 + +#define SUNXI_SCR_BASE 0x01c2c400 + +#ifndef CONFIG_MACH_SUN6I +#define SUNXI_GPS_BASE 0x01c30000 +#define SUNXI_MALI400_BASE 0x01c40000 +#define SUNXI_GMAC_BASE 0x01c50000 +#else +#define SUNXI_GMAC_BASE 0x01c30000 +#endif + +#define SUNXI_DRAM_COM_BASE 0x01c62000 +#define SUNXI_DRAM_CTL0_BASE 0x01c63000 +#define SUNXI_DRAM_CTL1_BASE 0x01c64000 +#define SUNXI_DRAM_PHY0_BASE 0x01c65000 +#define SUNXI_DRAM_PHY1_BASE 0x01c66000 + +/* module sram */ +#define SUNXI_SRAM_C_BASE 0x01d00000 + +#define SUNXI_DE_FE0_BASE 0x01e00000 +#define SUNXI_DE_FE1_BASE 0x01e20000 +#define SUNXI_DE_BE0_BASE 0x01e60000 +#define SUNXI_DE_BE1_BASE 0x01e40000 +#define SUNXI_MP_BASE 0x01e80000 +#define SUNXI_AVG_BASE 0x01ea0000 + +#define SUNXI_RTC_BASE 0x01f00000 +#define SUNXI_PRCM_BASE 0x01f01400 +#define SUN6I_CPUCFG_BASE 0x01f01c00 +#define SUNXI_R_UART_BASE 0x01f02800 +#define SUNXI_R_PIO_BASE 0x01f02c00 +#define SUN6I_P2WI_BASE 0x01f03400 +#define SUNXI_RSB_BASE 0x01f03400 + +/* CoreSight Debug Module */ +#define SUNXI_CSDM_BASE 0x3f500000 + +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ + +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +/* SS bonding ids used for cpu identification */ +#define SUNXI_SS_BOND_ID_A31 4 +#define SUNXI_SS_BOND_ID_A31S 5 + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_ss_bonding_id(void); +int sunxi_get_sid(unsigned int *sid); +#endif /* __ASSEMBLY__ */ + +#endif /* _SUNXI_CPU_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h new file mode 100644 index 0000000000..04889c51fa --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2015 Hans de Goede + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * Jerry Wang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_SUN9I_H +#define _SUNXI_CPU_SUN9I_H + +#define REGS_AHB0_BASE 0x01C00000 +#define REGS_AHB1_BASE 0x00800000 +#define REGS_AHB2_BASE 0x03000000 +#define REGS_APB0_BASE 0x06000000 +#define REGS_APB1_BASE 0x07000000 +#define REGS_RCPUS_BASE 0x08000000 + +#define SUNXI_SRAM_D_BASE 0x08100000 + +/* AHB0 Module */ +#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) +#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) + +#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) +#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) +#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) +#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) +#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) + +#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) +#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) +#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) +#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) + +#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) +#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) +#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) + +/* AHB1 Module */ +#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) +#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) +#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) +#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) +#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) + +/* AHB2 Module */ +#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) +#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) +#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) +#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) +#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) + +#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) +#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) +#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) + +#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) +#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) +#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) +#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) + +#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) +#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) +#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) +#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) +/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ +#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) +#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) + +/* APB0 Module */ +#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) +#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) +#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) +#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) +#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) +#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) + +/* APB1 Module */ +#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) +#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) +#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) +#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) +#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) +#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) +#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) +#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) +#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) +#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) +#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) + +/* RCPUS Module */ +#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) +#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) +#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) +#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) + +/* Misc. */ +#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_sid(unsigned int *sid); +#endif + +#endif /* _SUNXI_CPU_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h new file mode 100644 index 0000000000..e2a29cb181 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h @@ -0,0 +1,67 @@ +/* + * Sunxi A31 CPUCFG register definition. + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DISPLAY_H +#define _SUNXI_DISPLAY_H + +struct sunxi_de_fe_reg { + u32 enable; /* 0x000 */ + u32 frame_ctrl; /* 0x004 */ + u32 bypass; /* 0x008 */ + u32 algorithm_sel; /* 0x00c */ + u32 line_int_ctrl; /* 0x010 */ + u8 res0[0x0c]; /* 0x014 */ + u32 ch0_addr; /* 0x020 */ + u32 ch1_addr; /* 0x024 */ + u32 ch2_addr; /* 0x028 */ + u32 field_sequence; /* 0x02c */ + u32 ch0_offset; /* 0x030 */ + u32 ch1_offset; /* 0x034 */ + u32 ch2_offset; /* 0x038 */ + u8 res1[0x04]; /* 0x03c */ + u32 ch0_stride; /* 0x040 */ + u32 ch1_stride; /* 0x044 */ + u32 ch2_stride; /* 0x048 */ + u32 input_fmt; /* 0x04c */ + u32 ch3_addr; /* 0x050 */ + u32 ch4_addr; /* 0x054 */ + u32 ch5_addr; /* 0x058 */ + u32 output_fmt; /* 0x05c */ + u32 int_enable; /* 0x060 */ + u32 int_status; /* 0x064 */ + u32 status; /* 0x068 */ + u8 res2[0x04]; /* 0x06c */ + u32 csc_coef00; /* 0x070 */ + u32 csc_coef01; /* 0x074 */ + u32 csc_coef02; /* 0x078 */ + u32 csc_coef03; /* 0x07c */ + u32 csc_coef10; /* 0x080 */ + u32 csc_coef11; /* 0x084 */ + u32 csc_coef12; /* 0x088 */ + u32 csc_coef13; /* 0x08c */ + u32 csc_coef20; /* 0x090 */ + u32 csc_coef21; /* 0x094 */ + u32 csc_coef22; /* 0x098 */ + u32 csc_coef23; /* 0x09c */ + u32 deinterlace_ctrl; /* 0x0a0 */ + u32 deinterlace_diag; /* 0x0a4 */ + u32 deinterlace_tempdiff; /* 0x0a8 */ + u32 deinterlace_sawtooth; /* 0x0ac */ + u32 deinterlace_spatcomp; /* 0x0b0 */ + u32 deinterlace_burstlen; /* 0x0b4 */ + u32 deinterlace_preluma; /* 0x0b8 */ + u32 deinterlace_tile_addr; /* 0x0bc */ + u32 deinterlace_tile_stride; /* 0x0c0 */ + u8 res3[0x0c]; /* 0x0c4 */ + u32 wb_stride_enable; /* 0x0d0 */ + u32 ch3_stride; /* 0x0d4 */ + u32 ch4_stride; /* 0x0d8 */ + u32 ch5_stride; /* 0x0dc */ + u32 fe_3d_ctrl; /* 0x0e0 */ + u32 fe_3d_ch0_addr; /* 0x0e4 */ + u32 fe_3d_ch1_addr; /* 0x0e8 */ + u32 fe_3d_ch2_addr; /* 0x0ec */ + u32 fe_3d_ch0_offset; /* 0x0f0 */ + u32 fe_3d_ch1_offset; /* 0x0f4 */ + u32 fe_3d_ch2_offset; /* 0x0f8 */ + u8 res4[0x04]; /* 0x0fc */ + u32 ch0_insize; /* 0x100 */ + u32 ch0_outsize; /* 0x104 */ + u32 ch0_horzfact; /* 0x108 */ + u32 ch0_vertfact; /* 0x10c */ + u32 ch0_horzphase; /* 0x110 */ + u32 ch0_vertphase0; /* 0x114 */ + u32 ch0_vertphase1; /* 0x118 */ + u8 res5[0x04]; /* 0x11c */ + u32 ch0_horztapoffset0; /* 0x120 */ + u32 ch0_horztapoffset1; /* 0x124 */ + u32 ch0_verttapoffset; /* 0x128 */ + u8 res6[0xd4]; /* 0x12c */ + u32 ch1_insize; /* 0x200 */ + u32 ch1_outsize; /* 0x204 */ + u32 ch1_horzfact; /* 0x208 */ + u32 ch1_vertfact; /* 0x20c */ + u32 ch1_horzphase; /* 0x210 */ + u32 ch1_vertphase0; /* 0x214 */ + u32 ch1_vertphase1; /* 0x218 */ + u8 res7[0x04]; /* 0x21c */ + u32 ch1_horztapoffset0; /* 0x220 */ + u32 ch1_horztapoffset1; /* 0x224 */ + u32 ch1_verttapoffset; /* 0x228 */ + u8 res8[0x1d4]; /* 0x22c */ + u32 ch0_horzcoef0[32]; /* 0x400 */ + u32 ch0_horzcoef1[32]; /* 0x480 */ + u32 ch0_vertcoef[32]; /* 0x500 */ + u8 res9[0x80]; /* 0x580 */ + u32 ch1_horzcoef0[32]; /* 0x600 */ + u32 ch1_horzcoef1[32]; /* 0x680 */ + u32 ch1_vertcoef[32]; /* 0x700 */ + u8 res10[0x280]; /* 0x780 */ + u32 vpp_enable; /* 0xa00 */ + u32 vpp_dcti; /* 0xa04 */ + u32 vpp_lp1; /* 0xa08 */ + u32 vpp_lp2; /* 0xa0c */ + u32 vpp_wle; /* 0xa10 */ + u32 vpp_ble; /* 0xa14 */ +}; + +struct sunxi_de_be_reg { + u8 res0[0x800]; /* 0x000 */ + u32 mode; /* 0x800 */ + u32 backcolor; /* 0x804 */ + u32 disp_size; /* 0x808 */ + u8 res1[0x4]; /* 0x80c */ + u32 layer0_size; /* 0x810 */ + u32 layer1_size; /* 0x814 */ + u32 layer2_size; /* 0x818 */ + u32 layer3_size; /* 0x81c */ + u32 layer0_pos; /* 0x820 */ + u32 layer1_pos; /* 0x824 */ + u32 layer2_pos; /* 0x828 */ + u32 layer3_pos; /* 0x82c */ + u8 res2[0x10]; /* 0x830 */ + u32 layer0_stride; /* 0x840 */ + u32 layer1_stride; /* 0x844 */ + u32 layer2_stride; /* 0x848 */ + u32 layer3_stride; /* 0x84c */ + u32 layer0_addr_low32b; /* 0x850 */ + u32 layer1_addr_low32b; /* 0x854 */ + u32 layer2_addr_low32b; /* 0x858 */ + u32 layer3_addr_low32b; /* 0x85c */ + u32 layer0_addr_high4b; /* 0x860 */ + u32 layer1_addr_high4b; /* 0x864 */ + u32 layer2_addr_high4b; /* 0x868 */ + u32 layer3_addr_high4b; /* 0x86c */ + u32 reg_ctrl; /* 0x870 */ + u8 res3[0xc]; /* 0x874 */ + u32 color_key_max; /* 0x880 */ + u32 color_key_min; /* 0x884 */ + u32 color_key_config; /* 0x888 */ + u8 res4[0x4]; /* 0x88c */ + u32 layer0_attr0_ctrl; /* 0x890 */ + u32 layer1_attr0_ctrl; /* 0x894 */ + u32 layer2_attr0_ctrl; /* 0x898 */ + u32 layer3_attr0_ctrl; /* 0x89c */ + u32 layer0_attr1_ctrl; /* 0x8a0 */ + u32 layer1_attr1_ctrl; /* 0x8a4 */ + u32 layer2_attr1_ctrl; /* 0x8a8 */ + u32 layer3_attr1_ctrl; /* 0x8ac */ +}; + +struct sunxi_lcdc_reg { + u32 ctrl; /* 0x00 */ + u32 int0; /* 0x04 */ + u32 int1; /* 0x08 */ + u8 res0[0x04]; /* 0x0c */ + u32 tcon0_frm_ctrl; /* 0x10 */ + u32 tcon0_frm_seed[6]; /* 0x14 */ + u32 tcon0_frm_table[4]; /* 0x2c */ + u8 res1[4]; /* 0x3c */ + u32 tcon0_ctrl; /* 0x40 */ + u32 tcon0_dclk; /* 0x44 */ + u32 tcon0_timing_active; /* 0x48 */ + u32 tcon0_timing_h; /* 0x4c */ + u32 tcon0_timing_v; /* 0x50 */ + u32 tcon0_timing_sync; /* 0x54 */ + u32 tcon0_hv_intf; /* 0x58 */ + u8 res2[0x04]; /* 0x5c */ + u32 tcon0_cpu_intf; /* 0x60 */ + u32 tcon0_cpu_wr_dat; /* 0x64 */ + u32 tcon0_cpu_rd_dat0; /* 0x68 */ + u32 tcon0_cpu_rd_dat1; /* 0x6c */ + u32 tcon0_ttl_timing0; /* 0x70 */ + u32 tcon0_ttl_timing1; /* 0x74 */ + u32 tcon0_ttl_timing2; /* 0x78 */ + u32 tcon0_ttl_timing3; /* 0x7c */ + u32 tcon0_ttl_timing4; /* 0x80 */ + u32 tcon0_lvds_intf; /* 0x84 */ + u32 tcon0_io_polarity; /* 0x88 */ + u32 tcon0_io_tristate; /* 0x8c */ + u32 tcon1_ctrl; /* 0x90 */ + u32 tcon1_timing_source; /* 0x94 */ + u32 tcon1_timing_scale; /* 0x98 */ + u32 tcon1_timing_out; /* 0x9c */ + u32 tcon1_timing_h; /* 0xa0 */ + u32 tcon1_timing_v; /* 0xa4 */ + u32 tcon1_timing_sync; /* 0xa8 */ + u8 res3[0x44]; /* 0xac */ + u32 tcon1_io_polarity; /* 0xf0 */ + u32 tcon1_io_tristate; /* 0xf4 */ + u8 res4[0x128]; /* 0xf8 */ + u32 lvds_ana0; /* 0x220 */ + u32 lvds_ana1; /* 0x224 */ +}; + +struct sunxi_hdmi_reg { + u32 version_id; /* 0x000 */ + u32 ctrl; /* 0x004 */ + u32 irq; /* 0x008 */ + u32 hpd; /* 0x00c */ + u32 video_ctrl; /* 0x010 */ + u32 video_size; /* 0x014 */ + u32 video_bp; /* 0x018 */ + u32 video_fp; /* 0x01c */ + u32 video_spw; /* 0x020 */ + u32 video_polarity; /* 0x024 */ + u8 res0[0x58]; /* 0x028 */ + u8 avi_info_frame[0x14]; /* 0x080 */ + u8 res1[0x4c]; /* 0x094 */ + u32 qcp_packet0; /* 0x0e0 */ + u32 qcp_packet1; /* 0x0e4 */ + u8 res2[0x118]; /* 0x0e8 */ + u32 pad_ctrl0; /* 0x200 */ + u32 pad_ctrl1; /* 0x204 */ + u32 pll_ctrl; /* 0x208 */ + u32 pll_dbg0; /* 0x20c */ + u32 pll_dbg1; /* 0x210 */ + u32 hpd_cec; /* 0x214 */ + u8 res3[0x28]; /* 0x218 */ + u8 vendor_info_frame[0x14]; /* 0x240 */ + u8 res4[0x9c]; /* 0x254 */ + u32 pkt_ctrl0; /* 0x2f0 */ + u32 pkt_ctrl1; /* 0x2f4 */ + u8 res5[0x8]; /* 0x2f8 */ + u32 unknown; /* 0x300 */ + u8 res6[0xc]; /* 0x304 */ + u32 audio_sample_count; /* 0x310 */ + u8 res7[0xec]; /* 0x314 */ + u32 audio_tx_fifo; /* 0x400 */ + u8 res8[0xfc]; /* 0x404 */ +#ifndef CONFIG_MACH_SUN6I + u32 ddc_ctrl; /* 0x500 */ + u32 ddc_addr; /* 0x504 */ + u32 ddc_int_mask; /* 0x508 */ + u32 ddc_int_status; /* 0x50c */ + u32 ddc_fifo_ctrl; /* 0x510 */ + u32 ddc_fifo_status; /* 0x514 */ + u32 ddc_fifo_data; /* 0x518 */ + u32 ddc_byte_count; /* 0x51c */ + u32 ddc_cmnd; /* 0x520 */ + u32 ddc_exreg; /* 0x524 */ + u32 ddc_clock; /* 0x528 */ + u8 res9[0x14]; /* 0x52c */ + u32 ddc_line_ctrl; /* 0x540 */ +#else + u32 ddc_ctrl; /* 0x500 */ + u32 ddc_exreg; /* 0x504 */ + u32 ddc_cmnd; /* 0x508 */ + u32 ddc_addr; /* 0x50c */ + u32 ddc_int_mask; /* 0x510 */ + u32 ddc_int_status; /* 0x514 */ + u32 ddc_fifo_ctrl; /* 0x518 */ + u32 ddc_fifo_status; /* 0x51c */ + u32 ddc_clock; /* 0x520 */ + u32 ddc_timeout; /* 0x524 */ + u8 res9[0x18]; /* 0x528 */ + u32 ddc_dbg; /* 0x540 */ + u8 res10[0x3c]; /* 0x544 */ + u32 ddc_fifo_data; /* 0x580 */ +#endif +}; + +/* + * This is based on the A10s User Manual, and the A10s only supports + * composite video and not vga like the A10 / A20 does, still other + * than the removed vga out capability the tvencoder seems to be the same. + * "unknown#" registers are registers which are used in the A10 kernel code, + * but not documented in the A10s User Manual. + */ +struct sunxi_tve_reg { + u32 gctrl; /* 0x000 */ + u32 cfg0; /* 0x004 */ + u32 dac_cfg0; /* 0x008 */ + u32 filter; /* 0x00c */ + u32 chroma_freq; /* 0x010 */ + u32 porch_num; /* 0x014 */ + u32 unknown0; /* 0x018 */ + u32 line_num; /* 0x01c */ + u32 blank_black_level; /* 0x020 */ + u32 unknown1; /* 0x024, seems to be 1 byte per dac */ + u8 res0[0x08]; /* 0x028 */ + u32 auto_detect_en; /* 0x030 */ + u32 auto_detect_int_status; /* 0x034 */ + u32 auto_detect_status; /* 0x038 */ + u32 auto_detect_debounce; /* 0x03c */ + u32 csc_reg0; /* 0x040 */ + u32 csc_reg1; /* 0x044 */ + u32 csc_reg2; /* 0x048 */ + u32 csc_reg3; /* 0x04c */ + u8 res1[0xb0]; /* 0x050 */ + u32 color_burst; /* 0x100 */ + u32 vsync_num; /* 0x104 */ + u32 notch_freq; /* 0x108 */ + u32 cbr_level; /* 0x10c */ + u32 burst_phase; /* 0x110 */ + u32 burst_width; /* 0x114 */ + u8 res2[0x04]; /* 0x118 */ + u32 sync_vbi_level; /* 0x11c */ + u32 white_level; /* 0x120 */ + u32 active_num; /* 0x124 */ + u32 chroma_bw_gain; /* 0x128 */ + u32 notch_width; /* 0x12c */ + u32 resync_num; /* 0x130 */ + u32 slave_para; /* 0x134 */ + u32 cfg1; /* 0x138 */ + u32 cfg2; /* 0x13c */ +}; + +/* + * DE-FE register constants. + */ +#define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0) +#define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16) +#define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16) +#define SUNXI_DE_FE_ENABLE_EN (1 << 0) +#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0) +#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1) +#define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16) +#define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1) +#define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151 +#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002 + +/* + * DE-BE register constants. + */ +#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0) +#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16) +#define SUNXI_DE_BE_MODE_ENABLE (1 << 0) +#define SUNXI_DE_BE_MODE_START (1 << 1) +#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8) +#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5) +#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0) +#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002 +#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8) + +/* + * LCDC register constants. + */ +#define SUNXI_LCDC_X(x) (((x) - 1) << 16) +#define SUNXI_LCDC_Y(y) (((y) - 1) << 0) +#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) +#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) +#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) +#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) +#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) +#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) +#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) +#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 +#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 +#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 +#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 +#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 +#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) +#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) +#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) +#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) +#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) +#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) +#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) +#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) +#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#define SUNXI_LCDC_LVDS_ANA0 0x3f310000 +#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) +#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) +#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) + +/* + * HDMI register constants. + */ +#define SUNXI_HDMI_X(x) (((x) - 1) << 0) +#define SUNXI_HDMI_Y(y) (((y) - 1) << 16) +#define SUNXI_HDMI_CTRL_ENABLE (1 << 31) +#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0) +#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1) +#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73 +#define SUNXI_HDMI_HPD_DETECT (1 << 0) +#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31) +#define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30) +#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0) +#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1) +#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16) +#define SUNXI_HDMI_QCP_PACKET0 3 +#define SUNXI_HDMI_QCP_PACKET1 0 + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f +#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff +#else +#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000 +#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000 +#endif + +#ifdef CONFIG_MACH_SUN4I +#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820 +#elif defined CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PAD_CTRL1 0x01ded030 +#else +#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830 +#endif +#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6) + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PLL_CTRL 0xba48a308 +#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4) +#else +#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708 +#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4) +#endif +#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4) + +#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21) +#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21) + +#define SUNXI_HDMI_PKT_CTRL0 0x00000f21 +#define SUNXI_HDMI_PKT_CTRL1 0x0000000f +#define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000 + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0) +#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4) +#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6) +#define SUNXI_HMDI_DDC_CTRL_START (1 << 27) +#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31) +#else +#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0) +/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */ +#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0 +#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0 +#define SUNXI_HMDI_DDC_CTRL_START (1 << 30) +#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31) +#endif + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0) +#else +#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0) +#endif +#define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8) +#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16) +#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24) + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15) +#else +#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31) +#endif + +#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6 +#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7 + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_DDC_CLOCK 0x61 +#else +/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */ +#define SUNXI_HDMI_DDC_CLOCK 0x0d +#endif + +#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8) +#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9) + +/* + * TVE register constants. + */ +#define SUNXI_TVE_GCTRL_ENABLE (1 << 0) +/* + * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed + * dac from tve1. When using tve1 the mux value must be written to both tve0's + * and tve1's gctrl reg. + */ +#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4)) +#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) +#define SUNXI_TVE_GCTRL_CFG0_VGA 0x20000000 +#define SUNXI_TVE_GCTRL_DAC_CFG0_VGA 0x403e1ac7 +#define SUNXI_TVE_GCTRL_UNKNOWN1_VGA 0x00000000 +#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0)) +#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16)) +#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0)) +#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8) +#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8)) +#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0 +#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1 +#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3 +#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8) +#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8)) +#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31) +#define SUNXI_TVE_CSC_REG0 0x08440832 +#define SUNXI_TVE_CSC_REG1 0x3b6dace1 +#define SUNXI_TVE_CSC_REG2 0x0e1d13dc +#define SUNXI_TVE_CSC_REG3 0x00108080 + +int sunxi_simplefb_setup(void *blob); + +#endif /* _SUNXI_DISPLAY_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h new file mode 100644 index 0000000000..7ff43e6d3a --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * Sunxi platform dram register definition. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_H +#define _SUNXI_DRAM_H + +#include +#include + +/* dram regs definition */ +#if defined(CONFIG_MACH_SUN6I) +#include +#elif defined(CONFIG_MACH_SUN8I) +#include +#else +#include +#endif + +unsigned long sunxi_dram_init(void); + +/* + * Wait up to 1s for value to be set in given part of reg. + */ +static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val) +{ + unsigned long tmo = timer_get_us() + 1000000; + + while ((readl(reg) & mask) != val) { + if (timer_get_us() > tmo) + panic("Timeout initialising DRAM\n"); + } +} + +/* + * Test if memory at offset offset matches memory at begin of DRAM + */ +static inline bool mctl_mem_matches(u32 offset) +{ + /* Try to write different values to RAM at two addresses */ + writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset); + /* Check if the same value is actually observed when reading back */ + return readl(CONFIG_SYS_SDRAM_BASE) == + readl(CONFIG_SYS_SDRAM_BASE + offset); +} + +#endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h new file mode 100644 index 0000000000..40c385a5bc --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h @@ -0,0 +1,182 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * Sunxi platform dram register definition. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN4I_H +#define _SUNXI_DRAM_SUN4I_H + +struct sunxi_dram_reg { + u32 ccr; /* 0x00 controller configuration register */ + u32 dcr; /* 0x04 dram configuration register */ + u32 iocr; /* 0x08 i/o configuration register */ + u32 csr; /* 0x0c controller status register */ + u32 drr; /* 0x10 dram refresh register */ + u32 tpr0; /* 0x14 dram timing parameters register 0 */ + u32 tpr1; /* 0x18 dram timing parameters register 1 */ + u32 tpr2; /* 0x1c dram timing parameters register 2 */ + u32 gdllcr; /* 0x20 global dll control register */ + u8 res0[0x28]; + u32 rslr0; /* 0x4c rank system latency register */ + u32 rslr1; /* 0x50 rank system latency register */ + u8 res1[0x8]; + u32 rdgr0; /* 0x5c rank dqs gating register */ + u32 rdgr1; /* 0x60 rank dqs gating register */ + u8 res2[0x34]; + u32 odtcr; /* 0x98 odt configuration register */ + u32 dtr0; /* 0x9c data training register 0 */ + u32 dtr1; /* 0xa0 data training register 1 */ + u32 dtar; /* 0xa4 data training address register */ + u32 zqcr0; /* 0xa8 zq control register 0 */ + u32 zqcr1; /* 0xac zq control register 1 */ + u32 zqsr; /* 0xb0 zq status register */ + u32 idcr; /* 0xb4 initializaton delay configure reg */ + u8 res3[0x138]; + u32 mr; /* 0x1f0 mode register */ + u32 emr; /* 0x1f4 extended mode register */ + u32 emr2; /* 0x1f8 extended mode register */ + u32 emr3; /* 0x1fc extended mode register */ + u32 dllctr; /* 0x200 dll control register */ + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ + /* 0x208 dll control register 1(byte 1) */ + /* 0x20c dll control register 2(byte 2) */ + /* 0x210 dll control register 3(byte 3) */ + /* 0x214 dll control register 4(byte 4) */ + u32 dqtr0; /* 0x218 dq timing register */ + u32 dqtr1; /* 0x21c dq timing register */ + u32 dqtr2; /* 0x220 dq timing register */ + u32 dqtr3; /* 0x224 dq timing register */ + u32 dqstr; /* 0x228 dqs timing register */ + u32 dqsbtr; /* 0x22c dqsb timing register */ + u32 mcr; /* 0x230 mode configure register */ + u8 res[0x8]; + u32 ppwrsctl; /* 0x23c pad power save control */ + u32 apr; /* 0x240 arbiter period register */ + u32 pldtr; /* 0x244 priority level data threshold reg */ + u8 res5[0x8]; + u32 hpcr[32]; /* 0x250 host port configure register */ + u8 res6[0x10]; + u32 csel; /* 0x2e0 controller select register */ +}; + +struct dram_para { + u32 clock; + u32 mbus_clock; + u32 type; + u32 rank_num; + u32 density; + u32 io_width; + u32 bus_width; + u32 cas; + u32 zq; + u32 odt_en; + u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */ + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 emr1; + u32 emr2; + u32 emr3; + u32 dqs_gating_delay; + u32 active_windowing; +}; + +#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) +#define DRAM_CCR_DQS_GATE (0x1 << 14) +#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) +#define DRAM_CCR_ITM_OFF (0x1 << 28) +#define DRAM_CCR_DATA_TRAINING (0x1 << 30) +#define DRAM_CCR_INIT (0x1 << 31) + +#define DRAM_MEMORY_TYPE_DDR1 1 +#define DRAM_MEMORY_TYPE_DDR2 2 +#define DRAM_MEMORY_TYPE_DDR3 3 +#define DRAM_MEMORY_TYPE_LPDDR2 4 +#define DRAM_MEMORY_TYPE_LPDDR 5 +#define DRAM_DCR_TYPE (0x1 << 0) +#define DRAM_DCR_TYPE_DDR2 0x0 +#define DRAM_DCR_TYPE_DDR3 0x1 +#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) +#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) +#define DRAM_DCR_IO_WIDTH_8BIT 0x0 +#define DRAM_DCR_IO_WIDTH_16BIT 0x1 +#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) +#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) +#define DRAM_DCR_CHIP_DENSITY_256M 0x0 +#define DRAM_DCR_CHIP_DENSITY_512M 0x1 +#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 +#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 +#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 +#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 +#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) +#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) +#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 +#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 +#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 +#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) +#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) +#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) +#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) +#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) +#define DRAM_DCR_MODE_SEQ 0x0 +#define DRAM_DCR_MODE_INTERLEAVE 0x1 + +#define DRAM_CSR_DTERR (0x1 << 20) +#define DRAM_CSR_DTIERR (0x1 << 21) +#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR) + +#define DRAM_DRR_TRFC(n) ((n) & 0xff) +#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) +#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) + +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) +#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) +#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) +#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) +#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) +#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) +#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) +#define DRAM_MCR_RESET (0x1 << 12) +#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) +#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) +#define DRAM_MCR_DCLK_OUT (0x1 << 16) + +#define DRAM_DLLCR_NRESET (0x1 << 30) +#define DRAM_DLLCR_DISABLE (0x1 << 31) + +#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) +#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) +#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */ +#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */ + +#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ + +#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) +#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) + +#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) +#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) +#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) +#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) +#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) +#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) +#define DRAM_MR_POWER_DOWN (0x1 << 12) + +#define DRAM_CSEL_MAGIC 0x16237495 + +unsigned long dramc_init(struct dram_para *para); + +#endif /* _SUNXI_DRAM_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h new file mode 100644 index 0000000000..9b0b310c2e --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h @@ -0,0 +1,359 @@ +/* + * Sun6i platform dram controller register and constant defines + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN6I_H +#define _SUNXI_DRAM_SUN6I_H + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u32 dbgcr1; /* 0x0c */ + u32 rmcr[8]; /* 0x10 */ + u32 mmcr[16]; /* 0x30 */ + u32 mbagcr[6]; /* 0x70 */ + u32 maer; /* 0x88 */ + u8 res0[0x14]; /* 0x8c */ + u32 mdfscr; /* 0x100 */ + u32 mdfsmer; /* 0x104 */ + u32 mdfsmrmr; /* 0x108 */ + u32 mdfstr0; /* 0x10c */ + u32 mdfstr1; /* 0x110 */ + u32 mdfstr2; /* 0x114 */ + u32 mdfstr3; /* 0x118 */ + u32 mdfsgcr; /* 0x11c */ + u8 res1[0x1c]; /* 0x120 */ + u32 mdfsivr; /* 0x13c */ + u8 res2[0x0c]; /* 0x140 */ + u32 mdfstcr; /* 0x14c */ +}; + +struct sunxi_mctl_ctl_reg { + u8 res0[0x04]; /* 0x00 */ + u32 sctl; /* 0x04 */ + u32 sstat; /* 0x08 */ + u8 res1[0x34]; /* 0x0c */ + u32 mcmd; /* 0x40 */ + u8 res2[0x08]; /* 0x44 */ + u32 cmdstat; /* 0x4c */ + u32 cmdstaten; /* 0x50 */ + u8 res3[0x0c]; /* 0x54 */ + u32 mrrcfg0; /* 0x60 */ + u32 mrrstat0; /* 0x64 */ + u32 mrrstat1; /* 0x68 */ + u8 res4[0x10]; /* 0x6c */ + u32 mcfg1; /* 0x7c */ + u32 mcfg; /* 0x80 */ + u32 ppcfg; /* 0x84 */ + u32 mstat; /* 0x88 */ + u32 lp2zqcfg; /* 0x8c */ + u8 res5[0x04]; /* 0x90 */ + u32 dtustat; /* 0x94 */ + u32 dtuna; /* 0x98 */ + u32 dtune; /* 0x9c */ + u32 dtuprd0; /* 0xa0 */ + u32 dtuprd1; /* 0xa4 */ + u32 dtuprd2; /* 0xa8 */ + u32 dtuprd3; /* 0xac */ + u32 dtuawdt; /* 0xb0 */ + u8 res6[0x0c]; /* 0xb4 */ + u32 togcnt1u; /* 0xc0 */ + u8 res7[0x08]; /* 0xc4 */ + u32 togcnt100n; /* 0xcc */ + u32 trefi; /* 0xd0 */ + u32 tmrd; /* 0xd4 */ + u32 trfc; /* 0xd8 */ + u32 trp; /* 0xdc */ + u32 trtw; /* 0xe0 */ + u32 tal; /* 0xe4 */ + u32 tcl; /* 0xe8 */ + u32 tcwl; /* 0xec */ + u32 tras; /* 0xf0 */ + u32 trc; /* 0xf4 */ + u32 trcd; /* 0xf8 */ + u32 trrd; /* 0xfc */ + u32 trtp; /* 0x100 */ + u32 twr; /* 0x104 */ + u32 twtr; /* 0x108 */ + u32 texsr; /* 0x10c */ + u32 txp; /* 0x110 */ + u32 txpdll; /* 0x114 */ + u32 tzqcs; /* 0x118 */ + u32 tzqcsi; /* 0x11c */ + u32 tdqs; /* 0x120 */ + u32 tcksre; /* 0x124 */ + u32 tcksrx; /* 0x128 */ + u32 tcke; /* 0x12c */ + u32 tmod; /* 0x130 */ + u32 trstl; /* 0x134 */ + u32 tzqcl; /* 0x138 */ + u32 tmrr; /* 0x13c */ + u32 tckesr; /* 0x140 */ + u32 tdpd; /* 0x144 */ + u8 res8[0xb8]; /* 0x148 */ + u32 dtuwactl; /* 0x200 */ + u32 dturactl; /* 0x204 */ + u32 dtucfg; /* 0x208 */ + u32 dtuectl; /* 0x20c */ + u32 dtuwd0; /* 0x210 */ + u32 dtuwd1; /* 0x214 */ + u32 dtuwd2; /* 0x218 */ + u32 dtuwd3; /* 0x21c */ + u32 dtuwdm; /* 0x220 */ + u32 dturd0; /* 0x224 */ + u32 dturd1; /* 0x228 */ + u32 dturd2; /* 0x22c */ + u32 dturd3; /* 0x230 */ + u32 dtulfsrwd; /* 0x234 */ + u32 dtulfsrrd; /* 0x238 */ + u32 dtueaf; /* 0x23c */ + u32 dfitctldly; /* 0x240 */ + u32 dfiodtcfg; /* 0x244 */ + u32 dfiodtcfg1; /* 0x248 */ + u32 dfiodtrmap; /* 0x24c */ + u32 dfitphywrd; /* 0x250 */ + u32 dfitphywrl; /* 0x254 */ + u8 res9[0x08]; /* 0x258 */ + u32 dfitrdden; /* 0x260 */ + u32 dfitphyrdl; /* 0x264 */ + u8 res10[0x08]; /* 0x268 */ + u32 dfitphyupdtype0; /* 0x270 */ + u32 dfitphyupdtype1; /* 0x274 */ + u32 dfitphyupdtype2; /* 0x278 */ + u32 dfitphyupdtype3; /* 0x27c */ + u32 dfitctrlupdmin; /* 0x280 */ + u32 dfitctrlupdmax; /* 0x284 */ + u32 dfitctrlupddly; /* 0x288 */ + u8 res11[4]; /* 0x28c */ + u32 dfiupdcfg; /* 0x290 */ + u32 dfitrefmski; /* 0x294 */ + u32 dfitcrlupdi; /* 0x298 */ + u8 res12[0x10]; /* 0x29c */ + u32 dfitrcfg0; /* 0x2ac */ + u32 dfitrstat0; /* 0x2b0 */ + u32 dfitrwrlvlen; /* 0x2b4 */ + u32 dfitrrdlvlen; /* 0x2b8 */ + u32 dfitrrdlvlgateen; /* 0x2bc */ + u8 res13[0x04]; /* 0x2c0 */ + u32 dfistcfg0; /* 0x2c4 */ + u32 dfistcfg1; /* 0x2c8 */ + u8 res14[0x04]; /* 0x2cc */ + u32 dfitdramclken; /* 0x2d0 */ + u32 dfitdramclkdis; /* 0x2d4 */ + u8 res15[0x18]; /* 0x2d8 */ + u32 dfilpcfg0; /* 0x2f0 */ +}; + +struct sunxi_mctl_phy_reg { + u8 res0[0x04]; /* 0x00 */ + u32 pir; /* 0x04 */ + u32 pgcr; /* 0x08 phy general configuration register */ + u32 pgsr; /* 0x0c */ + u32 dllgcr; /* 0x10 */ + u32 acdllcr; /* 0x14 */ + u32 ptr0; /* 0x18 */ + u32 ptr1; /* 0x1c */ + u32 ptr2; /* 0x20 */ + u32 aciocr; /* 0x24 */ + u32 dxccr; /* 0x28 DATX8 common configuration register */ + u32 dsgcr; /* 0x2c dram system general config register */ + u32 dcr; /* 0x30 */ + u32 dtpr0; /* 0x34 dram timing parameters register 0 */ + u32 dtpr1; /* 0x38 dram timing parameters register 1 */ + u32 dtpr2; /* 0x3c dram timing parameters register 2 */ + u32 mr0; /* 0x40 mode register 0 */ + u32 mr1; /* 0x44 mode register 1 */ + u32 mr2; /* 0x48 mode register 2 */ + u32 mr3; /* 0x4c mode register 3 */ + u32 odtcr; /* 0x50 */ + u32 dtar; /* 0x54 data training address register */ + u32 dtd0; /* 0x58 */ + u32 dtd1; /* 0x5c */ + u8 res1[0x60]; /* 0x60 */ + u32 dcuar; /* 0xc0 */ + u32 dcudr; /* 0xc4 */ + u32 dcurr; /* 0xc8 */ + u32 dculr; /* 0xcc */ + u32 dcugcr; /* 0xd0 */ + u32 dcutpr; /* 0xd4 */ + u32 dcusr0; /* 0xd8 */ + u32 dcusr1; /* 0xdc */ + u8 res2[0x20]; /* 0xe0 */ + u32 bistrr; /* 0x100 */ + u32 bistmskr0; /* 0x104 */ + u32 bistmskr1; /* 0x108 */ + u32 bistwcr; /* 0x10c */ + u32 bistlsr; /* 0x110 */ + u32 bistar0; /* 0x114 */ + u32 bistar1; /* 0x118 */ + u32 bistar2; /* 0x11c */ + u32 bistupdr; /* 0x120 */ + u32 bistgsr; /* 0x124 */ + u32 bistwer; /* 0x128 */ + u32 bistber0; /* 0x12c */ + u32 bistber1; /* 0x130 */ + u32 bistber2; /* 0x134 */ + u32 bistwcsr; /* 0x138 */ + u32 bistfwr0; /* 0x13c */ + u32 bistfwr1; /* 0x140 */ + u8 res3[0x3c]; /* 0x144 */ + u32 zq0cr0; /* 0x180 zq 0 control register 0 */ + u32 zq0cr1; /* 0x184 zq 0 control register 1 */ + u32 zq0sr0; /* 0x188 zq 0 status register 0 */ + u32 zq0sr1; /* 0x18c zq 0 status register 1 */ + u8 res4[0x30]; /* 0x190 */ + u32 dx0gcr; /* 0x1c0 */ + u32 dx0gsr0; /* 0x1c4 */ + u32 dx0gsr1; /* 0x1c8 */ + u32 dx0dllcr; /* 0x1cc */ + u32 dx0dqtr; /* 0x1d0 */ + u32 dx0dqstr; /* 0x1d4 */ + u8 res5[0x28]; /* 0x1d8 */ + u32 dx1gcr; /* 0x200 */ + u32 dx1gsr0; /* 0x204 */ + u32 dx1gsr1; /* 0x208 */ + u32 dx1dllcr; /* 0x20c */ + u32 dx1dqtr; /* 0x210 */ + u32 dx1dqstr; /* 0x214 */ + u8 res6[0x28]; /* 0x218 */ + u32 dx2gcr; /* 0x240 */ + u32 dx2gsr0; /* 0x244 */ + u32 dx2gsr1; /* 0x248 */ + u32 dx2dllcr; /* 0x24c */ + u32 dx2dqtr; /* 0x250 */ + u32 dx2dqstr; /* 0x254 */ + u8 res7[0x28]; /* 0x258 */ + u32 dx3gcr; /* 0x280 */ + u32 dx3gsr0; /* 0x284 */ + u32 dx3gsr1; /* 0x288 */ + u32 dx3dllcr; /* 0x28c */ + u32 dx3dqtr; /* 0x290 */ + u32 dx3dqstr; /* 0x294 */ +}; + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_RANK_MASK (3 << 0) +#define MCTL_CR_RANK(x) (((x) - 1) << 0) +#define MCTL_CR_BANK_MASK (3 << 2) +#define MCTL_CR_BANK(x) ((x) << 2) +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_BUSW_MASK (3 << 12) +#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_BUSW32 (3 << 12) +#define MCTL_CR_SEQUENCE (1 << 15) +#define MCTL_CR_DDR3 (3 << 16) +#define MCTL_CR_CHANNEL_MASK (1 << 19) +#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) +#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20)) +#define MCTL_CCR_CH0_CLK_EN (1 << 0) +#define MCTL_CCR_CH1_CLK_EN (1 << 1) +#define MCTL_CCR_MASTER_CLK_EN (1 << 2) + +/* + * DRAM control (sunxi_mctl_ctl_reg) register constants. + * Note that we use constant values for a lot of the timings, this is what + * the original boot0 bootloader does. + */ +#define MCTL_SCTL_CONFIG 1 +#define MCTL_SCTL_ACCESS 2 +#define MCTL_MCMD_NOP 0x88000000 +#define MCTL_MCMD_BUSY 0x80000000 +#define MCTL_MCFG_DDR3 0x70061 +#define MCTL_TREFI 78 +#define MCTL_TMRD 4 +#define MCTL_TRFC 115 +#define MCTL_TRP 9 +#define MCTL_TPREA 0 +#define MCTL_TRTW 2 +#define MCTL_TAL 0 +#define MCTL_TCL 9 +#define MCTL_TCWL 8 +#define MCTL_TRAS 18 +#define MCTL_TRC 23 +#define MCTL_TRCD 9 +#define MCTL_TRRD 4 +#define MCTL_TRTP 4 +#define MCTL_TWR 8 +#define MCTL_TWTR 4 +#define MCTL_TEXSR 512 +#define MCTL_TXP 4 +#define MCTL_TXPDLL 14 +#define MCTL_TZQCS 64 +#define MCTL_TZQCSI 0 +#define MCTL_TDQS 1 +#define MCTL_TCKSRE 5 +#define MCTL_TCKSRX 5 +#define MCTL_TCKE 4 +#define MCTL_TMOD 12 +#define MCTL_TRSTL 80 +#define MCTL_TZQCL 512 +#define MCTL_TMRR 2 +#define MCTL_TCKESR 5 +#define MCTL_TDPD 0 +#define MCTL_DFITPHYRDL 15 +#define MCTL_DFIUPDCFG_UPD (1 << 1) +#define MCTL_DFISTCFG0 5 + +/* + * DRAM phy (sunxi_mctl_phy_reg) register values / constants. + */ +#define MCTL_PIR_CLEAR_STATUS (1 << 28) +#define MCTL_PIR_STEP1 0xe9 +#define MCTL_PIR_STEP2 0x81 +#define MCTL_PGCR_RANK (1 << 19) +#define MCTL_PGCR 0x018c0202 +#define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5) +/* constants for both acdllcr as well as dx#dllcr */ +#define MCTL_DLLCR_NRESET (1 << 30) +#define MCTL_DLLCR_DISABLE (1 << 31) +/* ptr constants these are or-ed together to get the final ptr# values */ +#define MCTL_TITMSRST 10 +#define MCTL_TDLLLOCK 2250 +#define MCTL_TDLLSRST 23 +#define MCTL_TDINIT0 217000 +#define MCTL_TDINIT1 160 +#define MCTL_TDINIT2 87000 +#define MCTL_TDINIT3 433 +/* end ptr constants */ +#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3)) +#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2)) +#define MCTL_DXCCR 0x800 +#define MCTL_DSGCR_ENABLE (1 << 28) +#define MCTL_DSGCR 0xf200001b +#define MCTL_DCR_DDR3 0x0b +/* dtpr constants these are or-ed together to get the final dtpr# values */ +#define MCTL_TCCD 0 +#define MCTL_TDQSCKMAX 1 +#define MCTL_TDQSCK 1 +#define MCTL_TRTODT 0 +#define MCTL_TFAW 20 +#define MCTL_TAOND 0 +#define MCTL_TDLLK 512 +/* end dtpr constants */ +#define MCTL_MR0 0x1a50 +#define MCTL_MR1 0x4 +#define MCTL_MR2 ((MCTL_TCWL - 5) << 3) +#define MCTL_MR3 0x0 +#define MCTL_DX_GCR_EN (1 << 0) +#define MCTL_DX_GCR 0x880 +#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0) +#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1) +#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4) +#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5) + +#endif /* _SUNXI_DRAM_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i.h new file mode 100644 index 0000000000..06adee2723 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i.h @@ -0,0 +1,266 @@ +/* + * Sun8i platform dram controller register and constant defines + * + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * CPL + * Jerry Wang + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN8I_H +#define _SUNXI_DRAM_SUN8I_H + +struct dram_para { + u32 clock; + u32 type; + u32 zq; + u32 odt_en; + u32 para1; + u32 para2; + u32 mr0; + u32 mr1; + u32 mr2; + u32 mr3; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 tpr6; + u32 tpr7; + u32 tpr8; + u32 tpr9; + u32 tpr10; + u32 tpr11; + u32 tpr12; + u32 tpr13; +}; + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u8 res0[0x4]; /* 0x0c */ + u32 mcr0_0; /* 0x10 */ + u32 mcr1_0; /* 0x14 */ + u32 mcr0_1; /* 0x18 */ + u32 mcr1_1; /* 0x1c */ + u32 mcr0_2; /* 0x20 */ + u32 mcr1_2; /* 0x24 */ + u32 mcr0_3; /* 0x28 */ + u32 mcr1_3; /* 0x2c */ + u32 mcr0_4; /* 0x30 */ + u32 mcr1_4; /* 0x34 */ + u32 mcr0_5; /* 0x38 */ + u32 mcr1_5; /* 0x3c */ + u32 mcr0_6; /* 0x40 */ + u32 mcr1_6; /* 0x44 */ + u32 mcr0_7; /* 0x48 */ + u32 mcr1_7; /* 0x4c */ + u32 mcr0_8; /* 0x50 */ + u32 mcr1_8; /* 0x54 */ + u32 mcr0_9; /* 0x58 */ + u32 mcr1_9; /* 0x5c */ + u32 mcr0_10; /* 0x60 */ + u32 mcr1_10; /* 0x64 */ + u32 mcr0_11; /* 0x68 */ + u32 mcr1_11; /* 0x6c */ + u32 mcr0_12; /* 0x70 */ + u32 mcr1_12; /* 0x74 */ + u32 mcr0_13; /* 0x78 */ + u32 mcr1_13; /* 0x7c */ + u32 mcr0_14; /* 0x80 */ + u32 mcr1_14; /* 0x84 */ + u32 mcr0_15; /* 0x88 */ + u32 mcr1_15; /* 0x8c */ + u32 bwcr; /* 0x90 */ + u32 maer; /* 0x94 */ + u8 res1[0x4]; /* 0x98 */ + u32 mcgcr; /* 0x9c */ + u32 bwctr; /* 0xa0 */ + u8 res2[0x4]; /* 0xa4 */ + u32 swonr; /* 0xa8 */ + u32 swoffr; /* 0xac */ +}; + +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x00 */ + u32 statr; /* 0x04 */ + u8 res0[0x08]; /* 0x08 */ + u32 mrctrl0; /* 0x10 */ + u32 mrctrl1; /* 0x14 */ + u32 mrstatr; /* 0x18 */ + u8 res1[0x04]; /* 0x1c */ + u32 derateen; /* 0x20 */ + u32 deratenint; /* 0x24 */ + u8 res2[0x08]; /* 0x28 */ + u32 pwrctl; /* 0x30 */ + u32 pwrtmg; /* 0x34 */ + u8 res3[0x18]; /* 0x38 */ + u32 rfshctl0; /* 0x50 */ + u32 rfshctl1; /* 0x54 */ + u8 res4[0x8]; /* 0x58 */ + u32 rfshctl3; /* 0x60 */ + u32 rfshtmg; /* 0x64 */ + u8 res6[0x68]; /* 0x68 */ + u32 init0; /* 0xd0 */ + u32 init1; /* 0xd4 */ + u32 init2; /* 0xd8 */ + u32 init3; /* 0xdc */ + u32 init4; /* 0xe0 */ + u32 init5; /* 0xe4 */ + u8 res7[0x0c]; /* 0xe8 */ + u32 rankctl; /* 0xf4 */ + u8 res8[0x08]; /* 0xf8 */ + u32 dramtmg0; /* 0x100 */ + u32 dramtmg1; /* 0x104 */ + u32 dramtmg2; /* 0x108 */ + u32 dramtmg3; /* 0x10c */ + u32 dramtmg4; /* 0x110 */ + u32 dramtmg5; /* 0x114 */ + u32 dramtmg6; /* 0x118 */ + u32 dramtmg7; /* 0x11c */ + u32 dramtmg8; /* 0x120 */ + u8 res9[0x5c]; /* 0x124 */ + u32 zqctl0; /* 0x180 */ + u32 zqctl1; /* 0x184 */ + u32 zqctl2; /* 0x188 */ + u32 zqstat; /* 0x18c */ + u32 pitmg0; /* 0x190 */ + u32 pitmg1; /* 0x194 */ + u32 plpcfg0; /* 0x198 */ + u8 res10[0x04]; /* 0x19c */ + u32 upd0; /* 0x1a0 */ + u32 upd1; /* 0x1a4 */ + u32 upd2; /* 0x1a8 */ + u32 upd3; /* 0x1ac */ + u32 pimisc; /* 0x1b0 */ + u8 res11[0x1c]; /* 0x1b4 */ + u32 trainctl0; /* 0x1d0 */ + u32 trainctl1; /* 0x1d4 */ + u32 trainctl2; /* 0x1d8 */ + u32 trainstat; /* 0x1dc */ + u8 res12[0x60]; /* 0x1e0 */ + u32 odtcfg; /* 0x240 */ + u32 odtmap; /* 0x244 */ + u8 res13[0x08]; /* 0x248 */ + u32 sched; /* 0x250 */ + u8 res14[0x04]; /* 0x254 */ + u32 perfshpr0; /* 0x258 */ + u32 perfshpr1; /* 0x25c */ + u32 perflpr0; /* 0x260 */ + u32 perflpr1; /* 0x264 */ + u32 perfwr0; /* 0x268 */ + u32 perfwr1; /* 0x26c */ +}; + +struct sunxi_mctl_phy_reg { + u8 res0[0x04]; /* 0x00 */ + u32 pir; /* 0x04 */ + u32 pgcr0; /* 0x08 phy general configuration register */ + u32 pgcr1; /* 0x0c phy general configuration register */ + u32 pgsr0; /* 0x10 */ + u32 pgsr1; /* 0x14 */ + u32 dllgcr; /* 0x18 */ + u32 ptr0; /* 0x1c */ + u32 ptr1; /* 0x20 */ + u32 ptr2; /* 0x24 */ + u32 ptr3; /* 0x28 */ + u32 ptr4; /* 0x2c */ + u32 acmdlr; /* 0x30 */ + u32 acbdlr; /* 0x34 */ + u32 aciocr; /* 0x38 */ + u32 dxccr; /* 0x3c DATX8 common configuration register */ + u32 dsgcr; /* 0x40 dram system general config register */ + u32 dcr; /* 0x44 */ + u32 dtpr0; /* 0x48 dram timing parameters register 0 */ + u32 dtpr1; /* 0x4c dram timing parameters register 1 */ + u32 dtpr2; /* 0x50 dram timing parameters register 2 */ + u32 mr0; /* 0x54 mode register 0 */ + u32 mr1; /* 0x58 mode register 1 */ + u32 mr2; /* 0x5c mode register 2 */ + u32 mr3; /* 0x60 mode register 3 */ + u32 odtcr; /* 0x64 */ + u32 dtcr; /* 0x68 */ + u32 dtar0; /* 0x6c data training address register 0 */ + u32 dtar1; /* 0x70 data training address register 1 */ + u32 dtar2; /* 0x74 data training address register 2 */ + u32 dtar3; /* 0x78 data training address register 3 */ + u32 dtdr0; /* 0x7c */ + u32 dtdr1; /* 0x80 */ + u32 dtedr0; /* 0x84 */ + u32 dtedr1; /* 0x88 */ + u32 pgcr2; /* 0x8c */ + u8 res1[0x70]; /* 0x90 */ + u32 bistrr; /* 0x100 */ + u32 bistwcr; /* 0x104 */ + u32 bistmskr0; /* 0x108 */ + u32 bistmskr1; /* 0x10c */ + u32 bistmskr2; /* 0x110 */ + u32 bistlsr; /* 0x114 */ + u32 bistar0; /* 0x118 */ + u32 bistar1; /* 0x11c */ + u32 bistar2; /* 0x120 */ + u32 bistupdr; /* 0x124 */ + u32 bistgsr; /* 0x128 */ + u32 bistwer; /* 0x12c */ + u32 bistber0; /* 0x130 */ + u32 bistber1; /* 0x134 */ + u32 bistber2; /* 0x138 */ + u32 bistber3; /* 0x13c */ + u32 bistwcsr; /* 0x140 */ + u32 bistfwr0; /* 0x144 */ + u32 bistfwr1; /* 0x148 */ + u32 bistfwr2; /* 0x14c */ + u8 res2[0x30]; /* 0x150 */ + u32 zqcr0; /* 0x180 zq control register 0 */ + u32 zqcr1; /* 0x184 zq control register 1 */ + u32 zqsr0; /* 0x188 zq status register 0 */ + u32 zqsr1; /* 0x18c zq status register 1 */ + u32 zqcr2; /* 0x190 zq control register 2 */ + u8 res3[0x2c]; /* 0x194 */ + u32 dx0gcr; /* 0x1c0 */ + u32 dx0gsr0; /* 0x1c4 */ + u32 dx0gsr1; /* 0x1c8 */ + u32 dx0bdlr0; /* 0x1cc */ + u32 dx0bdlr1; /* 0x1d0 */ + u32 dx0bdlr2; /* 0x1d4 */ + u32 dx0bdlr3; /* 0x1d8 */ + u32 dx0bdlr4; /* 0x1dc */ + u32 dx0lcdlr0; /* 0x1e0 */ + u32 dx0lcdlr1; /* 0x1e4 */ + u32 dx0lcdlr2; /* 0x1e8 */ + u32 dx0mdlr; /* 0x1ec */ + u32 dx0gtr; /* 0x1f0 */ + u32 dx0gsr2; /* 0x1f4 */ + u8 res4[0x08]; /* 0x1f8 */ + u32 dx1gcr; /* 0x200 */ + u32 dx1gsr0; /* 0x204 */ + u32 dx1gsr1; /* 0x208 */ + u32 dx1bdlr0; /* 0x20c */ + u32 dx1bdlr1; /* 0x210 */ + u32 dx1bdlr2; /* 0x214 */ + u32 dx1bdlr3; /* 0x218 */ + u32 dx1bdlr4; /* 0x21c */ + u32 dx1lcdlr0; /* 0x220 */ + u32 dx1lcdlr1; /* 0x224 */ + u32 dx1lcdlr2; /* 0x228 */ + u32 dx1mdlr; /* 0x22c */ + u32 dx1gtr; /* 0x230 */ + u32 dx1gsr2; /* 0x234 */ +}; + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((x) << 8) + +#endif /* _SUNXI_DRAM_SUN8I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h new file mode 100644 index 0000000000..f2c247d79f --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_GPIO_H +#define _SUNXI_GPIO_H + +#include +#include + +/* + * sunxi has 9 banks of gpio, they are: + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 + */ + +#define SUNXI_GPIO_A 0 +#define SUNXI_GPIO_B 1 +#define SUNXI_GPIO_C 2 +#define SUNXI_GPIO_D 3 +#define SUNXI_GPIO_E 4 +#define SUNXI_GPIO_F 5 +#define SUNXI_GPIO_G 6 +#define SUNXI_GPIO_H 7 +#define SUNXI_GPIO_I 8 + +/* + * This defines the number of GPIO banks for the _main_ GPIO controller. + * You should fix up the padding in struct sunxi_gpio_reg below if you + * change this. + */ +#define SUNXI_GPIO_BANKS 9 + +/* + * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) + * at a different register offset. + * + * sun6i has 2 banks: + * PL0 - PL8 | PM0 - PM7 + * + * sun8i has 1 bank: + * PL0 - PL11 + * + * sun9i has 3 banks: + * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 + */ +#define SUNXI_GPIO_L 11 +#define SUNXI_GPIO_M 12 +#define SUNXI_GPIO_N 13 + +struct sunxi_gpio { + u32 cfg[4]; + u32 dat; + u32 drv[2]; + u32 pull[2]; +}; + +/* gpio interrupt control */ +struct sunxi_gpio_int { + u32 cfg[3]; + u32 ctl; + u32 sta; + u32 deb; /* interrupt debounce */ +}; + +struct sunxi_gpio_reg { + struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; + u8 res[0xbc]; + struct sunxi_gpio_int gpio_int; +}; + +#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ + &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) + +#define GPIO_BANK(pin) ((pin) >> 5) +#define GPIO_NUM(pin) ((pin) & 0x1f) + +#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) +#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) + +#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) +#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) + +#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) +#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) + +/* GPIO bank sizes */ +#define SUNXI_GPIO_A_NR 32 +#define SUNXI_GPIO_B_NR 32 +#define SUNXI_GPIO_C_NR 32 +#define SUNXI_GPIO_D_NR 32 +#define SUNXI_GPIO_E_NR 32 +#define SUNXI_GPIO_F_NR 32 +#define SUNXI_GPIO_G_NR 32 +#define SUNXI_GPIO_H_NR 32 +#define SUNXI_GPIO_I_NR 32 +#define SUNXI_GPIO_L_NR 32 +#define SUNXI_GPIO_M_NR 32 + +#define SUNXI_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + 0) + +enum sunxi_gpio_number { + SUNXI_GPIO_A_START = 0, + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), + SUNXI_GPIO_L_START = 352, + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), + SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), + SUNXI_GPIO_AXP0_START = 1024, +}; + +/* SUNXI GPIO number definitions */ +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) +#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) + +#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) + +/* GPIO pin function config */ +#define SUNXI_GPIO_INPUT 0 +#define SUNXI_GPIO_OUTPUT 1 + +#define SUNXI_GPA0_EMAC 2 +#define SUN6I_GPA0_GMAC 2 +#define SUN7I_GPA0_GMAC 5 + +#define SUNXI_GPB0_TWI0 2 + +#define SUN4I_GPB22_UART0_TX 2 +#define SUN4I_GPB23_UART0_RX 2 + +#define SUN5I_GPB19_UART0_TX 2 +#define SUN5I_GPB20_UART0_RX 2 + +#define SUNXI_GPC6_SDC2 3 + +#define SUNXI_GPD0_LCD0 2 +#define SUNXI_GPD0_LVDS0 3 + +#define SUNXI_GPF0_SDC0 2 + +#define SUNXI_GPF2_SDC0 2 + +#ifdef CONFIG_MACH_SUN8I +#define SUNXI_GPF2_UART0_TX 3 +#define SUNXI_GPF4_UART0_RX 3 +#else +#define SUNXI_GPF2_UART0_TX 4 +#define SUNXI_GPF4_UART0_RX 4 +#endif + +#define SUN4I_GPG0_SDC1 4 + +#define SUN5I_GPG3_SDC1 2 + +#define SUN5I_GPG3_UART1_TX 4 +#define SUN5I_GPG4_UART1_RX 4 + +#define SUN4I_GPH22_SDC1 5 + +#define SUN6I_GPH20_UART0_TX 2 +#define SUN6I_GPH21_UART0_RX 2 + +#define SUN4I_GPI4_SDC3 2 + +#define SUN6I_GPL0_R_P2WI_SCK 3 +#define SUN6I_GPL1_R_P2WI_SDA 3 + +#define SUN8I_GPL0_R_RSB_SCK 2 +#define SUN8I_GPL1_R_RSB_SDA 2 +#define SUN8I_GPL2_R_UART_TX 2 +#define SUN8I_GPL3_R_UART_RX 2 + +#define SUN9I_GPN0_R_RSB_SCK 3 +#define SUN9I_GPN1_R_RSB_SDA 3 + +/* GPIO pin pull-up/down config */ +#define SUNXI_GPIO_PULL_DISABLE 0 +#define SUNXI_GPIO_PULL_UP 1 +#define SUNXI_GPIO_PULL_DOWN 2 + +void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); +void sunxi_gpio_set_cfgpin(u32 pin, u32 val); +int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); +int sunxi_gpio_get_cfgpin(u32 pin); +int sunxi_gpio_set_drv(u32 pin, u32 val); +int sunxi_gpio_set_pull(u32 pin, u32 val); +int sunxi_name_to_gpio(const char *name); +#define name_to_gpio(name) sunxi_name_to_gpio(name) + +#endif /* _SUNXI_GPIO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h new file mode 100644 index 0000000000..dc5406b213 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -0,0 +1,15 @@ +/* + * Copyright 2014 - Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SUNXI_I2C_H_ +#define _SUNXI_I2C_H_ + +#include + +#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE +/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ +#define CONFIG_SYS_TCLK 24000000 + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h new file mode 100644 index 0000000000..74833b51d1 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Aaron + * + * MMC register definition for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_MMC_H +#define _SUNXI_MMC_H + +#include + +struct sunxi_mmc { + u32 gctrl; /* 0x00 global control */ + u32 clkcr; /* 0x04 clock control */ + u32 timeout; /* 0x08 time out */ + u32 width; /* 0x0c bus width */ + u32 blksz; /* 0x10 block size */ + u32 bytecnt; /* 0x14 byte count */ + u32 cmd; /* 0x18 command */ + u32 arg; /* 0x1c argument */ + u32 resp0; /* 0x20 response 0 */ + u32 resp1; /* 0x24 response 1 */ + u32 resp2; /* 0x28 response 2 */ + u32 resp3; /* 0x2c response 3 */ + u32 imask; /* 0x30 interrupt mask */ + u32 mint; /* 0x34 masked interrupt status */ + u32 rint; /* 0x38 raw interrupt status */ + u32 status; /* 0x3c status */ + u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ + u32 funcsel; /* 0x44 function select */ + u32 cbcr; /* 0x48 CIU byte count */ + u32 bbcr; /* 0x4c BIU byte count */ + u32 dbgc; /* 0x50 debug enable */ + u32 res0[11]; + u32 dmac; /* 0x80 internal DMA control */ + u32 dlba; /* 0x84 internal DMA descr list base address */ + u32 idst; /* 0x88 internal DMA status */ + u32 idie; /* 0x8c internal DMA interrupt enable */ + u32 chda; /* 0x90 */ + u32 cbda; /* 0x94 */ + u32 res1[26]; +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ + defined(CONFIG_MACH_SUN9I) + u32 res2[64]; +#endif + u32 fifo; /* 0x100 / 0x200 FIFO access address */ +}; + +#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) +#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) +#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) + +#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) +#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) +#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) +#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ + SUNXI_MMC_GCTRL_FIFO_RESET|\ + SUNXI_MMC_GCTRL_DMA_RESET) +#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) +#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) + +#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) +#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) +#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) +#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) +#define SUNXI_MMC_CMD_WRITE (0x1 << 10) +#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) +#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) +#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) +#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) +#define SUNXI_MMC_CMD_START (0x1 << 31) + +#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) +#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) +#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) +#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) +#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) +#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) +#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) +#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) +#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) +#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) +#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) +#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) +#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) +#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) +#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) +#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) +#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) +#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) +#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ + (SUNXI_MMC_RINT_RESP_ERROR | \ + SUNXI_MMC_RINT_RESP_CRC_ERROR | \ + SUNXI_MMC_RINT_DATA_CRC_ERROR | \ + SUNXI_MMC_RINT_RESP_TIMEOUT | \ + SUNXI_MMC_RINT_DATA_TIMEOUT | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ + SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ + SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ + SUNXI_MMC_RINT_START_BIT_ERROR | \ + SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ +#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ + (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ + SUNXI_MMC_RINT_DATA_OVER | \ + SUNXI_MMC_RINT_COMMAND_DONE | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) + +#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) +#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) +#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) +#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) +#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) +#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) +#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) + +#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) +#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) +#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) + +#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) +#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) + +#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) +#define SUNXI_MMC_COMMON_RESET (1 << 18) + +struct mmc *sunxi_mmc_init(int sdc_no); +#endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/p2wi.h b/arch/arm/include/asm/arch-sunxi/p2wi.h new file mode 100644 index 0000000000..2cf2d51c61 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/p2wi.h @@ -0,0 +1,140 @@ +/* + * Sunxi platform Push-Push i2c register definition. + * + * (c) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * + * (c)Copyright 2006-2013 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_P2WI_H +#define _SUNXI_P2WI_H + +#include + +#define P2WI_CTRL_RESET (0x1 << 0) +#define P2WI_CTRL_IRQ_EN (0x1 << 1) +#define P2WI_CTRL_TRANS_ABORT (0x1 << 6) +#define P2WI_CTRL_TRANS_START (0x1 << 7) + +#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) +#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff) +#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) +#define P2WI_CC_CLK_DIV(n) \ + __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n)) +#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) +#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7) + +#define P2WI_IRQ_TRANS_DONE (0x1 << 0) +#define P2WI_IRQ_TRANS_ERR (0x1 << 1) +#define P2WI_IRQ_LOAD_BUSY (0x1 << 2) + +#define P2WI_STAT_TRANS_DONE (0x1 << 0) +#define P2WI_STAT_TRANS_ERR (0x1 << 1) +#define P2WI_STAT_LOAD_BUSY (0x1 << 2) +#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) +#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff) +#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01 +#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02 +#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04 +#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08 +#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10 +#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20 +#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40 +#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80 +#define P2WI_STAT_TRANS_ERR_BYTE_1 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1) +#define P2WI_STAT_TRANS_ERR_BYTE_2 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2) +#define P2WI_STAT_TRANS_ERR_BYTE_3 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3) +#define P2WI_STAT_TRANS_ERR_BYTE_4 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4) +#define P2WI_STAT_TRANS_ERR_BYTE_5 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5) +#define P2WI_STAT_TRANS_ERR_BYTE_6 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6) +#define P2WI_STAT_TRANS_ERR_BYTE_7 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7) +#define P2WI_STAT_TRANS_ERR_BYTE_8 \ + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8) + +#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0) +#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff) +#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8) +#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff) +#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16) +#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff) +#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24) +#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff) +#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0) +#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff) +#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8) +#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff) +#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16) +#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff) +#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24) +#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff) + +#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0) +#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7) +#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1) +#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4) + +#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0) +#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff) +#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8) +#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff) +#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16) +#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff) +#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24) +#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff) +#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0) +#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff) +#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8) +#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff) +#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16) +#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff) +#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24) +#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff) + +#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0) +#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1) +#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2) +#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3) +#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4) +#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5) + +#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0) +#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff) +#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8) +#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff) +#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16) +#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff) +#define P2WI_PM_INIT_SEND (0x1 << 31) + +struct sunxi_p2wi_reg { + u32 ctrl; /* 0x00 control */ + u32 cc; /* 0x04 clock control */ + u32 irq; /* 0x08 interrupt */ + u32 status; /* 0x0c status */ + u32 dataddr0; /* 0x10 data address 0 */ + u32 dataddr1; /* 0x14 data address 1 */ + u32 numbytes; /* 0x18 num bytes */ + u32 data0; /* 0x1c data buffer 0 */ + u32 data1; /* 0x20 data buffer 1 */ + u32 linectrl; /* 0x24 line control */ + u32 pm; /* 0x28 power management */ +}; + +void p2wi_init(void); +int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data); +int p2wi_read(const u8 addr, u8 *data); +int p2wi_write(const u8 addr, u8 data); + +#endif /* _SUNXI_P2WI_H */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h new file mode 100644 index 0000000000..82ed541e91 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -0,0 +1,240 @@ +/* + * Sunxi A31 Power Management Unit register definition. + * + * (C) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_PRCM_H +#define _SUNXI_PRCM_H + +#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) +#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3) +#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) +#define PRCM_CPUS_CFG_PRE_DIV(n) \ + __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n)) +#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) +#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f) +#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) +#define PRCM_CPUS_CFG_POST_DIV(n) \ + __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n)) +#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) +#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3) +#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0 +#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1 +#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2 +#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3 +#define PRCM_CPUS_CFG_CLK_SRC_LOSC \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC) +#define PRCM_CPUS_CFG_CLK_SRC_HOSC \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC) +#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6) +#define PRCM_CPUS_CFG_CLK_SRC_PDIV \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV) + +#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) +#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3) +#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) +#define PRCM_APB0_RATIO_DIV(n) \ + __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n)) + +#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0) +#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1) + +#define PRCM_APB0_GATE_PIO (0x1 << 0) +#define PRCM_APB0_GATE_IR (0x1 << 1) +#define PRCM_APB0_GATE_TIMER01 (0x1 << 2) +#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ +#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ +#define PRCM_APB0_GATE_UART (0x1 << 4) +#define PRCM_APB0_GATE_1WIRE (0x1 << 5) +#define PRCM_APB0_GATE_I2C (0x1 << 6) + +#define PRCM_APB0_RESET_PIO (0x1 << 0) +#define PRCM_APB0_RESET_IR (0x1 << 1) +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) +#define PRCM_APB0_RESET_P2WI (0x1 << 3) +#define PRCM_APB0_RESET_UART (0x1 << 4) +#define PRCM_APB0_RESET_1WIRE (0x1 << 5) +#define PRCM_APB0_RESET_I2C (0x1 << 6) + +#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0) +#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1) +#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4) +#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \ + __PRCM_PLL_CTRL_USB_CLK_SRC(0x3) +#define __PRCM_PLL_CTRL_USB_CLK_0 0x0 +#define __PRCM_PLL_CTRL_USB_CLK_1 0x1 +#define __PRCM_PLL_CTRL_USB_CLK_2 0x2 +#define __PRCM_PLL_CTRL_USB_CLK_3 0x3 +#define PRCM_PLL_CTRL_USB_CLK_0 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0) +#define PRCM_PLL_CTRL_USB_CLK_1 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1) +#define PRCM_PLL_CTRL_USB_CLK_2 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2) +#define PRCM_PLL_CTRL_USB_CLK_3 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3) +#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12) +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \ + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3) +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \ + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) +#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20) +#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3) +#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0 +#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1 +#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2 +#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3 +#define PRCM_PLL_CTRL_HOSC_CLK_0 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0) +#define PRCM_PLL_CTRL_HOSC_CLK_1 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1) +#define PRCM_PLL_CTRL_HOSC_CLK_2 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2) +#define PRCM_PLL_CTRL_HOSC_CLK_3 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3) +#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24) +#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0) +#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1) +#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2) +#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3) +#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */ +#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16) +#define PRCM_PLL_CTRL_LDO_OUT_MASK \ + __PRCM_PLL_CTRL_LDO_OUT(0x7) +/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ +#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) +#define PRCM_PLL_CTRL_LDO_OUT_H(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) +#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) +#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) +#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) +#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) + +#define PRCM_CLK_1WIRE_GATE (0x1 << 31) + +#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) +#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf) +#define __PRCM_CLK_MOD0_M_X(n) (n - 1) +#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n)) +#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8) +#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7) +#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) +#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3) +#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1) +#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n)) +#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20) +#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7) +#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24) +#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7) +#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31) + +#define PRCM_APB0_RESET_PIO (0x1 << 0) +#define PRCM_APB0_RESET_IR (0x1 << 1) +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) +#define PRCM_APB0_RESET_P2WI (0x1 << 3) +#define PRCM_APB0_RESET_UART (0x1 << 4) +#define PRCM_APB0_RESET_1WIRE (0x1 << 5) +#define PRCM_APB0_RESET_I2C (0x1 << 6) + +#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8) +#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7) +#define __PRCM_CLK_OUTD_M_X() ((n) - 1) +#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n)) +#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20) +#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7) +#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1) +#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n) +#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24) +#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3) +#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0 +#define __PRCM_CLK_OUTD_SRC_LOSC 0x1 +#define __PRCM_CLK_OUTD_SRC_HOSC 0x2 +#define __PRCM_CLK_OUTD_SRC_ERR 0x3 +#define PRCM_CLK_OUTD_SRC_LOSC2 \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2) +#define PRCM_CLK_OUTD_SRC_LOSC \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC) +#define PRCM_CLK_OUTD_SRC_HOSC \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC) +#define PRCM_CLK_OUTD_SRC_ERR \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR) +#define PRCM_CLK_OUTD_EN (0x1 << 31) + +#define PRCM_CPU0_PWROFF (0x1 << 0) +#define PRCM_CPU1_PWROFF (0x1 << 1) +#define PRCM_CPU2_PWROFF (0x1 << 2) +#define PRCM_CPU3_PWROFF (0x1 << 3) +#define PRCM_CPU_ALL_PWROFF (0xf << 0) + +#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0) +#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1) +#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2) +#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3) + +#define PRCM_VDD_GPU_PWROFF (0x1 << 0) + +#define PRCM_VDD_SYS_RESET (0x1 << 0) + +#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff) + +#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff) + +#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff) + +#ifndef __ASSEMBLY__ +struct sunxi_prcm_reg { + u32 cpus_cfg; /* 0x000 */ + u8 res0[0x8]; /* 0x004 */ + u32 apb0_ratio; /* 0x00c */ + u32 cpu0_cfg; /* 0x010 */ + u32 cpu1_cfg; /* 0x014 */ + u32 cpu2_cfg; /* 0x018 */ + u32 cpu3_cfg; /* 0x01c */ + u8 res1[0x8]; /* 0x020 */ + u32 apb0_gate; /* 0x028 */ + u8 res2[0x14]; /* 0x02c */ + u32 pll_ctrl0; /* 0x040 */ + u32 pll_ctrl1; /* 0x044 */ + u8 res3[0x8]; /* 0x048 */ + u32 clk_1wire; /* 0x050 */ + u32 clk_ir; /* 0x054 */ + u8 res4[0x58]; /* 0x058 */ + u32 apb0_reset; /* 0x0b0 */ + u8 res5[0x3c]; /* 0x0b4 */ + u32 clk_outd; /* 0x0f0 */ + u8 res6[0xc]; /* 0x0f4 */ + u32 cpu_pwroff; /* 0x100 */ + u8 res7[0xc]; /* 0x104 */ + u32 vdd_sys_pwroff; /* 0x110 */ + u8 res8[0x4]; /* 0x114 */ + u32 gpu_pwroff; /* 0x118 */ + u8 res9[0x4]; /* 0x11c */ + u32 vdd_pwr_reset; /* 0x120 */ + u8 res10[0x20]; /* 0x124 */ + u32 cpu1_pwr_clamp; /* 0x144 */ + u32 cpu2_pwr_clamp; /* 0x148 */ + u32 cpu3_pwr_clamp; /* 0x14c */ + u8 res11[0x30]; /* 0x150 */ + u32 dram_pwr; /* 0x180 */ + u8 res12[0xc]; /* 0x184 */ + u32 dram_tst; /* 0x190 */ +}; + +void prcm_apb0_enable(u32 flags); +#endif /* __ASSEMBLY__ */ +#endif /* _PRCM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h new file mode 100644 index 0000000000..a8934667c4 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/rsb.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2014 Hans de Goede + * + * Based on allwinner u-boot sources rsb code which is: + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * lixiang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SUNXI_RSB_H +#define __SUNXI_RSB_H + +#include +#include + +struct sunxi_rsb_reg { + u32 ctrl; /* 0x00 */ + u32 ccr; /* 0x04 */ + u32 inte; /* 0x08 */ + u32 stat; /* 0x0c */ + u32 addr; /* 0x10 */ + u8 res0[8]; /* 0x14 */ + u32 data; /* 0x1c */ + u8 res1[4]; /* 0x20 */ + u32 lcr; /* 0x24 */ + u32 dmcr; /* 0x28 */ + u32 cmd; /* 0x2c */ + u32 devaddr; /* 0x30 */ +}; + +#define RSB_CTRL_SOFT_RST (1 << 0) +#define RSB_CTRL_START_TRANS (1 << 7) + +#define RSB_STAT_TOVER_INT (1 << 0) +#define RSB_STAT_TERR_INT (1 << 1) +#define RSB_STAT_LBSY_INT (1 << 2) + +#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00 +#define RSB_DMCR_DEVICE_MODE_START (1 << 31) + +#define RSB_CMD_BYTE_WRITE 0x4e +#define RSB_CMD_BYTE_READ 0x8b +#define RSB_CMD_SET_RTSADDR 0xe8 + +#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16) +#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0) + +int rsb_init(void); +int rsb_set_device_address(u16 device_addr, u16 runtime_addr); +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data); +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data); + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h new file mode 100644 index 0000000000..acbec46cb8 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -0,0 +1,20 @@ +/* + * This is a copy of omap3/spl.h: + * + * (C) Copyright 2012 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_ONE_NAND 3 +#define BOOT_DEVICE_MMC2 5 /*emmc*/ +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_XIPWAIT 7 +#define BOOT_DEVICE_MMC2_2 0xff +#endif diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h new file mode 100644 index 0000000000..c3e636e1d9 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include + +void sdelay(unsigned long); + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h new file mode 100644 index 0000000000..9a5e488a38 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Configuration settings for the Allwinner A10-evb board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_TIMER_H_ +#define _SUNXI_TIMER_H_ + +#ifndef __ASSEMBLY__ + +#include +#include + +/* General purpose timer */ +struct sunxi_timer { + u32 ctl; + u32 inter; + u32 val; + u8 res[4]; +}; + +/* Audio video sync*/ +struct sunxi_avs { + u32 ctl; /* 0x80 */ + u32 cnt0; /* 0x84 */ + u32 cnt1; /* 0x88 */ + u32 div; /* 0x8c */ +}; + +/* 64 bit counter */ +struct sunxi_64cnt { + u32 ctl; /* 0xa0 */ + u32 lo; /* 0xa4 */ + u32 hi; /* 0xa8 */ +}; + +/* Rtc */ +struct sunxi_rtc { + u32 ctl; /* 0x100 */ + u32 yymmdd; /* 0x104 */ + u32 hhmmss; /* 0x108 */ +}; + +/* Alarm */ +struct sunxi_alarm { + u32 ddhhmmss; /* 0x10c */ + u32 hhmmss; /* 0x110 */ + u32 en; /* 0x114 */ + u32 irqen; /* 0x118 */ + u32 irqsta; /* 0x11c */ +}; + +/* Timer general purpose register */ +struct sunxi_tgp { + u32 tgpd; +}; + +struct sunxi_timer_reg { + u32 tirqen; /* 0x00 */ + u32 tirqsta; /* 0x04 */ + u8 res1[8]; + struct sunxi_timer timer[6]; /* We have 6 timers */ + u8 res2[16]; + struct sunxi_avs avs; +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + struct sunxi_wdog wdog; /* 0x90 */ + /* XXX the following is not accurate for sun5i/sun7i */ + struct sunxi_64cnt cnt64; /* 0xa0 */ + u8 res4[0x58]; + struct sunxi_rtc rtc; + struct sunxi_alarm alarm; + struct sunxi_tgp tgp[4]; + u8 res5[8]; + u32 cpu_cfg; +#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */ + u8 res3[16]; + struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ +#endif +}; + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h new file mode 100644 index 0000000000..cb538cdc7d --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/usbc.h @@ -0,0 +1,22 @@ +/* + * Sunxi usb-controller code shared between the ehci and musb controllers + * + * Copyright (C) 2014 Roman Byshko + * + * Roman Byshko + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +extern const struct musb_platform_ops sunxi_musb_ops; + +void *sunxi_usbc_get_io_base(int index); +int sunxi_usbc_request_resources(int index); +int sunxi_usbc_free_resources(int index); +void sunxi_usbc_enable(int index); +void sunxi_usbc_disable(int index); +void sunxi_usbc_vbus_enable(int index); +void sunxi_usbc_vbus_disable(int index); diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h new file mode 100644 index 0000000000..8108be97ba --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/watchdog.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2014 + * Chen-Yu Tsai + * + * Watchdog register definitions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_WATCHDOG_H_ +#define _SUNXI_WATCHDOG_H_ + +#define WDT_CTRL_RESTART (0x1 << 0) +#define WDT_CTRL_KEY (0x0a57 << 1) + +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + +#define WDT_MODE_EN (0x1 << 0) +#define WDT_MODE_RESET_EN (0x1 << 1) + +struct sunxi_wdog { + u32 ctl; /* 0x00 */ + u32 mode; /* 0x04 */ + u32 res[2]; +}; + +#else + +#define WDT_CFG_RESET (0x1) +#define WDT_MODE_EN (0x1) + +struct sunxi_wdog { + u32 irq_en; /* 0x00 */ + u32 irq_sta; /* 0x04 */ + u32 res1[2]; + u32 ctl; /* 0x10 */ + u32 cfg; /* 0x14 */ + u32 mode; /* 0x18 */ + u32 res2; +}; + +#endif + +#endif /* _SUNXI_WATCHDOG_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index bc5851c1d0..5c8be94d97 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -65,3 +65,12 @@ int tegra_get_sku_info(void); /* Do any chip-specific cache config */ void config_cache(void); + +#if defined(CONFIG_TEGRA124) +/* Do chip-specific vpr config */ +void config_vpr(void); +#else +static inline void config_vpr(void) +{ +} +#endif diff --git a/arch/arm/include/asm/arch-tegra20/apb_misc.h b/arch/arm/include/asm/arch-tegra/apb_misc.h similarity index 87% rename from arch/arm/include/asm/arch-tegra20/apb_misc.h rename to arch/arm/include/asm/arch-tegra/apb_misc.h index f314f5acc3..a5bc092ffd 100644 --- a/arch/arm/include/asm/arch-tegra20/apb_misc.h +++ b/arch/arm/include/asm/arch-tegra/apb_misc.h @@ -11,6 +11,8 @@ struct apb_misc_pp_ctlr { u32 reserved0[2]; u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ + u32 reserved1[6]; /* 0x0c .. 0x20 */ + u32 cfg_ctl; /* 0x24 */ }; /* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index 0e698644a0..783bb3c0fa 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -24,9 +24,11 @@ void gpio_early_init(void); /* overrideable GPIO config */ * an empty stub function will be called. */ -void pin_mux_usb(void); /* overrideable USB pinmux setup */ -void pin_mux_spi(void); /* overrideable SPI pinmux setup */ -void pin_mux_nand(void); /* overrideable NAND pinmux setup */ -void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */ +void pinmux_init(void); /* overridable general pinmux setup */ +void pin_mux_usb(void); /* overridable USB pinmux setup */ +void pin_mux_spi(void); /* overridable SPI pinmux setup */ +void pin_mux_nand(void); /* overridable NAND pinmux setup */ +void pin_mux_mmc(void); /* overridable mmc pinmux setup */ +void pin_mux_display(void); /* overridable DISPLAY pinmux setup */ #endif diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 074b3bca0b..7d28e16f1c 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -11,7 +11,8 @@ /* PLL registers - there are several PLLs in the clock controller */ struct clk_pll { uint pll_base; /* the control register */ - uint pll_out[2]; /* output control */ + /* pll_out[0] is output A control, pll_out[1] is output B control */ + uint pll_out[2]; uint pll_misc; /* other misc things */ }; @@ -21,6 +22,13 @@ struct clk_pll_simple { uint pll_misc; /* other misc things */ }; +struct clk_pllm { + uint pllm_base; /* the control register */ + uint pllm_out; /* output control */ + uint pllm_misc1; /* misc1 */ + uint pllm_misc2; /* misc2 */ +}; + /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ struct clk_set_clr { uint set; @@ -38,7 +46,8 @@ enum { TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ - TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/ + TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ + TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ }; /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ @@ -47,7 +56,7 @@ struct clk_rst_ctlr { uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ uint crc_reserved0; /* reserved_0, 0x1C */ - uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ + uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ @@ -75,7 +84,21 @@ struct clk_rst_ctlr { uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ - uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */ + uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */ + + uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + + uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + + uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */ + + uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + + uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; @@ -105,10 +128,10 @@ struct clk_rst_ctlr { uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTR1L_0, 0x384 */ + uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ - uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */ + uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ @@ -142,6 +165,47 @@ struct clk_rst_ctlr { uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ + + uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ + uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ + uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ + uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ + uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ + uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ + uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ + uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ + uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ + uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ + uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ + uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ + uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ + uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ + uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ + uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ + uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ + uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ + uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ + uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ + uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ + uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ + uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ + uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ + uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ + uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ + uint crc_reserved51[1]; /* _reserved_51, 0x538 */ + uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ + uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ + uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ + uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ + uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ + uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ + uint crc_reserved52[1]; /* _reserved_52, 0x554 */ + uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ + uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ + + /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */ + uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ + uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ }; /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ @@ -160,6 +224,9 @@ struct clk_rst_ctlr { #define PLL_BASE_OVRRIDE_MASK (1U << 28) +#define PLL_LOCK_SHIFT 27 +#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) + #define PLL_DIVP_SHIFT 20 #define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) @@ -209,6 +276,20 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; +#define PLLP_OUT1_RSTN_DIS (1 << 0) +#define PLLP_OUT1_RSTN_EN (0 << 0) +#define PLLP_OUT1_CLKEN (1 << 1) +#define PLLP_OUT2_RSTN_DIS (1 << 16) +#define PLLP_OUT2_RSTN_EN (0 << 16) +#define PLLP_OUT2_CLKEN (1 << 17) + +#define PLLP_OUT3_RSTN_DIS (1 << 0) +#define PLLP_OUT3_RSTN_EN (0 << 0) +#define PLLP_OUT3_CLKEN (1 << 1) +#define PLLP_OUT4_RSTN_DIS (1 << 16) +#define PLLP_OUT4_RSTN_EN (0 << 16) +#define PLLP_OUT4_CLKEN (1 << 17) + /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ #define PLLU_POWERDOWN (1 << 16) #define PLL_ENABLE_POWERDOWN (1 << 14) @@ -219,9 +300,15 @@ enum { #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_XOBP_SHIFT 1 -#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) +/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ +#define OSC_XOE_SHIFT 0 +#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT) +#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT) +#define OSC_XOBP_SHIFT 1 +#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) +#define OSC_XOFS_SHIFT 4 +#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) +#define OSC_DRIVE_STRENGTH 7 /* * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits @@ -233,11 +320,15 @@ enum { #define OUT_CLK_DIVISOR_SHIFT 0 #define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) -#define OUT_CLK_SOURCE_SHIFT 30 -#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) +#define OUT_CLK_SOURCE_31_30_SHIFT 30 +#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT) + +#define OUT_CLK_SOURCE_31_29_SHIFT 29 +#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT) -#define OUT_CLK_SOURCE4_SHIFT 28 -#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) +/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */ +#define OUT_CLK_SOURCE_31_28_SHIFT 28 +#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT) /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ #define SCLK_SYS_STATE_SHIFT 28U @@ -290,7 +381,7 @@ enum { #define SUPER_SCLK_DIVISOR_SHIFT 0 #define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT) -/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */ +/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 #define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) #define CLK_SYS_RATE_AHB_RATE_SHIFT 4 @@ -300,23 +391,53 @@ enum { #define CLK_SYS_RATE_APB_RATE_SHIFT 0 #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) -/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */ -#define CLR_CPURESET0 (1 << 0) -#define CLR_CPURESET1 (1 << 1) -#define CLR_CPURESET2 (1 << 2) -#define CLR_CPURESET3 (1 << 3) -#define CLR_DBGRESET0 (1 << 12) -#define CLR_DBGRESET1 (1 << 13) -#define CLR_DBGRESET2 (1 << 14) -#define CLR_DBGRESET3 (1 << 15) -#define CLR_CORERESET0 (1 << 16) -#define CLR_CORERESET1 (1 << 17) -#define CLR_CORERESET2 (1 << 18) -#define CLR_CORERESET3 (1 << 19) -#define CLR_CXRESET0 (1 << 20) -#define CLR_CXRESET1 (1 << 21) -#define CLR_CXRESET2 (1 << 22) -#define CLR_CXRESET3 (1 << 23) -#define CLR_NONCPURESET (1 << 29) +/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ +#define CLR_CPURESET0 (1 << 0) +#define CLR_CPURESET1 (1 << 1) +#define CLR_CPURESET2 (1 << 2) +#define CLR_CPURESET3 (1 << 3) +#define CLR_DBGRESET0 (1 << 12) +#define CLR_DBGRESET1 (1 << 13) +#define CLR_DBGRESET2 (1 << 14) +#define CLR_DBGRESET3 (1 << 15) +#define CLR_CORERESET0 (1 << 16) +#define CLR_CORERESET1 (1 << 17) +#define CLR_CORERESET2 (1 << 18) +#define CLR_CORERESET3 (1 << 19) +#define CLR_CXRESET0 (1 << 20) +#define CLR_CXRESET1 (1 << 21) +#define CLR_CXRESET2 (1 << 22) +#define CLR_CXRESET3 (1 << 23) +#define CLR_L2RESET (1 << 24) +#define CLR_NONCPURESET (1 << 29) +#define CLR_PRESETDBG (1 << 30) + +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ +#define CLR_CPU0_CLK_STP (1 << 8) +#define CLR_CPU1_CLK_STP (1 << 9) +#define CLR_CPU2_CLK_STP (1 << 10) +#define CLR_CPU3_CLK_STP (1 << 11) + +/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ +#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) + +/* CRC_CLK_ENB_V_SET_0 0x440 */ +#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) +#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) +#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ +#define PLL_ACTIVE_POWERDOWN (1 << 12) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLLU_POWERDOWN (1 << 16) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) + +/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ +#define PLLX_IDDQ_SHIFT 3 +#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) #endif /* _TEGRA_CLK_RST_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c3174bd7fc..9d8114c4ec 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -20,6 +20,21 @@ enum clock_osc_freq { CLOCK_OSC_FREQ_COUNT, }; +/* + * Note that no Tegra clock register actually uses all of bits 31:28 as + * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in + * those cases, nothing is stored in the bits about the mux field, so it's + * safe to pretend that the mux field extends all the way to the end of the + * register. As such, the U-Boot clock driver is currently a bit lazy, and + * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps + * them all together and pretends they're all 31:28. + */ +enum { + MASK_BITS_31_30, + MASK_BITS_31_29, + MASK_BITS_31_28, +}; + #include /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 @@ -113,9 +128,9 @@ void reset_set_enable(enum periph_id periph_id, int enable); enum crc_reset_id { /* Things we can hold in reset for each CPU */ crc_rst_cpu = 1, - crc_rst_de = 1 << 2, /* What is de? */ - crc_rst_watchdog = 1 << 3, - crc_rst_debug = 1 << 4, + crc_rst_de = 1 << 4, /* What is de? */ + crc_rst_watchdog = 1 << 8, + crc_rst_debug = 1 << 12, }; /** @@ -305,4 +320,6 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); /* SoC-specific TSC init */ void arch_timer_init(void); +void tegra30_set_up_pllp(void); + #endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h index c840c08a89..7a86acb1b2 100644 --- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -20,5 +20,6 @@ #define CHIPID_TEGRA20 0x20 #define CHIPID_TEGRA30 0x30 #define CHIPID_TEGRA114 0x35 +#define CHIPID_TEGRA124 0x40 #endif /* _TEGRA_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index d97190dd7c..7334e0ccd5 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -6,6 +6,8 @@ #ifndef _TEGRA_GPIO_H_ #define _TEGRA_GPIO_H_ +#define TEGRA_GPIOS_PER_PORT 8 +#define TEGRA_PORTS_PER_BANK 4 #define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) #define GPIO_NAME_SIZE 20 /* gpio_request max label len */ @@ -14,11 +16,32 @@ #define GPIO_FULLPORT(x) ((x) >> 3) #define GPIO_BIT(x) ((x) & 0x7) -/* - * Tegra-specific GPIO API +enum tegra_gpio_init { + TEGRA_GPIO_INIT_IN, + TEGRA_GPIO_INIT_OUT0, + TEGRA_GPIO_INIT_OUT1, +}; + +struct tegra_gpio_config { + u32 gpio:16; + u32 init:2; +}; + +/** + * tegra_spl_gpio_direction_output() - set the output value of a GPIO + * + * This function is only used from SPL on seaboard, which needs to enable a + * GPIO to get the UART running. It could be done in U-Boot rather than SPL, + * but for now, this gets it working */ +int tegra_spl_gpio_direction_output(int gpio, int value); -void gpio_info(void); +/** + * Configure a list of GPIOs + * + * @param config List of GPIO configurations + * @param len Number of config items in list + */ +void gpio_config_table(const struct tegra_gpio_config *config, int len); -#define gpio_status() gpio_info() #endif /* TEGRA_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h new file mode 100644 index 0000000000..da477697bf --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2010-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA_PINMUX_H_ +#define _TEGRA_PINMUX_H_ + +#include + +/* The pullup/pulldown state of a pin group */ +enum pmux_pull { + PMUX_PULL_NORMAL = 0, + PMUX_PULL_DOWN, + PMUX_PULL_UP, +}; + +/* Defines whether a pin group is tristated or in normal operation */ +enum pmux_tristate { + PMUX_TRI_NORMAL = 0, + PMUX_TRI_TRISTATE = 1, +}; + +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +enum pmux_pin_io { + PMUX_PIN_OUTPUT = 0, + PMUX_PIN_INPUT = 1, + PMUX_PIN_NONE, +}; + +enum pmux_pin_lock { + PMUX_PIN_LOCK_DEFAULT = 0, + PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_ENABLE, +}; + +enum pmux_pin_od { + PMUX_PIN_OD_DEFAULT = 0, + PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_ENABLE, +}; + +enum pmux_pin_ioreset { + PMUX_PIN_IO_RESET_DEFAULT = 0, + PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_ENABLE, +}; + +#ifdef TEGRA_PMX_HAS_RCV_SEL +enum pmux_pin_rcv_sel { + PMUX_PIN_RCV_SEL_DEFAULT = 0, + PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_HIGH, +}; +#endif /* TEGRA_PMX_HAS_RCV_SEL */ +#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ + +/* + * This defines the configuration for a pin, including the function assigned, + * pull up/down settings and tristate settings. Having set up one of these + * you can call pinmux_config_pingroup() to configure a pin in one step. Also + * available is pinmux_config_table() to configure a list of pins. + */ +struct pmux_pingrp_config { + u32 pingrp:16; /* pin group PMUX_PINGRP_... */ + u32 func:8; /* function to assign PMUX_FUNC_... */ + u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ + u32 tristate:2; /* tristate or normal PMUX_TRI_... */ +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC + u32 io:2; /* input or output PMUX_PIN_... */ + u32 lock:2; /* lock enable/disable PMUX_PIN... */ + u32 od:2; /* open-drain or push-pull driver */ + u32 ioreset:2; /* input/output reset PMUX_PIN... */ +#ifdef TEGRA_PMX_HAS_RCV_SEL + u32 rcv_sel:2; /* select between High and Normal */ + /* VIL/VIH receivers */ +#endif +#endif +}; + +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ +void pinmux_set_tristate_input_clamping(void); +#endif + +/* Set the mux function for a pin group */ +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); + +/* Set the pull up/down feature for a pin group */ +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); + +/* Set a pin group to tristate */ +void pinmux_tristate_enable(enum pmux_pingrp pin); + +/* Set a pin group to normal (non tristate) */ +void pinmux_tristate_disable(enum pmux_pingrp pin); + +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +/* Set a pin group as input or output */ +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); +#endif + +/** + * Configure a list of pin groups + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, + int len); + +#ifdef TEGRA_PMX_HAS_DRVGRPS + +#define PMUX_SLWF_MIN 0 +#define PMUX_SLWF_MAX 3 +#define PMUX_SLWF_NONE -1 + +#define PMUX_SLWR_MIN 0 +#define PMUX_SLWR_MAX 3 +#define PMUX_SLWR_NONE -1 + +#define PMUX_DRVUP_MIN 0 +#define PMUX_DRVUP_MAX 127 +#define PMUX_DRVUP_NONE -1 + +#define PMUX_DRVDN_MIN 0 +#define PMUX_DRVDN_MAX 127 +#define PMUX_DRVDN_NONE -1 + +/* Defines a pin group cfg's low-power mode select */ +enum pmux_lpmd { + PMUX_LPMD_X8 = 0, + PMUX_LPMD_X4, + PMUX_LPMD_X2, + PMUX_LPMD_X, + PMUX_LPMD_NONE = -1, +}; + +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pmux_schmt { + PMUX_SCHMT_DISABLE = 0, + PMUX_SCHMT_ENABLE = 1, + PMUX_SCHMT_NONE = -1, +}; + +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pmux_hsm { + PMUX_HSM_DISABLE = 0, + PMUX_HSM_ENABLE = 1, + PMUX_HSM_NONE = -1, +}; + +/* + * This defines the configuration for a pin group's pad control config + */ +struct pmux_drvgrp_config { + u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ + u32 slwf:3; /* falling edge slew */ + u32 slwr:3; /* rising edge slew */ + u32 drvup:8; /* pull-up drive strength */ + u32 drvdn:8; /* pull-down drive strength */ + u32 lpmd:3; /* low-power mode selection */ + u32 schmt:2; /* schmidt enable */ + u32 hsm:2; /* high-speed mode enable */ +}; + +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, + int len); + +#endif /* TEGRA_PMX_HAS_DRVGRPS */ + +struct pmux_pingrp_desc { + u8 funcs[4]; +#if defined(CONFIG_TEGRA20) + u8 ctl_id; + u8 pull_id; +#endif /* CONFIG_TEGRA20 */ +}; + +extern const struct pmux_pingrp_desc *tegra_soc_pingroups; + +#endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index ba22236ee3..1dd3154fbc 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010,2011,2014 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -21,7 +21,11 @@ struct pmc_ctlr { uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */ +#else + uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */ +#endif uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ @@ -103,6 +107,179 @@ struct pmc_ctlr { uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ uint pmc_gate; /* _GATE_0, offset 15C */ + /* The following fields are in Tegra124 and later only */ + uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */ + uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */ + uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */ + uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */ + uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */ + uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */ + uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */ + uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */ + uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */ + uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */ + uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */ + uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */ + uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */ + uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */ + uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */ + uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */ + uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */ + uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */ + uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */ + uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */ + uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */ + uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */ + uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */ + uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */ + uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */ + uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */ + uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */ + uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */ + + uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */ + uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */ + uint pmc_reserved0; /* _RESERVED, offset 1D8 */ + uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */ + uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */ + uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */ + uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */ + uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */ + uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */ + uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */ + uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */ + uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */ + + uint pmc_todo_0[9]; /* offset 200-220 */ + uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */ + uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */ + uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */ + uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */ + uint pmc_scratch45; + uint pmc_scratch46; + uint pmc_scratch47; + uint pmc_scratch48; + uint pmc_scratch49; + uint pmc_scratch50; + uint pmc_scratch51; + uint pmc_scratch52; + uint pmc_scratch53; + uint pmc_scratch54; + uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */ + uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */ + uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */ + uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */ + uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */ + uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */ + uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */ + uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */ + uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */ + uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */ + uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */ + uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */ + uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */ + uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */ + uint pmc_secure_scratch9; + uint pmc_secure_scratch10; + uint pmc_secure_scratch11; + uint pmc_secure_scratch12; + uint pmc_secure_scratch13; + uint pmc_secure_scratch14; + uint pmc_secure_scratch15; + uint pmc_secure_scratch16; + uint pmc_secure_scratch17; + uint pmc_secure_scratch18; + uint pmc_secure_scratch19; + uint pmc_secure_scratch20; + uint pmc_secure_scratch21; + uint pmc_secure_scratch22; + uint pmc_secure_scratch23; + uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */ + uint pmc_secure_scratch25; + uint pmc_secure_scratch26; + uint pmc_secure_scratch27; + uint pmc_secure_scratch28; + uint pmc_secure_scratch29; + uint pmc_secure_scratch30; + uint pmc_secure_scratch31; + uint pmc_secure_scratch32; + uint pmc_secure_scratch33; + uint pmc_secure_scratch34; + uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */ + + uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */ + uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */ + uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */ + uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */ + uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */ + uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */ + uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */ + + uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */ + uint pmc_scratch57; + uint pmc_scratch58; + uint pmc_scratch59; + uint pmc_scratch60; + uint pmc_scratch61; + uint pmc_scratch62; + uint pmc_scratch63; + uint pmc_scratch64; + uint pmc_scratch65; + uint pmc_scratch66; + uint pmc_scratch67; + uint pmc_scratch68; + uint pmc_scratch69; + uint pmc_scratch70; + uint pmc_scratch71; + uint pmc_scratch72; + uint pmc_scratch73; + uint pmc_scratch74; + uint pmc_scratch75; + uint pmc_scratch76; + uint pmc_scratch77; + uint pmc_scratch78; + uint pmc_scratch79; + uint pmc_scratch80; + uint pmc_scratch81; + uint pmc_scratch82; + uint pmc_scratch83; + uint pmc_scratch84; + uint pmc_scratch85; + uint pmc_scratch86; + uint pmc_scratch87; + uint pmc_scratch88; + uint pmc_scratch89; + uint pmc_scratch90; + uint pmc_scratch91; + uint pmc_scratch92; + uint pmc_scratch93; + uint pmc_scratch94; + uint pmc_scratch95; + uint pmc_scratch96; + uint pmc_scratch97; + uint pmc_scratch98; + uint pmc_scratch99; + uint pmc_scratch100; + uint pmc_scratch101; + uint pmc_scratch102; + uint pmc_scratch103; + uint pmc_scratch104; + uint pmc_scratch105; + uint pmc_scratch106; + uint pmc_scratch107; + uint pmc_scratch108; + uint pmc_scratch109; + uint pmc_scratch110; + uint pmc_scratch111; + uint pmc_scratch112; + uint pmc_scratch113; + uint pmc_scratch114; + uint pmc_scratch115; + uint pmc_scratch116; + uint pmc_scratch117; + uint pmc_scratch118; + uint pmc_scratch119; + uint pmc_scratch1_eco; /* offset 700 */ }; #define CPU_PWRED 1 @@ -114,11 +291,101 @@ struct pmc_ctlr { #define CPUPWRREQ_OE (1 << 16) #define CPUPWRREQ_POL (1 << 15) -#define CRAILID (0) -#define CE0ID (14) -#define C0NCID (15) -#define CRAIL (1 << CRAILID) -#define CE0 (1 << CE0ID) -#define C0NC (1 << C0NCID) +#define CRAIL 0 +#define CE0 14 +#define C0NC 15 + +#define PMC_XOFS_SHIFT 1 +#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) + +#if defined(CONFIG_TEGRA114) +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 2 +#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) +#elif defined(CONFIG_TEGRA124) +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 3 +#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT) +#endif + +#define MULT_1 0 +#define MULT_2 1 +#define MULT_4 2 +#define MULT_8 3 +#if defined(CONFIG_TEGRA124) +#define MULT_16 4 +#endif + +#define AMAP_WRITE_SHIFT 20 +#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) + +/* SEC_DISABLE_0, 0x04 */ +#define SEC_DISABLE_WRITE0_ON (1 << 4) +#define SEC_DISABLE_READ0_ON (1 << 5) +#define SEC_DISABLE_WRITE1_ON (1 << 6) +#define SEC_DISABLE_READ1_ON (1 << 7) +#define SEC_DISABLE_WRITE2_ON (1 << 8) +#define SEC_DISABLE_READ2_ON (1 << 9) +#define SEC_DISABLE_WRITE3_ON (1 << 10) +#define SEC_DISABLE_READ3_ON (1 << 11) +#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) + +/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ +#define PWRGATE_TOGGLE_PARTID_CRAIL 0 +#define PWRGATE_TOGGLE_PARTID_TD 1 +#define PWRGATE_TOGGLE_PARTID_VE 2 +#define PWRGATE_TOGGLE_PARTID_PCX 3 +#define PWRGATE_TOGGLE_PARTID_VDE 4 +#define PWRGATE_TOGGLE_PARTID_L2C 5 +#define PWRGATE_TOGGLE_PARTID_MPE 6 +#define PWRGATE_TOGGLE_PARTID_HEG 7 +#define PWRGATE_TOGGLE_PARTID_SAX 8 +#define PWRGATE_TOGGLE_PARTID_CE1 9 +#define PWRGATE_TOGGLE_PARTID_CE2 10 +#define PWRGATE_TOGGLE_PARTID_CE3 11 +#define PWRGATE_TOGGLE_PARTID_CELP 12 +#define PWRGATE_TOGGLE_PARTID_CE0 14 +#define PWRGATE_TOGGLE_PARTID_C0NC 15 +#define PWRGATE_TOGGLE_PARTID_C1NC 16 +#define PWRGATE_TOGGLE_PARTID_SOR 17 +#define PWRGATE_TOGGLE_PARTID_DIS 18 +#define PWRGATE_TOGGLE_PARTID_DISB 19 +#define PWRGATE_TOGGLE_PARTID_XUSBA 20 +#define PWRGATE_TOGGLE_PARTID_XUSBB 21 +#define PWRGATE_TOGGLE_PARTID_XUSBC 22 +#define PWRGATE_TOGGLE_PARTID_VIC 23 +#define PWRGATE_TOGGLE_PARTID_IRAM 24 +#define PWRGATE_TOGGLE_START (1 << 8) + +/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ +#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) +#define PWRGATE_STATUS_TD_ENABLE (1 << 1) +#define PWRGATE_STATUS_VE_ENABLE (1 << 2) +#define PWRGATE_STATUS_PCX_ENABLE (1 << 3) +#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) +#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) +#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) +#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) +#define PWRGATE_STATUS_SAX_ENABLE (1 << 8) +#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) +#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) +#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) +#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) +#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) +#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) +#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) +#define PWRGATE_STATUS_SOR_ENABLE (1 << 17) +#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) +#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) +#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) +#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) +#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) +#define PWRGATE_STATUS_VIC_ENABLE (1 << 23) +#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24) + +/* APBDEV_PMC_CNTRL2_0 0x440 */ +#define HOLD_CKE_LOW_EN (1 << 12) #endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/include/asm/arch-tegra/powergate.h new file mode 100644 index 0000000000..130b58bef1 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/powergate.h @@ -0,0 +1,38 @@ +#ifndef _TEGRA_POWERGATE_H_ +#define _TEGRA_POWERGATE_H_ + +#include + +enum tegra_powergate { + TEGRA_POWERGATE_CPU, + TEGRA_POWERGATE_3D, + TEGRA_POWERGATE_VENC, + TEGRA_POWERGATE_PCIE, + TEGRA_POWERGATE_VDEC, + TEGRA_POWERGATE_L2, + TEGRA_POWERGATE_MPE, + TEGRA_POWERGATE_HEG, + TEGRA_POWERGATE_SATA, + TEGRA_POWERGATE_CPU1, + TEGRA_POWERGATE_CPU2, + TEGRA_POWERGATE_CPU3, + TEGRA_POWERGATE_CELP, + TEGRA_POWERGATE_3D1, + TEGRA_POWERGATE_CPU0, + TEGRA_POWERGATE_C0NC, + TEGRA_POWERGATE_C1NC, + TEGRA_POWERGATE_SOR, + TEGRA_POWERGATE_DIS, + TEGRA_POWERGATE_DISB, + TEGRA_POWERGATE_XUSBA, + TEGRA_POWERGATE_XUSBB, + TEGRA_POWERGATE_XUSBC, + TEGRA_POWERGATE_VIC, + TEGRA_POWERGATE_IRAM, +}; + +int tegra_powergate_sequence_power_up(enum tegra_powergate id, + enum periph_id periph); +int tegra_powergate_power_off(enum tegra_powergate id); + +#endif diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 25d1fc4db1..d63af0e5fd 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -34,7 +34,12 @@ #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ + defined(CONFIG_TEGRA114) #define NV_PA_CSITE_BASE 0x70040000 +#else +#define NV_PA_CSITE_BASE 0x70800000 +#endif #define TEGRA_USB_ADDR_MASK 0xFFFFC000 #define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE @@ -65,8 +70,10 @@ enum { SKU_ID_T25E = 0x1c, SKU_ID_T33 = 0x80, SKU_ID_T30 = 0x81, /* Cardhu value */ + SKU_ID_TM30MQS_P_A3 = 0xb1, SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ SKU_ID_T114_1 = 0x01, + SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */ }; /* @@ -80,6 +87,7 @@ enum { TEGRA_SOC_T25, TEGRA_SOC_T30, TEGRA_SOC_T114, + TEGRA_SOC_T124, TEGRA_SOC_CNT, TEGRA_SOC_UNKNOWN = -1, diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 853e59bb6e..eeeb247d5d 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -124,6 +124,8 @@ struct i2c_ctlr { /* bit fields definitions for IO Packet Header 3 format */ #define PKT_HDR3_READ_MODE_SHIFT 19 #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) +#define PKT_HDR3_REPEAT_START_SHIFT 16 +#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT) #define PKT_HDR3_SLAVE_ADDR_SHIFT 0 #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) @@ -165,6 +167,6 @@ struct i2c_ctlr { * * @return number of bus, or -1 if there is no DVC active */ -int tegra_i2c_get_dvc_bus_num(void); +int tegra_i2c_get_dvc_bus(struct udevice **busp); #endif /* _TEGRA_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index b6896afd96..a20bdaa618 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -10,8 +10,10 @@ #define __TEGRA_MMC_H_ #include +#include -#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ +/* for mmc_config definition */ +#include #ifndef __ASSEMBLY__ struct tegra_mmc { @@ -133,11 +135,12 @@ struct mmc_host { int enabled; /* 1 to enable, 0 to disable */ int width; /* Bus Width, 1, 4 or 8 */ enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ - struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */ - struct fdt_gpio_state pwr_gpio; /* Power GPIO */ - struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */ + struct gpio_desc cd_gpio; /* Change Detect GPIO */ + struct gpio_desc pwr_gpio; /* Power GPIO */ + struct gpio_desc wp_gpio; /* Write Protect GPIO */ unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ + struct mmc_config cfg; /* mmc configuration */ }; void pad_init_mmc(struct mmc_host *host); diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index f66257c9f7..c817088fa5 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -8,6 +8,189 @@ #ifndef _TEGRA_USB_H_ #define _TEGRA_USB_H_ +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[2]; + +#ifdef CONFIG_TEGRA20 + /* 0x130 */ + uint reserved4_2[4]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; +#else + /* 0x130 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x140 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint reserved5_1; + + /* 0x150 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; + uint icusb_ctrl; + + /* 0x160 */ + uint ulpi_viewport; + uint reserved7[3]; + + /* 0x170 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x190 */ + uint reserved9[8]; + + /* 0x1b0 */ + uint reserved10; + uint hostpc1_devlc; + uint reserved10_1[2]; + + /* 0x1c0 */ + uint reserved10_2[4]; + + /* 0x1d0 */ + uint reserved10_3[4]; + + /* 0x1e0 */ + uint reserved10_4[4]; + + /* 0x1f0 */ + uint reserved10_5; + uint otgsc; + uint usb_mode; + uint reserved10_6; + + /* 0x200 */ + uint endpt_nak; + uint endpt_nak_enable; + uint endpt_setup_stat; + uint reserved11_1[0x7D]; +#endif + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + +#ifdef CONFIG_TEGRA20 + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[4]; + + /* 0x424 */ + uint ulpi_timing_ctrl_0; + uint ulpi_timing_ctrl_1; + uint reserved13[53]; +#else + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; +#endif + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + /* USB1_LEGACY_CTRL */ #define USB1_NO_LEGACY_MODE 1 @@ -24,22 +207,46 @@ #define USB_PHY_CLK_VALID (1 << 7) #define USB_SUSP_CLR (1 << 5) +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) /* USB2_IF_USB_SUSP_CTRL_0 */ #define ULPI_PHY_ENB (1 << 13) +/* USB2_IF_ULPI_TIMING_CTRL_0 */ +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) +#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) + +/* USB2_IF_ULPI_TIMING_CTRL_1 */ +#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) +#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) +#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) +#endif + /* USBx_UTMIP_MISC_CFG0 */ #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) /* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* + * Tegra 3 and later: Moved to Clock and Reset register space, see + * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 + */ #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 #define UTMIP_PLLU_STABLE_COUNT_MASK \ (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +/* + * Tegra 3 and later: Moved to Clock and Reset register space, see + * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 + */ #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) -#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) /* USBx_UTMIP_PLL_CFG1_0 */ +/* Tegra 3 and later: Moved to Clock and Reset register space */ #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) @@ -91,11 +298,23 @@ /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ #define IC_ENB1 (1 << 3) -/* PORTSC1, USB1, defined for Tegra20 */ +#ifdef CONFIG_TEGRA20 +/* PORTSC1, USB1 */ #define PTS1_SHIFT 31 #define PTS1_MASK (1 << PTS1_SHIFT) #define STS1 (1 << 30) +/* PORTSC, USB2, USB3 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) +#define STS (1 << 29) +#else +/* USB2D_HOSTPC1_DEVLC_0 */ +#define PTS_SHIFT 29 +#define PTS_MASK (0x7U << PTS_SHIFT) +#define STS (1 << 28) +#endif + #define PTS_UTMI 0 #define PTS_RESERVED 1 #define PTS_ULPI 2 @@ -130,9 +349,10 @@ /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ #define VBUS_VLD_STS (1 << 26) - +#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) +#define VBUS_B_SESS_VLD_SW_EN (1 << 11) /* Setup USB on the board */ -int board_usb_init(const void *blob); +int usb_process_devicetree(const void *blob); #endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h new file mode 100644 index 0000000000..b4b4c8ba4d --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h @@ -0,0 +1,24 @@ +#ifndef _TEGRA_XUSB_PADCTL_H_ +#define _TEGRA_XUSB_PADCTL_H_ + +struct tegra_xusb_phy; + +/** + * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY + * @type: the type of PHY to obtain + * + * The type of PHY varies between SoC generations. Typically there are XUSB, + * PCIe and SATA PHYs, though not all generations support all of them. The + * value of type can usually be directly parsed from a device tree. + * + * Return: a pointer to the PHY or NULL if no such PHY exists + */ +struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); + +void tegra_xusb_padctl_init(const void *fdt); +int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); +int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); +int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); +int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy); + +#endif diff --git a/arch/arm/include/asm/arch-tegra114/mc.h b/arch/arm/include/asm/arch-tegra114/mc.h new file mode 100644 index 0000000000..044b1e0b39 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/mc.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA114_MC_H_ +#define _TEGRA114_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA114_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 9c22c08b6e..b86562ac6d 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -1,616 +1,321 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_PINMUX_H_ #define _TEGRA114_PINMUX_H_ -/* - * Pin groups which we adjust. There are three basic attributes of each pin - * group which use this enum: - * - * - function - * - pullup / pulldown - * - tristate or normal - */ enum pmux_pingrp { - PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ - PINGRP_ULPI_DATA1, - PINGRP_ULPI_DATA2, - PINGRP_ULPI_DATA3, - PINGRP_ULPI_DATA4, - PINGRP_ULPI_DATA5, - PINGRP_ULPI_DATA6, - PINGRP_ULPI_DATA7, - PINGRP_ULPI_CLK, - PINGRP_ULPI_DIR, - PINGRP_ULPI_NXT, - PINGRP_ULPI_STP, - PINGRP_DAP3_FS, - PINGRP_DAP3_DIN, - PINGRP_DAP3_DOUT, - PINGRP_DAP3_SCLK, - PINGRP_GPIO_PV0, - PINGRP_GPIO_PV1, - PINGRP_SDMMC1_CLK, - PINGRP_SDMMC1_CMD, - PINGRP_SDMMC1_DAT3, - PINGRP_SDMMC1_DAT2, - PINGRP_SDMMC1_DAT1, - PINGRP_SDMMC1_DAT0, - PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3, - PINGRP_CLK2_REQ, - PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41, - PINGRP_DDC_SCL, - PINGRP_DDC_SDA, - PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19, - PINGRP_UART2_TXD, - PINGRP_UART2_RTS_N, - PINGRP_UART2_CTS_N, - PINGRP_UART3_TXD, - PINGRP_UART3_RXD, - PINGRP_UART3_CTS_N, - PINGRP_UART3_RTS_N, - PINGRP_GPIO_PU0, - PINGRP_GPIO_PU1, - PINGRP_GPIO_PU2, - PINGRP_GPIO_PU3, - PINGRP_GPIO_PU4, - PINGRP_GPIO_PU5, - PINGRP_GPIO_PU6, - PINGRP_GEN1_I2C_SDA, - PINGRP_GEN1_I2C_SCL, - PINGRP_DAP4_FS, - PINGRP_DAP4_DIN, - PINGRP_DAP4_DOUT, - PINGRP_DAP4_SCLK, - PINGRP_CLK3_OUT, - PINGRP_CLK3_REQ, - PINGRP_GMI_WP_N, - PINGRP_GMI_IORDY, - PINGRP_GMI_WAIT, - PINGRP_GMI_ADV_N, - PINGRP_GMI_CLK, - PINGRP_GMI_CS0_N, - PINGRP_GMI_CS1_N, - PINGRP_GMI_CS2_N, - PINGRP_GMI_CS3_N, - PINGRP_GMI_CS4_N, - PINGRP_GMI_CS6_N, - PINGRP_GMI_CS7_N, - PINGRP_GMI_AD0, - PINGRP_GMI_AD1, - PINGRP_GMI_AD2, - PINGRP_GMI_AD3, - PINGRP_GMI_AD4, - PINGRP_GMI_AD5, - PINGRP_GMI_AD6, - PINGRP_GMI_AD7, - PINGRP_GMI_AD8, - PINGRP_GMI_AD9, - PINGRP_GMI_AD10, - PINGRP_GMI_AD11, - PINGRP_GMI_AD12, - PINGRP_GMI_AD13, - PINGRP_GMI_AD14, - PINGRP_GMI_AD15, - PINGRP_GMI_A16, - PINGRP_GMI_A17, - PINGRP_GMI_A18, - PINGRP_GMI_A19, - PINGRP_GMI_WR_N, - PINGRP_GMI_OE_N, - PINGRP_GMI_DQS, - PINGRP_GMI_RST_N, - PINGRP_GEN2_I2C_SCL, - PINGRP_GEN2_I2C_SDA, - PINGRP_SDMMC4_CLK, - PINGRP_SDMMC4_CMD, - PINGRP_SDMMC4_DAT0, - PINGRP_SDMMC4_DAT1, - PINGRP_SDMMC4_DAT2, - PINGRP_SDMMC4_DAT3, - PINGRP_SDMMC4_DAT4, - PINGRP_SDMMC4_DAT5, - PINGRP_SDMMC4_DAT6, - PINGRP_SDMMC4_DAT7, - PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2, - PINGRP_GPIO_PCC1, - PINGRP_GPIO_PBB0, - PINGRP_CAM_I2C_SCL, - PINGRP_CAM_I2C_SDA, - PINGRP_GPIO_PBB3, - PINGRP_GPIO_PBB4, - PINGRP_GPIO_PBB5, - PINGRP_GPIO_PBB6, - PINGRP_GPIO_PBB7, - PINGRP_GPIO_PCC2, - PINGRP_JTAG_RTCK, - PINGRP_PWR_I2C_SCL, - PINGRP_PWR_I2C_SDA, - PINGRP_KB_ROW0, - PINGRP_KB_ROW1, - PINGRP_KB_ROW2, - PINGRP_KB_ROW3, - PINGRP_KB_ROW4, - PINGRP_KB_ROW5, - PINGRP_KB_ROW6, - PINGRP_KB_ROW7, - PINGRP_KB_ROW8, - PINGRP_KB_ROW9, - PINGRP_KB_ROW10, - PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6, - PINGRP_KB_COL1, - PINGRP_KB_COL2, - PINGRP_KB_COL3, - PINGRP_KB_COL4, - PINGRP_KB_COL5, - PINGRP_KB_COL6, - PINGRP_KB_COL7, - PINGRP_CLK_32K_OUT, - PINGRP_SYS_CLK_REQ, - PINGRP_CORE_PWR_REQ, - PINGRP_CPU_PWR_REQ, - PINGRP_PWR_INT_N, - PINGRP_CLK_32K_IN, - PINGRP_OWR, - PINGRP_DAP1_FS, - PINGRP_DAP1_DIN, - PINGRP_DAP1_DOUT, - PINGRP_DAP1_SCLK, - PINGRP_CLK1_REQ, - PINGRP_CLK1_OUT, - PINGRP_SPDIF_IN, - PINGRP_SPDIF_OUT, - PINGRP_DAP2_FS, - PINGRP_DAP2_DIN, - PINGRP_DAP2_DOUT, - PINGRP_DAP2_SCLK, - PINGRP_DVFS_PWM, - PINGRP_GPIO_X1_AUD, - PINGRP_GPIO_X3_AUD, - PINGRP_DVFS_CLK, - PINGRP_GPIO_X4_AUD, - PINGRP_GPIO_X5_AUD, - PINGRP_GPIO_X6_AUD, - PINGRP_GPIO_X7_AUD, - PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3, - PINGRP_SDMMC3_CMD, - PINGRP_SDMMC3_DAT0, - PINGRP_SDMMC3_DAT1, - PINGRP_SDMMC3_DAT2, - PINGRP_SDMMC3_DAT3, - PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */ - PINGRP_SDMMC1_WP_N, - PINGRP_SDMMC3_CD_N, - PINGRP_GPIO_W2_AUD, - PINGRP_GPIO_W3_AUD, - PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */ - PINGRP_USB_VBUS_EN1, - PINGRP_SDMMC3_CLK_LB_IN, - PINGRP_SDMMC3_CLK_LB_OUT, - PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2, - PINGRP_COUNT, + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_GMI_WP_N_PC7, + PMUX_PINGRP_GMI_IORDY_PI5, + PMUX_PINGRP_GMI_WAIT_PI7, + PMUX_PINGRP_GMI_ADV_N_PK0, + PMUX_PINGRP_GMI_CLK_PK1, + PMUX_PINGRP_GMI_CS0_N_PJ0, + PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_PINGRP_GMI_CS2_N_PK3, + PMUX_PINGRP_GMI_CS3_N_PK4, + PMUX_PINGRP_GMI_CS4_N_PK2, + PMUX_PINGRP_GMI_CS6_N_PI3, + PMUX_PINGRP_GMI_CS7_N_PI6, + PMUX_PINGRP_GMI_AD0_PG0, + PMUX_PINGRP_GMI_AD1_PG1, + PMUX_PINGRP_GMI_AD2_PG2, + PMUX_PINGRP_GMI_AD3_PG3, + PMUX_PINGRP_GMI_AD4_PG4, + PMUX_PINGRP_GMI_AD5_PG5, + PMUX_PINGRP_GMI_AD6_PG6, + PMUX_PINGRP_GMI_AD7_PG7, + PMUX_PINGRP_GMI_AD8_PH0, + PMUX_PINGRP_GMI_AD9_PH1, + PMUX_PINGRP_GMI_AD10_PH2, + PMUX_PINGRP_GMI_AD11_PH3, + PMUX_PINGRP_GMI_AD12_PH4, + PMUX_PINGRP_GMI_AD13_PH5, + PMUX_PINGRP_GMI_AD14_PH6, + PMUX_PINGRP_GMI_AD15_PH7, + PMUX_PINGRP_GMI_A16_PJ7, + PMUX_PINGRP_GMI_A17_PB0, + PMUX_PINGRP_GMI_A18_PB1, + PMUX_PINGRP_GMI_A19_PK7, + PMUX_PINGRP_GMI_WR_N_PI0, + PMUX_PINGRP_GMI_OE_N_PI1, + PMUX_PINGRP_GMI_DQS_P_PJ3, + PMUX_PINGRP_GMI_RST_N_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4), + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_SYS_CLK_REQ_PZ5, + PMUX_PINGRP_CORE_PWR_REQ, + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_CLK1_REQ_PEE2, + PMUX_PINGRP_CLK1_OUT_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_DVFS_PWM_PX0, + PMUX_PINGRP_GPIO_X1_AUD_PX1, + PMUX_PINGRP_GPIO_X3_AUD_PX3, + PMUX_PINGRP_DVFS_CLK_PX2, + PMUX_PINGRP_GPIO_X4_AUD_PX4, + PMUX_PINGRP_GPIO_X5_AUD_PX5, + PMUX_PINGRP_GPIO_X6_AUD_PX6, + PMUX_PINGRP_GPIO_X7_AUD_PX7, + PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), + PMUX_PINGRP_SDMMC1_WP_N_PV3, + PMUX_PINGRP_SDMMC3_CD_N_PV2, + PMUX_PINGRP_GPIO_W2_AUD_PW2, + PMUX_PINGRP_GPIO_W3_AUD_PW3, + PMUX_PINGRP_USB_VBUS_EN0_PN4, + PMUX_PINGRP_USB_VBUS_EN1_PN5, + PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, + PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, + PMUX_PINGRP_GMI_CLK_LB, + PMUX_PINGRP_RESET_OUT_N, + PMUX_PINGRP_COUNT, }; -enum pdrive_pingrp { - PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ - PDRIVE_PINGROUP_AO2, - PDRIVE_PINGROUP_AT1, - PDRIVE_PINGROUP_AT2, - PDRIVE_PINGROUP_AT3, - PDRIVE_PINGROUP_AT4, - PDRIVE_PINGROUP_AT5, - PDRIVE_PINGROUP_CDEV1, - PDRIVE_PINGROUP_CDEV2, - PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */ - PDRIVE_PINGROUP_DAP2, - PDRIVE_PINGROUP_DAP3, - PDRIVE_PINGROUP_DAP4, - PDRIVE_PINGROUP_DBG, - PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */ - PDRIVE_PINGROUP_SPI, - PDRIVE_PINGROUP_UAA, - PDRIVE_PINGROUP_UAB, - PDRIVE_PINGROUP_UART2, - PDRIVE_PINGROUP_UART3, - PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */ - PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */ - PDRIVE_PINGROUP_GMA, - PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */ - PDRIVE_PINGROUP_GMF, - PDRIVE_PINGROUP_GMG, - PDRIVE_PINGROUP_GMH, - PDRIVE_PINGROUP_OWR, - PDRIVE_PINGROUP_UAD, - PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ - PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ - PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */ - PDRIVE_PINGROUP_DAP5, - PDRIVE_PINGROUP_VBUS, - PDRIVE_PINGROUP_AO3, - PDRIVE_PINGROUP_HVC, - PDRIVE_PINGROUP_SDIO4, - PDRIVE_PINGROUP_AO0, - PDRIVE_PINGROUP_COUNT, +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_DAP1 = (0x28 / 4), + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_SDIO3 = (0x48 / 4), + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_DDC = (0x94 / 4), + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GME = (0xa8 / 4), + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_DEV3 = (0xc4 / 4), + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_AT6 = (0x12c / 4), + PMUX_DRVGRP_DAP5, + PMUX_DRVGRP_USB_VBUS_EN, + PMUX_DRVGRP_AO3, + PMUX_DRVGRP_HV0, + PMUX_DRVGRP_SDIO4, + PMUX_DRVGRP_AO0, + PMUX_DRVGRP_COUNT, }; -/* - * Functions which can be assigned to each of the pin groups. The values here - * bear no relation to the values programmed into pinmux registers and are - * purely a convenience. The translation is done through a table search. - */ enum pmux_func { - PMUX_FUNC_AHB_CLK, - PMUX_FUNC_APB_CLK, - PMUX_FUNC_AUDIO_SYNC, - PMUX_FUNC_CRT, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DAP3, - PMUX_FUNC_DAP4, - PMUX_FUNC_DAP5, - PMUX_FUNC_DISPA, - PMUX_FUNC_DISPB, - PMUX_FUNC_EMC_TEST0_DLL, - PMUX_FUNC_EMC_TEST1_DLL, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_INT, - PMUX_FUNC_HDMI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_IDE, - PMUX_FUNC_KBC, - PMUX_FUNC_MIO, - PMUX_FUNC_MIPI_HS, - PMUX_FUNC_NAND, - PMUX_FUNC_OSC, - PMUX_FUNC_OWR, - PMUX_FUNC_PCIE, - PMUX_FUNC_PLLA_OUT, - PMUX_FUNC_PLLC_OUT1, - PMUX_FUNC_PLLM_OUT1, - PMUX_FUNC_PLLP_OUT2, - PMUX_FUNC_PLLP_OUT3, - PMUX_FUNC_PLLP_OUT4, - PMUX_FUNC_PWM, - PMUX_FUNC_PWR_INTR, - PMUX_FUNC_PWR_ON, - PMUX_FUNC_RTCK, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SFLASH, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI2_ALT, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_TRACE, - PMUX_FUNC_TWC, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_UARTE, - PMUX_FUNC_ULPI, - PMUX_FUNC_VI, - PMUX_FUNC_VI_SENSOR_CLK, - PMUX_FUNC_XIO, - /* End of Tegra2 MUX selectors */ + PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, PMUX_FUNC_CEC, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_CLK, PMUX_FUNC_CLK12, + PMUX_FUNC_CPU, PMUX_FUNC_DAP, - PMUX_FUNC_DAPSDMMC2, - PMUX_FUNC_DDR, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYA_ALT, + PMUX_FUNC_DISPLAYB, PMUX_FUNC_DTV, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT2, - PMUX_FUNC_VI_ALT3, PMUX_FUNC_EMC_DLL, PMUX_FUNC_EXTPERIPH1, PMUX_FUNC_EXTPERIPH2, PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI, PMUX_FUNC_GMI_ALT, PMUX_FUNC_HDA, PMUX_FUNC_HSI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, PMUX_FUNC_I2C4, - PMUX_FUNC_I2C5, PMUX_FUNC_I2CPWR, PMUX_FUNC_I2S0, PMUX_FUNC_I2S1, PMUX_FUNC_I2S2, PMUX_FUNC_I2S3, PMUX_FUNC_I2S4, + PMUX_FUNC_IRDA, + PMUX_FUNC_KBC, + PMUX_FUNC_NAND, PMUX_FUNC_NAND_ALT, - PMUX_FUNC_POPSDIO4, - PMUX_FUNC_POPSDMMC4, + PMUX_FUNC_OWR, + PMUX_FUNC_PMI, PMUX_FUNC_PWM0, PMUX_FUNC_PWM1, PMUX_FUNC_PWM2, PMUX_FUNC_PWM3, - PMUX_FUNC_SATA, + PMUX_FUNC_PWRON, + PMUX_FUNC_RESET_OUT_N, + PMUX_FUNC_RTCK, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SOC, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, PMUX_FUNC_SPI5, PMUX_FUNC_SPI6, PMUX_FUNC_SYSCLK, + PMUX_FUNC_TRACE, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_ULPI, + PMUX_FUNC_USB, PMUX_FUNC_VGP1, PMUX_FUNC_VGP2, PMUX_FUNC_VGP3, PMUX_FUNC_VGP4, PMUX_FUNC_VGP5, PMUX_FUNC_VGP6, - /* End of Tegra3 MUX selectors */ - PMUX_FUNC_USB, - PMUX_FUNC_SOC, - PMUX_FUNC_CPU, - PMUX_FUNC_CLK, - PMUX_FUNC_PWRON, - PMUX_FUNC_PMI, - PMUX_FUNC_CLDVFS, - PMUX_FUNC_RESET_OUT_N, - /* End of Tegra114 MUX selectors */ - - PMUX_FUNC_SAFE, - PMUX_FUNC_MAX, - - PMUX_FUNC_INVALID = 0x4000, - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, -}; - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \ - || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) - -/* return 1 if a pingrp is in range */ -#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; -/* return 1 if a pin_pupd_is in range */ -#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ - ((pupd) <= PMUX_PULL_UP)) - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; -/* return 1 if a pin_tristate_is in range */ -#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \ - && ((tristate) <= PMUX_TRI_TRISTATE)) - -enum pmux_pin_io { - PMUX_PIN_OUTPUT = 0, - PMUX_PIN_INPUT = 1, - PMUX_PIN_NONE, -}; -/* return 1 if a pin_io_is in range */ -#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ - ((io) <= PMUX_PIN_INPUT)) - -enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, - PMUX_PIN_LOCK_ENABLE, -}; -/* return 1 if a pin_lock is in range */ -#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ - ((lock) <= PMUX_PIN_LOCK_ENABLE)) - -enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, - PMUX_PIN_OD_ENABLE, -}; -/* return 1 if a pin_od is in range */ -#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ - ((od) <= PMUX_PIN_OD_ENABLE)) - -enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, - PMUX_PIN_IO_RESET_ENABLE, -}; -/* return 1 if a pin_ioreset_is in range */ -#define pmux_pin_ioreset_isvalid(ioreset) \ - (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ - ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) - -enum pmux_pin_rcv_sel { - PMUX_PIN_RCV_SEL_DEFAULT = 0, - PMUX_PIN_RCV_SEL_NORMAL, - PMUX_PIN_RCV_SEL_HIGH, -}; -/* return 1 if a pin_rcv_sel_is in range */ -#define pmux_pin_rcv_sel_isvalid(rcv_sel) \ - (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \ - ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) - -/* Available power domains used by pin groups */ -enum pmux_vddio { - PMUX_VDDIO_BB = 0, - PMUX_VDDIO_LCD, - PMUX_VDDIO_VI, - PMUX_VDDIO_UART, - PMUX_VDDIO_DDR, - PMUX_VDDIO_NAND, - PMUX_VDDIO_SYS, - PMUX_VDDIO_AUDIO, - PMUX_VDDIO_SD, - PMUX_VDDIO_CAM, - PMUX_VDDIO_GMI, - PMUX_VDDIO_PEXCTL, - PMUX_VDDIO_SDMMC1, - PMUX_VDDIO_SDMMC3, - PMUX_VDDIO_SDMMC4, - - PMUX_VDDIO_NONE -}; - -#define PGRP_SLWF_NONE -1 -#define PGRP_SLWF_MAX 3 -#define PGRP_SLWR_NONE PGRP_SLWF_NONE -#define PGRP_SLWR_MAX PGRP_SLWF_MAX - -#define PGRP_DRVUP_NONE -1 -#define PGRP_DRVUP_MAX 127 -#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE -#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX - -#define PGRP_SCHMT_NONE -1 -#define PGRP_HSM_NONE PGRP_SCHMT_NONE - -/* return 1 if a padgrp is in range */ -#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) - -/* return 1 if a slew-rate rising/falling edge value is in range */ -#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \ - (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))) - -/* return 1 if a driver output pull-up/down strength code value is in range */ -#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \ - (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))) - -/* return 1 if a low-power mode value is in range */ -#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \ - (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))) - -/* Defines a pin group cfg's low-power mode select */ -enum pgrp_lpmd { - PGRP_LPMD_X8 = 0, - PGRP_LPMD_X4, - PGRP_LPMD_X2, - PGRP_LPMD_X, - PGRP_LPMD_NONE = -1, -}; - -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pgrp_schmt { - PGRP_SCHMT_DISABLE = 0, - PGRP_SCHMT_ENABLE = 1, -}; - -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pgrp_hsm { - PGRP_HSM_DISABLE = 0, - PGRP_HSM_ENABLE = 1, -}; - -/* - * This defines the configuration for a pin group's pad control config - */ -struct padctrl_config { - enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ - int slwf; /* falling edge slew */ - int slwr; /* rising edge slew */ - int drvup; /* pull-up drive strength */ - int drvdn; /* pull-down drive strength */ - enum pgrp_lpmd lpmd; /* low-power mode selection */ - enum pgrp_schmt schmt; /* schmidt enable */ - enum pgrp_hsm hsm; /* high-speed mode enable */ -}; - -/* t114 pin drive group and pin mux registers */ -#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) -#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ - PDRIVE_PINGROUP_COUNT) -struct pmux_tri_ctlr { - uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ - uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ - uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ - uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ - uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ - uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */ - uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ - - uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ - - uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ - uint pmt_reserved5[PMUX_OFFSET]; - uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */ -}; - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ - enum pmux_pin_io io; /* input or output PMUX_PIN_... */ - enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ - enum pmux_pin_od od; /* open-drain or push-pull driver */ - enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ - enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ - /* VIL/VIH receivers */ + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, }; -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(struct pingroup_config *config); - -/* Set a pin group to tristate or normal */ -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - -/* Set a pin group as input or output */ -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); - -/** - * Configure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_table(struct pingroup_config *config, int len); - -/* Set a group of pins from a table */ -void pinmux_init(void); - -/** - * Set the GP pad configs - * - * @param config List of config items - * @param len Number of config items in list - */ -void padgrp_config_table(struct padctrl_config *config, int len); +#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#define TEGRA_PMX_HAS_RCV_SEL +#define TEGRA_PMX_HAS_DRVGRPS +#include -#endif /* _TEGRA114_PINMUX_H_ */ +#endif /* _TEGRA114_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/powergate.h b/arch/arm/include/asm/arch-tegra114/powergate.h new file mode 100644 index 0000000000..260ea801b8 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA114_POWERGATE_H_ +#define _TEGRA114_POWERGATE_H_ + +#include + +#endif /* _TEGRA114_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h deleted file mode 100644 index ebb16fe1dd..0000000000 --- a/arch/arm/include/asm/arch-tegra114/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index 5d426b524a..c3d061ec58 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -19,6 +19,7 @@ #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 #include diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h deleted file mode 100644 index 48197bc27f..0000000000 --- a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra SPI controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA114_SPI_H_ -#define _TEGRA114_SPI_H_ - -#include - -int tegra114_spi_init(int *node_list, int count); -int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra114_spi_free_slave(struct spi_slave *slave); -int tegra114_spi_claim_bus(struct spi_slave *slave); -void tegra114_spi_cs_activate(struct spi_slave *slave); -void tegra114_spi_cs_deactivate(struct spi_slave *slave); -int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA114_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/usb.h b/arch/arm/include/asm/arch-tegra114/usb.h deleted file mode 100644 index d46048c8ce..0000000000 --- a/arch/arm/include/asm/arch-tegra114/usb.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA114_USB_H_ -#define _TEGRA114_USB_H_ - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[2]; - - /* 0x130 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x140 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint reserved5_1; - - /* 0x150 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; - uint icusb_ctrl; - - /* 0x160 */ - uint ulpi_viewport; - uint reserved7[3]; - - /* 0x170 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x190 */ - uint reserved9[8]; - - /* 0x1b0 */ - uint reserved10; - uint hostpc1_devlc; - uint reserved10_1[2]; - - /* 0x1c0 */ - uint reserved10_2[4]; - - /* 0x1d0 */ - uint reserved10_3[4]; - - /* 0x1e0 */ - uint reserved10_4[4]; - - /* 0x1f0 */ - uint reserved10_5; - uint otgsc; - uint usb_mode; - uint reserved10_6; - - /* 0x200 */ - uint endpt_nak; - uint endpt_nak_enable; - uint endpt_setup_stat; - uint reserved11_1[0x7D]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB2D_HOSTPC1_DEVLC_0 */ -#define PTS_SHIFT 29 -#define PTS_MASK (0x7U << PTS_SHIFT) - -#define STS (1 << 28) -#endif /* _TEGRA114_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h new file mode 100644 index 0000000000..4e48c43bbf --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/ahb.h @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_AHB_H_ +#define _TEGRA124_AHB_H_ + +struct ahb_ctlr { + u32 reserved0; /* 00h */ + u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ + u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ + u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ + u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ + u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ + u32 reserved6[2]; /* 18h, 1ch */ + u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ + u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ + u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ + u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ + u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ + u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ + u32 reserved13[2]; /* 38h, 3ch */ + u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ + u32 reserved15; /* 44h */ + u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ + u32 reserved17; /* 4ch */ + u32 gizmo_se; /* _GIZMO_SE_0, 50h */ + u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ + u32 reserved20[3]; /* 58h, 5ch, 60h */ + u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ + u32 reserved22[3]; /* 68h, 6ch, 70h */ + u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ + u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ + u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ + u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ + u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ + u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ + u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ + u32 reserved30[13]; /* 90h ~ c0h */ + u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ + u32 reserved32[5]; /* c8h ~ d8h */ + u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ + u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ + u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ + u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ + u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ + u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ + u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ + u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ + /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ + u32 arbitration_ahb_mem_wrque_mst_id; + u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ + u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ + u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ + u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ + u32 reserved46[4]; /* 110h ~ 11ch */ + u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ + u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ + u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ + u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ + u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ + u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ + /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ + u32 axicif_fastsync0_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ + u32 axicif_fastsync1_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ + u32 axicif_fastsync2_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ + u32 axicif_fastsync0_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ + u32 axicif_fastsync1_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ + u32 axicif_fastsync2_mcclk_to_cpuclk; +}; + +#define PPSB_STOPCLK_ENABLE (1 << 2) + +#define GIZ_ENABLE_SPLIT (1 << 0) +#define GIZ_ENB_FAST_REARB (1 << 2) +#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) + +#define GIZ_USB_IMMEDIATE (1 << 18) + +/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ +#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) + +#endif /* _TEGRA124_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h new file mode 100644 index 0000000000..daf9a2b351 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -0,0 +1,496 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 clock PLL tables */ + +#ifndef _TEGRA124_CLOCK_TABLES_H_ +#define _TEGRA124_CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SoC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + + CLOCK_ID_COUNT, /* number of PLLs */ + + /* + * These are clock IDs that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 (DEVICES_L) */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_COP, + PERIPH_ID_TRIGSYS, + PERIPH_ID_ISPB, + PERIPH_ID_RESERVED4, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_RESERVED13, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TCW, + PERIPH_ID_PWM, + PERIPH_ID_I2S2, + PERIPH_ID_RESERVED19, + PERIPH_ID_VI, + PERIPH_ID_RESERVED21, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_I2S0, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 (DEVICES_H) */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_RESERVED36, + PERIPH_ID_STAT_MON, + PERIPH_ID_RESERVED38, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_RESERVED43, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_I2C5, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_RESERVED53, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_MIPI_CAL, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_RESERVED60, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 (DEVICES_U) */ + PERIPH_ID_RESERVED64, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_LA, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, + PERIPH_ID_DTV, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_I2CSLOW, + PERIPH_ID_DSIB, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, + + /* 88 */ + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, + PERIPH_ID_RESERVED93, + PERIPH_ID_RESERVED94, + PERIPH_ID_XUSB_DEV, + + PERIPH_ID_VW_FIRST, + /* V word: 31:0 */ + PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, + PERIPH_ID_CPULP, + PERIPH_ID_V_RESERVED2, + PERIPH_ID_MSELECT, + PERIPH_ID_V_RESERVED4, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_I2C4, + + /* 104 */ + PERIPH_ID_SBC5, + PERIPH_ID_SBC6, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_HDA2CODEC2X, + + /* 112 */ + PERIPH_ID_ATOMICS, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, + PERIPH_ID_ACTMON, + + /* 120 */ + PERIPH_ID_EXTPERIPH1, + PERIPH_ID_EXTPERIPH2, + PERIPH_ID_EXTPERIPH3, + PERIPH_ID_OOB, + PERIPH_ID_SATA, + PERIPH_ID_HDA, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, + + /* W word: 31:0 */ + PERIPH_ID_HDA2HDMICODEC, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, + + /* 136 */ + PERIPH_ID_CEC, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, + + /* 144 */ + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_DDS, + PERIPH_ID_W_RESERVED23, + + /* 152 */ + PERIPH_ID_DP2, + PERIPH_ID_AMX0, + PERIPH_ID_ADX0, + PERIPH_ID_DVFS, + PERIPH_ID_XUSB_SS, + PERIPH_ID_W_RESERVED29, + PERIPH_ID_W_RESERVED30, + PERIPH_ID_W_RESERVED31, + + PERIPH_ID_X_FIRST, + /* X word: 31:0 */ + PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, + PERIPH_ID_X_RESERVED1, + PERIPH_ID_X_RESERVED2, + PERIPH_ID_X_RESERVED3, + PERIPH_ID_CAM_MCLK, + PERIPH_ID_CAM_MCLK2, + PERIPH_ID_I2C6, + PERIPH_ID_X_RESERVED7, + + /* 168 */ + PERIPH_ID_X_RESERVED8, + PERIPH_ID_X_RESERVED9, + PERIPH_ID_X_RESERVED10, + PERIPH_ID_VIM2_CLK, + PERIPH_ID_X_RESERVED12, + PERIPH_ID_X_RESERVED13, + PERIPH_ID_EMC_DLL, + PERIPH_ID_X_RESERVED15, + + /* 176 */ + PERIPH_ID_HDMI_AUDIO, + PERIPH_ID_CLK72MHZ, + PERIPH_ID_VIC, + PERIPH_ID_X_RESERVED19, + PERIPH_ID_ADX1, + PERIPH_ID_DPAUX, + PERIPH_ID_SOR0, + PERIPH_ID_X_RESERVED23, + + /* 184 */ + PERIPH_ID_GPU, + PERIPH_ID_AMX1, + PERIPH_ID_X_RESERVED26, + PERIPH_ID_X_RESERVED27, + PERIPH_ID_X_RESERVED28, + PERIPH_ID_X_RESERVED29, + PERIPH_ID_X_RESERVED30, + PERIPH_ID_X_RESERVED31, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* + * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want + * callers to use the PERIPH_ID for all access to peripheral clocks to avoid + * confusion bewteen PERIPH_ID_... and PERIPHC_... + * + * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be + * confusing. + */ +enum periphc_internal_id { + /* 0x00 */ + PERIPHC_I2S1, + PERIPHC_I2S2, + PERIPHC_SPDIF_OUT, + PERIPHC_SPDIF_IN, + PERIPHC_PWM, + PERIPHC_05h, + PERIPHC_SBC2, + PERIPHC_SBC3, + + /* 0x08 */ + PERIPHC_08h, + PERIPHC_I2C1, + PERIPHC_I2C5, + PERIPHC_0bh, + PERIPHC_0ch, + PERIPHC_SBC1, + PERIPHC_DISP1, + PERIPHC_DISP2, + + /* 0x10 */ + PERIPHC_10h, + PERIPHC_11h, + PERIPHC_VI, + PERIPHC_13h, + PERIPHC_SDMMC1, + PERIPHC_SDMMC2, + PERIPHC_G3D, + PERIPHC_G2D, + + /* 0x18 */ + PERIPHC_18h, + PERIPHC_SDMMC4, + PERIPHC_VFIR, + PERIPHC_1Bh, + PERIPHC_1Ch, + PERIPHC_HSI, + PERIPHC_UART1, + PERIPHC_UART2, + + /* 0x20 */ + PERIPHC_HOST1X, + PERIPHC_21h, + PERIPHC_22h, + PERIPHC_HDMI, + PERIPHC_24h, + PERIPHC_25h, + PERIPHC_I2C2, + PERIPHC_EMC, + + /* 0x28 */ + PERIPHC_UART3, + PERIPHC_29h, + PERIPHC_VI_SENSOR, + PERIPHC_2bh, + PERIPHC_2ch, + PERIPHC_SBC4, + PERIPHC_I2C3, + PERIPHC_SDMMC3, + + /* 0x30 */ + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_VDE, + PERIPHC_OWR, + PERIPHC_NOR, + PERIPHC_CSITE, + PERIPHC_I2S0, + PERIPHC_DTV, + + /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ + PERIPHC_40h = PERIPHC_VW_FIRST, + PERIPHC_MSELECT, + PERIPHC_TSENSOR, + PERIPHC_I2S3, + PERIPHC_I2S4, + PERIPHC_I2C4, + PERIPHC_SBC5, + PERIPHC_SBC6, + + /* 0x48 */ + PERIPHC_AUDIO, + PERIPHC_49h, + PERIPHC_DAM0, + PERIPHC_DAM1, + PERIPHC_DAM2, + PERIPHC_HDA2CODEC2X, + PERIPHC_ACTMON, + PERIPHC_EXTPERIPH1, + + /* 0x50 */ + PERIPHC_EXTPERIPH2, + PERIPHC_EXTPERIPH3, + PERIPHC_52h, + PERIPHC_I2CSLOW, + PERIPHC_SYS, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_59h, + PERIPHC_5ah, + PERIPHC_5bh, + PERIPHC_SATAOOB, + PERIPHC_SATA, + PERIPHC_HDA, /* 0x428 */ + PERIPHC_5fh, + + PERIPHC_X_FIRST, + /* 0x60 */ + PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ + PERIPHC_XUSB_FALCON, + PERIPHC_XUSB_FS, + PERIPHC_XUSB_CORE_DEV, + PERIPHC_XUSB_SS, + PERIPHC_CILAB, + PERIPHC_CILCD, + PERIPHC_CILE, + + /* 0x68 */ + PERIPHC_DSIA_LP, + PERIPHC_DSIB_LP, + PERIPHC_ENTROPY, + PERIPHC_DVFS_REF, + PERIPHC_DVFS_SOC, + PERIPHC_TRACECLKIN, + PERIPHC_ADX0, + PERIPHC_AMX0, + + /* 0x70 */ + PERIPHC_EMC_LATENCY, + PERIPHC_SOC_THERM, + PERIPHC_72h, + PERIPHC_73h, + PERIPHC_74h, + PERIPHC_75h, + PERIPHC_VI_SENSOR2, + PERIPHC_I2C6, + + /* 0x78 */ + PERIPHC_78h, + PERIPHC_EMC_DLL, + PERIPHC_HDMI_AUDIO, + PERIPHC_CLK72MHZ, + PERIPHC_ADX1, + PERIPHC_AMX1, + PERIPHC_VIC, + PERIPHC_7fh, + + PERIPHC_COUNT, + + PERIPHC_NONE = -1, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ +#define PERIPH_REG(id) \ + (id < PERIPH_ID_VW_FIRST) ? \ + ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _TEGRA124_CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h new file mode 100644 index 0000000000..8e65086252 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 clock control definitions */ + +#ifndef _TEGRA124_CLOCK_H_ +#define _TEGRA124_CLOCK_H_ + +#include + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) + +int tegra_plle_enable(void); + +#endif /* _TEGRA124_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h new file mode 100644 index 0000000000..0db1881bc6 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_FLOW_H_ +#define _TEGRA124_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +#endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h new file mode 100644 index 0000000000..df94d135f8 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/funcmux.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 high-level function multiplexing */ + +#ifndef _TEGRA124_FUNCMUX_H_ +#define _TEGRA124_FUNCMUX_H_ + +#include + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART1_KBC = 0, + FUNCMUX_UART4_GPIO = 0, +}; +#endif /* _TEGRA124_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h new file mode 100644 index 0000000000..440cbbfa3e --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_GP_PADCTRL_H_ +#define _TEGRA124_GP_PADCTRL_H_ + +#include + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 reserved1; /* 0x8C: */ + u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 reserved2[3]; /* 0xA4 - 0xAC: */ + u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 reserved3[9]; /* 0xC8-0xE8: */ + u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0xF0-0xF8: */ + u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x104-0x10C: */ + u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x128: */ + u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x130 - 0x134: */ + u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[22]; /* 0x13C - 0x190: */ + u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ +}; + +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + +#endif /* _TEGRA124_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h new file mode 100644 index 0000000000..1a6dcb8715 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/gpio.h @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_GPIO_H_ +#define _TEGRA124_GPIO_H_ + +/* + * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ + +#include + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; + uint gpio_masked_config[TEGRA_GPIO_PORTS]; + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_in[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +enum gpio_pin { + GPIO_PA0 = 0, /* pin 0 */ + GPIO_PA1, + GPIO_PA2, + GPIO_PA3, + GPIO_PA4, + GPIO_PA5, + GPIO_PA6, + GPIO_PA7, + GPIO_PB0, /* pin 8 */ + GPIO_PB1, + GPIO_PB2, + GPIO_PB3, + GPIO_PB4, + GPIO_PB5, + GPIO_PB6, + GPIO_PB7, + GPIO_PC0, /* pin 16 */ + GPIO_PC1, + GPIO_PC2, + GPIO_PC3, + GPIO_PC4, + GPIO_PC5, + GPIO_PC6, + GPIO_PC7, + GPIO_PD0, /* pin 24 */ + GPIO_PD1, + GPIO_PD2, + GPIO_PD3, + GPIO_PD4, + GPIO_PD5, + GPIO_PD6, + GPIO_PD7, + GPIO_PE0, /* pin 32 */ + GPIO_PE1, + GPIO_PE2, + GPIO_PE3, + GPIO_PE4, + GPIO_PE5, + GPIO_PE6, + GPIO_PE7, + GPIO_PF0, /* pin 40 */ + GPIO_PF1, + GPIO_PF2, + GPIO_PF3, + GPIO_PF4, + GPIO_PF5, + GPIO_PF6, + GPIO_PF7, + GPIO_PG0, /* pin 48 */ + GPIO_PG1, + GPIO_PG2, + GPIO_PG3, + GPIO_PG4, + GPIO_PG5, + GPIO_PG6, + GPIO_PG7, + GPIO_PH0, /* pin 56 */ + GPIO_PH1, + GPIO_PH2, + GPIO_PH3, + GPIO_PH4, + GPIO_PH5, + GPIO_PH6, + GPIO_PH7, + GPIO_PI0, /* pin 64 */ + GPIO_PI1, + GPIO_PI2, + GPIO_PI3, + GPIO_PI4, + GPIO_PI5, + GPIO_PI6, + GPIO_PI7, + GPIO_PJ0, /* pin 72 */ + GPIO_PJ1, + GPIO_PJ2, + GPIO_PJ3, + GPIO_PJ4, + GPIO_PJ5, + GPIO_PJ6, + GPIO_PJ7, + GPIO_PK0, /* pin 80 */ + GPIO_PK1, + GPIO_PK2, + GPIO_PK3, + GPIO_PK4, + GPIO_PK5, + GPIO_PK6, + GPIO_PK7, + GPIO_PL0, /* pin 88 */ + GPIO_PL1, + GPIO_PL2, + GPIO_PL3, + GPIO_PL4, + GPIO_PL5, + GPIO_PL6, + GPIO_PL7, + GPIO_PM0, /* pin 96 */ + GPIO_PM1, + GPIO_PM2, + GPIO_PM3, + GPIO_PM4, + GPIO_PM5, + GPIO_PM6, + GPIO_PM7, + GPIO_PN0, /* pin 104 */ + GPIO_PN1, + GPIO_PN2, + GPIO_PN3, + GPIO_PN4, + GPIO_PN5, + GPIO_PN6, + GPIO_PN7, + GPIO_PO0, /* pin 112 */ + GPIO_PO1, + GPIO_PO2, + GPIO_PO3, + GPIO_PO4, + GPIO_PO5, + GPIO_PO6, + GPIO_PO7, + GPIO_PP0, /* pin 120 */ + GPIO_PP1, + GPIO_PP2, + GPIO_PP3, + GPIO_PP4, + GPIO_PP5, + GPIO_PP6, + GPIO_PP7, + GPIO_PQ0, /* pin 128 */ + GPIO_PQ1, + GPIO_PQ2, + GPIO_PQ3, + GPIO_PQ4, + GPIO_PQ5, + GPIO_PQ6, + GPIO_PQ7, + GPIO_PR0, /* pin 136 */ + GPIO_PR1, + GPIO_PR2, + GPIO_PR3, + GPIO_PR4, + GPIO_PR5, + GPIO_PR6, + GPIO_PR7, + GPIO_PS0, /* pin 144 */ + GPIO_PS1, + GPIO_PS2, + GPIO_PS3, + GPIO_PS4, + GPIO_PS5, + GPIO_PS6, + GPIO_PS7, + GPIO_PT0, /* pin 152 */ + GPIO_PT1, + GPIO_PT2, + GPIO_PT3, + GPIO_PT4, + GPIO_PT5, + GPIO_PT6, + GPIO_PT7, + GPIO_PU0, /* pin 160 */ + GPIO_PU1, + GPIO_PU2, + GPIO_PU3, + GPIO_PU4, + GPIO_PU5, + GPIO_PU6, + GPIO_PU7, + GPIO_PV0, /* pin 168 */ + GPIO_PV1, + GPIO_PV2, + GPIO_PV3, + GPIO_PV4, + GPIO_PV5, + GPIO_PV6, + GPIO_PV7, + GPIO_PW0, /* pin 176 */ + GPIO_PW1, + GPIO_PW2, + GPIO_PW3, + GPIO_PW4, + GPIO_PW5, + GPIO_PW6, + GPIO_PW7, + GPIO_PX0, /* pin 184 */ + GPIO_PX1, + GPIO_PX2, + GPIO_PX3, + GPIO_PX4, + GPIO_PX5, + GPIO_PX6, + GPIO_PX7, + GPIO_PY0, /* pin 192 */ + GPIO_PY1, + GPIO_PY2, + GPIO_PY3, + GPIO_PY4, + GPIO_PY5, + GPIO_PY6, + GPIO_PY7, + GPIO_PZ0, /* pin 200 */ + GPIO_PZ1, + GPIO_PZ2, + GPIO_PZ3, + GPIO_PZ4, + GPIO_PZ5, + GPIO_PZ6, + GPIO_PZ7, + GPIO_PAA0, /* pin 208 */ + GPIO_PAA1, + GPIO_PAA2, + GPIO_PAA3, + GPIO_PAA4, + GPIO_PAA5, + GPIO_PAA6, + GPIO_PAA7, + GPIO_PBB0, /* pin 216 */ + GPIO_PBB1, + GPIO_PBB2, + GPIO_PBB3, + GPIO_PBB4, + GPIO_PBB5, + GPIO_PBB6, + GPIO_PBB7, + GPIO_PCC0, /* pin 224 */ + GPIO_PCC1, + GPIO_PCC2, + GPIO_PCC3, + GPIO_PCC4, + GPIO_PCC5, + GPIO_PCC6, + GPIO_PCC7, + GPIO_PDD0, /* pin 232 */ + GPIO_PDD1, + GPIO_PDD2, + GPIO_PDD3, + GPIO_PDD4, + GPIO_PDD5, + GPIO_PDD6, + GPIO_PDD7, + GPIO_PEE0, /* pin 240 */ + GPIO_PEE1, + GPIO_PEE2, + GPIO_PEE3, + GPIO_PEE4, + GPIO_PEE5, + GPIO_PEE6, + GPIO_PEE7, + GPIO_PFF0, /* pin 248 */ + GPIO_PFF1, + GPIO_PFF2, + GPIO_PFF3, + GPIO_PFF4, + GPIO_PFF5, + GPIO_PFF6, + GPIO_PFF7, /* pin 255 */ +}; + +#endif /* _TEGRA124_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h new file mode 100644 index 0000000000..114fce8ada --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/hardware.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_HARDWARE_H_ +#define _TEGRA124_HARDWARE_H_ + +/* + * Include Tegra-specific hardware definitions + * Nothing needed currently for Tegra124 + */ + +#endif /* _TEGRA124_HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h new file mode 100644 index 0000000000..d526dfe15c --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _TEGRA124_MC_H_ +#define _TEGRA124_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) + +#endif /* _TEGRA124_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h new file mode 100644 index 0000000000..1884935a57 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_PINMUX_H_ +#define _TEGRA124_PINMUX_H_ + +enum pmux_pingrp { + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_PC7, + PMUX_PINGRP_PI5, + PMUX_PINGRP_PI7, + PMUX_PINGRP_PK0, + PMUX_PINGRP_PK1, + PMUX_PINGRP_PJ0, + PMUX_PINGRP_PJ2, + PMUX_PINGRP_PK3, + PMUX_PINGRP_PK4, + PMUX_PINGRP_PK2, + PMUX_PINGRP_PI3, + PMUX_PINGRP_PI6, + PMUX_PINGRP_PG0, + PMUX_PINGRP_PG1, + PMUX_PINGRP_PG2, + PMUX_PINGRP_PG3, + PMUX_PINGRP_PG4, + PMUX_PINGRP_PG5, + PMUX_PINGRP_PG6, + PMUX_PINGRP_PG7, + PMUX_PINGRP_PH0, + PMUX_PINGRP_PH1, + PMUX_PINGRP_PH2, + PMUX_PINGRP_PH3, + PMUX_PINGRP_PH4, + PMUX_PINGRP_PH5, + PMUX_PINGRP_PH6, + PMUX_PINGRP_PH7, + PMUX_PINGRP_PJ7, + PMUX_PINGRP_PB0, + PMUX_PINGRP_PB1, + PMUX_PINGRP_PK7, + PMUX_PINGRP_PI0, + PMUX_PINGRP_PI1, + PMUX_PINGRP_PI2, + PMUX_PINGRP_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_ROW11_PS3, + PMUX_PINGRP_KB_ROW12_PS4, + PMUX_PINGRP_KB_ROW13_PS5, + PMUX_PINGRP_KB_ROW14_PS6, + PMUX_PINGRP_KB_ROW15_PS7, + PMUX_PINGRP_KB_COL0_PQ0, + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4), + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_DAP_MCLK1_REQ_PEE2, + PMUX_PINGRP_DAP_MCLK1_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_DVFS_PWM_PX0, + PMUX_PINGRP_GPIO_X1_AUD_PX1, + PMUX_PINGRP_GPIO_X3_AUD_PX3, + PMUX_PINGRP_DVFS_CLK_PX2, + PMUX_PINGRP_GPIO_X4_AUD_PX4, + PMUX_PINGRP_GPIO_X5_AUD_PX5, + PMUX_PINGRP_GPIO_X6_AUD_PX6, + PMUX_PINGRP_GPIO_X7_AUD_PX7, + PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4), + PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, + PMUX_PINGRP_PEX_WAKE_N_PDD3, + PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4), + PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, + PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), + PMUX_PINGRP_SDMMC1_WP_N_PV3, + PMUX_PINGRP_SDMMC3_CD_N_PV2, + PMUX_PINGRP_GPIO_W2_AUD_PW2, + PMUX_PINGRP_GPIO_W3_AUD_PW3, + PMUX_PINGRP_USB_VBUS_EN0_PN4, + PMUX_PINGRP_USB_VBUS_EN1_PN5, + PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, + PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, + PMUX_PINGRP_GMI_CLK_LB, + PMUX_PINGRP_RESET_OUT_N, + PMUX_PINGRP_KB_ROW16_PT0, + PMUX_PINGRP_KB_ROW17_PT1, + PMUX_PINGRP_USB_VBUS_EN2_PFF1, + PMUX_PINGRP_PFF2, + PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4), + PMUX_PINGRP_COUNT, +}; + +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_DAP1 = (0x28 / 4), + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_SDIO3 = (0x48 / 4), + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_DDC = (0x94 / 4), + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GME = (0xa8 / 4), + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_GPV, + PMUX_DRVGRP_DEV3, + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_AT6 = (0x12c / 4), + PMUX_DRVGRP_DAP5, + PMUX_DRVGRP_USB_VBUS_EN, + PMUX_DRVGRP_AO3 = (0x140 / 4), + PMUX_DRVGRP_AO0 = (0x148 / 4), + PMUX_DRVGRP_HV0, + PMUX_DRVGRP_SDIO4 = (0x15c / 4), + PMUX_DRVGRP_AO4, + PMUX_DRVGRP_COUNT, +}; + +enum pmux_func { + PMUX_FUNC_DEFAULT, + PMUX_FUNC_BLINK, + PMUX_FUNC_CCLA, + PMUX_FUNC_CEC, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_CLK, + PMUX_FUNC_CLK12, + PMUX_FUNC_CPU, + PMUX_FUNC_DAP, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, + PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYA_ALT, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DP, + PMUX_FUNC_DTV, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HSI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_IRDA, + PMUX_FUNC_KBC, + PMUX_FUNC_OWR, + PMUX_FUNC_PE, + PMUX_FUNC_PE0, + PMUX_FUNC_PE1, + PMUX_FUNC_PMI, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_PWRON, + PMUX_FUNC_RESET_OUT_N, + PMUX_FUNC_RTCK, + PMUX_FUNC_SATA, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SOC, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYS, + PMUX_FUNC_TMDS, + PMUX_FUNC_TRACE, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_ULPI, + PMUX_FUNC_USB, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_VIMCLK2, + PMUX_FUNC_VIMCLK2_ALT, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, +}; + +#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#define TEGRA_PMX_HAS_RCV_SEL +#define TEGRA_PMX_HAS_DRVGRPS +#include + +#endif /* _TEGRA124_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h new file mode 100644 index 0000000000..b10100a636 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/pmu.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_PMU_H_ +#define _TEGRA124_PMU_H_ + +/* Set core and CPU voltages to nominal levels */ +int pmu_set_nominal(void); + +#endif /* _TEGRA124_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/powergate.h b/arch/arm/include/asm/arch-tegra124/powergate.h new file mode 100644 index 0000000000..8a0cfbaf96 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA124_POWERGATE_H_ +#define _TEGRA124_POWERGATE_H_ + +#include + +#endif /* _TEGRA124_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h new file mode 100644 index 0000000000..3f0309b78f --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/sysctr.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_SYSCTR_H_ +#define _TEGRA124_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA124_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h new file mode 100644 index 0000000000..db3d837920 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/tegra.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_H_ +#define _TEGRA124_H_ + +#define NV_PA_SDRAM_BASE 0x80000000 +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ +#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ + +#include + +#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ + +#undef NVBOOTINFOTABLE_BCTSIZE +#undef NVBOOTINFOTABLE_BCTPTR +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ + +#define MAX_NUM_CPU 4 +#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) + +#define TEGRA_USB1_BASE 0x7D000000 + +#endif /* _TEGRA124_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h index a09cb01978..894be088cd 100644 --- a/arch/arm/include/asm/arch-tegra20/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h @@ -131,7 +131,7 @@ enum periph_id { /* 72 */ PERIPH_ID_AFI, PERIPH_ID_CORESIGHT, - PERIPH_ID_RESERVED74, + PERIPH_ID_PCIEXCLK, PERIPH_ID_AVPUCQ, PERIPH_ID_RESERVED76, PERIPH_ID_RESERVED77, diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h index 889c65a16f..4df8da96e2 100644 --- a/arch/arm/include/asm/arch-tegra20/clock.h +++ b/arch/arm/include/asm/arch-tegra20/clock.h @@ -15,4 +15,6 @@ #define OSC_FREQ_SHIFT 30 #define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) +int tegra_plle_enable(void); + #endif /* _TEGRA20_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h index a04c84e54b..6feeda3ba8 100644 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ b/arch/arm/include/asm/arch-tegra20/display.h @@ -10,6 +10,7 @@ #include #include +#include /* This holds information about a window which can be displayed */ struct disp_ctl_win { @@ -72,10 +73,10 @@ struct fdt_panel_config { int pwm_channel; /* PWM channel to use for backlight */ enum lcd_cache_t cache_type; - struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */ - struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */ - struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */ - struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */ + struct gpio_desc backlight_en; /* GPIO for backlight enable */ + struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */ + struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */ + struct gpio_desc panel_vdd; /* GPIO for panel vdd */ /* * Panel required timings * Timing 1: delay between panel_vdd-rise and data-rise diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/include/asm/arch-tegra20/mc.h new file mode 100644 index 0000000000..9c6e3ffb6f --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/mc.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA20_MC_H_ +#define _TEGRA20_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[3]; /* offset 0x00 - 0x08 */ + u32 mc_emem_cfg; /* offset 0x0C */ + u32 mc_emem_adr_cfg; /* offset 0x10 */ + u32 mc_emem_arb_cfg0; /* offset 0x14 */ + u32 mc_emem_arb_cfg1; /* offset 0x18 */ + u32 mc_emem_arb_cfg2; /* offset 0x1C */ + u32 reserved1; /* offset 0x20 */ + u32 mc_gart_cfg; /* offset 0x24 */ + u32 mc_gart_entry_addr; /* offset 0x28 */ + u32 mc_gart_entry_data; /* offset 0x2C */ + u32 mc_gart_error_req; /* offset 0x30 */ + u32 mc_gart_error_addr; /* offset 0x34 */ + u32 reserved2; /* offset 0x38 */ + u32 mc_timeout_ctrl; /* offset 0x3C */ + u32 reserved3[6]; /* offset 0x40 - 0x54 */ + u32 mc_decerr_emem_others_status; /* offset 0x58 */ + u32 mc_decerr_emem_others_adr; /* offset 0x5C */ + u32 reserved4[40]; /* offset 0x60 - 0xFC */ + u32 reserved5[93]; /* offset 0x100 - 0x270 */ +}; + +#endif /* _TEGRA20_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index 05925df861..f7bc97fe5f 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _PINMUX_H_ -#define _PINMUX_H_ +#ifndef _TEGRA20_PINMUX_H_ +#define _TEGRA20_PINMUX_H_ /* * Pin groups which we adjust. There are three basic attributes of each pin @@ -18,148 +18,146 @@ */ enum pmux_pingrp { /* APB_MISC_PP_TRISTATE_REG_A_0 */ - PINGRP_ATA, - PINGRP_ATB, - PINGRP_ATC, - PINGRP_ATD, - PINGRP_CDEV1, - PINGRP_CDEV2, - PINGRP_CSUS, - PINGRP_DAP1, - - PINGRP_DAP2, - PINGRP_DAP3, - PINGRP_DAP4, - PINGRP_DTA, - PINGRP_DTB, - PINGRP_DTC, - PINGRP_DTD, - PINGRP_DTE, - - PINGRP_GPU, - PINGRP_GPV, - PINGRP_I2CP, - PINGRP_IRTX, - PINGRP_IRRX, - PINGRP_KBCB, - PINGRP_KBCA, - PINGRP_PMC, - - PINGRP_PTA, - PINGRP_RM, - PINGRP_KBCE, - PINGRP_KBCF, - PINGRP_GMA, - PINGRP_GMC, - PINGRP_SDIO1, - PINGRP_OWC, + PMUX_PINGRP_ATA, + PMUX_PINGRP_ATB, + PMUX_PINGRP_ATC, + PMUX_PINGRP_ATD, + PMUX_PINGRP_CDEV1, + PMUX_PINGRP_CDEV2, + PMUX_PINGRP_CSUS, + PMUX_PINGRP_DAP1, + + PMUX_PINGRP_DAP2, + PMUX_PINGRP_DAP3, + PMUX_PINGRP_DAP4, + PMUX_PINGRP_DTA, + PMUX_PINGRP_DTB, + PMUX_PINGRP_DTC, + PMUX_PINGRP_DTD, + PMUX_PINGRP_DTE, + + PMUX_PINGRP_GPU, + PMUX_PINGRP_GPV, + PMUX_PINGRP_I2CP, + PMUX_PINGRP_IRTX, + PMUX_PINGRP_IRRX, + PMUX_PINGRP_KBCB, + PMUX_PINGRP_KBCA, + PMUX_PINGRP_PMC, + + PMUX_PINGRP_PTA, + PMUX_PINGRP_RM, + PMUX_PINGRP_KBCE, + PMUX_PINGRP_KBCF, + PMUX_PINGRP_GMA, + PMUX_PINGRP_GMC, + PMUX_PINGRP_SDIO1, + PMUX_PINGRP_OWC, /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ - PINGRP_GME, - PINGRP_SDC, - PINGRP_SDD, - PINGRP_RESERVED0, - PINGRP_SLXA, - PINGRP_SLXC, - PINGRP_SLXD, - PINGRP_SLXK, - - PINGRP_SPDI, - PINGRP_SPDO, - PINGRP_SPIA, - PINGRP_SPIB, - PINGRP_SPIC, - PINGRP_SPID, - PINGRP_SPIE, - PINGRP_SPIF, - - PINGRP_SPIG, - PINGRP_SPIH, - PINGRP_UAA, - PINGRP_UAB, - PINGRP_UAC, - PINGRP_UAD, - PINGRP_UCA, - PINGRP_UCB, - - PINGRP_RESERVED1, - PINGRP_ATE, - PINGRP_KBCC, - PINGRP_RESERVED2, - PINGRP_RESERVED3, - PINGRP_GMB, - PINGRP_GMD, - PINGRP_DDC, + PMUX_PINGRP_GME, + PMUX_PINGRP_SDC, + PMUX_PINGRP_SDD, + PMUX_PINGRP_RESERVED0, + PMUX_PINGRP_SLXA, + PMUX_PINGRP_SLXC, + PMUX_PINGRP_SLXD, + PMUX_PINGRP_SLXK, + + PMUX_PINGRP_SPDI, + PMUX_PINGRP_SPDO, + PMUX_PINGRP_SPIA, + PMUX_PINGRP_SPIB, + PMUX_PINGRP_SPIC, + PMUX_PINGRP_SPID, + PMUX_PINGRP_SPIE, + PMUX_PINGRP_SPIF, + + PMUX_PINGRP_SPIG, + PMUX_PINGRP_SPIH, + PMUX_PINGRP_UAA, + PMUX_PINGRP_UAB, + PMUX_PINGRP_UAC, + PMUX_PINGRP_UAD, + PMUX_PINGRP_UCA, + PMUX_PINGRP_UCB, + + PMUX_PINGRP_RESERVED1, + PMUX_PINGRP_ATE, + PMUX_PINGRP_KBCC, + PMUX_PINGRP_RESERVED2, + PMUX_PINGRP_RESERVED3, + PMUX_PINGRP_GMB, + PMUX_PINGRP_GMD, + PMUX_PINGRP_DDC, /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ - PINGRP_LD0, - PINGRP_LD1, - PINGRP_LD2, - PINGRP_LD3, - PINGRP_LD4, - PINGRP_LD5, - PINGRP_LD6, - PINGRP_LD7, - - PINGRP_LD8, - PINGRP_LD9, - PINGRP_LD10, - PINGRP_LD11, - PINGRP_LD12, - PINGRP_LD13, - PINGRP_LD14, - PINGRP_LD15, - - PINGRP_LD16, - PINGRP_LD17, - PINGRP_LHP0, - PINGRP_LHP1, - PINGRP_LHP2, - PINGRP_LVP0, - PINGRP_LVP1, - PINGRP_HDINT, - - PINGRP_LM0, - PINGRP_LM1, - PINGRP_LVS, - PINGRP_LSC0, - PINGRP_LSC1, - PINGRP_LSCK, - PINGRP_LDC, - PINGRP_LCSN, + PMUX_PINGRP_LD0, + PMUX_PINGRP_LD1, + PMUX_PINGRP_LD2, + PMUX_PINGRP_LD3, + PMUX_PINGRP_LD4, + PMUX_PINGRP_LD5, + PMUX_PINGRP_LD6, + PMUX_PINGRP_LD7, + + PMUX_PINGRP_LD8, + PMUX_PINGRP_LD9, + PMUX_PINGRP_LD10, + PMUX_PINGRP_LD11, + PMUX_PINGRP_LD12, + PMUX_PINGRP_LD13, + PMUX_PINGRP_LD14, + PMUX_PINGRP_LD15, + + PMUX_PINGRP_LD16, + PMUX_PINGRP_LD17, + PMUX_PINGRP_LHP0, + PMUX_PINGRP_LHP1, + PMUX_PINGRP_LHP2, + PMUX_PINGRP_LVP0, + PMUX_PINGRP_LVP1, + PMUX_PINGRP_HDINT, + + PMUX_PINGRP_LM0, + PMUX_PINGRP_LM1, + PMUX_PINGRP_LVS, + PMUX_PINGRP_LSC0, + PMUX_PINGRP_LSC1, + PMUX_PINGRP_LSCK, + PMUX_PINGRP_LDC, + PMUX_PINGRP_LCSN, /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ - PINGRP_LSPI, - PINGRP_LSDA, - PINGRP_LSDI, - PINGRP_LPW0, - PINGRP_LPW1, - PINGRP_LPW2, - PINGRP_LDI, - PINGRP_LHS, - - PINGRP_LPP, - PINGRP_RESERVED4, - PINGRP_KBCD, - PINGRP_GPU7, - PINGRP_DTF, - PINGRP_UDA, - PINGRP_CRTP, - PINGRP_SDB, + PMUX_PINGRP_LSPI, + PMUX_PINGRP_LSDA, + PMUX_PINGRP_LSDI, + PMUX_PINGRP_LPW0, + PMUX_PINGRP_LPW1, + PMUX_PINGRP_LPW2, + PMUX_PINGRP_LDI, + PMUX_PINGRP_LHS, + + PMUX_PINGRP_LPP, + PMUX_PINGRP_RESERVED4, + PMUX_PINGRP_KBCD, + PMUX_PINGRP_GPU7, + PMUX_PINGRP_DTF, + PMUX_PINGRP_UDA, + PMUX_PINGRP_CRTP, + PMUX_PINGRP_SDB, /* these pin groups only have pullup and pull down control */ - PINGRP_FIRST_NO_MUX, - PINGRP_CK32 = PINGRP_FIRST_NO_MUX, - PINGRP_DDRC, - PINGRP_PMCA, - PINGRP_PMCB, - PINGRP_PMCC, - PINGRP_PMCD, - PINGRP_PMCE, - PINGRP_XM2C, - PINGRP_XM2D, - - PINGRP_COUNT, + PMUX_PINGRP_CK32, + PMUX_PINGRP_DDRC, + PMUX_PINGRP_PMCA, + PMUX_PINGRP_PMCB, + PMUX_PINGRP_PMCC, + PMUX_PINGRP_PMCD, + PMUX_PINGRP_PMCE, + PMUX_PINGRP_XM2C, + PMUX_PINGRP_XM2D, + PMUX_PINGRP_COUNT, }; /* @@ -168,6 +166,7 @@ enum pmux_pingrp { * purely a convenience. The translation is done through a table search. */ enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_AHB_CLK, PMUX_FUNC_APB_CLK, PMUX_FUNC_AUDIO_SYNC, @@ -227,111 +226,13 @@ enum pmux_func { PMUX_FUNC_VI, PMUX_FUNC_VI_SENSOR_CLK, PMUX_FUNC_XIO, - PMUX_FUNC_SAFE, - - /* These don't have a name, but can be used in the table */ PMUX_FUNC_RSVD1, PMUX_FUNC_RSVD2, PMUX_FUNC_RSVD3, PMUX_FUNC_RSVD4, - PMUX_FUNC_RSVD, /* Not valid and should not be used */ - PMUX_FUNC_COUNT, - - PMUX_FUNC_NONE = -1, -}; - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \ - (func) != PMUX_FUNC_RSVD) - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; - -/* Available power domains used by pin groups */ -enum pmux_vddio { - PMUX_VDDIO_BB = 0, - PMUX_VDDIO_LCD, - PMUX_VDDIO_VI, - PMUX_VDDIO_UART, - PMUX_VDDIO_DDR, - PMUX_VDDIO_NAND, - PMUX_VDDIO_SYS, - PMUX_VDDIO_AUDIO, - PMUX_VDDIO_SD, - - PMUX_VDDIO_NONE -}; - -enum { - PMUX_TRISTATE_REGS = 4, - PMUX_MUX_REGS = 7, - PMUX_PULL_REGS = 5, -}; - -/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */ -struct pmux_tri_ctlr { - uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ - uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ - uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ - uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ - uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ - uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */ - uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ - - uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ - - uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */ - uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */ - uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */ -}; - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ }; -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(const struct pingroup_config *config); - -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - -/** - * Configuure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_table(const struct pingroup_config *config, int len); +#include -#endif /* PINMUX_H */ +#endif /* _TEGRA20_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/powergate.h b/arch/arm/include/asm/arch-tegra20/powergate.h new file mode 100644 index 0000000000..439d88b702 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA20_POWERGATE_H_ +#define _TEGRA20_POWERGATE_H_ + +#include + +#endif /* _TEGRA20_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/spl.h b/arch/arm/include/asm/arch-tegra20/spl.h deleted file mode 100644 index 8953b00a9f..0000000000 --- a/arch/arm/include/asm/arch-tegra20/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h index 18856ac372..22774abb93 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -9,6 +9,7 @@ #define _TEGRA20_H_ #define NV_PA_SDRAM_BASE 0x00000000 +#define NV_PA_MC_BASE 0x7000F000 #include diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h deleted file mode 100644 index e8cc68c6ea..0000000000 --- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra20 SPI-FLASH controller - * - * Copyright 2010-2012 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA20_SPI_H_ -#define _TEGRA20_SPI_H_ - -#include - -int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra20_spi_free_slave(struct spi_slave *slave); -int tegra20_spi_init(int *node_list, int count); -int tegra20_spi_claim_bus(struct spi_slave *slave); -void tegra20_spi_cs_activate(struct spi_slave *slave); -void tegra20_spi_cs_deactivate(struct spi_slave *slave); -int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA20_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h deleted file mode 100644 index 5aa74ddd6d..0000000000 --- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra SPI-SLINK controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA30_SPI_H_ -#define _TEGRA30_SPI_H_ - -#include - -int tegra30_spi_init(int *node_list, int count); -int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra30_spi_free_slave(struct spi_slave *slave); -int tegra30_spi_claim_bus(struct spi_slave *slave); -void tegra30_spi_cs_activate(struct spi_slave *slave); -void tegra30_spi_cs_deactivate(struct spi_slave *slave); -int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA30_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h deleted file mode 100644 index 3d94cc73b8..0000000000 --- a/arch/arm/include/asm/arch-tegra20/usb.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA20_USB_H_ -#define _TEGRA20_USB_H_ - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[6]; - - /* 0x140 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x150 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint async_tt_sts; - - /* 0x160 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; /* is this port_sc1 on some controllers? */ - uint icusb_ctrl; - - /* 0x170 */ - uint ulpi_viewport; - uint reserved7; - uint endpt_nak; - uint endpt_nak_enable; - - /* 0x180 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x1a0 */ - uint reserved9; - uint otgsc; - uint usb_mode; - uint endpt_setup_stat; - - /* 0x1b0 */ - uint reserved10[20]; - - /* 0x200 */ - uint reserved11[0x80]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[4]; - - /* 0x424 */ - uint ulpi_timing_ctrl_0; - uint ulpi_timing_ctrl_1; - uint reserved13[53]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -/* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) - -/* PORTSC, USB2, USB3 */ -#define PTS_SHIFT 30 -#define PTS_MASK (3U << PTS_SHIFT) - -#define STS (1 << 29) -#endif /* _TEGRA20_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h index 2f24a75cc4..410c352899 100644 --- a/arch/arm/include/asm/arch-tegra30/clock.h +++ b/arch/arm/include/asm/arch-tegra30/clock.h @@ -25,4 +25,6 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +int tegra_plle_enable(void); + #endif /* _TEGRA30_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/include/asm/arch-tegra30/mc.h new file mode 100644 index 0000000000..242a1fc64b --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/mc.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA30_MC_H_ +#define _TEGRA30_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 mc_smmu_asid_security; /* offset 0x38 */ + u32 reserved2[5]; /* offset 0x3C - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA30_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index a9e1b462c4..a42e00990f 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -1,668 +1,398 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA30_PINMUX_H_ #define _TEGRA30_PINMUX_H_ -/* - * Pin groups which we adjust. There are three basic attributes of each pin - * group which use this enum: - * - * - function - * - pullup / pulldown - * - tristate or normal - */ enum pmux_pingrp { - PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ - PINGRP_ULPI_DATA1, - PINGRP_ULPI_DATA2, - PINGRP_ULPI_DATA3, - PINGRP_ULPI_DATA4, - PINGRP_ULPI_DATA5, - PINGRP_ULPI_DATA6, - PINGRP_ULPI_DATA7, - PINGRP_ULPI_CLK, - PINGRP_ULPI_DIR, - PINGRP_ULPI_NXT, - PINGRP_ULPI_STP, - PINGRP_DAP3_FS, - PINGRP_DAP3_DIN, - PINGRP_DAP3_DOUT, - PINGRP_DAP3_SCLK, - PINGRP_GPIO_PV0, - PINGRP_GPIO_PV1, - PINGRP_SDMMC1_CLK, - PINGRP_SDMMC1_CMD, - PINGRP_SDMMC1_DAT3, - PINGRP_SDMMC1_DAT2, - PINGRP_SDMMC1_DAT1, - PINGRP_SDMMC1_DAT0, - PINGRP_GPIO_PV2, - PINGRP_GPIO_PV3, - PINGRP_CLK2_OUT, - PINGRP_CLK2_REQ, - PINGRP_LCD_PWR1, - PINGRP_LCD_PWR2, - PINGRP_LCD_SDIN, - PINGRP_LCD_SDOUT, - PINGRP_LCD_WR_N, - PINGRP_LCD_CS0_N, - PINGRP_LCD_DC0, - PINGRP_LCD_SCK, - PINGRP_LCD_PWR0, - PINGRP_LCD_PCLK, - PINGRP_LCD_DE, - PINGRP_LCD_HSYNC, - PINGRP_LCD_VSYNC, - PINGRP_LCD_D0, - PINGRP_LCD_D1, - PINGRP_LCD_D2, - PINGRP_LCD_D3, - PINGRP_LCD_D4, - PINGRP_LCD_D5, - PINGRP_LCD_D6, - PINGRP_LCD_D7, - PINGRP_LCD_D8, - PINGRP_LCD_D9, - PINGRP_LCD_D10, - PINGRP_LCD_D11, - PINGRP_LCD_D12, - PINGRP_LCD_D13, - PINGRP_LCD_D14, - PINGRP_LCD_D15, - PINGRP_LCD_D16, - PINGRP_LCD_D17, - PINGRP_LCD_D18, - PINGRP_LCD_D19, - PINGRP_LCD_D20, - PINGRP_LCD_D21, - PINGRP_LCD_D22, - PINGRP_LCD_D23, - PINGRP_LCD_CS1_N, - PINGRP_LCD_M1, - PINGRP_LCD_DC1, - PINGRP_HDMI_INT, - PINGRP_DDC_SCL, - PINGRP_DDC_SDA, - PINGRP_CRT_HSYNC, - PINGRP_CRT_VSYNC, - PINGRP_VI_D0, - PINGRP_VI_D1, - PINGRP_VI_D2, - PINGRP_VI_D3, - PINGRP_VI_D4, - PINGRP_VI_D5, - PINGRP_VI_D6, - PINGRP_VI_D7, - PINGRP_VI_D8, - PINGRP_VI_D9, - PINGRP_VI_D10, - PINGRP_VI_D11, - PINGRP_VI_PCLK, - PINGRP_VI_MCLK, - PINGRP_VI_VSYNC, - PINGRP_VI_HSYNC, - PINGRP_UART2_RXD, - PINGRP_UART2_TXD, - PINGRP_UART2_RTS_N, - PINGRP_UART2_CTS_N, - PINGRP_UART3_TXD, - PINGRP_UART3_RXD, - PINGRP_UART3_CTS_N, - PINGRP_UART3_RTS_N, - PINGRP_GPIO_PU0, - PINGRP_GPIO_PU1, - PINGRP_GPIO_PU2, - PINGRP_GPIO_PU3, - PINGRP_GPIO_PU4, - PINGRP_GPIO_PU5, - PINGRP_GPIO_PU6, - PINGRP_GEN1_I2C_SDA, - PINGRP_GEN1_I2C_SCL, - PINGRP_DAP4_FS, - PINGRP_DAP4_DIN, - PINGRP_DAP4_DOUT, - PINGRP_DAP4_SCLK, - PINGRP_CLK3_OUT, - PINGRP_CLK3_REQ, - PINGRP_GMI_WP_N, - PINGRP_GMI_IORDY, - PINGRP_GMI_WAIT, - PINGRP_GMI_ADV_N, - PINGRP_GMI_CLK, - PINGRP_GMI_CS0_N, - PINGRP_GMI_CS1_N, - PINGRP_GMI_CS2_N, - PINGRP_GMI_CS3_N, - PINGRP_GMI_CS4_N, - PINGRP_GMI_CS6_N, - PINGRP_GMI_CS7_N, - PINGRP_GMI_AD0, - PINGRP_GMI_AD1, - PINGRP_GMI_AD2, - PINGRP_GMI_AD3, - PINGRP_GMI_AD4, - PINGRP_GMI_AD5, - PINGRP_GMI_AD6, - PINGRP_GMI_AD7, - PINGRP_GMI_AD8, - PINGRP_GMI_AD9, - PINGRP_GMI_AD10, - PINGRP_GMI_AD11, - PINGRP_GMI_AD12, - PINGRP_GMI_AD13, - PINGRP_GMI_AD14, - PINGRP_GMI_AD15, - PINGRP_GMI_A16, - PINGRP_GMI_A17, - PINGRP_GMI_A18, - PINGRP_GMI_A19, - PINGRP_GMI_WR_N, - PINGRP_GMI_OE_N, - PINGRP_GMI_DQS, - PINGRP_GMI_RST_N, - PINGRP_GEN2_I2C_SCL, - PINGRP_GEN2_I2C_SDA, - PINGRP_SDMMC4_CLK, - PINGRP_SDMMC4_CMD, - PINGRP_SDMMC4_DAT0, - PINGRP_SDMMC4_DAT1, - PINGRP_SDMMC4_DAT2, - PINGRP_SDMMC4_DAT3, - PINGRP_SDMMC4_DAT4, - PINGRP_SDMMC4_DAT5, - PINGRP_SDMMC4_DAT6, - PINGRP_SDMMC4_DAT7, - PINGRP_SDMMC4_RST_N, - PINGRP_CAM_MCLK, - PINGRP_GPIO_PCC1, - PINGRP_GPIO_PBB0, - PINGRP_CAM_I2C_SCL, - PINGRP_CAM_I2C_SDA, - PINGRP_GPIO_PBB3, - PINGRP_GPIO_PBB4, - PINGRP_GPIO_PBB5, - PINGRP_GPIO_PBB6, - PINGRP_GPIO_PBB7, - PINGRP_GPIO_PCC2, - PINGRP_JTAG_RTCK, - PINGRP_PWR_I2C_SCL, - PINGRP_PWR_I2C_SDA, - PINGRP_KB_ROW0, - PINGRP_KB_ROW1, - PINGRP_KB_ROW2, - PINGRP_KB_ROW3, - PINGRP_KB_ROW4, - PINGRP_KB_ROW5, - PINGRP_KB_ROW6, - PINGRP_KB_ROW7, - PINGRP_KB_ROW8, - PINGRP_KB_ROW9, - PINGRP_KB_ROW10, - PINGRP_KB_ROW11, - PINGRP_KB_ROW12, - PINGRP_KB_ROW13, - PINGRP_KB_ROW14, - PINGRP_KB_ROW15, - PINGRP_KB_COL0, - PINGRP_KB_COL1, - PINGRP_KB_COL2, - PINGRP_KB_COL3, - PINGRP_KB_COL4, - PINGRP_KB_COL5, - PINGRP_KB_COL6, - PINGRP_KB_COL7, - PINGRP_CLK_32K_OUT, - PINGRP_SYS_CLK_REQ, - PINGRP_CORE_PWR_REQ, - PINGRP_CPU_PWR_REQ, - PINGRP_PWR_INT_N, - PINGRP_CLK_32K_IN, - PINGRP_OWR, - PINGRP_DAP1_FS, - PINGRP_DAP1_DIN, - PINGRP_DAP1_DOUT, - PINGRP_DAP1_SCLK, - PINGRP_CLK1_REQ, - PINGRP_CLK1_OUT, - PINGRP_SPDIF_IN, - PINGRP_SPDIF_OUT, - PINGRP_DAP2_FS, - PINGRP_DAP2_DIN, - PINGRP_DAP2_DOUT, - PINGRP_DAP2_SCLK, - PINGRP_SPI2_MOSI, - PINGRP_SPI2_MISO, - PINGRP_SPI2_CS0_N, - PINGRP_SPI2_SCK, - PINGRP_SPI1_MOSI, - PINGRP_SPI1_SCK, - PINGRP_SPI1_CS0_N, - PINGRP_SPI1_MISO, - PINGRP_SPI2_CS1_N, - PINGRP_SPI2_CS2_N, - PINGRP_SDMMC3_CLK, - PINGRP_SDMMC3_CMD, - PINGRP_SDMMC3_DAT0, - PINGRP_SDMMC3_DAT1, - PINGRP_SDMMC3_DAT2, - PINGRP_SDMMC3_DAT3, - PINGRP_SDMMC3_DAT4, - PINGRP_SDMMC3_DAT5, - PINGRP_SDMMC3_DAT6, - PINGRP_SDMMC3_DAT7, - PINGRP_PEX_L0_PRSNT_N, - PINGRP_PEX_L0_RST_N, - PINGRP_PEX_L0_CLKREQ_N, - PINGRP_PEX_WAKE_N, - PINGRP_PEX_L1_PRSNT_N, - PINGRP_PEX_L1_RST_N, - PINGRP_PEX_L1_CLKREQ_N, - PINGRP_PEX_L2_PRSNT_N, - PINGRP_PEX_L2_RST_N, - PINGRP_PEX_L2_CLKREQ_N, - PINGRP_HDMI_CEC, /* offset 0x33e0 */ - PINGRP_COUNT, + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_PV2, + PMUX_PINGRP_PV3, + PMUX_PINGRP_CLK2_OUT_PW5, + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_LCD_PWR1_PC1, + PMUX_PINGRP_LCD_PWR2_PC6, + PMUX_PINGRP_LCD_SDIN_PZ2, + PMUX_PINGRP_LCD_SDOUT_PN5, + PMUX_PINGRP_LCD_WR_N_PZ3, + PMUX_PINGRP_LCD_CS0_N_PN4, + PMUX_PINGRP_LCD_DC0_PN6, + PMUX_PINGRP_LCD_SCK_PZ4, + PMUX_PINGRP_LCD_PWR0_PB2, + PMUX_PINGRP_LCD_PCLK_PB3, + PMUX_PINGRP_LCD_DE_PJ1, + PMUX_PINGRP_LCD_HSYNC_PJ3, + PMUX_PINGRP_LCD_VSYNC_PJ4, + PMUX_PINGRP_LCD_D0_PE0, + PMUX_PINGRP_LCD_D1_PE1, + PMUX_PINGRP_LCD_D2_PE2, + PMUX_PINGRP_LCD_D3_PE3, + PMUX_PINGRP_LCD_D4_PE4, + PMUX_PINGRP_LCD_D5_PE5, + PMUX_PINGRP_LCD_D6_PE6, + PMUX_PINGRP_LCD_D7_PE7, + PMUX_PINGRP_LCD_D8_PF0, + PMUX_PINGRP_LCD_D9_PF1, + PMUX_PINGRP_LCD_D10_PF2, + PMUX_PINGRP_LCD_D11_PF3, + PMUX_PINGRP_LCD_D12_PF4, + PMUX_PINGRP_LCD_D13_PF5, + PMUX_PINGRP_LCD_D14_PF6, + PMUX_PINGRP_LCD_D15_PF7, + PMUX_PINGRP_LCD_D16_PM0, + PMUX_PINGRP_LCD_D17_PM1, + PMUX_PINGRP_LCD_D18_PM2, + PMUX_PINGRP_LCD_D19_PM3, + PMUX_PINGRP_LCD_D20_PM4, + PMUX_PINGRP_LCD_D21_PM5, + PMUX_PINGRP_LCD_D22_PM6, + PMUX_PINGRP_LCD_D23_PM7, + PMUX_PINGRP_LCD_CS1_N_PW0, + PMUX_PINGRP_LCD_M1_PW1, + PMUX_PINGRP_LCD_DC1_PD2, + PMUX_PINGRP_HDMI_INT_PN7, + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_CRT_HSYNC_PV6, + PMUX_PINGRP_CRT_VSYNC_PV7, + PMUX_PINGRP_VI_D0_PT4, + PMUX_PINGRP_VI_D1_PD5, + PMUX_PINGRP_VI_D2_PL0, + PMUX_PINGRP_VI_D3_PL1, + PMUX_PINGRP_VI_D4_PL2, + PMUX_PINGRP_VI_D5_PL3, + PMUX_PINGRP_VI_D6_PL4, + PMUX_PINGRP_VI_D7_PL5, + PMUX_PINGRP_VI_D8_PL6, + PMUX_PINGRP_VI_D9_PL7, + PMUX_PINGRP_VI_D10_PT2, + PMUX_PINGRP_VI_D11_PT3, + PMUX_PINGRP_VI_PCLK_PT0, + PMUX_PINGRP_VI_MCLK_PT1, + PMUX_PINGRP_VI_VSYNC_PD6, + PMUX_PINGRP_VI_HSYNC_PD7, + PMUX_PINGRP_UART2_RXD_PC3, + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_GMI_WP_N_PC7, + PMUX_PINGRP_GMI_IORDY_PI5, + PMUX_PINGRP_GMI_WAIT_PI7, + PMUX_PINGRP_GMI_ADV_N_PK0, + PMUX_PINGRP_GMI_CLK_PK1, + PMUX_PINGRP_GMI_CS0_N_PJ0, + PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_PINGRP_GMI_CS2_N_PK3, + PMUX_PINGRP_GMI_CS3_N_PK4, + PMUX_PINGRP_GMI_CS4_N_PK2, + PMUX_PINGRP_GMI_CS6_N_PI3, + PMUX_PINGRP_GMI_CS7_N_PI6, + PMUX_PINGRP_GMI_AD0_PG0, + PMUX_PINGRP_GMI_AD1_PG1, + PMUX_PINGRP_GMI_AD2_PG2, + PMUX_PINGRP_GMI_AD3_PG3, + PMUX_PINGRP_GMI_AD4_PG4, + PMUX_PINGRP_GMI_AD5_PG5, + PMUX_PINGRP_GMI_AD6_PG6, + PMUX_PINGRP_GMI_AD7_PG7, + PMUX_PINGRP_GMI_AD8_PH0, + PMUX_PINGRP_GMI_AD9_PH1, + PMUX_PINGRP_GMI_AD10_PH2, + PMUX_PINGRP_GMI_AD11_PH3, + PMUX_PINGRP_GMI_AD12_PH4, + PMUX_PINGRP_GMI_AD13_PH5, + PMUX_PINGRP_GMI_AD14_PH6, + PMUX_PINGRP_GMI_AD15_PH7, + PMUX_PINGRP_GMI_A16_PJ7, + PMUX_PINGRP_GMI_A17_PB0, + PMUX_PINGRP_GMI_A18_PB1, + PMUX_PINGRP_GMI_A19_PK7, + PMUX_PINGRP_GMI_WR_N_PI0, + PMUX_PINGRP_GMI_OE_N_PI1, + PMUX_PINGRP_GMI_DQS_PI2, + PMUX_PINGRP_GMI_RST_N_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_SDMMC4_RST_N_PCC3, + PMUX_PINGRP_CAM_MCLK_PCC0, + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK_PU7, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_ROW11_PS3, + PMUX_PINGRP_KB_ROW12_PS4, + PMUX_PINGRP_KB_ROW13_PS5, + PMUX_PINGRP_KB_ROW14_PS6, + PMUX_PINGRP_KB_ROW15_PS7, + PMUX_PINGRP_KB_COL0_PQ0, + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_SYS_CLK_REQ_PZ5, + PMUX_PINGRP_CORE_PWR_REQ, + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_CLK1_REQ_PEE2, + PMUX_PINGRP_CLK1_OUT_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_SPI2_MOSI_PX0, + PMUX_PINGRP_SPI2_MISO_PX1, + PMUX_PINGRP_SPI2_CS0_N_PX3, + PMUX_PINGRP_SPI2_SCK_PX2, + PMUX_PINGRP_SPI1_MOSI_PX4, + PMUX_PINGRP_SPI1_SCK_PX5, + PMUX_PINGRP_SPI1_CS0_N_PX6, + PMUX_PINGRP_SPI1_MISO_PX7, + PMUX_PINGRP_SPI2_CS1_N_PW2, + PMUX_PINGRP_SPI2_CS2_N_PW3, + PMUX_PINGRP_SDMMC3_CLK_PA6, + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_SDMMC3_DAT4_PD1, + PMUX_PINGRP_SDMMC3_DAT5_PD0, + PMUX_PINGRP_SDMMC3_DAT6_PD3, + PMUX_PINGRP_SDMMC3_DAT7_PD4, + PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0, + PMUX_PINGRP_PEX_L0_RST_N_PDD1, + PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, + PMUX_PINGRP_PEX_WAKE_N_PDD3, + PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4, + PMUX_PINGRP_PEX_L1_RST_N_PDD5, + PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, + PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7, + PMUX_PINGRP_PEX_L2_RST_N_PCC6, + PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7, + PMUX_PINGRP_HDMI_CEC_PEE3, + PMUX_PINGRP_COUNT, }; -enum pdrive_pingrp { - PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ - PDRIVE_PINGROUP_AO2, - PDRIVE_PINGROUP_AT1, - PDRIVE_PINGROUP_AT2, - PDRIVE_PINGROUP_AT3, - PDRIVE_PINGROUP_AT4, - PDRIVE_PINGROUP_AT5, - PDRIVE_PINGROUP_CDEV1, - PDRIVE_PINGROUP_CDEV2, - PDRIVE_PINGROUP_CSUS, - PDRIVE_PINGROUP_DAP1, - PDRIVE_PINGROUP_DAP2, - PDRIVE_PINGROUP_DAP3, - PDRIVE_PINGROUP_DAP4, - PDRIVE_PINGROUP_DBG, - PDRIVE_PINGROUP_LCD1, - PDRIVE_PINGROUP_LCD2, - PDRIVE_PINGROUP_SDIO2, - PDRIVE_PINGROUP_SDIO3, - PDRIVE_PINGROUP_SPI, - PDRIVE_PINGROUP_UAA, - PDRIVE_PINGROUP_UAB, - PDRIVE_PINGROUP_UART2, - PDRIVE_PINGROUP_UART3, - PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */ - PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */ - PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */ - PDRIVE_PINGROUP_DDC, - PDRIVE_PINGROUP_GMA, - PDRIVE_PINGROUP_GMB, - PDRIVE_PINGROUP_GMC, - PDRIVE_PINGROUP_GMD, - PDRIVE_PINGROUP_GME, - PDRIVE_PINGROUP_GMF, - PDRIVE_PINGROUP_GMG, - PDRIVE_PINGROUP_GMH, - PDRIVE_PINGROUP_OWR, - PDRIVE_PINGROUP_UAD, - PDRIVE_PINGROUP_GPV, - PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ - PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ - PDRIVE_PINGROUP_COUNT, +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_CSUS, + PMUX_DRVGRP_DAP1, + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_LCD1, + PMUX_DRVGRP_LCD2, + PMUX_DRVGRP_SDIO2, + PMUX_DRVGRP_SDIO3, + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_VI1, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_CRT = (0x90 / 4), + PMUX_DRVGRP_DDC, + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GMB, + PMUX_DRVGRP_GMC, + PMUX_DRVGRP_GMD, + PMUX_DRVGRP_GME, + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_GPV, + PMUX_DRVGRP_DEV3, + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_COUNT, }; -/* - * Functions which can be assigned to each of the pin groups. The values here - * bear no relation to the values programmed into pinmux registers and are - * purely a convenience. The translation is done through a table search. - */ enum pmux_func { - PMUX_FUNC_AHB_CLK, - PMUX_FUNC_APB_CLK, - PMUX_FUNC_AUDIO_SYNC, + PMUX_FUNC_DEFAULT, + PMUX_FUNC_BLINK, + PMUX_FUNC_CEC, + PMUX_FUNC_CLK_12M_OUT, + PMUX_FUNC_CLK_32K_IN, + PMUX_FUNC_CORE_PWR_REQ, + PMUX_FUNC_CPU_PWR_REQ, PMUX_FUNC_CRT, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DAP3, - PMUX_FUNC_DAP4, - PMUX_FUNC_DAP5, - PMUX_FUNC_DISPA, - PMUX_FUNC_DISPB, - PMUX_FUNC_EMC_TEST0_DLL, - PMUX_FUNC_EMC_TEST1_DLL, + PMUX_FUNC_DAP, + PMUX_FUNC_DDR, + PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DTV, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, PMUX_FUNC_GMI, - PMUX_FUNC_GMI_INT, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HDCP, PMUX_FUNC_HDMI, + PMUX_FUNC_HSI, PMUX_FUNC_I2C1, PMUX_FUNC_I2C2, PMUX_FUNC_I2C3, - PMUX_FUNC_IDE, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_INVALID, PMUX_FUNC_KBC, PMUX_FUNC_MIO, - PMUX_FUNC_MIPI_HS, PMUX_FUNC_NAND, - PMUX_FUNC_OSC, + PMUX_FUNC_NAND_ALT, PMUX_FUNC_OWR, PMUX_FUNC_PCIE, - PMUX_FUNC_PLLA_OUT, - PMUX_FUNC_PLLC_OUT1, - PMUX_FUNC_PLLM_OUT1, - PMUX_FUNC_PLLP_OUT2, - PMUX_FUNC_PLLP_OUT3, - PMUX_FUNC_PLLP_OUT4, - PMUX_FUNC_PWM, - PMUX_FUNC_PWR_INTR, - PMUX_FUNC_PWR_ON, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_PWR_INT_N, PMUX_FUNC_RTCK, + PMUX_FUNC_SATA, PMUX_FUNC_SDMMC1, PMUX_FUNC_SDMMC2, PMUX_FUNC_SDMMC3, PMUX_FUNC_SDMMC4, - PMUX_FUNC_SFLASH, PMUX_FUNC_SPDIF, PMUX_FUNC_SPI1, PMUX_FUNC_SPI2, PMUX_FUNC_SPI2_ALT, PMUX_FUNC_SPI3, PMUX_FUNC_SPI4, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYSCLK, + PMUX_FUNC_TEST, PMUX_FUNC_TRACE, - PMUX_FUNC_TWC, PMUX_FUNC_UARTA, PMUX_FUNC_UARTB, PMUX_FUNC_UARTC, PMUX_FUNC_UARTD, PMUX_FUNC_UARTE, PMUX_FUNC_ULPI, - PMUX_FUNC_VI, - PMUX_FUNC_VI_SENSOR_CLK, - PMUX_FUNC_XIO, - PMUX_FUNC_BLINK, - PMUX_FUNC_CEC, - PMUX_FUNC_CLK12, - PMUX_FUNC_DAP, - PMUX_FUNC_DAPSDMMC2, - PMUX_FUNC_DDR, - PMUX_FUNC_DEV3, - PMUX_FUNC_DTV, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT2, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_EMC_DLL, - PMUX_FUNC_EXTPERIPH1, - PMUX_FUNC_EXTPERIPH2, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_GMI_ALT, - PMUX_FUNC_HDA, - PMUX_FUNC_HSI, - PMUX_FUNC_I2C4, - PMUX_FUNC_I2C5, - PMUX_FUNC_I2CPWR, - PMUX_FUNC_I2S0, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4, - PMUX_FUNC_NAND_ALT, - PMUX_FUNC_POPSDIO4, - PMUX_FUNC_POPSDMMC4, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_SATA, - PMUX_FUNC_SPI5, - PMUX_FUNC_SPI6, - PMUX_FUNC_SYSCLK, PMUX_FUNC_VGP1, PMUX_FUNC_VGP2, PMUX_FUNC_VGP3, PMUX_FUNC_VGP4, PMUX_FUNC_VGP5, PMUX_FUNC_VGP6, - PMUX_FUNC_CLK_12M_OUT, - PMUX_FUNC_HDCP, - PMUX_FUNC_TEST, - PMUX_FUNC_CORE_PWR_REQ, - PMUX_FUNC_CPU_PWR_REQ, - PMUX_FUNC_PWR_INT_N, - PMUX_FUNC_CLK_32K_IN, - PMUX_FUNC_SAFE, - - PMUX_FUNC_MAX, - - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, -}; - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \ - || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) - -/* return 1 if a pingrp is in range */ -#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; -/* return 1 if a pin_pupd_is in range */ -#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ - ((pupd) <= PMUX_PULL_UP)) - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; -/* return 1 if a pin_tristate_is in range */ -#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \ - && ((tristate) <= PMUX_TRI_TRISTATE)) - -enum pmux_pin_io { - PMUX_PIN_OUTPUT = 0, - PMUX_PIN_INPUT = 1, -}; -/* return 1 if a pin_io_is in range */ -#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ - ((io) <= PMUX_PIN_INPUT)) - -enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, - PMUX_PIN_LOCK_ENABLE, -}; -/* return 1 if a pin_lock is in range */ -#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ - ((lock) <= PMUX_PIN_LOCK_ENABLE)) - -enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, - PMUX_PIN_OD_ENABLE, -}; -/* return 1 if a pin_od is in range */ -#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ - ((od) <= PMUX_PIN_OD_ENABLE)) - -enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, - PMUX_PIN_IO_RESET_ENABLE, -}; -/* return 1 if a pin_ioreset_is in range */ -#define pmux_pin_ioreset_isvalid(ioreset) \ - (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ - ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) - -/* Available power domains used by pin groups */ -enum pmux_vddio { - PMUX_VDDIO_BB = 0, - PMUX_VDDIO_LCD, - PMUX_VDDIO_VI, - PMUX_VDDIO_UART, - PMUX_VDDIO_DDR, - PMUX_VDDIO_NAND, - PMUX_VDDIO_SYS, - PMUX_VDDIO_AUDIO, - PMUX_VDDIO_SD, - PMUX_VDDIO_CAM, - PMUX_VDDIO_GMI, - PMUX_VDDIO_PEXCTL, - PMUX_VDDIO_SDMMC1, - PMUX_VDDIO_SDMMC3, - PMUX_VDDIO_SDMMC4, - - PMUX_VDDIO_NONE -}; - -#define PGRP_SLWF_NONE -1 -#define PGRP_SLWF_MAX 3 -#define PGRP_SLWR_NONE PGRP_SLWF_NONE -#define PGRP_SLWR_MAX PGRP_SLWF_MAX - -#define PGRP_DRVUP_NONE -1 -#define PGRP_DRVUP_MAX 127 -#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE -#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX - -/* return 1 if a padgrp is in range */ -#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) - -/* return 1 if a slew-rate rising/falling edge value is in range */ -#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)) - -/* return 1 if a driver output pull-up/down strength code value is in range */ -#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)) - -/* return 1 if a low-power mode value is in range */ -#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)) - -/* Defines a pin group cfg's low-power mode select */ -enum pgrp_lpmd { - PGRP_LPMD_X8 = 0, - PGRP_LPMD_X4, - PGRP_LPMD_X2, - PGRP_LPMD_X, - PGRP_LPMD_NONE = -1, -}; - -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pgrp_schmt { - PGRP_SCHMT_DISABLE = 0, - PGRP_SCHMT_ENABLE = 1, -}; - -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pgrp_hsm { - PGRP_HSM_DISABLE = 0, - PGRP_HSM_ENABLE = 1, -}; - -/* - * This defines the configuration for a pin group's pad control config - */ -struct padctrl_config { - enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ - int slwf; /* falling edge slew */ - int slwr; /* rising edge slew */ - int drvup; /* pull-up drive strength */ - int drvdn; /* pull-down drive strength */ - enum pgrp_lpmd lpmd; /* low-power mode selection */ - enum pgrp_schmt schmt; /* schmidt enable */ - enum pgrp_hsm hsm; /* high-speed mode enable */ -}; - -/* t30 pin drive group and pin mux registers */ -#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) -#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ - PDRIVE_PINGROUP_COUNT) -struct pmux_tri_ctlr { - uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ - uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ - uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ - uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ - uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ - uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */ - uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ - - uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ - - uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ - uint pmt_reserved5[PMUX_OFFSET]; - uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */ -}; - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ - enum pmux_pin_io io; /* input or output PMUX_PIN_... */ - enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ - enum pmux_pin_od od; /* open-drain or push-pull driver */ - enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT2, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, }; -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(struct pingroup_config *config); - -/* Set a pin group to tristate or normal */ -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - -/* Set a pin group as input or output */ -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); - -/** - * Configure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_table(struct pingroup_config *config, int len); - -/* Set a group of pins from a table */ -void pinmux_init(void); - -/** - * Set the GP pad configs - * - * @param config List of config items - * @param len Number of config items in list - */ -void padgrp_config_table(struct padctrl_config *config, int len); +#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#define TEGRA_PMX_HAS_DRVGRPS +#include -#endif /* _TEGRA30_PINMUX_H_ */ +#endif /* _TEGRA30_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/powergate.h b/arch/arm/include/asm/arch-tegra30/powergate.h new file mode 100644 index 0000000000..c70e44b621 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/powergate.h @@ -0,0 +1,6 @@ +#ifndef _TEGRA30_POWERGATE_H_ +#define _TEGRA30_POWERGATE_H_ + +#include + +#endif /* _TEGRA30_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/spl.h b/arch/arm/include/asm/arch-tegra30/spl.h deleted file mode 100644 index 8953b00a9f..0000000000 --- a/arch/arm/include/asm/arch-tegra30/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index c02c5d8500..93671793a9 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -17,6 +17,7 @@ #ifndef _TEGRA30_H_ #define _TEGRA30_H_ +#define NV_PA_MC_BASE 0x7000F000 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ #include diff --git a/arch/arm/include/asm/arch-tegra30/usb.h b/arch/arm/include/asm/arch-tegra30/usb.h deleted file mode 100644 index ab9b760b02..0000000000 --- a/arch/arm/include/asm/arch-tegra30/usb.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA30_USB_H_ -#define _TEGRA30_USB_H_ - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[2]; - - /* 0x130 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x140 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint reserved5_1; - - /* 0x150 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; - uint icusb_ctrl; - - /* 0x160 */ - uint ulpi_viewport; - uint reserved7[3]; - - /* 0x170 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x190 */ - uint reserved9[8]; - - /* 0x1b0 */ - uint reserved10; - uint hostpc1_devlc; - uint reserved10_1[2]; - - /* 0x1c0 */ - uint reserved10_2[4]; - - /* 0x1d0 */ - uint reserved10_3[4]; - - /* 0x1e0 */ - uint reserved10_4[4]; - - /* 0x1f0 */ - uint reserved10_5; - uint otgsc; - uint usb_mode; - uint reserved10_6; - - /* 0x200 */ - uint endpt_nak; - uint endpt_nak_enable; - uint endpt_setup_stat; - uint reserved11_1[0x7D]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -/* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) - -/* USB2D_HOSTPC1_DEVLC_0 */ -#define PTS_SHIFT 29 -#define PTS_MASK (0x7U << PTS_SHIFT) - -#define STS (1 << 28) -#endif /* _TEGRA30_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h deleted file mode 100644 index 9969a018e7..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h index aed6c46f64..d458e0bdf0 100644 --- a/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h @@ -9,7 +9,7 @@ #ifndef __ASSEMBLY__ -#include +#include #define ASYNC_EMIF_NUM_CS 4 #define ASYNC_EMIF_MODE_NOR 0 @@ -155,4 +155,6 @@ int wdt_kick(void); #define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) #define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h deleted file mode 100644 index b298fba905..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * TNETV107X: NAND definitions - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include -#include - -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/arch/arm/include/asm/arch-uniphier/arm-mpcore.h b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h new file mode 100644 index 0000000000..cf7cd46c10 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_ARM_MPCORE_H +#define ARCH_ARM_MPCORE_H + +/* Snoop Control Unit */ +#define SCU_OFFSET 0x00 + +/* SCU Control Register */ +#define SCU_CTRL 0x00 +/* SCU Configuration Register */ +#define SCU_CONF 0x04 +/* SCU CPU Power Status Register */ +#define SCU_PWR_STATUS 0x08 +/* SCU Invalidate All Registers in Secure State */ +#define SCU_INV_ALL 0x0C +/* SCU Filtering Start Address Register */ +#define SCU_FILTER_START 0x40 +/* SCU Filtering End Address Register */ +#define SCU_FILTER_END 0x44 +/* SCU Access Control Register */ +#define SCU_SAC 0x50 +/* SCU Non-secure Access Control Register */ +#define SCU_SNSAC 0x54 + +/* Global Timer */ +#define GLOBAL_TIMER_OFFSET 0x200 + +/* Global Timer Counter Registers */ +#define GTIMER_CNT_L 0x00 +#define GTIMER_CNT_H 0x04 +/* Global Timer Control Register */ +#define GTIMER_CTRL 0x08 +/* Global Timer Interrupt Status Register */ +#define GTIMER_STAT 0x0C +/* Comparator Value Registers */ +#define GTIMER_CMP_L 0x10 +#define GTIMER_CMP_H 0x14 +/* Auto-increment Register */ +#define GTIMER_INC 0x18 + +#endif /* ARCH_ARM_MPCORE_H */ diff --git a/arch/arm/include/asm/arch-uniphier/bcu-regs.h b/arch/arm/include/asm/arch-uniphier/bcu-regs.h new file mode 100644 index 0000000000..0dfd94e5d7 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/bcu-regs.h @@ -0,0 +1,30 @@ +/* + * UniPhier BCU (Bus Control Unit) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_BCU_REGS_H +#define ARCH_BCU_REGS_H + +#define BCU_BASE 0x50080000 + +#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4) +#define BCSCR0 (BCSCR(0)) +#define BCSCR1 (BCSCR(1)) +#define BCSCR2 (BCSCR(2)) +#define BCSCR3 (BCSCR(3)) +#define BCSCR4 (BCSCR(4)) +#define BCSCR5 (BCSCR(5)) + +#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4) +#define BCIPPCCHR0 (BCIPPCCHR(0)) +#define BCIPPCCHR1 (BCIPPCCHR(1)) +#define BCIPPCCHR2 (BCIPPCCHR(2)) +#define BCIPPCCHR3 (BCIPPCCHR(3)) +#define BCIPPCCHR4 (BCIPPCCHR(4)) +#define BCIPPCCHR5 (BCIPPCCHR(5)) + +#endif /* ARCH_BCU_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/board.h b/arch/arm/include/asm/arch-uniphier/board.h new file mode 100644 index 0000000000..e3cba5befe --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/board.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_BOARD_H +#define ARCH_BOARD_H + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \ + defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +void support_card_reset(void); +void support_card_init(void); +void support_card_late_init(void); +int check_support_card(void); +#else +#define support_card_reset() do {} while (0) +#define support_card_init() do {} while (0) +#define support_card_late_init() do {} while (0) +static inline int check_support_card(void) +{ + return 0; +} +#endif + +static inline void uniphier_board_reset(void) +{ + support_card_reset(); +} + +static inline void uniphier_board_init(void) +{ + support_card_init(); +} + +static inline void uniphier_board_late_init(void) +{ + support_card_late_init(); +} + +#endif /* ARCH_BOARD_H */ diff --git a/arch/arm/include/asm/arch-uniphier/boot-device.h b/arch/arm/include/asm/arch-uniphier/boot-device.h new file mode 100644 index 0000000000..6987f57669 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/boot-device.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_BOOT_DEVICE_H_ +#define _ASM_BOOT_DEVICE_H_ + +u32 get_boot_mode_sel(void); + +struct boot_device_info { + u32 type; + char *info; +}; + +extern struct boot_device_info boot_device_table[]; + +#endif /* _ASM_BOOT_DEVICE_H_ */ diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h new file mode 100644 index 0000000000..6b7d600a9c --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h @@ -0,0 +1,172 @@ +/* + * UniPhier DDR PHY registers + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_DDRPHY_REGS_H +#define ARCH_DDRPHY_REGS_H + +#include + +#ifndef __ASSEMBLY__ + +struct ddrphy { + u32 ridr; /* Revision Identification Register */ + u32 pir; /* PHY Initialixation Register */ + u32 pgcr[2]; /* PHY General Configuration Register */ + u32 pgsr[2]; /* PHY General Status Register */ + u32 pllcr; /* PLL Control Register */ + u32 ptr[5]; /* PHY Timing Register */ + u32 acmdlr; /* AC Master Delay Line Register */ + u32 acbdlr; /* AC Bit Delay Line Register */ + u32 aciocr; /* AC I/O Configuration Register */ + u32 dxccr; /* DATX8 Common Configuration Register */ + u32 dsgcr; /* DDR System General Configuration Register */ + u32 dcr; /* DRAM Configuration Register */ + u32 dtpr[3]; /* DRAM Timing Parameters Register */ + u32 mr0; /* Mode Register 0 */ + u32 mr1; /* Mode Register 1 */ + u32 mr2; /* Mode Register 2 */ + u32 mr3; /* Mode Register 3 */ + u32 odtcr; /* ODT Configuration Register */ + u32 dtcr; /* Data Training Configuration Register */ + u32 dtar[4]; /* Data Training Address Register */ + u32 dtdr[2]; /* Data Training Data Register */ + u32 dtedr[2]; /* Data Training Eye Data Register */ + u32 rsv0[13]; /* Reserved */ + u32 dcuar; /* DCU Address Register */ + u32 dcudr; /* DCU Data Register */ + u32 dcurr; /* DCU Run Register */ + u32 dculr; /* DCU Loop Register */ + u32 dcugcr; /* DCU General Configuration Register */ + u32 dcutpr; /* DCU Timing Parameters Register */ + u32 dcusr[2]; /* DCU Status Register */ + u32 rsv1[8]; /* Reserved */ + u32 bistrr; /* BIST Run Register */ + u32 bistwcr; /* BIST Word Count Register */ + u32 bistmskr[3]; /* BIST Mask Register */ + u32 bistlsr; /* BIST LFSR Sed Register */ + u32 bistar[3]; /* BIST Address Register */ + u32 bistudpr; /* BIST User Data Pattern Register */ + u32 bistgsr; /* BIST General Status Register */ + u32 bistwer; /* BIST Word Error Register */ + u32 bistber[4]; /* BIST Bit Error Register */ + u32 bistwcsr; /* BIST Word Count Status Register */ + u32 bistfwr[3]; /* BIST Fail Word Register */ + u32 rsv2[10]; /* Reserved */ + u32 gpr[2]; /* General Purpose Register */ + struct ddrphy_zq { /* ZQ */ + u32 cr[2]; /* Impedance Control Register */ + u32 sr[2]; /* Impedance Status Register */ + } zq[4]; + struct ddrphy_datx8 { /* DATX8 */ + u32 gcr; /* General Configuration Register */ + u32 gsr[2]; /* General Status Register */ + u32 bdlr[5]; /* Bit Delay Line Register */ + u32 lcdlr[3]; /* Local Calibrated Delay Line Register */ + u32 mdlr; /* Master Delay Line Register */ + u32 gtr; /* General Timing Register */ + u32 rsv[3]; /* Reserved */ + } dx[9]; +}; + +#endif /* __ASSEMBLY__ */ + +#define PIR_INIT (1 << 0) /* Initialization Trigger */ +#define PIR_ZCAL (1 << 1) /* Impedance Calibration */ +#define PIR_PLLINIT (1 << 4) /* PLL Initialization */ +#define PIR_DCAL (1 << 5) /* DDL Calibration */ +#define PIR_PHYRST (1 << 6) /* PHY Reset */ +#define PIR_DRAMRST (1 << 7) /* DRAM Reset */ +#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */ +#define PIR_WL (1 << 9) /* Write Leveling */ +#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */ +#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */ +#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */ +#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */ +#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */ +#define PIR_WREYE (1 << 15) /* Write Data Eye Training */ +#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */ +#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */ +#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */ +#define PIR_INITBYP (1 << 31) /* Initialization Bypass */ + +#define PGSR0_IDONE (1 << 0) /* Initialization Done */ +#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */ +#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */ +#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */ +#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */ +#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */ +#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */ +#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */ +#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */ +#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */ +#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */ +#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */ +#define PGSR0_IERR (1 << 16) /* Initialization Error */ +#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */ +#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */ +#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */ +#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */ +#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */ +#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */ +#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */ +#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */ +#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */ +#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */ +#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */ +#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ +#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT)) +#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */ + +#define DXCCR_DQSRES_OPEN (0 << 5) +#define DXCCR_DQSRES_688_OHM (1 << 5) +#define DXCCR_DQSRES_611_OHM (2 << 5) +#define DXCCR_DQSRES_550_OHM (3 << 5) +#define DXCCR_DQSRES_500_OHM (4 << 5) +#define DXCCR_DQSRES_458_OHM (5 << 5) +#define DXCCR_DQSRES_393_OHM (6 << 5) +#define DXCCR_DQSRES_344_OHM (7 << 5) + +#define DXCCR_DQSNRES_OPEN (0 << 9) +#define DXCCR_DQSNRES_688_OHM (1 << 9) +#define DXCCR_DQSNRES_611_OHM (2 << 9) +#define DXCCR_DQSNRES_550_OHM (3 << 9) +#define DXCCR_DQSNRES_500_OHM (4 << 9) +#define DXCCR_DQSNRES_458_OHM (5 << 9) +#define DXCCR_DQSNRES_393_OHM (6 << 9) +#define DXCCR_DQSNRES_344_OHM (7 << 9) + +#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ +#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) +#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ +#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ +#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) + +#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ +#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT)) + +/* SoC-specific parameters */ +#define NR_DATX8_PER_DDRPHY 2 + +#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#define NR_DDRPHY_PER_CH 1 +#else +#define NR_DDRPHY_PER_CH 2 +#endif + +#define NR_DDRCH 2 + +#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) + +#ifndef __ASSEMBLY__ +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); +int ddrphy_training(struct ddrphy __iomem *phy); +#endif + +#endif /* ARCH_DDRPHY_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/debug-uart.S b/arch/arm/include/asm/arch-uniphier/debug-uart.S new file mode 100644 index 0000000000..af55feed04 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/debug-uart.S @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#if !defined(CONFIG_DEBUG_SEMIHOSTING) +#include CONFIG_DEBUG_LL_INCLUDE +#endif + +#define BAUDRATE 115200 +#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) +#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE) + + .macro init_debug_uart, ra, rb, rc + addruart \ra, \rb, \rc + mov \rb, #UART_LCR_WLEN8 + strb \rb, [\ra, #0x11] + ldr \rb, =DIVISOR + str \rb, [\ra, #0x24] + .endm diff --git a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h new file mode 100644 index 0000000000..e9c5fb4af8 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLAT_UNIPHIER_EHCI_H +#define __PLAT_UNIPHIER_EHCI_H + +#include +#include +#include "mio-regs.h" + +struct uniphier_ehci_platform_data { + unsigned long base; +}; + +extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[]; + +static inline void uniphier_ehci_reset(int index, int on) +{ + u32 tmp; + + tmp = readl(MIO_USB_RSTCTRL(index)); + if (on) + tmp &= ~MIO_USB_RSTCTRL_XRST; + else + tmp |= MIO_USB_RSTCTRL_XRST; + writel(tmp, MIO_USB_RSTCTRL(index)); +} + +#endif /* __PLAT_UNIPHIER_EHCI_H */ diff --git a/arch/arm/include/asm/arch-uniphier/gpio.h b/arch/arm/include/asm/arch-uniphier/gpio.h new file mode 100644 index 0000000000..1fc4e19a61 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/gpio.h @@ -0,0 +1,6 @@ +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes via , so those SoCs that enable + * OF_CONTROL must have arch/gpio.h even if GPIO is not supported. + */ diff --git a/arch/arm/include/asm/arch-uniphier/led.h b/arch/arm/include/asm/arch-uniphier/led.h new file mode 100644 index 0000000000..21277dac76 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/led.h @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_LED_H +#define ARCH_LED_H + +#include + +#define LED_CHAR_0 0x7e +#define LED_CHAR_1 0x0c +#define LED_CHAR_2 0xb6 +#define LED_CHAR_3 0x9e +#define LED_CHAR_4 0xcc +#define LED_CHAR_5 0xda +#define LED_CHAR_6 0xfa +#define LED_CHAR_7 0x4e +#define LED_CHAR_8 0xfe +#define LED_CHAR_9 0xde + +#define LED_CHAR_A 0xee +#define LED_CHAR_B 0xf8 +#define LED_CHAR_C 0x72 +#define LED_CHAR_D 0xbc +#define LED_CHAR_E 0xf2 +#define LED_CHAR_F 0xe2 +#define LED_CHAR_G 0x7a +#define LED_CHAR_H 0xe8 +#define LED_CHAR_I 0x08 +#define LED_CHAR_J 0x3c +#define LED_CHAR_K 0xea +#define LED_CHAR_L 0x70 +#define LED_CHAR_M 0x6e +#define LED_CHAR_N 0xa8 +#define LED_CHAR_O 0xb8 +#define LED_CHAR_P 0xe6 +#define LED_CHAR_Q 0xce +#define LED_CHAR_R 0xa0 +#define LED_CHAR_S 0xc8 +#define LED_CHAR_T 0x8c +#define LED_CHAR_U 0x7c +#define LED_CHAR_V 0x54 +#define LED_CHAR_W 0xfc +#define LED_CHAR_X 0xec +#define LED_CHAR_Y 0xdc +#define LED_CHAR_Z 0xa4 + +#define LED_CHAR_SPACE 0x00 +#define LED_CHAR_DOT 0x01 + +#define LED_CHAR_ (LED_CHAR_SPACE) + +/** Macro to translate 4 characters into integer to display led */ +#define LED_C2I(C0, C1, C2, C3) \ + (~( \ + (LED_CHAR_##C0 << 24) | \ + (LED_CHAR_##C1 << 16) | \ + (LED_CHAR_##C2 << 8) | \ + (LED_CHAR_##C3) \ + )) + +#if defined(CONFIG_SUPPORT_CARD_LED_BASE) + +#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE + +#ifdef __ASSEMBLY__ + +#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3) +.macro raw_led_write data + ldr r0, =\data + ldr r1, =LED_ADDR + str r0, [r1] +.endm + +#else /* __ASSEMBLY__ */ + +#include + +#define led_write(C0, C1, C2, C3) \ +do { \ + raw_led_write(LED_C2I(C0, C1, C2, C3)); \ +} while (0) + +static inline void raw_led_write(u32 data) +{ + writel(data, LED_ADDR); +} + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_SUPPORT_CARD_LED_BASE */ + +#define led_write(C0, C1, C2, C3) +#define raw_led_write(x) + +#endif /* CONFIG_SUPPORT_CARD_LED_BASE */ + +#endif /* ARCH_LED_H */ diff --git a/arch/arm/include/asm/arch-uniphier/mio-regs.h b/arch/arm/include/asm/arch-uniphier/mio-regs.h new file mode 100644 index 0000000000..3306934ff7 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/mio-regs.h @@ -0,0 +1,20 @@ +/* + * UniPhier MIO (Media I/O) registers + * + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_MIO_REGS_H +#define ARCH_MIO_REGS_H + +#define MIO_BASE 0x59810000 + +#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020) +#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110) +#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114) + +#define MIO_USB_RSTCTRL_XRST (0x1 << 0) + +#endif /* ARCH_MIO_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/include/asm/arch-uniphier/platdevice.h new file mode 100644 index 0000000000..62a512659c --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/platdevice.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_PLATDEVICE_H +#define ARCH_PLATDEVICE_H + +#include +#include + +#define SERIAL_DEVICE(n, ba, clk) \ +static struct uniphier_serial_platform_data serial_device##n = { \ + .base = ba, \ + .uartclk = clk \ +}; \ +U_BOOT_DEVICE(serial##n) = { \ + .name = DRIVER_NAME, \ + .platdata = &serial_device##n \ +}; + +#include + +#endif /* ARCH_PLATDEVICE_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sbc-regs.h b/arch/arm/include/asm/arch-uniphier/sbc-regs.h new file mode 100644 index 0000000000..efb68e8564 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/sbc-regs.h @@ -0,0 +1,109 @@ +/* + * UniPhier SBC (System Bus Controller) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SBC_REGS_H +#define ARCH_SBC_REGS_H + +#define SBBASE_BASE 0x58c00100 +#define SBBASE(x) (SBBASE_BASE + (x) * 0x10) + +#define SBBASE0 (SBBASE(0)) +#define SBBASE1 (SBBASE(1)) +#define SBBASE2 (SBBASE(2)) +#define SBBASE3 (SBBASE(3)) +#define SBBASE4 (SBBASE(4)) +#define SBBASE5 (SBBASE(5)) +#define SBBASE6 (SBBASE(6)) +#define SBBASE7 (SBBASE(7)) + +#define SBBASE_BANK_ENABLE (0x00000001) + +#define SBCTRL_BASE 0x58c00200 +#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4) + +#define SBCTRL00 SBCTRL(0, 0) +#define SBCTRL01 SBCTRL(0, 1) +#define SBCTRL02 SBCTRL(0, 2) +#define SBCTRL03 SBCTRL(0, 3) +#define SBCTRL04 (SBCTRL_BASE + 0x100) + +#define SBCTRL10 SBCTRL(1, 0) +#define SBCTRL11 SBCTRL(1, 1) +#define SBCTRL12 SBCTRL(1, 2) +#define SBCTRL13 SBCTRL(1, 3) +#define SBCTRL14 (SBCTRL_BASE + 0x110) + +#define SBCTRL20 SBCTRL(2, 0) +#define SBCTRL21 SBCTRL(2, 1) +#define SBCTRL22 SBCTRL(2, 2) +#define SBCTRL23 SBCTRL(2, 3) +#define SBCTRL24 (SBCTRL_BASE + 0x120) + +#define SBCTRL30 SBCTRL(3, 0) +#define SBCTRL31 SBCTRL(3, 1) +#define SBCTRL32 SBCTRL(3, 2) +#define SBCTRL33 SBCTRL(3, 3) +#define SBCTRL34 (SBCTRL_BASE + 0x130) + +#define SBCTRL40 SBCTRL(4, 0) +#define SBCTRL41 SBCTRL(4, 1) +#define SBCTRL42 SBCTRL(4, 2) +#define SBCTRL43 SBCTRL(4, 3) +#define SBCTRL44 (SBCTRL_BASE + 0x140) + +#define SBCTRL50 SBCTRL(5, 0) +#define SBCTRL51 SBCTRL(5, 1) +#define SBCTRL52 SBCTRL(5, 2) +#define SBCTRL53 SBCTRL(5, 3) +#define SBCTRL54 (SBCTRL_BASE + 0x150) + +#define SBCTRL60 SBCTRL(6, 0) +#define SBCTRL61 SBCTRL(6, 1) +#define SBCTRL62 SBCTRL(6, 2) +#define SBCTRL63 SBCTRL(6, 3) +#define SBCTRL64 (SBCTRL_BASE + 0x160) + +#define SBCTRL70 SBCTRL(7, 0) +#define SBCTRL71 SBCTRL(7, 1) +#define SBCTRL72 SBCTRL(7, 2) +#define SBCTRL73 SBCTRL(7, 3) +#define SBCTRL74 (SBCTRL_BASE + 0x170) + +/* slower but LED works */ +#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000 +#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00 +#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009 +#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110 + +/* faster but LED does not work */ +#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000 +#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700 +/* NOR flash needs more wait counts than SRAM */ +#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009 +#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210 + +#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000 +#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500 +#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020 + +#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000 +#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500 +#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010 + +#define PC0CTRL 0x598000c0 +#define ROM_BOOT_ROMRSV2 0x59801208 + +#ifndef __ASSEMBLY__ +#include +static inline int boot_is_swapped(void) +{ + return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); +} +#endif + +#endif /* ARCH_SBC_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h new file mode 100644 index 0000000000..1197bb52d4 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h @@ -0,0 +1,62 @@ +/* + * UniPhier SC (System Control) block registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SC_REGS_H +#define ARCH_SC_REGS_H + +#define SC_BASE_ADDR 0x61840000 + +#define SC_MPLLOSCCTL (SC_BASE_ADDR | 0x1184) +#define SC_MPLLOSCCTL_MPLLEN (0x1 << 0) +#define SC_MPLLOSCCTL_MPLLST (0x1 << 1) + +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) +#define SC_DPLLCTRL_SSC_EN (0x1 << 31) +#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) +#define SC_DPLLCTRL_SSC_RATE (0x1 << 15) + +#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) +#define SC_DPLLCTRL2_NRSTDS (0x1 << 28) + +#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) +#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) +#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) + +#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) + +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) +#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) +#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) + +#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) +#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) +#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) + +#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL_NRST_ETHER (0x1 << 12) +#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) +#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) +#define SC_RSTCTRL_NRST_NAND (0x1 << 2) + +#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) +#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) + +#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) +#define SC_CLKCTRL_CLK_ETHER (0x1 << 12) +#define SC_CLKCTRL_CLK_MIO (0x1 << 11) +#define SC_CLKCTRL_CLK_UMC (0x1 << 4) +#define SC_CLKCTRL_CLK_NAND (0x1 << 2) +#define SC_CLKCTRL_CLK_SBC (0x1 << 1) +#define SC_CLKCTRL_CLK_PERI (0x1 << 0) + +/* System reset control register */ +#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) +#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) +#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) + +#endif /* ARCH_SC_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h new file mode 100644 index 0000000000..4ae67c8adb --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -0,0 +1,238 @@ +/* + * UniPhier SG (SoC Glue) block registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SG_REGS_H +#define ARCH_SG_REGS_H + +/* Base Address */ +#define SG_CTRL_BASE 0x5f800000 +#define SG_DBG_BASE 0x5f900000 + +/* Revision */ +#define SG_REVISION (SG_CTRL_BASE | 0x0000) +#define SG_REVISION_TYPE_SHIFT 16 +#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT) +#define SG_REVISION_MODEL_SHIFT 8 +#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT) +#define SG_REVISION_REV_SHIFT 0 +#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT) + +/* Memory Configuration */ +#define SG_MEMCONF (SG_CTRL_BASE | 0x0400) + +#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0)) +#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0)) +#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0)) +#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) +#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8) + +#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2)) +#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2)) +#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2)) +#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) +#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) + +#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) +#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) +#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) +#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) +#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) + +#define SG_MEMCONF_SPARSEMEM (0x1 << 4) + +/* Pin Control */ +#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) + +#if defined(CONFIG_MACH_PH1_PRO4) +# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8) +#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4) +#endif + +#if defined(CONFIG_MACH_PH1_PRO4) +#define SG_PINSELBITS 4 +#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#define SG_PINSELBITS 8 +#endif + +#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32)) +#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \ + ((n) * (SG_PINSELBITS) % 32))) +#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32)) + +/* Only for PH1-Pro4 */ +#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700) + +/* Input Enable */ +#define SG_IECTRL (SG_CTRL_BASE | 0x1d00) + +/* Pin Monitor */ +#define SG_PINMON0 (SG_DBG_BASE | 0x0100) + +#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19) + +#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16) + +#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) + +#ifdef __ASSEMBLY__ + + .macro set_pinsel, n, value, ra, rd + ldr \ra, =SG_PINSEL_ADDR(\n) + ldr \rd, [\ra] + and \rd, \rd, #SG_PINSEL_MASK(\n) + orr \rd, \rd, #SG_PINSEL_MODE(\n, \value) + str \rd, [\ra] + .endm + +#else + +#include +#include +#include + +static inline void sg_set_pinsel(int n, int value) +{ + writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n)) + | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n)); +} + +static inline u32 sg_memconf_val_ch0(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH0_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH0_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH0_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH0_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH0_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH0_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH0_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +static inline u32 sg_memconf_val_ch1(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH1_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH1_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH1_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH1_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH1_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH1_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH1_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +static inline u32 sg_memconf_val_ch2(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH2_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH2_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH2_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH2_SZ_512M; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH2_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH2_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} +#endif /* __ASSEMBLY__ */ + +#endif /* ARCH_SG_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/ssc-regs.h b/arch/arm/include/asm/arch-uniphier/ssc-regs.h new file mode 100644 index 0000000000..77b3470c6d --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/ssc-regs.h @@ -0,0 +1,67 @@ +/* + * UniPhier System Cache (L2 Cache) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SSC_REGS_H +#define ARCH_SSC_REGS_H + +#define SSCC 0x500c0000 +#define SSCC_BST (0x1 << 20) +#define SSCC_ACT (0x1 << 19) +#define SSCC_WTG (0x1 << 18) +#define SSCC_PRD (0x1 << 17) +#define SSCC_WBWA (0x1 << 16) +#define SSCC_EX (0x1 << 13) +#define SSCC_ON (0x1 << 0) + +#define SSCLPDAWCR 0x500c0030 + +#define SSCOPE 0x506c0244 +#define SSCOPE_CM_SYNC 0x00000008 + +#define SSCOQM 0x506c0248 +#define SSCOQM_TID_MASK (0x3 << 21) +#define SSCOQM_TID_BY_WAY (0x2 << 21) +#define SSCOQM_TID_BY_INST_WAY (0x1 << 21) +#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21) +#define SSCOQM_S_MASK (0x3 << 17) +#define SSCOQM_S_WAY (0x2 << 17) +#define SSCOQM_S_ALL (0x1 << 17) +#define SSCOQM_S_ADDRESS (0x0 << 17) +#define SSCOQM_CE (0x1 << 15) +#define SSCOQM_CW (0x1 << 14) +#define SSCOQM_CM_MASK (0x7) +#define SSCOQM_CM_DIRT_TOUCH (0x7) +#define SSCOQM_CM_ZERO_TOUCH (0x6) +#define SSCOQM_CM_NORM_TOUCH (0x5) +#define SSCOQM_CM_PREF_FETCH (0x4) +#define SSCOQM_CM_SSC_FETCH (0x3) +#define SSCOQM_CM_WB_INV (0x2) +#define SSCOQM_CM_WB (0x1) +#define SSCOQM_CM_INV (0x0) + +#define SSCOQAD 0x506c024c +#define SSCOQSZ 0x506c0250 +#define SSCOQWN 0x506c0258 + +#define SSCOPPQSEF 0x506c025c +#define SSCOPPQSEF_FE (0x1 << 1) +#define SSCOPPQSEF_OE (0x1 << 0) + +#define SSCOLPQS 0x506c0260 +#define SSCOLPQS_EF (0x1 << 2) +#define SSCOLPQS_EST (0x1 << 1) +#define SSCOLPQS_QST (0x1 << 0) + +#define SSCOQCE0 0x506c0270 + +#define SSC_LINE_SIZE 128 +#define SSC_NUM_ENTRIES 256 +#define SSC_WAY_SIZE ((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES)) +#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE)) + +#endif /* ARCH_SSC_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/umc-regs.h b/arch/arm/include/asm/arch-uniphier/umc-regs.h new file mode 100644 index 0000000000..6159281fd3 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/umc-regs.h @@ -0,0 +1,119 @@ +/* + * UniPhier UMC (Universal Memory Controller) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_UMC_REGS_H +#define ARCH_UMC_REGS_H + +#define UMC_BASE 0x5b800000 + +/* SSIF registers */ +#define UMC_SSIF_BASE UMC_BASE + +#define UMC_CPURST 0x00000700 +#define UMC_IDSRST 0x0000070C +#define UMC_IXMRST 0x00000714 +#define UMC_HDMRST 0x00000718 +#define UMC_MDMRST 0x0000071C +#define UMC_HDDRST 0x00000720 +#define UMC_MDDRST 0x00000724 +#define UMC_SIORST 0x00000728 +#define UMC_GIORST 0x0000072C +#define UMC_HD2RST 0x00000734 +#define UMC_VIORST 0x0000073C +#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */ +#define UMC_DVCRST 0x00000748 /* Pro4 */ +#define UMC_RGLRST 0x00000750 +#define UMC_VPERST 0x00000758 +#define UMC_AIORST 0x00000764 +#define UMC_DMDRST 0x00000770 + +#define UMC_HDMCHSEL 0x00000898 +#define UMC_MDMCHSEL 0x0000089C +#define UMC_DVCCHSEL 0x000008C8 +#define UMC_DMDCHSEL 0x000008F0 + +#define UMC_CLKEN_SSIF_FETCH 0x0000C060 +#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064 +#define UMC_CLKEN_SSIF_COMWC0 0x0000C068 +#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C +#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070 +#define UMC_CLKEN_SSIF_COMWC1 0x0000C074 +#define UMC_CLKEN_SSIF_COMRC1 0x0000C078 +#define UMC_CLKEN_SSIF_WC 0x0000C07C +#define UMC_CLKEN_SSIF_RC 0x0000C080 +#define UMC_CLKEN_SSIF_DST 0x0000C084 + +/* CA registers */ +#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch)) + +/* DRAM controller registers */ +#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch)) + +#define UMC_CMDCTLA 0x00000000 +#define UMC_CMDCTLB 0x00000004 +#define UMC_INITCTLA 0x00000008 +#define UMC_INITCTLB 0x0000000C +#define UMC_INITCTLC 0x00000010 +#define UMC_INITSET 0x00000014 +#define UMC_INITSTAT 0x00000018 +#define UMC_DRMMR0 0x0000001C +#define UMC_DRMMR1 0x00000020 +#define UMC_DRMMR2 0x00000024 +#define UMC_DRMMR3 0x00000028 +#define UMC_SPCCTLA 0x00000030 +#define UMC_SPCCTLB 0x00000034 +#define UMC_SPCSETA 0x00000038 +#define UMC_SPCSETB 0x0000003C +#define UMC_SPCSETC 0x00000040 +#define UMC_SPCSETD 0x00000044 +#define UMC_SPCSTATA 0x00000050 +#define UMC_SPCSTATB 0x00000054 +#define UMC_SPCSTATC 0x00000058 +#define UMC_ACSSETA 0x00000060 +#define UMC_FLOWCTLA 0x00000400 +#define UMC_FLOWCTLB 0x00000404 +#define UMC_FLOWCTLC 0x00000408 +#define UMC_FLOWCTLG 0x00000508 +#define UMC_RDATACTL_D0 0x00000600 +#define UMC_WDATACTL_D0 0x00000604 +#define UMC_RDATACTL_D1 0x00000608 +#define UMC_WDATACTL_D1 0x0000060C +#define UMC_DATASET 0x00000610 +#define UMC_DCCGCTL 0x00000720 +#define UMC_DICGCTLA 0x00000724 +#define UMC_DICGCTLB 0x00000728 +#define UMC_DIOCTLA 0x00000C00 +#define UMC_DFICUPDCTLA 0x00000C20 + +#ifndef __ASSEMBLY__ + +#include + +static inline void umc_polling(u32 address, u32 expval, u32 mask) +{ + u32 nmask = ~mask; + u32 data; + do { + data = readl(address) & nmask; + } while (data != expval); +} + +static inline void umc_dram_init_start(void __iomem *dramcont) +{ + writel(0x00000002, dramcont + UMC_INITSET); +} + +static inline void umc_dram_init_poll(void __iomem *dramcont) +{ + while ((readl(dramcont + UMC_INITSTAT) & 0x00000002)) + ; +} + +#endif + +#endif diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 85f1fda9f5..724682c683 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -55,57 +55,59 @@ struct ccm_reg { /* Analog components control digital interface (ANADIG) */ struct anadig_reg { + u32 reserved_0x000[4]; u32 pll3_ctrl; - u32 resv0[3]; + u32 reserved_0x014[3]; u32 pll7_ctrl; - u32 resv1[3]; + u32 reserved_0x024[3]; u32 pll2_ctrl; - u32 resv2[3]; + u32 reserved_0x034[3]; u32 pll2_ss; - u32 resv3[3]; + u32 reserved_0x044[3]; u32 pll2_num; - u32 resv4[3]; + u32 reserved_0x054[3]; u32 pll2_denom; - u32 resv5[3]; + u32 reserved_0x064[3]; u32 pll4_ctrl; - u32 resv6[3]; + u32 reserved_0x074[3]; u32 pll4_num; - u32 resv7[3]; + u32 reserved_0x084[3]; u32 pll4_denom; + u32 reserved_0x094[3]; u32 pll6_ctrl; - u32 resv8[3]; + u32 reserved_0x0A4[3]; u32 pll6_num; - u32 resv9[3]; + u32 reserved_0x0B4[3]; u32 pll6_denom; - u32 resv10[3]; + u32 reserved_0x0C4[7]; u32 pll5_ctrl; - u32 resv11[3]; + u32 reserved_0x0E4[3]; u32 pll3_pfd; - u32 resv12[3]; + u32 reserved_0x0F4[3]; u32 pll2_pfd; - u32 resv13[3]; + u32 reserved_0x104[3]; u32 reg_1p1; - u32 resv14[3]; + u32 reserved_0x114[3]; u32 reg_3p0; - u32 resv15[3]; + u32 reserved_0x124[3]; u32 reg_2p5; - u32 resv16[7]; + u32 reserved_0x134[7]; u32 ana_misc0; - u32 resv17[3]; + u32 reserved_0x154[3]; u32 ana_misc1; - u32 resv18[63]; + u32 reserved_0x164[63]; u32 anadig_digprog; - u32 resv19[3]; + u32 reserved_0x264[3]; u32 pll1_ctrl; - u32 resv20[3]; + u32 reserved_0x274[3]; u32 pll1_ss; - u32 resv21[3]; + u32 reserved_0x284[3]; u32 pll1_num; - u32 resv22[3]; + u32 reserved_0x294[3]; u32 pll1_denom; - u32 resv23[3]; + u32 reserved_0x2A4[3]; u32 pll1_pdf; - u32 resv24[3]; + u32 reserved_0x2B4[3]; u32 pll_lock; }; #endif @@ -148,25 +150,48 @@ struct anadig_reg { #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) +#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22 +#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) +#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22) #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) +#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12 +#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) +#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) #define CCM_CSCDR1_RMII_CLK_EN (1 << 24) +#define CCM_CSCDR2_NFC_EN (1 << 9) +#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) +#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) +#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 +#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) +#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) + #define CCM_CSCDR2_ESDHC1_EN (1 << 29) #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) +#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 +#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) +#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) +#define CCM_CSCDR3_QSPI0_EN (1 << 4) +#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) +#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) +#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) + #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) #define CCM_REG_CTRL_MASK 0xffffffff +#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) +#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) @@ -183,7 +208,12 @@ struct anadig_reg { #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) +#define CCM_CCGR10_NFC_CTRL_MASK 0x3 +#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL5_CTRL_DIV_SELECT 1 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL2_CTRL_DIV_SELECT 1 diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index b8c877f939..6b10bdf961 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -85,6 +85,10 @@ #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) +#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) +#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000) + +#define QSPI0_AMBA_BASE 0x20000000 /* MUX mode and PAD ctrl are in one register */ #define CONFIG_IOMUX_SHARE_CONF_REG @@ -99,9 +103,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x00002613 #define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x00210000 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x00002000 +#define DDRMC_PHY_OFF 0x00000000 +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE (1 << 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) @@ -134,7 +140,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) #define DDRMC_CR25_TREF_EN (1 << 16) #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) @@ -147,7 +153,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 << 16) #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) @@ -159,7 +165,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) @@ -178,9 +184,10 @@ #define DDRMC_CR77_CS_MAP (1 << 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) -#define DDRMC_CR82_INT_MASK 0x1fffffff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) +#define DDRMC_CR82_INT_MASK 0x10000000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) @@ -188,9 +195,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR97_WRLVL_EN (1 << 24) +#define DDRMC_CR98_WRLVL_DL_0 (0) +#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) @@ -204,19 +219,50 @@ #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) +#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8) #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) +#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) +#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) +#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) +#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) +#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) +#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) +#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) +#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) #define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) +#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) +#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) +#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) +#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf) + +/* System Reset Controller (SRC) */ +#define SRC_SRSR_SW_RST (0x1 << 18) +#define SRC_SRSR_RESETB (0x1 << 7) +#define SRC_SRSR_JTAG_RST (0x1 << 5) +#define SRC_SRSR_WDOG_M4 (0x1 << 4) +#define SRC_SRSR_WDOG_A5 (0x1 << 3) +#define SRC_SRSR_POR_RST (0x1 << 0) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 4a39eb0d60..9226e69fec 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,13 +17,28 @@ #define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_OBE_IBE_ENABLE) #define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm +#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \ + PAD_CTL_INPUT_DIFFERENTIAL) #define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE) +#define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ + PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_NFC_CN_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ + PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE) +#define VF610_NFC_RB_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE) + +#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -33,6 +48,15 @@ enum { VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), @@ -41,6 +65,46 @@ enum { VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), + VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD19__NF_IO3 = IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD17__NF_IO1 = IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD16__NF_IO0 = IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), + + VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -56,6 +120,7 @@ enum { VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -63,26 +128,26 @@ enum { VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/include/asm/arch-zynq/clk.h new file mode 100644 index 0000000000..250c5bc07b --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/clk.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ZYNQ_CLK_H_ +#define _ZYNQ_CLK_H_ + +enum zynq_clk { + armpll_clk, ddrpll_clk, iopll_clk, + cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk, + ddr2x_clk, ddr3x_clk, dci_clk, + lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk, + fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk, + sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk, + usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk, + sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk, + can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk, + uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, + smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; + +void zynq_clk_early_init(void); +int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate); +unsigned long zynq_clk_get_rate(enum zynq_clk clk); +const char *zynq_clk_get_name(enum zynq_clk clk); +unsigned long get_uart_clk(int dev_id); + +#endif diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h new file mode 100644 index 0000000000..a26ae87293 --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ZYNQ_GPIO_H +#define _ZYNQ_GPIO_H + +#endif /* _ZYNQ_GPIO_H */ diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 25f0e3d9c7..e2e0b7321a 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#define ZYNQ_SERIAL_BASEADDR0 0xE0000000 +#define ZYNQ_SERIAL_BASEADDR1 0xE0001000 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 @@ -17,18 +19,63 @@ #define ZYNQ_SDHCI_BASEADDR1 0xE0101000 #define ZYNQ_I2C_BASEADDR0 0xE0004000 #define ZYNQ_I2C_BASEADDR1 0xE0005000 +#define ZYNQ_SPI_BASEADDR0 0xE0006000 +#define ZYNQ_SPI_BASEADDR1 0xE0007000 +#define ZYNQ_QSPI_BASEADDR 0xE000D000 +#define ZYNQ_SMC_BASEADDR 0xE000E000 +#define ZYNQ_NAND_BASEADDR 0xE1000000 +#define ZYNQ_DDRC_BASEADDR 0xF8006000 +#define ZYNQ_EFUSE_BASEADDR 0xF800D000 +#define ZYNQ_USB_BASEADDR0 0xE0002000 +#define ZYNQ_USB_BASEADDR1 0xE0003000 + +/* Bootmode setting values */ +#define ZYNQ_BM_MASK 0x7 +#define ZYNQ_BM_QSPI 0x1 +#define ZYNQ_BM_NOR 0x2 +#define ZYNQ_BM_NAND 0x4 +#define ZYNQ_BM_SD 0x5 +#define ZYNQ_BM_JTAG 0x0 /* Reflect slcr offsets */ struct slcr_regs { u32 scl; /* 0x0 */ u32 slcr_lock; /* 0x4 */ u32 slcr_unlock; /* 0x8 */ - u32 reserved0[75]; + u32 reserved0_1[61]; + u32 arm_pll_ctrl; /* 0x100 */ + u32 ddr_pll_ctrl; /* 0x104 */ + u32 io_pll_ctrl; /* 0x108 */ + u32 reserved0_2[5]; + u32 arm_clk_ctrl; /* 0x120 */ + u32 ddr_clk_ctrl; /* 0x124 */ + u32 dci_clk_ctrl; /* 0x128 */ + u32 aper_clk_ctrl; /* 0x12c */ + u32 reserved0_3[2]; u32 gem0_rclk_ctrl; /* 0x138 */ u32 gem1_rclk_ctrl; /* 0x13c */ u32 gem0_clk_ctrl; /* 0x140 */ u32 gem1_clk_ctrl; /* 0x144 */ - u32 reserved1[46]; + u32 smc_clk_ctrl; /* 0x148 */ + u32 lqspi_clk_ctrl; /* 0x14c */ + u32 sdio_clk_ctrl; /* 0x150 */ + u32 uart_clk_ctrl; /* 0x154 */ + u32 spi_clk_ctrl; /* 0x158 */ + u32 can_clk_ctrl; /* 0x15c */ + u32 can_mioclk_ctrl; /* 0x160 */ + u32 dbg_clk_ctrl; /* 0x164 */ + u32 pcap_clk_ctrl; /* 0x168 */ + u32 reserved0_4[1]; + u32 fpga0_clk_ctrl; /* 0x170 */ + u32 reserved0_5[3]; + u32 fpga1_clk_ctrl; /* 0x180 */ + u32 reserved0_6[3]; + u32 fpga2_clk_ctrl; /* 0x190 */ + u32 reserved0_7[3]; + u32 fpga3_clk_ctrl; /* 0x1a0 */ + u32 reserved0_8[8]; + u32 clk_621_true; /* 0x1c4 */ + u32 reserved1[14]; u32 pss_rst_ctrl; /* 0x200 */ u32 reserved2[15]; u32 fpga_rst_ctrl; /* 0x240 */ @@ -84,4 +131,19 @@ struct scu_regs { #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR) +struct ddrc_regs { + u32 ddrc_ctrl; /* 0x0 */ + u32 reserved[60]; + u32 ecc_scrub; /* 0xF4 */ +}; +#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) + +struct efuse_reg { + u32 reserved1[4]; + u32 status; + u32 reserved2[3]; +}; + +#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 19a4eec6a9..9d50e2478f 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -10,12 +10,19 @@ extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); -extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); +extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); +extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); +extern int zynq_slcr_get_mio_pin_status(const char *periph); +extern void zynq_ddrc_init(void); +extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ -extern int zynq_sdhci_init(u32 regbase); +extern int zynq_sdhci_init(phys_addr_t regbase); +extern int zynq_sdhci_of_init(const void *blob); + +extern void ps7_init(void); #endif /* _SYS_PROTO_H_ */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 392d6a2db5..a13da23cf1 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -7,7 +7,6 @@ */ #ifndef ARMV7_H #define ARMV7_H -#include /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P1 0x410FC091 @@ -19,6 +18,22 @@ #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 #define MIDR_CORTEX_A15_R2P2 0x412FC0F2 +/* Cortex-A7 revisions */ +#define MIDR_CORTEX_A7_R0P0 0x410FC070 + +#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0 + +/* ID_PFR1 feature fields */ +#define CPUID_ARM_SEC_SHIFT 4 +#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT) +#define CPUID_ARM_VIRT_SHIFT 12 +#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT) +#define CPUID_ARM_GENTIMER_SHIFT 16 +#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT) + +/* valid bits in CBAR register / PERIPHBASE value */ +#define CBAR_MASK 0xFFFF8000 + /* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0 #define CCSIDR_LINE_SIZE_MASK 0x7 @@ -41,6 +56,9 @@ #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 +#ifndef __ASSEMBLY__ +#include + /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 @@ -58,4 +76,23 @@ void v7_outer_cache_inval_all(void); void v7_outer_cache_flush_range(u32 start, u32 end); void v7_outer_cache_inval_range(u32 start, u32 end); +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) + +int armv7_init_nonsec(void); +int armv7_update_dt(void *fdt); +bool armv7_boot_nonsec(void); + +/* defined in assembly file */ +unsigned int _nonsec_init(void); +void _do_nonsec_entry(void *target_pc, unsigned long r0, + unsigned long r1, unsigned long r2); +void _smp_pen(void); + +extern char __secure_start[]; +extern char __secure_end[]; + +#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */ + +#endif /* ! __ASSEMBLY__ */ + #endif diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h new file mode 100644 index 0000000000..4b7b67b643 --- /dev/null +++ b/arch/arm/include/asm/armv8/mmu.h @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_MMU_H_ +#define _ASM_ARMV8_MMU_H_ + +#ifdef __ASSEMBLY__ +#define _AC(X, Y) X +#else +#define _AC(X, Y) (X##Y) +#endif + +#define UL(x) _AC(x, UL) + +/***************************************************************/ +/* + * The following definitions are related each other, shoud be + * calculated specifically. + */ +#define VA_BITS (42) /* 42 bits virtual address */ + +/* PAGE_SHIFT determines the page size */ +#undef PAGE_SIZE +#define PAGE_SHIFT 16 +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +/* + * section address mask and size definitions. + */ +#define SECTION_SHIFT 29 +#define SECTION_SIZE (UL(1) << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) +/***************************************************************/ + +/* + * Memory types + */ +#define MT_DEVICE_NGNRNE 0 +#define MT_DEVICE_NGNRE 1 +#define MT_DEVICE_GRE 2 +#define MT_NORMAL_NC 3 +#define MT_NORMAL 4 + +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ + (0x04 << (MT_DEVICE_NGNRE*8)) | \ + (0x0c << (MT_DEVICE_GRE*8)) | \ + (0x44 << (MT_NORMAL_NC*8)) | \ + (UL(0xff) << (MT_NORMAL*8))) + +/* + * Hardware page table definitions. + * + * Level 2 descriptor (PMD). + */ +#define PMD_TYPE_MASK (3 << 0) +#define PMD_TYPE_FAULT (0 << 0) +#define PMD_TYPE_TABLE (3 << 0) +#define PMD_TYPE_SECT (1 << 0) + +/* + * Section + */ +#define PMD_SECT_S (3 << 8) +#define PMD_SECT_AF (1 << 10) +#define PMD_SECT_NG (1 << 11) +#define PMD_SECT_PXN (UL(1) << 53) +#define PMD_SECT_UXN (UL(1) << 54) + +/* + * AttrIndx[2:0] + */ +#define PMD_ATTRINDX(t) ((t) << 2) +#define PMD_ATTRINDX_MASK (7 << 2) + +/* + * TCR flags. + */ +#define TCR_T0SZ(x) ((64 - (x)) << 0) +#define TCR_IRGN_NC (0 << 8) +#define TCR_IRGN_WBWA (1 << 8) +#define TCR_IRGN_WT (2 << 8) +#define TCR_IRGN_WBNWA (3 << 8) +#define TCR_IRGN_MASK (3 << 8) +#define TCR_ORGN_NC (0 << 10) +#define TCR_ORGN_WBWA (1 << 10) +#define TCR_ORGN_WT (2 << 10) +#define TCR_ORGN_WBNWA (3 << 10) +#define TCR_ORGN_MASK (3 << 10) +#define TCR_SHARED_NON (0 << 12) +#define TCR_SHARED_OUTER (1 << 12) +#define TCR_SHARED_INNER (2 << 12) +#define TCR_TG0_4K (0 << 14) +#define TCR_TG0_64K (1 << 14) +#define TCR_TG0_16K (2 << 14) +#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ +#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ +#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ + +/* PTWs cacheable, inner/outer WBWA and non-shareable */ +#define TCR_FLAGS (TCR_TG0_64K | \ + TCR_SHARED_NON | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(VA_BITS)) + +#ifndef __ASSEMBLY__ +void set_pgtable_section(u64 *page_table, u64 index, + u64 section, u64 memory_type); +static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) +{ + asm volatile("dsb sy"); + if (el == 1) { + asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); + } else if (el == 2) { + asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); + } else if (el == 3) { + asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); + } else { + hang(); + } + asm volatile("isb"); +} +#endif +#endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 5e4789b145..11b80fb190 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -14,12 +14,14 @@ * assembler source. */ +#include + /* * Endian independent macros for shifting bytes within registers. */ #ifndef __ARMEB__ -#define pull lsr -#define push lsl +#define lspull lsr +#define lspush lsl #define get_byte_0 lsl #0 #define get_byte_1 lsr #8 #define get_byte_2 lsr #16 @@ -29,8 +31,8 @@ #define put_byte_2 lsl #16 #define put_byte_3 lsl #24 #else -#define pull lsl -#define push lsr +#define lspull lsl +#define lspush lsr #define get_byte_0 lsr #24 #define get_byte_1 lsr #16 #define get_byte_2 lsr #8 @@ -54,7 +56,28 @@ #define PLD(code...) #endif + .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo + .macro ret\c, reg +#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) + mov\c pc, \reg +#else + .ifeqs "\reg", "lr" + bx\c \reg + .else + mov\c pc, \reg + .endif +#endif + .endm + .endr + /* - * Cache alligned + * Cache aligned, used for optimized memcpy/memset + * In the kernel this is only enabled for Feroceon CPU's... + * We disable it especially for Thumb builds since those instructions + * are not made in a Thumb ready way... */ +#ifdef CONFIG_SYS_THUMB_BUILD +#define CALGN(code...) +#else #define CALGN(code...) code +#endif diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index ba9e4b72d8..34c07fe500 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -16,8 +16,6 @@ #ifndef __ASM_ARM_ATOMIC_H #define __ASM_ARM_ATOMIC_H -#include - #ifdef CONFIG_SMP #error SMP not supported #endif @@ -27,7 +25,7 @@ typedef struct { volatile int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } #ifdef __KERNEL__ -#include +#include #define atomic_read(v) ((v)->counter) #define atomic_set(v,i) (((v)->counter) = (i)) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 879e20e024..597dafbf9d 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -17,7 +17,7 @@ #ifdef __KERNEL__ -#include +#include #define smp_mb__before_clear_bit() do { } while (0) #define smp_mb__after_clear_bit() do { } while (0) diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h index c3489f1e1f..20cce7657e 100644 --- a/arch/arm/include/asm/byteorder.h +++ b/arch/arm/include/asm/byteorder.h @@ -23,7 +23,7 @@ # define __SWAB_64_THRU_32__ #endif -#ifdef __ARMEB__ +#if defined(__ARMEB__) || defined(__AARCH64EB__) #include #else #include diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 6d60a4a6d9..a836e9f2ab 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -11,6 +11,8 @@ #include +#ifndef CONFIG_ARM64 + /* * Invalidate L2 Cache using co-proc instruction */ @@ -27,7 +29,13 @@ void l2_cache_enable(void); void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); +void arm_init_before_mmu(void); +void arm_init_domains(void); +void cpu_cache_initialization(void); void dram_bank_mmu_setup(int bank); + +#endif + /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 99b703e1e4..dfa634d62e 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -7,6 +7,24 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#ifdef __aarch64__ +#define CONFIG_SYS_GENERIC_GLOBAL_DATA +#endif + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH + +#ifdef CONFIG_ARM64 +#define CONFIG_PHYS_64BIT +#define CONFIG_STATIC_RELA +#endif + +#ifdef CONFIG_FSL_LSCH3 +#include +#endif + +#ifdef CONFIG_SOC_LS102XA +#include +#endif + #endif diff --git a/arch/arm/include/asm/davinci_rtc.h b/arch/arm/include/asm/davinci_rtc.h new file mode 100644 index 0000000000..575b590888 --- /dev/null +++ b/arch/arm/include/asm/davinci_rtc.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ------------------------------------------------------------------------- + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_DAVINCI_RTC_H +#define __ASM_DAVINCI_RTC_H + +struct davinci_rtc { + unsigned int second; + unsigned int minutes; + unsigned int hours; + unsigned int day; + unsigned int month; /* 0x10 */ + unsigned int year; + unsigned int dotw; + unsigned int resv1; + unsigned int alarmsecond; /* 0x20 */ + unsigned int alarmminute; + unsigned int alarmhour; + unsigned int alarmday; + unsigned int alarmmonth; /* 0x30 */ + unsigned int alarmyear; + unsigned int resv2[2]; + unsigned int ctrl; /* 0x40 */ + unsigned int status; + unsigned int irq; + unsigned int complsb; + unsigned int compmsb; /* 0x50 */ + unsigned int osc; + unsigned int resv3[2]; + unsigned int scratch0; /* 0x60 */ + unsigned int scratch1; + unsigned int scratch2; + unsigned int kick0r; + unsigned int kick1r; /* 0x70 */ +}; + +#define RTC_STATE_BUSY 0x01 +#define RTC_STATE_RUN 0x02 + +#define RTC_KICK0R_WE 0x83e70b13 +#define RTC_KICK1R_WE 0x95a4f1e0 +#endif diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 009863beec..55a4e266a0 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -16,7 +16,7 @@ enum dma_data_direction { static void *dma_alloc_coherent(size_t len, unsigned long *handle) { - *handle = (unsigned long)malloc(len); + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); return (void *)*handle; } diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index 77e81701b8..c7bca05682 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -42,6 +42,7 @@ enum usbhs_omap_port_mode { /* Values of UHH_REVISION - Note: these are not given in the TRM */ #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ +#define OMAP_USBHS_REV2_1 0x50700101 /* OMAP5 */ /* UHH Register Set */ #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) @@ -60,6 +61,7 @@ enum usbhs_omap_port_mode { #define OMAP_P2_MODE_CLEAR (3 << 18) #define OMAP_P2_MODE_TLL (1 << 18) #define OMAP_P2_MODE_HSIC (3 << 18) +#define OMAP_P3_MODE_CLEAR (3 << 20) #define OMAP_P3_MODE_HSIC (3 << 20) /* EHCI Register Set */ @@ -143,8 +145,8 @@ struct omap_ehci { struct ehci_hccr; struct ehci_hcor; -int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, - struct ehci_hccr **hccr, struct ehci_hcor **hcor); +int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, + struct ehci_hccr **hccr, struct ehci_hcor **hcor); int omap_ehci_hcd_stop(void); #endif /* _OMAP_COMMON_EHCI_H_ */ diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 56cbd07431..72b6733c9a 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -14,11 +14,15 @@ #define _EMIF_H_ #include #include +#include /* Base address */ #define EMIF1_BASE 0x4c000000 #define EMIF2_BASE 0x4d000000 +#define EMIF_4D 0x4 +#define EMIF_4D5 0x5 + /* Registers shifts, masks and values */ /* EMIF_MOD_ID_REV */ @@ -581,7 +585,6 @@ (0xFF << EMIF_SYS_ADDR_SHIFT)) #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 -#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14 /* Reg mapping structure */ struct emif_reg_struct { @@ -639,9 +642,16 @@ struct emif_reg_struct { u32 emif_ddr_phy_ctrl_1; /* 0x0e4 */ u32 emif_ddr_phy_ctrl_1_shdw; /* 0x0e8 */ u32 emif_ddr_phy_ctrl_2; /* 0x0ec */ - u32 padding7[12]; /* 0x0f0 */ + u32 padding7[4]; /* 0x0f0 */ + u32 emif_prio_class_serv_map; /* 0x100 */ + u32 emif_connect_id_serv_1_map; /* 0x104 */ + u32 emif_connect_id_serv_2_map; /* 0x108 */ + u32 padding8[5]; /* 0x10c */ u32 emif_rd_wr_exec_thresh; /* 0x120 */ - u32 padding8[55]; /* 0x124 */ + u32 emif_cos_config; /* 0x124 */ + u32 padding9[6]; /* 0x128 */ + u32 emif_ddr_phy_status[28]; /* 0x140 */ + u32 padding10[20]; /* 0x1b0 */ u32 emif_ddr_ext_phy_ctrl_1; /* 0x200 */ u32 emif_ddr_ext_phy_ctrl_1_shdw; /* 0x204 */ u32 emif_ddr_ext_phy_ctrl_2; /* 0x248 */ @@ -690,6 +700,36 @@ struct emif_reg_struct { u32 emif_ddr_ext_phy_ctrl_23_shdw; /* 0x2a4 */ u32 emif_ddr_ext_phy_ctrl_24; /* 0x2a8 */ u32 emif_ddr_ext_phy_ctrl_24_shdw; /* 0x2ac */ + u32 emif_ddr_ext_phy_ctrl_25; /* 0x2b0 */ + u32 emif_ddr_ext_phy_ctrl_25_shdw; /* 0x2b4 */ + u32 emif_ddr_ext_phy_ctrl_26; /* 0x2b8 */ + u32 emif_ddr_ext_phy_ctrl_26_shdw; /* 0x2bc */ + u32 emif_ddr_ext_phy_ctrl_27; /* 0x2c0 */ + u32 emif_ddr_ext_phy_ctrl_27_shdw; /* 0x2c4 */ + u32 emif_ddr_ext_phy_ctrl_28; /* 0x2c8 */ + u32 emif_ddr_ext_phy_ctrl_28_shdw; /* 0x2cc */ + u32 emif_ddr_ext_phy_ctrl_29; /* 0x2d0 */ + u32 emif_ddr_ext_phy_ctrl_29_shdw; /* 0x2d4 */ + u32 emif_ddr_ext_phy_ctrl_30; /* 0x2d8 */ + u32 emif_ddr_ext_phy_ctrl_30_shdw; /* 0x2dc */ + u32 emif_ddr_ext_phy_ctrl_31; /* 0x2e0 */ + u32 emif_ddr_ext_phy_ctrl_31_shdw; /* 0x2e4 */ + u32 emif_ddr_ext_phy_ctrl_32; /* 0x2e8 */ + u32 emif_ddr_ext_phy_ctrl_32_shdw; /* 0x2ec */ + u32 emif_ddr_ext_phy_ctrl_33; /* 0x2f0 */ + u32 emif_ddr_ext_phy_ctrl_33_shdw; /* 0x2f4 */ + u32 emif_ddr_ext_phy_ctrl_34; /* 0x2f8 */ + u32 emif_ddr_ext_phy_ctrl_34_shdw; /* 0x2fc */ + u32 emif_ddr_ext_phy_ctrl_35; /* 0x300 */ + u32 emif_ddr_ext_phy_ctrl_35_shdw; /* 0x304 */ + union { + u32 emif_ddr_ext_phy_ctrl_36; /* 0x308 */ + u32 emif_ddr_fifo_misaligned_clear_1; + }; + union { + u32 emif_ddr_ext_phy_ctrl_36_shdw; /* 0x30c */ + u32 emif_ddr_fifo_misaligned_clear_2; + }; }; struct dmm_lisa_map_regs { @@ -865,7 +905,6 @@ struct dmm_lisa_map_regs { ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ - ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\ & EMIF_REG_LP_MODE_MASK) |\ ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ @@ -876,8 +915,6 @@ struct dmm_lisa_map_regs { & EMIF_REG_CS_TIM_SHDW_MASK) |\ ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\ & EMIF_REG_SR_TIM_SHDW_MASK) |\ - ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ - & EMIF_REG_PD_TIM_SHDW_MASK) |\ ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ & EMIF_REG_PD_TIM_SHDW_MASK)) @@ -1129,6 +1166,10 @@ struct emif_regs { u32 emif_rd_wr_lvl_rmp_ctl; u32 emif_rd_wr_lvl_ctl; u32 emif_rd_wr_exec_thresh; + u32 emif_prio_class_serv_map; + u32 emif_connect_id_serv_1_map; + u32 emif_connect_id_serv_2_map; + u32 emif_cos_config; }; struct lpddr2_mr_regs { @@ -1139,6 +1180,33 @@ struct lpddr2_mr_regs { s8 mr16; }; +struct read_write_regs { + u32 read_reg; + u32 write_reg; +}; + +static inline u32 get_emif_rev(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) + >> EMIF_REG_MAJOR_REVISION_SHIFT; +} + +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +static inline u32 emif_sdram_type(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) hang(); }) @@ -1167,4 +1235,5 @@ extern u32 *const T_den; void config_data_eye_leveling_samples(u32 emif_base); u32 emif_sdram_type(void); +const struct read_write_regs *get_bug_regs(u32 *iterations); #endif diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h new file mode 100644 index 0000000000..bd3a80cdf7 --- /dev/null +++ b/arch/arm/include/asm/gic.h @@ -0,0 +1,110 @@ +#ifndef __GIC_H__ +#define __GIC_H__ + +/* Register offsets for the ARM generic interrupt controller (GIC) */ + +#define GIC_DIST_OFFSET 0x1000 +#define GIC_CPU_OFFSET_A9 0x0100 +#define GIC_CPU_OFFSET_A15 0x2000 + +/* Distributor Registers */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_STATUSR 0x0010 +#define GICD_SETSPI_NSR 0x0040 +#define GICD_CLRSPI_NSR 0x0048 +#define GICD_SETSPI_SR 0x0050 +#define GICD_CLRSPI_SR 0x0058 +#define GICD_SEIR 0x0068 +#define GICD_IGROUPRn 0x0080 +#define GICD_ISENABLERn 0x0100 +#define GICD_ICENABLERn 0x0180 +#define GICD_ISPENDRn 0x0200 +#define GICD_ICPENDRn 0x0280 +#define GICD_ISACTIVERn 0x0300 +#define GICD_ICACTIVERn 0x0380 +#define GICD_IPRIORITYRn 0x0400 +#define GICD_ITARGETSRn 0x0800 +#define GICD_ICFGR 0x0c00 +#define GICD_IGROUPMODRn 0x0d00 +#define GICD_NSACRn 0x0e00 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGIRn 0x0f10 +#define GICD_SPENDSGIRn 0x0f20 +#define GICD_IROUTERn 0x6000 + +/* Cpu Interface Memory Mapped Registers */ +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000C +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APRn 0x00d0 +#define GICC_NSAPRn 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +/* ReDistributor Registers for Control and Physical LPIs */ +#define GICR_CTLR 0x0000 +#define GICR_IIDR 0x0004 +#define GICR_TYPER 0x0008 +#define GICR_STATUSR 0x0010 +#define GICR_WAKER 0x0014 +#define GICR_SETLPIR 0x0040 +#define GICR_CLRLPIR 0x0048 +#define GICR_SEIR 0x0068 +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 +#define GICR_INVLPIR 0x00a0 +#define GICR_INVALLR 0x00b0 +#define GICR_SYNCR 0x00c0 +#define GICR_MOVLPIR 0x0100 +#define GICR_MOVALLR 0x0110 + +/* ReDistributor Registers for SGIs and PPIs */ +#define GICR_IGROUPRn 0x0080 +#define GICR_ISENABLERn 0x0100 +#define GICR_ICENABLERn 0x0180 +#define GICR_ISPENDRn 0x0200 +#define GICR_ICPENDRn 0x0280 +#define GICR_ISACTIVERn 0x0300 +#define GICR_ICACTIVERn 0x0380 +#define GICR_IPRIORITYRn 0x0400 +#define GICR_ICFGR0 0x0c00 +#define GICR_ICFGR1 0x0c04 +#define GICR_IGROUPMODRn 0x0d00 +#define GICR_NSACRn 0x0e00 + +/* Cpu Interface System Registers */ +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 +#define ICC_DIR_EL1 S3_0_C12_C11_1 +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 +#define ICC_SEIEN_EL1 S3_0_C12_C13_0 +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + +#endif /* __GIC_H__ */ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 0649a4636d..5fb6506f4e 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -17,9 +17,18 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif + +#if defined(CONFIG_U_QE) + u32 qe_clk; + u32 brg_clk; + uint mp_alloc_base; + uint mp_alloc_top; +#endif /* CONFIG_U_QE */ + #ifdef CONFIG_VIDEO_IPUV3 unsigned int ipu_hw_rev; #endif + #ifdef CONFIG_AT91FAMILY /* "static data" needed by at91's clock.c */ unsigned long cpu_clk_rate_hz; @@ -35,9 +44,6 @@ struct arch_global_data { unsigned long tbl; unsigned long lastinc; unsigned long long timer_reset_value; -#ifdef CONFIG_IXP425 - unsigned long timestamp; -#endif #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; unsigned long tlb_size; @@ -50,6 +56,35 @@ struct arch_global_data { #include -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") +#ifdef __clang__ + +#define DECLARE_GLOBAL_DATA_PTR +#define gd get_gd() + +static inline gd_t *get_gd(void) +{ + gd_t *gd_ptr; + +#ifdef CONFIG_ARM64 + /* + * Make will already error that reserving x18 is not supported at the + * time of writing, clang: error: unknown argument: '-ffixed-x18' + */ + __asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr)); +#else + __asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr)); +#endif + + return gd_ptr; +} + +#else + +#ifdef CONFIG_ARM64 +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") +#else +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") +#endif +#endif #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h index 14a0c12ddc..a0eae0dffe 100644 --- a/arch/arm/include/asm/imx-common/dma.h +++ b/arch/arm/include/asm/imx-common/dma.h @@ -27,7 +27,7 @@ /* * MXS DMA channels */ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) enum { MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0, MXS_DMA_CHANNEL_AHB_APBH_SSP0, @@ -39,7 +39,7 @@ enum { MXS_DMA_CHANNEL_AHB_APBH_GPMI3, MXS_MAX_DMA_CHANNELS, }; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) enum { MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, MXS_DMA_CHANNEL_AHB_APBH_SSP1, @@ -59,7 +59,7 @@ enum { MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, MXS_MAX_DMA_CHANNELS, }; -#elif defined(CONFIG_MX6) +#elif defined(CONFIG_SOC_MX6) enum { MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, MXS_DMA_CHANNEL_AHB_APBH_GPMI1, @@ -164,4 +164,6 @@ void mxs_dma_init(void); int mxs_dma_init_channel(int chan); int mxs_dma_release(int chan); +void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc); + #endif /* __DMA_H__ */ diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index af4f835405..9af5af71c6 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -63,6 +63,8 @@ typedef u64 iomux_v3_cfg_t; #define MUX_SEL_INPUT_SHIFT 59 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ + MUX_MODE_SHIFT) #define __MUX_PAD_CTRL(x) ((x) | __PAD_CTRL_VALID) #define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)__MUX_PAD_CTRL(x) << \ MUX_PAD_CTRL_SHIFT)) @@ -90,7 +92,7 @@ typedef u64 iomux_v3_cfg_t; #define __PAD_CTRL_VALID (1 << 17) #define PAD_CTRL_VALID ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT) -#ifdef CONFIG_MX6 +#ifdef CONFIG_SOC_MX6 #define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 16) @@ -116,23 +118,36 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm __MUX_PAD_CTRL(6 << 3) #define PAD_CTL_DSE_34ohm __MUX_PAD_CTRL(7 << 3) -#elif defined(CONFIG_VF610) +#if defined CONFIG_SOC_MX6SL +#define PAD_CTL_LVE __MUX_PAD_CTRL(1 << 1) +#define PAD_CTL_LVE_BIT __MUX_PAD_CTRL(1 << 22) +#endif + +#elif defined(CONFIG_SOC_VF610) #define PAD_MUX_MODE_SHIFT 20 +#define PAD_CTL_INPUT_DIFFERENTIAL __MUX_PAD_CTRL(1 << 16) + #define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(1 << 12) #define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 12) +#define PAD_CTL_SRE __MUX_PAD_CTRL(1 << 11) + +#define PAD_CTL_DSE_150ohm __MUX_PAD_CTRL(1 << 6) #define PAD_CTL_DSE_50ohm __MUX_PAD_CTRL(3 << 6) #define PAD_CTL_DSE_25ohm __MUX_PAD_CTRL(6 << 6) #define PAD_CTL_DSE_20ohm __MUX_PAD_CTRL(7 << 6) #define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE) #define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE) #define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 3) #define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 2 | PAD_CTL_PKE) #define PAD_CTL_OBE_IBE_ENABLE __MUX_PAD_CTRL(3 << 0) +#define PAD_CTL_OBE_ENABLE __MUX_PAD_CTRL(1 << 1) +#define PAD_CTL_IBE_ENABLE __MUX_PAD_CTRL(1 << 0) #else @@ -171,8 +186,38 @@ typedef u64 iomux_v3_cfg_t; #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) -void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); +void imx_iomux_v3_setup_pad(const iomux_v3_cfg_t const pad); void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count); +/* +* Set bits for general purpose registers +*/ +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value); + +/* macros for declaring and using pinmux array */ +#if defined(CONFIG_SOC_MX6QDL) +#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) +#define SETUP_IOMUX_PAD(def) \ +if (is_cpu_type(MXC_CPU_MX6Q)) { \ + imx_iomux_v3_setup_pad(MX6Q_##def); \ +} else { \ + imx_iomux_v3_setup_pad(MX6DL_##def); \ +} +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) +#elif defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D) +#define IOMUX_PADS(x) MX6Q_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6Q_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#else +#define IOMUX_PADS(x) MX6DL_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6DL_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#endif #endif /* __ASM_ARCH_IOMUX_V3_H__*/ diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h index 47a9edc81b..295ef51299 100644 --- a/arch/arm/include/asm/imx-common/mxc_i2c.h +++ b/arch/arm/include/asm/imx-common/mxc_i2c.h @@ -19,8 +19,41 @@ struct i2c_pads_info { struct i2c_pin_ctrl sda; }; -void setup_i2c(unsigned i2c_index, int speed, int slave_addr, - struct i2c_pads_info *p); +#if defined(CONFIG_SOC_MX6QDL) +#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \ + struct i2c_pads_info mx6q_##name = { \ + .scl = { \ + .i2c_mode = MX6Q_##scl_i2c, \ + .gpio_mode = MX6Q_##scl_gpio, \ + .gp = scl_gp, \ + }, \ + .sda = { \ + .i2c_mode = MX6Q_##sda_i2c, \ + .gpio_mode = MX6Q_##sda_gpio, \ + .gp = sda_gp, \ + } \ + }; \ + struct i2c_pads_info mx6s_##name = { \ + .scl = { \ + .i2c_mode = MX6DL_##scl_i2c, \ + .gpio_mode = MX6DL_##scl_gpio, \ + .gp = scl_gp, \ + }, \ + .sda = { \ + .i2c_mode = MX6DL_##sda_i2c, \ + .gpio_mode = MX6DL_##sda_gpio, \ + .gp = sda_gp, \ + } \ + }; + + +#define I2C_PADS_INFO(name) \ + (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \ + &mx6q_##name : &mx6s_##name +#endif + +int setup_i2c(unsigned i2c_index, int speed, int slave_addr, + struct i2c_pads_info *p); void bus_i2c_init(void *base, int speed, int slave_addr, int (*idle_bus_fn)(void *p), void *p); int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h index bcbde05df3..1b14248b6f 100644 --- a/arch/arm/include/asm/imx-common/regs-apbh.h +++ b/arch/arm/include/asm/imx-common/regs-apbh.h @@ -17,7 +17,7 @@ #ifndef __ASSEMBLY__ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) struct mxs_apbh_regs { mxs_reg_32(hw_apbh_ctrl0); mxs_reg_32(hw_apbh_ctrl1); @@ -96,7 +96,7 @@ struct mxs_apbh_regs { mxs_reg_32(hw_apbh_version); }; -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) +#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6)) struct mxs_apbh_regs { mxs_reg_32(hw_apbh_ctrl0); /* 0x000 */ mxs_reg_32(hw_apbh_ctrl1); /* 0x010 */ @@ -243,7 +243,7 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE (1 << 30) #define APBH_CTRL0_AHB_BURST8_EN (1 << 29) #define APBH_CTRL0_APB_BURST_EN (1 << 28) -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define APBH_CTRL0_RSVD0_MASK (0xf << 24) #define APBH_CTRL0_RSVD0_OFFSET 24 #define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16) @@ -256,7 +256,7 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define APBH_CTRL0_RSVD0_MASK (0xfff << 16) #define APBH_CTRL0_RSVD0_OFFSET 16 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff @@ -275,7 +275,7 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 -#elif defined(CONFIG_MX6) +#elif defined(CONFIG_SOC_MX6) #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 @@ -356,7 +356,7 @@ struct mxs_apbh_regs { #define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) #define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) @@ -391,11 +391,11 @@ struct mxs_apbh_regs { #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 #endif -#if defined(CONFIG_MX6) +#if defined(CONFIG_SOC_MX6) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 #endif -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define APBH_DEVSEL_CH7_MASK (0xf << 28) #define APBH_DEVSEL_CH7_OFFSET 28 #define APBH_DEVSEL_CH6_MASK (0xf << 24) @@ -412,7 +412,7 @@ struct mxs_apbh_regs { #define APBH_DEVSEL_CH1_OFFSET 4 #define APBH_DEVSEL_CH0_MASK (0xf << 0) #define APBH_DEVSEL_CH0_OFFSET 0 -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define APBH_DEVSEL_CH15_MASK (0x3 << 30) #define APBH_DEVSEL_CH15_OFFSET 30 #define APBH_DEVSEL_CH14_MASK (0x3 << 28) @@ -447,7 +447,7 @@ struct mxs_apbh_regs { #define APBH_DEVSEL_CH0_OFFSET 0 #endif -#if defined(CONFIG_MX28) +#if defined(CONFIG_SOC_MX28) #define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) #define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 #define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) diff --git a/arch/arm/include/asm/imx-common/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h index 1ed5d94dd4..327b8d693f 100644 --- a/arch/arm/include/asm/imx-common/regs-bch.h +++ b/arch/arm/include/asm/imx-common/regs-bch.h @@ -35,6 +35,7 @@ struct bch_regs { mxs_reg_32(hw_bch_flash2layout1); mxs_reg_32(hw_bch_flash3layout0); mxs_reg_32(hw_bch_flash3layout1); + mxs_reg_32(hw_bch_debug0); mxs_reg_32(hw_bch_dbgkesread); mxs_reg_32(hw_bch_dbgcsferead); mxs_reg_32(hw_bch_dbgsyndegread); @@ -125,7 +126,7 @@ struct bch_regs { #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 -#if defined(CONFIG_MX6) +#if defined(CONFIG_SOC_MX6) #define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) #define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 #else @@ -155,7 +156,7 @@ struct bch_regs { #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 -#if defined(CONFIG_MX6) +#if defined(CONFIG_SOC_MX6) #define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) #define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 #else diff --git a/arch/arm/include/asm/imx-common/regs-gpmi.h b/arch/arm/include/asm/imx-common/regs-gpmi.h index 642864f3cf..29b20fb872 100644 --- a/arch/arm/include/asm/imx-common/regs-gpmi.h +++ b/arch/arm/include/asm/imx-common/regs-gpmi.h @@ -33,6 +33,8 @@ struct gpmi_regs { mxs_reg_32(hw_gpmi_stat); mxs_reg_32(hw_gpmi_debug); mxs_reg_32(hw_gpmi_version); + mxs_reg_32(hw_gpmi_debug2); + mxs_reg_32(hw_gpmi_debug3); }; #endif diff --git a/arch/arm/include/asm/imx-common/sata.h b/arch/arm/include/asm/imx-common/sata.h new file mode 100644 index 0000000000..6b864cbd11 --- /dev/null +++ b/arch/arm/include/asm/imx-common/sata.h @@ -0,0 +1,16 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_SATA_H_ +#define __IMX_SATA_H_ + +/* + * SATA setup for i.mx6 quad based platform + */ + +int setup_sata(void); + +#endif diff --git a/arch/arm/include/asm/imx-common/spi.h b/arch/arm/include/asm/imx-common/spi.h new file mode 100644 index 0000000000..1d4473a04a --- /dev/null +++ b/arch/arm/include/asm/imx-common/spi.h @@ -0,0 +1,17 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MXC_SPI_H_ +#define __MXC_SPI_H_ + +/* + * Board-level chip-select callback + * Should return GPIO # to be used for chip-select + */ + +int board_spi_cs_gpio(unsigned bus, unsigned cs); + +#endif diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h new file mode 100644 index 0000000000..1a907d44e4 --- /dev/null +++ b/arch/arm/include/asm/imx-common/video.h @@ -0,0 +1,29 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_VIDEO_H_ +#define __IMX_VIDEO_H_ + +#include +#include + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + +#ifdef CONFIG_IMX_HDMI +extern int detect_hdmi(struct display_info_t const *dev); +#endif + +#ifdef CONFIG_IMX_VIDEO_SKIP +extern struct display_info_t const displays[]; +extern size_t display_count; +#endif + +#endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 1fbc531a08..bfbe0a0988 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -70,47 +70,52 @@ static inline phys_addr_t virt_to_phys(void * vaddr) #define __arch_getb(a) (*(volatile unsigned char *)(a)) #define __arch_getw(a) (*(volatile unsigned short *)(a)) #define __arch_getl(a) (*(volatile unsigned int *)(a)) +#define __arch_getq(a) (*(volatile unsigned long long *)(a)) #define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v)) -extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) +static inline void __raw_writesb(unsigned long addr, const void *data, + int bytelen) { uint8_t *buf = (uint8_t *)data; while(bytelen--) __arch_putb(*buf++, addr); } -extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) +static inline void __raw_writesw(unsigned long addr, const void *data, + int wordlen) { uint16_t *buf = (uint16_t *)data; while(wordlen--) __arch_putw(*buf++, addr); } -extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) +static inline void __raw_writesl(unsigned long addr, const void *data, + int longlen) { uint32_t *buf = (uint32_t *)data; while(longlen--) __arch_putl(*buf++, addr); } -extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) +static inline void __raw_readsb(unsigned long addr, void *data, int bytelen) { uint8_t *buf = (uint8_t *)data; while(bytelen--) *buf++ = __arch_getb(addr); } -extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) +static inline void __raw_readsw(unsigned long addr, void *data, int wordlen) { uint16_t *buf = (uint16_t *)data; while(wordlen--) *buf++ = __arch_getw(addr); } -extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) +static inline void __raw_readsl(unsigned long addr, void *data, int longlen) { uint32_t *buf = (uint32_t *)data; while(longlen--) @@ -120,15 +125,18 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define __raw_writeb(v,a) __arch_putb(v,a) #define __raw_writew(v,a) __arch_putw(v,a) #define __raw_writel(v,a) __arch_putl(v,a) +#define __raw_writeq(v,a) __arch_putq(v,a) #define __raw_readb(a) __arch_getb(a) #define __raw_readw(a) __arch_getw(a) #define __raw_readl(a) __arch_getl(a) +#define __raw_readq(a) __arch_getq(a) /* * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ +#define mb() asm volatile("dsb sy" : : : "memory") #define dmb() __asm__ __volatile__ ("" : : : "memory") #define __iormb() dmb() #define __iowmb() dmb() @@ -136,10 +144,12 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) #define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) +#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; }) #define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) +#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) /* * The compiler seems to be incapable of optimising constants @@ -165,9 +175,11 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) #define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) +#define out_le64(a,v) out_arch(q,le64,a,v) #define out_le32(a,v) out_arch(l,le32,a,v) #define out_le16(a,v) out_arch(w,le16,a,v) +#define in_le64(a) in_arch(q,le64,a) #define in_le32(a) in_arch(l,le32,a) #define in_le16(a) in_arch(w,le16,a) @@ -364,7 +376,12 @@ out: return retval; } -#elif !defined(readb) +#else +#define memset_io(a, b, c) memset((void *)(a), (b), (c)) +#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) +#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) + +#if !defined(readb) #define readb(addr) (__readwrite_bug("readb"),0) #define readw(addr) (__readwrite_bug("readw"),0) @@ -377,6 +394,7 @@ out: #define check_signature(io,sig,len) (0) +#endif #endif /* __mem_pci */ /* @@ -434,4 +452,7 @@ out: #endif /* __mem_isa */ #endif /* __KERNEL__ */ + +#include + #endif /* __ASM_ARM_IO_H */ diff --git a/arch/arm/include/asm/iproc-common/armpll.h b/arch/arm/include/asm/iproc-common/armpll.h new file mode 100644 index 0000000000..1bee350b7b --- /dev/null +++ b/arch/arm/include/asm/iproc-common/armpll.h @@ -0,0 +1,14 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARMPLL_H +#define __ARMPLL_H + +#include + +uint32_t armpll_config(uint32_t clkmhz); + +#endif /*__ARMPLL_H */ diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h new file mode 100644 index 0000000000..c24de1f4a7 --- /dev/null +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IPROC_COMMON_CONFIGS_H +#define __IPROC_COMMON_CONFIGS_H + +#include + +/* Architecture, CPU, chip, etc */ +#define CONFIG_IPROC +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH + +/* Memory Info */ +#define CONFIG_SYS_TEXT_BASE 0x61000000 +#define CONFIG_SYS_SDRAM_BASE 0x61000000 + +#endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/arch/arm/include/asm/iproc-common/sysmap.h b/arch/arm/include/asm/iproc-common/sysmap.h new file mode 100644 index 0000000000..5766dc9e53 --- /dev/null +++ b/arch/arm/include/asm/iproc-common/sysmap.h @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SYSMAP_H +#define __SYSMAP_H + +#define IHOST_PROC_CLK_PLLARMA 0X19000C00 +#define IHOST_PROC_CLK_PLLARMB 0X19000C04 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24 + +#define IHOST_PROC_CLK_WR_ACCESS 0X19000000 +#define IHOST_PROC_CLK_POLICY_FREQ 0X19000008 +#define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8 +#define IHOST_PROC_CLK_POLICY_CTL 0X1900000C +#define IHOST_PROC_CLK_POLICY_CTL__GO 0 +#define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1 +#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0 +#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH 20 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK 28 +#define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R 0 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1 +#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0 +#define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200 +#define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204 +#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210 +#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300 +#define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400 +#define IPROC_CLKCT_HDELAY_SW_EN 0x00000303 + +#define IPROC_REG_WRITE_ACCESS 0x00a5a501 + +#define IPROC_PERIPH_BASE 0x19020000 +#define IPROC_PERIPH_INT_CTRL_REG_BASE (IPROC_PERIPH_BASE + 0x100) +#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200) +#define IPROC_PERIPH_PVT_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x600) +#define IPROC_PERIPH_INT_DISTR_REG_BASE (IPROC_PERIPH_BASE + 0x1000) + +#define PLL_AXI_CLK 0x1DCD6500 + +#endif /* __SYSMAP_H */ diff --git a/arch/arm/include/asm/iproc-common/timer.h b/arch/arm/include/asm/iproc-common/timer.h new file mode 100644 index 0000000000..2bc23221a4 --- /dev/null +++ b/arch/arm/include/asm/iproc-common/timer.h @@ -0,0 +1,37 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TIMER_H +#define __TIMER_H + +#include + +void timer_systick_init(uint32_t tick_ms); +void timer_global_init(void); + +/* ARM A9 Private Timer */ +#define TIMER_PVT_LOAD_OFFSET 0x00000000 +#define TIMER_PVT_COUNTER_OFFSET 0x00000004 +#define TIMER_PVT_CTRL_OFFSET 0x00000008 +#define TIMER_PVT_STATUS_OFFSET 0x0000000C +#define TIMER_PVT_TIM_CTRL_TIM_EN 0x00000001 +#define TIMER_PVT_TIM_CTRL_AUTO_RELD 0x00000002 +#define TIMER_PVT_TIM_CTRL_INT_EN 0x00000004 +#define TIMER_PVT_TIM_CTRL_PRESC_MASK 0x0000FF00 +#define TIMER_PVT_TIM_INT_STATUS_SET 0x00000001 + +/* Global timer */ +#define TIMER_GLB_LOW_OFFSET 0x00000000 +#define TIMER_GLB_HI_OFFSET 0x00000004 +#define TIMER_GLB_CTRL_OFFSET 0x00000008 +#define TIMER_GLB_TIM_CTRL_TIM_EN 0x00000001 +#define TIMER_GLB_TIM_CTRL_COMP_EN 0x00000002 +#define TIMER_GLB_TIM_CTRL_INT_EN 0x00000004 +#define TIMER_GLB_TIM_CTRL_AUTO_INC 0x00000008 +#define TIMER_GLB_TIM_CTRL_PRESC_MASK 0x0000FF00 +#define TIMER_GLB_TIM_INT_STATUS_SET 0x00000001 + +#endif /*__TIMER_H */ diff --git a/arch/arm/include/asm/kona-common/clk.h b/arch/arm/include/asm/kona-common/clk.h new file mode 100644 index 0000000000..a5e2fd9d6c --- /dev/null +++ b/arch/arm/include/asm/kona-common/clk.h @@ -0,0 +1,30 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This API file is loosely based on u-boot/drivers/video/ipu.h and linux */ + +#ifndef __KONA_COMMON_CLK_H +#define __KONA_COMMON_CLK_H + +#include + +struct clk; + +/* Only implement required functions for your specific architecture */ +int clk_init(void); +struct clk *clk_get(const char *id); +int clk_enable(struct clk *clk); +void clk_disable(struct clk *clk); +unsigned long clk_get_rate(struct clk *clk); +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); +struct clk *clk_get_parent(struct clk *clk); +int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep); +int clk_bsc_enable(void *base); +int clk_usb_otg_enable(void *base); + +#endif diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h new file mode 100644 index 0000000000..1ff0e55d13 --- /dev/null +++ b/arch/arm/include/asm/kona-common/kona_sdhci.h @@ -0,0 +1,12 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KONA_SDHCI_H +#define __KONA_SDHCI_H + +int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks); + +#endif diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041a16..d4a447b2b8 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1106,6 +1106,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP5_SEVM 3777 #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 +#define MACH_TYPE_COLIBRI_T30 4493 +#define MACH_TYPE_APALIS_T30 4513 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14235,6 +14237,30 @@ extern unsigned int __machine_arch_type; # define machine_is_kzm9g() (0) #endif +#ifdef CONFIG_MACH_COLIBRI_T30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI_T30 +# endif +# define machine_is_colibri_t30() (machine_arch_type == MACH_TYPE_COLIBRI_T30) +#else +# define machine_is_colibri_t30() (0) +#endif + +#ifdef CONFIG_MACH_APALIS_T30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APALIS_T30 +# endif +# define machine_is_apalis_t30() (machine_arch_type == MACH_TYPE_APALIS_T30) +#else +# define machine_is_apalis_t30() (0) +#endif + /* * These have not yet been registered */ diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index ff13f36ba0..1c8c4251ee 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -54,5 +54,151 @@ bcs 1b .endm +#ifdef CONFIG_ARM64 +/* + * Register aliases. + */ +lr .req x30 + +/* + * Branch according to exception level + */ +.macro switch_el, xreg, el3_label, el2_label, el1_label + mrs \xreg, CurrentEL + cmp \xreg, 0xc + b.eq \el3_label + cmp \xreg, 0x8 + b.eq \el2_label + cmp \xreg, 0x4 + b.eq \el1_label +.endm + +/* + * Branch if current processor is a slave, + * choose processor with all zero affinity value as the master. + */ +.macro branch_if_slave, xreg, slave_label + mrs \xreg, mpidr_el1 + tst \xreg, #0xff /* Test Affinity 0 */ + b.ne \slave_label + lsr \xreg, \xreg, #8 + tst \xreg, #0xff /* Test Affinity 1 */ + b.ne \slave_label + lsr \xreg, \xreg, #8 + tst \xreg, #0xff /* Test Affinity 2 */ + b.ne \slave_label + lsr \xreg, \xreg, #16 + tst \xreg, #0xff /* Test Affinity 3 */ + b.ne \slave_label +.endm + +/* + * Branch if current processor is a master, + * choose processor with all zero affinity value as the master. + */ +.macro branch_if_master, xreg1, xreg2, master_label + mrs \xreg1, mpidr_el1 + lsr \xreg2, \xreg1, #32 + lsl \xreg1, \xreg1, #40 + lsr \xreg1, \xreg1, #40 + orr \xreg1, \xreg1, \xreg2 + cbz \xreg1, \master_label +.endm + +.macro armv8_switch_to_el2_m, xreg1 + /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */ + mov \xreg1, #0x5b1 + msr scr_el3, \xreg1 + msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ + mov \xreg1, #0x33ff + msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */ + + /* Initialize SCTLR_EL2 + * + * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1 + * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) + + * EE,WXN,I,SA,C,A,M to 0 + */ + mov \xreg1, #0x0830 + movk \xreg1, #0x30C5, lsl #16 + msr sctlr_el2, \xreg1 + + /* Return to the EL2_SP2 mode from EL3 */ + mov \xreg1, sp + msr sp_el2, \xreg1 /* Migrate SP */ + mrs \xreg1, vbar_el3 + msr vbar_el2, \xreg1 /* Migrate VBAR */ + mov \xreg1, #0x3c9 + msr spsr_el3, \xreg1 /* EL2_SP2 | D | A | I | F */ + msr elr_el3, lr + eret +.endm + +.macro armv8_switch_to_el1_m, xreg1, xreg2 + /* Initialize Generic Timers */ + mrs \xreg1, cnthctl_el2 + orr \xreg1, \xreg1, #0x3 /* Enable EL1 access to timers */ + msr cnthctl_el2, \xreg1 + msr cntvoff_el2, xzr + + /* Initilize MPID/MPIDR registers */ + mrs \xreg1, midr_el1 + mrs \xreg2, mpidr_el1 + msr vpidr_el2, \xreg1 + msr vmpidr_el2, \xreg2 + + /* Disable coprocessor traps */ + mov \xreg1, #0x33ff + msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */ + msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */ + mov \xreg1, #3 << 20 + msr cpacr_el1, \xreg1 /* Enable FP/SIMD at EL1 */ + + /* Initialize HCR_EL2 */ + mov \xreg1, #(1 << 31) /* 64bit EL1 */ + orr \xreg1, \xreg1, #(1 << 29) /* Disable HVC */ + msr hcr_el2, \xreg1 + + /* SCTLR_EL1 initialization + * + * setting RES1 bits (29,28,23,22,20,11) to 1 + * and RES0 bits (31,30,27,21,17,13,10,6) + + * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD, + * CP15BEN,SA0,SA,C,A,M to 0 + */ + mov \xreg1, #0x0800 + movk \xreg1, #0x30d0, lsl #16 + msr sctlr_el1, \xreg1 + + /* Return to the EL1_SP1 mode from EL2 */ + mov \xreg1, sp + msr sp_el1, \xreg1 /* Migrate SP */ + mrs \xreg1, vbar_el2 + msr vbar_el1, \xreg1 /* Migrate VBAR */ + mov \xreg1, #0x3c5 + msr spsr_el2, \xreg1 /* EL1_SP1 | D | A | I | F */ + msr elr_el2, lr + eret +.endm + +#if defined(CONFIG_GICV3) +.macro gic_wait_for_interrupt_m xreg1 +0 : wfi + mrs \xreg1, ICC_IAR1_EL1 + msr ICC_EOIR1_EL1, \xreg1 + cbnz \xreg1, 0b +.endm +#elif defined(CONFIG_GICV2) +.macro gic_wait_for_interrupt_m xreg1, wreg2 +0 : wfi + ldr \wreg2, [\xreg1, GICC_AIAR] + str \wreg2, [\xreg1, GICC_AEOIR] + and \wreg2, \wreg2, #0x3ff + cbnz \wreg2, 0b +.endm +#endif + +#endif /* CONFIG_ARM64 */ + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_MACRO_H__ */ diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index c3b2afd907..1864ab9fb5 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -14,7 +14,6 @@ #if 0 /* XXX###XXX */ -#include #include /* diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index b56e9493ef..323952f5f1 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -73,6 +73,7 @@ struct prcm_regs { u32 cm_ssc_deltamstep_dpll_ddrphy; u32 cm_clkmode_dpll_dsp; u32 cm_shadow_freq_config1; + u32 cm_clkmode_dpll_gmac; u32 cm_mpu_mpu_clkctrl; /* cm1.dsp */ @@ -142,6 +143,8 @@ struct prcm_regs { u32 cm_div_m2_dpll_unipro; u32 cm_ssc_deltamstep_dpll_unipro; u32 cm_ssc_modfreqdiv_dpll_unipro; + u32 cm_coreaon_usb_phy_core_clkctrl; + u32 cm_coreaon_usb_phy2_core_clkctrl; /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; @@ -223,8 +226,11 @@ struct prcm_regs { u32 cm_l3init_hsusbotg_clkctrl; u32 cm_l3init_hsusbtll_clkctrl; u32 cm_l3init_p1500_clkctrl; + u32 cm_l3init_sata_clkctrl; u32 cm_l3init_fsusb_clkctrl; u32 cm_l3init_ocp2scp1_clkctrl; + u32 cm_l3init_ocp2scp3_clkctrl; + u32 cm_l3init_usb_otg_ss_clkctrl; u32 prm_irqstatus_mpu_2; @@ -265,6 +271,7 @@ struct prcm_regs { u32 cm_l4per_mmcsd4_clkctrl; u32 cm_l4per_msprohg_clkctrl; u32 cm_l4per_slimbus2_clkctrl; + u32 cm_l4per_qspi_clkctrl; u32 cm_l4per_uart1_clkctrl; u32 cm_l4per_uart2_clkctrl; u32 cm_l4per_uart3_clkctrl; @@ -309,12 +316,6 @@ struct prcm_regs { u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; - u32 prm_sldo_core_setup; - u32 prm_sldo_core_ctrl; - u32 prm_sldo_mpu_setup; - u32 prm_sldo_mpu_ctrl; - u32 prm_sldo_mm_setup; - u32 prm_sldo_mm_ctrl; u32 prm_abbldo_mpu_setup; u32 prm_abbldo_mpu_ctrl; @@ -339,11 +340,20 @@ struct prcm_regs { /* SCRM stuff, used by some boards */ u32 scrm_auxclk0; u32 scrm_auxclk1; + + /* GMAC Clk Ctrl */ + u32 cm_gmac_gmac_clkctrl; + u32 cm_gmac_clkstctrl; }; struct omap_sys_ctrl_regs { u32 control_status; + u32 control_core_mac_id_0_lo; + u32 control_core_mac_id_0_hi; + u32 control_core_mac_id_1_lo; + u32 control_core_mac_id_1_hi; u32 control_std_fuse_opp_vdd_mpu_2; + u32 control_phy_power_usb; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2; u32 control_core_mmr_lock3; @@ -357,6 +367,7 @@ struct omap_sys_ctrl_regs { u32 control_ldosram_mpu_voltage_ctrl; u32 control_ldosram_core_voltage_ctrl; u32 control_usbotghs_ctrl; + u32 control_phy_power_sata; u32 control_padconf_core_base; u32 control_paconf_global; u32 control_paconf_mode; @@ -483,6 +494,7 @@ struct dplls { const struct dpll_params *iva; const struct dpll_params *usb; const struct dpll_params *ddr; + const struct dpll_params *gmac; }; struct pmic_data { @@ -528,6 +540,7 @@ extern struct prcm_regs const omap5_es2_prcm; extern struct prcm_regs const omap4_prcm; extern struct prcm_regs const dra7xx_prcm; extern struct dplls const **dplls_data; +extern struct dplls dra7xx_dplls; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; @@ -535,6 +548,8 @@ extern struct omap_sys_ctrl_regs const omap4_ctrl; extern struct omap_sys_ctrl_regs const omap5_ctrl; extern struct omap_sys_ctrl_regs const dra7xx_ctrl; +extern struct pmic_data tps659038; + void hw_data_init(void); const struct dpll_params *get_mpu_dpll_params(struct dplls const *); @@ -555,7 +570,6 @@ u32 omap_ddr_clk(void); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); void scale_vcores(struct vcores_data const *); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); @@ -563,11 +577,7 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, u32 txdone, u32 txdone_mask, u32 opp); s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); -/* HW Init Context */ -#define OMAP_INIT_CONTEXT_SPL 0 -#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 -#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 -#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 +void usb_fake_mac_from_die_id(u32 *id); /* ABB */ #define OMAP_ABB_NOMINAL_OPP 0 @@ -588,6 +598,14 @@ static inline u32 omap_revision(void) return *omap_si_rev; } +#define OMAP44xx 0x44000000 + +static inline u8 is_omap44xx(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFF000000) == OMAP44xx; +}; + #define OMAP54xx 0x54000000 static inline u8 is_omap54xx(void) @@ -595,6 +613,14 @@ static inline u8 is_omap54xx(void) extern u32 *const omap_si_rev; return ((*omap_si_rev & 0xFF000000) == OMAP54xx); } + +#define DRA7XX 0x07000000 + +static inline u8 is_dra7xx(void) +{ + extern u32 *const omap_si_rev; + return ((*omap_si_rev & 0xFF000000) == DRA7XX); +} #endif /* @@ -612,6 +638,7 @@ static inline u8 is_omap54xx(void) #define OMAP4430_ES2_3 0x44300230 #define OMAP4460_ES1_0 0x44600100 #define OMAP4460_ES1_1 0x44600110 +#define OMAP4470_ES1_0 0x44700100 /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 @@ -622,6 +649,8 @@ static inline u8 is_omap54xx(void) /* DRA7XX */ #define DRA752_ES1_0 0x07520100 +#define DRA752_ES1_1 0x07520110 +#define DRA722_ES1_0 0x07220100 /* * SRAM scratch space entries diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h index 1ebfa8694f..839af54d48 100644 --- a/arch/arm/include/asm/omap_gpio.h +++ b/arch/arm/include/asm/omap_gpio.h @@ -2,20 +2,7 @@ * Copyright (c) 2009 Wind River Systems, Inc. * Tom Rix * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * This work is derived from the linux 2.6.27 kernel source * To fetch, use the kernel repository @@ -30,16 +17,27 @@ * * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _GPIO_H #define _GPIO_H #include +enum gpio_method { + METHOD_GPIO_24XX = 4, +}; + +#ifdef CONFIG_DM_GPIO + +/* Information about a GPIO bank */ +struct omap_gpio_platdata { + int bank_index; + ulong base; /* address of registers in physical memory */ + enum gpio_method method; +}; + +#else + struct gpio_bank { void *base; int method; @@ -47,8 +45,6 @@ struct gpio_bank { extern const struct gpio_bank *const omap_gpio_bank; -#define METHOD_GPIO_24XX 4 - /** * Check if gpio is valid. * @@ -56,4 +52,6 @@ extern const struct gpio_bank *const omap_gpio_bank; * @return 1 if ok, 0 on error */ int gpio_is_valid(int gpio); +#endif + #endif /* _GPIO_H_ */ diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h deleted file mode 100644 index dd40cb6c16..0000000000 --- a/arch/arm/include/asm/omap_gpmc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * (C) Copyright 2013 Andreas Bießmann - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_OMAP_GPMC_H -#define __ASM_OMAP_GPMC_H - -#include - -#define GPMC_BUF_EMPTY 0 -#define GPMC_BUF_FULL 1 - -#define ECCCLEAR (0x1 << 8) -#define ECCRESULTREG1 (0x1 << 0) -#define ECCSIZE512BYTE 0xFF -#define ECCSIZE1 (ECCSIZE512BYTE << 22) -#define ECCSIZE0 (ECCSIZE512BYTE << 12) -#define ECCSIZE0SEL (0x000 << 0) - -/* Generic ECC Layouts */ -/* Large Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ - 9, 10, 11, 12},\ - .oobfree = {\ - {.offset = 13,\ - .length = 51 } } \ -} -#endif - -/* Large Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13},\ - .oobfree = {\ - {.offset = 14,\ - .length = 50 } } \ -} -#endif - -/* Small Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {1, 2, 3},\ - .oobfree = {\ - {.offset = 4,\ - .length = 12 } } \ -} -#endif - -/* Small Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {2, 3, 4},\ - .oobfree = {\ - {.offset = 5,\ - .length = 11 } } \ -} -#endif - -#endif /* __ASM_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h new file mode 100644 index 0000000000..fb08578f10 --- /dev/null +++ b/arch/arm/include/asm/pcie_layerscape.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCIE_LAYERSCAPE_H_ +#define __PCIE_LAYERSCAPE_H_ + +void pci_init_board(void); +void ft_pcie_setup(void *blob, bd_t *bd); + +#endif diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index f41ad8c559..ddc245bfd5 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -12,6 +12,9 @@ /* Register bit fields */ #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) +#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) +#define L2X0_STNDBY_MODE_EN (1 << 0) +#define L2X0_CTRL_EN 1 struct pl310_regs { u32 pl310_cache_id; @@ -47,6 +50,24 @@ struct pl310_regs { u32 pad9[1]; u32 pl310_clean_inv_line_idx; u32 pl310_clean_inv_way; + u32 pad10[64]; + u32 pl310_lockdown_dbase; + u32 pl310_lockdown_ibase; + u32 pad11[190]; + u32 pl310_addr_filter_start; + u32 pl310_addr_filter_end; + u32 pad12[190]; + u32 pl310_test_operation; + u32 pad13[3]; + u32 pl310_line_data; + u32 pad14[7]; + u32 pl310_line_tag; + u32 pad15[3]; + u32 pl310_debug_ctrl; + u32 pad16[7]; + u32 pl310_prefetch_ctrl; + u32 pad17[7]; + u32 pl310_power_ctrl; }; void pl310_inval_all(void); diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h index c412486db5..d254b95b2a 100644 --- a/arch/arm/include/asm/posix_types.h +++ b/arch/arm/include/asm/posix_types.h @@ -28,9 +28,17 @@ typedef int __kernel_pid_t; typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; + +#ifdef __aarch64__ +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#else typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; +#endif + typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; diff --git a/arch/arm/include/asm/proc-armv/processor.h b/arch/arm/include/asm/proc-armv/processor.h index 5bfab7fb90..532f2079e6 100644 --- a/arch/arm/include/asm/proc-armv/processor.h +++ b/arch/arm/include/asm/proc-armv/processor.h @@ -18,7 +18,7 @@ #ifndef __ASM_PROC_PROCESSOR_H #define __ASM_PROC_PROCESSOR_H -#include +#include #define KERNEL_STACK_SIZE PAGE_SIZE diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index 79cc6443f4..71df5a9e25 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -10,7 +10,24 @@ #ifndef __ASM_PROC_PTRACE_H #define __ASM_PROC_PTRACE_H -#include +#ifdef CONFIG_ARM64 + +#define PCMASK 0 + +#ifndef __ASSEMBLY__ + +/* + * This struct defines the way the registers are stored + * on the stack during an exception. + */ +struct pt_regs { + unsigned long elr; + unsigned long regs[31]; +}; + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_ARM64 */ #define USR26_MODE 0x00 #define FIQ26_MODE 0x01 @@ -21,12 +38,14 @@ #define IRQ_MODE 0x12 #define SVC_MODE 0x13 #define ABT_MODE 0x17 +#define HYP_MODE 0x1a #define UND_MODE 0x1b #define SYSTEM_MODE 0x1f #define MODE_MASK 0x1f #define T_BIT 0x20 #define F_BIT 0x40 #define I_BIT 0x80 +#define A_BIT 0x100 #define CC_V_BIT (1 << 28) #define CC_C_BIT (1 << 29) #define CC_Z_BIT (1 << 30) @@ -106,4 +125,6 @@ static inline int valid_user_regs(struct pt_regs *regs) #endif /* __ASSEMBLY__ */ +#endif /* CONFIG_ARM64 */ + #endif diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h index b4cfa68ca3..c61374e9f2 100644 --- a/arch/arm/include/asm/proc-armv/system.h +++ b/arch/arm/include/asm/proc-armv/system.h @@ -10,11 +10,63 @@ #ifndef __ASM_PROC_SYSTEM_H #define __ASM_PROC_SYSTEM_H -#include - /* * Save the current interrupt enable state & disable IRQs */ +#ifdef CONFIG_ARM64 + +/* + * Save the current interrupt enable state + * and disable IRQs/FIQs + */ +#define local_irq_save(flags) \ + ({ \ + asm volatile( \ + "mrs %0, daif\n" \ + "msr daifset, #3" \ + : "=r" (flags) \ + : \ + : "memory"); \ + }) + +/* + * restore saved IRQ & FIQ state + */ +#define local_irq_restore(flags) \ + ({ \ + asm volatile( \ + "msr daif, %0" \ + : \ + : "r" (flags) \ + : "memory"); \ + }) + +/* + * Enable IRQs/FIQs + */ +#define local_irq_enable() \ + ({ \ + asm volatile( \ + "msr daifclr, #3" \ + : \ + : \ + : "memory"); \ + }) + +/* + * Disable IRQs/FIQs + */ +#define local_irq_disable() \ + ({ \ + asm volatile( \ + "msr daifset, #3" \ + : \ + : \ + : "memory"); \ + }) + +#else /* CONFIG_ARM64 */ + #define local_irq_save(x) \ ({ \ unsigned long temp; \ @@ -109,7 +161,10 @@ : "r" (x) \ : "memory") -#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) +#endif /* CONFIG_ARM64 */ + +#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \ + defined(CONFIG_ARM64) /* * On the StrongARM, "swp" is terminally broken since it bypasses the * cache totally. This means that the cache becomes inconsistent, and, diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 445d4495be..83481c6cda 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -45,7 +45,7 @@ typedef unsigned long mm_segment_t; /* domain register */ #if 0 /* XXX###XXX */ #include #endif /* XXX###XXX */ -#include +#include #include union debug_insn { diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h new file mode 100644 index 0000000000..704b4b0018 --- /dev/null +++ b/arch/arm/include/asm/psci.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __ARM_PSCI_H__ +#define __ARM_PSCI_H__ + +/* PSCI interface */ +#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n)) + +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) + +#define ARM_PSCI_RET_SUCCESS 0 +#define ARM_PSCI_RET_NI (-1) +#define ARM_PSCI_RET_INVAL (-2) +#define ARM_PSCI_RET_DENIED (-3) + +#endif /* __ARM_PSCI_H__ */ diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 73c9087b50..a836f6cc60 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -11,7 +11,7 @@ /* options set using PTRACE_SETOPTIONS */ #define PTRACE_O_TRACESYSGOOD 0x00000001 -#include +#include #ifndef __ASSEMBLY__ #define pc_pointer(v) \ diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h new file mode 100644 index 0000000000..effdb1858d --- /dev/null +++ b/arch/arm/include/asm/secure.h @@ -0,0 +1,26 @@ +#ifndef __ASM_SECURE_H +#define __ASM_SECURE_H + +#include + +#ifdef CONFIG_ARMV7_SECURE_BASE +/* + * Warning, horror ahead. + * + * The target code lives in our "secure ram", but u-boot doesn't know + * that, and has blindly added reloc_off to every relocation + * entry. Gahh. Do the opposite conversion. This hack also prevents + * GCC from generating code veeners, which u-boot doesn't relocate at + * all... + */ +#define secure_ram_addr(_fn) ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + void *__fn = _fn; \ + typeof(_fn) *__tmp = (__fn - gd->reloc_off); \ + __tmp; \ + }) +#else +#define secure_ram_addr(_fn) (_fn) +#endif + +#endif diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h new file mode 100644 index 0000000000..835ca7e4b6 --- /dev/null +++ b/arch/arm/include/asm/semihosting.h @@ -0,0 +1,17 @@ +/* + * Copyright 2014 Broadcom Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SEMIHOSTING_H__ +#define __SEMIHOSTING_H__ + +/* + * ARM semihosting functions for loading images to memory. See the source + * code for more information. + */ +int smh_load(const char *fname, void *memp, int avail, int verbose); +long smh_len(const char *fname); + +#endif /* __SEMIHOSTING_H__ */ diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h deleted file mode 100644 index 28cf5eaeba..0000000000 --- a/arch/arm/include/asm/sizes.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 90e5a9dde1..8acd7cd1bd 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -7,9 +7,29 @@ #ifndef _ASM_SPL_H_ #define _ASM_SPL_H_ +#if defined(CONFIG_OMAP) \ + || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ + || defined(CONFIG_EXYNOS4210) /* Platform-specific defines */ #include +#else +enum { + BOOT_DEVICE_RAM, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NOR, + BOOT_DEVICE_UART, + BOOT_DEVICE_SPI, + BOOT_DEVICE_SATA, + BOOT_DEVICE_I2C, + BOOT_DEVICE_NONE +}; +#endif + /* Linker symbols. */ extern char __bss_start[], __bss_end[]; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 8b5b9f47b4..f5096dc0fd 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,6 +1,89 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H +#ifdef CONFIG_ARM64 + +/* + * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +#define PGTABLE_SIZE (0x10000) + +#ifndef __ASSEMBLY__ + +#define isb() \ + ({asm volatile( \ + "isb" : : : "memory"); \ + }) + +#define wfi() \ + ({asm volatile( \ + "wfi" : : : "memory"); \ + }) + +static inline unsigned int current_el(void) +{ + unsigned int el; + asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); + return el >> 2; +} + +static inline unsigned int get_sctlr(void) +{ + unsigned int el, val; + + el = current_el(); + if (el == 1) + asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); + else if (el == 2) + asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); + else + asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); + + return val; +} + +static inline void set_sctlr(unsigned int val) +{ + unsigned int el; + + el = current_el(); + if (el == 1) + asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); + else if (el == 2) + asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); + else + asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); + + asm volatile("isb"); +} + +void __asm_flush_dcache_all(void); +void __asm_invalidate_dcache_all(void); +void __asm_flush_dcache_range(u64 start, u64 end); +void __asm_invalidate_tlb_all(void); +void __asm_invalidate_icache_all(void); + +void armv8_switch_to_el2(void); +void armv8_switch_to_el1(void); +void gic_init(void); +void gic_send_sgi(unsigned long sgino); +void wait_for_wakeup(void); +void smp_kick_all_cpus(void); + +void flush_l3_cache(void); + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_ARM64 */ + #ifdef __KERNEL__ #define CPU_ARCH_UNKNOWN 0 @@ -45,6 +128,8 @@ #define CR_AFE (1 << 29) /* Access flag enable */ #define CR_TE (1 << 30) /* Thumb exception enable */ +#define PGTABLE_SIZE (4096 * 4) + /* * This is used to ensure the compiler did actually allocate the register we * asked it for some inline assembly sequences. Apparently we can't trust @@ -100,6 +185,7 @@ enum dcache_option { DCACHE_OFF = 0x12, DCACHE_WRITETHROUGH = 0x1a, DCACHE_WRITEBACK = 0x1e, + DCACHE_WRITEALLOC = 0x16, }; /* Size of an MMU section */ @@ -115,7 +201,7 @@ enum { * \param size size of memory region to change * \param option dcache option to select */ -void mmu_set_region_dcache_behaviour(u32 start, int size, +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); /** @@ -126,10 +212,17 @@ void mmu_set_region_dcache_behaviour(u32 start, int size, */ void mmu_page_table_flush(unsigned long start, unsigned long stop); +#ifdef CONFIG_SYS_NONCACHED_MEMORY +void noncached_init(void); +phys_addr_t noncached_alloc(size_t size, size_t align); +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ + #endif /* __ASSEMBLY__ */ #define arch_align_stack(x) (x) #endif /* __KERNEL__ */ +#endif /* CONFIG_ARM64 */ + #endif diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h new file mode 100644 index 0000000000..11407be144 --- /dev/null +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -0,0 +1,98 @@ +/* + * NAND Flash Driver + * + * Copyright (C) 2006-2014 Texas Instruments. + * + * Based on Linux DaVinci NAND driver by TI. + */ + +#ifndef _DAVINCI_NAND_H_ +#define _DAVINCI_NAND_H_ + +#include +#include + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#define MASK_CLE 0x10 +#define MASK_ALE 0x08 + +#ifdef CONFIG_SYS_NAND_MASK_CLE +#undef MASK_CLE +#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#endif +#ifdef CONFIG_SYS_NAND_MASK_ALE +#undef MASK_ALE +#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#endif + +struct davinci_emif_regs { + uint32_t ercsr; + uint32_t awccr; + uint32_t sdbcr; + uint32_t sdrcr; + union { + uint32_t abncr[4]; + uint32_t ab1cr; + uint32_t ab2cr; + uint32_t ab3cr; + uint32_t ab4cr; + }; + uint32_t sdtimr; + uint32_t ddrsr; + uint32_t ddrphycr; + uint32_t ddrphysr; + uint32_t totar; + uint32_t totactr; + uint32_t ddrphyid_rev; + uint32_t sdsretr; + uint32_t eirr; + uint32_t eimr; + uint32_t eimsr; + uint32_t eimcr; + uint32_t ioctrlr; + uint32_t iostatr; + uint32_t rsvd0; + uint32_t one_nand_cr; + uint32_t nandfcr; + uint32_t nandfsr; + uint32_t rsvd1[2]; + uint32_t nandfecc[4]; + uint32_t rsvd2[15]; + uint32_t nand4biteccload; + uint32_t nand4bitecc[4]; + uint32_t nanderradd1; + uint32_t nanderradd2; + uint32_t nanderrval1; + uint32_t nanderrval2; +}; + +#define davinci_emif_regs \ + ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) + +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) +#define DAVINCI_NANDFCR_CS2NAND (1 << 0) + +/* Chip Select setup */ +#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) +#define DAVINCI_ABCR_EXT_WAIT (1 << 30) +#define DAVINCI_ABCR_WSETUP(n) (n << 26) +#define DAVINCI_ABCR_WSTROBE(n) (n << 20) +#define DAVINCI_ABCR_WHOLD(n) (n << 17) +#define DAVINCI_ABCR_RSETUP(n) (n << 13) +#define DAVINCI_ABCR_RSTROBE(n) (n << 7) +#define DAVINCI_ABCR_RHOLD(n) (n << 4) +#define DAVINCI_ABCR_TA(n) (n << 2) +#define DAVINCI_ABCR_ASIZE_16BIT 1 +#define DAVINCI_ABCR_ASIZE_8BIT 0 + +void davinci_nand_init(struct nand_chip *nand); + +#endif diff --git a/arch/arm/include/asm/ti-common/keystone_nav.h b/arch/arm/include/asm/ti-common/keystone_nav.h new file mode 100644 index 0000000000..696d8c6fc0 --- /dev/null +++ b/arch/arm/include/asm/ti-common/keystone_nav.h @@ -0,0 +1,191 @@ +/* + * Multicore Navigator definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KEYSTONE_NAV_H_ +#define _KEYSTONE_NAV_H_ + +#include +#include + +#define QM_OK 0 +#define QM_ERR -1 +#define QM_DESC_TYPE_HOST 0 +#define QM_DESC_PSINFO_IN_DESCR 0 +#define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \ + (QM_DESC_PSINFO_IN_DESCR << 22) + +/* Packet Info */ +#define QM_DESC_PINFO_EPIB 1 +#define QM_DESC_PINFO_RETURN_OWN 1 +#define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \ + (QM_DESC_PINFO_RETURN_OWN << 15) + +struct qm_cfg_reg { + u32 revision; + u32 __pad1; + u32 divert; + u32 link_ram_base0; + u32 link_ram_size0; + u32 link_ram_base1; + u32 link_ram_size1; + u32 link_ram_base2; + u32 starvation[0]; +}; + +struct descr_mem_setup_reg { + u32 base_addr; + u32 start_idx; + u32 desc_reg_size; + u32 _res0; +}; + +struct qm_reg_queue { + u32 entry_count; + u32 byte_count; + u32 packet_size; + u32 ptr_size_thresh; +}; + +struct qm_config { + /* QM module addresses */ + u32 stat_cfg; /* status and config */ + struct qm_reg_queue *queue; /* management region */ + u32 mngr_vbusm; /* management region (VBUSM) */ + u32 i_lram; /* internal linking RAM */ + struct qm_reg_queue *proxy; + u32 status_ram; + struct qm_cfg_reg *mngr_cfg; + /* Queue manager config region */ + u32 intd_cfg; /* QMSS INTD config region */ + struct descr_mem_setup_reg *desc_mem; + /* descritor memory setup region*/ + u32 region_num; + u32 pdsp_cmd; /* PDSP1 command interface */ + u32 pdsp_ctl; /* PDSP1 control registers */ + u32 pdsp_iram; + /* QM configuration parameters */ + + u32 qpool_num; /* */ +}; + +struct qm_host_desc { + u32 desc_info; + u32 tag_info; + u32 packet_info; + u32 buff_len; + u32 buff_ptr; + u32 next_bdptr; + u32 orig_buff_len; + u32 orig_buff_ptr; + u32 timestamp; + u32 swinfo[3]; + u32 ps_data[20]; +}; + +#define HDESC_NUM 256 + +int qm_init(void); +void qm_close(void); +void qm_push(struct qm_host_desc *hd, u32 qnum); +struct qm_host_desc *qm_pop(u32 qnum); + +void qm_buff_push(struct qm_host_desc *hd, u32 qnum, + void *buff_ptr, u32 buff_len); + +struct qm_host_desc *qm_pop_from_free_pool(void); +void queue_close(u32 qnum); + +/* + * DMA API + */ +#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \ + psloc, sopoff, qmgr, qnum) \ + (((einfo & 1) << 30) | \ + ((psinfo & 1) << 29) | \ + ((rxerr & 1) << 28) | \ + ((desc & 3) << 26) | \ + ((psloc & 1) << 25) | \ + ((sopoff & 0x1ff) << 16) | \ + ((qmgr & 3) << 12) | \ + ((qnum & 0xfff) << 0)) + +#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \ + (((fd0qm & 3) << 28) | \ + ((fd0qnum & 0xfff) << 16) | \ + ((fd1qm & 3) << 12) | \ + ((fd1qnum & 0xfff) << 0)) + +#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31) +#define CPDMA_CHAN_A_TDOWN (1 << 30) +#define TDOWN_TIMEOUT_COUNT 100 + +struct global_ctl_regs { + u32 revision; + u32 perf_control; + u32 emulation_control; + u32 priority_control; + u32 qm_base_addr[4]; +}; + +struct tx_chan_regs { + u32 cfg_a; + u32 cfg_b; + u32 res[6]; +}; + +struct rx_chan_regs { + u32 cfg_a; + u32 res[7]; +}; + +struct rx_flow_regs { + u32 control; + u32 tags; + u32 tag_sel; + u32 fdq_sel[2]; + u32 thresh[3]; +}; + +struct pktdma_cfg { + struct global_ctl_regs *global; + struct tx_chan_regs *tx_ch; + u32 tx_ch_num; + struct rx_chan_regs *rx_ch; + u32 rx_ch_num; + u32 *tx_sched; + struct rx_flow_regs *rx_flows; + u32 rx_flow_num; + + u32 rx_free_q; + u32 rx_rcv_q; + u32 tx_snd_q; + + u32 rx_flow; /* flow that is used for RX */ +}; + +extern struct pktdma_cfg netcp_pktdma; + +/* + * packet dma user allocates memory for rx buffers + * and describe it in the following structure + */ +struct rx_buff_desc { + u8 *buff_ptr; + u32 num_buffs; + u32 buff_len; + u32 rx_flow; +}; + +int ksnav_close(struct pktdma_cfg *pktdma); +int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers); +int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2); +void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes); +void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd); + +#endif /* _KEYSTONE_NAV_H_ */ diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h new file mode 100644 index 0000000000..011c03cf88 --- /dev/null +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -0,0 +1,249 @@ +/* + * emac definitions for keystone2 devices + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KEYSTONE_NET_H_ +#define _KEYSTONE_NET_H_ + +#include + +/* EMAC */ +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) +#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) +#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) +#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x04 +#define CPGMACSL_REG_STATUS 0x08 +#define CPGMACSL_REG_RESET 0x0c +#define CPGMACSL_REG_MAXLEN 0x10 + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) +#define CPGMACSL_REG_RX_PRI_MAP 0x020 +#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) +#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) +#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x330 +#define CPGMACSL_REG_STATUS 0x334 +#define CPGMACSL_REG_RESET 0x338 +#define CPGMACSL_REG_MAXLEN 0x024 + +#endif + +#define KEYSTONE2_EMAC_GIG_ENABLE + +#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE + +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ + +/* MII Status Register */ +#define MII_STATUS_REG 1 +#define MII_STATUS_LINK_MASK 0x4 + +#define MDIO_CONTROL_IDLE 0x80000000 +#define MDIO_CONTROL_ENABLE 0x40000000 +#define MDIO_CONTROL_FAULT_ENABLE 0x40000 +#define MDIO_CONTROL_FAULT 0x80000 +#define MDIO_USERACCESS0_GO 0x80000000 +#define MDIO_USERACCESS0_WRITE_READ 0x0 +#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000 +#define MDIO_USERACCESS0_ACK 0x20000000 + +#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 +#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) +#define EMAC_MACCONTROL_GIGFORCE BIT(17) +#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15) + +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 + +struct mac_sl_cfg { + u_int32_t max_rx_len; /* Maximum receive packet length. */ + u_int32_t ctl; /* Control bitfield */ +}; + +/** + * Definition: Control bitfields used in the ctl field of mac_sl_cfg + */ +#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24) +#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23) +#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22) +#define GMACSL_RX_ENABLE_EXT_CTL BIT(18) +#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17) +#define GMACSL_RX_ENABLE_IFCTL_B BIT(16) +#define GMACSL_RX_ENABLE_IFCTL_A BIT(15) +#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11) +#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10) +#define GMACSL_ENABLE_GIG_MODE BIT(7) +#define GMACSL_TX_ENABLE_PACE BIT(6) +#define GMACSL_ENABLE BIT(5) +#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4) +#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3) +#define GMACSL_ENABLE_LOOPBACK BIT(1) +#define GMACSL_ENABLE_FULL_DUPLEX BIT(0) + +/* EMAC SL function return values */ +#define GMACSL_RET_OK 0 +#define GMACSL_RET_INVALID_PORT -1 +#define GMACSL_RET_WARN_RESET_INCOMPLETE -2 +#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 +#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 + +/* EMAC SL register definitions */ +#define DEVICE_EMACSL_RESET_POLL_COUNT 100 + +/* Soft reset register values */ +#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0) +#define CPGMAC_REG_RESET_VAL_RESET BIT(0) +#define CPGMAC_REG_MAXLEN_LEN 0x3fff + +/* CPSW */ +/* Control bitfields */ +#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5) +#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4) +#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3) +#define CPSW_CTL_P0_ENABLE BIT(2) +#define CPSW_CTL_VLAN_AWARE BIT(1) +#define CPSW_CTL_FIFO_LOOPBACK BIT(0) + +#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS +#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) + +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800) +#define CPSW_REG_CTL 0x004 +#define CPSW_REG_STAT_PORT_EN 0x00c +#define CPSW_REG_MAXLEN 0x040 +#define CPSW_REG_ALE_CONTROL 0x608 +#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000) +#define CPSW_REG_CTL 0x00004 +#define CPSW_REG_STAT_PORT_EN 0x00014 +#define CPSW_REG_MAXLEN 0x01024 +#define CPSW_REG_ALE_CONTROL 0x1e008 +#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff + +#endif + +#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) +#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) +#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 + +#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE +#define SWITCH_MAX_PKT_SIZE 9000 + +/* SGMII */ +#define SGMII_REG_STATUS_LOCK BIT(4) +#define SGMII_REG_STATUS_LINK BIT(0) +#define SGMII_REG_STATUS_AUTONEG BIT(2) +#define SGMII_REG_CONTROL_AUTONEG BIT(0) +#define SGMII_REG_CONTROL_MASTER BIT(5) +#define SGMII_REG_MR_ADV_ENABLE BIT(0) +#define SGMII_REG_MR_ADV_LINK BIT(15) +#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) +#define SGMII_REG_MR_ADV_GIG_MODE BIT(11) + +#define SGMII_LINK_MAC_MAC_AUTONEG 0 +#define SGMII_LINK_MAC_PHY 1 +#define SGMII_LINK_MAC_MAC_FORCED 2 +#define SGMII_LINK_MAC_FIBER 3 +#define SGMII_LINK_MAC_PHY_FORCED 4 + +#ifdef CONFIG_KSNET_NETCP_V1_0 +#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) +#elif defined CONFIG_KSNET_NETCP_V1_5 +#define SGMII_OFFSET(x) ((x) * 0x100) +#endif + +#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000) +#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004) +#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010) +#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014) +#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018) +#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020) +#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030) +#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) +#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) + +/* PSS */ +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 + +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+4);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+8);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+12); + +#endif + +/* EMAC MDIO Registers Structure */ +struct mdio_regs { + u32 version; + u32 control; + u32 alive; + u32 link; + u32 linkintraw; + u32 linkintmasked; + u32 rsvd0[2]; + u32 userintraw; + u32 userintmasked; + u32 userintmaskset; + u32 userintmaskclear; + u32 rsvd1[20]; + u32 useraccess0; + u32 userphysel0; + u32 useraccess1; + u32 userphysel1; +}; + +struct eth_priv_t { + char int_name[32]; + int rx_flow; + int phy_addr; + int slave_port; + int sgmii_link_type; + struct phy_device *phy_dev; +}; + +int keystone2_emac_initialize(struct eth_priv_t *eth_priv); +void sgmii_serdes_setup_156p25mhz(void); +void sgmii_serdes_shutdown(void); + +#endif /* _KEYSTONE_NET_H_ */ diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h b/arch/arm/include/asm/ti-common/keystone_serdes.h new file mode 100644 index 0000000000..2e92411404 --- /dev/null +++ b/arch/arm/include/asm/ti-common/keystone_serdes.h @@ -0,0 +1,55 @@ +/* + * Texas Instruments Keystone SerDes driver + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TI_KEYSTONE_SERDES_H__ +#define __TI_KEYSTONE_SERDES_H__ + +/* SERDES Reference clock */ +enum ks2_serdes_clock { + SERDES_CLOCK_100M, /* 100 MHz */ + SERDES_CLOCK_122P88M, /* 122.88 MHz */ + SERDES_CLOCK_125M, /* 125 MHz */ + SERDES_CLOCK_156P25M, /* 156.25 MHz */ + SERDES_CLOCK_312P5M, /* 312.5 MHz */ +}; + +/* SERDES Lane Baud Rate */ +enum ks2_serdes_rate { + SERDES_RATE_4P9152G, /* 4.9152 GBaud */ + SERDES_RATE_5G, /* 5 GBaud */ + SERDES_RATE_6P144G, /* 6.144 GBaud */ + SERDES_RATE_6P25G, /* 6.25 GBaud */ + SERDES_RATE_10p3125g, /* 10.3215 GBaud */ + SERDES_RATE_12p5g, /* 12.5 GBaud */ +}; + +/* SERDES Lane Rate Mode */ +enum ks2_serdes_rate_mode { + SERDES_FULL_RATE, + SERDES_HALF_RATE, + SERDES_QUARTER_RATE, +}; + +/* SERDES PHY TYPE */ +enum ks2_serdes_interface { + SERDES_PHY_SGMII, + SERDES_PHY_PCSR, /* XGE SERDES */ +}; + +struct ks2_serdes { + enum ks2_serdes_clock clk; + enum ks2_serdes_rate rate; + enum ks2_serdes_rate_mode rate_mode; + enum ks2_serdes_interface intf; + u32 loopback; +}; + +int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes); + +#endif /* __TI_KEYSTONE_SERDES_H__ */ diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h new file mode 100644 index 0000000000..d3ab75fa32 --- /dev/null +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _TI_COMMON_SYS_PROTO_H_ +#define _TI_COMMON_SYS_PROTO_H_ + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_OMAP_COMMON +#define TI_ARMV7_DRAM_ADDR_SPACE_START 0x80000000 +#define TI_ARMV7_DRAM_ADDR_SPACE_END 0xFFFFFFFF + +#define OMAP_INIT_CONTEXT_SPL 0 +#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 + +static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (pc < TI_ARMV7_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * u-boot can be running from sdram either because of configuration + * Header or by SPL. If because of CH, then the romcode sets the + * CHSETTINGS executed bit to true in the boot parameter structure that + * it passes to the bootloader.This parameter is stored in the ch_flags + * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a + * mandatory section if CH is present. + */ + if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + return 0; + else + return running_from_sdram(); +} + +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap_hw_init_context(void) +{ +#ifdef CONFIG_SPL_BUILD + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; + else + return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; +#endif +} +#endif + +#endif diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h new file mode 100644 index 0000000000..4a311d4a2f --- /dev/null +++ b/arch/arm/include/asm/ti-common/ti-aemif.h @@ -0,0 +1,39 @@ +/* + * AEMIF definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _AEMIF_H_ +#define _AEMIF_H_ + +#define AEMIF_NUM_CS 4 +#define AEMIF_MODE_NOR 0 +#define AEMIF_MODE_NAND 1 +#define AEMIF_MODE_ONENAND 2 +#define AEMIF_PRESERVE -1 + +struct aemif_config { + unsigned mode; + unsigned select_strobe; + unsigned extend_wait; + unsigned wr_setup; + unsigned wr_strobe; + unsigned wr_hold; + unsigned rd_setup; + unsigned rd_strobe; + unsigned rd_hold; + unsigned turn_around; + enum { + AEMIF_WIDTH_8 = 0, + AEMIF_WIDTH_16 = 1, + AEMIF_WIDTH_32 = 2, + } width; +}; + +void aemif_init(int num_cs, struct aemif_config *config); + +#endif diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h new file mode 100644 index 0000000000..5adc1dac0e --- /dev/null +++ b/arch/arm/include/asm/ti-common/ti-edma3.h @@ -0,0 +1,121 @@ +/* + * Enhanced Direct Memory Access (EDMA3) Controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EDMA3_H_ +#define _EDMA3_H_ + +#include + +#define EDMA3_PARSET_NULL_LINK 0xffff + +/* + * All parameter RAM set options + * opt field in edma3_param_set_config structure + */ +#define EDMA3_SLOPT_PRIV_LEVEL BIT(31) +#define EDMA3_SLOPT_PRIV_ID(id) ((0xf & (id)) << 24) +#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23) +#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22) +#define EDMA3_SLOPT_INTERM_COMP_INT_ENB BIT(21) +#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20) +#define EDMA3_SLOPT_COMP_CODE(code) ((0x3f & (code)) << 12) +#define EDMA3_SLOPT_FIFO_WIDTH_8 0 +#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w & 0x7) << 8) +#define EDMA3_SLOPT_STATIC BIT(3) +#define EDMA3_SLOPT_AB_SYNC BIT(2) +#define EDMA3_SLOPT_DST_ADDR_CONST_MODE BIT(1) +#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE BIT(0) + +enum edma3_address_mode { + INCR = 0, + FIFO = 1 +}; + +enum edma3_fifo_width { + W8BIT = 0, + W16BIT = 1, + W32BIT = 2, + W64BIT = 3, + W128BIT = 4, + W256BIT = 5 +}; + +enum edma3_sync_dimension { + ASYNC = 0, + ABSYNC = 1 +}; + +/* PaRAM slots are laid out like this */ +struct edma3_slot_layout { + u32 opt; + u32 src; + u32 a_b_cnt; + u32 dst; + u32 src_dst_bidx; + u32 link_bcntrld; + u32 src_dst_cidx; + u32 ccnt; +} __packed; + +/* + * Use this to assign trigger word number of edma3_slot_layout struct. + * trigger_word_name - is the exact name from edma3_slot_layout. + */ +#define EDMA3_TWORD(trigger_word_name)\ + (offsetof(struct edma3_slot_layout, trigger_word_name) / 4) + +struct edma3_slot_config { + u32 opt; + u32 src; + u32 dst; + int bcnt; + int acnt; + int ccnt; + int src_bidx; + int dst_bidx; + int src_cidx; + int dst_cidx; + int bcntrld; + int link; +}; + +struct edma3_channel_config { + int slot; + int chnum; + int complete_code; /* indicate pending complete interrupt */ + int trigger_slot_word; /* only used for qedma */ +}; + +void qedma3_start(u32 base, struct edma3_channel_config *cfg); +void qedma3_stop(u32 base, struct edma3_channel_config *cfg); +void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg); +int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg); +void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param); +void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param); + +void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode, + enum edma3_fifo_width width); +void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx); +void edma3_set_dest_addr(u32 base, int slot, u32 dst); + +void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode, + enum edma3_fifo_width width); +void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx); +void edma3_set_src_addr(u32 base, int slot, u32 src); + +void edma3_set_transfer_params(u32 base, int slot, int acnt, + int bcnt, int ccnt, u16 bcnt_rld, + enum edma3_sync_dimension sync_mode); + +#endif diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 71dc049da6..2326420a7f 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -39,7 +39,11 @@ typedef unsigned int u32; typedef signed long long s64; typedef unsigned long long u64; +#ifdef CONFIG_ARM64 +#define BITS_PER_LONG 64 +#else /* CONFIG_ARM64 */ #define BITS_PER_LONG 32 +#endif /* CONFIG_ARM64 */ /* Dma addresses are 32-bits wide. */ diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index b16694c72f..f97f3dd149 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -45,4 +45,19 @@ void reset_timer_masked (void); ulong get_timer_masked (void); void udelay_masked (unsigned long usec); +/* calls to c from vectors.S */ +void bad_mode(void); +void do_undefined_instruction(struct pt_regs *pt_regs); +void do_software_interrupt(struct pt_regs *pt_regs); +void do_prefetch_abort(struct pt_regs *pt_regs); +void do_data_abort(struct pt_regs *pt_regs); +void do_not_used(struct pt_regs *pt_regs); +#ifdef CONFIG_ARM64 +void do_fiq(struct pt_regs *pt_regs, unsigned int esr); +void do_irq(struct pt_regs *pt_regs, unsigned int esr); +#else +void do_fiq(struct pt_regs *pt_regs); +void do_irq(struct pt_regs *pt_regswq); +#endif + #endif /* _U_BOOT_ARM_H_ */ diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index 2b5fce86ab..43cc494683 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -27,7 +27,6 @@ #ifndef __ASSEMBLY__ typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ unsigned long bi_arm_freq; /* arm frequency */ @@ -44,6 +43,10 @@ typedef struct bd_info { #endif /* !CONFIG_SYS_GENERIC_BOARD */ /* For image.h:image_check_target_arch() */ +#ifndef CONFIG_ARM64 #define IH_ARCH_DEFAULT IH_ARCH_ARM +#else +#define IH_ARCH_DEFAULT IH_ARCH_ARM64 +#endif #endif /* _U_BOOT_H_ */ diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h index 44593a8949..0a228fb8ee 100644 --- a/arch/arm/include/asm/unaligned.h +++ b/arch/arm/include/asm/unaligned.h @@ -8,7 +8,7 @@ /* * Select endianness */ -#ifndef __ARMEB__ +#if __BYTE_ORDER == __LITTLE_ENDIAN #define get_unaligned __get_unaligned_le #define put_unaligned __put_unaligned_le #else diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S new file mode 100644 index 0000000000..d47a892652 --- /dev/null +++ b/arch/arm/include/debug/8250.S @@ -0,0 +1,52 @@ +/* + * arch/arm/include/debug/8250.S + * + * Copyright (C) 1994-2013 Russell King + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + + .macro addruart, rp, rv, tmp + ldr \rp, =CONFIG_DEBUG_UART_PHYS + ldr \rv, =CONFIG_DEBUG_UART_VIRT + .endm + +#ifdef CONFIG_DEBUG_UART_8250_WORD + .macro store, rd, rx:vararg + str \rd, \rx + .endm + + .macro load, rd, rx:vararg + ldr \rd, \rx + .endm +#else + .macro store, rd, rx:vararg + strb \rd, \rx + .endm + + .macro load, rd, rx:vararg + ldrb \rd, \rx + .endm +#endif + +#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT + + .macro senduart,rd,rx + store \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: load \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + .macro waituart,rd,rx +#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL +1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] + tst \rd, #UART_MSR_CTS + beq 1001b +#endif + .endm diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index a68adf97ab..d74e4b8415 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -5,79 +5,52 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \ + _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o -LIB = $(obj)lib$(ARCH).o -LIBGCC = $(obj)libgcc.o - -GLSOBJS += _ashldi3.o -GLSOBJS += _ashrdi3.o -GLSOBJS += _divsi3.o -GLSOBJS += _lshrdi3.o -GLSOBJS += _modsi3.o -GLSOBJS += _udivsi3.o -GLSOBJS += _umodsi3.o - -GLCOBJS += div0.o +ifdef CONFIG_ARM64 +obj-y += crt0_64.o +else +obj-y += vectors.o crt0.o +endif ifndef CONFIG_SPL_BUILD -SOBJS-y += relocate.o +ifdef CONFIG_ARM64 +obj-y += relocate_64.o +else +obj-y += relocate.o +endif ifndef CONFIG_SYS_GENERIC_BOARD -COBJS-y += board.o +obj-y += board.o endif -COBJS-y += sections.o -COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o -SOBJS-y += crt0.o -SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o -SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o +obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o +obj-$(CONFIG_USE_ARCH_MEMSET) += memset.o +obj-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o else -COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o -ifndef CONFIG_SPL_NO_CPU_SUPPORT_CODE -SOBJS-y += crt0.o -endif +obj-$(CONFIG_SPL_FRAMEWORK) += spl.o endif +obj-$(CONFIG_SEMIHOSTING) += semihosting.o -COBJS-y += interrupts.o -COBJS-y += reset.o - -COBJS-y += cache.o -COBJS-y += cache-cp15.o - -SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ - $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -LGOBJS := $(addprefix $(obj),$(GLSOBJS)) \ - $(addprefix $(obj),$(GLCOBJS)) - -# Always build libarm.o -TARGETS := $(LIB) +obj-y += sections.o +ifdef CONFIG_ARM64 +obj-y += gic_64.o +obj-y += interrupts_64.o +else +obj-y += interrupts.o +endif +obj-y += reset.o -# Build private libgcc only when asked for -ifdef USE_PRIVATE_LIBGCC -TARGETS += $(LIBGCC) +obj-y += cache.o +ifndef CONFIG_ARM64 +obj-y += cache-cp15.o endif +obj-$(CONFIG_DEBUG_LL) += debug.o + # For EABI conformant tool chains, provide eabi_compat() ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) -TARGETS += $(obj)eabi_compat.o +extra-y += eabi_compat.o endif - -all: $(TARGETS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(LIBGCC): $(obj).depend $(LGOBJS) - $(call cmd_link_o_target, $(LGOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S index cfbadb2ab9..601549304e 100644 --- a/arch/arm/lib/_divsi3.S +++ b/arch/arm/lib/_divsi3.S @@ -1,4 +1,3 @@ - .macro ARM_DIV_BODY dividend, divisor, result, curbit #if __LINUX_ARM_ARCH__ >= 5 diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S index 539c584997..3d31a559f8 100644 --- a/arch/arm/lib/_modsi3.S +++ b/arch/arm/lib/_modsi3.S @@ -1,4 +1,3 @@ - .macro ARM_MOD_BODY dividend, divisor, order, spare #if __LINUX_ARM_ARCH__ >= 5 diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c new file mode 100644 index 0000000000..5aee498d35 --- /dev/null +++ b/arch/arm/lib/asm-offsets.c @@ -0,0 +1,288 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#if defined(CONFIG_MB86R0x) +#include +#endif +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX35) \ + || defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) +#include +#endif +#if defined(CONFIG_SOC_MX6) +#include +#endif + +int main(void) +{ + /* + * TODO : Check if each entry in this file is really necessary. + * - struct mb86r0x_ddr2 + * - struct mb86r0x_memc + * - struct esdramc_regs + * - struct max_regs + * - struct aips_regs + * - struct aipi_regs + * - struct clkctl + * - struct dpll + * are used only for generating asm-offsets.h. + * It means their offset addresses are referenced only from assembly + * code. Is it better to define the macros directly in headers? + */ + +#if defined(CONFIG_MB86R0x) + /* ddr2 controller */ + DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); + DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); + DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); + DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); + DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); + DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); + DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); + DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); + DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); + DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); + DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); + DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); + DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); + DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); + DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); + + /* clock reset generator */ + DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); + DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); + DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); + DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); + DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); + DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); + + /* chip control module */ + DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); + + /* external bus interface */ + DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); + DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); + DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); + DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); + DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); + DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); + DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); + DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); + DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); +#endif + +#if defined(CONFIG_SOC_MX25) + /* Clock Control Module */ + DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); + DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); + DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); + + /* Enhanced SDRAM Controller */ + DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); + DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); + DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); +#endif + +#if defined(CONFIG_SOC_MX27) + DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); + DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); + + DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); + DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); + DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); + DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); + DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); + DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); + DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); + + DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); + DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); + DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); + DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); + DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); + + DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, gpcr)); + DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, fmcr)); +#endif + +#if defined(CONFIG_SOC_MX35) + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); + DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); + DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); + DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); + DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); + DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); + DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); + DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); + DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); + DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); + DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); + DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); + DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); + DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); + DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); + DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); + DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); + DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); + DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); + DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); +#endif + +#if defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); + DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); + DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); + DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); + DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); + DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); + DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); + DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); + DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); + DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); + DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); + DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); + DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); + DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); + DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); + DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); + DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); + DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); + DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); + DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); + DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); + DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); + DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); + DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); + DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); + DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); + DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); + DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); + DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); + DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); + DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); + DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); + DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); + DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); +#if defined(CONFIG_SOC_MX53) + DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); +#endif + + /* DPLL */ + DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); + DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); + DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); + DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); + DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); + DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); + DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); + DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); +#endif +#if defined(CONFIG_SOC_MX6) + DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr)); + DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr)); + DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr)); + DEFINE(CCM_CCSR, offsetof(struct mxc_ccm_reg, ccsr)); + DEFINE(CCM_CACRR, offsetof(struct mxc_ccm_reg, cacrr)); + DEFINE(CCM_CBCDR, offsetof(struct mxc_ccm_reg, cbcdr)); + DEFINE(CCM_CBCMR, offsetof(struct mxc_ccm_reg, cbcmr)); + DEFINE(CCM_CSCMR1, offsetof(struct mxc_ccm_reg, cscmr1)); + DEFINE(CCM_CSCMR2, offsetof(struct mxc_ccm_reg, cscmr2)); + DEFINE(CCM_CSCDR1, offsetof(struct mxc_ccm_reg, cscdr1)); + DEFINE(CCM_CS1CDR, offsetof(struct mxc_ccm_reg, cs1cdr)); + DEFINE(CCM_CS2CDR, offsetof(struct mxc_ccm_reg, cs2cdr)); + DEFINE(CCM_CDCDR, offsetof(struct mxc_ccm_reg, cdcdr)); + DEFINE(CCM_CHSCCDR, offsetof(struct mxc_ccm_reg, chsccdr)); + DEFINE(CCM_CSCDR2, offsetof(struct mxc_ccm_reg, cscdr2)); + DEFINE(CCM_CSCDR3, offsetof(struct mxc_ccm_reg, cscdr3)); + DEFINE(CCM_CSCDR4, offsetof(struct mxc_ccm_reg, cscdr4)); + DEFINE(CCM_CDHIPR, offsetof(struct mxc_ccm_reg, cdhipr)); + DEFINE(CCM_CDCR, offsetof(struct mxc_ccm_reg, cdcr)); + DEFINE(CCM_CTOR, offsetof(struct mxc_ccm_reg, ctor)); + DEFINE(CCM_CLPCR, offsetof(struct mxc_ccm_reg, clpcr)); + DEFINE(CCM_CISR, offsetof(struct mxc_ccm_reg, cisr)); + DEFINE(CCM_CIMR, offsetof(struct mxc_ccm_reg, cimr)); + DEFINE(CCM_CCOSR, offsetof(struct mxc_ccm_reg, ccosr)); + DEFINE(CCM_CGPR, offsetof(struct mxc_ccm_reg, cgpr)); + DEFINE(CCM_CCGR0, offsetof(struct mxc_ccm_reg, CCGR0)); + DEFINE(CCM_CCGR1, offsetof(struct mxc_ccm_reg, CCGR1)); + DEFINE(CCM_CCGR2, offsetof(struct mxc_ccm_reg, CCGR2)); + DEFINE(CCM_CCGR3, offsetof(struct mxc_ccm_reg, CCGR3)); + DEFINE(CCM_CCGR4, offsetof(struct mxc_ccm_reg, CCGR4)); + DEFINE(CCM_CCGR5, offsetof(struct mxc_ccm_reg, CCGR5)); + DEFINE(CCM_CCGR6, offsetof(struct mxc_ccm_reg, CCGR6)); + DEFINE(CCM_CCGR7, offsetof(struct mxc_ccm_reg, CCGR7)); + DEFINE(CCM_CMEOR, offsetof(struct mxc_ccm_reg, cmeor)); + + DEFINE(ANATOP_PLL_ENET, offsetof(struct anatop_regs, pll_enet)); +#endif + return 0; +} diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index ad78e73667..3c0ba079d3 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include #include #include @@ -62,25 +64,15 @@ extern void dataflash_print_info(void); ************************************************************************ * May be supplied by boards if desired */ -inline void __coloured_LED_init(void) {} -void coloured_LED_init(void) - __attribute__((weak, alias("__coloured_LED_init"))); -inline void __red_led_on(void) {} -void red_led_on(void) __attribute__((weak, alias("__red_led_on"))); -inline void __red_led_off(void) {} -void red_led_off(void) __attribute__((weak, alias("__red_led_off"))); -inline void __green_led_on(void) {} -void green_led_on(void) __attribute__((weak, alias("__green_led_on"))); -inline void __green_led_off(void) {} -void green_led_off(void) __attribute__((weak, alias("__green_led_off"))); -inline void __yellow_led_on(void) {} -void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on"))); -inline void __yellow_led_off(void) {} -void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off"))); -inline void __blue_led_on(void) {} -void blue_led_on(void) __attribute__((weak, alias("__blue_led_on"))); -inline void __blue_led_off(void) {} -void blue_led_off(void) __attribute__((weak, alias("__blue_led_off"))); +__weak void coloured_LED_init(void) {} +__weak void red_led_on(void) {} +__weak void red_led_off(void) {} +__weak void green_led_on(void) {} +__weak void green_led_off(void) {} +__weak void yellow_led_on(void) {} +__weak void yellow_led_off(void) {} +__weak void blue_led_on(void) {} +__weak void blue_led_off(void) {} /* ************************************************************************ @@ -105,8 +97,8 @@ static int display_banner(void) { printf("\n\n%s\n\n", version_string); debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", - _TEXT_BASE, - _bss_start_ofs + _TEXT_BASE, _bss_end_ofs + _TEXT_BASE); + (ulong)&_start, + (ulong)&__bss_start, (ulong)&__bss_end); #ifdef CONFIG_MODEM_SUPPORT debug("Modem Support enabled\n"); #endif @@ -197,29 +189,21 @@ static int arm_pci_init(void) */ typedef int (init_fnc_t) (void); -int print_cpuinfo(void); - -void __dram_init_banksize(void) +__weak void dram_init_banksize(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; } -void dram_init_banksize(void) - __attribute__((weak, alias("__dram_init_banksize"))); -int __arch_cpu_init(void) +__weak int arch_cpu_init(void) { return 0; } -int arch_cpu_init(void) - __attribute__((weak, alias("__arch_cpu_init"))); -int __power_init_board(void) +__weak int power_init_board(void) { return 0; } -int power_init_board(void) - __attribute__((weak, alias("__power_init_board"))); /* Record the board_init_f() bootstage (after arch_cpu_init()) */ static int mark_bootstage(void) @@ -250,9 +234,7 @@ init_fnc_t *init_sequence[] = { serial_init, /* serial communications setup */ console_init_f, /* stage 1 init of console */ display_banner, /* say that we are here */ -#if defined(CONFIG_DISPLAY_CPUINFO) print_cpuinfo, /* display cpu info (and speed) */ -#endif #if defined(CONFIG_DISPLAY_BOARDINFO) checkboard, /* display board info */ #endif @@ -277,13 +259,13 @@ void board_init_f(ulong bootflag) memset((void *)gd, 0, sizeof(gd_t)); - gd->mon_len = _bss_end_ofs; + gd->mon_len = (ulong)&__bss_end - (ulong)_start; #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ - gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE); + gd->fdt_blob = &_end; #endif /* Allow the early environment to override the fdt address */ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, @@ -322,7 +304,7 @@ void board_init_f(ulong bootflag) gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; #endif - addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; + addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize(); #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR @@ -344,7 +326,7 @@ void board_init_f(ulong bootflag) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* reserve TLB table */ - gd->arch.tlb_size = 4096 * 4; + gd->arch.tlb_size = PGTABLE_SIZE; addr -= gd->arch.tlb_size; /* round down to next 64 kB limit */ @@ -419,6 +401,7 @@ void board_init_f(ulong bootflag) } #endif +#ifndef CONFIG_ARM64 /* setup stackpointer for exeptions */ gd->irq_sp = addr_sp; #ifdef CONFIG_USE_IRQ @@ -431,6 +414,10 @@ void board_init_f(ulong bootflag) /* 8-byte alignment for ABI compliance */ addr_sp &= ~0x07; +#else /* CONFIG_ARM64 */ + /* 16-byte alignment for ABI compliance */ + addr_sp &= ~0x0f; +#endif /* CONFIG_ARM64 */ #else addr_sp += 128; /* leave 32 words for abort-stack */ gd->irq_sp = addr_sp; @@ -443,15 +430,13 @@ void board_init_f(ulong bootflag) post_run(NULL, POST_ROM | post_bootmode_get(0)); #endif - gd->bd->bi_baudrate = gd->baudrate; /* Ram ist board specific, so move it to board code ... */ dram_init_banksize(); display_dram_config(); /* and display it */ gd->relocaddr = addr; gd->start_addr_sp = addr_sp; - gd->reloc_off = addr - _TEXT_BASE; - + gd->reloc_off = addr - (ulong)&_start; debug("relocation Offset is: %08lx\n", gd->reloc_off); if (new_fdt) { memcpy(new_fdt, gd->fdt_blob, fdt_size); @@ -516,7 +501,7 @@ void board_init_r(gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); - monitor_flash_len = _end_ofs; + monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start; /* Enable caches */ enable_caches(); @@ -593,6 +578,11 @@ void board_init_r(gd_t *id, ulong dest_addr) mmc_initialize(gd->bd); #endif +#ifdef CONFIG_CMD_SCSI + puts("SCSI: "); + scsi_init(); +#endif + #ifdef CONFIG_HAS_DATAFLASH AT91F_DataflashInit(); dataflash_print_info(); diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index e40691d15f..d4f1578e9e 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -17,13 +17,14 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; -int arch_fixup_memory_node(void *blob) +int arch_fixup_fdt(void *blob) { bd_t *bd = gd->bd; - int bank; + int bank, ret; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -32,5 +33,12 @@ int arch_fixup_memory_node(void *blob) size[bank] = bd->bi_dram[bank].size; } - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) + if (ret) + return ret; + + ret = armv7_update_dt(blob); +#endif + return ret; } diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index eefb456efb..0c1298a31e 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -20,7 +20,14 @@ #include #include #include +#include #include +#include +#include + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -67,8 +74,7 @@ static void announce_and_cleanup(int fake) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); #ifdef CONFIG_BOOTSTAGE_FDT - if (flag == BOOTM_STATE_OS_FAKE_GO) - bootstage_fdt_add_report(); + bootstage_fdt_add_report(); #endif #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); @@ -181,6 +187,18 @@ static void setup_end_tag(bd_t *bd) __weak void setup_board_tags(struct tag **in_params) {} +#ifdef CONFIG_ARM64 +static void do_nonsec_virt_switch(void) +{ + smp_kick_all_cpus(); + flush_dcache_all(); /* flush cache before swtiching to EL2 */ + armv8_switch_to_el2(); +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + armv8_switch_to_el1(); +#endif +} +#endif + /* Subcommand: PREP */ static void boot_prep_linux(bootm_headers_t *images) { @@ -219,9 +237,48 @@ static void boot_prep_linux(bootm_headers_t *images) } } +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +bool armv7_boot_nonsec(void) +{ + char *s = getenv("bootm_boot_mode"); +#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT + bool nonsec = false; +#else + bool nonsec = true; +#endif + + if (s && !strcmp(s, "sec")) + nonsec = false; + + if (s && !strcmp(s, "nonsec")) + nonsec = true; + + return nonsec; +} +#endif + /* Subcommand: GO */ static void boot_jump_linux(bootm_headers_t *images, int flag) { +#ifdef CONFIG_ARM64 + void (*kernel_entry)(void *fdt_addr, void *res0, void *res1, + void *res2); + int fake = (flag & BOOTM_STATE_OS_FAKE_GO); + + kernel_entry = (void (*)(void *fdt_addr, void *res0, void *res1, + void *res2))images->ep; + + debug("## Transferring control to Linux (at address %lx)...\n", + (ulong) kernel_entry); + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + announce_and_cleanup(fake); + + if (!fake) { + do_nonsec_virt_switch(); + kernel_entry(images->ft_addr, NULL, NULL, NULL); + } +#else unsigned long machid = gd->bd->bi_arch_number; char *s; void (*kernel_entry)(int zero, int arch, uint params); @@ -246,8 +303,17 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) else r2 = gd->bd->bi_boot_params; - if (!fake) - kernel_entry(0, machid, r2); + if (!fake) { +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) + if (armv7_boot_nonsec()) { + armv7_init_nonsec(); + secure_ram_addr(_do_nonsec_entry)(kernel_entry, + 0, machid, r2); + } else +#endif + kernel_entry(0, machid, r2); + } +#endif } /* Main Entry point for arm bootm implementation @@ -256,7 +322,8 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) * DIFFERENCE: Instead of calling prep and go at the end * they are called if subcommand is equal 0. */ -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +int do_bootm_linux(int flag, int argc, char * const argv[], + bootm_headers_t *images) { /* No need for those on ARM */ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) @@ -308,3 +375,26 @@ int bootz_setup(ulong image, ulong *start, ulong *end) } #endif /* CONFIG_CMD_BOOTZ */ + +#if defined(CONFIG_BOOTM_VXWORKS) +void boot_prep_vxworks(bootm_headers_t *images) +{ +#if defined(CONFIG_OF_LIBFDT) + int off; + + if (images->ft_addr) { + off = fdt_path_offset(images->ft_addr, "/memory"); + if (off < 0) { + if (arch_fixup_fdt(images->ft_addr)) + puts("## WARNING: fixup memory failed!\n"); + } + } +#endif + cleanup_before_linux(); +} +void boot_jump_vxworks(bootm_headers_t *images) +{ + /* ARM VxWorks requires device tree physical address to be passed */ + ((void (*)(void *))images->ep)(images->ft_addr); +} +#endif diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f283248dfa..751abe4e3c 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -14,11 +14,9 @@ DECLARE_GLOBAL_DATA_PTR; -void __arm_init_before_mmu(void) +__weak void arm_init_before_mmu(void) { } -void arm_init_before_mmu(void) - __attribute__((weak, alias("__arm_init_before_mmu"))); __weak void arm_init_domains(void) { @@ -34,23 +32,20 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } -void __mmu_page_table_flush(unsigned long start, unsigned long stop) +__weak void mmu_page_table_flush(unsigned long start, unsigned long stop) { debug("%s: Warning: not implemented\n", __func__); } -void mmu_page_table_flush(unsigned long start, unsigned long stop) - __attribute__((weak, alias("__mmu_page_table_flush"))); - -void mmu_set_region_dcache_behaviour(u32 start, int size, +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { u32 *page_table = (u32 *)gd->arch.tlb_addr; - u32 upto, end; + unsigned long upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; start = start >> MMU_SECTION_SHIFT; - debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size, + debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option); @@ -64,10 +59,12 @@ __weak void dram_bank_mmu_setup(int bank) debug("%s: bank: %d\n", __func__, bank); for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; + i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20); i++) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) set_section_dcache(i, DCACHE_WRITETHROUGH); +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + set_section_dcache(i, DCACHE_WRITEALLOC); #else set_section_dcache(i, DCACHE_WRITEBACK); #endif diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 8105e25110..20c708a7c3 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -8,15 +8,24 @@ /* for now: just dummy functions to satisfy the linker */ #include +#include -void __flush_cache(unsigned long start, unsigned long size) +__weak void flush_cache(unsigned long start, unsigned long size) { -#if defined(CONFIG_ARM1136) - void arm1136_cache_flush(void); +#if defined(CONFIG_CPU_ARM1136) - arm1136_cache_flush(); +#if !defined(CONFIG_SYS_ICACHE_OFF) + asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ #endif -#ifdef CONFIG_ARM926EJS + +#if !defined(CONFIG_SYS_DCACHE_OFF) + asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ +#endif + +#endif /* CONFIG_CPU_ARM1136 */ + +#ifdef CONFIG_CPU_ARM926EJS +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) asm( /* test and clean, page 2-23 of arm926ejs manual */ "0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" @@ -24,30 +33,67 @@ void __flush_cache(unsigned long start, unsigned long size) "mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory" ); #endif +#endif /* CONFIG_CPU_ARM926EJS */ return; } -void flush_cache(unsigned long start, unsigned long size) - __attribute__((weak, alias("__flush_cache"))); /* * Default implementation: * do a range flush for the entire range */ -void __flush_dcache_all(void) +__weak void flush_dcache_all(void) { flush_cache(0, ~0); } -void flush_dcache_all(void) - __attribute__((weak, alias("__flush_dcache_all"))); - /* * Default implementation of enable_caches() * Real implementation should be in platform code */ -void __enable_caches(void) +__weak void enable_caches(void) { puts("WARNING: Caches not enabled\n"); } -void enable_caches(void) - __attribute__((weak, alias("__enable_caches"))); + +#ifdef CONFIG_SYS_NONCACHED_MEMORY +/* + * Reserve one MMU section worth of address space below the malloc() area that + * will be mapped uncached. + */ +static unsigned long noncached_start; +static unsigned long noncached_end; +static unsigned long noncached_next; + +void noncached_init(void) +{ + phys_addr_t start, end; + size_t size; + + end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; + size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); + start = end - size; + + debug("mapping memory %pa-%pa non-cached\n", &start, &end); + + noncached_start = start; + noncached_end = end; + noncached_next = start; + +#ifndef CONFIG_SYS_DCACHE_OFF + mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); +#endif +} + +phys_addr_t noncached_alloc(size_t size, size_t align) +{ + phys_addr_t next = ALIGN(noncached_next, align); + + if (next >= noncached_end || (noncached_end - next) < size) + return 0; + + debug("allocated %zu bytes of uncached memory @%pa\n", size, &next); + noncached_next = next + size; + + return next; +} +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 7cfc52d6c2..8a774512b6 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,10 +67,22 @@ ENTRY(_main) ldr sp, =CONFIG_SYS_INIT_SP_ADDR #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - sub sp, #GD_SIZE /* allocate one GD above SP */ + mov r2, sp + sub sp, sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - mov r8, sp /* GD is above SP */ + mov r9, sp /* GD is above SP */ + mov r1, sp mov r0, #0 +clr_gd: + cmp r1, r2 /* while not at end of GD */ + strlo r0, [r1] /* clear 32-bit GD word */ + addlo r1, r1, #4 /* move to next */ + blo clr_gd +#if defined(CONFIG_SYS_MALLOC_F_LEN) + sub sp, sp, #CONFIG_SYS_MALLOC_F_LEN + str sp, [r9, #GD_MALLOC_BASE] +#endif + /* mov r0, #0 not needed due to above code */ bl board_init_f #if ! defined(CONFIG_SPL_BUILD) @@ -81,17 +93,22 @@ ENTRY(_main) * 'here' but relocated. */ - ldr sp, [r8, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ + ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r8, [r8, #GD_BD] /* r8 = gd->bd */ - sub r8, r8, #GD_SIZE /* new GD is below bd */ + ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ + sub r9, r9, #GD_SIZE /* new GD is below bd */ adr lr, here - ldr r0, [r8, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ + ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ add lr, lr, r0 - ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ b relocate_code here: +/* + * now relocate vectors + */ + + bl relocate_vectors /* Set up final (full) environment */ @@ -111,8 +128,8 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ bl red_led_on /* call board_init_r(gd_t *id, ulong dest_addr) */ - mov r0, r8 /* gd_t */ - ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */ + mov r0, r9 /* gd_t */ + ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */ /* call board_init_r */ ldr pc, =board_init_r /* this is auto-relocated! */ diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S new file mode 100644 index 0000000000..77563967e5 --- /dev/null +++ b/arch/arm/lib/crt0_64.S @@ -0,0 +1,113 @@ +/* + * crt0 - C-runtime startup Code for AArch64 U-Boot + * + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2012 + * Albert ARIBAUD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * This file handles the target-independent stages of the U-Boot + * start-up where a C runtime environment is needed. Its entry point + * is _main and is branched into from the target's start.S file. + * + * _main execution sequence is: + * + * 1. Set up initial environment for calling board_init_f(). + * This environment only provides a stack and a place to store + * the GD ('global data') structure, both located in some readily + * available RAM (SRAM, locked cache...). In this context, VARIABLE + * global data, initialized or not (BSS), are UNAVAILABLE; only + * CONSTANT initialized data are available. + * + * 2. Call board_init_f(). This function prepares the hardware for + * execution from system RAM (DRAM, DDR...) As system RAM may not + * be available yet, , board_init_f() must use the current GD to + * store any data which must be passed on to later stages. These + * data include the relocation destination, the future stack, and + * the future GD location. + * + * (the following applies only to non-SPL builds) + * + * 3. Set up intermediate environment where the stack and GD are the + * ones allocated by board_init_f() in system RAM, but BSS and + * initialized non-const data are still not available. + * + * 4. Call relocate_code(). This function relocates U-Boot from its + * current location into the relocation destination computed by + * board_init_f(). + * + * 5. Set up final environment for calling board_init_r(). This + * environment has BSS (initialized to 0), initialized non-const + * data (initialized to their intended value), and stack in system + * RAM. GD has retained values set by board_init_f(). Some CPUs + * have some work left to do at this point regarding memory, so + * call c_runtime_cpu_setup. + * + * 6. Branch to board_init_r(). + */ + +ENTRY(_main) + +/* + * Set up initial C runtime environment and call board_init_f(0). + */ + ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) + sub x0, x0, #GD_SIZE /* allocate one GD above SP */ + bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ + mov x18, sp /* GD is above SP */ + mov x0, #0 + bl board_init_f + +/* + * Set up intermediate environment (new sp and gd) and call + * relocate_code(addr_moni). Trick here is that we'll return + * 'here' but relocated. + */ + ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */ + bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ + ldr x18, [x18, #GD_BD] /* x18 <- gd->bd */ + sub x18, x18, #GD_SIZE /* new GD is below bd */ + + adr lr, relocation_return + ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ + add lr, lr, x9 /* new return address after relocation */ + ldr x0, [x18, #GD_RELOCADDR] /* x0 <- gd->relocaddr */ + b relocate_code + +relocation_return: + +/* + * Set up final (full) environment + */ + bl c_runtime_cpu_setup /* still call old routine */ + +/* + * Clear BSS section + */ + ldr x0, =__bss_start /* this is auto-relocated! */ + ldr x1, =__bss_end /* this is auto-relocated! */ + mov x2, #0 +clear_loop: + str x2, [x0] + add x0, x0, #8 + cmp x0, x1 + b.lo clear_loop + + /* call board_init_r(gd_t *id, ulong dest_addr) */ + mov x0, x18 /* gd_t */ + ldr x1, [x18, #GD_RELOCADDR] /* dest_addr */ + b board_init_r /* PC relative jump */ + + /* NOTREACHED - board_init_r() does not return */ + +ENDPROC(_main) diff --git a/arch/arm/lib/debug.S b/arch/arm/lib/debug.S new file mode 100644 index 0000000000..760ba74a3c --- /dev/null +++ b/arch/arm/lib/debug.S @@ -0,0 +1,136 @@ +/* + * linux/arch/arm/kernel/debug.S + * + * Copyright (C) 1994-1999 Russell King + * + * SPDX-License-Identifier: GPL-2.0+ + * + * 32-bit debugging code + */ +#include +#include + + .text + +/* + * Some debugging routines (useful if you've got MM problems and + * printk isn't working). For DEBUGGING ONLY!!! Do not leave + * references to these in a production kernel! + */ + +#if !defined(CONFIG_DEBUG_SEMIHOSTING) +#include CONFIG_DEBUG_LL_INCLUDE +#endif + +#ifdef CONFIG_MMU + .macro addruart_current, rx, tmp1, tmp2 + addruart \tmp1, \tmp2, \rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + moveq \rx, \tmp1 + movne \rx, \tmp2 + .endm + +#else /* !CONFIG_MMU */ + .macro addruart_current, rx, tmp1, tmp2 + addruart \rx, \tmp1, \tmp2 + .endm + +#endif /* CONFIG_MMU */ + +/* + * Useful debugging routines + */ +ENTRY(printhex8) + mov r1, #8 + b printhex +ENDPROC(printhex8) + +ENTRY(printhex4) + mov r1, #4 + b printhex +ENDPROC(printhex4) + +ENTRY(printhex2) + mov r1, #2 +printhex: adr r2, hexbuf + add r3, r2, r1 + mov r1, #0 + strb r1, [r3] +1: and r1, r0, #15 + mov r0, r0, lsr #4 + cmp r1, #10 + addlt r1, r1, #'0' + addge r1, r1, #'a' - 10 + strb r1, [r3, #-1]! + teq r3, r2 + bne 1b + mov r0, r2 + b printascii +ENDPROC(printhex2) + +hexbuf: .space 16 + + .ltorg + +#ifndef CONFIG_DEBUG_SEMIHOSTING + +ENTRY(printascii) + addruart_current r3, r1, r2 + b 2f +1: waituart r2, r3 + senduart r1, r3 + busyuart r2, r3 + teq r1, #'\n' + moveq r1, #'\r' + beq 1b +2: teq r0, #0 + ldrneb r1, [r0], #1 + teqne r1, #0 + bne 1b + mov pc, lr +ENDPROC(printascii) + +ENTRY(printch) + addruart_current r3, r1, r2 + mov r1, r0 + mov r0, #0 + b 1b +ENDPROC(printch) + +#ifdef CONFIG_MMU +ENTRY(debug_ll_addr) + addruart r2, r3, ip + str r2, [r0] + str r3, [r1] + mov pc, lr +ENDPROC(debug_ll_addr) +#endif + +#else + +ENTRY(printascii) + mov r1, r0 + mov r0, #0x04 @ SYS_WRITE0 + ARM( svc #0x123456 ) + THUMB( svc #0xab ) + mov pc, lr +ENDPROC(printascii) + +ENTRY(printch) + adr r1, hexbuf + strb r0, [r1] + mov r0, #0x03 @ SYS_WRITEC + ARM( svc #0x123456 ) + THUMB( svc #0xab ) + mov pc, lr +ENDPROC(printch) + +ENTRY(debug_ll_addr) + mov r2, #0 + str r2, [r0] + str r2, [r1] + mov pc, lr +ENDPROC(debug_ll_addr) + +#endif diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index 10d19333fc..a2cb06e49a 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -20,8 +20,19 @@ int raise (int signum) /* Dummy function to avoid linker complaints */ void __aeabi_unwind_cpp_pr0(void) { -}; +} void __aeabi_unwind_cpp_pr1(void) { -}; +} + +/* Copy memory like memcpy, but no return value required. */ +void __aeabi_memcpy(void *dest, const void *src, size_t n) +{ + (void) memcpy(dest, src, n); +} + +void __aeabi_memset(void *dest, size_t n, int c) +{ + (void) memset(dest, c, n); +} diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S new file mode 100644 index 0000000000..a3e18f7713 --- /dev/null +++ b/arch/arm/lib/gic_64.S @@ -0,0 +1,190 @@ +/* + * GIC Initialization Routines. + * + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + + +/************************************************************************* + * + * void gic_init_secure(DistributorBase); + * + * Initialize secure copy of GIC at EL3. + * + *************************************************************************/ +ENTRY(gic_init_secure) + /* + * Initialize Distributor + * x0: Distributor Base + */ +#if defined(CONFIG_GICV3) + mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */ + /* EnableGrp1S | ARE_S | ARE_NS */ + str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ + ldr w9, [x0, GICD_TYPER] + and w10, w9, #0x1f /* ITLinesNumber */ + cbz w10, 1f /* No SPIs */ + add x11, x0, (GICD_IGROUPRn + 4) + add x12, x0, (GICD_IGROUPMODRn + 4) + mov w9, #~0 +0: str w9, [x11], #0x4 + str wzr, [x12], #0x4 /* Config SPIs as Group1NS */ + sub w10, w10, #0x1 + cbnz w10, 0b +#elif defined(CONFIG_GICV2) + mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */ + str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ + ldr w9, [x0, GICD_TYPER] + and w10, w9, #0x1f /* ITLinesNumber */ + cbz w10, 1f /* No SPIs */ + add x11, x0, (GICD_IGROUPRn + 4) + mov w9, #~0 /* Config SPIs as Grp1 */ +0: str w9, [x11], #0x4 + sub w10, w10, #0x1 + cbnz w10, 0b +#endif +1: + ret +ENDPROC(gic_init_secure) + + +/************************************************************************* + * For Gicv2: + * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase); + * For Gicv3: + * void gic_init_secure_percpu(ReDistributorBase); + * + * Initialize secure copy of GIC at EL3. + * + *************************************************************************/ +ENTRY(gic_init_secure_percpu) +#if defined(CONFIG_GICV3) + /* + * Initialize ReDistributor + * x0: ReDistributor Base + */ + mrs x10, mpidr_el1 + lsr x9, x10, #32 + bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */ + mov x9, x0 +1: ldr x11, [x9, GICR_TYPER] + lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */ + cmp w10, w11 + b.eq 2f + add x9, x9, #(2 << 16) + b 1b + + /* x9: ReDistributor Base Address of Current CPU */ +2: mov w10, #~0x2 + ldr w11, [x9, GICR_WAKER] + and w11, w11, w10 /* Clear ProcessorSleep */ + str w11, [x9, GICR_WAKER] + dsb st + isb +3: ldr w10, [x9, GICR_WAKER] + tbnz w10, #2, 3b /* Wait Children be Alive */ + + add x10, x9, #(1 << 16) /* SGI_Base */ + mov w11, #~0 + str w11, [x10, GICR_IGROUPRn] + str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */ + mov w11, #0x1 /* Enable SGI 0 */ + str w11, [x10, GICR_ISENABLERn] + + /* Initialize Cpu Interface */ + mrs x10, ICC_SRE_EL3 + orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ + /* Allow EL2 access to ICC_SRE_EL2 */ + msr ICC_SRE_EL3, x10 + isb + + mrs x10, ICC_SRE_EL2 + orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ + /* Allow EL1 access to ICC_SRE_EL1 */ + msr ICC_SRE_EL2, x10 + isb + + mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */ + msr ICC_IGRPEN1_EL3, x10 + isb + + msr ICC_CTLR_EL3, xzr + isb + + msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */ + isb + + mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */ + msr ICC_PMR_EL1, x10 + isb +#elif defined(CONFIG_GICV2) + /* + * Initialize SGIs and PPIs + * x0: Distributor Base + * x1: Cpu Interface Base + */ + mov w9, #~0 /* Config SGIs and PPIs as Grp1 */ + str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */ + mov w9, #0x1 /* Enable SGI 0 */ + str w9, [x0, GICD_ISENABLERn] + + /* Initialize Cpu Interface */ + mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */ + /* Enable Ack Group1 Interrupt & */ + /* EnableGrp0 & EnableGrp1 */ + str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */ + + mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */ + str w9, [x1, GICC_PMR] +#endif + ret +ENDPROC(gic_init_secure_percpu) + + +/************************************************************************* + * For Gicv2: + * void gic_kick_secondary_cpus(DistributorBase); + * For Gicv3: + * void gic_kick_secondary_cpus(void); + * + *************************************************************************/ +ENTRY(gic_kick_secondary_cpus) +#if defined(CONFIG_GICV3) + mov x9, #(1 << 40) + msr ICC_ASGI1R_EL1, x9 + isb +#elif defined(CONFIG_GICV2) + mov w9, #0x8000 + movk w9, #0x100, lsl #16 + str w9, [x0, GICD_SGIR] +#endif + ret +ENDPROC(gic_kick_secondary_cpus) + + +/************************************************************************* + * For Gicv2: + * void gic_wait_for_interrupt(CpuInterfaceBase); + * For Gicv3: + * void gic_wait_for_interrupt(void); + * + * Wait for SGI 0 from master. + * + *************************************************************************/ +ENTRY(gic_wait_for_interrupt) +#if defined(CONFIG_GICV3) + gic_wait_for_interrupt_m x9 +#elif defined(CONFIG_GICV2) + gic_wait_for_interrupt_m x0, w9 +#endif + ret +ENDPROC(gic_wait_for_interrupt) diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index e0aef1b48e..3d6e5a3498 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -16,17 +16,20 @@ * (C) Copyright 2004 * Philippe Robin, ARM Ltd. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include -#include +#include +#include DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USE_IRQ int interrupt_init (void) { + unsigned long cpsr; + /* * setup up stacks if necessary */ @@ -34,6 +37,31 @@ int interrupt_init (void) IRQ_STACK_START_IN = gd->irq_sp + 8; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; + + __asm__ __volatile__("mrs %0, cpsr\n" + : "=r" (cpsr) + : + : "memory"); + + __asm__ __volatile__("msr cpsr_c, %0\n" + "mov sp, %1\n" + : + : "r" (IRQ_MODE | I_BIT | F_BIT | (cpsr & ~FIQ_MODE)), + "r" (IRQ_STACK_START) + : "memory"); + + __asm__ __volatile__("msr cpsr_c, %0\n" + "mov sp, %1\n" + : + : "r" (FIQ_MODE | I_BIT | F_BIT | (cpsr & ~IRQ_MODE)), + "r" (FIQ_STACK_START) + : "memory"); + + __asm__ __volatile__("msr cpsr_c, %0" + : + : "r" (cpsr) + : "memory"); + return arch_interrupt_init(); } @@ -103,7 +131,7 @@ void show_regs (struct pt_regs *regs) "UK12_26", "UK13_26", "UK14_26", "UK15_26", "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK8_32", "UK9_32", "HYP_32", "UND_32", "UK12_32", "UK13_32", "UK14_32", "SYS_32", }; @@ -171,14 +199,7 @@ void do_prefetch_abort (struct pt_regs *pt_regs) void do_data_abort (struct pt_regs *pt_regs) { - unsigned long fsr; - - /* Read Fault Status Register */ - asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r"(fsr)); - - printf ("data abort\n\n"); - if (fsr & 1) - printf ("MAYBE you should read doc/README.arm-unaligned-accesses\n\n"); + printf ("data abort\n"); fixup_pc(pt_regs, -8); show_regs (pt_regs); bad_mode (); diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c new file mode 100644 index 0000000000..b476722556 --- /dev/null +++ b/arch/arm/lib/interrupts_64.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + + +int interrupt_init(void) +{ + return 0; +} + +void enable_interrupts(void) +{ + return; +} + +int disable_interrupts(void) +{ + return 0; +} + +void show_regs(struct pt_regs *regs) +{ + int i; + + printf("ELR: %lx\n", regs->elr); + printf("LR: %lx\n", regs->regs[30]); + for (i = 0; i < 29; i += 2) + printf("x%-2d: %016lx x%-2d: %016lx\n", + i, regs->regs[i], i+1, regs->regs[i+1]); + printf("\n"); +} + +/* + * do_bad_sync handles the impossible case in the Synchronous Abort vector. + */ +void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_bad_irq handles the impossible case in the Irq vector. + */ +void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_bad_fiq handles the impossible case in the Fiq vector. + */ +void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_bad_error handles the impossible case in the Error vector. + */ +void do_bad_error(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_sync handles the Synchronous Abort exception. + */ +void do_sync(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_irq handles the Irq exception. + */ +void do_irq(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("\"Irq\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_fiq handles the Fiq exception. + */ +void do_fiq(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("\"Fiq\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_error handles the Error exception. + * Errors are more likely to be processor specific, + * it is defined with weak attribute and can be redefined + * in processor specific code. + */ +void __weak do_error(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("\"Error\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index f655256b5d..eeaf003529 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -10,9 +10,14 @@ * published by the Free Software Foundation. */ +#include #include +#ifdef CONFIG_SYS_THUMB_BUILD +#define W(instr) instr.w +#else #define W(instr) instr +#endif #define LDR1W_SHIFT 0 #define STR1W_SHIFT 0 @@ -30,7 +35,7 @@ .endm .macro ldr1b ptr reg cond=al abort - ldr\cond\()b \reg, [\ptr], #1 + ldrb\cond\() \reg, [\ptr], #1 .endm .macro str1w ptr reg abort @@ -42,7 +47,7 @@ .endm .macro str1b ptr reg cond=al abort - str\cond\()b \reg, [\ptr], #1 + strb\cond\() \reg, [\ptr], #1 .endm .macro enter reg1 reg2 @@ -56,10 +61,12 @@ .text /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ - -.globl memcpy -memcpy: - + .syntax unified +#ifdef CONFIG_SYS_THUMB_BUILD + .thumb + .thumb_func +#endif +ENTRY(memcpy) cmp r0, r1 moveq pc, lr @@ -79,7 +86,7 @@ memcpy: CALGN( ands ip, r0, #31 ) CALGN( rsb r3, ip, #32 ) - CALGN( sbcnes r4, r3, r2 ) @ C is always set here + CALGN( sbcsne r4, r3, r2 ) @ C is always set here CALGN( bcs 2f ) CALGN( adr r4, 6f ) CALGN( subs r2, r2, r3 ) @ C gets set @@ -178,7 +185,7 @@ memcpy: CALGN( ands ip, r0, #31 ) CALGN( rsb ip, ip, #32 ) - CALGN( sbcnes r4, ip, r2 ) @ C is always set here + CALGN( sbcsne r4, ip, r2 ) @ C is always set here CALGN( subcc r2, r2, ip ) CALGN( bcc 15f ) @@ -193,24 +200,24 @@ memcpy: 12: PLD( pld [r1, #124] ) 13: ldr4w r1, r4, r5, r6, r7, abort=19f - mov r3, lr, pull #\pull + mov r3, lr, lspull #\pull subs r2, r2, #32 ldr4w r1, r8, r9, ip, lr, abort=19f - orr r3, r3, r4, push #\push - mov r4, r4, pull #\pull - orr r4, r4, r5, push #\push - mov r5, r5, pull #\pull - orr r5, r5, r6, push #\push - mov r6, r6, pull #\pull - orr r6, r6, r7, push #\push - mov r7, r7, pull #\pull - orr r7, r7, r8, push #\push - mov r8, r8, pull #\pull - orr r8, r8, r9, push #\push - mov r9, r9, pull #\pull - orr r9, r9, ip, push #\push - mov ip, ip, pull #\pull - orr ip, ip, lr, push #\push + orr r3, r3, r4, lspush #\push + mov r4, r4, lspull #\pull + orr r4, r4, r5, lspush #\push + mov r5, r5, lspull #\pull + orr r5, r5, r6, lspush #\push + mov r6, r6, lspull #\pull + orr r6, r6, r7, lspush #\push + mov r7, r7, lspull #\pull + orr r7, r7, r8, lspush #\push + mov r8, r8, lspull #\pull + orr r8, r8, r9, lspush #\push + mov r9, r9, lspull #\pull + orr r9, r9, ip, lspush #\push + mov ip, ip, lspull #\pull + orr ip, ip, lr, lspush #\push str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f bge 12b PLD( cmn r2, #96 ) @@ -221,10 +228,10 @@ memcpy: 14: ands ip, r2, #28 beq 16f -15: mov r3, lr, pull #\pull +15: mov r3, lr, lspull #\pull ldr1w r1, lr, abort=21f subs ip, ip, #4 - orr r3, r3, lr, push #\push + orr r3, r3, lr, lspush #\push str1w r0, r3, abort=21f bgt 15b CALGN( cmp r2, #0 ) @@ -241,3 +248,24 @@ memcpy: 17: forward_copy_shift pull=16 push=16 18: forward_copy_shift pull=24 push=8 + + +/* + * Abort preamble and completion macros. + * If a fixup handler is required then those macros must surround it. + * It is assumed that the fixup code will handle the private part of + * the exit macro. + */ + + .macro copy_abort_preamble +19: ldmfd sp!, {r5 - r9} + b 21f +20: ldmfd sp!, {r5 - r8} +21: + .endm + + .macro copy_abort_end + ldmfd sp!, {r4, pc} + .endm + +ENDPROC(memcpy) diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 0cdf89535a..7208f20dda 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -9,32 +9,25 @@ * * ASM optimised string functions */ +#include #include .text .align 5 - .word 0 -1: subs r2, r2, #4 @ 1 do we have enough - blt 5f @ 1 bytes to align with? - cmp r3, #2 @ 1 - strltb r1, [r0], #1 @ 1 - strleb r1, [r0], #1 @ 1 - strb r1, [r0], #1 @ 1 - add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) -/* - * The pointer is now aligned and the length is adjusted. Try doing the - * memset again. - */ - -.globl memset -memset: + .syntax unified +#ifdef CONFIG_SYS_THUMB_BUILD + .thumb + .thumb_func +#endif +ENTRY(memset) ands r3, r0, #3 @ 1 unaligned? - bne 1b @ 1 + mov ip, r0 @ preserve r0 as return value + bne 6f @ 1 /* - * we know that the pointer in r0 is aligned to a word boundary. + * we know that the pointer in ip is aligned to a word boundary. */ - orr r1, r1, r1, lsl #8 +1: orr r1, r1, r1, lsl #8 orr r1, r1, r1, lsl #16 mov r3, r1 cmp r2, #16 @@ -43,29 +36,28 @@ memset: #if ! CALGN(1)+0 /* - * We need an extra register for this loop - save the return address and - * use the LR + * We need 2 extra registers for this loop - use r8 and the LR */ - str lr, [sp, #-4]! - mov ip, r1 + stmfd sp!, {r8, lr} + mov r8, r1 mov lr, r1 2: subs r2, r2, #64 - stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time. - stmgeia r0!, {r1, r3, ip, lr} - stmgeia r0!, {r1, r3, ip, lr} - stmgeia r0!, {r1, r3, ip, lr} + stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time. + stmiage ip!, {r1, r3, r8, lr} + stmiage ip!, {r1, r3, r8, lr} + stmiage ip!, {r1, r3, r8, lr} bgt 2b - ldmeqfd sp!, {pc} @ Now <64 bytes to go. + ldmfdeq sp!, {r8, pc} @ Now <64 bytes to go. /* * No need to correct the count; we're only testing bits from now on */ tst r2, #32 - stmneia r0!, {r1, r3, ip, lr} - stmneia r0!, {r1, r3, ip, lr} + stmiane ip!, {r1, r3, r8, lr} + stmiane ip!, {r1, r3, r8, lr} tst r2, #16 - stmneia r0!, {r1, r3, ip, lr} - ldr lr, [sp], #4 + stmiane ip!, {r1, r3, r8, lr} + ldmfd sp!, {r8, lr} #else @@ -74,53 +66,63 @@ memset: * whole cache lines at once. */ - stmfd sp!, {r4-r7, lr} + stmfd sp!, {r4-r8, lr} mov r4, r1 mov r5, r1 mov r6, r1 mov r7, r1 - mov ip, r1 + mov r8, r1 mov lr, r1 cmp r2, #96 - tstgt r0, #31 + tstgt ip, #31 ble 3f - and ip, r0, #31 - rsb ip, ip, #32 - sub r2, r2, ip - movs ip, ip, lsl #(32 - 4) - stmcsia r0!, {r4, r5, r6, r7} - stmmiia r0!, {r4, r5} - tst ip, #(1 << 30) - mov ip, r1 - strne r1, [r0], #4 + and r8, ip, #31 + rsb r8, r8, #32 + sub r2, r2, r8 + movs r8, r8, lsl #(32 - 4) + stmiacs ip!, {r4, r5, r6, r7} + stmiami ip!, {r4, r5} + tst r8, #(1 << 30) + mov r8, r1 + strne r1, [ip], #4 3: subs r2, r2, #64 - stmgeia r0!, {r1, r3-r7, ip, lr} - stmgeia r0!, {r1, r3-r7, ip, lr} + stmiage ip!, {r1, r3-r8, lr} + stmiage ip!, {r1, r3-r8, lr} bgt 3b - ldmeqfd sp!, {r4-r7, pc} + ldmfdeq sp!, {r4-r8, pc} tst r2, #32 - stmneia r0!, {r1, r3-r7, ip, lr} + stmiane ip!, {r1, r3-r8, lr} tst r2, #16 - stmneia r0!, {r4-r7} - ldmfd sp!, {r4-r7, lr} + stmiane ip!, {r4-r7} + ldmfd sp!, {r4-r8, lr} #endif 4: tst r2, #8 - stmneia r0!, {r1, r3} + stmiane ip!, {r1, r3} tst r2, #4 - strne r1, [r0], #4 + strne r1, [ip], #4 /* * When we get here, we've got less than 4 bytes to zero. We * may have an unaligned pointer as well. */ 5: tst r2, #2 - strneb r1, [r0], #1 - strneb r1, [r0], #1 + strbne r1, [ip], #1 + strbne r1, [ip], #1 tst r2, #1 - strneb r1, [r0], #1 - mov pc, lr + strbne r1, [ip], #1 + ret lr + +6: subs r2, r2, #4 @ 1 do we have enough + blt 5b @ 1 bytes to align with? + cmp r3, #2 @ 1 + strblt r1, [ip], #1 @ 1 + strble r1, [ip], #1 @ 1 + strb r1, [ip], #1 @ 1 + add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) + b 1b +ENDPROC(memset) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 90d612fd64..92f531452d 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -6,8 +6,51 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include +#include #include +/* + * Default/weak exception vectors relocation routine + * + * This routine covers the standard ARM cases: normal (0x00000000), + * high (0xffff0000) and VBAR. SoCs which do not comply with any of + * the standard cases must provide their own, strong, version. + */ + + .section .text.relocate_vectors,"ax",%progbits + .weak relocate_vectors + +ENTRY(relocate_vectors) + +#ifdef CONFIG_HAS_VBAR + /* + * If the ARM processor has the security extensions, + * use VBAR to relocate the exception vectors. + */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ +#else + /* + * Copy the relocated exception vectors to the + * correct address + * CP15 c1 V bit gives us the location of the vectors: + * 0x00000000 or 0xFFFF0000. + */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */ + ands r2, r2, #(1 << 13) + ldreq r1, =0x00000000 /* If V=0 */ + ldrne r1, =0xFFFF0000 /* If V=1 */ + ldmia r0!, {r2-r8,r10} + stmia r1!, {r2-r8,r10} + ldmia r0!, {r2-r8,r10} + stmia r1!, {r2-r8,r10} +#endif + bx lr + +ENDPROC(relocate_vectors) + /* * void relocate_code(addr_moni) * @@ -21,8 +64,8 @@ */ ENTRY(relocate_code) - ldr r1, =_start /* r1 <- SRC &__image_copy_start */ - subs r9, r0, r1 /* r9 <- relocation offset */ + ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */ + subs r4, r0, r1 /* r4 <- relocation offset */ beq relocate_done /* skip relocation */ ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */ @@ -44,9 +87,9 @@ fixloop: bne fixnext /* relative fix: increase location by offset */ - add r0, r0, r9 + add r0, r0, r4 ldr r1, [r0] - add r1, r1, r9 + add r1, r1, r4 str r1, [r0] fixnext: cmp r2, r3 @@ -66,9 +109,9 @@ relocate_done: /* ARMv4- don't know bx lr but the assembler fails to see that */ #ifdef __ARM_ARCH_4__ - mov pc, lr + mov pc, lr #else - bx lr + bx lr #endif ENDPROC(relocate_code) diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S new file mode 100644 index 0000000000..5c51cae8ab --- /dev/null +++ b/arch/arm/lib/relocate_64.S @@ -0,0 +1,77 @@ +/* + * relocate - common relocation function for AArch64 U-Boot + * + * (C) Copyright 2013 + * Albert ARIBAUD + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * void relocate_code (addr_moni) + * + * This function relocates the monitor code. + * x0 holds the destination address. + */ +ENTRY(relocate_code) + stp x29, x30, [sp, #-32]! /* create a stack frame */ + mov x29, sp + str x0, [sp, #16] + /* + * Copy u-boot from flash to RAM + */ + ldr x1, =__image_copy_start /* x1 <- SRC &__image_copy_start */ + subs x9, x0, x1 /* x9 <- relocation offset */ + b.eq relocate_done /* skip relocation */ + ldr x2, =__image_copy_end /* x2 <- SRC &__image_copy_end */ + +copy_loop: + ldp x10, x11, [x1], #16 /* copy from source address [x1] */ + stp x10, x11, [x0], #16 /* copy to target address [x0] */ + cmp x1, x2 /* until source end address [x2] */ + b.lo copy_loop + str x0, [sp, #24] + + /* + * Fix .rela.dyn relocations + */ + ldr x2, =__rel_dyn_start /* x2 <- SRC &__rel_dyn_start */ + ldr x3, =__rel_dyn_end /* x3 <- SRC &__rel_dyn_end */ +fixloop: + ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */ + ldr x4, [x2], #8 /* x4 <- addend */ + and x1, x1, #0xffffffff + cmp x1, #1027 /* relative fixup? */ + bne fixnext + + /* relative fix: store addend plus offset at dest location */ + add x0, x0, x9 + add x4, x4, x9 + str x4, [x0] +fixnext: + cmp x2, x3 + b.lo fixloop + +relocate_done: + switch_el x1, 3f, 2f, 1f + bl hang +3: mrs x0, sctlr_el3 + b 0f +2: mrs x0, sctlr_el2 + b 0f +1: mrs x0, sctlr_el1 +0: tbz w0, #2, 5f /* skip flushing cache if disabled */ + tbz w0, #12, 4f /* invalide i-cache is enabled */ + ic iallu /* i-cache invalidate all */ + isb sy +4: ldp x0, x1, [sp, #16] + bl __asm_flush_dcache_range +5: ldp x29, x30, [sp],#16 + ret +ENDPROC(relocate_code) diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 3b057e3a3d..18d3e7eeff 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -23,6 +23,10 @@ #include +__weak void reset_misc(void) +{ +} + int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { puts ("resetting ...\n"); @@ -30,6 +34,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) udelay (50000); /* wait 50 ms */ disable_interrupts(); + + reset_misc(); reset_cpu(0); hang(); } diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index e35687c09c..a1205c370d 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -25,3 +25,6 @@ char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); +char __secure_start[0] __attribute__((section(".__secure_start"))); +char __secure_end[0] __attribute__((section(".__secure_end"))); +char _end[0] __attribute__((section(".__end"))); diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c new file mode 100644 index 0000000000..fd6d8573f5 --- /dev/null +++ b/arch/arm/lib/semihosting.c @@ -0,0 +1,236 @@ +/* + * Copyright 2014 Broadcom Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Minimal semihosting implementation for reading files into memory. If more + * features like writing files or console output are required they can be + * added later. This code has been tested on arm64/aarch64 fastmodel only. + * An untested placeholder exists for armv7 architectures, but since they + * are commonly available in silicon now, fastmodel usage makes less sense + * for them. + */ +#include +#include + +#define SYSOPEN 0x01 +#define SYSCLOSE 0x02 +#define SYSREAD 0x06 +#define SYSFLEN 0x0C + +#define MODE_READ 0x0 +#define MODE_READBIN 0x1 + +/* + * Call the handler + */ +static long smh_trap(unsigned int sysnum, void *addr) +{ + register long result asm("r0"); +#if defined(CONFIG_ARM64) + asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); +#else + /* Note - untested placeholder */ + asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr)); +#endif + return result; +} + +/* + * Open a file on the host. Mode is "r" or "rb" currently. Returns a file + * descriptor or -1 on error. + */ +static long smh_open(const char *fname, char *modestr) +{ + long fd; + unsigned long mode; + struct smh_open_s { + const char *fname; + unsigned long mode; + size_t len; + } open; + + debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr); + + /* Check the file mode */ + if (!(strcmp(modestr, "r"))) { + mode = MODE_READ; + } else if (!(strcmp(modestr, "rb"))) { + mode = MODE_READBIN; + } else { + printf("%s: ERROR mode \'%s\' not supported\n", __func__, + modestr); + return -1; + } + + open.fname = fname; + open.len = strlen(fname); + open.mode = mode; + + /* Open the file on the host */ + fd = smh_trap(SYSOPEN, &open); + if (fd == -1) + printf("%s: ERROR fd %ld for file \'%s\'\n", __func__, fd, + fname); + + return fd; +} + +/* + * Read 'len' bytes of file into 'memp'. Returns 0 on success, else failure + */ +static long smh_read(long fd, void *memp, size_t len) +{ + long ret; + struct smh_read_s { + long fd; + void *memp; + size_t len; + } read; + + debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len); + + read.fd = fd; + read.memp = memp; + read.len = len; + + ret = smh_trap(SYSREAD, &read); + if (ret < 0) { + /* + * The ARM handler allows for returning partial lengths, + * but in practice this never happens so rather than create + * hard to maintain partial read loops and such, just fail + * with an error message. + */ + printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n", + __func__, ret, fd, len, memp); + return -1; + } + + return 0; +} + +/* + * Close the file using the file descriptor + */ +static long smh_close(long fd) +{ + long ret; + + debug("%s: fd %ld\n", __func__, fd); + + ret = smh_trap(SYSCLOSE, &fd); + if (ret == -1) + printf("%s: ERROR fd %ld\n", __func__, fd); + + return ret; +} + +/* + * Get the file length from the file descriptor + */ +static long smh_len_fd(long fd) +{ + long ret; + + debug("%s: fd %ld\n", __func__, fd); + + ret = smh_trap(SYSFLEN, &fd); + if (ret == -1) + printf("%s: ERROR ret %ld, fd %ld\n", __func__, ret, fd); + + return ret; +} + +/* + * Open, load a file into memory, and close it. Check that the available space + * is sufficient to store the entire file. Return the bytes actually read from + * the file as seen by the read function. The verbose flag enables some extra + * printing of successful read status. + */ +int smh_load(const char *fname, void *memp, int avail, int verbose) +{ + long ret; + long fd; + size_t len; + + ret = -1; + + debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname, + avail, memp); + + /* Open the file */ + fd = smh_open(fname, "rb"); + if (fd == -1) + return -1; + + /* Get the file length */ + ret = smh_len_fd(fd); + if (ret == -1) { + smh_close(fd); + return -1; + } + + /* Check that the file will fit in the supplied buffer */ + if (ret > avail) { + printf("%s: ERROR ret %ld, avail %u\n", __func__, ret, + avail); + smh_close(fd); + return -1; + } + + len = ret; + + /* Read the file into the buffer */ + ret = smh_read(fd, memp, len); + if (ret == 0) { + /* Print successful load information if requested */ + if (verbose) { + printf("\n%s\n", fname); + printf(" 0x%8p dest\n", memp); + printf(" 0x%08lx size\n", len); + printf(" 0x%08x avail\n", avail); + } + } + + /* Close the file */ + smh_close(fd); + + return ret; +} + +/* + * Get the file length from the filename + */ +long smh_len(const char *fname) +{ + long ret; + long fd; + long len; + + debug("%s: file \'%s\'\n", __func__, fname); + + /* Open the file */ + fd = smh_open(fname, "rb"); + if (fd < 0) + return fd; + + /* Get the file length */ + len = smh_len_fd(fd); + if (len < 0) { + smh_close(fd); + return len; + } + + /* Close the file */ + ret = smh_close(fd); + if (ret < 0) + return ret; + + debug("%s: returning len %ld\n", __func__, len); + + /* Return the file length (or -1 error indication) */ + return len; +} diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 583bdb3ac2..c41850aaee 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -15,6 +15,11 @@ /* Pointer to as well as the global data structure for SPL */ DECLARE_GLOBAL_DATA_PTR; + +/* + * WARNING: This is going away very soon. Don't use it and don't submit + * pafches that rely on it. The global_data area is set up in crt0.S. + */ gd_t gdata __attribute__ ((section(".data"))); /* @@ -25,13 +30,10 @@ gd_t gdata __attribute__ ((section(".data"))); */ void __weak board_init_f(ulong dummy) { - /* Set the stack pointer. */ - asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); - /* Set global data pointer. */ + /* TODO: Remove settings of the global data pointer here */ gd = &gdata; board_init_r(NULL, 0); @@ -45,12 +47,17 @@ void __weak board_init_f(ulong dummy) #ifdef CONFIG_SPL_OS_BOOT void __noreturn jump_to_image_linux(void *arg) { + unsigned long machid = 0xffffffff; +#ifdef CONFIG_MACH_TYPE + machid = CONFIG_MACH_TYPE; +#endif + debug("Entering kernel arg pointer: 0x%p\n", arg); typedef void (*image_entry_arg_t)(int, int, void *) __attribute__ ((noreturn)); image_entry_arg_t image_entry = (image_entry_arg_t) spl_image.entry_point; cleanup_before_linux(); - image_entry(0, CONFIG_MACH_TYPE, arg); + image_entry(0, machid, arg); } #endif diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S new file mode 100644 index 0000000000..2ac7ffe473 --- /dev/null +++ b/arch/arm/lib/vectors.S @@ -0,0 +1,295 @@ +/* + * vectors - Generic ARM exception table code + * + * Copyright (c) 1998 Dan Malek + * Copyright (c) 1999 Magnus Damm + * Copyright (c) 2000 Wolfgang Denk + * Copyright (c) 2001 Alex Züpke + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2002 Kyle Harris + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* + ************************************************************************* + * + * Symbol _start is referenced elsewhere, so make it global + * + ************************************************************************* + */ + +.globl _start + +/* + ************************************************************************* + * + * Vectors have their own section so linker script can map them easily + * + ************************************************************************* + */ + + .section ".vectors", "ax" + +/* + ************************************************************************* + * + * Exception vectors as described in ARM reference manuals + * + * Uses indirect branch to allow reaching handlers anywhere in memory. + * + ************************************************************************* + */ + +_start: + +#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG + .word CONFIG_SYS_DV_NOR_BOOT_CFG +#endif + + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +/* + ************************************************************************* + * + * Indirect vectors table + * + * Symbols referenced here must be defined somewhere else + * + ************************************************************************* + */ + + .globl _undefined_instruction + .globl _software_interrupt + .globl _prefetch_abort + .globl _data_abort + .globl _not_used + .globl _irq + .globl _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +/* SPL interrupt handling: just hang */ + +#ifdef CONFIG_SPL_BUILD + + .align 5 +undefined_instruction: +software_interrupt: +prefetch_abort: +data_abort: +not_used: +irq: +fiq: + +1: + bl 1b /* hang and never return */ + +#else /* !CONFIG_SPL_BUILD */ + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: +#ifndef CONFIG_SPL_STACK + .word 0x0badc0de +#else + .word CONFIG_SPL_STACK +#endif + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de + +#endif /* CONFIG_USE_IRQ */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + ldr r2, IRQ_STACK_START_IN + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif /* CONFIG_USE_IRQ */ + +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile new file mode 100644 index 0000000000..9dcab6958c --- /dev/null +++ b/arch/arm/mvebu-common/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = dram.o +obj-y += gpio.o +obj-$(CONFIG_ARMADA_XP) += mbus.o +obj-y += timer.o diff --git a/arch/arm/mvebu-common/dram.c b/arch/arm/mvebu-common/dram.c new file mode 100644 index 0000000000..db18791a86 --- /dev/null +++ b/arch/arm/mvebu-common/dram.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct sdram_bank { + u32 win_bar; + u32 win_sz; +}; + +struct sdram_addr_dec { + struct sdram_bank sdram_bank[4]; +}; + +#define REG_CPUCS_WIN_ENABLE (1 << 0) +#define REG_CPUCS_WIN_WR_PROTECT (1 << 1) +#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) +#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) + +/* + * mvebu_sdram_bar - reads SDRAM Base Address Register + */ +u32 mvebu_sdram_bar(enum memory_bank bank) +{ + struct sdram_addr_dec *base = + (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; + u32 result = 0; + u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); + + if ((!enable) || (bank > BANK3)) + return 0; + + result = readl(&base->sdram_bank[bank].win_bar); + return result; +} + +/* + * mvebu_sdram_bs_set - writes SDRAM Bank size + */ +static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size) +{ + struct sdram_addr_dec *base = + (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; + /* Read current register value */ + u32 reg = readl(&base->sdram_bank[bank].win_sz); + + /* Clear window size */ + reg &= ~REG_CPUCS_WIN_SIZE(0xFF); + + /* Set new window size */ + reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24); + + writel(reg, &base->sdram_bank[bank].win_sz); +} + +/* + * mvebu_sdram_bs - reads SDRAM Bank size + */ +u32 mvebu_sdram_bs(enum memory_bank bank) +{ + struct sdram_addr_dec *base = + (struct sdram_addr_dec *)MVEBU_SDRAM_BASE; + u32 result = 0; + u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); + + if ((!enable) || (bank > BANK3)) + return 0; + result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz); + result += 0x01000000; + return result; +} + +void mvebu_sdram_size_adjust(enum memory_bank bank) +{ + u32 size; + + /* probe currently equipped RAM size */ + size = get_ram_size((void *)mvebu_sdram_bar(bank), + mvebu_sdram_bs(bank)); + + /* adjust SDRAM window size accordingly */ + mvebu_sdram_bs_set(bank, size); +} + +#ifndef CONFIG_SYS_BOARD_DRAM_INIT +int dram_init(void) +{ + int i; + + gd->ram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = mvebu_sdram_bar(i); + gd->bd->bi_dram[i].size = mvebu_sdram_bs(i); + /* + * It is assumed that all memory banks are consecutive + * and without gaps. + * If the gap is found, ram_size will be reported for + * consecutive memory only + */ + if (gd->bd->bi_dram[i].start != gd->ram_size) + break; + + /* + * Don't report more than 3GiB of SDRAM, otherwise there is no + * address space left for the internal registers etc. + */ + if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) && + (gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30))) + gd->ram_size += gd->bd->bi_dram[i].size; + + } + + for (; i < CONFIG_NR_DRAM_BANKS; i++) { + /* If above loop terminated prematurely, we need to set + * remaining banks' start address & size as 0. Otherwise other + * u-boot functions and Linux kernel gets wrong values which + * could result in crash */ + gd->bd->bi_dram[i].start = 0; + gd->bd->bi_dram[i].size = 0; + } + + return 0; +} + +/* + * If this function is not defined here, + * board.c alters dram bank zero configuration defined above. + */ +void dram_init_banksize(void) +{ + dram_init(); +} +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/mvebu-common/gpio.c b/arch/arm/mvebu-common/gpio.c new file mode 100644 index 0000000000..56e54e0a62 --- /dev/null +++ b/arch/arm/mvebu-common/gpio.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * mvebu_config_gpio - GPIO configuration + */ +void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, + u32 gpp0_oe, u32 gpp1_oe) +{ + struct kwgpio_registers *gpio0reg = + (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + struct kwgpio_registers *gpio1reg = + (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + + /* Init GPIOS to default values as per board requirement */ + writel(gpp0_oe_val, &gpio0reg->dout); + writel(gpp1_oe_val, &gpio1reg->dout); + writel(gpp0_oe, &gpio0reg->oe); + writel(gpp1_oe, &gpio1reg->oe); +} diff --git a/arch/arm/mvebu-common/mbus.c b/arch/arm/mvebu-common/mbus.c new file mode 100644 index 0000000000..05c9ef2cbb --- /dev/null +++ b/arch/arm/mvebu-common/mbus.c @@ -0,0 +1,471 @@ +/* + * Address map functions for Marvell EBU SoCs (Kirkwood, Armada + * 370/XP, Dove, Orion5x and MV78xx0) + * + * Ported from the Barebox version to U-Boot by: + * Stefan Roese + * + * The Barebox version is: + * Sebastian Hesselbarth + * + * based on mbus driver from Linux + * (C) Copyright 2008 Marvell Semiconductor + * + * SPDX-License-Identifier: GPL-2.0 + * + * The Marvell EBU SoCs have a configurable physical address space: + * the physical address at which certain devices (PCIe, NOR, NAND, + * etc.) sit can be configured. The configuration takes place through + * two sets of registers: + * + * - One to configure the access of the CPU to the devices. Depending + * on the families, there are between 8 and 20 configurable windows, + * each can be use to create a physical memory window that maps to a + * specific device. Devices are identified by a tuple (target, + * attribute). + * + * - One to configure the access to the CPU to the SDRAM. There are + * either 2 (for Dove) or 4 (for other families) windows to map the + * SDRAM into the physical address space. + * + * This driver: + * + * - Reads out the SDRAM address decoding windows at initialization + * time, and fills the mbus_dram_info structure with these + * informations. The exported function mv_mbus_dram_info() allow + * device drivers to get those informations related to the SDRAM + * address decoding windows. This is because devices also have their + * own windows (configured through registers that are part of each + * device register space), and therefore the drivers for Marvell + * devices have to configure those device -> SDRAM windows to ensure + * that DMA works properly. + * + * - Provides an API for platform code or device drivers to + * dynamically add or remove address decoding windows for the CPU -> + * device accesses. This API is mvebu_mbus_add_window_by_id(), + * mvebu_mbus_add_window_remap_by_id() and + * mvebu_mbus_del_window(). + */ + +#include +#include +#include +#include +#include +#include + +#define BIT(nr) (1UL << (nr)) + +/* DDR target is the same on all platforms */ +#define TARGET_DDR 0 + +/* CPU Address Decode Windows registers */ +#define WIN_CTRL_OFF 0x0000 +#define WIN_CTRL_ENABLE BIT(0) +#define WIN_CTRL_TGT_MASK 0xf0 +#define WIN_CTRL_TGT_SHIFT 4 +#define WIN_CTRL_ATTR_MASK 0xff00 +#define WIN_CTRL_ATTR_SHIFT 8 +#define WIN_CTRL_SIZE_MASK 0xffff0000 +#define WIN_CTRL_SIZE_SHIFT 16 +#define WIN_BASE_OFF 0x0004 +#define WIN_BASE_LOW 0xffff0000 +#define WIN_BASE_HIGH 0xf +#define WIN_REMAP_LO_OFF 0x0008 +#define WIN_REMAP_LOW 0xffff0000 +#define WIN_REMAP_HI_OFF 0x000c + +#define ATTR_HW_COHERENCY (0x1 << 4) + +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_BASE_CS_HIGH_MASK 0xf +#define DDR_BASE_CS_LOW_MASK 0xff000000 +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) +#define DDR_SIZE_ENABLED BIT(0) +#define DDR_SIZE_CS_MASK 0x1c +#define DDR_SIZE_CS_SHIFT 2 +#define DDR_SIZE_MASK 0xff000000 + +#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4) + +struct mvebu_mbus_state; + +struct mvebu_mbus_soc_data { + unsigned int num_wins; + unsigned int num_remappable_wins; + unsigned int (*win_cfg_offset)(const int win); + void (*setup_cpu_target)(struct mvebu_mbus_state *s); +}; + +struct mvebu_mbus_state mbus_state + __attribute__ ((section(".data"))); +static struct mbus_dram_target_info mbus_dram_info + __attribute__ ((section(".data"))); + +/* + * Functions to manipulate the address decoding windows + */ + +static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus, + int win, int *enabled, u64 *base, + u32 *size, u8 *target, u8 *attr, + u64 *remap) +{ + void __iomem *addr = mbus->mbuswins_base + + mbus->soc->win_cfg_offset(win); + u32 basereg = readl(addr + WIN_BASE_OFF); + u32 ctrlreg = readl(addr + WIN_CTRL_OFF); + + if (!(ctrlreg & WIN_CTRL_ENABLE)) { + *enabled = 0; + return; + } + + *enabled = 1; + *base = ((u64)basereg & WIN_BASE_HIGH) << 32; + *base |= (basereg & WIN_BASE_LOW); + *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1; + + if (target) + *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT; + + if (attr) + *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT; + + if (remap) { + if (win < mbus->soc->num_remappable_wins) { + u32 remap_low = readl(addr + WIN_REMAP_LO_OFF); + u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF); + *remap = ((u64)remap_hi << 32) | remap_low; + } else { + *remap = 0; + } + } +} + +static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus, + int win) +{ + void __iomem *addr; + + addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); + + writel(0, addr + WIN_BASE_OFF); + writel(0, addr + WIN_CTRL_OFF); + if (win < mbus->soc->num_remappable_wins) { + writel(0, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } +} + +/* Checks whether the given window number is available */ +static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus, + const int win) +{ + void __iomem *addr = mbus->mbuswins_base + + mbus->soc->win_cfg_offset(win); + u32 ctrl = readl(addr + WIN_CTRL_OFF); + return !(ctrl & WIN_CTRL_ENABLE); +} + +/* + * Checks whether the given (base, base+size) area doesn't overlap an + * existing region + */ +static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, + phys_addr_t base, size_t size, + u8 target, u8 attr) +{ + u64 end = (u64)base + size; + int win; + + for (win = 0; win < mbus->soc->num_wins; win++) { + u64 wbase, wend; + u32 wsize; + u8 wtarget, wattr; + int enabled; + + mvebu_mbus_read_window(mbus, win, + &enabled, &wbase, &wsize, + &wtarget, &wattr, NULL); + + if (!enabled) + continue; + + wend = wbase + wsize; + + /* + * Check if the current window overlaps with the + * proposed physical range + */ + if ((u64)base < wend && end > wbase) + return 0; + + /* + * Check if target/attribute conflicts + */ + if (target == wtarget && attr == wattr) + return 0; + } + + return 1; +} + +static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus, + phys_addr_t base, size_t size) +{ + int win; + + for (win = 0; win < mbus->soc->num_wins; win++) { + u64 wbase; + u32 wsize; + int enabled; + + mvebu_mbus_read_window(mbus, win, + &enabled, &wbase, &wsize, + NULL, NULL, NULL); + + if (!enabled) + continue; + + if (base == wbase && size == wsize) + return win; + } + + return -ENODEV; +} + +static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, + int win, phys_addr_t base, size_t size, + phys_addr_t remap, u8 target, + u8 attr) +{ + void __iomem *addr = mbus->mbuswins_base + + mbus->soc->win_cfg_offset(win); + u32 ctrl, remap_addr; + + ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | + (attr << WIN_CTRL_ATTR_SHIFT) | + (target << WIN_CTRL_TGT_SHIFT) | + WIN_CTRL_ENABLE; + + writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF); + writel(ctrl, addr + WIN_CTRL_OFF); + if (win < mbus->soc->num_remappable_wins) { + if (remap == MVEBU_MBUS_NO_REMAP) + remap_addr = base; + else + remap_addr = remap; + writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } + + return 0; +} + +static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus, + phys_addr_t base, size_t size, + phys_addr_t remap, u8 target, + u8 attr) +{ + int win; + + if (remap == MVEBU_MBUS_NO_REMAP) { + for (win = mbus->soc->num_remappable_wins; + win < mbus->soc->num_wins; win++) + if (mvebu_mbus_window_is_free(mbus, win)) + return mvebu_mbus_setup_window(mbus, win, base, + size, remap, + target, attr); + } + + + for (win = 0; win < mbus->soc->num_wins; win++) + if (mvebu_mbus_window_is_free(mbus, win)) + return mvebu_mbus_setup_window(mbus, win, base, size, + remap, target, attr); + + return -ENOMEM; +} + +/* + * SoC-specific functions and definitions + */ + +static unsigned int armada_370_xp_mbus_win_offset(int win) +{ + /* The register layout is a bit annoying and the below code + * tries to cope with it. + * - At offset 0x0, there are the registers for the first 8 + * windows, with 4 registers of 32 bits per window (ctrl, + * base, remap low, remap high) + * - Then at offset 0x80, there is a hole of 0x10 bytes for + * the internal registers base address and internal units + * sync barrier register. + * - Then at offset 0x90, there the registers for 12 + * windows, with only 2 registers of 32 bits per window + * (ctrl, base). + */ + if (win < 8) + return win << 4; + else + return 0x90 + ((win - 8) << 3); +} + +static unsigned int orion5x_mbus_win_offset(int win) +{ + return win << 4; +} + +static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) +{ + int i; + int cs; + + mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); + u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); + + /* + * We only take care of entries for which the chip + * select is enabled, and that don't have high base + * address bits set (devices can only access the first + * 32 bits of the memory). + */ + if ((size & DDR_SIZE_ENABLED) && + !(base & DDR_BASE_CS_HIGH_MASK)) { + struct mbus_dram_window *w; + + w = &mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); +#if defined(CONFIG_ARMADA_XP) + w->mbus_attr |= ATTR_HW_COHERENCY; +#endif + w->base = base & DDR_BASE_CS_LOW_MASK; + w->size = (size | ~DDR_SIZE_MASK) + 1; + } + } + mbus_dram_info.num_cs = cs; +} + +static const struct mvebu_mbus_soc_data +armada_370_xp_mbus_data __maybe_unused = { + .num_wins = 20, + .num_remappable_wins = 8, + .win_cfg_offset = armada_370_xp_mbus_win_offset, + .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, +}; + +static const struct mvebu_mbus_soc_data +kirkwood_mbus_data __maybe_unused = { + .num_wins = 8, + .num_remappable_wins = 4, + .win_cfg_offset = orion5x_mbus_win_offset, + .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, +}; + +/* + * Public API of the driver + */ +const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) +{ + return &mbus_dram_info; +} + +int mvebu_mbus_add_window_remap_by_id(unsigned int target, + unsigned int attribute, + phys_addr_t base, size_t size, + phys_addr_t remap) +{ + struct mvebu_mbus_state *s = &mbus_state; + + if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) { + printf("Cannot add window '%x:%x', conflicts with another window\n", + target, attribute); + return -EINVAL; + } + + return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute); +} + +int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, + phys_addr_t base, size_t size) +{ + return mvebu_mbus_add_window_remap_by_id(target, attribute, base, + size, MVEBU_MBUS_NO_REMAP); +} + +int mvebu_mbus_del_window(phys_addr_t base, size_t size) +{ + int win; + + win = mvebu_mbus_find_window(&mbus_state, base, size); + if (win < 0) + return win; + + mvebu_mbus_disable_window(&mbus_state, win); + return 0; +} + +int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, + u32 base, u32 size, u8 target, u8 attr) +{ + if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) { + printf("Cannot add window '%04x:%04x', conflicts with another window\n", + target, attr); + return -EBUSY; + } + + /* + * In U-Boot we first try to add the mbus window to the remap windows. + * If this fails, lets try to add the windows to the non-remap windows. + */ + if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) { + if (mvebu_mbus_alloc_window(mbus, base, size, + MVEBU_MBUS_NO_REMAP, target, attr)) + return -ENOMEM; + } + + return 0; +} + +int mvebu_mbus_probe(struct mbus_win windows[], int count) +{ + int win; + int ret; + int i; + +#if defined(CONFIG_KIRKWOOD) + mbus_state.soc = &kirkwood_mbus_data; +#endif +#if defined(CONFIG_ARMADA_XP) + mbus_state.soc = &armada_370_xp_mbus_data; +#endif + + mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE; + mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE; + + for (win = 0; win < mbus_state.soc->num_wins; win++) + mvebu_mbus_disable_window(&mbus_state, win); + + mbus_state.soc->setup_cpu_target(&mbus_state); + + /* Setup statically declared windows in the DT */ + for (i = 0; i < count; i++) { + u32 base, size; + u8 target, attr; + + target = windows[i].target; + attr = windows[i].attr; + base = windows[i].base; + size = windows[i].size; + ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr); + if (ret < 0) + return ret; + } + + return 0; +} diff --git a/arch/arm/mvebu-common/timer.c b/arch/arm/mvebu-common/timer.c new file mode 100644 index 0000000000..40c4bc2da1 --- /dev/null +++ b/arch/arm/mvebu-common/timer.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) Marvell International Ltd. and its affiliates + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */ + +/* + * ARM Timers Registers Map + */ +#define CNTMR_CTRL_REG &tmr_regs->ctrl +#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload +#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val + +/* + * ARM Timers Control Register + * CPU_TIMERS_CTRL_REG (CTCR) + */ +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + +/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */ +#if defined(CONFIG_ARMADA_XP) +#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11) +#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr)) +#else +#define CTCR_ARM_TIMER_25MHZ(cntr) 0 +#endif + +#define TIMER_LOAD_VAL 0xffffffff + +#define timestamp gd->arch.tbl +#define lastdec gd->arch.lastinc + +/* Timer reload and current value registers */ +struct kwtmr_val { + u32 reload; /* Timer reload reg */ + u32 val; /* Timer value reg */ +}; + +/* Timer registers */ +struct kwtmr_registers { + u32 ctrl; /* Timer control reg */ + u32 pad[3]; + struct kwtmr_val tmr[4]; + u32 wdt_reload; + u32 wdt_val; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static struct kwtmr_registers *tmr_regs = + (struct kwtmr_registers *)MVEBU_TIMER_BASE; + +static inline ulong read_timer(void) +{ + return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000); +} + +ulong get_timer_masked(void) +{ + ulong now = read_timer(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + + (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + } + lastdec = now; + + return timestamp; +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void __udelay(unsigned long usec) +{ + uint current; + ulong delayticks; + + current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); + delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + + if (current < delayticks) { + delayticks -= current; + while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; + while ((TIMER_LOAD_VAL - delayticks) < + readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; + } else { + while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > + (current - delayticks)) ; + } +} + +/* + * init the counter + */ +int timer_init(void) +{ + /* load value into timer */ + writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + + /* enable timer in auto reload mode */ + clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR), + CTCR_ARM_TIMER_EN(UBOOT_CNTR) | + CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR)); + + /* init the timestamp and lastdec value */ + lastdec = read_timer(); + timestamp = 0; + + return 0; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + return (ulong)CONFIG_SYS_HZ; +} diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig new file mode 100644 index 0000000000..66de2ad7ef --- /dev/null +++ b/arch/avr32/Kconfig @@ -0,0 +1,50 @@ +menu "AVR32 architecture" + depends on AVR32 + +config SYS_ARCH + default "avr32" + +choice + prompt "Target select" + +config TARGET_ATNGW100 + bool "Support atngw100" + +config TARGET_ATNGW100MKII + bool "Support atngw100mkii" + +config TARGET_ATSTK1002 + bool "Support atstk1002" + +config TARGET_ATSTK1003 + bool "Support atstk1003" + +config TARGET_ATSTK1004 + bool "Support atstk1004" + +config TARGET_ATSTK1006 + bool "Support atstk1006" + +config TARGET_FAVR_32_EZKIT + bool "Support favr-32-ezkit" + +config TARGET_GRASSHOPPER + bool "Support grasshopper" + +config TARGET_MIMC200 + bool "Support mimc200" + +config TARGET_HAMMERHEAD + bool "Support hammerhead" + +endchoice + +source "board/atmel/atngw100/Kconfig" +source "board/atmel/atngw100mkii/Kconfig" +source "board/atmel/atstk1000/Kconfig" +source "board/earthlcd/favr-32-ezkit/Kconfig" +source "board/in-circuit/grasshopper/Kconfig" +source "board/mimc/mimc200/Kconfig" +source "board/miromico/hammerhead/Kconfig" + +endmenu diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile new file mode 100644 index 0000000000..e9b3184379 --- /dev/null +++ b/arch/avr32/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/avr32/cpu/start.o + +libs-y += arch/avr32/cpu/ +libs-y += arch/avr32/lib/ diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 4ab4745edf..469185e8b4 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= avr32-linux- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := avr32-linux- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 diff --git a/arch/avr32/cpu/Makefile b/arch/avr32/cpu/Makefile index 7e648fd7f5..00cede3fd9 100644 --- a/arch/avr32/cpu/Makefile +++ b/arch/avr32/cpu/Makefile @@ -7,34 +7,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y += start.o -LIB := $(obj)lib$(CPU).o +obj-y += cpu.o +obj-$(CONFIG_SYS_HSDRAMC) += hsdramc.o +obj-y += exception.o +obj-y += cache.o +obj-y += interrupts.o +obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o +obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o -START-y += start.o - -COBJS-y += cpu.o -COBJS-$(CONFIG_SYS_HSDRAMC) += hsdramc.o -COBJS-y += exception.o -COBJS-y += cache.o -COBJS-y += interrupts.o -COBJS-$(CONFIG_PORTMUX_PIO) += portmux-pio.o -COBJS-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o - -SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(START-y)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/ diff --git a/arch/avr32/cpu/at32ap700x/Makefile b/arch/avr32/cpu/at32ap700x/Makefile index 8be8c1d05e..06f18963e2 100644 --- a/arch/avr32/cpu/at32ap700x/Makefile +++ b/arch/avr32/cpu/at32ap700x/Makefile @@ -4,24 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(SOC).o - -COBJS := portmux.o clk.o mmu.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := portmux.o clk.o mmu.o diff --git a/arch/avr32/cpu/at32ap700x/clk.c b/arch/avr32/cpu/at32ap700x/clk.c index d5dbe3b908..0fc6088e3e 100644 --- a/arch/avr32/cpu/at32ap700x/clk.c +++ b/arch/avr32/cpu/at32ap700x/clk.c @@ -72,7 +72,7 @@ unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN)); rate = parent_rate; } else { - divider = min(255, divider / 2 - 1); + divider = min(255UL, divider / 2 - 1); sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN) | SM_BF(DIV, divider)); rate = parent_rate / (2 * (divider + 1)); diff --git a/arch/avr32/cpu/cache.c b/arch/avr32/cpu/cache.c index ab0374e587..b3ffc3348b 100644 --- a/arch/avr32/cpu/cache.c +++ b/arch/avr32/cpu/cache.c @@ -24,31 +24,31 @@ void dcache_clean_range(volatile void *start, size_t size) sync_write_buffer(); } -void dcache_invalidate_range(volatile void *start, size_t size) +void invalidate_dcache_range(unsigned long start, unsigned long stop) { - unsigned long v, begin, end, linesz; + unsigned long v, linesz; linesz = CONFIG_SYS_DCACHE_LINESZ; /* You asked for it, you got it */ - begin = (unsigned long)start & ~(linesz - 1); - end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + start = start & ~(linesz - 1); + stop = (stop + linesz - 1) & ~(linesz - 1); - for (v = begin; v < end; v += linesz) + for (v = start; v < stop; v += linesz) dcache_invalidate_line((void *)v); } -void dcache_flush_range(volatile void *start, size_t size) +void flush_dcache_range(unsigned long start, unsigned long stop) { - unsigned long v, begin, end, linesz; + unsigned long v, linesz; linesz = CONFIG_SYS_DCACHE_LINESZ; /* You asked for it, you got it */ - begin = (unsigned long)start & ~(linesz - 1); - end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + start = start & ~(linesz - 1); + stop = (stop + linesz - 1) & ~(linesz - 1); - for (v = begin; v < end; v += linesz) + for (v = start; v < stop; v += linesz) dcache_flush_line((void *)v); sync_write_buffer(); diff --git a/arch/avr32/cpu/pio2.h b/arch/avr32/cpu/pio2.h deleted file mode 100644 index 9719ea8c43..0000000000 --- a/arch/avr32/cpu/pio2.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Register definitions for Parallel Input/Output Controller - */ -#ifndef __CPU_AT32AP_PIO2_H__ -#define __CPU_AT32AP_PIO2_H__ - -/* PIO2 register offsets */ -#define PIO2_PER 0x0000 -#define PIO2_PDR 0x0004 -#define PIO2_PSR 0x0008 -#define PIO2_OER 0x0010 -#define PIO2_ODR 0x0014 -#define PIO2_OSR 0x0018 -#define PIO2_IFER 0x0020 -#define PIO2_IFDR 0x0024 -#define PIO2_ISFR 0x0028 -#define PIO2_SODR 0x0030 -#define PIO2_CODR 0x0034 -#define PIO2_ODSR 0x0038 -#define PIO2_PDSR 0x003c -#define PIO2_IER 0x0040 -#define PIO2_IDR 0x0044 -#define PIO2_IMR 0x0048 -#define PIO2_ISR 0x004c -#define PIO2_MDER 0x0050 -#define PIO2_MDDR 0x0054 -#define PIO2_MDSR 0x0058 -#define PIO2_PUDR 0x0060 -#define PIO2_PUER 0x0064 -#define PIO2_PUSR 0x0068 -#define PIO2_ASR 0x0070 -#define PIO2_BSR 0x0074 -#define PIO2_ABSR 0x0078 -#define PIO2_OWER 0x00a0 -#define PIO2_OWDR 0x00a4 -#define PIO2_OWSR 0x00a8 - -/* Register access macros */ -#define pio2_readl(base,reg) \ - readl((void *)base + PIO2_##reg) -#define pio2_writel(base,reg,value) \ - writel((value), (void *)base + PIO2_##reg) - -#endif /* __CPU_AT32AP_PIO2_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h b/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h index 13d6d3aed3..e08cd9de6d 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h +++ b/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h @@ -49,9 +49,7 @@ static inline void icache_invalidate_line(volatile void *vaddr) * Applies the above functions on all lines that are touched by the * specified virtual address range. */ -void dcache_invalidate_range(volatile void *start, size_t len); void dcache_clean_range(volatile void *start, size_t len); -void dcache_flush_range(volatile void *start, size_t len); void icache_invalidate_range(volatile void *start, size_t len); static inline void dcache_flush_unlocked(void) diff --git a/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h b/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h deleted file mode 100644 index 8801bd006c..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__ -#define __ASM_AVR32_ARCH_GPIO_IMPL_H__ - -/* Register offsets */ -struct gpio_regs { - u32 GPER; - u32 GPERS; - u32 GPERC; - u32 GPERT; - u32 PMR0; - u32 PMR0S; - u32 PMR0C; - u32 PMR0T; - u32 PMR1; - u32 PMR1S; - u32 PMR1C; - u32 PMR1T; - u32 __reserved0[4]; - u32 ODER; - u32 ODERS; - u32 ODERC; - u32 ODERT; - u32 OVR; - u32 OVRS; - u32 OVRC; - u32 OVRT; - u32 PVR; - u32 __reserved_PVRS; - u32 __reserved_PVRC; - u32 __reserved_PVRT; - u32 PUER; - u32 PUERS; - u32 PUERC; - u32 PUERT; - u32 PDER; - u32 PDERS; - u32 PDERC; - u32 PDERT; - u32 IER; - u32 IERS; - u32 IERC; - u32 IERT; - u32 IMR0; - u32 IMR0S; - u32 IMR0C; - u32 IMR0T; - u32 IMR1; - u32 IMR1S; - u32 IMR1C; - u32 IMR1T; - u32 GFER; - u32 GFERS; - u32 GFERC; - u32 GFERT; - u32 IFR; - u32 __reserved_IFRS; - u32 IFRC; - u32 __reserved_IFRT; - u32 ODMER; - u32 ODMERS; - u32 ODMERC; - u32 ODMERT; - u32 __reserved1[4]; - u32 ODCR0; - u32 ODCR0S; - u32 ODCR0C; - u32 ODCR0T; - u32 ODCR1; - u32 ODCR1S; - u32 ODCR1C; - u32 ODCR1T; - u32 __reserved2[4]; - u32 OSRR0; - u32 OSRR0S; - u32 OSRR0C; - u32 OSRR0T; - u32 __reserved3[8]; - u32 STER; - u32 STERS; - u32 STERC; - u32 STERT; - u32 __reserved4[35]; - u32 VERSION; -}; - -#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */ diff --git a/arch/avr32/include/asm/arch-common/portmux-gpio.h b/arch/avr32/include/asm/arch-common/portmux-gpio.h deleted file mode 100644 index fb01a17fc1..0000000000 --- a/arch/avr32/include/asm/arch-common/portmux-gpio.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __AVR32_PORTMUX_GPIO_H__ -#define __AVR32_PORTMUX_GPIO_H__ - -#include - -/* Register layout for this specific device */ -#include - -/* Register access macros */ -#define gpio_readl(port, reg) \ - __raw_readl(&((struct gpio_regs *)port)->reg) -#define gpio_writel(gpio, reg, value) \ - __raw_writel(value, &((struct gpio_regs *)port)->reg) - -/* Portmux API starts here. See doc/README.AVR32-port-muxing */ - -enum portmux_function { - PORTMUX_FUNC_A, - PORTMUX_FUNC_B, - PORTMUX_FUNC_C, - PORTMUX_FUNC_D, -}; - -#define PORTMUX_DIR_INPUT (0 << 0) -#define PORTMUX_DIR_OUTPUT (1 << 0) -#define PORTMUX_INIT_LOW (0 << 1) -#define PORTMUX_INIT_HIGH (1 << 1) -#define PORTMUX_PULL_UP (1 << 2) -#define PORTMUX_PULL_DOWN (2 << 2) -#define PORTMUX_BUSKEEPER (3 << 2) -#define PORTMUX_DRIVE_MIN (0 << 4) -#define PORTMUX_DRIVE_LOW (1 << 4) -#define PORTMUX_DRIVE_HIGH (2 << 4) -#define PORTMUX_DRIVE_MAX (3 << 4) -#define PORTMUX_OPEN_DRAIN (1 << 6) - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags); -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags); - -/* Internal helper functions */ - -static inline void *gpio_pin_to_port(unsigned int pin) -{ - return (void *)GPIO_BASE + (pin >> 5) * 0x200; -} - -static inline void __gpio_set_output_value(void *port, unsigned int pin, - int value) -{ - if (value) - gpio_writel(port, OVRS, 1 << pin); - else - gpio_writel(port, OVRC, 1 << pin); -} - -static inline int __gpio_get_input_value(void *port, unsigned int pin) -{ - return (gpio_readl(port, PVR) >> pin) & 1; -} - -void gpio_set_output_value(unsigned int pin, int value); -int gpio_get_input_value(unsigned int pin); - -/* GPIO API starts here */ - -/* - * GCC doesn't realize that the constant case is extremely trivial, - * so we need to help it make the right decision by using - * always_inline. - */ -__attribute__((always_inline)) -static inline void gpio_set_value(unsigned int pin, int value) -{ - if (__builtin_constant_p(pin)) - __gpio_set_output_value(gpio_pin_to_port(pin), - pin & 0x1f, value); - else - gpio_set_output_value(pin, value); -} - -__attribute__((always_inline)) -static inline int gpio_get_value(unsigned int pin) -{ - if (__builtin_constant_p(pin)) - return __gpio_get_input_value(gpio_pin_to_port(pin), - pin & 0x1f); - else - return gpio_get_input_value(pin); -} - -#endif /* __AVR32_PORTMUX_GPIO_H__ */ diff --git a/arch/avr32/include/asm/dma-mapping.h b/arch/avr32/include/asm/dma-mapping.h index 95ea81ff5e..dbdd2fee38 100644 --- a/arch/avr32/include/asm/dma-mapping.h +++ b/arch/avr32/include/asm/dma-mapping.h @@ -23,13 +23,15 @@ static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, switch (dir) { case DMA_BIDIRECTIONAL: - dcache_flush_range(vaddr, len); + flush_dcache_range((unsigned long)vaddr, + (unsigned long)vaddr + len); break; case DMA_TO_DEVICE: dcache_clean_range(vaddr, len); break; case DMA_FROM_DEVICE: - dcache_invalidate_range(vaddr, len); + invalidate_dcache_range((unsigned long)vaddr, + (unsigned long)vaddr + len); break; default: /* This will cause a linker error */ diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index bff17d5ed2..6aef808749 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -7,7 +7,6 @@ #define __ASM_U_BOOT_H__ 1 typedef struct bd_info { - unsigned int bi_baudrate; unsigned char bi_phy_id[4]; unsigned long bi_board_number; void *bi_boot_params; diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile index d5245d32f6..bb45cbe153 100644 --- a/arch/avr32/lib/Makefile +++ b/arch/avr32/lib/Makefile @@ -7,27 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).o - -SOBJS-y += memset.o - -COBJS-y += board.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-y += interrupts.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += memset.o +obj-y += board.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-y += interrupts.o diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 28c2ec09ef..bf0997f98d 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -65,8 +65,8 @@ static void dma_alloc_init(void) printf("DMA: Using memory from 0x%08lx to 0x%08lx\n", dma_alloc_start, dma_alloc_end); - dcache_invalidate_range(cached(dma_alloc_start), - dma_alloc_end - dma_alloc_start); + invalidate_dcache_range((unsigned long)cached(dma_alloc_start), + dma_alloc_end); } void *dma_alloc_coherent(size_t len, unsigned long *handle) @@ -220,7 +220,6 @@ void board_init_f(ulong board_type) */ bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; bd->bi_dram[0].size = sdram_size; - bd->bi_baudrate = gd->baudrate; memcpy(new_gd, gd, sizeof(gd_t)); diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig new file mode 100644 index 0000000000..31913fe29f --- /dev/null +++ b/arch/blackfin/Kconfig @@ -0,0 +1,149 @@ +menu "Blackfin architecture" + depends on BLACKFIN + +config SYS_ARCH + default "blackfin" + +choice + prompt "Target select" + +config TARGET_BCT_BRETTL2 + bool "Support bct-brettl2" + +config TARGET_BF506F_EZKIT + bool "Support bf506f-ezkit" + +config TARGET_BF518F_EZBRD + bool "Support bf518f-ezbrd" + +config TARGET_BF525_UCR2 + bool "Support bf525-ucr2" + +config TARGET_BF526_EZBRD + bool "Support bf526-ezbrd" + +config TARGET_BF527_AD7160_EVAL + bool "Support bf527-ad7160-eval" + +config TARGET_BF527_EZKIT + bool "Support bf527-ezkit" + +config TARGET_BF527_SDP + bool "Support bf527-sdp" + +config TARGET_BF533_EZKIT + bool "Support bf533-ezkit" + +config TARGET_BF533_STAMP + bool "Support bf533-stamp" + +config TARGET_BF537_MINOTAUR + bool "Support bf537-minotaur" + +config TARGET_BF537_PNAV + bool "Support bf537-pnav" + +config TARGET_BF537_SRV1 + bool "Support bf537-srv1" + +config TARGET_BF537_STAMP + bool "Support bf537-stamp" + +config TARGET_BF538F_EZKIT + bool "Support bf538f-ezkit" + +config TARGET_BF548_EZKIT + bool "Support bf548-ezkit" + +config TARGET_BF561_ACVILON + bool "Support bf561-acvilon" + +config TARGET_BF561_EZKIT + bool "Support bf561-ezkit" + +config TARGET_BF609_EZKIT + bool "Support bf609-ezkit" + +config TARGET_BLACKSTAMP + bool "Support blackstamp" + +config TARGET_BLACKVME + bool "Support blackvme" + +config TARGET_BR4 + bool "Support br4" + +config TARGET_CM_BF527 + bool "Support cm-bf527" + +config TARGET_CM_BF533 + bool "Support cm-bf533" + +config TARGET_CM_BF537E + bool "Support cm-bf537e" + +config TARGET_CM_BF537U + bool "Support cm-bf537u" + +config TARGET_CM_BF548 + bool "Support cm-bf548" + +config TARGET_CM_BF561 + bool "Support cm-bf561" + +config TARGET_DNP5370 + bool "Support dnp5370" + +config TARGET_IBF_DSP561 + bool "Support ibf-dsp561" + +config TARGET_IP04 + bool "Support ip04" + +config TARGET_PR1 + bool "Support pr1" + +config TARGET_TCM_BF518 + bool "Support tcm-bf518" + +config TARGET_TCM_BF537 + bool "Support tcm-bf537" + +endchoice + +source "board/bct-brettl2/Kconfig" +source "board/bf506f-ezkit/Kconfig" +source "board/bf518f-ezbrd/Kconfig" +source "board/bf525-ucr2/Kconfig" +source "board/bf526-ezbrd/Kconfig" +source "board/bf527-ad7160-eval/Kconfig" +source "board/bf527-ezkit/Kconfig" +source "board/bf527-sdp/Kconfig" +source "board/bf533-ezkit/Kconfig" +source "board/bf533-stamp/Kconfig" +source "board/bf537-minotaur/Kconfig" +source "board/bf537-pnav/Kconfig" +source "board/bf537-srv1/Kconfig" +source "board/bf537-stamp/Kconfig" +source "board/bf538f-ezkit/Kconfig" +source "board/bf548-ezkit/Kconfig" +source "board/bf561-acvilon/Kconfig" +source "board/bf561-ezkit/Kconfig" +source "board/bf609-ezkit/Kconfig" +source "board/blackstamp/Kconfig" +source "board/blackvme/Kconfig" +source "board/br4/Kconfig" +source "board/cm-bf527/Kconfig" +source "board/cm-bf533/Kconfig" +source "board/cm-bf537e/Kconfig" +source "board/cm-bf537u/Kconfig" +source "board/cm-bf548/Kconfig" +source "board/cm-bf561/Kconfig" +source "board/dnp5370/Kconfig" +source "board/ibf-dsp561/Kconfig" +source "board/ip04/Kconfig" +source "board/pr1/Kconfig" +source "board/tcm-bf518/Kconfig" +source "board/tcm-bf537/Kconfig" + +endmenu diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile new file mode 100644 index 0000000000..787475e130 --- /dev/null +++ b/arch/blackfin/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/blackfin/cpu/start.o + +libs-y += arch/blackfin/cpu/ +libs-y += arch/blackfin/lib/ diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 35f871662d..584b38b17a 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -5,21 +5,25 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= bfin-uclinux- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := bfin-uclinux- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin ifeq ($(CONFIG_BFIN_CPU),) CONFIG_BFIN_CPU := \ $(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \ - $(src)include/configs/$(BOARD).h) + $(srctree)/include/configs/$(BOARD).h) else -CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) +CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%)) endif -CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) +CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%)) + +# Support generic board on Blackfin +__HAVE_ARCH_GENERIC_BOARD := y PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic -PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN LDFLAGS_FINAL += --gc-sections LDFLAGS += -m elf32bfin @@ -28,10 +32,10 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) -ALL-y += $(obj)u-boot.ldr +ALL-y += u-boot.ldr endif ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) -CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o +CREATE_LDR_ENV = tools/envcrc --binary > env-ldr.o HOSTCFLAGS_NOPED_ADSP := \ $(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) ' | $(CPP) $(CPPFLAGS) - | gawk -f ./bootrom-asm-offsets.awk > $@.tmp - mv $@.tmp $@ -$(obj)bootrom-asm-offsets.s: $(obj)bootrom-asm-offsets.c - $(CC) $(CFLAGS) -S $^ -o $@.tmp - mv $@.tmp $@ -$(obj)bootrom-asm-offsets.h: $(obj)bootrom-asm-offsets.s - sed -ne "/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}" $^ > $@ +extra-y := init.elf +extra-y += initcode.o +extra-y += start.o +obj-y := interrupt.o cache.o +obj-y += cpu.o +obj-y += gpio.o +obj-y += interrupts.o +obj-$(CONFIG_JTAG_CONSOLE) += jtag-console.o +obj-y += os_log.o +obj-y += reset.o +obj-y += traps.o + +extra-y += check_initcode +clean-files := init.lds # make sure our initcode (which goes into LDR) does not # have relocs or external references -$(obj)initcode.o: CFLAGS += -fno-function-sections -fno-data-sections +CFLAGS_REMOVE_initcode.o := -ffunction-sections -fdata-sections READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $< -check_initcode: $(obj)initcode.o +$(obj)/check_initcode: $(obj)/initcode.o ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) @if $(READINIT) | grep '\.*\' ; then \ echo "$< contains external references!" 1>&2 ; \ @@ -58,16 +36,10 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) fi endif -$(obj)init.lds: init.lds.S - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@ -$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o - $(LD) $(LDFLAGS) -T $^ -o $@ - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +CPPFLAGS_init.lds := -ansi -######################################################################### +quiet_cmd_link_init = LD $@ + cmd_link_init = $(LD) $(LDFLAGS) -T $^ -o $@ +$(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o + $(call if_changed,link_init) +targets += init.lds init.o diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk deleted file mode 100755 index 1d61824254..0000000000 --- a/arch/blackfin/cpu/bootrom-asm-offsets.awk +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/gawk -f -BEGIN { - print "/* DO NOT EDIT: AUTOMATICALLY GENERATED" - print " * Input files: bootrom-asm-offsets.awk bootrom-asm-offsets.c.in" - print " * DO NOT EDIT: AUTOMATICALLY GENERATED" - print " */" - print "" - system("cat bootrom-asm-offsets.c.in") - print "{" -} - -{ - /* find a structure definition */ - if ($0 ~ /typedef struct .* {/) { - delete members; - i = 0; - - /* extract each member of the structure */ - while (1) { - getline - if ($1 == "}") - break; - gsub(/[*;]/, ""); - members[i++] = $NF; - } - - /* grab the structure's name */ - struct = $NF; - sub(/;$/, "", struct); - - /* output the DEFINE() macros */ - while (i-- > 0) - print "\tDEFINE(" struct ", " members[i] ");" - print "" - } -} - -END { - print "\treturn 0;" - print "}" -} diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.c.in b/arch/blackfin/cpu/bootrom-asm-offsets.c.in deleted file mode 100644 index 64c2f24120..0000000000 --- a/arch/blackfin/cpu/bootrom-asm-offsets.c.in +++ /dev/null @@ -1,12 +0,0 @@ -/* A little trick taken from the kernel asm-offsets.h where we convert - * the C structures automatically into a bunch of defines for use in - * the assembly files. - */ - -#include -#include - -#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val)) -#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m)) - -int main(int argc, char * const argv[]) diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 218f57ed38..91aa5cc89c 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -11,17 +11,23 @@ #include #include +#include +#include +#include + #include #include +#include #include #include #include -#include #include "cpu.h" #include "initcode.h" +#include "exports.h" ulong bfin_poweron_retx; +DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START) void bfin_core1_start(void) @@ -48,6 +54,252 @@ void bfin_core1_start(void) } #endif +__attribute__((always_inline)) +static inline void serial_early_puts(const char *s) +{ +#ifdef CONFIG_DEBUG_EARLY_SERIAL + serial_puts("Early: "); + serial_puts(s); +#endif +} + +static int global_board_data_init(void) +{ +#ifndef CONFIG_SYS_GBL_DATA_ADDR +# define CONFIG_SYS_GBL_DATA_ADDR 0 +#endif +#ifndef CONFIG_SYS_BD_INFO_ADDR +# define CONFIG_SYS_BD_INFO_ADDR 0 +#endif + + bd_t *bd; + + if (CONFIG_SYS_GBL_DATA_ADDR) { + gd = (gd_t *)(CONFIG_SYS_GBL_DATA_ADDR); + memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); + } else { + static gd_t _bfin_gd; + gd = &_bfin_gd; + } + if (CONFIG_SYS_BD_INFO_ADDR) { + bd = (bd_t *)(CONFIG_SYS_BD_INFO_ADDR); + memset(bd, 0, GENERATED_BD_INFO_SIZE); + } else { + static bd_t _bfin_bd; + bd = &_bfin_bd; + } + + gd->bd = bd; + + bd->bi_r_version = version_string; + bd->bi_cpu = __stringify(CONFIG_BFIN_CPU); + bd->bi_board_name = CONFIG_SYS_BOARD; + bd->bi_vco = get_vco(); + bd->bi_cclk = get_cclk(); + bd->bi_sclk = get_sclk(); + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + + gd->ram_size = CONFIG_SYS_MAX_RAM_SIZE; + + return 0; +} + +static void display_global_data(void) +{ + bd_t *bd; + +#ifndef CONFIG_DEBUG_EARLY_SERIAL + return; +#endif + + bd = gd->bd; + printf(" gd: %p\n", gd); + printf(" |-flags: %lx\n", gd->flags); + printf(" |-board_type: %lx\n", gd->arch.board_type); + printf(" |-baudrate: %u\n", gd->baudrate); + printf(" |-have_console: %lx\n", gd->have_console); + printf(" |-ram_size: %lx\n", gd->ram_size); + printf(" |-env_addr: %lx\n", gd->env_addr); + printf(" |-env_valid: %lx\n", gd->env_valid); + printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version); + printf(" \\-bd: %p\n", gd->bd); + printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); + printf(" |-bi_memstart: %lx\n", bd->bi_memstart); + printf(" |-bi_memsize: %lx\n", bd->bi_memsize); + printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart); + printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize); + printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset); +} + +#define CPLB_PAGE_SIZE (4 * 1024 * 1024) +#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) +#if defined(__ADSPBF60x__) +#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024) +#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1)) +#else +#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE +#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK +#endif +void init_cplbtables(void) +{ + uint32_t *ICPLB_ADDR, *ICPLB_DATA; + uint32_t *DCPLB_ADDR, *DCPLB_DATA; + uint32_t extern_memory; + size_t i; + + void icplb_add(uint32_t addr, uint32_t data) + { + bfin_write32(ICPLB_ADDR + i, addr); + bfin_write32(ICPLB_DATA + i, data); + } + void dcplb_add(uint32_t addr, uint32_t data) + { + bfin_write32(DCPLB_ADDR + i, addr); + bfin_write32(DCPLB_DATA + i, data); + } + + /* populate a few common entries ... we'll let + * the memory map and cplb exception handler do + * the rest of the work. + */ + i = 0; + ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0; + ICPLB_DATA = (uint32_t *)ICPLB_DATA0; + DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0; + DCPLB_DATA = (uint32_t *)DCPLB_DATA0; + + icplb_add(0xFFA00000, L1_IMEMORY); + dcplb_add(0xFF800000, L1_DMEMORY); + ++i; +#if defined(__ADSPBF60x__) + icplb_add(0x0, 0x0); + dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY | + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID); + ++i; +#endif + + if (CONFIG_MEM_SIZE) { + uint32_t mbase = CONFIG_SYS_MONITOR_BASE; + uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN - 1; + mbase &= CPLB_PAGE_MASK; + mend &= CPLB_PAGE_MASK; + + icplb_add(mbase, SDRAM_IKERNEL); + dcplb_add(mbase, SDRAM_DKERNEL); + ++i; + + /* + * If the monitor crosses a 4 meg boundary, we'll need + * to lock two entries for it. We assume it doesn't + * cross two 4 meg boundaries ... + */ + if (mbase != mend) { + icplb_add(mend, SDRAM_IKERNEL); + dcplb_add(mend, SDRAM_DKERNEL); + ++i; + } + } + +#ifndef __ADSPBF60x__ + icplb_add(0x20000000, SDRAM_INON_CHBL); + dcplb_add(0x20000000, SDRAM_EBIU); + ++i; +#endif + + /* Add entries for the rest of external RAM up to the bootrom */ + extern_memory = 0; + +#ifdef CONFIG_DEBUG_NULL_PTR + icplb_add(extern_memory, + (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB); + dcplb_add(extern_memory, + (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB); + ++i; + icplb_add(extern_memory, SDRAM_IKERNEL); + dcplb_add(extern_memory, SDRAM_DKERNEL); + extern_memory += CPLB_PAGE_SIZE; + ++i; +#endif + + while (i < 16 && extern_memory < + (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) { + icplb_add(extern_memory, SDRAM_IGENERIC); + dcplb_add(extern_memory, SDRAM_DGENERIC); + extern_memory += CPLB_EX_PAGE_SIZE; + ++i; + } + while (i < 16) { + icplb_add(0, 0); + dcplb_add(0, 0); + ++i; + } +} + +int print_cpuinfo(void) +{ + char buf[32]; + + printf("CPU: ADSP %s (Detected Rev: 0.%d) (%s boot)\n", + gd->bd->bi_cpu, + bfin_revid(), + get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE)); + + printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco())); + printf("Core: %s MHz, ", strmhz(buf, get_cclk())); +#if defined(__ADSPBF60x__) + printf("System0: %s MHz, ", strmhz(buf, get_sclk0())); + printf("System1: %s MHz, ", strmhz(buf, get_sclk1())); + printf("Dclk: %s MHz\n", strmhz(buf, get_dclk())); +#else + printf("System: %s MHz\n", strmhz(buf, get_sclk())); +#endif + + return 0; +} + +int exception_init(void) +{ + bfin_write_EVT3(trap); + return 0; +} + +int irq_init(void) +{ +#ifdef SIC_IMASK0 + bfin_write_SIC_IMASK0(0); + bfin_write_SIC_IMASK1(0); +# ifdef SIC_IMASK2 + bfin_write_SIC_IMASK2(0); +# endif +#elif defined(SICA_IMASK0) + bfin_write_SICA_IMASK0(0); + bfin_write_SICA_IMASK1(0); +#elif defined(SIC_IMASK) + bfin_write_SIC_IMASK(0); +#endif + /* Set up a dummy NMI handler if needed. */ + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219) + bfin_write_EVT2(evt_nmi); /* NMI */ + bfin_write_EVT5(evt_default); /* hardware error */ + bfin_write_EVT6(evt_default); /* core timer */ + bfin_write_EVT7(evt_default); + bfin_write_EVT8(evt_default); + bfin_write_EVT9(evt_default); + bfin_write_EVT10(evt_default); + bfin_write_EVT11(evt_default); + bfin_write_EVT12(evt_default); + bfin_write_EVT13(evt_default); + bfin_write_EVT14(evt_default); + bfin_write_EVT15(evt_default); + bfin_write_ILAT(0); + CSYNC(); + /* enable hardware error irq */ + irq_flags = 0x3f; + local_irq_enable(); + return 0; +} + __attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { @@ -102,48 +354,62 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) bfin_core1_start(); #endif - serial_early_puts("Board init flash\n"); - board_init_f(bootflag); + serial_early_puts("Init global data\n"); + global_board_data_init(); + + board_init_f(0); + + /* should not be reached */ + while (1); } -int exception_init(void) +int arch_cpu_init(void) { - bfin_write_EVT3(trap); + serial_early_puts("Init CPLB tables\n"); + init_cplbtables(); + + serial_early_puts("Exceptions setup\n"); + exception_init(); + +#ifndef CONFIG_ICACHE_OFF + serial_early_puts("Turn on ICACHE\n"); + icache_enable(); +#endif +#ifndef CONFIG_DCACHE_OFF + serial_early_puts("Turn on DCACHE\n"); + dcache_enable(); +#endif + +#ifdef DEBUG + if (GENERATED_GBL_DATA_SIZE < sizeof(*gd)) + hang(); +#endif + + /* Initialize */ + serial_early_puts("IRQ init\n"); + irq_init(); + return 0; } -int irq_init(void) +int arch_misc_init(void) { -#ifdef SIC_IMASK0 - bfin_write_SIC_IMASK0(0); - bfin_write_SIC_IMASK1(0); -# ifdef SIC_IMASK2 - bfin_write_SIC_IMASK2(0); -# endif -#elif defined(SICA_IMASK0) - bfin_write_SICA_IMASK0(0); - bfin_write_SICA_IMASK1(0); -#elif defined(SIC_IMASK) - bfin_write_SIC_IMASK(0); +#if defined(CONFIG_SYS_I2C) + i2c_reloc_fixup(); #endif - /* Set up a dummy NMI handler if needed. */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219) - bfin_write_EVT2(evt_nmi); /* NMI */ - bfin_write_EVT5(evt_default); /* hardware error */ - bfin_write_EVT6(evt_default); /* core timer */ - bfin_write_EVT7(evt_default); - bfin_write_EVT8(evt_default); - bfin_write_EVT9(evt_default); - bfin_write_EVT10(evt_default); - bfin_write_EVT11(evt_default); - bfin_write_EVT12(evt_default); - bfin_write_EVT13(evt_default); - bfin_write_EVT14(evt_default); - bfin_write_EVT15(evt_default); - bfin_write_ILAT(0); - CSYNC(); - /* enable hardware error irq */ - irq_flags = 0x3f; - local_irq_enable(); + + display_global_data(); + + if (CONFIG_MEM_SIZE && bfin_os_log_check()) { + puts("\nLog buffer from operating system:\n"); + bfin_os_log_dump(); + puts("\n"); + } + + return 0; +} + +int interrupt_init(void) +{ return 0; } diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index f9aff4d894..4b4cf93c2d 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -12,6 +12,7 @@ #include #include +#ifndef CONFIG_ADI_GPIO2 #if ANOMALY_05000311 || ANOMALY_05000323 enum { AWA_data = SYSCR, @@ -758,6 +759,54 @@ void bfin_reset_boot_spi_cs(unsigned short pin) udelay(1); } +int name_to_gpio(const char *name) +{ + int port_base; + + if (tolower(*name) == 'p') { + ++name; + + switch (tolower(*name)) { +#ifdef GPIO_PA0 + case 'a': port_base = GPIO_PA0; break; +#endif +#ifdef GPIO_PB0 + case 'b': port_base = GPIO_PB0; break; +#endif +#ifdef GPIO_PC0 + case 'c': port_base = GPIO_PC0; break; +#endif +#ifdef GPIO_PD0 + case 'd': port_base = GPIO_PD0; break; +#endif +#ifdef GPIO_PE0 + case 'e': port_base = GPIO_PE0; break; +#endif +#ifdef GPIO_PF0 + case 'f': port_base = GPIO_PF0; break; +#endif +#ifdef GPIO_PG0 + case 'g': port_base = GPIO_PG0; break; +#endif +#ifdef GPIO_PH0 + case 'h': port_base = GPIO_PH0; break; +#endif +#ifdef GPIO_PI0 + case 'i': port_base = GPIO_PI0; break; +#endif +#ifdef GPIO_PJ + case 'j': port_base = GPIO_PJ0; break; +#endif + default: return -1; + } + + ++name; + } else + port_base = 0; + + return port_base + simple_strtoul(name, NULL, 10); +} + void gpio_labels(void) { int c, gpio; @@ -774,3 +823,19 @@ void gpio_labels(void) continue; } } +#else +struct gpio_port_t * const gpio_array[] = { + (struct gpio_port_t *)PORTA_FER, + (struct gpio_port_t *)PORTB_FER, + (struct gpio_port_t *)PORTC_FER, + (struct gpio_port_t *)PORTD_FER, + (struct gpio_port_t *)PORTE_FER, + (struct gpio_port_t *)PORTF_FER, + (struct gpio_port_t *)PORTG_FER, +#if defined(CONFIG_BF54x) + (struct gpio_port_t *)PORTH_FER, + (struct gpio_port_t *)PORTI_FER, + (struct gpio_port_t *)PORTJ_FER, +#endif +}; +#endif diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index ffaf1017d7..fde54eaa3e 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -18,8 +18,6 @@ #include #include -#define BUG() while (1) asm volatile("emuexcpt;"); - #ifndef __ADSPBF60x__ #include #include @@ -147,8 +145,6 @@ static struct ddr_config ddr_config_table[] = { __attribute__((always_inline)) static inline void serial_init(void) { - uint32_t uart_base = UART_BASE; - #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__) # ifdef BFIN_BOOT_UART_USE_RTS # define BFIN_UART_USE_RTS 1 @@ -156,6 +152,7 @@ static inline void serial_init(void) # define BFIN_UART_USE_RTS 0 # endif if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { + uint32_t uart_base = UART_BASE; size_t i; /* force RTS rather than relying on auto RTS */ @@ -195,8 +192,8 @@ static inline void serial_init(void) #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS if (BFIN_DEBUG_EARLY_SERIAL) { - serial_early_init(uart_base); - serial_early_set_baud(uart_base, CONFIG_BAUDRATE); + serial_early_init(UART_BASE); + serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE); } #endif } @@ -547,7 +544,7 @@ maybe_self_refresh(ADI_BOOT_DATA *bs) __attribute__((always_inline)) static inline u16 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) { - u16 vr_ctl; + u16 vr_ctl = 0; serial_putc('a'); @@ -731,6 +728,8 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) serial_putc('a'); + if (BFIN_DEBUG_EARLY_SERIAL || + CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { #ifdef __ADSPBF60x__ sdivR = bfin_read_CGU_DIV(); sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7); @@ -744,6 +743,8 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) divisor = vcoB * sdivR; quotient = early_division(dividend, divisor); serial_early_put_div(quotient - ANOMALY_05000230); + } + serial_putc('c'); } @@ -913,7 +914,8 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) continue; serial_putc('z'); - uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4); + uint32_t *hibernate_magic = + (uint32_t *)bfin_read32(DPM0_RESTORE4); SSYNC(); /* make sure memory controller is done */ if (hibernate_magic[0] == 0xDEADBEEF) { serial_putc('c'); @@ -953,6 +955,7 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) uint32_t *hibernate_magic = 0; SSYNC(); + /* cppcheck-suppress nullPointer */ if (hibernate_magic[0] == 0xDEADBEEF) { serial_putc('c'); bfin_write_EVT15(hibernate_magic[1]); diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h index 1fec7f3d85..ab7fa45075 100644 --- a/arch/blackfin/cpu/initcode.h +++ b/arch/blackfin/cpu/initcode.h @@ -49,7 +49,7 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('a'); -#ifdef __ADSPBF60x__ +#ifndef __ADSPBF60x__ /* Program the async banks controller. */ #ifdef EBIU_AMGCTL bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); @@ -74,7 +74,7 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('c'); -#else /* __ADSPBF60x__ */ +#else /* __ADSPBF60x__ */ /* Program the static memory controller. */ # ifdef CONFIG_SMC_GCTL_VAL bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL); @@ -116,7 +116,7 @@ program_async_controller(ADI_BOOT_DATA *bs) bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL); # endif -#endif +#endif /* __ADSPBF60x__ */ serial_putc('d'); } diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c index 7cddb85a7f..b0abeda90a 100644 --- a/arch/blackfin/cpu/jtag-console.c +++ b/arch/blackfin/cpu/jtag-console.c @@ -112,11 +112,11 @@ static void jtag_send(const char *raw_str, uint32_t len) if (cooked_str != raw_str) free((char *)cooked_str); } -static void jtag_putc(const char c) +static void jtag_putc(struct stdio_dev *dev, const char c) { jtag_send(&c, 1); } -static void jtag_puts(const char *s) +static void jtag_puts(struct stdio_dev *dev, const char *s) { jtag_send(s, strlen(s)); } @@ -133,7 +133,7 @@ static int jtag_tstc_dbg(void) } /* Higher layers want to know when any data is available */ -static int jtag_tstc(void) +static int jtag_tstc(struct stdio_dev *dev) { return jtag_tstc_dbg() || leftovers_len; } @@ -142,7 +142,7 @@ static int jtag_tstc(void) * [32bit length][actual data] */ static uint32_t leftovers; -static int jtag_getc(void) +static int jtag_getc(struct stdio_dev *dev) { int ret; uint32_t emudat; @@ -168,12 +168,12 @@ static int jtag_getc(void) inbound_len = emudat; } else { /* store the bytes */ - leftovers_len = min(4, inbound_len); + leftovers_len = min((size_t)4, inbound_len); inbound_len -= leftovers_len; leftovers = emudat; } - return jtag_getc(); + return jtag_getc(dev); } int drv_jtag_console_init(void) diff --git a/arch/blackfin/cpu/os_log.c b/arch/blackfin/cpu/os_log.c index e1c8e2948d..2092d9e3b6 100644 --- a/arch/blackfin/cpu/os_log.c +++ b/arch/blackfin/cpu/os_log.c @@ -12,12 +12,12 @@ #define OS_LOG_MAGIC_ADDR ((unsigned long *)0x4f0) #define OS_LOG_PTR_ADDR ((char **)0x4f4) -bool bfin_os_log_check(void) +int bfin_os_log_check(void) { if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC) - return false; + return 0; *OS_LOG_MAGIC_ADDR = 0; - return true; + return 1; } void bfin_os_log_dump(void) diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index c99cf49833..f31abfacf2 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -190,19 +190,19 @@ ENTRY(_start) call _memcpy_ASM; #endif +.Lnorelocate: /* Initialize BSS section ... we know that memset() does not * use the BSS, so it is safe to call here. The bootrom LDR * takes care of clearing things for us. */ serial_early_puts("Zero BSS"); - r0.l = __bss_vma; - r0.h = __bss_vma; + r0.l = __bss_start; + r0.h = __bss_start; r1 = 0 (x); r2.l = __bss_len; r2.h = __bss_len; call _memset; -.Lnorelocate: /* Setup the actual stack in external memory */ sp.h = HI(CONFIG_STACKBASE); @@ -251,3 +251,13 @@ LENTRY(_get_pc) #endif rts; ENDPROC(_get_pc) + +ENTRY(_relocate_code) + /* Fake relocate code. Setup the new stack only */ + sp = r0; + fp = sp; + r0 = p3; + r1.h = 0x2000; + r1.l = 0x10; + jump.l _board_init_r +ENDPROC(_relocate_code) diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c index 20aeab81a2..10f72f8246 100644 --- a/arch/blackfin/cpu/traps.c +++ b/arch/blackfin/cpu/traps.c @@ -261,7 +261,7 @@ static void decode_address(char *buf, unsigned long address) if (!address) sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr); else if (address >= CONFIG_SYS_MONITOR_BASE && - address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr); else sprintf(buf, "<0x%p> /* unknown address */", paddr); diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds index 7f0411f612..ae1b813c1f 100644 --- a/arch/blackfin/cpu/u-boot.lds +++ b/arch/blackfin/cpu/u-boot.lds @@ -135,6 +135,8 @@ SECTIONS *(COMMON) . = ALIGN(4); } >ram_data - __bss_vma = ADDR(.bss); + __bss_end = .; + __bss_start = ADDR(.bss); __bss_len = SIZEOF(.bss); + __init_end = .; } diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index b58b0050ce..cd7e356459 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -13,7 +13,6 @@ * Copyright 1992, Linus Torvalds. */ -#include #include #include diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index ab31dcb815..868c82ea7d 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -42,16 +42,9 @@ # include -extern u_long get_vco(void); -extern u_long get_cclk(void); -extern u_long get_sclk(void); -extern u_long get_sclk0(void); -extern u_long get_sclk1(void); -extern u_long get_dclk(void); - # define bfin_revid() (bfin_read_CHIPID() >> 28) -extern bool bfin_os_log_check(void); +extern int bfin_os_log_check(void); extern void bfin_os_log_dump(void); extern void blackfin_icache_flush_range(const void *, const void *); @@ -81,6 +74,8 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); # define NOP_PAD_ANOMALY_05000198 #endif +#define BFIN_BUG() while (1) asm volatile("emuexcpt;"); + #define _bfin_readX(addr, size, asm_size, asm_ext) ({ \ u32 __v; \ __asm__ __volatile__( \ @@ -111,7 +106,7 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ - ({ BUG(); 0; }); \ + ({ BFIN_BUG(); 0; }); \ }) #define bfin_write(addr, val) \ do { \ @@ -119,7 +114,8 @@ do { \ case 1: bfin_write8(addr, val); break; \ case 2: bfin_write16(addr, val); break; \ case 4: bfin_write32(addr, val); break; \ - default: BUG(); \ + default: \ + BFIN_BUG(); \ } \ } while (0) diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h index f1fcd40499..05ae03c09a 100644 --- a/arch/blackfin/include/asm/clock.h +++ b/arch/blackfin/include/asm/clock.h @@ -1,4 +1,3 @@ - /* * Copyright (C) 2012 Analog Devices Inc. * Licensed under the GPL-2 or later. @@ -69,10 +68,21 @@ static inline uint32_t early_get_uart_clk(void) return uclk; } +extern u_long get_vco(void); +extern u_long get_cclk(void); +extern u_long get_sclk(void); + #ifdef CGU_DIV +extern u_long get_sclk0(void); +extern u_long get_sclk1(void); +extern u_long get_dclk(void); # define get_uart_clk get_sclk0 +# define get_i2c_clk get_sclk0 +# define get_spi_clk get_sclk1 #else # define get_uart_clk get_sclk +# define get_i2c_clk get_sclk +# define get_spi_clk get_sclk #endif #endif diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h index d0fd537d88..2d8b293c3e 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -9,9 +9,6 @@ #ifndef __ASM_BLACKFIN_CONFIG_PRE_H__ #define __ASM_BLACKFIN_CONFIG_PRE_H__ -/* Misc helper functions */ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - /* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE. * Depending on your cpu, some of these may not be valid, check your HRM. * The actual values here are meaningless as long as they're unique. diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index d870d1224f..73cbfa2cc8 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -155,13 +155,6 @@ #ifndef CONFIG_SYS_MAXARGS # define CONFIG_SYS_MAXARGS 16 #endif -#if defined(CONFIG_SYS_HZ) -# if (CONFIG_SYS_HZ != 1000) -# warning "CONFIG_SYS_HZ must always be 1000" -# endif -# undef CONFIG_SYS_HZ -#endif -#define CONFIG_SYS_HZ 1000 /* Blackfin POST tests */ #ifdef CONFIG_POST_BSPEC1_GPIO_LEDS @@ -181,4 +174,10 @@ } #endif +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_ARCH_MISC_INIT + +#define CONFIG_CPU CONFIG_BFIN_CPU + #endif diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 58a6191107..1fa1a8e6ec 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -8,6 +8,7 @@ #define __ARCH_BLACKFIN_GPIO_H__ #include +#include #define gpio_bank(x) ((x) >> 4) #define gpio_bit(x) (1<<((x) & 0xF)) @@ -71,7 +72,7 @@ #ifndef __ASSEMBLY__ -#ifdef CONFIG_ADI_GPIO1 +#ifndef CONFIG_ADI_GPIO2 void set_gpio_dir(unsigned, unsigned short); void set_gpio_inen(unsigned, unsigned short); void set_gpio_polar(unsigned, unsigned short); @@ -141,6 +142,8 @@ struct gpio_port_t { unsigned short dummy16; unsigned short inen; }; +#else +extern struct gpio_port_t * const gpio_array[]; #endif #ifdef ADI_SPECIAL_GPIO_BANKS @@ -157,55 +160,6 @@ static inline int gpio_is_valid(int number) #include -static inline int name_to_gpio(const char *name) -{ - int port_base; - - if (tolower(*name) == 'p') { - ++name; - - switch (tolower(*name)) { -#ifdef GPIO_PA0 - case 'a': port_base = GPIO_PA0; break; -#endif -#ifdef GPIO_PB0 - case 'b': port_base = GPIO_PB0; break; -#endif -#ifdef GPIO_PC0 - case 'c': port_base = GPIO_PC0; break; -#endif -#ifdef GPIO_PD0 - case 'd': port_base = GPIO_PD0; break; -#endif -#ifdef GPIO_PE0 - case 'e': port_base = GPIO_PE0; break; -#endif -#ifdef GPIO_PF0 - case 'f': port_base = GPIO_PF0; break; -#endif -#ifdef GPIO_PG0 - case 'g': port_base = GPIO_PG0; break; -#endif -#ifdef GPIO_PH0 - case 'h': port_base = GPIO_PH0; break; -#endif -#ifdef GPIO_PI0 - case 'i': port_base = GPIO_PI0; break; -#endif -#ifdef GPIO_PJ - case 'j': port_base = GPIO_PJ0; break; -#endif - default: return -1; - } - - ++name; - } else - port_base = 0; - - return port_base + simple_strtoul(name, NULL, 10); -} -#define name_to_gpio(n) name_to_gpio(n) - #define gpio_status() gpio_labels() #endif /* __ASSEMBLY__ */ diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index 69f08bc7ef..aadb0d2d4e 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h @@ -11,10 +11,9 @@ #ifdef __KERNEL__ +#include #include -#define __iomem - static inline void sync(void) { SSYNC(); diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h index 02b81d3fd1..fd0d86d39e 100644 --- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h @@ -125,6 +125,8 @@ #define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */ #define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */ +#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */ + #define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */ #define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */ diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h index 7a43bbb1a3..4c9bc9dc57 100644 --- a/arch/blackfin/include/asm/mach-common/bits/emac.h +++ b/arch/blackfin/include/asm/mach-common/bits/emac.h @@ -217,4 +217,7 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ +/*default value for EMAC_VLANx reg*/ +#define EMAC_VLANX_DEF_VAL 0xFFFF + #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/lockbox.h b/arch/blackfin/include/asm/mach-common/bits/lockbox.h deleted file mode 100644 index 77f849e8f2..0000000000 --- a/arch/blackfin/include/asm/mach-common/bits/lockbox.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Lockbox/Security Masks - */ - -#ifndef __BFIN_PERIPHERAL_LOCKBOX__ -#define __BFIN_PERIPHERAL_LOCKBOX__ - -#ifndef __ASSEMBLY__ - -#include "bootrom.h" - -/* SESR argument structure. Expected to reside at 0xFF900018. */ -typedef struct SESR_args { - unsigned short usFlags; /* security firmware flags */ - unsigned short usIRQMask; /* interrupt mask */ - unsigned long ulMessageSize; /* message length in bytes */ - unsigned long ulSFEntryPoint; /* entry point of secure function */ - unsigned long ulMessagePtr; /* pointer to the buffer containing - the digital signature and message */ - unsigned long ulReserved1; /* reserved */ - unsigned long ulReserved2; /* reserved */ -} tSESR_args; - -/* Secure Entry Service Routine */ -static void (* const sesr)(void) = (void *)_BOOTROM_SESR; - -#endif - -/* SESR flags argument bitfields */ -#define SESR_FLAGS_STAY_AT_NMI 0x0000 -#define SESR_FLAGS_DROP_BELOW_NMI 0x0001 -#define SESR_FLAGS_NO_SF_DMA 0x0000 -#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002 -#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000 -#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100 - -/* Bit masks for SECURE_SYSSWT */ -#define EMUDABL 0x00000001 /* Emulation Disable */ -#define RSTDABL 0x00000002 /* Reset Disable */ -#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */ -#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */ -#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */ -#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */ -#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */ -#define EMUOVR 0x00004000 /* Emulation Override */ -#define OTPSEN 0x00008000 /* OTP Secrets Enable */ -#define L2DABL 0x00070000 /* L2 Memory Disable */ - -/* Bit masks for SECURE_CONTROL */ -#define SECURE0 0x0001 /* SECURE 0 */ -#define SECURE1 0x0002 /* SECURE 1 */ -#define SECURE2 0x0004 /* SECURE 2 */ -#define SECURE3 0x0008 /* SECURE 3 */ - -/* Bit masks for SECURE_STATUS */ -#define SECMODE 0x0003 /* Secured Mode Control State */ -#define NMI 0x0004 /* Non Maskable Interrupt */ -#define AFVALID 0x0008 /* Authentication Firmware Valid */ -#define AFEXIT 0x0010 /* Authentication Firmware Exit */ -#define SECSTAT 0x00e0 /* Secure Status */ - -#endif diff --git a/arch/blackfin/include/asm/mach-common/bits/sport.h b/arch/blackfin/include/asm/mach-common/bits/sport.h deleted file mode 100644 index 88e7a5d324..0000000000 --- a/arch/blackfin/include/asm/mach-common/bits/sport.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * SPORT Masks - */ - -#ifndef __BFIN_PERIPHERAL_SPORT__ -#define __BFIN_PERIPHERAL_SPORT__ - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F /* TX Word Length */ -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F /* RX Word Length */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0xF000 /* Multichannel Window Size Field */ -#define WOFF 0x03FF /* Multichannel Window Offset Field */ - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0xF000 /* Multichannel Frame Delay */ -#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ -#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ -#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ -#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ -#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ -#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ -#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ -#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ -#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ -#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ -#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ -#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ -#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ -#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ -#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ -#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ - -#endif diff --git a/arch/blackfin/include/asm/net.h b/arch/blackfin/include/asm/net.h deleted file mode 100644 index 97cb46691e..0000000000 --- a/arch/blackfin/include/asm/net.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * net.h - misc Blackfin network helpers - * - * Copyright (c) 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_RAND_MAC__ -#define __ASM_BFIN_RAND_MAC__ - -/* If the board does not have a real MAC assigned to it, then generate a - * locally administrated pseudo-random one based on CYCLES and compile date. - */ -static inline void bfin_gen_rand_mac(uchar *mac_addr) -{ - /* make something up */ - const char s[] = __DATE__; - size_t i; - u32 cycles; - for (i = 0; i < 6; ++i) { - asm("%0 = CYCLES;" : "=r" (cycles)); - mac_addr[i] = cycles ^ s[i]; - } - mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */ -} - -#endif diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h new file mode 100644 index 0000000000..922cdbd892 --- /dev/null +++ b/arch/blackfin/include/asm/twi.h @@ -0,0 +1,15 @@ +/* + * i2c.c - driver for Blackfin on-chip TWI/I2C + * + * Copyright (c) 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_TWI_H +#define __ARCH_TWI_H + +#include +#include + +#endif diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h index fc36ced519..7b5cf6a1b6 100644 --- a/arch/blackfin/include/asm/u-boot.h +++ b/arch/blackfin/include/asm/u-boot.h @@ -13,7 +13,6 @@ #define _U_BOOT_H_ 1 typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ phys_size_t bi_memsize; /* size of DRAM memory in bytes */ @@ -26,9 +25,12 @@ typedef struct bd_info { unsigned long bi_vco; unsigned long bi_cclk; unsigned long bi_sclk; + unsigned char bi_enetaddr[6]; } bd_t; /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_BLACKFIN +int arch_misc_init(void); + #endif /* _U_BOOT_H_ */ diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile index 5603eb93e5..b534a98c9c 100644 --- a/arch/blackfin/lib/Makefile +++ b/arch/blackfin/lib/Makefile @@ -9,41 +9,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"' - -LIB = $(obj)lib$(ARCH).o - -SOBJS-y += ins.o -SOBJS-y += memcmp.o -SOBJS-y += memcpy.o -SOBJS-y += memmove.o -SOBJS-y += memset.o -SOBJS-y += outs.o -SOBJS-$(CONFIG_CMD_KGDB) += __kgdb.o - -COBJS-y += board.o -COBJS-y += boot.o -COBJS-y += cache.o -COBJS-y += clocks.o -COBJS-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o -COBJS-$(CONFIG_CMD_KGDB) += kgdb.o -COBJS-y += muldi3.o -COBJS-$(CONFIG_HAS_POST) += post.o -COBJS-y += string.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += ins.o +obj-y += memcmp.o +obj-y += memcpy.o +obj-y += memmove.o +obj-y += memset.o +obj-y += outs.o +obj-$(CONFIG_CMD_KGDB) += __kgdb.o +obj-y += boot.o +obj-y += cache.o +obj-y += clocks.o +obj-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o +obj-$(CONFIG_CMD_KGDB) += kgdb.o +obj-y += muldi3.o +obj-$(CONFIG_HAS_POST) += post.o +obj-y += string.o +obj-y += sections.o diff --git a/arch/blackfin/lib/__kgdb.S b/arch/blackfin/lib/__kgdb.S index 4ccde8f104..4e7b6a4eb5 100644 --- a/arch/blackfin/lib/__kgdb.S +++ b/arch/blackfin/lib/__kgdb.S @@ -1,4 +1,3 @@ - #include /* save stack context for non-local goto diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c deleted file mode 100644 index 17d1f468dd..0000000000 --- a/arch/blackfin/lib/board.c +++ /dev/null @@ -1,442 +0,0 @@ -/* - * U-boot - board.c First C file to be called contains init routines - * - * Copyright (c) 2005-2008 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_CMD_NAND -#include /* cannot even include nand.h if it isnt configured */ -#endif - -#ifdef CONFIG_BITBANGMII -#include -#endif - -#if defined(CONFIG_POST) -#include -int post_flag; -#endif - -#if defined(CONFIG_SYS_I2C) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -__attribute__((always_inline)) -static inline void serial_early_puts(const char *s) -{ -#ifdef CONFIG_DEBUG_EARLY_SERIAL - serial_puts("Early: "); - serial_puts(s); -#endif -} - -static int display_banner(void) -{ - display_options(); - printf("CPU: ADSP %s " - "(Detected Rev: 0.%d) " - "(%s boot)\n", - gd->bd->bi_cpu, - bfin_revid(), - get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE)); - return 0; -} - -static int init_baudrate(void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - gd->bd->bi_baudrate = gd->baudrate; - return 0; -} - -static void display_global_data(void) -{ - bd_t *bd; - -#ifndef CONFIG_DEBUG_EARLY_SERIAL - return; -#endif - - bd = gd->bd; - printf(" gd: %p\n", gd); - printf(" |-flags: %lx\n", gd->flags); - printf(" |-board_type: %lx\n", gd->arch.board_type); - printf(" |-baudrate: %u\n", gd->baudrate); - printf(" |-have_console: %lx\n", gd->have_console); - printf(" |-ram_size: %lx\n", gd->ram_size); - printf(" |-env_addr: %lx\n", gd->env_addr); - printf(" |-env_valid: %lx\n", gd->env_valid); - printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt)); - printf(" \\-bd: %p\n", gd->bd); - printf(" |-bi_baudrate: %x\n", bd->bi_baudrate); - printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); - printf(" |-bi_memstart: %lx\n", bd->bi_memstart); - printf(" |-bi_memsize: %lx\n", bd->bi_memsize); - printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart); - printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize); - printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset); -} - -#define CPLB_PAGE_SIZE (4 * 1024 * 1024) -#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) -#if defined(__ADSPBF60x__) -#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024) -#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1)) -#else -#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE -#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK -#endif -void init_cplbtables(void) -{ - volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; - volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA; - uint32_t extern_memory; - size_t i; - - void icplb_add(uint32_t addr, uint32_t data) - { - *(ICPLB_ADDR + i) = addr; - *(ICPLB_DATA + i) = data; - } - void dcplb_add(uint32_t addr, uint32_t data) - { - *(DCPLB_ADDR + i) = addr; - *(DCPLB_DATA + i) = data; - } - - /* populate a few common entries ... we'll let - * the memory map and cplb exception handler do - * the rest of the work. - */ - i = 0; - ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0; - ICPLB_DATA = (uint32_t *)ICPLB_DATA0; - DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0; - DCPLB_DATA = (uint32_t *)DCPLB_DATA0; - - icplb_add(0xFFA00000, L1_IMEMORY); - dcplb_add(0xFF800000, L1_DMEMORY); - ++i; -#if defined(__ADSPBF60x__) - icplb_add(0x0, 0x0); - dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); - ++i; -#endif - - if (CONFIG_MEM_SIZE) { - uint32_t mbase = CONFIG_SYS_MONITOR_BASE; - uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN; - mbase &= CPLB_PAGE_MASK; - mend &= CPLB_PAGE_MASK; - - icplb_add(mbase, SDRAM_IKERNEL); - dcplb_add(mbase, SDRAM_DKERNEL); - ++i; - - /* - * If the monitor crosses a 4 meg boundary, we'll need - * to lock two entries for it. We assume it doesn't - * cross two 4 meg boundaries ... - */ - if (mbase != mend) { - icplb_add(mend, SDRAM_IKERNEL); - dcplb_add(mend, SDRAM_DKERNEL); - ++i; - } - } - -#ifndef __ADSPBF60x__ - icplb_add(0x20000000, SDRAM_INON_CHBL); - dcplb_add(0x20000000, SDRAM_EBIU); - ++i; -#endif - - /* Add entries for the rest of external RAM up to the bootrom */ - extern_memory = 0; - -#ifdef CONFIG_DEBUG_NULL_PTR - icplb_add(extern_memory, (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB); - dcplb_add(extern_memory, (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB); - ++i; - icplb_add(extern_memory, SDRAM_IKERNEL); - dcplb_add(extern_memory, SDRAM_DKERNEL); - extern_memory += CPLB_PAGE_SIZE; - ++i; -#endif - - while (i < 16 && extern_memory < - (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) { - icplb_add(extern_memory, SDRAM_IGENERIC); - dcplb_add(extern_memory, SDRAM_DGENERIC); - extern_memory += CPLB_EX_PAGE_SIZE; - ++i; - } - while (i < 16) { - icplb_add(0, 0); - dcplb_add(0, 0); - ++i; - } -} - -static int global_board_data_init(void) -{ -#ifndef CONFIG_SYS_GBL_DATA_ADDR -# define CONFIG_SYS_GBL_DATA_ADDR 0 -#endif -#ifndef CONFIG_SYS_BD_INFO_ADDR -# define CONFIG_SYS_BD_INFO_ADDR 0 -#endif - - bd_t *bd; - - if (CONFIG_SYS_GBL_DATA_ADDR) { - gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR); - memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); - } else { - static gd_t _bfin_gd; - gd = &_bfin_gd; - } - - if (CONFIG_SYS_BD_INFO_ADDR) { - bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR); - memset(bd, 0, GENERATED_BD_INFO_SIZE); - } else { - static bd_t _bfin_bd; - bd = &_bfin_bd; - } - gd->bd = bd; - - bd->bi_r_version = version_string; - bd->bi_cpu = __stringify(CONFIG_BFIN_CPU); - bd->bi_board_name = BFIN_BOARD_NAME; - bd->bi_vco = get_vco(); - bd->bi_cclk = get_cclk(); - bd->bi_sclk = get_sclk(); - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - - return 0; -} - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - -extern int watchdog_init(void); -extern int exception_init(void); -extern int irq_init(void); -extern int timer_init(void); - -void board_init_f(ulong bootflag) -{ - char buf[32]; - -#ifdef CONFIG_BOARD_EARLY_INIT_F - serial_early_puts("Board early init flash\n"); - board_early_init_f(); -#endif - - serial_early_puts("Init CPLB tables\n"); - init_cplbtables(); - - serial_early_puts("Exceptions setup\n"); - exception_init(); - -#ifndef CONFIG_ICACHE_OFF - serial_early_puts("Turn on ICACHE\n"); - icache_enable(); -#endif -#ifndef CONFIG_DCACHE_OFF - serial_early_puts("Turn on DCACHE\n"); - dcache_enable(); -#endif - -#ifdef CONFIG_HW_WATCHDOG - serial_early_puts("Setting up external watchdog\n"); - hw_watchdog_init(); -#endif - -#ifdef DEBUG - if (GENERATED_GBL_DATA_SIZE < sizeof(*gd)) - hang(); -#endif - serial_early_puts("Init global data\n"); - - global_board_data_init(); - - /* Initialize */ - serial_early_puts("IRQ init\n"); - irq_init(); - serial_early_puts("Environment init\n"); - env_init(); - serial_early_puts("Baudrate init\n"); - init_baudrate(); - serial_early_puts("Serial init\n"); - serial_init(); - serial_initialize(); - serial_early_puts("Console init flash\n"); - console_init_f(); - serial_early_puts("End of early debugging\n"); - display_banner(); - - checkboard(); - timer_init(); - - printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco())); - printf("Core: %s MHz, ", strmhz(buf, get_cclk())); -#if defined(__ADSPBF60x__) - printf("System0: %s MHz, ", strmhz(buf, get_sclk0())); - printf("System1: %s MHz, ", strmhz(buf, get_sclk1())); - printf("Dclk: %s MHz\n", strmhz(buf, get_dclk())); -#else - printf("System: %s MHz\n", strmhz(buf, get_sclk())); -#endif - - if (CONFIG_MEM_SIZE) { - printf("RAM: "); - print_size(gd->bd->bi_memsize, "\n"); - } - -#if defined(CONFIG_POST) - post_init_f(); - post_bootmode_init(); - post_run(NULL, POST_ROM | post_bootmode_get(0)); -#endif - - board_init_r((gd_t *) gd, 0x20000010); -} - -static void board_net_init_r(bd_t *bd) -{ -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#ifdef CONFIG_CMD_NET - printf("Net: "); - eth_initialize(bd); -#endif -} - -void board_init_r(gd_t * id, ulong dest_addr) -{ - bd_t *bd; - gd = id; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - bd = gd->bd; - -#if defined(CONFIG_POST) - post_output_backlog(); -#endif - - /* initialize malloc() area */ - mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); - -#if !defined(CONFIG_SYS_NO_FLASH) - /* Initialize the flash and protect u-boot by default */ - extern flash_info_t flash_info[]; - puts("Flash: "); - ulong size = flash_init(); - print_size(size, "\n"); - flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - bd->bi_flashsize = size; - bd->bi_flashoffset = 0; -#else - bd->bi_flashstart = 0; - bd->bi_flashsize = 0; - bd->bi_flashoffset = 0; -#endif - -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); /* go init the NAND */ -#endif - -#ifdef CONFIG_GENERIC_MMC - puts("MMC: "); - mmc_initialize(bd); -#endif - -#if defined(CONFIG_SYS_I2C) - i2c_reloc_fixup(); -#endif - /* relocate environment function pointers etc. */ - env_relocate(); - - /* Initialize stdio devices */ - stdio_init(); - jumptable_init(); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r(); - -#ifdef CONFIG_CMD_KGDB - puts("KGDB: "); - kgdb_init(); -#endif - -#ifdef CONFIG_STATUS_LED - status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); - status_led_set(STATUS_LED_CRASH, STATUS_LED_OFF); -#endif - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r(); -#endif - - board_net_init_r(bd); - - display_global_data(); - -#if defined(CONFIG_POST) - if (post_flag) - post_run(NULL, POST_RAM | post_bootmode_get(0)); -#endif - - if (CONFIG_MEM_SIZE && bfin_os_log_check()) { - puts("\nLog buffer from operating system:\n"); - bfin_os_log_dump(); - puts("\n"); - } - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) - main_loop(); -} diff --git a/arch/blackfin/lib/cache.c b/arch/blackfin/lib/cache.c index 0a321a448f..e8a0cb5deb 100644 --- a/arch/blackfin/lib/cache.c +++ b/arch/blackfin/lib/cache.c @@ -111,3 +111,13 @@ int dcache_status(void) { return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE; } + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + blackfin_dcache_flush_invalidate_range((const void *)start, (const void *)stop); +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + blackfin_dcache_flush_range((const void *)start, (const void *)stop); +} diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c index 97795e11ac..7ed56a7274 100644 --- a/arch/blackfin/lib/clocks.c +++ b/arch/blackfin/lib/clocks.c @@ -36,7 +36,10 @@ u_long get_vco(void) u_long get_cclk(void) { static u_long cached_cclk_pll_div, cached_cclk; - u_long div, csel, ssel; + u_long div, csel; +#ifndef CGU_DIV + u_long ssel; +#endif if (pll_is_bypassed()) return CONFIG_CLKIN_HZ; diff --git a/arch/blackfin/lib/sections.c b/arch/blackfin/lib/sections.c new file mode 100644 index 0000000000..b50f30aa45 --- /dev/null +++ b/arch/blackfin/lib/sections.c @@ -0,0 +1,11 @@ +/* + * U-boot - section.c + * + * Copyright (c) 2014 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +char __bss_start[0] __attribute__((section(".__bss_start"))); +char __bss_end[0] __attribute__((section(".__bss_end"))); +char __init_end[0] __attribute__((section(".__init_end"))); diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c index f0a061b47a..211df7b430 100644 --- a/arch/blackfin/lib/string.c +++ b/arch/blackfin/lib/string.c @@ -121,7 +121,7 @@ static void dma_calc_size(unsigned long ldst, unsigned long lsrc, size_t count, *dshift = WDSIZE_P; #endif - *bpos = min(limit, ffs(ldst | lsrc | count)) - 1; + *bpos = min(limit, (unsigned long)ffs(ldst | lsrc | count)) - 1; } /* This version misbehaves for count values of 0 and 2^16+. @@ -157,7 +157,7 @@ void dma_memcpy_nocache(void *dst, const void *src, size_t count) #ifdef PSIZE /* The max memory DMA peripheral transfer size is 4 bytes. */ - dsize |= min(2, bpos) << PSIZE_P; + dsize |= min(2UL, bpos) << PSIZE_P; #endif /* Copy sram functions from sdram to sram */ diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig new file mode 100644 index 0000000000..78c98ed2d0 --- /dev/null +++ b/arch/m68k/Kconfig @@ -0,0 +1,93 @@ +menu "M68000 architecture" + depends on M68K + +config SYS_ARCH + default "m68k" + +choice + prompt "Target select" + +config TARGET_M52277EVB + bool "Support M52277EVB" + +config TARGET_M5235EVB + bool "Support M5235EVB" + +config TARGET_COBRA5272 + bool "Support cobra5272" + +config TARGET_EB_CPU5282 + bool "Support eb_cpu5282" + +config TARGET_M5208EVBE + bool "Support M5208EVBE" + +config TARGET_M5249EVB + bool "Support M5249EVB" + +config TARGET_M5253DEMO + bool "Support M5253DEMO" + +config TARGET_M5253EVBE + bool "Support M5253EVBE" + +config TARGET_M5272C3 + bool "Support M5272C3" + +config TARGET_M5275EVB + bool "Support M5275EVB" + +config TARGET_M5282EVB + bool "Support M5282EVB" + +config TARGET_ASTRO_MCF5373L + bool "Support astro_mcf5373l" + +config TARGET_M53017EVB + bool "Support M53017EVB" + +config TARGET_M5329EVB + bool "Support M5329EVB" + +config TARGET_M5373EVB + bool "Support M5373EVB" + +config TARGET_M54418TWR + bool "Support M54418TWR" + +config TARGET_M54451EVB + bool "Support M54451EVB" + +config TARGET_M54455EVB + bool "Support M54455EVB" + +config TARGET_M5475EVB + bool "Support M5475EVB" + +config TARGET_M5485EVB + bool "Support M5485EVB" + +endchoice + +source "board/BuS/eb_cpu5282/Kconfig" +source "board/astro/mcf5373l/Kconfig" +source "board/cobra5272/Kconfig" +source "board/freescale/m5208evbe/Kconfig" +source "board/freescale/m52277evb/Kconfig" +source "board/freescale/m5235evb/Kconfig" +source "board/freescale/m5249evb/Kconfig" +source "board/freescale/m5253demo/Kconfig" +source "board/freescale/m5253evbe/Kconfig" +source "board/freescale/m5272c3/Kconfig" +source "board/freescale/m5275evb/Kconfig" +source "board/freescale/m5282evb/Kconfig" +source "board/freescale/m53017evb/Kconfig" +source "board/freescale/m5329evb/Kconfig" +source "board/freescale/m5373evb/Kconfig" +source "board/freescale/m54418twr/Kconfig" +source "board/freescale/m54451evb/Kconfig" +source "board/freescale/m54455evb/Kconfig" +source "board/freescale/m547xevb/Kconfig" +source "board/freescale/m548xevb/Kconfig" + +endmenu diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile new file mode 100644 index 0000000000..aa3d2fae63 --- /dev/null +++ b/arch/m68k/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/m68k/cpu/$(CPU)/start.o + +libs-y += arch/m68k/cpu/$(CPU)/ +libs-y += arch/m68k/lib/ diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index 9c3e24f2fc..3b3a7e88ab 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -5,11 +5,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= m68k-elf- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := m68k-elf- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 -PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ +PLATFORM_CPPFLAGS += -D__M68K__ PLATFORM_LDFLAGS += -n -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data LDFLAGS_FINAL += --gc-sections diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile index e5384cc10e..e0c5db60f4 100644 --- a/arch/m68k/cpu/mcf5227x/Makefile +++ b/arch/m68k/cpu/mcf5227x/Makefile @@ -5,28 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +# ccflags-y += -DET_DEBUG -# CFLAGS += -DET_DEBUG - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o speed.o cpu_init.o interrupts.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf5227x/config.mk b/arch/m68k/cpu/mcf5227x/config.mk index 2681171458..b5c26e4e5b 100644 --- a/arch/m68k/cpu/mcf5227x/config.mk +++ b/arch/m68k/cpu/mcf5227x/config.mk @@ -7,5 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index c84edd3632..23024f94c8 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -2,7 +2,7 @@ * Copyright (C) 2003 Josef Baumgartner * Based on code from Bernhard Kuhn * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/m68k/cpu/mcf523x/Makefile b/arch/m68k/cpu/mcf523x/Makefile index e5384cc10e..e0c5db60f4 100644 --- a/arch/m68k/cpu/mcf523x/Makefile +++ b/arch/m68k/cpu/mcf523x/Makefile @@ -5,28 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +# ccflags-y += -DET_DEBUG -# CFLAGS += -DET_DEBUG - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o speed.o cpu_init.o interrupts.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf523x/config.mk b/arch/m68k/cpu/mcf523x/config.mk index 620769fb19..c9435ab99b 100644 --- a/arch/m68k/cpu/mcf523x/config.mk +++ b/arch/m68k/cpu/mcf523x/config.mk @@ -7,5 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 5a789540fc..af1fd56068 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -20,6 +20,13 @@ #include #endif +/* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */ +#ifdef CONFIG_M5235 +#define out_be_fbcs_reg out_be16 +#else +#define out_be_fbcs_reg out_be32 +#endif + /* * Breath some life into the CPU... * @@ -45,57 +52,57 @@ void cpu_init_f(void) out_8(&gpio->par_cs, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4); - out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); - out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5); - out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); - out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6); - out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); - out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); + out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE); + out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); #endif #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7); - out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); - out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); + out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE); + out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); #endif diff --git a/arch/m68k/cpu/mcf52x2/Makefile b/arch/m68k/cpu/mcf52x2/Makefile index 3a22aeebf1..b92fd864c4 100644 --- a/arch/m68k/cpu/mcf52x2/Makefile +++ b/arch/m68k/cpu/mcf52x2/Makefile @@ -5,29 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +# ccflags-y += -DET_DEBUG -# CFLAGS += -DET_DEBUG - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = interrupts.o cpu.o speed.o cpu_init.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = interrupts.o cpu.o speed.o cpu_init.o diff --git a/arch/m68k/cpu/mcf52x2/config.mk b/arch/m68k/cpu/mcf52x2/config.mk index d0be46fd9c..f66000b331 100644 --- a/arch/m68k/cpu/mcf52x2/config.mk +++ b/arch/m68k/cpu/mcf52x2/config.mk @@ -7,16 +7,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data - -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg)) -is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg)) -is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg)) -is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg)) -is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg)) -is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg)) -is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg)) +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is5208:=$(shell grep CONFIG_M5208 $(cfg)) +is5249:=$(shell grep CONFIG_M5249 $(cfg)) +is5253:=$(shell grep CONFIG_M5253 $(cfg)) +is5271:=$(shell grep CONFIG_M5271 $(cfg)) +is5272:=$(shell grep CONFIG_M5272 $(cfg)) +is5275:=$(shell grep CONFIG_M5275 $(cfg)) +is5282:=$(shell grep CONFIG_M5282 $(cfg)) ifneq (,$(findstring CONFIG_M5208,$(is5208))) PLATFORM_CPPFLAGS += -mcpu=5208 diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index 0882c3b8e5..edcb092fec 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -15,7 +15,7 @@ * MCF5275 additions * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/m68k/cpu/mcf532x/Makefile b/arch/m68k/cpu/mcf532x/Makefile index 7d71dd9ca5..9c53c50c48 100644 --- a/arch/m68k/cpu/mcf532x/Makefile +++ b/arch/m68k/cpu/mcf532x/Makefile @@ -5,28 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +# ccflags-y += -DET_DEBUG -# CFLAGS += -DET_DEBUG - -LIB = $(obj)lib$(CPU).o - -START = -COBJS = cpu.o speed.o cpu_init.o interrupts.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y := start.o +obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf532x/config.mk b/arch/m68k/cpu/mcf532x/config.mk index be1220365a..2efb60f04a 100644 --- a/arch/m68k/cpu/mcf532x/config.mk +++ b/arch/m68k/cpu/mcf532x/config.mk @@ -7,11 +7,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data - -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg)) -is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg)) +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is5301x:=$(shell grep CONFIG_MCF5301x $(cfg)) +is532x:=$(shell grep CONFIG_MCF532x $(cfg)) ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index db7ded4782..8d01f5fcf0 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -208,10 +208,10 @@ void cpu_init_f(void) scm2_t *scm2 = (scm2_t *) MMAP_SCM2; gpio_t *gpio = (gpio_t *) MMAP_GPIO; fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; +#ifndef CONFIG_WATCHDOG wdog_t *wdog = (wdog_t *) MMAP_WDOG; /* watchdog is enabled by default - disable the watchdog */ -#ifndef CONFIG_WATCHDOG out_be16(&wdog->cr, 0); #endif diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 322b699465..3b9ede0d3d 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -5,7 +5,7 @@ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile index b76d0ed803..9be91ed157 100644 --- a/arch/m68k/cpu/mcf5445x/Makefile +++ b/arch/m68k/cpu/mcf5445x/Makefile @@ -5,28 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +# ccflags-y += -DET_DEBUG -# CFLAGS += -DET_DEBUG - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk index d546b22058..13f8a9f57b 100644 --- a/arch/m68k/cpu/mcf5445x/config.mk +++ b/arch/m68k/cpu/mcf5445x/config.mk @@ -9,10 +9,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data - -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg)) +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is5441x:=$(shell grep CONFIG_MCF5441x $(cfg)) ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x))) PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 9c324dc968..b4a8eefa94 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -364,9 +364,9 @@ void uart_port_conf(int port) int fecpin_setclear(struct eth_device *dev, int setclear) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; +#ifdef CONFIG_MCF5445x struct fec_info_s *info = (struct fec_info_s *)dev->priv; -#ifdef CONFIG_MCF5445x if (setclear) { #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY if (info->iobase == CONFIG_SYS_FEC0_IOBASE) diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c index 235e2cc8f4..e41f36cdd2 100644 --- a/arch/m68k/cpu/mcf5445x/pci.c +++ b/arch/m68k/cpu/mcf5445x/pci.c @@ -2,7 +2,7 @@ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 07a9b359b5..4e363a4190 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -115,7 +115,7 @@ void setup_5441x_clocks(void) gd->cpu_clk = vco / temp; /* cpu clock */ gd->arch.flb_clk = vco / temp; /* FlexBus clock */ gd->arch.flb_clk >>= 1; - if (in_be16(ccm->misccr2) & 2) /* fsys/4 */ + if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ gd->arch.flb_clk >>= 1; temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1; diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 18f8da550c..979eb5a765 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -5,7 +5,7 @@ * Copyright 2010-2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/m68k/cpu/mcf547x_8x/Makefile b/arch/m68k/cpu/mcf547x_8x/Makefile index 13d3c9bb3c..4f82099b6b 100644 --- a/arch/m68k/cpu/mcf547x_8x/Makefile +++ b/arch/m68k/cpu/mcf547x_8x/Makefile @@ -5,28 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +# ccflags-y += -DET_DEBUG -# CFLAGS += -DET_DEBUG - -LIB = $(obj)lib$(CPU).o - -START = -COBJS = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o diff --git a/arch/m68k/cpu/mcf547x_8x/config.mk b/arch/m68k/cpu/mcf547x_8x/config.mk index 345f5841ac..825f6ccebe 100644 --- a/arch/m68k/cpu/mcf547x_8x/config.mk +++ b/arch/m68k/cpu/mcf547x_8x/config.mk @@ -7,7 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC ifneq (,$(findstring -linux-,$(shell $(CC) --version))) diff --git a/arch/m68k/cpu/mcf547x_8x/pci.c b/arch/m68k/cpu/mcf547x_8x/pci.c index 1a40108377..cde7e5aa69 100644 --- a/arch/m68k/cpu/mcf547x_8x/pci.c +++ b/arch/m68k/cpu/mcf547x_8x/pci.c @@ -2,7 +2,7 @@ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* diff --git a/arch/m68k/cpu/mcf547x_8x/slicetimer.c b/arch/m68k/cpu/mcf547x_8x/slicetimer.c index 7be713e62b..2e7ed36e11 100644 --- a/arch/m68k/cpu/mcf547x_8x/slicetimer.c +++ b/arch/m68k/cpu/mcf547x_8x/slicetimer.c @@ -2,7 +2,7 @@ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index c41c79a958..75de22d37c 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -2,7 +2,7 @@ * Copyright (C) 2003 Josef Baumgartner * Based on code from Bernhard Kuhn * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index 525d90ccb0..f9c434b4a3 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -5,7 +5,6 @@ #ifndef _M68K_BITOPS_H #define _M68K_BITOPS_H -#include #include extern void set_bit(int nr, volatile void *addr); diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h index 5f3ef5287a..a36e065c75 100644 --- a/arch/m68k/include/asm/immap_5282.h +++ b/arch/m68k/include/asm/immap_5282.h @@ -3,7 +3,7 @@ * * Copyright (c) 2003 Josef Baumgartner * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __IMMAP_5282__ diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index 5a87a9b810..2d2a51901b 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -32,10 +32,10 @@ #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) #else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#define readw(addr) in_be16((volatile u16 *)(addr)) +#define readl(addr) in_be32((volatile u32 *)(addr)) +#define writew(b,addr) out_be16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_be32((volatile u32 *)(addr),(b)) #endif /* diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h index 99de31aff5..983cb2d967 100644 --- a/arch/m68k/include/asm/u-boot.h +++ b/arch/m68k/include/asm/u-boot.h @@ -44,7 +44,6 @@ typedef struct bd_info { unsigned long bi_vcofreq; /* vco Freq in MHz */ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index 48973fd87b..65867d6e47 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -5,30 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).o - -SOBJS-y += - -COBJS-y += board.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-y += cache.o -COBJS-y += interrupts.o -COBJS-y += time.o -COBJS-y += traps.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += board.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-y += cache.o +obj-y += interrupts.o +obj-y += time.o +obj-y += traps.o diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index e75b6a98dd..9caff73505 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -31,9 +31,6 @@ #endif #include #include -#if defined(CONFIG_CMD_BEDBUG) -#include -#endif #ifdef CONFIG_SYS_ALLOC_DPRAM #include #endif @@ -342,7 +339,6 @@ board_init_f (ulong bootflag) bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ #endif - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CONFIG_SYS_EXTBDINFO strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); @@ -603,11 +599,6 @@ void board_init_r (gd_t *id, ulong dest_addr) last_stage_init (); #endif -#if defined(CONFIG_CMD_BEDBUG) - WATCHDOG_RESET (); - bedbug_init (); -#endif - #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) /* * Export available size of memory for Linux, @@ -629,13 +620,6 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif -#ifdef CONFIG_MODEM_SUPPORT - { - extern int do_mdm_init; - do_mdm_init = gd->do_mdm_init; - } -#endif - #ifdef CONFIG_WATCHDOG /* disable watchdog if environment is set */ if ((s = getenv ("watchdog")) != NULL) { diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index 804e01dae6..fa9c493081 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -50,11 +50,7 @@ void arch_lmb_reserve(struct lmb *lmb) int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { - ulong rd_len; - ulong initrd_start, initrd_end; int ret; - - ulong cmd_start, cmd_end; bd_t *kbd; void (*kernel) (bd_t *, ulong, ulong, ulong, ulong); struct lmb *lmb = &images->lmb; @@ -96,7 +92,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima * sp+16: Start of command line string * sp+20: End of command line string */ - (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + (*kernel)(kbd, images->initrd_start, images->initrd_end, + images->cmdline_start, images->cmdline_end); /* does not return */ error: return 1; diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c index a85c22bcb3..31633543e0 100644 --- a/arch/m68k/lib/time.c +++ b/arch/m68k/lib/time.c @@ -4,7 +4,7 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index 55bf0c290f..cbd410ceb7 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -20,7 +20,7 @@ extern void _int_handler(void); static void show_frame(struct pt_regs *fp) { printf ("Vector Number: %d Format: %02x Fault Status: %01x\n\n", (fp->vector & 0x3fc) >> 2, - fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8)); + fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8)); printf ("PC: %08lx SR: %08lx SP: %08lx\n", fp->pc, (long) fp->sr, (long) fp); printf ("D0: %08lx D1: %08lx D2: %08lx D3: %08lx\n", fp->d0, fp->d1, fp->d2, fp->d3); diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig new file mode 100644 index 0000000000..6f419f050d --- /dev/null +++ b/arch/microblaze/Kconfig @@ -0,0 +1,18 @@ +menu "MicroBlaze architecture" + depends on MICROBLAZE + +config SYS_ARCH + default "microblaze" + +choice + prompt "Target select" + +config TARGET_MICROBLAZE_GENERIC + bool "Support microblaze-generic" + select SUPPORT_SPL + +endchoice + +source "board/xilinx/microblaze-generic/Kconfig" + +endmenu diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile new file mode 100644 index 0000000000..ae4adc29c4 --- /dev/null +++ b/arch/microblaze/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/microblaze/cpu/start.o + +libs-y += arch/microblaze/cpu/ +libs-y += arch/microblaze/lib/ diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index fc545a9ee6..98bbf794fa 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -8,10 +8,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= mb- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := mb- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ - -LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index d0931f8495..4955e81236 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -5,28 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -SOBJS = irq.o -COBJS = cpu.o interrupts.o cache.o exception.o timer.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = irq.o +obj-y += cpu.o interrupts.o cache.o exception.o timer.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c index 9218355ae1..227842f6a4 100644 --- a/arch/microblaze/cpu/exception.c +++ b/arch/microblaze/cpu/exception.c @@ -35,6 +35,9 @@ void _hw_exception_handler (void) puts ("Divide by zero exception\n"); break; #ifdef MICROBLAZE_V5 + case 0x7: + puts("Priviledged or stack protection violation exception\n"); + break; case 0x1000: puts ("Exception in delay slot\n"); break; diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c new file mode 100644 index 0000000000..091226133e --- /dev/null +++ b/arch/microblaze/cpu/spl.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +bool boot_linux; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NOR; +} + +/* Board initialization after bss clearance */ +void spl_board_init(void) +{ + gd = (gd_t *)CONFIG_SPL_STACK_ADDR; + + /* enable console uart printing */ + preloader_console_init(); +} + +#ifdef CONFIG_SPL_OS_BOOT +void __noreturn jump_to_image_linux(void *arg) +{ + debug("Entering kernel arg pointer: 0x%p\n", arg); + typedef void (*image_entry_arg_t)(char *, ulong, ulong) + __attribute__ ((noreturn)); + image_entry_arg_t image_entry = + (image_entry_arg_t)spl_image.entry_point; + + image_entry(NULL, 0, (ulong)arg); +} +#endif /* CONFIG_SPL_OS_BOOT */ + +int spl_start_uboot(void) +{ +#ifdef CONFIG_SPL_OS_BOOT + if (boot_linux) + return 0; +#endif + + return 1; +} diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8928024838..84c29e5409 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -22,7 +22,16 @@ _start: */ mts rmsr, r0 /* disable cache */ + + addi r8, r0, __end + mts rslr, r8 +#if defined(CONFIG_SPL_BUILD) + addi r1, r0, CONFIG_SPL_STACK_ADDR + mts rshr, r1 + addi r1, r1, -4 /* Decrement SP to top of memory */ +#else addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET + mts rshr, r1 addi r1, r1, -4 /* Decrement SP to top of memory */ /* Find-out if u-boot is running on BIG/LITTLE endian platform @@ -115,6 +124,7 @@ _start: sh r7, r0, r8 rsubi r8, r10, 0x26 sh r6, r0, r8 +#endif /* BUILD_SPL */ /* Flush cache before enable cache */ addik r5, r0, 0 @@ -124,7 +134,7 @@ flush: bralid r15, flush_cache /* enable instruction and data cache */ mfs r12, rmsr - ori r12, r12, 0xa0 + ori r12, r12, 0x1a0 mts rmsr, r12 clear_bss: @@ -139,9 +149,14 @@ clear_bss: cmp r6, r5, r4 /* check if we have reach the end */ bnei r6, 2b 3: /* jumping to board_init */ +#ifndef CONFIG_SPL_BUILD brai board_init_f +#else + brai board_init_r +#endif 1: bri 1b +#ifndef CONFIG_SPL_BUILD /* * Read 16bit little endian */ @@ -174,3 +189,4 @@ out16: bslli r3, r6, 8 rtsd r15, 8 or r0, r0, r0 .end out16 +#endif diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c index 69ae6d4d87..3960bbb08a 100644 --- a/arch/microblaze/cpu/timer.c +++ b/arch/microblaze/cpu/timer.c @@ -34,6 +34,7 @@ void __udelay(unsigned long usec) } } +#ifndef CONFIG_SPL_BUILD static void timer_isr(void *arg) { timestamp++; @@ -62,10 +63,15 @@ int timer_init (void) if (ret) tmr = NULL; } - /* No problem if timer is not found/initialized */ return 0; } +#else +int timer_init(void) +{ + return 0; +} +#endif /* * This function is derived from PowerPC code (read timebase as long long). diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds new file mode 100644 index 0000000000..96353cd96c --- /dev/null +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +OUTPUT_ARCH(microblaze) +ENTRY(_start) + +SECTIONS +{ + .text ALIGN(0x4): + { + __text_start = .; + arch/microblaze/cpu/start.o (.text) + *(.text) + *(.text.*) + __text_end = .; + } + + .rodata ALIGN(0x4): + { + __rodata_start = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + __rodata_end = .; + } + + .data ALIGN(0x4): + { + __data_start = .; + *(.data) + *(.data.*) + __data_end = .; + } + + .bss ALIGN(0x4): + { + __bss_start = .; + *(.sbss) + *(.scommon) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; + } + __end = . ; +} + +#if defined(CONFIG_SPL_MAX_FOOTPRINT) +ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ + "SPL image plus BSS too big"); +#endif diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index 3e6204de32..fdad20753d 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { __data_start = .; #ifdef CONFIG_OF_EMBED - dts/libdts.o (.data) + dts/built-in.o (.data) #endif *(.data) __data_end = .; diff --git a/arch/microblaze/dts/.gitignore b/arch/microblaze/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/microblaze/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile new file mode 100644 index 0000000000..6d4a11f62f --- /dev/null +++ b/arch/microblaze/dts/Makefile @@ -0,0 +1,11 @@ +dtb-y += microblaze-generic.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/microblaze/dts/include/dt-bindings b/arch/microblaze/dts/include/dt-bindings new file mode 120000 index 0000000000..0cecb3d080 --- /dev/null +++ b/arch/microblaze/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings \ No newline at end of file diff --git a/board/xilinx/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts similarity index 100% rename from board/xilinx/dts/microblaze-generic.dts rename to arch/microblaze/dts/microblaze-generic.dts diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h index ce9bb8a8d6..c1c3b03985 100644 --- a/arch/microblaze/include/asm/asm.h +++ b/arch/microblaze/include/asm/asm.h @@ -3,7 +3,7 @@ * * Michal SIMEK * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* FSL macros */ diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h index eafa2b576b..0ac78d76f9 100644 --- a/arch/microblaze/include/asm/bitops.h +++ b/arch/microblaze/include/asm/bitops.h @@ -5,7 +5,6 @@ * Copyright 1992, Linus Torvalds. */ -#include #include /* swab32 */ #include /* save_flags */ diff --git a/arch/microblaze/include/asm/gpio.h b/arch/microblaze/include/asm/gpio.h index f5cad56686..4762de0243 100644 --- a/arch/microblaze/include/asm/gpio.h +++ b/arch/microblaze/include/asm/gpio.h @@ -12,4 +12,3 @@ extern int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no); extern void gpio_info(void); #endif - diff --git a/arch/microblaze/include/asm/microblaze_intc.h b/arch/microblaze/include/asm/microblaze_intc.h index bfbd724004..0fb9207882 100644 --- a/arch/microblaze/include/asm/microblaze_intc.h +++ b/arch/microblaze/include/asm/microblaze_intc.h @@ -3,7 +3,7 @@ * * Michal SIMEK * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ typedef volatile struct microblaze_intc_t { @@ -36,4 +36,3 @@ int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg); int interrupts_init(void); - diff --git a/arch/microblaze/include/asm/microblaze_timer.h b/arch/microblaze/include/asm/microblaze_timer.h index cfd3792ae9..0d8140201d 100644 --- a/arch/microblaze/include/asm/microblaze_timer.h +++ b/arch/microblaze/include/asm/microblaze_timer.h @@ -25,4 +25,3 @@ typedef volatile struct microblaze_timer_t { } microblaze_timer_t; int timer_init(void); - diff --git a/arch/microblaze/include/asm/posix_types.h b/arch/microblaze/include/asm/posix_types.h index 38dc5aa85d..ccc6235c8d 100644 --- a/arch/microblaze/include/asm/posix_types.h +++ b/arch/microblaze/include/asm/posix_types.h @@ -27,7 +27,11 @@ typedef int __kernel_pid_t; typedef unsigned short __kernel_ipc_pid_t; typedef unsigned int __kernel_uid_t; typedef unsigned int __kernel_gid_t; +#ifdef __GNUC__ +typedef __SIZE_TYPE__ __kernel_size_t; +#else typedef unsigned int __kernel_size_t; +#endif typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h index a2a58117b8..5afc8f9e5a 100644 --- a/arch/microblaze/include/asm/processor.h +++ b/arch/microblaze/include/asm/processor.h @@ -16,7 +16,6 @@ extern char __text_start[]; void board_init(void); /* Watchdog functions */ -extern int hw_watchdog_init(void); extern void hw_watchdog_disable(void); #endif /* __ASM_MICROBLAZE_PROCESSOR_H */ diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h new file mode 100644 index 0000000000..c1cae6cf0f --- /dev/null +++ b/arch/microblaze/include/asm/spl.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_MICROBLAZE_SPL_H_ +#define _ASM_MICROBLAZE_SPL_H_ + +#define BOOT_DEVICE_RAM 1 +#define BOOT_DEVICE_NOR 2 +#define BOOT_DEVICE_SPI 3 + +#endif diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h index 31b014c77d..54d415ebb5 100644 --- a/arch/microblaze/include/asm/u-boot.h +++ b/arch/microblaze/include/asm/u-boot.h @@ -24,7 +24,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ + ulong bi_boot_params; /* where this board expects params */ } bd_t; /* For image.h:image_check_target_arch() */ diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile index b86f980e16..339dd153a0 100644 --- a/arch/microblaze/lib/Makefile +++ b/arch/microblaze/lib/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).o - -SOBJS-y += - -COBJS-y += board.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-y += muldi3.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += board.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-y += muldi3.o diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index 8267191fde..600c80ab76 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,12 @@ DECLARE_GLOBAL_DATA_PTR; +static int display_banner(void) +{ + printf("\n\n%s\n\n", version_string); + return 0; +} + /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -43,12 +50,14 @@ init_fnc_t *init_sequence[] = { fdtdec_check_fdt, #endif serial_init, +#ifndef CONFIG_SPL_BUILD console_init_f, - interrupts_init, -#ifdef CONFIG_XILINX_TB_WATCHDOG - hw_watchdog_init, #endif + display_banner, +#ifndef CONFIG_SPL_BUILD + interrupts_init, timer_init, +#endif NULL, }; @@ -61,7 +70,7 @@ void board_init_f(ulong not_used) gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET); bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - GENERATED_BD_INFO_SIZE); -#if defined(CONFIG_CMD_FLASH) +#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD) ulong flash_size = 0; #endif asm ("nop"); /* FIXME gd is not initialize - wait */ @@ -69,7 +78,6 @@ void board_init_f(ulong not_used) memset((void *)bd, 0, GENERATED_BD_INFO_SIZE); gd->bd = bd; gd->baudrate = CONFIG_BAUDRATE; - bd->bi_baudrate = CONFIG_BAUDRATE; bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ @@ -78,14 +86,17 @@ void board_init_f(ulong not_used) #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; + gd->fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ gd->fdt_blob = (void *)__end; #endif + +#ifndef CONFIG_SPL_BUILD /* Allow the early environment to override the fdt address */ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, (uintptr_t)gd->fdt_blob); +#endif /* * The Malloc area is immediately below the monitor copy in DRAM @@ -96,12 +107,16 @@ void board_init_f(ulong not_used) serial_initialize(); +#ifdef CONFIG_XILINX_TB_WATCHDOG + hw_watchdog_init(); +#endif for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { WATCHDOG_RESET(); if ((*init_fnc_ptr) () != 0) hang(); } +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_OF_CONTROL /* For now, put this check after the console is ready */ if (fdtdec_prepare_fdt()) @@ -147,6 +162,10 @@ void board_init_f(ulong not_used) } #endif +#ifdef CONFIG_SPI + spi_init(); +#endif + /* relocate environment function pointers etc. */ env_relocate(); @@ -178,4 +197,5 @@ void board_init_f(ulong not_used) WATCHDOG_RESET(); main_loop(); } +#endif /* CONFIG_SPL_BUILD */ } diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index f5a7f1d48a..6977dd641a 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -5,7 +5,7 @@ * Michal SIMEK * Yasushi SHOJI * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -58,7 +58,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], /* fixup the initrd now that we know where it should be */ if (images->rd_start && images->rd_end && of_flat_tree) ret = fdt_initrd(of_flat_tree, images->rd_start, - images->rd_end, 1); + images->rd_end); if (ret) return 1; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig new file mode 100644 index 0000000000..bc4283d2f1 --- /dev/null +++ b/arch/mips/Kconfig @@ -0,0 +1,196 @@ +menu "MIPS architecture" + depends on MIPS + +config SYS_ARCH + default "mips" + +config SYS_CPU + default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2 + default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2 + +config USE_PRIVATE_LIBGCC + default y + +choice + prompt "Target select" + +config TARGET_QEMU_MIPS + bool "Support qemu-mips" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_CPU_MIPS64_R1 + select SUPPORTS_CPU_MIPS64_R2 + +config TARGET_MALTA + bool "Support malta" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SWAP_IO_SPACE + +config TARGET_VCT + bool "Support vct" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + +config TARGET_DBAU1X00 + bool "Support dbau1x00" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + +config TARGET_PB1X00 + bool "Support pb1x00" + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + + +endchoice + +source "board/dbau1x00/Kconfig" +source "board/imgtec/malta/Kconfig" +source "board/micronas/vct/Kconfig" +source "board/pb1x00/Kconfig" +source "board/qemu-mips/Kconfig" + +if MIPS + +choice + prompt "Endianness selection" + help + Some MIPS boards can be configured for either little or big endian + byte order. These modes require different U-Boot images. In general there + is one preferred byteorder for a particular system but some systems are + just as commonly used in the one or the other endianness. + +config SYS_BIG_ENDIAN + bool "Big endian" + depends on SUPPORTS_BIG_ENDIAN + +config SYS_LITTLE_ENDIAN + bool "Little endian" + depends on SUPPORTS_LITTLE_ENDIAN + +endchoice + +choice + prompt "CPU selection" + default CPU_MIPS32_R2 + +config CPU_MIPS32_R1 + bool "MIPS32 Release 1" + depends on SUPPORTS_CPU_MIPS32_R1 + select 32BIT + help + Choose this option to build an U-Boot for release 1 or later of the + MIPS32 architecture. + +config CPU_MIPS32_R2 + bool "MIPS32 Release 2" + depends on SUPPORTS_CPU_MIPS32_R2 + select 32BIT + help + Choose this option to build an U-Boot for release 2 or later of the + MIPS32 architecture. + +config CPU_MIPS64_R1 + bool "MIPS64 Release 1" + depends on SUPPORTS_CPU_MIPS64_R1 + select 64BIT + help + Choose this option to build a kernel for release 1 or later of the + MIPS64 architecture. + +config CPU_MIPS64_R2 + bool "MIPS64 Release 2" + depends on SUPPORTS_CPU_MIPS64_R2 + select 64BIT + help + Choose this option to build a kernel for release 2 or later of the + MIPS64 architecture. + +endchoice + +menu "OS boot interface" + +config MIPS_BOOT_CMDLINE_LEGACY + bool "Hand over legacy command line to Linux kernel" + default y + help + Enable this option if you want U-Boot to hand over the Yamon-style + command line to the kernel. All bootargs will be prepared as argc/argv + compatible list. The argument count (argc) is stored in register $a0. + The address of the argument list (argv) is stored in register $a1. + +config MIPS_BOOT_ENV_LEGACY + bool "Hand over legacy environment to Linux kernel" + default y + help + Enable this option if you want U-Boot to hand over the Yamon-style + environment to the kernel. Information like memory size, initrd + address and size will be prepared as zero-terminated key/value list. + The address of the enviroment is stored in register $a2. + +config MIPS_BOOT_FDT + bool "Hand over a flattened device tree to Linux kernel (INCOMPLETE)" + default n + help + Enable this option if you want U-Boot to hand over a flattened + device tree to the kernel. + + Note: the final hand over to the kernel is not yet implemented. After + the community agreed on the MIPS boot interface for device trees, + the corresponding code will be added. + +endmenu + +config SUPPORTS_BIG_ENDIAN + bool + +config SUPPORTS_LITTLE_ENDIAN + bool + +config SUPPORTS_CPU_MIPS32_R1 + bool + +config SUPPORTS_CPU_MIPS32_R2 + bool + +config SUPPORTS_CPU_MIPS64_R1 + bool + +config SUPPORTS_CPU_MIPS64_R2 + bool + +config CPU_MIPS32 + bool + default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 + +config CPU_MIPS64 + bool + default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 + +config 32BIT + bool + +config 64BIT + bool + +config SWAP_IO_SPACE + bool + +config SYS_MIPS_CACHE_INIT_RAM_LOAD + bool + +endif + +endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile new file mode 100644 index 0000000000..43f0f5c504 --- /dev/null +++ b/arch/mips/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/mips/cpu/start.o + +libs-y += arch/mips/cpu/ +libs-y += arch/mips/lib/ + +libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/ diff --git a/arch/mips/config.mk b/arch/mips/config.mk index c3f81b5a18..4dc88f4d51 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -5,25 +5,45 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= mips_4KC- - -# Handle special prefix in ELDK 4.0 toolchain -ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) -ENDIANNESS := -EL +ifdef CONFIG_SYS_BIG_ENDIAN +32bit-emul := elf32btsmip +64bit-emul := elf64btsmip +32bit-bfd := elf32-tradbigmips +64bit-bfd := elf64-tradbigmips +PLATFORM_CPPFLAGS += -EB +PLATFORM_LDFLAGS += -EB endif ifdef CONFIG_SYS_LITTLE_ENDIAN -ENDIANNESS := -EL +32bit-emul := elf32ltsmip +64bit-emul := elf64ltsmip +32bit-bfd := elf32-tradlittlemips +64bit-bfd := elf64-tradlittlemips +PLATFORM_CPPFLAGS += -EL +PLATFORM_LDFLAGS += -EL endif -ifdef CONFIG_SYS_BIG_ENDIAN -ENDIANNESS := -EB +ifdef CONFIG_32BIT +PLATFORM_CPPFLAGS += -mabi=32 +PLATFORM_LDFLAGS += -m $(32bit-emul) +OBJCOPYFLAGS += -O $(32bit-bfd) endif -# Default to EB if no endianess is configured -ENDIANNESS ?= -EB +ifdef CONFIG_64BIT +PLATFORM_CPPFLAGS += -mabi=64 +PLATFORM_LDFLAGS += -m$(64bit-emul) +OBJCOPYFLAGS += -O $(64bit-bfd) +endif + +cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 +cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 +cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 +cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 +PLATFORM_CPPFLAGS += $(cpuflags-y) + +PLATFORM_CPPFLAGS += -D__MIPS__ -PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ +__HAVE_ARCH_GENERIC_BOARD := y # # From Linux arch/mips/Makefile @@ -45,9 +65,10 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS) +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -msoft-float -PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS) +PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections -pie -OBJCFLAGS += --remove-section=.dynsym +OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got +OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile new file mode 100644 index 0000000000..fc6b455c68 --- /dev/null +++ b/arch/mips/cpu/Makefile @@ -0,0 +1,9 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y = start.o + +obj-y += time.o +obj-y += interrupts.o +obj-y += cpu.o diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c new file mode 100644 index 0000000000..8d3b2f5c2b --- /dev/null +++ b/arch/mips/cpu/cpu.c @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +void __weak _machine_restart(void) +{ + fprintf(stderr, "*** reset failed ***\n"); + + while (1) + /* NOP */; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + _machine_restart(); + + return 0; +} + +void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) +{ + write_c0_entrylo0(low0); + write_c0_pagemask(pagemask); + write_c0_entrylo1(low1); + write_c0_entryhi(hi); + write_c0_index(index); + tlb_write_indexed(); +} diff --git a/arch/mips/cpu/interrupts.c b/arch/mips/cpu/interrupts.c new file mode 100644 index 0000000000..275fcf5699 --- /dev/null +++ b/arch/mips/cpu/interrupts.c @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +int interrupt_init(void) +{ + return 0; +} + +void enable_interrupts(void) +{ +} + +int disable_interrupts(void) +{ + return 0; +} diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile deleted file mode 100644 index 1974034dfb..0000000000 --- a/arch/mips/cpu/mips32/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -SOBJS-y = cache.o -COBJS-y = cpu.o interrupts.o time.o - -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/cpu/mips32/au1x00/Makefile deleted file mode 100644 index 4a045e3a91..0000000000 --- a/arch/mips/cpu/mips32/au1x00/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S deleted file mode 100644 index 12f656cad0..0000000000 --- a/arch/mips/cpu/mips32/cache.S +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Cache-handling routined for MIPS CPUs - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - -#define RA t9 - -/* - * 16kB is the maximum size of instruction and data caches on MIPS 4K, - * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. - * - * Note that the above size is the maximum size of primary cache. U-Boot - * doesn't have L2 cache support for now. - */ -#define MIPS_MAX_CACHE_SIZE 0x10000 - -#define INDEX_BASE CKSEG0 - - .macro cache_op op addr - .set push - .set noreorder - .set mips3 - cache \op, 0(\addr) - .set pop - .endm - - .macro f_fill64 dst, offset, val - LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) -#if LONGSIZE == 4 - LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) -#endif - .endm - -/* - * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) - */ -LEAF(mips_init_icache) - blez a1, 9f - mtc0 zero, CP0_TAGLO - /* clear tag to invalidate */ - PTR_LI t0, INDEX_BASE - PTR_ADDU t1, t0, a1 -1: cache_op INDEX_STORE_TAG_I t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b - /* fill once, so data field parity is correct */ - PTR_LI t0, INDEX_BASE -2: cache_op FILL t0 - PTR_ADDU t0, a2 - bne t0, t1, 2b - /* invalidate again - prudent but not strictly neccessary */ - PTR_LI t0, INDEX_BASE -1: cache_op INDEX_STORE_TAG_I t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b -9: jr ra - END(mips_init_icache) - -/* - * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) - */ -LEAF(mips_init_dcache) - blez a1, 9f - mtc0 zero, CP0_TAGLO - /* clear all tags */ - PTR_LI t0, INDEX_BASE - PTR_ADDU t1, t0, a1 -1: cache_op INDEX_STORE_TAG_D t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b - /* load from each line (in cached space) */ - PTR_LI t0, INDEX_BASE -2: LONG_L zero, 0(t0) - PTR_ADDU t0, a2 - bne t0, t1, 2b - /* clear all tags */ - PTR_LI t0, INDEX_BASE -1: cache_op INDEX_STORE_TAG_D t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b -9: jr ra - END(mips_init_dcache) - -/* - * mips_cache_reset - low level initialisation of the primary caches - * - * This routine initialises the primary caches to ensure that they have good - * parity. It must be called by the ROM before any cached locations are used - * to prevent the possibility of data with bad parity being written to memory. - * - * To initialise the instruction cache it is essential that a source of data - * with good parity is available. This routine will initialise an area of - * memory starting at location zero to be used as a source of parity. - * - * RETURNS: N/A - * - */ -NESTED(mips_cache_reset, 0, ra) - move RA, ra - li t2, CONFIG_SYS_ICACHE_SIZE - li t3, CONFIG_SYS_DCACHE_SIZE - li t8, CONFIG_SYS_CACHELINE_SIZE - - li v0, MIPS_MAX_CACHE_SIZE - - /* - * Now clear that much memory starting from zero. - */ - PTR_LI a0, CKSEG1 - PTR_ADDU a1, a0, v0 -2: PTR_ADDIU a0, 64 - f_fill64 a0, -64, zero - bne a0, a1, 2b - - /* - * The caches are probably in an indeterminate state, - * so we force good parity into them by doing an - * invalidate, load/fill, invalidate for each line. - */ - - /* - * Assume bottom of RAM will generate good parity for the cache. - */ - - /* - * Initialize the I-cache first, - */ - move a1, t2 - move a2, t8 - PTR_LA v1, mips_init_icache - jalr v1 - - /* - * then initialize D-cache. - */ - move a1, t3 - move a2, t8 - PTR_LA v1, mips_init_dcache - jalr v1 - - jr RA - END(mips_cache_reset) - -/* - * dcache_status - get cache status - * - * RETURNS: 0 - cache disabled; 1 - cache enabled - * - */ -LEAF(dcache_status) - mfc0 t0, CP0_CONFIG - li t1, CONF_CM_UNCACHED - andi t0, t0, CONF_CM_CMASK - move v0, zero - beq t0, t1, 2f - li v0, 1 -2: jr ra - END(dcache_status) - -/* - * dcache_disable - disable cache - * - * RETURNS: N/A - * - */ -LEAF(dcache_disable) - mfc0 t0, CP0_CONFIG - li t1, -8 - and t0, t0, t1 - ori t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG - jr ra - END(dcache_disable) - -/* - * dcache_enable - enable cache - * - * RETURNS: N/A - * - */ -LEAF(dcache_enable) - mfc0 t0, CP0_CONFIG - ori t0, CONF_CM_CMASK - xori t0, CONF_CM_CMASK - ori t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG - jr ra - END(dcache_enable) diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index 067f871525..4257c56d59 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -5,20 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# -# Default optimization level for MIPS32 -# -# Note: Toolchains with binutils prior to v2.16 -# are no longer supported by U-Boot MIPS tree! -# -MIPSFLAGS := -march=mips32r2 - -PLATFORM_CPPFLAGS += $(MIPSFLAGS) -PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT -ifdef CONFIG_SYS_BIG_ENDIAN -PLATFORM_LDFLAGS += -m elf32btsmip -else -PLATFORM_LDFLAGS += -m elf32ltsmip -endif - -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \ + -T $(srctree)/examples/standalone/mips.lds diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c deleted file mode 100644 index 28d5c45683..0000000000 --- a/arch/mips/cpu/mips32/cpu.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set pop \n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -void __attribute__((weak)) _machine_restart(void) -{ -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - _machine_restart(); - - fprintf(stderr, "*** reset failed ***\n"); - return 0; -} - -void flush_cache(ulong start_addr, ulong size) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - - /* aend will be miscalculated when size is zero, so we return here */ - if (size == 0) - return; - - while (1) { - cache_op(HIT_WRITEBACK_INV_D, addr); - cache_op(HIT_INVALIDATE_I, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void flush_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - while (1) { - cache_op(HIT_WRITEBACK_INV_D, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void invalidate_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - while (1) { - cache_op(HIT_INVALIDATE_D, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) -{ - write_c0_entrylo0(low0); - write_c0_pagemask(pagemask); - write_c0_entrylo1(low1); - write_c0_entryhi(hi); - write_c0_index(index); - tlb_write_indexed(); -} - -int cpu_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SOC_AU1X00 - au1x00_enet_initialize(bis); -#endif - return 0; -} diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile deleted file mode 100644 index 6368d57a88..0000000000 --- a/arch/mips/cpu/mips32/incaip/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS = incaip_wdt.o -COBJS = incaip_clock.o asc_serial.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c deleted file mode 100644 index 6f0e4f2520..0000000000 --- a/arch/mips/cpu/mips32/incaip/asc_serial.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (INCA) ASC UART support - */ - -#include -#include -#include -#include -#include -#include "asc_serial.h" - - -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -extern uint incaip_get_fpiclk(void); - -static int serial_setopt (void); - -/* pointer to ASC register base address */ -static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC; - -/****************************************************************************** -* -* serial_init - initialize a INCAASC channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -static int asc_serial_init(void) -{ - /* we have to set PMU.EN13 bit to enable an ASC device*/ - INCAASC_PMU_ENABLE(13); - - /* and we have to set CLC register*/ - CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); - SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); - - /* initialy we are in async mode */ - pAsc->asc_con = ASCCON_M_8ASYNC; - - /* select input port */ - pAsc->asc_pisel = (CONSOLE_TTY & 0x1); - - /* TXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, - ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); - /* enable TXFIFO */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN); - - /* RXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK, - ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); - /* enable RXFIFO */ - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); - - /* enable error signals */ - SET_BIT(pAsc->asc_con, ASCCON_FEN); - SET_BIT(pAsc->asc_con, ASCCON_OEN); - - /* acknowledge ASC interrupts */ - ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); - - /* disable ASC interrupts */ - ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); - - /* set FIFOs into the transparent mode */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); - - /* set baud rate */ - serial_setbrg(); - - /* set the options */ - serial_setopt(); - - return 0; -} - -static void asc_serial_setbrg(void) -{ - ulong uiReloadValue, fdv; - ulong f_ASC; - - f_ASC = incaip_get_fpiclk(); - -#ifndef INCAASC_USE_FDV - fdv = 2; - uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; -#else - fdv = INCAASC_FDV_HIGH_BAUDRATE; - uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; -#endif /* INCAASC_USE_FDV */ - - if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) - { -#ifndef INCAASC_USE_FDV - fdv = 3; - uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; -#else - fdv = INCAASC_FDV_LOW_BAUDRATE; - uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; -#endif /* INCAASC_USE_FDV */ - - if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) - { - return; /* can't impossibly generate that baud rate */ - } - } - - /* Disable Baud Rate Generator; BG should only be written when R=0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_R); - -#ifndef INCAASC_USE_FDV - /* - * Disable Fractional Divider (FDE) - * Divide clock by reload-value + constant (BRS) - */ - /* FDE = 0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_FDE); - - if ( fdv == 2 ) - CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */ - else - SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */ - -#else /* INCAASC_USE_FDV */ - - /* Enable Fractional Divider */ - SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */ - - /* Set fractional divider value */ - pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK; - -#endif /* INCAASC_USE_FDV */ - - /* Set reload value in BG */ - pAsc->asc_bg = uiReloadValue; - - /* Enable Baud Rate Generator */ - SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */ -} - -/******************************************************************************* -* -* serial_setopt - set the serial options -* -* Set the channel operating mode to that specified. Following options -* are supported: CREAD, CSIZE, PARENB, and PARODD. -* -* Note, this routine disables the transmitter. The calling routine -* may have to re-enable it. -* -* RETURNS: -* Returns 0 to indicate success, otherwise -1 is returned -*/ - -static int serial_setopt (void) -{ - ulong con; - - switch ( ASC_OPTIONS & ASCOPT_CSIZE ) - { - /* 7-bit-data */ - case ASCOPT_CS7: - con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */ - break; - - /* 8-bit-data */ - case ASCOPT_CS8: - if ( ASC_OPTIONS & ASCOPT_PARENB ) - con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */ - else - con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */ - break; - - /* - * only 7 and 8-bit frames are supported - * if we don't use IOCTL extensions - */ - default: - return -1; - } - - if ( ASC_OPTIONS & ASCOPT_STOPB ) - SET_BIT(con, ASCCON_STP); /* 2 stop bits */ - else - CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */ - - if ( ASC_OPTIONS & ASCOPT_PARENB ) - SET_BIT(con, ASCCON_PEN); /* enable parity checking */ - else - CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */ - - if ( ASC_OPTIONS & ASCOPT_PARODD ) - SET_BIT(con, ASCCON_ODD); /* odd parity */ - else - CLEAR_BIT(con, ASCCON_ODD); /* even parity */ - - if ( ASC_OPTIONS & ASCOPT_CREAD ) - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */ - - pAsc->asc_con |= con; - - return 0; -} - -static void asc_serial_putc(const char c) -{ - uint txFl = 0; - - if (c == '\n') serial_putc ('\r'); - - /* check do we have a free space in the TX FIFO */ - /* get current filling level */ - do - { - txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; - } - while ( txFl == INCAASC_TXFIFO_FULL ); - - pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ - - /* check for errors */ - if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - return; - } -} - -static int asc_serial_getc(void) -{ - ulong symbol_mask; - char c; - - while (!serial_tstc()); - - symbol_mask = - ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff); - - c = (char)(pAsc->asc_rbuf & symbol_mask); - - return c; -} - -static int asc_serial_tstc(void) -{ - int res = 1; - - if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) - { - res = 0; - } - else if ( pAsc->asc_con & ASCCON_FE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_PE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - res = 0; - } - - return res; -} - -static struct serial_device asc_serial_drv = { - .name = "asc_serial", - .start = asc_serial_init, - .stop = NULL, - .setbrg = asc_serial_setbrg, - .putc = asc_serial_putc, - .puts = default_serial_puts, - .getc = asc_serial_getc, - .tstc = asc_serial_tstc, -}; - -void asc_serial_initialize(void) -{ - serial_register(&asc_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &asc_serial_drv; -} diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.h b/arch/mips/cpu/mips32/incaip/asc_serial.h deleted file mode 100644 index 7ffdcfaf8b..0000000000 --- a/arch/mips/cpu/mips32/incaip/asc_serial.h +++ /dev/null @@ -1,177 +0,0 @@ -/* incaAscSio.h - (INCA) ASC UART tty driver header */ - -#ifndef __INCincaAscSioh -#define __INCincaAscSioh - -#include - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -/* use fractional divider for baudrate settings */ -#define INCAASC_USE_FDV - -#ifdef INCAASC_USE_FDV - #define INCAASC_FDV_LOW_BAUDRATE 71 - #define INCAASC_FDV_HIGH_BAUDRATE 453 -#endif /*INCAASC_USE_FDV*/ - - -#define INCAASC_TXFIFO_FL 1 -#define INCAASC_RXFIFO_FL 1 -#define INCAASC_TXFIFO_FULL 16 - -/* interrupt lines masks for the ASC device interrupts*/ -/* change these macroses if it's necessary */ -#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ - -#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ -#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ -#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ -#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ - -/* interrupt controller access macros */ -#define ASC_INTERRUPTS_ENABLE(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X; -#define ASC_INTERRUPTS_DISABLE(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X; -#define ASC_INTERRUPTS_CLEAR(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X; - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0007 - #define ASCCON_M_8SYNC 0x0 - #define ASCCON_M_8ASYNC 0x1 - #define ASCCON_M_8IRDAASYNC 0x2 - #define ASCCON_M_7ASYNCPAR 0x3 - #define ASCCON_M_9ASYNC 0x4 - #define ASCCON_M_8WAKEUPASYNC 0x5 - #define ASCCON_M_8ASYNCPAR 0x7 -#define ASCCON_STP 0x0008 -#define ASCCON_REN 0x0010 -#define ASCCON_PEN 0x0020 -#define ASCCON_FEN 0x0040 -#define ASCCON_OEN 0x0080 -#define ASCCON_PE 0x0100 -#define ASCCON_FE 0x0200 -#define ASCCON_OE 0x0400 -#define ASCCON_FDE 0x0800 -#define ASCCON_ODD 0x1000 -#define ASCCON_BRS 0x2000 -#define ASCCON_LB 0x4000 -#define ASCCON_R 0x8000 - -/* WHBCON register's bits and bitfields */ -#define ASCWHBCON_CLRREN 0x0010 -#define ASCWHBCON_SETREN 0x0020 -#define ASCWHBCON_CLRPE 0x0100 -#define ASCWHBCON_CLRFE 0x0200 -#define ASCWHBCON_CLROE 0x0400 -#define ASCWHBCON_SETPE 0x0800 -#define ASCWHBCON_SETFE 0x1000 -#define ASCWHBCON_SETOE 0x2000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 -#define ASCABCON_EMMASK 0x0300 - #define ASCABCON_EMOFF 8 - #define ASCABCON_EM_DISAB 0x0 - #define ASCABCON_EM_DURAB 0x1 - #define ASCABCON_EM_ALWAYS 0x2 -#define ASCABCON_TXINV 0x0400 -#define ASCABCON_RXINV 0x0800 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_SETABEN 0x0001 -#define ASCWHBABCON_CLRABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_SETSCCDET 0x0040 -#define ASCWHBABSTAT_CLRSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXTMEN 0x0004 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXTMEN 0x0004 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT); - -typedef struct /* incaAsc_t */ -{ - volatile unsigned long asc_clc; /*0x0000*/ - volatile unsigned long asc_pisel; /*0x0004*/ - volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/ - volatile unsigned long asc_con; /*0x0010*/ - volatile unsigned long asc_bg; /*0x0014*/ - volatile unsigned long asc_fdv; /*0x0018*/ - volatile unsigned long asc_pmw; /* not used */ /*0x001C*/ - volatile unsigned long asc_tbuf; /*0x0020*/ - volatile unsigned long asc_rbuf; /*0x0024*/ - volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/ - volatile unsigned long asc_abcon; /*0x0030*/ - volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ - volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/ - volatile unsigned long asc_rxfcon; /*0x0040*/ - volatile unsigned long asc_txfcon; /*0x0044*/ - volatile unsigned long asc_fstat; /*0x0048*/ - volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/ - volatile unsigned long asc_whbcon; /*0x0050*/ - volatile unsigned long asc_whbabcon; /*0x0054*/ - volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/ - -} incaAsc_t; - -#endif /* __INCincaAscSioh */ diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk deleted file mode 100644 index 5c89129d8c..0000000000 --- a/arch/mips/cpu/mips32/incaip/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mtune=4kc diff --git a/arch/mips/cpu/mips32/incaip/incaip_clock.c b/arch/mips/cpu/mips32/incaip/incaip_clock.c deleted file mode 100644 index efada9f6f8..0000000000 --- a/arch/mips/cpu/mips32/incaip/incaip_clock.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -/******************************************************************************* -* -* get_cpuclk - returns the frequency of the CPU. -* -* Gets the value directly from the INCA-IP hardware. -* -* RETURNS: -* 150.000.000 for 150 MHz -* 133.333.333 for 133 MHz (= 400MHz/3) -* 100.000.000 for 100 MHz (= 400MHz/4) -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. Don't use the macros, which are set to init the CPU -* frequency in the ROM code. -*/ -uint incaip_get_cpuclk (void) -{ - /*-------------------------------------------------------------------------*/ - /* CPU Clock Input Multiplexer (MUX I) */ - /* Multiplexer MUX I selects the maximum input clock to the CPU. */ - /*-------------------------------------------------------------------------*/ - if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) & - INCA_IP_CGU_CGU_MUXCR_MUXI) { - /* MUX I set to 150 MHz clock */ - return 150000000; - } else { - /* MUX I set to 100/133 MHz clock */ - if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) { - /* Division value is 1/3, maximum CPU operating */ - /* frequency is 133.3 MHz */ - return 133333333; - } else { - /* Division value is 1/4, maximum CPU operating */ - /* frequency is 100 MHz */ - return 100000000; - } - } -} - -/******************************************************************************* -* -* get_fpiclk - returns the frequency of the FPI bus. -* -* Gets the value directly from the INCA-IP hardware. -* -* RETURNS: Frquency in Hz -* -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. Don't use the macros, which are set to init the CPU -* frequency in the ROM code. -* The calculation for the -*/ -uint incaip_get_fpiclk (void) -{ - uint clkCPU; - - clkCPU = incaip_get_cpuclk (); - - switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) { - case 0x4: - return clkCPU >> 1; /* devided by 2 */ - break; - case 0x8: - return clkCPU >> 2; /* devided by 4 */ - break; - default: - return clkCPU; - break; - } -} - -int incaip_set_cpuclk (void) -{ - extern void ebu_init(long); - extern void cgu_init(long); - extern void sdram_init(long); - char tmp[64]; - ulong cpuclk; - - if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) { - cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - cgu_init (cpuclk); - ebu_init (cpuclk); - sdram_init (cpuclk); - } - - return 0; -} diff --git a/arch/mips/cpu/mips32/incaip/incaip_wdt.S b/arch/mips/cpu/mips32/incaip/incaip_wdt.S deleted file mode 100644 index b15320a57c..0000000000 --- a/arch/mips/cpu/mips32/incaip/incaip_wdt.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * INCA-IP Watchdog timer management code. - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include - - -#define WD_BASE 0xb8000000 -#define WD_CON0(value) 0x0020(value) -#define WD_CON1(value) 0x0024(value) -#define WD_DISABLE 0x00000008 -#define WD_ENABLE 0x00000000 -#define WD_WRITE_PW 0xFFFC00F8 -#define WD_WRITE_ENDINIT 0xFFFC00F3 -#define WD_WRITE_INIT 0xFFFC00F2 - - - .globl disable_incaip_wdt -disable_incaip_wdt: - li t0, WD_BASE - - /* Calculate password. - */ - lw t2, WD_CON1(t0) - and t2, 0xC - - lw t3, WD_CON0(t0) - and t3, 0xFFFFFF01 - - or t3, t2 - or t3, 0xF0 - - sw t3, WD_CON0(t0) /* write password */ - - /* Clear ENDINIT. - */ - li t1, WD_WRITE_INIT - sw t1, WD_CON0(t0) - - - li t1, WD_DISABLE - sw t1, WD_CON1(t0) /* disable watchdog */ - li t1, WD_WRITE_PW - sw t1, WD_CON0(t0) /* write password */ - li t1, WD_WRITE_ENDINIT - sw t1, WD_CON0(t0) /* end command */ - - jr ra - nop diff --git a/arch/mips/cpu/mips32/interrupts.c b/arch/mips/cpu/mips32/interrupts.c deleted file mode 100644 index a7e2ed046a..0000000000 --- a/arch/mips/cpu/mips32/interrupts.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S deleted file mode 100644 index 70ad198cc9..0000000000 --- a/arch/mips/cpu/mips32/start.S +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Startup Code for MIPS32 CPU-core - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - - /* - * For the moment disable interrupts, mark the kernel mode and - * set ST0_KX so that the CPU does not spit fire when using - * 64-bit addresses. - */ - .macro setup_c0_status set clr - .set push - mfc0 t0, CP0_STATUS - or t0, ST0_CU0 | \set | 0x1f | \clr - xor t0, 0x1f | \clr - mtc0 t0, CP0_STATUS - .set noreorder - sll zero, 3 # ehb - .set pop - .endm - - .set noreorder - - .globl _start - .text -_start: - /* U-boot entry point */ - b reset - nop - - .org 0x10 -#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) - /* - * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to - * access external NOR flashes. If the board boots from NOR flash the - * internal BootROM does a blind read at address 0xB0000010 to read the - * initial configuration for that EBU in order to access the flash - * device with correct parameters. This config option is board-specific. - */ - .word CONFIG_SYS_XWAY_EBU_BOOTCFG - .word 0x0 -#elif defined(CONFIG_QEMU_MALTA) - /* - * Linux expects the Board ID here. - */ - .word 0x00000420 # 0x420 (Malta Board with CoreLV) - .word 0x00000000 -#endif - - .org 0x200 - /* TLB refill, 32 bit task */ -1: b 1b - nop - - .org 0x280 - /* XTLB refill, 64 bit task */ -1: b 1b - nop - - .org 0x300 - /* Cache error exception */ -1: b 1b - nop - - .org 0x380 - /* General exception */ -1: b 1b - nop - - .org 0x400 - /* Catch interrupt exceptions */ -1: b 1b - nop - - .org 0x480 - /* EJTAG debug exception */ -1: b 1b - nop - - .align 4 -reset: - - /* Clear watch registers */ - mtc0 zero, CP0_WATCHLO - mtc0 zero, CP0_WATCHHI - - /* WP(Watch Pending), SW0/1 should be cleared */ - mtc0 zero, CP0_CAUSE - - setup_c0_status 0 0 - - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - li t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG -#endif - - /* Initialize $gp */ - bal 1f - nop - .word _gp -1: - lw gp, 0(ra) - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* Initialize any external memory */ - la t9, lowlevel_init - jalr t9 - nop - - /* Initialize caches... */ - la t9, mips_cache_reset - jalr t9 - nop - - /* ... and enable them */ - li t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG -#endif - - /* Set up temporary stack */ - li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - - la t9, board_init_f - jr t9 - nop - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 # set new stack pointer - - move s0, a1 # save gd in s0 - move s2, a2 # save destination address in s2 - - li t0, CONFIG_SYS_MONITOR_BASE - sub s1, s2, t0 # s1 <-- relocation offset - - la t3, in_ram - lw t2, -12(t3) # t2 <-- __image_copy_end - move t1, a2 - - add gp, s1 # adjust gp - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -1: - lw t3, 0(t0) - sw t3, 0(t1) - addu t0, 4 - blt t0, t2, 1b - addu t1, 4 - - /* If caches were enabled, we would have to flush them here. */ - sub a1, t1, s2 # a1 <-- size - la t9, flush_cache - jalr t9 - move a0, s2 # a0 <-- destination address - - /* Jump to where we've relocated ourselves */ - addi t0, s2, in_ram - _start - jr t0 - nop - - .word __rel_dyn_end - .word __rel_dyn_start - .word __image_copy_end - .word _GLOBAL_OFFSET_TABLE_ - .word num_got_entries - -in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. - */ - lw t3, -4(t0) # t3 <-- num_got_entries - lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - add t8, s1 # t8 now holds relocated _G_O_T_ - addi t8, t8, 8 # skipping first two entries - li t2, 2 -1: - lw t1, 0(t8) - beqz t1, 2f - add t1, s1 - sw t1, 0(t8) -2: - addi t2, 1 - blt t2, t3, 1b - addi t8, 4 - - /* Update dynamic relocations */ - lw t1, -16(t0) # t1 <-- __rel_dyn_start - lw t2, -20(t0) # t2 <-- __rel_dyn_end - - b 2f # skip first reserved entry - addi t1, 8 - -1: - lw t8, -4(t1) # t8 <-- relocation info - - li t3, 3 - bne t8, t3, 2f # skip non R_MIPS_REL32 entries - nop - - lw t3, -8(t1) # t3 <-- location to fix up in FLASH - - lw t8, 0(t3) # t8 <-- original pointer - add t8, s1 # t8 <-- adjusted pointer - - add t3, s1 # t3 <-- location to fix up in RAM - sw t8, 0(t3) - -2: - blt t1, t2, 1b - addi t1, 8 # each rel.dyn entry is 8 bytes - - /* - * Clear BSS - * - * GOT is now relocated. Thus __bss_start and __bss_end can be - * accessed directly via $gp. - */ - la t1, __bss_start # t1 <-- __bss_start - la t2, __bss_end # t2 <-- __bss_end - -1: - sw zero, 0(t1) - blt t1, t2, 1b - addi t1, 4 - - move a0, s0 # a0 <-- gd - la t9, board_init_r - jr t9 - move a1, s2 - - .end relocate_code diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c deleted file mode 100644 index 386f45a1b0..0000000000 --- a/arch/mips/cpu/mips32/time.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -static unsigned long timestamp; - -/* how many counter cycles in a jiffy */ -#define CYCLES_PER_JIFFY \ - (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ - -/* - * timer without interrupts - */ - -int timer_init(void) -{ - /* Set up the timer for the first expiration. */ - write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); - - return 0; -} - -ulong get_timer(ulong base) -{ - unsigned int count; - unsigned int expirelo = read_c0_compare(); - - /* Check to see if we have missed any timestamps. */ - count = read_c0_count(); - while ((count - expirelo) < 0x7fffffff) { - expirelo += CYCLES_PER_JIFFY; - timestamp++; - } - write_c0_compare(expirelo); - - return timestamp - base; -} - -void __udelay(unsigned long usec) -{ - unsigned int tmo; - - tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000)); - while ((tmo - read_c0_count()) < 0x7fffffff) - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile deleted file mode 100644 index b4adb950a2..0000000000 --- a/arch/mips/cpu/mips64/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS-y = cpu.o interrupts.o time.o cache.o - -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S deleted file mode 100644 index 36d868818a..0000000000 --- a/arch/mips/cpu/mips64/cache.S +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Cache-handling routined for MIPS CPUs - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#define RA t9 - -/* - * 16kB is the maximum size of instruction and data caches on MIPS 4K, - * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. - * - * Note that the above size is the maximum size of primary cache. U-Boot - * doesn't have L2 cache support for now. - */ -#define MIPS_MAX_CACHE_SIZE 0x10000 - -#define INDEX_BASE CKSEG0 - - .macro cache_op op addr - .set push - .set noreorder - .set mips3 - cache \op, 0(\addr) - .set pop - .endm - - .macro f_fill64 dst, offset, val - LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) -#if LONGSIZE == 4 - LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) -#endif - .endm - -/* - * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) - */ -LEAF(mips_init_icache) - blez a1, 9f - mtc0 zero, CP0_TAGLO - /* clear tag to invalidate */ - PTR_LI t0, INDEX_BASE - PTR_ADDU t1, t0, a1 -1: cache_op INDEX_STORE_TAG_I t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b - /* fill once, so data field parity is correct */ - PTR_LI t0, INDEX_BASE -2: cache_op FILL t0 - PTR_ADDU t0, a2 - bne t0, t1, 2b - /* invalidate again - prudent but not strictly neccessary */ - PTR_LI t0, INDEX_BASE -1: cache_op INDEX_STORE_TAG_I t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b -9: jr ra - END(mips_init_icache) - -/* - * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) - */ -LEAF(mips_init_dcache) - blez a1, 9f - mtc0 zero, CP0_TAGLO - /* clear all tags */ - PTR_LI t0, INDEX_BASE - PTR_ADDU t1, t0, a1 -1: cache_op INDEX_STORE_TAG_D t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b - /* load from each line (in cached space) */ - PTR_LI t0, INDEX_BASE -2: LONG_L zero, 0(t0) - PTR_ADDU t0, a2 - bne t0, t1, 2b - /* clear all tags */ - PTR_LI t0, INDEX_BASE -1: cache_op INDEX_STORE_TAG_D t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b -9: jr ra - END(mips_init_dcache) - -/* - * mips_cache_reset - low level initialisation of the primary caches - * - * This routine initialises the primary caches to ensure that they have good - * parity. It must be called by the ROM before any cached locations are used - * to prevent the possibility of data with bad parity being written to memory. - * - * To initialise the instruction cache it is essential that a source of data - * with good parity is available. This routine will initialise an area of - * memory starting at location zero to be used as a source of parity. - * - * RETURNS: N/A - * - */ -NESTED(mips_cache_reset, 0, ra) - move RA, ra - li t2, CONFIG_SYS_ICACHE_SIZE - li t3, CONFIG_SYS_DCACHE_SIZE - li t8, CONFIG_SYS_CACHELINE_SIZE - - li v0, MIPS_MAX_CACHE_SIZE - - /* - * Now clear that much memory starting from zero. - */ - PTR_LI a0, CKSEG1 - PTR_ADDU a1, a0, v0 -2: PTR_ADDIU a0, 64 - f_fill64 a0, -64, zero - bne a0, a1, 2b - - /* - * The caches are probably in an indeterminate state, - * so we force good parity into them by doing an - * invalidate, load/fill, invalidate for each line. - */ - - /* - * Assume bottom of RAM will generate good parity for the cache. - */ - - /* - * Initialize the I-cache first, - */ - move a1, t2 - move a2, t8 - PTR_LA v1, mips_init_icache - jalr v1 - - /* - * then initialize D-cache. - */ - move a1, t3 - move a2, t8 - PTR_LA v1, mips_init_dcache - jalr v1 - - jr RA - END(mips_cache_reset) - -/* - * dcache_status - get cache status - * - * RETURNS: 0 - cache disabled; 1 - cache enabled - * - */ -LEAF(dcache_status) - mfc0 t0, CP0_CONFIG - li t1, CONF_CM_UNCACHED - andi t0, t0, CONF_CM_CMASK - move v0, zero - beq t0, t1, 2f - li v0, 1 -2: jr ra - END(dcache_status) - -/* - * dcache_disable - disable cache - * - * RETURNS: N/A - * - */ -LEAF(dcache_disable) - mfc0 t0, CP0_CONFIG - li t1, -8 - and t0, t0, t1 - ori t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG - jr ra - END(dcache_disable) - -/* - * dcache_enable - enable cache - * - * RETURNS: N/A - * - */ -LEAF(dcache_enable) - mfc0 t0, CP0_CONFIG - ori t0, CONF_CM_CMASK - xori t0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT - mtc0 t0, CP0_CONFIG - jr ra - END(dcache_enable) diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk index d1a8b2c7aa..96eb82948d 100644 --- a/arch/mips/cpu/mips64/config.mk +++ b/arch/mips/cpu/mips64/config.mk @@ -5,20 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# -# Default optimization level for MIPS64 -# -# Note: Toolchains with binutils prior to v2.16 -# are no longer supported by U-Boot MIPS tree! -# -MIPSFLAGS = -march=mips64 - -PLATFORM_CPPFLAGS += $(MIPSFLAGS) -PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT -ifdef CONFIG_SYS_BIG_ENDIAN -PLATFORM_LDFLAGS += -m elf64btsmip -else -PLATFORM_LDFLAGS += -m elf64ltsmip -endif - -CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \ + -T $(srctree)/examples/standalone/mips64.lds diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c deleted file mode 100644 index 9f45cfca5d..0000000000 --- a/arch/mips/cpu/mips64/cpu.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - " .set push\n" \ - " .set noreorder\n" \ - " .set mips64\n" \ - " cache %0, %1\n" \ - " .set pop\n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -void __attribute__((weak)) _machine_restart(void) -{ - fprintf(stderr, "*** reset failed ***\n"); - - while (1) - /* NOP */; -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - _machine_restart(); - - return 0; -} - -void flush_cache(ulong start_addr, ulong size) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - - /* aend will be miscalculated when size is zero, so we return here */ - if (size == 0) - return; - - while (1) { - cache_op(HIT_WRITEBACK_INV_D, addr); - cache_op(HIT_INVALIDATE_I, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void flush_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - while (1) { - cache_op(HIT_WRITEBACK_INV_D, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void invalidate_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - while (1) { - cache_op(HIT_INVALIDATE_D, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) -{ - write_c0_entrylo0(low0); - write_c0_pagemask(pagemask); - write_c0_entrylo1(low1); - write_c0_entryhi(hi); - write_c0_index(index); - tlb_write_indexed(); -} diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c deleted file mode 100644 index a7e2ed046a..0000000000 --- a/arch/mips/cpu/mips64/interrupts.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S deleted file mode 100644 index 92954e1c90..0000000000 --- a/arch/mips/cpu/mips64/start.S +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Startup Code for MIPS64 CPU-core - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - -#ifdef CONFIG_SYS_LITTLE_ENDIAN -#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) -#else -#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) -#endif - - /* - * For the moment disable interrupts, mark the kernel mode and - * set ST0_KX so that the CPU does not spit fire when using - * 64-bit addresses. - */ - .macro setup_c0_status set clr - .set push - mfc0 t0, CP0_STATUS - or t0, ST0_CU0 | \set | 0x1f | \clr - xor t0, 0x1f | \clr - mtc0 t0, CP0_STATUS - .set noreorder - sll zero, 3 # ehb - .set pop - .endm - - .set noreorder - - .globl _start - .text -_start: - /* U-boot entry point */ - b reset - nop - - .org 0x200 - /* TLB refill, 32 bit task */ -1: b 1b - nop - - .org 0x280 - /* XTLB refill, 64 bit task */ -1: b 1b - nop - - .org 0x300 - /* Cache error exception */ -1: b 1b - nop - - .org 0x380 - /* General exception */ -1: b 1b - nop - - .org 0x400 - /* Catch interrupt exceptions */ -1: b 1b - nop - - .org 0x480 - /* EJTAG debug exception */ -1: b 1b - nop - - .align 4 -reset: - - /* Clear watch registers */ - dmtc0 zero, CP0_WATCHLO - dmtc0 zero, CP0_WATCHHI - - /* WP(Watch Pending), SW0/1 should be cleared */ - mtc0 zero, CP0_CAUSE - - setup_c0_status ST0_KX 0 - - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - dli t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG -#endif - - /* - * Initialize $gp, force 8 byte alignment of bal instruction to forbid - * the compiler to put nop's between bal and _gp. This is required to - * keep _gp and ra aligned to 8 byte. - */ - .align 3 - bal 1f - nop - .dword _gp -1: - ld gp, 0(ra) - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* Initialize any external memory */ - dla t9, lowlevel_init - jalr t9 - nop - - /* Initialize caches... */ - dla t9, mips_cache_reset - jalr t9 - nop - - /* ... and enable them */ - dli t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG -#endif - - /* Set up temporary stack */ - dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - - dla t9, board_init_f - jr t9 - nop - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 # set new stack pointer - - move s0, a1 # save gd in s0 - move s2, a2 # save destination address in s2 - - dli t0, CONFIG_SYS_MONITOR_BASE - dsub s1, s2, t0 # s1 <-- relocation offset - - dla t3, in_ram - ld t2, -24(t3) # t2 <-- __image_copy_end - move t1, a2 - - dadd gp, s1 # adjust gp - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -1: - lw t3, 0(t0) - sw t3, 0(t1) - daddu t0, 4 - blt t0, t2, 1b - daddu t1, 4 - - /* If caches were enabled, we would have to flush them here. */ - dsub a1, t1, s2 # a1 <-- size - dla t9, flush_cache - jalr t9 - move a0, s2 # a0 <-- destination address - - /* Jump to where we've relocated ourselves */ - daddi t0, s2, in_ram - _start - jr t0 - nop - - .dword __rel_dyn_end - .dword __rel_dyn_start - .dword __image_copy_end - .dword _GLOBAL_OFFSET_TABLE_ - .dword num_got_entries - -in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. - */ - ld t3, -8(t0) # t3 <-- num_got_entries - ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - dadd t8, s1 # t8 now holds relocated _G_O_T_ - daddi t8, t8, 16 # skipping first two entries - dli t2, 2 -1: - ld t1, 0(t8) - beqz t1, 2f - dadd t1, s1 - sd t1, 0(t8) -2: - daddi t2, 1 - blt t2, t3, 1b - daddi t8, 8 - - /* Update dynamic relocations */ - ld t1, -32(t0) # t1 <-- __rel_dyn_start - ld t2, -40(t0) # t2 <-- __rel_dyn_end - - b 2f # skip first reserved entry - daddi t1, 16 - -1: - lw t8, -4(t1) # t8 <-- relocation info - - dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) - bne t8, t3, 2f # skip non R_MIPS_REL32 entries - nop - - ld t3, -16(t1) # t3 <-- location to fix up in FLASH - - ld t8, 0(t3) # t8 <-- original pointer - dadd t8, s1 # t8 <-- adjusted pointer - - dadd t3, s1 # t3 <-- location to fix up in RAM - sd t8, 0(t3) - -2: - blt t1, t2, 1b - daddi t1, 16 # each rel.dyn entry is 16 bytes - - /* - * Clear BSS - * - * GOT is now relocated. Thus __bss_start and __bss_end can be - * accessed directly via $gp. - */ - dla t1, __bss_start # t1 <-- __bss_start - dla t2, __bss_end # t2 <-- __bss_end - -1: - sd zero, 0(t1) - blt t1, t2, 1b - daddi t1, 8 - - move a0, s0 # a0 <-- gd - dla t9, board_init_r - jr t9 - move a1, s2 - - .end relocate_code diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c deleted file mode 100644 index 0497acf4a1..0000000000 --- a/arch/mips/cpu/mips64/time.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -static unsigned long timestamp; - -/* how many counter cycles in a jiffy */ -#define CYCLES_PER_JIFFY \ - (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ - -/* - * timer without interrupts - */ - -int timer_init(void) -{ - /* Set up the timer for the first expiration. */ - write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); - - return 0; -} - -ulong get_timer(ulong base) -{ - unsigned int count; - unsigned int expirelo = read_c0_compare(); - - /* Check to see if we have missed any timestamps. */ - count = read_c0_count(); - while ((count - expirelo) < 0x7fffffff) { - expirelo += CYCLES_PER_JIFFY; - timestamp++; - } - write_c0_compare(expirelo); - - return timestamp - base; -} - -void __udelay(unsigned long usec) -{ - unsigned int tmo; - - tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000)); - while ((tmo - read_c0_count()) < 0x7fffffff) - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S new file mode 100644 index 0000000000..3b5b622abe --- /dev/null +++ b/arch/mips/cpu/start.S @@ -0,0 +1,320 @@ +/* + * Startup Code for MIPS32 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + +#ifndef CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_SP_OFFSET) +#endif + +#ifdef CONFIG_32BIT +# define MIPS_RELOC 3 +# define STATUS_SET 0 +#endif + +#ifdef CONFIG_64BIT +# ifdef CONFIG_SYS_LITTLE_ENDIAN +# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ + (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) +# else +# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ + ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) +# endif +# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) +# define STATUS_SET ST0_KX +#endif + + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .set noreorder + + .globl _start + .text +_start: + /* U-boot entry point */ + b reset + nop + + .org 0x10 +#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) + /* + * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to + * access external NOR flashes. If the board boots from NOR flash the + * internal BootROM does a blind read at address 0xB0000010 to read the + * initial configuration for that EBU in order to access the flash + * device with correct parameters. This config option is board-specific. + */ + .word CONFIG_SYS_XWAY_EBU_BOOTCFG + .word 0x0 +#elif defined(CONFIG_MALTA) + /* + * Linux expects the Board ID here. + */ + .word 0x00000420 # 0x420 (Malta Board with CoreLV) + .word 0x00000000 +#endif + + .org 0x200 + /* TLB refill, 32 bit task */ +1: b 1b + nop + + .org 0x280 + /* XTLB refill, 64 bit task */ +1: b 1b + nop + + .org 0x300 + /* Cache error exception */ +1: b 1b + nop + + .org 0x380 + /* General exception */ +1: b 1b + nop + + .org 0x400 + /* Catch interrupt exceptions */ +1: b 1b + nop + + .org 0x480 + /* EJTAG debug exception */ +1: b 1b + nop + + .align 4 +reset: + + /* Clear watch registers */ + MTC0 zero, CP0_WATCHLO + MTC0 zero, CP0_WATCHHI + + /* WP(Watch Pending), SW0/1 should be cleared */ + mtc0 zero, CP0_CAUSE + + setup_c0_status STATUS_SET 0 + + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* CONFIG0 register */ + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG +#endif + + /* + * Initialize $gp, force pointer sized alignment of bal instruction to + * forbid the compiler to put nop's between bal and _gp. This is + * required to keep _gp and ra aligned to 8 byte. + */ + .align PTRLOG + bal 1f + nop + PTR _gp +1: + PTR_L gp, 0(ra) + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* Initialize any external memory */ + PTR_LA t9, lowlevel_init + jalr t9 + nop + + /* Initialize caches... */ + PTR_LA t9, mips_cache_reset + jalr t9 + nop + + /* ... and enable them */ + li t0, CONFIG_SYS_MIPS_CACHE_MODE + mtc0 t0, CP0_CONFIG +#endif + + /* Set up temporary stack */ + PTR_LI t0, -16 + PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR + and sp, t1, t0 # force 16 byte alignment + PTR_SUB sp, sp, GD_SIZE # reserve space for gd + and sp, sp, t0 # force 16 byte alignment + move k0, sp # save gd pointer +#ifdef CONFIG_SYS_MALLOC_F_LEN + PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN + PTR_SUB sp, sp, t2 # reserve space for early malloc + and sp, sp, t0 # force 16 byte alignment +#endif + move fp, sp + + /* Clear gd */ + move t0, k0 +1: + sw zero, 0(t0) + blt t0, t1, 1b + PTR_ADDI t0, 4 + +#ifdef CONFIG_SYS_MALLOC_F_LEN + PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset + sw sp, 0(t0) +#endif + + PTR_LA t9, board_init_f + jr t9 + move ra, zero + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a0 = addr_sp + * a1 = gd + * a2 = destination address + */ + .globl relocate_code + .ent relocate_code +relocate_code: + move sp, a0 # set new stack pointer + move fp, sp + + move s0, a1 # save gd in s0 + move s2, a2 # save destination address in s2 + + PTR_LI t0, CONFIG_SYS_MONITOR_BASE + PTR_SUB s1, s2, t0 # s1 <-- relocation offset + + PTR_LA t3, in_ram + PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end + move t1, a2 + + PTR_ADD gp, s1 # adjust gp + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ +1: + lw t3, 0(t0) + sw t3, 0(t1) + PTR_ADDU t0, 4 + blt t0, t2, 1b + PTR_ADDU t1, 4 + + /* If caches were enabled, we would have to flush them here. */ + PTR_SUB a1, t1, s2 # a1 <-- size + PTR_LA t9, flush_cache + jalr t9 + move a0, s2 # a0 <-- destination address + + /* Jump to where we've relocated ourselves */ + PTR_ADDI t0, s2, in_ram - _start + jr t0 + nop + + PTR __rel_dyn_end + PTR __rel_dyn_start + PTR __image_copy_end + PTR _GLOBAL_OFFSET_TABLE_ + PTR num_got_entries + +in_ram: + /* + * Now we want to update GOT. + * + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object + * generated by GNU ld. Skip these reserved entries from relocation. + */ + PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries + PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_ + PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries + PTR_LI t2, 2 +1: + PTR_L t1, 0(t8) + beqz t1, 2f + PTR_ADD t1, s1 + PTR_S t1, 0(t8) +2: + PTR_ADDI t2, 1 + blt t2, t3, 1b + PTR_ADDI t8, PTRSIZE + + /* Update dynamic relocations */ + PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start + PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end + + b 2f # skip first reserved entry + PTR_ADDI t1, 2 * PTRSIZE + +1: + lw t8, -4(t1) # t8 <-- relocation info + + PTR_LI t3, MIPS_RELOC + bne t8, t3, 2f # skip non-MIPS_RELOC entries + nop + + PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH + + PTR_L t8, 0(t3) # t8 <-- original pointer + PTR_ADD t8, s1 # t8 <-- adjusted pointer + + PTR_ADD t3, s1 # t3 <-- location to fix up in RAM + PTR_S t8, 0(t3) + +2: + blt t1, t2, 1b + PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes + + /* + * Clear BSS + * + * GOT is now relocated. Thus __bss_start and __bss_end can be + * accessed directly via $gp. + */ + PTR_LA t1, __bss_start # t1 <-- __bss_start + PTR_LA t2, __bss_end # t2 <-- __bss_end + +1: + PTR_S zero, 0(t1) + blt t1, t2, 1b + PTR_ADDI t1, PTRSIZE + + move a0, s0 # a0 <-- gd + move a1, s2 + PTR_LA t9, board_init_r + jr t9 + move ra, zero + + .end relocate_code diff --git a/arch/mips/cpu/time.c b/arch/mips/cpu/time.c new file mode 100644 index 0000000000..553da5f4ba --- /dev/null +++ b/arch/mips/cpu/time.c @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +unsigned long notrace timer_read_counter(void) +{ + return read_c0_count(); +} + +ulong notrace get_tbclk(void) +{ + return CONFIG_SYS_MIPS_TIMER_FREQ; +} diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index 16a9d6ac57..7d71c11ae4 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -53,6 +53,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; + __init_end = .; .rel.dyn : { __rel_dyn_start = .; @@ -60,7 +61,7 @@ SECTIONS __rel_dyn_end = .; } - .deadcode : { + .padding : { /* * Workaround for a binutils feature (or bug?). * @@ -75,12 +76,10 @@ SECTIONS * * Create a small section here to avoid that. */ - LONG(0xffffffff); + LONG(0xFFFFFFFF) } - .dynsym : { - *(.dynsym) - } + _end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; @@ -91,15 +90,39 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { + .dynsym _end : { + *(.dynsym) + } + + .dynbss : { *(.dynbss) + } + + .dynstr : { *(.dynstr) + } + + .dynamic : { *(.dynamic) + } + + .plt : { + *(.plt) + } + + .interp : { *(.interp) + } + + .gnu : { + *(.gnu*) + } + + .MIPS.stubs : { + *(.MIPS.stubs) + } + + .hash : { *(.hash) - *(.gnu.*) - *(.plt) - *(.got.plt) - *(.rel.plt) } } diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile deleted file mode 100644 index bf58e046b1..0000000000 --- a/arch/mips/cpu/xburst/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# Copyright (C) 2011 Xiangfu Liu -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -SOBJS-y = -COBJS-y = cpu.o timer.o jz_serial.o - -COBJS-$(CONFIG_JZ4740) += jz4740.o - -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk deleted file mode 100644 index d81da21017..0000000000 --- a/arch/mips/cpu/xburst/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (C) 2011 Xiangfu Liu -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=mips32 -PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT -ifdef CONFIG_SYS_BIG_ENDIAN -PLATFORM_LDFLAGS += -m elf32btsmip -else -PLATFORM_LDFLAGS += -m elf32ltsmip -endif - -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c deleted file mode 100644 index 1fdaa32bb0..0000000000 --- a/arch/mips/cpu/xburst/cpu.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * (C) Copyright 2011 - * Xiangfu Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - ".set push\n" \ - ".set noreorder\n" \ - ".set mips3\n" \ - "cache %0, %1\n" \ - ".set pop\n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -void __attribute__((weak)) _machine_restart(void) -{ - struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE; - struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE; - u16 tmp; - - /* wdt_select_extalclk() */ - tmp = readw(&wdt->tcsr); - tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN); - tmp |= WDT_TCSR_EXT_EN; - writew(tmp, &wdt->tcsr); - - /* wdt_select_clk_div64() */ - tmp = readw(&wdt->tcsr); - tmp &= ~WDT_TCSR_PRESCALE_MASK; - tmp |= WDT_TCSR_PRESCALE64, - writew(tmp, &wdt->tcsr); - - writew(100, &wdt->tdr); /* wdt_set_data(100) */ - writew(0, &wdt->tcnt); /* wdt_set_count(0); */ - writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ - writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */ - - while (1) - ; -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - _machine_restart(); - - fprintf(stderr, "*** reset failed ***\n"); - return 0; -} - -void flush_cache(ulong start_addr, ulong size) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - - for (; addr <= aend; addr += lsize) { - cache_op(HIT_WRITEBACK_INV_D, addr); - cache_op(HIT_INVALIDATE_I, addr); - } -} - -void flush_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - for (; addr <= aend; addr += lsize) - cache_op(HIT_WRITEBACK_INV_D, addr); -} - -void invalidate_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - for (; addr <= aend; addr += lsize) - cache_op(HIT_INVALIDATE_D, addr); -} - -void flush_icache_all(void) -{ - u32 addr, t = 0; - - __asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */ - __asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - cache_op(INDEX_STORE_TAG_I, addr); - } - - /* invalidate btb */ - __asm__ __volatile__( - ".set mips32\n\t" - "mfc0 %0, $16, 7\n\t" - "nop\n\t" - "ori %0,2\n\t" - "mtc0 %0, $16, 7\n\t" - ".set mips2\n\t" - : - : "r" (t)); -} - -void flush_dcache_all(void) -{ - u32 addr; - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - cache_op(INDEX_WRITEBACK_INV_D, addr); - } - - __asm__ __volatile__("sync"); -} - -void flush_cache_all(void) -{ - flush_dcache_all(); - flush_icache_all(); -} diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c deleted file mode 100644 index 30f35bde7a..0000000000 --- a/arch/mips/cpu/xburst/jz4740.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Jz4740 common routines - * Copyright (c) 2006 Ingenic Semiconductor, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} - -/* - * PLL output clock = EXTAL * NF / (NR * NO) - * NF = FD + 2, NR = RD + 2 - * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3) - */ -void pll_init(void) -{ - struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE; - - register unsigned int cfcr, plcr1; - int n2FR[33] = { - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, - 9 - }; - int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */ - int nf, pllout2; - - cfcr = CPM_CPCCR_CLKOEN | - CPM_CPCCR_PCS | - (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | - (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | - (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | - (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | - (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT); - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? - CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); - - /* Init USB Host clock, pllout2 must be n*48MHz */ - writel(pllout2 / 48000000 - 1, &cpm->uhccdr); - - nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - /* init PLL */ - writel(cfcr, &cpm->cpccr); - writel(plcr1, &cpm->cppcr); -} - -void sdram_init(void) -{ - struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE; - - register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - cpu_clk = CONFIG_SYS_CPU_SPEED; - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; - - writel(0, &emc->bcr); /* Disable bus release */ - writew(0, &emc->rtcsr); /* Disable clock for counting */ - - /* Fault DMCR value for mode register setting*/ -#define SDRAM_ROW0 11 -#define SDRAM_COL0 8 -#define SDRAM_BANK40 0 - - dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) | - ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) | - (SDRAM_BANK40 << EMC_DMCR_BA_BIT) | - (SDRAM_BW16 << EMC_DMCR_BW_BIT) | - EMC_DMCR_EPIN | - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* Basic DMCR value */ - dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) | - ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) | - (SDRAM_BANK4 << EMC_DMCR_BA_BIT) | - (SDRAM_BW16 << EMC_DMCR_BW_BIT) | - EMC_DMCR_EPIN | - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* SDRAM timimg */ - ns = 1000000000 / mem_clk; - tmp = SDRAM_TRAS / ns; - if (tmp < 4) - tmp = 4; - if (tmp > 11) - tmp = 11; - dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT; - tmp = SDRAM_RCD / ns; - - if (tmp > 3) - tmp = 3; - dmcr |= tmp << EMC_DMCR_RCD_BIT; - tmp = SDRAM_TPC / ns; - - if (tmp > 7) - tmp = 7; - dmcr |= tmp << EMC_DMCR_TPC_BIT; - tmp = SDRAM_TRWL / ns; - - if (tmp > 3) - tmp = 3; - dmcr |= tmp << EMC_DMCR_TRWL_BIT; - tmp = (SDRAM_TRAS + SDRAM_TPC) / ns; - - if (tmp > 14) - tmp = 14; - dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT; - - /* SDRAM mode value */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ - writel(dmcr, &emc->dmcr); - writeb(0, JZ4740_EMC_SDMR0 | sdmode); - - /* Wait for precharge, > 200us */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--) - ; - - /* Stage 2. Enable auto-refresh */ - writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr); - - tmp = SDRAM_TREF / ns; - tmp = tmp / 64 + 1; - if (tmp > 0xff) - tmp = 0xff; - writew(tmp, &emc->rtcor); - writew(0, &emc->rtcnt); - /* Divisor is 64, CKO/64 */ - writew(EMC_RTCSR_CKS_64, &emc->rtcsr); - - /* Wait for number of auto-refresh cycles */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--) - ; - - /* Stage 3. Mode Register Set */ - writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr); - writeb(0, JZ4740_EMC_SDMR0 | sdmode); - - /* Set back to basic DMCR value */ - writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr); - - /* everything is ok now */ -} - -DECLARE_GLOBAL_DATA_PTR; - -void calc_clocks(void) -{ - unsigned int pllout; - unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - pllout = __cpm_get_pllout(); - - gd->cpu_clk = pllout / div[__cpm_get_cdiv()]; - gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()]; - gd->arch.per_clk = pllout / div[__cpm_get_pdiv()]; - gd->mem_clk = pllout / div[__cpm_get_mdiv()]; - gd->arch.dev_clk = CONFIG_SYS_EXTAL; -} - -void rtc_init(void) -{ - struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE; - - while (!(readl(&rtc->rcr) & RTC_RCR_WRDY)) - ; - writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */ - - while (!(readl(&rtc->rcr) & RTC_RCR_WRDY)) - ; - writel(0x00007fff, &rtc->rgr); /* type value */ - - while (!(readl(&rtc->rcr) & RTC_RCR_WRDY)) - ; - writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */ - - while (!(readl(&rtc->rcr) & RTC_RCR_WRDY)) - ; - writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */ -} - -/* U-Boot common routines */ -phys_size_t initdram(int board_type) -{ - struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE; - u32 dmcr; - u32 rows, cols, dw, banks; - ulong size; - - dmcr = readl(&emc->dmcr); - rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); - cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; - - size = (1 << (rows + cols)) * dw * banks; - - return size; -} diff --git a/arch/mips/cpu/xburst/jz_serial.c b/arch/mips/cpu/xburst/jz_serial.c deleted file mode 100644 index 9184223794..0000000000 --- a/arch/mips/cpu/xburst/jz_serial.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Jz4740 UART support - * Copyright (c) 2011 - * Qi Hardware, Xiangfu Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -/* - * serial_init - initialize a channel - * - * This routine initializes the number of data bits, parity - * and set the selected baud rate. Interrupts are disabled. - * Set the modem control signals if the option is selected. - * - * RETURNS: N/A - */ -struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE; - -static int jz_serial_init(void) -{ - /* Disable port interrupts while changing hardware */ - writeb(0, &uart->dlhr_ier); - - /* Disable UART unit function */ - writeb(~UART_FCR_UUE, &uart->iir_fcr); - - /* Set both receiver and transmitter in UART mode (not SIR) */ - writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr); - - /* - * Set databits, stopbits and parity. - * (8-bit data, 1 stopbit, no parity) - */ - writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr); - - /* Set baud rate */ - serial_setbrg(); - - /* Enable UART unit, enable and clear FIFO */ - writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS, - &uart->iir_fcr); - - return 0; -} - -static void jz_serial_setbrg(void) -{ - u32 baud_div, tmp; - - baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE; - - tmp = readb(&uart->lcr); - tmp |= UART_LCR_DLAB; - writeb(tmp, &uart->lcr); - - writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier); - writeb(baud_div & 0xff, &uart->rbr_thr_dllr); - - tmp &= ~UART_LCR_DLAB; - writeb(tmp, &uart->lcr); -} - -static int jz_serial_tstc(void) -{ - if (readb(&uart->lsr) & UART_LSR_DR) - return 1; - - return 0; -} - -static void jz_serial_putc(const char c) -{ - if (c == '\n') - serial_putc('\r'); - - /* Wait for fifo to shift out some bytes */ - while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60)) - ; - - writeb((u8)c, &uart->rbr_thr_dllr); -} - -static int jz_serial_getc(void) -{ - while (!serial_tstc()) - ; - - return readb(&uart->rbr_thr_dllr); -} - -static struct serial_device jz_serial_drv = { - .name = "jz_serial", - .start = jz_serial_init, - .stop = NULL, - .setbrg = jz_serial_setbrg, - .putc = jz_serial_putc, - .puts = default_serial_puts, - .getc = jz_serial_getc, - .tstc = jz_serial_tstc, -}; - -void jz_serial_initialize(void) -{ - serial_register(&jz_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &jz_serial_drv; -} diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S deleted file mode 100644 index 10dffb4a5c..0000000000 --- a/arch/mips/cpu/xburst/start.S +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Startup Code for MIPS32 XBURST CPU-core - * - * Copyright (c) 2010 Xiangfu Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - - .set noreorder - - .globl _start - .text -_start: - /* Initialize $gp */ - bal 1f - nop - .word _gp -1: - lw gp, 0(ra) - - /* Set up temporary stack */ - li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - - la t9, board_init_f - jr t9 - nop - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 # set new stack pointer - - move s0, a1 # save gd in s0 - move s2, a2 # save destination address in s2 - - li t0, CONFIG_SYS_MONITOR_BASE - sub s1, s2, t0 # s1 <-- relocation offset - - la t3, in_ram - lw t2, -12(t3) # t2 <-- __image_copy_end - move t1, a2 - - add gp, s1 # adjust gp - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -1: - lw t3, 0(t0) - sw t3, 0(t1) - addu t0, 4 - blt t0, t2, 1b - addu t1, 4 - - /* If caches were enabled, we would have to flush them here. */ - - /* flush d-cache */ - li t0, KSEG0 - addi t1, t0, CONFIG_SYS_DCACHE_SIZE -2: - cache INDEX_WRITEBACK_INV_D, 0(t0) - bne t0, t1, 2b - addi t0, CONFIG_SYS_CACHELINE_SIZE - - sync - - /* flush i-cache */ - li t0, KSEG0 - addi t1, t0, CONFIG_SYS_ICACHE_SIZE -3: - cache INDEX_INVALIDATE_I, 0(t0) - bne t0, t1, 3b - addi t0, CONFIG_SYS_CACHELINE_SIZE - - /* Invalidate BTB */ - mfc0 t0, CP0_CONFIG, 7 - nop - ori t0, 2 - mtc0 t0, CP0_CONFIG, 7 - nop - - /* Jump to where we've relocated ourselves */ - addi t0, s2, in_ram - _start - jr t0 - nop - - .word __rel_dyn_end - .word __rel_dyn_start - .word __image_copy_end - .word _GLOBAL_OFFSET_TABLE_ - .word num_got_entries - -in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. - */ - lw t3, -4(t0) # t3 <-- num_got_entries - lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - add t8, s1 # t8 now holds relocated _G_O_T_ - addi t8, t8, 8 # skipping first two entries - li t2, 2 -1: - lw t1, 0(t8) - beqz t1, 2f - add t1, s1 - sw t1, 0(t8) -2: - addi t2, 1 - blt t2, t3, 1b - addi t8, 4 - - /* Update dynamic relocations */ - lw t1, -16(t0) # t1 <-- __rel_dyn_start - lw t2, -20(t0) # t2 <-- __rel_dyn_end - - b 2f # skip first reserved entry - addi t1, 8 - -1: - lw t8, -4(t1) # t8 <-- relocation info - - li t3, 3 - bne t8, t3, 2f # skip non R_MIPS_REL32 entries - nop - - lw t3, -8(t1) # t3 <-- location to fix up in FLASH - - lw t8, 0(t3) # t8 <-- original pointer - add t8, s1 # t8 <-- adjusted pointer - - add t3, s1 # t3 <-- location to fix up in RAM - sw t8, 0(t3) - -2: - blt t1, t2, 1b - addi t1, 8 # each rel.dyn entry is 8 bytes - - /* - * Clear BSS - * - * GOT is now relocated. Thus __bss_start and __bss_end can be - * accessed directly via $gp. - */ - la t1, __bss_start # t1 <-- __bss_start - la t2, __bss_end # t2 <-- __bss_end - -1: - sw zero, 0(t1) - blt t1, t2, 1b - addi t1, 4 - - move a0, s0 # a0 <-- gd - la t9, board_init_r - jr t9 - move a1, s2 - - .end relocate_code diff --git a/arch/mips/cpu/xburst/timer.c b/arch/mips/cpu/xburst/timer.c deleted file mode 100644 index 79f34f00c9..0000000000 --- a/arch/mips/cpu/xburst/timer.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2006 - * Ingenic Semiconductor, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include - -#define TIMER_CHAN 0 -#define TIMER_FDATA 0xffff /* Timer full data value */ - -DECLARE_GLOBAL_DATA_PTR; - -static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE; - -void reset_timer_masked(void) -{ - /* reset time */ - gd->arch.lastinc = readl(&tcu->tcnt0); - gd->arch.tbl = 0; -} - -ulong get_timer_masked(void) -{ - ulong now = readl(&tcu->tcnt0); - - if (gd->arch.lastinc <= now) - gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */ - else { - /* we have an overflow ... */ - gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc; - } - - gd->arch.lastinc = now; - - return gd->arch.tbl; -} - -void udelay_masked(unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= 1000*1000; - } else - tmo = 1; - } - - endtime = get_timer_masked() + tmo; - - do { - ulong now = get_timer_masked(); - diff = endtime - now; - } while (diff >= 0); -} - -int timer_init(void) -{ - writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0); - - writel(0, &tcu->tcnt0); - writel(0, &tcu->tdhr0); - writel(TIMER_FDATA, &tcu->tdfr0); - - /* mask irqs */ - writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr); - writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */ - writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */ - - gd->arch.lastinc = 0; - gd->arch.tbl = 0; - - return 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void set_timer(ulong t) -{ - gd->arch.tbl = t; -} - -void __udelay(unsigned long usec) -{ - ulong tmo, tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - if (usec >= 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= 1000 * 1000; - } else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer(0); - if ((tmp + tmo) < tmp) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked() < tmo) - ; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index f2dc533569..b5c2a6367d 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -16,7 +16,6 @@ #include #include -#include /* * clear_bit() doesn't provide any barrier for the compiler. diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 6464250d84..75ec380980 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -11,6 +11,19 @@ #ifndef __ASM_CACHEOPS_H #define __ASM_CACHEOPS_H +#ifndef __ASSEMBLY__ + +static inline void mips_cache(int op, const volatile void *addr) +{ +#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE + __builtin_mips_cache(op, addr); +#else + __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)) +#endif +} + +#endif /* !__ASSEMBLY__ */ + /* * Cache Operations available on all MIPS processors with R4000-style caches */ diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h index cd29734789..3a891ba627 100644 --- a/arch/mips/include/asm/config.h +++ b/arch/mips/include/asm/config.h @@ -7,4 +7,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_LMB +#define CONFIG_SYS_BOOT_RAMDISK_HIGH + #endif diff --git a/arch/mips/include/asm/inca-ip.h b/arch/mips/include/asm/inca-ip.h deleted file mode 100644 index 26f100290c..0000000000 --- a/arch/mips/include/asm/inca-ip.h +++ /dev/null @@ -1,2431 +0,0 @@ - -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ - -#define INCA_IP_WDT (0xB8000000) -/***********************************************************************/ - - -/***Reset Status Register Power On***/ -#define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014)) - -/***Reset Request Register***/ -#define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010)) -#define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24) -#define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16) -#define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5) -#define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4) -#define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3) -#define INCA_IP_WDT_RST_REQ_RREXT (1 << 2) -#define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1) -#define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0) - -/***NMI Status Register***/ -#define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C)) -#define INCA_IP_WDT_NMISR_NMIWDT (1 << 2) -#define INCA_IP_WDT_NMISR_NMIPLL (1 << 1) -#define INCA_IP_WDT_NMISR_NMIEXT (1 << 0) - -/***Manufacturer Identification Register***/ -#define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070)) -#define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074)) -#define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12) -#define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1) - -/***Redesign Tracing Identification Register***/ -#define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078)) -#define INCA_IP_WDT_RTID_LC (1 << 15) -#define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Watchdog Timer Control Register 0***/ -#define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020)) - -/***Watchdog Timer Control Register 1***/ -#define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024)) -#define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3) -#define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2) - -/***Watchdog Timer Status Register***/ -#define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028)) -#define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16) -#define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5) -#define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4) -#define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3) -#define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2) -#define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1) -#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_CGU (0xBF107000) -/***********************************************************************/ - - -/***CGU PLL1 Control Register***/ -#define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008)) -#define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30) -#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Control Register***/ -#define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000)) -#define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30) -#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Status Register***/ -#define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004)) -#define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31) -#define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29) -#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15) - -/***CGU PLL1 Status Register***/ -#define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C)) -#define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31) -#define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29) -#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15) - -/***CGU Divider Control Register***/ -#define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010)) - -/***CGU Multiplexer Control Register***/ -#define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014)) -#define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1) -#define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0) - -/***CGU Fractional Divider Control Register***/ -#define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018)) -#define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31) -#define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_PMU (0xBF102000) -/***********************************************************************/ - - -/***PM Global Enable Register***/ -#define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000)) -#define INCA_IP_PMU_PM_GEN_EN16 (1 << 16) -#define INCA_IP_PMU_PM_GEN_EN15 (1 << 15) -#define INCA_IP_PMU_PM_GEN_EN14 (1 << 14) -#define INCA_IP_PMU_PM_GEN_EN13 (1 << 13) -#define INCA_IP_PMU_PM_GEN_EN12 (1 << 12) -#define INCA_IP_PMU_PM_GEN_EN11 (1 << 11) -#define INCA_IP_PMU_PM_GEN_EN10 (1 << 10) -#define INCA_IP_PMU_PM_GEN_EN9 (1 << 9) -#define INCA_IP_PMU_PM_GEN_EN8 (1 << 8) -#define INCA_IP_PMU_PM_GEN_EN7 (1 << 7) -#define INCA_IP_PMU_PM_GEN_EN6 (1 << 6) -#define INCA_IP_PMU_PM_GEN_EN5 (1 << 5) -#define INCA_IP_PMU_PM_GEN_EN4 (1 << 4) -#define INCA_IP_PMU_PM_GEN_EN3 (1 << 3) -#define INCA_IP_PMU_PM_GEN_EN2 (1 << 2) -#define INCA_IP_PMU_PM_GEN_EN0 (1 << 0) - -/***PM Power Down Enable Register***/ -#define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008)) -#define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16) -#define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15) -#define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14) -#define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13) -#define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12) -#define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11) -#define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10) -#define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9) -#define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8) -#define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7) -#define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5) -#define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4) -#define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3) -#define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2) -#define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010)) -#define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16) -#define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15) -#define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14) -#define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13) -#define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12) -#define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11) -#define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10) -#define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9) -#define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8) -#define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7) -#define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5) -#define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4) -#define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3) -#define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2) -#define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0) - -/***PM Control Register***/ -#define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014)) -#define INCA_IP_PMU_PM_CR_AWEN (1 << 31) -#define INCA_IP_PMU_PM_CR_SWRST (1 << 30) -#define INCA_IP_PMU_PM_CR_SWCR (1 << 2) -#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_BCU (0xB8000100) -/***********************************************************************/ - - -/***BCU Control Register (0010H)***/ -#define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010)) -#define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_BCU_BCU_CON_SPE (1 << 19) -#define INCA_IP_BCU_BCU_CON_PSE (1 << 18) -#define INCA_IP_BCU_BCU_CON_DBG (1 << 16) -#define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***BCU Error Control Capture Register (0020H)***/ -#define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020)) -#define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) -#define INCA_IP_BCU_BCU_ECON_RDN (1 << 23) -#define INCA_IP_BCU_BCU_ECON_WRN (1 << 22) -#define INCA_IP_BCU_BCU_ECON_SVM (1 << 21) -#define INCA_IP_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) -#define INCA_IP_BCU_BCU_ECON_ABT (1 << 18) -#define INCA_IP_BCU_BCU_ECON_RDY (1 << 17) -#define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16) -#define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) -#define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024)) -#define INCA_IP_BCU_BCU_EADD_FPIADR - -/***BCU Error Data Capture Register (0028H)***/ -#define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028)) -#define INCA_IP_BCU_BCU_EDAT_FPIDAT - -/***********************************************************************/ -/* Module : MBC register address and bits */ -/***********************************************************************/ - -#define INCA_IP_MBC (0xBF103000) -/***********************************************************************/ - - -/***Mailbox CPU Configuration Register***/ -#define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080)) -#define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_MBC_MBC_CFG_RES (1 << 5) -#define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) -#define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0) - -/***Mailbox CPU Interrupt Status Register***/ -#define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084)) -#define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_ISR_B1E (1 << 29) -#define INCA_IP_MBC_MBC_ISR_B0E (1 << 28) -#define INCA_IP_MBC_MBC_ISR_WDT (1 << 27) -#define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask Register***/ -#define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088)) -#define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 01 Register***/ -#define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C)) -#define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK01_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 10 Register***/ -#define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090)) -#define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK10_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Short Command Register***/ -#define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094)) -#define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***Mailbox CPU Input Data of Buffer 0***/ -#define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000)) -#define INCA_IP_MBC_MBC_ID0_INDATA - -/***Mailbox CPU Input Data of Buffer 1***/ -#define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020)) -#define INCA_IP_MBC_MBC_ID1_INDATA - -/***Mailbox CPU Output Data of Buffer 2***/ -#define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040)) -#define INCA_IP_MBC_MBC_OD2_OUTDATA - -/***Mailbox CPU Output Data of Buffer 3***/ -#define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060)) -#define INCA_IP_MBC_MBC_OD3_OUTDATA - -/***Mailbox CPU Control Register of Buffer 0***/ -#define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004)) -#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 1***/ -#define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024)) -#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 2***/ -#define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044)) -#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 3***/ -#define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064)) -#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Free Space of Buffer 0***/ -#define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008)) -#define INCA_IP_MBC_MBC_FS0_FS - -/***Mailbox CPU Free Space of Buffer 1***/ -#define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028)) -#define INCA_IP_MBC_MBC_FS1_FS - -/***Mailbox CPU Free Space of Buffer 2***/ -#define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048)) -#define INCA_IP_MBC_MBC_FS2_FS - -/***Mailbox CPU Free Space of Buffer 3***/ -#define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068)) -#define INCA_IP_MBC_MBC_FS3_FS - -/***Mailbox CPU Data Available in Buffer 0***/ -#define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C)) -#define INCA_IP_MBC_MBC_DA0_DA - -/***Mailbox CPU Data Available in Buffer 1***/ -#define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C)) -#define INCA_IP_MBC_MBC_DA1_DA - -/***Mailbox CPU Data Available in Buffer 2***/ -#define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C)) -#define INCA_IP_MBC_MBC_DA2_DA - -/***Mailbox CPU Data Available in Buffer 3***/ -#define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C)) -#define INCA_IP_MBC_MBC_DA3_DA - -/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010)) -#define INCA_IP_MBC_MBC_IABS0_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030)) -#define INCA_IP_MBC_MBC_IABS1_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050)) -#define INCA_IP_MBC_MBC_IABS2_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070)) -#define INCA_IP_MBC_MBC_IABS3_IABS - -/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014)) -#define INCA_IP_MBC_MBC_ITMP0_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034)) -#define INCA_IP_MBC_MBC_ITMP1_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054)) -#define INCA_IP_MBC_MBC_ITMP2_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074)) -#define INCA_IP_MBC_MBC_ITMP3_ITMP - -/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018)) -#define INCA_IP_MBC_MBC_OABS0_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038)) -#define INCA_IP_MBC_MBC_OABS1_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058)) -#define INCA_IP_MBC_MBC_OABS2_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078)) -#define INCA_IP_MBC_MBC_OABS3_OABS - -/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C)) -#define INCA_IP_MBC_MBC_OTMP0_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C)) -#define INCA_IP_MBC_MBC_OTMP1_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C)) -#define INCA_IP_MBC_MBC_OTMP2_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C)) -#define INCA_IP_MBC_MBC_OTMP3_OTMP - -/***DSP Control Register***/ -#define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0)) -#define INCA_IP_MBC_DCTRL_BA (1 << 0) -#define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) -#define INCA_IP_MBC_DCTRL_IDL (1 << 4) -#define INCA_IP_MBC_DCTRL_RES (1 << 15) - -/***DSP Status Register***/ -#define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4)) -#define INCA_IP_MBC_DSTA_IDLE (1 << 0) -#define INCA_IP_MBC_DSTA_PD (1 << 1) - -/***DSP Test 1 Register***/ -#define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8)) -#define INCA_IP_MBC_DTST1_ABORT (1 << 0) -#define INCA_IP_MBC_DTST1_HWF32 (1 << 1) -#define INCA_IP_MBC_DTST1_HWF4M (1 << 2) -#define INCA_IP_MBC_DTST1_HWFOP (1 << 3) - -/***********************************************************************/ -/* Module : Switch register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Switch (0xBF104000) -/***********************************************************************/ - - -/***Unknown Destination Register***/ -#define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000)) -#define INCA_IP_Switch_UN_DEST_CB (1 << 8) -#define INCA_IP_Switch_UN_DEST_LB (1 << 7) -#define INCA_IP_Switch_UN_DEST_PB (1 << 6) -#define INCA_IP_Switch_UN_DEST_CM (1 << 5) -#define INCA_IP_Switch_UN_DEST_LM (1 << 4) -#define INCA_IP_Switch_UN_DEST_PM (1 << 3) -#define INCA_IP_Switch_UN_DEST_CU (1 << 2) -#define INCA_IP_Switch_UN_DEST_LU (1 << 1) -#define INCA_IP_Switch_UN_DEST_PU (1 << 0) - -/***VLAN Control Register***/ -#define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004)) -#define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6) -#define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5) -#define INCA_IP_Switch_VLAN_CTRL_SP (1 << 4) -#define INCA_IP_Switch_VLAN_CTRL_TC (1 << 3) -#define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2) -#define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1) -#define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0) - -/***PC VLAN Configuration Register***/ -#define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008)) -#define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***LAN VLAN Configuration Register***/ -#define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C)) -#define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***CPU VLAN Configuration Register***/ -#define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010)) -#define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***Priority CoS Mapping Register***/ -#define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014)) -#define INCA_IP_Switch_PRI_CoS_P7 (1 << 7) -#define INCA_IP_Switch_PRI_CoS_P6 (1 << 6) -#define INCA_IP_Switch_PRI_CoS_P5 (1 << 5) -#define INCA_IP_Switch_PRI_CoS_P4 (1 << 4) -#define INCA_IP_Switch_PRI_CoS_P3 (1 << 3) -#define INCA_IP_Switch_PRI_CoS_P2 (1 << 2) -#define INCA_IP_Switch_PRI_CoS_P1 (1 << 1) -#define INCA_IP_Switch_PRI_CoS_P0 (1 << 0) - -/***Spanning Tree Port Status Register***/ -#define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018)) -#define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***ARL Control Register***/ -#define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C)) -#define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15) -#define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14) -#define INCA_IP_Switch_ARL_CTL_CHCP (1 << 13) -#define INCA_IP_Switch_ARL_CTL_CC (1 << 12) -#define INCA_IP_Switch_ARL_CTL_CL (1 << 11) -#define INCA_IP_Switch_ARL_CTL_CP (1 << 10) -#define INCA_IP_Switch_ARL_CTL_CG (1 << 9) -#define INCA_IP_Switch_ARL_CTL_PS (1 << 8) -#define INCA_IP_Switch_ARL_CTL_MRO (1 << 7) -#define INCA_IP_Switch_ARL_CTL_SRC (1 << 6) -#define INCA_IP_Switch_ARL_CTL_ATS (1 << 5) -#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_ARL_CTL_MAF (1 << 1) -#define INCA_IP_Switch_ARL_CTL_ENL (1 << 0) -#define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***CPU Access Control Register***/ -#define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020)) -#define INCA_IP_Switch_CPU_ACTL_RA (1 << 31) -#define INCA_IP_Switch_CPU_ACTL_RW (1 << 30) -#define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9) -#define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8) -#define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***CPU Access Data Register 1***/ -#define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024)) -#define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***CPU Access Data Register 2***/ -#define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028)) -#define INCA_IP_Switch_DATA2_Data - -/***CPU Port Control Register***/ -#define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C)) -#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11) -#define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10) -#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value) (((( 1 << 3) - 1) & (value)) << 7) -#define INCA_IP_Switch_CPU_PCTL_MAM (1 << 6) -#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_Switch_CPU_PCTL_MAC (1 << 2) -#define INCA_IP_Switch_CPU_PCTL_EML (1 << 1) -#define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0) -#define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14) - -/***DSCP CoS Mapping Register 1***/ -#define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030)) -#define INCA_IP_Switch_DSCP_COS1_DSCP - -/***DSCP CoS Mapping Register 1***/ -#define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034)) -#define INCA_IP_Switch_DSCP_COS2_DSCP - -/***PC WFQ Control Register***/ -#define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080)) -#define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PC TX Control Register***/ -#define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084)) -#define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1) -#define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0) - -/***LAN WFQ Control Register***/ -#define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100)) -#define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***LAN TX Control Register***/ -#define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104)) -#define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1) -#define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0) - -/***CPU WFQ Control Register***/ -#define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180)) -#define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PM PC RX Watermark Register***/ -#define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200)) -#define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM LAN RX Watermark Register***/ -#define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204)) -#define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ -#define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208)) -#define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ -#define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C)) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM Control Register***/ -#define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210)) -#define INCA_IP_Switch_PM_CTL_GDN (1 << 3) -#define INCA_IP_Switch_PM_CTL_CDN (1 << 2) -#define INCA_IP_Switch_PM_CTL_LDN (1 << 1) -#define INCA_IP_Switch_PM_CTL_PDN (1 << 0) - -/***PM Header Control Register***/ -#define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280)) -#define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21) -#define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20) -#define INCA_IP_Switch_PMAC_HD_CTL_CM (1 << 19) -#define INCA_IP_Switch_PMAC_HD_CTL_CV (1 << 18) -#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2) -#define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1) -#define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0) - -/***PM Source Address Register 1***/ -#define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284)) -#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Source Address Register 2***/ -#define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288)) -#define INCA_IP_Switch_PMAC_SA2_SA_31_0 - -/***PM Dest Address Register 1***/ -#define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C)) -#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Dest Address Register 2***/ -#define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290)) -#define INCA_IP_Switch_PMAC_DA2_DA_31_0 - -/***PM VLAN Register***/ -#define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294)) -#define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13) -#define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12) -#define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***PM TX IPG Counter Register***/ -#define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298)) -#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM RX IPG Counter Register***/ -#define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C)) -#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Mirror Register***/ -#define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300)) -#define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_Switch_MRR_EC (1 << 5) -#define INCA_IP_Switch_MRR_EL (1 << 4) -#define INCA_IP_Switch_MRR_EP (1 << 3) -#define INCA_IP_Switch_MRR_IC (1 << 2) -#define INCA_IP_Switch_MRR_IL (1 << 1) -#define INCA_IP_Switch_MRR_IP (1 << 0) - -/***Packet Length Register***/ -#define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304)) -#define INCA_IP_Switch_PKT_LEN_ADD (1 << 11) -#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***MDIO Access Register***/ -#define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480)) -#define INCA_IP_Switch_MDIO_ACC_RA (1 << 31) -#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30) -#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21) -#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16) -#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Ethernet PHY Register***/ -#define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484)) -#define INCA_IP_Switch_EPHY_SL (1 << 7) -#define INCA_IP_Switch_EPHY_SP (1 << 6) -#define INCA_IP_Switch_EPHY_LL (1 << 5) -#define INCA_IP_Switch_EPHY_LP (1 << 4) -#define INCA_IP_Switch_EPHY_DL (1 << 3) -#define INCA_IP_Switch_EPHY_DP (1 << 2) -#define INCA_IP_Switch_EPHY_PL (1 << 1) -#define INCA_IP_Switch_EPHY_PP (1 << 0) - -/***Pause Write Enable Register***/ -#define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488)) -#define INCA_IP_Switch_PWR_EN_PL (1 << 1) -#define INCA_IP_Switch_PWR_EN_PP (1 << 0) - -/***MDIO Configuration Register***/ -#define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C)) -#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14) -#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9) -#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4) -#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3) -#define INCA_IP_Switch_MDIO_CFG_PS (1 << 2) -#define INCA_IP_Switch_MDIO_CFG_PT (1 << 1) -#define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0) - -/***Clock Configuration Register***/ -#define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500)) -#define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9) -#define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8) -#define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7) -#define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6) -#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5) - -/***********************************************************************/ -/* Module : SSC1 register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SSC1 (0xB8000500) -/***********************************************************************/ - - -/***Control Register (Programming Mode)***/ -#define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) -#define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15) -#define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14) -#define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12) -#define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11) -#define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10) -#define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9) -#define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8) -#define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7) -#define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6) -#define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5) -#define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4) -#define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ -#define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) -#define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15) -#define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14) -#define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12) -#define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11) -#define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10) -#define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9) -#define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8) -#define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ -#define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040)) -#define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15) -#define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14) -#define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13) -#define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12) -#define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11) -#define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10) -#define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9) -#define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ -#define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014)) -#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ -#define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020)) -#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ -#define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024)) -#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ -#define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030)) -#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1) -#define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ -#define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034)) -#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1) -#define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ -#define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038)) -#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ -#define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000)) -#define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : SSC2 register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SSC2 (0xB8000600) -/***********************************************************************/ - - -/***Control Register (Programming Mode)***/ -#define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) -#define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15) -#define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14) -#define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12) -#define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11) -#define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10) -#define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9) -#define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8) -#define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7) -#define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6) -#define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5) -#define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4) -#define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ -#define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) -#define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15) -#define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14) -#define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12) -#define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11) -#define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10) -#define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9) -#define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8) -#define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ -#define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040)) -#define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15) -#define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14) -#define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13) -#define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12) -#define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11) -#define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10) -#define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9) -#define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ -#define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014)) -#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ -#define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020)) -#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ -#define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024)) -#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ -#define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030)) -#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1) -#define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ -#define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034)) -#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1) -#define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ -#define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038)) -#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ -#define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000)) -#define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_EBU (0xB8000200) -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000)) -#define INCA_IP_EBU_EBU_CLC_DISS (1 << 1) -#define INCA_IP_EBU_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010)) -#define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5) -#define INCA_IP_EBU_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020)) -#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024)) -#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028)) -#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060)) -#define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON0_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON0_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064)) -#define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON1_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON1_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068)) -#define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON2_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON2_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SDRAM (0xBF800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100)) -#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108)) -#define INCA_IP_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800)) -#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) -#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) -#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_IOGP_CPS (1 << 11) -#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00)) -#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000)) -#define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008)) -#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) -#define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3) -#define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010)) -#define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018)) -#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038)) -#define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040)) -#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_GPTU (0xB8000300) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000)) -#define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1) -#define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014)) -#define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T3CON_T3EDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define INCA_IP_GPTU_GPT_T3CON_T3OTL (1 << 10) -#define INCA_IP_GPTU_GPT_T3CON_T3UD (1 << 7) -#define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6) -#define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C)) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010)) -#define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T2CON_TxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS (1 << 12) -#define INCA_IP_GPTU_GPT_T2CON_TxRC (1 << 9) -#define INCA_IP_GPTU_GPT_T2CON_TxUD (1 << 7) -#define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6) -#define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018)) -#define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T4CON_TxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS (1 << 12) -#define INCA_IP_GPTU_GPT_T4CON_TxRC (1 << 9) -#define INCA_IP_GPTU_GPT_T4CON_TxUD (1 << 7) -#define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6) -#define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048)) -#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050)) -#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030)) -#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034)) -#define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038)) -#define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C)) -#define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040)) -#define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044)) -#define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020)) -#define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15) -#define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14) -#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define INCA_IP_GPTU_GPT_T6CON_T6OTL (1 << 10) -#define INCA_IP_GPTU_GPT_T6CON_T6UD (1 << 7) -#define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6) -#define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054)) -#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) -#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C)) -#define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15) -#define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14) -#define INCA_IP_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) -#define INCA_IP_GPTU_GPT_T5CON_T5CC (1 << 11) -#define INCA_IP_GPTU_GPT_T5CON_CT3 (1 << 10) -#define INCA_IP_GPTU_GPT_T5CON_T5RC (1 << 9) -#define INCA_IP_GPTU_GPT_T5CON_T5UDE (1 << 8) -#define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7) -#define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6) -#define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : IOM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_IOM (0xBF105000) -/***********************************************************************/ - - -/***Receive FIFO***/ -#define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) -#define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Transmit FIFO***/ -#define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) -#define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Interrupt Status Register HDLC***/ -#define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) -#define INCA_IP_IOM_ISTAH_RME (1 << 7) -#define INCA_IP_IOM_ISTAH_RPF (1 << 6) -#define INCA_IP_IOM_ISTAH_RFO (1 << 5) -#define INCA_IP_IOM_ISTAH_XPR (1 << 4) -#define INCA_IP_IOM_ISTAH_XMR (1 << 3) -#define INCA_IP_IOM_ISTAH_XDU (1 << 2) - -/***Interrupt Mask Register HDLC***/ -#define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) -#define INCA_IP_IOM_MASKH_RME (1 << 7) -#define INCA_IP_IOM_MASKH_RPF (1 << 6) -#define INCA_IP_IOM_MASKH_RFO (1 << 5) -#define INCA_IP_IOM_MASKH_XPR (1 << 4) -#define INCA_IP_IOM_MASKH_XMR (1 << 3) -#define INCA_IP_IOM_MASKH_XDU (1 << 2) - -/***Status Register***/ -#define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) -#define INCA_IP_IOM_STAR_XDOV (1 << 7) -#define INCA_IP_IOM_STAR_XFW (1 << 6) -#define INCA_IP_IOM_STAR_RACI (1 << 3) -#define INCA_IP_IOM_STAR_XACI (1 << 1) - -/***Command Register***/ -#define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) -#define INCA_IP_IOM_CMDR_RMC (1 << 7) -#define INCA_IP_IOM_CMDR_RRES (1 << 6) -#define INCA_IP_IOM_CMDR_XTF (1 << 3) -#define INCA_IP_IOM_CMDR_XME (1 << 1) -#define INCA_IP_IOM_CMDR_XRES (1 << 0) - -/***Mode Register***/ -#define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088)) -#define INCA_IP_IOM_MODEH_MDS2 (1 << 7) -#define INCA_IP_IOM_MODEH_MDS1 (1 << 6) -#define INCA_IP_IOM_MODEH_MDS0 (1 << 5) -#define INCA_IP_IOM_MODEH_RAC (1 << 3) -#define INCA_IP_IOM_MODEH_DIM2 (1 << 2) -#define INCA_IP_IOM_MODEH_DIM1 (1 << 1) -#define INCA_IP_IOM_MODEH_DIM0 (1 << 0) - -/***Extended Mode Register***/ -#define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C)) -#define INCA_IP_IOM_EXMR_XFBS (1 << 7) -#define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) -#define INCA_IP_IOM_EXMR_SRA (1 << 4) -#define INCA_IP_IOM_EXMR_XCRC (1 << 3) -#define INCA_IP_IOM_EXMR_RCRC (1 << 2) -#define INCA_IP_IOM_EXMR_ITF (1 << 0) - -/***SAPI1 Register***/ -#define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094)) -#define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_SAP1_MHA (1 << 0) - -/***Receive Frame Byte Count Low***/ -#define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098)) -#define INCA_IP_IOM_RBCL_RBC(value) (1 << value) - - -/***SAPI2 Register***/ -#define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098)) -#define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_SAP2_MLA (1 << 0) - -/***Receive Frame Byte Count High***/ -#define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C)) -#define INCA_IP_IOM_RBCH_OV (1 << 4) -#define INCA_IP_IOM_RBCH_RBC11 (1 << 3) -#define INCA_IP_IOM_RBCH_RBC10 (1 << 2) -#define INCA_IP_IOM_RBCH_RBC9 (1 << 1) -#define INCA_IP_IOM_RBCH_RBC8 (1 << 0) - -/***TEI1 Register 1***/ -#define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C)) -#define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define INCA_IP_IOM_TEI1_EA (1 << 0) - -/***Receive Status Register***/ -#define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) -#define INCA_IP_IOM_RSTA_VFR (1 << 7) -#define INCA_IP_IOM_RSTA_RDO (1 << 6) -#define INCA_IP_IOM_RSTA_CRC (1 << 5) -#define INCA_IP_IOM_RSTA_RAB (1 << 4) -#define INCA_IP_IOM_RSTA_SA1 (1 << 3) -#define INCA_IP_IOM_RSTA_SA0 (1 << 2) -#define INCA_IP_IOM_RSTA_TA (1 << 0) -#define INCA_IP_IOM_RSTA_CR (1 << 1) - -/***TEI2 Register***/ -#define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) -#define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define INCA_IP_IOM_TEI2_EA (1 << 0) - -/***Test Mode Register HDLC***/ -#define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4)) -#define INCA_IP_IOM_TMH_TLP (1 << 0) - -/***Command/Indication Receive 0***/ -#define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) -#define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_IOM_CIR0_CIC0 (1 << 3) -#define INCA_IP_IOM_CIR0_CIC1 (1 << 2) -#define INCA_IP_IOM_CIR0_SG (1 << 1) -#define INCA_IP_IOM_CIR0_BAS (1 << 0) - -/***Command/Indication Transmit 0***/ -#define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) -#define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_IOM_CIX0_TBA2 (1 << 3) -#define INCA_IP_IOM_CIX0_TBA1 (1 << 2) -#define INCA_IP_IOM_CIX0_TBA0 (1 << 1) -#define INCA_IP_IOM_CIX0_BAC (1 << 0) - -/***Command/Indication Receive 1***/ -#define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) -#define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) - -/***Command/Indication Transmit 1***/ -#define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) -#define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_CIX1_CICW (1 << 1) -#define INCA_IP_IOM_CIX1_CI1E (1 << 0) - -/***Controller Data Access Reg. (CH10)***/ -#define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100)) -#define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH11)***/ -#define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104)) -#define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH20)***/ -#define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108)) -#define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH21)***/ -#define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C)) -#define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110)) -#define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114)) -#define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118)) -#define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C)) -#define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120)) -#define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124)) -#define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128)) -#define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C)) -#define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138)) -#define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5) -#define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4) -#define INCA_IP_IOM_CDA1_CR_EN_I0 (1 << 3) -#define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2) -#define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1) -#define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C)) -#define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5) -#define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4) -#define INCA_IP_IOM_CDA2_CR_EN_I0 (1 << 3) -#define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2) -#define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1) -#define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0) - -/***Control Register B-Channel Data***/ -#define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144)) -#define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4) -#define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3) - -/***Control Register B-Channel Data***/ -#define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148)) -#define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4) -#define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3) - -/***Control Reg. for HDLC and CI1 Data***/ -#define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) -#define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7) -#define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6) -#define INCA_IP_IOM_DCI_CR_EN_D (1 << 5) - -/***Control Reg. for HDLC and CI1 Data***/ -#define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) -#define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7) -#define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6) -#define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5) - -/***Control Reg. Serial Data Strobe x***/ -#define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154)) -#define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7) -#define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6) -#define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5) -#define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Control Register IOM Data***/ -#define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C)) -#define INCA_IP_IOM_IOM_CR_SPU (1 << 7) -#define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5) -#define INCA_IP_IOM_IOM_CR_TIC_DIS (1 << 4) -#define INCA_IP_IOM_IOM_CR_EN_BCL (1 << 3) -#define INCA_IP_IOM_IOM_CR_CLKM (1 << 2) -#define INCA_IP_IOM_IOM_CR_Res (1 << 1) -#define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0) - -/***Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) -#define INCA_IP_IOM_STI_STOV21 (1 << 7) -#define INCA_IP_IOM_STI_STOV20 (1 << 6) -#define INCA_IP_IOM_STI_STOV11 (1 << 5) -#define INCA_IP_IOM_STI_STOV10 (1 << 4) -#define INCA_IP_IOM_STI_STI21 (1 << 3) -#define INCA_IP_IOM_STI_STI20 (1 << 2) -#define INCA_IP_IOM_STI_STI11 (1 << 1) -#define INCA_IP_IOM_STI_STI10 (1 << 0) - -/***Acknowledge Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) -#define INCA_IP_IOM_ASTI_ACK21 (1 << 3) -#define INCA_IP_IOM_ASTI_ACK20 (1 << 2) -#define INCA_IP_IOM_ASTI_ACK11 (1 << 1) -#define INCA_IP_IOM_ASTI_ACK10 (1 << 0) - -/***Mask Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164)) -#define INCA_IP_IOM_MSTI_STOV21 (1 << 7) -#define INCA_IP_IOM_MSTI_STOV20 (1 << 6) -#define INCA_IP_IOM_MSTI_STOV11 (1 << 5) -#define INCA_IP_IOM_MSTI_STOV10 (1 << 4) -#define INCA_IP_IOM_MSTI_STI21 (1 << 3) -#define INCA_IP_IOM_MSTI_STI20 (1 << 2) -#define INCA_IP_IOM_MSTI_STI11 (1 << 1) -#define INCA_IP_IOM_MSTI_STI10 (1 << 0) - -/***Configuration Register for Serial Data Strobes***/ -#define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168)) -#define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0) - -/***Monitoring CDA Bits***/ -#define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C)) -#define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : ASC register address and bits */ -/***********************************************************************/ - -#define INCA_IP_ASC (0xB8000400) -/***********************************************************************/ - - -/***ASC Port Input Select Register***/ -#define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004)) -#define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0) - -/***ASC Control Register***/ -#define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010)) -#define INCA_IP_ASC_ASC_CON_R (1 << 15) -#define INCA_IP_ASC_ASC_CON_LB (1 << 14) -#define INCA_IP_ASC_ASC_CON_BRS (1 << 13) -#define INCA_IP_ASC_ASC_CON_ODD (1 << 12) -#define INCA_IP_ASC_ASC_CON_FDE (1 << 11) -#define INCA_IP_ASC_ASC_CON_OE (1 << 10) -#define INCA_IP_ASC_ASC_CON_FE (1 << 9) -#define INCA_IP_ASC_ASC_CON_PE (1 << 8) -#define INCA_IP_ASC_ASC_CON_OEN (1 << 7) -#define INCA_IP_ASC_ASC_CON_FEN (1 << 6) -#define INCA_IP_ASC_ASC_CON_PENRXDI (1 << 5) -#define INCA_IP_ASC_ASC_CON_REN (1 << 4) -#define INCA_IP_ASC_ASC_CON_STP (1 << 3) -#define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***ASC Write Hardware Modified Control Register***/ -#define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050)) -#define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13) -#define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12) -#define INCA_IP_ASC_ASC_WHBCON_SETPE (1 << 11) -#define INCA_IP_ASC_ASC_WHBCON_CLROE (1 << 10) -#define INCA_IP_ASC_ASC_WHBCON_CLRFE (1 << 9) -#define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8) -#define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5) -#define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4) - -/***ASC Baudrate Timer/Reload Register***/ -#define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014)) -#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***ASC Fractional Divider Register***/ -#define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018)) -#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC IrDA Pulse Mode/Width Register***/ -#define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C)) -#define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8) -#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***ASC Transmit Buffer Register***/ -#define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020)) -#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Receive Buffer Register***/ -#define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024)) -#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Autobaud Control Register***/ -#define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030)) -#define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11) -#define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10) -#define INCA_IP_ASC_ASC_ABCON_ABEM (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_ASC_ASC_ABCON_FCDETEN (1 << 4) -#define INCA_IP_ASC_ASC_ABCON_ABDETEN (1 << 3) -#define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2) -#define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1) -#define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0) - -/***Receive FIFO Control Register***/ -#define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040)) -#define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1) -#define INCA_IP_ASC_RXFCON_RXFEN (1 << 0) - -/***Transmit FIFO Control Register***/ -#define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044)) -#define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1) -#define INCA_IP_ASC_TXFCON_TXFEN (1 << 0) - -/***FIFO Status Register***/ -#define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048)) -#define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***ASC Write HW Modified Autobaud Control Register***/ -#define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054)) -#define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1) -#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0) - -/***ASC Autobaud Status Register***/ -#define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034)) -#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4) -#define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3) -#define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2) -#define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1) -#define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0) - -/***ASC Write HW Modified Autobaud Status Register***/ -#define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058)) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET (1 << 7) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET (1 << 6) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET (1 << 5) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET (1 << 4) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET (1 << 3) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0) - -/***ASC Clock Control Register***/ -#define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000)) -#define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_ASC_ASC_CLC_DISS (1 << 1) -#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define INCA_IP_DMA (0xBF108000) -/***********************************************************************/ - - -/***DMA RX Channel 0 Command Register***/ -#define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800)) -#define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31) -#define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2) -#define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1) -#define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0) - -/***DMA RX Channel 1 Command Register***/ -#define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804)) -#define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31) -#define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2) -#define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1) -#define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0) - -/***DMA Receive Interrupt Status Register***/ -#define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808)) -#define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Receive Interrupt Mask Register***/ -#define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C)) -#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Rx Channel 0 -***/ -#define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810)) -#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Rx Channel 1 -***/ -#define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814)) -#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Receive Channel Polling Time***/ -#define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818)) -#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30) -#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28) -#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA TX Channel 0 Command Register (Voice Port)***/ -#define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880)) -#define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0) - -/***DMA TX Channel 1 Command Register (Mangmt Port)***/ -#define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884)) -#define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0) - -/***DMA TX Channel 2 Command Register (SSC Port)***/ -#define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888)) -#define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR2_HBF (1 << 29) -#define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 0 -***/ -#define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0)) -#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 1 -***/ -#define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4)) -#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 2 -***/ -#define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8)) -#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Transmit Channel Arbitration Register***/ -#define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0)) -#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Transmit Channel Polling Time***/ -#define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4)) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Status Register***/ -#define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8)) -#define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) -#define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Mask Register***/ -#define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC)) -#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) -#define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Debug (0xBF106000) -/***********************************************************************/ - - -/***MCD Break Bus Switch Register***/ -#define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000)) -#define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19) -#define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18) -#define INCA_IP_Debug_MCD_BBS_BSP1 (1 << 17) -#define INCA_IP_Debug_MCD_BBS_BSP0 (1 << 16) -#define INCA_IP_Debug_MCD_BBS_BT5EN (1 << 15) -#define INCA_IP_Debug_MCD_BBS_BT4EN (1 << 14) -#define INCA_IP_Debug_MCD_BBS_BT5 (1 << 13) -#define INCA_IP_Debug_MCD_BBS_BT4 (1 << 12) -#define INCA_IP_Debug_MCD_BBS_BS5EN (1 << 7) -#define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6) -#define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5) -#define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4) - -/***MCD Multiplexer Control Register***/ -#define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008)) -#define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4) -#define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3) -#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0) - -/***********************************************************************/ -/* Module : TSF register address and bits */ -/***********************************************************************/ - -#define INCA_IP_TSF (0xB8000900) -/***********************************************************************/ - - -/***TSF Configuration Register (0000H)***/ -#define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000)) -#define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2) -#define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1) -#define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0) - -/***Key scan Configuration Register (0004H)***/ -#define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004)) -#define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Scan Register Line 0 and 1 (0008H)***/ -#define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008)) -#define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***Scan Register Line 2 and 3 (000CH)***/ -#define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C)) -#define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***Scan Register Line 4, 5 and 6 (0010H)***/ -#define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010)) -#define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24) -#define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***Scan Register Line 7 to 12 (0014H)***/ -#define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014)) -#define INCA_IP_TSF_SREG7to12_RES12x (1 << 28) -#define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_TSF_SREG7to12_RES10x (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8) -#define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***LEDMUX Configuration Register (0018H)***/ -#define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018)) -#define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25) -#define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24) -#define INCA_IP_TSF_LEDMUX_CONF_EDPX1 (1 << 23) -#define INCA_IP_TSF_LEDMUX_CONF_EACT1 (1 << 22) -#define INCA_IP_TSF_LEDMUX_CONF_ESPD1 (1 << 21) -#define INCA_IP_TSF_LEDMUX_CONF_ETL0 (1 << 20) -#define INCA_IP_TSF_LEDMUX_CONF_ESTA0 (1 << 19) -#define INCA_IP_TSF_LEDMUX_CONF_EDPX0 (1 << 18) -#define INCA_IP_TSF_LEDMUX_CONF_EACT0 (1 << 17) -#define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16) -#define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1) -#define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0) - -/***LED Register (001CH)***/ -#define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C)) -#define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***Pulse Width Modulator 1 and 2 Register (0020H)***/ -#define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020)) -#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***********************************************************************/ -/* Module : Ports register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Ports (0xB8000A00) -/***********************************************************************/ - - -/***Port 1 Data Output Register (0020H)***/ -#define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020)) -#define INCA_IP_Ports_P1_OUT_P(value) (1 << value) - - -/***Port 2 Data Output Register (0040H)***/ -#define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040)) -#define INCA_IP_Ports_P2_OUT_P(value) (1 << value) - - -/***Port 1 Data Input Register (0024H)***/ -#define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024)) -#define INCA_IP_Ports_P1_IN_P(value) (1 << value) - - -/***Port 2 Data Input Register (0044H)***/ -#define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044)) -#define INCA_IP_Ports_P2_IN_P(value) (1 << value) - - -/***Port 1 Direction Register (0028H)***/ -#define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028)) -#define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 2 Direction Register (0048H)***/ -#define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048)) -#define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 0 Alternate Function Select Register 0 (000C H) -***/ -#define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C)) -#define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value) - - -/***Port 1 Alternate Function Select Register 0 (002C H) -***/ -#define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C)) -#define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value) - - -/***Port 2 Alternate Function Select Register 0 (004C H) -***/ -#define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C)) -#define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value) - - -/***Port 0 Input Schmitt-Trigger Off Register (0010 H) -***/ -#define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010)) -#define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value) - - -/***Port 1 Input Schmitt-Trigger Off Register (0030 H) -***/ -#define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030)) -#define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Input Schmitt-Trigger Off Register (0050 H) -***/ -#define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050)) -#define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Open Drain Control Register (0054H)***/ -#define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054)) -#define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value) - - -/***Port 0 Pull Up Device Enable Register (0018 H)***/ -#define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018)) -#define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value) - - -/***Port 2 Pull Up Device Enable Register (0058 H)***/ -#define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058)) -#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - -#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - - -/***Port 0 Pull Up/Pull Down Select Register (001C H)***/ -#define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C)) -#define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value) - - -/***Port 2 Pull Up/Pull Down Select Register (005C H)***/ -#define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C)) -#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - -#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - - -/***********************************************************************/ -/* Module : DES/3DES register address and bits */ -/***********************************************************************/ - -#define INCA_IP_DES_3DES (0xB8000800) -/***********************************************************************/ - - -/***DES Input Data High Register***/ -#define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000)) -#define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value) - - -/***DES Input Data Low Register***/ -#define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004)) -#define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value) - - -/***DES Key #1 High Register***/ -#define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008)) -#define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value) - - -/***DES Key #1 Low Register***/ -#define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C)) -#define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value) - - -/***DES Key #2 High Register***/ -#define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010)) -#define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value) - - -/***DES Key #2 Low Register***/ -#define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014)) -#define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value) - - -/***DES Key #3 High Register***/ -#define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018)) -#define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value) - - -/***DES Key #3 Low Register***/ -#define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C)) -#define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value) - - -/***DES Initialization Vector High Register***/ -#define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020)) -#define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value) - - -/***DES Initialization Vector Low Register***/ -#define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024)) -#define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value) - - -/***DES Control Register***/ -#define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028)) -#define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31) -#define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16) -#define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value) - -#define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value) - -#define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8) -#define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7) -#define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6) -#define INCA_IP_DES_3DES_DES_CONTROLR_BUS (1 << 5) -#define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4) -#define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3) -#define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value) - - -/***DES Output Data High Register***/ -#define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C)) -#define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value) - - -/***DES Output Data Low Register***/ -#define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030)) -#define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value) - - -/***********************************************************************/ -/* Module : AES register address and bits */ -/***********************************************************************/ - -#define INCA_IP_AES (0xB8000880) -/***********************************************************************/ - - -/***AES Input Data 3 Register***/ -#define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID3R_I(value) (1 << value) - - -/***AES Input Data 2 Register***/ -#define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID2R_I(value) (1 << value) - - -/***AES Input Data 1 Register***/ -#define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID1R_I(value) (1 << value) - - -/***AES Input Data 0 Register***/ -#define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID0R_I(value) (1 << value) - - -/***AES Output Data 3 Register***/ -#define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD3R_O(value) (1 << value) - - -/***AES Output Data 2 Register***/ -#define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD2R_O(value) (1 << value) - - -/***AES Output Data 1 Register***/ -#define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD1R_O(value) (1 << value) - - -/***AES Output Data 0 Register***/ -#define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD0R_O(value) (1 << value) - - -/***AES Key 7 Register***/ -#define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K7R_K(value) (1 << value) - - -/***AES Key 6 Register***/ -#define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K6R_K(value) (1 << value) - - -/***AES Key 5 Register***/ -#define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K5R_K(value) (1 << value) - - -/***AES Key 4 Register***/ -#define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K4R_K(value) (1 << value) - - -/***AES Key 3 Register***/ -#define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K3R_K(value) (1 << value) - - -/***AES Key 2 Register***/ -#define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K2R_K(value) (1 << value) - - -/***AES Key 1 Register***/ -#define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K1R_K(value) (1 << value) - - -/***AES Key 0 Register***/ -#define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K0R_K(value) (1 << value) - - -/***AES Initialization Vector 3 Register***/ -#define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV3R_IV(value) (1 << value) - - -/***AES Initialization Vector 2 Register***/ -#define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV2R_IV(value) (1 << value) - - -/***AES Initialization Vector 1 Register***/ -#define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV1R_IV(value) (1 << value) - - -/***AES Initialization Vector 0 Register***/ -#define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0) - -/***AES Control Register***/ -#define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31) -#define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16) -#define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15) -#define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value) - -#define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value) - -#define INCA_IP_AES_AES_CONTROLR_GO (1 << 8) -#define INCA_IP_AES_AES_CONTROLR_STP (1 << 7) -#define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6) -#define INCA_IP_AES_AES_CONTROLR_BUS (1 << 5) -#define INCA_IP_AES_AES_CONTROLR_SM (1 << 4) -#define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3) -#define INCA_IP_AES_AES_CONTROLR_KV (1 << 2) -#define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value) - - -/***********************************************************************/ -/* Module : I²C register address and bits */ -/***********************************************************************/ - -#define INCA_IP_IIC (0xB8000700) -/***********************************************************************/ - - -/***I²C Port Input Select Register***/ -#define INCA_IP_IIC_IIC_PISEL ((volatile u32*)(INCA_IP_IIC+ 0x0004)) -#define INCA_IP_IIC_IIC_PISEL_SDAIS(value) (1 << value) - -#define INCA_IP_IIC_IIC_PISEL_SCLIS(value) (1 << value) - - -/***I²C Clock Control Register***/ -#define INCA_IP_IIC_IIC_CLC ((volatile u32*)(INCA_IP_IIC+ 0x0000)) -#define INCA_IP_IIC_IIC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_CLC_DISS (1 << 1) -#define INCA_IP_IIC_IIC_CLC_DISR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_0_WMEN (1 << 31) -#define INCA_IP_IIC_IIC_SYSCON_0_CI (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_IIC_IIC_SYSCON_0_STP (1 << 25) -#define INCA_IP_IIC_IIC_SYSCON_0_IGE (1 << 24) -#define INCA_IP_IIC_IIC_SYSCON_0_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_0_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_0_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_0_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_0_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_0_RMEN (1 << 15) -#define INCA_IP_IIC_IIC_SYSCON_0_CO (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_0_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_0_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_0_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_0_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_0_ADR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_1_RM (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_IIC_IIC_SYSCON_1_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_1_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_1_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_1_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_1_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_1_RMEN (1 << 15) -#define INCA_IP_IIC_IIC_SYSCON_1_CO (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_1_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_1_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_1_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_1_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_1_ADR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_2 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_2_WMEN (1 << 31) -#define INCA_IP_IIC_IIC_SYSCON_2_CI (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_IIC_IIC_SYSCON_2_STP (1 << 25) -#define INCA_IP_IIC_IIC_SYSCON_2_IGE (1 << 24) -#define INCA_IP_IIC_IIC_SYSCON_2_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_2_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_2_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_2_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_2_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_2_WM (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_2_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_2_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_2_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_2_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_2_ADR (1 << 0) - -/***I²C Write Hardware Modified System Control Register -***/ -#define INCA_IP_IIC_IIC_WHBSYSCON ((volatile u32*)(INCA_IP_IIC+ 0x0020)) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN (1 << 31) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN (1 << 30) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP (1 << 26) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP (1 << 25) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX (1 << 24) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX (1 << 23) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS (1 << 22) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM (1 << 20) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM (1 << 19) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC (1 << 17) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC (1 << 16) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN (1 << 15) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN (1 << 14) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE (1 << 10) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP (1 << 9) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD (1 << 8) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE (1 << 7) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP (1 << 6) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD (1 << 5) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL (1 << 2) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL (1 << 1) - -/***I²C Bus Control Register***/ -#define INCA_IP_IIC_IIC_BUSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) -#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD (1 << 31) -#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value) (((( 1 << 10) - 1) & (value)) << 16) -#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value) (1 << value) - -#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value) (1 << value) - - -/***I²C Bus Control Register***/ -#define INCA_IP_IIC_IIC_BUSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) -#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD (1 << 31) -#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value) (((( 1 << 7) - 1) & (value)) << 17) -#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value) (1 << value) - -#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value) (1 << value) - - -/***I²C Receive Transmit Buffer***/ -#define INCA_IP_IIC_IIC_RTB ((volatile u32*)(INCA_IP_IIC+ 0x0018)) -#define INCA_IP_IIC_IIC_RTB_RTB(value) (1 << value) - - -/***********************************************************************/ -/* Module : FB register address and bits */ -/***********************************************************************/ - -#define INCA_IP_FB (0xBF880000) -/***********************************************************************/ - - -/***FB Access Error Cause Register***/ -#define INCA_IP_FB_FB_ERRCAUSE ((volatile u32*)(INCA_IP_FB+ 0x0100)) -#define INCA_IP_FB_FB_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_FB_FB_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***FB Access Error Address Register***/ -#define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108)) -#define INCA_IP_FB_FB_ERRADDR_ADDR - -/***FB Configuration Register***/ -#define INCA_IP_FB_FB_CFG ((volatile u32*)(INCA_IP_FB+ 0x0800)) -#define INCA_IP_FB_FB_CFG_SVM (1 << 0) - -/***********************************************************************/ -/* Module : SRAM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SRAM (0xBF980000) -/***********************************************************************/ - - -/***SRAM Size Register***/ -#define INCA_IP_SRAM_SRAM_SIZE ((volatile u32*)(INCA_IP_SRAM+ 0x0800)) -#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_BIU (0xBFA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define INCA_IP_BIU_BIU_ID ((volatile u32*)(INCA_IP_BIU+ 0x0000)) -#define INCA_IP_BIU_BIU_ID_ARCH (1 << 16) -#define INCA_IP_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define INCA_IP_BIU_BIU_ERRCAUSE ((volatile u32*)(INCA_IP_BIU+ 0x0100)) -#define INCA_IP_BIU_BIU_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108)) -#define INCA_IP_BIU_BIU_ERRADDR_ADDR - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_ICU (0xBF101000) -/***********************************************************************/ - - -/***IM0 Interrupt Status Register***/ -#define INCA_IP_ICU_IM0_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0000)) -#define INCA_IP_ICU_IM0_ISR_IR(value) (1 << value) - - -/***IM1 Interrupt Status Register***/ -#define INCA_IP_ICU_IM1_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0200)) -#define INCA_IP_ICU_IM1_ISR_IR(value) (1 << value) - - -/***IM2 Interrupt Status Register***/ -#define INCA_IP_ICU_IM2_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0400)) -#define INCA_IP_ICU_IM2_ISR_IR(value) (1 << value) - - -/***IM0 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM0_IER ((volatile u32*)(INCA_IP_ICU+ 0x0008)) -#define INCA_IP_ICU_IM0_IER_IR(value) (1 << value) - - -/***IM1 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM1_IER ((volatile u32*)(INCA_IP_ICU+ 0x0208)) -#define INCA_IP_ICU_IM1_IER_IR(value) (1 << value) - - -/***IM2 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM2_IER ((volatile u32*)(INCA_IP_ICU+ 0x0408)) -#define INCA_IP_ICU_IM2_IER_IR(value) (1 << value) - - -/***IM0 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM0_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0010)) -#define INCA_IP_ICU_IM0_IOSR_IR(value) (1 << value) - - -/***IM1 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM1_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0210)) -#define INCA_IP_ICU_IM1_IOSR_IR(value) (1 << value) - - -/***IM2 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM2_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0410)) -#define INCA_IP_ICU_IM2_IOSR_IR(value) (1 << value) - - -/***IM0 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM0_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0018)) -#define INCA_IP_ICU_IM0_IRSR_IR(value) (1 << value) - - -/***IM1 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM1_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0218)) -#define INCA_IP_ICU_IM1_IRSR_IR(value) (1 << value) - - -/***IM2 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM2_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0418)) -#define INCA_IP_ICU_IM2_IRSR_IR(value) (1 << value) - - -/***External Interrupt Control Register***/ -#define INCA_IP_ICU_ICU_EICR ((volatile u32*)(INCA_IP_ICU+ 0x0B00)) -#define INCA_IP_ICU_ICU_EICR_EII5 (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_ICU_ICU_EICR_EII4 (value) (((( 1 << 3) - 1) & (value)) << 16) -#define INCA_IP_ICU_ICU_EICR_EII3 (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_ICU_ICU_EICR_EII2 (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_ICU_ICU_EICR_EII1 (value) (((( 1 << 3) - 1) & (value)) << 4) -#define INCA_IP_ICU_ICU_EICR_EII0 (value) (((( 1 << 3) - 1) & (value)) << 0) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 50a882ca5a..3fa37f5dd2 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -11,7 +11,6 @@ #ifndef _ASM_IO_H #define _ASM_IO_H -#include #if 0 #include #endif diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index d4d44a299f..d9ffc1558d 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -1,23 +1,72 @@ /* * Copyright (C) 2013 Gabor Juhos + * Copyright (C) 2013 Imagination Technologies * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _MIPS_ASM_MALTA_H #define _MIPS_ASM_MALTA_H -#define MALTA_IO_PORT_BASE 0x18000000 +#define MALTA_GT_BASE 0x1be00000 +#define MALTA_GT_PCIIO_BASE 0x18000000 +#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) -#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) +#define MALTA_MSC01_BIU_BASE 0x1bc80000 +#define MALTA_MSC01_PCI_BASE 0x1bd00000 +#define MALTA_MSC01_PBC_BASE 0x1bd40000 +#define MALTA_MSC01_IP1_BASE 0x1bc00000 +#define MALTA_MSC01_IP1_SIZE 0x00400000 +#define MALTA_MSC01_IP2_BASE1 0x10000000 +#define MALTA_MSC01_IP2_SIZE1 0x08000000 +#define MALTA_MSC01_IP2_BASE2 0x18000000 +#define MALTA_MSC01_IP2_SIZE2 0x04000000 +#define MALTA_MSC01_IP3_BASE 0x1c000000 +#define MALTA_MSC01_IP3_SIZE 0x04000000 +#define MALTA_MSC01_PCIMEM_BASE 0x10000000 +#define MALTA_MSC01_PCIMEM_SIZE 0x10000000 +#define MALTA_MSC01_PCIMEM_MAP 0x10000000 +#define MALTA_MSC01_PCIIO_BASE 0x1b000000 +#define MALTA_MSC01_PCIIO_SIZE 0x00800000 +#define MALTA_MSC01_PCIIO_MAP 0x00000000 +#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) -#define MALTA_GT_BASE 0x1be00000 +#define MALTA_ASCIIWORD 0x1f000410 +#define MALTA_ASCIIPOS0 0x1f000418 +#define MALTA_ASCIIPOS1 0x1f000420 +#define MALTA_ASCIIPOS2 0x1f000428 +#define MALTA_ASCIIPOS3 0x1f000430 +#define MALTA_ASCIIPOS4 0x1f000438 +#define MALTA_ASCIIPOS5 0x1f000440 +#define MALTA_ASCIIPOS6 0x1f000448 +#define MALTA_ASCIIPOS7 0x1f000450 -#define MALTA_RESET_BASE 0x1f000500 -#define GORESET 0x42 +#define MALTA_RESET_BASE 0x1f000500 +#define GORESET 0x42 -#define MALTA_FLASH_BASE 0x1fc00000 +#define MALTA_FLASH_BASE 0x1e000000 + +#define MALTA_REVISION 0x1fc00010 +#define MALTA_REVISION_CORID_SHF 10 +#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF) +#define MALTA_REVISION_CORID_CORE_LV 1 +#define MALTA_REVISION_CORID_CORE_FPGA6 14 + +#define PCI_CFG_PIIX4_PIRQRCA 0x60 +#define PCI_CFG_PIIX4_PIRQRCB 0x61 +#define PCI_CFG_PIIX4_PIRQRCC 0x62 +#define PCI_CFG_PIIX4_PIRQRCD 0x63 +#define PCI_CFG_PIIX4_SERIRQC 0x64 +#define PCI_CFG_PIIX4_GENCFG 0xb0 + +#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7) +#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6) + +#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16) + +#define PCI_CFG_PIIX4_IDETIM_PRI 0x40 +#define PCI_CFG_PIIX4_IDETIM_SEC 0x42 + +#define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15) #endif /* _MIPS_ASM_MALTA_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index be7e5c65ec..3571e4fdf2 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -494,11 +494,17 @@ #define MIPS_CONF1_PC (_ULCAST_(1) << 4) #define MIPS_CONF1_MD (_ULCAST_(1) << 5) #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA_SHIFT 7 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL_SHIFT 10 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS_SHIFT 13 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA_SHIFT 16 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL_SHIFT 19 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS_SHIFT 22 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 24858ddda5..ba7f5381a3 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -11,8 +11,6 @@ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H -#include - #include #include diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index b6d50e2f04..7a2895284e 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -16,7 +16,6 @@ #ifndef _ASM_SYSTEM_H #define _ASM_SYSTEM_H -#include #include #include #if 0 diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h index d4bb85999b..aebafdbba1 100644 --- a/arch/mips/include/asm/types.h +++ b/arch/mips/include/asm/types.h @@ -27,18 +27,12 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if (_MIPS_SZLONG == 64) - -typedef __signed__ long __s64; -typedef unsigned long __u64; - -#else - #if defined(__GNUC__) __extension__ typedef __signed__ long long __s64; __extension__ typedef unsigned long long __u64; -#endif - +#else +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif #endif /* __ASSEMBLY__ */ @@ -61,19 +55,8 @@ typedef unsigned short u16; typedef __signed int s32; typedef unsigned int u32; -#if (_MIPS_SZLONG == 64) - -typedef __signed__ long s64; -typedef unsigned long u64; - -#else - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) typedef __signed__ long long s64; typedef unsigned long long u64; -#endif - -#endif #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ || defined(CONFIG_64BIT) diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h index 9f3cce9a62..a5b2fc08f8 100644 --- a/arch/mips/include/asm/u-boot-mips.h +++ b/arch/mips/include/asm/u-boot-mips.h @@ -21,5 +21,3 @@ static inline unsigned long image_copy_end(void) extern char __image_copy_end[]; return (unsigned long) &__image_copy_end; } - -extern int incaip_set_cpuclk(void); diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index 985d7d808a..4909a2a5c4 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -15,8 +15,14 @@ #ifndef _U_BOOT_H_ #define _U_BOOT_H_ 1 +#ifdef CONFIG_SYS_GENERIC_BOARD + +/* Use the generic board which requires a unified bd_info */ +#include + +#else /* !CONFIG_SYS_GENERIC_BOARD */ + typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ @@ -26,6 +32,8 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ } bd_t; +#endif /* !CONFIG_SYS_GENERIC_BOARD */ + /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_MIPS diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h index 1d5112ea69..c25a8462c7 100644 --- a/arch/mips/include/asm/unaligned.h +++ b/arch/mips/include/asm/unaligned.h @@ -8,7 +8,7 @@ #ifndef _ASM_MIPS_UNALIGNED_H #define _ASM_MIPS_UNALIGNED_H -#include +#include #if defined(__MIPSEB__) #define get_unaligned __get_unaligned_be #define put_unaligned __put_unaligned_be diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index e9f82f711a..ac536da674 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -5,50 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y += cache.o +obj-y += cache_init.o +obj-y += io.o -LIB = $(obj)lib$(ARCH).o +obj-$(CONFIG_CMD_BOOTM) += bootm.o -## Build a couple of necessary functions into a private libgcc -LIBGCC = $(obj)libgcc.o -GLSOBJS += ashldi3.o -GLSOBJS += ashrdi3.o -GLSOBJS += lshrdi3.o -LGOBJS := $(addprefix $(obj),$(GLSOBJS)) - -SOBJS-y += - -COBJS-y += board.o -ifeq ($(CONFIG_QEMU_MIPS),y) -COBJS-$(CONFIG_CMD_BOOTM) += bootm_qemu_mips.o -else -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -endif - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -# Always build libmips.o -TARGETS := $(LIB) - -# Build private libgcc only when asked for -ifdef USE_PRIVATE_LIBGCC -TARGETS += $(LIBGCC) -endif - -all: $(TARGETS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(LIBGCC): $(obj).depend $(LGOBJS) - $(call cmd_link_o_target, $(LGOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c deleted file mode 100644 index 9e6ba15aca..0000000000 --- a/arch/mips/lib/board.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_BITBANGMII -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -ulong monitor_flash_len; - -static char *failed = "*** failed ***\n"; - -/* - * mips_io_port_base is the begin of the address space to which x86 style - * I/O ports are mapped. - */ -const unsigned long mips_io_port_base = -1; - -int __board_early_init_f(void) -{ - /* - * Nothing to do in this dummy implementation - */ - return 0; -} -int board_early_init_f(void) - __attribute__((weak, alias("__board_early_init_f"))); - -static int init_func_ram(void) -{ -#ifdef CONFIG_BOARD_TYPES - int board_type = gd->board_type; -#else - int board_type = 0; /* use dummy arg */ -#endif - puts("DRAM: "); - - gd->ram_size = initdram(board_type); - if (gd->ram_size > 0) { - print_size(gd->ram_size, "\n"); - return 0; - } - puts(failed); - return 1; -} - -static int display_banner(void) -{ - - printf("\n\n%s\n\n", version_string); - return 0; -} - -#ifndef CONFIG_SYS_NO_FLASH -static void display_flash_config(ulong size) -{ - puts("Flash: "); - print_size(size, "\n"); -} -#endif - -static int init_baudrate(void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - return 0; -} - - -/* - * Breath some life into the board... - * - * The first part of initialization is running from Flash memory; - * its main purpose is to initialize the RAM so that we - * can relocate the monitor code to RAM. - */ - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t)(void); - -init_fnc_t *init_sequence[] = { - board_early_init_f, - timer_init, - env_init, /* initialize environment */ -#ifdef CONFIG_INCA_IP - incaip_set_cpuclk, /* set cpu clock according to env. variable */ -#endif - init_baudrate, /* initialize baudrate settings */ - serial_init, /* serial communications setup */ - console_init_f, - display_banner, /* say that we are here */ - checkboard, - init_func_ram, - NULL, -}; - - -void board_init_f(ulong bootflag) -{ - gd_t gd_data, *id; - bd_t *bd; - init_fnc_t **init_fnc_ptr; - ulong addr, addr_sp, len; - ulong *s; - - /* Pointer is writable since we allocated a register for it. - */ - gd = &gd_data; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("" : : : "memory"); - - memset((void *)gd, 0, sizeof(gd_t)); - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr)() != 0) - hang(); - } - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - */ - addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; - - /* We can reserve some RAM "on top" here. - */ - - /* round down to next 4 kB limit. - */ - addr &= ~(4096 - 1); - debug("Top of RAM usable for U-Boot at: %08lx\n", addr); - - /* Reserve memory for U-Boot code, data & bss - * round down to next 16 kB limit - */ - len = bss_end() - CONFIG_SYS_MONITOR_BASE; - addr -= len; - addr &= ~(16 * 1024 - 1); - - debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); - - /* Reserve memory for malloc() arena. - */ - addr_sp = addr - TOTAL_MALLOC_LEN; - debug("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); - - /* - * (permanently) allocate a Board Info struct - * and a permanent copy of the "global" data - */ - addr_sp -= sizeof(bd_t); - bd = (bd_t *)addr_sp; - gd->bd = bd; - debug("Reserving %zu Bytes for Board Info at: %08lx\n", - sizeof(bd_t), addr_sp); - - addr_sp -= sizeof(gd_t); - id = (gd_t *)addr_sp; - debug("Reserving %zu Bytes for Global Data at: %08lx\n", - sizeof(gd_t), addr_sp); - - /* Reserve memory for boot params. - */ - addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN; - bd->bi_boot_params = addr_sp; - debug("Reserving %dk for boot params() at: %08lx\n", - CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp); - - /* - * Finally, we set up a new (bigger) stack. - * - * Leave some safety gap for SP, force alignment on 16 byte boundary - * Clear initial stack frame - */ - addr_sp -= 16; - addr_sp &= ~0xF; - s = (ulong *)addr_sp; - *s-- = 0; - *s-- = 0; - addr_sp = (ulong)s; - debug("Stack Pointer at: %08lx\n", addr_sp); - - /* - * Save local variables to board info struct - */ - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */ - bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ - - memcpy(id, (void *)gd, sizeof(gd_t)); - - relocate_code(addr_sp, id, addr); - - /* NOTREACHED - relocate_code() does not return */ -} - -/* - * This is the next part if the initialization sequence: we are now - * running from RAM and have a "normal" C environment, i. e. global - * data can be written, BSS has been cleared, the stack size in not - * that critical any more, etc. - */ - -void board_init_r(gd_t *id, ulong dest_addr) -{ -#ifndef CONFIG_SYS_NO_FLASH - ulong size; -#endif - bd_t *bd; - - gd = id; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - - gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; - - monitor_flash_len = image_copy_end() - dest_addr; - - serial_initialize(); - - bd = gd->bd; - - /* The Malloc area is immediately below the monitor copy in DRAM */ - mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - - TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); - -#ifndef CONFIG_SYS_NO_FLASH - /* configure available FLASH banks */ - size = flash_init(); - display_flash_config(size); - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - bd->bi_flashsize = size; - -#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */ -#else - bd->bi_flashoffset = 0; -#endif -#else - bd->bi_flashstart = 0; - bd->bi_flashsize = 0; - bd->bi_flashoffset = 0; -#endif - -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); /* go init the NAND */ -#endif - -#if defined(CONFIG_CMD_ONENAND) - onenand_init(); -#endif - - /* relocate environment function pointers etc. */ - env_relocate(); - -#if defined(CONFIG_PCI) - /* - * Do pci configuration - */ - pci_init(); -#endif - -/** leave this here (after malloc(), environment and PCI are working) **/ - /* Initialize stdio devices */ - stdio_init(); - - jumptable_init(); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r(); -/** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/ - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - -#ifdef CONFIG_CMD_SPI - puts("SPI: "); - spi_init(); /* go init the SPI */ - puts("ready\n"); -#endif - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r(); -#endif - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - puts("Net: "); - eth_initialize(gd->bd); -#endif - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) - main_loop(); - - /* NOTREACHED - no way out of command loop except booting */ -} diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index ade9af47e3..d9d8396e63 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -6,10 +6,8 @@ */ #include -#include #include -#include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -17,115 +15,145 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 +#if defined(CONFIG_MALTA) +#define mips_boot_malta 1 +#else +#define mips_boot_malta 0 +#endif + +#if defined(CONFIG_MIPS_BOOT_CMDLINE_LEGACY) +#define mips_boot_cmdline_legacy 1 +#else +#define mips_boot_cmdline_legacy 0 +#endif + +#if defined(CONFIG_MIPS_BOOT_ENV_LEGACY) +#define mips_boot_env_legacy 1 +#else +#define mips_boot_env_legacy 0 +#endif + static int linux_argc; static char **linux_argv; +static char *linux_argp; static char **linux_env; static char *linux_env_p; static int linux_env_idx; -static void linux_params_init(ulong start, char *commandline); -static void linux_env_set(char *env_name, char *env_val); - -static void boot_prep_linux(bootm_headers_t *images) +static ulong arch_get_sp(void) { - char *commandline = getenv("bootargs"); - char env_buf[12]; - char *cp; - - linux_params_init(UNCACHED_SDRAM(gd->bd->bi_boot_params), commandline); + ulong ret; -#ifdef CONFIG_MEMSIZE_IN_BYTES - sprintf(env_buf, "%lu", (ulong)gd->ram_size); - debug("## Giving linux memsize in bytes, %lu\n", (ulong)gd->ram_size); -#else - sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20)); - debug("## Giving linux memsize in MB, %lu\n", - (ulong)(gd->ram_size >> 20)); -#endif /* CONFIG_MEMSIZE_IN_BYTES */ + __asm__ __volatile__("move %0, $sp" : "=r"(ret) : ); - linux_env_set("memsize", env_buf); - - sprintf(env_buf, "0x%08X", (uint) UNCACHED_SDRAM(images->rd_start)); - linux_env_set("initrd_start", env_buf); + return ret; +} - sprintf(env_buf, "0x%X", (uint) (images->rd_end - images->rd_start)); - linux_env_set("initrd_size", env_buf); +void arch_lmb_reserve(struct lmb *lmb) +{ + ulong sp; - sprintf(env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); - linux_env_set("flash_start", env_buf); + sp = arch_get_sp(); + debug("## Current stack ends at 0x%08lx\n", sp); - sprintf(env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); - linux_env_set("flash_size", env_buf); + /* adjust sp by 4K to be safe */ + sp -= 4096; + lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp); +} - cp = getenv("ethaddr"); - if (cp) - linux_env_set("ethaddr", cp); +static int boot_setup_linux(bootm_headers_t *images) +{ + int ret; + ulong rd_len; + + rd_len = images->rd_end - images->rd_start; + ret = boot_ramdisk_high(&images->lmb, images->rd_start, + rd_len, &images->initrd_start, &images->initrd_end); + if (ret) + return ret; + +#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT) + if (images->ft_len) { + boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); + + ret = boot_relocate_fdt(&images->lmb, &images->ft_addr, + &images->ft_len); + if (ret) + return ret; + } +#endif - cp = getenv("eth1addr"); - if (cp) - linux_env_set("eth1addr", cp); + return 0; } -static void boot_jump_linux(bootm_headers_t *images) +static void boot_setup_fdt(bootm_headers_t *images) { - void (*theKernel) (int, char **, char **, int *); +#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT) + u64 mem_start = 0; + u64 mem_size = gd->ram_size; - /* find kernel entry point */ - theKernel = (void (*)(int, char **, char **, int *))images->ep; + debug("## setup FDT\n"); - debug("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) theKernel); + fdt_chosen(images->ft_addr, 1); + fdt_fixup_memory_banks(images->ft_addr, &mem_start, &mem_size, 1); + fdt_fixup_ethernet(images->ft_addr); + fdt_initrd(images->ft_addr, images->initrd_start, images->initrd_end, 1); - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - - /* we assume that the kernel is in place */ - printf("\nStarting kernel ...\n\n"); +#if defined(CONFIG_OF_BOARD_SETUP) + ft_board_setup(images->ft_addr, gd->bd); +#endif +#endif +} - theKernel(linux_argc, linux_argv, linux_env, 0); +static void linux_cmdline_init(void) +{ + linux_argc = 1; + linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params); + linux_argv[0] = 0; + linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS); } -int do_bootm_linux(int flag, int argc, char * const argv[], - bootm_headers_t *images) +static void linux_cmdline_set(const char *value, size_t len) { - /* No need for those on MIPS */ - if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) - return -1; + linux_argv[linux_argc] = linux_argp; + memcpy(linux_argp, value, len); + linux_argp[len] = 0; - if (flag & BOOTM_STATE_OS_PREP) { - boot_prep_linux(images); - return 0; - } + linux_argp += len + 1; + linux_argc++; +} - if (flag & BOOTM_STATE_OS_GO) { - boot_jump_linux(images); - return 0; - } +static void linux_cmdline_dump(void) +{ + int i; - boot_prep_linux(images); - boot_jump_linux(images); + debug("## cmdline argv at 0x%p, argp at 0x%p\n", + linux_argv, linux_argp); - /* does not return */ - return 1; + for (i = 1; i < linux_argc; i++) + debug(" arg %03d: %s\n", i, linux_argv[i]); } -static void linux_params_init(ulong start, char *line) +static void linux_cmdline_legacy(bootm_headers_t *images) { - char *next, *quote, *argp; + const char *bootargs, *next, *quote; - linux_argc = 1; - linux_argv = (char **) start; - linux_argv[0] = 0; - argp = (char *) (linux_argv + LINUX_MAX_ARGS); + linux_cmdline_init(); - next = line; + bootargs = getenv("bootargs"); + if (!bootargs) + return; - while (line && *line && linux_argc < LINUX_MAX_ARGS) { - quote = strchr(line, '"'); - next = strchr(line, ' '); + next = bootargs; + + while (bootargs && *bootargs && linux_argc < LINUX_MAX_ARGS) { + quote = strchr(bootargs, '"'); + next = strchr(bootargs, ' '); while (next && quote && quote < next) { - /* we found a left quote before the next blank + /* + * we found a left quote before the next blank * now we have to find the matching right quote */ next = strchr(quote + 1, '"'); @@ -136,28 +164,60 @@ static void linux_params_init(ulong start, char *line) } if (!next) - next = line + strlen(line); - - linux_argv[linux_argc] = argp; - memcpy(argp, line, next - line); - argp[next - line] = 0; + next = bootargs + strlen(bootargs); - argp += next - line + 1; - linux_argc++; + linux_cmdline_set(bootargs, next - bootargs); if (*next) next++; - line = next; + bootargs = next; } +} + +static void linux_cmdline_append(bootm_headers_t *images) +{ + char buf[24]; + ulong mem, rd_start, rd_size; + + /* append mem */ + mem = gd->ram_size >> 20; + sprintf(buf, "mem=%luM", mem); + linux_cmdline_set(buf, strlen(buf)); + + /* append rd_start and rd_size */ + rd_start = images->initrd_start; + rd_size = images->initrd_end - images->initrd_start; + + if (rd_size) { + sprintf(buf, "rd_start=0x%08lX", rd_start); + linux_cmdline_set(buf, strlen(buf)); + sprintf(buf, "rd_size=0x%lX", rd_size); + linux_cmdline_set(buf, strlen(buf)); + } +} - linux_env = (char **) (((ulong) argp + 15) & ~15); +static void boot_cmdline_linux(bootm_headers_t *images) +{ + if (mips_boot_cmdline_legacy && !images->ft_len) { + linux_cmdline_legacy(images); + + if (!mips_boot_env_legacy) + linux_cmdline_append(images); + + linux_cmdline_dump(); + } +} + +static void linux_env_init(void) +{ + linux_env = (char **)(((ulong) linux_argp + 15) & ~15); linux_env[0] = 0; - linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS); + linux_env_p = (char *)(linux_env + LINUX_MAX_ENVS); linux_env_idx = 0; } -static void linux_env_set(char *env_name, char *env_val) +static void linux_env_set(const char *env_name, const char *env_val) { if (linux_env_idx < LINUX_MAX_ENVS - 1) { linux_env[linux_env_idx] = linux_env_p; @@ -165,8 +225,12 @@ static void linux_env_set(char *env_name, char *env_val) strcpy(linux_env_p, env_name); linux_env_p += strlen(env_name); - strcpy(linux_env_p, "="); - linux_env_p += 1; + if (mips_boot_malta) { + linux_env_p++; + linux_env[++linux_env_idx] = linux_env_p; + } else { + *linux_env_p++ = '='; + } strcpy(linux_env_p, env_val); linux_env_p += strlen(env_val); @@ -175,3 +239,119 @@ static void linux_env_set(char *env_name, char *env_val) linux_env[++linux_env_idx] = 0; } } + +static void linux_env_legacy(bootm_headers_t *images) +{ + char env_buf[12]; + const char *cp; + ulong rd_start, rd_size; + +#ifdef CONFIG_MEMSIZE_IN_BYTES + sprintf(env_buf, "%lu", (ulong)gd->ram_size); + debug("## Giving linux memsize in bytes, %lu\n", (ulong)gd->ram_size); +#else + sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20)); + debug("## Giving linux memsize in MB, %lu\n", + (ulong)(gd->ram_size >> 20)); +#endif /* CONFIG_MEMSIZE_IN_BYTES */ + + rd_start = UNCACHED_SDRAM(images->initrd_start); + rd_size = images->initrd_end - images->initrd_start; + + linux_env_init(); + + linux_env_set("memsize", env_buf); + + sprintf(env_buf, "0x%08lX", rd_start); + linux_env_set("initrd_start", env_buf); + + sprintf(env_buf, "0x%lX", rd_size); + linux_env_set("initrd_size", env_buf); + + sprintf(env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); + linux_env_set("flash_start", env_buf); + + sprintf(env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); + linux_env_set("flash_size", env_buf); + + cp = getenv("ethaddr"); + if (cp) + linux_env_set("ethaddr", cp); + + cp = getenv("eth1addr"); + if (cp) + linux_env_set("eth1addr", cp); + + if (mips_boot_malta) { + sprintf(env_buf, "%un8r", gd->baudrate); + linux_env_set("modetty0", env_buf); + } +} + +static void boot_prep_linux(bootm_headers_t *images) +{ + if (mips_boot_env_legacy && !images->ft_len) + linux_env_legacy(images); + + if (images->ft_len) + boot_setup_fdt(images); +} + +static void boot_jump_linux(bootm_headers_t *images) +{ + typedef void __noreturn (*kernel_entry_t)(int, ulong, ulong, ulong); + kernel_entry_t kernel = (kernel_entry_t) images->ep; + ulong linux_extra = 0; + + debug("## Transferring control to Linux (at address %p) ...\n", kernel); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + if (mips_boot_malta) + linux_extra = gd->ram_size; + +#ifdef CONFIG_BOOTSTAGE_FDT + bootstage_fdt_add_report(); +#endif +#ifdef CONFIG_BOOTSTAGE_REPORT + bootstage_report(); +#endif + + kernel(linux_argc, (ulong)linux_argv, (ulong)linux_env, linux_extra); +} + +int do_bootm_linux(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + int ret; + + /* No need for those on MIPS */ + if (flag & BOOTM_STATE_OS_BD_T) + return -1; + + if (flag & BOOTM_STATE_OS_CMDLINE) { + boot_cmdline_linux(images); + return 0; + } + + if (flag & BOOTM_STATE_OS_PREP) { + boot_prep_linux(images); + return 0; + } + + if (flag & BOOTM_STATE_OS_GO) { + boot_jump_linux(images); + return 0; + } + + ret = boot_setup_linux(images); + if (ret) + return ret; + + boot_cmdline_linux(images); + boot_prep_linux(images); + boot_jump_linux(images); + + /* does not return */ + return 1; +} diff --git a/arch/mips/lib/bootm_qemu_mips.c b/arch/mips/lib/bootm_qemu_mips.c deleted file mode 100644 index 910ab73638..0000000000 --- a/arch/mips/lib/bootm_qemu_mips.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2008 - * Jean-Christophe PLAGNIOL-VILLARD - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int do_bootm_linux(int flag, int argc, char * const argv[], - bootm_headers_t *images) -{ - void (*theKernel) (int, char **, char **, int *); - char *bootargs = getenv("bootargs"); - char *start; - uint len; - - /* find kernel entry point */ - theKernel = (void (*)(int, char **, char **, int *))images->ep; - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - - debug("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) theKernel); - - gd->bd->bi_boot_params = gd->bd->bi_memstart + (16 << 20) - 256; - debug("%-12s= 0x%08lX\n", "boot_params", (ulong)gd->bd->bi_boot_params); - - /* set Magic */ - *(int32_t *)(gd->bd->bi_boot_params - 4) = 0x12345678; - /* set ram_size */ - *(int32_t *)(gd->bd->bi_boot_params - 8) = gd->ram_size; - - start = (char *)gd->bd->bi_boot_params; - - len = strlen(bootargs); - - strncpy(start, bootargs, len + 1); - - start += len; - - len = images->rd_end - images->rd_start; - if (len > 0) { - start += sprintf(start, " rd_start=0x%08X rd_size=0x%0X", - (uint) UNCACHED_SDRAM(images->rd_start), - (uint) len); - } - - /* we assume that the kernel is in place */ - printf("\nStarting kernel ...\n\n"); - - theKernel(0, NULL, NULL, 0); - - /* does not return */ - return 1; -} diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c new file mode 100644 index 0000000000..e245614d16 --- /dev/null +++ b/arch/mips/lib/cache.c @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_CACHELINE_SIZE + +static inline unsigned long icache_line_size(void) +{ + return CONFIG_SYS_CACHELINE_SIZE; +} + +static inline unsigned long dcache_line_size(void) +{ + return CONFIG_SYS_CACHELINE_SIZE; +} + +#else /* !CONFIG_SYS_CACHELINE_SIZE */ + +static inline unsigned long icache_line_size(void) +{ + unsigned long conf1, il; + conf1 = read_c0_config1(); + il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT; + if (!il) + return 0; + return 2 << il; +} + +static inline unsigned long dcache_line_size(void) +{ + unsigned long conf1, dl; + conf1 = read_c0_config1(); + dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT; + if (!dl) + return 0; + return 2 << dl; +} + +#endif /* !CONFIG_SYS_CACHELINE_SIZE */ + +void flush_cache(ulong start_addr, ulong size) +{ + unsigned long ilsize = icache_line_size(); + unsigned long dlsize = dcache_line_size(); + const void *addr, *aend; + + /* aend will be miscalculated when size is zero, so we return here */ + if (size == 0) + return; + + addr = (const void *)(start_addr & ~(dlsize - 1)); + aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1)); + + if (ilsize == dlsize) { + /* flush I-cache & D-cache simultaneously */ + while (1) { + mips_cache(HIT_WRITEBACK_INV_D, addr); + mips_cache(HIT_INVALIDATE_I, addr); + if (addr == aend) + break; + addr += dlsize; + } + return; + } + + /* flush D-cache */ + while (1) { + mips_cache(HIT_WRITEBACK_INV_D, addr); + if (addr == aend) + break; + addr += dlsize; + } + + /* flush I-cache */ + addr = (const void *)(start_addr & ~(ilsize - 1)); + aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1)); + while (1) { + mips_cache(HIT_INVALIDATE_I, addr); + if (addr == aend) + break; + addr += ilsize; + } +} + +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = dcache_line_size(); + const void *addr = (const void *)(start_addr & ~(lsize - 1)); + const void *aend = (const void *)((stop - 1) & ~(lsize - 1)); + + while (1) { + mips_cache(HIT_WRITEBACK_INV_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = dcache_line_size(); + const void *addr = (const void *)(start_addr & ~(lsize - 1)); + const void *aend = (const void *)((stop - 1) & ~(lsize - 1)); + + while (1) { + mips_cache(HIT_INVALIDATE_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S new file mode 100644 index 0000000000..137d7283ff --- /dev/null +++ b/arch/mips/lib/cache_init.S @@ -0,0 +1,241 @@ +/* + * Cache-handling routined for MIPS CPUs + * + * Copyright (c) 2003 Wolfgang Denk + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + +#define INDEX_BASE CKSEG0 + + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +#endif + .endm + + .macro cache_loop curr, end, line_sz, op +10: cache \op, 0(\curr) + PTR_ADDU \curr, \curr, \line_sz + bne \curr, \end, 10b + .endm + + .macro l1_info sz, line_sz, off + .set push + .set noat + + mfc0 $1, CP0_CONFIG, 1 + + /* detect line size */ + srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT + andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT) + move \sz, zero + beqz \line_sz, 10f + li \sz, 2 + sllv \line_sz, \sz, \line_sz + + /* detect associativity */ + srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT + andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT) + addi \sz, \sz, 1 + + /* sz *= line_sz */ + mul \sz, \sz, \line_sz + + /* detect log32(sets) */ + srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT + andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT) + addiu $1, $1, 1 + andi $1, $1, 0x7 + + /* sz <<= log32(sets) */ + sllv \sz, \sz, $1 + + /* sz *= 32 */ + li $1, 32 + mul \sz, \sz, $1 +10: + .set pop + .endm +/* + * mips_cache_reset - low level initialisation of the primary caches + * + * This routine initialises the primary caches to ensure that they have good + * parity. It must be called by the ROM before any cached locations are used + * to prevent the possibility of data with bad parity being written to memory. + * + * To initialise the instruction cache it is essential that a source of data + * with good parity is available. This routine will initialise an area of + * memory starting at location zero to be used as a source of parity. + * + * RETURNS: N/A + * + */ +LEAF(mips_cache_reset) +#ifdef CONFIG_SYS_ICACHE_SIZE + li t2, CONFIG_SYS_ICACHE_SIZE + li t8, CONFIG_SYS_CACHELINE_SIZE +#else + l1_info t2, t8, MIPS_CONF1_IA_SHIFT +#endif + +#ifdef CONFIG_SYS_DCACHE_SIZE + li t3, CONFIG_SYS_DCACHE_SIZE + li t9, CONFIG_SYS_CACHELINE_SIZE +#else + l1_info t3, t9, MIPS_CONF1_DA_SHIFT +#endif + +#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + + /* Determine the largest L1 cache size */ +#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE) +#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE + li v0, CONFIG_SYS_ICACHE_SIZE +#else + li v0, CONFIG_SYS_DCACHE_SIZE +#endif +#else + move v0, t2 + sltu t1, t2, t3 + movn v0, t3, t1 +#endif + /* + * Now clear that much memory starting from zero. + */ + PTR_LI a0, CKSEG1 + PTR_ADDU a1, a0, v0 +2: PTR_ADDIU a0, 64 + f_fill64 a0, -64, zero + bne a0, a1, 2b + +#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */ + + /* + * The TagLo registers used depend upon the CPU implementation, but the + * architecture requires that it is safe for software to write to both + * TagLo selects 0 & 2 covering supported cases. + */ + mtc0 zero, CP0_TAGLO + mtc0 zero, CP0_TAGLO, 2 + + /* + * The caches are probably in an indeterminate state, so we force good + * parity into them by doing an invalidate for each line. If + * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to + * perform a load/fill & a further invalidate for each line, assuming + * that the bottom of RAM (having just been cleared) will generate good + * parity for the cache. + */ + + /* + * Initialize the I-cache first, + */ + blez t2, 1f + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, t2 + /* clear tag to invalidate */ + cache_loop t0, t1, t8, INDEX_STORE_TAG_I +#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* fill once, so data field parity is correct */ + PTR_LI t0, INDEX_BASE + cache_loop t0, t1, t8, FILL + /* invalidate again - prudent but not strictly neccessary */ + PTR_LI t0, INDEX_BASE + cache_loop t0, t1, t8, INDEX_STORE_TAG_I +#endif + + /* + * then initialize D-cache. + */ +1: blez t3, 3f + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, t3 + /* clear all tags */ + cache_loop t0, t1, t9, INDEX_STORE_TAG_D +#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* load from each line (in cached space) */ + PTR_LI t0, INDEX_BASE +2: LONG_L zero, 0(t0) + PTR_ADDU t0, t9 + bne t0, t1, 2b + /* clear all tags */ + PTR_LI t0, INDEX_BASE + cache_loop t0, t1, t9, INDEX_STORE_TAG_D +#endif + +3: jr ra + END(mips_cache_reset) + +/* + * dcache_status - get cache status + * + * RETURNS: 0 - cache disabled; 1 - cache enabled + * + */ +LEAF(dcache_status) + mfc0 t0, CP0_CONFIG + li t1, CONF_CM_UNCACHED + andi t0, t0, CONF_CM_CMASK + move v0, zero + beq t0, t1, 2f + li v0, 1 +2: jr ra + END(dcache_status) + +/* + * dcache_disable - disable cache + * + * RETURNS: N/A + * + */ +LEAF(dcache_disable) + mfc0 t0, CP0_CONFIG + li t1, -8 + and t0, t0, t1 + ori t0, t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + jr ra + END(dcache_disable) + +/* + * dcache_enable - enable cache + * + * RETURNS: N/A + * + */ +LEAF(dcache_enable) + mfc0 t0, CP0_CONFIG + ori t0, CONF_CM_CMASK + xori t0, CONF_CM_CMASK + ori t0, CONFIG_SYS_MIPS_CACHE_MODE + mtc0 t0, CP0_CONFIG + jr ra + END(dcache_enable) diff --git a/arch/mips/lib/io.c b/arch/mips/lib/io.c new file mode 100644 index 0000000000..b2d4a094da --- /dev/null +++ b/arch/mips/lib/io.c @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * mips_io_port_base is the begin of the address space to which x86 style + * I/O ports are mapped. + */ +const unsigned long mips_io_port_base = -1; diff --git a/arch/mips/mach-au1x00/Makefile b/arch/mips/mach-au1x00/Makefile new file mode 100644 index 0000000000..c5643e713b --- /dev/null +++ b/arch/mips/mach-au1x00/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c similarity index 98% rename from arch/mips/cpu/mips32/au1x00/au1x00_eth.c rename to arch/mips/mach-au1x00/au1x00_eth.c index 65671cd188..39c5b6bc4a 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c +++ b/arch/mips/mach-au1x00/au1x00_eth.c @@ -3,7 +3,7 @@ * (C) Copyright 2003 * Thomas.Lange@corelatus.se * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -294,3 +294,9 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } + +int cpu_eth_init(bd_t *bis) +{ + au1x00_enet_initialize(bis); + return 0; +} diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_ide.c b/arch/mips/mach-au1x00/au1x00_ide.c similarity index 100% rename from arch/mips/cpu/mips32/au1x00/au1x00_ide.c rename to arch/mips/mach-au1x00/au1x00_ide.c diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c b/arch/mips/mach-au1x00/au1x00_serial.c similarity index 100% rename from arch/mips/cpu/mips32/au1x00/au1x00_serial.c rename to arch/mips/mach-au1x00/au1x00_serial.c diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/mach-au1x00/au1x00_usb_ohci.c similarity index 93% rename from arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c rename to arch/mips/mach-au1x00/au1x00_usb_ohci.c index 931f95a0da..74bdb77303 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c +++ b/arch/mips/mach-au1x00/au1x00_usb_ohci.c @@ -54,8 +54,6 @@ #define readl(a) au_readl((long)(a)) #define writel(v,a) au_writel((v),(int)(a)) -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - #define DEBUG #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) @@ -839,104 +837,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ @@ -1548,7 +1449,7 @@ static void hc_release_ohci (ohci_t *ohci) */ static char ohci_inited = 0; -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { u32 pin_func; u32 sys_freqctrl, sys_clksrc; diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h b/arch/mips/mach-au1x00/au1x00_usb_ohci.h similarity index 100% rename from arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h rename to arch/mips/mach-au1x00/au1x00_usb_ohci.h diff --git a/arch/mips/cpu/mips32/au1x00/config.mk b/arch/mips/mach-au1x00/config.mk similarity index 100% rename from arch/mips/cpu/mips32/au1x00/config.mk rename to arch/mips/mach-au1x00/config.mk diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig new file mode 100644 index 0000000000..81b0a0158f --- /dev/null +++ b/arch/nds32/Kconfig @@ -0,0 +1,25 @@ +menu "NDS32 architecture" + depends on NDS32 + +config SYS_ARCH + default "nds32" + +choice + prompt "Target select" + +config TARGET_ADP_AG101 + bool "Support adp-ag101" + +config TARGET_ADP_AG101P + bool "Support adp-ag101p" + +config TARGET_ADP_AG102 + bool "Support adp-ag102" + +endchoice + +source "board/AndesTech/adp-ag101/Kconfig" +source "board/AndesTech/adp-ag101p/Kconfig" +source "board/AndesTech/adp-ag102/Kconfig" + +endmenu diff --git a/arch/nds32/Makefile b/arch/nds32/Makefile new file mode 100644 index 0000000000..e1eccba173 --- /dev/null +++ b/arch/nds32/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/nds32/cpu/$(CPU)/start.o + +libs-y += arch/nds32/cpu/$(CPU)/ +libs-y += arch/nds32/lib/ diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk index e93e3a8c28..5ac9f90402 100644 --- a/arch/nds32/config.mk +++ b/arch/nds32/config.mk @@ -8,12 +8,15 @@ # # SPDX-License-Identifier: GPL-2.0+ -CROSS_COMPILE ?= nds32le-linux- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := nds32le-linux- +endif -CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds +CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \ + -T $(srctree)/examples/standalone/nds32.lds PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax PLATFORM_RELFLAGS += -gdwarf-2 -PLATFORM_CPPFLAGS += -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie +PLATFORM_CPPFLAGS += -D__nds32__ -G0 -ffixed-10 -fpie LDFLAGS_u-boot = --gc-sections --relax diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile index b8e0d72739..8ab1fcea26 100644 --- a/arch/nds32/cpu/n1213/Makefile +++ b/arch/nds32/cpu/n1213/Makefile @@ -9,26 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +extra-y = start.o -LIB = $(obj)lib$(CPU).o - -START = start.o - -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(if $(filter ag101,$(SOC)),y) += ag101/ +obj-$(if $(filter ag102,$(SOC)),y) += ag102/ diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile index b53a3eb5f4..c21ce02828 100644 --- a/arch/nds32/cpu/n1213/ag101/Makefile +++ b/arch/nds32/cpu/n1213/ag101/Makefile @@ -10,33 +10,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y := cpu.o timer.o +obj-y := cpu.o timer.o ifndef CONFIG_SKIP_LOWLEVEL_INIT -SOBJS-y := lowlevel_init.o +obj-y += lowlevel_init.o endif ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG -SOBJS-y += watchdog.o +obj-y += watchdog.o endif - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c deleted file mode 100644 index 92ada8ac28..0000000000 --- a/arch/nds32/cpu/n1213/ag101/asm-offsets.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include - -#include - -int main(void) -{ -#ifdef CONFIG_FTSMC020 - OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); - OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); -#endif - BLANK(); -#ifdef CONFIG_FTAHBC020S - OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); - OFFSET(FTAHBC020S_CR, ftahbc02s, cr); -#endif - BLANK(); -#ifdef CONFIG_FTPMU010 - OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0); -#endif - BLANK(); -#ifdef CONFIG_FTSDMC021 - OFFSET(FTSDMC021_TP1, ftsdmc021, tp1); - OFFSET(FTSDMC021_TP2, ftsdmc021, tp2); - OFFSET(FTSDMC021_CR1, ftsdmc021, cr1); - OFFSET(FTSDMC021_CR2, ftsdmc021, cr2); - OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr); - OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr); - OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr); - OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr); -#endif - return 0; -} diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index 810326d200..d6484b9cc5 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -32,6 +32,15 @@ #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR + +/* + * for Orca and Emerald + */ +#define BOARD_ID_REG 0x104 +#define BOARD_ID_FAMILY_MASK 0xfff000 +#define BOARD_ID_FAMILY_V5 0x556000 +#define BOARD_ID_FAMILY_K7 0x74b000 + /* * parameters for the static memory controller */ @@ -47,6 +56,10 @@ #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR) #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6) +/* + * for Orca and Emerald + */ +#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4) #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 /* @@ -100,14 +113,49 @@ mem_init: * we need to set onboard SDRAM before remap and relocation. */ led 0x01 - write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052 - write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151 + + /* + * for Orca and Emerald + * disable write protection and reset bank size + */ + li $r0, SMC_BANK0_CR_A + lwi $r1, [$r0+#0x00] + ori $r1, $r1, 0x8f0 + xori $r1, $r1, 0x8f0 + /* + * check board + */ + li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG + lwi $r3, [$r3] + li $r4, BOARD_ID_FAMILY_MASK + and $r3, $r3, $r4 + li $r4, BOARD_ID_FAMILY_K7 + xor $r4, $r3, $r4 + beqz $r4, use_flash_16bit_boot + /* + * 32-bit mode + */ +use_flash_32bit_boot: + ori $r1, $r1, 0x50 + li $r2, 0x00151151 + j sdram_b0_cr + /* + * 16-bit mode + */ +use_flash_16bit_boot: + ori $r1, $r1, 0x60 + li $r2, 0x00153153 + /* + * SRAM bank0 config + */ +sdram_b0_cr: + swi $r1, [$r0+#0x00] + swi $r2, [$r0+#0x04] /* * config AHB Controller */ led 0x02 - write32 AHBC_BSR6_A, AHBC_BSR6_D /* * config PMU controller @@ -194,7 +242,16 @@ relo_base: * a FLASH connected to bank0. */ led 0x11 - li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */ + /* + * for Orca and Emerald + * read sdram base address automatically + */ + li $r5, AHBC_BSR6_A + lwi $r8, [$r5] + li $r4, 0xfff00000 + and $r4, $r4, $r8 + + li $r5, 0x0 la $r1, relo_base /* get $pc or $lp */ sub $r2, $r0, $r1 @@ -218,6 +275,29 @@ relo_base: write32 SDMC_B1_BSR_A, 0x00001040 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 + /* + * for Orca and Emerald + * extend sdram size from 256MB to 2GB + */ + li $r5, AHBC_BSR6_A + lwi $r6, [$r5] + li $r4, 0xfff0ffff + and $r6 ,$r4 , $r6 + li $r4, 0x000b0000 + or $r6, $r4, $r6 + swi $r6, [$r5] + + /* + * for Orca and Emerald + * extend rom base from 256MB to 2GB + */ + li $r4, AHBC_BSR4_A + lwi $r5, [$r4] + li $r6, 0xffffff + and $r5, $r5, $r6 + li $r6, 0x80000000 + or $r5, $r5, $r6 + swi $r5, [$r4] #endif /* #ifdef CONFIG_MEM_REMAP */ move $lp, $r11 2: diff --git a/arch/nds32/cpu/n1213/ag102/Makefile b/arch/nds32/cpu/n1213/ag102/Makefile index b53a3eb5f4..c21ce02828 100644 --- a/arch/nds32/cpu/n1213/ag102/Makefile +++ b/arch/nds32/cpu/n1213/ag102/Makefile @@ -10,33 +10,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y := cpu.o timer.o +obj-y := cpu.o timer.o ifndef CONFIG_SKIP_LOWLEVEL_INIT -SOBJS-y := lowlevel_init.o +obj-y += lowlevel_init.o endif ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG -SOBJS-y += watchdog.o +obj-y += watchdog.o endif - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/cpu/n1213/ag102/asm-offsets.c deleted file mode 100644 index 4769a9521d..0000000000 --- a/arch/nds32/cpu/n1213/ag102/asm-offsets.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include - -#include - -int main(void) -{ -#ifdef CONFIG_FTSMC020 - OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); - OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); -#endif - BLANK(); -#ifdef CONFIG_FTAHBC020S - OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); - OFFSET(FTAHBC020S_CR, ftahbc02s, cr); -#endif - BLANK(); -#ifdef CONFIG_ANDES_PCU - OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ -#endif - BLANK(); -#ifdef CONFIG_DWCDDR21MCTL - OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */ - OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ - OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */ - OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */ - OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */ - OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */ - OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */ - OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */ - OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */ - OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */ - OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */ - OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */ - OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */ - OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */ - OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */ - OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */ - OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */ - OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ - OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ -#endif - return 0; -} diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h index 8170d28f7c..44e72d414b 100644 --- a/arch/nds32/include/asm/u-boot.h +++ b/arch/nds32/include/asm/u-boot.h @@ -23,7 +23,6 @@ #include typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile index 2f7e155578..6ea96db958 100644 --- a/arch/nds32/lib/Makefile +++ b/arch/nds32/lib/Makefile @@ -9,26 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).o - -COBJS-y += board.o -COBJS-y += cache.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-y += interrupts.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += board.o +obj-y += cache.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-y += interrupts.o diff --git a/arch/nds32/lib/asm-offsets.c b/arch/nds32/lib/asm-offsets.c new file mode 100644 index 0000000000..39e3480bd5 --- /dev/null +++ b/arch/nds32/lib/asm-offsets.c @@ -0,0 +1,82 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include + +#include + +int main(void) +{ + /* + * TODO : Check if each entry in this file is really necessary. + * - struct ftahbc02s + * - struct ftsdmc021 + * - struct andes_pcu + * - struct dwcddr21mctl + * are used only for generating asm-offsets.h. + * It means their offset addresses are referenced only from assembly + * code. Is it better to define the macros directly in headers? + */ + +#ifdef CONFIG_FTSMC020 + OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); + OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); +#endif + BLANK(); +#ifdef CONFIG_FTAHBC020S + OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]); + OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); + OFFSET(FTAHBC020S_CR, ftahbc02s, cr); +#endif + BLANK(); +#ifdef CONFIG_FTPMU010 + OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0); +#endif + BLANK(); +#ifdef CONFIG_FTSDMC021 + OFFSET(FTSDMC021_TP1, ftsdmc021, tp1); + OFFSET(FTSDMC021_TP2, ftsdmc021, tp2); + OFFSET(FTSDMC021_CR1, ftsdmc021, cr1); + OFFSET(FTSDMC021_CR2, ftsdmc021, cr2); + OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr); + OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr); + OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr); + OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr); +#endif + BLANK(); +#ifdef CONFIG_ANDES_PCU + OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ +#endif + BLANK(); +#ifdef CONFIG_DWCDDR21MCTL + OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */ + OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ + OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */ + OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */ + OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */ + OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */ + OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */ + OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */ + OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */ + OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */ + OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */ + OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */ + OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */ + OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */ + OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */ + OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */ + OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */ + OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ + OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ +#endif + + return 0; +} diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 2d4c6231a3..4c06a4866b 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -255,7 +255,6 @@ void board_init_f(ulong bootflag) addr_sp &= ~0x07; debug("New Stack Pointer is: %08lx\n", addr_sp); - gd->bd->bi_baudrate = gd->baudrate; /* Ram isn't board specific, so move it to board code ... */ dram_init_banksize(); display_dram_config(); /* and display it */ diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig new file mode 100644 index 0000000000..b3be7b56c3 --- /dev/null +++ b/arch/nios2/Kconfig @@ -0,0 +1,17 @@ +menu "Nios II architecture" + depends on NIOS2 + +config SYS_ARCH + default "nios2" + +choice + prompt "Target select" + +config TARGET_NIOS2_GENERIC + bool "Support nios2-generic" + +endchoice + +source "board/altera/nios2-generic/Kconfig" + +endmenu diff --git a/arch/nios2/Makefile b/arch/nios2/Makefile new file mode 100644 index 0000000000..18685a9250 --- /dev/null +++ b/arch/nios2/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/nios2/cpu/start.o + +libs-y += arch/nios2/cpu/ +libs-y += arch/nios2/lib/ diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 7d546eff69..9b7c56dc85 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -6,12 +6,16 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= nios2-elf- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := nios2-elf- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000 -PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ +PLATFORM_CPPFLAGS += -D__NIOS2__ PLATFORM_CPPFLAGS += -G0 LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections + +__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/nios2/cpu/Makefile b/arch/nios2/cpu/Makefile index 0834476731..3fe7847160 100644 --- a/arch/nios2/cpu/Makefile +++ b/arch/nios2/cpu/Makefile @@ -5,29 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -SOBJS = exceptions.o -COBJS = cpu.o interrupts.o sysid.o traps.o epcs.o -COBJS += fdt.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = exceptions.o +obj-y += cpu.o interrupts.o sysid.o traps.o +obj-y += fdt.o diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index e0dcbc201f..39ae97221c 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -6,15 +6,17 @@ */ #include -#include -#include +#include #include +DECLARE_GLOBAL_DATA_PTR; + #if defined (CONFIG_SYS_NIOS_SYSID_BASE) extern void display_sysid (void); #endif /* CONFIG_SYS_NIOS_SYSID_BASE */ -int checkcpu (void) +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) { printf ("CPU : Nios-II\n"); #if !defined(CONFIG_SYS_NIOS_SYSID_BASE) @@ -24,6 +26,7 @@ int checkcpu (void) #endif return (0); } +#endif /* CONFIG_DISPLAY_CPUINFO */ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -47,3 +50,11 @@ void dcache_disable(void) { flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE); } + +int arch_cpu_init(void) +{ + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} diff --git a/arch/nios2/cpu/epcs.c b/arch/nios2/cpu/epcs.c deleted file mode 100644 index c83f5eec4e..0000000000 --- a/arch/nios2/cpu/epcs.c +++ /dev/null @@ -1,717 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#if defined(CONFIG_SYS_NIOS_EPCSBASE) -#include -#include -#include -#include - - -/*-----------------------------------------------------------------------*/ -#define SHORT_HELP\ - "epcs - read/write Cyclone EPCS configuration device.\n" - -#define LONG_HELP\ - "\n"\ - "epcs erase start [end]\n"\ - " - erase sector start or sectors start through end.\n"\ - "epcs info\n"\ - " - display EPCS device information.\n"\ - "epcs protect on | off\n"\ - " - turn device protection on or off.\n"\ - "epcs read addr offset count\n"\ - " - read count bytes from offset to addr.\n"\ - "epcs write addr offset count\n"\ - " - write count bytes to offset from addr.\n"\ - "epcs verify addr offset count\n"\ - " - verify count bytes at offset from addr." - - -/*-----------------------------------------------------------------------*/ -/* Operation codes for serial configuration devices - */ -#define EPCS_WRITE_ENA 0x06 /* Write enable */ -#define EPCS_WRITE_DIS 0x04 /* Write disable */ -#define EPCS_READ_STAT 0x05 /* Read status */ -#define EPCS_READ_BYTES 0x03 /* Read bytes */ -#define EPCS_READ_ID 0xab /* Read silicon id */ -#define EPCS_WRITE_STAT 0x01 /* Write status */ -#define EPCS_WRITE_BYTES 0x02 /* Write bytes */ -#define EPCS_ERASE_BULK 0xc7 /* Erase entire device */ -#define EPCS_ERASE_SECT 0xd8 /* Erase sector */ - -/* Device status register bits - */ -#define EPCS_STATUS_WIP (1<<0) /* Write in progress */ -#define EPCS_STATUS_WEL (1<<1) /* Write enable latch */ - -/* Misc - */ -#define EPCS_TIMEOUT 100 /* 100 msec timeout */ - -static nios_spi_t *epcs = (nios_spi_t *)CONFIG_SYS_NIOS_EPCSBASE; - -/*********************************************************************** - * Device access - ***********************************************************************/ -static int epcs_cs (int assert) -{ - ulong start; - unsigned tmp; - - - if (assert) { - tmp = readl (&epcs->control); - writel (tmp | NIOS_SPI_SSO, &epcs->control); - } else { - /* Let all bits shift out */ - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - tmp = readl (&epcs->control); - writel (tmp & ~NIOS_SPI_SSO, &epcs->control); - } - return (0); -} - -static int epcs_tx (unsigned char c) -{ - ulong start; - - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - writel (c, &epcs->txdata); - return (0); -} - -static int epcs_rx (void) -{ - ulong start; - - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - return (readl (&epcs->rxdata)); -} - -static unsigned char bitrev[] = { - 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, - 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f -}; - -static unsigned char epcs_bitrev (unsigned char c) -{ - unsigned char val; - - val = bitrev[c>>4]; - val |= bitrev[c & 0x0f]<<4; - return (val); -} - -static void epcs_rcv (unsigned char *dst, int len) -{ - while (len--) { - epcs_tx (0); - *dst++ = epcs_rx (); - } -} - -static void epcs_rrcv (unsigned char *dst, int len) -{ - while (len--) { - epcs_tx (0); - *dst++ = epcs_bitrev (epcs_rx ()); - } -} - -static void epcs_snd (unsigned char *src, int len) -{ - while (len--) { - epcs_tx (*src++); - epcs_rx (); - } -} - -static void epcs_rsnd (unsigned char *src, int len) -{ - while (len--) { - epcs_tx (epcs_bitrev (*src++)); - epcs_rx (); - } -} - -static void epcs_wr_enable (void) -{ - epcs_cs (1); - epcs_tx (EPCS_WRITE_ENA); - epcs_rx (); - epcs_cs (0); -} - -static unsigned char epcs_status_rd (void) -{ - unsigned char status; - - epcs_cs (1); - epcs_tx (EPCS_READ_STAT); - epcs_rx (); - epcs_tx (0); - status = epcs_rx (); - epcs_cs (0); - return (status); -} - -static void epcs_status_wr (unsigned char status) -{ - epcs_wr_enable (); - epcs_cs (1); - epcs_tx (EPCS_WRITE_STAT); - epcs_rx (); - epcs_tx (status); - epcs_rx (); - epcs_cs (0); - return; -} - -/*********************************************************************** - * Device information - ***********************************************************************/ - -static struct epcs_devinfo_t devinfo[] = { - { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, - { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, - { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c }, - { "EPCS64", 0x16, 23,128, 16, 8, 0x1c }, - { 0, 0, 0, 0, 0, 0 } -}; - -int epcs_reset (void) -{ - /* When booting from an epcs controller, the epcs bootrom - * code may leave the slave select in an asserted state. - * This causes two problems: (1) The initial epcs access - * will fail -- not a big deal, and (2) a software reset - * will cause the bootrom code to hang since it does not - * ensure the select is negated prior to first access -- a - * big deal. Here we just negate chip select and everything - * gets better :-) - */ - epcs_cs (0); /* Negate chip select */ - return (0); -} - -epcs_devinfo_t *epcs_dev_find (void) -{ - unsigned char buf[4]; - unsigned char id; - int i; - struct epcs_devinfo_t *dev = NULL; - - /* Read silicon id requires 3 "dummy bytes" before it's put - * on the wire. - */ - buf[0] = EPCS_READ_ID; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rcv (buf,1); - if (epcs_cs (0) == -1) - return (NULL); - id = buf[0]; - - /* Find the info struct */ - i = 0; - while (devinfo[i].name) { - if (id == devinfo[i].id) { - dev = &devinfo[i]; - break; - } - i++; - } - - return (dev); -} - -/*********************************************************************** - * Misc Utilities - ***********************************************************************/ -int epcs_cfgsz (void) -{ - int sz = 0; - unsigned char buf[128]; - unsigned char *p; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - /* Read in the first 128 bytes of the device */ - buf[0] = EPCS_READ_BYTES; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rrcv (buf, sizeof(buf)); - epcs_cs (0); - - /* Search for the starting 0x6a which is followed by the - * 4-byte 'register' and 4-byte bit-count. - */ - p = buf; - while (p < buf + sizeof(buf)-8) { - if ( *p == 0x6a ) { - /* Point to bit count and extract */ - p += 5; - sz = *p++; - sz |= *p++ << 8; - sz |= *p++ << 16; - sz |= *p++ << 24; - /* Convert to byte count */ - sz += 7; - sz >>= 3; - } else if (*p == 0xff) { - /* 0xff is ok ... just skip */ - p++; - continue; - } else { - /* Not 0xff or 0x6a ... something's not - * right ... report 'unknown' (sz=0). - */ - break; - } - } - return (sz); -} - -int epcs_erase (unsigned start, unsigned end) -{ - unsigned off, sectsz; - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev || (start>end)) - return (-1); - - /* Erase the requested sectors. An address is required - * that lies within the requested sector -- we'll just - * use the first address in the sector. - */ - printf ("epcs erasing sector %d ", start); - if (start != end) - printf ("to %d ", end); - sectsz = (1 << dev->sz_sect); - while (start <= end) { - off = start * sectsz; - start++; - - buf[0] = EPCS_ERASE_SECT; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_wr_enable (); - epcs_cs (1); - epcs_snd (buf,4); - epcs_cs (0); - - printf ("."); /* Some user feedback */ - - /* Wait for erase to complete */ - while (epcs_status_rd() & EPCS_STATUS_WIP) - ; - } - printf (" done.\n"); - return (0); -} - -int epcs_read (ulong addr, ulong off, ulong cnt) -{ - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - buf[0] = EPCS_READ_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rrcv ((unsigned char *)addr, cnt); - epcs_cs (0); - - return (0); -} - -int epcs_write (ulong addr, ulong off, ulong cnt) -{ - ulong wrcnt; - unsigned pgsz; - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - pgsz = (1<sz_page); - while (cnt) { - if (off % pgsz) - wrcnt = pgsz - (off % pgsz); - else - wrcnt = pgsz; - wrcnt = (wrcnt > cnt) ? cnt : wrcnt; - - buf[0] = EPCS_WRITE_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_wr_enable (); - epcs_cs (1); - epcs_snd (buf,4); - epcs_rsnd ((unsigned char *)addr, wrcnt); - epcs_cs (0); - - /* Wait for write to complete */ - while (epcs_status_rd() & EPCS_STATUS_WIP) - ; - - cnt -= wrcnt; - off += wrcnt; - addr += wrcnt; - } - - return (0); -} - -int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err) -{ - ulong rdcnt; - unsigned char buf[256]; - unsigned char *start,*end; - int i; - - start = end = (unsigned char *)addr; - while (cnt) { - rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; - epcs_read ((ulong)buf, off, rdcnt); - for (i=0; isz_sect); - off = sectsz * sect; - end = off + sectsz; - - while (off < end) { - epcs_read ((ulong)buf, off, sizeof(buf)); - for (i=0; i < sizeof(buf); i++) { - if (buf[i] != 0xff) { - *offset = off + i; - return (0); - } - } - off += sizeof(buf); - } - return (1); -} - - -/*********************************************************************** - * Commands - ***********************************************************************/ -static -void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - int i; - unsigned char stat; - unsigned tmp; - int erased; - - /* Basic device info */ - printf ("%s: %d kbytes (%d sectors x %d kbytes," - " %d bytes/page)\n", - dev->name, 1 << (dev->size-10), - dev->num_sects, 1 << (dev->sz_sect-10), - 1 << dev->sz_page ); - - /* Status -- for now protection is all-or-nothing */ - stat = epcs_status_rd(); - printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", - stat, - (stat & EPCS_STATUS_WIP) ? 1 : 0, - (stat & EPCS_STATUS_WEL) ? 1 : 0, - (stat & dev->prot_mask) ? "on" : "off" ); - - /* Configuration */ - tmp = epcs_cfgsz (); - if (tmp) { - printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); - } else { - printf ("config: unknown\n" ); - } - - /* Sector info */ - for (i=0; (i < dev->num_sects) && (argc > 1); i++) { - erased = epcs_sect_erased (i, &tmp, dev); - if ((i & 0x03) == 0) printf ("\n"); - printf ("%4d: %07x ", - i, i*(1<sz_sect) ); - if (erased) - printf ("E "); - else - printf (" "); - } - printf ("\n"); - - return; -} - -static -void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - unsigned start,end; - - if ((argc < 3) || (argc > 4)) { - printf ("USAGE: epcs erase sect [end]\n"); - return; - } - if ((epcs_status_rd() & dev->prot_mask) != 0) { - printf ( "epcs: device protected.\n"); - return; - } - - start = simple_strtoul (argv[2], NULL, 10); - if (argc > 3) - end = simple_strtoul (argv[3], NULL, 10); - else - end = start; - if ((start >= dev->num_sects) || (start > end)) { - printf ("epcs: invalid sector range: [%d:%d]\n", - start, end ); - return; - } - - epcs_erase (start, end); - - return; -} - -static -void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - unsigned char stat; - - /* For now protection is all-or-nothing to keep things - * simple. The protection bits don't map in a linear - * fashion ... and we would rather protect the bottom - * of the device since it contains the config data and - * leave the top unprotected for app use. But unfortunately - * protection works from top-to-bottom so it does - * really help very much from a software app point-of-view. - */ - if (argc < 3) { - printf ("USAGE: epcs protect on | off\n"); - return; - } - if (!dev) - return; - - /* Protection on/off is just a matter of setting/clearing - * all protection bits in the status register. - */ - stat = epcs_status_rd (); - if (strcmp ("on", argv[2]) == 0) { - stat |= dev->prot_mask; - } else if (strcmp ("off", argv[2]) == 0 ) { - stat &= ~dev->prot_mask; - } else { - printf ("epcs: unknown protection: %s\n", argv[2]); - return; - } - epcs_status_wr (stat); - return; -} - -static -void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - ulong addr,off,cnt; - ulong sz; - - if (argc < 5) { - printf ("USAGE: epcs read addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n", - addr, off, cnt); - epcs_read (addr, off, cnt); - - return; -} - -static -void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: epcs write addr offset count\n"); - return; - } - if ((epcs_status_rd() & dev->prot_mask) != 0) { - printf ( "epcs: device protected.\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - epcs_write (addr, off, cnt); - if (epcs_verify (addr, off, cnt, &err) != 0) - printf ("epcs: write error at offset %06lx\n", err); - - return; -} - -static -void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: epcs verify addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - if (epcs_verify (addr, off, cnt, &err) != 0) - printf ("epcs: verify error at offset %06lx\n", err); - - return; -} - -/*-----------------------------------------------------------------------*/ -int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int len; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) { - printf ("epcs: device not found.\n"); - return (-1); - } - - if (argc < 2) { - do_epcs_info (dev, argc, argv); - return (0); - } - - len = strlen (argv[1]); - if (strncmp ("info", argv[1], len) == 0) { - do_epcs_info (dev, argc, argv); - } else if (strncmp ("erase", argv[1], len) == 0) { - do_epcs_erase (dev, argc, argv); - } else if (strncmp ("protect", argv[1], len) == 0) { - do_epcs_protect (dev, argc, argv); - } else if (strncmp ("read", argv[1], len) == 0) { - do_epcs_read (dev, argc, argv); - } else if (strncmp ("write", argv[1], len) == 0) { - do_epcs_write (dev, argc, argv); - } else if (strncmp ("verify", argv[1], len) == 0) { - do_epcs_verify (dev, argc, argv); - } else { - printf ("epcs: unknown operation: %s\n", argv[1]); - } - - return (0); -} - -/*-----------------------------------------------------------------------*/ - - -U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP ); - -#endif /* CONFIG_NIOS_EPCS */ diff --git a/arch/nios2/cpu/exceptions.S b/arch/nios2/cpu/exceptions.S index 50200d283c..f5fa8d7453 100644 --- a/arch/nios2/cpu/exceptions.S +++ b/arch/nios2/cpu/exceptions.S @@ -2,7 +2,7 @@ * (C) Copyright 2004, Psyent Corporation * Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c index 4d88f169df..5024682088 100644 --- a/arch/nios2/cpu/fdt.c +++ b/arch/nios2/cpu/fdt.c @@ -18,11 +18,13 @@ DECLARE_GLOBAL_DATA_PTR; -void __ft_board_setup(void *blob, bd_t *bd) +int __ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } -void ft_board_setup(void *blob, bd_t *bd) \ +int ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup"))); void ft_cpu_setup(void *blob, bd_t *bd) @@ -32,5 +34,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob); + + return 0; } #endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */ diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index c4bed2253d..9d7e193e28 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -9,8 +9,7 @@ */ -#include -#include +#include #include #include #include @@ -21,6 +20,25 @@ #include #endif +typedef volatile struct { + unsigned status; /* Timer status reg */ + unsigned control; /* Timer control reg */ + unsigned periodl; /* Timeout period low */ + unsigned periodh; /* Timeout period high */ + unsigned snapl; /* Snapshot low */ + unsigned snaph; /* Snapshot high */ +} nios_timer_t; + +/* status register */ +#define NIOS_TIMER_TO (1 << 0) /* Timeout */ +#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ + +/* control register */ +#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ +#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ +#define NIOS_TIMER_START (1 << 2) /* Start timer */ +#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ + #if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ) #error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation) #endif diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 7ce0d34d7f..6af9b4e943 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -134,11 +134,12 @@ _reloc: mov fp, sp /* - * Call board_init -- never returns + * Call board_init_f -- never returns */ - movhi r4, %hi(board_init@h) - ori r4, r4, %lo(board_init@h) - callr r4 + mov r4, r0 + movhi r2, %hi(board_init_f@h) + ori r2, r2, %lo(board_init_f@h) + callr r2 /* NEVER RETURNS -- but branch to the _start just * in case ;-) @@ -146,6 +147,31 @@ _reloc: br _start + +/* + * relocate_code -- Nios2 handles the relocation above. But + * the generic board code monkeys with the heap, stack, etc. + * (it makes some assumptions that may not be appropriate + * for Nios). Nevertheless, we capitulate here. + * + * We'll call the board_init_r from here since this isn't + * supposed to return. + * + * void relocate_code (ulong sp, gd_t *global_data, + * ulong reloc_addr) + * __attribute__ ((noreturn)); + */ + .text + .global relocate_code + +relocate_code: + mov sp, r4 /* Set the new sp */ + mov r4, r5 + movhi r8, %hi(board_init_r@h) + ori r8, r8, %lo(board_init_r@h) + callr r8 + ret + /* * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in * the core. For simple delay loops, we do our best by counting diff --git a/arch/nios2/cpu/sysid.c b/arch/nios2/cpu/sysid.c index 943bff8d29..50819b2424 100644 --- a/arch/nios2/cpu/sysid.c +++ b/arch/nios2/cpu/sysid.c @@ -11,12 +11,16 @@ #include #include -#include #include +typedef volatile struct { + unsigned id; /* The system build id */ + unsigned timestamp; /* Timestamp */ +} nios_sysid_t; + void display_sysid (void) { - struct nios_sysid_t *sysid = (struct nios_sysid_t *)CONFIG_SYS_NIOS_SYSID_BASE; + nios_sysid_t *sysid = (nios_sysid_t *)CONFIG_SYS_NIOS_SYSID_BASE; struct tm t; char asc[32]; time_t stamp; diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds index d7d5c6085d..6e174be2c0 100644 --- a/arch/nios2/cpu/u-boot.lds +++ b/arch/nios2/cpu/u-boot.lds @@ -2,9 +2,10 @@ * (C) Copyright 2004, Psyent Corporation * Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ +#include OUTPUT_FORMAT("elf32-littlenios2") OUTPUT_ARCH(nios2) @@ -12,6 +13,7 @@ ENTRY(_start) SECTIONS { + . = CONFIG_SYS_MONITOR_BASE; .text : { arch/nios2/cpu/start.o (.text) diff --git a/arch/nios2/include/asm/config.h b/arch/nios2/include/asm/config.h index cd29734789..476a32bdc6 100644 --- a/arch/nios2/include/asm/config.h +++ b/arch/nios2/include/asm/config.h @@ -7,4 +7,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_GENERIC_GLOBAL_DATA + #endif diff --git a/include/nios2.h b/arch/nios2/include/asm/nios2.h similarity index 95% rename from include/nios2.h rename to arch/nios2/include/asm/nios2.h index 0539ec3450..abe4df3581 100644 --- a/include/nios2.h +++ b/arch/nios2/include/asm/nios2.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __NIOS2_H__ -#define __NIOS2_H__ +#ifndef __ASM_NIOS2_H__ +#define __ASM_NIOS2_H__ /*------------------------------------------------------------------------ * Control registers -- use with wrctl() & rdctl() @@ -37,4 +37,4 @@ #define CACHE_BYPASS(a) ((a) | 0x80000000) #define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) -#endif /* __NIOS2_H__ */ +#endif /* __ASM_NIOS2_H__ */ diff --git a/arch/nios2/include/asm/posix_types.h b/arch/nios2/include/asm/posix_types.h index 673364099a..6b6c39bcc0 100644 --- a/arch/nios2/include/asm/posix_types.h +++ b/arch/nios2/include/asm/posix_types.h @@ -16,7 +16,11 @@ typedef int __kernel_pid_t; typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; +#ifdef __GNUC__ +typedef __SIZE_TYPE__ __kernel_size_t; +#else typedef unsigned long __kernel_size_t; +#endif typedef long __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h index 6849b4ae9f..cb02e98a82 100644 --- a/arch/nios2/include/asm/u-boot.h +++ b/arch/nios2/include/asm/u-boot.h @@ -15,16 +15,7 @@ #ifndef __ASM_NIOS2_U_BOOT_H_ #define __ASM_NIOS2_U_BOOT_H_ -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ -} bd_t; +#include /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_NIOS2 diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile index d5dce67abe..079378a905 100644 --- a/arch/nios2/lib/Makefile +++ b/arch/nios2/lib/Makefile @@ -5,28 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).o - -SOBJS-y += cache.o - -COBJS-y += board.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-y += libgcc.o -COBJS-y += time.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += cache.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-y += libgcc.o +obj-y += time.o diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c deleted file mode 100644 index bb1a8a7340..0000000000 --- a/arch/nios2/lib/board.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif -#if defined(CONFIG_SYS_NIOS_EPCSBASE) -#include -#endif -#ifdef CONFIG_CMD_NAND -#include /* cannot even include nand.h if it isnt configured */ -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - - -typedef int (init_fnc_t) (void); - - -/************************************************************************ - * Initialization sequence * - ***********************************************************************/ - -init_fnc_t *init_sequence[] = { -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, /* Call board-specific init code early.*/ -#endif -#if defined(CONFIG_SYS_NIOS_EPCSBASE) - epcs_reset, -#endif - - env_init, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, - NULL, /* Terminate this list */ -}; - - -/***********************************************************************/ -void board_init(void) -{ - bd_t *bd; - init_fnc_t **init_fnc_ptr; - static gd_t gd_data; - static bd_t bd_data; - - /* Pointer is writable since we allocated a register for it. */ - gd = &gd_data; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("" : : : "memory"); - - gd->bd = &bd_data; - gd->baudrate = CONFIG_BAUDRATE; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; -#ifndef CONFIG_SYS_NO_FLASH - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; -#endif -#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -#endif - bd->bi_baudrate = CONFIG_BAUDRATE; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - WATCHDOG_RESET(); - if ((*init_fnc_ptr) () != 0) - hang(); - } - - WATCHDOG_RESET(); - - /* The Malloc area is immediately below the monitor copy in RAM */ - mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); - -#ifndef CONFIG_SYS_NO_FLASH - WATCHDOG_RESET(); - bd->bi_flashsize = flash_init(); -#endif - -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); -#endif - -#ifdef CONFIG_GENERIC_MMC - puts("MMC: "); - mmc_initialize(bd); -#endif - - WATCHDOG_RESET(); - env_relocate(); - - WATCHDOG_RESET(); - stdio_init(); - jumptable_init(); - console_init_r(); - - WATCHDOG_RESET(); - interrupt_init(); - -#if defined(CONFIG_BOARD_LATE_INIT) - board_late_init(); -#endif - -#if defined(CONFIG_CMD_NET) - puts("Net: "); - eth_initialize(bd); -#endif - - /* main_loop */ - for (;;) { - WATCHDOG_RESET(); - main_loop(); - } -} diff --git a/arch/nios2/lib/libgcc.c b/arch/nios2/lib/libgcc.c index 3caee19340..cf1b836925 100644 --- a/arch/nios2/lib/libgcc.c +++ b/arch/nios2/lib/libgcc.c @@ -548,7 +548,7 @@ __mulsi3 (SItype a, SItype b) while (cnt) { if (cnt & 1) - { + { res += b; } b <<= 1; diff --git a/arch/nios2/lib/longlong.h b/arch/nios2/lib/longlong.h index 63c64ed74d..45ec5f0f19 100644 --- a/arch/nios2/lib/longlong.h +++ b/arch/nios2/lib/longlong.h @@ -3,6 +3,7 @@ 2005 Free Software Foundation, Inc. * SPDX-License-Identifier: GPL-2.0+ + */ /* You have to define the following before including this file: diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig new file mode 100644 index 0000000000..4d62b4c977 --- /dev/null +++ b/arch/openrisc/Kconfig @@ -0,0 +1,17 @@ +menu "OpenRISC architecture" + depends on OPENRISC + +config SYS_ARCH + default "openrisc" + +choice + prompt "Target select" + +config TARGET_OPENRISC_GENERIC + bool "Support openrisc-generic" + +endchoice + +source "board/openrisc/openrisc-generic/Kconfig" + +endmenu diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile new file mode 100644 index 0000000000..c4da3ce9d8 --- /dev/null +++ b/arch/openrisc/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/openrisc/cpu/start.o + +libs-y += arch/openrisc/cpu/ +libs-y += arch/openrisc/lib/ diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk index 13015ebc21..cd95f24b1f 100644 --- a/arch/openrisc/config.mk +++ b/arch/openrisc/config.mk @@ -5,12 +5,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= or32-elf- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := or32-elf- +endif # r10 used for global object pointer, already set in OR32 GCC but just to be # clear -PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10 +PLATFORM_CPPFLAGS += -D__OR1K__ -ffixed-r10 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 - -LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/openrisc/cpu/Makefile b/arch/openrisc/cpu/Makefile index 863d9b3e86..fc47d666fe 100644 --- a/arch/openrisc/cpu/Makefile +++ b/arch/openrisc/cpu/Makefile @@ -5,27 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS-y = cache.o cpu.o exceptions.o interrupts.o - -SRCS := $(START:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cache.o cpu.o exceptions.o interrupts.o diff --git a/arch/openrisc/cpu/cpu.c b/arch/openrisc/cpu/cpu.c index f238fe4c60..272656a361 100644 --- a/arch/openrisc/cpu/cpu.c +++ b/arch/openrisc/cpu/cpu.c @@ -138,8 +138,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Code the jump to __reset here as the compiler is prone to emitting a bad jump instruction if the function is in flash */ __asm__("l.movhi r1,hi(__reset); \ - l.ori r1,r1,lo(__reset); \ - l.jr r1"); + l.ori r1,r1,lo(__reset); \ + l.jr r1"); /* not reached, __reset does not return */ return 0; } diff --git a/arch/openrisc/cpu/start.S b/arch/openrisc/cpu/start.S index c54b0cfc98..1ae3b75f3b 100644 --- a/arch/openrisc/cpu/start.S +++ b/arch/openrisc/cpu/start.S @@ -1,6 +1,7 @@ /* * (C) Copyright 2011, Stefan Kristiansson * (C) Copyright 2011, Julius Baxter + * (C) Copyright 2014, Franck Jullien * * SPDX-License-Identifier: GPL-2.0+ */ @@ -40,9 +41,48 @@ __reset: l.ori r3,r0,SPR_SR_SM l.mtspr r0,r3,SPR_SR + l.jal _cur + l.nop +_cur: + l.ori r8, r9, 0 /* Get _cur current address */ + + l.movhi r3, hi(_cur) + l.ori r3, r3, lo(_cur) + l.sfeq r8, r3 /* If we are running at the linked address */ + l.bf _no_vector_reloc /* there is not need for relocation */ + l.sub r8, r8, r3 + + l.mfspr r4, r0, SPR_CPUCFGR + l.andi r4, r4, SPR_CPUCFGR_EVBARP /* Exception Vector Base Address Register present ? */ + l.sfnei r4,0 + l.bnf _reloc_vectors + l.movhi r5, 0 /* Destination */ + + l.mfspr r4, r0, SPR_EVBAR + l.add r5, r5, r4 + +_reloc_vectors: + /* Relocate vectors*/ + l.movhi r5, 0 /* Destination */ + l.movhi r6, hi(__start) /* Length */ + l.ori r6, r6, lo(__start) + l.ori r3, r8, 0 + +.L_relocvectors: + l.lwz r7, 0(r3) + l.sw 0(r5), r7 + l.addi r5, r5, 4 + l.sfeq r5, r6 + l.bnf .L_relocvectors + l.addi r3, r3, 4 + +_no_vector_reloc: + /* Relocate u-boot */ - l.movhi r3,hi(__start) /* source start address */ + l.movhi r3,hi(__start) /* source start offset */ l.ori r3,r3,lo(__start) + l.add r3,r8,r3 + l.movhi r4,hi(_stext) /* dest start address */ l.ori r4,r4,lo(_stext) l.movhi r5,hi(__end) /* dest end address */ @@ -56,19 +96,6 @@ __reset: l.bf .L_reloc l.addi r4,r4,4 /* delay slot */ -#ifdef CONFIG_SYS_RELOCATE_VECTORS - /* Relocate vectors from 0xf0000000 to 0x00000000 */ - l.movhi r4, 0xf000 /* source */ - l.movhi r5, 0 /* destination */ - l.addi r6, r5, CONFIG_SYS_VECTORS_LEN /* length */ -.L_relocvectors: - l.lwz r7, 0(r4) - l.sw 0(r5), r7 - l.addi r5, r5, 4 - l.sfeq r5,r6 - l.bnf .L_relocvectors - l.addi r4,r4, 4 -#endif l.movhi r4,hi(_start) l.ori r4,r4,lo(_start) l.jr r4 diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h index a863b3e0e4..e30d2104a0 100644 --- a/arch/openrisc/include/asm/spr-defs.h +++ b/arch/openrisc/include/asm/spr-defs.h @@ -46,6 +46,11 @@ #define SPR_ICCFGR (SPRGROUP_SYS + 6) #define SPR_DCFGR (SPRGROUP_SYS + 7) #define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_VR2 (SPRGROUP_SYS + 9) +#define SPR_AVR (SPRGROUP_SYS + 10) +#define SPR_EVBAR (SPRGROUP_SYS + 11) +#define SPR_AECR (SPRGROUP_SYS + 12) +#define SPR_AESR (SPRGROUP_SYS + 13) #define SPR_NPC (SPRGROUP_SYS + 16) #define SPR_SR (SPRGROUP_SYS + 17) #define SPR_PPC (SPRGROUP_SYS + 18) @@ -161,7 +166,13 @@ #define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ #define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ #define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ -#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ +#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */ +#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */ +#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */ +#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */ +#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */ + /* Arithmetic Exception Status Register (AESR) presents */ +#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */ /* * Bit definitions for the Debug configuration register and other diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h index 5c288a85ff..cdb8ff996e 100644 --- a/arch/openrisc/include/asm/u-boot.h +++ b/arch/openrisc/include/asm/u-boot.h @@ -16,7 +16,6 @@ #define _U_BOOT_H_ typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile index b2218c990f..dfa72d915f 100644 --- a/arch/openrisc/lib/Makefile +++ b/arch/openrisc/lib/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).o - -SOBJS-y += - -COBJS-y += board.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-y += timer.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += board.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-y += timer.o diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c index 391d1e19c5..234668538c 100644 --- a/arch/openrisc/lib/board.c +++ b/arch/openrisc/lib/board.c @@ -84,7 +84,6 @@ void board_init(void) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { WATCHDOG_RESET(); diff --git a/arch/openrisc/lib/bootm.c b/arch/openrisc/lib/bootm.c index 3df4d9ec1d..a18748f61f 100644 --- a/arch/openrisc/lib/bootm.c +++ b/arch/openrisc/lib/bootm.c @@ -8,7 +8,7 @@ * Michal SIMEK * Yasushi SHOJI * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig new file mode 100644 index 0000000000..8e5a3e2074 --- /dev/null +++ b/arch/powerpc/Kconfig @@ -0,0 +1,49 @@ +menu "PowerPC architecture" + depends on PPC + +config SYS_ARCH + default "powerpc" + +choice + prompt "CPU select" + +config MPC512X + bool "MPC512X" + +config 5xx + bool "MPC5xx" + +config MPC5xxx + bool "MPC5xxx" + +config MPC8260 + bool "MPC8260" + +config MPC83xx + bool "MPC83xx" + +config MPC85xx + bool "MPC85xx" + +config MPC86xx + bool "MPC86xx" + +config 8xx + bool "MPC8xx" + +config 4xx + bool "PPC4xx" + +endchoice + +source "arch/powerpc/cpu/mpc512x/Kconfig" +source "arch/powerpc/cpu/mpc5xx/Kconfig" +source "arch/powerpc/cpu/mpc5xxx/Kconfig" +source "arch/powerpc/cpu/mpc8260/Kconfig" +source "arch/powerpc/cpu/mpc83xx/Kconfig" +source "arch/powerpc/cpu/mpc85xx/Kconfig" +source "arch/powerpc/cpu/mpc86xx/Kconfig" +source "arch/powerpc/cpu/mpc8xx/Kconfig" +source "arch/powerpc/cpu/ppc4xx/Kconfig" + +endmenu diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile new file mode 100644 index 0000000000..8aa1d603fa --- /dev/null +++ b/arch/powerpc/Makefile @@ -0,0 +1,11 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/powerpc/cpu/$(CPU)/start.o +head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o +head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o + +libs-y += arch/powerpc/cpu/$(CPU)/ +libs-y += arch/powerpc/cpu/ +libs-y += arch/powerpc/lib/ diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index e6bb935729..fec02f2b82 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -5,12 +5,16 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= ppc_8xx- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := ppc_8xx- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections -PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections -PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ +LDFLAGS_FINAL += --bss-plt +PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \ + -meabi +PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 PLATFORM_LDFLAGS += -n # Support generic board on PPC @@ -32,5 +36,14 @@ endif # Only test once ifneq ($(CONFIG_SPL_BUILD),y) -ALL-y += checkgcc4 +archprepare: checkgcc4 + +# GCC 3.x is reported to have problems generating the type of relocation +# that U-Boot wants. +# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html +checkgcc4: + @if test $(call cc-version) -lt 0400; then \ + echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \ + false; \ + fi endif diff --git a/arch/powerpc/cpu/74xx_7xx/Makefile b/arch/powerpc/cpu/74xx_7xx/Makefile deleted file mode 100644 index de9b4a72cd..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -SOBJS = cache.o kgdb.o io.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/powerpc/cpu/74xx_7xx/cache.S b/arch/powerpc/cpu/74xx_7xx/cache.S deleted file mode 100644 index 66c72983d4..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/cache.S +++ /dev/null @@ -1,404 +0,0 @@ -#include -#include <74xx_7xx.h> -#include - -#include -#include - -#include -#include - -#ifndef CACHE_LINE_SIZE -# define CACHE_LINE_SIZE L1_CACHE_BYTES -#endif - -#if CACHE_LINE_SIZE == 128 -#define LG_CACHE_LINE_SIZE 7 -#elif CACHE_LINE_SIZE == 32 -#define LG_CACHE_LINE_SIZE 5 -#elif CACHE_LINE_SIZE == 16 -#define LG_CACHE_LINE_SIZE 4 -#elif CACHE_LINE_SIZE == 8 -#define LG_CACHE_LINE_SIZE 3 -#else -# error "Invalid cache line size!" -#endif - -/* - * Invalidate L1 instruction cache. - */ -_GLOBAL(invalidate_l1_instruction_cache) - mfspr r3,PVR - rlwinm r3,r3,16,16,31 - cmpi 0,r3,1 - beqlr /* for 601, do nothing */ - /* 603/604 processor - use invalidate-all bit in HID0 */ - mfspr r3,HID0 - ori r3,r3,HID0_ICFI - mtspr HID0,r3 - isync - blr - -/* - * Invalidate L1 data cache. - */ -_GLOBAL(invalidate_l1_data_cache) - mfspr r3,HID0 - ori r3,r3,HID0_DCFI - mtspr HID0,r3 - isync - blr - -/* - * Flush data cache. - */ -_GLOBAL(flush_dcache) - lis r3,0 - lis r5,CACHE_LINE_SIZE -flush: - cmp 0,1,r3,r5 - bge done - lwz r5,0(r3) - lis r5,CACHE_LINE_SIZE - addi r3,r3,0x4 - b flush -done: - blr -/* - * Write any modified data cache blocks out to memory - * and invalidate the corresponding instruction cache blocks. - * This is a no-op on the 601. - * - * flush_icache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(flush_icache_range) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CACHE_LINE_SIZE - bdnz 2b - sync /* additional sync needed on g4 */ - isync - blr -/* - * Write any modified data cache blocks out to memory. - * Does not invalidate the corresponding cache lines (especially for - * any corresponding instruction cache). - * - * clean_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(clean_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 /* align r3 down to cache line */ - subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ - add r4,r4,r5 /* r4 += cache_line_size-1 */ - srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ - beqlr /* if r4 == 0 return */ - mtctr r4 /* ctr = r4 */ - - sync -1: dcbst 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - blr - -/* - * Write any modified data cache blocks out to memory - * and invalidate the corresponding instruction cache blocks. - * - * flush_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(flush_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - - sync -1: dcbf 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbf's to get to ram */ - blr - -/* - * Like above, but invalidate the D-cache. This is used by the 8xx - * to invalidate the cache so the PPC core doesn't get stale data - * from the CPM (no cache snooping here :-). - * - * invalidate_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(invalidate_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - - sync -1: dcbi 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbi's to get to ram */ - blr - -/* - * Flush a particular page from the data cache to RAM. - * Note: this is necessary because the instruction cache does *not* - * snoop from the data cache. - * This is a no-op on the 601 which has a unified cache. - * - * void __flush_page_to_ram(void *page) - */ -_GLOBAL(__flush_page_to_ram) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - rlwinm r3,r3,0,0,19 /* Get page base address */ - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ - mtctr r4 - mr r6,r3 -0: dcbst 0,r3 /* Write line to ram */ - addi r3,r3,CACHE_LINE_SIZE - bdnz 0b - sync - mtctr r4 -1: icbi 0,r6 - addi r6,r6,CACHE_LINE_SIZE - bdnz 1b - sync - isync - blr - -/* - * Flush a particular page from the instruction cache. - * Note: this is necessary because the instruction cache does *not* - * snoop from the data cache. - * This is a no-op on the 601 which has a unified cache. - * - * void __flush_icache_page(void *page) - */ -_GLOBAL(__flush_icache_page) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ - mtctr r4 -1: icbi 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync - isync - blr - -/* - * Clear a page using the dcbz instruction, which doesn't cause any - * memory traffic (except to write out any cache lines which get - * displaced). This only works on cacheable memory. - */ -_GLOBAL(clear_page) - li r0,4096/CACHE_LINE_SIZE - mtctr r0 -1: dcbz 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - blr - -/* - * Enable L1 Instruction cache - */ -_GLOBAL(icache_enable) - mfspr r3, HID0 - li r5, HID0_ICFI|HID0_ILOCK - andc r3, r3, r5 - ori r3, r3, HID0_ICE - ori r5, r3, HID0_ICFI - mtspr HID0, r5 - mtspr HID0, r3 - isync - blr - -/* - * Disable L1 Instruction cache - */ -_GLOBAL(icache_disable) - mflr r4 - bl invalidate_l1_instruction_cache /* uses r3 */ - sync - mtlr r4 - mfspr r3, HID0 - li r5, 0 - ori r5, r5, HID0_ICE - andc r3, r3, r5 - mtspr HID0, r3 - isync - blr - -/* - * Is instruction cache enabled? - */ -_GLOBAL(icache_status) - mfspr r3, HID0 - andi. r3, r3, HID0_ICE - blr - - -_GLOBAL(l1dcache_enable) - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ - sync - blr - -/* - * Enable data cache(s) - L1 and optionally L2 - * Calls l2cache_enable. LR saved in r5 - */ -_GLOBAL(dcache_enable) - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ - sync -#ifdef CONFIG_SYS_L2 - mflr r5 - bl l2cache_enable /* uses r3 and r4 */ - sync - mtlr r5 -#endif - blr - - -/* - * Disable data cache(s) - L1 and optionally L2 - * Calls flush_dcache and l2cache_disable_no_flush. - * LR saved in r4 - */ -_GLOBAL(dcache_disable) - mflr r4 /* save link register */ - bl flush_dcache /* uses r3 and r5 */ - sync - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - li r5, HID0_DCE|HID0_DCFI - andc r3, r3, r5 /* no enable, no invalidate */ - mtspr HID0, r3 - sync -#ifdef CONFIG_SYS_L2 - bl l2cache_disable_no_flush /* uses r3 */ -#endif - mtlr r4 /* restore link register */ - blr - -/* - * Is data cache enabled? - */ -_GLOBAL(dcache_status) - mfspr r3, HID0 - andi. r3, r3, HID0_DCE - blr - -/* - * Invalidate L2 cache using L2I and polling L2IP or L2I - */ -_GLOBAL(l2cache_invalidate) - sync - mfspr r3, l2cr - oris r3, r3, L2CR_L2I@h - sync - mtspr l2cr, r3 - sync - mfspr r3, PVR - sync - rlwinm r3, r3, 16,16,31 - cmpli 0,r3,0x8000 /* 7451, 7441 */ - beq 0,inv_7450 - cmpli 0,r3,0x8001 /* 7455, 7445 */ - beq 0,inv_7450 - cmpli 0,r3,0x8002 /* 7457, 7447 */ - beq 0,inv_7450 - cmpli 0,r3,0x8003 /* 7447A */ - beq 0,inv_7450 - cmpli 0,r3,0x8004 /* 7448 */ - beq 0,inv_7450 -invl2: - mfspr r3, l2cr - andi. r3, r3, L2CR_L2IP - bne invl2 - /* turn off the global invalidate bit */ - mfspr r3, l2cr - rlwinm r3, r3, 0, 11, 9 - sync - mtspr l2cr, r3 - sync - blr -inv_7450: - mfspr r3, l2cr - andis. r3, r3, L2CR_L2I@h - bne inv_7450 - blr - -/* - * Enable L2 cache - * Calls l2cache_invalidate. LR is saved in r4 - */ -_GLOBAL(l2cache_enable) - mflr r4 /* save link register */ - bl l2cache_invalidate /* uses r3 */ - sync - lis r3, L2_ENABLE@h - ori r3, r3, L2_ENABLE@l - mtspr l2cr, r3 - isync - mtlr r4 /* restore link register */ - blr - -/* - * Disable L2 cache - * Calls flush_dcache. LR is saved in r4 - */ -_GLOBAL(l2cache_disable) - mflr r4 /* save link register */ - bl flush_dcache /* uses r3 and r5 */ - sync - mtlr r4 /* restore link register */ -l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ - lis r3, L2_INIT@h - ori r3, r3, L2_INIT@l - mtspr l2cr, r3 - isync - blr diff --git a/arch/powerpc/cpu/74xx_7xx/config.mk b/arch/powerpc/cpu/74xx_7xx/config.mk deleted file mode 100644 index 9053191602..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/arch/powerpc/cpu/74xx_7xx/cpu.c b/arch/powerpc/cpu/74xx_7xx/cpu.c deleted file mode 100644 index 6cd54bf924..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/cpu.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * cpu.c - * - * CPU specific code - * - * written or collected and sometimes rewritten by - * Magnus Damm - * - * minor modifications by - * Wolfgang Denk - * - * more modifications by - * Josh Huber - * added support for the 74xx series of cpus - * added support for the 7xx series of cpus - * made the code a little less hard-coded, and more auto-detectish - */ - -#include -#include -#include <74xx_7xx.h> -#include - -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -cpu_t -get_cpu_type(void) -{ - uint pvr = get_pvr(); - cpu_t type; - - type = CPU_UNKNOWN; - - switch (PVR_VER(pvr)) { - case 0x000c: - type = CPU_7400; - break; - case 0x0008: - type = CPU_750; - - if (((pvr >> 8) & 0xff) == 0x01) { - type = CPU_750CX; /* old CX (80100 and 8010x?)*/ - } else if (((pvr >> 8) & 0xff) == 0x22) { - type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */ - } else if (((pvr >> 8) & 0xff) == 0x33) { - type = CPU_750CX; /* CXe (83311) */ - } else if (((pvr >> 12) & 0xF) == 0x3) { - type = CPU_755; - } - break; - - case 0x7000: - type = CPU_750FX; - break; - - case 0x7002: - type = CPU_750GX; - break; - - case 0x800C: - type = CPU_7410; - break; - - case 0x8000: - type = CPU_7450; - break; - - case 0x8001: - type = CPU_7455; - break; - - case 0x8002: - type = CPU_7457; - break; - - case 0x8003: - type = CPU_7447A; - break; - - case 0x8004: - type = CPU_7448; - break; - - default: - break; - } - - return type; -} - -/* ------------------------------------------------------------------------- */ - -#if !defined(CONFIG_BAB7xx) -int checkcpu (void) -{ - uint type = get_cpu_type(); - uint pvr = get_pvr(); - ulong clock = gd->cpu_clk; - char buf[32]; - char *str; - - puts ("CPU: "); - - switch (type) { - case CPU_750CX: - printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"", - (pvr>>8) & 0xf, - pvr & 0xf); - goto PR_CLK; - - case CPU_750: - str = "750"; - break; - - case CPU_750FX: - str = "750FX"; - break; - - case CPU_750GX: - str = "750GX"; - break; - - case CPU_755: - str = "755"; - break; - - case CPU_7400: - str = "MPC7400"; - break; - - case CPU_7410: - str = "MPC7410"; - break; - - case CPU_7447A: - str = "MPC7447A"; - break; - - case CPU_7448: - str = "MPC7448"; - break; - - case CPU_7450: - str = "MPC7450"; - break; - - case CPU_7455: - str = "MPC7455"; - break; - - case CPU_7457: - str = "MPC7457"; - break; - - default: - printf("Unknown CPU -- PVR: 0x%08x\n", pvr); - return -1; - } - - printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF); -PR_CLK: - printf (" @ %s MHz\n", strmhz(buf, clock)); - - return (0); -} -#endif -/* these two functions are unimplemented currently [josh] */ - -/* -------------------------------------------------------------------- */ -/* L1 i-cache */ - -int -checkicache(void) -{ - return 0; /* XXX */ -} - -/* -------------------------------------------------------------------- */ -/* L1 d-cache */ - -int -checkdcache(void) -{ - return 0; /* XXX */ -} - -/* -------------------------------------------------------------------- */ - -static inline void -soft_restart(unsigned long addr) -{ - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); - __asm__ __volatile__ ("mtspr 27, 4"); - __asm__ __volatile__ ("rfi"); - - while(1); /* not reached */ -} - - -#if !defined(CONFIG_BAB7xx) && \ - !defined(CONFIG_ELPPC) && \ - !defined(CONFIG_PPMC7XX) -/* no generic way to do board reset. simply call soft_reset. */ -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - /* flush and disable I/D cache */ - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 4"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 5"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on your - * system and assign it to CONFIG_SYS_RESET_ADDRESS. - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - soft_restart(addr); - - /* not reached */ - while(1) - ; - - return 1; -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * For the 7400 the TB clock runs at 1/4 the cpu bus speed. - */ -#ifndef CONFIG_SYS_BUS_CLK -#define CONFIG_SYS_BUS_CLK gd->bus_clk -#endif - -unsigned long get_tbclk(void) -{ - return CONFIG_SYS_BUS_CLK / 4; -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -#if !defined(CONFIG_BAB7xx) -void -watchdog_reset(void) -{ - -} -#endif /* !CONFIG_BAB7xx */ -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_OF_LIBFDT -void ft_cpu_setup(void *blob, bd_t *bd) -{ - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 4, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); - - fdt_fixup_ethernet(blob); -} -#endif -/* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/74xx_7xx/cpu_init.c b/arch/powerpc/cpu/74xx_7xx/cpu_init.c deleted file mode 100644 index a6a8788433..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/cpu_init.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * cpu_init.c - low level cpu init - * - * there's really nothing going on here yet. future work area? - */ - -#include -#include <74xx_7xx.h> - -/* - * Breath some life into the CPU... - * - * there's basically nothing to do here since the memory controller - * isn't on the CPU in this case. - */ -void -cpu_init_f (void) -{ - switch (get_cpu_type()) { - case CPU_7450: - case CPU_7455: - case CPU_7457: - case CPU_7447A: - case CPU_7448: - /* enable the timebase bit in HID0 */ - set_hid0(get_hid0() | 0x4000000); - break; - default: - /* do nothing */ - break; - } -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ - return (0); -} diff --git a/arch/powerpc/cpu/74xx_7xx/interrupts.c b/arch/powerpc/cpu/74xx_7xx/interrupts.c deleted file mode 100644 index a9062435d7..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/interrupts.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * interrupts.c - just enough support for the decrementer/timer - */ - -#include -#include -#include -#include -#include -#include - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - debug("interrupt_init: GT main cause reg: %08x:%08x\n", - GTREGREAD(LOW_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(HIGH_INTERRUPT_CAUSE_REGISTER)); - debug("interrupt_init: ethernet cause regs: %08x %08x %08x\n", - GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(ETHERNET1_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(ETHERNET2_INTERRUPT_CAUSE_REGISTER)); - debug("interrupt_init: ethernet mask regs: %08x %08x %08x\n", - GTREGREAD(ETHERNET0_INTERRUPT_MASK_REGISTER), - GTREGREAD(ETHERNET1_INTERRUPT_MASK_REGISTER), - GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER)); - debug("interrupt_init: setting decrementer_count\n"); - - *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void -external_interrupt(struct pt_regs *regs) -{ - puts("external_interrupt (oops!)\n"); -} - -volatile ulong timestamp = 0; - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * Trivial implementation - no need to be really accurate. - */ -void -timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -/* - * Install and free a interrupt handler. - */ - -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) -{ - -} - -void -irq_free_handler(int vec) -{ - -} - -/****************************************************************************/ - -void -do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[]) -{ - puts("IRQ related functions are unimplemented currently.\n"); -} diff --git a/arch/powerpc/cpu/74xx_7xx/io.S b/arch/powerpc/cpu/74xx_7xx/io.S deleted file mode 100644 index 3b4b08a889..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/io.S +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - * Copyright (C) 2002 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* ------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0(3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,0,r3 - sync - blr diff --git a/arch/powerpc/cpu/74xx_7xx/kgdb.S b/arch/powerpc/cpu/74xx_7xx/kgdb.S deleted file mode 100644 index 42b3a76009..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/kgdb.S +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include <74xx_7xx.h> -#include - -#include -#include - -#include -#include - -#if defined(CONFIG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - lis r3,0 - addis r4,r0,0x0040 -kgdb_flush_loop: - lwz r5,0(r3) - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - cmp 0,0,r3,r4 - bne kgdb_flush_loop - SYNC - mfspr r3,1008 - ori r3,r3,0x8800 - mtspr 1008,r3 - sync - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CONFIG_SYS_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CONFIG_SYS_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif diff --git a/arch/powerpc/cpu/74xx_7xx/speed.c b/arch/powerpc/cpu/74xx_7xx/speed.c deleted file mode 100644 index eec9ed56b4..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/speed.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include <74xx_7xx.h> -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern unsigned long get_board_bus_clk (void); - -static const int hid1_multipliers_x_10[] = { - 25, /* 0000 - 2.5x */ - 75, /* 0001 - 7.5x */ - 70, /* 0010 - 7x */ - 10, /* 0011 - bypass */ - 20, /* 0100 - 2x */ - 65, /* 0101 - 6.5x */ - 100, /* 0110 - 10x */ - 45, /* 0111 - 4.5x */ - 30, /* 1000 - 3x */ - 55, /* 1001 - 5.5x */ - 40, /* 1010 - 4x */ - 50, /* 1011 - 5x */ - 80, /* 1100 - 8x */ - 60, /* 1101 - 6x */ - 35, /* 1110 - 3.5x */ - 0 /* 1111 - off */ -}; - -/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */ -static const int hid1_74xx_multipliers_x_10[] = { - 115, /* 00000 - 11.5x */ - 170, /* 00001 - 17x */ - 75, /* 00010 - 7.5x */ - 150, /* 00011 - 15x */ - 70, /* 00100 - 7x */ - 180, /* 00101 - 18x */ - 10, /* 00110 - bypass */ - 200, /* 00111 - 20x */ - 20, /* 01000 - 2x */ - 210, /* 01001 - 21x */ - 65, /* 01010 - 6.5x */ - 130, /* 01011 - 13x */ - 85, /* 01100 - 8.5x */ - 240, /* 01101 - 24x */ - 95, /* 01110 - 9.5x */ - 90, /* 01111 - 9x */ - 30, /* 10000 - 3x */ - 105, /* 10001 - 10.5x */ - 55, /* 10010 - 5.5x */ - 110, /* 10011 - 11x */ - 40, /* 10100 - 4x */ - 100, /* 10101 - 10x */ - 50, /* 10110 - 5x */ - 120, /* 10111 - 12x */ - 80, /* 11000 - 8x */ - 140, /* 11001 - 14x */ - 60, /* 11010 - 6x */ - 160, /* 11011 - 16x */ - 135, /* 11100 - 13.5x */ - 280, /* 11101 - 28x */ - 0, /* 11110 - off */ - 125 /* 11111 - 12.5x */ -}; - -static const int hid1_fx_multipliers_x_10[] = { - 00, /* 0000 - off */ - 00, /* 0001 - off */ - 10, /* 0010 - bypass */ - 10, /* 0011 - bypass */ - 20, /* 0100 - 2x */ - 25, /* 0101 - 2.5x */ - 30, /* 0110 - 3x */ - 35, /* 0111 - 3.5x */ - 40, /* 1000 - 4x */ - 45, /* 1001 - 4.5x */ - 50, /* 1010 - 5x */ - 55, /* 1011 - 5.5x */ - 60, /* 1100 - 6x */ - 65, /* 1101 - 6.5x */ - 70, /* 1110 - 7x */ - 75, /* 1111 - 7.5 */ - 80, /* 10000 - 8x */ - 85, /* 10001 - 8.5x */ - 90, /* 10010 - 9x */ - 95, /* 10011 - 9.5x */ - 100, /* 10100 - 10x */ - 110, /* 10101 - 11x */ - 120, /* 10110 - 12x */ -}; - - -/* ------------------------------------------------------------------------- */ - -/* - * Measure CPU clock speed (core clock GCLK1, GCLK2) - * - * (Approx. GCLK frequency in Hz) - */ - -int get_clocks (void) -{ - ulong clock = 0; - -#ifdef CONFIG_SYS_BUS_CLK - gd->bus_clk = CONFIG_SYS_BUS_CLK; /* bus clock is a fixed frequency */ -#else - gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */ -#endif - - /* calculate the clock frequency based upon the CPU type */ - switch (get_cpu_type()) { - case CPU_7447A: - case CPU_7448: - case CPU_7455: - case CPU_7457: - /* - * Make sure division is done before multiplication to prevent 32-bit - * arithmetic overflows which will cause a negative number - */ - clock = (gd->bus_clk / 10) * - hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; - break; - - case CPU_750GX: - case CPU_750FX: - clock = (gd->bus_clk / 10) * - hid1_fx_multipliers_x_10[get_hid1 () >> 27]; - break; - - case CPU_7450: - case CPU_740: - case CPU_740P: - case CPU_745: - case CPU_750CX: - case CPU_750: - case CPU_750P: - case CPU_755: - case CPU_7400: - case CPU_7410: - /* - * Make sure division is done before multiplication to prevent 32-bit - * arithmetic overflows which will cause a negative number - */ - clock = (gd->bus_clk / 10) * - hid1_multipliers_x_10[get_hid1 () >> 28]; - break; - - case CPU_UNKNOWN: - printf ("get_gclk_freq(): unknown CPU type\n"); - clock = 0; - return (1); - } - - gd->cpu_clk = clock; - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S deleted file mode 100644 index b0e102c668..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/start.S +++ /dev/null @@ -1,840 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000,2001,2002 Wolfgang Denk - * Copyright (C) 2001 Josh Huber - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0xfff00100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - */ -#include -#include -#include <74xx_7xx.h> -#include - -#include -#include - -#include -#include -#include - -#if !defined(CONFIG_DB64360) && \ - !defined(CONFIG_DB64460) && \ - !defined(CONFIG_CPCI750) && \ - !defined(CONFIG_P3Mx) -#include -#endif - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_ME | MSR_RI ) - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - b boot_cold - - /* the boot code is located below the exception table */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* - * On the MPC8xx, this is a software emulation interrupt. It - * occurs for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x2000 - -boot_cold: - /* disable everything */ - li r0, 0 - mtspr HID0, r0 - sync - mtmsr 0 - bl invalidate_bats - sync - -#ifdef CONFIG_SYS_L2 - /* init the L2 cache */ - addis r3, r0, L2_INIT@h - ori r3, r3, L2_INIT@l - sync - mtspr l2cr, r3 -#endif -#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx) - .long 0x7e00066c - /* - * dssall instruction, gas doesn't have it yet - * ...for altivec, data stream stop all this probably - * isn't needed unless we warm (software) reboot U-Boot - */ -#endif - -#ifdef CONFIG_SYS_L2 - /* invalidate the L2 cache */ - bl l2cache_invalidate - sync -#endif -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* do early init */ - bl board_asm_init -#endif - - /* - * Calculate absolute address in FLASH and jump there - *------------------------------------------------------*/ - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*------------------------------------------------------*/ - - /* perform low-level init */ - /* sdram init, galileo init, etc */ - /* r3: NHR bit from HID0 */ - - /* setup the bats */ - bl setup_bats - sync - - /* - * Cache must be enabled here for stack-in-cache trick. - * This means we need to enable the BATS. - * This means: - * 1) for the EVB, original gt regs need to be mapped - * 2) need to have an IBAT for the 0xf region, - * we are running there! - * Cache should be turned on after BATs, since by default - * everything is write-through. - * The init-mem BAT can be reused after reloc. The old - * gt-regs BAT can be reused after board_init_f calls - * board_early_init_f (EVB only). - */ -#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx) - /* enable address translation */ - bl enable_addr_trans - sync - - /* enable and invalidate the data cache */ - bl l1dcache_enable - sync -#endif -#ifdef CONFIG_SYS_INIT_RAM_LOCK - bl lock_ram_in_cache - sync -#endif - - /* set up the stack pointer in our newly created - * cache-ram (r1) */ - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - GET_GOT /* initialize GOT access */ - - /* run low-level CPU init code (from Flash) */ - bl cpu_init_f - sync - - /* run 1st part of board init code (from Flash) */ - bl board_init_f - sync - - /* NOTREACHED - board_init_f() does not return */ - - .globl invalidate_bats -invalidate_bats: - /* invalidate BATs */ - mtspr IBAT0U, r0 - mtspr IBAT1U, r0 - mtspr IBAT2U, r0 - mtspr IBAT3U, r0 -#ifdef CONFIG_HIGH_BATS - mtspr IBAT4U, r0 - mtspr IBAT5U, r0 - mtspr IBAT6U, r0 - mtspr IBAT7U, r0 -#endif - isync - mtspr DBAT0U, r0 - mtspr DBAT1U, r0 - mtspr DBAT2U, r0 - mtspr DBAT3U, r0 -#ifdef CONFIG_HIGH_BATS - mtspr DBAT4U, r0 - mtspr DBAT5U, r0 - mtspr DBAT6U, r0 - mtspr DBAT7U, r0 -#endif - isync - sync - blr - - /* setup_bats - set them up to some initial state */ - .globl setup_bats -setup_bats: - addis r0, r0, 0x0000 - - /* IBAT 0 */ - addis r4, r0, CONFIG_SYS_IBAT0L@h - ori r4, r4, CONFIG_SYS_IBAT0L@l - addis r3, r0, CONFIG_SYS_IBAT0U@h - ori r3, r3, CONFIG_SYS_IBAT0U@l - mtspr IBAT0L, r4 - mtspr IBAT0U, r3 - isync - - /* DBAT 0 */ - addis r4, r0, CONFIG_SYS_DBAT0L@h - ori r4, r4, CONFIG_SYS_DBAT0L@l - addis r3, r0, CONFIG_SYS_DBAT0U@h - ori r3, r3, CONFIG_SYS_DBAT0U@l - mtspr DBAT0L, r4 - mtspr DBAT0U, r3 - isync - - /* IBAT 1 */ - addis r4, r0, CONFIG_SYS_IBAT1L@h - ori r4, r4, CONFIG_SYS_IBAT1L@l - addis r3, r0, CONFIG_SYS_IBAT1U@h - ori r3, r3, CONFIG_SYS_IBAT1U@l - mtspr IBAT1L, r4 - mtspr IBAT1U, r3 - isync - - /* DBAT 1 */ - addis r4, r0, CONFIG_SYS_DBAT1L@h - ori r4, r4, CONFIG_SYS_DBAT1L@l - addis r3, r0, CONFIG_SYS_DBAT1U@h - ori r3, r3, CONFIG_SYS_DBAT1U@l - mtspr DBAT1L, r4 - mtspr DBAT1U, r3 - isync - - /* IBAT 2 */ - addis r4, r0, CONFIG_SYS_IBAT2L@h - ori r4, r4, CONFIG_SYS_IBAT2L@l - addis r3, r0, CONFIG_SYS_IBAT2U@h - ori r3, r3, CONFIG_SYS_IBAT2U@l - mtspr IBAT2L, r4 - mtspr IBAT2U, r3 - isync - - /* DBAT 2 */ - addis r4, r0, CONFIG_SYS_DBAT2L@h - ori r4, r4, CONFIG_SYS_DBAT2L@l - addis r3, r0, CONFIG_SYS_DBAT2U@h - ori r3, r3, CONFIG_SYS_DBAT2U@l - mtspr DBAT2L, r4 - mtspr DBAT2U, r3 - isync - - /* IBAT 3 */ - addis r4, r0, CONFIG_SYS_IBAT3L@h - ori r4, r4, CONFIG_SYS_IBAT3L@l - addis r3, r0, CONFIG_SYS_IBAT3U@h - ori r3, r3, CONFIG_SYS_IBAT3U@l - mtspr IBAT3L, r4 - mtspr IBAT3U, r3 - isync - - /* DBAT 3 */ - addis r4, r0, CONFIG_SYS_DBAT3L@h - ori r4, r4, CONFIG_SYS_DBAT3L@l - addis r3, r0, CONFIG_SYS_DBAT3U@h - ori r3, r3, CONFIG_SYS_DBAT3U@l - mtspr DBAT3L, r4 - mtspr DBAT3U, r3 - isync - -#ifdef CONFIG_HIGH_BATS - /* IBAT 4 */ - addis r4, r0, CONFIG_SYS_IBAT4L@h - ori r4, r4, CONFIG_SYS_IBAT4L@l - addis r3, r0, CONFIG_SYS_IBAT4U@h - ori r3, r3, CONFIG_SYS_IBAT4U@l - mtspr IBAT4L, r4 - mtspr IBAT4U, r3 - isync - - /* DBAT 4 */ - addis r4, r0, CONFIG_SYS_DBAT4L@h - ori r4, r4, CONFIG_SYS_DBAT4L@l - addis r3, r0, CONFIG_SYS_DBAT4U@h - ori r3, r3, CONFIG_SYS_DBAT4U@l - mtspr DBAT4L, r4 - mtspr DBAT4U, r3 - isync - - /* IBAT 5 */ - addis r4, r0, CONFIG_SYS_IBAT5L@h - ori r4, r4, CONFIG_SYS_IBAT5L@l - addis r3, r0, CONFIG_SYS_IBAT5U@h - ori r3, r3, CONFIG_SYS_IBAT5U@l - mtspr IBAT5L, r4 - mtspr IBAT5U, r3 - isync - - /* DBAT 5 */ - addis r4, r0, CONFIG_SYS_DBAT5L@h - ori r4, r4, CONFIG_SYS_DBAT5L@l - addis r3, r0, CONFIG_SYS_DBAT5U@h - ori r3, r3, CONFIG_SYS_DBAT5U@l - mtspr DBAT5L, r4 - mtspr DBAT5U, r3 - isync - - /* IBAT 6 */ - addis r4, r0, CONFIG_SYS_IBAT6L@h - ori r4, r4, CONFIG_SYS_IBAT6L@l - addis r3, r0, CONFIG_SYS_IBAT6U@h - ori r3, r3, CONFIG_SYS_IBAT6U@l - mtspr IBAT6L, r4 - mtspr IBAT6U, r3 - isync - - /* DBAT 6 */ - addis r4, r0, CONFIG_SYS_DBAT6L@h - ori r4, r4, CONFIG_SYS_DBAT6L@l - addis r3, r0, CONFIG_SYS_DBAT6U@h - ori r3, r3, CONFIG_SYS_DBAT6U@l - mtspr DBAT6L, r4 - mtspr DBAT6U, r3 - isync - - /* IBAT 7 */ - addis r4, r0, CONFIG_SYS_IBAT7L@h - ori r4, r4, CONFIG_SYS_IBAT7L@l - addis r3, r0, CONFIG_SYS_IBAT7U@h - ori r3, r3, CONFIG_SYS_IBAT7U@l - mtspr IBAT7L, r4 - mtspr IBAT7U, r3 - isync - - /* DBAT 7 */ - addis r4, r0, CONFIG_SYS_DBAT7L@h - ori r4, r4, CONFIG_SYS_DBAT7L@l - addis r3, r0, CONFIG_SYS_DBAT7U@h - ori r3, r3, CONFIG_SYS_DBAT7U@l - mtspr DBAT7L, r4 - mtspr DBAT7U, r3 - isync -#endif - - /* bats are done, now invalidate the TLBs */ - - addis r3, 0, 0x0000 - addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ - - isync - -tlblp: - tlbie r3 - sync - addi r3, r3, 0x1000 - cmp 0, 0, r3, r5 - blt tlblp - - blr - - .globl enable_addr_trans -enable_addr_trans: - /* enable address translation */ - mfmsr r5 - ori r5, r5, (MSR_IR | MSR_DR) - mtmsr r5 - isync - blr - - .globl disable_addr_trans -disable_addr_trans: - /* disable address translation */ - mflr r4 - mfmsr r3 - andi. r0, r3, (MSR_IR | MSR_DR) - beqlr - andc r3, r3, r0 - mtspr SRR0, r4 - mtspr SRR1, r3 - rfi - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - - .globl dc_read -dc_read: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*-----------------------------------------------------------------------*/ -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ -#ifdef CONFIG_ECC - bl board_relocate_rom - sync - mr r3, r10 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ -#else - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b -#endif -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: -#ifdef CONFIG_ECC - bl board_init_ecc -#endif - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -/* clear_bss: */ - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - mr r3, r10 /* Destination Address */ -#if defined(CONFIG_DB64360) || \ - defined(CONFIG_DB64460) || \ - defined(CONFIG_CPCI750) || \ - defined(CONFIG_PPMC7XX) || \ - defined(CONFIG_P3Mx) - mr r4, r9 /* Use RAM copy of the global data */ -#endif - bl after_reloc - - /* not reached - end relocate_code */ -/*-----------------------------------------------------------------------*/ - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - /* enable execptions from RAM vectors */ - mfmsr r7 - li r8,MSR_IP - andc r7,r7,r8 - mtmsr r7 - - mtlr r4 /* restore link register */ - blr - -#ifdef CONFIG_SYS_INIT_RAM_LOCK -lock_ram_in_cache: - /* Allocate Initial RAM in data cache. - */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r4 -1: - dcbz r0, r3 - addi r3, r3, 32 - bdnz 1b - - /* Lock the data cache */ - mfspr r0, HID0 - ori r0, r0, 0x1000 - sync - mtspr HID0, r0 - sync - blr - -.globl unlock_ram_in_cache -unlock_ram_in_cache: - /* invalidate the INIT_RAM section */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r4 -1: icbi r0, r3 - addi r3, r3, 32 - bdnz 1b - sync /* Wait for all icbi to complete on bus */ - isync - - /* Unlock the data cache and invalidate it */ - mfspr r0, HID0 - li r3,0x1000 - andc r0,r0,r3 - li r3,0x0400 - or r0,r0,r3 - sync - mtspr HID0, r0 - sync - blr -#endif diff --git a/arch/powerpc/cpu/74xx_7xx/traps.c b/arch/powerpc/cpu/74xx_7xx/traps.c deleted file mode 100644 index 111c86cc15..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/traps.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include -#include - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS:" - " %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP:" - " %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ - unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; - int i, j; - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - - p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0); - p -= 32; - for (i = 0; i < 256; i+=16) { - printf("%08x: ", (unsigned int)p+i); - for (j = 0; j < 16; j++) { - printf("%02x ", p[i+j]); - } - printf("\n"); - } - - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds deleted file mode 100644 index c099849084..0000000000 --- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2010 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - .text : - { - arch/powerpc/cpu/74xx_7xx/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile new file mode 100644 index 0000000000..88b5298be0 --- /dev/null +++ b/arch/powerpc/cpu/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_MPC83xx) += mpc8xxx/ +obj-$(CONFIG_MPC85xx) += mpc8xxx/ +obj-$(CONFIG_MPC86xx) += mpc8xxx/ diff --git a/arch/powerpc/cpu/mpc512x/Kconfig b/arch/powerpc/cpu/mpc512x/Kconfig new file mode 100644 index 0000000000..a0f0ede6f3 --- /dev/null +++ b/arch/powerpc/cpu/mpc512x/Kconfig @@ -0,0 +1,33 @@ +menu "mpc512x CPU" + depends on MPC512X + +config SYS_CPU + default "mpc512x" + +choice + prompt "Target select" + +config TARGET_PDM360NG + bool "Support pdm360ng" + +config TARGET_ARIA + bool "Support aria" + +config TARGET_MECP5123 + bool "Support mecp5123" + +config TARGET_MPC5121ADS + bool "Support mpc5121ads" + +config TARGET_AC14XX + bool "Support ac14xx" + +endchoice + +source "board/davedenx/aria/Kconfig" +source "board/esd/mecp5123/Kconfig" +source "board/freescale/mpc5121ads/Kconfig" +source "board/ifm/ac14xx/Kconfig" +source "board/pdm360ng/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile index 1af9ab1e96..a4934ef78a 100644 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ b/arch/powerpc/cpu/mpc512x/Makefile @@ -4,44 +4,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -$(shell mkdir -p $(OBJTREE)/board/freescale/common) - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS-y := cpu.o -COBJS-y += traps.o -COBJS-y += cpu_init.o -COBJS-y += fixed_sdram.o -COBJS-y += i2c.o -COBJS-y += interrupts.o -COBJS-y += iopin.o -COBJS-y += serial.o -COBJS-y += speed.o -COBJS-$(CONFIG_FSL_DIU_FB) += diu.o -COBJS-$(CONFIG_CMD_IDE) += ide.o -COBJS-$(CONFIG_PCI) += pci.o +extra-y = start.o +obj-y := cpu.o +obj-y += traps.o +obj-y += cpu_init.o +obj-y += fixed_sdram.o +obj-y += i2c.o +obj-y += interrupts.o +obj-y += iopin.o +obj-y += serial.o +obj-y += speed.o +obj-$(CONFIG_FSL_DIU_FB) += diu.o +obj-$(CONFIG_CMD_IDE) += ide.o +obj-$(CONFIG_PCI) += pci.o # Stub implementations of cache management functions for USB -COBJS-$(CONFIG_USB_EHCI) += cache.o - -COBJS := $(COBJS-y) -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_USB_EHCI) += cache.o diff --git a/arch/powerpc/cpu/mpc512x/config.mk b/arch/powerpc/cpu/mpc512x/config.mk index 04717a485e..5bf1b2a3b9 100644 --- a/arch/powerpc/cpu/mpc512x/config.mk +++ b/arch/powerpc/cpu/mpc512x/config.mk @@ -4,7 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ - -ffixed-r2 -msoft-float -mcpu=603e +PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float -mcpu=603e diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c index 42e0dc96f7..4105a28509 100644 --- a/arch/powerpc/cpu/mpc512x/serial.c +++ b/arch/powerpc/cpu/mpc512x/serial.c @@ -384,7 +384,7 @@ struct stdio_dev *open_port(int num, int baudrate) sprintf(env_val, "%d", baudrate); setenv(env_var, env_val); - if (port->start()) + if (port->start(port)) return NULL; set_bit(num, &initialized); @@ -407,7 +407,7 @@ int close_port(int num) if (!port) return -1; - ret = port->stop(); + ret = port->stop(port); clear_bit(num, &initialized); return ret; @@ -418,7 +418,7 @@ int write_port(struct stdio_dev *port, char *buf) if (!port || !buf) return -1; - port->puts(buf); + port->puts(port, buf); return 0; } @@ -433,8 +433,8 @@ int read_port(struct stdio_dev *port, char *buf, int size) if (!size) return 0; - while (port->tstc()) { - buf[cnt++] = port->getc(); + while (port->tstc(port)) { + buf[cnt++] = port->getc(port); if (cnt > size) break; } diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c index 10169912b7..9f5bcd7fc3 100644 --- a/arch/powerpc/cpu/mpc512x/traps.c +++ b/arch/powerpc/cpu/mpc512x/traps.c @@ -27,7 +27,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig new file mode 100644 index 0000000000..aad4a7cdd8 --- /dev/null +++ b/arch/powerpc/cpu/mpc5xx/Kconfig @@ -0,0 +1,21 @@ +menu "mpc5xx CPU" + depends on 5xx + +config SYS_CPU + default "mpc5xx" + +choice + prompt "Target select" + +config TARGET_CMI_MPC5XX + bool "Support cmi_mpc5xx" + +config TARGET_PATI + bool "Support PATI" + +endchoice + +source "board/cmi/Kconfig" +source "board/mpl/pati/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc5xx/Makefile b/arch/powerpc/cpu/mpc5xx/Makefile index e3e50af2cd..7b8826a643 100644 --- a/arch/powerpc/cpu/mpc5xx/Makefile +++ b/arch/powerpc/cpu/mpc5xx/Makefile @@ -16,28 +16,5 @@ # uses the definitions made in arch/powerpc/cpu/mpc5xx/config.mk # - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o diff --git a/arch/powerpc/cpu/mpc5xx/config.mk b/arch/powerpc/cpu/mpc5xx/config.mk index b33f17a1ba..dd2ec376c9 100644 --- a/arch/powerpc/cpu/mpc5xx/config.mk +++ b/arch/powerpc/cpu/mpc5xx/config.mk @@ -5,6 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float +PLATFORM_CPPFLAGS += -mpowerpc -msoft-float diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index bdd46d955d..6b196de355 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -19,13 +19,9 @@ #include #include -#define CONFIG_5xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include -#include #include #include diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig new file mode 100644 index 0000000000..9da00dad73 --- /dev/null +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -0,0 +1,102 @@ +menu "mpc5xxx CPU" + depends on MPC5xxx + +config SYS_CPU + default "mpc5xxx" + +choice + prompt "Target select" + +config TARGET_A3M071 + bool "Support a3m071" + select SUPPORT_SPL + +config TARGET_A4M072 + bool "Support a4m072" + +config TARGET_BC3450 + bool "Support BC3450" + +config TARGET_CANMB + bool "Support canmb" + +config TARGET_CM5200 + bool "Support cm5200" + +config TARGET_GALAXY5200 + bool "Support galaxy5200" + +config TARGET_INKA4X0 + bool "Support inka4x0" + +config TARGET_IPEK01 + bool "Support ipek01" + +config TARGET_JUPITER + bool "Support jupiter" + +config TARGET_MOTIONPRO + bool "Support motionpro" + +config TARGET_MUNICES + bool "Support munices" + +config TARGET_V38B + bool "Support v38b" + +config TARGET_O2D + bool "Support O2D" + +config TARGET_O2D300 + bool "Support O2D300" + +config TARGET_O2DNT2 + bool "Support O2DNT2" + +config TARGET_O2I + bool "Support O2I" + +config TARGET_O2MNT + bool "Support O2MNT" + +config TARGET_O3DNT + bool "Support O3DNT" + +config TARGET_DIGSY_MTC + bool "Support digsy_mtc" + +config TARGET_PCM030 + bool "Support pcm030" + +config TARGET_AEV + bool "Support aev" + +config TARGET_CHARON + bool "Support charon" + +config TARGET_TB5200 + bool "Support TB5200" + +config TARGET_TQM5200 + bool "Support TQM5200" + +endchoice + +source "board/a3m071/Kconfig" +source "board/a4m072/Kconfig" +source "board/bc3450/Kconfig" +source "board/canmb/Kconfig" +source "board/cm5200/Kconfig" +source "board/galaxy5200/Kconfig" +source "board/ifm/o2dnt2/Kconfig" +source "board/inka4x0/Kconfig" +source "board/intercontrol/digsy_mtc/Kconfig" +source "board/ipek01/Kconfig" +source "board/jupiter/Kconfig" +source "board/motionpro/Kconfig" +source "board/munices/Kconfig" +source "board/phytec/pcm030/Kconfig" +source "board/tqc/tqm5200/Kconfig" +source "board/v38b/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile index fc0b7a192e..d122b29aec 100644 --- a/arch/powerpc/cpu/mpc5xxx/Makefile +++ b/arch/powerpc/cpu/mpc5xxx/Makefile @@ -5,44 +5,23 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -SSTART = start.o -CSTART = traps.o -SOBJS += io.o -SOBJS += firmware_sc_task_bestcomm.impl.o -COBJS-y += i2c.o -COBJS-y += cpu.o -COBJS-y += cpu_init.o -COBJS-y += ide.o -COBJS-y += interrupts.o -COBJS-y += loadtask.o -COBJS-y += pci_mpc5200.o -COBJS-y += serial.o -COBJS-y += speed.o -COBJS-$(CONFIG_CMD_USB) += usb_ohci.o -COBJS-$(CONFIG_CMD_USB) += usb.o +extra-y = start.o +extra-y += traps.o +obj-y += cache.o +obj-y += io.o +obj-y += firmware_sc_task_bestcomm.impl.o +obj-y += i2c.o +obj-y += cpu.o +obj-y += cpu_init.o +obj-y += ide.o +obj-y += interrupts.o +obj-y += loadtask.o +obj-y += pci_mpc5200.o +obj-y += serial.o +obj-y += speed.o +obj-$(CONFIG_CMD_USB) += usb_ohci.o +obj-$(CONFIG_CMD_USB) += usb.o ifdef CONFIG_SPL_BUILD -COBJS-y += spl_boot.o +obj-y += spl_boot.o endif - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) -START := $(addprefix $(obj),$(SSTART) $(CSTART)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/powerpc/cpu/mpc5xxx/cache.c b/arch/powerpc/cpu/mpc5xxx/cache.c new file mode 100644 index 0000000000..5d674bce41 --- /dev/null +++ b/arch/powerpc/cpu/mpc5xxx/cache.c @@ -0,0 +1,15 @@ +/* + * This file contains stub implementation of + * invalidate_dcache_range() + * flush_dcache_range() + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} diff --git a/arch/powerpc/cpu/mpc5xxx/config.mk b/arch/powerpc/cpu/mpc5xxx/config.mk index 57bdd2d252..bcff2144a1 100644 --- a/arch/powerpc/cpu/mpc5xxx/config.mk +++ b/arch/powerpc/cpu/mpc5xxx/config.mk @@ -5,7 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ - -mstring -mcpu=603e -mmultiple +PLATFORM_CPPFLAGS += -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c index 03cd7fd4e0..9003b774ff 100644 --- a/arch/powerpc/cpu/mpc5xxx/ide.c +++ b/arch/powerpc/cpu/mpc5xxx/ide.c @@ -41,19 +41,11 @@ int ide_preinit (void) /* All sample codes do that... */ *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0; -#if defined(CONFIG_UC101) - /* Configure and reset host */ - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = - MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; - udelay (10); - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0; -#else /* Configure and reset host */ *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY | MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; udelay (10); *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY; -#endif /* Disable prefetch on Commbus */ psdma->PtdCntrl |= 1; diff --git a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c index a89d5fd7a6..70b7e6e6cb 100644 --- a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c +++ b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c @@ -33,21 +33,7 @@ static int mpc5200_read_config_dword(struct pci_controller *hose, *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; eieio(); udelay(10); -#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200) - if (dev & 0x00ff0000) { - u32 val; - val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2)); - udelay(10); - val = val << 16; - val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0)); - *value = val; - } else { - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); - } - udelay(10); -#else *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); -#endif eieio(); *(volatile u32 *)MPC5XXX_PCI_CAR = 0; udelay(10); diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 517b5808fe..94eb0d3fff 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -14,9 +14,6 @@ #include #include -#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include @@ -79,6 +76,21 @@ _start: * been done in the SPL u-boot version. */ GET_GOT /* initialize GOT access */ + + /* + * The GD (global data) struct needs to get cleared. Lets do + * this by calling memset(). + * This function is called when the platform is build with SPL + * support from the main (full-blown) U-Boot. And the GD needs + * to get cleared (again) so that the following generic + * board support code, defined via CONFIG_SYS_GENERIC_BOARD, + * initializes all variables correctly. + */ + mr r3, r2 /* parameter 1: GD pointer */ + li r4,0 /* parameter 2: value to fill */ + li r5,GD_SIZE /* parameter 3: count */ + bl memset + bl board_init_f /* run 1st part of board init code (in Flash)*/ /* NOTREACHED - board_init_f() does not return */ #else diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c index 3d345ff53e..b7c1b5594a 100644 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c +++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c @@ -42,8 +42,6 @@ #define readl(a) (*((volatile u32 *)(a))) #define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) #else @@ -842,104 +840,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ @@ -1544,7 +1445,7 @@ static void hc_release_ohci (ohci_t *ohci) */ static char ohci_inited = 0; -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { /* Set the USB Clock */ diff --git a/arch/powerpc/cpu/mpc824x/.gitignore b/arch/powerpc/cpu/mpc824x/.gitignore deleted file mode 100644 index 2d79931e96..0000000000 --- a/arch/powerpc/cpu/mpc824x/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/bedbug_603e.c diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile deleted file mode 100644 index 8f27aac25d..0000000000 --- a/arch/powerpc/cpu/mpc824x/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)drivers/epic $(obj)drivers/i2c) -endif - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \ - drivers/epic/epic1.o drivers/i2c/i2c.o pci.o -COBJS_LN = bedbug_603e.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(obj)bedbug_603e.c: - ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/powerpc/cpu/mpc824x/config.mk b/arch/powerpc/cpu/mpc824x/config.mk deleted file mode 100644 index ef605f0797..0000000000 --- a/arch/powerpc/cpu/mpc824x/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float diff --git a/arch/powerpc/cpu/mpc824x/cpu.c b/arch/powerpc/cpu/mpc824x/cpu.c deleted file mode 100644 index ee69e495b7..0000000000 --- a/arch/powerpc/cpu/mpc824x/cpu.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkcpu (void) -{ - unsigned int pvr = get_pvr (); - unsigned int version = pvr >> 16; - unsigned char revision; - ulong clock = gd->cpu_clk; - char buf[32]; - - puts ("CPU: "); - - switch (version) { - case CPU_TYPE_8240: - puts ("MPC8240"); - break; - - case CPU_TYPE_8245: - puts ("MPC8245"); - break; - - default: - return -1; /*not valid for this source */ - } - - CONFIG_READ_BYTE (REVID, revision); - - if (revision) { - printf (" Revision %d.%d", - (revision & 0xf0) >> 4, - (revision & 0x0f)); - } else { - return -1; /* no valid CPU revision info */ - } - - printf (" at %s MHz:", strmhz (buf, clock)); - - printf (" %u kB I-Cache", checkicache () >> 10); - printf (" %u kB D-Cache", checkdcache () >> 10); - - puts ("\n"); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -/* L1 i-cache */ - -int checkicache (void) -{ - /*TODO*/ - return 128 * 4 * 32; -}; - -/* ------------------------------------------------------------------------- */ -/* L1 d-cache */ - -int checkdcache (void) -{ - /*TODO*/ - return 128 * 4 * 32; - -}; - -/*------------------------------------------------------------------- */ - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong msr, addr; - - /* Interrupts and MMU off */ - __asm__ ("mtspr 81, 0"); - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~0x1030; - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on - * your system and assign it to CONFIG_SYS_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; - -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * This is the sys_logic_clk (memory bus) divided by 4 - */ -unsigned long get_tbclk (void) -{ - return ((get_bus_freq (0) + 2L) / 4L); -} - -/* ------------------------------------------------------------------------- */ - -/* - * The MPC824x has an integrated PCI controller known as the MPC107. - * The following are MPC107 Bridge Controller and PCI Support functions - * - */ - -/* - * This procedure reads a 32-bit address MPC107 register, and returns - * a 32 bit value. It swaps the address to little endian before - * writing it to config address, and swaps the value to big endian - * before returning to the caller. - */ -unsigned int mpc824x_mpc107_getreg (unsigned int regNum) -{ - unsigned int temp; - - /* swap the addr. to little endian */ - *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum); - temp = *(volatile unsigned int *) CHRP_REG_DATA; - return PCISWAP (temp); /* swap the data upon return */ -} - -/* - * This procedure writes a 32-bit address MPC107 register. It swaps - * the address to little endian before writing it to config address. - */ - -void mpc824x_mpc107_setreg (unsigned int regNum, unsigned int regVal) -{ - /* swap the addr. to little endian */ - *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum); - *(volatile unsigned int *) CHRP_REG_DATA = PCISWAP (regVal); - return; -} - - -/* - * Write a byte (8 bits) to a memory location. - */ -void mpc824x_mpc107_write8 (unsigned int addr, unsigned char data) -{ - *(unsigned char *) addr = data; - __asm__ ("sync"); -} - -/* - * Write a word (16 bits) to a memory location after the value - * has been byte swapped (big to little endian or vice versa) - */ - -void mpc824x_mpc107_write16 (unsigned int address, unsigned short data) -{ - *(volatile unsigned short *) address = BYTE_SWAP_16_BIT (data); - __asm__ ("sync"); -} - -/* - * Write a long word (32 bits) to a memory location after the value - * has been byte swapped (big to little endian or vice versa) - */ - -void mpc824x_mpc107_write32 (unsigned int address, unsigned int data) -{ - *(volatile unsigned int *) address = LONGSWAP (data); - __asm__ ("sync"); -} - -/* - * Read a byte (8 bits) from a memory location. - */ -unsigned char mpc824x_mpc107_read8 (unsigned int addr) -{ - return *(volatile unsigned char *) addr; -} - - -/* - * Read a word (16 bits) from a memory location, and byte swap the - * value before returning to the caller. - */ -unsigned short mpc824x_mpc107_read16 (unsigned int address) -{ - unsigned short retVal; - - retVal = BYTE_SWAP_16_BIT (*(unsigned short *) address); - return retVal; -} - - -/* - * Read a long word (32 bits) from a memory location, and byte - * swap the value before returning to the caller. - */ -unsigned int mpc824x_mpc107_read32 (unsigned int address) -{ - unsigned int retVal; - - retVal = LONGSWAP (*(unsigned int *) address); - return (retVal); -} - - -/* - * Read a register in the Embedded Utilities Memory Block address - * space. - * Input: regNum - register number + utility base address. Example, - * the base address of EPIC is 0x40000, the register number - * being passed is 0x40000+the address of the target register. - * (See epic.h for register addresses). - * Output: The 32 bit little endian value of the register. - */ - -unsigned int mpc824x_eummbar_read (unsigned int regNum) -{ - unsigned int temp; - - temp = *(volatile unsigned int *) (EUMBBAR_VAL + regNum); - temp = PCISWAP (temp); - return temp; -} - - -/* - * Write a value to a register in the Embedded Utilities Memory - * Block address space. - * Input: regNum - register number + utility base address. Example, - * the base address of EPIC is 0x40000, the register - * number is 0x40000+the address of the target register. - * (See epic.h for register addresses). - * regVal - value to be written to the register. - */ - -void mpc824x_eummbar_write (unsigned int regNum, unsigned int regVal) -{ - *(volatile unsigned int *) (EUMBBAR_VAL + regNum) = PCISWAP (regVal); - return; -} - -/* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c deleted file mode 100644 index b6ac69321e..0000000000 --- a/arch/powerpc/cpu/mpc824x/cpu_init.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor. Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#ifndef CONFIG_SYS_BANK0_ROW -#define CONFIG_SYS_BANK0_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK1_ROW -#define CONFIG_SYS_BANK1_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK2_ROW -#define CONFIG_SYS_BANK2_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK3_ROW -#define CONFIG_SYS_BANK3_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK4_ROW -#define CONFIG_SYS_BANK4_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK5_ROW -#define CONFIG_SYS_BANK5_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK6_ROW -#define CONFIG_SYS_BANK6_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK7_ROW -#define CONFIG_SYS_BANK7_ROW 0 -#endif -#ifndef CONFIG_SYS_DBUS_SIZE2 -#define CONFIG_SYS_DBUS_SIZE2 0 -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - */ -void -cpu_init_f (void) -{ -/* MOUSSE board is initialized in asm */ -#if !defined(CONFIG_MOUSSE) - register unsigned long val; - CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ -/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ - -#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62) -/* Why is this here, you ask? Try, just try setting 0x8000 - * in PCIACR with CONFIG_WRITE_HALFWORD() - * this one was a stumper, and we are annoyed - */ - -#define M_CONFIG_WRITE_HALFWORD( addr, data ) \ - __asm__ __volatile__(" \ - stw %2,0(%0)\n \ - sync\n \ - sth %3,2(%1)\n \ - sync\n \ - " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \ - "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \ - ); - - M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); -#endif - - CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ - CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */ - /* - * Note that although this bit is cleared after a hard reset, it - * must be explicitly set and then cleared by software during - * initialization in order to guarantee correct operation of the - * DLL and the SDRAM_CLK[0:3] signals (if they are used). - */ - CONFIG_READ_BYTE (AMBOR, val); - CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); - CONFIG_WRITE_BYTE(AMBOR, val | 0x20); - CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); -#ifdef CONFIG_MPC8245 - /* silicon bug 28 MPC8245 */ - CONFIG_READ_BYTE(AMBOR,val); - CONFIG_WRITE_BYTE(AMBOR,val|0x1); - -#if 0 - /* - * The following bug only affects older (XPC8245) processors. - * DMA transfers initiated by external devices get corrupted due - * to a hardware scheduling problem. - * - * The effect is: - * when transferring X words, the first 32 words are transferred - * OK, the next 3 x 32 words are 'old' data (from previous DMA) - * while the rest of the X words is xferred fine. - * - * Disabling 3 of the 4 32 word hardware buffers solves the problem - * with no significant performance loss. - */ - - CONFIG_READ_BYTE(PCMBCR,val); - /* in order not to corrupt data which is being read over the PCI bus - * with the PPC as slave, we need to reduce the number of PCMRBs to 1, - * 4.11 in the processor user manual - * */ - -#if 1 - CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */ -#else - CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */ - CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */ - /* default, 4 PCMRBs are used */ -#endif -#endif -#endif - - CONFIG_READ_WORD(PICR1, val); -#if defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) | - PIRC1_MSK | PICR1_PROC_TYPE_603E | - PICR1_FLASH_WR_EN | PICR1_MCP_EN | - PICR1_CF_DPARK | PICR1_EN_PCS | - PICR1_CF_APARK ); -#elif defined(CONFIG_MPC8245) - CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_RCS0)) | - PICR1_PROC_TYPE_603E | - PICR1_FLASH_WR_EN | PICR1_MCP_EN | - PICR1_CF_DPARK | PICR1_NO_BUSW_CK | - PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - - CONFIG_READ_WORD(PICR2, val); - val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ -#ifndef CONFIG_PN62 - val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/ -#endif - CONFIG_WRITE_WORD(PICR2, val); - - CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR); -#ifndef CONFIG_SYS_RAMBOOT - CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | - (CONFIG_SYS_BANK0_ROW) | - (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | - (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | - (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) | - (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) | - (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | - (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | - (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | - (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)); -#endif - -#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL) - CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT | - CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT | - CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT); -#else - CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT); -#endif - -#if defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD(MCCR3, - (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | - (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)); -#elif defined(CONFIG_MPC8245) - CONFIG_WRITE_WORD(MCCR3, - (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT)); -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -/* this is gross. We think these should all be the same, and various boards - * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if - * its not set, we define it to zero in this file - */ -#if defined(CONFIG_CU824) || defined(CONFIG_PN62) - CONFIG_WRITE_WORD(MCCR4, - (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - MCCR4_BIT21 | - (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CONFIG_SYS_BSTOPRE & 0x0003) <> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); -#elif defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD(MCCR4, - (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - MCCR4_BIT21 | - (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CONFIG_SYS_BSTOPRE & 0x0003) <> 6) <> 6) <> MICR_ADDR_SHIFT) | - (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMSAR1, - ( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MSAR2, - ( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMSAR2, - ( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MEAR1, - ( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMEAR1, - ( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MEAR2, - ( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMEAR2, - ( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - - CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR); -#ifdef CONFIG_SYS_DLL_MAX_DELAY - CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */ -#endif -#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL) - CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL); -#endif -#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD) - CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */ -#endif /* setup & hold time */ - - CONFIG_WRITE_BYTE(MBER, - CONFIG_SYS_BANK0_ENABLE | - (CONFIG_SYS_BANK1_ENABLE << 1) | - (CONFIG_SYS_BANK2_ENABLE << 2) | - (CONFIG_SYS_BANK3_ENABLE << 3) | - (CONFIG_SYS_BANK4_ENABLE << 4) | - (CONFIG_SYS_BANK5_ENABLE << 5) | - (CONFIG_SYS_BANK6_ENABLE << 6) | - (CONFIG_SYS_BANK7_ENABLE << 7)); - -#ifdef CONFIG_SYS_PGMAX - CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX); -#endif - - /* ! Wait 200us before initialize other registers */ - /*FIXME: write a decent udelay wait */ - __asm__ __volatile__( - " mtctr %0 \n \ - 0: bdnz 0b\n" - : - : "r" (0x10000)); - - CONFIG_READ_WORD(MCCR1, val); - CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ - __asm__ __volatile__("eieio"); - -#endif /* !CONFIG_MOUSSE */ -} - - -#ifdef CONFIG_MOUSSE -#ifdef INCLUDE_MPC107_REPORT -struct MPC107_s { - unsigned int iobase; - char desc[120]; -} MPC107Regs[] = { - { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" }, - { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" }, - { BMC_BASE + 0x08, "MPC107 Revision" }, - { BMC_BASE + 0x0C, "MPC107 Cache Line Size" }, - { BMC_BASE + 0x10, "MPC107 LMBAR" }, - { BMC_BASE + 0x14, "MPC824x PCSR" }, - { BMC_BASE + 0xA8, "MPC824x PICR1" }, - { BMC_BASE + 0xAC, "MPC824x PICR2" }, - { BMC_BASE + 0x46, "MPC824x PACR" }, - { BMC_BASE + 0x310, "MPC824x ITWR" }, - { BMC_BASE + 0x300, "MPC824x OMBAR" }, - { BMC_BASE + 0x308, "MPC824x OTWR" }, - { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" }, - { BMC_BASE + 0x78, "MPC107 EUMBAR" }, - { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" }, - { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" }, - { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" }, - { BMC_BASE + 0xE0, "MPC107 AMBOR Register" }, - { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" }, - { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" }, - { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" }, - { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" }, -}; -#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0])) -#endif /* INCLUDE_MPC107_REPORT */ -#endif /* CONFIG_MOUSSE */ - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ -#ifdef CONFIG_MOUSSE -#ifdef INCLUDE_MPC107_REPORT - unsigned int tmp = 0, i; -#endif - /* - * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg). - * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can - * be accessed. - */ - -#ifdef CONFIG_MPC8240 /* only on MPC8240 */ - mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL); - /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */ - mpc824x_mpc107_setreg (AMBOR, 0x000000C0); -#endif - - -#ifdef INCLUDE_MPC107_REPORT - /* Check MPC824x PCI Device and Vendor ID */ - while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) { - printf (" MPC107: offset=0x%x, val = 0x%x\n", - BMC_BASE, - tmp); - } - - for (i = 0; i < N_MPC107_Regs; i++) { - printf (" 0x%x/%s = 0x%x\n", - MPC107Regs[i].iobase, - MPC107Regs[i].desc, - mpc824x_mpc107_getreg (MPC107Regs[i].iobase)); - } - - printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L)); - printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U)); - printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L)); - printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U)); - printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L)); - printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U)); - printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L)); - printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U)); - printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L)); - printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U)); - printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L)); - printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U)); - printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L)); - printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U)); - printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L)); - printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U)); -#endif /* INCLUDE_MPC107_REPORT */ -#endif /* CONFIG_MOUSSE */ - return (0); -} diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic.h b/arch/powerpc/cpu/mpc824x/drivers/epic.h deleted file mode 100644 index 2803f631cf..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic.h +++ /dev/null @@ -1 +0,0 @@ -#include "epic/epic.h" diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/README b/arch/powerpc/cpu/mpc824x/drivers/epic/README deleted file mode 100644 index 57989969b9..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/README +++ /dev/null @@ -1,102 +0,0 @@ -CONTENT: - - epic.h - epic1.c - epic2.s - -WHAT ARE THESE FILES: - -These files contain MPC8240 (Kahlua) EPIC -driver routines. The driver routines are not -written for any specific operating system. -They serves the purpose of code sample, and -jump-start for using the MPC8240 EPIC unit. - -For the reason of correctness of C language -syntax, these files are compiled by Metaware -C compiler and assembler. - -ENDIAN NOTATION: - -The algorithm is designed for big-endian mode, -software is responsible for byte swapping. - -USAGE: - -1. The host system that is running on MPC8240 - shall link the files listed here. The memory - location of driver routines shall take into - account of that driver routines need to run - in supervisor mode and they process external - interrupts. - - The routine epic_exception shall be called by - exception vector at location 0x500, i.e., - 603e core external exception vector. - -2. The host system is responsible for configuring - the MPC8240 including Embedded Utilities Memory - Block. All EPIC driver functions require the - content of Embedded Utilities Memory Block - Base Address Register, EUMBBAR, as the first - parameter. - -3. Before EPIC unit of MPC8240 can be used, - initialize EPIC unit by calling epicInit - with the corresponding parameters. - - The initialization shall disable the 603e - core External Exception by calling CoreExtIntDisable( ). - Next, call epicInit( ). Last, enable the 603e core - External Exception by calling CoreExtIntEnable( ). - -4. After EPIC unit has been successfully initialized, - epicIntSourceSet( ) shall be used to register each - external interrupt source. Anytime, an external - interrupt source can be disabled or enabled by - calling corresponding function, epicIntDisable( ), - or epicIntEnable( ). - - Global Timers' resource, base count and frequency, - can be changed by calling epicTmFrequencySet( ) - and epicTmBaseSet( ). - - To stop counting a specific global timer, use - the function, epicTmInhibit while epicTmEnable - can be used to start counting a timer. - -5. To mask a set of external interrupts that are - are certain level below, epicIntPrioritySet( ) - can be used. For example, if the processor's - current task priority register is set to 0x7, - only interrupts of priority 0x8 or higher will - be passed to the processor. - - Be careful when using this function. It may - corrupt the current interrupt pending, selector, - and request registers, resulting an invalid vetor. - - After enabling an interrupt, disable it may also - cause an invalid vector. User may consider using - the spurious vector interrupt service routine to - handle this case. - -6. The EPIC driver routines contains a set - of utilities, Set and Get, for host system - to query and modify the desired EPIC source - registers. - -7. Each external interrupt source shall register - its interrupt service routine. The routine - shall contain all interrupt source specific - processes and keep as short as possible. - - Special customized end of interrupt routine - is optional. If it is needed, it shall contain - the external interrupt source specific end of - interrupt process. - - External interrupt exception vector at 0x500 - shall always call the epicEOI just before - rfi instruction. Refer to the routine, - epic_exception, for a code sample. diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h b/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h deleted file mode 100644 index 58f81c5dfd..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h +++ /dev/null @@ -1,163 +0,0 @@ -/********************************************************************* - * mpc8240epic.h - EPIC module of the MPC8240 micro-controller - * - * Copyrigh 1999 Motorola Inc. - * - * Modification History: - * ===================== - * 01a,04Feb99,My Created. - * 15Nov200, robt -modified to use in U-Boot - * -*/ - -#ifndef __INCEPICh -#define __INCEPICh - -#define ULONG unsigned long -#define MAXVEC 20 -#define MAXIRQ 5 /* IRQs */ -#define EPIC_DIRECT_IRQ 0 /* Direct interrupt type */ - -/* EPIC register addresses */ - -#define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */ -#define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */ -#define EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */ -#define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */ -#define EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */ -#define EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */ -#define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */ -#define EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */ - -#define EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/ -#define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/ -#define EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/ -#define EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */ - -#define EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/ -#define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/ -#define EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/ -#define EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */ - -#define EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/ -#define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/ -#define EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/ -#define EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */ - -#define EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/ -#define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/ -#define EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/ -#define EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */ - -#define EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */ -#define EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/ -#define EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */ -#define EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/ -#define EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */ -#define EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/ -#define EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */ -#define EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/ -#define EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */ -#define EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/ - -#define EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */ -#define EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */ -#define EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */ -#define EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/ -#define EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */ -#define EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/ -#define EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */ -#define EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/ -#define EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */ -#define EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/ - -#define EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */ -#define EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/ -#define EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */ -#define EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/ -#define EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */ -#define EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/ -#define EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */ -#define EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/ -#define EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */ -#define EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/ - -#define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */ -#define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/ -#define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */ -#define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/ -#define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */ -#define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/ -#define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */ -#define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/ -#define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */ -#define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/ -#define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */ -#define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/ - -#define EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/ -#define EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */ -#define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/ -#define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */ -#define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/ -#define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */ -#define EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/ -#define EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest */ - -#define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/ -#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */ -#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */ - -#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */ -#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */ - -/* Error code */ - -#define OK 0 -#define ERROR -1 - -/* function prototypes */ - -void epicVendorId( unsigned int *step, - unsigned int *devId, - unsigned int *venId - ); -void epicFeatures( unsigned int *noIRQs, - unsigned int *noCPUs, - unsigned int *VerId ); -extern void epicInit( unsigned int IRQType, unsigned int clkRatio); -ULONG sysEUMBBARRead ( ULONG regNum ); -void sysEUMBBARWrite ( ULONG regNum, ULONG regVal); -extern void epicTmFrequencySet( unsigned int frq ); -extern unsigned int epicTmFrequencyGet(void); -extern unsigned int epicTmBaseSet( ULONG srcAddr, - unsigned int cnt, - unsigned int inhibit ); -extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val ); -extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ); -extern unsigned int epicTmInhibit( unsigned int timer ); -extern unsigned int epicTmEnable( ULONG srcAdr ); -extern void CoreExtIntEnable(void); /* Enable 603e external interrupts */ -extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */ -extern unsigned char epicIntTaskGet(void); -extern void epicIntTaskSet( unsigned char val ); -extern unsigned int epicIntAck(void); -extern void epicSprSet( unsigned int eumbbar, unsigned char ); -extern void epicConfigGet( unsigned int *clkRatio, - unsigned int *serEnable ); -extern void SrcVecTableInit(void); -extern unsigned int epicModeGet(void); -extern void epicIntEnable(int Vect); -extern void epicIntDisable(int Vect); -extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio); -extern unsigned int epicIntAck(void); -extern void epicEOI(void); -extern int epicCurTaskPrioSet(int Vect); - -struct SrcVecTable - { - ULONG srcAddr; - char srcName[40]; - }; - -#endif /* EPIC_H */ diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c b/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c deleted file mode 100644 index ecbb42d0d6..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c +++ /dev/null @@ -1,517 +0,0 @@ -/************************************************** - * - * copyright @ motorola, 1999 - * - *************************************************/ -#include -#include -#include "epic.h" - - -#define PRINT(format, args...) printf(format , ## args) - -typedef void (*VOIDFUNCPTR) (void); /* ptr to function returning void */ -struct SrcVecTable SrcVecTable[MAXVEC] = /* Addr/Vector cross-reference tbl */ - { - { EPIC_EX_INT0_VEC_REG, "External Direct/Serial Source 0"}, - { EPIC_EX_INT1_VEC_REG, "External Direct/Serial Source 1"}, - { EPIC_EX_INT2_VEC_REG, "External Direct/Serial Source 2"}, - { EPIC_EX_INT3_VEC_REG, "External Direct/Serial Source 3"}, - { EPIC_EX_INT4_VEC_REG, "External Direct/Serial Source 4"}, - - { EPIC_SR_INT5_VEC_REG, "External Serial Source 5"}, - { EPIC_SR_INT6_VEC_REG, "External Serial Source 6"}, - { EPIC_SR_INT7_VEC_REG, "External Serial Source 7"}, - { EPIC_SR_INT8_VEC_REG, "External Serial Source 8"}, - { EPIC_SR_INT9_VEC_REG, "External Serial Source 9"}, - { EPIC_SR_INT10_VEC_REG, "External Serial Source 10"}, - { EPIC_SR_INT11_VEC_REG, "External Serial Source 11"}, - { EPIC_SR_INT12_VEC_REG, "External Serial Source 12"}, - { EPIC_SR_INT13_VEC_REG, "External Serial Source 13"}, - { EPIC_SR_INT14_VEC_REG, "External Serial Source 14"}, - { EPIC_SR_INT15_VEC_REG, "External Serial Source 15"}, - - { EPIC_I2C_INT_VEC_REG, "Internal I2C Source"}, - { EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source"}, - { EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source"}, - { EPIC_MSG_INT_VEC_REG, "Internal Message Source"}, - }; - -VOIDFUNCPTR intVecTbl[MAXVEC]; /* Interrupt vector table */ - - -/**************************************************************************** -* epicInit - Initialize the EPIC registers -* -* This routine resets the Global Configuration Register, thus it: -* - Disables all interrupts -* - Sets epic registers to reset values -* - Sets the value of the Processor Current Task Priority to the -* highest priority (0xF). -* epicInit then sets the EPIC operation mode to Mixed Mode (vs. Pass -* Through or 8259 compatible mode). -* -* If IRQType (input) is Direct IRQs: -* - IRQType is written to the SIE bit of the EPIC Interrupt -* Configuration register (ICR). -* - clkRatio is ignored. -* If IRQType is Serial IRQs: -* - both IRQType and clkRatio will be written to the ICR register -*/ - -void epicInit - ( - unsigned int IRQType, /* Direct or Serial */ - unsigned int clkRatio /* Clk Ratio for Serial IRQs */ - ) - { - ULONG tmp; - - tmp = sysEUMBBARRead(EPIC_GLOBAL_REG); - tmp |= 0xa0000000; /* Set the Global Conf. register */ - sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp); - /* - * Wait for EPIC to reset - CLH - */ - while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1); - sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000); - tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */ - - if (IRQType == EPIC_DIRECT_IRQ) /* direct mode */ - sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff); - else /* Serial mode */ - { - tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */ - sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp); - } - - while (epicIntAck() != 0xff) /* Clear all pending interrupts */ - epicEOI(); -} - -/**************************************************************************** - * epicIntEnable - Enable an interrupt source - * - * This routine clears the mask bit of an external, an internal or - * a Timer register to enable the interrupt. - * - * RETURNS: None - */ -void epicIntEnable(int intVec) -{ - ULONG tmp; - ULONG srAddr; - - srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */ - tmp = sysEUMBBARRead(srAddr); - tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */ - tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */ - tmp |= intVec; /* Set Vector number */ - sysEUMBBARWrite(srAddr, tmp); - - return; - } - -/**************************************************************************** - * epicIntDisable - Disable an interrupt source - * - * This routine sets the mask bit of an external, an internal or - * a Timer register to disable the interrupt. - * - * RETURNS: OK or ERROR - * - */ - -void epicIntDisable - ( - int intVec /* Interrupt vector number */ - ) - { - - ULONG tmp, srAddr; - - srAddr = SrcVecTable[intVec].srcAddr; - tmp = sysEUMBBARRead(srAddr); - tmp |= 0x80000000; /* Set the mask bit */ - sysEUMBBARWrite(srAddr, tmp); - return; - } - -/**************************************************************************** - * epicIntSourceConfig - Set properties of an interrupt source - * - * This function sets interrupt properites (Polarity, Sense, Interrupt - * Prority, and Interrupt Vector) of an Interrupt Source. The properties - * can be set when the current source is not in-request or in-service, - * which is determined by the Activity bit. This routine return ERROR - * if the the Activity bit is 1 (in-request or in-service). - * - * This function assumes that the Source Vector/Priority register (input) - * is a valid address. - * - * RETURNS: OK or ERROR - */ - -int epicIntSourceConfig - ( - int Vect, /* interrupt source vector number */ - int Polarity, /* interrupt source polarity */ - int Sense, /* interrupt source Sense */ - int Prio /* interrupt source priority */ - ) - - { - ULONG tmp, newVal; - ULONG actBit, srAddr; - - srAddr = SrcVecTable[Vect].srcAddr; - tmp = sysEUMBBARRead(srAddr); - actBit = (tmp & 40000000) >> 30; /* retrieve activity bit - bit 30 */ - if (actBit == 1) - return ERROR; - - tmp &= 0xff30ff00; /* Erase previously set P,S,Prio,Vector bits */ - newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect; - sysEUMBBARWrite(srAddr, tmp | newVal ); - return (OK); - } - -/**************************************************************************** - * epicIntAck - acknowledge an interrupt - * - * This function reads the Interrupt acknowldge register and return - * the vector number of the highest pending interrupt. - * - * RETURNS: Interrupt Vector number. - */ - -unsigned int epicIntAck(void) -{ - return(sysEUMBBARRead( EPIC_PROC_INT_ACK_REG )); -} - -/**************************************************************************** - * epicEOI - signal an end of interrupt - * - * This function writes 0x0 to the EOI register to signal end of interrupt. - * It is usually called after an interrupt routine is served. - * - * RETURNS: None - */ - -void epicEOI(void) - { - sysEUMBBARWrite(EPIC_PROC_EOI_REG, 0x0); - } - -/**************************************************************************** - * epicCurTaskPrioSet - sets the priority of the Processor Current Task - * - * This function should be called after epicInit() to lower the priority - * of the processor current task. - * - * RETURNS: OK or ERROR - */ - -int epicCurTaskPrioSet - ( - int prioNum /* New priority value */ - ) - { - - if ( (prioNum < 0) || (prioNum > 0xF)) - return ERROR; - sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum); - return OK; - } - - -/************************************************************************ - * function: epicIntTaskGet - * - * description: Get value of processor current interrupt task priority register - * - * note: - ***********************************************************************/ -unsigned char epicIntTaskGet() -{ - /* get the interrupt task priority register */ - ULONG reg; - unsigned char rec; - - reg = sysEUMBBARRead( EPIC_PROC_CTASK_PRI_REG ); - rec = ( reg & 0x0F ); - return rec; -} - - -/************************************************************** - * function: epicISR - * - * description: EPIC service routine called by the core exception - * at 0x500 - * - * note: - **************************************************************/ -unsigned int epicISR(void) -{ - return 0; -} - - -/************************************************************ - * function: epicModeGet - * - * description: query EPIC mode, return 0 if pass through mode - * return 1 if mixed mode - * - * note: - *************************************************************/ -unsigned int epicModeGet(void) -{ - ULONG val; - - val = sysEUMBBARRead( EPIC_GLOBAL_REG ); - return (( val & 0x20000000 ) >> 29); -} - - -/********************************************* - * function: epicConfigGet - * - * description: Get the EPIC interrupt Configuration - * return 0 if not error, otherwise return 1 - * - * note: - ********************************************/ -void epicConfigGet( unsigned int *clkRatio, unsigned int *serEnable) -{ - ULONG val; - - val = sysEUMBBARRead( EPIC_INT_CONF_REG ); - *clkRatio = ( val & 0x70000000 ) >> 28; - *serEnable = ( val & 0x8000000 ) >> 27; -} - - -/******************************************************************* - * sysEUMBBARRead - Read a 32-bit EUMBBAR register - * - * This routine reads the content of a register in the Embedded - * Utilities Memory Block, and swaps to big endian before returning - * the value. - * - * RETURNS: The content of the specified EUMBBAR register. - */ - -ULONG sysEUMBBARRead - ( - ULONG regNum - ) - { - ULONG temp; - - temp = *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum); - return ( LONGSWAP(temp)); - } - -/******************************************************************* - * sysEUMBBARWrite - Write a 32-bit EUMBBAR register - * - * This routine swaps the value to little endian then writes it to - * a register in the Embedded Utilities Memory Block address space. - * - * RETURNS: N/A - */ - -void sysEUMBBARWrite - ( - ULONG regNum, /* EUMBBAR register address */ - ULONG regVal /* Value to be written */ - ) - { - - *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum) = LONGSWAP(regVal); - return ; - } - - -/******************************************************** - * function: epicVendorId - * - * description: return the EPIC Vendor Identification - * register: - * - * siliccon version, device id, and vendor id - * - * note: - ********************************************************/ -void epicVendorId - ( - unsigned int *step, - unsigned int *devId, - unsigned int *venId - ) - { - ULONG val; - val = sysEUMBBARRead( EPIC_VENDOR_ID_REG ); - *step = ( val & 0x00FF0000 ) >> 16; - *devId = ( val & 0x0000FF00 ) >> 8; - *venId = ( val & 0x000000FF ); - } - -/************************************************** - * function: epicFeatures - * - * description: return the number of IRQ supported, - * number of CPU, and the version of the - * OpenEPIC - * - * note: - *************************************************/ -void epicFeatures - ( - unsigned int *noIRQs, - unsigned int *noCPUs, - unsigned int *verId - ) - { - ULONG val; - - val = sysEUMBBARRead( EPIC_FEATURES_REG ); - *noIRQs = ( val & 0x07FF0000 ) >> 16; - *noCPUs = ( val & 0x00001F00 ) >> 8; - *verId = ( val & 0x000000FF ); -} - - -/********************************************************* - * function: epciTmFrequncySet - * - * description: Set the timer frequency reporting register - ********************************************************/ -void epicTmFrequencySet( unsigned int frq ) -{ - sysEUMBBARWrite(EPIC_TM_FREQ_REG, frq); -} - -/******************************************************* - * function: epicTmFrequncyGet - * - * description: Get the current value of the Timer Frequency - * Reporting register - * - ******************************************************/ -unsigned int epicTmFrequencyGet(void) -{ - return( sysEUMBBARRead(EPIC_TM_FREQ_REG)) ; -} - - -/**************************************************** - * function: epicTmBaseSet - * - * description: Set the #n global timer base count register - * return 0 if no error, otherwise return 1. - * - * note: - ****************************************************/ -unsigned int epicTmBaseSet - ( - ULONG srcAddr, /* Address of the Timer Base register */ - unsigned int cnt, /* Base count */ - unsigned int inhibit /* 1 - count inhibit */ - ) -{ - - unsigned int val = 0x80000000; - /* First inhibit counting the timer */ - sysEUMBBARWrite(srcAddr, val) ; - - /* set the new value */ - val = (cnt & 0x7fffffff) | ((inhibit & 0x1) << 31); - sysEUMBBARWrite(srcAddr, val) ; - return 0; -} - -/*********************************************************************** - * function: epicTmBaseGet - * - * description: Get the current value of the global timer base count register - * return 0 if no error, otherwise return 1. - * - * note: - ***********************************************************************/ -unsigned int epicTmBaseGet( ULONG srcAddr, unsigned int *val ) -{ - *val = sysEUMBBARRead( srcAddr ); - *val = *val & 0x7fffffff; - return 0; -} - -/*********************************************************** - * function: epicTmCountGet - * - * description: Get the value of a given global timer - * current count register - * return 0 if no error, otherwise return 1 - * note: - **********************************************************/ -unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ) -{ - *val = sysEUMBBARRead( srcAddr ); - *val = *val & 0x7fffffff; - return 0; -} - - -/*********************************************************** - * function: epicTmInhibit - * - * description: Stop counting of a given global timer - * return 0 if no error, otherwise return 1 - * - * note: - ***********************************************************/ -unsigned int epicTmInhibit( unsigned int srcAddr ) -{ - ULONG val; - - val = sysEUMBBARRead( srcAddr ); - val |= 0x80000000; - sysEUMBBARWrite( srcAddr, val ); - return 0; -} - -/****************************************************************** - * function: epicTmEnable - * - * description: Enable counting of a given global timer - * return 0 if no error, otherwise return 1 - * - * note: - *****************************************************************/ -unsigned int epicTmEnable( ULONG srcAddr ) -{ - ULONG val; - - val = sysEUMBBARRead( srcAddr ); - val &= 0x7fffffff; - sysEUMBBARWrite( srcAddr, val ); - return 0; -} - -void epicSourcePrint(int Vect) - { - ULONG srcVal; - - srcVal = sysEUMBBARRead(SrcVecTable[Vect].srcAddr); - PRINT("%s\n", SrcVecTable[Vect].srcName); - PRINT("Address = 0x%lx\n", SrcVecTable[Vect].srcAddr); - PRINT("Vector = %ld\n", (srcVal & 0x000000FF) ); - PRINT("Mask = %ld\n", srcVal >> 31); - PRINT("Activitiy = %ld\n", (srcVal & 40000000) >> 30); - PRINT("Polarity = %ld\n", (srcVal & 0x00800000) >> 23); - PRINT("Sense = %ld\n", (srcVal & 0x00400000) >> 22); - PRINT("Priority = %ld\n", (srcVal & 0x000F0000) >> 16); - } diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S b/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S deleted file mode 100644 index 52d19aae8e..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S +++ /dev/null @@ -1,196 +0,0 @@ -/************************************** - * - * copyright @ Motorola, 1999 - * - **************************************/ - -#include -#include -#include - -/********************************************* - * function: CoreExtIntEnable - * - * description: Enable 603e core external interrupt - * - * note: mtmsr is context-synchronization - **********************************************/ - .text - .align 2 - .global CoreExtIntEnable -CoreExtIntEnable: - mfmsr r3 - - ori r3,r3,0x8000 /* enable external interrupt */ - mtmsr r3 - - bclr 20, 0 - -/******************************************* - * function: CoreExtIntDisable - * - * description: Disable 603e core external interrupt - * - * note: - *******************************************/ - .text - .align 2 - .global CoreExtIntDisable -CoreExtIntDisable: - mfmsr r4 - - xor r3,r3,r3 - or r3,r3,r4 - - andis. r4,r4,0xffff - andi. r3,r3,0x7fff /* disable external interrupt */ - - or r3,r3,r4 - mtmsr r3 - - bclr 20, 0 - -/********************************************************* - * function: epicEOI - * - * description: signal the EOI and restore machine status - * Input: r3 - value of eumbbar - * Output: r3 - value of eumbbar - * r4 - ISR vector value - * note: - ********************************************************/ - .text - .align 2 - .global epicEOI -epicEOI: - lis r5,0x0006 /* Build End Of Interrupt Register offset */ - ori r5,r5,0x00b0 - xor r7,r7,r7 /* Clear r7 */ - stwbrx r7,r5,r3 /* Save r7, writing to this register will - * intidate the end of processing the - * highest interrupt. - */ - sync - - /* ---RESTORE MACHINE STATE */ - mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */ - or r7,r7,r13 - - andis. r7,r7,0xffff - andi. r13,r13,0x7ffd /* (and disable interrupts) */ - or r13,r13,r7 - mtmsr r13 - - lwz r13,0x1c(r1) /* pull ctr */ - mtctr r13 - - lwz r13,0x18(r1) /* pull xer */ - mtctr r13 - - lwz r13,0x14(r1) /* pull lr */ - mtctr r13 - - lwz r13,0x10(r1) /* Pull SRR1 from stack */ - mtspr SRR1,r13 /* Restore SRR1 */ - - lwz r13,0xc(r1) /* Pull SRR0 from stack */ - mtspr SRR0,r13 /* Restore SRR0 */ - - lwz r13,0x8(r1) /* Pull User stack pointer from stack */ - mtspr SPRG1,r13 /* Restore SPRG1 */ - - lwz r4,0x4(r1) /* vector value */ - lwz r3,0x0(r1) /* eumbbar */ - sync - - addi r1,r1,0x20 /* Deallocate stack */ - mtspr SPRG0,r1 /* Save updated Supervisor stack pointer */ - mfspr r1,SPRG1 /* Restore User stack pointer */ - - bclr 20,0 - -/*********************************************************** - * function: exception routine called by exception vector - * at 0x500, external interrupt - * - * description: Kahlua EPIC controller - * - * input: r3 - content of eumbbar - * output: r3 - ISR return value - * r4 - Interrupt vector number - * note: - ***********************************************************/ - - .text - .align 2 - .global epic_exception - -epic_exception: - - /*---SAVE MACHINE STATE TO A STACK */ - mtspr SPRG1,r1 /* Save User stack pointer to SPRG1 */ - mfspr r1,SPRG0 /* Load Supervisor stack pointer into r1 */ - - stwu r3,-0x20(r1) /* Push the value of eumbbar onto stack */ - - mfspr r3,SPRG1 /* Push User stack pointer onto stack */ - stw r3,0x8(r1) - mfspr r3,SRR0 /* Push SRR0 onto stack */ - stw r1,0xc(r1) - mfspr r3,SRR1 /* Push SRR1 onto stack */ - stw r3,0x10(r1) - mflr r3 - stw r3,0x14(r1) /* Push LR */ - mfxer r3 - stw r3,0x18(r1) /* Push Xer */ - mfctr r3 - stw r3,0x1c(r1) /* Push CTR */ - - mtspr SPRG0,r1 /* Save updated Supervisor stack pointer - * value to SPRG0 - */ - mfmsr r3 - ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */ - mtmsr r3 - - /* ---READ IN THE EUMBAR REGISTER */ - lwz r6,0(r1) /* this is eumbbar */ - sync - - /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */ - lis r5,0x0006 /* Build Interrupt Acknowledge Register - * offset - */ - ori r5,r5,0x00a0 - lwbrx r7,r5,r6 /* Load interrupt vector into r7 */ - sync - - /* --MASK OFF ALL BITS EXCEPT THE VECTOR */ - xor r3,r3,r3 - xor r4,r4,r4 - or r3, r3, r6 /* eumbbar in r3 */ - andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ - - stw r4,0x04(r1) /* save the vector value */ - - lis r5,epicISR@ha - ori r5,r5,epicISR@l - mtlr r5 - blrl - - xor r30,r30,r30 - or r30,r30,r3 /* save the r3 which containts the return value from epicISR */ - - /* ---READ IN THE EUMBAR REGISTER */ - lwz r3,0(r1) - sync - - lis r5,epicEOI@ha - ori r5,r5,epicEOI@l - mtlr r5 - blrl - - xor r3,r3,r3 - or r3,r3,r30 /* restore the ISR return value */ - - bclr 20,0 diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S b/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S deleted file mode 100644 index 4877050ba4..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S +++ /dev/null @@ -1,57 +0,0 @@ -/************************************** - * - * copyright @ Motorola, 1999 - * - * - * This file contains two commonly used - * lower level utility routines. - * - * The utility routines are also in other - * Kahlua device driver libraries. The - * need to be linked in only once. - **************************************/ - -#include -#include - -/********************************************************** - * function: load_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * - * output: r3 - register content - **********************************************************/ - .text - .align 2 - .global load_runtime_reg - -load_runtime_reg: - - xor r5,r5,r5 - or r5,r5,r3 /* save eumbbar */ - - lwbrx r3,r4,r5 - sync - - bclr 20, 0 - -/**************************************************************** - * function: store_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * r5 - new value to be stored - * - ****************************************************************/ - .text - .align 2 - .global store_runtime_reg -store_runtime_reg: - - xor r0,r0,r0 - - stwbrx r5, r4, r3 - sync - - bclr 20,0 diff --git a/arch/powerpc/cpu/mpc824x/drivers/errors.h b/arch/powerpc/cpu/mpc824x/drivers/errors.h deleted file mode 100644 index 20794a2e89..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/errors.h +++ /dev/null @@ -1,212 +0,0 @@ -/* Copyright Motorola, Inc. 1993, 1994 - ALL RIGHTS RESERVED - - You are hereby granted a copyright license to use, modify, and - distribute the SOFTWARE so long as this entire notice is retained - without alteration in any modified and/or redistributed versions, - and that such modified versions are clearly identified as such. - No licenses are granted by implication, estoppel or otherwise under - any patents or trademarks of Motorola, Inc. - - The SOFTWARE is provided on an "AS IS" basis and without warranty. - To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS - ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED - WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR - PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS - THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. - - To the maximum extent permitted by applicable law, IN NO EVENT SHALL - MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER - (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF - BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS - INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR - INABILITY TO USE THE SOFTWARE. Motorola assumes no responsibility - for the maintenance and support of the SOFTWARE. - -*/ - - -#include "config.h" - -/* - 1 2 3 4 5 6 7 8 -01234567890123456789012345678901234567890123456789012345678901234567890123456789 -*/ -/* List define statements here */ - -/* These are for all the toolboxes and functions to use. These will help -to standardize the error handling in the current project */ - - /* this is the "data type" for the error - messages in the system */ -#define STATUS unsigned int - - /* this is a success status code */ -#define SUCCESS 1 - - /* likewise this is failure */ -#define FAILURE 0 - -#define NUM_ERRORS 47 - -/* This first section of "defines" are for error codes ONLY. The called - routine will return one of these error codes to the caller. If the final - returned code is "VALID", then everything is a-okay. However, if one - of the functions returns a non-valid status, that error code should be - propogated back to all the callers. At the end, the last caller will - call an error_processing function, and send in the status which was - returned. It's up to the error_processing function to determine which - error occured (as indicated by the status), and print an appropriate - message back to the user. -*/ -/*----------------------------------------------------------------------*/ -/* these are specifically for the parser routines */ - -#define UNKNOWN_COMMAND 0xfb00 /* "unrecognized command " */ -#define UNKNOWN_REGISTER 0xfb01 /* "unknown register "*/ -#define ILLEGAL_RD_STAGE 0xfb02 /* cannot specify reg. family in range*/ -#define ILLEGAL_REG_FAMILY 0xfb03 /* "cannot specify a range of special - or miscellaneous registers"*/ -#define RANGE_CROSS_FAMILY 0xfb04 /* "cannot specify a range across - register families" */ -#define UNIMPLEMENTED_STAGE 0xfb05 /* invalid rd or rmm parameter format */ -#define REG_NOT_WRITEABLE 0xfb06 /* "unknown operator in arguements"*/ -#define INVALID_FILENAME 0xfb07 /* "invalid download filename" */ -#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */ -#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */ -#define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */ - - -/*----------------------------------------------------------------------*/ -/* these are for the error checking toolbox */ - -#define INVALID 0xfd00 /* NOT valid */ -#define VALID 0xfd01 /* valid */ - - /* This error is found in the fcn: - is_right_size_input() to indicate - that the input was not 8 characters - long. */ -#define INVALID_SIZE 0xfd02 - - /* This error is found in the fcn: - is_valid_address_range() to indicate - that the address given falls outside - of valid memory defined by MEM_START - to MEM_END. - */ -#define OUT_OF_BOUNDS_ADDRESS 0xfd03 - - /* This error is found in the fcn: - is_valid_hex_input() to indicate that - one of more of the characters entered - are not valid hex characters. Valid - hex characters are 0-9, A-F, a-f. - */ -#define INVALID_HEX_INPUT 0xfd04 - - /* This error is found in the fcn: - is_valid_register_number() to indicate - that a given register does not exist. - */ -#define REG_NOT_READABLE 0xfd05 - - /* This error is found in the fcn: - is_word_aligned_address() to indicate - that the given address is not word- - aligned. A word-aligned address ends - in 0x0,0x4,0x8,0xc. - */ -#define NOT_WORD_ALIGNED 0xfd07 - - /* This error is found in the fcn: - is_valid_address_range() to indicate - that the starting address is greater - than the ending address. - */ -#define REVERSED_ADDRESS 0xfd08 - - /* this error tells us that the address - specified as the destination is within - the source addresses */ -#define RANGE_OVERLAP 0xfd09 - - -#define ERROR 0xfd0a /* An error occured */ -#define INVALID_PARAM 0xfd0b /* "invalid input parameter " */ - - -#define INVALID_FLAG 0xfd0c /* invalid flag */ - -/*----------------------------------------------------------------------*/ -/* these are for the getarg toolbox */ - -#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */ -#define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/ - - -/*----------------------------------------------------------------------*/ -/* these are for the tokenizer toolbox */ - -#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/ -#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */ -#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/ -#define INVALID_STRING 0xFF03 /* unable to extract string from input */ -#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */ -#define INVALID_MODE 0xFF05 /* input buf is in an unrecognized mode*/ -#define TOK_INTERNAL_ERROR 0xFF06 /* "internal tokenizer error" */ -#define TOO_MANY_IBS 0xFF07 /* "too many open input buffers" */ -#define NO_OPEN_IBS 0xFF08 /* "no open input buffers" */ - - -/* these are for the read from screen toolbox */ - -#define RESERVED_WORD 0xFC00 /* used a reserved word as an arguement*/ - - -/* these are for the breakpoint routines */ - -#define FULL_BPDS 0xFA00 /* breakpoint data structure is full */ - - -/* THESE are for the downloader */ - -#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */ -#define UNREC_RECORD_TYPE 0xf901 /* "unrecognized record type" */ -#define CONVERSION_ERROR 0xf902 /* "ascii to int conversion error" */ -#define INVALID_MEMORY 0xf903 /* "bad s-record memory address " */ - - -/* these are for the compression and decompression stuff */ - -#define COMP_UNK_CHARACTER 0xf800 /* "unknown compressed character " */ - -#define COMP_UNKNOWN_STATE 0xf801 /* "unknown binary state" */ - -#define NOT_IN_COMPRESSED_FORMAT 0xf802 /* not in compressed S-Record format */ - - -/* these are for the DUART handling things */ - - /* "unrecognized serial port configuration" */ -#define UNKNOWN_PORT_STATE 0xf700 - - -/* these are for the register toolbox */ - - /* "cannot find register in special - purpose register file " */ -#define SPR_NOT_FOUND 0xf600 - - -/* these are for the duart specific stuff */ - - /* "transparent mode needs access to - two serial ports" */ -#define TM_NEEDS_BOTH_PORTS 0xf500 - - -/*----------------------------------------------------------------------*/ -/* these are specifically for the flash routines */ -#define FLASH_ERROR 0xf100 /* general flash error */ diff --git a/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c b/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c deleted file mode 100644 index 3638ab0f8a..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#undef I2CDBG - -#ifdef CONFIG_HARD_I2C -#include - -#define TIMEOUT (CONFIG_SYS_HZ/4) - -#define I2C_Addr ((unsigned *)(CONFIG_SYS_EUMB_ADDR + 0x3000)) - -#define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[1] -#define I2CCCR &I2C_Addr[2] -#define I2CCSR &I2C_Addr[3] -#define I2CCDR &I2C_Addr[4] - -#define MPC107_CCR_MEN 0x80 -#define MPC107_CCR_MIEN 0x40 -#define MPC107_CCR_MSTA 0x20 -#define MPC107_CCR_MTX 0x10 -#define MPC107_CCR_TXAK 0x08 -#define MPC107_CCR_RSTA 0x04 - -#define MPC107_CSR_MCF 0x80 -#define MPC107_CSR_MAAS 0x40 -#define MPC107_CSR_MBB 0x20 -#define MPC107_CSR_MAL 0x10 -#define MPC107_CSR_SRW 0x04 -#define MPC107_CSR_MIF 0x02 -#define MPC107_CSR_RXAK 0x01 - -#define I2C_READ 1 -#define I2C_WRITE 0 - -/* taken from linux include/asm-ppc/io.h */ -inline unsigned in_le32 (volatile unsigned *addr) -{ - unsigned ret; - - __asm__ __volatile__ ("lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync":"=r" (ret): "r" (addr), "m" (*addr)); - return ret; -} - -inline void out_le32 (volatile unsigned *addr, int val) -{ - __asm__ __volatile__ ("stwbrx %1,0,%2; eieio":"=m" (*addr):"r" (val), - "r" (addr)); -} - -#define writel(val, addr) out_le32(addr, val) -#define readl(addr) in_le32(addr) - -void i2c_init (int speed, int slaveadd) -{ - /* stop I2C controller */ - writel (0x0, I2CCCR); - /* set clock */ - writel (0x1020, I2CFDR); - /* write slave address */ - writel (slaveadd, I2CADR); - /* clear status register */ - writel (0x0, I2CCSR); - /* start I2C controller */ - writel (MPC107_CCR_MEN, I2CCCR); - - return; -} - -static __inline__ int i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - - while (readl (I2CCSR) & MPC107_CSR_MBB) - if (get_timer (timeval) > TIMEOUT) - return -1; - - return 0; -} - -static __inline__ int i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer (0); - - do { - csr = readl (I2CCSR); - - if (!(csr & MPC107_CSR_MIF)) - continue; - - writel (0x0, I2CCSR); - - if (csr & MPC107_CSR_MAL) { -#ifdef I2CDBG - printf ("i2c_wait: MAL\n"); -#endif - return -1; - } - - if (!(csr & MPC107_CSR_MCF)) { -#ifdef I2CDBG - printf ("i2c_wait: unfinished\n"); -#endif - return -1; - } - - if (write == I2C_WRITE && (csr & MPC107_CSR_RXAK)) { -#ifdef I2CDBG - printf ("i2c_wait: No RXACK\n"); -#endif - return -1; - } - - return 0; - } while (get_timer (timeval) < TIMEOUT); - -#ifdef I2CDBG - printf ("i2c_wait: timed out\n"); -#endif - return -1; -} - -static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX | - (rsta ? MPC107_CCR_RSTA : 0), I2CCCR); - - writel ((dev << 1) | dir, I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - - return 1; -} - -static __inline__ int __i2c_write (u8 * data, int length) -{ - int i; - - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX, I2CCCR); - - for (i = 0; i < length; i++) { - writel (data[i], I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - - return i; -} - -static __inline__ int __i2c_read (u8 * data, int length) -{ - int i; - - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | - ((length == 1) ? MPC107_CCR_TXAK : 0), I2CCCR); - - /* dummy read */ - readl (I2CCDR); - - for (i = 0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | - MPC107_CCR_TXAK, I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writel (MPC107_CCR_MEN | MPC107_CCR_TXAK, I2CCCR); - - data[i] = readl (I2CCDR); - } - - return i; -} - -int i2c_read (u8 dev, uint addr, int alen, u8 * data, int length) -{ - int i = 0; - u8 *a = (u8 *) & addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - -exit: - writel (MPC107_CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_write (u8 dev, uint addr, int alen, u8 * data, int length) -{ - int i = 0; - u8 *a = (u8 *) & addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - -exit: - writel (MPC107_CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay (10000); - return i2c_read (chip, 0, 1, (uchar *) &tmp, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h b/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h deleted file mode 100644 index 6264d189bb..0000000000 --- a/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h +++ /dev/null @@ -1,103 +0,0 @@ -#ifndef I2C_EXPORT_H -#define I2C_EXPORT_H - -/**************************************************** - * - * Copyright Motrola 1999 - * - ****************************************************/ - -/* These are the defined return values for the I2C_do_transaction function. - * Any non-zero value indicates failure. Failure modes can be added for - * more detailed error reporting. - */ -typedef enum _i2c_status -{ - I2C_SUCCESS = 0, - I2C_ERROR, -} I2C_Status; - -/* These are the defined tasks for I2C_do_transaction. - * Modes for SLAVE_RCV and SLAVE_XMIT will be added. - */ -typedef enum _i2c_transaction_mode -{ - I2C_MASTER_RCV = 0, - I2C_MASTER_XMIT = 1, -} I2C_TRANSACTION_MODE; - -typedef enum _i2c_interrupt_mode -{ - I2C_INT_DISABLE = 0, - I2C_INT_ENABLE = 1, -} I2C_INTERRUPT_MODE; - -typedef enum _i2c_stop -{ - I2C_NO_STOP = 0, - I2C_STOP = 1, -} I2C_STOP_MODE; - -typedef enum _i2c_restart -{ - I2C_NO_RESTART = 0, - I2C_RESTART = 1, -} I2C_RESTART_MODE; - -/******************** App. API ******************** - * The application API is for user level application - * to use the functionality provided by I2C driver. - * This is a "generic" I2C interface, it should contain - * nothing specific to the Kahlua implementation. - * Only the generic functions are exported by the library. - * - * Note: Its App.s responsibility to swap the data - * byte. In our API, we just transfer whatever - * we are given - **************************************************/ - - -/* Initialize I2C unit with the following: - * driver's slave address - * interrupt enabled - * optional pointer to application layer print function - * - * These parameters may be added: - * desired clock rate - * digital filter frequency sampling rate - * - * This function must be called before I2C unit can be used. - */ -extern I2C_Status I2C_Initialize( - unsigned char addr, /* driver's I2C slave address */ - I2C_INTERRUPT_MODE en_int, /* 1 - enable I2C interrupt - * 0 - disable I2C interrupt - */ - int (*app_print_function)(char *,...)); /* pointer to optional "printf" - * provided by application - */ - -/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV - * are implemented. Both are only in polling mode. - * - * en_int controls interrupt/polling mode - * act is the type of transaction - * addr is the I2C address of the slave device - * len is the length of data to send or receive - * buffer is the address of the data buffer - * stop = I2C_NO_STOP, don't signal STOP at end of transaction - * I2C_STOP, signal STOP at end of transaction - * retry is the timeout retry value, currently ignored - * rsta = I2C_NO_RESTART, this is not continuation of existing transaction - * I2C_RESTART, this is a continuation of existing transaction - */ -extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int, - I2C_TRANSACTION_MODE act, - unsigned char i2c_addr, - unsigned char data_addr, - int len, - char *buffer, - I2C_STOP_MODE stop, - int retry, - I2C_RESTART_MODE rsta); -#endif diff --git a/arch/powerpc/cpu/mpc824x/interrupts.c b/arch/powerpc/cpu/mpc824x/interrupts.c deleted file mode 100644 index fad103fc6b..0000000000 --- a/arch/powerpc/cpu/mpc824x/interrupts.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "drivers/epic.h" - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - *decrementer_count = (get_bus_freq (0) / 4) / CONFIG_SYS_HZ; - - /* - * It's all broken at the moment and I currently don't need - * interrupts. If you want to fix it, have a look at the epic - * drivers in dink32 v12. They do everthing and Motorola said - * I could use the dink source in this project as long as - * copyright notices remain intact. - */ - - epicInit (EPIC_DIRECT_IRQ, 0); - /* EPIC won't generate INT unless Current Task Pri < 15 */ - epicCurTaskPrioSet(0); - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - register unsigned long temp; - - pci_readl (CONFIG_SYS_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp); - sync (); /* i'm not convinced this is needed, but dink source has it */ - temp &= 0xff; /*get vector */ - - /*TODO: handle them -... */ - epicEOI (); -} - -/****************************************************************************/ - -/* - * blank int handlers. - */ - -void -irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) -{ -} - -void irq_free_handler (int vec) -{ - -} - -/*TODO: some handlers for winbond and 87308 interrupts - and what about generic pci inteerupts? - vga? - */ - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} diff --git a/arch/powerpc/cpu/mpc824x/pci.c b/arch/powerpc/cpu/mpc824x/pci.c deleted file mode 100644 index 1257b086f2..0000000000 --- a/arch/powerpc/cpu/mpc824x/pci.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * arch/powerpc/kernel/mpc10x_common.c - * - * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge, - * Mem ctlr, EPIC, etc. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * Copyright 2001 MontaVista Software Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include -#include - -void pci_mpc824x_init (struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - CHRP_PCI_MEMORY_BUS, - CHRP_PCI_MEMORY_PHYS, - CHRP_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CHRP_PCI_MEM_BUS, - CHRP_PCI_MEM_PHYS, - CHRP_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CHRP_ISA_MEM_BUS, - CHRP_ISA_MEM_PHYS, - CHRP_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CHRP_PCI_IO_BUS, - CHRP_PCI_IO_PHYS, - CHRP_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CHRP_ISA_IO_BUS, - CHRP_ISA_IO_PHYS, - CHRP_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - CHRP_REG_ADDR, - CHRP_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} - -#endif diff --git a/arch/powerpc/cpu/mpc824x/speed.c b/arch/powerpc/cpu/mpc824x/speed.c deleted file mode 100644 index e6064a181c..0000000000 --- a/arch/powerpc/cpu/mpc824x/speed.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency on - * PCI_SYNC_IN . - * - * CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240 - * boards. It should be defined as the PCI to Memory Multiplier as - * documented in the MPC8240 Hardware Specs. - * - * Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER - * because they can determine it from the PCR. - * - * Gary Milliorn (who should know since - * he designed the Sandpoint) told us that the PCR is not in all revs - * of the MPC8240 CPU, so it's not guaranteeable and we cannot do - * away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether. - */ -/* ------------------------------------------------------------------------- */ - -/* This gives the PCI to Memory multiplier times 10 */ -/* The index is the value of PLL_CFG[0:4] */ -/* This is documented in the MPC8240/5 Hardware Specs */ - -short pll_pci_to_mem_multiplier[] = { -#if defined(CONFIG_MPC8240) - 30, 30, 10, 10, 20, 10, 0, 10, - 10, 0, 20, 0, 20, 0, 20, 0, - 30, 0, 15, 0, 20, 0, 20, 0, - 25, 0, 10, 0, 15, 15, 0, 0, -#elif defined(CONFIG_MPC8245) - 30, 30, 10, 10, 20, 10, 10, 10, - 10, 20, 20, 15, 20, 15, 20, 30, - 30, 40, 15, 40, 20, 25, 20, 40, - 25, 20, 10, 20, 15, 15, 15, 0, -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -}; - -#define CU824_PLL_STATE_REG 0xFE80002F -#define PCR 0x800000E2 - -/* ------------------------------------------------------------------------- */ - -/* compute the memory bus clock frequency */ -ulong get_bus_freq (ulong dummy) -{ - unsigned char pll_cfg; -#if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824) - return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER); -#elif defined(CONFIG_CU824) - pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG); - pll_cfg &= 0x1f; -#else - CONFIG_READ_BYTE(PCR, pll_cfg); - pll_cfg = (pll_cfg >> 3) & 0x1f; -#endif - return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10; -} - - -/* ------------------------------------------------------------------------- */ - -/* This gives the Memory to CPU Core multiplier times 10 */ -/* The index is the value of PLLRATIO in HID1 */ -/* This is documented in the MPC8240 Hardware Specs */ -/* This is not documented for MPC8245 ? FIXME */ -short pllratio_to_factor[] = { - 0, 0, 0, 10, 20, 20, 25, 45, - 30, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 10, 0, 0, 0, 45, - 30, 0, 40, 0, 0, 0, 35, 0, -}; - -/* compute the CPU and memory bus clock frequencies */ -int get_clocks (void) -{ - uint hid1 = mfspr(HID1); - hid1 = (hid1 >> (32-5)) & 0x1f; - gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5) - / 10; - gd->bus_clk = get_bus_freq(0); - return (0); -} diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S deleted file mode 100644 index 6f397a44c6..0000000000 --- a/arch/powerpc/cpu/mpc824x/start.S +++ /dev/null @@ -1,729 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000,2001,2002 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0x00000100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memorymap. - * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 - */ -#include -#include -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include -#include - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* FP, Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI ) - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) -#if defined(CONFIG_FADS) - GOT_ENTRY(environment) -#endif - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set FP, ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - addis r0,0,0x0000 /* lets make sure that r0 is really 0 */ - mtspr HID0, r0 /* disable I and D caches */ - - mfspr r3, ICR /* clear Interrupt Cause Register */ - - mfmsr r3 /* turn off address translation */ - addis r4,0,0xffff - ori r4,r4,0xffcf - and r3,r3,r4 - mtmsr r3 - isync - sync /* the MMU should be off... */ - - -in_flash: - /* - * Setup BATs - cannot be done in C since we don't have a stack yet - */ - bl setup_bats - - /* Enable MMU. - */ - mfmsr r3 - ori r3, r3, (MSR_IR | MSR_DR) - mtmsr r3 - - /* Enable and invalidate data cache. - */ - mfspr r3, HID0 - mr r2, r3 - ori r3, r3, HID0_DCE | HID0_DCI - ori r2, r2, HID0_DCE - sync - mtspr HID0, r3 - mtspr HID0, r2 - sync - - /* Allocate Initial RAM in data cache. - */ - lis r3, CONFIG_SYS_INIT_RAM_ADDR@h - ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l - li r2, 128 - mtctr r2 -1: - dcbz r0, r3 - addi r3, r3, 32 - bdnz 1b - - /* Lock way0 in data cache. - */ - mfspr r3, 1011 - lis r2, 0xffff - ori r2, r2, 0xff1f - and r3, r3, r2 - ori r3, r3, 0x0080 - sync - mtspr 1011, r3 - - /* - * Thisk the stack pointer *somewhere* sensible. Doesnt - * matter much where as we'll move it when we relocate - */ - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - bl board_init_f /* run 1st part of board init code (from Flash) */ - - /* NOTREACHED - board_init_f() does not return */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = EXC_OFF_ALIGN -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = EXC_OFF_PROGRAM -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - - STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException) - - STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException) - STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException) - - STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException) - STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException) - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - STD_EXCEPTION(0x1c00, ReservedC, UnknownException) - STD_EXCEPTION(0x1d00, ReservedD, UnknownException) - STD_EXCEPTION(0x1e00, ReservedE, UnknownException) - STD_EXCEPTION(0x1f00, ReservedF, UnknownException) - - STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException) - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) -#if 0 - andi. r23,r23,MSR_PR - mfspr r23,SPRG3 /* if from user, fix up tss.regs */ - beq 2f - addi r24,r1,STACK_FRAME_OVERHEAD - stw r24,PT_REGS(r23) -2: addi r2,r23,-TSS /* set r2 to current */ - tovirt(r2,r2,r23) -#endif - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ -#if 0 - addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */ - cmplw 0,r1,r2 - cmplw 1,r1,r24 - crand 1,1,4 - bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */ -#endif - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - ori r20,r20,0x30 /* enable IR, DR */ - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* Cache functions. -*/ - .globl icache_enable -icache_enable: - mfspr r5,HID0 /* turn on the I cache. */ - ori r5,r5,0x8800 /* Instruction cache only! */ - addis r6,0,0xFFFF - ori r6,r6,0xF7FF - and r6,r5,r6 /* clear the invalidate bit */ - sync - mtspr HID0,r5 - mtspr HID0,r6 - isync - sync - blr - - .globl icache_disable -icache_disable: - mfspr r5,HID0 - addis r6,0,0xFFFF - ori r6,r6,0x7FFF - and r5,r5,r6 - sync - mtspr HID0,r5 - isync - sync - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */ - andi. r3, r3, 1 - blr - - .globl dcache_enable -dcache_enable: - mfspr r5,HID0 /* turn on the D cache. */ - ori r5,r5,0x4400 /* Data cache only! */ - mfspr r4, PVR /* read PVR */ - srawi r3, r4, 16 /* shift off the least 16 bits */ - cmpi 0, 0, r3, 0xC /* Check for Max pvr */ - bne NotMax - ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */ -NotMax: - addis r6,0,0xFFFF - ori r6,r6,0xFBFF - and r6,r5,r6 /* clear the invalidate bit */ - sync - mtspr HID0,r5 - mtspr HID0,r6 - isync - sync - blr - - .globl dcache_disable -dcache_disable: - mfspr r5,HID0 - addis r6,0,0xFFFF - ori r6,r6,0xBFFF - and r5,r5,r6 - sync - mtspr HID0,r5 - isync - sync - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */ - andi. r3, r3, 1 - blr - - .globl dc_read -dc_read: -/*TODO : who uses this, what should it do? -*/ - blr - - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ -#ifdef CONFIG_SYS_RAMBOOT - lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_SDRAM_BASE@l -#else - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l -#endif - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* the the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -4: -/* Unlock the data cache and invalidate locked area */ - xor r0, r0, r0 - mtspr 1011, r0 - lis r4, CONFIG_SYS_INIT_RAM_ADDR@h - ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l - li r0, 128 - mtctr r0 -41: - dcbi r0, r4 - addi r4, r4, 32 - bdnz 41b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ - cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - blt 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr - - /* Setup the BAT registers. - */ -setup_bats: - lis r4, CONFIG_SYS_IBAT0L@h - ori r4, r4, CONFIG_SYS_IBAT0L@l - lis r3, CONFIG_SYS_IBAT0U@h - ori r3, r3, CONFIG_SYS_IBAT0U@l - mtspr IBAT0L, r4 - mtspr IBAT0U, r3 - isync - - lis r4, CONFIG_SYS_DBAT0L@h - ori r4, r4, CONFIG_SYS_DBAT0L@l - lis r3, CONFIG_SYS_DBAT0U@h - ori r3, r3, CONFIG_SYS_DBAT0U@l - mtspr DBAT0L, r4 - mtspr DBAT0U, r3 - isync - - lis r4, CONFIG_SYS_IBAT1L@h - ori r4, r4, CONFIG_SYS_IBAT1L@l - lis r3, CONFIG_SYS_IBAT1U@h - ori r3, r3, CONFIG_SYS_IBAT1U@l - mtspr IBAT1L, r4 - mtspr IBAT1U, r3 - isync - - lis r4, CONFIG_SYS_DBAT1L@h - ori r4, r4, CONFIG_SYS_DBAT1L@l - lis r3, CONFIG_SYS_DBAT1U@h - ori r3, r3, CONFIG_SYS_DBAT1U@l - mtspr DBAT1L, r4 - mtspr DBAT1U, r3 - isync - - lis r4, CONFIG_SYS_IBAT2L@h - ori r4, r4, CONFIG_SYS_IBAT2L@l - lis r3, CONFIG_SYS_IBAT2U@h - ori r3, r3, CONFIG_SYS_IBAT2U@l - mtspr IBAT2L, r4 - mtspr IBAT2U, r3 - isync - - lis r4, CONFIG_SYS_DBAT2L@h - ori r4, r4, CONFIG_SYS_DBAT2L@l - lis r3, CONFIG_SYS_DBAT2U@h - ori r3, r3, CONFIG_SYS_DBAT2U@l - mtspr DBAT2L, r4 - mtspr DBAT2U, r3 - isync - - lis r4, CONFIG_SYS_IBAT3L@h - ori r4, r4, CONFIG_SYS_IBAT3L@l - lis r3, CONFIG_SYS_IBAT3U@h - ori r3, r3, CONFIG_SYS_IBAT3U@l - mtspr IBAT3L, r4 - mtspr IBAT3U, r3 - isync - - lis r4, CONFIG_SYS_DBAT3L@h - ori r4, r4, CONFIG_SYS_DBAT3L@l - lis r3, CONFIG_SYS_DBAT3U@h - ori r3, r3, CONFIG_SYS_DBAT3U@l - mtspr DBAT3L, r4 - mtspr DBAT3U, r3 - isync - - /* Invalidate TLBs. - * -> for (val = 0; val < 0x20000; val+=0x1000) - * -> tlbie(val); - */ - lis r3, 0 - lis r5, 2 - -1: - tlbie r3 - addi r3, r3, 0x1000 - cmp 0, 0, r3, r5 - blt 1b - - blr diff --git a/arch/powerpc/cpu/mpc824x/traps.c b/arch/powerpc/cpu/mpc824x/traps.c deleted file mode 100644 index 6abf41d374..0000000000 --- a/arch/powerpc/cpu/mpc824x/traps.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x00400000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) -{ - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void DebugException(struct pt_regs *regs) -{ - - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds deleted file mode 100644 index 04aba84a0e..0000000000 --- a/arch/powerpc/cpu/mpc824x/u-boot.lds +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig new file mode 100644 index 0000000000..55941c830b --- /dev/null +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -0,0 +1,17 @@ +menu "mpc8260 CPU" + depends on MPC8260 + +config SYS_CPU + default "mpc8260" + +choice + prompt "Target select" + +config TARGET_KM82XX + bool "Support km82xx" + +endchoice + +source "board/keymile/km82xx/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc8260/Makefile b/arch/powerpc/cpu/mpc8260/Makefile index d87eff6414..83adc4c436 100644 --- a/arch/powerpc/cpu/mpc8260/Makefile +++ b/arch/powerpc/cpu/mpc8260/Makefile @@ -5,33 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o kgdb.o -COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ +extra-y = start.o +obj-y = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ interrupts.o ether_fcc.o i2c.o commproc.o \ - bedbug_603e.o pci.o spi.o - -COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o - -COBJS += $(COBJS-y) - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend + bedbug_603e.o pci.o spi.o kgdb.o -######################################################################### +obj-$(CONFIG_ETHER_ON_SCC) += ether_scc.o diff --git a/arch/powerpc/cpu/mpc8260/config.mk b/arch/powerpc/cpu/mpc8260/config.mk index 91b0497ccb..6a1b6e3eb4 100644 --- a/arch/powerpc/cpu/mpc8260/config.mk +++ b/arch/powerpc/cpu/mpc8260/config.mk @@ -5,7 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ +PLATFORM_CPPFLAGS += -DCONFIG_CPM2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c index f46a9c0a70..a9bb5adeb2 100644 --- a/arch/powerpc/cpu/mpc8260/cpu_init.c +++ b/arch/powerpc/cpu/mpc8260/cpu_init.c @@ -88,9 +88,7 @@ static void config_8260_ioports (volatile immap_t * immr) */ void cpu_init_f (volatile immap_t * immr) { -#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ uint sccr; -#endif #if defined(CONFIG_BOARD_GET_CPU_CLK_F) unsigned long cpu_clk; #endif @@ -141,13 +139,11 @@ void cpu_init_f (volatile immap_t * immr) /* initialize the PIT (4-42) */ immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; -#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ /* System clock control register (9-8) */ sccr = immr->im_clkrst.car_sccr & (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK); immr->im_clkrst.car_sccr = sccr | (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); -#endif /* !CONFIG_COGENT */ /* * Memory Controller: diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index d93a99109f..f9f15b59e5 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -645,32 +645,7 @@ eth_loopback_test (void) /* 28.9 - (1-2): ioports have been set up already */ -#if defined(CONFIG_HYMOD) - /* - * Attention: this is board-specific - * 0, FCC1 - * 1, FCC2 - * 2, FCC3 - */ -# define FCC_START_LOOP 0 -# define FCC_END_LOOP 2 - - /* - * Attention: this is board-specific - * - FCC1 Rx-CLK is CLK10 - * - FCC1 Tx-CLK is CLK11 - * - FCC2 Rx-CLK is CLK13 - * - FCC2 Tx-CLK is CLK14 - * - FCC3 Rx-CLK is CLK15 - * - FCC3 Tx-CLK is CLK16 - */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\ - CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\ - CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16; -#elif defined(CONFIG_SACSng) +#if defined(CONFIG_SACSng) /* * Attention: this is board-specific * 1, FCC2 diff --git a/arch/powerpc/cpu/mpc8260/interrupts.c b/arch/powerpc/cpu/mpc8260/interrupts.c index 30125a7a73..41d2c04c85 100644 --- a/arch/powerpc/cpu/mpc8260/interrupts.c +++ b/arch/powerpc/cpu/mpc8260/interrupts.c @@ -142,15 +142,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) immr->im_intctl.ic_sipnrh = 0xffffffff; immr->im_intctl.ic_sipnrl = 0xffffffff; -#ifdef CONFIG_HYMOD - /* - * ensure all external interrupt sources default to trigger on - * high-to-low transition (i.e. edge triggered active low) - */ - immr->im_intctl.ic_siexr = -1; -#endif - - return (0); + return 0; } /****************************************************************************/ diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S index 5a298f9d05..1432344bcc 100644 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ b/arch/powerpc/cpu/mpc8260/kgdb.S @@ -9,9 +9,6 @@ #include #include -#define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c index 49985c4f86..56f290ca92 100644 --- a/arch/powerpc/cpu/mpc8260/pci.c +++ b/arch/powerpc/cpu/mpc8260/pci.c @@ -6,7 +6,7 @@ * Vitaly Bordug * Added support for PCI bridge on MPC8272ADS * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -22,10 +22,6 @@ #include #endif -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 -DECLARE_GLOBAL_DATA_PTR; -#endif - /* * Local->PCI map (from CPU) controlled by * MPC826x master window @@ -235,38 +231,6 @@ void pci_mpc8250_init (struct pci_controller *hose) pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG, CONFIG_SYS_IMMR + PCI_CFG_DATA_REG); - /* - * Setting required to enable local bus for PCI (SIUMCR [LBPC]). - */ -#ifdef CONFIG_MPC8266ADS - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; -#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS -/* nothing to do for this board here */ -#elif defined CONFIG_MPC8272 - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_BBD & - ~SIUMCR_ESE & - ~SIUMCR_PBSE & - ~SIUMCR_CDIS & - ~SIUMCR_DPPC11 & - ~SIUMCR_L2CPC11 & - ~SIUMCR_LBPC11 & - ~SIUMCR_APPC11 & - ~SIUMCR_CS10PC11 & - ~SIUMCR_BCTLC11 & - ~SIUMCR_MMR11) - | SIUMCR_DPPC11 - | SIUMCR_L2CPC01 - | SIUMCR_LBPC00 - | SIUMCR_APPC10 - | SIUMCR_CS10PC00 - | SIUMCR_BCTLC00 - | SIUMCR_MMR11; -#elif defined(CONFIG_TQM8272) -/* nothing to do for this Board here */ -#else /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), * and local bus for PCI (SIUMCR [LBPC]). @@ -278,7 +242,6 @@ void pci_mpc8250_init (struct pci_controller *hose) SIUMCR_LBPC01 | SIUMCR_CS10PC01 | SIUMCR_APPC10; -#endif /* Make PCI lowest priority */ /* Each 4 bits is a device bus request and the MS 4bits @@ -308,24 +271,11 @@ void pci_mpc8250_init (struct pci_controller *hose) immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK; - immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; -#endif - /* Release PCI RST (by default the PCI RST signal is held low) */ immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); /* give it some time */ { -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - /* Give the PCI cards more time to initialize before query - This might be good for other boards also - */ - int i; - - for (i = 0; i < 1000; ++i) -#endif udelay (1000); } @@ -362,11 +312,7 @@ void pci_mpc8250_init (struct pci_controller *hose) immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ /* See above for description - puts PCI request as highest priority */ -#ifdef CONFIG_MPC8272 - immap->im_siu_conf.sc_ppc_alrh = 0x01236745; -#else immap->im_siu_conf.sc_ppc_alrh = 0x03124567; -#endif /* Park the bus on the PCI */ immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; @@ -392,30 +338,16 @@ void pci_mpc8250_init (struct pci_controller *hose) hose->last_busno = 0xff; /* System memory space */ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 - pci_set_region (hose->regions + 0, - PCI_SLV_MEM_BUS, - PCI_SLV_MEM_LOCAL, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); -#else pci_set_region (hose->regions + 0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE, 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); -#endif /* PCI memory space */ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - pci_set_region (hose->regions + 1, - PCI_MSTR_MEMIO_BUS, - PCI_MSTR_MEMIO_LOCAL, - PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); -#else pci_set_region (hose->regions + 1, PCI_MSTR_MEM_BUS, PCI_MSTR_MEM_LOCAL, PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); -#endif /* PCI I/O space */ pci_set_region (hose->regions + 2, diff --git a/arch/powerpc/cpu/mpc8260/speed.h b/arch/powerpc/cpu/mpc8260/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/arch/powerpc/cpu/mpc8260/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 1269291c45..d255bdeeb8 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -14,9 +14,6 @@ #include #include -#define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include @@ -51,9 +48,6 @@ GOT_ENTRY(__init_end) GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) -#if defined(CONFIG_HYMOD) - GOT_ENTRY(environment) -#endif END_GOT /* @@ -140,29 +134,8 @@ _hrcw_table: .globl _start _start: -#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR) - lis r3, CONFIG_SYS_DEFAULT_IMMR@h - nop - lwz r4, 0(r3) - nop - rlwinm r4, r4, 0, 8, 5 - nop - oris r4, r4, 0x0200 - nop - stw r4, 0(r3) - nop -#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */ - mfmsr r5 /* save msr contents */ -#if defined(CONFIG_COGENT) - /* this is what the cogent EPROM does */ - li r0, 0 - mtmsr r0 - isync - bl cogent_init_8260 -#endif /* CONFIG_COGENT */ - #if defined(CONFIG_SYS_DEFAULT_IMMR) lis r3, CONFIG_SYS_IMMR@h ori r3, r3, CONFIG_SYS_IMMR@l @@ -398,57 +371,6 @@ int_return: SYNC rfi -#if defined(CONFIG_COGENT) - -/* - * This code initialises the MPC8260 processor core - * (conforms to PowerPC 603e spec) - */ - - .globl cogent_init_8260 -cogent_init_8260: - - /* Taken from page 14 of CMA282 manual */ - /*--------------------------------------------------------------*/ - - lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h - lis r3, CONFIG_SYS_IMMR@h - stw r3, IM_IMMR@l(r4) - lwz r3, IM_IMMR@l(r4) - stw r3, 0(r0) - lis r3, CONFIG_SYS_SYPCR@h - ori r3, r3, CONFIG_SYS_SYPCR@l - stw r3, IM_SYPCR@l(r4) - lwz r3, IM_SYPCR@l(r4) - stw r3, 4(r0) - lis r3, CONFIG_SYS_SCCR@h - ori r3, r3, CONFIG_SYS_SCCR@l - stw r3, IM_SCCR@l(r4) - lwz r3, IM_SCCR@l(r4) - stw r3, 8(r0) - - /* the rest of this was disassembled from the */ - /* EPROM code that came with my CMA282 CPU module */ - /*--------------------------------------------------------------*/ - - lis r1, 0x1234 - ori r1, r1, 0x5678 - stw r1, 0x20(r0) - lwz r1, 0x20(r0) - stw r1, 0x24(r0) - lwz r1, 0x24(r0) - lis r3, 0x0e80 - ori r3, r3, 0 - stw r1, 4(r3) - lwz r1, 4(r3) - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -#endif /* CONFIG_COGENT */ - /* * This code initialises the MPC8260 processor core * (conforms to PowerPC 603e spec) @@ -475,11 +397,9 @@ init_8260_core: /*--------------------------------------------------------------*/ lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h -#if !defined(CONFIG_COGENT) lis r4, CONFIG_SYS_SYPCR@h ori r4, r4, CONFIG_SYS_SYPCR@l stw r4, IM_SYPCR@l(r3) -#endif /* !CONFIG_COGENT */ #if defined(CONFIG_WATCHDOG) li r4, 21868 /* = 0x556c */ sth r4, IM_SWSR@l(r3) @@ -894,18 +814,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else lwz r4,GOT(__bss_end) -#endif cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig new file mode 100644 index 0000000000..4d6cb0964b --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -0,0 +1,88 @@ +menu "mpc83xx CPU" + depends on MPC83xx + +config SYS_CPU + default "mpc83xx" + +choice + prompt "Target select" + +config TARGET_MPC8308_P1M + bool "Support mpc8308_p1m" + +config TARGET_SBC8349 + bool "Support sbc8349" + +config TARGET_VE8313 + bool "Support ve8313" + +config TARGET_VME8349 + bool "Support vme8349" + +config TARGET_MPC8308RDB + bool "Support MPC8308RDB" + +config TARGET_MPC8313ERDB + bool "Support MPC8313ERDB" + select SUPPORT_SPL + +config TARGET_MPC8315ERDB + bool "Support MPC8315ERDB" + +config TARGET_MPC8323ERDB + bool "Support MPC8323ERDB" + +config TARGET_MPC832XEMDS + bool "Support MPC832XEMDS" + +config TARGET_MPC8349EMDS + bool "Support MPC8349EMDS" + +config TARGET_MPC8349ITX + bool "Support MPC8349ITX" + +config TARGET_MPC837XEMDS + bool "Support MPC837XEMDS" + +config TARGET_MPC837XERDB + bool "Support MPC837XERDB" + +config TARGET_IDS8313 + bool "Support ids8313" + +config TARGET_KM8360 + bool "Support km8360" + +config TARGET_SUVD3 + bool "Support suvd3" + +config TARGET_TUXX1 + bool "Support tuxx1" + +config TARGET_TQM834X + bool "Support TQM834x" + +config TARGET_HRCON + bool "Support hrcon" + +endchoice + +source "board/esd/vme8349/Kconfig" +source "board/freescale/mpc8308rdb/Kconfig" +source "board/freescale/mpc8313erdb/Kconfig" +source "board/freescale/mpc8315erdb/Kconfig" +source "board/freescale/mpc8323erdb/Kconfig" +source "board/freescale/mpc832xemds/Kconfig" +source "board/freescale/mpc8349emds/Kconfig" +source "board/freescale/mpc8349itx/Kconfig" +source "board/freescale/mpc837xemds/Kconfig" +source "board/freescale/mpc837xerdb/Kconfig" +source "board/ids/ids8313/Kconfig" +source "board/keymile/km83xx/Kconfig" +source "board/mpc8308_p1m/Kconfig" +source "board/sbc8349/Kconfig" +source "board/tqc/tqm834x/Kconfig" +source "board/ve8313/Kconfig" +source "board/gdsys/mpc8308/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 6341cd4fff..cf9116274d 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -19,62 +15,32 @@ MINIMAL=y endif endif -START = start.o +extra-y = start.o ifdef MINIMAL -COBJS-y += spl_minimal.o +obj-y += spl_minimal.o else -COBJS-y += traps.o -COBJS-y += cpu.o -COBJS-y += cpu_init.o -COBJS-y += speed.o -COBJS-y += interrupts.o -COBJS-y += ecc.o -COBJS-$(CONFIG_QE) += qe_io.o -COBJS-$(CONFIG_FSL_SERDES) += serdes.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_PCIE) += pcie.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +obj-y += traps.o +obj-y += cpu.o +obj-y += cpu_init.o +obj-y += speed.o +obj-y += interrupts.o +obj-y += ecc.o +obj-$(CONFIG_QE) += qe_io.o +obj-$(CONFIG_FSL_SERDES) += serdes.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_PCIE) += pcie.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o # Stub implementations of cache management functions for USB -COBJS-y += cache.o +obj-y += cache.o -ifdef CONFIG_FSL_DDR2 -COBJS_LN-$(CONFIG_MPC8349) += ddr-gen2.o -else -COBJS-y += spd_sdram.o +ifndef CONFIG_SYS_FSL_DDRC_GEN2 +obj-y += spd_sdram.o endif -COBJS-$(CONFIG_FSL_DDR2) += law.o +obj-$(CONFIG_SYS_FSL_DDR2) += law.o endif # not minimal - -COBJS := $(COBJS-y) -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(obj)ddr-gen1.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c - -$(obj)ddr-gen2.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c - -$(obj)ddr-gen3.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/powerpc/cpu/mpc83xx/config.mk b/arch/powerpc/cpu/mpc83xx/config.mk index c16a00376f..0c083504ed 100644 --- a/arch/powerpc/cpu/mpc83xx/config.mk +++ b/arch/powerpc/cpu/mpc83xx/config.mk @@ -4,7 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \ - -ffixed-r2 -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index e275fcea41..38093097e4 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -19,8 +19,8 @@ #include #include #include -#ifdef CONFIG_BOOTCOUNT_LIMIT -#include +#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x) +#include #include #endif diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index d568f889d2..00572de121 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -315,7 +315,7 @@ void cpu_init_f (volatile immap_t * im) #endif #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x) uint32_t temp; - struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; /* Configure interface. */ setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); @@ -425,15 +425,15 @@ static int print_83xx_arb_event(int force) }; int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT) - >> AEATR_EVENT_SHIFT; + >> AEATR_EVENT_SHIFT; int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID) - >> AEATR_MSTR_ID_SHIFT; + >> AEATR_MSTR_ID_SHIFT; int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST) - >> AEATR_TBST_SHIFT; + >> AEATR_TBST_SHIFT; int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE) - >> AEATR_TSIZE_SHIFT; + >> AEATR_TSIZE_SHIFT; int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE) - >> AEATR_TTYPE_SHIFT; + >> AEATR_TTYPE_SHIFT; if (!force && !gd->arch.arbiter_event_address) return 0; diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 120b37ba63..985a024425 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -15,8 +15,8 @@ void ecc_print_status(void) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#ifdef CONFIG_FSL_DDR2 - ccsr_ddr_t *ddr = &immap->ddr; +#ifdef CONFIG_SYS_FSL_DDR2 + struct ccsr_ddr __iomem *ddr = &immap->ddr; #else ddr83xx_t *ddr = &immap->ddr; #endif @@ -99,8 +99,8 @@ void ecc_print_status(void) int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#ifdef CONFIG_FSL_DDR2 - ccsr_ddr_t *ddr = &immap->ddr; +#ifdef CONFIG_SYS_FSL_DDR2 + struct ccsr_ddr __iomem *ddr = &immap->ddr; #else ddr83xx_t *ddr = &immap->ddr; #endif diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index cce7d6b265..f249a585ed 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -17,8 +17,8 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ - (defined(CONFIG_QE)) -#include + (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) +#include void fdt_fixup_muram (void *blob) { @@ -124,7 +124,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -#if defined(CONFIG_BOOTCOUNT_LIMIT) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && \ + (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) fdt_fixup_muram (blob); #endif } diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index e073c904ef..30606fbe58 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -67,7 +67,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) pci_ctrl->pibar1 = 0; pci_ctrl->piebar1 = 0; pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1)); + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1)); i = hose->region_count++; hose->regions[i].bus_start = 0; @@ -79,7 +79,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) hose->last_busno = 0xff; pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80, - CONFIG_SYS_IMMR + 0x8304 + bus * 0x80); + CONFIG_SYS_IMMR + 0x8304 + bus * 0x80); pci_register_hose(hose); diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 09970b0589..28c25e5feb 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -299,6 +299,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) printf("PCIE%d: ", bus); +#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ +#define PCI_LTSSM_L0 0x16 /* L0 state */ reg16 = in_le16(hose_cfg_base + PCI_LTSSM); if (reg16 >= PCI_LTSSM_L0) printf("link\n"); diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 3580706105..f62e1b79d3 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -8,7 +8,7 @@ * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index b4fafe65ef..9bd86d82d6 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -20,7 +20,6 @@ #include #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include @@ -120,6 +119,11 @@ disable_addr_trans: mtspr SRR1, r3 rfi + .globl get_svr +get_svr: + mfspr r3, SVR + blr + .globl get_pvr get_pvr: mfspr r3, PVR @@ -279,6 +283,7 @@ in_flash: bl cpu_init_f /* run 1st part of board init code (in Flash)*/ + li r3, 0 /* clear boot_flag for calling board_init_f */ bl board_init_f /* NOTREACHED - board_init_f() does not return */ @@ -954,18 +959,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else lwz r4,GOT(__bss_end) -#endif cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig new file mode 100644 index 0000000000..adb5bd378c --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -0,0 +1,198 @@ +menu "mpc85xx CPU" + depends on MPC85xx + +config SYS_CPU + default "mpc85xx" + +choice + prompt "Target select" + +config TARGET_SBC8548 + bool "Support sbc8548" + +config TARGET_SOCRATES + bool "Support socrates" + +config TARGET_B4860QDS + bool "Support B4860QDS" + select SUPPORT_SPL + +config TARGET_BSC9131RDB + bool "Support BSC9131RDB" + select SUPPORT_SPL + +config TARGET_BSC9132QDS + bool "Support BSC9132QDS" + select SUPPORT_SPL + +config TARGET_C29XPCIE + bool "Support C29XPCIE" + select SUPPORT_SPL + select SUPPORT_TPL + +config TARGET_P3041DS + bool "Support P3041DS" + +config TARGET_P4080DS + bool "Support P4080DS" + +config TARGET_P5020DS + bool "Support P5020DS" + +config TARGET_P5040DS + bool "Support P5040DS" + +config TARGET_MPC8536DS + bool "Support MPC8536DS" + +config TARGET_MPC8540ADS + bool "Support MPC8540ADS" + +config TARGET_MPC8541CDS + bool "Support MPC8541CDS" + +config TARGET_MPC8544DS + bool "Support MPC8544DS" + +config TARGET_MPC8548CDS + bool "Support MPC8548CDS" + +config TARGET_MPC8555CDS + bool "Support MPC8555CDS" + +config TARGET_MPC8560ADS + bool "Support MPC8560ADS" + +config TARGET_MPC8568MDS + bool "Support MPC8568MDS" + +config TARGET_MPC8569MDS + bool "Support MPC8569MDS" + +config TARGET_MPC8572DS + bool "Support MPC8572DS" + +config TARGET_P1010RDB + bool "Support P1010RDB" + select SUPPORT_SPL + select SUPPORT_TPL + +config TARGET_P1022DS + bool "Support P1022DS" + select SUPPORT_SPL + select SUPPORT_TPL + +config TARGET_P1023RDB + bool "Support P1023RDB" + +config TARGET_P1_P2_RDB_PC + bool "Support p1_p2_rdb_pc" + select SUPPORT_SPL + select SUPPORT_TPL + +config TARGET_P1_TWR + bool "Support p1_twr" + +config TARGET_P2041RDB + bool "Support P2041RDB" + +config TARGET_QEMU_PPCE500 + bool "Support qemu-ppce500" + +config TARGET_T102XQDS + bool "Support T102xQDS" + select SUPPORT_SPL + +config TARGET_T102XRDB + bool "Support T102xRDB" + select SUPPORT_SPL + +config TARGET_T1040QDS + bool "Support T1040QDS" + +config TARGET_T104XRDB + bool "Support T104xRDB" + select SUPPORT_SPL + +config TARGET_T208XQDS + bool "Support T208xQDS" + select SUPPORT_SPL + +config TARGET_T208XRDB + bool "Support T208xRDB" + select SUPPORT_SPL + +config TARGET_T4240EMU + bool "Support T4240EMU" + +config TARGET_T4240QDS + bool "Support T4240QDS" + select SUPPORT_SPL + +config TARGET_T4240RDB + bool "Support T4240RDB" + +config TARGET_CONTROLCENTERD + bool "Support controlcenterd" + +config TARGET_KMP204X + bool "Support kmp204x" + +config TARGET_STXGP3 + bool "Support stxgp3" + +config TARGET_STXSSA + bool "Support stxssa" + +config TARGET_XPEDITE520X + bool "Support xpedite520x" + +config TARGET_XPEDITE537X + bool "Support xpedite537x" + +config TARGET_XPEDITE550X + bool "Support xpedite550x" + +endchoice + +source "board/freescale/b4860qds/Kconfig" +source "board/freescale/bsc9131rdb/Kconfig" +source "board/freescale/bsc9132qds/Kconfig" +source "board/freescale/c29xpcie/Kconfig" +source "board/freescale/corenet_ds/Kconfig" +source "board/freescale/mpc8536ds/Kconfig" +source "board/freescale/mpc8540ads/Kconfig" +source "board/freescale/mpc8541cds/Kconfig" +source "board/freescale/mpc8544ds/Kconfig" +source "board/freescale/mpc8548cds/Kconfig" +source "board/freescale/mpc8555cds/Kconfig" +source "board/freescale/mpc8560ads/Kconfig" +source "board/freescale/mpc8568mds/Kconfig" +source "board/freescale/mpc8569mds/Kconfig" +source "board/freescale/mpc8572ds/Kconfig" +source "board/freescale/p1010rdb/Kconfig" +source "board/freescale/p1022ds/Kconfig" +source "board/freescale/p1023rdb/Kconfig" +source "board/freescale/p1_p2_rdb_pc/Kconfig" +source "board/freescale/p1_twr/Kconfig" +source "board/freescale/p2041rdb/Kconfig" +source "board/freescale/qemu-ppce500/Kconfig" +source "board/freescale/t102xqds/Kconfig" +source "board/freescale/t102xrdb/Kconfig" +source "board/freescale/t1040qds/Kconfig" +source "board/freescale/t104xrdb/Kconfig" +source "board/freescale/t208xqds/Kconfig" +source "board/freescale/t208xrdb/Kconfig" +source "board/freescale/t4qds/Kconfig" +source "board/freescale/t4rdb/Kconfig" +source "board/gdsys/p1022/Kconfig" +source "board/keymile/kmp204x/Kconfig" +source "board/sbc8548/Kconfig" +source "board/socrates/Kconfig" +source "board/stx/stxgp3/Kconfig" +source "board/stx/stxssa/Kconfig" +source "board/xes/xpedite520x/Kconfig" +source "board/xes/xpedite537x/Kconfig" +source "board/xes/xpedite550x/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 0d1e8f1f0a..b93158b9ed 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -8,10 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -20,147 +16,105 @@ MINIMAL=y endif endif -START = start.o resetvec.o +extra-y = start.o resetvec.o ifdef MINIMAL -COBJS-y += cpu_init_early.o tlb.o spl_minimal.o +obj-y += cpu_init_early.o tlb.o spl_minimal.o else -SOBJS-$(CONFIG_MP) += release.o -SOBJS = $(SOBJS-y) - -COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o -COBJS-$(CONFIG_CPM2) += commproc.o - -# supports ddr1 -COBJS-$(CONFIG_MPC8540) += ddr-gen1.o -COBJS-$(CONFIG_MPC8560) += ddr-gen1.o -COBJS-$(CONFIG_MPC8541) += ddr-gen1.o -COBJS-$(CONFIG_MPC8555) += ddr-gen1.o - -# supports ddr1/2 -COBJS-$(CONFIG_MPC8548) += ddr-gen2.o -COBJS-$(CONFIG_MPC8568) += ddr-gen2.o -COBJS-$(CONFIG_MPC8544) += ddr-gen2.o - -# supports ddr1/2/3 -COBJS-$(CONFIG_MPC8572) += ddr-gen3.o -COBJS-$(CONFIG_MPC8536) += ddr-gen3.o -COBJS-$(CONFIG_MPC8569) += ddr-gen3.o -COBJS-$(CONFIG_P1010) += ddr-gen3.o -COBJS-$(CONFIG_P1011) += ddr-gen3.o -COBJS-$(CONFIG_P1012) += ddr-gen3.o -COBJS-$(CONFIG_P1013) += ddr-gen3.o -COBJS-$(CONFIG_P1014) += ddr-gen3.o -COBJS-$(CONFIG_P1020) += ddr-gen3.o -COBJS-$(CONFIG_P1021) += ddr-gen3.o -COBJS-$(CONFIG_P1022) += ddr-gen3.o -COBJS-$(CONFIG_P1023) += ddr-gen3.o -COBJS-$(CONFIG_P1024) += ddr-gen3.o -COBJS-$(CONFIG_P1025) += ddr-gen3.o -COBJS-$(CONFIG_P2010) += ddr-gen3.o -COBJS-$(CONFIG_P2020) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o -COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o -COBJS-$(CONFIG_PPC_T4160) += ddr-gen3.o -COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o -COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o -COBJS-$(CONFIG_BSC9131) += ddr-gen3.o -COBJS-$(CONFIG_BSC9132) += ddr-gen3.o -COBJS-$(CONFIG_PPC_T1040) += ddr-gen3.o - -COBJS-$(CONFIG_CPM2) += ether_fcc.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS-$(CONFIG_FSL_CORENET) += liodn.o -COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o +obj-$(CONFIG_MP) += release.o + +obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o +obj-$(CONFIG_CPM2) += commproc.o + +obj-$(CONFIG_CPM2) += ether_fcc.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_FSL_CORENET) += liodn.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o -COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o -COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o -COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o -COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o -COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o -COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o -COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o -COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o -COBJS-$(CONFIG_PPC_T1040) += t1040_ids.o - -COBJS-$(CONFIG_QE) += qe_io.o -COBJS-$(CONFIG_CPM2) += serial_scc.o -COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o -COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o +obj-$(CONFIG_PPC_P2041) += p2041_ids.o +obj-$(CONFIG_PPC_P3041) += p3041_ids.o +obj-$(CONFIG_PPC_P4080) += p4080_ids.o +obj-$(CONFIG_PPC_P5020) += p5020_ids.o +obj-$(CONFIG_PPC_P5040) += p5040_ids.o +obj-$(CONFIG_PPC_T4240) += t4240_ids.o +obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_PPC_T4080) += t4240_ids.o +obj-$(CONFIG_PPC_B4420) += b4860_ids.o +obj-$(CONFIG_PPC_B4860) += b4860_ids.o +obj-$(CONFIG_PPC_T1040) += t1040_ids.o +obj-$(CONFIG_PPC_T1042) += t1040_ids.o +obj-$(CONFIG_PPC_T1020) += t1040_ids.o +obj-$(CONFIG_PPC_T1022) += t1040_ids.o +obj-$(CONFIG_PPC_T1023) += t1024_ids.o +obj-$(CONFIG_PPC_T1024) += t1024_ids.o +obj-$(CONFIG_PPC_T2080) += t2080_ids.o +obj-$(CONFIG_PPC_T2081) += t2080_ids.o + + +obj-$(CONFIG_QE) += qe_io.o +obj-$(CONFIG_CPM2) += serial_scc.o +obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o +obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o # SoC specific SERDES support -COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o -COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o -COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o -COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o -COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o -COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o -COBJS-$(CONFIG_P1010) += p1010_serdes.o -COBJS-$(CONFIG_P1011) += p1021_serdes.o -COBJS-$(CONFIG_P1012) += p1021_serdes.o -COBJS-$(CONFIG_P1013) += p1022_serdes.o -COBJS-$(CONFIG_P1014) += p1010_serdes.o -COBJS-$(CONFIG_P1017) += p1023_serdes.o -COBJS-$(CONFIG_P1020) += p1021_serdes.o -COBJS-$(CONFIG_P1021) += p1021_serdes.o -COBJS-$(CONFIG_P1022) += p1022_serdes.o -COBJS-$(CONFIG_P1023) += p1023_serdes.o -COBJS-$(CONFIG_P1024) += p1021_serdes.o -COBJS-$(CONFIG_P1025) += p1021_serdes.o -COBJS-$(CONFIG_P2010) += p2020_serdes.o -COBJS-$(CONFIG_P2020) += p2020_serdes.o -COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o -COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o -COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o -COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o -COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o -COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o -COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o -COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o -COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o -COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o -COBJS-$(CONFIG_PPC_T1040) += t1040_serdes.o - -COBJS-y += cpu.o -COBJS-y += cpu_init.o -COBJS-y += cpu_init_early.o -COBJS-y += interrupts.o -COBJS-y += speed.o -COBJS-y += tlb.o -COBJS-y += traps.o +obj-$(CONFIG_PPC_C29X) += c29x_serdes.o +obj-$(CONFIG_MPC8536) += mpc8536_serdes.o +obj-$(CONFIG_MPC8544) += mpc8544_serdes.o +obj-$(CONFIG_MPC8548) += mpc8548_serdes.o +obj-$(CONFIG_MPC8568) += mpc8568_serdes.o +obj-$(CONFIG_MPC8569) += mpc8569_serdes.o +obj-$(CONFIG_MPC8572) += mpc8572_serdes.o +obj-$(CONFIG_P1010) += p1010_serdes.o +obj-$(CONFIG_P1011) += p1021_serdes.o +obj-$(CONFIG_P1012) += p1021_serdes.o +obj-$(CONFIG_P1013) += p1022_serdes.o +obj-$(CONFIG_P1014) += p1010_serdes.o +obj-$(CONFIG_P1017) += p1023_serdes.o +obj-$(CONFIG_P1020) += p1021_serdes.o +obj-$(CONFIG_P1021) += p1021_serdes.o +obj-$(CONFIG_P1022) += p1022_serdes.o +obj-$(CONFIG_P1023) += p1023_serdes.o +obj-$(CONFIG_P1024) += p1021_serdes.o +obj-$(CONFIG_P1025) += p1021_serdes.o +obj-$(CONFIG_P2010) += p2020_serdes.o +obj-$(CONFIG_P2020) += p2020_serdes.o +obj-$(CONFIG_PPC_P2041) += p2041_serdes.o +obj-$(CONFIG_PPC_P3041) += p3041_serdes.o +obj-$(CONFIG_PPC_P4080) += p4080_serdes.o +obj-$(CONFIG_PPC_P5020) += p5020_serdes.o +obj-$(CONFIG_PPC_P5040) += p5040_serdes.o +obj-$(CONFIG_PPC_T4240) += t4240_serdes.o +obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_PPC_T4080) += t4240_serdes.o +obj-$(CONFIG_PPC_B4420) += b4860_serdes.o +obj-$(CONFIG_PPC_B4860) += b4860_serdes.o +obj-$(CONFIG_BSC9132) += bsc9132_serdes.o +obj-$(CONFIG_PPC_T1040) += t1040_serdes.o +obj-$(CONFIG_PPC_T1042) += t1040_serdes.o +obj-$(CONFIG_PPC_T1020) += t1040_serdes.o +obj-$(CONFIG_PPC_T1022) += t1040_serdes.o +obj-$(CONFIG_PPC_T1023) += t1024_serdes.o +obj-$(CONFIG_PPC_T1024) += t1024_serdes.o +obj-$(CONFIG_PPC_T2080) += t2080_serdes.o +obj-$(CONFIG_PPC_T2081) += t2080_serdes.o + +obj-y += cpu.o +obj-y += cpu_init.o +obj-y += cpu_init_early.o +obj-y += interrupts.o +ifneq ($(CONFIG_QEMU_E500),y) +obj-y += speed.o +endif +obj-y += tlb.o +obj-y += traps.o # Stub implementations of cache management functions for USB -COBJS-y += cache.o +obj-y += cache.o endif # not minimal - -COBJS = $(COBJS-y) - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 53c6a7faf9..fd7f5fa7e1 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -41,8 +41,8 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { #ifdef CONFIG_SYS_SRIO struct srio_liodn_id_table srio_liodn_tbl[] = { - SET_SRIO_LIODN_1(1, 307), - SET_SRIO_LIODN_1(2, 387), + SET_SRIO_LIODN_BASE(1, 307), + SET_SRIO_LIODN_BASE(2, 387), }; int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); #endif @@ -55,12 +55,12 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 552), - SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(1, "fsl-usb2-dr", 553), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), #ifndef CONFIG_PPC_B4420 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), @@ -112,10 +112,10 @@ int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); #ifdef CONFIG_SYS_DPAA_RMAN struct liodn_id_table rman_liodn_tbl[] = { /* Set RMan block 0-3 liodn offset */ - SET_RMAN_LIODN(0, 678), - SET_RMAN_LIODN(1, 679), - SET_RMAN_LIODN(2, 680), - SET_RMAN_LIODN(3, 681), + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), }; int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); #endif diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 6ff6a70294..63172def68 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -18,12 +18,36 @@ struct serdes_config { #ifdef CONFIG_PPC_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ + {0x01, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x02, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x04, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x05, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x06, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x07, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x08, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x09, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0A, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0B, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0C, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, @@ -32,6 +56,9 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2F, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x30, {AURORA, AURORA, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, CPRI4, CPRI3, CPRI2, CPRI1}}, @@ -44,18 +71,38 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x34, {AURORA, AURORA, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x39, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3A, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3C, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3D, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x5C, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x5D, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, {} }; static struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ + {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1} }, {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, SRIO1, SRIO1}}, {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, SRIO1, SRIO1}}, + {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, SRIO1, SRIO1} }, {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, SRIO1, SRIO1}}, @@ -63,6 +110,9 @@ static struct serdes_config serdes2_cfg_tbl[] = { SRIO2, SRIO2, AURORA, AURORA, SRIO1, SRIO1}}, + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1} }, {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, SRIO1, SRIO1, SRIO1, SRIO1}}, @@ -75,18 +125,30 @@ static struct serdes_config serdes2_cfg_tbl[] = { {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x79, {SRIO2, SRIO2, SRIO2, SRIO2, + SRIO1, SRIO1, SRIO1, SRIO1} }, {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, XFI_FM1_MAC9, XFI_FM1_MAC10}}, {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, AURORA, AURORA, XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, @@ -101,6 +163,9 @@ static struct serdes_config serdes2_cfg_tbl[] = { SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1_MAC10, XAUI_FM1_MAC10, XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XFI_FM1_MAC9, XFI_FM1_MAC10}}, @@ -123,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, NONE, NONE} }, {0x0F, {NONE, NONE, CPRI6, CPRI5, CPRI4, CPRI3, NONE, NONE} }, + {0x17, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x18, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, {0x1B, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x1D, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, {0x1E, {NONE, NONE, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x21, {NONE, NONE, AURORA, AURORA, @@ -138,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = { {} }; static struct serdes_config serdes2_cfg_tbl[] = { + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, + {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x99, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x9A, {PCIE1, PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1, + NONE, NONE, NONE, NONE} }, {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE} }, {} diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c new file mode 100644 index 0000000000..51972cb7cb --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -0,0 +1,62 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS1_MAX_LANES]; +}; + +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {2, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {3, {PCIE1, PCIE1, NONE, NONE} }, + {4, {PCIE1, PCIE1, NONE, NONE} }, + {5, {PCIE1, NONE, NONE, NONE} }, + {6, {PCIE1, NONE, NONE, NONE} }, + {} +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + return (1 << device) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + const struct serdes_config *ptr; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + ptr = &serdes1_cfg_tbl[srds_cfg]; + if (!ptr->protocol) + return; + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = ptr->lanes[lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 5cd02ccde6..2d5ddf012b 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,7 +7,9 @@ #include #include #include +#include #include +#include #include "fsl_corenet_serdes.h" #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 @@ -112,6 +114,21 @@ static void check_erratum_a4580(uint32_t svr) } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +/* + * This workaround can be implemented in PBI, or by u-boot. + */ +static void check_erratum_a007212(void) +{ + u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + + if (in_be32(plldgdcr) & 0x1fe) { + /* check if PLL ratio is set by workaround */ + puts("Work-around for Erratum A007212 enabled\n"); + } +} +#endif + static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 @@ -155,7 +172,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum CPU-A003999 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) - puts("Work-around for Erratum DDR-A003473 enabled\n"); + puts("Work-around for Erratum DDR-A003474 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); @@ -215,6 +232,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) puts("Work-around for Erratum NMG ETSEC129 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004508 + puts("Work-around for Erratum A004508 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 puts("Work-around for Erratum A004510 enabled\n"); #endif @@ -228,6 +248,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A005871 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006475 + if (SVR_MAJ(get_svr()) == 1) + puts("Work-around for Erratum A006475 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006384 + if (SVR_MAJ(get_svr()) == 1) + puts("Work-around for Erratum A006384 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 /* This work-around is implemented in PBI, so just check for it */ check_erratum_a4849(svr); @@ -242,9 +270,59 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 puts("Work-around for Erratum USB14 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 + if (has_erratum_a007186()) + puts("Work-around for Erratum A007186 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) + puts("Work-around for Erratum A006379 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A003571 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + puts("Work-around for Erratum A-005812 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + puts("Work-around for Erratum A005125 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007075 + if (has_erratum_a007075()) + puts("Work-around for Erratum A007075 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007798 + if (has_erratum_a007798()) + puts("Work-around for Erratum A007798 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 + if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || + (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) + puts("Work-around for Erratum I2C-A004447 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + puts("Work-around for Erratum A006261 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + check_erratum_a007212(); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + puts("Work-around for Erratum A-005434 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \ + defined(CONFIG_A008044_WORKAROUND) + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A-008044 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) + puts("Work-around for Erratum XFI on B4860QDS enabled\n"); +#endif + return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk index 9eef539e5e..72c964cd15 100644 --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -5,13 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string +PLATFORM_CPPFLAGS += -Wa,-me500 -msoft-float -mno-string # -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; # see "[PATCH,rs6000] make -mno-spe work as expected" on # http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html -PF_CPPFLAGS_SPE := $(call cc-option,-mspe=yes) \ +PLATFORM_CPPFLAGS += $(call cc-option,-mspe=yes) \ $(call cc-option,-mno-spe) -PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_SPE) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 91ac4ee617..3d6ec843df 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -17,12 +17,12 @@ #include #include #include -#include +#include #include #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -44,10 +44,10 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if (defined(CONFIG_DDR_CLK_FREQ) || \ - defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif /* CONFIG_FSL_CORENET */ +#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async @@ -77,6 +77,30 @@ int checkcpu (void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + if (SVR_SOC_VER(svr) == SVR_T4080) { + ccsr_rcpm_t *rcpm = + (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + + setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || + FSL_CORENET_DEVDISR2_DTSEC1_9); + setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); + setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); + + /* It needs SW to disable core4~7 as HW design sake on T4080 */ + for (i = 4; i < 8; i++) + cpu_disable(i); + + /* request core4~7 into PH20 state, prior to entering PCL10 + * state, all cores in cluster should be placed in PH20 state. + */ + setbits_be32(&rcpm->pcph20setr, 0xf0); + + /* put the 2nd cluster into PCL10 state */ + setbits_be32(&rcpm->clpcl10setr, 1 << 1); + } +#endif + if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" @@ -130,86 +154,107 @@ int checkcpu (void) get_sys_info(&sysinfo); +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + if (sysinfo.diff_sysclk == 1) + puts("Single Source Clock Configuration\n"); +#endif + puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, - strmhz(buf1, sysinfo.freqProcessor[core])); + strmhz(buf1, sysinfo.freq_processor[core])); } - printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); + printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); + printf("\n"); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", - strmhz(buf1, sysinfo.freqDDRBus/2), - strmhz(buf2, sysinfo.freqDDRBus)); + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", - strmhz(buf1, sysinfo.freqDDRBus/2), - strmhz(buf2, sysinfo.freqDDRBus)); + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", - strmhz(buf1, sysinfo.freqDDRBus/2), - strmhz(buf2, sysinfo.freqDDRBus)); + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", - strmhz(buf1, sysinfo.freqDDRBus/2), - strmhz(buf2, sysinfo.freqDDRBus)); + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", - strmhz(buf1, sysinfo.freqDDRBus/2), - strmhz(buf2, sysinfo.freqDDRBus)); + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); break; } #endif #if defined(CONFIG_FSL_LBC) - if (sysinfo.freqLocalBus > LCRR_CLKDIV) { - printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); + if (sysinfo.freq_localbus > LCRR_CLKDIV) { + printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", - sysinfo.freqLocalBus); + sysinfo.freq_localbus); } #endif #if defined(CONFIG_FSL_IFC) - printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); + printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); #endif #ifdef CONFIG_CPM2 - printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); + printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); #endif #ifdef CONFIG_QE - printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); + printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, - strmhz(buf1, sysinfo.freqFMan[i])); + strmhz(buf1, sysinfo.freq_fman[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN - printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); + printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); #endif #ifdef CONFIG_SYS_DPAA_PME - printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); + printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); #endif - puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); + puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); + +#ifdef CONFIG_FSL_CORENET + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); +#endif return 0; } @@ -256,7 +301,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifndef CONFIG_SYS_FSL_TBCLK_DIV #define CONFIG_SYS_FSL_TBCLK_DIV 8 #endif -unsigned long get_tbclk (void) +__weak unsigned long get_tbclk (void) { unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; @@ -265,6 +310,14 @@ unsigned long get_tbclk (void) #if defined(CONFIG_WATCHDOG) +#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE) +void +init_85xx_watchdog(void) +{ + mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | + TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC)); +} + void reset_85xx_watchdog(void) { @@ -322,7 +375,8 @@ void mpc85xx_reginfo(void) !defined(CONFIG_SYS_INIT_L2_ADDR) phys_size_t initdram(int board_type) { -#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ + defined(CONFIG_QEMU_E500) return fsl_ddr_sdram_size(); #else return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; @@ -387,7 +441,7 @@ phys_size_t initdram(int board_type) /* Board-specific functions defined in each board's ddr.c */ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num); + unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn); unsigned int @@ -400,12 +454,12 @@ static void dump_spd_ddr_reg(void) int i, j, k, m; u8 *p_8; u32 *p_32; - ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; generic_spd_eeprom_t spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - fsl_ddr_get_spd(spd[i], i); + fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR); puts("SPD data of all dimms (zero vaule is omitted)...\n"); puts("Byte (hex) "); @@ -437,21 +491,21 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { switch (i) { case 0: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; #endif default: @@ -466,7 +520,7 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); puts("\n"); - for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { + for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { m = 0; printf("%6d (0x%04x)", k * 4, k * 4); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 25beda233e..4cf8853b72 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -19,22 +19,101 @@ #include #include #include +#include #include #include #include +#include #include #include #include "mp.h" +#ifdef CONFIG_FSL_CAAM +#include +#endif #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include #include #endif #include "../../../../drivers/block/fsl_sata.h" +#ifdef CONFIG_U_QE +#include "../../../../drivers/qe/qe.h" +#endif DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_QE +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +/* + * For deriving usb clock from 100MHz sysclk, reference divisor is set + * to a value of 5, which gives an intermediate value 20(100/5). The + * multiplication factor integer is set to 24, which when multiplied to + * above intermediate value provides clock for usb ip. + */ +void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + if (sysinfo.diff_sysclk == 1) { + clrbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_MFI); + setbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | + CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); + } +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 +void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) +{ +#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE + u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); + + /* Increase Disconnect Threshold by 50mV */ + xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | + INC_DCNT_THRESHOLD_50MV; + /* Enable programming of USB High speed Disconnect threshold */ + xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; + out_be32(&usb_phy->port1.xcvrprg, xcvrprg); + + xcvrprg = in_be32(&usb_phy->port2.xcvrprg); + /* Increase Disconnect Threshold by 50mV */ + xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | + INC_DCNT_THRESHOLD_50MV; + /* Enable programming of USB High speed Disconnect threshold */ + xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; + out_be32(&usb_phy->port2.xcvrprg, xcvrprg); +#else + + u32 temp = 0; + u32 status = in_be32(&usb_phy->status1); + + u32 squelch_prog_rd_0_2 = + (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) + & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; + + u32 squelch_prog_rd_3_5 = + (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) + & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; + + setbits_be32(&usb_phy->config1, + CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); + setbits_be32(&usb_phy->config2, + CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); + + temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; + out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); + + temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; + out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); +#endif +} +#endif + + +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); @@ -123,17 +202,14 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) #endif #ifdef CONFIG_SYS_FSL_CPC -static void enable_cpc(void) +#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) +void disable_cpc_sram(void) { int i; - u32 size = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { - u32 cpccfg0 = in_be32(&cpc->cpccfg0); - size += CPC_CFG0_SZ_K(cpccfg0); -#ifdef CONFIG_RAMBOOT_PBL if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); @@ -148,8 +224,71 @@ static void enable_cpc(void) out_be32(&cpc->cpccsr0, 0); out_be32(&cpc->cpcsrcr0, 0); } + } +} +#endif + +#if defined(T1040_TDM_QUIRK_CCSR_BASE) +#ifdef CONFIG_POST +#error POST memory test cannot be enabled with TDM +#endif +static void enable_tdm_law(void) +{ + int ret; + char buffer[HWCONFIG_BUFFER_SIZE] = {0}; + int tdm_hwconfig_enabled = 0; + + /* + * Extract hwconfig from environment since environment + * is not setup properly yet. Search for tdm entry in + * hwconfig. + */ + ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (ret > 0) { + tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); + /* If tdm is defined in hwconfig, set law for tdm workaround */ + if (tdm_hwconfig_enabled) + set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, + LAW_TRGT_IF_CCSR); + } +} #endif +void enable_cpc(void) +{ + int i; + int ret; + u32 size = 0; + u32 cpccfg0; + char buffer[HWCONFIG_BUFFER_SIZE]; + char cpc_subarg[16]; + bool have_hwconfig = false; + int cpc_args = 0; + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + /* Extract hwconfig from environment */ + ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (ret > 0) { + /* + * If "en_cpc" is not defined in hwconfig then by default all + * cpcs are enable. If this config is defined then individual + * cpcs which have to be enabled should also be defined. + * e.g en_cpc:cpc1,cpc2; + */ + if (hwconfig_f("en_cpc", buffer)) + have_hwconfig = true; + } + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + if (have_hwconfig) { + sprintf(cpc_subarg, "cpc%u", i + 1); + cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); + if (cpc_args == 0) + continue; + } + cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); #endif @@ -159,6 +298,12 @@ static void enable_cpc(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) { + setbits_be32(&cpc->cpchdbcr0, + CPC_HDBCR0_SPLRU_LEVEL_EN); + } +#endif out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ @@ -166,7 +311,8 @@ static void enable_cpc(void) } - printf("Corenet Platform Cache: %d KB enabled\n", size); + puts("Corenet Platform Cache: "); + print_size(size * 1024, " enabled\n"); } static void invalidate_cpc(void) @@ -187,6 +333,7 @@ static void invalidate_cpc(void) #else #define enable_cpc() #define invalidate_cpc() +#define disable_cpc_sram() #endif /* CONFIG_SYS_FSL_CPC */ /* @@ -210,10 +357,76 @@ static void corenet_tb_init(void) } #endif -void cpu_init_f (void) +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +void fsl_erratum_a007212_workaround(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_pll_ratio; + u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); + u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); + u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); + u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); +#endif +#endif + /* + * Even this workaround applies to selected version of SoCs, it is + * safe to apply to all versions, with the limitation of odd ratios. + * If RCW has disabled DDR PLL, we have to apply this workaround, + * otherwise DDR will not work. + */ + ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* check if RCW sets ratio to 0, required by this workaround */ + if (ddr_pll_ratio != 0) + return; + ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* check if reserved bits have the desired ratio */ + if (ddr_pll_ratio == 0) { + printf("Error: Unknown DDR PLL ratio!\n"); + return; + } + ddr_pll_ratio >>= 1; + + setbits_be32(plldadcr1, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + setbits_be32(plldadcr2, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + setbits_be32(plldadcr3, 0x02000001); +#endif +#endif + setbits_be32(dpdovrcr4, 0xe0000000); + out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); +#endif +#endif + udelay(100); + clrbits_be32(plldadcr1, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + clrbits_be32(plldadcr2, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + clrbits_be32(plldadcr3, 0x02000001); +#endif +#endif + clrbits_be32(dpdovrcr4, 0xe0000000); +} +#endif + +ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ + (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_SECURE_BOOT) @@ -241,6 +454,16 @@ void cpu_init_f (void) law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index); + +#if defined(CONFIG_SYS_CPC_REINIT_F) + disable_cpc_sram(); +#endif + +#if defined(CONFIG_FSL_CORENET) + /* Put PAMU in bypass mode */ + out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS); +#endif + #endif #ifdef CONFIG_CPM2 @@ -252,10 +475,12 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif -#ifdef CONFIG_QE + +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) /* Config QE ioports */ config_qe_ioports(); #endif + #if defined(CONFIG_FSL_DMA) dma_init(); #endif @@ -273,6 +498,11 @@ void cpu_init_f (void) in_be32(&gur->dcsrcr); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + fsl_erratum_a007212_workaround(); +#endif + + return 0; } /* Implement a dummy function for those platforms w/o SERDES */ @@ -282,14 +512,21 @@ static void __fsl_serdes__init(void) } __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) int enable_cluster_l2(void) { int i = 0; - u32 cluster; + u32 cluster, svr = get_svr(); ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache; + /* only the L2 of first cluster should be enabled as expected on T4080, + * but there is no EOC in the first cluster as HW sake, so return here + * to skip enabling L2 cache of the 2nd cluster. + */ + if (SVR_SOC_VER(svr) == SVR_T4080) + return 0; + cluster = in_be32(&gur->tp_cluster[i].lower); if (cluster & TP_CLUSTER_EOC) return 0; @@ -310,7 +547,8 @@ int enable_cluster_l2(void) u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; u32 type = in_be32(&gur->tp_ityp[idx]); - if (type & TP_ITYP_AV) + if ((type & TP_ITYP_AV) && + TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) cluster_valid = 1; } @@ -335,78 +573,15 @@ int enable_cluster_l2(void) /* * Initialize L2 as cache. - * - * The newer 8548, etc, parts have twice as much cache, but - * use the same bit-encoding as the older 8555, etc, parts. - * */ -int cpu_init_r(void) +int l2cache_init(void) { __maybe_unused u32 svr = get_svr(); -#ifdef CONFIG_SYS_LBC_LCRR - fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; -#endif #ifdef CONFIG_L2_CACHE ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; -#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif -#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) - extern int spin_table_compat; - const char *spin; -#endif - -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ - defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) - /* - * CPU22 and NMG_CPU_A011 share the same workaround. - * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 - * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 - * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both - * fixed in 2.0. NMG_CPU_A011 is activated by default and can - * be disabled by hwconfig with syntax: - * - * fsl_cpu_a011:disable - */ - extern int enable_cpu_a011_workaround; -#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 - enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); -#else - char buffer[HWCONFIG_BUFFER_SIZE]; - char *buf = NULL; - int n, res; - - n = getenv_f("hwconfig", buffer, sizeof(buffer)); - if (n > 0) - buf = buffer; - - res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); - if (res > 0) - enable_cpu_a011_workaround = 0; - else { - if (n >= HWCONFIG_BUFFER_SIZE) { - printf("fsl_cpu_a011 was not found. hwconfig variable " - "may be too long\n"); - } - enable_cpu_a011_workaround = - (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || - (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); - } -#endif - if (enable_cpu_a011_workaround) { - flush_dcache(); - mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); - sync(); - } -#endif - -#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) - spin = getenv("spin_table_compat"); - if (spin && (*spin == 'n')) - spin_table_compat = 0; - else - spin_table_compat = 1; -#endif puts ("L2: "); @@ -448,28 +623,28 @@ int cpu_init_r(void) case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || ver == SVR_8541 || ver == SVR_8555) { - puts("128 KB "); - /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ + puts("128 KiB "); + /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ cache_ctl = 0xc4000000; } else { - puts("256 KB "); + puts("256 KiB "); cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ } break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || ver == SVR_8541 || ver == SVR_8555) { - puts("256 KB "); - /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ + puts("256 KiB "); + /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ cache_ctl = 0xc8000000; } else { - puts ("512 KB "); + puts("512 KiB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; } break; case 0x3: - puts("1024 KB "); + puts("1024 KiB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; break; @@ -517,23 +692,121 @@ int cpu_init_r(void) if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) ; - printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); + print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); } skip_l2: -#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (l2cache->l2csr0 & L2CSR0_L2E) - printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64); + print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, + " enabled\n"); enable_cluster_l2(); #else puts("disabled\n"); #endif + return 0; +} + +/* + * + * The newer 8548, etc, parts have twice as much cache, but + * use the same bit-encoding as the older 8555, etc, parts. + * + */ +int cpu_init_r(void) +{ + __maybe_unused u32 svr = get_svr(); +#ifdef CONFIG_SYS_LBC_LCRR + fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; +#endif +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + extern int spin_table_compat; + const char *spin; +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 and NMG_CPU_A011 share the same workaround. + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both + * fixed in 2.0. NMG_CPU_A011 is activated by default and can + * be disabled by hwconfig with syntax: + * + * fsl_cpu_a011:disable + */ + extern int enable_cpu_a011_workaround; +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 + enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); +#else + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + int n, res; + + n = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (n > 0) + buf = buffer; + + res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); + if (res > 0) { + enable_cpu_a011_workaround = 0; + } else { + if (n >= HWCONFIG_BUFFER_SIZE) { + printf("fsl_cpu_a011 was not found. hwconfig variable " + "may be too long\n"); + } + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || + (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); + } +#endif + if (enable_cpu_a011_workaround) { + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); + sync(); + } +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running + * in write shadow mode. Checking DCWS before setting SPR 976. + */ + if (mfspr(L1CSR2) & L1CSR2_DCWS) + mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); +#endif + +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + spin = getenv("spin_table_compat"); + if (spin && (*spin == 'n')) + spin_table_compat = 0; + else + spin_table_compat = 1; +#endif + + l2cache_init(); +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif enable_cpc(); +#if defined(T1040_TDM_QUIRK_CCSR_BASE) + enable_tdm_law(); +#endif +#ifndef CONFIG_SYS_FSL_NO_SERDES /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 +#define MCFGR_AXIPIPE 0x000000f0 + if (IS_SVR_REV(svr, 1, 0)) + sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 if (IS_SVR_REV(svr, 1, 0)) { @@ -595,16 +868,24 @@ skip_l2: #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE { - ccsr_usb_phy_t *usb_phy1 = + struct ccsr_usb_phy __iomem *usb_phy1 = (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy1); +#endif out_be32(&usb_phy1->usb_enable_override, CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); } #endif #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE { - ccsr_usb_phy_t *usb_phy2 = + struct ccsr_usb_phy __iomem *usb_phy2 = (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy2); +#endif out_be32(&usb_phy2->usb_enable_override, CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); } @@ -625,13 +906,16 @@ skip_l2: #endif #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) - ccsr_usb_phy_t *usb_phy = + struct ccsr_usb_phy __iomem *usb_phy = (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; setbits_be32(&usb_phy->pllprg[1], CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | CONFIG_SYS_FSL_USB_PLLPRG2_MFI | CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + usb_single_source_clk_configure(usb_phy); +#endif setbits_be32(&usb_phy->port1.ctrl, CONFIG_SYS_FSL_USB_CTRL_PHY_EN); setbits_be32(&usb_phy->port1.drvvbuscfg, @@ -644,12 +928,22 @@ skip_l2: CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); setbits_be32(&usb_phy->port2.pwrfltcfg, CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy); #endif +#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ + #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) /* * For P1022/1013 Rev1.0 silicon, after power on SATA host @@ -673,12 +967,11 @@ skip_l2: } #endif + init_used_tlb_cams(); return 0; } -extern void setup_ivors(void); - void arch_preboot_os(void) { u32 msr; @@ -691,8 +984,6 @@ void arch_preboot_os(void) msr = mfmsr(); msr &= ~(MSR_ME|MSR_CE); mtmsr(msr); - - setup_ivors(); } #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) @@ -707,21 +998,13 @@ int sata_initialize(void) void cpu_secondary_init_r(void) { -#ifdef CONFIG_QE +#ifdef CONFIG_U_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ +#elif defined CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ -#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND - int ret; - size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; - - /* load QE firmware from NAND flash to DDR first */ - ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); - - if (ret && ret == -EUCLEAN) { - printf ("NAND read for QE firmware at offset %x failed %d\n", - CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); - } #endif + +#ifdef CONFIG_QE qe_init(qe_base); qe_reset(); #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 993b8b828b..5ca9bf5ff9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -70,16 +70,16 @@ void setup_ifc(void) #endif /* Change flash's physical address */ - out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); - out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); - out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); + ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); + ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); return ; } #endif /* We run cpu_init_early_f in AS = 1 */ -void cpu_init_early_f(void) +void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; int i; @@ -102,6 +102,14 @@ void cpu_init_early_f(void) for (i = 0; i < sizeof(gd_t); i++) ((char *)gd)[i] = 0; +#ifdef CONFIG_QEMU_E500 + /* + * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, + * so we need to populate it before it accesses it. + */ + gd->fdt_blob = fdt; +#endif + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); @@ -153,9 +161,12 @@ void cpu_init_early_f(void) setup_ifc_sram = (void *)SRAM_BASE_ADDR; dst = (u32 *) SRAM_BASE_ADDR; src = (u32 *) setup_ifc; - for (i = 0; i < 1024; i++) + for (i = 0; i < 1024; i++) { + /* cppcheck-suppress nullPointer */ *dst++ = *src++; + } + /* cppcheck-suppress nullPointer */ setup_ifc_sram(); /* CLEANUP */ diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c deleted file mode 100644 index 8a86819fb5..0000000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num) -{ - unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - if (ctrl_num != 0) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); -#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541) - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); -#endif - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - asm("sync;isync;msync"); - udelay(500); -} - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -/* - * Initialize all of memory for ECC, then enable errors. - */ - -void -ddr_enable_ecc(unsigned int dram_size) -{ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* - * Enable errors for ECC. - */ - debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); -} - -#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c deleted file mode 100644 index a705862522..0000000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num) -{ - unsigned int i; - ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - -#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint svr; -#endif - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - -#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 - /* - * Set the DDR IO receiver to an acceptable bias point. - * Fixed in Rev 2.1. - */ - svr = get_svr(); - if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) { - if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == - SDRAM_CFG_SDRAM_TYPE_DDR2) - out_be32(&gur->ddrioovcr, 0x90000000); - else - out_be32(&gur->ddrioovcr, 0xA8000000); - } -#endif - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while (in_be32(&ddr->sdram_cfg_2) & 0x10) { - udelay(10000); /* throttle polling rate */ - } -} diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c deleted file mode 100644 index c5b47200e0..0000000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ /dev/null @@ -1,430 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num) -{ - unsigned int i, bus_width; - volatile ccsr_ddr_t *ddr; - u32 temp_sdram_cfg; - u32 total_gb_size_per_controller; - int timeout; -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - int timeout_save; - volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; - unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; - int csn = -1; -#endif - - switch (ctrl_num) { - case 0: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - break; -#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) - case 1: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - break; -#endif -#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) - case 2: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; - break; -#endif -#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) - case 3: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; - break; -#endif - default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - if (regs->ddr_eor) - out_be32(&ddr->eor, regs->ddr_eor); -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - debug("Workaround for ERRATUM_DDR111_DDR134\n"); - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; - cs_ea = regs->cs[i].bnds & 0xfff; - if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { - csn = i; - csn_bnds_backup = regs->cs[i].bnds; - csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; - if (cs_ea > 0xeff) - *csn_bnds_t = regs->cs[i].bnds + 0x01000000; - else - *csn_bnds_t = regs->cs[i].bnds + 0x01000100; - debug("Found cs%d_bns (0x%08x) covering 0xff000000, " - "change it to 0x%x\n", - csn, csn_bnds_backup, regs->cs[i].bnds); - break; - } - } -#endif - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); - out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); - out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); - out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); - out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); - out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); - out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); - if (regs->ddr_wrlvl_cntl_2) - out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); - if (regs->ddr_wrlvl_cntl_3) - out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); - - out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); - out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); - out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); - out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); - out_be32(&ddr->err_disable, regs->err_disable); - out_be32(&ddr->err_int_en, regs->err_int_en); - for (i = 0; i < 32; i++) { - if (regs->debug[i]) { - debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); - out_be32(&ddr->debug[i], regs->debug[i]); - } - } -#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 - out_be32(&ddr->debug[28], 0x30003000); -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 - out_be32(&ddr->debug[12], 0x00000015); - out_be32(&ddr->debug[21], 0x24000000); -#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ - - /* Set, but do not enable the memory */ - temp_sdram_cfg = regs->ddr_sdram_cfg; - temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 - debug("Workaround for ERRATUM_DDR_A003\n"); - if (regs->ddr_sdram_rcw_2 & 0x00f00000) { - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); - out_be32(&ddr->debug[2], 0x00000400); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); - out_be32(&ddr->mtcr, 0); - out_be32(&ddr->debug[12], 0x00000015); - out_be32(&ddr->debug[21], 0x24000000); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); - - asm volatile("sync;isync"); - while (!(in_be32(&ddr->debug[1]) & 0x2)) - ; - - switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { - case 0x00000000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x02)); - break; - case 0x00100000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x0a)); - break; - case 0x00200000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x12)); - break; - case 0x00300000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x1a)); - break; - default: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x02)); - printf("Unsupported RC10\n"); - break; - } - - while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) - ; - udelay(6); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->debug[2], 0x0); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->debug[12], 0x0); - out_be32(&ddr->debug[21], 0x0); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - - } -#endif - /* - * For 8572 DDR1 erratum - DDR controller may enter illegal state - * when operatiing in 32-bit bus mode with 4-beat bursts, - * This erratum does not affect DDR3 mode, only for DDR2 mode. - */ -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 - debug("Workaround for ERRATUM_DDR_115\n"); - if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) - && in_be32(&ddr->sdram_cfg) & 0x80000) { - /* set DEBUG_1[31] */ - setbits_be32(&ddr->debug[0], 1); - } -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - debug("Workaround for ERRATUM_DDR111_DDR134\n"); - /* - * This is the combined workaround for DDR111 and DDR134 - * following the published errata for MPC8572 - */ - - /* 1. Set EEBACR[3] */ - setbits_be32(&ecm->eebacr, 0x10000000); - debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); - - /* 2. Set DINIT in SDRAM_CFG_2*/ - setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); - debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", - in_be32(&ddr->sdram_cfg_2)); - - /* 3. Set DEBUG_3[21] */ - setbits_be32(&ddr->debug[2], 0x400); - debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); - -#endif /* part 1 of the workaound */ - - /* - * 500 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - * DDR2 need 200 us, and DDR3 need 500 us from spec, - * we choose the max, that is 500 us for all of case. - */ - udelay(500); - asm volatile("sync;isync"); - - /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); - asm volatile("sync;isync"); - - total_gb_size_per_controller = 0; - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (!(regs->cs[i].config & 0x80000000)) - continue; - total_gb_size_per_controller += 1 << ( - ((regs->cs[i].config >> 14) & 0x3) + 2 + - ((regs->cs[i].config >> 8) & 0x7) + 12 + - ((regs->cs[i].config >> 0) & 0x7) + 8 + - 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - - 26); /* minus 26 (count of 64M) */ - } - if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ - total_gb_size_per_controller *= 3; - else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ - total_gb_size_per_controller <<= 1; - /* - * total memory / bus width = transactions needed - * transactions needed / data rate = seconds - * to add plenty of buffer, double the time - * For example, 2GB on 666MT/s 64-bit bus takes about 402ms - * Let's wait for 800ms - */ - bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) - >> SDRAM_CFG_DBW_SHIFT); - timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 1; -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - timeout_save = timeout; -#endif - total_gb_size_per_controller >>= 4; /* shift down to gb size */ - debug("total %d GB\n", total_gb_size_per_controller); - debug("Need to wait up to %d * 10ms\n", timeout); - - /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && - (timeout >= 0)) { - udelay(10000); /* throttle polling rate */ - timeout--; - } - - if (timeout <= 0) - printf("Waiting for D_INIT timeout. Memory may not work.\n"); - -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - /* continue this workaround */ - - /* 4. Clear DEBUG3[21] */ - clrbits_be32(&ddr->debug[2], 0x400); - debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); - - /* DDR134 workaround starts */ - /* A: Clear sdram_cfg_2[odt_cfg] */ - clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); - debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", - in_be32(&ddr->sdram_cfg_2)); - - /* B: Set DEBUG1[15] */ - setbits_be32(&ddr->debug[0], 0x10000); - debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); - - /* C: Set timing_cfg_2[cpo] to 0b11111 */ - setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); - debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", - in_be32(&ddr->timing_cfg_2)); - - /* D: Set D6 to 0x9f9f9f9f */ - out_be32(&ddr->debug[5], 0x9f9f9f9f); - debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); - - /* E: Set D7 to 0x9f9f9f9f */ - out_be32(&ddr->debug[6], 0x9f9f9f9f); - debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); - - /* F: Set D2[20] */ - setbits_be32(&ddr->debug[1], 0x800); - debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); - - /* G: Poll on D2[20] until cleared */ - while (in_be32(&ddr->debug[1]) & 0x800) - udelay(10000); /* throttle polling rate */ - - /* H: Clear D1[15] */ - clrbits_be32(&ddr->debug[0], 0x10000); - debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); - - /* I: Set sdram_cfg_2[odt_cfg] */ - setbits_be32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); - debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); - - /* Continuing with the DDR111 workaround */ - /* 5. Set D2[21] */ - setbits_be32(&ddr->debug[1], 0x400); - debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); - - /* 6. Poll D2[21] until its cleared */ - while (in_be32(&ddr->debug[1]) & 0x400) - udelay(10000); /* throttle polling rate */ - - /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ - debug("Wait for %d * 10ms\n", timeout_save); - udelay(timeout_save * 10000); - - /* 8. Set sdram_cfg_2[dinit] if options requires */ - setbits_be32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); - debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); - - /* 9. Poll until dinit is cleared */ - timeout = timeout_save; - debug("Need to wait up to %d * 10ms\n", timeout); - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && - (timeout >= 0)) { - udelay(10000); /* throttle polling rate */ - timeout--; - } - - if (timeout <= 0) - printf("Waiting for D_INIT timeout. Memory may not work.\n"); - - /* 10. Clear EEBACR[3] */ - clrbits_be32(&ecm->eebacr, 10000000); - debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); - - if (csn != -1) { - csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds; - *csn_bnds_t = csn_bnds_backup; - debug("Change cs%d_bnds back to 0x%08x\n", - csn, regs->cs[csn].bnds); - setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ - switch (csn) { - case 0: - out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); - break; - case 1: - out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); - break; - case 2: - out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); - break; - case 3: - out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); - break; - } - clrbits_be32(&ddr->sdram_cfg, 0x2); - } -#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ -} diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index cfaa2edced..d4c3d9df9b 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -14,6 +14,7 @@ #include #include #include +#include #ifdef CONFIG_FSL_ESDHC #include #endif @@ -35,6 +36,11 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) u32 bootpg = determine_mp_bootpg(NULL); u32 id = get_my_id(); const char *enable_method; +#if defined(T1040_TDM_QUIRK_CCSR_BASE) + int ret; + int tdm_hwconfig_enabled = 0; + char buffer[HWCONFIG_BUFFER_SIZE] = {0}; +#endif off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { @@ -77,6 +83,26 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) "device_type", "cpu", 4); } +#if defined(T1040_TDM_QUIRK_CCSR_BASE) +#define CONFIG_MEM_HOLE_16M 0x1000000 + /* + * Extract hwconfig from environment. + * Search for tdm entry in hwconfig. + */ + ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (ret > 0) + tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); + + /* Reserve the memory hole created by TDM LAW, so OSes dont use it */ + if (tdm_hwconfig_enabled) { + off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, + CONFIG_MEM_HOLE_16M); + if (off < 0) + printf("Failed to reserve memory for tdm: %s\n", + fdt_strerror(off)); + } +#endif + /* Reserve the boot page so OSes dont use it */ if ((u64)bootpg < memory_limit) { off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); @@ -108,6 +134,21 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) printf("Failed to reserve memory for spin table: %s\n", fdt_strerror(off)); } +#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_SPL_MMC_BOOT + off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, + CONFIG_SYS_MMC_U_BOOT_SIZE); + if (off < 0) + printf("Failed to reserve memory for SD deep sleep: %s\n", + fdt_strerror(off)); +#elif defined(CONFIG_SPL_SPI_BOOT) + off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, + CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); + if (off < 0) + printf("Failed to reserve memory for SPI deep sleep: %s\n", + fdt_strerror(off)); +#endif +#endif } #endif @@ -273,14 +314,18 @@ static inline void ft_fixup_l2cache(void *blob) if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) /* Only initialize every eighth thread */ - if (reg && !((*reg) % 8)) + if (reg && !((*reg) % 8)) { + fdt_setprop_cell(blob, l2_off, "cache-stash-id", + (*reg / 4) + 32 + 1); + } #else - if (reg) -#endif + if (reg) { fdt_setprop_cell(blob, l2_off, "cache-stash-id", - (*reg * 2) + 32 + 1); + (*reg * 2) + 32 + 1); + } +#endif #endif fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); @@ -403,22 +448,22 @@ static void ft_fixup_dpaa_clks(void *blob) get_sys_info(&sysinfo); #ifdef CONFIG_SYS_DPAA_FMAN ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, - sysinfo.freqFMan[0]); + sysinfo.freq_fman[0]); #if (CONFIG_SYS_NUM_FMAN == 2) ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, - sysinfo.freqFMan[1]); + sysinfo.freq_fman[1]); #endif #endif #ifdef CONFIG_SYS_DPAA_QBMAN do_fixup_by_compat_u32(blob, "fsl,qman", - "clock-frequency", sysinfo.freqQMAN, 1); + "clock-frequency", sysinfo.freq_qman, 1); #endif #ifdef CONFIG_SYS_DPAA_PME do_fixup_by_compat_u32(blob, "fsl,pme", - "clock-frequency", sysinfo.freqPME, 1); + "clock-frequency", sysinfo.freq_pme, 1); #endif } #else @@ -476,7 +521,7 @@ void fdt_fixup_fman_firmware(void *blob) if (!p) return; - fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0); + fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16); if (!fmanfw) return; @@ -582,10 +627,83 @@ static void fdt_fixup_usb(void *fdt) #define fdt_fixup_usb(x) #endif +#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \ + defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) +void fdt_fixup_dma3(void *blob) +{ + /* the 3rd DMA is not functional if SRIO2 is chosen */ + int nodeoff; + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + +#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) +#if defined(CONFIG_PPC_T2080) + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + switch (srds_prtcl_s2) { + case 0x29: + case 0x2d: + case 0x2e: +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) + u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS4_PRTCL; + srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; + + switch (srds_prtcl_s4) { + case 6: + case 8: + case 14: + case 16: +#endif + nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma", + CONFIG_SYS_ELO3_DMA3); + if (nodeoff > 0) + fdt_status_disabled(blob, nodeoff); + else + printf("WARNING: unable to disable dma3\n"); + break; + default: + break; + } +} +#else +#define fdt_fixup_dma3(x) +#endif + +#if defined(CONFIG_PPC_T1040) +static void fdt_fixup_l2_switch(void *blob) +{ + uchar l2swaddr[6]; + int node; + + /* The l2switch node from device-tree has + * compatible string "vitesse-9953" */ + node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953"); + if (node == -FDT_ERR_NOTFOUND) + /* no l2switch node has been found */ + return; + + /* Get MAC address for the l2switch from "l2switchaddr"*/ + if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { + printf("Warning: MAC address for l2switch not found\n"); + memset(l2swaddr, 0, sizeof(l2swaddr)); + } + + /* Add MAC address to l2switch node */ + fdt_setprop(blob, node, "local-mac-address", l2swaddr, + sizeof(l2swaddr)); +} +#else +#define fdt_fixup_l2_switch(x) +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; int val; + int len; sys_info_t sysinfo; /* delete crypto node if not on an E-processor */ @@ -596,7 +714,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) ccsr_sec_t __iomem *sec; sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; - fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms)); + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif @@ -604,15 +722,19 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_add_enet_stashing(blob); +#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV +#define CONFIG_FSL_TBCLK_EXTRA_DIV 1 +#endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", get_tbclk(), 1); + "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV, + 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); get_sys_info(&sysinfo); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { - u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); + val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); fdt_setprop(blob, off, "clock-frequency", &val, 4); off = fdt_node_offset_by_prop_value(blob, off, "device_type", "cpu", 4); @@ -638,7 +760,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_CPM2 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", - "current-speed", bd->bi_baudrate, 1); + "current-speed", gd->baudrate, 1); do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", "clock-frequency", bd->bi_brgfreq, 1); @@ -714,6 +836,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", gd->bus_clk/2, 1); fdt_fixup_usb(blob); + + fdt_fixup_l2_switch(blob); + + fdt_fixup_dma3(blob); } /* diff --git a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S deleted file mode 100644 index ebbb8c0744..0000000000 --- a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * Kumar Gala - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* This file is intended to be included by other asm code since - * we will want to execute this on both the primary core when - * it does a bootm and the secondary core's that get released - * out of the spin table */ - -#define SET_IVOR(vector_number, vector_offset) \ - li r3,vector_offset@l; \ - mtspr SPRN_IVOR##vector_number,r3; - -#define SET_GIVOR(vector_number, vector_offset) \ - li r3,vector_offset@l; \ - mtspr SPRN_GIVOR##vector_number,r3; - - SET_IVOR(0, 0x020) /* Critical Input */ - SET_IVOR(1, 0x000) /* Machine Check */ - SET_IVOR(2, 0x060) /* Data Storage */ - SET_IVOR(3, 0x080) /* Instruction Storage */ - SET_IVOR(4, 0x0a0) /* External Input */ - SET_IVOR(5, 0x0c0) /* Alignment */ - SET_IVOR(6, 0x0e0) /* Program */ - SET_IVOR(7, 0x100) /* FP Unavailable */ - SET_IVOR(8, 0x120) /* System Call */ - SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ - SET_IVOR(10, 0x160) /* Decrementer */ - SET_IVOR(11, 0x180) /* Fixed Interval Timer */ - SET_IVOR(12, 0x1a0) /* Watchdog Timer */ - SET_IVOR(13, 0x1c0) /* Data TLB Error */ - SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ - SET_IVOR(15, 0x040) /* Debug */ - -/* e500v1 & e500v2 only */ -#ifndef CONFIG_E500MC - SET_IVOR(32, 0x200) /* SPE Unavailable */ - SET_IVOR(33, 0x220) /* Embedded FP Data */ - SET_IVOR(34, 0x240) /* Embedded FP Round */ -#endif - - SET_IVOR(35, 0x260) /* Performance monitor */ - -/* e500mc only */ -#ifdef CONFIG_E500MC - SET_IVOR(36, 0x280) /* Processor doorbell */ - SET_IVOR(37, 0x2a0) /* Processor doorbell critical */ - SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */ - SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */ - SET_IVOR(40, 0x300) /* Hypervisor system call */ - SET_IVOR(41, 0x320) /* Hypervisor Priviledge */ - - SET_GIVOR(2, 0x060) /* Guest Data Storage */ - SET_GIVOR(3, 0x080) /* Guest Instruction Storage */ - SET_GIVOR(4, 0x0a0) /* Guest External Input */ - SET_GIVOR(8, 0x120) /* Guest System Call */ - SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */ - SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */ -#endif diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index de6bd11a16..acb1353e5d 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -11,15 +11,20 @@ #include #include #include +#include #include "fsl_corenet2_serdes.h" -static u64 serdes1_prtcl_map; -static u64 serdes2_prtcl_map; +#ifdef CONFIG_SYS_FSL_SRDS_1 +static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 +static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; +#endif #ifdef CONFIG_SYS_FSL_SRDS_3 -static u64 serdes3_prtcl_map; +static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #ifdef CONFIG_SYS_FSL_SRDS_4 -static u64 serdes4_prtcl_map; +static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT]; #endif #ifdef DEBUG @@ -71,20 +76,32 @@ static const char *serdes_prtcl_str[] = { [XFI_FM2_MAC9] = "XFI_FM2_MAC9", [XFI_FM2_MAC10] = "XFI_FM2_MAC10", [INTERLAKEN] = "INTERLAKEN", + [QSGMII_SW1_A] = "QSGMII_SW1_A", + [QSGMII_SW1_B] = "QSGMII_SW1_B", + [SGMII_SW1_MAC1] = "SGMII_SW1_MAC1", + [SGMII_SW1_MAC2] = "SGMII_SW1_MAC2", + [SGMII_SW1_MAC3] = "SGMII_SW1_MAC3", + [SGMII_SW1_MAC4] = "SGMII_SW1_MAC4", + [SGMII_SW1_MAC5] = "SGMII_SW1_MAC5", + [SGMII_SW1_MAC6] = "SGMII_SW1_MAC6", }; #endif int is_serdes_configured(enum srds_prtcl device) { - u64 ret = 0; + int ret = 0; - ret |= (1ULL << device) & serdes1_prtcl_map; - ret |= (1ULL << device) & serdes2_prtcl_map; +#ifdef CONFIG_SYS_FSL_SRDS_1 + ret |= serdes1_prtcl_map[device]; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + ret |= serdes2_prtcl_map[device]; +#endif #ifdef CONFIG_SYS_FSL_SRDS_3 - ret |= (1ULL << device) & serdes3_prtcl_map; + ret |= serdes3_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_4 - ret |= (1ULL << device) & serdes4_prtcl_map; + ret |= serdes4_prtcl_map[device]; #endif return !!ret; @@ -97,14 +114,18 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) int i; switch (sd) { +#ifdef CONFIG_SYS_FSL_SRDS_1 case FSL_SRDS_1: cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; break; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 case FSL_SRDS_2: cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; break; +#endif #ifdef CONFIG_SYS_FSL_SRDS_3 case FSL_SRDS_3: cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; @@ -133,19 +154,164 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) return -ENODEV; } -u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) +#define BC3_SHIFT 9 +#define DC3_SHIFT 6 +#define FC3_SHIFT 0 +#define BC2_SHIFT 19 +#define DC2_SHIFT 16 +#define FC2_SHIFT 10 +#define BC1_SHIFT 29 +#define DC1_SHIFT 26 +#define FC1_SHIFT 20 +#define BC_MASK 0x1 +#define DC_MASK 0x7 +#define FC_MASK 0x3F + +#define FUSE_VAL_MASK 0x00000003 +#define FUSE_VAL_SHIFT 30 +#define CR0_DCBIAS_SHIFT 5 +#define CR1_FCAP_SHIFT 15 +#define CR1_BCAP_SHIFT 29 +#define FCAP_MASK 0x001F8000 +#define BCAP_MASK 0x20000000 +#define BCAP_OVD_MASK 0x10000000 +#define BYP_CAL_MASK 0x02000000 + +void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, + u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u64 serdes_prtcl_map = 0; u32 cfg; int lane; + memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 + struct ccsr_sfp_regs __iomem *sfp_regs = + (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); + u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; + u32 bc_status, fc_status, dc_status, pll_sr2; + serdes_corenet_t __iomem *srds_regs = (void *)sd_addr; + u32 sfp_spfr0, sel; +#endif + cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; - /* Is serdes enabled at all? */ - if (!cfg) { - printf("SERDES%d is not enabled\n", sd + 1); - return 0; + +/* Erratum A-007186 + * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0) + * The workaround requires factory pre-set SerDes calibration values to be + * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0) + * These values have been shown to work across the + * entire temperature range for all SerDes. These values are then written into + * the SerDes registers to calibrate the SerDes PLL. + * + * This workaround for the protocols and rates that only have the Ring VCO. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 + sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0); + debug("A007186: sfp_spfr0= %x\n", sfp_spfr0); + + sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK; + + if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) { + for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) { + pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); + debug("A007186: pll_num=%x pllcr0=%x\n", + pll_num, pll_status); + /* STEP 1 */ + /* Read factory pre-set SerDes calibration values + * from fuse block(SFP scratch register-sfp_spfr0) + */ + switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) { + case SRDS_PLLCR0_FRATE_SEL_3_0: + case SRDS_PLLCR0_FRATE_SEL_3_072: + debug("A007186: 3.0/3.072 protocol rate\n"); + bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK; + dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK; + fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK; + break; + case SRDS_PLLCR0_FRATE_SEL_3_125: + debug("A007186: 3.125 protocol rate\n"); + bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK; + dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK; + fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK; + break; + case SRDS_PLLCR0_FRATE_SEL_3_75: + debug("A007186: 3.75 protocol rate\n"); + bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK; + dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK; + fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK; + break; + default: + continue; + } + + /* STEP 2 */ + /* Write SRDSxPLLnCR1[11:16] = FC + * Write SRDSxPLLnCR1[2] = BC + */ + pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); + pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) | + ((fc << CR1_FCAP_SHIFT) & FCAP_MASK)); + out_be32(&srds_regs->bank[pll_num].pllcr1, + (pll_cr_upd | pll_cr1)); + debug("A007186: pll_num=%x Updated PLLCR1=%x\n", + pll_num, (pll_cr_upd | pll_cr1)); + /* Write SRDSxPLLnCR0[24:26] = DC + */ + pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); + out_be32(&srds_regs->bank[pll_num].pllcr0, + pll_cr0 | (dc << CR0_DCBIAS_SHIFT)); + debug("A007186: pll_num=%x, Updated PLLCR0=%x\n", + pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT))); + /* Write SRDSxPLLnCR1[3] = 1 + * Write SRDSxPLLnCR1[6] = 1 + */ + pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); + pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK); + out_be32(&srds_regs->bank[pll_num].pllcr1, + (pll_cr_upd | pll_cr1)); + debug("A007186: pll_num=%x Updated PLLCR1=%x\n", + pll_num, (pll_cr_upd | pll_cr1)); + + /* STEP 3 */ + /* Read the status Registers */ + /* Verify SRDSxPLLnSR2[8] = BC */ + pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); + debug("A007186: pll_num=%x pllsr2=%x\n", + pll_num, pll_sr2); + bc_status = (pll_sr2 >> 23) & BC_MASK; + if (bc_status != bc) + debug("BC mismatch\n"); + fc_status = (pll_sr2 >> 16) & FC_MASK; + if (fc_status != fc) + debug("FC mismatch\n"); + pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); + out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 | + 0x02000000); + pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); + dc_status = (pll_sr2 >> 17) & DC_MASK; + if (dc_status != dc) + debug("DC mismatch\n"); + pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); + out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 & + 0xfdffffff); + + /* STEP 4 */ + /* Wait 750us to verify the PLL is locked + * by checking SRDSxPLLnCR0[8] = 1. + */ + udelay(750); + pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); + debug("A007186: pll_num=%x pllcr0=%x\n", + pll_num, pll_status); + + if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0) + printf("A007186 Serdes PLL not locked\n"); + else + debug("A007186 Serdes PLL locked\n"); + } } +#endif cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); @@ -154,34 +320,64 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); - serdes_prtcl_map |= (1ULL << lane_prtcl); + if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) + debug("Unknown SerDes lane protocol %d\n", lane_prtcl); + else + serdes_prtcl_map[lane_prtcl] = 1; } - - return serdes_prtcl_map; } void fsl_serdes_init(void) { - serdes1_prtcl_map = serdes_init(FSL_SRDS_1, - CONFIG_SYS_FSL_CORENET_SERDES_ADDR, - FSL_CORENET2_RCWSR4_SRDS1_PRTCL, - FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); - serdes2_prtcl_map = serdes_init(FSL_SRDS_2, - CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, - FSL_CORENET2_RCWSR4_SRDS2_PRTCL, - FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); +#ifdef CONFIG_SYS_FSL_SRDS_1 + serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR, + FSL_CORENET2_RCWSR4_SRDS1_PRTCL, + FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT, + serdes1_prtcl_map); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes_init(FSL_SRDS_2, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS2_PRTCL, + FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT, + serdes2_prtcl_map); +#endif #ifdef CONFIG_SYS_FSL_SRDS_3 - serdes3_prtcl_map = serdes_init(FSL_SRDS_3, - CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, - FSL_CORENET2_RCWSR4_SRDS3_PRTCL, - FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); + serdes_init(FSL_SRDS_3, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS3_PRTCL, + FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT, + serdes3_prtcl_map); #endif #ifdef CONFIG_SYS_FSL_SRDS_4 - serdes4_prtcl_map = serdes_init(FSL_SRDS_4, - CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, - FSL_CORENET2_RCWSR4_SRDS4_PRTCL, - FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); + serdes_init(FSL_SRDS_4, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS4_PRTCL, + FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT, + serdes4_prtcl_map); #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: +#if defined(CONFIG_T4240QDS) + return "???"; +#else + return "122.88"; +#endif + } +} + diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h index 6de572d594..d515b234a4 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h @@ -9,5 +9,4 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl); int serdes_lane_enabled(int lane); -enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); #endif /* __FSL_CORENET2_SERDES_H */ diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 680b5222bc..ba22f90a6f 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -858,3 +858,20 @@ void fsl_serdes_init(void) } #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: + return "150"; + } +} + diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index a36a4af9da..daf46a9ba8 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -42,7 +42,7 @@ int interrupt_init_cpu(unsigned int *decrementer_count) *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; /* PIE is same as DIE, dec interrupt enable */ - mtspr(SPRN_TCR, TCR_PIE); + mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE); #ifdef CONFIG_INTERRUPTS pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 4b00da9f75..7a2d4be42c 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -66,12 +66,12 @@ static void setup_sec_liodn_base(void) return; /* QILCR[QSLOM] */ - out_be32(&sec->qilcr_ms, 0x3ff<<16); + sec_out32(&sec->qilcr_ms, 0x3ff<<16); base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) | liodn_bases[FSL_HW_PORTAL_SEC].id[1]; - out_be32(&sec->qilcr_ls, base); + sec_out32(&sec->qilcr_ls, base); } #ifdef CONFIG_SYS_DPAA_FMAN @@ -239,9 +239,9 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) #endif #define CONFIG_SYS_MAX_PCI_EPS 8 -#define CONFIG_SYS_PCI_EP_LIODN_START 256 -static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) +static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat, + int ep_liodn_start) { int off, pci_idx = 0, pci_cnt = 0, i, rc; const uint32_t *base_liodn; @@ -271,7 +271,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) continue; } for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++) - liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START + + liodn_offs[i + 1] = ep_liodn_start + i * pci_cnt + pci_idx - *base_liodn; rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list", liodn_offs, sizeof(liodn_offs)); @@ -338,5 +338,22 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif - fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4"); + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0; + + if (pci_ver >= 0x0204) { + if (pci_ver >= 0x0300) + liodn_base = 1024; + else + liodn_base = 256; + } + + if (liodn_base) { + char compat[32]; + + sprintf(compat, "fsl,qoriq-pcie-v%d.%d", + (pci_ver & 0xff00) >> 8, pci_ver & 0xff); + fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base); + fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base); + } } diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 5f198eb305..88c8e65930 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 488e078467..6e3cdddaed 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -50,8 +50,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 7d98870e3f..2b57703b2e 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index b2a23c0c9e..94a51439a0 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -40,8 +40,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), - SET_DMA_LIODN(1, 196), - SET_DMA_LIODN(2, 197), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 196), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 197), SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index b5d787c8e7..0f292cf5a8 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 990f179491..98a568fb10 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -42,30 +42,30 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197), - SET_DMA_LIODN(1, 193), - SET_DMA_LIODN(2, 194), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 193), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 194), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN struct liodn_id_table fman1_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(1, 0, 6), - SET_FMAN_RX_1G_LIODN(1, 1, 7), - SET_FMAN_RX_1G_LIODN(1, 2, 8), - SET_FMAN_RX_1G_LIODN(1, 3, 9), - SET_FMAN_RX_1G_LIODN(1, 4, 10), - SET_FMAN_RX_10G_LIODN(1, 0, 11), + SET_FMAN_RX_1G_LIODN(1, 0, 11), + SET_FMAN_RX_1G_LIODN(1, 1, 12), + SET_FMAN_RX_1G_LIODN(1, 2, 13), + SET_FMAN_RX_1G_LIODN(1, 3, 14), + SET_FMAN_RX_1G_LIODN(1, 4, 15), + SET_FMAN_RX_10G_LIODN(1, 0, 16), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) struct liodn_id_table fman2_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(2, 0, 12), - SET_FMAN_RX_1G_LIODN(2, 1, 13), - SET_FMAN_RX_1G_LIODN(2, 2, 14), - SET_FMAN_RX_1G_LIODN(2, 3, 15), - SET_FMAN_RX_1G_LIODN(2, 4, 16), - SET_FMAN_RX_10G_LIODN(2, 0, 17), + SET_FMAN_RX_1G_LIODN(2, 0, 17), + SET_FMAN_RX_1G_LIODN(2, 1, 18), + SET_FMAN_RX_1G_LIODN(2, 2, 19), + SET_FMAN_RX_1G_LIODN(2, 3, 20), + SET_FMAN_RX_1G_LIODN(2, 4, 21), + SET_FMAN_RX_10G_LIODN(2, 0, 22), }; int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); #endif diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 98815f8e1e..ec3b2924b9 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -14,9 +14,46 @@ #include #include +#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE) +#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE) +static void inhibit_portals(void __iomem *addr, int max_portals, + int arch_max_portals, int portal_cinh_size) +{ + uint32_t val; + int i; + + /* arch_max_portals is the maximum based on memory size. This includes + * the reserved memory in the SoC. max_portals the number of physical + * portals in the SoC */ + if (max_portals > arch_max_portals) { + printf("ERROR: portal config error\n"); + max_portals = arch_max_portals; + } + + for (i = 0; i < max_portals; i++) { + out_be32(addr, -1); + val = in_be32(addr); + if (!val) { + printf("ERROR: Stopped after %d portals\n", i); + goto done; + } + addr += portal_cinh_size; + } +#ifdef DEBUG + printf("Cleared %d portals\n", i); +#endif +done: + + return; +} + void setup_portals(void) { ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; + void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE + + CONFIG_SYS_BMAN_SWP_ISDR_REG; + void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE + + CONFIG_SYS_QMAN_SWP_ISDR_REG; #ifdef CONFIG_FSL_CORENET int i; @@ -38,6 +75,12 @@ void setup_portals(void) out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); #endif out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); + + /* Change default state of BMan ISDR portals to all 1s */ + inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, + CONFIG_SYS_BMAN_SP_CINH_SIZE); + inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, + CONFIG_SYS_QMAN_SP_CINH_SIZE); } /* Update portal containter to match LAW setup of portal in phy map */ diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index 76c60da420..d2825ec36e 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -12,7 +12,7 @@ #include "asm/io.h" #include "asm/immap_85xx.h" -#if defined(CONFIG_QE) +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) #define NUM_OF_PINS 32 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) { diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 15bbbc15aa..a2c0ad4244 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -10,8 +10,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include @@ -226,6 +224,21 @@ __secondary_start_page: 2: #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in + * write shadow mode. This code should run after other code setting + * DCWS. + */ + mfspr r3,L1CSR2 + andis. r3,r3,(L1CSR2_DCWS)@h + beq 1f + mfspr r3, SPRN_HDBCR0 + oris r3, r3, 0x8000 + mtspr SPRN_HDBCR0, r3 +1: +#endif + #ifdef CONFIG_BACKSIDE_L2_CACHE /* skip L2 setup on P2040/P2040E as they have no L2 */ mfspr r3,SPRN_SVR @@ -392,9 +405,6 @@ __second_half_boot_page: bne 3b isync - /* setup IVORs to match fixed offsets */ -#include "fixed_ivor.S" - /* get the upper bits of the addr */ lwz r11,ENTRY_ADDR_UPPER(r10) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f093960fe7..7e698730f3 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -18,9 +18,13 @@ DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 +#endif /* --------------------------------------------------------------- */ -void get_sys_info (sys_info_t * sysInfo) +void get_sys_info(sys_info_t *sys_info) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_FSL_IFC @@ -30,6 +34,10 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; +#endif + __maybe_unused u32 svr; const u8 core_cplx_PLL[16] = { [ 0] = 0, /* CC1 PPL / 1 */ @@ -46,7 +54,7 @@ void get_sys_info (sys_info_t * sysInfo) [14] = 3, /* CC4 PPL / 4 */ }; - const u8 core_cplx_PLL_div[16] = { + const u8 core_cplx_pll_div[16] = { [ 0] = 1, /* CC1 PPL / 1 */ [ 1] = 2, /* CC1 PPL / 2 */ [ 2] = 4, /* CC1 PPL / 4 */ @@ -60,163 +68,250 @@ void get_sys_info (sys_info_t * sysInfo) [13] = 2, /* CC4 PPL / 2 */ [14] = 4, /* CC4 PPL / 4 */ }; - uint i, freqCC_PLL[6], rcw_tmp; - uint ratio[6]; + uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) + uint rcw_tmp; +#endif + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; - sysInfo->freqSystemBus = sysclk; + sys_info->freq_systembus = sysclk; +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + uint ddr_refclk_sel; + unsigned int porsr1_sys_clk; + porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT + & FSL_DCFG_PORSR1_SYSCLK_MASK; + if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) + sys_info->diff_sysclk = 1; + else + sys_info->diff_sysclk = 0; + + /* + * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS + * are driven by separate DDR Refclock or single source + * differential clock. + */ + ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; + /* + * For single source clocking, both ddrclock and sysclock + * are driven by differential sysclock. + */ + if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) + sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; + else +#endif #ifdef CONFIG_DDR_CLK_FREQ - sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else - sysInfo->freqDDRBus = sysclk; + sys_info->freq_ddrbus = sysclk; #endif - sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + if (mem_pll_rat == 0) { + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + } +#endif + /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of + * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 + * it uses 6. + * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 + */ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) + svr = get_svr(); + switch (SVR_SOC_VER(svr)) { + case SVR_T4240: + case SVR_T4160: + case SVR_T4120: + case SVR_T4080: + if (SVR_MAJ(svr) >= 2) + mem_pll_rat *= 2; + break; + case SVR_T2080: + case SVR_T2081: + if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1)) + mem_pll_rat *= 2; + break; + default: + break; + } +#endif if (mem_pll_rat > 2) - sysInfo->freqDDRBus *= mem_pll_rat; + sys_info->freq_ddrbus *= mem_pll_rat; else - sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat; - - ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; - ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; - ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; - ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; - ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f; - ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f; - for (i = 0; i < 6; i++) { + sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; + + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; if (ratio[i] > 4) - freqCC_PLL[i] = sysclk * ratio[i]; + freq_c_pll[i] = sysclk * ratio[i]; else - freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* + * As per CHASSIS2 architeture total 12 clusters are posible and * Each cluster has up to 4 cores, sharing the same PLL selection. - * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are - * cluster group A, feeding cores on cluster 1 and cluster 2. - * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3 - * and cluster 4 if existing. + * The cluster clock assignment is SoC defined. + * + * Total 4 clock groups are possible with 3 PLLs each. + * as per array indices, clock group A has 0, 1, 2 numbered PLLs & + * clock group B has 3, 4, 6 and so on. + * + * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster + * depends upon the SoC architeture. Same applies to other + * clock groups and clusters. + * */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { int cluster = fsl_qoriq_core_to_cluster(cpu); u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; - if (cplx_pll > 3) - printf("Unsupported architecture configuration" - " in function %s\n", __func__); - cplx_pll += (cluster / 2) * 3; - sysInfo->freqProcessor[cpu] = - freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; + cplx_pll += cc_group[cluster] - 1; + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#ifdef CONFIG_PPC_B4860 +#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ + defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#define FM1_CLK_SEL 0x00000007 +#define FM1_CLK_SHIFT 0 #else #define PME_CLK_SEL 0xe0000000 #define PME_CLK_SHIFT 29 #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 #endif +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) + rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; +#else rcw_tmp = in_be32(&gur->rcwsr[7]); +#endif +#endif #ifdef CONFIG_SYS_DPAA_PME +#ifndef CONFIG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: - sysInfo->freqPME = freqCC_PLL[0]; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; break; case 2: - sysInfo->freqPME = freqCC_PLL[0] / 2; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; break; case 3: - sysInfo->freqPME = freqCC_PLL[0] / 3; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; break; case 4: - sysInfo->freqPME = freqCC_PLL[0] / 4; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; break; case 6: - sysInfo->freqPME = freqCC_PLL[1] / 2; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; break; case 7: - sysInfo->freqPME = freqCC_PLL[1] / 3; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; break; default: printf("Error: Unknown PME clock select!\n"); case 0: - sysInfo->freqPME = sysInfo->freqSystemBus / 2; + sys_info->freq_pme = sys_info->freq_systembus / 2; break; } +#else + sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; + +#endif #endif #ifdef CONFIG_SYS_DPAA_QBMAN - sysInfo->freqQMAN = sysInfo->freqSystemBus / 2; +#ifndef CONFIG_QBMAN_CLK_DIV +#define CONFIG_QBMAN_CLK_DIV 2 +#endif + sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; #endif #ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: - sysInfo->freqFMan[0] = freqCC_PLL[3]; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; break; case 2: - sysInfo->freqFMan[0] = freqCC_PLL[3] / 2; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; break; case 3: - sysInfo->freqFMan[0] = freqCC_PLL[3] / 3; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; break; case 4: - sysInfo->freqFMan[0] = freqCC_PLL[3] / 4; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; break; case 5: - sysInfo->freqFMan[0] = sysInfo->freqSystemBus; + sys_info->freq_fman[0] = sys_info->freq_systembus; break; case 6: - sysInfo->freqFMan[0] = freqCC_PLL[4] / 2; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; break; case 7: - sysInfo->freqFMan[0] = freqCC_PLL[4] / 3; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; break; default: printf("Error: Unknown FMan1 clock select!\n"); case 0: - sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + sys_info->freq_fman[0] = sys_info->freq_systembus / 2; break; } #if (CONFIG_SYS_NUM_FMAN) == 2 +#ifdef CONFIG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { case 1: - sysInfo->freqFMan[1] = freqCC_PLL[4]; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; break; case 2: - sysInfo->freqFMan[1] = freqCC_PLL[4] / 2; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; break; case 3: - sysInfo->freqFMan[1] = freqCC_PLL[4] / 3; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; break; case 4: - sysInfo->freqFMan[1] = freqCC_PLL[4] / 4; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; + break; + case 5: + sys_info->freq_fman[1] = sys_info->freq_systembus; break; case 6: - sysInfo->freqFMan[1] = freqCC_PLL[3] / 2; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; break; case 7: - sysInfo->freqFMan[1] = freqCC_PLL[3] / 3; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; break; default: printf("Error: Unknown FMan2 clock select!\n"); case 0: - sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + sys_info->freq_fman[1] = sys_info->freq_systembus / 2; break; } +#endif #endif /* CONFIG_SYS_NUM_FMAN == 2 */ -#endif /* CONFIG_SYS_DPAA_FMAN */ +#else + sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; +#endif +#endif #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ @@ -225,8 +320,8 @@ void get_sys_info (sys_info_t * sysInfo) & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; - sysInfo->freqProcessor[cpu] = - freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 @@ -246,43 +341,47 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_SYS_DPAA_PME if (rcw_tmp & PME_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; + sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; else - sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; + sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; } else { - sysInfo->freqPME = sysInfo->freqSystemBus / 2; + sys_info->freq_pme = sys_info->freq_systembus / 2; } #endif #ifdef CONFIG_SYS_DPAA_FMAN if (rcw_tmp & FM1_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; + sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; else - sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; + sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; } else { - sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + sys_info->freq_fman[0] = sys_info->freq_systembus / 2; } #if (CONFIG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; + sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; else - sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; + sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; } else { - sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + sys_info->freq_fman[1] = sys_info->freq_systembus / 2; } #endif #endif #ifdef CONFIG_SYS_DPAA_QBMAN - sysInfo->freqQMAN = sysInfo->freqSystemBus / 2; + sys_info->freq_qman = sys_info->freq_systembus / 2; #endif #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#ifdef CONFIG_U_QE + sys_info->freq_qe = sys_info->freq_systembus / 2; +#endif + #else /* CONFIG_FSL_CORENET */ - uint plat_ratio, e500_ratio, half_freqSystemBus; + uint plat_ratio, e500_ratio, half_freq_systembus; int i; #ifdef CONFIG_QE __maybe_unused u32 qe_ratio; @@ -290,40 +389,40 @@ void get_sys_info (sys_info_t * sysInfo) plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; /* Divide before multiply to avoid integer * overflow for processor speeds above 2GHz */ - half_freqSystemBus = sysInfo->freqSystemBus/2; + half_freq_systembus = sys_info->freq_systembus/2; for (i = 0; i < cpu_numcores(); i++) { e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; - sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; + sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; } - /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ - sysInfo->freqDDRBus = sysInfo->freqSystemBus; + /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ + sys_info->freq_ddrbus = sys_info->freq_systembus; #ifdef CONFIG_DDR_CLK_FREQ { u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; if (ddr_ratio != 0x7) - sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif #ifdef CONFIG_QE #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) - sysInfo->freqQE = sysInfo->freqSystemBus; + sys_info->freq_qe = sys_info->freq_systembus; #else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; - sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; + sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif #endif #ifdef CONFIG_SYS_DPAA_FMAN - sysInfo->freqFMan[0] = sysInfo->freqSystemBus; + sys_info->freq_fman[0] = sys_info->freq_systembus; #endif #endif /* CONFIG_FSL_CORENET */ @@ -350,18 +449,18 @@ void get_sys_info (sys_info_t * sysInfo) */ lcrr_div *= 2; #endif - sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div; + sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; } else { /* In case anyone cares what the unknown value is */ - sysInfo->freqLocalBus = lcrr_div; + sys_info->freq_localbus = lcrr_div; } #endif #if defined(CONFIG_FSL_IFC) - ccr = in_be32(&ifc_regs->ifc_ccr); + ccr = ifc_in32(&ifc_regs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / ccr; #endif } @@ -382,13 +481,13 @@ int get_clocks (void) dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; #endif get_sys_info (&sys_info); - gd->cpu_clk = sys_info.freqProcessor[0]; - gd->bus_clk = sys_info.freqSystemBus; - gd->mem_clk = sys_info.freqDDRBus; - gd->arch.lbc_clk = sys_info.freqLocalBus; + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + gd->arch.lbc_clk = sys_info.freq_localbus; #ifdef CONFIG_QE - gd->arch.qe_clk = sys_info.freqQE; + gd->arch.qe_clk = sys_info.freq_qe; gd->arch.brg_clk = gd->arch.qe_clk / 2; #endif /* @@ -399,8 +498,9 @@ int get_clocks (void) * AN2919. */ #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) - gd->arch.i2c1_clk = sys_info.freqSystemBus; + defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ + defined(CONFIG_P1022) + gd->arch.i2c1_clk = sys_info.freq_systembus; #elif defined(CONFIG_MPC8544) /* * On the 8544, the I2C clock is the same as the SEC clock. This can be @@ -410,12 +510,12 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->arch.i2c1_clk = sys_info.freqSystemBus / 3; + gd->arch.i2c1_clk = sys_info.freq_systembus / 3; else - gd->arch.i2c1_clk = sys_info.freqSystemBus / 2; + gd->arch.i2c1_clk = sys_info.freq_systembus / 2; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ - gd->arch.i2c1_clk = sys_info.freqSystemBus / 2; + gd->arch.i2c1_clk = sys_info.freq_systembus / 2; #endif gd->arch.i2c2_clk = gd->arch.i2c1_clk; @@ -429,7 +529,7 @@ int get_clocks (void) #endif /* defined(CONFIG_FSL_ESDHC) */ #if defined(CONFIG_CPM2) - gd->arch.vco_out = 2*sys_info.freqSystemBus; + gd->arch.vco_out = 2*sys_info.freq_systembus; gd->arch.cpm_clk = gd->arch.vco_out / 2; gd->arch.scc_clk = gd->arch.vco_out / 4; gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 199b33e3bd..cc45f715e8 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -7,12 +7,12 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; -void cpu_init_f(void) +ulong cpu_init_f(void) { #ifdef CONFIG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; @@ -27,6 +27,8 @@ void cpu_init_f(void) out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); #endif + + return 0; } #ifndef CONFIG_SYS_FSL_TBCLK_DIV diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index cfc3a60d2f..d8c9fb6b28 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -2,7 +2,7 @@ * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards @@ -17,8 +17,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include @@ -28,12 +26,15 @@ #undef MSR_KERNEL #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ +#define LAW_EN 0x80000000 + #if defined(CONFIG_NAND_SPL) || \ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) #define MINIMAL_SPL #endif -#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \ + !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define NOR_BOOT #endif @@ -79,6 +80,13 @@ _start_e500: li r1,MSR_DE mtmsr r1 + /* + * If we got an ePAPR device tree pointer passed in as r3, we need that + * later in cpu_init_early_f(). Save it to a safe register before we + * clobber it so that we can fetch it from there later. + */ + mr r24, r3 + #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 mfspr r3,SPRN_SVR rlwinm r3,r3,0,0xff @@ -107,8 +115,17 @@ _start_e500: isync 2: #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + msync + isync + mfspr r3, SPRN_HDBCR0 + oris r3, r3, 0x0080 + mtspr SPRN_HDBCR0, r3 +#endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) + +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ + !defined(CONFIG_E6500) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later * as part of it's normal flow @@ -297,7 +314,7 @@ l2_disabled: #endif mtspr HID0,r0 -#ifndef CONFIG_E500MC +#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500) li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mfspr r3,PVR andi. r3,r3, 0xff @@ -453,7 +470,8 @@ nexti: mflr r1 /* R1 = our PC */ 2: cmpw r3, r4 blt 1b -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ + !defined(CONFIG_SECURE_BOOT) /* * TLB entry for debuggging in AS1 * Create temporary TLB entry in AS0 to handle debug exception @@ -474,12 +492,6 @@ nexti: mflr r1 /* R1 = our PC */ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 -#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 #else /* * TLB entry is created for IVPR + IVOR15 to map on valid OP code address @@ -567,7 +579,6 @@ infinite_debug_loop: #ifdef CONFIG_FSL_CORENET #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) -#define LAW_EN 0x80000000 #define LAW_SIZE_4K 0xb #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) #define CCSRAR_C 0x80000000 /* Commit */ @@ -690,7 +701,7 @@ delete_temp_tlbs: #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: /* * Create a TLB for the MMR location of CCSR @@ -877,7 +888,11 @@ delete_ccsr_l2_tlb: erratum_set_dcsr 0xb0008 0x00900000 erratum_set_dcsr 0xb0e40 0xe00a0000 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY +#ifdef CONFIG_RAMBOOT_PBL + erratum_set_ccsr 0x10f00 0x495e5000 +#else erratum_set_ccsr 0x10f00 0x415e5000 +#endif erratum_set_ccsr 0x11f00 0x415e5000 /* Make temp mapping uncacheable again, if it was initially */ @@ -1131,6 +1146,10 @@ _start_cont: mr r1,r3 /* Transfer to SP(r1) */ GET_GOT + + /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */ + mr r3, r24 + bl cpu_init_early_f /* switch back to AS = 0 */ @@ -1139,7 +1158,7 @@ _start_cont: mtmsr r3 isync - bl cpu_init_f + bl cpu_init_f /* return boot_flag for calling board_init_f */ bl board_init_f isync @@ -1633,6 +1652,7 @@ relocate_code: mr r10,r5 /* Save copy of Destination Address */ GET_GOT +#ifndef CONFIG_SPL_SKIP_RELOCATE mr r3,r5 /* Destination Address */ lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4,r4,CONFIG_SYS_MONITOR_BASE@l @@ -1723,6 +1743,7 @@ relocate_code: mtlr r0 blr /* NEVER RETURNS! */ +#endif .globl in_ram in_ram: @@ -1954,10 +1975,4 @@ flush_dcache: isync blr - -.globl setup_ivors -setup_ivors: - -#include "fixed_ivor.S" - blr #endif /* !MINIMAL_SPL */ diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c new file mode 100644 index 0000000000..132689b26e --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -0,0 +1,82 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), +}; +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + + SET_SATA_LIODN(1, 555), + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), + /* SET_NEXUS_LIODN(557), -- not yet implemented */ + SET_QE_LIODN(559), + SET_TDM_LIODN(560), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_10G_LIODN(1, 0, 94), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c new file mode 100644 index 0000000000..2ba314a7f6 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -0,0 +1,54 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + + +static u8 serdes_cfg_tbl[][4] = { + [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1}, + [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1}, + [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1}, + [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1}, + [0x46] = {PCIE1, PCIE1, PCIE2, SATA1}, + [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1}, + [0x56] = {PCIE1, PCIE3, PCIE2, SATA1}, + [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1}, + [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, + [0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1}, + [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1}, + [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, + [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC1}, + [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1}, + [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC1}, + [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1}, + [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1}, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < 4; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 32075ce220..80917224b9 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -21,30 +21,9 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(8, 34, 1, 3), SET_QP_INFO(9, 35, 1, 0), SET_QP_INFO(10, 36, 1, 0), - SET_QP_INFO(11, 37, 1, 1), - SET_QP_INFO(12, 38, 1, 1), - SET_QP_INFO(13, 39, 1, 2), - SET_QP_INFO(14, 40, 1, 2), - SET_QP_INFO(15, 41, 1, 3), - SET_QP_INFO(16, 42, 1, 3), - SET_QP_INFO(17, 43, 1, 0), - SET_QP_INFO(18, 44, 1, 0), - SET_QP_INFO(19, 45, 1, 1), - SET_QP_INFO(20, 46, 1, 1), - SET_QP_INFO(21, 47, 1, 2), - SET_QP_INFO(22, 48, 1, 2), - SET_QP_INFO(23, 49, 1, 3), - SET_QP_INFO(24, 50, 1, 3), - SET_QP_INFO(25, 51, 1, 0), }; #endif -struct srio_liodn_id_table srio_liodn_tbl[] = { - SET_SRIO_LIODN_1(1, 307), - SET_SRIO_LIODN_1(2, 387), -}; -int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); - struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(62), @@ -53,19 +32,25 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 552), + SET_PME_LIODN(117), + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 148), + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), /* SET_NEXUS_LIODN(557), -- not yet implemented */ + SET_QE_LIODN(559), + SET_TDM_LIODN(560), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); @@ -77,8 +62,6 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 3, 91), SET_FMAN_RX_1G_LIODN(1, 4, 92), SET_FMAN_RX_1G_LIODN(1, 5, 93), - SET_FMAN_RX_10G_LIODN(1, 0, 94), - SET_FMAN_RX_10G_LIODN(1, 1, 95), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif @@ -94,26 +77,21 @@ struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_RTIC_LIODN_ENTRY(d, 551), SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); -#ifdef CONFIG_SYS_DPAA_RMAN -struct liodn_id_table rman_liodn_tbl[] = { - /* Set RMan block 0-3 liodn offset */ - SET_RMAN_LIODN(0, 678), - SET_RMAN_LIODN(1, 679), - SET_RMAN_LIODN(2, 680), - SET_RMAN_LIODN(3, 681), -}; -int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); -#endif - struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), #endif -#ifdef CONFIG_SYS_DPAA_RMAN - [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c index 94814ac13e..d5dccd5cf2 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -8,68 +8,59 @@ #include #include #include -#include "fsl_corenet2_serdes.h" -static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = { - { /* SerDes 1 */ - [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, - PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE3, PCIE4, SATA1}, + [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE3, SATA2, SATA1}, + [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE2, PCIE2, PCIE2}, [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, PCIE2, PCIE3, PCIE4, SATA1}, [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, - PCIE2, PCIE2, PCIE2, PCIE2}, - [0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2, - PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5}, - [0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2, - PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1}, + [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE3, PCIE4, SATA1}, + [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, - [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, - [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE2, PCIE2, PCIE2}, - [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, - PCIE2, PCIE3, PCIE4, SATA1}, - [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1, - PCIE2, PCIE3, SATA2, SATA1}, + [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2, + PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1}, + [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2, + PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5}, [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, - [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, - [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, - PCIE2, PCIE2, PCIE2, PCIE2}, - }, - { - }, - { - }, - { - }, + [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, + [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, }; - enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) { - return serdes_cfg_tbl[serdes][cfg][lane]; + return serdes_cfg_tbl[cfg][lane]; } int is_serdes_prtcl_valid(int serdes, u32 prtcl) { int i; - if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes])) + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; for (i = 0; i < SRDS_MAX_LANES; i++) { - if (serdes_cfg_tbl[serdes][prtcl][i] != NONE) + if (serdes_cfg_tbl[prtcl][i] != NONE) return 1; } diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c new file mode 100644 index 0000000000..eda7f59da0 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -0,0 +1,144 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), + SET_QP_INFO(11, 37, 1, 1), + SET_QP_INFO(12, 38, 1, 1), + SET_QP_INFO(13, 39, 1, 2), + SET_QP_INFO(14, 40, 1, 2), + SET_QP_INFO(15, 41, 1, 3), + SET_QP_INFO(16, 42, 1, 3), + SET_QP_INFO(17, 43, 1, 0), + SET_QP_INFO(18, 44, 1, 0), +}; +#endif + +#ifdef CONFIG_SYS_SRIO +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_BASE(1, 307), + SET_SRIO_LIODN_BASE(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + +#ifdef CONFIG_FSL_SATA_V2 + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), +#endif + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), + SET_DMA_LIODN(3, "fsl,elo3-dma", 226), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + +#ifdef CONFIG_SYS_PMAN + SET_PMAN_LIODN(1, 513), + SET_PMAN_LIODN(2, 514), + SET_PMAN_LIODN(3, 515), +#endif + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { +#ifdef CONFIG_SYS_DPAA_DCE + [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694), +#endif + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c new file mode 100644 index 0000000000..c65f41d0f8 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -0,0 +1,229 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, + PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE3, PCIE3, PCIE3, PCIE3} }, + {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {} +}; + +#ifndef CONFIG_PPC_T2081 +static const struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, + {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, + {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} }, + {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, + {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, + {} +}; +#endif + +static const struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +#ifndef CONFIG_PPC_T2081 + serdes2_cfg_tbl, +#endif +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index e173cb5f95..470b0800bf 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -64,11 +64,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +#ifdef CONFIG_SYS_SRIO struct srio_liodn_id_table srio_liodn_tbl[] = { - SET_SRIO_LIODN_1(1, 307), - SET_SRIO_LIODN_1(2, 387), + SET_SRIO_LIODN_BASE(1, 307), + SET_SRIO_LIODN_BASE(2, 387), }; int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN @@ -86,13 +88,13 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 555), SET_SATA_LIODN(2, 556), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), @@ -159,10 +161,10 @@ int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); #ifdef CONFIG_SYS_DPAA_RMAN struct liodn_id_table rman_liodn_tbl[] = { /* Set RMan block 0-3 liodn offset */ - SET_RMAN_LIODN(0, 678), - SET_RMAN_LIODN(1, 679), - SET_RMAN_LIODN(2, 680), - SET_RMAN_LIODN(3, 681), + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), }; int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); #endif diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index ed88602c31..74c4c81887 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = { HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {37, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE} }, {38, {NONE, NONE, QSGMII_FM1_B, NONE, NONE, NONE, QSGMII_FM1_A, NONE}}, + {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, + {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, + {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, @@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = { XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -89,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -97,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {37, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, NONE, QSGMII_FM2_A, NONE} }, {38, {NONE, NONE, QSGMII_FM2_B, NONE, - NONE, NONE, QSGMII_FM1_A, NONE}}, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM1_A, NONE}}, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM1_A, NONE}}, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM1_A, NONE}}, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, - NONE, NONE, QSGMII_FM1_A, NONE}}, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, QSGMII_FM1_A, NONE}}, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, QSGMII_FM1_A, NONE}}, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {55, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {56, {XFI_FM1_MAC9, XFI_FM1_MAC10, XFI_FM2_MAC10, XFI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -137,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = { }; static const struct serdes_config serdes3_cfg_tbl[] = { /* SerDes 3 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}}, + {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, + {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, + {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2}}, + {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2}}, + {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, + {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, @@ -161,18 +244,26 @@ static const struct serdes_config serdes3_cfg_tbl[] = { }; static const struct serdes_config serdes4_cfg_tbl[] = { /* SerDes 4 */ + {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} }, {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}}, + {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}}, + {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} }, {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} }, {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} }, {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} }, + {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} }, {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} }, + {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} }, {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} }, {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, @@ -187,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = { HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, + {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {37, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE} }, {38, {NONE, NONE, QSGMII_FM1_B, NONE, NONE, NONE, QSGMII_FM1_A, NONE} }, {} }; static const struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ + {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -225,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, NONE, NONE} }, + {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {37, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, QSGMII_FM1_A, NONE, NONE} }, {38, {NONE, NONE, QSGMII_FM2_B, NONE, NONE, QSGMII_FM1_A, NONE, NONE} }, + {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {55, {NONE, XFI_FM1_MAC10, + XFI_FM2_MAC10, NONE, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {56, {NONE, XFI_FM1_MAC10, XFI_FM2_MAC10, NONE, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -265,22 +418,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = { }; static const struct serdes_config serdes3_cfg_tbl[] = { /* SerDes 3 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, + {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, + {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2} }, + {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2} }, + {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, + {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, @@ -289,12 +454,19 @@ static const struct serdes_config serdes3_cfg_tbl[] = { }; static const struct serdes_config serdes4_cfg_tbl[] = { /* SerDes 4 */ + {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, + {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, + {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, + {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, + {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} }, {} diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index da3c345d6f..8e0508f362 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -24,7 +24,7 @@ void invalidate_tlb(u8 tlb) mtspr(MMUCSR0, 0x2); } -void init_tlbs(void) +__weak void init_tlbs(void) { int i; @@ -39,7 +39,8 @@ void init_tlbs(void) return ; } -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_NAND_SPL) && \ + (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { @@ -235,20 +236,26 @@ void init_addr_map(void) } #endif -unsigned int -setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) +uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, + enum tlb_map_type map_type) { int i; unsigned int tlb_size; - unsigned int wimge = MAS2_M; - unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int wimge; + unsigned int perm; unsigned int max_cam, tsize_mask; - u64 size, memsize = (u64)memsize_in_meg << 20; + if (map_type == TLB_MAP_RAM) { + perm = MAS3_SX|MAS3_SW|MAS3_SR; + wimge = MAS2_M; #ifdef CONFIG_SYS_PPC_DDR_WIMGE - wimge = CONFIG_SYS_PPC_DDR_WIMGE; + wimge = CONFIG_SYS_PPC_DDR_WIMGE; #endif - size = min(memsize, CONFIG_MAX_MEM_MAPPED); + } else { + perm = MAS3_SW|MAS3_SR; + wimge = MAS2_I|MAS2_G; + } + if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { /* Convert (4^max) kB to (2^max) bytes */ max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10; @@ -260,11 +267,11 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) } for (i = 0; size && i < 8; i++) { - int ram_tlb_index = find_free_tlbcam(); + int tlb_index = find_free_tlbcam(); u32 camsize = __ilog2_u64(size) & tsize_mask; - u32 align = __ilog2(ram_tlb_address) & tsize_mask; + u32 align = __ilog2(v_addr) & tsize_mask; - if (ram_tlb_index == -1) + if (tlb_index == -1) break; if (align == -2) align = max_cam; @@ -276,18 +283,33 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) tlb_size = camsize - 10; - set_tlb(1, ram_tlb_address, p_addr, - MAS3_SX|MAS3_SW|MAS3_SR, wimge, - 0, ram_tlb_index, tlb_size, 1); + set_tlb(1, v_addr, p_addr, perm, wimge, + 0, tlb_index, tlb_size, 1); size -= 1ULL << camsize; - memsize -= 1ULL << camsize; - ram_tlb_address += 1UL << camsize; + v_addr += 1UL << camsize; p_addr += 1UL << camsize; } - if (memsize) - print_size(memsize, " left unmapped\n"); + return size; +} + +unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, + unsigned int memsize_in_meg) +{ + unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + u64 memsize = (u64)memsize_in_meg << 20; + u64 size; + + size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); + size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); + + if (size || memsize > CONFIG_MAX_MEM_MAPPED) { + print_size(memsize > CONFIG_MAX_MEM_MAPPED ? + memsize - CONFIG_MAX_MEM_MAPPED + size : size, + " left unmapped\n"); + } + return memsize_in_meg; } diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index c9adc71af8..24adbc3078 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -13,7 +13,7 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -35,7 +35,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index df3b0f9168..f933b21944 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -4,6 +4,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include "config.h" + +#ifndef CONFIG_SYS_MONITOR_LEN +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ @@ -76,7 +82,7 @@ SECTIONS KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) } :text = 0xffff - . = ADDR(.text) + 0x80000; + . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; __bss_start = .; .bss (NOLOAD) : diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 844f7e94f1..b83c55388c 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -7,7 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "config.h" /* CONFIG_BOARDDIR */ +#include "config.h" OUTPUT_ARCH(powerpc) SECTIONS diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 08188d75e5..5ae7b3eedb 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -7,7 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "config.h" /* CONFIG_BOARDDIR */ +#include "config.h" OUTPUT_ARCH(powerpc) #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC @@ -44,32 +44,59 @@ SECTIONS } _edata = .; + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + . = ALIGN(8); __init_begin = .; __init_end = .; -/* FIXME for non-NAND SPL */ +#ifdef CONFIG_SPL_SKIP_RELOCATE + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif + +/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg ADDR(.text) - 0x1000 : + { + KEEP(*(.bootpg)) + } :text = 0xffff +#else #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : +#ifndef BOOT_PAGE_OFFSET +#define BOOT_PAGE_OFFSET 0x1000 +#endif + .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } +#ifndef RESET_VECTOR_OFFSET #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#endif #elif defined(CONFIG_FSL_ELBC) #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ #else #error unknown NAND controller #endif -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(*(.bootpg)) - } :text = 0xffff -#else .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff #endif +#ifndef CONFIG_SPL_SKIP_RELOCATE /* * Make sure that the bss segment isn't linked at 0x0, otherwise its * address won't be updated during relocation fixups. @@ -84,4 +111,5 @@ SECTIONS } . = ALIGN(4); __bss_end = .; +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 2af4c80f60..2cf0b25952 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "config.h" /* CONFIG_BOARDDIR */ +#include "config.h" #ifdef CONFIG_RESET_VECTOR_ADDRESS #define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS @@ -12,7 +12,12 @@ #define RESET_VECTOR_ADDRESS 0xfffffffc #endif +#ifndef CONFIG_SYS_MONITOR_LEN +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + OUTPUT_ARCH(powerpc) +ENTRY(_start_e500) PHDRS { @@ -84,7 +89,7 @@ SECTIONS { KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) } :text = 0xffff - . = ADDR(.text) + 0x80000; + . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; #else .bootpg RESET_VECTOR_ADDRESS - 0xffc : { diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig new file mode 100644 index 0000000000..14e8b1aa66 --- /dev/null +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -0,0 +1,29 @@ +menu "mpc86xx CPU" + depends on MPC86xx + +config SYS_CPU + default "mpc86xx" + +choice + prompt "Target select" + +config TARGET_SBC8641D + bool "Support sbc8641d" + +config TARGET_MPC8610HPCD + bool "Support MPC8610HPCD" + +config TARGET_MPC8641HPCN + bool "Support MPC8641HPCN" + +config TARGET_XPEDITE517X + bool "Support xpedite517x" + +endchoice + +source "board/freescale/mpc8610hpcd/Kconfig" +source "board/freescale/mpc8641hpcn/Kconfig" +source "board/sbc8641d/Kconfig" +source "board/xes/xpedite517x/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile index 04271b0f0c..0f790b0efc 100644 --- a/arch/powerpc/cpu/mpc86xx/Makefile +++ b/arch/powerpc/cpu/mpc86xx/Makefile @@ -8,42 +8,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -SSTART = start.o -CSTART = traps.o - -SOBJS-y += cache.o -SOBJS-$(CONFIG_MP) += release.o - -COBJS-y += cpu.o -COBJS-y += cpu_init.o -# 8610 & 8641 are identical w/regards to DDR -COBJS-$(CONFIG_MPC8610) += ddr-8641.o -COBJS-$(CONFIG_MPC8641) += ddr-8641.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS-y += interrupts.o -COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_MPC8610) += mpc8610_serdes.o -COBJS-$(CONFIG_MPC8641) += mpc8641_serdes.o -COBJS-y += speed.o - -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(SSTART) $(CSTART)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +extra-y += traps.o + +obj-y += cache.o +obj-$(CONFIG_MP) += release.o + +obj-y += cpu.o +obj-y += cpu_init.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-y += interrupts.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_MPC8610) += mpc8610_serdes.o +obj-$(CONFIG_MPC8641) += mpc8641_serdes.o +obj-y += speed.o diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk index 5dbf6a8472..69a0b96ead 100644 --- a/arch/powerpc/cpu/mpc86xx/config.mk +++ b/arch/powerpc/cpu/mpc86xx/config.mk @@ -5,7 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -ffixed-r2 -mstring -PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float +PLATFORM_CPPFLAGS += -mstring -maltivec -mabi=altivec -msoft-float diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index d6b28dd077..30518544dd 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -72,21 +72,21 @@ checkcpu(void) get_sys_info(&sysinfo); puts("Clock Configuration:\n"); - printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); - printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); + printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor)); + printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); printf(" DDR:%-4s MHz (%s MT/s data rate), ", - strmhz(buf1, sysinfo.freqSystemBus / 2), - strmhz(buf2, sysinfo.freqSystemBus)); + strmhz(buf1, sysinfo.freq_systembus / 2), + strmhz(buf2, sysinfo.freq_systembus)); - if (sysinfo.freqLocalBus > LCRR_CLKDIV) { - printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); + if (sysinfo.freq_localbus > LCRR_CLKDIV) { + printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", - sysinfo.freqLocalBus); + sysinfo.freq_localbus); } - puts("L1: D-cache 32 KB enabled\n"); - puts(" I-cache 32 KB enabled\n"); + puts("L1: D-cache 32 KiB enabled\n"); + puts(" I-cache 32 KiB enabled\n"); puts("L2: "); if (get_l2cr() & 0x80000000) { @@ -95,7 +95,7 @@ checkcpu(void) #elif defined(CONFIG_MPC8641) puts("512"); #endif - puts(" KB enabled\n"); + puts(" KiB enabled\n"); } else { puts("Disabled\n"); } @@ -131,7 +131,7 @@ get_tbclk(void) sys_info_t sys_info; get_sys_info(&sys_info); - return (sys_info.freqSystemBus + 3L) / 4L; + return (sys_info.freq_systembus + 3L) / 4L; } diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c deleted file mode 100644 index 92ba26dc8e..0000000000 --- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num) -{ - unsigned int i; - volatile ccsr_ddr_t *ddr; - - switch (ctrl_num) { - case 0: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - break; - case 1: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - break; - default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - debug("before go\n"); - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - /* - * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done - */ - while (in_be32(&ddr->sdram_cfg_2) & 0x10) { - udelay(10000); /* throttle polling rate */ - } -} diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c index ea366ab9e4..5abe6f0bf2 100644 --- a/arch/powerpc/cpu/mpc86xx/speed.c +++ b/arch/powerpc/cpu/mpc86xx/speed.c @@ -6,7 +6,7 @@ * (C) Copyright 2000-2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; /* used in some defintiions of CONFIG_SYS_CLK_FREQ */ extern unsigned long get_board_sys_clk(unsigned long dummy); -void get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -31,7 +31,7 @@ void get_sys_info(sys_info_t *sysInfo) switch (plat_ratio) { case 0x0: - sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; + sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ; break; case 0x02: case 0x03: @@ -43,10 +43,10 @@ void get_sys_info(sys_info_t *sysInfo) case 0x0a: case 0x0c: case 0x10: - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; break; default: - sysInfo->freqSystemBus = 0; + sys_info->freq_systembus = 0; break; } @@ -55,25 +55,26 @@ void get_sys_info(sys_info_t *sysInfo) switch (e600_ratio) { case 0x10: - sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; + sys_info->freq_processor = 2 * sys_info->freq_systembus; break; case 0x19: - sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2; + sys_info->freq_processor = 5 * sys_info->freq_systembus / 2; break; case 0x20: - sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; + sys_info->freq_processor = 3 * sys_info->freq_systembus; break; case 0x39: - sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2; + sys_info->freq_processor = 7 * sys_info->freq_systembus / 2; break; case 0x28: - sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus; + sys_info->freq_processor = 4 * sys_info->freq_systembus; break; case 0x1d: - sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2; + sys_info->freq_processor = 9 * sys_info->freq_systembus / 2; break; default: - sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; + sys_info->freq_processor = e600_ratio + + sys_info->freq_systembus; break; } @@ -84,10 +85,11 @@ void get_sys_info(sys_info_t *sysInfo) lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV; #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { - sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2); + sys_info->freq_localbus = sys_info->freq_systembus + / (lcrr_div * 2); } else { /* In case anyone cares what the unknown value is */ - sysInfo->freqLocalBus = lcrr_div; + sys_info->freq_localbus = lcrr_div; } } @@ -102,9 +104,9 @@ int get_clocks(void) sys_info_t sys_info; get_sys_info(&sys_info); - gd->cpu_clk = sys_info.freqProcessor; - gd->bus_clk = sys_info.freqSystemBus; - gd->arch.lbc_clk = sys_info.freqLocalBus; + gd->cpu_clk = sys_info.freq_processor; + gd->bus_clk = sys_info.freq_systembus; + gd->arch.lbc_clk = sys_info.freq_localbus; /* * The base clock for I2C depends on the actual SOC. Unfortunately, @@ -114,9 +116,9 @@ int get_clocks(void) * AN2919. */ #ifdef CONFIG_MPC8610 - gd->arch.i2c1_clk = sys_info.freqSystemBus; + gd->arch.i2c1_clk = sys_info.freq_systembus; #else - gd->arch.i2c1_clk = sys_info.freqSystemBus / 2; + gd->arch.i2c1_clk = sys_info.freq_systembus / 2; #endif gd->arch.i2c2_clk = gd->arch.i2c1_clk; @@ -138,7 +140,7 @@ ulong get_bus_freq(ulong dummy) sys_info_t sys_info; get_sys_info(&sys_info); - val = sys_info.freqSystemBus; + val = sys_info.freq_systembus; return val; } diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S index e33672a3a0..ec5f4a756a 100644 --- a/arch/powerpc/cpu/mpc86xx/start.S +++ b/arch/powerpc/cpu/mpc86xx/start.S @@ -273,6 +273,7 @@ diag_done: /* bl l2cache_enable */ /* run 1st part of board init code (from Flash) */ + li r3, 0 /* clear boot_flag for calling board_init_f */ bl board_init_f sync diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c index 0b7ea3b184..92fb537453 100644 --- a/arch/powerpc/cpu/mpc86xx/traps.c +++ b/arch/powerpc/cpu/mpc86xx/traps.c @@ -29,7 +29,6 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -extern ulong get_effective_memsize(void); #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig new file mode 100644 index 0000000000..e8bcbe98a1 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -0,0 +1,50 @@ +menu "mpc8xx CPU" + depends on 8xx + +config SYS_CPU + default "mpc8xx" + +choice + prompt "Target select" + +config TARGET_TQM823L + bool "Support TQM823L" + +config TARGET_TQM823M + bool "Support TQM823M" + +config TARGET_TQM850L + bool "Support TQM850L" + +config TARGET_TQM850M + bool "Support TQM850M" + +config TARGET_TQM855L + bool "Support TQM855L" + +config TARGET_TQM855M + bool "Support TQM855M" + +config TARGET_TQM860L + bool "Support TQM860L" + +config TARGET_TQM860M + bool "Support TQM860M" + +config TARGET_TQM862L + bool "Support TQM862L" + +config TARGET_TQM862M + bool "Support TQM862M" + +config TARGET_TQM866M + bool "Support TQM866M" + +config TARGET_TQM885D + bool "Support TQM885D" + +endchoice + +source "board/tqc/tqm8xx/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index 71d5e302ca..f83fd5ecf4 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -5,45 +5,23 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -# CFLAGS += -DET_DEBUG - -LIB = $(obj)lib$(CPU).o - -SSTART-y += start.o -CSTART-y += traps.o -COBJS-y += bedbug_860.o -COBJS-y += commproc.o -COBJS-y += cpu.o -COBJS-y += cpu_init.o -COBJS-y += fec.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS-y += i2c.o -COBJS-y += interrupts.o -COBJS-y += scc.o -COBJS-y += serial.o -COBJS-y += speed.o -COBJS-y += spi.o -COBJS-y += upatch.o -COBJS-y += video.o -SOBJS-y += kgdb.o -SOBJS-y += plprcr_write.o - -SRCS := $(SSTART-y:.o=.S) $(CSTART-y:.o=.c) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(SSTART-y) $(CSTART-y)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +# ccflags-y += -DET_DEBUG + +extra-y += start.o +extra-y += traps.o +obj-y += bedbug_860.o +obj-y += commproc.o +obj-y += cpu.o +obj-y += cpu_init.o +obj-y += fec.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-y += i2c.o +obj-y += interrupts.o +obj-y += scc.o +obj-y += serial.o +obj-y += speed.o +obj-y += spi.o +obj-y += upatch.o +obj-y += video.o +obj-y += kgdb.o +obj-y += plprcr_write.o diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk index c04e7338c8..485e43d2de 100644 --- a/arch/powerpc/cpu/mpc8xx/config.mk +++ b/arch/powerpc/cpu/mpc8xx/config.mk @@ -5,6 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float +PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 1550045e6c..105be9ccc7 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -97,14 +97,8 @@ static int check_CPU (long clock, uint pvr, uint immr) pre = 'M'; m = 1; if (id_str == NULL) id_str = -# if defined(CONFIG_MPC852T) - "PC852T"; -# elif defined(CONFIG_MPC859T) +# if defined(CONFIG_MPC859T) "PC859T"; -# elif defined(CONFIG_MPC859DSL) - "PC859DSL"; -# elif defined(CONFIG_MPC866T) - "PC866T"; # else "PC866x"; /* Unknown chip from MPC866 family */ # endif @@ -136,10 +130,8 @@ static int check_CPU (long clock, uint pvr, uint immr) #else printf (" at %s MHz: ", strmhz (buf, clock)); #endif - printf ("%u kB I-Cache %u kB D-Cache", - checkicache () >> 10, - checkdcache () >> 10 - ); + print_size(checkicache(), " I-Cache "); + print_size(checkdcache(), " D-Cache"); /* do we have a FEC (860T/P or 852/859/866/885)? */ @@ -204,10 +196,10 @@ static int check_CPU (long clock, uint pvr, uint immr) printf ("unknown MPC857 (0x%08x)", k); #endif - printf (" at %s MHz:", strmhz (buf, clock)); + printf(" at %s MHz: ", strmhz(buf, clock)); - printf (" %u kB I-Cache", checkicache () >> 10); - printf (" %u kB D-Cache", checkdcache () >> 10); + print_size(checkicache(), " I-Cache "); + print_size(checkdcache(), " D-Cache"); /* lets check and see if we're running on a 862T (or P?) */ @@ -265,10 +257,10 @@ static int check_CPU (long clock, uint pvr, uint immr) if (suf) printf ("PPC823ZTnn%s", suf); - printf (" at %s MHz:", strmhz (buf, clock)); + printf(" at %s MHz: ", strmhz(buf, clock)); - printf (" %u kB I-Cache", checkicache () >> 10); - printf (" %u kB D-Cache", checkdcache () >> 10); + print_size(checkicache(), " I-Cache "); + print_size(checkdcache(), " D-Cache"); /* lets check and see if we're running on a 860T (or P?) */ @@ -321,10 +313,10 @@ static int check_CPU (long clock, uint pvr, uint immr) default: printf ("unknown MPC850 (0x%08x)", k); } - printf (" at %s MHz:", strmhz (buf, clock)); + printf(" at %s MHz: ", strmhz(buf, clock)); - printf (" %u kB I-Cache", checkicache () >> 10); - printf (" %u kB D-Cache", checkdcache () >> 10); + print_size(checkicache(), " I-Cache "); + print_size(checkdcache(), " D-Cache"); /* lets check and see if we're running on a 850T (or P?) */ @@ -465,8 +457,6 @@ void upmconfig (uint upm, uint * table, uint size) /* ------------------------------------------------------------------------- */ -#ifndef CONFIG_LWMON - int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong msr, addr; @@ -501,32 +491,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } -#else /* CONFIG_LWMON */ - -/* - * On the LWMON board, the MCLR reset input of the PIC's on the board - * uses a 47K/1n RC combination which has a 47us time constant. The - * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us - * and thus too short to reset the external hardware. So we use the - * watchdog to reset the board. - */ -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - /* prevent triggering the watchdog */ - disable_interrupts (); - - /* make sure the watchdog is running */ - reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); - - /* wait for watchdog reset */ - while (1) {}; - - /* NOTREACHED */ - return 1; -} - -#endif /* CONFIG_LWMON */ - /* ------------------------------------------------------------------------- */ /* @@ -588,42 +552,15 @@ void watchdog_reset (void) } #endif /* CONFIG_WATCHDOG */ -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON) +#if defined(CONFIG_WATCHDOG) void reset_8xx_watchdog (volatile immap_t * immr) { -# if defined(CONFIG_LWMON) - /* - * The LWMON board uses a MAX6301 Watchdog - * with the trigger pin connected to port PA.7 - * - * (The old board version used a MAX706TESA Watchdog, which - * had to be handled exactly the same.) - */ -# define WATCHDOG_BIT 0x0100 - immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ - immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ - immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ - - immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ -# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) - /* - * The KUP4 boards uses a TPS3705 Watchdog - * with the trigger pin connected to port PA.5 - */ -# define WATCHDOG_BIT 0x0400 - immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ - immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ - immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ - - immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ -# else /* * All other boards use the MPC8xx Internal Watchdog */ immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ -# endif /* CONFIG_LWMON */ } #endif /* CONFIG_WATCHDOG */ diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 53f873d1ab..f621d6285c 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -29,12 +29,10 @@ void cpm_load_patch (volatile immap_t * immr); */ void cpu_init_f (volatile immap_t * immr) { -#ifndef CONFIG_MBX volatile memctl8xx_t *memctl = &immr->im_memctl; # ifdef CONFIG_SYS_PLPRCR ulong mfmask; # endif -#endif ulong reg; /* SYPCR - contains watchdog control (11-9) */ @@ -46,11 +44,7 @@ void cpu_init_f (volatile immap_t * immr) #endif /* CONFIG_WATCHDOG */ /* SIUMCR - contains debug pin configuration (11-6) */ -#ifndef CONFIG_SVM_SC8xx immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; -#else - immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; -#endif /* initialize timebase status and control register (11-26) */ /* unlock TBSCRK */ @@ -74,8 +68,6 @@ void cpu_init_f (volatile immap_t * immr) immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; -#ifndef CONFIG_MBX /* MBX board does things different */ - /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF @@ -133,23 +125,6 @@ void cpu_init_f (volatile immap_t * immr) * I owe him a free beer. - wd] */ -#if defined(CONFIG_HERMES) || \ - defined(CONFIG_ICU862) || \ - defined(CONFIG_IP860) || \ - defined(CONFIG_IVML24) || \ - defined(CONFIG_IVMS8) || \ - defined(CONFIG_LWMON) || \ - defined(CONFIG_MHPC) || \ - defined(CONFIG_R360MPI) || \ - defined(CONFIG_RMU) || \ - defined(CONFIG_RPXCLASSIC) || \ - defined(CONFIG_RPXLITE) || \ - defined(CONFIG_SPC1920) || \ - defined(CONFIG_SPD823TS) - - memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; -#endif - #if defined(CONFIG_SYS_OR0_REMAP) memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; #endif @@ -169,10 +144,6 @@ void cpu_init_f (volatile immap_t * immr) memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; #endif -#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */ - memctl->memc_br0 = 0; -#endif - #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; @@ -203,8 +174,6 @@ void cpu_init_f (volatile immap_t * immr) memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif -#endif /* ! CONFIG_MBX */ - /* * Reset CPM */ @@ -213,24 +182,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); -#ifdef CONFIG_MBX - /* - * on the MBX, things are a little bit different: - * - we need to read the VPD to get board information - * - the plprcr is set up dynamically - * - the memory controller is set up dynamically - */ - mbx_init (); -#endif /* CONFIG_MBX */ - -#ifdef CONFIG_RPXCLASSIC - rpxclassic_init (); -#endif - -#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM) - rpxlite_init (); -#endif - #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ /* write config value */ immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index 65dfeabba4..22b8ec752b 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -205,11 +205,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length) j = 0; while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) { @@ -377,26 +373,6 @@ static void fec_pin_init(int fecidx) */ immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; -#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) - { - volatile fec_t *fecp; - - /* - * only two FECs please - */ - if ((unsigned int)fecidx >= 2) - hang(); - - if (fecidx == 0) - fecp = &immr->im_cpm.cp_fec1; - else - fecp = &immr->im_cpm.cp_fec2; - - /* our PHYs are the limit at 2.5 MHz */ - fecp->fec_mii_speed <<= 1; - } -#endif - #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) /* use MDC for MII */ immr->im_ioport.iop_pdpar |= 0x0080; @@ -444,7 +420,7 @@ static void fec_pin_init(int fecidx) #endif /* !CONFIG_RMII */ -#elif !defined(CONFIG_ICU862) +#else /* * Configure all of port D for MII. */ @@ -457,42 +433,8 @@ static void fec_pin_init(int fecidx) immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ else immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ -#else - /* - * Configure port A for MII. - */ - -#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY) - - /* - * On the ICU862 board the MII-MDC pin is routed to PD8 pin - * * of CPU, so for this board we need to configure Utopia and - * * enable PD8 to MII-MDC function - */ - immr->im_ioport.iop_pdpar |= 0x4080; #endif - /* - * Has Utopia been configured? - */ - if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { - /* - * YES - Use MUXED mode for UTOPIA bus. - * This frees Port A for use by MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode &= ~0x80; - } else { - /* - * NO - set SPLIT mode for UTOPIA bus. - * - * This doesn't really effect UTOPIA (which isn't - * enabled anyway) but just tells the 862 - * to use port A for MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode |= 0x80; - } -#endif /* !defined(CONFIG_ICU862) */ - #endif /* CONFIG_ETHER_ON_FEC1 */ } else if (fecidx == 1) { @@ -562,32 +504,6 @@ static int fec_init (struct eth_device *dev, bd_t * bd) (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); int i; - if (efis->ether_index == 0) { -#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */ -#if defined(CONFIG_MPC885ADS) - *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST); -#else - /* configure FADS for fast (FEC) ethernet, half-duplex */ - /* The LXT970 needs about 50ms to recover from reset, so - * wait for it by discovering the PHY before leaving eth_init(). - */ - { - volatile uint *bcsr4 = (volatile uint *) BCSR4; - - *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1)) - | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | - BCSR4_FETHRST); - - /* reset the LXT970 PHY */ - *bcsr4 &= ~BCSR4_FETHRST; - udelay (10); - *bcsr4 |= BCSR4_FETHRST; - udelay (10); - } -#endif /* CONFIG_MPC885ADS */ -#endif /* CONFIG_FADS */ - } - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* the MII interface is connected to FEC1 * so for the miiphy_xxx function to work we must diff --git a/arch/powerpc/cpu/mpc8xx/i2c.c b/arch/powerpc/cpu/mpc8xx/i2c.c index 2f8b1393f2..6146de3875 100644 --- a/arch/powerpc/cpu/mpc8xx/i2c.c +++ b/arch/powerpc/cpu/mpc8xx/i2c.c @@ -17,9 +17,6 @@ #include #include -#ifdef CONFIG_LWMON -#include -#endif DECLARE_GLOBAL_DATA_PTR; @@ -591,10 +588,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) uchar xaddr[4]; int rc; -#ifdef CONFIG_LWMON - WATCHDOG_RESET(); -#endif - xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; xaddr[2] = (addr >> 8) & 0xFF; diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S index ea27d59a6c..e774d1e70a 100644 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ b/arch/powerpc/cpu/mpc8xx/kgdb.S @@ -9,9 +9,6 @@ #include #include -#define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc8xx/plprcr_write.S b/arch/powerpc/cpu/mpc8xx/plprcr_write.S index 923b8dc916..e28292f5e2 100644 --- a/arch/powerpc/cpu/mpc8xx/plprcr_write.S +++ b/arch/powerpc/cpu/mpc8xx/plprcr_write.S @@ -2,7 +2,7 @@ * (C) Copyright 2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 2ef77b4c14..251966b4a0 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -193,23 +193,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; -#if defined(CONFIG_LWMON) - reset_phy(); -#endif - -#ifdef CONFIG_FADS -#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T) - /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */ - *((uint *) BCSR4) &= ~BCSR4_ETHLOOP; - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#else - *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN); - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif -#endif - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]); rxIdx = 0; @@ -459,61 +442,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) immr->im_cpm.cp_pbdir |= PB_ENET_TENA; #else #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined -#endif - -#if defined(CONFIG_ADS) && defined(CONFIG_MPC860) - /* - * Port C is used to control the PHY,MC68160. - */ - immr->im_ioport.iop_pcdir |= - (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); - - immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; - immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif /* MPC860ADS */ - -#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - -#ifdef CONFIG_RPXLITE - *((uchar *) BCSR0) |= BCSR0_ETHEN; -#endif - -#if defined(CONFIG_QS860T) - /* - * PB27=FDE-, set output low for full duplex - * PB26=Link Test Enable, normally high output - */ - immr->im_cpm.cp_pbdir |= 0x00000030; - immr->im_cpm.cp_pbdat |= 0x00000020; - immr->im_cpm.cp_pbdat &= ~0x00000010; -#endif /* QS860T */ - -#ifdef CONFIG_MBX - board_ether_init (); -#endif - -#if defined(CONFIG_NETVIA) -#if defined(PA_ENET_PDN) - immr->im_ioport.iop_papar &= ~PA_ENET_PDN; - immr->im_ioport.iop_padir |= PA_ENET_PDN; - immr->im_ioport.iop_padat |= PA_ENET_PDN; -#elif defined(PB_ENET_PDN) - immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN; - immr->im_cpm.cp_pbdir |= PB_ENET_PDN; - immr->im_cpm.cp_pbdat |= PB_ENET_PDN; -#elif defined(PC_ENET_PDN) - immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN; - immr->im_ioport.iop_pcdir |= PC_ENET_PDN; - immr->im_ioport.iop_pcdat |= PC_ENET_PDN; -#elif defined(PD_ENET_PDN) - immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN; - immr->im_ioport.iop_pddir |= PD_ENET_PDN; - immr->im_ioport.iop_pddat |= PD_ENET_PDN; -#endif #endif /* @@ -523,15 +451,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - /* - * Work around transmit problem with first eth packet - */ -#if defined (CONFIG_FADS) - udelay (10000); /* wait 10 ms */ -#elif defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ -#endif - return 1; } diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index 4e840498d7..af65c969c2 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -173,20 +173,6 @@ static int smc_init (void) # endif #endif -#if defined(CONFIG_FADS) || defined(CONFIG_ADS) - /* Enable RS232 */ -#if defined(CONFIG_8xx_CONS_SMC1) - *((uint *) BCSR1) &= ~BCSR1_RS232EN_1; -#else - *((uint *) BCSR1) &= ~BCSR1_RS232EN_2; -#endif -#endif /* CONFIG_FADS */ - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) - /* Enable Monitor Port Transceiver */ - *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; -#endif /* CONFIG_RPXLITE */ - /* Set the physical address of the host memory buffers in * the buffer descriptors. */ @@ -225,10 +211,6 @@ static int smc_init (void) up->smc_tstate = 0; #endif -#if defined(CONFIG_MBX) - board_serial_init(); -#endif /* CONFIG_MBX */ - /* Set UART mode, 8 bit, no parity, one stop. * Enable receive and transmit. */ @@ -423,22 +405,6 @@ static int scc_init (void) sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]); up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC]; -#if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2) - { /* Disable Ethernet, enable Serial */ - uchar c; - - c = pic_read (0x61); - c &= ~0x40; /* enable COM3 */ - c |= 0x80; /* disable Ethernet */ - pic_write (0x61, c); - - /* enable RTS2 */ - cp->cp_pbpar |= 0x2000; - cp->cp_pbdat |= 0x2000; - cp->cp_pbdir |= 0x2000; - } -#endif /* CONFIG_LWMON */ - /* Disable transmitter/receiver. */ sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); @@ -450,18 +416,13 @@ static int scc_init (void) cp->cp_pbdir &= ~0x06; cp->cp_pbodr &= ~0x06; -#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860) +#elif (SCC_INDEX < 2) /* * Standard configuration for SCC's is on Part A */ ip->iop_papar |= ((3 << (2 * SCC_INDEX))); ip->iop_padir &= ~((3 << (2 * SCC_INDEX))); ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); -#else - /* - * The IP860 has SCC3 and SCC4 on Port D - */ - ip->iop_pdpar |= ((3 << (2 * SCC_INDEX))); #endif /* Allocate space for two buffer descriptors in the DP ram. */ diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 9869bbd183..f8aa93d611 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -26,9 +26,6 @@ #include #include -#define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 02cd0debc2..659e6889bf 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -52,34 +52,6 @@ DECLARE_GLOBAL_DATA_PTR; #define VIDEO_INFO_X VIDEO_LOGO_WIDTH+8 #define VIDEO_INFO_Y 16 -/************************************************************************/ -/* ** VIDEO ENCODER CONSTANTS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_ENCODER_AD7176 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7176_ADDR -#endif - -#ifdef CONFIG_VIDEO_ENCODER_AD7177 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7177_ADDR -#endif - -#ifdef CONFIG_VIDEO_ENCODER_AD7179 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7179_ADDR -#endif - /************************************************************************/ /* ** VIDEO MODE CONSTANTS */ /************************************************************************/ @@ -109,7 +81,6 @@ DECLARE_GLOBAL_DATA_PTR; /************************************************************************/ #include /* Get font data, width and height */ -#include #ifdef CONFIG_VIDEO_LOGO #include /* Get logo data, width and height */ @@ -468,7 +439,6 @@ static inline void video_putstring (int xx, int yy, unsigned char *s) /* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */ /************************************************************************/ -#if !defined(CONFIG_RRVISION) static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) { int i; @@ -481,7 +451,6 @@ static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) dest[0].lcyc++; /* Add a cycle to the first entry */ dest[entries - 1].lst = 1; /* Set end of ram entries */ } -#endif static void inline video_mode_addentry (VRAM * vr, int Hx, int Vx, int Fx, int Bx, @@ -642,72 +611,6 @@ static int video_mode_generate (void) #ifdef VIDEO_MODE_PAL -#if defined(CONFIG_RRVISION) - -#define HPW 160 /* horizontal pulse width (was 139) */ -#define VPW 2 /* vertical pulse width */ -#define HBP 104 /* horizontal back porch (was 112) */ -#define VBP 19 /* vertical back porch (was 19) */ -#define VID_R 240 /* number of rows */ - - debug ("[VIDEO CTRL] Starting to add controller entries..."); -/* - * Even field - */ - ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); - - ADDENTRY (0, 0, 0, 3, 1, 0, VPW, 1, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); - - ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); -/* - * Active area - */ - ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); - ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); - - ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); -/* - * Odd field - */ - ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); - - ADDENTRY (0, 0, 0, 3, 1, 0, VPW+1, 1, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); - - ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); -/* - * Active area - */ - ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); - ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); - - ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); - - debug ("done\n"); - -#else /* !CONFIG_RRVISION */ - /* * Hx Vx Fx Bx VDS INT LCYC LP LST * @@ -759,7 +662,6 @@ static int video_mode_generate (void) * one more cycle loop and a last identifier) */ video_mode_dupefield (vr, &vr[entry], entry); -#endif /* CONFIG_RRVISION */ #endif /* VIDEO_MODE_PAL */ @@ -788,58 +690,6 @@ static int video_mode_generate (void) static void video_encoder_init (void) { -#ifdef VIDEO_I2C - int rc; - - /* Initialize the I2C */ - debug ("[VIDEO ENCODER] Initializing I2C bus...\n"); -#ifdef CONFIG_SYS_I2C - i2c_init_all(); -#else - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - -#ifdef CONFIG_FADS - /* Reset ADV7176 chip */ - debug ("[VIDEO ENCODER] Resetting encoder...\n"); - (*(int *) BCSR4) &= ~(1 << 21); - - /* Wait for 5 ms inside the reset */ - debug ("[VIDEO ENCODER] Waiting for encoder reset...\n"); - udelay (5000); - - /* Take ADV7176 out of reset */ - (*(int *) BCSR4) |= 1 << 21; - - /* Wait for 5 ms after the reset */ - udelay (5000); -#endif /* CONFIG_FADS */ - - /* Send configuration */ -#ifdef DEBUG - { - int i; - - puts ("[VIDEO ENCODER] Configuring the encoder...\n"); - - printf ("Sending %zu bytes (@ %08lX) to I2C 0x%lX:\n ", - sizeof(video_encoder_data), - (ulong)video_encoder_data, - (ulong)VIDEO_I2C_ADDR); - for (i=0; iim_vid.vid_vccr, VIDEO_VCCR_VON, 0); -#ifdef CONFIG_FADS - /* Turn on Video Port LED */ - debug ("[VIDEO CTRL] Turning off video port led...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 1); - - /* Disable internal clock */ - debug ("[VIDEO CTRL] Disabling internal clock...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 0); -#endif - /* Generate and make active a new video mode */ debug ("[VIDEO CTRL] Generating video mode...\n"); video_mode_generate (); @@ -893,30 +733,6 @@ static void video_ctrl_init (void *memptr) immap->im_ioport.iop_pdpar = 0x1fff; immap->im_ioport.iop_pddir = 0x0000; -#ifdef CONFIG_FADS - /* Turn on Video Port Clock - ONLY AFTER SET VCCR TO ENABLE EXTERNAL CLOCK */ - debug ("[VIDEO CTRL] Turning on video clock...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 1); - - /* Turn on Video Port LED */ - debug ("[VIDEO CTRL] Turning on video port led...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0); -#endif -#ifdef CONFIG_RRVISION - debug ("PC5->Output(1): enable PAL clock"); - immap->im_ioport.iop_pcpar &= ~(0x0400); - immap->im_ioport.iop_pcdir |= 0x0400 ; - immap->im_ioport.iop_pcdat |= 0x0400 ; - debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", - immap->im_ioport.iop_pdpar, - immap->im_ioport.iop_pddir, - immap->im_ioport.iop_pddat); - debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", - immap->im_ioport.iop_pcpar, - immap->im_ioport.iop_pcdir, - immap->im_ioport.iop_pcdat); -#endif /* CONFIG_RRVISION */ - /* Blanking the screen. */ debug ("[VIDEO CTRL] Blanking the screen...\n"); video_fill (VIDEO_BG_COL); @@ -984,7 +800,7 @@ static inline void console_newline (void) } } -void video_putc (const char c) +void video_putc(struct stdio_dev *dev, const char c) { if (!video_enable) { serial_putc (c); @@ -1021,7 +837,7 @@ void video_putc (const char c) } } -void video_puts (const char *s) +void video_puts(struct stdio_dev *dev, const char *s) { int count = strlen (s); @@ -1030,7 +846,7 @@ void video_puts (const char *s) serial_putc (*s++); else while (count--) - video_putc (*s++); + video_putc(dev, *s++); } /************************************************************************/ @@ -1154,9 +970,7 @@ static void *video_logo (void) { u16 *screen = video_fb_address, width = VIDEO_COLS; #ifdef VIDEO_INFO -# ifndef CONFIG_FADS char temp[32]; -# endif char info[80]; #endif /* VIDEO_INFO */ @@ -1174,24 +988,15 @@ static void *video_logo (void) sprintf (info, " Wolfgang DENK, wd@denx.de"); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, info); -#ifndef CONFIG_FADS /* all normal boards */ + /* leave one blank line */ - sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash", + sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash", strmhz(temp, gd->cpu_clk), gd->ram_size >> 20, gd->bd->bi_flashsize >> 20 ); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4, info); -#else /* FADS :-( */ - sprintf (info, "MPC823 CPU at 50 MHz on FADS823 board"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, - info); - - sprintf (info, "2MB FLASH - 8MB DRAM - 4MB SRAM"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, - info); -#endif #endif return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN; diff --git a/arch/powerpc/cpu/mpc8xx/wlkbd.c b/arch/powerpc/cpu/mpc8xx/wlkbd.c deleted file mode 100644 index 3a41c2f164..0000000000 --- a/arch/powerpc/cpu/mpc8xx/wlkbd.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#ifdef CONFIG_WL_4PPM_KEYBOARD - -/* WIP: Wireless keyboard on SMC - */ -int drv_wlkbd_init (void) -{ - return 0 ; -} - -#endif /* CONFIG_WL_4PPM_KEYBOARD */ diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 3dc8e055b6..e95539e0a3 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -6,10 +6,6 @@ # Version 2 as published by the Free Software Foundation. # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib8xxx.o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -20,30 +16,15 @@ endif ifdef MINIMAL -COBJS-$(CONFIG_FSL_LAW) += law.o +obj-$(CONFIG_FSL_LAW) += law.o else +obj-$(CONFIG_MPC85xx) += cpu.o +obj-$(CONFIG_MPC86xx) += cpu.o -ifneq ($(CPU),mpc83xx) -COBJS-y += cpu.o -endif - -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o -COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o -COBJS-$(CONFIG_SYS_SRIO) += srio.o -COBJS-$(CONFIG_FSL_LAW) += law.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_FSL_LBC) += fsl_lbc.o +obj-$(CONFIG_SYS_SRIO) += srio.o +obj-$(CONFIG_FSL_LAW) += law.o endif - -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 7369582ef1..c92589fb9d 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -62,10 +63,11 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T4240, T4240, 0), CPU_TYPE_ENTRY(T4120, T4120, 0), CPU_TYPE_ENTRY(T4160, T4160, 0), + CPU_TYPE_ENTRY(T4080, T4080, 4), CPU_TYPE_ENTRY(B4860, B4860, 0), CPU_TYPE_ENTRY(G4860, G4860, 0), - CPU_TYPE_ENTRY(G4060, G4060, 0), CPU_TYPE_ENTRY(B4440, B4440, 0), + CPU_TYPE_ENTRY(B4460, B4460, 0), CPU_TYPE_ENTRY(G4440, G4440, 0), CPU_TYPE_ENTRY(B4420, B4420, 0), CPU_TYPE_ENTRY(B4220, B4220, 0), @@ -75,10 +77,19 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T1020, T1020, 0), CPU_TYPE_ENTRY(T1021, T1021, 0), CPU_TYPE_ENTRY(T1022, T1022, 0), + CPU_TYPE_ENTRY(T1024, T1024, 0), + CPU_TYPE_ENTRY(T1023, T1023, 0), + CPU_TYPE_ENTRY(T1014, T1014, 0), + CPU_TYPE_ENTRY(T1013, T1013, 0), + CPU_TYPE_ENTRY(T2080, T2080, 0), + CPU_TYPE_ENTRY(T2081, T2081, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), CPU_TYPE_ENTRY(BSC9131, 9131, 1), CPU_TYPE_ENTRY(BSC9132, 9132, 2), CPU_TYPE_ENTRY(BSC9232, 9232, 2), + CPU_TYPE_ENTRY(C291, C291, 1), + CPU_TYPE_ENTRY(C292, C292, 1), + CPU_TYPE_ENTRY(C293, C293, 1), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), @@ -171,7 +182,7 @@ struct cpu_type *identify_cpu(u32 ver) /* * Return a 32-bit mask indicating which cores are present on this SOC. */ -u32 cpu_mask(void) +__weak u32 cpu_mask(void) { ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->arch.cpu; @@ -190,7 +201,7 @@ u32 cpu_mask(void) /* * Return the number of cores on this SOC. */ -int cpu_numcores(void) +__weak int cpu_numcores(void) { struct cpu_type *cpu = gd->arch.cpu; @@ -261,5 +272,9 @@ int cpu_eth_init(bd_t *bis) #ifdef CONFIG_FMAN_ENET fm_standard_init(bis); #endif + +#ifdef CONFIG_VSC9953 + vsc9953_init(bis); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile deleted file mode 100644 index 29523aa913..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright 2008-2011 Freescale Semiconductor, Inc. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# Version 2 as published by the Free Software Foundation. -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)libddr.o - -COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o - -COBJS-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o - -COBJS-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o -ifdef CONFIG_DDR_SPD -SPD := y -endif -ifdef CONFIG_SPD_EEPROM -SPD := y -endif -ifdef SPD -COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o -COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o -COBJS-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o -endif - -COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o - -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h deleted file mode 100644 index 06706ed78c..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef COMMON_TIMING_PARAMS_H -#define COMMON_TIMING_PARAMS_H - -typedef struct { - /* parameters to constrict */ - - unsigned int tCKmin_X_ps; - unsigned int tCKmax_ps; - unsigned int tCKmax_max_ps; - unsigned int tRCD_ps; - unsigned int tRP_ps; - unsigned int tRAS_ps; - - unsigned int tWR_ps; /* maximum = 63750 ps */ - unsigned int tWTR_ps; /* maximum = 63750 ps */ - unsigned int tRFC_ps; /* maximum = 255 ns + 256 ns + .75 ns - = 511750 ps */ - - unsigned int tRRD_ps; /* maximum = 63750 ps */ - unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - unsigned int refresh_rate_ps; - - unsigned int tIS_ps; /* byte 32, spd->ca_setup */ - unsigned int tIH_ps; /* byte 33, spd->ca_hold */ - unsigned int tDS_ps; /* byte 34, spd->data_setup */ - unsigned int tDH_ps; /* byte 35, spd->data_hold */ - unsigned int tRTP_ps; /* byte 38, spd->trtp */ - unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tQHS_ps; /* byte 45, spd->tqhs */ - - unsigned int ndimms_present; - unsigned int lowest_common_SPD_caslat; - unsigned int highest_common_derated_caslat; - unsigned int additive_latency; - unsigned int all_DIMMs_burst_lengths_bitmask; - unsigned int all_DIMMs_registered; - unsigned int all_DIMMs_unbuffered; - unsigned int all_DIMMs_ECC_capable; - - unsigned long long total_mem; - unsigned long long base_address; - - /* DDR3 RDIMM */ - unsigned char rcw[16]; /* Register Control Word 0-15 */ -} common_timing_params_t; - -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c deleted file mode 100644 index ff5812df55..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ /dev/null @@ -1,1642 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - */ - -#include -#include - -#include "ddr.h" - -#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR - -static u32 fsl_ddr_get_version(void) -{ - ccsr_ddr_t *ddr; - u32 ver_major_minor_errata; - - ddr = (void *)_DDR_ADDR; - ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; - ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; - - return ver_major_minor_errata; -} - -unsigned int picos_to_mclk(unsigned int picos); - -/* - * Determine Rtt value. - * - * This should likely be either board or controller specific. - * - * Rtt(nominal) - DDR2: - * 0 = Rtt disabled - * 1 = 75 ohm - * 2 = 150 ohm - * 3 = 50 ohm - * Rtt(nominal) - DDR3: - * 0 = Rtt disabled - * 1 = 60 ohm - * 2 = 120 ohm - * 3 = 40 ohm - * 4 = 20 ohm - * 5 = 30 ohm - * - * FIXME: Apparently 8641 needs a value of 2 - * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 - * - * FIXME: There was some effort down this line earlier: - * - * unsigned int i; - * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { - * if (popts->dimmslot[i].num_valid_cs - * && (popts->cs_local_opts[2*i].odt_rd_cfg - * || popts->cs_local_opts[2*i].odt_wr_cfg)) { - * rtt = 2; - * break; - * } - * } - */ -static inline int fsl_ddr_get_rtt(void) -{ - int rtt; - -#if defined(CONFIG_FSL_DDR1) - rtt = 0; -#elif defined(CONFIG_FSL_DDR2) - rtt = 3; -#else - rtt = 0; -#endif - - return rtt; -} - -/* - * compute the CAS write latency according to DDR3 spec - * CWL = 5 if tCK >= 2.5ns - * 6 if 2.5ns > tCK >= 1.875ns - * 7 if 1.875ns > tCK >= 1.5ns - * 8 if 1.5ns > tCK >= 1.25ns - * 9 if 1.25ns > tCK >= 1.07ns - * 10 if 1.07ns > tCK >= 0.935ns - * 11 if 0.935ns > tCK >= 0.833ns - * 12 if 0.833ns > tCK >= 0.75ns - */ -static inline unsigned int compute_cas_write_latency(void) -{ - unsigned int cwl; - const unsigned int mclk_ps = get_memory_clk_period_ps(); - - if (mclk_ps >= 2500) - cwl = 5; - else if (mclk_ps >= 1875) - cwl = 6; - else if (mclk_ps >= 1500) - cwl = 7; - else if (mclk_ps >= 1250) - cwl = 8; - else if (mclk_ps >= 1070) - cwl = 9; - else if (mclk_ps >= 935) - cwl = 10; - else if (mclk_ps >= 833) - cwl = 11; - else if (mclk_ps >= 750) - cwl = 12; - else { - cwl = 12; - printf("Warning: CWL is out of range\n"); - } - return cwl; -} - -/* Chip Select Configuration (CSn_CONFIG) */ -static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const dimm_params_t *dimm_params) -{ - unsigned int cs_n_en = 0; /* Chip Select enable */ - unsigned int intlv_en = 0; /* Memory controller interleave enable */ - unsigned int intlv_ctl = 0; /* Interleaving control */ - unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ - unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ - unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ - unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ - unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ - unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ - int go_config = 0; - - /* Compute CS_CONFIG only for existing ranks of each DIMM. */ - switch (i) { - case 0: - if (dimm_params[dimm_number].n_ranks > 0) { - go_config = 1; - /* These fields only available in CS0_CONFIG */ - if (!popts->memctl_interleaving) - break; - switch (popts->memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - intlv_en = popts->memctl_interleaving; - intlv_ctl = popts->memctl_interleaving_mode; - break; - default: - break; - } - } - break; - case 1: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ - (dimm_number == 1 && dimm_params[1].n_ranks > 0)) - go_config = 1; - break; - case 2: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ - (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) - go_config = 1; - break; - case 3: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ - (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ - (dimm_number == 3 && dimm_params[3].n_ranks > 0)) - go_config = 1; - break; - default: - break; - } - if (go_config) { - unsigned int n_banks_per_sdram_device; - cs_n_en = 1; - ap_n_en = popts->cs_local_opts[i].auto_precharge; - odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; - odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; - n_banks_per_sdram_device - = dimm_params[dimm_number].n_banks_per_sdram_device; - ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; - row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; - col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; - } - ddr->cs[i].config = (0 - | ((cs_n_en & 0x1) << 31) - | ((intlv_en & 0x3) << 29) - | ((intlv_ctl & 0xf) << 24) - | ((ap_n_en & 0x1) << 23) - - /* XXX: some implementation only have 1 bit starting at left */ - | ((odt_rd_cfg & 0x7) << 20) - - /* XXX: Some implementation only have 1 bit starting at left */ - | ((odt_wr_cfg & 0x7) << 16) - - | ((ba_bits_cs_n & 0x3) << 14) - | ((row_bits_cs_n & 0x7) << 8) - | ((col_bits_cs_n & 0x7) << 0) - ); - debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); -} - -/* Chip Select Configuration 2 (CSn_CONFIG_2) */ -/* FIXME: 8572 */ -static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int pasr_cfg = 0; /* Partial array self refresh config */ - - ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); - debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); -} - -/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ - -#if !defined(CONFIG_FSL_DDR1) -static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) -{ -#if CONFIG_DIMM_SLOTS_PER_CTLR == 1 - if (dimm_params[0].n_ranks == 4) - return 1; -#endif - -#if CONFIG_DIMM_SLOTS_PER_CTLR == 2 - if ((dimm_params[0].n_ranks == 2) && - (dimm_params[1].n_ranks == 2)) - return 1; - -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (dimm_params[0].n_ranks == 4) - return 1; -#endif -#endif - return 0; -} - -/* - * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) - * - * Avoid writing for DDR I. The new PQ38 DDR controller - * dreams up non-zero default values to be backwards compatible. - */ -static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const dimm_params_t *dimm_params) -{ - unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ - unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ - /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ - unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ - unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ - - /* Active powerdown exit timing (tXARD and tXARDS). */ - unsigned char act_pd_exit_mclk; - /* Precharge powerdown exit timing (tXP). */ - unsigned char pre_pd_exit_mclk; - /* ODT powerdown exit timing (tAXPD). */ - unsigned char taxpd_mclk; - /* Mode register set cycle time (tMRD). */ - unsigned char tmrd_mclk; - -#ifdef CONFIG_FSL_DDR3 - /* - * (tXARD and tXARDS). Empirical? - * The DDR3 spec has not tXARD, - * we use the tXP instead of it. - * tXP=max(3nCK, 7.5ns) for DDR3. - * spec has not the tAXPD, we use - * tAXPD=1, need design to confirm. - */ - int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - unsigned int data_rate = get_ddr_freq(0); - tmrd_mclk = 4; - /* set the turnaround time */ - - /* - * for single quad-rank DIMM and two dual-rank DIMMs - * to avoid ODT overlap - */ - if (avoid_odt_overlap(dimm_params)) { - twwt_mclk = 2; - trrt_mclk = 1; - } - /* for faster clock, need more time for data setup */ - trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; - - if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) - twrt_mclk = 1; - - if (popts->dynamic_power == 0) { /* powerdown is not used */ - act_pd_exit_mclk = 1; - pre_pd_exit_mclk = 1; - taxpd_mclk = 1; - } else { - /* act_pd_exit_mclk = tXARD, see above */ - act_pd_exit_mclk = picos_to_mclk(tXP); - /* Mode register MR0[A12] is '1' - fast exit */ - pre_pd_exit_mclk = act_pd_exit_mclk; - taxpd_mclk = 1; - } -#else /* CONFIG_FSL_DDR2 */ - /* - * (tXARD and tXARDS). Empirical? - * tXARD = 2 for DDR2 - * tXP=2 - * tAXPD=8 - */ - act_pd_exit_mclk = 2; - pre_pd_exit_mclk = 2; - taxpd_mclk = 8; - tmrd_mclk = 2; -#endif - - if (popts->trwt_override) - trwt_mclk = popts->trwt; - - ddr->timing_cfg_0 = (0 - | ((trwt_mclk & 0x3) << 30) /* RWT */ - | ((twrt_mclk & 0x3) << 28) /* WRT */ - | ((trrt_mclk & 0x3) << 26) /* RRT */ - | ((twwt_mclk & 0x3) << 24) /* WWT */ - | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ - | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ - | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ - | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ - ); - debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); -} -#endif /* defined(CONFIG_FSL_DDR2) */ - -/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ -static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) -{ - /* Extended precharge to activate interval (tRP) */ - unsigned int ext_pretoact = 0; - /* Extended Activate to precharge interval (tRAS) */ - unsigned int ext_acttopre = 0; - /* Extended activate to read/write interval (tRCD) */ - unsigned int ext_acttorw = 0; - /* Extended refresh recovery time (tRFC) */ - unsigned int ext_refrec; - /* Extended MCAS latency from READ cmd */ - unsigned int ext_caslat = 0; - /* Extended last data to precharge interval (tWR) */ - unsigned int ext_wrrec = 0; - /* Control Adjust */ - unsigned int cntl_adj = 0; - - ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4; - ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4; - ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4; - ext_caslat = (2 * cas_latency - 1) >> 4; - ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4; - /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ - ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) + - (popts->OTF_burst_chop_en ? 2 : 0)) >> 4; - - ddr->timing_cfg_3 = (0 - | ((ext_pretoact & 0x1) << 28) - | ((ext_acttopre & 0x2) << 24) - | ((ext_acttorw & 0x1) << 22) - | ((ext_refrec & 0x1F) << 16) - | ((ext_caslat & 0x3) << 12) - | ((ext_wrrec & 0x1) << 8) - | ((cntl_adj & 0x7) << 0) - ); - debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); -} - -/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ -static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) -{ - /* Precharge-to-activate interval (tRP) */ - unsigned char pretoact_mclk; - /* Activate to precharge interval (tRAS) */ - unsigned char acttopre_mclk; - /* Activate to read/write interval (tRCD) */ - unsigned char acttorw_mclk; - /* CASLAT */ - unsigned char caslat_ctrl; - /* Refresh recovery time (tRFC) ; trfc_low */ - unsigned char refrec_ctrl; - /* Last data to precharge minimum interval (tWR) */ - unsigned char wrrec_mclk; - /* Activate-to-activate interval (tRRD) */ - unsigned char acttoact_mclk; - /* Last write data pair to read command issue interval (tWTR) */ - unsigned char wrtord_mclk; - /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ - static const u8 wrrec_table[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; - - pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps); - acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps); - acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps); - - /* - * Translate CAS Latency to a DDR controller field value: - * - * CAS Lat DDR I DDR II Ctrl - * Clocks SPD Bit SPD Bit Value - * ------- ------- ------- ----- - * 1.0 0 0001 - * 1.5 1 0010 - * 2.0 2 2 0011 - * 2.5 3 0100 - * 3.0 4 3 0101 - * 3.5 5 0110 - * 4.0 4 0111 - * 4.5 1000 - * 5.0 5 1001 - */ -#if defined(CONFIG_FSL_DDR1) - caslat_ctrl = (cas_latency + 1) & 0x07; -#elif defined(CONFIG_FSL_DDR2) - caslat_ctrl = 2 * cas_latency - 1; -#else - /* - * if the CAS latency more than 8 cycle, - * we need set extend bit for it at - * TIMING_CFG_3[EXT_CASLAT] - */ - caslat_ctrl = 2 * cas_latency - 1; -#endif - - refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); - - if (wrrec_mclk > 16) - printf("Error: WRREC doesn't support more than 16 clocks\n"); - else - wrrec_mclk = wrrec_table[wrrec_mclk - 1]; - if (popts->OTF_burst_chop_en) - wrrec_mclk += 2; - - acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps); - /* - * JEDEC has min requirement for tRRD - */ -#if defined(CONFIG_FSL_DDR3) - if (acttoact_mclk < 4) - acttoact_mclk = 4; -#endif - wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps); - /* - * JEDEC has some min requirements for tWTR - */ -#if defined(CONFIG_FSL_DDR2) - if (wrtord_mclk < 2) - wrtord_mclk = 2; -#elif defined(CONFIG_FSL_DDR3) - if (wrtord_mclk < 4) - wrtord_mclk = 4; -#endif - if (popts->OTF_burst_chop_en) - wrtord_mclk += 2; - - ddr->timing_cfg_1 = (0 - | ((pretoact_mclk & 0x0F) << 28) - | ((acttopre_mclk & 0x0F) << 24) - | ((acttorw_mclk & 0xF) << 20) - | ((caslat_ctrl & 0xF) << 16) - | ((refrec_ctrl & 0xF) << 12) - | ((wrrec_mclk & 0x0F) << 8) - | ((acttoact_mclk & 0x0F) << 4) - | ((wrtord_mclk & 0x0F) << 0) - ); - debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); -} - -/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ -static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) -{ - /* Additive latency */ - unsigned char add_lat_mclk; - /* CAS-to-preamble override */ - unsigned short cpo; - /* Write latency */ - unsigned char wr_lat; - /* Read to precharge (tRTP) */ - unsigned char rd_to_pre; - /* Write command to write data strobe timing adjustment */ - unsigned char wr_data_delay; - /* Minimum CKE pulse width (tCKE) */ - unsigned char cke_pls; - /* Window for four activates (tFAW) */ - unsigned short four_act; - - /* FIXME add check that this must be less than acttorw_mclk */ - add_lat_mclk = additive_latency; - cpo = popts->cpo_override; - -#if defined(CONFIG_FSL_DDR1) - /* - * This is a lie. It should really be 1, but if it is - * set to 1, bits overlap into the old controller's - * otherwise unused ACSM field. If we leave it 0, then - * the HW will magically treat it as 1 for DDR 1. Oh Yea. - */ - wr_lat = 0; -#elif defined(CONFIG_FSL_DDR2) - wr_lat = cas_latency - 1; -#else - wr_lat = compute_cas_write_latency(); -#endif - - rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); - /* - * JEDEC has some min requirements for tRTP - */ -#if defined(CONFIG_FSL_DDR2) - if (rd_to_pre < 2) - rd_to_pre = 2; -#elif defined(CONFIG_FSL_DDR3) - if (rd_to_pre < 4) - rd_to_pre = 4; -#endif - if (additive_latency) - rd_to_pre += additive_latency; - if (popts->OTF_burst_chop_en) - rd_to_pre += 2; /* according to UM */ - - wr_data_delay = popts->write_data_delay; - cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps); - four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps); - - ddr->timing_cfg_2 = (0 - | ((add_lat_mclk & 0xf) << 28) - | ((cpo & 0x1f) << 23) - | ((wr_lat & 0xf) << 19) - | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) - | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) - | ((cke_pls & 0x7) << 6) - | ((four_act & 0x3f) << 0) - ); - debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); -} - -/* DDR SDRAM Register Control Word */ -static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - if (common_dimm->all_DIMMs_registered - && !common_dimm->all_DIMMs_unbuffered) { - if (popts->rcw_override) { - ddr->ddr_sdram_rcw_1 = popts->rcw_1; - ddr->ddr_sdram_rcw_2 = popts->rcw_2; - } else { - ddr->ddr_sdram_rcw_1 = - common_dimm->rcw[0] << 28 | \ - common_dimm->rcw[1] << 24 | \ - common_dimm->rcw[2] << 20 | \ - common_dimm->rcw[3] << 16 | \ - common_dimm->rcw[4] << 12 | \ - common_dimm->rcw[5] << 8 | \ - common_dimm->rcw[6] << 4 | \ - common_dimm->rcw[7]; - ddr->ddr_sdram_rcw_2 = - common_dimm->rcw[8] << 28 | \ - common_dimm->rcw[9] << 24 | \ - common_dimm->rcw[10] << 20 | \ - common_dimm->rcw[11] << 16 | \ - common_dimm->rcw[12] << 12 | \ - common_dimm->rcw[13] << 8 | \ - common_dimm->rcw[14] << 4 | \ - common_dimm->rcw[15]; - } - debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); - debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); - } -} - -/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ -static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - unsigned int mem_en; /* DDR SDRAM interface logic enable */ - unsigned int sren; /* Self refresh enable (during sleep) */ - unsigned int ecc_en; /* ECC enable. */ - unsigned int rd_en; /* Registered DIMM enable */ - unsigned int sdram_type; /* Type of SDRAM */ - unsigned int dyn_pwr; /* Dynamic power management mode */ - unsigned int dbw; /* DRAM dta bus width */ - unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ - unsigned int ncap = 0; /* Non-concurrent auto-precharge */ - unsigned int threeT_en; /* Enable 3T timing */ - unsigned int twoT_en; /* Enable 2T timing */ - unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ - unsigned int x32_en = 0; /* x32 enable */ - unsigned int pchb8 = 0; /* precharge bit 8 enable */ - unsigned int hse; /* Global half strength override */ - unsigned int mem_halt = 0; /* memory controller halt */ - unsigned int bi = 0; /* Bypass initialization */ - - mem_en = 1; - sren = popts->self_refresh_in_sleep; - if (common_dimm->all_DIMMs_ECC_capable) { - /* Allow setting of ECC only if all DIMMs are ECC. */ - ecc_en = popts->ECC_mode; - } else { - ecc_en = 0; - } - - if (common_dimm->all_DIMMs_registered - && !common_dimm->all_DIMMs_unbuffered) { - rd_en = 1; - twoT_en = 0; - } else { - rd_en = 0; - twoT_en = popts->twoT_en; - } - - sdram_type = CONFIG_FSL_SDRAM_TYPE; - - dyn_pwr = popts->dynamic_power; - dbw = popts->data_bus_width; - /* 8-beat burst enable DDR-III case - * we must clear it when use the on-the-fly mode, - * must set it when use the 32-bits bus mode. - */ - if (sdram_type == SDRAM_TYPE_DDR3) { - if (popts->burst_length == DDR_BL8) - eight_be = 1; - if (popts->burst_length == DDR_OTF) - eight_be = 0; - if (dbw == 0x1) - eight_be = 1; - } - - threeT_en = popts->threeT_en; - ba_intlv_ctl = popts->ba_intlv_ctl; - hse = popts->half_strength_driver_enable; - - ddr->ddr_sdram_cfg = (0 - | ((mem_en & 0x1) << 31) - | ((sren & 0x1) << 30) - | ((ecc_en & 0x1) << 29) - | ((rd_en & 0x1) << 28) - | ((sdram_type & 0x7) << 24) - | ((dyn_pwr & 0x1) << 21) - | ((dbw & 0x3) << 19) - | ((eight_be & 0x1) << 18) - | ((ncap & 0x1) << 17) - | ((threeT_en & 0x1) << 16) - | ((twoT_en & 0x1) << 15) - | ((ba_intlv_ctl & 0x7F) << 8) - | ((x32_en & 0x1) << 5) - | ((pchb8 & 0x1) << 4) - | ((hse & 0x1) << 3) - | ((mem_halt & 0x1) << 1) - | ((bi & 0x1) << 0) - ); - debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); -} - -/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ -static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const unsigned int unq_mrs_en) -{ - unsigned int frc_sr = 0; /* Force self refresh */ - unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ - unsigned int dll_rst_dis; /* DLL reset disable */ - unsigned int dqs_cfg; /* DQS configuration */ - unsigned int odt_cfg = 0; /* ODT configuration */ - unsigned int num_pr; /* Number of posted refreshes */ - unsigned int slow = 0; /* DDR will be run less than 1250 */ - unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ - unsigned int ap_en; /* Address Parity Enable */ - unsigned int d_init; /* DRAM data initialization */ - unsigned int rcw_en = 0; /* Register Control Word Enable */ - unsigned int md_en = 0; /* Mirrored DIMM Enable */ - unsigned int qd_en = 0; /* quad-rank DIMM Enable */ - int i; - - dll_rst_dis = 1; /* Make this configurable */ - dqs_cfg = popts->DQS_config; - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->cs_local_opts[i].odt_rd_cfg - || popts->cs_local_opts[i].odt_wr_cfg) { - odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; - break; - } - } - - num_pr = 1; /* Make this configurable */ - - /* - * 8572 manual says - * {TIMING_CFG_1[PRETOACT] - * + [DDR_SDRAM_CFG_2[NUM_PR] - * * ({EXT_REFREC || REFREC} + 8 + 2)]} - * << DDR_SDRAM_INTERVAL[REFINT] - */ -#if defined(CONFIG_FSL_DDR3) - obc_cfg = popts->OTF_burst_chop_en; -#else - obc_cfg = 0; -#endif - -#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) - slow = get_ddr_freq(0) < 1249000000; -#endif - - if (popts->registered_dimm_en) { - rcw_en = 1; - ap_en = popts->ap_en; - } else { - ap_en = 0; - } - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Use the DDR controller to auto initialize memory. */ - d_init = popts->ECC_init_using_memctl; - ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; - debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); -#else - /* Memory will be initialized via DMA, or not at all. */ - d_init = 0; -#endif - -#if defined(CONFIG_FSL_DDR3) - md_en = popts->mirrored_dimm; -#endif - qd_en = popts->quad_rank_present ? 1 : 0; - ddr->ddr_sdram_cfg_2 = (0 - | ((frc_sr & 0x1) << 31) - | ((sr_ie & 0x1) << 30) - | ((dll_rst_dis & 0x1) << 29) - | ((dqs_cfg & 0x3) << 26) - | ((odt_cfg & 0x3) << 21) - | ((num_pr & 0xf) << 12) - | ((slow & 1) << 11) - | (qd_en << 9) - | (unq_mrs_en << 8) - | ((obc_cfg & 0x1) << 6) - | ((ap_en & 0x1) << 5) - | ((d_init & 0x1) << 4) - | ((rcw_en & 0x1) << 2) - | ((md_en & 0x1) << 0) - ); - debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); -} - -/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ - unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ - -#if defined(CONFIG_FSL_DDR3) - int i; - unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ - unsigned int srt = 0; /* self-refresh temerature, normal range */ - unsigned int asr = 0; /* auto self-refresh disable */ - unsigned int cwl = compute_cas_write_latency() - 5; - unsigned int pasr = 0; /* partial array self refresh disable */ - - if (popts->rtt_override) - rtt_wr = popts->rtt_wr_override_value; - else - rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; - esdmode2 = (0 - | ((rtt_wr & 0x3) << 9) - | ((srt & 0x1) << 7) - | ((asr & 0x1) << 6) - | ((cwl & 0x7) << 3) - | ((pasr & 0x7) << 0)); -#endif - ddr->ddr_sdram_mode_2 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); - -#ifdef CONFIG_FSL_DDR3 - if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->rtt_override) - rtt_wr = popts->rtt_wr_override_value; - else - rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; - - esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ - esdmode2 |= (rtt_wr & 0x3) << 9; - switch (i) { - case 1: - ddr->ddr_sdram_mode_4 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - case 2: - ddr->ddr_sdram_mode_6 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - case 3: - ddr->ddr_sdram_mode_8 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - } - } - debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", - ddr->ddr_sdram_mode_4); - debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", - ddr->ddr_sdram_mode_6); - debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", - ddr->ddr_sdram_mode_8); - } -#endif -} - -/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ -static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - unsigned int refint; /* Refresh interval */ - unsigned int bstopre; /* Precharge interval */ - - refint = picos_to_mclk(common_dimm->refresh_rate_ps); - - bstopre = popts->bstopre; - - /* refint field used 0x3FFF in earlier controllers */ - ddr->ddr_sdram_interval = (0 - | ((refint & 0xFFFF) << 16) - | ((bstopre & 0x3FFF) << 0) - ); - debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); -} - -#if defined(CONFIG_FSL_DDR3) -/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode; /* Extended SDRAM mode */ - unsigned short sdmode; /* SDRAM mode */ - - /* Mode Register - MR1 */ - unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ - unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ - unsigned int rtt; - unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ - unsigned int al = 0; /* Posted CAS# additive latency (AL) */ - unsigned int dic = 0; /* Output driver impedance, 40ohm */ - unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), - 1=Disable (Test/Debug) */ - - /* Mode Register - MR0 */ - unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ - unsigned int wr = 0; /* Write Recovery */ - unsigned int dll_rst; /* DLL Reset */ - unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ - /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ - unsigned int bt; - unsigned int bl; /* BL: Burst Length */ - - unsigned int wr_mclk; - /* - * DDR_SDRAM_MODE doesn't support 9,11,13,15 - * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 - * for this table - */ - static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; - - const unsigned int mclk_ps = get_memory_clk_period_ps(); - int i; - - if (popts->rtt_override) - rtt = popts->rtt_override_value; - else - rtt = popts->cs_local_opts[0].odt_rtt_norm; - - if (additive_latency == (cas_latency - 1)) - al = 1; - if (additive_latency == (cas_latency - 2)) - al = 2; - - if (popts->quad_rank_present) - dic = 1; /* output driver impedance 240/7 ohm */ - - /* - * The esdmode value will also be used for writing - * MR1 during write leveling for DDR3, although the - * bits specifically related to the write leveling - * scheme will be handled automatically by the DDR - * controller. so we set the wrlvl_en = 0 here. - */ - esdmode = (0 - | ((qoff & 0x1) << 12) - | ((tdqs_en & 0x1) << 11) - | ((rtt & 0x4) << 7) /* rtt field is split */ - | ((wrlvl_en & 0x1) << 7) - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((dic & 0x2) << 4) /* DIC field is split */ - | ((al & 0x3) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ - | ((dic & 0x1) << 1) /* DIC field is split */ - | ((dll_en & 0x1) << 0) - ); - - /* - * DLL control for precharge PD - * 0=slow exit DLL off (tXPDLL) - * 1=fast exit DLL on (tXP) - */ - dll_on = 1; - - wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps; - if (wr_mclk <= 16) { - wr = wr_table[wr_mclk - 5]; - } else { - printf("Error: unsupported write recovery for mode register " - "wr_mclk = %d\n", wr_mclk); - } - - dll_rst = 0; /* dll no reset */ - mode = 0; /* normal mode */ - - /* look up table to get the cas latency bits */ - if (cas_latency >= 5 && cas_latency <= 16) { - unsigned char cas_latency_table[] = { - 0x2, /* 5 clocks */ - 0x4, /* 6 clocks */ - 0x6, /* 7 clocks */ - 0x8, /* 8 clocks */ - 0xa, /* 9 clocks */ - 0xc, /* 10 clocks */ - 0xe, /* 11 clocks */ - 0x1, /* 12 clocks */ - 0x3, /* 13 clocks */ - 0x5, /* 14 clocks */ - 0x7, /* 15 clocks */ - 0x9, /* 16 clocks */ - }; - caslat = cas_latency_table[cas_latency - 5]; - } else { - printf("Error: unsupported cas latency for mode register\n"); - } - - bt = 0; /* Nibble sequential */ - - switch (popts->burst_length) { - case DDR_BL8: - bl = 0; - break; - case DDR_OTF: - bl = 1; - break; - case DDR_BC4: - bl = 2; - break; - default: - printf("Error: invalid burst length of %u specified. " - " Defaulting to on-the-fly BC4 or BL8 beats.\n", - popts->burst_length); - bl = 1; - break; - } - - sdmode = (0 - | ((dll_on & 0x1) << 12) - | ((wr & 0x7) << 9) - | ((dll_rst & 0x1) << 8) - | ((mode & 0x1) << 7) - | (((caslat >> 1) & 0x7) << 4) - | ((bt & 0x1) << 3) - | ((caslat & 1) << 2) - | ((bl & 0x3) << 0) - ); - - ddr->ddr_sdram_mode = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - - debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); - - if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->rtt_override) - rtt = popts->rtt_override_value; - else - rtt = popts->cs_local_opts[i].odt_rtt_norm; - - esdmode &= 0xFDBB; /* clear bit 9,6,2 */ - esdmode |= (0 - | ((rtt & 0x4) << 7) /* rtt field is split */ - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((rtt & 0x1) << 2) /* rtt field is split */ - ); - switch (i) { - case 1: - ddr->ddr_sdram_mode_3 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - case 2: - ddr->ddr_sdram_mode_5 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - case 3: - ddr->ddr_sdram_mode_7 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - } - } - debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", - ddr->ddr_sdram_mode_3); - debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", - ddr->ddr_sdram_mode_5); - debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", - ddr->ddr_sdram_mode_5); - } -} - -#else /* !CONFIG_FSL_DDR3 */ - -/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode; /* Extended SDRAM mode */ - unsigned short sdmode; /* SDRAM mode */ - - /* - * FIXME: This ought to be pre-calculated in a - * technology-specific routine, - * e.g. compute_DDR2_mode_register(), and then the - * sdmode and esdmode passed in as part of common_dimm. - */ - - /* Extended Mode Register */ - unsigned int mrs = 0; /* Mode Register Set */ - unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ - unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ - unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ - unsigned int ocd = 0; /* 0x0=OCD not supported, - 0x7=OCD default state */ - unsigned int rtt; - unsigned int al; /* Posted CAS# additive latency (AL) */ - unsigned int ods = 0; /* Output Drive Strength: - 0 = Full strength (18ohm) - 1 = Reduced strength (4ohm) */ - unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), - 1=Disable (Test/Debug) */ - - /* Mode Register (MR) */ - unsigned int mr; /* Mode Register Definition */ - unsigned int pd; /* Power-Down Mode */ - unsigned int wr; /* Write Recovery */ - unsigned int dll_res; /* DLL Reset */ - unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat = 0;/* CAS# latency */ - /* BT: Burst Type (0=Sequential, 1=Interleaved) */ - unsigned int bt; - unsigned int bl; /* BL: Burst Length */ - -#if defined(CONFIG_FSL_DDR2) - const unsigned int mclk_ps = get_memory_clk_period_ps(); -#endif - dqs_en = !popts->DQS_config; - rtt = fsl_ddr_get_rtt(); - - al = additive_latency; - - esdmode = (0 - | ((mrs & 0x3) << 14) - | ((outputs & 0x1) << 12) - | ((rdqs_en & 0x1) << 11) - | ((dqs_en & 0x1) << 10) - | ((ocd & 0x7) << 7) - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((al & 0x7) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ - | ((ods & 0x1) << 1) - | ((dll_en & 0x1) << 0) - ); - - mr = 0; /* FIXME: CHECKME */ - - /* - * 0 = Fast Exit (Normal) - * 1 = Slow Exit (Low Power) - */ - pd = 0; - -#if defined(CONFIG_FSL_DDR1) - wr = 0; /* Historical */ -#elif defined(CONFIG_FSL_DDR2) - wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1; -#endif - dll_res = 0; - mode = 0; - -#if defined(CONFIG_FSL_DDR1) - if (1 <= cas_latency && cas_latency <= 4) { - unsigned char mode_caslat_table[4] = { - 0x5, /* 1.5 clocks */ - 0x2, /* 2.0 clocks */ - 0x6, /* 2.5 clocks */ - 0x3 /* 3.0 clocks */ - }; - caslat = mode_caslat_table[cas_latency - 1]; - } else { - printf("Warning: unknown cas_latency %d\n", cas_latency); - } -#elif defined(CONFIG_FSL_DDR2) - caslat = cas_latency; -#endif - bt = 0; - - switch (popts->burst_length) { - case DDR_BL4: - bl = 2; - break; - case DDR_BL8: - bl = 3; - break; - default: - printf("Error: invalid burst length of %u specified. " - " Defaulting to 4 beats.\n", - popts->burst_length); - bl = 2; - break; - } - - sdmode = (0 - | ((mr & 0x3) << 14) - | ((pd & 0x1) << 12) - | ((wr & 0x7) << 9) - | ((dll_res & 0x1) << 8) - | ((mode & 0x1) << 7) - | ((caslat & 0x7) << 4) - | ((bt & 0x1) << 3) - | ((bl & 0x7) << 0) - ); - - ddr->ddr_sdram_mode = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); -} -#endif - -/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ -static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_value; /* Initialization value */ - -#ifdef CONFIG_MEM_INIT_VALUE - init_value = CONFIG_MEM_INIT_VALUE; -#else - init_value = 0xDEADBEEF; -#endif - ddr->ddr_data_init = init_value; -} - -/* - * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) - * The old controller on the 8540/60 doesn't have this register. - * Hope it's OK to set it (to 0) anyway. - */ -static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned int clk_adjust; /* Clock adjust */ - - clk_adjust = popts->clk_adjust; - ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; - debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); -} - -/* DDR Initialization Address (DDR_INIT_ADDR) */ -static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_addr = 0; /* Initialization address */ - - ddr->ddr_init_addr = init_addr; -} - -/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ -static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int uia = 0; /* Use initialization address */ - unsigned int init_ext_addr = 0; /* Initialization address */ - - ddr->ddr_init_ext_addr = (0 - | ((uia & 0x1) << 31) - | (init_ext_addr & 0xF) - ); -} - -/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ -static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ - unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ - unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ - unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ - unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ - -#if defined(CONFIG_FSL_DDR3) - if (popts->burst_length == DDR_BL8) { - /* We set BL/2 for fixed BL8 */ - rrt = 0; /* BL/2 clocks */ - wwt = 0; /* BL/2 clocks */ - } else { - /* We need to set BL/2 + 2 to BC4 and OTF */ - rrt = 2; /* BL/2 + 2 clocks */ - wwt = 2; /* BL/2 + 2 clocks */ - } - dll_lock = 1; /* tDLLK = 512 clocks from spec */ -#endif - ddr->timing_cfg_4 = (0 - | ((rwt & 0xf) << 28) - | ((wrt & 0xf) << 24) - | ((rrt & 0xf) << 20) - | ((wwt & 0xf) << 16) - | (dll_lock & 0x3) - ); - debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); -} - -/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ -static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) -{ - unsigned int rodt_on = 0; /* Read to ODT on */ - unsigned int rodt_off = 0; /* Read to ODT off */ - unsigned int wodt_on = 0; /* Write to ODT on */ - unsigned int wodt_off = 0; /* Write to ODT off */ - -#if defined(CONFIG_FSL_DDR3) - /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ - rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1; - rodt_off = 4; /* 4 clocks */ - wodt_on = 1; /* 1 clocks */ - wodt_off = 4; /* 4 clocks */ -#endif - - ddr->timing_cfg_5 = (0 - | ((rodt_on & 0x1f) << 24) - | ((rodt_off & 0x7) << 20) - | ((wodt_on & 0x1f) << 12) - | ((wodt_off & 0x7) << 8) - ); - debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); -} - -/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ -static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) -{ - unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ - /* Normal Operation Full Calibration Time (tZQoper) */ - unsigned int zqoper = 0; - /* Normal Operation Short Calibration Time (tZQCS) */ - unsigned int zqcs = 0; - - if (zq_en) { - zqinit = 9; /* 512 clocks */ - zqoper = 8; /* 256 clocks */ - zqcs = 6; /* 64 clocks */ - } - - ddr->ddr_zq_cntl = (0 - | ((zq_en & 0x1) << 31) - | ((zqinit & 0xF) << 24) - | ((zqoper & 0xF) << 16) - | ((zqcs & 0xF) << 8) - ); - debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); -} - -/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ -static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, - const memctl_options_t *popts) -{ - /* - * First DQS pulse rising edge after margining mode - * is programmed (tWL_MRD) - */ - unsigned int wrlvl_mrd = 0; - /* ODT delay after margining mode is programmed (tWL_ODTEN) */ - unsigned int wrlvl_odten = 0; - /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ - unsigned int wrlvl_dqsen = 0; - /* WRLVL_SMPL: Write leveling sample time */ - unsigned int wrlvl_smpl = 0; - /* WRLVL_WLR: Write leveling repeition time */ - unsigned int wrlvl_wlr = 0; - /* WRLVL_START: Write leveling start time */ - unsigned int wrlvl_start = 0; - - /* suggest enable write leveling for DDR3 due to fly-by topology */ - if (wrlvl_en) { - /* tWL_MRD min = 40 nCK, we set it 64 */ - wrlvl_mrd = 0x6; - /* tWL_ODTEN 128 */ - wrlvl_odten = 0x7; - /* tWL_DQSEN min = 25 nCK, we set it 32 */ - wrlvl_dqsen = 0x5; - /* - * Write leveling sample time at least need 6 clocks - * higher than tWLO to allow enough time for progagation - * delay and sampling the prime data bits. - */ - wrlvl_smpl = 0xf; - /* - * Write leveling repetition time - * at least tWLO + 6 clocks clocks - * we set it 64 - */ - wrlvl_wlr = 0x6; - /* - * Write leveling start time - * The value use for the DQS_ADJUST for the first sample - * when write leveling is enabled. It probably needs to be - * overriden per platform. - */ - wrlvl_start = 0x8; - /* - * Override the write leveling sample and start time - * according to specific board - */ - if (popts->wrlvl_override) { - wrlvl_smpl = popts->wrlvl_sample; - wrlvl_start = popts->wrlvl_start; - } - } - - ddr->ddr_wrlvl_cntl = (0 - | ((wrlvl_en & 0x1) << 31) - | ((wrlvl_mrd & 0x7) << 24) - | ((wrlvl_odten & 0x7) << 20) - | ((wrlvl_dqsen & 0x7) << 16) - | ((wrlvl_smpl & 0xf) << 12) - | ((wrlvl_wlr & 0x7) << 8) - | ((wrlvl_start & 0x1F) << 0) - ); - debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); - ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; - debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); - ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; - debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); - -} - -/* DDR Self Refresh Counter (DDR_SR_CNTR) */ -static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) -{ - /* Self Refresh Idle Threshold */ - ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; -} - -static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - if (popts->addr_hash) { - ddr->ddr_eor = 0x40000000; /* address hash enable */ - puts("Address hashing enabled.\n"); - } -} - -static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - ddr->ddr_cdr1 = popts->ddr_cdr1; - debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); -} - -static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - ddr->ddr_cdr2 = popts->ddr_cdr2; - debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); -} - -unsigned int -check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int res = 0; - - /* - * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are - * not set at the same time. - */ - if (ddr->ddr_sdram_cfg & 0x10000000 - && ddr->ddr_sdram_cfg & 0x00008000) { - printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " - " should not be set at the same time.\n"); - res++; - } - - return res; -} - -unsigned int -compute_fsl_memctl_config_regs(const memctl_options_t *popts, - fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm, - const dimm_params_t *dimm_params, - unsigned int dbw_cap_adj, - unsigned int size_only) -{ - unsigned int i; - unsigned int cas_latency; - unsigned int additive_latency; - unsigned int sr_it; - unsigned int zq_en; - unsigned int wrlvl_en; - unsigned int ip_rev = 0; - unsigned int unq_mrs_en = 0; - int cs_en = 1; - - memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); - - if (common_dimm == NULL) { - printf("Error: subset DIMM params struct null pointer\n"); - return 1; - } - - /* - * Process overrides first. - * - * FIXME: somehow add dereated caslat to this - */ - cas_latency = (popts->cas_latency_override) - ? popts->cas_latency_override_value - : common_dimm->lowest_common_SPD_caslat; - - additive_latency = (popts->additive_latency_override) - ? popts->additive_latency_override_value - : common_dimm->additive_latency; - - sr_it = (popts->auto_self_refresh_en) - ? popts->sr_it - : 0; - /* ZQ calibration */ - zq_en = (popts->zq_en) ? 1 : 0; - /* write leveling */ - wrlvl_en = (popts->wrlvl_en) ? 1 : 0; - - /* Chip Select Memory Bounds (CSn_BNDS) */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - unsigned long long ea, sa; - unsigned int cs_per_dimm - = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; - unsigned int dimm_number - = i / cs_per_dimm; - unsigned long long rank_density - = dimm_params[dimm_number].rank_density >> dbw_cap_adj; - - if (dimm_params[dimm_number].n_ranks == 0) { - debug("Skipping setup of CS%u " - "because n_ranks on DIMM %u is 0\n", i, dimm_number); - continue; - } - if (popts->memctl_interleaving) { - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - break; - case FSL_DDR_CS0_CS1: - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - if (i > 1) - cs_en = 0; - break; - case FSL_DDR_CS2_CS3: - default: - if (i > 0) - cs_en = 0; - break; - } - sa = common_dimm->base_address; - ea = sa + common_dimm->total_mem - 1; - } else if (!popts->memctl_interleaving) { - /* - * If memory interleaving between controllers is NOT - * enabled, the starting address for each memory - * controller is distinct. However, because rank - * interleaving is enabled, the starting and ending - * addresses of the total memory on that memory - * controller needs to be programmed into its - * respective CS0_BNDS. - */ - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - sa = common_dimm->base_address; - ea = sa + common_dimm->total_mem - 1; - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - if ((i >= 2) && (dimm_number == 0)) { - sa = dimm_params[dimm_number].base_address + - 2 * rank_density; - ea = sa + 2 * rank_density - 1; - } else { - sa = dimm_params[dimm_number].base_address; - ea = sa + 2 * rank_density - 1; - } - break; - case FSL_DDR_CS0_CS1: - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (i != 1) - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - if (i == 0) - ea += rank_density; - break; - case FSL_DDR_CS2_CS3: - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (i != 3) - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - if (i == 2) - ea += (rank_density >> dbw_cap_adj); - break; - default: /* No bank(chip-select) interleaving */ - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - break; - } - } - - sa >>= 24; - ea >>= 24; - - if (cs_en) { - ddr->cs[i].bnds = (0 - | ((sa & 0xFFF) << 16)/* starting address MSB */ - | ((ea & 0xFFF) << 0) /* ending address MSB */ - ); - } else { - debug("FSLDDR: setting bnds to 0 for inactive CS\n"); - ddr->cs[i].bnds = 0; - } - - debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); - set_csn_config(dimm_number, i, ddr, popts, dimm_params); - set_csn_config_2(i, ddr); - } - - /* - * In the case we only need to compute the ddr sdram size, we only need - * to set csn registers, so return from here. - */ - if (size_only) - return 0; - - set_ddr_eor(ddr, popts); - -#if !defined(CONFIG_FSL_DDR1) - set_timing_cfg_0(ddr, popts, dimm_params); -#endif - - set_timing_cfg_3(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_2(ddr, popts, common_dimm, - cas_latency, additive_latency); - - set_ddr_cdr1(ddr, popts); - set_ddr_cdr2(ddr, popts); - set_ddr_sdram_cfg(ddr, popts, common_dimm); - ip_rev = fsl_ddr_get_version(); - if (ip_rev > 0x40400) - unq_mrs_en = 1; - - set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); - set_ddr_sdram_mode(ddr, popts, common_dimm, - cas_latency, additive_latency, unq_mrs_en); - set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en); - set_ddr_sdram_interval(ddr, popts, common_dimm); - set_ddr_data_init(ddr); - set_ddr_sdram_clk_cntl(ddr, popts); - set_ddr_init_addr(ddr); - set_ddr_init_ext_addr(ddr); - set_timing_cfg_4(ddr, popts); - set_timing_cfg_5(ddr, cas_latency); - - set_ddr_zq_cntl(ddr, zq_en); - set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); - - set_ddr_sr_cntr(ddr, sr_it); - - set_ddr_sdram_rcw(ddr, popts, common_dimm); - - return check_fsl_memctl_config_regs(ddr); -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h deleted file mode 100644 index 4dd55fc4c3..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef FSL_DDR_MAIN_H -#define FSL_DDR_MAIN_H - -#include -#include - -#include "common_timing_params.h" - -#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) -/* - * Bind the main DDR setup driver's generic names - * to this specific DDR technology. - */ -static __inline__ int -compute_dimm_parameters(const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); -} -#endif - -/* - * Data Structures - * - * All data structures have to be on the stack - */ -#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR - -typedef struct { - generic_spd_eeprom_t - spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; - struct dimm_params_s - dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; - memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; - common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; - fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; -} fsl_ddr_info_t; - -/* Compute steps */ -#define STEP_GET_SPD (1 << 0) -#define STEP_COMPUTE_DIMM_PARMS (1 << 1) -#define STEP_COMPUTE_COMMON_PARMS (1 << 2) -#define STEP_GATHER_OPTS (1 << 3) -#define STEP_ASSIGN_ADDRESSES (1 << 4) -#define STEP_COMPUTE_REGS (1 << 5) -#define STEP_PROGRAM_REGS (1 << 6) -#define STEP_ALL 0xFFF - -unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, - unsigned int size_only); - -const char *step_to_string(unsigned int step); - -unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, - fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm, - const dimm_params_t *dimm_parameters, - unsigned int dbw_capacity_adjust, - unsigned int size_only); -unsigned int compute_lowest_common_dimm_parameters( - const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - unsigned int number_of_dimms); -unsigned int populate_memctl_options(int all_DIMMs_registered, - memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num); -void check_interleaving_options(fsl_ddr_info_t *pinfo); - -unsigned int mclk_to_picos(unsigned int mclk); -unsigned int get_memory_clk_period_ps(void); -unsigned int picos_to_mclk(unsigned int picos); -void fsl_ddr_set_lawbar( - const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); - -int fsl_ddr_interactive_env_var_exists(void); -unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num); - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); - -/* processor specific function */ -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); - -/* board specific function */ -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number); -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c deleted file mode 100644 index 1ed6c77150..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ /dev/null @@ -1,1866 +0,0 @@ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - * York Sun [at freescale.com] - */ - -#include -#include -#include - -#include -#include "ddr.h" - -/* Option parameter Structures */ -struct options_string { - const char *option_name; - size_t offset; - unsigned int size; - const char printhex; -}; - -static unsigned int picos_to_mhz(unsigned int picos) -{ - return 1000000 / picos; -} - -static void print_option_table(const struct options_string *table, - int table_size, - const void *base) -{ - unsigned int i; - unsigned int *ptr; - unsigned long long *ptr_l; - - for (i = 0; i < table_size; i++) { - switch (table[i].size) { - case 4: - ptr = (unsigned int *) (base + table[i].offset); - if (table[i].printhex) { - printf("%s = 0x%08X\n", - table[i].option_name, *ptr); - } else { - printf("%s = %u\n", - table[i].option_name, *ptr); - } - break; - case 8: - ptr_l = (unsigned long long *) (base + table[i].offset); - printf("%s = %llu\n", - table[i].option_name, *ptr_l); - break; - default: - printf("Unrecognized size!\n"); - break; - } - } -} - -static int handle_option_table(const struct options_string *table, - int table_size, - void *base, - const char *opt, - const char *val) -{ - unsigned int i; - unsigned int value, *ptr; - unsigned long long value_l, *ptr_l; - - for (i = 0; i < table_size; i++) { - if (strcmp(table[i].option_name, opt) != 0) - continue; - switch (table[i].size) { - case 4: - value = simple_strtoul(val, NULL, 0); - ptr = base + table[i].offset; - *ptr = value; - break; - case 8: - value_l = simple_strtoull(val, NULL, 0); - ptr_l = base + table[i].offset; - *ptr_l = value_l; - break; - default: - printf("Unrecognized size!\n"); - break; - } - return 1; - } - - return 0; -} - -static void fsl_ddr_generic_edit(void *pdata, - void *pend, - unsigned int element_size, - unsigned int element_num, - unsigned int value) -{ - char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */ - - pcdata += element_num * element_size; - if ((pcdata + element_size) > (char *) pend) { - printf("trying to write past end of data\n"); - return; - } - - switch (element_size) { - case 1: - __raw_writeb(value, pcdata); - break; - case 2: - __raw_writew(value, pcdata); - break; - case 4: - __raw_writel(value, pcdata); - break; - default: - printf("unexpected element size %u\n", element_size); - break; - } -} - -static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - unsigned int dimm_num, - unsigned int element_num, - unsigned int value) -{ - generic_spd_eeprom_t *pspd; - - pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); - fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value); -} - -#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \ - sizeof((common_timing_params_t *)0)->x, 0} - -static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - const char *optname_str, - const char *value_str) -{ - common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; - - static const struct options_string options[] = { - COMMON_TIMING(tCKmin_X_ps), - COMMON_TIMING(tCKmax_ps), - COMMON_TIMING(tCKmax_max_ps), - COMMON_TIMING(tRCD_ps), - COMMON_TIMING(tRP_ps), - COMMON_TIMING(tRAS_ps), - COMMON_TIMING(tWR_ps), - COMMON_TIMING(tWTR_ps), - COMMON_TIMING(tRFC_ps), - COMMON_TIMING(tRRD_ps), - COMMON_TIMING(tRC_ps), - COMMON_TIMING(refresh_rate_ps), - COMMON_TIMING(tIS_ps), - COMMON_TIMING(tIH_ps), - COMMON_TIMING(tDS_ps), - COMMON_TIMING(tDH_ps), - COMMON_TIMING(tRTP_ps), - COMMON_TIMING(tDQSQ_max_ps), - COMMON_TIMING(tQHS_ps), - COMMON_TIMING(ndimms_present), - COMMON_TIMING(lowest_common_SPD_caslat), - COMMON_TIMING(highest_common_derated_caslat), - COMMON_TIMING(additive_latency), - COMMON_TIMING(all_DIMMs_burst_lengths_bitmask), - COMMON_TIMING(all_DIMMs_registered), - COMMON_TIMING(all_DIMMs_unbuffered), - COMMON_TIMING(all_DIMMs_ECC_capable), - COMMON_TIMING(total_mem), - COMMON_TIMING(base_address), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, optname_str, value_str)) - return; - - printf("Error: couldn't find option string %s\n", optname_str); -} - -#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \ - sizeof((dimm_params_t *)0)->x, 0} - -static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - unsigned int dimm_num, - const char *optname_str, - const char *value_str) -{ - dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); - - static const struct options_string options[] = { - DIMM_PARM(n_ranks), - DIMM_PARM(data_width), - DIMM_PARM(primary_sdram_width), - DIMM_PARM(ec_sdram_width), - DIMM_PARM(registered_dimm), - - DIMM_PARM(n_row_addr), - DIMM_PARM(n_col_addr), - DIMM_PARM(edc_config), - DIMM_PARM(n_banks_per_sdram_device), - DIMM_PARM(burst_lengths_bitmask), - DIMM_PARM(row_density), - - DIMM_PARM(tCKmin_X_ps), - DIMM_PARM(tCKmin_X_minus_1_ps), - DIMM_PARM(tCKmin_X_minus_2_ps), - DIMM_PARM(tCKmax_ps), - - DIMM_PARM(caslat_X), - DIMM_PARM(caslat_X_minus_1), - DIMM_PARM(caslat_X_minus_2), - - DIMM_PARM(caslat_lowest_derated), - - DIMM_PARM(tRCD_ps), - DIMM_PARM(tRP_ps), - DIMM_PARM(tRAS_ps), - DIMM_PARM(tWR_ps), - DIMM_PARM(tWTR_ps), - DIMM_PARM(tRFC_ps), - DIMM_PARM(tRRD_ps), - DIMM_PARM(tRC_ps), - DIMM_PARM(refresh_rate_ps), - - DIMM_PARM(tIS_ps), - DIMM_PARM(tIH_ps), - DIMM_PARM(tDS_ps), - DIMM_PARM(tDH_ps), - DIMM_PARM(tRTP_ps), - DIMM_PARM(tDQSQ_max_ps), - DIMM_PARM(tQHS_ps), - - DIMM_PARM(rank_density), - DIMM_PARM(capacity), - DIMM_PARM(base_address), - }; - - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, optname_str, value_str)) - return; - - printf("couldn't find option string %s\n", optname_str); -} - -static void print_dimm_parameters(const dimm_params_t *pdimm) -{ - static const struct options_string options[] = { - DIMM_PARM(n_ranks), - DIMM_PARM(data_width), - DIMM_PARM(primary_sdram_width), - DIMM_PARM(ec_sdram_width), - DIMM_PARM(registered_dimm), - - DIMM_PARM(n_row_addr), - DIMM_PARM(n_col_addr), - DIMM_PARM(edc_config), - DIMM_PARM(n_banks_per_sdram_device), - - DIMM_PARM(tCKmin_X_ps), - DIMM_PARM(tCKmin_X_minus_1_ps), - DIMM_PARM(tCKmin_X_minus_2_ps), - DIMM_PARM(tCKmax_ps), - - DIMM_PARM(caslat_X), - DIMM_PARM(tAA_ps), - DIMM_PARM(caslat_X_minus_1), - DIMM_PARM(caslat_X_minus_2), - DIMM_PARM(caslat_lowest_derated), - - DIMM_PARM(tRCD_ps), - DIMM_PARM(tRP_ps), - DIMM_PARM(tRAS_ps), - DIMM_PARM(tWR_ps), - DIMM_PARM(tWTR_ps), - DIMM_PARM(tRFC_ps), - DIMM_PARM(tRRD_ps), - DIMM_PARM(tRC_ps), - DIMM_PARM(refresh_rate_ps), - - DIMM_PARM(tIS_ps), - DIMM_PARM(tIH_ps), - DIMM_PARM(tDS_ps), - DIMM_PARM(tDH_ps), - DIMM_PARM(tRTP_ps), - DIMM_PARM(tDQSQ_max_ps), - DIMM_PARM(tQHS_ps), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (pdimm->n_ranks == 0) { - printf("DIMM not present\n"); - return; - } - printf("DIMM organization parameters:\n"); - printf("module part name = %s\n", pdimm->mpart); - printf("rank_density = %llu bytes (%llu megabytes)\n", - pdimm->rank_density, pdimm->rank_density / 0x100000); - printf("capacity = %llu bytes (%llu megabytes)\n", - pdimm->capacity, pdimm->capacity / 0x100000); - printf("burst_lengths_bitmask = %02X\n", - pdimm->burst_lengths_bitmask); - printf("base_addresss = %llu (%08llX %08llX)\n", - pdimm->base_address, - (pdimm->base_address >> 32), - pdimm->base_address & 0xFFFFFFFF); - print_option_table(options, n_opts, pdimm); -} - -static void print_lowest_common_dimm_parameters( - const common_timing_params_t *plcd_dimm_params) -{ - static const struct options_string options[] = { - COMMON_TIMING(tCKmax_max_ps), - COMMON_TIMING(tRCD_ps), - COMMON_TIMING(tRP_ps), - COMMON_TIMING(tRAS_ps), - COMMON_TIMING(tWR_ps), - COMMON_TIMING(tWTR_ps), - COMMON_TIMING(tRFC_ps), - COMMON_TIMING(tRRD_ps), - COMMON_TIMING(tRC_ps), - COMMON_TIMING(refresh_rate_ps), - COMMON_TIMING(tIS_ps), - COMMON_TIMING(tDS_ps), - COMMON_TIMING(tDH_ps), - COMMON_TIMING(tRTP_ps), - COMMON_TIMING(tDQSQ_max_ps), - COMMON_TIMING(tQHS_ps), - COMMON_TIMING(lowest_common_SPD_caslat), - COMMON_TIMING(highest_common_derated_caslat), - COMMON_TIMING(additive_latency), - COMMON_TIMING(ndimms_present), - COMMON_TIMING(all_DIMMs_registered), - COMMON_TIMING(all_DIMMs_unbuffered), - COMMON_TIMING(all_DIMMs_ECC_capable), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - /* Clock frequencies */ - printf("tCKmin_X_ps = %u (%u MHz)\n", - plcd_dimm_params->tCKmin_X_ps, - picos_to_mhz(plcd_dimm_params->tCKmin_X_ps)); - printf("tCKmax_ps = %u (%u MHz)\n", - plcd_dimm_params->tCKmax_ps, - picos_to_mhz(plcd_dimm_params->tCKmax_ps)); - printf("all_DIMMs_burst_lengths_bitmask = %02X\n", - plcd_dimm_params->all_DIMMs_burst_lengths_bitmask); - - print_option_table(options, n_opts, plcd_dimm_params); - - printf("total_mem = %llu (%llu megabytes)\n", - plcd_dimm_params->total_mem, - plcd_dimm_params->total_mem / 0x100000); - printf("base_address = %llu (%llu megabytes)\n", - plcd_dimm_params->base_address, - plcd_dimm_params->base_address / 0x100000); -} - -#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \ - sizeof((memctl_options_t *)0)->x, 0} -#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \ - offsetof(memctl_options_t, cs_local_opts[x].y), \ - sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0} - -static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, - unsigned int ctl_num, - const char *optname_str, - const char *value_str) -{ - memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]); - /* - * This array all on the stack and *computed* each time this - * function is rung. - */ - static const struct options_string options[] = { - CTRL_OPTIONS_CS(0, odt_rd_cfg), - CTRL_OPTIONS_CS(0, odt_wr_cfg), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rd_cfg), - CTRL_OPTIONS_CS(1, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rd_cfg), - CTRL_OPTIONS_CS(2, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(3, odt_rd_cfg), - CTRL_OPTIONS_CS(3, odt_wr_cfg), -#endif -#if defined(CONFIG_FSL_DDR3) - CTRL_OPTIONS_CS(0, odt_rtt_norm), - CTRL_OPTIONS_CS(0, odt_rtt_wr), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rtt_norm), - CTRL_OPTIONS_CS(1, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rtt_norm), - CTRL_OPTIONS_CS(2, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(3, odt_rtt_norm), - CTRL_OPTIONS_CS(3, odt_rtt_wr), -#endif -#endif - CTRL_OPTIONS(memctl_interleaving), - CTRL_OPTIONS(memctl_interleaving_mode), - CTRL_OPTIONS(ba_intlv_ctl), - CTRL_OPTIONS(ECC_mode), - CTRL_OPTIONS(ECC_init_using_memctl), - CTRL_OPTIONS(DQS_config), - CTRL_OPTIONS(self_refresh_in_sleep), - CTRL_OPTIONS(dynamic_power), - CTRL_OPTIONS(data_bus_width), - CTRL_OPTIONS(burst_length), - CTRL_OPTIONS(cas_latency_override), - CTRL_OPTIONS(cas_latency_override_value), - CTRL_OPTIONS(use_derated_caslat), - CTRL_OPTIONS(additive_latency_override), - CTRL_OPTIONS(additive_latency_override_value), - CTRL_OPTIONS(clk_adjust), - CTRL_OPTIONS(cpo_override), - CTRL_OPTIONS(write_data_delay), - CTRL_OPTIONS(half_strength_driver_enable), - - /* - * These can probably be changed to 2T_EN and 3T_EN - * (using a leading numerical character) without problem - */ - CTRL_OPTIONS(twoT_en), - CTRL_OPTIONS(threeT_en), - CTRL_OPTIONS(ap_en), - CTRL_OPTIONS(bstopre), - CTRL_OPTIONS(wrlvl_override), - CTRL_OPTIONS(wrlvl_sample), - CTRL_OPTIONS(wrlvl_start), - CTRL_OPTIONS(rcw_override), - CTRL_OPTIONS(rcw_1), - CTRL_OPTIONS(rcw_2), - CTRL_OPTIONS(ddr_cdr1), - CTRL_OPTIONS(ddr_cdr2), - CTRL_OPTIONS(tCKE_clock_pulse_width_ps), - CTRL_OPTIONS(tFAW_window_four_activates_ps), - CTRL_OPTIONS(trwt_override), - CTRL_OPTIONS(trwt), - }; - - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, - optname_str, value_str)) - return; - - printf("couldn't find option string %s\n", optname_str); -} - -#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \ - sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1} -#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \ - offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \ - sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1} - -static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int i; - static const struct options_string options[] = { - CFG_REGS_CS(0, bnds), - CFG_REGS_CS(0, config), - CFG_REGS_CS(0, config_2), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CFG_REGS_CS(1, bnds), - CFG_REGS_CS(1, config), - CFG_REGS_CS(1, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(2, bnds), - CFG_REGS_CS(2, config), - CFG_REGS_CS(2, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(3, bnds), - CFG_REGS_CS(3, config), - CFG_REGS_CS(3, config_2), -#endif - CFG_REGS(timing_cfg_3), - CFG_REGS(timing_cfg_0), - CFG_REGS(timing_cfg_1), - CFG_REGS(timing_cfg_2), - CFG_REGS(ddr_sdram_cfg), - CFG_REGS(ddr_sdram_cfg_2), - CFG_REGS(ddr_sdram_mode), - CFG_REGS(ddr_sdram_mode_2), - CFG_REGS(ddr_sdram_mode_3), - CFG_REGS(ddr_sdram_mode_4), - CFG_REGS(ddr_sdram_mode_5), - CFG_REGS(ddr_sdram_mode_6), - CFG_REGS(ddr_sdram_mode_7), - CFG_REGS(ddr_sdram_mode_8), - CFG_REGS(ddr_sdram_interval), - CFG_REGS(ddr_data_init), - CFG_REGS(ddr_sdram_clk_cntl), - CFG_REGS(ddr_init_addr), - CFG_REGS(ddr_init_ext_addr), - CFG_REGS(timing_cfg_4), - CFG_REGS(timing_cfg_5), - CFG_REGS(ddr_zq_cntl), - CFG_REGS(ddr_wrlvl_cntl), - CFG_REGS(ddr_wrlvl_cntl_2), - CFG_REGS(ddr_wrlvl_cntl_3), - CFG_REGS(ddr_sr_cntr), - CFG_REGS(ddr_sdram_rcw_1), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_cdr1), - CFG_REGS(ddr_cdr2), - CFG_REGS(err_disable), - CFG_REGS(err_int_en), - CFG_REGS(ddr_eor), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - print_option_table(options, n_opts, ddr); - - for (i = 0; i < 32; i++) - printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); -} - -static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - const char *regname, - const char *value_str) -{ - unsigned int i; - fsl_ddr_cfg_regs_t *ddr; - char buf[20]; - static const struct options_string options[] = { - CFG_REGS_CS(0, bnds), - CFG_REGS_CS(0, config), - CFG_REGS_CS(0, config_2), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CFG_REGS_CS(1, bnds), - CFG_REGS_CS(1, config), - CFG_REGS_CS(1, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(2, bnds), - CFG_REGS_CS(2, config), - CFG_REGS_CS(2, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CFG_REGS_CS(3, bnds), - CFG_REGS_CS(3, config), - CFG_REGS_CS(3, config_2), -#endif - CFG_REGS(timing_cfg_3), - CFG_REGS(timing_cfg_0), - CFG_REGS(timing_cfg_1), - CFG_REGS(timing_cfg_2), - CFG_REGS(ddr_sdram_cfg), - CFG_REGS(ddr_sdram_cfg_2), - CFG_REGS(ddr_sdram_mode), - CFG_REGS(ddr_sdram_mode_2), - CFG_REGS(ddr_sdram_mode_3), - CFG_REGS(ddr_sdram_mode_4), - CFG_REGS(ddr_sdram_mode_5), - CFG_REGS(ddr_sdram_mode_6), - CFG_REGS(ddr_sdram_mode_7), - CFG_REGS(ddr_sdram_mode_8), - CFG_REGS(ddr_sdram_interval), - CFG_REGS(ddr_data_init), - CFG_REGS(ddr_sdram_clk_cntl), - CFG_REGS(ddr_init_addr), - CFG_REGS(ddr_init_ext_addr), - CFG_REGS(timing_cfg_4), - CFG_REGS(timing_cfg_5), - CFG_REGS(ddr_zq_cntl), - CFG_REGS(ddr_wrlvl_cntl), - CFG_REGS(ddr_wrlvl_cntl_2), - CFG_REGS(ddr_wrlvl_cntl_3), - CFG_REGS(ddr_sr_cntr), - CFG_REGS(ddr_sdram_rcw_1), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_cdr1), - CFG_REGS(ddr_cdr2), - CFG_REGS(err_disable), - CFG_REGS(err_int_en), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_eor), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - debug("fsl_ddr_regs_edit: ctrl_num = %u, " - "regname = %s, value = %s\n", - ctrl_num, regname, value_str); - if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS) - return; - - ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); - - if (handle_option_table(options, n_opts, ddr, regname, value_str)) - return; - - for (i = 0; i < 32; i++) { - unsigned int value = simple_strtoul(value_str, NULL, 0); - sprintf(buf, "debug_%u", i + 1); - if (strcmp(buf, regname) == 0) { - ddr->debug[i] = value; - return; - } - } - printf("Error: couldn't find register string %s\n", regname); -} - -#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \ - sizeof((memctl_options_t *)0)->x, 1} - -static void print_memctl_options(const memctl_options_t *popts) -{ - static const struct options_string options[] = { - CTRL_OPTIONS_CS(0, odt_rd_cfg), - CTRL_OPTIONS_CS(0, odt_wr_cfg), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rd_cfg), - CTRL_OPTIONS_CS(1, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rd_cfg), - CTRL_OPTIONS_CS(2, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CTRL_OPTIONS_CS(3, odt_rd_cfg), - CTRL_OPTIONS_CS(3, odt_wr_cfg), -#endif -#if defined(CONFIG_FSL_DDR3) - CTRL_OPTIONS_CS(0, odt_rtt_norm), - CTRL_OPTIONS_CS(0, odt_rtt_wr), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rtt_norm), - CTRL_OPTIONS_CS(1, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rtt_norm), - CTRL_OPTIONS_CS(2, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CTRL_OPTIONS_CS(3, odt_rtt_norm), - CTRL_OPTIONS_CS(3, odt_rtt_wr), -#endif -#endif - CTRL_OPTIONS(memctl_interleaving), - CTRL_OPTIONS(memctl_interleaving_mode), - CTRL_OPTIONS_HEX(ba_intlv_ctl), - CTRL_OPTIONS(ECC_mode), - CTRL_OPTIONS(ECC_init_using_memctl), - CTRL_OPTIONS(DQS_config), - CTRL_OPTIONS(self_refresh_in_sleep), - CTRL_OPTIONS(dynamic_power), - CTRL_OPTIONS(data_bus_width), - CTRL_OPTIONS(burst_length), - CTRL_OPTIONS(cas_latency_override), - CTRL_OPTIONS(cas_latency_override_value), - CTRL_OPTIONS(use_derated_caslat), - CTRL_OPTIONS(additive_latency_override), - CTRL_OPTIONS(additive_latency_override_value), - CTRL_OPTIONS(clk_adjust), - CTRL_OPTIONS(cpo_override), - CTRL_OPTIONS(write_data_delay), - CTRL_OPTIONS(half_strength_driver_enable), - /* - * These can probably be changed to 2T_EN and 3T_EN - * (using a leading numerical character) without problem - */ - CTRL_OPTIONS(twoT_en), - CTRL_OPTIONS(threeT_en), - CTRL_OPTIONS(registered_dimm_en), - CTRL_OPTIONS(ap_en), - CTRL_OPTIONS(bstopre), - CTRL_OPTIONS(wrlvl_override), - CTRL_OPTIONS(wrlvl_sample), - CTRL_OPTIONS(wrlvl_start), - CTRL_OPTIONS(rcw_override), - CTRL_OPTIONS(rcw_1), - CTRL_OPTIONS(rcw_2), - CTRL_OPTIONS_HEX(ddr_cdr1), - CTRL_OPTIONS_HEX(ddr_cdr2), - CTRL_OPTIONS(tCKE_clock_pulse_width_ps), - CTRL_OPTIONS(tFAW_window_four_activates_ps), - CTRL_OPTIONS(trwt_override), - CTRL_OPTIONS(trwt), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - print_option_table(options, n_opts, popts); -} - -#ifdef CONFIG_FSL_DDR1 -void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd) -{ - unsigned int i; - - printf("%-3d : %02x %s\n", 0, spd->info_size, - " spd->info_size, * 0 # bytes written into serial memory *"); - printf("%-3d : %02x %s\n", 1, spd->chip_size, - " spd->chip_size, * 1 Total # bytes of SPD memory device *"); - printf("%-3d : %02x %s\n", 2, spd->mem_type, - " spd->mem_type, * 2 Fundamental memory type *"); - printf("%-3d : %02x %s\n", 3, spd->nrow_addr, - " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); - printf("%-3d : %02x %s\n", 4, spd->ncol_addr, - " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); - printf("%-3d : %02x %s\n", 5, spd->nrows, - " spd->nrows * 5 # of DIMM Banks *"); - printf("%-3d : %02x %s\n", 6, spd->dataw_lsb, - " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); - printf("%-3d : %02x %s\n", 7, spd->dataw_msb, - " spd->dataw_msb, * 7 Data Width msb of this assembly *"); - printf("%-3d : %02x %s\n", 8, spd->voltage, - " spd->voltage, * 8 Voltage intf std of this assembly *"); - printf("%-3d : %02x %s\n", 9, spd->clk_cycle, - " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); - printf("%-3d : %02x %s\n", 10, spd->clk_access, - " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); - printf("%-3d : %02x %s\n", 11, spd->config, - " spd->config, * 11 DIMM Configuration type *"); - printf("%-3d : %02x %s\n", 12, spd->refresh, - " spd->refresh, * 12 Refresh Rate/Type *"); - printf("%-3d : %02x %s\n", 13, spd->primw, - " spd->primw, * 13 Primary SDRAM Width *"); - printf("%-3d : %02x %s\n", 14, spd->ecw, - " spd->ecw, * 14 Error Checking SDRAM width *"); - printf("%-3d : %02x %s\n", 15, spd->min_delay, - " spd->min_delay, * 15 Back to Back Random Access *"); - printf("%-3d : %02x %s\n", 16, spd->burstl, - " spd->burstl, * 16 Burst Lengths Supported *"); - printf("%-3d : %02x %s\n", 17, spd->nbanks, - " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); - printf("%-3d : %02x %s\n", 18, spd->cas_lat, - " spd->cas_lat, * 18 CAS# Latencies Supported *"); - printf("%-3d : %02x %s\n", 19, spd->cs_lat, - " spd->cs_lat, * 19 Chip Select Latency *"); - printf("%-3d : %02x %s\n", 20, spd->write_lat, - " spd->write_lat, * 20 Write Latency/Recovery *"); - printf("%-3d : %02x %s\n", 21, spd->mod_attr, - " spd->mod_attr, * 21 SDRAM Module Attributes *"); - printf("%-3d : %02x %s\n", 22, spd->dev_attr, - " spd->dev_attr, * 22 SDRAM Device Attributes *"); - printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, - " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); - printf("%-3d : %02x %s\n", 24, spd->clk_access2, - " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); - printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, - " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); - printf("%-3d : %02x %s\n", 26, spd->clk_access3, - " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); - printf("%-3d : %02x %s\n", 27, spd->trp, - " spd->trp, * 27 Min Row Precharge Time (tRP)*"); - printf("%-3d : %02x %s\n", 28, spd->trrd, - " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); - printf("%-3d : %02x %s\n", 29, spd->trcd, - " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); - printf("%-3d : %02x %s\n", 30, spd->tras, - " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); - printf("%-3d : %02x %s\n", 31, spd->bank_dens, - " spd->bank_dens, * 31 Density of each bank on module *"); - printf("%-3d : %02x %s\n", 32, spd->ca_setup, - " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); - printf("%-3d : %02x %s\n", 33, spd->ca_hold, - " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); - printf("%-3d : %02x %s\n", 34, spd->data_setup, - " spd->data_setup, * 34 Data signal input setup time *"); - printf("%-3d : %02x %s\n", 35, spd->data_hold, - " spd->data_hold, * 35 Data signal input hold time *"); - printf("%-3d : %02x %s\n", 36, spd->res_36_40[0], - " spd->res_36_40[0], * 36 Reserved / tWR *"); - printf("%-3d : %02x %s\n", 37, spd->res_36_40[1], - " spd->res_36_40[1], * 37 Reserved / tWTR *"); - printf("%-3d : %02x %s\n", 38, spd->res_36_40[2], - " spd->res_36_40[2], * 38 Reserved / tRTP *"); - printf("%-3d : %02x %s\n", 39, spd->res_36_40[3], - " spd->res_36_40[3], * 39 Reserved / mem_probe *"); - printf("%-3d : %02x %s\n", 40, spd->res_36_40[4], - " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); - printf("%-3d : %02x %s\n", 41, spd->trc, - " spd->trc, * 41 Min Active to Auto refresh time tRC *"); - printf("%-3d : %02x %s\n", 42, spd->trfc, - " spd->trfc, * 42 Min Auto to Active period tRFC *"); - printf("%-3d : %02x %s\n", 43, spd->tckmax, - " spd->tckmax, * 43 Max device cycle time tCKmax *"); - printf("%-3d : %02x %s\n", 44, spd->tdqsq, - " spd->tdqsq, * 44 Max DQS to DQ skew *"); - printf("%-3d : %02x %s\n", 45, spd->tqhs, - " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); - printf("%-3d : %02x %s\n", 46, spd->res_46, - " spd->res_46, * 46 Reserved/ PLL Relock time *"); - printf("%-3d : %02x %s\n", 47, spd->dimm_height, - " spd->dimm_height * 47 SDRAM DIMM Height *"); - - printf("%-3d-%3d: ", 48, 61); - - for (i = 0; i < 14; i++) - printf("%02x", spd->res_48_61[i]); - - printf(" * 48-61 IDD in SPD and Reserved space *\n"); - - printf("%-3d : %02x %s\n", 62, spd->spd_rev, - " spd->spd_rev, * 62 SPD Data Revision Code *"); - printf("%-3d : %02x %s\n", 63, spd->cksum, - " spd->cksum, * 63 Checksum for bytes 0-62 *"); - printf("%-3d-%3d: ", 64, 71); - - for (i = 0; i < 8; i++) - printf("%02x", spd->mid[i]); - - printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); - printf("%-3d : %02x %s\n", 72, spd->mloc, - " spd->mloc, * 72 Manufacturing Location *"); - - printf("%-3d-%3d: >>", 73, 90); - - for (i = 0; i < 18; i++) - printf("%c", spd->mpart[i]); - - printf("<<* 73 Manufacturer's Part Number *\n"); - - printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], - "* 91 Revision Code *"); - printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], - "* 93 Manufacturing Date *"); - printf("%-3d-%3d: ", 95, 98); - - for (i = 0; i < 4; i++) - printf("%02x", spd->sernum[i]); - - printf("* 95 Assembly Serial Number *\n"); - - printf("%-3d-%3d: ", 99, 127); - - for (i = 0; i < 27; i++) - printf("%02x", spd->mspec[i]); - - printf("* 99 Manufacturer Specific Data *\n"); -} -#endif - -#ifdef CONFIG_FSL_DDR2 -void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) -{ - unsigned int i; - - printf("%-3d : %02x %s\n", 0, spd->info_size, - " spd->info_size, * 0 # bytes written into serial memory *"); - printf("%-3d : %02x %s\n", 1, spd->chip_size, - " spd->chip_size, * 1 Total # bytes of SPD memory device *"); - printf("%-3d : %02x %s\n", 2, spd->mem_type, - " spd->mem_type, * 2 Fundamental memory type *"); - printf("%-3d : %02x %s\n", 3, spd->nrow_addr, - " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); - printf("%-3d : %02x %s\n", 4, spd->ncol_addr, - " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); - printf("%-3d : %02x %s\n", 5, spd->mod_ranks, - " spd->mod_ranks * 5 # of Module Rows on this assembly *"); - printf("%-3d : %02x %s\n", 6, spd->dataw, - " spd->dataw, * 6 Data Width of this assembly *"); - printf("%-3d : %02x %s\n", 7, spd->res_7, - " spd->res_7, * 7 Reserved *"); - printf("%-3d : %02x %s\n", 8, spd->voltage, - " spd->voltage, * 8 Voltage intf std of this assembly *"); - printf("%-3d : %02x %s\n", 9, spd->clk_cycle, - " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); - printf("%-3d : %02x %s\n", 10, spd->clk_access, - " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); - printf("%-3d : %02x %s\n", 11, spd->config, - " spd->config, * 11 DIMM Configuration type *"); - printf("%-3d : %02x %s\n", 12, spd->refresh, - " spd->refresh, * 12 Refresh Rate/Type *"); - printf("%-3d : %02x %s\n", 13, spd->primw, - " spd->primw, * 13 Primary SDRAM Width *"); - printf("%-3d : %02x %s\n", 14, spd->ecw, - " spd->ecw, * 14 Error Checking SDRAM width *"); - printf("%-3d : %02x %s\n", 15, spd->res_15, - " spd->res_15, * 15 Reserved *"); - printf("%-3d : %02x %s\n", 16, spd->burstl, - " spd->burstl, * 16 Burst Lengths Supported *"); - printf("%-3d : %02x %s\n", 17, spd->nbanks, - " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); - printf("%-3d : %02x %s\n", 18, spd->cas_lat, - " spd->cas_lat, * 18 CAS# Latencies Supported *"); - printf("%-3d : %02x %s\n", 19, spd->mech_char, - " spd->mech_char, * 19 Mechanical Characteristics *"); - printf("%-3d : %02x %s\n", 20, spd->dimm_type, - " spd->dimm_type, * 20 DIMM type *"); - printf("%-3d : %02x %s\n", 21, spd->mod_attr, - " spd->mod_attr, * 21 SDRAM Module Attributes *"); - printf("%-3d : %02x %s\n", 22, spd->dev_attr, - " spd->dev_attr, * 22 SDRAM Device Attributes *"); - printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, - " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); - printf("%-3d : %02x %s\n", 24, spd->clk_access2, - " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); - printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, - " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); - printf("%-3d : %02x %s\n", 26, spd->clk_access3, - " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); - printf("%-3d : %02x %s\n", 27, spd->trp, - " spd->trp, * 27 Min Row Precharge Time (tRP)*"); - printf("%-3d : %02x %s\n", 28, spd->trrd, - " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); - printf("%-3d : %02x %s\n", 29, spd->trcd, - " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); - printf("%-3d : %02x %s\n", 30, spd->tras, - " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); - printf("%-3d : %02x %s\n", 31, spd->rank_dens, - " spd->rank_dens, * 31 Density of each rank on module *"); - printf("%-3d : %02x %s\n", 32, spd->ca_setup, - " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); - printf("%-3d : %02x %s\n", 33, spd->ca_hold, - " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); - printf("%-3d : %02x %s\n", 34, spd->data_setup, - " spd->data_setup, * 34 Data signal input setup time *"); - printf("%-3d : %02x %s\n", 35, spd->data_hold, - " spd->data_hold, * 35 Data signal input hold time *"); - printf("%-3d : %02x %s\n", 36, spd->twr, - " spd->twr, * 36 Write Recovery time tWR *"); - printf("%-3d : %02x %s\n", 37, spd->twtr, - " spd->twtr, * 37 Int write to read delay tWTR *"); - printf("%-3d : %02x %s\n", 38, spd->trtp, - " spd->trtp, * 38 Int read to precharge delay tRTP *"); - printf("%-3d : %02x %s\n", 39, spd->mem_probe, - " spd->mem_probe, * 39 Mem analysis probe characteristics *"); - printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext, - " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); - printf("%-3d : %02x %s\n", 41, spd->trc, - " spd->trc, * 41 Min Active to Auto refresh time tRC *"); - printf("%-3d : %02x %s\n", 42, spd->trfc, - " spd->trfc, * 42 Min Auto to Active period tRFC *"); - printf("%-3d : %02x %s\n", 43, spd->tckmax, - " spd->tckmax, * 43 Max device cycle time tCKmax *"); - printf("%-3d : %02x %s\n", 44, spd->tdqsq, - " spd->tdqsq, * 44 Max DQS to DQ skew *"); - printf("%-3d : %02x %s\n", 45, spd->tqhs, - " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); - printf("%-3d : %02x %s\n", 46, spd->pll_relock, - " spd->pll_relock, * 46 PLL Relock time *"); - printf("%-3d : %02x %s\n", 47, spd->Tcasemax, - " spd->Tcasemax, * 47 Tcasemax *"); - printf("%-3d : %02x %s\n", 48, spd->psiTAdram, - " spd->psiTAdram, * 48 Thermal Resistance of DRAM Package " - "from Top (Case) to Ambient (Psi T-A DRAM) *"); - printf("%-3d : %02x %s\n", 49, spd->dt0_mode, - " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " - "Ambient due to Activate-Precharge/Mode Bits " - "(DT0/Mode Bits) *)"); - printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q, - " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from " - "Ambient due to Precharge/Quiet Standby " - "(DT2N/DT2Q) *"); - printf("%-3d : %02x %s\n", 51, spd->dt2p, - " spd->dt2p, * 51 DRAM Case Temperature Rise from " - "Ambient due to Precharge Power-Down (DT2P) *"); - printf("%-3d : %02x %s\n", 52, spd->dt3n, - " spd->dt3n, * 52 DRAM Case Temperature Rise from " - "Ambient due to Active Standby (DT3N) *"); - printf("%-3d : %02x %s\n", 53, spd->dt3pfast, - " spd->dt3pfast, * 53 DRAM Case Temperature Rise from " - "Ambient due to Active Power-Down with Fast PDN Exit " - "(DT3Pfast) *"); - printf("%-3d : %02x %s\n", 54, spd->dt3pslow, - " spd->dt3pslow, * 54 DRAM Case Temperature Rise from " - "Ambient due to Active Power-Down with Slow PDN Exit " - "(DT3Pslow) *"); - printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w, - " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from " - "Ambient due to Page Open Burst Read/DT4R4W Mode Bit " - "(DT4R/DT4R4W Mode Bit) *"); - printf("%-3d : %02x %s\n", 56, spd->dt5b, - " spd->dt5b, * 56 DRAM Case Temperature Rise from " - "Ambient due to Burst Refresh (DT5B) *"); - printf("%-3d : %02x %s\n", 57, spd->dt7, - " spd->dt7, * 57 DRAM Case Temperature Rise from " - "Ambient due to Bank Interleave Reads with " - "Auto-Precharge (DT7) *"); - printf("%-3d : %02x %s\n", 58, spd->psiTApll, - " spd->psiTApll, * 58 Thermal Resistance of PLL Package form" - " Top (Case) to Ambient (Psi T-A PLL) *"); - printf("%-3d : %02x %s\n", 59, spd->psiTAreg, - " spd->psiTAreg, * 59 Thermal Reisitance of Register Package" - " from Top (Case) to Ambient (Psi T-A Register) *"); - printf("%-3d : %02x %s\n", 60, spd->dtpllactive, - " spd->dtpllactive, * 60 PLL Case Temperature Rise from " - "Ambient due to PLL Active (DT PLL Active) *"); - printf("%-3d : %02x %s\n", 61, spd->dtregact, - " spd->dtregact, " - "* 61 Register Case Temperature Rise from Ambient due to " - "Register Active/Mode Bit (DT Register Active/Mode Bit) *"); - printf("%-3d : %02x %s\n", 62, spd->spd_rev, - " spd->spd_rev, * 62 SPD Data Revision Code *"); - printf("%-3d : %02x %s\n", 63, spd->cksum, - " spd->cksum, * 63 Checksum for bytes 0-62 *"); - - printf("%-3d-%3d: ", 64, 71); - - for (i = 0; i < 8; i++) - printf("%02x", spd->mid[i]); - - printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); - - printf("%-3d : %02x %s\n", 72, spd->mloc, - " spd->mloc, * 72 Manufacturing Location *"); - - printf("%-3d-%3d: >>", 73, 90); - for (i = 0; i < 18; i++) - printf("%c", spd->mpart[i]); - - - printf("<<* 73 Manufacturer's Part Number *\n"); - - printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], - "* 91 Revision Code *"); - printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], - "* 93 Manufacturing Date *"); - printf("%-3d-%3d: ", 95, 98); - - for (i = 0; i < 4; i++) - printf("%02x", spd->sernum[i]); - - printf("* 95 Assembly Serial Number *\n"); - - printf("%-3d-%3d: ", 99, 127); - for (i = 0; i < 27; i++) - printf("%02x", spd->mspec[i]); - - - printf("* 99 Manufacturer Specific Data *\n"); -} -#endif - -#ifdef CONFIG_FSL_DDR3 -void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) -{ - unsigned int i; - - /* General Section: Bytes 0-59 */ - -#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); -#define PRINT_NNXXS(n0, n1, x0, x1, s) \ - printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); - - PRINT_NXS(0, spd->info_size_crc, - "info_size_crc bytes written into serial memory, " - "CRC coverage"); - PRINT_NXS(1, spd->spd_rev, - "spd_rev SPD Revision"); - PRINT_NXS(2, spd->mem_type, - "mem_type Key Byte / DRAM Device Type"); - PRINT_NXS(3, spd->module_type, - "module_type Key Byte / Module Type"); - PRINT_NXS(4, spd->density_banks, - "density_banks SDRAM Density and Banks"); - PRINT_NXS(5, spd->addressing, - "addressing SDRAM Addressing"); - PRINT_NXS(6, spd->module_vdd, - "module_vdd Module Nominal Voltage, VDD"); - PRINT_NXS(7, spd->organization, - "organization Module Organization"); - PRINT_NXS(8, spd->bus_width, - "bus_width Module Memory Bus Width"); - PRINT_NXS(9, spd->ftb_div, - "ftb_div Fine Timebase (FTB) Dividend / Divisor"); - PRINT_NXS(10, spd->mtb_dividend, - "mtb_dividend Medium Timebase (MTB) Dividend"); - PRINT_NXS(11, spd->mtb_divisor, - "mtb_divisor Medium Timebase (MTB) Divisor"); - PRINT_NXS(12, spd->tCK_min, - "tCK_min SDRAM Minimum Cycle Time"); - PRINT_NXS(13, spd->res_13, - "res_13 Reserved"); - PRINT_NXS(14, spd->caslat_lsb, - "caslat_lsb CAS Latencies Supported, LSB"); - PRINT_NXS(15, spd->caslat_msb, - "caslat_msb CAS Latencies Supported, MSB"); - PRINT_NXS(16, spd->tAA_min, - "tAA_min Min CAS Latency Time"); - PRINT_NXS(17, spd->tWR_min, - "tWR_min Min Write REcovery Time"); - PRINT_NXS(18, spd->tRCD_min, - "tRCD_min Min RAS# to CAS# Delay Time"); - PRINT_NXS(19, spd->tRRD_min, - "tRRD_min Min Row Active to Row Active Delay Time"); - PRINT_NXS(20, spd->tRP_min, - "tRP_min Min Row Precharge Delay Time"); - PRINT_NXS(21, spd->tRAS_tRC_ext, - "tRAS_tRC_ext Upper Nibbles for tRAS and tRC"); - PRINT_NXS(22, spd->tRAS_min_lsb, - "tRAS_min_lsb Min Active to Precharge Delay Time, LSB"); - PRINT_NXS(23, spd->tRC_min_lsb, - "tRC_min_lsb Min Active to Active/Refresh Delay Time, LSB"); - PRINT_NXS(24, spd->tRFC_min_lsb, - "tRFC_min_lsb Min Refresh Recovery Delay Time LSB"); - PRINT_NXS(25, spd->tRFC_min_msb, - "tRFC_min_msb Min Refresh Recovery Delay Time MSB"); - PRINT_NXS(26, spd->tWTR_min, - "tWTR_min Min Internal Write to Read Command Delay Time"); - PRINT_NXS(27, spd->tRTP_min, - "tRTP_min " - "Min Internal Read to Precharge Command Delay Time"); - PRINT_NXS(28, spd->tFAW_msb, - "tFAW_msb Upper Nibble for tFAW"); - PRINT_NXS(29, spd->tFAW_min, - "tFAW_min Min Four Activate Window Delay Time"); - PRINT_NXS(30, spd->opt_features, - "opt_features SDRAM Optional Features"); - PRINT_NXS(31, spd->therm_ref_opt, - "therm_ref_opt SDRAM Thermal and Refresh Opts"); - PRINT_NXS(32, spd->therm_sensor, - "therm_sensor SDRAM Thermal Sensor"); - PRINT_NXS(33, spd->device_type, - "device_type SDRAM Device Type"); - PRINT_NXS(34, spd->fine_tCK_min, - "fine_tCK_min Fine offset for tCKmin"); - PRINT_NXS(35, spd->fine_tAA_min, - "fine_tAA_min Fine offset for tAAmin"); - PRINT_NXS(36, spd->fine_tRCD_min, - "fine_tRCD_min Fine offset for tRCDmin"); - PRINT_NXS(37, spd->fine_tRP_min, - "fine_tRP_min Fine offset for tRPmin"); - PRINT_NXS(38, spd->fine_tRC_min, - "fine_tRC_min Fine offset for tRCmin"); - - printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ - - for (i = 39; i <= 59; i++) - printf("%02x ", spd->res_39_59[i - 39]); - - puts("\n"); - - switch (spd->module_type) { - case 0x02: /* UDIMM */ - case 0x03: /* SO-DIMM */ - case 0x04: /* Micro-DIMM */ - case 0x06: /* Mini-UDIMM */ - PRINT_NXS(60, spd->mod_section.unbuffered.mod_height, - "mod_height (Unbuffered) Module Nominal Height"); - PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness, - "mod_thickness (Unbuffered) Module Maximum Thickness"); - PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card, - "ref_raw_card (Unbuffered) Reference Raw Card Used"); - PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping, - "addr_mapping (Unbuffered) Address mapping from " - "Edge Connector to DRAM"); - break; - case 0x01: /* RDIMM */ - case 0x05: /* Mini-RDIMM */ - PRINT_NXS(60, spd->mod_section.registered.mod_height, - "mod_height (Registered) Module Nominal Height"); - PRINT_NXS(61, spd->mod_section.registered.mod_thickness, - "mod_thickness (Registered) Module Maximum Thickness"); - PRINT_NXS(62, spd->mod_section.registered.ref_raw_card, - "ref_raw_card (Registered) Reference Raw Card Used"); - PRINT_NXS(63, spd->mod_section.registered.modu_attr, - "modu_attr (Registered) DIMM Module Attributes"); - PRINT_NXS(64, spd->mod_section.registered.thermal, - "thermal (Registered) Thermal Heat " - "Spreader Solution"); - PRINT_NXS(65, spd->mod_section.registered.reg_id_lo, - "reg_id_lo (Registered) Register Manufacturer ID " - "Code, LSB"); - PRINT_NXS(66, spd->mod_section.registered.reg_id_hi, - "reg_id_hi (Registered) Register Manufacturer ID " - "Code, MSB"); - PRINT_NXS(67, spd->mod_section.registered.reg_rev, - "reg_rev (Registered) Register " - "Revision Number"); - PRINT_NXS(68, spd->mod_section.registered.reg_type, - "reg_type (Registered) Register Type"); - for (i = 69; i <= 76; i++) { - printf("%-3d : %02x rcw[%d]\n", i, - spd->mod_section.registered.rcw[i-69], i-69); - } - break; - default: - /* Module-specific Section, Unsupported Module Type */ - printf("%-3d-%3d: ", 60, 116); - - for (i = 60; i <= 116; i++) - printf("%02x", spd->mod_section.uc[i - 60]); - - break; - } - - /* Unique Module ID: Bytes 117-125 */ - PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); - PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); - PRINT_NXS(119, spd->mloc, "Mfg Location"); - PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date"); - - printf("%-3d-%3d: ", 122, 125); - - for (i = 122; i <= 125; i++) - printf("%02x ", spd->sernum[i - 122]); - printf(" Module Serial Number\n"); - - /* CRC: Bytes 126-127 */ - PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); - - /* Other Manufacturer Fields and User Space: Bytes 128-255 */ - printf("%-3d-%3d: ", 128, 145); - for (i = 128; i <= 145; i++) - printf("%02x ", spd->mpart[i - 128]); - printf(" Mfg's Module Part Number\n"); - - PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1], - "Module Revision code"); - - PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); - PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); - - printf("%-3d-%3d: ", 150, 175); - for (i = 150; i <= 175; i++) - printf("%02x ", spd->msd[i - 150]); - printf(" Mfg's Specific Data\n"); - - printf("%-3d-%3d: ", 176, 255); - for (i = 176; i <= 255; i++) - printf("%02x", spd->cust[i - 176]); - printf(" Mfg's Specific Data\n"); - -} -#endif - -static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) -{ -#if defined(CONFIG_FSL_DDR1) - ddr1_spd_dump(spd); -#elif defined(CONFIG_FSL_DDR2) - ddr2_spd_dump(spd); -#elif defined(CONFIG_FSL_DDR3) - ddr3_spd_dump(spd); -#endif -} - -static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo, - unsigned int ctrl_mask, - unsigned int dimm_mask, - unsigned int do_mask) -{ - unsigned int i, j, retval; - - /* STEP 1: DIMM SPD data */ - if (do_mask & STEP_GET_SPD) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - if (!(dimm_mask & (1 << j))) - continue; - - printf("SPD info: Controller=%u " - "DIMM=%u\n", i, j); - generic_spd_dump( - &(pinfo->spd_installed_dimms[i][j])); - printf("\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 2: DIMM Parameters */ - if (do_mask & STEP_COMPUTE_DIMM_PARMS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - if (!(dimm_mask & (1 << j))) - continue; - printf("DIMM parameters: Controller=%u " - "DIMM=%u\n", i, j); - print_dimm_parameters( - &(pinfo->dimm_params[i][j])); - printf("\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 3: Common Parameters */ - if (do_mask & STEP_COMPUTE_COMMON_PARMS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("\"lowest common\" DIMM parameters: " - "Controller=%u\n", i); - print_lowest_common_dimm_parameters( - &pinfo->common_timing_params[i]); - printf("\n"); - } - printf("\n"); - } - - /* STEP 4: User Configuration Options */ - if (do_mask & STEP_GATHER_OPTS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("User Config Options: Controller=%u\n", i); - print_memctl_options(&pinfo->memctl_opts[i]); - printf("\n"); - } - printf("\n"); - } - - /* STEP 5: Address assignment */ - if (do_mask & STEP_ASSIGN_ADDRESSES) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - printf("Address Assignment: Controller=%u " - "DIMM=%u\n", i, j); - printf("Don't have this functionality yet\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 6: computed controller register values */ - if (do_mask & STEP_COMPUTE_REGS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("Computed Register Values: Controller=%u\n", i); - print_fsl_memctl_config_regs( - &pinfo->fsl_ddr_config_reg[i]); - retval = check_fsl_memctl_config_regs( - &pinfo->fsl_ddr_config_reg[i]); - if (retval) { - printf("check_fsl_memctl_config_regs " - "result = %u\n", retval); - } - printf("\n"); - } - printf("\n"); - } -} - -struct data_strings { - const char *data_name; - unsigned int step_mask; - unsigned int dimm_number_required; -}; - -#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm} - -static unsigned int fsl_ddr_parse_interactive_cmd( - char **argv, - int argc, - unsigned int *pstep_mask, - unsigned int *pctlr_mask, - unsigned int *pdimm_mask, - unsigned int *pdimm_number_required - ) { - - static const struct data_strings options[] = { - DATA_OPTIONS(spd, STEP_GET_SPD, 1), - DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1), - DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0), - DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0), - DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0), - DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - unsigned int i, j; - unsigned int error = 0; - - for (i = 1; i < argc; i++) { - unsigned int matched = 0; - - for (j = 0; j < n_opts; j++) { - if (strcmp(options[j].data_name, argv[i]) != 0) - continue; - *pstep_mask |= options[j].step_mask; - *pdimm_number_required = - options[j].dimm_number_required; - matched = 1; - break; - } - - if (matched) - continue; - - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) - *pctlr_mask |= 1 << (c - '0'); - continue; - } - - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) - *pdimm_mask |= 1 << (c - '0'); - continue; - } - - printf("unknown arg %s\n", argv[i]); - *pstep_mask = 0; - error = 1; - break; - } - - return error; -} - -int fsl_ddr_interactive_env_var_exists(void) -{ - char buffer[CONFIG_SYS_CBSIZE]; - - if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0) - return 1; - - return 0; -} - -unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set) -{ - unsigned long long ddrsize; - const char *prompt = "FSL DDR>"; - char buffer[CONFIG_SYS_CBSIZE]; - char buffer2[CONFIG_SYS_CBSIZE]; - char *p = NULL; - char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ - int argc; - unsigned int next_step = STEP_GET_SPD; - const char *usage = { - "commands:\n" - "print print SPD and intermediate computed data\n" - "reset reboot machine\n" - "recompute reload SPD and options to default and recompute regs\n" - "edit modify spd, parameter, or option\n" - "compute recompute registers from current next_step to end\n" - "copy copy parameters\n" - "next_step shows current next_step\n" - "help this message\n" - "go program the memory controller and continue with u-boot\n" - }; - - if (var_is_set) { - if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) { - p = buffer2; - } else { - var_is_set = 0; - } - } - - /* - * The strategy for next_step is that it points to the next - * step in the computation process that needs to be done. - */ - while (1) { - if (var_is_set) { - char *pend = strchr(p, ';'); - if (pend) { - /* found command separator, copy sub-command */ - *pend = '\0'; - strcpy(buffer, p); - p = pend + 1; - } else { - /* separator not found, copy whole string */ - strcpy(buffer, p); - p = NULL; - var_is_set = 0; - } - } else { - /* - * No need to worry for buffer overflow here in - * this function; readline() maxes out at CFG_CBSIZE - */ - readline_into_buffer(prompt, buffer, 0); - } - argc = parse_line(buffer, argv); - if (argc == 0) - continue; - - - if (strcmp(argv[0], "help") == 0) { - puts(usage); - continue; - } - - if (strcmp(argv[0], "next_step") == 0) { - printf("next_step = 0x%02X (%s)\n", - next_step, - step_to_string(next_step)); - continue; - } - - if (strcmp(argv[0], "copy") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int src_ctlr_mask = 0; - unsigned int src_dimm_mask = 0; - unsigned int dimm_number_required = 0; - unsigned int src_ctlr_num = 0; - unsigned int src_dimm_num = 0; - unsigned int dst_ctlr_num = -1; - unsigned int dst_dimm_num = -1; - unsigned int i, num_dest_parms; - - if (argc == 1) { - printf("copy \n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc, - &step_mask, - &src_ctlr_mask, - &src_dimm_mask, - &dimm_number_required - ); - - /* XXX: only dimm_number_required and step_mask will - be used by this function. Parse the controller and - DIMM number separately because it is easier. */ - - if (error) - continue; - - /* parse source destination controller / DIMM */ - - num_dest_parms = dimm_number_required ? 2 : 1; - - for (i = 0; i < argc; i++) { - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) { - src_ctlr_num = (c - '0'); - break; - } - } - } - - for (i = 0; i < argc; i++) { - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) { - src_dimm_num = (c - '0'); - break; - } - } - } - - /* parse destination controller / DIMM */ - - for (i = argc - 1; i >= argc - num_dest_parms; i--) { - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) { - dst_ctlr_num = (c - '0'); - break; - } - } - } - - for (i = argc - 1; i >= argc - num_dest_parms; i--) { - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) { - dst_dimm_num = (c - '0'); - break; - } - } - } - - /* TODO: validate inputs */ - - debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n", - src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask); - - - switch (step_mask) { - - case STEP_GET_SPD: - memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]), - &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]), - sizeof(pinfo->spd_installed_dimms[0][0])); - break; - - case STEP_COMPUTE_DIMM_PARMS: - memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]), - &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]), - sizeof(pinfo->dimm_params[0][0])); - break; - - case STEP_COMPUTE_COMMON_PARMS: - memcpy(&(pinfo->common_timing_params[dst_ctlr_num]), - &(pinfo->common_timing_params[src_ctlr_num]), - sizeof(pinfo->common_timing_params[0])); - break; - - case STEP_GATHER_OPTS: - memcpy(&(pinfo->memctl_opts[dst_ctlr_num]), - &(pinfo->memctl_opts[src_ctlr_num]), - sizeof(pinfo->memctl_opts[0])); - break; - - /* someday be able to have addresses to copy addresses... */ - - case STEP_COMPUTE_REGS: - memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]), - &(pinfo->fsl_ddr_config_reg[src_ctlr_num]), - sizeof(pinfo->memctl_opts[0])); - break; - - default: - printf("unexpected step_mask value\n"); - } - - continue; - - } - - if (strcmp(argv[0], "edit") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int ctlr_mask = 0; - unsigned int dimm_mask = 0; - char *p_element = NULL; - char *p_value = NULL; - unsigned int dimm_number_required = 0; - unsigned int ctrl_num; - unsigned int dimm_num; - - if (argc == 1) { - /* Only the element and value must be last */ - printf("edit " - " \n"); - printf("for spd, specify byte number for " - "element\n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc - 2, - &step_mask, - &ctlr_mask, - &dimm_mask, - &dimm_number_required - ); - - if (error) - continue; - - - /* Check arguments */ - - /* ERROR: If no steps were found */ - if (step_mask == 0) { - printf("Error: No valid steps were specified " - "in argument.\n"); - continue; - } - - /* ERROR: If multiple steps were found */ - if (step_mask & (step_mask - 1)) { - printf("Error: Multiple steps specified in " - "argument.\n"); - continue; - } - - /* ERROR: Controller not specified */ - if (ctlr_mask == 0) { - printf("Error: controller number not " - "specified or no element and " - "value specified\n"); - continue; - } - - if (ctlr_mask & (ctlr_mask - 1)) { - printf("Error: multiple controllers " - "specified, %X\n", ctlr_mask); - continue; - } - - /* ERROR: DIMM number not specified */ - if (dimm_number_required && dimm_mask == 0) { - printf("Error: DIMM number number not " - "specified or no element and " - "value specified\n"); - continue; - } - - if (dimm_mask & (dimm_mask - 1)) { - printf("Error: multipled DIMMs specified\n"); - continue; - } - - p_element = argv[argc - 2]; - p_value = argv[argc - 1]; - - ctrl_num = __ilog2(ctlr_mask); - dimm_num = __ilog2(dimm_mask); - - switch (step_mask) { - case STEP_GET_SPD: - { - unsigned int element_num; - unsigned int value; - - element_num = simple_strtoul(p_element, - NULL, 0); - value = simple_strtoul(p_value, - NULL, 0); - fsl_ddr_spd_edit(pinfo, - ctrl_num, - dimm_num, - element_num, - value); - next_step = STEP_COMPUTE_DIMM_PARMS; - } - break; - - case STEP_COMPUTE_DIMM_PARMS: - fsl_ddr_dimm_parameters_edit( - pinfo, ctrl_num, dimm_num, - p_element, p_value); - next_step = STEP_COMPUTE_COMMON_PARMS; - break; - - case STEP_COMPUTE_COMMON_PARMS: - lowest_common_dimm_parameters_edit(pinfo, - ctrl_num, p_element, p_value); - next_step = STEP_GATHER_OPTS; - break; - - case STEP_GATHER_OPTS: - fsl_ddr_options_edit(pinfo, ctrl_num, - p_element, p_value); - next_step = STEP_ASSIGN_ADDRESSES; - break; - - case STEP_ASSIGN_ADDRESSES: - printf("editing of address assignment " - "not yet implemented\n"); - break; - - case STEP_COMPUTE_REGS: - { - fsl_ddr_regs_edit(pinfo, - ctrl_num, - p_element, - p_value); - next_step = STEP_PROGRAM_REGS; - } - break; - - default: - printf("programming error\n"); - while (1) - ; - break; - } - continue; - } - - if (strcmp(argv[0], "reset") == 0) { - /* - * Reboot machine. - * Args don't seem to matter because this - * doesn't return - */ - do_reset(NULL, 0, 0, NULL); - printf("Reset didn't work\n"); - } - - if (strcmp(argv[0], "recompute") == 0) { - /* - * Recalculate everything, starting with - * loading SPD EEPROM from DIMMs - */ - next_step = STEP_GET_SPD; - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - continue; - } - - if (strcmp(argv[0], "compute") == 0) { - /* - * Compute rest of steps starting at - * the current next_step/ - */ - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - continue; - } - - if (strcmp(argv[0], "print") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int ctlr_mask = 0; - unsigned int dimm_mask = 0; - unsigned int dimm_number_required = 0; - - if (argc == 1) { - printf("print [c] [d] [spd] [dimmparms] " - "[commonparms] [opts] [addresses] [regs]\n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc, - &step_mask, - &ctlr_mask, - &dimm_mask, - &dimm_number_required - ); - - if (error) - continue; - - /* If no particular controller was found, print all */ - if (ctlr_mask == 0) - ctlr_mask = 0xFF; - - /* If no particular dimm was found, print all dimms. */ - if (dimm_mask == 0) - dimm_mask = 0xFF; - - /* If no steps were found, print all steps. */ - if (step_mask == 0) - step_mask = STEP_ALL; - - fsl_ddr_printinfo(pinfo, ctlr_mask, - dimm_mask, step_mask); - continue; - } - - if (strcmp(argv[0], "go") == 0) { - if (next_step) - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - break; - } - - printf("unknown command %s\n", argv[0]); - } - - debug("end of memory = %llu\n", (u64)ddrsize); - - return ddrsize; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c deleted file mode 100644 index e958e138dd..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include "ddr.h" - -#if defined(CONFIG_FSL_DDR3) -static unsigned int -compute_cas_latency_ddr3(const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - unsigned int number_of_dimms) -{ - unsigned int i; - unsigned int tAAmin_ps = 0; - unsigned int tCKmin_X_ps = 0; - unsigned int common_caslat; - unsigned int caslat_actual; - unsigned int retry = 16; - unsigned int tmp; - const unsigned int mclk_ps = get_memory_clk_period_ps(); - - /* compute the common CAS latency supported between slots */ - tmp = dimm_params[0].caslat_X; - for (i = 1; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) - tmp &= dimm_params[i].caslat_X; - } - common_caslat = tmp; - - /* compute the max tAAmin tCKmin between slots */ - for (i = 0; i < number_of_dimms; i++) { - tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps); - tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps); - } - /* validate if the memory clk is in the range of dimms */ - if (mclk_ps < tCKmin_X_ps) { - printf("DDR clock (MCLK cycle %u ps) is faster than " - "the slowest DIMM(s) (tCKmin %u ps) can support.\n", - mclk_ps, tCKmin_X_ps); - } - /* determine the acutal cas latency */ - caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps; - /* check if the dimms support the CAS latency */ - while (!(common_caslat & (1 << caslat_actual)) && retry > 0) { - caslat_actual++; - retry--; - } - /* once the caculation of caslat_actual is completed - * we must verify that this CAS latency value does not - * exceed tAAmax, which is 20 ns for all DDR3 speed grades - */ - if (caslat_actual * mclk_ps > 20000) { - printf("The choosen cas latency %d is too large\n", - caslat_actual); - } - outpdimm->lowest_common_SPD_caslat = caslat_actual; - - return 0; -} -#endif - -/* - * compute_lowest_common_dimm_parameters() - * - * Determine the worst-case DIMM timing parameters from the set of DIMMs - * whose parameters have been computed into the array pointed to - * by dimm_params. - */ -unsigned int -compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - const unsigned int number_of_dimms) -{ - unsigned int i, j; - - unsigned int tCKmin_X_ps = 0; - unsigned int tCKmax_ps = 0xFFFFFFFF; - unsigned int tCKmax_max_ps = 0; - unsigned int tRCD_ps = 0; - unsigned int tRP_ps = 0; - unsigned int tRAS_ps = 0; - unsigned int tWR_ps = 0; - unsigned int tWTR_ps = 0; - unsigned int tRFC_ps = 0; - unsigned int tRRD_ps = 0; - unsigned int tRC_ps = 0; - unsigned int refresh_rate_ps = 0; - unsigned int tIS_ps = 0; - unsigned int tIH_ps = 0; - unsigned int tDS_ps = 0; - unsigned int tDH_ps = 0; - unsigned int tRTP_ps = 0; - unsigned int tDQSQ_max_ps = 0; - unsigned int tQHS_ps = 0; - - unsigned int temp1, temp2; - unsigned int additive_latency = 0; -#if !defined(CONFIG_FSL_DDR3) - const unsigned int mclk_ps = get_memory_clk_period_ps(); - unsigned int lowest_good_caslat; - unsigned int not_ok; - - debug("using mclk_ps = %u\n", mclk_ps); -#endif - - temp1 = 0; - for (i = 0; i < number_of_dimms; i++) { - /* - * If there are no ranks on this DIMM, - * it probably doesn't exist, so skip it. - */ - if (dimm_params[i].n_ranks == 0) { - temp1++; - continue; - } - if (dimm_params[i].n_ranks == 4 && i != 0) { - printf("Found Quad-rank DIMM in wrong bank, ignored." - " Software may not run as expected.\n"); - temp1++; - continue; - } - - /* - * check if quad-rank DIMM is plugged if - * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined - * Only the board with proper design is capable - */ -#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (dimm_params[i].n_ranks == 4 && \ - CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) { - printf("Found Quad-rank DIMM, not able to support."); - temp1++; - continue; - } -#endif - /* - * Find minimum tCKmax_ps to find fastest slow speed, - * i.e., this is the slowest the whole system can go. - */ - tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps); - - /* Either find maximum value to determine slowest - * speed, delay, time, period, etc */ - tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps); - tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps); - tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps); - tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps); - tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps); - tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps); - tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps); - tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps); - tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps); - tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps); - tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps); - tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps); - tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps); - tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps); - tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps); - tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps); - refresh_rate_ps = max(refresh_rate_ps, - dimm_params[i].refresh_rate_ps); - - /* - * Find maximum tDQSQ_max_ps to find slowest. - * - * FIXME: is finding the slowest value the correct - * strategy for this parameter? - */ - tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps); - } - - outpdimm->ndimms_present = number_of_dimms - temp1; - - if (temp1 == number_of_dimms) { - debug("no dimms this memory controller\n"); - return 0; - } - - outpdimm->tCKmin_X_ps = tCKmin_X_ps; - outpdimm->tCKmax_ps = tCKmax_ps; - outpdimm->tCKmax_max_ps = tCKmax_max_ps; - outpdimm->tRCD_ps = tRCD_ps; - outpdimm->tRP_ps = tRP_ps; - outpdimm->tRAS_ps = tRAS_ps; - outpdimm->tWR_ps = tWR_ps; - outpdimm->tWTR_ps = tWTR_ps; - outpdimm->tRFC_ps = tRFC_ps; - outpdimm->tRRD_ps = tRRD_ps; - outpdimm->tRC_ps = tRC_ps; - outpdimm->refresh_rate_ps = refresh_rate_ps; - outpdimm->tIS_ps = tIS_ps; - outpdimm->tIH_ps = tIH_ps; - outpdimm->tDS_ps = tDS_ps; - outpdimm->tDH_ps = tDH_ps; - outpdimm->tRTP_ps = tRTP_ps; - outpdimm->tDQSQ_max_ps = tDQSQ_max_ps; - outpdimm->tQHS_ps = tQHS_ps; - - /* Determine common burst length for all DIMMs. */ - temp1 = 0xff; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - temp1 &= dimm_params[i].burst_lengths_bitmask; - } - } - outpdimm->all_DIMMs_burst_lengths_bitmask = temp1; - - /* Determine if all DIMMs registered buffered. */ - temp1 = temp2 = 0; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - if (dimm_params[i].registered_dimm) { - temp1 = 1; - printf("Detected RDIMM %s\n", - dimm_params[i].mpart); - } else { - temp2 = 1; - printf("Detected UDIMM %s\n", - dimm_params[i].mpart); - } - } - } - - outpdimm->all_DIMMs_registered = 0; - outpdimm->all_DIMMs_unbuffered = 0; - if (temp1 && !temp2) { - outpdimm->all_DIMMs_registered = 1; - } else if (!temp1 && temp2) { - outpdimm->all_DIMMs_unbuffered = 1; - } else { - printf("ERROR: Mix of registered buffered and unbuffered " - "DIMMs detected!\n"); - } - - temp1 = 0; - if (outpdimm->all_DIMMs_registered) - for (j = 0; j < 16; j++) { - outpdimm->rcw[j] = dimm_params[0].rcw[j]; - for (i = 1; i < number_of_dimms; i++) { - if (!dimm_params[i].n_ranks) - continue; - if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { - temp1 = 1; - break; - } - } - } - - if (temp1 != 0) - printf("ERROR: Mix different RDIMM detected!\n"); - -#if defined(CONFIG_FSL_DDR3) - if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms)) - return 1; -#else - /* - * Compute a CAS latency suitable for all DIMMs - * - * Strategy for SPD-defined latencies: compute only - * CAS latency defined by all DIMMs. - */ - - /* - * Step 1: find CAS latency common to all DIMMs using bitwise - * operation. - */ - temp1 = 0xFF; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - temp2 = 0; - temp2 |= 1 << dimm_params[i].caslat_X; - temp2 |= 1 << dimm_params[i].caslat_X_minus_1; - temp2 |= 1 << dimm_params[i].caslat_X_minus_2; - /* - * FIXME: If there was no entry for X-2 (X-1) in - * the SPD, then caslat_X_minus_2 - * (caslat_X_minus_1) contains either 255 or - * 0xFFFFFFFF because that's what the glorious - * __ilog2 function returns for an input of 0. - * On 32-bit PowerPC, left shift counts with bit - * 26 set (that the value of 255 or 0xFFFFFFFF - * will have), cause the destination register to - * be 0. That is why this works. - */ - temp1 &= temp2; - } - } - - /* - * Step 2: check each common CAS latency against tCK of each - * DIMM's SPD. - */ - lowest_good_caslat = 0; - temp2 = 0; - while (temp1) { - not_ok = 0; - temp2 = __ilog2(temp1); - debug("checking common caslat = %u\n", temp2); - - /* Check if this CAS latency will work on all DIMMs at tCK. */ - for (i = 0; i < number_of_dimms; i++) { - if (!dimm_params[i].n_ranks) { - continue; - } - if (dimm_params[i].caslat_X == temp2) { - if (mclk_ps >= dimm_params[i].tCKmin_X_ps) { - debug("CL = %u ok on DIMM %u at tCK=%u" - " ps with its tCKmin_X_ps of %u\n", - temp2, i, mclk_ps, - dimm_params[i].tCKmin_X_ps); - continue; - } else { - not_ok++; - } - } - - if (dimm_params[i].caslat_X_minus_1 == temp2) { - unsigned int tCKmin_X_minus_1_ps - = dimm_params[i].tCKmin_X_minus_1_ps; - if (mclk_ps >= tCKmin_X_minus_1_ps) { - debug("CL = %u ok on DIMM %u at " - "tCK=%u ps with its " - "tCKmin_X_minus_1_ps of %u\n", - temp2, i, mclk_ps, - tCKmin_X_minus_1_ps); - continue; - } else { - not_ok++; - } - } - - if (dimm_params[i].caslat_X_minus_2 == temp2) { - unsigned int tCKmin_X_minus_2_ps - = dimm_params[i].tCKmin_X_minus_2_ps; - if (mclk_ps >= tCKmin_X_minus_2_ps) { - debug("CL = %u ok on DIMM %u at " - "tCK=%u ps with its " - "tCKmin_X_minus_2_ps of %u\n", - temp2, i, mclk_ps, - tCKmin_X_minus_2_ps); - continue; - } else { - not_ok++; - } - } - } - - if (!not_ok) { - lowest_good_caslat = temp2; - } - - temp1 &= ~(1 << temp2); - } - - debug("lowest common SPD-defined CAS latency = %u\n", - lowest_good_caslat); - outpdimm->lowest_common_SPD_caslat = lowest_good_caslat; - - - /* - * Compute a common 'de-rated' CAS latency. - * - * The strategy here is to find the *highest* dereated cas latency - * with the assumption that all of the DIMMs will support a dereated - * CAS latency higher than or equal to their lowest dereated value. - */ - temp1 = 0; - for (i = 0; i < number_of_dimms; i++) { - temp1 = max(temp1, dimm_params[i].caslat_lowest_derated); - } - outpdimm->highest_common_derated_caslat = temp1; - debug("highest common dereated CAS latency = %u\n", temp1); -#endif /* #if defined(CONFIG_FSL_DDR3) */ - - /* Determine if all DIMMs ECC capable. */ - temp1 = 1; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks && - !(dimm_params[i].edc_config & EDC_ECC)) { - temp1 = 0; - break; - } - } - if (temp1) { - debug("all DIMMs ECC capable\n"); - } else { - debug("Warning: not all DIMMs ECC capable, cant enable ECC\n"); - } - outpdimm->all_DIMMs_ECC_capable = temp1; - -#ifndef CONFIG_FSL_DDR3 - /* FIXME: move to somewhere else to validate. */ - if (mclk_ps > tCKmax_max_ps) { - printf("Warning: some of the installed DIMMs " - "can not operate this slowly.\n"); - return 1; - } -#endif - /* - * Compute additive latency. - * - * For DDR1, additive latency should be 0. - * - * For DDR2, with ODT enabled, use "a value" less than ACTTORW, - * which comes from Trcd, and also note that: - * add_lat + caslat must be >= 4 - * - * For DDR3, we use the AL=0 - * - * When to use additive latency for DDR2: - * - * I. Because you are using CL=3 and need to do ODT on writes and - * want functionality. - * 1. Are you going to use ODT? (Does your board not have - * additional termination circuitry for DQ, DQS, DQS_, - * DM, RDQS, RDQS_ for x4/x8 configs?) - * 2. If so, is your lowest supported CL going to be 3? - * 3. If so, then you must set AL=1 because - * - * WL >= 3 for ODT on writes - * RL = AL + CL - * WL = RL - 1 - * -> - * WL = AL + CL - 1 - * AL + CL - 1 >= 3 - * AL + CL >= 4 - * QED - * - * RL >= 3 for ODT on reads - * RL = AL + CL - * - * Since CL aren't usually less than 2, AL=0 is a minimum, - * so the WL-derived AL should be the -- FIXME? - * - * II. Because you are using auto-precharge globally and want to - * use additive latency (posted CAS) to get more bandwidth. - * 1. Are you going to use auto-precharge mode globally? - * - * Use addtivie latency and compute AL to be 1 cycle less than - * tRCD, i.e. the READ or WRITE command is in the cycle - * immediately following the ACTIVATE command.. - * - * III. Because you feel like it or want to do some sort of - * degraded-performance experiment. - * 1. Do you just want to use additive latency because you feel - * like it? - * - * Validation: AL is less than tRCD, and within the other - * read-to-precharge constraints. - */ - - additive_latency = 0; - -#if defined(CONFIG_FSL_DDR2) - if (lowest_good_caslat < 4) { - additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat) - ? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0; - if (mclk_to_picos(additive_latency) > tRCD_ps) { - additive_latency = picos_to_mclk(tRCD_ps); - debug("setting additive_latency to %u because it was " - " greater than tRCD_ps\n", additive_latency); - } - } - -#elif defined(CONFIG_FSL_DDR3) - /* - * The system will not use the global auto-precharge mode. - * However, it uses the page mode, so we set AL=0 - */ - additive_latency = 0; -#endif - - /* - * Validate additive latency - * FIXME: move to somewhere else to validate - * - * AL <= tRCD(min) - */ - if (mclk_to_picos(additive_latency) > tRCD_ps) { - printf("Error: invalid additive latency exceeds tRCD(min).\n"); - return 1; - } - - /* - * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled - * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled - * ADD_LAT (the register) must be set to a value less - * than ACTTORW if WL = 1, then AL must be set to 1 - * RD_TO_PRE (the register) must be set to a minimum - * tRTP + AL if AL is nonzero - */ - - /* - * Additive latency will be applied only if the memctl option to - * use it. - */ - outpdimm->additive_latency = additive_latency; - - debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps); - debug("tRCD_ps = %u\n", outpdimm->tRCD_ps); - debug("tRP_ps = %u\n", outpdimm->tRP_ps); - debug("tRAS_ps = %u\n", outpdimm->tRAS_ps); - debug("tWR_ps = %u\n", outpdimm->tWR_ps); - debug("tWTR_ps = %u\n", outpdimm->tWTR_ps); - debug("tRFC_ps = %u\n", outpdimm->tRFC_ps); - debug("tRRD_ps = %u\n", outpdimm->tRRD_ps); - debug("tRC_ps = %u\n", outpdimm->tRC_ps); - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c deleted file mode 100644 index 7a8636de16..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ /dev/null @@ -1,667 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - */ - -#include -#include -#include -#include - -#include "ddr.h" - -void fsl_ddr_set_lawbar( - const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); -void fsl_ddr_set_intl3r(const unsigned int granule_size); - -/* processor specific function */ -extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); - -#if defined(SPD_EEPROM_ADDRESS) || \ - defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ - defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) -#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS, -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ - [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ - [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ - [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ - [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ - [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ -}; - -#endif - -static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) -{ - int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, - sizeof(generic_spd_eeprom_t)); - - if (ret) { - if (i2c_address == -#ifdef SPD_EEPROM_ADDRESS - SPD_EEPROM_ADDRESS -#elif defined(SPD_EEPROM_ADDRESS1) - SPD_EEPROM_ADDRESS1 -#endif - ) { - printf("DDR: failed to read SPD from address %u\n", - i2c_address); - } else { - debug("DDR: failed to read SPD from address %u\n", - i2c_address); - } - memset(spd, 0, sizeof(generic_spd_eeprom_t)); - } -} - -__attribute__((weak, alias("__get_spd"))) -void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); - -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - i2c_address = spd_i2c_addr[ctrl_num][i]; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} -#else -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ -} -#endif /* SPD_EEPROM_ADDRESSx */ - -/* - * ASSUMPTIONS: - * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller - * - Same memory data bus width on all controllers - * - * NOTES: - * - * The memory controller and associated documentation use confusing - * terminology when referring to the orgranization of DRAM. - * - * Here is a terminology translation table: - * - * memory controller/documention |industry |this code |signals - * -------------------------------|-----------|-----------|----------------- - * physical bank/bank |rank |rank |chip select (CS) - * logical bank/sub-bank |bank |bank |bank address (BA) - * page/row |row |page |row address - * ??? |column |column |column address - * - * The naming confusion is further exacerbated by the descriptions of the - * memory controller interleaving feature, where accesses are interleaved - * _BETWEEN_ two seperate memory controllers. This is configured only in - * CS0_CONFIG[INTLV_CTL] of each memory controller. - * - * memory controller documentation | number of chip selects - * | per memory controller supported - * --------------------------------|----------------------------------------- - * cache line interleaving | 1 (CS0 only) - * page interleaving | 1 (CS0 only) - * bank interleaving | 1 (CS0 only) - * superbank interleraving | depends on bank (chip select) - * | interleraving [rank interleaving] - * | mode used on every memory controller - * - * Even further confusing is the existence of the interleaving feature - * _WITHIN_ each memory controller. The feature is referred to in - * documentation as chip select interleaving or bank interleaving, - * although it is configured in the DDR_SDRAM_CFG field. - * - * Name of field | documentation name | this code - * -----------------------------|-----------------------|------------------ - * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving - * | interleaving - */ - -const char *step_string_tbl[] = { - "STEP_GET_SPD", - "STEP_COMPUTE_DIMM_PARMS", - "STEP_COMPUTE_COMMON_PARMS", - "STEP_GATHER_OPTS", - "STEP_ASSIGN_ADDRESSES", - "STEP_COMPUTE_REGS", - "STEP_PROGRAM_REGS", - "STEP_ALL" -}; - -const char * step_to_string(unsigned int step) { - - unsigned int s = __ilog2(step); - - if ((1 << s) != step) - return step_string_tbl[7]; - - return step_string_tbl[s]; -} - -static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, - unsigned int dbw_cap_adj[]) -{ - int i, j; - unsigned long long total_mem, current_mem_base, total_ctlr_mem; - unsigned long long rank_density, ctlr_density = 0; - - /* - * If a reduced data width is requested, but the SPD - * specifies a physically wider device, adjust the - * computed dimm capacities accordingly before - * assigning addresses. - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - unsigned int found = 0; - - switch (pinfo->memctl_opts[i].data_bus_width) { - case 2: - /* 16-bit */ - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int dw; - if (!pinfo->dimm_params[i][j].n_ranks) - continue; - dw = pinfo->dimm_params[i][j].primary_sdram_width; - if ((dw == 72 || dw == 64)) { - dbw_cap_adj[i] = 2; - break; - } else if ((dw == 40 || dw == 32)) { - dbw_cap_adj[i] = 1; - break; - } - } - break; - - case 1: - /* 32-bit */ - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int dw; - dw = pinfo->dimm_params[i][j].data_width; - if (pinfo->dimm_params[i][j].n_ranks - && (dw == 72 || dw == 64)) { - /* - * FIXME: can't really do it - * like this because this just - * further reduces the memory - */ - found = 1; - break; - } - } - if (found) { - dbw_cap_adj[i] = 1; - } - break; - - case 0: - /* 64-bit */ - break; - - default: - printf("unexpected data bus width " - "specified controller %u\n", i); - return 1; - } - debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); - } - - current_mem_base = 0ull; - total_mem = 0; - if (pinfo->memctl_opts[0].memctl_interleaving) { - rank_density = pinfo->dimm_params[0][0].rank_density >> - dbw_cap_adj[0]; - switch (pinfo->memctl_opts[0].ba_intlv_ctl & - FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - ctlr_density = 4 * rank_density; - break; - case FSL_DDR_CS0_CS1: - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - ctlr_density = 2 * rank_density; - break; - case FSL_DDR_CS2_CS3: - default: - ctlr_density = rank_density; - break; - } - debug("rank density is 0x%llx, ctlr density is 0x%llx\n", - rank_density, ctlr_density); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (pinfo->memctl_opts[i].memctl_interleaving) { - switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - total_ctlr_mem = 2 * ctlr_density; - break; - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - total_ctlr_mem = 3 * ctlr_density; - break; - case FSL_DDR_4WAY_1KB_INTERLEAVING: - case FSL_DDR_4WAY_4KB_INTERLEAVING: - case FSL_DDR_4WAY_8KB_INTERLEAVING: - total_ctlr_mem = 4 * ctlr_density; - break; - default: - panic("Unknown interleaving mode"); - } - pinfo->common_timing_params[i].base_address = - current_mem_base; - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem = current_mem_base + total_ctlr_mem; - debug("ctrl %d base 0x%llx\n", i, current_mem_base); - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - } else { - /* when 3rd controller not interleaved */ - current_mem_base = total_mem; - total_ctlr_mem = 0; - pinfo->common_timing_params[i].base_address = - current_mem_base; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned long long cap = - pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; - pinfo->dimm_params[i][j].base_address = - current_mem_base; - debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); - current_mem_base += cap; - total_ctlr_mem += cap; - } - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem += total_ctlr_mem; - } - } - } else { - /* - * Simple linear assignment if memory - * controllers are not interleaved. - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - total_ctlr_mem = 0; - pinfo->common_timing_params[i].base_address = - current_mem_base; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - /* Compute DIMM base addresses. */ - unsigned long long cap = - pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; - pinfo->dimm_params[i][j].base_address = - current_mem_base; - debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); - current_mem_base += cap; - total_ctlr_mem += cap; - } - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem += total_ctlr_mem; - } - } - debug("Total mem by %s is 0x%llx\n", __func__, total_mem); - - return total_mem; -} - -/* Use weak function to allow board file to override the address assignment */ -__attribute__((weak, alias("__step_assign_addresses"))) -unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, - unsigned int dbw_cap_adj[]); - -unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, - unsigned int size_only) -{ - unsigned int i, j; - unsigned long long total_mem = 0; - - fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; - common_timing_params_t *timing_params = pinfo->common_timing_params; - - /* data bus width capacity adjust shift amount */ - unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - dbw_capacity_adjust[i] = 0; - } - - debug("starting at step %u (%s)\n", - start_step, step_to_string(start_step)); - - switch (start_step) { - case STEP_GET_SPD: -#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) - /* STEP 1: Gather all DIMM SPD data */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); - } - - case STEP_COMPUTE_DIMM_PARMS: - /* STEP 2: Compute DIMM parameters from SPD data */ - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int retval; - generic_spd_eeprom_t *spd = - &(pinfo->spd_installed_dimms[i][j]); - dimm_params_t *pdimm = - &(pinfo->dimm_params[i][j]); - - retval = compute_dimm_parameters(spd, pdimm, i); -#ifdef CONFIG_SYS_DDR_RAW_TIMING - if (!i && !j && retval) { - printf("SPD error on controller %d! " - "Trying fallback to raw timing " - "calculation\n", i); - fsl_ddr_get_dimm_params(pdimm, i, j); - } -#else - if (retval == 2) { - printf("Error: compute_dimm_parameters" - " non-zero returned FATAL value " - "for memctl=%u dimm=%u\n", i, j); - return 0; - } -#endif - if (retval) { - debug("Warning: compute_dimm_parameters" - " non-zero return value for memctl=%u " - "dimm=%u\n", i, j); - } - } - } - -#elif defined(CONFIG_SYS_DDR_RAW_TIMING) - case STEP_COMPUTE_DIMM_PARMS: - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - dimm_params_t *pdimm = - &(pinfo->dimm_params[i][j]); - fsl_ddr_get_dimm_params(pdimm, i, j); - } - } - debug("Filling dimm parameters from board specific file\n"); -#endif - case STEP_COMPUTE_COMMON_PARMS: - /* - * STEP 3: Compute a common set of timing parameters - * suitable for all of the DIMMs on each memory controller - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Computing lowest common DIMM" - " parameters for memctl=%u\n", i); - compute_lowest_common_dimm_parameters( - pinfo->dimm_params[i], - &timing_params[i], - CONFIG_DIMM_SLOTS_PER_CTLR); - } - - case STEP_GATHER_OPTS: - /* STEP 4: Gather configuration requirements from user */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Reloading memory controller " - "configuration options for memctl=%u\n", i); - /* - * This "reloads" the memory controller options - * to defaults. If the user "edits" an option, - * next_step points to the step after this, - * which is currently STEP_ASSIGN_ADDRESSES. - */ - populate_memctl_options( - timing_params[i].all_DIMMs_registered, - &pinfo->memctl_opts[i], - pinfo->dimm_params[i], i); - } - case STEP_ASSIGN_ADDRESSES: - /* STEP 5: Assign addresses to chip selects */ - check_interleaving_options(pinfo); - total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); - - case STEP_COMPUTE_REGS: - /* STEP 6: compute controller register values */ - debug("FSL Memory ctrl register computation\n"); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (timing_params[i].ndimms_present == 0) { - memset(&ddr_reg[i], 0, - sizeof(fsl_ddr_cfg_regs_t)); - continue; - } - - compute_fsl_memctl_config_regs( - &pinfo->memctl_opts[i], - &ddr_reg[i], &timing_params[i], - pinfo->dimm_params[i], - dbw_capacity_adjust[i], - size_only); - } - - default: - break; - } - - { - /* - * Compute the amount of memory available just by - * looking for the highest valid CSn_BNDS value. - * This allows us to also experiment with using - * only CS0 when using dual-rank DIMMs. - */ - unsigned int max_end = 0; - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { - fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; - if (reg->cs[j].config & 0x80000000) { - unsigned int end; - end = reg->cs[j].bnds & 0xFFF; - if (end > max_end) { - max_end = end; - } - } - } - } - - total_mem = 1 + (((unsigned long long)max_end << 24ULL) - | 0xFFFFFFULL); - } - - return total_mem; -} - -/* - * fsl_ddr_sdram() -- this is the main function to be called by - * initdram() in the board file. - * - * It returns amount of memory configured in bytes. - */ -phys_size_t fsl_ddr_sdram(void) -{ - unsigned int i; - unsigned int law_memctl = LAW_TRGT_IF_DDR_1; - unsigned long long total_memory; - fsl_ddr_info_t info; - - /* Reset info structure. */ - memset(&info, 0, sizeof(fsl_ddr_info_t)); - - /* Compute it once normally. */ -#ifdef CONFIG_FSL_DDR_INTERACTIVE - if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ - total_memory = fsl_ddr_interactive(&info, 0); - } else if (fsl_ddr_interactive_env_var_exists()) { - total_memory = fsl_ddr_interactive(&info, 1); - } else -#endif - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); - - /* setup 3-way interleaving before enabling DDRC */ - if (info.memctl_opts[0].memctl_interleaving) { - switch (info.memctl_opts[0].memctl_interleaving_mode) { - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - fsl_ddr_set_intl3r( - info.memctl_opts[0].memctl_interleaving_mode); - break; - default: - break; - } - } - - /* Program configuration registers. */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Programming controller %u\n", i); - if (info.common_timing_params[i].ndimms_present == 0) { - debug("No dimms present on controller %u; " - "skipping programming\n", i); - continue; - } - - fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i); - } - - /* program LAWs */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (info.memctl_opts[i].memctl_interleaving) { - switch (info.memctl_opts[i].memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - if (i == 0) { - law_memctl = LAW_TRGT_IF_DDR_INTRLV; - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } else if (i == 2) { - law_memctl = LAW_TRGT_IF_DDR_INTLV_34; - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - break; - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - law_memctl = LAW_TRGT_IF_DDR_INTLV_123; - if (i == 0) { - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - break; - case FSL_DDR_4WAY_1KB_INTERLEAVING: - case FSL_DDR_4WAY_4KB_INTERLEAVING: - case FSL_DDR_4WAY_8KB_INTERLEAVING: - law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; - if (i == 0) - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - /* place holder for future 4-way interleaving */ - break; - default: - break; - } - } else { - switch (i) { - case 0: - law_memctl = LAW_TRGT_IF_DDR_1; - break; - case 1: - law_memctl = LAW_TRGT_IF_DDR_2; - break; - case 2: - law_memctl = LAW_TRGT_IF_DDR_3; - break; - case 3: - law_memctl = LAW_TRGT_IF_DDR_4; - break; - default: - break; - } - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - } - - debug("total_memory by %s = %llu\n", __func__, total_memory); - -#if !defined(CONFIG_PHYS_64BIT) - /* Check for 4G or more. Bad. */ - if (total_memory >= (1ull << 32)) { - printf("Detected %lld MB of memory\n", total_memory >> 20); - printf(" This U-Boot only supports < 4G of DDR\n"); - printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); - printf(" "); /* re-align to match init_func_ram print */ - total_memory = CONFIG_MAX_MEM_MAPPED; - } -#endif - - return total_memory; -} - -/* - * fsl_ddr_sdram_size() - This function only returns the size of the total - * memory without setting ddr control registers. - */ -phys_size_t -fsl_ddr_sdram_size(void) -{ - fsl_ddr_info_t info; - unsigned long long total_memory = 0; - - memset(&info, 0 , sizeof(fsl_ddr_info_t)); - - /* Compute it once normally. */ - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); - - return total_memory; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c deleted file mode 100644 index acfe1f095f..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include - -#include "ddr.h" - -/* To avoid 64-bit full-divides, we factor this here */ -#define ULL_2E12 2000000000000ULL -#define UL_5POW12 244140625UL -#define UL_2POW13 (1UL << 13) - -#define ULL_8FS 0xFFFFFFFFULL - -/* - * Round up mclk_ps to nearest 1 ps in memory controller code - * if the error is 0.5ps or more. - * - * If an imprecise data rate is too high due to rounding error - * propagation, compute a suitably rounded mclk_ps to compute - * a working memory controller configuration. - */ -unsigned int get_memory_clk_period_ps(void) -{ - unsigned int data_rate = get_ddr_freq(0); - unsigned int result; - - /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ - unsigned long long rem, mclk_ps = ULL_2E12; - - /* Now perform the big divide, the result fits in 32-bits */ - rem = do_div(mclk_ps, data_rate); - result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; - - return result; -} - -/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ -unsigned int picos_to_mclk(unsigned int picos) -{ - unsigned long long clks, clks_rem; - unsigned long data_rate = get_ddr_freq(0); - - /* Short circuit for zero picos */ - if (!picos) - return 0; - - /* First multiply the time by the data rate (32x32 => 64) */ - clks = picos * (unsigned long long)data_rate; - /* - * Now divide by 5^12 and track the 32-bit remainder, then divide - * by 2*(2^12) using shifts (and updating the remainder). - */ - clks_rem = do_div(clks, UL_5POW12); - clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; - clks >>= 13; - - /* If we had a remainder greater than the 1ps error, then round up */ - if (clks_rem > data_rate) - clks++; - - /* Clamp to the maximum representable value */ - if (clks > ULL_8FS) - clks = ULL_8FS; - return (unsigned int) clks; -} - -unsigned int mclk_to_picos(unsigned int mclk) -{ - return get_memory_clk_period_ps() * mclk; -} - -void -__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, - unsigned int law_memctl, - unsigned int ctrl_num) -{ - unsigned long long base = memctl_common_params->base_address; - unsigned long long size = memctl_common_params->total_mem; - - /* - * If no DIMMs on this controller, do not proceed any further. - */ - if (!memctl_common_params->ndimms_present) { - return; - } - -#if !defined(CONFIG_PHYS_64BIT) - if (base >= CONFIG_MAX_MEM_MAPPED) - return; - if ((base + size) >= CONFIG_MAX_MEM_MAPPED) - size = CONFIG_MAX_MEM_MAPPED - base; -#endif - if (set_ddr_laws(base, size, law_memctl) < 0) { - printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, - law_memctl); - return ; - } - debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", - base, size, law_memctl); -} - -__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void -fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); - -void fsl_ddr_set_intl3r(const unsigned int granule_size) -{ -#ifdef CONFIG_E6500 - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); - *mcintl3r = 0x80000000 | (granule_size & 0x1f); - debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); -#endif -} - -u32 fsl_ddr_get_intl3r(void) -{ - u32 val = 0; -#ifdef CONFIG_E6500 - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); - val = *mcintl3r; -#endif - return val; -} - -void board_add_ram_info(int use_default) -{ - ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); - -#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); -#endif -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) - uint32_t cs0_config = in_be32(&ddr->cs0_config); -#endif - uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); - int cas_lat; - -#if CONFIG_NUM_DDR_CONTROLLERS >= 2 - if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { - ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); - } -#endif -#if CONFIG_NUM_DDR_CONTROLLERS >= 3 - if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { - ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); - } -#endif - puts(" (DDR"); - switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> - SDRAM_CFG_SDRAM_TYPE_SHIFT) { - case SDRAM_TYPE_DDR1: - puts("1"); - break; - case SDRAM_TYPE_DDR2: - puts("2"); - break; - case SDRAM_TYPE_DDR3: - puts("3"); - break; - default: - puts("?"); - break; - } - - if (sdram_cfg & SDRAM_CFG_32_BE) - puts(", 32-bit"); - else if (sdram_cfg & SDRAM_CFG_16_BE) - puts(", 16-bit"); - else - puts(", 64-bit"); - - /* Calculate CAS latency based on timing cfg values */ - cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; - if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) - cas_lat += (8 << 1); - printf(", CL=%d", cas_lat >> 1); - if (cas_lat & 0x1) - puts(".5"); - - if (sdram_cfg & SDRAM_CFG_ECC_EN) - puts(", ECC on)"); - else - puts(", ECC off)"); - -#if (CONFIG_NUM_DDR_CONTROLLERS == 3) -#ifdef CONFIG_E6500 - if (*mcintl3r & 0x80000000) { - puts("\n"); - puts(" DDR Controller Interleaving Mode: "); - switch (*mcintl3r & 0x1f) { - case FSL_DDR_3WAY_1KB_INTERLEAVING: - puts("3-way 1KB"); - break; - case FSL_DDR_3WAY_4KB_INTERLEAVING: - puts("3-way 4KB"); - break; - case FSL_DDR_3WAY_8KB_INTERLEAVING: - puts("3-way 8KB"); - break; - default: - puts("3-way UNKNOWN"); - break; - } - } -#endif -#endif -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) - if (cs0_config & 0x20000000) { - puts("\n"); - puts(" DDR Controller Interleaving Mode: "); - - switch ((cs0_config >> 24) & 0xf) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - puts("cache line"); - break; - case FSL_DDR_PAGE_INTERLEAVING: - puts("page"); - break; - case FSL_DDR_BANK_INTERLEAVING: - puts("bank"); - break; - case FSL_DDR_SUPERBANK_INTERLEAVING: - puts("super-bank"); - break; - default: - puts("invalid"); - break; - } - } -#endif - - if ((sdram_cfg >> 8) & 0x7f) { - puts("\n"); - puts(" DDR Chip-Select Interleaving Mode: "); - switch(sdram_cfg >> 8 & 0x7f) { - case FSL_DDR_CS0_CS1_CS2_CS3: - puts("CS0+CS1+CS2+CS3"); - break; - case FSL_DDR_CS0_CS1: - puts("CS0+CS1"); - break; - case FSL_DDR_CS2_CS3: - puts("CS2+CS3"); - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - puts("CS0+CS1 and CS2+CS3"); - break; - default: - puts("invalid"); - break; - } - } -} diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 89966e0d2f..9cc1676b60 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2009-2014 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -15,7 +15,9 @@ #include #include -#define FSL_MAX_NUM_USB_CTRLS 2 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -71,304 +73,6 @@ void ft_fixup_num_cores(void *blob) { } #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, - const char *phy_type, int start_offset) -{ - const char *compat_dr = "fsl-usb2-dr"; - const char *compat_mph = "fsl-usb2-mph"; - const char *prop_mode = "dr_mode"; - const char *prop_type = "phy_type"; - const char *node_type = NULL; - int node_offset; - int err; - - node_offset = fdt_node_offset_by_compatible(blob, - start_offset, compat_mph); - if (node_offset < 0) { - node_offset = fdt_node_offset_by_compatible(blob, - start_offset, compat_dr); - if (node_offset < 0) { - printf("WARNING: could not find compatible" - " node %s or %s: %s.\n", compat_mph, - compat_dr, fdt_strerror(node_offset)); - return -1; - } else - node_type = compat_dr; - } else - node_type = compat_mph; - - if (mode) { - err = fdt_setprop(blob, node_offset, prop_mode, mode, - strlen(mode) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_mode, node_type, fdt_strerror(err)); - } - - if (phy_type) { - err = fdt_setprop(blob, node_offset, prop_type, phy_type, - strlen(phy_type) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_type, node_type, fdt_strerror(err)); - } - - return node_offset; -} - -void fdt_fixup_dr_usb(void *blob, bd_t *bd) -{ - const char *modes[] = { "host", "peripheral", "otg" }; - const char *phys[] = { "ulpi", "utmi" }; - const char *mode = NULL; - const char *phy_type = NULL; - const char *dr_mode_type = NULL; - const char *dr_phy_type = NULL; - char usb1_defined = 0; - int usb_mode_off = -1; - int usb_phy_off = -1; - char str[5]; - int i, j; - - for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) { - int mode_idx = -1, phy_idx = -1; - snprintf(str, 5, "%s%d", "usb", i); - if (hwconfig(str)) { - for (j = 0; j < ARRAY_SIZE(modes); j++) { - if (hwconfig_subarg_cmp(str, "dr_mode", - modes[j])) { - mode_idx = j; - break; - } - } - - for (j = 0; j < ARRAY_SIZE(phys); j++) { - if (hwconfig_subarg_cmp(str, "phy_type", - phys[j])) { - phy_idx = j; - break; - } - } - - if (mode_idx < 0 || phy_idx < 0) { - puts("ERROR: wrong usb mode/phy defined!!\n"); - return; - } - - dr_mode_type = modes[mode_idx]; - dr_phy_type = phys[phy_idx]; - - /* use usb_dr_mode and usb_phy_type if - usb1_defined = 0; these variables are to - be deprecated */ - if (!strcmp(str, "usb1")) - usb1_defined = 1; - - if (mode_idx < 0 && phy_idx < 0) { - printf("WARNING: invalid phy or mode\n"); - return; - } - } - - usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, - dr_mode_type, NULL, usb_mode_off); - - if (usb_mode_off < 0) - return; - - usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, - NULL, dr_phy_type, usb_phy_off); - - if (usb_phy_off < 0) - return; - } - - if (!usb1_defined) { - int usb_off = -1; - mode = getenv("usb_dr_mode"); - phy_type = getenv("usb_phy_type"); - if (mode || phy_type) { - printf("WARNING: usb_dr_mode and usb_phy_type " - "are to be deprecated soon. Use " - "hwconfig to set these values instead!!\n"); - fdt_fixup_usb_mode_phy_type(blob, mode, - phy_type, usb_off); - } - } -} -#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */ - -/* - * update crypto node properties to a specified revision of the SEC - * called with sec_rev == 0 if not on an E processor - */ -#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */ -void fdt_fixup_crypto_node(void *blob, int sec_rev) -{ - static const struct sec_rev_prop { - u32 sec_rev; - u32 num_channels; - u32 channel_fifo_len; - u32 exec_units_mask; - u32 descriptor_types_mask; - } sec_rev_prop_list [] = { - { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ - { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ - { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ - { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ - { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ - { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ - { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ - }; - static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * - sizeof("fsl,secX.Y")]; - int crypto_node, sec_idx, err; - char *p; - u32 val; - - /* locate crypto node based on lowest common compatible */ - crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); - if (crypto_node == -FDT_ERR_NOTFOUND) - return; - - /* delete it if not on an E-processor */ - if (crypto_node > 0 && !sec_rev) { - fdt_del_node(blob, crypto_node); - return; - } - - /* else we got called for possible uprev */ - for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) - if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) - break; - - if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { - puts("warning: unknown SEC revision number\n"); - return; - } - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); - err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); - err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); - err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); - err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = 0; - while (sec_idx >= 0) { - p = compat_strlist + val; - val += sprintf(p, "fsl,sec%d.%d", - (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, - sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; - sec_idx--; - } - err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); -} -#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ -static u8 caam_get_era(void) -{ - static const struct { - u16 ip_id; - u8 maj_rev; - u8 era; - } caam_eras[] = { - {0x0A10, 1, 1}, - {0x0A10, 2, 2}, - {0x0A12, 1, 3}, - {0x0A14, 1, 3}, - {0x0A14, 2, 4}, - {0x0A16, 1, 4}, - {0x0A10, 3, 4}, - {0x0A11, 1, 4}, - {0x0A18, 1, 4}, - {0x0A11, 2, 5}, - {0x0A12, 2, 5}, - {0x0A13, 1, 5}, - {0x0A1C, 1, 5} - }; - - ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; - u32 secvid_ms = in_be32(&sec->secvid_ms); - u32 ccbvid = in_be32(&sec->ccbvid); - u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> - SEC_SECVID_MS_IPID_SHIFT; - u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >> - SEC_SECVID_MS_MAJ_REV_SHIFT; - u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT; - - int i; - - if (era) /* This is '0' prior to CAAM ERA-6 */ - return era; - - for (i = 0; i < ARRAY_SIZE(caam_eras); i++) - if (caam_eras[i].ip_id == ip_id && - caam_eras[i].maj_rev == maj_rev) - return caam_eras[i].era; - - return 0; -} - -static void fdt_fixup_crypto_era(void *blob, u32 era) -{ - int err; - int crypto_node; - - crypto_node = fdt_path_offset(blob, "crypto"); - if (crypto_node < 0) { - printf("WARNING: Missing crypto node\n"); - return; - } - - err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era, - sizeof(era)); - if (err < 0) { - printf("ERROR: could not set fsl,sec-era property: %s\n", - fdt_strerror(err)); - } -} - -void fdt_fixup_crypto_node(void *blob, int sec_rev) -{ - u8 era; - - if (!sec_rev) { - fdt_del_node_and_alias(blob, "crypto"); - return; - } - - /* Add SEC ERA information in compatible */ - era = caam_get_era(); - if (era) { - fdt_fixup_crypto_era(blob, era); - } else { - printf("WARNING: Unable to get ERA for CAAM rev: %d\n", - sec_rev); - } -} -#endif - int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { return fdt_setprop_string(blob, offset, "phy-connection-type", diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 89a561e0ac..33d53a8cfe 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -76,7 +76,8 @@ void disable_law(u8 idx) return; } -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_NAND_SPL) && \ + (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) static int get_law_entry(u8 i, struct law_entry *e) { u32 lawar; @@ -106,7 +107,8 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) return idx; } -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_NAND_SPL) && \ + (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; @@ -219,6 +221,32 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) } #endif /* not SPL */ +void disable_non_ddr_laws(void) +{ + int i; + int id; + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + u32 lawar = in_be32(LAWAR_ADDR(i)); + + if (lawar & LAW_EN) { + id = (lawar & ~LAW_EN) >> 20; + switch (id) { + case LAW_TRGT_IF_DDR_1: + case LAW_TRGT_IF_DDR_2: + case LAW_TRGT_IF_DDR_3: + case LAW_TRGT_IF_DDR_4: + case LAW_TRGT_IF_DDR_INTRLV: + case LAW_TRGT_IF_DDR_INTLV_34: + case LAW_TRGT_IF_DDR_INTLV_123: + case LAW_TRGT_IF_DDR_INTLV_1234: + continue; + default: + disable_law(i); + } + } + } +} + void init_laws(void) { int i; @@ -231,6 +259,23 @@ void init_laws(void) #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \ + !defined(CONFIG_E500MC) + /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms, + * which is not disabled before transferring the control to uboot. + * Disable the LAW 0 entry here. + */ + disable_law(0); +#endif + +#if !defined(CONFIG_SECURE_BOOT) + /* + * if any non DDR LAWs has been created earlier, remove them before + * LAW table is parsed. + */ + disable_non_ddr_laws(); +#endif + /* * Any LAWs that were set up before we booted assume they are meant to * be around and mark them used. @@ -242,15 +287,6 @@ void init_laws(void) gd->arch.used_laws |= (1 << i); } -#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) - /* - * in SPL boot we've already parsed the law_table and setup those LAWs - * so don't do it again. - */ - return; -#endif - for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c index 4417646f83..717e7badbe 100644 --- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c +++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c @@ -23,7 +23,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c index 52340f209d..36e7b01e8c 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c @@ -23,7 +23,7 @@ * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* define DEBUG for debugging output (obviously ;-)) */ diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index fe928db039..71bb9d776f 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -49,7 +49,6 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void update_rdcc(void) { u32 val; @@ -72,7 +71,6 @@ static void update_rdcc(void) } } } -#endif #if defined(CONFIG_440) /* @@ -101,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes); #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) -#if !defined(CONFIG_NAND_SPL) /*-----------------------------------------------------------------------------+ * sdram_memsize *-----------------------------------------------------------------------------*/ @@ -217,7 +214,6 @@ void board_add_ram_info(int use_default) val = (val & SDRAM_MMODE_DCL_MASK) >> 4; printf(", CL%d)", val); } -#endif /* !CONFIG_NAND_SPL */ #if defined(CONFIG_SPD_EEPROM) @@ -1665,7 +1661,7 @@ static void program_mode(unsigned long *dimm_populated, for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) - t_wr_ns = max(t_wr_ns, + t_wr_ns = max(t_wr_ns, (unsigned long) spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); } @@ -1842,12 +1838,18 @@ static void program_tr(unsigned long *dimm_populated, else sdram_ddr1 = false; - t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); - t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); - t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2); - t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30)); - t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41)); - t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42)); + t_rcd_ns = max(t_rcd_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); + t_rrd_ns = max(t_rrd_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); + t_rp_ns = max(t_rp_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2); + t_ras_ns = max(t_ras_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30)); + t_rc_ns = max(t_rc_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41)); + t_rfc_ns = max(t_rfc_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42)); } } @@ -1920,9 +1922,12 @@ static void program_tr(unsigned long *dimm_populated, for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) { - t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); - t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2); - t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2); + t_wpc_ns = max(t_wtr_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); + t_wtr_ns = max(t_wtr_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2); + t_rpc_ns = max(t_rpc_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2); } } @@ -2318,7 +2323,8 @@ static void program_ecc(unsigned long *dimm_populated, for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) - ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11)); + ecc = max(ecc, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11)); } if (ecc == 0) return; @@ -2843,16 +2849,6 @@ static void test(void) *---------------------------------------------------------------------------*/ phys_size_t initdram(int board_type) { - /* - * Only run this SDRAM init code once. For NAND booting - * targets like Kilauea, we call initdram() early from the - * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). - * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) - * which calls initdram() again. This time the controller - * mustn't be reconfigured again since we're already running - * from SDRAM. - */ -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) unsigned long val; #if defined(CONFIG_440) @@ -2969,12 +2965,10 @@ phys_size_t initdram(int board_type) #endif #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) /*------------------------------------------------------------------ | DQS calibration. +-----------------------------------------------------------------*/ DQS_autocalibration(); -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ /* @@ -3009,13 +3003,10 @@ phys_size_t initdram(int board_type) set_mcsr(get_mcsr()); #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ -#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ - return (CONFIG_SYS_MBYTES_SDRAM << 20); } #endif /* CONFIG_SPD_EEPROM */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #if defined(CONFIG_440) u32 mfdcr_any(u32 dcr) { @@ -3062,7 +3053,6 @@ void mtdcr_any(u32 dcr, u32 val) } } #endif /* defined(CONFIG_440) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ inline void ppc4xx_ibm_ddr2_register_dump(void) { diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 82823147fe..67f149deef 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -27,12 +27,6 @@ #include "ecc.h" -/* - * Only compile the DDR auto-calibration code for NOR boot and - * not for NAND boot (NAND SPL and NAND U-Boot - NUB) - */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - #define MAXBXCF 4 #define SDRAM_RXBAS_SHIFT_1M 20 @@ -1231,9 +1225,3 @@ u32 DQS_autocalibration(void) return 0; } -#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ -u32 DQS_autocalibration(void) -{ - return 0; -} -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c index 2ca355b134..b26ec2a611 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c @@ -1,26 +1,5 @@ -/*-----------------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of - * the GNU General Public license version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs * * File Name: 405gp_pci.c * @@ -84,10 +63,6 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_405GP) || defined(CONFIG_405EP) -#if defined(CONFIG_PMC405) -ushort pmc405_pci_subsys_deviceid(void); -#endif - /*#define DEBUG*/ /* @@ -164,14 +139,14 @@ void pci_405gp_init(struct pci_controller *hose) ptmla_str = getenv("ptm1la"); ptmms_str = getenv("ptm1ms"); if(NULL != ptmla_str && NULL != ptmms_str ) { - ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); + ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); } ptmla_str = getenv("ptm2la"); ptmms_str = getenv("ptm2ms"); if(NULL != ptmla_str && NULL != ptmms_str ) { - ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); + ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); } #endif diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index 1ad19abff6..c02058f79b 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -5,30 +5,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + * SPDX-License-Identifier: GPL-2.0 IBM-pibs */ #include @@ -40,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ +#if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_440) @@ -91,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR; #define UDIV_SUBTRACT 0 #define UART0_SDR SDR0_UART0 #define UART1_SDR SDR0_UART1 -#else /* CONFIG_405GP || CONFIG_405CR */ +#else /* CONFIG_405GP */ #define CR0_MASK 0x00001fff #define CR0_EXTCLK_ENA 0x000000c0 #define CR0_UDIV_POS 1 @@ -196,7 +173,7 @@ int get_serial_clock(void) * Let's handle this in some #ifdef's for the SoC's. */ -#if defined(CONFIG_405CR) || defined(CONFIG_405GP) +#if defined(CONFIG_405GP) reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; @@ -223,7 +200,7 @@ int get_serial_clock(void) #else clk = CONFIG_SYS_BASE_BAUD * 16; #endif -#endif /* CONFIG_405CR */ +#endif #if defined(CONFIG_405EP) { @@ -288,4 +265,4 @@ int get_serial_clock(void) return clk; } -#endif /* CONFIG_405GP || CONFIG_405CR */ +#endif /* CONFIG_405GP */ diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig new file mode 100644 index 0000000000..5db5e34627 --- /dev/null +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -0,0 +1,226 @@ +menu "ppc4xx CPU" + depends on 4xx + +config SYS_CPU + default "ppc4xx" + +choice + prompt "Target select" + +config TARGET_CSB272 + bool "Support csb272" + +config TARGET_CSB472 + bool "Support csb472" + +config TARGET_JSE + bool "Support JSE" + +config TARGET_KORAT + bool "Support korat" + +config TARGET_LWMON5 + bool "Support lwmon5" + select SUPPORT_SPL + +config TARGET_PCS440EP + bool "Support pcs440ep" + +config TARGET_SBC405 + bool "Support sbc405" + +config TARGET_SC3 + bool "Support sc3" + +config TARGET_T3CORP + bool "Support t3corp" + +config TARGET_W7OLMC + bool "Support W7OLMC" + +config TARGET_W7OLMG + bool "Support W7OLMG" + +config TARGET_ZEUS + bool "Support zeus" + +config TARGET_ACADIA + bool "Support acadia" + +config TARGET_BAMBOO + bool "Support bamboo" + +config TARGET_BUBINGA + bool "Support bubinga" + +config TARGET_CANYONLANDS + bool "Support canyonlands" + +config TARGET_EBONY + bool "Support ebony" + +config TARGET_KATMAI + bool "Support katmai" + +config TARGET_KILAUEA + bool "Support kilauea" + +config TARGET_LUAN + bool "Support luan" + +config TARGET_MAKALU + bool "Support makalu" + +config TARGET_OCOTEA + bool "Support ocotea" + +config TARGET_REDWOOD + bool "Support redwood" + +config TARGET_SEQUOIA + bool "Support sequoia" + +config TARGET_TAIHU + bool "Support taihu" + +config TARGET_TAISHAN + bool "Support taishan" + +config TARGET_WALNUT + bool "Support walnut" + +config TARGET_YOSEMITE + bool "Support yosemite" + +config TARGET_YUCCA + bool "Support yucca" + +config TARGET_FX12MM + bool "Support fx12mm" + +config TARGET_V5FX30TEVAL + bool "Support v5fx30teval" + +config TARGET_CPCI2DP + bool "Support CPCI2DP" + +config TARGET_CPCI4052 + bool "Support CPCI4052" + +config TARGET_PLU405 + bool "Support PLU405" + +config TARGET_PMC405DE + bool "Support PMC405DE" + +config TARGET_PMC440 + bool "Support PMC440" + +config TARGET_VOM405 + bool "Support VOM405" + +config TARGET_DLVISION_10G + bool "Support dlvision-10g" + +config TARGET_IO + bool "Support io" + +config TARGET_IOCON + bool "Support iocon" + +config TARGET_NEO + bool "Support neo" + +config TARGET_IO64 + bool "Support io64" + +config TARGET_DLVISION + bool "Support dlvision" + +config TARGET_GDPPC440ETX + bool "Support gdppc440etx" + +config TARGET_INTIP + bool "Support intip" + +config TARGET_ICON + bool "Support icon" + +config TARGET_MIP405 + bool "Support MIP405" + +config TARGET_PIP405 + bool "Support PIP405" + +config TARGET_ALPR + bool "Support alpr" + +config TARGET_P3P440 + bool "Support p3p440" + +config TARGET_XPEDITE1000 + bool "Support xpedite1000" + +config TARGET_ML507 + bool "Support ml507" + +config TARGET_XILINX_PPC405_GENERIC + bool "Support xilinx-ppc405-generic" + +config TARGET_XILINX_PPC440_GENERIC + bool "Support xilinx-ppc440-generic" + +endchoice + +source "board/amcc/acadia/Kconfig" +source "board/amcc/bamboo/Kconfig" +source "board/amcc/bubinga/Kconfig" +source "board/amcc/canyonlands/Kconfig" +source "board/amcc/ebony/Kconfig" +source "board/amcc/katmai/Kconfig" +source "board/amcc/kilauea/Kconfig" +source "board/amcc/luan/Kconfig" +source "board/amcc/makalu/Kconfig" +source "board/amcc/ocotea/Kconfig" +source "board/amcc/redwood/Kconfig" +source "board/amcc/sequoia/Kconfig" +source "board/amcc/taihu/Kconfig" +source "board/amcc/taishan/Kconfig" +source "board/amcc/walnut/Kconfig" +source "board/amcc/yosemite/Kconfig" +source "board/amcc/yucca/Kconfig" +source "board/avnet/fx12mm/Kconfig" +source "board/avnet/v5fx30teval/Kconfig" +source "board/csb272/Kconfig" +source "board/csb472/Kconfig" +source "board/esd/cpci2dp/Kconfig" +source "board/esd/cpci405/Kconfig" +source "board/esd/plu405/Kconfig" +source "board/esd/pmc405de/Kconfig" +source "board/esd/pmc440/Kconfig" +source "board/esd/vom405/Kconfig" +source "board/gdsys/405ep/Kconfig" +source "board/gdsys/405ex/Kconfig" +source "board/gdsys/dlvision/Kconfig" +source "board/gdsys/gdppc440etx/Kconfig" +source "board/gdsys/intip/Kconfig" +source "board/jse/Kconfig" +source "board/korat/Kconfig" +source "board/lwmon5/Kconfig" +source "board/mosaixtech/icon/Kconfig" +source "board/mpl/mip405/Kconfig" +source "board/mpl/pip405/Kconfig" +source "board/pcs440ep/Kconfig" +source "board/prodrive/alpr/Kconfig" +source "board/prodrive/p3p440/Kconfig" +source "board/sbc405/Kconfig" +source "board/sc3/Kconfig" +source "board/t3corp/Kconfig" +source "board/w7o/Kconfig" +source "board/xes/xpedite1000/Kconfig" +source "board/xilinx/ml507/Kconfig" +source "board/xilinx/ppc405-generic/Kconfig" +source "board/xilinx/ppc440-generic/Kconfig" +source "board/zeus/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile index d38b4aa701..4b792ae2d2 100644 --- a/arch/powerpc/cpu/ppc4xx/Makefile +++ b/arch/powerpc/cpu/ppc4xx/Makefile @@ -5,71 +5,45 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START := resetvec.o -START += start.o - -SOBJS := cache.o -SOBJS += dcr.o -SOBJS += kgdb.o - -COBJS := 40x_spd_sdram.o - -ifndef CONFIG_NAND_SPL -ifndef CONFIG_NAND_U_BOOT -COBJS += 44x_spd_ddr.o -endif -endif -COBJS-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o -COBJS-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o -COBJS += 4xx_pci.o -COBJS += 4xx_pcie.o -COBJS += bedbug_405.o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += cmd_chip_config.o -COBJS += cpu.o -COBJS += cpu_init.o -COBJS += denali_data_eye.o -COBJS += denali_spd_ddr2.o -COBJS += ecc.o -COBJS-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o -COBJS += fdt.o -COBJS += interrupts.o -COBJS-$(CONFIG_CMD_REGINFO) += reginfo.o -COBJS += sdram.o -COBJS += speed.o -COBJS += tlb.o -COBJS += traps.o -COBJS += usb.o -COBJS += usb_ohci.o -COBJS-$(CONFIG_XILINX_440) += xilinx_irq.o +extra-y := resetvec.o +extra-y += start.o + +obj-y := cache.o +obj-y += dcr.o +obj-y += kgdb.o + +obj-y += 40x_spd_sdram.o + +obj-y += 44x_spd_ddr.o +obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o +obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o +obj-y += 4xx_pci.o +obj-y += 4xx_pcie.o +obj-y += bedbug_405.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += cmd_chip_config.o +obj-y += cpu.o +obj-y += cpu_init.o +obj-y += denali_data_eye.o +obj-y += denali_spd_ddr2.o +obj-y += ecc.o +obj-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o +obj-y += fdt.o +obj-y += interrupts.o +obj-$(CONFIG_CMD_REGINFO) += reginfo.o +obj-y += sdram.o +obj-y += speed.o +obj-y += tlb.o +obj-y += traps.o +obj-y += usb.o +obj-y += usb_ohci.o +obj-$(CONFIG_XILINX_440) += xilinx_irq.o ifndef CONFIG_XILINX_440 -COBJS += 4xx_uart.o -COBJS += gpio.o -COBJS += miiphy.o -COBJS += uic.o +obj-y += 4xx_uart.o +obj-y += gpio.o +obj-y += miiphy.o +obj-y += uic.o endif ifdef CONFIG_SPL_BUILD -COBJS-y += spl_boot.o +obj-y += spl_boot.o endif - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk index c2b0f9aab6..f87c9dc49b 100644 --- a/arch/powerpc/cpu/ppc4xx/config.mk +++ b/arch/powerpc/cpu/ppc4xx/config.mk @@ -5,11 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -meabi -PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float +PLATFORM_CPPFLAGS += -mstring -msoft-float -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is440:=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is440:=$(shell grep CONFIG_440 $(cfg)) ifneq (,$(findstring CONFIG_440,$(is440))) PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index fe050985e5..aab65d405c 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -234,20 +234,6 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif -#if defined(CONFIG_APM821XX) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "RESERVED", - "RESERVED", - "RESERVED", - "NAND (8 bits)", - "NOR (8 bits)", - "NOR (8 bits) w/PLL Bypassed", - "I2C (Addr 0x54)", - "I2C (Addr 0x52)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; -#endif #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) @@ -320,25 +306,9 @@ int checkcpu (void) puts("405GP Rev. D"); break; -#ifdef CONFIG_405GP - case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ + case PVR_405GP_RE: puts("405GP Rev. E"); break; -#endif - - case PVR_405CR_RA: - puts("405CR Rev. A"); - break; - - case PVR_405CR_RB: - puts("405CR Rev. B"); - break; - -#ifdef CONFIG_405CR - case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ - puts("405CR Rev. C"); - break; -#endif case PVR_405GPR_RB: puts("405GPr Rev. B"); @@ -623,9 +593,6 @@ int checkcpu (void) #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]); -#ifdef CONFIG_NAND_U_BOOT - puts(", booting from NAND"); -#endif /* CONFIG_NAND_U_BOOT */ putc('\n'); #endif /* SDR0_PINSTP_SHIFT */ @@ -647,12 +614,12 @@ int checkcpu (void) #endif #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) - printf (" 16 kB I-Cache 16 kB D-Cache"); + printf(" 16 KiB I-Cache 16 KiB D-Cache"); #elif defined(CONFIG_440) - printf (" 32 kB I-Cache 32 kB D-Cache"); + printf(" 32 KiB I-Cache 32 KiB D-Cache"); #else - printf (" 16 kB I-Cache %d kB D-Cache", - ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); + printf(" 16 KiB I-Cache %d KiB D-Cache", + ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); #endif #endif /* !defined(CONFIG_405) */ diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index d53d882511..e5a0e21e36 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -12,9 +12,7 @@ #include #include -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) DECLARE_GLOBAL_DATA_PTR; -#endif #ifndef CONFIG_SYS_PLL_RECONFIG #define CONFIG_SYS_PLL_RECONFIG 0 @@ -286,7 +284,7 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \ - !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE) + !defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -326,7 +324,7 @@ cpu_init_f (void) * External Bus Controller (EBC) Setup */ #if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) -#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ +#if (defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_405)) /* @@ -442,7 +440,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ @@ -451,6 +449,11 @@ cpu_init_f (void) mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ + + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset((void *)gd, 0, sizeof(gd_t)); } /* diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S index c80bc45b14..6b13528c9a 100644 --- a/arch/powerpc/cpu/ppc4xx/dcr.S +++ b/arch/powerpc/cpu/ppc4xx/dcr.S @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -10,8 +10,6 @@ #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c index bd905d1586..eef9c5a17f 100644 --- a/arch/powerpc/cpu/ppc4xx/fdt.c +++ b/arch/powerpc/cpu/ppc4xx/fdt.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; -void __ft_board_setup(void *blob, bd_t *bd) +int __ft_board_setup(void *blob, bd_t *bd) { int rc; int i; @@ -60,8 +60,11 @@ void __ft_board_setup(void *blob, bd_t *bd) printf("Unable to update property EBC mappings, err=%s\n", fdt_strerror(rc)); } + + return 0; } -void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup"))); +int ft_board_setup(void *blob, bd_t *bd) + __attribute__((weak, alias("__ft_board_setup"))); /* * Fixup all PCIe nodes by setting the device_type property diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index dbc4a6c881..f274c5d564 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -10,7 +10,6 @@ #include #define CONFIG_405GP 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 297155fdaf..10147de089 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -1,25 +1,6 @@ -/*-----------------------------------------------------------------------------+ - | This source code is dual-licensed. You may use it under the terms of the - | GNU General Public License version 2, or under the license below. - | - | This source code has been made available to you by IBM on an AS-IS - | basis. Anyone receiving this source is licensed under IBM - | copyrights to use it in any way he or she deems fit, including - | copying it, modifying it, compiling it, and redistributing it either - | with or without modifications. No license under IBM patents or - | patent applications is to be implied by the copyright license. - | - | Any user of this software should understand that IBM cannot provide - | technical support for this software and will not be responsible for - | any consequences resulting from the use of this software. - | - | Any person who transfers this source code or any derivative work - | must include the IBM copyright notice, this paragraph, and the - | preceding two paragraphs in the transferred software. - | - | COPYRIGHT I B M CORPORATION 1995 - | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - +-----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /*-----------------------------------------------------------------------------+ | | File Name: miiphy.c diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c index 2d95bc53c2..d4ef36d39f 100644 --- a/arch/powerpc/cpu/ppc4xx/sdram.c +++ b/arch/powerpc/cpu/ppc4xx/sdram.c @@ -8,7 +8,7 @@ * (C) Copyright 2002-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 3345e73347..3e1a7016d9 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -19,9 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUGF(fmt,args...) #endif -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) +#if defined(CONFIG_405GP) void get_sys_info (PPC4xx_SYS_INFO * sysInfo) { @@ -173,7 +171,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -234,78 +232,6 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } -#if defined(CONFIG_APM821XX) - -void get_sys_info(sys_info_t *sysInfo) -{ - unsigned long plld; - unsigned long temp; - unsigned long mul; - unsigned long cpudv; - unsigned long plb2dv; - unsigned long ddr2dv; - - /* Calculate Forward divisor A and Feeback divisor */ - mfcpr(CPR0_PLLD, plld); - - temp = CPR0_PLLD_FWDVA(plld); - sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); - - temp = CPR0_PLLD_FDV(plld); - sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); - - /* Calculate OPB clock divisor */ - mfcpr(CPR0_OPBD, temp); - temp = CPR0_OPBD_OPBDV(temp); - sysInfo->pllOpbDiv = temp ? temp : 4; - - /* Calculate Peripheral clock divisor */ - mfcpr(CPR0_PERD, temp); - temp = CPR0_PERD_PERDV(temp); - sysInfo->pllExtBusDiv = temp ? temp : 4; - - /* Calculate CPU clock divisor */ - mfcpr(CPR0_CPUD, temp); - temp = CPR0_CPUD_CPUDV(temp); - cpudv = temp ? temp : 8; - - /* Calculate PLB2 clock divisor */ - mfcpr(CPR0_PLB2D, temp); - temp = CPR0_PLB2D_PLB2DV(temp); - plb2dv = temp ? temp : 4; - - /* Calculate DDR2 clock divisor */ - mfcpr(CPR0_DDR2D, temp); - temp = CPR0_DDR2D_DDR2DV(temp); - ddr2dv = temp ? temp : 4; - - /* Calculate 'M' based on feedback source */ - mfcpr(CPR0_PLLC, temp); - temp = CPR0_PLLC_SEL(temp); - if (temp == 0) { - /* PLL internal feedback */ - mul = sysInfo->pllFbkDiv; - } else { - /* PLL PerClk feedback */ - mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv - * plb2dv * 2 * sysInfo->pllOpbDiv * - sysInfo->pllExtBusDiv; - } - - /* Now calculate the individual clocks */ - sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); - sysInfo->freqProcessor = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv; - sysInfo->freqPLB = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv / plb2dv / 2; - sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; - sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; - sysInfo->freqDDR = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; - sysInfo->freqUART = sysInfo->freqPLB; -} - -#else /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -363,7 +289,6 @@ void get_sys_info (sys_info_t * sysInfo) return; } -#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -1184,7 +1109,7 @@ ulong get_bus_freq (ulong dummy) { ulong val; -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ +#if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_405) || \ defined(CONFIG_440) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 57ae1d3820..09a02d771c 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -6,46 +6,7 @@ * Copyright (c) 2008 Nuovation System Designs, LLC * Grant Erickson * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/*------------------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *------------------------------------------------------------------------------- + * SPDX-License-Identifier: GPL-2.0 IBM-pibs */ /* @@ -70,8 +31,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include @@ -223,16 +182,13 @@ .extern ext_bus_cntlr_init -#ifdef CONFIG_NAND_U_BOOT - .extern reconfig_tlb0 -#endif /* * Set up GOT: Global Offset Table * * Use r12 to access the GOT */ -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) @@ -246,22 +202,7 @@ GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT -#endif /* CONFIG_NAND_SPL */ - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ - !defined(CONFIG_SPL_BUILD) - /* - * NAND U-Boot image is started from offset 0 - */ - .text -#if defined(CONFIG_440) - bl reconfig_tlb0 -#endif - GET_GOT - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - bl board_init_f - /* NOTREACHED - board_init_f() does not return */ -#endif +#endif /* CONFIG_SPL_BUILD */ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD) /* @@ -296,9 +237,7 @@ */ #if defined(CONFIG_440) -#if !defined(CONFIG_NAND_SPL) .section .bootpg,"ax" -#endif .globl _start_440 /**************************************************************************/ @@ -552,7 +491,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */ * r3 - 1st arg to board_init(): IMMP pointer * r4 - 2nd arg to board_init(): boot flag */ -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) .text .long 0x27051956 /* U-Boot Magic Number */ .globl version_string @@ -725,8 +664,7 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -755,7 +693,7 @@ _start: ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ - defined(CONFIG_460GT) || defined(CONFIG_APM821XX) + defined(CONFIG_460GT) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -768,8 +706,7 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC @@ -818,9 +755,6 @@ _start: stwu r1,-8(r1) /* Save back chain and move SP */ stw r0,+12(r1) /* Save return addr (underflow vect) */ -#ifdef CONFIG_NAND_SPL - bl nand_boot_common /* will not return */ -#else #ifndef CONFIG_SPL_BUILD GET_GOT #endif @@ -828,12 +762,11 @@ _start: bl cpu_init_f /* run low-level CPU init code (from Flash) */ bl board_init_f /* NOTREACHED - board_init_f() does not return */ -#endif #endif /* CONFIG_440 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ +#if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_405) /*----------------------------------------------------------------------- */ @@ -1091,9 +1024,6 @@ _start: stw r0, +12(r1) /* Save return addr (underflow vect) */ #endif /* CONFIG_SYS_INIT_DCACHE_CS */ -#ifdef CONFIG_NAND_SPL - bl nand_boot_common /* will not return */ -#else GET_GOT /* initialize GOT access */ bl cpu_init_f /* run low-level CPU init code (from Flash) */ @@ -1101,13 +1031,11 @@ _start: bl board_init_f /* run first part of init code (from Flash) */ /* NOTREACHED - board_init_f() does not return */ -#endif /* CONFIG_NAND_SPL */ - -#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ +#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */ /*----------------------------------------------------------------------- */ -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) /* * This code finishes saving the registers to the exception frame * and jumps to the appropriate handler for the exception. @@ -1673,7 +1601,7 @@ __440_msr_continue: blr function_epilog(dcbz_area) #endif /* CONFIG_440 */ -#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_SPL_BUILD */ /*------------------------------------------------------------------------------- */ /* Function: in8 */ @@ -2022,75 +1950,3 @@ pll_wait: blr function_epilog(mftlb1) #endif /* CONFIG_440 */ - -#if defined(CONFIG_NAND_SPL) -/* - * void nand_boot_relocate(dst, src, bytes) - * - * r3 = Destination address to copy code to (in SDRAM) - * r4 = Source address to copy code from - * r5 = size to copy in bytes - */ -nand_boot_relocate: - mr r6,r3 - mr r7,r4 - mflr r8 - - /* - * Copy SPL from icache into SDRAM - */ - subi r3,r3,4 - subi r4,r4,4 - srwi r5,r5,2 - mtctr r5 -..spl_loop: - lwzu r0,4(r4) - stwu r0,4(r3) - bdnz ..spl_loop - - /* - * Calculate "corrected" link register, so that we "continue" - * in execution in destination range - */ - sub r3,r7,r6 /* r3 = src - dst */ - sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ - mtlr r8 - blr - -nand_boot_common: - /* - * First initialize SDRAM. It has to be available *before* calling - * nand_boot(). - */ - lis r3,CONFIG_SYS_SDRAM_BASE@h - ori r3,r3,CONFIG_SYS_SDRAM_BASE@l - bl initdram - - /* - * Now copy the 4k SPL code into SDRAM and continue execution - * from there. - */ - lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h - ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l - lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h - ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l - lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h - ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l - bl nand_boot_relocate - - /* - * We're running from SDRAM now!!! - * - * It is necessary for 4xx systems to relocate from running at - * the original location (0xfffffxxx) to somewhere else (SDRAM - * preferably). This is because CS0 needs to be reconfigured for - * NAND access. And we can't reconfigure this CS when currently - * "running" from it. - */ - - /* - * Finally call nand_boot() to load main NAND U-Boot image from - * NAND and jump to it. - */ - bl nand_boot /* will not return */ -#endif /* CONFIG_NAND_SPL */ diff --git a/arch/powerpc/cpu/ppc4xx/tlb.c b/arch/powerpc/cpu/ppc4xx/tlb.c index 86521676f1..3cb09bda43 100644 --- a/arch/powerpc/cpu/ppc4xx/tlb.c +++ b/arch/powerpc/cpu/ppc4xx/tlb.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c index b371a752f9..65a0675446 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c @@ -40,8 +40,6 @@ #define readl(a) (*((volatile u32 *)(a))) #define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) #else @@ -847,104 +845,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ @@ -1549,7 +1450,7 @@ static void hc_release_ohci (ohci_t *ohci) */ static char ohci_inited = 0; -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { memset (&gohci, 0, sizeof (ohci_t)); memset (&urb_priv, 0, sizeof (urb_priv_t)); diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h index 01129ed4f0..dfaddb6f1d 100644 --- a/arch/powerpc/include/asm/8xx_immap.h +++ b/arch/powerpc/include/asm/8xx_immap.h @@ -1,4 +1,3 @@ - /* * MPC8xx Internal Memory Map * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h deleted file mode 100644 index 11c06a2239..0000000000 --- a/arch/powerpc/include/asm/apm821xx.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _APM821XX_H_ -#define _APM821XX_H_ - -#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ - -/* Memory mapped registers */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) - -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) - -#define SDR0_SRST0_DMC 0x00200000 -#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ - -/* AHB config. */ -#define AHB_TOP 0xA4 -#define AHB_BOT 0xA5 - -/* clk divisors */ -#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ -#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ -#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ -#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ -#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ -#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ -#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ -#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ -#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ - -/* - + * Clocking Controller - + */ -#define CPR0_CLKUPD 0x0020 -#define CPR0_PLLC 0x0040 -#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) -#define CPR0_PLLD 0x0060 -#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) -#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) -#define CPR0_CPUD 0x0080 -#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) -#define CPR0_PLB2D 0x00a0 -#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) -#define CPR0_OPBD 0x00c0 -#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) -#define CPR0_PERD 0x00e0 -#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) -#define CPR0_DDR2D 0x0100 -#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) -#define CLK_ICFG 0x0140 - -#endif /* _APM821XX_H_ */ diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h new file mode 100644 index 0000000000..8beed3037a --- /dev/null +++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes via , so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_MX85XX_GPIO_H +#define __ASM_ARCH_MX85XX_GPIO_H + +#endif diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h index 23f22df1b7..43a2bb2b3e 100644 --- a/arch/powerpc/include/asm/atomic.h +++ b/arch/powerpc/include/asm/atomic.h @@ -5,8 +5,6 @@ #ifndef _ASM_PPC_ATOMIC_H_ #define _ASM_PPC_ATOMIC_H_ -#include - #ifdef CONFIG_SMP typedef struct { volatile int counter; } atomic_t; #else diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index adaf091492..a6bcf3c3fe 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -5,7 +5,6 @@ #ifndef _PPC_BITOPS_H #define _PPC_BITOPS_H -#include #include extern void set_bit(int nr, volatile void *addr); diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index 5f9c640aa2..d3a83910b6 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -4,7 +4,6 @@ #ifndef __ARCH_PPC_CACHE_H #define __ARCH_PPC_CACHE_H -#include #include /* bytes per L1 cache line */ @@ -58,6 +57,12 @@ extern void unlock_ram_in_cache(void); #endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */ +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +int l2cache_init(void); +void enable_cpc(void); +void disable_cpc_sram(void); +#endif + /* prep registers for L2 */ #define CACHECRBA 0x80000823 /* Cache configuration register address */ #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 3c17c99146..65496d0d90 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -9,10 +9,16 @@ #ifdef CONFIG_MPC85xx #include +#define CONFIG_SYS_FSL_DDR #endif #ifdef CONFIG_MPC86xx #include +#define CONFIG_SYS_FSL_DDR +#endif + +#ifdef CONFIG_MPC83xx +#define CONFIG_SYS_FSL_DDR #endif #ifndef HWCONFIG_BUFFER_SIZE @@ -69,6 +75,7 @@ * SEC (crypto unit) major compatible version determination */ #if defined(CONFIG_MPC83xx) +#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SEC_COMPAT 2 #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7ed93acdcf..01b09058cc 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -19,7 +19,12 @@ */ #define CONFIG_PPC_SPINTABLE_COMPATIBLE -#define FSL_DDR_VER_4_7 47 +#include +#define CONFIG_SYS_FSL_DDR_BE + +/* IP endianness */ +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_SEC_BE /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) @@ -34,28 +39,35 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8540) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8541) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -67,21 +79,27 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8560) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8568) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 @@ -106,6 +124,8 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 @@ -115,6 +135,8 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1010) #define CONFIG_MAX_CPUS 1 @@ -125,13 +147,22 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 +#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A007075 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 +#define CONFIG_ESDHC_HC_BLK_ADDR /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -141,14 +172,18 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1012 is single core version of P1021 */ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -159,11 +194,14 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1013 is single core version of P1022 */ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -171,6 +209,8 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS 1 @@ -181,11 +221,13 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_A004508 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -195,11 +237,14 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -211,6 +256,11 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 @@ -225,6 +275,9 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 @@ -232,10 +285,13 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1023) #define CONFIG_MAX_CPUS 2 @@ -244,11 +300,16 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -258,14 +319,18 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -276,6 +341,8 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 /* P2010 is single core version of P2020 */ #elif defined(CONFIG_P2010) @@ -283,9 +350,12 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P2020) #define CONFIG_MAX_CPUS 2 @@ -300,9 +370,13 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 +#define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -311,6 +385,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -333,9 +408,13 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #elif defined(CONFIG_PPC_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -344,6 +423,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -351,6 +431,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_USB14 @@ -366,9 +447,14 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 +#define CONFIG_SYS_FSL_ERRATUM_A005812 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -379,6 +465,8 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" @@ -410,10 +498,15 @@ #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_A004580 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 +#define CONFIG_SYS_FSL_ERRATUM_A005812 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A007075 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -422,6 +515,8 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -440,10 +535,14 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5040) #define CONFIG_SYS_PPC64 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -454,6 +553,8 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" @@ -468,7 +569,9 @@ #define CONFIG_SYS_FSL_ERRATUM_A004699 #define CONFIG_SYS_FSL_ERRATUM_A004510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 +#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CONFIG_SYS_FSL_ERRATUM_A005812 #elif defined(CONFIG_BSC9131) #define CONFIG_MAX_CPUS 1 @@ -477,12 +580,16 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_BSC9132) #define CONFIG_MAX_CPUS 2 @@ -492,14 +599,26 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 +#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 +#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 +#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" - -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A005434 +#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_ESDHC_HC_BLK_ADDR + +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -508,41 +627,60 @@ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #ifdef CONFIG_PPC_T4240 #define CONFIG_MAX_CPUS 12 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #else -#define CONFIG_MAX_CPUS 8 -#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 7 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#if defined(CONFIG_PPC_T4160) +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#elif defined(CONFIG_PPC_T4080) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } +#endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM1_CLK 3 +#define CONFIG_SYS_FM2_CLK 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_SRIO_LIODN #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007798 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) @@ -552,8 +690,12 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 @@ -563,54 +705,204 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007075 +#define CONFIG_SYS_FSL_ERRATUM_A006475 +#define CONFIG_SYS_FSL_ERRATUM_A006384 +#define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#endif +#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) #define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 +#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) +#define CONFIG_MAX_CPUS 2 +#endif +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CONFIG_SYS_SDHC_CLOCK 0 #define CONFIG_SYS_FSL_NUM_LAWS 16 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_PME_PLAT_CLK_DIV 2 +#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FSL_ERRATUM_A008044 #define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_FM_PLAT_CLK_DIV 1 +#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ +defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define CONFIG_E5500 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_SYS_FMAN_V3 +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#endif +#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define CONFIG_MAX_CPUS 1 +#endif +#define CONFIG_SYS_FSL_NUM_CC_PLL 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CONFIG_SYS_SDHC_CLOCK 0 +#define CONFIG_SYS_FSL_NUM_LAWS 16 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_QBMAN_CLK_DIV 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_SFP_VER_3_0 + +#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define CONFIG_E6500 +#define CONFIG_SYS_PPC64 /* 64-bit core */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_QMAN_V3 +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_PCI_VER_3_X +#if defined(CONFIG_PPC_T2080) +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 4 +#define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_FSL_SRIO_LIODN #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_SYS_NUM_FM1_DTSEC 6 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#endif +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_PME_PLAT_CLK_DIV 1 +#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ISBC_VER 2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007186 +#define CONFIG_SYS_FSL_ERRATUM_A006379 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define CONFIG_SYS_FSL_SFP_VER_3_0 + + +#elif defined(CONFIG_PPC_C29X) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 +#define CONFIG_TSECV2_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 6 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_ERRATUM_A005125 + +#elif defined(CONFIG_QEMU_E500) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 #else #error Processor type not defined for this platform @@ -626,4 +918,11 @@ #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 #endif +#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN4) +#define CONFIG_SYS_FSL_DDRC_GEN3 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h index 694b110302..4f9b2252be 100644 --- a/arch/powerpc/include/asm/config_mpc86xx.h +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -7,6 +7,8 @@ #ifndef _ASM_MPC86xx_CONFIG_H_ #define _ASM_MPC86xx_CONFIG_H_ +#define CONFIG_SYS_FSL_DDR_86XX + /* SoC specific defines for Freescale MPC86xx processors */ #if defined(CONFIG_MPC8610) diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h index 6a4a51a9aa..4f78186d9d 100644 --- a/arch/powerpc/include/asm/cpm_8260.h +++ b/arch/powerpc/include/asm/cpm_8260.h @@ -1,4 +1,3 @@ - /* * MPC8260 Communication Processor Module. * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h index 1681ecd507..b137a71450 100644 --- a/arch/powerpc/include/asm/cpm_85xx.h +++ b/arch/powerpc/include/asm/cpm_85xx.h @@ -1,4 +1,3 @@ - /* * MPC85xx Communication Processor Module * Copyright (c) 2003,Motorola Inc. diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h deleted file mode 100644 index ffe4db8b8a..0000000000 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef DDR2_DIMM_PARAMS_H -#define DDR2_DIMM_PARAMS_H - -#define EDC_DATA_PARITY 1 -#define EDC_ECC 2 -#define EDC_AC_PARITY 4 - -/* Parameters for a DDR2 dimm computed from the SPD */ -typedef struct dimm_params_s { - - /* DIMM organization parameters */ - char mpart[19]; /* guaranteed null terminated */ - - unsigned int n_ranks; - unsigned long long rank_density; - unsigned long long capacity; - unsigned int data_width; - unsigned int primary_sdram_width; - unsigned int ec_sdram_width; - unsigned int registered_dimm; - - /* SDRAM device parameters */ - unsigned int n_row_addr; - unsigned int n_col_addr; - unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ - unsigned int n_banks_per_sdram_device; - unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ - unsigned int row_density; - - /* used in computing base address of DIMMs */ - unsigned long long base_address; - /* mirrored DIMMs */ - unsigned int mirrored_dimm; /* only for ddr3 */ - - /* DIMM timing parameters */ - - unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ - unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ - unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ - unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ - - /* - * SDRAM clock periods - * The range for these are 1000-10000 so a short should be sufficient - */ - unsigned int tCKmin_X_ps; - unsigned int tCKmin_X_minus_1_ps; - unsigned int tCKmin_X_minus_2_ps; - unsigned int tCKmax_ps; - - /* SPD-defined CAS latencies */ - unsigned int caslat_X; - unsigned int caslat_X_minus_1; - unsigned int caslat_X_minus_2; - - unsigned int caslat_lowest_derated; /* Derated CAS latency */ - - /* basic timing parameters */ - unsigned int tRCD_ps; - unsigned int tRP_ps; - unsigned int tRAS_ps; - - unsigned int tWR_ps; /* maximum = 63750 ps */ - unsigned int tWTR_ps; /* maximum = 63750 ps */ - unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns - = 511750 ps */ - - unsigned int tRRD_ps; /* maximum = 63750 ps */ - unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - unsigned int refresh_rate_ps; - - /* DDR3 doesn't need these as below */ - unsigned int tIS_ps; /* byte 32, spd->ca_setup */ - unsigned int tIH_ps; /* byte 33, spd->ca_hold */ - unsigned int tDS_ps; /* byte 34, spd->data_setup */ - unsigned int tDH_ps; /* byte 35, spd->data_hold */ - unsigned int tRTP_ps; /* byte 38, spd->trtp */ - unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tQHS_ps; /* byte 45, spd->tqhs */ - - /* DDR3 RDIMM */ - unsigned char rcw[16]; /* Register Control Word 0-15 */ -} dimm_params_t; - -extern unsigned int ddr_compute_dimm_parameters( - const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number); - -#endif diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h deleted file mode 100644 index 640d3297d6..0000000000 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef FSL_DDR_MEMCTL_H -#define FSL_DDR_MEMCTL_H - -/* - * Pick a basic DDR Technology. - */ -#include - -#define SDRAM_TYPE_DDR1 2 -#define SDRAM_TYPE_DDR2 3 -#define SDRAM_TYPE_LPDDR1 6 -#define SDRAM_TYPE_DDR3 7 - -#define DDR_BL4 4 /* burst length 4 */ -#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ -#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ -#define DDR_BL8 8 /* burst length 8 */ - -#define DDR3_RTT_OFF 0 -#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ -#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ -#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ -#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ -#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ - -#define DDR2_RTT_OFF 0 -#define DDR2_RTT_75_OHM 1 -#define DDR2_RTT_150_OHM 2 -#define DDR2_RTT_50_OHM 3 - -#if defined(CONFIG_FSL_DDR1) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) -typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 -#endif -#elif defined(CONFIG_FSL_DDR2) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) -typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 -#endif -#elif defined(CONFIG_FSL_DDR3) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ -typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 -#endif -#endif /* #if defined(CONFIG_FSL_DDR1) */ - -#define FSL_DDR_ODT_NEVER 0x0 -#define FSL_DDR_ODT_CS 0x1 -#define FSL_DDR_ODT_ALL_OTHER_CS 0x2 -#define FSL_DDR_ODT_OTHER_DIMM 0x3 -#define FSL_DDR_ODT_ALL 0x4 -#define FSL_DDR_ODT_SAME_DIMM 0x5 -#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 -#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 - -/* define bank(chip select) interleaving mode */ -#define FSL_DDR_CS0_CS1 0x40 -#define FSL_DDR_CS2_CS3 0x20 -#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) -#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) - -/* define memory controller interleaving mode */ -#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 -#define FSL_DDR_PAGE_INTERLEAVING 0x1 -#define FSL_DDR_BANK_INTERLEAVING 0x2 -#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 -#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA -#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC -#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD -/* placeholder for 4-way interleaving */ -#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A -#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C -#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D - -#define SDRAM_CS_CONFIG_EN 0x80000000 - -/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration - */ -#define SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG_SREN 0x40000000 -#define SDRAM_CFG_ECC_EN 0x20000000 -#define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 -#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 -#define SDRAM_CFG_DYN_PWR 0x00200000 -#define SDRAM_CFG_DBW_MASK 0x00180000 -#define SDRAM_CFG_DBW_SHIFT 19 -#define SDRAM_CFG_32_BE 0x00080000 -#define SDRAM_CFG_16_BE 0x00100000 -#define SDRAM_CFG_8_BE 0x00040000 -#define SDRAM_CFG_NCAP 0x00020000 -#define SDRAM_CFG_2T_EN 0x00008000 -#define SDRAM_CFG_BI 0x00000001 - -#define SDRAM_CFG2_D_INIT 0x00000010 -#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 -#define SDRAM_CFG2_ODT_NEVER 0 -#define SDRAM_CFG2_ODT_ONLY_WRITE 1 -#define SDRAM_CFG2_ODT_ONLY_READ 2 -#define SDRAM_CFG2_ODT_ALWAYS 3 - -#define TIMING_CFG_2_CPO_MASK 0x0F800000 - -#if defined(CONFIG_P4080) -#define RD_TO_PRE_MASK 0xf -#define RD_TO_PRE_SHIFT 13 -#define WR_DATA_DELAY_MASK 0xf -#define WR_DATA_DELAY_SHIFT 9 -#else -#define RD_TO_PRE_MASK 0x7 -#define RD_TO_PRE_SHIFT 13 -#define WR_DATA_DELAY_MASK 0x7 -#define WR_DATA_DELAY_SHIFT 10 -#endif - -/* DDR_MD_CNTL */ -#define MD_CNTL_MD_EN 0x80000000 -#define MD_CNTL_CS_SEL_CS0 0x00000000 -#define MD_CNTL_CS_SEL_CS1 0x10000000 -#define MD_CNTL_CS_SEL_CS2 0x20000000 -#define MD_CNTL_CS_SEL_CS3 0x30000000 -#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 -#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 -#define MD_CNTL_MD_SEL_MR 0x00000000 -#define MD_CNTL_MD_SEL_EMR 0x01000000 -#define MD_CNTL_MD_SEL_EMR2 0x02000000 -#define MD_CNTL_MD_SEL_EMR3 0x03000000 -#define MD_CNTL_SET_REF 0x00800000 -#define MD_CNTL_SET_PRE 0x00400000 -#define MD_CNTL_CKE_CNTL_LOW 0x00100000 -#define MD_CNTL_CKE_CNTL_HIGH 0x00200000 -#define MD_CNTL_WRCW 0x00080000 -#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) - -/* DDR_CDR1 */ -#define DDR_CDR1_DHC_EN 0x80000000 -#define DDR_CDR1_ODT_SHIFT 17 -#define DDR_CDR1_ODT_MASK 0x6 -#define DDR_CDR2_ODT_MASK 0x1 -#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) -#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) - -#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ - (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) -#define DDR_CDR_ODT_OFF 0x0 -#define DDR_CDR_ODT_120ohm 0x1 -#define DDR_CDR_ODT_180ohm 0x2 -#define DDR_CDR_ODT_75ohm 0x3 -#define DDR_CDR_ODT_110ohm 0x4 -#define DDR_CDR_ODT_60hm 0x5 -#define DDR_CDR_ODT_70ohm 0x6 -#define DDR_CDR_ODT_47ohm 0x7 -#else -#define DDR_CDR_ODT_75ohm 0x0 -#define DDR_CDR_ODT_55ohm 0x1 -#define DDR_CDR_ODT_60ohm 0x2 -#define DDR_CDR_ODT_50ohm 0x3 -#define DDR_CDR_ODT_150ohm 0x4 -#define DDR_CDR_ODT_43ohm 0x5 -#define DDR_CDR_ODT_120ohm 0x6 -#endif - -/* Record of register values computed */ -typedef struct fsl_ddr_cfg_regs_s { - struct { - unsigned int bnds; - unsigned int config; - unsigned int config_2; - } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; - unsigned int timing_cfg_3; - unsigned int timing_cfg_0; - unsigned int timing_cfg_1; - unsigned int timing_cfg_2; - unsigned int ddr_sdram_cfg; - unsigned int ddr_sdram_cfg_2; - unsigned int ddr_sdram_mode; - unsigned int ddr_sdram_mode_2; - unsigned int ddr_sdram_mode_3; - unsigned int ddr_sdram_mode_4; - unsigned int ddr_sdram_mode_5; - unsigned int ddr_sdram_mode_6; - unsigned int ddr_sdram_mode_7; - unsigned int ddr_sdram_mode_8; - unsigned int ddr_sdram_md_cntl; - unsigned int ddr_sdram_interval; - unsigned int ddr_data_init; - unsigned int ddr_sdram_clk_cntl; - unsigned int ddr_init_addr; - unsigned int ddr_init_ext_addr; - unsigned int timing_cfg_4; - unsigned int timing_cfg_5; - unsigned int ddr_zq_cntl; - unsigned int ddr_wrlvl_cntl; - unsigned int ddr_wrlvl_cntl_2; - unsigned int ddr_wrlvl_cntl_3; - unsigned int ddr_sr_cntr; - unsigned int ddr_sdram_rcw_1; - unsigned int ddr_sdram_rcw_2; - unsigned int ddr_eor; - unsigned int ddr_cdr1; - unsigned int ddr_cdr2; - unsigned int err_disable; - unsigned int err_int_en; - unsigned int debug[32]; -} fsl_ddr_cfg_regs_t; - -typedef struct memctl_options_partial_s { - unsigned int all_DIMMs_ECC_capable; - unsigned int all_DIMMs_tCKmax_ps; - unsigned int all_DIMMs_burst_lengths_bitmask; - unsigned int all_DIMMs_registered; - unsigned int all_DIMMs_unbuffered; - /* unsigned int lowest_common_SPD_caslat; */ - unsigned int all_DIMMs_minimum_tRCD_ps; -} memctl_options_partial_t; - -#define DDR_DATA_BUS_WIDTH_64 0 -#define DDR_DATA_BUS_WIDTH_32 1 -#define DDR_DATA_BUS_WIDTH_16 2 -/* - * Generalized parameters for memory controller configuration, - * might be a little specific to the FSL memory controller - */ -typedef struct memctl_options_s { - /* - * Memory organization parameters - * - * if DIMM is present in the system - * where DIMMs are with respect to chip select - * where chip selects are with respect to memory boundaries - */ - unsigned int registered_dimm_en; /* use registered DIMM support */ - - /* Options local to a Chip Select */ - struct cs_local_opts_s { - unsigned int auto_precharge; - unsigned int odt_rd_cfg; - unsigned int odt_wr_cfg; - unsigned int odt_rtt_norm; - unsigned int odt_rtt_wr; - } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; - - /* Special configurations for chip select */ - unsigned int memctl_interleaving; - unsigned int memctl_interleaving_mode; - unsigned int ba_intlv_ctl; - unsigned int addr_hash; - - /* Operational mode parameters */ - unsigned int ECC_mode; /* Use ECC? */ - /* Initialize ECC using memory controller? */ - unsigned int ECC_init_using_memctl; - unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */ - /* SREN - self-refresh during sleep */ - unsigned int self_refresh_in_sleep; - unsigned int dynamic_power; /* DYN_PWR */ - /* memory data width to use (16-bit, 32-bit, 64-bit) */ - unsigned int data_bus_width; - unsigned int burst_length; /* BL4, OTF and BL8 */ - /* On-The-Fly Burst Chop enable */ - unsigned int OTF_burst_chop_en; - /* mirrior DIMMs for DDR3 */ - unsigned int mirrored_dimm; - unsigned int quad_rank_present; - unsigned int ap_en; /* address parity enable for RDIMM */ - - /* Global Timing Parameters */ - unsigned int cas_latency_override; - unsigned int cas_latency_override_value; - unsigned int use_derated_caslat; - unsigned int additive_latency_override; - unsigned int additive_latency_override_value; - - unsigned int clk_adjust; /* */ - unsigned int cpo_override; - unsigned int write_data_delay; /* DQS adjust */ - - unsigned int wrlvl_override; - unsigned int wrlvl_sample; /* Write leveling */ - unsigned int wrlvl_start; - unsigned int wrlvl_ctl_2; - unsigned int wrlvl_ctl_3; - - unsigned int half_strength_driver_enable; - unsigned int twoT_en; - unsigned int threeT_en; - unsigned int bstopre; - unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ - unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ - - /* Rtt impedance */ - unsigned int rtt_override; /* rtt_override enable */ - unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ - unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ - - /* Automatic self refresh */ - unsigned int auto_self_refresh_en; - unsigned int sr_it; - /* ZQ calibration */ - unsigned int zq_en; - /* Write leveling */ - unsigned int wrlvl_en; - /* RCW override for RDIMM */ - unsigned int rcw_override; - unsigned int rcw_1; - unsigned int rcw_2; - /* control register 1 */ - unsigned int ddr_cdr1; - unsigned int ddr_cdr2; - - unsigned int trwt_override; - unsigned int trwt; /* read-to-write turnaround */ -} memctl_options_t; - -extern phys_size_t fsl_ddr_sdram(void); -extern phys_size_t fsl_ddr_sdram_size(void); -extern int fsl_use_spd(void); -extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); -u32 fsl_ddr_get_intl3r(void); - -/* - * The 85xx boards have a common prototype for fixed_sdram so put the - * declaration here. - */ -#ifdef CONFIG_MPC85xx -extern phys_size_t fixed_sdram(void); -#endif - -#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - - -typedef struct fixed_ddr_parm{ - int min_freq; - int max_freq; - fsl_ddr_cfg_regs_t *ddr_settings; -} fixed_ddr_parm_t; -#endif diff --git a/arch/powerpc/include/asm/fsl_enet.h b/arch/powerpc/include/asm/fsl_enet.h deleted file mode 100644 index 96146b6e32..0000000000 --- a/arch/powerpc/include/asm/fsl_enet.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_PPC_FSL_ENET_H -#define __ASM_PPC_FSL_ENET_H - -#include - -struct tsec_mii_mng { - u32 miimcfg; /* MII management configuration reg */ - u32 miimcom; /* MII management command reg */ - u32 miimadd; /* MII management address reg */ - u32 miimcon; /* MII management control reg */ - u32 miimstat; /* MII management status reg */ - u32 miimind; /* MII management indication reg */ - u32 ifstat; /* Interface Status Register */ -} __attribute__ ((packed)); - -int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); - -#endif /* __ASM_PPC_FSL_ENET_H */ diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h new file mode 100644 index 0000000000..61c6d70c4b --- /dev/null +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -0,0 +1,53 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_FSL_ERRATA_H +#define _ASM_FSL_ERRATA_H + +#include +#include + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) + return true; + + return false; +} +#endif +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 +static inline bool has_erratum_a007186(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + return IS_SVR_REV(svr, 2, 0); + case SVR_T4160: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4860: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4420: + return IS_SVR_REV(svr, 2, 0); + case SVR_T2081: + case SVR_T2080: + return IS_SVR_REV(svr, 1, 0); + } + + return false; +} +#endif diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h index 4f71341327..d6537fd633 100644 --- a/arch/powerpc/include/asm/fsl_i2c.h +++ b/arch/powerpc/include/asm/fsl_i2c.h @@ -54,6 +54,7 @@ typedef struct fsl_i2c { #define I2C_CR_MTX 0x10 #define I2C_CR_TXAK 0x08 #define I2C_CR_RSTA 0x04 +#define I2C_CR_BIT6 0x02 /* required for workaround A004447 */ #define I2C_CR_BCST 0x01 u8 sr; /* I2C status register */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index bea1636768..3b504875e0 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -68,6 +68,7 @@ enum law_trgt_if { LAW_TRGT_IF_DDR_INTLV_1234 = 0x16, LAW_TRGT_IF_BMAN = 0x18, LAW_TRGT_IF_DCSR = 0x1d, + LAW_TRGT_IF_CCSR = 0x1e, LAW_TRGT_IF_LBC = 0x1f, LAW_TRGT_IF_QMAN = 0x3c, @@ -82,7 +83,7 @@ enum law_trgt_if { #ifndef CONFIG_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) LAW_TRGT_IF_OCN_DSP = 0x03, #else #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) @@ -92,9 +93,14 @@ enum law_trgt_if { LAW_TRGT_IF_LBC = 0x04, LAW_TRGT_IF_CCSR = 0x08, LAW_TRGT_IF_DSP_CCSR = 0x09, + LAW_TRGT_IF_PLATFORM_SRAM = 0x0a, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, +#if defined(CONFIG_BSC9132) + LAW_TRGT_IF_CLASS_DSP = 0x0d, +#else LAW_TRGT_IF_RIO_2 = 0x0d, +#endif LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, LAW_TRGT_IF_DDR = 0x0f, LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 3f543d9249..811f034293 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -29,6 +29,13 @@ struct srio_liodn_id_table { + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ } +#define SET_SRIO_LIODN_BASE(port, id_a) \ + { .id = { id_a }, .num_ids = 1, .portid = port, \ + .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \ + + (port - 1) * 0x200 \ + + CONFIG_SYS_FSL_SRIO_ADDR, \ + } + struct liodn_id_table { const char * compat; u32 id[2]; @@ -84,14 +91,22 @@ extern void fdt_fixup_liodn(void *blob); CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) /* reg nodes for DMA start @ 0x300 */ -#define SET_DMA_LIODN(dmaNum, liodn) \ - SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\ +#define SET_DMA_LIODN(dmaNum, compat, liodn) \ + SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\ CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300) #define SET_SDHC_LIODN(sdhcNum, liodn) \ SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define SET_QE_LIODN(liodn) \ + SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\ + CONFIG_SYS_MPC85xx_QE_OFFSET) + +#define SET_TDM_LIODN(liodn) \ + SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\ + CONFIG_SYS_MPC85xx_TDM_OFFSET) + #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ CONFIG_SYS_FSL_QMAN_OFFSET, \ diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h index 4640e33a5e..bed2a40bb2 100644 --- a/arch/powerpc/include/asm/fsl_memac.h +++ b/arch/powerpc/include/asm/fsl_memac.h @@ -159,6 +159,7 @@ struct memac { #define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ #define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ #define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN) +#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */ /* HASHTABLE_CTRL - Hashtable control register */ #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ @@ -243,6 +244,7 @@ struct memac_mdio_controller { #define MDIO_STAT_PRE (1 << 5) #define MDIO_STAT_ENC (1 << 6) #define MDIO_STAT_HOLD_15_CLK (7 << 2) +#define MDIO_STAT_NEG (1 << 23) #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index c740da37ce..5be718b162 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2012 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,6 +13,16 @@ #define PEX_IP_BLK_REV_2_2 0x02080202 #define PEX_IP_BLK_REV_2_3 0x02080203 +#define PEX_IP_BLK_REV_3_0 0x02080300 + +/* Freescale-specific PCI config registers */ +#define FSL_PCI_PBFR 0x44 + +#define FSL_PCIE_CFG_RDY 0x4b0 +#define FSL_PROG_IF_AGENT 0x1 + +#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ +#define PCI_LTSSM_L0 0x16 /* L0 state */ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); @@ -149,7 +159,10 @@ typedef struct ccsr_pci { u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ char res23[200]; u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ - char res24[252]; + char res24[16]; + u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/ + u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/ + char res25[228]; } ccsr_fsl_pci_t; #define PCIE_CONFIG_PC 0x00020000 #define PCIE_CONFIG_OB_CK 0x00002000 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index c36f3c388a..b4c0c99b39 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -7,11 +7,30 @@ #ifndef __FSL_SECURE_BOOT_H #define __FSL_SECURE_BOOT_H +#ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#elif defined(CONFIG_BSC9132QDS) +#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 +#elif defined(CONFIG_C29XPCIE) +#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#if defined(CONFIG_B4860QDS) || \ + defined(CONFIG_T4240QDS) || \ + defined(CONFIG_T2080QDS) || \ + defined(CONFIG_T2080RDB) || \ + defined(CONFIG_T1040QDS) || \ + defined(CONFIG_T104xRDB) || \ + defined(CONFIG_PPC_T1023) || \ + defined(CONFIG_PPC_T1024) +#define CONFIG_SYS_CPC_REINIT_F +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + +#endif #endif diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 59189adb39..45e248eba1 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -62,19 +62,38 @@ enum srds_prtcl { QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ QSGMII_FM2_A, QSGMII_FM2_B, + XFI_FM1_MAC1, + XFI_FM1_MAC2, XFI_FM1_MAC9, XFI_FM1_MAC10, XFI_FM2_MAC9, XFI_FM2_MAC10, INTERLAKEN, - SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */ - SGMII_SW1_DTSEC2, - SGMII_SW1_DTSEC3, - SGMII_SW1_DTSEC4, - SGMII_SW1_DTSEC5, - SGMII_SW1_DTSEC6, - QSGMII_SW1_A, /* SW indicates on L2 swtich */ + QSGMII_SW1_A, /* Indicates ports on L2 Switch */ QSGMII_SW1_B, + SGMII_2500_FM1_DTSEC1, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC3, + SGMII_2500_FM1_DTSEC4, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC6, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SGMII_2500_FM2_DTSEC1, + SGMII_2500_FM2_DTSEC2, + SGMII_2500_FM2_DTSEC3, + SGMII_2500_FM2_DTSEC4, + SGMII_2500_FM2_DTSEC5, + SGMII_2500_FM2_DTSEC6, + SGMII_2500_FM2_DTSEC9, + SGMII_2500_FM2_DTSEC10, + SGMII_SW1_MAC1, + SGMII_SW1_MAC2, + SGMII_SW1_MAC3, + SGMII_SW1_MAC4, + SGMII_SW1_MAC5, + SGMII_SW1_MAC6, + SERDES_PRCTL_COUNT /* Keep this item the last one */ }; enum srds { @@ -86,10 +105,12 @@ enum srds { int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); +const char *serdes_clock_to_string(u32 clock); #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); #else int serdes_get_first_lane(enum srds_prtcl device); #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 8e59e8ba74..c57d9c0faf 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -100,16 +100,13 @@ struct arch_global_data { #if defined(CONFIG_4xx) u32 uart_clk; #endif /* CONFIG_4xx */ -#if defined(CONFIG_SYS_GT_6426x) - unsigned int mirror_hack[16]; -#endif #ifdef CONFIG_SYS_FPGA_COUNT unsigned fpga_state[CONFIG_SYS_FPGA_COUNT]; #endif #if defined(CONFIG_WD_MAX_RATE) unsigned long long wdt_last; /* trace watch-dog triggering rate */ #endif -#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5) +#if defined(CONFIG_LWMON5) unsigned long kbd_status; #endif }; diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 01c9efff97..bed80aa933 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -279,8 +279,8 @@ typedef struct ddr512x { u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ - u32 DQS_config_offset_count; /* DQS Config Offset Count */ - u32 DQS_config_offset_time; /* DQS Config Offset Time */ + u32 dqs_config_offset_count; /* DQS Config Offset Count */ + u32 dqs_config_offset_time; /* DQS Config Offset Time */ u32 DQS_delay_status; /* DQS Delay Status */ u32 res0[0xF]; u32 prioman_config1; /* Priority Manager Configuration */ @@ -1255,9 +1255,9 @@ static inline u32 get_pata_base (void) } #endif /* __ASSEMBLY__ */ -#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000 -#define CONFIG_SYS_MPC512x_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET) +#define CONFIG_SYS_MPC512x_USB1_OFFSET 0x4000 +#define CONFIG_SYS_MPC512x_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET) #define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim)) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 57189c9136..251840255b 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -14,6 +14,7 @@ #ifndef __IMMAP_83xx__ #define __IMMAP_83xx__ +#include #include #include #include @@ -277,107 +278,10 @@ typedef struct qesba83xx { } qesba83xx_t; /* - * DDR Memory Controller Memory Map + * DDR Memory Controller Memory Map for DDR1 + * The structure of DDR2, or DDR3 is defined in fsl_immap.h */ -#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) -typedef struct ccsr_ddr { - u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ - u8 res1[4]; - u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ - u8 res2[4]; - u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ - u8 res3[4]; - u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ - u8 res4[100]; - u32 cs0_config; /* Chip Select Configuration */ - u32 cs1_config; /* Chip Select Configuration */ - u32 cs2_config; /* Chip Select Configuration */ - u32 cs3_config; /* Chip Select Configuration */ - u8 res4a[48]; - u32 cs0_config_2; /* Chip Select Configuration 2 */ - u32 cs1_config_2; /* Chip Select Configuration 2 */ - u32 cs2_config_2; /* Chip Select Configuration 2 */ - u32 cs3_config_2; /* Chip Select Configuration 2 */ - u8 res5[48]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 sdram_data_init; /* SDRAM Data initialization */ - u8 res6[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res7[20]; - u32 init_addr; /* training init addr */ - u32 init_ext_addr; /* training init extended addr */ - u8 res8_1[16]; - u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ - u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u8 reg8_1a[8]; - u32 ddr_zq_cntl; /* ZQ calibration control*/ - u32 ddr_wrlvl_cntl; /* write leveling control*/ - u8 reg8_1aa[4]; - u32 ddr_sr_cntr; /* self refresh counter */ - u32 ddr_sdram_rcw_1; /* Control Words 1 */ - u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u8 reg_1ab[8]; - u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ - u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ - u8 res8_1b[104]; - u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ - u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ - u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ - u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ - u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ - u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ - u8 res8_1ba[0x908]; - u32 ddr_dsr1; /* Debug Status 1 */ - u32 ddr_dsr2; /* Debug Status 2 */ - u32 ddr_cdr1; /* Control Driver 1 */ - u32 ddr_cdr2; /* Control Driver 2 */ - u8 res8_1c[200]; - u32 ip_rev1; /* IP Block Revision 1 */ - u32 ip_rev2; /* IP Block Revision 2 */ - u32 eor; /* Enhanced Optimization Register */ - u8 res8_2[252]; - u32 mtcr; /* Memory Test Control Register */ - u8 res8_3[28]; - u32 mtp1; /* Memory Test Pattern 1 */ - u32 mtp2; /* Memory Test Pattern 2 */ - u32 mtp3; /* Memory Test Pattern 3 */ - u32 mtp4; /* Memory Test Pattern 4 */ - u32 mtp5; /* Memory Test Pattern 5 */ - u32 mtp6; /* Memory Test Pattern 6 */ - u32 mtp7; /* Memory Test Pattern 7 */ - u32 mtp8; /* Memory Test Pattern 8 */ - u32 mtp9; /* Memory Test Pattern 9 */ - u32 mtp10; /* Memory Test Pattern 10 */ - u8 res8_4[184]; - u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ - u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ - u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ - u8 res9[20]; - u32 capture_data_hi; /* Data Path Read Capture High */ - u32 capture_data_lo; /* Data Path Read Capture Low */ - u32 capture_ecc; /* Data Path Read Capture ECC */ - u8 res10[20]; - u32 err_detect; /* Error Detect */ - u32 err_disable; /* Error Disable */ - u32 err_int_en; - u32 capture_attributes; /* Error Attrs Capture */ - u32 capture_address; /* Error Addr Capture */ - u32 capture_ext_address; /* Error Extended Addr Capture */ - u32 err_sbe; /* Single-Bit ECC Error Management */ - u8 res11[164]; - u32 debug[32]; /* debug_1 to debug_32 */ - u8 res12[128]; -} ccsr_ddr_t; -#else +#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3) typedef struct ddr_cs_bnds { u32 csbnds; u8 res0[4]; @@ -739,8 +643,8 @@ typedef struct immap { u8 dll_ddr[0x100]; u8 dll_lbc[0x100]; u8 res1[0xE00]; -#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) - ccsr_ddr_t ddr; /* DDR Memory Controller Memory */ +#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) + struct ccsr_ddr ddr; /* DDR Memory Controller Memory */ #else ddr83xx_t ddr; /* DDR Memory Controller Memory */ #endif @@ -763,10 +667,17 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; +#ifndef CONFIG_MPC834x #ifdef CONFIG_HAS_FSL_MPH_USB -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */ +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ +#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 +#else +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 +#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ +#endif #else -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */ +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 +#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 #endif #elif defined(CONFIG_MPC8313) @@ -1022,7 +933,7 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) -#define CONFIG_SYS_MPC8xxx_DDR_ADDR \ +#define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) #define CONFIG_SYS_MPC83xx_DMA_ADDR \ @@ -1031,11 +942,15 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) -#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 +#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000 +#endif +#define CONFIG_SYS_MPC83xx_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) +#if defined(CONFIG_MPC834x) +#define CONFIG_SYS_MPC83xx_USB2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) #endif -#define CONFIG_SYS_MPC83xx_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 81b3322fe6..ace1d120c6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -15,9 +15,11 @@ #include #include #include -#include +#include +#include #include #include +#include typedef struct ccsr_local { u32 ccsrbarh; /* CCSR Base Addr High */ @@ -112,105 +114,6 @@ typedef struct ccsr_local_ecm { u8 res24[492]; } ccsr_local_ecm_t; -/* DDR memory controller registers */ -typedef struct ccsr_ddr { - u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ - u8 res1[4]; - u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ - u8 res2[4]; - u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ - u8 res3[4]; - u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ - u8 res4[100]; - u32 cs0_config; /* Chip Select Configuration */ - u32 cs1_config; /* Chip Select Configuration */ - u32 cs2_config; /* Chip Select Configuration */ - u32 cs3_config; /* Chip Select Configuration */ - u8 res4a[48]; - u32 cs0_config_2; /* Chip Select Configuration 2 */ - u32 cs1_config_2; /* Chip Select Configuration 2 */ - u32 cs2_config_2; /* Chip Select Configuration 2 */ - u32 cs3_config_2; /* Chip Select Configuration 2 */ - u8 res5[48]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 sdram_data_init; /* SDRAM Data initialization */ - u8 res6[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res7[20]; - u32 init_addr; /* training init addr */ - u32 init_ext_addr; /* training init extended addr */ - u8 res8_1[16]; - u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ - u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u8 reg8_1a[8]; - u32 ddr_zq_cntl; /* ZQ calibration control*/ - u32 ddr_wrlvl_cntl; /* write leveling control*/ - u8 reg8_1aa[4]; - u32 ddr_sr_cntr; /* self refresh counter */ - u32 ddr_sdram_rcw_1; /* Control Words 1 */ - u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u8 reg_1ab[8]; - u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ - u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ - u8 res8_1b[104]; - u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ - u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ - u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ - u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ - u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ - u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ - u8 res8_1ba[0x908]; - u32 ddr_dsr1; /* Debug Status 1 */ - u32 ddr_dsr2; /* Debug Status 2 */ - u32 ddr_cdr1; /* Control Driver 1 */ - u32 ddr_cdr2; /* Control Driver 2 */ - u8 res8_1c[200]; - u32 ip_rev1; /* IP Block Revision 1 */ - u32 ip_rev2; /* IP Block Revision 2 */ - u32 eor; /* Enhanced Optimization Register */ - u8 res8_2[252]; - u32 mtcr; /* Memory Test Control Register */ - u8 res8_3[28]; - u32 mtp1; /* Memory Test Pattern 1 */ - u32 mtp2; /* Memory Test Pattern 2 */ - u32 mtp3; /* Memory Test Pattern 3 */ - u32 mtp4; /* Memory Test Pattern 4 */ - u32 mtp5; /* Memory Test Pattern 5 */ - u32 mtp6; /* Memory Test Pattern 6 */ - u32 mtp7; /* Memory Test Pattern 7 */ - u32 mtp8; /* Memory Test Pattern 8 */ - u32 mtp9; /* Memory Test Pattern 9 */ - u32 mtp10; /* Memory Test Pattern 10 */ - u8 res8_4[184]; - u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ - u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ - u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ - u8 res9[20]; - u32 capture_data_hi; /* Data Path Read Capture High */ - u32 capture_data_lo; /* Data Path Read Capture Low */ - u32 capture_ecc; /* Data Path Read Capture ECC */ - u8 res10[20]; - u32 err_detect; /* Error Detect */ - u32 err_disable; /* Error Disable */ - u32 err_int_en; - u32 capture_attributes; /* Error Attrs Capture */ - u32 capture_address; /* Error Addr Capture */ - u32 capture_ext_address; /* Error Extended Addr Capture */ - u32 err_sbe; /* Single-Bit ECC Error Management */ - u8 res11[164]; - u32 debug[32]; /* debug_1 to debug_32 */ - u8 res12[128]; -} ccsr_ddr_t; - #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ @@ -282,7 +185,9 @@ typedef struct ccsr_pcix { u32 int_ack; /* PCIX IRQ Acknowledge */ u8 res000c[52]; u32 liodn_base; /* PCIX LIODN base register */ - u8 res0044[3004]; + u8 res0044[2996]; + u32 ipver1; /* PCIX IP block revision register 1 */ + u32 ipver2; /* PCIX IP block revision register 2 */ u32 potar0; /* PCIX Outbound Transaction Addr 0 */ u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ @@ -1544,6 +1449,18 @@ struct rio_pw { }; #endif +#ifdef CONFIG_SYS_FSL_SRIO_LIODN +struct rio_liodn { + u32 plbr; + u8 res0[28]; + u32 plaor; + u8 res1[12]; + u32 pludr; + u32 plldr; + u8 res2[456]; +}; +#endif + /* RapidIO Registers */ struct ccsr_rio { struct rio_arch arch; @@ -1566,6 +1483,10 @@ struct ccsr_rio { u8 res7[100]; struct rio_pw pw; #endif +#ifdef CONFIG_SYS_FSL_SRIO_LIODN + u8 res5[8192]; + struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +#endif }; #endif @@ -1655,6 +1576,7 @@ typedef struct cpc_corenet { #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 +#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ @@ -1662,6 +1584,12 @@ typedef struct cpc_corenet { typedef struct ccsr_gur { u32 porsr1; /* POR status 1 */ u32 porsr2; /* POR status 2 */ +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15 +#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1 +#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1 +#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0 +#endif u8 res_008[0x20-0x8]; u32 gpporcr1; /* General-purpose POR configuration */ u32 gpporcr2; /* General-purpose POR configuration 2 */ @@ -1698,8 +1626,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 +#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000 +#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000 +#else #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 +#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 +#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 +#endif #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 @@ -1799,6 +1734,9 @@ typedef struct ccsr_gur { u32 rstrqpblsr; /* Reset request preboot loader status */ u8 res11[8]; u32 rstrqmr1; /* Reset request mask */ +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800 +#endif u8 res12[4]; u32 rstrqsr1; /* Reset request status */ u8 res13[4]; @@ -1813,8 +1751,11 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 +/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1830,11 +1771,48 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 +#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 +#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 +#define PXCKEN_MASK 0x80000000 +#define PXCK_MASK 0x00FF0000 +#define PXCK_BITS_START 16 +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \ + defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 +#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ +#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC2 0x0c000000 +#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000 +#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 +#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00 +#define PXCKEN_MASK 0x80000000 +#define PXCK_MASK 0x00FF0000 +#define PXCK_BITS_START 16 +#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 @@ -1844,6 +1822,9 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 @@ -1889,7 +1870,8 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 @@ -1897,6 +1879,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 +#endif +#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ +#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 +#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ +#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000 #endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ @@ -1929,7 +1920,10 @@ typedef struct ccsr_gur { u32 sata2liodnr; /* SATA 2 LIODN */ u32 sata3liodnr; /* SATA 3 LIODN */ u32 sata4liodnr; /* SATA 4 LIODN */ - u8 res22[32]; + u8 res22[20]; + u32 tdmliodnr; /* TDM LIODN */ + u32 qeliodnr; /* QE LIODN */ + u8 res_57c[4]; u32 dma1liodnr; /* DMA 1 LIODN */ u32 dma2liodnr; /* DMA 2 LIODN */ u32 dma3liodnr; /* DMA 3 LIODN */ @@ -1938,6 +1932,7 @@ typedef struct ccsr_gur { u8 res24[64]; u32 pblsr; /* Preboot loader status */ u32 pamubypenr; /* PAMU bypass enable */ +#define FSL_CORENET_PAMU_BYPASS 0xffff0000 u32 dmacr1; /* DMA control */ u8 res25[4]; u32 gensr1; /* General status */ @@ -2000,20 +1995,13 @@ typedef struct ccsr_clk { u8 res_004[0x0c]; u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ u8 res_014[0x0c]; - } clkcsr[8]; - u8 res_100[0x700]; /* 0x100 */ - u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */ - u8 res10[0x1c]; - u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */ - u8 res11[0x1c]; - u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */ - u8 res12[0x1c]; - u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */ - u8 res13[0x1c]; - u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */ - u8 res14[0x1c]; - u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */ - u8 res15[0x35c]; + } clkcsr[12]; + u8 res_100[0x680]; /* 0x100 */ + struct { + u32 pllcngsr; + u8 res10[0x1c]; + } pllcgsr[12]; + u8 res21[0x280]; u32 pllpgsr; /* 0xc00 Platform PLL General Status */ u8 res16[0x1c]; u32 plldgsr; /* 0xc20 DDR PLL General Status */ @@ -2131,6 +2119,11 @@ typedef struct ccsr_gur { #ifdef CONFIG_MPC8536 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#elif defined(CONFIG_PPC_C29X) +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ + & MPC85xx_PORDEVSR2_DDR_SPD_0) \ + >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) #else #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 @@ -2178,6 +2171,9 @@ typedef struct ccsr_gur { #elif defined(CONFIG_BSC9132) #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 +#elif defined(CONFIG_PPC_C29X) +#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 @@ -2193,6 +2189,10 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 u32 pordbgmsr; /* POR debug mode status */ u32 pordevsr2; /* POR I/O device status 2 */ +#if defined(CONFIG_PPC_C29X) +#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 +#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 +#endif /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 u8 res1[8]; @@ -2338,6 +2338,11 @@ typedef struct ccsr_gur { #ifdef CONFIG_BSC9132 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 +#endif +#if defined(CONFIG_PPC_C29X) +#define MPC85xx_PMUXCR_SPI_MASK 0x00000300 +#define MPC85xx_PMUXCR_SPI 0x00000000 +#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 #endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_P1010) || defined(CONFIG_P1014) @@ -2526,7 +2531,10 @@ typedef struct serdes_corenet { #define SRDS_RSTCTL_RSTDONE 0x40000000 #define SRDS_RSTCTL_RSTERR 0x20000000 #define SRDS_RSTCTL_SWRST 0x10000000 -#define SRDS_RSTCTL_SDPD 0x00000020 +#define SRDS_RSTCTL_SDEN 0x00000020 +#define SRDS_RSTCTL_SDRST_B 0x00000040 +#define SRDS_RSTCTL_PLLRST_B 0x00000080 +#define SRDS_RSTCTL_RSTERR_SHIFT 29 u32 pllcr0; /* PLL Control Register 0 */ #define SRDS_PLLCR0_POFF 0x80000000 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 @@ -2536,16 +2544,33 @@ typedef struct serdes_corenet { #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_PLL_LCK 0x00800000 +#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 -#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 -#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 +#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000 +#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000 +#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000 +#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0 +#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4 u32 pllcr1; /* PLL Control Register 1 */ -#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 - u32 res_0c; /* 0x00c */ +#define SRDS_PLLCR1_BCAP_EN 0x20000000 +#define SRDS_PLLCR1_BCAP_OVD 0x10000000 +#define SRDS_PLLCR1_PLL_FCAP 0x001F8000 +#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15 +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 +#define SRDS_PLLCR1_BYP_CAL 0x02000000 + u32 pllsr2; /* At 0x00c, PLL Status Register 2 */ +#define SRDS_PLLSR2_BCAP_EN 0x00800000 +#define SRDS_PLLSR2_BCAP_EN_SHIFT 23 +#define SRDS_PLLSR2_FCAP 0x003F0000 +#define SRDS_PLLSR2_FCAP_SHIFT 16 +#define SRDS_PLLSR2_DCBIAS 0x000F0000 +#define SRDS_PLLSR2_DCBIAS_SHIFT 16 u32 pllcr3; u32 pllcr4; u8 res_18[0x20-0x18]; @@ -2672,72 +2697,6 @@ enum { FSL_SRDS_B3_LANE_D = 23, }; -/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ -#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 -typedef struct ccsr_sec { - u32 res0; - u32 mcfgr; /* Master CFG Register */ - u8 res1[0x8]; - struct { - u32 ms; /* Job Ring LIODN Register, MS */ - u32 ls; /* Job Ring LIODN Register, LS */ - } jrliodnr[4]; - u8 res2[0x30]; - struct { - u32 ms; /* RTIC LIODN Register, MS */ - u32 ls; /* RTIC LIODN Register, LS */ - } rticliodnr[4]; - u8 res3[0x1c]; - u32 decorr; /* DECO Request Register */ - struct { - u32 ms; /* DECO LIODN Register, MS */ - u32 ls; /* DECO LIODN Register, LS */ - } decoliodnr[8]; - u8 res4[0x40]; - u32 dar; /* DECO Avail Register */ - u32 drr; /* DECO Reset Register */ - u8 res5[0xe78]; - u32 crnr_ms; /* CHA Revision Number Register, MS */ - u32 crnr_ls; /* CHA Revision Number Register, LS */ - u32 ctpr_ms; /* Compile Time Parameters Register, MS */ - u32 ctpr_ls; /* Compile Time Parameters Register, LS */ - u8 res6[0x10]; - u32 far_ms; /* Fault Address Register, MS */ - u32 far_ls; /* Fault Address Register, LS */ - u32 falr; /* Fault Address LIODN Register */ - u32 fadr; /* Fault Address Detail Register */ - u8 res7[0x4]; - u32 csta; /* CAAM Status Register */ - u8 res8[0x8]; - u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ - u32 ccbvid; /* CHA Cluster Block Version ID Register */ - u32 chavid_ms; /* CHA Version ID Register, MS */ - u32 chavid_ls; /* CHA Version ID Register, LS */ - u32 chanum_ms; /* CHA Number Register, MS */ - u32 chanum_ls; /* CHA Number Register, LS */ - u32 secvid_ms; /* SEC Version ID Register, MS */ - u32 secvid_ls; /* SEC Version ID Register, LS */ - u8 res9[0x6020]; - u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ - u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ - u8 res10[0x8fd8]; -} ccsr_sec_t; - -#define SEC_CTPR_MS_AXI_LIODN 0x08000000 -#define SEC_CTPR_MS_QI 0x02000000 -#define SEC_RVID_MA 0x0f000000 -#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 -#define SEC_CHANUM_MS_JRNUM_SHIFT 28 -#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 -#define SEC_CHANUM_MS_DECONUM_SHIFT 24 -#define SEC_SECVID_MS_IPID_MASK 0xffff0000 -#define SEC_SECVID_MS_IPID_SHIFT 16 -#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 -#define SEC_SECVID_MS_MAJ_REV_SHIFT 8 -#define SEC_CCBVID_ERA_MASK 0xff000000 -#define SEC_CCBVID_ERA_SHIFT 24 -#endif - typedef struct ccsr_qman { #ifdef CONFIG_SYS_FSL_QMAN_V3 u8 res0[0x200]; @@ -2811,54 +2770,6 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; -#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE -struct ccsr_usb_port_ctrl { - u32 ctrl; - u32 drvvbuscfg; - u32 pwrfltcfg; - u32 sts; - u8 res_14[0xc]; - u32 bistcfg; - u32 biststs; - u32 abistcfg; - u32 abiststs; - u8 res_30[0x10]; - u32 xcvrprg; - u32 anaprg; - u32 anadrv; - u32 anasts; -}; - -typedef struct ccsr_usb_phy { - u32 id; - struct ccsr_usb_port_ctrl port1; - u8 res_50[0xc]; - u32 tvr; - u32 pllprg[4]; - u8 res_70[0x4]; - u32 anaccfg; - u32 dbg; - u8 res_7c[0x4]; - struct ccsr_usb_port_ctrl port2; - u8 res_dc[0x334]; -} ccsr_usb_phy_t; - -#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) -#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) -#else -typedef struct ccsr_usb_phy { - u8 res0[0x18]; - u32 usb_enable_override; - u8 res[0xe4]; -} ccsr_usb_phy_t; -#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 -#endif - #ifdef CONFIG_SYS_FSL_RAID_ENGINE struct ccsr_raide { u8 res0[0x543]; @@ -2912,6 +2823,21 @@ struct ccsr_pman { u8 res_f4[0xf0c]; }; #endif +#ifdef CONFIG_SYS_FSL_SFP_VER_3_0 +struct ccsr_sfp_regs { + u32 ospr; /* 0x200 */ + u32 reserved0[14]; + u32 srk_hash[8]; /* 0x23c Super Root Key Hash */ + u32 oem_uid; /* 0x9c OEM Unique ID */ + u8 reserved2[0x04]; + u32 ovpr; /* 0xA4 Intent To Secure */ + u8 reserved4[0x08]; + u32 fsl_uid; /* 0xB0 FSL Unique ID */ + u8 reserved5[0x04]; + u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */ + u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */ +}; +#endif #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 @@ -2925,17 +2851,31 @@ struct ccsr_pman { #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#ifdef CONFIG_SYS_FSL_SFP_VER_3_0 +/* In SFPv3, OSPR register is now at offset 0x200. + * * So directly mapping sfp register map to this address */ +#define CONFIG_SYS_OSPR_OFFSET 0x200 +#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) +#else +#define CONFIG_SYS_SFP_OFFSET 0xE8000 +#endif #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 +#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 +#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 +#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 +#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000 +#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ && !defined(CONFIG_PPC_B4420) @@ -2951,12 +2891,12 @@ struct ccsr_pman { #endif #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 -#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 +#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 @@ -3004,16 +2944,24 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 -#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 #ifdef CONFIG_TSECV2 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#elif defined(CONFIG_TSECV2_1) +#define CONFIG_SYS_TSEC1_OFFSET 0x10000 #else #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #endif #define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 +#if defined(CONFIG_PPC_C29X) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 +#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 +#else #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 +#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000 +#endif #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_SNVS_OFFSET 0xE6000 @@ -3031,8 +2979,20 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 +#if defined(CONFIG_BSC9132) +#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 +#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ + (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) +#endif + #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) +#define CONFIG_SYS_FSL_SCFG_ADDR \ + (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) +#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ + (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) +#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \ + (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) #define CONFIG_SYS_FSL_BMAN_ADDR \ @@ -3053,11 +3013,11 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) #define CONFIG_SYS_MPC85xx_ECM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR_ADDR \ +#define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \ +#define CONFIG_SYS_FSL_DDR2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \ +#define CONFIG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) @@ -3093,14 +3053,22 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET) +#define CONFIG_SYS_MPC85xx_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) +#define CONFIG_SYS_MPC85xx_USB2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET) #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) #define CONFIG_SYS_FSL_FM1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ @@ -3123,6 +3091,9 @@ struct ccsr_pman { #define CONFIG_SYS_PCIE4_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) +#define CONFIG_SYS_SFP_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) + #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) @@ -3193,4 +3164,26 @@ struct dcsr_dcfg_regs { #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ }; + +#define CONFIG_SYS_MPC85xx_SCFG \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET) +#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 +/* The supplement configuration unit register */ +struct ccsr_scfg { + u32 dpslpcr; /* 0x000 Deep Sleep Control register */ + u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */ + u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */ + u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */ + u32 res1[4]; + u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */ + u32 res2; + u32 pixclkcr; /* 0x028 Pixel Clock Control register */ + u32 res3[245]; + u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */ + u32 emiiocr; /* 0x404 EMI MDIO Control Register */ + u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */ + u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */ + u32 res4[60]; + u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ +}; #endif /*__IMMAP_85xx__*/ diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 2a704fe6b7..177918b7f9 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -10,6 +10,7 @@ #ifndef __IMMAP_86xx__ #define __IMMAP_86xx__ +#include #include #include #include @@ -89,75 +90,6 @@ typedef struct ccsr_local_mcm { char res31[488]; } ccsr_local_mcm_t; -/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ - -typedef struct ccsr_ddr { - uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ - char res1[4]; - uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ - char res2[4]; - uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ - char res3[4]; - uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ - char res4[4]; - uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ - char res5[4]; - uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ - char res6[84]; - uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ - uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ - uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ - uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ - uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ - char res7[104]; - uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ - uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ - uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ - uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ - uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ - uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ - uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ - uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ - char res8[4]; - uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res9[12]; - uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ - uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ - uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */ - char res10[2728]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ - char res11[512]; - uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ - uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ - uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ - char res12[20]; - uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ - uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ - uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ - char res13[20]; - uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ - uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ - uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ - uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ - uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ - uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ - char res14[164]; - uint debug_1; /* 0x2f00 */ - uint debug_2; - uint debug_3; - uint debug_4; - uint debug_5; - char res15[236]; -} ccsr_ddr_t; - - /* Daul I2C Registers(0x3000-0x4000) */ typedef struct ccsr_i2c { struct fsl_i2c i2c[2]; @@ -1225,11 +1157,11 @@ typedef struct ccsr_wdt { typedef struct immap { ccsr_local_mcm_t im_local_mcm; - ccsr_ddr_t im_ddr1; + struct ccsr_ddr im_ddr1; ccsr_i2c_t im_i2c; ccsr_duart_t im_duart; fsl_lbc_t im_lbc; - ccsr_ddr_t im_ddr2; + struct ccsr_ddr im_ddr2; char res1[4096]; ccsr_pex_t im_pex1; ccsr_pex_t im_pex2; @@ -1253,9 +1185,9 @@ typedef struct immap { extern immap_t *immr; #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 -#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 -#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) #define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) #define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000 diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 1f12c29ba8..a5257e9b62 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -7,7 +7,6 @@ #ifndef _PPC_IO_H #define _PPC_IO_H -#include #include #ifdef CONFIG_ADDR_MAP @@ -124,6 +123,9 @@ static inline void isync(void) #define iobarrier_r() eieio() #define iobarrier_w() eieio() +#define mb() sync() +#define isb() isync() + /* * Non ordered and non-swapping "raw" accessors */ diff --git a/arch/powerpc/include/asm/iopin_85xx.h b/arch/powerpc/include/asm/iopin_85xx.h deleted file mode 100644 index 0f07ba355e..0000000000 --- a/arch/powerpc/include/asm/iopin_85xx.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * MPC85xx I/O port pin manipulation functions - */ - -#ifndef _ASM_IOPIN_85xx_H_ -#define _ASM_IOPIN_85xx_H_ - -#include -#include - -#ifdef __KERNEL__ - -typedef struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ -} iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -extern __inline__ void iopin_set_high (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_low (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_high (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_low (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_out (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_in (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_out (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_in (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_odr (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_act (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_odr (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_act (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_ded (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_gen (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_ded (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_gen (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_opt2 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_opt1 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_85xx_H_ */ diff --git a/arch/powerpc/include/asm/m8260_pci.h b/arch/powerpc/include/asm/m8260_pci.h index 45f01de820..6daca4f99b 100644 --- a/arch/powerpc/include/asm/m8260_pci.h +++ b/arch/powerpc/include/asm/m8260_pci.h @@ -1,4 +1,3 @@ - #ifndef _PPC_KERNEL_M8260_PCI_H #define _PPC_KERNEL_M8260_PCI_H diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index b700a3a0be..5aa916f2e2 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -5,8 +5,6 @@ #ifndef _PPC_MMU_H_ #define _PPC_MMU_H_ -#include - #ifndef __ASSEMBLY__ /* Hardware Page Table Entry */ typedef struct _PTE { @@ -511,6 +509,14 @@ extern void print_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); extern void clear_ddr_tlbs(unsigned int memsize_in_meg); +enum tlb_map_type { + TLB_MAP_RAM, + TLB_MAP_IO, +}; + +extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, + enum tlb_map_type map_type); + extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h index 3d1188467c..87bb4a092b 100644 --- a/arch/powerpc/include/asm/mpc85xx_gpio.h +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -20,7 +20,7 @@ static inline void mpc85xx_gpio_set(unsigned int mask, unsigned int dir, unsigned int val) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); /* First mask off the unwanted parts of "dir" and "val" */ dir &= mask; @@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios) static inline unsigned int mpc85xx_gpio_get(unsigned int mask) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); /* Read the requested values */ return in_be32(&gpio->gpdat) & mask; diff --git a/arch/powerpc/include/asm/pnp.h b/arch/powerpc/include/asm/pnp.h deleted file mode 100644 index 22ceba2253..0000000000 --- a/arch/powerpc/include/asm/pnp.h +++ /dev/null @@ -1,643 +0,0 @@ -/* 11/02/95 */ -/*----------------------------------------------------------------------------*/ -/* Plug and Play header definitions */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for PnP on PowerPC Reference Platform */ -/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ -/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ -/* This code has extensions to that specification, namely new short and */ -/* long tag types for platform dependent information */ - -/* Warning: LE notation used throughout this file */ - -/* For enum's: if given in hex then they are bit significant, i.e. */ -/* only one bit is on for each enum */ - -#ifndef _PNP_ -#define _PNP_ - -#ifndef __ASSEMBLY__ -#define MAX_MEM_REGISTERS 9 -#define MAX_IO_PORTS 20 -#define MAX_IRQS 7 -/*#define MAX_DMA_CHANNELS 7*/ - -/* Interrupt controllers */ - -#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ -#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ -#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ -#define PNPinterrupt3 "PNP0003" /* APIC */ -#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ - -/* Timers */ - -#define PNPtimer0 "PNP0100" /* AT Timer */ -#define PNPtimer1 "PNP0101" /* EISA Timer */ -#define PNPtimer2 "PNP0102" /* MCA Timer */ - -/* DMA controllers */ - -#define PNPdma0 "PNP0200" /* AT DMA Controller */ -#define PNPdma1 "PNP0201" /* EISA DMA Controller */ -#define PNPdma2 "PNP0202" /* MCA DMA Controller */ - -/* start of August 15, 1994 additions */ -/* CMOS */ -#define PNPCMOS "IBM0009" /* CMOS */ - -/* L2 Cache */ -#define PNPL2 "IBM0007" /* L2 Cache */ - -/* NVRAM */ -#define PNPNVRAM "IBM0008" /* NVRAM */ - -/* Power Management */ -#define PNPPM "IBM0005" /* Power Management */ -/* end of August 15, 1994 additions */ - -/* Keyboards */ - -#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ -#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ -#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ -#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ -#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ -#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ -#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ -#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ - -/* Parallel port controllers */ - -#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ -#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ -#define PNPepp "IBM001C" /* EPP Parallel Port */ - -/* Serial port controllers */ - -#define PNPserial0 "PNP0500" /* Standard PC Serial port */ -#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ - -/* Disk controllers */ - -#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ -#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ -#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ - -/* Diskette controllers */ - -#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ - -/* Display controllers */ - -#define PNPdisplay0 "PNP0900" /* VGA Compatible */ -#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ -#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ -#define PNPdisplay3 "PNP0903" /* Trident VGA */ -#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ -#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ -#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ -#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ -#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ -#define PNPdisplay9 "PNP0909" /* S3 */ -#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ -#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ -#define PNPdisplayC "PNP090C" /* XGA Compatible */ -#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ -#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ -#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ - -/* Peripheral busses */ - -#define PNPbuses0 "PNP0A00" /* ISA Bus */ -#define PNPbuses1 "PNP0A01" /* EISA Bus */ -#define PNPbuses2 "PNP0A02" /* MCA Bus */ -#define PNPbuses3 "PNP0A03" /* PCI Bus */ -#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ - -/* RTC, BIOS, planar devices */ - -#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ -#define PNPrtc0 "PNP0B00" /* AT RTC */ -#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ -#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ -#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ -#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ - -/* PCMCIA controller */ - -#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ - -/* Mice */ - -#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ -#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ -#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ -#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ -#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ -#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ -#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ -#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ -#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ -#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ -#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ -#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ - -/* Modems */ - -#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ - -/* Network controllers */ - -#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ -#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ -#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ -#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ -#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ -#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ -#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ -#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ - -/* SCSI controllers */ - -#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ -#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ -#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ -#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ -#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ -#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ -#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ - -/* Sound/Video, Multimedia */ - -#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ -#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ -#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ -#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ -#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ -#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ -#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ -#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ - -/* Operator Panel */ -#define PNPopctl "IBM000B" /* Operator's panel */ - -/* Service Processor */ -#define PNPsp "IBM0011" /* IBM Service Processor */ -#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ -#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ - -/* Memory Controller */ -#define PNPmemctl "IBM000A" /* Memory controller */ - -/* Graphics Assist */ -#define PNPg_assist "IBM0014" /* Graphics Assist */ - -/* Miscellaneous Device Controllers */ -#define PNPtablet "IBM0019" /* IBM Tablet Controller */ - -/* PNP Packet Handles */ - -#define S1_Packet 0x0A /* Version resource */ -#define S2_Packet 0x15 /* Logical DEVID (without flags) */ -#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ -#define S3_Packet 0x1C /* Compatible device ID */ -#define S4_Packet 0x22 /* IRQ resource (without flags) */ -#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ -#define S5_Packet 0x2A /* DMA resource */ -#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ -#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ -#define S7_Packet 0x38 /* Depend funct end */ -#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ -#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ -#define S14_Packet 0x71 /* Vendor defined */ -#define S15_Packet 0x78 /* End of resource (w/o checksum) */ -#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ -#define L1_Packet 0x81 /* Memory range */ -#define L1_Shadow 0x20 /* Memory is shadowable */ -#define L1_32bit_mem 0x18 /* 32-bit memory only */ -#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ -#define L1_Decode_Hi 0x04 /* decode supports high address */ -#define L1_Cache 0x02 /* read cacheable, write-through */ -#define L1_Writeable 0x01 /* Memory is writeable */ -#define L2_Packet 0x82 /* ANSI ID string */ -#define L3_Packet 0x83 /* Unicode ID string */ -#define L4_Packet 0x84 /* Vendor defined */ -#define L5_Packet 0x85 /* Large I/O */ -#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ -#define END_TAG 0x78 /* End of resource */ -#define DF_START_TAG 0x30 /* Dependent function start */ -#define DF_START_TAG_priority 0x31 /* Dependent function start */ -#define DF_END_TAG 0x38 /* Dependent function end */ -#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ - -/* Device Base Type Codes */ - -typedef enum _PnP_BASE_TYPE { - Reserved = 0, - MassStorageDevice = 1, - NetworkInterfaceController = 2, - DisplayController = 3, - MultimediaController = 4, - MemoryController = 5, - BridgeController = 6, - CommunicationsDevice = 7, - SystemPeripheral = 8, - InputDevice = 9, - ServiceProcessor = 0x0A, /* 11/2/95 */ - } PnP_BASE_TYPE; - -/* Device Sub Type Codes */ - -typedef enum _PnP_SUB_TYPE { - SCSIController = 0, - IDEController = 1, - FloppyController = 2, - IPIController = 3, - OtherMassStorageController = 0x80, - - EthernetController = 0, - TokenRingController = 1, - FDDIController = 2, - OtherNetworkController = 0x80, - - VGAController= 0, - SVGAController= 1, - XGAController= 2, - OtherDisplayController = 0x80, - - VideoController = 0, - AudioController = 1, - OtherMultimediaController = 0x80, - - RAM = 0, - FLASH = 1, - OtherMemoryDevice = 0x80, - - HostProcessorBridge = 0, - ISABridge = 1, - EISABridge = 2, - MicroChannelBridge = 3, - PCIBridge = 4, - PCMCIABridge = 5, - VMEBridge = 6, - OtherBridgeDevice = 0x80, - - RS232Device = 0, - ATCompatibleParallelPort = 1, - OtherCommunicationsDevice = 0x80, - - ProgrammableInterruptController = 0, - DMAController = 1, - SystemTimer = 2, - RealTimeClock = 3, - L2Cache = 4, - NVRAM = 5, - PowerManagement = 6, - CMOS = 7, - OperatorPanel = 8, - ServiceProcessorClass1 = 9, - ServiceProcessorClass2 = 0xA, - ServiceProcessorClass3 = 0xB, - GraphicAssist = 0xC, - SystemPlanar = 0xF, /* 10/5/95 */ - OtherSystemPeripheral = 0x80, - - KeyboardController = 0, - Digitizer = 1, - MouseController = 2, - TabletController = 3, /* 10/27/95 */ - OtherInputController = 0x80, - - GeneralMemoryController = 0, - } PnP_SUB_TYPE; - -/* Device Interface Type Codes */ - -typedef enum _PnP_INTERFACE { - General = 0, - GeneralSCSI = 0, - GeneralIDE = 0, - ATACompatible = 1, - - GeneralFloppy = 0, - Compatible765 = 1, - NS398_Floppy = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26E_Floppy = 3, /* Ports 26E and 26F */ - NS15C_Floppy = 4, /* Ports 15C and 15D */ - NS2E_Floppy = 5, /* Ports 2E and 2F */ - CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ - - GeneralIPI = 0, - - GeneralEther = 0, - GeneralToken = 0, - GeneralFDDI = 0, - - GeneralVGA = 0, - GeneralSVGA = 0, - GeneralXGA = 0, - - GeneralVideo = 0, - GeneralAudio = 0, - CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ - - GeneralRAM = 0, - GeneralFLASH = 0, - PCIMemoryController = 0, /* PCI Config Method */ - RS6KMemoryController = 1, /* RS6K Config Method */ - - GeneralHostBridge = 0, - GeneralISABridge = 0, - GeneralEISABridge = 0, - GeneralMCABridge = 0, - GeneralPCIBridge = 0, - PCIBridgeDirect = 0, - PCIBridgeIndirect = 1, - PCIBridgeRS6K = 2, - GeneralPCMCIABridge = 0, - GeneralVMEBridge = 0, - - GeneralRS232 = 0, - COMx = 1, - Compatible16450 = 2, - Compatible16550 = 3, - NS398SerPort = 4, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26ESerPort = 5, /* Ports 26E and 26F */ - NS15CSerPort = 6, /* Ports 15C and 15D */ - NS2ESerPort = 7, /* Ports 2E and 2F */ - - GeneralParPort = 0, - LPTx = 1, - NS398ParPort = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26EParPort = 3, /* Ports 26E and 26F */ - NS15CParPort = 4, /* Ports 15C and 15D */ - NS2EParPort = 5, /* Ports 2E and 2F */ - - GeneralPIC = 0, - ISA_PIC = 1, - EISA_PIC = 2, - MPIC = 3, - RS6K_PIC = 4, - - GeneralDMA = 0, - ISA_DMA = 1, - EISA_DMA = 2, - - GeneralTimer = 0, - ISA_Timer = 1, - EISA_Timer = 2, - GeneralRTC = 0, - ISA_RTC = 1, - - StoreThruOnly = 1, - StoreInEnabled = 2, - RS6KL2Cache = 3, - - IndirectNVRAM = 0, /* Indirectly addressed */ - DirectNVRAM = 1, /* Memory Mapped */ - IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ - - GeneralPowerManagement = 0, - EPOWPowerManagement = 1, - PowerControl = 2, /* d1378 */ - - GeneralCMOS = 0, - - GeneralOPPanel = 0, - HarddiskLight = 1, - CDROMLight = 2, - PowerLight = 3, - KeyLock = 4, - ANDisplay = 5, /* AlphaNumeric Display */ - SystemStatusLED = 6, /* 3 digit 7 segment LED */ - CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ - - GeneralServiceProcessor = 0, - - TransferData = 1, - IGMC32 = 2, - IGMC64 = 3, - - GeneralSystemPlanar = 0, /* 10/5/95 */ - - } PnP_INTERFACE; - -/* PnP resources */ - -/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ - -typedef struct _SERIAL_ID { - unsigned char VendorID0; /* Bit(7)=0 */ - /* Bits(6:2)=1st character in */ - /* compressed ASCII */ - /* Bits(1:0)=2nd character in */ - /* compressed ASCII bits(4:3) */ - unsigned char VendorID1; /* Bits(7:5)=2nd character in */ - /* compressed ASCII bits(2:0) */ - /* Bits(4:0)=3rd character in */ - /* compressed ASCII */ - unsigned char VendorID2; /* Product number - vendor assigned */ - unsigned char VendorID3; /* Product number - vendor assigned */ - -/* Serial number is to provide uniqueness if more than one board of same */ -/* type is in system. Must be "FFFFFFFF" if feature not supported. */ - - unsigned char Serial0; /* Unique serial number bits (7:0) */ - unsigned char Serial1; /* Unique serial number bits (15:8) */ - unsigned char Serial2; /* Unique serial number bits (23:16) */ - unsigned char Serial3; /* Unique serial number bits (31:24) */ - unsigned char Checksum; - } SERIAL_ID; - -typedef enum _PnPItemName { - Unused = 0, - PnPVersion = 1, - LogicalDevice = 2, - CompatibleDevice = 3, - IRQFormat = 4, - DMAFormat = 5, - StartDepFunc = 6, - EndDepFunc = 7, - IOPort = 8, - FixedIOPort = 9, - Res1 = 10, - Res2 = 11, - Res3 = 12, - SmallVendorItem = 14, - EndTag = 15, - MemoryRange = 1, - ANSIIdentifier = 2, - UnicodeIdentifier = 3, - LargeVendorItem = 4, - MemoryRange32 = 5, - MemoryRangeFixed32 = 6, - } PnPItemName; - -/* Define a bunch of access functions for the bits in the tag field */ - -/* Tag type - 0 = small; 1 = large */ -#define tag_type(t) (((t) & 0x80)>>7) -#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) - -/* Small item name is 4 bits - one of PnPItemName enum above */ -#define tag_small_item_name(t) (((t) & 0x78)>>3) -#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) - -/* Small item count is 3 bits - count of further bytes in packet */ -#define tag_small_count(t) ((t) & 0x07) -#define set_tag_count(t,v) (t = (t & 0x78) | (v)) - -/* Large item name is 7 bits - one of PnPItemName enum above */ -#define tag_large_item_name(t) ((t) & 0x7f) -#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) - -/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ - -typedef union _PnP_TAG_PACKET { - struct _S1_Pack{ /* VERSION PACKET */ - unsigned char Tag; /* small tag = 0x0a */ - unsigned char Version[2]; /* PnP version, Vendor version */ - } S1_Pack; - - struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x15 or 0x16 */ - unsigned char DevId[4]; /* Logical device id */ - unsigned char Flags[2]; /* bit(0) boot device; */ - /* bit(7:1) cmd in range x31-x37 */ - /* bit(7:0) cmd in range x28-x3f (opt)*/ - } S2_Pack; - - struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x1c */ - unsigned char CompatId[4]; /* Compatible device id */ - } S3_Pack; - - struct _S4_Pack{ /* IRQ PACKET */ - unsigned char Tag; /* small tag = 0x22 or 0x23 */ - unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ - /* bit(0) is IRQ8 ... */ - unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ - /* bit(0) - high true edge sensitive */ - /* bit(1) - low true edge sensitive */ - /* bit(2) - high true level sensitive*/ - /* bit(3) - low true level sensitive */ - /* bit(7:4) - must be 0 */ - } S4_Pack; - - struct _S5_Pack{ /* DMA PACKET */ - unsigned char Tag; /* small tag = 0x2a */ - unsigned char DMAMask; /* bit(0) is channel 0 ... */ - unsigned char DMAInfo; - } S5_Pack; - - struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x30 or 0x31 */ - unsigned char Priority; /* Optional; if missing then x01; else*/ - /* x00 = best possible */ - /* x01 = acceptible */ - /* x02 = sub-optimal but functional */ - } S6_Pack; - - struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x38 */ - } S7_Pack; - - struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ - unsigned char Tag; /* small tag x47 */ - unsigned char IOInfo; /* x0 = decode only bits(9:0); */ -#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ - unsigned char RangeMin[2]; /* Min base address */ - unsigned char RangeMax[2]; /* Max base address */ - unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S8_Pack; - - struct _S9_Pack{ /* FIXED I/O PORT PACKET */ - unsigned char Tag; /* small tag = 0x4b */ - unsigned char Range[2]; /* base address 10 bits */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S9_Pack; - - struct _S14_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* small tag = 0x7m m = 1-7 */ - union _S14_Data{ - unsigned char Data[7]; /* Vendor defined */ - struct _S14_PPCPack{ /* Pr*p s14 pack */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[6]; /* Vendor defined */ - } S14_PPCPack; - } S14_Data; - } S14_Pack; - - struct _S15_Pack{ /* END PACKET */ - unsigned char Tag; /* small tag = 0x78 or 0x79 */ - unsigned char Check; /* optional - checksum */ - } S15_Pack; - - struct _L1_Pack{ /* MEMORY RANGE PACKET */ - unsigned char Tag; /* large tag = 0x81 */ - unsigned char Count0; /* x09 */ - unsigned char Count1; /* x00 */ - unsigned char Data[9]; /* a variable array of bytes, */ - /* count in tag */ - } L1_Pack; - - struct _L2_Pack{ /* ANSI ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x82 */ - unsigned char Count0; /* Length of string */ - unsigned char Count1; - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L2_Pack; - - struct _L3_Pack{ /* UNICODE ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x83 */ - unsigned char Count0; /* Length + 2 of string */ - unsigned char Count1; - unsigned char Country0; /* TBD */ - unsigned char Country1; /* TBD */ - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L3_Pack; - - struct _L4_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* large tag = 0x84 */ - unsigned char Count0; - unsigned char Count1; - union _L4_Data{ - unsigned char Data[1]; /* a variable array of bytes, */ - /* count in tag */ - struct _L4_PPCPack{ /* Pr*p L4 packet */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[1]; /* a variable array of bytes, */ - /* count in tag */ - } L4_PPCPack; - } L4_Data; - } L4_Pack; - - struct _L5_Pack{ - unsigned char Tag; /* large tag = 0x85 */ - unsigned char Count0; /* Count = 17 */ - unsigned char Count1; - unsigned char Data[17]; - } L5_Pack; - - struct _L6_Pack{ - unsigned char Tag; /* large tag = 0x86 */ - unsigned char Count0; /* Count = 9 */ - unsigned char Count1; - unsigned char Data[9]; - } L6_Pack; - - } PnP_TAG_PACKET; - -#endif /* __ASSEMBLY__ */ -#endif /* ndef _PNP_ */ diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h index 892848aacf..f2ed16a216 100644 --- a/arch/powerpc/include/asm/ppc405.h +++ b/arch/powerpc/include/asm/ppc405.h @@ -1,25 +1,6 @@ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of the -| GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ #ifndef __PPC405_H__ #define __PPC405_H__ diff --git a/arch/powerpc/include/asm/ppc405cr.h b/arch/powerpc/include/asm/ppc405cr.h deleted file mode 100644 index 0ea69bd096..0000000000 --- a/arch/powerpc/include/asm/ppc405cr.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PPC405CR_H_ -#define _PPC405CR_H_ - -#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ - -/* Memory mapped register */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) - -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) - -/* DCR's */ -#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */ -#define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */ -#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */ -#define OCM0_DSARC 0x001a /* OCM D-side address compare */ -#define OCM0_DSCNTL 0x001b /* OCM D-side control */ -#define CPC0_PLLMR 0x00b0 /* PLL mode register */ -#define CPC0_CR0 0x00b1 /* chip control register 0 */ -#define CPC0_CR1 0x00b2 /* chip control register 1 */ -#define CPC0_PSR 0x00b4 /* chip pin strapping reg */ -#define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */ -#define CPC0_SR 0x00b8 /* Power management status */ -#define CPC0_ER 0x00b9 /* Power management enable */ -#define CPC0_FR 0x00ba /* Power management force */ -#define CPC0_ECR 0x00aa /* edge conditioner register */ - -#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ -#define PLLMR_FWD_DIV_BYPASS 0xE0000000 -#define PLLMR_FWD_DIV_3 0xA0000000 -#define PLLMR_FWD_DIV_4 0x80000000 -#define PLLMR_FWD_DIV_6 0x40000000 - -#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ -#define PLLMR_FB_DIV_1 0x02000000 -#define PLLMR_FB_DIV_2 0x04000000 -#define PLLMR_FB_DIV_3 0x06000000 -#define PLLMR_FB_DIV_4 0x08000000 - -#define PLLMR_TUNING_MASK 0x01F80000 - -#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ -#define PLLMR_CPU_PLB_DIV_1 0x00000000 -#define PLLMR_CPU_PLB_DIV_2 0x00020000 -#define PLLMR_CPU_PLB_DIV_3 0x00040000 -#define PLLMR_CPU_PLB_DIV_4 0x00060000 - -#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ -#define PLLMR_OPB_PLB_DIV_1 0x00000000 -#define PLLMR_OPB_PLB_DIV_2 0x00008000 -#define PLLMR_OPB_PLB_DIV_3 0x00010000 -#define PLLMR_OPB_PLB_DIV_4 0x00018000 - -#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ -#define PLLMR_PCI_PLB_DIV_1 0x00000000 -#define PLLMR_PCI_PLB_DIV_2 0x00002000 -#define PLLMR_PCI_PLB_DIV_3 0x00004000 -#define PLLMR_PCI_PLB_DIV_4 0x00006000 - -#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ -#define PLLMR_EXB_PLB_DIV_2 0x00000000 -#define PLLMR_EXB_PLB_DIV_3 0x00000800 -#define PLLMR_EXB_PLB_DIV_4 0x00001000 -#define PLLMR_EXB_PLB_DIV_5 0x00001800 - -/* definitions for PPC405GPr (new mode strapping) */ -#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ - -#define PSR_PLL_FWD_MASK 0xC0000000 -#define PSR_PLL_FDBACK_MASK 0x30000000 -#define PSR_PLL_TUNING_MASK 0x0E000000 -#define PSR_PLB_CPU_MASK 0x01800000 -#define PSR_OPB_PLB_MASK 0x00600000 -#define PSR_PCI_PLB_MASK 0x00180000 -#define PSR_EB_PLB_MASK 0x00060000 -#define PSR_ROM_WIDTH_MASK 0x00018000 -#define PSR_ROM_LOC 0x00004000 -#define PSR_PCI_ASYNC_EN 0x00001000 -#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ -#define PSR_PCI_ARBIT_EN 0x00000400 -#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ - -#endif /* _PPC405CR_H_ */ diff --git a/arch/powerpc/include/asm/ppc405ep.h b/arch/powerpc/include/asm/ppc405ep.h index ae3c99c5be..9f04215661 100644 --- a/arch/powerpc/include/asm/ppc405ep.h +++ b/arch/powerpc/include/asm/ppc405ep.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC405EP_H_ diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h index 179ef149d7..083405ccb6 100644 --- a/arch/powerpc/include/asm/ppc405ex.h +++ b/arch/powerpc/include/asm/ppc405ex.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC405EX_H_ diff --git a/arch/powerpc/include/asm/ppc405ez.h b/arch/powerpc/include/asm/ppc405ez.h index 0a53458af1..40cf8ed51b 100644 --- a/arch/powerpc/include/asm/ppc405ez.h +++ b/arch/powerpc/include/asm/ppc405ez.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC405EZ_H_ diff --git a/arch/powerpc/include/asm/ppc405gp.h b/arch/powerpc/include/asm/ppc405gp.h index 60d2d3d6af..0044a3a42c 100644 --- a/arch/powerpc/include/asm/ppc405gp.h +++ b/arch/powerpc/include/asm/ppc405gp.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC405GP_H_ diff --git a/arch/powerpc/include/asm/ppc440.h b/arch/powerpc/include/asm/ppc440.h index 411d441a20..0cfa88bff5 100644 --- a/arch/powerpc/include/asm/ppc440.h +++ b/arch/powerpc/include/asm/ppc440.h @@ -1,26 +1,3 @@ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of the -| GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ - /* * (C) Copyright 2006 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com @@ -32,7 +9,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 IBM-pibs */ #ifndef __PPC440_H__ diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h index 9ebbfcc2b2..c2c3abb0b0 100644 --- a/arch/powerpc/include/asm/ppc440ep_gr.h +++ b/arch/powerpc/include/asm/ppc440ep_gr.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC440EP_GR_H_ diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h index 2520050773..93c3e2ef1a 100644 --- a/arch/powerpc/include/asm/ppc440epx_grx.h +++ b/arch/powerpc/include/asm/ppc440epx_grx.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC440EPX_GRX_H_ diff --git a/arch/powerpc/include/asm/ppc440gp.h b/arch/powerpc/include/asm/ppc440gp.h index 7eb16216c7..01b66c0508 100644 --- a/arch/powerpc/include/asm/ppc440gp.h +++ b/arch/powerpc/include/asm/ppc440gp.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC440GP_H_ diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h index 4e3cbfb896..7bd36e860b 100644 --- a/arch/powerpc/include/asm/ppc440gx.h +++ b/arch/powerpc/include/asm/ppc440gx.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC440GX_H_ diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h index ca69179a9b..5c2192ee43 100644 --- a/arch/powerpc/include/asm/ppc440sp.h +++ b/arch/powerpc/include/asm/ppc440sp.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC440SP_H_ diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h index 2ae2193de8..105dc01196 100644 --- a/arch/powerpc/include/asm/ppc440spe.h +++ b/arch/powerpc/include/asm/ppc440spe.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC440SPE_H_ diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h index 31750a4555..f41df0da6a 100644 --- a/arch/powerpc/include/asm/ppc460ex_gt.h +++ b/arch/powerpc/include/asm/ppc460ex_gt.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC460EX_GT_H_ diff --git a/arch/powerpc/include/asm/ppc460sx.h b/arch/powerpc/include/asm/ppc460sx.h index d6dcda52e2..b692d07f33 100644 --- a/arch/powerpc/include/asm/ppc460sx.h +++ b/arch/powerpc/include/asm/ppc460sx.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC460SX_H_ diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 9eb50ee84d..952783f961 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC4xx_EBC_H_ @@ -14,12 +14,12 @@ * Within this group there is a slight variation concerning the bit field * position of the EMPL and EMPH fields: */ -#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ +#if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define CONFIG_EBC_PPC4xx_IBM_VER1 -#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ +#if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) #define EBC_CFG_EMPH_POS 8 #define EBC_CFG_EMPL_POS 6 @@ -32,7 +32,7 @@ /* * Define the max number of EBC banks (chip selects) */ -#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ +#if defined(CONFIG_405GP) || \ defined(CONFIG_405EZ) || \ defined(CONFIG_440GP) || defined(CONFIG_440GX) #define EBC_NUM_BANKS 8 @@ -53,8 +53,7 @@ #define EBC_NUM_BANKS 6 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define EBC_NUM_BANKS 3 #endif diff --git a/arch/powerpc/include/asm/ppc4xx-emac.h b/arch/powerpc/include/asm/ppc4xx-emac.h index a219fa97fa..76fa95ca37 100644 --- a/arch/powerpc/include/asm/ppc4xx-emac.h +++ b/arch/powerpc/include/asm/ppc4xx-emac.h @@ -1,25 +1,6 @@ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of the -| GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /*----------------------------------------------------------------------------+ | | File Name: enetemac.h diff --git a/arch/powerpc/include/asm/ppc4xx-i2c.h b/arch/powerpc/include/asm/ppc4xx-i2c.h index 09189cf19b..df97f175b3 100644 --- a/arch/powerpc/include/asm/ppc4xx-i2c.h +++ b/arch/powerpc/include/asm/ppc4xx-i2c.h @@ -72,6 +72,8 @@ struct ppc4xx_i2c { #define IIC_EXTSTS_XFRA 0x01 #define IIC_EXTSTS_ICT 0x02 #define IIC_EXTSTS_LA 0x04 +#define IIC_EXTSTS_BCS_MASK 0x70 +#define IIC_EXTSTS_BCS_FREE 0x40 /* XTCNTLSS Register Bit definition */ #define IIC_XTCNTLSS_SRST 0x01 diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index 04fc8916eb..2ae399f248 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -1,4 +1,3 @@ - /* * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,8 +8,7 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -27,8 +25,7 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -42,8 +39,6 @@ #if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_SIZE 0x0984 /* OCM size 64k */ -#elif defined(CONFIG_APM821XX) -#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ #endif /* @@ -52,7 +47,7 @@ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-mal.h b/arch/powerpc/include/asm/ppc4xx-mal.h index 71986856b1..ef8b174461 100644 --- a/arch/powerpc/include/asm/ppc4xx-mal.h +++ b/arch/powerpc/include/asm/ppc4xx-mal.h @@ -1,26 +1,7 @@ /* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of the -| GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /*----------------------------------------------------------------------------+ | | File Name: mal.h diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 84968f81f6..e6fed83bf1 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC4xx_SDRAM_H_ @@ -276,7 +276,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -349,7 +349,7 @@ /* * Memory controller registers */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -359,9 +359,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX || CONFIG_APM821XX */ +#else /* CONFIG_405EX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX || CONFIG_APM821XX */ +#endif /* CONFIG_405EX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -407,12 +407,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) +#if !defined(CONFIG_405EX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 13211e3a9c..58e65c1336 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -4,7 +4,7 @@ * (C) Copyright 2008-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PPC4xx_UIC_H_ @@ -15,7 +15,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -236,8 +236,7 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index 9f2a08b8b3..b8b0ff9f25 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -1,25 +1,6 @@ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of -| the GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ @@ -27,10 +8,6 @@ /* * Include SoC specific headers */ -#if defined(CONFIG_405CR) -#include -#endif - #if defined(CONFIG_405EP) #include #endif @@ -79,10 +56,6 @@ #include #endif -#if defined(CONFIG_APM821XX) -#include -#endif - /* * Common registers for all SoC's */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 56b22d840a..db8cc8c4e6 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -7,8 +7,6 @@ */ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) -#include - #include #include @@ -380,11 +378,16 @@ #else #define SPRN_TCR 0x154 /* Book E Timer Control Register */ #endif /* CONFIG_BOOKE */ +#ifdef CONFIG_E500MC +#define TCR_WP(x) (((64-x)&0x3)<<30)| \ + (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/ +#else #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ #define WP_2_17 0 /* 2^17 clocks */ #define WP_2_21 1 /* 2^21 clocks */ #define WP_2_25 2 /* 2^25 clocks */ #define WP_2_29 3 /* 2^29 clocks */ +#endif /* CONFIG_E500 */ #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ #define WRC_NONE 0 /* No reset will occur */ #define WRC_CORE 1 /* Core reset will occur */ @@ -847,7 +850,7 @@ /* System-On-Chip Version Register (SVR) field extraction */ #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFF) /* Revision field */ #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ @@ -894,9 +897,6 @@ #define PVR_405GP_RC 0x40110082 #define PVR_405GP_RD 0x401100C4 #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ -#define PVR_405CR_RA 0x40110041 -#define PVR_405CR_RB 0x401100C5 -#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 #define PVR_405EZ_RA 0x41511460 @@ -1043,9 +1043,6 @@ /* System Version Register (SVR) field extraction */ -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ - #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ @@ -1119,9 +1116,13 @@ #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 #define SVR_T4160 0x824100 +#define SVR_T4080 0x824102 +#define SVR_C291 0x850000 +#define SVR_C292 0x850020 +#define SVR_C293 0x850030 #define SVR_B4860 0X868000 #define SVR_G4860 0x868001 -#define SVR_G4060 0x868003 +#define SVR_B4460 0x868003 #define SVR_B4440 0x868100 #define SVR_G4440 0x868101 #define SVR_B4420 0x868102 @@ -1132,6 +1133,12 @@ #define SVR_T1020 0x852100 #define SVR_T1021 0x852101 #define SVR_T1022 0x852102 +#define SVR_T1024 0x854000 +#define SVR_T1023 0x854100 +#define SVR_T1014 0x854400 +#define SVR_T1013 0x854500 +#define SVR_T2080 0x853000 +#define SVR_T2081 0x853100 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 @@ -1347,26 +1354,12 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); #if defined(CONFIG_8xx) #define _machine _MACH_8xx #define have_of 0 -#elif defined(CONFIG_OAK) -#define _machine _MACH_oak -#define have_of 0 #elif defined(CONFIG_WALNUT) #define _machine _MACH_walnut #define have_of 0 -#elif defined(CONFIG_APUS) -#define _machine _MACH_apus -#define have_of 0 -#elif defined(CONFIG_GEMINI) -#define _machine _MACH_gemini -#define have_of 0 -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #define _machine _MACH_8260 #define have_of 0 -#elif defined(CONFIG_SANDPOINT) -#define _machine _MACH_sandpoint -#elif defined(CONFIG_HIDDEN_DRAGON) -#define _machine _MACH_hidden_dragon -#define have_of 0 #else #error "Machine not defined correctly" #endif diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index cf09edf156..2d56de61d1 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -17,8 +17,6 @@ * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. */ -#include - #ifndef __ASSEMBLY__ #ifdef CONFIG_PPC64BRIDGE #define PPC_REG unsigned long /*long*/ diff --git a/arch/powerpc/include/asm/residual.h b/arch/powerpc/include/asm/residual.h deleted file mode 100644 index dc85edbc3c..0000000000 --- a/arch/powerpc/include/asm/residual.h +++ /dev/null @@ -1,331 +0,0 @@ -/* 7/18/95 */ -/*----------------------------------------------------------------------------*/ -/* Residual Data header definitions and prototypes */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for RESIDUAL on PowerPC Reference Platform */ -/* residual.h - Residual data structure passed in r3. */ -/* Load point passed in r4 to boot image. */ -/* For enum's: if given in hex then they are bit significant, */ -/* i.e. only one bit is on for each enum */ -/* Reserved fields must be filled with zeros. */ - -#ifndef _RESIDUAL_ -#define _RESIDUAL_ - -#ifndef __ASSEMBLY__ - -#define MAX_CPUS 32 /* These should be set to the maximum */ -#define MAX_MEMS 64 /* number possible for this system. */ -#define MAX_DEVICES 256 /* Changing these will change the */ -#define AVE_PNP_SIZE 32 /* structure, hence the version of */ -#define MAX_MEM_SEGS 64 /* this header file. */ - -/*----------------------------------------------------------------------------*/ -/* Public structures... */ -/*----------------------------------------------------------------------------*/ - -#include "pnp.h" - -typedef enum _L1CACHE_TYPE { - NoneCAC = 0, - SplitCAC = 1, - CombinedCAC = 2 - } L1CACHE_TYPE; - -typedef enum _TLB_TYPE { - NoneTLB = 0, - SplitTLB = 1, - CombinedTLB = 2 - } TLB_TYPE; - -typedef enum _FIRMWARE_SUPPORT { - Conventional = 0x01, - OpenFirmware = 0x02, - Diagnostics = 0x04, - LowDebug = 0x08, - Multiboot = 0x10, - LowClient = 0x20, - Hex41 = 0x40, - FAT = 0x80, - ISO9660 = 0x0100, - SCSI_InitiatorID_Override = 0x0200, - Tape_Boot = 0x0400, - FW_Boot_Path = 0x0800 - } FIRMWARE_SUPPORT; - -typedef enum _FIRMWARE_SUPPLIERS { - IBMFirmware = 0x00, - MotoFirmware = 0x01, /* 7/18/95 */ - FirmWorks = 0x02, /* 10/5/95 */ - Bull = 0x03, /* 04/03/96 */ - } FIRMWARE_SUPPLIERS; - -typedef enum _ENDIAN_SWITCH_METHODS { - UsePort92 = 0x01, - UsePCIConfigA8 = 0x02, - UseFF001030 = 0x03, - } ENDIAN_SWITCH_METHODS; - -typedef enum _SPREAD_IO_METHODS { - UsePort850 = 0x00, -/*UsePCIConfigA8 = 0x02,*/ - } SPREAD_IO_METHODS; - -typedef struct _VPD { - - /* Box dependent stuff */ - unsigned char PrintableModel[32]; /* Null terminated string. - Must be of the form: - vvv,<20h>,,<0x0> - where vvv is the vendor ID - e.g. IBM PPS MODEL 6015<0x0> */ - unsigned char Serial[16]; /* 12/94: - Serial Number; must be of the form: - vvv where vvv is the - vendor ID. - e.g. IBM60151234567<20h><20h> */ - unsigned char Reserved[48]; - unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ - unsigned long FirmwareSupports; /* See FirmwareSupport enum */ - unsigned long NvramSize; /* Size of nvram in bytes */ - unsigned long NumSIMMSlots; - unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ - unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ - unsigned long SmpIar; - unsigned long RAMErrLogOffset; /* Heap offset to error log */ - unsigned long Reserved5; - unsigned long Reserved6; - unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ - unsigned long ProcessorBusHz; /* Processor bus clock frequency */ - unsigned long Reserved7; - unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ - unsigned long WordWidth; /* Word width in bits */ - unsigned long PageSize; /* Page size in bytes */ - unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache - for which coherency is maintained; - normally <= CacheLineSize. */ - unsigned long GranuleSize; /* Unit of lock allocation to avoid */ - /* false sharing of locks. */ - - /* L1 Cache variables */ - unsigned long CacheSize; /* L1 Cache size in KB. This is the */ - /* total size of the L1, whether */ - /* combined or split */ - unsigned long CacheAttrib; /* L1CACHE_TYPE */ - unsigned long CacheAssoc; /* L1 Cache associativity. Use this - for combined cache. If split, put - zeros here. */ - unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use - for combined cache. If split, put - zeros here. */ - /* For split L1 Cache: (= combined if combined cache) */ - unsigned long I_CacheSize; - unsigned long I_CacheAssoc; - unsigned long I_CacheLineSize; - unsigned long D_CacheSize; - unsigned long D_CacheAssoc; - unsigned long D_CacheLineSize; - - /* Translation Lookaside Buffer variables */ - unsigned long TLBSize; /* Total number of TLBs on the system */ - unsigned long TLBAttrib; /* Combined I+D or split TLB */ - unsigned long TLBAssoc; /* TLB Associativity. Use this for - combined TLB. If split, put zeros - here. */ - /* For split TLB: (= combined if combined TLB) */ - unsigned long I_TLBSize; - unsigned long I_TLBAssoc; - unsigned long D_TLBSize; - unsigned long D_TLBAssoc; - - unsigned long ExtendedVPD; /* Offset to extended VPD area; - null if unused */ - } VPD; - -typedef enum _DEVICE_FLAGS { - Enabled = 0x4000, /* 1 - PCI device is enabled */ - Integrated = 0x2000, - Failed = 0x1000, /* 1 - device failed POST code tests */ - Static = 0x0800, /* 0 - dynamically configurable - 1 - static */ - Dock = 0x0400, /* 0 - not a docking station device - 1 - is a docking station device */ - Boot = 0x0200, /* 0 - device cannot be used for BOOT - 1 - can be a BOOT device */ - Configurable = 0x0100, /* 1 - device is configurable */ - Disableable = 0x80, /* 1 - device can be disabled */ - PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ - ReadOnly = 0x20, /* 1 - device is read only */ - Removable = 0x10, /* 1 - device is removable */ - ConsoleIn = 0x08, - ConsoleOut = 0x04, - Input = 0x02, - Output = 0x01 - } DEVICE_FLAGS; - -typedef enum _BUS_ID { - ISADEVICE = 0x01, - EISADEVICE = 0x02, - PCIDEVICE = 0x04, - PCMCIADEVICE = 0x08, - PNPISADEVICE = 0x10, - MCADEVICE = 0x20, - MXDEVICE = 0x40, /* Devices on mezzanine bus */ - PROCESSORDEVICE = 0x80, /* Devices on processor bus */ - VMEDEVICE = 0x100, - } BUS_ID; - -typedef struct _DEVICE_ID { - unsigned long BusId; /* See BUS_ID enum above */ - unsigned long DevId; /* Big Endian format */ - unsigned long SerialNum; /* For multiple usage of a single - DevId */ - unsigned long Flags; /* See DEVICE_FLAGS enum above */ - unsigned char BaseType; /* See pnp.h for bit definitions */ - unsigned char SubType; /* See pnp.h for bit definitions */ - unsigned char Interface; /* See pnp.h for bit definitions */ - unsigned char Spare; - } DEVICE_ID; - -typedef union _BUS_ACCESS { - struct _PnPAccess{ - unsigned char CSN; - unsigned char LogicalDevNumber; - unsigned short ReadDataPort; - } PnPAccess; - struct _ISAAccess{ - unsigned char SlotNumber; /* ISA Slot Number generally not - available; 0 if unknown */ - unsigned char LogicalDevNumber; - unsigned short ISAReserved; - } ISAAccess; - struct _MCAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short MCAReserved; - } MCAAccess; - struct _PCMCIAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short PCMCIAReserved; - } PCMCIAAccess; - struct _EISAAccess{ - unsigned char SlotNumber; - unsigned char FunctionNumber; - unsigned short EISAReserved; - } EISAAccess; - struct _PCIAccess{ - unsigned char BusNumber; - unsigned char DevFuncNumber; - unsigned short PCIReserved; - } PCIAccess; - struct _ProcBusAccess{ - unsigned char BusNumber; - unsigned char BUID; - unsigned short ProcBusReserved; - } ProcBusAccess; - } BUS_ACCESS; - -/* Per logical device information */ -typedef struct _PPC_DEVICE { - DEVICE_ID DeviceId; - BUS_ACCESS BusAccess; - - /* The following three are offsets into the DevicePnPHeap */ - /* All are in PnP compressed format */ - unsigned long AllocatedOffset; /* Allocated resource description */ - unsigned long PossibleOffset; /* Possible resource description */ - unsigned long CompatibleOffset; /* Compatible device identifiers */ - } PPC_DEVICE; - -typedef enum _CPU_STATE { - CPU_GOOD = 0, /* CPU is present, and active */ - CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ - CPU_OFF = 2, /* CPU is present, but inactive */ - CPU_FAILED = 3, /* CPU is present, but failed POST */ - CPU_NOT_PRESENT = 255 /* CPU not present */ - } CPU_STATE; - -typedef struct _PPC_CPU { - unsigned long CpuType; /* Result of mfspr from Processor - Version Register (PVR). - PVR(0-15) = Version (e.g. 601) - PVR(16-31 = EC Level */ - unsigned char CpuNumber; /* CPU Number for this processor */ - unsigned char CpuState; /* CPU State, see CPU_STATE enum */ - unsigned short Reserved; - } PPC_CPU; - -typedef struct _PPC_MEM { - unsigned long SIMMSize; /* 0 - absent or bad - 8M, 32M (in MB) */ - } PPC_MEM; - -typedef enum _MEM_USAGE { - Other = 0x8000, - ResumeBlock = 0x4000, /* for use by power management */ - SystemROM = 0x2000, /* Flash memory (populated) */ - UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ - IOMemory = 0x0800, - SystemIO = 0x0400, - SystemRegs = 0x0200, - PCIAddr = 0x0100, - PCIConfig = 0x80, - ISAAddr = 0x40, - Unpopulated = 0x20, /* Unpopulated part of System Memory */ - Free = 0x10, /* Free part of System Memory */ - BootImage = 0x08, /* BootImage part of System Memory */ - FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ - FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ - FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ - } MEM_USAGE; - -typedef struct _MEM_MAP { - unsigned long Usage; /* See MEM_USAGE above */ - unsigned long BasePage; /* Page number measured in 4KB pages */ - unsigned long PageCount; /* Page count measured in 4KB pages */ - } MEM_MAP; - -typedef struct _RESIDUAL { - unsigned long ResidualLength; /* Length of Residual */ - unsigned char Version; /* of this data structure */ - unsigned char Revision; /* of this data structure */ - unsigned short EC; /* of this data structure */ - /* VPD */ - VPD VitalProductData; - /* CPU */ - unsigned short MaxNumCpus; /* Max CPUs in this system */ - unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ - /* that there are unpopulated or */ - /* otherwise unusable cpu locations */ - PPC_CPU Cpus[MAX_CPUS]; - /* Memory */ - unsigned long TotalMemory; /* Total amount of memory installed */ - unsigned long GoodMemory; /* Total amount of good memory */ - unsigned long ActualNumMemSegs; - MEM_MAP Segs[MAX_MEM_SEGS]; - unsigned long ActualNumMemories; - PPC_MEM Memories[MAX_MEMS]; - /* Devices */ - unsigned long ActualNumDevices; - PPC_DEVICE Devices[MAX_DEVICES]; - unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; - } RESIDUAL; - - -extern RESIDUAL *res; -extern void print_residual_device_info(void); -extern PPC_DEVICE *residual_find_device(unsigned long BusMask, - unsigned char * DevID, int BaseType, - int SubType, int Interface, int n); -extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, - int n); -extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); -extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); -#endif /* __ASSEMBLY__ */ -#endif /* ndef _RESIDUAL_ */ diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h index 037570993a..441619042d 100644 --- a/arch/powerpc/include/asm/status_led.h +++ b/arch/powerpc/include/asm/status_led.h @@ -11,7 +11,7 @@ #ifndef CONFIG_BOARD_SPECIFIC_LED # if defined(CONFIG_8xx) # include -# elif defined(CONFIG_8260) +# elif defined(CONFIG_MPC8260) # include # elif defined(CONFIG_5xx) # include diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h index b27a6b753a..b29ce792f7 100644 --- a/arch/powerpc/include/asm/types.h +++ b/arch/powerpc/include/asm/types.h @@ -41,8 +41,12 @@ typedef unsigned long long u64; #define BITS_PER_LONG 32 +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long dma_addr_t; +#else /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; +#endif #ifdef CONFIG_PHYS_64BIT typedef unsigned long long phys_addr_t; diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index f17b146da3..a61e998df6 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -35,7 +35,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif @@ -64,10 +64,8 @@ typedef struct bd_info { unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ - defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || \ @@ -79,9 +77,6 @@ typedef struct bd_info { unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ #endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif #ifdef CONFIG_HAS_ETH1 unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ @@ -107,9 +102,6 @@ typedef struct bd_info { unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif -#if defined(CONFIG_NX823) - unsigned char bi_sernum[8]; -#endif #if defined(CONFIG_4xx) #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 88152920b2..0f6298269a 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -5,22 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - ## Build a couple of necessary functions into a private libgcc -LIBGCC = $(obj)libgcc.o -GLSOBJS += _ashldi3.o -GLSOBJS += _ashrdi3.o -GLSOBJS += _lshrdi3.o -LGOBJS := $(addprefix $(obj),$(GLSOBJS)) \ - $(addprefix $(obj),$(GLCOBJS)) - -## But only build it if the user asked for it -ifdef USE_PRIVATE_LIBGCC -TARGETS += $(LIBGCC) -endif - -LIB = $(obj)lib$(ARCH).o +## if the user asked for it +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o MINIMAL= @@ -31,29 +18,29 @@ endif endif ifdef MINIMAL -COBJS-y += cache.o time.o -SOBJS-y += ticks.o +obj-y += cache.o time.o +obj-y += ticks.o else -SOBJS-y += ppcstring.o +obj-y += ppcstring.o -SOBJS-y += ppccache.o -SOBJS-y += ticks.o -SOBJS-y += reloc.o +obj-y += ppccache.o +obj-y += ticks.o +obj-y += reloc.o -COBJS-$(CONFIG_BAT_RW) += bat_rw.o +obj-$(CONFIG_BAT_RW) += bat_rw.o ifndef CONFIG_SPL_BUILD ifndef CONFIG_SYS_GENERIC_BOARD -COBJS-y += board.o +obj-y += board.o endif endif -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-y += cache.o -COBJS-y += extable.o -COBJS-y += interrupts.o -COBJS-$(CONFIG_CMD_KGDB) += kgdb.o -COBJS-${CONFIG_CMD_IDE} += ide.o -COBJS-y += time.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-y += cache.o +obj-y += extable.o +obj-y += interrupts.o +obj-$(CONFIG_CMD_KGDB) += kgdb.o +obj-$(CONFIG_CMD_IDE) += ide.o +obj-y += time.o # Don't include the MPC5xxx special memcpy into the # SPL U-Boot image. memcpy is used in the SPL NOR @@ -63,42 +50,17 @@ ifndef CONFIG_SPL_BUILD # Workaround for local bus unaligned access problems # on MPC512x and MPC5200 ifdef CONFIG_MPC512X -$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy -COBJS-y += memcpy_mpc5200.o +AFLAGS_ppcstring.o += -Dmemcpy=__memcpy +obj-y += memcpy_mpc5200.o endif ifdef CONFIG_MPC5200 -$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy -COBJS-y += memcpy_mpc5200.o +AFLAGS_ppcstring.o += -Dmemcpy=__memcpy +obj-y += memcpy_mpc5200.o endif endif endif # not minimal ifdef CONFIG_SPL_BUILD -COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o +obj-$(CONFIG_SPL_FRAMEWORK) += spl.o endif - -COBJS += $(sort $(COBJS-y)) - -SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ - $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -TARGETS += $(LIB) - -all: $(TARGETS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(LIBGCC): $(obj).depend $(LGOBJS) - $(call cmd_link_o_target, $(LGOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index a101e03601..91645d36ee 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -226,6 +226,9 @@ static int init_func_spi(void) #if defined(CONFIG_WATCHDOG) int init_func_watchdog_init(void) { +#if defined(CONFIG_MPC85xx) + init_85xx_watchdog(); +#endif puts(" Watchdog enabled\n"); WATCHDOG_RESET(); return 0; @@ -277,10 +280,10 @@ static init_fnc_t *init_sequence[] = { serial_init, console_init_f, display_options, -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) prt_8260_rsr, prt_8260_clks, -#endif /* CONFIG_8260 */ +#endif /* CONFIG_MPC8260 */ #if defined(CONFIG_MPC83xx) prt_83xx_rsr, #endif @@ -312,17 +315,6 @@ static init_fnc_t *init_sequence[] = { NULL, /* Terminate this list */ }; -ulong get_effective_memsize(void) -{ -#ifndef CONFIG_VERY_BIG_RAM - return gd->ram_size; -#else - /* limit stack to what we can reasonable map */ - return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); -#endif -} - static int __fixup_cpu(void) { return 0; @@ -343,13 +335,6 @@ int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu"))); * initialized, and stack space is limited to a few kB. */ -#ifdef CONFIG_LOGBUFFER -unsigned long logbuffer_base(void) -{ - return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; -} -#endif - void board_init_f(ulong bootflag) { bd_t *bd; @@ -374,6 +359,8 @@ void board_init_f(ulong bootflag) memset((void *) gd, 0, sizeof(gd_t)); #endif + gd->flags = bootflag; + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) if ((*init_fnc_ptr) () != 0) hang(); @@ -522,7 +509,7 @@ void board_init_f(ulong bootflag) bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif -#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif @@ -549,7 +536,6 @@ void board_init_f(ulong bootflag) bd->bi_ipbfreq = gd->arch.ipb_clk; bd->bi_pcifreq = gd->pci_clk; #endif /* CONFIG_MPC5xxx */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CONFIG_SYS_EXTBDINFO strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); @@ -813,13 +799,6 @@ void board_init_r(gd_t *id, ulong dest_addr) mac_read_from_eeprom(); #endif -#ifdef CONFIG_HERMES - if ((gd->board_type >> 16) == 2) - bd->bi_ethspeed = gd->board_type & 0xFFFF; - else - bd->bi_ethspeed = 0xFFFF; -#endif - #ifdef CONFIG_CMD_NET /* kept around for legacy kernels only ... ignore the next section */ eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr); @@ -869,11 +848,6 @@ void board_init_r(gd_t *id, ulong dest_addr) misc_init_r(); #endif -#ifdef CONFIG_HERMES - if (bd->bi_ethspeed != 0xFFFF) - hermes_start_lxt980((int) bd->bi_ethspeed); -#endif - #if defined(CONFIG_CMD_KGDB) WATCHDOG_RESET(); puts("KGDB: "); @@ -984,7 +958,7 @@ void board_init_r(gd_t *id, ulong dest_addr) pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; #endif #endif - sprintf(memsz, "%ldk", (bd->bi_memsize / 1024) - pram); + sprintf(memsz, "%ldk", (ulong) (bd->bi_memsize / 1024) - pram); setenv("mem", memsz); } #endif @@ -994,14 +968,6 @@ void board_init_r(gd_t *id, ulong dest_addr) kbd_init(); #endif -#ifdef CONFIG_MODEM_SUPPORT - { - extern int do_mdm_init; - - do_mdm_init = gd->do_mdm_init; - } -#endif - /* Initialization complete - start the monitor */ /* main_loop() can return to retry autoboot, if so just run it again. */ diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index e7153b0480..ef15e7ac92 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -30,8 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; -extern ulong get_effective_memsize(void); static ulong get_sp (void); +extern void ft_fixup_num_cores(void *blob); static void set_clocks_in_mhz (bd_t *kbd); #ifndef CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE @@ -53,6 +53,13 @@ static void boot_jump_linux(bootm_headers_t *images) bootstage_mark(BOOTSTAGE_ID_RUN_OS); +#ifdef CONFIG_BOOTSTAGE_FDT + bootstage_fdt_add_report(); +#endif +#ifdef CONFIG_BOOTSTAGE_REPORT + bootstage_report(); +#endif + #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); #endif @@ -119,7 +126,7 @@ void arch_lmb_reserve(struct lmb *lmb) #endif size = min(bootm_size, get_effective_memsize()); - size = min(size, CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE); + size = min(size, (ulong)CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE); if (size < bootm_size) { ulong base = bootmap_base + size; @@ -277,3 +284,58 @@ static void set_clocks_in_mhz (bd_t *kbd) #endif /* CONFIG_MPC5xxx */ } } + +#if defined(CONFIG_BOOTM_VXWORKS) +void boot_prep_vxworks(bootm_headers_t *images) +{ +#if defined(CONFIG_OF_LIBFDT) + int off; + u64 base, size; + + if (!images->ft_addr) + return; + + base = (u64)gd->bd->bi_memstart; + size = (u64)gd->bd->bi_memsize; + + off = fdt_path_offset(images->ft_addr, "/memory"); + if (off < 0) + fdt_fixup_memory(images->ft_addr, base, size); + +#if defined(CONFIG_MP) +#if defined(CONFIG_MPC85xx) + ft_fixup_cpu(images->ft_addr, base + size); + ft_fixup_num_cores(images->ft_addr); +#elif defined(CONFIG_MPC86xx) + off = fdt_add_mem_rsv(images->ft_addr, + determine_mp_bootpg(NULL), (u64)4096); + if (off < 0) + printf("## WARNING %s: %s\n", __func__, fdt_strerror(off)); + ft_fixup_num_cores(images->ft_addr); +#endif + flush_cache((unsigned long)images->ft_addr, images->ft_len); +#endif +#endif +} + +void boot_jump_vxworks(bootm_headers_t *images) +{ + /* PowerPC VxWorks boot interface conforms to the ePAPR standard + * general purpuse registers: + * + * r3: Effective address of the device tree image + * r4: 0 + * r5: 0 + * r6: ePAPR magic value + * r7: shall be the size of the boot IMA in bytes + * r8: 0 + * r9: 0 + * TCR: WRC = 0, no watchdog timer reset will occur + */ + WATCHDOG_RESET(); + + ((void (*)(void *, ulong, ulong, ulong, + ulong, ulong, ulong))images->ep)(images->ft_addr, + 0, 0, EPAPR_MAGIC, getenv_bootm_mapsize(), 0, 0); +} +#endif diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c index 19a56dbe21..01a7708aef 100644 --- a/arch/powerpc/lib/kgdb.c +++ b/arch/powerpc/lib/kgdb.c @@ -159,7 +159,7 @@ kgdb_trap(struct pt_regs *regs) #define SPACE_REQUIRED ((32*4)+(32*8)+(6*4)) -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 /* store floating double indexed */ #define STFDI(n,p) __asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n])) /* store floating double multiple */ @@ -190,7 +190,7 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max) *ptr++ = regs->gpr[i]; /* Floating Point Regs */ -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 STFDM(ptr); ptr += 32*2; #else @@ -213,7 +213,7 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max) /* set the value of the CPU registers */ -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 /* load floating double */ #define LFD(n,v) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v)) /* load floating double indexed */ @@ -252,7 +252,7 @@ kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length) regs->gpr[regno] = *ptr; else switch (regno) { -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 #define caseF(n) \ case (n) + 32: LFD(n, *ptr); break; @@ -298,7 +298,7 @@ kgdb_putregs(struct pt_regs *regs, char *buf, int length) regs->gpr[i] = *ptr++; /* Floating Point Regs */ -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 LFDM(ptr); #endif ptr += 32*2; diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig new file mode 100644 index 0000000000..3057325b47 --- /dev/null +++ b/arch/sandbox/Kconfig @@ -0,0 +1,13 @@ +menu "Sandbox architecture" + depends on SANDBOX + +config SYS_ARCH + default "sandbox" + +config SYS_BOARD + default "sandbox" + +config SYS_CONFIG_NAME + default "sandbox" + +endmenu diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile new file mode 100644 index 0000000000..23fdcdb53c --- /dev/null +++ b/arch/sandbox/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/sandbox/cpu/start.o + +libs-y += arch/sandbox/cpu/ +libs-y += arch/sandbox/lib/ diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 6142dd4c70..e38a44bd11 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -1,9 +1,26 @@ # Copyright (c) 2011 The Chromium OS Authors. # SPDX-License-Identifier: GPL-2.0+ -PLATFORM_CPPFLAGS += -DCONFIG_SANDBOX -D__SANDBOX__ -U_FORTIFY_SOURCE +PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD PLATFORM_LIBS += -lrt +ifdef CONFIG_SANDBOX_SDL +PLATFORM_LIBS += $(shell sdl-config --libs) +PLATFORM_CPPFLAGS += $(shell sdl-config --cflags) +endif + # Support generic board on sandbox __HAVE_ARCH_GENERIC_BOARD := y + +cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \ + -Wl,--start-group $(u-boot-main) -Wl,--end-group \ + $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map + +CONFIG_ARCH_DEVICE_TREE := sandbox + +# Define this to avoid linking with SDL, which requires SDL libraries +# This can solve 'sdl-config: Command not found' errors +ifneq ($(NO_SDL),) +PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL +endif diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index e386867fe6..7d4410c42a 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -7,29 +7,16 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -COBJS := cpu.o os.o start.o state.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) +obj-y := cpu.o os.o start.o state.o +obj-$(CONFIG_SANDBOX_SDL) += sdl.o # os.c is build in the system environment, so needs standard includes -$(obj)os.o: ALL_CFLAGS := $(filter-out -nostdinc,$(ALL_CFLAGS)) -$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,$(CPPFLAGS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +# CFLAGS_REMOVE_os.o cannot be used to drop header include path +quiet_cmd_cc_os.o = CC $(quiet_modtag) $@ +cmd_cc_os.o = $(CC) $(filter-out -nostdinc, \ + $(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $< + +$(obj)/os.o: $(src)/os.c FORCE + $(call if_changed_dep,cc_os.o) +$(obj)/sdl.o: $(src)/sdl.c FORCE + $(call if_changed_dep,cc_os.o) diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index cfc1fda1e1..1aa397c5e7 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -4,14 +4,28 @@ */ #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +void reset_cpu(ulong ignored) { + if (state_uninit()) + os_exit(2); + + if (dm_uninit()) + os_exit(2); + /* This is considered normal termination for now */ os_exit(0); +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + reset_cpu(0); + return 0; } @@ -28,7 +42,14 @@ unsigned long __attribute__((no_instrument_function)) timer_get_us(void) int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { - return -1; + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + printf("## Transferring control to Linux (at address %08lx)...\n", + images->ep); + reset_cpu(0); + } + + return 0; } int cleanup_before_linux(void) @@ -41,7 +62,7 @@ void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) return (void *)(gd->arch.ram_buf + paddr); } -phys_addr_t map_to_sysmem(void *ptr) +phys_addr_t map_to_sysmem(const void *ptr) { return (u8 *)ptr - gd->arch.ram_buf; } diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index c2e5f57193..4d5f805753 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,10 @@ /* Operating System Interface */ +struct os_mem_hdr { + size_t length; /* number of bytes in the block */ +}; + ssize_t os_read(int fd, void *buf, size_t count) { return read(fd, buf, count); @@ -87,6 +92,11 @@ int os_close(int fd) return close(fd); } +int os_unlink(const char *pathname) +{ + return unlink(pathname); +} + void os_exit(int exit_code) { exit(exit_code); @@ -94,21 +104,22 @@ void os_exit(int exit_code) /* Restore tty state when we exit */ static struct termios orig_term; +static bool term_setup; static void os_fd_restore(void) { - tcsetattr(0, TCSANOW, &orig_term); + if (term_setup) + tcsetattr(0, TCSANOW, &orig_term); } /* Put tty into raw mode so and work */ -void os_tty_raw(int fd) +void os_tty_raw(int fd, bool allow_sigs) { - static int setup = 0; struct termios term; - if (setup) + if (term_setup) return; - setup = 1; + term_setup = true; /* If not a tty, don't complain */ if (tcgetattr(fd, &orig_term)) @@ -118,7 +129,7 @@ void os_tty_raw(int fd) term.c_iflag = IGNBRK | IGNPAR; term.c_oflag = OPOST | ONLCR; term.c_cflag = CS8 | CREAD | CLOCAL; - term.c_lflag = 0; + term.c_lflag = allow_sigs ? ISIG : 0; if (tcsetattr(fd, TCSANOW, &term)) return; @@ -127,8 +138,45 @@ void os_tty_raw(int fd) void *os_malloc(size_t length) { - return mmap(NULL, length, PROT_READ | PROT_WRITE, - MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + struct os_mem_hdr *hdr; + + hdr = mmap(NULL, length + sizeof(*hdr), PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (hdr == MAP_FAILED) + return NULL; + hdr->length = length; + + return hdr + 1; +} + +void os_free(void *ptr) +{ + struct os_mem_hdr *hdr = ptr; + + hdr--; + if (ptr) + munmap(hdr, hdr->length + sizeof(*hdr)); +} + +void *os_realloc(void *ptr, size_t length) +{ + struct os_mem_hdr *hdr = ptr; + void *buf = NULL; + + hdr--; + if (length != 0) { + buf = os_malloc(length); + if (!buf) + return buf; + if (ptr) { + if (length > hdr->length) + length = hdr->length; + memcpy(buf, ptr, length); + } + } + os_free(ptr); + + return buf; } void os_usleep(unsigned long usec) @@ -136,7 +184,7 @@ void os_usleep(unsigned long usec) usleep(usec); } -u64 __attribute__((no_instrument_function)) os_get_nsec(void) +uint64_t __attribute__((no_instrument_function)) os_get_nsec(void) { #if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK) struct timespec tp; @@ -160,7 +208,7 @@ static struct option *long_opts; int os_parse_args(struct sandbox_state *state, int argc, char *argv[]) { - struct sb_cmdline_option **sb_opt = __u_boot_sandbox_option_start; + struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start; size_t num_options = __u_boot_sandbox_option_count(); size_t i; @@ -293,6 +341,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp) ret = -ENOMEM; goto done; } + next->next = NULL; strcpy(next->name, entry.d_name); switch (entry.d_type) { case DT_REG: @@ -318,6 +367,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp) done: closedir(dir); + free(fname); return ret; } @@ -336,7 +386,7 @@ const char *os_dirent_get_typename(enum os_dirent_t type) return os_dirent_typename[OS_FILET_UNKNOWN]; } -ssize_t os_get_filesize(const char *fname) +int os_get_filesize(const char *fname, loff_t *size) { struct stat buf; int ret; @@ -344,5 +394,146 @@ ssize_t os_get_filesize(const char *fname) ret = stat(fname, &buf); if (ret) return ret; - return buf.st_size; + *size = buf.st_size; + return 0; +} + +void os_putc(int ch) +{ + putchar(ch); +} + +void os_puts(const char *str) +{ + while (*str) + os_putc(*str++); +} + +int os_write_ram_buf(const char *fname) +{ + struct sandbox_state *state = state_get_current(); + int fd, ret; + + fd = open(fname, O_CREAT | O_WRONLY, 0777); + if (fd < 0) + return -ENOENT; + ret = write(fd, state->ram_buf, state->ram_size); + close(fd); + if (ret != state->ram_size) + return -EIO; + + return 0; +} + +int os_read_ram_buf(const char *fname) +{ + struct sandbox_state *state = state_get_current(); + int fd, ret; + loff_t size; + + ret = os_get_filesize(fname, &size); + if (ret < 0) + return ret; + if (size != state->ram_size) + return -ENOSPC; + fd = open(fname, O_RDONLY); + if (fd < 0) + return -ENOENT; + + ret = read(fd, state->ram_buf, state->ram_size); + close(fd); + if (ret != state->ram_size) + return -EIO; + + return 0; +} + +static int make_exec(char *fname, const void *data, int size) +{ + int fd; + + strcpy(fname, "/tmp/u-boot.jump.XXXXXX"); + fd = mkstemp(fname); + if (fd < 0) + return -ENOENT; + if (write(fd, data, size) < 0) + return -EIO; + close(fd); + if (chmod(fname, 0777)) + return -ENOEXEC; + + return 0; +} + +static int add_args(char ***argvp, const char *add_args[], int count) +{ + char **argv; + int argc; + + for (argv = *argvp, argc = 0; (*argvp)[argc]; argc++) + ; + + argv = malloc((argc + count + 1) * sizeof(char *)); + if (!argv) { + printf("Out of memory for %d argv\n", count); + return -ENOMEM; + } + memcpy(argv, *argvp, argc * sizeof(char *)); + memcpy(argv + argc, add_args, count * sizeof(char *)); + argv[argc + count] = NULL; + + *argvp = argv; + return 0; +} + +int os_jump_to_image(const void *dest, int size) +{ + struct sandbox_state *state = state_get_current(); + char fname[30], mem_fname[30]; + int fd, err; + const char *extra_args[5]; + char **argv = state->argv; +#ifdef DEBUG + int argc, i; +#endif + + err = make_exec(fname, dest, size); + if (err) + return err; + + strcpy(mem_fname, "/tmp/u-boot.mem.XXXXXX"); + fd = mkstemp(mem_fname); + if (fd < 0) + return -ENOENT; + close(fd); + err = os_write_ram_buf(mem_fname); + if (err) + return err; + + os_fd_restore(); + + extra_args[0] = "-j"; + extra_args[1] = fname; + extra_args[2] = "-m"; + extra_args[3] = mem_fname; + extra_args[4] = "--rm_memory"; + err = add_args(&argv, extra_args, + sizeof(extra_args) / sizeof(extra_args[0])); + if (err) + return err; + +#ifdef DEBUG + for (i = 0; argv[i]; i++) + printf("%d %s\n", i, argv[i]); +#endif + + if (state_uninit()) + os_exit(2); + + err = execv(fname, argv); + free(argv); + if (err) + return err; + + return unlink(fname); } diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c new file mode 100644 index 0000000000..18dc7edf19 --- /dev/null +++ b/arch/sandbox/cpu/sdl.c @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static struct sdl_info { + SDL_Surface *screen; + int width; + int height; + int depth; + int pitch; + uint frequency; + uint audio_pos; + uint audio_size; + uint8_t *audio_data; + bool audio_active; + bool inited; +} sdl; + +static void sandbox_sdl_poll_events(void) +{ + /* + * We don't want to include common.h in this file since it uses + * system headers. So add a declation here. + */ + extern void reset_cpu(unsigned long addr); + SDL_Event event; + + while (SDL_PollEvent(&event)) { + switch (event.type) { + case SDL_QUIT: + puts("LCD window closed - quitting\n"); + reset_cpu(1); + break; + } + } +} + +static int sandbox_sdl_ensure_init(void) +{ + if (!sdl.inited) { + if (SDL_Init(0) < 0) { + printf("Unable to initialize SDL: %s\n", + SDL_GetError()); + return -EIO; + } + + atexit(SDL_Quit); + + sdl.inited = true; + } + return 0; +} + +int sandbox_sdl_init_display(int width, int height, int log2_bpp) +{ + struct sandbox_state *state = state_get_current(); + int err; + + if (!width || !state->show_lcd) + return 0; + err = sandbox_sdl_ensure_init(); + if (err) + return err; + if (SDL_InitSubSystem(SDL_INIT_VIDEO) < 0) { + printf("Unable to initialize SDL LCD: %s\n", SDL_GetError()); + return -EPERM; + } + SDL_WM_SetCaption("U-Boot", "U-Boot"); + + sdl.width = width; + sdl.height = height; + sdl.depth = 1 << log2_bpp; + sdl.pitch = sdl.width * sdl.depth / 8; + sdl.screen = SDL_SetVideoMode(width, height, 0, 0); + sandbox_sdl_poll_events(); + + return 0; +} + +int sandbox_sdl_sync(void *lcd_base) +{ + SDL_Surface *frame; + + frame = SDL_CreateRGBSurfaceFrom(lcd_base, sdl.width, sdl.height, + sdl.depth, sdl.pitch, + 0x1f << 11, 0x3f << 5, 0x1f << 0, 0); + SDL_BlitSurface(frame, NULL, sdl.screen, NULL); + SDL_FreeSurface(frame); + SDL_UpdateRect(sdl.screen, 0, 0, 0, 0); + sandbox_sdl_poll_events(); + + return 0; +} + +#define NONE (-1) +#define NUM_SDL_CODES (SDLK_UNDO + 1) + +static int16_t sdl_to_keycode[NUM_SDL_CODES] = { + /* 0 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, KEY_BACKSPACE, KEY_TAB, + NONE, NONE, NONE, KEY_ENTER, NONE, + NONE, NONE, NONE, NONE, KEY_POWER, /* use PAUSE as POWER */ + + /* 20 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, KEY_ESC, NONE, NONE, + NONE, NONE, KEY_SPACE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 40 */ + NONE, NONE, NONE, NONE, KEY_COMMA, + KEY_MINUS, KEY_DOT, KEY_SLASH, KEY_0, KEY_1, + KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, + KEY_7, KEY_8, KEY_9, NONE, KEY_SEMICOLON, + + /* 60 */ + NONE, KEY_EQUAL, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 80 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, KEY_BACKSLASH, NONE, NONE, + NONE, KEY_GRAVE, KEY_A, KEY_B, KEY_C, + + /* 100 */ + KEY_D, KEY_E, KEY_F, KEY_G, KEY_H, + KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, + KEY_N, KEY_O, KEY_P, KEY_Q, KEY_R, + KEY_S, KEY_T, KEY_U, KEY_V, KEY_W, + + /* 120 */ + KEY_X, KEY_Y, KEY_Z, NONE, NONE, + NONE, NONE, KEY_DELETE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 140 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 160 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 180 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 200 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 220 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 240 */ + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, + NONE, KEY_KP0, KEY_KP1, KEY_KP2, KEY_KP3, + + /* 260 */ + KEY_KP4, KEY_KP5, KEY_KP6, KEY_KP7, KEY_KP8, + KEY_KP9, KEY_KPDOT, KEY_KPSLASH, KEY_KPASTERISK, KEY_KPMINUS, + KEY_KPPLUS, KEY_KPENTER, KEY_KPEQUAL, KEY_UP, KEY_DOWN, + KEY_RIGHT, KEY_LEFT, KEY_INSERT, KEY_HOME, KEY_END, + + /* 280 */ + KEY_PAGEUP, KEY_PAGEDOWN, KEY_F1, KEY_F2, KEY_F3, + KEY_F4, KEY_F5, KEY_F6, KEY_F7, KEY_F8, + KEY_F9, KEY_F10, KEY_F11, KEY_F12, NONE, + NONE, NONE, NONE, NONE, NONE, + + /* 300 */ + KEY_NUMLOCK, KEY_CAPSLOCK, KEY_SCROLLLOCK, KEY_RIGHTSHIFT, + KEY_LEFTSHIFT, + KEY_RIGHTCTRL, KEY_LEFTCTRL, KEY_RIGHTALT, KEY_LEFTALT, KEY_RIGHTMETA, + KEY_LEFTMETA, NONE, KEY_FN, NONE, KEY_COMPOSE, + NONE, KEY_PRINT, KEY_SYSRQ, KEY_PAUSE, NONE, + + /* 320 */ + NONE, NONE, NONE, +}; + +int sandbox_sdl_scan_keys(int key[], int max_keys) +{ + Uint8 *keystate; + int i, count; + + sandbox_sdl_poll_events(); + keystate = SDL_GetKeyState(NULL); + for (i = count = 0; i < NUM_SDL_CODES; i++) { + if (count >= max_keys) + break; + else if (keystate[i]) + key[count++] = sdl_to_keycode[i]; + } + + return count; +} + +int sandbox_sdl_key_pressed(int keycode) +{ + int key[8]; /* allow up to 8 keys to be pressed at once */ + int count; + int i; + + count = sandbox_sdl_scan_keys(key, sizeof(key) / sizeof(key[0])); + for (i = 0; i < count; i++) { + if (key[i] == keycode) + return 0; + } + + return -ENOENT; +} + +void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len) +{ + int avail; + + avail = sdl.audio_size - sdl.audio_pos; + if (avail < len) + len = avail; + + SDL_MixAudio(stream, sdl.audio_data + sdl.audio_pos, len, + SDL_MIX_MAXVOLUME); + sdl.audio_pos += len; + + /* Loop if we are at the end */ + if (sdl.audio_pos == sdl.audio_size) + sdl.audio_pos = 0; +} + +int sandbox_sdl_sound_init(void) +{ + SDL_AudioSpec wanted; + + if (sandbox_sdl_ensure_init()) + return -1; + + if (sdl.audio_active) + return 0; + + /* + * At present all sandbox sounds crash. This is probably due to + * symbol name conflicts with U-Boot. We can remove the malloc() + * probles with: + * + * #define USE_DL_PREFIX + * + * and get this: + * + * Assertion 'e->pollfd->fd == e->fd' failed at pulse/mainloop.c:676, + * function dispatch_pollfds(). Aborting. + * + * The right solution is probably to make U-Boot's names private or + * link os.c and sdl.c against their libraries before liking with + * U-Boot. TBD. For now sound is disabled. + */ + printf("(Warning: sandbox sound disabled)\n"); + return 0; + + /* Set the audio format */ + wanted.freq = 22050; + wanted.format = AUDIO_S16; + wanted.channels = 1; /* 1 = mono, 2 = stereo */ + wanted.samples = 1024; /* Good low-latency value for callback */ + wanted.callback = sandbox_sdl_fill_audio; + wanted.userdata = NULL; + + sdl.audio_size = sizeof(uint16_t) * wanted.freq; + sdl.audio_data = malloc(sdl.audio_size); + if (!sdl.audio_data) { + printf("%s: Out of memory\n", __func__); + return -1; + } + sdl.audio_pos = 0; + + if (SDL_InitSubSystem(SDL_INIT_AUDIO) < 0) { + printf("Unable to initialize SDL audio: %s\n", SDL_GetError()); + goto err; + } + + /* Open the audio device, forcing the desired format */ + if (SDL_OpenAudio(&wanted, NULL) < 0) { + printf("Couldn't open audio: %s\n", SDL_GetError()); + goto err; + } + sdl.audio_active = true; + + return 0; + +err: + free(sdl.audio_data); + return -1; +} + +int sandbox_sdl_sound_start(uint frequency) +{ + if (!sdl.audio_active) + return -1; + sdl.frequency = frequency; + sound_create_square_wave((unsigned short *)sdl.audio_data, + sdl.audio_size, frequency); + sdl.audio_pos = 0; + SDL_PauseAudio(0); + + return 0; +} + +int sandbox_sdl_sound_stop(void) +{ + if (!sdl.audio_active) + return -1; + SDL_PauseAudio(1); + + return 0; +} diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index f1cb7930b1..097f29a290 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -4,16 +4,20 @@ */ #include +#include +#include +#include #include +#include #include #include -#include +DECLARE_GLOBAL_DATA_PTR; int sandbox_early_getopt_check(void) { struct sandbox_state *state = state_get_current(); - struct sb_cmdline_option **sb_opt = __u_boot_sandbox_option_start; + struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start; size_t num_options = __u_boot_sandbox_option_count(); size_t i; int max_arg_len, max_noarg_len; @@ -36,11 +40,11 @@ int sandbox_early_getopt_check(void) max_arg_len = 0; for (i = 0; i < num_options; ++i) - max_arg_len = max(strlen(sb_opt[i]->flag), max_arg_len); + max_arg_len = max((int)strlen(sb_opt[i]->flag), max_arg_len); max_noarg_len = max_arg_len + 7; for (i = 0; i < num_options; ++i) { - struct sb_cmdline_option *opt = sb_opt[i]; + struct sandbox_cmdline_option *opt = sb_opt[i]; /* first output the short flag if it has one */ if (opt->flag_short >= 0x100) @@ -50,9 +54,9 @@ int sandbox_early_getopt_check(void) /* then the long flag */ if (opt->has_arg) - printf("--%-*s", max_noarg_len, opt->flag); - else printf("--%-*s ", max_arg_len, opt->flag); + else + printf("--%-*s", max_noarg_len, opt->flag); /* finally the help text */ printf(" %s\n", opt->help); @@ -61,12 +65,12 @@ int sandbox_early_getopt_check(void) os_exit(0); } -static int sb_cmdline_cb_help(struct sandbox_state *state, const char *arg) +static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg) { /* just flag to sandbox_early_getopt_check to show usage */ return 1; } -SB_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help"); +SANDBOX_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help"); int sandbox_main_loop_init(void) { @@ -74,46 +78,205 @@ int sandbox_main_loop_init(void) /* Execute command if required */ if (state->cmd) { + cli_init(); + run_command_list(state->cmd, -1, 0); - os_exit(state->exit_type); + if (!state->interactive) + os_exit(state->exit_type); } return 0; } -static int sb_cmdline_cb_command(struct sandbox_state *state, const char *arg) +static int sandbox_cmdline_cb_command(struct sandbox_state *state, + const char *arg) { state->cmd = arg; return 0; } -SB_CMDLINE_OPT_SHORT(command, 'c', 1, "Execute U-Boot command"); +SANDBOX_CMDLINE_OPT_SHORT(command, 'c', 1, "Execute U-Boot command"); -static int sb_cmdline_cb_fdt(struct sandbox_state *state, const char *arg) +static int sandbox_cmdline_cb_fdt(struct sandbox_state *state, const char *arg) { state->fdt_fname = arg; return 0; } -SB_CMDLINE_OPT_SHORT(fdt, 'd', 1, "Specify U-Boot's control FDT"); +SANDBOX_CMDLINE_OPT_SHORT(fdt, 'd', 1, "Specify U-Boot's control FDT"); -int main(int argc, char *argv[]) +static int sandbox_cmdline_cb_default_fdt(struct sandbox_state *state, + const char *arg) +{ + const char *fmt = "%s.dtb"; + char *fname; + int len; + + len = strlen(state->argv[0]) + strlen(fmt) + 1; + fname = os_malloc(len); + if (!fname) + return -ENOMEM; + snprintf(fname, len, fmt, state->argv[0]); + state->fdt_fname = fname; + + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(default_fdt, 'D', 0, + "Use the default u-boot.dtb control FDT in U-Boot directory"); + +static int sandbox_cmdline_cb_interactive(struct sandbox_state *state, + const char *arg) +{ + state->interactive = true; + return 0; +} + +SANDBOX_CMDLINE_OPT_SHORT(interactive, 'i', 0, "Enter interactive mode"); + +static int sandbox_cmdline_cb_jump(struct sandbox_state *state, + const char *arg) +{ + /* Remember to delete this U-Boot image later */ + state->jumped_fname = arg; + + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(jump, 'j', 1, "Jumped from previous U-Boot"); + +static int sandbox_cmdline_cb_memory(struct sandbox_state *state, + const char *arg) { - struct sandbox_state *state; int err; - err = state_init(); - if (err) + /* For now assume we always want to write it */ + state->write_ram_buf = true; + state->ram_buf_fname = arg; + + err = os_read_ram_buf(arg); + if (err) { + printf("Failed to read RAM buffer\n"); return err; + } + + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(memory, 'm', 1, + "Read/write ram_buf memory contents from file"); + +static int sandbox_cmdline_cb_rm_memory(struct sandbox_state *state, + const char *arg) +{ + state->ram_buf_rm = true; + + return 0; +} +SANDBOX_CMDLINE_OPT(rm_memory, 0, "Remove memory file after reading"); + +static int sandbox_cmdline_cb_state(struct sandbox_state *state, + const char *arg) +{ + state->state_fname = arg; + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(state, 's', 1, "Specify the sandbox state FDT"); + +static int sandbox_cmdline_cb_read(struct sandbox_state *state, + const char *arg) +{ + state->read_state = true; + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(read, 'r', 0, "Read the state FDT on startup"); + +static int sandbox_cmdline_cb_write(struct sandbox_state *state, + const char *arg) +{ + state->write_state = true; + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(write, 'w', 0, "Write state FDT on exit"); + +static int sandbox_cmdline_cb_ignore_missing(struct sandbox_state *state, + const char *arg) +{ + state->ignore_missing_state_on_read = true; + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(ignore_missing, 'n', 0, + "Ignore missing state on read"); + +static int sandbox_cmdline_cb_show_lcd(struct sandbox_state *state, + const char *arg) +{ + state->show_lcd = true; + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(show_lcd, 'l', 0, + "Show the sandbox LCD display"); + +static const char *term_args[STATE_TERM_COUNT] = { + "raw-with-sigs", + "raw", + "cooked", +}; + +static int sandbox_cmdline_cb_terminal(struct sandbox_state *state, + const char *arg) +{ + int i; + + for (i = 0; i < STATE_TERM_COUNT; i++) { + if (!strcmp(arg, term_args[i])) { + state->term_raw = i; + return 0; + } + } + + printf("Unknown terminal setting '%s' (", arg); + for (i = 0; i < STATE_TERM_COUNT; i++) + printf("%s%s", i ? ", " : "", term_args[i]); + puts(")\n"); + + return 1; +} +SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1, + "Set terminal to raw/cooked mode"); + +int main(int argc, char *argv[]) +{ + struct sandbox_state *state; + gd_t data; + int ret; + + ret = state_init(); + if (ret) + goto err; state = state_get_current(); if (os_parse_args(state, argc, argv)) return 1; - /* - * Do pre- and post-relocation init, then start up U-Boot. This will - * never return. - */ + ret = sandbox_read_state(state, state->state_fname); + if (ret) + goto err; + + /* Remove old memory file if required */ + if (state->ram_buf_rm && state->ram_buf_fname) + os_unlink(state->ram_buf_fname); + + memset(&data, '\0', sizeof(data)); + gd = &data; +#ifdef CONFIG_SYS_MALLOC_F_LEN + gd->malloc_base = CONFIG_MALLOC_F_ADDR; +#endif + + /* Do pre- and post-relocation init */ board_init_f(0); - /* NOTREACHED - board_init_f() does not return */ + board_init_r(gd->new_gd, 0); + + /* NOTREACHED - board_init_r() does not return */ return 0; + +err: + printf("Error %d\n", ret); + return 1; } diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 56d5041411..ba73b7e251 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -4,6 +4,9 @@ */ #include +#include +#include +#include #include /* Main state record for the sandbox */ @@ -15,6 +18,324 @@ void state_record_exit(enum exit_type_id exit_type) state->exit_type = exit_type; } +static int state_ensure_space(int extra_size) +{ + void *blob = state->state_fdt; + int used, size, free; + void *buf; + int ret; + + used = fdt_off_dt_strings(blob) + fdt_size_dt_strings(blob); + size = fdt_totalsize(blob); + free = size - used; + if (free > extra_size) + return 0; + + size = used + extra_size; + buf = os_malloc(size); + if (!buf) + return -ENOMEM; + + ret = fdt_open_into(blob, buf, size); + if (ret) { + os_free(buf); + return -EIO; + } + + os_free(blob); + state->state_fdt = buf; + return 0; +} + +static int state_read_file(struct sandbox_state *state, const char *fname) +{ + loff_t size; + int ret; + int fd; + + ret = os_get_filesize(fname, &size); + if (ret < 0) { + printf("Cannot find sandbox state file '%s'\n", fname); + return ret; + } + state->state_fdt = os_malloc(size); + if (!state->state_fdt) { + puts("No memory to read sandbox state\n"); + return -ENOMEM; + } + fd = os_open(fname, OS_O_RDONLY); + if (fd < 0) { + printf("Cannot open sandbox state file '%s'\n", fname); + ret = -EPERM; + goto err_open; + } + if (os_read(fd, state->state_fdt, size) != size) { + printf("Cannot read sandbox state file '%s'\n", fname); + ret = -EIO; + goto err_read; + } + os_close(fd); + + return 0; +err_read: + os_close(fd); +err_open: + os_free(state->state_fdt); + state->state_fdt = NULL; + + return ret; +} + +/*** + * sandbox_read_state_nodes() - Read state associated with a driver + * + * This looks through all compatible nodes and calls the read function on + * each one, to read in the state. + * + * If nothing is found, it still calls the read function once, to set up a + * single global state for that driver. + * + * @state: Sandbox state + * @io: Method to use for reading state + * @blob: FDT containing state + * @return 0 if OK, -EINVAL if the read function returned failure + */ +int sandbox_read_state_nodes(struct sandbox_state *state, + struct sandbox_state_io *io, const void *blob) +{ + int count; + int node; + int ret; + + debug(" - read %s\n", io->name); + if (!io->read) + return 0; + + node = -1; + count = 0; + while (blob) { + node = fdt_node_offset_by_compatible(blob, node, io->compat); + if (node < 0) + return 0; /* No more */ + debug(" - read node '%s'\n", fdt_get_name(blob, node, NULL)); + ret = io->read(blob, node); + if (ret) { + printf("Unable to read state for '%s'\n", io->compat); + return -EINVAL; + } + count++; + } + + /* + * If we got no saved state, call the read function once without a + * node, to set up the global state. + */ + if (count == 0) { + debug(" - read global\n"); + ret = io->read(NULL, -1); + if (ret) { + printf("Unable to read global state for '%s'\n", + io->name); + return -EINVAL; + } + } + + return 0; +} + +int sandbox_read_state(struct sandbox_state *state, const char *fname) +{ + struct sandbox_state_io *io; + const void *blob; + bool got_err; + int ret; + + if (state->read_state && fname) { + ret = state_read_file(state, fname); + if (ret == -ENOENT && state->ignore_missing_state_on_read) + ret = 0; + if (ret) + return ret; + } + + /* Call all the state read funtcions */ + got_err = false; + blob = state->state_fdt; + io = ll_entry_start(struct sandbox_state_io, state_io); + for (; io < ll_entry_end(struct sandbox_state_io, state_io); io++) { + ret = sandbox_read_state_nodes(state, io, blob); + if (ret < 0) + got_err = true; + } + + if (state->read_state && fname) { + debug("Read sandbox state from '%s'%s\n", fname, + got_err ? " (with errors)" : ""); + } + + return got_err ? -1 : 0; +} + +/*** + * sandbox_write_state_node() - Write state associated with a driver + * + * This calls the write function to write out global state for that driver. + * + * TODO(sjg@chromium.org): Support writing out state from multiple drivers + * of the same time. We don't need this yet,and it will be much easier to + * do when driver model is available. + * + * @state: Sandbox state + * @io: Method to use for writing state + * @return 0 if OK, -EIO if there is a fatal error (such as out of space + * for adding the data), -EINVAL if the write function failed. + */ +int sandbox_write_state_node(struct sandbox_state *state, + struct sandbox_state_io *io) +{ + void *blob; + int node; + int ret; + + if (!io->write) + return 0; + + ret = state_ensure_space(SANDBOX_STATE_MIN_SPACE); + if (ret) { + printf("Failed to add more space for state\n"); + return -EIO; + } + + /* The blob location can change when the size increases */ + blob = state->state_fdt; + node = fdt_node_offset_by_compatible(blob, -1, io->compat); + if (node == -FDT_ERR_NOTFOUND) { + node = fdt_add_subnode(blob, 0, io->name); + if (node < 0) { + printf("Cannot create node '%s': %s\n", io->name, + fdt_strerror(node)); + return -EIO; + } + + if (fdt_setprop_string(blob, node, "compatible", io->compat)) { + puts("Cannot set compatible\n"); + return -EIO; + } + } else if (node < 0) { + printf("Cannot access node '%s': %s\n", io->name, + fdt_strerror(node)); + return -EIO; + } + debug("Write state for '%s' to node %d\n", io->compat, node); + ret = io->write(blob, node); + if (ret) { + printf("Unable to write state for '%s'\n", io->compat); + return -EINVAL; + } + + return 0; +} + +int sandbox_write_state(struct sandbox_state *state, const char *fname) +{ + struct sandbox_state_io *io; + bool got_err; + int size; + int ret; + int fd; + + /* Create a state FDT if we don't have one */ + if (!state->state_fdt) { + size = 0x4000; + state->state_fdt = os_malloc(size); + if (!state->state_fdt) { + puts("No memory to create FDT\n"); + return -ENOMEM; + } + ret = fdt_create_empty_tree(state->state_fdt, size); + if (ret < 0) { + printf("Cannot create empty state FDT: %s\n", + fdt_strerror(ret)); + ret = -EIO; + goto err_create; + } + } + + /* Call all the state write funtcions */ + got_err = false; + io = ll_entry_start(struct sandbox_state_io, state_io); + ret = 0; + for (; io < ll_entry_end(struct sandbox_state_io, state_io); io++) { + ret = sandbox_write_state_node(state, io); + if (ret == -EIO) + break; + else if (ret) + got_err = true; + } + + if (ret == -EIO) { + printf("Could not write sandbox state\n"); + goto err_create; + } + + ret = fdt_pack(state->state_fdt); + if (ret < 0) { + printf("Cannot pack state FDT: %s\n", fdt_strerror(ret)); + ret = -EINVAL; + goto err_create; + } + size = fdt_totalsize(state->state_fdt); + fd = os_open(fname, OS_O_WRONLY | OS_O_CREAT); + if (fd < 0) { + printf("Cannot open sandbox state file '%s'\n", fname); + ret = -EIO; + goto err_create; + } + if (os_write(fd, state->state_fdt, size) != size) { + printf("Cannot write sandbox state file '%s'\n", fname); + ret = -EIO; + goto err_write; + } + os_close(fd); + + debug("Wrote sandbox state to '%s'%s\n", fname, + got_err ? " (with errors)" : ""); + + return 0; +err_write: + os_close(fd); +err_create: + os_free(state->state_fdt); + + return ret; +} + +int state_setprop(int node, const char *prop_name, const void *data, int size) +{ + void *blob; + int len; + int ret; + + fdt_getprop(state->state_fdt, node, prop_name, &len); + + /* Add space for the new property, its name and some overhead */ + ret = state_ensure_space(size - len + strlen(prop_name) + 32); + if (ret) + return ret; + + /* This should succeed, barring a mutiny */ + blob = state->state_fdt; + ret = fdt_setprop(blob, node, prop_name, data, size); + if (ret) { + printf("%s: Unable to set property '%s' in node '%s': %s\n", + __func__, prop_name, fdt_get_name(blob, node, NULL), + fdt_strerror(ret)); + return -ENOSPC; + } + + return 0; +} + struct sandbox_state *state_get_current(void) { assert(state); @@ -25,6 +346,10 @@ int state_init(void) { state = &main_state; + state->ram_size = CONFIG_SYS_SDRAM_SIZE; + state->ram_buf = os_malloc(state->ram_size); + assert(state->ram_buf); + /* * Example of how to use GPIOs: * @@ -33,3 +358,35 @@ int state_init(void) */ return 0; } + +int state_uninit(void) +{ + int err; + + state = &main_state; + + if (state->write_ram_buf && !state->ram_buf_rm) { + err = os_write_ram_buf(state->ram_buf_fname); + if (err) { + printf("Failed to write RAM buffer\n"); + return err; + } + } + + if (state->write_state) { + if (sandbox_write_state(state, state->state_fname)) { + printf("Failed to write sandbox state\n"); + return -1; + } + } + + /* Delete this at the last moment so as not to upset gdb too much */ + if (state->jumped_fname) + os_unlink(state->jumped_fname); + + if (state->state_fdt) + os_free(state->state_fdt); + memset(state, '\0', sizeof(*state)); + + return 0; +} diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds index 615c5567c3..7e92b4ac66 100644 --- a/arch/sandbox/cpu/u-boot.lds +++ b/arch/sandbox/cpu/u-boot.lds @@ -3,7 +3,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ SECTIONS diff --git a/arch/sandbox/dts/.gitignore b/arch/sandbox/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/sandbox/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile new file mode 100644 index 0000000000..a4c980b235 --- /dev/null +++ b/arch/sandbox/dts/Makefile @@ -0,0 +1,11 @@ +dtb-$(CONFIG_SANDBOX) += sandbox.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/sandbox/dts/include/dt-bindings b/arch/sandbox/dts/include/dt-bindings new file mode 120000 index 0000000000..0cecb3d080 --- /dev/null +++ b/arch/sandbox/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings \ No newline at end of file diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts new file mode 100644 index 0000000000..9ce31bf075 --- /dev/null +++ b/arch/sandbox/dts/sandbox.dts @@ -0,0 +1,184 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <0>; + + chosen { + stdout-path = "/serial"; + }; + + /* Needs to be available prior to relocation */ + uart0: serial { + compatible = "sandbox,serial"; + sandbox,text-colour = "cyan"; + }; + + triangle { + compatible = "demo-shape"; + colour = "cyan"; + sides = <3>; + character = <83>; + light-gpios = <&gpio_a 2>, <&gpio_b 6 0>; + }; + square { + compatible = "demo-shape"; + colour = "blue"; + sides = <4>; + }; + hexagon { + compatible = "demo-simple"; + colour = "white"; + sides = <6>; + }; + + host@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sandbox,host-emulation"; + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + #address-cells = <1>; + #size-cells = <1>; + + /* Information for sandbox */ + ro { + reg = <0 0xf000>; + }; + wp-ro { + reg = <0xf000 0x1000>; + }; + rw { + reg = <0x10000 0x10000>; + }; + }; + }; + }; + + lcd { + compatible = "sandbox,lcd-sdl"; + xres = <800>; + yres = <600>; + }; + + cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,ghost-filter; + /* + * Keymap entries take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * The values below are for a US keyboard layout and + * are taken from the Linux driver. Note that the + * 102ND key is not used for US keyboards. + */ + linux,keymap = < + /* CAPSLCK F1 B F10 */ + 0x0001003a 0x0002003b 0x00030030 0x00040044 + /* N = R_ALT ESC */ + 0x00060031 0x0008000d 0x000a0064 0x01010001 + /* F4 G F7 H */ + 0x0102003e 0x01030022 0x01040041 0x01060023 + /* ' F9 BKSPACE L_CTRL */ + 0x01080028 0x01090043 0x010b000e 0x0200001d + /* TAB F3 T F6 */ + 0x0201000f 0x0202003d 0x02030014 0x02040040 + /* ] Y 102ND [ */ + 0x0205001b 0x02060015 0x02070056 0x0208001a + /* F8 GRAVE F2 5 */ + 0x02090042 0x03010029 0x0302003c 0x03030006 + /* F5 6 - \ */ + 0x0304003f 0x03060007 0x0308000c 0x030b002b + /* R_CTRL A D F */ + 0x04000061 0x0401001e 0x04020020 0x04030021 + /* S K J ; */ + 0x0404001f 0x04050025 0x04060024 0x04080027 + /* L ENTER Z C */ + 0x04090026 0x040b001c 0x0501002c 0x0502002e + /* V X , M */ + 0x0503002f 0x0504002d 0x05050033 0x05060032 + /* L_SHIFT / . SPACE */ + 0x0507002a 0x05080035 0x05090034 0x050B0039 + /* 1 3 4 2 */ + 0x06010002 0x06020004 0x06030005 0x06040003 + /* 8 7 0 9 */ + 0x06050009 0x06060008 0x0608000b 0x0609000a + /* L_ALT DOWN RIGHT Q */ + 0x060a0038 0x060b006c 0x060c006a 0x07010010 + /* E R W I */ + 0x07020012 0x07030013 0x07040011 0x07050017 + /* U R_SHIFT P O */ + 0x07060016 0x07070036 0x07080019 0x07090018 + /* UP LEFT */ + 0x070b0067 0x070c0069>; + }; + + gpio_a: gpios@0 { + gpio-controller; + compatible = "sandbox,gpio"; + #gpio-cells = <1>; + gpio-bank-name = "a"; + num-gpios = <20>; + }; + + gpio_b: gpios@1 { + gpio-controller; + compatible = "sandbox,gpio"; + #gpio-cells = <2>; + gpio-bank-name = "b"; + num-gpios = <10>; + }; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + compatible = "sandbox,i2c"; + clock-frequency = <400000>; + eeprom@2c { + reg = <0x2c>; + compatible = "i2c-eeprom"; + emul { + compatible = "sandbox,i2c-eeprom"; + sandbox,filename = "i2c.bin"; + sandbox,size = <128>; + }; + }; + }; + + spi@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + compatible = "sandbox,spi"; + cs-gpios = <0>, <&gpio_a 0>; + flash@0 { + reg = <0>; + compatible = "spansion,m25p16", "sandbox,spi-flash"; + spi-max-frequency = <40000000>; + sandbox,filename = "spi.bin"; + }; + }; + + cros-ec@0 { + compatible = "google,cros-ec"; + #address-cells = <1>; + #size-cells = <1>; + firmware_storage_spi: flash@0 { + reg = <0 0x400000>; + }; + }; + +}; diff --git a/arch/sandbox/include/asm/bitops.h b/arch/sandbox/include/asm/bitops.h index 74219c56a7..e807c4ef34 100644 --- a/arch/sandbox/include/asm/bitops.h +++ b/arch/sandbox/include/asm/bitops.h @@ -17,6 +17,7 @@ #ifndef __ASM_SANDBOX_BITOPS_H #define __ASM_SANDBOX_BITOPS_H +#include #include #ifdef __KERNEL__ @@ -53,7 +54,7 @@ static inline int __test_and_set_bit(int nr, void *addr) static inline int test_and_set_bit(int nr, void *addr) { - unsigned long flags; + unsigned long __always_unused flags; int out; local_irq_save(flags); @@ -75,7 +76,7 @@ static inline int __test_and_clear_bit(int nr, void *addr) static inline int test_and_clear_bit(int nr, void *addr) { - unsigned long flags; + unsigned long __always_unused flags; int out; local_irq_save(flags); diff --git a/arch/sandbox/include/asm/byteorder.h b/arch/sandbox/include/asm/byteorder.h index ca1cb816ca..ba3c1643d9 100644 --- a/arch/sandbox/include/asm/byteorder.h +++ b/arch/sandbox/include/asm/byteorder.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_SANDBOX_BYTEORDER_H diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h index 7755a4deff..ec7729eb4c 100644 --- a/arch/sandbox/include/asm/config.h +++ b/arch/sandbox/include/asm/config.h @@ -9,4 +9,12 @@ #define CONFIG_SANDBOX_ARCH +/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */ +#ifndef CONFIG_SANDBOX_SPI_MAX_BUS +#define CONFIG_SANDBOX_SPI_MAX_BUS 1 +#endif +#ifndef CONFIG_SANDBOX_SPI_MAX_CS +#define CONFIG_SANDBOX_SPI_MAX_CS 10 +#endif + #endif diff --git a/arch/sandbox/include/asm/getopt.h b/arch/sandbox/include/asm/getopt.h index 685883cd3f..3048c2cc30 100644 --- a/arch/sandbox/include/asm/getopt.h +++ b/arch/sandbox/include/asm/getopt.h @@ -18,7 +18,7 @@ struct sandbox_state; * consumer code should focus on the macros below and * the callback function. */ -struct sb_cmdline_option { +struct sandbox_cmdline_option { /* The long flag name: "help" for "--help" */ const char *flag; /* The (optional) short flag name: "h" for "-h" */ @@ -35,18 +35,19 @@ struct sb_cmdline_option { * Internal macro to expand the lower macros into the necessary * magic junk that makes this all work. */ -#define _SB_CMDLINE_OPT(f, s, ha, h) \ - static struct sb_cmdline_option sb_cmdline_option_##f = { \ +#define _SANDBOX_CMDLINE_OPT(f, s, ha, h) \ + static struct sandbox_cmdline_option sandbox_cmdline_option_##f = { \ .flag = #f, \ .flag_short = s, \ .help = h, \ .has_arg = ha, \ - .callback = sb_cmdline_cb_##f, \ + .callback = sandbox_cmdline_cb_##f, \ }; \ /* Ppointer to the struct in a special section for the linker script */ \ static __attribute__((section(".u_boot_sandbox_getopt"), used)) \ - struct sb_cmdline_option *sb_cmdline_option_##f##_ptr = \ - &sb_cmdline_option_##f + struct sandbox_cmdline_option \ + *sandbox_cmdline_option_##f##_ptr = \ + &sandbox_cmdline_option_##f /** * Macros for end code to declare new command line flags. @@ -56,16 +57,16 @@ struct sb_cmdline_option { * @param h The help string displayed when showing --help * * This invocation: - * SB_CMDLINE_OPT(foo, 0, "The foo arg"); + * SANDBOX_CMDLINE_OPT(foo, 0, "The foo arg"); * Will create a new flag named "--foo" (no short option) that takes * no argument. If the user specifies "--foo", then the callback func - * sb_cmdline_cb_foo() will automatically be called. + * sandbox_cmdline_cb_foo() will automatically be called. */ -#define SB_CMDLINE_OPT(f, ha, h) _SB_CMDLINE_OPT(f, 0, ha, h) +#define SANDBOX_CMDLINE_OPT(f, ha, h) _SANDBOX_CMDLINE_OPT(f, 0, ha, h) /* * Same as above, but @s is used to specify a short flag e.g. - * SB_CMDLINE_OPT(foo, 'f', 0, "The foo arg"); + * SANDBOX_CMDLINE_OPT(foo, 'f', 0, "The foo arg"); */ -#define SB_CMDLINE_OPT_SHORT(f, s, ha, h) _SB_CMDLINE_OPT(f, s, ha, h) +#define SANDBOX_CMDLINE_OPT_SHORT(f, s, ha, h) _SANDBOX_CMDLINE_OPT(f, s, ha, h) #endif diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index d70532aa4d..b2e9b488f1 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -12,7 +12,7 @@ /* Architecture-specific global data */ struct arch_global_data { - u8 *ram_buf; /* emulated RAM buffer */ + uint8_t *ram_buf; /* emulated RAM buffer */ }; #include diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h index afb9c7842f..8317db1ad3 100644 --- a/arch/sandbox/include/asm/gpio.h +++ b/arch/sandbox/include/asm/gpio.h @@ -29,7 +29,7 @@ * @param gp GPIO number * @return -1 on error, 0 if GPIO is low, >0 if high */ -int sandbox_gpio_get_value(unsigned gp); +int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset); /** * Set the simulated value of a GPIO (used only in sandbox test code) @@ -38,7 +38,7 @@ int sandbox_gpio_get_value(unsigned gp); * @param value value to set (0 for low, non-zero for high) * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_value(unsigned gp, int value); +int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value); /** * Return the simulated direction of a GPIO (used only in sandbox test code) @@ -46,7 +46,7 @@ int sandbox_gpio_set_value(unsigned gp, int value); * @param gp GPIO number * @return -1 on error, 0 if GPIO is input, >0 if output */ -int sandbox_gpio_get_direction(unsigned gp); +int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset); /** * Set the simulated direction of a GPIO (used only in sandbox test code) @@ -55,11 +55,7 @@ int sandbox_gpio_get_direction(unsigned gp); * @param output 0 to set as input, 1 to set as output * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_direction(unsigned gp, int output); - -/* Display information about each GPIO */ -void gpio_info(void); - -#define gpio_status() gpio_info() +int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, + int output); #endif diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 0f41864682..895fcb872f 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SANDBOX_ASM_IO_H @@ -38,6 +38,16 @@ static inline void unmap_sysmem(const void *vaddr) } /* Map from a pointer to our RAM buffer */ -phys_addr_t map_to_sysmem(void *ptr); +phys_addr_t map_to_sysmem(const void *ptr); + +/* Define nops for sandbox I/O access */ +#define readb(addr) 0 +#define readw(addr) 0 +#define readl(addr) 0 +#define writeb(v, addr) +#define writew(v, addr) +#define writel(v, addr) + +#include #endif diff --git a/arch/sandbox/include/asm/ptrace.h b/arch/sandbox/include/asm/ptrace.h index 4d651cfb65..e9f552f4ae 100644 --- a/arch/sandbox/include/asm/ptrace.h +++ b/arch/sandbox/include/asm/ptrace.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_SANDBOX_PTRACE_H diff --git a/arch/sandbox/include/asm/sdl.h b/arch/sandbox/include/asm/sdl.h new file mode 100644 index 0000000000..6edec1acfa --- /dev/null +++ b/arch/sandbox/include/asm/sdl.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SANDBOX_SDL_H +#define __SANDBOX_SDL_H + +#include + +#ifdef CONFIG_SANDBOX_SDL + +/** + * sandbox_sdl_init_display() - Set up SDL video ready for use + * + * @width: Window width in pixels + * @height Window height in pixels + * @log2_bpp: Log to base 2 of the number of bits per pixel. So a 32bpp + * display will pass 5, since 2*5 = 32 + * @return 0 if OK, -ENODEV if no device, -EIO if SDL failed to initialize + * and -EPERM if the video failed to come up. + */ +int sandbox_sdl_init_display(int width, int height, int log2_bpp); + +/** + * sandbox_sdl_sync() - Sync current U-Boot LCD frame buffer to SDL + * + * This must be called periodically to update the screen for SDL so that the + * user can see it. + * + * @lcd_base: Base of frame buffer + * @return 0 if screen was updated, -ENODEV is there is no screen. + */ +int sandbox_sdl_sync(void *lcd_base); + +/** + * sandbox_sdl_scan_keys() - scan for pressed keys + * + * Works out which keys are pressed and returns a list + * + * @key: Array to receive keycodes + * @max_keys: Size of array + * @return number of keycodes found, 0 if none, -ENODEV if no keyboard + */ +int sandbox_sdl_scan_keys(int key[], int max_keys); + +/** + * sandbox_sdl_key_pressed() - check if a particular key is pressed + * + * @keycode: Keycode to check (KEY_... - see include/linux/input.h + * @return 0 if pressed, -ENOENT if not pressed. -ENODEV if keybord not + * available, + */ +int sandbox_sdl_key_pressed(int keycode); + +/** + * sandbox_sdl_sound_start() - start playing a sound + * + * @frequency: Frequency of sounds in Hertz + * @return 0 if OK, -ENODEV if no sound is available + */ +int sandbox_sdl_sound_start(uint frequency); + +/** + * sandbox_sdl_sound_stop() - stop playing a sound + * + * @return 0 if OK, -ENODEV if no sound is available + */ +int sandbox_sdl_sound_stop(void); + +/** + * sandbox_sdl_sound_init() - set up the sound system + * + * @return 0 if OK, -ENODEV if no sound is available + */ +int sandbox_sdl_sound_init(void); + +#else +static inline int sandbox_sdl_init_display(int width, int height, + int log2_bpp) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_sync(void *lcd_base) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_scan_keys(int key[], int max_keys) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_key_pressed(int keycode) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_sound_start(uint frequency) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_sound_stop(void) +{ + return -ENODEV; +} + +static inline int sandbox_sdl_sound_init(void) +{ + return -ENODEV; +} + +#endif + +#endif diff --git a/arch/sandbox/include/asm/sections.h b/arch/sandbox/include/asm/sections.h index 4c378600b0..fbc1bd11a3 100644 --- a/arch/sandbox/include/asm/sections.h +++ b/arch/sandbox/include/asm/sections.h @@ -11,9 +11,9 @@ #include -struct sb_cmdline_option; +struct sandbox_cmdline_option; -extern struct sb_cmdline_option *__u_boot_sandbox_option_start[], +extern struct sandbox_cmdline_option *__u_boot_sandbox_option_start[], *__u_boot_sandbox_option_end[]; static inline size_t __u_boot_sandbox_option_count(void) diff --git a/arch/sandbox/include/asm/sound.h b/arch/sandbox/include/asm/sound.h new file mode 100644 index 0000000000..a32e8c802d --- /dev/null +++ b/arch/sandbox/include/asm/sound.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SANDBOX_SOUND_H +#define __SANDBOX_SOUND_H + +int sound_play(unsigned int msec, unsigned int frequency); + +int sound_init(const void *blob); + +#endif diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h new file mode 100644 index 0000000000..9985e3c494 --- /dev/null +++ b/arch/sandbox/include/asm/spi.h @@ -0,0 +1,45 @@ +/* + * Simulate a SPI port and clients (see README.sandbox for details) + * + * Copyright (c) 2011-2013 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_SPI_H__ +#define __ASM_SPI_H__ + +#include + +/* + * The interface between the SPI bus and the SPI client. The bus will + * instantiate a client, and that then call into it via these entry + * points. These should be enough for the client to emulate the SPI + * device just like the real hardware. + */ +struct sandbox_spi_emu_ops { + /* The bus wants to instantiate a new client, so setup everything */ + int (*setup)(void **priv, const char *spec); + /* The bus is done with us, so break things down */ + void (*free)(void *priv); + /* The CS has been "activated" -- we won't worry about low/high */ + void (*cs_activate)(void *priv); + /* The CS has been "deactivated" -- we won't worry about low/high */ + void (*cs_deactivate)(void *priv); + /* The client is rx-ing bytes from the bus, so it should tx some */ + int (*xfer)(void *priv, const u8 *rx, u8 *tx, uint bytes); +}; + +/* + * Extract the bus/cs from the spi spec and return the start of the spi + * client spec. If the bus/cs are invalid for the current config, then + * it returns NULL. + * + * Example: arg="0:1:foo" will set bus to 0, cs to 1, and return "foo" + */ +const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus, + unsigned long *cs); + +#endif diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 093c81d918..32d55ccc4c 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -7,6 +7,8 @@ #define __SANDBOX_STATE_H #include +#include +#include /* How we exited U-Boot */ enum exit_type_id { @@ -15,16 +17,127 @@ enum exit_type_id { STATE_EXIT_POWER_OFF, }; +/** + * Selects the behavior of the serial terminal. + * + * If Ctrl-C is processed by U-Boot, then the only way to quit sandbox is with + * the 'reset' command, or equivalent. + * + * If the terminal is cooked, then Ctrl-C will terminate U-Boot, and the + * command line will not be quite such a faithful emulation. + * + * Options are: + * + * raw-with-sigs - Raw, but allow signals (Ctrl-C will quit) + * raw - Terminal is always raw + * cooked - Terminal is always cooked + */ +enum state_terminal_raw { + STATE_TERM_RAW_WITH_SIGS, /* Default */ + STATE_TERM_RAW, + STATE_TERM_COOKED, + + STATE_TERM_COUNT, +}; + +struct sandbox_spi_info { + const char *spec; + struct udevice *emul; +}; + /* The complete state of the test system */ struct sandbox_state { const char *cmd; /* Command to execute */ + bool interactive; /* Enable cmdline after execute */ const char *fdt_fname; /* Filename of FDT binary */ enum exit_type_id exit_type; /* How we exited U-Boot */ const char *parse_err; /* Error to report from parsing */ int argc; /* Program arguments */ - char **argv; + char **argv; /* Command line arguments */ + const char *jumped_fname; /* Jumped from previous U_Boot */ + uint8_t *ram_buf; /* Emulated RAM buffer */ + unsigned int ram_size; /* Size of RAM buffer */ + const char *ram_buf_fname; /* Filename to use for RAM buffer */ + bool ram_buf_rm; /* Remove RAM buffer file after read */ + bool write_ram_buf; /* Write RAM buffer on exit */ + const char *state_fname; /* File containing sandbox state */ + void *state_fdt; /* Holds saved state for sandbox */ + bool read_state; /* Read sandbox state on startup */ + bool write_state; /* Write sandbox state on exit */ + bool ignore_missing_state_on_read; /* No error if state missing */ + bool show_lcd; /* Show LCD on start-up */ + enum state_terminal_raw term_raw; /* Terminal raw/cooked */ + + /* Pointer to information for each SPI bus/cs */ + struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] + [CONFIG_SANDBOX_SPI_MAX_CS]; }; +/* Minimum space we guarantee in the state FDT when calling read/write*/ +#define SANDBOX_STATE_MIN_SPACE 0x1000 + +/** + * struct sandbox_state_io - methods to saved/restore sandbox state + * @name: Name of of the device tree node, also the name of the variable + * holding this data so it should be an identifier (use underscore + * instead of minus) + * @compat: Compatible string for the node containing this state + * + * @read: Function to read state from FDT + * If data is available, then blob and node will provide access to it. If + * not (blob == NULL and node == -1) this function should set up an empty + * data set for start-of-day. + * @param blob: Pointer to device tree blob, or NULL if no data to read + * @param node: Node offset to read from + * @return 0 if OK, -ve on error + * + * @write: Function to write state to FDT + * The caller will ensure that there is a node ready for the state. The + * node may already contain the old state, in which case it should be + * overridden. There is guaranteed to be SANDBOX_STATE_MIN_SPACE bytes + * of free space, so error checking is not required for fdt_setprop...() + * calls which add up to less than this much space. + * + * For adding larger properties, use state_setprop(). + * + * @param blob: Device tree blob holding state + * @param node: Node to write our state into + * + * Note that it is possible to save data as large blobs or as individual + * hierarchical properties. However, unless you intend to keep state files + * around for a long time and be able to run an old state file on a new + * sandbox, it might not be worth using individual properties for everything. + * This is certainly supported, it is just a matter of the effort you wish + * to put into the state read/write feature. + */ +struct sandbox_state_io { + const char *name; + const char *compat; + int (*write)(void *blob, int node); + int (*read)(const void *blob, int node); +}; + +/** + * SANDBOX_STATE_IO - Declare sandbox state to read/write + * + * Sandbox permits saving state from one run and restoring it in another. This + * allows the test system to retain state between runs and thus better + * emulate a real system. Examples of state that might be useful to save are + * the emulated GPIOs pin settings, flash memory contents and TPM private + * data. U-Boot memory contents is dealth with separately since it is large + * and it is not normally useful to save it (since a normal system does not + * preserve DRAM between runs). See the '-m' option for this. + * + * See struct sandbox_state_io above for member documentation. + */ +#define SANDBOX_STATE_IO(_name, _compat, _read, _write) \ + ll_entry_declare(struct sandbox_state_io, _name, state_io) = { \ + .name = __stringify(_name), \ + .read = _read, \ + .write = _write, \ + .compat = _compat, \ + } + /** * Record the exit type to be reported by the test program. * @@ -39,9 +152,60 @@ void state_record_exit(enum exit_type_id exit_type); */ struct sandbox_state *state_get_current(void); +/** + * Read the sandbox state from the supplied device tree file + * + * This calls all registered state handlers to read in the sandbox state + * from a previous test run. + * + * @param state Sandbox state to update + * @param fname Filename of device tree file to read from + * @return 0 if OK, -ve on error + */ +int sandbox_read_state(struct sandbox_state *state, const char *fname); + +/** + * Write the sandbox state to the supplied device tree file + * + * This calls all registered state handlers to write out the sandbox state + * so that it can be preserved for a future test run. + * + * If the file exists it is overwritten. + * + * @param state Sandbox state to update + * @param fname Filename of device tree file to write to + * @return 0 if OK, -ve on error + */ +int sandbox_write_state(struct sandbox_state *state, const char *fname); + +/** + * Add a property to a sandbox state node + * + * This is equivalent to fdt_setprop except that it automatically enlarges + * the device tree if necessary. That means it is safe to write any amount + * of data here. + * + * This function can only be called from within struct sandbox_state_io's + * ->write method, i.e. within state I/O drivers. + * + * @param node Device tree node to write to + * @param prop_name Property to write + * @param data Data to write into property + * @param size Size of data to write into property + */ +int state_setprop(int node, const char *prop_name, const void *data, int size); + /** * Initialize the test system state */ int state_init(void); +/** + * Uninitialize the test system state, writing out state if configured to + * do so. + * + * @return 0 if OK, -ve on error + */ +int state_uninit(void); + #endif diff --git a/arch/sandbox/include/asm/string.h b/arch/sandbox/include/asm/string.h index ef820fa736..f247ff3ba7 100644 --- a/arch/sandbox/include/asm/string.h +++ b/arch/sandbox/include/asm/string.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/sandbox/include/asm/system.h b/arch/sandbox/include/asm/system.h index 95ec7d1068..02beed35a7 100644 --- a/arch/sandbox/include/asm/system.h +++ b/arch/sandbox/include/asm/system.h @@ -1,17 +1,14 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_SANDBOX_SYSTEM_H #define __ASM_SANDBOX_SYSTEM_H /* Define this as nops for sandbox architecture */ -static inline void local_irq_save(unsigned flags __attribute__((unused))) -{ -} - +#define local_irq_save(x) #define local_irq_enable() #define local_irq_disable() #define local_save_flags(x) diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h new file mode 100644 index 0000000000..25a0c85971 --- /dev/null +++ b/arch/sandbox/include/asm/test.h @@ -0,0 +1,26 @@ +/* + * Test-related constants for sandbox + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_TEST_H +#define __ASM_TEST_H + +/* The sandbox driver always permits an I2C device with this address */ +#define SANDBOX_I2C_TEST_ADDR 0x59 + +enum sandbox_i2c_eeprom_test_mode { + SIE_TEST_MODE_NONE, + /* Permits read/write of only one byte per I2C transaction */ + SIE_TEST_MODE_SINGLE_BYTE, +}; + +void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev, + enum sandbox_i2c_eeprom_test_mode mode); + +void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len); + +#endif diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h index 4f1ab13d10..42c09e2fff 100644 --- a/arch/sandbox/include/asm/types.h +++ b/arch/sandbox/include/asm/types.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_SANDBOX_TYPES_H @@ -42,14 +42,19 @@ typedef unsigned short u16; typedef signed int s32; typedef unsigned int u32; +#if !defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__) typedef signed long long s64; typedef unsigned long long u64; +#else +typedef __INT64_TYPE__ s64; +typedef __UINT64_TYPE__ u64; +#endif #define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG typedef unsigned long dma_addr_t; -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; +typedef u32 phys_addr_t; +typedef u32 phys_size_t; #endif /* __KERNEL__ */ diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h index bed720cf81..d2f1b6566d 100644 --- a/arch/sandbox/include/asm/u-boot-sandbox.h +++ b/arch/sandbox/include/asm/u-boot-sandbox.h @@ -23,4 +23,9 @@ int dram_init(void); int sandbox_early_getopt_check(void); int sandbox_main_loop_init(void); +int cleanup_before_linux(void); + +/* drivers/video/sandbox_sdl.c */ +int sandbox_lcd_sdl_early_init(void); + #endif /* _U_BOOT_SANDBOX_H_ */ diff --git a/arch/sandbox/include/asm/unaligned.h b/arch/sandbox/include/asm/unaligned.h index 2df1cd0449..e52980499f 100644 --- a/arch/sandbox/include/asm/unaligned.h +++ b/arch/sandbox/include/asm/unaligned.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index 993fb4e06b..4c1a38d6bc 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -7,28 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = $(obj)lib$(ARCH).o - -COBJS-y += interrupts.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -# Always build libsandbox.o -TARGETS := $(LIB) - -all: $(TARGETS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += interrupts.o diff --git a/arch/sandbox/lib/interrupts.c b/arch/sandbox/lib/interrupts.c index 52ba7c2104..c6d8ae913a 100644 --- a/arch/sandbox/lib/interrupts.c +++ b/arch/sandbox/lib/interrupts.c @@ -3,7 +3,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig new file mode 100644 index 0000000000..ff8f5b5ce8 --- /dev/null +++ b/arch/sh/Kconfig @@ -0,0 +1,149 @@ +menu "SuperH architecture" + depends on SH + +config CPU_SH2 + bool + +config CPU_SH2A + bool + select CPU_SH2 + +config CPU_SH3 + bool + +config CPU_SH4 + bool + +config CPU_SH4A + bool + select CPU_SH4 + +config SH_32BIT + bool "32bit mode" + depends on CPU_SH4A + default n + help + SH4A has 2 physical memory maps. This use 32bit mode. + And this is board specific. Please check your board if you + want to use this. + +choice + prompt "Target select" + +config TARGET_RSK7203 + bool "RSK+ 7203" + select CPU_SH2A + +config TARGET_RSK7264 + bool "RSK2+SH7264" + select CPU_SH2A + +config TARGET_RSK7269 + bool "RSK2+SH7269" + select CPU_SH2A + +config TARGET_MPR2 + bool "Magic Panel Release 2 board" + select CPU_SH3 + +config TARGET_MS7720SE + bool "Support ms7720se" + select CPU_SH3 + +config TARGET_SHMIN + bool "SHMIN" + select CPU_SH3 + +config TARGET_ESPT + bool "Data Technology ESPT-GIGA board" + select CPU_SH4 + +config TARGET_MS7722SE + bool "SolutionEngine 7722" + select CPU_SH4 + +config TARGET_MS7750SE + bool "SolutionEngine 7750" + select CPU_SH4 + +config TARGET_AP_SH4A_4A + bool "ALPHAPROJECT AP-SH4A-4A" + select CPU_SH4A + +config TARGET_AP325RXA + bool "Renesas AP-325RXA" + select CPU_SH4 + +config TARGET_ECOVEC + bool "EcoVec" + select CPU_SH4A + +config TARGET_MIGOR + bool "Migo-R" + select CPU_SH4 + +config TARGET_R0P7734 + bool "Support r0p7734" + select CPU_SH4A + +config TARGET_R2DPLUS + bool "Renesas R2D-PLUS" + select CPU_SH4 + +config TARGET_R7780MP + bool "R7780MP board" + select CPU_SH4A + +config TARGET_SH7752EVB + bool "SH7752EVB" + select CPU_SH4A + +config TARGET_SH7753EVB + bool "SH7753EVB" + select CPU_SH4 + +config TARGET_SH7757LCR + bool "SH7757LCR" + select CPU_SH4A + +config TARGET_SH7763RDP + bool "SH7763RDP" + select CPU_SH4 + +config TARGET_SH7785LCR + bool "SH7785LCR" + select CPU_SH4A + +endchoice + +config SYS_ARCH + default "sh" + +config SYS_CPU + default "sh2" if CPU_SH2 + default "sh3" if CPU_SH3 + default "sh4" if CPU_SH4 + +source "board/alphaproject/ap_sh4a_4a/Kconfig" +source "board/espt/Kconfig" +source "board/mpr2/Kconfig" +source "board/ms7720se/Kconfig" +source "board/ms7722se/Kconfig" +source "board/ms7750se/Kconfig" +source "board/renesas/MigoR/Kconfig" +source "board/renesas/ap325rxa/Kconfig" +source "board/renesas/ecovec/Kconfig" +source "board/renesas/r0p7734/Kconfig" +source "board/renesas/r2dplus/Kconfig" +source "board/renesas/r7780mp/Kconfig" +source "board/renesas/rsk7203/Kconfig" +source "board/renesas/rsk7264/Kconfig" +source "board/renesas/rsk7269/Kconfig" +source "board/renesas/sh7752evb/Kconfig" +source "board/renesas/sh7753evb/Kconfig" +source "board/renesas/sh7757lcr/Kconfig" +source "board/renesas/sh7763rdp/Kconfig" +source "board/renesas/sh7785lcr/Kconfig" +source "board/shmin/Kconfig" + +endmenu diff --git a/arch/sh/Makefile b/arch/sh/Makefile new file mode 100644 index 0000000000..ca55fac920 --- /dev/null +++ b/arch/sh/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/sh/cpu/$(CPU)/start.o + +libs-y += arch/sh/cpu/$(CPU)/ +libs-y += arch/sh/lib/ diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 758c0701e5..0578fa3fd8 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= sh4-linux- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := sh4-linux- +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000 ifeq ($(CPU),sh2) @@ -15,3 +17,4 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE) LDFLAGS_FINAL = --gc-sections +PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/arch/sh/cpu/sh2/Makefile b/arch/sh/cpu/sh2/Makefile index 1cc00313e9..a19ed5ecf5 100644 --- a/arch/sh/cpu/sh2/Makefile +++ b/arch/sh/cpu/sh2/Makefile @@ -8,25 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -SOBJS = start.o -COBJS = cpu.o interrupts.o watchdog.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu.o interrupts.o watchdog.o diff --git a/arch/sh/cpu/sh2/cache.c b/arch/sh/cpu/sh2/cache.c deleted file mode 100644 index 8093e98e2a..0000000000 --- a/arch/sh/cpu/sh2/cache.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda - * - * Copyright (C) 2007, 2008 Nobobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ -} while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ -} while (0) - -#define CACHE_VALID 1 -#define CACHE_UPDATED 2 - -static inline void cache_wback_all(void) -{ - unsigned long addr, data, i, j; - - jump_to_P2(); - for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { - for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { - addr = CACHE_OC_ADDRESS_ARRAY - | (j << CACHE_OC_WAY_SHIFT) - | (i << CACHE_OC_ENTRY_SHIFT); - data = inl(addr); - if (data & CACHE_UPDATED) { - data &= ~CACHE_UPDATED; - outl(data, addr); - } - } - } - back_to_P1(); -} - - -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 - -int cache_control(unsigned int cmd) -{ - unsigned long ccr; - - jump_to_P2(); - ccr = inl(CCR); - - if (ccr & CCR_CACHE_ENABLE) - cache_wback_all(); - - if (cmd == CACHE_DISABLE) - outl(CCR_CACHE_STOP, CCR); - else - outl(CCR_CACHE_INIT, CCR); - back_to_P1(); - - return 0; -} diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk index 8a0de96714..12e202d539 100644 --- a/arch/sh/cpu/sh2/config.mk +++ b/arch/sh/cpu/sh2/config.mk @@ -7,12 +7,11 @@ # ENDIANNESS += -EB -ifdef CONFIG_SH2A -PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -ffreestanding +ifdef CONFIG_CPU_SH2A +PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb else # SH2 PLATFORM_CPPFLAGS += -m3e -mb endif PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic) -PLATFORM_RELFLAGS += -ffixed-r13 PLATFORM_LDFLAGS += $(ENDIANNESS) diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c index 18479a4c40..a2f856f459 100644 --- a/arch/sh/cpu/sh2/cpu.c +++ b/arch/sh/cpu/sh2/cpu.c @@ -23,11 +23,7 @@ int checkcpu(void) { -#if defined(CONFIG_SH2A) - puts("CPU: SH2A\n"); -#else puts("CPU: SH2\n"); -#endif return 0; } diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds deleted file mode 100644 index 254d9f274b..0000000000 --- a/arch/sh/cpu/sh2/u-boot.lds +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh2/start.o (.text)) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/arch/sh/cpu/sh3/Makefile b/arch/sh/cpu/sh3/Makefile index e707de3f89..1dccaf9520 100644 --- a/arch/sh/cpu/sh3/Makefile +++ b/arch/sh/cpu/sh3/Makefile @@ -11,25 +11,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -SOBJS = start.o -COBJS = cpu.o interrupts.o watchdog.o cache.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu.o interrupts.o watchdog.o cache.o diff --git a/arch/sh/cpu/sh3/config.mk b/arch/sh/cpu/sh3/config.mk index 5c77e5c32d..dcafd19e58 100644 --- a/arch/sh/cpu/sh3/config.mk +++ b/arch/sh/cpu/sh3/config.mk @@ -12,4 +12,3 @@ # # PLATFORM_CPPFLAGS += -m3 -PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/sh3/u-boot.lds deleted file mode 100644 index 26de08606a..0000000000 --- a/arch/sh/cpu/sh3/u-boot.lds +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2007 - * Yoshihiro Shimoda - * - * Copyright (C) 2007 - * Nobuhiro Iwamatsu - * - * Copyright (C) 2008 - * Mark Jonas - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh3/start.o (.text)) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/arch/sh/cpu/sh4/Makefile b/arch/sh/cpu/sh4/Makefile index e7d8903814..38c6188c38 100644 --- a/arch/sh/cpu/sh4/Makefile +++ b/arch/sh/cpu/sh4/Makefile @@ -8,25 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -SOBJS = start.o -COBJS = cpu.o interrupts.o watchdog.o cache.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu.o interrupts.o watchdog.o cache.o diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 1947ec8e95..e1ee970a91 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -91,7 +91,7 @@ int cache_control(unsigned int cmd) return 0; } -void dcache_wback_range(u32 start, u32 end) +void flush_dcache_range(unsigned long start, unsigned long end) { u32 v; @@ -102,7 +102,7 @@ void dcache_wback_range(u32 start, u32 end) } } -void dcache_invalid_range(u32 start, u32 end) +void invalidate_dcache_range(unsigned long start, unsigned long end) { u32 v; diff --git a/arch/sh/cpu/sh4/config.mk b/arch/sh/cpu/sh4/config.mk index c3575570e7..4fb2dc23aa 100644 --- a/arch/sh/cpu/sh4/config.mk +++ b/arch/sh/cpu/sh4/config.mk @@ -9,4 +9,3 @@ # # PLATFORM_CPPFLAGS += -m4-nofpu -PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c index 9fae61473b..e8ee0a45ab 100644 --- a/arch/sh/cpu/sh4/cpu.c +++ b/arch/sh/cpu/sh4/cpu.c @@ -13,11 +13,7 @@ int checkcpu(void) { -#ifdef CONFIG_SH4A - puts("CPU: SH-4A\n"); -#else puts("CPU: SH4\n"); -#endif return 0; } @@ -41,7 +37,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) void flush_cache (unsigned long addr, unsigned long size) { - dcache_invalid_range( addr , addr + size ); + invalidate_dcache_range(addr , addr + size); } void icache_enable (void) diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds deleted file mode 100644 index 57544ce040..0000000000 --- a/arch/sh/cpu/sh4/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu - * - * Copyright (C) 2008-2009 - * Yoshihiro Shimoda - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh4/start.o (.text)) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss (NOLOAD) : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds new file mode 100644 index 0000000000..30c7a9d3f8 --- /dev/null +++ b/arch/sh/cpu/u-boot.lds @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu + * + * Copyright (C) 2008-2009 + * Yoshihiro Shimoda + * + * Copyright (C) 2008 + * Mark Jonas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + KEEP(*/start.o (.text)) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (__bss_end = .); +} diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h index 24941b3019..abaf4050c3 100644 --- a/arch/sh/include/asm/cache.h +++ b/arch/sh/include/asm/cache.h @@ -1,7 +1,7 @@ #ifndef __ASM_SH_CACHE_H #define __ASM_SH_CACHE_H -#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) +#if defined(CONFIG_CPU_SH4) int cache_control(unsigned int cmd); @@ -10,9 +10,6 @@ int cache_control(unsigned int cmd); struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct *)(x)) -void dcache_wback_range(u32 start, u32 end); -void dcache_invalid_range(u32 start, u32 end); - #else /* @@ -21,7 +18,7 @@ void dcache_invalid_range(u32 start, u32 end); */ #define ARCH_DMA_MINALIGN 32 -#endif /* CONFIG_SH4 || CONFIG_SH4A */ +#endif /* CONFIG_CPU_SH4 */ /* * Use the L1 data cache line size value for the minimum DMA buffer alignment diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index 9181d59a94..9f48e4fe04 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -37,6 +37,8 @@ # include #elif defined (CONFIG_CPU_SH7752) # include +#elif defined (CONFIG_CPU_SH7753) +# include #elif defined (CONFIG_CPU_SH7757) # include #elif defined (CONFIG_CPU_SH7763) diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h index 7be37ae984..bf57e18a64 100644 --- a/arch/sh/include/asm/cpu_sh7722.h +++ b/arch/sh/include/asm/cpu_sh7722.h @@ -1250,8 +1250,9 @@ #define PUDR 0xA4050162 #define PVDR 0xA4050164 #define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A +#define PXDR 0xA4050168 +#define PYDR 0xA405016A +#define PZDR 0xA405016C /* UBC */ #define CBR0 0xFF200000 diff --git a/arch/sh/include/asm/cpu_sh7723.h b/arch/sh/include/asm/cpu_sh7723.h index 3af0b0db2f..9d8cb8db44 100644 --- a/arch/sh/include/asm/cpu_sh7723.h +++ b/arch/sh/include/asm/cpu_sh7723.h @@ -178,8 +178,9 @@ #define PUDR 0xA4050162 #define PVDR 0xA4050164 #define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A +#define PXDR 0xA4050168 +#define PYDR 0xA405016A +#define PZDR 0xA405016C /* UBC */ /* H-UDI */ diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h index 2c2a474d37..88c418a17f 100644 --- a/arch/sh/include/asm/cpu_sh7724.h +++ b/arch/sh/include/asm/cpu_sh7724.h @@ -200,8 +200,9 @@ #define PUDR 0xA4050162 #define PVDR 0xA4050164 #define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A +#define PXDR 0xA4050168 +#define PYDR 0xA405016A +#define PZDR 0xA405016C /* Ether */ #define EDMR 0xA4600000 diff --git a/arch/sh/include/asm/cpu_sh7753.h b/arch/sh/include/asm/cpu_sh7753.h new file mode 100644 index 0000000000..cd0e0bba6c --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7753.h @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_CPU_SH7753_H_ +#define _ASM_CPU_SH7753_H_ + +#define CCR 0xFF00001C +#define WTCNT 0xFFCC0000 +#define CCR_CACHE_INIT 0x0000090b +#define CACHE_OC_NUM_WAYS 1 + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ +/* MMU */ +struct mmu_regs { + unsigned int reserved[4]; + unsigned int mmucr; +}; +#define MMU_BASE ((struct mmu_regs *)0xff000000) + +/* Watchdog */ +#define WTCSR0 0xffcc0002 +#define WRSTCSR_R 0xffcc0003 +#define WRSTCSR_W 0xffcc0002 +#define WTCSR_PREFIX 0xa500 +#define WRSTCSR_PREFIX 0x6900 +#define WRSTCSR_WOVF_PREFIX 0x9600 + +/* SCIF */ +#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ +#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ +#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ + +/* TMU0 */ +#define TMU_BASE 0xFE430000 + +/* ETHER, GETHER MAC address */ +struct ether_mac_regs { + unsigned int reserved[114]; + unsigned int mahr; + unsigned int reserved2; + unsigned int malr; +}; +#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) +#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) +#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) +#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) + +/* GETHER */ +struct gether_control_regs { + unsigned int gbecont; +}; +#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) +#define GBECONT_RMII1 0x00020000 +#define GBECONT_RMII0 0x00010000 + +/* SerMux */ +struct sermux_regs { + unsigned char smr0; + unsigned char smr1; + unsigned char smr2; + unsigned char smr3; + unsigned char smr4; + unsigned char smr5; +}; +#define SERMUX_BASE ((struct sermux_regs *)0xfe470000) + + +/* USB0/1 */ +struct usb_common_regs { + unsigned short reserved[129]; + unsigned short suspmode; +}; +#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) +#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) + +struct usb0_phy_regs { + unsigned short reset; + unsigned short reserved[4]; + unsigned short portsel; +}; +#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) + +struct usb1_port_regs { + unsigned int port1sel; + unsigned int reserved; + unsigned int usb1intsts; +}; +#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) + +struct usb1_alignment_regs { + unsigned int ehcidatac; /* 0xfe4fe018 */ + unsigned int reserved[63]; + unsigned int ohcidatac; +}; +#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) + +/* GPIO */ +struct gpio_regs { + unsigned short pacr; + unsigned short pbcr; + unsigned short pccr; + unsigned short pdcr; + unsigned short pecr; + unsigned short pfcr; + unsigned short pgcr; + unsigned short phcr; + unsigned short picr; + unsigned short pjcr; + unsigned short pkcr; + unsigned short plcr; + unsigned short pmcr; + unsigned short pncr; + unsigned short pocr; + unsigned short reserved; + unsigned short pqcr; + unsigned short prcr; + unsigned short pscr; + unsigned short ptcr; + unsigned short pucr; + unsigned short pvcr; + unsigned short pwcr; + unsigned short pxcr; + unsigned short pycr; + unsigned short pzcr; + unsigned char padr; + unsigned char reserved_a; + unsigned char pbdr; + unsigned char reserved_b; + unsigned char pcdr; + unsigned char reserved_c; + unsigned char pddr; + unsigned char reserved_d; + unsigned char pedr; + unsigned char reserved_e; + unsigned char pfdr; + unsigned char reserved_f; + unsigned char pgdr; + unsigned char reserved_g; + unsigned char phdr; + unsigned char reserved_h; + unsigned char pidr; + unsigned char reserved_i; + unsigned char pjdr; + unsigned char reserved_j; + unsigned char pkdr; + unsigned char reserved_k; + unsigned char pldr; + unsigned char reserved_l; + unsigned char pmdr; + unsigned char reserved_m; + unsigned char pndr; + unsigned char reserved_n; + unsigned char podr; + unsigned char reserved_o; + unsigned char ppdr; + unsigned char reserved_p; + unsigned char pqdr; + unsigned char reserved_q; + unsigned char prdr; + unsigned char reserved_r; + unsigned char psdr; + unsigned char reserved_s; + unsigned char ptdr; + unsigned char reserved_t; + unsigned char pudr; + unsigned char reserved_u; + unsigned char pvdr; + unsigned char reserved_v; + unsigned char pwdr; + unsigned char reserved_w; + unsigned char pxdr; + unsigned char reserved_x; + unsigned char pydr; + unsigned char reserved_y; + unsigned char pzdr; + unsigned char reserved_z; + unsigned short ncer; + unsigned short ncmcr; + unsigned short nccsr; + unsigned char reserved2[2]; + unsigned short psel0; /* +0x70 */ + unsigned short psel1; + unsigned short psel2; + unsigned short psel3; + unsigned short psel4; + unsigned short psel5; + unsigned short psel6; + unsigned short reserved3[2]; + unsigned short psel7; +}; +#define GPIO_BASE ((struct gpio_regs *)0xffec0000) + +#endif /* ifndef __ASSEMBLY__ */ +#endif /* _ASM_CPU_SH7753_H_ */ diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index 938a89cff5..b07fe542e3 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -1,12 +1,10 @@ #ifndef _ASM_SH_PROCESSOR_H_ #define _ASM_SH_PROCESSOR_H_ -#if defined(CONFIG_SH2) || \ - defined (CONFIG_SH2A) +#if defined(CONFIG_CPU_SH2) # include -#elif defined (CONFIG_SH3) +#elif defined(CONFIG_CPU_SH3) # include -#elif defined (CONFIG_SH4) || \ - defined (CONFIG_SH4A) +#elif defined(CONFIG_CPU_SH4) # include #endif #endif diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h index 81d5161282..ea37c24497 100644 --- a/arch/sh/include/asm/u-boot.h +++ b/arch/sh/include/asm/u-boot.h @@ -20,7 +20,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ unsigned long bi_boot_params; /* where this board expects params */ } bd_t; diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h index 2e0d164050..06096eeac5 100644 --- a/arch/sh/include/asm/unaligned.h +++ b/arch/sh/include/asm/unaligned.h @@ -8,7 +8,7 @@ #include #else /* Otherwise, SH can't handle unaligned accesses. */ -#include +#include #if defined(__BIG_ENDIAN__) #define get_unaligned __get_unaligned_be #define put_unaligned __put_unaligned_be diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 8165963ee8..1304f4ee93 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -5,57 +5,15 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = $(obj)lib$(ARCH).o -LIBGCC = $(obj)libgcc.o - -SOBJS-y += -GLSOBJS += ashiftrt.o -GLSOBJS += ashiftlt.o -GLSOBJS += lshiftrt.o -GLSOBJS += ashldi3.o -GLSOBJS += ashrsi3.o -GLSOBJS += lshrdi3.o -GLSOBJS += movmem.o - -COBJS-y += board.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -ifeq ($(CONFIG_SH2),y) -COBJS-y += time_sh2.o +obj-y += board.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +ifeq ($(CONFIG_CPU_SH2),y) +obj-y += time_sh2.o else -COBJS-y += time.o -endif -ifeq ($(CONFIG_CMD_SH_ZIMAGEBOOT),y) -COBJS-y += zimageboot.o -endif - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -LGOBJS := $(addprefix $(obj),$(GLSOBJS)) \ - $(addprefix $(obj),$(GLCOBJS)) - -# Always build libsh.o -TARGETS := $(LIB) - -# Build private libgcc only when asked for -ifdef USE_PRIVATE_LIBGCC -TARGETS += $(LIBGCC) +obj-y += time.o endif +obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o -all: $(TARGETS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(LIBGCC): $(obj).depend $(LGOBJS) - $(call cmd_link_o_target, $(LGOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashiftrt.o ashiftlt.o lshiftrt.o \ + ashldi3.o ashrsi3.o lshrdi3.o movmem.o diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 8498153d4e..1eb7afb89e 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -155,7 +155,6 @@ void sh_generic_init(void) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { WATCHDOG_RESET(); diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c index 1fe537e83b..d970a1e4f0 100644 --- a/arch/sh/lib/time.c +++ b/arch/sh/lib/time.c @@ -12,36 +12,23 @@ */ #include -#include #include #include #include -static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE; +#define TCR_TPSC 0x07 -static u16 bit; -static unsigned long last_tcnt; -static unsigned long long overflow_ticks; +static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE; unsigned long get_tbclk(void) { - return get_tmu0_clk_rate() >> ((bit + 1) * 2); + u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1; + return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2); } -static inline unsigned long long tick_to_time(unsigned long long tick) +unsigned long timer_read_counter(void) { - tick *= CONFIG_SYS_HZ; - do_div(tick, get_tbclk()); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= get_tbclk(); - do_div(usec, 1000000); - - return usec; + return ~readl(&tmu->tcnt0); } static void tmu_timer_start(unsigned int timer) @@ -60,55 +47,12 @@ static void tmu_timer_stop(unsigned int timer) int timer_init(void) { - bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1; - writew(readw(&tmu->tcr0) | bit, &tmu->tcr0); + u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1; + writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0); tmu_timer_stop(0); tmu_timer_start(0); - last_tcnt = 0; - overflow_ticks = 0; - return 0; } -unsigned long long get_ticks(void) -{ - unsigned long tcnt = 0 - readl(&tmu->tcnt0); - - if (last_tcnt > tcnt) /* overflow */ - overflow_ticks++; - last_tcnt = tcnt; - - return (overflow_ticks << 32) | tcnt; -} - -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = usec_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -unsigned long get_timer(unsigned long base) -{ - /* return msec */ - return tick_to_time(get_ticks()) - base; -} - -void set_timer(unsigned long t) -{ - writel((0 - t), &tmu->tcnt0); -} - -void reset_timer(void) -{ - tmu_timer_stop(0); - set_timer(0); - tmu_timer_start(0); -} diff --git a/arch/sh/lib/time_sh2.c b/arch/sh/lib/time_sh2.c index be3896c3ed..4b1f47b6ad 100644 --- a/arch/sh/lib/time_sh2.c +++ b/arch/sh/lib/time_sh2.c @@ -84,5 +84,5 @@ void __udelay(unsigned long usec) unsigned long get_tbclk(void) { - return CONFIG_SYS_HZ; + return CONFIG_SH_CMT_CLK_FREQ; } diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c index 86d39983c8..3fea5f5b53 100644 --- a/arch/sh/lib/zimageboot.c +++ b/arch/sh/lib/zimageboot.c @@ -45,6 +45,7 @@ int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bootargs = getenv("bootargs"); /* Clear zero page */ + /* cppcheck-suppress nullPointer */ memset(param, 0, 0x1000); /* Set commandline */ diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig new file mode 100644 index 0000000000..2df09b2e50 --- /dev/null +++ b/arch/sparc/Kconfig @@ -0,0 +1,60 @@ +menu "SPARC architecture" + depends on SPARC + +config LEON + bool + +config LEON2 + bool + select LEON + +config LEON3 + bool + select LEON + +choice + prompt "Board select" + +config TARGET_GRSIM_LEON2 + bool "GRSIM simulating a LEON2 board" + select LEON2 + +config TARGET_GR_CPCI_AX2000 + bool "Gaisler GR-CPCI-AX2000 board" + select LEON3 + +config TARGET_GR_EP2S60 + bool "Gaisler Template design for Altera NIOS board with Stratix EP2S60" + select LEON3 + help + Gaisler Research AB's Template design (GPL Open Source SPARC/LEON3 + 96MHz) for Altera NIOS Development board Stratix II edition, + with the FPGA device EP2S60. + +config TARGET_GR_XC3S_1500 + bool "Gaisler GR-XC3S-1500 spartan board" + select LEON3 + +config TARGET_GRSIM + bool "GRSIM simulating a LEON3 GR-XC3S-1500 board" + select LEON3 + +endchoice + +config SYS_ARCH + default "sparc" + +config SYS_CPU + default "leon2" if LEON2 + default "leon3" if LEON3 + +config SYS_VENDOR + default "gaisler" + +source "board/gaisler/gr_cpci_ax2000/Kconfig" +source "board/gaisler/gr_ep2s60/Kconfig" +source "board/gaisler/gr_xc3s_1500/Kconfig" +source "board/gaisler/grsim/Kconfig" +source "board/gaisler/grsim_leon2/Kconfig" + +endmenu diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile new file mode 100644 index 0000000000..2d4c9715a6 --- /dev/null +++ b/arch/sparc/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/sparc/cpu/$(CPU)/start.o + +libs-y += arch/sparc/cpu/$(CPU)/ +libs-y += arch/sparc/lib/ diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk index e94e7cbab5..d615f294fe 100644 --- a/arch/sparc/config.mk +++ b/arch/sparc/config.mk @@ -5,8 +5,15 @@ # SPDX-License-Identifier: GPL-2.0+ # -CROSS_COMPILE ?= sparc-elf- +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := sparc-elf- +endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) -T sparc.lds +gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) -PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ +CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \ + -T $(srctree)/examples/standalone/sparc.lds + +PLATFORM_CPPFLAGS += -D__sparc__ + +PLATFORM_RELFLAGS += -fPIC diff --git a/arch/sparc/cpu/leon2/Makefile b/arch/sparc/cpu/leon2/Makefile index f43d3d2cd3..8c95ca5670 100644 --- a/arch/sparc/cpu/leon2/Makefile +++ b/arch/sparc/cpu/leon2/Makefile @@ -5,28 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -SOBJS = -COBJS = cpu_init.o serial.o cpu.o interrupts.o prom.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu_init.o serial.o cpu.o interrupts.o prom.o diff --git a/arch/sparc/cpu/leon2/config.mk b/arch/sparc/cpu/leon2/config.mk deleted file mode 100644 index f9b0d347f7..0000000000 --- a/arch/sparc/cpu/leon2/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fPIC - -PLATFORM_CPPFLAGS += -DCONFIG_LEON diff --git a/arch/sparc/cpu/leon2/cpu_init.c b/arch/sparc/cpu/leon2/cpu_init.c index de310fbbbb..6e07fe6bb4 100644 --- a/arch/sparc/cpu/leon2/cpu_init.c +++ b/arch/sparc/cpu/leon2/cpu_init.c @@ -13,6 +13,9 @@ #include +#define TIMER_BASE_CLK 1000000 +#define US_PER_TICK (1000000 / CONFIG_SYS_HZ) + DECLARE_GLOBAL_DATA_PTR; /* reset CPU (jump to 0, without reset) */ @@ -90,7 +93,7 @@ void cpu_wait_ticks(unsigned long ticks) while (get_timer(start) < ticks) ; } -/* initiate and setup timer0 interrupt to 1MHz +/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz. * Return irq number for timer int or a negative number for * dealing with self */ @@ -98,28 +101,31 @@ int timer_interrupt_init_cpu(void) { LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; - /* 1ms ticks */ + /* SYS_HZ ticks per second */ leon2->Timer_Counter_1 = 0; - leon2->Timer_Reload_1 = 999; /* (((1000000 / 100) - 1)) */ + leon2->Timer_Reload_1 = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1; leon2->Timer_Control_1 = (LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD); return LEON2_TIMER1_IRQNO; } +ulong get_tbclk(void) +{ + return TIMER_BASE_CLK; +} + /* * This function is intended for SHORT delays only. */ unsigned long cpu_usec2ticks(unsigned long usec) { - /* timer set to 1kHz ==> 1 clk tick = 1 msec */ - if (usec < 1000) + if (usec < US_PER_TICK) return 1; - return (usec / 1000); + return usec / US_PER_TICK; } unsigned long cpu_ticks2usec(unsigned long ticks) { - /* 1tick = 1usec */ - return ticks * 1000; + return ticks * US_PER_TICK; } diff --git a/arch/sparc/cpu/leon3/Makefile b/arch/sparc/cpu/leon3/Makefile index 95bbfc9bac..4f13ec3071 100644 --- a/arch/sparc/cpu/leon3/Makefile +++ b/arch/sparc/cpu/leon3/Makefile @@ -5,28 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -SOBJS = -COBJS = cpu_init.o serial.o cpu.o ambapp.o interrupts.o prom.o usb_uhci.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-y = cpu_init.o serial.o cpu.o ambapp.o interrupts.o prom.o usb_uhci.o diff --git a/arch/sparc/cpu/leon3/config.mk b/arch/sparc/cpu/leon3/config.mk deleted file mode 100644 index f9b0d347f7..0000000000 --- a/arch/sparc/cpu/leon3/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fPIC - -PLATFORM_CPPFLAGS += -DCONFIG_LEON diff --git a/arch/sparc/cpu/leon3/cpu_init.c b/arch/sparc/cpu/leon3/cpu_init.c index 4720f42a93..2f41d8847b 100644 --- a/arch/sparc/cpu/leon3/cpu_init.c +++ b/arch/sparc/cpu/leon3/cpu_init.c @@ -14,6 +14,9 @@ #include +#define TIMER_BASE_CLK 1000000 +#define US_PER_TICK (1000000 / CONFIG_SYS_HZ) + DECLARE_GLOBAL_DATA_PTR; /* reset CPU (jump to 0, without reset) */ @@ -203,15 +206,15 @@ void cpu_wait_ticks(unsigned long ticks) while (get_timer(start) < ticks) ; } -/* initiate and setup timer0 interrupt to 1MHz +/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz. * Return irq number for timer int or a negative number for * dealing with self */ int timer_interrupt_init_cpu(void) { - /* 1ms ticks */ + /* SYS_HZ ticks per second */ gptimer->e[0].val = 0; - gptimer->e[0].rld = 999; /* (((1000000 / 100) - 1)) */ + gptimer->e[0].rld = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1; gptimer->e[0].ctrl = (LEON3_GPTIMER_EN | LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN); @@ -219,19 +222,22 @@ int timer_interrupt_init_cpu(void) return gptimer_irq; } +ulong get_tbclk(void) +{ + return TIMER_BASE_CLK; +} + /* * This function is intended for SHORT delays only. */ unsigned long cpu_usec2ticks(unsigned long usec) { - /* timer set to 1kHz ==> 1 clk tick = 1 msec */ - if (usec < 1000) + if (usec < US_PER_TICK) return 1; - return (usec / 1000); + return usec / US_PER_TICK; } unsigned long cpu_ticks2usec(unsigned long ticks) { - /* 1tick = 1usec */ - return ticks * 1000; + return ticks * US_PER_TICK; } diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S index 70aee78054..cf897f6877 100644 --- a/arch/sparc/cpu/leon3/start.S +++ b/arch/sparc/cpu/leon3/start.S @@ -1,31 +1,41 @@ -TRAP ta 0; nop; nop; nop; - -/* Software trap. Treat as BAD_TRAP for the time being... */ -#define SOFT_TRAP TRAP(_hwerr) - -#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */ -#define WIM_INIT 2 - -/* All traps low-level code here must end with this macro. */ -#define RESTORE_ALL b ret_trap_entry; clr %l6; - -#define WRITE_PAUSE nop;nop;nop - -WINDOWSIZE = (16 * 4) -ARGPUSHSIZE = (6 * 4) -ARGPUSH = (WINDOWSIZE + 4) -MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) - -/* Number of register windows */ -#ifndef CONFIG_SYS_SPARC_NWINDOWS -#error Must define number of SPARC register windows, default is 8 -#endif - -#define STACK_ALIGN 8 -#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1)) +/* This is where the SPARC/LEON3 starts + * Copyright (C) 2007, + * Daniel Hellstrom, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * SPDX-License-Identifier: GPL-2.0+ + */ - .section ".start", "ax" - .globl _starttate */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Entry for traps which jump to a programmer-specified trap handler. */ +#define TRAPR(H) \ + wr %g0, 0xfe0, %psr; \ + mov %g0, %tbr; \ + ba (H); \ + mov %g0, %wim; + +#define TRAP(H) \ + mov %psr, %l0; \ + ba (H); \ + nop; nop; + +#define TRAPI(ilevel) \ + mov ilevel, %l7; \ + mov %psr, %l0; \ + b _irq_entry; \ + mov %wim, %l3 + +/* Unexcpected trap will halt the processor by forcing it to error state */ #undef BAD_TRAP #define BAD_TRAP ta 0; nop; nop; nop; diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c index 5de48c11c2..ca7d6e86f0 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.c +++ b/arch/sparc/cpu/leon3/usb_uhci.c @@ -688,7 +688,7 @@ void handle_usb_interrupt(void) /* init uhci */ -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { unsigned char temp; ambapp_ahbdev ahbdev; @@ -757,110 +757,9 @@ static void usb_display_Req(unsigned short req) } #endif -static unsigned char root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.0 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x01, /* __u8 iManufacturer; */ - 0x00, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static unsigned char root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_hub_des[] = { - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x02, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -static unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = { - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#define WANT_USB_ROOT_HUB_HUB_DES +#include +#undef WANT_USB_ROOT_HUB_HUB_DES /* * Root Hub Control Pipe (interrupt Pipes are not supported) diff --git a/arch/sparc/cpu/u-boot.lds b/arch/sparc/cpu/u-boot.lds new file mode 100644 index 0000000000..1ade3b344b --- /dev/null +++ b/arch/sparc/cpu/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2007-2008 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") +OUTPUT_ARCH(sparc) +ENTRY(_start) +SECTIONS +{ + +/* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + + .text : { + _load_addr = .; + _text = .; + + *(.start) + */start.o (.text) +/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ + . = ALIGN(8192); +/* PROM CODE, Will be relocated to the end of memory, + * no global data accesses please. + */ + __prom_start = .; + *(.prom.pgt) + *(.prom.data) + *(.prom.text) + . = ALIGN(16); + __prom_end = .; + *(.text) + *(.fixup) + *(.gnu.warning) +/* *(.got1)*/ + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + . = ALIGN(4); + _etext = .; + + /* CMD Table */ + + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + .data : + { + *(.data) + *(.data1) + *(.data.rel) + *(.data.rel.*) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = ALIGN(4); + __got_start = .; + .got : { + *(.got) +/* *(.data.rel) + *(.data.rel.local)*/ + . = ALIGN(16); + } + __got_end = .; + +/* .data.rel : { } */ + + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(16); /* to speed clearing of bss up */ + } + __bss_end = . ; + __bss_end = . ; + PROVIDE (end = .); + +/* Relocated into main memory */ + + /* Start of main memory */ + /*. = 0x40000000;*/ + + .stack (NOLOAD) : { *(.stack) } + + /* PROM CODE */ + + /* global data in RAM passed to kernel after booting */ + + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + +} diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h index 8ee0976659..d9671d1c74 100644 --- a/arch/sparc/include/asm/cache.h +++ b/arch/sparc/include/asm/cache.h @@ -8,7 +8,6 @@ #ifndef __SPARC_CACHE_H__ #define __SPARC_CACHE_H__ -#include #include /* diff --git a/arch/sparc/include/asm/page.h b/arch/sparc/include/asm/page.h index ecc0dc5657..181d1c1952 100644 --- a/arch/sparc/include/asm/page.h +++ b/arch/sparc/include/asm/page.h @@ -10,7 +10,6 @@ #ifndef _SPARC_PAGE_H #define _SPARC_PAGE_H -#include #ifdef CONFIG_SUN4 #define PAGE_SHIFT 13 #else diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h index 66cf4b023d..5f12e58131 100644 --- a/arch/sparc/include/asm/u-boot.h +++ b/arch/sparc/include/asm/u-boot.h @@ -40,7 +40,6 @@ typedef struct bd_info { unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile index 7e78d44754..e69b9ba426 100644 --- a/arch/sparc/lib/Makefile +++ b/arch/sparc/lib/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).o - -SOBJS = - -COBJS = board.o cache.o interrupts.o time.o -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = board.o cache.o interrupts.o time.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index c778ba26e7..b311a946c0 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -173,7 +173,6 @@ void board_init_f(ulong bootflag) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig new file mode 100644 index 0000000000..90e828a26e --- /dev/null +++ b/arch/x86/Kconfig @@ -0,0 +1,359 @@ +menu "x86 architecture" + depends on X86 + +config SYS_ARCH + default "x86" + +config USE_PRIVATE_LIBGCC + default y + +choice + prompt "Target select" + +config TARGET_COREBOOT + bool "Support coreboot" + help + This target is used for running U-Boot on top of Coreboot. In + this case Coreboot does the early inititalisation, and U-Boot + takes over once the RAM, video and CPU are fully running. + U-Boot is loaded as a fallback payload from Coreboot, in + Coreboot terminology. This method was used for the Chromebook + Pixel when launched. + +config TARGET_CHROMEBOOK_LINK + bool "Support Chromebook link" + help + This is the Chromebook Pixel released in 2013. It uses an Intel + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of + SDRAM. It has a Panther Point platform controller hub, PCIe + WiFi and Bluetooth. It also includes a 720p webcam, USB SD + reader, microphone and speakers, display port and 32GB SATA + solid state drive. There is a Chrome OS EC connected on LPC, + and it provides a 2560x1700 high resolution touch-enabled LCD + display. + +config TARGET_CROWNBAY + bool "Support Intel Crown Bay CRB" + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + +endchoice + +config RAMBASE + hex + default 0x100000 + +config XIP_ROM_SIZE + hex + depends on X86_RESET_VECTOR + default ROM_SIZE + +config CPU_ADDR_BITS + int + default 36 + +config HPET_ADDRESS + hex + default 0xfed00000 if !HPET_ADDRESS_OVERRIDE + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + +config X86_RESET_VECTOR + bool + default n + +config SYS_X86_START16 + hex + depends on X86_RESET_VECTOR + default 0xfffff800 + +config BOARD_ROMSIZE_KB_512 + bool +config BOARD_ROMSIZE_KB_1024 + bool +config BOARD_ROMSIZE_KB_2048 + bool +config BOARD_ROMSIZE_KB_4096 + bool +config BOARD_ROMSIZE_KB_8192 + bool +config BOARD_ROMSIZE_KB_16384 + bool + +choice + prompt "ROM chip size" + depends on X86_RESET_VECTOR + default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 + default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 + default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 + default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 + default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 + help + Select the size of the ROM chip you intend to flash U-Boot on. + + The build system will take care of creating a u-boot.rom file + of the matching size. + +config UBOOT_ROMSIZE_KB_512 + bool "512 KB" + help + Choose this option if you have a 512 KB ROM chip. + +config UBOOT_ROMSIZE_KB_1024 + bool "1024 KB (1 MB)" + help + Choose this option if you have a 1024 KB (1 MB) ROM chip. + +config UBOOT_ROMSIZE_KB_2048 + bool "2048 KB (2 MB)" + help + Choose this option if you have a 2048 KB (2 MB) ROM chip. + +config UBOOT_ROMSIZE_KB_4096 + bool "4096 KB (4 MB)" + help + Choose this option if you have a 4096 KB (4 MB) ROM chip. + +config UBOOT_ROMSIZE_KB_8192 + bool "8192 KB (8 MB)" + help + Choose this option if you have a 8192 KB (8 MB) ROM chip. + +config UBOOT_ROMSIZE_KB_16384 + bool "16384 KB (16 MB)" + help + Choose this option if you have a 16384 KB (16 MB) ROM chip. + +endchoice + +# Map the config names to an integer (KB). +config UBOOT_ROMSIZE_KB + int + default 512 if UBOOT_ROMSIZE_KB_512 + default 1024 if UBOOT_ROMSIZE_KB_1024 + default 2048 if UBOOT_ROMSIZE_KB_2048 + default 4096 if UBOOT_ROMSIZE_KB_4096 + default 8192 if UBOOT_ROMSIZE_KB_8192 + default 16384 if UBOOT_ROMSIZE_KB_16384 + +# Map the config names to a hex value (bytes). +config ROM_SIZE + hex + default 0x80000 if UBOOT_ROMSIZE_KB_512 + default 0x100000 if UBOOT_ROMSIZE_KB_1024 + default 0x200000 if UBOOT_ROMSIZE_KB_2048 + default 0x400000 if UBOOT_ROMSIZE_KB_4096 + default 0x800000 if UBOOT_ROMSIZE_KB_8192 + default 0xc00000 if UBOOT_ROMSIZE_KB_12288 + default 0x1000000 if UBOOT_ROMSIZE_KB_16384 + +config HAVE_INTEL_ME + bool "Platform requires Intel Management Engine" + help + Newer higher-end devices have an Intel Management Engine (ME) + which is a very large binary blob (typically 1.5MB) which is + required for the platform to work. This enforces a particular + SPI flash format. You will need to supply the me.bin file in + your board directory. + +config X86_RAMTEST + bool "Perform a simple RAM test after SDRAM initialisation" + help + If there is something wrong with SDRAM then the platform will + often crash within U-Boot or the kernel. This option enables a + very simple RAM test that quickly checks whether the SDRAM seems + to work correctly. It is not exhaustive but can save time by + detecting obvious failures. + +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + +menu "Display" + +config FRAMEBUFFER_SET_VESA_MODE + prompt "Set framebuffer graphics resolution" + bool + help + Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) + +choice + prompt "framebuffer graphics resolution" + default FRAMEBUFFER_VESA_MODE_117 + depends on FRAMEBUFFER_SET_VESA_MODE + help + This option sets the resolution used for the coreboot framebuffer (and + bootsplash screen). + +config FRAMEBUFFER_VESA_MODE_100 + bool "640x400 256-color" + +config FRAMEBUFFER_VESA_MODE_101 + bool "640x480 256-color" + +config FRAMEBUFFER_VESA_MODE_102 + bool "800x600 16-color" + +config FRAMEBUFFER_VESA_MODE_103 + bool "800x600 256-color" + +config FRAMEBUFFER_VESA_MODE_104 + bool "1024x768 16-color" + +config FRAMEBUFFER_VESA_MODE_105 + bool "1024x7686 256-color" + +config FRAMEBUFFER_VESA_MODE_106 + bool "1280x1024 16-color" + +config FRAMEBUFFER_VESA_MODE_107 + bool "1280x1024 256-color" + +config FRAMEBUFFER_VESA_MODE_108 + bool "80x60 text" + +config FRAMEBUFFER_VESA_MODE_109 + bool "132x25 text" + +config FRAMEBUFFER_VESA_MODE_10A + bool "132x43 text" + +config FRAMEBUFFER_VESA_MODE_10B + bool "132x50 text" + +config FRAMEBUFFER_VESA_MODE_10C + bool "132x60 text" + +config FRAMEBUFFER_VESA_MODE_10D + bool "320x200 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_10E + bool "320x200 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_10F + bool "320x200 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_110 + bool "640x480 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_111 + bool "640x480 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_112 + bool "640x480 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_113 + bool "800x600 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_114 + bool "800x600 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_115 + bool "800x600 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_116 + bool "1024x768 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_117 + bool "1024x768 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_118 + bool "1024x768 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_119 + bool "1280x1024 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_11A + bool "1280x1024 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_11B + bool "1280x1024 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_USER + bool "Manually select VESA mode" + +endchoice + +# Map the config names to an integer (KB). +config FRAMEBUFFER_VESA_MODE + prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER + hex + default 0x100 if FRAMEBUFFER_VESA_MODE_100 + default 0x101 if FRAMEBUFFER_VESA_MODE_101 + default 0x102 if FRAMEBUFFER_VESA_MODE_102 + default 0x103 if FRAMEBUFFER_VESA_MODE_103 + default 0x104 if FRAMEBUFFER_VESA_MODE_104 + default 0x105 if FRAMEBUFFER_VESA_MODE_105 + default 0x106 if FRAMEBUFFER_VESA_MODE_106 + default 0x107 if FRAMEBUFFER_VESA_MODE_107 + default 0x108 if FRAMEBUFFER_VESA_MODE_108 + default 0x109 if FRAMEBUFFER_VESA_MODE_109 + default 0x10A if FRAMEBUFFER_VESA_MODE_10A + default 0x10B if FRAMEBUFFER_VESA_MODE_10B + default 0x10C if FRAMEBUFFER_VESA_MODE_10C + default 0x10D if FRAMEBUFFER_VESA_MODE_10D + default 0x10E if FRAMEBUFFER_VESA_MODE_10E + default 0x10F if FRAMEBUFFER_VESA_MODE_10F + default 0x110 if FRAMEBUFFER_VESA_MODE_110 + default 0x111 if FRAMEBUFFER_VESA_MODE_111 + default 0x112 if FRAMEBUFFER_VESA_MODE_112 + default 0x113 if FRAMEBUFFER_VESA_MODE_113 + default 0x114 if FRAMEBUFFER_VESA_MODE_114 + default 0x115 if FRAMEBUFFER_VESA_MODE_115 + default 0x116 if FRAMEBUFFER_VESA_MODE_116 + default 0x117 if FRAMEBUFFER_VESA_MODE_117 + default 0x118 if FRAMEBUFFER_VESA_MODE_118 + default 0x119 if FRAMEBUFFER_VESA_MODE_119 + default 0x11A if FRAMEBUFFER_VESA_MODE_11A + default 0x11B if FRAMEBUFFER_VESA_MODE_11B + default 0x117 if FRAMEBUFFER_VESA_MODE_USER + +endmenu + +config TSC_CALIBRATION_BYPASS + bool "Bypass Time-Stamp Counter (TSC) calibration" + default n + help + By default U-Boot automatically calibrates Time-Stamp Counter (TSC) + running frequency via Model-Specific Register (MSR) and Programmable + Interval Timer (PIT). If the calibration does not work on your board, + select this option and provide a hardcoded TSC running frequency with + CONFIG_TSC_FREQ_IN_MHZ below. + + Normally this option should be turned on in a simulation environment + like qemu. + +config TSC_FREQ_IN_MHZ + int "Time-Stamp Counter (TSC) running frequency in MHz" + depends on TSC_CALIBRATION_BYPASS + default 1000 + help + The running frequency in MHz of Time-Stamp Counter (TSC). + +source "arch/x86/cpu/coreboot/Kconfig" + +source "arch/x86/cpu/ivybridge/Kconfig" + +source "arch/x86/cpu/queensbay/Kconfig" + +source "board/coreboot/coreboot/Kconfig" + +source "board/google/chromebook_link/Kconfig" + +source "board/intel/crownbay/Kconfig" + +endmenu diff --git a/arch/x86/Makefile b/arch/x86/Makefile new file mode 100644 index 0000000000..36a601822a --- /dev/null +++ b/arch/x86/Makefile @@ -0,0 +1,12 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/x86/cpu/start.o +ifeq ($(CONFIG_SPL_BUILD),y) +head-y += arch/x86/cpu/start16.o +head-y += arch/x86/cpu/resetvec.o +endif + +libs-y += arch/x86/cpu/ +libs-y += arch/x86/lib/ diff --git a/arch/x86/config.mk b/arch/x86/config.mk index b22959f54b..bb2da4637e 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -8,30 +8,22 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 PLATFORM_CPPFLAGS += -fno-strict-aliasing -PLATFORM_CPPFLAGS += -Wstrict-prototypes PLATFORM_CPPFLAGS += -mregparm=3 PLATFORM_CPPFLAGS += -fomit-frame-pointer -PF_CPPFLAGS_X86 := $(call cc-option, -ffreestanding) \ - $(call cc-option, -fno-toplevel-reorder, \ +PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ $(call cc-option, -fno-unit-at-a-time)) \ - $(call cc-option, -fno-stack-protector) \ $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0 +PLATFORM_CPPFLAGS += -march=i386 -m32 # Support generic board on x86 __HAVE_ARCH_GENERIC_BOARD := y PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden -PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions +PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -m elf_i386 LDFLAGS_FINAL += --gc-sections -pie LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 - -NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) -PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC)) - -export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC)) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 41555abc34..62e43c04e5 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -8,28 +8,15 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START-y = start.o -START-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o -COBJS = interrupts.o cpu.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START-y)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y = start.o +obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o +obj-y += interrupts.o cpu.o call64.o + +obj-$(CONFIG_SYS_COREBOOT) += coreboot/ +obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ +obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ +obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ +obj-y += lapic.o +obj-y += mtrr.o +obj-$(CONFIG_PCI) += pci.o +obj-y += turbo.o diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S new file mode 100644 index 0000000000..74dd5a89dc --- /dev/null +++ b/arch/x86/cpu/call64.S @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2014 Google, Inc + * Copyright (C) 1991, 1992, 1993 Linus Torvalds + * + * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +.code32 +.globl cpu_call64 +cpu_call64: + /* + * cpu_call64(ulong pgtable, ulong setup_base, ulong target) + * + * eax - pgtable + * edx - setup_base + * ecx - target + */ + cli + push %ecx /* arg2 = target */ + push %edx /* arg1 = setup_base */ + mov %eax, %ebx + + /* Load new GDT with the 64bit segments using 32bit descriptor */ + leal gdt, %eax + movl %eax, gdt+2 + lgdt gdt + + /* Enable PAE mode */ + movl $(X86_CR4_PAE), %eax + movl %eax, %cr4 + + /* Enable the boot page tables */ + leal (%ebx), %eax + movl %eax, %cr3 + + /* Enable Long mode in EFER (Extended Feature Enable Register) */ + movl $MSR_EFER, %ecx + rdmsr + btsl $_EFER_LME, %eax + wrmsr + + /* After gdt is loaded */ + xorl %eax, %eax + lldt %ax + movl $0x20, %eax + ltr %ax + + /* + * Setup for the jump to 64bit mode + * + * When the jump is performed we will be in long mode but + * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1 + * (and in turn EFER.LMA = 1). To jump into 64bit mode we use + * the new gdt/idt that has __KERNEL_CS with CS.L = 1. + * We place all of the values on our mini stack so lret can + * used to perform that far jump. See the gdt below. + */ + pop %esi /* setup_base */ + + pushl $0x10 + leal lret_target, %eax + pushl %eax + + /* Enter paged protected Mode, activating Long Mode */ + movl $(X86_CR0_PG | X86_CR0_PE), %eax + movl %eax, %cr0 + + /* Jump from 32bit compatibility mode into 64bit mode. */ + lret + +code64: +lret_target: + pop %eax /* target */ + mov %eax, %eax /* Clear bits 63:32 */ + jmp *%eax /* Jump to the 64-bit target */ + + .data +gdt: + .word gdt_end - gdt + .long gdt + .word 0 + .quad 0x0000000000000000 /* NULL descriptor */ + .quad 0x00af9a000000ffff /* __KERNEL_CS */ + .quad 0x00cf92000000ffff /* __KERNEL_DS */ + .quad 0x0080890000000000 /* TS descriptor */ + .quad 0x0000000000000000 /* TS continued */ +gdt_end: diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index c1568cacd0..84aeaf3edc 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -7,10 +7,11 @@ CROSS_COMPILE ?= i386-linux- -PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386 -Werror +PLATFORM_CPPFLAGS += -D__I386__ -Werror # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=0xffff0000 LDPPFLAGS += -DRESET_SEG_SIZE=0x10000 -LDPPFLAGS += -DRESET_VEC_LOC=0xfff0 -LDPPFLAGS += -DSTART_16=0xf800 +LDPPFLAGS += -DRESET_VEC_LOC=0xfffffff0 +LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) +LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)" diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig new file mode 100644 index 0000000000..e0e3c64506 --- /dev/null +++ b/arch/x86/cpu/coreboot/Kconfig @@ -0,0 +1,15 @@ +if TARGET_COREBOOT + +config SYS_COREBOOT + bool + default y + +config CBMEM_CONSOLE + bool + default y + +config VIDEO_COREBOOT + bool + default y + +endif diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index 18fa115826..b6e870a7cb 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -13,31 +13,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(SOC).o - -SOBJS-$(CONFIG_SYS_COREBOOT) += car.o -COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o -COBJS-$(CONFIG_SYS_COREBOOT) += tables.o -COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o -COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o -COBJS-$(CONFIG_SYS_COREBOOT) += timestamp.o -COBJS-$(CONFIG_PCI) += pci.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += car.o +obj-y += coreboot.o +obj-y += tables.o +obj-y += sdram.o +obj-y += timestamp.o +obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/asm-offsets.c b/arch/x86/cpu/coreboot/asm-offsets.c deleted file mode 100644 index d65c6ab1b0..0000000000 --- a/arch/x86/cpu/coreboot/asm-offsets.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int main(void) -{ - DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off)); - return 0; -} diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 1ce3b5ef6c..4cdd0d4035 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -3,7 +3,7 @@ * (C) Copyright 2008 * Graeme Russ, graeme.russ@gmail.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -13,25 +13,26 @@ #include #include #include +#include #include -#include -#include +#include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; -/* - * Miscellaneous platform dependent initializations - */ -int cpu_init_f(void) +int arch_cpu_init(void) { int ret = get_coreboot_info(&lib_sysinfo); - if (ret != 0) + if (ret != 0) { printf("Failed to parse coreboot tables.\n"); + return ret; + } timestamp_init(); - return ret; + return x86_cpu_init_f(); } int board_early_init_f(void) @@ -39,38 +40,9 @@ int board_early_init_f(void) return 0; } -int board_early_init_r(void) -{ - /* CPU Speed to 100MHz */ - gd->cpu_clk = 100000000; - - /* Crystal is 33.000MHz */ - gd->bus_clk = 33000000; - - return 0; -} - -void show_boot_progress(int val) +int print_cpuinfo(void) { -#if MIN_PORT80_KCLOCKS_DELAY - /* - * Scale the time counter reading to avoid using 64 bit arithmetics. - * Can't use get_timer() here becuase it could be not yet - * initialized or even implemented. - */ - if (!gd->arch.tsc_prev) { - gd->arch.tsc_base_kclocks = rdtsc() / 1000; - gd->arch.tsc_prev = 0; - } else { - uint32_t now; - - do { - now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; - } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); - gd->arch.tsc_prev = now; - } -#endif - outb(val, 0x80); + return default_print_cpuinfo(); } int last_stage_init(void) @@ -93,12 +65,7 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } -#define MTRR_TYPE_WP 5 -#define MTRRcap_MSR 0xfe -#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) -#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) - -int board_final_cleanup(void) +void board_final_cleanup(void) { /* Un-cache the ROM so the kernel has one * more MTRR available. @@ -106,22 +73,22 @@ int board_final_cleanup(void) * Coreboot should have assigned this to the * top available variable MTRR. */ - u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; - u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; + u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1; + u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff; /* Make sure this MTRR is the correct Write-Protected type */ - if (top_type == MTRR_TYPE_WP) { - disable_caches(); - wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); - wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); - enable_caches(); + if (top_type == MTRR_TYPE_WRPROT) { + struct mtrr_state state; + + mtrr_open(&state); + wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); + wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); + mtrr_close(&state); } /* Issue SMI to Coreboot to lock down ME and registers */ printf("Finalizing Coreboot\n"); outb(0xcb, 0xb2); - - return 0; } void panic_puts(const char *str) @@ -132,3 +99,8 @@ void panic_puts(const char *str) while (*str) NS16550_putc(port, *str++); } + +int misc_init_r(void) +{ + return 0; +} diff --git a/arch/x86/cpu/coreboot/ipchecksum.c b/arch/x86/cpu/coreboot/ipchecksum.c deleted file mode 100644 index 57733d8f0d..0000000000 --- a/arch/x86/cpu/coreboot/ipchecksum.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * It has originally been taken from the FreeBSD project. - * - * Copyright (c) 2001 Charles Mott - * Copyright (c) 2008 coresystems GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include - -unsigned short ipchksum(const void *vptr, unsigned long nbytes) -{ - int sum, oddbyte; - const unsigned short *ptr = vptr; - - sum = 0; - while (nbytes > 1) { - sum += *ptr++; - nbytes -= 2; - } - if (nbytes == 1) { - oddbyte = 0; - ((u8 *)&oddbyte)[0] = *(u8 *) ptr; - ((u8 *)&oddbyte)[1] = 0; - sum += oddbyte; - } - sum = (sum >> 16) + (sum & 0xffff); - sum += (sum >> 16); - return ~sum; -} diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 7484c5c02a..c9983f1588 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -6,21 +6,21 @@ * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include -static struct pci_controller coreboot_hose; +DECLARE_GLOBAL_DATA_PTR; static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) { u8 secondary; hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); - hose->last_busno = max(hose->last_busno, secondary); + hose->last_busno = max(hose->last_busno, (int)secondary); pci_hose_scan_bus(hose, secondary); } @@ -31,19 +31,37 @@ static struct pci_config_table pci_coreboot_config_table[] = { {} }; -void pci_init_board(void) +void board_pci_setup_hose(struct pci_controller *hose) { - coreboot_hose.config_table = pci_coreboot_config_table; - coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0; + hose->config_table = pci_coreboot_config_table; + hose->first_busno = 0; + hose->last_busno = 0; - pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, - PCI_REGION_MEM); - coreboot_hose.region_count = 1; + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); - pci_setup_type1(&coreboot_hose); + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); - pci_register_hose(&coreboot_hose); + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); - pci_hose_scan(&coreboot_hose); + pci_set_region(hose->regions + 3, + 0, + 0, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 959feaaea3..e98a2302e7 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -11,8 +11,10 @@ #include #include #include +#include #include #include +#include #include #include @@ -22,7 +24,7 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) { int i; - unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries); + unsigned num_entries = min((unsigned)lib_sysinfo.n_memranges, max_entries); if (num_entries < lib_sysinfo.n_memranges) { printf("Warning: Limiting e820 map to %d entries.\n", num_entries); @@ -79,7 +81,7 @@ ulong board_get_usable_ram_top(ulong total_size) return (ulong)dest_addr; } -int dram_init_f(void) +int dram_init(void) { int i; phys_size_t ram_size = 0; @@ -94,10 +96,11 @@ int dram_init_f(void) gd->ram_size = ram_size; if (ram_size == 0) return -1; - return 0; + + return calculate_relocation_address(); } -int dram_init_banksize(void) +void dram_init_banksize(void) { int i, j; @@ -114,10 +117,4 @@ int dram_init_banksize(void) } } } - return 0; -} - -int dram_init(void) -{ - return dram_init_banksize(); } diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index b116d59555..2b12b19ba2 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -4,34 +4,13 @@ * Copyright (C) 2008 Advanced Micro Devices, Inc. * Copyright (C) 2009 coresystems GmbH * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include -#include -#include -#include +#include +#include +#include /* * This needs to be in the .data section so that it's copied over during @@ -152,11 +131,11 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) return 0; /* Make sure the checksums match. */ - if (ipchksum((u16 *) header, sizeof(*header)) != 0) + if (!ip_checksum_ok(header, sizeof(*header))) return -1; - if (ipchksum((u16 *) (ptr + sizeof(*header)), - header->table_bytes) != header->table_checksum) + if (compute_ip_checksum(ptr + sizeof(*header), header->table_bytes) != + header->table_checksum) return -1; /* Now, walk the tables. */ diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index bd3558a021..0edee6bd2c 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -3,18 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -38,9 +27,27 @@ static struct timestamp_table *ts_table __attribute__((section(".data"))); void timestamp_init(void) { +#ifdef CONFIG_SYS_X86_TSC_TIMER + uint64_t base_time; +#endif + ts_table = lib_sysinfo.tstamp_table; #ifdef CONFIG_SYS_X86_TSC_TIMER - timer_set_base(ts_table->base_time); + /* + * If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value + * of base_time in coreboot's timestamp table as our timer base, + * otherwise TSC counter value will be used. + * + * Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, + * the value of base_time in the timestamp table is still zero, so + * we must exclude this case too (this is currently seen on booting + * coreboot in qemu) + */ + if (ts_table && ts_table->base_time) + base_time = ts_table->base_time; + else + base_time = rdtsc(); + timer_set_base(base_time); #endif timestamp_add_now(TS_U_BOOT_INITTED); } diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 623e3af61f..ed7905c1d7 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -13,17 +13,26 @@ * Sysgo Real-Time Solutions, GmbH * Alex Zuepke * + * Part of this file is adapted from coreboot + * src/arch/x86/lib/cpu.c + * * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include +#include #include +#include +#include #include #include #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * Constructor for a conventional segment GDT (or LDT) entry * This is a macro so it can be used in initialisers @@ -40,6 +49,52 @@ struct gdt_ptr { u32 ptr; } __packed; +struct cpu_device_id { + unsigned vendor; + unsigned device; +}; + +struct cpuinfo_x86 { + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; +}; + +/* + * List of cpu vendor strings along with their normalized + * id values. + */ +static struct { + int vendor; + const char *name; +} x86_vendors[] = { + { X86_VENDOR_INTEL, "GenuineIntel", }, + { X86_VENDOR_CYRIX, "CyrixInstead", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_UMC, "UMC UMC UMC ", }, + { X86_VENDOR_NEXGEN, "NexGenDriven", }, + { X86_VENDOR_CENTAUR, "CentaurHauls", }, + { X86_VENDOR_RISE, "RiseRiseRise", }, + { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, + { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, + { X86_VENDOR_NSC, "Geode by NSC", }, + { X86_VENDOR_SIS, "SiS SiS SiS ", }, +}; + +static const char *const x86_vendor_name[] = { + [X86_VENDOR_INTEL] = "Intel", + [X86_VENDOR_CYRIX] = "Cyrix", + [X86_VENDOR_AMD] = "AMD", + [X86_VENDOR_UMC] = "UMC", + [X86_VENDOR_NEXGEN] = "NexGen", + [X86_VENDOR_CENTAUR] = "Centaur", + [X86_VENDOR_RISE] = "Rise", + [X86_VENDOR_TRANSMETA] = "Transmeta", + [X86_VENDOR_NSC] = "NSC", + [X86_VENDOR_SIS] = "SiS", +}; + static void load_ds(u32 segment) { asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); @@ -69,7 +124,7 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries) { struct gdt_ptr gdt; - gdt.len = (num_entries * 8) - 1; + gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; gdt.ptr = (u32)boot_gdt; asm volatile("lgdtl %0\n" : : "m" (gdt)); @@ -89,10 +144,13 @@ void setup_gdt(gd_t *id, u64 *gdt_addr) (ulong)&id->arch.gd_addr, 0xfffff); /* 16-bit CS: code, read/execute, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff); + gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); /* 16-bit DS: data, read/write, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff); + gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); + + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); load_ds(X86_GDT_ENTRY_32BIT_DS); @@ -112,6 +170,134 @@ int __weak x86_cleanup_before_linux(void) return 0; } +/* + * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected + * by the fact that they preserve the flags across the division of 5/2. + * PII and PPro exhibit this behavior too, but they have cpuid available. + */ + +/* + * Perform the Cyrix 5/2 test. A Cyrix won't change + * the flags, while other 486 chips will. + */ +static inline int test_cyrix_52div(void) +{ + unsigned int test; + + __asm__ __volatile__( + "sahf\n\t" /* clear flags (%eax = 0x0005) */ + "div %b2\n\t" /* divide 5 by 2 */ + "lahf" /* store flags into %ah */ + : "=a" (test) + : "0" (5), "q" (2) + : "cc"); + + /* AH is 0x02 on Cyrix after the divide.. */ + return (unsigned char) (test >> 8) == 0x02; +} + +/* + * Detect a NexGen CPU running without BIOS hypercode new enough + * to have CPUID. (Thanks to Herbert Oppmann) + */ + +static int deep_magic_nexgen_probe(void) +{ + int ret; + + __asm__ __volatile__ ( + " movw $0x5555, %%ax\n" + " xorw %%dx,%%dx\n" + " movw $2, %%cx\n" + " divw %%cx\n" + " movl $0, %%eax\n" + " jnz 1f\n" + " movl $1, %%eax\n" + "1:\n" + : "=a" (ret) : : "cx", "dx"); + return ret; +} + +static bool has_cpuid(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + +static bool has_mtrr(void) +{ + return cpuid_edx(0x00000001) & (1 << 12) ? true : false; +} + +static int build_vendor_name(char *vendor_name) +{ + struct cpuid_result result; + result = cpuid(0x00000000); + unsigned int *name_as_ints = (unsigned int *)vendor_name; + + name_as_ints[0] = result.ebx; + name_as_ints[1] = result.edx; + name_as_ints[2] = result.ecx; + + return result.eax; +} + +static void identify_cpu(struct cpu_device_id *cpu) +{ + char vendor_name[16]; + int i; + + vendor_name[0] = '\0'; /* Unset */ + cpu->device = 0; /* fix gcc 4.4.4 warning */ + + /* Find the id and vendor_name */ + if (!has_cpuid()) { + /* Its a 486 if we can modify the AC flag */ + if (flag_is_changeable_p(X86_EFLAGS_AC)) + cpu->device = 0x00000400; /* 486 */ + else + cpu->device = 0x00000300; /* 386 */ + if ((cpu->device == 0x00000400) && test_cyrix_52div()) { + memcpy(vendor_name, "CyrixInstead", 13); + /* If we ever care we can enable cpuid here */ + } + /* Detect NexGen with old hypercode */ + else if (deep_magic_nexgen_probe()) + memcpy(vendor_name, "NexGenDriven", 13); + } + if (has_cpuid()) { + int cpuid_level; + + cpuid_level = build_vendor_name(vendor_name); + vendor_name[12] = '\0'; + + /* Intel-defined flags: level 0x00000001 */ + if (cpuid_level >= 0x00000001) { + cpu->device = cpuid_eax(0x00000001); + } else { + /* Have CPUID level 0 only unheard of */ + cpu->device = 0x00000400; + } + } + cpu->vendor = X86_VENDOR_UNKNOWN; + for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { + if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { + cpu->vendor = x86_vendors[i].vendor; + break; + } + } +} + +static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) +{ + c->x86 = (tfms >> 8) & 0xf; + c->x86_model = (tfms >> 4) & 0xf; + c->x86_mask = tfms & 0xf; + if (c->x86 == 0xf) + c->x86 += (tfms >> 20) & 0xff; + if (c->x86 >= 0x6) + c->x86_model += ((tfms >> 16) & 0xF) << 4; +} + int x86_cpu_init_f(void) { const u32 em_rst = ~X86_CR0_EM; @@ -125,17 +311,24 @@ int x86_cpu_init_f(void) "movl %%eax, %%cr0\n" \ : : "i" (em_rst), "i" (mp_ne_set) : "eax"); - return 0; -} -int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f"))); + /* identify CPU via cpuid and store the decoded info into gd->arch */ + if (has_cpuid()) { + struct cpu_device_id cpu; + struct cpuinfo_x86 c; + + identify_cpu(&cpu); + get_fms(&c, cpu.device); + gd->arch.x86 = c.x86; + gd->arch.x86_vendor = cpu.vendor; + gd->arch.x86_model = c.x86_model; + gd->arch.x86_mask = c.x86_mask; + gd->arch.x86_device = cpu.device; + + gd->arch.has_mtrr = has_mtrr(); + } -int x86_cpu_init_r(void) -{ - /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts(); return 0; } -int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); void x86_enable_caches(void) { @@ -195,14 +388,13 @@ asm(".globl generate_gpf\n" "generate_gpf:\n" "ljmp $0x70, $0x47114711\n"); -void __reset_cpu(ulong addr) +__weak void reset_cpu(ulong addr) { printf("Resetting using x86 Triple Fault\n"); set_vector(13, generate_gpf); /* general protection fault handler */ set_vector(8, generate_gpf); /* double fault handler */ generate_gpf(); /* start the show */ } -void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); int dcache_status(void) { @@ -240,3 +432,164 @@ int icache_status(void) { return 1; } + +void cpu_enable_paging_pae(ulong cr3) +{ + __asm__ __volatile__( + /* Load the page table address */ + "movl %0, %%cr3\n" + /* Enable pae */ + "movl %%cr4, %%eax\n" + "orl $0x00000020, %%eax\n" + "movl %%eax, %%cr4\n" + /* Enable paging */ + "movl %%cr0, %%eax\n" + "orl $0x80000000, %%eax\n" + "movl %%eax, %%cr0\n" + : + : "r" (cr3) + : "eax"); +} + +void cpu_disable_paging_pae(void) +{ + /* Turn off paging */ + __asm__ __volatile__ ( + /* Disable paging */ + "movl %%cr0, %%eax\n" + "andl $0x7fffffff, %%eax\n" + "movl %%eax, %%cr0\n" + /* Disable pae */ + "movl %%cr4, %%eax\n" + "andl $0xffffffdf, %%eax\n" + "movl %%eax, %%cr4\n" + : + : + : "eax"); +} + +static bool can_detect_long_mode(void) +{ + return cpuid_eax(0x80000000) > 0x80000000UL; +} + +static bool has_long_mode(void) +{ + return cpuid_edx(0x80000001) & (1 << 29) ? true : false; +} + +int cpu_has_64bit(void) +{ + return has_cpuid() && can_detect_long_mode() && + has_long_mode(); +} + +const char *cpu_vendor_name(int vendor) +{ + const char *name; + name = ""; + if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && + (x86_vendor_name[vendor] != 0)) + name = x86_vendor_name[vendor]; + + return name; +} + +char *cpu_get_name(char *name) +{ + unsigned int *name_as_ints = (unsigned int *)name; + struct cpuid_result regs; + char *ptr; + int i; + + /* This bit adds up to 48 bytes */ + for (i = 0; i < 3; i++) { + regs = cpuid(0x80000002 + i); + name_as_ints[i * 4 + 0] = regs.eax; + name_as_ints[i * 4 + 1] = regs.ebx; + name_as_ints[i * 4 + 2] = regs.ecx; + name_as_ints[i * 4 + 3] = regs.edx; + } + name[CPU_MAX_NAME_LEN - 1] = '\0'; + + /* Skip leading spaces. */ + ptr = name; + while (*ptr == ' ') + ptr++; + + return ptr; +} + +int default_print_cpuinfo(void) +{ + printf("CPU: %s, vendor %s, device %xh\n", + cpu_has_64bit() ? "x86_64" : "x86", + cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); + + return 0; +} + +#define PAGETABLE_SIZE (6 * 4096) + +/** + * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode + * + * @pgtable: Pointer to a 24iKB block of memory + */ +static void build_pagetable(uint32_t *pgtable) +{ + uint i; + + memset(pgtable, '\0', PAGETABLE_SIZE); + + /* Level 4 needs a single entry */ + pgtable[0] = (uint32_t)&pgtable[1024] + 7; + + /* Level 3 has one 64-bit entry for each GiB of memory */ + for (i = 0; i < 4; i++) { + pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + + 0x1000 * i + 7; + } + + /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ + for (i = 0; i < 2048; i++) + pgtable[2048 + i * 2] = 0x183 + (i << 21UL); +} + +int cpu_jump_to_64bit(ulong setup_base, ulong target) +{ + uint32_t *pgtable; + + pgtable = memalign(4096, PAGETABLE_SIZE); + if (!pgtable) + return -ENOMEM; + + build_pagetable(pgtable); + cpu_call64((ulong)pgtable, setup_base, target); + free(pgtable); + + return -EFAULT; +} + +void show_boot_progress(int val) +{ +#if MIN_PORT80_KCLOCKS_DELAY + /* + * Scale the time counter reading to avoid using 64 bit arithmetics. + * Can't use get_timer() here becuase it could be not yet + * initialized or even implemented. + */ + if (!gd->arch.tsc_prev) { + gd->arch.tsc_base_kclocks = rdtsc() / 1000; + gd->arch.tsc_prev = 0; + } else { + uint32_t now; + + do { + now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; + } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); + gd->arch.tsc_prev = now; + } +#endif + outb(val, POST_PORT); +} diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 6f3d85fab0..a21d2a6c50 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -31,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; "pushl $"#x"\n" \ "jmp irq_common_entry\n" -void dump_regs(struct irq_regs *regs) +static void dump_regs(struct irq_regs *regs) { unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; @@ -128,9 +129,6 @@ int cpu_init_interrupts(void) int irq_entry_size = irq_1 - irq_0; void *irq_entry = (void *)irq_0; - /* Just in case... */ - disable_interrupts(); - /* Setup the IDT */ for (i = 0; i < 256; i++) { idt[i].access = 0x8e; @@ -146,9 +144,6 @@ int cpu_init_interrupts(void) load_idt(&idt_ptr); - /* It is now safe to enable interrupts */ - enable_interrupts(); - return 0; } @@ -172,6 +167,25 @@ int disable_interrupts(void) return flags & X86_EFLAGS_IF; } +int interrupt_init(void) +{ + /* Just in case... */ + disable_interrupts(); + +#ifdef CONFIG_SYS_PCAT_INTERRUPTS + /* Initialize the master/slave i8259 pic */ + i8259_init(); +#endif + + /* Initialize core interrupt and exception functionality of CPU */ + cpu_init_interrupts(); + + /* It is now safe to enable interrupts */ + enable_interrupts(); + + return 0; +} + /* IRQ Low-Level Service Routine */ void irq_llsr(struct irq_regs *regs) { @@ -603,31 +617,3 @@ asm(".globl irq_common_entry\n" \ DECLARE_INTERRUPT(253) \ DECLARE_INTERRUPT(254) \ DECLARE_INTERRUPT(255)); - -#if defined(CONFIG_INTEL_CORE_ARCH) -/* - * Get the number of CPU time counter ticks since it was read first time after - * restart. This yields a free running counter guaranteed to take almost 6 - * years to wrap around even at 100GHz clock rate. - */ -u64 get_ticks(void) -{ - u64 now_tick = rdtsc(); - - if (!gd->arch.tsc_base) - gd->arch.tsc_base = now_tick; - - return now_tick - gd->arch.tsc_base; -} - -#define PLATFORM_INFO_MSR 0xce - -unsigned long get_tbclk(void) -{ - u32 ratio; - u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); - - ratio = (platform_info >> 8) & 0xff; - return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */ -} -#endif diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig new file mode 100644 index 0000000000..e4595be3ae --- /dev/null +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -0,0 +1,144 @@ +# +# From Coreboot src/northbridge/intel/sandybridge/Kconfig +# +# Copyright (C) 2010 Google Inc. +# +# SPDX-License-Identifier: GPL-2.0 + + +config NORTHBRIDGE_INTEL_SANDYBRIDGE + bool + select CACHE_MRC_BIN + select CPU_INTEL_MODEL_206AX + +config NORTHBRIDGE_INTEL_IVYBRIDGE + bool + select CACHE_MRC_BIN + select CPU_INTEL_MODEL_306AX + +if NORTHBRIDGE_INTEL_SANDYBRIDGE + +config VGA_BIOS_ID + string + default "8086,0106" + +config CACHE_MRC_SIZE_KB + int + default 256 + +config DCACHE_RAM_BASE + hex + default 0xff7f0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +endif + +if NORTHBRIDGE_INTEL_IVYBRIDGE + +config VGA_BIOS_ID + string + default "8086,0166" + +config EXTERNAL_MRC_BLOB + bool + default n + +config CACHE_MRC_SIZE_KB + int + default 512 + +config DCACHE_RAM_BASE + hex + default 0xff7e0000 + +config DCACHE_RAM_SIZE + hex + default 0x20000 + +endif + +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE + +config HAVE_MRC + bool "Add a System Agent binary" + help + Select this option to add a System Agent binary to + the resulting U-Boot image. MRC stands for Memory Reference Code. + It is a binary blob which U-Boot uses to set up SDRAM. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x4000 + help + This is the amount of CAR (Cache as RAM) reserved for use by the + memory reference code. This should be set to 16KB (0x4000 hex) + so that MRC has enough space to run. + +config MRC_FILE + string "Intel System Agent path and filename" + depends on HAVE_MRC + default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE + default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE + help + The path and filename of the file to use as System Agent + binary. + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMM_TSEG + select ARCH_BOOTBLOCK_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select SMP + select SSE2 + select UDELAY_LAPIC + select CPU_MICROCODE_IN_CBFS + select TSC_SYNC_MFENCE + select HAVE_INTEL_ME + select X86_RAMTEST + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + help + Virtual Machine Extensions are provided in many x86 CPUs. These + provide various facilities for allowing a host OS to provide an + environment where potentially several guest OSes have only + limited access to the underlying hardware. This is achieved + without resorting to software trapping and/or instruction set + emulation (which would be very slow). + + Intel's implementation of this is called VT-x. This option enables + VT-x this so that the OS that is booted by U-Boot can make use of + these facilities. If this option is not enabled, then the host OS + will be unable to support virtualisation, or it will run very + slowly. + +endif + +config CPU_INTEL_SOCKET_RPGA989 + bool + +if CPU_INTEL_SOCKET_RPGA989 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + select CACHE_AS_RAM + +config CACHE_MRC_BIN + bool + default n + +endif diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile new file mode 100644 index 0000000000..3576b83266 --- /dev/null +++ b/arch/x86/cpu/ivybridge/Makefile @@ -0,0 +1,25 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += bd82x6x.o +obj-y += car.o +obj-y += cpu.o +obj-y += early_init.o +obj-y += early_me.o +obj-y += gma.o +obj-y += lpc.o +obj-y += me_status.o +obj-y += model_206ax.o +obj-y += microcode_intel.o +obj-y += mrccache.o +obj-y += northbridge.o +obj-y += pch.o +obj-y += pci.o +obj-y += report_platform.o +obj-y += sata.o +obj-y += sdram.o +obj-y += usb_ehci.o +obj-y += usb_xhci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c new file mode 100644 index 0000000000..65a17d3e7f --- /dev/null +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void bd82x6x_pci_init(pci_dev_t dev) +{ + u16 reg16; + u8 reg8; + + debug("bd82x6x PCI init.\n"); + /* Enable Bus Master */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* This device has no interrupt */ + pci_write_config8(dev, INTR, 0xff); + + /* disable parity error response and SERR */ + reg16 = pci_read_config16(dev, BCTRL); + reg16 &= ~(1 << 0); + reg16 &= ~(1 << 1); + pci_write_config16(dev, BCTRL, reg16); + + /* Master Latency Count must be set to 0x04! */ + reg8 = pci_read_config8(dev, SMLT); + reg8 &= 0x07; + reg8 |= (0x04 << 3); + pci_write_config8(dev, SMLT, reg8); + + /* Will this improve throughput of bus masters? */ + pci_write_config8(dev, PCI_MIN_GNT, 0x06); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, PSTS); + /* reg16 |= 0xf900; */ + pci_write_config16(dev, PSTS, reg16); + + reg16 = pci_read_config16(dev, SECSTS); + /* reg16 |= 0xf900; */ + pci_write_config16(dev, SECSTS, reg16); +} + +#define PCI_BRIDGE_UPDATE_COMMAND +void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) +{ + uint16_t command; + + command = pci_read_config16(dev, PCI_COMMAND); + command |= PCI_COMMAND_IO; +#ifdef PCI_BRIDGE_UPDATE_COMMAND + /* + * If we write to PCI_COMMAND, on some systems this will cause the + * ROM and APICs to become invisible. + */ + debug("%x cmd <- %02x\n", dev, command); + pci_write_config16(dev, PCI_COMMAND, command); +#else + printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); +#endif +} + +void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) +{ + uint16_t ctrl; + + ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + ctrl |= PCI_COMMAND_IO; + ctrl |= PCI_BRIDGE_CTL_VGA; + debug("%x bridge ctrl <- %04x\n", dev, ctrl); + pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + + bd82x6x_pci_dev_enable_resources(dev); +} + +int bd82x6x_init_pci_devices(void) +{ + const void *blob = gd->fdt_blob; + struct pci_controller *hose; + struct x86_cpu_priv *cpu; + int sata_node, gma_node; + int ret; + + hose = pci_bus_to_hose(0); + lpc_enable(PCH_LPC_DEV); + lpc_init(hose, PCH_LPC_DEV); + sata_node = fdtdec_next_compatible(blob, 0, + COMPAT_INTEL_PANTHERPOINT_AHCI); + if (sata_node < 0) { + debug("%s: Cannot find SATA node\n", __func__); + return -EINVAL; + } + bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); + bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); + bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); + + cpu = calloc(1, sizeof(*cpu)); + if (!cpu) + return -ENOMEM; + model_206ax_init(cpu); + + gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); + if (gma_node < 0) { + debug("%s: Cannot find GMA node\n", __func__); + return -EINVAL; + } + ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob, + gma_node); + if (ret) + return ret; + + return 0; +} + +int bd82x6x_init(void) +{ + const void *blob = gd->fdt_blob; + int sata_node; + + sata_node = fdtdec_next_compatible(blob, 0, + COMPAT_INTEL_PANTHERPOINT_AHCI); + if (sata_node < 0) { + debug("%s: Cannot find SATA node\n", __func__); + return -EINVAL; + } + + bd82x6x_pci_init(PCH_DEV); + bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); + northbridge_enable(PCH_DEV); + northbridge_init(PCH_DEV); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S new file mode 100644 index 0000000000..9441666f5a --- /dev/null +++ b/arch/x86/cpu/ivybridge/car.S @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc + * + * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Kyösti Mälkki + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) +#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache 4GB - MRC_SIZE_KB for MRC */ +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) + +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) + +#define NOEVICTMOD_MSR 0x2e0 + + /* + * Note: ebp must not be touched in this code as it holds the BIST + * value (built-in self test). We preserve this value until it can + * be written to global_data when CAR is ready for use. + */ +.globl car_init +car_init: + post_code(POST_CAR_START) + + /* Send INIT IPI to all excluding ourself */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* TODO: Load microcode later - the 'no eviction' mode breaks this */ + movl $MSR_IA32_UCODE_WRITE, %ecx + xorl %edx, %edx + movl $_dt_ucode_base_size, %eax + movl (%eax), %eax + addl $UCODE_HEADER_LEN, %eax + wrmsr + + post_code(POST_CAR_SIPI) + /* Zero out all fixed range and variable range MTRRs */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + post_code(POST_CAR_MTRR) + /* Configure the default memory type to uncacheable */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(POST_CAR_UNCACHEABLE) + /* Set Cache-as-RAM base address */ + movl $(MTRR_PHYS_BASE_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask */ + movl $(MTRR_PHYS_MASK_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(POST_CAR_MASK) + + /* Enable MTRR */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0) */ + movl %cr0, %eax + andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NOEVICTMOD_MSR, %ecx + rdmsr + orl $1, %eax + andl $~2, %eax + wrmsr + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + xorl %eax, %eax + rep stosl + + /* enable the 'no eviction run' state */ + movl $NOEVICTMOD_MSR, %ecx + rdmsr + orl $3, %eax + wrmsr + + post_code(POST_CAR_FILL) + /* Enable Cache-as-RAM mode by disabling cache */ + movl %cr0, %eax + orl $X86_CR0_CD, %eax + movl %eax, %cr0 + + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRR_PHYS_BASE_MSR(1), %ecx + xorl %edx, %edx + movl $car_init_ret, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + post_code(POST_CAR_ROM_CACHE) +#ifdef CONFIG_CACHE_MRC_BIN + /* Enable caching for ram init code to run faster */ + movl $MTRR_PHYS_BASE_MSR(2), %ecx + movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRR_PHYS_MASK_MSR(2), %ecx + movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + + post_code(POST_CAR_MRC_CACHE) + /* Enable cache */ + movl %cr0, %eax + andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax + movl %eax, %cr0 + + post_code(POST_CAR_CPU_CACHE) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + /* return */ + jmp car_init_ret + +.globl car_uninit +car_uninit: + /* Disable cache */ + movl %cr0, %eax + orl $X86_CR0_CD, %eax + movl %eax, %cr0 + + /* Disable MTRRs */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~MTRR_DEF_TYPE_EN), %eax + wrmsr + + /* Disable the no-eviction run state */ + movl NOEVICTMOD_MSR, %ecx + rdmsr + andl $~2, %eax + wrmsr + + invd + + /* Disable the no-eviction mode */ + rdmsr + andl $~1, %eax + wrmsr + +#ifdef CONFIG_CACHE_MRC_BIN + /* Clear the MTRR that was used to cache MRC */ + xorl %eax, %eax + xorl %edx, %edx + movl $MTRR_PHYS_BASE_MSR(2), %ecx + wrmsr + movl $MTRR_PHYS_MASK_MSR(2), %ecx + wrmsr +#endif + + /* Enable MTRRs */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + invd + + ret + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F + .word 0x210, 0x211, 0x212, 0x213 +mtrr_table_end: + + .align 4 +_dt_ucode_base_size: + /* These next two fields are filled in by ifdtool */ + .long 0 /* microcode base */ + .long 0 /* microcode size */ diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c new file mode 100644 index 0000000000..e9253100f6 --- /dev/null +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2014 Google, Inc + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * Some portions from coreboot src/mainboard/google/link/romstage.c + * and src/cpu/intel/model_206ax/bootblock.c + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) +{ + /* Enable port 80 POST on LPC */ + pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + clrbits_le32(RCB_REG(GCS), 4); +} + +/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) +{ + u8 reg8; + + pci_hose_read_config_byte(hose, dev, 0xdc, ®8); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_hose_write_config_byte(hose, dev, 0xdc, reg8); +} + +static int set_flex_ratio_to_tdp_nominal(void) +{ + msr_t flex_ratio, msr; + u8 nominal_ratio; + + /* Minimum CPU revision for configurable TDP support */ + if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) + return -EINVAL; + + /* Check for Flex Ratio support */ + flex_ratio = msr_read(MSR_FLEX_RATIO); + if (!(flex_ratio.lo & FLEX_RATIO_EN)) + return -EINVAL; + + /* Check for >0 configurable TDPs */ + msr = msr_read(MSR_PLATFORM_INFO); + if (((msr.hi >> 1) & 3) == 0) + return -EINVAL; + + /* Use nominal TDP ratio for flex ratio */ + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + nominal_ratio = msr.lo & 0xff; + + /* See if flex ratio is already set to nominal TDP ratio */ + if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) + return 0; + + /* Set flex ratio to nominal TDP ratio */ + flex_ratio.lo &= ~0xff00; + flex_ratio.lo |= nominal_ratio << 8; + flex_ratio.lo |= FLEX_RATIO_LOCK; + msr_write(MSR_FLEX_RATIO, flex_ratio); + + /* Set flex ratio in soft reset data register bits 11:6 */ + clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, + (nominal_ratio & 0x3f) << 6); + + /* Set soft reset control to use register value */ + setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); + + /* Issue warm reset, will be "CPU only" due to soft reset data */ + outb(0x0, PORT_RESET); + outb(0x6, PORT_RESET); + cpu_hlt(); + + /* Not reached */ + return -EINVAL; +} + +static void set_spi_speed(void) +{ + u32 fdod; + + /* Observe SPI Descriptor Component Section 0 */ + writel(0x1000, RCB_REG(SPI_DESC_COMP0)); + + /* Extract the1 Write/Erase SPI Frequency from descriptor */ + fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); + fdod >>= 24; + fdod &= 7; + + /* Set Software Sequence frequency to match */ + clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); +} + +int arch_cpu_init(void) +{ + const void *blob = gd->fdt_blob; + struct pci_controller *hose; + int node; + int ret; + + post_code(POST_CPU_INIT); + timer_set_base(rdtsc()); + + ret = x86_cpu_init_f(); + if (ret) + return ret; + + ret = pci_early_init_hose(&hose); + if (ret) + return ret; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + if (node < 0) + return -ENOENT; + ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); + if (ret) + return ret; + + enable_spi_prefetch(hose, PCH_LPC_DEV); + + /* This is already done in start.S, but let's do it in C */ + enable_port80_on_lpc(hose, PCH_LPC_DEV); + + set_spi_speed(); + + /* + * We should do as little as possible before the serial console is + * up. Perhaps this should move to later. Our next lot of init + * happens in print_cpuinfo() when we have a console + */ + ret = set_flex_ratio_to_tdp_nominal(); + if (ret) + return ret; + + return 0; +} + +static int enable_smbus(void) +{ + pci_dev_t dev; + uint16_t value; + + /* Set the SMBus device statically. */ + dev = PCI_BDF(0x0, 0x1f, 0x3); + + /* Check to make sure we've got the right device. */ + value = pci_read_config16(dev, 0x0); + if (value != 0x8086) { + printf("SMBus controller not found\n"); + return -ENOSYS; + } + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + debug("SMBus controller enabled\n"); + + return 0; +} + +#define PCH_EHCI0_TEMP_BAR0 0xe8000000 +#define PCH_EHCI1_TEMP_BAR0 0xe8000400 +#define PCH_XHCI_TEMP_BAR0 0xe8001000 + +/* + * Setup USB controller MMIO BAR to prevent the reference code from + * resetting the controller. + * + * The BAR will be re-assigned during device enumeration so these are only + * temporary. + * + * This is used to speed up the resume path. + */ +static void enable_usb_bar(void) +{ + pci_dev_t usb0 = PCH_EHCI1_DEV; + pci_dev_t usb1 = PCH_EHCI2_DEV; + pci_dev_t usb3 = PCH_XHCI_DEV; + u32 cmd; + + /* USB Controller 1 */ + pci_write_config32(usb0, PCI_BASE_ADDRESS_0, + PCH_EHCI0_TEMP_BAR0); + cmd = pci_read_config32(usb0, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb0, PCI_COMMAND, cmd); + + /* USB Controller 1 */ + pci_write_config32(usb1, PCI_BASE_ADDRESS_0, + PCH_EHCI1_TEMP_BAR0); + cmd = pci_read_config32(usb1, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb1, PCI_COMMAND, cmd); + + /* USB3 Controller */ + pci_write_config32(usb3, PCI_BASE_ADDRESS_0, + PCH_XHCI_TEMP_BAR0); + cmd = pci_read_config32(usb3, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb3, PCI_COMMAND, cmd); +} + +static int report_bist_failure(void) +{ + if (gd->arch.bist != 0) { + post_code(POST_BIST_FAILURE); + printf("BIST failed: %08x\n", gd->arch.bist); + return -EFAULT; + } + + return 0; +} + +int print_cpuinfo(void) +{ + enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; + char processor_name[CPU_MAX_NAME_LEN]; + const char *name; + uint32_t pm1_cnt; + uint16_t pm1_sts; + int ret; + + /* Halt if there was a built in self test failure */ + ret = report_bist_failure(); + if (ret) + return ret; + + enable_lapic(); + + ret = microcode_update_intel(); + if (ret) + return ret; + + /* Enable upper 128bytes of CMOS */ + writel(1 << 2, RCB_REG(RC)); + + /* TODO: cmos_post_init() */ + if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { + debug("soft reset detected\n"); + boot_mode = PEI_BOOT_SOFT_RESET; + + /* System is not happy after keyboard reset... */ + debug("Issuing CF9 warm reset\n"); + outb(0x6, 0xcf9); + cpu_hlt(); + } + + /* Early chipset init required before RAM init can work */ + sandybridge_early_init(SANDYBRIDGE_MOBILE); + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + debug("Resume from S3 detected.\n"); + boot_mode = PEI_BOOT_RESUME; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); +#else + debug("Resume from S3 detected, but disabled.\n"); +#endif + } else { + /* + * TODO: An indication of life might be possible here (e.g. + * keyboard light) + */ + } + post_code(POST_EARLY_INIT); + + /* Enable SPD ROMs and DDR-III DRAM */ + ret = enable_smbus(); + if (ret) + return ret; + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == PEI_BOOT_RESUME) + enable_usb_bar(); + + gd->arch.pei_boot_mode = boot_mode; + + /* TODO: Move this to the board or driver */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + /* Print processor name */ + name = cpu_get_name(processor_name); + printf("CPU: %s\n", name); + + post_code(POST_CPU_INFO); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c new file mode 100644 index 0000000000..eb8f6139fe --- /dev/null +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -0,0 +1,145 @@ +/* + * From Coreboot + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev) +{ + /* Setting up Southbridge. In the northbridge code. */ + debug("Setting up static southbridge registers\n"); + pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + + pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ + + debug("Disabling watchdog reboot\n"); + setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ + outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + + /* Set up all hardcoded northbridge BARs */ + debug("Setting up static registers\n"); + pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + /* 64MB - busses 0-63 */ + pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + pci_write_config32(pch_dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(pch_dev, PAM0, 0x30); + pci_write_config8(pch_dev, PAM1, 0x33); + pci_write_config8(pch_dev, PAM2, 0x33); + pci_write_config8(pch_dev, PAM3, 0x33); + pci_write_config8(pch_dev, PAM4, 0x33); + pci_write_config8(pch_dev, PAM5, 0x33); + pci_write_config8(pch_dev, PAM6, 0x33); +} + +static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) +{ + u32 reg32; + u16 reg16; + u8 reg8; + + reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID); + switch (reg16) { + case 0x0102: /* GT1 Desktop */ + case 0x0106: /* GT1 Mobile */ + case 0x010a: /* GT1 Server */ + case 0x0112: /* GT2 Desktop */ + case 0x0116: /* GT2 Mobile */ + case 0x0122: /* GT2 Desktop >=1.3GHz */ + case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0156: /* IvyBridge */ + case 0x0166: /* IvyBridge */ + break; + default: + debug("Graphics not supported by this CPU/chipset\n"); + return; + } + + debug("Initialising Graphics\n"); + + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + reg16 = pci_read_config16(pch_dev, GGC); + reg16 &= ~0x00f8; + reg16 |= 1 << 3; + /* Program GTT memory by setting GGC[9:8] = 2MB */ + reg16 &= ~0x0300; + reg16 |= 2 << 8; + /* Enable VGA decode */ + reg16 &= ~0x0002; + pci_write_config16(pch_dev, GGC, reg16); + + /* Enable 256MB aperture */ + reg8 = pci_read_config8(video_dev, MSAC); + reg8 &= ~0x06; + reg8 |= 0x02; + pci_write_config8(video_dev, MSAC, reg8); + + /* Erratum workarounds */ + reg32 = readl(MCHBAR_REG(0x5f00)); + reg32 |= (1 << 9) | (1 << 10); + writel(reg32, MCHBAR_REG(0x5f00)); + + /* Enable SA Clock Gating */ + reg32 = readl(MCHBAR_REG(0x5f00)); + writel(reg32 | 1, MCHBAR_REG(0x5f00)); + + /* GPU RC6 workaround for sighting 366252 */ + reg32 = readl(MCHBAR_REG(0x5d14)); + reg32 |= (1 << 31); + writel(reg32, MCHBAR_REG(0x5d14)); + + /* VLW */ + reg32 = readl(MCHBAR_REG(0x6120)); + reg32 &= ~(1 << 0); + writel(reg32, MCHBAR_REG(0x6120)); + + reg32 = readl(MCHBAR_REG(0x5418)); + reg32 |= (1 << 4) | (1 << 5); + writel(reg32, MCHBAR_REG(0x5418)); +} + +void sandybridge_early_init(int chipset_type) +{ + pci_dev_t pch_dev = PCH_DEV; + pci_dev_t video_dev = PCH_VIDEO_DEV; + pci_dev_t lpc_dev = PCH_LPC_DEV; + u32 capid0_a; + u8 reg8; + + /* Device ID Override Enable should be done very early */ + capid0_a = pci_read_config32(pch_dev, 0xe4); + if (capid0_a & (1 << 10)) { + reg8 = pci_read_config8(pch_dev, 0xf3); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + pci_write_config8(pch_dev, 0xf3, reg8); + } + + /* Setup all BARs required for early PCIe and raminit */ + sandybridge_setup_bars(pch_dev, lpc_dev); + + /* Device Enable */ + pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + + sandybridge_setup_graphics(pch_dev, video_dev); +} diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c new file mode 100644 index 0000000000..b24dea10b1 --- /dev/null +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -0,0 +1,191 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/early_me.c + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +static const char *const me_ack_values[] = { + [ME_HFS_ACK_NO_DID] = "No DID Ack received", + [ME_HFS_ACK_RESET] = "Non-power cycle reset", + [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset", + [ME_HFS_ACK_S3] = "Go to S3", + [ME_HFS_ACK_S4] = "Go to S4", + [ME_HFS_ACK_S5] = "Go to S5", + [ME_HFS_ACK_GBL_RESET] = "Global Reset", + [ME_HFS_ACK_CONTINUE] = "Continue to boot" +}; + +static inline void pci_read_dword_ptr(void *ptr, int offset) +{ + u32 dword; + + dword = pci_read_config32(PCH_ME_DEV, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void pci_write_dword_ptr(void *ptr, int offset) +{ + u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); + pci_write_config32(PCH_ME_DEV, offset, dword); +} + +void intel_early_me_status(void) +{ + struct me_hfs hfs; + struct me_gmes gmes; + + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + pci_read_dword_ptr(&gmes, PCI_ME_GMES); + + intel_me_status(&hfs, &gmes); +} + +int intel_early_me_init(void) +{ + int count; + struct me_uma uma; + struct me_hfs hfs; + + debug("Intel ME early init\n"); + + /* Wait for ME UMA SIZE VALID bit to be set */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(&uma, PCI_ME_UMA); + if (uma.valid) + break; + udelay(ME_DELAY); + } + if (!count) { + printf("ERROR: ME is not ready!\n"); + return -EBUSY; + } + + /* Check for valid firmware */ + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.fpt_bad) { + printf("WARNING: ME has bad firmware\n"); + return -EBADF; + } + + debug("Intel ME firmware is ready\n"); + + return 0; +} + +int intel_early_me_uma_size(void) +{ + struct me_uma uma; + + pci_read_dword_ptr(&uma, PCI_ME_UMA); + if (uma.valid) { + debug("ME: Requested %uMB UMA\n", uma.size); + return uma.size; + } + + debug("ME: Invalid UMA size\n"); + return -EINVAL; +} + +static inline void set_global_reset(int enable) +{ + u32 etr3; + + etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + + /* Clear CF9 Without Resume Well Reset Enable */ + etr3 &= ~ETR3_CWORWRE; + + /* CF9GR indicates a Global Reset */ + if (enable) + etr3 |= ETR3_CF9GR; + else + etr3 &= ~ETR3_CF9GR; + + pci_write_config32(PCH_LPC_DEV, ETR3, etr3); +} + +int intel_early_me_init_done(u8 status) +{ + u8 reset; + int count; + u32 mebase_l, mebase_h; + struct me_hfs hfs; + struct me_did did = { + .init_done = ME_INIT_DONE, + .status = status + }; + + /* MEBASE from MESEG_BASE[35:20] */ + mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L); + mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H); + mebase_h &= 0xf; + did.uma_base = (mebase_l >> 20) | (mebase_h << 12); + + /* Send message to ME */ + debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n", + status, did.uma_base); + + pci_write_dword_ptr(&did, PCI_ME_H_GS); + + /* Must wait for ME acknowledgement */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.bios_msg_ack) + break; + udelay(ME_DELAY); + } + if (!count) { + printf("ERROR: ME failed to respond\n"); + return -1; + } + + /* Return the requested BIOS action */ + debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]); + + /* Check status after acknowledgement */ + intel_early_me_status(); + + reset = 0; + switch (hfs.ack_data) { + case ME_HFS_ACK_CONTINUE: + /* Continue to boot */ + return 0; + case ME_HFS_ACK_RESET: + /* Non-power cycle reset */ + set_global_reset(0); + reset = 0x06; + break; + case ME_HFS_ACK_PWR_CYCLE: + /* Power cycle reset */ + set_global_reset(0); + reset = 0x0e; + break; + case ME_HFS_ACK_GBL_RESET: + /* Global reset */ + set_global_reset(1); + reset = 0x0e; + break; + case ME_HFS_ACK_S3: + case ME_HFS_ACK_S4: + case ME_HFS_ACK_S5: + break; + } + + /* Perform the requested reset */ + if (reset) { + outb(reset, 0xcf9); + cpu_hlt(); + } + return -1; +} diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c new file mode 100644 index 0000000000..6cf9654e02 --- /dev/null +++ b/arch/x86/cpu/ivybridge/gma.c @@ -0,0 +1,770 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2011 Chromium OS Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct gt_powermeter { + u16 reg; + u32 value; +}; + +static const struct gt_powermeter snb_pm_gt1[] = { + { 0xa200, 0xcc000000 }, + { 0xa204, 0x07000040 }, + { 0xa208, 0x0000fe00 }, + { 0xa20c, 0x00000000 }, + { 0xa210, 0x17000000 }, + { 0xa214, 0x00000021 }, + { 0xa218, 0x0817fe19 }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0xcc000000 }, + { 0xa228, 0x07000040 }, + { 0xa22c, 0x0000fe00 }, + { 0xa230, 0x00000000 }, + { 0xa234, 0x17000000 }, + { 0xa238, 0x00000021 }, + { 0xa23c, 0x0817fe19 }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +static const struct gt_powermeter snb_pm_gt2[] = { + { 0xa200, 0x330000a6 }, + { 0xa204, 0x402d0031 }, + { 0xa208, 0x00165f83 }, + { 0xa20c, 0xf1000000 }, + { 0xa210, 0x00000000 }, + { 0xa214, 0x00160016 }, + { 0xa218, 0x002a002b }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0x330000a6 }, + { 0xa228, 0x402d0031 }, + { 0xa22c, 0x00165f83 }, + { 0xa230, 0xf1000000 }, + { 0xa234, 0x00000000 }, + { 0xa238, 0x00160016 }, + { 0xa23c, 0x002a002b }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt1[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00021c00 }, + { 0xa808, 0x00000403 }, + { 0xa80c, 0x02001700 }, + { 0xa810, 0x05000200 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00690500 }, + { 0xa81c, 0x0000007f }, + { 0xa820, 0x01002501 }, + { 0xa824, 0x00000300 }, + { 0xa828, 0x01000331 }, + { 0xa82c, 0x0000000c }, + { 0xa830, 0x00010016 }, + { 0xa834, 0x01100101 }, + { 0xa838, 0x00010103 }, + { 0xa83c, 0x00041300 }, + { 0xa840, 0x00000b30 }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x7f000000 }, + { 0xa84c, 0x05000008 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000004 }, + { 0xa858, 0x00000007 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00010000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00001c00 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x06000000 }, + { 0xa910, 0x09000200 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00590000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x04002501 }, + { 0xa924, 0x00000100 }, + { 0xa928, 0x03000410 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00020000 }, + { 0xa934, 0x02070106 }, + { 0xa938, 0x00010100 }, + { 0xa93c, 0x00401c00 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x10000e00 }, + { 0xa94c, 0x02000004 }, + { 0xa950, 0x00000001 }, + { 0xa954, 0x00000004 }, + { 0xa960, 0x00060000 }, + { 0xaa3c, 0x00001c00 }, + { 0xaa54, 0x00000004 }, + { 0xaa60, 0x00060000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2[] = { + { 0xa800, 0x10000000 }, + { 0xa804, 0x00033800 }, + { 0xa808, 0x00000902 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x12000400 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20800 }, + { 0xa81c, 0x00000002 }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00010032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x0000151d }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x20001b00 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000000 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003500 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000500 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000200 }, + { 0xa928, 0x07000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x050f020d }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2_17w[] = { + { 0xa800, 0x20000000 }, + { 0xa804, 0x000e3800 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000800 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000002 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x0000000f }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2_35w[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00030400 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000300 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +/* + * Some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + */ + +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x80860102: /* GT1 Desktop */ + case 0x8086010a: /* GT1 Server */ + case 0x80860112: /* GT2 Desktop */ + case 0x80860116: /* GT2 Mobile */ + case 0x80860122: /* GT2 Desktop >=1.3GHz */ + case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860156: /* IVB */ + case 0x80860166: /* IVB */ + /* Set to GT1 Mobile */ + new_vendev = 0x80860106; + break; + } + + return new_vendev; +} + +static inline u32 gtt_read(void *bar, u32 reg) +{ + return readl(bar + reg); +} + +static inline void gtt_write(void *bar, u32 reg, u32 data) +{ + writel(data, bar + reg); +} + +static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm) +{ + for (; pm && pm->reg; pm++) + gtt_write(bar, pm->reg, pm->value); +} + +#define GTT_RETRY 1000 +static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value) +{ + unsigned try = GTT_RETRY; + u32 data; + + while (try--) { + data = gtt_read(bar, reg); + if ((data & mask) == value) + return 1; + udelay(10); + } + + printf("GT init timeout\n"); + return 0; +} + +static int gma_pm_init_pre_vbios(void *gtt_bar) +{ + u32 reg32; + + debug("GT Power Management Init, silicon = %#x\n", + bridge_silicon_revision()); + + if (bridge_silicon_revision() < IVB_STEP_C0) { + /* 1: Enable force wake */ + gtt_write(gtt_bar, 0xa18c, 0x00000001); + gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0)); + } else { + gtt_write(gtt_bar, 0xa180, 1 << 5); + gtt_write(gtt_bar, 0xa188, 0xffff0001); + gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0)); + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ + reg32 = gtt_read(gtt_bar, 0x42004); + reg32 |= (1 << 14) | (1 << 15); + gtt_write(gtt_bar, 0x42004, reg32); + } + + if (bridge_silicon_revision() >= IVB_STEP_A0) { + /* Display Reset Acknowledge Settings */ + reg32 = gtt_read(gtt_bar, 0x45010); + reg32 |= (1 << 1) | (1 << 0); + gtt_write(gtt_bar, 0x45010, reg32); + } + + /* 2: Get GT SKU from GTT+0x911c[13] */ + reg32 = gtt_read(gtt_bar, 0x911c); + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if (reg32 & (1 << 13)) { + debug("SNB GT1 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, snb_pm_gt1); + } else { + debug("SNB GT2 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, snb_pm_gt2); + } + } else { + u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf; + + if (reg32 & (1 << 13)) { + /* GT1 SKU */ + debug("IVB GT1 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt1); + } else { + /* GT2 SKU */ + u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff; + tdp /= (1 << unit); + + if (tdp <= 17) { + /* <=17W ULV */ + debug("IVB GT2 17W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w); + } else if ((tdp >= 25) && (tdp <= 35)) { + /* 25W-35W */ + debug("IVB GT2 25W-35W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); + } else { + /* All others */ + debug("IVB GT2 35W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); + } + } + } + + /* 3: Gear ratio map */ + gtt_write(gtt_bar, 0xa004, 0x00000010); + + /* 4: GFXPAUSE */ + gtt_write(gtt_bar, 0xa000, 0x00070020); + + /* 5: Dynamic EU trip control */ + gtt_write(gtt_bar, 0xa080, 0x00000004); + + /* 6: ECO bits */ + reg32 = gtt_read(gtt_bar, 0xa180); + reg32 |= (1 << 26) | (1 << 31); + /* (bit 20=1 for SNB step D1+ / IVB A0+) */ + if (bridge_silicon_revision() >= SNB_STEP_D1) + reg32 |= (1 << 20); + gtt_write(gtt_bar, 0xa180, reg32); + + /* 6a: for SnB step D2+ only */ + if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && + (bridge_silicon_revision() >= SNB_STEP_D2)) { + reg32 = gtt_read(gtt_bar, 0x9400); + reg32 |= (1 << 7); + gtt_write(gtt_bar, 0x9400, reg32); + + reg32 = gtt_read(gtt_bar, 0x941c); + reg32 &= 0xf; + reg32 |= (1 << 1); + gtt_write(gtt_bar, 0x941c, reg32); + gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1)); + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + reg32 = gtt_read(gtt_bar, 0x907c); + reg32 |= (1 << 16); + gtt_write(gtt_bar, 0x907c, reg32); + + /* 6b: Clocking reset controls */ + gtt_write(gtt_bar, 0x9424, 0x00000001); + } else { + /* 6b: Clocking reset controls */ + gtt_write(gtt_bar, 0x9424, 0x00000000); + } + + /* 7 */ + if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) { + gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */ + /* Mailbox Cmd for RC6 VID */ + gtt_write(gtt_bar, 0x138124, 0x80000004); + if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) + gtt_write(gtt_bar, 0x138124, 0x8000000a); + gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)); + } + + /* 8 */ + gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */ + gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ + gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ + gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ + gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */ + gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */ + + /* 9 */ + gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */ + gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */ + gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */ + + /* 10 */ + gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */ + gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */ + gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */ + gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */ + gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */ + + /* 11 */ + gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */ + gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */ + gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */ + gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */ + gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */ + gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */ + gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */ + + /* 11a: Enable Render Standby (RC6) */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* + * IvyBridge should also support DeepRenderStandby. + * + * Unfortunately it does not work reliably on all SKUs so + * disable it here and it can be enabled by the kernel. + */ + gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ + } else { + gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ + } + + /* 12: Normal Frequency Request */ + /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ + reg32 = readl(MCHBAR_REG(0x5998)); + reg32 >>= 16; + reg32 &= 0xef; + reg32 <<= 25; + gtt_write(gtt_bar, 0xa008, reg32); + + /* 13: RP Control */ + gtt_write(gtt_bar, 0xa024, 0x00000592); + + /* 14: Enable PM Interrupts */ + gtt_write(gtt_bar, 0x4402c, 0x03000076); + + /* Clear 0x6c024 [8:6] */ + reg32 = gtt_read(gtt_bar, 0x6c024); + reg32 &= ~0x000001c0; + gtt_write(gtt_bar, 0x6c024, reg32); + + return 0; +} + +int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node) +{ + u32 reg32, cycle_delay; + + debug("GT Power Management Init (post VBIOS)\n"); + + /* 15: Deassert Force Wake */ + if (bridge_silicon_revision() < IVB_STEP_C0) { + gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1); + gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0)); + } else { + gtt_write(gtt_bar, 0xa188, 0x1fffe); + if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) { + gtt_write(gtt_bar, 0xa188, + gtt_read(gtt_bar, 0xa188) | 1); + } + } + + /* 16: SW RC Control */ + gtt_write(gtt_bar, 0xa094, 0x00060000); + + /* Setup Digital Port Hotplug */ + reg32 = gtt_read(gtt_bar, 0xc4030); + if (!reg32) { + u32 dp_hotplug[3]; + + if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug", + dp_hotplug, ARRAY_SIZE(dp_hotplug))) + return -EINVAL; + + reg32 = (dp_hotplug[0] & 0x7) << 2; + reg32 |= (dp_hotplug[0] & 0x7) << 10; + reg32 |= (dp_hotplug[0] & 0x7) << 18; + gtt_write(gtt_bar, 0xc4030, reg32); + } + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(gtt_bar, 0xc7208); + if (!reg32) { + reg32 = (unsigned)fdtdec_get_int(blob, node, + "panel-port-select", 0) << 30; + reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0) + << 16; + reg32 |= fdtdec_get_int(blob, node, + "panel-power-backlight-on-delay", 0); + gtt_write(gtt_bar, 0xc7208, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(gtt_bar, 0xc720c); + if (!reg32) { + reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0) + << 16; + reg32 |= fdtdec_get_int(blob, node, + "panel-power-backlight-off-delay", 0); + gtt_write(gtt_bar, 0xc720c, reg32); + } + + /* Setup Panel Power Cycle Delay */ + cycle_delay = fdtdec_get_int(blob, node, + "intel,panel-power-cycle-delay", 0); + if (cycle_delay) { + reg32 = gtt_read(gtt_bar, 0xc7210); + reg32 &= ~0xff; + reg32 |= cycle_delay; + gtt_write(gtt_bar, 0xc7210, reg32); + } + + /* Enable Backlight if needed */ + reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0); + if (reg32) { + gtt_write(gtt_bar, 0x48250, (1 << 31)); + gtt_write(gtt_bar, 0x48254, reg32); + } + reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0); + if (reg32) { + gtt_write(gtt_bar, 0xc8250, (1 << 31)); + gtt_write(gtt_bar, 0xc8254, reg32); + } + + return 0; +} + +/* + * Some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + */ + +uint32_t board_map_oprom_vendev(uint32_t vendev) +{ + switch (vendev) { + case 0x80860102: /* GT1 Desktop */ + case 0x8086010a: /* GT1 Server */ + case 0x80860112: /* GT2 Desktop */ + case 0x80860116: /* GT2 Mobile */ + case 0x80860122: /* GT2 Desktop >=1.3GHz */ + case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860156: /* IVB */ + case 0x80860166: /* IVB */ + return 0x80860106; /* GT1 Mobile */ + } + + return vendev; +} + +static int int15_handler(void) +{ + int res = 0; + + debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX); + + switch (M.x86.R_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + M.x86.R_AX = 0x005f; + M.x86.R_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0003; /* eDP */ + res = 1; + break; + case 0x5f70: + switch (M.x86.R_CH) { + case 0: + /* Get Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + debug("Unknown INT15 5f70 function: 0x%02x\n", + M.x86.R_CH); + break; + } + break; + case 0x5fac: + res = 1; + break; + default: + debug("Unknown INT15 function %04x!\n", M.x86.R_AX); + break; + } + return res; +} + +int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, + const void *blob, int node) +{ +#ifdef CONFIG_VIDEO + ulong start; +#endif + void *gtt_bar; + ulong base; + u32 reg32; + int ret; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Use write-combining for the graphics memory, 256MB */ + base = pci_read_bar32(hose, dev, 2); + mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20); + mtrr_commit(true); + + gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0); + debug("GT bar %p\n", gtt_bar); + ret = gma_pm_init_pre_vbios(gtt_bar); + if (ret) + return ret; + +#ifdef CONFIG_VIDEO + start = get_timer(0); + ret = pci_run_vga_bios(dev, int15_handler, false); + debug("BIOS ran in %lums\n", get_timer(start)); +#endif + /* Post VBIOS init */ + ret = gma_pm_init_post_vbios(gtt_bar, blob, node); + if (ret) + return ret; + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/gma.h b/arch/x86/cpu/ivybridge/gma.h new file mode 100644 index 0000000000..e7ec649b80 --- /dev/null +++ b/arch/x86/cpu/ivybridge/gma.h @@ -0,0 +1,156 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2012 Chromium OS Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/* mailbox 0: header */ +__packed struct opregion_header { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +}; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +__packed struct opregion_mailbox1 { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +}; + +/* mailbox 2: software sci interface */ +__packed struct opregion_mailbox2 { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +}; + +/* mailbox 3: power conservation */ +__packed struct opregion_mailbox3 { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +}; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +__packed struct { + u8 gvd1[7168]; +} opregion_vbt_t; + +/* IGD OpRegion */ +__packed struct igd_opregion { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +}; + +/* Intel Video BIOS (Option ROM) */ +__packed struct optionrom_header { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +}; + +#define OPROM_SIGNATURE 0xaa55 + +__packed struct optionrom_pcir { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +}; + +__packed struct optionrom_vbt { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +}; + +#define VBT_SIGNATURE 0x54425624 diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c new file mode 100644 index 0000000000..43fdd31428 --- /dev/null +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -0,0 +1,569 @@ +/* + * From coreboot southbridge/intel/bd82x6x/lpc.c + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NMI_OFF 0 + +#define ENABLE_ACPI_MODE_IN_COREBOOT 0 +#define TEST_SMM_FLASH_LOCKDOWN 0 + +static int pch_enable_apic(pci_dev_t dev) +{ + u32 reg32; + int i; + + /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */ + pci_write_config8(dev, ACPI_CNTL, 0x80); + + writel(0, IO_APIC_INDEX); + writel(1 << 25, IO_APIC_DATA); + + /* affirm full set of redirection table entries ("write once") */ + writel(1, IO_APIC_INDEX); + reg32 = readl(IO_APIC_DATA); + writel(1, IO_APIC_INDEX); + writel(reg32, IO_APIC_DATA); + + writel(0, IO_APIC_INDEX); + reg32 = readl(IO_APIC_DATA); + debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) { + printf("APIC Error - cannot write to registers\n"); + return -EPERM; + } + + debug("Dumping IOAPIC registers\n"); + for (i = 0; i < 3; i++) { + writel(i, IO_APIC_INDEX); + debug(" reg 0x%04x:", i); + reg32 = readl(IO_APIC_DATA); + debug(" 0x%08x\n", reg32); + } + + /* Select Boot Configuration register. */ + writel(3, IO_APIC_INDEX); + + /* Use Processor System Bus to deliver interrupts. */ + writel(1, IO_APIC_DATA); + + return 0; +} + +static void pch_enable_serial_irqs(pci_dev_t dev) +{ + u32 value; + + /* Set packet length and toggle silent mode bit for one frame. */ + value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); +#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE + pci_write_config8(dev, SERIRQ_CNTL, value); +#else + pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6)); +#endif +} + +static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) +{ + uint8_t route[8], *ptr; + + if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route, + sizeof(route))) + return -EINVAL; + ptr = route; + pci_write_config8(dev, PIRQA_ROUT, *ptr++); + pci_write_config8(dev, PIRQB_ROUT, *ptr++); + pci_write_config8(dev, PIRQC_ROUT, *ptr++); + pci_write_config8(dev, PIRQD_ROUT, *ptr++); + + pci_write_config8(dev, PIRQE_ROUT, *ptr++); + pci_write_config8(dev, PIRQF_ROUT, *ptr++); + pci_write_config8(dev, PIRQG_ROUT, *ptr++); + pci_write_config8(dev, PIRQH_ROUT, *ptr++); + + /* + * TODO(sjg@chromium.org): U-Boot does not set up the interrupts + * here. It's unclear if it is needed + */ + return 0; +} + +static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev) +{ + u8 route[16]; + u32 reg; + int gpi; + + if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route, + sizeof(route))) + return -EINVAL; + + for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) + reg |= route[gpi] << (gpi * 2); + + pci_write_config32(dev, 0xb8, reg); + + return 0; +} + +static int pch_power_options(const void *blob, int node, pci_dev_t dev) +{ + u8 reg8; + u16 reg16, pmbase; + u32 reg32; + const char *state; + int pwr_on; + int nmi_option; + int ret; + + /* + * Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use Kconfig setting. + * TODO(sjg@chromium.org): Make this configurable + */ + pwr_on = MAINBOARD_POWER_ON; + + reg16 = pci_read_config16(dev, GEN_PMCON_3); + reg16 &= 0xfffe; + switch (pwr_on) { + case MAINBOARD_POWER_OFF: + reg16 |= 1; + state = "off"; + break; + case MAINBOARD_POWER_ON: + reg16 &= ~1; + state = "on"; + break; + case MAINBOARD_POWER_KEEP: + reg16 &= ~1; + state = "state keep"; + break; + default: + state = "undefined"; + } + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + + pci_write_config16(dev, GEN_PMCON_3, reg16); + debug("Set power %s after power failure.\n", state); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x70); + /* TODO(sjg@chromium.org): Make this configurable */ + nmi_option = NMI_OFF; + if (nmi_option) { + debug("NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + debug("NMI sources disabled.\n"); + /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); + } + outb(reg8, 0x70); + + /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ + reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ + reg16 |= (3 << 0); /* Periodic SMI every 8s */ +#endif + pci_write_config16(dev, GEN_PMCON_1, reg16); + + /* Set the board's GPI routing. */ + ret = pch_gpi_routing(blob, node, dev); + if (ret) + return ret; + + pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + + writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, + "intel,gpe0-enable", 0)); + writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node, + "intel,alt-gp-smi-enable", 0)); + + /* Set up power management block and determine sleep mode */ + reg32 = inl(pmbase + 0x04); /* PM1_CNT */ + reg32 &= ~(7 << 10); /* SLP_TYP */ + reg32 |= (1 << 0); /* SCI_EN */ + outl(reg32, pmbase + 0x04); + + /* Clear magic status bits to prevent unexpected wake */ + setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); + clrbits_le32(RCB_REG(0x3f02), 0xf); + + return 0; +} + +static void pch_rtc_init(pci_dev_t dev) +{ + int rtc_failed; + u8 reg8; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + debug("rtc_failed = 0x%x\n", rtc_failed); + +#if CONFIG_HAVE_ACPI_RESUME + /* Avoid clearing pending interrupts and resetting the RTC control + * register in the resume path because the Linux kernel relies on + * this to know if it should restart the RTC timerqueue if the wake + * was due to the RTC alarm. + */ + if (acpi_get_slp_type() == 3) + return; +#endif + /* TODO: Handle power failure */ + if (rtc_failed) + printf("RTC power failed\n"); + rtc_init(); +} + +/* CougarPoint PCH Power Management init */ +static void cpt_pm_init(pci_dev_t dev) +{ + debug("CougarPoint PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); + + setbits_le32(RCB_REG(0x228c), 1 << 0); + setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); + setbits_le32(RCB_REG(0x0900), 1 << 14); + writel(0xc0388400, RCB_REG(0x2304)); + setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); + setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); + clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); + writel(0x050f0000, RCB_REG(0x3318)); + writel(0x04000000, RCB_REG(0x3324)); + setbits_le32(RCB_REG(0x3340), 0xfffff); + setbits_le32(RCB_REG(0x3344), 1 << 1); + + writel(0x0001c000, RCB_REG(0x3360)); + writel(0x00061100, RCB_REG(0x3368)); + writel(0x7f8fdfff, RCB_REG(0x3378)); + writel(0x000003fc, RCB_REG(0x337c)); + writel(0x00001000, RCB_REG(0x3388)); + writel(0x0001c000, RCB_REG(0x3390)); + writel(0x00000800, RCB_REG(0x33a0)); + writel(0x00001000, RCB_REG(0x33b0)); + writel(0x00093900, RCB_REG(0x33c0)); + writel(0x24653002, RCB_REG(0x33cc)); + writel(0x062108fe, RCB_REG(0x33d0)); + clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); + writel(0x01010000, RCB_REG(0x3a28)); + writel(0x01010404, RCB_REG(0x3a2c)); + writel(0x01041041, RCB_REG(0x3a80)); + clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); + setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */ + setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */ + writel(0x00000001, RCB_REG(0x3a6c)); + clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c); + clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); + writel(0, RCB_REG(0x33c8)); + setbits_le32(RCB_REG(0x21b0), 0xf); +} + +/* PantherPoint PCH Power Management init */ +static void ppt_pm_init(pci_dev_t dev) +{ + debug("PantherPoint PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + setbits_le32(RCB_REG(0x2238), 1 << 0); + setbits_le32(RCB_REG(0x228c), 1 << 0); + setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); + setbits_le16(RCB_REG(0x0900), 1 << 14); + writel(0xc03b8400, RCB_REG(0x2304)); + setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); + setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); + clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); + writel(0x054f0000, RCB_REG(0x3318)); + writel(0x04000000, RCB_REG(0x3324)); + setbits_le32(RCB_REG(0x3340), 0xfffff); + setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0)); + writel(0x0001c000, RCB_REG(0x3360)); + writel(0x00061100, RCB_REG(0x3368)); + writel(0x7f8fdfff, RCB_REG(0x3378)); + writel(0x000003fd, RCB_REG(0x337c)); + writel(0x00001000, RCB_REG(0x3388)); + writel(0x0001c000, RCB_REG(0x3390)); + writel(0x00000800, RCB_REG(0x33a0)); + writel(0x00001000, RCB_REG(0x33b0)); + writel(0x00093900, RCB_REG(0x33c0)); + writel(0x24653002, RCB_REG(0x33cc)); + writel(0x067388fe, RCB_REG(0x33d0)); + clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); + writel(0x01010000, RCB_REG(0x3a28)); + writel(0x01010404, RCB_REG(0x3a2c)); + writel(0x01040000, RCB_REG(0x3a80)); + clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); + /* SATA 2/3 disabled */ + setbits_le32(RCB_REG(0x3a84), 1 << 24); + /* SATA 4/5 disabled */ + setbits_le32(RCB_REG(0x3a88), 1 << 0); + writel(0x00000001, RCB_REG(0x3a6c)); + clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); + clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); + setbits_le32(RCB_REG(0x33a4), (1 << 0)); + writel(0, RCB_REG(0x33c8)); + setbits_le32(RCB_REG(0x21b0), 0xf); +} + +static void enable_hpet(void) +{ + /* Move HPET to default address 0xfed00000 and enable it */ + clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); +} + +static void enable_clock_gating(pci_dev_t dev) +{ + u32 reg32; + u16 reg16; + + setbits_le32(RCB_REG(0x2234), 0xf); + + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 |= (1 << 2) | (1 << 11); + pci_write_config16(dev, GEN_PMCON_1, reg16); + + pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); + pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); + pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + + reg32 = readl(RCB_REG(CG)); + reg32 |= (1 << 31); + reg32 |= (1 << 29) | (1 << 28); + reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); + reg32 |= (1 << 16); + reg32 |= (1 << 17); + reg32 |= (1 << 18); + reg32 |= (1 << 22); + reg32 |= (1 << 23); + reg32 &= ~(1 << 20); + reg32 |= (1 << 19); + reg32 |= (1 << 0); + reg32 |= (0xf << 1); + writel(reg32, RCB_REG(CG)); + + setbits_le32(RCB_REG(0x38c0), 0x7); + setbits_le32(RCB_REG(0x36d4), 0x6680c004); + setbits_le32(RCB_REG(0x3564), 0x3); +} + +#if CONFIG_HAVE_SMI_HANDLER +static void pch_lock_smm(pci_dev_t dev) +{ +#if TEST_SMM_FLASH_LOCKDOWN + u8 reg8; +#endif + + if (acpi_slp_type != 3) { +#if ENABLE_ACPI_MODE_IN_COREBOOT + debug("Enabling ACPI via APMC:\n"); + outb(0xe1, 0xb2); /* Enable ACPI mode */ + debug("done.\n"); +#else + debug("Disabling ACPI via APMC:\n"); + outb(0x1e, 0xb2); /* Disable ACPI mode */ + debug("done.\n"); +#endif + } + + /* Don't allow evil boot loaders, kernels, or + * userspace applications to deceive us: + */ + smm_lock(); + +#if TEST_SMM_FLASH_LOCKDOWN + /* Now try this: */ + debug("Locking BIOS to RO... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + reg8 &= ~(1 << 0); /* clear BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + reg8 |= (1 << 1); /* set BLE */ + pci_write_config8(dev, 0xdc, reg8); + debug("ok.\n"); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + + debug("Writing:\n"); + writeb(0, 0xfff00000); + debug("Testing:\n"); + reg8 |= (1 << 0); /* set BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + debug("Done.\n"); +#endif +} +#endif + +static void pch_disable_smm_only_flashing(pci_dev_t dev) +{ + u8 reg8; + + debug("Enabling BIOS updates outside of SMM... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 &= ~(1 << 5); + pci_write_config8(dev, 0xdc, reg8); +} + +static void pch_fixups(pci_dev_t dev) +{ + u8 gen_pmcon_2; + + /* Indicate DRAM init done for MRC S3 to know it can resume */ + gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); + gen_pmcon_2 |= (1 << 7); + pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + + /* Enable DMI ASPM in the PCH */ + clrbits_le32(RCB_REG(0x2304), 1 << 10); + setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10)); + setbits_le32(RCB_REG(0x21a8), 0x3); +} + +int lpc_early_init(const void *blob, int node, pci_dev_t dev) +{ + struct reg_info { + u32 base; + u32 size; + } values[4], *ptr; + int count; + int i; + + count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec", + (u32 *)values, sizeof(values) / sizeof(u32)); + if (count < 0) + return -EINVAL; + + /* Set COM1/COM2 decode range */ + pci_write_config16(dev, LPC_IO_DEC, 0x0010); + + /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ + pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + GAMEL_LPC_EN | COMA_LPC_EN); + + /* Write all registers but use 0 if we run out of data */ + count = count * sizeof(u32) / sizeof(values[0]); + for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) { + u32 reg = 0; + + if (i < count) + reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); + pci_write_config32(dev, LPC_GENX_DEC(i), reg); + } + + return 0; +} + +int lpc_init(struct pci_controller *hose, pci_dev_t dev) +{ + const void *blob = gd->fdt_blob; + int node; + + debug("pch: lpc_init\n"); + pci_write_bar32(hose, dev, 0, 0); + pci_write_bar32(hose, dev, 1, 0xff800000); + pci_write_bar32(hose, dev, 2, 0xfec00000); + pci_write_bar32(hose, dev, 3, 0x800); + pci_write_bar32(hose, dev, 4, 0x900); + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + if (node < 0) + return -ENOENT; + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + pch_enable_apic(dev); + + pch_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + pch_pirq_init(blob, node, dev); + + /* Setup power options. */ + pch_power_options(blob, node, dev); + + /* Initialize power management */ + switch (pch_silicon_type()) { + case PCH_TYPE_CPT: /* CougarPoint */ + cpt_pm_init(dev); + break; + case PCH_TYPE_PPT: /* PantherPoint */ + ppt_pm_init(dev); + break; + default: + printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev), + PCI_FUNC(dev)); + return -ENOSYS; + } + + /* Initialize the real time clock. */ + pch_rtc_init(dev); + + /* Initialize the High Precision Event Timers, if present. */ + enable_hpet(); + + /* Initialize Clock Gating */ + enable_clock_gating(dev); + + pch_disable_smm_only_flashing(dev); + +#if CONFIG_HAVE_SMI_HANDLER + pch_lock_smm(dev); +#endif + + pch_fixups(dev); + + return 0; +} + +void lpc_enable(pci_dev_t dev) +{ + /* Enable PCH Display Port */ + writew(0x0010, RCB_REG(DISPBDF)); + setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); +} diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/ivybridge/me_status.c new file mode 100644 index 0000000000..15cf69f40e --- /dev/null +++ b/arch/x86/cpu/ivybridge/me_status.c @@ -0,0 +1,195 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/me_status.c + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +/* HFS1[3:0] Current Working State Values */ +static const char *const me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" +}; + +/* HFS1[8:6] Current Operation State Values */ +static const char *const me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFS[19:16] Current Operation Mode Values */ +static const char *const me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFS[15:12] Error Code Values */ +static const char *const me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* GMES[31:28] ME Progress Code */ +static const char *const me_progress_values[] = { + [ME_GMES_PHASE_ROM] = "ROM Phase", + [ME_GMES_PHASE_BUP] = "BUP Phase", + [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", + [ME_GMES_PHASE_POLICY] = "Policy Module", + [ME_GMES_PHASE_MODULE] = "Module Loading", + [ME_GMES_PHASE_UNKNOWN] = "Unknown", + [ME_GMES_PHASE_HOST] = "Host Communication" +}; + +/* GMES[27:24] Power Management Event */ +static const char *const me_pmevent_values[] = { + [0x00] = "Clean Moff->Mx wake", + [0x01] = "Moff->Mx wake after an error", + [0x02] = "Clean global reset", + [0x03] = "Global reset after an error", + [0x04] = "Clean Intel ME reset", + [0x05] = "Intel ME reset due to exception", + [0x06] = "Pseudo-global reset", + [0x07] = "S0/M0->Sx/M3", + [0x08] = "Sx/M3->S0/M0", + [0x09] = "Non-power cycle reset", + [0x0a] = "Power cycle reset through M3", + [0x0b] = "Power cycle reset through Moff", + [0x0c] = "Sx/Mx->Sx/Moff" +}; + +/* Progress Code 0 states */ +static const char *const me_progress_rom_values[] = { + [0x00] = "BEGIN", + [0x06] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *const me_progress_bup_values[] = { + [0x00] = "Initialization starts", + [0x01] = "Disable the host wake event", + [0x04] = "Flow determination start process", + [0x08] = "Error reading/matching the VSCC table in the descriptor", + [0x0a] = "Check to see if straps say ME DISABLED", + [0x0b] = "Timeout waiting for PWROK", + [0x0d] = "Possibly handle BUP manufacturing override strap", + [0x11] = "Bringup in M3", + [0x12] = "Bringup in M0", + [0x13] = "Flow detection error", + [0x15] = "M3 clock switching error", + [0x18] = "M3 kernel load", + [0x1c] = "T34 missing - cannot program ICC", + [0x1f] = "Waiting for DID BIOS message", + [0x20] = "Waiting for DID BIOS message failure", + [0x21] = "DID reported an error", + [0x22] = "Enabling UMA", + [0x23] = "Enabling UMA error", + [0x24] = "Sending DID Ack to BIOS", + [0x25] = "Sending DID Ack to BIOS error", + [0x26] = "Switching clocks in M0", + [0x27] = "Switching clocks in M0 error", + [0x28] = "ME in temp disable", + [0x32] = "M0 kernel load", +}; + +/* Progress Code 3 states */ +static const char *const me_progress_policy_values[] = { + [0x00] = "Entery into Policy Module", + [0x03] = "Received S3 entry", + [0x04] = "Received S4 entry", + [0x05] = "Received S5 entry", + [0x06] = "Received UPD entry", + [0x07] = "Received PCR entry", + [0x08] = "Received NPCR entry", + [0x09] = "Received host wake", + [0x0a] = "Received AC<>DC switch", + [0x0b] = "Received DRAM Init Done", + [0x0c] = "VSCC Data not found for flash device", + [0x0d] = "VSCC Table is not valid", + [0x0e] = "Flash Partition Boundary is outside address space", + [0x0f] = "ME cannot access the chipset descriptor region", + [0x10] = "Required VSCC values for flash parts do not match", +}; + +void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) +{ + /* Check Current States */ + debug("ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + debug("ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + debug("ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + debug("ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + debug("ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + debug("ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + debug("ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + debug("ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + debug("ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + debug("ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + debug("ME: Progress Phase : %s\n", + me_progress_values[gmes->progress_code]); + debug("ME: Power Management Event : %s\n", + me_pmevent_values[gmes->current_pmevent]); + + debug("ME: Progress Phase State : "); + switch (gmes->progress_code) { + case ME_GMES_PHASE_ROM: /* ROM Phase */ + debug("%s", me_progress_rom_values[gmes->current_state]); + break; + + case ME_GMES_PHASE_BUP: /* Bringup Phase */ + if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) && + me_progress_bup_values[gmes->current_state]) + debug("%s", + me_progress_bup_values[gmes->current_state]); + else + debug("0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ + if (gmes->current_state < + ARRAY_SIZE(me_progress_policy_values) && + me_progress_policy_values[gmes->current_state]) + debug("%s", + me_progress_policy_values[gmes->current_state]); + else + debug("0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_HOST: /* Host Communication Phase */ + if (!gmes->current_state) + debug("Host communication established"); + else + debug("0x%02x", gmes->current_state); + break; + + default: + debug("Unknown 0x%02x", gmes->current_state); + } + debug("\n"); +} diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/ivybridge/microcode_intel.c new file mode 100644 index 0000000000..2440a97c48 --- /dev/null +++ b/arch/x86/cpu/ivybridge/microcode_intel.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2014 Google, Inc + * Copyright (C) 2000 Ronald G. Minnich + * + * Microcode update for Intel PIII and later CPUs + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * struct microcode_update - standard microcode header from Intel + * + * We read this information out of the device tree and use it to determine + * whether the update is applicable or not. We also use the same structure + * to read information from the CPU. + */ +struct microcode_update { + uint header_version; + uint update_revision; + uint date_code; + uint processor_signature; + uint checksum; + uint loader_revision; + uint processor_flags; + const void *data; + int size; +}; + +static int microcode_decode_node(const void *blob, int node, + struct microcode_update *update) +{ + update->data = fdt_getprop(blob, node, "data", &update->size); + if (!update->data) + return -EINVAL; + update->data += UCODE_HEADER_LEN; + update->size -= UCODE_HEADER_LEN; + + update->header_version = fdtdec_get_int(blob, node, + "intel,header-version", 0); + update->update_revision = fdtdec_get_int(blob, node, + "intel,update-revision", 0); + update->date_code = fdtdec_get_int(blob, node, + "intel,date-code", 0); + update->processor_signature = fdtdec_get_int(blob, node, + "intel,processor-signature", 0); + update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0); + update->loader_revision = fdtdec_get_int(blob, node, + "intel,loader-revision", 0); + update->processor_flags = fdtdec_get_int(blob, node, + "intel,processor-flags", 0); + + return 0; +} + +static inline uint32_t microcode_read_rev(void) +{ + /* + * Some Intel CPUs can be very finicky about the CPUID sequence used. + * So this is implemented in assembly so that it works reliably. + */ + uint32_t low, high; + + asm volatile ( + "xorl %%eax, %%eax\n" + "xorl %%edx, %%edx\n" + "movl %2, %%ecx\n" + "wrmsr\n" + "movl $0x01, %%eax\n" + "cpuid\n" + "movl %2, %%ecx\n" + "rdmsr\n" + : /* outputs */ + "=a" (low), "=d" (high) + : /* inputs */ + "i" (MSR_IA32_UCODE_REV) + : /* clobbers */ + "ebx", "ecx" + ); + + return high; +} + +static void microcode_read_cpu(struct microcode_update *cpu) +{ + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ + unsigned int x86_model, x86_family; + struct cpuid_result result; + uint32_t low, high; + + wrmsr(MSR_IA32_UCODE_REV, 0, 0); + result = cpuid(1); + rdmsr(MSR_IA32_UCODE_REV, low, cpu->update_revision); + x86_model = (result.eax >> 4) & 0x0f; + x86_family = (result.eax >> 8) & 0x0f; + cpu->processor_signature = result.eax; + + cpu->processor_flags = 0; + if ((x86_model >= 5) || (x86_family > 6)) { + rdmsr(0x17, low, high); + cpu->processor_flags = 1 << ((high >> 18) & 7); + } + debug("microcode: sig=%#x pf=%#x revision=%#x\n", + cpu->processor_signature, cpu->processor_flags, + cpu->update_revision); +} + +/* Get a microcode update from the device tree and apply it */ +int microcode_update_intel(void) +{ + struct microcode_update cpu, update; + const void *blob = gd->fdt_blob; + int skipped; + int count; + int node; + int ret; + int rev; + + microcode_read_cpu(&cpu); + node = 0; + count = 0; + skipped = 0; + do { + node = fdtdec_next_compatible(blob, node, + COMPAT_INTEL_MICROCODE); + if (node < 0) { + debug("%s: Found %d updates\n", __func__, count); + return count ? 0 : skipped ? -EEXIST : -ENOENT; + } + + ret = microcode_decode_node(blob, node, &update); + if (ret) { + debug("%s: Unable to decode update: %d\n", __func__, + ret); + return ret; + } + if (!(update.processor_signature == cpu.processor_signature && + (update.processor_flags & cpu.processor_flags))) { + debug("%s: Skipping non-matching update, sig=%x, pf=%x\n", + __func__, update.processor_signature, + update.processor_flags); + skipped++; + continue; + } + wrmsr(MSR_IA32_UCODE_WRITE, (ulong)update.data, 0); + rev = microcode_read_rev(); + debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n", + rev, update.date_code & 0xffff, + (update.date_code >> 24) & 0xff, + (update.date_code >> 16) & 0xff); + if (update.update_revision != rev) { + printf("Microcode update failed\n"); + return -EFAULT; + } + count++; + } while (1); +} diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c new file mode 100644 index 0000000000..11dc625da9 --- /dev/null +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -0,0 +1,514 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void enable_vmx(void) +{ + struct cpuid_result regs; +#ifdef CONFIG_ENABLE_VMX + int enable = true; +#else + int enable = false; +#endif + msr_t msr; + + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) + return; + + msr = msr_read(MSR_IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + debug("VMX is locked, so %s will do nothing\n", __func__); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = 0; + msr.lo = 0; + + debug("%s VMX\n", enable ? "Enabling" : "Disabling"); + + /* + * Even though the Intel manual says you must set the lock bit in + * addition to the VMX bit in order for VMX to work, it is incorrect. + * Thus we leave it unlocked for the OS to manage things itself. + * This is good for a few reasons: + * - No need to reflash the bios just to toggle the lock bit. + * - The VMX bits really really should match each other across cores, + * so hard locking it on one while another has the opposite setting + * can easily lead to crashes as code using VMX migrates between + * them. + * - Vendors that want to "upsell" from a bios that disables+locks to + * one that doesn't is sleazy. + * By leaving this to the OS (e.g. Linux), people can do exactly what + * they want on the fly, and do it correctly (e.g. across multiple + * cores). + */ + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + msr_write(MSR_IA32_FEATURE_CONTROL, msr); +} + +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + +int cpu_config_tdp_levels(void) +{ + struct cpuid_result result; + msr_t platform_info; + + /* Minimum CPU revision */ + result = cpuid(1); + if (result.eax < IVB_CONFIG_TDP_MIN_CPUID) + return 0; + + /* Bits 34:33 indicate how many levels supported */ + platform_info = msr_read(MSR_PLATFORM_INFO); + return (platform_info.hi >> 1) & 3; +} + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time) +{ + msr_t msr = msr_read(MSR_PLATFORM_INFO); + msr_t limit; + unsigned power_unit; + unsigned tdp, min_power, max_power, max_time; + u8 power_limit_1_val; + + if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) + return; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = msr_read(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + + /* Get power defaults for this SKU */ + msr = msr_read(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + debug("CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP */ + limit.hi = 0; + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Power limit 2 time is only programmable on SNB EP/EX */ + + msr_write(MSR_PKG_POWER_LIMIT, limit); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + limit.hi = 0; + limit.lo = msr.lo & 0xff; + msr_write(MSR_TURBO_ACTIVATION_RATIO, limit); + } +} + +static void configure_c_states(void) +{ + struct cpuid_result result; + msr_t msr; + + msr = msr_read(MSR_PMG_CST_CONFIG_CTL); + msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */ + msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */ + msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */ + msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */ + msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */ + msr.lo |= 7; /* No package C-state limit */ + msr_write(MSR_PMG_CST_CONFIG_CTL, msr); + + msr = msr_read(MSR_PMG_IO_CAPTURE_ADR); + msr.lo &= ~0x7ffff; + msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */ + msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */ + msr_write(MSR_PMG_IO_CAPTURE_ADR, msr); + + msr = msr_read(MSR_MISC_PWR_MGMT); + msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */ + msr_write(MSR_MISC_PWR_MGMT, msr); + + msr = msr_read(MSR_POWER_CTL); + msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */ + msr.lo |= (1 << 1); /* C1E Enable */ + msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */ + msr_write(MSR_POWER_CTL, msr); + + /* C3 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; + msr_write(MSR_PKGC3_IRTL, msr); + + /* C6 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; + msr_write(MSR_PKGC6_IRTL, msr); + + /* C7 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; + msr_write(MSR_PKGC7_IRTL, msr); + + /* Primary Plane Current Limit */ + msr = msr_read(MSR_PP0_CURRENT_CONFIG); + msr.lo &= ~0x1fff; + msr.lo |= PP0_CURRENT_LIMIT; + msr_write(MSR_PP0_CURRENT_CONFIG, msr); + + /* Secondary Plane Current Limit */ + msr = msr_read(MSR_PP1_CURRENT_CONFIG); + msr.lo &= ~0x1fff; + result = cpuid(1); + if (result.eax >= 0x30600) + msr.lo |= PP1_CURRENT_LIMIT_IVB; + else + msr.lo |= PP1_CURRENT_LIMIT_SNB; + msr_write(MSR_PP1_CURRENT_CONFIG, msr); +} + +static int configure_thermal_target(void) +{ + int tcc_offset; + msr_t msr; + int node; + + /* Find pointer to CPU configuration */ + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_INTEL_MODEL_206AX); + if (node < 0) + return -ENOENT; + tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0); + + /* Set TCC activaiton offset if supported */ + msr = msr_read(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && tcc_offset) { + msr = msr_read(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (tcc_offset & 0xf) << 24; + msr_write(MSR_TEMPERATURE_TARGET, msr); + } + + return 0; +} + +static void configure_misc(void) +{ + msr_t msr; + + msr = msr_read(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr_write(IA32_MISC_ENABLE, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + msr_write(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = msr_read(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + msr_write(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + struct cpuid_result cpuid_regs; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + cpuid_regs = cpuid(1); + if (cpuid_regs.ecx & (1 << 18)) { + msr = msr_read(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + msr_write(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void set_max_ratio(void) +{ + msr_t msr, perf_ctl; + + perf_ctl.hi = 0; + + /* Check for configurable TDP option */ + if (cpu_config_tdp_levels()) { + /* Set to nominal TDP ratio */ + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = msr_read(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + msr_write(IA32_PERF_CTL, perf_ctl); + + debug("model_x06ax: frequency set to %d\n", + ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + + /* Energy Policy is bits 3:0 */ + msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr); + + debug("model_x06ax: energy policy set to %u\n", policy); +} + +static void configure_mca(void) +{ + msr_t msr; + int i; + + msr.lo = 0; + msr.hi = 0; + /* This should only be done on a cold boot */ + for (i = 0; i < 7; i++) + msr_write(IA32_MC0_STATUS + (i * 4), msr); +} + +#if CONFIG_USBDEBUG +static unsigned ehci_debug_addr; +#endif + +/* + * Initialize any extra cores/threads in this package. + */ +static int intel_cores_init(struct x86_cpu_priv *cpu) +{ + struct cpuid_result result; + unsigned threads_per_package, threads_per_core, i; + + /* Logical processors (threads) per core */ + result = cpuid_ext(0xb, 0); + threads_per_core = result.ebx & 0xffff; + + /* Logical processors (threads) per package */ + result = cpuid_ext(0xb, 1); + threads_per_package = result.ebx & 0xffff; + + debug("CPU: %u has %u cores, %u threads per core\n", + cpu->apic_id, threads_per_package / threads_per_core, + threads_per_core); + + for (i = 1; i < threads_per_package; ++i) { + struct x86_cpu_priv *new_cpu; + + new_cpu = calloc(1, sizeof(*new_cpu)); + if (!new_cpu) + return -ENOMEM; + + new_cpu->apic_id = cpu->apic_id + i; + + /* Update APIC ID if no hyperthreading */ + if (threads_per_core == 1) + new_cpu->apic_id <<= 1; + + debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id); + +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + /* Start the new cpu */ + if (!start_cpu(new_cpu)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU %u would not start!\n", + new_cpu->apic_id); + new_cpu->start_err = 1; + } +#endif + } + + return 0; +} + +int model_206ax_init(struct x86_cpu_priv *cpu) +{ + int ret; + + /* Clear out pending MCEs */ + configure_mca(); + +#if CONFIG_USBDEBUG + /* Is this caution really needed? */ + if (!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + + /* Setup MTRRs based on physical address size */ +#if 0 /* TODO: Implement this */ + struct cpuid_result cpuid_regs; + + cpuid_regs = cpuid(0x80000008); + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_mtrr_check(); +#endif + +#if CONFIG_USBDEBUG + set_ehci_debug(ehci_debug_addr); +#endif + + /* Enable the local cpu apics */ + enable_lapic_tpr(); + lapic_setup(); + + /* Enable virtualization if enabled in CMOS */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Thermal throttle activation offset */ + ret = configure_thermal_target(); + if (ret) + return ret; + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Set Max Ratio */ + set_max_ratio(); + + /* Enable Turbo */ + turbo_enable(); + + /* Start up extra cores */ + intel_cores_init(cpu); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/mrccache.c b/arch/x86/cpu/ivybridge/mrccache.c new file mode 100644 index 0000000000..0f1a64b268 --- /dev/null +++ b/arch/x86/cpu/ivybridge/mrccache.c @@ -0,0 +1,156 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/mrccache.c + * + * Copyright (C) 2014 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mrc_data_container *next_mrc_block( + struct mrc_data_container *mrc_cache) +{ + /* MRC data blocks are aligned within the region */ + u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->data_size; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { + mrc_size &= ~(MRC_DATA_ALIGN - 1UL); + mrc_size += MRC_DATA_ALIGN; + } + + u8 *region_ptr = (u8 *)mrc_cache; + region_ptr += mrc_size; + return (struct mrc_data_container *)region_ptr; +} + +static int is_mrc_cache(struct mrc_data_container *cache) +{ + return cache && (cache->signature == MRC_DATA_SIGNATURE); +} + +/* + * Find the largest index block in the MRC cache. Return NULL if none is + * found. + */ +struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry) +{ + struct mrc_data_container *cache, *next; + ulong base_addr, end_addr; + uint id; + + base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset; + end_addr = base_addr + entry->length; + cache = NULL; + + /* Search for the last filled entry in the region */ + for (id = 0, next = (struct mrc_data_container *)base_addr; + is_mrc_cache(next); + id++) { + cache = next; + next = next_mrc_block(next); + if ((ulong)next >= end_addr) + break; + } + + if (id-- == 0) { + debug("%s: No valid MRC cache found.\n", __func__); + return NULL; + } + + /* Verify checksum */ + if (cache->checksum != compute_ip_checksum(cache->data, + cache->data_size)) { + printf("%s: MRC cache checksum mismatch\n", __func__); + return NULL; + } + + debug("%s: picked entry %u from cache block\n", __func__, id); + + return cache; +} + +/** + * find_next_mrc_cache() - get next cache entry + * + * @entry: MRC cache flash area + * @cache: Entry to start from + * + * @return next cache entry if found, NULL if we got to the end + */ +static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry, + struct mrc_data_container *cache) +{ + ulong base_addr, end_addr; + + base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset; + end_addr = base_addr + entry->length; + + cache = next_mrc_block(cache); + if ((ulong)cache >= end_addr) { + /* Crossed the boundary */ + cache = NULL; + debug("%s: no available entries found\n", __func__); + } else { + debug("%s: picked next entry from cache block at %p\n", + __func__, cache); + } + + return cache; +} + +int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, + struct mrc_data_container *cur) +{ + struct mrc_data_container *cache; + ulong offset; + ulong base_addr; + int ret; + + /* Find the last used block */ + base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset; + debug("Updating MRC cache data\n"); + cache = mrccache_find_current(entry); + if (cache && (cache->data_size == cur->data_size) && + (!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) { + debug("MRC data in flash is up to date. No update\n"); + return -EEXIST; + } + + /* Move to the next block, which will be the first unused block */ + if (cache) + cache = find_next_mrc_cache(entry, cache); + + /* + * If we have got to the end, erase the entire mrc-cache area and start + * again at block 0. + */ + if (!cache) { + debug("Erasing the MRC cache region of %x bytes at %x\n", + entry->length, entry->offset); + + ret = spi_flash_erase(sf, entry->offset, entry->length); + if (ret) { + debug("Failed to erase flash region\n"); + return ret; + } + cache = (struct mrc_data_container *)base_addr; + } + + /* Write the data out */ + offset = (ulong)cache - base_addr + entry->offset; + debug("Write MRC cache update to flash at %lx\n", offset); + ret = spi_flash_write(sf, offset, cur->data_size + sizeof(*cur), cur); + if (ret) { + debug("Failed to write to SPI flash\n"); + return ret; + } + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c new file mode 100644 index 0000000000..c50b5ded83 --- /dev/null +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -0,0 +1,188 @@ +/* + * From Coreboot northbridge/intel/sandybridge/northbridge.c + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int bridge_revision_id = -1; + +int bridge_silicon_revision(void) +{ + if (bridge_revision_id < 0) { + struct cpuid_result result; + uint8_t stepping, bridge_id; + pci_dev_t dev; + + result = cpuid(1); + stepping = result.eax & 0xf; + dev = PCI_BDF(0, 0, 0); + bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0; + bridge_revision_id = bridge_id | stepping; + } + + return bridge_revision_id; +} + +/* + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) + * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI + */ +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 384; + +static int get_pcie_bar(u32 *base, u32 *len) +{ + pci_dev_t dev = PCI_BDF(0, 0, 0); + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: /* 256MB */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static void add_fixed_resources(pci_dev_t dev, int index) +{ + u32 pcie_config_base, pcie_config_size; + + if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { + debug("Adding PCIe config bar base=0x%08x size=0x%x\n", + pcie_config_base, pcie_config_size); + } +} + +static void northbridge_dmi_init(pci_dev_t dev) +{ + /* Clear error status bits */ + writel(0xffffffff, DMIBAR_REG(0x1c4)); + writel(0xffffffff, DMIBAR_REG(0x1d0)); + + /* Steps prior to DMI ASPM */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), + 1 << 21); + } + + setbits_le32(DMIBAR_REG(0x238), 1 << 29); + + if (bridge_silicon_revision() >= SNB_STEP_D0) { + setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); + } else if (bridge_silicon_revision() >= SNB_STEP_D1) { + clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); + setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); + } + + /* Enable ASPM on SNB link, should happen before PCH link */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) + setbits_le32(DMIBAR_REG(0xd04), 1 << 4); + + setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); +} + +void northbridge_init(pci_dev_t dev) +{ + u32 bridge_type; + + add_fixed_resources(dev, 6); + northbridge_dmi_init(dev); + + bridge_type = readl(MCHBAR_REG(0x5f10)); + bridge_type &= ~0xff; + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* Enable Power Aware Interrupt Routing - fixed priority */ + clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); + + /* 30h for IvyBridge */ + bridge_type |= 0x30; + } else { + /* 20h for Sandybridge */ + bridge_type |= 0x20; + } + writel(bridge_type, MCHBAR_REG(0x5f10)); + + /* + * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management + */ + setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); + debug("Set BIOS_RESET_CPL\n"); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + set_power_limits(28); + + /* + * CPUs with configurable TDP also need power limits set + * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. + */ + if (cpu_config_tdp_levels()) { + msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); + + writel(msr.lo, MCHBAR_REG(0x59A0)); + writel(msr.hi, MCHBAR_REG(0x59A4)); + } + + /* Set here before graphics PM init */ + writel(0x00100001, MCHBAR_REG(0x5500)); +} + +void northbridge_enable(pci_dev_t dev) +{ +#if CONFIG_HAVE_ACPI_RESUME + switch (pci_read_config32(dev, SKPAD)) { + case 0xcafebabe: + debug("Normal boot.\n"); + apci_set_slp_type(0); + break; + case 0xcafed00d: + debug("S3 Resume.\n"); + apci_set_slp_type(3); + break; + default: + debug("Unknown boot method, assuming normal.\n"); + apci_set_slp_type(0); + break; + } +#endif +} diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c new file mode 100644 index 0000000000..fa04d488f3 --- /dev/null +++ b/arch/x86/cpu/ivybridge/pch.c @@ -0,0 +1,123 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +static int pch_revision_id = -1; +static int pch_type = -1; + +int pch_silicon_revision(void) +{ + pci_dev_t dev; + + dev = PCH_LPC_DEV; + + if (pch_revision_id < 0) + pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); + return pch_revision_id; +} + +int pch_silicon_type(void) +{ + pci_dev_t dev; + + dev = PCH_LPC_DEV; + + if (pch_type < 0) + pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); + return pch_type; +} + +int pch_silicon_supported(int type, int rev) +{ + int cur_type = pch_silicon_type(); + int cur_rev = pch_silicon_revision(); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned try = IOBP_RETRY; + u32 data; + + while (try--) { + data = readl(RCB_REG(IOBPS)); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printf("IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data; + + /* Set the address */ + writel(address, RCB_REG(IOBPIRI)); + + /* READ OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_READ_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = readl(RCB_REG(IOBPD)); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { + printf("IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Write IOBP data */ + writel(data, RCB_REG(IOBPD)); + if (!iobp_poll()) + return; +} diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c new file mode 100644 index 0000000000..452d1c3a15 --- /dev/null +++ b/arch/x86/cpu/ivybridge/pci.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008,2009 + * Graeme Russ, + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + if (secondary != 0) + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_ivybridge_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, + {} +}; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->config_table = pci_ivybridge_config_table; + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + hose->region_count = 3; +} + +int board_pci_pre_scan(struct pci_controller *hose) +{ + pci_dev_t dev; + u16 reg16; + + bd82x6x_init(); + + reg16 = 0xff; + dev = PCH_DEV; + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + pci_write_bar32(hose, dev, 0, 0xf0000000); + + return 0; +} + +int board_pci_post_scan(struct pci_controller *hose) +{ + int ret; + + ret = bd82x6x_init_pci_devices(); + if (ret) { + printf("bd82x6x_init_pci_devices() failed: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c new file mode 100644 index 0000000000..69e31b3ca2 --- /dev/null +++ b/arch/x86/cpu/ivybridge/report_platform.c @@ -0,0 +1,89 @@ +/* + * From Coreboot src/northbridge/intel/sandybridge/report_platform.c + * + * Copyright (C) 2012 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +static void report_cpu_info(void) +{ + char cpu_string[CPU_MAX_NAME_LEN], *cpu_name; + const char *mode[] = {"NOT ", ""}; + struct cpuid_result cpuidr; + int vt, txt, aes; + u32 index; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + cpu_name = cpu_string; + } else { + cpu_name = cpu_get_name(cpu_string); + } + + cpuidr = cpuid(1); + debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name); + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + debug("AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +/* The PCI id name match comes from Intel document 472178 */ +static struct { + u16 dev_id; + const char *dev_name; +} pch_table[] = { + {0x1E41, "Desktop Sample"}, + {0x1E42, "Mobile Sample"}, + {0x1E43, "SFF Sample"}, + {0x1E44, "Z77"}, + {0x1E45, "H71"}, + {0x1E46, "Z75"}, + {0x1E47, "Q77"}, + {0x1E48, "Q75"}, + {0x1E49, "B75"}, + {0x1E4A, "H77"}, + {0x1E53, "C216"}, + {0x1E55, "QM77"}, + {0x1E56, "QS77"}, + {0x1E58, "UM77"}, + {0x1E57, "HM77"}, + {0x1E59, "HM76"}, + {0x1E5D, "HM75"}, + {0x1E5E, "HM70"}, + {0x1E5F, "NM70"}, +}; + +static void report_pch_info(void) +{ + const char *pch_type = "Unknown"; + int i; + u16 dev_id; + uint8_t rev_id; + + dev_id = pci_read_config16(PCH_LPC_DEV, 2); + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].dev_id == dev_id) { + pch_type = pch_table[i].dev_name; + break; + } + } + rev_id = pci_read_config8(PCH_LPC_DEV, 8); + debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id, + rev_id); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_pch_info(); +} diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c new file mode 100644 index 0000000000..bbcd47da60 --- /dev/null +++ b/arch/x86/cpu/ivybridge/sata.c @@ -0,0 +1,225 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include + +static inline u32 sir_read(pci_dev_t dev, int idx) +{ + pci_write_config32(dev, SATA_SIRI, idx); + return pci_read_config32(dev, SATA_SIRD); +} + +static inline void sir_write(pci_dev_t dev, int idx, u32 value) +{ + pci_write_config32(dev, SATA_SIRI, idx); + pci_write_config32(dev, SATA_SIRD, value); +} + +static void common_sata_init(pci_dev_t dev, unsigned int port_map) +{ + u32 reg32; + u16 reg16; + + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Port enable */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= port_map; + pci_write_config16(dev, 0x92, reg16); + + /* SATA Initialization register */ + port_map &= 0xff; + pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); +} + +void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) +{ + unsigned int port_map, speed_support, port_tx; + struct pci_controller *hose = pci_bus_to_hose(0); + const char *mode; + u32 reg32; + u16 reg16; + + debug("SATA: Initializing...\n"); + + /* SATA configuration */ + port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); + speed_support = fdtdec_get_int(blob, node, + "sata_interface_speed_support", 0); + + /* Enable BARs */ + pci_write_config16(dev, PCI_COMMAND, 0x0007); + + mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); + if (!mode || !strcmp(mode, "ahci")) { + u32 abar; + + debug("SATA: Controller in AHCI mode\n"); + + /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); + + common_sata_init(dev, 0x8000 | port_map); + + /* Initialize AHCI memory-mapped space */ + abar = pci_read_bar32(hose, dev, 5); + debug("ABAR: %08X\n", abar); + /* CAP (HBA Capabilities) : enable power management */ + reg32 = readl(abar + 0x00); + reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ + /* Set ISS, if available */ + if (speed_support) { + reg32 &= ~0x00f00000; + reg32 |= (speed_support & 0x03) << 20; + } + writel(reg32, abar + 0x00); + /* PI (Ports implemented) */ + writel(port_map, abar + 0x0c); + (void) readl(abar + 0x0c); /* Read back 1 */ + (void) readl(abar + 0x0c); /* Read back 2 */ + /* CAP2 (HBA Capabilities Extended)*/ + reg32 = readl(abar + 0x24); + reg32 &= ~0x00000002; + writel(reg32, abar + 0x24); + /* VSP (Vendor Specific Register */ + reg32 = readl(abar + 0xa0); + reg32 &= ~0x00000005; + writel(reg32, abar + 0xa0); + } else if (!strcmp(mode, "combined")) { + debug("SATA: Controller in combined mode\n"); + + /* No AHCI: clear AHCI base */ + pci_write_bar32(hose, dev, 5, 0x00000000); + /* And without AHCI BAR no memory decoding */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + pci_write_config8(dev, 0x09, 0x80); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + + common_sata_init(dev, port_map); + } else { + debug("SATA: Controller in plain-ide mode\n"); + + /* No AHCI: clear AHCI base */ + pci_write_bar32(hose, dev, 5, 0x00000000); + + /* And without AHCI BAR no memory decoding */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* + * Native mode capable on both primary and secondary (0xa) + * OR'ed with enabled (0x50) = 0xf + */ + pci_write_config8(dev, 0x09, 0x8f); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0xff); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_SITRE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); + + common_sata_init(dev, port_map); + } + + /* Set Gen3 Transmitter settings if needed */ + port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); + if (port_tx) + pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx); + + port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); + if (port_tx) + pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx); + + /* Additional Programming Requirements */ + sir_write(dev, 0x04, 0x00001600); + sir_write(dev, 0x28, 0xa0000033); + reg32 = sir_read(dev, 0x54); + reg32 &= 0xff000000; + reg32 |= 0x5555aa; + sir_write(dev, 0x54, reg32); + sir_write(dev, 0x64, 0xcccc8484); + reg32 = sir_read(dev, 0x68); + reg32 &= 0xffff0000; + reg32 |= 0xcccc; + sir_write(dev, 0x68, reg32); + reg32 = sir_read(dev, 0x78); + reg32 &= 0x0000ffff; + reg32 |= 0x88880000; + sir_write(dev, 0x78, reg32); + sir_write(dev, 0x84, 0x001c7000); + sir_write(dev, 0x88, 0x88338822); + sir_write(dev, 0xa0, 0x001c7000); + sir_write(dev, 0xc4, 0x0c0c0c0c); + sir_write(dev, 0xc8, 0x0c0c0c0c); + sir_write(dev, 0xd4, 0x10000000); + + pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); + pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); +} + +void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) +{ + unsigned port_map; + const char *mode; + u16 map = 0; + + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); + if (mode && !strcmp(mode, "ahci")) + map = 0x0060; + port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); + + map |= (port_map ^ 0x3f) << 8; + pci_write_config16(dev, 0x90, map); +} diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c new file mode 100644 index 0000000000..49634485f3 --- /dev/null +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 + * Graeme Russ, + * + * Portions from Coreboot mainboard/google/link/romstage.c + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define CMOS_OFFSET_MRC_SEED 152 +#define CMOS_OFFSET_MRC_SEED_S3 156 +#define CMOS_OFFSET_MRC_SEED_CHK 160 + +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. + * It overrides the default implementation found elsewhere which simply + * picks the end of ram, wherever that may be. The location of the stack, + * the relocation address, and how far U-Boot is moved by relocation are + * set in the global data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + struct memory_info *info = &gd->arch.meminfo; + uintptr_t dest_addr = 0; + struct memory_area *largest = NULL; + int i; + + /* Find largest area of memory below 4GB */ + + for (i = 0; i < info->num_areas; i++) { + struct memory_area *area = &info->area[i]; + + if (area->start >= 1ULL << 32) + continue; + if (!largest || area->size > largest->size) + largest = area; + } + + /* If no suitable area was found, return an error. */ + assert(largest); + if (!largest || largest->size < (2 << 20)) + panic("No available memory found for relocation"); + + dest_addr = largest->start + largest->size; + + return (ulong)dest_addr; +} + +void dram_init_banksize(void) +{ + struct memory_info *info = &gd->arch.meminfo; + int num_banks; + int i; + + for (i = 0, num_banks = 0; i < info->num_areas; i++) { + struct memory_area *area = &info->area[i]; + + if (area->start >= 1ULL << 32) + continue; + gd->bd->bi_dram[num_banks].start = area->start; + gd->bd->bi_dram[num_banks].size = area->size; + num_banks++; + } +} + +static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry) +{ + const void *blob = gd->fdt_blob; + int node, spi_node, mrc_node; + int upto; + + /* Find the flash chip within the SPI controller node */ + upto = 0; + spi_node = fdtdec_next_alias(blob, "spi", COMPAT_INTEL_ICH_SPI, &upto); + if (spi_node < 0) + return -ENOENT; + node = fdt_first_subnode(blob, spi_node); + if (node < 0) + return -ECHILD; + + /* Find the place where we put the MRC cache */ + mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache"); + if (mrc_node < 0) + return -EPERM; + + if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry)) + return -EINVAL; + + if (sfp) { + *sfp = spi_flash_probe_fdt(blob, node, spi_node); + if (!*sfp) + return -EBADF; + } + + return 0; +} + +static int read_seed_from_cmos(struct pei_data *pei_data) +{ + u16 c1, c2, checksum, seed_checksum; + + /* + * Read scrambler seeds from CMOS RAM. We don't want to store them in + * SPI flash since they change on every boot and that would wear down + * the flash too much. So we store these in CMOS and the large MRC + * data in SPI flash. + */ + pei_data->scrambler_seed = rtc_read32(CMOS_OFFSET_MRC_SEED); + debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", + pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); + + pei_data->scrambler_seed_s3 = rtc_read32(CMOS_OFFSET_MRC_SEED_S3); + debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", + pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); + + /* Compute seed checksum and compare */ + c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, + sizeof(u32)); + c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, + sizeof(u32)); + checksum = add_ip_checksums(sizeof(u32), c1, c2); + + seed_checksum = rtc_read8(CMOS_OFFSET_MRC_SEED_CHK); + seed_checksum |= rtc_read8(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; + + if (checksum != seed_checksum) { + debug("%s: invalid seed checksum\n", __func__); + pei_data->scrambler_seed = 0; + pei_data->scrambler_seed_s3 = 0; + return -EINVAL; + } + + return 0; +} + +static int prepare_mrc_cache(struct pei_data *pei_data) +{ + struct mrc_data_container *mrc_cache; + struct fmap_entry entry; + int ret; + + ret = read_seed_from_cmos(pei_data); + if (ret) + return ret; + ret = get_mrc_entry(NULL, &entry); + if (ret) + return ret; + mrc_cache = mrccache_find_current(&entry); + if (!mrc_cache) + return -ENOENT; + + /* + * TODO(sjg@chromium.org): Skip this for now as it causes boot + * problems + */ + if (0) { + pei_data->mrc_input = mrc_cache->data; + pei_data->mrc_input_len = mrc_cache->data_size; + } + debug("%s: at %p, size %x checksum %04x\n", __func__, + pei_data->mrc_input, pei_data->mrc_input_len, + mrc_cache->checksum); + + return 0; +} + +static int build_mrc_data(struct mrc_data_container **datap) +{ + struct mrc_data_container *data; + int orig_len; + int output_len; + + orig_len = gd->arch.mrc_output_len; + output_len = ALIGN(orig_len, 16); + data = malloc(output_len + sizeof(*data)); + if (!data) + return -ENOMEM; + data->signature = MRC_DATA_SIGNATURE; + data->data_size = output_len; + data->reserved = 0; + memcpy(data->data, gd->arch.mrc_output, orig_len); + + /* Zero the unused space in aligned buffer. */ + if (output_len > orig_len) + memset(data->data + orig_len, 0, output_len - orig_len); + + data->checksum = compute_ip_checksum(data->data, output_len); + *datap = data; + + return 0; +} + +static int write_seeds_to_cmos(struct pei_data *pei_data) +{ + u16 c1, c2, checksum; + + /* Save the MRC seed values to CMOS */ + rtc_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); + debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", + pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); + + rtc_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); + debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", + pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); + + /* Save a simple checksum of the seed values */ + c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, + sizeof(u32)); + c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, + sizeof(u32)); + checksum = add_ip_checksums(sizeof(u32), c1, c2); + + rtc_write8(CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); + rtc_write8(CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); + + return 0; +} + +static int sdram_save_mrc_data(void) +{ + struct mrc_data_container *data; + struct fmap_entry entry; + struct spi_flash *sf; + int ret; + + if (!gd->arch.mrc_output_len) + return 0; + debug("Saving %d bytes of MRC output data to SPI flash\n", + gd->arch.mrc_output_len); + + ret = get_mrc_entry(&sf, &entry); + if (ret) + goto err_entry; + ret = build_mrc_data(&data); + if (ret) + goto err_data; + ret = mrccache_update(sf, &entry, data); + if (!ret) + debug("Saved MRC data with checksum %04x\n", data->checksum); + + free(data); +err_data: + spi_flash_free(sf); +err_entry: + if (ret) + debug("%s: Failed: %d\n", __func__, ret); + return ret; +} + +/* Use this hook to save our SDRAM parameters */ +int misc_init_r(void) +{ + int ret; + + ret = sdram_save_mrc_data(); + if (ret) + printf("Unable to save MRC data: %d\n", ret); + + return 0; +} + +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active" +}; + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +static void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = readl(MCHBAR_REG(0x5000)); + addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); + addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); + + debug("memcfg DDR3 clock %d MHz\n", + (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); + debug("memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + debug(" enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + debug(" rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + debug(" DIMMA %d MB width x%d %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? 16 : 8, + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + debug(" DIMMB %d MB width x%d %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 20) & 1) ? 16 : 8, + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} + +static void post_system_agent_init(struct pei_data *pei_data) +{ + /* If PCIe init is skipped, set the PEG clock gating */ + if (!pei_data->pcie_init) + setbits_le32(MCHBAR_REG(0x7010), 1); +} + +static asmlinkage void console_tx_byte(unsigned char byte) +{ +#ifdef DEBUG + putc(byte); +#endif +} + +static int recovery_mode_enabled(void) +{ + return false; +} + +/** + * Find the PEI executable in the ROM and execute it. + * + * @param pei_data: configuration data for UEFI PEI reference code + */ +int sdram_initialise(struct pei_data *pei_data) +{ + unsigned version; + const char *data; + uint16_t done; + int ret; + + report_platform_info(); + + /* Wait for ME to be ready */ + ret = intel_early_me_init(); + if (ret) + return ret; + ret = intel_early_me_uma_size(); + if (ret < 0) + return ret; + + debug("Starting UEFI PEI System Agent\n"); + + /* + * Do not pass MRC data in for recovery mode boot, + * Always pass it in for S3 resume. + */ + if (!recovery_mode_enabled() || + pei_data->boot_mode == PEI_BOOT_RESUME) { + ret = prepare_mrc_cache(pei_data); + if (ret) + debug("prepare_mrc_cache failed: %d\n", ret); + } + + /* If MRC data is not found we cannot continue S3 resume. */ + if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { + debug("Giving up in sdram_initialize: No MRC data\n"); + outb(0x6, PORT_RESET); + cpu_hlt(); + } + + /* Pass console handler in pei_data */ + pei_data->tx_byte = console_tx_byte; + + debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); + + data = (char *)CONFIG_X86_MRC_ADDR; + if (data) { + int rv; + int (*func)(struct pei_data *); + + debug("Calling MRC at %p\n", data); + post_code(POST_PRE_MRC); + func = (int (*)(struct pei_data *))data; + rv = func(pei_data); + post_code(POST_MRC); + if (rv) { + switch (rv) { + case -1: + printf("PEI version mismatch.\n"); + break; + case -2: + printf("Invalid memory frequency.\n"); + break; + default: + printf("MRC returned %x.\n", rv); + } + printf("Nonzero MRC return value.\n"); + return -EFAULT; + } + } else { + printf("UEFI PEI System Agent not found.\n"); + return -ENOSYS; + } + +#if CONFIG_USBDEBUG + /* mrc.bin reconfigures USB, so reinit it to have debug */ + early_usbdebug_init(); +#endif + + version = readl(MCHBAR_REG(0x5034)); + debug("System Agent Version %d.%d.%d Build %d\n", + version >> 24 , (version >> 16) & 0xff, + (version >> 8) & 0xff, version & 0xff); + debug("MCR output data length %#x at %p\n", pei_data->mrc_output_len, + pei_data->mrc_output); + + /* + * Send ME init done for SandyBridge here. This is done inside the + * SystemAgent binary on IvyBridge + */ + done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID); + done &= BASE_REV_MASK; + if (BASE_REV_SNB == done) + intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); + else + intel_early_me_status(); + + post_system_agent_init(pei_data); + report_memory_config(); + + /* S3 resume: don't save scrambler seed or MRC data */ + if (pei_data->boot_mode != PEI_BOOT_RESUME) { + /* + * This will be copied to SDRAM in reserve_arch(), then written + * to SPI flash in sdram_save_mrc_data() + */ + gd->arch.mrc_output = (char *)pei_data->mrc_output; + gd->arch.mrc_output_len = pei_data->mrc_output_len; + ret = write_seeds_to_cmos(pei_data); + if (ret) + debug("Failed to write seeds to CMOS: %d\n", ret); + } + + return 0; +} + +int reserve_arch(void) +{ + u16 checksum; + + checksum = compute_ip_checksum(gd->arch.mrc_output, + gd->arch.mrc_output_len); + debug("Saving %d bytes for MRC output data, checksum %04x\n", + gd->arch.mrc_output_len, checksum); + gd->start_addr_sp -= gd->arch.mrc_output_len; + memcpy((void *)gd->start_addr_sp, gd->arch.mrc_output, + gd->arch.mrc_output_len); + gd->arch.mrc_output = (char *)gd->start_addr_sp; + gd->start_addr_sp &= ~0xf; + + return 0; +} + +static int copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {41, 42, 43, 10, -1}; + int spd_index; + const void *blob = gd->fdt_blob; + int node, spd_node; + int ret, i; + + for (i = 0; ; i++) { + if (gpio_vector[i] == -1) + break; + ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); + if (ret) { + debug("%s: Could not request gpio %d\n", __func__, + gpio_vector[i]); + return ret; + } + } + spd_index = gpio_get_values_as_int(gpio_vector); + debug("spd index %d\n", spd_index); + node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); + if (node < 0) { + printf("SPD data not found.\n"); + return -ENOENT; + } + + for (spd_node = fdt_first_subnode(blob, node); + spd_node > 0; + spd_node = fdt_next_subnode(blob, spd_node)) { + const char *data; + int len; + + if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) + continue; + data = fdt_getprop(blob, spd_node, "data", &len); + if (len < sizeof(peid->spd_data[0])) { + printf("Missing SPD data\n"); + return -EINVAL; + } + + debug("Using SDRAM SPD data for '%s'\n", + fdt_get_name(blob, spd_node, NULL)); + memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); + break; + } + + if (spd_node < 0) { + printf("No SPD data found for index %d\n", spd_index); + return -ENOENT; + } + + return 0; +} + +/** + * add_memory_area() - Add a new usable memory area to our list + * + * Note: @start and @end must not span the first 4GB boundary + * + * @info: Place to store memory info + * @start: Start of this memory area + * @end: End of this memory area + 1 + */ +static int add_memory_area(struct memory_info *info, + uint64_t start, uint64_t end) +{ + struct memory_area *ptr; + + if (info->num_areas == CONFIG_NR_DRAM_BANKS) + return -ENOSPC; + + ptr = &info->area[info->num_areas]; + ptr->start = start; + ptr->size = end - start; + info->total_memory += ptr->size; + if (ptr->start < (1ULL << 32)) + info->total_32bit_memory += ptr->size; + debug("%d: memory %llx size %llx, total now %llx / %llx\n", + info->num_areas, ptr->start, ptr->size, + info->total_32bit_memory, info->total_memory); + info->num_areas++; + + return 0; +} + +/** + * sdram_find() - Find available memory + * + * This is a bit complicated since on x86 there are system memory holes all + * over the place. We create a list of available memory blocks + */ +static int sdram_find(pci_dev_t dev) +{ + struct memory_info *info = &gd->arch.meminfo; + uint32_t tseg_base, uma_size, tolud; + uint64_t tom, me_base, touud; + uint64_t uma_memory_base = 0; + uint64_t uma_memory_size; + unsigned long long tomk; + uint16_t ggc; + + /* Total Memory 2GB example: + * + * 00000000 0000MB-1992MB 1992MB RAM (writeback) + * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) + * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) + * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) + * 7f200000 2034MB TOLUD + * 7f800000 2040MB MEBASE + * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) + * 80000000 2048MB TOM + * 100000000 4096MB-4102MB 6MB RAM (writeback) + * + * Total Memory 4GB example: + * + * 00000000 0000MB-2768MB 2768MB RAM (writeback) + * ad000000 2768MB-2776MB 8MB TSEG (SMRR) + * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) + * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) + * afa00000 2810MB TOLUD + * ff800000 4088MB MEBASE + * ff800000 4088MB-4096MB 8MB ME UMA (uncached) + * 100000000 4096MB TOM + * 100000000 4096MB-5374MB 1278MB RAM (writeback) + * 14fe00000 5368MB TOUUD + */ + + /* Top of Upper Usable DRAM, including remap */ + touud = pci_read_config32(dev, TOUUD+4); + touud <<= 32; + touud |= pci_read_config32(dev, TOUUD); + + /* Top of Lower Usable DRAM */ + tolud = pci_read_config32(dev, TOLUD); + + /* Top of Memory - does not account for any UMA */ + tom = pci_read_config32(dev, 0xa4); + tom <<= 32; + tom |= pci_read_config32(dev, 0xa0); + + debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); + + /* ME UMA needs excluding if total memory <4GB */ + me_base = pci_read_config32(dev, 0x74); + me_base <<= 32; + me_base |= pci_read_config32(dev, 0x70); + + debug("MEBASE %llx\n", me_base); + + /* TODO: Get rid of all this shifting by 10 bits */ + tomk = tolud >> 10; + if (me_base == tolud) { + /* ME is from MEBASE-TOM */ + uma_size = (tom - me_base) >> 10; + /* Increment TOLUD to account for ME as RAM */ + tolud += uma_size << 10; + /* UMA starts at old TOLUD */ + uma_memory_base = tomk * 1024ULL; + uma_memory_size = uma_size * 1024ULL; + debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); + } + + /* Graphics memory comes next */ + ggc = pci_read_config16(dev, GGC); + if (!(ggc & 2)) { + debug("IGD decoded, subtracting "); + + /* Graphics memory */ + uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; + debug("%uM UMA", uma_size >> 10); + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + + /* GTT Graphics Stolen Memory Size (GGMS) */ + uma_size = ((ggc >> 8) & 0x3) * 1024ULL; + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + debug(" and %uM GTT\n", uma_size >> 10); + } + + /* Calculate TSEG size from its base which must be below GTT */ + tseg_base = pci_read_config32(dev, 0xb8); + uma_size = (uma_memory_base - tseg_base) >> 10; + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); + + debug("Available memory below 4GB: %lluM\n", tomk >> 10); + + /* Report the memory regions */ + add_memory_area(info, 1 << 20, 2 << 28); + add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); + add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); + add_memory_area(info, 1ULL << 32, touud); + + /* Add MTRRs for memory */ + mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); + mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20); + mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20); + mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20); + mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20), + 32 << 20); + + /* + * If >= 4GB installed then memory from TOLUD to 4GB + * is remapped above TOM, TOUUD will account for both + */ + if (touud > (1ULL << 32ULL)) { + debug("Available memory above 4GB: %lluM\n", + (touud >> 20) - 4096); + } + + return 0; +} + +static void rcba_config(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P3IP WLAN INTA -> PIRQB + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * TRACKPAD -> PIRQE (Edge Triggered) + * TOUCHSCREEN -> PIRQG (Edge Triggered) + */ + + /* Device interrupt pin register (board specific) */ + writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); + writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); + writel(INTA << D29IP_E1P, RCB_REG(D29IP)); + writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); + writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); + writel(INTA << D26IP_E2P, RCB_REG(D26IP)); + writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); + writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); + + /* Device interrupt route registers */ + writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); + writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); + writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); + writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); + writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); + writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); + writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); + + /* Enable IOAPIC (generic) */ + writew(0x0100, RCB_REG(OIC)); + /* PCH BWG says to read back the IOAPIC enable register */ + (void)readw(RCB_REG(OIC)); + + /* Disable unused devices (board specific) */ + setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); +} + +int dram_init(void) +{ + struct pei_data pei_data __aligned(8) = { + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .ddr3lv_support = 1, + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* + * Empty and onboard Ports 0-7, set to un-used pin + * OC3 + */ + { 0, 3, 0x0000 }, /* P0= Empty */ + { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ + { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ + { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ + { 0, 3, 0x0000 }, /* P4= Empty */ + { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ + { 0, 3, 0x0000 }, /* P6= Empty */ + { 0, 3, 0x0000 }, /* P7= Empty */ + /* + * Empty and onboard Ports 8-13, set to un-used pin + * OC4 + */ + { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ + { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ + { 0, 4, 0x0000 }, /* P10= Empty */ + { 0, 4, 0x0000 }, /* P11= Empty */ + { 0, 4, 0x0000 }, /* P12= Empty */ + { 0, 4, 0x0000 }, /* P13= Empty */ + }, + }; + pci_dev_t dev = PCI_BDF(0, 0, 0); + int ret; + + debug("Boot mode %d\n", gd->arch.pei_boot_mode); + debug("mcr_input %p\n", pei_data.mrc_input); + pei_data.boot_mode = gd->arch.pei_boot_mode; + ret = copy_spd(&pei_data); + if (!ret) + ret = sdram_initialise(&pei_data); + if (ret) + return ret; + + rcba_config(); + quick_ram_check(); + + writew(0xCAFE, MCHBAR_REG(SSKPD)); + + post_code(POST_DRAM); + + ret = sdram_find(dev); + if (ret) + return ret; + + gd->ram_size = gd->arch.meminfo.total_32bit_memory; + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c new file mode 100644 index 0000000000..291c971a2f --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_ehci.c @@ -0,0 +1,29 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +void bd82x6x_usb_ehci_init(pci_dev_t dev) +{ + u32 reg32; + + /* Disable Wake on Disconnect in RMH */ + reg32 = readl(RCB_REG(0x35b0)); + reg32 |= 0x22; + writel(reg32, RCB_REG(0x35b0)); + + debug("EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + /* reg32 |= PCI_COMMAND_SERR; */ + pci_write_config32(dev, PCI_COMMAND, reg32); + + debug("done.\n"); +} diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c new file mode 100644 index 0000000000..4a32a7eb31 --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_xhci.c @@ -0,0 +1,32 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +void bd82x6x_usb_xhci_init(pci_dev_t dev) +{ + u32 reg32; + + debug("XHCI: Setting up controller.. "); + + /* lock overcurrent map */ + reg32 = pci_read_config32(dev, 0x44); + reg32 |= 1; + pci_write_config32(dev, 0x44, reg32); + + /* Enable clock gating */ + reg32 = pci_read_config32(dev, 0x40); + reg32 &= ~((1 << 20) | (1 << 21)); + reg32 |= (1 << 19) | (1 << 18) | (1 << 17); + reg32 |= (1 << 10) | (1 << 9) | (1 << 8); + reg32 |= (1 << 31); /* lock */ + pci_write_config32(dev, 0x40, reg32); + + debug("done.\n"); +} diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c new file mode 100644 index 0000000000..4690603c75 --- /dev/null +++ b/arch/x86/cpu/lapic.c @@ -0,0 +1,57 @@ +/* + * From coreboot file of same name + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +void lapic_setup(void) +{ +#if NEED_LAPIC == 1 + /* Only Pentium Pro and later have those MSR stuff */ + debug("Setting up local apic: "); + + /* Enable the local apic */ + enable_lapic(); + + /* + * Set Task Priority to 'accept all'. + */ + lapic_write_around(LAPIC_TASKPRI, + lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); + + /* Put the local apic in virtual wire mode */ + lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) & + ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE); + lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | + LAPIC_DELIVERY_MODE_MASK)) | + (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | + LAPIC_DELIVERY_MODE_EXTINT)); + lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | + LAPIC_DELIVERY_MODE_MASK)) | + (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | + LAPIC_DELIVERY_MODE_NMI)); + + debug("apic_id: 0x%02lx, ", lapicid()); +#else /* !NEED_LLAPIC */ + /* Only Pentium Pro and later have those MSR stuff */ + debug("Disabling local apic: "); + disable_lapic(); +#endif /* !NEED_LAPIC */ + debug("done.\n"); + post_code(POST_LAPIC); +} diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c new file mode 100644 index 0000000000..5d36b3e020 --- /dev/null +++ b/arch/x86/cpu/mtrr.c @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Memory Type Range Regsters - these are used to tell the CPU whether + * memory is cacheable and if so the cache write mode to use. + * + * These can speed up booting. See the mtrr command. + * + * Reference: Intel Architecture Software Developer's Manual, Volume 3: + * System Programming + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Prepare to adjust MTRRs */ +void mtrr_open(struct mtrr_state *state) +{ + if (!gd->arch.has_mtrr) + return; + + state->enable_cache = dcache_status(); + + if (state->enable_cache) + disable_caches(); + state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR); + wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN); +} + +/* Clean up after adjusting MTRRs, and enable them */ +void mtrr_close(struct mtrr_state *state) +{ + if (!gd->arch.has_mtrr) + return; + + wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN); + if (state->enable_cache) + enable_caches(); +} + +int mtrr_commit(bool do_caches) +{ + struct mtrr_request *req = gd->arch.mtrr_req; + struct mtrr_state state; + uint64_t mask; + int i; + + if (!gd->arch.has_mtrr) + return -ENOSYS; + + mtrr_open(&state); + for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) { + mask = ~(req->size - 1); + mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; + wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type); + wrmsrl(MTRR_PHYS_MASK_MSR(i), mask | MTRR_PHYS_MASK_VALID); + } + + /* Clear the ones that are unused */ + for (; i < MTRR_COUNT; i++) + wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); + mtrr_close(&state); + + return 0; +} + +int mtrr_add_request(int type, uint64_t start, uint64_t size) +{ + struct mtrr_request *req; + uint64_t mask; + + if (!gd->arch.has_mtrr) + return -ENOSYS; + + if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS) + return -ENOSPC; + req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++]; + req->type = type; + req->start = start; + req->size = size; + debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1, + req->type, req->start, req->size); + mask = ~(req->size - 1); + mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; + mask |= MTRR_PHYS_MASK_VALID; + debug(" %016llx %016llx\n", req->start | req->type, mask); + + return 0; +} diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c new file mode 100644 index 0000000000..ab1aaaa059 --- /dev/null +++ b/arch/x86/cpu/pci.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008,2009 + * Graeme Russ, + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct pci_controller x86_hose; + +int pci_early_init_hose(struct pci_controller **hosep) +{ + struct pci_controller *hose; + + hose = calloc(1, sizeof(struct pci_controller)); + if (!hose) + return -ENOMEM; + + board_pci_setup_hose(hose); + pci_setup_type1(hose); + hose->last_busno = pci_hose_scan(hose); + gd->hose = hose; + *hosep = hose; + + return 0; +} + +__weak int board_pci_pre_scan(struct pci_controller *hose) +{ + return 0; +} + +__weak int board_pci_post_scan(struct pci_controller *hose) +{ + return 0; +} + +void pci_init_board(void) +{ + struct pci_controller *hose = &x86_hose; + + /* Stop using the early hose */ + gd->hose = NULL; + + board_pci_setup_hose(hose); + pci_setup_type1(hose); + pci_register_hose(hose); + + board_pci_pre_scan(hose); + hose->last_busno = pci_hose_scan(hose); + board_pci_post_scan(hose); +} + +static struct pci_controller *get_hose(void) +{ + if (gd->hose) + return gd->hose; + + return pci_bus_to_hose(0); +} + +unsigned int pci_read_config8(pci_dev_t dev, unsigned where) +{ + uint8_t value; + + pci_hose_read_config_byte(get_hose(), dev, where, &value); + + return value; +} + +unsigned int pci_read_config16(pci_dev_t dev, unsigned where) +{ + uint16_t value; + + pci_hose_read_config_word(get_hose(), dev, where, &value); + + return value; +} + +unsigned int pci_read_config32(pci_dev_t dev, unsigned where) +{ + uint32_t value; + + pci_hose_read_config_dword(get_hose(), dev, where, &value); + + return value; +} + +void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_byte(get_hose(), dev, where, value); +} + +void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_word(get_hose(), dev, where, value); +} + +void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_dword(get_hose(), dev, where, value); +} diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig new file mode 100644 index 0000000000..f6b52010c3 --- /dev/null +++ b/arch/x86/cpu/queensbay/Kconfig @@ -0,0 +1,79 @@ +# +# Copyright (C) 2014, Bin Meng +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_QUEENSBAY + bool + select HAVE_FSP + select HAVE_CMC + +if INTEL_QUEENSBAY + +config HAVE_FSP + bool "Add an Firmware Support Package binary" + help + Select this option to add an Firmware Support Package binary to + the resulting U-Boot image. It is a binary blob which U-Boot uses + to set up SDRAM and other chipset specific initialization. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config FSP_FILE + string "Firmware Support Package binary filename" + depends on HAVE_FSP + default "fsp.bin" + help + The filename of the file to use as Firmware Support Package binary + in the board directory. + +config FSP_ADDR + hex "Firmware Support Package binary location" + depends on HAVE_FSP + default 0xfffc0000 + help + FSP is not Position Independent Code (PIC) and the whole FSP has to + be rebased if it is placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + + The default base address of 0xfffc0000 indicates that the binary must + be located at offset 0xc0000 from the beginning of a 1MB flash device. + +config FSP_TEMP_RAM_ADDR + hex + default 0x2000000 + help + Stack top address which is used in FspInit after DRAM is ready and + CAR is disabled. + +config HAVE_CMC + bool "Add a Chipset Micro Code state machine binary" + help + Select this option to add a Chipset Micro Code state machine binary + to the resulting U-Boot image. It is a 64K data block of machine + specific code which must be put in the flash for the processor to + access when powered up before system BIOS is executed. + +config CMC_FILE + string "Chipset Micro Code state machine filename" + depends on HAVE_CMC + default "cmc.bin" + help + The filename of the file to use as Chipset Micro Code state machine + binary in the board directory. + +config CMC_ADDR + hex "Chipset Micro Code state machine binary location" + depends on HAVE_CMC + default 0xfffb0000 + help + The location of the CMC binary is determined by a strap. It must be + put in flash at a location matching the strap-determined base address. + + The default base address of 0xfffb0000 indicates that the binary must + be located at offset 0xb0000 from the beginning of a 1MB flash device. + +endif diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile new file mode 100644 index 0000000000..2c2ec01ed2 --- /dev/null +++ b/arch/x86/cpu/queensbay/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2014, Bin Meng +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o +obj-y += fsp_configs.o fsp_support.o +obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c new file mode 100644 index 0000000000..af28e457f6 --- /dev/null +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#include +#include + +void update_fsp_upd(struct upd_region *fsp_upd) +{ + /* Override any UPD setting if required */ + + /* Uncomment the line below to enable DEBUG message */ + /* fsp_upd->serial_dbgport_type = 1; */ + + /* Examples on how to initialize the pointers in UPD region */ + /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */ +} diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c new file mode 100644 index 0000000000..aed3e2b300 --- /dev/null +++ b/arch/x86/cpu/queensbay/fsp_support.c @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#include +#include +#include + +/** + * Compares two GUIDs + * + * If the GUIDs are identical then true is returned. + * If there are any bit differences in the two GUIDs, then false is returned. + * + * @guid1: A pointer to a 128 bit GUID. + * @guid2: A pointer to a 128 bit GUID. + * + * @retval true: guid1 and guid2 are identical. + * @retval false: guid1 and guid2 are not identical. + */ +static bool compare_guid(const struct efi_guid *guid1, + const struct efi_guid *guid2) +{ + if (memcmp(guid1, guid2, sizeof(struct efi_guid)) == 0) + return true; + else + return false; +} + +u32 __attribute__((optimize("O0"))) find_fsp_header(void) +{ + /* + * This function may be called before the a stack is established, + * so special care must be taken. First, it cannot declare any local + * variable using stack. Only register variable can be used here. + * Secondly, some compiler version will add prolog or epilog code + * for the C function. If so the function call may not work before + * stack is ready. + * + * GCC 4.8.1 has been verified to be working for the following codes. + */ + volatile register u8 *fsp asm("eax"); + + /* Initalize the FSP base */ + fsp = (u8 *)CONFIG_FSP_ADDR; + + /* Check the FV signature, _FVH */ + if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) { + /* Go to the end of the FV header and align the address */ + fsp += ((struct fv_header *)fsp)->ext_hdr_off; + fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size; + fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8); + } else { + fsp = 0; + } + + /* Check the FFS GUID */ + if (fsp && + ((struct ffs_file_header *)fsp)->name.data1 == FSP_GUID_DATA1 && + ((struct ffs_file_header *)fsp)->name.data2 == FSP_GUID_DATA2 && + ((struct ffs_file_header *)fsp)->name.data3 == FSP_GUID_DATA3 && + ((struct ffs_file_header *)fsp)->name.data4[0] == FSP_GUID_DATA4_0 && + ((struct ffs_file_header *)fsp)->name.data4[1] == FSP_GUID_DATA4_1 && + ((struct ffs_file_header *)fsp)->name.data4[2] == FSP_GUID_DATA4_2 && + ((struct ffs_file_header *)fsp)->name.data4[3] == FSP_GUID_DATA4_3 && + ((struct ffs_file_header *)fsp)->name.data4[4] == FSP_GUID_DATA4_4 && + ((struct ffs_file_header *)fsp)->name.data4[5] == FSP_GUID_DATA4_5 && + ((struct ffs_file_header *)fsp)->name.data4[6] == FSP_GUID_DATA4_6 && + ((struct ffs_file_header *)fsp)->name.data4[7] == FSP_GUID_DATA4_7) { + /* Add the FFS header size to find the raw section header */ + fsp += sizeof(struct ffs_file_header); + } else { + fsp = 0; + } + + if (fsp && + ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) { + /* Add the raw section header size to find the FSP header */ + fsp += sizeof(struct raw_section); + } else { + fsp = 0; + } + + return (u32)fsp; +} + +void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list) +{ + u32 stack_len; + u32 stack_base; + u32 stack_top; + + post_code(POST_MRC); + + assert(status == 0); + + /* Get the migrated stack in normal memory */ + stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len); + assert(stack_base != 0); + stack_top = stack_base + stack_len - sizeof(u32); + + /* + * Old stack base is stored at the very end of the stack top, + * use it to calculate the migrated shared data base + */ + shared_data = (struct shared_data *)(stack_base + + ((u32)shared_data - *(u32 *)stack_top)); + + /* The boot loader main function entry */ + fsp_init_done(hob_list); +} + +void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) +{ + struct shared_data shared_data; + fsp_init_f init; + struct fsp_init_params params; + struct fspinit_rtbuf rt_buf; + struct vpd_region *fsp_vpd; + struct fsp_header *fsp_hdr; + struct fsp_init_params *params_ptr; + struct upd_region *fsp_upd; + + fsp_hdr = (struct fsp_header *)find_fsp_header(); + if (fsp_hdr == NULL) { + /* No valid FSP info header was found */ + panic("Invalid FSP header"); + } + + fsp_upd = (struct upd_region *)&shared_data.fsp_upd; + memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); + + /* Reserve a gap in stack top */ + rt_buf.common.stack_top = (u32 *)stack_top - 32; + rt_buf.common.boot_mode = boot_mode; + rt_buf.common.upd_data = (struct upd_region *)fsp_upd; + + /* Get VPD region start */ + fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base + + fsp_hdr->cfg_region_off); + + /* Verifify the VPD data region is valid */ + assert((fsp_vpd->img_rev == VPD_IMAGE_REV) && + (fsp_vpd->sign == VPD_IMAGE_ID)); + + /* Copy default data from Flash */ + memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset), + sizeof(struct upd_region)); + + /* Verifify the UPD data region is valid */ + assert(fsp_upd->terminator == UPD_TERMINATOR); + + /* Override any UPD setting if required */ + update_fsp_upd(fsp_upd); + + memset(¶ms, 0, sizeof(struct fsp_init_params)); + params.nvs_buf = nvs_buf; + params.rt_buf = (struct fspinit_rtbuf *)&rt_buf; + params.continuation = (fsp_continuation_f)asm_continuation; + + init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); + params_ptr = ¶ms; + + shared_data.fsp_hdr = fsp_hdr; + shared_data.stack_top = (u32 *)stack_top; + + post_code(POST_PRE_MRC); + + /* + * Use ASM code to ensure the register value in EAX & ECX + * will be passed into BlContinuationFunc + */ + asm volatile ( + "pushl %0;" + "call *%%eax;" + ".global asm_continuation;" + "asm_continuation:;" + "movl %%ebx, %%eax;" /* shared_data */ + "movl 4(%%esp), %%edx;" /* status */ + "movl 8(%%esp), %%ecx;" /* hob_list */ + "jmp fsp_continue;" + : : "m"(params_ptr), "a"(init), "b"(&shared_data) + ); + + /* + * Should never get here. + * Control will continue from fsp_continue. + * This line below is to prevent the compiler from optimizing + * structure intialization. + * + * DO NOT REMOVE! + */ + init(¶ms); +} + +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) +{ + fsp_notify_f notify; + struct fsp_notify_params params; + struct fsp_notify_params *params_ptr; + u32 status; + + if (!fsp_hdr) + fsp_hdr = (struct fsp_header *)find_fsp_header(); + + if (fsp_hdr == NULL) { + /* No valid FSP info header */ + panic("Invalid FSP header"); + } + + notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify); + params.phase = phase; + params_ptr = ¶ms; + + /* + * Use ASM code to ensure correct parameter is on the stack for + * FspNotify as U-Boot is using different ABI from FSP + */ + asm volatile ( + "pushl %1;" /* push notify phase */ + "call *%%eax;" /* call FspNotify */ + "addl $4, %%esp;" /* clean up the stack */ + : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr) + ); + + return status; +} + +u32 fsp_get_usable_lowmem_top(const void *hob_list) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t phys_start; + u32 top; + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* * Collect memory ranges */ + top = FSP_LOWMEM_BASE; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM) { + phys_start = res_desc->phys_start; + /* Need memory above 1MB to be collected here */ + if (phys_start >= FSP_LOWMEM_BASE && + phys_start < (phys_addr_t)FSP_HIGHMEM_BASE) + top += (u32)(res_desc->len); + } + } + hdr = get_next_hob(hdr); + } + + return top; +} + +u64 fsp_get_usable_highmem_top(const void *hob_list) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t phys_start; + u64 top; + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* Collect memory ranges */ + top = FSP_HIGHMEM_BASE; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM) { + phys_start = res_desc->phys_start; + /* Need memory above 1MB to be collected here */ + if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE) + top += (u32)(res_desc->len); + } + } + hdr = get_next_hob(hdr); + } + + return top; +} + +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len, + struct efi_guid *guid) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* Collect memory ranges */ + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_MEM_RESERVED) { + if (compare_guid(&res_desc->owner, guid)) { + if (len) + *len = (u32)(res_desc->len); + + return (u64)(res_desc->phys_start); + } + } + } + hdr = get_next_hob(hdr); + } + + return 0; +} + +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len) +{ + const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + u64 length; + u32 base; + + base = (u32)fsp_get_reserved_mem_from_guid(hob_list, + &length, (struct efi_guid *)&guid); + if ((len != 0) && (base != 0)) + *len = (u32)length; + + return base; +} + +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len) +{ + const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; + u64 length; + u32 base; + + base = (u32)fsp_get_reserved_mem_from_guid(hob_list, + &length, (struct efi_guid *)&guid); + if ((len != 0) && (base != 0)) + *len = (u32)length; + + return base; +} + +const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list) +{ + const struct hob_header *hdr; + + hdr = hob_list; + + /* Parse the HOB list until end of list or matching type is found */ + while (!end_of_hob(hdr)) { + if (hdr->type == type) + return hdr; + + hdr = get_next_hob(hdr); + } + + return NULL; +} + +const struct hob_header *fsp_get_next_guid_hob(const struct efi_guid *guid, + const void *hob_list) +{ + const struct hob_header *hdr; + struct hob_guid *guid_hob; + + hdr = hob_list; + while ((hdr = fsp_get_next_hob(HOB_TYPE_GUID_EXT, + hdr)) != NULL) { + guid_hob = (struct hob_guid *)hdr; + if (compare_guid(guid, &(guid_hob->name))) + break; + hdr = get_next_hob(hdr); + } + + return hdr; +} + +void *fsp_get_guid_hob_data(const void *hob_list, u32 *len, + struct efi_guid *guid) +{ + const struct hob_header *guid_hob; + + guid_hob = fsp_get_next_guid_hob(guid, hob_list); + if (guid_hob == NULL) { + return NULL; + } else { + if (len) + *len = get_guid_hob_data_size(guid_hob); + + return get_guid_hob_data(guid_hob); + } +} + +void *fsp_get_nvs_data(const void *hob_list, u32 *len) +{ + const struct efi_guid guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + + return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid); +} + +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) +{ + const struct efi_guid guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID; + + return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid); +} diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c new file mode 100644 index 0000000000..8637cdca2d --- /dev/null +++ b/arch/x86/cpu/queensbay/tnc.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static void unprotect_spi_flash(void) +{ + u32 bc; + + bc = pci_read_config32(PCH_LPC_DEV, 0xd8); + bc |= 0x1; /* unprotect the flash */ + pci_write_config32(PCH_LPC_DEV, 0xd8, bc); +} + +int arch_cpu_init(void) +{ + struct pci_controller *hose; + int ret; + + post_code(POST_CPU_INIT); +#ifdef CONFIG_SYS_X86_TSC_TIMER + timer_set_base(rdtsc()); +#endif + + ret = x86_cpu_init_f(); + if (ret) + return ret; + + ret = pci_early_init_hose(&hose); + if (ret) + return ret; + + unprotect_spi_flash(); + + return 0; +} + +int print_cpuinfo(void) +{ + post_code(POST_CPU_INFO); + return default_print_cpuinfo(); +} + +void reset_cpu(ulong addr) +{ + /* cold reset */ + outb(0x06, PORT_RESET); +} + +void board_final_cleanup(void) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); + status = fsp_notify(NULL, INIT_PHASE_BOOT); + if (status != FSP_SUCCESS) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return; +} diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S new file mode 100644 index 0000000000..5e09568b85 --- /dev/null +++ b/arch/x86/cpu/queensbay/tnc_car.S @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +.globl car_init +car_init: + /* + * Note: ebp holds the BIST value (built-in self test) so far, but ebp + * will be destroyed through the FSP call, thus we have to test the + * BIST value here before we call into FSP. + */ + test %ebp, %ebp + jz car_init_start + post_code(POST_BIST_FAILURE) + jmp die + +car_init_start: + post_code(POST_CAR_START) + lea find_fsp_header_romstack, %esp + jmp find_fsp_header + +find_fsp_header_ret: + /* EAX points to FSP_INFO_HEADER */ + mov %eax, %ebp + + /* sanity test */ + cmp $CONFIG_FSP_ADDR, %eax + jb die + + /* calculate TempRamInitEntry address */ + mov 0x30(%ebp), %eax + add 0x1c(%ebp), %eax + + /* call FSP TempRamInitEntry to setup temporary stack */ + lea temp_ram_init_romstack, %esp + jmp *%eax + +temp_ram_init_ret: + addl $4, %esp + cmp $0, %eax + jnz car_init_fail + + post_code(POST_CAR_CPU_CACHE) + + /* + * The FSP TempRamInit initializes the ecx and edx registers to + * point to a temporary but writable memory range (Cache-As-RAM). + * ecx: the start of this temporary memory range, + * edx: the end of this range. + */ + + /* stack grows down from top of CAR */ + movl %edx, %esp + + /* + * TODO: + * + * According to FSP architecture spec, the fsp_init() will not return + * to its caller, instead it requires the bootloader to provide a + * so-called continuation function to pass into the FSP as a parameter + * of fsp_init, and fsp_init() will call that continuation function + * directly. + * + * The call to fsp_init() may need to be moved out of the car_init() + * to cpu_init_f() with the help of some inline assembly codes. + * Note there is another issue that fsp_init() will setup another stack + * using the fsp_init parameter stack_top after DRAM is initialized, + * which means any data on the previous stack (on the CAR) gets lost + * (ie: U-Boot global_data). FSP is supposed to support such scenario, + * however it does not work. This should be revisited in the future. + */ + movl $CONFIG_FSP_TEMP_RAM_ADDR, %eax + xorl %edx, %edx + xorl %ecx, %ecx + call fsp_init + +.global fsp_init_done +fsp_init_done: + /* + * We come here from FspInit with eax pointing to the HOB list. + * Save eax to esi temporarily. + */ + movl %eax, %esi + /* + * Re-initialize the ebp (BIST) to zero, as we already reach here + * which means we passed BIST testing before. + */ + xorl %ebp, %ebp + jmp car_init_ret + +car_init_fail: + post_code(POST_CAR_FAILURE) + +die: + hlt + jmp die + hlt + + /* + * The function call before CAR initialization is tricky. It cannot + * be called using the 'call' instruction but only the 'jmp' with + * the help of a handcrafted stack in the ROM. The stack needs to + * contain the function return address as well as the parameters. + */ + .balign 4 +find_fsp_header_romstack: + .long find_fsp_header_ret + + .balign 4 +temp_ram_init_romstack: + .long temp_ram_init_ret + .long temp_ram_init_params +temp_ram_init_params: +_dt_ucode_base_size: + /* These next two fields are filled in by ifdtool */ + .long 0 /* microcode base */ + .long 0 /* microcode size */ + .long CONFIG_SYS_MONITOR_BASE /* code region base */ + .long CONFIG_SYS_MONITOR_LEN /* code region size */ diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c new file mode 100644 index 0000000000..df79a39dd8 --- /dev/null +++ b/arch/x86/cpu/queensbay/tnc_dram.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + phys_size_t ram_size = 0; + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + hdr = gd->arch.hob_list; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM || + res_desc->type == RES_MEM_RESERVED) { + ram_size += res_desc->len; + } + } + hdr = get_next_hob(hdr); + } + + gd->ram_size = ram_size; + post_code(POST_DRAM); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. + * It overrides the default implementation found elsewhere which simply + * picks the end of ram, wherever that may be. The location of the stack, + * the relocation address, and how far U-Boot is moved by relocation are + * set in the global data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + return fsp_get_usable_lowmem_top(gd->arch.hob_list); +} + +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + unsigned num_entries = 0; + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + hdr = gd->arch.hob_list; + + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + entries[num_entries].addr = res_desc->phys_start; + entries[num_entries].size = res_desc->len; + + if (res_desc->type == RES_SYS_MEM) + entries[num_entries].type = E820_RAM; + else if (res_desc->type == RES_MEM_RESERVED) + entries[num_entries].type = E820_RESERVED; + } + hdr = get_next_hob(hdr); + num_entries++; + } + + return num_entries; +} diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c new file mode 100644 index 0000000000..39bff49c8d --- /dev/null +++ b/arch/x86/cpu/queensbay/tnc_pci.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + pci_set_region(hose->regions + 3, + 0, + 0, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; +} + +int board_pci_post_scan(struct pci_controller *hose) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); + status = fsp_notify(NULL, INIT_PHASE_PCI); + if (status != FSP_SUCCESS) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return 0; +} diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c new file mode 100644 index 0000000000..b01422a965 --- /dev/null +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, + { } +}; + +int cpu_mmc_init(bd_t *bis) +{ + struct sdhci_host *mmc_host; + pci_dev_t devbusfn; + u32 iobase; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) { + devbusfn = pci_find_devices(mmc_supported, i); + if (devbusfn == -1) + return -ENODEV; + + mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + if (!mmc_host) + return -ENOMEM; + + mmc_host->name = "Topcliff SDHCI"; + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + mmc_host->ioaddr = (void *)iobase; + mmc_host->quirks = 0; + ret = add_sdhci(mmc_host, 0, 0); + if (ret) + return ret; + } + + return 0; +} diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 329bb3ab35..f51f1121d0 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -1,5 +1,5 @@ /* - * U-boot - x86 Startup Code + * U-Boot - x86 Startup Code * * (C) Copyright 2008-2011 * Graeme Russ, @@ -13,9 +13,11 @@ #include #include #include +#include #include #include #include +#include .section .text .code32 @@ -49,6 +51,8 @@ _start: */ movw $GD_FLG_COLD_BOOT, %bx 1: + /* Save BIST */ + movl %eax, %ebp /* Load the segement registes to match the gdt loaded in start16.S */ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax @@ -65,27 +69,61 @@ _start: jmp early_board_init .globl early_board_init_ret early_board_init_ret: + post_code(POST_START) /* Initialise Cache-As-RAM */ jmp car_init .globl car_init_ret car_init_ret: +#ifndef CONFIG_HAVE_FSP /* * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, * or fully initialised SDRAM - we really don't care which) * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack + * and early malloc area. The MRC requires some space at the top. + * + * Stack grows down from top of CAR. We have: + * + * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE + * MRC area + * global_data + * x86 global descriptor table + * early malloc area + * stack + * bottom-> CONFIG_SYS_CAR_ADDR */ - - /* Stack grows down from top of CAR */ - movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE), %esp + movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp +#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE + subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp +#endif +#else + /* + * When we get here after car_init, esp points to a temporary stack + * and esi holds the HOB list address returned by the FSP. + */ +#endif /* Reserve space on stack for global data */ subl $GENERATED_GBL_DATA_SIZE, %esp /* Align global data to 16-byte boundary */ andl $0xfffffff0, %esp + post_code(POST_START_STACK) - /* Setup first parameter to setup_gdt */ + /* Zero the global data since it won't happen later */ + xorl %eax, %eax + movl $GENERATED_GBL_DATA_SIZE, %ecx + movl %esp, %edi + rep stosb + +#ifdef CONFIG_HAVE_FSP + /* Store HOB list */ + movl %esp, %edx + addl $GD_HOB_LIST, %edx + movl %esi, (%edx) +#endif + + /* Setup first parameter to setup_gdt, pointer to global_data */ movl %esp, %eax /* Reserve space for global descriptor table */ @@ -93,16 +131,28 @@ car_init_ret: /* Align temporary global descriptor table to 16-byte boundary */ andl $0xfffffff0, %esp + movl %esp, %ecx + +#if defined(CONFIG_SYS_MALLOC_F_LEN) + subl $CONFIG_SYS_MALLOC_F_LEN, %esp + movl %eax, %edx + addl $GD_MALLOC_BASE, %edx + movl %esp, (%edx) +#endif + /* Store BIST */ + movl %eax, %edx + addl $GD_BIST, %edx + movl %ebp, (%edx) /* Set second parameter to setup_gdt */ - movl %esp, %edx + movl %ecx, %edx /* Setup global descriptor table so gd->xyz works */ call setup_gdt /* Set parameter to board_init_f() to boot flags */ + post_code(POST_START_DONE) xorl %eax, %eax - movw %bx, %ax /* Enter, U-boot! */ call board_init_f @@ -155,6 +205,14 @@ board_init_f_r_trampoline: /* Setup global descriptor table so gd->xyz works */ call setup_gdt + /* Set if we need to disable CAR */ +.weak car_uninit + movl $car_uninit, %eax + cmpl $0, %eax + jz 1f + + call car_uninit +1: /* Re-enter U-Boot by calling board_init_f_r */ call board_init_f_r diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 8b9b327cd4..826e2b4361 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -1,5 +1,5 @@ /* - * U-boot - x86 Startup Code + * U-Boot - x86 Startup Code * * (C) Copyright 2008-2011 * Graeme Russ, @@ -21,18 +21,16 @@ .code16 .globl start16 start16: + /* Save BIST */ + movl %eax, %ecx + /* Set the Cold Boot / Hard Reset flag */ movl $GD_FLG_COLD_BOOT, %ebx - /* - * First we let the BSP do some early initialization - * this code have to map the flash to its final position - */ - jmp board_init16 -.globl board_init16_ret -board_init16_ret: + xorl %eax, %eax + movl %eax, %cr3 /* Invalidate TLB */ - /* Turn of cache (this might require a 486-class CPU) */ + /* Turn off cache (this might require a 486-class CPU) */ movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 @@ -50,9 +48,11 @@ o32 cs lgdt gdt_ptr /* Flush the prefetch queue */ jmp ff ff: - /* Finally jump to the 32bit initialization code */ + + /* Finally restore BIST and jump to the 32-bit initialization code */ movw $code32start, %ax movw %ax, %bp + movl %ecx, %eax o32 cs ljmp *(%bp) /* 48-bit far pointer */ @@ -64,17 +64,17 @@ idt_ptr: .word 0 /* limit */ .long 0 /* base */ -/* - * The following Global Descriptor Table is just enough to get us into - * 'Flat Protected Mode' - It will be discarded as soon as the final - * GDT is setup in a safe location in RAM - */ + /* + * The following Global Descriptor Table is just enough to get us into + * 'Flat Protected Mode' - It will be discarded as soon as the final + * GDT is setup in a safe location in RAM + */ gdt_ptr: - .word 0x20 /* limit (32 bytes = 4 GDT entries) */ + .word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */ .long BOOT_SEG + gdt /* base */ -/* Some CPUs are picky about GDT alignment... */ -.align 16 + /* Some CPUs are picky about GDT alignment... */ + .align 16 gdt: /* * The GDT table ... diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c new file mode 100644 index 0000000000..254d0de0e4 --- /dev/null +++ b/arch/x86/cpu/turbo.c @@ -0,0 +1,98 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2011 The Chromium Authors. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED +static inline int get_global_turbo_state(void) +{ + return TURBO_UNKNOWN; +} + +static inline void set_global_turbo_state(int state) +{ +} +#else +static int g_turbo_state = TURBO_UNKNOWN; + +static inline int get_global_turbo_state(void) +{ + return g_turbo_state; +} + +static inline void set_global_turbo_state(int state) +{ + g_turbo_state = state; +} +#endif + +static const char *const turbo_state_desc[] = { + [TURBO_UNKNOWN] = "unknown", + [TURBO_UNAVAILABLE] = "unavailable", + [TURBO_DISABLED] = "available but hidden", + [TURBO_ENABLED] = "available and visible" +}; + +/* + * Determine the current state of Turbo and cache it for later. + * Turbo is a package level config so it does not need to be + * enabled on every core. + */ +int turbo_get_state(void) +{ + struct cpuid_result cpuid_regs; + int turbo_en, turbo_cap; + msr_t msr; + int turbo_state = get_global_turbo_state(); + + /* Return cached state if available */ + if (turbo_state != TURBO_UNKNOWN) + return turbo_state; + + cpuid_regs = cpuid(CPUID_LEAF_PM); + turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); + + msr = msr_read(MSR_IA32_MISC_ENABLES); + turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); + + if (!turbo_cap && turbo_en) { + /* Unavailable */ + turbo_state = TURBO_UNAVAILABLE; + } else if (!turbo_cap && !turbo_en) { + /* Available but disabled */ + turbo_state = TURBO_DISABLED; + } else if (turbo_cap && turbo_en) { + /* Available */ + turbo_state = TURBO_ENABLED; + } + + set_global_turbo_state(turbo_state); + debug("Turbo is %s\n", turbo_state_desc[turbo_state]); + return turbo_state; +} + +void turbo_enable(void) +{ + msr_t msr; + + /* Only possible if turbo is available but hidden */ + if (turbo_get_state() == TURBO_DISABLED) { + /* Clear Turbo Disable bit in Misc Enables */ + msr = msr_read(MSR_IA32_MISC_ENABLES); + msr.hi &= ~H_MISC_DISABLE_TURBO; + msr_write(MSR_IA32_MISC_ENABLES, msr); + + /* Update cached turbo state */ + set_global_turbo_state(TURBO_ENABLED); + debug("Turbo has been enabled\n"); + } +} diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index f48bff54e1..b0d8531a60 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -44,7 +44,9 @@ SECTIONS . = ALIGN(4); __rel_dyn_start = .; - .rel.dyn : { *(.rel.dyn) } + .rel.dyn : { + *(.rel*) + } __rel_dyn_end = .; . = ALIGN(4); _end = .; @@ -64,15 +66,19 @@ SECTIONS /DISCARD/ : { *(.gnu*) } #ifdef CONFIG_X86_RESET_VECTOR - /* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM */ - . = START_16; - .start16 : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); } + . = START_16 - RESET_SEG_START; + .start16 : AT (START_16) { + KEEP(*(.start16)); + } - . = RESET_VEC_LOC; - .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); } + . = RESET_VEC_LOC - RESET_SEG_START; + .resetvec : AT (RESET_VEC_LOC) { + KEEP(*(.resetvec)); + } #endif + } diff --git a/arch/x86/dts/.gitignore b/arch/x86/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/x86/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile new file mode 100644 index 0000000000..97ed884288 --- /dev/null +++ b/arch/x86/dts/Makefile @@ -0,0 +1,12 @@ +dtb-y += chromebook_link.dtb \ + crownbay.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts new file mode 100644 index 0000000000..45ada610b3 --- /dev/null +++ b/arch/x86/dts/chromebook_link.dts @@ -0,0 +1,229 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" + +/ { + model = "Google Link"; + compatible = "google,link", "intel,celeron-ivybridge"; + + aliases { + spi0 = "/spi"; + }; + + config { + silent_console = <0>; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + + chosen { + stdout-path = "/serial"; + }; + + spd { + compatible = "memory-spd"; + #address-cells = <1>; + #size-cells = <0>; + elpida_4Gb_1600_x16 { + reg = <0>; + data = [92 10 0b 03 04 19 02 02 + 03 52 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + 20 08 3c 3c 01 40 83 81 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 11 42 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 02 fe 00 + 11 52 00 00 00 07 7f 37 + 45 42 4a 32 30 55 47 36 + 45 42 55 30 2d 47 4e 2d + 46 20 30 20 02 fe 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00]; + }; + samsung_4Gb_1600_1.35v_x16 { + reg = <1>; + data = [92 11 0b 03 04 19 02 02 + 03 11 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + f0 0a 3c 3c 01 40 83 01 + 00 80 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 11 02 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 80 ce 01 + 00 00 00 00 00 00 6a 04 + 4d 34 37 31 42 35 36 37 + 34 42 48 30 2d 59 4b 30 + 20 20 00 00 80 ce 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00]; + }; + micron_4Gb_1600_1.35v_x16 { + reg = <2>; + data = [92 11 0b 03 04 19 02 02 + 03 11 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + 20 08 3c 3c 01 40 83 05 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 01 02 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 80 2c 00 + 00 00 00 00 00 00 ad 75 + 34 4b 54 46 32 35 36 36 + 34 48 5a 2d 31 47 36 45 + 31 20 45 31 80 2c 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff]; + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + /* Alignment: 4k (for updating) */ + reg = <0x003e0000 0x00010000>; + type = "wiped"; + wipe-value = [ff]; + }; + }; + }; + + pci { + sata { + compatible = "intel,pantherpoint-ahci"; + intel,sata-mode = "ahci"; + intel,sata-port-map = <1>; + intel,sata-port0-gen3-tx = <0x00880a7f>; + }; + + gma { + compatible = "intel,gma"; + intel,dp_hotplug = <0 0 0x06>; + intel,panel-port-select = <1>; + intel,panel-power-cycle-delay = <6>; + intel,panel-power-up-delay = <2000>; + intel,panel-power-down-delay = <500>; + intel,panel-power-backlight-on-delay = <2000>; + intel,panel-power-backlight-off-delay = <2000>; + intel,cpu-backlight = <0x00000200>; + intel,pch-backlight = <0x04000000>; + }; + + lpc { + compatible = "intel,lpc"; + #address-cells = <1>; + #size-cells = <1>; + gen-dec = <0x800 0xfc 0x900 0xfc>; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; + intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b + 0x80 0x80 0x80 0x80>; + intel,gpi-routing = <0 0 0 0 0 0 0 2 + 1 0 0 0 0 0 0 0>; + /* Enable EC SMI source */ + intel,alt-gp-smi-enable = <0x0100>; + + cros-ec@200 { + compatible = "google,cros-ec"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* Describes the flash memory within the EC */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; + }; + }; + }; + + microcode { + update@0 { +#include "microcode/m12306a9_0000001b.dtsi" + }; + }; + +}; diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi deleted file mode 100644 index 4862a59704..0000000000 --- a/arch/x86/dts/coreboot.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/include/ "skeleton.dtsi" - -/ { - aliases { - console = "/serial"; - }; - - serial { - compatible = "ns16550"; - reg-shift = <1>; - io-mapped = <1>; - multiplier = <1>; - baudrate = <115200>; - status = "disabled"; - }; -}; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts new file mode 100644 index 0000000000..e81054ebc5 --- /dev/null +++ b/arch/x86/dts/crownbay.dts @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" + +/ { + model = "Intel Crown Bay"; + compatible = "intel,crownbay", "intel,queensbay"; + + config { + silent_console = <0>; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + chosen { + /* + * By default the legacy superio serial port is used as the + * U-Boot serial console. If we want to use UART from Topcliff + * PCH as the console, change this property to &pciuart#. + * + * For example, stdout-path = &pciuart0 will use the first + * UART on Topcliff PCH. + */ + stdout-path = "/serial"; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich7"; + spi-flash@0 { + reg = <0>; + compatible = "sst,25vf016b", "spi-flash"; + memory-map = <0xffe00000 0x00200000>; + }; + }; + + microcode { + update@0 { +#include "microcode/m0220661105_cv.dtsi" + }; + }; + + pci { + #address-cells = <3>; + #size-cells = <2>; + compatible = "intel,pci"; + device_type = "pci"; + + pcie@17,0 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "intel,pci"; + device_type = "pci"; + + topcliff@0,0 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "intel,pci"; + device_type = "pci"; + + pciuart0: uart@a,1 { + compatible = "pci8086,8811.00", + "pci8086,8811", + "pciclass,070002", + "pciclass,0700", + "x86-uart"; + reg = <0x00025100 0x0 0x0 0x0 0x0 + 0x01025110 0x0 0x0 0x0 0x0>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pciuart1: uart@a,2 { + compatible = "pci8086,8812.00", + "pci8086,8812", + "pciclass,070002", + "pciclass,0700", + "x86-uart"; + reg = <0x00025200 0x0 0x0 0x0 0x0 + 0x01025210 0x0 0x0 0x0 0x0>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pciuart2: uart@a,3 { + compatible = "pci8086,8813.00", + "pci8086,8813", + "pciclass,070002", + "pciclass,0700", + "x86-uart"; + reg = <0x00025300 0x0 0x0 0x0 0x0 + 0x01025310 0x0 0x0 0x0 0x0>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pciuart3: uart@a,4 { + compatible = "pci8086,8814.00", + "pci8086,8814", + "pciclass,070002", + "pciclass,0700", + "x86-uart"; + reg = <0x00025400 0x0 0x0 0x0 0x0 + 0x01025410 0x0 0x0 0x0 0x0>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + }; + }; + }; + +}; diff --git a/arch/x86/dts/include/dt-bindings b/arch/x86/dts/include/dt-bindings new file mode 120000 index 0000000000..0cecb3d080 --- /dev/null +++ b/arch/x86/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings \ No newline at end of file diff --git a/arch/x86/dts/microcode/m0220661105_cv.dtsi b/arch/x86/dts/microcode/m0220661105_cv.dtsi new file mode 100644 index 0000000000..ada8bfcdf9 --- /dev/null +++ b/arch/x86/dts/microcode/m0220661105_cv.dtsi @@ -0,0 +1,368 @@ +/* + * Copyright (c) <1995-2014>, Intel Corporation. + * All rights reserved. + * Redistribution. Redistribution and use in binary form, without modification, are + * permitted provided that the following conditions are met: + * .Redistributions must reproduce the above copyright notice and the following + * disclaimer in the documentation and/or other materials provided with the + * distribution. + * .Neither the name of Intel Corporation nor the names of its suppliers may be used + * to endorse or promote products derived from this software without specific prior + * written permission. + * .No reverse engineering, decompilation, or disassembly of this software is + * permitted. + * ."Binary form" includes any format commonly used for electronic conveyance + * which is a reversible, bit-exact translation of binary representation to ASCII or + * ISO text, for example, "uuencode." + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: Sat Sep 13 22:51:38 CST 2014 + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x105>; +intel,date-code = <0x7182011>; +intel,processor-signature = <0x20661>; +intel,checksum = <0x52558795>; +intel,loader-revision = <1>; +intel,processor-flags = <0x2>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x05010000 0x11201807 0x61060200 + 0x95875552 0x01000000 0x02000000 0xd0130000 + 0x00140000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x05010000 + 0x19000000 0x00010500 0x15071120 0x01040000 + 0x01000000 0x61060200 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x9557a557 0x7d7a0fe3 0x8e2fbe53 0x0db9e346 + 0xd35c00d6 0x21bb34b7 0x662b6406 0xa0425035 + 0x3d028208 0xcb843695 0xee06be0a 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0x3ba56bb3 0x1c343938 0xabc0df54 + 0x8ba4f1e8 0xfbd4c592 0xb678c884 0xff3be2f1 + 0xca013570 0xfb0598df 0x3cb9cc1d 0xe3ba8ca3 + 0xc3d7ecee 0x0ae84a0b 0x0d70f0c3 0x963110ff + >; diff --git a/arch/x86/dts/microcode/m12206a7_00000029.dtsi b/arch/x86/dts/microcode/m12206a7_00000029.dtsi new file mode 100644 index 0000000000..fe888bfa41 --- /dev/null +++ b/arch/x86/dts/microcode/m12206a7_00000029.dtsi @@ -0,0 +1,686 @@ +/* + * Copyright (c) <1995-2014>, Intel Corporation. + * All rights reserved. + * Redistribution. Redistribution and use in binary form, without modification, are + * permitted provided that the following conditions are met: + * .Redistributions must reproduce the above copyright notice and the following + * disclaimer in the documentation and/or other materials provided with the + * distribution. + * .Neither the name of Intel Corporation nor the names of its suppliers may be used + * to endorse or promote products derived from this software without specific prior + * written permission. + * .No reverse engineering, decompilation, or disassembly of this software is + * permitted. + * ."Binary form" includes any format commonly used for electronic conveyance + * which is a reversible, bit-exact translation of binary representation to ASCII or + * ISO text, for example, "uuencode." + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x29>; +intel,date-code = <0x6122013>; +intel,processor-signature = <0x206a7>; +intel,checksum = <0xc9c91df0>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x29000000 0x13201206 0xa7060200 + 0xf01dc9c9 0x01000000 0x12000000 0xd0270000 + 0x00280000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x29000000 + 0x00000000 0x00000000 0x11061320 0xd1090000 + 0x01000000 0xa7060200 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xd1090000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0xfd2a2f68 0x82ac7ebb 0xa4916328 0x7480b81b + 0xd329a777 0x25750339 0x9a8f7a9b 0xf1da9cb8 + 0xb1be7b1a 0x621d5a35 0x94b57e2e 0xa9def809 + 0xe4492a43 0x530252bf 0x1040fada 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--- /dev/null +++ b/arch/x86/dts/microcode/m12306a9_0000001b.dtsi @@ -0,0 +1,814 @@ +/* + * Copyright (c) <1995-2014>, Intel Corporation. + * All rights reserved. + * Redistribution. Redistribution and use in binary form, without modification, are + * permitted provided that the following conditions are met: + * .Redistributions must reproduce the above copyright notice and the following + * disclaimer in the documentation and/or other materials provided with the + * distribution. + * .Neither the name of Intel Corporation nor the names of its suppliers may be used + * to endorse or promote products derived from this software without specific prior + * written permission. + * .No reverse engineering, decompilation, or disassembly of this software is + * permitted. + * ."Binary form" includes any format commonly used for electronic conveyance + * which is a reversible, bit-exact translation of binary representation to ASCII or + * ISO text, for example, "uuencode." + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x1b>; +intel,date-code = <0x5292014>; +intel,processor-signature = <0x306a9>; +intel,checksum = <0x579ae07a>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x1b000000 0x14202905 0xa9060300 + 0x7ae09a57 0x01000000 0x12000000 0xd02f0000 + 0x00300000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x1b000000 + 0x00000000 0x00000000 0x16051420 0x610b0000 + 0x01000000 0xa9060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0xc2b13ad8 0x6ce74fea 0xd364ad12 0xf6404a69 + 0xc89041e4 0x217fa2f6 0x6ff6e43f 0x79cde4eb + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6 + 0x5fb36178 0xbc17d76b 0x31b7b923 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0x66ed6178 0x26be9f81 0xeac41ee5 + 0xbe5e2e6b 0x177f9068 0xede56c48 0x438b3811 + 0xd5bd7ee4 0xc027d1a8 0xc1c0f725 0x48d4d4eb + 0x6ffa28d5 0xbd6ac9eb 0xd497781d 0x24d3a154 + 0x409bb5c0 0x8079bf76 0x90a522dc 0x19bf7033 + 0x1a529b6e 0xe5207e4d 0x3d49b7bc 0x3eca6d54 + 0xa37681a6 0xaa9a62e4 0xe54aa1e1 0xb91e7157 + 0x8cce8f65 0xbcbbd62c 0x7fa477b5 0x44f46b50 + 0x54263fcf 0x529cbb5d 0x8923e390 0x0778d6d7 + 0x0cc0503f 0x02c374ce 0xb89c3e5c 0x25b1b353 + 0xb227cb2d 0x44108698 0x5e5968c2 0x82c48632 + 0x0b8f4209 0x1a241879 0x9edca6f1 0xa1fa51ab + 0x206db0c6 0xbfbbbe98 0xa71c91f6 0xa1b28056 + 0xb8bfaaa9 0xa5914f75 0x77d26574 0xacfd459d + 0x77f7cab2 0x249ebf26 0xef902bdd 0x77f6e48d + 0x82497035 0x93333a9d 0x34ea9953 0x8f08d41c + >; diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi new file mode 100644 index 0000000000..9b097f4f9b --- /dev/null +++ b/arch/x86/dts/serial.dtsi @@ -0,0 +1,9 @@ +/ { + serial { + compatible = "x86-uart"; + reg = <0x3f8 8>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; +}; diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h new file mode 100644 index 0000000000..4872b92860 --- /dev/null +++ b/arch/x86/include/asm/acpi.h @@ -0,0 +1,24 @@ +/* + * From coreboot + * + * Copyright (C) 2004 SUSE LINUX AG + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2008-2009 coresystems GmbH + * (Written by Stefan Reinauer ) + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ACPI_H +#define __ASM_ACPI_H + +#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ +#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */ +#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */ +#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */ + +/* 0 = S0, 1 = S1 ...*/ +int acpi_get_slp_type(void); +void apci_set_slp_type(int type); + +#endif diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h new file mode 100644 index 0000000000..31edef9623 --- /dev/null +++ b/arch/x86/include/asm/arch-coreboot/gpio.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2014, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x48 + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-coreboot/ipchecksum.h b/arch/x86/include/asm/arch-coreboot/ipchecksum.h deleted file mode 100644 index 1d73b4d912..0000000000 --- a/arch/x86/include/asm/arch-coreboot/ipchecksum.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * It has originally been taken from the FreeBSD project. - * - * Copyright (c) 2001 Charles Mott - * Copyright (c) 2008 coresystems GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _COREBOOT_IPCHECKSUM_H -#define _COREBOOT_IPCHECKSUM_H - -unsigned short ipchksum(const void *vptr, unsigned long nbytes); - -#endif diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h index 78d3a9d49e..832c50aa63 100644 --- a/arch/x86/include/asm/arch-coreboot/sysinfo.h +++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h @@ -3,35 +3,14 @@ * * Copyright (C) 2008 Advanced Micro Devices, Inc. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _COREBOOT_SYSINFO_H #define _COREBOOT_SYSINFO_H #include -#include +#include #include #include diff --git a/arch/x86/include/asm/arch-coreboot/tables.h b/arch/x86/include/asm/arch-coreboot/tables.h index ad34a8b0f1..e254484e75 100644 --- a/arch/x86/include/asm/arch-coreboot/tables.h +++ b/arch/x86/include/asm/arch-coreboot/tables.h @@ -3,34 +3,13 @@ * * Copyright (C) 2008 Advanced Micro Devices, Inc. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _COREBOOT_TABLES_H #define _COREBOOT_TABLES_H -#include +#include struct cbuint64 { u32 lo; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h new file mode 100644 index 0000000000..e1d9a9b7b2 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_BD82X6X_H +#define _ASM_ARCH_BD82X6X_H + +void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); +void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); +void bd82x6x_pci_init(pci_dev_t dev); +void bd82x6x_usb_ehci_init(pci_dev_t dev); +void bd82x6x_usb_xhci_init(pci_dev_t dev); +int bd82x6x_init_pci_devices(void); +int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, + const void *blob, int node); +int bd82x6x_init(void); + +struct x86_cpu_priv; +int model_206ax_init(struct x86_cpu_priv *cpu); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h new file mode 100644 index 0000000000..31edef9623 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/gpio.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2014, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x48 + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h new file mode 100644 index 0000000000..3a0809d6ec --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/me.h @@ -0,0 +1,356 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/me.h + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_INTEL_ME_H +#define _ASM_INTEL_ME_H + +#include +#include + +#define ME_RETRY 100000 /* 1 second */ +#define ME_DELAY 10 /* 10 us */ + +/* + * Management Engine PCI registers + */ + +#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ +#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ + +#define PCI_ME_HFS 0x40 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 + +struct me_hfs { + u32 working_state:4; + u32 mfg_mode:1; + u32 fpt_bad:1; + u32 operation_state:3; + u32 fw_init_complete:1; + u32 ft_bup_ld_flr:1; + u32 update_in_progress:1; + u32 error_code:4; + u32 operation_mode:4; + u32 reserved:4; + u32 boot_options_present:1; + u32 ack_data:3; + u32 bios_msg_ack:4; +} __packed; + +#define PCI_ME_UMA 0x44 + +struct me_uma { + u32 size:6; + u32 reserved_1:10; + u32 valid:1; + u32 reserved_0:14; + u32 set_to_one:1; +} __packed; + +#define PCI_ME_H_GS 0x4c +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 + +struct me_did { + u32 uma_base:16; + u32 reserved:8; + u32 status:4; + u32 init_done:4; +} __packed; + +#define PCI_ME_GMES 0x48 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 + +struct me_gmes { + u32 bist_in_prog:1; + u32 icc_prog_sts:2; + u32 invoke_mebx:1; + u32 cpu_replaced_sts:1; + u32 mbp_rdy:1; + u32 mfs_failure:1; + u32 warm_rst_req_for_df:1; + u32 cpu_replaced_valid:1; + u32 reserved_1:2; + u32 fw_upd_ipu:1; + u32 reserved_2:4; + u32 current_state:8; + u32 current_pmevent:4; + u32 progress_code:4; +} __packed; + +#define PCI_ME_HERES 0xbc +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_HER(x) (0xc0+(4*(x))) + +struct me_heres { + u32 extend_reg_algorithm:4; + u32 reserved:26; + u32 extend_feature_present:1; + u32 extend_reg_valid:1; +} __packed; + +/* + * Management Engine MEI registers + */ + +#define MEI_H_CB_WW 0x00 +#define MEI_H_CSR 0x04 +#define MEI_ME_CB_RW 0x08 +#define MEI_ME_CSR_HA 0x0c + +struct mei_csr { + u32 interrupt_enable:1; + u32 interrupt_status:1; + u32 interrupt_generate:1; + u32 ready:1; + u32 reset:1; + u32 reserved:3; + u32 buffer_read_ptr:8; + u32 buffer_write_ptr:8; + u32 buffer_depth:8; +} __packed; + +#define MEI_ADDRESS_CORE 0x01 +#define MEI_ADDRESS_AMT 0x02 +#define MEI_ADDRESS_RESERVED 0x03 +#define MEI_ADDRESS_WDT 0x04 +#define MEI_ADDRESS_MKHI 0x07 +#define MEI_ADDRESS_ICC 0x08 +#define MEI_ADDRESS_THERMAL 0x09 + +#define MEI_HOST_ADDRESS 0 + +struct mei_header { + u32 client_address:8; + u32 host_address:8; + u32 length:9; + u32 reserved:6; + u32 is_complete:1; +} __packed; + +#define MKHI_GROUP_ID_CBM 0x00 +#define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_GROUP_ID_MDES 0x08 +#define MKHI_GROUP_ID_GEN 0xff + +#define MKHI_GLOBAL_RESET 0x0b + +#define MKHI_FWCAPS_GET_RULE 0x02 + +#define MKHI_MDES_ENABLE 0x09 + +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_END_OF_POST 0x0c +#define MKHI_FEATURE_OVERRIDE 0x14 + +struct mkhi_header { + u32 group_id:8; + u32 command:7; + u32 is_response:1; + u32 reserved:8; + u32 result:8; +} __packed; + +struct me_fw_version { + u16 code_minor; + u16 code_major; + u16 code_build_number; + u16 code_hot_fix; + u16 recovery_minor; + u16 recovery_major; + u16 recovery_build_number; + u16 recovery_hot_fix; +} __packed; + + +#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 + +#define CBM_RR_GLOBAL_RESET 0x01 + +#define GLOBAL_RESET_BIOS_MRC 0x01 +#define GLOBAL_RESET_BIOS_POST 0x02 +#define GLOBAL_RESET_MEBX 0x03 + +struct me_global_reset { + u8 request_origin; + u8 reset_type; +} __packed; + +enum me_bios_path { + ME_NORMAL_BIOS_PATH, + ME_S3WAKE_BIOS_PATH, + ME_ERROR_BIOS_PATH, + ME_RECOVERY_BIOS_PATH, + ME_DISABLE_BIOS_PATH, + ME_FIRMWARE_UPDATE_BIOS_PATH, +}; + +struct __packed mbp_fw_version_name { + u32 major_version:16; + u32 minor_version:16; + u32 hotfix_version:16; + u32 build_version:16; +}; + +struct __packed mbp_icc_profile { + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 register_lock_mask[3]; +}; + +struct __packed mefwcaps_sku { + u32 full_net:1; + u32 std_net:1; + u32 manageability:1; + u32 small_business:1; + u32 l3manageability:1; + u32 intel_at:1; + u32 intel_cls:1; + u32 reserved:3; + u32 intel_mpc:1; + u32 icc_over_clocking:1; + u32 pavp:1; + u32 reserved_1:4; + u32 ipv6:1; + u32 kvm:1; + u32 och:1; + u32 vlan:1; + u32 tls:1; + u32 reserved_4:1; + u32 wlan:1; + u32 reserved_5:8; +}; + +struct __packed tdt_state_flag { + u16 lock_state:1; + u16 authenticate_module:1; + u16 s3authentication:1; + u16 flash_wear_out:1; + u16 flash_variable_security:1; + u16 wwan3gpresent:1; + u16 wwan3goob:1; + u16 reserved:9; +}; + +struct __packed tdt_state_info { + u8 state; + u8 last_theft_trigger; + struct tdt_state_flag flags; +}; + +struct __packed platform_type_rule_data { + u32 platform_target_usage_type:4; + u32 platform_target_market_type:2; + u32 super_sku:1; + u32 reserved:1; + u32 intel_me_fw_image_type:4; + u32 platform_brand:4; + u32 reserved_1:16; +}; + +struct __packed mbp_fw_caps { + struct mefwcaps_sku fw_capabilities; + u8 available; +}; + +struct __packed mbp_rom_bist_data { + u16 device_id; + u16 fuse_test_flags; + u32 umchid[4]; +}; + +struct __packed mbp_platform_key { + u32 key[8]; +}; + +struct __packed mbp_plat_type { + struct platform_type_rule_data rule_data; + u8 available; +}; + +struct __packed me_bios_payload { + struct mbp_fw_version_name fw_version_name; + struct mbp_fw_caps fw_caps_sku; + struct mbp_rom_bist_data rom_bist_data; + struct mbp_platform_key platform_key; + struct mbp_plat_type fw_plat_type; + struct mbp_icc_profile icc_profile; + struct tdt_state_info at_state; + u32 mfsintegrity; +}; + +struct __packed mbp_header { + u32 mbp_size:8; + u32 num_entries:8; + u32 rsvd:16; +}; + +struct __packed mbp_item_header { + u32 app_id:8; + u32 item_id:8; + u32 length:8; + u32 rsvd:8; +}; + +struct __packed me_fwcaps { + u32 id; + u8 length; + struct mefwcaps_sku caps_sku; + u8 reserved[3]; +}; + +/* Defined in me_status.c for both romstage and ramstage */ +void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); + +void intel_early_me_status(void); +int intel_early_me_init(void); +int intel_early_me_uma_size(void); +int intel_early_me_init_done(u8 status); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/arch-ivybridge/microcode.h new file mode 100644 index 0000000000..b868283761 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/microcode.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MICROCODE_H +#define __ASM_ARCH_MICROCODE_H + +/* Length of the public header on Intel microcode blobs */ +#define UCODE_HEADER_LEN 0x30 + +#ifndef __ASSEMBLY__ + +/** + * microcode_update_intel() - Apply microcode updates + * + * Applies any microcode updates in the device tree. + * + * @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if + * not updates were found, -EINVAL if an update was invalid + */ +int microcode_update_intel(void); +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h new file mode 100644 index 0000000000..7b4f2e790b --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -0,0 +1,86 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2011 The ChromiumOS Authors. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_MODEL_206AX_H +#define _ASM_ARCH_MODEL_206AX_H + +/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ +#define SANDYBRIDGE_BCLK 100 + +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define MSR_FEATURE_CONFIG 0x13c +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) +#define IA32_PLATFORM_DCA_CAP 0x1f8 +#define IA32_MISC_ENABLE 0x1a0 +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define IA32_PERF_CTL 0x199 +#define IA32_THERM_INTERRUPT 0x19b +#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 +#define ENERGY_POLICY_PERFORMANCE 0 +#define ENERGY_POLICY_NORMAL 6 +#define ENERGY_POLICY_POWERSAVE 15 +#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define IA32_MC0_STATUS 0x401 + +#define MSR_PIC_MSG_CONTROL 0x2e +#define PLATFORM_INFO_SET_TDP (1 << 29) + +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_POWER_CTL 0x1fc + +#define MSR_PKGC3_IRTL 0x60a +#define MSR_PKGC6_IRTL 0x60b +#define MSR_PKGC7_IRTL 0x60c +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) + +/* long duration in low dword, short duration in high dword */ +#define PKG_POWER_LIMIT_MASK 0x7fff +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK 0x7f + +#define MSR_PP0_CURRENT_CONFIG 0x601 +#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ +#define MSR_PP1_CURRENT_CONFIG 0x602 +#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ +#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_SKU 0x614 + +#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/mrccache.h b/arch/x86/include/asm/arch-ivybridge/mrccache.h new file mode 100644 index 0000000000..968b2eff9e --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/mrccache.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_MRCCACHE_H +#define _ASM_ARCH_MRCCACHE_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \ + ('D'<<24)) + +__packed struct mrc_data_container { + u32 signature; /* "MRCD" */ + u32 data_size; /* Size of the 'data' field */ + u32 checksum; /* IP style checksum */ + u32 reserved; /* For header alignment */ + u8 data[0]; /* Variable size, platform/run time dependent */ +}; + +struct fmap_entry; +struct spi_flash; + +/** + * mrccache_find_current() - find the latest MRC cache record + * + * This searches the MRC cache region looking for the latest record to use + * for setting up SDRAM + * + * @entry: Information about the position and size of the MRC cache + * @return pointer to latest record, or NULL if none + */ +struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); + +/** + * mrccache_update() - update the MRC cache with a new record + * + * This writes a new record to the end of the MRC cache. If the new record is + * the same as the latest record then the write is skipped + * + * @sf: SPI flash to write to + * @entry: Position and size of MRC cache in SPI flash + * @cur: Record to write + * @return 0 if updated, -EEXIST if the record is the same as the latest + * record, other error if SPI write failed + */ +int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, + struct mrc_data_container *cur); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h new file mode 100644 index 0000000000..21df083842 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot src/southbridge/intel/bd82x6x/pch.h + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_PCH_H +#define _ASM_ARCH_PCH_H + +#include + +/* PCH types */ +#define PCH_TYPE_CPT 0x1c /* CougarPoint */ +#define PCH_TYPE_PPT 0x1e /* IvyBridge */ + +/* PCH stepping values for LPC device */ +#define PCH_STEP_A0 0 +#define PCH_STEP_A1 1 +#define PCH_STEP_B0 2 +#define PCH_STEP_B1 3 +#define PCH_STEP_B2 4 +#define PCH_STEP_B3 5 +#define DEFAULT_GPIOBASE 0x0480 +#define DEFAULT_PMBASE 0x0500 + +#define SMBUS_IO_BASE 0x0400 + +int pch_silicon_revision(void); +int pch_silicon_type(void); +int pch_silicon_supported(int type, int rev); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +/* PCI Configuration Space (D30:F0): PCI2PCI */ +#define PSTS 0x06 +#define SMLT 0x1b +#define SECSTS 0x1e +#define INTR 0x3c +#define BCTRL 0x3e +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) + +#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) +#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) +#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) +#define PCH_ME_DEV PCI_BDF(0, 0x16, 0) +#define PCH_PCIE_DEV_SLOT 28 + +#define PCH_DEV PCI_BDF(0, 0, 0) +#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0) + +/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) +#define SERIRQ_CNTL 0x64 + +#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) + +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0xDC +#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_ROUT 0xb8 + +#define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 +#define PIRQE_ROUT 0x68 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B + +#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0xDC +#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_ROUT 0xb8 + +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ +#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ +#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ +#define LPC_GENX_DEC(x) (0x84 + 4 * (x)) + +/* PCI Configuration Space (D31:F1): IDE */ +#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) +#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2) +#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5) + +#define INTR_LN 0x3c +#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) +#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ + +#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) + +#define IDE_SDMA_TIM 0x4a + +#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) + +#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ +#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ +#define SATA_SP 0xd0 /* Scratchpad */ + +/* SATA IOBP Registers */ +#define SATA_IOBP_SP0G3IR 0xea000151 +#define SATA_IOBP_SP1G3IR 0xea000051 + +/* PCI Configuration Space (D31:F3): SMBus */ +#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) +#define SMB_BASE 0x20 +#define HOSTC 0x40 +#define SMB_RCV_SLVA 0x09 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + + +/* Root Complex Register Block */ +#define DEFAULT_RCBA 0xfed1c000 +#define RCB_REG(reg) (DEFAULT_RCBA + (reg)) + +#define PCH_RCBA_BASE 0xf0 + +#define VCH 0x0000 /* 32bit */ +#define VCAP1 0x0004 /* 32bit */ +#define VCAP2 0x0008 /* 32bit */ +#define PVC 0x000c /* 16bit */ +#define PVS 0x000e /* 16bit */ + +#define V0CAP 0x0010 /* 32bit */ +#define V0CTL 0x0014 /* 32bit */ +#define V0STS 0x001a /* 16bit */ + +#define V1CAP 0x001c /* 32bit */ +#define V1CTL 0x0020 /* 32bit */ +#define V1STS 0x0026 /* 16bit */ + +#define RCTCL 0x0100 /* 32bit */ +#define ESD 0x0104 /* 32bit */ +#define ULD 0x0110 /* 32bit */ +#define ULBA 0x0118 /* 64bit */ + +#define RP1D 0x0120 /* 32bit */ +#define RP1BA 0x0128 /* 64bit */ +#define RP2D 0x0130 /* 32bit */ +#define RP2BA 0x0138 /* 64bit */ +#define RP3D 0x0140 /* 32bit */ +#define RP3BA 0x0148 /* 64bit */ +#define RP4D 0x0150 /* 32bit */ +#define RP4BA 0x0158 /* 64bit */ +#define HDD 0x0160 /* 32bit */ +#define HDBA 0x0168 /* 64bit */ +#define RP5D 0x0170 /* 32bit */ +#define RP5BA 0x0178 /* 64bit */ +#define RP6D 0x0180 /* 32bit */ +#define RP6BA 0x0188 /* 64bit */ + +#define RPC 0x0400 /* 32bit */ +#define RPFN 0x0404 /* 32bit */ + +#define TRSR 0x1e00 /* 8bit */ +#define TRCR 0x1e10 /* 64bit */ +#define TWDR 0x1e18 /* 64bit */ + +#define IOTR0 0x1e80 /* 64bit */ +#define IOTR1 0x1e88 /* 64bit */ +#define IOTR2 0x1e90 /* 64bit */ +#define IOTR3 0x1e98 /* 64bit */ + +#define TCTL 0x3000 /* 8bit */ + +#define NOINT 0 +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +#define DIR_IDR 12 /* Interrupt D Pin Offset */ +#define DIR_ICR 8 /* Interrupt C Pin Offset */ +#define DIR_IBR 4 /* Interrupt B Pin Offset */ +#define DIR_IAR 0 /* Interrupt A Pin Offset */ + +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) +#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) + +#define D31IP 0x3100 /* 32bit */ +#define D31IP_TTIP 24 /* Thermal Throttle Pin */ +#define D31IP_SIP2 20 /* SATA Pin 2 */ +#define D31IP_SMIP 12 /* SMBUS Pin */ +#define D31IP_SIP 8 /* SATA Pin */ +#define D30IP 0x3104 /* 32bit */ +#define D30IP_PIP 0 /* PCI Bridge Pin */ +#define D29IP 0x3108 /* 32bit */ +#define D29IP_E1P 0 /* EHCI #1 Pin */ +#define D28IP 0x310c /* 32bit */ +#define D28IP_P8IP 28 /* PCI Express Port 8 */ +#define D28IP_P7IP 24 /* PCI Express Port 7 */ +#define D28IP_P6IP 20 /* PCI Express Port 6 */ +#define D28IP_P5IP 16 /* PCI Express Port 5 */ +#define D28IP_P4IP 12 /* PCI Express Port 4 */ +#define D28IP_P3IP 8 /* PCI Express Port 3 */ +#define D28IP_P2IP 4 /* PCI Express Port 2 */ +#define D28IP_P1IP 0 /* PCI Express Port 1 */ +#define D27IP 0x3110 /* 32bit */ +#define D27IP_ZIP 0 /* HD Audio Pin */ +#define D26IP 0x3114 /* 32bit */ +#define D26IP_E2P 0 /* EHCI #2 Pin */ +#define D25IP 0x3118 /* 32bit */ +#define D25IP_LIP 0 /* GbE LAN Pin */ +#define D22IP 0x3124 /* 32bit */ +#define D22IP_KTIP 12 /* KT Pin */ +#define D22IP_IDERIP 8 /* IDE-R Pin */ +#define D22IP_MEI2IP 4 /* MEI #2 Pin */ +#define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCIIP 0 +#define D31IR 0x3140 /* 16bit */ +#define D30IR 0x3142 /* 16bit */ +#define D29IR 0x3144 /* 16bit */ +#define D28IR 0x3146 /* 16bit */ +#define D27IR 0x3148 /* 16bit */ +#define D26IR 0x314c /* 16bit */ +#define D25IR 0x3150 /* 16bit */ +#define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ +#define OIC 0x31fe /* 16bit */ + +#define SPI_FREQ_SWSEQ 0x3893 +#define SPI_DESC_COMP0 0x38b0 +#define SPI_FREQ_WR_ERA 0x38b4 +#define SOFT_RESET_CTRL 0x38f4 +#define SOFT_RESET_DATA 0x38f8 + +#define DIR_ROUTE(a, b, c, d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + ((b) << DIR_IBR) | ((a) << DIR_IAR)) + +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ +#define PCH_DISABLE_GBE (1 << 5) +#define FD 0x3418 /* 32bit */ +#define DISPBDF 0x3424 /* 16bit */ +#define FD2 0x3428 /* 32bit */ +#define CG 0x341c /* 32bit */ + +/* Function Disable 1 RCBA 0x3418 */ +#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) +#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_SATA1 (1 << 2) +#define PCH_DISABLE_SMBUS (1 << 3) +#define PCH_DISABLE_HD_AUDIO (1 << 4) +#define PCH_DISABLE_EHCI2 (1 << 13) +#define PCH_DISABLE_LPC (1 << 14) +#define PCH_DISABLE_EHCI1 (1 << 15) +#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) +#define PCH_DISABLE_THERMAL (1 << 24) +#define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) + +/* Function Disable 2 RCBA 0x3428 */ +#define PCH_DISABLE_KT (1 << 4) +#define PCH_DISABLE_IDER (1 << 3) +#define PCH_DISABLE_MEI2 (1 << 2) +#define PCH_DISABLE_MEI1 (1 << 1) +#define PCH_ENABLE_DBDF (1 << 0) + +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + +/* ICH7 PMBASE */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x50 /* mobile only */ +#define GPE0_STS 0x20 +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN 0x28 +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ +#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */ +#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 +#define TCO1_STS 0x64 +#define DMISCI_STS (1 << 9) +#define TCO2_STS 0x66 + +int lpc_init(struct pci_controller *hose, pci_dev_t dev); +void lpc_enable(pci_dev_t dev); + +/** + * lpc_early_init() - set up LPC serial ports and other early things + * + * @blob: Device tree blob + * @node: Offset of LPC node + * @dev: PCH PCI device containing the LPC + * @return 0 if OK, -ve on error + */ +int lpc_early_init(const void *blob, int node, pci_dev_t dev); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/pei_data.h b/arch/x86/include/asm/arch-ivybridge/pei_data.h new file mode 100644 index 0000000000..94533368ea --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/pei_data.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2011, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef ASM_ARCH_PEI_DATA_H +#define ASM_ARCH_PEI_DATA_H + +#include + +struct pch_usb3_controller_settings { + /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ + uint16_t mode; + /* 4 bit mask, 1: switchable, 0: not switchable */ + uint16_t hs_port_switch_mask; + /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ + uint16_t preboot_support; + /* 0: Disable, 1: Enable */ + uint16_t xhci_streams; +}; + +typedef asmlinkage void (*tx_byte_func)(unsigned char byte); + +#define PEI_VERSION 6 + +struct __packed pei_data { + uint32_t pei_version; + uint32_t mchbar; + uint32_t dmibar; + uint32_t epbar; + uint32_t pciexbar; + uint16_t smbusbar; + uint32_t wdbbar; + uint32_t wdbsize; + uint32_t hpet_address; + uint32_t rcba; + uint32_t pmbase; + uint32_t gpiobase; + uint32_t thermalbase; + uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ + uint32_t tseg_size; + uint8_t spd_addresses[4]; + uint8_t ts_addresses[4]; + int boot_mode; + int ec_present; + int gbe_enable; + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + int dimm_channel0_disabled; + int dimm_channel1_disabled; + /* Seed values saved in CMOS */ + uint32_t scrambler_seed; + uint32_t scrambler_seed_s3; + /* Data read from flash and passed into MRC */ + unsigned char *mrc_input; + unsigned int mrc_input_len; + /* Data from MRC that should be saved to flash */ + unsigned char *mrc_output; + unsigned int mrc_output_len; + /* + * Max frequency DDR3 could be ran at. Could be one of four values: + * 800, 1067, 1333, 1600 + */ + uint32_t max_ddr3_freq; + /* + * USB Port Configuration: + * [0] = enable + * [1] = overcurrent pin + * [2] = length + * + * Ports 0-7 can be mapped to OC0-OC3 + * Ports 8-13 can be mapped to OC4-OC7 + * + * Port Length + * MOBILE: + * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * DESKTOP: + * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) + */ + uint16_t usb_port_config[16][3]; + /* See the usb3 struct above for details */ + struct pch_usb3_controller_settings usb3; + /* + * SPD data array for onboard RAM. Specify address 0xf0, + * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in + * spd_address for a given "DIMM". + */ + uint8_t spd_data[4][256]; + tx_byte_func tx_byte; + int ddr3lv_support; + /* + * pcie_init needs to be set to 1 to have the system agent initialise + * PCIe. Note: This should only be required if your system has Gen3 + * devices and it will increase your boot time by at least 100ms. + */ + int pcie_init; + /* + * N mode functionality. Leave this setting at 0. + * 0 Auto + * 1 1N + * 2 2N + */ + int nmode; + /* + * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + int ddr_refresh_rate_config; +}; + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h new file mode 100644 index 0000000000..cf7457f42d --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file of the same name + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ACH_ASM_SANDYBRIDGE_H +#define _ACH_ASM_SANDYBRIDGE_H + +/* Chipset types */ +#define SANDYBRIDGE_MOBILE 0 +#define SANDYBRIDGE_DESKTOP 1 +#define SANDYBRIDGE_SERVER 2 + +/* Device ID for SandyBridge and IvyBridge */ +#define BASE_REV_SNB 0x00 +#define BASE_REV_IVB 0x50 +#define BASE_REV_MASK 0x50 + +/* SandyBridge CPU stepping */ +#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ +#define SNB_STEP_D1 (BASE_REV_SNB + 6) +#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ + +/* IvyBridge CPU stepping */ +#define IVB_STEP_A0 (BASE_REV_IVB + 0) +#define IVB_STEP_B0 (BASE_REV_IVB + 2) +#define IVB_STEP_C0 (BASE_REV_IVB + 4) +#define IVB_STEP_K0 (BASE_REV_IVB + 5) +#define IVB_STEP_D0 (BASE_REV_IVB + 6) + +/* Intel Enhanced Debug region must be 4MB */ +#define IED_SIZE 0x400000 + +/* Northbridge BARs */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_RCBABASE 0xfed1c000 +/* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define X60BAR 0x60 + +#define GGC 0x50 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_PEG60 (1 << 13) +#define DEVEN_IGD (1 << 4) +#define DEVEN_PEG10 (1 << 3) +#define DEVEN_PEG11 (1 << 2) +#define DEVEN_PEG12 (1 << 1) +#define DEVEN_HOST (1 << 0) + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define LAC 0x87 /* Legacy Access Control */ +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define TOM 0xa0 +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +/* Device 0:1.0 PCI configuration space (PCI Express) */ +#define BCTRL1 0x3e /* 16bit */ + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define MSAC 0x62 /* Multi Size Aperture Control */ +#define SWSCI 0xe8 /* SWSCI enable */ +#define ASLS 0xfc /* OpRegion Base */ + +/* + * MCHBAR + */ +#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg)) + +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ + +/* + * DMIBAR + */ + +#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x) + +int bridge_silicon_revision(void); + +void northbridge_enable(pci_dev_t dev); +void northbridge_init(pci_dev_t dev); + +void report_platform_info(void); + +void sandybridge_early_init(int chipset_type); + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h new file mode 100644 index 0000000000..a9d7156109 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_API_H__ +#define __FSP_API_H__ + +/* + * FspInit continuation function prototype. + * Control will be returned to this callback function after FspInit API call. + */ +typedef void (*fsp_continuation_f)(u32 status, void *hob_list); + +struct fsp_init_params { + /* Non-volatile storage buffer pointer */ + void *nvs_buf; + /* Runtime buffer pointer */ + void *rt_buf; + /* Continuation function address */ + fsp_continuation_f continuation; +}; + +struct common_buf { + /* + * Stack top pointer used by the bootloader. The new stack frame will be + * set up at this location after FspInit API call. + */ + u32 *stack_top; + u32 boot_mode; /* Current system boot mode */ + void *upd_data; /* User platform configuraiton data region */ + u32 reserved[7]; /* Reserved */ +}; + +enum fsp_phase { + /* Notification code for post PCI enuermation */ + INIT_PHASE_PCI = 0x20, + /* Notification code before transfering control to the payload */ + INIT_PHASE_BOOT = 0x40 +}; + +struct fsp_notify_params { + /* Notification phase used for NotifyPhase API */ + enum fsp_phase phase; +}; + +/* FspInit API function prototype */ +typedef u32 (*fsp_init_f)(struct fsp_init_params *params); + +/* FspNotify API function prototype */ +typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params); + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h new file mode 100644 index 0000000000..c3f8b49471 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_BOOT_MODE_H__ +#define __FSP_BOOT_MODE_H__ + +/* 0x21 - 0xf..f are reserved */ +#define BOOT_FULL_CONFIG 0x00 +#define BOOT_MINIMAL_CONFIG 0x01 +#define BOOT_NO_CONFIG_CHANGES 0x02 +#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03 +#define BOOT_DEFAULT_SETTINGS 0x04 +#define BOOT_ON_S4_RESUME 0x05 +#define BOOT_ON_S5_RESUME 0x06 +#define BOOT_ON_S2_RESUME 0x10 +#define BOOT_ON_S3_RESUME 0x11 +#define BOOT_ON_FLASH_UPDATE 0x12 +#define BOOT_IN_RECOVERY_MODE 0x20 + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h new file mode 100644 index 0000000000..eaec2b490e --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_FFS_H__ +#define __FSP_FFS_H__ + +/* Used to verify the integrity of the file */ +union __packed ffs_integrity { + struct { + /* + * The IntegrityCheck.checksum.header field is an 8-bit + * checksum of the file header. The State and + * IntegrityCheck.checksum.file fields are assumed to be zero + * and the checksum is calculated such that the entire header + * sums to zero. + */ + u8 header; + /* + * If the FFS_ATTRIB_CHECKSUM (see definition below) bit of + * the Attributes field is set to one, the + * IntegrityCheck.checksum.file field is an 8-bit checksum of + * the file data. If the FFS_ATTRIB_CHECKSUM bit of the + * Attributes field is cleared to zero, the + * IntegrityCheck.checksum.file field must be initialized with + * a value of 0xAA. The IntegrityCheck.checksum.file field is + * valid any time the EFI_FILE_DATA_VALID bit is set in the + * State field. + */ + u8 file; + } checksum; + + /* This is the full 16 bits of the IntegrityCheck field */ + u16 checksum16; +}; + +/* + * Each file begins with the header that describe the + * contents and state of the files. + */ +struct __packed ffs_file_header { + /* + * This GUID is the file name. + * It is used to uniquely identify the file. + */ + struct efi_guid name; + /* Used to verify the integrity of the file */ + union ffs_integrity integrity; + /* Identifies the type of file */ + u8 type; + /* Declares various file attribute bits */ + u8 attr; + /* The length of the file in bytes, including the FFS header */ + u8 size[3]; + /* + * Used to track the state of the file throughout the life of + * the file from creation to deletion. + */ + u8 state; +}; + +struct __packed ffs_file_header2 { + /* + * This GUID is the file name. It is used to uniquely identify the file. + * There may be only one instance of a file with the file name GUID of + * Name in any given firmware volume, except if the file type is + * EFI_FV_FILE_TYPE_FFS_PAD. + */ + struct efi_guid name; + /* Used to verify the integrity of the file */ + union ffs_integrity integrity; + /* Identifies the type of file */ + u8 type; + /* Declares various file attribute bits */ + u8 attr; + /* + * The length of the file in bytes, including the FFS header. + * The length of the file data is either + * (size - sizeof(struct ffs_file_header)). This calculation means a + * zero-length file has a size of 24 bytes, which is + * sizeof(struct ffs_file_header). Size is not required to be a + * multiple of 8 bytes. Given a file F, the next file header is located + * at the next 8-byte aligned firmware volume offset following the last + * byte of the file F. + */ + u8 size[3]; + /* + * Used to track the state of the file throughout the life of + * the file from creation to deletion. + */ + u8 state; + /* + * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists + * and size must be set to zero. + * If FFS_ATTRIB_LARGE_FILE is not set then + * struct ffs_file_header is used. + */ + u32 ext_size; +}; + +/* + * Pseudo type. It is used as a wild card when retrieving sections. + * The section type EFI_SECTION_ALL matches all section types. + */ +#define EFI_SECTION_ALL 0x00 + +/* Encapsulation section Type values */ +#define EFI_SECTION_COMPRESSION 0x01 +#define EFI_SECTION_GUID_DEFINED 0x02 +#define EFI_SECTION_DISPOSABLE 0x03 + +/* Leaf section Type values */ +#define EFI_SECTION_PE32 0x10 +#define EFI_SECTION_PIC 0x11 +#define EFI_SECTION_TE 0x12 +#define EFI_SECTION_DXE_DEPEX 0x13 +#define EFI_SECTION_VERSION 0x14 +#define EFI_SECTION_USER_INTERFACE 0x15 +#define EFI_SECTION_COMPATIBILITY16 0x16 +#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 +#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 +#define EFI_SECTION_RAW 0x19 +#define EFI_SECTION_PEI_DEPEX 0x1B +#define EFI_SECTION_SMM_DEPEX 0x1C + +/* Common section header */ +struct __packed raw_section { + /* + * A 24-bit unsigned integer that contains the total size of + * the section in bytes, including the EFI_COMMON_SECTION_HEADER. + */ + u8 size[3]; + u8 type; +}; + +struct __packed raw_section2 { + /* + * A 24-bit unsigned integer that contains the total size of + * the section in bytes, including the EFI_COMMON_SECTION_HEADER. + */ + u8 size[3]; + u8 type; + /* + * If size is 0xFFFFFF, then ext_size contains the size of + * the section. If size is not equal to 0xFFFFFF, then this + * field does not exist. + */ + u32 ext_size; +}; + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h new file mode 100644 index 0000000000..a024451a74 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_FV___ +#define __FSP_FV___ + +/* Value of EFI_FV_FILE_ATTRIBUTES */ +#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F +#define EFI_FV_FILE_ATTR_FIXED 0x00000100 +#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200 + +/* Attributes bit definitions */ +#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 +#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 +#define EFI_FVB2_READ_STATUS 0x00000004 +#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 +#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 +#define EFI_FVB2_WRITE_STATUS 0x00000020 +#define EFI_FVB2_LOCK_CAP 0x00000040 +#define EFI_FVB2_LOCK_STATUS 0x00000080 +#define EFI_FVB2_STICKY_WRITE 0x00000200 +#define EFI_FVB2_MEMORY_MAPPED 0x00000400 +#define EFI_FVB2_ERASE_POLARITY 0x00000800 +#define EFI_FVB2_READ_LOCK_CAP 0x00001000 +#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 +#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 +#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 +#define EFI_FVB2_ALIGNMENT 0x001F0000 +#define EFI_FVB2_ALIGNMENT_1 0x00000000 +#define EFI_FVB2_ALIGNMENT_2 0x00010000 +#define EFI_FVB2_ALIGNMENT_4 0x00020000 +#define EFI_FVB2_ALIGNMENT_8 0x00030000 +#define EFI_FVB2_ALIGNMENT_16 0x00040000 +#define EFI_FVB2_ALIGNMENT_32 0x00050000 +#define EFI_FVB2_ALIGNMENT_64 0x00060000 +#define EFI_FVB2_ALIGNMENT_128 0x00070000 +#define EFI_FVB2_ALIGNMENT_256 0x00080000 +#define EFI_FVB2_ALIGNMENT_512 0x00090000 +#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 +#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 +#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 +#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 +#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 +#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 +#define EFI_FVB2_ALIGNMENT_64K 0x00100000 +#define EFI_FVB2_ALIGNMENT_128K 0x00110000 +#define EFI_FVB2_ALIGNMENT_256K 0x00120000 +#define EFI_FVB2_ALIGNMENT_512K 0x00130000 +#define EFI_FVB2_ALIGNMENT_1M 0x00140000 +#define EFI_FVB2_ALIGNMENT_2M 0x00150000 +#define EFI_FVB2_ALIGNMENT_4M 0x00160000 +#define EFI_FVB2_ALIGNMENT_8M 0x00170000 +#define EFI_FVB2_ALIGNMENT_16M 0x00180000 +#define EFI_FVB2_ALIGNMENT_32M 0x00190000 +#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 +#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 +#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 +#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 +#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 +#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 + +struct fv_blkmap_entry { + /* The number of sequential blocks which are of the same size */ + u32 num_blocks; + /* The size of the blocks */ + u32 length; +}; + +/* Describes the features and layout of the firmware volume */ +struct fv_header { + /* + * The first 16 bytes are reserved to allow for the reset vector of + * processors whose reset vector is at address 0. + */ + u8 zero_vec[16]; + /* + * Declares the file system with which the firmware volume + * is formatted. + */ + struct efi_guid fs_guid; + /* + * Length in bytes of the complete firmware volume, including + * the header. + */ + u64 fv_len; + /* Set to EFI_FVH_SIGNATURE */ + u32 sign; + /* + * Declares capabilities and power-on defaults for the firmware + * volume. + */ + u32 attr; + /* Length in bytes of the complete firmware volume header */ + u16 hdr_len; + /* + * A 16-bit checksum of the firmware volume header. + * A valid header sums to zero. + */ + u16 checksum; + /* + * Offset, relative to the start of the header, of the extended + * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is + * no extended header. + */ + u16 ext_hdr_off; + /* This field must always be set to zero */ + u8 reserved[1]; + /* + * Set to 2. Future versions of this specification may define new + * header fields and will increment the Revision field accordingly. + */ + u8 rev; + /* + * An array of run-length encoded FvBlockMapEntry structures. + * The array is terminated with an entry of {0,0}. + */ + struct fv_blkmap_entry block_map[1]; +}; + +#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H') + +/* Firmware Volume Header Revision definition */ +#define EFI_FVH_REVISION 0x02 + +/* Extension header pointed by ExtHeaderOffset of volume header */ +struct fv_ext_header { + /* firmware volume name */ + struct efi_guid fv_name; + /* Size of the rest of the extension header including this structure */ + u32 ext_hdr_size; +}; + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h new file mode 100644 index 0000000000..6cca7f5654 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_HOB_H__ +#define __FSP_HOB_H__ + +/* Type of HOB Header */ +#define HOB_TYPE_MEM_ALLOC 0x0002 +#define HOB_TYPE_RES_DESC 0x0003 +#define HOB_TYPE_GUID_EXT 0x0004 +#define HOB_TYPE_UNUSED 0xFFFE +#define HOB_TYPE_EOH 0xFFFF + +/* + * Describes the format and size of the data inside the HOB. + * All HOBs must contain this generic HOB header. + */ +struct hob_header { + u16 type; /* HOB type */ + u16 len; /* HOB length */ + u32 reserved; /* always zero */ +}; + +/* Enumeration of memory types introduced in UEFI */ +enum efi_mem_type { + EFI_RESERVED_MEMORY_TYPE, + /* + * The code portions of a loaded application. + * (Note that UEFI OS loaders are UEFI applications.) + */ + EFI_LOADER_CODE, + /* + * The data portions of a loaded application and + * the default data allocation type used by an application + * to allocate pool memory. + */ + EFI_LOADER_DATA, + /* The code portions of a loaded Boot Services Driver */ + EFI_BOOT_SERVICES_CODE, + /* + * The data portions of a loaded Boot Serves Driver and + * the default data allocation type used by a Boot Services + * Driver to allocate pool memory. + */ + EFI_BOOT_SERVICES_DATA, + /* The code portions of a loaded Runtime Services Driver */ + EFI_RUNTIME_SERVICES_CODE, + /* + * The data portions of a loaded Runtime Services Driver and + * the default data allocation type used by a Runtime Services + * Driver to allocate pool memory. + */ + EFI_RUNTIME_SERVICES_DATA, + /* Free (unallocated) memory */ + EFI_CONVENTIONAL_MEMORY, + /* Memory in which errors have been detected */ + EFI_UNUSABLE_MEMORY, + /* Memory that holds the ACPI tables */ + EFI_ACPI_RECLAIM_MEMORY, + /* Address space reserved for use by the firmware */ + EFI_ACPI_MEMORY_NVS, + /* + * Used by system firmware to request that a memory-mapped IO region + * be mapped by the OS to a virtual address so it can be accessed by + * EFI runtime services. + */ + EFI_MMAP_IO, + /* + * System memory-mapped IO region that is used to translate + * memory cycles to IO cycles by the processor. + */ + EFI_MMAP_IO_PORT, + /* + * Address space reserved by the firmware for code that is + * part of the processor. + */ + EFI_PAL_CODE, + EFI_MAX_MEMORY_TYPE +}; + +/* + * Describes all memory ranges used during the HOB producer phase that + * exist outside the HOB list. This HOB type describes how memory is used, + * not the physical attributes of memory. + */ +struct hob_mem_alloc { + struct hob_header hdr; + /* + * A GUID that defines the memory allocation region's type and purpose, + * as well as other fields within the memory allocation HOB. This GUID + * is used to define the additional data within the HOB that may be + * present for the memory allocation HOB. Type efi_guid is defined in + * InstallProtocolInterface() in the UEFI 2.0 specification. + */ + struct efi_guid name; + /* + * The base address of memory allocated by this HOB. + * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0 + * specification. + */ + phys_addr_t mem_base; + /* The length in bytes of memory allocated by this HOB */ + phys_size_t mem_len; + /* + * Defines the type of memory allocated by this HOB. + * The memory type definition follows the EFI_MEMORY_TYPE definition. + * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0 + * specification. + */ + enum efi_mem_type mem_type; + /* padding */ + u8 reserved[4]; +}; + +/* Value of ResourceType in HOB_RES_DESC */ +#define RES_SYS_MEM 0x00000000 +#define RES_MMAP_IO 0x00000001 +#define RES_IO 0x00000002 +#define RES_FW_DEVICE 0x00000003 +#define RES_MMAP_IO_PORT 0x00000004 +#define RES_MEM_RESERVED 0x00000005 +#define RES_IO_RESERVED 0x00000006 +#define RES_MAX_MEM_TYPE 0x00000007 + +/* + * These types can be ORed together as needed. + * + * The first three enumerations describe settings + * The rest of the settings describe capabilities + */ +#define RES_ATTR_PRESENT 0x00000001 +#define RES_ATTR_INITIALIZED 0x00000002 +#define RES_ATTR_TESTED 0x00000004 +#define RES_ATTR_SINGLE_BIT_ECC 0x00000008 +#define RES_ATTR_MULTIPLE_BIT_ECC 0x00000010 +#define RES_ATTR_ECC_RESERVED_1 0x00000020 +#define RES_ATTR_ECC_RESERVED_2 0x00000040 +#define RES_ATTR_READ_PROTECTED 0x00000080 +#define RES_ATTR_WRITE_PROTECTED 0x00000100 +#define RES_ATTR_EXECUTION_PROTECTED 0x00000200 +#define RES_ATTR_UNCACHEABLE 0x00000400 +#define RES_ATTR_WRITE_COMBINEABLE 0x00000800 +#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x00001000 +#define RES_ATTR_WRITE_BACK_CACHEABLE 0x00002000 +#define RES_ATTR_16_BIT_IO 0x00004000 +#define RES_ATTR_32_BIT_IO 0x00008000 +#define RES_ATTR_64_BIT_IO 0x00010000 +#define RES_ATTR_UNCACHED_EXPORTED 0x00020000 + +/* + * Describes the resource properties of all fixed, nonrelocatable resource + * ranges found on the processor host bus during the HOB producer phase. + */ +struct hob_res_desc { + struct hob_header hdr; + /* + * A GUID representing the owner of the resource. This GUID is + * used by HOB consumer phase components to correlate device + * ownership of a resource. + */ + struct efi_guid owner; + u32 type; + u32 attr; + /* The physical start address of the resource region */ + phys_addr_t phys_start; + /* The number of bytes of the resource region */ + phys_size_t len; +}; + +/* + * Allows writers of executable content in the HOB producer phase to + * maintain and manage HOBs with specific GUID. + */ +struct hob_guid { + struct hob_header hdr; + /* A GUID that defines the contents of this HOB */ + struct efi_guid name; + /* GUID specific data goes here */ +}; + +/** + * get_next_hob() - return a pointer to the next HOB in the HOB list + * + * This macro returns a pointer to HOB that follows the HOB specified by hob + * in the HOB List. + * + * @hdr: A pointer to a HOB. + * + * @return: A pointer to the next HOB in the HOB list. + */ +static inline const struct hob_header *get_next_hob(const struct hob_header *hdr) +{ + return (const struct hob_header *)((u32)hdr + hdr->len); +} + +/** + * end_of_hob() - determine if a HOB is the last HOB in the HOB list + * + * This macro determine if the HOB specified by hob is the last HOB in the + * HOB list. If hob is last HOB in the HOB list, then true is returned. + * Otherwise, false is returned. + * + * @hdr: A pointer to a HOB. + * + * @retval true: The HOB specified by hdr is the last HOB in the HOB list. + * @retval false: The HOB specified by hdr is not the last HOB in the HOB list. + */ +static inline bool end_of_hob(const struct hob_header *hdr) +{ + return hdr->type == HOB_TYPE_EOH; +} + +/** + * get_guid_hob_data() - return a pointer to data buffer from a HOB of + * type HOB_TYPE_GUID_EXT + * + * This macro returns a pointer to the data buffer in a HOB specified by hob. + * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT. + * + * @hdr: A pointer to a HOB. + * + * @return: A pointer to the data buffer in a HOB. + */ +static inline void *get_guid_hob_data(const struct hob_header *hdr) +{ + return (void *)((u32)hdr + sizeof(struct hob_guid)); +} + +/** + * get_guid_hob_data_size() - return the size of the data buffer from a HOB + * of type HOB_TYPE_GUID_EXT + * + * This macro returns the size, in bytes, of the data buffer in a HOB + * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT. + * + * @hdr: A pointer to a HOB. + * + * @return: The size of the data buffer. + */ +static inline u16 get_guid_hob_data_size(const struct hob_header *hdr) +{ + return hdr->len - sizeof(struct hob_guid); +} + +/* FSP specific GUID HOB definitions */ +#define FSP_GUID_DATA1 0x912740be +#define FSP_GUID_DATA2 0x2284 +#define FSP_GUID_DATA3 0x4734 +#define FSP_GUID_DATA4_0 0xb9 +#define FSP_GUID_DATA4_1 0x71 +#define FSP_GUID_DATA4_2 0x84 +#define FSP_GUID_DATA4_3 0xb0 +#define FSP_GUID_DATA4_4 0x27 +#define FSP_GUID_DATA4_5 0x35 +#define FSP_GUID_DATA4_6 0x3f +#define FSP_GUID_DATA4_7 0x0c + +#define FSP_HEADER_GUID \ + { \ + FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \ + { FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \ + FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \ + FSP_GUID_DATA4_6, FSP_GUID_DATA4_7 } \ + } + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + { \ + 0x721acf02, 0x4d77, 0x4c2a, \ + { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ + } + +#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \ + { \ + 0xbbcff46c, 0xc8d3, 0x4113, \ + { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ + { \ + 0x69a79759, 0x1373, 0x4367, \ + { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ + { \ + 0xd038747c, 0xd00c, 0x4980, \ + { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \ + } + +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ + { \ + 0x9c7c3aa7, 0x5332, 0x4917, \ + { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ + } + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h new file mode 100644 index 0000000000..4a4d627b28 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef _FSP_HEADER_H_ +#define _FSP_HEADER_H_ + +#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */ + +struct __packed fsp_header { + u32 sign; /* 'FSPH' */ + u32 hdr_len; /* header length */ + u8 reserved1[3]; + u8 hdr_rev; /* header rev */ + u32 img_rev; /* image rev */ + char img_id[8]; /* signature string */ + u32 img_size; /* image size */ + u32 img_base; /* image base */ + u32 img_attr; /* image attribute */ + u32 cfg_region_off; /* configuration region offset */ + u32 cfg_region_size; /* configuration region size */ + u32 api_num; /* number of API entries */ + u32 fsp_tempram_init; /* tempram_init offset */ + u32 fsp_init; /* fsp_init offset */ + u32 fsp_notify; /* fsp_notify offset */ + u32 reserved2; +}; + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h new file mode 100644 index 0000000000..61286ceb46 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_PLATFORM_H__ +#define __FSP_PLATFORM_H__ + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h new file mode 100644 index 0000000000..ebdbd03435 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include "fsp_types.h" +#include "fsp_fv.h" +#include "fsp_ffs.h" +#include "fsp_api.h" +#include "fsp_hob.h" +#include "fsp_platform.h" +#include "fsp_infoheader.h" +#include "fsp_bootmode.h" +#include "fsp_vpd.h" + +struct shared_data { + struct fsp_header *fsp_hdr; + u32 *stack_top; + struct upd_region fsp_upd; +}; + +#define FSP_LOWMEM_BASE 0x100000UL +#define FSP_HIGHMEM_BASE 0x100000000ULL + +/** + * FSP Continuation assembly helper routine + * + * This routine jumps to the C version of FSP continuation function + */ +void asm_continuation(void); + +/** + * FSP initialization complete + * + * This is the function that indicates FSP initialization is complete and jumps + * back to the bootloader with HOB list pointer as the parameter. + * + * @hob_list: HOB list pointer + */ +void fsp_init_done(void *hob_list); + +/** + * FSP Continuation function + * + * @shared_data: Shared data base before stack migration + * @status: Always 0 + * @hob_list: HOB list pointer + * + * @retval: Never returns + */ +void fsp_continue(struct shared_data *shared_data, u32 status, + void *hob_list); + +/** + * Find FSP header offset in FSP image + * + * @retval: the offset of FSP header. If signature is invalid, returns 0. + */ +u32 find_fsp_header(void); + +/** + * FSP initialization wrapper function. + * + * @stack_top: bootloader stack top address + * @boot_mode: boot mode defined in fsp_bootmode.h + * @nvs_buf: Non-volatile memory buffer pointer + */ +void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf); + +/** + * FSP notification wrapper function + * + * @fsp_hdr: Pointer to FSP information header + * @phase: FSP initialization phase defined in enum fsp_phase + * + * @retval: compatible status code with EFI_STATUS defined in PI spec + */ +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); + +/** + * This function retrieves the top of usable low memory. + * + * @hob_list: A HOB list pointer. + * + * @retval: Usable low memory top. + */ +u32 fsp_get_usable_lowmem_top(const void *hob_list); + +/** + * This function retrieves the top of usable high memory. + * + * @hob_list: A HOB list pointer. + * + * @retval: Usable high memory top. + */ +u64 fsp_get_usable_highmem_top(const void *hob_list); + +/** + * This function retrieves a special reserved memory region. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the GUID HOB data buffer length. + * If the GUID HOB is located, the length will be updated. + * @guid: A pointer to the owner guild. + * + * @retval: Reserved region start address. + * 0 if this region does not exist. + */ +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, + u64 *len, struct efi_guid *guid); + +/** + * This function retrieves the FSP reserved normal memory. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the FSP reserved memory length buffer. + * If the GUID HOB is located, the length will be updated. + * @retval: FSP reserved memory base + * 0 if this region does not exist. + */ +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len); + +/** + * This function retrieves the TSEG reserved normal memory. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the TSEG reserved memory length buffer. + * If the GUID HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the TSEG reserved memory. + * @retval others: TSEG reserved memory base. + */ +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); + +/** + * Returns the next instance of a HOB type from the starting HOB. + * + * @type: HOB type to search + * @hob_list: A pointer to the HOB list + * + * @retval: A HOB object with matching type; Otherwise NULL. + */ +const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list); + +/** + * Returns the next instance of the matched GUID HOB from the starting HOB. + * + * @guid: GUID to search + * @hob_list: A pointer to the HOB list + * + * @retval: A HOB object with matching GUID; Otherwise NULL. + */ +const struct hob_header *fsp_get_next_guid_hob(const struct efi_guid *guid, + const void *hob_list); + +/** + * This function retrieves a GUID HOB data buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the GUID HOB data buffer length. + * If the GUID HOB is located, the length will be updated. + * @guid A pointer to HOB GUID. + * + * @retval NULL: Failed to find the GUID HOB. + * @retval others: GUID HOB data buffer pointer. + */ +void *fsp_get_guid_hob_data(const void *hob_list, u32 *len, + struct efi_guid *guid); + +/** + * This function retrieves FSP Non-volatile Storage HOB buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the NVS data buffer length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the NVS HOB. + * @retval others: FSP NVS data buffer pointer. + */ +void *fsp_get_nvs_data(const void *hob_list, u32 *len); + +/** + * This function retrieves Bootloader temporary stack buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the bootloader temporary stack length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the bootloader temporary stack HOB. + * @retval others: Bootloader temporary stackbuffer pointer. + */ +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); + +/** + * This function overrides the default configurations in the UPD data region. + * + * @fsp_upd: A pointer to the upd_region data strcture + * + * @return: None + */ +void update_fsp_upd(struct upd_region *fsp_upd); + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h new file mode 100644 index 0000000000..f32d8273a0 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_TYPES_H__ +#define __FSP_TYPES_H__ + +/* 128 bit buffer containing a unique identifier value */ +struct efi_guid { + u32 data1; + u16 data2; + u16 data3; + u8 data4[8]; +}; + +/** + * Returns a 16-bit signature built from 2 ASCII characters. + * + * This macro returns a 16-bit value built from the two ASCII characters + * specified by A and B. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * + * @return: A 16-bit value built from the two ASCII characters specified by + * A and B. + */ +#define SIGNATURE_16(A, B) ((A) | (B << 8)) + +/** + * Returns a 32-bit signature built from 4 ASCII characters. + * + * This macro returns a 32-bit value built from the four ASCII characters + * specified by A, B, C, and D. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * @C: The third ASCII character. + * @D: The fourth ASCII character. + * + * @return: A 32-bit value built from the two ASCII characters specified by + * A, B, C and D. + */ +#define SIGNATURE_32(A, B, C, D) \ + (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) + +/** + * Returns a 64-bit signature built from 8 ASCII characters. + * + * This macro returns a 64-bit value built from the eight ASCII characters + * specified by A, B, C, D, E, F, G,and H. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * @C: The third ASCII character. + * @D: The fourth ASCII character. + * @E: The fifth ASCII character. + * @F: The sixth ASCII character. + * @G: The seventh ASCII character. + * @H: The eighth ASCII character. + * + * @return: A 64-bit value built from the two ASCII characters specified by + * A, B, C, D, E, F, G and H. + */ +#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ + (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) + +/* + * Define FSP API return status code. + * Compatiable with EFI_STATUS defined in PI Spec. + */ +#define FSP_SUCCESS 0 +#define FSP_INVALID_PARAM 0x80000002 +#define FSP_UNSUPPORTED 0x80000003 +#define FSP_DEVICE_ERROR 0x80000007 +#define FSP_NOT_FOUND 0x8000000E +#define FSP_ALREADY_STARTED 0x80000014 + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h new file mode 100644 index 0000000000..bce58b1e69 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + * + * This file is automatically generated. Please do NOT modify !!! + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __VPDHEADER_H__ +#define __VPDHEADER_H__ + +#define UPD_TERMINATOR 0x55AA + +struct __packed upd_region { + u64 sign; /* Offset 0x0000 */ + u64 reserved; /* Offset 0x0008 */ + u8 dummy[240]; /* Offset 0x0010 */ + u8 hda_verb_header[12]; /* Offset 0x0100 */ + u32 hda_verb_length; /* Offset 0x010C */ + u8 hda_verb_data0[16]; /* Offset 0x0110 */ + u8 hda_verb_data1[16]; /* Offset 0x0120 */ + u8 hda_verb_data2[16]; /* Offset 0x0130 */ + u8 hda_verb_data3[16]; /* Offset 0x0140 */ + u8 hda_verb_data4[16]; /* Offset 0x0150 */ + u8 hda_verb_data5[16]; /* Offset 0x0160 */ + u8 hda_verb_data6[16]; /* Offset 0x0170 */ + u8 hda_verb_data7[16]; /* Offset 0x0180 */ + u8 hda_verb_data8[16]; /* Offset 0x0190 */ + u8 hda_verb_data9[16]; /* Offset 0x01A0 */ + u8 hda_verb_data10[16]; /* Offset 0x01B0 */ + u8 hda_verb_data11[16]; /* Offset 0x01C0 */ + u8 hda_verb_data12[16]; /* Offset 0x01D0 */ + u8 hda_verb_data13[16]; /* Offset 0x01E0 */ + u8 hda_verb_pad[47]; /* Offset 0x01F0 */ + u16 terminator; /* Offset 0x021F */ +}; + +#define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */ +#define VPD_IMAGE_REV 0x00000301 + +struct __packed vpd_region { + u64 sign; /* Offset 0x0000 */ + u32 img_rev; /* Offset 0x0008 */ + u32 upd_offset; /* Offset 0x000C */ + u8 unused[16]; /* Offset 0x0010 */ + u32 fsp_res_memlen; /* Offset 0x0020 */ + u8 disable_pcie1; /* Offset 0x0024 */ + u8 disable_pcie2; /* Offset 0x0025 */ + u8 disable_pcie3; /* Offset 0x0026 */ + u8 enable_azalia; /* Offset 0x0027 */ + u8 legacy_seg_decode; /* Offset 0x0028 */ + u8 pcie_port_ioh; /* Offset 0x0029 */ +}; + +#endif diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h new file mode 100644 index 0000000000..ab4e059131 --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/gpio.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x44 + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h new file mode 100644 index 0000000000..67c5e0586c --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_TNC_H_ +#define _X86_ARCH_TNC_H_ + +#include + +/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) + +#endif /* _X86_ARCH_TNC_H_ */ diff --git a/arch/x86/include/asm/bootm.h b/arch/x86/include/asm/bootm.h new file mode 100644 index 0000000000..f6a64ce2c9 --- /dev/null +++ b/arch/x86/include/asm/bootm.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2013, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARM_BOOTM_H +#define ARM_BOOTM_H + +void bootm_announce_and_cleanup(void); + +/** + * boot_linux_kernel() - boot a linux kernel + * + * This boots a kernel image, either 32-bit or 64-bit. It will also work with + * a self-extracting kernel, if you set @image_64bit to false. + * + * @setup_base: Pointer to the setup.bin information for the kernel + * @load_address: Pointer to the start of the kernel image + * @image_64bit: true if the image is a raw 64-bit kernel, false if it + * is raw 32-bit or any type of self-extracting kernel + * such as a bzImage. + * @return -ve error code. This function does not return if the kernel was + * booted successfully. + */ +int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit); + +#endif diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h index f06a15cdfc..ff15828a71 100644 --- a/arch/x86/include/asm/config.h +++ b/arch/x86/include/asm/config.h @@ -8,4 +8,7 @@ #define _ASM_CONFIG_H_ #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_LMB +#define CONFIG_SYS_BOOT_RAMDISK_HIGH + #endif diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h new file mode 100644 index 0000000000..c8392915f1 --- /dev/null +++ b/arch/x86/include/asm/cpu.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. + * + * Part of this file is adapted from coreboot + * src/arch/x86/include/arch/cpu.h and + * src/arch/x86/lib/cpu.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +enum { + X86_VENDOR_INVALID = 0, + X86_VENDOR_INTEL, + X86_VENDOR_CYRIX, + X86_VENDOR_AMD, + X86_VENDOR_UMC, + X86_VENDOR_NEXGEN, + X86_VENDOR_CENTAUR, + X86_VENDOR_RISE, + X86_VENDOR_TRANSMETA, + X86_VENDOR_NSC, + X86_VENDOR_SIS, + X86_VENDOR_ANY = 0xfe, + X86_VENDOR_UNKNOWN = 0xff +}; + +struct cpuid_result { + uint32_t eax; + uint32_t ebx; + uint32_t ecx; + uint32_t edx; +}; + +/* + * Generic CPUID function + */ +static inline struct cpuid_result cpuid(int op) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op) + : "edi"); + return result; +} + +/* + * Generic Extended CPUID function + */ +static inline struct cpuid_result cpuid_ext(int op, unsigned ecx) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op), "2" (ecx) + : "edi"); + return result; +} + +/* + * CPUID functions returning a single datum + */ +static inline unsigned int cpuid_eax(unsigned int op) +{ + unsigned int eax; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax) + : "0" (op) + : "ecx", "edx", "edi"); + return eax; +} + +static inline unsigned int cpuid_ebx(unsigned int op) +{ + unsigned int eax, ebx; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=S" (ebx) + : "0" (op) + : "ecx", "edx", "edi"); + return ebx; +} + +static inline unsigned int cpuid_ecx(unsigned int op) +{ + unsigned int eax, ecx; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=c" (ecx) + : "0" (op) + : "edx", "edi"); + return ecx; +} + +static inline unsigned int cpuid_edx(unsigned int op) +{ + unsigned int eax, edx; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=d" (edx) + : "0" (op) + : "ecx", "edi"); + return edx; +} + +/* Standard macro to see if a specific flag is changeable */ +static inline int flag_is_changeable_p(uint32_t flag) +{ + uint32_t f1, f2; + + asm( + "pushfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "movl %0,%1\n\t" + "xorl %2,%0\n\t" + "pushl %0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "popfl\n\t" + : "=&r" (f1), "=&r" (f2) + : "ir" (flag)); + return ((f1^f2) & flag) != 0; +} + +/** + * cpu_enable_paging_pae() - Enable PAE-paging + * + * @cr3: Value to set in cr3 (PDPT or PML4T) + */ +void cpu_enable_paging_pae(ulong cr3); + +/** + * cpu_disable_paging_pae() - Disable paging and PAE + */ +void cpu_disable_paging_pae(void); + +/** + * cpu_has_64bit() - Check if the CPU has 64-bit support + * + * @return 1 if this CPU supports long mode (64-bit), 0 if not + */ +int cpu_has_64bit(void); + +/** + * cpu_vendor_name() - Get CPU vendor name + * + * @vendor: CPU vendor enumeration number + * + * @return: Address to hold the CPU vendor name string + */ +const char *cpu_vendor_name(int vendor); + +#define CPU_MAX_NAME_LEN 49 + +/** + * cpu_get_name() - Get the name of the current cpu + * + * @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including + * @return pointer to name, which will likely be a few bytes after the start + * of @name + * \0 terminator + */ +char *cpu_get_name(char *name); + +/** + * cpu_call64() - Jump to a 64-bit Linux kernel (internal function) + * + * The kernel is uncompressed and the 64-bit entry point is expected to be + * at @target. + * + * This function is used internally - see cpu_jump_to_64bit() for a more + * useful function. + * + * @pgtable: Address of 24KB area containing the page table + * @setup_base: Pointer to the setup.bin information for the kernel + * @target: Pointer to the start of the kernel image + */ +void cpu_call64(ulong pgtable, ulong setup_base, ulong target); + +/** + * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel + * + * The kernel is uncompressed and the 64-bit entry point is expected to be + * at @target. + * + * @setup_base: Pointer to the setup.bin information for the kernel + * @target: Pointer to the start of the kernel image + */ +int cpu_jump_to_64bit(ulong setup_base, ulong target); + +#endif diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 3e8e2cdb9e..5ee06eb70d 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -10,13 +10,64 @@ #ifndef __ASSEMBLY__ +enum pei_boot_mode_t { + PEI_BOOT_NONE = 0, + PEI_BOOT_SOFT_RESET, + PEI_BOOT_RESUME, + +}; + +struct memory_area { + uint64_t start; + uint64_t size; +}; + +struct memory_info { + int num_areas; + uint64_t total_memory; + uint64_t total_32bit_memory; + struct memory_area area[CONFIG_NR_DRAM_BANKS]; +}; + +#define MAX_MTRR_REQUESTS 8 + +/** + * A request for a memory region to be set up in a particular way. These + * requests are processed before board_init_r() is called. They are generally + * optional and can be ignored with some performance impact. + */ +struct mtrr_request { + int type; /* MTRR_TYPE_... */ + uint64_t start; + uint64_t size; +}; + /* Architecture-specific global data */ struct arch_global_data { - struct global_data *gd_addr; /* Location of Global Data */ + struct global_data *gd_addr; /* Location of Global Data */ + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; + uint32_t x86_device; uint64_t tsc_base; /* Initial value returned by rdtsc() */ uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */ uint32_t tsc_prev; /* For show_boot_progress() */ + uint32_t tsc_mhz; /* TSC frequency in MHz */ void *new_fdt; /* Relocated FDT */ + uint32_t bist; /* Built-in self test value */ + enum pei_boot_mode_t pei_boot_mode; + const struct pch_gpio_map *gpio_map; /* board GPIO map */ + struct memory_info meminfo; /* Memory information */ +#ifdef CONFIG_HAVE_FSP + void *hob_list; /* FSP HOB list */ +#endif + struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS]; + int mtrr_req_count; + int has_mtrr; + /* MRC training data to save for the next boot */ + char *mrc_output; + unsigned int mrc_output_len; }; #endif diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index fe09f31515..1099427388 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -1,11 +1,153 @@ /* * Copyright (c) 2012, Google Inc. All rights reserved. - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _X86_GPIO_H_ #define _X86_GPIO_H_ +#include +#include #include +struct ich6_bank_platdata { + uint16_t base_addr; + const char *bank_name; +}; + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 +#define GPIO_MODE_NONE 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_NO_INVERT 0 +#define GPIO_INVERT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_NO_BLINK 0 +#define GPIO_BLINK 1 + +#define GPIO_RESET_PWROK 0 +#define GPIO_RESET_RSMRST 1 + +struct pch_gpio_set1 { + u32 gpio0:1; + u32 gpio1:1; + u32 gpio2:1; + u32 gpio3:1; + u32 gpio4:1; + u32 gpio5:1; + u32 gpio6:1; + u32 gpio7:1; + u32 gpio8:1; + u32 gpio9:1; + u32 gpio10:1; + u32 gpio11:1; + u32 gpio12:1; + u32 gpio13:1; + u32 gpio14:1; + u32 gpio15:1; + u32 gpio16:1; + u32 gpio17:1; + u32 gpio18:1; + u32 gpio19:1; + u32 gpio20:1; + u32 gpio21:1; + u32 gpio22:1; + u32 gpio23:1; + u32 gpio24:1; + u32 gpio25:1; + u32 gpio26:1; + u32 gpio27:1; + u32 gpio28:1; + u32 gpio29:1; + u32 gpio30:1; + u32 gpio31:1; +} __packed; + +struct pch_gpio_set2 { + u32 gpio32:1; + u32 gpio33:1; + u32 gpio34:1; + u32 gpio35:1; + u32 gpio36:1; + u32 gpio37:1; + u32 gpio38:1; + u32 gpio39:1; + u32 gpio40:1; + u32 gpio41:1; + u32 gpio42:1; + u32 gpio43:1; + u32 gpio44:1; + u32 gpio45:1; + u32 gpio46:1; + u32 gpio47:1; + u32 gpio48:1; + u32 gpio49:1; + u32 gpio50:1; + u32 gpio51:1; + u32 gpio52:1; + u32 gpio53:1; + u32 gpio54:1; + u32 gpio55:1; + u32 gpio56:1; + u32 gpio57:1; + u32 gpio58:1; + u32 gpio59:1; + u32 gpio60:1; + u32 gpio61:1; + u32 gpio62:1; + u32 gpio63:1; +} __packed; + +struct pch_gpio_set3 { + u32 gpio64:1; + u32 gpio65:1; + u32 gpio66:1; + u32 gpio67:1; + u32 gpio68:1; + u32 gpio69:1; + u32 gpio70:1; + u32 gpio71:1; + u32 gpio72:1; + u32 gpio73:1; + u32 gpio74:1; + u32 gpio75:1; +} __packed; + +/* + * This hilariously complex structure came from Coreboot. The + * setup_pch_gpios() function uses it. It could be move to device tree, or + * adjust to use masks instead of bitfields. + */ +struct pch_gpio_map { + struct { + const struct pch_gpio_set1 *mode; + const struct pch_gpio_set1 *direction; + const struct pch_gpio_set1 *level; + const struct pch_gpio_set1 *reset; + const struct pch_gpio_set1 *invert; + const struct pch_gpio_set1 *blink; + } set1; + struct { + const struct pch_gpio_set2 *mode; + const struct pch_gpio_set2 *direction; + const struct pch_gpio_set2 *level; + const struct pch_gpio_set2 *reset; + } set2; + struct { + const struct pch_gpio_set3 *mode; + const struct pch_gpio_set3 *direction; + const struct pch_gpio_set3 *level; + const struct pch_gpio_set3 *reset; + } set3; +}; + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio); +void ich_gpio_set_gpio_map(const struct pch_gpio_map *map); + #endif /* _X86_GPIO_H_ */ diff --git a/arch/x86/include/asm/i8254.h b/arch/x86/include/asm/i8254.h index c3ccd4f906..4116de1f07 100644 --- a/arch/x86/include/asm/i8254.h +++ b/arch/x86/include/asm/i8254.h @@ -36,4 +36,7 @@ #define PIT_CMD_MODE4 0x08 /* Select mode 4 */ #define PIT_CMD_MODE5 0x0A /* Select mode 5 */ +/* The clock frequency of the i8253/i8254 PIT */ +#define PIT_TICK_RATE 1193182ul + #endif diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index 73113f90a8..bc4033bed2 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -69,4 +69,6 @@ #define ICW4_AEOI 0x02 /* Automatic EOI Mode */ #define ICW4_PM 0x01 /* Microprocessor Mode */ +int i8259_init(void); + #endif diff --git a/arch/x86/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h index 0f9665f549..c3b5187c22 100644 --- a/arch/x86/include/asm/ibmpc.h +++ b/arch/x86/include/asm/ibmpc.h @@ -18,14 +18,7 @@ #define SYSCTLA 0x92 #define SLAVE_PIC 0xa0 -#if 1 -#define UART0_BASE 0x3f8 -#define UART1_BASE 0x2f8 -#else -/* FixMe: uarts swapped */ -#define UART0_BASE 0x2f8 -#define UART1_BASE 0x3f8 -#endif - +#define UART0_BASE 0x3f8 +#define UART1_BASE 0x2f8 #endif diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h index b07887eadc..8cbe08eb56 100644 --- a/arch/x86/include/asm/init_helpers.h +++ b/arch/x86/include/asm/init_helpers.h @@ -13,7 +13,5 @@ int calculate_relocation_address(void); int init_cache_f_r(void); int init_bd_struct_r(void); int init_func_spi(void); -int find_fdt(void); -int prepare_fdt(void); #endif /* !_INIT_HELPERS_H_ */ diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index 3f46e0920a..25abde7be6 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -27,4 +27,15 @@ void specific_eoi(int irq); extern char exception_stack[]; +/** + * configure_irq_trigger() - Configure IRQ triggering + * + * Switch the given interrupt to be level / edge triggered + * + * @param int_num legacy interrupt number (3-7, 9-15) + * @param is_level_triggered true for level triggered interrupt, false for + * edge triggered interrupt + */ +void configure_irq_trigger(int int_num, bool is_level_triggered); + #endif diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 86bac90e8e..e0b25619cd 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -1,7 +1,7 @@ #ifndef _ASM_IO_H #define _ASM_IO_H -#include +#include /* * This file contains the definitions for the x86 IO instructions @@ -69,6 +69,55 @@ #define memcpy_fromio(a,b,c) memcpy((a),(b),(c)) #define memcpy_toio(a,b,c) memcpy((a),(b),(c)) +#define write_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define read_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define write_le64(a, v) write_arch(q, le64, a, v) +#define write_le32(a, v) write_arch(l, le32, a, v) +#define write_le16(a, v) write_arch(w, le16, a, v) + +#define read_le64(a) read_arch(q, le64, a) +#define read_le32(a) read_arch(l, le32, a) +#define read_le16(a) read_arch(w, le16, a) + +#define write_be32(a, v) write_arch(l, be32, a, v) +#define write_be16(a, v) write_arch(w, be16, a, v) + +#define read_be32(a) read_arch(l, be32, a) +#define read_be16(a) read_arch(w, be16, a) + +#define write_8(a, v) __raw_writeb(v, a) +#define read_8(a) __raw_readb(a) + +#define clrbits(type, addr, clear) \ + write_##type((addr), read_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + write_##type((addr), read_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + write_##type((addr), (read_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + /* * ISA space is 'always mapped' on a typical x86 system, no need to * explicitly ioremap() it. The fact that the ISA IO space is mapped diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h new file mode 100644 index 0000000000..699160f9f7 --- /dev/null +++ b/arch/x86/include/asm/ioapic.h @@ -0,0 +1,38 @@ +/* + * From coreboot file of the same name + * + * Copyright (C) 2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_IOAPIC_H +#define __ASM_IOAPIC_H + +#define IO_APIC_ADDR 0xfec00000 +#define IO_APIC_INDEX IO_APIC_ADDR +#define IO_APIC_DATA (IO_APIC_ADDR + 0x10) +#define IO_APIC_INTERRUPTS 24 + +#define ALL (0xff << 24) +#define NONE 0 +#define DISABLED (1 << 16) +#define ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8) + +u32 io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_write(u32 ioapic_base, u32 reg, u32 value); +void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); +void setup_ioapic(u32 ioapic_base, u8 ioapic_id); +void clear_ioapic(u32 ioapic_base); + +#endif diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h new file mode 100644 index 0000000000..0a7f443195 --- /dev/null +++ b/arch/x86/include/asm/lapic.h @@ -0,0 +1,179 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ARCH_ASM_LAPIC_H +#define _ARCH_ASM_LAPIC_H + +#include +#include +#include +#include + +/* See if I need to initialize the local apic */ +#if CONFIG_SMP || CONFIG_IOAPIC +# define NEED_LAPIC 1 +#else +# define NEED_LAPIC 0 +#endif + +static inline __attribute__((always_inline)) + unsigned long lapic_read(unsigned long reg) +{ + return readl(LAPIC_DEFAULT_BASE + reg); +} + +static inline __attribute__((always_inline)) + void lapic_write(unsigned long reg, unsigned long val) +{ + writel(val, LAPIC_DEFAULT_BASE + reg); +} + +static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void) +{ + do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY); +} + +static inline void enable_lapic(void) +{ + msr_t msr; + + msr = msr_read(LAPIC_BASE_MSR); + msr.hi &= 0xffffff00; + msr.lo |= LAPIC_BASE_MSR_ENABLE; + msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; + msr.lo |= LAPIC_DEFAULT_BASE; + msr_write(LAPIC_BASE_MSR, msr); +} + +static inline void disable_lapic(void) +{ + msr_t msr; + + msr = msr_read(LAPIC_BASE_MSR); + msr.lo &= ~(1 << 11); + msr_write(LAPIC_BASE_MSR, msr); +} + +static inline __attribute__((always_inline)) unsigned long lapicid(void) +{ + return lapic_read(LAPIC_ID) >> 24; +} + +#if !CONFIG_AP_IN_SIPI_WAIT +/* If we need to go back to sipi wait, we use the long non-inlined version of + * this function in lapic_cpu_init.c + */ +static inline __attribute__((always_inline)) void stop_this_cpu(void) +{ + /* Called by an AP when it is ready to halt and wait for a new task */ + for (;;) + cpu_hlt(); +} +#else +void stop_this_cpu(void); +#endif + +#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ + sizeof(*(ptr)))) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +/* + * Note: no "lock" prefix even on SMP: xchg always implies lock anyway + * Note 2: xchg has side effect, so that attribute volatile is necessary, + * but generally the primitive is invalid, *ptr is output argument. --ANK + */ +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + switch (size) { + case 1: + __asm__ __volatile__("xchgb %b0,%1" + : "=q" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 2: + __asm__ __volatile__("xchgw %w0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 4: + __asm__ __volatile__("xchgl %0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + } + + return x; +} + +static inline void lapic_write_atomic(unsigned long reg, unsigned long v) +{ + (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v); +} + + +#ifdef X86_GOOD_APIC +# define FORCE_READ_AROUND_WRITE 0 +# define lapic_read_around(x) lapic_read(x) +# define lapic_write_around(x, y) lapic_write((x), (y)) +#else +# define FORCE_READ_AROUND_WRITE 1 +# define lapic_read_around(x) lapic_read(x) +# define lapic_write_around(x, y) lapic_write_atomic((x), (y)) +#endif + +static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) +{ + int timeout; + unsigned long status; + int result; + lapic_wait_icr_idle(); + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); + timeout = 0; + do { + status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; + } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); + + result = -1; + if (status == LAPIC_ICR_RR_VALID) { + *pvalue = lapic_read(LAPIC_RRR); + result = 0; + } + return result; +} + + +void lapic_setup(void); + +#if CONFIG_SMP +struct device; +int start_cpu(struct device *cpu); +#endif /* CONFIG_SMP */ + +int boot_cpu(void); + +/** + * struct x86_cpu_priv - Information about a single CPU + * + * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is + * just a number representing the CPU core + * + * TODO: Move this to driver model once lifecycle is understood + */ +struct x86_cpu_priv { + int apic_id; + int start_err; +}; + +#endif diff --git a/arch/x86/include/asm/lapic_def.h b/arch/x86/include/asm/lapic_def.h new file mode 100644 index 0000000000..722ceadaa4 --- /dev/null +++ b/arch/x86/include/asm/lapic_def.h @@ -0,0 +1,101 @@ +/* + * Taken from the Coreboot file of the same name + * + * (C) Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_LAPIC_DEF_H +#define _ASM_LAPIC_DEF_H + +#define LAPIC_BASE_MSR 0x1B +#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8) +#define LAPIC_BASE_MSR_ENABLE (1 << 11) +#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 + +#define LOCAL_APIC_ADDR 0xfee00000 +#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR + +#define LAPIC_ID 0x020 +#define LAPIC_LVR 0x030 +#define LAPIC_TASKPRI 0x80 +#define LAPIC_TPRI_MASK 0xFF +#define LAPIC_ARBID 0x090 +#define LAPIC_RRR 0x0C0 +#define LAPIC_SVR 0x0f0 +#define LAPIC_SPIV 0x0f0 +#define LAPIC_SPIV_ENABLE 0x100 +#define LAPIC_ESR 0x280 +#define LAPIC_ESR_SEND_CS 0x00001 +#define LAPIC_ESR_RECV_CS 0x00002 +#define LAPIC_ESR_SEND_ACC 0x00004 +#define LAPIC_ESR_RECV_ACC 0x00008 +#define LAPIC_ESR_SENDILL 0x00020 +#define LAPIC_ESR_RECVILL 0x00040 +#define LAPIC_ESR_ILLREGA 0x00080 +#define LAPIC_ICR 0x300 +#define LAPIC_DEST_SELF 0x40000 +#define LAPIC_DEST_ALLINC 0x80000 +#define LAPIC_DEST_ALLBUT 0xC0000 +#define LAPIC_ICR_RR_MASK 0x30000 +#define LAPIC_ICR_RR_INVALID 0x00000 +#define LAPIC_ICR_RR_INPROG 0x10000 +#define LAPIC_ICR_RR_VALID 0x20000 +#define LAPIC_INT_LEVELTRIG 0x08000 +#define LAPIC_INT_ASSERT 0x04000 +#define LAPIC_ICR_BUSY 0x01000 +#define LAPIC_DEST_LOGICAL 0x00800 +#define LAPIC_DM_FIXED 0x00000 +#define LAPIC_DM_LOWEST 0x00100 +#define LAPIC_DM_SMI 0x00200 +#define LAPIC_DM_REMRD 0x00300 +#define LAPIC_DM_NMI 0x00400 +#define LAPIC_DM_INIT 0x00500 +#define LAPIC_DM_STARTUP 0x00600 +#define LAPIC_DM_EXTINT 0x00700 +#define LAPIC_VECTOR_MASK 0x000FF +#define LAPIC_ICR2 0x310 +#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) +#define SET_LAPIC_DEST_FIELD(x) ((x) << 24) +#define LAPIC_LVTT 0x320 +#define LAPIC_LVTPC 0x340 +#define LAPIC_LVT0 0x350 +#define LAPIC_LVT_TIMER_BASE_MASK (0x3 << 18) +#define GET_LAPIC_TIMER_BASE(x) (((x) >> 18) & 0x3) +#define SET_LAPIC_TIMER_BASE(x) (((x) << 18)) +#define LAPIC_TIMER_BASE_CLKIN 0x0 +#define LAPIC_TIMER_BASE_TMBASE 0x1 +#define LAPIC_TIMER_BASE_DIV 0x2 +#define LAPIC_LVT_TIMER_PERIODIC (1 << 17) +#define LAPIC_LVT_MASKED (1 << 16) +#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15) +#define LAPIC_LVT_REMOTE_IRR (1 << 14) +#define LAPIC_INPUT_POLARITY (1 << 13) +#define LAPIC_SEND_PENDING (1 << 12) +#define LAPIC_LVT_RESERVED_1 (1 << 11) +#define LAPIC_DELIVERY_MODE_MASK (7 << 8) +#define LAPIC_DELIVERY_MODE_FIXED (0 << 8) +#define LAPIC_DELIVERY_MODE_NMI (4 << 8) +#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8) +#define GET_LAPIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) +#define SET_LAPIC_DELIVERY_MODE(x, y) (((x) & ~0x700)|((y) << 8)) +#define LAPIC_MODE_FIXED 0x0 +#define LAPIC_MODE_NMI 0x4 +#define LAPIC_MODE_EXINT 0x7 +#define LAPIC_LVT1 0x360 +#define LAPIC_LVTERR 0x370 +#define LAPIC_TMICT 0x380 +#define LAPIC_TMCCT 0x390 +#define LAPIC_TDCR 0x3E0 +#define LAPIC_TDR_DIV_TMBASE (1 << 2) +#define LAPIC_TDR_DIV_1 0xB +#define LAPIC_TDR_DIV_2 0x0 +#define LAPIC_TDR_DIV_4 0x1 +#define LAPIC_TDR_DIV_8 0x2 +#define LAPIC_TDR_DIV_16 0x3 +#define LAPIC_TDR_DIV_32 0x8 +#define LAPIC_TDR_DIV_64 0x9 +#define LAPIC_TDR_DIV_128 0xA + +#endif diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h new file mode 100644 index 0000000000..bdca72eb6c --- /dev/null +++ b/arch/x86/include/asm/linkage.h @@ -0,0 +1,6 @@ +#ifndef _ASM_X86_LINKAGE_H +#define _ASM_X86_LINKAGE_H + +#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0))) + +#endif /* _ASM_X86_LINKAGE_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 0a36e178f5..2cbb270089 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -44,12 +44,16 @@ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd +#define MSR_NHM_PLATFORM_INFO 0x000000ce #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) +#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) +#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) +#define MSR_PLATFORM_INFO 0x000000ce #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e @@ -64,10 +68,20 @@ #define MSR_OFFCORE_RSP_0 0x000001a6 #define MSR_OFFCORE_RSP_1 0x000001a7 +#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad +#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae + +#define MSR_LBR_SELECT 0x000001c8 +#define MSR_LBR_TOS 0x000001c9 +#define MSR_LBR_NHM_FROM 0x00000680 +#define MSR_LBR_NHM_TO 0x000006c0 +#define MSR_LBR_CORE_FROM 0x00000040 +#define MSR_LBR_CORE_TO 0x00000060 #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 +#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 #define MSR_MTRRfix64K_00000 0x00000250 #define MSR_MTRRfix16K_80000 0x00000258 @@ -91,7 +105,8 @@ #define MSR_IA32_LASTINTTOIP 0x000001de /* DEBUGCTLMSR bits (others vary by model): */ -#define DEBUGCTLMSR_LBR (1UL << 0) +#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ +/* single-step on branches */ #define DEBUGCTLMSR_BTF (1UL << 1) #define DEBUGCTLMSR_TR (1UL << 6) #define DEBUGCTLMSR_BTS (1UL << 7) @@ -100,11 +115,50 @@ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) +#define MSR_IA32_POWER_CTL 0x000001fc + #define MSR_IA32_MC0_CTL 0x00000400 #define MSR_IA32_MC0_STATUS 0x00000401 #define MSR_IA32_MC0_ADDR 0x00000402 #define MSR_IA32_MC0_MISC 0x00000403 +/* C-state Residency Counters */ +#define MSR_PKG_C3_RESIDENCY 0x000003f8 +#define MSR_PKG_C6_RESIDENCY 0x000003f9 +#define MSR_PKG_C7_RESIDENCY 0x000003fa +#define MSR_CORE_C3_RESIDENCY 0x000003fc +#define MSR_CORE_C6_RESIDENCY 0x000003fd +#define MSR_CORE_C7_RESIDENCY 0x000003fe +#define MSR_PKG_C2_RESIDENCY 0x0000060d +#define MSR_PKG_C8_RESIDENCY 0x00000630 +#define MSR_PKG_C9_RESIDENCY 0x00000631 +#define MSR_PKG_C10_RESIDENCY 0x00000632 + +/* Run Time Average Power Limiting (RAPL) Interface */ + +#define MSR_RAPL_POWER_UNIT 0x00000606 + +#define MSR_PKG_POWER_LIMIT 0x00000610 +#define MSR_PKG_ENERGY_STATUS 0x00000611 +#define MSR_PKG_PERF_STATUS 0x00000613 +#define MSR_PKG_POWER_INFO 0x00000614 + +#define MSR_DRAM_POWER_LIMIT 0x00000618 +#define MSR_DRAM_ENERGY_STATUS 0x00000619 +#define MSR_DRAM_PERF_STATUS 0x0000061b +#define MSR_DRAM_POWER_INFO 0x0000061c + +#define MSR_PP0_POWER_LIMIT 0x00000638 +#define MSR_PP0_ENERGY_STATUS 0x00000639 +#define MSR_PP0_POLICY 0x0000063a +#define MSR_PP0_PERF_STATUS 0x0000063b + +#define MSR_PP1_POWER_LIMIT 0x00000640 +#define MSR_PP1_ENERGY_STATUS 0x00000641 +#define MSR_PP1_POLICY 0x00000642 + +#define MSR_CORE_C1_RES 0x00000660 + #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) @@ -123,18 +177,31 @@ #define MSR_P6_EVNTSEL0 0x00000186 #define MSR_P6_EVNTSEL1 0x00000187 +#define MSR_KNC_PERFCTR0 0x00000020 +#define MSR_KNC_PERFCTR1 0x00000021 +#define MSR_KNC_EVNTSEL0 0x00000028 +#define MSR_KNC_EVNTSEL1 0x00000029 + +/* Alternative perfctr range with full access. */ +#define MSR_IA32_PMC0 0x000004c1 + /* AMD64 MSRs. Not complete. See the architecture manual for a more complete list. */ #define MSR_AMD64_PATCH_LEVEL 0x0000008b +#define MSR_AMD64_TSC_RATIO 0xc0000104 #define MSR_AMD64_NB_CFG 0xc001001f #define MSR_AMD64_PATCH_LOADER 0xc0010020 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 +#define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 +#define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 +#define MSR_AMD64_IBSFETCH_REG_COUNT 3 +#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL< - * - * Copyright (C) 1997-1999 Richard Gooch + * From Coreboot file of the same name * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _ASM_X86_MTRR_H -#define _ASM_X86_MTRR_H +#ifndef _ASM_MTRR_H +#define _ASM_MTRR_H -#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) -#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) +/* MTRR region types */ +#define MTRR_TYPE_UNCACHEABLE 0 +#define MTRR_TYPE_WRCOMB 1 +#define MTRR_TYPE_WRTHROUGH 4 +#define MTRR_TYPE_WRPROT 5 +#define MTRR_TYPE_WRBACK 6 -#ifndef __ASSEMBLY__ +#define MTRR_TYPE_COUNT 7 -#include -#include -#include +#define MTRR_CAP_MSR 0x0fe +#define MTRR_DEF_TYPE_MSR 0x2ff -#define MTRR_IOCTL_BASE 'M' +#define MTRR_DEF_TYPE_EN (1 << 11) +#define MTRR_DEF_TYPE_FIX_EN (1 << 10) -struct mtrr_sentry { - unsigned long base; /* Base address */ - unsigned int size; /* Size of region */ - unsigned int type; /* Type of region */ -}; +#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) +#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) -/* - * Warning: this structure has a different order from i386 - * on x86-64. The 32bit emulation code takes care of that. - * But you need to use this for 64bit, otherwise your X server - * will break. - */ +#define MTRR_PHYS_MASK_VALID (1 << 11) -#ifdef __i386__ -struct mtrr_gentry { - unsigned int regnum; /* Register number */ - unsigned long base; /* Base address */ - unsigned int size; /* Size of region */ - unsigned int type; /* Type of region */ -}; +#define MTRR_BASE_TYPE_MASK 0x7 -#else /* __i386__ */ +/* Number of MTRRs supported */ +#define MTRR_COUNT 8 -struct mtrr_gentry { - unsigned long base; /* Base address */ - unsigned int size; /* Size of region */ - unsigned int regnum; /* Register number */ - unsigned int type; /* Type of region */ -}; -#endif /* !__i386__ */ +#if !defined(__ASSEMBLER__) -struct mtrr_var_range { - __u32 base_lo; - __u32 base_hi; - __u32 mask_lo; - __u32 mask_hi; +/** + * Information about the previous MTRR state, set up by mtrr_open() + * + * @deftype: Previous value of MTRR_DEF_TYPE_MSR + * @enable_cache: true if cache was enabled + */ +struct mtrr_state { + uint64_t deftype; + bool enable_cache; }; -/* - * In the Intel processor's MTRR interface, the MTRR type is always held in - * an 8 bit field: +/** + * mtrr_open() - Prepare to adjust MTRRs + * + * Use mtrr_open() passing in a structure - this function will init it. Then + * when done, pass the same structure to mtrr_close() to re-enable MTRRs and + * possibly the cache. + * + * @state: Empty structure to pass in to hold settings */ -typedef __u8 mtrr_type; - -#define MTRR_NUM_FIXED_RANGES 88 -#define MTRR_MAX_VAR_RANGES 256 +void mtrr_open(struct mtrr_state *state); -struct mtrr_state_type { - struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES]; - mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES]; - unsigned char enabled; - unsigned char have_fixed; - mtrr_type def_type; -}; +/** + * mtrr_open() - Clean up after adjusting MTRRs, and enable them + * + * This uses the structure containing information returned from mtrr_open(). + * + * @state: Structure from mtrr_open() + */ +void mtrr_close(struct mtrr_state *state); -/* These are the various ioctls */ -#define MTRRIOC_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry) -#define MTRRIOC_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry) -#define MTRRIOC_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry) -#define MTRRIOC_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry) -#define MTRRIOC_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry) -#define MTRRIOC_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry) -#define MTRRIOC_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry) -#define MTRRIOC_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry) -#define MTRRIOC_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry) -#define MTRRIOC_KILL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry) - -/* These are the region types */ -#define MTRR_TYPE_UNCACHABLE 0 -#define MTRR_TYPE_WRCOMB 1 -/*#define MTRR_TYPE_ 2*/ -/*#define MTRR_TYPE_ 3*/ -#define MTRR_TYPE_WRTHROUGH 4 -#define MTRR_TYPE_WRPROT 5 -#define MTRR_TYPE_WRBACK 6 -#define MTRR_NUM_TYPES 7 - -#ifdef __KERNEL__ - -/* The following functions are for use by other drivers */ -# ifdef CONFIG_MTRR -extern u8 mtrr_type_lookup(u64 addr, u64 end); -extern void mtrr_save_fixed_ranges(void *); -extern void mtrr_save_state(void); -extern int mtrr_add(unsigned long base, unsigned long size, - unsigned int type, bool increment); -extern int mtrr_add_page(unsigned long base, unsigned long size, - unsigned int type, bool increment); -extern int mtrr_del(int reg, unsigned long base, unsigned long size); -extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); -extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); -extern void mtrr_ap_init(void); -extern void mtrr_bp_init(void); -extern void set_mtrr_aps_delayed_init(void); -extern void mtrr_aps_init(void); -extern void mtrr_bp_restore(void); -extern int mtrr_trim_uncached_memory(unsigned long end_pfn); -extern int amd_special_default_mtrr(void); -# else -static inline u8 mtrr_type_lookup(u64 addr, u64 end) -{ - /* - * Return no-MTRRs: - */ - return 0xff; -} -#define mtrr_save_fixed_ranges(arg) do {} while (0) -#define mtrr_save_state() do {} while (0) -static inline int mtrr_del(int reg, unsigned long base, unsigned long size) -{ - return -ENODEV; -} -static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size) -{ - return -ENODEV; -} -static inline int mtrr_trim_uncached_memory(unsigned long end_pfn) -{ - return 0; -} -static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) -{ -} - -#define mtrr_ap_init() do {} while (0) -#define mtrr_bp_init() do {} while (0) -#define set_mtrr_aps_delayed_init() do {} while (0) -#define mtrr_aps_init() do {} while (0) -#define mtrr_bp_restore() do {} while (0) -# endif - -#ifdef CONFIG_COMPAT -#include - -struct mtrr_sentry32 { - compat_ulong_t base; /* Base address */ - compat_uint_t size; /* Size of region */ - compat_uint_t type; /* Type of region */ -}; +/** + * mtrr_add_request() - Add a new MTRR request + * + * This adds a request for a memory region to be set up in a particular way. + * + * @type: Requested type (MTRR_TYPE_) + * @start: Start address + * @size: Size + * + * @return: 0 on success, non-zero on failure + */ +int mtrr_add_request(int type, uint64_t start, uint64_t size); -struct mtrr_gentry32 { - compat_ulong_t regnum; /* Register number */ - compat_uint_t base; /* Base address */ - compat_uint_t size; /* Size of region */ - compat_uint_t type; /* Type of region */ -}; +/** + * mtrr_commit() - set up the MTRR registers based on current requests + * + * This sets up MTRRs for the available DRAM and the requests received so far. + * It must be called with caches disabled. + * + * @do_caches: true if caches are currently on + * + * @return: 0 on success, non-zero on failure + */ +int mtrr_commit(bool do_caches); -#define MTRR_IOCTL_BASE 'M' +#endif -#define MTRRIOC32_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry32) -#define MTRRIOC32_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry32) -#define MTRRIOC32_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry32) -#define MTRRIOC32_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry32) -#define MTRRIOC32_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry32) -#define MTRRIOC32_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry32) -#define MTRRIOC32_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry32) -#define MTRRIOC32_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry32) -#define MTRRIOC32_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry32) -#define MTRRIOC32_KILL_PAGE_ENTRY \ - _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry32) -#endif /* CONFIG_COMPAT */ +#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) +# error "CONFIG_XIP_ROM_SIZE is not a power of 2" +#endif -#endif /* __KERNEL__ */ +#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) +# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +#endif -#endif /* __ASSEMBLY__ */ +#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) -#endif /* _ASM_X86_MTRR_H */ +#endif diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index cbc4a9e2e9..c30dd4c218 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -1,5 +1,4 @@ - /* * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se @@ -13,5 +12,41 @@ #define DEFINE_PCI_DEVICE_TABLE(_table) \ const struct pci_device_id _table[] +struct pci_controller; + void pci_setup_type1(struct pci_controller *hose); + +/** + * board_pci_setup_hose() - Set up the PCI hose + * + * This is called by the common x86 PCI code to set up the PCI controller + * hose. It may be called when no memory/BSS is available so should just + * store things in 'hose' and not in BSS variables. + */ +void board_pci_setup_hose(struct pci_controller *hose); + +/** + * pci_early_init_hose() - Set up PCI host before relocation + * + * This allocates memory for, sets up and returns the PCI hose. It can be + * called before relocation. The hose will be stored in gd->hose for + * later use, but will become invalid one DRAM is available. + */ +int pci_early_init_hose(struct pci_controller **hosep); + +int board_pci_pre_scan(struct pci_controller *hose); +int board_pci_post_scan(struct pci_controller *hose); + +/* + * Simple PCI access routines - these work from either the early PCI hose + * or the 'real' one, created after U-Boot has memory available + */ +unsigned int pci_read_config8(pci_dev_t dev, unsigned where); +unsigned int pci_read_config16(pci_dev_t dev, unsigned where); +unsigned int pci_read_config32(pci_dev_t dev, unsigned where); + +void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); +void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); +void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); + #endif diff --git a/arch/x86/include/asm/pnp_def.h b/arch/x86/include/asm/pnp_def.h new file mode 100644 index 0000000000..24b038d26a --- /dev/null +++ b/arch/x86/include/asm/pnp_def.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * Adapted from coreboot src/include/device/pnp_def.h + * and arch/x86/include/arch/io.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_PNP_DEF_H_ +#define _ASM_PNP_DEF_H_ + +#include + +#define PNP_IDX_EN 0x30 +#define PNP_IDX_IO0 0x60 +#define PNP_IDX_IO1 0x62 +#define PNP_IDX_IO2 0x64 +#define PNP_IDX_IO3 0x66 +#define PNP_IDX_IRQ0 0x70 +#define PNP_IDX_IRQ1 0x72 +#define PNP_IDX_DRQ0 0x74 +#define PNP_IDX_DRQ1 0x75 +#define PNP_IDX_MSC0 0xf0 +#define PNP_IDX_MSC1 0xf1 + +/* Generic functions for pnp devices */ + +/* + * pnp device is a 16-bit integer composed of its i/o port address at high byte + * and logic function number at low byte. + */ +#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) + +static inline void pnp_write_config(uint16_t dev, uint8_t reg, uint8_t value) +{ + uint8_t port = dev >> 8; + + outb(reg, port); + outb(value, port + 1); +} + +static inline uint8_t pnp_read_config(uint16_t dev, uint8_t reg) +{ + uint8_t port = dev >> 8; + + outb(reg, port); + return inb(port + 1); +} + +static inline void pnp_set_logical_device(uint16_t dev) +{ + uint8_t device = dev & 0xff; + + pnp_write_config(dev, 0x07, device); +} + +static inline void pnp_set_enable(uint16_t dev, int enable) +{ + pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0); +} + +static inline int pnp_read_enable(uint16_t dev) +{ + return !!pnp_read_config(dev, PNP_IDX_EN); +} + +static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase) +{ + pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); + pnp_write_config(dev, index + 1, iobase & 0xff); +} + +static inline uint16_t pnp_read_iobase(uint16_t dev, uint8_t index) +{ + return ((uint16_t)(pnp_read_config(dev, index)) << 8) | + pnp_read_config(dev, index + 1); +} + +static inline void pnp_set_irq(uint16_t dev, uint8_t index, unsigned irq) +{ + pnp_write_config(dev, index, irq); +} + +static inline void pnp_set_drq(uint16_t dev, uint8_t index, unsigned drq) +{ + pnp_write_config(dev, index, drq & 0xff); +} + +#endif /* _ASM_PNP_DEF_H_ */ diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h new file mode 100644 index 0000000000..f49ce992d1 --- /dev/null +++ b/arch/x86/include/asm/post.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _post_h +#define _post_h + +/* port to use for post codes */ +#define POST_PORT 0x80 + +/* post codes which represent various stages of init */ +#define POST_START 0x1e +#define POST_CAR_START 0x1f +#define POST_CAR_SIPI 0x20 +#define POST_CAR_MTRR 0x21 +#define POST_CAR_UNCACHEABLE 0x22 +#define POST_CAR_BASE_ADDRESS 0x23 +#define POST_CAR_MASK 0x24 +#define POST_CAR_FILL 0x25 +#define POST_CAR_ROM_CACHE 0x26 +#define POST_CAR_MRC_CACHE 0x27 +#define POST_CAR_CPU_CACHE 0x28 +#define POST_START_STACK 0x29 +#define POST_START_DONE 0x2a +#define POST_CPU_INIT 0x2b +#define POST_EARLY_INIT 0x2c +#define POST_CPU_INFO 0x2d +#define POST_PRE_MRC 0x2e +#define POST_MRC 0x2f +#define POST_DRAM 0x2f +#define POST_LAPIC 0x30 + +#define POST_RAM_FAILURE 0xea +#define POST_BIST_FAILURE 0xeb +#define POST_CAR_FAILURE 0xec + +/* Output a post code using al - value must be 0 to 0xff */ +#ifdef __ASSEMBLY__ +#define post_code(value) \ + movb $value, %al; \ + outb %al, $POST_PORT +#else +#include + +static inline void post_code(int code) +{ + outb(code, POST_PORT); +} +#endif + +#endif diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index bb3172ff91..3e26202aa5 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -8,26 +8,40 @@ #ifndef __ASM_PROCESSOR_H_ #define __ASM_PROCESSOR_H_ 1 -#define X86_GDT_ENTRY_SIZE 8 +#define X86_GDT_ENTRY_SIZE 8 + +#define X86_GDT_ENTRY_NULL 0 +#define X86_GDT_ENTRY_UNUSED 1 +#define X86_GDT_ENTRY_32BIT_CS 2 +#define X86_GDT_ENTRY_32BIT_DS 3 +#define X86_GDT_ENTRY_32BIT_FS 4 +#define X86_GDT_ENTRY_16BIT_CS 5 +#define X86_GDT_ENTRY_16BIT_DS 6 +#define X86_GDT_ENTRY_16BIT_FLAT_CS 7 +#define X86_GDT_ENTRY_16BIT_FLAT_DS 8 +#define X86_GDT_NUM_ENTRIES 9 + +#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) #ifndef __ASSEMBLY__ -enum { - X86_GDT_ENTRY_NULL = 0, - X86_GDT_ENTRY_UNUSED, - X86_GDT_ENTRY_32BIT_CS, - X86_GDT_ENTRY_32BIT_DS, - X86_GDT_ENTRY_32BIT_FS, - X86_GDT_ENTRY_16BIT_CS, - X86_GDT_ENTRY_16BIT_DS, - X86_GDT_NUM_ENTRIES -}; -#else -/* NOTE: If the above enum is modified, this define must be checked */ -#define X86_GDT_ENTRY_32BIT_DS 3 -#define X86_GDT_NUM_ENTRIES 7 -#endif +#define PORT_RESET 0xcf9 -#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) +static inline __attribute__((always_inline)) void cpu_hlt(void) +{ + asm("hlt"); +} + +static inline ulong cpu_get_sp(void) +{ + ulong result; + + asm volatile( + "mov %%esp, %%eax" + : "=a" (result)); + return result; +} + +#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/x86/include/asm/speedstep.h b/arch/x86/include/asm/speedstep.h new file mode 100644 index 0000000000..b938b86ba8 --- /dev/null +++ b/arch/x86/include/asm/speedstep.h @@ -0,0 +1,89 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_SPEEDSTEP_H +#define _ASM_SPEEDSTEP_H + +/* Magic value used to locate speedstep configuration in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +/* MWAIT coordination I/O base address. This must match + * the \_PR_.CPU0 PM base address. + */ +#define PMB0_BASE 0x510 + +/* PMB1: I/O port that triggers SMI once cores are in the same state. + * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] + */ +#define PMB1_BASE 0x800 + +struct sst_state { + uint8_t dynfsb:1; /* whether this is SLFM */ + uint8_t nonint:1; /* add .5 to ratio */ + uint8_t ratio:6; + uint8_t vid; + uint8_t is_turbo; + uint8_t is_slfm; + uint32_t power; +}; +#define SPEEDSTEP_RATIO_SHIFT 8 +#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) +#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) +#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_VID_MASK 0x3f +#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \ + 0, /* dynfsb won't be read. */ \ + ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ + (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ + >> SPEEDSTEP_RATIO_SHIFT), \ + (val & mask) & SPEEDSTEP_VID_MASK, \ + 0, /* not turbo by default */ \ + 0, /* not slfm by default */ \ + 0 /* power is hardcoded in software. */ \ + }) +#define SPEEDSTEP_ENCODE_STATE(state) ( \ + ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ + ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ + ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ + ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) +#define SPEEDSTEP_DOUBLE_RATIO(state) ( \ + ((uint8_t)(state).ratio * 2) + (state).nonint) + +struct sst_params { + struct sst_state slfm; + struct sst_state min; + struct sst_state max; + struct sst_state turbo; +}; + +/* Looking at core2's spec, the highest normal bus ratio for an eist enabled + processor is 14, the lowest is always 6. This makes 5 states with the + minimal step width of 2. With turbo mode and super LFM we have at most 7. */ +#define SPEEDSTEP_MAX_NORMAL_STATES 5 +#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) +struct sst_table { + /* Table of p-states for EMTTM and ACPI by decreasing performance. */ + struct sst_state states[SPEEDSTEP_MAX_STATES]; + int num_states; +}; + +void speedstep_gen_pstates(struct sst_table *); + +#define SPEEDSTEP_MAX_POWER_YONAH 31000 +#define SPEEDSTEP_MIN_POWER_YONAH 13100 +#define SPEEDSTEP_MAX_POWER_MEROM 35000 +#define SPEEDSTEP_MIN_POWER_MEROM 25000 +#define SPEEDSTEP_SLFM_POWER_MEROM 12000 +#define SPEEDSTEP_MAX_POWER_PENRYN 35000 +#define SPEEDSTEP_MIN_POWER_PENRYN 15000 +#define SPEEDSTEP_SLFM_POWER_PENRYN 12000 + +#endif diff --git a/arch/x86/include/asm/turbo.h b/arch/x86/include/asm/turbo.h new file mode 100644 index 0000000000..bb0d4b4354 --- /dev/null +++ b/arch/x86/include/asm/turbo.h @@ -0,0 +1,31 @@ +/* + * From coreboot file of the same name + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_TURBO_H +#define _ASM_TURBO_H + +#define CPUID_LEAF_PM 6 +#define PM_CAP_TURBO_MODE (1 << 1) + +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define H_MISC_DISABLE_TURBO (1 << 6) + +enum { + TURBO_UNKNOWN, + TURBO_UNAVAILABLE, + TURBO_DISABLED, + TURBO_ENABLED, +}; + +/* Return current turbo state */ +int turbo_get_state(void); + +/* Enable turbo */ +void turbo_enable(void); + +#endif diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h index e9fde88f7d..e272c90eb7 100644 --- a/arch/x86/include/asm/types.h +++ b/arch/x86/include/asm/types.h @@ -36,8 +36,13 @@ typedef unsigned short u16; typedef signed int s32; typedef unsigned int u32; +#if !defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__) typedef signed long long s64; typedef unsigned long long u64; +#else +typedef __INT64_TYPE__ s64; +typedef __UINT64_TYPE__ u64; +#endif #define BITS_PER_LONG 32 diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 9e525dd782..b98afa801d 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -9,8 +9,7 @@ #define _U_BOOT_I386_H_ 1 /* cpu/.../cpu.c */ -int x86_cpu_init_r(void); -int cpu_init_r(void); +int arch_cpu_init(void); int x86_cpu_init_f(void); int cpu_init_f(void); void init_gd(gd_t *id, u64 *gdt_addr); @@ -27,8 +26,8 @@ unsigned long get_tbclk_mhz(void); void timer_set_base(uint64_t base); int pcat_timer_init(void); -/* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */ -int dram_init_f(void); +/* Architecture specific DRAM init */ +int dram_init(void); /* cpu/.../interrupts.c */ int cpu_init_interrupts(void); @@ -36,6 +35,16 @@ int cpu_init_interrupts(void); /* board/.../... */ int dram_init(void); +int cleanup_before_linux(void); +int x86_cleanup_before_linux(void); +void x86_enable_caches(void); +void x86_disable_caches(void); +int x86_init_cache(void); +void reset_cpu(ulong addr); +ulong board_get_usable_ram_top(ulong total_size); +void dram_init_banksize(void); +int default_print_cpuinfo(void); + void setup_pcat_compatibility(void); void isa_unmap_rom(u32 addr); @@ -59,4 +68,8 @@ static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void) void timer_set_tsc_base(uint64_t new_base); uint64_t timer_get_tsc(void); +void quick_ram_check(void); + +#define PCI_VGA_RAM_IMAGE_START 0xc0000 + #endif /* _U_BOOT_I386_H_ */ diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 0f36662688..8e7dd424ca 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -35,10 +35,8 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *); struct boot_params *load_zimage(char *image, unsigned long kernel_size, - void **load_address); + ulong *load_addressp); int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, unsigned long initrd_addr, unsigned long initrd_size); -void boot_zimage(void *setup_base, void *load_address); - #endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index f389767fb9..32d7b98fa6 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -5,41 +5,30 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).o - -COBJS-$(CONFIG_CMD_BOOTM) += bootm.o -COBJS-y += cmd_boot.o -COBJS-y += gcc.o -COBJS-y += init_helpers.o -COBJS-y += interrupts.o -COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o -COBJS-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o -COBJS-$(CONFIG_PCI) += pci_type1.o -COBJS-y += relocate.o -COBJS-y += physmem.o -COBJS-y += string.o -COBJS-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o -COBJS-$(CONFIG_VIDEO_VGA) += video.o -COBJS-$(CONFIG_CMD_ZBOOT) += zimage.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(PREFIXED_LIBGCC): $(NORMAL_LIBGCC) - $(OBJCOPY) $< $@ --prefix-symbols=__normal_ - -$(LIB): $(PREFIXED_LIBGCC) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += bios.o +obj-y += bios_asm.o +obj-y += bios_interrupts.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-y += cmd_boot.o +obj-$(CONFIG_HAVE_FSP) += cmd_hob.o +obj-y += gcc.o +obj-y += init_helpers.o +obj-y += interrupts.o +obj-y += cmd_mtrr.o +obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o +obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o +obj-$(CONFIG_PCI) += pci_type1.o +obj-y += relocate.o +obj-y += physmem.o +obj-$(CONFIG_X86_RAMTEST) += ramtest.o +obj-y += string.o +obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o +obj-$(CONFIG_VIDEO_VGA) += video.o +obj-$(CONFIG_CMD_ZBOOT) += zimage.o + +extra-$(CONFIG_USE_PRIVATE_LIBGCC) := lib.a + +NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name) +OBJCOPYFLAGS := --prefix-symbols=__normal_ +$(obj)/lib.a: $(NORMAL_LIBGCC) FORCE + $(call if_changed,objcopy) diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c new file mode 100644 index 0000000000..70ccf1b0b0 --- /dev/null +++ b/arch/x86/lib/asm-offsets.c @@ -0,0 +1,25 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int main(void) +{ + DEFINE(GD_BIST, offsetof(gd_t, arch.bist)); +#ifdef CONFIG_HAVE_FSP + DEFINE(GD_HOB_LIST, offsetof(gd_t, arch.hob_list)); +#endif + return 0; +} diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c new file mode 100644 index 0000000000..1d75cfc263 --- /dev/null +++ b/arch/x86/lib/bios.c @@ -0,0 +1,350 @@ +/* + * From Coreboot file device/oprom/realmode/x86.c + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bios.h" + +/* Interrupt handlers for each interrupt the ROM can call */ +static int (*int_handler[256])(void); + +/* to have a common register file for interrupt handlers */ +X86EMU_sysEnv _X86EMU_env; + +asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi); + +asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi); + +static void setup_realmode_code(void) +{ + memcpy((void *)REALMODE_BASE, &asm_realmode_code, + asm_realmode_code_size); + + /* Ensure the global pointers are relocated properly. */ + realmode_call = PTR_TO_REAL_MODE(asm_realmode_call); + realmode_interrupt = PTR_TO_REAL_MODE(__realmode_interrupt); + + debug("Real mode stub @%x: %d bytes\n", REALMODE_BASE, + asm_realmode_code_size); +} + +static void setup_rombios(void) +{ + const char date[] = "06/11/99"; + memcpy((void *)0xffff5, &date, 8); + + const char ident[] = "PCI_ISA"; + memcpy((void *)0xfffd9, &ident, 7); + + /* system model: IBM-AT */ + writeb(0xfc, 0xffffe); +} + +static int int_exception_handler(void) +{ + /* compatibility shim */ + struct eregs reg_info = { + .eax = M.x86.R_EAX, + .ecx = M.x86.R_ECX, + .edx = M.x86.R_EDX, + .ebx = M.x86.R_EBX, + .esp = M.x86.R_ESP, + .ebp = M.x86.R_EBP, + .esi = M.x86.R_ESI, + .edi = M.x86.R_EDI, + .vector = M.x86.intno, + .error_code = 0, + .eip = M.x86.R_EIP, + .cs = M.x86.R_CS, + .eflags = M.x86.R_EFLG + }; + struct eregs *regs = ®_info; + + debug("Oops, exception %d while executing option rom\n", regs->vector); + cpu_hlt(); + + return 0; +} + +static int int_unknown_handler(void) +{ + debug("Unsupported software interrupt #0x%x eax 0x%x\n", + M.x86.intno, M.x86.R_EAX); + + return -1; +} + +/* setup interrupt handlers for mainboard */ +void bios_set_interrupt_handler(int intnum, int (*int_func)(void)) +{ + int_handler[intnum] = int_func; +} + +static void setup_interrupt_handlers(void) +{ + int i; + + /* + * The first 16 int_handler functions are not BIOS services, + * but the CPU-generated exceptions ("hardware interrupts") + */ + for (i = 0; i < 0x10; i++) + int_handler[i] = &int_exception_handler; + + /* Mark all other int_handler calls as unknown first */ + for (i = 0x10; i < 0x100; i++) { + /* Skip if bios_set_interrupt_handler() isn't called first */ + if (int_handler[i]) + continue; + + /* + * Now set the default functions that are actually needed + * to initialize the option roms. The board may override + * these with bios_set_interrupt_handler() + */ + switch (i) { + case 0x10: + int_handler[0x10] = &int10_handler; + break; + case 0x12: + int_handler[0x12] = &int12_handler; + break; + case 0x16: + int_handler[0x16] = &int16_handler; + break; + case 0x1a: + int_handler[0x1a] = &int1a_handler; + break; + default: + int_handler[i] = &int_unknown_handler; + break; + } + } +} + +static void write_idt_stub(void *target, u8 intnum) +{ + unsigned char *codeptr; + + codeptr = (unsigned char *)target; + memcpy(codeptr, &__idt_handler, __idt_handler_size); + codeptr[3] = intnum; /* modify int# in the code stub. */ +} + +static void setup_realmode_idt(void) +{ + struct realmode_idt *idts = NULL; + int i; + + /* + * Copy IDT stub code for each interrupt. This might seem wasteful + * but it is really simple + */ + for (i = 0; i < 256; i++) { + idts[i].cs = 0; + idts[i].offset = 0x1000 + (i * __idt_handler_size); + write_idt_stub((void *)((u32)idts[i].offset), i); + } + + /* + * Many option ROMs use the hard coded interrupt entry points in the + * system bios. So install them at the known locations. + */ + + /* int42 is the relocated int10 */ + write_idt_stub((void *)0xff065, 0x42); + /* BIOS Int 11 Handler F000:F84D */ + write_idt_stub((void *)0xff84d, 0x11); + /* BIOS Int 12 Handler F000:F841 */ + write_idt_stub((void *)0xff841, 0x12); + /* BIOS Int 13 Handler F000:EC59 */ + write_idt_stub((void *)0xfec59, 0x13); + /* BIOS Int 14 Handler F000:E739 */ + write_idt_stub((void *)0xfe739, 0x14); + /* BIOS Int 15 Handler F000:F859 */ + write_idt_stub((void *)0xff859, 0x15); + /* BIOS Int 16 Handler F000:E82E */ + write_idt_stub((void *)0xfe82e, 0x16); + /* BIOS Int 17 Handler F000:EFD2 */ + write_idt_stub((void *)0xfefd2, 0x17); + /* ROM BIOS Int 1A Handler F000:FE6E */ + write_idt_stub((void *)0xffe6e, 0x1a); +} + +static u8 vbe_get_mode_info(struct vbe_mode_info *mi) +{ + u16 buffer_seg; + u16 buffer_adr; + char *buffer; + + debug("VBE: Getting information about VESA mode %04x\n", + mi->video_mode); + buffer = PTR_TO_REAL_MODE(asm_realmode_buffer); + buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00; + buffer_adr = ((unsigned long)buffer) & 0xffff; + + realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode, + 0x0000, buffer_seg, buffer_adr); + memcpy(mi->mode_info_block, buffer, sizeof(struct vbe_mode_info)); + mi->valid = true; + + return 0; +} + +static u8 vbe_set_mode(struct vbe_mode_info *mi) +{ + int video_mode = mi->video_mode; + + debug("VBE: Setting VESA mode %#04x\n", video_mode); + /* request linear framebuffer mode */ + video_mode |= (1 << 14); + /* don't clear the framebuffer, we do that later */ + video_mode |= (1 << 15); + realmode_interrupt(0x10, VESA_SET_MODE, video_mode, + 0x0000, 0x0000, 0x0000, 0x0000); + + return 0; +} + +static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) +{ + unsigned char *framebuffer; + + mode_info->video_mode = (1 << 14) | vesa_mode; + vbe_get_mode_info(mode_info); + + framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr; + debug("VBE: resolution: %dx%d@%d\n", + le16_to_cpu(mode_info->vesa.x_resolution), + le16_to_cpu(mode_info->vesa.y_resolution), + mode_info->vesa.bits_per_pixel); + debug("VBE: framebuffer: %p\n", framebuffer); + if (!framebuffer) { + debug("VBE: Mode does not support linear framebuffer\n"); + return; + } + + mode_info->video_mode &= 0x3ff; + vbe_set_mode(mode_info); +} + +void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode, + struct vbe_mode_info *mode_info) +{ + u32 num_dev; + + num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 | + PCI_FUNC(pcidev); + + /* Needed to avoid exceptions in some ROMs */ + interrupt_init(); + + /* Set up some legacy information in the F segment */ + setup_rombios(); + + /* Set up C interrupt handlers */ + setup_interrupt_handlers(); + + /* Set up real-mode IDT */ + setup_realmode_idt(); + + /* Make sure the code is placed. */ + setup_realmode_code(); + + debug("Calling Option ROM at %lx, pci device %#x...", addr, num_dev); + + /* Option ROM entry point is at OPROM start + 3 */ + realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, + 0x0); + debug("done\n"); + + if (vesa_mode != -1) + vbe_set_graphics(vesa_mode, mode_info); +} + +asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses, + u32 edi, u32 esi, u32 ebp, u32 esp, + u32 ebx, u32 edx, u32 ecx, u32 eax, + u32 cs_ip, u16 stackflags) +{ + u32 ip; + u32 cs; + u32 flags; + int ret = 0; + + ip = cs_ip & 0xffff; + cs = cs_ip >> 16; + flags = stackflags; + +#ifdef CONFIG_REALMODE_DEBUG + debug("oprom: INT# 0x%x\n", intnumber); + debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", + eax, ebx, ecx, edx); + debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n", + ebp, esp, edi, esi); + debug("oprom: ip: %04x cs: %04x flags: %08x\n", + ip, cs, flags); + debug("oprom: stackflags = %04x\n", stackflags); +#endif + + /* + * Fetch arguments from the stack and put them to a place + * suitable for the interrupt handlers + */ + M.x86.R_EAX = eax; + M.x86.R_ECX = ecx; + M.x86.R_EDX = edx; + M.x86.R_EBX = ebx; + M.x86.R_ESP = esp; + M.x86.R_EBP = ebp; + M.x86.R_ESI = esi; + M.x86.R_EDI = edi; + M.x86.intno = intnumber; + M.x86.R_EIP = ip; + M.x86.R_CS = cs; + M.x86.R_EFLG = flags; + + /* Call the interrupt handler for this interrupt number */ + ret = int_handler[intnumber](); + + /* + * This code is quite strange... + * + * Put registers back on the stack. The assembler code will pop them + * later. We force (volatile!) changing the values of the parameters + * of this function. We know that they stay alive on the stack after + * we leave this function. + */ + *(volatile u32 *)&eax = M.x86.R_EAX; + *(volatile u32 *)&ecx = M.x86.R_ECX; + *(volatile u32 *)&edx = M.x86.R_EDX; + *(volatile u32 *)&ebx = M.x86.R_EBX; + *(volatile u32 *)&esi = M.x86.R_ESI; + *(volatile u32 *)&edi = M.x86.R_EDI; + flags = M.x86.R_EFLG; + + /* Pass success or error back to our caller via the CARRY flag */ + if (ret) { + flags &= ~1; /* no error: clear carry */ + } else { + debug("int%02x call returned error\n", intnumber); + flags |= 1; /* error: set carry */ + } + *(volatile u16 *)&stackflags = flags; + + return ret; +} diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h new file mode 100644 index 0000000000..668f4b5525 --- /dev/null +++ b/arch/x86/lib/bios.h @@ -0,0 +1,100 @@ +/* + * From Coreboot file device/oprom/realmode/x86.h + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _X86_LIB_BIOS_H +#define _X86_LIB_BIOS_H + +#include + +#define REALMODE_BASE 0x600 + +#ifdef __ASSEMBLY__ + +#define PTR_TO_REAL_MODE(x) (x - asm_realmode_code + REALMODE_BASE) + +#else + +/* Convert a symbol address to our real mode area */ +#define PTR_TO_REAL_MODE(sym)\ + (void *)(REALMODE_BASE + ((char *)&(sym) - (char *)&asm_realmode_code)) + +/* + * The following symbols cannot be used directly. They need to be fixed up + * to point to the correct address location after the code has been copied + * to REALMODE_BASE. Absolute symbols are not used because those symbols are + * relocated by U-Boot. + */ +extern unsigned char asm_realmode_call, __realmode_interrupt; +extern unsigned char asm_realmode_buffer; + +#define DOWNTO8(A) \ + union { \ + struct { \ + union { \ + struct { \ + uint8_t A##l; \ + uint8_t A##h; \ + } __packed; \ + uint16_t A##x; \ + } __packed; \ + uint16_t h##A##x; \ + } __packed; \ + uint32_t e##A##x; \ + } __packed; + +#define DOWNTO16(A) \ + union { \ + struct { \ + uint16_t A; \ + uint16_t h##A; \ + } __packed; \ + uint32_t e##A; \ + } __packed; + +struct eregs { + DOWNTO8(a); + DOWNTO8(c); + DOWNTO8(d); + DOWNTO8(b); + DOWNTO16(sp); + DOWNTO16(bp); + DOWNTO16(si); + DOWNTO16(di); + uint32_t vector; + uint32_t error_code; + uint32_t eip; + uint32_t cs; + uint32_t eflags; +}; + +struct realmode_idt { + u16 offset, cs; +}; + +void x86_exception(struct eregs *info); + +/* From x86_asm.S */ +extern unsigned char __idt_handler; +extern unsigned int __idt_handler_size; +extern unsigned char asm_realmode_code; +extern unsigned int asm_realmode_code_size; + +asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi); + +asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi); + +int int10_handler(void); +int int12_handler(void); +int int16_handler(void); +int int1a_handler(void); +#endif /*__ASSEMBLY__ */ + +#endif diff --git a/arch/x86/lib/bios_asm.S b/arch/x86/lib/bios_asm.S new file mode 100644 index 0000000000..4faa70e314 --- /dev/null +++ b/arch/x86/lib/bios_asm.S @@ -0,0 +1,281 @@ +/* + * From coreboot x86_asm.S, cleaned up substantially + * + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include "bios.h" + +#define SEG(segment) $segment * X86_GDT_ENTRY_SIZE + +/* + * This is the interrupt handler stub code. It gets copied to the IDT and + * to some fixed addresses in the F segment. Before the code can used, + * it gets patched up by the C function copying it: byte 3 (the $0 in + * movb $0, %al) is overwritten with the interrupt numbers. + */ + + .code16 + .globl __idt_handler +__idt_handler: + pushal + movb $0, %al /* This instruction gets modified */ + ljmp $0, $__interrupt_handler_16bit + .globl __idt_handler_size +__idt_handler_size: + .long . - __idt_handler + +.macro setup_registers + /* initial register values */ + movl 44(%ebp), %eax + movl %eax, __registers + 0 /* eax */ + movl 48(%ebp), %eax + movl %eax, __registers + 4 /* ebx */ + movl 52(%ebp), %eax + movl %eax, __registers + 8 /* ecx */ + movl 56(%ebp), %eax + movl %eax, __registers + 12 /* edx */ + movl 60(%ebp), %eax + movl %eax, __registers + 16 /* esi */ + movl 64(%ebp), %eax + movl %eax, __registers + 20 /* edi */ +.endm + +.macro enter_real_mode + /* Activate the right segment descriptor real mode. */ + ljmp SEG(X86_GDT_ENTRY_16BIT_CS), $PTR_TO_REAL_MODE(1f) +1: +.code16 + /* + * Load the segment registers with properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. + */ + mov SEG(X86_GDT_ENTRY_16BIT_DS), %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss + + /* Turn off protection */ + movl %cr0, %eax + andl $~X86_CR0_PE, %eax + movl %eax, %cr0 + + /* Now really going into real mode */ + ljmp $0, $PTR_TO_REAL_MODE(1f) +1: + /* + * Set up a stack: Put the stack at the end of page zero. That way + * we can easily share it between real and protected, since the + * 16-bit ESP at segment 0 will work for any case. + */ + mov $0x0, %ax + mov %ax, %ss + + /* Load 16 bit IDT */ + xor %ax, %ax + mov %ax, %ds + lidt __realmode_idt + +.endm + +.macro prepare_for_irom + movl $0x1000, %eax + movl %eax, %esp + + /* Initialise registers for option rom lcall */ + movl __registers + 0, %eax + movl __registers + 4, %ebx + movl __registers + 8, %ecx + movl __registers + 12, %edx + movl __registers + 16, %esi + movl __registers + 20, %edi + + /* Set all segments to 0x0000, ds to 0x0040 */ + push %ax + xor %ax, %ax + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov SEG(X86_GDT_ENTRY_16BIT_FLAT_DS), %ax + mov %ax, %ds + pop %ax + +.endm + +.macro enter_protected_mode + /* Go back to protected mode */ + movl %cr0, %eax + orl $X86_CR0_PE, %eax + movl %eax, %cr0 + + /* Now that we are in protected mode jump to a 32 bit code segment */ + data32 ljmp SEG(X86_GDT_ENTRY_32BIT_CS), $PTR_TO_REAL_MODE(1f) +1: + .code32 + mov SEG(X86_GDT_ENTRY_32BIT_DS), %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %gs + mov %ax, %ss + mov SEG(X86_GDT_ENTRY_32BIT_FS), %ax + mov %ax, %fs + + /* restore proper idt */ + lidt idt_ptr +.endm + +/* + * In order to be independent of U-Boot's position in RAM we relocate a part + * of the code to the first megabyte of RAM, so the CPU can use it in + * real-mode. This code lives at asm_realmode_code. + */ + .globl asm_realmode_code +asm_realmode_code: + +/* Realmode IDT pointer structure. */ +__realmode_idt = PTR_TO_REAL_MODE(.) + .word 1023 /* 16 bit limit */ + .long 0 /* 24 bit base */ + .word 0 + +/* Preserve old stack */ +__stack = PTR_TO_REAL_MODE(.) + .long 0 + +/* Register store for realmode_call and realmode_interrupt */ +__registers = PTR_TO_REAL_MODE(.) + .long 0 /* 0 - EAX */ + .long 0 /* 4 - EBX */ + .long 0 /* 8 - ECX */ + .long 0 /* 12 - EDX */ + .long 0 /* 16 - ESI */ + .long 0 /* 20 - EDI */ + +/* 256 byte buffer, used by int10 */ + .globl asm_realmode_buffer +asm_realmode_buffer: + .skip 256 + + .code32 + .globl asm_realmode_call +asm_realmode_call: + /* save all registers to the stack */ + pusha + pushf + movl %esp, __stack + movl %esp, %ebp + + /* + * This function is called with regparm=0 and we have to skip the + * 36 bytes from pushf+pusha. Hence start at 40. + * Set up our call instruction. + */ + movl 40(%ebp), %eax + mov %ax, __lcall_instr + 1 + andl $0xffff0000, %eax + shrl $4, %eax + mov %ax, __lcall_instr + 3 + + wbinvd + + setup_registers + enter_real_mode + prepare_for_irom + +__lcall_instr = PTR_TO_REAL_MODE(.) + .byte 0x9a + .word 0x0000, 0x0000 + + enter_protected_mode + + /* restore stack pointer, eflags and register values and exit */ + movl __stack, %esp + popf + popa + ret + + .globl __realmode_interrupt +__realmode_interrupt: + /* save all registers to the stack and store the stack pointer */ + pusha + pushf + movl %esp, __stack + movl %esp, %ebp + + /* + * This function is called with regparm=0 and we have to skip the + * 36 bytes from pushf+pusha. Hence start at 40. + * Prepare interrupt calling code. + */ + movl 40(%ebp), %eax + movb %al, __intXX_instr + 1 /* intno */ + + setup_registers + enter_real_mode + prepare_for_irom + +__intXX_instr = PTR_TO_REAL_MODE(.) + .byte 0xcd, 0x00 /* This becomes intXX */ + + enter_protected_mode + + /* restore stack pointer, eflags and register values and exit */ + movl __stack, %esp + popf + popa + ret + +/* + * This is the 16-bit interrupt entry point called by the IDT stub code. + * + * Before this code code is called, %eax is pushed to the stack, and the + * interrupt number is loaded into %al. On return this function cleans up + * for its caller. + */ + .code16 +__interrupt_handler_16bit = PTR_TO_REAL_MODE(.) + push %ds + push %es + push %fs + push %gs + + /* Clear DF to not break ABI assumptions */ + cld + + /* + * Clean up the interrupt number. We could do this in the stub, but + * it would cost two more bytes per stub entry. + */ + andl $0xff, %eax + pushl %eax /* ... and make it the first parameter */ + + enter_protected_mode + + /* Call the C interrupt handler */ + movl $interrupt_handler, %eax + call *%eax + + enter_real_mode + + /* + * Restore all registers, including those manipulated by the C + * handler + */ + popl %eax + pop %gs + pop %fs + pop %es + pop %ds + popal + iret + + .globl asm_realmode_code_size +asm_realmode_code_size: + .long . - asm_realmode_code diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c new file mode 100644 index 0000000000..b0e2ecbbca --- /dev/null +++ b/arch/x86/lib/bios_interrupts.c @@ -0,0 +1,217 @@ +/* + * From Coreboot + * + * Copyright (C) 2001 Ronald G. Minnich + * Copyright (C) 2005 Nick.Barker9@btinternet.com + * Copyright (C) 2007-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include "bios_emul.h" + +/* errors go in AH. Just set these up so that word assigns will work */ +enum { + PCIBIOS_SUCCESSFUL = 0x0000, + PCIBIOS_UNSUPPORTED = 0x8100, + PCIBIOS_BADVENDOR = 0x8300, + PCIBIOS_NODEV = 0x8600, + PCIBIOS_BADREG = 0x8700 +}; + +int int10_handler(void) +{ + static u8 cursor_row, cursor_col; + int res = 0; + + switch ((M.x86.R_EAX & 0xff00) >> 8) { + case 0x01: /* Set cursor shape */ + res = 1; + break; + case 0x02: /* Set cursor position */ + if (cursor_row != ((M.x86.R_EDX >> 8) & 0xff) || + cursor_col >= (M.x86.R_EDX & 0xff)) { + debug("\n"); + } + cursor_row = (M.x86.R_EDX >> 8) & 0xff; + cursor_col = M.x86.R_EDX & 0xff; + res = 1; + break; + case 0x03: /* Get cursor position */ + M.x86.R_EAX &= 0x00ff; + M.x86.R_ECX = 0x0607; + M.x86.R_EDX = (cursor_row << 8) | cursor_col; + res = 1; + break; + case 0x06: /* Scroll up */ + debug("\n"); + res = 1; + break; + case 0x08: /* Get Character and Mode at Cursor Position */ + M.x86.R_EAX = 0x0f00 | 'A'; /* White on black 'A' */ + res = 1; + break; + case 0x09: /* Write Character and attribute */ + case 0x0e: /* Write Character */ + debug("%c", M.x86.R_EAX & 0xff); + res = 1; + break; + case 0x0f: /* Get video mode */ + M.x86.R_EAX = 0x5002; /*80 x 25 */ + M.x86.R_EBX &= 0x00ff; + res = 1; + break; + default: + printf("Unknown INT10 function %04x\n", M.x86.R_EAX & 0xffff); + break; + } + return res; +} + +int int12_handler(void) +{ + M.x86.R_EAX = 64 * 1024; + return 1; +} + +int int16_handler(void) +{ + int res = 0; + + switch ((M.x86.R_EAX & 0xff00) >> 8) { + case 0x00: /* Check for Keystroke */ + M.x86.R_EAX = 0x6120; /* Space Bar, Space */ + res = 1; + break; + case 0x01: /* Check for Keystroke */ + M.x86.R_EFLG |= 1 << 6; /* Zero Flag set (no key available) */ + res = 1; + break; + default: + printf("Unknown INT16 function %04x\n", M.x86.R_EAX & 0xffff); + +break; + } + return res; +} + +#define PCI_CONFIG_SPACE_TYPE1 (1 << 0) +#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4) + +int int1a_handler(void) +{ + unsigned short func = (unsigned short)M.x86.R_EAX; + int retval = 1; + unsigned short devid, vendorid, devfn; + /* Use short to get rid of gabage in upper half of 32-bit register */ + short devindex; + unsigned char bus; + pci_dev_t dev; + u32 dword; + u16 word; + u8 byte, reg; + + switch (func) { + case 0xb101: /* PCIBIOS Check */ + M.x86.R_EDX = 0x20494350; /* ' ICP' */ + M.x86.R_EAX &= 0xffff0000; /* Clear AH / AL */ + M.x86.R_EAX |= PCI_CONFIG_SPACE_TYPE1 | + PCI_SPECIAL_CYCLE_TYPE1; + /* + * last bus in the system. Hard code to 255 for now. + * dev_enumerate() does not seem to tell us (publically) + */ + M.x86.R_ECX = 0xff; + M.x86.R_EDI = 0x00000000; /* protected mode entry */ + retval = 1; + break; + case 0xb102: /* Find Device */ + devid = M.x86.R_ECX; + vendorid = M.x86.R_EDX; + devindex = M.x86.R_ESI; + dev = pci_find_device(vendorid, devid, devindex); + if (dev != -1) { + unsigned short busdevfn; + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; + /* + * busnum is an unsigned char; + * devfn is an int, so we mask it off. + */ + busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 | + PCI_FUNC(dev); + debug("0x%x: return 0x%x\n", func, busdevfn); + M.x86.R_EBX = busdevfn; + retval = 1; + } else { + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_NODEV; + retval = 0; + } + break; + case 0xb10a: /* Read Config Dword */ + case 0xb109: /* Read Config Word */ + case 0xb108: /* Read Config Byte */ + case 0xb10d: /* Write Config Dword */ + case 0xb10c: /* Write Config Word */ + case 0xb10b: /* Write Config Byte */ + devfn = M.x86.R_EBX & 0xff; + bus = M.x86.R_EBX >> 8; + reg = M.x86.R_EDI; + dev = PCI_BDF(bus, devfn >> 3, devfn & 7); + if (!dev) { + debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, + bus, devfn); + /* Or are we supposed to return PCIBIOS_NODEV? */ + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_BADREG; + retval = 0; + return retval; + } + switch (func) { + case 0xb108: /* Read Config Byte */ + byte = pci_read_config8(dev, reg); + M.x86.R_ECX = byte; + break; + case 0xb109: /* Read Config Word */ + word = pci_read_config16(dev, reg); + M.x86.R_ECX = word; + break; + case 0xb10a: /* Read Config Dword */ + dword = pci_read_config32(dev, reg); + M.x86.R_ECX = dword; + break; + case 0xb10b: /* Write Config Byte */ + byte = M.x86.R_ECX; + pci_write_config8(dev, reg, byte); + break; + case 0xb10c: /* Write Config Word */ + word = M.x86.R_ECX; + pci_write_config16(dev, reg, word); + break; + case 0xb10d: /* Write Config Dword */ + dword = M.x86.R_ECX; + pci_write_config32(dev, reg, dword); + break; + } + +#ifdef CONFIG_REALMODE_DEBUG + debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, + bus, devfn, reg, M.x86.R_ECX); +#endif + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; + retval = 1; + break; + default: + printf("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_UNSUPPORTED; + retval = 0; + break; + } + + return retval; +} diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index ff158dd6a9..86030cf52a 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -10,80 +10,195 @@ #include #include +#include +#include #include #include #include +#include #include #include +#ifdef CONFIG_SYS_COREBOOT +#include +#endif #define COMMAND_LINE_OFFSET 0x9000 -/*cmd_boot.c*/ -int do_bootm_linux(int flag, int argc, char * const argv[], - bootm_headers_t *images) +/* + * Implement a weak default function for boards that optionally + * need to clean up the system before jumping to the kernel. + */ +__weak void board_final_cleanup(void) { - struct boot_params *base_ptr = NULL; - ulong os_data, os_len; - image_header_t *hdr; - void *load_address; +} -#if defined(CONFIG_FIT) - const void *data; - size_t len; +void bootm_announce_and_cleanup(void) +{ + printf("\nStarting kernel ...\n\n"); + +#ifdef CONFIG_SYS_COREBOOT + timestamp_add_now(TS_U_BOOT_START_KERNEL); #endif + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); +#ifdef CONFIG_BOOTSTAGE_REPORT + bootstage_report(); +#endif + board_final_cleanup(); +} - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; +#if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) +int arch_fixup_memory_node(void *blob) +{ + bd_t *bd = gd->bd; + int bank; + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = bd->bi_dram[bank].start; + size[bank] = bd->bi_dram[bank].size; + } + + return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); +} +#endif + +/* Subcommand: PREP */ +static int boot_prep_linux(bootm_headers_t *images) +{ + char *cmd_line_dest = NULL; + image_header_t *hdr; + int is_zimage = 0; + void *data = NULL; + size_t len; + int ret; + +#ifdef CONFIG_OF_LIBFDT + if (images->ft_len) { + debug("using: FDT\n"); + if (image_setup_linux(images)) { + puts("FDT creation failed! hanging..."); + hang(); + } + } +#endif if (images->legacy_hdr_valid) { hdr = images->legacy_hdr_os; if (image_check_type(hdr, IH_TYPE_MULTI)) { + ulong os_data, os_len; + /* if multi-part image, we need to get first subimage */ image_multi_getimg(hdr, 0, &os_data, &os_len); + data = (void *)os_data; + len = os_len; } else { /* otherwise get image data */ - os_data = image_get_data(hdr); - os_len = image_get_data_size(hdr); + data = (void *)image_get_data(hdr); + len = image_get_data_size(hdr); } + is_zimage = 1; #if defined(CONFIG_FIT) - } else if (images->fit_uname_os) { - int ret; - + } else if (images->fit_uname_os && is_zimage) { ret = fit_image_get_data(images->fit_hdr_os, - images->fit_noffset_os, &data, &len); + images->fit_noffset_os, + (const void **)&data, &len); if (ret) { puts("Can't get image data/size!\n"); goto error; } - os_data = (ulong)data; - os_len = (ulong)len; + is_zimage = 1; #endif - } else { - puts("Could not find kernel image!\n"); - goto error; } -#ifdef CONFIG_CMD_ZBOOT - base_ptr = load_zimage((void *)os_data, os_len, &load_address); -#endif + if (is_zimage) { + ulong load_address; + char *base_ptr; - if (NULL == base_ptr) { - printf("## Kernel loading failed ...\n"); + base_ptr = (char *)load_zimage(data, len, &load_address); + images->os.load = load_address; + cmd_line_dest = base_ptr + COMMAND_LINE_OFFSET; + images->ep = (ulong)base_ptr; + } else if (images->ep) { + cmd_line_dest = (void *)images->ep + COMMAND_LINE_OFFSET; + } else { + printf("## Kernel loading failed (missing x86 kernel setup) ...\n"); goto error; } - if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET, + printf("Setup at %#08lx\n", images->ep); + ret = setup_zimage((void *)images->ep, cmd_line_dest, 0, images->rd_start, - images->rd_end - images->rd_start)) { + images->rd_end - images->rd_start); + + if (ret) { printf("## Setting up boot parameters failed ...\n"); - goto error; + return 1; } - boot_zimage(base_ptr, load_address); - /* does not return */ + return 0; error: return 1; } + +int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit) +{ + bootm_announce_and_cleanup(); + +#ifdef CONFIG_SYS_COREBOOT + timestamp_add_now(TS_U_BOOT_START_KERNEL); +#endif + if (image_64bit) { + if (!cpu_has_64bit()) { + puts("Cannot boot 64-bit kernel on 32-bit machine\n"); + return -EFAULT; + } + return cpu_jump_to_64bit(setup_base, load_address); + } else { + /* + * Set %ebx, %ebp, and %edi to 0, %esi to point to the + * boot_params structure, and then jump to the kernel. We + * assume that %cs is 0x10, 4GB flat, and read/execute, and + * the data segments are 0x18, 4GB flat, and read/write. + * U-boot is setting them up that way for itself in + * arch/i386/cpu/cpu.c. + */ + __asm__ __volatile__ ( + "movl $0, %%ebp\n" + "cli\n" + "jmp *%[kernel_entry]\n" + :: [kernel_entry]"a"(load_address), + [boot_params] "S"(setup_base), + "b"(0), "D"(0) + ); + } + + /* We can't get to here */ + return -EFAULT; +} + +/* Subcommand: GO */ +static int boot_jump_linux(bootm_headers_t *images) +{ + debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n", + images->ep, images->os.load); + + return boot_linux_kernel(images->ep, images->os.load, + images->os.arch == IH_ARCH_X86_64); +} + +int do_bootm_linux(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + /* No need for those on x86 */ + if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) + return -1; + + if (flag & BOOTM_STATE_OS_PREP) + return boot_prep_linux(images); + + if (flag & BOOTM_STATE_OS_GO) + return boot_jump_linux(images); + + return boot_jump_linux(images); +} diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c new file mode 100644 index 0000000000..a0ef037da1 --- /dev/null +++ b/arch/x86/lib/cmd_hob.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static char *hob_type[] = { + "reserved", + "Hand-off", + "Memory Allocation", + "Resource Descriptor", + "GUID Extension", + "Firmware Volume", + "CPU", + "Memory Pool", + "reserved", + "Firmware Volume 2", + "Load PEIM Unused", + "UEFI Capsule", +}; + +int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const struct hob_header *hdr; + uint type; + char *desc; + int i = 0; + + hdr = gd->arch.hob_list; + + printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr); + + printf("No. | Address | Type | Length in Bytes\n"); + printf("----|----------|---------------------|----------------\n"); + while (!end_of_hob(hdr)) { + printf("%-3d | %08x | ", i, (unsigned int)hdr); + type = hdr->type; + if (type == HOB_TYPE_UNUSED) + desc = "*Unused*"; + else if (type == HOB_TYPE_EOH) + desc = "*END OF HOB*"; + else if (type >= 0 && type <= ARRAY_SIZE(hob_type)) + desc = hob_type[type]; + else + desc = "*Invalid Type*"; + printf("%-19s | %-15d\n", desc, hdr->len); + hdr = get_next_hob(hdr); + i++; + } + + return 0; +} + +U_BOOT_CMD( + hob, 1, 1, do_hob, + "print Firmware Support Package (FSP) Hand-Off Block information", + "" +); diff --git a/arch/x86/lib/cmd_mtrr.c b/arch/x86/lib/cmd_mtrr.c new file mode 100644 index 0000000000..7e0506b75d --- /dev/null +++ b/arch/x86/lib/cmd_mtrr.c @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { + "Uncacheable", + "Combine", + "2", + "3", + "Through", + "Protect", + "Back", +}; + +static int do_mtrr_list(void) +{ + int i; + + printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", + "Mask ||", "Size ||"); + for (i = 0; i < MTRR_COUNT; i++) { + const char *type = "Invalid"; + uint64_t base, mask, size; + bool valid; + + base = native_read_msr(MTRR_PHYS_BASE_MSR(i)); + mask = native_read_msr(MTRR_PHYS_MASK_MSR(i)); + size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); + size |= (1 << 12) - 1; + size += 1; + valid = mask & MTRR_PHYS_MASK_VALID; + type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; + printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, + valid ? "Y" : "N", type, base, mask, size); + } + + return 0; +} + +static int do_mtrr_set(uint reg, int argc, char * const argv[]) +{ + const char *typename = argv[0]; + struct mtrr_state state; + uint32_t start, size; + uint64_t base, mask; + int i, type = -1; + bool valid; + + if (argc < 3) + return CMD_RET_USAGE; + for (i = 0; i < MTRR_TYPE_COUNT; i++) { + if (*typename == *mtrr_type_name[i]) + type = i; + } + if (type == -1) { + printf("Invalid type name %s\n", typename); + return CMD_RET_USAGE; + } + start = simple_strtoul(argv[1], NULL, 16); + size = simple_strtoul(argv[2], NULL, 16); + + base = start | type; + valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID; + mask = ~((uint64_t)size - 1); + mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; + if (valid) + mask |= MTRR_PHYS_MASK_VALID; + + printf("base=%llx, mask=%llx\n", base, mask); + mtrr_open(&state); + wrmsrl(MTRR_PHYS_BASE_MSR(reg), base); + wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); + mtrr_close(&state); + + return 0; +} + +static int mtrr_set_valid(int reg, bool valid) +{ + struct mtrr_state state; + uint64_t mask; + + mtrr_open(&state); + mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg)); + if (valid) + mask |= MTRR_PHYS_MASK_VALID; + else + mask &= ~MTRR_PHYS_MASK_VALID; + wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); + mtrr_close(&state); + + return 0; +} + +static int do_mtrr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *cmd; + uint reg; + + cmd = argv[1]; + if (argc < 2 || *cmd == 'l') + return do_mtrr_list(); + argc -= 2; + argv += 2; + if (argc <= 0) + return CMD_RET_USAGE; + reg = simple_strtoul(argv[0], NULL, 16); + if (reg >= MTRR_COUNT) { + printf("Invalid register number\n"); + return CMD_RET_USAGE; + } + if (*cmd == 'e') + return mtrr_set_valid(reg, true); + else if (*cmd == 'd') + return mtrr_set_valid(reg, false); + else if (*cmd == 's') + return do_mtrr_set(reg, argc - 1, argv + 1); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + mtrr, 6, 1, do_mtrr, + "Use x86 memory type range registers (32-bit only)", + "[list] - list current registers\n" + "set - set a register\n" + "\t is Uncacheable, Combine, Through, Protect, Back\n" + "disable - disable a register\n" + "ensable - enable a register" +); diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 582c0ffe24..5097ca274a 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -66,6 +68,14 @@ int calculate_relocation_address(void) int init_cache_f_r(void) { +#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP) + int ret; + + ret = mtrr_commit(false); + /* If MTRR MSR is not implemented by the processor, just ignore it */ + if (ret && ret != -ENOSYS) + return ret; +#endif /* Initialise the CPU cache(s) */ return init_cache(); } @@ -87,30 +97,3 @@ int init_func_spi(void) puts("ready\n"); return 0; } - -int find_fdt(void) -{ -#ifdef CONFIG_OF_EMBED - /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; -#elif defined CONFIG_OF_SEPARATE - /* FDT is at end of image */ - gd->fdt_blob = (ulong *)&_end; -#endif - /* Allow the early environment to override the fdt address */ - gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, - (uintptr_t)gd->fdt_blob); - - return 0; -} - -int prepare_fdt(void) -{ - /* For now, put this check after the console is ready */ - if (fdtdec_prepare_fdt()) { - panic("** CONFIG_OF_CONTROL defined but no FDT - please see " - "doc/README.fdt-control"); - } - - return 0; -} diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index 6bb22d25e8..146ad11fb5 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -130,7 +130,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Interrupt-Information:\n"); printf("Nr Routine Arg Count\n"); - for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { + for (irq = 0; irq < CONFIG_SYS_NUM_IRQS; irq++) { if (irq_handlers[irq].handler != NULL) { printf("%02d %08lx %08lx %d\n", irq, diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index 4c86f7fc6a..a9af87e4ce 100644 --- a/arch/x86/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -24,12 +24,10 @@ #error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined" #endif -int interrupt_init(void) +int i8259_init(void) { u8 i; - disable_interrupts(); - /* Mask all interrupts */ outb(0xff, MASTER_PIC + IMR); outb(0xff, SLAVE_PIC + IMR); @@ -62,7 +60,8 @@ int interrupt_init(void) */ unmask_irq(2); - enable_interrupts(); + /* Interrupt 9 should be level triggered (SCI). The OS might do this */ + configure_irq_trigger(9, true); return 0; } @@ -114,3 +113,38 @@ void specific_eoi(int irq) outb(OCW2_SEOI | irq, MASTER_PIC + OCW2); } + +#define ELCR1 0x4d0 +#define ELCR2 0x4d1 + +void configure_irq_trigger(int int_num, bool is_level_triggered) +{ + u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8); + + debug("%s: current interrupts are 0x%x\n", __func__, int_bits); + if (is_level_triggered) + int_bits |= (1 << int_num); + else + int_bits &= ~(1 << int_num); + + /* Write new values */ + debug("%s: try to set interrupts 0x%x\n", __func__, int_bits); + outb((u8)(int_bits & 0xff), ELCR1); + outb((u8)(int_bits >> 8), ELCR2); + +#ifdef PARANOID_IRQ_TRIGGERS + /* + * Try reading back the new values. This seems like an error but is + * not + */ + if (inb(ELCR1) != (int_bits & 0xff)) { + printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (int_bits & 0xff), inb(ELCR1)); + } + + if (inb(ELCR2) != (int_bits >> 8)) { + printf("%s: higher order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (int_bits>>8), inb(ELCR2)); + } +#endif +} diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index 59b3fe977d..c3c709ec07 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -10,6 +10,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -112,41 +113,13 @@ static void x86_phys_enter_paging(void) x86_phys_map_page(page_addr, page_addr, 0); } - /* Turn on paging */ - __asm__ __volatile__( - /* Load the page table address */ - "movl %0, %%cr3\n\t" - /* Enable pae */ - "movl %%cr4, %%eax\n\t" - "orl $0x00000020, %%eax\n\t" - "movl %%eax, %%cr4\n\t" - /* Enable paging */ - "movl %%cr0, %%eax\n\t" - "orl $0x80000000, %%eax\n\t" - "movl %%eax, %%cr0\n\t" - : - : "r" (pdpt) - : "eax" - ); + cpu_enable_paging_pae((ulong)pdpt); } /* Disable paging and PAE mode. */ static void x86_phys_exit_paging(void) { - /* Turn off paging */ - __asm__ __volatile__ ( - /* Disable paging */ - "movl %%cr0, %%eax\n\t" - "andl $0x7fffffff, %%eax\n\t" - "movl %%eax, %%cr0\n\t" - /* Disable pae */ - "movl %%cr4, %%eax\n\t" - "andl $0xffffffdf, %%eax\n\t" - "movl %%eax, %%cr4\n\t" - : - : - : "eax" - ); + cpu_disable_paging_pae(); } /* @@ -189,7 +162,7 @@ phys_addr_t arch_phys_memset(phys_addr_t start, int c, phys_size_t size) /* Handle memory below 4GB. */ if (start <= max_addr) { - phys_size_t low_size = MIN(max_addr + 1 - start, size); + phys_size_t low_size = min(max_addr + 1 - start, size); void *start_ptr = (void *)(uintptr_t)start; assert(((phys_addr_t)(uintptr_t)start) == start); @@ -208,7 +181,7 @@ phys_addr_t arch_phys_memset(phys_addr_t start, int c, phys_size_t size) /* Handle the first partial page. */ if (offset) { phys_addr_t end = - MIN(map_addr + LARGE_PAGE_SIZE, start + size); + min(map_addr + LARGE_PAGE_SIZE, start + size); phys_size_t cur_size = end - start; x86_phys_memset_page(map_addr, offset, c, cur_size); size -= cur_size; diff --git a/arch/x86/lib/ramtest.c b/arch/x86/lib/ramtest.c new file mode 100644 index 0000000000..c21be03848 --- /dev/null +++ b/arch/x86/lib/ramtest.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot src/lib/ramtest.c + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +static void write_phys(unsigned long addr, u32 value) +{ +#if CONFIG_SSE2 + asm volatile( + "movnti %1, (%0)" + : /* outputs */ + : "r" (addr), "r" (value) /* inputs */ + : /* clobbers */ + ); +#else + writel(value, addr); +#endif +} + +static u32 read_phys(unsigned long addr) +{ + return readl(addr); +} + +static void phys_memory_barrier(void) +{ +#if CONFIG_SSE2 + /* Needed for movnti */ + asm volatile( + "sfence" + : + : + : "memory" + ); +#else + asm volatile("" + : + : + : "memory"); +#endif +} + +void quick_ram_check(void) +{ + int fail = 0; + u32 backup; + + backup = read_phys(CONFIG_RAMBASE); + write_phys(CONFIG_RAMBASE, 0x55555555); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0x55555555) + fail = 1; + write_phys(CONFIG_RAMBASE, 0xaaaaaaaa); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa) + fail = 1; + write_phys(CONFIG_RAMBASE, 0x00000000); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0x00000000) + fail = 1; + write_phys(CONFIG_RAMBASE, 0xffffffff); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0xffffffff) + fail = 1; + + write_phys(CONFIG_RAMBASE, backup); + if (fail) { + post_code(POST_RAM_FAILURE); + panic("RAM INIT FAILURE!\n"); + } + phys_memory_barrier(); +} diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index 526daaf93a..b33586b54c 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -75,6 +76,9 @@ int do_elf_reloc_fixups(void) /* The size of the region of u-boot that runs out of RAM. */ uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; + if (re_src == re_end) + panic("No relocation data"); + do { /* Get the location from the relocation entry */ offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; @@ -94,7 +98,7 @@ int do_elf_reloc_fixups(void) *offset_ptr_ram += gd->reloc_off; } else { debug(" %p: rom reloc %x, ram %p, value %x," - " limit %lx\n", re_src, + " limit %" PRIXPTR "\n", re_src, re_src->r_offset, offset_ptr_ram, *offset_ptr_ram, CONFIG_SYS_TEXT_BASE + size); diff --git a/arch/x86/lib/string.c b/arch/x86/lib/string.c index a1656ccfe7..6c66431ed9 100644 --- a/arch/x86/lib/string.c +++ b/arch/x86/lib/string.c @@ -8,9 +8,9 @@ /* From glibc-2.14, sysdeps/i386/memset.c */ -#include -#include #include +#include +#include typedef uint32_t op_t; diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c index 8b38702ef5..7f5ba2ca6f 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/arch/x86/lib/tsc_timer.c @@ -1,6 +1,9 @@ /* * Copyright (c) 2012 The Chromium OS Authors. * + * TSC calibration codes are adapted from Linux kernel + * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,8 +15,269 @@ #include #include +/* CPU reference clock frequency: in KHz */ +#define FREQ_83 83200 +#define FREQ_100 99840 +#define FREQ_133 133200 +#define FREQ_166 166400 + +#define MAX_NUM_FREQS 8 + DECLARE_GLOBAL_DATA_PTR; +/* + * According to Intel 64 and IA-32 System Programming Guide, + * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be + * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. + * Unfortunately some Intel Atom SoCs aren't quite compliant to this, + * so we need manually differentiate SoC families. This is what the + * field msr_plat does. + */ +struct freq_desc { + u8 x86_family; /* CPU family */ + u8 x86_model; /* model */ + /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */ + u8 msr_plat; + u32 freqs[MAX_NUM_FREQS]; +}; + +static struct freq_desc freq_desc_tables[] = { + /* PNW */ + { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, + /* CLV+ */ + { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, + /* TNG */ + { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } }, + /* VLV2 */ + { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } }, + /* Ivybridge */ + { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } }, + /* ANN */ + { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, +}; + +static int match_cpu(u8 family, u8 model) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) { + if ((family == freq_desc_tables[i].x86_family) && + (model == freq_desc_tables[i].x86_model)) + return i; + } + + return -1; +} + +/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */ +#define id_to_freq(cpu_index, freq_id) \ + (freq_desc_tables[cpu_index].freqs[freq_id]) + +/* + * Do MSR calibration only for known/supported CPUs. + * + * Returns the calibration value or 0 if MSR calibration failed. + */ +static unsigned long __maybe_unused try_msr_calibrate_tsc(void) +{ + u32 lo, hi, ratio, freq_id, freq; + unsigned long res; + int cpu_index; + + cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model); + if (cpu_index < 0) + return 0; + + if (freq_desc_tables[cpu_index].msr_plat) { + rdmsr(MSR_PLATFORM_INFO, lo, hi); + ratio = (lo >> 8) & 0x1f; + } else { + rdmsr(MSR_IA32_PERF_STATUS, lo, hi); + ratio = (hi >> 8) & 0x1f; + } + debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); + + if (!ratio) + goto fail; + + if (freq_desc_tables[cpu_index].msr_plat == 2) { + /* TODO: Figure out how best to deal with this */ + freq = FREQ_100; + debug("Using frequency: %u KHz\n", freq); + } else { + /* Get FSB FREQ ID */ + rdmsr(MSR_FSB_FREQ, lo, hi); + freq_id = lo & 0x7; + freq = id_to_freq(cpu_index, freq_id); + debug("Resolved frequency ID: %u, frequency: %u KHz\n", + freq_id, freq); + } + if (!freq) + goto fail; + + /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ + res = freq * ratio / 1000; + debug("TSC runs at %lu MHz\n", res); + + return res; + +fail: + debug("Fast TSC calibration using MSR failed\n"); + return 0; +} + +/* + * This reads the current MSB of the PIT counter, and + * checks if we are running on sufficiently fast and + * non-virtualized hardware. + * + * Our expectations are: + * + * - the PIT is running at roughly 1.19MHz + * + * - each IO is going to take about 1us on real hardware, + * but we allow it to be much faster (by a factor of 10) or + * _slightly_ slower (ie we allow up to a 2us read+counter + * update - anything else implies a unacceptably slow CPU + * or PIT for the fast calibration to work. + * + * - with 256 PIT ticks to read the value, we have 214us to + * see the same MSB (and overhead like doing a single TSC + * read per MSB value etc). + * + * - We're doing 2 reads per loop (LSB, MSB), and we expect + * them each to take about a microsecond on real hardware. + * So we expect a count value of around 100. But we'll be + * generous, and accept anything over 50. + * + * - if the PIT is stuck, and we see *many* more reads, we + * return early (and the next caller of pit_expect_msb() + * then consider it a failure when they don't see the + * next expected value). + * + * These expectations mean that we know that we have seen the + * transition from one expected value to another with a fairly + * high accuracy, and we didn't miss any events. We can thus + * use the TSC value at the transitions to calculate a pretty + * good value for the TSC frequencty. + */ +static inline int pit_verify_msb(unsigned char val) +{ + /* Ignore LSB */ + inb(0x42); + return inb(0x42) == val; +} + +static inline int pit_expect_msb(unsigned char val, u64 *tscp, + unsigned long *deltap) +{ + int count; + u64 tsc = 0, prev_tsc = 0; + + for (count = 0; count < 50000; count++) { + if (!pit_verify_msb(val)) + break; + prev_tsc = tsc; + tsc = rdtsc(); + } + *deltap = rdtsc() - prev_tsc; + *tscp = tsc; + + /* + * We require _some_ success, but the quality control + * will be based on the error terms on the TSC values. + */ + return count > 5; +} + +/* + * How many MSB values do we want to see? We aim for + * a maximum error rate of 500ppm (in practice the + * real error is much smaller), but refuse to spend + * more than 50ms on it. + */ +#define MAX_QUICK_PIT_MS 50 +#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) + +static unsigned long __maybe_unused quick_pit_calibrate(void) +{ + int i; + u64 tsc, delta; + unsigned long d1, d2; + + /* Set the Gate high, disable speaker */ + outb((inb(0x61) & ~0x02) | 0x01, 0x61); + + /* + * Counter 2, mode 0 (one-shot), binary count + * + * NOTE! Mode 2 decrements by two (and then the + * output is flipped each time, giving the same + * final output frequency as a decrement-by-one), + * so mode 0 is much better when looking at the + * individual counts. + */ + outb(0xb0, 0x43); + + /* Start at 0xffff */ + outb(0xff, 0x42); + outb(0xff, 0x42); + + /* + * The PIT starts counting at the next edge, so we + * need to delay for a microsecond. The easiest way + * to do that is to just read back the 16-bit counter + * once from the PIT. + */ + pit_verify_msb(0); + + if (pit_expect_msb(0xff, &tsc, &d1)) { + for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { + if (!pit_expect_msb(0xff-i, &delta, &d2)) + break; + + /* + * Iterate until the error is less than 500 ppm + */ + delta -= tsc; + if (d1+d2 >= delta >> 11) + continue; + + /* + * Check the PIT one more time to verify that + * all TSC reads were stable wrt the PIT. + * + * This also guarantees serialization of the + * last cycle read ('d2') in pit_expect_msb. + */ + if (!pit_verify_msb(0xfe - i)) + break; + goto success; + } + } + debug("Fast TSC calibration failed\n"); + return 0; + +success: + /* + * Ok, if we get here, then we've seen the + * MSB of the PIT decrement 'i' times, and the + * error has shrunk to less than 500 ppm. + * + * As a result, we can depend on there not being + * any odd delays anywhere, and the TSC reads are + * reliable (within the error). + * + * kHz = ticks / time-in-seconds / 1000; + * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 + * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) + */ + delta *= PIT_TICK_RATE; + delta /= (i*256*1000); + debug("Fast TSC calibration using PIT\n"); + return delta / 1000; +} + void timer_set_base(u64 base) { gd->arch.tsc_base = base; @@ -34,17 +298,28 @@ u64 __attribute__((no_instrument_function)) get_ticks(void) return now_tick - gd->arch.tsc_base; } -#define PLATFORM_INFO_MSR 0xce - /* Get the speed of the TSC timer in MHz */ unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void) { - u32 ratio; - u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); + unsigned long fast_calibrate; + + if (gd->arch.tsc_mhz) + return gd->arch.tsc_mhz; + +#ifdef CONFIG_TSC_CALIBRATION_BYPASS + fast_calibrate = CONFIG_TSC_FREQ_IN_MHZ; +#else + fast_calibrate = try_msr_calibrate_tsc(); + if (!fast_calibrate) { + + fast_calibrate = quick_pit_calibrate(); + if (!fast_calibrate) + panic("TSC frequency is ZERO"); + } +#endif - /* 100MHz times Max Non Turbo ratio */ - ratio = (platform_info >> 8) & 0xff; - return 100 * ratio; + gd->arch.tsc_mhz = fast_calibrate; + return fast_calibrate; } unsigned long get_tbclk(void) diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c index dfd2a8496e..975949daa3 100644 --- a/arch/x86/lib/video.c +++ b/arch/x86/lib/video.c @@ -104,7 +104,7 @@ static void __video_putc(const char c, int *x, int *y) } } -static void video_putc(const char c) +static void video_putc(struct stdio_dev *dev, const char c) { int x, y, pos; @@ -123,7 +123,7 @@ static void video_putc(const char c) outb_p(0xff & (pos >> 1), vidport+1); } -static void video_puts(const char *s) +static void video_puts(struct stdio_dev *dev, const char *s) { int x, y, pos; char c; @@ -178,8 +178,6 @@ int video_init(void) vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; vga_dev.putc = video_putc; /* 'putc' function */ vga_dev.puts = video_puts; /* 'puts' function */ - vga_dev.tstc = NULL; /* 'tstc' function */ - vga_dev.getc = NULL; /* 'getc' function */ if (stdio_register(&vga_dev) == 0) return 1; @@ -191,8 +189,6 @@ int video_init(void) strcpy(kbd_dev.name, "kbd"); kbd_dev.ext = 0; kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbd_dev.putc = NULL; /* 'putc' function */ - kbd_dev.puts = NULL; /* 'puts' function */ kbd_dev.tstc = i8042_tstc; /* 'tstc' function */ kbd_dev.getc = i8042_getc; /* 'getc' function */ diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 1dab3cc788..566b048c88 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #ifdef CONFIG_SYS_COREBOOT #include @@ -102,7 +103,7 @@ static int get_boot_protocol(struct setup_header *hdr) } struct boot_params *load_zimage(char *image, unsigned long kernel_size, - void **load_address) + ulong *load_addressp) { struct boot_params *setup_base; int setup_size; @@ -154,9 +155,9 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, /* Determine load address */ if (big_image) - *load_address = (void *)BZIMAGE_LOAD_ADDR; + *load_addressp = BZIMAGE_LOAD_ADDR; else - *load_address = (void *)ZIMAGE_LOAD_ADDR; + *load_addressp = ZIMAGE_LOAD_ADDR; printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base); memset(setup_base, 0, sizeof(*setup_base)); @@ -203,10 +204,10 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, return 0; } - printf("Loading %s at address %p (%ld bytes)\n", - big_image ? "bzImage" : "zImage", *load_address, kernel_size); + printf("Loading %s at address %lx (%ld bytes)\n", + big_image ? "bzImage" : "zImage", *load_addressp, kernel_size); - memmove(*load_address, image + setup_size, kernel_size); + memmove((void *)*load_addressp, image + setup_size, kernel_size); return setup_base; } @@ -242,63 +243,24 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, hdr->loadflags |= HEAP_FLAG; } - if (bootproto >= 0x0202) { - hdr->cmd_line_ptr = (uintptr_t)cmd_line; - } else if (bootproto >= 0x0200) { - setup_base->screen_info.cl_magic = COMMAND_LINE_MAGIC; - setup_base->screen_info.cl_offset = - (uintptr_t)cmd_line - (uintptr_t)setup_base; + if (cmd_line) { + if (bootproto >= 0x0202) { + hdr->cmd_line_ptr = (uintptr_t)cmd_line; + } else if (bootproto >= 0x0200) { + setup_base->screen_info.cl_magic = COMMAND_LINE_MAGIC; + setup_base->screen_info.cl_offset = + (uintptr_t)cmd_line - (uintptr_t)setup_base; + + hdr->setup_move_size = 0x9100; + } - hdr->setup_move_size = 0x9100; + /* build command line at COMMAND_LINE_OFFSET */ + build_command_line(cmd_line, auto_boot); } - /* build command line at COMMAND_LINE_OFFSET */ - build_command_line(cmd_line, auto_boot); return 0; } -/* - * Implement a weak default function for boards that optionally - * need to clean up the system before jumping to the kernel. - */ -__weak void board_final_cleanup(void) -{ -} - -void boot_zimage(void *setup_base, void *load_address) -{ - debug("## Transferring control to Linux (at address %08x) ...\n", - (u32)setup_base); - - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef CONFIG_BOOTSTAGE_REPORT - bootstage_report(); -#endif - board_final_cleanup(); - - printf("\nStarting kernel ...\n\n"); - -#ifdef CONFIG_SYS_COREBOOT - timestamp_add_now(TS_U_BOOT_START_KERNEL); -#endif - /* - * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params - * structure, and then jump to the kernel. We assume that %cs is - * 0x10, 4GB flat, and read/execute, and the data segments are 0x18, - * 4GB flat, and read/write. U-boot is setting them up that way for - * itself in arch/i386/cpu/cpu.c. - */ - __asm__ __volatile__ ( - "movl $0, %%ebp\n" - "cli\n" - "jmp *%[kernel_entry]\n" - :: [kernel_entry]"a"(load_address), - [boot_params] "S"(setup_base), - "b"(0), "D"(0) - : "%ebp" - ); -} - void setup_pcat_compatibility(void) __attribute__((weak, alias("__setup_pcat_compatibility"))); @@ -310,7 +272,7 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { struct boot_params *base_ptr; void *bzImage_addr = NULL; - void *load_address; + ulong load_address; char *s; ulong bzImage_size = 0; ulong initrd_addr = 0; @@ -345,20 +307,17 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address); if (!base_ptr) { - printf("## Kernel loading failed ...\n"); + puts("## Kernel loading failed ...\n"); return -1; } if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET, 0, initrd_addr, initrd_size)) { - printf("Setting up boot parameters failed ...\n"); + puts("Setting up boot parameters failed ...\n"); return -1; } /* we assume that the kernel is in place */ - boot_zimage(base_ptr, load_address); - /* does not return */ - - return -1; + return boot_linux_kernel((ulong)base_ptr, load_address, false); } U_BOOT_CMD( diff --git a/board/8dtech/eco5pk/Kconfig b/board/8dtech/eco5pk/Kconfig new file mode 100644 index 0000000000..55535669fa --- /dev/null +++ b/board/8dtech/eco5pk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ECO5PK + +config SYS_BOARD + default "eco5pk" + +config SYS_VENDOR + default "8dtech" + +config SYS_CONFIG_NAME + default "eco5pk" + +endif diff --git a/board/8dtech/eco5pk/MAINTAINERS b/board/8dtech/eco5pk/MAINTAINERS new file mode 100644 index 0000000000..20c1c8c87e --- /dev/null +++ b/board/8dtech/eco5pk/MAINTAINERS @@ -0,0 +1,6 @@ +ECO5PK BOARD +M: Raphael Assenat +S: Maintained +F: board/8dtech/eco5pk/ +F: include/configs/eco5pk.h +F: configs/eco5pk_defconfig diff --git a/board/8dtech/eco5pk/Makefile b/board/8dtech/eco5pk/Makefile index 2fafcb8682..3333781fb6 100644 --- a/board/8dtech/eco5pk/Makefile +++ b/board/8dtech/eco5pk/Makefile @@ -7,21 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := eco5pk.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := eco5pk.o diff --git a/board/8dtech/eco5pk/eco5pk.h b/board/8dtech/eco5pk/eco5pk.h index a794764852..acf2b80307 100644 --- a/board/8dtech/eco5pk/eco5pk.h +++ b/board/8dtech/eco5pk/eco5pk.h @@ -332,7 +332,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/AndesTech/adp-ag101/Kconfig b/board/AndesTech/adp-ag101/Kconfig new file mode 100644 index 0000000000..8f0197a638 --- /dev/null +++ b/board/AndesTech/adp-ag101/Kconfig @@ -0,0 +1,18 @@ +if TARGET_ADP_AG101 + +config SYS_CPU + default "n1213" + +config SYS_BOARD + default "adp-ag101" + +config SYS_VENDOR + default "AndesTech" + +config SYS_SOC + default "ag101" + +config SYS_CONFIG_NAME + default "adp-ag101" + +endif diff --git a/board/AndesTech/adp-ag101/MAINTAINERS b/board/AndesTech/adp-ag101/MAINTAINERS new file mode 100644 index 0000000000..1f0169bb66 --- /dev/null +++ b/board/AndesTech/adp-ag101/MAINTAINERS @@ -0,0 +1,6 @@ +ADP-AG101 BOARD +M: Andes +S: Maintained +F: board/AndesTech/adp-ag101/ +F: include/configs/adp-ag101.h +F: configs/adp-ag101_defconfig diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile index 826414f5b1..4cc590ff29 100644 --- a/board/AndesTech/adp-ag101/Makefile +++ b/board/AndesTech/adp-ag101/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := adp-ag101.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := adp-ag101.o diff --git a/board/AndesTech/adp-ag101p/Kconfig b/board/AndesTech/adp-ag101p/Kconfig new file mode 100644 index 0000000000..5e8aa22c44 --- /dev/null +++ b/board/AndesTech/adp-ag101p/Kconfig @@ -0,0 +1,18 @@ +if TARGET_ADP_AG101P + +config SYS_CPU + default "n1213" + +config SYS_BOARD + default "adp-ag101p" + +config SYS_VENDOR + default "AndesTech" + +config SYS_SOC + default "ag101" + +config SYS_CONFIG_NAME + default "adp-ag101p" + +endif diff --git a/board/AndesTech/adp-ag101p/MAINTAINERS b/board/AndesTech/adp-ag101p/MAINTAINERS new file mode 100644 index 0000000000..9a2c7a3c16 --- /dev/null +++ b/board/AndesTech/adp-ag101p/MAINTAINERS @@ -0,0 +1,6 @@ +ADP-AG101P BOARD +M: Andes +S: Maintained +F: board/AndesTech/adp-ag101p/ +F: include/configs/adp-ag101p.h +F: configs/adp-ag101p_defconfig diff --git a/board/AndesTech/adp-ag101p/Makefile b/board/AndesTech/adp-ag101p/Makefile index 875fb9228c..2ba7da46da 100644 --- a/board/AndesTech/adp-ag101p/Makefile +++ b/board/AndesTech/adp-ag101p/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := adp-ag101p.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := adp-ag101p.o diff --git a/board/AndesTech/adp-ag102/Kconfig b/board/AndesTech/adp-ag102/Kconfig new file mode 100644 index 0000000000..fc17be3989 --- /dev/null +++ b/board/AndesTech/adp-ag102/Kconfig @@ -0,0 +1,18 @@ +if TARGET_ADP_AG102 + +config SYS_CPU + default "n1213" + +config SYS_BOARD + default "adp-ag102" + +config SYS_VENDOR + default "AndesTech" + +config SYS_SOC + default "ag102" + +config SYS_CONFIG_NAME + default "adp-ag102" + +endif diff --git a/board/AndesTech/adp-ag102/MAINTAINERS b/board/AndesTech/adp-ag102/MAINTAINERS new file mode 100644 index 0000000000..94b87c7f0e --- /dev/null +++ b/board/AndesTech/adp-ag102/MAINTAINERS @@ -0,0 +1,6 @@ +ADP-AG102 BOARD +M: Andes +S: Maintained +F: board/AndesTech/adp-ag102/ +F: include/configs/adp-ag102.h +F: configs/adp-ag102_defconfig diff --git a/board/AndesTech/adp-ag102/Makefile b/board/AndesTech/adp-ag102/Makefile index 6c187190b2..fc4bf88a5c 100644 --- a/board/AndesTech/adp-ag102/Makefile +++ b/board/AndesTech/adp-ag102/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := adp-ag102.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := adp-ag102.o diff --git a/board/Barix/ipam390/Kconfig b/board/Barix/ipam390/Kconfig new file mode 100644 index 0000000000..b85d4da44b --- /dev/null +++ b/board/Barix/ipam390/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IPAM390 + +config SYS_BOARD + default "ipam390" + +config SYS_VENDOR + default "Barix" + +config SYS_CONFIG_NAME + default "ipam390" + +endif diff --git a/board/Barix/ipam390/MAINTAINERS b/board/Barix/ipam390/MAINTAINERS new file mode 100644 index 0000000000..640e34fc8d --- /dev/null +++ b/board/Barix/ipam390/MAINTAINERS @@ -0,0 +1,6 @@ +IPAM390 BOARD +M: Heiko Schocher +S: Maintained +F: board/Barix/ipam390/ +F: include/configs/ipam390.h +F: configs/ipam390_defconfig diff --git a/board/Barix/ipam390/Makefile b/board/Barix/ipam390/Makefile new file mode 100644 index 0000000000..1cb4b57c2c --- /dev/null +++ b/board/Barix/ipam390/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ipam390.o diff --git a/board/Barix/ipam390/README.ipam390 b/board/Barix/ipam390/README.ipam390 new file mode 100644 index 0000000000..5c45fca59f --- /dev/null +++ b/board/Barix/ipam390/README.ipam390 @@ -0,0 +1,229 @@ +Summary +======= +The README is for the boot procedure on the ipam390 board + +In the context of U-Boot, the board is booted in three stages. The initial +bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits +in the internal ROM. The RBL initializes the internal memory and then +depending on the exact board and pin configurations will initialize another +controller (such as NAND) to continue the boot process by loading +the secondary program loader (SPL). The SPL will initialize the system +further (some clocks, SDRAM). As on this board is used the falcon boot +mode, now 2 ways are possible depending on the GPIO 7_14 input pin, +connected with the "soft reset switch" + +If this pin is logical 1 (high level): +spl code starts the kernel image without delay + +If this pin is logical 0 (low level): +spl code starts the u-boot image + +AIS is an image format defined by TI for the images that are to be loaded +to memory by the RBL. The image is divided into a series of sections and +the image's entry point is specified. Each section comes with meta data +like the target address the section is to be copied to and the size of the +section, which is used by the RBL to load the image. At the end of the +image the RBL jumps to the image entry point. The AIS format allows for +other things such as programming the clocks and SDRAM if the header is +programmed for it. We do not take advantage of this and instead use SPL as +it allows for additional flexibility (run-time detect of board revision, +loading the next image from a different media, etc). + +Compilation +=========== +run "./MAKEALL ipam390" in the u-boot source tree. +Once this build completes you will have a u-boot.ais file that needs to +be written to the nand flash. + +Flashing the images to NAND +========================== +The AIS image can be written to NAND flash using the following commands. +Assuming that the network is configured and enabled and the u-boot.ais file +is tftp'able. + +U-Boot > print upd_uboot +upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize} +U-Boot > +U-Boot > run upd_uboot +Using DaVinci-EMAC device +TFTP from server 192.168.1.1; our IP address is 192.168.20.71 +Filename '/tftpboot/ipam390/u-boot.ais'. +Load address: 0xc0000000 +Loading: ################################## + 1.5 MiB/s +done +Bytes transferred = 493716 (78894 hex) + +NAND erase.part: device 0 offset 0x20000, size 0x160000 +Erasing at 0x160000 -- 100% complete. +OK + +NAND write: device 0 offset 0x20000, size 0x78894 + 493716 bytes written: OK +U-Boot > + +Recovery +======== + +In the case of a "bricked" board, you need to use the TI tools found +here[1] to create an uboot-uart-ais.bin file + +- cd to the u-boot source tree + +- compile the u-boot for the ipam390 board: +$ ./MAKEALL ipam390 + + -> Now we shall have u-boot.bin + +- Create u-boot-uart-ais.bin +$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini +ipam390-ais-uart.cfg -o ./uboot-uart-ais.bin ./u-boot.bin@0xC1080000; + +Note: The ipam390-ais-uart.cfg is found in the board directory +for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg + +- We can now run bootloader on IPAM390 via UART using the command below: + +$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin +NOTE: Do not cancel the command execution! The command takes 20+ seconds +to upload u-boot over serial and run it! +Outcome: +Waiting for the OMAP-L138... +(AIS Parse): Read magic word 0x41504954. +(AIS Parse): Waiting for BOOTME... (power on or reset target now) +(AIS Parse): BOOTME received! +(AIS Parse): Performing Start-Word Sync... +(AIS Parse): Performing Ping Opcode Sync... +(AIS Parse): Processing command 0: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 1: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 2: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 3: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 4: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 5: 0x58535901. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Loading section... +(AIS Parse): Loaded 326516-Byte section to address 0xC1080000. +(AIS Parse): Processing command 6: 0x58535906. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Performing jump and close... +(AIS Parse): AIS complete. Jump to address 0xC1080000. +(AIS Parse): Waiting for DONE... +(AIS Parse): Boot completed successfully. + +Operation completed successfully. + +Falcon Bootmode (boot linux without booting U-Boot) +=================================================== + +The Falcon Mode extends this way allowing to start the Linux kernel directly +from SPL. A new command is added to U-Boot to prepare the parameters that SPL +must pass to the kernel, using ATAGS or Device Tree. + +In normal mode, these parameters are generated each time before +loading the kernel, passing to Linux the address in memory where +the parameters can be read. +With Falcon Mode, this snapshot can be saved into persistent storage and SPL is +informed to load it before running the kernel. + +To boot the kernel, these steps under a Falcon-aware U-Boot are required: + +1. Boot the board into U-Boot. +Use the "spl export" command to generate the kernel parameters area or the DT. +U-Boot runs as when it boots the kernel, but stops before passing the control +to the kernel. + +Here the command sequence for the ipam390 board: +- load the linux kernel image into ram: + +U-Boot > nand read c0100000 2 200000 400000 + +NAND read: device 0 offset 0x200000, size 0x400000 + 4194304 bytes read: OK + +- generate the bootparms image: + +U-Boot > spl export atags c0100000 +## Booting kernel from Legacy Image at c0100000 ... + Image Name: Linux-3.5.1 + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 2504280 Bytes = 2.4 MiB + Load Address: c0008000 + Entry Point: c0008000 + Verifying Checksum ... OK + Loading Kernel Image ... OK +subcommand not supported +subcommand not supported +Argument image is now in RAM at: 0xc0000100 + +- copy the bootparms image into nand: + +U-Boot > mtdparts + +device nand0 , # parts = 6 + #: name size offset mask_flags + 0: u-boot-env 0x00020000 0x00000000 0 + 1: u-boot 0x00160000 0x00020000 0 + 2: bootparms 0x00020000 0x00180000 0 + 3: factory-info 0x00060000 0x001a0000 0 + 4: kernel 0x00400000 0x00200000 0 + 5: rootfs 0x07a00000 0x00600000 0 + +active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000 + +defaults: +mtdids : nand0=davinci_nand.0 +mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs) +U-Boot > nand erase.part bootparms + +NAND erase.part: device 0 offset 0x180000, size 0x20000 +Erasing at 0x180000 -- 100% complete. +OK +U-Boot > nand write c0000100 180000 20000 + +NAND write: device 0 offset 0x180000, size 0x20000 + 131072 bytes written: OK +U-Boot > + +You can use also the predefined U-Boot Environment variable "setbootparms", +which will do all the above steps in one command: + +U-Boot > print setbootparms +setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000 +U-Boot > run setbootparms + +NAND read: device 0 offset 0x200000, size 0x400000 + 4194304 bytes read: OK +## Booting kernel from Legacy Image at c0100000 ... + Image Name: Linux-3.5.1 + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 2504280 Bytes = 2.4 MiB + Load Address: c0008000 + Entry Point: c0008000 + Verifying Checksum ... OK + Loading Kernel Image ... OK +subcommand not supported +subcommand not supported +Argument image is now in RAM at: 0xc0000100 + +NAND erase.part: device 0 offset 0x180000, size 0x20000 +Erasing at 0x180000 -- 100% complete. +OK + +NAND write: device 0 offset 0x180000, size 0x20000 + 131072 bytes written: OK +U-Boot > + +Links +===== +[1] + http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/ diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg new file mode 100644 index 0000000000..709cf231d0 --- /dev/null +++ b/board/Barix/ipam390/ipam390-ais-uart.cfg @@ -0,0 +1,202 @@ +; General settings that can be overwritten in the host code +; that calls the AISGen library. +[General] + +; Can be 8 or 16 - used in emifa +busWidth=8 + +; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW +BootMode=UART + +; 8,16,24 - used for SPI,I2C +;AddrWidth=8 + +; NO_CRC,SECTION_CRC,SINGLE_CRC +crcCheckType=NO_CRC + +; This section allows setting the PLL0 system clock with a +; specified multiplier and divider as shown. The clock source +; can also be chosen for internal or external. +; |------24|------16|-------8|-------0| +; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| +; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| +;[PLL0CONFIG] +;PLL0CFG0 = 0x00180001 +;PLL0CFG1 = 0x00000205 + +[PLLANDCLOCKCONFIG] +PLL0CFG0 = 0x00180001 +PLL0CFG1 = 0x00000205 +PERIPHCLKCFG = 0x00000051 + +; This section allows setting up the PLL1. Usually this will +; take place as part of the EMIF3a DDR setup. The format of +; the input args is as follows: +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| +; PLL1CFG1: | RSVD | PLLDIV3| +[PLL1CONFIG] +PLL1CFG0 = 0x18010001 +PLL1CFG1 = 0x00000002 + +; This section lets us configure the peripheral interface +; of the current booting peripheral (I2C, SPI, or UART). +; Use with caution. The format of the PERIPHCLKCFG field +; is as follows: +; SPI: |------24|------16|-------8|-------0| +; | RSVD |PRESCALE| +; +; I2C: |------24|------16|-------8|-------0| +; | RSVD |PRESCALE| CLKL | CLKH | +; +; UART: |------24|------16|-------8|-------0| +; | RSVD | OSR | DLH | DLL | +[PERIPHCLKCFG] +PERIPHCLKCFG = 0x00000051 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface. +; See PLL1CONFIG section for the format of the PLL1CFG fields. +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLL1CFG | +; PLL1CFG1: | PLL1CFG | +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +[EMIF3DDR] +PLL1CFG0 = 0x18010001 +PLL1CFG1 = 0x00000002 +DDRPHYC1R = 0x000000C2 +SDCR = 0x0017C432 +SDTIMR = 0x26922A09 +SDTIMR2 = 0x4414C722 +SDRCR = 0x00000498 +CLK2XSRC = 0x00000000 + +; This section can be used to configure the EMIFA to use +; CS0 as an SDRAM interface. The fields required to do this +; are given below. +; |------24|------16|-------8|-------0| +; SDBCR: | SDBCR | +; SDTIMR: | SDTIMR | +; SDRSRPDEXIT: | SDRSRPDEXIT | +; SDRCR: | SDRCR | +; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | +;[EMIF25SDRAM] +;SDBCR = 0x00004421 +;SDTIMR = 0x42215810 +;SDRSRPDEXIT = 0x00000009 +;SDRCR = 0x00000410 +;DIV4p5_CLK_ENABLE = 0x00000001 + +; This section can be used to configure the async chip selects +; of the EMIFA (CS2-CS5). The fields required to do this +; are given below. +; |------24|------16|-------8|-------0| +; A1CR: | A1CR | +; A2CR: | A2CR | +; A3CR: | A3CR | +; A4CR: | A4CR | +; NANDFCR: | NANDFCR | +;[EMIF25ASYNC] +;A1CR = 0x00000000 +;A2CR = 0x00000000 +;A3CR = 0x00000000 +;A4CR = 0x00000000 +;NANDFCR = 0x00000000 +[EMIF25ASYNC] +A1CR = 0x00000000 +A2CR = 0x04202110 +A3CR = 0x00000000 +A4CR = 0x00000000 +NANDFCR = 0x00000012 + +; This section should be used in place of PLL0CONFIG when +; the I2C, SPI, or UART modes are being used. This ensures that +; the system PLL and the peripheral's clocks are changed together. +; See PLL0CONFIG section for the format of the PLL0CFG fields. +; See PERIPHCLKCFG section for the format of the CLKCFG field. +; |------24|------16|-------8|-------0| +; PLL0CFG0: | PLL0CFG | +; PLL0CFG1: | PLL0CFG | +; PERIPHCLKCFG: | CLKCFG | +;[PLLANDCLOCKCONFIG] +;PLL0CFG0 = 0x00180001 +;PLL0CFG1 = 0x00000205 +;PERIPHCLKCFG = 0x00010032 + +; This section should be used to setup the power state of modules +; of the two PSCs. This section can be included multiple times to +; allow the configuration of any or all of the device modules. +; |------24|------16|-------8|-------0| +; LPSCCFG: | PSCNUM | MODULE | PD | STATE | +;[PSCCONFIG] +;LPSCCFG= + +; This section allows setting of a single PINMUX register. +; This section can be included multiple times to allow setting +; as many PINMUX registers as needed. +; |------24|------16|-------8|-------0| +; REGNUM: | regNum | +; MASK: | mask | +; VALUE: | value | +;[PINMUX] +;REGNUM = 5 +;MASK = 0x00FF0000 +;VALUE = 0x00880000 + +; No Params required - simply include this section for the fast boot +; function to be called +;[FASTBOOT] + +; This section allows setting up the PLL1. Usually this will +; take place as part of the EMIF3a DDR setup. The format of +; the input args is as follows: +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| +; PLL1CFG1: | RSVD | PLLDIV3| +;[PLL1CONFIG] +;PLL1CFG0 = 0x15010001 +;PLL1CFG1 = 0x00000002 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface on ARM-boot D800K002 devices. +; |------24|------16|-------8|-------0| +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +;[ARM_EMIF3DDR_PATCHFXN] +;DDRPHYC1R = 0x000000C2 +;SDCR = 0x0017C432 +;SDTIMR = 0x26922A09 +;SDTIMR2 = 0x4414C722 +;SDRCR = 0x00000498 +;CLK2XSRC = 0x00000000 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface on DSP-boot D800K002 devices. +; |------24|------16|-------8|-------0| +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +;[DSP_EMIF3DDR_PATCHFXN] +;DDRPHYC1R = 0x000000C4 +;SDCR = 0x08134632 +;SDTIMR = 0x26922A09 +;SDTIMR2 = 0x0014C722 +;SDRCR = 0x00000492 +;CLK2XSRC = 0x00000000 + +;[INPUTFILE] +;FILENAME=u-boot.bin +;LOADADDRESS=0xC1080000 +;ENTRYPOINTADDRESS=0xC1080000 diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c new file mode 100644 index 0000000000..6ce8960bbd --- /dev/null +++ b/board/Barix/ipam390/ipam390.c @@ -0,0 +1,337 @@ +/* + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * Based on: + * U-Boot:board/davinci/da8xxevm/da850evm.c + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. + * Copyright (C) 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DRIVER_TI_EMAC +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII +#define HAS_RMII 1 +#else +#define HAS_RMII 0 +#endif +#endif /* CONFIG_DRIVER_TI_EMAC */ + +void dsp_lpsc_on(unsigned domain, unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (*ptstat & (0x1 << domain)) + ; + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + *ptcmd = 0x1 << domain; + + while (*ptstat & (0x1 << domain)) + ; + while ((*mdstat & 0x1f) != 0x03) + ; /* Probably an overkill... */ +} + +static void dspwake(void) +{ + unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; + u32 val; + + /* if the device is ARM only, return */ + if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) + return; + + if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) + return; + + *resetvect++ = 0x1E000; /* DSP Idle */ + /* clear out the next 10 words as NOP */ + memset(resetvect, 0, sizeof(unsigned) * 10); + + /* setup the DSP reset vector */ + writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); + + dsp_lpsc_on(1, DAVINCI_LPSC_GEM); + val = readl(PSC0_MDCTL + (15 * 4)); + val |= 0x100; + writel(val, (PSC0_MDCTL + (15 * 4))); +} + +int misc_init_r(void) +{ + dspwake(); + return 0; +} + +static const struct pinmux_config gpio_pins[] = { + /* GP7[14] selects bootmode*/ + { pinmux(16), 8, 3 }, /* GP7[14] */ +}; + +const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_DRIVER_TI_EMAC + PINMUX_ITEM(emac_pins_mdio), +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + PINMUX_ITEM(emac_pins_rmii), +#else + PINMUX_ITEM(emac_pins_mii), +#endif +#endif + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(uart0_pins_txrx), + PINMUX_ITEM(uart0_pins_rtscts), +#ifdef CONFIG_NAND_DAVINCI + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_nand), +#endif + PINMUX_ITEM(gpio_pins), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_UART0 }, /* console */ + { DAVINCI_LPSC_GPIO }, +}; + +const int lpsc_size = ARRAY_SIZE(lpsc); + +#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK +#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 +#endif + +#define REV_AM18X_EVM 0x100 + +/* + * get_board_rev() - setup to pass kernel board revision information + * Returns: + * bit[0-3] Maximum cpu clock rate supported by onboard SoC + * 0000b - 300 MHz + * 0001b - 372 MHz + * 0010b - 408 MHz + * 0011b - 456 MHz + */ +u32 get_board_rev(void) +{ + char *s; + u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; + u32 rev = 0; + + s = getenv("maxcpuclk"); + if (s) + maxcpuclk = simple_strtoul(s, NULL, 10); + + if (maxcpuclk >= 456000000) + rev = 3; + else if (maxcpuclk >= 408000000) + rev = 2; + else if (maxcpuclk >= 372000000) + rev = 1; +#ifdef CONFIG_DA850_AM18X_EVM + rev |= REV_AM18X_EVM; +#endif + return rev; +} + +int board_early_init_f(void) +{ + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; + + return 0; +} + +int board_init(void) +{ +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* setup the SUSPSRC for ARM to control emulation suspend */ + writel(readl(&davinci_syscfg_regs->suspsrc) & + ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART0), + &davinci_syscfg_regs->suspsrc); + + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) + return 1; + +#ifdef CONFIG_DRIVER_TI_EMAC + davinci_emac_mii_mode_sel(HAS_RMII); +#endif /* CONFIG_DRIVER_TI_EMAC */ + + /* enable the console UART */ + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), +#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) + &davinci_uart0_ctrl_regs->pwremu_mgmt); +#else + &davinci_uart2_ctrl_regs->pwremu_mgmt); +#endif + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +static int init_led(int gpio, char *name, int val) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) + return -1; + ret = gpio_direction_output(gpio, val); + if (ret) + return -1; + + return gpio; +} + +#define LED_ON 0 +#define LED_OFF 1 + +#if !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int status) +{ + static int red; + static int green; + + if (red == 0) + red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); + if (red != CONFIG_IPAM390_GPIO_LED_RED) + return; + if (green == 0) + green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", + LED_OFF); + if (green != CONFIG_IPAM390_GPIO_LED_GREEN) + return; + + switch (status) { + case BOOTSTAGE_ID_RUN_OS: + /* + * set normal state + * LED Red : on + * LED green: off + */ + gpio_set_value(red, LED_ON); + gpio_set_value(green, LED_OFF); + break; + case BOOTSTAGE_ID_MAIN_LOOP: + /* + * U-Boot operation + * LED Red : on + * LED green: on + */ + gpio_set_value(red, LED_ON); + gpio_set_value(green, LED_ON); + break; + } +} +#endif +#endif + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + int ret; + int bootmode = 0; + + /* + * GP7[14] selects bootmode: + * 1: boot linux + * 0: boot u-boot + * if error accessing gpio boot U-Boot + * + * SPL bootmode + * 0: boot linux + * 1: boot u-boot + */ + ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode"); + if (ret) + bootmode = 1; + if (!bootmode) { + ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE); + if (ret) + bootmode = 1; + } + if (!bootmode) + ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE); + if (!bootmode) + if (ret == 0) + bootmode = 1; + /* + * LED red : on + * LED green: off + */ + init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); + init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); + return bootmode; +} +#endif diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds new file mode 100644 index 0000000000..5f290ec7db --- /dev/null +++ b/board/Barix/ipam390/u-boot-spl-ipam390.lds @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_FOOTPRINT } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/arm926ejs/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sram + + __image_copy_end = .; + + .end : + { + *(.__end) + } >.sram +} diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h new file mode 100644 index 0000000000..15225b0724 --- /dev/null +++ b/board/BuR/common/bur_common.h @@ -0,0 +1,22 @@ +/* + * bur_comon.h + * + * common board information header for B&R boards + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BUR_COMMON_H_ +#define _BUR_COMMON_H_ + +void blink(u32 blinks, u32 intervall, u32 pin); +void pmicsetup(u32 mpupll); +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +int board_eth_init(bd_t *bis); + +#endif diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c new file mode 100644 index 0000000000..25cbe62b1f --- /dev/null +++ b/board/BuR/common/common.c @@ -0,0 +1,223 @@ +/* + * common.c + * + * common board functions for B&R boards + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bur_common.h" + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +/* --------------------------------------------------------------------------*/ +void blink(u32 blinks, u32 intervall, u32 pin) +{ + gpio_direction_output(pin, 0); + int val = 0; + + do { + val ^= 0x01; + gpio_set_value(pin, val); + mdelay(intervall); + } while (blinks--); + + gpio_set_value(pin, 0); +} +#ifdef CONFIG_SPL_BUILD +void pmicsetup(u32 mpupll) +{ + int mpu_vdd; + int usb_cur_lim; + + /* setup I2C */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + if (i2c_probe(TPS65217_CHIP_PM)) { + puts("PMIC (0x24) not found! skip further initalization.\n"); + return; + } + + /* Get the frequency which is defined by device fuses */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + printf("detected max. frequency: %d - ", dpll_mpu_opp100.m); + + if (0 != mpupll) { + dpll_mpu_opp100.m = MPUPLL_M_1000; + printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m); + } else { + puts("ok.\n"); + } + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, + usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set LDO3 to 1.8V */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + /* Set LDO4 to 3.3V */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +#endif /* CONFIG_SPL_BUILD */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +/* describing port offsets of TI's CPSW block */ +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 2, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* CONFIG_DRIVER_TI_CPSW, ... */ + +#if defined(CONFIG_DRIVER_TI_CPSW) + +int board_eth_init(bd_t *bis) +{ + int rv = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC ... "); + + if (is_valid_ether_addr(mac_addr)) { + printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5] + ); + eth_setenv_enetaddr("ethaddr", mac_addr); + } + } + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + + rv = cpsw_register(&cpsw_data); + if (rv < 0) { + printf("Error %d registering CPSW switch\n", rv); + return 0; + } +#endif /* CONFIG_DRIVER_TI_CPSW, ... */ + return rv; +} +#endif /* CONFIG_DRIVER_TI_CPSW */ +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(1, 0, 0, -1, -1); +} +#endif diff --git a/board/BuR/kwb/Kconfig b/board/BuR/kwb/Kconfig new file mode 100644 index 0000000000..4beefbf771 --- /dev/null +++ b/board/BuR/kwb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_KWB + +config SYS_BOARD + default "kwb" + +config SYS_VENDOR + default "BuR" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "kwb" + +endif diff --git a/board/BuR/kwb/MAINTAINERS b/board/BuR/kwb/MAINTAINERS new file mode 100644 index 0000000000..c28fb49fe4 --- /dev/null +++ b/board/BuR/kwb/MAINTAINERS @@ -0,0 +1,6 @@ +KWB BOARD +M: Hannes Petermaier +S: Maintained +F: board/BuR/kwb/ +F: include/configs/kwb.h +F: configs/kwb_defconfig diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile new file mode 100644 index 0000000000..7b04b26ae4 --- /dev/null +++ b/board/BuR/kwb/Makefile @@ -0,0 +1,12 @@ +# +# Makefile +# +# Copyright (C) 2014 Hannes Petermaier - +# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPL_BUILD) += mux.o +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c new file mode 100644 index 0000000000..804765a8de --- /dev/null +++ b/board/BuR/kwb/board.c @@ -0,0 +1,240 @@ +/* + * board.c + * + * Board functions for B&R KWB Board + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" + +/* -------------------------------------------------------------------------*/ +/* -- defines for used GPIO Hardware -- */ +#define KEY (0+4) +#define LCD_PWR (0+5) +#define PUSH_KEY (0+31) +#define USB2SD_NRST (32+29) +#define USB2SD_PWR (96+13) +/* -------------------------------------------------------------------------*/ +/* -- PSOC Resetcontroller Register defines -- */ + +/* I2C Address of controller */ +#define RSTCTRL_ADDR 0x75 +/* Register for CTRL-word */ +#define RSTCTRL_CTRLREG 0x01 +/* Register for giving some information to VxWorks OS */ +#define RSTCTRL_SCRATCHREG 0x04 + +/* -- defines for RSTCTRL_CTRLREG -- */ +#define RSTCTRL_FORCE_PWR_NEN 0x0404 + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + unsigned int oldspeed; + unsigned short buf; + + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; + struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; + /* + * enable additional clocks of modules which are accessed later from + * VxWorks OS + */ + u32 *const clk_domains[] = { 0 }; + + u32 *const clk_modules_kwbspecific[] = { + &cmwkup->wkup_adctscctrl, + &cmper->spi1clkctrl, + &cmper->dcan0clkctrl, + &cmper->dcan1clkctrl, + &cmper->epwmss0clkctrl, + &cmper->epwmss1clkctrl, + &cmper->epwmss2clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1); + + /* power-OFF LCD-Display */ + gpio_direction_output(LCD_PWR, 0); + + /* setup I2C */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + /* power-ON 3V3 via Resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + buf = RSTCTRL_FORCE_PWR_NEN; + i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); + } + +#if defined(CONFIG_AM335X_USB0) + /* power on USB2SD Controller */ + gpio_direction_output(USB2SD_PWR, 1); + mdelay(1); + /* give a reset Pulse to USB2SD Controller */ + gpio_direction_output(USB2SD_NRST, 0); + mdelay(1); + gpio_set_value(USB2SD_NRST, 1); +#endif + pmicsetup(0); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gpmc_init(); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + const unsigned int ton = 250; + const unsigned int toff = 1000; + unsigned int cnt = 3; + unsigned short buf = 0xAAAA; + unsigned int oldspeed; + + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */ + + if (gpio_get_value(KEY)) { + do { + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x09, 0xFF); + mdelay(ton); + /* turn off light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x01, 0xFF); + mdelay(toff); + cnt--; + if (!gpio_get_value(KEY) && + gpio_get_value(PUSH_KEY) && 1 == cnt) { + puts("updating from USB ...\n"); + setenv("bootcmd", "run usbupdate"); + break; + } else if (!gpio_get_value(KEY)) { + break; + } + } while (cnt); + } + + switch (cnt) { + case 0: + puts("3 blinks ... entering BOOT mode.\n"); + buf = 0x0000; + break; + case 1: + puts("2 blinks ... entering DIAGNOSE mode.\n"); + buf = 0x0F0F; + break; + case 2: + puts("1 blinks ... entering SERVICE mode.\n"); + buf = 0xB4B4; + break; + case 3: + puts("0 blinks ... entering RUN mode.\n"); + buf = 0x0404; + break; + } + mdelay(ton); + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x09, 0xFF); + /* write bootinfo into scratchregister of resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); + } + /* + * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does + * expect that vectors are there, original u-boot moves them to _start + */ + __asm__("ldr r0,=0x20000"); + __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */ + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c new file mode 100644 index 0000000000..ecb2e7a427 --- /dev/null +++ b/board/BuR/kwb/mux.c @@ -0,0 +1,197 @@ +/* + * mux.c + * + * Pinmux Setting for B&R LEIT Board(s) + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, + /* USB0 DrvBus Receiver disable (from romcode 0x20) */ + {OFFSET(usb0_drvvbus), (MODE(0))}, + /* USB1 DrvBus as GPIO due to HW-Workaround */ + {OFFSET(usb1_drvvbus), (MODE(7))}, + {-1}, +}; +static struct module_pin_mux spi1_pin_mux[] = { + /* SPI1_SCLK */ + {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_D0 */ + {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_D1 */ + {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_CS0 */ + {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux dcan0_pin_mux[] = { + /* DCAN0 TX */ + {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN0 RX */ + {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux dcan1_pin_mux[] = { + /* DCAN1 TX */ + {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN1 RX */ + {OFFSET(uart1_txd), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux gpios[] = { + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, + /* GPIO0_4 (SPI D1) - TA602 */ + {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */ + {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, + /* GPIO0_7 (PWW0 OUT) - CAN TERM */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */ + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)}, + /* GPIO0_30 (GPMC_WAIT0) - TA601 */ + {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */ + {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)}, + /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */ + {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO2_4 (GPMC_nWE) - TST_BAST */ + {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, + /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */ + {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */ + {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */ + {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(dcan0_pin_mux); + configure_module_pin_mux(dcan1_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(gpios); +} diff --git a/board/BuR/tseries/Kconfig b/board/BuR/tseries/Kconfig new file mode 100644 index 0000000000..ed48300c0a --- /dev/null +++ b/board/BuR/tseries/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TSERIES + +config SYS_BOARD + default "tseries" + +config SYS_VENDOR + default "BuR" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "tseries" + +endif diff --git a/board/BuR/tseries/MAINTAINERS b/board/BuR/tseries/MAINTAINERS new file mode 100644 index 0000000000..e57326aaf3 --- /dev/null +++ b/board/BuR/tseries/MAINTAINERS @@ -0,0 +1,8 @@ +TSERIES BOARD +M: Hannes Petermaier +S: Maintained +F: board/BuR/tseries/ +F: include/configs/tseries.h +F: configs/tseries_mmc_defconfig +F: configs/tseries_nand_defconfig +F: configs/tseries_spi_defconfig diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile new file mode 100644 index 0000000000..ec0d27a7aa --- /dev/null +++ b/board/BuR/tseries/Makefile @@ -0,0 +1,14 @@ +# +# Makefile +# +# Copyright (C) 2013 Hannes Petermaier +# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y := mux.o +endif +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c new file mode 100644 index 0000000000..c0178e75cf --- /dev/null +++ b/board/BuR/tseries/board.c @@ -0,0 +1,149 @@ +/* + * board.c + * + * Board functions for B&R LEIT Board + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* --------------------------------------------------------------------------*/ +/* -- defines for GPIO -- */ +#define ETHLED_ORANGE (96+16) /* GPIO3_16 */ +#define REPSWITCH (0+20) /* GPIO0_20 */ + + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +/* + * called from spl_nand.c + * return 0 for loading linux, return 1 for loading u-boot + */ +int spl_start_uboot(void) +{ + if (0 == gpio_get_value(REPSWITCH)) { + blink(5, 125, ETHLED_ORANGE); + mdelay(1000); + printf("SPL: entering u-boot instead kernel image.\n"); + return 1; + } + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + +#define OSC (V_OSCK/1000000) +static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + pmicsetup(1000); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ + +/* Basic board specific setup. Pinmux has been handled already. */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#ifdef CONFIG_NAND + gpmc_init(); +#endif + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + gpio_direction_output(ETHLED_ORANGE, 0); + + if (0 == gpio_get_value(REPSWITCH)) { + printf("\n\n\n" + "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n" + "!!!!!!! recovery switch activated !!!!!!!\n" + "!!!!!!! running usbupdate !!!!!!!\n" + "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n"); + setenv("bootcmd", "sleep 2; run netupdate;"); + } + + printf("turning on display power+backlight ... "); + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1, + 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2, + 0x62, TPS65217_MASK_ALL_BITS); /* 100% */ + printf("ok.\n"); + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c new file mode 100644 index 0000000000..0ba25ee318 --- /dev/null +++ b/board/BuR/tseries/mux.c @@ -0,0 +1,233 @@ +/* + * mux.c + * + * Pinmux Setting for B&R LEIT Board(s) + * + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; +#ifdef CONFIG_MMC +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ + + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + {-1}, +}; +#endif +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + /* SPI0_SCLK */ + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D0 */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D1 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_CS0 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ + {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ + {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, + /* + * MII2_CRS is shared with + * NAND_WAIT0 + */ + {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */ + {-1}, +}; +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; +#endif +static struct module_pin_mux gpIOs[] = { + /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */ + {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ + {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */ + {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */ + {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ + {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */ + {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */ + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */ + {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */ + {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */ + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO2_0 (GPMC_nCS3) - DCOK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* + * GPIO0_7 (PWW0 OUT) + * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) + */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */ + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - REP-Switch */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, + /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */ + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */ + {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, + /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, + + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mii2_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_MMC) + configure_module_pin_mux(mmc1_pin_mux); +#endif + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(gpIOs); +} diff --git a/board/BuS/eb_cpu5282/Kconfig b/board/BuS/eb_cpu5282/Kconfig new file mode 100644 index 0000000000..237dc1b5c0 --- /dev/null +++ b/board/BuS/eb_cpu5282/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EB_CPU5282 + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "eb_cpu5282" + +config SYS_VENDOR + default "BuS" + +config SYS_CONFIG_NAME + default "eb_cpu5282" + +endif diff --git a/board/BuS/eb_cpu5282/MAINTAINERS b/board/BuS/eb_cpu5282/MAINTAINERS new file mode 100644 index 0000000000..87298ad9f3 --- /dev/null +++ b/board/BuS/eb_cpu5282/MAINTAINERS @@ -0,0 +1,7 @@ +EB_CPU5282 BOARD +M: Jens Scharsig +S: Maintained +F: board/BuS/eb_cpu5282/ +F: include/configs/eb_cpu5282.h +F: configs/eb_cpu5282_defconfig +F: configs/eb_cpu5282_internal_defconfig diff --git a/board/BuS/eb_cpu5282/Makefile b/board/BuS/eb_cpu5282/Makefile index e7f4fb63b0..3eb7278988 100644 --- a/board/BuS/eb_cpu5282/Makefile +++ b/board/BuS/eb_cpu5282/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = eb_cpu5282.o diff --git a/board/BuS/eb_cpux9k2/Kconfig b/board/BuS/eb_cpux9k2/Kconfig new file mode 100644 index 0000000000..230e64d8fc --- /dev/null +++ b/board/BuS/eb_cpux9k2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EB_CPUX9K2 + +config SYS_BOARD + default "eb_cpux9k2" + +config SYS_VENDOR + default "BuS" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "eb_cpux9k2" + +endif diff --git a/board/BuS/eb_cpux9k2/MAINTAINERS b/board/BuS/eb_cpux9k2/MAINTAINERS new file mode 100644 index 0000000000..81c4349ac9 --- /dev/null +++ b/board/BuS/eb_cpux9k2/MAINTAINERS @@ -0,0 +1,7 @@ +EB_CPUX9K2 BOARD +M: Jens Scharsig +S: Maintained +F: board/BuS/eb_cpux9k2/ +F: include/configs/eb_cpux9k2.h +F: configs/eb_cpux9k2_defconfig +F: configs/eb_cpux9k2_ram_defconfig diff --git a/board/BuS/eb_cpux9k2/Makefile b/board/BuS/eb_cpux9k2/Makefile index d69195e1b6..b2ec389ab9 100644 --- a/board/BuS/eb_cpux9k2/Makefile +++ b/board/BuS/eb_cpux9k2/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cpux9k2.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cpux9k2.o diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index 5e4778e978..76ad7c443b 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -98,7 +98,7 @@ int misc_init_r(void) puts("Error: invalid MAC at EEPROM\n"); } } - gd->jt[XF_do_reset] = (void *) do_reset; + gd->jt->do_reset = do_reset; #ifdef CONFIG_STATUS_LED status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); diff --git a/board/BuS/vl_ma2sc/Kconfig b/board/BuS/vl_ma2sc/Kconfig new file mode 100644 index 0000000000..2f43519089 --- /dev/null +++ b/board/BuS/vl_ma2sc/Kconfig @@ -0,0 +1,15 @@ +if TARGET_VL_MA2SC + +config SYS_BOARD + default "vl_ma2sc" + +config SYS_VENDOR + default "BuS" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "vl_ma2sc" + +endif diff --git a/board/BuS/vl_ma2sc/MAINTAINERS b/board/BuS/vl_ma2sc/MAINTAINERS new file mode 100644 index 0000000000..b70104d52e --- /dev/null +++ b/board/BuS/vl_ma2sc/MAINTAINERS @@ -0,0 +1,7 @@ +VL_MA2SC BOARD +M: Jens Scharsig +S: Maintained +F: board/BuS/vl_ma2sc/ +F: include/configs/vl_ma2sc.h +F: configs/vl_ma2sc_defconfig +F: configs/vl_ma2sc_ram_defconfig diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile index 821c1a0ecb..d4b24ac8c2 100644 --- a/board/BuS/vl_ma2sc/Makefile +++ b/board/BuS/vl_ma2sc/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS += vl_ma2sc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += vl_ma2sc.o diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c index e2ae6fde6c..da39c86258 100644 --- a/board/BuS/vl_ma2sc/vl_ma2sc.c +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -8,15 +8,15 @@ #include #include -#include +#include #include +#include #include #include #include #include #include #include -#include #include #include #include @@ -66,35 +66,22 @@ static void vl_ma2sc_nand_hw_init(void) /* Configure RDY/BSY */ #ifdef CONFIG_SYS_NAND_READY_PIN - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); #endif /* Enable NandFlash */ - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif #ifdef CONFIG_MACB static void vl_ma2sc_macb_hw_init(void) { - unsigned long erstl; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ writel(1 << ATMEL_ID_EMAC, &pmc->pcer); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + at91_phy_reset(); at91_macb_hw_init(); } diff --git a/board/CarMediaLab/flea3/Kconfig b/board/CarMediaLab/flea3/Kconfig new file mode 100644 index 0000000000..7113f2b51f --- /dev/null +++ b/board/CarMediaLab/flea3/Kconfig @@ -0,0 +1,15 @@ +if TARGET_FLEA3 + +config SYS_BOARD + default "flea3" + +config SYS_VENDOR + default "CarMediaLab" + +config SYS_SOC + default "mx35" + +config SYS_CONFIG_NAME + default "flea3" + +endif diff --git a/board/CarMediaLab/flea3/MAINTAINERS b/board/CarMediaLab/flea3/MAINTAINERS new file mode 100644 index 0000000000..c7b0df7bc4 --- /dev/null +++ b/board/CarMediaLab/flea3/MAINTAINERS @@ -0,0 +1,6 @@ +FLEA3 BOARD +M: Stefano Babic +S: Maintained +F: board/CarMediaLab/flea3/ +F: include/configs/flea3.h +F: configs/flea3_defconfig diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile index 82a2208c15..f34be748c2 100644 --- a/board/CarMediaLab/flea3/Makefile +++ b/board/CarMediaLab/flea3/Makefile @@ -6,31 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := flea3.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := flea3.o +obj-y += lowlevel_init.o diff --git a/board/LEOX/elpt860/Makefile b/board/LEOX/elpt860/Makefile deleted file mode 100644 index 0268f9ce48..0000000000 --- a/board/LEOX/elpt860/Makefile +++ /dev/null @@ -1,42 +0,0 @@ - -####################################################################### -# -# Copyright (C) 2000, 2001, 2002, 2003 -# The LEOX team , http://www.leox.org -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# LEOX.org is about the development of free hardware and software resources -# for system on chip. -# -# Description: U-Boot port on the LEOX's ELPT860 CPU board -# ~~~~~~~~~~~ -# -####################################################################### -# -# SPDX-License-Identifier: GPL-2.0+ -# -####################################################################### - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/LEOX/elpt860/README.LEOX b/board/LEOX/elpt860/README.LEOX deleted file mode 100644 index fe3c0f1528..0000000000 --- a/board/LEOX/elpt860/README.LEOX +++ /dev/null @@ -1,424 +0,0 @@ -============================================================================= - - U-Boot port on the LEOX's ELPT860 CPU board - ------------------------------------------- - -LEOX.org is about the development of free hardware and software resources - for system on chip. - -For more information, contact The LEOX team - -References: -~~~~~~~~~~ - 1) Get the last stable release from denx.de: - o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2 - 2) Get the current CVS snapshot: - o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login - o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot - -============================================================================= - -The ELPT860 CPU board has the following features: - -Processor: - MPC860T @ 50MHz - - PowerPC Core - - 65 MIPS - - Caches: D->4KB, I->4KB - - CPM: 4 SCCs, 2 SMCs - - Ethernet 10/100 - - SPI, I2C, PCMCIA, Parallel - -CPU board: - DRAM: 16 MB - - FLASH: 512 KB + (2 * 4 MB) - - NVRAM: 128 KB - - 1 Serial link - - 2 Ethernet 10 BaseT Channels - -On power-up the processor jumps to the address of 0x02000100 - -Thus, U-Boot is configured to reside in flash starting at the address of -0x02001000. The environment space is located in NVRAM separately from -U-Boot, at the address of 0x03000000. - -============================================================================= - - U-Boot test results - -============================================================================= - - -################################################## -# Operation on the serial console (SMC1) -############################## - -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) - -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present - *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** -Board: ### No HW ID - assuming ELPT860 -DRAM: 16 MB -FLASH: 512 kB -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET - -Type "run nfsboot" to mount root filesystem over NFS - -Hit any key to stop autoboot: 0 -LEOX_elpt860: help -askenv - get environment variables from stdin -base - print or set address offset -bdinfo - print Board Info structure -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -cmp - memory compare -coninfo - print console devices and informations -cp - memory copy -crc32 - checksum calculation -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -iminfo - print header information for application image -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loop - infinite loop on address range -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sleep - delay execution for some time -source - run script from memory -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -version - print monitor version -? - alias for 'help' - -################################################## -# Environment Variables (CONFIG_ENV_IS_IN_NVRAM) -############################## - -LEOX_elpt860: printenv -bootdelay=5 -loads_echo=1 -baudrate=9600 -stdin=serial -stdout=serial -stderr=serial -ethaddr=00:03:ca:00:64:df -ipaddr=192.168.0.30 -netmask=255.255.255.0 -serverip=192.168.0.1 -nfsserverip=192.168.0.1 -preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo -gatewayip=192.168.0.1 -ramargs=setenv bootargs root=/dev/ram rw -rootargs=setenv rootpath /tftp/${ipaddr} -nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath} -addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0: -ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm -nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm -bootcmd=run ramboot -clocks_in_mhz=1 - -Environment size: 730/16380 bytes - -################################################## -# Flash Memory Information -############################## - -LEOX_elpt860: flinfo - -Bank # 1: AMD AM29F040 (4 Mbits) - Size: 512 KB in 8 Sectors - Sector Start Addresses: - 02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000 - 02050000 02060000 02070000 - -################################################## -# Board Information Structure -############################## - -LEOX_elpt860: bdinfo -memstart = 0x00000000 -memsize = 0x01000000 -flashstart = 0x02000000 -flashsize = 0x00080000 -flashoffset = 0x00030000 -sramstart = 0x00000000 -sramsize = 0x00000000 -immr_base = 0xFF000000 -bootflags = 0x00000001 -intfreq = 50 MHz -busfreq = 50 MHz -ethaddr = 00:03:ca:00:64:df -IP addr = 192.168.0.30 -baudrate = 9600 bps - -################################################## -# Image Download and run over serial port -# hello_world (S-Record image) -# ===> 1) Enter "loads" command into U-Boot monitor -# ===> 2) From TeraTerm's bar menu, Select 'File/Send file...' -# Then select 'hello_world.srec' with the file browser -############################## - -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) - -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present - *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** -Board: ### No HW ID - assuming ELPT860 -DRAM: 16 MB -FLASH: 512 kB -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET - -Type "run nfsboot" to mount root filesystem over NFS - -Hit any key to stop autoboot: 0 -LEOX_elpt860: loads -## Ready for S-Record download ... -S804040004F3050154000501709905014C000501388D -## First Load Addr = 0x00040000 -## Last Load Addr = 0x0005018B -## Total Size = 0x0001018C = 65932 Bytes -## Start Addr = 0x00040004 -LEOX_elpt860: go 40004 This is a test !!! -## Starting application at 0x00040004 ... -Hello World -argc = 6 -argv[0] = "40004" -argv[1] = "This" -argv[2] = "is" -argv[3] = "a" -argv[4] = "test" -argv[5] = "!!!" -argv[6] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 - -################################################## -# Image download and run over ethernet interface -# Linux-2.4.4 (uImage) + Root filesystem mounted over NFS -############################## - -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) - -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present - *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** -Board: ### No HW ID - assuming ELPT860 -DRAM: 16 MB -FLASH: 512 kB -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET - -Type "run nfsboot" to mount root filesystem over NFS - -Hit any key to stop autoboot: 0 -LEOX_elpt860: run nfsboot -ARP broadcast 1 -TFTP from server 192.168.0.1; our IP address is 192.168.0.30 -Filename '/home/leox/uImage'. -Load address: 0x400000 -Loading: ################################################################# - ############################# -done -Bytes transferred = 477294 (7486e hex) -## Booting image at 00400000 ... - Image Name: Linux-2.4.4 - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 477230 Bytes = 466 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 -On node 0 totalpages: 4096 -zone(0): 4096 pages. -zone(1): 0 pages. -zone(2): 0 pages. -Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0: -rtsched version <20010618.1050.24> -Decrementer Frequency: 3125000 -Warning: real time clock seems stuck! -Calibrating delay loop... 49.76 BogoMIPS -Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem) -Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) -Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) -Page-cache hash table entries: 4096 (order: 2, 16384 bytes) -Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) -POSIX conformance testing by UNIFIX -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Starting kswapd v1.8 -CPM UART driver version 0.03 -ttyS0 on SMC1 at 0x0280, BRG1 -block: queued sectors max/low 9701kB/3233kB, 64 slots per queue -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize -eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 1024 bind 1024) -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -Looking up port of RPC 100003/2 on 192.168.0.1 -Looking up port of RPC 100005/2 on 192.168.0.1 -VFS: Mounted root (nfs filesystem). -Freeing unused kernel memory: 44k init -INIT: version 2.78 booting - Welcome to DENX Embedded Linux Environment - Press 'I' to enter interactive startup. -Mounting proc filesystem: [ OK ] -Configuring kernel parameters: [ OK ] -Cannot access the Hardware Clock via any known method. -Use the --debug option to see the details of our search for an access method. -Setting clock : Wed Dec 31 19:00:11 EST 1969 [ OK ] -Activating swap partitions: [ OK ] -Setting hostname 192.168.0.30: [ OK ] -Finding module dependencies: -[ OK ] -Checking filesystems -Checking all file systems. -[ OK ] -Mounting local filesystems: [ OK ] -Enabling swap space: [ OK ] -INIT: Entering runlevel: 3 -Entering non-interactive startup -Starting system logger: [ OK ] -Starting kernel logger: [ OK ] -Starting xinetd: [ OK ] - -192 login: root -Last login: Wed Dec 31 19:00:41 on ttyS0 -bash-2.04# - -################################################## -# Image download and run over ethernet interface -# Linux-2.4.4 + Root filesystem mounted from RAM (pMulti) -############################## - -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) - -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present - *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** -Board: ### No HW ID - assuming ELPT860 -DRAM: 16 MB -FLASH: 512 kB -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET - -Type "run nfsboot" to mount root filesystem over NFS - -Hit any key to stop autoboot: 0 -LEOX_elpt860: run ramboot -ARP broadcast 1 -TFTP from server 192.168.0.1; our IP address is 192.168.0.30 -Filename '/home/leox/pMulti'. -Load address: 0x400000 -Loading: ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ######################################################## -done -Bytes transferred = 1947816 (1db8a8 hex) -## Booting image at 00400000 ... - Image Name: linux-2.4.4-2002-03-21 Multiboot - Image Type: PowerPC Linux Multi-File Image (gzip compressed) - Data Size: 1947752 Bytes = 1902 kB = 1 MB - Load Address: 00000000 - Entry Point: 00000000 - Contents: - Image 0: 477230 Bytes = 466 kB = 0 MB - Image 1: 1470508 Bytes = 1436 kB = 1 MB - Verifying Checksum ... OK - Uncompressing Multi-File Image ... OK - Loading Ramdisk to 00e44000, end 00fab02c ... OK -Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 -On node 0 totalpages: 4096 -zone(0): 4096 pages. -zone(1): 0 pages. -zone(2): 0 pages. -Kernel command line: root=/dev/ram rw -rtsched version <20010618.1050.24> -Decrementer Frequency: 3125000 -Warning: real time clock seems stuck! -Calibrating delay loop... 49.76 BogoMIPS -Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem) -Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) -Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) -Page-cache hash table entries: 4096 (order: 2, 16384 bytes) -Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) -POSIX conformance testing by UNIFIX -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Starting kswapd v1.8 -CPM UART driver version 0.03 -ttyS0 on SMC1 at 0x0280, BRG1 -block: queued sectors max/low 8741kB/2913kB, 64 slots per queue -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize -eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df -RAMDISK: Compressed image found at block 0 -Freeing initrd memory: 1436k freed -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 1024 bind 1024) -IP-Config: Incomplete network configuration information. -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -VFS: Mounted root (ext2 filesystem). -Freeing unused kernel memory: 44k init -init started: BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname -Configuring lo... -Configuring eth0... -Configuring Gateway... - -Please press Enter to activate this console. - -ELPT860 login: root -Password: -Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz) - - a8888b. - d888888b. - 8P"YP"Y88 - _ _ 8|o||o|88 - | | |_| 8' .88 - | | _ ____ _ _ _ _ 8`._.' Y8. - | | | | _ \| | | |\ \/ / d/ `8b. - | |___ | | | | | |_| |/ \ .dP . Y8b. - |_____||_|_| |_|\____|\_/\_/ d8:' " `::88b. - d8" `Y88b - :8P ' :888 - 8a. : _a88P - ._/"Yaa_ : .| 88P| - \ YP" `| 8P `. - / \._____.d| .' - `--..__)888888P`._.' -login[21]: root login on `ttyS0' - - - -BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash) -Enter 'help' for a list of built-in commands. - -root@ELPT860:~ # diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c deleted file mode 100644 index 81820cb3e6..0000000000 --- a/board/LEOX/elpt860/elpt860.c +++ /dev/null @@ -1,336 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** - * SPDX-License-Identifier: GPL-2.0+ -** -**===================================================================== -*/ - -/* -** Note 1: In this file, you have to provide the following functions: -** ------ -** int board_early_init_f(void) -** int checkboard(void) -** phys_size_t initdram(int board_type) -** called from 'board_init_f()' into 'common/board.c' -** -** void reset_phy(void) -** called from 'board_init_r()' into 'common/board.c' -*/ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint init_sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, - 0xFFFFFC04, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */ - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, - 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */ - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34, - 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */ -}; - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, - 0xFF0FFC00, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, - 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00, - 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00, - 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */ - _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00, - 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04, - 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_, - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */ -}; - -/* ------------------------------------------------------------------------- */ - -#define CONFIG_SYS_PC4 0x0800 - -#define CONFIG_SYS_DS1 CONFIG_SYS_PC4 - -/* - * Very early board init code (fpga boot, etc.) - */ -int board_early_init_f (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Light up the red led on ELPT860 pcb (DS1) (PCDAT) - */ - immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1; /* PCDAT (DS1 = 0) */ - immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1; /* PCPAR (0=general purpose I/O) */ - immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1; /* PCDIR (I/O: 0=input, 1=output) */ - - return (0); /* success */ -} - -/* - * Check Board Identity: - * - * Test ELPT860 ID string - * - * Return 1 if no second DRAM bank, otherwise returns 0 - */ - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - if ((i < 0) || strncmp(buf, "ELPT860", 7)) - printf ("### No HW ID - assuming ELPT860\n"); - - return (0); /* success */ -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - - /* - * This sequence initializes SDRAM chips on ELPT860 board - */ - upmconfig (UPMA, (uint *) init_sdram_table, - sizeof (init_sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = 0x18002111; - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */ - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - /* - * The following value is used as an address (i.e. opcode) for - * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If - * the port size is 32bit the SDRAM does NOT "see" the lower two - * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for - * MICRON SDRAMs: - * -> 0 00 010 0 010 - * | | | | +- Burst Length = 4 - * | | | +----- Burst Type = Sequential - * | | +------- CAS Latency = 2 - * | +----------- Operating Mode = Standard - * +-------------- Write Burst Mode = Programmed Burst Length - */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, - SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, - SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; - /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); - /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size_b0 < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - { - unsigned long reg; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int -dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define CONFIG_SYS_PA1 0x4000 -#define CONFIG_SYS_PA2 0x2000 - -#define CONFIG_SYS_LBKs (CONFIG_SYS_PA2 | CONFIG_SYS_PA1) - -void reset_phy (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect - * and no AUI loopback - */ - immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs; /* PADAT (LBK eth 1&2 = 0) */ - immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs; /* PAPAR (0=general purpose I/O) */ - immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs; /* PADIR (I/O: 0=input, 1=output) */ -} diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c deleted file mode 100644 index 0377c8970c..0000000000 --- a/board/LEOX/elpt860/flash.c +++ /dev/null @@ -1,602 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** - * SPDX-License-Identifier: GPL-2.0+ -** -**===================================================================== -*/ - -/* -** Note 1: In this file, you have to provide the following variable: -** ------ -** flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS] -** 'flash_info_t' structure is defined into 'include/flash.h' -** and defined as extern into 'common/cmd_flash.c' -** -** Note 2: In this file, you have to provide the following functions: -** ------ -** unsigned long flash_init(void) -** called from 'board_init_r()' into 'common/board.c' -** -** void flash_print_info(flash_info_t *info) -** called from 'do_flinfo()' into 'common/cmd_flash.c' -** -** int flash_erase(flash_info_t *info, -** int s_first, -** int s_last) -** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c' -** -** int write_buff (flash_info_t *info, -** uchar *src, -** ulong addr, -** ulong cnt) -** called from 'flash_write()' into 'common/cmd_flash.c' -*/ - -#include -#include - - -#ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Internal Functions - */ -static void flash_get_offsets (ulong base, flash_info_t *info); -static ulong flash_get_size (volatile unsigned char *addr, flash_info_t *info); - -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int write_byte (flash_info_t *info, ulong dest, uchar data); - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void -flash_get_offsets (ulong base, - flash_info_t *info) -{ - int i; - -#define SECTOR_64KB 0x00010000 - - /* set up sector start adress table */ - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = base + (i * SECTOR_64KB); - } -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if ( info->flash_id == FLASH_UNKNOWN ) - { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ( info->flash_id & FLASH_VENDMASK ) - { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_STM: printf ("STM (Thomson) "); break; - default: printf ("Unknown Vendor "); break; - } - - switch ( info->flash_id & FLASH_TYPEMASK ) - { - case FLASH_AM040: printf ("AM29F040 (4 Mbits)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) - { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong -flash_get_size (volatile unsigned char *addr, - flash_info_t *info) -{ - short i; - uchar value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x90; - - value = addr[0]; - - switch ( value ) - { - /* case AMD_MANUFACT: */ - case 0x01: - info->flash_id = FLASH_MAN_AMD; - break; - /* case FUJ_MANUFACT: */ - case 0x04: - info->flash_id = FLASH_MAN_FUJ; - break; - /* case STM_MANUFACT: */ - case 0x20: - info->flash_id = FLASH_MAN_STM; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch ( value ) - { - case STM_ID_F040B: - case AMD_ID_F040B: - info->flash_id += FLASH_AM040; /* 4 Mbits = 512k * 8 */ - info->sector_count = 8; - info->size = 0x00080000; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start adress table */ - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = base + (i * 0x00010000); - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if ( info->flash_id != FLASH_UNKNOWN ) - { - addr = (volatile unsigned char *)info->start[0]; - - *addr = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int -flash_erase (flash_info_t *info, - int s_first, - int s_last) -{ - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ( (s_first < 0) || (s_first > s_last) ) - { - if ( info->flash_id == FLASH_UNKNOWN ) - { - printf ("- missing\n"); - } - else - { - printf ("- no sectors to erase\n"); - } - return ( 1 ); - } - - if ( (info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP) ) - { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return ( 1 ); - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) - { - if ( info->protect[sect] ) - { - prot++; - } - } - - if ( prot ) - { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } - else - { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) - { - if (info->protect[sect] == 0) /* not protected */ - { - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if ( flag ) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if ( l_sect < 0 ) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - while ( (addr[0] & 0x80) != 0x80 ) - { - if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT ) - { - printf ("Timeout\n"); - return ( 1 ); - } - /* show that we're waiting */ - if ( (now - last) > 1000 ) /* every second */ - { - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf (" done\n"); - - return ( 0 ); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int -write_buff (flash_info_t *info, - uchar *src, - ulong addr, - ulong cnt) -{ - ulong cp, wp, data; - uchar bdata; - int i, l, rc; - - if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 ) - { - /* Width of the data bus: 8 bits */ - - wp = addr; - - while ( cnt ) - { - bdata = *src++; - - if ( (rc = write_byte(info, wp, bdata)) != 0 ) - { - return (rc); - } - - ++wp; - --cnt; - } - - return ( 0 ); - } - else - { - /* Width of the data bus: 32 bits */ - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ( (l = addr - wp) != 0 ) - { - data = 0; - for (i=0, cp=wp; i0; ++i) - { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) - { - data = (data << 8) | (*(uchar *)cp); - } - - if ( (rc = write_word(info, wp, data)) != 0 ) - { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while ( cnt >= 4 ) - { - data = 0; - for (i=0; i<4; ++i) - { - data = (data << 8) | *src++; - } - if ( (rc = write_word(info, wp, data)) != 0 ) - { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if ( cnt == 0 ) - { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) - { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) - { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); - } -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_word (flash_info_t *info, - ulong dest, - ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ( (*((vu_long *)dest) & data) != data ) - { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if ( flag ) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) ) - { - if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) - { - return (1); - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_byte (flash_info_t *info, - ulong dest, - uchar data) -{ - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ( (*((volatile unsigned char *)dest) & data) != data ) - { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((volatile unsigned char *)dest) = data; - - /* re-enable interrupts if necessary */ - if ( flag ) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) ) - { - if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) - { - return (1); - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds deleted file mode 100644 index f9c2bebd2d..0000000000 --- a/board/LEOX/elpt860/u-boot.lds +++ /dev/null @@ -1,104 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** - * SPDX-License-Identifier: GPL-2.0+ -** -**===================================================================== -*/ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - common/libcommon.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - board/LEOX/elpt860/libelpt860.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) -/* drivers/rtc/librtc.o (.text*) */ - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug deleted file mode 100644 index ce81046e73..0000000000 --- a/board/LEOX/elpt860/u-boot.lds.debug +++ /dev/null @@ -1,126 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** - * SPDX-License-Identifier: GPL-2.0+ -** -**===================================================================== -*/ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o (.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig new file mode 100644 index 0000000000..ac3fe3fbcb --- /dev/null +++ b/board/LaCie/edminiv2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_EDMINIV2 + +config SYS_BOARD + default "edminiv2" + +config SYS_VENDOR + default "LaCie" + +config SYS_CONFIG_NAME + default "edminiv2" + +endif diff --git a/board/LaCie/edminiv2/MAINTAINERS b/board/LaCie/edminiv2/MAINTAINERS new file mode 100644 index 0000000000..e0591f4b80 --- /dev/null +++ b/board/LaCie/edminiv2/MAINTAINERS @@ -0,0 +1,6 @@ +EDMINIV2 BOARD +M: Albert ARIBAUD +S: Maintained +F: board/LaCie/edminiv2/ +F: include/configs/edminiv2.h +F: configs/edminiv2_defconfig diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile index 482f118185..035f6865d9 100644 --- a/board/LaCie/edminiv2/Makefile +++ b/board/LaCie/edminiv2/Makefile @@ -9,26 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS := edminiv2.o ../common/common.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := edminiv2.o ../common/common.o diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig new file mode 100644 index 0000000000..ba460dba45 --- /dev/null +++ b/board/LaCie/net2big_v2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NET2BIG_V2 + +config SYS_BOARD + default "net2big_v2" + +config SYS_VENDOR + default "LaCie" + +config SYS_CONFIG_NAME + default "lacie_kw" + +endif diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS new file mode 100644 index 0000000000..205c75e4cb --- /dev/null +++ b/board/LaCie/net2big_v2/MAINTAINERS @@ -0,0 +1,11 @@ +NET2BIG_V2 BOARD +#M: - +S: Maintained +F: board/LaCie/net2big_v2/ +F: include/configs/lacie_kw.h +F: configs/d2net_v2_defconfig + +NET2BIG_V2 BOARD +M: Simon Guinot +S: Maintained +F: configs/net2big_v2_defconfig diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile index ad402318ff..f3074af256 100644 --- a/board/LaCie/net2big_v2/Makefile +++ b/board/LaCie/net2big_v2/Makefile @@ -9,36 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o ../common/common.o +obj-y := net2big_v2.o ../common/common.o ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),) -COBJS += ../common/cpld-gpio-bus.o +obj-y += ../common/cpld-gpio-bus.o endif - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 4c3a9ba785..263bb5426c 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include @@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* GPIO configuration */ - kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, - NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); + mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, + NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -77,7 +77,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig new file mode 100644 index 0000000000..930b822dfb --- /dev/null +++ b/board/LaCie/netspace_v2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NETSPACE_V2 + +config SYS_BOARD + default "netspace_v2" + +config SYS_VENDOR + default "LaCie" + +config SYS_CONFIG_NAME + default "lacie_kw" + +endif diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS new file mode 100644 index 0000000000..55fd50d4eb --- /dev/null +++ b/board/LaCie/netspace_v2/MAINTAINERS @@ -0,0 +1,14 @@ +NETSPACE_V2 BOARD +M: Simon Guinot +S: Maintained +F: board/LaCie/netspace_v2/ +F: include/configs/lacie_kw.h +F: configs/inetspace_v2_defconfig +F: configs/netspace_max_v2_defconfig +F: configs/netspace_v2_defconfig + +NETSPACE_LITE_V2 BOARD +#M: - +S: Maintained +F: configs/netspace_lite_v2_defconfig +F: configs/netspace_mini_v2_defconfig diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile index a65b96506f..47778d8472 100644 --- a/board/LaCie/netspace_v2/Makefile +++ b/board/LaCie/netspace_v2/Makefile @@ -9,27 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o ../common/common.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := netspace_v2.o ../common/common.o diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 3773587cc6..17e629622f 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, - NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); + mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, + NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -73,7 +73,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig new file mode 100644 index 0000000000..75a2fc5a75 --- /dev/null +++ b/board/LaCie/wireless_space/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WIRELESS_SPACE + +config SYS_BOARD + default "wireless_space" + +config SYS_VENDOR + default "LaCie" + +config SYS_CONFIG_NAME + default "wireless_space" + +endif diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS new file mode 100644 index 0000000000..c32ecb8b73 --- /dev/null +++ b/board/LaCie/wireless_space/MAINTAINERS @@ -0,0 +1,6 @@ +WIRELESS_SPACE BOARD +M: Albert ARIBAUD +S: Maintained +F: board/LaCie/wireless_space/ +F: include/configs/wireless_space.h +F: configs/wireless_space_defconfig diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile index a65b96506f..90a84f4892 100644 --- a/board/LaCie/wireless_space/Makefile +++ b/board/LaCie/wireless_space/Makefile @@ -9,27 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o ../common/common.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := wireless_space.o ../common/common.o diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c index 2dc5018560..8620e4b5d1 100644 --- a/board/LaCie/wireless_space/wireless_space.c +++ b/board/LaCie/wireless_space/wireless_space.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include @@ -97,8 +97,8 @@ struct mv88e61xx_config swcfg = { int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, - WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ kirkwood_mpp_conf(kwmpp_config, NULL); @@ -112,7 +112,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig new file mode 100644 index 0000000000..4dd49c4452 --- /dev/null +++ b/board/Marvell/aspenite/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ASPENITE + +config SYS_BOARD + default "aspenite" + +config SYS_VENDOR + default "Marvell" + +config SYS_SOC + default "armada100" + +config SYS_CONFIG_NAME + default "aspenite" + +endif diff --git a/board/Marvell/aspenite/MAINTAINERS b/board/Marvell/aspenite/MAINTAINERS new file mode 100644 index 0000000000..a77d30eb78 --- /dev/null +++ b/board/Marvell/aspenite/MAINTAINERS @@ -0,0 +1,6 @@ +ASPENITE BOARD +M: Prafulla Wadaskar +S: Maintained +F: board/Marvell/aspenite/ +F: include/configs/aspenite.h +F: configs/aspenite_defconfig diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile index 1ba7e2a05a..726d0e43d5 100644 --- a/board/Marvell/aspenite/Makefile +++ b/board/Marvell/aspenite/Makefile @@ -7,24 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := aspenite.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := aspenite.o diff --git a/board/Marvell/common/ecctest.c b/board/Marvell/common/ecctest.c deleted file mode 100644 index 0a9a2a4c4f..0000000000 --- a/board/Marvell/common/ecctest.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2001 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifdef ECC_TEST -static inline void ecc_off (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000; -} - -static inline void ecc_on (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000; -} - -static int putshex (const char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - printf ("%02x", buf[i]); - } - return 0; -} - -static int char_memcpy (void *d, const void *s, int len) -{ - int i; - char *cd = d; - const char *cs = s; - - for (i = 0; i < len; i++) { - *(cd++) = *(cs++); - } - return 0; -} - -static int memory_test (char *buf) -{ - const char src[][16] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}, - {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, - 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}, - {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}, - {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, - 0x08, 0x08, 0x08, 0x08, 0x08, 0x08}, - {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, - {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, - {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}, - {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, - {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}, - {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}, - {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }; - const int foo[] = { 0 }; - int i, j, a; - - printf ("\ntest @ %d %p\n", foo[0], buf); - for (i = 0; i < 12; i++) { - for (a = 0; a < 8; a++) { - const char *s = src[i] + a; - int align = (unsigned) (s) & 0x7; - - /* ecc_off(); */ - memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - /* ecc_off(); */ - char_memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - } - } - - return 0; -} -#endif diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c deleted file mode 100644 index 32f226dcc3..0000000000 --- a/board/Marvell/common/flash.c +++ /dev/null @@ -1,1056 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * flash.c - flash support for the 512k, 8bit boot flash - and the 8MB 32bit extra flash on the DB64360 - * most of this file was based on the existing U-Boot - * flash drivers. - * - * written or collected and sometimes rewritten by - * Ingo Assmus - * - */ - -#include -#include -#include "../include/mv_gen_reg.h" -#include "../include/memory.h" -#include "intel_flash.h" - -#define FLASH_ROM 0xFFFD /* unknown flash type */ -#define FLASH_RAM 0xFFFE /* unknown flash type */ -#define FLASH_MAN_UNKNOWN 0xFFFF0000 - -/* #define DEBUG */ - -/* Intel flash commands */ -int flash_erase_intel (flash_info_t * info, int s_first, int s_last); -int write_word_intel (bank_addr_t addr, bank_word_t value); - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (int portwidth, vu_long * addr, - flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long size_b0 = 0, size_b1 = 0; - unsigned long base, flash_size; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* the boot flash */ - base = CONFIG_SYS_FLASH_BASE; - size_b0 = - flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base, - &flash_info[0]); - - printf ("[%ldkB@%lx] ", size_b0 / 1024, base); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20); - } - - base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE); -/* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/ - for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - unsigned long size = - flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH, - (vu_long *) base, &flash_info[i]); - - printf ("[%ldMB@%lx] ", size >> 20, base); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - if (i == 1) { - printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b1, size_b1 << 20); - } - break; - } - size_b1 += size; - base += size; - } - - flash_size = size_b0 + size_b1; - return flash_size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - int sector_size; - - if (!info->sector_count) - return; - - /* set up sector start address table */ - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - case FLASH_28F128J3A: - case FLASH_28F640J3A: - case FLASH_RAM: - /* this chip has uniformly spaced sectors */ - sector_size = info->size / info->sector_count; - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sector_size); - break; - default: - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64 Mbit)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128 Mbit)\n"); - break; - case FLASH_ROM: - printf ("ROM\n"); - break; - case FLASH_RAM: - printf ("RAM\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if ((info->size >> 20) > 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", - info->size >> 10, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static inline void flash_cmd (int width, volatile unsigned char *addr, - int offset, unsigned char cmd) -{ - /* supports 1x8, 1x16, and 2x16 */ - /* 2x8 and 4x8 are not supported */ - if (width == 4) { - /* assuming chips are in 16 bit mode */ - /* 2x16 */ - unsigned long cmd32 = (cmd << 16) | cmd; - - *(volatile unsigned long *) (addr + offset * 2) = cmd32; - } else { - /* 1x16 or 1x8 */ - *(volatile unsigned char *) (addr + offset) = cmd; - } -} - -static ulong -flash_get_size (int portwidth, vu_long * addr, flash_info_t * info) -{ - short i; - volatile unsigned char *caddr = (unsigned char *) addr; - volatile unsigned short *saddr = (unsigned short *) addr; - volatile unsigned long *laddr = (unsigned long *) addr; - char old[2], save; - ulong id = 0, manu = 0, base = (ulong) addr; - -#ifdef DEBUG - printf ("%s: enter\n", __FUNCTION__); -#endif - info->portwidth = portwidth; - - save = *caddr; - - flash_cmd (portwidth, caddr, 0, 0xf0); - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - - old[0] = caddr[0]; - old[1] = caddr[1]; - - - if (old[0] != 0xf0) { - flash_cmd (portwidth, caddr, 0, 0xf0); - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - - if (*caddr == 0xf0) { - /* this area is ROM */ - *caddr = save; - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; - } - } else { - *caddr = 0; - - udelay (10); - - if (*caddr == 0) { - /* this area is RAM */ - *caddr = save; - info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; - } - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - } - - /* Write auto select command: read Manufacturer ID */ - flash_cmd (portwidth, caddr, 0x555, 0xAA); - flash_cmd (portwidth, caddr, 0x2AA, 0x55); - flash_cmd (portwidth, caddr, 0x555, 0x90); - - udelay (10); - - if ((caddr[0] == old[0]) && (caddr[1] == old[1])) { - - /* this area is ROM */ - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; -#ifdef DEBUG - } else { - printf ("%px%d: %02x:%02x -> %02x:%02x\n", - caddr, portwidth, old[0], old[1], caddr[0], caddr[1]); -#endif - } - - switch (portwidth) { - case 1: - manu = caddr[0]; - manu |= manu << 16; - id = caddr[1]; - break; - case 2: - manu = saddr[0]; - manu |= manu << 16; - id = saddr[1]; - id |= id << 16; - break; - case 4: - manu = laddr[0]; - id = laddr[1]; - break; - } - -#ifdef DEBUG - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("\n%08lx:%08lx:%08lx\n", base, manu, id); - printf ("%08lx %08lx %08lx %08lx\n", - laddr[0], laddr[1], laddr[2], laddr[3]); -#endif - - switch (manu) { - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("Unknown Mfr [%08lx]:%08lx\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (id) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth = 1; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth = 1; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth = 1; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth = 1; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth = 1; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth = 1; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth = 1; - break; /* => 512 kB */ - - case INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 128 * 1024 * 64; /* 128kbytes x 64 blocks */ - info->chipwidth = 2; - if (portwidth == 4) - info->size *= 2; /* 2x16 */ - break; - - case INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 128 * 1024 * 128; /* 128kbytes x 128 blocks */ - info->chipwidth = 2; - if (portwidth == 4) - info->size *= 2; /* 2x16 */ - break; - - default: - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("Unknown id %lx:[%lx]\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->chipwidth = 1; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets (base, info); - - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0)=0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *) (info->start[i]); - saddr = (volatile unsigned short *) (info->start[i]); - laddr = (volatile unsigned long *) (info->start[i]); - if (portwidth == 1) - info->protect[i] = caddr[2] & 1; - else if (portwidth == 2) - info->protect[i] = saddr[2] & 1; - else - info->protect[i] = laddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *) info->start[0]; - - flash_cmd (portwidth, caddr, 0, 0xF0); /* reset bank */ - } - - return (info->size); -} - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile unsigned char *addr = (uchar *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - -/* modified to support 2x16 Intel flash */ -/* Note that the code will not exit on a flash erasure error or timeout */ -/* but will print and error message and continue processing sectors */ -/* until they are all erased. */ -/* 10-16-2002 P. Marchese */ - ulong mask; - int timeout; - - if (info->portwidth == 4) -/* { - printf ("- Warning: erasing of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - { - /* make sure it's Intel flash */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - /* yup! it's an Intel flash */ - /* is it 16-bits wide? */ - if (info->chipwidth == 2) { - /* yup! it's 16-bits wide */ - /* are there any sectors to process? */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("Error: There are no sectors to erase\n"); - printf ("Either sector %d is less than zero\n", s_first); - printf ("or sector %d is greater than sector %d\n", s_first, s_last); - return 1; - } - /* check for protected sectors */ - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) - if (info->protect[sect]) - prot++; - /* if variable "prot" is nonzero, there are protected sectors */ - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - /* Clear the status register */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_CLR_STAT); - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - /* is the sector unprotected? */ - if (info->protect[sect] == 0) { /* not protected */ - /* issue the single block erase command, 0x20 */ - flash_cmd (info->portwidth, - (volatile unsigned - char *) info-> - start[sect], 0, - CHIP_CMD_ERASE1); - /* issue the erase confirm command, 0xD0 */ - flash_cmd (info->portwidth, - (volatile unsigned - char *) info-> - start[sect], 0, - CHIP_CMD_ERASE2); - l_sect = sect; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - /* poll for erasure completion */ - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - /* setup the status register mask */ - mask = CHIP_STAT_RDY | - (CHIP_STAT_RDY << 16); - /* init. the timeout counter */ - start = get_timer (0); - /* keep looping while the flash is not ready */ - /* exit the loop by timing out or the flash */ - /* becomes ready again */ - timeout = 0; - while ((* - (volatile unsigned - long *) info-> - start[sect] & mask) != - mask) { - /* has the timeout limit been reached? */ - if (get_timer (start) - > - CONFIG_SYS_FLASH_ERASE_TOUT) - { - /* timeout limit reached */ - printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]); - printf ("Continuing with next sector\n"); - timeout = 1; - goto timed_out_error; - } - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info-> - portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - } - /* did we timeout? */ - timed_out_error:if (timeout == 0) - { - /* didn't timeout, so check the status register */ - /* create the status mask to check for errors */ - mask = CHIP_STAT_ECLBS; - mask = mask | (mask << - 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info-> - portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - /* are there any errors? */ - if ((* - (volatile - unsigned long *) - info-> - start[sect] & - mask) != 0) { - /* We got an erasure error */ - printf ("Flash erasure error at address 0x%08lx\n", info->start[sect]); - printf ("Continuing with next sector\n"); - /* reset the flash */ - flash_cmd - (info-> - portwidth, - addr, - 0, - CHIP_CMD_RST); - } - } - /* erasure completed without errors */ - /* reset the flash */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RST); - } /* end if not protected */ - } /* end for loop */ - printf ("Flash erasure done\n"); - return 0; - } else { - /* The Intel flash is not 16-bit wide */ - /* print and error message and return */ - /* NOTE: you can add routines here to handle other size flash */ - printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8); - printf ("The erasure code only handles Intel 16-bit wide flash memory\n"); - return 1; - } - } else { - /* Not Intel flash so return an error as a write timeout */ - /* NOTE: if it's another type flash, stick its routine here */ - printf ("Error: The flash device is not Intel type\n"); - printf ("The erasure code only supports Intel flash in a 32-bit port width\n"); - return 1; - } - } - - /* end 32-bit wide flash code */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 1; /* Rom can not be erased */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { /* RAM just copy 0s to RAM */ - for (sect = s_first; sect <= s_last; sect++) { - int sector_size = info->size / info->sector_count; - - addr = (uchar *) (info->start[sect]); - memset ((void *) addr, 0, sector_size); - } - return 0; - } - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { /* Intel works spezial */ - return flash_erase_intel (info, - (unsigned short) s_first, - (unsigned short) s_last); - } -#if 0 - if ((info->flash_id == FLASH_UNKNOWN) || /* Flash is unknown to PPCBoot */ - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } -#endif - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - flash_cmd (info->portwidth, addr, 0x555, 0xAA); /* start erase routine */ - flash_cmd (info->portwidth, addr, 0x2AA, 0x55); - flash_cmd (info->portwidth, addr, 0x555, 0x80); - flash_cmd (info->portwidth, addr, 0x555, 0xAA); - flash_cmd (info->portwidth, addr, 0x2AA, 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (uchar *) (info->start[sect]); - flash_cmd (info->portwidth, addr, 0, 0x30); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *) (info->start[l_sect]); - /* broken for 2x16: TODO */ - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned char *) info->start[0]; - flash_cmd (info->portwidth, addr, 0, 0xf0); - flash_cmd (info->portwidth, addr, 0, 0xf0); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -/* broken for 2x16: TODO */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - -/* Commented out since the below code should work for 32-bit(2x 16 flash) */ -/* 10-16-2002 P. Marchese */ -/* if(info->portwidth==4) return 1; */ -/* if(info->portwidth==4) { - printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 0; - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - memcpy ((void *) addr, src, cnt); - return 0; - } - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -/* broken for 2x16: TODO */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile unsigned char *addr = (uchar *) (info->start[0]); - ulong start; - int flag, i; - ulong mask; - -/* modified so that it handles 32-bit(2x16 Intel flash programming */ -/* 10-16-2002 P. Marchese */ - - if (info->portwidth == 4) -/* { - printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - { - /* make sure it's Intel flash */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - /* yup! it's an Intel flash */ - /* is it 16-bits wide? */ - if (info->chipwidth == 2) { - /* yup! it's 16-bits wide */ - /* so we know how to program it */ - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - /* Clear the status register */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_CLR_STAT); - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* 1st cycle of word/byte program */ - /* write 0x40 to the location to program */ - flash_cmd (info->portwidth, (uchar *) dest, 0, - CHIP_CMD_PROG); - /* 2nd cycle of word/byte program */ - /* write the data to the destination address */ - *(ulong *) dest = data; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - /* setup the status register mask */ - mask = CHIP_STAT_RDY | (CHIP_STAT_RDY << 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - /* init. the timeout counter */ - start = get_timer (0); - /* keep looping while the flash is not ready */ - /* exit the loop by timing out or the flash */ - /* becomes ready again */ -/* 11-13-2002 Paul Marchese */ -/* modified while loop conditional statement */ -/* because we were always timing out. */ -/* there is a type mismatch, "addr[0]" */ -/* returns a byte but "mask" is a 32-bit value */ - while ((*(volatile unsigned long *) info-> - start[0] & mask) != mask) -/* original code */ -/* while (addr[0] & mask) != mask) */ - { - /* has the timeout limit been reached? */ - if (get_timer (start) > - CONFIG_SYS_FLASH_WRITE_TOUT) { - /* timeout limit reached */ - printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data); - /* reset the flash */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RST); - return (1); - } - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - } - /* flash is ready, so check the status */ - /* create the status mask to check for errors */ - mask = CHIP_STAT_DPS | CHIP_STAT_VPPS | - CHIP_STAT_PSLBS; - mask = mask | (mask << 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - /* are there any errors? */ - if ((addr[0] & mask) != 0) { - /* We got a one of the following errors: */ - /* Voltage range, Device protect, or programming */ - /* return the error as a device timeout */ - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - printf ("Flash programming error at address 0x%08lx\n", dest); - printf ("Flash status register contains 0x%08lx\n", (unsigned long) addr[0]); - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - return 1; - } - /* write completed without errors */ - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - return 0; - } else { - /* it's not 16-bits wide, so return an error as a write timeout */ - /* NOTE: you can add routines here to handle other size flash */ - printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8); - printf ("The write code only handles Intel 16-bit wide flash memory\n"); - return 1; - } - } else { - /* not Intel flash so return an error as a write timeout */ - /* NOTE: if it's another type flash, stick its routine here */ - printf ("Error: The flash device is not Intel type\n"); - printf ("The code only supports Intel flash in a 32-bit port width\n"); - return 1; - } - } - - /* end of 32-bit flash code */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 1; - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - *(unsigned long *) dest = data; - return 0; - } - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - unsigned short low = data & 0xffff; - unsigned short hi = (data >> 16) & 0xffff; - int ret = write_word_intel ((bank_addr_t) dest, hi); - - if (!ret) - ret = write_word_intel ((bank_addr_t) (dest + 2), - low); - - return ret; - } - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* first, perform an unlock bypass command to speed up flash writes */ - addr[0x555] = 0xAA; - addr[0x2AA] = 0x55; - addr[0x555] = 0x20; - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *) &data; - - addr[0] = 0xA0; - *(((char *) dest) + i) = data_ch[i]; - udelay (10); /* XXX */ - } - - /* we're done, now do an unlock bypass reset */ - addr[0] = 0x90; - addr[0] = 0x00; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c deleted file mode 100644 index abdde868a7..0000000000 --- a/board/Marvell/common/i2c.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - * extra improvments by Brain Waite - */ -#include -#include -#include -#include -#include "../include/mv_gen_reg.h" -#include "../include/core.h" - -#define MAX_I2C_RETRYS 10 -#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ -#undef DEBUG_I2C -/*#define DEBUG_I2C*/ - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -void i2c_init (int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualN = 0, actualM = 0; - unsigned int control, status; - unsigned int minMargin = 0xffffffff; - unsigned int tclk = CONFIG_SYS_TCLK; - unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ - - DP (puts ("i2c_init\n")); -/* gtI2cMasterInit */ - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - power = 2 << n; /* power = 2^(n+1) */ - freq = tclk / (10 * (m + 1) * power); - if (i2cFreq > freq) - margin = i2cFreq - freq; - else - margin = freq - i2cFreq; - if (margin < minMargin) { - minMargin = margin; - actualN = n; - actualM = m; - } - } - } - - DP (puts ("setup i2c bus\n")); - - /* Setup bus */ -/* gtI2cReset */ - GT_REG_WRITE (I2C_SOFT_RESET, 0); - - DP (puts ("udelay...\n")); - - udelay (I2C_DELAY); - - DP (puts ("set baudrate\n")); - - GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); - GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - - udelay (I2C_DELAY * 10); - - DP (puts ("read control, baudrate\n")); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - GT_REG_READ (I2C_CONTROL, &control); -} - -static uchar i2c_start (void) -{ /* DB64360 checked -> ok */ - unsigned int control, status; - int count = 0; - - DP (puts ("i2c_start\n")); - - /* Set the start bit */ - -/* gtI2cGenerateStartBit() */ - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 5); /* generate the I2C_START_BIT */ - GT_REG_WRITE (I2C_CONTROL, control); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - - count = 0; - while ((status & 0xff) != 0x08) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - return (0); -} - -static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - int count = 0; - - DP (puts ("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) { - bits = 10; - } - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE (I2C_DATA, data); - /* assert the address */ - RESET_REG_BITS (I2C_CONTROL, BIT3); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - if (bits == 10) { - printf ("10 bit I2C addressing not yet implemented\n"); - return (0xff); - } - - return (0); -} - -static uchar i2c_get_data (uchar * return_data, int len) -{ - - unsigned int data, status = 0; - int count = 0; - - DP (puts ("i2c_get_data\n")); - - while (len) { - - /* Get and return the data */ - - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY * 5); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - udelay (I2C_DELAY); - if (count > 2) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return 0; - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ (I2C_DATA, &data); - len--; - *return_data = (uchar) data; - return_data++; - } - RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3); - while ((status & 0xff) != 0x58) { - udelay (I2C_DELAY); - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */ - - return (0); -} - -static uchar i2c_write_data (unsigned int *data, int len) -{ - unsigned int status; - int count = 0; - unsigned int temp; - unsigned int *temp_ptr = data; - - DP (puts ("i2c_write_data\n")); - - while (len) { - temp = (unsigned int) (*temp_ptr); - GT_REG_WRITE (I2C_DATA, temp); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } -/* 11-14-2002 Paul Marchese */ -/* Can't have the write issuing a stop command */ -/* it's wrong to have a stop bit in read stream or write stream */ -/* since we don't know if it's really the end of the command */ -/* or whether we have just send the device address + offset */ -/* we will push issuing the stop command off to the original */ -/* calling function */ - /* set the interrupt bit in the control register */ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 3)); - udelay (I2C_DELAY * 10); - return (0); -} - -/* 11-14-2002 Paul Marchese */ -/* created this function to get the i2c_write() */ -/* function working properly. */ -/* function to write bytes out on the i2c bus */ -/* this is identical to the function i2c_write_data() */ -/* except that it requires a buffer that is an */ -/* unsigned character array. You can't use */ -/* i2c_write_data() to send an array of unsigned characters */ -/* since the byte of interest ends up on the wrong end of the bus */ -/* aah, the joys of big endian versus little endian! */ -/* */ -/* returns 0 = success */ -/* anything other than zero is failure */ -static uchar i2c_write_byte (unsigned char *data, int len) -{ - unsigned int status; - int count = 0; - unsigned int temp; - unsigned char *temp_ptr = data; - - DP (puts ("i2c_write_byte\n")); - - while (len) { - /* Set and assert the data */ - temp = *temp_ptr; - GT_REG_WRITE (I2C_DATA, temp); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } -/* Can't have the write issuing a stop command */ -/* it's wrong to have a stop bit in read stream or write stream */ -/* since we don't know if it's really the end of the command */ -/* or whether we have just send the device address + offset */ -/* we will push issuing the stop command off to the original */ -/* calling function */ -/* GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */ - /* set the interrupt bit in the control register */ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 3)); - udelay (I2C_DELAY * 10); - - return (0); -} - -static uchar -i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, - int alen) -{ - uchar status; - unsigned int table[2]; - -/* initialize the table of address offset bytes */ -/* utilized for 2 byte address offsets */ -/* NOTE: the order is high byte first! */ - table[1] = offset & 0xff; /* low byte */ - table[0] = offset / 0x100; /* high byte */ - - DP (puts ("i2c_set_dev_offset\n")); - - status = i2c_select_device (dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } -/* check the address offset length */ - if (alen == 0) - /* no address offset */ - return (0); - else if (alen == 1) { - /* 1 byte address offset */ - status = i2c_write_data (&offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else if (alen == 2) { - /* 2 bytes address offset */ - status = i2c_write_data (table, 2); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else { - /* address offset unknown or not supported */ - printf ("Address length offset %d is not supported\n", alen); - return 1; - } - return 0; /* sucessful completion */ -} - -int -i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_read\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_start (); - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - /* set the i2c frequency again */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_start (); - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction restart failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_select_device (dev_addr, 1, 0); /* send the slave address */ - if (status) { -#ifdef DEBUG_I2C - printf ("Address not acknowledged: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_get_data (data, len); - if (status) { -#ifdef DEBUG_I2C - printf ("Data not received: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} - -/* 11-14-2002 Paul Marchese */ -/* Function to set the I2C stop bit */ -void i2c_stop (void) -{ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); -} - -/* 11-14-2002 Paul Marchese */ -/* I2C write function */ -/* dev_addr = device address */ -/* offset = address offset */ -/* alen = length in bytes of the address offset */ -/* data = pointer to buffer to read data into */ -/* len = # of bytes to read */ -/* */ -/* returns 0 = succesful */ -/* anything but zero is failure */ -int -i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_write\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_start (); /* send a start bit */ - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - - status = i2c_write_byte (data, len); /* write the data */ - if (status) { -#ifdef DEBUG_I2C - printf ("Data not written: 0x%02x\n", status); -#endif - return status; - } - /* issue a stop bit */ - i2c_stop (); - return 0; -} - -/* 11-14-2002 Paul Marchese */ -/* function to determine if an I2C device is present */ -/* chip = device address of chip to check for */ -/* */ -/* returns 0 = sucessful, the device exists */ -/* anything other than zero is failure, no device */ -int i2c_probe (uchar chip) -{ - - /* We are just looking for an back. */ - /* To see if the device/chip is there */ - -#ifdef DEBUG_I2C - unsigned int i2c_status; -#endif - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_probe\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_start (); /* send a start bit */ - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return (int) status; - } - - status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address: 0x%02x\n", status); -#endif - return (int) status; - } -#ifdef DEBUG_I2C - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status); - printf ("address %#x returned %#x\n", chip, i2c_status); -#endif - /* issue a stop bit */ - i2c_stop (); - return 0; /* successful completion */ -} diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c deleted file mode 100644 index d6970d4e95..0000000000 --- a/board/Marvell/common/intel_flash.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the marvell db64360 eval board by - * Ingo Assmus - */ - -#include -#include -#include "../include/mv_gen_reg.h" -#include "../include/memory.h" -#include "intel_flash.h" - - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -static void bank_reset (flash_info_t * info, int sect) -{ - bank_addr_t addrw, eaddrw; - - addrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (addrw); - - while (addrw < eaddrw) { -#ifdef FLASH_DEBUG - printf (" writing reset cmd to addr 0x%08lx\n", - (unsigned long) addrw); -#endif - *addrw = BANK_CMD_RST; - addrw++; - } -} - -static void bank_erase_init (flash_info_t * info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int flag; - -#ifdef FLASH_DEBUG - printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); - printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); - printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); - printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); - printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); - printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); - printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); -#endif - - saddrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (saddrw); - -#ifdef FLASH_DEBUG - printf ("erasing sector %d, start addr = 0x%08lx " - "(bank next word addr = 0x%08lx)\n", sect, - (unsigned long) saddrw, (unsigned long) eaddrw); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts (); - - for (addrw = saddrw; addrw < eaddrw; addrw++) { -#ifdef FLASH_DEBUG - printf (" writing erase cmd to addr 0x%08lx\n", - (unsigned long) addrw); -#endif - *addrw = BANK_CMD_ERASE1; - *addrw = BANK_CMD_ERASE2; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); -} - -static int bank_erase_poll (flash_info_t * info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int sectdone, haderr; - - saddrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (saddrw); - - sectdone = 1; - haderr = 0; - - for (addrw = saddrw; addrw < eaddrw; addrw++) { - bank_word_t stat = *addrw; - -#ifdef FLASH_DEBUG - printf (" checking status at addr " - "0x%08x [0x%08x]\n", (unsigned long) addrw, stat); -#endif - if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) - sectdone = 0; - else if ((stat & BANK_STAT_ERR) != 0) { - printf (" failed on sector %d " - "(stat = 0x%08x) at " - "address 0x%p\n", sect, stat, addrw); - *addrw = BANK_CMD_CLR_STAT; - haderr = 1; - } - } - - if (haderr) - return (-1); - else - return (sectdone); -} - -int write_word_intel (bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf ("flash program failed (stat = 0x%08lx) " - "at address 0x%08lx\n", (ulong) stat, (ulong) addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - - done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase_intel (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - -#ifdef FLASH_DEBUG - printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info (info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init (info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer (start); - - do { - now = get_timer (start); - - if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - break; - } -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll (info, sect); - - if (sectdone < 0) { - haderr = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset (info, sect); - } - } - return haderr; -} diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S deleted file mode 100644 index b3a089803a..0000000000 --- a/board/Marvell/common/misc.S +++ /dev/null @@ -1,235 +0,0 @@ -#include -#include <74xx_7xx.h> -#include "version.h" - -#include -#include - -#include -#include - -#include "../include/mv_gen_reg.h" - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CONFIG_SYS_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CONFIG_SYS_MONITOR_LEN@h - ori r8, r8, CONFIG_SYS_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CONFIG_SYS_DFL_GT_REGS@h - ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ -/* rlwinm r7, r4, 8, 16, 31 - rlwinm r7, r4, 12, 16, 31 */ /* original */ - rlwinm r7, r4, 16, 16, 31 - /* -----------------------------------------------------*/ - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0_relocated -led_on0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC80 - ori r18, r18, 0x8000 - stw r21, 0x0(r18) -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off0_relocated -led_off0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC81 - ori r18, r18, 0x4000 - stw r21, 0x0(r18) -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_off0 -led_off0: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x4000 - stw r18, 0x0(r18) - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr - - .global led_off1 -led_off1: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 - stw r18, 0x0(r18) - sync - blr - - .global led_off2 -led_off2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 56ba0daa05..432aa0660e 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -20,15 +20,6 @@ #include #include "../include/memory.h" -#include "serial.h" - -#ifdef CONFIG_DB64360 -#include "../db64360/mpsc.h" -#endif - -#ifdef CONFIG_DB64460 -#include "../db64460/mpsc.h" -#endif #include "ns16550.h" diff --git a/board/Marvell/common/serial.h b/board/Marvell/common/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/Marvell/common/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig new file mode 100644 index 0000000000..98aa10ade0 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DB_MV784MP_GP + +config SYS_BOARD + default "db-mv784mp-gp" + +config SYS_VENDOR + default "Marvell" + +config SYS_SOC + default "armada-xp" + +config SYS_CONFIG_NAME + default "db-mv784mp-gp" + +endif diff --git a/board/Marvell/db-mv784mp-gp/MAINTAINERS b/board/Marvell/db-mv784mp-gp/MAINTAINERS new file mode 100644 index 0000000000..a095f898d4 --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/MAINTAINERS @@ -0,0 +1,6 @@ +DB_MV784MP_GP BOARD +M: Stefan Roese +S: Maintained +F: board/Marvell/db-mv784mp-gp/ +F: include/configs/db-mv784mp-gp.h +F: configs/db-mv784mp-gp_defconfig diff --git a/board/Marvell/db-mv784mp-gp/Makefile b/board/Marvell/db-mv784mp-gp/Makefile new file mode 100644 index 0000000000..8f5a7fb6cb --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := db-mv784mp-gp.o diff --git a/board/Marvell/db-mv784mp-gp/binary.0 b/board/Marvell/db-mv784mp-gp/binary.0 new file mode 100644 index 0000000000..17bfad99dc --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/binary.0 @@ -0,0 +1,17 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. + +In a few weeks, mainline U-Boot will get support to generate the +bin_hdr with the DDR training code itself. By implementing this code +as SPL U-Boot. Then this file will not be needed any more and will +get removed. + diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c new file mode 100644 index 0000000000..b3dae8910d --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT(nr) (1UL << (nr)) + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka + * "RD-AXP-GP rev 1.0". + * + * GPPs + * MPP# NAME IN/OUT + * ---------------------------------------------- + * 21 SW_Reset_ OUT + * 25 Phy_Int# IN + * 28 SDI_WP IN + * 29 SDI_Status IN + * 54-61 On GPP Connector ? + * 62 Switch Interrupt IN + * 63-65 Reserved from SW Board ? + * 66 SW_BRD connected IN + */ +#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20))) +#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27))) +#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20)) +#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27)) +#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00000000, MVEBU_MPP_BASE + 0x00); + writel(0x00000000, MVEBU_MPP_BASE + 0x04); + writel(0x33000000, MVEBU_MPP_BASE + 0x08); + writel(0x11000000, MVEBU_MPP_BASE + 0x0c); + writel(0x11111111, MVEBU_MPP_BASE + 0x10); + writel(0x00221100, MVEBU_MPP_BASE + 0x14); + writel(0x00000003, MVEBU_MPP_BASE + 0x18); + writel(0x00000000, MVEBU_MPP_BASE + 0x1c); + writel(0x00000000, MVEBU_MPP_BASE + 0x20); + + /* Configure GPIO */ + writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Marvell DB-MV784MP-GP\n"); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1545 PHY */ +void reset_phy(void) +{ + u16 devadr = CONFIG_PHY_BASE_ADDR; + char *name = "neta0"; + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* Enable QSGMII AN */ + /* Set page to 4 */ + miiphy_write(name, devadr, 0x16, 4); + /* Enable AN */ + miiphy_write(name, devadr, 0x0, 0x1140); + /* Set page to 0 */ + miiphy_write(name, devadr, 0x16, 0); + + /* Phy C_ANEG */ + miiphy_read(name, devadr, 0x4, ®); + reg |= 0x1E0; + miiphy_write(name, devadr, 0x4, reg); + + /* Soft-Reset */ + miiphy_write(name, devadr, 22, 0x0000); + miiphy_write(name, devadr, 0, 0x9140); + + /* Power up the phy */ + miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®); + reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); + miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg); + + printf("88E1545 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg new file mode 100644 index 0000000000..d7ef4071dd --- /dev/null +++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068 diff --git a/board/Marvell/db64360/64360.h b/board/Marvell/db64360/64360.h deleted file mode 100644 index 99512629c2..0000000000 --- a/board/Marvell/db64360/64360.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * main board support/init for the Galileo Eval board DB64360. - */ - -#ifndef __64360_H__ -#define __64360_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64360_H__ */ diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile deleted file mode 100644 index a5f2c54556..0000000000 --- a/board/Marvell/db64360/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -SOBJS = ../common/misc.o - -COBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ - mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ - sdram_init.o ../common/intel_flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/Marvell/db64360/README b/board/Marvell/db64360/README deleted file mode 100644 index ebac4cec19..0000000000 --- a/board/Marvell/db64360/README +++ /dev/null @@ -1,105 +0,0 @@ -This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360. - -Author: Ronen Shitrit - -This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT. - -Supported CPU Types : -+++++++++++++++++++++ - IBM750FX (ver 2.3) - MPC7455 (ver 2.1) - -Supported CPU Cache Library: -++++++++++++++++++++++++++++ - L1 and L2 only. - -CPU Control: -++++++++++++ - Marvell optimized CPU control settings: - Big Endian - Enable CPU pipeline - Data and address parity checking - AACK# assert after 2 cycles - -U-Boot I/O Interface Support: -+++++++++++++++++++++++++++++ -- Serial Interface (UART) - This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module. -- Network Interface - This LSP supports the following network devices: - o MV64360 Gigabit Ethernet Controller device - o Intel 82559 PCI NIC device -- PCI Interface - This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units: - o Local PCI configuration header control. - o External PCI configuration header control (for other agents on the bus). - o PCI configuration application. Scans and configures the PCI agents on the bus. - o PCI Internal Arbiter activation and configuration. - -Memory Interface Support: -+++++++++++++++++++++++++ -- DDR - o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs). - o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma. - -- Devices - o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM. - o JFFS2 - JFFS2 is a crash/power down safe file system for disk-less embedded devices. - This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it. - -Unsupported Features: -+++++++++++++++++++++ - Messaging unit - No support for MV64360 Messaging unit. - Watchdog Timer - No support for MV64360 Watchdog unit. - L3 cache - No support for L3 cache on MPC7455 - Dual PCU - No support for Dual CPU - PCI-X was never tested - IDMA driver - No support for MV64360 IDMA unit. - -BSP Special Considerations: -+++++++++++++++++++++++++++ -- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots. -- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical. - -Test Cases: -########### -UART: -+++++ -Check that the UART baud rate is configured to 57600 and 115200, and check: - Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom. - Load S-Record file over the UART using Windows HyperTerminal. - -Network: -++++++++ -Use TFTP application to load a debugged executable and execute it. -Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC. - -Memory: -+++++++ -Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters: -o 128MB DIMM consist of 16 x 64Mbit devices -o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz. -o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz. -o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz. -o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz. -o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz. -o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered - -For each chip select device perform data access to verify its accessibility. - -Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage. -Load the U-Boot and: -use the ls command to check correct scan of the JFFS2 on the large flash. -Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage. - -PCI: -++++ -1)Insert different PCI cards: -Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10 -on different slots (0-3) of the PCI and check: -o Correct detection of the PCI devices. -o Correct address mapping of the PCI devices. -2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot. - -Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal) diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c deleted file mode 100644 index 36d26e3f14..0000000000 --- a/board/Marvell/db64360/db64360.c +++ /dev/null @@ -1,922 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com - */ - -/* - * db64360.c - main board support/init for the Galileo Eval board. - */ - -#include -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include -#include -#include - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64360.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; -int display_mem_map (void); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CONFIG_SYS_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6436x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6436x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) - sram_boot = 1; - if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - - memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); - - - /* configure device timing */ -#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ - if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); -#endif - -#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); -#endif -#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); -#endif - -#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CONFIG_SYS_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); - } - display_mem_map (); - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ - volatile int *addr = 0; - __maybe_unused int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x08000); - break; - - case 1: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x0c000); - break; - - case 2: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x14000); - break; - - case 1: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x18000); - break; - - case 2: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x1c000); - break; - } - } - - dummy = *addr; -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } - - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } - - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- EXT SRAM (actual - 1M)\n"); - else if (i == 1) - printf ("\t- RTC\n"); - else if (i == 2) - printf ("\t- UART\n"); - else - printf ("\t- LARGE FLASH\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n", - base, size >> 20, width); - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CONFIG_SYS_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; - const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; - const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata, runaddress, runwalk; - - rundata = getenv_yesno("testdramdata") == 1; - runaddress = getenv_yesno("testdramaddress") == 1; - runwalk = getenv_yesno("testdramwalk") == 1; - -/* rundata = 1; */ -/* runaddress = 0; */ -/* runwalk = 0; */ - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - } -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); -/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */ - -/* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); - - icache_disable (); - dcache_disable (); -} - -int board_eth_init(bd_t *bis) -{ - int ret; - ret = pci_eth_init(bis); - if (!ret) - ret = mv6436x_eth_initialize(bis); - return ret; -} diff --git a/board/Marvell/db64360/eth.h b/board/Marvell/db64360/eth.h deleted file mode 100644 index 4e427683b4..0000000000 --- a/board/Marvell/db64360/eth.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64360_ETH_H__ -#define __EVB64360_ETH_H__ - -#include -#include -#include -#include - - -int db64360_eth0_poll(void); -int db64360_eth0_transmit(unsigned int s, volatile char *p); -void db64360_eth0_disable(void); -bool network_start(bd_t *bis); - -int mv6436x_eth_initialize(bd_t *); - -#endif /* __EVB64360_ETH_H__ */ diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c deleted file mode 100644 index d87f18eea3..0000000000 --- a/board/Marvell/db64360/mpsc.c +++ /dev/null @@ -1,1001 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include -#include -#include - -#include -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../include/memory.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#else - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64360 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* true for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/Marvell/db64360/mpsc.h b/board/Marvell/db64360/mpsc.h deleted file mode 100644 index ca1e89a6f6..0000000000 --- a/board/Marvell/db64360/mpsc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c deleted file mode 100644 index b2df1f743d..0000000000 --- a/board/Marvell/db64360/mv_eth.c +++ /dev/null @@ -1,3128 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include -#include -#include - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64360_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64360_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64360_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64360_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64360 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64360_eth_real_open (struct eth_device *eth); -static int mv64360_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64360_eth_update_stat (struct eth_device *dev); -bool db64360_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64360_eth_receive (struct eth_device *dev); - -int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64360_eth_print_stat (struct eth_device *dev); -#endif - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64360_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64360_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64360_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64360_eth - * - **********************************************************************/ -int db64360_eth_probe (struct eth_device *dev) -{ - return ((int) db64360_eth_start (dev)); -} - -int db64360_eth_poll (struct eth_device *dev) -{ - return mv64360_eth_receive (dev); -} - -int db64360_eth_transmit(struct eth_device *dev, void *packet, int length) -{ - mv64360_eth_xmit (dev, packet, length); - return 0; -} - -void db64360_eth_disable (struct eth_device *dev) -{ - mv64360_eth_stop (dev); -} - - -void mv6436x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64360_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64360_eth_transmit; - dev->recv = (void *) db64360_eth_poll; - - ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *) ethernet_private; - - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64360_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64360_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64360_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64360_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64360_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64360_eth_open (struct eth_device *dev) -{ - return (mv64360_eth_real_open (dev)); -} - -/* Helper function for mv64360_eth_open */ -static int mv64360_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - u32 phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64360_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64360_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64360_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64360_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64360_eth_stop (struct eth_device *dev) -{ - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64360_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64360_eth_stop */ - -static int mv64360_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64360_eth_free_tx_rings (dev); - mv64360_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64360_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64360_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - pkt_info.return_info = 0; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64360_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64360_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64360_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64360_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - - mv64360_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64360_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64360_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64360_eth_start (struct eth_device *dev) -{ - return (mv64360_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) - MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/Marvell/db64360/mv_eth.h b/board/Marvell/db64360/mv_eth.h deleted file mode 100644 index 790b0df4da..0000000000 --- a/board/Marvell/db64360/mv_eth.h +++ /dev/null @@ -1,818 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64360_ETH_H__ -#define __DB64360_ETH_H__ - -#include -#include -#include -#include -#include -#include "mv_regs.h" -#include - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64360_TX_QUEUE_NUM 1 -#define MV64360_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE -#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE -#else -#define MV64360_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE -#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE -#else -#define MV64360_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64360_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64360_TX_BUFFER_SIZE 1600 -#endif - - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64360_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - - -int mv64360_eth_init (struct eth_device *dev); -int mv64360_eth_stop (struct eth_device *dev); -int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length); -int mv64360_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64360_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64360_ETH_ */ diff --git a/board/Marvell/db64360/mv_regs.h b/board/Marvell/db64360/mv_regs.h deleted file mode 100644 index 45274f08d9..0000000000 --- a/board/Marvell/db64360/mv_regs.h +++ /dev/null @@ -1,1108 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** -* gt64360r.h - GT-64360 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64360 - -/* Supported by the Atlantis */ -#define MV64360_INCLUDE_PCI_1 -#define MV64360_INCLUDE_PCI_0_ARBITER -#define MV64360_INCLUDE_PCI_1_ARBITER -#define MV64360_INCLUDE_SNOOP_SUPPORT -#define MV64360_INCLUDE_P2P -#define MV64360_INCLUDE_ETH_PORT_2 -#define MV64360_INCLUDE_CPU_MAPPING -#define MV64360_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64360_CS_0_BASE_ADDR 0x008 -#define MV64360_CS_0_SIZE 0x010 -#define MV64360_CS_1_BASE_ADDR 0x208 -#define MV64360_CS_1_SIZE 0x210 -#define MV64360_CS_2_BASE_ADDR 0x018 -#define MV64360_CS_2_SIZE 0x020 -#define MV64360_CS_3_BASE_ADDR 0x218 -#define MV64360_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64360_PCI_0_IO_BASE_ADDR 0x048 -#define MV64360_PCI_0_IO_SIZE 0x050 -#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64360_PCI_0_MEMORY0_SIZE 0x060 -#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64360_PCI_0_MEMORY1_SIZE 0x088 -#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64360_PCI_0_MEMORY2_SIZE 0x260 -#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64360_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64360_PCI_1_IO_BASE_ADDR 0x090 -#define MV64360_PCI_1_IO_SIZE 0x098 -#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64360_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64360_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64360_CPU_CONFIG 0x000 -#define MV64360_CPU_MODE 0x120 -#define MV64360_CPU_MASTER_CONTROL 0x160 -#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64360_SMP_WHO_AM_I 0x200 -#define MV64360_SMP_CPU0_DOORBELL 0x214 -#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64360_SMP_CPU1_DOORBELL 0x224 -#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64360_SMP_SEMAPHOR0 0x244 -#define MV64360_SMP_SEMAPHOR1 0x24c -#define MV64360_SMP_SEMAPHOR2 0x254 -#define MV64360_SMP_SEMAPHOR3 0x25c -#define MV64360_SMP_SEMAPHOR4 0x264 -#define MV64360_SMP_SEMAPHOR5 0x26c -#define MV64360_SMP_SEMAPHOR6 0x274 -#define MV64360_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64360_CPU_ERROR_ADDR_LOW 0x070 -#define MV64360_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64360_CPU_ERROR_DATA_LOW 0x128 -#define MV64360_CPU_ERROR_DATA_HIGH 0x130 -#define MV64360_CPU_ERROR_PARITY 0x138 -#define MV64360_CPU_ERROR_CAUSE 0x140 -#define MV64360_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64360_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64360_SRAM_CONFIG 0x380 -#define MV64360_SRAM_TEST_MODE 0X3F4 -#define MV64360_SRAM_ERROR_CAUSE 0x388 -#define MV64360_SRAM_ERROR_ADDR 0x390 -#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64360_SRAM_ERROR_DATA_LOW 0x398 -#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64360_SDRAM_CONFIG 0x1400 -#define MV64360_D_UNIT_CONTROL_LOW 0x1404 -#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64360_SDRAM_ADDR_CONTROL 0x1410 -#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64360_SDRAM_OPERATION 0x1418 -#define MV64360_SDRAM_MODE 0x141c -#define MV64360_EXTENDED_DRAM_MODE 0x1420 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64360_SDRAM_ERROR_ADDR 0x1450 -#define MV64360_SDRAM_RECEIVED_ECC 0x1448 -#define MV64360_SDRAM_CALCULATED_ECC 0x144c -#define MV64360_SDRAM_ECC_CONTROL 0x1454 -#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64360_DFCDL_CONFIG0 0x1480 -#define MV64360_DFCDL_CONFIG1 0x1484 -#define MV64360_DLL_WRITE 0x1488 -#define MV64360_DLL_READ 0x148c -#define MV64360_SRAM_ADDR 0x1490 -#define MV64360_SRAM_DATA0 0x1494 -#define MV64360_SRAM_DATA1 0x1498 -#define MV64360_SRAM_DATA2 0x149c -#define MV64360_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64360_DUNIT_DEBUG_LOW 0x1460 -#define MV64360_DUNIT_DEBUG_HIGH 0x1464 -#define MV64360_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64360_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64360_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64360_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64360_DEVICE_ERROR_ADDR 0x4d8 -#define MV64360_DEVICE_ERROR_DATA 0x4dc -#define MV64360_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64360_DEVICE_DEBUG_LOW 0x4e4 -#define MV64360_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64360_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64360_PCI_0_COMMAND 0xc00 -#define MV64360_PCI_1_COMMAND 0xc80 -#define MV64360_PCI_0_MODE 0xd00 -#define MV64360_PCI_1_MODE 0xd80 -#define MV64360_PCI_0_RETRY 0xc04 -#define MV64360_PCI_1_RETRY 0xc84 -#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64360_PCI_0_P2P_CONFIG 0x1d14 -#define MV64360_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64360_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64360_PCI_1_CONFIG_ADDR 0xc78 -#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64360_PCI_0_SERR_MASK 0xc28 -#define MV64360_PCI_1_SERR_MASK 0xca8 -#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64360_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64360_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64360_PCI_0_ERROR_MASK 0x1d5c -#define MV64360_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64360_PCI_0_MMASK 0X1D24 -#define MV64360_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64360_PCI_STATUS_AND_COMMAND 0x004 -#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64360_PCI_VPD_ADDR 0x048 -#define MV64360_PCI_VPD_DATA 0x04c -#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64360_PCI_X_COMMAND 0x060 -#define MV64360_PCI_X_STATUS 0x064 -#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64360_ETH_PHY_ADDR_REG 0x2000 -#define MV64360_ETH_SMI_REG 0x2004 -#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64360_ETH_BAR_0 0x2200 -#define MV64360_ETH_BAR_1 0x2208 -#define MV64360_ETH_BAR_2 0x2210 -#define MV64360_ETH_BAR_3 0x2218 -#define MV64360_ETH_BAR_4 0x2220 -#define MV64360_ETH_BAR_5 0x2228 -#define MV64360_ETH_SIZE_REG_0 0x2204 -#define MV64360_ETH_SIZE_REG_1 0x220c -#define MV64360_ETH_SIZE_REG_2 0x2214 -#define MV64360_ETH_SIZE_REG_3 0x221c -#define MV64360_ETH_SIZE_REG_4 0x2224 -#define MV64360_ETH_SIZE_REG_5 0x222c -#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64360_CUNIT_SIZE0 0xf204 -#define MV64360_CUNIT_SIZE1 0xf20c -#define MV64360_CUNIT_SIZE2 0xf214 -#define MV64360_CUNIT_SIZE3 0xf21c -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64360_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64360_CUNIT_CONFIG_REG 0xb40c -#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64360_CUNIT_DEBUG_LOW 0xf340 -#define MV64360_CUNIT_DEBUG_HIGH 0xf344 -#define MV64360_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64360_MPSC_ROUTING_REG 0xb400 -#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64360_SDMA_CAUSE_REG 0xb800 -#define MV64360_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64360_SDMA_SRAM_TARGET 0x0003 -#define MV64360_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64360_PCI_0_TARGET 0x0003 -#define MV64360_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64360_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64360_BRG_CAUSE_REG 0xb834 -#define MV64360_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_CONTROL 0x840 -#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64360_DMA_CHANNEL1_CONTROL 0x844 -#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64360_DMA_CHANNEL2_CONTROL 0x848 -#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64360_DMA_CHANNEL3_CONTROL 0x84C -#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64360_DMA_BASE_ADDR_REG0 0xa00 -#define MV64360_DMA_BASE_ADDR_REG1 0xa08 -#define MV64360_DMA_BASE_ADDR_REG2 0xa10 -#define MV64360_DMA_BASE_ADDR_REG3 0xa18 -#define MV64360_DMA_BASE_ADDR_REG4 0xa20 -#define MV64360_DMA_BASE_ADDR_REG5 0xa28 -#define MV64360_DMA_BASE_ADDR_REG6 0xa30 -#define MV64360_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64360_DMA_SIZE_REG0 0xa04 -#define MV64360_DMA_SIZE_REG1 0xa0c -#define MV64360_DMA_SIZE_REG2 0xa14 -#define MV64360_DMA_SIZE_REG3 0xa1c -#define MV64360_DMA_SIZE_REG4 0xa24 -#define MV64360_DMA_SIZE_REG5 0xa2c -#define MV64360_DMA_SIZE_REG6 0xa34 -#define MV64360_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64360_DMA_ARBITER_CONTROL 0x860 -#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64360_DMA_ERROR_ADDR 0x8c8 -#define MV64360_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64360_DMA_DEBUG_LOW 0x8e0 -#define MV64360_DMA_DEBUG_HIGH 0x8e4 -#define MV64360_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64360_TIMER_COUNTER0 0x850 -#define MV64360_TIMER_COUNTER1 0x854 -#define MV64360_TIMER_COUNTER2 0x858 -#define MV64360_TIMER_COUNTER3 0x85C -#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64360_WATCHDOG_CONFIG_REG 0xb410 -#define MV64360_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64360_I2C_SLAVE_ADDR 0xc000 -#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64360_I2C_DATA 0xc004 -#define MV64360_I2C_CONTROL 0xc008 -#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64360_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64360_GPP_IO_CONTROL 0xf100 -#define MV64360_GPP_LEVEL_CONTROL 0xf110 -#define MV64360_GPP_VALUE 0xf104 -#define MV64360_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64360_GPP_INTERRUPT_MASK0 0xf10c -#define MV64360_GPP_INTERRUPT_MASK1 0xf114 -#define MV64360_GPP_VALUE_SET 0xf118 -#define MV64360_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64360_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64360_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64360_MPP_CONTROL0 0xf000 -#define MV64360_MPP_CONTROL1 0xf004 -#define MV64360_MPP_CONTROL2 0xf008 -#define MV64360_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64360_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64360_SERIAL_INIT_CONTROL 0xf328 -#define MV64360_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64360rh */ diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c deleted file mode 100644 index 8c25198e3b..0000000000 --- a/board/Marvell/db64360/pci.c +++ /dev/null @@ -1,923 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PCI.c - PCI functions */ - - -#include -#include - -#include "../include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 MHz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 MHz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 MHz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c deleted file mode 100644 index dafbe59f52..0000000000 --- a/board/Marvell/db64360/sdram_init.c +++ /dev/null @@ -1,1945 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * adaption for the Marvell DB64360 Board - * Ingo Assmus (ingo.assmus@keymile.com) - ************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "../common/i2c.h" -#include "64360.h" -#include "mv_regs.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define MAP_PCI - -int set_dfcdlInit (void); /* setup delay line of Mv64360 */ -int mvDmaIsChannelActive (int); -int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); -int mvDmaTransfer (int, ulong, ulong, ulong, ulong); - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; - -typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, -} VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = - 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = - 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD { SD_CL_1 = - 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, - SD_FAULT } MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - unsigned long spd_checksum; - -#ifdef ZUMA_NTL - /* zero all the values */ - memset (info, 0, sizeof (*info)); - -/* - if (!slot) { - info->slot = 0; - info->banks = 1; - info->registered = 0; - info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ -/* info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -*/ -#ifdef CONFIG_MV64360_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - dimmInfo->errorCheckType = 2; -/* info->ecc = 2;*/ -#endif -} - -return 0; - -#else - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, tras_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - debug("before i2c read\n"); - - ret = i2c_read (addr, 0, 1, data, 128); - - debug("after i2c read\n"); - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - debug("No DIMM in slot %d [err = %x]\n", slot, ret); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG -/* find Manufactura of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - -/* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - -/* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - -/* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - -/* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - -/* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - -/* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif - -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; - - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); - - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; - if (dimmInfo->memoryType == 0) - debug - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot); - if (dimmInfo->memoryType == 1) - debug - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - debug - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - debug - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - debug - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - debug - ("Module Data Width: %d\n", - dimmInfo->dataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - debug - ("Module is TTL_5V_TOLERANT\n"); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - debug - ("Module is LVTTL\n"); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - debug - ("Module is TTL_5V_TOLERANT\n"); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - debug - ("Module is HSTL_1_5V\n"); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - debug - ("Module is SSTL_2_5V\n"); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - debug - ("Module is VOLTAGE_UNKNOWN\n"); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - debug - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -/*#ifdef CONFIG_ECC */ - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - debug - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType); - break; -/* #endif */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - debug - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - debug - ("Sdram Width: %d\n", - dimmInfo->sdramWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - debug - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - debug - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - debug - ("Burst Length Supported: "); - if (dimmInfo->burstLengthSupported & 0x01) - debug("1, "); - if (dimmInfo->burstLengthSupported & 0x02) - debug("2, "); - if (dimmInfo->burstLengthSupported & 0x04) - debug("4, "); - if (dimmInfo->burstLengthSupported & 0x08) - debug("8, "); - debug(" Bit \n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - debug - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - debug - ("Suported Cas Latencies: (CL) "); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - debug - ("%d, ", - k + 1); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - debug("1, "); - if (dimmInfo->suportedCasLatencies & 2) - debug("1.5, "); - if (dimmInfo->suportedCasLatencies & 4) - debug("2, "); - if (dimmInfo->suportedCasLatencies & 8) - debug("2.5, "); - if (dimmInfo->suportedCasLatencies & 16) - debug("3, "); - if (dimmInfo->suportedCasLatencies & 32) - debug("3.5, "); - - } - debug("\n"); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - debug - ("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - debug - ("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - debug - ("Max. Cas Latencies (DDR): 3.5 clk's\n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - debug - ("Max. Cas Latencies (DDR): 3 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - debug - ("Max. Cas Latencies (DDR): 2.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - debug - ("Max. Cas Latencies (DDR): 2 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - debug - ("Max. Cas Latencies (DDR): 1.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - - /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy - lower then our SDRAM cycle count, we won't be able to support this CAL - and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - < - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - < - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - dimmInfo-> - maxClSupported_DDR - = - dimmInfo-> - maxClSupported_DDR - >> 1; - debug - ("*** Change actual Cas Latencies cause of minimumCycleTime n"); - } - /* ronen - checkif the Dimm frequency compared to the Sysclock. */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - > - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - > - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - printf ("*********************************************************\n"); - printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); - printf ("*********************************************************\n"); - hang (); - } - - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - debug - ("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - debug("\nModul Attributes (SPD Byte 21): \n"); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; -#ifdef DEBUG - if (dimmInfo->bufferedAddrAndControlInputs == 1) - debug - (" - Buffered Address/Control Input: Yes \n"); - else - debug - (" - Buffered Address/Control Input: No \n"); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - debug - (" - Registered Address/Control Input: Yes \n"); - else - debug - (" - Registered Address/Control Input: No \n"); - - if (dimmInfo->onCardPLL == 1) - debug - (" - On-Card PLL (clock): Yes \n"); - else - debug - (" - On-Card PLL (clock): No \n"); - - if (dimmInfo->bufferedDQMBinputs == 1) - debug - (" - Bufferd DQMB Inputs: Yes \n"); - else - debug - (" - Bufferd DQMB Inputs: No \n"); - - if (dimmInfo->registeredDQMBinputs == 1) - debug - (" - Registered DQMB Inputs: Yes \n"); - else - debug - (" - Registered DQMB Inputs: No \n"); - - if (dimmInfo->differentialClockInput == 1) - debug - (" - Differential Clock Input: Yes \n"); - else - debug - (" - Differential Clock Input: No \n"); - - if (dimmInfo->redundantRowAddressing == 1) - debug - (" - redundant Row Addressing: Yes \n"); - else - debug - (" - redundant Row Addressing: No \n"); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - debug("\nModul Attributes (SPD Byte 22): \n"); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; -#ifdef DEBUG - if (dimmInfo->suportedEarlyRasPreCharge == 1) - debug - (" - Early Ras Precharge: Yes \n"); - else - debug - (" - Early Ras Precharge: No \n"); - - if (dimmInfo->suportedAutoPreCharge == 1) - debug - (" - AutoPreCharge: Yes \n"); - else - debug - (" - AutoPreCharge: No \n"); - - if (dimmInfo->suportedPreChargeAll == 1) - debug - (" - Precharge All: Yes \n"); - else - debug - (" - Precharge All: No \n"); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - debug - (" - Write 1/ReadBurst: Yes \n"); - else - debug - (" - Write 1/ReadBurst: No \n"); - - if (dimmInfo->suported5PercentLowVCC == 1) - debug - (" - lower VCC tolerance: 5 Percent \n"); - else - debug - (" - lower VCC tolerance: 10 Percent \n"); - - if (dimmInfo->suported5PercentUpperVCC == 1) - debug - (" - upper VCC tolerance: 5 Percent \n"); - else - debug - (" - upper VCC tolerance: 10 Percent \n"); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - debug - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - debug - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - debug - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100); - debug - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - debug - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - debug - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity); -#ifdef DEBUG - debug - ("*** Offered Densities (more than 1 = Multisize-Module): "); - { - if (dimmInfo->moduleBankDensity & 1) - debug("4MB, "); - if (dimmInfo->moduleBankDensity & 2) - debug("8MB, "); - if (dimmInfo->moduleBankDensity & 4) - debug("16MB, "); - if (dimmInfo->moduleBankDensity & 8) - debug("32MB, "); - if (dimmInfo->moduleBankDensity & 16) - debug("64MB, "); - if (dimmInfo->moduleBankDensity & 32) - debug("128MB, "); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - debug("ERROR, "); - hang (); - } - } - debug("\n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - - /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ - dimmInfo->numberOfDevices / 8); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; - - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - debug("cal_val = %d\n", cal_val); - - /* bummer, did't work... */ - if (cal_val == 0) { - debug("Couldn't find a good CAS latency\n"); - hang (); - return 0; - } - - return true; - -#endif -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp, check; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - int i; - - /* added 8/21/2003 P. Marchese */ - unsigned int sdram_config_reg; - - /* added 10/10/2003 P. Marchese */ - ulong sdram_chip_size; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - debug("Delay line set done\n"); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); - } - - /* SDRAM configuration */ -/* added 8/21/2003 P. Marchese */ -/* code allows usage of registered DIMMS */ - - /* figure out the memory refresh internal */ - switch (info->RefreshInterval) { - case 0x0: - case 0x80: /* refresh period is 15.625 usec */ - sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK) - / (float) 1000000.0); - break; - case 0x1: - case 0x81: /* refresh period is 3.9 usec */ - sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x2: - case 0x82: /* refresh period is 7.8 usec */ - sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x3: - case 0x83: /* refresh period is 31.3 usec */ - sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x4: - case 0x84: /* refresh period is 62.5 usec */ - sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x5: - case 0x85: /* refresh period is 125 usec */ - sdram_config_reg = - (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - default: /* refresh period undefined */ - printf ("DRAM refresh period is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - debug("calculated refresh interval %0x\n", sdram_config_reg); - - /* make sure the refresh value is only 14 bits */ - if (sdram_config_reg > 0x1fff) - sdram_config_reg = 0x1fff; - debug("adjusted refresh interval %0x\n", sdram_config_reg); - - /* we want physical bank interleaving and */ - /* virtual bank interleaving enabled so do nothing */ - /* since these bits need to be zero to enable the interleaving */ - - /* registered DRAM ? */ - if (info->registeredAddrAndControlInputs == 1) { - /* it's registered DRAM, so set the reg. DRAM bit */ - sdram_config_reg = sdram_config_reg | BIT17; - debug("Enabling registered DRAM bit\n"); - } - /* turn on DRAM ECC? */ -#ifdef CONFIG_MV64360_ECC - if (info->errorCheckType == 0x2) { - /* DRAM has ECC, so turn it on */ - sdram_config_reg = sdram_config_reg | BIT18; - debug("Enabling ECC\n"); - } -#endif - /* set the data DQS pin configuration */ - switch (info->sdramWidth) { - case 0x4: /* memory is x4 */ - sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - debug("Data DQS pins set for 16 pins\n"); - break; - case 0x8: /* memory is x8 or x16 */ - case 0x10: - sdram_config_reg = sdram_config_reg | BIT21; - debug("Data DQS pins set for 8 pins\n"); - break; - case 0x20: /* memory is x32 */ - /* both bits are cleared for x32 so nothing to do */ - debug("Data DQS pins set for 2 pins\n"); - break; - default: /* memory width unsupported */ - printf ("DRAM chip width is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - - /* perform read buffer assignments */ - /* we are going to use the Power-up defaults */ - /* bit 26 = CPU = buffer 1 */ - /* bit 27 = PCI bus #0 = buffer 0 */ - /* bit 28 = PCI bus #1 = buffer 0 */ - /* bit 29 = MPSC = buffer 0 */ - /* bit 30 = IDMA = buffer 0 */ - /* bit 31 = Gigabit = buffer 0 */ - sdram_config_reg = sdram_config_reg | BIT26; - /* sdram_config_reg = sdram_config_reg | 0x58000000; */ - /* sdram_config_reg = sdram_config_reg & 0xffffff00; */ - - /* write the value into the SDRAM configuration register */ - GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - debug - ("OOOOOOOOO sdram_conf 0x1400: %08x\n", - GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM open pages control keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - debug - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - debug("Core Signals are sync (by HW-Setting)!!!\n"); - else - debug - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); - - /* SDRAM set CAS Latency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - printf ("### SD-RAM not supported !!!\n"); - printf ("Aborting!!!\n"); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - /* Calculate the settings for SDRAM mode and Dunit control low registers */ - /* Values set according to technical bulletin TB-92 rev. c */ - case DDR: - debug("### SET-CL for DDR-RAM\n"); - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x05110051; - else - tmp_dunit_control_low = 0x24110051; - debug - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x2C1107F2; - else - tmp_dunit_control_low = 0x3C1107d2; - debug - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_2_5: - tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x25110051; - else - tmp_dunit_control_low = 0x24110051; - debug - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x1B1107d2; - debug - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_2: - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x04110051; - else - tmp_dunit_control_low = 0x03110051; - debug - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x3B1107d2; - debug - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_1_5: - tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x24110051; - else - tmp_dunit_control_low = 0x23110051; - debug - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x1A1107d2; - debug - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } /* end DDR switch */ - break; - } /* end CL switch */ - - /* Write results of CL detection procedure */ - /* set SDRAM mode reg. 0x141c */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); - } - -/*------------------------------------------------------------------------------ */ - - /* bank parameters */ - /* SDRAM address decode register 0x1410 */ - /* program this with the default value */ - tmp = 0x02; /* power-up default address select decoding value */ - - debug("drb_size (n*64Mbit): %d\n", info->drb_size); -/* figure out the DRAM chip size */ - sdram_chip_size = - (1 << (info->numOfRowAddresses + info->numOfColAddresses)); - sdram_chip_size *= info->sdramWidth; - sdram_chip_size *= 4; - debug("computed sdram chip size is %#lx\n", sdram_chip_size); - /* divide sdram chip size by 64 Mbits */ - sdram_chip_size = sdram_chip_size / 0x4000000; - switch (sdram_chip_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - debug("RAM-Device_size 64Mbit or 128Mbit)\n"); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - debug("RAM-Device_size 256Mbit or 512Mbit)\n"); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - debug("RAM-Device_size 1Gbit or 2Gbit)\n"); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - printf ("RAM-Device_size is unsupported\n"); - hang (); - } - - /* SDRAM address control */ - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - debug - ("setting up sdram address control (0x1410) with: %08lx \n", - tmp); - -/* ------------------------------------------------------------------------------ */ -/* same settings for registerd & non-registerd DDR SDRAM */ - debug - ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x11511220); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - debug - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV64360 */ - tmp |= (1 << 26); - debug - ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG)); - debug - ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM timing To_do: */ -/* ------------------------------------------------------------------------------ */ - - debug - ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0x9); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9); - - debug - ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a); - GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - - debug - ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a); - GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); - -/* ------------------------------------------------------------------------------ */ - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - i = info->slot; - debug - ("\n*** Running a MRS cycle for bank %d ***\n", i); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - check = GTREGREAD (SDRAM_OPERATION); - debug - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check); - - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0); - check = GTREGREAD (SDRAM_OPERATION); - debug - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; - -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - debug - ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr); - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -phys_size_t initdram (int board_type) -{ - int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int nhr, bank_no; - ulong dest, memSpaceAttr; - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - check_dimm (0, &dimmInfo1); - - /* DIMM1 */ - check_dimm (1, &dimmInfo2); - - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* ronen check correct set of DIMMS */ - if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { - if (dimmInfo1.errorCheckType != - dimmInfo2.errorCheckType) - printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); - if (dimmInfo1.maxClSupported_DDR != - dimmInfo2.maxClSupported_DDR) - printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); - if (dimmInfo1.registeredAddrAndControlInputs != - dimmInfo2.registeredAddrAndControlInputs) - printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); - } - - if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - if (dimmInfo1.numOfModuleBanks > 0) { - checkbank[0] = 1; - } - if (dimmInfo1.numOfModuleBanks > 1) { - checkbank[1] = 1; - } - if (dimmInfo1.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); - - if (dimmInfo2.numOfModuleBanks > 0) { - checkbank[2] = 1; - } - if (dimmInfo2.numOfModuleBanks > 1) { - checkbank[3] = 1; - } - if (dimmInfo2.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - /* ronen - realsize = dram_size((long int *)total, check); */ - if (bank_no == 0 || bank_no == 1) { - if (checkbank[1] == 1) - realsize = dimmInfo1.size / 2; - else - realsize = dimmInfo1.size; - } - if (bank_no == 2 || bank_no == 3) { - if (checkbank[3] == 1) - realsize = dimmInfo2.size / 2; - else - realsize = dimmInfo2.size; - } - memory_map_bank (bank_no, total, realsize); - - /* ronen - initialize the DRAM for ECC */ -#ifdef CONFIG_MV64360_ECC - if ((dimmInfo1.errorCheckType != 0) && - ((dimmInfo2.errorCheckType != 0) - || (dimmInfo2.numOfModuleBanks == 0))) { - printf ("ECC Initialization of Bank %d:", bank_no); - memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; - mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, - realsize); - for (dest = total; dest < total + realsize; - dest += _8M) { - mvDmaTransfer (0, total, dest, _8M, - BIT8 /*DMA_DTL_128BYTES */ | - BIT3 /*DMA_HOLD_SOURCE_ADDR */ - | - BIT11 - /*DMA_BLOCK_TRANSFER_MODE */ ); - while (mvDmaIsChannelActive (0)); - } - printf (" PASS\n"); - } -#endif - - total += realsize; - } - - /* ronen- add DRAM conf prints */ - switch ((GTREGREAD (0x141c) >> 4) & 0x7) { - case 0x2: - printf ("CAS Latency = 2"); - break; - case 0x3: - printf ("CAS Latency = 3"); - break; - case 0x5: - printf ("CAS Latency = 1.5"); - break; - case 0x6: - printf ("CAS Latency = 2.5"); - break; - } - printf (" tRP = %d tRAS = %d tRCD=%d\n", - ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); - -/* Setup Ethernet DMA Adress window to DRAM Area */ - if (total > _256M) - printf ("*** ONLY the first 256MB DRAM memory are used out of the "); - else - printf ("Total SDRAM memory is "); - /* (cause all the 4 BATS are taken) */ - return (total); -} - - -/* ronen- add Idma functions for usage of the ecc dram init. */ -/******************************************************************************* -* mvDmaIsChannelActive - Checks if a engine is busy. -********************************************************************************/ -int mvDmaIsChannelActive (int engine) -{ - ulong data; - - data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); - if (data & BIT14 /*activity status */ ) { - return 1; - } - return 0; -} - -/******************************************************************************* -* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding -* map. -*******************************************************************************/ -int mvDmaSetMemorySpace (ulong memSpace, - ulong memSpaceTarget, - ulong memSpaceAttr, ulong baseAddress, ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return 0; - } - if (size >= 0x10000 /*64K */ ) { - size &= 0xffff0000; - baseAddress = (baseAddress & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << memSpace))); - return 1; - } - return 0; -} - - -/******************************************************************************* -* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 -* DMA channels. -********************************************************************************/ -int mvDmaTransfer (int engine, ulong sourceAddr, - ulong destAddr, ulong numOfBytes, ulong command) -{ - ulong engOffReg = 0; /* Engine Offset Register */ - - if (numOfBytes > 0xffff) { - command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; - } - command = command | ((command >> 6) & 0x7); - engOffReg = engine * 4; - GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg, - numOfBytes); - GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, - sourceAddr); - GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, - destAddr); - command = - command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 - /*DMA_NON_CHAIN_MODE */ ; - /* Activate DMA engine By writting to mvDmaControlRegister */ - GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command); - return 1; -} - -/**************************************************************************************** - * SDRAM INIT * - * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * - * This procedure fits only the Atlantis * - * * - ***************************************************************************************/ - - -/**************************************************************************************** - * DFCDL initialize MV643xx Design Considerations * - * * - ***************************************************************************************/ -int set_dfcdlInit (void) -{ - int i; - unsigned int dfcdl_word = 0x391; /* 0x14f; ronen new dfcdl */ - - for (i = 0; i < 64; i++) { - GT_REG_WRITE (SRAM_DATA0, dfcdl_word); -/* dfcdl_word += 0x41; - ronen new dfcdl */ - } - GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ - - return (0); -} diff --git a/board/Marvell/db64460/64460.h b/board/Marvell/db64460/64460.h deleted file mode 100644 index 9cf7feea58..0000000000 --- a/board/Marvell/db64460/64460.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * main board support/init for the Galileo Eval board DB64460. - */ - -#ifndef __64460_H__ -#define __64460_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64460_H__ */ diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile deleted file mode 100644 index a5f2c54556..0000000000 --- a/board/Marvell/db64460/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -SOBJS = ../common/misc.o - -COBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ - mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ - sdram_init.o ../common/intel_flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/Marvell/db64460/README b/board/Marvell/db64460/README deleted file mode 100644 index c6e01fe1ef..0000000000 --- a/board/Marvell/db64460/README +++ /dev/null @@ -1,105 +0,0 @@ -This file contains status information for the port of the U-Boot to the Marvell Development Board DB64460. - -Author: Ronen Shitrit - - -Supported CPU Types : -+++++++++++++++++++++ -IBM750Gx Rev 1.0 -MPC7457 Rev 1.1 - -Supported CPU Cache Library: -++++++++++++++++++++++++++++ - L1 and L2 only. - -CPU Control: -++++++++++++ - Marvell optimized CPU control settings: - Big Endian - Enable CPU pipeline - Data and address parity checking - AACK# assert after 2 cycles - -U-Boot I/O Interface Support: -+++++++++++++++++++++++++++++ -- Serial Interface (UART) - This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module. -- Network Interface - This LSP supports the following network devices: - o MV64360 Gigabit Ethernet Controller device - o Intel 82559 PCI NIC device -- PCI Interface - This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units: - o Local PCI configuration header control. - o External PCI configuration header control (for other agents on the bus). - o PCI configuration application. Scans and configures the PCI agents on the bus. - o PCI Internal Arbiter activation and configuration. - -Memory Interface Support: -+++++++++++++++++++++++++ -- DDR - o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs). - o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma. - -- Devices - o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM. - o JFFS2 - JFFS2 is a crash/power down safe file system for disk-less embedded devices. - This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it. - -Unsupported Features: -+++++++++++++++++++++ - Messaging unit - No support for MV64360 Messaging unit. - Watchdog Timer - No support for MV64360 Watchdog unit. - L3 cache - No support for L3 cache on MPC7455 - Dual PCU - No support for Dual CPU - PCI-X was never tested - IDMA driver - No support for MV64360 IDMA unit. - XOR Engine - No support for MV64460 XOR Engine - -BSP Special Considerations: -+++++++++++++++++++++++++++ -- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots. -- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical. - -Test Cases: -########### -UART: -+++++ -Check that the UART baud rate is configured to 57600 and 115200, and check: - Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom. - Load S-Record file over the UART using Windows HyperTerminal. - -Network: -++++++++ -Use TFTP application to load a debugged executable and execute it. -Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC. - -Memory: -+++++++ -Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters: -o 128MB DIMM consist of 16 x 64Mbit devices -o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz. -o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz. -o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz. -o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz. -o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz. -o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered - -For each chip select device perform data access to verify its accessibility. - -Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage. -Load the U-Boot and: -use the ls command to check correct scan of the JFFS2 on the large flash. -Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage. - -PCI: -++++ -1)Insert different PCI cards: -Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10 -on different slots (0-3) of the PCI and check: -o Correct detection of the PCI devices. -o Correct address mapping of the PCI devices. -2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot. - -Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal) diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c deleted file mode 100644 index 9baaaac8a8..0000000000 --- a/board/Marvell/db64460/db64460.c +++ /dev/null @@ -1,922 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com - */ - -/* - * db64460.c - main board support/init for the Galileo Eval board. - */ - -#include -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include -#include -#include - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64460.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; -int display_mem_map (void); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CONFIG_SYS_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64460 P.399 */ -#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6446x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6446x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) - sram_boot = 1; - if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - - memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); - - - /* configure device timing */ -#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ - if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); -#endif - -#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); -#endif -#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); -#endif - -#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CONFIG_SYS_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); - } - display_mem_map (); - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ - volatile int *addr = 0; - __maybe_unused int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x08000); - break; - - case 1: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x0c000); - break; - - case 2: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x14000); - break; - - case 1: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x18000); - break; - - case 2: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x1c000); - break; - } - } - - dummy = *addr; -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } - - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } - - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- EXT SRAM (actual - 1M)\n"); - else if (i == 1) - printf ("\t- RTC\n"); - else if (i == 2) - printf ("\t- UART\n"); - else - printf ("\t- LARGE FLASH\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n", - base, size >> 20, width); - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CONFIG_SYS_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; - const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; - const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata, runaddress, runwalk; - - rundata = getenv_yesno("testdramdata") == 1; - runaddress = getenv_yesno("testdramaddress") == 1; - runwalk = getenv_yesno("testdramwalk") == 1; - -/* rundata = 1; */ -/* runaddress = 0; */ -/* runwalk = 0; */ - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - } -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); - -/* Relocate MV64460 internal regs */ - my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); - - icache_disable (); - dcache_disable (); -} - -int board_eth_init(bd_t *bis) -{ - int ret; - ret = pci_eth_init(bis); - if (!ret) - ret = mv6446x_eth_initialize(bis); - return ret; -} diff --git a/board/Marvell/db64460/eth.h b/board/Marvell/db64460/eth.h deleted file mode 100644 index c2067a4d94..0000000000 --- a/board/Marvell/db64460/eth.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64460_ETH_H__ -#define __EVB64460_ETH_H__ - -#include -#include -#include -#include - -int db64460_eth0_poll(void); -int db64460_eth0_transmit(unsigned int s, volatile char *p); -void db64460_eth0_disable(void); -bool network_start(bd_t *bis); - -int mv6446x_eth_initialize(bd_t *); - -#endif /* __EVB64460_ETH_H__ */ diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c deleted file mode 100644 index 9fbbae87fa..0000000000 --- a/board/Marvell/db64460/mpsc.c +++ /dev/null @@ -1,1001 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64460 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include -#include -#include - -#include -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../include/memory.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#else - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64460 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* true for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/Marvell/db64460/mpsc.h b/board/Marvell/db64460/mpsc.h deleted file mode 100644 index 9e65e677e2..0000000000 --- a/board/Marvell/db64460/mpsc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64460 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c deleted file mode 100644 index 82fcadf31d..0000000000 --- a/board/Marvell/db64460/mv_eth.c +++ /dev/null @@ -1,3127 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include -#include -#include - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64460_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64460_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64460_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64460_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64460 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64460_eth_real_open (struct eth_device *eth); -static int mv64460_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64460_eth_update_stat (struct eth_device *dev); -bool db64460_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64460_eth_receive (struct eth_device *dev); - -int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64460_eth_print_stat (struct eth_device *dev); -#endif - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64460_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64460_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64460_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64460_eth - * - **********************************************************************/ -int db64460_eth_probe (struct eth_device *dev) -{ - return ((int) db64460_eth_start (dev)); -} - -int db64460_eth_poll (struct eth_device *dev) -{ - return mv64460_eth_receive (dev); -} - -int db64460_eth_transmit(struct eth_device *dev, void *packet, int length) -{ - mv64460_eth_xmit (dev, packet, length); - return 0; -} - -void db64460_eth_disable (struct eth_device *dev) -{ - mv64460_eth_stop (dev); -} - - -void mv6446x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64460_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64460_eth_transmit; - dev->recv = (void *) db64460_eth_poll; - - ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *)ethernet_private; - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64460_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64460_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64460_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64460_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64460_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64460_eth_open (struct eth_device *dev) -{ - return (mv64460_eth_real_open (dev)); -} - -/* Helper function for mv64460_eth_open */ -static int mv64460_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - u32 phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64460_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64460_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64460_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64460_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64460_eth_stop (struct eth_device *dev) -{ - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64460_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64460_eth_stop */ - -static int mv64460_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64460_eth_free_tx_rings (dev); - mv64460_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64460_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64460_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - pkt_info.return_info = 0; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64460_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64460_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64460_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64460_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - - mv64460_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64460_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64460_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64460_eth_start (struct eth_device *dev) -{ - return (mv64460_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) - MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/Marvell/db64460/mv_eth.h b/board/Marvell/db64460/mv_eth.h deleted file mode 100644 index 97a3a6661f..0000000000 --- a/board/Marvell/db64460/mv_eth.h +++ /dev/null @@ -1,815 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64460_ETH_H__ -#define __DB64460_ETH_H__ - -#include -#include -#include -#include -#include -#include "mv_regs.h" -#include - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64460_TX_QUEUE_NUM 1 -#define MV64460_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE -#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE -#else -#define MV64460_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE -#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE -#else -#define MV64460_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64460_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64460_TX_BUFFER_SIZE 1600 -#endif - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64460_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - -int mv64460_eth_init (struct eth_device *dev); -int mv64460_eth_stop (struct eth_device *dev); -int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length); -int mv64460_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64460_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64460_ETH_ */ diff --git a/board/Marvell/db64460/mv_regs.h b/board/Marvell/db64460/mv_regs.h deleted file mode 100644 index 4aefb3f683..0000000000 --- a/board/Marvell/db64460/mv_regs.h +++ /dev/null @@ -1,1108 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** -* gt64460r.h - GT-64460 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64460 - -/* Supported by the Atlantis */ -#define MV64460_INCLUDE_PCI_1 -#define MV64460_INCLUDE_PCI_0_ARBITER -#define MV64460_INCLUDE_PCI_1_ARBITER -#define MV64460_INCLUDE_SNOOP_SUPPORT -#define MV64460_INCLUDE_P2P -#define MV64460_INCLUDE_ETH_PORT_2 -#define MV64460_INCLUDE_CPU_MAPPING -#define MV64460_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64460_CS_0_BASE_ADDR 0x008 -#define MV64460_CS_0_SIZE 0x010 -#define MV64460_CS_1_BASE_ADDR 0x208 -#define MV64460_CS_1_SIZE 0x210 -#define MV64460_CS_2_BASE_ADDR 0x018 -#define MV64460_CS_2_SIZE 0x020 -#define MV64460_CS_3_BASE_ADDR 0x218 -#define MV64460_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64460_PCI_0_IO_BASE_ADDR 0x048 -#define MV64460_PCI_0_IO_SIZE 0x050 -#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64460_PCI_0_MEMORY0_SIZE 0x060 -#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64460_PCI_0_MEMORY1_SIZE 0x088 -#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64460_PCI_0_MEMORY2_SIZE 0x260 -#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64460_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64460_PCI_1_IO_BASE_ADDR 0x090 -#define MV64460_PCI_1_IO_SIZE 0x098 -#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64460_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64460_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64460_CPU_CONFIG 0x000 -#define MV64460_CPU_MODE 0x120 -#define MV64460_CPU_MASTER_CONTROL 0x160 -#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64460_SMP_WHO_AM_I 0x200 -#define MV64460_SMP_CPU0_DOORBELL 0x214 -#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64460_SMP_CPU1_DOORBELL 0x224 -#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64460_SMP_SEMAPHOR0 0x244 -#define MV64460_SMP_SEMAPHOR1 0x24c -#define MV64460_SMP_SEMAPHOR2 0x254 -#define MV64460_SMP_SEMAPHOR3 0x25c -#define MV64460_SMP_SEMAPHOR4 0x264 -#define MV64460_SMP_SEMAPHOR5 0x26c -#define MV64460_SMP_SEMAPHOR6 0x274 -#define MV64460_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64460_CPU_ERROR_ADDR_LOW 0x070 -#define MV64460_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64460_CPU_ERROR_DATA_LOW 0x128 -#define MV64460_CPU_ERROR_DATA_HIGH 0x130 -#define MV64460_CPU_ERROR_PARITY 0x138 -#define MV64460_CPU_ERROR_CAUSE 0x140 -#define MV64460_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64460_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64460_SRAM_CONFIG 0x380 -#define MV64460_SRAM_TEST_MODE 0X3F4 -#define MV64460_SRAM_ERROR_CAUSE 0x388 -#define MV64460_SRAM_ERROR_ADDR 0x390 -#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64460_SRAM_ERROR_DATA_LOW 0x398 -#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64460_SDRAM_CONFIG 0x1400 -#define MV64460_D_UNIT_CONTROL_LOW 0x1404 -#define MV64460_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64460_SDRAM_ADDR_CONTROL 0x1410 -#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64460_SDRAM_OPERATION 0x1418 -#define MV64460_SDRAM_MODE 0x141c -#define MV64460_EXTENDED_DRAM_MODE 0x1420 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64460_SDRAM_ERROR_ADDR 0x1450 -#define MV64460_SDRAM_RECEIVED_ECC 0x1448 -#define MV64460_SDRAM_CALCULATED_ECC 0x144c -#define MV64460_SDRAM_ECC_CONTROL 0x1454 -#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64460_DFCDL_CONFIG0 0x1480 -#define MV64460_DFCDL_CONFIG1 0x1484 -#define MV64460_DLL_WRITE 0x1488 -#define MV64460_DLL_READ 0x148c -#define MV64460_SRAM_ADDR 0x1490 -#define MV64460_SRAM_DATA0 0x1494 -#define MV64460_SRAM_DATA1 0x1498 -#define MV64460_SRAM_DATA2 0x149c -#define MV64460_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64460_DUNIT_DEBUG_LOW 0x1460 -#define MV64460_DUNIT_DEBUG_HIGH 0x1464 -#define MV64460_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64460_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64460_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64460_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64460_DEVICE_ERROR_ADDR 0x4d8 -#define MV64460_DEVICE_ERROR_DATA 0x4dc -#define MV64460_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64460_DEVICE_DEBUG_LOW 0x4e4 -#define MV64460_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64460_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64460_PCI_0_COMMAND 0xc00 -#define MV64460_PCI_1_COMMAND 0xc80 -#define MV64460_PCI_0_MODE 0xd00 -#define MV64460_PCI_1_MODE 0xd80 -#define MV64460_PCI_0_RETRY 0xc04 -#define MV64460_PCI_1_RETRY 0xc84 -#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64460_PCI_0_P2P_CONFIG 0x1d14 -#define MV64460_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64460_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64460_PCI_1_CONFIG_ADDR 0xc78 -#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64460_PCI_0_SERR_MASK 0xc28 -#define MV64460_PCI_1_SERR_MASK 0xca8 -#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64460_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64460_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64460_PCI_0_ERROR_MASK 0x1d5c -#define MV64460_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64460_PCI_0_MMASK 0X1D24 -#define MV64460_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64460_PCI_STATUS_AND_COMMAND 0x004 -#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64460_PCI_VPD_ADDR 0x048 -#define MV64460_PCI_VPD_DATA 0x04c -#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64460_PCI_X_COMMAND 0x060 -#define MV64460_PCI_X_STATUS 0x064 -#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64460_ETH_PHY_ADDR_REG 0x2000 -#define MV64460_ETH_SMI_REG 0x2004 -#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64460_ETH_BAR_0 0x2200 -#define MV64460_ETH_BAR_1 0x2208 -#define MV64460_ETH_BAR_2 0x2210 -#define MV64460_ETH_BAR_3 0x2218 -#define MV64460_ETH_BAR_4 0x2220 -#define MV64460_ETH_BAR_5 0x2228 -#define MV64460_ETH_SIZE_REG_0 0x2204 -#define MV64460_ETH_SIZE_REG_1 0x220c -#define MV64460_ETH_SIZE_REG_2 0x2214 -#define MV64460_ETH_SIZE_REG_3 0x221c -#define MV64460_ETH_SIZE_REG_4 0x2224 -#define MV64460_ETH_SIZE_REG_5 0x222c -#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64460_CUNIT_SIZE0 0xf204 -#define MV64460_CUNIT_SIZE1 0xf20c -#define MV64460_CUNIT_SIZE2 0xf214 -#define MV64460_CUNIT_SIZE3 0xf21c -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64460_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64460_CUNIT_CONFIG_REG 0xb40c -#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64460_CUNIT_DEBUG_LOW 0xf340 -#define MV64460_CUNIT_DEBUG_HIGH 0xf344 -#define MV64460_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64460_MPSC_ROUTING_REG 0xb400 -#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64460_SDMA_CAUSE_REG 0xb800 -#define MV64460_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64460_SDMA_SRAM_TARGET 0x0003 -#define MV64460_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64460_PCI_0_TARGET 0x0003 -#define MV64460_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64460_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64460_BRG_CAUSE_REG 0xb834 -#define MV64460_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_CONTROL 0x840 -#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64460_DMA_CHANNEL1_CONTROL 0x844 -#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64460_DMA_CHANNEL2_CONTROL 0x848 -#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64460_DMA_CHANNEL3_CONTROL 0x84C -#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64460_DMA_BASE_ADDR_REG0 0xa00 -#define MV64460_DMA_BASE_ADDR_REG1 0xa08 -#define MV64460_DMA_BASE_ADDR_REG2 0xa10 -#define MV64460_DMA_BASE_ADDR_REG3 0xa18 -#define MV64460_DMA_BASE_ADDR_REG4 0xa20 -#define MV64460_DMA_BASE_ADDR_REG5 0xa28 -#define MV64460_DMA_BASE_ADDR_REG6 0xa30 -#define MV64460_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64460_DMA_SIZE_REG0 0xa04 -#define MV64460_DMA_SIZE_REG1 0xa0c -#define MV64460_DMA_SIZE_REG2 0xa14 -#define MV64460_DMA_SIZE_REG3 0xa1c -#define MV64460_DMA_SIZE_REG4 0xa24 -#define MV64460_DMA_SIZE_REG5 0xa2c -#define MV64460_DMA_SIZE_REG6 0xa34 -#define MV64460_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64460_DMA_ARBITER_CONTROL 0x860 -#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64460_DMA_ERROR_ADDR 0x8c8 -#define MV64460_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64460_DMA_DEBUG_LOW 0x8e0 -#define MV64460_DMA_DEBUG_HIGH 0x8e4 -#define MV64460_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64460_TIMER_COUNTER0 0x850 -#define MV64460_TIMER_COUNTER1 0x854 -#define MV64460_TIMER_COUNTER2 0x858 -#define MV64460_TIMER_COUNTER3 0x85C -#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64460_WATCHDOG_CONFIG_REG 0xb410 -#define MV64460_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64460_I2C_SLAVE_ADDR 0xc000 -#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64460_I2C_DATA 0xc004 -#define MV64460_I2C_CONTROL 0xc008 -#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64460_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64460_GPP_IO_CONTROL 0xf100 -#define MV64460_GPP_LEVEL_CONTROL 0xf110 -#define MV64460_GPP_VALUE 0xf104 -#define MV64460_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64460_GPP_INTERRUPT_MASK0 0xf10c -#define MV64460_GPP_INTERRUPT_MASK1 0xf114 -#define MV64460_GPP_VALUE_SET 0xf118 -#define MV64460_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64460_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64460_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64460_MPP_CONTROL0 0xf000 -#define MV64460_MPP_CONTROL1 0xf004 -#define MV64460_MPP_CONTROL2 0xf008 -#define MV64460_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64460_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64460_SERIAL_INIT_CONTROL 0xf328 -#define MV64460_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64460rh */ diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c deleted file mode 100644 index 8c25198e3b..0000000000 --- a/board/Marvell/db64460/pci.c +++ /dev/null @@ -1,923 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PCI.c - PCI functions */ - - -#include -#include - -#include "../include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 MHz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 MHz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 MHz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c deleted file mode 100644 index 71c2d9eb32..0000000000 --- a/board/Marvell/db64460/sdram_init.c +++ /dev/null @@ -1,1950 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * adaption for the Marvell DB64460 Board - * Ingo Assmus (ingo.assmus@keymile.com) - ************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "../common/i2c.h" -#include "64460.h" -#include "mv_regs.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define MAP_PCI - -int set_dfcdlInit (void); /* setup delay line of Mv64460 */ -int mvDmaIsChannelActive (int); -int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); -int mvDmaTransfer (int, ulong, ulong, ulong, ulong); - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - - if (bankLength > 0) { - debug("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - debug("unmapping bank %d\n", bankNo); - } - - memoryMapBank (bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; - -typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, -} VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = - 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = - 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD { SD_CL_1 = - 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, - SD_FAULT } MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - unsigned long spd_checksum; - -#ifdef ZUMA_NTL - /* zero all the values */ - memset (info, 0, sizeof (*info)); - -/* - if (!slot) { - info->slot = 0; - info->banks = 1; - info->registered = 0; - info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ -/* info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -*/ -#ifdef CONFIG_MV64460_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - dimmInfo->errorCheckType = 2; -/* info->ecc = 2;*/ -#endif -} - -return 0; - -#else - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, tras_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - debug("before i2c read\n"); - - ret = i2c_read (addr, 0, 1, data, 128); - - debug("after i2c read\n"); - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - debug("No DIMM in slot %d [err = %x]\n", slot, ret); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG -/* find Manufactura of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - -/* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - -/* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - -/* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - -/* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - -/* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - -/* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif - -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; - - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); - - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG - if (dimmInfo->memoryType == 0) - debug - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot); - if (dimmInfo->memoryType == 1) - debug - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - debug - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - debug - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - debug - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - debug - ("Module Data Width: %d\n", - dimmInfo->dataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - debug - ("Module is TTL_5V_TOLERANT\n"); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - debug - ("Module is LVTTL\n"); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - debug - ("Module is TTL_5V_TOLERANT\n"); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - debug - ("Module is HSTL_1_5V\n"); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - debug - ("Module is SSTL_2_5V\n"); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - debug - ("Module is VOLTAGE_UNKNOWN\n"); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - debug - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -/*#ifdef CONFIG_ECC */ - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - debug - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType); - break; -/* #endif */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - debug - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - debug - ("Sdram Width: %d\n", - dimmInfo->sdramWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - debug - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - debug - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - debug - ("Burst Length Supported: "); - if (dimmInfo->burstLengthSupported & 0x01) - debug("1, "); - if (dimmInfo->burstLengthSupported & 0x02) - debug("2, "); - if (dimmInfo->burstLengthSupported & 0x04) - debug("4, "); - if (dimmInfo->burstLengthSupported & 0x08) - debug("8, "); - debug(" Bit \n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - debug - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - debug - ("Suported Cas Latencies: (CL) "); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - debug - ("%d, ", - k + 1); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - debug("1, "); - if (dimmInfo->suportedCasLatencies & 2) - debug("1.5, "); - if (dimmInfo->suportedCasLatencies & 4) - debug("2, "); - if (dimmInfo->suportedCasLatencies & 8) - debug("2.5, "); - if (dimmInfo->suportedCasLatencies & 16) - debug("3, "); - if (dimmInfo->suportedCasLatencies & 32) - debug("3.5, "); - - } - debug("\n"); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - debug - ("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - debug - ("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - debug - ("Max. Cas Latencies (DDR): 3.5 clk's\n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - debug - ("Max. Cas Latencies (DDR): 3 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - debug - ("Max. Cas Latencies (DDR): 2.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - debug - ("Max. Cas Latencies (DDR): 2 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - debug - ("Max. Cas Latencies (DDR): 1.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - - /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy - lower then our SDRAM cycle count, we won't be able to support this CAL - and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - < - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - < - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - dimmInfo-> - maxClSupported_DDR - = - dimmInfo-> - maxClSupported_DDR - >> 1; - debug - ("*** Change actual Cas Latencies cause of minimumCycleTime n"); - } - /* ronen - checkif the Dimm frequency compared to the Sysclock. */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - > - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - > - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - printf ("*********************************************************\n"); - printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); - printf ("*********************************************************\n"); - hang (); - } - - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - debug - ("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - debug("\nModul Attributes (SPD Byte 21): \n"); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; -#ifdef DEBUG - if (dimmInfo->bufferedAddrAndControlInputs == 1) - debug - (" - Buffered Address/Control Input: Yes \n"); - else - debug - (" - Buffered Address/Control Input: No \n"); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - debug - (" - Registered Address/Control Input: Yes \n"); - else - debug - (" - Registered Address/Control Input: No \n"); - - if (dimmInfo->onCardPLL == 1) - debug - (" - On-Card PLL (clock): Yes \n"); - else - debug - (" - On-Card PLL (clock): No \n"); - - if (dimmInfo->bufferedDQMBinputs == 1) - debug - (" - Bufferd DQMB Inputs: Yes \n"); - else - debug - (" - Bufferd DQMB Inputs: No \n"); - - if (dimmInfo->registeredDQMBinputs == 1) - debug - (" - Registered DQMB Inputs: Yes \n"); - else - debug - (" - Registered DQMB Inputs: No \n"); - - if (dimmInfo->differentialClockInput == 1) - debug - (" - Differential Clock Input: Yes \n"); - else - debug - (" - Differential Clock Input: No \n"); - - if (dimmInfo->redundantRowAddressing == 1) - debug - (" - redundant Row Addressing: Yes \n"); - else - debug - (" - redundant Row Addressing: No \n"); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - debug("\nModul Attributes (SPD Byte 22): \n"); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; -#ifdef DEBUG - if (dimmInfo->suportedEarlyRasPreCharge == 1) - debug - (" - Early Ras Precharge: Yes \n"); - else - debug - (" - Early Ras Precharge: No \n"); - - if (dimmInfo->suportedAutoPreCharge == 1) - debug - (" - AutoPreCharge: Yes \n"); - else - debug - (" - AutoPreCharge: No \n"); - - if (dimmInfo->suportedPreChargeAll == 1) - debug - (" - Precharge All: Yes \n"); - else - debug - (" - Precharge All: No \n"); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - debug - (" - Write 1/ReadBurst: Yes \n"); - else - debug - (" - Write 1/ReadBurst: No \n"); - - if (dimmInfo->suported5PercentLowVCC == 1) - debug - (" - lower VCC tolerance: 5 Percent \n"); - else - debug - (" - lower VCC tolerance: 10 Percent \n"); - - if (dimmInfo->suported5PercentUpperVCC == 1) - debug - (" - upper VCC tolerance: 5 Percent \n"); - else - debug - (" - upper VCC tolerance: 10 Percent \n"); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - debug - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - debug - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - debug - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100); - debug - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - debug - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - debug - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity); -#ifdef DEBUG - debug - ("*** Offered Densities (more than 1 = Multisize-Module): "); - { - if (dimmInfo->moduleBankDensity & 1) - debug("4MB, "); - if (dimmInfo->moduleBankDensity & 2) - debug("8MB, "); - if (dimmInfo->moduleBankDensity & 4) - debug("16MB, "); - if (dimmInfo->moduleBankDensity & 8) - debug("32MB, "); - if (dimmInfo->moduleBankDensity & 16) - debug("64MB, "); - if (dimmInfo->moduleBankDensity & 32) - debug("128MB, "); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - debug("ERROR, "); - hang (); - } - } - debug("\n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - - /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ - dimmInfo->numberOfDevices / 8); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; - - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - debug("cal_val = %d\n", cal_val); - - /* bummer, did't work... */ - if (cal_val == 0) { - debug("Couldn't find a good CAS latency\n"); - hang (); - return 0; - } - - return true; -#endif -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp, check; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - int i; - - /* added 8/21/2003 P. Marchese */ - unsigned int sdram_config_reg; - - /* added 10/10/2003 P. Marchese */ - ulong sdram_chip_size; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - debug("Delay line set done\n"); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); - } - - /* SDRAM configuration */ -/* added 8/21/2003 P. Marchese */ -/* code allows usage of registered DIMMS */ - - /* figure out the memory refresh internal */ - switch (info->RefreshInterval) { - case 0x0: - case 0x80: /* refresh period is 15.625 usec */ - sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK) - / (float) 1000000.0); - break; - case 0x1: - case 0x81: /* refresh period is 3.9 usec */ - sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x2: - case 0x82: /* refresh period is 7.8 usec */ - sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x3: - case 0x83: /* refresh period is 31.3 usec */ - sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x4: - case 0x84: /* refresh period is 62.5 usec */ - sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x5: - case 0x85: /* refresh period is 125 usec */ - sdram_config_reg = - (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - default: /* refresh period undefined */ - printf ("DRAM refresh period is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - debug("calculated refresh interval %0x\n", sdram_config_reg); - - /* make sure the refresh value is only 14 bits */ - if (sdram_config_reg > 0x1fff) - sdram_config_reg = 0x1fff; - debug("adjusted refresh interval %0x\n", sdram_config_reg); - - /* we want physical bank interleaving and */ - /* virtual bank interleaving enabled so do nothing */ - /* since these bits need to be zero to enable the interleaving */ - - /* registered DRAM ? */ - if (info->registeredAddrAndControlInputs == 1) { - /* it's registered DRAM, so set the reg. DRAM bit */ - sdram_config_reg = sdram_config_reg | BIT17; - debug("Enabling registered DRAM bit\n"); - } - /* turn on DRAM ECC? */ -#ifdef CONFIG_MV64460_ECC - if (info->errorCheckType == 0x2) { - /* DRAM has ECC, so turn it on */ - sdram_config_reg = sdram_config_reg | BIT18; - debug("Enabling ECC\n"); - } -#endif - /* set the data DQS pin configuration */ - switch (info->sdramWidth) { - case 0x4: /* memory is x4 */ - sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - debug("Data DQS pins set for 16 pins\n"); - break; - case 0x8: /* memory is x8 or x16 */ - case 0x10: - sdram_config_reg = sdram_config_reg | BIT21; - debug("Data DQS pins set for 8 pins\n"); - break; - case 0x20: /* memory is x32 */ - /* both bits are cleared for x32 so nothing to do */ - debug("Data DQS pins set for 2 pins\n"); - break; - default: /* memory width unsupported */ - printf ("DRAM chip width is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - - /*ronen db64460 */ - /* perform read buffer assignments */ - /* we are going to use the Power-up defaults */ - /* bit 27 = PCI bus #0 = buffer 0 */ - /* bit 28 = PCI bus #1 = buffer 0 */ - /* bit 29 = MPSC = buffer 0 */ - /* bit 30 = IDMA = buffer 0 */ - /* bit 31 = Gigabit = buffer 0 */ - sdram_config_reg = sdram_config_reg | 0x58000000; - sdram_config_reg = sdram_config_reg & 0xffffff00; - /* bit 14 FBSplit = FCRAM controller bsplit enable. */ - /* bit 15 vw = FCRAM Variable write length enable. */ - /* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */ - sdram_config_reg = sdram_config_reg | BIT14 | BIT15; - - /* write the value into the SDRAM configuration register */ - GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM open pages control keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - debug - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - debug("Core Signals are sync (by HW-Setting)!!!\n"); - else - debug - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); - - /* SDRAM set CAS Latency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - printf ("### SD-RAM not supported !!!\n"); - printf ("Aborting!!!\n"); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - /* Calculate the settings for SDRAM mode and Dunit control low registers */ - /* Values set according to technical bulletin TB-92 rev. c */ - case DDR: - debug("### SET-CL for DDR-RAM\n"); - /* ronen db64460 - change the tmp_dunit_control_low setting!!! */ - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x05110051; - else - tmp_dunit_control_low = 0x24110051; - debug - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0xC5000540; - else - tmp_dunit_control_low = 0xC4000540; - debug - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_2_5: - tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x25110051; - else - tmp_dunit_control_low = 0x24110051; - debug - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0xC5000540; - /* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /* printf("Aborting!!!\n");1 */ - /* hang();1 */ - } else - tmp_dunit_control_low = 0xC4000540; - debug - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_2: - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x04110051; - else - tmp_dunit_control_low = 0x03110051; - debug - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - /*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /*printf("Aborting!!!\n");1 */ - /*hang();1 */ - tmp_dunit_control_low = 0xC4000540; - } else - tmp_dunit_control_low = 0xC3000540;; - debug - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_1_5: - tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x24110051; - else - tmp_dunit_control_low = 0x23110051; - debug - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - /*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /*printf("Aborting!!!\n");1 */ - /*hang();1 */ - tmp_dunit_control_low = 0xC4000540; - } else - tmp_dunit_control_low = 0xC3000540; - debug - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } /* end DDR switch */ - break; - } /* end CL switch */ - - /* Write results of CL detection procedure */ - /* set SDRAM mode reg. 0x141c */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); - } - -/*------------------------------------------------------------------------------ */ - - /* bank parameters */ - /* SDRAM address decode register 0x1410 */ - /* program this with the default value */ - tmp = 0x02; /* power-up default address select decoding value */ - - debug("drb_size (n*64Mbit): %d\n", info->drb_size); -/* figure out the DRAM chip size */ - sdram_chip_size = - (1 << (info->numOfRowAddresses + info->numOfColAddresses)); - sdram_chip_size *= info->sdramWidth; - sdram_chip_size *= 4; - debug("computed sdram chip size is %#lx\n", sdram_chip_size); - /* divide sdram chip size by 64 Mbits */ - sdram_chip_size = sdram_chip_size / 0x4000000; - switch (sdram_chip_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - debug("RAM-Device_size 64Mbit or 128Mbit)\n"); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - debug("RAM-Device_size 256Mbit or 512Mbit)\n"); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - debug("RAM-Device_size 1Gbit or 2Gbit)\n"); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - printf ("RAM-Device_size is unsupported\n"); - hang (); - } - - /* SDRAM address control */ - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - debug - ("setting up sdram address control (0x1410) with: %08lx \n", - tmp); - -/* ------------------------------------------------------------------------------ */ -/* same settings for registerd & non-registerd DDR SDRAM */ - debug - ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x01501220); - /*ronen db64460 */ - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - debug - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -4460 */ - tmp |= (1 << 26); - debug - ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG)); - debug - ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM timing To_do: */ -/* ------------------------------------------------------------------------------ */ - /* ronen db64460 */ - debug - ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0xc); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc); - - debug - ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a); - GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - - debug - ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a); - GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); - -/* ------------------------------------------------------------------------------ */ - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - i = info->slot; - debug - ("\n*** Running a MRS cycle for bank %d ***\n", i); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - check = GTREGREAD (SDRAM_OPERATION); - debug - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check); - - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0); - check = GTREGREAD (SDRAM_OPERATION); - debug - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; - -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - debug - ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr); - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -phys_size_t initdram (int board_type) -{ - int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int nhr, bank_no; - ulong dest, memSpaceAttr; - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - check_dimm (0, &dimmInfo1); - - /* DIMM1 */ - check_dimm (1, &dimmInfo2); - - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* ronen check correct set of DIMMS */ - if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { - if (dimmInfo1.errorCheckType != - dimmInfo2.errorCheckType) - printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); - if (dimmInfo1.maxClSupported_DDR != - dimmInfo2.maxClSupported_DDR) - printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); - if (dimmInfo1.registeredAddrAndControlInputs != - dimmInfo2.registeredAddrAndControlInputs) - printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); - } - - if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - if (dimmInfo1.numOfModuleBanks > 0) { - checkbank[0] = 1; - } - if (dimmInfo1.numOfModuleBanks > 1) { - checkbank[1] = 1; - } - if (dimmInfo1.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); - - if (dimmInfo2.numOfModuleBanks > 0) { - checkbank[2] = 1; - } - if (dimmInfo2.numOfModuleBanks > 1) { - checkbank[3] = 1; - } - if (dimmInfo2.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - /* ronen - realsize = dram_size((long int *)total, check); */ - if (bank_no == 0 || bank_no == 1) { - if (checkbank[1] == 1) - realsize = dimmInfo1.size / 2; - else - realsize = dimmInfo1.size; - } - if (bank_no == 2 || bank_no == 3) { - if (checkbank[3] == 1) - realsize = dimmInfo2.size / 2; - else - realsize = dimmInfo2.size; - } - memory_map_bank (bank_no, total, realsize); - - /* ronen - initialize the DRAM for ECC */ -#ifdef CONFIG_MV64460_ECC - if ((dimmInfo1.errorCheckType != 0) && - ((dimmInfo2.errorCheckType != 0) - || (dimmInfo2.numOfModuleBanks == 0))) { - printf ("ECC Initialization of Bank %d:", bank_no); - memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; - mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, - realsize); - for (dest = total; dest < total + realsize; - dest += _8M) { - mvDmaTransfer (0, total, dest, _8M, - BIT8 /*DMA_DTL_128BYTES */ | - BIT3 /*DMA_HOLD_SOURCE_ADDR */ - | - BIT11 - /*DMA_BLOCK_TRANSFER_MODE */ ); - while (mvDmaIsChannelActive (0)); - } - printf (" PASS\n"); - } -#endif - - total += realsize; - } - - /* ronen */ - switch ((GTREGREAD (0x141c) >> 4) & 0x7) { - case 0x2: - printf ("CAS Latency = 2"); - break; - case 0x3: - printf ("CAS Latency = 3"); - break; - case 0x5: - printf ("CAS Latency = 1.5"); - break; - case 0x6: - printf ("CAS Latency = 2.5"); - break; - } - printf (" tRP = %d tRAS = %d tRCD=%d\n", - ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); - -/* Setup Ethernet DMA Adress window to DRAM Area */ - if (total > _256M) - printf ("*** ONLY the first 256MB DRAM memory are used out of the "); - else - printf ("Total SDRAM memory is "); - /* (cause all the 4 BATS are taken) */ - return (total); -} - - -/* ronen- add Idma functions for usage of the ecc dram init. */ -/******************************************************************************* -* mvDmaIsChannelActive - Checks if a engine is busy. -********************************************************************************/ -int mvDmaIsChannelActive (int engine) -{ - ulong data; - - data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine); - if (data & BIT14 /*activity status */ ) { - return 1; - } - return 0; -} - -/******************************************************************************* -* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding -* map. -*******************************************************************************/ -int mvDmaSetMemorySpace (ulong memSpace, - ulong memSpaceTarget, - ulong memSpaceAttr, ulong baseAddress, ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return 0; - } - if (size >= 0x10000 /*64K */ ) { - size &= 0xffff0000; - baseAddress = (baseAddress & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << memSpace))); - return 1; - } - return 0; -} - - -/******************************************************************************* -* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 -* DMA channels. -********************************************************************************/ -int mvDmaTransfer (int engine, ulong sourceAddr, - ulong destAddr, ulong numOfBytes, ulong command) -{ - ulong engOffReg = 0; /* Engine Offset Register */ - - if (numOfBytes > 0xffff) { - command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; - } - command = command | ((command >> 6) & 0x7); - engOffReg = engine * 4; - GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, - numOfBytes); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, - sourceAddr); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, - destAddr); - command = - command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 - /*DMA_NON_CHAIN_MODE */ ; - /* Activate DMA engine By writting to mvDmaControlRegister */ - GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command); - return 1; -} - -/**************************************************************************************** - * SDRAM INIT * - * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * - * This procedure fits only the Atlantis * - * * - ***************************************************************************************/ - - -/**************************************************************************************** - * DFCDL initialize MV643xx Design Considerations * - * * - ***************************************************************************************/ -int set_dfcdlInit (void) -{ - /*ronen the dfcdl init are done by the I2C */ - return (0); -} diff --git a/board/Marvell/dkb/Kconfig b/board/Marvell/dkb/Kconfig new file mode 100644 index 0000000000..f6748941c6 --- /dev/null +++ b/board/Marvell/dkb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DKB + +config SYS_BOARD + default "dkb" + +config SYS_VENDOR + default "Marvell" + +config SYS_SOC + default "pantheon" + +config SYS_CONFIG_NAME + default "dkb" + +endif diff --git a/board/Marvell/dkb/MAINTAINERS b/board/Marvell/dkb/MAINTAINERS new file mode 100644 index 0000000000..c272b7ae74 --- /dev/null +++ b/board/Marvell/dkb/MAINTAINERS @@ -0,0 +1,6 @@ +DKB BOARD +M: Lei Wen +S: Maintained +F: board/Marvell/dkb/ +F: include/configs/dkb.h +F: configs/dkb_defconfig diff --git a/board/Marvell/dkb/Makefile b/board/Marvell/dkb/Makefile index 9173154e06..9d88579120 100644 --- a/board/Marvell/dkb/Makefile +++ b/board/Marvell/dkb/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := dkb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dkb.o diff --git a/board/Marvell/dreamplug/Kconfig b/board/Marvell/dreamplug/Kconfig new file mode 100644 index 0000000000..f65ff73713 --- /dev/null +++ b/board/Marvell/dreamplug/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DREAMPLUG + +config SYS_BOARD + default "dreamplug" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "dreamplug" + +endif diff --git a/board/Marvell/dreamplug/MAINTAINERS b/board/Marvell/dreamplug/MAINTAINERS new file mode 100644 index 0000000000..2561ba8134 --- /dev/null +++ b/board/Marvell/dreamplug/MAINTAINERS @@ -0,0 +1,6 @@ +DREAMPLUG BOARD +M: Jason Cooper +S: Maintained +F: board/Marvell/dreamplug/ +F: include/configs/dreamplug.h +F: configs/dreamplug_defconfig diff --git a/board/Marvell/dreamplug/Makefile b/board/Marvell/dreamplug/Makefile index ef09f3b5d0..23e6c53184 100644 --- a/board/Marvell/dreamplug/Makefile +++ b/board/Marvell/dreamplug/Makefile @@ -9,30 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := dreamplug.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dreamplug.o diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index b53c81080d..0887d92c29 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include "dreamplug.h" @@ -25,9 +25,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(DREAMPLUG_OE_VAL_LOW, - DREAMPLUG_OE_VAL_HIGH, - DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); + mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW, + DREAMPLUG_OE_VAL_HIGH, + DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -90,7 +90,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/gplugd/Kconfig b/board/Marvell/gplugd/Kconfig new file mode 100644 index 0000000000..d944816509 --- /dev/null +++ b/board/Marvell/gplugd/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GPLUGD + +config SYS_BOARD + default "gplugd" + +config SYS_VENDOR + default "Marvell" + +config SYS_SOC + default "armada100" + +config SYS_CONFIG_NAME + default "gplugd" + +endif diff --git a/board/Marvell/gplugd/MAINTAINERS b/board/Marvell/gplugd/MAINTAINERS new file mode 100644 index 0000000000..320bc09de5 --- /dev/null +++ b/board/Marvell/gplugd/MAINTAINERS @@ -0,0 +1,6 @@ +GPLUGD BOARD +M: Ajay Bhargav +S: Maintained +F: board/Marvell/gplugd/ +F: include/configs/gplugd.h +F: configs/gplugd_defconfig diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile index 139f316ce5..b38457845d 100644 --- a/board/Marvell/gplugd/Makefile +++ b/board/Marvell/gplugd/Makefile @@ -12,24 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := gplugd.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := gplugd.o diff --git a/board/Marvell/guruplug/Kconfig b/board/Marvell/guruplug/Kconfig new file mode 100644 index 0000000000..529e6e3b4b --- /dev/null +++ b/board/Marvell/guruplug/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GURUPLUG + +config SYS_BOARD + default "guruplug" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "guruplug" + +endif diff --git a/board/Marvell/guruplug/MAINTAINERS b/board/Marvell/guruplug/MAINTAINERS new file mode 100644 index 0000000000..b5d0734831 --- /dev/null +++ b/board/Marvell/guruplug/MAINTAINERS @@ -0,0 +1,6 @@ +GURUPLUG BOARD +M: Siddarth Gore +S: Maintained +F: board/Marvell/guruplug/ +F: include/configs/guruplug.h +F: configs/guruplug_defconfig diff --git a/board/Marvell/guruplug/Makefile b/board/Marvell/guruplug/Makefile index f835762cb4..974497a334 100644 --- a/board/Marvell/guruplug/Makefile +++ b/board/Marvell/guruplug/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := guruplug.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := guruplug.o diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 72bccc821c..b0d5f1e10f 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "guruplug.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(GURUPLUG_OE_VAL_LOW, - GURUPLUG_OE_VAL_HIGH, - GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); + mvebu_config_gpio(GURUPLUG_OE_VAL_LOW, + GURUPLUG_OE_VAL_HIGH, + GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h deleted file mode 100644 index 3119d0a073..0000000000 --- a/board/Marvell/include/core.h +++ /dev/null @@ -1,236 +0,0 @@ -/* Core.h - Basic core logic functions and definitions */ - -/* Copyright Galileo Technology. */ - -/* -DESCRIPTION -This header file contains simple read/write macros for addressing -the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address -space). The macros take care of Big/Little endian conversions. -*/ - -#ifndef __INCcoreh -#define __INCcoreh - -#include "mv_gen_reg.h" - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/****************************************/ -/* GENERAL Definitions */ -/****************************************/ - -#define NO_BIT 0x00000000 -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#define _1K 0x00000400 -#define _2K 0x00000800 -#define _4K 0x00001000 -#define _8K 0x00002000 -#define _16K 0x00004000 -#define _32K 0x00008000 -#define _64K 0x00010000 -#define _128K 0x00020000 -#define _256K 0x00040000 -#define _512K 0x00080000 - -#define _1M 0x00100000 -#define _2M 0x00200000 -#define _3M 0x00300000 -#define _4M 0x00400000 -#define _5M 0x00500000 -#define _6M 0x00600000 -#define _7M 0x00700000 -#define _8M 0x00800000 -#define _9M 0x00900000 -#define _10M 0x00a00000 -#define _11M 0x00b00000 -#define _12M 0x00c00000 -#define _13M 0x00d00000 -#define _14M 0x00e00000 -#define _15M 0x00f00000 -#define _16M 0x01000000 - -#define _32M 0x02000000 -#define _64M 0x04000000 -#define _128M 0x08000000 -#define _256M 0x10000000 -#define _512M 0x20000000 - -#define _1G 0x40000000 -#define _2G 0x80000000 - -/* Little to Big endian conversion macros */ - -#ifdef LE /* Little Endian */ -#define SHORT_SWAP(X) (X) -#define WORD_SWAP(X) (X) -#define LONG_SWAP(X) ((l64)(X)) - -#else /* Big Endian */ -#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) - -#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ - (((X)&0xff00)<<8)+ \ - (((X)&0xff0000)>>8)+ \ - (((X)&0xff000000)>>24) - -#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ - (((X)&0xff00ULL)<<40)+ \ - (((X)&0xff0000ULL)<<24)+ \ - (((X)&0xff000000ULL)<<8)+ \ - (((X)&0xff00000000ULL)>>8)+ \ - (((X)&0xff0000000000ULL)>>24)+ \ - (((X)&0xff000000000000ULL)>>40)+ \ - (((X)&0xff00000000000000ULL)>>56)) - -#endif - -#ifndef NULL -#define NULL 0 -#endif - -/* Those two definitions were defined to be compatible with MIPS */ -#define NONE_CACHEABLE 0x00000000 -#define CACHEABLE 0x00000000 - -/* 750 cache line */ -#define CACHE_LINE_SIZE 32 -#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) -#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) - -/* Read/Write to/from GT`s internal registers */ -#define GT_REG_READ(offset, pData) \ -*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ -*pData = WORD_SWAP(*pData) - -#define GTREGREAD(offset) \ - (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) )) - -#define GT_REG_WRITE(offset, data) \ -*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ - WORD_SWAP(data) - -/* Write 32/16/8 bit */ -#define WRITE_CHAR(address, data) \ - *((unsigned char *)(address)) = data -#define WRITE_SHORT(address, data) \ - *((unsigned short *)(address)) = data -#define WRITE_WORD(address, data) \ - *((unsigned int *)(address)) = data - -#define GT_WRITE_CHAR(address, data) WRITE_CHAR(address, data) - -/* Write 32/16/8 bit NonCacheable */ -/* -#define GT_WRITE_CHAR(address, data) \ - (*((unsigned char *)NONE_CACHEABLE(address))) = data -#define GT_WRITE_SHORT(address, data) \ - (*((unsigned short *)NONE_CACHEABLE(address))) = data -#define GT_WRITE_WORD(address, data) \ - (*((unsigned int *)NONE_CACHEABLE(address))) = data -*/ - /*#define GT_WRITE_CHAR(address, data) ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */ - - /*#define GT_WRITE_SHORT(address, data) ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */ - - /*#define GT_WRITE_WORD(address, data) ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */ - - -/* Read 32/16/8 bits - returns data in variable. */ -#define READ_CHAR(address, pData) \ - *pData = *((volatile unsigned char *)(address)) - -#define READ_SHORT(address, pData) \ - *pData = *((volatile unsigned short *)(address)) - -#define READ_WORD(address, pData) \ - *pData = *((volatile unsigned int *)(address)) - -/* Read 32/16/8 bit - returns data direct. */ -#define READCHAR(address) \ - *((volatile unsigned char *)((address) | NONE_CACHEABLE)) - -#define READSHORT(address) \ - *((volatile unsigned short *)((address) | NONE_CACHEABLE)) - -#define READWORD(address) \ - *((volatile unsigned int *)((address) | NONE_CACHEABLE)) - -/* Those two Macros were defined to be compatible with MIPS */ -#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) -#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE) - -/* SET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '1' in the - internal register the bits which given as an input example: - SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '1' in register 0x840 while the other bits stays as is. */ -#define SET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ - regOffset) |= (unsigned int)WORD_SWAP(bits) - -/* RESET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '0' in the - internal register the bits which given as an input example: - RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '0' in register 0x840 while the other bits stays as is. */ -#define RESET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ - | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) -/* gets register offset and bits: a 32bit value. It set to logic '1' in the - internal register the bits which given as an input example: - GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '1' in register 0x840 while the other bits stays as is. */ - /*#define GT_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */ - /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */ -#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits) -/* gets register offset and bits: a 32bit value. It set to logic '0' in the - internal register the bits which given as an input example: - GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to - logic '0' in register 0x840 while the other bits stays as is. */ - /*#define GT_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */ -#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits) - - -#define DEBUG_LED0_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0) -#define DEBUG_LED1_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0) -#define DEBUG_LED2_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0) -#define DEBUG_LED0_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0) -#define DEBUG_LED1_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0) -#define DEBUG_LED2_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0) - -#endif /* __INCcoreh */ diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h deleted file mode 100644 index 008185ec78..0000000000 --- a/board/Marvell/include/mv_gen_reg.h +++ /dev/null @@ -1,2296 +0,0 @@ -/* mv_gen_reg.h - Internal registers definition file */ -/* Copyright - Galileo technology. */ - - -/******************************************************************************* -* Copyright 2002, GALILEO TECHNOLOGY, LTD. * -* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -* * -* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI). * -******************************************************************************** -* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_gen_regh -#define __INCmv_gen_regh - - -/* Supported by the Atlantis */ -#define INCLUDE_PCI_1 -#define INCLUDE_PCI_0_ARBITER -#define INCLUDE_PCI_1_ARBITER -#define INCLUDE_SNOOP_SUPPORT -#define INCLUDE_P2P -#define INCLUDE_ETH_PORT_2 -#define INCLUDE_CPU_MAPPING -#define INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - - -/****************************************/ -/* Processor Address Space */ -/****************************************/ -/* DDR SDRAM BAR and size registers */ - -/* Sdram's BAR'S */ -#define SCS_0_LOW_DECODE_ADDRESS 0x008 -#define SCS_0_HIGH_DECODE_ADDRESS 0x010 -#define SCS_1_LOW_DECODE_ADDRESS 0x208 -#define SCS_1_HIGH_DECODE_ADDRESS 0x210 -#define SCS_2_LOW_DECODE_ADDRESS 0x018 -#define SCS_2_HIGH_DECODE_ADDRESS 0x020 -#define SCS_3_LOW_DECODE_ADDRESS 0x218 -#define SCS_3_HIGH_DECODE_ADDRESS 0x220 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define CS_0_BASE_ADDR SCS_0_LOW_DECODE_ADDRESS -#define CS_0_SIZE SCS_0_HIGH_DECODE_ADDRESS -#define CS_1_BASE_ADDR SCS_1_LOW_DECODE_ADDRESS -#define CS_1_SIZE SCS_1_HIGH_DECODE_ADDRESS -#define CS_2_BASE_ADDR SCS_2_LOW_DECODE_ADDRESS -#define CS_2_SIZE SCS_2_HIGH_DECODE_ADDRESS -#define CS_3_BASE_ADDR SCS_3_LOW_DECODE_ADDRESS -#define CS_3_SIZE SCS_3_HIGH_DECODE_ADDRESS - -/* Devices BAR'S */ -#define CS_0_LOW_DECODE_ADDRESS 0x028 -#define CS_0_HIGH_DECODE_ADDRESS 0x030 -#define CS_1_LOW_DECODE_ADDRESS 0x228 -#define CS_1_HIGH_DECODE_ADDRESS 0x230 -#define CS_2_LOW_DECODE_ADDRESS 0x248 -#define CS_2_HIGH_DECODE_ADDRESS 0x250 -#define CS_3_LOW_DECODE_ADDRESS 0x038 -#define CS_3_HIGH_DECODE_ADDRESS 0x040 -#define BOOTCS_LOW_DECODE_ADDRESS 0x238 -#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -/* Devices BAR and size registers */ - -#define DEV_CS0_BASE_ADDR CS_0_LOW_DECODE_ADDRESS -#define DEV_CS0_SIZE CS_0_HIGH_DECODE_ADDRESS -#define DEV_CS1_BASE_ADDR CS_1_LOW_DECODE_ADDRESS -#define DEV_CS1_SIZE CS_1_HIGH_DECODE_ADDRESS -#define DEV_CS2_BASE_ADDR CS_2_LOW_DECODE_ADDRESS -#define DEV_CS2_SIZE CS_2_HIGH_DECODE_ADDRESS -#define DEV_CS3_BASE_ADDR CS_3_LOW_DECODE_ADDRESS -#define DEV_CS3_SIZE CS_3_HIGH_DECODE_ADDRESS -#define BOOTCS_BASE_ADDR BOOTCS_LOW_DECODE_ADDRESS -#define BOOTCS_SIZE BOOTCS_HIGH_DECODE_ADDRESS - -/* PCI 0 BAR and size registers old names of evb64260*/ - -#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 -#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 -#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 -#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 -#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 -#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 -#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 -#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 -#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 -#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define PCI_0_IO_BASE_ADDR 0x048 -#define PCI_0_IO_SIZE 0x050 -#define PCI_0_MEMORY0_BASE_ADDR 0x058 -#define PCI_0_MEMORY0_SIZE 0x060 -#define PCI_0_MEMORY1_BASE_ADDR 0x080 -#define PCI_0_MEMORY1_SIZE 0x088 -#define PCI_0_MEMORY2_BASE_ADDR 0x258 -#define PCI_0_MEMORY2_SIZE 0x260 -#define PCI_0_MEMORY3_BASE_ADDR 0x280 -#define PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers old names of evb64260*/ -#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 -#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 -#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 -#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 -#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 -#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 -#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 -#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 -#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 -#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define PCI_1_IO_BASE_ADDR 0x090 -#define PCI_1_IO_SIZE 0x098 -#define PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define PCI_1_MEMORY0_SIZE 0x0a8 -#define PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define PCI_1_MEMORY1_SIZE 0x0b8 -#define PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define PCI_1_MEMORY2_SIZE 0x2a8 -#define PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define PCI_1_MEMORY3_SIZE 0x2b8 - -/* internal registers space base address */ -#define INTERNAL_SPACE_DECODE 0x068 -#define INTERNAL_SPACE_BASE_ADDR INTERNAL_SPACE_DECODE - -/* SRAM base address */ -#define INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define BASE_ADDR_ENABLE 0x278 - - -#define CPU_0_LOW_DECODE_ADDRESS 0x290 -#define CPU_0_HIGH_DECODE_ADDRESS 0x298 -#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 -#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ -/*****************************************************************************************/ - /* PCI 0 */ -/* old fashion evb 64260 */ -#define PCI_0I_O_ADDRESS_REMAP 0x0f0 -#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 -#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 -#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 -#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 -#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 -#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 -#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 -#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 - -#define PCI_0_IO_ADDR_REMAP PCI_0I_O_ADDRESS_REMAP -#define PCI_0_MEMORY0_LOW_ADDR_REMAP PCI_0MEMORY0_ADDRESS_REMAP -#define PCI_0_MEMORY0_HIGH_ADDR_REMAP PCI_0MEMORY0_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY1_LOW_ADDR_REMAP PCI_0MEMORY1_ADDRESS_REMAP -#define PCI_0_MEMORY1_HIGH_ADDR_REMAP PCI_0MEMORY1_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY2_LOW_ADDR_REMAP PCI_0MEMORY2_ADDRESS_REMAP -#define PCI_0_MEMORY2_HIGH_ADDR_REMAP PCI_0MEMORY2_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY3_LOW_ADDR_REMAP PCI_0MEMORY3_ADDRESS_REMAP -#define PCI_0_MEMORY3_HIGH_ADDR_REMAP PCI_0MEMORY3_HIGH_ADDRESS_REMAP - - /* PCI 1 */ -/* old fashion evb 64260 */ -#define PCI_1I_O_ADDRESS_REMAP 0x108 -#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 -#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 -#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 -#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 -#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 -#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 -#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 -#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 - -#define PCI_1_IO_ADDR_REMAP PCI_1I_O_ADDRESS_REMAP -#define PCI_1_MEMORY0_LOW_ADDR_REMAP PCI_1MEMORY0_ADDRESS_REMAP -#define PCI_1_MEMORY0_HIGH_ADDR_REMAP PCI_1MEMORY0_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY1_LOW_ADDR_REMAP PCI_1MEMORY1_ADDRESS_REMAP -#define PCI_1_MEMORY1_HIGH_ADDR_REMAP PCI_1MEMORY1_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY2_LOW_ADDR_REMAP PCI_1MEMORY2_ADDRESS_REMAP -#define PCI_1_MEMORY2_HIGH_ADDR_REMAP PCI_1MEMORY2_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY3_LOW_ADDR_REMAP PCI_1MEMORY3_ADDRESS_REMAP -#define PCI_1_MEMORY3_HIGH_ADDR_REMAP PCI_1MEMORY3_HIGH_ADDRESS_REMAP - -/* old fashion evb 64260 */ -#define CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define CPU_GE_HEADERS_RETARGET_BASE 0x3d8 - -/* MV64360 and MV64460 no changes needed*/ -/*****************************************************************************************/ - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ -/* CPU MASTER CONTROL REGISTER */ -#define CPU_CONFIGURATION 0x000 -#define CPU_MASTER_CONTROL 0x160 - -#define CPU_CONFIG 0x000 -#define CPU_MODE 0x120 -#define CPU_MASTER_CONTROL 0x160 -/* new in MV64360 and MV64460 */ -#define CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define SMP_WHO_AM_I 0x200 -#define SMP_CPU0_DOORBELL 0x214 -#define SMP_CPU0_DOORBELL_CLEAR 0x21C -#define SMP_CPU1_DOORBELL 0x224 -#define SMP_CPU1_DOORBELL_CLEAR 0x22C -#define SMP_CPU0_DOORBELL_MASK 0x234 -#define SMP_CPU1_DOORBELL_MASK 0x23C -#define SMP_SEMAPHOR0 0x244 -#define SMP_SEMAPHOR1 0x24c -#define SMP_SEMAPHOR2 0x254 -#define SMP_SEMAPHOR3 0x25c -#define SMP_SEMAPHOR4 0x264 -#define SMP_SEMAPHOR5 0x26c -#define SMP_SEMAPHOR6 0x274 -#define SMP_SEMAPHOR7 0x27c - - -/****************************************/ -/* CPU Sync Barrier */ -/****************************************/ -#define CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define CPU_LOW_PROTECT_ADDRESS_0 0x180 -#define CPU_HIGH_PROTECT_ADDRESS_0 0x188 -#define CPU_LOW_PROTECT_ADDRESS_1 0x190 -#define CPU_HIGH_PROTECT_ADDRESS_1 0x198 -#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0 -#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8 -#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0 -#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8 -/*#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0 -#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8 -#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0 -#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8 -#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0 -#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8 -#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0 -#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8 -*/ - -#define CPU_PROTECT_WINDOW_0_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */ -#define CPU_PROTECT_WINDOW_0_SIZE CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */ -#define CPU_PROTECT_WINDOW_1_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */ -#define CPU_PROTECT_WINDOW_1_SIZE CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */ -#define CPU_PROTECT_WINDOW_2_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */ -#define CPU_PROTECT_WINDOW_2_SIZE CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */ -#define CPU_PROTECT_WINDOW_3_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */ -#define CPU_PROTECT_WINDOW_3_SIZE CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */ - - -/****************************************/ -/* Snoop Control */ -/****************************************/ - -/*#define SNOOP_BASE_ADDRESS_0 0x380 -#define SNOOP_TOP_ADDRESS_0 0x388 -#define SNOOP_BASE_ADDRESS_1 0x390 -#define SNOOP_TOP_ADDRESS_1 0x398 -#define SNOOP_BASE_ADDRESS_2 0x3a0 -#define SNOOP_TOP_ADDRESS_2 0x3a8 -#define SNOOP_BASE_ADDRESS_3 0x3b0 -#define SNOOP_TOP_ADDRESS_3 0x3b8 -*/ - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define SRAM_CONFIG 0x380 -#define SRAM_TEST_MODE 0x3F4 -#define SRAM_ERROR_CAUSE 0x388 -#define SRAM_ERROR_ADDR 0x390 -#define SRAM_ERROR_ADDR_HIGH 0x3F8 -#define SRAM_ERROR_DATA_LOW 0x398 -#define SRAM_ERROR_DATA_HIGH 0x3a0 -#define SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define CPU_ERROR_ADDRESS_LOW 0x070 -#define CPU_ERROR_ADDRESS_HIGH 0x078 -#define CPU_ERROR_DATA_LOW 0x128 -#define CPU_ERROR_DATA_HIGH 0x130 -#define CPU_ERROR_PARITY 0x138 -#define CPU_ERROR_CAUSE 0x140 -#define CPU_ERROR_MASK 0x148 - -#define CPU_ERROR_ADDR_LOW CPU_ERROR_ADDRESS_LOW /* 0x0701 */ -#define CPU_ERROR_ADDR_HIGH CPU_ERROR_ADDRESS_HIGH /* 0x0781 */ - -/****************************************/ -/* Pslave Debug */ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define X_0_ADDRESS 0x360 -#define X_0_COMMAND_ID 0x368 -#define X_1_ADDRESS 0x370 -#define X_1_COMMAND_ID 0x378 - /*#define WRITE_DATA_LOW 0x3c01 */ - /*#define WRITE_DATA_HIGH 0x3c81 */ - /*#define WRITE_BYTE_ENABLE 0x3e01 */ - /*#define READ_DATA_LOW 0x3d01 */ - /*#define READ_DATA_HIGH 0x3d81 */ - /*#define READ_ID 0x3e81 */ - -#define PUNIT_SLAVE_DEBUG_LOW X_0_ADDRESS /* 0x3601 */ -#define PUNIT_SLAVE_DEBUG_HIGH X_0_COMMAND_ID /* 0x3681 */ -#define PUNIT_MASTER_DEBUG_LOW X_1_ADDRESS /* 0x3701 */ -#define PUNIT_MASTER_DEBUG_HIGH X_1_COMMAND_ID /* 0x3781 */ -#define PUNIT_MMASK 0x3e4 - - -/****************************************/ -/* SDRAM and Device Address Space */ -/****************************************/ - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ -#define SDRAM_CONFIG 0x1400 /* MV64260 0x448 some changes*/ -#define D_UNIT_CONTROL_LOW 0x1404 /* NEW in MV64360 and MV64460 */ -#define D_UNIT_CONTROL_HIGH 0x1424 /* NEW in MV64360 and MV64460 */ -#define SDRAM_TIMING_CONTROL_LOW 0x1408 /* MV64260 0x4b4 new SDRAM TIMING REGISTER */ -#define SDRAM_TIMING_CONTROL_HIGH 0x140c /* MV64260 0x4b4 new SDRAM TIMING REGISTER */ -#define SDRAM_ADDR_CONTROL 0x1410 /* MV64260 0x47c some changes*/ -#define SDRAM_OPEN_PAGES_CONTROL 0x1414 /* NEW in MV64360 and MV64460 */ -#define SDRAM_OPERATION 0x1418 /* MV64260 0x474 some changes*/ -#define SDRAM_MODE 0x141c /* NEW in MV64360 and MV64460 */ -#define EXTENDED_DRAM_MODE 0x1420 /* NEW in MV64360 and MV64460 */ -#define SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 /* MV64260 0x4a8 NO changes*/ -#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 /* MV64260 0x4ac NO changes*/ -#define SDRAM_CROSS_BAR_TIMEOUT 0x1438 /* MV64260 0x4b0 NO changes*/ -#define SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 /* what is this ??? */ -#define SDRAM_DATA_PADS_CALIBRATION 0x14c4 /* what is this ??? */ -/****************************************/ -/* SDRAM Configuration MV64260 */ -/****************************************/ - /*#define SDRAM_CONFIGURATION 0x4481 */ - /*#define SDRAM_OPERATION_MODE 0x4741 */ - /*#define SDRAM_ADDRESS_DECODE 0x47c1 */ - /*#define SDRAM_UMA_CONTROL 0x4a4 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a81 */ - /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */ - /*#define SDRAM_CROSS_BAR_TIMEOUT 0x4b01 */ - /*#define SDRAM_TIMING 0x4b41 */ - - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ -#define SDRAM_ERROR_DATA_LOW 0x1444 /* MV64260 0x484 NO changes*/ -#define SDRAM_ERROR_DATA_HIGH 0x1440 /* MV64260 0x480 NO changes*/ -#define SDRAM_ERROR_ADDR 0x1450 /* MV64260 0x490 NO changes*/ -#define SDRAM_RECEIVED_ECC 0x1448 /* MV64260 0x488 NO changes*/ -#define SDRAM_CALCULATED_ECC 0x144c /* MV64260 0x48c NO changes*/ -#define SDRAM_ECC_CONTROL 0x1454 /* MV64260 0x494 NO changes*/ -#define SDRAM_ECC_ERROR_COUNTER 0x1458 /* MV64260 0x498 NO changes*/ -#define SDRAM_MMASK 0x1B40 /* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/ -/****************************************/ -/* SDRAM Error Report MV64260 */ -/****************************************/ - /*#define SDRAM_ERROR_DATA_LOW 0x4841 */ - /*#define SDRAM_ERROR_DATA_HIGH 0x4801 */ - /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x4901 */ - /*#define SDRAM_RECEIVED_ECC 0x4881 */ - /*#define SDRAM_CALCULATED_ECC 0x48c1 */ - /*#define SDRAM_ECC_CONTROL 0x4941 */ - /*#define SDRAM_ECC_ERROR_COUNTER 0x4981 */ - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ -#define DFCDL_CONFIG0 0x1480 -#define DFCDL_CONFIG1 0x1484 -#define DLL_WRITE 0x1488 -#define DLL_READ 0x148c -#define SRAM_ADDR 0x1490 -#define SRAM_DATA0 0x1494 -#define SRAM_DATA1 0x1498 -#define SRAM_DATA2 0x149c -#define DFCL_PROBE 0x14a0 - - -/****************************************/ -/* SDRAM Parameters only in MV64260 */ -/****************************************/ - - /*#define SDRAM_BANK0PARAMETERS 0x44C eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK1PARAMETERS 0x450 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK2PARAMETERS 0x454 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK3PARAMETERS 0x458 eliminated in MV64360 and MV64460 */ - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define DUNIT_DEBUG_LOW 0x1460 -#define DUNIT_DEBUG_HIGH 0x1464 -#define DUNIT_MMASK 0x1b40 - -/****************************************/ -/* SDunit Debug (for internal use) */ -/****************************************/ - -#define X0_ADDRESS 0x500 -#define X0_COMMAND_AND_ID 0x504 -#define X0_WRITE_DATA_LOW 0x508 -#define X0_WRITE_DATA_HIGH 0x50c -#define X0_WRITE_BYTE_ENABLE 0x518 -#define X0_READ_DATA_LOW 0x510 -#define X0_READ_DATA_HIGH 0x514 -#define X0_READ_ID 0x51c -#define X1_ADDRESS 0x520 -#define X1_COMMAND_AND_ID 0x524 -#define X1_WRITE_DATA_LOW 0x528 -#define X1_WRITE_DATA_HIGH 0x52c -#define X1_WRITE_BYTE_ENABLE 0x538 -#define X1_READ_DATA_LOW 0x530 -#define X1_READ_DATA_HIGH 0x534 -#define X1_READ_ID 0x53c -#define X0_SNOOP_ADDRESS 0x540 -#define X0_SNOOP_COMMAND 0x544 -#define X1_SNOOP_ADDRESS 0x548 -#define X1_SNOOP_COMMAND 0x54c - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define DEVICE_BANK0PARAMETERS 0x45c -#define DEVICE_BANK1PARAMETERS 0x460 -#define DEVICE_BANK2PARAMETERS 0x464 -#define DEVICE_BANK3PARAMETERS 0x468 -#define DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define DEVICE_CONTROL 0x4c0 -#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define DEVICE_BANK0_PARAMETERS DEVICE_BANK0PARAMETERS /* 0x45c1 */ -#define DEVICE_BANK1_PARAMETERS DEVICE_BANK1PARAMETERS /* 0x4601 */ -#define DEVICE_BANK2_PARAMETERS DEVICE_BANK2PARAMETERS /* 0x4641 */ -#define DEVICE_BANK3_PARAMETERS DEVICE_BANK3PARAMETERS /* 0x4681 */ -/*#define DEVICE_BOOT_BANK_PARAMETERS 0x46c1 */ -#define DEVICE_INTERFACE_CONTROL DEVICE_CONTROL /* 0x4c01 */ -#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW DEVICE_CROSS_BAR_CONTROL_LOW /* 0x4c81 */ -#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH DEVICE_CROSS_BAR_CONTROL_HIGH /* 0x4cc1 */ -#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT DEVICE_CROSS_BAR_TIMEOUT /* 0x4c41 */ - - -/****************************************/ -/* Device Interrupt */ -/****************************************/ - -#define DEVICE_INTERRUPT_CAUSE 0x4d0 -#define DEVICE_INTERRUPT_MASK 0x4d4 -#define DEVICE_ERROR_ADDRESS 0x4d8 - /*#define DEVICE_INTERRUPT_CAUSE 0x4d01 */ - /*#define DEVICE_INTERRUPT_MASK 0x4d41 */ -#define DEVICE_ERROR_ADDR DEVICE_ERROR_ADDRESS /*0x4d81 */ -#define DEVICE_ERROR_DATA 0x4dc -#define DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define DEVICE_DEBUG_LOW 0x4e4 -#define DEVICE_DEBUG_HIGH 0x4e8 -#define RUNIT_MMASK 0x4f0 - -/****************************************/ -/* DMA Record */ -/****************************************/ - - /*#define CHANNEL4_DMA_BYTE_COUNT 0x9001 */ - /*#define CHANNEL5_DMA_BYTE_COUNT 0x9041 */ - /*#define CHANNEL6_DMA_BYTE_COUNT 0x9081 */ - /*#define CHANNEL7_DMA_BYTE_COUNT 0x90C1 */ - /*#define CHANNEL4_DMA_SOURCE_ADDRESS 0x9101 */ - /*#define CHANNEL5_DMA_SOURCE_ADDRESS 0x9141 */ - /*#define CHANNEL6_DMA_SOURCE_ADDRESS 0x9181 */ - /*#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C1 */ - /*#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x9201 */ - /*#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x9241 */ - /*#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x9281 */ - /*#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C1 */ - /*#define CHANNEL4NEXT_RECORD_POINTER 0x9301 */ - /*#define CHANNEL5NEXT_RECORD_POINTER 0x9341 */ - /*#define CHANNEL6NEXT_RECORD_POINTER 0x9381 */ - /*#define CHANNEL7NEXT_RECORD_POINTER 0x93C1 */ - /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x9701 */ - /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x9741 */ - /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x9781 */ - /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C1 */ - /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8901 */ - /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8941 */ - /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8981 */ - /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c1 */ - /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9901 */ - /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9941 */ - /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9981 */ - /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c1 */ - /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a01 */ - /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a41 */ - /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a81 */ - /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac1 */ - /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a01 */ - /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a41 */ - /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a81 */ - /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac1 */ - /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b01 */ - /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b41 */ - /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b81 */ - /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc1 */ - /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b01 */ - /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b41 */ - /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b81 */ - /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc1 */ - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define CHANNEL0CONTROL 0x840 -#define CHANNEL0CONTROL_HIGH 0x880 -#define CHANNEL1CONTROL 0x844 -#define CHANNEL1CONTROL_HIGH 0x884 -#define CHANNEL2CONTROL 0x848 -#define CHANNEL2CONTROL_HIGH 0x888 -#define CHANNEL3CONTROL 0x84C -#define CHANNEL3CONTROL_HIGH 0x88C - -#define DMA_CHANNEL0_CONTROL CHANNEL0CONTROL /*0x8401 */ -#define DMA_CHANNEL0_CONTROL_HIGH CHANNEL0CONTROL_HIGH /*0x8801 */ -#define DMA_CHANNEL1_CONTROL CHANNEL1CONTROL /* 0x8441 */ -#define DMA_CHANNEL1_CONTROL_HIGH CHANNEL1CONTROL_HIGH /*0x8841 */ -#define DMA_CHANNEL2_CONTROL CHANNEL2CONTROL /*0x8481 */ -#define DMA_CHANNEL2_CONTROL_HIGH CHANNEL2CONTROL_HIGH /*0x8881 */ -#define DMA_CHANNEL3_CONTROL CHANNEL3CONTROL /*0x84C1 */ -#define DMA_CHANNEL3_CONTROL_HIGH CHANNEL3CONTROL_HIGH /*0x88C1 */ - - /*#define CHANNEL4CONTROL 0x9401 */ - /*#define CHANNEL4CONTROL_HIGH 0x9801 */ - /*#define CHANNEL5CONTROL 0x9441 */ - /*#define CHANNEL5CONTROL_HIGH 0x9841 */ - /*#define CHANNEL6CONTROL 0x9481 */ - /*#define CHANNEL6CONTROL_HIGH 0x9881 */ - /*#define CHANNEL7CONTROL 0x94C1 */ - /*#define CHANNEL7CONTROL_HIGH 0x98C1 */ - - -/****************************************/ -/* DMA Arbiter */ -/****************************************/ - - /*#define ARBITER_CONTROL_0_3 0x8601 */ -#define ARBITER_CONTROL_4_7 0x960 -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define DMA_CHANNEL0_BYTE_COUNT CHANNEL0_DMA_BYTE_COUNT /*0x8001 */ -#define DMA_CHANNEL1_BYTE_COUNT CHANNEL1_DMA_BYTE_COUNT /*0x8041 */ -#define DMA_CHANNEL2_BYTE_COUNT CHANNEL2_DMA_BYTE_COUNT /*0x8081 */ -#define DMA_CHANNEL3_BYTE_COUNT CHANNEL3_DMA_BYTE_COUNT /*0x80C1 */ -#define DMA_CHANNEL0_SOURCE_ADDR CHANNEL0_DMA_SOURCE_ADDRESS /*0x8101 */ -#define DMA_CHANNEL1_SOURCE_ADDR CHANNEL1_DMA_SOURCE_ADDRESS /*0x8141 */ -#define DMA_CHANNEL2_SOURCE_ADDR CHANNEL2_DMA_SOURCE_ADDRESS /*0x8181 */ -#define DMA_CHANNEL3_SOURCE_ADDR CHANNEL3_DMA_SOURCE_ADDRESS /*0x81c1 */ -#define DMA_CHANNEL0_DESTINATION_ADDR CHANNEL0_DMA_DESTINATION_ADDRESS /*0x8201 */ -#define DMA_CHANNEL1_DESTINATION_ADDR CHANNEL1_DMA_DESTINATION_ADDRESS /*0x8241 */ -#define DMA_CHANNEL2_DESTINATION_ADDR CHANNEL2_DMA_DESTINATION_ADDRESS /*0x8281 */ -#define DMA_CHANNEL3_DESTINATION_ADDR CHANNEL3_DMA_DESTINATION_ADDRESS /*0x82C1 */ -#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER CHANNEL0NEXT_RECORD_POINTER /*0x8301 */ -#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER CHANNEL1NEXT_RECORD_POINTER /*0x8341 */ -#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER CHANNEL2NEXT_RECORD_POINTER /*0x8381 */ -#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER CHANNEL3NEXT_RECORD_POINTER /*0x83C1 */ -#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER CHANNEL0CURRENT_DESCRIPTOR_POINTER /*0x8701 */ -#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER CHANNEL1CURRENT_DESCRIPTOR_POINTER /*0x8741 */ -#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER CHANNEL2CURRENT_DESCRIPTOR_POINTER /*0x8781 */ -#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER CHANNEL3CURRENT_DESCRIPTOR_POINTER /*0x87C1 */ - -#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C -#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 -#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 -#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 -#define CHANNEL0NEXT_RECORD_POINTER 0x830 -#define CHANNEL1NEXT_RECORD_POINTER 0x834 -#define CHANNEL2NEXT_RECORD_POINTER 0x838 -#define CHANNEL3NEXT_RECORD_POINTER 0x83C -#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 -#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 -#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 -#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C -#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 -#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 -#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 -#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C -#define CHANNEL0_DMA_BYTE_COUNT 0x800 -#define CHANNEL1_DMA_BYTE_COUNT 0x804 -#define CHANNEL2_DMA_BYTE_COUNT 0x808 -#define CHANNEL3_DMA_BYTE_COUNT 0x80C - - /* IDMA Address Decoding Base Address Registers */ - -#define DMA_BASE_ADDR_REG0 0xa00 -#define DMA_BASE_ADDR_REG1 0xa08 -#define DMA_BASE_ADDR_REG2 0xa10 -#define DMA_BASE_ADDR_REG3 0xa18 -#define DMA_BASE_ADDR_REG4 0xa20 -#define DMA_BASE_ADDR_REG5 0xa28 -#define DMA_BASE_ADDR_REG6 0xa30 -#define DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define DMA_SIZE_REG0 0xa04 -#define DMA_SIZE_REG1 0xa0c -#define DMA_SIZE_REG2 0xa14 -#define DMA_SIZE_REG3 0xa1c -#define DMA_SIZE_REG4 0xa24 -#define DMA_SIZE_REG5 0xa2c -#define DMA_SIZE_REG6 0xa34 -#define DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define DMA_ARBITER_CONTROL 0x860 -#define DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - - /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e01 */ - /*#define CPU_IDMA_HEADERS_RETARGET_BASE 0x3e81 */ - -#define DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define DMA_HEADERS_RETARGET_BASE 0xa88 - -/****************************************/ -/* DMA Interrupt */ -/****************************************/ - -#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 -#define CHANELS0_3_INTERRUPT_MASK 0x8c4 -#define CHANELS0_3_ERROR_ADDRESS 0x8c8 -#define CHANELS0_3_ERROR_SELECT 0x8cc - /*#define CHANELS4_7_INTERRUPT_CAUSE 0x9c01 */ - /*#define CHANELS4_7_INTERRUPT_MASK 0x9c41 */ - /*#define CHANELS4_7_ERROR_ADDRESS 0x9c81 */ - /*#define CHANELS4_7_ERROR_SELECT 0x9cc1 */ - -#define DMA_INTERRUPT_CAUSE_REG CHANELS0_3_INTERRUPT_CAUSE /*0x8c01 */ -#define DMA_INTERRUPT_CAUSE_MASK CHANELS0_3_INTERRUPT_MASK /*0x8c41 */ -#define DMA_ERROR_ADDR CHANELS0_3_ERROR_ADDRESS /*0x8c81 */ -#define DMA_ERROR_SELECT CHANELS0_3_ERROR_SELECT /*0x8cc1 */ - - -/****************************************/ -/* DMA Debug (for internal use) */ -/****************************************/ - -#define DMA_X0_ADDRESS 0x8e0 -#define DMA_X0_COMMAND_AND_ID 0x8e4 - /*#define DMA_X0_WRITE_DATA_LOW 0x8e81 */ - /*#define DMA_X0_WRITE_DATA_HIGH 0x8ec1 */ - /*#define DMA_X0_WRITE_BYTE_ENABLE 0x8f81 */ - /*#define DMA_X0_READ_DATA_LOW 0x8f01 */ - /*#define DMA_X0_READ_DATA_HIGH 0x8f41 */ - /*#define DMA_X0_READ_ID 0x8fc1 */ - /*#define DMA_X1_ADDRESS 0x9e01 */ - /*#define DMA_X1_COMMAND_AND_ID 0x9e41 */ - /*#define DMA_X1_WRITE_DATA_LOW 0x9e81 */ - /*#define DMA_X1_WRITE_DATA_HIGH 0x9ec1 */ - /*#define DMA_X1_WRITE_BYTE_ENABLE 0x9f81 */ - /*#define DMA_X1_READ_DATA_LOW 0x9f01 */ - /*#define DMA_X1_READ_DATA_HIGH 0x9f41 */ - /*#define DMA_X1_READ_ID 0x9fc1 */ - - /* IDMA Debug Register ( for internal use ) */ - -#define DMA_DEBUG_LOW DMA_X0_ADDRESS /* 0x8e01 */ -#define DMA_DEBUG_HIGH DMA_X0_COMMAND_AND_ID /*0x8e41 */ -#define DMA_SPARE 0xA8C - - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define TIMER_COUNTER0 0x850 -#define TIMER_COUNTER1 0x854 -#define TIMER_COUNTER2 0x858 -#define TIMER_COUNTER3 0x85C -#define TIMER_COUNTER_0_3_CONTROL 0x864 -#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - /*#define TIMER_COUNTER4 0x9501 */ - /*#define TIMER_COUNTER5 0x9541 */ - /*#define TIMER_COUNTER6 0x9581 */ - /*#define TIMER_COUNTER7 0x95C1 */ - /*#define TIMER_COUNTER_4_7_CONTROL 0x9641 */ - /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x9681 */ - /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c1 */ - -/****************************************/ -/* PCI Slave Address Decoding */ -/****************************************/ -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ -#define PCI_0_CS_0_BANK_SIZE PCI_0SCS_0_BANK_SIZE /*0xc081 */ -#define PCI_1_CS_0_BANK_SIZE PCI_1SCS_0_BANK_SIZE /* 0xc881 */ -#define PCI_0_CS_1_BANK_SIZE PCI_0SCS_1_BANK_SIZE /*0xd081 */ -#define PCI_1_CS_1_BANK_SIZE PCI_1SCS_1_BANK_SIZE /* 0xd881 */ -#define PCI_0_CS_2_BANK_SIZE PCI_0SCS_2_BANK_SIZE /*0xc0c1 */ -#define PCI_1_CS_2_BANK_SIZE PCI_1SCS_2_BANK_SIZE /*0xc8c1 */ -#define PCI_0_CS_3_BANK_SIZE PCI_0SCS_3_BANK_SIZE /*0xd0c1 */ -#define PCI_1_CS_3_BANK_SIZE PCI_1SCS_3_BANK_SIZE /*0xd8c1 */ -#define PCI_0_DEVCS_0_BANK_SIZE PCI_0CS_0_BANK_SIZE /*0xc101 */ -#define PCI_1_DEVCS_0_BANK_SIZE PCI_1CS_0_BANK_SIZE /*0xc901 */ -#define PCI_0_DEVCS_1_BANK_SIZE PCI_0CS_1_BANK_SIZE /*0xd101 */ -#define PCI_1_DEVCS_1_BANK_SIZE PCI_1CS_1_BANK_SIZE /* 0xd901 */ -#define PCI_0_DEVCS_2_BANK_SIZE PCI_0CS_2_BANK_SIZE /* 0xd181 */ -#define PCI_1_DEVCS_2_BANK_SIZE PCI_1CS_2_BANK_SIZE /*0xd981 */ -#define PCI_0_DEVCS_3_BANK_SIZE PCI_0CS_3_BANK_SIZE /* 0xc141 */ -#define PCI_1_DEVCS_3_BANK_SIZE PCI_1CS_3_BANK_SIZE /*0xc941 */ -#define PCI_0_DEVCS_BOOT_BANK_SIZE PCI_0CS_BOOT_BANK_SIZE /*0xd141 */ -#define PCI_1_DEVCS_BOOT_BANK_SIZE PCI_1CS_BOOT_BANK_SIZE /* 0xd941 */ -#define PCI_0_P2P_MEM0_BAR_SIZE PCI_0P2P_MEM0_BAR_SIZE /*0xd1c1 */ -#define PCI_1_P2P_MEM0_BAR_SIZE PCI_1P2P_MEM0_BAR_SIZE /*0xd9c1 */ -#define PCI_0_P2P_MEM1_BAR_SIZE PCI_0P2P_MEM1_BAR_SIZE /*0xd201 */ -#define PCI_1_P2P_MEM1_BAR_SIZE PCI_1P2P_MEM1_BAR_SIZE /*0xda01 */ -#define PCI_0_P2P_I_O_BAR_SIZE PCI_0P2P_I_O_BAR_SIZE /*0xd241 */ -#define PCI_1_P2P_I_O_BAR_SIZE PCI_1P2P_I_O_BAR_SIZE /*0xda41 */ -#define PCI_0_CPU_BAR_SIZE PCI_0CPU_BAR_SIZE /*0xd281 */ -#define PCI_1_CPU_BAR_SIZE PCI_1CPU_BAR_SIZE /*0xda81 */ -#define PCI_0_INTERNAL_SRAM_BAR_SIZE PCI_0DAC_SCS_0_BANK_SIZE /*0xe001 */ -#define PCI_1_INTERNAL_SRAM_BAR_SIZE PCI_1DAC_SCS_0_BANK_SIZE /*0xe801 */ -#define PCI_0_EXPANSION_ROM_BAR_SIZE PCI_0EXPANSION_ROM_BAR_SIZE /*0xd2c1 */ -#define PCI_1_EXPANSION_ROM_BAR_SIZE PCI_1EXPANSION_ROM_BAR_SIZE /*0xd9c1 */ -#define PCI_0_BASE_ADDR_REG_ENABLE PCI_0BASE_ADDRESS_REGISTERS_ENABLE /*0xc3c1 */ -#define PCI_1_BASE_ADDR_REG_ENABLE PCI_1BASE_ADDRESS_REGISTERS_ENABLE /*0xcbc1 */ -#define PCI_0_CS_0_BASE_ADDR_REMAP PCI_0SCS_0_BASE_ADDRESS_REMAP /*0xc481 */ -#define PCI_1_CS_0_BASE_ADDR_REMAP PCI_1SCS_0_BASE_ADDRESS_REMAP /*0xcc81 */ -#define PCI_0_CS_1_BASE_ADDR_REMAP PCI_0SCS_1_BASE_ADDRESS_REMAP /*0xd481 */ -#define PCI_1_CS_1_BASE_ADDR_REMAP PCI_1SCS_1_BASE_ADDRESS_REMAP /*0xdc81 */ -#define PCI_0_CS_2_BASE_ADDR_REMAP PCI_0SCS_2_BASE_ADDRESS_REMAP /*0xc4c1 */ -#define PCI_1_CS_2_BASE_ADDR_REMAP PCI_1SCS_2_BASE_ADDRESS_REMAP /*0xccc1 */ -#define PCI_0_CS_3_BASE_ADDR_REMAP PCI_0SCS_3_BASE_ADDRESS_REMAP /*0xd4c1 */ -#define PCI_1_CS_3_BASE_ADDR_REMAP PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */ -#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP -#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP -#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP -#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP -#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP -#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP -#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP -#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP -#define PCI_0_DEVCS_0_BASE_ADDR_REMAP PCI_0CS_0_BASE_ADDRESS_REMAP /*0xc501 */ -#define PCI_1_DEVCS_0_BASE_ADDR_REMAP PCI_1CS_0_BASE_ADDRESS_REMAP /*0xcd01 */ -#define PCI_0_DEVCS_1_BASE_ADDR_REMAP PCI_0CS_1_BASE_ADDRESS_REMAP /*0xd501 */ -#define PCI_1_DEVCS_1_BASE_ADDR_REMAP PCI_1CS_1_BASE_ADDRESS_REMAP /*0xdd01 */ -#define PCI_0_DEVCS_2_BASE_ADDR_REMAP PCI_0CS_2_BASE_ADDRESS_REMAP /*0xd581 */ -#define PCI_1_DEVCS_2_BASE_ADDR_REMAP PCI_1CS_2_BASE_ADDRESS_REMAP /*0xdd81 */ -#define PCI_0_DEVCS_3_BASE_ADDR_REMAP PCI_0CS_3_BASE_ADDRESS_REMAP /*0xc541 */ -#define PCI_1_DEVCS_3_BASE_ADDR_REMAP PCI_1CS_3_BASE_ADDRESS_REMAP /*0xcd41 */ -#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP /*0xd541 */ -#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP /*0xdd41 */ -#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xd5c1 */ -#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xddc1 */ -#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xd601 */ -#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xde01 */ -#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xd641 */ -#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xde41 */ -#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xd681 */ -#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xde81 */ -#define PCI_0_P2P_I_O_BASE_ADDR_REMAP PCI_0P2P_I_O_BASE_ADDRESS_REMAP /*0xd6c1 */ -#define PCI_1_P2P_I_O_BASE_ADDR_REMAP PCI_1P2P_I_O_BASE_ADDRESS_REMAP /*0xdec 1 */ -#define PCI_0_CPU_BASE_ADDR_REMAP_LOW PCI_0CPU_BASE_ADDRESS_REMAP /*0xd701 */ -#define PCI_1_CPU_BASE_ADDR_REMAP_LOW PCI_1CPU_BASE_ADDRESS_REMAP /*0xdf01 */ -#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP /*0xf001 */ -#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xf381 */ -#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xfb81 */ -#define PCI_0_ADDR_DECODE_CONTROL PCI_0ADDRESS_DECODE_CONTROL /*0xd3c1 */ -#define PCI_1_ADDR_DECODE_CONTROL PCI_1ADDRESS_DECODE_CONTROL /*0xdbc1 */ -#define PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -#define PCI_0SCS_0_BANK_SIZE 0xc08 -#define PCI_1SCS_0_BANK_SIZE 0xc88 -#define PCI_0SCS_1_BANK_SIZE 0xd08 -#define PCI_1SCS_1_BANK_SIZE 0xd88 -#define PCI_0SCS_2_BANK_SIZE 0xc0c -#define PCI_1SCS_2_BANK_SIZE 0xc8c -#define PCI_0SCS_3_BANK_SIZE 0xd0c -#define PCI_1SCS_3_BANK_SIZE 0xd8c -#define PCI_0CS_0_BANK_SIZE 0xc10 -#define PCI_1CS_0_BANK_SIZE 0xc90 -#define PCI_0CS_1_BANK_SIZE 0xd10 -#define PCI_1CS_1_BANK_SIZE 0xd90 -#define PCI_0CS_2_BANK_SIZE 0xd18 -#define PCI_1CS_2_BANK_SIZE 0xd98 -#define PCI_0CS_3_BANK_SIZE 0xc14 -#define PCI_1CS_3_BANK_SIZE 0xc94 -#define PCI_0CS_BOOT_BANK_SIZE 0xd14 -#define PCI_1CS_BOOT_BANK_SIZE 0xd94 -#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c -#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c -#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 -#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 -#define PCI_0P2P_I_O_BAR_SIZE 0xd24 -#define PCI_1P2P_I_O_BAR_SIZE 0xda4 -#define PCI_0CPU_BAR_SIZE 0xd28 -#define PCI_1CPU_BAR_SIZE 0xda8 -#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 -#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 -#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 -#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 -#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 -#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 -#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c -#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c -#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 -#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 -#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 -#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 -#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 -#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 -#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c -#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c -#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 -#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 - -#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 -#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 -#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 -#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 -#define PCI_0DAC_CPU_BAR_SIZE 0xe2c -#define PCI_1DAC_CPU_BAR_SIZE 0xeac -#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c -#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac -#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c -#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc -#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 -#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 -#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 -#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 -#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c -#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc -#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c -#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc -#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 -#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 -#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 -#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 -#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 -#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 -#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 -#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 -#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 -#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 -#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c -#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec -#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 -#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 -#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 -#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 -#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 -#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 -#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 -#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 -#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c -#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c -#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 -#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 -#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 -#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 -#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 -#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 -#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c -#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c -#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 -#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 -#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 -#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 -#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 -#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 -#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c -#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc - -/****************************************/ -/* PCI Control */ -/****************************************/ - -#define PCI_0COMMAND 0xc00 -#define PCI_1COMMAND 0xc80 -#define PCI_0MODE 0xd00 -#define PCI_1MODE 0xd80 -#define PCI_0TIMEOUT_RETRY 0xc04 -#define PCI_1TIMEOUT_RETRY 0xc84 -#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 -#define MSI_0TRIGGER_TIMER 0xc38 -#define MSI_1TRIGGER_TIMER 0xcb8 -#define PCI_0ARBITER_CONTROL 0x1d00 -#define PCI_1ARBITER_CONTROL 0x1d80 -/* changing untill here */ -#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c -#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 -#define PCI_0P2P_CONFIGURATION 0x1d14 -#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 -#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 -#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 -#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 -#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 -#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 -#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60 -#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 -#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 -#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70 -#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 -#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 -#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c -#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 -#define PCI_1P2P_CONFIGURATION 0x1d94 -#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 -#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 -#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 -#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 -#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 -#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 -#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0 -#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 -#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 -#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0 -#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 -#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 - -/****************************************/ -/* PCI Snoop Control */ -/****************************************/ - -#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 -#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 -#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 -#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 -#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 -#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 -#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 -#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 -#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 -#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 -#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 -#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 -#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 -#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 -#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 -#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 -#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 -#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 -#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 -#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 -#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 -#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 -#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 -#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 - -/****************************************/ -/* PCI Configuration Address */ -/****************************************/ - -#define PCI_0CONFIGURATION_ADDRESS 0xcf8 -#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc -#define PCI_1CONFIGURATION_ADDRESS 0xc78 -#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c -#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 -#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 - -/****************************************/ -/* PCI Error Report */ -/****************************************/ - -#define PCI_0SERR_MASK 0xc28 -#define PCI_0ERROR_ADDRESS_LOW 0x1d40 -#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 -#define PCI_0ERROR_DATA_LOW 0x1d48 -#define PCI_0ERROR_DATA_HIGH 0x1d4c -#define PCI_0ERROR_COMMAND 0x1d50 -#define PCI_0ERROR_CAUSE 0x1d58 -#define PCI_0ERROR_MASK 0x1d5c -#define PCI_1SERR_MASK 0xca8 -#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 -#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 -#define PCI_1ERROR_DATA_LOW 0x1dc8 -#define PCI_1ERROR_DATA_HIGH 0x1dcc -#define PCI_1ERROR_COMMAND 0x1dd0 -#define PCI_1ERROR_CAUSE 0x1dd8 -#define PCI_1ERROR_MASK 0x1ddc - - -/****************************************/ -/* Lslave Debug (for internal use) */ -/****************************************/ - -#define L_SLAVE_X0_ADDRESS 0x1d20 -#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 -#define L_SLAVE_X1_ADDRESS 0x1d28 -#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c -#define L_SLAVE_WRITE_DATA_LOW 0x1d30 -#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 -#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 -#define L_SLAVE_READ_DATA_LOW 0x1d38 -#define L_SLAVE_READ_DATA_HIGH 0x1d3c -#define L_SLAVE_READ_ID 0x1d64 - -/****************************************/ -/* PCI Configuration Function 0 */ -/****************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/****************************************/ -/* PCI Configuration Function 1 */ -/****************************************/ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/****************************************/ -/* PCI Configuration Function 2 */ -/****************************************/ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 - /*#define PCI_P2P_MEM1_BASE_ADDRESS 0x2141 */ -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 - /*#define PCI_CPU_BASE_ADDRESS 0x21c1 */ - -/****************************************/ -/* PCI Configuration Function 4 */ -/****************************************/ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/****************************************/ -/* PCI Configuration Function 5 */ -/****************************************/ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/****************************************/ -/* PCI Configuration Function 6 */ -/****************************************/ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/****************************************/ -/* PCI Configuration Function 7 */ -/****************************************/ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 - -/****************************** MV64360 and MV64460 PCI ***************************/ -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define PCI_0_COMMAND 0xc00 -#define PCI_1_COMMAND 0xc80 -#define PCI_0_MODE 0xd00 -#define PCI_1_MODE 0xd80 -#define PCI_0_RETRY 0xc04 -#define PCI_1_RETRY 0xc84 -#define PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define PCI_0_ARBITER_CONTROL 0x1d00 -#define PCI_1_ARBITER_CONTROL 0x1d80 -#define PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define PCI_0_P2P_CONFIG 0x1d14 -#define PCI_1_P2P_CONFIG 0x1d94 - -#define PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define PCI_0_CONFIG_ADDR 0xcf8 -#define PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define PCI_1_CONFIG_ADDR 0xc78 -#define PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define PCI_0_SERR_MASK 0xc28 -#define PCI_1_SERR_MASK 0xca8 -#define PCI_0_ERROR_ADDR_LOW 0x1d40 -#define PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define PCI_0_ERROR_COMMAND 0x1d50 -#define PCI_1_ERROR_COMMAND 0x1dd0 -#define PCI_0_ERROR_CAUSE 0x1d58 -#define PCI_1_ERROR_CAUSE 0x1dd8 -#define PCI_0_ERROR_MASK 0x1d5c -#define PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define PCI_0_MMASK 0X1D24 -#define PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 - /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c1 */ -#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDR 0x048 -#define PCI_VPD_DATA 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDR 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_X_COMMAND 0x060 -#define PCI_X_STATUS 0x064 -#define PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define PCI_CPU_BASE_ADDR_LOW 0x220 -#define PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define PCI_P2P_I_O_BASE_ADDR 0x420 -#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************** MV64360 and MV64460 PCI End ***************************/ -/****************************************/ -/* I20 Support registers */ -/****************************************/ - -#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C -#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C - -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C - - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - - -/****************************************/ -/* Communication Unit Registers */ -/****************************************/ -/* -#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200 -#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 -#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 -#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c -#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 -#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 -#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 -#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 -#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 -#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 -#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c -#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 -#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 -#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 -#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 -#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 -#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 -#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c -#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 -#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 -#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 - */ -#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 -#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 -#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 -#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c -#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 -#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 -#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0 -#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4 -#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 -#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc -#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 -#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 - /*#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf3201 */ -#define COMM_UNIT_ARBITER_CONTROL 0xf300 -#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 -#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 -#define COMM_UNIT_INTERRUPT_MASK 0xf314 -#define COMM_UNIT_ERROR_ADDRESS 0xf314 -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - - /*#define SERIAL_INIT_LAST_DATA 0xf3241 */ - /*#define SERIAL_INIT_STATUS_AND_CONTROL 0xf3281 */ -#define SERIAL_INIT_LAST_DATA 0xf324 -#define SERIAL_INIT_CONTROL 0xf328 -#define SERIAL_INIT_STATUS 0xf32c - - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define ETH_PHY_ADDR_REG 0x2000 -#define ETH_SMI_REG 0x2004 -#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define ETH_UNIT_DEFAULTID_REG 0x200c -#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define ETH_BAR_0 0x2200 -#define ETH_BAR_1 0x2208 -#define ETH_BAR_2 0x2210 -#define ETH_BAR_3 0x2218 -#define ETH_BAR_4 0x2220 -#define ETH_BAR_5 0x2228 -#define ETH_SIZE_REG_0 0x2204 -#define ETH_SIZE_REG_1 0x220c -#define ETH_SIZE_REG_2 0x2214 -#define ETH_SIZE_REG_3 0x221c -#define ETH_SIZE_REG_4 0x2224 -#define ETH_SIZE_REG_5 0x222c -#define ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define ETH_DSCP_3(port) (0x242c + (port<<10)) -#define ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/****************************************/ -/* Cunit Debug (for internal use) */ -/****************************************/ - -#define CUNIT_ADDRESS 0xf340 -#define CUNIT_COMMAND_AND_ID 0xf344 -#define CUNIT_WRITE_DATA_LOW 0xf348 -#define CUNIT_WRITE_DATA_HIGH 0xf34c -#define CUNIT_WRITE_BYTE_ENABLE 0xf358 -#define CUNIT_READ_DATA_LOW 0xf350 -#define CUNIT_READ_DATA_HIGH 0xf354 -#define CUNIT_READ_ID 0xf35c - -/****************************************/ -/* Fast Ethernet Unit Registers */ -/****************************************/ - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define ETH_PHY_ADDR_REG 0x2000 -#define ETH_SMI_REG 0x2004 -#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define ETH_UNIT_DEFAULTID_REG 0x200c -#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define ETH_BAR_0 0x2200 -#define ETH_BAR_1 0x2208 -#define ETH_BAR_2 0x2210 -#define ETH_BAR_3 0x2218 -#define ETH_BAR_4 0x2220 -#define ETH_BAR_5 0x2228 -#define ETH_SIZE_REG_0 0x2204 -#define ETH_SIZE_REG_1 0x220c -#define ETH_SIZE_REG_2 0x2214 -#define ETH_SIZE_REG_3 0x221c -#define ETH_SIZE_REG_4 0x2224 -#define ETH_SIZE_REG_5 0x222c -#define ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define ETH_DSCP_3(port) (0x242c + (port<<10)) -#define ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/* Compat with interrupts.c */ -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(0) -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(1) -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(2) - -#define ETHERNET0_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(0) -#define ETHERNET1_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(1) -#define ETHERNET2_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(2) - -/* Ethernet GT64260 */ -/* -#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 -#define ETHERNET_SMI_REGISTER 0x2010 -*/ -/* Ethernet 0 */ -/* -#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 -#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 -#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 -#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 -#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 -#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 -#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 -#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 -#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 -#define ETHERNET0_MIB_COUNTER_BASE 0x2500 -*/ -/* Ethernet 1 */ -/* -#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 -#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 -#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 -#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 -#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 -#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 -#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 -#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 -#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 -#define ETHERNET1_MIB_COUNTER_BASE 0x2900 -*/ -/* Ethernet 2 */ -/* -#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 -#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 -#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 -#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 -#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 -#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 -#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 -#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 -#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 -#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 -*/ - -/****************************************/ -/* SDMA Registers */ -/****************************************/ - -#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 -#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 -#define CHANNEL0_COMMAND_REGISTER 0x4008 -#define CHANNEL0_RX_CMD_STATUS 0x4800 -#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 -#define CHANNEL0_RX_BUFFER_POINTER 0x4808 -#define CHANNEL0_RX_NEXT_POINTER 0x480c -#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 -#define CHANNEL0_TX_CMD_STATUS 0x4C00 -#define CHANNEL0_TX_PACKET_SIZE 0x4C04 -#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 -#define CHANNEL0_TX_NEXT_POINTER 0x4C0c -#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 -#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 -/* -#define CHANNEL1_CONFIGURATION_REGISTER 0x5000 -#define CHANNEL1_COMMAND_REGISTER 0x5008 -#define CHANNEL1_RX_CMD_STATUS 0x5800 -#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804 -#define CHANNEL1_RX_BUFFER_POINTER 0x5808 -#define CHANNEL1_RX_NEXT_POINTER 0x580c -#define CHANNEL1_TX_CMD_STATUS 0x5C00 -#define CHANNEL1_TX_PACKET_SIZE 0x5C04 -#define CHANNEL1_TX_BUFFER_POINTER 0x5C08 -#define CHANNEL1_TX_NEXT_POINTER 0x5C0c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810 -#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10 -#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14 -#define CHANNEL2_CONFIGURATION_REGISTER 0x6000 -#define CHANNEL2_COMMAND_REGISTER 0x6008 -#define CHANNEL2_RX_CMD_STATUS 0x6800 -#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804 -#define CHANNEL2_RX_BUFFER_POINTER 0x6808 -#define CHANNEL2_RX_NEXT_POINTER 0x680c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_TX_CMD_STATUS 0x6C00 -#define CHANNEL2_TX_PACKET_SIZE 0x6C04 -#define CHANNEL2_TX_BUFFER_POINTER 0x6C08 -#define CHANNEL2_TX_NEXT_POINTER 0x6C0c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 -#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 -*/ -/* SDMA Interrupt */ -/* -#define SDMA_CAUSE 0xb820 -#define SDMA_MASK 0xb8a0 -*/ -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define SDMA_CAUSE_REG 0xb800 -#define SDMA_MASK_REG 0xb880 - -/****************************************/ -/* Baude Rate Generators Registers */ -/****************************************/ - -/* BRG 0 */ -#define BRG0_CONFIGURATION_REGISTER 0xb200 -#define BRG0_BAUDE_TUNING_REGISTER 0xb204 - -/* BRG 1 */ -#define BRG1_CONFIGURATION_REGISTER 0xb208 -#define BRG1_BAUDE_TUNING_REGISTER 0xb20c - -/* BRG 2 */ -#define BRG2_CONFIGURATION_REGISTER 0xb210 -#define BRG2_BAUDE_TUNING_REGISTER 0xb214 - -/* BRG Interrupts */ -#define BRG_CAUSE_REGISTER 0xb834 -#define BRG_MASK_REGISTER 0xb8b4 -#define BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3)) -#define BRG_CAUSE_REG BRG_CAUSE_REGISTER /*0xb8341 */ -#define BRG_MASK_REG BRG_MASK_REGISTER /*0xb8b41 */ - -/* MISC */ - -#define MAIN_ROUTING_REGISTER 0xb400 -#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 -#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 -#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ -#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 -#define WATCHDOG_VALUE_REGISTER 0xb414 -#define WATCHDOG_CONFIG_REG WATCHDOG_CONFIGURATION_REGISTER /*0xb4101 */ -#define WATCHDOG_VALUE_REG WATCHDOG_VALUE_REGISTER /*0xb4141 */ - - -/****************************************/ -/* Flex TDM Registers */ -/****************************************/ - -/* FTDM Port */ - -#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 -#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 -#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 -#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c -#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 -#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 -#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 - -/* FTDM Interrupts */ - -#define FTDM_CAUSE_REGISTER 0xb830 -#define FTDM_MASK_REGISTER 0xb8b0 - - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define GPP_IO_CONTROL 0xf100 -#define GPP_LEVEL_CONTROL 0xf110 -#define GPP_VALUE 0xf104 -#define GPP_INTERRUPT_CAUSE 0xf108 -#define GPP_INTERRUPT_MASK 0xf10c -#define GPP_INTERRUPT_MASK0 GPP_INTERRUPT_MASK /* 0xf10c1 */ -#define GPP_INTERRUPT_MASK1 0xf114 -#define GPP_VALUE_SET 0xf118 -#define GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ -#define MPP_CONTROL0 0xf000 -#define MPP_CONTROL1 0xf004 -#define MPP_CONTROL2 0xf008 -#define MPP_CONTROL3 0xf00c -#define DEBUG_PORT_MULTIPLEX 0xf014 - /*#define SERIAL_PORT_MULTIPLEX 0xf0101 */ - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ -/****************************************/ -/* Interrupts (checked I.A. 14.10.02) */ -/****************************************/ - -#define LOW_INTERRUPT_CAUSE_REGISTER 0x004 /* gt64260: 0xc181 */ -#define HIGH_INTERRUPT_CAUSE_REGISTER 0x00c /* gt64260: 0xc681 */ -#define CPU_INTERRUPT_MASK_REGISTER_LOW 0x014 /* gt64260: 0xc1c1 */ -#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0x01c /* gt64260: 0xc6c1 */ -#define CPU_SELECT_CAUSE_REGISTER 0x024 /* gt64260: 0xc701 */ -#define CPU_INTERRUPT_1_MASK_REGISTER_LOW 0x034 /* new in the MV64360 and MV64460 */ -#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH 0x03c /* new in the MV64360 and MV64460 */ -#define CPU_SELECT_1_CAUSE_REGISTER 0x044 /* new in the MV64360 and MV64460 */ -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x054 /* gt64260: 0xc241 */ -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c /* gt64260: 0xc641 */ -#define PCI_0SELECT_CAUSE 0x064 /* gt64260: 0xc741 */ -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x074 /* gt64260: 0xca41 */ -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c /* gt64260: 0xce41 */ -#define PCI_1SELECT_CAUSE 0x084 /* gt64260: 0xcf41 */ -/*#define CPU_INT_0_MASK 0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_1_MASK 0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_2_MASK 0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_3_MASK 0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */ - -#define MAIN_INTERRUPT_CAUSE_LOW LOW_INTERRUPT_CAUSE_REGISTER /* 0x0041 */ -#define MAIN_INTERRUPT_CAUSE_HIGH HIGH_INTERRUPT_CAUSE_REGISTER /* 0x00c1 */ -#define CPU_INTERRUPT0_MASK_LOW CPU_INTERRUPT_MASK_REGISTER_LOW /* 0x0141 */ -#define CPU_INTERRUPT0_MASK_HIGH CPU_INTERRUPT_MASK_REGISTER_HIGH /*0x01c1 */ -#define CPU_INTERRUPT0_SELECT_CAUSE CPU_SELECT_CAUSE_REGISTER /* 0x0241 */ -#define CPU_INTERRUPT1_MASK_LOW CPU_INTERRUPT_1_MASK_REGISTER_LOW /* 0x0341 */ -#define CPU_INTERRUPT1_MASK_HIGH CPU_INTERRUPT_1_MASK_REGISTER_HIGH /* 0x03c1 */ -#define CPU_INTERRUPT1_SELECT_CAUSE CPU_SELECT_1_CAUSE_REGISTER /* 0x0441 */ -#define INTERRUPT0_MASK_0_LOW PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */ -#define INTERRUPT0_MASK_0_HIGH PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x05c1 */ -#define INTERRUPT0_SELECT_CAUSE PCI_0SELECT_CAUSE /* 0x0641 */ -#define INTERRUPT1_MASK_0_LOW PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0741 */ -#define INTERRUPT1_MASK_0_HIGH PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x07c1 */ -#define INTERRUPT1_SELECT_CAUSE PCI_1SELECT_CAUSE /* 0x0841 */ - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define I2C_SLAVE_ADDRESS 0xc000 -#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 -#define I2C_DATA 0xc004 -#define I2C_CONTROL 0xc008 -#define I2C_STATUS_BAUDE_RATE 0xc00C -#define I2C_SOFT_RESET 0xc01c -#define I2C_SLAVE_ADDR I2C_SLAVE_ADDRESS /* 0xc0001 */ -#define I2C_EXTENDED_SLAVE_ADDR I2C_EXTENDED_SLAVE_ADDRESS /*0xc0101 */ - -/****************************************/ -/* MPSC Registers */ -/****************************************/ - - /* MPSCs Clocks Routing Registers */ - -#define MPSC_ROUTING_REG 0xb400 -#define MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - -/* MPSC0 */ - -#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 -#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 -#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 -#define CHANNEL0_REGISTER1 0x800c -#define CHANNEL0_REGISTER2 0x8010 -#define CHANNEL0_REGISTER3 0x8014 -#define CHANNEL0_REGISTER4 0x8018 -#define CHANNEL0_REGISTER5 0x801c -#define CHANNEL0_REGISTER6 0x8020 -#define CHANNEL0_REGISTER7 0x8024 -#define CHANNEL0_REGISTER8 0x8028 -#define CHANNEL0_REGISTER9 0x802c -#define CHANNEL0_REGISTER10 0x8030 -#define CHANNEL0_REGISTER11 0x8034 - -/* MPSC1 */ - -#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840 -#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844 -#define MPSC1_PROTOCOL_CONFIGURATION 0x8848 -#define CHANNEL1_REGISTER1 0x884c -#define CHANNEL1_REGISTER2 0x8850 -#define CHANNEL1_REGISTER3 0x8854 -#define CHANNEL1_REGISTER4 0x8858 -#define CHANNEL1_REGISTER5 0x885c -#define CHANNEL1_REGISTER6 0x8860 -#define CHANNEL1_REGISTER7 0x8864 -#define CHANNEL1_REGISTER8 0x8868 -#define CHANNEL1_REGISTER9 0x886c -#define CHANNEL1_REGISTER10 0x8870 -#define CHANNEL1_REGISTER11 0x8874 - -/* MPSC2 */ - -#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040 -#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044 -#define MPSC2_PROTOCOL_CONFIGURATION 0x9048 -#define CHANNEL2_REGISTER1 0x904c -#define CHANNEL2_REGISTER2 0x9050 -#define CHANNEL2_REGISTER3 0x9054 -#define CHANNEL2_REGISTER4 0x9058 -#define CHANNEL2_REGISTER5 0x905c -#define CHANNEL2_REGISTER6 0x9060 -#define CHANNEL2_REGISTER7 0x9064 -#define CHANNEL2_REGISTER8 0x9068 -#define CHANNEL2_REGISTER9 0x906c -#define CHANNEL2_REGISTER10 0x9070 -#define CHANNEL2_REGISTER11 0x9074 - -/* MPSCs Interrupts */ - -#define MPSC0_CAUSE 0xb824 -#define MPSC0_MASK 0xb8a4 -#define MPSC1_CAUSE 0xb828 -#define MPSC1_MASK 0xb8a8 -#define MPSC2_CAUSE 0xb82c -#define MPSC2_MASK 0xb8ac - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define CUNIT_BASE_ADDR_REG0 0xf200 -#define CUNIT_BASE_ADDR_REG1 0xf208 -#define CUNIT_BASE_ADDR_REG2 0xf210 -#define CUNIT_BASE_ADDR_REG3 0xf218 -#define CUNIT_SIZE0 0xf204 -#define CUNIT_SIZE1 0xf20c -#define CUNIT_SIZE2 0xf214 -#define CUNIT_SIZE3 0xf21c -#define CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define CUNIT_INTERRUPT_MASK_REG 0xf314 -#define CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define CUNIT_ARBITER_CONTROL_REG 0xf300 -#define CUNIT_CONFIG_REG 0xb40c -#define CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define CUNIT_DEBUG_LOW 0xf340 -#define CUNIT_DEBUG_HIGH 0xf344 -#define CUNIT_MMASK 0xf380 - -#endif /* __INCmv_gen_regh */ diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h index 167248db1e..572e0d345d 100644 --- a/board/Marvell/include/pci.h +++ b/board/Marvell/include/pci.h @@ -7,8 +7,8 @@ /* includes */ -#include"core.h" -#include"memory.h" +#include "core.h" +#include "memory.h" /* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ #define PCI_MAX_DEVICES 22 diff --git a/board/Marvell/mv88f6281gtw_ge/Kconfig b/board/Marvell/mv88f6281gtw_ge/Kconfig new file mode 100644 index 0000000000..00d7d1c5ee --- /dev/null +++ b/board/Marvell/mv88f6281gtw_ge/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MV88F6281GTW_GE + +config SYS_BOARD + default "mv88f6281gtw_ge" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "mv88f6281gtw_ge" + +endif diff --git a/board/Marvell/mv88f6281gtw_ge/MAINTAINERS b/board/Marvell/mv88f6281gtw_ge/MAINTAINERS new file mode 100644 index 0000000000..9c26ca7658 --- /dev/null +++ b/board/Marvell/mv88f6281gtw_ge/MAINTAINERS @@ -0,0 +1,6 @@ +MV88F6281GTW_GE BOARD +M: Prafulla Wadaskar +S: Maintained +F: board/Marvell/mv88f6281gtw_ge/ +F: include/configs/mv88f6281gtw_ge.h +F: configs/mv88f6281gtw_ge_defconfig diff --git a/board/Marvell/mv88f6281gtw_ge/Makefile b/board/Marvell/mv88f6281gtw_ge/Makefile index ceb33491d9..e83bbf76e2 100644 --- a/board/Marvell/mv88f6281gtw_ge/Makefile +++ b/board/Marvell/mv88f6281gtw_ge/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mv88f6281gtw_ge.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mv88f6281gtw_ge.o diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index e1652c0831..ef08ad8928 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include "mv88f6281gtw_ge.h" @@ -24,9 +24,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, - MV88F6281GTW_GE_OE_VAL_HIGH, - MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); + mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW, + MV88F6281GTW_GE_OE_VAL_HIGH, + MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -94,7 +94,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig new file mode 100644 index 0000000000..124b66da0f --- /dev/null +++ b/board/Marvell/openrd/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OPENRD + +config SYS_BOARD + default "openrd" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "openrd" + +endif diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS new file mode 100644 index 0000000000..7a189ab6d5 --- /dev/null +++ b/board/Marvell/openrd/MAINTAINERS @@ -0,0 +1,12 @@ +OPENRD BOARD +M: Prafulla Wadaskar +S: Maintained +F: board/Marvell/openrd/ +F: include/configs/openrd.h +F: configs/openrd_base_defconfig + +OPENRD_CLIENT BOARD +#M: - +S: Maintained +F: configs/openrd_client_defconfig +F: configs/openrd_ultimate_defconfig diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile index f87fe7a6e9..8f95b7922e 100644 --- a/board/Marvell/openrd/Makefile +++ b/board/Marvell/openrd/Makefile @@ -11,24 +11,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := openrd.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := openrd.o diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index a005a2f79d..55cf525cf8 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include "openrd.h" @@ -27,9 +27,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(OPENRD_OE_VAL_LOW, - OPENRD_OE_VAL_HIGH, - OPENRD_OE_LOW, OPENRD_OE_HIGH); + mvebu_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -104,7 +104,7 @@ int board_init(void) #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/rd6281a/Kconfig b/board/Marvell/rd6281a/Kconfig new file mode 100644 index 0000000000..025ee26dc6 --- /dev/null +++ b/board/Marvell/rd6281a/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RD6281A + +config SYS_BOARD + default "rd6281a" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "rd6281a" + +endif diff --git a/board/Marvell/rd6281a/MAINTAINERS b/board/Marvell/rd6281a/MAINTAINERS new file mode 100644 index 0000000000..d4ad592a9e --- /dev/null +++ b/board/Marvell/rd6281a/MAINTAINERS @@ -0,0 +1,6 @@ +RD6281A BOARD +M: Prafulla Wadaskar +S: Maintained +F: board/Marvell/rd6281a/ +F: include/configs/rd6281a.h +F: configs/rd6281a_defconfig diff --git a/board/Marvell/rd6281a/Makefile b/board/Marvell/rd6281a/Makefile index 67f7162c1e..cb773705e8 100644 --- a/board/Marvell/rd6281a/Makefile +++ b/board/Marvell/rd6281a/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := rd6281a.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := rd6281a.o diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 33ef0c78e5..b0020c95a5 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include "rd6281a.h" @@ -23,9 +23,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(RD6281A_OE_VAL_LOW, - RD6281A_OE_VAL_HIGH, - RD6281A_OE_LOW, RD6281A_OE_HIGH); + mvebu_config_gpio(RD6281A_OE_VAL_LOW, + RD6281A_OE_VAL_HIGH, + RD6281A_OE_LOW, RD6281A_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -93,7 +93,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_RD88F6281; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/Marvell/sheevaplug/Kconfig b/board/Marvell/sheevaplug/Kconfig new file mode 100644 index 0000000000..e5f9284729 --- /dev/null +++ b/board/Marvell/sheevaplug/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SHEEVAPLUG + +config SYS_BOARD + default "sheevaplug" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "sheevaplug" + +endif diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS new file mode 100644 index 0000000000..2b0103d07d --- /dev/null +++ b/board/Marvell/sheevaplug/MAINTAINERS @@ -0,0 +1,6 @@ +SHEEVAPLUG BOARD +M: Prafulla Wadaskar +S: Maintained +F: board/Marvell/sheevaplug/ +F: include/configs/sheevaplug.h +F: configs/sheevaplug_defconfig diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile index 6ce57abd1e..e812545837 100644 --- a/board/Marvell/sheevaplug/Makefile +++ b/board/Marvell/sheevaplug/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sheevaplug.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sheevaplug.o diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 87e49f417b..8907fb58ff 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "sheevaplug.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW, - SHEEVAPLUG_OE_VAL_HIGH, - SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); + mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW, + SHEEVAPLUG_OE_VAL_HIGH, + SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile deleted file mode 100644 index c7c05a17e6..0000000000 --- a/board/RPXClassic/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o eccx.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/RPXClassic/README b/board/RPXClassic/README deleted file mode 100644 index e03f670d1c..0000000000 --- a/board/RPXClassic/README +++ /dev/null @@ -1,19 +0,0 @@ -# Porting U-Boot onto RPXClassic LF_BW31 board -# Written by Pierre AUBERT -# E-Mail p.aubert@staubli.com -# Stäubli Faverges - -# -# Sept. 20 2001 -# -# Cross compile: Montavista Hardhat ported on HP-UX 10.20 -# - -Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000 -DRAM : 16 Mb from 0 -NVRAM : 512 kb from 0xfa000000 - - -- environment is stored in NVRAM -- Mac address is read from EEPROM -- ethernet on SCC1 or fast ethernet on FEC are running (depending on the - configuration flag CONFIG_FEC_ENET) diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c deleted file mode 100644 index f47e8fa44d..0000000000 --- a/board/RPXClassic/RPXClassic.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static unsigned char aschex_to_byte (unsigned char *cp); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXClassic\n"); - return (0); -} - -/*----------------------------------------------------------------------------- - * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM - *----------------------------------------------------------------------------- - */ -static void board_get_enetaddr(uchar *enet) -{ - int i; - char buff[256], *cp; - - /* Initialize I2C */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x54, 0, 1, (uchar *)buff, 128); - i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128); - - /* Retrieve MAC address in buffer (key EA) */ - for (cp = buff;;) { - if (cp[0] == 'E' && cp[1] == 'A') { - cp += 3; - /* Read MAC address */ - for (i = 0; i < 6; i++, cp += 2) { - enet[i] = aschex_to_byte ((unsigned char *)cp); - } - } - /* Scan to the end of the record */ - while ((*cp != '\n') && (*cp != (char)0xff)) { - cp++; - } - /* If the next character is a \n, 0 or ff, we are done. */ - cp++; - if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff)) - break; - } - -#ifdef CONFIG_FEC_ENET - /* The MAC address is the same as normal ethernet except the 3rd byte */ - /* (See the E.P. Planet Core Overview manual */ - enet[3] |= 0x80; -#endif - - printf("MAC address = %pM\n", enet); -} - -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -void rpxclassic_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; - -#ifdef CONFIG_FEC_ENET - - /* Validate the fast ethernet tranceiver */ - *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; - *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; - *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; - *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; -#endif - -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} -/*----------------------------------------------------------------------------- - * aschex_to_byte -- - *----------------------------------------------------------------------------- - */ -static unsigned char aschex_to_byte (unsigned char *cp) -{ - u_char byte, c; - - c = *cp++; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte = c * 16; - - c = *cp; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte += c; - - return (byte); -} diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c deleted file mode 100644 index 766a19eb1e..0000000000 --- a/board/RPXClassic/eccx.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* Video support for the ECCX daughter board */ - - -#include -#include - -#ifdef CONFIG_VIDEO_SED13806 -#include - - -/* Screen configurations: the initialization of the SD13806 depends on - screen and on display mode. We handle only 8bpp and 16 bpp modes */ - -/* ECCX board is supplied with a NEC NL6448BC20 screen */ -#ifdef CONFIG_NEC_NL6448BC20 -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SED13806_8BPP -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x40}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x01}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; -#endif /* CONFIG_VIDEO_SED13806_8BPP */ - -#ifdef CONFIG_VIDEO_SED13806_16BPP - -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x01}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SED13806_16BPP */ -#endif /* CONFIG_NEC_NL6448BC20 */ - - -#ifdef CONFIG_CONSOLE_EXTRA_INFO - -/*----------------------------------------------------------------------------- - * video_get_info_str -- setup a board string: type, speed, etc. - * line_number= location to place info string beside logo - * info= buffer for info string - *----------------------------------------------------------------------------- - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " RPXClassic board"); - } - else { - info [0] = '\0'; - } - -} -#endif - -/*----------------------------------------------------------------------------- - * board_video_init -- init de l'EPSON, config du CS - *----------------------------------------------------------------------------- - */ -unsigned int board_video_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Program ECCX registers */ - *(ECCX_CSR12) |= ECCX_860; - *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2; - *(ECCX_CSR8) |= ECCX_ENEPSON; - - memctl->memc_or2 = SED13806_OR; - memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES; - - return (SED13806_REG_ADDR); -} - -/*----------------------------------------------------------------------------- - * board_validate_screen -- - *----------------------------------------------------------------------------- - */ -void board_validate_screen (unsigned int base) -{ - /* Activate the panel bias power */ - *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80; -} -/*----------------------------------------------------------------------------- - * board_get_regs -- - *----------------------------------------------------------------------------- - */ -const S1D_REGS *board_get_regs (void) -{ - return (init_regs); -} -/*----------------------------------------------------------------------------- - * board_get_width -- - *----------------------------------------------------------------------------- - */ -int board_get_width (void) -{ - return (DISPLAY_WIDTH); -} - -/*----------------------------------------------------------------------------- - * board_get_height -- - *----------------------------------------------------------------------------- - */ -int board_get_height (void) -{ - return (DISPLAY_HEIGHT); -} - -#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c deleted file mode 100644 index 97ffa68aa2..0000000000 --- a/board/RPXClassic/flash.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * RPXClassic uses Am29DL323B flash memory with 2 banks - * - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: - printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Reset flash componeny */ - addr [0] = 0xf0f0f0f0; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0xAAAAAAAA ; - addr[0x555] = 0x55555555 ; - addr[0xAAA] = 0x90909090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 16 Mb */ - - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - - /* check for protected sectors */ - for (i = 0; i < 23; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - /* Check for protected sectors in the 2nd bank */ - addr[0x100AAA] = 0xAAAAAAAA ; - addr[0x100555] = 0x55555555 ; - addr[0x100AAA] = 0x90909090 ; - - for (i = 23; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank 1 */ - addr = (volatile unsigned long *)info->start[23]; - - *addr = 0xF0F0F0F0; /* reset bank 2 */ - - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/RPXClassic/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug deleted file mode 100644 index b9c84c77d6..0000000000 --- a/board/RPXClassic/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/RPXlite/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/RPXlite/README b/board/RPXlite/README deleted file mode 100644 index 3ca671126d..0000000000 --- a/board/RPXlite/README +++ /dev/null @@ -1,877 +0,0 @@ -# Porting U-Boot onto RPXlite board -# Written by Yoo. Jonghoon -# E-Mail : yooth@ipone.co.kr -# IP ONE Inc. - -# Since 2001. 1. 29 - -# Shell : bash -# Cross-compile tools : Montavista Hardhat -# Debugging tools : Windriver VisionProbe (PowerPC BDM) -# ppcboot ver. : ppcboot-0.8.1 - -############################################################### -# 1. Hardware setting -############################################################### - -1.1. Board, BDM settings - Install board, BDM, connect each other - -1.2. Save Register value - Boot with board-on monitor program and save the - register values with BDM. - -1.3. Configure flash programmer - Check flash memory area in the memory map. - 0xFFC00000 - 0xFFFFFFFF - - Boot monitor program is at - 0xFFF00000 - - You can program on-board flash memory with VisionClick - flash programmer. Set the target flash device as: - - 29DL800B - - (?) The flash memory device in the board *is* 29LV800B, - but I cannot program it with '29LV800B' option. - (in VisionClick flash programming tools) - I don't know why... - -1.4. Save boot monitor program *IMPORTANT* - Upload boot monitor program from board to file. - boot monitor program starts at 0xFFF00000 - -1.5. Test flash memory programming - Try to erase boot program in the flash memory, - and re-write them. - *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE - BEFORE ERASING FLASH - -############################################################### -# 2. U-Boot setting -############################################################### - -2.1. Download U-Boot tarball at - ftp://ftp.denx.de - (The latest version is ppcboot-0.8.1.tar.bz2) - - To extract the archive use the following syntax : - > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - - -2.2. Add the following lines in '.profile' - export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin - -2.3. Make board specific config, for example: - > cd ppcboot-0.8.1 - > make TQM860L_config - - Now we can build ppcboot bin files. - After make all, you must see these files in your - ppcboot root directory. - - ppcboot - ppcboot.bin - ppcboot.srec - ppcboot.map - -2.4. Make your own board directory into the - ppcboot-0.8.1/board - and make your board-specific files here. - - For exmanple, tqm8xx files are composed of - .depend : Nothing - Makefile : To make config file - config.mk : Sets base address - flash.c : Flash memory control files - ppcboot.lds : linker(ld) script? (I don't know this yet) - tqm8xx.c : DRAM control and board check routines - - And, add your board config lines in the - ppcboot-0.8.1/Makefile - - Finally, add config_(your board).h file in the - ppcboot-0.8.1/include/ - - I've made board/rpxlite directory, and just copied - tqm8xx settings for now. - - Rebuild ppcboot for rpxlite board: - > make rpxlite_config - > make - -############################################################### -# 3. U-Boot porting -############################################################### - -3.1. My RPXlite files are based on tqm8xx board files. - > cd board - > cp -r tqm8xx RPXLITE - > cd RPXLITE - > mv tqm8xx.c RPXLITE.c - > cd ../../include - > cp config_tqm8xx.h config_RPXLITE.h - -3.2. Modified files are: - board/RPXLITE/RPXLITE.c /* DRAM-related routines */ - board/RPXLITE/flash.c /* flash-related routines */ - board/RPXLITE/config.mk /* set text base address */ - arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */ - include/config_RPXLITE.h /* board specific registers */ - - See 'reg_config.txt' for register values in detail. - -############################################################### -# 4. Running Linux -############################################################### - - -############################################################### -# Misc Information -############################################################### - -mem_config.txt: -=============== - -Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device -manufacturer id : 01 (AMD) -device id : 5B (AM29LV800B) -size : 4Mbyte -sector # : 19 - -Sector information : - -number start addr. size -00 FFC0_0000 64 -01 FFC1_0000 32 -02 FFC1_8000 32 -03 FFC2_0000 128 -04 FFC4_0000 256 -05 FFC8_0000 256 -06 FFCC_0000 256 -07 FFD0_0000 256 -08 FFD4_0000 256 -09 FFD8_0000 256 -10 FFDC_0000 256 -11 FFE0_0000 256 -12 FFE4_0000 256 -13 FFE8_0000 256 -14 FFEC_0000 256 -15 FFF0_0000 256 -16 FFF4_0000 256 -17 FFF8_0000 256 -18 FFFC_0000 256 - - -reg_config.txt: -=============== - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* SIU (System Interface Unit) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - - -/*### IMMR */ -/*### Internal Memory Map Register */ -/*### Chap. 11.4.1 */ - - ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ - PARTNUM = 0x21 - MASKNUM = 0x00 - - => 0xFA20 2100 - ---------------------------------------------------------------------- - -/*### SIUMCR */ -/*### SIU Module Configuration Register */ -/*### Chap. 11.4.2 */ -/*### Offset : 0x0000 0000 */ - - EARB = 0 - EARP = 0 - DSHW = 0 - DBGC = 0 - DBPC = 0 - FRC = 0 - DLK = 0 - OPAR = 0 - PNCS = 0 - DPC = 0 - MPRE = 0 - MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ - AEME = 0 - SEME = 0 - BSC = 0 - GB5E = 0 - B2DD = 0 - B3DD = 0 - - => 0x0000 0800 - ---------------------------------------------------------------------- - -/*### SYPCR */ -/*### System Protection Control Register */ -/*### Chap. 11.4.3 */ -/*### Offset : 0x0000 0004 */ - - SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ - BMT = 0x06 /* BUS monitoring timing */ - BME = 1 /* BUS monitor enable */ - SWF = 1 - SWE = 0 /* SW watchdog disable */ - SWRI = 0 - SWP = 1 - - => 0xFFFF 0689 - ---------------------------------------------------------------------- - -/*### TESR */ -/*### Transfer Error Status Register */ -/*### Chap. 11.4.4 */ -/*### Offset : 0x0000 0020 */ - - IEXT = 0 - ITMT = 0 - IPB = 0000 - DEXT = 0 - DTMT = 0 - DPB = 0000 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIPEND */ -/*### SIU Interrupt Pending Register */ -/*### Chap. 11.5.4.1 */ -/*### Offset : 0x0000 0010 */ - - IRQ0~IRQ7 = 0 - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIMASK */ -/*### SIU Interrupt Mask Register */ -/*### Chap. 11.5.4.2 */ -/*### Offset : 0x0000 0014 */ - - IRM0~IRM7 = 0 /* Mask all interrupts */ - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIEL */ -/*### SIU Interrupt Edge/Level Register */ -/*### Chap. 11.5.4.3 */ -/*### Offset : 0x0000 0018 */ - - ED0~ED7 = 0 /* Low level triggered */ - WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIVEC */ -/*### SIU Interrupt Vector Register */ -/*### Chap. 11.5.4.4 */ -/*### Offset : 0x0000 001C */ - - INTC = 3C /* The lowest interrupt is pending..(?) */ - - => 0x3C00 0000 - ---------------------------------------------------------------------- - -/*### SWSR */ -/*### Software Service Register */ -/*### Chap. 11.7.1 */ -/*### Offset : 0x0000 001E */ - - SEQ = 0 - - => 0x0000 - ---------------------------------------------------------------------- - -/*### SDCR */ -/*### SDMA Configuration Register */ -/*### Chap. 20.2.1 */ -/*### Offset : 0x0000 0032 */ - - FRZ = 0 - RAID = 01 /* Priority level 5 (BR5) (normal operation) */ - - => 0x0000 0001 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMA (User Programmable Machine A) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - -/*### Chap. 16.6.4.1 */ -/*### Offset = 0x0000 017c */ - - T0 = CFFF CC24 /* Single Read */ - T1 = 0FFF CC04 - T2 = 0CAF CC04 - T3 = 03AF CC08 - T4 = 3FBF CC27 /* last */ - T5 = FFFF CC25 - T6 = FFFF CC25 - T7 = FFFF CC25 - T8 = CFFF CC24 /* Burst Read */ - T9 = 0FFF CC04 - T10 = 0CAF CC84 - T11 = 03AF CC88 - T12 = 3FBF CC27 /* last */ - T13 = FFFF CC25 - T14 = FFFF CC25 - T15 = FFFF CC25 - T16 = FFFF CC25 - T17 = FFFF CC25 - T18 = FFFF CC25 - T19 = FFFF CC25 - T20 = FFFF CC25 - T21 = FFFF CC25 - T22 = FFFF CC25 - T23 = FFFF CC25 - T24 = CFFF CC24 /* Single Write */ - T25 = 0FFF CC04 - T26 = 0CFF CC04 - T27 = 03FF CC00 - T28 = 3FFF CC27 /* last */ - T29 = FFFF CC25 - T30 = FFFF CC25 - T31 = FFFF CC25 - T32 = CFFF CC24 /* Burst Write */ - T33 = 0FFF CC04 - T34 = 0CFF CC80 - T35 = 03FF CC8C - T36 = 0CFF CC00 - T37 = 33FF CC27 /* last */ - T38 = FFFF CC25 - T39 = FFFF CC25 - T40 = FFFF CC25 - T41 = FFFF CC25 - T42 = FFFF CC25 - T43 = FFFF CC25 - T44 = FFFF CC25 - T45 = FFFF CC25 - T46 = FFFF CC25 - T47 = FFFF CC25 - T48 = C0FF CC24 /* Refresh */ - T49 = 03FF CC24 - T50 = 0FFF CC24 - T51 = 0FFF CC24 - T52 = 3FFF CC27 /* last */ - T53 = FFFF CC25 - T54 = FFFF CC25 - T55 = FFFF CC25 - T56 = FFFF CC25 - T57 = FFFF CC25 - T58 = FFFF CC25 - T59 = FFFF CC25 - T60 = FFFF CC25 /* Exception */ - T61 = FFFF CC25 - T62 = FFFF CC25 - T63 = FFFF CC25 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMB */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### Chap. 16.6.4.1 */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* MEMC */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### BR0 & OR0 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ -/*### Flash memory */ - - BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFE00 0001 - - AM = 1111 1110 0000 0000 0 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 0 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0100 /* cycle length = 4 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0140 - -/*### BR1 & OR1 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ -/*### SDRAM */ - - BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 1 /* UPMA */ - V = 1 /* Valid */ - - => 0x0000 0081 - - AM = 1111 1110 0000 0000 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 11 - BIH = 0 - SCY = 0000 /* cycle length = 0 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0E00 - -/*### BR2 & OR2 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ - - BR2 & OR2 = 0x0000 0000 /* Not used */ - -/*### BR3 & OR3 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ -/*### BCSR */ - - BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA40 0001 - - AM = 1111 1111 0111 1111 1 /* (?) */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0001 /* cycle length = 1 */ - SETA = 0 - TRLX = 0 - - => 0xFF7F 8910 - -/*### BR4 & OR4 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ -/*### NVRAM & SRAM */ - - BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ - AT = 000 - PS = 01 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA00 0401 - - AM = 1111 1111 1111 1000 0 /* 8MByte */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0111 /* cycle length = 7 */ - SETA = 0 - TRLX = 0 - - => 0xFFF8 0970 - -/*### BR5 & OR5 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ - - BR5 & OR5 = 0x0000 0000 /* Not used */ - -/*### BR6 & OR6 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ - - BR6 & OR6 = 0x0000 0000 /* Not used */ - -/*### BR7 & OR7 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ - - BR7 & OR7 = 0x0000 0000 /* Not used */ - -/*### MAR */ -/*### Memory Address Register */ -/*### Chap. 16.4.7 */ -/*### Offset : 0x0000 0164 */ - - MA = External memory address - -/*### MCR */ -/*### Memory Command Register */ -/*### Chap. 16.4.5 */ -/*### Offset : 0x0000 0168 */ - - OP = xx /* Command op code */ - UM = 1 /* Select UPMA */ - MB = 001 /* Select CS1 */ - MCLF = xxxx /* Loop times */ - MAD = xx xxxx /* Memory array index */ - -/*### MAMR */ -/*### Machine A Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0170 */ - - PTA = 0101 1000 - PTAE = 1 /* Periodic timer A enabled */ - AMA = 010 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0100 - WLFA = 0011 - TLFA = 0000 - - => 0x58A0 1430 - -/*### MBMR */ -/*### Machine B Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0174 */ - - PTA = 0100 1110 - PTAE = 0 /* Periodic timer B disabled */ - AMA = 000 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0000 - WLFA = 0000 - TLFA = 0000 - - => 0x4E00 1000 - -/*### MSTAT */ -/*### Memory Status Register */ -/*### Chap. 16.4.3 */ -/*### Offset : 0x0000 0178 */ - - PER0~PER7 = Parity error - WPER = Write protection error - - => 0x0000 - -/*### MPTPR */ -/*### Memory Periodic Timer Prescaler Register */ -/*### Chap. 16.4.8 */ -/*### Offset : 0x0000 017A */ - - PTP = 0000 1000 /* Divide by 8 */ - - => 0x0800 - -/*### MDR */ -/*### Memory Data Register */ -/*### Chap. 16.4.6 */ -/*### Offset : 0x0000 017C */ - - MD = Memory data contains the RAM array word - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* TIMERS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### TBREFx */ -/*### Timebase Reference Registers */ -/*### Chap. 11.9.2 */ -/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ -/*### (Locked) */ - - TBREFF0 = 0xFFFF FFFF - TBREFF1 = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### TBSCR */ -/*### Timebase Status and Control Registers */ -/*### Chap. 11.9.3 */ -/*### Offset : 0x0000 0200 */ -/*### (Locked) */ - - TBIRQ = 00000000 - REF0 = 0 - REF1 = 0 - REFE0 = 0 /* Reference interrupt disable */ - REFE1 = 0 - TBF = 1 - TBE = 1 /* Timebase enable */ - - => 0x0003 - ---------------------------------------------------------------------- - -/*### RTCSC */ -/*### Real-Time Clock Status and Control Registers */ -/*### Chap. 11.10.1 */ -/*### Offset : 0x0000 0220 */ -/*### (Locked) */ - - RTCIRQ = 00000000 - SEC = 1 - ALR = 0 - 38K = 0 /* PITRTCLK is driven by 32.768KHz */ - SIE = 0 - ALE = 0 - RTF = 0 - RTE = 1 /* Real-Time clock enabled */ - - => 0x0081 - ---------------------------------------------------------------------- - -/*### RTC */ -/*### Real-Time Clock Registers */ -/*### Chap. 11.10.2 */ -/*### Offset : 0x0000 0224 */ -/*### (Locked) */ - - RTC = Real time clock measured in second - ---------------------------------------------------------------------- - -/*### RTCAL */ -/*### Real-Time Clock Alarm Registers */ -/*### Chap. 11.10.3 */ -/*### Offset : 0x0000 022C */ -/*### (Locked) */ - - ALARM = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### RTSEC */ -/*### Real-Time Clock Alarm Second Registers */ -/*### Chap. 11.10.4 */ -/*### Offset : 0x0000 0228 */ -/*### (Locked) */ - - COUNTER = Counter bits(fraction of a second) - ---------------------------------------------------------------------- - -/*### PISCR */ -/*### Periodic Interrupt Status and Control Register */ -/*### Chap. 11.11.1 */ -/*### Offset : 0x0000 0240 */ -/*### (Locked) */ - - PIRQ = 0 - PS = 0 /* Write 1 to clear */ - PIE = 0 - PITF = 1 - PTE = 0 /* PIT disabled */ - ---------------------------------------------------------------------- - -/*### PITC */ -/*### PIT Count Register */ -/*### Chap. 11.11.2 */ -/*### Offset : 0x0000 0244 */ -/*### (Locked) */ - - PITC = PIT count - ---------------------------------------------------------------------- - -/*### PITR */ -/*### PIT Register */ -/*### Chap. 11.11.3 */ -/*### Offset : 0x0000 0248 */ -/*### (Locked) */ - - PIT = PIT count /* Read only */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* CLOCKS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - - ---------------------------------------------------------------------- - -/*### SCCR */ -/*### System Clock and Reset Control Register */ -/*### Chap. 15.6.1 */ -/*### Offset : 0x0000 0280 */ -/*### (Locked) */ - - COM = 11 /* Clock output disabled */ - TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ - RTDIV = 0 /* The clock is divided by 4 */ - RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ - CRQEN = 0 - PRQEN = 0 - EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ - DFSYNC = 00 /* Divided by 1 (normal operation) */ - DFBRG = 00 /* Divided by 1 (normal operation) */ - DFNL = 000 - DFNH = 000 - - => 0x6200 0000 - ---------------------------------------------------------------------- - -/*### PLPRCR */ -/*### PLL, Low-Power, and Reset Control Register */ -/*### Chap. 15.6.2 */ -/*### Offset : 0x0000 0284 */ -/*### (Locked) */ - - MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ - SPLSS = 0 - TEXPS = 0 - TMIST = 0 - CSRC = 0 /* The general system clock is generated by the DFNH field */ - LPM = 00 /* Normal high/normal low mode */ - CSR = 0 - LOLRE = 0 - FIOPD = 0 - - => 0x0050 0000 - ---------------------------------------------------------------------- - -/*### RSR */ -/*### Reset Status Register */ -/*### Chap. 12.2 */ -/*### Offset : 0x0000 0288 */ -/*### (Locked) */ - - EHRS = External hard reset - ESRS = External soft reset - LLRS = Loss-of-lock reset - SWRS = Software watchdog reset - CSRS = Check stop reset - DBHRS = Debug port hard reset - DBSRS = Debug port soft reset - JTRS = JTAG reset - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* DMA */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### SDSR */ -/*### SDMA Status Register */ -/*### Chap. 20.2.2 */ -/*### Offset : 0x0000 0908 */ - - SBER = 0 /* SDMA channel bus error */ - DSP2 = 0 /* DSP chain2 (Tx) interrupt */ - DSP1 = 0 /* DSP chain1 (Rx) interrupt */ - - => 0x00 - -/*### SDMR */ -/*### SDMA Mask Register */ -/*### Chap. 20.2.3 */ -/*### Offset : 0x0000 090C */ - - SBER = 0 - DSP2 = 0 - DSP1 = 0 /* All interrupts are masked */ - - => 0x00 - -/*### SDAR */ -/*### SDMA Address Register */ -/*### Chap. 20.2.4 */ -/*### Offset : 0x0000 0904 */ - - AR = 0xxxxx xxxx /* current system address */ - - => 0xFA20 23AC - -/*### IDSRx */ -/*### IDMA Status Register */ -/*### Chap. 20.3.3.2 */ -/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ - - AD = 0 - DONE = 0 - OB = 0 - - => 0x00 - -/*### IDMRx */ -/*### IDMA Mask Register */ -/*### Chap. 20.3.3.3 */ -/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ - - AD = 0 - DONE = 0 - OB = 0 diff --git a/board/RPXlite/README.PlanetCore b/board/RPXlite/README.PlanetCore deleted file mode 100644 index b73c5f5a87..0000000000 --- a/board/RPXlite/README.PlanetCore +++ /dev/null @@ -1,163 +0,0 @@ -After several heart-struck failure, I got one workable way to program -each other in FLASH between PlanetCore and U-Boot. - -Hardware Platform : RPXlite DW(EP 823 H1 DW) - -1. From U-Boot to PlanetCore - -Utilities : PlanetCore Boot Loader - PCL200.mot - -[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot -PCL200.mot pcl200.bin - -[Target Operation] -u-boot>t 100000 pcl200.bin -u-boot>go 0x100000 -## Starting application at 0x00100000 ... - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - - -Program MPC8xx PlanetCore Boot Loader v2.00 -Built Sep 19, 2001 at 14:34:42 -Image located from FC000000 to FC01B5D1. -(Skipping an image, only loading low boot image) - -Low boot board detected, skipping high boot image. -Erasing, programming and verifying will start in 20 -seconds -Press P to start immediately or ESC to cancel -Press Space or Enter for more options. -.............. - -Erasing -Programming -FLASH programmed successfully! -Press R to induce a hard reset - -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK -> - -2. From PlanetCore to U-Boot - -Utilities : PlanetCore FLASH Burner - PCB200.mot - -Use Flash Burner to finish the work: - -First, TFTP the U-Boot image file to RAM; For example, -RPXlite_DW.bin to 0x400000 -Second, TFTP FLASH Burner to RAM; For example, -0x100000 -Third, run the FLASH Burner and Program the U-Boot -image into the correct location in FLASH. - -[Target Operation] -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename : RPXlite_DW.bin -Enter (B)inary or (S)record input mode : B -Enter address offset : <00400000 hex> : - -Total bytes = 120096 in 232184 uSecs -Loaded addresses 00400000 through 0041D51F. -Start address = 00400000 ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename : PCB200.mot -Enter (B)inary or (S)record input mode : S -Enter address offset : <00000000 hex> : -.512.1024..2048....4096..... -Total bytes = 326280 in 2570249 uSecs -Loaded addresses 00100000 through 0011BB51. -Start address = 00100000 ->go -[Go 00100000] - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - -Bad start address -Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length = -0xFFFFFFFF -Forcing Menu Interface - -h[elp] Show commands. -c[ode] Show information on code to be loaded. -di[splay] Display all flash sections. -du[mp] Dump memory. d ? for more info. -e[rase] Erase flash sections. -f[ill] Fill flash sections. -im[age] Toggle load high, low, or both flash -images. -in[fo] Show flash information. -ma[p] Show memory map. -mo[dify] Modify memory. m ? for more info. -p[rogram] Erase, program, and verify now. -reset Restart the loader. -s[how] Show flash sections to erase and program. -t[est] Test flash sections. -q[uit] Quit without programming. -#program 400000 ff000000 1D51F -doProgram( 400000 ff000000 1D51F ) - -Start = 0x00400000, target = 0xFF000000, length = -0x0001D51F -Erasing sector 0xFF000000, length 0x008000. -Erasing sector 0xFF008000, length 0x008000. -Erasing sector 0xFF010000, length 0x008000. -Erasing sector 0xFF018000, length 0x008000. -Programming FF000000 through FF01D51E -FLASH programmed successfully! -Press R to induce a hard reset - -Forcing Hard Reset by MachineCheck and -ResetOnCheckstop... - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB -D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -------------------------------------------------- - -Well, sometimes network function of PlanetCore couldn't work when -switching from U-Boot to PlanetCore. For example, you couldn't -download a file from HOST PC via TFTP. Don't worry, just restart your -HOST PC and everything would work as smooth as clockwork. I don't -know the reason WHY:-) - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Merry Christmas and Happy New Year! - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -===== -Best regards, - -Sam diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c deleted file mode 100644 index 08575a4930..0000000000 --- a/board/RPXlite/RPXlite.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c deleted file mode 100644 index 21b11d4e90..0000000000 --- a/board/RPXlite/flash.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */ -/* volatile memctl8xx_t *memctl = &immap->im_memctl; */ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; -%%%*/ - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /*%%% sector start address modified */ - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/RPXlite/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug deleted file mode 100644 index b9c84c77d6..0000000000 --- a/board/RPXlite/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite_dw/Makefile b/board/RPXlite_dw/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/RPXlite_dw/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README deleted file mode 100644 index 14296b2ab4..0000000000 --- a/board/RPXlite_dw/README +++ /dev/null @@ -1,161 +0,0 @@ - -After following the step of Yoo. Jonghoon and Wolfgang Denk, -I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW. - -There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW. - -Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH -RPXlite RPXlite CW 850 16MB 4MB -RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB - -This fireware is specially coded for EmbeddedPlanet Co. Software Development -Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel. - -It has the following three features: - -1. 64MHz/48MHz system frequence setting options. -The default setting is 48MHz.To get a 64MHz u-boot,just add -'64' in make command,like - -make distclean -make RPXlite_DW_64_config -make all - -2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM - -The default environment parameter is stored in FLASH because it is a common choice for -environment parameter.So I make NVRAM as backup parameter storeage.The reason why I -didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter -home.Because of the possibility of using two firewares on this board,I didn't -'disturb' EEPROM.To get NVRAM support,you may use the following build command: - -make distclean -make RPXlite_DW_NVRAM_config -make all - -3. LCD panel support - -To support the Platform better,I added LCD panel(NL6448BC20-08) function. -For the convenience of debug, CONFIG_PERBOOT was supported. So you just -perss ENTER if you want to get a serial console in boot downcounting. -Then you can switch to LCD and serial console freely just typing -'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled. - -To get a LCD support u-boot,you can do the following: - -make distclean -make RPXlite_DW_LCD_config -make all - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The basic make commands could be: - -make RPXlite_DW_config -make RPXlite_DW_64_config -make RPXlite_DW_LCD_config -make RPXlite_DW_NVRAM_config - -BTW,you can combine the above features together and get a workable u-boot to meet your need. -For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type: - -make RPXlite_DW_NVRAM_64_LCD_config -make all - -So other combining make commands could be: - -make RPXlite_DW_NVRAM_64_config -make RPXlite_DW_NVRAM_LCD_config -make RPXlite_DW_64_LCD_config - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The boot process by "make RPXlite_DW_config" could be: - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -A word on the U-Boot enviroment variable setting and usage : - -In the beginning, you could just need very simple defult environment variable setting, -like[include/configs/RPXlite.h] : - -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -This is enough for kernel NFS test. But as debug process goes on, you would expect -to save some time on environment variable setting and u-boot/kernel updating. -So the default environment variable setting would become more complicated. Just like -the one I did in include/configs/RPXlite_DW.h. - -Two u-boot commands, ku and uu, should be careful to use. They were designed to update -kernel and u-boot image file respectively. You must tftp your image to default address -'100000' and then use them correctly. Yeah, you can create your own command to do this -job. :-) The example u-boot image updating process could be : - -u-boot>t 100000 RPXlite_DW_LCD.bin -Using SCC ETHERNET device -TFTP from server 172.16.115.6; our IP address is 172.16.115.7 -Filename 'RPXlite_DW_LCD.bin'. -Load address: 0x100000 -Loading: ############################# -done -Bytes transferred = 144700 (2353c hex) -u-boot>run uu -Un-Protect Flash Sectors 0-4 in Bank # 1 -Erase Flash Sectors 0-4 in Bank # 1 -.... done -Copy to Flash... done -ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2 -ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 - -ff000020: 31353a32 303a3238 29000000 00000000 15:20:28)....... -ff000030: 00000000 00000000 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: 00000000 00000000 00000000 00000000 ................ -ff000090: 00000000 00000000 00000000 00000000 ................ -ff0000a0: 00000000 00000000 00000000 00000000 ................ -ff0000b0: 00000000 00000000 00000000 00000000 ................ -ff0000c0: 00000000 00000000 00000000 00000000 ................ -ff0000d0: 00000000 00000000 00000000 00000000 ................ -ff0000e0: 00000000 00000000 00000000 00000000 ................ -ff0000f0: 00000000 00000000 00000000 00000000 ................ -u-boot updating finished -u-boot> - -Also for environment updating, 'run eu' could let you erase OLD default environment variable -and then use the working u-boot environment setting. - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Finally, if you want to keep the serial port to possible debug on spot for deployment, you -just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string -defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot. - -I'd like to extend my heartfelt gratitute to kind people for helping me work it out. -I would particually thank Wolfgang Denk for his nice help. - -Enjoy, - -Sam Song, samsongshu@yahoo.com.cn -Institute of Electrical Machinery and Controls -Shanghai University - -Oct. 11, 2004 diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c deleted file mode 100644 index 29d52dec8c..0000000000 --- a/board/RPXlite_dw/RPXlite_dw.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2004 - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Sam Song - * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW - * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz - * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75. - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ -static long int dram_size (long int, long int *, long int); -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */ - _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35, - _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, - /* INIT sequence RAM WORDS - * SDRAM Initialization (offset 0x36 in UPMA RAM) - * The above definition uses the remaining space - * to establish an initialization sequence, - * which is executed by a RUN command. - * The sequence is COMMAND INHIBIT(NOP),Precharge, - * Load Mode Register,NOP,Auto Refresh. - */ - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite_DW\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR ; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - /*Disable Periodic timer A. */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */ - - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - /*Enable Periodic timer A */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 9 column mode - */ - - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); - - /* - * Final mapping: - */ - - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - - udelay (1000); - - return (size9); -} - -void rpxlite_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c deleted file mode 100644 index c8de5ef5ee..0000000000 --- a/board/RPXlite_dw/flash.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -/* Yes,Yoo.They do use other FLASH for the board. - * - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * U-Boot port on RPXlite DW version board - * - * By now,it uses 4 AM29DL323DB90VI devices(4x8bit). - * The total FLASH has 16MB(4x4MB). - * I just made some necessary changes on the basis of Wolfgang and Yoo's job. - * - * June 8, 2004 */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions vu_long : volatile unsigned long IN include/common.h - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - /* If Monitor is in the cope of FLASH,then - * protect this area by default in case for - * other occupation. [SAM] */ - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, - &flash_info[0]); -#endif - flash_info[0].size = size_b0; - return (size_b0); -} - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000); - } - } else { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n"); - break; - /* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */ - default: printf ("Unknown Chip Type\n"); - break; - } - printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */ - info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */ - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /* Size doubled by yooth */ - break; /* => 4 MB */ - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* => 16 MB(4x4MB) */ - /* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013 - * AMD_ID_DL323B could be found in .[SAM] - * So we could get : flash_id = 0x00000013. - * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1, - * it means bottom boot flash. GOOD IDEA! [SAM] - */ - - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - /* info->protect[i] = addr[4] & 1 ; */ - /* Mask it for disorder FLASH protection **[Sam]** */ - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - return (info->size); -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/RPXlite_dw/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug deleted file mode 100644 index 0ea27e8759..0000000000 --- a/board/RPXlite_dw/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RRvision/Makefile b/board/RRvision/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/RRvision/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c deleted file mode 100644 index d94e238b43..0000000000 --- a/board/RRvision/RRvision.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Always return 1 (no second DRAM bank). - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: RRvision "); - - for (i=0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long reg; - long int size8, size9; - long int size = 0; - - upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 the SDRAM bank 2 at physical address 0. - */ - memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/RRvision/flash.c b/board/RRvision/flash.c deleted file mode 100644 index 146a923e11..0000000000 --- a/board/RRvision/flash.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define DEBUG - -#include -#include - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: puts ("AMD "); break; - case FLASH_MAN_FUJ: puts ("FUJITSU "); break; - default: puts ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: puts ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - puts ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - puts ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - switch (value) { - case AMD_ID_LV400B: - case AMD_ID_LV800B: - case AMD_ID_LV160B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV400T: - case AMD_ID_LV800T: - case AMD_ID_LV160T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_LV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - case AMD_ID_LV320T: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The last 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < (info->sector_count - 8)) - ? 2 * (64 << 10) - : 2 * ( 8 << 10); - } - break; - default: - return (0); - break; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - puts ("- missing\n"); - } else { - puts ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - puts ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - puts ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - puts (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds deleted file mode 100644 index 9470a24e74..0000000000 --- a/board/RRvision/u-boot.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - . = env_offset; - common/env_embedded.o (.ppcenv) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RRvision/video_ad7179.h b/board/RRvision/video_ad7179.h deleted file mode 100644 index 1fc1ef4407..0000000000 --- a/board/RRvision/video_ad7179.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2003 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define VIDEO_ENCODER_NAME "Analog Devices AD7179" - -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */ -#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ - -#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ -#undef VIDEO_MODE_RGB -#define VIDEO_MODE_BPP 16 - -#ifdef VIDEO_MODE_PAL -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 576 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 480 -#else -#error "NTSC mode is not supported" -#endif - -static unsigned char video_encoder_data[] = { - 0x05, /* Mode Register 0 */ - 0x11, /* Mode Register 1 */ - 0x20, /* Mode Register 2 */ - 0x0C, /* Mode Register 3 */ - 0x01, /* Mode Register 4 */ - 0x00, /* Reserved */ - 0x00, /* Reserved */ - 0x04, /* Timing Register 0 */ - 0x00, /* Timing Register 1 */ - 0xCB, /* Subcarrier Frequency Register 0 */ - 0x0A, /* Subcarrier Frequency Register 1 */ - 0x09, /* Subcarrier Frequency Register 2 */ - 0x2A, /* Subcarrier Frequency Register 3 */ - 0x00, /* Subcarrier Phase */ - 0x00, /* Closed Captioning Ext Reg 0 */ - 0x00, /* Closed Captioning Ext Reg 1 */ - 0x00, /* Closed Captioning Reg 0 */ - 0x00, /* Closed Captioning Reg 1 */ - 0x00, /* Pedestal Control Reg 0 */ - 0x00, /* Pedestal Control Reg 1 */ - 0x00, /* Pedestal Control Reg 2 */ - 0x00, /* Pedestal Control Reg 3 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00 /* Teletext Req. Control Reg */ -} ; diff --git a/board/Seagate/dockstar/Kconfig b/board/Seagate/dockstar/Kconfig new file mode 100644 index 0000000000..b50cd3b7f6 --- /dev/null +++ b/board/Seagate/dockstar/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DOCKSTAR + +config SYS_BOARD + default "dockstar" + +config SYS_VENDOR + default "Seagate" + +config SYS_CONFIG_NAME + default "dockstar" + +endif diff --git a/board/Seagate/dockstar/MAINTAINERS b/board/Seagate/dockstar/MAINTAINERS new file mode 100644 index 0000000000..f259e58ae6 --- /dev/null +++ b/board/Seagate/dockstar/MAINTAINERS @@ -0,0 +1,6 @@ +DOCKSTAR BOARD +M: Eric Cooper +S: Maintained +F: board/Seagate/dockstar/ +F: include/configs/dockstar.h +F: configs/dockstar_defconfig diff --git a/board/Seagate/dockstar/Makefile b/board/Seagate/dockstar/Makefile index 1754c81733..2ef5093f06 100644 --- a/board/Seagate/dockstar/Makefile +++ b/board/Seagate/dockstar/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := dockstar.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dockstar.o diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index ff6a6a09ed..83ab1bc32d 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #include #include @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(DOCKSTAR_OE_VAL_LOW, - DOCKSTAR_OE_VAL_HIGH, - DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); + mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW, + DOCKSTAR_OE_VAL_HIGH, + DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -96,7 +96,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR; /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } @@ -143,7 +143,7 @@ void reset_phy(void) static void set_leds(u32 leds, u32 blinking) { - struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE; + struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; u32 oe = readl(&r->oe) | BOTH_LEDS; writel(oe & ~leds, &r->oe); /* active low */ u32 bl = readl(&r->blink_en) & ~BOTH_LEDS; diff --git a/board/Seagate/goflexhome/Kconfig b/board/Seagate/goflexhome/Kconfig new file mode 100644 index 0000000000..0cbeaf7ca7 --- /dev/null +++ b/board/Seagate/goflexhome/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GOFLEXHOME + +config SYS_BOARD + default "goflexhome" + +config SYS_VENDOR + default "Seagate" + +config SYS_CONFIG_NAME + default "goflexhome" + +endif diff --git a/board/Seagate/goflexhome/MAINTAINERS b/board/Seagate/goflexhome/MAINTAINERS new file mode 100644 index 0000000000..6d6a1ff4e3 --- /dev/null +++ b/board/Seagate/goflexhome/MAINTAINERS @@ -0,0 +1,6 @@ +GOFLEXHOME BOARD +M: Suriyan Ramasami +S: Maintained +F: board/Seagate/goflexhome/ +F: include/configs/goflexhome.h +F: configs/goflexhome_defconfig diff --git a/board/Seagate/goflexhome/Makefile b/board/Seagate/goflexhome/Makefile index d97eb02186..e56230c71f 100644 --- a/board/Seagate/goflexhome/Makefile +++ b/board/Seagate/goflexhome/Makefile @@ -12,24 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := goflexhome.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := goflexhome.o diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index a6598e9c81..1f4fb92494 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include #include @@ -83,9 +83,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(GOFLEXHOME_OE_VAL_LOW, - GOFLEXHOME_OE_VAL_HIGH, - GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); + mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW, + GOFLEXHOME_OE_VAL_HIGH, + GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -98,7 +98,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME; /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } @@ -149,7 +149,7 @@ static void set_leds(u32 leds, u32 blinking) u32 oe; u32 bl; - r = (struct kwgpio_registers *)KW_GPIO1_BASE; + r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; oe = readl(&r->oe) | BOTH_LEDS; writel(oe & ~leds, &r->oe); /* active low */ bl = readl(&r->blink_en) & ~BOTH_LEDS; diff --git a/board/Seagate/nas220/Kconfig b/board/Seagate/nas220/Kconfig new file mode 100644 index 0000000000..0fa529cde1 --- /dev/null +++ b/board/Seagate/nas220/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NAS220 + +config SYS_BOARD + default "nas220" + +config SYS_VENDOR + default "Seagate" + +config SYS_CONFIG_NAME + default "nas220" + +endif diff --git a/board/Seagate/nas220/MAINTAINERS b/board/Seagate/nas220/MAINTAINERS new file mode 100644 index 0000000000..f2df7ea64f --- /dev/null +++ b/board/Seagate/nas220/MAINTAINERS @@ -0,0 +1,6 @@ +NAS220 BOARD +M: Evgeni Dobrev +S: Maintained +F: board/Seagate/nas220/ +F: include/configs/nas220.h +F: configs/nas220_defconfig diff --git a/board/Seagate/nas220/Makefile b/board/Seagate/nas220/Makefile new file mode 100644 index 0000000000..9de73e6f5e --- /dev/null +++ b/board/Seagate/nas220/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Evgeni Dobrev +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nas220.o diff --git a/board/Seagate/nas220/kwbimage.cfg b/board/Seagate/nas220/kwbimage.cfg new file mode 100644 index 0000000000..dbbfb9c020 --- /dev/null +++ b/board/Seagate/nas220/kwbimage.cfg @@ -0,0 +1,151 @@ +# +# Copyright (C) 2014 Evgeni Dobrev +# +# Based on sheevaplug/kwbimage.cfg originally written by +# Prafulla Wadaskar +# (C) Copyright 2009 +# Marvell Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0200 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000819 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + + +DATA 0xFFD01410 0x0000000d # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 0 +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +DATA 0xffd01620 0x00465000 + +# End of Header extension +DATA 0x0 0x0 + diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c new file mode 100644 index 0000000000..d9a06273a3 --- /dev/null +++ b/board/Seagate/nas220/nas220.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2014 Evgeni Dobrev + * + * Based on sheevaplug.c originally written by + * Prafulla Wadaskar + * (C) Copyright 2009 + * Marvell Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + */ + mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH, + NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_SPI_SCn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP13_GPIO, + MPP14_GPIO, + MPP15_SATA0_ACTn, + MPP16_SATA1_ACTn, + MPP17_SATA0_PRESENTn, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NAS220; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { + printf("Err..%s could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/a3000/Makefile b/board/a3000/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/a3000/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/a3000/README b/board/a3000/README deleted file mode 100644 index f0e92c543d..0000000000 --- a/board/a3000/README +++ /dev/null @@ -1,17 +0,0 @@ -U-Boot for Artis SBC-A3000 ---------------------------- - -Artis SBC-A3000 has one flash socket that the user uses Intel 28F128J3A (16MB) -or 28F064J3A (8MB) chips. - -In board's notation, bank 0 is the one at the address of 0xFF000000. -bank 1 is the one at the address of 0xFF800000 - -On power-up the processor jumps to the address of 0xFFF00100, the last -megabyte of the bank 0 of flash. - -Thus, U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the address of 0xFFFE0000. - -There is a National ns83815 10/100M ethernet controller on-board. diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c deleted file mode 100644 index 3e2f6b0f03..0000000000 --- a/board/a3000/a3000.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * Modified during 2003 by - * Ken Chou, kchou@ieee.org - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -int checkboard (void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; - -} - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_a3000_config_table[] = { - /* vendor, device, class */ - /* bus, dev, func */ - { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */ - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */ - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */ - pci_cfgfunc_config_device, { PCI_ENET2_IOADDR, - PCI_ENET2_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */ - pci_cfgfunc_config_device, { PCI_ENET3_IOADDR, - PCI_ENET3_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_a3000_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/a3000/flash.c b/board/a3000/flash.c deleted file mode 100644 index f2dd3c2f17..0000000000 --- a/board/a3000/flash.c +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - - -/*---------------------------------------------------------------------*/ -#define DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data (flash_info_t *info, uchar *dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#define BS(b) (b) -#define BYTEME(x) ((x) & 0xFF) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS; - unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN); - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE); - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - size = 0; - DEBUGF("## Final Flash bank sizes: "); - for (i=0; iflash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; /* 128k per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - -#if 1 - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -#endif - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ - vu_char manuf, device; - - addr[0] = BS(0x90); - manuf = BS(addr[0]); - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, manuf); - - switch (manuf) { - case BYTEME(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case BYTEME(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case BYTEME(SST_MANUFACT): - info->flash_id = FLASH_MAN_SST; - break; - case BYTEME(STM_MANUFACT): - info->flash_id = FLASH_MAN_STM; - break; - case BYTEME(INTEL_MANUFACT): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ - return 0; /* no or unknown flash */ - } - - device = BS(addr[2]); /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), device); - - switch (device) { - case BYTEME(INTEL_ID_28F320J3A): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case BYTEME(INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case BYTEME(INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ - return 0; /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = BS(0xFF); /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (vu_char *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x50); /* clear status register */ - *addr = BS(0x20); /* erase setup */ - *addr = BS(0xD0); /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = BS(0xB0); /* suspend erase */ - *addr = BS(0xFF); /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = BS(0xFF); /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 1 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - uchar *wp = (uchar *)addr; - int rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - while (cnt > 0) { - if ((rc = write_data(info, wp, *src)) != 0) { - return rc; - } - wp++; - src++; - cnt--; - } - - return cnt; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, uchar *dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((BS(*addr) & data) != data) { - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x40); /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - start = get_timer (0); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = BS(0xFF); /* restore read mode */ - return 1; - } - } - - *addr = BS(0xFF); /* restore read mode */ - - return 0; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/a3m071/Kconfig b/board/a3m071/Kconfig new file mode 100644 index 0000000000..444c450d8a --- /dev/null +++ b/board/a3m071/Kconfig @@ -0,0 +1,9 @@ +if TARGET_A3M071 + +config SYS_BOARD + default "a3m071" + +config SYS_CONFIG_NAME + default "a3m071" + +endif diff --git a/board/a3m071/MAINTAINERS b/board/a3m071/MAINTAINERS new file mode 100644 index 0000000000..975107d2c0 --- /dev/null +++ b/board/a3m071/MAINTAINERS @@ -0,0 +1,7 @@ +A3M071 BOARD +M: Stefan Roese +S: Maintained +F: board/a3m071/ +F: include/configs/a3m071.h +F: configs/a3m071_defconfig +F: configs/a4m2k_defconfig diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile index 5d2e4d162b..4e31e33936 100644 --- a/board/a3m071/Makefile +++ b/board/a3m071/Makefile @@ -2,24 +2,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := a3m071.o diff --git a/board/a3m071/README b/board/a3m071/README index a0fe832fb2..112c47b60d 100644 --- a/board/a3m071/README +++ b/board/a3m071/README @@ -57,13 +57,13 @@ the following command: => fdt print 5. Save fdt to NOR flash: -=> erase fc060000 fc07ffff -=> cp.b 1800000 fc060000 10000 +=> erase fc180000 fc07ffff +=> cp.b 1800000 fc180000 10000 All this can be integrated into an environment command: -=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip2 addtty; \ - fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc060000 fc07ffff; \ - cp.b 1800000 fc060000 10000' +=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \ + fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \ + cp.b 1800000 fc180000 10000' => saveenv After this, only "run upd_fdt" needs to get called to load, patch diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index 7aeefb29a9..ee1681b5db 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -392,9 +392,11 @@ int misc_init_r(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t * bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ @@ -412,7 +414,8 @@ int spl_start_uboot(void) env_init(); getenv_f("boot_os", s, sizeof(s)); - if ((s != NULL) && (strcmp(s, "yes") == 0)) + if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' || + *s == 't' || *s == 'T')) return 0; return 1; diff --git a/board/a4m072/Kconfig b/board/a4m072/Kconfig new file mode 100644 index 0000000000..ba5447fb9a --- /dev/null +++ b/board/a4m072/Kconfig @@ -0,0 +1,9 @@ +if TARGET_A4M072 + +config SYS_BOARD + default "a4m072" + +config SYS_CONFIG_NAME + default "a4m072" + +endif diff --git a/board/a4m072/MAINTAINERS b/board/a4m072/MAINTAINERS new file mode 100644 index 0000000000..83dc59e87f --- /dev/null +++ b/board/a4m072/MAINTAINERS @@ -0,0 +1,6 @@ +A4M072 BOARD +M: Sergei Poselenov +S: Maintained +F: board/a4m072/ +F: include/configs/a4m072.h +F: configs/a4m072_defconfig diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile index 3acd06bba7..2a40e5799e 100644 --- a/board/a4m072/Makefile +++ b/board/a4m072/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := a4m072.o diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c index d3d4c181af..c5d161bca3 100644 --- a/board/a4m072/a4m072.c +++ b/board/a4m072/a4m072.c @@ -171,10 +171,11 @@ void pci_init_board(void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/abilis/tb100/Kconfig b/board/abilis/tb100/Kconfig new file mode 100644 index 0000000000..904a92c7a0 --- /dev/null +++ b/board/abilis/tb100/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TB100 + +config SYS_CPU + default "arc700" + +config SYS_BOARD + default "tb100" + +config SYS_VENDOR + default "abilis" + +config SYS_CONFIG_NAME + default "tb100" + +endif diff --git a/board/abilis/tb100/MAINTAINERS b/board/abilis/tb100/MAINTAINERS new file mode 100644 index 0000000000..f08c3fe350 --- /dev/null +++ b/board/abilis/tb100/MAINTAINERS @@ -0,0 +1,6 @@ +TB100 BOARD +M: Alexey Brodkin +S: Maintained +F: board/abilis/tb100/ +F: include/configs/tb100.h +F: configs/tb100_defconfig diff --git a/board/abilis/tb100/Makefile b/board/abilis/tb100/Makefile new file mode 100644 index 0000000000..4f273b322b --- /dev/null +++ b/board/abilis/tb100/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += tb100.o diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c new file mode 100644 index 0000000000..ff3632f6c0 --- /dev/null +++ b/board/abilis/tb100/tb100.c @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void reset_cpu(ulong addr) +{ +#define CRM_SWRESET 0xff101044 + writel(0x1, (void *)CRM_SWRESET); +} + +int board_eth_init(bd_t *bis) +{ + if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0) + return 1; + + return 0; +} diff --git a/board/actux1/Makefile b/board/actux1/Makefile deleted file mode 100644 index 9e581e3508..0000000000 --- a/board/actux1/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := actux1.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c deleted file mode 100644 index 03ccd936b4..0000000000 --- a/board/actux1/actux1.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "actux1_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: HwRel */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - - /* Setup GPIOs for PCI INTA */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA); - - /* Setup GPIOs for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - - ACTUX1_LED1(2); - ACTUX1_LED2(2); - ACTUX1_LED3(0); - ACTUX1_LED4(0); - ACTUX1_LED5(0); - ACTUX1_LED6(0); - ACTUX1_LED7(0); - - ACTUX1_HS(ACTUX1_HS_DCD); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-1 rev."); - putc(ACTUX1_BOARDREL + 'A' - 1); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX1_BOARDREL; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -void reset_phy(void) -{ - u16 id1, id2; - - /* initialize the PHY */ - miiphy_reset("NPE0", CONFIG_PHY_ADDR); - - miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); - miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); - - id2 &= 0xFFF0; /* mask out revision bits */ - - if (id1 == 0x13 && id2 == 0x78e0) { - /* - * LXT971/LXT972 PHY: set LED outputs: - * LED1(green) = Link/ACT, - * LED2 (unused) = LINK, - * LED3(red) = Coll - */ - miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); - } else if (id1 == 0x143 && id2 == 0xbc30) { - /* BCM5241: default values are OK */ - } else - printf("unknown ethernet PHY ID: %x %x\n", id1, id2); -} diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h deleted file mode 100644 index 5627f24796..0000000000 --- a/board/actux1/actux1_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-1 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX1_HW_H -#define _ACTUX1_HW_H - -/* 0 = LED off,1 = green, 2 = red, 3 = orange */ -#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3) -#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4) -#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5) -#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) -#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) -#define ACTUX1_HS_DCD 0x01 -#define ACTUX1_HS_DSR 0x02 - -#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) - -/* GPIO settings */ -#define CONFIG_SYS_GPIO_PCI1_INTA 2 -#define CONFIG_SYS_GPIO_PCI2_INTA 3 -#define CONFIG_SYS_GPIO_I2C_SDA 4 -#define CONFIG_SYS_GPIO_I2C_SCL 5 -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds deleted file mode 100644 index a656fa99d1..0000000000 --- a/board/actux1/u-boot.lds +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/libnet.o(.text*) - board/actux1/libactux1.o(.text*) - arch/arm/cpu/ixp/libixp.o(.text*) - drivers/input/libinput.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/board/actux2/Makefile b/board/actux2/Makefile deleted file mode 100644 index dcb2bdabac..0000000000 --- a/board/actux2/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := actux2.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c deleted file mode 100644 index e578cd0996..0000000000 --- a/board/actux2/actux2.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include - -#include "actux2_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: IPAC-X */ - writel(0x94d10013, IXP425_EXP_CS1); - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: HW release register */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); - - /* Setup GPIOs for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); - - /* Setup GPIOs for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); - - ACTUX2_LED1(1); - ACTUX2_LED2(0); - ACTUX2_LED3(0); - ACTUX2_LED4(0); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-2 rev."); - putc(ACTUX2_BOARDREL + 'A' - 1); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX2_BOARDREL; -} - -void reset_phy(void) -{ - /* init IcPlus IP175C ethernet switch to native IP175C mode */ - miiphy_write("NPE0", 29, 31, 0x175C); -} diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h deleted file mode 100644 index 57c6fa7076..0000000000 --- a/board/actux2/actux2_hw.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX2_HW_H -#define _ACTUX2_HW_H - -/* 0 = LED off,1 = green, 2 = red, 3 = orange */ -#define ACTUX2_LED1(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX2_LED2(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX2_LED3(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX2_LED4(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3) - -#define ACTUX2_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX2_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) -#define ACTUX2_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_DBGINT 0 -#define CONFIG_SYS_GPIO_ETHINT 1 -#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */ -#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */ -#define CONFIG_SYS_GPIO_UNUSED4 4 -#define CONFIG_SYS_GPIO_UNUSED5 5 -#define CONFIG_SYS_GPIO_DSR 6 /* Out */ -#define CONFIG_SYS_GPIO_DCD 7 /* Out */ -#define CONFIG_SYS_GPIO_IPAC_INT 8 -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds deleted file mode 100644 index 7a1717640a..0000000000 --- a/board/actux2/u-boot.lds +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/libnet.o(.text*) - board/actux2/libactux2.o(.text*) - arch/arm/cpu/ixp/libixp.o(.text*) - drivers/input/libinput.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/board/actux3/Makefile b/board/actux3/Makefile deleted file mode 100644 index effa9a1e91..0000000000 --- a/board/actux3/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := actux3.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c deleted file mode 100644 index 09c803ccd4..0000000000 --- a/board/actux3/actux3.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "actux3_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: IPAC-X */ - writel(0x94d10013, IXP425_EXP_CS1); - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: Release/Option register */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN); - - /* - * Setup GPIO's for Interrupt inputs - */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); - - /* - * Setup GPIO's for 33MHz clock output - */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - /* we need a minimum PCI reset pulse width after enabling the clock */ - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); - - ACTUX3_LED1_RT(1); - ACTUX3_LED1_GN(0); - ACTUX3_LED2_RT(0); - ACTUX3_LED2_GN(0); - ACTUX3_LED3_RT(0); - ACTUX3_LED3_GN(0); - ACTUX3_LED4_GN(0); - ACTUX3_LED5_RT(0); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-3 rev."); - putc(ACTUX3_BOARDREL + 'A' - 1); - - if (i > 0) { - puts (", serial# "); - puts (buf); - } - putc('\n'); - - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX3_BOARDREL; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -void reset_phy(void) -{ - int i; - - /* initialize the PHY */ - miiphy_reset("NPE0", CONFIG_PHY_ADDR); - - /* all LED outputs = Link/Act */ - miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); - - /* - * The Marvell 88E6060 switch comes up with all ports disabled. - * set all ethernet switch ports to forwarding state - */ - for (i = 1; i <= 5; i++) - miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03); - -} diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h deleted file mode 100644 index f8acb4d060..0000000000 --- a/board/actux3/actux3_hw.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-3 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX3_HW_H -#define _ACTUX3_HW_H - -/* 0 = LED off,1 = ON */ -#define ACTUX3_LED1_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX3_LED1_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX3_LED2_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX3_LED2_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3) -#define ACTUX3_LED3_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4) -#define ACTUX3_LED3_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5) -#define ACTUX3_LED4_GN(a) writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) -#define ACTUX3_LED5_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) - -#define ACTUX3_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX3_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) -#define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) - -/* GPIO settings */ -#define CONFIG_SYS_GPIO_DBGINT 0 -#define CONFIG_SYS_GPIO_ETHINT 1 -#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */ -#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */ -#define CONFIG_SYS_GPIO_LED6_RT 4 /* Out */ -#define CONFIG_SYS_GPIO_LED6_GN 5 /* Out */ -#define CONFIG_SYS_GPIO_DSR 6 /* Out */ -#define CONFIG_SYS_GPIO_DCD 7 /* Out */ -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds deleted file mode 100644 index aadfdd2f57..0000000000 --- a/board/actux3/u-boot.lds +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/libnet.o(.text*) - board/actux3/libactux3.o(.text*) - arch/arm/cpu/ixp/libixp.o(.text*) - drivers/input/libinput.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/board/actux4/Makefile b/board/actux4/Makefile deleted file mode 100644 index b96d385300..0000000000 --- a/board/actux4/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := actux4.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c deleted file mode 100644 index 81c545884e..0000000000 --- a/board/actux4/actux4.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "actux4_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - writel(0xbd113c42, IXP425_EXP_CS1); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON); - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - - /* led not populated on board*/ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3); - - /* middle LED */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2); - - /* right LED */ - /* weak pulldown = LED weak on */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1); - - /* Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); - - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); - - /* Setup GPIO's for 33MHz clock output */ - writel(0x011001FF, IXP425_GPIO_GPCLKR); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - - udelay(10000); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - udelay(10000); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - udelay(10000); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - - return 0; -} - -/* Check Board Identity */ -int checkboard(void) -{ - puts("Board: AcTux-4\n"); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -/* - * Hardcoded flash setup: - * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus. - * Flash 1 is an Intel *16 flash using the CFI driver. - */ -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = 1; - info->chipwidth = 1; - info->interface = FLASH_CFI_X8; - return 1; - } else - return 0; -} diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h deleted file mode 100644 index b936376de9..0000000000 --- a/board/actux4/actux4_hw.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the AcTux-4 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX4_HW_H -#define _ACTUX4_HW_H - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_USBINTA 0 -#define CONFIG_SYS_GPIO_USBINTB 1 -#define CONFIG_SYS_GPIO_USBINTC 2 -#define CONFIG_SYS_GPIO_nPWRON 3 /* Out */ -#define CONFIG_SYS_GPIO_I2C_SCL 4 -#define CONFIG_SYS_GPIO_I2C_SDA 5 -#define CONFIG_SYS_GPIO_PCI_INTB 6 -#define CONFIG_SYS_GPIO_BUTTON1 7 -#define CONFIG_SYS_GPIO_LED1 8 /* Out */ -#define CONFIG_SYS_GPIO_RTCINT 9 -#define CONFIG_SYS_GPIO_LED2 10 /* Out */ -#define CONFIG_SYS_GPIO_PCI_INTA 11 -#define CONFIG_SYS_GPIO_IORST 12 /* Out */ -#define CONFIG_SYS_GPIO_LED3 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/adder/Makefile b/board/adder/Makefile deleted file mode 100644 index 07fa3f3a2f..0000000000 --- a/board/adder/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/adder/adder.c b/board/adder/adder.c deleted file mode 100644 index fa1a54b1a7..0000000000 --- a/board/adder/adder.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2004-2005 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Analogue&Micro Adder boards family. - * Tested on AdderII and Adder87x. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#if defined(CONFIG_OF_LIBFDT) - #include -#endif - -/* - * SDRAM is single Samsung K4S643232F-T70 chip (8MB) - * or single Micron MT48LC4M32B2TG-7 chip (16MB). - * Minimal CPU frequency is 40MHz. - */ -static uint sdram_table[] = { - /* Single read (offset 0x00 in UPM RAM) */ - 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00, - 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04, - - /* Burst read (offset 0x08 in UPM RAM) */ - 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44, - 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35, - 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35, - - /* Single write (offset 0x18 in UPM RAM) */ - 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47, - 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Burst write (offset 0x20 in UPM RAM) */ - 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Refresh (offset 0x30 in UPM RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Exception (offset 0x3C in UPM RAM) */ - 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 -}; - -phys_size_t initdram (int board_type) -{ - long int msize; - volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* Configure SDRAM refresh */ - memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ - - memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */ - udelay(200); - - /* Run precharge from location 0x15 */ - memctl->memc_mar = 0x0; - memctl->memc_mcr = 0x80002115; - udelay(200); - - /* Run 8 refresh cycles */ - memctl->memc_mcr = 0x80002830; - udelay(200); - - /* Run MRS pattern from location 0x16 */ - memctl->memc_mar = 0x88; - memctl->memc_mcr = 0x80002116; - udelay(200); - - memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ - memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; - - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE); - memctl->memc_or1 |= ~(msize - 1); - - return msize; -} - -int checkboard( void ) -{ - puts("Board: Adder"); -#if defined(CONFIG_MPC885_FAMILY) - puts("87x\n"); -#elif defined(CONFIG_MPC866_FAMILY) - puts("II\n"); -#endif - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - -} -#endif diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds deleted file mode 100644 index 38567d1c6e..0000000000 --- a/board/adder/u-boot.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/afeb9260/Kconfig b/board/afeb9260/Kconfig new file mode 100644 index 0000000000..6a5a93139d --- /dev/null +++ b/board/afeb9260/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AFEB9260 + +config SYS_BOARD + default "afeb9260" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "afeb9260" + +endif diff --git a/board/afeb9260/MAINTAINERS b/board/afeb9260/MAINTAINERS new file mode 100644 index 0000000000..337f3029cd --- /dev/null +++ b/board/afeb9260/MAINTAINERS @@ -0,0 +1,6 @@ +AFEB9260 BOARD +M: Sergey Lapin +S: Maintained +F: board/afeb9260/ +F: include/configs/afeb9260.h +F: configs/afeb9260_defconfig diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile index dcf926c75b..e0c3cd5422 100644 --- a/board/afeb9260/Makefile +++ b/board/afeb9260/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += afeb9260.o -COBJS-y += partition.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += afeb9260.o +obj-y += partition.o diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index e1b1c10d52..ea9575d413 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -67,8 +66,6 @@ static void afeb9260_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable EMAC clock */ @@ -94,20 +91,7 @@ static void afeb9260_macb_hw_init(void) pin_to_mask(AT91_PIN_PA28), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); - + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | diff --git a/board/ait/cam_enc_4xx/Kconfig b/board/ait/cam_enc_4xx/Kconfig new file mode 100644 index 0000000000..64e18f4e23 --- /dev/null +++ b/board/ait/cam_enc_4xx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CAM_ENC_4XX + +config SYS_BOARD + default "cam_enc_4xx" + +config SYS_VENDOR + default "ait" + +config SYS_CONFIG_NAME + default "cam_enc_4xx" + +endif diff --git a/board/ait/cam_enc_4xx/MAINTAINERS b/board/ait/cam_enc_4xx/MAINTAINERS new file mode 100644 index 0000000000..d6477c69d2 --- /dev/null +++ b/board/ait/cam_enc_4xx/MAINTAINERS @@ -0,0 +1,6 @@ +CAM_ENC_4XX BOARD +M: Heiko Schocher +S: Maintained +F: board/ait/cam_enc_4xx/ +F: include/configs/cam_enc_4xx.h +F: configs/cam_enc_4xx_defconfig diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile index 81eb7e72de..0d03ce003e 100644 --- a/board/ait/cam_enc_4xx/Makefile +++ b/board/ait/cam_enc_4xx/Makefile @@ -7,24 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cam_enc_4xx.o diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 7e1b16ac46..290dc1984a 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -8,15 +8,15 @@ */ #include +#include #include -#include #include #include #include #include #include #include -#include +#include #include #ifdef CONFIG_DAVINCI_MMC #include @@ -777,7 +777,7 @@ static void ait_menu_read_env(char *name) sprintf(output, "%s old: %s value: ", name, getenv(name)); memset(cbuf, 0, CONFIG_SYS_CBSIZE); - readret = readline_into_buffer(output, cbuf, 0); + readret = cli_readline_into_buffer(output, cbuf, 0); if (readret >= 0) { ret = setenv(name, cbuf); diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk index c280029a36..2022151309 100644 --- a/board/ait/cam_enc_4xx/config.mk +++ b/board/ait/cam_enc_4xx/config.mk @@ -7,11 +7,9 @@ # (mem base + reserved) # -#Provide at least 16MB spacing between us and the Linux Kernel image -CONFIG_SPL_PAD_TO := 12320 -UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg +UBL_CONFIG = $(srctree)/board/$(BOARDDIR)/ublimage.cfg ifndef CONFIG_SPL_BUILD -ALL-y += $(obj)u-boot.ubl +ALL-y += u-boot.ubl else # as SPL_TEXT_BASE is not page-aligned, we need for some # linkers the -n flag (Do not page align data), to prevent diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index fdfbfc38a9..f5c19df0d3 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -22,6 +22,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram @@ -48,5 +49,9 @@ SECTIONS } >.sram __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } } diff --git a/board/alphaproject/ap_sh4a_4a/Kconfig b/board/alphaproject/ap_sh4a_4a/Kconfig new file mode 100644 index 0000000000..4692851b26 --- /dev/null +++ b/board/alphaproject/ap_sh4a_4a/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AP_SH4A_4A + +config SYS_BOARD + default "ap_sh4a_4a" + +config SYS_VENDOR + default "alphaproject" + +config SYS_CONFIG_NAME + default "ap_sh4a_4a" + +endif diff --git a/board/alphaproject/ap_sh4a_4a/MAINTAINERS b/board/alphaproject/ap_sh4a_4a/MAINTAINERS new file mode 100644 index 0000000000..f24489d01d --- /dev/null +++ b/board/alphaproject/ap_sh4a_4a/MAINTAINERS @@ -0,0 +1,7 @@ +AP_SH4A_4A BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/alphaproject/ap_sh4a_4a/ +F: include/configs/ap_sh4a_4a.h +F: configs/ap_sh4a_4a_defconfig diff --git a/board/alphaproject/ap_sh4a_4a/Makefile b/board/alphaproject/ap_sh4a_4a/Makefile index a9ba17568e..486d0ac550 100644 --- a/board/alphaproject/ap_sh4a_4a/Makefile +++ b/board/alphaproject/ap_sh4a_4a/Makefile @@ -3,25 +3,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ap_sh4a_4a.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ap_sh4a_4a.o +obj-y += lowlevel_init.o diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c deleted file mode 100644 index eaa6b98025..0000000000 --- a/board/altera/common/AMDLV065D.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#if defined(CONFIG_NIOS) -#include -#else -#include -#endif - -#define SECTSZ (64 * 1024) -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------*/ -unsigned long flash_init (void) -{ - int i; - unsigned long addr; - flash_info_t *fli = &flash_info[0]; - - fli->size = CONFIG_SYS_FLASH_SIZE; - fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - - addr = CONFIG_SYS_FLASH_BASE; - for (i = 0; i < fli->sector_count; ++i) { - fli->start[i] = addr; - addr += SECTSZ; - fli->protect[i] = 1; - } - - return (CONFIG_SYS_FLASH_SIZE); -} -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - int erased; - unsigned long *addr; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - erased = 1; - addr = (unsigned long *) info->start[i]; - for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) { - if ( readl(addr++) != (unsigned long)-1) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - unsigned char *addr = (unsigned char *) info->start[0]; - unsigned char *addr2; - int prot, sect; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (unsigned char *) info->start[sect]; - writeb (0xaa, addr); - writeb (0x55, addr); - writeb (0x80, addr); - writeb (0xaa, addr); - writeb (0x55, addr); - writeb (0x30, addr2); - /* Now just wait for 0xff & provide some user - * feedback while we wait. - */ - start = get_timer (0); - while ( readb (addr2) != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - } - } - printf ("\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - - vu_char *cmd = (vu_char *) info->start[0]; - vu_char *dst = (vu_char *) addr; - unsigned char b; - ulong start; - - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((readb (dst) & b) != b) { - printf ("%02x : %02x\n", readb (dst), b); - return (2); - } - - writeb (0xaa, cmd); - writeb (0x55, cmd); - writeb (0xa0, cmd); - writeb (b, dst); - - /* Verify write */ - start = get_timer (0); - while (readb (dst) != b) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - dst++; - src++; - cnt--; - } - - return (0); -} diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c deleted file mode 100644 index 639170f7fd..0000000000 --- a/board/altera/common/epled.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* The LED port is configured as output only, so we - * must track the state manually. - */ -static led_id_t val = 0; - -void __led_init (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_set (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_toggle (led_id_t mask) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - val ^= mask; - writel (val, &pio->data); -} diff --git a/board/altera/common/flash.c b/board/altera/common/flash.c deleted file mode 100644 index 8f56a30b48..0000000000 --- a/board/altera/common/flash.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - unsigned long size; - int erased; - volatile unsigned char *flash; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned char *) info->start[i]; - for (k = 0; k < size; k++) { - if (*flash++ != 0xff) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", info->start[i], erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int prot, sect; - unsigned oldpri; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - for (sect = s_first; sect <= s_last; sect++) { - printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]); - } -#endif - - /* NOTE: disabling interrupts on Nios can be very bad since it - * also disables the LO_LIMIT exception. It's better here to - * set the interrupt priority to 3 & restore it when we're done. - */ - oldpri = ipri (3); - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - *addr = 0xaa; - *addr = 0x55; - *addr = 0x80; - *addr = 0xaa; - *addr = 0x55; - *addr2 = 0x30; - /* Now just wait for 0xff & provide some user - * feedback while we wait. Here we have to grant - * timer interrupts. Otherwise get_timer() can't - * work right. */ - ipri(oldpri); - start = get_timer (0); - while (*addr2 != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - oldpri = ipri (3); /* disallow non important irqs again */ - } - } - - printf ("\n"); - - /* Restore interrupt priority */ - ipri (oldpri); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - - vu_char *cmd = (vu_char *) info->start[0]; - vu_char *dst = (vu_char *) addr; - unsigned char b; - unsigned oldpri; - ulong start; - - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((*dst & b) != b) { - printf ("%02x : %02x\n", *dst, b); - return (2); - } - - /* Disable interrupts other than window underflow - * (interrupt priority 2) - */ - oldpri = ipri (3); - *cmd = 0xaa; - *cmd = 0x55; - *cmd = 0xa0; - *dst = b; - - /* Verify write */ - start = get_timer (0); - while (*dst != b) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - ipri (oldpri); - return 1; - } - } - dst++; - src++; - cnt--; - ipri (oldpri); - } - - return (0); -} diff --git a/board/altera/common/sevenseg.c b/board/altera/common/sevenseg.c deleted file mode 100644 index 7ae7ca2116..0000000000 --- a/board/altera/common/sevenseg.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * SPDX-License-Identifier: GPL-2.0+ - * - * common/sevenseg.c - * - * NIOS PIO based seven segment led support functions - */ - -#include -#include - -#ifdef CONFIG_SEVENSEG - -#define SEVENDEG_MASK_DP ((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP) - -#ifdef SEVENSEG_WRONLY /* emulate read access */ -#if (SEVENSEG_ACTIVE == 0) -static unsigned int sevenseg_portval = ~0; -#else -static unsigned int sevenseg_portval = 0; -#endif -#endif - -static int sevenseg_init_done = 0; - -static inline void __sevenseg_set_masked (unsigned int mask, int value) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - -#if (SEVENSEG_ACTIVE == 0) - if (value) - sevenseg_portval &= ~mask; - else - sevenseg_portval |= mask; -#else - if (value) - sevenseg_portval |= mask; - else - sevenseg_portval &= ~mask; -#endif - - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - -#if (SEVENSEG_ACTIVE == 0) - if (value) - piop->data &= ~mask; - else - piop->data |= mask; -#else - if (value) - piop->data |= mask; - else - piop->data &= ~mask; -#endif - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_toggle_masked (unsigned int mask) -{ - nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - - sevenseg_portval ^= mask; - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - - piop->data ^= mask; - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_set (unsigned int value) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - -#if (SEVENSEG_ACTIVE == 0) - sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP) - | ((~value) & (~SEVENDEG_MASK_DP)); -#else - sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP) - | (value); -#endif - - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - -#if (SEVENSEG_ACTIVE == 0) - piop->data = (piop->data & SEVENDEG_MASK_DP) - | ((~value) & (~SEVENDEG_MASK_DP)); -#else - piop->data = (piop->data & SEVENDEG_MASK_DP) - | (value); -#endif - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_init (void) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - - __sevenseg_set(0); - -#ifndef SEVENSEG_WRONLY /* setup direction */ - - piop->direction |= mask; - -#endif /* SEVENSEG_WRONLY */ -} - - -void sevenseg_set(int value) -{ - unsigned char digits[] = { - SEVENSEG_DIGITS_0, - SEVENSEG_DIGITS_1, - SEVENSEG_DIGITS_2, - SEVENSEG_DIGITS_3, - SEVENSEG_DIGITS_4, - SEVENSEG_DIGITS_5, - SEVENSEG_DIGITS_6, - SEVENSEG_DIGITS_7, - SEVENSEG_DIGITS_8, - SEVENSEG_DIGITS_9, - SEVENSEG_DIGITS_A, - SEVENSEG_DIGITS_B, - SEVENSEG_DIGITS_C, - SEVENSEG_DIGITS_D, - SEVENSEG_DIGITS_E, - SEVENSEG_DIGITS_F - }; - - if (!sevenseg_init_done) { - __sevenseg_init(); - sevenseg_init_done++; - } - - switch (value & SEVENSEG_MASK_CTRL) { - - case SEVENSEG_RAW: - __sevenseg_set( ( - (digits[((value & SEVENSEG_MASK_VAL) >> 4)] << 8) | - digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) ); - return; - break; /* paranoia */ - - case SEVENSEG_OFF: - __sevenseg_set(0); - __sevenseg_set_masked(SEVENDEG_MASK_DP, 0); - return; - break; /* paranoia */ - - case SEVENSEG_SET_DPL: - __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1); - return; - break; /* paranoia */ - - case SEVENSEG_SET_DPH: - __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1); - return; - break; /* paranoia */ - - case SEVENSEG_RES_DPL: - __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0); - return; - break; /* paranoia */ - - case SEVENSEG_RES_DPH: - __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0); - return; - break; /* paranoia */ - - case SEVENSEG_TOG_DPL: - __sevenseg_toggle_masked(SEVENSEG_DIGIT_DP); - return; - break; /* paranoia */ - - case SEVENSEG_TOG_DPH: - __sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8)); - return; - break; /* paranoia */ - - case SEVENSEG_LO: - case SEVENSEG_HI: - case SEVENSEG_STR: - default: - break; - } -} - -#endif /* CONFIG_SEVENSEG */ diff --git a/board/altera/common/sevenseg.h b/board/altera/common/sevenseg.h deleted file mode 100644 index 34348329ec..0000000000 --- a/board/altera/common/sevenseg.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * SPDX-License-Identifier: GPL-2.0+ - * - * common/sevenseg.h - * - * NIOS PIO based seven segment led support functions - */ - -#ifndef __DK1S10_SEVENSEG_H__ -#define __DK1S10_SEVENSEG_H__ - -#ifdef CONFIG_SEVENSEG - -/* - * 15 8 7 0 - * |-----------------------|--------| - * | controll value | value | - * ---------------------------------- - */ -#define SEVENSEG_RAW (int)(0) /* write out byte value (hex) */ -#define SEVENSEG_OFF (int)( 1 << 8) /* display switch off */ -#define SEVENSEG_SET_DPL (int)( 2 << 8) /* set dp low nibble */ -#define SEVENSEG_SET_DPH (int)( 3 << 8) /* set dp high nibble */ -#define SEVENSEG_RES_DPL (int)( 4 << 8) /* reset dp low nibble */ -#define SEVENSEG_RES_DPH (int)( 5 << 8) /* reset dp high nibble */ -#define SEVENSEG_TOG_DPL (int)( 6 << 8) /* toggle dp low nibble */ -#define SEVENSEG_TOG_DPH (int)( 7 << 8) /* toggle dp high nibble */ -#define SEVENSEG_LO (int)( 8 << 8) /* write out low nibble only */ -#define SEVENSEG_HI (int)( 9 << 8) /* write out high nibble only */ -#define SEVENSEG_STR (int)(10 << 8) /* write out a string */ - -#define SEVENSEG_MASK_VAL (0xff) /* only used by SEVENSEG_RAW */ -#define SEVENSEG_MASK_CTRL (~SEVENSEG_MASK_VAL) - -#ifdef SEVENSEG_DIGIT_HI_LO_EQUAL - -#define SEVENSEG_DIGITS_0 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F ) -#define SEVENSEG_DIGITS_1 ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C ) -#define SEVENSEG_DIGITS_2 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_3 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_4 ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_5 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_6 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_7 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C ) -#define SEVENSEG_DIGITS_8 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_9 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_A ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_B ( SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_C ( SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_D ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_E ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_F ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) - -#else /* !SEVENSEG_DIGIT_HI_LO_EQUAL */ -#error SEVENSEG: different pin asssignments not supported -#endif - -void sevenseg_set(int value); - -#endif /* CONFIG_SEVENSEG */ - -#endif /* __DK1S10_SEVENSEG_H__ */ diff --git a/board/altera/nios2-generic/Kconfig b/board/altera/nios2-generic/Kconfig new file mode 100644 index 0000000000..cd3d0980a7 --- /dev/null +++ b/board/altera/nios2-generic/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NIOS2_GENERIC + +config SYS_BOARD + default "nios2-generic" + +config SYS_VENDOR + default "altera" + +config SYS_CONFIG_NAME + default "nios2-generic" + +endif diff --git a/board/altera/nios2-generic/MAINTAINERS b/board/altera/nios2-generic/MAINTAINERS new file mode 100644 index 0000000000..9cbcba983b --- /dev/null +++ b/board/altera/nios2-generic/MAINTAINERS @@ -0,0 +1,6 @@ +NIOS2-GENERIC BOARD +M: Scott McNutt +S: Maintained +F: board/altera/nios2-generic/ +F: include/configs/nios2-generic.h +F: configs/nios2-generic_defconfig diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile index ceaf45eb47..5e4192c1e7 100644 --- a/board/altera/nios2-generic/Makefile +++ b/board/altera/nios2-generic/Makefile @@ -6,32 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o -COBJS-$(CONFIG_EPLED) += ../common/epled.o -COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o - -SOBJS-y := text_base.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := nios2-generic.o +obj-$(CONFIG_CMD_IDE) += ../common/cfide.o diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk index f9f317c440..a673525195 100644 --- a/board/altera/nios2-generic/config.mk +++ b/board/altera/nios2-generic/config.mk @@ -5,11 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# we get text_base from board config header, so do not use this -#CONFIG_SYS_TEXT_BASE = do-not-use-me - PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h index fd3ec9a8d8..cf75d35648 100644 --- a/board/altera/nios2-generic/custom_fpga.h +++ b/board/altera/nios2-generic/custom_fpga.h @@ -1,78 +1,89 @@ /* - * (C) Copyright 2010, Thomas Chou + * This header is generated by sopc2dts + * Sopc2dts is written by Walter Goossens + * in cooperation with the nios2 community * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file is generated by sopc-create-config-files. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CUSTOM_FPGA_H_ #define _CUSTOM_FPGA_H_ -/* generated from std_1c20.sopc */ - -/* cpu.data_master is a altera_nios2 */ -#define CONFIG_SYS_CLK_FREQ 50000000 -#define CONFIG_SYS_RESET_ADDR 0x00000000 -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 -#define CONFIG_SYS_ICACHE_SIZE 4096 -#define CONFIG_SYS_ICACHELINE_SIZE 32 -#define CONFIG_SYS_DCACHE_SIZE 2048 -#define CONFIG_SYS_DCACHELINE_SIZE 4 - -/* sdram.s1 is a altera_avalon_new_sdram_controller */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 - -/* uart1.s1 is a altera_avalon_uart */ -#define CONFIG_SYS_UART_BASE 0x82120840 -#define CONFIG_SYS_UART_FREQ 50000000 -#define CONFIG_SYS_UART_BAUD 115200 - -/* lan91c111.s1 is a altera_avalon_lan91c111 */ -#define CONFIG_SMC91111_BASE 0x82110300 -#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT - -/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */ -#define EPCS_CONTROLLER_REG_BASE 0x82100200 -#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE } -#define CONFIG_ALTERA_SPI -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO +/* generated from qsys_ghrd_3c120.sopcinfo */ + +/* Dumping slaves of cpu.data_master */ + +/* cpu.jtag_debug_module is a altera_nios2_qsys */ +#define CONFIG_SYS_CLK_FREQ 125000000 +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_DCACHELINE_SIZE 32 +#define CONFIG_SYS_ICACHELINE_SIZE 32 +#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020 +#define CONFIG_SYS_ICACHE_SIZE 32768 +#define CONFIG_SYS_RESET_ADDR 0xc2800000 +#define IO_REGION_BASE 0xE0000000 + +/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */ +/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */ + +/* ddr2_bot.s1 is a altmemddr2 */ +#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */ +/* Dumping slaves of pb_cpu_to_io.m0 */ + +/* timer_1ms.s1 is a altera_avalon_timer */ +#define CONFIG_SYS_TIMER_IRQ 11 +#define CONFIG_SYS_TIMER_FREQ 125000000 +#define CONFIG_SYS_TIMER_BASE 0xE8400000 + +/* sysid.control_slave is a altera_avalon_sysid_qsys */ +#define CONFIG_SYS_SYSID_BASE 0xE8004D40 /* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ -#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0 +#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50 + +/* tse_mac.control_port is a triple_speed_ethernet */ +#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048 +#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800 +#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400 +#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048 +#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000 +#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000 +#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000 +#define CONFIG_ALTERA_TSE +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18 +#define CONFIG_SYS_ALTERA_TSE_FLAGS 1 + +/* uart.s1 is a altera_avalon_uart */ +#define CONFIG_SYS_UART_BAUD 115200 +#define CONFIG_SYS_UART_BASE 0xE8004C80 +#define CONFIG_SYS_UART_FREQ 62500000 + +/* user_led_pio_8out.s1 is a altera_avalon_pio */ +#define USER_LED_PIO_8OUT_BASE 0xE8004CC0 -/* led_pio.s1 is a altera_avalon_pio */ -#define LED_PIO_BASE 0x82120870 -#define LED_PIO_WIDTH 8 -#define LED_PIO_RSTVAL 0x0 +/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */ +#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0 +#define USER_DIPSW_PIO_8IN_IRQ 8 -/* high_res_timer.s1 is a altera_avalon_timer */ -#define CONFIG_SYS_TIMER_BASE 0x82120820 -#define CONFIG_SYS_TIMER_IRQ 3 -#define CONFIG_SYS_TIMER_FREQ 50000000 +/* user_pb_pio_4in.s1 is a altera_avalon_pio */ +#define USER_PB_PIO_4IN_BASE 0xE8004D00 +#define USER_PB_PIO_4IN_IRQ 9 + +/* cfi_flash_64m.uas is a altera_generic_tristate_controller */ +#define CFI_FLASH_64M_BASE 0xE0000000 /* ext_flash.s1 is a altera_avalon_cfi_flash */ -#define CONFIG_SYS_FLASH_BASE 0x80000000 +#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 -#define CONFIG_SYS_SRAM_SIZE 0x00100000 - -/* sysid.control_slave is a altera_avalon_sysid */ -#define CONFIG_SYS_SYSID_BASE 0x821208b8 +#define CONFIG_SYS_MAX_FLASH_SECT 512 #endif /* _CUSTOM_FPGA_H_ */ diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c index 5c5b1b9148..834cbeb2d5 100644 --- a/board/altera/nios2-generic/nios2-generic.c +++ b/board/altera/nios2-generic/nios2-generic.c @@ -8,13 +8,14 @@ #include #include +#if defined(CONFIG_CFI_FLASH_MTD) #include +#endif #include #include -void text_base_hook(void); /* nop hook for text_base.S */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ + defined(CONFIG_CFI_FLASH_MTD) static void __early_flash_cmd_reset(void) { /* reset flash before we read env */ @@ -27,7 +28,6 @@ void early_flash_cmd_reset(void) int board_early_init_f(void) { - text_base_hook(); #ifdef CONFIG_ALTERA_PIO #ifdef LED_PIO_BASE altera_pio_init(LED_PIO_BASE, LED_PIO_WIDTH, 'o', @@ -35,7 +35,8 @@ int board_early_init_f(void) "led"); #endif #endif -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ + defined(CONFIG_CFI_FLASH_MTD) early_flash_cmd_reset(); #endif return 0; diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S deleted file mode 100644 index f236db13e5..0000000000 --- a/board/altera/nios2-generic/text_base.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * text_base - * - * (C) Copyright 2010, Thomas Chou - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include - -#ifdef CONFIG_SYS_MONITOR_BASE - .text - /* text base used in link script u-boot.lds */ - .global text_base - .equ text_base,CONFIG_SYS_MONITOR_BASE - /* dummy func to let linker include this file */ - .global text_base_hook -text_base_hook: - ret -#endif diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds deleted file mode 100644 index 9720d58584..0000000000 --- a/board/altera/nios2-generic/u-boot.lds +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -OUTPUT_FORMAT("elf32-littlenios2") -OUTPUT_ARCH(nios2) -ENTRY(_start) - -SECTIONS -{ - . = text_base; - .text : - { - arch/nios2/cpu/start.o (.text) - *(.text) - *(.text.*) - *(.gnu.linkonce.t*) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.gnu.linkonce.r*) - } - . = ALIGN (4); - _etext = .; - PROVIDE (etext = .); - - /* CMD TABLE - sandwich this in between text and data so - * the initialization code relocates the command table as - * well -- admittedly, this is just pure laziness ;-) - */ - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - /* INIT DATA sections - "Small" data (see the gcc -G option) - * is always gp-relative. Here we make all init data sections - * adjacent to simplify the startup code -- and provide - * the global pointer for gp-relative access. - */ - _data = .; - .data : - { - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - } - - . = ALIGN(16); - _gp = .; /* Global pointer addr */ - PROVIDE (gp = .); - - .sdata : - { - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - } - . = ALIGN(4); - - _edata = .; - PROVIDE (edata = .); - - /* UNINIT DATA - Small uninitialized data is first so it's - * adjacent to sdata and can be referenced via gp. The normal - * bss follows. We keep it adjacent to simplify init code. - */ - __bss_start = .; - .sbss (NOLOAD) : - { - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - } - . = ALIGN(4); - .bss (NOLOAD) : - { - *(.bss) - *(.bss.*) - *(.dynbss) - *(COMMON) - *(.scommon) - } - . = ALIGN(4); - __bss_end = .; - PROVIDE (end = .); - - /* DEBUG -- symbol table, string table, etc. etc. - */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/board/altera/socfpga/Kconfig b/board/altera/socfpga/Kconfig new file mode 100644 index 0000000000..fc42185a83 --- /dev/null +++ b/board/altera/socfpga/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SOCFPGA_CYCLONE5 + +config SYS_BOARD + default "socfpga" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga" + +config SYS_CONFIG_NAME + default "socfpga_cyclone5" + +endif diff --git a/board/altera/socfpga/MAINTAINERS b/board/altera/socfpga/MAINTAINERS new file mode 100644 index 0000000000..0482581921 --- /dev/null +++ b/board/altera/socfpga/MAINTAINERS @@ -0,0 +1,12 @@ +SOCFPGA BOARD +M: Dinh Nguyen +M: Chin-Liang See +S: Maintained +F: board/altera/socfpga/ +F: include/configs/socfpga_cyclone5.h +F: configs/socfpga_cyclone5_defconfig + +SOCRATES BOARD +M: Stefan Roese +S: Maintained +F: configs/socfpga_socrates_defconfig diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile new file mode 100644 index 0000000000..44baa0068c --- /dev/null +++ b/board/altera/socfpga/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga_cyclone5.o +obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c new file mode 100644 index 0000000000..b4b5ff8972 --- /dev/null +++ b/board/altera/socfpga/iocsr_config.c @@ -0,0 +1,657 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#include + +const unsigned long iocsr_scan_chain0_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x08020000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { + 0x000C0300, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00004010, + 0x01004000, + 0x01000000, + 0x00003004, + 0x00001004, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00800000, + 0x00000002, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { + 0x80040100, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C010040, + 0x00008000, + 0x18020080, + 0x00000000, + 0x08000000, + 0x00040020, + 0x06018060, + 0x00004000, + 0x0C010040, + 0x04010000, + 0x00000030, + 0x00000000, + 0x03004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x02000018, + 0x00006008, + 0x01802008, + 0x00001000, + 0x03004010, + 0x01004000, + 0x0100000C, + 0x00003004, + 0x00C01004, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { + 0x2C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00A28, + 0xA20D0000, + 0x24906808, + 0x00A28340, + 0xD000001A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00040, + 0xA20D0002, + 0x24906808, + 0x00A28340, + 0xD005141A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x000001C1, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x04510680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x8341D348, + 0x821A0124, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x40120800, + 0x00000070, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x001A1A1A, + 0x085506A0, + 0x0000E1D4, + 0x045506A0, + 0x0000E1D4, + 0x085506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x022A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x021541A8, + 0x00003875, + 0x011541A8, + 0x00003875, + 0x021541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0x38D612AF, + 0x86F8E38E, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x028A4320, + 0xEC2CB23D, + 0x8F5D1451, + 0xA47A88A2, + 0x0001A0E9, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x51EC2CB2, + 0xA28F5D14, + 0xE9A47A88, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x08AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h new file mode 100644 index 0000000000..490f109e4b --- /dev/null +++ b/board/altera/socfpga/iocsr_config.h @@ -0,0 +1,17 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_IOCSR_CONFIG_H_ +#define _PRELOADER_IOCSR_CONFIG_H_ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) + +#endif /*_PRELOADER_IOCSR_CONFIG_H_*/ diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c new file mode 100644 index 0000000000..8b09005b60 --- /dev/null +++ b/board/altera/socfpga/pinmux_config.c @@ -0,0 +1,214 @@ +/* This file is generated by Preloader Generator */ + +#include "pinmux_config.h" + +/* pin mux configuration data */ +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { + 0, /* EMACIO0 - Unused */ + 2, /* EMACIO1 - USB */ + 2, /* EMACIO2 - USB */ + 2, /* EMACIO3 - USB */ + 2, /* EMACIO4 - USB */ + 2, /* EMACIO5 - USB */ + 2, /* EMACIO6 - USB */ + 2, /* EMACIO7 - USB */ + 2, /* EMACIO8 - USB */ + 0, /* EMACIO9 - Unused */ + 2, /* EMACIO10 - USB */ + 2, /* EMACIO11 - USB */ + 2, /* EMACIO12 - USB */ + 2, /* EMACIO13 - USB */ + 0, /* EMACIO14 - N/A */ + 0, /* EMACIO15 - N/A */ + 0, /* EMACIO16 - N/A */ + 0, /* EMACIO17 - N/A */ + 0, /* EMACIO18 - N/A */ + 0, /* EMACIO19 - N/A */ + 3, /* FLASHIO0 - SDMMC */ + 3, /* FLASHIO1 - SDMMC */ + 3, /* FLASHIO2 - SDMMC */ + 3, /* FLASHIO3 - SDMMC */ + 0, /* FLASHIO4 - SDMMC */ + 0, /* FLASHIO5 - SDMMC */ + 0, /* FLASHIO6 - SDMMC */ + 0, /* FLASHIO7 - SDMMC */ + 0, /* FLASHIO8 - SDMMC */ + 3, /* FLASHIO9 - SDMMC */ + 3, /* FLASHIO10 - SDMMC */ + 3, /* FLASHIO11 - SDMMC */ + 3, /* GENERALIO0 - TRACE */ + 3, /* GENERALIO1 - TRACE */ + 3, /* GENERALIO2 - TRACE */ + 3, /* GENERALIO3 - TRACE */ + 3, /* GENERALIO4 - TRACE */ + 3, /* GENERALIO5 - TRACE */ + 3, /* GENERALIO6 - TRACE */ + 3, /* GENERALIO7 - TRACE */ + 3, /* GENERALIO8 - TRACE */ + 3, /* GENERALIO9 - SPIM0 */ + 3, /* GENERALIO10 - SPIM0 */ + 3, /* GENERALIO11 - SPIM0 */ + 3, /* GENERALIO12 - SPIM0 */ + 2, /* GENERALIO13 - CAN0 */ + 2, /* GENERALIO14 - CAN0 */ + 3, /* GENERALIO15 - I2C0 */ + 3, /* GENERALIO16 - I2C0 */ + 2, /* GENERALIO17 - UART0 */ + 2, /* GENERALIO18 - UART0 */ + 0, /* GENERALIO19 - N/A */ + 0, /* GENERALIO20 - N/A */ + 0, /* GENERALIO21 - N/A */ + 0, /* GENERALIO22 - N/A */ + 0, /* GENERALIO23 - N/A */ + 0, /* GENERALIO24 - N/A */ + 0, /* GENERALIO25 - N/A */ + 0, /* GENERALIO26 - N/A */ + 0, /* GENERALIO27 - N/A */ + 0, /* GENERALIO28 - N/A */ + 0, /* GENERALIO29 - N/A */ + 0, /* GENERALIO30 - N/A */ + 0, /* GENERALIO31 - N/A */ + 2, /* MIXED1IO0 - EMAC */ + 2, /* MIXED1IO1 - EMAC */ + 2, /* MIXED1IO2 - EMAC */ + 2, /* MIXED1IO3 - EMAC */ + 2, /* MIXED1IO4 - EMAC */ + 2, /* MIXED1IO5 - EMAC */ + 2, /* MIXED1IO6 - EMAC */ + 2, /* MIXED1IO7 - EMAC */ + 2, /* MIXED1IO8 - EMAC */ + 2, /* MIXED1IO9 - EMAC */ + 2, /* MIXED1IO10 - EMAC */ + 2, /* MIXED1IO11 - EMAC */ + 2, /* MIXED1IO12 - EMAC */ + 2, /* MIXED1IO13 - EMAC */ + 0, /* MIXED1IO14 - Unused */ + 3, /* MIXED1IO15 - QSPI */ + 3, /* MIXED1IO16 - QSPI */ + 3, /* MIXED1IO17 - QSPI */ + 3, /* MIXED1IO18 - QSPI */ + 3, /* MIXED1IO19 - QSPI */ + 3, /* MIXED1IO20 - QSPI */ + 0, /* MIXED1IO21 - GPIO */ + 0, /* MIXED2IO0 - N/A */ + 0, /* MIXED2IO1 - N/A */ + 0, /* MIXED2IO2 - N/A */ + 0, /* MIXED2IO3 - N/A */ + 0, /* MIXED2IO4 - N/A */ + 0, /* MIXED2IO5 - N/A */ + 0, /* MIXED2IO6 - N/A */ + 0, /* MIXED2IO7 - N/A */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; diff --git a/board/altera/socfpga/pinmux_config.h b/board/altera/socfpga/pinmux_config.h new file mode 100644 index 0000000000..f278f2b280 --- /dev/null +++ b/board/altera/socfpga/pinmux_config.h @@ -0,0 +1,54 @@ +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_PINMUX_CONFIG_H_ +#define _PRELOADER_PINMUX_CONFIG_H_ + +/* + * State of enabling for which IP connected out through the muxing. + * Value 1 mean the IP connection is muxed out + */ +#define CONFIG_HPS_EMAC0 (0) +#define CONFIG_HPS_EMAC1 (1) +#define CONFIG_HPS_USB0 (0) +#define CONFIG_HPS_USB1 (1) +#define CONFIG_HPS_NAND (0) +#define CONFIG_HPS_SDMMC (1) +#define CONFIG_HPS_QSPI (1) +#define CONFIG_HPS_UART0 (1) +#define CONFIG_HPS_UART1 (0) +#define CONFIG_HPS_TRACE (1) +#define CONFIG_HPS_I2C0 (1) +#define CONFIG_HPS_I2C1 (0) +#define CONFIG_HPS_I2C2 (0) +#define CONFIG_HPS_I2C3 (0) +#define CONFIG_HPS_SPIM0 (1) +#define CONFIG_HPS_SPIM1 (0) +#define CONFIG_HPS_SPIS0 (0) +#define CONFIG_HPS_SPIS1 (0) +#define CONFIG_HPS_CAN0 (1) +#define CONFIG_HPS_CAN1 (0) + +/* IP attribute value (which affected by pin muxing configuration) */ +#define CONFIG_HPS_SDMMC_BUSWIDTH (4) + +/* 1 if the pins are connected out */ +#define CONFIG_HPS_QSPI_CS0 (1) +#define CONFIG_HPS_QSPI_CS1 (0) +#define CONFIG_HPS_QSPI_CS2 (0) +#define CONFIG_HPS_QSPI_CS3 (0) + +/* UART */ +/* 1 means the pin is mux out or available */ +#define CONFIG_HPS_UART0_TX (1) +#define CONFIG_HPS_UART0_RX (1) +#define CONFIG_HPS_UART0_CTS (0) +#define CONFIG_HPS_UART0_RTS (0) +#define CONFIG_HPS_UART1_TX (0) +#define CONFIG_HPS_UART1_RX (0) +#define CONFIG_HPS_UART1_CTS (0) +#define CONFIG_HPS_UART1_RTS (0) + +/* Pin mux data */ +#define CONFIG_HPS_PINMUX_NUM (207) + +#endif /* _PRELOADER_PINMUX_CONFIG_H_ */ diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h new file mode 100644 index 0000000000..f0f59a9519 --- /dev/null +++ b/board/altera/socfpga/pll_config.h @@ -0,0 +1,121 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +/* PLL configuration data */ +/* Main PLL */ +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +/* + * To tell where is the clock source: + * 0 = MAINPLL + * 1 = PERIPHPLL + */ +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) + +/* Peripheral PLL */ +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) +/* + * To tell where is the VCOs source: + * 0 = EOSC1 + * 1 = EOSC2 + * 2 = F2S + */ +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +/* + * To tell where is the clock source: + * 0 = F2S_PERIPH_REF_CLK + * 1 = MAIN_CLK + * 2 = PERIPH_CLK + */ +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +/* SDRAM PLL */ +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz + * This if..else... is not required if generated by tools */ +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) +#else +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#endif /* CONFIG_SOCFPGA_ARRIA5 */ + +/* + * To tell where is the VCOs source: + * 0 = EOSC1 + * 1 = EOSC2 + * 2 = F2S + */ +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +/* Info for driver */ +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ 0 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000) +#else +#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) +#endif +#define CONFIG_HPS_CLK_EMAC0_HZ (250000000) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (400000000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (100000000) +#define CONFIG_HPS_CLK_CAN1_HZ (100000000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) + +#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c new file mode 100644 index 0000000000..459d82f351 --- /dev/null +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Print Board information + */ +int checkboard(void) +{ + puts("BOARD: Altera SoCFPGA Cyclone5 Board\n"); + return 0; +} + +/* + * Initialization function which happen at early stage of c code + */ +int board_early_init_f(void) +{ + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/* + * PHY configuration + */ +#ifdef CONFIG_PHY_MICREL_KSZ9021 +int board_phy_config(struct phy_device *phydev) +{ + int ret; + /* + * These skew settings for the KSZ9021 ethernet phy is required for ethernet + * to work reliably on most flavors of cyclone5 boards. + */ + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + if (ret) + return ret; + + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + if (ret) + return ret; + + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); + if (ret) + return ret; + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_GADGET +struct s3c_plat_otg_data socfpga_otg_data = { + .regs_otg = CONFIG_USB_DWC2_REG_ADDR, + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + return s3c_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile deleted file mode 100644 index 101fc7c71c..0000000000 --- a/board/altera/socfpga_cyclone5/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2010, Thomas Chou -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := socfpga_cyclone5.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c deleted file mode 100644 index 576066bef1..0000000000 --- a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Print CPU information - */ -int print_cpuinfo(void) -{ - puts("CPU : Altera SOCFPGA Platform\n"); - return 0; -} - -/* - * Print Board information - */ -int checkboard(void) -{ - puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); - return 0; -} - -/* - * Initialization function which happen at early stage of c code - */ -int board_early_init_f(void) -{ - return 0; -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - icache_enable(); - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - return 0; -} -#endif - -/* - * DesignWare Ethernet initialization - */ -/* We know all the init functions have been run now */ -int board_eth_init(bd_t *bis) -{ - return 0; -} diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig new file mode 100644 index 0000000000..033deaf7d6 --- /dev/null +++ b/board/amcc/acadia/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ACADIA + +config SYS_BOARD + default "acadia" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "acadia" + +endif diff --git a/board/amcc/acadia/MAINTAINERS b/board/amcc/acadia/MAINTAINERS new file mode 100644 index 0000000000..c16961fde8 --- /dev/null +++ b/board/amcc/acadia/MAINTAINERS @@ -0,0 +1,6 @@ +ACADIA BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/acadia/ +F: include/configs/acadia.h +F: configs/acadia_defconfig diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile index 06f5c6ac61..035f407275 100644 --- a/board/amcc/acadia/Makefile +++ b/board/amcc/acadia/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o -SOBJS = - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = acadia.o cmd_acadia.o memory.o pll.o diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 9c6deeabcf..2eb18df5e7 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -39,12 +39,10 @@ int board_early_init_f(void) { unsigned int reg; -#if !defined(CONFIG_NAND_U_BOOT) /* don't reinit PLL when booting via I2C bootstrap option */ mfsdr(SDR0_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); -#endif acadia_gpio_init(); diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 61bfea3fab..9673118857 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -17,7 +17,6 @@ extern void board_pll_init_f(void); -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { wr_val <<= 2; @@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val) return; } -#endif phys_size_t initdram(int board_type) { -#if defined(CONFIG_NAND_SPL) - u32 reg; - - /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR0_PINSTP, reg); - if (reg != 0xf0000000) - board_pll_init_f(); -#endif - -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; @@ -88,7 +76,6 @@ phys_size_t initdram(int board_type) /* Wait a short while, since for NAND booting this is too fast */ for (i=0; i<200000; i++) ; -#endif return (CONFIG_SYS_MBYTES_RAM << 20); } diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index d74b725ae5..d868582ba9 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -135,45 +135,3 @@ void board_pll_init_f(void) mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU__405EZ */ - -#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk(void) -{ - unsigned long cpr_plld; - unsigned long cpr_primad; - unsigned long primad_cpudv; - unsigned long pllFbkDiv; - unsigned long freqProcessor; - - /* - * Read PLL Mode registers - */ - mfcpr(CPR0_PLLD, cpr_plld); - - /* - * Read CPR_PRIMAD register - */ - mfcpr(CPR0_PRIMAD, cpr_primad); - - /* - * Determine CPU clock frequency - */ - primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) - primad_cpudv = 16; - - /* - * Determine FBK_DIV. - */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; - - freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; - - return (freqProcessor); -} -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds deleted file mode 100644 index 9a331c50a9..0000000000 --- a/board/amcc/acadia/u-boot-nand.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text*) - - /* Align to next NAND block */ - . = ALIGN(0x4000); - common/env_embedded.o (.ppcenv) - /* Keep some space here for redundant env and potential bad env blocks */ - . = ALIGN(0x10000); - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig new file mode 100644 index 0000000000..c0bd40aee7 --- /dev/null +++ b/board/amcc/bamboo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BAMBOO + +config SYS_BOARD + default "bamboo" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "bamboo" + +endif diff --git a/board/amcc/bamboo/MAINTAINERS b/board/amcc/bamboo/MAINTAINERS new file mode 100644 index 0000000000..4c8929ece7 --- /dev/null +++ b/board/amcc/bamboo/MAINTAINERS @@ -0,0 +1,6 @@ +BAMBOO BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/bamboo/ +F: include/configs/bamboo.h +F: configs/bamboo_defconfig diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile index 6a5464d597..4c0a1253f1 100644 --- a/board/amcc/bamboo/Makefile +++ b/board/amcc/bamboo/Makefile @@ -5,27 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = bamboo.o flash.o +extra-y += init.o diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 84bbacf4c5..c8d09636ab 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -16,7 +16,6 @@ void ext_bus_cntlr_init(void); void configure_ppc440ep_pins(void); int is_nand_selected(void); -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) /************************************************************************* * * Bamboo has one bank onboard sdram (plus DIMM) @@ -178,7 +177,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { 0, 0 }; -#endif #if 0 { /* GPIO Alternate1 Alternate2 Alternate3 */ @@ -440,15 +438,11 @@ int checkboard(void) phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) long dram_size; dram_size = spd_sdram(); return dram_size; -#else - return CONFIG_SYS_MBYTES_SDRAM << 20; -#endif } /*----------------------------------------------------------------------------+ @@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) { update_ndfc_ios(gpio_tab); - -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_CHIPSELGAT_EN1 | SDR0_CUST0_CHIPSELGAT_EN2); -#else - mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_CHIPSELGAT_EN0 | - SDR0_CUST0_CHIPSELGAT_EN2); -#endif - ndfc_selection_in_fpga(); } else diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index e85841a014..49f200aa0b 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -2,7 +2,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /*----------------------------------------------------------------------------+ diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index 408450c080..5c7c839079 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -4,7 +4,7 @@ * * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -32,12 +32,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G) -#else - tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G) - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) -#endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) @@ -58,31 +53,3 @@ tlbtab: tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG) tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds deleted file mode 100644 index 5e84369fe1..0000000000 --- a/board/amcc/bamboo/u-boot-nand.lds +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text*) - board/amcc/bamboo/init.o (.text*) - - /* Align to next NAND block */ - . = ALIGN(0x4000); - common/env_embedded.o (.ppcenv) - /* Keep some space here for redundant env and potential bad env blocks */ - . = ALIGN(0x10000); - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile deleted file mode 100644 index 289b3796ad..0000000000 --- a/board/amcc/bluestone/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -SOBJS := init.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c deleted file mode 100644 index 6520f75c68..0000000000 --- a/board/amcc/bluestone/bluestone.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Bluestone board support - * - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int board_early_init_f(void) -{ - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - /* - * Configure PFC (Pin Function Control) registers - * UART0: 2 pins - */ - mtsdr(SDR0_PFC1, 0x0000000); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Bluestone Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - return 0; -} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk deleted file mode 100644 index a947e82af7..0000000000 --- a/board/amcc/bluestone/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Applied Micro APM821XX Evaluation board. -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S deleted file mode 100644 index a1bf16804c..0000000000 --- a/board/amcc/bluestone/init.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* TLB 0 */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_RWX | SA_G) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G) - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, - AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, - CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) - tlbtab_end diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig new file mode 100644 index 0000000000..540d9b6235 --- /dev/null +++ b/board/amcc/bubinga/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BUBINGA + +config SYS_BOARD + default "bubinga" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "bubinga" + +endif diff --git a/board/amcc/bubinga/MAINTAINERS b/board/amcc/bubinga/MAINTAINERS new file mode 100644 index 0000000000..3299cc34e3 --- /dev/null +++ b/board/amcc/bubinga/MAINTAINERS @@ -0,0 +1,6 @@ +BUBINGA BOARD +#M: - +S: Maintained +F: board/amcc/bubinga/ +F: include/configs/bubinga.h +F: configs/bubinga_defconfig diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile index bea58a7cae..0e7ebcaedd 100644 --- a/board/amcc/bubinga/Makefile +++ b/board/amcc/bubinga/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = bubinga.o flash.o diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig new file mode 100644 index 0000000000..530a6efd60 --- /dev/null +++ b/board/amcc/canyonlands/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CANYONLANDS + +config SYS_BOARD + default "canyonlands" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "canyonlands" + +endif diff --git a/board/amcc/canyonlands/MAINTAINERS b/board/amcc/canyonlands/MAINTAINERS new file mode 100644 index 0000000000..52bf004f6c --- /dev/null +++ b/board/amcc/canyonlands/MAINTAINERS @@ -0,0 +1,8 @@ +CANYONLANDS BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/canyonlands/ +F: include/configs/canyonlands.h +F: configs/arches_defconfig +F: configs/canyonlands_defconfig +F: configs/glacier_defconfig diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile index 415ec3298f..ba0765fe99 100644 --- a/board/amcc/canyonlands/Makefile +++ b/board/amcc/canyonlands/Makefile @@ -5,29 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -SOBJS := init.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := canyonlands.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +extra-y += init.o diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index cc36f4587c..c5cc4ffa69 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -16,6 +16,7 @@ #include #include #include +#include extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -188,7 +189,7 @@ int board_early_init_f(void) } #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) -int usb_board_init(void) +int board_usb_init(int index, enum usb_init_type init) { struct board_bcsr *bcsr_data = (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; @@ -229,7 +230,7 @@ int usb_board_stop(void) return 0; } -int usb_board_init_fail(void) +int board_usb_cleanup(int index, enum usb_init_type init) { return usb_board_stop(); } @@ -378,11 +379,7 @@ int board_early_init_r (void) */ /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); -#else mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); -#endif /* Remove TLB entry of boot EBC mapping */ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); @@ -493,9 +490,9 @@ int misc_init_r(void) #endif /* !defined(CONFIG_ARCHES) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -extern void __ft_board_setup(void *blob, bd_t *bd); +extern int __ft_board_setup(void *blob, bd_t *bd); -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { __ft_board_setup(blob, bd); @@ -518,5 +515,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", "disabled", sizeof("disabled"), 1); } + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index e3134ddd6a..bf00bd6bca 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -31,13 +31,7 @@ tlbtab: * use the speed up boot process. It is patched after relocation to * enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */ -#else - tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G) - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) - tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG) -#endif /* * TLB entries for SDRAM are not needed on this platform. @@ -95,31 +89,3 @@ tlbtab: #endif tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds deleted file mode 100644 index 31a2123bf1..0000000000 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/amcc/canyonlands/init.o (.text*) - - /* Align to next NAND block */ - . = ALIGN(0x20000); - common/env_embedded.o (.ppcenv) - /* Keep some space here for redundant env and potential bad env blocks */ - . = ALIGN(0x80000); - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/ebony/Kconfig b/board/amcc/ebony/Kconfig new file mode 100644 index 0000000000..62394b68fa --- /dev/null +++ b/board/amcc/ebony/Kconfig @@ -0,0 +1,12 @@ +if TARGET_EBONY + +config SYS_BOARD + default "ebony" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "ebony" + +endif diff --git a/board/amcc/ebony/MAINTAINERS b/board/amcc/ebony/MAINTAINERS new file mode 100644 index 0000000000..bc62851509 --- /dev/null +++ b/board/amcc/ebony/MAINTAINERS @@ -0,0 +1,6 @@ +EBONY BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/ebony/ +F: include/configs/ebony.h +F: configs/ebony_defconfig diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile index 553fc6b14a..5876486f58 100644 --- a/board/amcc/ebony/Makefile +++ b/board/amcc/ebony/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = ebony.o flash.o +extra-y += init.o diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index df35589aa6..eb424489ef 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig new file mode 100644 index 0000000000..fc606cff1c --- /dev/null +++ b/board/amcc/katmai/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KATMAI + +config SYS_BOARD + default "katmai" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "katmai" + +endif diff --git a/board/amcc/katmai/MAINTAINERS b/board/amcc/katmai/MAINTAINERS new file mode 100644 index 0000000000..f0893522cc --- /dev/null +++ b/board/amcc/katmai/MAINTAINERS @@ -0,0 +1,6 @@ +KATMAI BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/katmai/ +F: include/configs/katmai.h +F: configs/katmai_defconfig diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile index b190ebad2a..b738defc1e 100644 --- a/board/amcc/katmai/Makefile +++ b/board/amcc/katmai/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -SOBJS = init.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := katmai.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +extra-y += init.o diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 83ccd53020..32f26672e2 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -4,7 +4,7 @@ * * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig new file mode 100644 index 0000000000..3f2f434827 --- /dev/null +++ b/board/amcc/kilauea/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KILAUEA + +config SYS_BOARD + default "kilauea" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "kilauea" + +endif diff --git a/board/amcc/kilauea/MAINTAINERS b/board/amcc/kilauea/MAINTAINERS new file mode 100644 index 0000000000..12bbcb1b15 --- /dev/null +++ b/board/amcc/kilauea/MAINTAINERS @@ -0,0 +1,7 @@ +KILAUEA BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/kilauea/ +F: include/configs/kilauea.h +F: configs/haleakala_defconfig +F: configs/kilauea_defconfig diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile index 7e7ff2747a..754dadc66a 100644 --- a/board/amcc/kilauea/Makefile +++ b/board/amcc/kilauea/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := kilauea.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds deleted file mode 100644 index 9a331c50a9..0000000000 --- a/board/amcc/kilauea/u-boot-nand.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text*) - - /* Align to next NAND block */ - . = ALIGN(0x4000); - common/env_embedded.o (.ppcenv) - /* Keep some space here for redundant env and potential bad env blocks */ - . = ALIGN(0x10000); - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig new file mode 100644 index 0000000000..3df90af484 --- /dev/null +++ b/board/amcc/luan/Kconfig @@ -0,0 +1,12 @@ +if TARGET_LUAN + +config SYS_BOARD + default "luan" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "luan" + +endif diff --git a/board/amcc/luan/MAINTAINERS b/board/amcc/luan/MAINTAINERS new file mode 100644 index 0000000000..a23296d44f --- /dev/null +++ b/board/amcc/luan/MAINTAINERS @@ -0,0 +1,6 @@ +LUAN BOARD +M: John Otken +S: Maintained +F: board/amcc/luan/ +F: include/configs/luan.h +F: configs/luan_defconfig diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile index 553fc6b14a..345ad564dc 100644 --- a/board/amcc/luan/Makefile +++ b/board/amcc/luan/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = luan.o flash.o +extra-y += init.o diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S index 9514fb8b8a..0f4a78e1e7 100644 --- a/board/amcc/luan/init.S +++ b/board/amcc/luan/init.S @@ -4,7 +4,7 @@ * * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 509595b5ad..774671db43 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -2,7 +2,7 @@ * (C) Copyright 2005 * John Otken, jotken@softadvances.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig new file mode 100644 index 0000000000..31ce5f10c6 --- /dev/null +++ b/board/amcc/makalu/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MAKALU + +config SYS_BOARD + default "makalu" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "makalu" + +endif diff --git a/board/amcc/makalu/MAINTAINERS b/board/amcc/makalu/MAINTAINERS new file mode 100644 index 0000000000..ecd5e19c61 --- /dev/null +++ b/board/amcc/makalu/MAINTAINERS @@ -0,0 +1,6 @@ +MAKALU BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/makalu/ +F: include/configs/makalu.h +F: configs/makalu_defconfig diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile index efc4bf8530..dcf162ca98 100644 --- a/board/amcc/makalu/Makefile +++ b/board/amcc/makalu/Makefile @@ -5,24 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o cmd_pll.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = makalu.o cmd_pll.o +obj-y += init.o diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S index 032640f67f..e15c62249e 100644 --- a/board/amcc/makalu/init.S +++ b/board/amcc/makalu/init.S @@ -7,7 +7,7 @@ * * Originally based on code provided from Senao and AMCC * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ .globl ext_bus_cntlr_init diff --git a/board/amcc/ocotea/Kconfig b/board/amcc/ocotea/Kconfig new file mode 100644 index 0000000000..18c1a15ef4 --- /dev/null +++ b/board/amcc/ocotea/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OCOTEA + +config SYS_BOARD + default "ocotea" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "ocotea" + +endif diff --git a/board/amcc/ocotea/MAINTAINERS b/board/amcc/ocotea/MAINTAINERS new file mode 100644 index 0000000000..34634a2f77 --- /dev/null +++ b/board/amcc/ocotea/MAINTAINERS @@ -0,0 +1,6 @@ +OCOTEA BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/ocotea/ +F: include/configs/ocotea.h +F: configs/ocotea_defconfig diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile index 553fc6b14a..7646bbb961 100644 --- a/board/amcc/ocotea/Makefile +++ b/board/amcc/ocotea/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = ocotea.o flash.o +extra-y += init.o diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S index e23cc7e134..35085f0a06 100644 --- a/board/amcc/ocotea/init.S +++ b/board/amcc/ocotea/init.S @@ -1,7 +1,7 @@ /* * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index e0039485e6..5f11f195e8 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -4,7 +4,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig new file mode 100644 index 0000000000..d710590998 --- /dev/null +++ b/board/amcc/redwood/Kconfig @@ -0,0 +1,12 @@ +if TARGET_REDWOOD + +config SYS_BOARD + default "redwood" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "redwood" + +endif diff --git a/board/amcc/redwood/MAINTAINERS b/board/amcc/redwood/MAINTAINERS new file mode 100644 index 0000000000..756b30135c --- /dev/null +++ b/board/amcc/redwood/MAINTAINERS @@ -0,0 +1,6 @@ +REDWOOD BOARD +M: Feng Kan +S: Maintained +F: board/amcc/redwood/ +F: include/configs/redwood.h +F: configs/redwood_defconfig diff --git a/board/amcc/redwood/Makefile b/board/amcc/redwood/Makefile index 2ab3b20460..2bc632b240 100644 --- a/board/amcc/redwood/Makefile +++ b/board/amcc/redwood/Makefile @@ -5,24 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = redwood.o +extra-y += init.o diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S index 748422dedd..fd05130870 100644 --- a/board/amcc/redwood/init.S +++ b/board/amcc/redwood/init.S @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig new file mode 100644 index 0000000000..67ee3ca2eb --- /dev/null +++ b/board/amcc/sequoia/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SEQUOIA + +config SYS_BOARD + default "sequoia" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "sequoia" + +endif diff --git a/board/amcc/sequoia/MAINTAINERS b/board/amcc/sequoia/MAINTAINERS new file mode 100644 index 0000000000..6c28a3717c --- /dev/null +++ b/board/amcc/sequoia/MAINTAINERS @@ -0,0 +1,9 @@ +SEQUOIA BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/sequoia/ +F: include/configs/sequoia.h +F: configs/rainier_defconfig +F: configs/rainier_ramboot_defconfig +F: configs/sequoia_defconfig +F: configs/sequoia_ramboot_defconfig diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile index c2a4c4b675..b4ab5daa85 100644 --- a/board/amcc/sequoia/Makefile +++ b/board/amcc/sequoia/Makefile @@ -5,29 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y = $(BOARD).o sdram.o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -SOBJS = init.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = sequoia.o sdram.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +extra-y += init.o diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 9497865575..f876639d35 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -48,11 +48,7 @@ tlbtab: /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) -#else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) -#endif #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ @@ -81,31 +77,3 @@ tlbtab: tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 2c5a21806a..67640d7edf 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -26,14 +26,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); -#if defined(CONFIG_NAND_SPL) -/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big - * for the 4k NAND boot image so define bus_frequency to 133MHz here - * which is save for the refresh counter setup. - */ -#define get_bus_freq(val) 133333333 -#endif - /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -41,8 +33,7 @@ extern void denali_core_search_data_eye(void); ************************************************************************/ phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \ - defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_SYS_RAMBOOT) ulong speed = get_bus_freq(0); mtsdram(DDR0_02, 0x00000000); @@ -81,7 +72,7 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ +#endif /* #ifndef CONFIG_SYS_RAMBOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+ diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 73c65c56aa..91c6cbf7aa 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -142,8 +143,7 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ - defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) mtdcr(EBC0_CFGADDR, PB3CR); #else mtdcr(EBC0_CFGADDR, PB0CR); @@ -151,8 +151,7 @@ int misc_init_r(void) pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ - defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) mtdcr(EBC0_CFGADDR, PB3CR); #else mtdcr(EBC0_CFGADDR, PB0CR); @@ -360,12 +359,12 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) } #endif -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) /* * On NAND-booting sequoia, we need to patch the chips select numbers * in the dtb (CS0 - NAND, CS3 - NOR) */ -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int rc; int len; @@ -383,15 +382,14 @@ void ft_board_setup(void *blob, bd_t *bd) prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); if (prop == NULL) { printf("Unable to update NOR chip select for NAND booting\n"); - return; + return -FDT_ERR_NOTFOUND; } reg = (u32 *)&prop->data[0]; reg[0] = 3; rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); if (rc) { - printf("Unable to update property NOR mappings, err=%s\n", - fdt_strerror(rc)); - return; + printf("Unable to update property NOR mappings\n"); + return rc; } /* And now configure NAND chip select to 0 instead of 3 */ @@ -400,15 +398,16 @@ void ft_board_setup(void *blob, bd_t *bd) prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); if (prop == NULL) { printf("Unable to update NDFC chip select for NAND booting\n"); - return; + return len; } reg = (u32 *)&prop->data[0]; reg[0] = 0; rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); if (rc) { - printf("Unable to update property NDFC mappings, err=%s\n", - fdt_strerror(rc)); - return; + printf("Unable to update property NDFC mapping\n"); + return rc; } + + return 0; } -#endif /* CONFIG_NAND_U_BOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds deleted file mode 100644 index f4d752c30b..0000000000 --- a/board/amcc/sequoia/u-boot-nand.lds +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/amcc/sequoia/init.o (.text*) - - /* Align to next NAND block */ - . = ALIGN(0x4000); - common/env_embedded.o (.ppcenv) - /* Keep some space here for redundant env and potential bad env blocks */ - . = ALIGN(0x10000); - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/taihu/Kconfig b/board/amcc/taihu/Kconfig new file mode 100644 index 0000000000..fc5cb1de7e --- /dev/null +++ b/board/amcc/taihu/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TAIHU + +config SYS_BOARD + default "taihu" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "taihu" + +endif diff --git a/board/amcc/taihu/MAINTAINERS b/board/amcc/taihu/MAINTAINERS new file mode 100644 index 0000000000..2efc254954 --- /dev/null +++ b/board/amcc/taihu/MAINTAINERS @@ -0,0 +1,6 @@ +TAIHU BOARD +M: John Otken +S: Maintained +F: board/amcc/taihu/ +F: include/configs/taihu.h +F: configs/taihu_defconfig diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile index 8a7bf4ad98..65606fe080 100644 --- a/board/amcc/taihu/Makefile +++ b/board/amcc/taihu/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o lcd.o update.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = taihu.o flash.o lcd.o update.o diff --git a/board/amcc/taishan/Kconfig b/board/amcc/taishan/Kconfig new file mode 100644 index 0000000000..abd07f570d --- /dev/null +++ b/board/amcc/taishan/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TAISHAN + +config SYS_BOARD + default "taishan" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "taishan" + +endif diff --git a/board/amcc/taishan/MAINTAINERS b/board/amcc/taishan/MAINTAINERS new file mode 100644 index 0000000000..d9d80bf1c2 --- /dev/null +++ b/board/amcc/taishan/MAINTAINERS @@ -0,0 +1,6 @@ +TAISHAN BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/taishan/ +F: include/configs/taishan.h +F: configs/taishan_defconfig diff --git a/board/amcc/taishan/Makefile b/board/amcc/taishan/Makefile index 4bb14fe98b..04e93cc0da 100644 --- a/board/amcc/taishan/Makefile +++ b/board/amcc/taishan/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o lcd.o update.o showinfo.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = taishan.o lcd.o update.o showinfo.o +extra-y += init.o diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S index 0ff4a9134a..ab1bb34fb8 100644 --- a/board/amcc/taishan/init.S +++ b/board/amcc/taishan/init.S @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c index c0a668a95e..124b81ee0b 100644 --- a/board/amcc/taishan/lcd.c +++ b/board/amcc/taishan/lcd.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index bc74e8a9af..53bfdf790b 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 52af23c6e9..5c8d9ec8f1 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -4,7 +4,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c index 3440d50a2d..273898929a 100644 --- a/board/amcc/taishan/update.c +++ b/board/amcc/taishan/update.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig new file mode 100644 index 0000000000..94e3dc9e78 --- /dev/null +++ b/board/amcc/walnut/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WALNUT + +config SYS_BOARD + default "walnut" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "walnut" + +endif diff --git a/board/amcc/walnut/MAINTAINERS b/board/amcc/walnut/MAINTAINERS new file mode 100644 index 0000000000..2a98c85a14 --- /dev/null +++ b/board/amcc/walnut/MAINTAINERS @@ -0,0 +1,7 @@ +WALNUT BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/walnut/ +F: include/configs/walnut.h +F: configs/sycamore_defconfig +F: configs/walnut_defconfig diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile index bea58a7cae..922817076c 100644 --- a/board/amcc/walnut/Makefile +++ b/board/amcc/walnut/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = walnut.o flash.o diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig new file mode 100644 index 0000000000..dfa10687c2 --- /dev/null +++ b/board/amcc/yosemite/Kconfig @@ -0,0 +1,12 @@ +if TARGET_YOSEMITE + +config SYS_BOARD + default "yosemite" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "yosemite" + +endif diff --git a/board/amcc/yosemite/MAINTAINERS b/board/amcc/yosemite/MAINTAINERS new file mode 100644 index 0000000000..3f553e190a --- /dev/null +++ b/board/amcc/yosemite/MAINTAINERS @@ -0,0 +1,7 @@ +YOSEMITE BOARD +M: Stefan Roese +S: Maintained +F: board/amcc/yosemite/ +F: include/configs/yosemite.h +F: configs/yellowstone_defconfig +F: configs/yosemite_defconfig diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile index 1d80df8b74..daf020a5a9 100644 --- a/board/amcc/yosemite/Makefile +++ b/board/amcc/yosemite/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = yosemite.o +extra-y += init.o diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 8523ac33ee..56b5191d66 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -2,7 +2,7 @@ * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig new file mode 100644 index 0000000000..61d95891e4 --- /dev/null +++ b/board/amcc/yucca/Kconfig @@ -0,0 +1,12 @@ +if TARGET_YUCCA + +config SYS_BOARD + default "yucca" + +config SYS_VENDOR + default "amcc" + +config SYS_CONFIG_NAME + default "yucca" + +endif diff --git a/board/amcc/yucca/MAINTAINERS b/board/amcc/yucca/MAINTAINERS new file mode 100644 index 0000000000..1cbdb0e70d --- /dev/null +++ b/board/amcc/yucca/MAINTAINERS @@ -0,0 +1,6 @@ +YUCCA BOARD +#M: - +S: Maintained +F: board/amcc/yucca/ +F: include/configs/yucca.h +F: configs/yucca_defconfig diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile index eaeb3871ef..5b1af3290f 100644 --- a/board/amcc/yucca/Makefile +++ b/board/amcc/yucca/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o cmd_yucca.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = yucca.o flash.o cmd_yucca.o +extra-y += init.o diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index dc78b73731..c1724bf034 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -8,6 +8,7 @@ */ #include +#include #include #include "yucca.h" #include @@ -51,7 +52,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -74,7 +75,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); #endif } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -118,7 +119,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); #endif - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -142,7 +143,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -163,13 +164,13 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("Pci-X clk = %s MHz\n", pcixClock); do { - printf("\npress [y] to write I2C bootstrap \n"); - printf("or [n] to abort. \n"); - printf("Don't forget to set board switches \n"); - printf("according to your choice before re-starting \n"); - printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); + printf("\npress [y] to write I2C bootstrap\n"); + printf("or [n] to abort.\n"); + printf("Don't forget to set board switches\n"); + printf("according to your choice before re-starting\n"); + printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "n") == 0) return 0; diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index b2fc43e52f..7da5c0d44f 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -4,7 +4,7 @@ * * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig new file mode 100644 index 0000000000..b8e380eb84 --- /dev/null +++ b/board/aristainetos/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ARISTAINETOS + +config SYS_BOARD + default "aristainetos" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "aristainetos" + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS new file mode 100644 index 0000000000..d45d4236c6 --- /dev/null +++ b/board/aristainetos/MAINTAINERS @@ -0,0 +1,6 @@ +ARISTAINETOS BOARD +M: Heiko Schocher +S: Maintained +F: board/aristainetos/ +F: include/configs/aristainetos.h +F: configs/aristainetos_defconfig diff --git a/board/aristainetos/Makefile b/board/aristainetos/Makefile new file mode 100644 index 0000000000..5de48bc439 --- /dev/null +++ b/board/aristainetos/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := aristainetos.o diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c new file mode 100644 index 0000000000..67ac260055 --- /dev/null +++ b/board/aristainetos/aristainetos.c @@ -0,0 +1,525 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define DISP_PAD_CTRL (0x10) + +#define ECSPI4_CS1 IMX_GPIO_NR(5, 2) + +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const gpio_pads[] = { + /* LED enable */ + MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi flash WP protect */ + MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* backlight enable */ + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED yellow */ + MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED red */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED green */ + MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED blue */ + MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* i2c4 scl */ + MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* i2c4 sda */ + MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi CS 1 */ + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const misc_pads[] = { + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG Power enable */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); +} + +iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const ecspi4_pads[] = { + MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const display_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DI0_PIN4__GPIO4_IO20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) + ? (IMX_GPIO_NR(3, 20)) : -1; +} + +static void setup_spi(void) +{ + int i; + + imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); + for (i = 0; i < 3; i++) + enable_spi_clk(true, i); + + /* set cs1 to high */ + gpio_direction_output(ECSPI4_CS1, 1); +} + +static void setup_iomux_gpio(void) +{ + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | + fsl_esdhc_initialize(bis, &usdhc_cfg[1]); +} +#endif + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *iomuxc_regs = + (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + setup_iomux_enet(); + /* clear gpr1[14], gpr1[18:17] to select anatop clock */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); + + ret = enable_fec_anatop_clock(ENET_50MHZ); + if (ret) + return ret; + + return cpu_eth_init(bis); +} +#if defined(CONFIG_VIDEO_IPUV3) + +static void enable_lvds(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + display_pads, + ARRAY_SIZE(display_pads)); + imx_iomux_v3_setup_multiple_pads( + backlight_pads, + ARRAY_SIZE(backlight_pads)); + + /* enable backlight PWM 3 */ + if (pwm_init(2, 0, 0)) + goto error; + /* duty cycle 200ns, period: 3000ns */ + if (pwm_config(2, 200, 3000)) + goto error; + if (pwm_enable(2)) + goto error; + return; + +error: + puts("error init pwm for backlight\n"); + return; +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "lb07wv8", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33246, + .left_margin = 88, + .right_margin = 88, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 25, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED + } + } +}; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + + enable_ipu_clock(); + + reg = readl(&mxc_ccm->cs2cdr); + /* select pll 5 clock */ + reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK; + reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cs2cdr); + + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); +} + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_gpio(); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +int board_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_spi(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info2); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info3); + + /* i2c4 not used, set it to gpio input */ + gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl"); + gpio_direction_input(IMX_GPIO_NR(1, 7)); + gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda"); + gpio_direction_input(IMX_GPIO_NR(1, 8)); + + /* SPI NOR Flash read only */ + gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor"); + gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0); + gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH); + + /* enable LED */ + gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); + gpio_direction_output(IMX_GPIO_NR(2, 13), 0); + + gpio_request(IMX_GPIO_NR(1, 3), "LED yellow"); + gpio_direction_output(IMX_GPIO_NR(1, 3), 1); + gpio_request(IMX_GPIO_NR(1, 4), "LED red"); + gpio_direction_output(IMX_GPIO_NR(1, 4), 1); + gpio_request(IMX_GPIO_NR(1, 5), "LED green"); + gpio_direction_output(IMX_GPIO_NR(1, 5), 1); + gpio_request(IMX_GPIO_NR(1, 6), "LED blue"); + gpio_direction_output(IMX_GPIO_NR(1, 6), 1); + + setup_gpmi_nand(); + + /* GPIO_1 for USB_OTG_ID */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK); + imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); + + return 0; +} + +int checkboard(void) +{ + puts("Board: aristaitenos\n"); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + int ret; + + ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr"); + if (!ret) + gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1); + ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr"); + if (!ret) + gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1); + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on); + else + gpio_set_value(ARISTAINETOS_USB_H1_PWR, on); + return 0; +} +#endif diff --git a/board/aristainetos/aristainetos.cfg b/board/aristainetos/aristainetos.cfg new file mode 100644 index 0000000000..2290180b45 --- /dev/null +++ b/board/aristainetos/aristainetos.cfg @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd + */ +BOOT_FROM spi + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "mt41j128M.cfg" +#include "clocks.cfg" diff --git a/board/aristainetos/clocks.cfg b/board/aristainetos/clocks.cfg new file mode 100644 index 0000000000..651449e567 --- /dev/null +++ b/board/aristainetos/clocks.cfg @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00c03f3f +DATA 4, CCM_CCGR1, 0x0030fcff +DATA 4, CCM_CCGR2, 0x0fffcfc0 +DATA 4, CCM_CCGR3, 0x3ff0300f +DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0f0000c3 +DATA 4, CCM_CCGR6, 0x000003ff diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg new file mode 100644 index 0000000000..c72a3ef821 --- /dev/null +++ b/board/aristainetos/ddr-setup.cfg @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* DDR IO TYPE */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* Clock */ +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +/* Address */ +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* Control */ +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +/* Data Strobe */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 diff --git a/board/aristainetos/mt41j128M.cfg b/board/aristainetos/mt41j128M.cfg new file mode 100644 index 0000000000..3561655727 --- /dev/null +++ b/board/aristainetos/mt41j128M.cfg @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/* ZQ Calibration */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F +/* + * DQS gating, read delay, write delay calibration values + * based on calibration compare of 0x00ffff00 + */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +/* Complete calibration by forced measurment */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +/* in DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 +/* MR2 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a +/* MR3 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b +/* MR1 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 +/* MR0 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +/* final ddr setup */ +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d +DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/armadeus/apf27/Kconfig b/board/armadeus/apf27/Kconfig new file mode 100644 index 0000000000..65544a8448 --- /dev/null +++ b/board/armadeus/apf27/Kconfig @@ -0,0 +1,15 @@ +if TARGET_APF27 + +config SYS_BOARD + default "apf27" + +config SYS_VENDOR + default "armadeus" + +config SYS_SOC + default "mx27" + +config SYS_CONFIG_NAME + default "apf27" + +endif diff --git a/board/armadeus/apf27/MAINTAINERS b/board/armadeus/apf27/MAINTAINERS new file mode 100644 index 0000000000..09f0525c51 --- /dev/null +++ b/board/armadeus/apf27/MAINTAINERS @@ -0,0 +1,7 @@ +APF27 BOARD +M: Philippe Reynes +M: Eric Jarrige +S: Maintained +F: board/armadeus/apf27/ +F: include/configs/apf27.h +F: configs/apf27_defconfig diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile new file mode 100644 index 0000000000..57129718d5 --- /dev/null +++ b/board/armadeus/apf27/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2012-2013 +# Eric Jarrige +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := apf27.o +obj-y += lowlevel_init.o +obj-$(CONFIG_FPGA) += fpga.o diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c new file mode 100644 index 0000000000..30e720d167 --- /dev/null +++ b/board/armadeus/apf27/apf27.c @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2008-2013 Eric Jarrige + * + * based on the files by + * Sascha Hauer, Pengutronix + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "apf27.h" +#include "crc.h" +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Fuse bank 1 row 8 is "reserved for future use" and therefore available for + * customer use. The APF27 board uses this fuse to store the board revision: + * 0: initial board revision + * 1: first revision - Presence of the second RAM chip on the board is blown in + * fuse bank 1 row 9 bit 0 - No hardware change + * N: to be defined + */ +static u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + + return readl(&iim->bank[1].fuse_regs[8]); +} + +/* + * Fuse bank 1 row 9 is "reserved for future use" and therefore available for + * customer use. The APF27 board revision 1 uses the bit 0 to permanently store + * the presence of the second RAM chip + * 0: AFP27 with 1 RAM of 64 MiB + * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB) + */ +static int get_num_ram_bank(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + int nr_dram_banks = 1; + + if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1)) + nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01; + else + nr_dram_banks = CONFIG_NR_DRAM_POPULATED; + + return nr_dram_banks; +} + +static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2, + u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2, + u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr, + u32 puen, u32 gius) +{ + struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE; + + writel(gpio_dr, ®s->port[port].gpio_dr); + writel(ocr1, ®s->port[port].ocr1); + writel(ocr2, ®s->port[port].ocr2); + writel(iconfa1, ®s->port[port].iconfa1); + writel(iconfa2, ®s->port[port].iconfa2); + writel(iconfb1, ®s->port[port].iconfb1); + writel(iconfb2, ®s->port[port].iconfb2); + writel(icr1, ®s->port[port].icr1); + writel(icr2, ®s->port[port].icr2); + writel(imr, ®s->port[port].imr); + writel(gpio_dir, ®s->port[port].gpio_dir); + writel(gpr, ®s->port[port].gpr); + writel(puen, ®s->port[port].puen); + writel(gius, ®s->port[port].gius); +} + +#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \ + ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \ + ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \ + ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \ + ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \ + ACFG_GIUS_##n##_VAL) + +static void apf27_iomux_init(void) +{ + APF27_PORT_INIT(A); + APF27_PORT_INIT(B); + APF27_PORT_INIT(C); + APF27_PORT_INIT(D); + APF27_PORT_INIT(E); + APF27_PORT_INIT(F); +} + +static int apf27_devices_init(void) +{ + int i; + unsigned int mode[] = { + PC5_PF_I2C2_DATA, + PC6_PF_I2C2_CLK, + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +#ifdef CONFIG_MXC_UART + mx27_uart1_init_pins(); +#endif + +#ifdef CONFIG_FEC_MXC + mx27_fec_init_pins(); +#endif + +#ifdef CONFIG_MXC_MMC + mx27_sd2_init_pins(); + imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16)); + gpio_request(PC_PWRON, "pc_pwron"); + gpio_set_value(PC_PWRON, 1); +#endif + return 0; +} + +static void apf27_setup_csx(void) +{ + struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE; + + writel(ACFG_CS0U_VAL, &weim->cs0u); + writel(ACFG_CS0L_VAL, &weim->cs0l); + writel(ACFG_CS0A_VAL, &weim->cs0a); + + writel(ACFG_CS1U_VAL, &weim->cs1u); + writel(ACFG_CS1L_VAL, &weim->cs1l); + writel(ACFG_CS1A_VAL, &weim->cs1a); + + writel(ACFG_CS2U_VAL, &weim->cs2u); + writel(ACFG_CS2L_VAL, &weim->cs2l); + writel(ACFG_CS2A_VAL, &weim->cs2a); + + writel(ACFG_CS3U_VAL, &weim->cs3u); + writel(ACFG_CS3L_VAL, &weim->cs3l); + writel(ACFG_CS3A_VAL, &weim->cs3a); + + writel(ACFG_CS4U_VAL, &weim->cs4u); + writel(ACFG_CS4L_VAL, &weim->cs4l); + writel(ACFG_CS4A_VAL, &weim->cs4a); + + writel(ACFG_CS5U_VAL, &weim->cs5u); + writel(ACFG_CS5L_VAL, &weim->cs5l); + writel(ACFG_CS5A_VAL, &weim->cs5a); + + writel(ACFG_EIM_VAL, &weim->eim); +} + +static void apf27_setup_port(void) +{ + struct system_control_regs *system = + (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; + + writel(ACFG_FMCR_VAL, &system->fmcr); +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + apf27_setup_csx(); + apf27_setup_port(); + apf27_iomux_init(); + apf27_devices_init(); +#if defined(CONFIG_FPGA) + APF27_init_fpga(); +#endif + + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + if (get_num_ram_bank() > 1) + gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + if (get_num_ram_bank() > 1) + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); + else + gd->bd->bi_dram[1].size = 0; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + ulong ramtop; + + if (get_num_ram_bank() > 1) + ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); + else + ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + + return ramtop; +} + +int checkboard(void) +{ + printf("Board: Armadeus APF27 revision %d\n", get_board_rev()); + return 0; +} + +#ifdef CONFIG_SPL_BUILD +inline void hang(void) +{ + for (;;) + ; +} + +void board_init_f(ulong bootflag) +{ + /* + * copy ourselves from where we are running to where we were + * linked at. Use ulong pointers as all addresses involved + * are 4-byte-aligned. + */ + ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; + asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); + asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); + asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); + asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); + for (dst = start_ptr; dst < end_ptr; dst++) + *dst = *(dst+(run_ptr-link_ptr)); + + /* + * branch to nand_boot's link-time address. + */ + asm volatile("ldr pc, =nand_boot"); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h new file mode 100644 index 0000000000..64e7e4dfbb --- /dev/null +++ b/board/armadeus/apf27/apf27.h @@ -0,0 +1,489 @@ +/* + * Copyright (C) 2008-2013 Eric Jarrige + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __APF27_H +#define __APF27_H + +/* FPGA program pin configuration */ +#define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ +#define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ +#define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ +#define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */ +#define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */ +#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ +#define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ +#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ +#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ +#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ +#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ + +/* MMC pin */ +#define PC_PWRON (GPIO_PORTF | 16) + +/* + * MPU CLOCK source before PLL + * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) + */ +#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ +#define ACFG_MPCTL1_VAL 0 +#define CONFIG_MPLL_FREQ 399 + +#define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ + +/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/ +#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ +#define ACFG_SPCTL1_VAL 0 +#define CONFIG_SPLL_FREQ 300 /* MHz */ + +/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ +#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ + +/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */ +#define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */ + +#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */ +#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ +#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ +#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ +#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */ +#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */ +#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */ +#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */ +#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ +#define CONFIG_CLK0_EN 1 /* CLK0 enabled */ + +/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ +#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */ + +/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ +#define CONFIG_USB_FREQ 60 /* 60 MHz */ + +/* + * SDRAM + */ +#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ +/* micron 64MB */ +#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 + * column address bits + */ +#define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 + * row address bits + */ +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + * 2=4096 3=8192 refresh + */ +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power + * down delay + */ +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read + * cycle delay > 0 + */ +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register + * cycle delay 1..4 + */ +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck + * SDRAM: 0=1ck 1=2ck + */ +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + * refresh to command) + */ +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + * estimated fo CL=1 + * 0=force 3 for lpddr + */ +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + * 3=Eighth 4=Sixteenth + */ +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half + * 2=quater 3=Eighth + */ +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access + * 0 = Burst mode + */ +#endif + +#if (ACFG_SDRAM_MBYTE_SYZE == 128) +/* micron 128MB */ +#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 + * column address bits + */ +#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 + * row address bits + */ +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + * 2=4096 3=8192 refresh + */ +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power + * down delay + */ +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read + * cycle delay > 0 + */ +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register + * cycle delay 1..4 + */ +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck + * SDRAM: 0=1ck 1=2ck + */ +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + * refresh to command) + */ +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + * estimated fo CL=1 + * 0=force 3 for lpddr + */ +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + * 3=Eighth 4=Sixteenth + */ +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half + * 2=quater 3=Eighth + */ +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access + * 0 = Burst mode + */ +#endif + +#if (ACFG_SDRAM_MBYTE_SYZE == 256) +/* micron 256MB */ +#define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 + * column address bits + */ +#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 + * row address bits + */ +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + * 2=4096 3=8192 refresh + */ +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power + * down delay + */ +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle + * delay > 0 + */ +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register + * cycle delay 1..4 + */ +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck + * SDRAM: 0=1ck 1=2ck + */ +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + * refresh to command) + */ +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + * estimated fo CL=1 + * 0=force 3 for lpddr + */ +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + * 3=Eighth 4=Sixteenth + */ +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength + * 1=half + * 2=quater + * 3=Eighth + */ +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access + * 0 = Burst mode + */ +#endif + +/* + * External interface + */ +/* + * CSCRxU_VAL: + * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 + * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | + * + * 15| x x | x x x x x x | x | x x x x | x x x x |0 + * | CNC | WSC |EW | WWS | EDC | + * + * CSCRxL_VAL: + * 31| x x x x | x x x x | x x x x | x x x x |16 + * | OEA | OEN | EBWA | EBWN | + * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 + * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| + * + * CSCRxA_VAL: + * 31| x x x x | x x x x | x x x x | x x x x |16 + * | EBRA | EBRN | RWA | RWN | + * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 + * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| + */ + +/* CS0 configuration for 16 bit nor flash */ +#define ACFG_CS0U_VAL 0x0000CC03 +#define ACFG_CS0L_VAL 0xa0330D01 +#define ACFG_CS0A_VAL 0x00220800 + +#define ACFG_CS1U_VAL 0x00000f00 +#define ACFG_CS1L_VAL 0x00000D01 +#define ACFG_CS1A_VAL 0 + +#define ACFG_CS2U_VAL 0 +#define ACFG_CS2L_VAL 0 +#define ACFG_CS2A_VAL 0 + +#define ACFG_CS3U_VAL 0 +#define ACFG_CS3L_VAL 0 +#define ACFG_CS3A_VAL 0 + +#define ACFG_CS4U_VAL 0 +#define ACFG_CS4L_VAL 0 +#define ACFG_CS4A_VAL 0 + +/* FPGA 16 bit data bus */ +#define ACFG_CS5U_VAL 0x00000600 +#define ACFG_CS5L_VAL 0x00000D01 +#define ACFG_CS5A_VAL 0 + +#define ACFG_EIM_VAL 0x00002200 + + +/* + * FPGA specific settings + */ + +/* CLKO */ +#define ACFG_CCSR_VAL 0x00000305 +/* drive strength CLKO set to 2 */ +#define ACFG_DSCR10_VAL 0x00020000 +/* drive strength A1..A12 set to 2 */ +#define ACFG_DSCR3_VAL 0x02AAAAA8 +/* drive strength ctrl */ +#define ACFG_DSCR7_VAL 0x00020880 +/* drive strength data */ +#define ACFG_DSCR2_VAL 0xAAAAAAAA + + +/* + * Default configuration for GPIOs and peripherals + */ +#define ACFG_DDIR_A_VAL 0x00000000 +#define ACFG_OCR1_A_VAL 0x00000000 +#define ACFG_OCR2_A_VAL 0x00000000 +#define ACFG_ICFA1_A_VAL 0xFFFFFFFF +#define ACFG_ICFA2_A_VAL 0xFFFFFFFF +#define ACFG_ICFB1_A_VAL 0xFFFFFFFF +#define ACFG_ICFB2_A_VAL 0xFFFFFFFF +#define ACFG_DR_A_VAL 0x00000000 +#define ACFG_GIUS_A_VAL 0xFFFFFFFF +#define ACFG_ICR1_A_VAL 0x00000000 +#define ACFG_ICR2_A_VAL 0x00000000 +#define ACFG_IMR_A_VAL 0x00000000 +#define ACFG_GPR_A_VAL 0x00000000 +#define ACFG_PUEN_A_VAL 0xFFFFFFFF + +#define ACFG_DDIR_B_VAL 0x00000000 +#define ACFG_OCR1_B_VAL 0x00000000 +#define ACFG_OCR2_B_VAL 0x00000000 +#define ACFG_ICFA1_B_VAL 0xFFFFFFFF +#define ACFG_ICFA2_B_VAL 0xFFFFFFFF +#define ACFG_ICFB1_B_VAL 0xFFFFFFFF +#define ACFG_ICFB2_B_VAL 0xFFFFFFFF +#define ACFG_DR_B_VAL 0x00000000 +#define ACFG_GIUS_B_VAL 0xFF3FFFF0 +#define ACFG_ICR1_B_VAL 0x00000000 +#define ACFG_ICR2_B_VAL 0x00000000 +#define ACFG_IMR_B_VAL 0x00000000 +#define ACFG_GPR_B_VAL 0x00000000 +#define ACFG_PUEN_B_VAL 0xFFFFFFFF + +#define ACFG_DDIR_C_VAL 0x00000000 +#define ACFG_OCR1_C_VAL 0x00000000 +#define ACFG_OCR2_C_VAL 0x00000000 +#define ACFG_ICFA1_C_VAL 0xFFFFFFFF +#define ACFG_ICFA2_C_VAL 0xFFFFFFFF +#define ACFG_ICFB1_C_VAL 0xFFFFFFFF +#define ACFG_ICFB2_C_VAL 0xFFFFFFFF +#define ACFG_DR_C_VAL 0x00000000 +#define ACFG_GIUS_C_VAL 0xFFFFC07F +#define ACFG_ICR1_C_VAL 0x00000000 +#define ACFG_ICR2_C_VAL 0x00000000 +#define ACFG_IMR_C_VAL 0x00000000 +#define ACFG_GPR_C_VAL 0x00000000 +#define ACFG_PUEN_C_VAL 0xFFFFFF87 + +#define ACFG_DDIR_D_VAL 0x00000000 +#define ACFG_OCR1_D_VAL 0x00000000 +#define ACFG_OCR2_D_VAL 0x00000000 +#define ACFG_ICFA1_D_VAL 0xFFFFFFFF +#define ACFG_ICFA2_D_VAL 0xFFFFFFFF +#define ACFG_ICFB1_D_VAL 0xFFFFFFFF +#define ACFG_ICFB2_D_VAL 0xFFFFFFFF +#define ACFG_DR_D_VAL 0x00000000 +#define ACFG_GIUS_D_VAL 0xFFFFFFFF +#define ACFG_ICR1_D_VAL 0x00000000 +#define ACFG_ICR2_D_VAL 0x00000000 +#define ACFG_IMR_D_VAL 0x00000000 +#define ACFG_GPR_D_VAL 0x00000000 +#define ACFG_PUEN_D_VAL 0xFFFFFFFF + +#define ACFG_DDIR_E_VAL 0x00000000 +#define ACFG_OCR1_E_VAL 0x00000000 +#define ACFG_OCR2_E_VAL 0x00000000 +#define ACFG_ICFA1_E_VAL 0xFFFFFFFF +#define ACFG_ICFA2_E_VAL 0xFFFFFFFF +#define ACFG_ICFB1_E_VAL 0xFFFFFFFF +#define ACFG_ICFB2_E_VAL 0xFFFFFFFF +#define ACFG_DR_E_VAL 0x00000000 +#define ACFG_GIUS_E_VAL 0xFCFFCCF8 +#define ACFG_ICR1_E_VAL 0x00000000 +#define ACFG_ICR2_E_VAL 0x00000000 +#define ACFG_IMR_E_VAL 0x00000000 +#define ACFG_GPR_E_VAL 0x00000000 +#define ACFG_PUEN_E_VAL 0xFFFFFFFF + +#define ACFG_DDIR_F_VAL 0x00000000 +#define ACFG_OCR1_F_VAL 0x00000000 +#define ACFG_OCR2_F_VAL 0x00000000 +#define ACFG_ICFA1_F_VAL 0xFFFFFFFF +#define ACFG_ICFA2_F_VAL 0xFFFFFFFF +#define ACFG_ICFB1_F_VAL 0xFFFFFFFF +#define ACFG_ICFB2_F_VAL 0xFFFFFFFF +#define ACFG_DR_F_VAL 0x00000000 +#define ACFG_GIUS_F_VAL 0xFF7F8000 +#define ACFG_ICR1_F_VAL 0x00000000 +#define ACFG_ICR2_F_VAL 0x00000000 +#define ACFG_IMR_F_VAL 0x00000000 +#define ACFG_GPR_F_VAL 0x00000000 +#define ACFG_PUEN_F_VAL 0xFFFFFFFF + +/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ +#define ACFG_GPCR_VAL 0x0003000F + +#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN + +/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ +#if (CONFIG_NR_DRAM_BANKS == 1) +#define ACFG_FMCR_VAL 0xFFFFFFF9 +#elif (CONFIG_NR_DRAM_BANKS == 2) +#define ACFG_FMCR_VAL 0xFFFFFFFB +#endif + +#define ACFG_AIPI1_PSR0_VAL 0x20040304 +#define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB +#define ACFG_AIPI2_PSR0_VAL 0x00000000 +#define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF + +/* PCCR enable DMA FEC I2C1 IIM SDHC1 */ +#define ACFG_PCCR0_VAL 0x05070410 +#define ACFG_PCCR1_VAL 0xA14A0608 + +/* + * From here, there should not be any user configuration. + * All Equations are automatic + */ + +/* fixme none integer value (7.5ns) => 2*hclock = 15ns */ +#define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ + +/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ +#define CSCR_MASK 0x0300800D + +#define ACFG_CSCR_VAL \ + (CSCR_MASK \ + |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ + |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ + |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) + +/* SSIx CLKO NFC H264 MSHC */ +#define ACFG_PCDR0_VAL\ + (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ + |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ + |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ + |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ + |(((CONFIG_CLK0_DIV)&0x07)<<22)\ + |(((CONFIG_CLK0_EN)&0x01)<<25)\ + |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) + +/* PERCLKx */ +#define ACFG_PCDR1_VAL\ + (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ + |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ + |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ + |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) + +/* SDRAM controller programming Values */ +#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \ + (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1)) +#define REG_FIELD_SCL_VAL 3 +#define REG_FIELD_SCLIMX_VAL 0 +#else +#define REG_FIELD_SCL_VAL\ + ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH) +#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL +#endif + +#if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH)) +#define REG_FIELD_SRC_VAL 0 +#else +#define REG_FIELD_SRC_VAL\ + ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH) +#endif + +/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ +#define REG_ESDCTL_BASE_CONFIG (0x80020485\ + | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\ + | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\ + | (((ACFG_SDRAM_REFRESH)&0x7)<<13)) + +#define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) +#define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) +#define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) +#define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) + +/* ESDRAMC Configuration Registers : force CL=3 to lpddr */ +#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\ + | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\ + | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\ + | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \ + ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \ + | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ + | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\ + | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \ + | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \ + | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ + | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \ + | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) + +/* Issue Mode register Command to SDRAM */ +#define ACFG_SDRAM_MODE_REGISTER_VAL\ + ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\ + | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ + | ((0)<<(3)) /* sequentiql access */ \ + /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) + +/* Issue Extended Mode register Command to SDRAM */ +#define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\ + ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\ + | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\ + | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2))) + +/* Issue Precharge all Command to SDRAM */ +#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10) + +#endif /* __APF27_H */ diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c new file mode 100644 index 0000000000..65a4812c35 --- /dev/null +++ b/board/armadeus/apf27/fpga.c @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2002-2013 + * Eric Jarrige + * + * based on the files by + * Rich Ireland, Enterasys Networks, rireland@enterasys.com + * and + * Keith Outwater, keith_outwater@mvis.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + +#include +#include +#include +#include +#include +#include "fpga.h" +#include +#include "apf27.h" + +/* + * Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * Spartan2 code is used to download our Spartan 3 :) code is compatible. + * Just take care about the file size + */ +xilinx_spartan3_slave_parallel_fns fpga_fns = { + fpga_pre_fn, + fpga_pgm_fn, + fpga_init_fn, + NULL, + fpga_done_fn, + fpga_clk_fn, + fpga_cs_fn, + fpga_wr_fn, + fpga_rdata_fn, + fpga_wdata_fn, + fpga_busy_fn, + fpga_abort_fn, + fpga_post_fn, +}; + +xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + {xilinx_spartan3, + slave_parallel, + 1196128l/8, + (void *)&fpga_fns, + 0, + &spartan3_op, + "3s200aft256"} +}; + +/* + * Initialize GPIO port B before download + */ +int fpga_pre_fn(int cookie) +{ + /* Initialize GPIO pins */ + gpio_set_value(ACFG_FPGA_PWR, 1); + imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO); + gpio_set_value(ACFG_FPGA_RESET, 1); + imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + gpio_set_value(ACFG_FPGA_PRG, 1); + gpio_set_value(ACFG_FPGA_CLK, 1); + gpio_set_value(ACFG_FPGA_RW, 1); + gpio_set_value(ACFG_FPGA_CS, 1); + gpio_set_value(ACFG_FPGA_SUSPEND, 0); + gpio_set_value(ACFG_FPGA_PWR, 0); + udelay(30000); /*wait until supply started*/ + + return cookie; +} + +/* + * Set the FPGA's active-low program line to the specified level + */ +int fpga_pgm_fn(int assert, int flush, int cookie) +{ + debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__, + assert ? "high" : "low"); + gpio_set_value(ACFG_FPGA_PRG, !assert); + return assert; +} + +/* + * Set the FPGA's active-high clock line to the specified level + */ +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__, + assert_clk ? "high" : "low"); + gpio_set_value(ACFG_FPGA_CLK, !assert_clk); + return assert_clk; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int fpga_init_fn(int cookie) +{ + int value; + debug("%s:%d: INIT check... ", __func__, __LINE__); + value = gpio_get_value(ACFG_FPGA_INIT); + /* printf("init value read %x",value); */ +#ifdef CONFIG_SYS_FPGA_IS_PROTO + return value; +#else + return !value; +#endif +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +int fpga_done_fn(int cookie) +{ + debug("%s:%d: DONE check... %s", __func__, __LINE__, + gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low"); + return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL; +} + +/* + * Set the FPGA's wr line to the specified level + */ +int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + debug("%s:%d: FPGA RW... %s ", __func__, __LINE__, + assert_write ? "high" : "low"); + gpio_set_value(ACFG_FPGA_RW, !assert_write); + return assert_write; +} + +int fpga_cs_fn(int assert_cs, int flush, int cookie) +{ + debug("%s:%d: FPGA CS %s ", __func__, __LINE__, + assert_cs ? "high" : "low"); + gpio_set_value(ACFG_FPGA_CS, !assert_cs); + return assert_cs; +} + +int fpga_rdata_fn(unsigned char *data, int cookie) +{ + debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__, + *((char *)ACFG_FPGA_RDATA)); + *data = (unsigned char) + ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF); + return *data; +} + +int fpga_wdata_fn(unsigned char data, int flush, int cookie) +{ + debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__, + data); + *((unsigned short *)ACFG_FPGA_WDATA) = data; + return data; +} + +int fpga_abort_fn(int cookie) +{ + return fpga_post_fn(cookie); +} + + +int fpga_busy_fn(int cookie) +{ + return 1; +} + +int fpga_post_fn(int cookie) +{ + debug("%s:%d: FPGA POST ", __func__, __LINE__); + + imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN); + imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN); + imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN); + gpio_set_value(ACFG_FPGA_PRG, 1); + gpio_set_value(ACFG_FPGA_RESET, 0); + imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + return cookie; +} + +void apf27_fpga_setup(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + struct system_control_regs *system = + (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; + + /* Configure FPGA CLKO */ + writel(ACFG_CCSR_VAL, &pll->ccsr); + + /* Configure strentgh for FPGA */ + writel(ACFG_DSCR10_VAL, &system->dscr10); + writel(ACFG_DSCR3_VAL, &system->dscr3); + writel(ACFG_DSCR7_VAL, &system->dscr7); + writel(ACFG_DSCR2_VAL, &system->dscr2); +} + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +void APF27_init_fpga(void) +{ + int i; + + apf27_fpga_setup(); + + fpga_init(); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i); + fpga_add(fpga_xilinx, &fpga[i]); + } + + return; +} diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h new file mode 100644 index 0000000000..84a5244a6d --- /dev/null +++ b/board/armadeus/apf27/fpga.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2002-2013 + * Eric Jarrige + * + * based on the files by + * Rich Ireland, Enterasys Networks, rireland@enterasys.com + * and + * Keith Outwater, keith_outwater@mvis.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +extern void APF27_init_fpga(void); + +extern int fpga_pre_fn(int cookie); +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_cs_fn(int assert_cs, int flush, int cookie); +extern int fpga_init_fn(int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(int assert_write, int flush, int cookie); +extern int fpga_rdata_fn(unsigned char *data, int cookie); +extern int fpga_wdata_fn(unsigned char data, int flush, int cookie); +extern int fpga_abort_fn(int cookie); +extern int fpga_post_fn(int cookie); +extern int fpga_busy_fn(int cookie); diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S new file mode 100644 index 0000000000..4293cb1080 --- /dev/null +++ b/board/armadeus/apf27/lowlevel_init.S @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2013 Philippe Reynes + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "apf27.h" + + .macro init_aipi + /* + * setup AIPI1 and AIPI2 + */ + write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL + write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL + write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL + write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL + + /* Change SDRAM signal strengh */ + ldr r0, =GPCR + ldr r1, =ACFG_GPCR_VAL + ldr r5, [r0] + orr r5, r5, r1 + str r5, [r0] + + .endm /* init_aipi */ + + .macro init_clock + ldr r0, =CSCR + /* disable MPLL/SPLL first */ + ldr r1, [r0] + bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) + str r1, [r0] + + /* + * pll clock initialization predefined in apf27.h + */ + write32 MPCTL0, ACFG_MPCTL0_VAL + write32 SPCTL0, ACFG_SPCTL0_VAL + + write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART + + /* + * add some delay here + */ + mov r1, #0x1000 + 1: subs r1, r1, #0x1 + bne 1b + + /* peripheral clock divider */ + write32 PCDR0, ACFG_PCDR0_VAL + write32 PCDR1, ACFG_PCDR1_VAL + + /* Configure PCCR0 and PCCR1 */ + write32 PCCR0, ACFG_PCCR0_VAL + write32 PCCR1, ACFG_PCCR1_VAL + + .endm /* init_clock */ + + .macro init_ddr + /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ + ldr r0, =IMX_ESD_BASE + ldr r4, =ESDMISC_SDRAM_RDY +2: ldr r1, [r0, #ESDMISC_ROF] + ands r1, r1, r4 + bpl 2b + + /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ + ldr r0, =IMX_ESD_BASE + ldr r4, =ACFG_ESDMISC_VAL + orr r1, r4, #ESDMISC_MDDR_DL_RST + str r1, [r0, #ESDMISC_ROF] + + /* Hold for more than 200ns */ + ldr r1, =0x10000 +1: subs r1, r1, #0x1 + bne 1b + + str r4, [r0] + + ldr r0, =IMX_ESD_BASE + ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL + str r1, [r0, #ESDCFG0_ROF] + + ldr r0, =IMX_ESD_BASE + ldr r1, =ACFG_PRECHARGE_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* write8(0xA0001000, any value) */ + ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL + strb r2, [r1] + + ldr r1, =ACFG_AUTOREFRESH_CMD + str r1, [r0, #ESDCTL0_ROF] + + ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ + + ldr r6,=0x7 /* load loop counter */ +1: str r5,[r4] /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 + bne 1b + + ldr r1, =ACFG_SET_MODE_REG_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* set standard mode register */ + ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL + strb r2, [r4] + + /* set extended mode register */ + ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL + strb r5, [r4] + + ldr r1, =ACFG_NORMAL_RW_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* 2nd sdram */ + ldr r0, =IMX_ESD_BASE + ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL + str r1, [r0, #ESDCFG1_ROF] + + ldr r0, =IMX_ESD_BASE + ldr r1, =ACFG_PRECHARGE_CMD + str r1, [r0, #ESDCTL1_ROF] + + /* write8(0xB0001000, any value) */ + ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL + strb r2, [r1] + + ldr r1, =ACFG_AUTOREFRESH_CMD + str r1, [r0, #ESDCTL1_ROF] + + ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ + + ldr r6,=0x7 /* load loop counter */ +1: str r5,[r4] /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 + bne 1b + + ldr r1, =ACFG_SET_MODE_REG_CMD + str r1, [r0, #ESDCTL1_ROF] + + /* set standard mode register */ + ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL + strb r2, [r4] + + /* set extended mode register */ + ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL + strb r2, [r4] + + ldr r1, =ACFG_NORMAL_RW_CMD + str r1, [r0, #ESDCTL1_ROF] + .endm /* init_ddr */ + +.globl lowlevel_init +lowlevel_init: + + init_aipi + init_clock +#ifdef CONFIG_SPL_BUILD + init_ddr +#endif + + mov pc, lr diff --git a/board/armltd/integrator/Kconfig b/board/armltd/integrator/Kconfig new file mode 100644 index 0000000000..6153b5dd7d --- /dev/null +++ b/board/armltd/integrator/Kconfig @@ -0,0 +1,103 @@ +if TARGET_INTEGRATORAP_CM720T + +config SYS_BOARD + default "integrator" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "integratorap" + +endif + +if TARGET_INTEGRATORAP_CM920T + +config SYS_BOARD + default "integrator" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "integratorap" + +endif + +if TARGET_INTEGRATORCP_CM920T + +config SYS_BOARD + default "integrator" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "integratorcp" + +endif + +if TARGET_INTEGRATORAP_CM926EJS + +config SYS_BOARD + default "integrator" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "integratorap" + +endif + +if TARGET_INTEGRATORCP_CM926EJS + +config SYS_BOARD + default "integrator" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "integratorcp" + +endif + +if TARGET_INTEGRATORCP_CM1136 + +config SYS_BOARD + default "integrator" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "integratorcp" + +endif + +if TARGET_INTEGRATORAP_CM946ES + +config SYS_BOARD + default "integrator" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "integratorap" + +endif + +if TARGET_INTEGRATORCP_CM946ES + +config SYS_BOARD + default "integrator" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "integratorcp" + +endif diff --git a/board/armltd/integrator/MAINTAINERS b/board/armltd/integrator/MAINTAINERS new file mode 100644 index 0000000000..8af765eaeb --- /dev/null +++ b/board/armltd/integrator/MAINTAINERS @@ -0,0 +1,14 @@ +INTEGRATOR BOARD +M: Linus Walleij +S: Maintained +F: board/armltd/integrator/ +F: include/configs/integratorcp.h +F: configs/integratorcp_cm1136_defconfig +F: include/configs/integratorap.h +F: configs/integratorap_cm720t_defconfig +F: configs/integratorap_cm920t_defconfig +F: configs/integratorcp_cm920t_defconfig +F: configs/integratorap_cm926ejs_defconfig +F: configs/integratorcp_cm926ejs_defconfig +F: configs/integratorap_cm946es_defconfig +F: configs/integratorcp_cm946es_defconfig diff --git a/board/armltd/integrator/Makefile b/board/armltd/integrator/Makefile index b86fbfbdad..7e5f6b03fd 100644 --- a/board/armltd/integrator/Makefile +++ b/board/armltd/integrator/Makefile @@ -9,28 +9,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := lowlevel_init.o -LIB = $(obj)lib$(BOARD).o - -SOBJS-y := lowlevel_init.o - -COBJS-y := integrator.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-y += timer.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -COBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(COBJS) $(SOBJS) - $(call cmd_link_o_target, $(COBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += integrator.o +obj-$(CONFIG_PCI) += pci.o +obj-y += timer.o diff --git a/board/armltd/integrator/arm-ebi.h b/board/armltd/integrator/arm-ebi.h index fb6ed56851..6381fcc464 100644 --- a/board/armltd/integrator/arm-ebi.h +++ b/board/armltd/integrator/arm-ebi.h @@ -5,7 +5,7 @@ * Register definitions for the External Bus Interface (EBI) * found in the ARM Integrator AP and CP reference designs * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ARM_EBI_H diff --git a/board/armltd/integrator/integrator-sc.h b/board/armltd/integrator/integrator-sc.h index e9897c823b..7a94d67304 100644 --- a/board/armltd/integrator/integrator-sc.h +++ b/board/armltd/integrator/integrator-sc.h @@ -6,7 +6,7 @@ * the similar "CP Controller" found in the ARM Integrator/AP and * Integrator/CP reference designs * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ARM_SC_H diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 62870c6f43..f0fe0fd3aa 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -14,7 +14,7 @@ * ARM Ltd. * Philippe Robin, * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S index 4e2da4006f..0fb42adc6f 100644 --- a/board/armltd/integrator/lowlevel_init.S +++ b/board/armltd/integrator/lowlevel_init.S @@ -4,7 +4,7 @@ * (C) Copyright 2004, ARM Ltd. * Philippe Robin, * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -183,7 +183,7 @@ cm_remap: /* Now 0x00000000 is writeable, replace the vectors */ ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_TEXT_BASE /* r2 <- past vectors */ + add r2, r0, #64 /* r2 <- past vectors */ sub r1,r1,r1 /* destination 0x00000000 */ copy_vec: diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c index c3f84236e5..157138b03a 100644 --- a/board/armltd/integrator/pci.c +++ b/board/armltd/integrator/pci.c @@ -18,7 +18,7 @@ * Linaro * Linus Walleij * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c index f77edad4ff..14a52c4608 100644 --- a/board/armltd/integrator/timer.c +++ b/board/armltd/integrator/timer.c @@ -14,7 +14,7 @@ * ARM Ltd. * Philippe Robin, * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/armltd/versatile/MAINTAINERS b/board/armltd/versatile/MAINTAINERS new file mode 100644 index 0000000000..a56dd99bb3 --- /dev/null +++ b/board/armltd/versatile/MAINTAINERS @@ -0,0 +1,8 @@ +VERSATILE BOARD +#M: - +S: Maintained +F: board/armltd/versatile/ +F: include/configs/versatile.h +F: configs/versatileab_defconfig +F: configs/versatilepb_defconfig +F: configs/versatileqemu_defconfig diff --git a/board/armltd/versatile/Makefile b/board/armltd/versatile/Makefile index 89ae01f816..a09a0ae550 100644 --- a/board/armltd/versatile/Makefile +++ b/board/armltd/versatile/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := versatile.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := versatile.o +obj-y += lowlevel_init.o diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index 30a3b904db..4e2d3421d8 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -52,7 +52,11 @@ int board_early_init_f (void) int board_init (void) { /* arch number of Versatile Board */ +#ifdef CONFIG_ARCH_VERSATILE_AB + gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB; +#else gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/armltd/vexpress/Kconfig b/board/armltd/vexpress/Kconfig new file mode 100644 index 0000000000..2e15e0d497 --- /dev/null +++ b/board/armltd/vexpress/Kconfig @@ -0,0 +1,38 @@ +if TARGET_VEXPRESS_CA15_TC2 + +config SYS_BOARD + default "vexpress" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_ca15_tc2" + +endif + +if TARGET_VEXPRESS_CA5X2 + +config SYS_BOARD + default "vexpress" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_ca5x2" + +endif + +if TARGET_VEXPRESS_CA9X4 + +config SYS_BOARD + default "vexpress" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_ca9x4" + +endif diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS new file mode 100644 index 0000000000..a6943d7426 --- /dev/null +++ b/board/armltd/vexpress/MAINTAINERS @@ -0,0 +1,14 @@ +VEXPRESS BOARD +#M: - +S: Maintained +F: board/armltd/vexpress/ +F: include/configs/vexpress_ca15_tc2.h +F: configs/vexpress_ca15_tc2_defconfig + +VEXPRESS_CA5X2 BOARD +#M: Matt Waddel +S: Orphan (since 2014-08) +F: include/configs/vexpress_ca5x2.h +F: configs/vexpress_ca5x2_defconfig +F: include/configs/vexpress_ca9x4.h +F: configs/vexpress_ca9x4_defconfig diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile index e7dc3122ad..1dd6780708 100644 --- a/board/armltd/vexpress/Makefile +++ b/board/armltd/vexpress/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := vexpress_common.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := vexpress_common.o diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 4c7a7f46d5..cb2de2f4dd 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -26,9 +26,6 @@ #include #include "../drivers/mmc/arm_pl180_mmci.h" -static ulong timestamp; -static ulong lastdec; - static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; @@ -122,11 +119,6 @@ void dram_init_banksize(void) get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); } -int timer_init(void) -{ - return 0; -} - /* * Start timer: * Setup a 32 bit timer, running at 1KHz @@ -152,8 +144,6 @@ static void vexpress_timer_init(void) writel(SYSTIMER_EN | SYSTIMER_32BIT | readl(&systimer_base->timer0control), &systimer_base->timer0control); - - reset_timer_masked(); } int v2m_cfg_write(u32 devfn, u32 data) @@ -183,62 +173,6 @@ void reset_cpu(ulong addr) printf("Unable to reboot\n"); } -/* - * Delay x useconds AND perserve advance timstamp value - * assumes timer is ticking at 1 msec - */ -void __udelay(ulong usec) -{ - ulong tmo, tmp; - - tmo = usec / 1000; - tmp = get_timer(0); /* get current timestamp */ - - /* - * If setting this forward will roll time stamp then - * reset "advancing" timestamp to 0 and set lastdec value - * otherwise set the advancing stamp to the wake up time - */ - if ((tmo + tmp + 1) < tmp) - reset_timer_masked(); - else - tmo += tmp; - - while (get_timer_masked() < tmo) - ; /* loop till wakeup event */ -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void reset_timer_masked(void) -{ - lastdec = readl(&systimer_base->timer0value) / 1000; - timestamp = 0; -} - -ulong get_timer_masked(void) -{ - ulong now = readl(&systimer_base->timer0value) / 1000; - - if (lastdec >= now) { /* normal mode (non roll) */ - timestamp += lastdec - now; - } else { /* count down timer overflowed */ - /* - * nts = ts + ld - now - * ts = old stamp, ld = time before passing through - 1 - * now = amount of time after passing though - 1 - * nts = new "advancing time stamp" - */ - timestamp += lastdec + SYSTIMER_RELOAD - now; - } - lastdec = now; - - return timestamp; -} - void lowlevel_init(void) { } @@ -247,12 +181,17 @@ ulong get_board_rev(void){ return readl((u32 *)SYS_ID); } -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -ulong get_tbclk(void) +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Setting the address at which secondary cores start from. + * Versatile Express uses one address for all cores, so ignore corenr + */ +void smp_set_core_boot_addr(unsigned long addr, int corenr) { - return (ulong)CONFIG_SYS_HZ; + /* The SYSFLAGS register on VExpress needs to be cleared first + * by writing to the next address, since any writes to the address + * at offset 0 will only be ORed in + */ + writel(~0, CONFIG_SYSFLAGS_ADDR + 4); + writel(addr, CONFIG_SYSFLAGS_ADDR); } +#endif diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig new file mode 100644 index 0000000000..7d5e7bee8b --- /dev/null +++ b/board/armltd/vexpress64/Kconfig @@ -0,0 +1,38 @@ +if TARGET_VEXPRESS64_AEMV8A + +config SYS_BOARD + default "vexpress64" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_aemv8a" + +endif + +if TARGET_VEXPRESS64_BASE_FVP + +config SYS_BOARD + default "vexpress64" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_aemv8a" + +endif + +if TARGET_VEXPRESS64_JUNO + +config SYS_BOARD + default "vexpress64" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_aemv8a" + +endif diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS new file mode 100644 index 0000000000..0ba044d7ff --- /dev/null +++ b/board/armltd/vexpress64/MAINTAINERS @@ -0,0 +1,16 @@ +VEXPRESS64 BOARD +M: David Feng +S: Maintained +F: board/armltd/vexpress64/ +F: include/configs/vexpress_aemv8a.h +F: configs/vexpress_aemv8a_defconfig + +VEXPRESS_AEMV8A_SEMI BOARD +M: Linus Walleij +S: Maintained +F: configs/vexpress_aemv8a_semi_defconfig + +JUNO DEVELOPMENT PLATFORM BOARD +M: Linus Walleij +S: Maintained +F: configs/vexpress_aemv8a_juno_defconfig diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile new file mode 100644 index 0000000000..e009141a42 --- /dev/null +++ b/board/armltd/vexpress64/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := vexpress64.o diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c new file mode 100644 index 0000000000..58973185ec --- /dev/null +++ b/board/armltd/vexpress64/vexpress64.c @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2013 + * David Feng + * Sharma Bhupesh + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + /* + * Clear spin table so that secondary processors + * observe the correct value after waken up from wfe. + */ + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SEMIHOSTING + /* + * Please refer to doc/README.semihosting for a more complete + * description. + * + * We require that the board include file defines these env variables: + * - kernel_name + * - kernel_addr_r + * - initrd_name + * - initrd_addr_r + * - fdt_name + * - fdt_addr_r + * + * For the "fdt chosen" startup macro, this code will then define: + * - initrd_end (based on initrd_addr_r plus actual initrd_size) + * + * We will then load the kernel, initrd, and fdt into the specified + * locations in memory in a similar way that the ATF fastmodel code + * uses semihosting calls to load other boot stages and u-boot itself. + */ + + /* Env variable strings */ + char *kernel_name = getenv("kernel_name"); + char *kernel_addr_str = getenv("kernel_addr_r"); + char *initrd_name = getenv("initrd_name"); + char *initrd_addr_str = getenv("initrd_addr_r"); + char *fdt_name = getenv("fdt_name"); + char *fdt_addr_str = getenv("fdt_addr_r"); + char initrd_end_str[64]; + + /* Actual addresses converted from env variables */ + void *kernel_addr_r; + void *initrd_addr_r; + void *fdt_addr_r; + + /* Actual initrd base and size */ + unsigned long initrd_base; + unsigned long initrd_size; + + /* Space available */ + int avail; + + /* Make sure the environment variables needed are set */ + if (!(kernel_addr_str && initrd_addr_str && fdt_addr_str)) { + printf("%s: Define {kernel/initrd/fdt}_addr_r\n", __func__); + return -1; + } + if (!(kernel_name && initrd_name && fdt_name)) { + printf("%s: Define {kernel/initrd/fdt}_name\n", __func__); + return -1; + } + + /* Get exact initrd_size */ + initrd_size = smh_len(initrd_name); + if (initrd_size == -1) { + printf("%s: Can't get file size for \'%s\'\n", __func__, + initrd_name); + return -1; + } + + /* Set initrd_end */ + initrd_base = simple_strtoul(initrd_addr_str, NULL, 16); + initrd_addr_r = (void *)initrd_base; + sprintf(initrd_end_str, "0x%lx", initrd_base + initrd_size - 1); + setenv("initrd_end", initrd_end_str); + + /* Load kernel to memory */ + fdt_addr_r = (void *)simple_strtoul(fdt_addr_str, NULL, 16); + kernel_addr_r = (void *)simple_strtoul(kernel_addr_str, NULL, 16); + + /* + * The kernel must be lower in memory than fdt and loading the + * kernel must not trample the fdt or vice versa. + */ + avail = fdt_addr_r - kernel_addr_r; + if (avail < 0) { + printf("%s: fdt must be after kernel\n", __func__); + return -1; + } + smh_load(kernel_name, kernel_addr_r, avail, 1); + + /* Load fdt to memory */ + smh_load(fdt_name, fdt_addr_r, 0x20000, 1); + + /* Load initrd to memory */ + smh_load(initrd_name, initrd_addr_r, initrd_size, 1); + +#endif /* CONFIG_SEMIHOSTING */ + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} diff --git a/board/astro/mcf5373l/Kconfig b/board/astro/mcf5373l/Kconfig new file mode 100644 index 0000000000..a7c04cef83 --- /dev/null +++ b/board/astro/mcf5373l/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ASTRO_MCF5373L + +config SYS_CPU + default "mcf532x" + +config SYS_BOARD + default "mcf5373l" + +config SYS_VENDOR + default "astro" + +config SYS_CONFIG_NAME + default "astro_mcf5373l" + +endif diff --git a/board/astro/mcf5373l/MAINTAINERS b/board/astro/mcf5373l/MAINTAINERS new file mode 100644 index 0000000000..6c23da7196 --- /dev/null +++ b/board/astro/mcf5373l/MAINTAINERS @@ -0,0 +1,6 @@ +MCF5373L BOARD +M: Wolfgang Wegner +S: Maintained +F: board/astro/mcf5373l/ +F: include/configs/astro_mcf5373l.h +F: configs/astro_mcf5373l_defconfig diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile index b7497a0d7c..005d036975 100644 --- a/board/astro/mcf5373l/Makefile +++ b/board/astro/mcf5373l/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o fpga.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = mcf5373l.o fpga.o diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index c679ad7f65..d1110dfd6e 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -100,7 +100,7 @@ int altera_done_fn(int cookie) * writing the complete buffer in one function is much faster, * then calling it for every bit */ -int altera_write_fn(void *buf, size_t len, int flush, int cookie) +int altera_write_fn(const void *buf, size_t len, int flush, int cookie) { size_t bytecount = 0; gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -203,7 +203,7 @@ int astro5373l_altera_load(void) } /* Set the FPGA's PROG_B line to the specified level */ -int xilinx_pgm_fn(int assert, int flush, int cookie) +int xilinx_pgm_config_fn(int assert, int flush, int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -218,7 +218,7 @@ int xilinx_pgm_fn(int assert, int flush, int cookie) * Test the state of the active-low FPGA INIT line. Return 1 on INIT * asserted (low). */ -int xilinx_init_fn(int cookie) +int xilinx_init_config_fn(int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -226,7 +226,7 @@ int xilinx_init_fn(int cookie) } /* Test the state of the active-high FPGA DONE pin */ -int xilinx_done_fn(int cookie) +int xilinx_done_config_fn(int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -234,7 +234,7 @@ int xilinx_done_fn(int cookie) } /* Abort an FPGA operation */ -int xilinx_abort_fn(int cookie) +int xilinx_abort_config_fn(int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; /* ensure all SPI peripherals and FPGAs are deselected */ @@ -300,7 +300,7 @@ int xilinx_post_config_fn(int cookie) return rc; } -int xilinx_clk_fn(int assert_clk, int flush, int cookie) +int xilinx_clk_config_fn(int assert_clk, int flush, int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -311,7 +311,7 @@ int xilinx_clk_fn(int assert_clk, int flush, int cookie) return assert_clk; } -int xilinx_wr_fn(int assert_write, int flush, int cookie) +int xilinx_wr_config_fn(int assert_write, int flush, int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -322,7 +322,7 @@ int xilinx_wr_fn(int assert_write, int flush, int cookie) return assert_write; } -int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) +int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie) { size_t bytecount = 0; gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -363,23 +363,24 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) * relocated at runtime. * FIXME: relocation not yet working for coldfire, see below! */ -Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { +xilinx_spartan3_slave_serial_fns xilinx_fns = { xilinx_pre_config_fn, - xilinx_pgm_fn, - xilinx_clk_fn, - xilinx_init_fn, - xilinx_done_fn, - xilinx_wr_fn, + xilinx_pgm_config_fn, + xilinx_clk_config_fn, + xilinx_init_config_fn, + xilinx_done_config_fn, + xilinx_wr_config_fn, 0, - xilinx_fastwr_fn + xilinx_fastwr_config_fn }; -Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Spartan3, +xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { + {xilinx_spartan3, slave_serial, XILINX_XC3S4000_SIZE, (void *)&xilinx_fns, - 0} + 0, + &spartan3_op} }; /* Initialize the fpga. Return 1 on success, 0 on failure. */ @@ -395,12 +396,12 @@ int astro5373l_xilinx_load(void) * so set stuff here instead of static initialisation: */ xilinx_fns.pre = xilinx_pre_config_fn; - xilinx_fns.pgm = xilinx_pgm_fn; - xilinx_fns.clk = xilinx_clk_fn; - xilinx_fns.init = xilinx_init_fn; - xilinx_fns.done = xilinx_done_fn; - xilinx_fns.wr = xilinx_wr_fn; - xilinx_fns.bwr = xilinx_fastwr_fn; + xilinx_fns.pgm = xilinx_pgm_config_fn; + xilinx_fns.clk = xilinx_clk_config_fn; + xilinx_fns.init = xilinx_init_config_fn; + xilinx_fns.done = xilinx_done_config_fn; + xilinx_fns.wr = xilinx_wr_config_fn; + xilinx_fns.bwr = xilinx_fastwr_config_fn; xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; fpga_add(fpga_xilinx, &xilinx_fpga[i]); } diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index daba32c9dc..7ec7cb378f 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -79,7 +79,7 @@ phys_size_t initdram(int board_type) * (Do not rely on the SDCS register(s) being set to 0x00000000 * during reset as stated in the data sheet.) */ - return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE, + return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000 - CONFIG_SYS_SDRAM_BASE); } diff --git a/board/atc/Makefile b/board/atc/Makefile deleted file mode 100644 index aa100e4213..0000000000 --- a/board/atc/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ti113x.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/atc/atc.c b/board/atc/atc.c deleted file mode 100644 index 0038561b10..0000000000 --- a/board/atc/atc.c +++ /dev/null @@ -1,382 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ - /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ - /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ -#if 1 - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ -#else - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ -#endif - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ - /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ -#if 0 - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ -#else - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */ -#endif - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ -#if 0 - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ -#else - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */ -#endif - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ - } -}; - -/* - * UPMB initialization table - */ -#define _NOT_USED_ 0xFFFFFFFF - -static const uint rtc_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800, - 0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800, - 0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */ - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - printf ("Board: ATC\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -int misc_init_r(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint)); - memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM; - - return (0); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - ulong size8, size9; -#endif - long psize; - - psize = 8 * 1024 * 1024; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = CONFIG_SYS_PSRT; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL) "); - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/atc/flash.c b/board/atc/flash.c deleted file mode 100644 index 5a9c510c49..0000000000 --- a/board/atc/flash.c +++ /dev/null @@ -1,647 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { -#if 0 - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; -#else - ulong flashbase = CONFIG_SYS_FLASH_BASE; -#endif - - memset(&flash_info[i], 0, sizeof(flash_info_t)); - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} diff --git a/board/atc/ti113x.c b/board/atc/ti113x.c deleted file mode 100644 index c7c502ce46..0000000000 --- a/board/atc/ti113x.c +++ /dev/null @@ -1,620 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - ******************************************************************** - * - * Lots of code copied from: - * - * i82365.c 1.352 - Linux driver for Intel 82365 and compatible - * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. - * (C) 1999 David A. Hinds - */ - -#include - -#ifdef CONFIG_I82365 - -#include -#include -#include -#include - -#include -#include -#include -#include - -static struct pci_device_id supported[] = { - {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510}, - {0, 0} -}; - -#define CYCLE_TIME 120 - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev); -#endif - -typedef struct socket_info_t { - pci_dev_t dev; - u_short bcr; - u_char pci_lat, cb_lat, sub_bus, cache; - u_int cb_phys; - - socket_cap_t cap; - u_short type; - u_int flags; - ti113x_state_t state; -} socket_info_t; - -static socket_info_t socket; -static socket_state_t state; -static struct pccard_mem_map mem; -static struct pccard_io_map io; - -/*====================================================================*/ - -/* Some PCI shortcuts */ - -static int pci_readb (socket_info_t * s, int r, u_char * v) -{ - return pci_read_config_byte (s->dev, r, v); -} -static int pci_writeb (socket_info_t * s, int r, u_char v) -{ - return pci_write_config_byte (s->dev, r, v); -} -static int pci_readw (socket_info_t * s, int r, u_short * v) -{ - return pci_read_config_word (s->dev, r, v); -} -static int pci_writew (socket_info_t * s, int r, u_short v) -{ - return pci_write_config_word (s->dev, r, v); -} -static int pci_readl (socket_info_t * s, int r, u_int * v) -{ - return pci_read_config_dword (s->dev, r, v); -} -static int pci_writel (socket_info_t * s, int r, u_int v) -{ - return pci_write_config_dword (s->dev, r, v); -} - -/*====================================================================*/ - -#define cb_readb(s, r) readb((s)->cb_phys + (r)) -#define cb_readl(s, r) readl((s)->cb_phys + (r)) -#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r)) -#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) - -static u_char i365_get (socket_info_t * s, u_short reg) -{ - return cb_readb (s, 0x0800 + reg); -} - -static void i365_set (socket_info_t * s, u_short reg, u_char data) -{ - cb_writeb (s, 0x0800 + reg, data); -} - -static void i365_bset (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) | mask); -} - -static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) & ~mask); -} - -#if 0 /* not used */ -static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) -{ - u_char d = i365_get (s, reg); - - i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); -} - -static u_short i365_get_pair (socket_info_t * s, u_short reg) -{ - return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); -} -#endif /* not used */ - -static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) -{ - i365_set (s, reg, data & 0xff); - i365_set (s, reg + 1, data >> 8); -} - -/*====================================================================== - - Code to save and restore global state information for TI 1130 and - TI 1131 controllers, and to set and report global configuration - options. - -======================================================================*/ - -static void ti113x_get_state (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - - pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl); - pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl); - pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl); - pci_readb (s, TI1250_DIAGNOSTIC, &p->diag); - pci_readl (s, TI12XX_IRQMUX, &p->irqmux); -} - -static void ti113x_set_state (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - - pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl); - pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl); - pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl); - pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0); - pci_writeb (s, TI1250_DIAGNOSTIC, p->diag); - pci_writel (s, TI12XX_IRQMUX, p->irqmux); - i365_set_pair (s, TI113X_IO_OFFSET (0), 0); - i365_set_pair (s, TI113X_IO_OFFSET (1), 0); -} - -static u_int ti113x_set_opts (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - u_int mask = 0xffff; - - p->cardctl &= ~TI113X_CCR_ZVENABLE; - p->cardctl |= TI113X_CCR_SPKROUTEN; - - return mask; -} - -/*====================================================================== - - Routines to handle common CardBus options - -======================================================================*/ - -/* Default settings for PCI command configuration register */ -#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ - PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) - -static void cb_get_state (socket_info_t * s) -{ - pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); - pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); - pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); - pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); - pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); - pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); -} - -static void cb_set_state (socket_info_t * s) -{ - pci_writel (s, CB_LEGACY_MODE_BASE, 0); - pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys); - pci_writew (s, PCI_COMMAND, CMD_DFLT); - pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); - pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); - pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); - pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); - pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); - pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); -} - -static void cb_set_opts (socket_info_t * s) -{ - if (s->cache == 0) - s->cache = 8; - if (s->pci_lat == 0) - s->pci_lat = 0xa8; - if (s->cb_lat == 0) - s->cb_lat = 0xb0; -} - -/*====================================================================== - - Power control for Cardbus controllers: used both for 16-bit and - Cardbus cards. - -======================================================================*/ - -static int cb_set_power (socket_info_t * s, socket_state_t * state) -{ - u_int reg = 0; - - /* restart card voltage detection if it seems appropriate */ - if ((state->Vcc == 0) && (state->Vpp == 0) && - !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE)) - cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST); - switch (state->Vcc) { - case 0: - reg = 0; - break; - case 33: - reg = CB_SC_VCC_3V; - break; - case 50: - reg = CB_SC_VCC_5V; - break; - default: - return -1; - } - switch (state->Vpp) { - case 0: - break; - case 33: - reg |= CB_SC_VPP_3V; - break; - case 50: - reg |= CB_SC_VPP_5V; - break; - case 120: - reg |= CB_SC_VPP_12V; - break; - default: - return -1; - } - if (reg != cb_readl (s, CB_SOCKET_CONTROL)) - cb_writel (s, CB_SOCKET_CONTROL, reg); - - return 0; -} - -/*====================================================================== - - Generic routines to get and set controller options - -======================================================================*/ - -static void get_bridge_state (socket_info_t * s) -{ - ti113x_get_state (s); - cb_get_state (s); -} - -static void set_bridge_state (socket_info_t * s) -{ - cb_set_state (s); - i365_set (s, I365_GBLCTL, 0x00); - i365_set (s, I365_GENCTL, 0x00); - ti113x_set_state (s); -} - -static void set_bridge_opts (socket_info_t * s) -{ - ti113x_set_opts (s); - cb_set_opts (s); -} - -/*====================================================================*/ -#define PD67_EXT_INDEX 0x2e /* Extension index */ -#define PD67_EXT_DATA 0x2f /* Extension data */ -#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) - -#define pd67_ext_get(s, r) \ - (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) - -static int i365_get_status (socket_info_t * s, u_int * value) -{ - u_int status; - - status = i365_get (s, I365_IDENT); - status = i365_get (s, I365_STATUS); - *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; - if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { - *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; - } else { - *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; - *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; - } - *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; - *value |= (status & I365_CS_READY) ? SS_READY : 0; - *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; - - status = cb_readl (s, CB_SOCKET_STATE); - *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0; - *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0; - *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0; - *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING; - /* For now, ignore cards with unsupported voltage keys */ - if (*value & SS_XVCARD) - *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD); - - return 0; -} /* i365_get_status */ - -static int i365_set_socket (socket_info_t * s, socket_state_t * state) -{ - u_char reg; - - set_bridge_state (s); - - /* IO card, RESET flag */ - reg = 0; - reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; - reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; - i365_set (s, I365_INTCTL, reg); - - reg = I365_PWR_NORESET; - if (state->flags & SS_PWR_AUTO) - reg |= I365_PWR_AUTO; - if (state->flags & SS_OUTPUT_ENA) - reg |= I365_PWR_OUT; - - cb_set_power (s, state); - reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK); - - if (reg != i365_get (s, I365_POWER)) - i365_set (s, I365_POWER, reg); - - return 0; -} /* i365_set_socket */ - -/*====================================================================*/ - -static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) -{ - u_short base, i; - u_char map; - - debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", - mem->map, mem->flags, mem->speed, - mem->sys_start, mem->sys_stop, mem->card_start); - - map = mem->map; - if ((map > 4) || - (mem->card_start > 0x3ffffff) || - (mem->sys_start > mem->sys_stop) || - (mem->speed > 1000)) { - return -1; - } - - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); - - /* Take care of high byte, for PCI controllers */ - i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); - - base = I365_MEM (map); - i = (mem->sys_start >> 12) & 0x0fff; - if (mem->flags & MAP_16BIT) - i |= I365_MEM_16BIT; - if (mem->flags & MAP_0WS) - i |= I365_MEM_0WS; - i365_set_pair (s, base + I365_W_START, i); - - i = (mem->sys_stop >> 12) & 0x0fff; - switch (mem->speed / CYCLE_TIME) { - case 0: - break; - case 1: - i |= I365_MEM_WS0; - break; - case 2: - i |= I365_MEM_WS1; - break; - default: - i |= I365_MEM_WS1 | I365_MEM_WS0; - break; - } - i365_set_pair (s, base + I365_W_STOP, i); - - i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff; - if (mem->flags & MAP_WRPROT) - i |= I365_MEM_WRPROT; - if (mem->flags & MAP_ATTRIB) - i |= I365_MEM_REG; - i365_set_pair (s, base + I365_W_OFF, i); - - /* Turn on the window if necessary */ - if (mem->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); - return 0; -} /* i365_set_mem_map */ - -static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) -{ - u_char map, ioctl; - - map = io->map; - /* comment out: comparison is always false due to limited range of data type */ - if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ - (io->stop < io->start)) - return -1; - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); - i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); - i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); - ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); - if (io->speed) - ioctl |= I365_IOCTL_WAIT (map); - if (io->flags & MAP_0WS) - ioctl |= I365_IOCTL_0WS (map); - if (io->flags & MAP_16BIT) - ioctl |= I365_IOCTL_16BIT (map); - if (io->flags & MAP_AUTOSZ) - ioctl |= I365_IOCTL_IOCS16 (map); - i365_set (s, I365_IOCTL, ioctl); - /* Turn on the window if necessary */ - if (io->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); - return 0; -} /* i365_set_io_map */ - -/*====================================================================*/ - -static int i82365_init (void) -{ - u_int val; - int i; - - if ((socket.dev = pci_find_devices (supported, 0)) < 0) { - /* Controller not found */ - return 1; - } - debug ("i82365 Device Found!\n"); - - pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys); - socket.cb_phys &= ~0xf; - - get_bridge_state (&socket); - set_bridge_opts (&socket); - - i = i365_get_status (&socket, &val); - - if (val & SS_DETECT) { - if (val & SS_3VCARD) { - state.Vcc = state.Vpp = 33; - puts (" 3.3V card found: "); - } else if (!(val & SS_XVCARD)) { - state.Vcc = state.Vpp = 50; - puts (" 5.0V card found: "); - } else { - puts ("i82365: unsupported voltage key\n"); - state.Vcc = state.Vpp = 0; - } - } else { - /* No card inserted */ - puts ("No card\n"); - return 1; - } - - state.flags = SS_IOCARD | SS_OUTPUT_ENA; - state.csc_mask = 0; - state.io_irq = 0; - - i365_set_socket (&socket, &state); - - for (i = 500; i; i--) { - if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) - break; - udelay (1000); - } - - if (i == 0) { - /* PC Card not ready for data transfer */ - puts ("i82365 PC Card not ready for data transfer\n"); - return 1; - } - debug (" PC Card ready for data transfer: "); - - mem.map = 0; - mem.flags = MAP_ATTRIB | MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - - io.map = 0; - io.flags = MAP_AUTOSZ | MAP_ACTIVE; - io.speed = 0; - io.start = 0x0100; - io.stop = 0x010F; - i365_set_io_map (&socket, &io); - -#ifdef DEBUG - i82365_dump_regions (socket.dev); -#endif - - return 0; -} - -static void i82365_exit (void) -{ - io.map = 0; - io.flags = 0; - io.speed = 0; - io.start = 0; - io.stop = 0x1; - - i365_set_io_map (&socket, &io); - - mem.map = 0; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); - - socket.state.sysctl &= 0xFFFF00FF; - - state.Vcc = state.Vpp = 0; - - i365_set_socket (&socket, &state); -} - -int pcmcia_on (void) -{ - u_int rc; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - rc = i82365_init(); - if (rc) - goto exit; - - rc = check_ide_device(0); - if (rc == 0) - goto exit; - - i82365_exit(); - -exit: - return rc; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_off (void) -{ - printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - i82365_exit(); - - return 0; -} -#endif - -/*====================================================================== - - Debug stuff - -======================================================================*/ - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev) -{ - u_int tmp[2]; - u_int *mem = (void *) socket.cb_phys; - u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR; - u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET); - - pci_read_config_dword (dev, 0x00, tmp + 0); - pci_read_config_dword (dev, 0x80, tmp + 1); - - printf ("PCI CONF: %08X ... %08X\n", - tmp[0], tmp[1]); - printf ("PCI MEM: ... %08X ... %08X\n", - mem[0x8 / 4], mem[0x800 / 4]); - printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", - cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], - cis[0x40], cis[0x42], cis[0x44], cis[0x48]); - printf ("CIS CONF: %02X %02X %02X ...\n", - cis[0x200], cis[0x202], cis[0x204]); - printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", - ide[0], ide[1], ide[2], ide[3], - ide[4], ide[5], ide[6], ide[7]); -} -#endif /* DEBUG */ - -#endif /* CONFIG_I82365 */ diff --git a/board/atmark-techno/armadillo-800eva/Kconfig b/board/atmark-techno/armadillo-800eva/Kconfig new file mode 100644 index 0000000000..cd37dd4861 --- /dev/null +++ b/board/atmark-techno/armadillo-800eva/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ARMADILLO_800EVA + +config SYS_BOARD + default "armadillo-800eva" + +config SYS_VENDOR + default "atmark-techno" + +config SYS_CONFIG_NAME + default "armadillo-800eva" + +endif diff --git a/board/atmark-techno/armadillo-800eva/MAINTAINERS b/board/atmark-techno/armadillo-800eva/MAINTAINERS new file mode 100644 index 0000000000..6f547d82ec --- /dev/null +++ b/board/atmark-techno/armadillo-800eva/MAINTAINERS @@ -0,0 +1,6 @@ +ARMADILLO-800EVA BOARD +M: Nobuhiro Iwamatsu +S: Maintained +F: board/atmark-techno/armadillo-800eva/ +F: include/configs/armadillo-800eva.h +F: configs/armadillo-800eva_defconfig diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile index 9f9618b518..2743809e57 100644 --- a/board/atmark-techno/armadillo-800eva/Makefile +++ b/board/atmark-techno/armadillo-800eva/Makefile @@ -16,31 +16,5 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += armadillo-800eva.o -COBJS := $(COBJS-y) - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += armadillo-800eva.o diff --git a/board/atmel/at91rm9200ek/Kconfig b/board/atmel/at91rm9200ek/Kconfig new file mode 100644 index 0000000000..bad4a37da0 --- /dev/null +++ b/board/atmel/at91rm9200ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AT91RM9200EK + +config SYS_BOARD + default "at91rm9200ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "at91rm9200ek" + +endif diff --git a/board/atmel/at91rm9200ek/MAINTAINERS b/board/atmel/at91rm9200ek/MAINTAINERS new file mode 100644 index 0000000000..d2a479bbc3 --- /dev/null +++ b/board/atmel/at91rm9200ek/MAINTAINERS @@ -0,0 +1,7 @@ +AT91RM9200EK BOARD +M: Andreas Bießmann +S: Maintained +F: board/atmel/at91rm9200ek/ +F: include/configs/at91rm9200ek.h +F: configs/at91rm9200ek_defconfig +F: configs/at91rm9200ek_ram_defconfig diff --git a/board/atmel/at91rm9200ek/Makefile b/board/atmel/at91rm9200ek/Makefile index 317920976e..0530830b99 100644 --- a/board/atmel/at91rm9200ek/Makefile +++ b/board/atmel/at91rm9200ek/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += led.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += at91rm9200ek.o +obj-y += led.o diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c index 2298e3619c..6761b141fb 100644 --- a/board/atmel/at91rm9200ek/led.c +++ b/board/atmel/at91rm9200ek/led.c @@ -14,6 +14,7 @@ #include #include #include +#include /* bit mask in PIO port B */ #define GREEN_LED (1<<0) diff --git a/board/atmel/at91sam9260ek/Kconfig b/board/atmel/at91sam9260ek/Kconfig new file mode 100644 index 0000000000..fe00ed5e60 --- /dev/null +++ b/board/atmel/at91sam9260ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AT91SAM9260EK + +config SYS_BOARD + default "at91sam9260ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "at91sam9260ek" + +endif diff --git a/board/atmel/at91sam9260ek/MAINTAINERS b/board/atmel/at91sam9260ek/MAINTAINERS new file mode 100644 index 0000000000..0c7c721995 --- /dev/null +++ b/board/atmel/at91sam9260ek/MAINTAINERS @@ -0,0 +1,16 @@ +AT91SAM9260EK BOARD +M: Stelian Pop +S: Maintained +F: board/atmel/at91sam9260ek/ +F: include/configs/at91sam9260ek.h +F: configs/at91sam9260ek_dataflash_cs0_defconfig +F: configs/at91sam9260ek_dataflash_cs1_defconfig +F: configs/at91sam9260ek_nandflash_defconfig +F: configs/at91sam9g20ek_2mmc_nandflash_defconfig +F: configs/at91sam9g20ek_dataflash_cs0_defconfig +F: configs/at91sam9g20ek_dataflash_cs1_defconfig +F: configs/at91sam9g20ek_mmc_defconfig +F: configs/at91sam9g20ek_nandflash_defconfig +F: configs/at91sam9xeek_dataflash_cs0_defconfig +F: configs/at91sam9xeek_dataflash_cs1_defconfig +F: configs/at91sam9xeek_nandflash_defconfig diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile index a949000573..c6edbeee24 100644 --- a/board/atmel/at91sam9260ek/Makefile +++ b/board/atmel/at91sam9260ek/Makefile @@ -9,26 +9,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91sam9260ek.o -COBJS-y += led.o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += at91sam9260ek.o +obj-y += led.o +obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 263de49c76..7f14af1011 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include @@ -73,8 +72,6 @@ static void at91sam9260ek_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable EMAC clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); @@ -98,21 +95,7 @@ static void at91sam9260ek_macb_hw_init(void) pin_to_mask(AT91_PIN_PA28), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c index 56d811ca42..fbe15afd28 100644 --- a/board/atmel/at91sam9260ek/led.c +++ b/board/atmel/at91sam9260ek/led.c @@ -9,6 +9,7 @@ #include #include #include +#include void coloured_LED_init(void) { diff --git a/board/atmel/at91sam9261ek/Kconfig b/board/atmel/at91sam9261ek/Kconfig new file mode 100644 index 0000000000..d839c1a632 --- /dev/null +++ b/board/atmel/at91sam9261ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AT91SAM9261EK + +config SYS_BOARD + default "at91sam9261ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "at91sam9261ek" + +endif diff --git a/board/atmel/at91sam9261ek/MAINTAINERS b/board/atmel/at91sam9261ek/MAINTAINERS new file mode 100644 index 0000000000..682dfdfbf3 --- /dev/null +++ b/board/atmel/at91sam9261ek/MAINTAINERS @@ -0,0 +1,11 @@ +AT91SAM9261EK BOARD +M: Stelian Pop +S: Maintained +F: board/atmel/at91sam9261ek/ +F: include/configs/at91sam9261ek.h +F: configs/at91sam9261ek_dataflash_cs0_defconfig +F: configs/at91sam9261ek_dataflash_cs3_defconfig +F: configs/at91sam9261ek_nandflash_defconfig +F: configs/at91sam9g10ek_dataflash_cs0_defconfig +F: configs/at91sam9g10ek_dataflash_cs3_defconfig +F: configs/at91sam9g10ek_nandflash_defconfig diff --git a/board/atmel/at91sam9261ek/Makefile b/board/atmel/at91sam9261ek/Makefile index 1551aa2196..c547fed42a 100644 --- a/board/atmel/at91sam9261ek/Makefile +++ b/board/atmel/at91sam9261ek/Makefile @@ -9,26 +9,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91sam9261ek.o -COBJS-y += led.o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += at91sam9261ek.o +obj-y += led.o +obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 3e8f062f89..a301d72e8c 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -133,20 +133,20 @@ static void at91sam9261ek_dm9000_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/atmel/at91sam9263ek/Kconfig b/board/atmel/at91sam9263ek/Kconfig new file mode 100644 index 0000000000..311c504da2 --- /dev/null +++ b/board/atmel/at91sam9263ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AT91SAM9263EK + +config SYS_BOARD + default "at91sam9263ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "at91sam9263ek" + +endif diff --git a/board/atmel/at91sam9263ek/MAINTAINERS b/board/atmel/at91sam9263ek/MAINTAINERS new file mode 100644 index 0000000000..3b4b654bfb --- /dev/null +++ b/board/atmel/at91sam9263ek/MAINTAINERS @@ -0,0 +1,10 @@ +AT91SAM9263EK BOARD +M: Stelian Pop +S: Maintained +F: board/atmel/at91sam9263ek/ +F: include/configs/at91sam9263ek.h +F: configs/at91sam9263ek_dataflash_defconfig +F: configs/at91sam9263ek_dataflash_cs0_defconfig +F: configs/at91sam9263ek_nandflash_defconfig +F: configs/at91sam9263ek_norflash_defconfig +F: configs/at91sam9263ek_norflash_boot_defconfig diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile index fdb53d3417..7b31f18e4f 100644 --- a/board/atmel/at91sam9263ek/Makefile +++ b/board/atmel/at91sam9263ek/Makefile @@ -9,26 +9,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91sam9263ek.o -COBJS-y += led.o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += at91sam9263ek.o +obj-y += led.o +obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 2e9246f31c..927adb0d38 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -7,12 +7,11 @@ */ #include -#include +#include #include #include #include #include -#include #include #include #include @@ -25,6 +24,7 @@ #include #endif #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -82,10 +82,9 @@ static void at91sam9263ek_nand_hw_init(void) #ifdef CONFIG_MACB static void at91sam9263ek_macb_hw_init(void) { - unsigned long erstl; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ writel(1 << ATMEL_ID_EMAC, &pmc->pcer); @@ -97,23 +96,10 @@ static void at91sam9263ek_macb_hw_init(void) * * PHY has internal pull-down */ - writel(1 << 25, &pio->pioc.pudr); writel((1 << 25) | (1 <<26), &pio->pioe.pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(1 << 25, &pio->pioc.puer); @@ -125,20 +111,20 @@ static void at91sam9263ek_macb_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -229,6 +215,15 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif + int board_early_init_f(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; diff --git a/board/atmel/at91sam9m10g45ek/Kconfig b/board/atmel/at91sam9m10g45ek/Kconfig new file mode 100644 index 0000000000..1bc086a483 --- /dev/null +++ b/board/atmel/at91sam9m10g45ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AT91SAM9M10G45EK + +config SYS_BOARD + default "at91sam9m10g45ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "at91sam9m10g45ek" + +endif diff --git a/board/atmel/at91sam9m10g45ek/MAINTAINERS b/board/atmel/at91sam9m10g45ek/MAINTAINERS new file mode 100644 index 0000000000..6389e6ac61 --- /dev/null +++ b/board/atmel/at91sam9m10g45ek/MAINTAINERS @@ -0,0 +1,7 @@ +AT91SAM9M10G45EK BOARD +M: Bo Shen +S: Maintained +F: board/atmel/at91sam9m10g45ek/ +F: include/configs/at91sam9m10g45ek.h +F: configs/at91sam9m10g45ek_mmc_defconfig +F: configs/at91sam9m10g45ek_nandflash_defconfig diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile index 84f613bcc9..e5448ecc67 100644 --- a/board/atmel/at91sam9m10g45ek/Makefile +++ b/board/atmel/at91sam9m10g45ek/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91sam9m10g45ek.o -COBJS-y += led.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += at91sam9m10g45ek.o +obj-y += led.o diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 6a071f6b7d..b807ef9a42 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -12,11 +12,11 @@ #include #include #include -#include #include #include #include #include +#include #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include #endif @@ -88,8 +88,6 @@ static void at91sam9m10g45ek_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable clock */ writel(1 << ATMEL_ID_EMAC, &pmc->pcer); @@ -107,21 +105,7 @@ static void at91sam9m10g45ek_macb_hw_init(void) pin_to_mask(AT91_PIN_PA13), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA15) | @@ -137,20 +121,20 @@ static void at91sam9m10g45ek_macb_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 480, - vl_row: 272, - vl_clk: 9000000, - vl_sync: ATMEL_LCDC_INVLINE_NORMAL | - ATMEL_LCDC_INVFRAME_NORMAL, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 45, - vl_left_margin: 1, - vl_right_margin:1, - vl_vsync_len: 1, - vl_upper_margin:40, - vl_lower_margin:1, - mmio : ATMEL_BASE_LCDC, + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | + ATMEL_LCDC_INVFRAME_NORMAL, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 45, + .vl_left_margin = 1, + .vl_right_margin = 1, + .vl_vsync_len = 1, + .vl_upper_margin = 40, + .vl_lower_margin = 1, + .mmio = ATMEL_BASE_LCDC, }; @@ -234,6 +218,15 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI0); +} +#endif + int board_early_init_f(void) { at91_seriald_hw_init(); diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/atmel/at91sam9m10g45ek/config.mk deleted file mode 100644 index 9d3c5ae277..0000000000 --- a/board/atmel/at91sam9m10g45ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x73f00000 diff --git a/board/atmel/at91sam9n12ek/Kconfig b/board/atmel/at91sam9n12ek/Kconfig new file mode 100644 index 0000000000..cf1d1a3670 --- /dev/null +++ b/board/atmel/at91sam9n12ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AT91SAM9N12EK + +config SYS_BOARD + default "at91sam9n12ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "at91sam9n12ek" + +endif diff --git a/board/atmel/at91sam9n12ek/MAINTAINERS b/board/atmel/at91sam9n12ek/MAINTAINERS new file mode 100644 index 0000000000..82a91928c5 --- /dev/null +++ b/board/atmel/at91sam9n12ek/MAINTAINERS @@ -0,0 +1,8 @@ +AT91SAM9N12EK BOARD +M: Josh Wu +S: Maintained +F: board/atmel/at91sam9n12ek/ +F: include/configs/at91sam9n12ek.h +F: configs/at91sam9n12ek_mmc_defconfig +F: configs/at91sam9n12ek_nandflash_defconfig +F: configs/at91sam9n12ek_spiflash_defconfig diff --git a/board/atmel/at91sam9n12ek/Makefile b/board/atmel/at91sam9n12ek/Makefile index 859817f670..9f069ca74a 100644 --- a/board/atmel/at91sam9n12ek/Makefile +++ b/board/atmel/at91sam9n12ek/Makefile @@ -13,24 +13,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91sam9n12ek.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += at91sam9n12ek.o diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 2ec32ebc21..9adc9920b4 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -199,6 +199,13 @@ void at91sam9n12ek_ks8851_hw_init(void) } #endif +#ifdef CONFIG_USB_ATMEL +void at91sam9n12ek_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTB, 7, 0); +} +#endif + int board_early_init_f(void) { /* Enable clocks for all PIOs */ @@ -230,6 +237,10 @@ int board_init(void) at91sam9n12ek_ks8851_hw_init(); #endif +#ifdef CONFIG_USB_ATMEL + at91sam9n12ek_usb_hw_init(); +#endif + return 0; } diff --git a/board/atmel/at91sam9rlek/Kconfig b/board/atmel/at91sam9rlek/Kconfig new file mode 100644 index 0000000000..438d300421 --- /dev/null +++ b/board/atmel/at91sam9rlek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AT91SAM9RLEK + +config SYS_BOARD + default "at91sam9rlek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "at91sam9rlek" + +endif diff --git a/board/atmel/at91sam9rlek/MAINTAINERS b/board/atmel/at91sam9rlek/MAINTAINERS new file mode 100644 index 0000000000..7dd8ef79ee --- /dev/null +++ b/board/atmel/at91sam9rlek/MAINTAINERS @@ -0,0 +1,7 @@ +AT91SAM9RLEK BOARD +M: Stelian Pop +S: Maintained +F: board/atmel/at91sam9rlek/ +F: include/configs/at91sam9rlek.h +F: configs/at91sam9rlek_dataflash_defconfig +F: configs/at91sam9rlek_nandflash_defconfig diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile index 7f6ea90a25..51daf8d30c 100644 --- a/board/atmel/at91sam9rlek/Makefile +++ b/board/atmel/at91sam9rlek/Makefile @@ -9,26 +9,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91sam9rlek.o -COBJS-y += led.o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += at91sam9rlek.o +obj-y += led.o +obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index c700a9076b..56ca1d4f7e 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -78,20 +78,20 @@ static void at91sam9rlek_nand_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/atmel/at91sam9x5ek/Kconfig b/board/atmel/at91sam9x5ek/Kconfig new file mode 100644 index 0000000000..5c5ec61577 --- /dev/null +++ b/board/atmel/at91sam9x5ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AT91SAM9X5EK + +config SYS_BOARD + default "at91sam9x5ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "at91sam9x5ek" + +endif diff --git a/board/atmel/at91sam9x5ek/MAINTAINERS b/board/atmel/at91sam9x5ek/MAINTAINERS new file mode 100644 index 0000000000..5fea4890db --- /dev/null +++ b/board/atmel/at91sam9x5ek/MAINTAINERS @@ -0,0 +1,9 @@ +AT91SAM9X5EK BOARD +M: Bo Shen +S: Maintained +F: board/atmel/at91sam9x5ek/ +F: include/configs/at91sam9x5ek.h +F: configs/at91sam9x5ek_dataflash_defconfig +F: configs/at91sam9x5ek_mmc_defconfig +F: configs/at91sam9x5ek_nandflash_defconfig +F: configs/at91sam9x5ek_spiflash_defconfig diff --git a/board/atmel/at91sam9x5ek/Makefile b/board/atmel/at91sam9x5ek/Makefile index e8f19ea0d4..5c42b6fe86 100644 --- a/board/atmel/at91sam9x5ek/Makefile +++ b/board/atmel/at91sam9x5ek/Makefile @@ -13,24 +13,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91sam9x5ek.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += at91sam9x5ek.o diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 6f67c34a53..17a2a40b4b 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -271,7 +271,6 @@ int board_init(void) #endif #ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 0); at91_spi0_hw_init(1 << 4); #endif diff --git a/board/atmel/at91sam9x5ek/config.mk b/board/atmel/at91sam9x5ek/config.mk deleted file mode 100644 index 6589a12a93..0000000000 --- a/board/atmel/at91sam9x5ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x26f00000 diff --git a/board/atmel/atngw100/Kconfig b/board/atmel/atngw100/Kconfig new file mode 100644 index 0000000000..28037b67b4 --- /dev/null +++ b/board/atmel/atngw100/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ATNGW100 + +config SYS_BOARD + default "atngw100" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "atngw100" + +endif diff --git a/board/atmel/atngw100/MAINTAINERS b/board/atmel/atngw100/MAINTAINERS new file mode 100644 index 0000000000..1c319f66b4 --- /dev/null +++ b/board/atmel/atngw100/MAINTAINERS @@ -0,0 +1,6 @@ +ATNGW100 BOARD +#M: Haavard Skinnemoen +S: Orphan (since 2014-06) +F: board/atmel/atngw100/ +F: include/configs/atngw100.h +F: configs/atngw100_defconfig diff --git a/board/atmel/atngw100/Makefile b/board/atmel/atngw100/Makefile index 955a9c558b..f9b93c9738 100644 --- a/board/atmel/atngw100/Makefile +++ b/board/atmel/atngw100/Makefile @@ -3,23 +3,4 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := atngw100.o diff --git a/board/atmel/atngw100mkii/Kconfig b/board/atmel/atngw100mkii/Kconfig new file mode 100644 index 0000000000..ca04269080 --- /dev/null +++ b/board/atmel/atngw100mkii/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ATNGW100MKII + +config SYS_BOARD + default "atngw100mkii" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "atngw100mkii" + +endif diff --git a/board/atmel/atngw100mkii/MAINTAINERS b/board/atmel/atngw100mkii/MAINTAINERS new file mode 100644 index 0000000000..212363e4cf --- /dev/null +++ b/board/atmel/atngw100mkii/MAINTAINERS @@ -0,0 +1,6 @@ +ATNGW100MKII BOARD +M: Andreas Bießmann +S: Maintained +F: board/atmel/atngw100mkii/ +F: include/configs/atngw100mkii.h +F: configs/atngw100mkii_defconfig diff --git a/board/atmel/atngw100mkii/Makefile b/board/atmel/atngw100mkii/Makefile index 955a9c558b..90bf5bc84e 100644 --- a/board/atmel/atngw100mkii/Makefile +++ b/board/atmel/atngw100mkii/Makefile @@ -3,23 +3,4 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := atngw100mkii.o diff --git a/board/atmel/atstk1000/Kconfig b/board/atmel/atstk1000/Kconfig new file mode 100644 index 0000000000..6d4151453f --- /dev/null +++ b/board/atmel/atstk1000/Kconfig @@ -0,0 +1,63 @@ +if TARGET_ATSTK1002 + +config SYS_BOARD + default "atstk1000" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "atstk1002" + +endif + +if TARGET_ATSTK1003 + +config SYS_BOARD + default "atstk1000" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "atstk1003" + +endif + +if TARGET_ATSTK1004 + +config SYS_BOARD + default "atstk1000" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "atstk1004" + +endif + +if TARGET_ATSTK1006 + +config SYS_BOARD + default "atstk1000" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "atstk1006" + +endif diff --git a/board/atmel/atstk1000/MAINTAINERS b/board/atmel/atstk1000/MAINTAINERS new file mode 100644 index 0000000000..378e1b3dbc --- /dev/null +++ b/board/atmel/atstk1000/MAINTAINERS @@ -0,0 +1,12 @@ +ATSTK1000 BOARD +#M: Haavard Skinnemoen +S: Orphan (since 2014-06) +F: board/atmel/atstk1000/ +F: include/configs/atstk1002.h +F: configs/atstk1002_defconfig +F: include/configs/atstk1003.h +F: configs/atstk1003_defconfig +F: include/configs/atstk1004.h +F: configs/atstk1004_defconfig +F: include/configs/atstk1006.h +F: configs/atstk1006_defconfig diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile index 4eab5a789e..ad76631b97 100644 --- a/board/atmel/atstk1000/Makefile +++ b/board/atmel/atstk1000/Makefile @@ -6,23 +6,4 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += atstk1000.o diff --git a/board/atmel/sama5d3_xplained/Kconfig b/board/atmel/sama5d3_xplained/Kconfig new file mode 100644 index 0000000000..0ba8a7bf93 --- /dev/null +++ b/board/atmel/sama5d3_xplained/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D3_XPLAINED + +config SYS_BOARD + default "sama5d3_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d3_xplained" + +endif diff --git a/board/atmel/sama5d3_xplained/MAINTAINERS b/board/atmel/sama5d3_xplained/MAINTAINERS new file mode 100644 index 0000000000..8a09c19c85 --- /dev/null +++ b/board/atmel/sama5d3_xplained/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D3_XPLAINED BOARD +M: Bo Shen +S: Maintained +F: board/atmel/sama5d3_xplained/ +F: include/configs/sama5d3_xplained.h +F: configs/sama5d3_xplained_mmc_defconfig +F: configs/sama5d3_xplained_nandflash_defconfig diff --git a/board/atmel/sama5d3_xplained/Makefile b/board/atmel/sama5d3_xplained/Makefile new file mode 100644 index 0000000000..ec82b06990 --- /dev/null +++ b/board/atmel/sama5d3_xplained/Makefile @@ -0,0 +1,15 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# (C) Copyright 2014 +# Bo Shen +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d3_xplained.o diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c new file mode 100644 index 0000000000..92ed4e81d3 --- /dev/null +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2014 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_NAND_ATMEL +void sama5d3_xplained_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | + AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | + AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d3_xplained_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 3, 0); + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +static void sama5d3_xplained_mci0_hw_init(void) +{ + at91_mci_hw_init(); + + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ +} +#endif + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + sama5d3_xplained_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d3_xplained_usb_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d3_xplained_mci0_hw_init(); +#endif +#ifdef CONFIG_MACB + at91_gmac_hw_init(); + at91_macb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_MACB + macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); + macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); +#endif + return 0; +} + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + atmel_mci_init((void *)ATMEL_BASE_MCI0); + + return 0; +} +#endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + sama5d3_xplained_mci0_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d3_xplained_nand_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ENRDM_ON | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + /* + * As the DDR2-SDRAm device requires a refresh time is 7.8125us + * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks + */ + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr ddr2; + + ddr2_conf(&ddr2); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(0x4, &pmc->scer); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(43) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x3 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_MDIV_4 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/atmel/sama5d3xek/Kconfig b/board/atmel/sama5d3xek/Kconfig new file mode 100644 index 0000000000..2a9ed23ecf --- /dev/null +++ b/board/atmel/sama5d3xek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D3XEK + +config SYS_BOARD + default "sama5d3xek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d3xek" + +endif diff --git a/board/atmel/sama5d3xek/MAINTAINERS b/board/atmel/sama5d3xek/MAINTAINERS new file mode 100644 index 0000000000..560303caad --- /dev/null +++ b/board/atmel/sama5d3xek/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D3XEK BOARD +M: Bo Shen +S: Maintained +F: board/atmel/sama5d3xek/ +F: include/configs/sama5d3xek.h +F: configs/sama5d3xek_mmc_defconfig +F: configs/sama5d3xek_nandflash_defconfig +F: configs/sama5d3xek_spiflash_defconfig diff --git a/board/atmel/sama5d3xek/Makefile b/board/atmel/sama5d3xek/Makefile index 384ca3f791..7ff74810ce 100644 --- a/board/atmel/sama5d3xek/Makefile +++ b/board/atmel/sama5d3xek/Makefile @@ -12,24 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += sama5d3xek.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += sama5d3xek.o diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 4a309ad17f..cf6ed8b94c 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -15,10 +15,19 @@ #include #include #include -#include +#include #include +#include +#include #include #include +#include +#include +#include + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -59,6 +68,61 @@ void sama5d3xek_nand_hw_init(void) } #endif +#ifndef CONFIG_SYS_NO_FLASH +static void sama5d3xek_nor_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS0 for NOR flash */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[0].setup); + writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) | + AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11), + &smc->cs[0].pulse); + writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14), + &smc->cs[0].cycle); + writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) | + AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) | + AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)| + AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[0].mode); + + /* Address pin (A1 ~ A23) configuration */ + at91_set_a_periph(AT91_PIO_PORTE, 1, 0); + at91_set_a_periph(AT91_PIO_PORTE, 2, 0); + at91_set_a_periph(AT91_PIO_PORTE, 3, 0); + at91_set_a_periph(AT91_PIO_PORTE, 4, 0); + at91_set_a_periph(AT91_PIO_PORTE, 5, 0); + at91_set_a_periph(AT91_PIO_PORTE, 6, 0); + at91_set_a_periph(AT91_PIO_PORTE, 7, 0); + at91_set_a_periph(AT91_PIO_PORTE, 8, 0); + at91_set_a_periph(AT91_PIO_PORTE, 9, 0); + at91_set_a_periph(AT91_PIO_PORTE, 10, 0); + at91_set_a_periph(AT91_PIO_PORTE, 11, 0); + at91_set_a_periph(AT91_PIO_PORTE, 12, 0); + at91_set_a_periph(AT91_PIO_PORTE, 13, 0); + at91_set_a_periph(AT91_PIO_PORTE, 14, 0); + at91_set_a_periph(AT91_PIO_PORTE, 15, 0); + at91_set_a_periph(AT91_PIO_PORTE, 16, 0); + at91_set_a_periph(AT91_PIO_PORTE, 17, 0); + at91_set_a_periph(AT91_PIO_PORTE, 18, 0); + at91_set_a_periph(AT91_PIO_PORTE, 19, 0); + at91_set_a_periph(AT91_PIO_PORTE, 20, 0); + at91_set_a_periph(AT91_PIO_PORTE, 21, 0); + at91_set_a_periph(AT91_PIO_PORTE, 22, 0); + at91_set_a_periph(AT91_PIO_PORTE, 23, 0); + /* CS0 pin configuration */ + at91_set_a_periph(AT91_PIO_PORTE, 26, 0); +} +#endif + #ifdef CONFIG_CMD_USB static void sama5d3xek_usb_hw_init(void) { @@ -82,7 +146,6 @@ vidinfo_t panel_info = { .vl_col = 800, .vl_row = 480, .vl_clk = 24000000, - .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL, .vl_bpix = LCD_BPP, .vl_tft = 1, .vl_hsync_len = 128, @@ -126,7 +189,8 @@ static void sama5d3xek_lcd_hw_init(void) void lcd_show_board_info(void) { - ulong dram_size, nand_size; + ulong dram_size; + uint64_t nand_size; int i; char temp[32]; @@ -145,7 +209,7 @@ void lcd_show_board_info(void) for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += nand_info[i].size; #endif - lcd_printf("%ld MB SDRAM, %ld MB NAND\n", + lcd_printf("%ld MB SDRAM, %lld MB NAND\n", dram_size >> 20, nand_size >> 20); } #endif /* CONFIG_LCD_INFO */ @@ -153,6 +217,12 @@ void lcd_show_board_info(void) int board_early_init_f(void) { + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + at91_seriald_hw_init(); return 0; @@ -166,9 +236,15 @@ int board_init(void) #ifdef CONFIG_NAND_ATMEL sama5d3xek_nand_hw_init(); #endif +#ifndef CONFIG_SYS_NO_FLASH + sama5d3xek_nor_hw_init(); +#endif #ifdef CONFIG_CMD_USB sama5d3xek_usb_hw_init(); #endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif #ifdef CONFIG_GENERIC_ATMEL_MCI sama5d3xek_mci_hw_init(); #endif @@ -178,6 +254,8 @@ int board_init(void) #ifdef CONFIG_MACB if (has_emac()) at91_macb_hw_init(); + if (has_gmac()) + at91_gmac_hw_init(); #endif #ifdef CONFIG_LCD if (has_lcdc()) @@ -193,6 +271,31 @@ int dram_init(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + /* board specific timings for GMAC */ + if (has_gmac()) { + /* rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x2222); + /* tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x2222); + /* rx/tx clock delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf2f4); + } + + /* always run the PHY's config routine */ + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + int board_eth_init(bd_t *bis) { int rc = 0; @@ -200,6 +303,14 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_MACB if (has_emac()) rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); + if (has_gmac()) + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif #endif return rc; @@ -257,3 +368,89 @@ void spi_cs_deactivate(struct spi_slave *slave) } } #endif /* CONFIG_ATMEL_SPI */ + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + sama5d3xek_mci_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d3xek_nand_hw_init(); +#elif CONFIG_SYS_USE_SERIALFLASH + at91_spi0_hw_init(1 << 0); +#endif +} + +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ENRDM_ON | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + /* + * As the DDR2-SDRAm device requires a refresh time is 7.8125us + * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks + */ + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr ddr2; + + ddr2_conf(&ddr2); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(0x4, &pmc->scer); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(43) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x3 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_MDIV_4 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/atmel/sama5d4_xplained/Kconfig b/board/atmel/sama5d4_xplained/Kconfig new file mode 100644 index 0000000000..f320a68d30 --- /dev/null +++ b/board/atmel/sama5d4_xplained/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D4_XPLAINED + +config SYS_BOARD + default "sama5d4_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d4_xplained" + +endif diff --git a/board/atmel/sama5d4_xplained/MAINTAINERS b/board/atmel/sama5d4_xplained/MAINTAINERS new file mode 100644 index 0000000000..035f64c6ea --- /dev/null +++ b/board/atmel/sama5d4_xplained/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D4 XPLAINED ULTRA BOARD +M: Bo Shen +S: Maintained +F: board/atmel/sama5d4_xplained/ +F: include/configs/sama5d4_xplained.h +F: configs/sama5d4_xplained_mmc_defconfig +F: configs/sama5d4_xplained_nandflash_defconfig +F: configs/sama5d4_xplained_spiflash_defconfig diff --git a/board/atmel/sama5d4_xplained/Makefile b/board/atmel/sama5d4_xplained/Makefile new file mode 100644 index 0000000000..c59b12df24 --- /dev/null +++ b/board/atmel/sama5d4_xplained/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2014 Atmel +# Bo Shen +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d4_xplained.o diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c new file mode 100644 index 0000000000..1c5b92c8b5 --- /dev/null +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2014 Atmel + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ATMEL_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); +} + +static void sama5d4_xplained_spi0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_SPI0); +} +#endif /* CONFIG_ATMEL_SPI */ + +#ifdef CONFIG_NAND_ATMEL +static void sama5d4_xplained_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d4_xplained_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 11, 1); + at91_set_pio_output(AT91_PIO_PORTE, 14, 1); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_hsync_len = 41, + .vl_left_margin = 2, + .vl_right_margin = 2, + .vl_vsync_len = 11, + .vl_upper_margin = 2, + .vl_lower_margin = 2, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void sama5d4_xplained_lcd_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf("2014 ATMEL Corp\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; +#ifdef CONFIG_NAND_ATMEL + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; +#endif + lcd_printf("%ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, nand_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ + +#endif /* CONFIG_LCD */ + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void sama5d4_xplained_mci1_hw_init(void) +{ + at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the interanl pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI1); +} + +int board_mmc_init(bd_t *bis) +{ + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif /* CONFIG_GENERIC_ATMEL_MCI */ + +#ifdef CONFIG_MACB +void sama5d4_xplained_macb0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC0); +} +#endif + +static void sama5d4_xplained_serial3_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + sama5d4_xplained_serial3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + sama5d4_xplained_spi0_hw_init(); +#endif +#ifdef CONFIG_NAND_ATMEL + sama5d4_xplained_nand_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d4_xplained_mci1_hw_init(); +#endif +#ifdef CONFIG_MACB + sama5d4_xplained_macb0_hw_init(); +#endif +#ifdef CONFIG_LCD + sama5d4_xplained_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d4_xplained_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} diff --git a/board/atmel/sama5d4ek/Kconfig b/board/atmel/sama5d4ek/Kconfig new file mode 100644 index 0000000000..7dc569c411 --- /dev/null +++ b/board/atmel/sama5d4ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D4EK + +config SYS_BOARD + default "sama5d4ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d4ek" + +endif diff --git a/board/atmel/sama5d4ek/MAINTAINERS b/board/atmel/sama5d4ek/MAINTAINERS new file mode 100644 index 0000000000..afe88ddead --- /dev/null +++ b/board/atmel/sama5d4ek/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D4EK BOARD +M: Bo Shen +S: Maintained +F: board/atmel/sama5d4ek/ +F: include/configs/sama5d4ek.h +F: configs/sama5d4ek_mmc_defconfig +F: configs/sama5d4ek_nandflash_defconfig +F: configs/sama5d4ek_spiflash_defconfig diff --git a/board/atmel/sama5d4ek/Makefile b/board/atmel/sama5d4ek/Makefile new file mode 100644 index 0000000000..55823ba77b --- /dev/null +++ b/board/atmel/sama5d4ek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2014 Atmel +# Bo Shen +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d4ek.o diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c new file mode 100644 index 0000000000..d8ff648957 --- /dev/null +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2014 Atmel + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ATMEL_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); +} + +static void sama5d4ek_spi0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_SPI0); +} +#endif /* CONFIG_ATMEL_SPI */ + +#ifdef CONFIG_NAND_ATMEL +static void sama5d4ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d4ek_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 11, 0); + at91_set_pio_output(AT91_PIO_PORTE, 12, 0); + at91_set_pio_output(AT91_PIO_PORTE, 10, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 800, + .vl_row = 480, + .vl_clk = 33260000, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 128, + .vl_right_margin = 0, + .vl_vsync_len = 5, + .vl_upper_margin = 23, + .vl_lower_margin = 22, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void sama5d4ek_lcd_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf("2014 ATMEL Corp\n"); + lcd_printf("at91@atmel.com\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; +#ifdef CONFIG_NAND_ATMEL + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; +#endif + lcd_printf("%ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, nand_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ + +#endif /* CONFIG_LCD */ + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void sama5d4ek_mci1_hw_init(void) +{ + at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the interanl pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI1); +} + +int board_mmc_init(bd_t *bis) +{ + /* Enable power for MCI1 interface */ + at91_set_pio_output(AT91_PIO_PORTE, 15, 0); + + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif /* CONFIG_GENERIC_ATMEL_MCI */ + +#ifdef CONFIG_MACB +void sama5d4ek_macb0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC0); +} +#endif + +static void sama5d4ek_serial3_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + sama5d4ek_serial3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + sama5d4ek_spi0_hw_init(); +#endif +#ifdef CONFIG_NAND_ATMEL + sama5d4ek_nand_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d4ek_mci1_hw_init(); +#endif +#ifdef CONFIG_MACB + sama5d4ek_macb0_hw_init(); +#endif +#ifdef CONFIG_LCD + sama5d4ek_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d4ek_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h new file mode 100644 index 0000000000..00634f17aa --- /dev/null +++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h @@ -0,0 +1,385 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_ +#define _PINMUX_CONFIG_TAMONTEN_NG_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config tamonten_ng_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS6_N_PI3, RSVD1, UP, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* UART1 */ + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT), + + /* UART2 */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + + /* UART3 */ + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + + /* UART4 */ + DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), + + /* DAP */ + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), + + /* I2S1 */ + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), + + /* SPDIF */ + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), + + /* I2S2 */ + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + + /* DAP4 */ + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + + /* Tamonten GPIO */ + DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N_PW2, RSVD1, NORMAL, NORMAL, INPUT), + + /* LCD */ + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), + + /* BT656 */ + LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* GPIOs */ + DEFAULT_PINMUX(PU5, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, INPUT), + + /* LCD BL */ + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10_PH2, RSVD4, NORMAL, NORMAL, OUTPUT), + + /* SPI4 */ + DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT), + + /* Video input GPIO */ + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, NORMAL, INPUT), + + /* Sensor GPIO */ + DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, NORMAL, INPUT), + + /* JTAG */ + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* Power controls */ + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, INPUT), + + /* SPI1 */ + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + + /* PMU */ + DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT), + + /* PCI */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), + + /* HDMI */ + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), +}; + +static struct pmux_pingrp_config unused_pins_lowpower[] = { + /* UART1 - NC */ + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT), + + /* UART2 - NC */ + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + + /* DAP - NC */ + DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_OUT_PEE0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, NORMAL, INPUT), + + /* DAP4 - NC */ + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + + /* Tamonten GPIO - NC */ + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + + /* BT656 - NC */ + LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* GPIO - NC */ + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU4, RSVD1, NORMAL, NORMAL, INPUT), + + /* Video input - NC */ + DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB5, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, RSVD1, NORMAL, NORMAL, INPUT), + + /* KBC keys - NC */ + DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), + + /* PMU - NC */ + DEFAULT_PINMUX(CLK_32K_OUT_PA0, RSVD1, NORMAL, NORMAL, INPUT), + + /* Power rails GPIO - NC */ + DEFAULT_PINMUX(SPI2_SCK_PX2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB4, RSVD1, NORMAL, NORMAL, INPUT), + + /* Others - NC */ + DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), +}; + +static struct pmux_drvgrp_config tamonten_ng_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */ diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c new file mode 100644 index 0000000000..1704627112 --- /dev/null +++ b/board/avionic-design/common/tamonten-ng.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "pinmux-config-tamonten-ng.h" +#include + +#define PMU_I2C_ADDRESS 0x2D + +#define PMU_REG_LDO5 0x32 + +#define PMU_REG_LDO_HIGH_POWER 1 + +/* Voltage selection for the LDOs with 100mV resolution */ +#define PMU_REG_LDO_SEL_100(mV) ((((mV - 1000) / 100) + 2) << 2) + +#define PMU_REG_LDO_100(st, mV) (PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV)) + +#define PMU_LDO5(st, mV) PMU_REG_LDO_100(st, mV) + +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tamonten_ng_pinmux_common, + ARRAY_SIZE(tamonten_ng_pinmux_common)); + pinmux_config_pingrp_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + pinmux_config_drvgrp_table(tamonten_ng_padctrl, + ARRAY_SIZE(tamonten_ng_padctrl)); +} + +void gpio_early_init(void) +{ + /* Turn on the alive signal */ + gpio_request(GPIO_PV2, "ALIVE"); + gpio_direction_output(GPIO_PV2, 1); + + /* Remove the reset on the external periph */ + gpio_request(GPIO_PI4, "nRST_PERIPH"); + gpio_direction_output(GPIO_PI4, 1); +} + +void pmu_write(uchar reg, uchar data) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, 1, &dev); + if (ret) { + debug("%s: Cannot find PMIC I2C chip\n", __func__); + return; + } + dm_i2c_write(dev, reg, &data, 1); +} + +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + /* Enable LDO5 with 3.3v for SDMMC3 */ + pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300)); + + /* Switch the power on */ + gpio_request(GPIO_PJ2, "EN_3V3_EMMC"); + gpio_direction_output(GPIO_PJ2, 1); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO1 power rail */ + board_sdmmc_voltage_init(); +} diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 177d185ea8..9c8677943a 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -37,8 +37,8 @@ void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); /* for write-protect GPIO PI6 */ - pinmux_tristate_disable(PINGRP_ATA); + pinmux_tristate_disable(PMUX_PINGRP_ATA); /* for CD GPIO PH2 */ - pinmux_tristate_disable(PINGRP_ATD); + pinmux_tristate_disable(PMUX_PINGRP_ATD); } #endif diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig new file mode 100644 index 0000000000..267647cb41 --- /dev/null +++ b/board/avionic-design/medcom-wide/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MEDCOM_WIDE + +config SYS_BOARD + default "medcom-wide" + +config SYS_VENDOR + default "avionic-design" + +config SYS_CONFIG_NAME + default "medcom-wide" + +endif diff --git a/board/avionic-design/medcom-wide/MAINTAINERS b/board/avionic-design/medcom-wide/MAINTAINERS new file mode 100644 index 0000000000..0a00fcf719 --- /dev/null +++ b/board/avionic-design/medcom-wide/MAINTAINERS @@ -0,0 +1,6 @@ +MEDCOM-WIDE BOARD +M: Alban Bedel +S: Maintained +F: board/avionic-design/medcom-wide/ +F: include/configs/medcom-wide.h +F: configs/medcom-wide_defconfig diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile index 3077319ae2..bcf7ccfe2a 100644 --- a/board/avionic-design/medcom-wide/Makefile +++ b/board/avionic-design/medcom-wide/Makefile @@ -7,28 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := ../common/tamonten.o -$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := ../common/tamonten.o - -include ../../nvidia/common/common.mk - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig new file mode 100644 index 0000000000..09a3ac940d --- /dev/null +++ b/board/avionic-design/plutux/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PLUTUX + +config SYS_BOARD + default "plutux" + +config SYS_VENDOR + default "avionic-design" + +config SYS_CONFIG_NAME + default "plutux" + +endif diff --git a/board/avionic-design/plutux/MAINTAINERS b/board/avionic-design/plutux/MAINTAINERS new file mode 100644 index 0000000000..e8ef5096e5 --- /dev/null +++ b/board/avionic-design/plutux/MAINTAINERS @@ -0,0 +1,6 @@ +PLUTUX BOARD +M: Alban Bedel +S: Maintained +F: board/avionic-design/plutux/ +F: include/configs/plutux.h +F: configs/plutux_defconfig diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index 3077319ae2..bcf7ccfe2a 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -7,28 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := ../common/tamonten.o -$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := ../common/tamonten.o - -include ../../nvidia/common/common.mk - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig new file mode 100644 index 0000000000..36a0cec1be --- /dev/null +++ b/board/avionic-design/tec-ng/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TEC_NG + +config SYS_BOARD + default "tec-ng" + +config SYS_VENDOR + default "avionic-design" + +config SYS_CONFIG_NAME + default "tec-ng" + +endif diff --git a/board/avionic-design/tec-ng/MAINTAINERS b/board/avionic-design/tec-ng/MAINTAINERS new file mode 100644 index 0000000000..5cbdf8e7eb --- /dev/null +++ b/board/avionic-design/tec-ng/MAINTAINERS @@ -0,0 +1,6 @@ +TEC-NG BOARD +M: Alban Bedel +S: Maintained +F: board/avionic-design/tec-ng/ +F: include/configs/tec-ng.h +F: configs/tec-ng_defconfig diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile new file mode 100644 index 0000000000..a556b92e8e --- /dev/null +++ b/board/avionic-design/tec-ng/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2013 +# Avionic Design GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ../common/tamonten-ng.o + +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig new file mode 100644 index 0000000000..bc9751b108 --- /dev/null +++ b/board/avionic-design/tec/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TEC + +config SYS_BOARD + default "tec" + +config SYS_VENDOR + default "avionic-design" + +config SYS_CONFIG_NAME + default "tec" + +endif diff --git a/board/avionic-design/tec/MAINTAINERS b/board/avionic-design/tec/MAINTAINERS new file mode 100644 index 0000000000..10f1aac7a6 --- /dev/null +++ b/board/avionic-design/tec/MAINTAINERS @@ -0,0 +1,6 @@ +TEC BOARD +M: Alban Bedel +S: Maintained +F: board/avionic-design/tec/ +F: include/configs/tec.h +F: configs/tec_defconfig diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index 3077319ae2..bcf7ccfe2a 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -7,28 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := ../common/tamonten.o -$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := ../common/tamonten.o - -include ../../nvidia/common/common.mk - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avnet/fx12mm/.gitignore b/board/avnet/fx12mm/.gitignore deleted file mode 100644 index b644f59941..0000000000 --- a/board/avnet/fx12mm/.gitignore +++ /dev/null @@ -1 +0,0 @@ -config.tmp diff --git a/board/avnet/fx12mm/Kconfig b/board/avnet/fx12mm/Kconfig new file mode 100644 index 0000000000..0b67ebde93 --- /dev/null +++ b/board/avnet/fx12mm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_FX12MM + +config SYS_BOARD + default "fx12mm" + +config SYS_VENDOR + default "avnet" + +config SYS_CONFIG_NAME + default "fx12mm" + +endif diff --git a/board/avnet/fx12mm/MAINTAINERS b/board/avnet/fx12mm/MAINTAINERS new file mode 100644 index 0000000000..c92e258df9 --- /dev/null +++ b/board/avnet/fx12mm/MAINTAINERS @@ -0,0 +1,7 @@ +FX12MM BOARD +M: Georg Schardt +S: Maintained +F: board/avnet/fx12mm/ +F: include/configs/fx12mm.h +F: configs/fx12mm_defconfig +F: configs/fx12mm_flash_defconfig diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile index 2dd48b67f1..618b42f891 100644 --- a/board/avnet/fx12mm/Makefile +++ b/board/avnet/fx12mm/Makefile @@ -6,6 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -COBJS += $(BOARD).o +obj-y += fx12mm.o -include $(SRCTREE)/board/xilinx/ppc405-generic/Makefile +include $(srctree)/board/xilinx/ppc405-generic/Makefile diff --git a/board/avnet/v5fx30teval/.gitignore b/board/avnet/v5fx30teval/.gitignore deleted file mode 100644 index f6418a0c50..0000000000 --- a/board/avnet/v5fx30teval/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/config.tmp diff --git a/board/avnet/v5fx30teval/Kconfig b/board/avnet/v5fx30teval/Kconfig new file mode 100644 index 0000000000..079387b707 --- /dev/null +++ b/board/avnet/v5fx30teval/Kconfig @@ -0,0 +1,12 @@ +if TARGET_V5FX30TEVAL + +config SYS_BOARD + default "v5fx30teval" + +config SYS_VENDOR + default "avnet" + +config SYS_CONFIG_NAME + default "v5fx30teval" + +endif diff --git a/board/avnet/v5fx30teval/MAINTAINERS b/board/avnet/v5fx30teval/MAINTAINERS new file mode 100644 index 0000000000..91dde7a5c8 --- /dev/null +++ b/board/avnet/v5fx30teval/MAINTAINERS @@ -0,0 +1,7 @@ +V5FX30TEVAL BOARD +M: Ricardo Ribalda +S: Maintained +F: board/avnet/v5fx30teval/ +F: include/configs/v5fx30teval.h +F: configs/v5fx30teval_defconfig +F: configs/v5fx30teval_flash_defconfig diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile index 51b777c234..8c41af02d4 100644 --- a/board/avnet/v5fx30teval/Makefile +++ b/board/avnet/v5fx30teval/Makefile @@ -6,6 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -COBJS += $(BOARD).o +obj-y += v5fx30teval.o -include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile +include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig new file mode 100644 index 0000000000..7f8a6a1abc --- /dev/null +++ b/board/bachmann/ot1200/Kconfig @@ -0,0 +1,15 @@ +if TARGET_OT1200 + +config SYS_BOARD + default "ot1200" + +config SYS_VENDOR + default "bachmann" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "ot1200" + +endif diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS new file mode 100644 index 0000000000..ad75c24ee4 --- /dev/null +++ b/board/bachmann/ot1200/MAINTAINERS @@ -0,0 +1,6 @@ +BACHMANN ELECTRONIC OT1200 BOARD +M: Christian Gmeiner +S: Maintained +F: board/bachmann/ot1200 +F: include/configs/ot1200.h +F: configs/ot1200*_defconfig diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile new file mode 100644 index 0000000000..1bd42e8321 --- /dev/null +++ b/board/bachmann/ot1200/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ot1200.o diff --git a/board/bachmann/ot1200/README b/board/bachmann/ot1200/README new file mode 100644 index 0000000000..c03d44e458 --- /dev/null +++ b/board/bachmann/ot1200/README @@ -0,0 +1,20 @@ +U-Boot for the Bachmann electronic GmbH OT1200 devices + +There are two different versions of the base board, which differ +in the way ethernet is done. The variant detection is done during +runtime based on the address of the found phy. + +- "mr" variant +FEC is connected directly to an ethernet switch (KSZ8895). The ethernet +port is always up and auto-negotiation is not possible. + +- normal variant +FEC is connected to a normal phy and auto-negotiation is possible. + + +The variant name is part of the dtb file name loaded by u-boot. This +make is possible to boot the linux kernel and make use variant specific +devicetree (fixed-phy link). + +In order to support different display resoltuions/sizes the OT1200 devices +are making use of EDID data stored in an i2c EEPROM. diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg similarity index 100% rename from board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg rename to board/bachmann/ot1200/mx6q_4x_mt41j128.cfg diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c new file mode 100644 index 0000000000..93f3d65176 --- /dev/null +++ b/board/bachmann/ot1200/ot1200.c @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2014, Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ + PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \ + PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ + PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +static void setup_iomux_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1; +} + +static iomux_v3_cfg_t const feature_pads[] = { + /* SD card detect */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN), + + /* eMMC soldered? */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP), +}; + +static void setup_iomux_features(void) +{ + imx_iomux_v3_setup_multiple_pads(feature_pads, + ARRAY_SIZE(feature_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_spi(); + setup_iomux_features(); + + return 0; +} + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(4, 5)); + ret = gpio_get_value(IMX_GPIO_NR(4, 5)); + } else { + gpio_direction_input(IMX_GPIO_NR(1, 5)); + ret = !gpio_get_value(IMX_GPIO_NR(1, 5)); + } + + return ret; +} + +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + int ret; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].max_bus_width = 4; + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; +} + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C3 - IO expander */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +static iomux_v3_cfg_t const pwm_pad[] = { + MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), +}; + +static void leds_on(void) +{ + /* turn on all possible leds connected via GPIO expander */ + i2c_set_bus_num(2); + pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT); + pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0); +} + +static void backlight_lcd_off(void) +{ + unsigned gpio = IMX_GPIO_NR(2, 0); + gpio_direction_output(gpio, 0); + + gpio = IMX_GPIO_NR(2, 3); + gpio_direction_output(gpio, 0); +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + + /* scan phy 0 and 5 */ + phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return 0; + } + + /* depending on the phy address we can detect our board version */ + if (phydev->addr == 0) + setenv("boardver", ""); + else + setenv("boardver", "mr"); + + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + backlight_lcd_off(); + + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + leds_on(); + + /* enable ecspi3 clocks */ + enable_cspi_clock(1, 2); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: "CONFIG_SYS_BOARD"\n"); + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} diff --git a/board/balloon3/Kconfig b/board/balloon3/Kconfig new file mode 100644 index 0000000000..53b7a9a5c7 --- /dev/null +++ b/board/balloon3/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BALLOON3 + +config SYS_BOARD + default "balloon3" + +config SYS_CONFIG_NAME + default "balloon3" + +endif diff --git a/board/balloon3/MAINTAINERS b/board/balloon3/MAINTAINERS new file mode 100644 index 0000000000..df9a5bbcfa --- /dev/null +++ b/board/balloon3/MAINTAINERS @@ -0,0 +1,6 @@ +BALLOON3 BOARD +M: Marek Vasut +S: Maintained +F: board/balloon3/ +F: include/configs/balloon3.h +F: configs/balloon3_defconfig diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile index 34e2542213..d7fb5e036e 100644 --- a/board/balloon3/Makefile +++ b/board/balloon3/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := balloon3.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := balloon3.o diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index ecbac16d59..aa108ca153 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -13,6 +13,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -59,7 +60,7 @@ void dram_init_banksize(void) } #ifdef CONFIG_CMD_USB -int usb_board_init(void) +int board_usb_init(int index, enum usb_init_type init) { writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), @@ -90,9 +91,9 @@ int usb_board_init(void) return 0; } -void usb_board_init_fail(void) +int board_usb_cleanup(int index, enum usb_init_type init) { - return; + return 0; } void usb_board_stop(void) @@ -190,7 +191,7 @@ int fpga_cs_fn(int assert_clk, int flush, int cookie) return assert_clk; } -Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = { +xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_init_fn, @@ -206,7 +207,7 @@ Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = { fpga_post_config_fn, }; -Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel, +xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel, (void *)&balloon3_fpga_fns, 0); /* Initialize the FPGA */ diff --git a/board/barco/titanium/Kconfig b/board/barco/titanium/Kconfig new file mode 100644 index 0000000000..b6f7c855b5 --- /dev/null +++ b/board/barco/titanium/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TITANIUM + +config SYS_BOARD + default "titanium" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "titanium" + +endif diff --git a/board/barco/titanium/MAINTAINERS b/board/barco/titanium/MAINTAINERS new file mode 100644 index 0000000000..7e9913ffa6 --- /dev/null +++ b/board/barco/titanium/MAINTAINERS @@ -0,0 +1,6 @@ +TITANIUM BOARD +M: Stefan Roese +S: Maintained +F: board/barco/titanium/ +F: include/configs/titanium.h +F: configs/titanium_defconfig diff --git a/board/barco/titanium/Makefile b/board/barco/titanium/Makefile new file mode 100644 index 0000000000..0ad4cb9b15 --- /dev/null +++ b/board/barco/titanium/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := titanium.o diff --git a/board/freescale/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg similarity index 100% rename from board/freescale/titanium/imximage.cfg rename to board/barco/titanium/imximage.cfg diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c new file mode 100644 index 0000000000..84a7b849ad --- /dev/null +++ b/board/barco/titanium/titanium.c @@ -0,0 +1,317 @@ +/* + * Copyright (C) 2013 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + return 0; +} + +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[1] = { + { USDHC3_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(7, 0)); + return !gpio_get_value(IMX_GPIO_NR(7, 0)); + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + /* + * Only one USDHC controller on titianium + */ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + setup_gpmi_nand(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: Titanium\n"); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* NAND */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + /* 4 bit bus width */ + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, + { NULL, 0 }, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} diff --git a/board/bc3450/Kconfig b/board/bc3450/Kconfig new file mode 100644 index 0000000000..a0fc19f63c --- /dev/null +++ b/board/bc3450/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BC3450 + +config SYS_BOARD + default "bc3450" + +config SYS_CONFIG_NAME + default "BC3450" + +endif diff --git a/board/bc3450/MAINTAINERS b/board/bc3450/MAINTAINERS new file mode 100644 index 0000000000..81a7076093 --- /dev/null +++ b/board/bc3450/MAINTAINERS @@ -0,0 +1,6 @@ +BC3450 BOARD +#M: - +S: Maintained +F: board/bc3450/ +F: include/configs/BC3450.h +F: configs/BC3450_defconfig diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile index 07970c65e3..b8d22bafed 100644 --- a/board/bc3450/Makefile +++ b/board/bc3450/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o cmd_bc3450.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bc3450.o cmd_bc3450.o diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c index bfb11bf78e..a5c6d750cb 100644 --- a/board/bc3450/bc3450.c +++ b/board/bc3450/bc3450.c @@ -11,7 +11,7 @@ * (C) Copyright 2006 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/bct-brettl2/Kconfig b/board/bct-brettl2/Kconfig new file mode 100644 index 0000000000..9c5407e7b2 --- /dev/null +++ b/board/bct-brettl2/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BCT_BRETTL2 + +config SYS_BOARD + default "bct-brettl2" + +config SYS_CONFIG_NAME + default "bct-brettl2" + +endif diff --git a/board/bct-brettl2/MAINTAINERS b/board/bct-brettl2/MAINTAINERS new file mode 100644 index 0000000000..32245d4bcd --- /dev/null +++ b/board/bct-brettl2/MAINTAINERS @@ -0,0 +1,6 @@ +BCT-BRETTL2 BOARD +M: Peter Meerwald +S: Maintained +F: board/bct-brettl2/ +F: include/configs/bct-brettl2.h +F: configs/bct-brettl2_defconfig diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile index 6f9f701c06..12154b625e 100644 --- a/board/bct-brettl2/Makefile +++ b/board/bct-brettl2/Makefile @@ -9,21 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o gpio_cfi_flash.o cled.o -COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := bct-brettl2.o gpio_cfi_flash.o cled.o +obj-$(CONFIG_BFIN_MAC) += smsc9303.o diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c index de5b9ff0e7..6be9b18015 100644 --- a/board/bct-brettl2/bct-brettl2.c +++ b/board/bct-brettl2/bct-brettl2.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -33,7 +32,7 @@ int checkboard(void) static void board_init_enetaddr(uchar *mac_addr) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr); } diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bct-brettl2/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf506f-ezkit/Kconfig b/board/bf506f-ezkit/Kconfig new file mode 100644 index 0000000000..e6fc12ccb2 --- /dev/null +++ b/board/bf506f-ezkit/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF506F_EZKIT + +config SYS_BOARD + default "bf506f-ezkit" + +config SYS_CONFIG_NAME + default "bf506f-ezkit" + +endif diff --git a/board/bf506f-ezkit/MAINTAINERS b/board/bf506f-ezkit/MAINTAINERS new file mode 100644 index 0000000000..aaf1b7eaaf --- /dev/null +++ b/board/bf506f-ezkit/MAINTAINERS @@ -0,0 +1,6 @@ +BF506F-EZKIT BOARD +M: Sonic Zhang +S: Maintained +F: board/bf506f-ezkit/ +F: include/configs/bf506f-ezkit.h +F: configs/bf506f-ezkit_defconfig diff --git a/board/bf506f-ezkit/Makefile b/board/bf506f-ezkit/Makefile index b7275f49fe..0f134f9ac3 100644 --- a/board/bf506f-ezkit/Makefile +++ b/board/bf506f-ezkit/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf506f-ezkit.o diff --git a/board/bf518f-ezbrd/Kconfig b/board/bf518f-ezbrd/Kconfig new file mode 100644 index 0000000000..a0e80a8bde --- /dev/null +++ b/board/bf518f-ezbrd/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF518F_EZBRD + +config SYS_BOARD + default "bf518f-ezbrd" + +config SYS_CONFIG_NAME + default "bf518f-ezbrd" + +endif diff --git a/board/bf518f-ezbrd/MAINTAINERS b/board/bf518f-ezbrd/MAINTAINERS new file mode 100644 index 0000000000..6727ae4e8a --- /dev/null +++ b/board/bf518f-ezbrd/MAINTAINERS @@ -0,0 +1,6 @@ +BF518F-EZBRD BOARD +M: Sonic Zhang +S: Maintained +F: board/bf518f-ezbrd/ +F: include/configs/bf518f-ezbrd.h +F: configs/bf518f-ezbrd_defconfig diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile index b7275f49fe..3a6abaa63b 100644 --- a/board/bf518f-ezbrd/Makefile +++ b/board/bf518f-ezbrd/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf518f-ezbrd.o diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index 09a2353e7d..3a94a572eb 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -48,7 +47,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bf518f-ezbrd/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf525-ucr2/Kconfig b/board/bf525-ucr2/Kconfig new file mode 100644 index 0000000000..cd52daaacd --- /dev/null +++ b/board/bf525-ucr2/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF525_UCR2 + +config SYS_BOARD + default "bf525-ucr2" + +config SYS_CONFIG_NAME + default "bf525-ucr2" + +endif diff --git a/board/bf525-ucr2/MAINTAINERS b/board/bf525-ucr2/MAINTAINERS new file mode 100644 index 0000000000..f2e9575a7a --- /dev/null +++ b/board/bf525-ucr2/MAINTAINERS @@ -0,0 +1,7 @@ +BF525-UCR2 BOARD +M: Haitao Zhang +M: Chong Huang +S: Maintained +F: board/bf525-ucr2/ +F: include/configs/bf525-ucr2.h +F: configs/bf525-ucr2_defconfig diff --git a/board/bf525-ucr2/Makefile b/board/bf525-ucr2/Makefile index b7275f49fe..8de71a1886 100644 --- a/board/bf525-ucr2/Makefile +++ b/board/bf525-ucr2/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf525-ucr2.o diff --git a/board/bf526-ezbrd/Kconfig b/board/bf526-ezbrd/Kconfig new file mode 100644 index 0000000000..e138ea5545 --- /dev/null +++ b/board/bf526-ezbrd/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF526_EZBRD + +config SYS_BOARD + default "bf526-ezbrd" + +config SYS_CONFIG_NAME + default "bf526-ezbrd" + +endif diff --git a/board/bf526-ezbrd/MAINTAINERS b/board/bf526-ezbrd/MAINTAINERS new file mode 100644 index 0000000000..f7c2d18913 --- /dev/null +++ b/board/bf526-ezbrd/MAINTAINERS @@ -0,0 +1,6 @@ +BF526-EZBRD BOARD +M: Sonic Zhang +S: Maintained +F: board/bf526-ezbrd/ +F: include/configs/bf526-ezbrd.h +F: configs/bf526-ezbrd_defconfig diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile index b7275f49fe..34ac56323a 100644 --- a/board/bf526-ezbrd/Makefile +++ b/board/bf526-ezbrd/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf526-ezbrd.o diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c index 4695b1161a..368d6be25f 100644 --- a/board/bf526-ezbrd/bf526-ezbrd.c +++ b/board/bf526-ezbrd/bf526-ezbrd.c @@ -12,7 +12,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -45,7 +44,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bf526-ezbrd/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf527-ad7160-eval/Kconfig b/board/bf527-ad7160-eval/Kconfig new file mode 100644 index 0000000000..fe56241212 --- /dev/null +++ b/board/bf527-ad7160-eval/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF527_AD7160_EVAL + +config SYS_BOARD + default "bf527-ad7160-eval" + +config SYS_CONFIG_NAME + default "bf527-ad7160-eval" + +endif diff --git a/board/bf527-ad7160-eval/MAINTAINERS b/board/bf527-ad7160-eval/MAINTAINERS new file mode 100644 index 0000000000..e93de1a234 --- /dev/null +++ b/board/bf527-ad7160-eval/MAINTAINERS @@ -0,0 +1,6 @@ +BF527-AD7160-EVAL BOARD +M: Sonic Zhang +S: Maintained +F: board/bf527-ad7160-eval/ +F: include/configs/bf527-ad7160-eval.h +F: configs/bf527-ad7160-eval_defconfig diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile index b7275f49fe..9d8ecf118d 100644 --- a/board/bf527-ad7160-eval/Makefile +++ b/board/bf527-ad7160-eval/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf527-ad7160-eval.o diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bf527-ad7160-eval/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf527-ezkit/Kconfig b/board/bf527-ezkit/Kconfig new file mode 100644 index 0000000000..df49d7a60d --- /dev/null +++ b/board/bf527-ezkit/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF527_EZKIT + +config SYS_BOARD + default "bf527-ezkit" + +config SYS_CONFIG_NAME + default "bf527-ezkit" + +endif diff --git a/board/bf527-ezkit/MAINTAINERS b/board/bf527-ezkit/MAINTAINERS new file mode 100644 index 0000000000..7a953960d4 --- /dev/null +++ b/board/bf527-ezkit/MAINTAINERS @@ -0,0 +1,7 @@ +BF527-EZKIT BOARD +M: Sonic Zhang +S: Maintained +F: board/bf527-ezkit/ +F: include/configs/bf527-ezkit.h +F: configs/bf527-ezkit_defconfig +F: configs/bf527-ezkit-v2_defconfig diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile index 1a6ca64c72..cedd821b24 100644 --- a/board/bf527-ezkit/Makefile +++ b/board/bf527-ezkit/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_VIDEO) += video.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf527-ezkit.o +obj-$(CONFIG_VIDEO) += video.o diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index 211cf24ac3..88e18690e0 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -13,7 +13,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -47,7 +46,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/bf527-ezkit/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 5d8a0910de..c2bf145013 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -391,14 +391,6 @@ void video_stop(void) #endif } -void video_putc(const char c) -{ -} - -void video_puts(const char *s) -{ -} - int drv_video_init(void) { int error, devices = 1; @@ -448,8 +440,6 @@ int drv_video_init(void) strcpy(videodev.name, "video"); videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ error = stdio_register(&videodev); diff --git a/board/bf527-sdp/Kconfig b/board/bf527-sdp/Kconfig new file mode 100644 index 0000000000..928bd776b9 --- /dev/null +++ b/board/bf527-sdp/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF527_SDP + +config SYS_BOARD + default "bf527-sdp" + +config SYS_CONFIG_NAME + default "bf527-sdp" + +endif diff --git a/board/bf527-sdp/MAINTAINERS b/board/bf527-sdp/MAINTAINERS new file mode 100644 index 0000000000..32ccfc5e90 --- /dev/null +++ b/board/bf527-sdp/MAINTAINERS @@ -0,0 +1,6 @@ +BF527-SDP BOARD +M: Sonic Zhang +S: Maintained +F: board/bf527-sdp/ +F: include/configs/bf527-sdp.h +F: configs/bf527-sdp_defconfig diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile index b7275f49fe..1ddb026cae 100644 --- a/board/bf527-sdp/Makefile +++ b/board/bf527-sdp/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf527-sdp.o diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk index 5f327a990e..1d46cfcd48 100644 --- a/board/bf527-sdp/config.mk +++ b/board/bf527-sdp/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6 diff --git a/board/bf533-ezkit/Kconfig b/board/bf533-ezkit/Kconfig new file mode 100644 index 0000000000..555ab298f2 --- /dev/null +++ b/board/bf533-ezkit/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF533_EZKIT + +config SYS_BOARD + default "bf533-ezkit" + +config SYS_CONFIG_NAME + default "bf533-ezkit" + +endif diff --git a/board/bf533-ezkit/MAINTAINERS b/board/bf533-ezkit/MAINTAINERS new file mode 100644 index 0000000000..bfa7c3cb29 --- /dev/null +++ b/board/bf533-ezkit/MAINTAINERS @@ -0,0 +1,6 @@ +BF533-EZKIT BOARD +M: Sonic Zhang +S: Maintained +F: board/bf533-ezkit/ +F: include/configs/bf533-ezkit.h +F: configs/bf533-ezkit_defconfig diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index 63a48b27c7..6838cf0451 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o flash.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf533-ezkit.o flash.o diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index 973d357559..7f9138b09b 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf533-stamp/Kconfig b/board/bf533-stamp/Kconfig new file mode 100644 index 0000000000..0cffde3b47 --- /dev/null +++ b/board/bf533-stamp/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF533_STAMP + +config SYS_BOARD + default "bf533-stamp" + +config SYS_CONFIG_NAME + default "bf533-stamp" + +endif diff --git a/board/bf533-stamp/MAINTAINERS b/board/bf533-stamp/MAINTAINERS new file mode 100644 index 0000000000..c7aeefaee0 --- /dev/null +++ b/board/bf533-stamp/MAINTAINERS @@ -0,0 +1,6 @@ +BF533-STAMP BOARD +M: Sonic Zhang +S: Maintained +F: board/bf533-stamp/ +F: include/configs/bf533-stamp.h +F: configs/bf533-stamp_defconfig diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index d2bc49ab56..244f9e0497 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -9,26 +9,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_STAMP_CF) += ide-cf.o -COBJS-$(CONFIG_VIDEO) += video.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf533-stamp.o +obj-$(CONFIG_STAMP_CF) += ide-cf.o +obj-$(CONFIG_VIDEO) += video.o diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index 973d357559..7f9138b09b 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf537-minotaur/Kconfig b/board/bf537-minotaur/Kconfig new file mode 100644 index 0000000000..204f609e09 --- /dev/null +++ b/board/bf537-minotaur/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF537_MINOTAUR + +config SYS_BOARD + default "bf537-minotaur" + +config SYS_CONFIG_NAME + default "bf537-minotaur" + +endif diff --git a/board/bf537-minotaur/MAINTAINERS b/board/bf537-minotaur/MAINTAINERS new file mode 100644 index 0000000000..04643b1afd --- /dev/null +++ b/board/bf537-minotaur/MAINTAINERS @@ -0,0 +1,6 @@ +BF537-MINOTAUR BOARD +M: Martin Strubel +S: Maintained +F: board/bf537-minotaur/ +F: include/configs/bf537-minotaur.h +F: configs/bf537-minotaur_defconfig diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile index b7275f49fe..66d2f05f44 100644 --- a/board/bf537-minotaur/Makefile +++ b/board/bf537-minotaur/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf537-minotaur.o diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c index 920429c12e..ca61ef97b8 100644 --- a/board/bf537-minotaur/bf537-minotaur.c +++ b/board/bf537-minotaur/bf537-minotaur.c @@ -12,7 +12,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -27,7 +26,7 @@ int checkboard(void) static void board_init_enetaddr(uchar *mac_addr) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr); } diff --git a/board/bf537-pnav/Kconfig b/board/bf537-pnav/Kconfig new file mode 100644 index 0000000000..acb1f89233 --- /dev/null +++ b/board/bf537-pnav/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF537_PNAV + +config SYS_BOARD + default "bf537-pnav" + +config SYS_CONFIG_NAME + default "bf537-pnav" + +endif diff --git a/board/bf537-pnav/MAINTAINERS b/board/bf537-pnav/MAINTAINERS new file mode 100644 index 0000000000..b8b22a3d46 --- /dev/null +++ b/board/bf537-pnav/MAINTAINERS @@ -0,0 +1,6 @@ +BF537-PNAV BOARD +M: Sonic Zhang +S: Maintained +F: board/bf537-pnav/ +F: include/configs/bf537-pnav.h +F: configs/bf537-pnav_defconfig diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile index b7275f49fe..ffcdf1f0b0 100644 --- a/board/bf537-pnav/Makefile +++ b/board/bf537-pnav/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf537-pnav.o diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c index c5125288cb..df0011026a 100644 --- a/board/bf537-pnav/bf537-pnav.c +++ b/board/bf537-pnav/bf537-pnav.c @@ -12,7 +12,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -27,7 +26,7 @@ int checkboard(void) static void board_init_enetaddr(uchar *mac_addr) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr); } diff --git a/board/bf537-srv1/Kconfig b/board/bf537-srv1/Kconfig new file mode 100644 index 0000000000..2ddcd69482 --- /dev/null +++ b/board/bf537-srv1/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF537_SRV1 + +config SYS_BOARD + default "bf537-srv1" + +config SYS_CONFIG_NAME + default "bf537-srv1" + +endif diff --git a/board/bf537-srv1/MAINTAINERS b/board/bf537-srv1/MAINTAINERS new file mode 100644 index 0000000000..c8f1458656 --- /dev/null +++ b/board/bf537-srv1/MAINTAINERS @@ -0,0 +1,6 @@ +BF537-SRV1 BOARD +M: Martin Strubel +S: Maintained +F: board/bf537-srv1/ +F: include/configs/bf537-srv1.h +F: configs/bf537-srv1_defconfig diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile index b7275f49fe..cd0da272a6 100644 --- a/board/bf537-srv1/Makefile +++ b/board/bf537-srv1/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf537-srv1.o diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c index 04d38910b3..725296a416 100644 --- a/board/bf537-srv1/bf537-srv1.c +++ b/board/bf537-srv1/bf537-srv1.c @@ -12,7 +12,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -27,7 +26,7 @@ int checkboard(void) static void board_init_enetaddr(uchar *mac_addr) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr); } diff --git a/board/bf537-stamp/Kconfig b/board/bf537-stamp/Kconfig new file mode 100644 index 0000000000..4f86128e9c --- /dev/null +++ b/board/bf537-stamp/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF537_STAMP + +config SYS_BOARD + default "bf537-stamp" + +config SYS_CONFIG_NAME + default "bf537-stamp" + +endif diff --git a/board/bf537-stamp/MAINTAINERS b/board/bf537-stamp/MAINTAINERS new file mode 100644 index 0000000000..7d9c1334bf --- /dev/null +++ b/board/bf537-stamp/MAINTAINERS @@ -0,0 +1,6 @@ +BF537-STAMP BOARD +M: Sonic Zhang +S: Maintained +F: board/bf537-stamp/ +F: include/configs/bf537-stamp.h +F: configs/bf537-stamp_defconfig diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index 3e267edc0b..234119a52a 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -9,26 +9,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_BFIN_IDE) += ide-cf.o -COBJS-$(CONFIG_HAS_POST) += post-memory.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf537-stamp.o +obj-$(CONFIG_BFIN_IDE) += ide-cf.o +obj-$(CONFIG_HAS_POST) += post-memory.o diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 5fdf8379c0..32045a9e47 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -48,7 +47,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index ae2ea0b747..ab0fbecab9 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 diff --git a/board/bf538f-ezkit/Kconfig b/board/bf538f-ezkit/Kconfig new file mode 100644 index 0000000000..e40fcdb2a2 --- /dev/null +++ b/board/bf538f-ezkit/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF538F_EZKIT + +config SYS_BOARD + default "bf538f-ezkit" + +config SYS_CONFIG_NAME + default "bf538f-ezkit" + +endif diff --git a/board/bf538f-ezkit/MAINTAINERS b/board/bf538f-ezkit/MAINTAINERS new file mode 100644 index 0000000000..7964735e6d --- /dev/null +++ b/board/bf538f-ezkit/MAINTAINERS @@ -0,0 +1,6 @@ +BF538F-EZKIT BOARD +M: Sonic Zhang +S: Maintained +F: board/bf538f-ezkit/ +F: include/configs/bf538f-ezkit.h +F: configs/bf538f-ezkit_defconfig diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile index b7275f49fe..7c8cda05e9 100644 --- a/board/bf538f-ezkit/Makefile +++ b/board/bf538f-ezkit/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf538f-ezkit.o diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk index 973d357559..7f9138b09b 100644 --- a/board/bf538f-ezkit/config.mk +++ b/board/bf538f-ezkit/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf548-ezkit/Kconfig b/board/bf548-ezkit/Kconfig new file mode 100644 index 0000000000..550227fa30 --- /dev/null +++ b/board/bf548-ezkit/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF548_EZKIT + +config SYS_BOARD + default "bf548-ezkit" + +config SYS_CONFIG_NAME + default "bf548-ezkit" + +endif diff --git a/board/bf548-ezkit/MAINTAINERS b/board/bf548-ezkit/MAINTAINERS new file mode 100644 index 0000000000..e2683bb474 --- /dev/null +++ b/board/bf548-ezkit/MAINTAINERS @@ -0,0 +1,6 @@ +BF548-EZKIT BOARD +M: Sonic Zhang +S: Maintained +F: board/bf548-ezkit/ +F: include/configs/bf548-ezkit.h +F: configs/bf548-ezkit_defconfig diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile index 1a6ca64c72..6f4200bd46 100644 --- a/board/bf548-ezkit/Makefile +++ b/board/bf548-ezkit/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_VIDEO) += video.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf548-ezkit.o +obj-$(CONFIG_VIDEO) += video.o diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk index ad3a7293df..7bb8e9c9ee 100644 --- a/board/bf548-ezkit/config.mk +++ b/board/bf548-ezkit/config.mk @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1 diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index 6737ac1628..47e68c6a97 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -281,14 +281,6 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) } -void video_putc(const char c) -{ -} - -void video_puts(const char *s) -{ -} - int drv_video_init(void) { int error, devices = 1; @@ -338,8 +330,6 @@ int drv_video_init(void) strcpy(videodev.name, "video"); videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ error = stdio_register(&videodev); diff --git a/board/bf561-acvilon/Kconfig b/board/bf561-acvilon/Kconfig new file mode 100644 index 0000000000..ba1580d87b --- /dev/null +++ b/board/bf561-acvilon/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF561_ACVILON + +config SYS_BOARD + default "bf561-acvilon" + +config SYS_CONFIG_NAME + default "bf561-acvilon" + +endif diff --git a/board/bf561-acvilon/MAINTAINERS b/board/bf561-acvilon/MAINTAINERS new file mode 100644 index 0000000000..056ee0bdb7 --- /dev/null +++ b/board/bf561-acvilon/MAINTAINERS @@ -0,0 +1,6 @@ +BF561-ACVILON BOARD +M: Valentin Yakovenkov +S: Maintained +F: board/bf561-acvilon/ +F: include/configs/bf561-acvilon.h +F: configs/bf561-acvilon_defconfig diff --git a/board/bf561-acvilon/Makefile b/board/bf561-acvilon/Makefile index 988cdd88c1..48bec2884d 100644 --- a/board/bf561-acvilon/Makefile +++ b/board/bf561-acvilon/Makefile @@ -11,24 +11,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf561-acvilon.o diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk index c33aef9d28..854d7dbb86 100644 --- a/board/bf561-acvilon/config.mk +++ b/board/bf561-acvilon/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/bf561-ezkit/Kconfig b/board/bf561-ezkit/Kconfig new file mode 100644 index 0000000000..495a5c51eb --- /dev/null +++ b/board/bf561-ezkit/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF561_EZKIT + +config SYS_BOARD + default "bf561-ezkit" + +config SYS_CONFIG_NAME + default "bf561-ezkit" + +endif diff --git a/board/bf561-ezkit/MAINTAINERS b/board/bf561-ezkit/MAINTAINERS new file mode 100644 index 0000000000..5ced3bb7d6 --- /dev/null +++ b/board/bf561-ezkit/MAINTAINERS @@ -0,0 +1,6 @@ +BF561-EZKIT BOARD +M: Sonic Zhang +S: Maintained +F: board/bf561-ezkit/ +F: include/configs/bf561-ezkit.h +F: configs/bf561-ezkit_defconfig diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile index 099bcaf999..23c7101c20 100644 --- a/board/bf561-ezkit/Makefile +++ b/board/bf561-ezkit/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf561-ezkit.o diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index c33aef9d28..854d7dbb86 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/bf609-ezkit/Kconfig b/board/bf609-ezkit/Kconfig new file mode 100644 index 0000000000..7992e1ec86 --- /dev/null +++ b/board/bf609-ezkit/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BF609_EZKIT + +config SYS_BOARD + default "bf609-ezkit" + +config SYS_CONFIG_NAME + default "bf609-ezkit" + +endif diff --git a/board/bf609-ezkit/MAINTAINERS b/board/bf609-ezkit/MAINTAINERS new file mode 100644 index 0000000000..acfc6c7a86 --- /dev/null +++ b/board/bf609-ezkit/MAINTAINERS @@ -0,0 +1,6 @@ +BF609-EZKIT BOARD +M: Sonic Zhang +S: Maintained +F: board/bf609-ezkit/ +F: include/configs/bf609-ezkit.h +F: configs/bf609-ezkit_defconfig diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile index cd2fdc746c..3bfd0887bc 100644 --- a/board/bf609-ezkit/Makefile +++ b/board/bf609-ezkit/Makefile @@ -9,31 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_BFIN_SOFT_SWITCH) += soft_switch.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := bf609-ezkit.o +obj-$(CONFIG_BFIN_SOFT_SWITCH) += soft_switch.o diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c index 0388226db4..43a43306bb 100644 --- a/board/bf609-ezkit/bf609-ezkit.c +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "soft_switch.h" @@ -40,12 +41,12 @@ int board_eth_init(bd_t *bis) if (CONFIG_DW_PORTS & 1) { static const unsigned short pins[] = P_RMII0; if (!peripheral_request_list(pins, "emac0")) - ret += designware_initialize(0, EMAC0_MACCFG, 1, 0); + ret += designware_initialize(EMAC0_MACCFG, 0); } if (CONFIG_DW_PORTS & 2) { static const unsigned short pins[] = P_RMII1; if (!peripheral_request_list(pins, "emac1")) - ret += designware_initialize(1, EMAC1_MACCFG, 1, 0); + ret += designware_initialize(EMAC1_MACCFG, 0); } return ret; diff --git a/board/blackstamp/Kconfig b/board/blackstamp/Kconfig new file mode 100644 index 0000000000..7ce086a78f --- /dev/null +++ b/board/blackstamp/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BLACKSTAMP + +config SYS_BOARD + default "blackstamp" + +config SYS_CONFIG_NAME + default "blackstamp" + +endif diff --git a/board/blackstamp/MAINTAINERS b/board/blackstamp/MAINTAINERS new file mode 100644 index 0000000000..a0d72c6e20 --- /dev/null +++ b/board/blackstamp/MAINTAINERS @@ -0,0 +1,8 @@ +BLACKSTAMP BOARD +M: Wojtek Skulski +M: Wojtek Skulski +M: Benjamin Matthews +S: Maintained +F: board/blackstamp/ +F: include/configs/blackstamp.h +F: configs/blackstamp_defconfig diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile index b7275f49fe..38e5da7469 100644 --- a/board/blackstamp/Makefile +++ b/board/blackstamp/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := blackstamp.o diff --git a/board/blackvme/Kconfig b/board/blackvme/Kconfig new file mode 100644 index 0000000000..5e73f84eff --- /dev/null +++ b/board/blackvme/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BLACKVME + +config SYS_BOARD + default "blackvme" + +config SYS_CONFIG_NAME + default "blackvme" + +endif diff --git a/board/blackvme/MAINTAINERS b/board/blackvme/MAINTAINERS new file mode 100644 index 0000000000..3f8b32c884 --- /dev/null +++ b/board/blackvme/MAINTAINERS @@ -0,0 +1,8 @@ +BLACKVME BOARD +M: Wojtek Skulski +M: Wojtek Skulski +M: Benjamin Matthews +S: Maintained +F: board/blackvme/ +F: include/configs/blackvme.h +F: configs/blackvme_defconfig diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile index b7275f49fe..4ff989a140 100644 --- a/board/blackvme/Makefile +++ b/board/blackvme/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := blackvme.o diff --git a/board/bluegiga/apx4devkit/Kconfig b/board/bluegiga/apx4devkit/Kconfig new file mode 100644 index 0000000000..f327fa15cf --- /dev/null +++ b/board/bluegiga/apx4devkit/Kconfig @@ -0,0 +1,15 @@ +if TARGET_APX4DEVKIT + +config SYS_BOARD + default "apx4devkit" + +config SYS_VENDOR + default "bluegiga" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "apx4devkit" + +endif diff --git a/board/bluegiga/apx4devkit/MAINTAINERS b/board/bluegiga/apx4devkit/MAINTAINERS new file mode 100644 index 0000000000..286e9e9f06 --- /dev/null +++ b/board/bluegiga/apx4devkit/MAINTAINERS @@ -0,0 +1,6 @@ +APX4DEVKIT BOARD +M: Lauri Hintsala +S: Maintained +F: board/bluegiga/apx4devkit/ +F: include/configs/apx4devkit.h +F: configs/apx4devkit_defconfig diff --git a/board/bluegiga/apx4devkit/Makefile b/board/bluegiga/apx4devkit/Makefile index 9c05b616f8..a7fcb63aed 100644 --- a/board/bluegiga/apx4devkit/Makefile +++ b/board/bluegiga/apx4devkit/Makefile @@ -5,27 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifndef CONFIG_SPL_BUILD -COBJS := apx4devkit.o +obj-y := apx4devkit.o else -COBJS := spl_boot.o +obj-y := spl_boot.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c index 3b05baaa70..81419f9635 100644 --- a/board/bluegiga/apx4devkit/spl_boot.c +++ b/board/bluegiga/apx4devkit/spl_boot.c @@ -132,9 +132,9 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, }; -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); /* switch LED on */ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); diff --git a/board/bluewater/snapper9260/Kconfig b/board/bluewater/snapper9260/Kconfig new file mode 100644 index 0000000000..c896c46895 --- /dev/null +++ b/board/bluewater/snapper9260/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SNAPPER9260 + +config SYS_BOARD + default "snapper9260" + +config SYS_VENDOR + default "bluewater" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "snapper9260" + +endif diff --git a/board/bluewater/snapper9260/MAINTAINERS b/board/bluewater/snapper9260/MAINTAINERS new file mode 100644 index 0000000000..1f8f4d6988 --- /dev/null +++ b/board/bluewater/snapper9260/MAINTAINERS @@ -0,0 +1,7 @@ +SNAPPER9260 BOARD +M: Simon Glass +S: Maintained +F: board/bluewater/snapper9260/ +F: include/configs/snapper9260.h +F: configs/snapper9260_defconfig +F: configs/snapper9g20_defconfig diff --git a/board/bluewater/snapper9260/Makefile b/board/bluewater/snapper9260/Makefile index d050473ac3..af7f0da84b 100644 --- a/board/bluewater/snapper9260/Makefile +++ b/board/bluewater/snapper9260/Makefile @@ -8,24 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += snapper9260.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += snapper9260.o diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c index 8a6919dbb1..95633b0d2e 100644 --- a/board/bluewater/snapper9260/snapper9260.c +++ b/board/bluewater/snapper9260/snapper9260.c @@ -9,13 +9,15 @@ */ #include +#include #include +#include #include #include #include #include -#include #include +#include #include #include #include @@ -31,8 +33,6 @@ static void macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); @@ -54,18 +54,7 @@ static void macb_hw_init(void) /* Enable ethernet power */ pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0); - /* Need to reset PHY -> 500ms reset */ - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + at91_phy_reset(); /* Bring the ethernet out of reset */ pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1); @@ -109,10 +98,12 @@ static void nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy"); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce"); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } int board_init(void) @@ -154,3 +145,12 @@ int dram_init(void) void reset_phy(void) { } + +static struct atmel_serial_platdata at91sam9260_serial_plat = { + .base_addr = ATMEL_BASE_DBGU, +}; + +U_BOOT_DEVICE(at91sam9260_serial) = { + .name = "serial_atmel", + .platdata = &at91sam9260_serial_plat, +}; diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg index bb5716e88d..1096f777ec 100644 --- a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg +++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg @@ -24,18 +24,18 @@ DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251 -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027 +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029 DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt index 0d8e8e542b..1a62bbf12e 100644 --- a/board/boundary/nitrogen6x/6x_upgrade.txt +++ b/board/boundary/nitrogen6x/6x_upgrade.txt @@ -6,39 +6,39 @@ if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk if sf probe || sf probe || \ sf probe 1 27000000 || sf probe 1 27000000 ; then echo "probed SPI ROM" ; - if sf read 0x12400000 $offset $filesize ; then - if cmp.b 0x12000000 0x12400000 $filesize ; then - echo "------- U-Boot versions match" ; - else - echo "Need U-Boot upgrade" ; - echo "Program in 5 seconds" ; - for n in 5 4 3 2 1 ; do - echo $n ; - sleep 1 ; - done + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + echo "------- U-Boot versions match" ; + else + echo "Need U-Boot upgrade" ; + echo "Program in 5 seconds" ; + for n in 5 4 3 2 1 ; do + echo $n ; + sleep 1 ; + done echo "erasing" ; - sf erase 0 0x50000 ; + sf erase 0 0xC0000 ; # two steps to prevent bricking echo "programming" ; - sf write 0x12000000 $offset $filesize ; + sf write 0x12000000 $offset $filesize ; echo "verifying" ; - if sf read 0x12400000 $offset $filesize ; then - if cmp.b 0x12000000 0x12400000 $filesize ; then - while echo "---- U-Boot upgraded. reset" ; do + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + while echo "---- U-Boot upgraded. reset" ; do sleep 120 done - else - echo "Read verification error" ; - fi - else - echo "Error re-reading EEPROM" ; - fi - fi - else - echo "Error reading boot loader from EEPROM" ; - fi + else + echo "Read verification error" ; + fi + else + echo "Error re-reading EEPROM" ; + fi + fi + else + echo "Error reading boot loader from EEPROM" ; + fi else - echo "Error initializing EEPROM" ; + echo "Error initializing EEPROM" ; fi ; else echo "No U-Boot image found on SD card" ; diff --git a/board/boundary/nitrogen6x/Kconfig b/board/boundary/nitrogen6x/Kconfig new file mode 100644 index 0000000000..03b0f6f278 --- /dev/null +++ b/board/boundary/nitrogen6x/Kconfig @@ -0,0 +1,15 @@ +if TARGET_NITROGEN6X + +config SYS_BOARD + default "nitrogen6x" + +config SYS_VENDOR + default "boundary" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "nitrogen6x" + +endif diff --git a/board/boundary/nitrogen6x/MAINTAINERS b/board/boundary/nitrogen6x/MAINTAINERS new file mode 100644 index 0000000000..cb06c03691 --- /dev/null +++ b/board/boundary/nitrogen6x/MAINTAINERS @@ -0,0 +1,12 @@ +NITROGEN6X BOARD +M: Eric Nelson +S: Maintained +F: board/boundary/nitrogen6x/ +F: include/configs/nitrogen6x.h +F: configs/mx6qsabrelite_defconfig +F: configs/nitrogen6dl_defconfig +F: configs/nitrogen6dl2g_defconfig +F: configs/nitrogen6q_defconfig +F: configs/nitrogen6q2g_defconfig +F: configs/nitrogen6s_defconfig +F: configs/nitrogen6s1g_defconfig diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile index 066f60dd30..f875d68182 100644 --- a/board/boundary/nitrogen6x/Makefile +++ b/board/boundary/nitrogen6x/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := nitrogen6x.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := nitrogen6x.o diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README index 50490931e0..9d84265029 100644 --- a/board/boundary/nitrogen6x/README +++ b/board/boundary/nitrogen6x/README @@ -67,10 +67,10 @@ override auto-detection and force activation of the specified panel. To build U-Boot for one of the Nitrogen6x or SabreLite board: make nitrogen6x_config - make u-boot.imx + make Note that 'nitrogen6x' is a placeholder. The complete list of supported -board configurations is shown in tha MAINTAINERS file: +board configurations is shown in the boards.cfg file: nitrogen6q i.MX6Q/6D 1GB nitrogen6dl i.MX6DL 1GB nitrogen6s i.MX6S 512MB diff --git a/board/freescale/mx6qsabrelite/README b/board/boundary/nitrogen6x/README.mx6qsabrelite similarity index 100% rename from board/freescale/mx6qsabrelite/README rename to board/boundary/nitrogen6x/README.mx6qsabrelite diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg index 97ae0c291b..1cdccad772 100644 --- a/board/boundary/nitrogen6x/nitrogen6dl.cfg +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg index 82f837e108..516d67e4be 100644 --- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg index b6f1518ea9..b6642e6901 100644 --- a/board/boundary/nitrogen6x/nitrogen6q.cfg +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg index 8d7ff25f7f..fe6dfc1f44 100644 --- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg index 34fb9d0688..ca30cd6c46 100644 --- a/board/boundary/nitrogen6x/nitrogen6s.cfg +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg index d61453c665..b1489fb907 100644 --- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 72745f63e3..c84c220047 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -2,7 +2,7 @@ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. * Copyright (C) 2013, Boundary Devices * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -17,19 +17,24 @@ #include #include #include +#include +#include #include +#include #include #include #include #include #include -#include -#include #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; +#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ @@ -69,123 +74,140 @@ int dram_init(void) return 0; } -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1, SGTL5000 */ -struct i2c_pads_info i2c_pad_info0 = { +static struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, .gp = IMX_GPIO_NR(3, 21) }, .sda = { .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, .gp = IMX_GPIO_NR(3, 28) } }; /* I2C2 Camera, MIPI */ -struct i2c_pads_info i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, .gp = IMX_GPIO_NR(4, 12) }, .sda = { .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; /* I2C3, J15 - RGB connector */ -struct i2c_pads_info i2c_pad_info2 = { +static struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, .gp = IMX_GPIO_NR(1, 5) }, .sda = { .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, .gp = IMX_GPIO_NR(7, 11) } }; -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0, /* CD */ +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00, /* CD */ }; -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO_2_6, /* CD */ +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO2_IO06, /* CD */ }; -iomux_v3_cfg_t const enet_pads1[] = { +static iomux_v3_cfg_t const enet_pads1[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30, + MX6_PAD_RGMII_RXC__GPIO6_IO30, /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25, + MX6_PAD_RGMII_RD0__GPIO6_IO25, /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27, + MX6_PAD_RGMII_RD1__GPIO6_IO27, /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28, + MX6_PAD_RGMII_RD2__GPIO6_IO28, /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29, + MX6_PAD_RGMII_RD3__GPIO6_IO29, /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24, + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24, /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23, - MX6_PAD_ENET_RXD0__GPIO_1_27, + MX6_PAD_EIM_D23__GPIO3_IO23, + MX6_PAD_ENET_RXD0__GPIO1_IO27, }; -iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), +static iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; +static iomux_v3_cfg_t const misc_pads[] = { + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP), + /* OTG Power enable */ + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), +}; + /* wl1271 pads on nitrogen6x */ -iomux_v3_cfg_t const wl12xx_pads[] = { - (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) +static iomux_v3_cfg_t const wl12xx_pads[] = { + (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(WEAK_PULLDOWN), - (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) + (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(OUTPUT_40OHM), - (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) + (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(OUTPUT_40OHM), }; #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) @@ -195,17 +217,17 @@ iomux_v3_cfg_t const wl12xx_pads[] = { /* Button assignments for J14 */ static iomux_v3_cfg_t const button_pads[] = { /* Menu */ - MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Back */ - MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Labelled Search (mapped to Power under Android) */ - MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Home */ - MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Down */ - MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Up */ - MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -226,10 +248,11 @@ static void setup_iomux_enet(void) gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + udelay(100); /* Wait 100 us before using mii interface */ } -iomux_v3_cfg_t const usb_pads[] = { - MX6_PAD_GPIO_17__GPIO_7_12, +static iomux_v3_cfg_t const usb_pads[] = { + MX6_PAD_GPIO_17__GPIO7_IO12, }; static void setup_iomux_uart(void) @@ -250,10 +273,19 @@ int board_ehci_hcd_init(int port) return 0; } + +int board_ehci_power(int port, int on) +{ + if (port) + return 0; + gpio_set_value(GP_USB_OTG_PWR, on); + return 0; +} + #endif #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[2] = { +static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; @@ -261,22 +293,16 @@ struct fsl_esdhc_cfg usdhc_cfg[2] = { int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; + int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) : + IMX_GPIO_NR(2, 6); - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(7, 0)); - ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); - } else { - gpio_direction_input(IMX_GPIO_NR(2, 6)); - ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); - } - - return ret; + gpio_direction_input(gp_cd); + return !gpio_get_value(gp_cd); } int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -299,26 +325,33 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif #ifdef CONFIG_MXC_SPI -iomux_v3_cfg_t const ecspi1_pads[] = { +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; +} + +static iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ - MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19, MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), }; -void setup_spi(void) +static void setup_spi(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); @@ -369,6 +402,11 @@ int board_eth_init(bd_t *bis) free(bus); } #endif + +#ifdef CONFIG_CI_UDC + /* For otg ethernet*/ + usb_eth_initialize(bis); +#endif return 0; } @@ -378,108 +416,53 @@ static void setup_buttons(void) ARRAY_SIZE(button_pads)); } -#ifdef CONFIG_CMD_SATA - -int setup_sata(void) -{ - struct iomuxc_base_regs *const iomuxc_regs - = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; - int ret = enable_sata_clock(); - if (ret) - return ret; - - clrsetbits_le32(&iomuxc_regs->gpr[13], - IOMUXC_GPR13_SATA_MASK, - IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB - |IOMUXC_GPR13_SATA_PHY_7_SATA2M - |IOMUXC_GPR13_SATA_SPEED_3G - |(3<phy_stat0) & HDMI_PHY_HPD; -} - -static void enable_hdmi(struct display_info_t const *dev) +static void do_enable_hdmi(struct display_info_t const *dev) { - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg; - printf("%s: setup HDMI monitor\n", __func__); - reg = readb(&hdmi->phy_conf0); - reg |= HDMI_PHY_CONF0_PDZ_MASK; - writeb(reg, &hdmi->phy_conf0); - - udelay(3000); - reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - writeb(reg, &hdmi->phy_conf0); - udelay(3000); - reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - writeb(reg, &hdmi->phy_conf0); - writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); + imx_enable_hdmi_phy(); } static int detect_i2c(struct display_info_t const *dev) @@ -499,6 +482,17 @@ static void enable_lvds(struct display_info_t const *dev) gpio_direction_output(LVDS_BACKLIGHT_GP, 1); } +static void enable_lvds_jeida(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); +} + static void enable_rgb(struct display_info_t const *dev) { imx_iomux_v3_setup_multiple_pads( @@ -507,12 +501,12 @@ static void enable_rgb(struct display_info_t const *dev) gpio_direction_output(RGB_BACKLIGHT_GP, 1); } -static struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, +struct display_info_t const displays[] = {{ + .bus = 1, + .addr = 0x50, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = enable_hdmi, + .detect = detect_i2c, + .enable = do_enable_hdmi, .mode = { .name = "HDMI", .refresh = 60, @@ -527,6 +521,46 @@ static struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds_jeida, + .mode = { + .name = "LDB-WXGA", + .refresh = 60, + .xres = 1280, + .yres = 800, + .pixclock = 14065, + .left_margin = 40, + .right_margin = 40, + .upper_margin = 3, + .lower_margin = 80, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "LDB-WXGA-S", + .refresh = 60, + .xres = 1280, + .yres = 800, + .pixclock = 14065, + .left_margin = 40, + .right_margin = 40, + .upper_margin = 3, + .lower_margin = 80, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x4, @@ -547,6 +581,26 @@ static struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "LG-9.7", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, /* ~65MHz */ + .left_margin = 480, + .right_margin = 260, + .upper_margin = 16, + .lower_margin = 6, + .hsync_len = 250, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x38, @@ -567,6 +621,86 @@ static struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x10, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_rgb, + .mode = { + .name = "fusion7", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33898, + .left_margin = 96, + .right_margin = 24, + .upper_margin = 3, + .lower_margin = 10, + .hsync_len = 72, + .vsync_len = 7, + .sync = 0x40000002, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "svga", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x41, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "amp1024x600", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = 0, + .enable = enable_lvds, + .mode = { + .name = "wvga-lvds", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x48, @@ -587,79 +721,47 @@ static struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = 0, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "qvga", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = 37037, + .left_margin = 38, + .right_margin = 37, + .upper_margin = 16, + .lower_margin = 15, + .hsync_len = 30, + .vsync_len = 3, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED } } }; +size_t display_count = ARRAY_SIZE(displays); -int board_video_skip(void) +int board_cfb_skip(void) { - int i; - int ret; - char const *panel = getenv("panel"); - if (!panel) { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - struct display_info_t const *dev = displays+i; - if (dev->detect(dev)) { - panel = dev->mode.name; - printf("auto-detected panel %s\n", panel); - break; - } - } - if (!panel) { - panel = displays[0].mode.name; - printf("No panel detected: default to %s\n", panel); - } - } else { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - if (!strcmp(panel, displays[i].mode.name)) - break; - } - } - if (i < ARRAY_SIZE(displays)) { - ret = ipuv3_fb_init(&displays[i].mode, 0, - displays[i].pixfmt); - if (!ret) { - displays[i].enable(displays+i); - printf("Display: %s (%ux%u)\n", - displays[i].mode.name, - displays[i].mode.xres, - displays[i].mode.yres); - } else - printf("LCD %s cannot be configured: %d\n", - displays[i].mode.name, ret); - } else { - printf("unsupported panel %s\n", panel); - ret = -EINVAL; - } - return (0 != ret); + return NULL != getenv("novideo"); } static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - int reg; + enable_ipu_clock(); + imx_setup_hdmi(); /* Turn on LDB0,IPU,IPU DI0 clocks */ reg = __raw_readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET - |MXC_CCM_CCGR3_LDB_DI0_MASK; + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; writel(reg, &mxc_ccm->CCGR3); - /* Turn on HDMI PHY clock */ - reg = __raw_readl(&mxc_ccm->CCGR2); - reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK - |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; - writel(reg, &mxc_ccm->CCGR2); - - /* clear HDMI PHY reset */ - writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); - - /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ - writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); - writel(0x13<pfd_480_set); - /* set LDB0, LDB1 clk select to 011/011 */ reg = readl(&mxc_ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK @@ -673,15 +775,8 @@ static void setup_display(void) writel(reg, &mxc_ccm->cscmr2); reg = readl(&mxc_ccm->chsccdr); - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK - |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK - |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - <chsccdr); reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES @@ -696,7 +791,8 @@ static void setup_display(void) writel(reg, &iomux->gpr[2]); reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <gpr[3]); @@ -709,16 +805,62 @@ static void setup_display(void) } #endif +static iomux_v3_cfg_t const init_pads[] = { + /* SGTL5000 sys_mclk */ + NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), + + /* J5 - Camera MCLK */ + NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM), + + /* wl1271 pads on nitrogen6x */ + /* WL12XX_WL_IRQ_GP */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN), + /* WL12XX_WL_ENABLE_GP */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM), + /* WL12XX_BT_ENABLE_GP */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM), + /* USB otg power */ + NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM), + NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM), + NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM), + NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM), + NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM), +}; + +#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) + +static unsigned gpios_out_low[] = { + /* Disable wl1271 */ + IMX_GPIO_NR(6, 15), /* disable wireless */ + IMX_GPIO_NR(6, 16), /* disable bluetooth */ + IMX_GPIO_NR(3, 22), /* disable USB otg power */ + IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */ + IMX_GPIO_NR(1, 8), /* ov5642 reset */ +}; + +static unsigned gpios_out_high[] = { + IMX_GPIO_NR(1, 6), /* ov5642 powerdown */ + IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */ +}; + +static void set_gpios(unsigned *p, int cnt, int val) +{ + int i; + + for (i = 0; i < cnt; i++) + gpio_direction_output(*p++, val); +} + int board_early_init_f(void) { setup_iomux_uart(); - /* Disable wl1271 For Nitrogen6w */ + set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1); + set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0); gpio_direction_input(WL12XX_WL_IRQ_GP); - gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); - gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); + imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); setup_buttons(); #if defined(CONFIG_VIDEO_IPUV3) @@ -738,12 +880,22 @@ int overwrite_console(void) int board_init(void) { + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrsetbits_le32(&iomuxc_regs->gpr[1], + IOMUXC_GPR1_OTG_ID_MASK, + IOMUXC_GPR1_OTG_ID_GPIO1); + + imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_MXC_SPI setup_spi(); #endif + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); diff --git a/board/br4/Kconfig b/board/br4/Kconfig new file mode 100644 index 0000000000..a10a06053a --- /dev/null +++ b/board/br4/Kconfig @@ -0,0 +1,9 @@ +if TARGET_BR4 + +config SYS_BOARD + default "br4" + +config SYS_CONFIG_NAME + default "br4" + +endif diff --git a/board/br4/MAINTAINERS b/board/br4/MAINTAINERS new file mode 100644 index 0000000000..4085da5452 --- /dev/null +++ b/board/br4/MAINTAINERS @@ -0,0 +1,6 @@ +BR4 BOARD +M: Dimitar Penev +S: Maintained +F: board/br4/ +F: include/configs/br4.h +F: configs/br4_defconfig diff --git a/board/br4/Makefile b/board/br4/Makefile index f023abfee4..68e24ab83f 100644 --- a/board/br4/Makefile +++ b/board/br4/Makefile @@ -11,24 +11,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := br4.o diff --git a/board/br4/config.mk b/board/br4/config.mk deleted file mode 100644 index 5c18d5c9e4..0000000000 --- a/board/br4/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) Switchfin Org. -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/broadcom/bcm11130/MAINTAINERS b/board/broadcom/bcm11130/MAINTAINERS new file mode 100644 index 0000000000..b22e86f6b1 --- /dev/null +++ b/board/broadcom/bcm11130/MAINTAINERS @@ -0,0 +1,6 @@ +BCM11130 BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm_ep_board.h +F: configs/bcm11130_defconfig diff --git a/board/broadcom/bcm11130_nand/MAINTAINERS b/board/broadcom/bcm11130_nand/MAINTAINERS new file mode 100644 index 0000000000..881db5bf78 --- /dev/null +++ b/board/broadcom/bcm11130_nand/MAINTAINERS @@ -0,0 +1,6 @@ +BCM11130_NAND BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm_ep_board.h +F: configs/bcm11130_nand_defconfig diff --git a/board/broadcom/bcm28155_ap/Kconfig b/board/broadcom/bcm28155_ap/Kconfig new file mode 100644 index 0000000000..f1b4e08941 --- /dev/null +++ b/board/broadcom/bcm28155_ap/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BCM28155_AP + +config SYS_BOARD + default "bcm28155_ap" + +config SYS_VENDOR + default "broadcom" + +config SYS_SOC + default "bcm281xx" + +config SYS_CONFIG_NAME + default "bcm28155_ap" + +endif diff --git a/board/broadcom/bcm28155_ap/MAINTAINERS b/board/broadcom/bcm28155_ap/MAINTAINERS new file mode 100644 index 0000000000..a74c3941b2 --- /dev/null +++ b/board/broadcom/bcm28155_ap/MAINTAINERS @@ -0,0 +1,6 @@ +BCM28155_AP BOARD +M: Tim Kryger +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm28155_ap.h +F: configs/bcm28155_ap_defconfig diff --git a/board/broadcom/bcm28155_ap/Makefile b/board/broadcom/bcm28155_ap/Makefile new file mode 100644 index 0000000000..4bb9e70823 --- /dev/null +++ b/board/broadcom/bcm28155_ap/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += bcm28155_ap.o diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c new file mode 100644 index 0000000000..940a1c2c50 --- /dev/null +++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c @@ -0,0 +1,87 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 +#define SECWATCHDOG_SDOGCR_EN_SHIFT 27 +#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26 +#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20 +#define SECWATCHDOG_SDOGCR_LD_SHIFT 0 + +DECLARE_GLOBAL_DATA_PTR; + +/* + * board_init - early hardware init + */ +int board_init(void) +{ + printf("Relocation Offset is: %08lx\n", gd->reloc_off); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + clk_init(); + + return 0; +} + +/* + * misc_init_r - miscellaneous platform dependent initializations + */ +int misc_init_r(void) +{ + /* Disable watchdog reset - watchdog unused */ + writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) | + (0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) | + (4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) | + (0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT), + (SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET)); + + return 0; +} + +/* + * dram_init - sets uboots idea of sdram size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +/* This is called after dram_init() so use get_ram_size result */ +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +#ifdef CONFIG_KONA_SDHCI +/* + * mmc_init - Initializes mmc + */ +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + + /* Register eMMC - SDIO2 */ + ret = kona_sdhci_init(1, 400000, 0); + if (ret) + return ret; + + /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */ + ret = kona_sdhci_init(3, 400000, 0); + return ret; +} +#endif diff --git a/board/broadcom/bcm28155_w1d/MAINTAINERS b/board/broadcom/bcm28155_w1d/MAINTAINERS new file mode 100644 index 0000000000..a436490555 --- /dev/null +++ b/board/broadcom/bcm28155_w1d/MAINTAINERS @@ -0,0 +1,6 @@ +BCM28155_W1D BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm28155_ap.h +F: configs/bcm28155_w1d_defconfig diff --git a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS new file mode 100644 index 0000000000..b5f0207140 --- /dev/null +++ b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS @@ -0,0 +1,6 @@ +BCM911360_ENTPHN-NS BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm911360_entphn-ns_defconfig diff --git a/board/broadcom/bcm911360_entphn/MAINTAINERS b/board/broadcom/bcm911360_entphn/MAINTAINERS new file mode 100644 index 0000000000..fb7ee2bbc6 --- /dev/null +++ b/board/broadcom/bcm911360_entphn/MAINTAINERS @@ -0,0 +1,6 @@ +BCM911360_ENTPHN BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm911360_entphn_defconfig diff --git a/board/broadcom/bcm911360k/MAINTAINERS b/board/broadcom/bcm911360k/MAINTAINERS new file mode 100644 index 0000000000..754a15f0c7 --- /dev/null +++ b/board/broadcom/bcm911360k/MAINTAINERS @@ -0,0 +1,6 @@ +BCM911360K BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm911360k_defconfig diff --git a/board/broadcom/bcm958300k-ns/MAINTAINERS b/board/broadcom/bcm958300k-ns/MAINTAINERS new file mode 100644 index 0000000000..763401a3f1 --- /dev/null +++ b/board/broadcom/bcm958300k-ns/MAINTAINERS @@ -0,0 +1,6 @@ +BCM958300K-NS BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm958300k-ns_defconfig diff --git a/board/broadcom/bcm958300k/MAINTAINERS b/board/broadcom/bcm958300k/MAINTAINERS new file mode 100644 index 0000000000..8afc728a25 --- /dev/null +++ b/board/broadcom/bcm958300k/MAINTAINERS @@ -0,0 +1,6 @@ +BCM958300K BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm958300k_defconfig diff --git a/board/broadcom/bcm958305k/MAINTAINERS b/board/broadcom/bcm958305k/MAINTAINERS new file mode 100644 index 0000000000..179fd4ee9e --- /dev/null +++ b/board/broadcom/bcm958305k/MAINTAINERS @@ -0,0 +1,6 @@ +BCM958305K BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm958305k_defconfig diff --git a/board/broadcom/bcm958622hr/MAINTAINERS b/board/broadcom/bcm958622hr/MAINTAINERS new file mode 100644 index 0000000000..d08aded83f --- /dev/null +++ b/board/broadcom/bcm958622hr/MAINTAINERS @@ -0,0 +1,6 @@ +BCM958622HR BOARD +M: Steve Rae +S: Maintained +F: board/broadcom/bcmnsp/ +F: include/configs/bcm_ep_board.h +F: configs/bcm958622hr_defconfig diff --git a/board/broadcom/bcm_ep/Makefile b/board/broadcom/bcm_ep/Makefile new file mode 100644 index 0000000000..8914e547e8 --- /dev/null +++ b/board/broadcom/bcm_ep/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c new file mode 100644 index 0000000000..6a70a2e305 --- /dev/null +++ b/board/broadcom/bcm_ep/board.c @@ -0,0 +1,69 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * board_init - early hardware init + */ +int board_init(void) +{ + /* + * Address of boot parameters passed to kernel + * Use default offset 0x100 + */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/* + * dram_init - sets u-boot's idea of sdram size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +int board_early_init_f(void) +{ + uint32_t status = 0; + + /* Setup PLL if required */ +#if defined(CONFIG_ARMCLK) + armpll_config(CONFIG_ARMCLK); +#endif + + return status; +} + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ +} + +void smp_kick_all_cpus(void) +{ +} + +void smp_waitloop(unsigned previous_address) +{ +} +#endif diff --git a/board/broadcom/bcmcygnus/Kconfig b/board/broadcom/bcmcygnus/Kconfig new file mode 100644 index 0000000000..faba4cf82b --- /dev/null +++ b/board/broadcom/bcmcygnus/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BCMCYGNUS + +config SYS_BOARD + default "bcm_ep" + +config SYS_VENDOR + default "broadcom" + +config SYS_SOC + default "bcmcygnus" + +config SYS_CONFIG_NAME + default "bcm_ep_board" + +endif diff --git a/board/broadcom/bcmnsp/Kconfig b/board/broadcom/bcmnsp/Kconfig new file mode 100644 index 0000000000..a975082355 --- /dev/null +++ b/board/broadcom/bcmnsp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BCMNSP + +config SYS_BOARD + default "bcm_ep" + +config SYS_VENDOR + default "broadcom" + +config SYS_SOC + default "bcmnsp" + +config SYS_CONFIG_NAME + default "bcm_ep_board" + +endif diff --git a/board/buffalo/lsxl/Kconfig b/board/buffalo/lsxl/Kconfig new file mode 100644 index 0000000000..ef78896378 --- /dev/null +++ b/board/buffalo/lsxl/Kconfig @@ -0,0 +1,12 @@ +if TARGET_LSXL + +config SYS_BOARD + default "lsxl" + +config SYS_VENDOR + default "buffalo" + +config SYS_CONFIG_NAME + default "lsxl" + +endif diff --git a/board/buffalo/lsxl/MAINTAINERS b/board/buffalo/lsxl/MAINTAINERS new file mode 100644 index 0000000000..facc2dd7d9 --- /dev/null +++ b/board/buffalo/lsxl/MAINTAINERS @@ -0,0 +1,7 @@ +LSXL BOARD +M: Michael Walle +S: Maintained +F: board/buffalo/lsxl/ +F: include/configs/lsxl.h +F: configs/lschlv2_defconfig +F: configs/lsxhl_defconfig diff --git a/board/buffalo/lsxl/Makefile b/board/buffalo/lsxl/Makefile index a8700e8430..1b01b4018c 100644 --- a/board/buffalo/lsxl/Makefile +++ b/board/buffalo/lsxl/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := lsxl.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := lsxl.o diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index eca1683a6f..b0d49c4ee6 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -13,11 +13,12 @@ #include #include #include -#include +#include +#include +#include #include #include #include -#include #include "lsxl.h" @@ -51,9 +52,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(LSXL_OE_VAL_LOW, - LSXL_OE_VAL_HIGH, - LSXL_OE_LOW, LSXL_OE_HIGH); + mvebu_config_gpio(LSXL_OE_VAL_LOW, + LSXL_OE_VAL_HIGH, + LSXL_OE_LOW, LSXL_OE_HIGH); /* * Multi-Purpose Pins Functionality configuration @@ -167,7 +168,7 @@ static void set_led(int state) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; set_led(LED_POWER_BLINKING); @@ -231,7 +232,7 @@ static void rescue_mode(void) printf("Entering rescue mode..\n"); #ifdef CONFIG_RANDOM_MACADDR if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - eth_random_enetaddr(enetaddr); + eth_random_addr(enetaddr); if (eth_setenv_enetaddr("ethaddr", enetaddr)) { printf("Failed to set ethernet address\n"); set_led(LED_ALARM_BLINKING); diff --git a/board/calao/sbc35_a9g20/Kconfig b/board/calao/sbc35_a9g20/Kconfig new file mode 100644 index 0000000000..fb5a1a3f42 --- /dev/null +++ b/board/calao/sbc35_a9g20/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SBC35_A9G20 + +config SYS_BOARD + default "sbc35_a9g20" + +config SYS_VENDOR + default "calao" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sbc35_a9g20" + +endif diff --git a/board/calao/sbc35_a9g20/MAINTAINERS b/board/calao/sbc35_a9g20/MAINTAINERS new file mode 100644 index 0000000000..0ac8225d06 --- /dev/null +++ b/board/calao/sbc35_a9g20/MAINTAINERS @@ -0,0 +1,7 @@ +SBC35_A9G20 BOARD +#M: Albin Tonnerre +S: Orphan (since 2014-06) +F: board/calao/sbc35_a9g20/ +F: include/configs/sbc35_a9g20.h +F: configs/sbc35_a9g20_eeprom_defconfig +F: configs/sbc35_a9g20_nandflash_defconfig diff --git a/board/calao/sbc35_a9g20/Makefile b/board/calao/sbc35_a9g20/Makefile index e385f8d370..9ae2d24c59 100644 --- a/board/calao/sbc35_a9g20/Makefile +++ b/board/calao/sbc35_a9g20/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += sbc35_a9g20.o -COBJS-$(CONFIG_ATMEL_SPI) += spi.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += sbc35_a9g20.o +obj-$(CONFIG_ATMEL_SPI) += spi.o diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index ecf261c1ae..2074a93a12 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -77,8 +76,6 @@ static void sbc35_a9g20_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable EMAC clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); @@ -102,21 +99,7 @@ static void sbc35_a9g20_macb_hw_init(void) pin_to_mask(AT91_PIN_PA28), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | diff --git a/board/calao/tny_a9260/Kconfig b/board/calao/tny_a9260/Kconfig new file mode 100644 index 0000000000..b1de8f8ba8 --- /dev/null +++ b/board/calao/tny_a9260/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TNY_A9260 + +config SYS_BOARD + default "tny_a9260" + +config SYS_VENDOR + default "calao" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "tny_a9260" + +endif diff --git a/board/calao/tny_a9260/MAINTAINERS b/board/calao/tny_a9260/MAINTAINERS new file mode 100644 index 0000000000..1f24e3948b --- /dev/null +++ b/board/calao/tny_a9260/MAINTAINERS @@ -0,0 +1,9 @@ +TNY_A9260 BOARD +#M: Albin Tonnerre +S: Orphan (since 2014-06) +F: board/calao/tny_a9260/ +F: include/configs/tny_a9260.h +F: configs/tny_a9260_eeprom_defconfig +F: configs/tny_a9260_nandflash_defconfig +F: configs/tny_a9g20_eeprom_defconfig +F: configs/tny_a9g20_nandflash_defconfig diff --git a/board/calao/tny_a9260/Makefile b/board/calao/tny_a9260/Makefile index 8a95ce252e..55a6157bac 100644 --- a/board/calao/tny_a9260/Makefile +++ b/board/calao/tny_a9260/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += tny_a9260.o -COBJS-$(CONFIG_ATMEL_SPI) += spi.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += tny_a9260.o +obj-$(CONFIG_ATMEL_SPI) += spi.o diff --git a/board/calao/usb_a9263/Kconfig b/board/calao/usb_a9263/Kconfig new file mode 100644 index 0000000000..7a159dc3ba --- /dev/null +++ b/board/calao/usb_a9263/Kconfig @@ -0,0 +1,15 @@ +if TARGET_USB_A9263 + +config SYS_BOARD + default "usb_a9263" + +config SYS_VENDOR + default "calao" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "usb_a9263" + +endif diff --git a/board/calao/usb_a9263/MAINTAINERS b/board/calao/usb_a9263/MAINTAINERS new file mode 100644 index 0000000000..2f39cd3def --- /dev/null +++ b/board/calao/usb_a9263/MAINTAINERS @@ -0,0 +1,6 @@ +USB_A9263 BOARD +M: Mateusz Kulikowski +S: Maintained +F: board/calao/usb_a9263/ +F: include/configs/usb_a9263.h +F: configs/usb_a9263_dataflash_defconfig diff --git a/board/calao/usb_a9263/Makefile b/board/calao/usb_a9263/Makefile new file mode 100644 index 0000000000..8a22b3eac7 --- /dev/null +++ b/board/calao/usb_a9263/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# (C) Copyright 2013 +# Mateusz Kulikowski +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += usb_a9263.o diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c new file mode 100644 index 0000000000..266e9507ef --- /dev/null +++ b/board/calao/usb_a9263/usb_a9263.c @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2007-2013 + * Stelian Pop + * Lead Tech Design + * Thomas Petazzoni, Free Electrons, + * Mateusz Kulikowski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_HAS_DATAFLASH +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00004000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"}, +}; +#endif + +#ifdef CONFIG_CMD_NAND +static void usb_a9263_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); + + writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer); + + /* Configure RDY/BSY */ + gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy"); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + + /* Enable NandFlash */ + gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable"); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void usb_a9263_macb_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal weak pull-up/pull-down + */ + gpio_request(GPIO_PIN_PC(25), "PHY mode"); + gpio_direction_input(GPIO_PIN_PC(25)); + + gpio_request(GPIO_PIN_PE(25), "PHY ADDR0"); + gpio_direction_input(GPIO_PIN_PE(25)); + + gpio_request(GPIO_PIN_PE(26), "PHY ADDR1"); + gpio_direction_input(GPIO_PIN_PE(26)); + + at91_phy_reset(); + + /* It will set proper pinmux for ports PC25, PE25-26 */ + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + usb_a9263_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + usb_a9263_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001); +#endif + return rc; +} diff --git a/board/canmb/Kconfig b/board/canmb/Kconfig new file mode 100644 index 0000000000..b5cf2057f4 --- /dev/null +++ b/board/canmb/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CANMB + +config SYS_BOARD + default "canmb" + +config SYS_CONFIG_NAME + default "canmb" + +endif diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS new file mode 100644 index 0000000000..71750ead47 --- /dev/null +++ b/board/canmb/MAINTAINERS @@ -0,0 +1,6 @@ +CANMB BOARD +#M: - +S: Maintained +F: board/canmb/ +F: include/configs/canmb.h +F: configs/canmb_defconfig diff --git a/board/canmb/Makefile b/board/canmb/Makefile index 4698706bb9..4286a9123c 100644 --- a/board/canmb/Makefile +++ b/board/canmb/Makefile @@ -5,28 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -#ifneq ($(OBJTREE),$(SRCTREE)) -#$(shell mkdir -p $(obj)../common) -#endif +obj-y := canmb.o -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -#../common/flash.o ../common/vpd.o ../common/am79c874.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile deleted file mode 100644 index e2222ab674..0000000000 --- a/board/chromebook-x86/coreboot/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright (c) 2011 The Chromium OS Authors. -# (C) Copyright 2008 -# Graeme Russ, graeme.russ@gmail.com. -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -SOBJS-y += coreboot_start.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk deleted file mode 100644 index f720851aac..0000000000 --- a/board/chromebook-x86/coreboot/config.mk +++ /dev/null @@ -1,37 +0,0 @@ -# -# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following disclaimer -# in the documentation and/or other materials provided with the -# distribution. -# * Neither the name of Google Inc. nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Alternatively, this software may be distributed under the terms of the -# GNU General Public License ("GPL") version 2 as published by the Free -# Software Foundation. -# - -HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros diff --git a/board/chromebook-x86/dts/alex.dts b/board/chromebook-x86/dts/alex.dts deleted file mode 100644 index cb6a9e41ee..0000000000 --- a/board/chromebook-x86/dts/alex.dts +++ /dev/null @@ -1,24 +0,0 @@ -/dts-v1/; - -/include/ "coreboot.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Google Alex"; - compatible = "google,alex", "intel,atom-pineview"; - - config { - silent_console = <0>; - }; - - gpio: gpio {}; - - serial { - reg = <0x3f8 8>; - clock-frequency = <115200>; - }; - - chosen { }; - memory { device_type = "memory"; reg = <0 0>; }; -}; diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts deleted file mode 100644 index c95ee8a108..0000000000 --- a/board/chromebook-x86/dts/link.dts +++ /dev/null @@ -1,35 +0,0 @@ -/dts-v1/; - -/include/ "coreboot.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Google Link"; - compatible = "google,link", "intel,celeron-ivybridge"; - - config { - silent_console = <0>; - }; - - gpio: gpio {}; - - serial { - reg = <0x3f8 8>; - clock-frequency = <115200>; - }; - - chosen { }; - memory { device_type = "memory"; reg = <0 0>; }; - - spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich9"; - spi-flash@0 { - reg = <0>; - compatible = "winbond,w25q64", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - }; - }; -}; diff --git a/board/cirrus/edb93xx/Kconfig b/board/cirrus/edb93xx/Kconfig new file mode 100644 index 0000000000..c5f4897f8a --- /dev/null +++ b/board/cirrus/edb93xx/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EDB93XX + +config SYS_BOARD + default "edb93xx" + +config SYS_VENDOR + default "cirrus" + +config SYS_SOC + default "ep93xx" + +config SYS_CONFIG_NAME + default "edb93xx" + +endif diff --git a/board/cirrus/edb93xx/MAINTAINERS b/board/cirrus/edb93xx/MAINTAINERS new file mode 100644 index 0000000000..3bb284335b --- /dev/null +++ b/board/cirrus/edb93xx/MAINTAINERS @@ -0,0 +1,6 @@ +EDB93XX BOARD +M: Sergey Kostanbaev +S: Maintained +F: board/cirrus/edb93xx/ +F: include/configs/edb93xx.h +F: configs/edb9315a_defconfig diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile new file mode 100644 index 0000000000..d03c498478 --- /dev/null +++ b/board/cirrus/edb93xx/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2013 +# Sergey Kostanbaev fairwaves.ru> +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd denx.de. +# +# * SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := edb93xx.o diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c new file mode 100644 index 0000000000..8963d3a582 --- /dev/null +++ b/board/cirrus/edb93xx/edb93xx.c @@ -0,0 +1,382 @@ +/* + * Board initialization for EP93xx + * + * Copyright (C) 2013 + * Sergey Kostanbaev fairwaves.ru> + * + * Copyright (C) 2009 + * Matthias Kaehlcke kaehlcke.net> + * + * (C) Copyright 2002 2003 + * Network Audio Technologies, Inc. + * Adam Bezanson netaudiotech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * usb_div: 4, nbyp2: 1, pll2_en: 1 + * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, + * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 + */ +#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ + SYSCON_CLKSET2_PLL2_EN | \ + SYSCON_CLKSET2_NBYP2 | \ + 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) + +#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ + SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ + 1 << SMC_BCR_MW_SHIFT) + +/* delay execution before timers are initialized */ +static inline void early_udelay(uint32_t usecs) +{ + /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ + register uint32_t loops = (usecs * 1000) / 20; + + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +#ifndef CONFIG_EP93XX_NO_FLASH_CFG +static void flash_cfg(void) +{ + struct smc_regs *smc = (struct smc_regs *)SMC_BASE; + + writel(SMC_BCR6_VALUE, &smc->bcr6); +} +#else +#define flash_cfg() +#endif + +int board_init(void) +{ + /* + * Setup PLL2, PPL1 has been set during lowlevel init + */ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + writel(CLKSET2_VAL, &syscon->clkset2); + + /* + * the user's guide recommends to wait at least 1 ms for PLL2 to + * stabilize + */ + early_udelay(1000); + + /* Go to Async mode */ + __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0"); + __asm__ volatile ("orr r0, r0, #0xc0000000"); + __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0"); + + icache_enable(); + +#ifdef USE_920T_MMU + dcache_enable(); +#endif + + /* Machine number, as defined in linux/arch/arm/tools/mach-types */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* We have a console */ + gd->have_console = 1; + + enable_interrupts(); + + flash_cfg(); + + green_led_on(); + red_led_off(); + + return 0; +} + +int board_early_init_f(void) +{ + /* + * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of + * 14.7456/2 MHz + */ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt); + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ep93xx_eth_initialize(0, MAC_BASE); +} + +static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt, + unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]) +{ + if (dram_bank_cnt == 1) { + dram_bank_base[0] = PHYS_SDRAM_1; + } else { + /* Table lookup for holes in address space. Maximum memory + * for the single SDCS may be up to 256Mb. We start scanning + * banks from 1Mb, so it could be up to 128 banks theoretically. + * We need at maximum 7 bits for the loockup, 8 slots is + * enough for the worst case. + */ + unsigned tbl[8]; + unsigned i = dram_bank_cnt / 2; + unsigned j = 0x00100000; /* 1 Mb */ + unsigned *ptbl = tbl; + do { + while (!(dram_addr_mask & j)) { + j <<= 1; + } + *ptbl++ = j; + j <<= 1; + i >>= 1; + } while (i != 0); + + for (i = dram_bank_cnt, j = 0; + (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) { + unsigned addr = PHYS_SDRAM_1; + unsigned k; + unsigned bit; + + for (k = 0, bit = 1; k < 8; k++, bit <<= 1) { + if (bit & j) + addr |= tbl[k]; + } + + dram_bank_base[j] = addr; + } + } +} + +/* called in board_init_f (before relocation) */ +static unsigned dram_init_banksize_int(int print) +{ + /* + * Collect information of banks that has been filled during lowlevel + * initialization + */ + unsigned i; + unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]; + unsigned dram_total = 0; + unsigned dram_bank_size = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE); + unsigned dram_addr_mask = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK); + unsigned dram_bank_cnt = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT); + + dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base); + + for (i = 0; i < dram_bank_cnt; i++) { + gd->bd->bi_dram[i].start = dram_bank_base[i]; + gd->bd->bi_dram[i].size = dram_bank_size; + dram_total += dram_bank_size; + } + for (; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = 0; + gd->bd->bi_dram[i].size = 0; + } + + if (print) { + printf("DRAM mask: %08x\n", dram_addr_mask); + printf("DRAM total %u banks:\n", dram_bank_cnt); + printf("bank base-address size\n"); + + if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) { + printf("WARNING! UBoot was configured for %u banks,\n" + "but %u has been found. " + "Supressing extra memory banks\n", + CONFIG_NR_DRAM_BANKS, dram_bank_cnt); + dram_bank_cnt = CONFIG_NR_DRAM_BANKS; + } + + for (i = 0; i < dram_bank_cnt; i++) { + printf(" %u %08x %08x\n", + i, dram_bank_base[i], dram_bank_size); + } + printf(" ------------------------------------------\n" + "Total %9d\n\n", + dram_total); + } + + return dram_total; +} + +void dram_init_banksize(void) +{ + dram_init_banksize_int(0); +} + +/* called in board_init_f (before relocation) */ +int dram_init(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + unsigned sec_id = readl(SECURITY_EXTENSIONID); + unsigned chip_id = readl(&syscon->chipid); + + printf("CPU: Cirrus Logic "); + switch (sec_id & 0x000001FE) { + case 0x00000008: + printf("EP9301"); + break; + case 0x00000004: + printf("EP9307"); + break; + case 0x00000002: + printf("EP931x"); + break; + case 0x00000000: + printf("EP9315"); + break; + default: + printf(""); + break; + } + + printf(" - Rev. "); + switch (chip_id & 0xF0000000) { + case 0x00000000: + printf("A"); + break; + case 0x10000000: + printf("B"); + break; + case 0x20000000: + printf("C"); + break; + case 0x30000000: + printf("D0"); + break; + case 0x40000000: + printf("D1"); + break; + case 0x50000000: + printf("E0"); + break; + case 0x60000000: + printf("E1"); + break; + case 0x70000000: + printf("E2"); + break; + default: + printf("?"); + break; + } + printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id); + + gd->ram_size = dram_init_banksize_int(1); + return 0; +} + + +#ifdef CONFIG_EP93XX_SPI +#include + +/* + * EGIO0-EGIPO7 -> port A + * EGIO8-EGIP15 -> port B + */ + +static void ep93xx_set_epgio(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->padr) | (1<padr); + else + writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr); +} + +static void ep93xx_clear_epgio(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->padr) & (~(1<padr); + else + writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr); +} + +static void ep93xx_dir_epgio_out(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->paddr) | (1<paddr); + else + writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (bus == 0 && cs < 16) + return 1; + + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + ep93xx_clear_epgio(slave->cs); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + ep93xx_set_epgio(slave->cs); +} + +#ifdef CONFIG_MMC_SPI +#include + +#ifndef CONFIG_MMC_SPI_CS_EPGIO +# define CONFIG_MMC_SPI_CS_EPGIO 4 +#endif + +#ifndef CONFIG_MMC_SPI_SPEED +# define CONFIG_MMC_SPI_SPEED 25000000 +#endif + +#ifndef CONFIG_MMC_SPI_MODE +# define CONFIG_MMC_SPI_MODE SPI_MODE_0 +#endif + +int board_mmc_init(bd_t *bis) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + + ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO); + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO); + +#ifdef CONFIG_MMC_SPI_POWER_EGPIO + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO); + ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO); +#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO) + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO); + ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO); +#endif + struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO, + CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE); + + if (!mmc) { + printf("Failed to create MMC Device\n"); + return 1; + } + mmc_init(mmc); + return 0; +} + + +#endif /* CONFIG_MMC_SPI */ +#endif /* CONFIG_EP93XX_SPI */ diff --git a/board/cirrus/edb93xx/u-boot.lds b/board/cirrus/edb93xx/u-boot.lds new file mode 100644 index 0000000000..4aa7891660 --- /dev/null +++ b/board/cirrus/edb93xx/u-boot.lds @@ -0,0 +1,116 @@ +/* + * + * Copyright (C) 2013 + * Sergey Kostanbaev fairwaves.ru> + * + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : { + *(.__image_copy_start) + *(.vectors) + arch/arm/cpu/arm920t/start.o (.text*) + . = 0x1000; + + LONG(0x53555243) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu.hash : { *(.gnu.hash) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } +} diff --git a/board/cloudengines/pogo_e02/Kconfig b/board/cloudengines/pogo_e02/Kconfig new file mode 100644 index 0000000000..eaa68d9375 --- /dev/null +++ b/board/cloudengines/pogo_e02/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POGO_E02 + +config SYS_BOARD + default "pogo_e02" + +config SYS_VENDOR + default "cloudengines" + +config SYS_CONFIG_NAME + default "pogo_e02" + +endif diff --git a/board/cloudengines/pogo_e02/MAINTAINERS b/board/cloudengines/pogo_e02/MAINTAINERS new file mode 100644 index 0000000000..42c5dda306 --- /dev/null +++ b/board/cloudengines/pogo_e02/MAINTAINERS @@ -0,0 +1,6 @@ +POGO_E02 BOARD +M: Dave Purdy +S: Maintained +F: board/cloudengines/pogo_e02/ +F: include/configs/pogo_e02.h +F: configs/pogo_e02_defconfig diff --git a/board/cloudengines/pogo_e02/Makefile b/board/cloudengines/pogo_e02/Makefile index 3bda5e1eb7..8ff0f4505c 100644 --- a/board/cloudengines/pogo_e02/Makefile +++ b/board/cloudengines/pogo_e02/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := pogo_e02.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := pogo_e02.o diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index 0e632582d3..8309d06882 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include "pogo_e02.h" @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(POGO_E02_OE_VAL_LOW, - POGO_E02_OE_VAL_HIGH, - POGO_E02_OE_LOW, POGO_E02_OE_HIGH); + mvebu_config_gpio(POGO_E02_OE_VAL_LOW, + POGO_E02_OE_VAL_HIGH, + POGO_E02_OE_LOW, POGO_E02_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -64,7 +64,7 @@ int board_early_init_f(void) int board_init(void) { /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/cm-bf527/Kconfig b/board/cm-bf527/Kconfig new file mode 100644 index 0000000000..8d14179124 --- /dev/null +++ b/board/cm-bf527/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CM_BF527 + +config SYS_BOARD + default "cm-bf527" + +config SYS_CONFIG_NAME + default "cm-bf527" + +endif diff --git a/board/cm-bf527/MAINTAINERS b/board/cm-bf527/MAINTAINERS new file mode 100644 index 0000000000..fefcfcfb7d --- /dev/null +++ b/board/cm-bf527/MAINTAINERS @@ -0,0 +1,6 @@ +CM-BF527 BOARD +#M: Bluetechnix Tinyboards +S: Orphan (since 2014-03) +F: board/cm-bf527/ +F: include/configs/cm-bf527.h +F: configs/cm-bf527_defconfig diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile index 57b0a7c83d..ff8ad43d51 100644 --- a/board/cm-bf527/Makefile +++ b/board/cm-bf527/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o gpio_cfi_flash.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm-bf527.o gpio_cfi_flash.o diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c index a5f70a4f83..1533eb9c7a 100644 --- a/board/cm-bf527/cm-bf527.c +++ b/board/cm-bf527/cm-bf527.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include "../cm-bf537e/gpio_cfi_flash.h" @@ -46,7 +45,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/cm-bf527/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/cm-bf533/Kconfig b/board/cm-bf533/Kconfig new file mode 100644 index 0000000000..cedd7529d5 --- /dev/null +++ b/board/cm-bf533/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CM_BF533 + +config SYS_BOARD + default "cm-bf533" + +config SYS_CONFIG_NAME + default "cm-bf533" + +endif diff --git a/board/cm-bf533/MAINTAINERS b/board/cm-bf533/MAINTAINERS new file mode 100644 index 0000000000..0bf51fb1ea --- /dev/null +++ b/board/cm-bf533/MAINTAINERS @@ -0,0 +1,6 @@ +CM-BF533 BOARD +#M: Bluetechnix Tinyboards +S: Orphan (since 2014-03) +F: board/cm-bf533/ +F: include/configs/cm-bf533.h +F: configs/cm-bf533_defconfig diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile index b7275f49fe..ec99638d0a 100644 --- a/board/cm-bf533/Makefile +++ b/board/cm-bf533/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm-bf533.o diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk index 973d357559..7f9138b09b 100644 --- a/board/cm-bf533/config.mk +++ b/board/cm-bf533/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537e/Kconfig b/board/cm-bf537e/Kconfig new file mode 100644 index 0000000000..af2e548cb9 --- /dev/null +++ b/board/cm-bf537e/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CM_BF537E + +config SYS_BOARD + default "cm-bf537e" + +config SYS_CONFIG_NAME + default "cm-bf537e" + +endif diff --git a/board/cm-bf537e/MAINTAINERS b/board/cm-bf537e/MAINTAINERS new file mode 100644 index 0000000000..63d242893e --- /dev/null +++ b/board/cm-bf537e/MAINTAINERS @@ -0,0 +1,6 @@ +CM-BF537E BOARD +#M: Bluetechnix Tinyboards +S: Orphan (since 2014-03) +F: board/cm-bf537e/ +F: include/configs/cm-bf537e.h +F: configs/cm-bf537e_defconfig diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile index 57b0a7c83d..be8056f4ba 100644 --- a/board/cm-bf537e/Makefile +++ b/board/cm-bf537e/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o gpio_cfi_flash.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm-bf537e.o gpio_cfi_flash.o diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c index 8daf3ad06e..e79f90f95b 100644 --- a/board/cm-bf537e/cm-bf537e.c +++ b/board/cm-bf537e/cm-bf537e.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,7 +31,7 @@ static void board_init_enetaddr(char *var) return; printf("Warning: %s: generating 'random' MAC address\n", var); - bfin_gen_rand_mac(enetaddr); + eth_random_addr(enetaddr); eth_setenv_enetaddr(var, enetaddr); } diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk index 973d357559..7f9138b09b 100644 --- a/board/cm-bf537e/config.mk +++ b/board/cm-bf537e/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537u/Kconfig b/board/cm-bf537u/Kconfig new file mode 100644 index 0000000000..baf9e8cf61 --- /dev/null +++ b/board/cm-bf537u/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CM_BF537U + +config SYS_BOARD + default "cm-bf537u" + +config SYS_CONFIG_NAME + default "cm-bf537u" + +endif diff --git a/board/cm-bf537u/MAINTAINERS b/board/cm-bf537u/MAINTAINERS new file mode 100644 index 0000000000..a89cfcae74 --- /dev/null +++ b/board/cm-bf537u/MAINTAINERS @@ -0,0 +1,6 @@ +CM-BF537U BOARD +#M: Bluetechnix Tinyboards +S: Orphan (since 2014-03) +F: board/cm-bf537u/ +F: include/configs/cm-bf537u.h +F: configs/cm-bf537u_defconfig diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile index 57b0a7c83d..38dd3fbb21 100644 --- a/board/cm-bf537u/Makefile +++ b/board/cm-bf537u/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o gpio_cfi_flash.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm-bf537u.o gpio_cfi_flash.o diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c index 5941b5fcbe..632cbda5c0 100644 --- a/board/cm-bf537u/cm-bf537u.c +++ b/board/cm-bf537u/cm-bf537u.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,7 +31,7 @@ static void board_init_enetaddr(char *var) return; printf("Warning: %s: generating 'random' MAC address\n", var); - bfin_gen_rand_mac(enetaddr); + eth_random_addr(enetaddr); eth_setenv_enetaddr(var, enetaddr); } diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk index 973d357559..7f9138b09b 100644 --- a/board/cm-bf537u/config.mk +++ b/board/cm-bf537u/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf548/Kconfig b/board/cm-bf548/Kconfig new file mode 100644 index 0000000000..b96cb5f153 --- /dev/null +++ b/board/cm-bf548/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CM_BF548 + +config SYS_BOARD + default "cm-bf548" + +config SYS_CONFIG_NAME + default "cm-bf548" + +endif diff --git a/board/cm-bf548/MAINTAINERS b/board/cm-bf548/MAINTAINERS new file mode 100644 index 0000000000..b7f5779cef --- /dev/null +++ b/board/cm-bf548/MAINTAINERS @@ -0,0 +1,6 @@ +CM-BF548 BOARD +#M: Bluetechnix Tinyboards +S: Orphan (since 2014-03) +F: board/cm-bf548/ +F: include/configs/cm-bf548.h +F: configs/cm-bf548_defconfig diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile index 1a6ca64c72..98aca32b1f 100644 --- a/board/cm-bf548/Makefile +++ b/board/cm-bf548/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_VIDEO) += video.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm-bf548.o +obj-$(CONFIG_VIDEO) += video.o diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk index c005afb881..beb9834649 100644 --- a/board/cm-bf548/config.mk +++ b/board/cm-bf548/config.mk @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1 diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index a43413e976..b098615d4c 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -282,14 +283,6 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) } -void video_putc(const char c) -{ -} - -void video_puts(const char *s) -{ -} - int drv_video_init(void) { int error, devices = 1; @@ -341,8 +334,6 @@ int drv_video_init(void) strcpy(videodev.name, "video"); videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ error = stdio_register(&videodev); diff --git a/board/cm-bf561/Kconfig b/board/cm-bf561/Kconfig new file mode 100644 index 0000000000..8b302a5c8f --- /dev/null +++ b/board/cm-bf561/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CM_BF561 + +config SYS_BOARD + default "cm-bf561" + +config SYS_CONFIG_NAME + default "cm-bf561" + +endif diff --git a/board/cm-bf561/MAINTAINERS b/board/cm-bf561/MAINTAINERS new file mode 100644 index 0000000000..9c86c8d39a --- /dev/null +++ b/board/cm-bf561/MAINTAINERS @@ -0,0 +1,6 @@ +CM-BF561 BOARD +#M: Bluetechnix Tinyboards +S: Orphan (since 2014-03) +F: board/cm-bf561/ +F: include/configs/cm-bf561.h +F: configs/cm-bf561_defconfig diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile index b7275f49fe..c8764fb3ce 100644 --- a/board/cm-bf561/Makefile +++ b/board/cm-bf561/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm-bf561.o diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk index c33aef9d28..854d7dbb86 100644 --- a/board/cm-bf561/config.mk +++ b/board/cm-bf561/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/cm4008/Kconfig b/board/cm4008/Kconfig new file mode 100644 index 0000000000..de87d5bc12 --- /dev/null +++ b/board/cm4008/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM4008 + +config SYS_BOARD + default "cm4008" + +config SYS_SOC + default "ks8695" + +config SYS_CONFIG_NAME + default "cm4008" + +endif diff --git a/board/cm4008/MAINTAINERS b/board/cm4008/MAINTAINERS new file mode 100644 index 0000000000..5f08bc3b5c --- /dev/null +++ b/board/cm4008/MAINTAINERS @@ -0,0 +1,6 @@ +CM4008 BOARD +M: Greg Ungerer +S: Maintained +F: board/cm4008/ +F: include/configs/cm4008.h +F: configs/cm4008_defconfig diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile index d8f9d5400a..04b152917b 100644 --- a/board/cm4008/Makefile +++ b/board/cm4008/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cm4008.o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm4008.o flash.o diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 251192839e..8315a57ed9 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -57,7 +57,7 @@ unsigned long flash_init (void) */ flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start_ofs, + CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), &flash_info[0]); return size; diff --git a/board/cm41xx/Kconfig b/board/cm41xx/Kconfig new file mode 100644 index 0000000000..99e675b12d --- /dev/null +++ b/board/cm41xx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM41XX + +config SYS_BOARD + default "cm41xx" + +config SYS_SOC + default "ks8695" + +config SYS_CONFIG_NAME + default "cm41xx" + +endif diff --git a/board/cm41xx/MAINTAINERS b/board/cm41xx/MAINTAINERS new file mode 100644 index 0000000000..f10eeb58f3 --- /dev/null +++ b/board/cm41xx/MAINTAINERS @@ -0,0 +1,6 @@ +CM41XX BOARD +#M: - +S: Maintained +F: board/cm41xx/ +F: include/configs/cm41xx.h +F: configs/cm41xx_defconfig diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile index 752bfdb2ff..b71ea05566 100644 --- a/board/cm41xx/Makefile +++ b/board/cm41xx/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cm41xx.o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm41xx.o flash.o diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 251192839e..8315a57ed9 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -57,7 +57,7 @@ unsigned long flash_init (void) */ flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start_ofs, + CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), &flash_info[0]); return size; diff --git a/board/cm5200/Kconfig b/board/cm5200/Kconfig new file mode 100644 index 0000000000..ccea5c96e4 --- /dev/null +++ b/board/cm5200/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CM5200 + +config SYS_BOARD + default "cm5200" + +config SYS_CONFIG_NAME + default "cm5200" + +endif diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS new file mode 100644 index 0000000000..1e1df3f6dc --- /dev/null +++ b/board/cm5200/MAINTAINERS @@ -0,0 +1,6 @@ +CM5200 BOARD +#M: - +S: Maintained +F: board/cm5200/ +F: include/configs/cm5200.h +F: configs/cm5200_defconfig diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile index 59353e9895..76f8b9fc05 100644 --- a/board/cm5200/Makefile +++ b/board/cm5200/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o cmd_cm5200.o fwupdate.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cm5200.o cmd_cm5200.o fwupdate.o diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index e391dfc9e1..5276907b45 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -16,7 +16,7 @@ * - run-time SDRAM controller configuration * - LIBFDT support * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -359,9 +359,11 @@ int last_stage_init(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); ft_blob_update(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h index 9abc3568b6..c2573f3bf6 100644 --- a/board/cm5200/cm5200.h +++ b/board/cm5200/cm5200.h @@ -4,7 +4,7 @@ * Author: Bartlomiej Sieka * Author: Grzegorz Bernacki * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CM5200_H diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c index e963eb553f..06d50234e9 100644 --- a/board/cm5200/fwupdate.c +++ b/board/cm5200/fwupdate.c @@ -7,7 +7,7 @@ * - code clean-up * - bugfix for overwriting bootargs by user * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h index ca77f89ab0..6ddf0bac35 100644 --- a/board/cm5200/fwupdate.h +++ b/board/cm5200/fwupdate.h @@ -3,7 +3,7 @@ * * Author: Michel Marti * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __FW_UPDATE_H diff --git a/board/cmi/Kconfig b/board/cmi/Kconfig new file mode 100644 index 0000000000..6efe6b1cb7 --- /dev/null +++ b/board/cmi/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CMI_MPC5XX + +config SYS_BOARD + default "cmi" + +config SYS_CONFIG_NAME + default "cmi_mpc5xx" + +endif diff --git a/board/cmi/MAINTAINERS b/board/cmi/MAINTAINERS new file mode 100644 index 0000000000..60701bfd99 --- /dev/null +++ b/board/cmi/MAINTAINERS @@ -0,0 +1,6 @@ +CMI BOARD +#M: - +S: Maintained +F: board/cmi/ +F: include/configs/cmi_mpc5xx.h +F: configs/cmi_mpc5xx_defconfig diff --git a/board/cmi/Makefile b/board/cmi/Makefile index 0d1c6fbb21..cd3bb0db21 100644 --- a/board/cmi/Makefile +++ b/board/cmi/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := flash.o cmi.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := flash.o cmi.o diff --git a/board/cobra5272/Kconfig b/board/cobra5272/Kconfig new file mode 100644 index 0000000000..ba04622c21 --- /dev/null +++ b/board/cobra5272/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COBRA5272 + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "cobra5272" + +config SYS_CONFIG_NAME + default "cobra5272" + +endif diff --git a/board/cobra5272/MAINTAINERS b/board/cobra5272/MAINTAINERS new file mode 100644 index 0000000000..a064da2f15 --- /dev/null +++ b/board/cobra5272/MAINTAINERS @@ -0,0 +1,6 @@ +COBRA5272 BOARD +#M: - +S: Maintained +F: board/cobra5272/ +F: include/configs/cobra5272.h +F: configs/cobra5272_defconfig diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile index 871865b6ee..fbbbb877c7 100644 --- a/board/cobra5272/Makefile +++ b/board/cobra5272/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cobra5272.o flash.o diff --git a/board/cogent/Makefile b/board/cogent/Makefile deleted file mode 100644 index e7d69dffdc..0000000000 --- a/board/cogent/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cogent/README b/board/cogent/README deleted file mode 100644 index 4343f733ff..0000000000 --- a/board/cogent/README +++ /dev/null @@ -1,118 +0,0 @@ -Cogent Modular Architecture configuration ------------------------------------------ - -As the name suggests, the Cogent platform is a modular system where -you have a motherboard into which plugs a cpu module and one or more -i/o modules. This provides very nice flexibility, but makes the -configuration task somewhat harder. - -The possible Cogent motherboards are: - -Code Config Variable Description ----- --------------- ----------- - -CMA101 CONFIG_CMA101 32MB ram, 2 ser, 1 par, rtc, dipsw, - 2x16 lcd, eth(?) -CMA102 CONFIG_CMA102 32MB ram, 2 ser, 1 par, rtc, dipsw, - 2x16 lcd -CMA111 CONFIG_CMA111 32MB ram, 1MB flash, 4 ser, 1 par, - rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI, - 10/100TP eth -CMA120 CONFIG_CMA120 32MB ram, 1MB flash, 4 ser, 1 par, - rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI, - 10/100TP eth, 2xPCMCIA, video/lcd-panel -CMA150 CONFIG_CMA150 8MB ram, 1MB flash, 2 ser, 1 par, rtc, - ps/2 kbd/mse, 2x16 lcd - -The possible Cogent PowerPC CPU modules are: - -Code Config Variable Description ----- --------------- ----------- - -CMA278-603EV CONFIG_CMA278_603EV PPC603ev CPU, 66MHz clock, 512K EPROM, - JTAG/COP -CMA278-603ER CONFIG_CMA278_603ER PPC603er CPU, 66MHz clock, 512K EPROM, - JTAG/COP -CMA278-740 CONFIG_CMA278_740 PPC740 CPU, 66MHz clock, 512K EPROM, - JTAG/COP -CMA280-509 CONFIG_CMA280_509 MPC505/509 CPU, 50MHz clock, - 512K EPROM, BDM -CMA282 CONFIG_CMA282 MPC8260 CPU, 66MHz clock, 512K EPROM, - JTAG, 16M RAM, 1 x ser (SMC2), - 1 x 10baseT PHY (SCC4), 1 x 10/100 TP - PHY (FCC1), 2 x 48pin DIN (FCC2 + TDM1) -CMA285 CONFIG_CMA285 MPC801 CPU, 33MHz clock, 512K EPROM, - BDM -CMA286-21 CONFIG_CMA286_21 MPC821 CPU, 66MHz clock, 512K EPROM, - BDM, 16M RAM, 2 x ser (SMC1 + SMC2), - 1 x 10baseT PHY (SCC2) -CMA286-60-OLD CONFIG_CMA286_60_OLD MPC860 CPU, 33MHz clock, 128K EPROM, - BDM -CMA286-60 CONFIG_CMA286_60 MPC860 CPU, 66MHz clock, 512K EPROM, - BDM, 16M RAM, 2 x ser (SMC1 + SMC2), - 1 x 10baseT PHY (SCC2) -CMA286-60P CONFIG_CMA286_60P MPC860P CPU, 66MHz clock, 512K EPROM, - BDM, 16M RAM, 2 x ser (SMC1 + SMC2), - 1 x 10baseT PHY (SCC2) -CMA287-23 CONFIG_CMA287_23 MPC823 CPU, 33MHz clock, 512K EPROM, - BDM -CMA287-50 CONFIG_CMA287_50 MPC850 CPU, 33MHz clock, 512K EPROM, - BDM - -(there are a lot of other cpu modules with ARM, MIPS and M-CORE CPUs, -but we'll worry about those later). - -The possible Cogent CMA I/O Modules are: - -Code Config Variable Description ----- --------------- ----------- - -CMA302 CONFIG_CMA302 up to 16M flash, ps/2 keyboard/mouse -CMA352 CONFIG_CMA352 CMAbus <=> PCI - -Currently supported: - - Motherboards: CMA102 - CPU Modules: CMA286-60-OLD - I/O Modules: CMA302 I/O module - -To configure, perform the usual U-Boot configuration task of editing -"include/config_cogent_mpc8xx.h" and reviewing all the options and -settings in there. In particular, check the chip select values -installed into the memory controller's various option and base -registers - these are set by the defines CONFIG_SYS_CMA_CSn_{BASE,SIZE} and -CONFIG_SYS_{B,O}Rn_PRELIM. Also be careful of the clock settings installed -into the SCCR - via the define CONFIG_SYS_SCCR. Finally, decide whether you -want the serial console on motherboard serial port A or on one of the -8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly -(NONE means use Cogent motherboard serial port A). - -Then edit the file "cogent/config.mk". Firstly, set CONFIG_SYS_TEXT_BASE to be -the base address of the EPROM for the CPU module. This should be the -same as the value selected for CONFIG_SYS_MONITOR_BASE in -"include/config_cogent_*.h" (in fact, I have made this automatic via -the -CONFIG_SYS_TEXT_BASE=... option in CPPFLAGS). - -Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS). - -$(CMA_MB) is the name of the directory that contains support for your -motherboard. At this stage, only "cma10x" exists, which supports the -CMA101 and CMA102 motherboards - but only selected devices, namely -serial, lcd and dipsw. - -$(CMA_IOMS) is a list of zero or more directories that contain -support for the i/o modules you have installed. At this stage, only -"cma302" exists, which supports the CMA302 flash i/o module - but -only the flash part, not the ps/2 keyboard and mouse interfaces. - -There should be a make variable for each of the above directories, -which is the directory name with "_O" appended. This make variable is -a list of object files to compile from that directory and include in -the library. - - e.g. cma10x_O = serial.o ... - -That's it. Good Luck. - -Murray.Jensen@cmst.csiro.au -August 31, 2000. diff --git a/board/cogent/README.cma286 b/board/cogent/README.cma286 deleted file mode 100644 index 0345feae00..0000000000 --- a/board/cogent/README.cma286 +++ /dev/null @@ -1,69 +0,0 @@ -CPU module revisions --------------------- - -My cpu module has the model number "CMA286-60-990526-01". My motherboard -has the model number "CMA102-32M-990526-01". These are both fairly old, -and may not reflect current design. In particular, I can see from the -Cogent web site that the CMA286 has been significantly redesigned - it -now has on board RAM (4M), ethernet 10baseT PHY (on SCC2), 2 serial ports -(SMC1 and SMC2), and 48pin DIN for the FEC (if present i.e. MPC860T), and -also the EPROM is 512K. - -My CMA286-60 has none of this, and only 128K EPROM. In addition, the CPU -clock is listed as 66MHz, whereas mine is 33.333MHz. - -Clocks ------- - -Quote from my "CMA286 MPC860/821 User's Manual": - -"When setting up the Periodic Interrupt Timer (PIT), be aware that the -CMA286 places the MPC860/821 in PLL X1 Mode. This means that we feed -a 25MHz clock directly into the MPC860/821. This mode sets the divisor -for the PIT to be 512. In addition, the Time Base Register (TMB) -divisor is set to 16." - -I interpreted this information to mean that EXTCLK is 25MHz and that at -power on reset, MODCK1=1 and MODCK2=0, which selects EXTCLK as the -source for OSCCLK and PITRTCLK, sets RTDIV to 512 and sets MF (the -multiplication factor) to 1 (I assume this is what they mean by X1 -mode above). MF=1 means the cpus internal clock runs at the same -rate as EXTCLK i.e. 25MHz. - -Furthermore, since SCCR[TBS] (the Time Base Source selector bit in the -System Clock and Reset Control register) is set in the cpu initialisation -code, the TMBCLK source is forced to be GCLK2 and the TMBCLK prescale is -forced to be 16. This results in TMBCLK=1562500. - -One problem - since PITRTCLK source is EXTCLK (25Mhz) and RTDIV is 512, -PITRTCLK will be 48828.125 (huh?). Another quote from the MPC860 Users -Manual: - -"When used by the real-time clock (RTC), the PITRTCLK source is first -divided as determined by RTDIV, and then divided in the RTC circuits by -either 8192 or 9600. Therefore, in order for the RTC to count in -seconds, the clock source must satisfy: - - (EXTCLK or OSCM) / [(4 or 512) x (8192 or 9600)] = 1 - -The RTC will operate with other frequencies, but it will not count in -units of seconds." - -Therefore, the internal RTC of the MPC860 is not going to count in -seconds, so we must use the motherboard RTC (if we need a RTC). - -I presume this means that they do not provide a fixed oscillator for -OSCM. The code in get_gclk_freq() assumes PITRTCLK source is OSCM, -RTDIV is 4, and that OSCM/4 is 8192 (i.e. a ~32KHz oscillator). Since -the CMA286-60 doesn't have this (at least mine doesn't) we can't use -the code in get_gclk_freq(). - -Finally, it appears that the internal clock in my CMA286-60 is actually -33.333MHz. Which makes TMBCLK=2083312.5 (another huh?) and -PITRTCLK=65103.515625 (bloody hell!). - -If anyone finds anything wrong with the stuff above, I would appreciate -an email about it. - -Murray Jensen -21-Aug-00 diff --git a/board/cogent/config.mk b/board/cogent/config.mk deleted file mode 100644 index 1452d46a9f..0000000000 --- a/board/cogent/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# Cogent Modular Architecture -# - -PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c deleted file mode 100644 index d2027c9758..0000000000 --- a/board/cogent/dipsw.c +++ /dev/null @@ -1,50 +0,0 @@ -#include -#include - -unsigned char -dipsw_raw(void) -{ - return cma_mb_reg_read(&((cma_mb_dipsw *)CMA_MB_DIPSW_BASE)->dip_val); -} - -unsigned char -dipsw_cooked(void) -{ - unsigned char val1, val2, mask1, mask2; - - val1 = dipsw_raw(); - - /* - * we want to mirror the bits because the low bit is switch 1 and high - * bit is switch 8 and also invert them because 1=off and 0=on, according - * to manual. - * - * this makes the value more intuitive i.e. - * - left most, or high, or top, bit is left most switch (1); - * - right most, or low, or bottom, bit is right most switch (8) - * - a set bit means "on" and a clear bit means "off" - */ - - val2 = 0; - for (mask1 = 1 << 7, mask2 = 1; mask1 > 0; mask1 >>= 1, mask2 <<= 1) - if ((val1 & mask1) == 0) - val2 |= mask2; - - return (val2); -} - -void -dipsw_init(void) -{ - unsigned char val, mask; - - val = dipsw_cooked(); - - printf("|"); - for (mask = 1 << 7; mask > 0; mask >>= 1) - if (val & mask) - printf("on |"); - else - printf("off|"); - printf("\n"); -} diff --git a/board/cogent/dipsw.h b/board/cogent/dipsw.h deleted file mode 100644 index 4f52fd4392..0000000000 --- a/board/cogent/dipsw.h +++ /dev/null @@ -1,3 +0,0 @@ -extern unsigned char dipsw_raw(void); -extern unsigned char dipsw_cooked(void); -extern void dipsw_init(void); diff --git a/board/cogent/flash.c b/board/cogent/flash.c deleted file mode 100644 index 207380f099..0000000000 --- a/board/cogent/flash.c +++ /dev/null @@ -1,633 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - - -#if defined(CONFIG_CMA302) - -/* - * probe for the existence of flash at address "addr" - * 0 = yes, 1 = bad Manufacturer's Id, 2 = bad Device Id - */ -static int -c302f_probe_word(c302f_addr_t addr) -{ - /* reset the flash */ - *addr = C302F_BNK_CMD_RST; - - /* check the manufacturer id */ - *addr = C302F_BNK_CMD_RD_ID; - if (*C302F_BNK_ADDR_MAN(addr) != C302F_BNK_RD_ID_MAN) - return 1; - - /* check the device id */ - *addr = C302F_BNK_CMD_RD_ID; - if (*C302F_BNK_ADDR_DEV(addr) != C302F_BNK_RD_ID_DEV) - return 2; - -#ifdef FLASH_DEBUG - { - int i; - - printf("\nMaster Lock Config = 0x%08lx\n", - *C302F_BNK_ADDR_CFGM(addr)); - for (i = 0; i < C302F_BNK_NBLOCKS; i++) - printf("Block %2d Lock Config = 0x%08lx\n", - i, *C302F_BNK_ADDR_CFG(i, addr)); - } -#endif - - /* reset the flash again */ - *addr = C302F_BNK_CMD_RST; - - return 0; -} - -/* - * probe for Cogent CMA302 flash module at address "base" and store - * info for any found into flash_info entry "fip". Must find at least - * one bank. - */ -static void -c302f_probe(flash_info_t *fip, c302f_addr_t base) -{ - c302f_addr_t addr, eaddr; - int nbanks; - - fip->size = 0L; - fip->sector_count = 0; - - addr = base; - eaddr = C302F_BNK_ADDR_BASE(addr, C302F_MAX_BANKS); - nbanks = 0; - - while (addr < eaddr) { - c302f_addr_t addrw, eaddrw, addrb; - int i, osc, nsc; - - addrw = addr; - eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw); - - while (addrw < eaddrw) - if (c302f_probe_word(addrw++) != 0) - goto out; - - /* bank exists - append info for this bank to *fip */ - fip->flash_id = FLASH_MAN_INTEL|FLASH_28F008S5; - fip->size += C302F_BNK_SIZE; - osc = fip->sector_count; - fip->sector_count += C302F_BNK_NBLOCKS; - if ((nsc = fip->sector_count) >= CONFIG_SYS_MAX_FLASH_SECT) - panic("Too many sectors in flash at address 0x%08lx\n", - (unsigned long)base); - - addrb = addr; - for (i = osc; i < nsc; i++) { - fip->start[i] = (ulong)addrb; - fip->protect[i] = 0; - addrb = C302F_BNK_ADDR_NEXT_BLK(addrb); - } - - addr = C302F_BNK_ADDR_NEXT_BNK(addr); - nbanks++; - } - -out: - if (nbanks == 0) - panic("ERROR: no flash found at address 0x%08lx\n", - (unsigned long)base); -} - -static void -c302f_reset(flash_info_t *info, int sect) -{ - c302f_addr_t addrw, eaddrw; - - addrw = (c302f_addr_t)info->start[sect]; - eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw); - - while (addrw < eaddrw) { -#ifdef FLASH_DEBUG - printf(" writing reset cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = C302F_BNK_CMD_RST; - addrw++; - } -} - -static void -c302f_erase_init(flash_info_t *info, int sect) -{ - c302f_addr_t addrw, saddrw, eaddrw; - int flag; - -#ifdef FLASH_DEBUG - printf("0x%08lx C302F_BNK_CMD_PROG\n", C302F_BNK_CMD_PROG); - printf("0x%08lx C302F_BNK_CMD_ERASE1\n", C302F_BNK_CMD_ERASE1); - printf("0x%08lx C302F_BNK_CMD_ERASE2\n", C302F_BNK_CMD_ERASE2); - printf("0x%08lx C302F_BNK_CMD_CLR_STAT\n", C302F_BNK_CMD_CLR_STAT); - printf("0x%08lx C302F_BNK_CMD_RST\n", C302F_BNK_CMD_RST); - printf("0x%08lx C302F_BNK_STAT_RDY\n", C302F_BNK_STAT_RDY); - printf("0x%08lx C302F_BNK_STAT_ERR\n", C302F_BNK_STAT_ERR); -#endif - - saddrw = (c302f_addr_t)info->start[sect]; - eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw); - -#ifdef FLASH_DEBUG - printf("erasing sector %d, start addr = 0x%08lx " - "(bank next word addr = 0x%08lx)\n", sect, - (unsigned long)saddrw, (unsigned long)eaddrw); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts(); - - for (addrw = saddrw; addrw < eaddrw; addrw++) { -#ifdef FLASH_DEBUG - printf(" writing erase cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = C302F_BNK_CMD_ERASE1; - *addrw = C302F_BNK_CMD_ERASE2; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); -} - -static int -c302f_erase_poll(flash_info_t *info, int sect) -{ - c302f_addr_t addrw, saddrw, eaddrw; - int sectdone, haderr; - - saddrw = (c302f_addr_t)info->start[sect]; - eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw); - - sectdone = 1; - haderr = 0; - - for (addrw = saddrw; addrw < eaddrw; addrw++) { - c302f_word_t stat = *addrw; - -#ifdef FLASH_DEBUG - printf(" checking status at addr " - "0x%08lx [0x%08lx]\n", - (unsigned long)addrw, stat); -#endif - if ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY) - sectdone = 0; - else if ((stat & C302F_BNK_STAT_ERR) != 0) { - printf(" failed on sector %d " - "(stat = 0x%08lx) at " - "address 0x%08lx\n", - sect, stat, - (unsigned long)addrw); - *addrw = C302F_BNK_CMD_CLR_STAT; - haderr = 1; - } - } - - if (haderr) - return (-1); - else - return (sectdone); -} - -static int -c302f_write_word(c302f_addr_t addr, c302f_word_t value) -{ - c302f_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = C302F_BNK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY); - - if ((stat & C302F_BNK_STAT_ERR) != 0) { - printf("flash program failed (stat = 0x%08lx) " - "at address 0x%08lx\n", (ulong)stat, (ulong)addr); - *addr = C302F_BNK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = C302F_BNK_CMD_RST; - - return (retval); -} - -#endif /* CONFIG_CMA302 */ - -unsigned long -flash_init(void) -{ - unsigned long total; - int i; - __maybe_unused flash_info_t *fip; - - /* Init: no FLASHes known */ - for (i=0; isize; - fip++; -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) - /* not yet ... - cmbf_probe(fip, (cmbf_addr_t)CMA_MB_FLASH_BASE); - total += fip->size; - fip++; - */ -#endif - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return total; -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F008S5: printf ("28F008S5\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 4) == 0) - printf ("\n "); - printf (" %2d - %08lX%s", i, - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - void (*erase_init)(flash_info_t *, int); - int (*erase_poll)(flash_info_t *, int); - void (*reset)(flash_info_t *, int); - int rcode = 0; - -#ifdef FLASH_DEBUG - printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info(info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id) { - -#if defined(CONFIG_CMA302) - case FLASH_MAN_INTEL|FLASH_28F008S5: - erase_init = c302f_erase_init; - erase_poll = c302f_erase_poll; - reset = c302f_reset; - break; -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) - case FLASH_MAN_INTEL|FLASH_28F800_B: - case FLASH_MAN_AMD|FLASH_AM29F800B: - /* not yet ... - erase_init = cmbf_erase_init; - erase_poll = cmbf_erase_poll; - reset = cmbf_reset; - break; - */ -#endif - - default: - printf ("Flash type %08lx not supported - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sector%s will not be erased!\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - (*erase_init)(info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer(start); - - do { - now = get_timer(start); - - if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = (*erase_poll)(info, sect); - - if (sectdone < 0) { - haderr = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) { - printf (" failed\n"); - rcode = 1; - } - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - (*reset)(info, sect); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - write error - */ - -int -write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - ulong start, now, last; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - start = get_timer (0); - last = 0; - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - - /* show that we're waiting */ - now = get_timer(start); - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - write error - */ -static int -write_word(flash_info_t *info, ulong dest, ulong data) -{ - int retval; - - /* Check if Flash is (sufficiently) erased */ - if ((*(ulong *)dest & data) != data) { - return (2); - } - - switch (info->flash_id) { - -#if defined(CONFIG_CMA302) - case FLASH_MAN_INTEL|FLASH_28F008S5: - retval = c302f_write_word((c302f_addr_t)dest, (c302f_word_t)data); - break; -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) - case FLASH_MAN_INTEL|FLASH_28F800_B: - case FLASH_MAN_AMD|FLASH_AM29F800B: - /* not yet ... - retval = cmbf_write_word((cmbf_addr_t)dest, (cmbf_word_t)data); - */ - retval = 3; - break; -#endif - - default: - printf ("Flash type %08lx not supported - aborted\n", - info->flash_id); - retval = 3; - break; - } - - return (retval); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cogent/flash.h b/board/cogent/flash.h deleted file mode 100644 index 0b8d6aaef6..0000000000 --- a/board/cogent/flash.h +++ /dev/null @@ -1,305 +0,0 @@ -/**************** DEFINES for Intel 28F008S5 FLASH chip **********************/ - -/* register addresses, valid only following a I8S5_CMD_RD_ID command */ -#define I8S5_ADDR_MAN 0x00000 /* manufacturer's id */ -#define I8S5_ADDR_DEV 0x00001 /* device id */ -#define I8S5_ADDR_CFGM 0x00003 /* master lock configuration */ -#define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */ - -/* Commands */ -#define I8S5_CMD_RST 0xFF /* reset flash */ -#define I8S5_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define I8S5_CMD_RD_STAT 0x70 /* read the status register */ -#define I8S5_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define I8S5_CMD_ERASE1 0x20 /* first word for block erase */ -#define I8S5_CMD_ERASE2 0xD0 /* second word for block erase */ -#define I8S5_CMD_PROG 0x40 /* program word command */ -#define I8S5_CMD_LOCK 0x60 /* first word for all lock commands */ -#define I8S5_CMD_SET_LOCK_BLK 0x01 /* 2nd word for set block lock bit */ -#define I8S5_CMD_SET_LOCK_MSTR 0xF1 /* 2nd word for set master lock bit */ -#define I8S5_CMD_CLR_LOCK_BLK 0xD0 /* 2nd word for clear block lock bit */ - -/* status register bits */ -#define I8S5_STAT_DPS 0x02 /* Device Protect Status */ -#define I8S5_STAT_PSS 0x04 /* Program Suspend Status */ -#define I8S5_STAT_VPPS 0x08 /* VPP Status */ -#define I8S5_STAT_PSLBS 0x10 /* Program and Set Lock Bit Status */ -#define I8S5_STAT_ECLBS 0x20 /* Erase and Clear Lock Bit Status */ -#define I8S5_STAT_ESS 0x40 /* Erase Suspend Status */ -#define I8S5_STAT_RDY 0x80 /* Write State Machine Status, 1=rdy */ - -#define I8S5_STAT_ERR (I8S5_STAT_VPPS | I8S5_STAT_DPS | \ - I8S5_STAT_ECLBS | I8S5_STAT_PSLBS) - -/* ID and Lock Configuration */ -#define I8S5_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ -#define I8S5_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define I8S5_RD_ID_DEV 0xA6 /* Device code = 0xA6, 28F008S5 */ - -/* dimensions */ -#define I8S5_NBLOCKS 16 /* a 28F008S5 consists of 16 blocks */ -#define I8S5_BLKSZ (64*1024) /* of 64Kbyte each */ -#define I8S5_SIZE (I8S5_BLKSZ * I8S5_NBLOCKS) - -/**************** DEFINES for Intel 28F800B5 FLASH chip **********************/ - -/* register addresses, valid only following a I8S5_CMD_RD_ID command */ -#define I8B5_ADDR_MAN 0x00000 /* manufacturer's id */ -#define I8B5_ADDR_DEV 0x00001 /* device id */ - -/* Commands */ -#define I8B5_CMD_RST 0xFF /* reset flash */ -#define I8B5_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define I8B5_CMD_RD_STAT 0x70 /* read the status register */ -#define I8B5_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define I8B5_CMD_ERASE1 0x20 /* first word for block erase */ -#define I8B5_CMD_ERASE2 0xD0 /* second word for block erase */ -#define I8B5_CMD_PROG 0x40 /* program word command */ - -/* status register bits */ -#define I8B5_STAT_VPPS 0x08 /* VPP Status */ -#define I8B5_STAT_DWS 0x10 /* Program and Set Lock Bit Status */ -#define I8B5_STAT_ES 0x20 /* Erase and Clear Lock Bit Status */ -#define I8B5_STAT_ESS 0x40 /* Erase Suspend Status */ -#define I8B5_STAT_RDY 0x80 /* Write State Machine Status, 1=rdy */ - -#define I8B5_STAT_ERR (I8B5_STAT_VPPS | I8B5_STAT_DWS | I8B5_STAT_ES) - -/* ID Configuration */ -#define I8B5_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define I8B5_RD_ID_DEV1 0x889D /* Device code = 0x889D, 28F800B5 */ - -/* dimensions */ -#define I8B5_NBLOCKS 8 /* a 28F008S5 consists of 16 blocks */ -#define I8B5_BLKSZ (128*1024) /* of 64Kbyte each */ -#define I8B5_SIZE (I8B5_BLKSZ * I8B5_NBLOCKS) - -/****************** DEFINES for Cogent CMA302 Flash **************************/ - -/* - * Quoted from the CMA302 manual: - * - * Although the CMA302 supports 64-bit reads, all writes must be done with - * word size only. When programming the CMA302, the FLASH devices appear as 2 - * banks of interleaved, 32-bit wide FLASH. Each 32-bit word consists of four - * 28F008S5 devices. The first bank is accessed when the word address is even, - * while the second bank is accessed when the word address is odd. This must - * be taken into account when programming the desired word. Also, when locking - * blocks, software must lock both banks. The CMA302 does not directly support - * byte writing. Programming and/or erasing individual bytes is done with - * selective use of the Write Command. By not placing the Write Command value - * on a particular byte lane, that byte will not be written with the following - * Write Data. Also, remember that within a byte lane (i.e. D0-7), there are - * two 28F008S5 devices, one for each bank or every other word. - * - * End quote. - * - * Each 28F008S5 is 8Mbit, with 8 bit wide data. i.e. each is 1Mbyte. The - * chips are arranged on the CMA302 in multiples of two banks, each bank having - * 4 chips. Each bank must be accessed as a single 32 bit wide device (i.e. - * aligned on a 32 bit boundary), with each byte lane within the 32 bits (0-3) - * going to each of the 4 chips and the word address selecting the bank, even - * being the low bank and odd the high bank. For 64bit reads, both banks are - * read simultaneously with the second bank on byte lanes 4-7. Each 28F008S5 - * consists of 16 64Kbyte "block"s. Before programming a byte, the block that - * the byte resides within must be erased. So if you want to program contiguous - * memory locations, you must erase all 8 chips at the same time. i.e. the - * flash on the CMA302 can be viewed as a number of 512Kbyte blocks. - * - * Note: I am going to treat banks as 8 Mbytes (1Meg of 64bit words), whereas - * the example code treats them as a pair of interleaved 1 Mbyte x 32bit banks. - */ - -typedef unsigned long c302f_word_t; /* 32 or 64 bit unsigned integer */ -typedef volatile c302f_word_t *c302f_addr_t; -typedef unsigned long c302f_size_t; /* want this big - at least 32 bit */ - -/* layout of banks on cma302 board */ -#define C302F_BNK_WIDTH 8 /* each bank is 8 chips wide */ -#define C302F_BNK_WSHIFT 3 /* log base 2 of C302F_BNK_WIDTH */ -#define C302F_BNK_NBLOCKS I8S5_NBLOCKS -#define C302F_BNK_BLKSZ (I8S5_BLKSZ * C302F_BNK_WIDTH) -#define C302F_BNK_SIZE (I8S5_SIZE * C302F_BNK_WIDTH) - -#define C302F_MAX_BANKS 2 /* up to 2 banks (8M each) on CMA302 */ - -/* align addresses and sizes to bank boundaries */ -#define C302F_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ - & ~(C302F_BNK_WIDTH - 1))) -#define C302F_BNK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BNK_ADDR_ALIGN( \ - (c302f_size_t)(s) + (C302F_BNK_WIDTH - 1))) - -/* align addresses and sizes to block boundaries */ -#define C302F_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ - & ~(C302F_BNK_BLKSZ - 1))) -#define C302F_BLK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BLK_ADDR_ALIGN( \ - (c302f_size_t)(s) + (C302F_BNK_BLKSZ - 1))) - -/* add a byte offset to a flash address */ -#define C302F_ADDR_ADD_BYTEOFF(a,o) \ - (c302f_addr_t)((c302f_size_t)(a) + (o)) - -/* get base address of bank b, given flash base address a */ -#define C302F_BNK_ADDR_BASE(a,b) \ - C302F_ADDR_ADD_BYTEOFF((a), \ - (c302f_size_t)(b) * C302F_BNK_SIZE) - -/* adjust an address a (within a bank) to next word, block or bank */ -#define C302F_BNK_ADDR_NEXT_WORD(a) \ - C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_WIDTH) -#define C302F_BNK_ADDR_NEXT_BLK(a) \ - C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_BLKSZ) -#define C302F_BNK_ADDR_NEXT_BNK(a) \ - C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define C302F_BNK_ADDR_I8S5REG(a,r) \ - C302F_ADDR_ADD_BYTEOFF((a), \ - (r) << C302F_BNK_WSHIFT) - -/* make a bank representation for each chip address */ - -#define C302F_BNK_ADDR_MAN(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN) -#define C302F_BNK_ADDR_DEV(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV) -#define C302F_BNK_ADDR_CFGM(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM) -#define C302F_BNK_ADDR_CFG(b,a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the c302f_word_t type - */ -#define C302F_FILL_WORD(o) (((unsigned long)(o) << 24) | \ - ((unsigned long)(o) << 16) | \ - ((unsigned long)(o) << 8) | \ - (unsigned long)(o)) - -/* make a bank representation for each chip cmd/stat/rd value */ - -/* Commands */ -#define C302F_BNK_CMD_RST C302F_FILL_WORD(I8S5_CMD_RST) -#define C302F_BNK_CMD_RD_ID C302F_FILL_WORD(I8S5_CMD_RD_ID) -#define C302F_BNK_CMD_RD_STAT C302F_FILL_WORD(I8S5_CMD_RD_STAT) -#define C302F_BNK_CMD_CLR_STAT C302F_FILL_WORD(I8S5_CMD_CLR_STAT) -#define C302F_BNK_CMD_ERASE1 C302F_FILL_WORD(I8S5_CMD_ERASE1) -#define C302F_BNK_CMD_ERASE2 C302F_FILL_WORD(I8S5_CMD_ERASE2) -#define C302F_BNK_CMD_PROG C302F_FILL_WORD(I8S5_CMD_PROG) -#define C302F_BNK_CMD_LOCK C302F_FILL_WORD(I8S5_CMD_LOCK) -#define C302F_BNK_CMD_SET_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_SET_LOCK_BLK) -#define C302F_BNK_CMD_SET_LOCK_MSTR C302F_FILL_WORD(I8S5_CMD_SET_LOCK_MSTR) -#define C302F_BNK_CMD_CLR_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define C302F_BNK_STAT_DPS C302F_FILL_WORD(I8S5_STAT_DPS) -#define C302F_BNK_STAT_PSS C302F_FILL_WORD(I8S5_STAT_PSS) -#define C302F_BNK_STAT_VPPS C302F_FILL_WORD(I8S5_STAT_VPPS) -#define C302F_BNK_STAT_PSLBS C302F_FILL_WORD(I8S5_STAT_PSLBS) -#define C302F_BNK_STAT_ECLBS C302F_FILL_WORD(I8S5_STAT_ECLBS) -#define C302F_BNK_STAT_ESS C302F_FILL_WORD(I8S5_STAT_ESS) -#define C302F_BNK_STAT_RDY C302F_FILL_WORD(I8S5_STAT_RDY) - -#define C302F_BNK_STAT_ERR C302F_FILL_WORD(I8S5_STAT_ERR) - -/* ID and Lock Configuration */ -#define C302F_BNK_RD_ID_LOCK C302F_FILL_WORD(I8S5_RD_ID_LOCK) -#define C302F_BNK_RD_ID_MAN C302F_FILL_WORD(I8S5_RD_ID_MAN) -#define C302F_BNK_RD_ID_DEV C302F_FILL_WORD(I8S5_RD_ID_DEV) - -/*************** DEFINES for Cogent Motherboard Flash ************************/ - -typedef unsigned short cmbf_word_t; /* 16 bit unsigned integer */ -typedef volatile cmbf_word_t *cmbf_addr_t; -typedef unsigned long cmbf_size_t; /* want this big - at least 32 bit */ - -/* layout of banks on cogent motherboard - only 1 bank, 16 bit wide */ -#define CMBF_BNK_WIDTH 1 /* each bank is one chip wide */ -#define CMBF_BNK_WSHIFT 0 /* log base 2 of CMBF_BNK_WIDTH */ -#define CMBF_BNK_NBLOCKS I8B5_NBLOCKS -#define CMBF_BNK_BLKSZ (I8B5_BLKSZ * CMBF_BNK_WIDTH) -#define CMBF_BNK_SIZE (I8B5_SIZE * CMBF_BNK_WIDTH) - -#define CMBF_MAX_BANKS 1 /* only 1 x 1Mbyte bank on cogent m/b */ - -/* align addresses and sizes to bank boundaries */ -#define CMBF_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ - & ~(CMBF_BNK_WIDTH - 1))) -#define CMBF_BNK_SIZE_ALIGN(s) ((c302f_size_t)CMBF_BNK_ADDR_ALIGN( \ - (c302f_size_t)(s) + (CMBF_BNK_WIDTH - 1))) - -/* align addresses and sizes to block boundaries */ -#define CMBF_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ - & ~(CMBF_BNK_BLKSZ - 1))) -#define CMBF_BLK_SIZE_ALIGN(s) ((c302f_size_t)CMBF_BLK_ADDR_ALIGN( \ - (c302f_size_t)(s) + (CMBF_BNK_BLKSZ - 1))) - -/* add a byte offset to a flash address */ -#define CMBF_ADDR_ADD_BYTEOFF(a,o) \ - (c302f_addr_t)((c302f_size_t)(a) + (o)) - -/* get base address of bank b, given flash base address a */ -#define CMBF_BNK_ADDR_BASE(a,b) \ - CMBF_ADDR_ADD_BYTEOFF((a), \ - (c302f_size_t)(b) * CMBF_BNK_SIZE) - -/* adjust an address a (within a bank) to next word, block or bank */ -#define CMBF_BNK_ADDR_NEXT_WORD(a) \ - CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_WIDTH) -#define CMBF_BNK_ADDR_NEXT_BLK(a) \ - CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_BLKSZ) -#define CMBF_BNK_ADDR_NEXT_BNK(a) \ - CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define CMBF_BNK_ADDR_I8B5REG(a,r) \ - CMBF_ADDR_ADD_BYTEOFF((a), \ - (r) << CMBF_BNK_WSHIFT) - -/* make a bank representation for each chip address */ - -#define CMBF_BNK_ADDR_MAN(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN) -#define CMBF_BNK_ADDR_DEV(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV) -#define CMBF_BNK_ADDR_CFGM(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM) -#define CMBF_BNK_ADDR_CFG(b,a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the c302f_word_t type - */ -#define CMBF_FILL_WORD(o) (((unsigned long)(o) << 24) | \ - ((unsigned long)(o) << 16) | \ - ((unsigned long)(o) << 8) | \ - (unsigned long)(o)) - -/* make a bank representation for each chip cmd/stat/rd value */ - -/* Commands */ -#define CMBF_BNK_CMD_RST CMBF_FILL_WORD(I8B5_CMD_RST) -#define CMBF_BNK_CMD_RD_ID CMBF_FILL_WORD(I8B5_CMD_RD_ID) -#define CMBF_BNK_CMD_RD_STAT CMBF_FILL_WORD(I8B5_CMD_RD_STAT) -#define CMBF_BNK_CMD_CLR_STAT CMBF_FILL_WORD(I8B5_CMD_CLR_STAT) -#define CMBF_BNK_CMD_ERASE1 CMBF_FILL_WORD(I8B5_CMD_ERASE1) -#define CMBF_BNK_CMD_ERASE2 CMBF_FILL_WORD(I8B5_CMD_ERASE2) -#define CMBF_BNK_CMD_PROG CMBF_FILL_WORD(I8B5_CMD_PROG) -#define CMBF_BNK_CMD_LOCK CMBF_FILL_WORD(I8B5_CMD_LOCK) -#define CMBF_BNK_CMD_SET_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_BLK) -#define CMBF_BNK_CMD_SET_LOCK_MSTR CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_MSTR) -#define CMBF_BNK_CMD_CLR_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define CMBF_BNK_STAT_DPS CMBF_FILL_WORD(I8B5_STAT_DPS) -#define CMBF_BNK_STAT_PSS CMBF_FILL_WORD(I8B5_STAT_PSS) -#define CMBF_BNK_STAT_VPPS CMBF_FILL_WORD(I8B5_STAT_VPPS) -#define CMBF_BNK_STAT_PSLBS CMBF_FILL_WORD(I8B5_STAT_PSLBS) -#define CMBF_BNK_STAT_ECLBS CMBF_FILL_WORD(I8B5_STAT_ECLBS) -#define CMBF_BNK_STAT_ESS CMBF_FILL_WORD(I8B5_STAT_ESS) -#define CMBF_BNK_STAT_RDY CMBF_FILL_WORD(I8B5_STAT_RDY) - -#define CMBF_BNK_STAT_ERR CMBF_FILL_WORD(I8B5_STAT_ERR) - -/* ID and Lock Configuration */ -#define CMBF_BNK_RD_ID_LOCK CMBF_FILL_WORD(I8B5_RD_ID_LOCK) -#define CMBF_BNK_RD_ID_MAN CMBF_FILL_WORD(I8B5_RD_ID_MAN) -#define CMBF_BNK_RD_ID_DEV CMBF_FILL_WORD(I8B5_RD_ID_DEV) diff --git a/board/cogent/kbm.c b/board/cogent/kbm.c deleted file mode 100644 index 84964025ac..0000000000 --- a/board/cogent/kbm.c +++ /dev/null @@ -1,3 +0,0 @@ -/* keyboard/mouse not implemented yet */ - -int cma_kbm_not_implemented = 1; diff --git a/board/cogent/kbm.h b/board/cogent/kbm.h deleted file mode 100644 index 7eb419c1d6..0000000000 --- a/board/cogent/kbm.h +++ /dev/null @@ -1,79 +0,0 @@ -/* keyboard/mouse not implemented yet */ - -extern int cma_kbm_not_implemented; - -/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/ - -/* - * note the auxillary port is used to control the mouse - */ - -/* 8542B Commands (Sent to the Command Port) */ -#define HT8542_CMD_SET_BYTE 0x60 /* Set the command byte */ -#define HT8542_CMD_GET_BYTE 0x20 /* Get the command byte */ -#define HT8542_CMD_KBD_OBUFF 0xD2 /* Write to HT8542 Kbd Output Buffer */ -#define HT8542_CMD_AUX_OBUFF 0xD3 /* Write to HT8542 Mse Output Buffer */ -#define HT8542_CMD_AUX_WRITE 0xD4 /* Write to Mouse Port */ -#define HT8542_CMD_AUX_OFF 0xA7 /* Disable Mouse Port */ -#define HT8542_CMD_AUX_ON 0xA8 /* Re-Enable Mouse Port */ -#define HT8542_CMD_AUX_TEST 0xA9 /* Test for the presence of a Mouse */ -#define HT8542_CMD_DIAG 0xAA /* Start Diagnostics */ -#define HT8542_CMD_KBD_TEST 0xAB /* Test for presence of a keyboard */ -#define HT8542_CMD_KBD_OFF 0xAD /* Disable Kbd Port (use KBD_DAT_ON) */ -#define HT8542_CMD_KBD_ON 0xAE /* Enable Kbd Port (use KBD_DAT_OFF) */ - -/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */ -#define HT8542_CMD_BYTE_TRANS 0x40 -#define HT8542_CMD_BYTE_AUX_OFF 0x20 /* 1 = mse port disabled, 0 = enabled */ -#define HT8542_CMD_BYTE_KBD_OFF 0x10 /* 1 = kbd port disabled, 0 = enabled */ -#define HT8542_CMD_BYTE_OVER 0x08 /* 1 = override keyboard lock */ -#define HT8542_CMD_BYTE_RES 0x04 /* reserved */ -#define HT8542_CMD_BYTE_AUX_INT 0x02 /* 1 = enable mouse interrupt */ -#define HT8542_CMD_BYTE_KBD_INT 0x01 /* 1 = enable keyboard interrupt */ - -/* Keyboard Commands (Sent to the Data Port) */ -#define KBD_CMD_LED 0xED /* Set Keyboard LEDS with next byte */ -#define KBD_CMD_ECHO 0xEE /* Echo - we get 0xFA, 0xEE back */ -#define KBD_CMD_MODE 0xF0 /* set scan code mode with next byte */ -#define KBD_CMD_ID 0xF2 /* get keyboard/mouse ID */ -#define KBD_CMD_RPT 0xF3 /* Set Repeat Rate and Delay 2nd Byte */ -#define KBD_CMD_ON 0xF4 /* Enable keyboard */ -#define KBD_CMD_OFF 0xF5 /* Disables Scanning, Resets to Def */ -#define KBD_CMD_DEF 0xF6 /* Reverts kbd to default settings */ -#define KBD_CMD_RST 0xFF /* Reset - should get 0xFA, 0xAA back */ - -/* Set LED second bit defines */ -#define KBD_CMD_LED_SCROLL 0x01 /* Set SCROLL LOCK LED on */ -#define KBD_CMD_LED_NUM 0x02 /* Set NUM LOCK LED on */ -#define KBD_CMD_LED_CAPS 0x04 /* Set CAPS LOCK LED on */ - -/* Set Mode second byte defines */ -#define KBD_CMD_MODE_STAT 0x00 /* get current scan code mode */ -#define KBD_CMD_MODE_SCAN1 0x01 /* set mode to scan code 1 */ -#define KBD_CMD_MODE_SCAN2 0x02 /* set mode to scan code 2 */ -#define KBD_CMD_MODE_SCAN3 0x03 /* set mode to scan code 3 */ - -/* Keyboard/Mouse ID Codes */ -#define KBD_CMD_ID_1ST 0xAB /* 1st byte is 0xAB, 2nd is actual ID */ -#define KBD_CMD_ID_KBD 0x83 /* Keyboard */ -#define KBD_CMD_ID_MOUSE 0x00 /* Mouse */ - -/* Keyboard Data Return Defines */ -#define KBD_STAT_OVER 0x00 /* Buffer Overrun */ -#define KBD_STAT_DIAG_OK 0x55 /* Internal Self Test OK */ -#define KBD_STAT_RST_OK 0xAA /* Reset Complete */ -#define KBD_STAT_ECHO 0xEE /* Echo Command Return */ -#define KBD_STAT_BRK 0xF0 /* Prefix for Break Key Code */ -#define KBD_STAT_ACK 0xFA /* Received after all commands */ -#define KBD_STAT_DIAG_FAIL 0xFD /* Internal Self Test Failed */ -#define KBD_STAT_RESEND 0xFE /* Resend Last Command */ - -/* HT8542B Status Register Bit Defines */ -#define HT8542_STAT_OBF 0x01 /* 1 = output buffer is full */ -#define HT8542_STAT_IBF 0x02 /* 1 = input buffer is full */ -#define HT8542_STAT_SYS 0x04 /* system flag - unused */ -#define HT8542_STAT_CMD 0x08 /* 1 = cmd in input buffer, 0 = data */ -#define HT8542_STAT_INH 0x10 /* 1 = Inhibit - unused */ -#define HT8542_STAT_TX 0x20 /* 1 = Transmit Timeout has occured */ -#define HT8542_STAT_RX 0x40 /* 1 = Receive Timeout has occured */ -#define HT8542_STAT_PERR 0x80 /* 1 = Parity Error from Keyboard */ diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c deleted file mode 100644 index 76f5ad103f..0000000000 --- a/board/cogent/lcd.c +++ /dev/null @@ -1,245 +0,0 @@ -/* most of this is taken from the file */ -/* hal/powerpc/cogent/current/src/hal_diag.c in the */ -/* Cygnus eCos source. Here is the copyright notice: */ -/* */ -/*============================================================================= */ -/* */ -/* hal_diag.c */ -/* */ -/* HAL diagnostic output code */ -/* */ -/*============================================================================= */ -/*####COPYRIGHTBEGIN#### */ -/* */ -/* ------------------------------------------- */ -/* The contents of this file are subject to the Cygnus eCos Public License */ -/* Version 1.0 (the "License"); you may not use this file except in */ -/* compliance with the License. You may obtain a copy of the License at */ -/* http://sourceware.cygnus.com/ecos */ -/* */ -/* Software distributed under the License is distributed on an "AS IS" */ -/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */ -/* License for the specific language governing rights and limitations under */ -/* the License. */ -/* */ -/* The Original Code is eCos - Embedded Cygnus Operating System, released */ -/* September 30, 1998. */ -/* */ -/* The Initial Developer of the Original Code is Cygnus. Portions created */ -/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */ -/* ------------------------------------------- */ -/* */ -/*####COPYRIGHTEND#### */ -/*============================================================================= */ -/*#####DESCRIPTIONBEGIN#### */ -/* */ -/* Author(s): nickg, jskov */ -/* Contributors: nickg, jskov */ -/* Date: 1999-03-23 */ -/* Purpose: HAL diagnostic output */ -/* Description: Implementations of HAL diagnostic output support. */ -/* */ -/*####DESCRIPTIONEND#### */ -/* */ -/*============================================================================= */ - -/*----------------------------------------------------------------------------- */ -/* Cogent board specific LCD code */ - -#include -#include -#include - -static char lines[2][LCD_LINE_LENGTH+1]; -static int curline; -static int linepos; -static int heartbeat_active; -/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */ -/* pad to the right with spaces if necessary */ -static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent "; -static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000"; - -static inline unsigned char -lcd_read_status(cma_mb_lcd *clp) -{ - /* read the Busy Status Register */ - return (cma_mb_reg_read(&clp->lcd_bsr)); -} - -static inline void -lcd_wait_not_busy(cma_mb_lcd *clp) -{ - /* - * wait for not busy - * Note: It seems that the LCD isn't quite ready to process commands - * when it clears the BUSY flag. Reading the status address an extra - * time seems to give it enough breathing room. - */ - - while (lcd_read_status(clp) & LCD_STAT_BUSY) - ; - - (void)lcd_read_status(clp); -} - -static inline void -lcd_write_command(cma_mb_lcd *clp, unsigned char cmd) -{ - lcd_wait_not_busy(clp); - - /* write the Command Register */ - cma_mb_reg_write(&clp->lcd_cmd, cmd); -} - -static inline void -lcd_write_data(cma_mb_lcd *clp, unsigned char data) -{ - lcd_wait_not_busy(clp); - - /* write the Current Character Register */ - cma_mb_reg_write(&clp->lcd_ccr, data); -} - -static inline void -lcd_dis(int addr, char *string) -{ - cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; - int pos, linelen; - - linelen = LCD_LINE_LENGTH; - if (heartbeat_active && addr == LCD_LINE0) - linelen--; - - lcd_write_command(clp, LCD_CMD_ADD + addr); - for (pos = 0; *string != '\0' && pos < linelen; pos++) - lcd_write_data(clp, *string++); -} - -void -lcd_init(void) -{ - cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; - int i; - - /* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */ - lcd_write_command(clp, LCD_CMD_MODE); - - /* turn the LCD display on */ - lcd_write_command(clp, LCD_CMD_DON); - - curline = 0; - linepos = 0; - - for (i = 0; i < LCD_LINE_LENGTH; i++) { - lines[0][i] = init_line0[i]; - lines[1][i] = init_line1[i]; - } - - lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0; - - lcd_dis(LCD_LINE0, lines[0]); - lcd_dis(LCD_LINE1, lines[1]); - - printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH); -} - -void -lcd_write_char(const char c) -{ - int i, linelen; - - /* ignore CR */ - if (c == '\r') - return; - - linelen = LCD_LINE_LENGTH; - if (heartbeat_active && curline == 0) - linelen--; - - if (c == '\n') { - lcd_dis(LCD_LINE0, &lines[curline^1][0]); - lcd_dis(LCD_LINE1, &lines[curline][0]); - - /* Do a line feed */ - curline ^= 1; - linelen = LCD_LINE_LENGTH; - if (heartbeat_active && curline == 0) - linelen--; - linepos = 0; - - for (i = 0; i < linelen; i++) - lines[curline][i] = ' '; - - return; - } - - /* Only allow to be output if there is room on the LCD line */ - if (linepos < linelen) - lines[curline][linepos++] = c; -} - -void -lcd_flush(void) -{ - lcd_dis(LCD_LINE1, &lines[curline][0]); -} - -void -lcd_write_string(const char *s) -{ - char *p; - - for (p = (char *)s; *p != '\0'; p++) - lcd_write_char(*p); -} - -void -lcd_printf(const char *fmt, ...) -{ - va_list args; - char buf[CONFIG_SYS_PBSIZE]; - - va_start(args, fmt); - (void)vsprintf(buf, fmt, args); - va_end(args); - - lcd_write_string(buf); -} - -void -lcd_heartbeat(void) -{ - cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; -#if 0 - static char rotchars[] = { '|', '/', '-', '\\' }; -#else - /* HD44780 Rom Code A00 has no backslash */ - static char rotchars[] = { '|', '/', '-', '\315' }; -#endif - static int rotator_index = 0; - - heartbeat_active = 1; - - /* write the address */ - lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1)); - - /* write the next char in the sequence */ - lcd_write_data(clp, rotchars[rotator_index]); - - if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0])) - rotator_index = 0; -} - -#ifdef CONFIG_SHOW_ACTIVITY -void board_show_activity (ulong timestamp) -{ -#ifdef CONFIG_STATUS_LED - if ((timestamp % (CONFIG_SYS_HZ / 2) == 0) - lcd_heartbeat (); -#endif -} - -void show_activity(int arg) -{ -} -#endif diff --git a/board/cogent/lcd.h b/board/cogent/lcd.h deleted file mode 100644 index 9e6157ee66..0000000000 --- a/board/cogent/lcd.h +++ /dev/null @@ -1,84 +0,0 @@ -/* most of this is taken from the file */ -/* hal/powerpc/cogent/current/src/hal_diag.c in the */ -/* Cygnus eCos source. Here is the copyright notice: */ -/* */ -/*============================================================================= */ -/* */ -/* hal_diag.c */ -/* */ -/* HAL diagnostic output code */ -/* */ -/*============================================================================= */ -/*####COPYRIGHTBEGIN#### */ -/* */ -/* ------------------------------------------- */ -/* The contents of this file are subject to the Cygnus eCos Public License */ -/* Version 1.0 (the "License"); you may not use this file except in */ -/* compliance with the License. You may obtain a copy of the License at */ -/* http://sourceware.cygnus.com/ecos */ -/* */ -/* Software distributed under the License is distributed on an "AS IS" */ -/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */ -/* License for the specific language governing rights and limitations under */ -/* the License. */ -/* */ -/* The Original Code is eCos - Embedded Cygnus Operating System, released */ -/* September 30, 1998. */ -/* */ -/* The Initial Developer of the Original Code is Cygnus. Portions created */ -/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */ -/* ------------------------------------------- */ -/* */ -/*####COPYRIGHTEND#### */ -/*============================================================================= */ -/*#####DESCRIPTIONBEGIN#### */ -/* */ -/* Author(s): nickg, jskov */ -/* Contributors: nickg, jskov */ -/* Date: 1999-03-23 */ -/* Purpose: HAL diagnostic output */ -/* Description: Implementations of HAL diagnostic output support. */ -/* */ -/*####DESCRIPTIONEND#### */ -/* */ -/*============================================================================= */ - -/* FEMA 162B 16 character x 2 line LCD */ - -/* status register bit definitions */ -#define LCD_STAT_BUSY 0x80 /* 1 = display busy */ -#define LCD_STAT_ADD 0x7F /* bits 0-6 return current display address */ - -/* command register definitions */ -#define LCD_CMD_RST 0x01 /* clear entire display and reset display addr */ -#define LCD_CMD_HOME 0x02 /* reset display address and reset any shifting */ -#define LCD_CMD_ECL 0x04 /* move cursor left one pos on next data write */ -#define LCD_CMD_ESL 0x05 /* shift display left one pos on next data write */ -#define LCD_CMD_ECR 0x06 /* move cursor right one pos on next data write */ -#define LCD_CMD_ESR 0x07 /* shift disp right one pos on next data write */ -#define LCD_CMD_DOFF 0x08 /* display off, cursor off, blinking off */ -#define LCD_CMD_BL 0x09 /* blink character at current cursor position */ -#define LCD_CMD_CUR 0x0A /* enable cursor on */ -#define LCD_CMD_DON 0x0C /* turn display on */ -#define LCD_CMD_CL 0x10 /* move cursor left one position */ -#define LCD_CMD_SL 0x14 /* shift display left one position */ -#define LCD_CMD_CR 0x18 /* move cursor right one position */ -#define LCD_CMD_SR 0x1C /* shift display right one position */ -#define LCD_CMD_MODE 0x38 /* sets 8 bits, 2 lines, 5x7 characters */ -#define LCD_CMD_ACG 0x40 /* bits 0-5 sets character generator address */ -#define LCD_CMD_ADD 0x80 /* bits 0-6 sets display data addr to line 1 + */ - -/* LCD status values */ -#define LCD_OK 0x00 -#define LCD_ERR 0x01 - -#define LCD_LINE0 0x00 -#define LCD_LINE1 0x40 - -#define LCD_LINE_LENGTH 16 - -extern void lcd_init(void); -extern void lcd_write_char(const char); -extern void lcd_flush(void); -extern void lcd_write_string(const char *); -extern void lcd_printf(const char *, ...); diff --git a/board/cogent/mb.c b/board/cogent/mb.c deleted file mode 100644 index 603f1235a4..0000000000 --- a/board/cogent/mb.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_8260) - -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ {0, 0, 0, 0, 0, 0}, - /* PA30 */ {0, 0, 0, 0, 0, 0}, - /* PA29 */ {0, 0, 0, 0, 0, 0}, - /* PA28 */ {0, 0, 0, 0, 0, 0}, - /* PA27 */ {0, 0, 0, 0, 0, 0}, - /* PA26 */ {0, 0, 0, 0, 0, 0}, - /* PA25 */ {0, 0, 0, 0, 0, 0}, - /* PA24 */ {0, 0, 0, 0, 0, 0}, - /* PA23 */ {0, 0, 0, 0, 0, 0}, - /* PA22 */ {0, 0, 0, 0, 0, 0}, - /* PA21 */ {0, 0, 0, 0, 0, 0}, - /* PA20 */ {0, 0, 0, 0, 0, 0}, - /* PA19 */ {0, 0, 0, 0, 0, 0}, - /* PA18 */ {0, 0, 0, 0, 0, 0}, - /* PA17 */ {0, 0, 0, 0, 0, 0}, - /* PA16 */ {0, 0, 0, 0, 0, 0}, - /* PA15 */ {0, 0, 0, 0, 0, 0}, - /* PA14 */ {0, 0, 0, 0, 0, 0}, - /* PA13 */ {0, 0, 0, 0, 0, 0}, - /* PA12 */ {0, 0, 0, 0, 0, 0}, - /* PA11 */ {0, 0, 0, 0, 0, 0}, - /* PA10 */ {0, 0, 0, 0, 0, 0}, - /* PA9 */ {1, 1, 0, 1, 0, 0}, - /* SMC2 TXD */ - /* PA8 */ {1, 1, 0, 0, 0, 0}, - /* SMC2 RXD */ - /* PA7 */ {0, 0, 0, 0, 0, 0}, - /* PA6 */ {0, 0, 0, 0, 0, 0}, - /* PA5 */ {0, 0, 0, 0, 0, 0}, - /* PA4 */ {0, 0, 0, 0, 0, 0}, - /* PA3 */ {0, 0, 0, 0, 0, 0}, - /* PA2 */ {0, 0, 0, 0, 0, 0}, - /* PA1 */ {0, 0, 0, 0, 0, 0}, - /* PA0 */ {0, 0, 0, 0, 0, 0} - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ {0, 0, 0, 0, 0, 0}, - /* PB30 */ {0, 0, 0, 0, 0, 0}, - /* PB29 */ {0, 0, 0, 0, 0, 0}, - /* PB28 */ {0, 0, 0, 0, 0, 0}, - /* PB27 */ {0, 0, 0, 0, 0, 0}, - /* PB26 */ {0, 0, 0, 0, 0, 0}, - /* PB25 */ {0, 0, 0, 0, 0, 0}, - /* PB24 */ {0, 0, 0, 0, 0, 0}, - /* PB23 */ {0, 0, 0, 0, 0, 0}, - /* PB22 */ {0, 0, 0, 0, 0, 0}, - /* PB21 */ {0, 0, 0, 0, 0, 0}, - /* PB20 */ {0, 0, 0, 0, 0, 0}, - /* PB19 */ {0, 0, 0, 0, 0, 0}, - /* PB18 */ {0, 0, 0, 0, 0, 0}, - /* PB17 */ {0, 0, 0, 0, 0, 0}, - /* PB16 */ {0, 0, 0, 0, 0, 0}, - /* PB15 */ {0, 0, 0, 0, 0, 0}, - /* PB14 */ {0, 0, 0, 0, 0, 0}, - /* PB13 */ {0, 0, 0, 0, 0, 0}, - /* PB12 */ {0, 0, 0, 0, 0, 0}, - /* PB11 */ {0, 0, 0, 0, 0, 0}, - /* PB10 */ {0, 0, 0, 0, 0, 0}, - /* PB9 */ {0, 0, 0, 0, 0, 0}, - /* PB8 */ {0, 0, 0, 0, 0, 0}, - /* PB7 */ {0, 0, 0, 0, 0, 0}, - /* PB6 */ {0, 0, 0, 0, 0, 0}, - /* PB5 */ {0, 0, 0, 0, 0, 0}, - /* PB4 */ {0, 0, 0, 0, 0, 0}, - /* PB3 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PB2 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PB1 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PB0 */ {0, 0, 0, 0, 0, 0} - /* pin doesn't exist */ - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ {0, 0, 0, 0, 0, 0}, - /* PC30 */ {0, 0, 0, 0, 0, 0}, - /* PC29 */ {0, 0, 0, 0, 0, 0}, - /* PC28 */ {0, 0, 0, 0, 0, 0}, - /* PC27 */ {0, 0, 0, 0, 0, 0}, - /* PC26 */ {0, 0, 0, 0, 0, 0}, - /* PC25 */ {0, 0, 0, 0, 0, 0}, - /* PC24 */ {0, 0, 0, 0, 0, 0}, - /* PC23 */ {0, 0, 0, 0, 0, 0}, - /* PC22 */ {0, 0, 0, 0, 0, 0}, - /* PC21 */ {0, 0, 0, 0, 0, 0}, - /* PC20 */ {0, 0, 0, 0, 0, 0}, - /* PC19 */ {0, 0, 0, 0, 0, 0}, - /* PC18 */ {0, 0, 0, 0, 0, 0}, - /* PC17 */ {0, 0, 0, 0, 0, 0}, - /* PC16 */ {0, 0, 0, 0, 0, 0}, - /* PC15 */ {0, 0, 0, 0, 0, 0}, - /* PC14 */ {0, 0, 0, 0, 0, 0}, - /* PC13 */ {0, 0, 0, 0, 0, 0}, - /* PC12 */ {0, 0, 0, 0, 0, 0}, - /* PC11 */ {0, 0, 0, 0, 0, 0}, - /* PC10 */ {0, 0, 0, 0, 0, 0}, - /* PC9 */ {0, 0, 0, 0, 0, 0}, - /* PC8 */ {0, 0, 0, 0, 0, 0}, - /* PC7 */ {0, 0, 0, 0, 0, 0}, - /* PC6 */ {0, 0, 0, 0, 0, 0}, - /* PC5 */ {0, 0, 0, 0, 0, 0}, - /* PC4 */ {0, 0, 0, 0, 0, 0}, - /* PC3 */ {0, 0, 0, 0, 0, 0}, - /* PC2 */ {0, 0, 0, 0, 0, 0}, - /* PC1 */ {0, 0, 0, 0, 0, 0}, - /* PC0 */ {0, 0, 0, 0, 0, 0} - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ {0, 0, 0, 0, 0, 0}, - /* PD30 */ {0, 0, 0, 0, 0, 0}, - /* PD29 */ {0, 0, 0, 0, 0, 0}, - /* PD28 */ {0, 0, 0, 0, 0, 0}, - /* PD27 */ {0, 0, 0, 0, 0, 0}, - /* PD26 */ {0, 0, 0, 0, 0, 0}, - /* PD25 */ {0, 0, 0, 0, 0, 0}, - /* PD24 */ {0, 0, 0, 0, 0, 0}, - /* PD23 */ {0, 0, 0, 0, 0, 0}, - /* PD22 */ {0, 0, 0, 0, 0, 0}, - /* PD21 */ {0, 0, 0, 0, 0, 0}, - /* PD20 */ {0, 0, 0, 0, 0, 0}, - /* PD19 */ {0, 0, 0, 0, 0, 0}, - /* PD18 */ {0, 0, 0, 0, 0, 0}, - /* PD17 */ {0, 0, 0, 0, 0, 0}, - /* PD16 */ {0, 0, 0, 0, 0, 0}, - /* PD15 */ {1, 1, 1, 0, 0, 0}, - /* I2C SDA */ - /* PD14 */ {1, 1, 1, 0, 0, 0}, - /* I2C SCL */ - /* PD13 */ {0, 0, 0, 0, 0, 0}, - /* PD12 */ {0, 0, 0, 0, 0, 0}, - /* PD11 */ {0, 0, 0, 0, 0, 0}, - /* PD10 */ {0, 0, 0, 0, 0, 0}, - /* PD9 */ {1, 1, 0, 1, 0, 0}, - /* SMC1 TXD */ - /* PD8 */ {1, 1, 0, 0, 0, 0}, - /* SMC1 RXD */ - /* PD7 */ {0, 0, 0, 0, 0, 0}, - /* PD6 */ {0, 0, 0, 0, 0, 0}, - /* PD5 */ {0, 0, 0, 0, 0, 0}, - /* PD4 */ {0, 0, 0, 0, 0, 0}, - /* PD3 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PD2 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PD1 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PD0 */ {0, 0, 0, 0, 0, 0} - /* pin doesn't exist */ - } -}; - -#endif /* CONFIG_8260 */ - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a " - COGENT_CPU_MODULE " CPU Module\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations while still - * running in flash - */ - -int misc_init_f (void) -{ - printf ("DIPSW: "); - dipsw_init (); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ -#ifdef CONFIG_CMA111 - return (32L * 1024L * 1024L); -#else - unsigned char dipsw_val; - int dual, size0, size1; - long int memsize; - - dipsw_val = dipsw_cooked (); - - dual = dipsw_val & 0x01; - size0 = (dipsw_val & 0x08) >> 3; - size1 = (dipsw_val & 0x04) >> 2; - - if (size0) - if (size1) - memsize = 16L * 1024L * 1024L; - else - memsize = 1L * 1024L * 1024L; - else if (size1) - memsize = 4L * 1024L * 1024L; - else { - printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] "); - memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */ - } - - if (dual) - memsize *= 2L; - - return (memsize); -#endif -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations after monitor - * has been relocated into ram - */ - -int misc_init_r (void) -{ - printf ("LCD: "); - lcd_init (); - -#if 0 - printf ("RTC: "); - rtc_init (); - - printf ("PAR: "); - par_init (); - - printf ("KBM: "); - kbm_init (); - - printf ("PCI: "); - pci_init (); -#endif - return (0); -} diff --git a/board/cogent/mb.h b/board/cogent/mb.h deleted file mode 100644 index 1db516fb02..0000000000 --- a/board/cogent/mb.h +++ /dev/null @@ -1,513 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * defines for Cogent Motherboards - */ - -#ifndef _COGENT_MB_H -#define _COGENT_MB_H - -/* - * Cogent Motherboard Address Map - * - * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits). - * - * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following - * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and - * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3). - * Most other motherboard devices have registers mapped into the area - * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF - * is free for whatever. - * - * The location of the motherboard address space in the physical address space - * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu - * module plugged into the motherboard and is configured above. - * - * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF) - * generally only use byte lane 0 (D0-7) for their transfers, i.e. only - * 8 bit, or 1 byte, transfers can take place, so all the registers are - * only 8 bits wide. The exceptions are the motherboard flash, which uses - * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space. - * - * I/O registers within the mapped motherboard devices are 64 bit aligned - * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register - * will be at byte 7 (the address + 7). For little endian addressing, the - * register will be at byte 0 (the address + 0). To learn the endianess - * we must include - * - * Take the CMA102 and CMA111 motherboards as examples... - * - * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3 - * CMABus slots are each mapped directly onto the three general I/O slots. - * - * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI - * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard - * PCI Bus space is mapped onto general I/O slot 2, with a small area at the - * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF). - * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area - * 0xA000000-0xDFFFFFF. - */ - -#define CMA_MB_RAM_BASE (CONFIG_SYS_CMA_MB_BASE+0x0000000) -#define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */ - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1) -#define CMA_MB_SLOT1_BASE (CONFIG_SYS_CMA_MB_BASE+0x2000000) -#define CMA_MB_SLOT1_SIZE 0x2000000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) -#define CMA_MB_SLOT2_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000) -#define CMA_MB_SLOT2_SIZE 0x2000000 -#endif -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) -#define CMA_MB_STDPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000) -#define CMA_MB_STDPCI_SIZE 0x1ff0000 -#define CMA_MB_V360EPC_BASE (CONFIG_SYS_CMA_MB_BASE+0x5ff0000) -#define CMA_MB_V360EPC_SIZE 0x10000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3) -#define CMA_MB_SLOT3_BASE (CONFIG_SYS_CMA_MB_BASE+0x6000000) -#define CMA_MB_SLOT3_SIZE 0x2000000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) -#define CMA_MB_EXTPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0xa000000) -#define CMA_MB_EXTPCI_SIZE 0x4000000 -#endif - -#define CMA_MB_ROMLOW_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000) -#define CMA_MB_ROMLOW_SIZE 0x800000 -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -#define CMA_MB_FLLOW_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000) -#define CMA_MB_FLLOW_EXEC_SIZE 0x100000 -#define CMA_MB_FLLOW_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe400000) -#define CMA_MB_FLLOW_RDWR_SIZE 0x400000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_RTC) -#define CMA_MB_RTC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe800000) -#define CMA_MB_RTC_SIZE 0x4000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) -#define CMA_MB_SERPAR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900000) -#define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00) -#define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40) -#define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80) -#define CMA_MB_SERPAR_SIZE 0xa0 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) -#define CMA_MB_PKBM_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900100) -#define CMA_MB_PKBM_SIZE 0x10 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_LCD) -#define CMA_MB_LCD_BASE (CONFIG_SYS_CMA_MB_BASE+0xeb00000) -#define CMA_MB_LCD_SIZE 0x10 -#endif - -#define CMA_MB_DIPSW_BASE (CONFIG_SYS_CMA_MB_BASE+0xec00000) -#define CMA_MB_DIPSW_SIZE 0x10 - -#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM)) -#define CMA_MB_SLOT1CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf100000) -#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80) -#define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00) -#define CMA_MB_SER2A_BASE (CMA_MB_SER2_BASE+0x40) -#endif -#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1) -#define CMA_MB_S1KBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200) -#endif -#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150) -#define CMA_MB_IREQ1STAT_BASE (CMA_MB_SLOT1CFG_BASE+0x100) -#define CMA_MB_AKBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200) -#define CMA_MB_IREQ1MASK_BASE (CMA_MB_SLOT1CFG_BASE+0x300) -#endif -#define CMA_MB_SLOT1CFG_SIZE 0x400 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) -#define CMA_MB_SLOT2CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000) -#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2) -#define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200) -#endif -#define CMA_MB_SLOT2CFG_SIZE 0x400 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) -#define CMA_MB_PCICTL_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000) -#define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100) -#define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200) -#define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300) -#define CMA_MB_PCI_ISTAT_BASE (CMA_MB_PCICTL_BASE+0x400) -#define CMA_MB_PCI_MBID_BASE (CMA_MB_PCICTL_BASE+0x500) -#define CMA_MB_PCI_MBREV_BASE (CMA_MB_PCICTL_BASE+0x600) -#define CMA_MB_PCICTL_SIZE 0x700 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3) -#define CMA_MB_SLOT3CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf300000) -#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3) -#define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200) -#endif -#define CMA_MB_SLOT3CFG_SIZE 0x400 -#endif - -#define CMA_MB_ROMHIGH_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000) -#define CMA_MB_ROMHIGH_SIZE 0x800000 -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -#define CMA_MB_FLHIGH_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000) -#define CMA_MB_FLHIGH_EXEC_SIZE 0x100000 -#define CMA_MB_FLHIGH_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xfc00000) -#define CMA_MB_FLHIGH_RDWR_SIZE 0x400000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) - -/* PCI Control Register bits */ - -/* V360EPC Control register bits */ -#define CMA_MB_PCI_V3CTL_RESET 0x01 -#define CMA_MB_PCI_V3CTL_EXTADD 0x08 - -/* PCI ID Select register bits */ -#define CMA_MB_PCI_IDSEL_SLOTA 0x01 -#define CMA_MB_PCI_IDSEL_SLOTB 0x02 -#define CMA_MB_PCI_IDSEL_GD82559 0x04 -#define CMA_MB_PCI_IDSEL_B69000 0x08 -#define CMA_MB_PCI_IDSEL_PD6832 0x10 - -/* PCI Interrupt Mask/Status register bits */ -#define CMA_MB_PCI_IMS_INTA 0x01 -#define CMA_MB_PCI_IMS_INTB 0x02 -#define CMA_MB_PCI_IMS_INTC 0x04 -#define CMA_MB_PCI_IMS_INTD 0x08 -#define CMA_MB_PCI_IMS_CBINT 0x10 -#define CMA_MB_PCI_IMS_V3LINT 0x80 - -#endif - -#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150) - -/* - * IREQ1 Interrupt Mask/Status register bits - * (Note: not available on CMA150 - must poll HT6542B interrupt register) - */ - -#define IREQ1_MINT 0x01 -#define IREQ1_KINT 0x02 -#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define IREQ1_SINT2 0x04 -#define IREQ1_SINT3 0x08 -#endif - -#endif - -#ifndef __ASSEMBLY__ - -#ifdef USE_HOSTCC -#include /* avoid using private kernel header files */ -#else -#include /* use U-Boot provided headers */ -#endif - -/* a single CMA10x motherboard i/o register */ -typedef - struct { -#if __BYTE_ORDER == __LITTLE_ENDIAN - unsigned char value; -#endif - unsigned char filler[7]; -#if __BYTE_ORDER == __BIG_ENDIAN - unsigned char value; -#endif - } -cma_mb_reg; - -extern __inline__ unsigned char -cma_mb_reg_read(volatile cma_mb_reg *reg) -{ - unsigned char data = reg->value; - __asm__ __volatile__ ("eieio" : : : "memory"); - return data; -} - -extern __inline__ void -cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data) -{ - reg->value = data; - __asm__ __volatile__ ("eieio" : : : "memory"); -} - -#if (CMA_MB_CAPS & CMA_MB_CAP_RTC) - -/* MK48T02 RTC registers */ -typedef - struct { - cma_mb_reg sram[2040];/* Battery-Backed SRAM */ - cma_mb_reg clk_ctl; /* Clock Control Register */ - cma_mb_reg clk_sec; /* Clock Seconds Register */ - cma_mb_reg clk_min; /* Clock Minutes Register */ - cma_mb_reg clk_hour; /* Clock Hour Register */ - cma_mb_reg clk_day; /* Clock Day Register */ - cma_mb_reg clk_date; /* Clock Date Register */ - cma_mb_reg clk_month; /* Clock Month Register */ - cma_mb_reg clk_year; /* Clock Year Register */ - } -cma_mb_rtc; - -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) - -/* ST16C522 Serial I/O */ -typedef - struct { - cma_mb_reg ser_rhr; /* Receive Holding Register (R, DLAB=0) */ - cma_mb_reg ser_ier; /* Interrupt Enable Register (R/W, DLAB=0) */ - cma_mb_reg ser_isr; /* Interrupt Status Register (R) */ - cma_mb_reg ser_lcr; /* Line Control Register (R/W) */ - cma_mb_reg ser_mcr; /* Modem Control Register (R/W) */ - cma_mb_reg ser_lsr; /* Line Status Register (R) */ - cma_mb_reg ser_msr; /* Modem Status Register (R/W) */ - cma_mb_reg ser_spr; /* Scratch Pad Register (R/W) */ - } -cma_mb_serial; - -#define ser_thr ser_rhr /* Transmit Holding Register (W, DLAB=0) */ -#define ser_brl ser_rhr /* Baud Rate Divisor Low Byte (R/W, DLAB=1) */ -#define ser_brh ser_ier /* Baud Rate Divisor High Byte (R/W, DLAB=1) */ -#define ser_fcr ser_isr /* FIFO Control Register (W) */ -#define ser_nop ser_lsr /* No Operation (W) */ - -/* ST16C522 Parallel I/O */ -typedef - struct { - cma_mb_reg par_rdr; /* Port Read Data Register (R) */ - cma_mb_reg par_sr; /* Status Register (R) */ - cma_mb_reg par_cmd; /* Command Register (R) */ - } -cma_mb_parallel; - -#define par_wdr par_rdr /* Port Write Data Register (W) */ -#define par_ios par_sr /* I/O Select Register (W) */ -#define par_ctl par_cmd /* Control Register (W) */ - -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302) - -/* HT6542B PS/2 Keyboard/Mouse Controller */ -typedef - struct { - cma_mb_reg kbm_rdr; /* Read Data Register (R) */ - cma_mb_reg kbm_sr; /* Status Register (R) */ - } -cma_mb_kbm; - -#define kbm_wdr kbm_rdr /* Write Data Register (W) */ -#define kbm_cmd kbm_sr /* Command Register (W) */ - -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_LCD) - -/* HD44780 LCD Display */ -typedef - struct { - cma_mb_reg lcd_ccr; /* Current Character Register (R/W) */ - cma_mb_reg lcd_bsr; /* Busy Status Register (R) */ - } -cma_mb_lcd; - -#define lcd_cmd lcd_bsr /* Command Register (W) */ - -#endif - -/* 8-Position Configuration Switch */ -typedef - struct { - cma_mb_reg dip_val; /* Dip Switch value (R) */ - } -cma_mb_dipsw; - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) - -/* V360EPC PCI Bridge */ -typedef - struct { -#if __BYTE_ORDER == __LITTLE_ENDIAN - unsigned short v3_pci_vendor; /* 0x00 */ - unsigned short v3_pci_device; - unsigned short v3_pci_cmd; /* 0x04 */ - unsigned short v3_pci_stat; - unsigned long v3_pci_cc_rev; /* 0x08 */ - unsigned long v3_pci_hdr_cfg; /* 0x0c */ - unsigned long v3_pci_io_base; /* 0x10 */ - unsigned long v3_pci_base0; /* 0x14 */ - unsigned long v3_pci_base1; /* 0x18 */ - unsigned long reserved1[4]; /* 0x1c */ - unsigned short v3_pci_sub_vendor; /* 0x2c */ - unsigned short v3_pci_sub_id; - unsigned long v3_pci_rom; /* 0x30 */ - unsigned long reserved2[2]; /* 0x34 */ - unsigned long v3_pci_bparam; /* 0x3c */ - unsigned long v3_pci_map0; /* 0x40 */ - unsigned long v3_pci_map1; /* 0x44 */ - unsigned long v3_pci_int_stat; /* 0x48 */ - unsigned long v3_pci_int_cfg; /* 0x4c */ - unsigned long reserved3[1]; /* 0x50 */ - unsigned long v3_lb_base0; /* 0x54 */ - unsigned long v3_lb_base1; /* 0x58 */ - unsigned short reserved4; /* 0x5c */ - unsigned short v3_lb_map0; - unsigned short reserved5; /* 0x60 */ - unsigned short v3_lb_map1; - unsigned short v3_lb_base2; /* 0x64 */ - unsigned short v3_lb_map2; - unsigned long v3_lb_size; /* 0x68 */ - unsigned short reserved6; /* 0x6c */ - unsigned short v3_lb_io_base; - unsigned short v3_fifo_cfg; /* 0x70 */ - unsigned short v3_fifo_priority; - unsigned short v3_fifo_stat; /* 0x74 */ - unsigned char v3_lb_istat; - unsigned char v3_lb_imask; - unsigned short v3_system; /* 0x78 */ - unsigned short v3_lb_cfg; - unsigned short v3_pci_cfg; /* 0x7c */ - unsigned short reserved7; - unsigned long v3_dma_pci_addr0; /* 0x80 */ - unsigned long v3_dma_local_addr0; /* 0x84 */ - unsigned long v3_dma_length0:24; /* 0x88 */ - unsigned long v3_dma_csr0:8; - unsigned long v3_dma_ctlb_adr0; /* 0x8c */ - unsigned long v3_dma_pci_addr1; /* 0x90 */ - unsigned long v3_dma_local_addr1; /* 0x94 */ - unsigned long v3_dma_length1:24; /* 0x98 */ - unsigned long v3_dma_csr1:8; - unsigned long v3_dma_ctlb_adr1; /* 0x9c */ - unsigned long v3_i20_mups[8]; /* 0xa0 */ - unsigned char v3_mail_data0; /* 0xc0 */ - unsigned char v3_mail_data1; - unsigned char v3_mail_data2; - unsigned char v3_mail_data3; - unsigned char v3_mail_data4; /* 0xc4 */ - unsigned char v3_mail_data5; - unsigned char v3_mail_data6; - unsigned char v3_mail_data7; - unsigned char v3_mail_data8; /* 0xc8 */ - unsigned char v3_mail_data9; - unsigned char v3_mail_data10; - unsigned char v3_mail_data11; - unsigned char v3_mail_data12; /* 0xcc */ - unsigned char v3_mail_data13; - unsigned char v3_mail_data14; - unsigned char v3_mail_data15; - unsigned short v3_pci_mail_iewr; /* 0xd0 */ - unsigned short v3_pci_mail_ierd; - unsigned short v3_lb_mail_iewr; /* 0xd4 */ - unsigned short v3_lb_mail_ierd; - unsigned short v3_mail_wr_stat; /* 0xd8 */ - unsigned short v3_mail_rd_stat; - unsigned long v3_qba_map; /* 0xdc */ - unsigned long v3_dma_delay:8; /* 0xe0 */ - unsigned long reserved8:24; - unsigned long reserved9[7]; /* 0xe4 */ -#endif -#if __BYTE_ORDER == __BIG_ENDIAN - unsigned short v3_pci_device; /* 0x00 */ - unsigned short v3_pci_vendor; - unsigned short v3_pci_stat; /* 0x04 */ - unsigned short v3_pci_cmd; - unsigned long v3_pci_cc_rev; /* 0x08 */ - unsigned long v3_pci_hdr_cfg; /* 0x0c */ - unsigned long v3_pci_io_base; /* 0x10 */ - unsigned long v3_pci_base0; /* 0x14 */ - unsigned long v3_pci_base1; /* 0x18 */ - unsigned long reserved1[4]; /* 0x1c */ - unsigned short v3_pci_sub_id; /* 0x2c */ - unsigned short v3_pci_sub_vendor; - unsigned long v3_pci_rom; /* 0x30 */ - unsigned long reserved2[2]; /* 0x34 */ - unsigned long v3_pci_bparam; /* 0x3c */ - unsigned long v3_pci_map0; /* 0x40 */ - unsigned long v3_pci_map1; /* 0x44 */ - unsigned long v3_pci_int_stat; /* 0x48 */ - unsigned long v3_pci_int_cfg; /* 0x4c */ - unsigned long reserved3; /* 0x50 */ - unsigned long v3_lb_base0; /* 0x54 */ - unsigned long v3_lb_base1; /* 0x58 */ - unsigned short v3_lb_map0; /* 0x5c */ - unsigned short reserved4; - unsigned short v3_lb_map1; /* 0x60 */ - unsigned short reserved5; - unsigned short v3_lb_map2; /* 0x64 */ - unsigned short v3_lb_base2; - unsigned long v3_lb_size; /* 0x68 */ - unsigned short v3_lb_io_base; /* 0x6c */ - unsigned short reserved6; - unsigned short v3_fifo_priority; /* 0x70 */ - unsigned short v3_fifo_cfg; - unsigned char v3_lb_imask; /* 0x74 */ - unsigned char v3_lb_istat; - unsigned short v3_fifo_stat; - unsigned short v3_lb_cfg; /* 0x78 */ - unsigned short v3_system; - unsigned short reserved7; /* 0x7c */ - unsigned short v3_pci_cfg; - unsigned long v3_dma_pci_addr0; /* 0x80 */ - unsigned long v3_dma_local_addr0; /* 0x84 */ - unsigned long v3_dma_csr0:8; /* 0x88 */ - unsigned long v3_dma_length0:24; - unsigned long v3_dma_ctlb_adr0; /* 0x8c */ - unsigned long v3_dma_pci_addr1; /* 0x90 */ - unsigned long v3_dma_local_addr1; /* 0x94 */ - unsigned long v3_dma_csr1:8; /* 0x98 */ - unsigned long v3_dma_length1:24; - unsigned long v3_dma_ctlb_adr1; /* 0x9c */ - unsigned long v3_i20_mups[8]; /* 0xa0 */ - unsigned char v3_mail_data3; /* 0xc0 */ - unsigned char v3_mail_data2; - unsigned char v3_mail_data1; - unsigned char v3_mail_data0; - unsigned char v3_mail_data7; /* 0xc4 */ - unsigned char v3_mail_data6; - unsigned char v3_mail_data5; - unsigned char v3_mail_data4; - unsigned char v3_mail_data11; /* 0xc8 */ - unsigned char v3_mail_data10; - unsigned char v3_mail_data9; - unsigned char v3_mail_data8; - unsigned char v3_mail_data15; /* 0xcc */ - unsigned char v3_mail_data14; - unsigned char v3_mail_data13; - unsigned char v3_mail_data12; - unsigned short v3_pci_mail_ierd; /* 0xd0 */ - unsigned short v3_pci_mail_iewr; - unsigned short v3_lb_mail_ierd; /* 0xd4 */ - unsigned short v3_lb_mail_iewr; - unsigned short v3_mail_rd_stat; /* 0xd8 */ - unsigned short v3_mail_wr_stat; - unsigned long v3_qba_map; /* 0xdc */ - unsigned long reserved8:24; /* 0xe0 */ - unsigned long v3_dma_delay:8; - unsigned long reserved9[7]; /* 0xe4 */ -#endif - } /* 0x100 */ -cma_mb_v360epc; - -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* _COGENT_MB_H */ diff --git a/board/cogent/par.c b/board/cogent/par.c deleted file mode 100644 index a03c0f10d2..0000000000 --- a/board/cogent/par.c +++ /dev/null @@ -1,3 +0,0 @@ -/* parallel not implemented yet */ - -int cma_parallel_not_implemented = 1; diff --git a/board/cogent/par.h b/board/cogent/par.h deleted file mode 100644 index 664ae4a952..0000000000 --- a/board/cogent/par.h +++ /dev/null @@ -1,3 +0,0 @@ -/* parallel not implemented yet */ - -extern int cma_parallel_not_implemented; diff --git a/board/cogent/pci.c b/board/cogent/pci.c deleted file mode 100644 index 0a57c0c558..0000000000 --- a/board/cogent/pci.c +++ /dev/null @@ -1,3 +0,0 @@ -/* pci not implemented yet */ - -int cma_pci_not_implemented = 1; diff --git a/board/cogent/pci.h b/board/cogent/pci.h deleted file mode 100644 index 35aa354a24..0000000000 --- a/board/cogent/pci.h +++ /dev/null @@ -1,3 +0,0 @@ -/* pci not implemented yet */ - -extern int cma_pci_not_implemented; diff --git a/board/cogent/rtc.c b/board/cogent/rtc.c deleted file mode 100644 index ace9193542..0000000000 --- a/board/cogent/rtc.c +++ /dev/null @@ -1,3 +0,0 @@ -/* rtc not implemented yet */ - -int cma_rtc_not_implemented = 1; diff --git a/board/cogent/rtc.h b/board/cogent/rtc.h deleted file mode 100644 index 4b55bd2275..0000000000 --- a/board/cogent/rtc.h +++ /dev/null @@ -1,3 +0,0 @@ -/* rtc not implemented yet */ - -extern int cma_rtc_not_implemented; diff --git a/board/cogent/serial.c b/board/cogent/serial.c deleted file mode 100644 index 20631d162d..0000000000 --- a/board/cogent/serial.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Simple serial driver for Cogent motherboard serial ports - * for use during boot - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) - -#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \ - (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE)) - -#if CONFIG_CONS_INDEX == 1 -#define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE -#elif CONFIG_CONS_INDEX == 2 -#define CMA_MB_SERIAL_BASE CMA_MB_SERIALB_BASE -#elif CONFIG_CONS_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_SERIAL_BASE CMA_MB_SER2A_BASE -#elif CONFIG_CONS_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_SERIAL_BASE CMA_MB_SER2B_BASE -#else -#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial -#endif - -static int cogent_serial_init(void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - - cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */ - serial_setbrg (); - cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ - cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */ - cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ - - return (0); -} - -static void cogent_serial_setbrg(void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - unsigned int divisor; - unsigned char lcr; - - if ((divisor = br_to_div (gd->baudrate)) == 0) - divisor = DEFDIV; - - lcr = cma_mb_reg_read (&mbsp->ser_lcr); - cma_mb_reg_write (&mbsp->ser_lcr, lcr | 0x80); /* Access baud rate(set DLAB) */ - cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff); - cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff); - cma_mb_reg_write (&mbsp->ser_lcr, lcr); /* unset DLAB */ -} - -static void cogent_serial_putc(const char c) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - - if (c == '\n') - serial_putc ('\r'); - - while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0); - - cma_mb_reg_write (&mbsp->ser_thr, c); -} - -static int cogent_serial_getc(void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - - while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0); - - return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f); -} - -static int cogent_serial_tstc(void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; - - return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0); -} - -static struct serial_device cogent_serial_drv = { - .name = "cogent_serial", - .start = cogent_serial_init, - .stop = NULL, - .setbrg = cogent_serial_setbrg, - .putc = cogent_serial_putc, - .puts = default_serial_puts, - .getc = cogent_serial_getc, - .tstc = cogent_serial_tstc, -}; - -void cogent_serial_initialize(void) -{ - serial_register(&cogent_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &cogent_serial_drv; -} -#endif /* CONS_NONE */ - -#if defined(CONFIG_CMD_KGDB) && \ - defined(CONFIG_KGDB_NONE) - -#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX -#error Console and kgdb are on the same serial port - this is not supported -#endif - -#if CONFIG_KGDB_INDEX == 1 -#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALA_BASE -#elif CONFIG_KGDB_INDEX == 2 -#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALB_BASE -#elif CONFIG_KGDB_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2A_BASE -#elif CONFIG_KGDB_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2B_BASE -#else -#error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial -#endif - -void kgdb_serial_init (void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE; - unsigned int divisor; - - if ((divisor = br_to_div (CONFIG_KGDB_BAUDRATE)) == 0) - divisor = DEFDIV; - - cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */ - cma_mb_reg_write (&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB) */ - cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff); - cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff); - cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ - cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */ - cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ - - printf ("[on cma10x serial port B] "); -} - -void putDebugChar (int c) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE; - - while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0); - - cma_mb_reg_write (&mbsp->ser_thr, c & 0xff); -} - -void putDebugStr (const char *str) -{ - while (*str != '\0') { - if (*str == '\n') - putDebugChar ('\r'); - putDebugChar (*str++); - } -} - -int getDebugChar (void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE; - - while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0); - - return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f); -} - -void kgdb_interruptible (int yes) -{ - cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE; - - if (yes == 1) { - printf ("kgdb: turning serial ints on\n"); - cma_mb_reg_write (&mbsp->ser_ier, 0xf); - } else { - printf ("kgdb: turning serial ints off\n"); - cma_mb_reg_write (&mbsp->ser_ier, 0x0); - } -} - -#endif /* KGDB && KGDB_NONE */ - -#endif /* CAPS & SERPAR */ diff --git a/board/cogent/serial.h b/board/cogent/serial.h deleted file mode 100644 index 89962d887d..0000000000 --- a/board/cogent/serial.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Line Status Register bits */ -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -#define CLKRATE 3686400 /* cogent motherboard serial clk = 3.6864MHz */ -#define DEFDIV 1 /* default to 230400 bps */ - -#define br_to_div(br) (CLKRATE / (16 * (br))) -#define div_to_br(div) (CLKRATE / (16 * (div))) diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds deleted file mode 100644 index 4c63ff2946..0000000000 --- a/board/cogent/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { -#ifdef CONFIG_MPC8260 - arch/powerpc/cpu/mpc8260/start.o (.text*) -#else - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) -#endif - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug deleted file mode 100644 index b9c84c77d6..0000000000 --- a/board/cogent/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/comelit/dig297/Kconfig b/board/comelit/dig297/Kconfig new file mode 100644 index 0000000000..6dccaff5b0 --- /dev/null +++ b/board/comelit/dig297/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DIG297 + +config SYS_BOARD + default "dig297" + +config SYS_VENDOR + default "comelit" + +config SYS_CONFIG_NAME + default "dig297" + +endif diff --git a/board/comelit/dig297/MAINTAINERS b/board/comelit/dig297/MAINTAINERS new file mode 100644 index 0000000000..318374e256 --- /dev/null +++ b/board/comelit/dig297/MAINTAINERS @@ -0,0 +1,6 @@ +DIG297 BOARD +M: Luca Ceresoli +S: Maintained +F: board/comelit/dig297/ +F: include/configs/dig297.h +F: configs/dig297_defconfig diff --git a/board/comelit/dig297/Makefile b/board/comelit/dig297/Makefile index 1a5b598077..1c85b63bf3 100644 --- a/board/comelit/dig297/Makefile +++ b/board/comelit/dig297/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := dig297.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dig297.o diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index 2b826dffc5..9d4c41b00b 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -133,6 +133,11 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} #endif #ifdef CONFIG_CMD_NET diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts deleted file mode 100644 index 780203cfb3..0000000000 --- a/board/compal/dts/tegra20-paz00.dts +++ /dev/null @@ -1,91 +0,0 @@ -/dts-v1/; - -#include "tegra20.dtsi" - -/ { - model = "Toshiba AC100 / Dynabook AZ"; - compatible = "compal,paz00", "nvidia,tegra20"; - - aliases { - usb0 = "/usb@c5008000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000000"; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - host1x { - status = "okay"; - dc@54200000 { - status = "okay"; - rgb { - status = "okay"; - nvidia,panel = <&lcd_panel>; - }; - }; - }; - - serial@70006000 { - clock-frequency = < 216000000 >; - }; - - i2c@7000c000 { - status = "disabled"; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - - usb@c5000000 { - status = "disabled"; - }; - - usb@c5004000 { - status = "disabled"; - }; - - sdhci@c8000000 { - status = "okay"; - cd-gpios = <&gpio 173 1>; /* gpio PV5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 169 0>; /* gpio PV1 */ - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - }; - - lcd_panel: panel { - /* PAZ00 has 1024x600 */ - clock = <54030000>; - xres = <1024>; - yres = <600>; - right-margin = <160>; - left-margin = <24>; - hsync-len = <136>; - upper-margin = <3>; - lower-margin = <61>; - vsync-len = <6>; - hsync-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 0 0>; - nvidia,backlight-enable-gpios = <&gpio 164 0>; /* PU4 */ - nvidia,lvds-shutdown-gpios = <&gpio 102 0>; /* PM6 */ - nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ - nvidia,panel-vdd-gpios = <&gpio 4 0>; /* PA4 */ - nvidia,panel-timings = <400 4 203 17 15>; - }; -}; diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig new file mode 100644 index 0000000000..30ba11d360 --- /dev/null +++ b/board/compal/paz00/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PAZ00 + +config SYS_BOARD + default "paz00" + +config SYS_VENDOR + default "compal" + +config SYS_CONFIG_NAME + default "paz00" + +endif diff --git a/board/compal/paz00/MAINTAINERS b/board/compal/paz00/MAINTAINERS new file mode 100644 index 0000000000..ee2b2e9545 --- /dev/null +++ b/board/compal/paz00/MAINTAINERS @@ -0,0 +1,7 @@ +PAZ00 BOARD +M: Tom Warren +M: Stephen Warren +S: Maintained +F: board/compal/paz00/ +F: include/configs/paz00.h +F: configs/paz00_defconfig diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index fa5c510340..e6a0b29997 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -14,28 +14,6 @@ # more details. # -include $(TOPDIR)/config.mk +obj-y := paz00.o -$(shell mkdir -p $(obj)../../nvidia/common) - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -include ../../nvidia/common/common.mk - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index d6e5c3740e..462ab05556 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -28,23 +28,23 @@ void pin_mux_mmc(void) { /* SDMMC4: config 3, x8 on 2nd set of pins */ - pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); - pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); - pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); - pinmux_tristate_disable(PINGRP_ATB); - pinmux_tristate_disable(PINGRP_GMA); - pinmux_tristate_disable(PINGRP_GME); + pinmux_tristate_disable(PMUX_PINGRP_ATB); + pinmux_tristate_disable(PMUX_PINGRP_GMA); + pinmux_tristate_disable(PMUX_PINGRP_GME); /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ - pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); + pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PINGRP_SDIO1); + pinmux_tristate_disable(PMUX_PINGRP_SDIO1); /* For power GPIO PV1 */ - pinmux_tristate_disable(PINGRP_UAC); + pinmux_tristate_disable(PMUX_PINGRP_UAC); /* For CD GPIO PV5 */ - pinmux_tristate_disable(PINGRP_GPV); + pinmux_tristate_disable(PMUX_PINGRP_GPV); } #endif @@ -55,6 +55,6 @@ void pin_mux_display(void) debug("init display pinmux\n"); /* EN_VDD_PANEL GPIO A4 */ - pinmux_tristate_disable(PINGRP_DAP2); + pinmux_tristate_disable(PMUX_PINGRP_DAP2); } #endif diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig new file mode 100644 index 0000000000..508c21f58b --- /dev/null +++ b/board/compulab/cm_fx6/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CM_FX6 + +config SYS_BOARD + default "cm_fx6" + +config SYS_VENDOR + default "compulab" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "cm_fx6" + +endif diff --git a/board/compulab/cm_fx6/MAINTAINERS b/board/compulab/cm_fx6/MAINTAINERS new file mode 100644 index 0000000000..5b2623a664 --- /dev/null +++ b/board/compulab/cm_fx6/MAINTAINERS @@ -0,0 +1,6 @@ +CM_FX6 BOARD +M: Nikita Kiryanov +S: Maintained +F: board/compulab/cm_fx6/ +F: include/configs/cm_fx6.h +F: configs/cm_fx6_defconfig diff --git a/board/compulab/cm_fx6/Makefile b/board/compulab/cm_fx6/Makefile new file mode 100644 index 0000000000..3e5c9034df --- /dev/null +++ b/board/compulab/cm_fx6/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2014 CompuLab, Ltd. +# +# Authors: Nikita Kiryanov +# +# SPDX-License-Identifier: GPL-2.0+ +# +ifdef CONFIG_SPL_BUILD +obj-y = common.o spl.o +else +obj-y = common.o cm_fx6.o +endif diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c new file mode 100644 index 0000000000..84e36439fa --- /dev/null +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -0,0 +1,584 @@ +/* + * Board functions for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "../common/eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DWC_AHSATA +static int cm_fx6_issd_gpios[] = { + /* The order of the GPIOs in the array is important! */ + CM_FX6_SATA_LDO_EN, + CM_FX6_SATA_PHY_SLP, + CM_FX6_SATA_NRSTDLY, + CM_FX6_SATA_PWREN, + CM_FX6_SATA_NSTANDBY1, + CM_FX6_SATA_NSTANDBY2, +}; + +static void cm_fx6_sata_power(int on) +{ + int i; + + if (!on) { /* tell the iSSD that the power will be removed */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); + mdelay(10); + } + + for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { + gpio_direction_output(cm_fx6_issd_gpios[i], on); + udelay(100); + } + + if (!on) /* for compatibility lower the power loss interrupt */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); +} + +static iomux_v3_cfg_t const sata_pads[] = { + /* SATA PWR */ + IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* SATA CTRL */ + IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static int cm_fx6_setup_issd(void) +{ + int ret, i; + + SETUP_IOMUX_PADS(sata_pads); + + for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { + ret = gpio_request(cm_fx6_issd_gpios[i], "sata"); + if (ret) + return ret; + } + + ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int"); + if (ret) + return ret; + + return 0; +} + +#define CM_FX6_SATA_INIT_RETRIES 10 +int sata_initialize(void) +{ + int err, i; + + /* Make sure this gpio has logical 0 value */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); + udelay(100); + cm_fx6_sata_power(1); + + for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { + err = setup_sata(); + if (err) { + printf("SATA setup failed: %d\n", err); + return err; + } + + udelay(100); + + err = __sata_initialize(); + if (!err) + break; + + /* There is no device on the SATA port */ + if (sata_port_status(0, 0) == 0) + break; + + /* There's a device, but link not established. Retry */ + } + + return err; +} + +int sata_stop(void) +{ + __sata_stop(); + cm_fx6_sata_power(0); + mdelay(250); + + return 0; +} +#else +static int cm_fx6_setup_issd(void) { return 0; } +#endif + +#ifdef CONFIG_SYS_I2C_MXC +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +I2C_PADS(i2c0_pads, + PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(3, 21), + PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(3, 28)); + +I2C_PADS(i2c1_pads, + PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(4, 12), + PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(4, 13)); + +I2C_PADS(i2c2_pads, + PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(1, 3), + PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(1, 6)); + + +static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) +{ + int ret; + + ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads); + if (ret) + printf("Warning: I2C%d setup failed: %d\n", busnum, ret); + + return ret; +} + +static int cm_fx6_setup_i2c(void) +{ + int ret = 0, err; + + /* i2c_pads are wierd macro variables; we can't use an array */ + err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads)); + if (err) + ret = err; + err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads)); + if (err) + ret = err; + err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads)); + if (err) + ret = err; + + return ret; +} +#else +static int cm_fx6_setup_i2c(void) { return 0; } +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_SRE_SLOW) +#define MX6_USBNC_BASEADDR 0x2184800 +#define USBNC_USB_H1_PWR_POL (1 << 9) + +static int cm_fx6_setup_usb_host(void) +{ + int err; + + err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); + if (err) + return err; + + SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); + + return 0; +} + +static int cm_fx6_setup_usb_otg(void) +{ + int err; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); + if (err) { + printf("USB OTG pwr gpio request failed: %d\n", err); + return err; + } + + SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | + MUX_PAD_CTRL(WEAK_PULLDOWN)); + clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); + /* disable ext. charger detect, or it'll affect signal quality at dp. */ + return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); +} + +int board_ehci_hcd_init(int port) +{ + int ret; + u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); + + /* Only 1 host controller in use. port 0 is OTG & needs no attention */ + if (port != 1) + return 0; + + /* Set PWR polarity to match power switch's enable polarity */ + setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); + ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0); + if (ret) + return ret; + + udelay(10); + ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1); + if (ret) + return ret; + + mdelay(1); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port == 0) + return gpio_direction_output(SB_FX6_USB_OTG_PWR, on); + + return 0; +} +#else +static int cm_fx6_setup_usb_otg(void) { return 0; } +static int cm_fx6_setup_usb_host(void) { return 0; } +#endif + +#ifdef CONFIG_FEC_MXC +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +static int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* Ar8031 phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= ~(0x1 << 8); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), +}; + +static int handle_mac_address(void) +{ + unsigned char enetaddr[6]; + int rc; + + rc = eth_getenv_enetaddr("ethaddr", enetaddr); + if (rc) + return 0; + + rc = cl_eeprom_read_mac_addr(enetaddr); + if (rc) + return rc; + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("ethaddr", enetaddr); +} + +int board_eth_init(bd_t *bis) +{ + int err; + + err = handle_mac_address(); + if (err) + puts("No MAC address found\n"); + + SETUP_IOMUX_PADS(enet_pads); + /* phy reset */ + err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); + if (err) + printf("Etnernet NRST gpio request failed: %d\n", err); + gpio_direction_output(CM_FX6_ENET_NRST, 0); + udelay(500); + gpio_set_value(CM_FX6_ENET_NRST, 1); + enable_enet_clk(1); + return cpu_eth_init(bis); +} +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void cm_fx6_setup_gpmi_nand(void) +{ + SETUP_IOMUX_PADS(nand_pads); + /* Enable clock roots */ + enable_usdhc_clk(1, 3); + enable_usdhc_clk(1, 4); + + setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); +} +#else +static void cm_fx6_setup_gpmi_nand(void) {} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, +}; + +static enum mxc_clock usdhc_clk[3] = { + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, +}; + +int board_mmc_init(bd_t *bis) +{ + int i; + + cm_fx6_set_usdhc_iomux(); + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]); + usdhc_cfg[i].max_bus_width = 4; + fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + enable_usdhc_clk(1, i); + } + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +int cm_fx6_setup_ecspi(void) +{ + cm_fx6_set_ecspi_iomux(); + return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0"); +} +#else +int cm_fx6_setup_ecspi(void) { return 0; } +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + uint8_t enetaddr[6]; + + /* MAC addr */ + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + fdt_find_and_setprop(blob, "/fec", "local-mac-address", + enetaddr, 6, 1); + } + + return 0; +} +#endif + +int board_init(void) +{ + int ret; + + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + cm_fx6_setup_gpmi_nand(); + + ret = cm_fx6_setup_ecspi(); + if (ret) + printf("Warning: ECSPI setup failed: %d\n", ret); + + ret = cm_fx6_setup_usb_otg(); + if (ret) + printf("Warning: USB OTG setup failed: %d\n", ret); + + ret = cm_fx6_setup_usb_host(); + if (ret) + printf("Warning: USB host setup failed: %d\n", ret); + + /* + * cm-fx6 may have iSSD not assembled and in this case it has + * bypasses for a (m)SATA socket on the baseboard. The socketed + * device is not controlled by those GPIOs. So just print a warning + * if the setup fails. + */ + ret = cm_fx6_setup_issd(); + if (ret) + printf("Warning: iSSD setup failed: %d\n", ret); + + /* Warn on failure but do not abort boot */ + ret = cm_fx6_setup_i2c(); + if (ret) + printf("Warning: I2C setup failed: %d\n", ret); + + return 0; +} + +int checkboard(void) +{ + puts("Board: CM-FX6\n"); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + + switch (gd->ram_size) { + case 0x10000000: /* DDR_16BIT_256MB */ + gd->bd->bi_dram[0].size = 0x10000000; + gd->bd->bi_dram[1].size = 0; + break; + case 0x20000000: /* DDR_32BIT_512MB */ + gd->bd->bi_dram[0].size = 0x20000000; + gd->bd->bi_dram[1].size = 0; + break; + case 0x40000000: + if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ + gd->bd->bi_dram[0].size = 0x20000000; + gd->bd->bi_dram[1].size = 0x20000000; + } else { /* DDR_64BIT_1GB */ + gd->bd->bi_dram[0].size = 0x40000000; + gd->bd->bi_dram[1].size = 0; + } + break; + case 0x80000000: /* DDR_64BIT_2GB */ + gd->bd->bi_dram[0].size = 0x40000000; + gd->bd->bi_dram[1].size = 0x40000000; + break; + case 0xEFF00000: /* DDR_64BIT_4GB */ + gd->bd->bi_dram[0].size = 0x70000000; + gd->bd->bi_dram[1].size = 0x7FF00000; + break; + } +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + switch (gd->ram_size) { + case 0x10000000: + case 0x20000000: + case 0x40000000: + case 0x80000000: + break; + case 0xF0000000: + gd->ram_size -= 0x100000; + break; + default: + printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size); + return -1; + } + + return 0; +} + +u32 get_board_rev(void) +{ + return cl_eeprom_get_board_rev(); +} + +static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = { + .reg = (struct mxc_uart *)UART4_BASE, +}; + +U_BOOT_DEVICE(cm_fx6_serial) = { + .name = "serial_mxc", + .platdata = &cm_fx6_mxc_serial_plat, +}; diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c new file mode 100644 index 0000000000..59c9d1ac06 --- /dev/null +++ b/board/compulab/cm_fx6/common.c @@ -0,0 +1,85 @@ +/* + * Code used by both U-Boot and SPL for Compulab CM-FX6 + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FSL_ESDHC +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +void cm_fx6_set_usdhc_iomux(void) +{ + SETUP_IOMUX_PADS(usdhc_pads); +} + +/* CINS bit doesn't work, so always try to access the MMC card */ +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} +#endif + +#ifdef CONFIG_MXC_SPI +#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +static iomux_v3_cfg_t const ecspi_pads[] = { + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), +}; + +void cm_fx6_set_ecspi_iomux(void) +{ + SETUP_IOMUX_PADS(ecspi_pads); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1; +} +#endif diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h new file mode 100644 index 0000000000..76097f80af --- /dev/null +++ b/board/compulab/cm_fx6/common.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30) +#define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) +#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) +#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define CM_FX6_SATA_PWREN IMX_GPIO_NR(1, 28) +#define CM_FX6_SATA_VDDC_CTRL IMX_GPIO_NR(1, 30) +#define CM_FX6_SATA_LDO_EN IMX_GPIO_NR(2, 16) +#define CM_FX6_SATA_NSTANDBY1 IMX_GPIO_NR(3, 20) +#define CM_FX6_SATA_PHY_SLP IMX_GPIO_NR(3, 23) +#define CM_FX6_SATA_STBY_REQ IMX_GPIO_NR(3, 29) +#define CM_FX6_SATA_NSTANDBY2 IMX_GPIO_NR(5, 2) +#define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6) +#define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31) + + +void cm_fx6_set_usdhc_iomux(void); +void cm_fx6_set_ecspi_iomux(void); diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c new file mode 100644 index 0000000000..5b4b76f5b7 --- /dev/null +++ b/board/compulab/cm_fx6/spl.c @@ -0,0 +1,366 @@ +/* + * SPL specific code for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum ddr_config { + DDR_16BIT_256MB, + DDR_32BIT_512MB, + DDR_32BIT_1GB, + DDR_64BIT_1GB, + DDR_64BIT_2GB, + DDR_64BIT_4GB, + DDR_UNKNOWN, +}; + +/* + * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to + * Freescale QRM, but this is exactly the value used by the automatic + * calibration script and it works also in all our tests, so we leave + * it as is at this point. + */ +#define CM_FX6_DDR_IOMUX_CFG \ + .dram_sdqs0 = 0x00000038, \ + .dram_sdqs1 = 0x00000038, \ + .dram_sdqs2 = 0x00000038, \ + .dram_sdqs3 = 0x00000038, \ + .dram_sdqs4 = 0x00000038, \ + .dram_sdqs5 = 0x00000038, \ + .dram_sdqs6 = 0x00000038, \ + .dram_sdqs7 = 0x00000038, \ + .dram_dqm0 = 0x00000038, \ + .dram_dqm1 = 0x00000038, \ + .dram_dqm2 = 0x00000038, \ + .dram_dqm3 = 0x00000038, \ + .dram_dqm4 = 0x00000038, \ + .dram_dqm5 = 0x00000038, \ + .dram_dqm6 = 0x00000038, \ + .dram_dqm7 = 0x00000038, \ + .dram_cas = 0x00000038, \ + .dram_ras = 0x00000038, \ + .dram_sdclk_0 = 0x00000038, \ + .dram_sdclk_1 = 0x00000038, \ + .dram_sdcke0 = 0x00003000, \ + .dram_sdcke1 = 0x00003000, \ + .dram_reset = 0x00000038, \ + .dram_sdba2 = 0x00000000, \ + .dram_sdodt0 = 0x00000038, \ + .dram_sdodt1 = 0x00000038, + +#define CM_FX6_GPR_IOMUX_CFG \ + .grp_b0ds = 0x00000038, \ + .grp_b1ds = 0x00000038, \ + .grp_b2ds = 0x00000038, \ + .grp_b3ds = 0x00000038, \ + .grp_b4ds = 0x00000038, \ + .grp_b5ds = 0x00000038, \ + .grp_b6ds = 0x00000038, \ + .grp_b7ds = 0x00000038, \ + .grp_addds = 0x00000038, \ + .grp_ddrmode_ctl = 0x00020000, \ + .grp_ddrpke = 0x00000000, \ + .grp_ddrmode = 0x00020000, \ + .grp_ctlds = 0x00000038, \ + .grp_ddr_type = 0x000C0000, + +static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG }; +static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG }; +static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG }; +static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG }; + +static struct mx6_mmdc_calibration cm_fx6_calib_s = { + .p0_mpwldectrl0 = 0x005B0061, + .p0_mpwldectrl1 = 0x004F0055, + .p0_mpdgctrl0 = 0x0314030C, + .p0_mpdgctrl1 = 0x025C0268, + .p0_mprddlctl = 0x42464646, + .p0_mpwrdlctl = 0x36322C34, +}; + +static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = { + .cs1_mirror = 1, + .cs_density = 16, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 1, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = { + .mem_speed = 800, + .density = 4, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1800, + .trcmin = 5200, + .trasmin = 3600, + .SRT = 0, +}; + +static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset) +{ + if (reset) + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; + + switch (dram_config) { + case DDR_16BIT_256MB: + cm_fx6_sysinfo_s.dsize = 0; + cm_fx6_sysinfo_s.ncs = 1; + break; + case DDR_32BIT_512MB: + cm_fx6_sysinfo_s.dsize = 1; + cm_fx6_sysinfo_s.ncs = 1; + break; + case DDR_32BIT_1GB: + cm_fx6_sysinfo_s.dsize = 1; + cm_fx6_sysinfo_s.ncs = 2; + break; + default: + puts("Tried to setup invalid DDR configuration\n"); + hang(); + } + + mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s); + udelay(100); +} + +static struct mx6_mmdc_calibration cm_fx6_calib_q = { + .p0_mpwldectrl0 = 0x00630068, + .p0_mpwldectrl1 = 0x0068005D, + .p0_mpdgctrl0 = 0x04140428, + .p0_mpdgctrl1 = 0x037C037C, + .p0_mprddlctl = 0x3C30303A, + .p0_mpwrdlctl = 0x3A344038, + .p1_mpwldectrl0 = 0x0035004C, + .p1_mpwldectrl1 = 0x00170026, + .p1_mpdgctrl0 = 0x0374037C, + .p1_mpdgctrl1 = 0x0350032C, + .p1_mprddlctl = 0x30322A3C, + .p1_mpwrdlctl = 0x48304A3E, +}; + +static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = { + .cs_density = 16, + .cs1_mirror = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 1, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = { + .mem_speed = 1066, + .density = 4, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1324, + .trcmin = 59500, + .trasmin = 9750, + .SRT = 0, +}; + +static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset) +{ + if (reset) + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; + + cm_fx6_ddr3_cfg_q.rowaddr = 14; + switch (dram_config) { + case DDR_16BIT_256MB: + cm_fx6_sysinfo_q.dsize = 0; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_32BIT_512MB: + cm_fx6_sysinfo_q.dsize = 1; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_64BIT_1GB: + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_64BIT_2GB: + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 2; + break; + case DDR_64BIT_4GB: + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 2; + cm_fx6_ddr3_cfg_q.rowaddr = 15; + break; + default: + puts("Tried to setup invalid DDR configuration\n"); + hang(); + } + + mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q); + udelay(100); +} + +static int cm_fx6_spl_dram_init(void) +{ + unsigned long bank1_size, bank2_size; + + switch (get_cpu_type()) { + case MXC_CPU_MX6SOLO: + mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s); + + spl_mx6s_dram_init(DDR_32BIT_1GB, false); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000); + if (bank1_size == 0x20000000) { + if (bank2_size == 0x20000000) + return 0; + + spl_mx6s_dram_init(DDR_32BIT_512MB, true); + return 0; + } + + spl_mx6s_dram_init(DDR_16BIT_256MB, true); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x10000000) + return 0; + + break; + case MXC_CPU_MX6D: + case MXC_CPU_MX6Q: + mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q); + + spl_mx6q_dram_init(DDR_64BIT_4GB, false); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x80000000) + return 0; + + if (bank1_size == 0x40000000) { + bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, + 0x80000000); + if (bank2_size == 0x40000000) { + /* Don't do a full reset here */ + spl_mx6q_dram_init(DDR_64BIT_2GB, false); + } else { + spl_mx6q_dram_init(DDR_64BIT_1GB, true); + } + + return 0; + } + + spl_mx6q_dram_init(DDR_32BIT_512MB, true); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x20000000) + return 0; + + spl_mx6q_dram_init(DDR_16BIT_256MB, true); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x10000000) + return 0; + + break; + } + + return -1; +} + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void cm_fx6_setup_uart(void) +{ + SETUP_IOMUX_PADS(uart4_pads); + enable_uart_clk(1); +} + +#ifdef CONFIG_SPL_SPI_SUPPORT +static void cm_fx6_setup_ecspi(void) +{ + cm_fx6_set_ecspi_iomux(); + enable_cspi_clock(1, 0); +} +#else +static void cm_fx6_setup_ecspi(void) { } +#endif + +void board_init_f(ulong dummy) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* + * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot + * initializes DMA very early (before all board code), so the only + * opportunity we have to initialize APBHDMA clocks is in SPL. + */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); + enable_usdhc_clk(1, 2); + + arch_cpu_init(); + timer_init(); + cm_fx6_setup_ecspi(); + cm_fx6_setup_uart(); + get_clocks(); + preloader_console_init(); + gpio_direction_output(CM_FX6_GREEN_LED, 1); + if (cm_fx6_spl_dram_init()) { + puts("!!!ERROR!!! DRAM detection failed!!!\n"); + hang(); + } + + memset(__bss_start, 0, __bss_end - __bss_start); + board_init_r(NULL, 0); +} + +void spl_board_init(void) +{ + u32 boot_device = spl_boot_device(); + + if (boot_device == BOOT_DEVICE_SPI) + puts("Booting from SPI flash\n"); + else if (boot_device == BOOT_DEVICE_MMC1) + puts("Booting from MMC\n"); + else + puts("Unknown boot device\n"); +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +static struct fsl_esdhc_cfg usdhc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 4, +}; + +int board_mmc_init(bd_t *bis) +{ + cm_fx6_set_usdhc_iomux(); + + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} +#endif diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig new file mode 100644 index 0000000000..683efde764 --- /dev/null +++ b/board/compulab/cm_t335/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CM_T335 + +config SYS_BOARD + default "cm_t335" + +config SYS_VENDOR + default "compulab" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "cm_t335" + +endif diff --git a/board/compulab/cm_t335/MAINTAINERS b/board/compulab/cm_t335/MAINTAINERS new file mode 100644 index 0000000000..5fb922c68b --- /dev/null +++ b/board/compulab/cm_t335/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T335 BOARD +M: Igor Grinberg +S: Maintained +F: board/compulab/cm_t335/ +F: include/configs/cm_t335.h +F: configs/cm_t335_defconfig diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile new file mode 100644 index 0000000000..b405caaa5c --- /dev/null +++ b/board/compulab/cm_t335/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/ +# +# Author: Ilya Ledvich +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cm_t335.o +obj-$(CONFIG_SPL_BUILD) += mux.o spl.o diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c new file mode 100644 index 0000000000..9583149bed --- /dev/null +++ b/board/compulab/cm_t335/cm_t335.c @@ -0,0 +1,162 @@ +/* + * Board functions for Compulab CM-T335 board + * + * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ + * + * Author: Ilya Ledvich + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "../common/eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + gpmc_init(); + +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); +#endif + return 0; +} + +#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slave = { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = &cpsw_slave, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +/* PHY reset GPIO */ +#define GPIO_PHY_RST GPIO_PIN(3, 7) + +static void board_phy_init(void) +{ + gpio_request(GPIO_PHY_RST, "phy_rst"); + gpio_direction_output(GPIO_PHY_RST, 0); + mdelay(2); + gpio_set_value(GPIO_PHY_RST, 1); + mdelay(2); +} + +static void get_efuse_mac_addr(uchar *enetaddr) +{ + uint32_t mac_hi, mac_lo; + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + enetaddr[0] = mac_hi & 0xFF; + enetaddr[1] = (mac_hi & 0xFF00) >> 8; + enetaddr[2] = (mac_hi & 0xFF0000) >> 16; + enetaddr[3] = (mac_hi & 0xFF000000) >> 24; + enetaddr[4] = mac_lo & 0xFF; + enetaddr[5] = (mac_lo & 0xFF00) >> 8; +} + +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int handle_mac_address(void) +{ + uchar enetaddr[6]; + int rv; + + rv = eth_getenv_enetaddr("ethaddr", enetaddr); + if (rv) + return 0; + + rv = cl_eeprom_read_mac_addr(enetaddr); + if (rv) + get_efuse_mac_addr(enetaddr); + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("ethaddr", enetaddr); +} + +#define AR8051_PHY_DEBUG_ADDR_REG 0x1d +#define AR8051_PHY_DEBUG_DATA_REG 0x1e +#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 +#define AR8051_RGMII_TX_CLK_DLY 0x100 + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + const char *devname; + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + rv = handle_mac_address(); + if (rv) + printf("No MAC address found!\n"); + + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + + board_phy_init(); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + + /* + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the AR8051 PHY. Since we only support a single ethernet + * device, we only do this for the first instance. + */ + devname = miiphy_get_current_dev(); + + miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, + AR8051_DEBUG_RGMII_CLK_DLY_REG); + miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, + AR8051_RGMII_TX_CLK_DLY); + return n; +} +#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */ diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c new file mode 100644 index 0000000000..7d2beb01e5 --- /dev/null +++ b/board/compulab/cm_t335/mux.c @@ -0,0 +1,117 @@ +/* + * Pinmux configuration for Compulab CM-T335 board + * + * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ + * + * Author: Ilya Ledvich + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, + {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux eth_phy_rst_pin_mux[] = { + {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */ + {-1}, +}; + +static struct module_pin_mux status_led_pin_mux[] = { + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */ + {-1}, +}; + +void set_uart_mux_conf(void) +{ + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(uart1_pin_mux); +} + +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(eth_phy_rst_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(status_led_pin_mux); +} diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c new file mode 100644 index 0000000000..d57436445e --- /dev/null +++ b/board/compulab/cm_t335/spl.c @@ -0,0 +1,114 @@ +/* + * SPL specific code for Compulab CM-T335 board + * + * Board functions for Compulab CM-T335 board + * + * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ + * + * Author: Ilya Ledvich + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include +#include +#include +#include +#include + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41J128MJT125_RD_DQS, + .datawdsratio0 = MT41J128MJT125_WR_DQS, + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41J128MJT125_RATIO, + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd1csratio = MT41J128MJT125_RATIO, + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd2csratio = MT41J128MJT125_RATIO, + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41J128MJT125_EMIF_SDCFG, + .ref_ctrl = MT41J128MJT125_EMIF_SDREF, + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, + .zq_config = MT41J128MJT125_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +const struct dpll_params dpll_ddr = { +/* M N M2 M3 M4 M5 M6 */ + 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +static void probe_sdram_size(long size) +{ + switch (size) { + case SZ_512M: + ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; + break; + case SZ_256M: + ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; + break; + case SZ_128M: + ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; + break; + default: + puts("Failed configuring DRAM, resetting...\n\n"); + reset_cpu(0); + } + debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); + config_ddr(303, &ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} + +void sdram_init(void) +{ + long size = SZ_1G; + + do { + size = size / 2; + probe_sdram_size(size); + } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); + + return; +} diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds new file mode 100644 index 0000000000..627583668a --- /dev/null +++ b/board/compulab/cm_t335/u-boot.lds @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/compulab/cm_t335/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} diff --git a/board/compulab/cm_t35/Kconfig b/board/compulab/cm_t35/Kconfig new file mode 100644 index 0000000000..d87741f146 --- /dev/null +++ b/board/compulab/cm_t35/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM_T35 + +config SYS_BOARD + default "cm_t35" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "cm_t35" + +endif diff --git a/board/compulab/cm_t35/MAINTAINERS b/board/compulab/cm_t35/MAINTAINERS new file mode 100644 index 0000000000..fc5d73f04c --- /dev/null +++ b/board/compulab/cm_t35/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T35 BOARD +M: Igor Grinberg +S: Maintained +F: board/compulab/cm_t35/ +F: include/configs/cm_t35.h +F: configs/cm_t35_defconfig diff --git a/board/compulab/cm_t35/Makefile b/board/compulab/cm_t35/Makefile index 6d07947d51..ede250b524 100644 --- a/board/compulab/cm_t35/Makefile +++ b/board/compulab/cm_t35/Makefile @@ -7,26 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o -COBJS-$(CONFIG_LCD) += display.o - -COBJS := cm_t35.o leds.o $(COBJS-y) - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += cm_t35.o diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 3caa5be845..43463d5b47 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -19,12 +19,11 @@ #include #include #include -#include #include -#include #include #include +#include #include #include #include @@ -33,7 +32,8 @@ #include #include -#include "eeprom.h" +#include "../common/common.h" +#include "../common/eeprom.h" DECLARE_GLOBAL_DATA_PTR; @@ -43,86 +43,28 @@ const omap3_sysinfo sysinfo = { "NAND", }; -static u32 gpmc_net_config[GPMC_MAX_REG] = { - NET_GPMC_CONFIG1, - NET_GPMC_CONFIG2, - NET_GPMC_CONFIG3, - NET_GPMC_CONFIG4, - NET_GPMC_CONFIG5, - NET_GPMC_CONFIG6, - 0 -}; - -static u32 gpmc_nand_config[GPMC_MAX_REG] = { - SMNAND_GPMC_CONFIG1, - SMNAND_GPMC_CONFIG2, - SMNAND_GPMC_CONFIG3, - SMNAND_GPMC_CONFIG4, - SMNAND_GPMC_CONFIG5, - SMNAND_GPMC_CONFIG6, - 0, -}; - -#ifdef CONFIG_LCD -#ifdef CONFIG_CMD_NAND -static int splash_load_from_nand(u32 bmp_load_addr) -{ - struct bmp_header *bmp_hdr; - int res, splash_screen_nand_offset = 0x100000; - size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); - - if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) - goto splash_address_too_high; - - res = nand_read_skip_bad(&nand_info[nand_curr_device], - splash_screen_nand_offset, &bmp_header_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - if (res < 0) - return res; - - bmp_hdr = (struct bmp_header *)bmp_load_addr; - bmp_size = le32_to_cpu(bmp_hdr->file_size); - - if (bmp_load_addr + bmp_size >= gd->start_addr_sp) - goto splash_address_too_high; - - return nand_read_skip_bad(&nand_info[nand_curr_device], - splash_screen_nand_offset, &bmp_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - -splash_address_too_high: - printf("Error: splashimage address too high. Data overwrites U-Boot " - "and/or placed beyond DRAM boundaries.\n"); - - return -1; -} -#else -static inline int splash_load_from_nand(void) +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) { - return -1; + timings->mr = MICRON_V_MR_165; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } -#endif /* CONFIG_CMD_NAND */ +#endif + +#define CM_T35_SPLASH_NAND_OFFSET 0x100000 int splash_screen_prepare(void) { - char *env_splashimage_value; - u32 bmp_load_addr; - - env_splashimage_value = getenv("splashimage"); - if (env_splashimage_value == NULL) - return -1; - - bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); - if (bmp_load_addr == 0) { - printf("Error: bad splashimage address specified\n"); - return -1; - } - - return splash_load_from_nand(bmp_load_addr); + return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET); } -#endif /* CONFIG_LCD */ /* * Routine: board_init @@ -132,9 +74,6 @@ int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], - CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); - /* board id for Linux */ if (get_cpu_family() == CPU_OMAP34XX) gd->bd->bi_arch_number = MACH_TYPE_CM_T35; @@ -151,34 +90,18 @@ int board_init(void) return 0; } -static u32 cm_t3x_rev; - /* * Routine: get_board_rev * Description: read system revision */ u32 get_board_rev(void) { - if (!cm_t3x_rev) - cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); - - return cm_t3x_rev; + return cl_eeprom_get_board_rev(); }; -/* - * Routine: misc_init_r - * Description: display die ID - */ int misc_init_r(void) { - u32 board_rev = get_board_rev(); - u32 rev_major = board_rev / 100; - u32 rev_minor = board_rev - (rev_major * 100); - - if ((rev_minor / 10) * 10 == rev_minor) - rev_minor = rev_minor / 10; - - printf("PCB: %u.%u\n", rev_major, rev_minor); + cl_print_pcb_info(); dieid_num_r(); return 0; @@ -268,6 +191,9 @@ static void cm_t3x_set_common_muxconf(void) /* DVI enable */ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ + /* DataImage backlight */ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ + /* CM-T3x Ethernet */ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ @@ -362,7 +288,7 @@ static void cm_t3x_set_common_muxconf(void) MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ @@ -374,6 +300,15 @@ static void cm_t3x_set_common_muxconf(void) MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ + + /* SPI */ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ + + /* display controls */ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ } static void cm_t35_set_muxconf(void) @@ -428,7 +363,9 @@ void set_muxconf_regs(void) cm_t3730_set_muxconf(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +#define SB_T35_WP_GPIO 59 + int board_mmc_getcd(struct mmc *mmc) { u8 val; @@ -441,41 +378,23 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1, 59); + return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO); } #endif -/* - * Routine: setup_net_chip_gmpc - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip_gmpc(void) +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) { - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], - CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], - SB_T35_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); + twl4030_power_mmc_init(0); } +#endif -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX /* * Routine: reset_net_chip * Description: reset the Ethernet controller via TPS65930 GPIO */ -static void reset_net_chip(void) +static int cm_t3x_reset_net_chip(int gpio) { /* Set GPIO1 of TPS65930 as output */ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, @@ -490,9 +409,10 @@ static void reset_net_chip(void) twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 0x02); mdelay(1); + return 0; } #else -static inline void reset_net_chip(void) {} +static inline int cm_t3x_reset_net_chip(int gpio) { return 0; } #endif #ifdef CONFIG_SMC911X @@ -509,7 +429,7 @@ static int handle_mac_address(void) if (rc) return 0; - rc = cm_t3x_eeprom_read_mac_addr(enetaddr); + rc = cl_eeprom_read_mac_addr(enetaddr); if (rc) return rc; @@ -519,7 +439,6 @@ static int handle_mac_address(void) return eth_setenv_enetaddr("ethaddr", enetaddr); } - /* * Routine: board_eth_init * Description: initialize module and base-board Ethernet chips @@ -528,18 +447,16 @@ int board_eth_init(bd_t *bis) { int rc = 0, rc1 = 0; - setup_net_chip_gmpc(); - reset_net_chip(); - rc1 = handle_mac_address(); if (rc1) printf("No MAC address found! "); - rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); + rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE, + cm_t3x_reset_net_chip, -EINVAL); if (rc1 > 0) rc++; - rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); + rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL); if (rc1 > 0) rc++; @@ -547,16 +464,6 @@ int board_eth_init(bd_t *bis) } #endif -void __weak get_board_serial(struct tag_serialnr *serialnr) -{ - /* - * This corresponds to what happens when we can communicate with the - * eeprom but don't get a valid board serial value. - */ - serialnr->low = 0; - serialnr->high = 0; -}; - #ifdef CONFIG_USB_EHCI_OMAP struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, @@ -565,21 +472,13 @@ struct omap_usbhs_board_data usbhs_bdata = { }; #define SB_T35_USB_HUB_RESET_GPIO 167 -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { u8 val; int offset; - if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { - printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", - SB_T35_USB_HUB_RESET_GPIO); - return -1; - } - - gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); - udelay(10); - gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); - udelay(1000); + cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); @@ -591,12 +490,12 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); udelay(1); - return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); } int ehci_hcd_stop(void) { + cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); return omap_ehci_hcd_stop(); } - #endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t35/display.c b/board/compulab/cm_t35/display.c deleted file mode 100644 index fae8d95403..0000000000 --- a/board/compulab/cm_t35/display.c +++ /dev/null @@ -1,406 +0,0 @@ -/* - * (C) Copyright 2012 - 2013 CompuLab, Ltd. - * - * Authors: Nikita Kiryanov - * - * Parsing code based on linux/drivers/video/pxafb.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -enum display_type { - NONE, - DVI, - DVI_CUSTOM, -}; - -#define CMAP_ADDR 0x80100000 - -/* - * The frame buffer is allocated before we have the chance to parse user input. - * To make sure enough memory is allocated for all resolutions, we define - * vl_{col | row} to the maximal resolution supported by OMAP3. - */ -vidinfo_t panel_info = { - .vl_col = 1400, - .vl_row = 1050, - .vl_bpix = LCD_BPP, - .cmap = (ushort *)CMAP_ADDR, -}; - -static struct panel_config panel_cfg; -static enum display_type lcd_def; - -/* - * A note on DVI presets; - * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can - * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to - * support two BMP types with one setting. - */ -static const struct panel_config preset_dvi_640X480 = { - .lcd_size = PANEL_LCD_SIZE(640, 480), - .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), - .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), - .divisor = 12 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_800X600 = { - .lcd_size = PANEL_LCD_SIZE(800, 600), - .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), - .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), - .divisor = 8 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_1024X768 = { - .lcd_size = PANEL_LCD_SIZE(1024, 768), - .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), - .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), - .divisor = 5 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_1152X864 = { - .lcd_size = PANEL_LCD_SIZE(1152, 864), - .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), - .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), - .divisor = 3 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_1280X960 = { - .lcd_size = PANEL_LCD_SIZE(1280, 960), - .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), - .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), - .divisor = 3 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_1280X1024 = { - .lcd_size = PANEL_LCD_SIZE(1280, 1024), - .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), - .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), - .divisor = 3 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -/* - * set_resolution_params() - * - * Due to usage of multiple display related APIs resolution data is located in - * more than one place. This function updates them all. - */ -static void set_resolution_params(int x, int y) -{ - panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y); - panel_info.vl_col = x; - panel_info.vl_row = y; - lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; -} - -static void set_preset(const struct panel_config preset, int x_res, int y_res) -{ - panel_cfg = preset; - set_resolution_params(x_res, y_res); -} - -static enum display_type set_dvi_preset(const struct panel_config preset, - int x_res, int y_res) -{ - set_preset(preset, x_res, y_res); - return DVI; -} - -/* - * parse_mode() - parse the mode parameter of custom lcd settings - * - * @mode: x - * - * Returns -1 on error, 0 on success. - */ -static int parse_mode(const char *mode) -{ - unsigned int modelen = strlen(mode); - int res_specified = 0; - unsigned int xres = 0, yres = 0; - int yres_specified = 0; - int i; - - for (i = modelen - 1; i >= 0; i--) { - switch (mode[i]) { - case 'x': - if (!yres_specified) { - yres = simple_strtoul(&mode[i + 1], NULL, 0); - yres_specified = 1; - } else { - goto done_parsing; - } - - break; - case '0' ... '9': - break; - default: - goto done_parsing; - } - } - - if (i < 0 && yres_specified) { - xres = simple_strtoul(mode, NULL, 0); - res_specified = 1; - } - -done_parsing: - if (res_specified) { - set_resolution_params(xres, yres); - } else { - printf("LCD: invalid mode: %s\n", mode); - return -1; - } - - return 0; -} - -#define PIXEL_CLK_NUMERATOR (26 * 432 / 39) -/* - * parse_pixclock() - Parse the pixclock parameter of custom lcd settings - * - * @pixclock: the desired pixel clock - * - * Returns -1 on error, 0 on success. - * - * Handling the pixel_clock: - * - * Pixel clock is defined in the OMAP35x TRM as follows: - * pixel_clock = - * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) / - * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] * - * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1)) - * - * In practice, this means that in order to set the - * divisor for the desired pixel clock one needs to - * solve the following equation: - * - * 26 * 432 / (39 * ) = DSS.DISPC_DIVISOR[6:0] - * - * NOTE: the explicit equation above is reduced. Do not - * try to infer anything from these numbers. - */ -static int parse_pixclock(char *pixclock) -{ - int divisor, pixclock_val; - char *pixclk_start = pixclock; - - pixclock_val = simple_strtoul(pixclock, &pixclock, 10); - divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val); - /* 0 and 1 are illegal values for PCD */ - if (divisor <= 1) - divisor = 2; - - panel_cfg.divisor = divisor | (1 << 16); - if (pixclock[0] != '\0') { - printf("LCD: invalid value for pixclock:%s\n", pixclk_start); - return -1; - } - - return 0; -} - -/* - * parse_setting() - parse a single setting of custom lcd parameters - * - * @setting: The custom lcd setting : - * - * Returns -1 on failure, 0 on success. - */ -static int parse_setting(char *setting) -{ - int num_val; - char *setting_start = setting; - - if (!strncmp(setting, "mode:", 5)) { - return parse_mode(setting + 5); - } else if (!strncmp(setting, "pixclock:", 9)) { - return parse_pixclock(setting + 9); - } else if (!strncmp(setting, "left:", 5)) { - num_val = simple_strtoul(setting + 5, &setting, 0); - panel_cfg.timing_h |= DSS_HBP(num_val); - } else if (!strncmp(setting, "right:", 6)) { - num_val = simple_strtoul(setting + 6, &setting, 0); - panel_cfg.timing_h |= DSS_HFP(num_val); - } else if (!strncmp(setting, "upper:", 6)) { - num_val = simple_strtoul(setting + 6, &setting, 0); - panel_cfg.timing_v |= DSS_VBP(num_val); - } else if (!strncmp(setting, "lower:", 6)) { - num_val = simple_strtoul(setting + 6, &setting, 0); - panel_cfg.timing_v |= DSS_VFP(num_val); - } else if (!strncmp(setting, "hsynclen:", 9)) { - num_val = simple_strtoul(setting + 9, &setting, 0); - panel_cfg.timing_h |= DSS_HSW(num_val); - } else if (!strncmp(setting, "vsynclen:", 9)) { - num_val = simple_strtoul(setting + 9, &setting, 0); - panel_cfg.timing_v |= DSS_VSW(num_val); - } else if (!strncmp(setting, "hsync:", 6)) { - if (simple_strtoul(setting + 6, &setting, 0) == 0) - panel_cfg.pol_freq |= DSS_IHS; - else - panel_cfg.pol_freq &= ~DSS_IHS; - } else if (!strncmp(setting, "vsync:", 6)) { - if (simple_strtoul(setting + 6, &setting, 0) == 0) - panel_cfg.pol_freq |= DSS_IVS; - else - panel_cfg.pol_freq &= ~DSS_IVS; - } else if (!strncmp(setting, "outputen:", 9)) { - if (simple_strtoul(setting + 9, &setting, 0) == 0) - panel_cfg.pol_freq |= DSS_IEO; - else - panel_cfg.pol_freq &= ~DSS_IEO; - } else if (!strncmp(setting, "pixclockpol:", 12)) { - if (simple_strtoul(setting + 12, &setting, 0) == 0) - panel_cfg.pol_freq |= DSS_IPC; - else - panel_cfg.pol_freq &= ~DSS_IPC; - } else if (!strncmp(setting, "active", 6)) { - panel_cfg.panel_type = ACTIVE_DISPLAY; - return 0; /* Avoid sanity check below */ - } else if (!strncmp(setting, "passive", 7)) { - panel_cfg.panel_type = PASSIVE_DISPLAY; - return 0; /* Avoid sanity check below */ - } else if (!strncmp(setting, "display:", 8)) { - if (!strncmp(setting + 8, "dvi", 3)) { - lcd_def = DVI_CUSTOM; - return 0; /* Avoid sanity check below */ - } - } else { - printf("LCD: unknown option %s\n", setting_start); - return -1; - } - - if (setting[0] != '\0') { - printf("LCD: invalid value for %s\n", setting_start); - return -1; - } - - return 0; -} - -/* - * env_parse_customlcd() - parse custom lcd params from an environment variable. - * - * @custom_lcd_params: The environment variable containing the lcd params. - * - * Returns -1 on failure, 0 on success. - */ -static int parse_customlcd(char *custom_lcd_params) -{ - char params_cpy[160]; - char *setting; - - strncpy(params_cpy, custom_lcd_params, 160); - setting = strtok(params_cpy, ","); - while (setting) { - if (parse_setting(setting) < 0) - return -1; - - setting = strtok(NULL, ","); - } - - /* Currently we don't support changing this via custom lcd params */ - panel_cfg.data_lines = LCD_INTERFACE_24_BIT; - panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */ - - return 0; -} - -/* - * env_parse_displaytype() - parse display type. - * - * Parses the environment variable "displaytype", which contains the - * name of the display type or preset, in which case it applies its - * configurations. - * - * Returns the type of display that was specified. - */ -static enum display_type env_parse_displaytype(char *displaytype) -{ - if (!strncmp(displaytype, "dvi640x480", 10)) - return set_dvi_preset(preset_dvi_640X480, 640, 480); - else if (!strncmp(displaytype, "dvi800x600", 10)) - return set_dvi_preset(preset_dvi_800X600, 800, 600); - else if (!strncmp(displaytype, "dvi1024x768", 11)) - return set_dvi_preset(preset_dvi_1024X768, 1024, 768); - else if (!strncmp(displaytype, "dvi1152x864", 11)) - return set_dvi_preset(preset_dvi_1152X864, 1152, 864); - else if (!strncmp(displaytype, "dvi1280x960", 11)) - return set_dvi_preset(preset_dvi_1280X960, 1280, 960); - else if (!strncmp(displaytype, "dvi1280x1024", 12)) - return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024); - - return NONE; -} - -void lcd_ctrl_init(void *lcdbase) -{ - struct prcm *prcm = (struct prcm *)PRCM_BASE; - char *custom_lcd; - char *displaytype = getenv("displaytype"); - - if (displaytype == NULL) - return; - - lcd_def = env_parse_displaytype(displaytype); - /* If we did not recognize the preset, check if it's an env variable */ - if (lcd_def == NONE) { - custom_lcd = getenv(displaytype); - if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0) - return; - } - - panel_cfg.frame_buffer = lcdbase; - omap3_dss_panel_config(&panel_cfg); - /* - * Pixel clock is defined with many divisions and only few - * multiplications of the system clock. Since DSS FCLK divisor is set - * to 16 by default, we need to set it to a smaller value, like 3 - * (chosen via trial and error). - */ - clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); -} - -void lcd_enable(void) -{ - if (lcd_def == DVI || lcd_def == DVI_CUSTOM) { - gpio_direction_output(54, 0); /* Turn on DVI */ - omap3_dss_enable(); - } -} - -void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {} diff --git a/board/compulab/cm_t35/eeprom.c b/board/compulab/cm_t35/eeprom.c deleted file mode 100644 index df91acd4a7..0000000000 --- a/board/compulab/cm_t35/eeprom.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2011 CompuLab, Ltd. - * - * Authors: Nikita Kiryanov - * Igor Grinberg - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#define EEPROM_LAYOUT_VER_OFFSET 44 -#define BOARD_SERIAL_OFFSET 20 -#define BOARD_SERIAL_OFFSET_LEGACY 8 -#define BOARD_REV_OFFSET 0 -#define BOARD_REV_OFFSET_LEGACY 6 -#define BOARD_REV_SIZE 2 -#define MAC_ADDR_OFFSET 4 -#define MAC_ADDR_OFFSET_LEGACY 0 - -#define LAYOUT_INVALID 0 -#define LAYOUT_LEGACY 0xff - -static int eeprom_layout; /* Implicitly LAYOUT_INVALID */ - -static int cm_t3x_eeprom_read(uint offset, uchar *buf, int len) -{ - return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); -} - -static int eeprom_setup_layout(void) -{ - int res; - - if (eeprom_layout != LAYOUT_INVALID) - return 0; - - res = cm_t3x_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, - (uchar *)&eeprom_layout, 1); - if (res) { - eeprom_layout = LAYOUT_INVALID; - return res; - } - - if (eeprom_layout == 0 || eeprom_layout >= 0x20) - eeprom_layout = LAYOUT_LEGACY; - - return 0; -} - -void get_board_serial(struct tag_serialnr *serialnr) -{ - u32 serial[2]; - uint offset; - - memset(serialnr, 0, sizeof(*serialnr)); - if (eeprom_setup_layout()) - return; - - offset = (eeprom_layout != LAYOUT_LEGACY) ? - BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY; - if (cm_t3x_eeprom_read(offset, (uchar *)serial, 8)) - return; - - if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) { - serialnr->low = serial[0]; - serialnr->high = serial[1]; - } -} - -/* - * Routine: cm_t3x_eeprom_read_mac_addr - * Description: read mac address and store it in buf. - */ -int cm_t3x_eeprom_read_mac_addr(uchar *buf) -{ - uint offset; - - if (eeprom_setup_layout()) - return 0; - - offset = (eeprom_layout != LAYOUT_LEGACY) ? - MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY; - return cm_t3x_eeprom_read(offset, buf, 6); -} - -/* - * Routine: cm_t3x_eeprom_get_board_rev - * Description: read system revision from eeprom - */ -u32 cm_t3x_eeprom_get_board_rev(void) -{ - u32 rev = 0; - char str[5]; /* Legacy representation can contain at most 4 digits */ - uint offset = BOARD_REV_OFFSET_LEGACY; - - if (eeprom_setup_layout()) - return 0; - - if (eeprom_layout != LAYOUT_LEGACY) - offset = BOARD_REV_OFFSET; - - if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) - return 0; - - /* - * Convert legacy syntactic representation to semantic - * representation. i.e. for rev 1.00: 0x100 --> 0x64 - */ - if (eeprom_layout == LAYOUT_LEGACY) { - sprintf(str, "%x", rev); - rev = simple_strtoul(str, NULL, 10); - } - - return rev; -}; diff --git a/board/compulab/cm_t35/eeprom.h b/board/compulab/cm_t35/eeprom.h deleted file mode 100644 index 02ffbb1a99..0000000000 --- a/board/compulab/cm_t35/eeprom.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2011 CompuLab, Ltd. - * - * Authors: Nikita Kiryanov - * Igor Grinberg - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EEPROM_ -#define _EEPROM_ - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C -int cm_t3x_eeprom_read_mac_addr(uchar *buf); -u32 cm_t3x_eeprom_get_board_rev(void); -#else -static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf) -{ - return 1; -} -static inline u32 cm_t3x_eeprom_get_board_rev(void) -{ - return 0; -} -#endif - -#endif diff --git a/board/compulab/cm_t35/leds.c b/board/compulab/cm_t35/leds.c deleted file mode 100644 index 7e2803e3b8..0000000000 --- a/board/compulab/cm_t35/leds.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2011 - 2013 CompuLab, Ltd. - * - * Author: Igor Grinberg - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -static unsigned int leds[] = { GREEN_LED_GPIO }; - -void __led_init(led_id_t mask, int state) -{ - if (gpio_request(leds[mask], "") != 0) { - printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]); - return; - } - - gpio_direction_output(leds[mask], 0); -} - -void __led_set(led_id_t mask, int state) -{ - gpio_set_value(leds[mask], state == STATUS_LED_ON); -} - -void __led_toggle(led_id_t mask) -{ - gpio_set_value(leds[mask], !gpio_get_value(leds[mask])); -} diff --git a/board/compulab/cm_t3517/Kconfig b/board/compulab/cm_t3517/Kconfig new file mode 100644 index 0000000000..2f5473d76a --- /dev/null +++ b/board/compulab/cm_t3517/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM_T3517 + +config SYS_BOARD + default "cm_t3517" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "cm_t3517" + +endif diff --git a/board/compulab/cm_t3517/MAINTAINERS b/board/compulab/cm_t3517/MAINTAINERS new file mode 100644 index 0000000000..fbb6882138 --- /dev/null +++ b/board/compulab/cm_t3517/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T3517 BOARD +M: Igor Grinberg +S: Maintained +F: board/compulab/cm_t3517/ +F: include/configs/cm_t3517.h +F: configs/cm_t3517_defconfig diff --git a/board/compulab/cm_t3517/Makefile b/board/compulab/cm_t3517/Makefile new file mode 100644 index 0000000000..4f0db01e37 --- /dev/null +++ b/board/compulab/cm_t3517/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 CompuLab, Ltd. +# +# Authors: Igor Grinberg +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cm_t3517.o mux.o diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c new file mode 100644 index 0000000000..cac1ad9ef1 --- /dev/null +++ b/board/compulab/cm_t3517/cm_t3517.c @@ -0,0 +1,231 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. + * + * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/common.h" +#include "../common/eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "CM-T3517 board", + "NAND 128/512M", +}; + +#ifdef CONFIG_USB_MUSB_AM35X +static struct musb_hdrc_config cm_t3517_musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +static struct omap_musb_board_data cm_t3517_musb_board_data = { + .set_phy_power = am35x_musb_phy_power, + .clear_irq = am35x_musb_clear_irq, + .reset = am35x_musb_reset, +}; + +static struct musb_hdrc_platform_data cm_t3517_musb_pdata = { +#if defined(CONFIG_MUSB_HOST) + .mode = MUSB_HOST, +#elif defined(CONFIG_MUSB_GADGET) + .mode = MUSB_PERIPHERAL, +#else +#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET" +#endif + .config = &cm_t3517_musb_config, + .power = 250, + .platform_ops = &am35x_ops, + .board_data = &cm_t3517_musb_board_data, +}; + +static void cm_t3517_musb_init(void) +{ + /* + * Set up USB clock/mode in the DEVCONF2 register. + * USB2.0 PHY reference clock is 13 MHz + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE, + CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | + CONF2_VBDTCTEN | CONF2_DATPOL); + + if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data, + (void *)AM35XX_IPSS_USBOTGSS_BASE)) + printf("Failed initializing AM35x MUSB!\n"); +} +#else +static inline void am3517_evm_musb_init(void) {} +#endif + +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif + + cm_t3517_musb_init(); + + return 0; +} + +int misc_init_r(void) +{ + cl_print_pcb_info(); + dieid_num_r(); + + return 0; +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +#define SB_T35_CD_GPIO 144 +#define SB_T35_WP_GPIO 59 + +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO); +} +#endif + +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONTROL_EFUSE_EMAC_LSB 0x48002380 +#define CONTROL_EFUSE_EMAC_MSB 0x48002384 + +static int am3517_get_efuse_enetaddr(u8 *enetaddr) +{ + u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB); + u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB); + + enetaddr[0] = (u8)((msb >> 16) & 0xff); + enetaddr[1] = (u8)((msb >> 8) & 0xff); + enetaddr[2] = (u8)(msb & 0xff); + enetaddr[3] = (u8)((lsb >> 16) & 0xff); + enetaddr[4] = (u8)((lsb >> 8) & 0xff); + enetaddr[5] = (u8)(lsb & 0xff); + + return is_valid_ether_addr(enetaddr); +} + +static inline int cm_t3517_init_emac(bd_t *bis) +{ + int ret = cpu_eth_init(bis); + + if (ret > 0) + return ret; + + printf("Failed initializing EMAC! "); + return 0; +} +#else /* !CONFIG_DRIVER_TI_EMAC */ +static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; } +static inline int cm_t3517_init_emac(bd_t *bis) { return 0; } +#endif /* CONFIG_DRIVER_TI_EMAC */ + +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int cm_t3517_handle_mac_address(void) +{ + unsigned char enetaddr[6]; + int ret; + + ret = eth_getenv_enetaddr("ethaddr", enetaddr); + if (ret) + return 0; + + ret = cl_eeprom_read_mac_addr(enetaddr); + if (ret) { + ret = am3517_get_efuse_enetaddr(enetaddr); + if (ret) + return ret; + } + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("ethaddr", enetaddr); +} + +#define SB_T35_ETH_RST_GPIO 164 + +/* + * Routine: board_eth_init + * Description: initialize module and base-board Ethernet chips + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0, rc1 = 0; + + rc1 = cm_t3517_handle_mac_address(); + if (rc1) + printf("No MAC address found! "); + + rc1 = cm_t3517_init_emac(bis); + if (rc1 > 0) + rc++; + + rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE, + NULL, SB_T35_ETH_RST_GPIO); + if (rc1 > 0) + rc++; + + return rc; +} + +#ifdef CONFIG_USB_EHCI_OMAP +static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +#define CM_T3517_USB_HUB_RESET_GPIO 152 +#define SB_T35_USB_HUB_RESET_GPIO 98 + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst"); + cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); + + return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO); + cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); + + return omap_ehci_hcd_stop(); +} +#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t3517/mux.c b/board/compulab/cm_t3517/mux.c new file mode 100644 index 0000000000..88ce2cc2e6 --- /dev/null +++ b/board/compulab/cm_t3517/mux.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. + * + * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void set_muxconf_regs(void) +{ + /* SDRC */ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); + + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); + + /* SB-T35 Ethernet */ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); + /* DVI enable */ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ + /* DataImage backlight */ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ + + /* SB-T35 SD/MMC WP GPIO59 */ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); + /* SB-T35 Audio Enable GPIO61 */ + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); + /* SB-T35 Ethernet IRQ GPIO65 */ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ + + /* UART3 Console */ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); + /* RTC V3020 nCS GPIO163 */ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ + /* SB-T35 Ethernet nRESET GPIO164 */ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ + + /* SB-T35 SD/MMC CD GPIO144 */ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ + /* WIFI nRESET GPIO145 */ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ + /* USB1 PHY Reset GPIO 146 */ + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ + /* USB2 PHY Reset GPIO 147 */ + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ + + /* MMC1 */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); + + /* DSS */ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); + + /* I2C */ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); + + /* SB-T35 USB HUB Reset GPIO98 */ + MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ + /* CM-T3517 USB HUB Reset GPIO152 */ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ + + /* RMII */ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(RMII_MDIO_CLK), (M0)); + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); + MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); + MUX_VAL(CP(RMII_TXEN), (IDIS | M0)); + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0)); + + /* Green LED GPIO186 */ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ + + /* SPI */ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ + /* LCD reset GPIO157 */ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ + + /* RTC V3020 CS Enable GPIO160 */ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ + /* SB-T35 LVDS Transmitter SHDN GPIO162 */ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/ + + /* USB0 - mUSB */ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); + /* USB1 EHCI */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ + /* USB2 EHCI */ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + + /* SYS_BOOT */ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ +} diff --git a/board/compulab/cm_t54/Kconfig b/board/compulab/cm_t54/Kconfig new file mode 100644 index 0000000000..52d38804df --- /dev/null +++ b/board/compulab/cm_t54/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM_T54 + +config SYS_BOARD + default "cm_t54" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "cm_t54" + +endif diff --git a/board/compulab/cm_t54/MAINTAINERS b/board/compulab/cm_t54/MAINTAINERS new file mode 100644 index 0000000000..461fe098c0 --- /dev/null +++ b/board/compulab/cm_t54/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T54 BOARD +M: Dmitry Lifshitz +S: Maintained +F: board/compulab/cm_t54/ +F: include/configs/cm_t54.h +F: configs/cm_t54_defconfig diff --git a/board/compulab/cm_t54/Makefile b/board/compulab/cm_t54/Makefile new file mode 100644 index 0000000000..298ddd2d1d --- /dev/null +++ b/board/compulab/cm_t54/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2014 Compulab Ltd - http://compulab.co.il/ +# +# Author: Dmitry Lifshitz +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cm_t54.o +obj-$(CONFIG_SPL_BUILD) += mux.o spl.o diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c new file mode 100644 index 0000000000..2c2530ab3f --- /dev/null +++ b/board/compulab/cm_t54/cm_t54.c @@ -0,0 +1,259 @@ +/* + * Board functions for Compulab CM-T54 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Dmitry Lifshitz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "../common/eeprom.h" + +#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) +#define DIE_ID_REG_OFFSET 0x200 + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_SPL_BUILD) +inline void set_muxconf_regs_essential(void){}; +#endif + +const struct omap_sysinfo sysinfo = { + "Board: CM-T54\n" +}; + +/* + * Routine: board_init + * Description: hardware init. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +/* + * Routine: cm_t54_palmas_regulator_set + * Description: select voltage and turn on/off Palmas PMIC regulator. + */ +static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval) +{ + int err; + + /* Setup voltage */ + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, vreg, vval); + if (err) { + printf("cm_t54: could not set regulator 0x%02x voltage : %d\n", + vreg, err); + return err; + } + + /* Turn on/off regulator */ + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, creg, cval); + if (err) { + printf("cm_t54: could not turn on/off regulator 0x%02x : %d\n", + creg, err); + return err; + } + + return 0; +} + +/* + * Routine: mmc_get_env_part + * Description: setup environment storage device partition. + */ +#ifdef CONFIG_SYS_MMC_ENV_PART +uint mmc_get_env_part(struct mmc *mmc) +{ + u32 bootmode = gd->arch.omap_boot_params.omap_bootmode; + uint bootpart = CONFIG_SYS_MMC_ENV_PART; + + /* + * If booted from eMMC boot partition then force eMMC + * FIRST boot partition to be env storage + */ + if (bootmode == BOOT_DEVICE_MMC2) + bootpart = 1; + + return bootpart; +} +#endif + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +#define SB_T54_CD_GPIO 228 +#define SB_T54_WP_GPIO 229 + +int board_mmc_init(bd_t *bis) +{ + int ret0, ret1; + + ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO); + if (ret0) + printf("cm_t54: failed to initialize mmc0\n"); + + ret1 = omap_mmc_init(1, 0, 0, -1, -1); + if (ret1) + printf("cm_t54: failed to initialize mmc1\n"); + + if (ret0 && ret1) + return -1; + + return 0; +} +#endif + +#ifdef CONFIG_USB_HOST_ETHER + +int ft_board_setup(void *blob, bd_t *bd) +{ + uint8_t enetaddr[6]; + + /* MAC addr */ + if (eth_getenv_enetaddr("usbethaddr", enetaddr)) { + fdt_find_and_setprop(blob, "/smsc95xx@0", "mac-address", + enetaddr, 6, 1); + } + + return 0; +} + +static void generate_mac_addr(uint8_t *enetaddr) +{ + int reg; + + reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET; + + /* + * create a fake MAC address from the processor ID code. + * first byte is 0x02 to signify locally administered. + */ + enetaddr[0] = 0x02; + enetaddr[1] = readl(reg + 0x10) & 0xff; + enetaddr[2] = readl(reg + 0xC) & 0xff; + enetaddr[3] = readl(reg + 0x8) & 0xff; + enetaddr[4] = readl(reg) & 0xff; + enetaddr[5] = (readl(reg) >> 8) & 0xff; +} + +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int handle_mac_address(void) +{ + uint8_t enetaddr[6]; + int ret; + + ret = eth_getenv_enetaddr("usbethaddr", enetaddr); + if (ret) + return 0; + + ret = cl_eeprom_read_mac_addr(enetaddr); + if (ret || !is_valid_ether_addr(enetaddr)) + generate_mac_addr(enetaddr); + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("usbethaddr", enetaddr); +} + +int board_eth_init(bd_t *bis) +{ + return handle_mac_address(); +} +#endif + +#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, + .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, +}; + +static void setup_host_clocks(bool enable) +{ + int usbhost_clk = OPTFCLKEN_HSIC60M_P3_CLK | + OPTFCLKEN_HSIC480M_P3_CLK | + OPTFCLKEN_HSIC60M_P2_CLK | + OPTFCLKEN_HSIC480M_P2_CLK | + OPTFCLKEN_UTMI_P3_CLK | + OPTFCLKEN_UTMI_P2_CLK; + + int usbtll_clk = OPTFCLKEN_USB_CH1_CLK_ENABLE | + OPTFCLKEN_USB_CH2_CLK_ENABLE; + + int usbhub_clk = CKOBUFFER_CLK_ENABLE_MASK; + + if (enable) { + /* Enable port 2 and 3 clocks*/ + setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk); + /* Enable port 2 and 3 usb host ports tll clocks*/ + setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk); + /* Request FREF_XTAL_CLK clock for HSIC USB Hub */ + setbits_le32((*ctrl)->control_ckobuffer, usbhub_clk); + } else { + clrbits_le32((*ctrl)->control_ckobuffer, usbhub_clk); + clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk); + clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk); + } +} + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int ret; + + /* VCC_3V3_ETH */ + cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_3V3, SMPS9_CTRL, + SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO); + + setup_host_clocks(true); + + ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); + if (ret < 0) + printf("cm_t54: Failed to initialize ehci : %d\n", ret); + + return ret; +} + +int ehci_hcd_stop(void) +{ + int ret = omap_ehci_hcd_stop(); + + setup_host_clocks(false); + + cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_OFF, + SMPS9_CTRL, SMPS_MODE_SLP_AUTO); + + return ret; +} + +void usb_hub_reset_devices(int port) +{ + /* The LAN9730 needs to be reset after the port power has been set. */ + if (port == 3) { + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0); + udelay(10); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1); + } +} +#endif + diff --git a/board/compulab/cm_t54/mux.c b/board/compulab/cm_t54/mux.c new file mode 100644 index 0000000000..da353831c0 --- /dev/null +++ b/board/compulab/cm_t54/mux.c @@ -0,0 +1,94 @@ +/* + * Pinmux configuration for Compulab CM-T54 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Dmitry Lifshitz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CM_T54_MUX_DATA_H +#define _CM_T54_MUX_DATA_H + +#include +#include + +const struct pad_conf_entry core_padconf_array_essential[] = { + /* MMC1 - SD CARD */ + {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ + {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ + {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0 */ + {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1 */ + {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2 */ + {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3 */ + + /* SD CARD CD and WP GPIOs*/ + {TIMER5_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_228 */ + {TIMER6_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_229 */ + + /* MMC2 - eMMC */ + {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ + {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ + {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ + {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ + {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ + {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ + {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ + {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ + {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ + {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ + + /* UART4 */ + {I2C5_SCL, (PTU | IEN | M2)}, /* UART4_RX */ + {I2C5_SDA, (M2)}, /* UART4_TX */ + + /* Led */ + {HSI2_CAFLAG, (PTU | M6)}, /* GPIO3_80 */ + + /* I2C1 */ + {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ + {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ + + /* USBB2, USBB3 */ + {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ + {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ + {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE */ + {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ + + /* USB Hub and USB Eth reset GPIOs */ + {HSI2_CAREADY, (PTD | M6)}, /* GPIO3_76 */ + {HSI2_ACDATA, (PTD | M6)}, /* GPIO3_83 */ + + /* I2C4 */ + {I2C4_SCL, (PTU | IEN | M0)}, /* I2C4_SCL */ + {I2C4_SDA, (PTU | IEN | M0)}, /* I2C4_SDA */ +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ + {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ + {SYS_32K, (IEN | M0)}, /* SYS_32K */ + + /* USB Hub clock */ + {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */ +}; + +/* + * Routine: set_muxconf_regs_essential + * Description: setup board pinmux configuration. + */ +void set_muxconf_regs_essential(void) +{ + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#endif /* _CM_T54_MUX_DATA_H */ diff --git a/board/compulab/cm_t54/spl.c b/board/compulab/cm_t54/spl.c new file mode 100644 index 0000000000..5c7b2c8e93 --- /dev/null +++ b/board/compulab/cm_t54/spl.c @@ -0,0 +1,66 @@ +/* + * SPL specific code for Compulab CM-T54 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Dmitry Lifshitz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = { +#if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M) + .sdram_config_init = 0x618522B2, + .sdram_config = 0x618522B2, +#elif defined(CONFIG_DRAM_2G) + .sdram_config_init = 0x618522BA, + .sdram_config = 0x618522BA, +#endif + .sdram_config2 = 0x0, + .ref_ctrl = 0x00001040, + .sdram_tim1 = 0xEEEF36F3, + .sdram_tim2 = 0x348F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x1007190B, + .temp_alert_config = 0x00000000, + + .emif_ddr_phy_ctlr_1_init = 0x0030400B, + .emif_ddr_phy_ctlr_1 = 0x0034400B, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x4350D435, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x40000305, +}; + +const struct dmm_lisa_map_regs lisa_map_cm_t54 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + +#ifdef CONFIG_DRAM_2G + .dmm_lisa_map_2 = 0x80740300, +#elif defined(CONFIG_DRAM_1G) + .dmm_lisa_map_2 = 0x80640300, +#elif defined(CONFIG_DRAM_512M) + .dmm_lisa_map_2 = 0x80500100, +#endif + .dmm_lisa_map_3 = 0x00000000, + .is_ma_present = 0x1, +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + *regs = &emif_regs_ddr3_532_mhz_cm_t54; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &lisa_map_cm_t54; +} diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile new file mode 100644 index 0000000000..dbf0009652 --- /dev/null +++ b/board/compulab/common/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2011 - 2013 CompuLab, Ltd. +# +# Author: Igor Grinberg +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += common.o +obj-$(CONFIG_SYS_I2C) += eeprom.o +obj-$(CONFIG_LCD) += omap3_display.o +obj-$(CONFIG_SPLASH_SCREEN) += splash.o +obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c new file mode 100644 index 0000000000..b25d9a20b4 --- /dev/null +++ b/board/compulab/common/common.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. + * + * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "common.h" +#include "eeprom.h" + +void cl_print_pcb_info(void) +{ + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); +} + +#ifdef CONFIG_SERIAL_TAG +void __weak get_board_serial(struct tag_serialnr *serialnr) +{ + /* + * This corresponds to what happens when we can communicate with the + * eeprom but don't get a valid board serial value. + */ + serialnr->low = 0; + serialnr->high = 0; +}; +#endif + +#ifdef CONFIG_CMD_USB +int cl_usb_hub_init(int gpio, const char *label) +{ + if (gpio_request(gpio, label)) { + printf("Error: can't obtain GPIO%d for %s", gpio, label); + return -1; + } + + gpio_direction_output(gpio, 0); + udelay(10); + gpio_set_value(gpio, 1); + udelay(1000); + return 0; +} + +void cl_usb_hub_deinit(int gpio) +{ + gpio_free(gpio); +} +#endif diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h new file mode 100644 index 0000000000..68ffb111dc --- /dev/null +++ b/board/compulab/common/common.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. + * + * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CL_COMMON_ +#define _CL_COMMON_ + +#include + +void cl_print_pcb_info(void); + +#ifdef CONFIG_CMD_USB +int cl_usb_hub_init(int gpio, const char *label); +void cl_usb_hub_deinit(int gpio); +#else /* !CONFIG_CMD_USB */ +static inline int cl_usb_hub_init(int gpio, const char *label) +{ + return -ENOSYS; +} +static inline void cl_usb_hub_deinit(int gpio) {} +#endif /* CONFIG_CMD_USB */ + +#ifdef CONFIG_SPLASH_SCREEN +int cl_splash_screen_prepare(int nand_offset); +#else /* !CONFIG_SPLASH_SCREEN */ +static inline int cl_splash_screen_prepare(int nand_offset) +{ + return -ENOSYS; +} +#endif /* CONFIG_SPLASH_SCREEN */ + +#ifdef CONFIG_SMC911X +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio); +#else /* !CONFIG_SMC911X */ +static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio) +{ + return -ENOSYS; +} +#endif /* CONFIG_SMC911X */ + +#endif /* _CL_COMMON_ */ diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c new file mode 100644 index 0000000000..a45e7be11f --- /dev/null +++ b/board/compulab/common/eeprom.c @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2011 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#ifndef CONFIG_SYS_I2C_EEPROM_ADDR +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#endif + +#ifndef CONFIG_SYS_I2C_EEPROM_BUS +#define CONFIG_SYS_I2C_EEPROM_BUS 0 +#endif + +#define EEPROM_LAYOUT_VER_OFFSET 44 +#define BOARD_SERIAL_OFFSET 20 +#define BOARD_SERIAL_OFFSET_LEGACY 8 +#define BOARD_REV_OFFSET 0 +#define BOARD_REV_OFFSET_LEGACY 6 +#define BOARD_REV_SIZE 2 +#define MAC_ADDR_OFFSET 4 +#define MAC_ADDR_OFFSET_LEGACY 0 + +#define LAYOUT_INVALID 0 +#define LAYOUT_LEGACY 0xff + +static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */ + +static int cl_eeprom_read(uint offset, uchar *buf, int len) +{ + int res; + unsigned int current_i2c_bus = i2c_get_bus_num(); + + res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); + if (res < 0) + return res; + + res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); + + i2c_set_bus_num(current_i2c_bus); + + return res; +} + +static int cl_eeprom_setup_layout(void) +{ + int res; + + if (cl_eeprom_layout != LAYOUT_INVALID) + return 0; + + res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, + (uchar *)&cl_eeprom_layout, 1); + if (res) { + cl_eeprom_layout = LAYOUT_INVALID; + return res; + } + + if (cl_eeprom_layout == 0 || cl_eeprom_layout >= 0x20) + cl_eeprom_layout = LAYOUT_LEGACY; + + return 0; +} + +void get_board_serial(struct tag_serialnr *serialnr) +{ + u32 serial[2]; + uint offset; + + memset(serialnr, 0, sizeof(*serialnr)); + + if (cl_eeprom_setup_layout()) + return; + + offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? + BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY; + + if (cl_eeprom_read(offset, (uchar *)serial, 8)) + return; + + if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) { + serialnr->low = serial[0]; + serialnr->high = serial[1]; + } +} + +/* + * Routine: cl_eeprom_read_mac_addr + * Description: read mac address and store it in buf. + */ +int cl_eeprom_read_mac_addr(uchar *buf) +{ + uint offset; + + if (cl_eeprom_setup_layout()) + return 0; + + offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? + MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY; + + return cl_eeprom_read(offset, buf, 6); +} + +static u32 board_rev; + +/* + * Routine: cl_eeprom_get_board_rev + * Description: read system revision from eeprom + */ +u32 cl_eeprom_get_board_rev(void) +{ + char str[5]; /* Legacy representation can contain at most 4 digits */ + uint offset = BOARD_REV_OFFSET_LEGACY; + + if (board_rev) + return board_rev; + + if (cl_eeprom_setup_layout()) + return 0; + + if (cl_eeprom_layout != LAYOUT_LEGACY) + offset = BOARD_REV_OFFSET; + + if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE)) + return 0; + + /* + * Convert legacy syntactic representation to semantic + * representation. i.e. for rev 1.00: 0x100 --> 0x64 + */ + if (cl_eeprom_layout == LAYOUT_LEGACY) { + sprintf(str, "%x", board_rev); + board_rev = simple_strtoul(str, NULL, 10); + } + + return board_rev; +}; diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h new file mode 100644 index 0000000000..85d5bf03d6 --- /dev/null +++ b/board/compulab/common/eeprom.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2011 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EEPROM_ +#define _EEPROM_ + +#ifdef CONFIG_SYS_I2C +int cl_eeprom_read_mac_addr(uchar *buf); +u32 cl_eeprom_get_board_rev(void); +#else +static inline int cl_eeprom_read_mac_addr(uchar *buf) +{ + return 1; +} +static inline u32 cl_eeprom_get_board_rev(void) +{ + return 0; +} +#endif + +#endif diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c new file mode 100644 index 0000000000..61707f5b90 --- /dev/null +++ b/board/compulab/common/omap3_display.c @@ -0,0 +1,454 @@ +/* + * (C) Copyright 2012 - 2013 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * + * Parsing code based on linux/drivers/video/pxafb.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum display_type { + NONE, + DVI, + DVI_CUSTOM, + DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */ +}; + +#define CMAP_ADDR 0x80100000 + +/* + * The frame buffer is allocated before we have the chance to parse user input. + * To make sure enough memory is allocated for all resolutions, we define + * vl_{col | row} to the maximal resolution supported by OMAP3. + */ +vidinfo_t panel_info = { + .vl_col = 1400, + .vl_row = 1050, + .vl_bpix = LCD_BPP, + .cmap = (ushort *)CMAP_ADDR, +}; + +static struct panel_config panel_cfg; +static enum display_type lcd_def; + +/* + * A note on DVI presets; + * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can + * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to + * support two BMP types with one setting. + */ +static const struct panel_config preset_dvi_640X480 = { + .lcd_size = PANEL_LCD_SIZE(640, 480), + .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), + .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 12 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_800X600 = { + .lcd_size = PANEL_LCD_SIZE(800, 600), + .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), + .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 8 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1024X768 = { + .lcd_size = PANEL_LCD_SIZE(1024, 768), + .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), + .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 5 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1152X864 = { + .lcd_size = PANEL_LCD_SIZE(1152, 864), + .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), + .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 4 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X960 = { + .lcd_size = PANEL_LCD_SIZE(1280, 960), + .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), + .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X1024 = { + .lcd_size = PANEL_LCD_SIZE(1280, 1024), + .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), + .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dataimage_480X800 = { + .lcd_size = PANEL_LCD_SIZE(480, 800), + .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2), + .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3), + .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF, + .divisor = 10 | (1 << 10), + .data_lines = LCD_INTERFACE_18_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +/* + * set_resolution_params() + * + * Due to usage of multiple display related APIs resolution data is located in + * more than one place. This function updates them all. + */ +static void set_resolution_params(int x, int y) +{ + panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y); + panel_info.vl_col = x; + panel_info.vl_row = y; + lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; +} + +static void set_preset(const struct panel_config preset, int x_res, int y_res) +{ + panel_cfg = preset; + set_resolution_params(x_res, y_res); +} + +static enum display_type set_dvi_preset(const struct panel_config preset, + int x_res, int y_res) +{ + set_preset(preset, x_res, y_res); + return DVI; +} + +static enum display_type set_dataimage_preset(const struct panel_config preset, + int x_res, int y_res) +{ + set_preset(preset, x_res, y_res); + return DATA_IMAGE; +} + +/* + * parse_mode() - parse the mode parameter of custom lcd settings + * + * @mode: x + * + * Returns -1 on error, 0 on success. + */ +static int parse_mode(const char *mode) +{ + unsigned int modelen = strlen(mode); + int res_specified = 0; + unsigned int xres = 0, yres = 0; + int yres_specified = 0; + int i; + + for (i = modelen - 1; i >= 0; i--) { + switch (mode[i]) { + case 'x': + if (!yres_specified) { + yres = simple_strtoul(&mode[i + 1], NULL, 0); + yres_specified = 1; + } else { + goto done_parsing; + } + + break; + case '0' ... '9': + break; + default: + goto done_parsing; + } + } + + if (i < 0 && yres_specified) { + xres = simple_strtoul(mode, NULL, 0); + res_specified = 1; + } + +done_parsing: + if (res_specified) { + set_resolution_params(xres, yres); + } else { + printf("LCD: invalid mode: %s\n", mode); + return -1; + } + + return 0; +} + +#define PIXEL_CLK_NUMERATOR (26 * 432 / 39) +/* + * parse_pixclock() - Parse the pixclock parameter of custom lcd settings + * + * @pixclock: the desired pixel clock + * + * Returns -1 on error, 0 on success. + * + * Handling the pixel_clock: + * + * Pixel clock is defined in the OMAP35x TRM as follows: + * pixel_clock = + * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) / + * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] * + * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1)) + * + * In practice, this means that in order to set the + * divisor for the desired pixel clock one needs to + * solve the following equation: + * + * 26 * 432 / (39 * ) = DSS.DISPC_DIVISOR[6:0] + * + * NOTE: the explicit equation above is reduced. Do not + * try to infer anything from these numbers. + */ +static int parse_pixclock(char *pixclock) +{ + int divisor, pixclock_val; + char *pixclk_start = pixclock; + + pixclock_val = simple_strtoul(pixclock, &pixclock, 10); + divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val); + /* 0 and 1 are illegal values for PCD */ + if (divisor <= 1) + divisor = 2; + + panel_cfg.divisor = divisor | (1 << 16); + if (pixclock[0] != '\0') { + printf("LCD: invalid value for pixclock:%s\n", pixclk_start); + return -1; + } + + return 0; +} + +/* + * parse_setting() - parse a single setting of custom lcd parameters + * + * @setting: The custom lcd setting : + * + * Returns -1 on failure, 0 on success. + */ +static int parse_setting(char *setting) +{ + int num_val; + char *setting_start = setting; + + if (!strncmp(setting, "mode:", 5)) { + return parse_mode(setting + 5); + } else if (!strncmp(setting, "pixclock:", 9)) { + return parse_pixclock(setting + 9); + } else if (!strncmp(setting, "left:", 5)) { + num_val = simple_strtoul(setting + 5, &setting, 0); + panel_cfg.timing_h |= DSS_HBP(num_val); + } else if (!strncmp(setting, "right:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_h |= DSS_HFP(num_val); + } else if (!strncmp(setting, "upper:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VBP(num_val); + } else if (!strncmp(setting, "lower:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VFP(num_val); + } else if (!strncmp(setting, "hsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_h |= DSS_HSW(num_val); + } else if (!strncmp(setting, "vsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_v |= DSS_VSW(num_val); + } else if (!strncmp(setting, "hsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IHS; + else + panel_cfg.pol_freq &= ~DSS_IHS; + } else if (!strncmp(setting, "vsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IVS; + else + panel_cfg.pol_freq &= ~DSS_IVS; + } else if (!strncmp(setting, "outputen:", 9)) { + if (simple_strtoul(setting + 9, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IEO; + else + panel_cfg.pol_freq &= ~DSS_IEO; + } else if (!strncmp(setting, "pixclockpol:", 12)) { + if (simple_strtoul(setting + 12, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IPC; + else + panel_cfg.pol_freq &= ~DSS_IPC; + } else if (!strncmp(setting, "active", 6)) { + panel_cfg.panel_type = ACTIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "passive", 7)) { + panel_cfg.panel_type = PASSIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "display:", 8)) { + if (!strncmp(setting + 8, "dvi", 3)) { + lcd_def = DVI_CUSTOM; + return 0; /* Avoid sanity check below */ + } + } else { + printf("LCD: unknown option %s\n", setting_start); + return -1; + } + + if (setting[0] != '\0') { + printf("LCD: invalid value for %s\n", setting_start); + return -1; + } + + return 0; +} + +/* + * env_parse_customlcd() - parse custom lcd params from an environment variable. + * + * @custom_lcd_params: The environment variable containing the lcd params. + * + * Returns -1 on failure, 0 on success. + */ +static int parse_customlcd(char *custom_lcd_params) +{ + char params_cpy[160]; + char *setting; + + strncpy(params_cpy, custom_lcd_params, 160); + setting = strtok(params_cpy, ","); + while (setting) { + if (parse_setting(setting) < 0) + return -1; + + setting = strtok(NULL, ","); + } + + /* Currently we don't support changing this via custom lcd params */ + panel_cfg.data_lines = LCD_INTERFACE_24_BIT; + panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */ + + return 0; +} + +/* + * env_parse_displaytype() - parse display type. + * + * Parses the environment variable "displaytype", which contains the + * name of the display type or preset, in which case it applies its + * configurations. + * + * Returns the type of display that was specified. + */ +static enum display_type env_parse_displaytype(char *displaytype) +{ + if (!strncmp(displaytype, "dvi640x480", 10)) + return set_dvi_preset(preset_dvi_640X480, 640, 480); + else if (!strncmp(displaytype, "dvi800x600", 10)) + return set_dvi_preset(preset_dvi_800X600, 800, 600); + else if (!strncmp(displaytype, "dvi1024x768", 11)) + return set_dvi_preset(preset_dvi_1024X768, 1024, 768); + else if (!strncmp(displaytype, "dvi1152x864", 11)) + return set_dvi_preset(preset_dvi_1152X864, 1152, 864); + else if (!strncmp(displaytype, "dvi1280x960", 11)) + return set_dvi_preset(preset_dvi_1280X960, 1280, 960); + else if (!strncmp(displaytype, "dvi1280x1024", 12)) + return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024); + else if (!strncmp(displaytype, "dataimage480x800", 16)) + return set_dataimage_preset(preset_dataimage_480X800, 480, 800); + + return NONE; +} + +void lcd_ctrl_init(void *lcdbase) +{ + struct prcm *prcm = (struct prcm *)PRCM_BASE; + char *custom_lcd; + char *displaytype = getenv("displaytype"); + + if (displaytype == NULL) + return; + + lcd_def = env_parse_displaytype(displaytype); + /* If we did not recognize the preset, check if it's an env variable */ + if (lcd_def == NONE) { + custom_lcd = getenv(displaytype); + if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0) + return; + } + + panel_cfg.frame_buffer = lcdbase; + omap3_dss_panel_config(&panel_cfg); + /* + * Pixel clock is defined with many divisions and only few + * multiplications of the system clock. Since DSS FCLK divisor is set + * to 16 by default, we need to set it to a smaller value, like 3 + * (chosen via trial and error). + */ + clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); +} + +#ifdef CONFIG_SCF0403_LCD +static void scf0403_enable(void) +{ + gpio_direction_output(58, 1); + scf0403_init(157); +} +#else +static inline void scf0403_enable(void) {} +#endif + +void lcd_enable(void) +{ + switch (lcd_def) { + case NONE: + return; + case DVI: + case DVI_CUSTOM: + gpio_direction_output(54, 0); /* Turn on DVI */ + break; + case DATA_IMAGE: + scf0403_enable(); + break; + } + + omap3_dss_enable(); +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {} diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c new file mode 100644 index 0000000000..4561661987 --- /dev/null +++ b/board/compulab/common/omap3_smc911x.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. + * + * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "common.h" + +static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = { + NET_GPMC_CONFIG1, + NET_GPMC_CONFIG2, + NET_GPMC_CONFIG3, + NET_GPMC_CONFIG4, + NET_GPMC_CONFIG5, + NET_GPMC_CONFIG6, + 0 +}; + +static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config, + &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); +} + +#ifdef CONFIG_OMAP_GPIO +static int cl_omap3_smc911x_reset_net_chip(int gpio) +{ + int err; + + if (!gpio_is_valid(gpio)) + return -EINVAL; + + err = gpio_request(gpio, "eth rst"); + if (err) + return err; + + /* Set gpio as output and send a pulse */ + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + mdelay(40); + gpio_set_value(gpio, 1); + mdelay(1); + + return 0; +} +#else /* !CONFIG_OMAP_GPIO */ +static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; } +#endif /* CONFIG_OMAP_GPIO */ + +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio) +{ + int ret; + + cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr); + + if (reset) + reset(rst_gpio); + else + cl_omap3_smc911x_reset_net_chip(rst_gpio); + + ret = smc911x_initialize(id, base_addr); + if (ret > 0) + return ret; + + printf("Failed initializing SMC911x! "); + return 0; +} diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c new file mode 100644 index 0000000000..49ed49b81e --- /dev/null +++ b/board/compulab/common/splash.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. + * + * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_NAND +static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) +{ + struct bmp_header *bmp_hdr; + int res; + size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); + + if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) + goto splash_address_too_high; + + res = nand_read_skip_bad(&nand_info[nand_curr_device], + nand_offset, &bmp_header_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + if (res < 0) + return res; + + bmp_hdr = (struct bmp_header *)bmp_load_addr; + bmp_size = le32_to_cpu(bmp_hdr->file_size); + + if (bmp_load_addr + bmp_size >= gd->start_addr_sp) + goto splash_address_too_high; + + return nand_read_skip_bad(&nand_info[nand_curr_device], + nand_offset, &bmp_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + +splash_address_too_high: + printf("Error: splashimage address too high. Data overwrites U-Boot " + "and/or placed beyond DRAM boundaries.\n"); + + return -1; +} +#else +static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) +{ + return -1; +} +#endif /* CONFIG_CMD_NAND */ + +int cl_splash_screen_prepare(int nand_offset) +{ + char *env_splashimage_value; + u32 bmp_load_addr; + + env_splashimage_value = getenv("splashimage"); + if (env_splashimage_value == NULL) + return -1; + + bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); + if (bmp_load_addr == 0) { + printf("Error: bad splashimage address specified\n"); + return -1; + } + + return splash_load_from_nand(bmp_load_addr, nand_offset); +} diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts deleted file mode 100644 index ee31476c1e..0000000000 --- a/board/compulab/dts/tegra20-trimslice.dts +++ /dev/null @@ -1,64 +0,0 @@ -/dts-v1/; - -#include "tegra20.dtsi" - -/ { - model = "Compulab TrimSlice board"; - compatible = "compulab,trimslice", "nvidia,tegra20"; - - aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000000"; - }; - - memory { - reg = <0x00000000 0x40000000>; - }; - - serial@70006000 { - clock-frequency = <216000000>; - }; - - i2c@7000c000 { - status = "disabled"; - }; - - spi@7000c380 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - - usb@c5000000 { - nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */ - }; - - usb@c5004000 { - status = "disabled"; - }; - - sdhci@c8000000 { - status = "okay"; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio 121 1>; /* gpio PP1 */ - wp-gpios = <&gpio 122 0>; /* gpio PP2 */ - bus-width = <4>; - }; -}; diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig new file mode 100644 index 0000000000..3576914034 --- /dev/null +++ b/board/compulab/trimslice/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TRIMSLICE + +config SYS_BOARD + default "trimslice" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "trimslice" + +endif diff --git a/board/compulab/trimslice/MAINTAINERS b/board/compulab/trimslice/MAINTAINERS new file mode 100644 index 0000000000..85b120017f --- /dev/null +++ b/board/compulab/trimslice/MAINTAINERS @@ -0,0 +1,7 @@ +TRIMSLICE BOARD +M: Tom Warren +M: Stephen Warren +S: Maintained +F: board/compulab/trimslice/ +F: include/configs/trimslice.h +F: configs/trimslice_defconfig diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index 3ce180cf01..311eb92d7b 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -5,28 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := trimslice.o -$(shell mkdir -p $(obj)../../nvidia/common) - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -include ../../nvidia/common/common.mk - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index ef949303a6..c9da80d5eb 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -13,6 +13,7 @@ #include #include #include +#include void pin_mux_usb(void) { @@ -20,7 +21,7 @@ void pin_mux_usb(void) * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO * in the current device tree. */ - pinmux_tristate_disable(PINGRP_UAC); + pinmux_tristate_disable(PMUX_PINGRP_UAC); } void pin_mux_spi(void) @@ -38,5 +39,12 @@ void pin_mux_mmc(void) funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); /* For CD GPIO PP1 */ - pinmux_tristate_disable(PINGRP_DAP3); + pinmux_tristate_disable(PMUX_PINGRP_DAP3); } + +#ifdef CONFIG_PCI +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} +#endif diff --git a/board/congatec/cgtqmx6eval/Kconfig b/board/congatec/cgtqmx6eval/Kconfig new file mode 100644 index 0000000000..0a837bde0e --- /dev/null +++ b/board/congatec/cgtqmx6eval/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CGTQMX6EVAL + +config SYS_BOARD + default "cgtqmx6eval" + +config SYS_VENDOR + default "congatec" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "cgtqmx6eval" + +endif diff --git a/board/congatec/cgtqmx6eval/MAINTAINERS b/board/congatec/cgtqmx6eval/MAINTAINERS new file mode 100644 index 0000000000..35f4a2a21a --- /dev/null +++ b/board/congatec/cgtqmx6eval/MAINTAINERS @@ -0,0 +1,6 @@ +CGTQMX6EVAL BOARD +#M: Leo Sartre +S: Orphan (since 2014-06) +F: board/congatec/cgtqmx6eval/ +F: include/configs/cgtqmx6eval.h +F: configs/cgtqmx6qeval_defconfig diff --git a/board/congatec/cgtqmx6eval/Makefile b/board/congatec/cgtqmx6eval/Makefile index 8668d97688..1bce4737f0 100644 --- a/board/congatec/cgtqmx6eval/Makefile +++ b/board/congatec/cgtqmx6eval/Makefile @@ -7,23 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cgtqmx6eval.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cgtqmx6eval.o diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README index bbf0f75a4d..5e76d2ac5e 100644 --- a/board/congatec/cgtqmx6eval/README +++ b/board/congatec/cgtqmx6eval/README @@ -7,8 +7,7 @@ Conga-QEVAl Evaluation Carrier board with qmx6 quad module. 1. Boot source, boot from SD card --------------------------------- -This version of u-boot works only on the SD card. By default, the -Congatec board can boot only from the SPI-NOR. +By default, the Congatec board can boot only from the SPI-NOR. But, with the u-boot version provided with the board you can write boot registers to force the board to reboot and boot from the SD slot. If "bmode" command is not available from your pre-installed u-boot, these diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 0d07f1b8a3..ac64bcc911 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -4,7 +4,7 @@ * Copyright (C) 2013, Adeneo Embedded * Leo Sartre, * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -35,32 +35,32 @@ int dram_init(void) } iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO_2_6, /* CD */ + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO2_IO06, /* CD */ }; static void setup_iomux_uart(void) diff --git a/board/congatec/cgtqmx6eval/imximage.cfg b/board/congatec/cgtqmx6eval/imximage.cfg new file mode 100644 index 0000000000..bb6c60b4c3 --- /dev/null +++ b/board/congatec/cgtqmx6eval/imximage.cfg @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 + +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 + +DATA 4 0x020e05ac 0x00020030 +DATA 4 0x020e05b4 0x00020030 +DATA 4 0x020e0528 0x00020030 +DATA 4 0x020e0520 0x00020030 + +DATA 4 0x020e0514 0x00020030 +DATA 4 0x020e0510 0x00020030 +DATA 4 0x020e05bc 0x00020030 +DATA 4 0x020e05c4 0x00020030 + +DATA 4 0x020e056c 0x00020030 +DATA 4 0x020e0578 0x00020030 +DATA 4 0x020e0588 0x00020030 +DATA 4 0x020e0594 0x00020030 + +DATA 4 0x020e057c 0x00020030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 + +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 + +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 + +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0750 0x00020000 + +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0798 0x000C0000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b0018 0x00081740 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b002c 0x000026D2 + +DATA 4 0x021b0030 0x005A1023 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 + +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x0408803A +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803B +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038 + +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0800 0xA1380003 +DATA 4 0x021b4800 0xA1380003 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b4818 0x00022227 + +DATA 4 0x021b083c 0x434B0350 +DATA 4 0x021b0840 0x034C0359 +DATA 4 0x021b483c 0x434B0350 +DATA 4 0x021b4840 0x03650348 +DATA 4 0x021b0848 0x4436383B +DATA 4 0x021b4848 0x39393341 +DATA 4 0x021b0850 0x35373933 +DATA 4 0x021b4850 0x48254A36 + +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F + +DATA 4 0x021b480c 0x00440044 +DATA 4 0x021b4810 0x00440044 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b0404 0x00011006 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig new file mode 100644 index 0000000000..981de1f071 --- /dev/null +++ b/board/coreboot/coreboot/Kconfig @@ -0,0 +1,40 @@ +if TARGET_COREBOOT + +config SYS_BOARD + default "coreboot" + +config SYS_VENDOR + default "coreboot" + +config SYS_SOC + default "coreboot" + +comment "coreboot-specific options" + +config SYS_CONFIG_NAME + string "Board configuration file" + default "chromebook_link" + help + This option selects the board configuration file in include/configs/ + directory to be used to build U-Boot for coreboot. + +config DEFAULT_DEVICE_TREE + string "Board Device Tree Source (dts) file" + default "chromebook_link" + help + This option selects the board Device Tree Source (dts) file in + arch/x86/dts/ directory to be used to build U-Boot for coreboot. + +config SYS_CAR_ADDR + hex "Board specific Cache-As-RAM (CAR) address" + default 0x19200000 + help + This option specifies the board specific Cache-As-RAM (CAR) address. + +config SYS_CAR_SIZE + hex "Board specific Cache-As-RAM (CAR) size" + default 0x4000 + help + This option specifies the board specific Cache-As-RAM (CAR) size. + +endif diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS new file mode 100644 index 0000000000..2736aa0282 --- /dev/null +++ b/board/coreboot/coreboot/MAINTAINERS @@ -0,0 +1,6 @@ +COREBOOT BOARD +M: Simon Glass +S: Maintained +F: board/coreboot/coreboot/ +F: include/configs/chromebook_link.h +F: configs/coreboot-x86_defconfig diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile new file mode 100644 index 0000000000..27ebe78eb1 --- /dev/null +++ b/board/coreboot/coreboot/Makefile @@ -0,0 +1,15 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += coreboot_start.o coreboot.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c new file mode 100644 index 0000000000..e076ea69cf --- /dev/null +++ b/board/coreboot/coreboot/coreboot.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int arch_early_init_r(void) +{ +#ifdef CONFIG_CROS_EC + if (cros_ec_board_init()) + return -1; +#endif + + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/board/chromebook-x86/coreboot/coreboot_start.S b/board/coreboot/coreboot/coreboot_start.S similarity index 87% rename from board/chromebook-x86/coreboot/coreboot_start.S rename to board/coreboot/coreboot/coreboot_start.S index c6279bb30b..932fe6c24b 100644 --- a/board/chromebook-x86/coreboot/coreboot_start.S +++ b/board/coreboot/coreboot/coreboot_start.S @@ -3,7 +3,7 @@ * (C) Copyright 2008 * Graeme Russ, graeme.russ@gmail.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* board early intialization */ diff --git a/board/corscience/tricorder/Kconfig b/board/corscience/tricorder/Kconfig new file mode 100644 index 0000000000..345ac83d48 --- /dev/null +++ b/board/corscience/tricorder/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TRICORDER + +config SYS_BOARD + default "tricorder" + +config SYS_VENDOR + default "corscience" + +config SYS_CONFIG_NAME + default "tricorder" + +endif diff --git a/board/corscience/tricorder/MAINTAINERS b/board/corscience/tricorder/MAINTAINERS new file mode 100644 index 0000000000..8a8171b550 --- /dev/null +++ b/board/corscience/tricorder/MAINTAINERS @@ -0,0 +1,7 @@ +TRICORDER BOARD +M: Thomas Weber +S: Maintained +F: board/corscience/tricorder/ +F: include/configs/tricorder.h +F: configs/tricorder_defconfig +F: configs/tricorder_flash_defconfig diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile index 2ab12bb954..266432dd2d 100644 --- a/board/corscience/tricorder/Makefile +++ b/board/corscience/tricorder/Makefile @@ -8,23 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := tricorder.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := tricorder.o tricorder-eeprom.o led.o diff --git a/board/corscience/tricorder/led.c b/board/corscience/tricorder/led.c new file mode 100644 index 0000000000..30f2f508f0 --- /dev/null +++ b/board/corscience/tricorder/led.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013 Corscience GmbH & Co.KG + * Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +#define TRICORDER_STATUS_LED_YELLOW 42 +#define TRICORDER_STATUS_LED_GREEN 43 + +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); +} + +void __led_toggle(led_id_t mask) +{ + int toggle_gpio = 0; +#ifdef STATUS_LED_BIT + if (!toggle_gpio && STATUS_LED_BIT & mask) + toggle_gpio = TRICORDER_STATUS_LED_GREEN; +#endif +#ifdef STATUS_LED_BIT1 + if (!toggle_gpio && STATUS_LED_BIT1 & mask) + toggle_gpio = TRICORDER_STATUS_LED_YELLOW; +#endif +#ifdef STATUS_LED_BIT2 + if (!toggle_gpio && STATUS_LED_BIT2 & mask) { + uint8_t val; + twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, + &val); + val ^= (TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDAPWM); + twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, + val); + } +#endif + if (toggle_gpio) { + int state; + gpio_request(toggle_gpio, ""); + state = gpio_get_value(toggle_gpio); + gpio_set_value(toggle_gpio, !state); + } +} + +void __led_set(led_id_t mask, int state) +{ +#ifdef STATUS_LED_BIT + if (STATUS_LED_BIT & mask) { + gpio_request(TRICORDER_STATUS_LED_GREEN, ""); + gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0); + gpio_set_value(TRICORDER_STATUS_LED_GREEN, state); + } +#endif +#ifdef STATUS_LED_BIT1 + if (STATUS_LED_BIT1 & mask) { + gpio_request(TRICORDER_STATUS_LED_YELLOW, ""); + gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0); + gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state); + } +#endif +#ifdef STATUS_LED_BIT2 + if (STATUS_LED_BIT2 & mask) { + if (STATUS_LED_OFF == state) + twl4030_i2c_write_u8(TWL4030_CHIP_LED, + TWL4030_LED_LEDEN, 0); + else + twl4030_i2c_write_u8(TWL4030_CHIP_LED, + TWL4030_LED_LEDEN, + (TWL4030_LED_LEDEN_LEDAON | + TWL4030_LED_LEDEN_LEDAPWM)); + } +#endif +} diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c new file mode 100644 index 0000000000..1c74a0f7d0 --- /dev/null +++ b/board/corscience/tricorder/tricorder-eeprom.c @@ -0,0 +1,251 @@ +/* + * (C) Copyright 2013 + * Corscience GmbH & Co. KG, + * Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#include "tricorder-eeprom.h" + +static inline void warn_wrong_value(const char *msg, unsigned int a, + unsigned int b) +{ + printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b); +} + +static int handle_eeprom_v0(struct tricorder_eeprom *eeprom) +{ + struct tricorder_eeprom_v0 { + uint32_t magic; + uint16_t length; + uint16_t version; + char board_name[TRICORDER_BOARD_NAME_LENGTH]; + char board_version[TRICORDER_BOARD_VERSION_LENGTH]; + char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; + uint32_t crc32; + } __packed eepromv0; + uint32_t crc; + + printf("Old EEPROM (v0), consider rewrite!\n"); + + if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) { + warn_wrong_value("length", sizeof(eepromv0), + be16_to_cpu(eeprom->length)); + return 1; + } + + memcpy(&eepromv0, eeprom, sizeof(eepromv0)); + + crc = crc32(0L, (unsigned char *)&eepromv0, + sizeof(eepromv0) - sizeof(eepromv0.crc32)); + if (be32_to_cpu(eepromv0.crc32) != crc) { + warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32), + crc); + return 1; + } + + /* Ok the content is correct, do the conversion */ + memset(eeprom->interface_version, 0x0, + TRICORDER_INTERFACE_VERSION_LENGTH); + crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); + eeprom->crc32 = cpu_to_be32(crc); + + return 0; +} + +static int handle_eeprom_v1(struct tricorder_eeprom *eeprom) +{ + uint32_t crc; + + if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) { + warn_wrong_value("length", TRICORDER_EEPROM_SIZE, + be16_to_cpu(eeprom->length)); + return 1; + } + + crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); + if (be32_to_cpu(eeprom->crc32) != crc) { + warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc); + return 1; + } + + return 0; +} + +int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom) +{ +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + unsigned int bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif + + memset(eeprom, 0, TRICORDER_EEPROM_SIZE); + + i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE); +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif + + if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) { + warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC, + be32_to_cpu(eeprom->magic)); + return 1; + } + + switch (be16_to_cpu(eeprom->version)) { + case 0: + return handle_eeprom_v0(eeprom); + case 1: + return handle_eeprom_v1(eeprom); + default: + warn_wrong_value("version", TRICORDER_EEPROM_VERSION, + be16_to_cpu(eeprom->version)); + return 1; + } +} + +#if !defined(CONFIG_SPL) +int tricorder_eeprom_read(unsigned devaddr) +{ + struct tricorder_eeprom eeprom; + int ret = tricorder_get_eeprom(devaddr, &eeprom); + + if (ret) + return ret; + + printf("Board type: %.*s\n", + sizeof(eeprom.board_name), eeprom.board_name); + printf("Board version: %.*s\n", + sizeof(eeprom.board_version), eeprom.board_version); + printf("Board serial: %.*s\n", + sizeof(eeprom.board_serial), eeprom.board_serial); + printf("Board interface version: %.*s\n", + sizeof(eeprom.interface_version), + eeprom.interface_version); + + return ret; +} + +int tricorder_eeprom_write(unsigned devaddr, const char *name, + const char *version, const char *serial, const char *interface) +{ + struct tricorder_eeprom eeprom, eeprom_verify; + size_t length; + uint32_t crc; + int ret; + unsigned char *p; + int i; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + unsigned int bus; +#endif + + memset(eeprom, 0, TRICORDER_EEPROM_SIZE); + memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE); + + eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC); + eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE); + eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION); + + length = min(sizeof(eeprom.board_name), strlen(name)); + strncpy(eeprom.board_name, name, length); + + length = min(sizeof(eeprom.board_version), strlen(version)); + strncpy(eeprom.board_version, version, length); + + length = min(sizeof(eeprom.board_serial), strlen(serial)); + strncpy(eeprom.board_serial, serial, length); + + if (interface) { + length = min(sizeof(eeprom.interface_version), + strlen(interface)); + strncpy(eeprom.interface_version, interface, length); + } + + crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE); + eeprom.crc32 = cpu_to_be32(crc); + +#if defined(DEBUG) + puts("Tricorder EEPROM content:\n"); + print_buffer(0, &eeprom, 1, sizeof(eeprom), 16); +#endif + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif + + /* do page write to the eeprom */ + for (i = 0, p = (unsigned char *)&eeprom; + i < sizeof(eeprom); + i += 32, p += 32) { + ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + p, min(sizeof(eeprom) - i, 32)); + if (ret) + break; + udelay(5000); /* 5ms write cycle timing */ + } + + ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify, + TRICORDER_EEPROM_SIZE); + + if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) { + printf("Tricorder: Could not verify EEPROM content!\n"); + ret = 1; + } + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif + return ret; +} + +int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc == 3) { + ulong dev_addr = simple_strtoul(argv[2], NULL, 16); + eeprom_init(); + if (strcmp(argv[1], "read") == 0) { + int rcode; + + rcode = tricorder_eeprom_read(dev_addr); + + return rcode; + } + } else if (argc == 6 || argc == 7) { + ulong dev_addr = simple_strtoul(argv[2], NULL, 16); + char *name = argv[3]; + char *version = argv[4]; + char *serial = argv[5]; + char *interface = NULL; + eeprom_init(); + + if (argc == 7) + interface = argv[6]; + + if (strcmp(argv[1], "write") == 0) { + int rcode; + + rcode = tricorder_eeprom_write(dev_addr, name, version, + serial, interface); + + return rcode; + } + } + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + tricordereeprom, 7, 1, do_tricorder_eeprom, + "Tricorder EEPROM", + "read devaddr\n" + " - read Tricorder EEPROM at devaddr and print content\n" + "tricordereeprom write devaddr name version serial [interface]\n" + " - write Tricorder EEPROM at devaddr with 'name', 'version'" + "and 'serial'\n" + " optional add an HW interface parameter" +); +#endif /* CONFIG_SPL */ diff --git a/board/corscience/tricorder/tricorder-eeprom.h b/board/corscience/tricorder/tricorder-eeprom.h new file mode 100644 index 0000000000..06ed9a5911 --- /dev/null +++ b/board/corscience/tricorder/tricorder-eeprom.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2013 + * Corscience GmbH & Co. KG, + * Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef TRICORDER_EEPROM_H_ +#define TRICORDER_EEPROM_H_ + +#include + +#define TRICORDER_EEPROM_MAGIC 0xc2a94f52 +#define TRICORDER_EEPROM_VERSION 1 + +#define TRICORDER_BOARD_NAME_LENGTH 12 +#define TRICORDER_BOARD_VERSION_LENGTH 4 +#define TRICORDER_BOARD_SERIAL_LENGTH 12 +#define TRICORDER_INTERFACE_VERSION_LENGTH 4 + +struct tricorder_eeprom { + uint32_t magic; + uint16_t length; + uint16_t version; + char board_name[TRICORDER_BOARD_NAME_LENGTH]; + char board_version[TRICORDER_BOARD_VERSION_LENGTH]; + char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; + char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH]; + uint32_t crc32; +} __packed; + +#define TRICORDER_EEPROM_SIZE sizeof(struct tricorder_eeprom) +#define TRICORDER_EEPROM_CRC_SIZE (TRICORDER_EEPROM_SIZE - \ + sizeof(uint32_t)) + +/** + * @brief read eeprom information from a specific eeprom address + */ +int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom); + +#endif /* TRICORDER_EEPROM_H_ */ diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index c7099e5e3a..0fddf4551e 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -13,11 +13,13 @@ #include #include #include +#include #include #include #include #include #include "tricorder.h" +#include "tricorder-eeprom.h" DECLARE_GLOBAL_DATA_PTR; @@ -34,16 +36,93 @@ int board_init(void) return 0; } +/** + * get_eeprom - read the eeprom + * + * @eeprom - pointer to a eeprom struct to fill + * + * This function will panic() on wrong EEPROM content + */ +static void get_eeprom(struct tricorder_eeprom *eeprom) +{ + int ret; + + if (!eeprom) + panic("No eeprom given!\n"); + + ret = gpio_request(7, "BMS"); + if (ret) + panic("gpio: requesting BMS pin failed\n"); + + ret = gpio_direction_input(7); + if (ret) + panic("gpio: set BMS as input failed\n"); + + ret = gpio_get_value(7); + if (ret < 0) + panic("gpio: get BMS pin state failed\n"); + + gpio_free(7); + + if (ret == 0) { + /* BMS is _not_ set, do the EEPROM check */ + ret = tricorder_get_eeprom(0x51, eeprom); + if (!ret) { + if (strncmp(eeprom->board_name, "CS10411", 7) != 0) + panic("Wrong board name '%.*s'\n", + sizeof(eeprom->board_name), + eeprom->board_name); + if (eeprom->board_version[0] < 'D') + panic("Wrong board version '%.*s'\n", + sizeof(eeprom->board_version), + eeprom->board_version); + } else { + panic("Could not get board revision\n"); + } + } else { + memset(eeprom, 0, TRICORDER_EEPROM_SIZE); + } +} + +/** + * print_hwversion - print out a HW version string + * + * @eeprom - pointer to the eeprom + */ +static void print_hwversion(struct tricorder_eeprom *eeprom) +{ + size_t len; + if (!eeprom) + panic("No eeprom given!"); + + printf("Board %.*s:%.*s serial %.*s", + sizeof(eeprom->board_name), eeprom->board_name, + sizeof(eeprom->board_version), eeprom->board_version, + sizeof(eeprom->board_serial), eeprom->board_serial); + + len = strnlen(eeprom->interface_version, + sizeof(eeprom->interface_version)); + if (len > 0) + printf(" HW interface version %.*s", + sizeof(eeprom->interface_version), + eeprom->interface_version); + puts("\n"); +} + /* * Routine: misc_init_r * Description: Configure board specific parts */ int misc_init_r(void) { + struct tricorder_eeprom eeprom; + get_eeprom(&eeprom); + print_hwversion(&eeprom); + twl4030_power_init(); -#ifdef CONFIG_TWL4030_LED - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); -#endif + status_led_set(0, STATUS_LED_ON); + status_led_set(1, STATUS_LED_ON); + status_led_set(2, STATUS_LED_ON); dieid_num_r(); @@ -68,6 +147,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + /* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header @@ -77,12 +163,43 @@ int board_mmc_init(bd_t *bis) */ void get_board_mem_timings(struct board_sdrc_timings *timings) { + struct tricorder_eeprom eeprom; + get_eeprom(&eeprom); + /* General SDRC config */ - timings->mcfg = MICRON_V_MCFG_165(128 << 20); - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + if (eeprom.board_version[0] > 'D') { + /* use optimized timings for our SDRAM device */ + timings->mcfg = MCFG((256 << 20), 14); +#define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define MT46H64M32_TRRD 2 /* 12/6 = 2 */ +#define MT46H64M32_TRCD 3 /* 18/6 = 3 */ +#define MT46H64M32_TRP 3 /* 18/6 = 3 */ +#define MT46H64M32_TRAS 7 /* 42/6 = 7 */ +#define MT46H64M32_TRC 10 /* 60/6 = 10 */ +#define MT46H64M32_TRFC 12 /* 72/6 = 12 */ + timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC, + MT46H64M32_TRAS, MT46H64M32_TRP, + MT46H64M32_TRCD, MT46H64M32_TRRD, + MT46H64M32_TDPL, + MT46H64M32_TDAL); + +#define MT46H64M32_TWTR 1 +#define MT46H64M32_TCKE 1 +#define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */ +#define MT46H64M32_TXP 1 + timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE, + MT46H64M32_TXP, MT46H64M32_XSR); - /* AC timings */ - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + /* use conservative beagleboard timings as default */ + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } } diff --git a/board/corscience/tricorder/tricorder.h b/board/corscience/tricorder/tricorder.h index 820a50c9f7..67c35c56bc 100644 --- a/board/corscience/tricorder/tricorder.h +++ b/board/corscience/tricorder/tricorder.h @@ -75,8 +75,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile deleted file mode 100644 index 446585fc1d..0000000000 --- a/board/cpc45/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o plx9030.o pd67290.o ide.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c deleted file mode 100644 index f182e79fd9..0000000000 --- a/board/cpc45/cpc45.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -int sysControlDisplay(int digit, uchar ascii_code); -extern void Plx9030Init(void); -extern void SPD67290Init(void); - - /* We have to clear the initial data area here. Couldn't have done it - * earlier because DRAM had not been initialized. - */ -int board_early_init_f(void) -{ - - /* enable DUAL UART Mode on CPC45 */ - *(uchar*)DUART_DCR |= 0x1; /* set DCM bit */ - - return 0; -} - -int checkboard(void) -{ -/* - char revision = BOARD_REV; -*/ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - puts ("CPC45 "); -/* - printf("Revision %d ", revision); -*/ - printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); - - return 0; -} - -phys_size_t initdram (int board_type) -{ - int m, row, col, bank, i, ref; - unsigned long start, end; - uint32_t mccr1, mccr2; - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; - uint8_t mber = 0; - unsigned int tmp; - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - if (i2c_reg_read (0x50, 2) != 0x04) - return 0; /* Memory type */ - - m = i2c_reg_read (0x50, 5); /* # of physical banks */ - row = i2c_reg_read (0x50, 3); /* # of rows */ - col = i2c_reg_read (0x50, 4); /* # of columns */ - bank = i2c_reg_read (0x50, 17); /* # of logical banks */ - ref = i2c_reg_read (0x50, 12); /* refresh rate / type */ - - CONFIG_READ_WORD(MCCR1, mccr1); - mccr1 &= 0xffff0000; - - CONFIG_READ_WORD(MCCR2, mccr2); - mccr2 &= 0xffff0000; - - start = CONFIG_SYS_SDRAM_BASE; - end = start + (1 << (col + row + 3) ) * bank - 1; - - for (i = 0; i < m; i++) { - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; - if (i < 4) { - msar1 |= ((start >> 20) & 0xff) << i * 8; - emsar1 |= ((start >> 28) & 0xff) << i * 8; - mear1 |= ((end >> 20) & 0xff) << i * 8; - emear1 |= ((end >> 28) & 0xff) << i * 8; - } else { - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; - } - mber |= 1 << i; - start += (1 << (col + row + 3) ) * bank; - end += (1 << (col + row + 3) ) * bank; - } - for (; i < 8; i++) { - if (i < 4) { - msar1 |= 0xff << i * 8; - emsar1 |= 0x30 << i * 8; - mear1 |= 0xff << i * 8; - emear1 |= 0x30 << i * 8; - } else { - msar2 |= 0xff << (i-4) * 8; - emsar2 |= 0x30 << (i-4) * 8; - mear2 |= 0xff << (i-4) * 8; - emear2 |= 0x30 << (i-4) * 8; - } - } - - switch(ref) { - case 0x00: - case 0x80: - tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22; - break; - case 0x01: - case 0x81: - tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22; - break; - case 0x02: - case 0x82: - tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22; - break; - case 0x03: - case 0x83: - tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22; - break; - case 0x04: - case 0x84: - tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22; - break; - case 0x05: - case 0x85: - tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22; - break; - default: - tmp = 0x512; - break; - } - - CONFIG_WRITE_WORD(MCCR1, mccr1); - CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT); - CONFIG_WRITE_WORD(MSAR1, msar1); - CONFIG_WRITE_WORD(EMSAR1, emsar1); - CONFIG_WRITE_WORD(MEAR1, mear1); - CONFIG_WRITE_WORD(EMEAR1, emear1); - CONFIG_WRITE_WORD(MSAR2, msar2); - CONFIG_WRITE_WORD(EMSAR2, emsar2); - CONFIG_WRITE_WORD(MEAR2, mear2); - CONFIG_WRITE_WORD(EMEAR2, emear2); - CONFIG_WRITE_BYTE(MBER, mber); - - return (1 << (col + row + 3) ) * bank * m; -} - - -/* - * Initialize PCI Devices, report devices found. - */ - -static struct pci_config_table pci_cpc45_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR, - PCI_PLX9030_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCMCIA_IO_BASE, - PCMCIA_IO_BASE, - PCI_COMMAND_MEMORY | PCI_COMMAND_IO }}, -#endif /*CONFIG_PCI_PNP*/ - { } -}; - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_cpc45_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); - - /* init PCI_to_LOCAL Bus BRIDGE */ - Plx9030Init(); - - /* Clear Display */ - DISP_CWORD = 0x0; - - sysControlDisplay(0,' '); - sysControlDisplay(1,'C'); - sysControlDisplay(2,'P'); - sysControlDisplay(3,'C'); - sysControlDisplay(4,' '); - sysControlDisplay(5,'4'); - sysControlDisplay(6,'5'); - sysControlDisplay(7,' '); - -} - -/************************************************************************** -* -* sysControlDisplay - controls one of the Alphanum. Display digits. -* -* This routine will write an ASCII character to the display digit requested. -* -* SEE ALSO: -* -* RETURNS: NA -*/ - -int sysControlDisplay (int digit, /* number of digit 0..7 */ - uchar ascii_code /* ASCII code */ - ) -{ - if ((digit < 0) || (digit > 7)) - return (-1); - - *((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code; - - return (0); -} - -#if defined(CONFIG_CMD_PCMCIA) - -#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init(void) -{ - u_int rc; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - rc = i82365_init(); - - return rc; -} - -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c deleted file mode 100644 index 917db34a4b..0000000000 --- a/board/cpc45/flash.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x40000 -#define PARAM_SECT_SIZE 0x8000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static int write_data (flash_info_t * info, ulong dest, ulong * data); -static void write_via_fpu (vu_long * addr, ulong * data); -static __inline__ unsigned long get_msr (void); -static __inline__ void set_msr (unsigned long msr); - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -/*---------------------------------------------------------------------*/ -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - uchar tempChar; - vu_long *tmpaddr; - - /* Enable flash writes on CPC45 */ - - tempChar = BOARD_CTRL; - - tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1); - - tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0); - - BOARD_CTRL = tempChar; - - __asm__ volatile ("sync\n eieio"); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0] = 0x00900090; - - __asm__ volatile ("sync\n eieio"); - - udelay (100); - - DEBUGF ("Flash bank # %d:\n" - "\tManuf. ID @ 0x%08lX: 0x%08lX\n" - "\tDevice ID @ 0x%08lX: 0x%08lX\n", - i, - (ulong) (&addr[0]), addr[0], - (ulong) (&addr[2]), addr[2]); - - - if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && - (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) { - - flash_info[i].flash_id = - (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160F3T & FLASH_TYPEMASK); - - } else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) - && (addr[2] == addr[3]) - && (addr[2] == INTEL_ID_28F160C3T)) { - - flash_info[i].flash_id = - (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160C3T & FLASH_TYPEMASK); - - } else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFFFFFFFF; - goto Done; - } - - DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); - - addr[0] = 0xFFFFFFFF; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j > 30) { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + - i * FLASH_BANK_SIZE + - (MAIN_SECT_SIZE * 31) + (j - - 31) * - PARAM_SECT_SIZE; - } else { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + - i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE; - } - } - - /* unlock sectors, if 160C3T */ - - for (j = 0; j < flash_info[i].sector_count; j++) { - tmpaddr = (vu_long *) flash_info[i].start[j]; - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) { - tmpaddr[0] = 0x00600060; - tmpaddr[0] = 0x00D000D0; - tmpaddr[1] = 0x00600060; - tmpaddr[1] = 0x00D000D0; - } - } - - size += flash_info[i].size; - - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#else - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); -#else - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif -#endif - -Done: - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch ((i = info->flash_id & FLASH_VENDMASK)) { - case (FLASH_MAN_INTEL & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor 0x%04x ", i); - break; - } - - switch ((i = info->flash_id & FLASH_TYPEMASK)) { - case (INTEL_ID_28F160F3T & FLASH_TYPEMASK): - printf ("28F160F3T (16Mbit)\n"); - break; - - case (INTEL_ID_28F160C3T & FLASH_TYPEMASK): - printf ("28F160C3T (16Mbit)\n"); - break; - - default: - printf ("Unknown Chip Type 0x%04x\n", i); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - DEBUGF ("Erase flash bank %d sect %d ... %d\n", - info - &flash_info[0], s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (FLASH_MAN_INTEL & FLASH_VENDMASK)) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - - DEBUGF ("Erase sect %d @ 0x%08lX\n", - sect, (ulong) addr); - - /* Disable interrupts which might cause a timeout - * here. - */ - flag = disable_interrupts (); - - addr[0] = 0x00500050; /* clear status register */ - addr[0] = 0x00200020; /* erase setup */ - addr[0] = 0x00D000D0; /* erase confirm */ - - addr[1] = 0x00500050; /* clear status register */ - addr[1] = 0x00200020; /* erase setup */ - addr[1] = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080)) { - if ((now = get_timer (start)) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0x00B000B0; /* suspend erase */ - addr[0] = 0x00FF00FF; /* to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - addr[0] = 0x00FF00FF; - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 8 /* flash bus width in bytes */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, cp, msr; - int l, rc, i; - ulong data[2]; - ulong *datah = &data[0]; - ulong *datal = &data[1]; - - DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", - addr, (ulong) src, cnt); - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - msr = get_msr (); - set_msr (msr | MSR_FP); - - wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - *datah = *datal = 0; - - for (i = 0, cp = wp; i < l; i++, cp++) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *) cp); - } - for (; i < FLASH_WIDTH && cnt > 0; ++i) { - char tmp = *src++; - - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datah << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - set_msr (msr); - return (rc); - } - - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - *datah = *(ulong *) src; - *datal = *(ulong *) (src + 4); - if ((rc = write_data (info, wp, data)) != 0) { - set_msr (msr); - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - src += FLASH_WIDTH; - } - - if (cnt == 0) { - set_msr (msr); - return (0); - } - - /* - * handle unaligned tail bytes - */ - *datah = *datal = 0; - for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { - char tmp = *src++; - - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> - 24); - } - - *datal = (*datal << 8) | tmp; - --cnt; - } - - for (; i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> - 24); - } - - *datal = (*datal << 8) | (*(uchar *) cp); - } - - rc = write_data (info, wp, data); - set_msr (msr); - - return (rc); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, ulong * data) -{ - vu_long *addr = (vu_long *) dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if (((addr[0] & data[0]) != data[0]) || - ((addr[1] & data[1]) != data[1])) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0] = 0x00400040; /* write setup */ - write_via_fpu (addr, data); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - addr[0] = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - addr[0] = 0x00FF00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu (vu_long * addr, ulong * data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); -} - -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); -} diff --git a/board/cpc45/ide.c b/board/cpc45/ide.c deleted file mode 100644 index 448d887b3a..0000000000 --- a/board/cpc45/ide.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define EIEIO __asm__ volatile ("eieio") -#define SYNC __asm__ volatile ("sync") - -void ide_input_swap_data(int dev, ulong *sect_buf, int words) -{ - uchar i; - volatile uchar *pbuf_even = - (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - volatile uchar *pbuf_odd = - (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - ushort *dbuf = (ushort *) sect_buf; - - while (words--) { - for (i = 0; i < 2; i++) { - *(((uchar *) (dbuf)) + 1) = *pbuf_even; - *(uchar *) dbuf = *pbuf_odd; - dbuf += 1; - } - } -} - -void ide_input_data(int dev, ulong *sect_buf, int words) -{ - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (words--) { - *dbuf++ = *pbuf_even; - EIEIO; - SYNC; - *dbuf++ = *pbuf_odd; - EIEIO; - SYNC; - *dbuf++ = *pbuf_even; - EIEIO; - SYNC; - *dbuf++ = *pbuf_odd; - EIEIO; - SYNC; - } -} - -void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) -{ - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (shorts--) { - EIEIO; - *dbuf++ = *pbuf_even; - EIEIO; - *dbuf++ = *pbuf_odd; - } -} - -void ide_output_data(int dev, const ulong *sect_buf, int words) -{ - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (words--) { - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - } -} - -void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) -{ - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (shorts--) { - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - } -} - -void ide_led(uchar led, uchar status) -{ - u_char val; - /* We have one PCMCIA slot and use LED H4 for the IDE Interface */ - val = readb(BCSR_BASE + 0x04); - if (status) /* led on */ - val |= B_CTRL_LED0; - else - val &= ~B_CTRL_LED0; - - writeb(val, BCSR_BASE + 0x04); -} - diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c deleted file mode 100644 index 23d87f6825..0000000000 --- a/board/cpc45/pd67290.c +++ /dev/null @@ -1,797 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - ******************************************************************** - * - * Lots of code copied from: - * - * i82365.c 1.352 - Linux driver for Intel 82365 and compatible - * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. - * (C) 1999 David A. Hinds - */ - -#include - -#ifdef CONFIG_I82365 - -#include -#include -#include -#include - -#include -#include -#include -#include - -static struct pci_device_id supported[] = { - {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, - {0, 0} -}; - -#define CYCLE_TIME 120 - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev); -#endif - -typedef struct socket_info_t { - pci_dev_t dev; - u_short bcr; - u_char pci_lat, cb_lat, sub_bus, cache; - u_int cb_phys; - - socket_cap_t cap; - u_short type; - u_int flags; - cirrus_state_t c_state; -} socket_info_t; - -/* These definitions must match the pcic table! */ -typedef enum pcic_id { - IS_PD6710, IS_PD672X, IS_VT83C469 -} pcic_id; - -typedef struct pcic_t { - char *name; -} pcic_t; - -static pcic_t pcic[] = { - {" Cirrus PD6710: "}, - {" Cirrus PD672x: "}, - {" VIA VT83C469: "}, -}; - -static socket_info_t socket; -static socket_state_t state; -static struct pccard_mem_map mem; -static struct pccard_io_map io; - -/*====================================================================*/ - -/* Some PCI shortcuts */ - -static int pci_readb (socket_info_t * s, int r, u_char * v) -{ - return pci_read_config_byte (s->dev, r, v); -} -static int pci_writeb (socket_info_t * s, int r, u_char v) -{ - return pci_write_config_byte (s->dev, r, v); -} -static int pci_readw (socket_info_t * s, int r, u_short * v) -{ - return pci_read_config_word (s->dev, r, v); -} -static int pci_writew (socket_info_t * s, int r, u_short v) -{ - return pci_write_config_word (s->dev, r, v); -} - -/*====================================================================*/ - -#define cb_readb(s) readb((s)->cb_phys + 1) -#define cb_writeb(s, v) writeb(v, (s)->cb_phys) -#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1) -#define cb_readl(s, r) readl((s)->cb_phys + (r)) -#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) - - -static u_char i365_get (socket_info_t * s, u_short reg) -{ - u_char val; -#ifdef CONFIG_PCMCIA_SLOT_A - int slot = 0; -#else - int slot = 1; -#endif - - val = I365_REG (slot, reg); - - cb_writeb (s, val); - val = cb_readb (s); - - debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val); - return val; -} - -static void i365_set (socket_info_t * s, u_short reg, u_char data) -{ -#ifdef CONFIG_PCMCIA_SLOT_A - int slot = 0; -#else - int slot = 1; -#endif - u_char val; - - val = I365_REG (slot, reg); - - cb_writeb (s, val); - cb_writeb2 (s, data); - - debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data); -} - -static void i365_bset (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) | mask); -} - -static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) & ~mask); -} - -#if 0 /* not used */ -static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) -{ - u_char d = i365_get (s, reg); - - i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); -} - -static u_short i365_get_pair (socket_info_t * s, u_short reg) -{ - return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); -} -#endif /* not used */ - -static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) -{ - i365_set (s, reg, data & 0xff); - i365_set (s, reg + 1, data >> 8); -} - -/*====================================================================== - - Code to save and restore global state information for Cirrus - PD67xx controllers, and to set and report global configuration - options. - -======================================================================*/ - -#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) - -static void cirrus_get_state (socket_info_t * s) -{ - int i; - cirrus_state_t *p = &s->c_state; - - p->misc1 = i365_get (s, PD67_MISC_CTL_1); - p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); - p->misc2 = i365_get (s, PD67_MISC_CTL_2); - for (i = 0; i < 6; i++) - p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i); - -} - -static void cirrus_set_state (socket_info_t * s) -{ - int i; - u_char misc; - cirrus_state_t *p = &s->c_state; - - misc = i365_get (s, PD67_MISC_CTL_2); - i365_set (s, PD67_MISC_CTL_2, p->misc2); - if (misc & PD67_MC2_SUSPEND) - udelay (50000); - misc = i365_get (s, PD67_MISC_CTL_1); - misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); - i365_set (s, PD67_MISC_CTL_1, misc | p->misc1); - for (i = 0; i < 6; i++) - i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]); -} - -static u_int cirrus_set_opts (socket_info_t * s) -{ - cirrus_state_t *p = &s->c_state; - u_int mask = 0xffff; - char buf[200] = {0}; - - if (has_ring == -1) - has_ring = 1; - flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring); - flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); -#if DEBUG - if (p->misc2 & PD67_MC2_IRQ15_RI) - strcat (buf, " [ring]"); - if (p->misc2 & PD67_MC2_DYNAMIC_MODE) - strcat (buf, " [dyn mode]"); - if (p->misc1 & PD67_MC1_INPACK_ENA) - strcat (buf, " [inpack]"); -#endif - - if (p->misc2 & PD67_MC2_IRQ15_RI) - mask &= ~0x8000; - if (has_led > 0) { -#if DEBUG - strcat (buf, " [led]"); -#endif - mask &= ~0x1000; - } - if (has_dma > 0) { -#if DEBUG - strcat (buf, " [dma]"); -#endif - mask &= ~0x0600; - flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); -#if DEBUG - if (p->misc2 & PD67_MC2_FREQ_BYPASS) - strcat (buf, " [freq bypass]"); -#endif - } - - if (setup_time >= 0) - p->timer[0] = p->timer[3] = setup_time; - if (cmd_time > 0) { - p->timer[1] = cmd_time; - p->timer[4] = cmd_time * 2 + 4; - } - if (p->timer[1] == 0) { - p->timer[1] = 6; - p->timer[4] = 16; - if (p->timer[0] == 0) - p->timer[0] = p->timer[3] = 1; - } - if (recov_time >= 0) - p->timer[2] = p->timer[5] = recov_time; - - debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n", - buf, - p->timer[0], p->timer[1], p->timer[2], - p->timer[3], p->timer[4], p->timer[5]); - - return mask; -} - -/*====================================================================== - - Routines to handle common CardBus options - -======================================================================*/ - -/* Default settings for PCI command configuration register */ -#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ - PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) - -static void cb_get_state (socket_info_t * s) -{ - pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); - pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); - pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); - pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); - pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); - pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); -} - -static void cb_set_state (socket_info_t * s) -{ - pci_writew (s, PCI_COMMAND, CMD_DFLT); - pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); - pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); - pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); - pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); - pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); - pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); -} - -static void cb_set_opts (socket_info_t * s) -{ -} - -/*====================================================================== - - Power control for Cardbus controllers: used both for 16-bit and - Cardbus cards. - -======================================================================*/ - -static int cb_set_power (socket_info_t * s, socket_state_t * state) -{ - u_int reg = 0; - - reg = I365_PWR_NORESET; - if (state->flags & SS_PWR_AUTO) - reg |= I365_PWR_AUTO; - if (state->flags & SS_OUTPUT_ENA) - reg |= I365_PWR_OUT; - if (state->Vpp != 0) { - if (state->Vpp == 120) { - reg |= I365_VPP1_12V; - puts (" 12V card found: "); - } else if (state->Vpp == state->Vcc) { - reg |= I365_VPP1_5V; - } else { - puts (" power not found: "); - return -1; - } - } - if (state->Vcc != 0) { - reg |= I365_VCC_5V; - if (state->Vcc == 33) { - puts (" 3.3V card found: "); - i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else if (state->Vcc == 50) { - puts (" 5V card found: "); - i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else { - puts (" power not found: "); - return -1; - } - } - - if (reg != i365_get (s, I365_POWER)) { - reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V); - i365_set (s, I365_POWER, reg); - } - - return 0; -} - -/*====================================================================== - - Generic routines to get and set controller options - -======================================================================*/ - -static void get_bridge_state (socket_info_t * s) -{ - cirrus_get_state (s); - cb_get_state (s); -} - -static void set_bridge_state (socket_info_t * s) -{ - cb_set_state (s); - i365_set (s, I365_GBLCTL, 0x00); - i365_set (s, I365_GENCTL, 0x00); - cirrus_set_state (s); -} - -static void set_bridge_opts (socket_info_t * s) -{ - cirrus_set_opts (s); - cb_set_opts (s); -} - -/*====================================================================*/ -#define PD67_EXT_INDEX 0x2e /* Extension index */ -#define PD67_EXT_DATA 0x2f /* Extension data */ -#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) - -#define pd67_ext_get(s, r) \ - (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) - -static int i365_get_status (socket_info_t * s, u_int * value) -{ - u_int status; - u_char val; - u_char power, vcc, vpp; - u_int powerstate; - - status = i365_get (s, I365_IDENT); - status = i365_get (s, I365_STATUS); - *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; - if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { - *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; - } else { - *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; - *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; - } - *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; - *value |= (status & I365_CS_READY) ? SS_READY : 0; - *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; - - /* Check for Cirrus CL-PD67xx chips */ - i365_set (s, PD67_CHIP_INFO, 0); - val = i365_get (s, PD67_CHIP_INFO); - s->type = -1; - if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { - val = i365_get (s, PD67_CHIP_INFO); - if ((val & PD67_INFO_CHIP_ID) == 0) { - s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; - i365_set (s, PD67_EXT_INDEX, 0xe5); - if (i365_get (s, PD67_EXT_INDEX) != 0xe5) - s->type = IS_VT83C469; - } - } else { - printf ("no Cirrus Chip found\n"); - *value = 0; - return -1; - } - - power = i365_get (s, I365_POWER); - state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; - state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; - vcc = power & I365_VCC_MASK; - vpp = power & I365_VPP1_MASK; - state.Vcc = state.Vpp = 0; - if((vcc== 0) || (vpp == 0)) { - /* - * On the Cirrus we get the info which card voltage - * we have in EXTERN DATA and write it to MISC_CTL1 - */ - powerstate = pd67_ext_get(s, PD67_EXTERN_DATA); - if (powerstate & PD67_EXD_VS1(0)) { - /* 5V Card */ - i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else { - /* 3.3V Card */ - i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } - i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V)); - power = i365_get (s, I365_POWER); - } - if (power & I365_VCC_5V) { - state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50; - } - - if (power == I365_VPP1_12V) - state.Vpp = 120; - - /* IO card, RESET flags, IO interrupt */ - power = i365_get (s, I365_INTCTL); - state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET; - if (power & I365_PC_IOCARD) - state.flags |= SS_IOCARD; - state.io_irq = power & I365_IRQ_MASK; - - /* Card status change mask */ - power = i365_get (s, I365_CSCINT); - state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0; - if (state.flags & SS_IOCARD) - state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0; - else { - state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0; - state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0; - state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0; - } - debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, " - "io_irq %d, csc_mask %#2.2x\n", state.flags, - state.Vcc, state.Vpp, state.io_irq, state.csc_mask); - - return 0; -} /* i365_get_status */ - -static int i365_set_socket (socket_info_t * s, socket_state_t * state) -{ - u_char reg; - - set_bridge_state (s); - - /* IO card, RESET flag */ - reg = 0; - reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; - reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; - i365_set (s, I365_INTCTL, reg); - - cb_set_power (s, state); - -#if 0 - /* Card status change interrupt mask */ - reg = s->cs_irq << 4; - if (state->csc_mask & SS_DETECT) - reg |= I365_CSC_DETECT; - if (state->flags & SS_IOCARD) { - if (state->csc_mask & SS_STSCHG) - reg |= I365_CSC_STSCHG; - } else { - if (state->csc_mask & SS_BATDEAD) - reg |= I365_CSC_BVD1; - if (state->csc_mask & SS_BATWARN) - reg |= I365_CSC_BVD2; - if (state->csc_mask & SS_READY) - reg |= I365_CSC_READY; - } - i365_set (s, I365_CSCINT, reg); - i365_get (s, I365_CSC); -#endif /* 0 */ - - return 0; -} /* i365_set_socket */ - -/*====================================================================*/ - -static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) -{ - u_short base, i; - u_char map; - - debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", - mem->map, mem->flags, mem->speed, - mem->sys_start, mem->sys_stop, mem->card_start); - - map = mem->map; - if ((map > 4) || - (mem->card_start > 0x3ffffff) || - (mem->sys_start > mem->sys_stop) || - (mem->speed > 1000)) { - return -1; - } - - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); - - /* Take care of high byte, for PCI controllers */ - i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); - - base = I365_MEM (map); - i = (mem->sys_start >> 12) & 0x0fff; - if (mem->flags & MAP_16BIT) - i |= I365_MEM_16BIT; - if (mem->flags & MAP_0WS) - i |= I365_MEM_0WS; - i365_set_pair (s, base + I365_W_START, i); - - i = (mem->sys_stop >> 12) & 0x0fff; - switch (mem->speed / CYCLE_TIME) { - case 0: - break; - case 1: - i |= I365_MEM_WS0; - break; - case 2: - i |= I365_MEM_WS1; - break; - default: - i |= I365_MEM_WS1 | I365_MEM_WS0; - break; - } - i365_set_pair (s, base + I365_W_STOP, i); - - i = 0; - if (mem->flags & MAP_WRPROT) - i |= I365_MEM_WRPROT; - if (mem->flags & MAP_ATTRIB) - i |= I365_MEM_REG; - i365_set_pair (s, base + I365_W_OFF, i); - - /* set System Memory map Upper Adress */ - i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map)); - i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff)); - - /* Turn on the window if necessary */ - if (mem->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); - return 0; -} /* i365_set_mem_map */ - -static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) -{ - u_char map, ioctl; - - map = io->map; - /* comment out: comparison is always false due to limited range of data type */ - if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ - (io->stop < io->start)) - return -1; - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); - i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); - i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); - ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); - if (io->speed) - ioctl |= I365_IOCTL_WAIT (map); - if (io->flags & MAP_0WS) - ioctl |= I365_IOCTL_0WS (map); - if (io->flags & MAP_16BIT) - ioctl |= I365_IOCTL_16BIT (map); - if (io->flags & MAP_AUTOSZ) - ioctl |= I365_IOCTL_IOCS16 (map); - i365_set (s, I365_IOCTL, ioctl); - /* Turn on the window if necessary */ - if (io->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); - return 0; -} /* i365_set_io_map */ - -/*====================================================================*/ - -/* - * PCI_ADDR = (HOST_ADDR - 0xfe000000) - * see MPC 8245 Users Manual Adress Map B - */ -#define HOST_TO_PCI(addr) ((addr) - 0xfe000000) -#define PCI_TO_HOST(addr) ((addr) + 0xfe000000) - -static int i82365_init (void) -{ - u_int val; - int i; - - if ((socket.dev = pci_find_devices (supported, 0)) < 0) { - /* Controller not found */ - printf ("No PD67290 device found !!\n"); - return 1; - } - debug ("i82365 Device Found!\n"); - - socket.cb_phys = PCMCIA_IO_BASE; - - /* set base address */ - pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0, - HOST_TO_PCI(socket.cb_phys)); - - /* enable mapped memory and IO addresses */ - pci_write_config_dword (socket.dev, - PCI_COMMAND, - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | PCI_COMMAND_WAIT); - - get_bridge_state (&socket); - set_bridge_opts (&socket); - - i = i365_get_status (&socket, &val); - - if (i > -1) { - puts (pcic[socket.type].name); - } else { - printf ("i82365: Controller not found.\n"); - return 1; - } - if((val & SS_DETECT) != SS_DETECT){ - puts ("No card\n"); - return 1; - } - - state.flags |= SS_OUTPUT_ENA; - - i365_set_socket (&socket, &state); - - for (i = 500; i; i--) { - if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) - break; - udelay (1000); - } - - if (i == 0) { - /* PC Card not ready for data transfer */ - puts ("i82365 PC Card not ready for data transfer\n"); - return 1; - } - debug (" PC Card ready for data transfer: "); - - mem.map = 0; - mem.flags = MAP_ATTRIB | MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - - mem.map = 1; - mem.flags = MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - -#ifdef DEBUG - i82365_dump_regions (socket.dev); -#endif - - return 0; -} - -static void i82365_exit (void) -{ - io.map = 0; - io.flags = 0; - io.speed = 0; - io.start = 0; - io.stop = 0x1; - - i365_set_io_map (&socket, &io); - - mem.map = 0; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); - - mem.map = 1; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); - - state.Vcc = state.Vpp = 0; - - i365_set_socket (&socket, &state); -} - -int pcmcia_on (void) -{ - u_int rc; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - rc = i82365_init(); - if (rc) - goto exit; - - rc = check_ide_device(0); - if (rc == 0) - goto exit; - - i82365_exit(); - -exit: - return rc; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_off (void) -{ - printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - i82365_exit(); - - return 0; -} -#endif - -/*====================================================================== - - Debug stuff - -======================================================================*/ - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev) -{ - u_int tmp[2]; - u_int *mem = (void *) socket.cb_phys; - u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR; - u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET); - - pci_read_config_dword (dev, 0x00, tmp + 0); - pci_read_config_dword (dev, 0x80, tmp + 1); - - printf ("PCI CONF: %08X ... %08X\n", - tmp[0], tmp[1]); - printf ("PCI MEM: ... %08X ... %08X\n", - mem[0x8 / 4], mem[0x800 / 4]); - printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", - cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], - cis[0x40], cis[0x42], cis[0x44], cis[0x48]); - printf ("CIS CONF: %02X %02X %02X ...\n", - cis[0x200], cis[0x202], cis[0x204]); - printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", - ide[0], ide[1], ide[2], ide[3], - ide[4], ide[5], ide[6], ide[7]); -} -#endif /* DEBUG */ - -#endif /* CONFIG_I82365 */ diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c deleted file mode 100644 index 06fb8d6c9a..0000000000 --- a/board/cpc45/plx9030.c +++ /dev/null @@ -1,156 +0,0 @@ -/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */ -/* - * (C) Copyright 2002-2003 - * Josef Wagner, MicroSys GmbH, wagner@microsys.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * Date Modification by - * ------- ---------------------------------------------- --- - * 30sep02 converted from VxWorks to LINUX wa -*/ - - -/* -DESCRIPTION - -This is the configuration module for the PLX9030 PCI to Local Bus Bridge. -It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local -registers (CS3) on CPC45. -*/ - -/* includes */ - -#include -#include -#include -#include -#include - -/* imports */ - - -/* defines */ -#define PLX9030_VENDOR_ID 0x10B5 -#define PLX9030_DEVICE_ID 0x9030 - -#undef PLX_DEBUG - -/* PLX9030 register offsets */ -#define P9030_LAS0RR 0x00 -#define P9030_LAS1RR 0x04 -#define P9030_LAS2RR 0x08 -#define P9030_LAS3RR 0x0c -#define P9030_EROMRR 0x10 -#define P9030_LAS0BA 0x14 -#define P9030_LAS1BA 0x18 -#define P9030_LAS2BA 0x1c -#define P9030_LAS3BA 0x20 -#define P9030_EROMBA 0x24 -#define P9030_LAS0BRD 0x28 -#define P9030_LAS1BRD 0x2c -#define P9030_LAS2BRD 0x30 -#define P9030_LAS3BRD 0x34 -#define P9030_EROMBRD 0x38 -#define P9030_CS0BASE 0x3C -#define P9030_CS1BASE 0x40 -#define P9030_CS2BASE 0x44 -#define P9030_CS3BASE 0x48 -#define P9030_INTCSR 0x4c -#define P9030_CNTRL 0x50 -#define P9030_GPIOC 0x54 - -/* typedefs */ - - -/* locals */ - -static struct pci_device_id supported[] = { - { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID }, - { } -}; - -/* forward declarations */ -void sysOutLong(ulong address, ulong value); - - -/*************************************************************************** -* -* Plx9030Init - init CS0..CS3 for CPC45 -* -* -* RETURNS: N/A -*/ - -void Plx9030Init (void) -{ - pci_dev_t devno; - ulong membaseCsr; /* base address of device memory space */ - int idx = 0; /* general index */ - - - /* find plx9030 device */ - - if ((devno = pci_find_devices(supported, idx++)) < 0) - { - printf("No PLX9030 device found !!\n"); - return; - } - - -#ifdef PLX_DEBUG - printf("PLX 9030 device found ! devno = 0x%x\n",devno); -#endif - - membaseCsr = PCI_PLX9030_MEMADDR; - - /* set base address */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr); - - /* enable mapped memory and IO addresses */ - pci_write_config_dword(devno, - PCI_COMMAND, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - - - /* configure GBIOC */ - sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */ - - /* configure CS0 (SRAM) */ - sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */ - sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */ - /* remap CS0 (SRAM) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE); - - /* configure CS1 (ST16552 / CHAN A) */ - sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */ - /* remap CS1 (ST16552 / CHAN A) */ - /* remap CS1 (ST16552 / CHAN A) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE); - - /* configure CS2 (ST16552 / CHAN B) */ - sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */ - /* remap CS2 (ST16552 / CHAN B) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE); - - /* configure CS3 (BCSR) */ - sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */ - sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */ - /* remap CS3 (DISPLAY and BCSR) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE); -} - -void sysOutLong(ulong address, ulong value) -{ - *(ulong*)address = cpu_to_le32(value); -} diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/cpu86/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c deleted file mode 100644 index 929291052f..0000000000 --- a/board/cpu86/cpu86.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "cpu86.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ - /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ - /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ - /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - ulong size8, size9; -#endif - long psize; - - psize = 32 * 1024 * 1024; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = CONFIG_SYS_PSRT; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL) "); - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h deleted file mode 100644 index ca0c39f6b8..0000000000 --- a/board/cpu86/cpu86.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __BOARD_CPU86__ -#define __BOARD_CPU86__ - -#include - -#define REG8(x) (*(volatile unsigned char *)(x)) - -/* CPU86 register definitions */ -#define CPU86_VME_EAC REG8(CONFIG_SYS_BCRS_BASE + 0x00) -#define CPU86_VME_SAC REG8(CONFIG_SYS_BCRS_BASE + 0x01) -#define CPU86_VME_MAC REG8(CONFIG_SYS_BCRS_BASE + 0x02) -#define CPU86_BCR REG8(CONFIG_SYS_BCRS_BASE + 0x03) -#define CPU86_BSR REG8(CONFIG_SYS_BCRS_BASE + 0x04) -#define CPU86_WDOG_RPORT REG8(CONFIG_SYS_BCRS_BASE + 0x05) -#define CPU86_MBOX_IRQ REG8(CONFIG_SYS_BCRS_BASE + 0x04) -#define CPU86_REV REG8(CONFIG_SYS_BCRS_BASE + 0x07) -#define CPU86_VME_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x80) -#define CPU86_VME_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x81) -#define CPU86_LOCAL_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x82) -#define CPU86_LOCAL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x83) -#define CPU86_PMCL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x84) - -/* Board Control Register bits */ -#define CPU86_BCR_FWPT 0x01 -#define CPU86_BCR_FWRE 0x02 - -#endif /* __BOARD_CPU86__ */ diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c deleted file mode 100644 index fd97c36d21..0000000000 --- a/board/cpu86/flash.c +++ /dev/null @@ -1,599 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include "cpu86.h" - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_int_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write identify command sequence and test FLASH answer - */ - baseaddr[0] = 0x00900090; - baseaddr[1] = 0x00900090; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3) - */ - for (i = 0; i < info->sector_count; i++) { - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info) -{ - short i; - uchar vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x90; - - udelay(1000); - - vendor = addr[0]; - devid = addr[1] & 0xff; - - /* only support AMD */ - if (vendor != 0x01) { - return 0; - } - - vendor &= 0xf; - devid &= 0xff; - - if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 8; - info->size = info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 16; - info->size = 4 * info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F016D) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = 4 * info->sector_count * 0x10000; - } - else { - printf ("## Unknown Flash Type: %02x\n", devid); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - unsigned long size_b1 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Disable flash protection */ - CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE); - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]); - - if (size_b0 > 0 || size_b1 > 0) { - - printf("("); - - if (size_b0 > 0) { - puts ("Bank#1 - "); - print_size (size_b0, (size_b1 > 0) ? ", " : ") "); - } - - if (size_b1 > 0) { - puts ("Bank#2 - "); - print_size (size_b1, ") "); - } - } - else { - printf ("## No FLASH found.\n"); - return 0; - } - /* protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE - if (size_b1) { - /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE - * but we shouldn't protect it. - */ - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] - ); - } -#else -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -#endif -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE - if (size_b1) { - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); - } -# else - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -# endif -#endif - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 Mbit, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 Mbit, bottom sector)\n"); - break; - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size < 0x100000) - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - else - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Check the type of erased flash - */ - if (info->flash_id >> 16 == 0x1) { - /* Erase AMD flash - */ - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto AMD_DONE; - - start = get_timer (0); - last = start; - addr = (vu_char *)(info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -AMD_DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - } else { - /* Erase Intel flash - */ - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); -static int write_byte (flash_info_t *info, ulong dest, uchar data); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, rc, cc = cnt, res = 0; - - if (info->flash_id >> 16 == 0x1) { - - /* Write to AMD 8-bit flash - */ - while (cnt > 0) { - if ((rc = write_byte(info, addr, *src)) != 0) { - return (rc); - } - addr++; - src++; - cnt--; - } - - return (0); - } else { - - /* Write to Intel 64-bit flash - */ - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cpu87/Makefile b/board/cpu87/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/cpu87/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c deleted file mode 100644 index 01f90d2ebb..0000000000 --- a/board/cpu87/cpu87.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "cpu87.h" -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ - /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ - /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ - /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - ulong size8, size9, size10; -#endif - long psize; - - psize = 32 * 1024 * 1024; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = CONFIG_SYS_PSRT; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - psize = max(size8,max(size9,size10)); - - if (psize == size8) { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL) "); - } else if (psize == size9){ - psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:9COL) "); - } else - printf ("(60x:10COL) "); - -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h deleted file mode 100644 index 45cb853a26..0000000000 --- a/board/cpu87/cpu87.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __BOARD_CPU87__ -#define __BOARD_CPU87__ - -#include - -#define REG8(x) (*(volatile unsigned char *)(x)) - -/* CPU86 register definitions */ -#define CPU86_VME_EAC REG8(CONFIG_SYS_BCRS_BASE + 0x00) -#define CPU86_VME_SAC REG8(CONFIG_SYS_BCRS_BASE + 0x01) -#define CPU86_VME_MAC REG8(CONFIG_SYS_BCRS_BASE + 0x02) -#define CPU86_BCR REG8(CONFIG_SYS_BCRS_BASE + 0x03) -#define CPU86_BSR REG8(CONFIG_SYS_BCRS_BASE + 0x04) -#define CPU86_WDOG_RPORT REG8(CONFIG_SYS_BCRS_BASE + 0x05) -#define CPU86_MBOX_IRQ REG8(CONFIG_SYS_BCRS_BASE + 0x04) -#define CPU86_REV REG8(CONFIG_SYS_BCRS_BASE + 0x07) -#define CPU86_VME_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x80) -#define CPU86_VME_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x81) -#define CPU86_LOCAL_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x82) -#define CPU86_LOCAL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x83) -#define CPU86_PMCL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x84) - -/* Board Control Register bits */ -#define CPU86_BCR_FWPT 0x01 -#define CPU86_BCR_FWRE 0x02 - -#endif /* __BOARD_CPU87__ */ diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c deleted file mode 100644 index 79ec7e8ee5..0000000000 --- a/board/cpu87/flash.c +++ /dev/null @@ -1,608 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include "cpu87.h" - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_int_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write identify command sequence and test FLASH answer - */ - baseaddr[0] = 0x00900090; - baseaddr[1] = 0x00900090; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F640C3B: - info->flash_id = FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3) - */ - for (i = 0; i < info->sector_count; i++) { - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info) -{ - short i; - uchar vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x90; - - udelay(1000); - - vendor = addr[0]; - devid = addr[1] & 0xff; - - /* only support AMD */ - if (vendor != 0x01) { - return 0; - } - - vendor &= 0xf; - devid &= 0xff; - - if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 8; - info->size = info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 16; - info->size = 4 * info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F016D) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = 4 * info->sector_count * 0x10000; - } - else { - printf ("## Unknown Flash Type: %02x\n", devid); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - unsigned long size_b1 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Disable flash protection */ - CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE); - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]); - - if (size_b0 > 0 || size_b1 > 0) { - - printf("("); - - if (size_b0 > 0) { - puts ("Bank#1 - "); - print_size (size_b0, (size_b1 > 0) ? ", " : ") "); - } - - if (size_b1 > 0) { - puts ("Bank#2 - "); - print_size (size_b1, ") "); - } - } - else { - printf ("## No FLASH found.\n"); - return 0; - } - /* protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE - if (size_b1) { - /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE - * but we shouldn't protect it. - */ - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] - ); - } -#else -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -#endif -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE - if (size_b1) { - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); - } -# else - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -# endif -#endif - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 Mbit, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 Mbit, bottom sector)\n"); - break; - case FLASH_28F640C3B: - printf ("28F640C3B (64 M, bottom sector)\n"); - break; - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size < 0x100000) - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - else - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Check the type of erased flash - */ - if (info->flash_id >> 16 == 0x1) { - /* Erase AMD flash - */ - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto AMD_DONE; - - start = get_timer (0); - last = start; - addr = (vu_char *)(info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -AMD_DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - } else { - /* Erase Intel flash - */ - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); -static int write_byte (flash_info_t *info, ulong dest, uchar data); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, rc, cc = cnt, res = 0; - - if (info->flash_id >> 16 == 0x1) { - - /* Write to AMD 8-bit flash - */ - while (cnt > 0) { - if ((rc = write_byte(info, addr, *src)) != 0) { - return (rc); - } - addr++; - src++; - cnt--; - } - - return (0); - } else { - - /* Write to Intel 64-bit flash - */ - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c deleted file mode 100644 index d706ff10d3..0000000000 --- a/board/cray/L1/L1.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define L1_MEMSIZE (32*1024*1024) - -/* the std. DHCP stufff */ -#define DHCP_ROUTER 3 -#define DHCP_NETMASK 1 -#define DHCP_BOOTFILE 67 -#define DHCP_ROOTPATH 17 -#define DHCP_HOSTNAME 12 - -/* some extras used by CRAY - * - * on the server this looks like: - * - * option L1-initrd-image code 224 = string; - * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image" - */ -#define DHCP_L1_INITRD 224 - -/* new, [better?] way via official vendor-extensions, defining an option - * space. - * on the server this looks like: - * - * option space CRAYL1; - * option CRAYL1.initrd code 3 = string; - * ..etc... - */ -#define DHCP_VENDOR_SPECX 43 -#define DHCP_VX_INITRD 3 -#define DHCP_VX_BOOTCMD 4 -#define DHCP_VX_BOOTARGS 5 -#define DHCP_VX_ROOTDEV 6 -#define DHCP_VX_FROMFLASH 7 -#define DHCP_VX_BOOTSCRIPT 8 -#define DHCP_VX_RCFILE 9 -#define DHCP_VX_MAGIC 10 - -/* Things DHCP server can tellme about. If there's no flash address, then - * they dont participate in 'update' to flash, and we force their values - * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I - * know this is a pain... - * - * If I get no bootfile, boot from flash. If rootpath, use that. If no - * rootpath use initrd in flash. - */ -typedef struct dhcp_item_s { - u8 dhcp_option; - u8 dhcp_vendor_option; - char *dhcpvalue; - char *envname; -} dhcp_item_t; -static dhcp_item_t Things[] = { - {DHCP_ROUTER, 0, NULL, "gateway"}, - {DHCP_NETMASK, 0, NULL, "netmask"}, - {DHCP_BOOTFILE, 0, NULL, "bootfile"}, - {DHCP_ROOTPATH, 0, NULL, "rootpath"}, - {DHCP_HOSTNAME, 0, NULL, "hostname"}, - {DHCP_L1_INITRD, 0, NULL, "initrd"}, -/* and the other way.. */ - {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"}, - {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"}, - {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL}, - {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL} -}; - -#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) - -extern char bootscript[]; - -/* Here is the boot logic as HUSH script. Overridden by any TFP provided - * bootscript file. - */ - -static void init_sdram (void); - -/* ------------------------------------------------------------------------- */ -int board_early_init_f (void) -{ - /* Running from ROM: global data is still READONLY */ - init_sdram (); - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - return 0; -} - -/* ------------------------------------------------------------------------- */ -int checkboard (void) -{ - return (0); -} -/* ------------------------------------------------------------------------- */ - -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ - char *s, *e; - image_header_t *hdr; - time_t timestamp; - struct rtc_time tm; - char bootcmd[32]; - - hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ()); -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - timestamp = (time_t)image_get_time (hdr); - to_tm (timestamp, &tm); - printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); - -#define FACTORY_SETTINGS 0xFFFC0000 - if ((s = getenv ("ethaddr")) == NULL) { - e = (char *) (FACTORY_SETTINGS); - if (*(e + 0) != '0' - || *(e + 1) != '0' - || *(e + 2) != ':' - || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') { - printf ("No valid MAC address in flash location 0x3C0000!\n"); - } else { - printf ("Factory MAC: %s\n", e); - setenv ("ethaddr", e); - } - } - sprintf (bootcmd,"source %X",(unsigned)bootscript); - setenv ("bootcmd", bootcmd); - return (0); -} - -/* ------------------------------------------------------------------------- */ -/* stubs so we can print dates w/o any nvram RTC.*/ -int rtc_get (struct rtc_time *tmp) -{ - return 0; -} -int rtc_set (struct rtc_time *tmp) -{ - return 0; -} -void rtc_reset (void) -{ - return; -} - -/* ------------------------------------------------------------------------- */ -/* Do sdram bank init in C so I can read it..no console to print to yet! - */ -static void init_sdram (void) -{ - unsigned long tmp; - - /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - mtdcr (SDRAM0_CFGDATA, 0x00062001); - -/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ -/* To set the appropriate timings, we need to know the SDRAM speed. */ -/* We can use the PLB speed since the SDRAM speed is the same as */ -/* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25MHz. */ -/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ -/* 150MHz; if FBK is 3, SDRAM is 150MHz. */ - - /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ - -/* write SDRAM timing for 100MHz. */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - mtdcr (SDRAM0_CFGDATA, 0x0086400D); - -/* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - mtdcr (SDRAM0_CFGDATA, 0x05F00000); - udelay (200); - -/* sdram controller.*/ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, 0x90800000); - udelay (200); - -/* initially, disable ECC on all banks */ - udelay (200); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp &= 0xff0fffff; - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - mtdcr (SDRAM0_CFGDATA, tmp); - - return; -} - -extern int memory_post_test (int flags); - -int testdram (void) -{ - unsigned long tmp; - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) L1_MEMSIZE; - uint *p; - - if (getenv_f("booted",NULL,0) <= 0) - { - printf ("testdram.."); - /*AA*/ - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0xaaaaaaaa); - return 1; - } - } - /*55*/ - for (p = pstart; p < pend; p++) - *p = 0x55555555; - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0x55555555); - return 1; - } - } - /*addr*/ - for (p = pstart; p < pend; p++) - *p = (unsigned)p; - for (p = pstart; p < pend; p++) { - if (*p != (unsigned)p) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, (uint)p); - return 1; - } - } - printf ("Success. "); - } - printf ("Enable ECC.."); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (600); - for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) - ; - udelay (400); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp |= 0x00800000; - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (400); - printf ("enabled.\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ -static u8 *dhcp_env_update (u8 thing, u8 * pop) -{ - u8 i, oplen; - - oplen = *(pop + 1); - - if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) { - printf ("Whoops! failed to malloc space for DHCP thing %s\n", - Things[thing].envname); - return NULL; - } - for (i = 0; (i < oplen); i++) - if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ') - break; - *(Things[thing].dhcpvalue + i) = '\0'; - -/* set env. */ - if (Things[thing].envname) - { - setenv (Things[thing].envname, Things[thing].dhcpvalue); - } - return ((u8 *)(Things[thing].dhcpvalue)); -} - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_prep (u8 * e) -{ - u8 thing; - -/* ask for the things I want. */ - *e++ = 55; /* Parameter Request List */ - *e++ = N_THINGS; - for (thing = 0; thing < N_THINGS; thing++) - *e++ = Things[thing].dhcp_option; - *e++ = 255; - - return e; -} - -/* ------------------------------------------------------------------------- */ -/* .. return NULL means it wasnt mine, non-null means I got it..*/ -u8 *dhcp_vendorex_proc (u8 * pop) -{ - u8 oplen, *sub_op, sub_oplen, *retval; - u8 thing = 0; - - retval = NULL; - oplen = *(pop + 1); -/* if pop is vender spec indicator, there are sub-options. */ - if (*pop == DHCP_VENDOR_SPECX) { - for (sub_op = pop + 2; - oplen && (sub_oplen = *(sub_op + 1)); - oplen -= sub_oplen, sub_op += (sub_oplen + 2)) { - for (thing = 0; thing < N_THINGS; thing++) { - if (*sub_op == Things[thing].dhcp_vendor_option) { - if (!(retval = dhcp_env_update (thing, sub_op))) { - return NULL; - } - } - } - } - } else { - for (thing = 0; thing < N_THINGS; thing++) { - if (*pop == Things[thing].dhcp_option) - if (!(retval = dhcp_env_update (thing, pop))) - return NULL; - } - } - return (pop); -} diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h deleted file mode 100644 index 42c34dd910..0000000000 --- a/board/cray/L1/L1.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip - * - * Start Address Length - * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- - * | Failsafe Linux Image | (1M) - * +=======================+ 0xFFD0_0000 - * | (Reserved FlashFiles) | (1M) - * +=======================+ 0xFFE0_0000 - * | Failsafe RootFS | (1M) - * +=======================+ 0xFFF0_0000 - * | | - * | U N U S E D | - * | | - * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes) - * | environment settings | (64k) - * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes) - * | U-Boot | 0xFFFE_0040 _start of U-Boot - * | | 0xFFFE_FFFC reset vector - branch to _start - * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash ----------------- - *****************************************************************************/ diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile deleted file mode 100644 index 9e6461ace1..0000000000 --- a/board/cray/L1/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o -SOBJS = init.o - - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not -# built in the depend stage. So... put bootscript.o here, not in OBJS -$(LIB): $(OBJS) $(SOBJS) $(obj)bootscript.o - $(call cmd_link_o_target, $^) - -$(obj)$(BOARD).o : $(src)$(BOARD).c $(obj)bootscript.o - -$(obj)bootscript.c: $(obj)bootscript.image - od -t x1 -v -A x $^ | awk -f x2c.awk > $@ - -$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile - -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@ - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cray/L1/bootscript.hush b/board/cray/L1/bootscript.hush deleted file mode 100644 index f2f78ad5c3..0000000000 --- a/board/cray/L1/bootscript.hush +++ /dev/null @@ -1,117 +0,0 @@ -# $Header$ -# hush bootscript for PPCBOOT on L1 -# note: all #s are in hex, do _NOT_ prefix it with 0x - -flash_rfs=ffc00000 -flash_krl=fff00000 -tftp_addr=100000 -tftp2_addr=1000000 - -if printenv booted -then - echo already booted before -else - echo first boot in environment, create and save settings - setenv booted OK - saveenv -fi - -setenv autoload no -# clear out stale env stuff, so we get fresh from dhcp. -for setting in initrd fromflash kernel rootfs rootpath -do -setenv $setting -done - -dhcp - -# if host provides us with a different bootscript, us it. -if printenv bootscript - then - tftp $tftp_addr $bootcript - if imi $tftp_addr - then - source $tftp_addr - fi -fi - -# default base kernel arguments. -setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120 - -# Have a kernel in flash? -if imi $flash_krl -then - echo ok kernel to boot from $flash_krl - setenv kernel $flash_krl -else - echo no kernel to boot from $flash_krl, need tftp -fi - -# Have a rootfs in flash? -echo test for SQUASHfs at $flash_rfs - -if imi $flash_rfs -then - echo appears to be a good initrd image at base of flash OK - setenv rootfs $flash_rfs -else - echo no image at base of flash, need nfsroot or initrd -fi - -# I boot from flash if told to and I can. -if printenv fromflash && printenv kernel && printenv rootfs -then - echo booting entirely from flash - setenv bootargs root=/dev/ram0 rw $bootargs - bootm $kernel $rootfs - echo oh no failed so I try some other stuff -fi - -# TFTP down a kernel -if printenv bootfile -then - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - echo I will boot the TFTP kernel -else - if printenv kernel - then - echo no bootfile specified, will use one from flash - else - setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image - echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - fi -fi - -# the rootfs. -if printenv rootpath -then - echo rootpath is $rootpath - if printenv initrd - then - echo initrd is also specified, so use $initrd - tftp $tftp2_addr $initrd - setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs - bootm $kernel $tftp2_addr - else - echo initrd is not specified, so use NFSROOT $rootpat - setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs - bootm $kernel - fi -else - echo we have no rootpath check for one in flash - if printenv rootfs - then - echo I will use the one in flash - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - else - setenv rootpath /export/crayl1 - echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - fi -fi -reset diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c deleted file mode 100644 index 96a1e474a5..0000000000 --- a/board/cray/L1/flash.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -/* - * Modified July 20, 2001 - * Strip down to support ONLY the AMD29F032B. - * Dave Updegraff - Cray, Inc. dave@cray.com - */ - -#include -#include -#include - -/* The flash chip we use... */ -#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */ -#define FLASH_AM320B 0x0009 - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; isector_count; i++) - info->start[i] = base + (i * 0x00010000); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id += FLASH_AM320B; - info->sector_count = 64; - info->size = 0x0400000; /* => 4 MB */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S deleted file mode 100644 index 1662141488..0000000000 --- a/board/cray/L1/init.S +++ /dev/null @@ -1,140 +0,0 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code is dual-licensed. You may use it under the terms */ -/* of the GNU General Public License version 2, or under the license */ -/* below. */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*-----------------------------------------------------------------------------#include */ -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ -/* except for #1 which we use for DMA'ing to IOCA-like things, so the */ -/* control registers to set that up are determined by what we've */ -/* empirically discovered work there. */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*------------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 0 (Flash) initialization */ - /*---------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x9B01 - ori r4,r4,0x5480 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 1 (NVRAM/RTC) initialization */ - /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ - /* and we do DMA on it. The ConfigurationRegister part is threfore */ - /* almost arbitrary, except that our linux driver needs to know the */ - /* address, but it can query, it.. */ - /* */ - /* The AccessParameter is CRITICAL, */ - /* thouch, since it needs to agree with the electrical timings on the */ - /* IOCA parallel interface. That value is: 0x0185,4380 */ - /* BurstModeEnable BME=0 */ - /* TransferWait TWT=3 */ - /* ChipSelectOnTiming CSN=1 */ - /* OutputEnableOnTimimg OEN=1 */ - /* WriteByteEnableOnTiming WBN=1 */ - /* WriteByteEnableOffTiming WBF=0 */ - /* TransferHold TH=1 */ - /* ReadyEnable RE=1 */ - /* SampleOnReady SOR=1 */ - /* ByteEnableMode BEM=0 */ - /* ParityEnable PEN=0 */ - /* all reserved bits=0 */ - /*---------------------------------------------------------------------- */ - /*---------------------------------------------------------------------- */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0185 /* hiword */ - ori r4,r4,0x4380 /* loword */ - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB1CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr diff --git a/board/cray/L1/patchme b/board/cray/L1/patchme deleted file mode 100644 index e77ee7e1f5..0000000000 --- a/board/cray/L1/patchme +++ /dev/null @@ -1,30 +0,0 @@ -# master confi.mk -echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk - -# patch the examples/Makefile to ignore return value from OBJCOPY -sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile - -# add a built target for mkimage on the target architecture -sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile - -cat <>tools/makefile -mkimage.ppc : mkimage.o.ppc crc32.o.ppc - powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^ - powerpc-linux-strip $@ - -XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes" -mkimage.o.ppc: mkimage.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -crc32.o.ppc: crc32.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -EOF - -# make an image by default out of the u-boot image -sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile -cat <>makefile -u-boot.image: u-boot.bin - tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@ - -EOF diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug deleted file mode 100644 index 890f592e9b..0000000000 --- a/board/cray/L1/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/cray/L1/x2c.awk b/board/cray/L1/x2c.awk deleted file mode 100644 index 9235e6cb36..0000000000 --- a/board/cray/L1/x2c.awk +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/awk -BEGIN { print "unsigned char bootscript[] = { \n"} -{ for (i = 2; i <= NF ; i++ ) printf "0x"$i"," - print "" -} -END { print "\n};\n" } diff --git a/board/creative/xfi3/Kconfig b/board/creative/xfi3/Kconfig new file mode 100644 index 0000000000..7b681cd81b --- /dev/null +++ b/board/creative/xfi3/Kconfig @@ -0,0 +1,15 @@ +if TARGET_XFI3 + +config SYS_BOARD + default "xfi3" + +config SYS_VENDOR + default "creative" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "xfi3" + +endif diff --git a/board/creative/xfi3/MAINTAINERS b/board/creative/xfi3/MAINTAINERS new file mode 100644 index 0000000000..fb8235a329 --- /dev/null +++ b/board/creative/xfi3/MAINTAINERS @@ -0,0 +1,6 @@ +XFI3 BOARD +M: Marek Vasut +S: Maintained +F: board/creative/xfi3/ +F: include/configs/xfi3.h +F: configs/xfi3_defconfig diff --git a/board/creative/xfi3/Makefile b/board/creative/xfi3/Makefile new file mode 100644 index 0000000000..e8eb9ab26e --- /dev/null +++ b/board/creative/xfi3/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y := xfi3.o +else +obj-y := spl_boot.o +endif diff --git a/board/creative/xfi3/spl_boot.c b/board/creative/xfi3/spl_boot.c new file mode 100644 index 0000000000..af7aa0ebdd --- /dev/null +++ b/board/creative/xfi3/spl_boot.c @@ -0,0 +1,134 @@ +/* + * Creative ZEN X-Fi3 setup + * + * Copyright (C) 2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* EMI */ + MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, + + MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + + MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, + MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, + MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + + MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP, + + MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP, + MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP, + + /* PWM -- FIXME */ + MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP, +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* mDDR configuration values */ + const uint32_t regs[] = { + 0x01010001, 0x00010000, 0x01000000, 0x00000001, + 0x00010101, 0x00000001, 0x00010000, 0x01000001, + 0x01010000, 0x00000001, 0x07000200, 0x04070203, + 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, + 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, + 0x03061323, 0x0000000a, 0x00080008, 0x00200020, + 0x00200020, 0x00200020, 0x000003f7, 0x00000000, + 0x00000000, 0x00000000, 0x00000020, 0x00000000, + 0x001023cd, 0x20410010, 0x00006665, 0x00000000, + 0x00000101, 0x00000001, 0x00000000, 0x00000000, + }; + memcpy(dram_vals, regs, sizeof(regs)); +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/creative/xfi3/xfi3.c b/board/creative/xfi3/xfi3.c new file mode 100644 index 0000000000..1d83ea89aa --- /dev/null +++ b/board/creative/xfi3/xfi3.c @@ -0,0 +1,224 @@ +/* + * Creative ZEN X-Fi3 board + * + * Copyright (C) 2013 Marek Vasut + * + * Hardware investigation done by: + * + * Amaury Pouly + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#ifdef CONFIG_CMD_MMC +static int xfi3_mmc_cd(int id) +{ + switch (id) { + case 0: + /* The SSP_DETECT is inverted on this board. */ + return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1); + case 1: + /* Phison bridge always present */ + return 1; + default: + return 0; + } +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* MicroSD slot */ + gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1); + gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0); + ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd); + if (ret) + return ret; + + /* Phison SD-NAND bridge */ + ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd); + + return ret; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static int mxsfb_write_byte(uint32_t payload, const unsigned int data) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + const unsigned int timeout = 0x10000; + + if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, + timeout)) + return -ETIMEDOUT; + + writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | + (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET), + ®s->hw_lcdif_transfer_count); + + writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN, + ®s->hw_lcdif_ctrl_clr); + + if (data) + writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set); + + writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); + + if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, + timeout)) + return -ETIMEDOUT; + + writel(payload, ®s->hw_lcdif_data); + return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, + timeout); +} + +static void mxsfb_write_register(uint32_t reg, uint32_t data) +{ + mxsfb_write_byte(reg, 0); + mxsfb_write_byte(data, 1); +} + +static const struct { + uint8_t reg; + uint8_t delay; + uint16_t val; +} lcd_regs[] = { + { 0x01, 0, 0x001c }, + { 0x02, 0, 0x0100 }, + /* Writing 0x30 to reg. 0x03 flips the LCD */ + { 0x03, 0, 0x1038 }, + { 0x08, 0, 0x0808 }, + /* This can contain 0x111 to rotate the LCD. */ + { 0x0c, 0, 0x0000 }, + { 0x0f, 0, 0x0c01 }, + { 0x20, 0, 0x0000 }, + { 0x21, 30, 0x0000 }, + /* Wait 30 mS here */ + { 0x10, 0, 0x0a00 }, + { 0x11, 30, 0x1038 }, + /* Wait 30 mS here */ + { 0x12, 0, 0x1010 }, + { 0x13, 0, 0x0050 }, + { 0x14, 0, 0x4f58 }, + { 0x30, 0, 0x0000 }, + { 0x31, 0, 0x00db }, + { 0x32, 0, 0x0000 }, + { 0x33, 0, 0x0000 }, + { 0x34, 0, 0x00db }, + { 0x35, 0, 0x0000 }, + { 0x36, 0, 0x00af }, + { 0x37, 0, 0x0000 }, + { 0x38, 0, 0x00db }, + { 0x39, 0, 0x0000 }, + { 0x50, 0, 0x0000 }, + { 0x51, 0, 0x0705 }, + { 0x52, 0, 0x0e0a }, + { 0x53, 0, 0x0300 }, + { 0x54, 0, 0x0a0e }, + { 0x55, 0, 0x0507 }, + { 0x56, 0, 0x0000 }, + { 0x57, 0, 0x0003 }, + { 0x58, 0, 0x090a }, + { 0x59, 30, 0x0a09 }, + /* Wait 30 mS here */ + { 0x07, 30, 0x1017 }, + /* Wait 40 mS here */ + { 0x36, 0, 0x00af }, + { 0x37, 0, 0x0000 }, + { 0x38, 0, 0x00db }, + { 0x39, 0, 0x0000 }, + { 0x20, 0, 0x0000 }, + { 0x21, 0, 0x0000 }, +}; + +void board_mxsfb_system_setup(void) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + int i; + + /* Switch the LCDIF into System-Mode */ + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE | + LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr); + + /* Restart the SmartLCD controller */ + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_set); + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_clr); + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_set); + mdelay(50); + + /* Program the SmartLCD controller */ + writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set); + + writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) | + (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) | + (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) | + (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET), + ®s->hw_lcdif_timing); + + /* + * OTM2201A init and configuration sequence. + */ + for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) { + mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val); + if (lcd_regs[i].delay) + mdelay(lcd_regs[i].delay); + } + /* Turn on Framebuffer Upload Mode */ + mxsfb_write_byte(0x22, 0); + + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT, + ®s->hw_lcdif_ctrl_set); +} +#endif + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* Turn on PWM backlight */ + gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + usb_eth_initialize(bis); + return 0; +} diff --git a/board/csb272/Kconfig b/board/csb272/Kconfig new file mode 100644 index 0000000000..eed04f0431 --- /dev/null +++ b/board/csb272/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CSB272 + +config SYS_BOARD + default "csb272" + +config SYS_CONFIG_NAME + default "csb272" + +endif diff --git a/board/csb272/MAINTAINERS b/board/csb272/MAINTAINERS new file mode 100644 index 0000000000..4bc95eaeb8 --- /dev/null +++ b/board/csb272/MAINTAINERS @@ -0,0 +1,6 @@ +CSB272 BOARD +M: Tolunay Orkun +S: Maintained +F: board/csb272/ +F: include/configs/csb272.h +F: configs/csb272_defconfig diff --git a/board/csb272/Makefile b/board/csb272/Makefile index fdcbb43034..36ec9b6f4d 100644 --- a/board/csb272/Makefile +++ b/board/csb272/Makefile @@ -5,28 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -#COBJS = $(BOARD).o flash.o -#COBJS = $(BOARD).o strataflash.o -COBJS = $(BOARD).o - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = csb272.o +obj-y += init.o diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 43a1aa0521..dc2c9503e6 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -2,7 +2,7 @@ * (C) Copyright 2004 * Tolunay Orkun, Nextio Inc., torkun@nextio.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/csb272/init.S b/board/csb272/init.S index 82c6fdb965..bf1d98680d 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -1,31 +1,9 @@ -/****************************************************************************** - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/csb472/Kconfig b/board/csb472/Kconfig new file mode 100644 index 0000000000..53b1e7ad9a --- /dev/null +++ b/board/csb472/Kconfig @@ -0,0 +1,9 @@ +if TARGET_CSB472 + +config SYS_BOARD + default "csb472" + +config SYS_CONFIG_NAME + default "csb472" + +endif diff --git a/board/csb472/MAINTAINERS b/board/csb472/MAINTAINERS new file mode 100644 index 0000000000..25041ed824 --- /dev/null +++ b/board/csb472/MAINTAINERS @@ -0,0 +1,6 @@ +CSB472 BOARD +M: Tolunay Orkun +S: Maintained +F: board/csb472/ +F: include/configs/csb472.h +F: configs/csb472_defconfig diff --git a/board/csb472/Makefile b/board/csb472/Makefile index fdcbb43034..5f7e8b533e 100644 --- a/board/csb472/Makefile +++ b/board/csb472/Makefile @@ -5,28 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -#COBJS = $(BOARD).o flash.o -#COBJS = $(BOARD).o strataflash.o -COBJS = $(BOARD).o - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = csb472.o +obj-y += init.o diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 2fd32444ea..b1de18ce51 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -2,7 +2,7 @@ * (C) Copyright 2004 * Tolunay Orkun, Nextio Inc., torkun@nextio.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/csb472/init.S b/board/csb472/init.S index e00b5f530c..7383a708b0 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -1,31 +1,9 @@ -/****************************************************************************** - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/cu824/Makefile b/board/cu824/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/cu824/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cu824/README b/board/cu824/README deleted file mode 100644 index cc0d207f5d..0000000000 --- a/board/cu824/README +++ /dev/null @@ -1,453 +0,0 @@ -ppcboot for a CU824 board ---------------------------- - -CU824 has two banks of flash 8MB each. In board's notation, bank 0 is -the one at the address of 0xFF800000 and bank 1 is the one at the -address of 0xFF000000. On power-up the processor jumps to the address -of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus, -U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is not embedded in the U-Boot code -and is located in flash separately from U-Boot, at the address of -0xFF008000. - - -U-Boot test results --------------------- - -x.x Operation on all available serial consoles - -x.x.x CONFIG_CONS_INDEX 1 - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>he -go - start application at address 'addr' -run - run commands in an environment variable -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -rarpboot- boot image via network using RARP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -loads - load S-Record file over serial line -loadb - load binary file over serial line (kermit mode) -md - memory display -mm - memory modify (auto-incrementing) -nm - memory modify (constant address) -mw - memory write (fill) -cp - memory copy -cmp - memory compare -crc32 - checksum calculation -base - print or set address offset -printenv- print environment variables -setenv - set environment variables -saveenv - save environment variables to persistent storage -protect - enable or disable FLASH write protection -erase - erase FLASH memory -flinfo - print FLASH memory information -bdinfo - print Board Info structure -iminfo - print header information for application image -coninfo - print console devices and informations -loop - infinite loop on address range -mtest - simple RAM test -icache - enable or disable instruction cache -dcache - enable or disable data cache -reset - Perform RESET of the CPU -echo - echo args to console -version - print monitor version -help - print online help -? - alias for 'help' -=> - - -x.x.x CONFIG_CONS_INDEX 2 - -**** NOT TESTED **** - -x.x Flash Driver Operation - -x.x.x Erase Operation - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=>md ff000000 -ff000000: 27051956 70706362 6f6f7420 302e382e '..Vppcboot 0.8. -ff000010: 3320284d 61792031 31203230 3031202d 3 (May 11 2001 - -ff000020: 2031343a 35373a30 33290000 00000000 14:57:03)...... -ff000030: 00000000 00000000 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: 00000000 00000000 00000000 00000000 ................ -ff000090: 00000000 00000000 00000000 00000000 ................ -ff0000a0: 00000000 00000000 00000000 00000000 ................ -ff0000b0: 00000000 00000000 00000000 00000000 ................ -ff0000c0: 00000000 00000000 00000000 00000000 ................ -ff0000d0: 00000000 00000000 00000000 00000000 ................ -ff0000e0: 00000000 00000000 00000000 00000000 ................ -ff0000f0: 00000000 00000000 00000000 00000000 ................ -=>erase ff000000 ff007fff -Erase Flash from 0xff000000 to 0xff007fff - done -Erased 1 sectors -=>md ff000000 -ff000000: ffffffff ffffffff ffffffff ffffffff ................ -ff000010: ffffffff ffffffff ffffffff ffffffff ................ -ff000020: ffffffff ffffffff ffffffff ffffffff ................ -ff000030: ffffffff ffffffff ffffffff ffffffff ................ -ff000040: ffffffff ffffffff ffffffff ffffffff ................ -ff000050: ffffffff ffffffff ffffffff ffffffff ................ -ff000060: ffffffff ffffffff ffffffff ffffffff ................ -ff000070: ffffffff ffffffff ffffffff ffffffff ................ -ff000080: ffffffff ffffffff ffffffff ffffffff ................ -ff000090: ffffffff ffffffff ffffffff ffffffff ................ -ff0000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000f0: ffffffff ffffffff ffffffff ffffffff ................ -=> - -x.x.x Information - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=> -=>flinfo - -Bank # 1: Intel: 28F160F3B (16Mbit) - Size: 8 MB in 39 Sectors - Sector Start Addresses: - FF000000 FF008000 (RO) FF010000 FF018000 FF020000 - FF028000 FF030000 FF038000 FF040000 FF080000 - FF0C0000 FF100000 FF140000 FF180000 FF1C0000 - FF200000 FF240000 FF280000 FF2C0000 FF300000 - FF340000 FF380000 FF3C0000 FF400000 FF440000 - FF480000 FF4C0000 FF500000 FF540000 FF580000 - FF5C0000 FF600000 FF640000 FF680000 FF6C0000 - FF700000 FF740000 FF780000 FF7C0000 - -Bank # 2: Intel: 28F160F3B (16Mbit) - Size: 8 MB in 39 Sectors - Sector Start Addresses: - FF800000 FF808000 FF810000 FF818000 FF820000 - FF828000 FF830000 FF838000 FF840000 FF880000 - FF8C0000 FF900000 FF940000 FF980000 FF9C0000 - FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000 - FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000 - FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000 - FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000 - FFF00000 (RO) FFF40000 FFF80000 FFFC0000 -=> - -x.x.x Flash Programming - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=> -=>cp 0 ff000000 20 -Copy to Flash... done -=>md 0 -00000000: 0ec08ce0 03f9800c 00000001 040c0000 ................ -00000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................ -00000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4. -00000030: 03fcd5bc 03fcdabc 00000000 00000000 ................ -00000040: 00000000 00000000 00000000 00000000 ................ -00000050: 00000000 00000000 00000000 00000000 ................ -00000060: 00000000 00000000 00000000 00000000 ................ -00000070: 00000000 00000000 00000000 00000000 ................ -00000080: 00000000 00000000 00000000 00000000 ................ -00000090: 00000000 00000000 00000000 00000000 ................ -000000a0: 00000000 00000000 00000000 00000000 ................ -000000b0: 00000000 00000000 00000000 00000000 ................ -000000c0: 00000000 00000000 00000000 00000000 ................ -000000d0: 00000000 00000000 00000000 00000000 ................ -000000e0: 00000000 00000000 00000000 00000000 ................ -000000f0: 00000000 00000000 00000000 00000000 ................ -=>md ff000000 -ff000000: 0ec08ce0 03f9800c 00000001 040c0000 ................ -ff000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................ -ff000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4. -ff000030: 03fcd5bc 03fcdabc 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: ffffffff ffffffff ffffffff ffffffff ................ -ff000090: ffffffff ffffffff ffffffff ffffffff ................ -ff0000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000f0: ffffffff ffffffff ffffffff ffffffff ................ -=> - -x.x.x Storage of environment variables in flash - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>printenv -bootargs= -bootcmd=bootm FE020000 -bootdelay=5 -baudrate=9600 -ipaddr=192.168.4.2 -serverip=192.168.4.1 -ethaddr=00:40:42:01:00:a0 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 167/32764 bytes -=>setenv myvar 1234 -=>save_env -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=>reset - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>printenv -bootargs= -bootcmd=bootm FE020000 -bootdelay=5 -baudrate=9600 -ipaddr=192.168.4.2 -serverip=192.168.4.1 -ethaddr=00:40:42:01:00:a0 -myvar=1234 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 178/32764 bytes -=> - -x.x Image Download and run over serial port - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=>mw 40000 0 10000 -=>md 40000 -00040000: 00000000 00000000 00000000 00000000 ................ -00040010: 00000000 00000000 00000000 00000000 ................ -00040020: 00000000 00000000 00000000 00000000 ................ -00040030: 00000000 00000000 00000000 00000000 ................ -00040040: 00000000 00000000 00000000 00000000 ................ -00040050: 00000000 00000000 00000000 00000000 ................ -00040060: 00000000 00000000 00000000 00000000 ................ -00040070: 00000000 00000000 00000000 00000000 ................ -00040080: 00000000 00000000 00000000 00000000 ................ -00040090: 00000000 00000000 00000000 00000000 ................ -000400a0: 00000000 00000000 00000000 00000000 ................ -000400b0: 00000000 00000000 00000000 00000000 ................ -000400c0: 00000000 00000000 00000000 00000000 ................ -000400d0: 00000000 00000000 00000000 00000000 ................ -000400e0: 00000000 00000000 00000000 00000000 ................ -000400f0: 00000000 00000000 00000000 00000000 ................ -=>loads -## Ready for S-Record download ... - -(Back at xpert.denx.de) -[vlad@xpert vlad]$ cat hello_world.srec >/dev/ttyS0 -[vlad@xpert vlad]$ kermit -l /dev/ttyS0 -b 9600 -c -Connecting to /dev/ttyS0, speed 9600. -The escape character is Ctrl-\ (ASCII 28, FS) -Type the escape character followed by C to get back, -or followed by ? to see other options. -md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8 -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|... -000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|... -000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8 -000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8 -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=>go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> - -x.x Image download and run over ethernet interface - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=>mw 40000 0 10000 -=>md 40000 -00040000: 00000000 00000000 00000000 00000000 ................ -00040010: 00000000 00000000 00000000 00000000 ................ -00040020: 00000000 00000000 00000000 00000000 ................ -00040030: 00000000 00000000 00000000 00000000 ................ -00040040: 00000000 00000000 00000000 00000000 ................ -00040050: 00000000 00000000 00000000 00000000 ................ -00040060: 00000000 00000000 00000000 00000000 ................ -00040070: 00000000 00000000 00000000 00000000 ................ -00040080: 00000000 00000000 00000000 00000000 ................ -00040090: 00000000 00000000 00000000 00000000 ................ -000400a0: 00000000 00000000 00000000 00000000 ................ -000400b0: 00000000 00000000 00000000 00000000 ................ -000400c0: 00000000 00000000 00000000 00000000 ................ -000400d0: 00000000 00000000 00000000 00000000 ................ -000400e0: 00000000 00000000 00000000 00000000 ................ -000400f0: 00000000 00000000 00000000 00000000 ................ -=>tftpboot 40000 hello_world.bin -ARP broadcast 1 -TFTP from server 192.168.4.1; our IP address is 192.168.4.2 -Filename 'hello_world.bin'. -Load address: 0x40000 -Loading: ############# -done -Bytes transferred = 65912 (10178 hex) -=>md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8 -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|... -000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|... -000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8 -000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8 -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=>go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c deleted file mode 100644 index 6b23c53788..0000000000 --- a/board/cu824/cu824.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2001-2006 - * Wolfgang Denk, DENX Software Engineering, - - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define BOARD_REV_REG 0xFE80002B - -int checkboard (void) -{ - char revision = *(volatile char *)(BOARD_REV_REG); - char buf[32]; - - puts ("Board: CU824 "); - printf("Revision %d ", revision); - printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk)); - - return 0; -} - -phys_size_t initdram(int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/cu824/flash.c b/board/cu824/flash.c deleted file mode 100644 index 3a6d954cca..0000000000 --- a/board/cu824/flash.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x40000 -#define PARAM_SECT_SIZE 0x8000 - -#define BOARD_CTRL_REG 0xFE800013 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static int write_data (flash_info_t *info, ulong dest, ulong *data); -static void write_via_fpu(vu_long *addr, ulong *data); -static __inline__ unsigned long get_msr(void); -static __inline__ void set_msr(unsigned long msr); - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -/*---------------------------------------------------------------------*/ -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - int i, j; - ulong size = 0; - volatile unsigned char *bcr = (volatile unsigned char *)(BOARD_CTRL_REG); - - DEBUGF("Write protect was: 0x%02X\n", *bcr); - *bcr &= 0x1; /* FWPT must be 0 */ - *bcr |= 0x6; /* FWP0 = FWP1 = 1 */ - DEBUGF("Write protect is: 0x%02X\n", *bcr); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *)(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0] = 0x00900090; - - DEBUGF ("Flash bank # %d:\n" - "\tManuf. ID @ 0x%08lX: 0x%08lX\n" - "\tDevice ID @ 0x%08lX: 0x%08lX\n", - i, - (ulong)(&addr[0]), addr[0], - (ulong)(&addr[2]), addr[2]); - - if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && - (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B)) - { - flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160F3B & FLASH_TYPEMASK); - } else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFFFFFFFF; - goto Done; - } - - DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); - - addr[0] = 0xFFFFFFFF; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 7) { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + - i * FLASH_BANK_SIZE + - j * PARAM_SECT_SIZE; - } else { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + - i * FLASH_BANK_SIZE + - (j - 7)*MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#else - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[1]); -#else - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif -#endif - -Done: - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch ((i = info->flash_id & FLASH_VENDMASK)) { - case (FLASH_MAN_INTEL & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor 0x%04x ", i); - break; - } - - switch ((i = info->flash_id & FLASH_TYPEMASK)) { - case (INTEL_ID_28F160F3B & FLASH_TYPEMASK): - printf ("28F160F3B (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type 0x%04x\n", i); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - DEBUGF ("Erase flash bank %d sect %d ... %d\n", - info - &flash_info[0], s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (FLASH_MAN_INTEL & FLASH_VENDMASK)) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - DEBUGF ("Erase sect %d @ 0x%08lX\n", - sect, (ulong)addr); - - /* Disable interrupts which might cause a timeout - * here. - */ - flag = disable_interrupts(); - - addr[0] = 0x00500050; /* clear status register */ - addr[0] = 0x00200020; /* erase setup */ - addr[0] = 0x00D000D0; /* erase confirm */ - - addr[1] = 0x00500050; /* clear status register */ - addr[1] = 0x00200020; /* erase setup */ - addr[1] = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080) ) { - if ((now=get_timer(start)) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0x00B000B0; /* suspend erase */ - addr[0] = 0x00FF00FF; /* to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - addr[0] = 0x00FF00FF; - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 8 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp, cp, msr; - int l, rc, i; - ulong data[2]; - ulong *datah = &data[0]; - ulong *datal = &data[1]; - - DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", - addr, (ulong)src, cnt); - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - msr = get_msr(); - set_msr(msr | MSR_FP); - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - *datah = *datal = 0; - - for (i = 0, cp = wp; i < l; i++, cp++) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *)cp); - } - for (; i < FLASH_WIDTH && cnt > 0; ++i) { - char tmp; - - tmp = *src; - - src++; - - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - - --cnt; ++cp; - } - - for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datah << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - set_msr(msr); - return (rc); - } - - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - *datah = *(ulong *)src; - *datal = *(ulong *)(src + 4); - if ((rc = write_data(info, wp, data)) != 0) { - set_msr(msr); - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - src += FLASH_WIDTH; - } - - if (cnt == 0) { - set_msr(msr); - return (0); - } - - /* - * handle unaligned tail bytes - */ - *datah = *datal = 0; - for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { - char tmp; - - tmp = *src; - - src++; - - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - - --cnt; - } - - for (; i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *)cp); - } - - rc = write_data(info, wp, data); - set_msr(msr); - - return (rc); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, ulong *data) -{ - vu_long *addr = (vu_long *)dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if (((addr[0] & data[0]) != data[0]) || - ((addr[1] & data[1]) != data[1]) ) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0] = 0x00400040; /* write setup */ - write_via_fpu(addr, data); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080) ) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - addr[0] = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - addr[0] = 0x00FF00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu(vu_long *addr, ulong *data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr)); -} -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); -} diff --git a/board/d-link/dns325/Kconfig b/board/d-link/dns325/Kconfig new file mode 100644 index 0000000000..f6341ada60 --- /dev/null +++ b/board/d-link/dns325/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DNS325 + +config SYS_BOARD + default "dns325" + +config SYS_VENDOR + default "d-link" + +config SYS_CONFIG_NAME + default "dns325" + +endif diff --git a/board/d-link/dns325/MAINTAINERS b/board/d-link/dns325/MAINTAINERS new file mode 100644 index 0000000000..a37b7990e0 --- /dev/null +++ b/board/d-link/dns325/MAINTAINERS @@ -0,0 +1,6 @@ +DNS325 BOARD +M: Stefan Herbrechtsmeier +S: Maintained +F: board/d-link/dns325/ +F: include/configs/dns325.h +F: configs/dns325_defconfig diff --git a/board/d-link/dns325/Makefile b/board/d-link/dns325/Makefile index 8a8ec0b5c5..c39afcae9d 100644 --- a/board/d-link/dns325/Makefile +++ b/board/d-link/dns325/Makefile @@ -1,6 +1,6 @@ # # Copyright (C) 2011 -# Stefan Herbrechtsmeier +# Stefan Herbrechtsmeier # # Based on Kirkwood support: # (C) Copyright 2009 @@ -10,24 +10,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := dns325.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dns325.o diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index ff70e9415f..75dd775762 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2011 - * Stefan Herbrechtsmeier + * Stefan Herbrechtsmeier * * Based on Kirkwood support: * (C) Copyright 2009 @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include "dns325.h" @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* Gpio configuration */ - kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, - DNS325_OE_LOW, DNS325_OE_HIGH); + mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, + DNS325_OE_LOW, DNS325_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -92,7 +92,7 @@ int board_early_init_f(void) int board_init(void) { /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dns325/dns325.h index f7b25f285f..01671111ec 100644 --- a/board/d-link/dns325/dns325.h +++ b/board/d-link/dns325/dns325.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2011 - * Stefan Herbrechtsmeier + * Stefan Herbrechtsmeier * * Based on Kirkwood support: * (C) Copyright 2009 diff --git a/board/d-link/dns325/kwbimage.cfg b/board/d-link/dns325/kwbimage.cfg index b69c1df5c0..dbd31a1d30 100644 --- a/board/d-link/dns325/kwbimage.cfg +++ b/board/d-link/dns325/kwbimage.cfg @@ -1,6 +1,6 @@ # # Copyright (C) 2011 -# Stefan Herbrechtsmeier +# Stefan Herbrechtsmeier # # Based on Kirkwood support: # (C) Copyright 2009 diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile deleted file mode 100644 index eafe6e3daf..0000000000 --- a/board/dave/PPChameleonEVB/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o nand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c deleted file mode 100644 index c9ab50e126..0000000000 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * (C) Copyright 2003 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -int board_early_init_f (void) -{ - out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */ - out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) - * IRQ 26 (EXT IRQ 1) - * IRQ 27 (EXT IRQ 2) - * IRQ 28 (EXT IRQ 3) - * IRQ 29 (EXT IRQ 4) - * IRQ 30 (EXT IRQ 5) - * IRQ 31 (EXT IRQ 6) - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ -#if 1 /* test-only */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ -#else - mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */ -#endif - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -int misc_init_r (void) -{ - /* adjust flash start and size as well as the offset */ - gd->bd->bi_flashstart = 0 - flash_info[0].size; - gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN; -#if 0 - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); - volatile unsigned char *duart0_mcr = - (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = - (unsigned char *)((ulong)DUART1_BA + 4); - - bd_t *bd = gd->bd; - char * tmp; /* Temporary char pointer */ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - unsigned long CPC0_CR0Reg; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ -#endif - -#if 0 - /* - * Enable power on PS/2 interface - */ - *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET; - - /* - * Enable interrupts in exar duart mcr[3] - */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; -#endif - return (0); -} - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming PPChameleonEVB"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_CFB_CONSOLE -# ifdef CONFIG_CONSOLE_EXTRA_INFO -# include -extern GraphicDevice smi; - -void video_get_info_str (int line_number, char *info) -{ - uint pvr = get_pvr (); - - /* init video info strings for graphic console */ - switch (line_number) { - case 1: - switch (pvr) { - case PVR_405EP_RB: - sprintf (info, " AMCC PowerPC 405EP Rev. B"); - break; - default: - sprintf (info, " AMCC PowerPC 405EP Rev. "); - break; - } - return; - case 2: - sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it"); - return; - case 3: - sprintf (info, " %s", smi.modeIdent); - return; - } - - /* no more info lines */ - *info = 0; - return; -} -# endif /* CONFIG_CONSOLE_EXTRA_INFO */ -#endif /* CONFIG_CFB_CONSOLE */ diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c deleted file mode 100644 index 771151b80b..0000000000 --- a/board/dave/PPChameleonEVB/flash.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -#ifdef __DEBUG_START_FROM_SRAM__ - return CONFIG_SYS_DUMMY_FLASH_SIZE; -#else - unsigned long size; - int i; - uint pbcr; - unsigned long base; - int size_val = 0; - - debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__); - debug("[%s, %d] flash_info = 0x%p ...\n", __func__, __LINE__, - flash_info); - - /* Init: no FLASHes known */ - for (i=0; i -#include - -#if defined(CONFIG_CMD_NAND) - -#include - -/* - * hardware specific access to control-lines - * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) - */ -static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - ulong base = (ulong) this->IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - MACRO_NAND_CTL_SETCLE((unsigned long)base); - else - MACRO_NAND_CTL_CLRCLE((unsigned long)base); - if ( ctrl & NAND_ALE ) - MACRO_NAND_CTL_CLRCLE((unsigned long)base); - else - MACRO_NAND_CTL_CLRALE((unsigned long)base); - if ( ctrl & NAND_NCE ) - MACRO_NAND_ENABLE_CE((unsigned long)base); - else - MACRO_NAND_DISABLE_CE((unsigned long)base); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - - -/* - * read device ready pin - * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) - */ -static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - ulong rb_gpio_pin; - - /* use the base addr to find out which chip are we dealing with */ - switch((ulong) this->IO_ADDR_W) { - case CONFIG_SYS_NAND0_BASE: - rb_gpio_pin = CONFIG_SYS_NAND0_RDY; - break; - case CONFIG_SYS_NAND1_BASE: - rb_gpio_pin = CONFIG_SYS_NAND1_RDY; - break; - default: /* this should never happen */ - return 0; - break; - } - - if (in32(GPIO0_IR) & rb_gpio_pin) - return 1; - return 0; -} - - -/* - * Board-specific NAND initialization. The following members of the - * argument are board-specific (per include/linux/mtd/nand.h): - * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device - * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device - * - cmd_ctrl: hardwarespecific function for accesing control-lines - * - dev_ready: hardwarespecific function for accesing device ready/busy line - * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must - * only be provided if a hardware ECC is available - * - ecc.mode: mode of ecc, see defines - * - chip_delay: chip dependent delay for transfering data from array to - * read regs (tR) - * - options: various chip options. They can partly be set to inform - * nand_scan about special functionality. See the defines for further - * explanation - * Members with a "?" were not set in the merged testing-NAND branch, - * so they are not set here either. - */ -int board_nand_init(struct nand_chip *nand) -{ - - nand->cmd_ctrl = ppchameleonevb_hwcontrol; - nand->dev_ready = ppchameleonevb_device_ready; - nand->ecc.mode = NAND_ECC_SOFT; - nand->chip_delay = NAND_BIG_DELAY_US; - nand->options = NAND_SAMSUNG_LP_OPTIONS; - return 0; -} -#endif diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds deleted file mode 100644 index 5af55e95e4..0000000000 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "config.h" /* CONFIG_BOARDDIR */ - -#ifndef RESET_VECTOR_ADDRESS -#define RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -OUTPUT_ARCH(powerpc) - -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - *(.text*) - } :text - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified."); - . = 0xFFFF8000; - .ppcenv : - { - common/env_embedded.o(.ppcenv); - } - - .resetvec RESET_VECTOR_ADDRESS : - { - KEEP(*(.resetvec)) - } :text = 0xffff - - . = RESET_VECTOR_ADDRESS + 0x4; - - /* - * Make sure that the bss segment isn't linked at 0x0, otherwise its - * address won't be updated during relocation fixups. Note that - * this is a temporary fix. Code to dynamically the fixup the bss - * location will be added in the future. When the bss relocation - * fixup code is present this workaround should be removed. - */ -#if (RESET_VECTOR_ADDRESS == 0xfffffffc) - . |= 0x10; -#endif - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - } :bss - - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c deleted file mode 100644 index 0869ca0718..0000000000 --- a/board/dave/common/fpga.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#ifdef FPGA_DEBUG -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -#define MAX_ONES 226 - -#ifdef CONFIG_SYS_FPGA_PRG -# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/ -# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */ -#else -# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#endif - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ - -#define SET_FPGA(data) out32(GPIO0_OR, data) - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#if 0 -static int fpga_boot (unsigned char *fpgadata, int size) -{ - int i, index, len; - int count; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - int j; -#else - unsigned char b; - int bit; -#endif - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - DBG ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - DBG ("FPGA: configdata starts at position 0x%x\n", index); - DBG ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ - out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ - out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */ - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA init line low */ - count = 0; - while (in32 (GPIO0_IR) & FPGA_INIT) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(in32 (GPIO0_IR) & FPGA_INIT)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - DBG ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { - for (j = 0; j < 8; j++) { - if ((fpgadata[i] & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - fpgadata[i] <<= 1; - } - } -#else /* ! CONFIG_SYS_FPGA_SPARTAN2 */ - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif /* CONFIG_SYS_FPGA_SPARTAN2 */ - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(in32 (GPIO0_IR) & FPGA_DONE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - DBG ("FPGA: Booting successful!\n"); - return 0; -} -#endif /* 0 */ diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c deleted file mode 100644 index 71bc8ac096..0000000000 --- a/board/dave/common/pci.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - - -u_long pci9054_iobase; - - -#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ -#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ - - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_read_config_dword -| Description: Read a PCI configuration register -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| value Address of the configuration register value -| Return value: -| 0 Successful -+-----------------------------------------------------------------------------*/ -int pci9054_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - unsigned long conAdrVal; - unsigned long val; - - /* generate coded value for CON_ADR register */ - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - /* Note: *pResult comes back as -1 if machine check happened */ - val = in32r(PCI_PRIMARY_CDR); - - *value = (unsigned long) val; - - out32r(PCI_PRIMARY_CAR, 0); - - if ((*(unsigned long *)0x50000304) & 0x60000000) - { - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - } - - return 0; -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_write_config_dword -| Description: Write a PCI configuration register. -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| Value Configuration register value -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int pci9054_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - unsigned long conAdrVal; - - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - out32r(PCI_PRIMARY_CDR, value); - - out32r(PCI_PRIMARY_CAR, 0); - - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - - return (0); -} - -/*----------------------------------------------------------------------- - */ - -#ifdef CONFIG_DASA_SIM -static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned int iobase; - unsigned short status = 0; - unsigned char timer; - - /* - * Configure PLX PCI9054 - */ - pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status); - status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status); - - /* Check the latency timer for values >= 0x60. - */ - pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); - if (timer < 0x60) - { - pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); - } - - /* Set I/O base register. - */ - pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE); - pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - - pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); - - if (pci9054_iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - return; - } -} -#endif - -static struct pci_config_table pci9054_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN), - pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE, - CONFIG_SYS_ETH_IOBASE, - PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, -#ifdef CONFIG_DASA_SIM - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN), - pci_dasa_sim_config_pci9054 }, -#endif -#endif - { } -}; - -static struct pci_controller pci9054_hose = { - config_table: pci9054_config_table, -}; - -void pci_init(void) -{ - struct pci_controller *hose = &pci9054_hose; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - 0x00000000, 0x00000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI Memory space */ - pci_set_region(hose->regions + 1, - 0x00000000, 0xc0000000, 0x10000000, - PCI_REGION_MEM); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - pci9054_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - pci9054_write_config_dword); - - hose->region_count = 2; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/davedenx/aria/Kconfig b/board/davedenx/aria/Kconfig new file mode 100644 index 0000000000..54a86b9e13 --- /dev/null +++ b/board/davedenx/aria/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ARIA + +config SYS_BOARD + default "aria" + +config SYS_VENDOR + default "davedenx" + +config SYS_CONFIG_NAME + default "aria" + +endif diff --git a/board/davedenx/aria/MAINTAINERS b/board/davedenx/aria/MAINTAINERS new file mode 100644 index 0000000000..a6152c985a --- /dev/null +++ b/board/davedenx/aria/MAINTAINERS @@ -0,0 +1,6 @@ +ARIA BOARD +M: Wolfgang Denk +S: Maintained +F: board/davedenx/aria/ +F: include/configs/aria.h +F: configs/aria_defconfig diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile index f78fe13d35..dd38b7f389 100644 --- a/board/davedenx/aria/Makefile +++ b/board/davedenx/aria/Makefile @@ -4,25 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := aria.o diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index c740669f33..a15a9edac4 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -107,8 +107,10 @@ int checkboard (void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/davedenx/qong/Kconfig b/board/davedenx/qong/Kconfig new file mode 100644 index 0000000000..76cf343ded --- /dev/null +++ b/board/davedenx/qong/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QONG + +config SYS_BOARD + default "qong" + +config SYS_VENDOR + default "davedenx" + +config SYS_SOC + default "mx31" + +config SYS_CONFIG_NAME + default "qong" + +endif diff --git a/board/davedenx/qong/MAINTAINERS b/board/davedenx/qong/MAINTAINERS new file mode 100644 index 0000000000..a275b5bce4 --- /dev/null +++ b/board/davedenx/qong/MAINTAINERS @@ -0,0 +1,6 @@ +QONG BOARD +M: Wolfgang Denk +S: Maintained +F: board/davedenx/qong/ +F: include/configs/qong.h +F: configs/qong_defconfig diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile index 06f63a7b20..48c443d760 100644 --- a/board/davedenx/qong/Makefile +++ b/board/davedenx/qong/Makefile @@ -7,25 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := qong.o fpga.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := qong.o fpga.o +obj-y += lowlevel_init.o diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig new file mode 100644 index 0000000000..1a841ce6e0 --- /dev/null +++ b/board/davinci/da8xxevm/Kconfig @@ -0,0 +1,38 @@ +if TARGET_DA830EVM + +config SYS_BOARD + default "da8xxevm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "da830evm" + +endif + +if TARGET_DA850EVM + +config SYS_BOARD + default "da8xxevm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "da850evm" + +endif + +if TARGET_HAWKBOARD + +config SYS_BOARD + default "da8xxevm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "hawkboard" + +endif diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS new file mode 100644 index 0000000000..dd66f07e72 --- /dev/null +++ b/board/davinci/da8xxevm/MAINTAINERS @@ -0,0 +1,22 @@ +DA8XXEVM BOARD +M: Nick Thompson +S: Maintained +F: board/davinci/da8xxevm/ +F: include/configs/da830evm.h +F: configs/da830evm_defconfig + +DA850_AM18XXEVM BOARD +M: Sudhakar Rajashekhara +S: Maintained +F: include/configs/da850evm.h +F: configs/da850_am18xxevm_defconfig +F: configs/da850evm_defconfig +F: configs/da850evm_direct_nor_defconfig + +HAWKBOARD BOARD +M: Syed Mohammed Khasim +M: Sughosh Ganu +S: Maintained +F: include/configs/hawkboard.h +F: configs/hawkboard_defconfig +F: configs/hawkboard_uart_defconfig diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile index 26dc72ce06..d3acacc33d 100644 --- a/board/davinci/da8xxevm/Makefile +++ b/board/davinci/da8xxevm/Makefile @@ -7,27 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o -COBJS-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o -COBJS-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o - -COBJS := $(COBJS-y) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o +obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o +obj-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 4f5c780e54..c40587ff09 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -25,12 +25,11 @@ #include #include #include -#include #include #include #include #include -#include +#include #include #ifdef CONFIG_DAVINCI_MMC diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 01745b211a..b9ca38e929 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -323,10 +323,6 @@ int board_early_init_f(void) int board_init(void) { -#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC) - u32 val; -#endif - #ifndef CONFIG_USE_IRQ irq_init(); #endif @@ -366,12 +362,10 @@ int board_init(void) #ifdef CONFIG_USE_NOR /* Set the GPIO direction as output */ - clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as low */ - val = readl(GPIO_BANK0_REG_SET_ADDR); - val |= (0x01 << 11); - writel(val, GPIO_BANK0_REG_CLR_ADDR); + writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR); #endif #ifdef CONFIG_DAVINCI_MMC @@ -379,9 +373,7 @@ int board_init(void) clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as high */ - val = readl(GPIO_BANK0_REG_SET_ADDR); - val |= (0x01 << 11); - writel(val, GPIO_BANK0_REG_SET_ADDR); + writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR); #endif #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 5480d1f276..ab4f50cbbe 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -22,6 +22,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram @@ -49,5 +50,9 @@ SECTIONS } >.sram __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } } diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index e43130aa67..5c629db139 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -18,9 +18,10 @@ SECTIONS . = ALIGN(4); .text : { + *(.vectors) arch/arm/cpu/arm926ejs/start.o (.text*) - arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*) - drivers/mtd/nand/libnand.o (.text*) + arch/arm/cpu/arm926ejs/built-in.o (.text*) + drivers/mtd/nand/built-in.o (.text*) *(.text*) } @@ -61,5 +62,8 @@ SECTIONS __bss_end = .; } - _end = .; + .end : + { + *(.__end) + } } diff --git a/board/davinci/dm355evm/Kconfig b/board/davinci/dm355evm/Kconfig new file mode 100644 index 0000000000..ec2c27623d --- /dev/null +++ b/board/davinci/dm355evm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DAVINCI_DM355EVM + +config SYS_BOARD + default "dm355evm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "davinci_dm355evm" + +endif diff --git a/board/davinci/dm355evm/MAINTAINERS b/board/davinci/dm355evm/MAINTAINERS new file mode 100644 index 0000000000..c017e09717 --- /dev/null +++ b/board/davinci/dm355evm/MAINTAINERS @@ -0,0 +1,6 @@ +DM355EVM BOARD +#M: Sandeep Paulraj +S: Orphan (since 2014-08) +F: board/davinci/dm355evm/ +F: include/configs/davinci_dm355evm.h +F: configs/davinci_dm355evm_defconfig diff --git a/board/davinci/dm355evm/Makefile b/board/davinci/dm355evm/Makefile index 81eb7e72de..bcb7e6fed5 100644 --- a/board/davinci/dm355evm/Makefile +++ b/board/davinci/dm355evm/Makefile @@ -7,24 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dm355evm.o diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c index 10422b226b..e5a958f7e0 100644 --- a/board/davinci/dm355evm/dm355evm.c +++ b/board/davinci/dm355evm/dm355evm.c @@ -8,8 +8,7 @@ #include #include #include -#include -#include +#include #include #include #include diff --git a/board/davinci/dm355leopard/Kconfig b/board/davinci/dm355leopard/Kconfig new file mode 100644 index 0000000000..ab4230a637 --- /dev/null +++ b/board/davinci/dm355leopard/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DAVINCI_DM355LEOPARD + +config SYS_BOARD + default "dm355leopard" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "davinci_dm355leopard" + +endif diff --git a/board/davinci/dm355leopard/MAINTAINERS b/board/davinci/dm355leopard/MAINTAINERS new file mode 100644 index 0000000000..ed04d4354b --- /dev/null +++ b/board/davinci/dm355leopard/MAINTAINERS @@ -0,0 +1,6 @@ +DM355LEOPARD BOARD +#M: Sandeep Paulraj +S: Orphan (since 2014-08) +F: board/davinci/dm355leopard/ +F: include/configs/davinci_dm355leopard.h +F: configs/davinci_dm355leopard_defconfig diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile index 81eb7e72de..7035429c92 100644 --- a/board/davinci/dm355leopard/Makefile +++ b/board/davinci/dm355leopard/Makefile @@ -7,24 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dm355leopard.o diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c index 534184329c..53902f996c 100644 --- a/board/davinci/dm355leopard/dm355leopard.c +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/davinci/dm365evm/Kconfig b/board/davinci/dm365evm/Kconfig new file mode 100644 index 0000000000..724c7b6204 --- /dev/null +++ b/board/davinci/dm365evm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DAVINCI_DM365EVM + +config SYS_BOARD + default "dm365evm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "davinci_dm365evm" + +endif diff --git a/board/davinci/dm365evm/MAINTAINERS b/board/davinci/dm365evm/MAINTAINERS new file mode 100644 index 0000000000..97c3ed3b69 --- /dev/null +++ b/board/davinci/dm365evm/MAINTAINERS @@ -0,0 +1,6 @@ +DM365EVM BOARD +#M: Sandeep Paulraj +S: Orphan (since 2014-08) +F: board/davinci/dm365evm/ +F: include/configs/davinci_dm365evm.h +F: configs/davinci_dm365evm_defconfig diff --git a/board/davinci/dm365evm/Makefile b/board/davinci/dm365evm/Makefile index 81eb7e72de..d35d81c2bf 100644 --- a/board/davinci/dm365evm/Makefile +++ b/board/davinci/dm365evm/Makefile @@ -7,24 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dm365evm.o diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index ceffd4d603..24bec56d56 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -8,8 +8,7 @@ #include #include #include -#include -#include +#include #include #include #include diff --git a/board/davinci/dm6467evm/Kconfig b/board/davinci/dm6467evm/Kconfig new file mode 100644 index 0000000000..56d2ab487d --- /dev/null +++ b/board/davinci/dm6467evm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DAVINCI_DM6467EVM + +config SYS_BOARD + default "dm6467evm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "davinci_dm6467evm" + +endif diff --git a/board/davinci/dm6467evm/MAINTAINERS b/board/davinci/dm6467evm/MAINTAINERS new file mode 100644 index 0000000000..8ca53c43c8 --- /dev/null +++ b/board/davinci/dm6467evm/MAINTAINERS @@ -0,0 +1,7 @@ +DM6467EVM BOARD +#M: Sandeep Paulraj +S: Orphan (since 2014-08) +F: board/davinci/dm6467evm/ +F: include/configs/davinci_dm6467evm.h +F: configs/davinci_dm6467evm_defconfig +F: configs/davinci_dm6467Tevm_defconfig diff --git a/board/davinci/dm6467evm/Makefile b/board/davinci/dm6467evm/Makefile index 81eb7e72de..acbbdd5032 100644 --- a/board/davinci/dm6467evm/Makefile +++ b/board/davinci/dm6467evm/Makefile @@ -7,24 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dm6467evm.o diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c index 469c9bac4b..e51cc9e638 100644 --- a/board/davinci/dm6467evm/dm6467evm.c +++ b/board/davinci/dm6467evm/dm6467evm.c @@ -8,7 +8,8 @@ #include #include #include -#include +#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/dvevm/Kconfig b/board/davinci/dvevm/Kconfig new file mode 100644 index 0000000000..3f0ef82215 --- /dev/null +++ b/board/davinci/dvevm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DAVINCI_DVEVM + +config SYS_BOARD + default "dvevm" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "davinci_dvevm" + +endif diff --git a/board/davinci/dvevm/MAINTAINERS b/board/davinci/dvevm/MAINTAINERS new file mode 100644 index 0000000000..a718b90050 --- /dev/null +++ b/board/davinci/dvevm/MAINTAINERS @@ -0,0 +1,6 @@ +DVEVM BOARD +#M: - +S: Maintained +F: board/davinci/dvevm/ +F: include/configs/davinci_dvevm.h +F: configs/davinci_dvevm_defconfig diff --git a/board/davinci/dvevm/Makefile b/board/davinci/dvevm/Makefile index 870314a168..7ade325968 100644 --- a/board/davinci/dvevm/Makefile +++ b/board/davinci/dvevm/Makefile @@ -7,24 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := board_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dvevm.o +obj-y += board_init.o diff --git a/board/davinci/ea20/Kconfig b/board/davinci/ea20/Kconfig new file mode 100644 index 0000000000..ae5b16e142 --- /dev/null +++ b/board/davinci/ea20/Kconfig @@ -0,0 +1,12 @@ +if TARGET_EA20 + +config SYS_BOARD + default "ea20" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "ea20" + +endif diff --git a/board/davinci/ea20/MAINTAINERS b/board/davinci/ea20/MAINTAINERS new file mode 100644 index 0000000000..5c300a3cbf --- /dev/null +++ b/board/davinci/ea20/MAINTAINERS @@ -0,0 +1,6 @@ +EA20 BOARD +M: Stefano Babic +S: Maintained +F: board/davinci/ea20/ +F: include/configs/ea20.h +F: configs/ea20_defconfig diff --git a/board/davinci/ea20/Makefile b/board/davinci/ea20/Makefile index 9bdfa7cc74..a5311c40ae 100644 --- a/board/davinci/ea20/Makefile +++ b/board/davinci/ea20/Makefile @@ -7,25 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += ea20.o - -COBJS := $(COBJS-y) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += ea20.o diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index c786997799..66804d75bd 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -19,12 +19,12 @@ #include #include #include -#include +#include #include #include #include #include -#include +#include "../../../drivers/video/da8xx-fb.h" DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +43,30 @@ static const struct da8xx_panel lcd_panel = { .invert_pxl_clk = 0, }; +static const struct display_panel disp_panel = { + QVGA, + 16, + 16, + COLOR_ACTIVE, +}; + +static const struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 255, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + /* SPI0 pin muxer settings */ static const struct pinmux_config spi1_pins[] = { { pinmux(5), 1, 1 }, @@ -259,7 +283,7 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - da8xx_video_init(&lcd_panel, 16); + da8xx_video_init(&lcd_panel, &lcd_cfg, 16); return 0; } diff --git a/board/davinci/schmoogie/Kconfig b/board/davinci/schmoogie/Kconfig new file mode 100644 index 0000000000..35810755f9 --- /dev/null +++ b/board/davinci/schmoogie/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DAVINCI_SCHMOOGIE + +config SYS_BOARD + default "schmoogie" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "davinci_schmoogie" + +endif diff --git a/board/davinci/schmoogie/MAINTAINERS b/board/davinci/schmoogie/MAINTAINERS new file mode 100644 index 0000000000..808e7fc046 --- /dev/null +++ b/board/davinci/schmoogie/MAINTAINERS @@ -0,0 +1,6 @@ +SCHMOOGIE BOARD +#M: - +S: Maintained +F: board/davinci/schmoogie/ +F: include/configs/davinci_schmoogie.h +F: configs/davinci_schmoogie_defconfig diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile index 870314a168..e170d551ff 100644 --- a/board/davinci/schmoogie/Makefile +++ b/board/davinci/schmoogie/Makefile @@ -7,24 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := board_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := schmoogie.o +obj-y += board_init.o diff --git a/board/davinci/sffsdr/Kconfig b/board/davinci/sffsdr/Kconfig new file mode 100644 index 0000000000..dc48f3118c --- /dev/null +++ b/board/davinci/sffsdr/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DAVINCI_SFFSDR + +config SYS_BOARD + default "sffsdr" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "davinci_sffsdr" + +endif diff --git a/board/davinci/sffsdr/MAINTAINERS b/board/davinci/sffsdr/MAINTAINERS new file mode 100644 index 0000000000..5c7e1324a9 --- /dev/null +++ b/board/davinci/sffsdr/MAINTAINERS @@ -0,0 +1,6 @@ +SFFSDR BOARD +#M: - +S: Maintained +F: board/davinci/sffsdr/ +F: include/configs/davinci_sffsdr.h +F: configs/davinci_sffsdr_defconfig diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile index 870314a168..4ab30a4061 100644 --- a/board/davinci/sffsdr/Makefile +++ b/board/davinci/sffsdr/Makefile @@ -7,24 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := board_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sffsdr.o +obj-y += board_init.o diff --git a/board/davinci/sonata/Kconfig b/board/davinci/sonata/Kconfig new file mode 100644 index 0000000000..4440d95bc2 --- /dev/null +++ b/board/davinci/sonata/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DAVINCI_SONATA + +config SYS_BOARD + default "sonata" + +config SYS_VENDOR + default "davinci" + +config SYS_CONFIG_NAME + default "davinci_sonata" + +endif diff --git a/board/davinci/sonata/MAINTAINERS b/board/davinci/sonata/MAINTAINERS new file mode 100644 index 0000000000..40659e5210 --- /dev/null +++ b/board/davinci/sonata/MAINTAINERS @@ -0,0 +1,6 @@ +SONATA BOARD +#M: - +S: Maintained +F: board/davinci/sonata/ +F: include/configs/davinci_sonata.h +F: configs/davinci_sonata_defconfig diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile index 870314a168..92e1a180c0 100644 --- a/board/davinci/sonata/Makefile +++ b/board/davinci/sonata/Makefile @@ -7,24 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o -SOBJS := board_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sonata.o +obj-y += board_init.o diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index aa04041246..f5c3258de5 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig new file mode 100644 index 0000000000..1286e4509f --- /dev/null +++ b/board/dbau1x00/Kconfig @@ -0,0 +1,30 @@ +if TARGET_DBAU1X00 + +config SYS_BOARD + default "dbau1x00" + +config SYS_SOC + default "au1x00" + +config SYS_CONFIG_NAME + default "dbau1x00" + +menu "dbau1x00 board options" + +choice + prompt "Select au1x00 SoC type" + +config DBAU1100 + bool "Select AU1100" + +config DBAU1500 + bool "Select AU1500" + +config DBAU1550 + bool "Select AU1550" + +endchoice + +endmenu + +endif diff --git a/board/dbau1x00/MAINTAINERS b/board/dbau1x00/MAINTAINERS new file mode 100644 index 0000000000..b94ed8154c --- /dev/null +++ b/board/dbau1x00/MAINTAINERS @@ -0,0 +1,10 @@ +DBAU1X00 BOARD +M: Thomas Lange +S: Maintained +F: board/dbau1x00/ +F: include/configs/dbau1x00.h +F: configs/dbau1000_defconfig +F: configs/dbau1100_defconfig +F: configs/dbau1500_defconfig +F: configs/dbau1550_defconfig +F: configs/dbau1550_el_defconfig diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile index 9024919913..2f14402a60 100644 --- a/board/dbau1x00/Makefile +++ b/board/dbau1x00/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = dbau1x00.o +obj-y += lowlevel_init.o diff --git a/board/denx/m28evk/Kconfig b/board/denx/m28evk/Kconfig new file mode 100644 index 0000000000..dd4dc4d096 --- /dev/null +++ b/board/denx/m28evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M28EVK + +config SYS_BOARD + default "m28evk" + +config SYS_VENDOR + default "denx" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "m28evk" + +endif diff --git a/board/denx/m28evk/MAINTAINERS b/board/denx/m28evk/MAINTAINERS new file mode 100644 index 0000000000..b0535a9186 --- /dev/null +++ b/board/denx/m28evk/MAINTAINERS @@ -0,0 +1,6 @@ +M28EVK BOARD +M: Marek Vasut +S: Maintained +F: board/denx/m28evk/ +F: include/configs/m28evk.h +F: configs/m28evk_defconfig diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile index 8bdeeceaa0..5e890b1eaf 100644 --- a/board/denx/m28evk/Makefile +++ b/board/denx/m28evk/Makefile @@ -5,27 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifndef CONFIG_SPL_BUILD -COBJS := m28evk.o +obj-y := m28evk.o else -COBJS := spl_boot.o +obj-y := spl_boot.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index f4453d64ab..33d38cfc54 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -116,6 +116,8 @@ int board_eth_init(bd_t *bis) int ret; ret = cpu_eth_init(bis); + if (ret) + return ret; clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c index b7c09347bd..8044a717d6 100644 --- a/board/denx/m28evk/spl_boot.c +++ b/board/denx/m28evk/spl_boot.c @@ -200,9 +200,9 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), }; -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } static uint32_t dram_vals[] = { diff --git a/board/denx/m53evk/Kconfig b/board/denx/m53evk/Kconfig new file mode 100644 index 0000000000..0696ad7ffb --- /dev/null +++ b/board/denx/m53evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M53EVK + +config SYS_BOARD + default "m53evk" + +config SYS_VENDOR + default "denx" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "m53evk" + +endif diff --git a/board/denx/m53evk/MAINTAINERS b/board/denx/m53evk/MAINTAINERS new file mode 100644 index 0000000000..5d8c76455c --- /dev/null +++ b/board/denx/m53evk/MAINTAINERS @@ -0,0 +1,6 @@ +M53EVK BOARD +M: Marek Vasut +S: Maintained +F: board/denx/m53evk/ +F: include/configs/m53evk.h +F: configs/m53evk_defconfig diff --git a/board/denx/m53evk/Makefile b/board/denx/m53evk/Makefile index 1ae71dfaa9..19b8977ae7 100644 --- a/board/denx/m53evk/Makefile +++ b/board/denx/m53evk/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := m53evk.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := m53evk.o diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c index 32751704b1..5dd6cddd02 100644 --- a/board/denx/m53evk/m53evk.c +++ b/board/denx/m53evk/m53evk.c @@ -13,7 +13,8 @@ #include #include #include -#include +#include +#include #include #include #include @@ -22,27 +23,49 @@ #include #include #include +#include +#include + +/* Special MXCFB sync flags are here. */ +#include "../drivers/video/mxcfb.h" DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) { - u32 size1, size2; + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); - gd->ram_size = size1 + size2; + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; return 0; } + void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; } static void setup_iomux_uart(void) @@ -166,6 +189,32 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_VIDEO +static struct fb_videomode const ampire_wvga = { + .name = "Ampire", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29851, /* picosecond (33.5 MHz) */ + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_CLK_LAT_FALL, +}; + +int board_video_skip(void) +{ + int ret; + ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666); + if (ret) + printf("Ampire LCD cannot be configured: %d\n", ret); + return ret; +} +#endif + #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) @@ -179,6 +228,46 @@ static void setup_iomux_i2c(void) imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); } +static void setup_iomux_video(void) +{ + static const iomux_v3_cfg_t lcd_pads[] = { + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, + MX53_PAD_EIM_DA13__IPU_DI1_D0_CS, + MX53_PAD_EIM_DA14__IPU_DI1_D1_CS, + MX53_PAD_EIM_DA15__IPU_DI1_PIN1, + MX53_PAD_EIM_DA11__IPU_DI1_PIN2, + MX53_PAD_EIM_DA12__IPU_DI1_PIN3, + MX53_PAD_EIM_A25__IPU_DI1_PIN12, + MX53_PAD_EIM_DA10__IPU_DI1_PIN15, + }; + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); +} + static void setup_iomux_nand(void) { static const iomux_v3_cfg_t nand_pads[] = { @@ -269,6 +358,7 @@ int board_early_init_f(void) setup_iomux_fec(); setup_iomux_i2c(); setup_iomux_nand(); + setup_iomux_video(); m53_set_clock(); diff --git a/board/dnp5370/Kconfig b/board/dnp5370/Kconfig new file mode 100644 index 0000000000..797081d5f2 --- /dev/null +++ b/board/dnp5370/Kconfig @@ -0,0 +1,9 @@ +if TARGET_DNP5370 + +config SYS_BOARD + default "dnp5370" + +config SYS_CONFIG_NAME + default "dnp5370" + +endif diff --git a/board/dnp5370/MAINTAINERS b/board/dnp5370/MAINTAINERS new file mode 100644 index 0000000000..8333891a40 --- /dev/null +++ b/board/dnp5370/MAINTAINERS @@ -0,0 +1,6 @@ +DNP5370 BOARD +M: M.Hasewinkel (MHA) +S: Maintained +F: board/dnp5370/ +F: include/configs/dnp5370.h +F: configs/dnp5370_defconfig diff --git a/board/dnp5370/Makefile b/board/dnp5370/Makefile index 099bcaf999..865522fd6d 100644 --- a/board/dnp5370/Makefile +++ b/board/dnp5370/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dnp5370.o diff --git a/board/dnp5370/dnp5370.c b/board/dnp5370/dnp5370.c index 4b3873bd4f..df721c9944 100644 --- a/board/dnp5370/dnp5370.c +++ b/board/dnp5370/dnp5370.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -55,7 +54,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/dvlhost/Makefile b/board/dvlhost/Makefile deleted file mode 100644 index 19753b5932..0000000000 --- a/board/dvlhost/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := dvlhost.o watchdog.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c deleted file mode 100644 index 087070f40d..0000000000 --- a/board/dvlhost/dvlhost.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "dvlhost_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS1: LED Latch */ - writel(0xBFFF0002, IXP425_EXP_CS1); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* Setup GPIOs used as output */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST); - - /* - * LED latch enable and watchdog enable are tied to the same GPIO, - * so we need to trigger the watchdog if we want to enable the LEDs. - */ -#ifdef CONFIG_HW_WATCHDOG - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN); -#else - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN); -#endif - - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST); - - /* Setup GPIOs for Interrupt inputs */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB); - - /* Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x01FF01FF, IXP425_GPIO_GPCLKR); - - /* turn off all LEDs */ - writew(0x0000, DVLHOST_LED_LATCH); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST); - - return 0; -} - -/* Check Board Identity */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: dLAN 200AV (dvlhost)"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -void reset_phy(void) -{ - /* init IcPlus IP175C ethernet switch to native IP175C mode */ - miiphy_write("NPE1", 29, 31, 0x175C); -} diff --git a/board/dvlhost/dvlhost_hw.h b/board/dvlhost/dvlhost_hw.h deleted file mode 100644 index 545099e9ea..0000000000 --- a/board/dvlhost/dvlhost_hw.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * hardware register definitions for the - * dLAN200 AV Wireless G ("dvlhost") board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DVLHOST_HW_H -#define _DVLHOST_HW_H - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPIO_WDGTRIGGER 0 /* Out */ -#define CONFIG_SYS_GPIO_BTN_WLAN 1 -#define CONFIG_SYS_GPIO_BTN_PAIRING 6 -#define CONFIG_SYS_GPIO_DLAN_PAIRING 7 /* Out */ -#define CONFIG_SYS_GPIO_BTN_RESET 9 -#define CONFIG_SYS_GPIO_IRQB 10 -#define CONFIG_SYS_GPIO_IRQA 11 -#define CONFIG_SYS_GPIO_WDG_LED_EN 12 /* Out */ -#define CONFIG_SYS_GPIO_PCIRST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#define DVLHOST_LED_LATCH IXP425_EXP_BUS_CS1_BASE_PHYS - -#endif diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds deleted file mode 100644 index 40c9c8038b..0000000000 --- a/board/dvlhost/u-boot.lds +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/libnet.o(.text*) - board/dvlhost/libdvlhost.o(.text*) - arch/arm/cpu/ixp/libixp.o(.text*) - drivers/serial/libserial.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN (4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN (4); - .data : { - *(.data*) - } - . = ALIGN (4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/board/dvlhost/watchdog.c b/board/dvlhost/watchdog.c deleted file mode 100644 index 02ec35eb1a..0000000000 --- a/board/dvlhost/watchdog.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "dvlhost_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_HW_WATCHDOG -#include -#include - -void hw_watchdog_reset(void) -{ - unsigned int x; - x = readl(IXP425_GPIO_GPOUTR); - x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER)); - writel(x, IXP425_GPIO_GPOUTR); -} - -#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile deleted file mode 100644 index 5fd87809f0..0000000000 --- a/board/eXalion/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c deleted file mode 100644 index 304ff2195c..0000000000 --- a/board/eXalion/eXalion.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "piix_pci.h" -#include "eXalion.h" - -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - - printf ("Board: eXalion MPC824x - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); - - return 0; -} - -int checkflash (void) -{ - printf ("checkflash\n"); - flash_init (); - return (0); -} - -phys_size_t initdram (int board_type) -{ - int i, cnt; - volatile uchar *base = CONFIG_SYS_SDRAM_BASE; - volatile ulong *addr; - ulong save[32]; - ulong val, ret = 0; - - for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0; - cnt >>= 1) { - addr = (volatile ulong *) base + cnt; - save[i++] = *addr; - *addr = ~cnt; - } - - addr = (volatile ulong *) base; - save[i] = *addr; - *addr = 0; - - if (*addr != 0) { - *addr = save[i]; - goto Done; - } - - for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - val = *addr; - *addr = save[--i]; - if (val != ~cnt) { - ulong new_bank0_end = cnt * sizeof (long) - 1; - ulong mear1 = mpc824x_mpc107_getreg (MEAR1); - ulong emear1 = mpc824x_mpc107_getreg (EMEAR1); - - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> - MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> - MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg (MEAR1, mear1); - mpc824x_mpc107_setreg (EMEAR1, emear1); - - ret = cnt * sizeof (long); - goto Done; - } - } - - ret = CONFIG_SYS_MAX_RAM_SIZE; - Done: - return ret; -} - -int misc_init_r (void) -{ - pci_dev_t bdf; - u32 val32; - u8 val8; - - puts ("ISA: "); - bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0); - if (bdf == -1) { - puts ("Unable to find PIIX4 ISA bridge !\n"); - hang (); - } - - /* set device for normal ISA instead EIO */ - pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32); - val32 |= 0x00000001; - pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32); - printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf), - PCI_DEV (bdf), PCI_FUNC (bdf)); - - puts ("ISA: "); - bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0); - if (bdf == -1) { - puts ("Unable to find PIIX4 IDE controller !\n"); - hang (); - } - - /* Init BMIBA register */ - /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */ - /* val32 |= 0x1000; */ - /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */ - - /* Enable BUS master and IO access */ - val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO; - pci_write_config_dword (bdf, PCI_COMMAND, val32); - - /* Set latency */ - pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8); - val8 = 0x40; - pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8); - - /* Enable Primary ATA/IDE */ - pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32); - /* val32 = 0xa307a307; */ - val32 = 0x00008000; - pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32); - - - printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf), - PCI_DEV (bdf), PCI_FUNC (bdf)); - - /* Try to get FAT working... */ - /* fat_register_read(ide_read); */ - - - return (0); -} - -/* - * Show/Init PCI devices on the specified bus number. - */ - -void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line; - - switch (PCI_DEV (dev)) { - case 16: - line = PCI_INT_A; - break; - case 17: - line = PCI_INT_B; - break; - case 18: - line = PCI_INT_C; - break; - case 19: - line = PCI_INT_D; - break; -#if defined (CONFIG_MPC8245) - case 20: - line = PCI_INT_A; - break; - case 21: - line = PCI_INT_B; - break; - case 22: - line = PCI_INT_NA; - break; -#endif - default: - line = PCI_INT_A; - break; - } - pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line); -} - - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -#if defined (CONFIG_MPC8240) -static struct pci_config_table pci_eXalion_config_table[] = { - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 PCI to ISA bridge */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 IDE controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - {} -}; -#elif defined (CONFIG_MPC8245) -static struct pci_config_table pci_eXalion_config_table[] = { - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, - pci_cfgfunc_config_device, {PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Broadcom BCM5690 Gigabit switch */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, - pci_cfgfunc_config_device, {PCI_ENET2_IOADDR, - PCI_ENET2_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Broadcom BCM5690 Gigabit switch */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00, - pci_cfgfunc_config_device, {PCI_ENET3_IOADDR, - PCI_ENET3_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 PCI to ISA bridge */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 IDE controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - {} -}; -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#endif /* #ifndef CONFIG_PCI_PNP */ - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_eXalion_config_table, - fixup_irq:pci_eXalion_fixup_irq, -#endif -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/eXalion/eXalion.h b/board/eXalion/eXalion.h deleted file mode 100644 index 7804f4f2a9..0000000000 --- a/board/eXalion/eXalion.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * James Dougherty (jfd@broadcom.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __EXALION_H -#define __EXALION_H - -/* IRQ settings */ -#define PCI_INT_NA (0xff) /* PCI Intr. not used */ -#define PCI_INT_A (0x09) /* PCI Intr. A Interrupt Request Line Nr. */ -#define PCI_INT_B (0x0a) /* PCI Intr. B Interrupt Request Line Nr. */ -#define PCI_INT_C (0x0b) /* PCI Intr. C Interrupt Request Line Nr. */ -#define PCI_INT_D (0x0c) /* PCI Intr. D Interrupt Request Line Nr. */ -#if defined (CPU_MPC8245) -#define LN_1_INT PCI_INT_B /* ethernet interrupt level */ -#define LN_2_INT PCI_INT_C /* ethernet interrupt level */ -#define BCM_1_INT PCI_INT_A /* BCM5690 interrupt level */ -#define BCM_2_INT PCI_INT_B /* BCM5690 interrupt level */ -#elif defined (CPU_MPC8240) -#define BCM_INT PCI_INT_B /* BCM5600 interrupt level */ -#define LN_INT PCI_INT_C /* ethernet interrupt level */ -#endif - -#ifndef __ASSEMBLY__ -#endif /* !__ASSEMBLY__ */ - -#endif /* __EXALION_H */ diff --git a/board/eXalion/piix_pci.h b/board/eXalion/piix_pci.h deleted file mode 100644 index 21c636f7a9..0000000000 --- a/board/eXalion/piix_pci.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _PIIX4_PCI_H -#define _PIIX4_PCI_H - -#include -#include -#include -#include -#include - -#define PIIX4_VENDOR_ID 0x8086 -#define PIIX4_ISA_DEV_ID 0x7110 -#define PIIX4_IDE_DEV_ID 0x7111 - -/* Function 0 ISA Bridge */ -#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ -#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ -#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ -#define PCI_CFG_PIIX4_SERIRQ 0x64 -#define PCI_CFG_PIIX4_TOM 0x69 -#define PCI_CFG_PIIX4_MSTAT 0x6A -#define PCI_CFG_PIIX4_MBDMA 0x76 -#define PCI_CFG_PIIX4_APICBS 0x80 -#define PCI_CFG_PIIX4_DLC 0x82 -#define PCI_CFG_PIIX4_PDMACFG 0x90 -#define PCI_CFG_PIIX4_DDMABS 0x92 -#define PCI_CFG_PIIX4_GENCFG 0xB0 -#define PCI_CFG_PIIX4_RTCCFG 0xCB - -/* IO Addresses */ -#define PIIX4_ISA_DMA1_CH0BA 0x00 -#define PIIX4_ISA_DMA1_CH0CA 0x01 -#define PIIX4_ISA_DMA1_CH1BA 0x02 -#define PIIX4_ISA_DMA1_CH1CA 0x03 -#define PIIX4_ISA_DMA1_CH2BA 0x04 -#define PIIX4_ISA_DMA1_CH2CA 0x05 -#define PIIX4_ISA_DMA1_CH3BA 0x06 -#define PIIX4_ISA_DMA1_CH3CA 0x07 -#define PIIX4_ISA_DMA1_CMDST 0x08 -#define PIIX4_ISA_DMA1_REQ 0x09 -#define PIIX4_ISA_DMA1_WSBM 0x0A -#define PIIX4_ISA_DMA1_CH_MOD 0x0B -#define PIIX4_ISA_DMA1_CLR_PT 0x0C -#define PIIX4_ISA_DMA1_M_CLR 0x0D -#define PIIX4_ISA_DMA1_CLR_M 0x0E -#define PIIX4_ISA_DMA1_RWAMB 0x0F - -#define PIIX4_ISA_DMA2_CH0BA 0xC0 -#define PIIX4_ISA_DMA2_CH0CA 0xC1 -#define PIIX4_ISA_DMA2_CH1BA 0xC2 -#define PIIX4_ISA_DMA2_CH1CA 0xC3 -#define PIIX4_ISA_DMA2_CH2BA 0xC4 -#define PIIX4_ISA_DMA2_CH2CA 0xC5 -#define PIIX4_ISA_DMA2_CH3BA 0xC6 -#define PIIX4_ISA_DMA2_CH3CA 0xC7 -#define PIIX4_ISA_DMA2_CMDST 0xD0 -#define PIIX4_ISA_DMA2_REQ 0xD2 -#define PIIX4_ISA_DMA2_WSBM 0xD4 -#define PIIX4_ISA_DMA2_CH_MOD 0xD6 -#define PIIX4_ISA_DMA2_CLR_PT 0xD8 -#define PIIX4_ISA_DMA2_M_CLR 0xDA -#define PIIX4_ISA_DMA2_CLR_M 0xDC -#define PIIX4_ISA_DMA2_RWAMB 0xDE - -#define PIIX4_ISA_INT1_ICW1 0x20 -#define PIIX4_ISA_INT1_OCW2 0x20 -#define PIIX4_ISA_INT1_OCW3 0x20 -#define PIIX4_ISA_INT1_ICW2 0x21 -#define PIIX4_ISA_INT1_ICW3 0x21 -#define PIIX4_ISA_INT1_ICW4 0x21 -#define PIIX4_ISA_INT1_OCW1 0x21 - -#define PIIX4_ISA_INT1_ELCR 0x4D0 - -#define PIIX4_ISA_INT2_ICW1 0xA0 -#define PIIX4_ISA_INT2_OCW2 0xA0 -#define PIIX4_ISA_INT2_OCW3 0xA0 -#define PIIX4_ISA_INT2_ICW2 0xA1 -#define PIIX4_ISA_INT2_ICW3 0xA1 -#define PIIX4_ISA_INT2_ICW4 0xA1 -#define PIIX4_ISA_INT2_OCW1 0xA1 -#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ - -#define PIIX4_ISA_INT2_ELCR 0x4D1 - -#define PIIX4_ISA_TMR0_CNT_ST 0x40 -#define PIIX4_ISA_TMR1_CNT_ST 0x41 -#define PIIX4_ISA_TMR2_CNT_ST 0x42 -#define PIIX4_ISA_TMR_TCW 0x43 - -#define PIIX4_ISA_RST_XBUS 0x60 - -#define PIIX4_ISA_NMI_CNT_ST 0x61 -#define PIIX4_ISA_NMI_ENABLE 0x70 - -#define PIIX4_ISA_RTC_INDEX 0x70 -#define PIIX4_ISA_RTC_DATA 0x71 -#define PIIX4_ISA_RTCEXT_IND 0x70 -#define PIIX4_ISA_RTCEXT_DATA 0x71 - -#define PIIX4_ISA_DMA1_CH2LPG 0x81 -#define PIIX4_ISA_DMA1_CH3LPG 0x82 -#define PIIX4_ISA_DMA1_CH1LPG 0x83 -#define PIIX4_ISA_DMA1_CH0LPG 0x87 -#define PIIX4_ISA_DMA2_CH2LPG 0x89 -#define PIIX4_ISA_DMA2_CH3LPG 0x8A -#define PIIX4_ISA_DMA2_CH1LPG 0x8B -#define PIIX4_ISA_DMA2_LPGRFR 0x8F - -#define PIIX4_ISA_PORT_92 0x92 - -#define PIIX4_ISA_APM_CONTRL 0xB2 -#define PIIX4_ISA_APM_STATUS 0xB3 - -#define PIIX4_ISA_COCPU_ERROR 0xF0 - -/* Function 1 IDE Controller */ -#define PCI_CFG_PIIX4_BMIBA 0x20 -#define PCI_CFG_PIIX4_IDETIM 0x40 -#define PCI_CFG_PIIX4_SIDETIM 0x44 -#define PCI_CFG_PIIX4_UDMACTL 0x48 -#define PCI_CFG_PIIX4_UDMATIM 0x4A - -/* Function 2 USB Controller */ -#define PCI_CFG_PIIX4_SBRNUM 0x60 -#define PCI_CFG_PIIX4_LEGSUP 0xC0 - -/* Function 3 Power Management */ -#define PCI_CFG_PIIX4_PMAB 0x40 -#define PCI_CFG_PIIX4_CNTA 0x44 -#define PCI_CFG_PIIX4_CNTB 0x48 -#define PCI_CFG_PIIX4_GPICTL 0x4C -#define PCI_CFG_PIIX4_DEVRESD 0x50 -#define PCI_CFG_PIIX4_DEVACTA 0x54 -#define PCI_CFG_PIIX4_DEVACTB 0x58 -#define PCI_CFG_PIIX4_DEVRESA 0x5C -#define PCI_CFG_PIIX4_DEVRESB 0x60 -#define PCI_CFG_PIIX4_DEVRESC 0x64 -#define PCI_CFG_PIIX4_DEVRESE 0x68 -#define PCI_CFG_PIIX4_DEVRESF 0x6C -#define PCI_CFG_PIIX4_DEVRESG 0x70 -#define PCI_CFG_PIIX4_DEVRESH 0x74 -#define PCI_CFG_PIIX4_DEVRESI 0x78 -#define PCI_CFG_PIIX4_PMMISC 0x80 -#define PCI_CFG_PIIX4_SMBBA 0x90 - - -#endif /* _PIIX4_PCI_H */ diff --git a/board/earthlcd/favr-32-ezkit/Kconfig b/board/earthlcd/favr-32-ezkit/Kconfig new file mode 100644 index 0000000000..50e29ec241 --- /dev/null +++ b/board/earthlcd/favr-32-ezkit/Kconfig @@ -0,0 +1,15 @@ +if TARGET_FAVR_32_EZKIT + +config SYS_BOARD + default "favr-32-ezkit" + +config SYS_VENDOR + default "earthlcd" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "favr-32-ezkit" + +endif diff --git a/board/earthlcd/favr-32-ezkit/MAINTAINERS b/board/earthlcd/favr-32-ezkit/MAINTAINERS new file mode 100644 index 0000000000..89ba862149 --- /dev/null +++ b/board/earthlcd/favr-32-ezkit/MAINTAINERS @@ -0,0 +1,6 @@ +FAVR-32-EZKIT BOARD +#M: Hans-Christian Egtvedt +S: Orphan (since 2014-06) +F: board/earthlcd/favr-32-ezkit/ +F: include/configs/favr-32-ezkit.h +F: configs/favr-32-ezkit_defconfig diff --git a/board/earthlcd/favr-32-ezkit/Makefile b/board/earthlcd/favr-32-ezkit/Makefile index 0b3ebe3e67..f712ab9c7a 100644 --- a/board/earthlcd/favr-32-ezkit/Makefile +++ b/board/earthlcd/favr-32-ezkit/Makefile @@ -6,23 +6,4 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := favr-32-ezkit.o flash.o diff --git a/board/egnite/ethernut5/Kconfig b/board/egnite/ethernut5/Kconfig new file mode 100644 index 0000000000..c42c734f1f --- /dev/null +++ b/board/egnite/ethernut5/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ETHERNUT5 + +config SYS_BOARD + default "ethernut5" + +config SYS_VENDOR + default "egnite" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "ethernut5" + +endif diff --git a/board/egnite/ethernut5/MAINTAINERS b/board/egnite/ethernut5/MAINTAINERS new file mode 100644 index 0000000000..a4ad913b63 --- /dev/null +++ b/board/egnite/ethernut5/MAINTAINERS @@ -0,0 +1,6 @@ +ETHERNUT5 BOARD +M: egnite GmbH +S: Maintained +F: board/egnite/ethernut5/ +F: include/configs/ethernut5.h +F: configs/ethernut5_defconfig diff --git a/board/egnite/ethernut5/Makefile b/board/egnite/ethernut5/Makefile index 275be0a1a9..2513873840 100644 --- a/board/egnite/ethernut5/Makefile +++ b/board/egnite/ethernut5/Makefile @@ -8,25 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += $(BOARD)_pwrman.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += ethernut5.o +obj-y += ethernut5_pwrman.o diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 1f5eea56ac..b45213c245 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -71,6 +71,7 @@ #include #include #include +#include #include "ethernut5_pwrman.h" @@ -141,7 +142,7 @@ static void ethernut5_nand_hw_init(void) /* Ready pin is optional. */ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); #endif - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile deleted file mode 100644 index 51179c08df..0000000000 --- a/board/eltec/elppc/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o - -SOBJS = asm_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S deleted file mode 100644 index 10fdfa254d..0000000000 --- a/board/eltec/elppc/asm_init.S +++ /dev/null @@ -1,862 +0,0 @@ -/* - * (C) Copyright 2001 ELTEC Elektronik AG - * Frank Gottschling - * - * ELTEC ELPPC RAM initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include -#include - -.globl board_asm_init -board_asm_init: - -/* - * setup pointer to message block - */ - mflr r13 /* save away link register */ - bl get_lnk_reg /* r3=addr of next instruction */ - subi r4, r3, 8 /* r4=board_asm_init addr */ - addi r29, r4, (MessageBlock-board_asm_init) - -/* - * dcache_disable - */ - mfspr r3, HID0 - li r4, HID0_DCE - andc r3, r3, r4 - mr r2, r3 - ori r3, r3, HID0_DCI - sync - mtspr HID0, r3 - mtspr HID0, r2 - isync - sync -/* - * icache_disable - */ - mfspr r3, HID0 - li r4, 0 - ori r4, r4, HID0_ICE - andc r3, r3, r4 - sync - mtspr HID0, r3 -/* - * invalidate caches - */ - ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE) - or r4, r4, r3 - isync - mtspr HID0, r4 - andc r4, r4, r3 - isync - mtspr HID0, r4 - isync -/* - * icache_enable - */ - mfspr r3, HID0 - ori r3, r3, (HID0_ICE | HID0_ICFI) - sync - mtspr HID0, r3 - - -/* - * setup memory controller - */ - lis r1, MPC106_REG_ADDR@h - ori r1, r1, MPC106_REG_ADDR@l - lis r2, MPC106_REG_DATA@h - ori r2, r2, MPC106_REG_DATA@l - - /* Configure PICR1 */ - lis r3, MPC106_REG@h - ori r3, r3, PCI_PICR1 - stwbrx r3, 0, r1 - addis r3, r0, 0xFF14 - ori r3, r3, 0x1CC8 - eieio - stwbrx r3, 0, r2 - - /* Configure PICR2 */ - lis r3, MPC106_REG@h - ori r3, r3, PCI_PICR2 - stwbrx r3, 0, r1 - addis r3, r0, 0x0000 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure EUMBAR */ - lis r3, MPC106_REG@h - ori r3, r3, 0x0078 /* offest of EUMBAR in PCI config space */ - stwbrx r3, 0, r1 - lis r3, MPC107_EUMB_ADDR@h - eieio - stwbrx r3, 0, r2 - - /* Configure Address Map B Option Reg */ - lis r3, MPC106_REG@h - ori r3, r3, 0x00e0 /* offest of AMBOR in PCI config space */ - stwbrx r3, 0, r1 - lis r3, 0 - eieio - stwbrx r3, 0, r2 - - /* Configure I2C Controller */ - lis r14, MPC107_I2C_ADDR@h /* base of I2C controller */ - ori r14, r14, MPC107_I2C_ADDR@l - lis r3, 0x2b10 /* I2C clock = 100MHz/1024 */ - stw r3, 4(r14) - li r3, 0 /* clear arbitration */ - eieio - stw r3, 12(r14) - - /* Configure MCCR1 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR1 - stwbrx r3, 0, r1 - addis r3, r0, 0x0660 /* don't set MEMGO now ! */ - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure MCCR2 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR2 - stwbrx r3, 0, r1 - addis r3, r0, 0x0400 - ori r3, r3, 0x1800 - eieio - stwbrx r3, 0, r2 - - - /* Configure MCCR3 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR3 - stwbrx r3, 0, r1 - addis r3, r0, 0x0230 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure MCCR4 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR4 - stwbrx r3, 0, r1 - addis r3, r0, 0x2532 - ori r3, r3, 0x2220 - eieio - stwbrx r3, 0, r2 - -/* - * configure memory interface (MICRs) - */ - addis r3, r0, 0x8000 /* ADDR_80 */ - ori r3, r3, 0x0080 /* SMEMADD1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0x4000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_84 */ - ori r3, r3, 0x0084 /* SMEMADD2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0xFFFF - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_88 */ - ori r3, r3, 0x0088 /* EXTSMEM1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_8C */ - ori r3, r3, 0x008c /* EXTSMEM2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0303 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_90 */ - ori r3, r3, 0x0090 /* EMEMADD1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0x7F3F - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_94 */ - ori r3, r3, 0x0094 /* EMEMADD2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0xFFFF - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_98 */ - ori r3, r3, 0x0098 /* EXTEMEM1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_9C */ - ori r3, r3, 0x009c /* EXTEMEM2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0303 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_A0 */ - ori r3, r3, 0x00a0 /* MEMBNKEN */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0000 - ori r3, r3, 0x0003 - eieio - stwbrx r3, 0, r2 - -/* - * must wait at least 100us after HRESET to issue a MEMGO - */ - lis r0, 1 - mtctr r0 -memStartWait: - bdnz memStartWait - -/* - * enable RAM Operations through MCCR1 (MEMGO) - */ - lis r3, 0x8000 - ori r3, r3, 0x00f0 - stwbrx r3, r0, r1 - sync - lwbrx r3, 0, r2 - lis r0, 0x0008 - or r3, r0, r3 - stwbrx r3, 0, r2 - sync - -/* - * set LEDs first time - */ - li r3, 0x1 - lis r30, CONFIG_SYS_USR_LED_BASE@h - stb r3, 2(r30) - sync - -/* - * init COM1 for polled output - */ - lis r8, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r8, r8, CONFIG_SYS_NS16550_COM1@l - li r9, 0x00 - stb r9, 1(r8) /* int disabled */ - eieio - li r9, 0x00 - stb r9, 4(r8) /* modem ctrl */ - eieio - li r9, 0x80 - stb r9, 3(r8) /* link ctrl */ - eieio - li r9, (CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) - stb r9, 0(r8) /* baud rate (LSB)*/ - eieio - li r9, ((CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8) - stb r9, 1(r8) /* baud rate (MSB) */ - eieio - li r9, 0x07 - stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ - eieio - li r9, 0x0b - stb r9, 4(r8) /* enable the receiver and transmitter (modem ctrl) */ - eieio -waitEmpty: - lbz r9, 5(r8) /* transmit empty */ - andi. r9, r9, 0x40 - beq waitEmpty - li r9, 0x47 - stb r9, 3(r8) /* send break, 8 data bits, 2 stop bit, no parity */ - eieio - - lis r0, 0x0001 - mtctr r0 -waitCOM1: - lwz r0, 5(r8) /* load from port for delay */ - bdnz waitCOM1 - -waitEmpty1: - lbz r9, 5(r8) /* transmit empty */ - andi. r9, r9, 0x40 - beq waitEmpty1 - li r9, 0x07 - stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ - eieio - -/* - * intro message from message block - */ - addi r3, r29, (MnewLine-MessageBlock) - bl Printf - addi r3, r29, (MinitLogo-MessageBlock) - bl Printf - -/* - * memory cofiguration using SPD information stored on the SODIMMs - */ - addi r3, r29, (Mspd01-MessageBlock) - bl Printf - - li r17, 0 - - li r3, 0x0002 /* get RAM type from spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, -1 /* error ? */ - bne noSpdError - - addi r3, r29, (Mfail-MessageBlock) - bl Printf - - li r6, 0xe /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -noSpdError: - mr r15, r3 /* save r3 */ - - addi r3, r29, (Mok-MessageBlock) - bl Printf - - cmpli 0, 0, r15, 0x0004 /* SDRAM ? */ - beq isSDRAM - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xd /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -isSDRAM: - li r3, 0x0012 /* get supported CAS latencies from byte 18 */ - bl spdRead - mr r15, r3 - li r3, 0x09 - andi. r0, r15, 0x04 - bne maxCLis3 - li r3, 0x17 -maxCLis3: - andi. r0, r15, 0x02 - bne CL2 - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xc /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ -CL2: - bl spdRead - cmpli 0, 0, r3, 0xa1 /* cycle time must be 10ns max. */ - blt speedOk - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xb /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ -speedOk: - lis r20, 0x06e8 /* preset MCR1 value */ - - li r3, 0x0011 /* get number of internal banks from spd for bank0/1 */ - bl spdRead - - cmpli 0, 0, r3, 0x02 - beq SD_2B - cmpli 0, 0, r3, 0x04 - beq SD_4B -memConfErr: - addi r3, r29, (MramConfErr-MessageBlock) - bl Printf - - li r6, 0xa /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -SD_2B: - li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ - bl spdRead - cmpli 0, 0, r3, 0x0b - beq row11x2 - cmpli 0, 0, r3, 0x0c - beq row12x2or13x2 - cmpli 0, 0, r3, 0x0d - beq row12x2or13x2 - b memConfErr -SD_4B: - li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ - bl spdRead - cmpli 0, 0, r3, 0x0b - beq row11x4or12x4 - cmpli 0, 0, r3, 0x0c - beq row11x4or12x4 - cmpli 0, 0, r3, 0x0d - beq row13x4 - b memConfErr -row12x2or13x2: - ori r20, r20, 0x05 - b row11x4or12x4 -row13x4: - ori r20, r20, 0x0a - b row11x4or12x4 -row11x2: - ori r20, r20, 0x0f -row11x4or12x4: - /* get the size of bank 0-1 */ - - li r3, 0x001f /* get bank size from spd for bank0/1 */ - bl spdRead - - rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte (128 MB max.) */ - - li r3, 0x0005 /* get number of banks from spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, 2 /* 2 banks ? */ - bne SDRAMnobank1 - - mr r17, r16 - -SDRAMnobank1: - li r3, 0x000c /* get refresh from spd for bank0/1 */ - bl spdRead - andi. r3, r3, 0x007f /* mask selfrefresh bit */ - li r4, 0x1800 /* refesh cycle 1536 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */ - beq writeRefresh - - li r4, 0x0c00 /* refesh cycle 768 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */ - beq writeRefresh - - li r4, 0x3000 /* refesh cycle 3072 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */ - beq writeRefresh - - li r4, 0x6000 /* refesh cycle 6144 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */ - beq writeRefresh - - li r4, 0 - ori r4, r4, 0xc000 /* refesh cycle 8224 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0005 /* 125 us ? */ - beq writeRefresh - - b memConfErr - -writeRefresh: - lis r21, 0x0400 /* preset MCCR2 value */ - or r21, r21, r4 - - /* Overwrite MCCR1 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR1 - stwbrx r3, 0, r1 - eieio - stwbrx r20, 0, r2 - - /* Overwrite MCCR2 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR2 - stwbrx r3, 0, r1 - eieio - stwbrx r21, 0, r2 - - /* set the memory boundary registers for bank 0-3 */ - li r20, 0 - lis r23, 0x0303 - lis r24, 0x0303 - subi r21, r16, 1 /* calculate end address bank0 */ - li r22, 1 - - cmpi 0, 0, r17, 0 /* bank1 present ? */ - beq nobank1 - - andi. r3, r16, 0x00ff /* calculate start address of bank1 */ - andi. r4, r16, 0x0300 - rlwinm r3, r3, 8, 16, 23 - or r20, r20, r3 - or r23, r23, r4 - - add r16, r16, r17 /* add to total memory size */ - - subi r3, r16, 1 /* calculate end address of bank1 */ - andi. r4, r3, 0x0300 - andi. r3, r3, 0x00ff - rlwinm r3, r3, 8, 16, 23 - or r21, r21, r3 - or r24, r24, r4 - - ori r22, r22, 2 /* enable bank1 */ - b bankOk -nobank1: - ori r23, r23, 0x0300 /* set bank1 start to unused area */ - ori r24, r24, 0x0300 /* set bank1 end to unused area */ -bankOk: - addi r3, r29, (Mactivate-MessageBlock) - bl Printf - mr r3, r16 - bl OutDec - addi r3, r29, (Mact0123e-MessageBlock) - bl Printf - -/* - * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1 - */ - addis r3, r0, 0x8000 /* ADDR_80 */ - ori r3, r3, 0x0080 /* MSAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r20, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_88 */ - ori r3, r3, 0x0088 /* EMSAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r23, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_90 */ - ori r3, r3, 0x0090 /* MEAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r21, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_98 */ - ori r3, r3, 0x0098 /* EMEAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r24, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_A0 */ - ori r3, r3, 0x00a0 /* MBER */ - stwbrx r3, 0, r1 - eieio - stwbrx r22, 0, r2 - -/* - * delay to let SDRAM go through several initialization/refresh cycles - */ - lis r3, 3 - mtctr r3 -memStartWait_1: - bdnz memStartWait_1 - eieio - -/* - * set LEDs end - */ - li r3, 0xf - lis r30, CONFIG_SYS_USR_LED_BASE@h - stb r3, 2(r30) - sync - - mtlr r13 - blr /* EXIT board_asm_init ... */ - -/*----------------------------------------------------------------------------*/ -/* - * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string) - */ - -Printf: - lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CONFIG_SYS_NS16550_COM1@l -WaitChr: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, WaitChr /* wait till empty */ - lbzx r0, r0, r3 /* get char */ - stb r0, 0(r10) /* write to transmit reg */ - eieio - addi r3, r3, 1 /* next char */ - lbzx r0, r0, r3 /* get char */ - cmpwi cr1, r0, 0 /* end of string ? */ - bne cr1, WaitChr - blr - -/* - * print a char to COM1 in polling mode (r10=COM1 port, r3=char) - */ -OutChr: - lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CONFIG_SYS_NS16550_COM1@l -OutChr1: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutChr1 /* wait till empty */ - stb r3, 0(r10) /* write to transmit reg */ - eieio - blr - -/* - * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val) - */ -OutHex2: - li r9, 4 /* shift reg for 2 digits */ - b OHstart -OutHex4: - li r9, 12 /* shift reg for 4 digits */ - b OHstart -OutHex: - li r9, 28 /* shift reg for 8 digits */ -OHstart: - lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CONFIG_SYS_NS16550_COM1@l -OutDig: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDig - sraw r0, r3, r9 - clrlwi r0, r0, 28 - cmpwi cr1, r0, 9 - ble cr1, digIsNum - addic r0, r0, 55 - b nextDig -digIsNum: - addic r0, r0, 48 -nextDig: - stb r0, 0(r10) /* write to transmit reg */ - eieio - addic. r9, r9, -4 - bge OutDig - blr - -/* - * print 3 digits hdec value to COM1 in polling mode - * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch) - */ -OutDec: - li r6, 10 - divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */ - mullw r10, r0, r6 - subf r9, r10, r3 - mr r3, r0 - divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */ - mullw r10, r0, r6 - subf r8, r10, r3 - mr r3, r0 - divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */ - mullw r10, r0, r6 - subf r7, r10, r3 - lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CONFIG_SYS_NS16550_COM1@l - or. r7, r7, r7 - bne noblank1 - li r3, 0x20 - b OutDec4 -noblank1: - addi r3, r7, 48 /* convert to ASCII */ -OutDec4: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec4 - stb r3, 0(r10) /* x00 to transmit */ - eieio - or. r7, r7, r8 - beq OutDec5 - addi r3, r8, 48 /* convert to ASCII */ -OutDec5: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec5 - stb r3, 0(r10) /* x0 to transmit */ - eieio - addi r3, r9, 48 /* convert to ASCII */ -OutDec6: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec6 - stb r3, 0(r10) /* x to transmit */ - eieio - blr - -/* - * hang endless loop - */ -toggleError: /* fail type in r6, r7=0xff, toggle LEDs */ - stb r7, 2(r30) /* r7 to LED */ - li r0, 0 - lis r9, 127 - ori r9, r9, 65535 -toggleError1: - addic r0, r0, 1 - cmpw cr1, r0, r9 - ble cr1, toggleError1 - stb r6, 2(r30) /* r6 to LED */ - li r0, 0 - lis r9, 127 - ori r9, r9, 65535 -toggleError2: - addic r0, r0, 1 - cmpw cr1, r0, r9 - ble cr1, toggleError2 - b toggleError - -/* - * routines to read from ram spd - */ -spdWaitIdle: - lis r0, 0x1 /* timeout for about 100us */ - mtctr r0 -iSpd: - lbz r10, 12(r14) - andi. r10, r10, 0x20 /* mask and test MBB */ - beq idle - bdnz iSpd - orc. r10, r0, r0 /* return -1 to caller */ -idle: - bclr 20, 0 /* return to caller */ - -waitSpd: - lis r0, 0x10 /* timeout for about 1.5ms */ - mtctr r0 -wSpd: - lbz r10, 12(r14) - andi. r10, r10, 0x82 - cmpli 0, 0, r10, 0x82 /* test MCF and MIF set */ - beq wend - bdnz wSpd - orc. r10, r0, r0 /* return -1 to caller */ - bclr 20, 0 /* return to caller */ - -wend: - li r10, 0 - stb r10, 12(r14) /* clear status */ - bclr 20, 0 /* return to caller */ - -/* - * spdread - * in: r3 adr to read - * out: r3 val or -1 for error - * uses r10, assumes that r14 points to I2C controller - */ -spdRead: - mfspr r25, 8 /* save link register */ - - bl spdWaitIdle - bne spdErr - - li r10, 0x80 /* start with MEN */ - stb r10, 8(r14) - eieio - - li r10, 0xb0 /* start as master */ - stb r10, 8(r14) - eieio - - li r10, 0xa0 /* write device 0xA0 */ - stb r10, 16(r14) - eieio - bl waitSpd - bne spdErr - - lbz r10, 12(r14) /* test ACK */ - andi. r10, r10, 0x01 - bne gotNoAck - - stb r3, 16(r14) /* data address */ - eieio - bl waitSpd - bne spdErr - - - li r10, 0xb4 /* switch to read - restart */ - stb r10, 8(r14) - eieio - - li r10, 0xa1 /* read device 0xA0 */ - stb r10, 16(r14) - eieio - bl waitSpd - bne spdErr - - li r10, 0xa8 /* no ACK */ - stb r10, 8(r14) - eieio - - lbz r10, 16(r14) /* trigger read next byte */ - eieio - bl waitSpd - bne spdErr - - li r10, 0x88 /* generate STOP condition */ - stb r10, 8(r14) - eieio - - lbz r3, 16(r14) /* return read byte */ - - mtspr 8, r25 /* restore link register */ - blr - -gotNoAck: - li r10, 0x80 /* generate STOP condition */ - stb r10, 8(r14) - eieio -spdErr: - orc r3, r0, r0 /* return -1 */ - mtspr 8, r25 /* restore link register */ - blr - -get_lnk_reg: - mflr r3 /* return link reg */ - blr - -MessageBlock: - -MinitLogo: - .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012" - .ascii "\015\012Initialising RAM\015\012\000" -Mspd01: - .ascii " Reading SPD of SODIMM ...... \000" -MramTyp: - .ascii "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000" -MramConfErr: - .ascii "\015\012\Unsupported SODIMM Configuration!\015\012\000" -Mactivate: - .ascii " Activating \000" -Mact0123e: - .ascii " MByte.\015\012\000" -Mok: - .ascii "OK \015\012\000" -Mfail: - .ascii "FAILED \015\012\000" -MnewLine: - .ascii "\015\012\000" - .align 4 diff --git a/board/eltec/elppc/eepro100_srom.c b/board/eltec/elppc/eepro100_srom.c deleted file mode 100644 index 05ba9c4472..0000000000 --- a/board/eltec/elppc/eepro100_srom.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Local network srom writing for first time run - */ - -/* includes */ -#include -#include -#include -#include "srom.h" - -extern int eepro100_write_eeprom (struct eth_device *dev, - int location, int addr_len, - unsigned short data); - -/*----------------------------------------------------------------------------*/ - -unsigned short eepro100_srom_checksum (unsigned short *sromdata) -{ - unsigned short sum = 0; - unsigned int i; - - for (i = 0; i < (EE_SIZE - 1); i++) { - sum += sromdata[i]; - } - return (EE_CHECKSUM - sum); -} - -/*----------------------------------------------------------------------------*/ - -int eepro100_srom_store (unsigned short *source) -{ - int count; - struct eth_device onboard_dev; - - /* get onboard network iobase */ - pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0, - (unsigned int *) &onboard_dev.iobase); - onboard_dev.iobase &= ~0xf; - - source[63] = eepro100_srom_checksum (source); - - for (count = 0; count < EE_SIZE; count++) { - if (eepro100_write_eeprom ((struct eth_device *) &onboard_dev, - count, EE_ADDR_BITS, - SROM_SHORT (source)) == -1) { - return -1; - } - source++; - } - return 0; -} - -/*----------------------------------------------------------------------------*/ - -#ifdef EEPRO100_SROM_CHECK - -extern int read_eeprom (struct eth_device *dev, int location, int addr_len); - -void eepro100_srom_load (unsigned short *destination) -{ - int count; - struct eth_device onboard_dev; - -#ifdef DEBUG - int lr = 0; - - printf ("eepro100_srom_download:\n"); -#endif - - /* get onboard network iobase */ - pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0, - &onboard_dev.iobase); - onboard_dev.iobase &= ~0xf; - - memset (destination, 0x65, 128); - - for (count = 0; count < 0x40; count++) { - *destination++ = read_eeprom ((struct eth_device *) &onboard_dev, - count, EE_ADDR_BITS); -#ifdef DEBUG - printf ("%04x ", *(destination - 1)); - if (lr++ == 7) { - printf ("\n"); - lr = 0; - } -#endif - } -} -#endif /* EEPRO100_SROM_CHECK */ - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c deleted file mode 100644 index ac814b89ab..0000000000 --- a/board/eltec/elppc/elppc.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -int checkboard (void) -{ - puts ("Board: ELTEC PowerPC\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int checkflash (void) -{ - /* TODO */ - printf ("Test not implemented !\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -static unsigned int mpc106_read_cfg_dword (unsigned int reg) -{ - unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC); - - out32r (MPC106_REG_ADDR, reg_addr); - - return (in32r (MPC106_REG_DATA | (reg & 0x3))); -} - -/* ------------------------------------------------------------------------- */ - -long int dram_size (int board_type) -{ - /* - * No actual initialisation to do - done when setting up - * PICRs MCCRs ME/SARs etc in asm_init.S. - */ - - register unsigned long i, msar1, mear1, memSize; - -#if defined(CONFIG_SYS_MEMTEST) - register unsigned long reg; - - printf ("Testing DRAM\n"); - - /* write each mem addr with it's address */ - for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) - *reg = reg; - - for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) { - if (*reg != reg) - return -1; - } -#endif - - /* - * Since MPC107 memory controller chip has already been set to - * control all memory, just read and interpret its memory boundery register. - */ - memSize = 0; - msar1 = mpc106_read_cfg_dword (MPC106_MSAR1); - mear1 = mpc106_read_cfg_dword (MPC106_MEAR1); - i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf; - - do { - if (i & 0x01) /* is bank enabled ? */ - memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1; - msar1 >>= 8; - mear1 >>= 8; - i >>= 1; - } while (i); - - return (memSize * 0x100000); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - return dram_size (board_type); -} - -/* ------------------------------------------------------------------------- */ - -/* - * The BAB 911 can be reset by writing bit 0 of the Processor Initialization - * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities - * Memory Block). - */ -int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - out8 (MPC107_EUMB_PI, 1); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) - -/* - * Since the 7xx CPUs don't have an internal watchdog, this function is - * board specific. - */ -void watchdog_reset (void) -{ -} -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ - -void after_reloc (ulong dest_addr) -{ - /* - * Jump to the main U-Boot board init code - */ - board_init_r ((gd_t *)gd, dest_addr); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -extern GraphicDevice smi; - -void video_get_info_str (int line_number, char *info) -{ - /* init video info strings for graphic console */ - switch (line_number) { - case 1: - sprintf (info, " MPC7xx V%d.%d at %d / %d MHz", - (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100); - return; - case 2: - sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH", - dram_size (0) / 0x100000, flash_init () / 0x100000); - return; - case 3: - sprintf (info, " %s", smi.modeIdent); - return; - } - - /* no more info lines */ - *info = 0; - return; -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c deleted file mode 100644 index 2b41685c7b..0000000000 --- a/board/eltec/elppc/flash.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC). - * fixed monitor protection part - * - * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage - * of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use - * any other. - */ - -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*flash command address offsets*/ - -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - unsigned long size1, size2; - int i; - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - flash_init(); - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - case AMD_ID_F032B: - printf ("AM29F032B (32 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------------*/ -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong vendor, devid; - ulong base = (ulong)addr; - volatile unsigned char *caddr = (unsigned char *)addr; - -#ifdef DEBUG - printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr); -#endif - - /* Write auto select command: read Manufacturer ID */ - caddr[0] = 0xF0; /* reset bank */ - udelay(10); - - eieio(); - caddr[0x555] = 0xAA; - udelay(10); - caddr[0x2AA] = 0x55; - udelay(10); - caddr[0x555] = 0x90; - - udelay(10); - - vendor = caddr[0]; - devid = caddr[1]; - -#ifdef DEBUG - printf("Manufacturer: 0x%lx\n", vendor); -#endif - - vendor &= 0xff; - devid &= 0xff; - - /* We accept only two AMD types */ - switch (vendor) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (devid) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id |= AMD_ID_F040B; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F016D: - info->flash_id |= AMD_ID_F016D; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id |= AMD_ID_F032B; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#ifdef DEBUG - printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - caddr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------------*/ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - int rc = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[sect]); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ - } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return rc; -} - -/*----------------------------------------------------------------------------*/ -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------------*/ -/* Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c deleted file mode 100644 index d80eaba2d0..0000000000 --- a/board/eltec/elppc/misc.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* includes */ -#include -#include -#include -#include -#include "srom.h" - -/* imports */ -extern int l2_cache_enable (int l2control); -extern int eepro100_write_eeprom (struct eth_device *dev, int location, - int addr_len, unsigned short data); -extern int read_eeprom (struct eth_device *dev, int location, int addr_len); - -/*----------------------------------------------------------------------------*/ -/* - * read/write to nvram is only byte access - */ -void *nvram_read (void *dest, const long src, size_t count) -{ - uchar *d = (uchar *) dest; - uchar *s = (uchar *) (CONFIG_ENV_MAP_ADRS + src); - - while (count--) - *d++ = *s++; - - return dest; -} - -void nvram_write (long dest, const void *src, size_t count) -{ - uchar *d = (uchar *) (CONFIG_ENV_MAP_ADRS + dest); - uchar *s = (uchar *) src; - - while (count--) - *d++ = *s++; -} - -/*----------------------------------------------------------------------------*/ -/* - * handle sroms on ELPPC - * fix ether address - * set serial console as default - */ -int misc_init_r (void) -{ - revinfo eerev; - u_char *ptr; - u_int i, l, initSrom, copyNv; - char buf[256]; - char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, - 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 - }; - - /* Clock setting for MPC107 i2c */ - mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b); - - /* Reset the EPIC */ - out32r (MPC107_EUMB_GCR, 0xa0000000); - while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */ - out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */ - while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */ - - /* - * Check/Remake revision info - */ - initSrom = 0; - copyNv = 0; - - /* read out current revision srom contens */ - mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo), - SECOND_DEVICE, FIRST_BLOCK); - - /* read out current nvram shadow image */ - nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE); - - if (strcmp (eerev.magic, "ELTEC") != 0) { - /* srom is not initialized -> create a default revision info */ - for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo); - i++) - *ptr++ = 0x00; - strcpy (eerev.magic, "ELTEC"); - eerev.revrev[0] = 1; - eerev.revrev[1] = 0; - eerev.size = 0x00E0; - eerev.category[0] = 0x01; - - /* node id from dead e128 as default */ - eerev.etheraddr[0] = 0x00; - eerev.etheraddr[1] = 0x00; - eerev.etheraddr[2] = 0x5B; - eerev.etheraddr[3] = 0x00; - eerev.etheraddr[4] = 0x2E; - eerev.etheraddr[5] = 0x4D; - - /* cache config word for ELPPC */ - memset(&eerev.res[0], 0, 4); - - initSrom = 1; /* force dialog */ - copyNv = 1; /* copy to nvram */ - } - - if ((copyNv == 0) - && (el_srom_checksum ((u_char *) & eerev, CONFIG_SYS_SROM_SIZE) != - el_srom_checksum ((u_char *) buf, CONFIG_SYS_SROM_SIZE))) { - printf ("Invalid revision info copy in nvram !\n"); - printf ("Press key:\n to copy current revision info to nvram.\n"); - printf (" to reenter revision info.\n"); - printf ("=> "); - if (0 != readline (NULL)) { - switch ((char) toupper (console_buffer[0])) { - case 'C': - copyNv = 1; - break; - case 'R': - copyNv = 1; - initSrom = 1; - break; - } - } - } - - if (initSrom) { - memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ - printf ("Enter revision number (0-9): %c ", - eerev.revision[0][0]); - if (0 != readline (NULL)) { - eerev.revision[0][0] = - (char) toupper (console_buffer[0]); - memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ - } - - printf ("Enter revision character (A-Z): %c ", - eerev.revision[0][1]); - if (1 == readline (NULL)) { - eerev.revision[0][1] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter board name (V-XXXX-XXXX): %s ", - (char *) &eerev.board); - if (11 == readline (NULL)) { - for (i = 0; i < 11; i++) - eerev.board[i] = - (char) toupper (console_buffer[i]); - eerev.board[11] = '\0'; - } - - printf ("Enter serial number: %s ", (char *) &eerev.serial); - if (6 == readline (NULL)) { - for (i = 0; i < 6; i++) - eerev.serial[i] = console_buffer[i]; - eerev.serial[6] = '\0'; - } - - printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]); - if (12 == readline (NULL)) { - for (i = 0; i < 12; i += 2) - eerev.etheraddr[i >> 1] = - (char) (16 * - hex[toupper - (console_buffer[i]) - - '0'] + - hex[toupper - (console_buffer[i + 1]) - - '0']); - } - - l = strlen ((char *) &eerev.text); - printf ("Add to text section (max 64 chr): %s ", - (char *) &eerev.text); - if (0 != readline (NULL)) { - for (i = l; i < 63; i++) - eerev.text[i] = console_buffer[i - l]; - eerev.text[63] = '\0'; - } - - /* prepare network eeprom */ - memset (buf, 0, 128); - - buf[0] = eerev.etheraddr[1]; - buf[1] = eerev.etheraddr[0]; - buf[2] = eerev.etheraddr[3]; - buf[3] = eerev.etheraddr[2]; - buf[4] = eerev.etheraddr[5]; - buf[5] = eerev.etheraddr[4]; - - buf[20] = 0x48; - buf[21] = 0xB2; - - buf[22] = 0x00; - buf[23] = 0x04; - - buf[24] = 0x14; - buf[25] = 0x33; - - printf ("\nSRom: Writing i82559 info ........ "); - if (eepro100_srom_store ((unsigned short *) buf) == -1) - printf ("FAILED\n"); - else - printf ("OK\n"); - - /* update CRC */ - eerev.crc = - el_srom_checksum ((u_char *) eerev.board, eerev.size); - - /* write new values */ - printf ("\nSRom: Writing revision info ...... "); - if (mpc107_srom_store - ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev, - sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1) - printf ("FAILED\n\n"); - else - printf ("OK\n\n"); - - /* write new values as shadow image to nvram */ - nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev, - CONFIG_SYS_SROM_SIZE); - - } - - /*if (initSrom) */ - /* copy current values as shadow image to nvram */ - if (initSrom == 0 && copyNv == 1) - nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev, - CONFIG_SYS_SROM_SIZE); - - /* update environment */ - sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", - eerev.etheraddr[0], eerev.etheraddr[1], - eerev.etheraddr[2], eerev.etheraddr[3], - eerev.etheraddr[4], eerev.etheraddr[5]); - setenv ("ethaddr", buf); - - /* print actual board identification */ - printf ("Ident: %s Ser %s Rev %c%c\n", - eerev.board, (char *) &eerev.serial, - eerev.revision[0][0], eerev.revision[0][1]); - - return (0); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/mpc107_i2c.c b/board/eltec/elppc/mpc107_i2c.c deleted file mode 100644 index 4f95703e14..0000000000 --- a/board/eltec/elppc/mpc107_i2c.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* includes */ -#include -#include "srom.h" - -/* locals */ -static unsigned long mpc107_eumb_addr = 0; - -/*----------------------------------------------------------------------------*/ - -/* - * calculate checksum for ELTEC revision srom - */ -unsigned long el_srom_checksum (ptr, size) -register unsigned char *ptr; -unsigned long size; -{ - u_long f, accu = 0; - u_int i; - u_char byte; - - for (; size; size--) - { - byte = *ptr++; - for (i = 8; i; i--) - { - f = ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0; - accu >>= 1; accu ^= f; - byte >>= 1; - } - } - return(accu); -} - -/*----------------------------------------------------------------------------*/ - -static int mpc107_i2c_wait ( unsigned long timeout ) -{ - unsigned long x; - - while (((x = in32r(MPC107_I2CSR)) & 0x82) != 0x82) - { - if (!timeout--) - return -1; - } - - if (x & 0x10) - { - return -1; - } - out32r(MPC107_I2CSR, 0); - - return 0; -} - -/*----------------------------------------------------------------------------*/ - -static int mpc107_i2c_wait_idle ( unsigned long timeout ) -{ - while (in32r(MPC107_I2CSR) & 0x20) - { - if (!timeout--) - return -1; - } - return 0; -} - - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_read_byte ( - unsigned char device, - unsigned char block, - unsigned char offset ) -{ - unsigned long timeout = MPC107_I2C_TIMEOUT; - int data; - - if (!mpc107_eumb_addr) - return -6; - - mpc107_i2c_wait_idle (timeout); - - /* Start with MEN */ - out32r(MPC107_I2CCR, 0x80); - - /* Start as master */ - out32r(MPC107_I2CCR, 0xB0); - out32r(MPC107_I2CDR, (0xA0 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 1\n"); - return -2; - } - - if (in32r(MPC107_I2CSR)&0x1) - { - /* Generate STOP condition; device busy or not existing */ - out32r(MPC107_I2CCR, 0x80); - return -1; - } - - /* Data address */ - out32r(MPC107_I2CDR, offset); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 2\n"); - return -3; - } - - /* Switch to read - restart */ - out32r(MPC107_I2CCR, 0xB4); - out32r(MPC107_I2CDR, (0xA1 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 3\n"); - return -4; - } - - out32r(MPC107_I2CCR, 0xA8); /* no ACK */ - in32r(MPC107_I2CDR); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 4\n"); - return -5; - } - /* Generate STOP condition */ - out32r(MPC107_I2CCR, 0x88); - - /* read */ - data = in32r(MPC107_I2CDR); - - return (data); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_write_byte ( - unsigned char device, - unsigned char block, - unsigned char offset, - unsigned char val ) -{ - - unsigned long timeout = MPC107_I2C_TIMEOUT; - - if (!mpc107_eumb_addr) - return -6; - - mpc107_i2c_wait_idle(timeout); - - /* Start with MEN */ - out32r(MPC107_I2CCR, 0x80); - - /* Start as master */ - out32r(MPC107_I2CCR, 0xB0); - out32r(MPC107_I2CDR, (0xA0 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 1\n"); - return -1; - } - - /* Data address */ - out32r(MPC107_I2CDR, offset); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 2\n"); - return -1; - } - - /* Write */ - out32r(MPC107_I2CDR, val); - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 3\n"); - return -1; - } - - /* Generate Stop Condition */ - out32r(MPC107_I2CCR, 0x80); - - /* Return ACK or no ACK */ - return (in32r(MPC107_I2CSR) & 0x01); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_srom_load ( - unsigned char addr, - unsigned char *pBuf, - int cnt, - unsigned char device, - unsigned char block ) -{ - register int i; - int val; - int timeout; - - for (i = 0; i < cnt; i++) - { - timeout=100; - do - { - val = mpc107_i2c_read_byte (device, block, addr); - if (val < -1) - { - printf("i2c_read_error %d at dev %x block %x addr %x\n", - val, device, block, addr); - return -1; - } - else if (timeout==0) - { - printf ("i2c_read_error: timeout at dev %x block %x addr %x\n", - device, block, addr); - return -1; - } - timeout--; - } while (val == -1); /* if no ack: try again! */ - - *pBuf++ = (unsigned char)val; - addr++; - - if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */ - { - if (block == FIRST_BLOCK) - block = SECOND_BLOCK; - else - { - printf ("ic2_read_error: read beyond 2. block !\n"); - return -1; - } - } - } - udelay(100000); - return (cnt); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_srom_store ( - unsigned char addr, - unsigned char *pBuf, - int cnt, - unsigned char device, - unsigned char block ) -{ - register int i; - - for (i = 0; i < cnt; i++) - { - while (mpc107_i2c_write_byte (device,block,addr,*pBuf) == 1); - addr++; - pBuf++; - - if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */ - { - if (block == FIRST_BLOCK) - block = SECOND_BLOCK; - else - { - printf ("ic2_write_error: write beyond 2. block !\n"); - return -1; - } - } - } - udelay(100000); - return(cnt); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_init ( unsigned long eumb_addr, unsigned long divider ) -{ - unsigned long x; - - if (eumb_addr) - mpc107_eumb_addr = eumb_addr; - else - return -1; - - /* Set I2C clock */ - x = in32r(MPC107_I2CFDR) & 0xffffff00; - out32r(MPC107_I2CFDR, (x | divider)); - - /* Clear arbitration */ - out32r(MPC107_I2CSR, 0); - - return mpc107_eumb_addr; -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c deleted file mode 100644 index d81a41aadc..0000000000 --- a/board/eltec/elppc/pci.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI initialisation for the MPC10x. - */ - -#include -#include -#include - -#ifdef CONFIG_PCI - -struct pci_controller local_hose; - -void pci_init_board(void) -{ - struct pci_controller* hose = (struct pci_controller *)&local_hose; - u16 reg16; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI_MEM_BUS, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_ISA_MEM_BUS, - CONFIG_SYS_ISA_MEM_PHYS, - CONFIG_SYS_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CONFIG_SYS_PCI_IO_BUS, - CONFIG_SYS_PCI_IO_PHYS, - CONFIG_SYS_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CONFIG_SYS_ISA_IO_BUS, - CONFIG_SYS_ISA_IO_PHYS, - CONFIG_SYS_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - MPC106_REG_ADDR, - MPC106_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* Initialises the MPC10x PCI Configuration regs. */ - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* Clear non-reserved bits in status register */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); -} - -#endif /* CONFIG_PCI */ diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h deleted file mode 100644 index 662daf84e7..0000000000 --- a/board/eltec/elppc/srom.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* common srom defs */ -#define FIRST_DEVICE 0x00 -#define SECOND_DEVICE 0x04 -#define FIRST_BLOCK 0x00 -#define SECOND_BLOCK 0x02 -#define BLOCK_SIZE 0x100 -#define ERROR (-1) - -#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100 -#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100 - -#define CPU_TYPE_740 0x08 -#define CPU_TYPE_750 0x08 -#define CPU_TYPE ((get_pvr()>>16)&0xffff) - -#define ABS(x) ((x<0)?-x:x) -#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8) - -/* bab7xx ELTEC srom */ -#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220) -#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221) - -/* srom at mpc107 */ -#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */ -#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */ -#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */ -#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */ -#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */ -#define MPC107_I2C_TIMEOUT 10000000 - -/* i82559 */ -#define EE_ADDR_BITS 6 -#define EE_SIZE 0x40 /* 0x40 words */ -#define EE_CHECKSUM 0xBABA - -/* dc21143 */ -#define DEC_SROM_SIZE 128 - - -/* - * structure of revision srom - */ -typedef struct { - char magic[8]; /* 000 - Magic number */ - char revrev[2]; /* 008 - Revision of structure */ - unsigned short size; /* 00A - Size of CRC area */ - unsigned long crc; /* 00C - CRC */ - char board[16]; /* 010 - Board Revision information */ - char option[4][16]; /* 020 - Option Revision information */ - char serial[8]; /* 060 - Board serial number */ - char etheraddr[6]; /* 068 - Ethernet node addresse */ - char reserved[2]; /* 06E - Reserved */ - char revision[7][2]; /* 070 - Revision codes */ - char category[2]; /* 07E - Category codes */ - char text[64]; /* 080 - Text field */ - char res[64]; /* 0C0 - Reserved */ -} revinfo; - -unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size); -int el_srom_load (unsigned char addr, unsigned char *buf, int cnt, - unsigned char device, unsigned char block); -int el_srom_store (unsigned char addr, unsigned char *buf, int cnt, - unsigned char device, unsigned char block); - -int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider); -int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset); -int mpc107_i2c_write_byte (unsigned char device, unsigned char block, - unsigned char offset, unsigned char val); -int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt, - unsigned char device, unsigned char block); -int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt, - unsigned char device, unsigned char block); - -int dc_srom_load (unsigned short *dest); -int dc_srom_store (unsigned short *src); - -unsigned short eepro100_srom_checksum (unsigned short *sromdata); -void eepro100_srom_load (unsigned short *destination); -int eepro100_srom_store (unsigned short *source); diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/eltec/mhpc/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c deleted file mode 100644 index ad89df92cf..0000000000 --- a/board/eltec/mhpc/flash.c +++ /dev/null @@ -1,414 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F640J5 : - printf ("28F640J5 \n"); break; - default: printf ("Unknown Chip Type=0x%lXh\n", - info->flash_id & FLASH_TYPEMASK); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0xAA00AA00; - addr[0x2AAA] = (FPW)0x55005500; - addr[0x5555] = (FPW)0x90009000; - - value = SWAP(addr[0]); - - switch (value) { - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0xFF00FF00; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = SWAP(addr[1]); /* device ID no swap !*/ - - switch (value) { - case (FPW)INTEL_ID_28F640J5 : - info->flash_id += FLASH_28F640J5 ; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0xFF00FF00; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rc = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x50005000; /* clear status register */ - *addr = (FPW)0x20002000; /* erase setup */ - *addr = (FPW)0xD000D000; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0xB000B000; /* suspend erase */ - *addr = (FPW)0xFF00FF00; /* reset to read mode */ - rc = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW)0xFF00FF00; /* reset to read mode */ - printf (" done\n"); - } - } - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= port_width) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW)0xFF00FF00; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0xFF00FF00; /* restore read mode */ - - return (0); -} diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c deleted file mode 100644 index f3f564ffe4..0000000000 --- a/board/eltec/mhpc/mhpc.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2001 - * ELTEC Elektronik AG - * Frank Gottschling - * - * Board specific routines for the miniHiPerCam - * - * - initialisation (eeprom) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include "mpc8xx.h" -#include - -extern void eeprom_init (void); -extern int eeprom_read (unsigned dev_addr, unsigned offset, - unsigned char *buffer, unsigned cnt); -extern int eeprom_write (unsigned dev_addr, unsigned offset, - unsigned char *buffer, unsigned cnt); - -/* globals */ -void *video_hw_init (void); -void video_set_lut (unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ); - -GraphicDevice gdev; - -/* locals */ -static void video_circle (char *center, int radius, int color, int pitch); -static void video_test_image (void); -static void video_default_lut (unsigned int clut_type); - -/* revision info foer MHPC EEPROM offset 480 */ -typedef struct { - char board[12]; /* 000 - Board Revision information */ - char sensor; /* 012 - Sensor Type information */ - char serial[8]; /* 013 - Board serial number */ - char etheraddr[6]; /* 021 - Ethernet node addresse */ - char revision[2]; /* 027 - Revision code */ - char option[3]; /* 029 - resevered for options */ -} revinfo; - -/* ------------------------------------------------------------------------- */ - -static const unsigned int sdram_table[] = { - /* read single beat cycle */ - 0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00, - 0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35, - - /* read burst cycle */ - 0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00, - 0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* write single beat cycle */ - 0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* write burst cycle */ - 0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440, - 0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* periodic timer expired */ - 0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84, - 0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* exception */ - 0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04 -}; - -/* ------------------------------------------------------------------------- */ - -int board_early_init_f (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport); - - /* reset the port A s.a. cpm-routines */ - ip->iop_padat = 0x0000; - ip->iop_papar = 0x0000; - ip->iop_padir = 0x0800; - ip->iop_paodr = 0x0000; - - /* reset the port B for digital and LCD output */ - cp->cp_pbdat = 0x0300; - cp->cp_pbpar = 0x5001; - cp->cp_pbdir = 0x5301; - cp->cp_pbodr = 0x0000; - - /* reset the port C configured for SMC1 serial port and aqc. control */ - ip->iop_pcdat = 0x0800; - ip->iop_pcpar = 0x0000; - ip->iop_pcdir = 0x0e30; - ip->iop_pcso = 0x0000; - - /* Config port D for LCD output */ - ip->iop_pdpar = 0x1fff; - ip->iop_pddir = 0x1fff; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity - */ -int checkboard (void) -{ - puts ("Board: ELTEC miniHiperCam\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - revinfo mhpcRevInfo; - char nid[32]; - char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color", - "OMNIVISON OV7110 b&w", NULL - }; - char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, - 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 - }; - int i; - - /* check revision data */ - eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32); - - if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { - printf ("Enter revision number (0-9): %c ", - mhpcRevInfo.revision[0]); - if (0 != readline (NULL)) { - mhpcRevInfo.revision[0] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter revision character (A-Z): %c ", - mhpcRevInfo.revision[1]); - if (1 == readline (NULL)) { - mhpcRevInfo.revision[1] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter board name (V-XXXX-XXXX): %s ", - (char *) &mhpcRevInfo.board); - if (11 == readline (NULL)) { - for (i = 0; i < 11; i++) { - mhpcRevInfo.board[i] = - (char) toupper (console_buffer[i]); - mhpcRevInfo.board[11] = '\0'; - } - } - - printf ("Supported sensor types:\n"); - i = 0; - do { - printf ("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]); - } while (mhpcSensorTypes[++i] != NULL); - - do { - printf ("\nEnter sensor number (0-255): %d ", - (int) mhpcRevInfo.sensor); - if (0 != readline (NULL)) { - mhpcRevInfo.sensor = - (unsigned char) - simple_strtoul (console_buffer, NULL, - 10); - } - } while (mhpcRevInfo.sensor >= i); - - printf ("Enter serial number: %s ", - (char *) &mhpcRevInfo.serial); - if (6 == readline (NULL)) { - for (i = 0; i < 6; i++) { - mhpcRevInfo.serial[i] = console_buffer[i]; - } - mhpcRevInfo.serial[6] = '\0'; - } - - printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - if (12 == readline (NULL)) { - for (i = 0; i < 12; i += 2) { - mhpcRevInfo.etheraddr[i >> 1] = - (char) (16 * - hex[toupper - (console_buffer[i]) - - '0'] + - hex[toupper - (console_buffer[i + 1]) - - '0']); - } - } - - /* setup new revision data */ - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, - 32); - } - - /* set environment */ - sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x", - mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], - mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], - mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - setenv ("ethaddr", nid); - - /* print actual board identification */ - printf ("Ident: %s %s Ser %s Rev %c%c\n", - mhpcRevInfo.board, - (mhpcRevInfo.sensor == 0 ? "color" : "b&w"), - (char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0], - mhpcRevInfo.revision[1]); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */ - memctl->memc_mptpr = MPTPR_PTP_DIV64; - memctl->memc_mar = 0x00008800; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - udelay (200); - - /* - * Map controller SDRAM bank 1 - */ - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (10000); - - /* leave place for framebuffers */ - return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE); -} - -/* ------------------------------------------------------------------------- */ - -static void video_circle (char *center, int radius, int color, int pitch) -{ - int x, y, d, dE, dSE; - - x = 0; - y = radius; - d = 1 - radius; - dE = 3; - dSE = -2 * radius + 5; - - *(center + x + y * pitch) = color; - *(center + y + x * pitch) = color; - *(center + y - x * pitch) = color; - *(center + x - y * pitch) = color; - *(center - x - y * pitch) = color; - *(center - y - x * pitch) = color; - *(center - y + x * pitch) = color; - *(center - x + y * pitch) = color; - while (y > x) { - if (d < 0) { - d += dE; - dE += 2; - dSE += 2; - x++; - } else { - d += dSE; - dE += 2; - dSE += 4; - x++; - y--; - } - *(center + x + y * pitch) = color; - *(center + y + x * pitch) = color; - *(center + y - x * pitch) = color; - *(center + x - y * pitch) = color; - *(center - x - y * pitch) = color; - *(center - y - x * pitch) = color; - *(center - y + x * pitch) = color; - *(center - x + y * pitch) = color; - } -} - -/* ------------------------------------------------------------------------- */ - -static void video_test_image (void) -{ - char *di; - int i, n; - - /* draw raster */ - for (i = 0; i < LCD_VIDEO_ROWS; i += 32) { - memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS), - LCD_VIDEO_FG, LCD_VIDEO_COLS); - for (n = i + 1; n < i + 32; n++) - memset ((char *) (LCD_VIDEO_ADDR + - n * LCD_VIDEO_COLS), LCD_VIDEO_BG, - LCD_VIDEO_COLS); - } - - for (i = 0; i < LCD_VIDEO_COLS; i += 32) { - for (n = 0; n < LCD_VIDEO_ROWS; n++) - *(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) = - LCD_VIDEO_FG; - } - - /* draw gray bar */ - di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 + - 97 * LCD_VIDEO_COLS); - for (n = 0; n < 63; n++) { - for (i = 0; i < 256; i++) { - *di++ = (char) i; - *(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255; - } - di += LCD_VIDEO_COLS - 256; - } - - video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 + - LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2, - LCD_VIDEO_FG, LCD_VIDEO_COLS); -} - -/* ------------------------------------------------------------------------- */ - -static void video_default_lut (unsigned int clut_type) -{ - unsigned int i; - unsigned char RGB[] = { - 0x00, 0x00, 0x00, /* black */ - 0x80, 0x80, 0x80, /* gray */ - 0xff, 0x00, 0x00, /* red */ - 0x00, 0xff, 0x00, /* green */ - 0x00, 0x00, 0xff, /* blue */ - 0x00, 0xff, 0xff, /* cyan */ - 0xff, 0x00, 0xff, /* magenta */ - 0xff, 0xff, 0x00, /* yellow */ - 0x80, 0x00, 0x00, /* dark red */ - 0x00, 0x80, 0x00, /* dark green */ - 0x00, 0x00, 0x80, /* dark blue */ - 0x00, 0x80, 0x80, /* dark cyan */ - 0x80, 0x00, 0x80, /* dark magenta */ - 0x80, 0x80, 0x00, /* dark yellow */ - 0xc0, 0xc0, 0xc0, /* light gray */ - 0xff, 0xff, 0xff, /* white */ - }; - - switch (clut_type) { - case 1: - for (i = 0; i < 240; i++) - video_set_lut (i, i, i, i); - for (i = 0; i < 16; i++) - video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1], - RGB[i * 3 + 2]); - break; - default: - for (i = 0; i < 256; i++) - video_set_lut (i, i, i, i); - } -} - -/* ------------------------------------------------------------------------- */ - -void *video_hw_init (void) -{ - unsigned int clut = 0; - unsigned char *penv; - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* enable video only on CLUT value */ - if ((penv = (uchar *)getenv ("clut")) != NULL) - clut = (u_int) simple_strtoul ((char *)penv, NULL, 10); - else - return NULL; - - /* disable graphic before write LCD regs. */ - immr->im_lcd.lcd_lccr = 0x96000866; - - /* config LCD regs. */ - immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR; - immr->im_lcd.lcd_lchcr = 0x010a0093; - immr->im_lcd.lcd_lcvcr = 0x900f0024; - - printf ("Video: 640x480 8Bit Index Lut %s\n", - (clut == 1 ? "240/16 (gray/vga)" : "256(gray)")); - - video_default_lut (clut); - - /* clear framebuffer */ - memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG, - LCD_VIDEO_ROWS * LCD_VIDEO_COLS); - - /* enable graphic */ - immr->im_lcd.lcd_lccr = 0x96000867; - - /* fill in Graphic Device */ - gdev.frameAdrs = LCD_VIDEO_ADDR; - gdev.winSizeX = LCD_VIDEO_COLS; - gdev.winSizeY = LCD_VIDEO_ROWS; - gdev.gdfBytesPP = 1; - gdev.gdfIndex = GDF__8BIT_INDEX; - - if (clut > 1) - /* return Graphic Device for console */ - return (void *) &gdev; - else - /* just graphic enabled - draw something beautiful */ - video_test_image (); - - return NULL; /* this disabels cfb - console */ -} - -/* ------------------------------------------------------------------------- */ - -void video_set_lut (unsigned int index, - unsigned char r, unsigned char g, unsigned char b) -{ - unsigned int lum; - unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00); - - /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */ - /* y = 0.299*R + 0.587*G + 0.114*B */ - lum = (2990 * r + 5870 * g + 1140 * b) / 10000; - pLut[index] = - ((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum & - 0x3f); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds deleted file mode 100644 index 7ae91ffb2e..0000000000 --- a/board/eltec/mhpc/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug deleted file mode 100644 index b0091db0c6..0000000000 --- a/board/eltec/mhpc/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/embest/mx6boards/Kconfig b/board/embest/mx6boards/Kconfig new file mode 100644 index 0000000000..53a39d31dd --- /dev/null +++ b/board/embest/mx6boards/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EMBESTMX6BOARDS + +config SYS_BOARD + default "mx6boards" + +config SYS_VENDOR + default "embest" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "embestmx6boards" + +endif diff --git a/board/embest/mx6boards/MAINTAINERS b/board/embest/mx6boards/MAINTAINERS new file mode 100644 index 0000000000..0ffd4668b4 --- /dev/null +++ b/board/embest/mx6boards/MAINTAINERS @@ -0,0 +1,7 @@ +MX6BOARDS BOARD +M: Eric Bénard +S: Maintained +F: board/embest/mx6boards/ +F: include/configs/embestmx6boards.h +F: configs/marsboard_defconfig +F: configs/riotboard_defconfig diff --git a/board/embest/mx6boards/Makefile b/board/embest/mx6boards/Makefile new file mode 100644 index 0000000000..467fb50003 --- /dev/null +++ b/board/embest/mx6boards/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6boards.o diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c new file mode 100644 index 0000000000..f8c746824a --- /dev/null +++ b/board/embest/mx6boards/mx6boards.c @@ -0,0 +1,610 @@ +/* + * Copyright (C) 2014 Eukréa Electromatique + * Author: Eric Bénard + * Fabio Estevam + * Jon Nettleton + * + * based on sabresd.c which is : + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * and on hummingboard.c which is : + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton . + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +static int board_type = -1; +#define BOARD_IS_MARSBOARD 0 +#define BOARD_IS_RIOTBOARD 1 + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* GPIO16 -> AR8035 25MHz */ + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + /* AR8035 PHY Reset */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + /* AR8035 PHY Interrupt */ + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8035 PHY */ + gpio_direction_output(IMX_GPIO_NR(3, 31) , 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(3, 31), 1); +} + +int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* from linux/arch/arm/mach-imx/mach-imx6q.c : + * Ar803x phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const riotboard_usdhc3_pads[] = { + MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* eMMC RST */ + MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + if (board_type == BOARD_IS_RIOTBOARD) + ret = !gpio_get_value(USDHC3_CD_GPIO); + else if (board_type == BOARD_IS_MARSBOARD) + ret = 1; /* eMMC/uSDHC3 is always present */ + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * ** RiOTboard : + * mmc0 SDCard slot (bottom) + * mmc1 uSDCard slot (top) + * mmc2 eMMC + * ** MarSBoard : + * mmc0 uSDCard slot (bottom) + * mmc1 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].max_bus_width = 4; + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + if (board_type == BOARD_IS_RIOTBOARD) { + imx_iomux_v3_setup_multiple_pads( + riotboard_usdhc3_pads, + ARRAY_SIZE(riotboard_usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + } else { + gpio_direction_output(IMX_GPIO_NR(7, 8) , 0); + udelay(250); + gpio_set_value(IMX_GPIO_NR(7, 8), 1); + } + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[2].max_bus_width = 4; + gpio_direction_output(IMX_GPIO_NR(6, 8) , 0); + udelay(250); + gpio_set_value(IMX_GPIO_NR(6, 8), 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; +} + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} +#endif + +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; + +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 6) + } +}; + +iomux_v3_cfg_t const tft_pads_riot[] = { + /* LCD_PWR_EN */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* TOUCH_INT */ + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED_PWR_EN */ + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* BL LEVEL */ + MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const tft_pads_mars[] = { + /* LCD_PWR_EN */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* TOUCH_INT */ + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED_PWR_EN */ + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* BL LEVEL (PWM4) */ + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#if defined(CONFIG_VIDEO_IPUV3) + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + setbits_le32(&iomux->gpr[2], + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT); + /* set backlight level to ON */ + if (board_type == BOARD_IS_RIOTBOARD) + gpio_direction_output(IMX_GPIO_NR(1, 18) , 1); + else if (board_type == BOARD_IS_MARSBOARD) + gpio_direction_output(IMX_GPIO_NR(2, 10) , 1); +} + +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* set backlight level to OFF */ + if (board_type == BOARD_IS_RIOTBOARD) + gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); + else if (board_type == BOARD_IS_MARSBOARD) + gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); + + clrbits_le32(&iomux->gpr[2], + IOMUXC_GPR2_LVDS_CH0_MODE_MASK); +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + disable_lvds(dev); + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return (0 == i2c_set_bus_num(dev->bus)) && + (0 == i2c_probe(dev->addr)); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x1, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "LCD8000-97C", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 100, + .right_margin = 200, + .upper_margin = 10, + .lower_margin = 20, + .hsync_len = 20, + .vsync_len = 8, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0, IPU,IPU DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, + MXC_CCM_CCGR3_LDB_DI0_MASK); + + /* set LDB0 clk select to 011/011 */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, + (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); + + setbits_le32(&mxc_ccm->cscmr2, + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + setbits_le32(&mxc_ccm->chsccdr, + (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK, + IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + u32 cputype = cpu_type(get_cpu_rev()); + + switch (cputype) { + case MXC_CPU_MX6SOLO: + board_type = BOARD_IS_RIOTBOARD; + break; + case MXC_CPU_MX6D: + board_type = BOARD_IS_MARSBOARD; + break; + } + + setup_iomux_uart(); + + if (board_type == BOARD_IS_RIOTBOARD) + imx_iomux_v3_setup_multiple_pads( + tft_pads_riot, ARRAY_SIZE(tft_pads_riot)); + else if (board_type == BOARD_IS_MARSBOARD) + imx_iomux_v3_setup_multiple_pads( + tft_pads_mars, ARRAY_SIZE(tft_pads_mars)); +#if defined(CONFIG_VIDEO_IPUV3) + /* power ON LCD */ + gpio_direction_output(IMX_GPIO_NR(1, 29) , 1); + /* touch interrupt is an input */ + gpio_direction_input(IMX_GPIO_NR(6, 14)); + /* power ON backlight */ + gpio_direction_output(IMX_GPIO_NR(6, 15) , 1); + /* set backlight level to off */ + if (board_type == BOARD_IS_RIOTBOARD) + gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); + else if (board_type == BOARD_IS_MARSBOARD) + gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); + setup_display(); +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + /* i2c2 : HDMI EDID */ + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + /* i2c3 : LVDS, Expansion connector */ + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode riotboard_boot_modes[] = { + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +static const struct boot_mode marsboard_boot_modes[] = { + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + if (board_type == BOARD_IS_RIOTBOARD) + add_board_boot_modes(riotboard_boot_modes); + else if (board_type == BOARD_IS_RIOTBOARD) + add_board_boot_modes(marsboard_boot_modes); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: "); + if (board_type == BOARD_IS_MARSBOARD) + puts("MarSBoard\n"); + else if (board_type == BOARD_IS_RIOTBOARD) + puts("RIoTboard\n"); + else + printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev())); + + return 0; +} diff --git a/board/emk/common/am79c874.c b/board/emk/common/am79c874.c deleted file mode 100644 index b3840a2222..0000000000 --- a/board/emk/common/am79c874.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/***************************************************************************** - * check fiber optic link present, and then copper link present. do auto switch - * between both - *****************************************************************************/ diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c deleted file mode 100644 index ae5777c796..0000000000 --- a/board/emk/common/flash.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined (CONFIG_TOP860) - typedef unsigned short FLASH_PORT_WIDTH; - typedef volatile unsigned short FLASH_PORT_WIDTHV; - #define FLASH_ID_MASK 0xFF - - #define FPW FLASH_PORT_WIDTH - #define FPWV FLASH_PORT_WIDTHV - - #define FLASH_CYCLE1 0x0555 - #define FLASH_CYCLE2 0x02aa - #define FLASH_ID1 0 - #define FLASH_ID2 1 - #define FLASH_ID3 0x0e - #define FLASH_ID4 0x0F -#endif - -#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200) - typedef unsigned char FLASH_PORT_WIDTH; - typedef volatile unsigned char FLASH_PORT_WIDTHV; - #define FLASH_ID_MASK 0xFF - - #define FPW FLASH_PORT_WIDTH - #define FPWV FLASH_PORT_WIDTHV - - #define FLASH_CYCLE1 0x0aaa - #define FLASH_CYCLE2 0x0555 - #define FLASH_ID1 0 - #define FLASH_ID2 2 - #define FLASH_ID3 0x1c - #define FLASH_ID4 0x1E -#endif - -#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200) - typedef unsigned char FLASH_PORT_WIDTH; - typedef volatile unsigned char FLASH_PORT_WIDTHV; - #define FLASH_ID_MASK 0xFF - - #define FPW FLASH_PORT_WIDTH - #define FPWV FLASH_PORT_WIDTHV - - #define FLASH_CYCLE1 0x0555 - #define FLASH_CYCLE2 0x02aa - #define FLASH_ID1 0 - #define FLASH_ID2 1 - #define FLASH_ID3 0x0E - #define FLASH_ID4 0x0F -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i = 0; - extern void flash_preinit(void); - extern void flash_afterinit(uint, ulong, ulong); - ulong flashbase = CONFIG_SYS_FLASH_BASE; - - flash_preinit(); - - /* There is only ONE FLASH device */ - memset(&flash_info[i], 0, sizeof(flash_info_t)); - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - size += flash_info[i].size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - - flash_afterinit(i, flash_info[i].start[0], flash_info[i].size); - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && - info->start[0] <= base && base <= info->start[0] + info->size - 1) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; -#if 0 - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; -#endif - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160T: - case FLASH_AM160B: - fmt = "29LV160%s (16 Mbit, %s)\n"; - break; - case FLASH_AMLV640U: - fmt = "29LV640M (64 Mbit)\n"; - break; - case FLASH_AMDLV065D: - fmt = "29LV065D (64 Mbit)\n"; - break; - case FLASH_AMLV256U: - fmt = "29LV256M (256 Mbit)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - ulong size; - int erased; - ulong *flash = (unsigned long *) info->start[i]; - - if ((i % 5) == 0) { - printf ("\n "); - } - - /* - * Check if whole sector is erased - */ - size = - (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for ( - flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++ - ) - erased = *flash == ~0x0UL; - - printf (" %08lX %s %s", - info->start[i], - erased ? "E": " ", - info->protect[i] ? "(RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[FLASH_ID1] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - -#if 0 - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; -#endif - - default: - printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) { - - case (FPW)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - info->start[0] = (ulong)addr; - info->start[1] = (ulong)addr + 0x4000; - info->start[2] = (ulong)addr + 0x6000; - info->start[3] = (ulong)addr + 0x8000; - for (i = 4; i < info->sector_count; i++) - { - info->start[i] = (ulong)addr + 0x10000 * (i-3); - } - break; - - case (FPW)AMD_ID_LV065D: - info->flash_id += FLASH_AMDLV065D; - info->sector_count = 128; - info->size = 0x00800000; - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = (ulong)addr + 0x10000 * i; - } - break; - - case (FPW)AMD_ID_MIRROR: - /* MIRROR BIT FLASH, read more ID bytes */ - if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 && - (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3) - { - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x00800000; - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = (ulong)addr + 0x10000 * i; - } - break; - } - if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 && - (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3) - { - /* attention: only the first 16 MB will be used in u-boot */ - info->flash_id += FLASH_AMLV256U; - info->sector_count = 256; - info->size = 0x01000000; - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = (ulong)addr + 0x10000 * i; - } - break; - } - - /* fall thru to here ! */ - default: - printf ("unknown AMD device=%x %x %x", - (FPW)addr[FLASH_ID2], - (FPW)addr[FLASH_ID3], - (FPW)addr[FLASH_ID4]); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0x800000; - break; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: - case FLASH_AMLV640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c deleted file mode 100644 index d9af92a528..0000000000 --- a/board/emk/common/vpd.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/***************************************************************************** - * read "factory" part of EEPROM and set some environment variables - *****************************************************************************/ -void read_factory_r (void) -{ - /* read 'factory' part of EEPROM */ - uchar buf[81]; - uchar *p; - uint length; - uint addr; - uint len; - - /* get length first */ - addr = CONFIG_SYS_FACT_OFFSET; - if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, 2)) { - bailout: - printf ("cannot read factory configuration\n"); - printf ("be sure to set ethaddr yourself!\n"); - return; - } - length = buf[0] + (buf[1] << 8); - addr += 2; - - /* sanity check */ - if (length < 20 || length > CONFIG_SYS_FACT_SIZE - 2) - goto bailout; - - /* read lines */ - while (length > 0) { - /* read one line */ - len = length > 80 ? 80 : length; - if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, len)) - goto bailout; - /* mark end of buffer */ - buf[len] = 0; - /* search end of line */ - for (p = buf; *p && *p != 0x0a; p++); - if (!*p) - goto bailout; - *p++ = 0; - /* advance to next line start */ - length -= p - buf; - addr += p - buf; - /*printf ("%s\n", buf); */ - /* search for our specific entry */ - if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) { - setenv ("ethaddr", (char *)(buf + 19)); - } else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) { - setenv ("serial#", (char *)(buf + 15)); - } else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) { - setenv ("board_id", (char *)(buf + 13)); - } - } -} diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile deleted file mode 100644 index 4b15bb6637..0000000000 --- a/board/emk/top5200/Makefile +++ /dev/null @@ -1,32 +0,0 @@ - -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c deleted file mode 100644 index 8eaf7cbde3..0000000000 --- a/board/emk/top5200/top5200.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/***************************************************************************** - * initialize SDRAM/DDRAM controller. - * TBD: get data from I2C EEPROM - *****************************************************************************/ -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT -#if 0 - ulong t; - ulong tap_del; -#endif - - #define MODE_EN 0x80000000 - #define SOFT_PRE 2 - #define SOFT_REF 4 - - /* configure SDRAM start/end */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE; - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN; - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE; -#ifdef CONFIG_SYS_DRAM_DDR - /* set extended mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE; -#endif - /* set mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400; - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE; - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF; - /* set mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE; - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL; - /* write default TAP delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24; - -#if 0 - for (tap_del = 0; tap_del < 32; tap_del++) - { - *(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24; - - printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG); - for (t = 0; t < 0x04000000; t+=4) - *(vu_long *) t = t; - printf ("Checking DRAM...\n"); - for (t = 0; t < 0x04000000; t+=4) - { - ulong rval = *(vu_long *) t; - if (rval != t) - { - printf ("mismatch at %x: ", t); - printf (" 1.read %x", rval); - printf (" 2.read %x", *(vu_long *) t); - printf (" 3.read %x", *(vu_long *) t); - break; - } - } - } -#endif -#endif /* CONFIG_SYS_RAMBOOT */ - - dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20); - - /* return total ram size */ - return dramsize; -} - -/***************************************************************************** - * print board identification - *****************************************************************************/ -int checkboard (void) -{ -#if defined (CONFIG_EVAL5200) - puts ("Board: EMK TOP5200 on EVAL5200\n"); -#else -#if defined (CONFIG_LITE5200) - puts ("Board: LITE5200\n"); -#else -#if defined (CONFIG_MINI5200) - puts ("Board: EMK TOP5200 on MINI5200\n"); -#else - puts ("Board: EMK TOP5200\n"); -#endif -#endif -#endif - return 0; -} - -/***************************************************************************** - * prepare for FLASH detection - *****************************************************************************/ -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -/***************************************************************************** - * finalize FLASH setup - *****************************************************************************/ -void flash_afterinit(uint bank, ulong start, ulong size) -{ - if (bank == 0) { /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(start); - *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size); - } -} - -/***************************************************************************** - * otherinits after RAM is there and we are relocated to RAM - * note: though this is an int function, nobody cares for the result! - *****************************************************************************/ -int misc_init_r (void) -{ -#if !defined (CONFIG_LITE5200) - /* read 'factory' part of EEPROM */ - extern void read_factory_r (void); - read_factory_r (); -#endif - return (0); -} - -/***************************************************************************** - * initialize the PCI system - *****************************************************************************/ -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -/***************************************************************************** - * provide the IDE Reset Function - *****************************************************************************/ -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -} -#endif diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile deleted file mode 100644 index a45f0ef26a..0000000000 --- a/board/emk/top860/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c deleted file mode 100644 index c88ae75e9b..0000000000 --- a/board/emk/top860/top860.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2003 - * EMK Elektronik GmbH - * Reinhard Meyer - * - * Board specific routines for the TOP860 - * - * - initialisation - * - interface to VPD data (mac address, clock speeds) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/***************************************************************************** - * UPM table for 60ns EDO RAM at 25 MHz bus/external clock - *****************************************************************************/ -static const uint edo_60ns_25MHz_tbl[] = { - -/* single read (offset 0x00 in upm ram) */ - 0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00, - 0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05, -/* burst read (offset 0x08 in upm ram) */ - 0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40, - 0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48, - 0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, -/* single write (offset 0x18 in upm ram) */ - 0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, -/* burst write (offset 0x20 in upm ram) */ - 0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c, - 0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c, - 0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, -/* refresh (offset 0x30 in upm ram) */ - 0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, -/* exception (offset 0x3C in upm ram) */ - 0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05, -}; - -/***************************************************************************** - * Print Board Identity - *****************************************************************************/ -int checkboard (void) -{ - puts ("Board:"CONFIG_IDENT_STRING"\n"); - return (0); -} - -/***************************************************************************** - * Initialize DRAM controller - *****************************************************************************/ -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* - * Only initialize memory controller when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - volatile uint *addr1, *addr2; - uint i; - - upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl, - sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = 0x0ca20330; - memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM; - memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V; - /* - * Do 8 read accesses to DRAM - */ - addr1 = (volatile uint *) 0; - addr2 = (volatile uint *) 0x00400000; - for (i = 0; i < 8; i++) - in_be32(addr1); - - /* - * Now check whether we got 4MB or 16MB populated - */ - addr1[0] = 0x12345678; - addr1[1] = 0x9abcdef0; - addr2[0] = 0xfeedc0de; - addr2[1] = 0x47110815; - if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) { - /* only 4MB populated */ - memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM; - } - } - - return -(memctl->memc_or2 & 0xffff0000); -} - -/***************************************************************************** - * prepare for FLASH detection - *****************************************************************************/ -void flash_preinit(void) -{ -} - -/***************************************************************************** - * finalize FLASH setup - *****************************************************************************/ -void flash_afterinit(uint bank, ulong start, ulong size) -{ -} - -/***************************************************************************** - * otherinits after RAM is there and we are relocated to RAM - * note: though this is an int function, nobody cares for the result! - *****************************************************************************/ -int misc_init_r (void) -{ - /* read 'factory' part of EEPROM */ - extern void read_factory_r (void); - read_factory_r (); - - return (0); -} diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds deleted file mode 100644 index 79fcbf4adc..0000000000 --- a/board/emk/top860/u-boot.lds +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug deleted file mode 100644 index eec132d38c..0000000000 --- a/board/emk/top860/u-boot.lds.debug +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/emk/top9000/Makefile b/board/emk/top9000/Makefile deleted file mode 100644 index 3125164ca9..0000000000 --- a/board/emk/top9000/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2010 -# Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_ATMEL_SPI) += spi.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/emk/top9000/spi.c b/board/emk/top9000/spi.c deleted file mode 100644 index afcd00bd51..0000000000 --- a/board/emk/top9000/spi.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -static const struct { - u32 port; - u32 bit; -} cs_to_portbit[2][4] = { - {{AT91_PIO_PORTA, 3}, {AT91_PIO_PORTC, 11}, - {AT91_PIO_PORTC, 16}, {AT91_PIO_PORTC, 17} }, - {{AT91_PIO_PORTB, 3}, {AT91_PIO_PORTC, 5}, - {AT91_PIO_PORTC, 4}, {AT91_PIO_PORTC, 3} } -}; - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs); - if (bus < 2 && cs < 4) - return 1; - return 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs); - at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port, - cs_to_portbit[slave->bus][slave->cs].bit, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs); - at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port, - cs_to_portbit[slave->bus][slave->cs].bit, 1); -} diff --git a/board/emk/top9000/top9000.c b/board/emk/top9000/top9000.c deleted file mode 100644 index 6e2ffddb0a..0000000000 --- a/board/emk/top9000/top9000.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CMD_NAND -static void nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - /* Assign CS3 to NAND/SmartMedia Interface */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[3].mode); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); - - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} -#endif - -#ifdef CONFIG_MACB -static void macb_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable EMAC clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); - - /* Initialize EMAC=MACB hardware */ - at91_macb_hw_init(); -} -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable MCI clock */ - writel(1 << ATMEL_ID_MCI, &pmc->pcer); - - /* Initialize MCI hardware */ - at91_mci_hw_init(); - - /* This calls the atmel_mmc_init in gen_atmel_mci.c */ - return atmel_mci_init((void *)ATMEL_BASE_MCI); -} - -/* this is a weak define that we are overriding */ -int board_mmc_getcd(struct mmc *mmc) -{ - return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN); -} - -#endif - -int board_early_init_f(void) -{ - struct at91_shdwn *shdwn = (struct at91_shdwn *)ATMEL_BASE_SHDWN; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* - * make sure the board can be powered on by - * any transition on WKUP - */ - writel(AT91_SHDW_MR_WKMODE0H2L | AT91_SHDW_MR_WKMODE0L2H, - &shdwn->mr); - - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC), - &pmc->pcer); - - /* set SCL0 and SDA0 to open drain */ - at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1); - at91_set_pio_multi_drive(I2C0_PORT, SCL0_PIN, 1); - at91_set_pio_pullup(I2C0_PORT, SCL0_PIN, 1); - at91_set_pio_output(I2C0_PORT, SDA0_PIN, 1); - at91_set_pio_multi_drive(I2C0_PORT, SDA0_PIN, 1); - at91_set_pio_pullup(I2C0_PORT, SDA0_PIN, 1); - - /* set SCL1 and SDA1 to open drain */ - at91_set_pio_output(I2C1_PORT, SCL1_PIN, 1); - at91_set_pio_multi_drive(I2C1_PORT, SCL1_PIN, 1); - at91_set_pio_pullup(I2C1_PORT, SCL1_PIN, 1); - at91_set_pio_output(I2C1_PORT, SDA1_PIN, 1); - at91_set_pio_multi_drive(I2C1_PORT, SDA1_PIN, 1); - at91_set_pio_pullup(I2C1_PORT, SDA1_PIN, 1); - return 0; -} - -int board_init(void) -{ - /* arch number of TOP9000 Board */ - gd->bd->bi_arch_number = MACH_TYPE_TOP9000; - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - at91_seriald_hw_init(); -#ifdef CONFIG_CMD_NAND - nand_hw_init(); -#endif -#ifdef CONFIG_MACB - macb_hw_init(); -#endif -#ifdef CONFIG_ATMEL_SPI0 - /* (n+4) denotes to use nSPISEL(0) in GPIO mode! */ - at91_spi0_hw_init(1 << (FRAM_CS_NUM + 4)); -#endif -#ifdef CONFIG_ATMEL_SPI1 - at91_spi1_hw_init(1 << (ENC_CS_NUM + 4)); -#endif - return 0; -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - /* read 'factory' part of EEPROM */ - read_factory_r(); - return 0; -} -#endif - -int dram_init(void) -{ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ - /* - * Initialize ethernet HW addresses prior to starting Linux, - * needed for nfsroot. - * TODO: We need to investigate if that is really necessary. - */ - eth_init(gd->bd); -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; - int num = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, - (void *)ATMEL_BASE_EMAC0, - CONFIG_SYS_PHY_ID); - if (!rc) - num++; -#endif -#ifdef CONFIG_ENC28J60 - rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM, - ENC_SPI_CLOCK, SPI_MODE_0); - if (!rc) - num++; -# ifdef CONFIG_ENC28J60_2 - rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+1, - ENC_SPI_CLOCK, SPI_MODE_0); - if (!rc) - num++; -# ifdef CONFIG_ENC28J60_3 - rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+2, - ENC_SPI_CLOCK, SPI_MODE_0); - if (!rc) - num++; -# endif -# endif -#endif - return num; -} - -/* - * I2C access functions - * - * Note: - * We need to access Bus 0 before relocation to access the - * environment settings. - * However i2c_get_bus_num() cannot be called before - * relocation. - */ -#ifdef CONFIG_SYS_I2C_SOFT -void iic_init(void) -{ - /* ports are now initialized in board_early_init_f() */ -} - -int iic_read(void) -{ - switch (I2C_ADAP_HWNR) { - case 0: - return at91_get_pio_value(I2C0_PORT, SDA0_PIN); - case 1: - return at91_get_pio_value(I2C1_PORT, SDA1_PIN); - } - return 1; -} - -void iic_sda(int bit) -{ - switch (I2C_ADAP_HWNR) { - case 0: - at91_set_pio_value(I2C0_PORT, SDA0_PIN, bit); - break; - case 1: - at91_set_pio_value(I2C1_PORT, SDA1_PIN, bit); - break; - } -} - -void iic_scl(int bit) -{ - switch (I2C_ADAP_HWNR) { - case 0: - at91_set_pio_value(I2C0_PORT, SCL0_PIN, bit); - break; - case 1: - at91_set_pio_value(I2C1_PORT, SCL1_PIN, bit); - break; - } -} - -#endif diff --git a/board/enbw/enbw_cmc/Kconfig b/board/enbw/enbw_cmc/Kconfig new file mode 100644 index 0000000000..796736d865 --- /dev/null +++ b/board/enbw/enbw_cmc/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ENBW_CMC + +config SYS_BOARD + default "enbw_cmc" + +config SYS_VENDOR + default "enbw" + +config SYS_CONFIG_NAME + default "enbw_cmc" + +endif diff --git a/board/enbw/enbw_cmc/MAINTAINERS b/board/enbw/enbw_cmc/MAINTAINERS new file mode 100644 index 0000000000..f7c99207db --- /dev/null +++ b/board/enbw/enbw_cmc/MAINTAINERS @@ -0,0 +1,6 @@ +ENBW_CMC BOARD +M: Heiko Schocher +S: Maintained +F: board/enbw/enbw_cmc/ +F: include/configs/enbw_cmc.h +F: configs/enbw_cmc_defconfig diff --git a/board/enbw/enbw_cmc/Makefile b/board/enbw/enbw_cmc/Makefile index 16e390d80b..054d6e7c83 100644 --- a/board/enbw/enbw_cmc/Makefile +++ b/board/enbw/enbw_cmc/Makefile @@ -7,23 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := enbw_cmc.o diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index c477962f34..53b8362147 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -29,13 +29,14 @@ #include #include #include -#include +#include #include #include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile deleted file mode 100644 index c573be952c..0000000000 --- a/board/ep8248/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c deleted file mode 100644 index 736c1806d1..0000000000 --- a/board/ep8248/ep8248.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Embedded Planet EP8248 boards. - * Tested on EP8248E. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */ - /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */ - /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -int board_early_init_f (void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - bcsr[4] |= 0x30; /* Turn the LEDs off */ - -#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC) - bcsr[6] |= 0x10; -#endif -#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC) - bcsr[7] |= 0x10; -#endif - -#if CONFIG_SYS_FCC1 - bcsr[8] |= 0xC0; -#endif /* CONFIG_SYS_FCC1 */ -#if CONFIG_SYS_FCC2 - bcsr[8] |= 0x30; -#endif /* CONFIG_SYS_FCC2 */ - - return 0; -} - -phys_size_t initdram(int board_type) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - long int msize = 16L << (bcsr[2] & 3); - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE; - uchar c = 0xFF; - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or1 = CONFIG_SYS_SDRAM_OR; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BR; - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* !CONFIG_SYS_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - puts("Board: "); - switch (bcsr[0]) { - case 0x0C: - printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]); - break; - default: - printf("unknown: ID=%02X\n", bcsr[0]); - } - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup( blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile deleted file mode 100644 index 0a716f9535..0000000000 --- a/board/ep8260/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o mii_phy.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c deleted file mode 100644 index 3697d24fdf..0000000000 --- a/board/ep8260/ep8260.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Frank Panno , Delphin Technology AG - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "ep8260.h" -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Setup CS4 to enable the Board Control/Status registers. - * Otherwise the smcs won't work. -*/ -int board_early_init_f (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */ - regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */ - return 0; -} - -void reset_phy (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; - - regs->bcsr4 = 0xC0; -} - -/* - * Check Board Identity: - * I don' know, how the next board revisions will be coded. - * Thats why its a static interpretation ... -*/ - -int checkboard (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; - uint major = 0, minor = 0; - - switch (regs->bcsr0) { - case 0x02: - major = 1; - break; - case 0x03: - major = 1; - minor = 1; - break; - case 0x06: - major = 1; - minor = 3; - break; - default: - break; - } - printf ("Board: Embedded Planet EP8260, Revision %d.%d\n", - major, minor); - return 0; -} - - -/* ------------------------------------------------------------------------- */ - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110; - -/* - ulong psdmr = CONFIG_SYS_PSDMR; -#ifdef CONFIG_SYS_LSDRAM - ulong lsdmr = CONFIG_SYS_LSDMR; -#endif -*/ - long size = CONFIG_SYS_SDRAM0_SIZE; - int i; - - -/* -* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): -* -* "At system reset, initialization software must set up the -* programmable parameters in the memory controller banks registers -* (ORx, BRx, P/LSDMR). After all memory parameters are configured, -* system software should execute the following initialization sequence -* for each SDRAM device. -* -* 1. Issue a PRECHARGE-ALL-BANKS command -* 2. Issue eight CBR REFRESH commands -* 3. Issue a MODE-SET command to initialize the mode register -* -* The initial commands are executed by setting P/LSDMR[OP] and -* accessing the SDRAM with a single-byte transaction." -* -* The appropriate BRx/ORx registers have already been set when we -* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. -*/ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - -#ifndef CONFIG_SYS_RAMBOOT -#ifdef CONFIG_SYS_LSDRAM - size += CONFIG_SYS_SDRAM1_SIZE; - ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c; - memctl->memc_lsrt = CONFIG_SYS_LSRT; - - memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; -#endif /* CONFIG_SYS_LSDRAM */ -#endif /* CONFIG_SYS_RAMBOOT */ - return (size * 1024 * 1024); -} diff --git a/board/ep8260/ep8260.h b/board/ep8260/ep8260.h deleted file mode 100644 index 3032b14245..0000000000 --- a/board/ep8260/ep8260.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __EP8260_H__ -#define __EP8260_H__ - -typedef struct tt_ep_regs { - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; - volatile unsigned char bcsr6; - volatile unsigned char bcsr7; - volatile unsigned char bcsr8; - volatile unsigned char bcsr9; - volatile unsigned char bcsr10; - volatile unsigned char bcsr11; - volatile unsigned char bcsr12; - volatile unsigned char bcsr13; - volatile unsigned char bcsr14; - volatile unsigned char bcsr15; -} t_ep_regs; -typedef t_ep_regs *tp_ep_regs; - -#endif diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c deleted file mode 100644 index 44f63ee382..0000000000 --- a/board/ep8260/flash.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Frank Panno , Delphin Technology AG - * - * Flash Routines for AMD device AM29DL323DB on the EP8260 board. - * - * This file is based on board/tqm8260/flash.c. - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ -void flash_reset(void) -{ - if( flash_info[0].flash_id != FLASH_UNKNOWN ) { - V_ULONG( flash_info[0].start[0] ) = 0x00F000F0; - V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0; - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size( ulong baseaddr, flash_info_t *info ) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - /* Write auto select command sequence and test FLASH answer */ - V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA; - V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055; - V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090; - V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA; - V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055; - V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090; - - flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */ - flashtest_l = V_ULONG(baseaddr + 4); - - if ((int)flashtest_h == AMD_MANUFACT) { - info->flash_id = FLASH_MAN_AMD; - } else { - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - flashtest_h = V_ULONG(baseaddr + 8); /* device ID */ - flashtest_l = V_ULONG(baseaddr + 12); - if (flashtest_h != flashtest_l) { - info->flash_id = FLASH_UNKNOWN; - return(0); - } - - switch((int)flashtest_h) { - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 4 * 4 MB = 16 MB */ - break; - case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */ - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x02000000; /* 4 * 8 MB = 32 MB */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return(0); /* no or unknown flash */ - } - - if(flashtest_h == AMD_ID_LV640U) { - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - } else { - /* set up sector start adress table (bottom sector type) */ - for (i = 0; i < 8; i++) { - info->start[i] = baseaddr + (i * 0x00008000); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000; - } - } - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) || - (V_ULONG( info->start[i] + 20 ) & 0x00010001)) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset(); - return(info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i>20); - } - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AMLV640U: printf ("29LV640U (64 M, uniform sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - V_ULONG( info->start[sect] ) = 0x00300030; - V_ULONG( info->start[sect] + 4 ) = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 || - (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080) - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - -static int write_dword (flash_info_t *, ulong, unsigned char *); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++; - if ((rc = write_dword(info, dp, bb)) != 0) - { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword(info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i); - } - return (write_dword(info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata) -{ - ulong start; - ulong cl = 0, ch =0; - int flag, i; - - for (ch=0, i=0; i < 4; i++) - ch = (ch << 8) + *pdata++; /* high word */ - for (cl=0, i=0; i < 4; i++) - cl = (cl << 8) + *pdata++; /* low word */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & ch) != ch - ||(*((vu_long *)(dest + 4)) & cl) != cl) - { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0; - V_ULONG( dest ) = ch; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0; - V_ULONG( dest + 4 ) = cl; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) || - ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/ep8260/mii_phy.c b/board/ep8260/mii_phy.c deleted file mode 100644 index c7aa2755f7..0000000000 --- a/board/ep8260/mii_phy.c +++ /dev/null @@ -1,107 +0,0 @@ -#include -#include -#include "ep8260.h" - -#define MII_MDIO 0x01 -#define MII_MDCK 0x02 -#define MII_MDIR 0x04 - -void -mii_discover_phy(void) -{ - int known; - unsigned short phy_reg; - unsigned long phy_id; - - known = 0; - printf("Discovering phy @ 0: "); - phy_id = mii_phy_read(2) << 16; - phy_id |= mii_phy_read(3); - if ((phy_id & 0xFFFFFC00) == 0x00137800) { - printf("Level One "); - if ((phy_id & 0x000003F0) == 0xE0) { - printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); - known = 1; - } - else printf("unknown type\n"); - } - else printf("unknown OUI = 0x%08lX\n", phy_id); - - phy_reg = mii_phy_read(1); - if (!(phy_reg & 0x0004)) printf("Link is down\n"); - if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); - if (phy_reg & 0x0002) printf("Jabber condition detected\n"); - if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); - - if (known) { - phy_reg = mii_phy_read(17); - if (phy_reg & 0x0400) - printf("Phy operating at %d MBit/s in %s-duplex mode\n", - phy_reg & 0x4000 ? 100 : 10, - phy_reg & 0x0200 ? "full" : "half"); - else - printf("bad link!!\n"); -/* -left off: no link, green 100MBit, yellow 10MBit -right off: no activity, green full-duplex, yellow half-duplex -*/ - mii_phy_write(20, 0x0452); - } -} - -unsigned short -mii_phy_read(unsigned short reg) -{ - int i; - unsigned short tmp, val = 0, adr = 0; - t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x6002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - regs->bcsr4 |= MII_MDIR; - for (i = 0; i < 16; i++) { - val <<= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); - if (regs->bcsr4 & MII_MDIO) val |= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); - } - return val; -} - -void -mii_phy_write(unsigned short reg, unsigned short val) -{ - int i; - unsigned short tmp, adr = 0; - t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x5002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (val & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - val <<= 1; - } -} diff --git a/board/ep82xxm/Makefile b/board/ep82xxm/Makefile deleted file mode 100644 index 459d7b8ab1..0000000000 --- a/board/ep82xxm/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c deleted file mode 100644 index fdde5355b5..0000000000 --- a/board/ep82xxm/ep82xxm.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright (C) 2006 Embedded Planet, LLC. - * - * Support for Embedded Planet EP82xxM boards. - * Tested on EP82xxM (MPC8270). - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#endif -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC2 1 -#define CONFIG_SYS_FCC3 1 - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */ - /* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */ - /* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */ - /* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */ - /* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */ - /* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */ - /* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */ - /* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */ - /* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */ - /* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */ - /* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */ - /* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */ - /* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */ - /* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */ - /* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */ - /* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */ - /* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */ - /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */ - /* PC17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */ - /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */ - /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */ - /* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ - /* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */ - /* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ - /* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */ - /* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */ - /* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */ - /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */ - /* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */ - /* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */ - /* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -#ifdef CONFIG_PCI -typedef struct pci_ic_s { - unsigned long pci_int_stat; - unsigned long pci_int_mask; -}pci_ic_t; -#endif - -int board_early_init_f (void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - bcsr[4] |= 0x30; /* Turn the LEDs off */ - -#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC) - bcsr[6] |= 0x10; -#endif -#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC) - bcsr[7] |= 0x10; -#endif - -#if CONFIG_SYS_FCC3 - bcsr[8] |= 0xC0; -#endif /* CONFIG_SYS_FCC3 */ -#if CONFIG_SYS_FCC2 - bcsr[8] |= 0x30; -#endif /* CONFIG_SYS_FCC2 */ - - return 0; -} - -phys_size_t initdram(int board_type) -{ - /* Size in MB of SDRAM populated on board*/ - long int msize = 256; - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - unsigned char *ramptr1 = (unsigned char *)0x00000110; - __maybe_unused unsigned char ramtmp; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -udelay(400); - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or1 = CONFIG_SYS_SDRAM_OR; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BR; - memctl->memc_psdmr = psdmr; - -udelay(400); - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ - ramtmp = *ramptr1; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) { - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - } - ramtmp = *ramptr1; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ - *ramptr1 = 0xFF; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ -#endif /* !CONFIG_SYS_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - puts("Board: "); - switch (bcsr[0]) { - case 0x0A: - printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]); - break; - default: - printf("unknown: ID=%02X\n", bcsr[0]); - } - - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/ep88x/Makefile b/board/ep88x/Makefile deleted file mode 100644 index 07fa3f3a2f..0000000000 --- a/board/ep88x/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c deleted file mode 100644 index 8a60b5850f..0000000000 --- a/board/ep88x/ep88x.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2005 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Embedded Planet EP88x boards. - * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* - * SDRAM uses two Micron chips. - * Minimal CPU frequency is 40MHz. - */ -static uint sdram_table[] = { - /* Single read (offset 0x00 in UPM RAM) */ - 0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404, - 0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, - - /* Burst read (offset 0x08 in UPM RAM) */ - 0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404, - 0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00, - 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, - 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, - - /* Single write (offset 0x18 in UPM RAM) */ - 0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404, - 0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, - - /* Burst write (offset 0x20 in UPM RAM) */ - 0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400, - 0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05, - 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, - 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, - - /* Refresh (offset 0x30 in UPM RAM) */ - 0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04, - 0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4, - - /* Exception (offset 0x3C in UPM RAM) */ - 0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05 -}; - -int board_early_init_f (void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - bcsr[0] |= 0x0C; /* Turn the LEDs off */ - bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for - flash detection by CFI driver - */ - -#if defined(CONFIG_8xx_CONS_SMC1) - bcsr[6] |= 0x10; /* Enables RS-232 transceiver */ -#endif -#if defined(CONFIG_8xx_CONS_SCC2) - bcsr[7] |= 0x10; /* Enables RS-232 transceiver */ -#endif -#ifdef CONFIG_ETHER_ON_FEC1 - bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */ -#endif -#ifdef CONFIG_ETHER_ON_FEC2 - bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */ -#endif - - return 0; -} - -phys_size_t initdram (int board_type) -{ - long int msize; - volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* Configure SDRAM refresh */ - memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */ - - memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */ - udelay(100); - - /* Run MRS pattern from location 0x36 */ - memctl->memc_mar = 0x88; - memctl->memc_mcr = 0x80002236; - udelay(100); - - memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ - memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; - - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE); - memctl->memc_or1 |= ~(msize - 1); - - return msize; -} - -int checkboard( void ) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - puts("Board: "); - switch (bcsr[15]) { - case 0xE7: - puts("EP88xC 1.0"); - break; - default: - printf("unknown ID=%02X", bcsr[15]); - } - printf(" CPLD revision %d\n", bcsr[14]); - - return 0; -} diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds deleted file mode 100644 index cbb17d1aee..0000000000 --- a/board/ep88x/u-boot.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile deleted file mode 100644 index cbe2987ea2..0000000000 --- a/board/esd/adciop/Makefile +++ /dev/null @@ -1,32 +0,0 @@ - -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c deleted file mode 100644 index b3d637e0a2..0000000000 --- a/board/esd/adciop/adciop.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include "adciop.h" - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* ------------------------------------------------------------------------- */ - - -int board_early_init_f (void) -{ - /* - * Set port pin in escc2 to keep living, and configure user led output - */ - *(unsigned char *) 0x2000033e = 0x77; /* ESCC2: PCR bit3=pwr on, bit7=led out */ - *(unsigned char *) 0x2000033c = 0x88; /* ESCC2: PVR pwr on, led off */ - - /* - * Init pci regs - */ - *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */ - *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */ - *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */ - *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */ - *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */ - *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */ - *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */ - - return 0; -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "ADCIOP", 6)) { - puts ("### No HW ID - assuming ADCIOP\n"); - return (1); - } - - puts (str); - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/esd/adciop/adciop.h b/board/esd/adciop/adciop.h deleted file mode 100644 index 75e7950bcd..0000000000 --- a/board/esd/adciop/adciop.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c deleted file mode 100644 index b1db12ecc8..0000000000 --- a/board/esd/adciop/flash.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM+size_b0-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0-1, - &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0), - &flash_info[1]); - - flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0+size_b1-1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect(FLAG_PROTECT_CLEAR, - FLASH_BASE0_PRELIM+size_b0-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0-1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile deleted file mode 100644 index b84e6624bf..0000000000 --- a/board/esd/apc405/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o \ - ../common/misc.o \ - ../common/auto_update.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c deleted file mode 100644 index f13f088d55..0000000000 --- a/board/esd/apc405/apc405.c +++ /dev/null @@ -1,461 +0,0 @@ -/* - * (C) Copyright 2005-2008 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#undef FPGA_DEBUG - -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -#ifdef CONFIG_LCD_USED -/* logo bitmap data - gzip compressed and generated by bin2c */ -unsigned char logo_bmp[] = -{ -#include "logo_640_480_24bpp.c" -}; - -/* - * include common lcd code (for esd boards) - */ -#include "../common/lcd.c" -#include "../common/s1d13505_640_480_16bpp.h" -#include "../common/s1d13806_640_480_16bpp.h" -#endif /* CONFIG_LCD_USED */ - -/* - * include common auto-update code (for esd boards) - */ -#include "../common/auto_update.h" - -au_image_t au_image[] = { - {"preinst.img", 0, -1, AU_SCRIPT}, - {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT}, - {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT}, - {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT}, - {"work.img", 0xfe500000, 0x01400000, AU_NOR}, - {"data.img", 0xff900000, 0x00580000, AU_NOR}, - {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT}, - {"postinst.img", 0, 0, AU_SCRIPT}, -}; - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - -int board_revision(void) -{ - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Get version of APC405 board from GPIO's - */ - - /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000); - - /* wait some time before reading input */ - udelay(1000); - - /* get config bits */ - value = in_be32((void*)GPIO0_IR) & 0x001c0000; - /* - * Restore GPIO settings - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - switch (value) { - case 0x001c0000: - /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */ - return 2; - case 0x000c0000: - /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */ - return 3; - case 0x00180000: - /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */ - return 6; - case 0x00140000: - /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */ - return 8; - default: - /* should not be reached! */ - return 0; - } -} - -int board_early_init_f (void) -{ - /* - * First pull fpga-prg pin low, to disable fpga logic - */ - out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out_be32((void*)GPIO0_OR, 0); /* pull prg low */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - /* - * New boards have a single 32MB flash connected to CS0 - * instead of two 16MB flashes on CS0+1. - */ - if (board_revision() >= 8) { - /* disable CS1 */ - mtebc(PB1AP, 0); - mtebc(PB1CR, 0); - - /* resize CS0 to 32MB */ - mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8); - mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8); - } - - return 0; -} - -int board_early_init_r(void) -{ - if (gd->board_type >= 8) - cfi_flash_num_flash_banks = 1; - - return 0; -} - -#define FUJI_BASE 0xf0100200 -#define LCDBL_PWM 0xa0 -#define LCDBL_PWMMIN 0xa4 -#define LCDBL_PWMMAX 0xa8 - -int misc_init_r(void) -{ - u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); - u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2); - u8 *duart0_mcr = (u8 *)(DUART0_BA + 4); - u8 *duart1_mcr = (u8 *)(DUART1_BA + 4); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - unsigned long CPC0_CR0Reg; - char *str; - uchar *logo_addr; - ulong logo_size; - ushort minb, maxb; - int result; - - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf("GUNZIP ERROR - must RESET board to recover\n"); - do_reset(NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: " - "INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: " - "INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: " - "DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len + 3; - } - putc('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index = 0; index < 1000; index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - - /* restore gpio/cs settings */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = dst[index]; - printf("%s ", &(dst[index + 1])); - index += len + 3; - } - putc('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Write board revision in FPGA - */ - out_be16(fpga_ctrl2, - (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f)); - - /* - * Enable power on PS/2 interface (with reset) - */ - out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET); - for (i=0;i<100;i++) - udelay(1000); - udelay(1000); - out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET); - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8(duart0_mcr, 0x08); - out_8(duart1_mcr, 0x08); - - /* - * Init lcd interface and display logo - */ - str = getenv("splashimage"); - if (str) { - logo_addr = (uchar *)simple_strtoul(str, NULL, 16); - logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; - } else { - logo_addr = logo_bmp; - logo_size = sizeof(logo_bmp); - } - - if (gd->board_type >= 6) { - result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, - (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13505_640_480_16bpp, - sizeof(regs_13505_640_480_16bpp) / - sizeof(regs_13505_640_480_16bpp[0]), - logo_addr, logo_size); - if (result && str) { - /* retry with internal image */ - logo_addr = logo_bmp; - logo_size = sizeof(logo_bmp); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, - (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13505_640_480_16bpp, - sizeof(regs_13505_640_480_16bpp) / - sizeof(regs_13505_640_480_16bpp[0]), - logo_addr, logo_size); - } - } else { - result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, - (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp) / - sizeof(regs_13806_640_480_16bpp[0]), - logo_addr, logo_size); - if (result && str) { - /* retry with internal image */ - logo_addr = logo_bmp; - logo_size = sizeof(logo_bmp); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, - (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp) / - sizeof(regs_13806_640_480_16bpp[0]), - logo_addr, logo_size); - } - } - - /* - * Reset microcontroller and setup backlight PWM controller - */ - out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014); - for (i=0;i<10;i++) - udelay(1000); - out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c); - - minb = 0; - maxb = 0xff; - str = getenv("lcdbl"); - if (str) { - minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff; - if (str && (*str=',')) { - str++; - maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff; - } else - minb = 0; - - out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb); - out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb); - - printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb); - } - out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff); - - /* - * fix environment for field updated units - */ - if (getenv("altbootcmd") == NULL) { - setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND); - setenv("usbargs", CONFIG_SYS_USB_ARGS); - setenv("bootcmd", CONFIG_BOOTCOMMAND); - setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND); - setenv("bootlimit", CONFIG_SYS_BOOTLIMIT); - setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND); - saveenv(); - } - - return (0); -} - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming APC405"); - } else { - puts(str); - } - - gd->board_type = board_revision(); - printf(", Rev. 1.%ld\n", gd->board_type); - - return 0; -} - -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); - - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { - out_be16(fpga_mode, - in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET); - } else { - out_be16(fpga_mode, - in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET); - } -} -#endif /* CONFIG_IDE_RESET */ - -void reset_phy(void) -{ - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -} - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) -int usb_board_init(void) -{ - return 0; -} - -int usb_board_stop(void) -{ - unsigned short tmp; - int i; - - /* - * reset PCI bus - * This is required to make some very old Linux OHCI driver - * work after U-Boot has used the OHCI controller. - */ - pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp); - pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000)); - - for (i = 0; i < 100; i++) - udelay(1000); - - pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp); - return 0; -} - -int usb_board_init_fail(void) -{ - usb_board_stop(); - return 0; -} -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c deleted file mode 100644 index b68668c153..0000000000 --- a/board/esd/apc405/fpgadata.c +++ /dev/null @@ -1,4008 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0x49, 0xe1, 0xdb, 0x46, -0x00, 0x03, 0x61, 0x62, 0x67, 0x34, 0x30, 0x35, -0x5f, 0x31, 0x5f, 0x30, 0x33, 0x2e, 0x62, 0x69, -0x74, 0x00, 0xed, 0xfd, 0x7d, 0x7c, 0x14, 0xd7, -0x75, 0x3f, 0x8e, 0x9f, 0xb9, 0x33, 0x12, 0xa3, -0xdd, 0x95, 0x76, 0xf4, 0xe4, 0xac, 0x6d, 0x20, -0xa3, 0x95, 0x20, 0x6b, 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a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile deleted file mode 100644 index e5caf2331a..0000000000 --- a/board/esd/ar405/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ../common/misc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c deleted file mode 100644 index d33aba4713..0000000000 --- a/board/esd/ar405/ar405.c +++ /dev/null @@ -1,394 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include "ar405.h" -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -const unsigned char fpgadata_xl30[] = { -#include "fpgadata_xl30.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - int index, len, i; - int status; - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - /* first try 40er image */ - gd->board_type = 40; - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* try xl30er image */ - gd->board_type = 30; - status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - } - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */ - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - const unsigned char *fpga; - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming AR405"); - } else { - puts(str); - } - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - if (gd->board_type == 30) { - fpga = fpgadata_xl30; - } else { - fpga = fpgadata; - } - index = 15; - for (i = 0; i < 4; i++) { - len = fpga[index]; - printf ("%s ", &(fpga[index + 1])); - index += len + 3; - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - - -#if 1 /* test-only: some internal test routines... */ -#define DIGEN ((void *)0xf03000b4) /* u8 */ -#define DIGOUT ((void *)0xf03000b0) /* u16 */ -#define DIGIN ((void *)0xf03000a0) /* u16 */ - -/* - * Some test routines - */ -int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - int k; - int start; - int end; - - if (argc != 3) { - puts("Usage: digtest n_start n_end (digtest 0 7)\n"); - return 0; - } - - start = simple_strtol (argv[1], NULL, 10); - end = simple_strtol (argv[2], NULL, 10); - - /* - * Enable digital outputs - */ - out_8(DIGEN, 0x08); - - printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n", - start, end); - - /* - * Set outputs one by one - */ - for (;;) { - for (i=start; i<=end; i++) { - out_be16(DIGOUT, 0x0001 << i); - for (k=0; k<200; k++) - udelay(1000); - - if (in_be16(DIGIN) != (0x0001 << i)) { - printf("ERROR: OUT=0x%04X, IN=0x%04X\n", - 0x0001 << i, in_be16(DIGIN)); - return 0; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - } - } - - return 0; -} -U_BOOT_CMD( - digtest, 3, 1, do_digtest, - "Test digital in-/output", - "" -); - -#define ERROR_DELTA 256 - -struct io { - short val; - short dummy; -}; - -int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - short val; - int i; - int volt; - struct io *out; - struct io *in; - - out = (struct io *)0xf0300090; - in = (struct io *)0xf0300000; - - i = simple_strtol (argv[1], NULL, 10); - - volt = 0; - printf("Setting Channel %d to %dV...\n", i, volt); - out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10); - udelay(10000); - val = in_be16((void *)&(in[i*2].val)); - printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - val = in_be16((void *)&(in[i*2+1].val)); - printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - - volt = 5; - printf("Setting Channel %d to %dV...\n", i, volt); - out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10); - udelay(10000); - val = in_be16((void *)&(in[i*2].val)); - printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - val = in_be16((void *)&(in[i*2+1].val)); - printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - - volt = 10; - printf("Setting Channel %d to %dV...\n", i, volt); - out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10); - udelay(10000); - val = in_be16((void *)&(in[i*2].val)); - printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - val = in_be16((void *)&(in[i*2+1].val)); - printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - - printf("Channel %d OK!\n", i); - - return 0; -} -U_BOOT_CMD( - anatest, 2, 1, do_anatest, - "Test analog in-/output", - "" -); - - -int counter = 0; - -void cyclicInt(void *ptr) -{ - out_be16((void *)0xf03000e8, 0x0800); /* ack int */ - counter++; -} - - -int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong *incin; - int i; - - incin = (ulong *)0xf0300040; - - /* - * Clear inc counter - */ - out_be32((void *)&incin[0], 0); - out_be32((void *)&incin[1], 0); - out_be32((void *)&incin[2], 0); - out_be32((void *)&incin[3], 0); - - incin = (ulong *)0xf0300050; - - /* - * Inc a little - */ - for (i=0; i<10000; i++) { - switch (i & 0x03) { - case 0: - out_8(DIGEN, 0x02); - break; - case 1: - out_8(DIGEN, 0x03); - break; - case 2: - out_8(DIGEN, 0x01); - break; - case 3: - out_8(DIGEN, 0x00); - break; - } - udelay(10); - } - - printf("Inc 0 = %d\n", in_be32((void *)&incin[0])); - printf("Inc 1 = %d\n", in_be32((void *)&incin[1])); - printf("Inc 2 = %d\n", in_be32((void *)&incin[2])); - printf("Inc 3 = %d\n", in_be32((void *)&incin[3])); - - out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */ - out_be16((void *)0xf03000ec, - in_be16((void *)0xf03000ec) | 0x0800); /* enable int */ - irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL); - printf("counter=%d\n", counter); - - return 0; -} -U_BOOT_CMD( - inctest, 3, 1, do_inctest, - "Test incremental encoder inputs", - "" -); -#endif diff --git a/board/esd/ar405/ar405.h b/board/esd/ar405/ar405.h deleted file mode 100644 index 75e7950bcd..0000000000 --- a/board/esd/ar405/ar405.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c deleted file mode 100644 index 23e81642e0..0000000000 --- a/board/esd/ar405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); - udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); - udelay(1000); /* wait 1ms */ - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8((void *)(DUART0_BA + 4), 0x08); - out_8((void *)(DUART1_BA + 4), 0x08); - out_8((void *)(DUART2_BA + 4), 0x08); - out_8((void *)(DUART3_BA + 4), 0x08); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming ASH405"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c deleted file mode 100644 index 23e81642e0..0000000000 --- a/board/esd/ash405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include "canbt.h" -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -/* fpga configuration data */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - unsigned long CPC0_CR0Reg; - int index, len, i; - int status; - - /* - * Setup GPIO pins - */ - CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff; - CPC0_CR0Reg |= 0x0070f000; - mtdcr (CPC0_CR0, CPC0_CR0Reg); - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - - /* - * Setup port pins for normal operation - */ - out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32 ((void *)GPIO0_TCR, 0x07038100); /* setup for output */ - out_be32 ((void *)GPIO0_OR, 0x07030100); /* set output pins to high (default) */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "CANBT", 5)) { - puts ("### No HW ID - assuming CANBT\n"); - return (0); - } - - puts (str); - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - - putc ('\n'); - - return 0; -} diff --git a/board/esd/canbt/canbt.h b/board/esd/canbt/canbt.h deleted file mode 100644 index 75e7950bcd..0000000000 --- a/board/esd/canbt/canbt.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c deleted file mode 100644 index 34bdc053fc..0000000000 --- a/board/esd/canbt/flash.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - /* - * Reset CPLD via GPIO12 (CS3) pin - */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET); - udelay(1000); /* wait 1ms */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET); - udelay(1000); /* wait 1ms */ - - return 0; -} - -int misc_init_r (void) -{ - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Setup and enable EEPROM write protection - */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - - return (0); -} - - -/* - * Check Board Identity: - */ -#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000) -int checkboard (void) -{ - char str[64]; - int flashcnt; - int delay; - - puts ("Board: "); - - if (getenv_f("serial#", str, sizeof(str)) == -1) { - puts ("### No HW ID - assuming CMS700"); - } else { - puts(str); - } - - printf(" (PLD-Version=%02d)\n", - in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001))); - - /* - * Flash LEDs - */ - for (flashcnt = 0; flashcnt < 3; flashcnt++) { - out_8((void *)LED_REG, 0x00); /* LEDs off */ - for (delay = 0; delay < 100; delay++) - udelay(1000); - out_8((void *)LED_REG, 0x0f); /* LEDs on */ - for (delay = 0; delay < 50; delay++) - udelay(1000); - } - out_8((void *)LED_REG, 0x70); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - -/* ------------------------------------------------------------------------- */ - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c deleted file mode 100644 index 23e81642e0..0000000000 --- a/board/esd/cms700/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i - -#include -#include -#include -#include -#include - -#include "auto_update.h" - -#ifdef CONFIG_AUTO_UPDATE - -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" -#endif - -extern au_image_t au_image[]; -extern int N_AU_IMAGES; - -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x100000) -#define MAX_LOADSZ 0x1c00000 - -/* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); -long do_fat_read (const char *filename, void *buffer, - unsigned long maxsize, int dols); -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); - -extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE]; - -int au_check_cksum_valid(int i, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if ((au_image[i].type == AU_FIRMWARE) && - (au_image[i].size != image_get_data_size (hdr))) { - printf ("Image %s has wrong size\n", au_image[i].name); - return -1; - } - - if (nbytes != (image_get_image_size (hdr))) { - printf ("Image %s bad total SIZE\n", au_image[i].name); - return -1; - } - - /* check the data CRC */ - if (!image_check_dcrc (hdr)) { - printf ("Image %s bad data checksum\n", au_image[i].name); - return -1; - } - return 0; -} - -int au_check_header_valid(int i, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* check the easy ones first */ - if (nbytes < image_get_header_size ()) { - printf ("Image %s bad header SIZE\n", au_image[i].name); - return -1; - } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { - printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name); - return -1; - } - if (!image_check_hcrc (hdr)) { - printf ("Image %s bad header checksum\n", au_image[i].name); - return -1; - } - - /* check the type - could do this all in one gigantic if() */ - if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) && - !image_check_type (hdr, IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", au_image[i].name); - return -1; - } - if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) && - !image_check_type (hdr, IH_TYPE_SCRIPT)) { - printf ("Image %s wrong type\n", au_image[i].name); - return -1; - } - - return 0; -} - -int au_do_update(int i, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - int k; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - switch (au_image[i].type & AU_TYPEMASK) { - case AU_SCRIPT: - printf("Executing script %s\n", au_image[i].name); - - /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; - addr += 8; - - /* - * Replace cr/lf with ; - */ - k = 0; - while (addr[k] != 0) { - if ((addr[k] == 10) || (addr[k] == 13)) { - addr[k] = ';'; - } - k++; - } - - run_command(addr, 0); - return 0; - } - - break; - - case AU_FIRMWARE: - case AU_NOR: - case AU_NAND: - start = au_image[i].start; - end = au_image[i].start + au_image[i].size - 1; - - /* - * do not update firmware when image is already in flash. - */ - if (au_image[i].type == AU_FIRMWARE) { - char *orig = (char*)start; - char *new = (char *)((char *)hdr + - image_get_header_size ()); - nbytes = image_get_data_size (hdr); - - while (--nbytes) { - if (*orig++ != *new++) { - break; - } - } - if (!nbytes) { - printf ("Skipping firmware update - " - "images are identical\n"); - break; - } - } - - /* unprotect the address range */ - if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || - (au_image[i].type == AU_FIRMWARE)) { - flash_sect_protect (0, start, end); - } - - /* - * erase the address range. - */ - if (au_image[i].type != AU_NAND) { - printf ("Updating NOR FLASH with image %s\n", - au_image[i].name); - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase (start, end); - } - - udelay(10000); - - /* strip the header - except for the kernel and ramdisk */ - if (au_image[i].type != AU_FIRMWARE) { - addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); - } else { - addr = (char *)((char *)hdr + image_get_header_size ()); - off = 0; - nbytes = image_get_data_size (hdr); - } - - /* - * copy the data from RAM to FLASH - */ - if (au_image[i].type != AU_NAND) { - debug ("flash_write(%p, %lx, %x)\n", - addr, start, nbytes); - rc = flash_write ((char *)addr, start, - (nbytes + 1) & ~1); - } else { - rc = -1; - } - if (rc != 0) { - printf ("Flashing failed due to error %d\n", rc); - return -1; - } - - /* - * check the dcrc of the copy - */ - if (au_image[i].type != AU_NAND) { - rc = crc32 (0, (uchar *)(start + off), - image_get_data_size (hdr)); - } - if (rc != image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum After COPY\n", - au_image[i].name); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || - (au_image[i].type == AU_FIRMWARE)) { - flash_sect_protect (1, start, end); - } - - break; - - default: - printf("Wrong image type selected!\n"); - } - - return 0; -} - -static void process_macros (const char *input, char *output) -{ - char c, prev; - const char *varname_start = NULL; - int inputcnt = strlen (input); - int outputcnt = CONFIG_SYS_CBSIZE; - int state = 0; /* 0 = waiting for '$' */ - /* 1 = waiting for '(' or '{' */ - /* 2 = waiting for ')' or '}' */ - /* 3 = waiting for ''' */ -#ifdef DEBUG_PARSER - char *output_start = output; - - printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", - strlen(input), input); -#endif - - prev = '\0'; /* previous character */ - - while (inputcnt && outputcnt) { - c = *input++; - inputcnt--; - - if (state != 3) { - /* remove one level of escape characters */ - if ((c == '\\') && (prev != '\\')) { - if (inputcnt-- == 0) - break; - prev = c; - c = *input++; - } - } - - switch (state) { - case 0: /* Waiting for (unescaped) $ */ - if ((c == '\'') && (prev != '\\')) { - state = 3; - break; - } - if ((c == '$') && (prev != '\\')) { - state++; - } else { - *(output++) = c; - outputcnt--; - } - break; - case 1: /* Waiting for ( */ - if (c == '(' || c == '{') { - state++; - varname_start = input; - } else { - state = 0; - *(output++) = '$'; - outputcnt--; - - if (outputcnt) { - *(output++) = c; - outputcnt--; - } - } - break; - case 2: /* Waiting for ) */ - if (c == ')' || c == '}') { - int i; - char envname[CONFIG_SYS_CBSIZE], *envval; - /* Varname # of chars */ - int envcnt = input - varname_start - 1; - - /* Get the varname */ - for (i = 0; i < envcnt; i++) { - envname[i] = varname_start[i]; - } - envname[i] = 0; - - /* Get its value */ - envval = getenv (envname); - - /* Copy into the line if it exists */ - if (envval != NULL) - while ((*envval) && outputcnt) { - *(output++) = *(envval++); - outputcnt--; - } - /* Look for another '$' */ - state = 0; - } - break; - case 3: /* Waiting for ' */ - if ((c == '\'') && (prev != '\\')) { - state = 0; - } else { - *(output++) = c; - outputcnt--; - } - break; - } - prev = c; - } - - if (outputcnt) - *output = 0; - -#ifdef DEBUG_PARSER - printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", - strlen (output_start), output_start); -#endif -} - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int do_auto_update(void) -{ - block_dev_desc_t *stor_dev = NULL; - long sz; - int i, res, cnt, old_ctrlc; - char buffer[32]; - char str[80]; - int n; - - if (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) { - stor_dev = get_dev ("ide", 0); - if (stor_dev == NULL) { - debug ("ide: unknown device\n"); - return -1; - } - } - - if (fat_register_device (stor_dev, 1) != 0) { - debug ("Unable to register ide disk 0:1\n"); - return -1; - } - - /* - * Check if magic file is present - */ - if ((n = do_fat_read (AU_MAGIC_FILE, buffer, - sizeof(buffer), LS_NO)) <= 0) { - debug ("No auto_update magic file (n=%d)\n", n); - return -1; - } - -#ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show (1); -#endif - puts("\nAutoUpdate Disk detected! Trying to update system...\n"); - - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc (0); - - /* just loop thru all the possible files */ - for (i = 0; i < N_AU_IMAGES; i++) { - /* - * Try to expand the environment var in the fname - */ - process_macros (au_image[i].name, str); - strcpy (au_image[i].name, str); - - printf("Reading %s ...", au_image[i].name); - /* just read the header */ - sz = do_fat_read (au_image[i].name, LOAD_ADDR, - image_get_header_size (), LS_NO); - debug ("read %s sz %ld hdr %d\n", - au_image[i].name, sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { - puts(" not found\n"); - continue; - } - if (au_check_header_valid (i, sz) < 0) { - puts(" header not valid\n"); - continue; - } - sz = do_fat_read (au_image[i].name, LOAD_ADDR, - MAX_LOADSZ, LS_NO); - debug ("read %s sz %ld hdr %d\n", - au_image[i].name, sz, image_get_header_size ()); - if (sz <= 0 || sz <= image_get_header_size ()) { - puts(" not found\n"); - continue; - } - if (au_check_cksum_valid (i, sz) < 0) { - puts(" checksum not valid\n"); - continue; - } - puts(" done\n"); - - do { - res = au_do_update (i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc ()) { - clear_ctrlc (); - break; - } - cnt++; - } while (res < 0); - } - - /* restore the old state */ - disable_ctrlc (old_ctrlc); - - puts("AutoUpdate finished\n\n"); -#ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show (0); -#endif - - return 0; -} - -int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - do_auto_update(); - - return 0; -} -U_BOOT_CMD( - autoupd, 1, 1, auto_update, - "Automatically update images", - "" -); -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h deleted file mode 100644 index be8f439e47..0000000000 --- a/board/esd/common/auto_update.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _AUTO_UPDATE_H_ -#define _AUTO_UPDATE_H_ - -#define MBR_MAGIC 0x07081967 -#define MBR_MAGIC_ADDR 0x100 /* offset 0x100 should be free space */ - -#define AU_MAGIC_FILE "__auto_update" - -#define AU_TYPEMASK 0x000000ff -#define AU_FLAGMASK 0xffff0000 - -#define AU_PROTECT 0x80000000 - -#define AU_SCRIPT 0x01 -#define AU_FIRMWARE (0x02 | AU_PROTECT) -#define AU_NOR 0x03 -#define AU_NAND 0x04 - -struct au_image_s { - char name[80]; - ulong start; - ulong size; - ulong type; -}; - -typedef struct au_image_s au_image_t; - -int do_auto_update(void); -#ifdef CONFIG_AUTO_UPDATE_SHOW -void board_auto_update_show(int au_active); -#endif - -#endif /* #ifndef _AUTO_UPDATE_H_ */ diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index 803179a472..95d18911c3 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -12,9 +12,6 @@ #endif #if defined(CONFIG_CMD_BSP) - -extern int do_source (cmd_tbl_t *, int, int, char *[]); - #define ADDRMASK 0xfffff000 /* @@ -27,7 +24,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int count2 = 0; char addr[16]; char str[] = "\\|/-"; - char *local_args[2]; u32 la, ptm1la; #if defined(CONFIG_440) @@ -84,9 +80,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Boot image via "source" command */ printf("executing script at addr 0x%s ...\n", addr); - local_args[0] = addr; - local_args[1] = NULL; - do_source(cmdtp, 0, 1, local_args); + source(la, NULL); break; case 2: diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h index 96e4b9972d..5b14bf9260 100644 --- a/board/esd/common/lcd.h +++ b/board/esd/common/lcd.h @@ -9,7 +9,7 @@ * Neutralize little endians. */ #define SWAP_LONG(data) ((unsigned long) \ - (((unsigned long)(data) >> 24) | \ + (((unsigned long)(data) >> 24) | \ ((unsigned long)(data) << 24) | \ (((unsigned long)(data) >> 8) & 0x0000ff00 ) | \ (((unsigned long)(data) << 8) & 0x00ff0000 ))) diff --git a/board/esd/common/s1d13806_640_480_8bpp.h b/board/esd/common/s1d13806_640_480_8bpp.h deleted file mode 100644 index ddc0289b2e..0000000000 --- a/board/esd/common/s1d13806_640_480_8bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_640_320_16bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x18}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x00}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register (8bpp) */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/cpci2dp/Kconfig b/board/esd/cpci2dp/Kconfig new file mode 100644 index 0000000000..646e8ffa1c --- /dev/null +++ b/board/esd/cpci2dp/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CPCI2DP + +config SYS_BOARD + default "cpci2dp" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "CPCI2DP" + +endif diff --git a/board/esd/cpci2dp/MAINTAINERS b/board/esd/cpci2dp/MAINTAINERS new file mode 100644 index 0000000000..660e1859c8 --- /dev/null +++ b/board/esd/cpci2dp/MAINTAINERS @@ -0,0 +1,6 @@ +CPCI2DP BOARD +M: Matthias Fuchs +S: Maintained +F: board/esd/cpci2dp/ +F: include/configs/CPCI2DP.h +F: configs/CPCI2DP_defconfig diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile index a6edac0c6c..ce2c6dd912 100644 --- a/board/esd/cpci2dp/Makefile +++ b/board/esd/cpci2dp/Makefile @@ -5,27 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index aade55ac67..336c551263 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -2,7 +2,7 @@ * (C) Copyright 2005 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/esd/cpci405/Kconfig b/board/esd/cpci405/Kconfig new file mode 100644 index 0000000000..0df2755177 --- /dev/null +++ b/board/esd/cpci405/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CPCI4052 + +config SYS_BOARD + default "cpci405" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "CPCI4052" + +endif diff --git a/board/esd/cpci405/MAINTAINERS b/board/esd/cpci405/MAINTAINERS new file mode 100644 index 0000000000..1da58dc002 --- /dev/null +++ b/board/esd/cpci405/MAINTAINERS @@ -0,0 +1,12 @@ +CPCI405 BOARD +M: Matthias Fuchs +S: Maintained +F: board/esd/cpci405/ +F: include/configs/CPCI405.h +F: configs/CPCI405_defconfig +F: include/configs/CPCI4052.h +F: configs/CPCI4052_defconfig +F: include/configs/CPCI405AB.h +F: configs/CPCI405AB_defconfig +F: include/configs/CPCI405DT.h +F: configs/CPCI405DT_defconfig diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile index 6868e6886a..7490b780ed 100644 --- a/board/esd/cpci405/Makefile +++ b/board/esd/cpci405/Makefile @@ -5,28 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o -COBJS += ../common/cmd_loadpci.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = cpci405.o flash.o ../common/misc.o +obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 63cd862d2d..bf5a4cb682 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -24,13 +24,7 @@ extern void __ft_board_setup(void *blob, bd_t *bd); const unsigned char fpgadata[] = { #if defined(CONFIG_CPCI405_VER2) -# if defined(CONFIG_CPCI405AB) -# include "fpgadata_cpci405ab.c" -# else -# include "fpgadata_cpci4052.c" -# endif -#else -# include "fpgadata_cpci405.c" +# include "fpgadata_cpci4052.c" #endif }; @@ -38,37 +32,6 @@ const unsigned char fpgadata[] = * include common fpga code (for esd boards) */ #include "../common/fpga.c" -#include "../common/auto_update.h" - -#if defined(CONFIG_CPCI405AB) -au_image_t au_image[] = { - {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, - {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, - {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, -}; -#else -#if defined(CONFIG_CPCI405_VER2) -au_image_t au_image[] = { - {"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, - {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, - {"cpci4052/postinst.img", 0, 0, AU_SCRIPT}, -}; -#else -au_image_t au_image[] = { - {"cpci405/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR}, - {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE}, - {"cpci405/postinst.img", 0, 0, AU_SCRIPT}, -}; -#endif -#endif - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); /* Prototypes */ int cpci405_version(void); @@ -508,7 +471,7 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -526,242 +489,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_strerror(rc)); } } -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -#if defined(CONFIG_CPCI405AB) -#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_MODE), \ - in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_MODE)) | \ - CONFIG_SYS_FPGA_MODE_1WIRE_DIR) - -#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_MODE), \ - in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_MODE)) & \ - ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) - -#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_STATUS)) & \ - CONFIG_SYS_FPGA_MODE_1WIRE) - -/* - * Generate a 1-wire reset, return 1 if no presence detect was found, - * return 0 otherwise. - * (NOTE: Does not handle alarm presence from DS2404/DS1994) - */ -int OWTouchReset(void) -{ - int result; - - ONE_WIRE_CLEAR; - udelay(480); - ONE_WIRE_SET; - udelay(70); - - result = ONE_WIRE_GET; - - udelay(410); - return result; -} - -/* - * Send 1 a 1-wire write bit. - * Provide 10us recovery time. - */ -void OWWriteBit(int bit) -{ - if (bit) { - /* - * write '1' bit - */ - ONE_WIRE_CLEAR; - udelay(6); - ONE_WIRE_SET; - udelay(64); - } else { - /* - * write '0' bit - */ - ONE_WIRE_CLEAR; - udelay(60); - ONE_WIRE_SET; - udelay(10); - } -} - -/* - * Read a bit from the 1-wire bus and return it. - * Provide 10us recovery time. - */ -int OWReadBit(void) -{ - int result; - - ONE_WIRE_CLEAR; - udelay(6); - ONE_WIRE_SET; - udelay(9); - - result = ONE_WIRE_GET; - - udelay(55); - return result; -} - -void OWWriteByte(int data) -{ - int loop; - - for (loop = 0; loop < 8; loop++) { - OWWriteBit(data & 0x01); - data >>= 1; - } -} - -int OWReadByte(void) -{ - int loop, result = 0; - - for (loop = 0; loop < 8; loop++) { - result >>= 1; - if (OWReadBit()) - result |= 0x80; - } - - return result; -} - -int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short val; - int result; - int i; - unsigned char ow_id[6]; - char str[32]; - - /* - * Clear 1-wire bit (open drain with pull-up) - */ - val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + - CONFIG_SYS_FPGA_MODE)); - val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */ - out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + - CONFIG_SYS_FPGA_MODE), val); - - result = OWTouchReset(); - if (result != 0) - puts("No 1-wire device detected!\n"); - - OWWriteByte(0x33); /* send read rom command */ - OWReadByte(); /* skip family code ( == 0x01) */ - for (i = 0; i < 6; i++) - ow_id[i] = OWReadByte(); - OWReadByte(); /* read crc */ - - sprintf(str, "%02X%02X%02X%02X%02X%02X", - ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]); - printf("Setting environment variable 'ow_id' to %s\n", str); - setenv("ow_id", str); - - return 0; -} -U_BOOT_CMD( - onewire, 1, 1, do_onewire, - "Read 1-write ID", - "" -); - -#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */ -#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */ - -/* - * Write backplane ip-address... - */ -int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *buf; - ulong crc; - char str[32]; - char *ptr; - IPaddr_t ipaddr; - - buf = malloc(CONFIG_ENV_SIZE_2); - if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, - (uchar *)buf, CONFIG_ENV_SIZE_2)) - puts("\nError reading backplane EEPROM!\n"); - else { - crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); - if (crc != *(ulong *)buf) { - printf("ERROR: crc mismatch %08lx %08lx\n", - crc, *(ulong *)buf); - return -1; - } - - /* - * Find bp_ip - */ - ptr = strstr(buf+4, "bp_ip="); - if (ptr == NULL) { - printf("ERROR: bp_ip not found!\n"); - return -1; - } - ptr += 6; - ipaddr = string_to_ip(ptr); - - /* - * Update whole ip-addr - */ - sprintf(str, "%pI4", &ipaddr); - setenv("ipaddr", str); - printf("Updated ip_addr from bp_eeprom to %s!\n", str); - } - - free(buf); return 0; } -U_BOOT_CMD( - getbpip, 1, 1, do_get_bpip, - "Update IP-Address with Backplane IP-Address", - "" -); - -/* - * Set and print backplane ip... - */ -int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *buf; - char str[32]; - ulong crc; - - if (argc < 2) { - puts("ERROR!\n"); - return -1; - } - - printf("Setting bp_ip to %s\n", argv[1]); - buf = malloc(CONFIG_ENV_SIZE_2); - memset(buf, 0, CONFIG_ENV_SIZE_2); - sprintf(str, "bp_ip=%s", argv[1]); - strcpy(buf+4, str); - crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); - *(ulong *)buf = crc; - - if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, - 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) - puts("\nError writing backplane EEPROM!\n"); - - free(buf); - - return 0; -} -U_BOOT_CMD( - setbpip, 2, 1, do_set_bpip, - "Write Backplane IP-Address", - "" -); - -#endif /* CONFIG_CPCI405AB */ +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/cpci405/fpgadata_cpci405.c b/board/esd/cpci405/fpgadata_cpci405.c deleted file mode 100644 index 46c2feda73..0000000000 --- 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-0x8c, 0x5b, 0xcb, 0xc0, 0xd7, 0xb2, 0xb5, 0x84, -0xad, 0x45, 0x8d, 0x46, 0xaf, 0xf2, 0x27, 0xdf, -0xe7, 0x4f, 0xf1, 0x75, 0x7f, 0xca, 0x73, 0x86, -0x0c, 0x71, 0xbe, 0xc8, 0xe7, 0xab, 0xb5, 0xfc, -0xff, 0xbe, 0x36, 0xff, 0xf9, 0x27, 0x04, 0xba, -0x44, 0xf8, 0xff, 0x46, 0xae, 0xff, 0x2f, 0xfe, -0xd3, 0xaf, 0x3e, 0x5f, 0x7d, 0xbe, 0xfa, 0x7c, -0xf5, 0xf9, 0xea, 0xf3, 0xd5, 0xe7, 0xab, 0xcf, -0x57, 0x9f, 0xff, 0x5f, 0x7c, 0x78, 0xbc, 0x44, -0x78, 0xbc, 0x64, 0xfc, 0x3f, 0xdd, 0x97, 0xaf, -0x3e, 0x5f, 0x7d, 0xbe, 0xfa, 0x7c, 0xf5, 0xf9, -0xea, 0xf3, 0xd5, 0xe7, 0xab, 0xcf, 0x57, 0x9f, -0xff, 0xbb, 0x3f, 0x21, 0x2e, 0x0c, 0x7b, 0xa3, -0x36, 0x04, 0xbc, 0xa8, 0x2b, 0x87, 0xc0, 0xc8, -0xfb, 0xd3, 0xfe, 0x1d, 0x6f, 0xef, 0x0a, 0x41, -0x42, 0xca, 0xdc, 0xa7, 0xe7, 0x1f, 0x27, 0xf6, -0xf5, 0xff, 0x02, 0xd6, 0x2c, 0x67, 0x26, 0xbd, -0xa4, 0x00, 0x00, diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile deleted file mode 100644 index 80eb23d6f4..0000000000 --- a/board/esd/cpci5200/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -# ifneq ($(OBJTREE),$(SRCTREE)) -# $(shell mkdir -p $(obj)../common/xilinx_jtag) -# endif - -LIB = $(obj)lib$(BOARD).o - -# Objects for Xilinx JTAG programming (CPLD) -# CPLD = ../common/xilinx_jtag/lenval.o \ -# ../common/xilinx_jtag/micro.o \ -# ../common/xilinx_jtag/ports.o - -# COBJS = $(BOARD).o flash.o $(CPLD) -COBJS = $(BOARD).o strataflash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c deleted file mode 100644 index 8bded0bbca..0000000000 --- a/board/esd/cpci5200/cpci5200.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * cpci5200.c - main board support/init for the esd cpci5200. - */ - -#include -#include -#include -#include -#include - -#include "mt46v16m16-75.h" - -void init_ata_reset(void); - -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register: extended mode */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - - /* set tap delay */ - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); - - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(dramsize >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ - } else { -#if 0 - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ -#else - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(0x08000000 >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ -#endif - } - -#if 0 - /* find RAM size using SDRAM CS1 only */ - sdram_start(0); - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(1); - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(0); -#endif - /* set SDRAM CS1 size according to the amount of RAM found */ - - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - - init_ata_reset(); - return (dramsize); -} - -int checkboard(void) -{ - puts("Board: esd CPCI5200 (cpci5200)\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == 0x02000000) { - /* adjust mapping */ - *(vu_long *) MPC5XXX_BOOTCS_START = - *(vu_long *) MPC5XXX_CS0_START = - START_REG(CONFIG_SYS_BOOTCS_START | size); - *(vu_long *) MPC5XXX_BOOTCS_STOP = - *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) { - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -void init_ide_reset(void) -{ - debug("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -} - -void ide_set_reset(int idereset) -{ - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -} -#endif - -#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) -#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) - -#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) -#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) -#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) -#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) - -#define GPIO_WU6 0x40000000UL -#define GPIO_USB0 0x00010000UL -#define GPIO_USB9 0x08000000UL -#define GPIO_USB9S 0x00080000UL - -void init_ata_reset(void) -{ - debug("init_ata_reset\n"); - - /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; - __asm__ volatile ("sync"); - - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; - __asm__ volatile ("sync"); - } -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int addr; - unsigned int size; - int i; - volatile unsigned long *ptr; - - addr = simple_strtol(argv[1], NULL, 16); - size = simple_strtol(argv[2], NULL, 16); - - printf("\nWriting at addr %08x, size %08x.\n", addr, size); - - while (1) { - ptr = (volatile unsigned long *)addr; - for (i = 0; i < (size >> 2); i++) { - *ptr++ = i; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - putc('.'); - } - return 0; -} - -U_BOOT_CMD(writepci, 3, 1, do_writepci, - "Write some data to pcibus", - " \n" - "" -); diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h deleted file mode 100644 index 63a403231d..0000000000 --- a/board/esd/cpci5200/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x705f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c deleted file mode 100644 index 4983112a87..0000000000 --- a/board/esd/cpci5200/strataflash.c +++ /dev/null @@ -1,786 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char *cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size(ulong base, int banknum); -static int flash_write_cfiword(flash_info_t * info, ulong dest, - cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, - ulong tout, char *prompt); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, - int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *) (info->start[sect] + (offset * info->portwidth))); -} - -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar *addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2 * info->portwidth) - 1] << 8) | - addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar *addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2 * info->portwidth) - 1] << 24) | - (addr[(info->portwidth) - 1] << 16) | - (addr[(4 * info->portwidth) - 1] << 8) | - addr[(3 * info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init(void) -{ - unsigned long size; - int i; - unsigned long address; - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CONFIG_SYS_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CONFIG_SYS_FLASH_INCREMENT; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf - ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, flash_info[0].size, flash_info[i].size << 20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) - for (i = 0; - flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1; - i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if (info->flash_id != FLASH_MAN_CFI) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if (flash_full_status_check - (info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf(" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3), (info->chipwidth << 3)); - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf - (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, - info->buffer_size); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n"); - printf(" %08lX%5s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if ((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for (i = 0; i < aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *) cp)); - - for (; (i < info->portwidth) && (cnt > 0); i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *) cp)); - if ((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - while (cnt >= info->portwidth) { - i = info->buffer_size > cnt ? cnt : info->buffer_size; - if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -= i; - } -#else - /* handle the aligned part */ - while (cnt >= info->portwidth) { - cword.l = 0; - for (i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if ((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i < info->portwidth; ++i, ++cp) { - flash_add_byte(info, &cword, (*(uchar *) cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t * info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if ((retcode = - flash_full_status_check(info, sector, info->erase_blk_tout, - prot ? "protect" : "unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if (prot == 0) { - int i; - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} - -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, - char *prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer(0); - while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, - info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, - ulong tout, char *prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if ((retcode == ERR_OK) - && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt, - info->start[sector]); - if (flash_isset - (info, sector, 0, - FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { - printf("Command Sequence Error.\n"); - } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) { - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} - -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c) -{ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf) -{ - int i; - uchar *cp = (uchar *) cmdbuf; - for (i = 0; i < info->portwidth; i++) - *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, - uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for (info->portwidth = FLASH_CFI_8BIT; - info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) { - for (info->chipwidth = FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, - FLASH_CMD_CFI); - if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, - 'R') - && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, - 'Y')) - return 1; - } - } - return 0; -} - -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size(ulong base, int banknum) -{ - flash_info_t *info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio = 0; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; -#if 0 - invalidate_dcache_range(base, base + 0x400); -#endif - if (flash_detect_cfi(info)) { - - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = - flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); - - sect_cnt = 0; - sector = base; - for (i = 0; i < num_erase_regions; i++) { - if (i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = - flash_read_long(info, 0, - FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = - (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) + 1; - for (j = 0; j < erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = - flash_isset(info, sect_cnt, - FLASH_OFFSET_PROTECT, - FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = - (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * - size_ratio; - info->buffer_size = - (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = - (tmp * - (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = - (tmp * - (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = - (tmp * - (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) / - 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif -#ifdef DEBUG_FLASH - printf("size=%08x sectors=%08x \n", info->size, info->sector_count); -#endif - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword) -{ - - cfiptr_t cptr; - int flag; - - cptr.cp = (uchar *)dest; - - /* Check if Flash is (sufficiently) erased */ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if (!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t * info, ulong addr) -{ - int sector; - for (sector = info->sector_count - 1; sector >= 0; sector--) { - if (addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, - int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *) dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if ((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, - FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = - flash_full_status_check(info, sector, - info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci750/64360.h b/board/esd/cpci750/64360.h deleted file mode 100644 index 92133f0baf..0000000000 --- a/board/esd/cpci750/64360.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * for cpci750 Reinhard Arlt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * main board support/init for the cpci750. - */ - -#ifndef __64360_H__ -#define __64360_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64360_H__ */ diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile deleted file mode 100644 index 0be10fe1d4..0000000000 --- a/board/esd/cpci750/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../Marvell/common) -endif - -LIB = $(obj)lib$(BOARD).o - -SOBJS = misc.o - -COBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \ - mv_eth.o mpsc.o i2c.o \ - sdram_init.o ide.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c deleted file mode 100644 index fcaf3e67c7..0000000000 --- a/board/esd/cpci750/cpci750.c +++ /dev/null @@ -1,1088 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com - * modifications for the cpci750 by reinhard.arlt@esd-electronics.com - */ - -/* - * cpci750.c - main board support/init for the esd cpci750. - */ - -#include -#include -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64360.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#ifdef CONFIG_PCI -#define MAP_PCI -#endif /* of CONFIG_PCI */ - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */ - {"PCI0DLL_1 "}, /* 30 */ - {"PCI0DLL_0 "}, /* 29 */ - {"PCI1DLL_2 "}, /* 28 */ - {"PCI1DLL_1 "}, /* 27 */ - {"PCI1DLL_0 "}, /* 26 */ - {"BbEP2En "}, /* 25 */ - {"SDRAMRdDataDel"}, /* 24 */ - {"SDRAMRdDel "}, /* 23 */ - {"SDRAMSync "}, /* 22 */ - {"SDRAMPipeSel_1"}, /* 21 */ - {"SDRAMPipeSel_0"}, /* 20 */ - {"SDRAMAddDel "}, /* 19 */ - {"SDRAMClkSel "}, /* 18 */ - {"Reserved(1!) "}, /* 17 */ - {"PCIRty "}, /* 16 */ - {"BootCSWidth_1 "}, /* 15 */ - {"BootCSWidth_0 "}, /* 14 */ - {"PCI1PadsCal "}, /* 13 */ - {"PCI0PadsCal "}, /* 12 */ - {"MultiMVId_1 "}, /* 11 */ - {"MultiMVId_0 "}, /* 10 */ - {"MultiGTEn "}, /* 09 */ - {"Int60xArb "}, /* 08 */ - {"CPUBusConfig_1"}, /* 07 */ - {"CPUBusConfig_0"}, /* 06 */ - {"DefIntSpc "}, /* 05 */ - {0 }, /* 04 */ - {"SROMAdd_1 "}, /* 03 */ - {"SROMAdd_0 "}, /* 02 */ - {"DRAMPadCal "}, /* 01 */ - {"SInitEn "}, /* 00 */ - {0 }, /* 31 */ - {0 }, /* 30 */ - {0 }, /* 29 */ - {0 }, /* 28 */ - {0 }, /* 27 */ - {0 }, /* 26 */ - {0 }, /* 25 */ - {0 }, /* 24 */ - {0 }, /* 23 */ - {0 }, /* 22 */ - {"JTAGCalBy "}, /* 21 */ - {"GB2Sel "}, /* 20 */ - {"GB1Sel "}, /* 19 */ - {"DRAMPLL_MDiv_5"}, /* 18 */ - {"DRAMPLL_MDiv_4"}, /* 17 */ - {"DRAMPLL_MDiv_3"}, /* 16 */ - {"DRAMPLL_MDiv_2"}, /* 15 */ - {"DRAMPLL_MDiv_1"}, /* 14 */ - {"DRAMPLL_MDiv_0"}, /* 13 */ - {"GB0Sel "}, /* 12 */ - {"DRAMPLLPU "}, /* 11 */ - {"DRAMPLL_HIKVCO"}, /* 10 */ - {"DRAMPLLNP "}, /* 09 */ - {"DRAMPLL_NDiv_7"}, /* 08 */ - {"DRAMPLL_NDiv_6"}, /* 07 */ - {"CPUPadCal "}, /* 06 */ - {"DRAMPLL_NDiv_5"}, /* 05 */ - {"DRAMPLL_NDiv_4"}, /* 04 */ - {"DRAMPLL_NDiv_3"}, /* 03 */ - {"DRAMPLL_NDiv_2"}, /* 02 */ - {"DRAMPLL_NDiv_1"}, /* 01 */ - {"DRAMPLL_NDiv_0"}}; /* 00 */ - -extern flash_info_t flash_info[]; - -extern int do_bootvx (cmd_tbl_t *, int, int, char *[]); - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; -int display_mem_map (void); - -/* - * Skip video initialization on slave variant. - * This function will overwrite the weak default in cfb_console.c - */ -int board_video_skip(void) -{ - return CPCI750_SLAVE_TEST; -} - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int data; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) { - data = pciReadConfigReg(stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF); - data = (data & 0x0f) | CONFIG_SYS_GT_REGS; - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, data); - } -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6436x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6436x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); - - - /* configure device timing */ - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR); - -#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CONFIG_SYS_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) { - unsigned int flash_offset; - unsigned int l; - - flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size; - for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) { - if (flash_info[3].start[l] != 0) { - flash_info[3].start[l] += flash_offset; - } - } - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[3]); - } - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, - CONFIG_SYS_BOOT_SIZE); - - display_mem_map (); - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } -#ifdef CONFIG_PCI - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } -#endif /* of CONFIG_PCI */ - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- FLASH\n"); - else if (i == 1) - printf ("\t- FLASH\n"); - else if (i == 2) - printf ("\t- FLASH\n"); - else - printf ("\t- RTC/REGS/CAN\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n", - base, size >> 20, width); - return (0); -} - -/* - * Command loadpci: wait for signal from host and boot image. - */ -int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile unsigned int *ptr; - int count = 0; - int count2 = 0; - int status = 0; - char addr[16]; - char str[] = "\\|/-"; - char *local_args[2]; - - /* - * Mark sync address - */ - ptr = 0; - ptr[0] = 0xffffffff; - ptr[1] = 0xffffffff; - puts("\nWaiting for image from pci host -"); - - /* - * Wait for host to write the start address - */ - while (*ptr == 0xffffffff) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - sprintf(addr, "%08x", *ptr); - printf("\nBooting Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - switch (ptr[1] == 0) { - case 0: - /* - * Boot image via bootm - */ - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootm (cmdtp, 0, 1, local_args); - break; - case 1: - /* - * Boot image via bootvx - */ - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootvx (cmdtp, 0, 1, local_args); - break; - } - - return status; -} - -U_BOOT_CMD( - loadpci, 1, 1, do_loadpci, - "loadpci - Wait for pci-image and boot it\n", - NULL - ); - -/* DRAM check routines copied from gw8260 */ - -#if defined (CONFIG_SYS_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaLL, - 0xccccccccccccccccLL, - 0xf0f0f0f0f0f0f0f0LL, - 0xff00ff00ff00ff00LL, - 0xffff0000ffff0000LL, - 0xffffffff00000000LL, - 0x00000000ffffffffLL, - 0x0000ffff0000ffffLL, - 0x00ff00ff00ff00ffLL, - 0x0f0f0f0f0f0f0f0fLL, - 0x3333333333333333LL, - 0x5555555555555555LL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; - const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; - const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata = 0; - int runaddress = 0; - int runwalk = 0; - -#ifdef CONFIG_SYS_DRAM_TEST_DATA - rundata = getenv_yesno("testdramdata") == 1; -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - runaddress = getenv_yesno("testdramaddress") == 1; -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - runwalk = getenv_yesno("testdramwalk") == 1; -#endif - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - } -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); -/* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */ -/* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */ - -/* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS); - - icache_disable (); - dcache_disable (); -} - -int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int reset_sample_low; - unsigned int reset_sample_high; - unsigned int l, l1, l2; - - GT_REG_READ(0x3c4, &reset_sample_low); - GT_REG_READ(0x3d4, &reset_sample_high); - printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high); - - l2 = 0; - for (l=0; l<63; l++) { - if (show_config_tab[l][0] != 0) { - printf("%14s:%1x ", show_config_tab[l], - ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01); - l2++; - if ((l2 % 4) == 0) - printf("\n"); - } else { - l1++; - } - if (l == 32) - reset_sample_low = reset_sample_high; - } - printf("\n"); - - return(0); -} - -U_BOOT_CMD( - show_config, 1, 1, do_show_config, - "Show Marvell strapping register", - "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)" -); - -int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER)); - - return 0; -} - -U_BOOT_CMD( - pldver, 1, 1, do_pldver, - "Show PLD version", - "Show PLD version)"); - -int board_eth_init(bd_t *bis) -{ - return mv6436x_eth_initialize(bis); -} diff --git a/board/esd/cpci750/eth.h b/board/esd/cpci750/eth.h deleted file mode 100644 index 4e427683b4..0000000000 --- a/board/esd/cpci750/eth.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64360_ETH_H__ -#define __EVB64360_ETH_H__ - -#include -#include -#include -#include - - -int db64360_eth0_poll(void); -int db64360_eth0_transmit(unsigned int s, volatile char *p); -void db64360_eth0_disable(void); -bool network_start(bd_t *bis); - -int mv6436x_eth_initialize(bd_t *); - -#endif /* __EVB64360_ETH_H__ */ diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c deleted file mode 100644 index bad0dac05d..0000000000 --- a/board/esd/cpci750/i2c.c +++ /dev/null @@ -1,475 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - * extra improvments by Brain Waite - * for cpci750 by reinhard.arlt@esd-electronics.com - */ -#include -#include -#include -#include -#include "../../Marvell/include/mv_gen_reg.h" -#include "../../Marvell/include/core.h" - -#define I2C_DELAY 100 -#undef DEBUG_I2C - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -void i2c_init (int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualN = 0, actualM = 0; - unsigned int minMargin = 0xffffffff; - unsigned int tclk = CONFIG_SYS_TCLK; - unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ - - DP (puts ("i2c_init\n")); -/* gtI2cMasterInit */ - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - power = 2 << n; /* power = 2^(n+1) */ - freq = tclk / (10 * (m + 1) * power); - if (i2cFreq > freq) - margin = i2cFreq - freq; - else - margin = freq - i2cFreq; - if (margin < minMargin) { - minMargin = margin; - actualN = n; - actualM = m; - } - } - } - - DP (puts ("setup i2c bus\n")); - - /* Setup bus */ - /* gtI2cReset */ - GT_REG_WRITE (I2C_SOFT_RESET, 0); - asm(" sync"); - GT_REG_WRITE (I2C_CONTROL, 0); - asm(" sync"); - - DP (puts ("set baudrate\n")); - - GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); - asm(" sync"); - - DP (puts ("udelay...\n")); - - udelay (I2C_DELAY); - - GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - asm(" sync"); -} - - -static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - unsigned int control; - int count = 0; - - DP (puts ("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) { - bits = 10; - } - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 2); - GT_REG_WRITE (I2C_CONTROL, control); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 5); /* generate the I2C_START_BIT */ - GT_REG_WRITE (I2C_CONTROL, control); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x01 << 3)); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - - count = 0; - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){ - if (count > 200) { -#ifdef DEBUG_I2C - printf ("Failed to set startbit: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - DP (puts ("i2c_select_device:write addr byte\n")); - - /* assert the address */ - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE (I2C_DATA, data); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, BIT3); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - if (count > 200) { -#ifdef DEBUG_I2C - printf ("Failed to write address: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - asm(" sync"); - count++; - } - - if (bits == 10) { - printf ("10 bit I2C addressing not yet implemented\n"); - return (0xff); - } - - return (0); -} - -static uchar i2c_get_data (uchar * return_data, int len) -{ - - unsigned int data, status; - int count = 0; - - DP (puts ("i2c_get_data\n")); - - while (len) { - - RESET_REG_BITS (I2C_CONTROL, BIT3); - asm(" sync"); - - /* Get and return the data */ - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - if (count > 20) { -#ifdef DEBUG_I2C - printf ("Failed to get data len status: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return 0; - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ (I2C_DATA, &data); - len--; - *return_data = (uchar) data; - return_data++; - - } - RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3); - asm(" sync"); - count = 0; - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - while ((status & 0xff) != 0x58) { - if (count > 2000) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */ - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - return (0); -} - - -static uchar i2c_write_data (unsigned int *data, int len) -{ - unsigned int status; - int count; - unsigned int temp; - unsigned int *temp_ptr = data; - - DP (puts ("i2c_write_data\n")); - - while (len) { - count = 0; - temp = (unsigned int) (*temp_ptr); - GT_REG_WRITE (I2C_DATA, temp); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } - return (0); -} - - -static uchar i2c_write_byte (unsigned char *data, int len) -{ - unsigned int status; - int count; - unsigned int temp; - unsigned char *temp_ptr = data; - - DP (puts ("i2c_write_byte\n")); - - while (len) { - count = 0; - /* Set and assert the data */ - temp = *temp_ptr; - GT_REG_WRITE (I2C_DATA, temp); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } - return (0); -} - -static uchar -i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, - int alen) -{ - uchar status; - unsigned int table[2]; - - table[1] = (offset ) & 0x0ff; /* low byte */ - table[0] = (offset >> 8) & 0x0ff; /* high byte */ - - DP (puts ("i2c_set_dev_offset\n")); - - status = i2c_select_device (dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C -22 printf ("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } -/* check the address offset length */ - if (alen == 0) - /* no address offset */ - return (0); - else if (alen == 1) { - /* 1 byte address offset */ - status = i2c_write_data (&offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else if (alen == 2) { - /* 2 bytes address offset */ - status = i2c_write_data (table, 2); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else { - /* address offset unknown or not supported */ - printf ("Address length offset %d is not supported\n", alen); - return 1; - } - return 0; /* sucessful completion */ -} - -int -i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_read\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_select_device (dev_addr, 1, 0); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to select device for data read: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_get_data (data, len); - if (status) { -#ifdef DEBUG_I2C - printf ("Data not read: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} - - -void i2c_stop (void) -{ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); - asm(" sync"); -} - - -int -i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_write\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - - status = i2c_write_byte (data, len); /* write the data */ - if (status) { -#ifdef DEBUG_I2C - printf ("Data not written: 0x%02x\n", status); -#endif - return status; - } - /* issue a stop bit */ - i2c_stop (); - return 0; -} - - -int i2c_probe (uchar chip) -{ - -#ifdef DEBUG_I2C - unsigned int i2c_status; -#endif - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_probe\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address: 0x%02x\n", status); -#endif - return (int) status; - } -#ifdef DEBUG_I2C - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status); - printf ("address %#x returned %#x\n", chip, i2c_status); -#endif - /* issue a stop bit */ - i2c_stop (); - return 0; /* successful completion */ -} diff --git a/board/esd/cpci750/i2c.h b/board/esd/cpci750/i2c.h deleted file mode 100644 index a879ea93c8..0000000000 --- a/board/esd/cpci750/i2c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - */ - -#ifndef __I2C_H__ -#define __I2C_H__ - -/* function declarations */ -uchar i2c_read(uchar, unsigned int, int, uchar*, int); - -#endif diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c deleted file mode 100644 index 5f306855ac..0000000000 --- a/board/esd/cpci750/ide.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* ide.c - ide support functions */ - - -#include -#if defined(CONFIG_CMD_IDE) -#include -#include -#include - -int cpci_hd_type; - -int ata_device(int dev) -{ - int retval; - - retval = (dev & 1) << 4; - if (cpci_hd_type == 2) - retval ^= 1 << 4; - return retval; -} - - -int ide_preinit (void) -{ - int status; - pci_dev_t devbusfn; - int l; - - status = 1; - cpci_hd_type = 0; - if (CPCI750_SLAVE_TEST != 0) - return status; - for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { - ide_bus_offset[l] = -ATA_STATUS; - } - devbusfn = pci_find_device (0x1103, 0x0004, 0); - if (devbusfn != -1) { - cpci_hd_type = 1; - } else { - devbusfn = pci_find_device (0x1095, 0x3114, 0); - if (devbusfn != -1) { - cpci_hd_type = 2; - } - } - if (devbusfn != -1) { - ulong *ide_bus_offset_ptr; - - status = 0; - - ide_bus_offset_ptr = &ide_bus_offset[0]; - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - (u32 *)ide_bus_offset_ptr); - ide_bus_offset[0] &= 0xfffffffe; - ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE; - ide_bus_offset_ptr = &ide_bus_offset[1]; - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, - (u32 *)ide_bus_offset_ptr); - ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE; - } - return status; -} - -void ide_set_reset (int flag) { - return; -} - -#endif /* of CONFIG_CMDS_IDE */ diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h deleted file mode 100644 index 084f99f717..0000000000 --- a/board/esd/cpci750/local.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * include/local.h - local configuration options, board specific - */ - -#ifndef __LOCAL_H -#define __LOCAL_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* This tells PPCBoot that the config options are compiled in */ -/* #undef ENV_IS_EMBEDDED */ -/* Don't touch this! PPCBOOT figures this out based on other - * magic. */ - -/* Uncomment and define any of the below options */ - -/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ -#define CONFIG_750FX /* The 750FX doesn't support as many things in L2CR like 750CX*/ - -/* These want string arguments */ -/* #define CONFIG_BOOTARGS */ -/* #define CONFIG_BOOTCOMMAND */ -/* #define CONFIG_RAMBOOTCOMMAND */ -/* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CONFIG_SYS_AUTOLOAD */ -/* #define CONFIG_PREBOOT */ - -/* These don't */ - -/* #define CONFIG_BOOTDELAY */ -/* #define CONFIG_BAUDRATE */ -/* #define CONFIG_LOADS_ECHO */ -/* #define CONFIG_ETHADDR */ -/* #define CONFIG_ETH2ADDR */ -/* #define CONFIG_ETH3ADDR */ -/* #define CONFIG_IPADDR */ -/* #define CONFIG_SERVERIP */ -/* #define CONFIG_ROOTPATH */ -/* #define CONFIG_GATEWAYIP */ -/* #define CONFIG_NETMASK */ -/* #define CONFIG_HOSTNAME */ -/* #define CONFIG_BOOTFILE */ -/* #define CONFIG_LOADADDR */ - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -/* #define CONFIG_ETHADDR 86:06:2d:7e:c6:53 */ -#define CONFIG_ETHADDR 64:36:00:00:00:01 - -/* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 86:06:2d:7e:c6:54 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 86:06:2d:7e:c6:55 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S deleted file mode 100644 index 233fd83bcc..0000000000 --- a/board/esd/cpci750/misc.S +++ /dev/null @@ -1,245 +0,0 @@ -#include -#include <74xx_7xx.h> -#include "version.h" - -#include -#include - -#include -#include - -#include "../../Marvell/include/mv_gen_reg.h" - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CONFIG_SYS_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CONFIG_SYS_MONITOR_LEN@h - ori r8, r8, CONFIG_SYS_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CONFIG_SYS_DFL_GT_REGS@h - ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ -/* rlwinm r7, r4, 8, 16, 31 - rlwinm r7, r4, 12, 16, 31 */ /* original */ - rlwinm r7, r4, 16, 16, 31 - /* -----------------------------------------------------*/ - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - lis r3, CONFIG_SYS_INT_SRAM_BASE@h - ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l - rlwinm r3, r3, 16, 16, 31 - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTEGRATED_SRAM_BASE_ADDR - stwbrx r3, r5, r4 - -2: lwbrx r6, r5, r4 - cmp cr0, r3, r6 - bne 2b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0_relocated -led_on0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC80 - ori r18, r18, 0x8000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_off0_relocated -led_off0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC81 - ori r18, r18, 0x4000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off0 -led_off0: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x4000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off1 -led_off1: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off2 -led_off2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c deleted file mode 100644 index a15877457d..0000000000 --- a/board/esd/cpci750/mpsc.c +++ /dev/null @@ -1,1002 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include -#include -#include - -#include -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../../Marvell/include/memory.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ - -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#else - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64360 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* true for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/esd/cpci750/mpsc.h b/board/esd/cpci750/mpsc.h deleted file mode 100644 index 241f28a31a..0000000000 --- a/board/esd/cpci750/mpsc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../../Marvell/include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c deleted file mode 100644 index 91b4063ed1..0000000000 --- a/board/esd/cpci750/mv_eth.c +++ /dev/null @@ -1,3146 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include -#include -#include - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64360_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64360_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64360_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64360_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64360 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64360_eth_real_open (struct eth_device *eth); -static int mv64360_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64360_eth_update_stat (struct eth_device *dev); -bool db64360_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64360_eth_receive (struct eth_device *dev); - -int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64360_eth_print_stat (struct eth_device *dev); -#endif - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64360_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64360_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64360_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64360_eth - * - **********************************************************************/ -int db64360_eth_probe (struct eth_device *dev) -{ - return ((int) db64360_eth_start (dev)); -} - -int db64360_eth_poll (struct eth_device *dev) -{ - return mv64360_eth_receive (dev); -} - -int db64360_eth_transmit(struct eth_device *dev, void *packet, int length) -{ - mv64360_eth_xmit (dev, packet, length); - return 0; -} - -void db64360_eth_disable (struct eth_device *dev) -{ - mv64360_eth_stop (dev); -} - - -void mv6436x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64360_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64360_eth_transmit; - dev->recv = (void *) db64360_eth_poll; - - ethernet_private = - calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *) ethernet_private; - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = - calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64360_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64360_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64360_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64360_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64360_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64360_eth_open (struct eth_device *dev) -{ - return (mv64360_eth_real_open (dev)); -} - -/* Helper function for mv64360_eth_open */ -static int mv64360_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - u32 phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64360_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64360_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64360_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64360_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64360_eth_stop (struct eth_device *dev) -{ - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64360_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64360_eth_stop */ - -static int mv64360_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64360_eth_free_tx_rings (dev); - mv64360_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64360_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64360_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - pkt_info.return_info = 0; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64360_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64360_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64360_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64360_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - - mv64360_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64360_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - (void)eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - (void)eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64360_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64360_eth_start (struct eth_device *dev) -{ - return (mv64360_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) { - (void)MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); - } - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h deleted file mode 100644 index b93cb27825..0000000000 --- a/board/esd/cpci750/mv_eth.h +++ /dev/null @@ -1,819 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64360_ETH_H__ -#define __DB64360_ETH_H__ - -#include -#include -#include -#include -#include -#include "mv_regs.h" -#include - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64360_TX_QUEUE_NUM 1 -#define MV64360_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE -#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE -#else -#define MV64360_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE -#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE -#else -#define MV64360_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64360_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64360_TX_BUFFER_SIZE 1600 -#endif - - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64360_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - - -int mv64360_eth_init (struct eth_device *dev); -int mv64360_eth_stop (struct eth_device *dev); -int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length); -int mv64360_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64360_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64360_ETH_ */ diff --git a/board/esd/cpci750/mv_regs.h b/board/esd/cpci750/mv_regs.h deleted file mode 100644 index 45274f08d9..0000000000 --- a/board/esd/cpci750/mv_regs.h +++ /dev/null @@ -1,1108 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** -* gt64360r.h - GT-64360 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64360 - -/* Supported by the Atlantis */ -#define MV64360_INCLUDE_PCI_1 -#define MV64360_INCLUDE_PCI_0_ARBITER -#define MV64360_INCLUDE_PCI_1_ARBITER -#define MV64360_INCLUDE_SNOOP_SUPPORT -#define MV64360_INCLUDE_P2P -#define MV64360_INCLUDE_ETH_PORT_2 -#define MV64360_INCLUDE_CPU_MAPPING -#define MV64360_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64360_CS_0_BASE_ADDR 0x008 -#define MV64360_CS_0_SIZE 0x010 -#define MV64360_CS_1_BASE_ADDR 0x208 -#define MV64360_CS_1_SIZE 0x210 -#define MV64360_CS_2_BASE_ADDR 0x018 -#define MV64360_CS_2_SIZE 0x020 -#define MV64360_CS_3_BASE_ADDR 0x218 -#define MV64360_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64360_PCI_0_IO_BASE_ADDR 0x048 -#define MV64360_PCI_0_IO_SIZE 0x050 -#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64360_PCI_0_MEMORY0_SIZE 0x060 -#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64360_PCI_0_MEMORY1_SIZE 0x088 -#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64360_PCI_0_MEMORY2_SIZE 0x260 -#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64360_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64360_PCI_1_IO_BASE_ADDR 0x090 -#define MV64360_PCI_1_IO_SIZE 0x098 -#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64360_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64360_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64360_CPU_CONFIG 0x000 -#define MV64360_CPU_MODE 0x120 -#define MV64360_CPU_MASTER_CONTROL 0x160 -#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64360_SMP_WHO_AM_I 0x200 -#define MV64360_SMP_CPU0_DOORBELL 0x214 -#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64360_SMP_CPU1_DOORBELL 0x224 -#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64360_SMP_SEMAPHOR0 0x244 -#define MV64360_SMP_SEMAPHOR1 0x24c -#define MV64360_SMP_SEMAPHOR2 0x254 -#define MV64360_SMP_SEMAPHOR3 0x25c -#define MV64360_SMP_SEMAPHOR4 0x264 -#define MV64360_SMP_SEMAPHOR5 0x26c -#define MV64360_SMP_SEMAPHOR6 0x274 -#define MV64360_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64360_CPU_ERROR_ADDR_LOW 0x070 -#define MV64360_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64360_CPU_ERROR_DATA_LOW 0x128 -#define MV64360_CPU_ERROR_DATA_HIGH 0x130 -#define MV64360_CPU_ERROR_PARITY 0x138 -#define MV64360_CPU_ERROR_CAUSE 0x140 -#define MV64360_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64360_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64360_SRAM_CONFIG 0x380 -#define MV64360_SRAM_TEST_MODE 0X3F4 -#define MV64360_SRAM_ERROR_CAUSE 0x388 -#define MV64360_SRAM_ERROR_ADDR 0x390 -#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64360_SRAM_ERROR_DATA_LOW 0x398 -#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64360_SDRAM_CONFIG 0x1400 -#define MV64360_D_UNIT_CONTROL_LOW 0x1404 -#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64360_SDRAM_ADDR_CONTROL 0x1410 -#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64360_SDRAM_OPERATION 0x1418 -#define MV64360_SDRAM_MODE 0x141c -#define MV64360_EXTENDED_DRAM_MODE 0x1420 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64360_SDRAM_ERROR_ADDR 0x1450 -#define MV64360_SDRAM_RECEIVED_ECC 0x1448 -#define MV64360_SDRAM_CALCULATED_ECC 0x144c -#define MV64360_SDRAM_ECC_CONTROL 0x1454 -#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64360_DFCDL_CONFIG0 0x1480 -#define MV64360_DFCDL_CONFIG1 0x1484 -#define MV64360_DLL_WRITE 0x1488 -#define MV64360_DLL_READ 0x148c -#define MV64360_SRAM_ADDR 0x1490 -#define MV64360_SRAM_DATA0 0x1494 -#define MV64360_SRAM_DATA1 0x1498 -#define MV64360_SRAM_DATA2 0x149c -#define MV64360_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64360_DUNIT_DEBUG_LOW 0x1460 -#define MV64360_DUNIT_DEBUG_HIGH 0x1464 -#define MV64360_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64360_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64360_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64360_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64360_DEVICE_ERROR_ADDR 0x4d8 -#define MV64360_DEVICE_ERROR_DATA 0x4dc -#define MV64360_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64360_DEVICE_DEBUG_LOW 0x4e4 -#define MV64360_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64360_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64360_PCI_0_COMMAND 0xc00 -#define MV64360_PCI_1_COMMAND 0xc80 -#define MV64360_PCI_0_MODE 0xd00 -#define MV64360_PCI_1_MODE 0xd80 -#define MV64360_PCI_0_RETRY 0xc04 -#define MV64360_PCI_1_RETRY 0xc84 -#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64360_PCI_0_P2P_CONFIG 0x1d14 -#define MV64360_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64360_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64360_PCI_1_CONFIG_ADDR 0xc78 -#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64360_PCI_0_SERR_MASK 0xc28 -#define MV64360_PCI_1_SERR_MASK 0xca8 -#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64360_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64360_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64360_PCI_0_ERROR_MASK 0x1d5c -#define MV64360_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64360_PCI_0_MMASK 0X1D24 -#define MV64360_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64360_PCI_STATUS_AND_COMMAND 0x004 -#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64360_PCI_VPD_ADDR 0x048 -#define MV64360_PCI_VPD_DATA 0x04c -#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64360_PCI_X_COMMAND 0x060 -#define MV64360_PCI_X_STATUS 0x064 -#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64360_ETH_PHY_ADDR_REG 0x2000 -#define MV64360_ETH_SMI_REG 0x2004 -#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64360_ETH_BAR_0 0x2200 -#define MV64360_ETH_BAR_1 0x2208 -#define MV64360_ETH_BAR_2 0x2210 -#define MV64360_ETH_BAR_3 0x2218 -#define MV64360_ETH_BAR_4 0x2220 -#define MV64360_ETH_BAR_5 0x2228 -#define MV64360_ETH_SIZE_REG_0 0x2204 -#define MV64360_ETH_SIZE_REG_1 0x220c -#define MV64360_ETH_SIZE_REG_2 0x2214 -#define MV64360_ETH_SIZE_REG_3 0x221c -#define MV64360_ETH_SIZE_REG_4 0x2224 -#define MV64360_ETH_SIZE_REG_5 0x222c -#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64360_CUNIT_SIZE0 0xf204 -#define MV64360_CUNIT_SIZE1 0xf20c -#define MV64360_CUNIT_SIZE2 0xf214 -#define MV64360_CUNIT_SIZE3 0xf21c -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64360_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64360_CUNIT_CONFIG_REG 0xb40c -#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64360_CUNIT_DEBUG_LOW 0xf340 -#define MV64360_CUNIT_DEBUG_HIGH 0xf344 -#define MV64360_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64360_MPSC_ROUTING_REG 0xb400 -#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64360_SDMA_CAUSE_REG 0xb800 -#define MV64360_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64360_SDMA_SRAM_TARGET 0x0003 -#define MV64360_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64360_PCI_0_TARGET 0x0003 -#define MV64360_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64360_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64360_BRG_CAUSE_REG 0xb834 -#define MV64360_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_CONTROL 0x840 -#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64360_DMA_CHANNEL1_CONTROL 0x844 -#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64360_DMA_CHANNEL2_CONTROL 0x848 -#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64360_DMA_CHANNEL3_CONTROL 0x84C -#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64360_DMA_BASE_ADDR_REG0 0xa00 -#define MV64360_DMA_BASE_ADDR_REG1 0xa08 -#define MV64360_DMA_BASE_ADDR_REG2 0xa10 -#define MV64360_DMA_BASE_ADDR_REG3 0xa18 -#define MV64360_DMA_BASE_ADDR_REG4 0xa20 -#define MV64360_DMA_BASE_ADDR_REG5 0xa28 -#define MV64360_DMA_BASE_ADDR_REG6 0xa30 -#define MV64360_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64360_DMA_SIZE_REG0 0xa04 -#define MV64360_DMA_SIZE_REG1 0xa0c -#define MV64360_DMA_SIZE_REG2 0xa14 -#define MV64360_DMA_SIZE_REG3 0xa1c -#define MV64360_DMA_SIZE_REG4 0xa24 -#define MV64360_DMA_SIZE_REG5 0xa2c -#define MV64360_DMA_SIZE_REG6 0xa34 -#define MV64360_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64360_DMA_ARBITER_CONTROL 0x860 -#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64360_DMA_ERROR_ADDR 0x8c8 -#define MV64360_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64360_DMA_DEBUG_LOW 0x8e0 -#define MV64360_DMA_DEBUG_HIGH 0x8e4 -#define MV64360_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64360_TIMER_COUNTER0 0x850 -#define MV64360_TIMER_COUNTER1 0x854 -#define MV64360_TIMER_COUNTER2 0x858 -#define MV64360_TIMER_COUNTER3 0x85C -#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64360_WATCHDOG_CONFIG_REG 0xb410 -#define MV64360_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64360_I2C_SLAVE_ADDR 0xc000 -#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64360_I2C_DATA 0xc004 -#define MV64360_I2C_CONTROL 0xc008 -#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64360_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64360_GPP_IO_CONTROL 0xf100 -#define MV64360_GPP_LEVEL_CONTROL 0xf110 -#define MV64360_GPP_VALUE 0xf104 -#define MV64360_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64360_GPP_INTERRUPT_MASK0 0xf10c -#define MV64360_GPP_INTERRUPT_MASK1 0xf114 -#define MV64360_GPP_VALUE_SET 0xf118 -#define MV64360_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64360_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64360_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64360_MPP_CONTROL0 0xf000 -#define MV64360_MPP_CONTROL1 0xf004 -#define MV64360_MPP_CONTROL2 0xf008 -#define MV64360_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64360_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64360_SERIAL_INIT_CONTROL 0xf328 -#define MV64360_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64360rh */ diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c deleted file mode 100644 index c9b3ac2a4f..0000000000 --- a/board/esd/cpci750/pci.c +++ /dev/null @@ -1,1028 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PCI.c - PCI functions */ - - -#include -#ifdef CONFIG_PCI -#include - -#include "../../Marvell/include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - -#ifdef CONFIG_USE_CPCIDVI -typedef struct { - unsigned int base; - unsigned int init; -} GT_CPCIDVI_ROM_T; - -static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; -#endif - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 MHz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 MHz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 MHz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, - offset | (PCI_FUNC(dev) << 8), - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr, - offset | (PCI_FUNC(dev) << 8), - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset | (PCI_FUNC(dev) << 8), - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset | (PCI_FUNC(dev) << 8), - PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - if (CPCI750_SLAVE_TEST != 0) - return; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - -#ifdef CONFIG_USE_CPCIDVI -static void gt_setup_cpcidvi (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - u32 bar_value, pci_response; - - if (CPCI750_SLAVE_TEST != 0) - return; - - pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); - pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); - pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value); - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00)); - pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0); - pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value); - pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01); - gt_cpcidvi_rom.base = bar_value & 0xffffff00; - gt_cpcidvi_rom.init = 1; -} - -unsigned char gt_cpcidvi_in8(unsigned int offset) -{ - unsigned char data; - - if (gt_cpcidvi_rom.init == 0) { - return(0); - } - data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); - return(data); -} - -void gt_cpcidvi_out8(unsigned int offset, unsigned char data) -{ - unsigned int off; - - if (gt_cpcidvi_rom.init == 0) { - return; - } - off = data; - off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; - in8(off); - return; -} -#endif - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { -#ifdef CONFIG_USE_CPCIDVI - {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi}, -#endif - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - unsigned int slave; -#ifdef CONFIG_PCI_PNP - unsigned int bar; -#endif -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif -#ifdef CONFIG_USE_CPCIDVI - gt_cpcidvi_rom.init = 0; - gt_cpcidvi_rom.base = 0; -#endif - - slave = CPCI750_SLAVE_TEST; - - pci0_hose.config_table = gt_config_table; - pci1_hose.config_table = gt_config_table; - -#ifdef CONFIG_USE_CPCIDVI - gt_config_table[0].config_device = gt_setup_cpcidvi; -#endif - gt_config_table[1].config_device = gt_setup_ide; - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - if (slave == 0) { - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci0_hose); - pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); -#endif -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, - pci0_hose.first_busno); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - } else { - pciArbiterDisable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - pci0_hose.last_busno = pci0_hose.first_busno; - } - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci1_hose); - pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar); -#endif - pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} -#endif /* of CONFIG_PCI */ diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c deleted file mode 100644 index 89f94aa6aa..0000000000 --- a/board/esd/cpci750/sdram_init.c +++ /dev/null @@ -1,1702 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * adaption for the Marvell DB64360 Board - * Ingo Assmus (ingo.assmus@keymile.com) - * - * adaption for the cpci750 Board - * Reinhard Arlt (reinhard.arlt@esd-electronics.com) - *************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "../../Marvell/common/i2c.h" -#include "64360.h" -#include "mv_regs.h" - -DECLARE_GLOBAL_DATA_PTR; - -int set_dfcdlInit(void); /* setup delay line of Mv64360 */ - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank(unsigned int bankNo, - unsigned int bankBase, - unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - -#ifdef DEBUG - if (bankLength > 0) { - printf("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank(bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host=PCI_HOST0;host<=PCI_HOST1;host++) { - const int features= - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | - PCI_NO_SWAP; - - pciMapMemoryBank(host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE; - -typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, - } VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short -NS10to10PS(unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return(ns*100 + ns10*10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short -NSto10PS(unsigned char spd_byte) -{ - return(spd_byte*100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, tras_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - memset (data, 0, sizeof (data)); - - - ret = 0; - - debug("before i2c read\n"); - - ret = i2c_read (addr, 0, 2, data, 128); - - debug("after i2c read\n"); - - if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd') - || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm') - || (data[70] != 'b') || (data[71] != 'h')) { - ret = -1; - } - - if ((ret != 0) && (slot == 0)) { - memset (data, 0, sizeof (data)); - data[0] = 0x80; - data[1] = 0x08; - data[2] = 0x07; - data[3] = 0x0c; - data[4] = 0x09; - data[5] = 0x01; - data[6] = 0x48; - data[7] = 0x00; - data[8] = 0x04; - data[9] = 0x75; - data[10] = 0x80; - data[11] = 0x02; - data[12] = 0x80; - data[13] = 0x10; - data[14] = 0x08; - data[15] = 0x01; - data[16] = 0x0e; - data[17] = 0x04; - data[18] = 0x0c; - data[19] = 0x01; - data[20] = 0x02; - data[21] = 0x20; - data[22] = 0x00; - data[23] = 0xa0; - data[24] = 0x80; - data[25] = 0x00; - data[26] = 0x00; - data[27] = 0x50; - data[28] = 0x3c; - data[29] = 0x50; - data[30] = 0x32; - data[31] = 0x10; - data[32] = 0xb0; - data[33] = 0xb0; - data[34] = 0x60; - data[35] = 0x60; - data[64] = 'e'; - data[65] = 's'; - data[66] = 'd'; - data[67] = '-'; - data[68] = 'g'; - data[69] = 'm'; - data[70] = 'b'; - data[71] = 'h'; - ret = 0; - } - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - debug("No DIMM in slot %d [err = %x]\n", slot, ret); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG - /* find Manufacturer of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - - /* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - - /* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - - /* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - - /* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - - /* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - - /* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ -#if 0 /* test-only */ - spd_checksum = 0; - - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); -#endif /* test-only */ - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG - if (dimmInfo->memoryType == 0) - debug("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot); - if (dimmInfo->memoryType == 1) - debug("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - debug("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - debug("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - debug("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - debug("Module Data Width: %d\n", - dimmInfo->dataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - debug("Module is TTL_5V_TOLERANT\n"); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - debug("Module is LVTTL\n"); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - debug("Module is TTL_5V_TOLERANT\n"); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - debug("Module is HSTL_1_5V\n"); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - debug("Module is SSTL_2_5V\n"); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - debug("Module is VOLTAGE_UNKNOWN\n"); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - debug("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - debug("Clock To Data Out: %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -#ifdef CONFIG_MV64360_ECC - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - debug("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType); - break; -#endif /* of ifdef CONFIG_MV64360_ECC */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - debug("Sdram Width: %d\n", - dimmInfo->sdramWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - debug("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - debug("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - debug("Burst Length Supported: "); - if (dimmInfo->burstLengthSupported & 0x01) - debug("1, "); - if (dimmInfo->burstLengthSupported & 0x02) - debug("2, "); - if (dimmInfo->burstLengthSupported & 0x04) - debug("4, "); - if (dimmInfo->burstLengthSupported & 0x08) - debug("8, "); - debug(" Bit \n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - debug("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - debug("Suported Cas Latencies: (CL) "); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - debug("%d, ", - k + 1); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - debug("1, "); - if (dimmInfo->suportedCasLatencies & 2) - debug("1.5, "); - if (dimmInfo->suportedCasLatencies & 4) - debug("2, "); - if (dimmInfo->suportedCasLatencies & 8) - debug("2.5, "); - if (dimmInfo->suportedCasLatencies & 16) - debug("3, "); - if (dimmInfo->suportedCasLatencies & 32) - debug("3.5, "); - - } - debug("\n"); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - debug("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - debug("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - debug("Max. Cas Latencies (DDR): 3.5 clk's\n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - debug("Max. Cas Latencies (DDR): 3 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - debug("Max. Cas Latencies (DDR): 2.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - debug("Max. Cas Latencies (DDR): 2 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - debug("Max. Cas Latencies (DDR): 1.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - debug("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - debug("\nModul Attributes (SPD Byte 21): \n"); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; - - if (dimmInfo->bufferedAddrAndControlInputs == 1) - debug(" - Buffered Address/Control Input: Yes \n"); - else - debug(" - Buffered Address/Control Input: No \n"); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - debug(" - Registered Address/Control Input: Yes \n"); - else - debug(" - Registered Address/Control Input: No \n"); - - if (dimmInfo->onCardPLL == 1) - debug(" - On-Card PLL (clock): Yes \n"); - else - debug(" - On-Card PLL (clock): No \n"); - - if (dimmInfo->bufferedDQMBinputs == 1) - debug(" - Bufferd DQMB Inputs: Yes \n"); - else - debug(" - Bufferd DQMB Inputs: No \n"); - - if (dimmInfo->registeredDQMBinputs == 1) - debug(" - Registered DQMB Inputs: Yes \n"); - else - debug(" - Registered DQMB Inputs: No \n"); - - if (dimmInfo->differentialClockInput == 1) - debug(" - Differential Clock Input: Yes \n"); - else - debug(" - Differential Clock Input: No \n"); - - if (dimmInfo->redundantRowAddressing == 1) - debug(" - redundant Row Addressing: Yes \n"); - else - debug(" - redundant Row Addressing: No \n"); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - debug("\nModul Attributes (SPD Byte 22): \n"); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; - - if (dimmInfo->suportedEarlyRasPreCharge == 1) - debug(" - Early Ras Precharge: Yes \n"); - else - debug(" - Early Ras Precharge: No \n"); - - if (dimmInfo->suportedAutoPreCharge == 1) - debug(" - AutoPreCharge: Yes \n"); - else - debug(" - AutoPreCharge: No \n"); - - if (dimmInfo->suportedPreChargeAll == 1) - debug(" - Precharge All: Yes \n"); - else - debug(" - Precharge All: No \n"); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - debug(" - Write 1/ReadBurst: Yes \n"); - else - debug(" - Write 1/ReadBurst: No \n"); - - if (dimmInfo->suported5PercentLowVCC == 1) - debug(" - lower VCC tolerance: 5 Percent \n"); - else - debug(" - lower VCC tolerance: 10 Percent \n"); - - if (dimmInfo->suported5PercentUpperVCC == 1) - debug(" - upper VCC tolerance: 5 Percent \n"); - else - debug(" - upper VCC tolerance: 10 Percent \n"); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - debug("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - debug("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - debug("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100); - debug("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - debug("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - debug("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity); -#ifdef DEBUG - debug("*** Offered Densities (more than 1 = Multisize-Module): "); - { - if (dimmInfo->moduleBankDensity & 1) - debug("4MB, "); - if (dimmInfo->moduleBankDensity & 2) - debug("8MB, "); - if (dimmInfo->moduleBankDensity & 4) - debug("16MB, "); - if (dimmInfo->moduleBankDensity & 8) - debug("32MB, "); - if (dimmInfo->moduleBankDensity & 16) - debug("64MB, "); - if (dimmInfo->moduleBankDensity & 32) - debug("128MB, "); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - debug("ERROR, "); - hang (); - } - } - debug("\n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - devicesForErrCheck); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1; - - cal_val = 0; - if (supp_cal & 8) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 6; - } - if (supp_cal & 4) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 5; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 4; - } - - debug("cal_val = %d\n", cal_val * 5); - - /* bummer, did't work... */ - if (cal_val == 0) { - debug("Couldn't find a good CAS latency\n"); - hang (); - return 0; - } - - return true; -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG; - int i; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - - /* Program the GT with the discovered data */ - if (info->registeredAddrAndControlInputs == true) - debug("Module is registered, but we do not support registered Modules !!!\n"); - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - debug("Delay line set done\n"); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); - } - -#ifdef CONFIG_MV64360_ECC - if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) { - /* DRAM has ECC, so turn it on */ - sdram_config_reg |= BIT18; - debug("Enabling ECC\n"); - } -#endif /* of ifdef CONFIG_MV64360_ECC */ - - /* SDRAM configuration */ - GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg); - debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM open pages controll keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - debug("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); - - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - debug("Core Signals are sync (by HW-Setting)!!!\n"); - else - debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); - - /* SDRAM set CAS Lentency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - debug("### SD-RAM not supported yet !!!\n"); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - - case DDR: - debug("### SET-CL for DDR-RAM\n"); - - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - break; - - case DDR_CL_2_5: - if (tmp == 1) { /* clocks sync */ - tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - case DDR_CL_2: - if (tmp == 1) { /* Sync */ - tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* Not sync. */ - - tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - case DDR_CL_1_5: - if (tmp == 1) { /* Sync */ - tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* not sync */ - - tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } - break; - } - - /* Write results of CL detection procedure */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp != 1) { /*clocks are not sync */ - /* asyncmode */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, - (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) | - 0x18110780 | tmp_dunit_control_low); - } else { - /* syncmode */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, - (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) | - 0x00110000 | tmp_dunit_control_low); - } - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); - } - -/*------------------------------------------------------------------------------ */ - - - /* bank parameters */ - /* SDRAM address decode register */ - /* program this with the default value */ - tmp = 0x02; - - - debug("drb_size (n*64Mbit): %d\n", info->drb_size); - switch (info->drb_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - debug("RAM-Device_size 64Mbit or 128Mbit)\n"); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - debug("RAM-Device_size 256Mbit or 512Mbit)\n"); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - debug("RAM-Device_size 1Gbit or 2Gbit)\n"); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"); - tmp |= (0x02 << 4); - return 1; - } - - /* SDRAM bank parameters */ - /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ - debug("setting up slot %d config with: %08lx \n", info->slot, tmp); - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - -/* ------------------------------------------------------------------------------ */ - - debug("setting up sdram_timing_control_low with: %08x \n", - 0x11511220); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV64360 */ - tmp |= (1 << 26); - debug("Before Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG)); - debug("After Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM timing To_do: */ - - - tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH); - debug("# sdram_timing_control_high is : %08lx \n", tmp); - - /* SDRAM address decode register */ - /* program this with the default value */ - tmp = GTREGREAD (SDRAM_ADDR_CONTROL); - debug("SDRAM address control (before: decode): %08x ", - GTREGREAD (SDRAM_ADDR_CONTROL)); - GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2)); - debug("SDRAM address control (after: decode): %08x\n", - GTREGREAD (SDRAM_ADDR_CONTROL)); - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - int l, l1; - - i = info->slot; - debug("\n*** Running a MRS cycle for bank %d ***\n", i); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); -#if 1 /* test only */ - - tmp = GTREGREAD (SDRAM_MODE); - GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0); - GT_REG_WRITE (SDRAM_OPERATION, 0x4); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - GT_REG_WRITE (SDRAM_MODE, tmp | 0x80); - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - l1 = 0; - for (l=0;l<200;l++) - l1 += GTREGREAD (SDRAM_OPERATION); - - GT_REG_WRITE (SDRAM_MODE, tmp); - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - -#endif /* test only */ - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int -dram_size(long int *base, long int maxsize) -{ - volatile long int *addr, *b=base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr=cnt; /* write cnt to addr */ - *b=0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr=save1; /* restore *addr */ - *b=save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr=save1; - *b=save2; - - if (val != cnt) { - debug("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr); - /* fix boundary condition.. STARTVAL means zero */ - if(cnt==STARTVAL/sizeof(long)) cnt=0; - return (cnt * sizeof(long)); - } - } - return maxsize; -} - -#ifdef CONFIG_MV64360_ECC -/* - * mv_dma_is_channel_active: - * Checks if a engine is busy. - */ -int mv_dma_is_channel_active(int engine) -{ - ulong data; - - data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); - if (data & BIT14) /* activity status */ - return 1; - - return 0; -} - -/* - * mv_dma_set_memory_space: - * Set a DMA memory window for the DMA's address decoding map. - */ -int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target, - ulong mem_space_attr, ulong base_address, - ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (base_address % size != 0) - return 0; - - if (size >= 0x10000) { - size &= 0xffff0000; - base_address = (base_address & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8, - (base_address | mem_space_target | - mem_space_attr)); - GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << mem_space))); - return 1; - } - - return 0; -} - - -/* - * mv_dma_transfer: - * Transfer data from source_addr to dest_addr on one of the 4 DMA channels. - */ -int mv_dma_transfer(int engine, ulong source_addr, - ulong dest_addr, ulong bytes, ulong command) -{ - ulong eng_off_reg; /* Engine Offset Register */ - - if (bytes > 0xffff) - command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */ - - command = command | ((command >> 6) & 0x7); - eng_off_reg = engine * 4; - GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg, - bytes); - GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg, - source_addr); - GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg, - dest_addr); - command |= BIT12 /* DMA_CHANNEL_ENABLE */ - | BIT9; /* DMA_NON_CHAIN_MODE */ - - /* Activate DMA engine By writting to mv_dma_control_register */ - GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command); - - return 1; -} -#endif /* of ifdef CONFIG_MV64360_ECC */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -phys_size_t -initdram(int board_type) -{ - int checkbank[4] = { [0 ... 3] = 0 }; - ulong realsize, total, check; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int bank_no, nhr; -#ifdef CONFIG_MV64360_ECC - ulong dest, mem_space_attr; -#endif /* of ifdef CONFIG_MV64360_ECC */ - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0() & (1 << 16); - - if (nhr) { - printf("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - (void)check_dimm(0, &dimmInfo1); - - /* DIMM1 */ - (void)check_dimm(1, &dimmInfo2); - - memory_map_bank(0, 0, 0); - memory_map_bank(1, 0, 0); - memory_map_bank(2, 0, 0); - memory_map_bank(3, 0, 0); - - if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) { - printf("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) { - printf("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0(get_hid0() | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - check = GB/4; - if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");} - if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");} - if (dimmInfo1.numOfModuleBanks > 2) - printf("Error, SPD claims DIMM1 has >2 banks\n"); - - if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");} - if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");} - if (dimmInfo2.numOfModuleBanks > 2) - printf("Error, SPD claims DIMM2 has >2 banks\n"); - - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (! checkbank[bank_no]) - continue; - - if ((total + check) > CONFIG_SYS_GT_REGS) - check = CONFIG_SYS_GT_REGS - total; - - memory_map_bank(bank_no, total, check); - realsize = dram_size((long int *)total, check); - memory_map_bank(bank_no, total, realsize); - -#ifdef CONFIG_MV64360_ECC - if (((dimmInfo1.errorCheckType != 0) && - ((dimmInfo2.errorCheckType != 0) || - (dimmInfo2.numOfModuleBanks == 0))) && - (CPCI750_ECC_TEST)) { - printf("ECC Initialization of Bank %d:", bank_no); - mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8; - mv_dma_set_memory_space(0, 0, mem_space_attr, total, - realsize); - for (dest = total; dest < total + realsize; - dest += _8M) { - mv_dma_transfer(0, total, dest, _8M, - BIT8 | /* DMA_DTL_128BYTES */ - BIT3 | /* DMA_HOLD_SOURCE_ADDR */ - BIT11); /* DMA_BLOCK_TRANSFER_MODE */ - while (mv_dma_is_channel_active(0)) - ; - } - printf(" PASS\n"); - } -#endif /* of ifdef CONFIG_MV64360_ECC */ - - total += realsize; - } - -/* Setup Ethernet DMA Adress window to DRAM Area */ - return(total); -} - -/* *************************************************************************************** -! * SDRAM INIT * -! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * -! * This procedure fits only the Atlantis * -! * * -! *************************************************************************************** */ - - -/* *************************************************************************************** -! * DFCDL initialize MV643xx Design Considerations * -! * * -! *************************************************************************************** */ -int set_dfcdlInit (void) -{ - int i; - unsigned int dfcdl_word = 0x0000014f; - - for (i = 0; i < 64; i++) { - GT_REG_WRITE (SRAM_DATA0, dfcdl_word); - } - GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ - - - return (0); -} - -int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int ecc_counter; - unsigned int ecc_addr; - - GT_REG_READ(0x1458, &ecc_counter); - GT_REG_READ(0x1450, &ecc_addr); - GT_REG_WRITE(0x1450, 0); - - printf("Error Counter since Reset: %8d\n", ecc_counter); - printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8); - if (ecc_addr & 0x01) - printf("double"); - else - printf("single"); - printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1)); - - return 0; -} - - -U_BOOT_CMD( - show_ecc, 1, 1, do_show_ecc, - "Show Marvell MV64360 ECC Info", - "Show Marvell MV64360 ECC Counter and last error." -); diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c deleted file mode 100644 index f42510545c..0000000000 --- a/board/esd/cpci750/serial.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * modified for cpci750 board by - * Reinhard Arlt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * serial.c - serial support for esd cpci750 board - */ - -/* supports the MPSC */ - -#include -#include -#include -#include - -#include "../../Marvell/include/memory.h" -#include "serial.h" - -#include "mpsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -static int cpci750_serial_init(void) -{ - mpsc_init (gd->baudrate); - - return (0); -} - -static void cpci750_serial_putc(const char c) -{ - if (c == '\n') - mpsc_putchar ('\r'); - - mpsc_putchar (c); -} - -static int cpci750_serial_getc(void) -{ - return mpsc_getchar (); -} - -static int cpci750_serial_tstc(void) -{ - return mpsc_test_char (); -} - -static void cpci750_serial_setbrg(void) -{ - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); -} - -static struct serial_device cpci750_serial_drv = { - .name = "cpci750_serial", - .start = cpci750_serial_init, - .stop = NULL, - .setbrg = cpci750_serial_setbrg, - .putc = cpci750_serial_putc, - .puts = default_serial_puts, - .getc = cpci750_serial_getc, - .tstc = cpci750_serial_tstc, -}; - -void cpci750_serial_initialize(void) -{ - serial_register(&cpci750_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &cpci750_serial_drv; -} - -#if defined(CONFIG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/esd/cpci750/serial.h b/board/esd/cpci750/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/esd/cpci750/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile deleted file mode 100644 index e5caf2331a..0000000000 --- a/board/esd/cpciiser4/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ../common/misc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c deleted file mode 100644 index e61cd5b1b3..0000000000 --- a/board/esd/cpciiser4/cpciiser4.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2000 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include "cpciiser4.h" -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -#if 0 -#define FPGA_DEBUG2 -#endif - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - int index, len, i; - int status; - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - - /* - * Init FPGA via RESET (read access on CS3) - */ - in_8((void *)0xf0200000); - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - /* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */ - mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming AR405"); - } else { - puts(str); - } - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} diff --git a/board/esd/cpciiser4/cpciiser4.h b/board/esd/cpciiser4/cpciiser4.h deleted file mode 100644 index 75e7950bcd..0000000000 --- a/board/esd/cpciiser4/cpciiser4.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c deleted file mode 100644 index 34bdc053fc..0000000000 --- a/board/esd/cpciiser4/flash.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include - -#define OK 0 -#define ERROR (-1) - -extern u_long pci9054_iobase; - - -/*************************************************************************** - * - * Routines for PLX PCI9054 eeprom access - * - */ - -static unsigned int PciEepromReadLongVPD (int offs) -{ - unsigned int value; - unsigned int ret; - int count; - - pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, - (offs << 16) | 0x0003); - count = 0; - - for (;;) { - udelay (10 * 1000); - pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); - if ((ret & 0x80000000) != 0) { - break; - } else { - count++; - if (count > 10) { - printf ("\nTimeout: ret=%08x - Please try again!\n", ret); - break; - } - } - } - - pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value); - - return value; -} - - -static int PciEepromWriteLongVPD (int offs, unsigned int value) -{ - unsigned int ret; - int count; - - pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value); - pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, - (offs << 16) | 0x80000003); - count = 0; - - for (;;) { - udelay (10 * 1000); - pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); - if ((ret & 0x80000000) == 0) { - break; - } else { - count++; - if (count > 10) { - printf ("\nTimeout: ret=%08x - Please try again!\n", ret); - break; - } - } - } - - return true; -} - - -static void showPci9054 (void) -{ - int val; - int l, i; - - /* read 9054-values */ - for (l = 0; l < 6; l++) { - printf ("%02x: ", l * 0x10); - for (i = 0; i < 4; i++) { - pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, - l * 16 + i * 4, - (unsigned int *)&val); - printf ("%08x ", val); - } - printf ("\n"); - } - printf ("\n"); - - for (l = 0; l < 7; l++) { - printf ("%02x: ", l * 0x10); - for (i = 0; i < 4; i++) - printf ("%08x ", - PciEepromReadLongVPD ((i + l * 4) * 4)); - printf ("\n"); - } - printf ("\n"); -} - - -static void updatePci9054 (void) -{ - /* - * Set EEPROM write-protect register to 0 - */ - out_be32 ((void *)(pci9054_iobase + 0x0c), - in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); - - /* Long Serial EEPROM Load Registers... */ - PciEepromWriteLongVPD (0x00, 0x905410b5); - PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ - PciEepromWriteLongVPD (0x08, 0x28140100); - - PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ - PciEepromWriteLongVPD (0x10, 0x00000000); - - /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */ - PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ - PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ - - PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ - PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ - - PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ - PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ - - PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ - - PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ - PciEepromWriteLongVPD (0x34, 0x00000000); - PciEepromWriteLongVPD (0x38, 0x00000000); - - PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ - PciEepromWriteLongVPD (0x40, 0x00000000); - - /* Extra Long Serial EEPROM Load Registers... */ - PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ - - /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */ - /* Offset to LAS1: Group 1: 0x00040000 */ - /* Group 2: 0x00080000 */ - /* Group 3: 0x000c0000 */ - PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ - PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ - PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ - - PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ - - printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n"); -} - - -static void clearPci9054 (void) -{ - /* - * Set EEPROM write-protect register to 0 - */ - out_be32 ((void *)(pci9054_iobase + 0x0c), - in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); - - /* Long Serial EEPROM Load Registers... */ - PciEepromWriteLongVPD (0x00, 0xffffffff); - PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ - - printf ("Finished clearing PLX PCI9054 EEPROM!\n"); -} - - -/* ------------------------------------------------------------------------- */ -int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc, - char * const argv[]) -{ - if (strcmp (argv[1], "info") == 0) { - showPci9054 (); - return 0; - } - - if (strcmp (argv[1], "update") == 0) { - updatePci9054 (); - return 0; - } - - if (strcmp (argv[1], "clear") == 0) { - clearPci9054 (); - return 0; - } - - return cmd_usage(cmdtp); -} - -U_BOOT_CMD( - pci9054, 3, 1, do_pci9054, - "PLX PCI9054 EEPROM access", - "pci9054 info - print EEPROM values\n" - "pci9054 update - updates EEPROM with default values" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c deleted file mode 100644 index b779a09e82..0000000000 --- a/board/esd/dasa_sim/dasa_sim.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include "dasa_sim.h" - -/* ------------------------------------------------------------------------- */ - -#undef FPGA_DEBUG - -#define _NOT_USED_ 0xFFFFFFFF - -/* ------------------------------------------------------------------------- */ - -/* fpga configuration data - generated by bit2inc */ -static unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */ -#define LOAD_LONG(a) a - - -/****************************************************************************** - * - * sysFpgaBoot - Load fpga-image into fpga - * - */ -static int fpgaBoot (void) -{ - int i, j, index, len; - unsigned char b; - int imageSize; - - imageSize = sizeof (fpgadata); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - index += len + 3; - } - - /* search for preamble 0xFF2X */ - for (index = 0; index < imageSize - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x20)) - break; - } - - /* enable cs1 instead of user0... */ - *(unsigned long *) 0x50000084 &= ~0x00000002; - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ? - "NOT DONE" : "DONE"); -#endif - - /* init fpga by asserting and deasserting PROGRAM* (USER2)... */ - *(unsigned long *) 0x50000084 &= ~0x00000400; - udelay (FPGA_PRG_SLEEP * 1000); - - *(unsigned long *) 0x50000084 |= 0x00000400; - udelay (FPGA_PRG_SLEEP * 1000); - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ? - "NOT DONE" : "DONE"); -#endif - - /* cs1: disable burst, disable ready */ - *(unsigned long *) 0x50000114 &= ~0x00000300; - - /* cs1: set write timing */ - *(unsigned long *) 0x50000118 |= 0x00010900; - - /* write configuration-data into fpga... */ - for (i = index; i < imageSize; i++) { - b = fpgadata[i]; - for (j = 0; j < 8; j++) { - *(unsigned long *) 0x30000000 = - ((b & 0x80) == 0x80) - ? LOAD_LONG (0x03030101) - : LOAD_LONG (0x02020000); - b <<= 1; - } - } - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ? - "NOT DONE" : "DONE"); -#endif - - /* set cs1 to 32 bit data-width, disable burst, enable ready */ - *(unsigned long *) 0x50000114 |= 0x00000202; - *(unsigned long *) 0x50000114 &= ~0x00000100; - - /* cs1: set iop access to little endian */ - *(unsigned long *) 0x50000114 &= ~0x00000010; - - /* cs1: set read and write timing */ - *(unsigned long *) 0x50000118 = 0x00010000; - *(unsigned long *) 0x5000011c = 0x00010001; - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ? - "NOT DONE" : "DONE"); -#endif - - /* wait for 30 ms... */ - udelay (30 * 1000); - /* check if fpga's DONE signal - correctly booted ? */ - if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0) - return -1; - - return 0; -} - - -int board_early_init_f (void) -{ - /* - * Init pci regs - */ - *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */ - *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */ - *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */ - *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */ - *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */ - *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */ - *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */ - - return 0; -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - int fpga; - unsigned short val; - - puts ("Board: "); - - /* - * Boot onboard FPGA - */ - fpga = fpgaBoot (); - - if (!i || strncmp (str, "DASA_SIM", 8)) { - puts ("### No HW ID - assuming DASA_SIM"); - } - - puts (str); - - if (fpga == 0) { - val = *(unsigned short *) 0x30000202; - printf (" (Id=%d Version=%d Revision=%d)", - (val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1); - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - } else { - puts ("\nFPGA: Booting failed!"); - } - - putc ('\n'); - - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (16 * 1024 * 1024); -} diff --git a/board/esd/dasa_sim/dasa_sim.h b/board/esd/dasa_sim/dasa_sim.h deleted file mode 100644 index 75e7950bcd..0000000000 --- a/board/esd/dasa_sim/dasa_sim.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/dasa_sim/eeprom.c b/board/esd/dasa_sim/eeprom.c deleted file mode 100644 index 1fc78decd2..0000000000 --- a/board/esd/dasa_sim/eeprom.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define EEPROM_CAP 0x50000358 -#define EEPROM_DATA 0x5000035c - - -unsigned int eepromReadLong(int offs) -{ - unsigned int value; - unsigned short ret; - int count; - - out_be16((void *)EEPROM_CAP, offs); - - count = 0; - - for (;;) - { - count++; - ret = in_be16((void *)EEPROM_CAP); - - if ((ret & 0x8000) != 0) - break; - } - - value = in_be32((void *)EEPROM_DATA); - - return value; -} - - -unsigned char eepromReadByte(int offs) -{ - unsigned int valueLong; - unsigned char *ptr; - - valueLong = eepromReadLong(offs & ~3); - ptr = (unsigned char *)&valueLong; - - return ptr[offs & 3]; -} - - -void eepromWriteLong(int offs, unsigned int value) -{ - unsigned short ret; - int count; - - count = 0; - - out_be32((void *)EEPROM_DATA, value); - out_be16((void *)EEPROM_CAP, 0x8000 + offs); - - for (;;) - { - count++; - ret = in_be16((void *)EEPROM_CAP); - - if ((ret & 0x8000) == 0) - break; - } -} - - -void eepromWriteByte(int offs, unsigned char valueByte) -{ - unsigned int valueLong; - unsigned char *ptr; - - valueLong = eepromReadLong(offs & ~3); - ptr = (unsigned char *)&valueLong; - - ptr[offs & 3] = valueByte; - - eepromWriteLong(offs & ~3, valueLong); -} - - -void i2c_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - int len2, ptr; - - /* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */ - - ptr = *(short *)addr; - - /* - * Read till lword boundary - */ - len2 = 4 - (*(short *)addr & 0x0003); - for (i=0; i> 2; - for (i=0; i> 2; - for (i=0; i -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile deleted file mode 100644 index 0fd6fe53cb..0000000000 --- a/board/esd/dp405/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif - -LIB = $(obj)lib$(BOARD).o - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c deleted file mode 100644 index 730ff215e9..0000000000 --- a/board/esd/dp405/dp405.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - /* - * Reset CPLD via GPIO13 (CS4) pin - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13)); - udelay(1000); /* wait 1ms */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | (0x80000000 >> 13)); - udelay(1000); /* wait 1ms */ - - return 0; -} - -int misc_init_r (void) -{ - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, - 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; - unsigned char id1, id2, rev; - - puts ("Board: "); - - if (i == -1) - puts ("### No HW ID - assuming DP405"); - else - puts(str); - - id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f]; - id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f]; - - rev = in_8((void *)0xf0001000); - if (rev & 0x10) /* old DP405 compatibility */ - rev = in_8((void *)0xf0000800); - - switch (rev & 0xc0) { - case 0x00: - puts(" (HW=DP405"); - break; - case 0x80: - puts(" (HW=DP405/CO"); - break; - case 0xc0: - puts(" (HW=DN405"); - break; - } - printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f); - - if ((rev & 0xc0) == 0xc0) { - printf(", C5V=%s", - in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on"); - } - puts(")\n"); - - return 0; -} diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c deleted file mode 100644 index 23e81642e0..0000000000 --- a/board/esd/dp405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include "du405.h" -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - - -#if 0 -#define FPGA_DEBUG -#endif - -#if 0 -#define FPGA_DEBUG2 -#endif - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - int index, len, i; - int status; - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive - * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive - * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive - * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive - * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 100 us - */ - mtebc (EBC0_CFG, 0xb8400000); - - return 0; -} - - -int misc_init_r (void) -{ - unsigned long CPC0_CR0Reg; - - /* - * Setup UART1 handshaking: use CTS instead of DSR - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming DU405"); - } else { - puts (str); - } - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - - putc ('\n'); - - /* - * Reset external DUART via FPGA - */ - out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */ - out_8((void *)FPGA_MODE_REG, 0x00); /* low again */ - - return 0; -} - -void reset_phy(void) -{ -#if defined(CONFIG_LXT971_NO_SLEEP) - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/du405/du405.h b/board/esd/du405/du405.h deleted file mode 100644 index 292f196304..0000000000 --- a/board/esd/du405/du405.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c deleted file mode 100644 index 5650e5eaf2..0000000000 --- a/board/esd/du405/flash.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr (EBC0_CFGADDR, PB0CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr (EBC0_CFGADDR, PB1CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (EBC0_CFGDATA, pbcr); - /* printf("PB0CR = %x\n", pbcr); */ - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/du405/fpgadata.c b/board/esd/du405/fpgadata.c deleted file mode 100644 index 262f2ca223..0000000000 --- a/board/esd/du405/fpgadata.c +++ /dev/null @@ -1,1405 +0,0 @@ -0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, -0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d, -0x64, 0x75, 0x72, 0x61, 0x67, 0x34, 0x30, 0x35, -0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b, -0x73, 0x32, 0x30, 0x78, 0x6c, 0x74, 0x71, 0x31, -0x34, 0x34, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, -0x30, 0x32, 0x2f, 0x30, 0x32, 0x2f, 0x32, 0x31, -0x00, 0x64, 0x00, 0x09, 0x31, 0x32, 0x3a, 0x35, -0x31, 0x3a, 0x30, 0x38, 0x00, 0x65, 0xe2, 0x01, -0x00, 0x00, 0x2b, 0x98, 0xff, 0x30, 0xe6, 0xe5, -0xe5, 0x02, 0x04, 0x01, 0xe6, 0x04, 0x01, 0x0d, -0x04, 0x04, 0x02, 0x01, 0x04, 0x04, 0x03, 0x07, -0x01, 0x03, 0x01, 0x04, 0x11, 0x01, 0x06, 0x02, -0x15, 0x09, 0x02, 0x05, 0x07, 0x02, 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0x06, 0xe5, 0x02, 0x04, 0x04, 0x01, -0x07, 0x04, 0x04, 0x05, 0x03, 0x01, 0x07, 0x01, -0x07, 0x01, 0x03, 0x03, 0x02, 0x04, 0x04, 0x06, -0x01, 0x03, 0xe5, 0xe5, 0xe6, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile deleted file mode 100644 index 7ccd9a8574..0000000000 --- a/board/esd/du440/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk deleted file mode 100644 index 9cb071e45b..0000000000 --- a/board/esd/du440/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c deleted file mode 100644 index b168b247bd..0000000000 --- a/board/esd/du440/du440.c +++ /dev/null @@ -1,882 +0,0 @@ -/* - * (C) Copyright 2008 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include "du440.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -extern ulong flash_get_size (ulong base, int banknum); - -int usbhub_init(void); -int dvi_init(void); -int eeprom_write_enable (unsigned dev_addr, int state); -int board_revision(void); - -static int du440_post_errors; - -int board_early_init_f(void) -{ - u32 sdr0_cust0; - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; - - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, 0xb8400000); - - /* - * Setup the GPIO pins - */ - out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP); - out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP); - out_be32((void*)GPIO0_OSRL, 0x50055400); - out_be32((void*)GPIO0_OSRH, 0x55005000); - out_be32((void*)GPIO0_TSRL, 0x50055400); - out_be32((void*)GPIO0_TSRH, 0x55005000); - out_be32((void*)GPIO0_ISR1L, 0x50000000); - out_be32((void*)GPIO0_ISR1H, 0x00000000); - out_be32((void*)GPIO0_ISR2L, 0x00000000); - out_be32((void*)GPIO0_ISR2H, 0x00000000); - out_be32((void*)GPIO0_ISR3L, 0x00000000); - out_be32((void*)GPIO0_ISR3H, 0x00000000); - - out_be32((void*)GPIO1_OR, 0x00000000); - out_be32((void*)GPIO1_TCR, 0xc2000000 | - CONFIG_SYS_GPIO1_IORSTN | - CONFIG_SYS_GPIO1_IORST2N | - CONFIG_SYS_GPIO1_LEDUSR1 | - CONFIG_SYS_GPIO1_LEDUSR2 | - CONFIG_SYS_GPIO1_LEDPOST | - CONFIG_SYS_GPIO1_LEDDU); - out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU); - out_be32((void*)GPIO1_OSRL, 0x0c280000); - out_be32((void*)GPIO1_OSRH, 0x00000000); - out_be32((void*)GPIO1_TSRL, 0xcc000000); - out_be32((void*)GPIO1_TSRH, 0x00000000); - out_be32((void*)GPIO1_ISR1L, 0x00005550); - out_be32((void*)GPIO1_ISR1H, 0x00000000); - out_be32((void*)GPIO1_ISR2L, 0x00050000); - out_be32((void*)GPIO1_ISR2H, 0x00000000); - out_be32((void*)GPIO1_ISR3L, 0x01400000); - out_be32((void*)GPIO1_ISR3H, 0x00000000); - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - /* - * UIC1: - * bit30: ext. Irq 1: PLD : int 32+30 - */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xfffffffd); - mtdcr(UIC1TR, 0x00000000); - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - /* - * UIC2 - * bit3: ext. Irq 2: DCF77 : int 64+3 - */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* select Ethernet pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_PFC2, sdr0_pfc2); - - /* setup EMAC bridge interface */ - if (board_revision() == 0) { - /* 1 x MII */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_1_2; - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_1_2; - } else { - /* 2 x SMII */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_6; - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_6; - } - - /* enable 2nd IIC */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; - - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* PCI arbiter enabled */ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); - - /* setup NAND FLASH */ - mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) | - (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); - - return 0; -} - -int misc_init_r(void) -{ - uint pbcr; - int size_val = 0; - u32 reg; - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; - unsigned long sdr0_srst0, sdr0_srst1; - int i, j; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - size_val = ffs(gd->bd->bi_flashsize) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - - /* - * USB suff... - */ - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB0, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - - /* An 8-bit/60MHz interface is the only possible alternative - when connecting the Device to the PHY */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; - - /* To enable the USB 2.0 Device function through the UTMI interface */ - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB0, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /* - * Take USB out of reset: - * -Initial status = all cores are in reset - * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores - * -wait 1 ms - * -deassert reset to PHY - * -wait 1 ms - * -deassert reset to HOST - * -wait 4 ms - * -deassert all other resets - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ - SDR0_SRST1_P4OPB0 | \ - SDR0_SRST1_OPBA2 | \ - SDR0_SRST1_PLB42OPB1 | \ - SDR0_SRST1_OPB2PLB40); - mtsdr(SDR0_SRST1, sdr0_srst1); - udelay(1000); - - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; - mtsdr(SDR0_SRST1, sdr0_srst1); - udelay(1000); - - mfsdr(SDR0_SRST0, sdr0_srst0); - sdr0_srst0 &= ~SDR0_SRST0_USB2H; - mtsdr(SDR0_SRST0, sdr0_srst0); - udelay(4000); - - /* finally all the other resets */ - mtsdr(SDR0_SRST1, 0x00000000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Host(int phy)\n"); - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - - /* - * release IO-RST# - * We have to wait at least 560ms until we may call usbhub_init - */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | - CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N); - - /* - * flash USR1/2 LEDs (600ms) - * This results in the necessary delay from IORST# until - * calling usbhub_init will succeed - */ - for (j = 0; j < 3; j++) { - out_be32((void*)GPIO1_OR, - (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) | - CONFIG_SYS_GPIO1_LEDUSR1); - - for (i = 0; i < 100; i++) - udelay(1000); - - out_be32((void*)GPIO1_OR, - (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) | - CONFIG_SYS_GPIO1_LEDUSR2); - - for (i = 0; i < 100; i++) - udelay(1000); - } - - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & - ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2)); - - if (usbhub_init()) - du440_post_errors++; - - if (dvi_init()) - du440_post_errors++; - - return 0; -} - -int pld_revision(void) -{ - out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00); - return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK); -} - -int board_revision(void) -{ - int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK) - >> CONFIG_SYS_GPIO1_HWVER_SHIFT); - - return ((rpins & 1) << 3) | ((rpins & 2) << 1) | - ((rpins & 4) >> 1) | ((rpins & 8) >> 3); -} - -#if defined(CONFIG_SHOW_ACTIVITY) -void board_show_activity (ulong timestamp) -{ - if ((timestamp % 100) == 0) - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1); -} - -void show_activity(int arg) -{ -} -#endif /* CONFIG_SHOW_ACTIVITY */ - -int du440_phy_addr(int devnum) -{ - if (board_revision() == 0) - return devnum; - - return devnum + 1; -} - -int checkboard(void) -{ - char serno[32]; - - puts("Board: DU440"); - - if (getenv_f("serial#", serno, sizeof(serno)) > 0) { - puts(", serial# "); - puts(serno); - } - - printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n", - board_revision(), pld_revision()); - return (0); -} - -int last_stage_init(void) -{ - int e, i; - - /* everyting is ok: turn on POST-LED */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST); - - /* slowly blink on errors and finally keep LED off */ - for (e = 0; e < du440_post_errors; e++) { - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST); - - for (i = 0; i < 500; i++) - udelay(1000); - - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST); - - for (i = 0; i < 500; i++) - udelay(1000); - } - - return 0; -} - -/* - * read field strength from I2C ADC - */ -int dcf77_status(void) -{ - unsigned int oldbus; - uchar u[2]; - int mv; - - oldbus = I2C_GET_BUS(); - I2C_SET_BUS(1); - - if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) { - I2C_SET_BUS(oldbus); - return -1; - } - - mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024; - - I2C_SET_BUS(oldbus); - return mv; -} - -int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int mv; - u32 pin, pinold; - unsigned long long t1, t2; - bd_t *bd = gd->bd; - - printf("DCF77: "); - mv = dcf77_status(); - if (mv > 0) - printf("signal=%d mV\n", mv); - else - printf("ERROR - no signal\n"); - - t1 = t2 = 0; - pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77; - while (!ctrlc()) { - pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77; - if (pin && !pinold) { /* bit start */ - t1 = get_ticks(); - if (t2 && ((unsigned int)(t1 - t2) / - (bd->bi_procfreq / 1000) >= 1800)) - printf("Start of minute\n"); - - t2 = t1; - } - if (t1 && !pin && pinold) { /* bit end */ - printf("%5d\n", (unsigned int)(get_ticks() - t1) / - (bd->bi_procfreq / 1000)); - } - pinold = pin; - } - - printf("Abort\n"); - return 0; -} -U_BOOT_CMD( - dcf77, 1, 1, do_dcf77, - "Check DCF77 receiver", - "" -); - -/* - * initialize USB hub via I2C1 - */ -int usbhub_init(void) -{ - int reg; - int ret = 0; - unsigned int oldbus; - uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3, - 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64, - 0x32}; - uchar stcd; - - printf("Hub: "); - - oldbus = I2C_GET_BUS(); - I2C_SET_BUS(1); - - for (reg = 0; reg < sizeof(u); reg++) - if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) { - ret = -1; - break; - } - - if (ret == 0) { - stcd = 0x03; - if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1)) - ret = -1; - } - - if (ret == 0) - printf("initialized\n"); - else - printf("failed - cannot initialize USB hub\n"); - - I2C_SET_BUS(oldbus); - return ret; -} - -int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - usbhub_init(); - return 0; -} -U_BOOT_CMD( - hubinit, 1, 1, do_hubinit, - "Initialize USB hub", - "" -); - -#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 -int boot_eeprom_write (unsigned dev_addr, - unsigned offset, - uchar *buffer, - unsigned cnt) -{ - unsigned end = offset + cnt; - unsigned blk_off; - int rcode = 0; - -#if defined(CONFIG_SYS_EEPROM_WREN) - eeprom_write_enable(dev_addr, 1); -#endif - /* - * Write data until done or would cross a write page boundary. - * We must write the address again when changing pages - * because the address counter only increments within a page. - */ - - while (offset < end) { - unsigned alen, len; - unsigned maxlen; - - uchar addr[2]; - - blk_off = offset & 0xFF; /* block offset */ - - addr[0] = offset >> 8; /* block number */ - addr[1] = blk_off; /* block offset */ - alen = 2; - addr[0] |= dev_addr; /* insert device address */ - - len = end - offset; - - /* - * For a FRAM device there is no limit on the number of the - * bytes that can be ccessed with the single read or write - * operation. - */ -#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) - -#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) -#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) - - maxlen = BOOT_EEPROM_PAGE_SIZE - - BOOT_EEPROM_PAGE_OFFSET(blk_off); -#else - maxlen = 0x100 - blk_off; -#endif - if (maxlen > I2C_RXTX_LEN) - maxlen = I2C_RXTX_LEN; - - if (len > maxlen) - len = maxlen; - - if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0) - rcode = 1; - - buffer += len; - offset += len; - -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); -#endif - } -#if defined(CONFIG_SYS_EEPROM_WREN) - eeprom_write_enable(dev_addr, 0); -#endif - return rcode; -} - -int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong sdsdp[4]; - - if (argc > 1) { - if (!strcmp(argv[1], "533")) { - printf("Bootstrapping for 533MHz\n"); - sdsdp[0] = 0x87788252; - /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */ - sdsdp[1] = 0x095fa030; - sdsdp[2] = 0x40082350; - sdsdp[3] = 0x0d050000; - } else if (!strcmp(argv[1], "533-66")) { - printf("Bootstrapping for 533MHz (66MHz PCI)\n"); - sdsdp[0] = 0x87788252; - /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */ - sdsdp[1] = 0x0957a030; - sdsdp[2] = 0x40082350; - sdsdp[3] = 0x0d050000; - } else if (!strcmp(argv[1], "667")) { - printf("Bootstrapping for 667MHz\n"); - sdsdp[0] = 0x8778a256; - /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */ - sdsdp[1] = 0x0947a030; - /* PLB-PCI-divider = 3 : sync PCI clock=44MHz - * -> not working when overclocking 533MHz chips - * -> untested on 667MHz chips */ - /* sdsdp[1]=0x095fa030; */ - sdsdp[2] = 0x40082350; - sdsdp[3] = 0x0d050000; - } else if (!strcmp(argv[1], "667-166")) { - printf("Bootstrapping for 667-166MHz\n"); - sdsdp[0] = 0x8778a252; - sdsdp[1] = 0x09d7a030; - sdsdp[2] = 0x40082350; - sdsdp[3] = 0x0d050000; - } - } else { - printf("Bootstrapping for 533MHz (default)\n"); - sdsdp[0] = 0x87788252; - /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */ - sdsdp[1] = 0x095fa030; - sdsdp[2] = 0x40082350; - sdsdp[3] = 0x0d050000; - } - - printf("Writing boot EEPROM ...\n"); - if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, - 0, (uchar*)sdsdp, 16) != 0) - printf("boot_eeprom_write failed\n"); - else - printf("done (dump via 'i2c md 52 0.1 10')\n"); - - return 0; -} -U_BOOT_CMD( - sbe, 2, 0, do_setup_boot_eeprom, - "setup boot eeprom", - "" -); - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* - * Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) && - (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) - return -1; - else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void*)GPIO0_OR) & - CONFIG_SYS_GPIO0_EP_EEP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) - puts ("Query of write access state failed.\n"); - else { - printf ("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) - puts ("Setup of write access state failed.\n"); - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - -static int got_pldirq; - -static int pld_interrupt(u32 arg) -{ - int rc = -1; /* not for us */ - u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE); - - /* check for PLD interrupt */ - if (status & PWR_INT_FLAG) { - /* reset this int */ - out_8((void *)CONFIG_SYS_CPLD_BASE, 0); - rc = 0; - got_pldirq = 1; /* trigger backend */ - } - - return rc; -} - -int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - got_pldirq = 0; - - /* clear any pending interrupt */ - out_8((void *)CONFIG_SYS_CPLD_BASE, 0); - - irq_install_handler(CPLD_IRQ, - (interrupt_handler_t *)pld_interrupt, 0); - - printf("Waiting ...\n"); - while(!got_pldirq) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - break; - } - } - if (got_pldirq) { - printf("Got interrupt!\n"); - printf("Power %sready!\n", - in_8((void *)CONFIG_SYS_CPLD_BASE) & - PWR_RDY ? "":"NOT "); - } - - irq_free_handler(CPLD_IRQ); - return 0; -} -U_BOOT_CMD( - wpi, 1, 1, do_waitpwrirq, - "Wait for power change interrupt", - "" -); - -/* - * initialize DVI panellink transmitter - */ -int dvi_init(void) -{ - int i; - int ret = 0; - unsigned int oldbus; - uchar u[] = {0x08, 0x34, - 0x09, 0x20, - 0x0a, 0x90, - 0x0c, 0x89, - 0x08, 0x35}; - - printf("DVI: "); - - oldbus = I2C_GET_BUS(); - I2C_SET_BUS(0); - - for (i = 0; i < sizeof(u); i += 2) - if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) { - ret = -1; - break; - } - - if (ret == 0) - printf("initialized\n"); - else - printf("failed - cannot initialize DVI transmitter\n"); - - I2C_SET_BUS(oldbus); - return ret; -} - -int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - dvi_init(); - return 0; -} -U_BOOT_CMD( - dviinit, 1, 1, do_dviinit, - "Initialize DVI Panellink transmitter", - "" -); - -/* - * TODO: 'time' command might be useful for others as well. - * Move to 'common' directory. - */ -int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned long long start, end; - char c, cmd[CONFIG_SYS_CBSIZE]; - char *p, *d = cmd; - int ret, i; - ulong us; - - for (i = 1; i < argc; i++) { - p = argv[i]; - - if (i > 1) - *d++ = ' '; - - while ((c = *p++) != '\0') { - *d++ = c; - } - } - *d = '\0'; - - start = get_ticks(); - ret = run_command(cmd, 0); - end = get_ticks(); - - printf("ticks=%ld\n", (ulong)(end - start)); - us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000)); - printf("usec=%ld\n", us); - - return ret; -} -U_BOOT_CMD( - time, CONFIG_SYS_MAXARGS, 1, do_time, - "run command and output execution time", - "" -); - -extern void video_hw_rectfill ( - unsigned int bpp, /* bytes per pixel */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y, /* frame height */ - unsigned int color /* fill color */ - ); - -/* - * graphics demo - * draw rectangles using pseudorandom number generator - * (see http://www.embedded.com/columns/technicalinsights/20900500) - */ -unsigned int rprime = 9972; -static unsigned int r; -static unsigned int Y; - -unsigned int prng(unsigned int max) -{ - if (r == 0 || r == 1 || r == -1) - r = rprime; /* keep from getting stuck */ - - r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */ - Y = (r >> 16) % max; /* choose upper bits and reduce */ - return Y; -} - -int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int color; - unsigned int x, y, dx, dy; - - while (!ctrlc()) { - x = prng(1280 - 1); - y = prng(1024 - 1); - dx = prng(1280- x - 1); - dy = prng(1024 - y - 1); - color = prng(0x10000); - video_hw_rectfill(2, x, y, dx, dy, color); - } - - return 0; -} -U_BOOT_CMD( - gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo, - "demo", - "" -); diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h deleted file mode 100644 index df065ba017..0000000000 --- a/board/esd/du440/du440.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2008 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDR0_USB0 0x0320 /* USB Control Register */ - -#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */ -#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */ - -#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */ -#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */ - -#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */ -#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4 -#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */ -#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */ -#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */ -#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */ - -#define CPLD_VERSION_MASK 0x0f -#define PWR_INT_FLAG 0x80 -#define PWR_RDY 0x10 - -#define CPLD_IRQ (32+30) diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S deleted file mode 100644 index f3d76b8538..0000000000 --- a/board/esd/du440/init.S +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2008 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - */ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) - - /* TLB-entry for PCI IO */ - tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG ) - - /* TLB-entries for EBC: CPLD, DUMEM, DUIO */ - tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG ) - - /* TLB-entry for NAND */ - tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG ) - - /* TLB-entry for Internal Registers & OCM */ - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) - - /* TLB-entry PCI registers */ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - tlbtab_end diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile deleted file mode 100644 index fdae010b1b..0000000000 --- a/board/esd/hh405/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - ../common/auto_update.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c deleted file mode 100644 index 23e81642e0..0000000000 --- a/board/esd/hh405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* FPGA internal regs */ -#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000)) -#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002)) -#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004)) -#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006)) - -/* FPGA Control Reg */ -#define FPGA_CTRL_REV0 0x0001 -#define FPGA_CTRL_REV1 0x0002 -#define FPGA_CTRL_VGA0_BL 0x0004 -#define FPGA_CTRL_VGA0_BL_MODE 0x0008 -#define FPGA_CTRL_CF_RESET 0x0040 -#define FPGA_CTRL_PS2_PWR 0x0080 -#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */ -#define FPGA_CTRL_CF_BUS_EN 0x0200 -#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */ -#define FPGA_CTRL_OW_ENABLE 0x8000 - -#define FPGA_STATUS_CF_DETECT 0x8000 - -#ifdef CONFIG_VIDEO_SM501 - -#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ - (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) - -#ifdef CONFIG_VIDEO_SM501_8BPP -#error CONFIG_VIDEO_SM501_8BPP not supported. -#endif /* CONFIG_VIDEO_SM501_8BPP */ - -#ifdef CONFIG_VIDEO_SM501_16BPP -#define BPP 16 - -/* - * 800x600 display B084SN03: PCLK = 40MHz - * => 2*PCLK = 80MHz - * 336/4 = 84MHz - * => PCLK = 84MHz - */ -static const SMI_REGS init_regs_800x600 [] = -{ -#if 1 /* test-only */ - {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */ -#else - {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */ -#endif - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* GPIO */ - {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ - /* panel control regs... */ - {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ - {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ - {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x02580320)}, /* panel plane br location */ - {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */ - {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */ - {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -/* - * 1024x768 display G150XG02: PCLK = 65MHz - * => 2*PCLK = 130MHz - * 288/2 = 144MHz - * => PCLK = 72MHz - */ -static const SMI_REGS init_regs_1024x768 [] = -{ - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* GPIO */ - {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ - /* panel control regs... */ - {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ - {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ - {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x03000400)}, /* panel plane br location */ - {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */ - {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */ - {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SM501_16BPP */ - -#ifdef CONFIG_VIDEO_SM501_32BPP -#define BPP 32 - -/* - * 800x600 display B084SN03: PCLK = 40MHz - * => 2*PCLK = 80MHz - * 336/4 = 84MHz - * => PCLK = 84MHz - */ -static const SMI_REGS init_regs_800x600 [] = -{ -#if 0 /* test-only */ - {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */ -#else - {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */ -#endif - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* GPIO */ - {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ - /* panel control regs... */ - {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ - {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ - {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x02580320)}, /* panel plane br location */ - {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */ - {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */ - {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -/* - * 1024x768 display G150XG02: PCLK = 65MHz - * => 2*PCLK = 130MHz - * 288/2 = 144MHz - * => PCLK = 72MHz - */ -static const SMI_REGS init_regs_1024x768 [] = -{ - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* GPIO */ - {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ - /* panel control regs... */ - {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ - {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ - {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x03000400)}, /* panel plane br location */ - {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */ - {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */ - {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SM501_32BPP */ - -#endif /* CONFIG_VIDEO_SM501 */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* logo bitmap data - gzip compressed and generated by bin2c */ -unsigned char logo_bmp_320[] = -{ -#include "logo_320_240_4bpp.c" -}; - -unsigned char logo_bmp_320_8bpp[] = -{ -#include "logo_320_240_8bpp.c" -}; - -unsigned char logo_bmp_640[] = -{ -#include "logo_640_480_24bpp.c" -}; - -unsigned char logo_bmp_1024[] = -{ -#include "logo_1024_768_8bpp.c" -}; - - -/* - * include common lcd code (for esd boards) - */ -#include "../common/lcd.c" - -#include "../common/s1d13704_320_240_4bpp.h" -#include "../common/s1d13705_320_240_8bpp.h" -#include "../common/s1d13806_640_480_16bpp.h" -#include "../common/s1d13806_1024_768_8bpp.h" - - -/* - * include common auto-update code (for esd boards) - */ -#include "../common/auto_update.h" - -au_image_t au_image[] = { - {"hh405/preinst.img", 0, -1, AU_SCRIPT}, - {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE}, - {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND}, - {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND}, - {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND}, - {"hh405/postinst.img", 0, 0, AU_SCRIPT}, -}; - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - - -/* - * Get version of HH405 board from GPIO's - */ -int board_revision(void) -{ - unsigned long osrh_reg; - unsigned long isr1h_reg; - unsigned long tcr_reg; - unsigned long value; - - /* - * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) - */ - osrh_reg = in_be32((void *)GPIO0_OSRH); - isr1h_reg = in_be32((void *)GPIO0_ISR1H); - tcr_reg = in_be32((void *)GPIO0_TCR); - out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */ - out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */ - out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */ - - udelay(1000); /* wait some time before reading input */ - value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */ - - /* - * Restore GPIO settings - */ - out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */ - out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */ - out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ - - if (value & 0x80000000) { - /* Revision 1.0 or 1.1 detected */ - return 1; - } else { - if (value & 0x00400000) { - /* unused */ - return 3; - } else { - return 2; - } - } -} - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int cf_enable(void) -{ - int i; - - if (gd->board_type >= 2) { - if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) { - if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) { - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN); - - for (i=0; i<300; i++) - udelay(1000); - - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN); - - for (i=0; i<20; i++) - udelay(1000); - } - } else { - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN); - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN); - } - } - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - char *str; - unsigned long contrast0 = 0xffffffff; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_INIT pin - */ - /* setup FPGA_INIT as output */ - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | FPGA_INIT); - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */ - udelay(1000); /* wait 1ms */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */ - udelay(1000); /* wait 1ms */ - - /* - * Write Board revision into FPGA - */ - out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003)); - - /* - * Setup and enable EEPROM write protection - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - - /* - * Reset touch-screen controller - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST); - udelay(1000); - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST); - - /* - * Enable power on PS/2 interface (with reset) - */ - out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR); - for (i=0;i<500;i++) - udelay(1000); - out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR); - - /* - * Get contrast value from environment variable - */ - str = getenv("contrast0"); - if (str) { - contrast0 = simple_strtol(str, NULL, 16); - if (contrast0 > 255) { - printf("ERROR: contrast0 value too high (0x%lx)!\n", - contrast0); - contrast0 = 0xffffffff; - } - } - - /* - * Init lcd interface and display logo - */ - - str = getenv("bd_type"); - if (strcmp(str, "ppc230") == 0) { - /* - * Switch backlight on - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL); - out_be16(FPGA_BL, 0x0000); - - lcd_setup(1, 0); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_1024_768_8bpp, - sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]), - logo_bmp_1024, sizeof(logo_bmp_1024)); - } else if (strcmp(str, "ppc220") == 0) { - /* - * Switch backlight on - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL); - out_be16(FPGA_BL, 0x0000); - - lcd_setup(1, 0); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp_640, sizeof(logo_bmp_640)); - } else if (strcmp(str, "ppc215") == 0) { - /* - * Set default display contrast voltage - */ - if (contrast0 == 0xffffffff) { - out_be16(FPGA_CTR, 0x0082); - } else { - out_be16(FPGA_CTR, contrast0); - } - out_be16(FPGA_BL, 0xffff); - /* - * Switch backlight on - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | - FPGA_CTRL_VGA0_BL | - FPGA_CTRL_VGA0_BL_MODE); - /* - * Set lcd clock (small epson) - */ - out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250); - udelay(100); /* wait for 100 us */ - - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13705_320_240_8bpp, - sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]), - logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp)); - } else if (strcmp(str, "ppc210") == 0) { - /* - * Set default display contrast voltage - */ - if (contrast0 == 0xffffffff) { - out_be16(FPGA_CTR, 0x0060); - } else { - out_be16(FPGA_CTR, contrast0); - } - out_be16(FPGA_BL, 0xffff); - /* - * Switch backlight on - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | - FPGA_CTRL_VGA0_BL | - FPGA_CTRL_VGA0_BL_MODE); - /* - * Set lcd clock (small epson), enable 1-wire interface - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | - LCD_CLK_08330 | - FPGA_CTRL_OW_ENABLE); - - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); -#ifdef CONFIG_VIDEO_SM501 - } else { - pci_dev_t devbusfn; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - puts("VGA: SM501 with 8 MB "); - if (strcmp(str, "ppc221") == 0) { - printf("(800*600, %dbpp)\n", BPP); - out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */ - } else if (strcmp(str, "ppc231") == 0) { - printf("(1024*768, %dbpp)\n", BPP); - out_be16(FPGA_BL, 0x0000); - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } -#endif /* CONFIG_VIDEO_SM501 */ - } - - cf_enable(); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming HH405"); - } else { - puts(str); - } - - if (getenv_f("bd_type", str, sizeof(str)) != -1) { - printf(" (%s", str); - } else { - puts(" (Missing bd_type!"); - } - - gd->board_type = board_revision(); - printf(", Rev %ld.x)\n", gd->board_type); - - return 0; -} - -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - if (((gd->board_type >= 2) && - (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) || - (gd->board_type < 2)) { - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - cf_enable(); - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) & - ~FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | - FPGA_CTRL_CF_RESET); - } - } -} -#endif /* CONFIG_IDE_RESET */ - - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) & - CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - - -#ifdef CONFIG_VIDEO_SM501 -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - char str[64]; - char str2[64]; - int i = getenv_f("serial#", str2, sizeof(str)); - - if (line_number == 1) { - sprintf(str, " Board: "); - - if (i == -1) { - strcat(str, "### No HW ID - assuming HH405"); - } else { - strcat(str, str2); - } - - if (getenv_f("bd_type", str2, sizeof(str2)) != -1) { - strcat(str, " ("); - strcat(str, str2); - } else { - strcat(str, " (Missing bd_type!"); - } - - sprintf(str2, ", Rev %ld.x)", gd->board_type); - strcat(str, str2); - strcpy(info, str); - } else { - info [0] = '\0'; - } -} -#endif /* CONFIG_CONSOLE_EXTRA_INFO */ - -/* - * Returns SM501 register base address. First thing called in the driver. - */ -unsigned int board_video_init (void) -{ - pci_dev_t devbusfn; - u32 addr; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr); - return (addr & 0xfffffffe); - } - - return 0; -} - -/* - * Returns SM501 framebuffer address - */ -unsigned int board_video_get_fb (void) -{ - pci_dev_t devbusfn; - u32 addr; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr); - addr &= 0xfffffffe; -#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET - addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; -#endif - return addr; - } - - return 0; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen (unsigned int base) -{ -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return init_regs_800x600; - } else { - return init_regs_1024x768; - } -} - -int board_get_width (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return 800; - } else { - return 1024; - } -} - -int board_get_height (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return 600; - } else { - return 768; - } -} - -#endif /* CONFIG_VIDEO_SM501 */ - - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/hh405/logo_1024_768_8bpp.c b/board/esd/hh405/logo_1024_768_8bpp.c deleted file mode 100644 index 331540f7f7..0000000000 --- a/board/esd/hh405/logo_1024_768_8bpp.c +++ /dev/null @@ -1,5087 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0x20, 0xb5, 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SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c deleted file mode 100644 index 23e81642e0..0000000000 --- a/board/esd/hub405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -int board_revision(void) -{ - unsigned long osrl_reg; - unsigned long isr1l_reg; - unsigned long tcr_reg; - unsigned long value; - - /* - * Get version of HUB405 board from GPIO's - */ - - /* - * Setup GPIO pin(s) (IRQ6/GPIO23) - */ - osrl_reg = in_be32((void *)GPIO0_OSRH); - isr1l_reg = in_be32((void *)GPIO0_ISR1H); - tcr_reg = in_be32((void *)GPIO0_TCR); - out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */ - out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */ - out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */ - - udelay(1000); /* wait some time before reading input */ - value = in_be32((void *)GPIO0_IR) & 0x00000100; /* get config bits */ - - /* - * Restore GPIO settings - */ - out_be32((void *)GPIO0_OSRH, osrl_reg); /* output select */ - out_be32((void *)GPIO0_ISR1H, isr1l_reg); /* input select */ - out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ - - if (value & 0x00000100) { - /* Revision 1.1 or 1.2 detected */ - return 1; - } - - /* Revision 1.0 */ - return 0; -} - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -#define LED_REG (DUART0_BA + 0x20) -int misc_init_r (void) -{ - unsigned long val; - int delay, flashcnt; - char *str; - char hw_rev[4]; - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8((void *)(DUART0_BA + 4), 0x08); - out_8((void *)(DUART1_BA + 4), 0x08); - out_8((void *)(DUART2_BA + 4), 0x08); - out_8((void *)(DUART3_BA + 4), 0x08); - - /* - * Set RS232/RS422 control (RS232 = high on GPIO) - */ - val = in_be32((void *)GPIO0_OR); - val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 | - CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232); - - str = getenv("phys0"); - if (!str || (str && (str[0] == '0'))) - val |= CONFIG_SYS_UART2_RS232; - - str = getenv("phys1"); - if (!str || (str && (str[0] == '0'))) - val |= CONFIG_SYS_UART3_RS232; - - str = getenv("phys2"); - if (!str || (str && (str[0] == '0'))) - val |= CONFIG_SYS_UART4_RS232; - - str = getenv("phys3"); - if (!str || (str && (str[0] == '0'))) - val |= CONFIG_SYS_UART5_RS232; - - out_be32((void *)GPIO0_OR, val); - - /* - * check board type and setup AP power - */ - str = getenv("bd_type"); /* this is only set on non prototype hardware */ - if (str != NULL) { - if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) { - unsigned char led_reg_default = 0; - str = getenv("ap_pwr"); - if (!str || (str && (str[0] == '1'))) - led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */ - - /* - * Flash LEDs - */ - for (flashcnt = 0; flashcnt < 3; flashcnt++) { - /* LED_A..D off */ - out_8((void *)LED_REG, led_reg_default); - for (delay = 0; delay < 100; delay++) - udelay(1000); - /* LED_A..D on */ - out_8((void *)LED_REG, led_reg_default | 0xf0); - for (delay = 0; delay < 50; delay++) - udelay(1000); - } - out_8((void *)LED_REG, led_reg_default); - } - } - - /* - * Reset external DUARTs - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Store hardware revision in environment for further processing - */ - sprintf(hw_rev, "1.%ld", gd->board_type); - setenv("hw_rev", hw_rev); - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming HUB405"); - } else { - puts(str); - } - - if (getenv_f("bd_type", str, sizeof(str)) != -1) { - printf(" (%s", str); - } else { - puts(" (Missing bd_type!"); - } - - gd->board_type = board_revision(); - printf(", Rev 1.%ld)\n", gd->board_type); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} diff --git a/board/esd/mecp5123/Kconfig b/board/esd/mecp5123/Kconfig new file mode 100644 index 0000000000..3f2a411196 --- /dev/null +++ b/board/esd/mecp5123/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MECP5123 + +config SYS_BOARD + default "mecp5123" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "mecp5123" + +endif diff --git a/board/esd/mecp5123/MAINTAINERS b/board/esd/mecp5123/MAINTAINERS new file mode 100644 index 0000000000..ae5fcead90 --- /dev/null +++ b/board/esd/mecp5123/MAINTAINERS @@ -0,0 +1,6 @@ +MECP5123 BOARD +M: Reinhard Arlt +S: Maintained +F: board/esd/mecp5123/ +F: include/configs/mecp5123.h +F: configs/mecp5123_defconfig diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile index f78fe13d35..f5ebb0144f 100644 --- a/board/esd/mecp5123/Makefile +++ b/board/esd/mecp5123/Makefile @@ -4,25 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mecp5123.o diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index 97006116f4..cda1d7bccc 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -199,8 +199,10 @@ int checkboard(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/mecp5200/Makefile b/board/esd/mecp5200/Makefile deleted file mode 100644 index c85223385b..0000000000 --- a/board/esd/mecp5200/Makefile +++ /dev/null @@ -1,29 +0,0 @@ - -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c deleted file mode 100644 index 17a70a9ff6..0000000000 --- a/board/esd/mecp5200/mecp5200.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * pf5200.c - main board support/init for the esd pf5200. - */ - -#include -#include -#include -#include -#include - -#include "mt46v16m16-75.h" - -void init_power_switch(void); - -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register: extended mode */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - - /* set tap delay */ - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000); - - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(dramsize >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ - } else { -#if 0 - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ -#else - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(0x08000000 >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ -#endif - } - -#if 0 - /* find RAM size using SDRAM CS1 only */ - sdram_start(0); - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(1); - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(0); -#endif - /* set SDRAM CS1 size according to the amount of RAM found */ - - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - - init_power_switch(); - return (dramsize); -} - -int checkboard(void) -{ - puts("Board: esd CPX CPU5200 (mecp5200)\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == CONFIG_SYS_FLASH_SIZE) { - /* adjust mapping */ - *(vu_long *) MPC5XXX_BOOTCS_START = - *(vu_long *) MPC5XXX_CS0_START = - START_REG(CONFIG_SYS_BOOTCS_START | size); - *(vu_long *) MPC5XXX_BOOTCS_STOP = - *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -#define GPIO_PSC1_4 0x01000000UL - -void init_ide_reset(void) -{ - debug("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -} - -void ide_set_reset(int idereset) -{ - debug("ide_reset(%d)\n", idereset); - - if (idereset) - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - else - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -} -#endif - -#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) -#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) - -#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) -#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) -#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) -#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) - -#define GPIO_WU6 0x40000000UL -#define GPIO_USB0 0x00010000UL -#define GPIO_USB9 0x08000000UL -#define GPIO_USB9S 0x00080000UL - -void init_power_switch(void) -{ - debug("init_power_switch\n"); - - /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; - __asm__ volatile ("sync"); - - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; - __asm__ volatile ("sync"); - } -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h deleted file mode 100644 index 63a403231d..0000000000 --- a/board/esd/mecp5200/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x705f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/esd/meesc/Kconfig b/board/esd/meesc/Kconfig new file mode 100644 index 0000000000..5041041dd2 --- /dev/null +++ b/board/esd/meesc/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MEESC + +config SYS_BOARD + default "meesc" + +config SYS_VENDOR + default "esd" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "meesc" + +endif diff --git a/board/esd/meesc/MAINTAINERS b/board/esd/meesc/MAINTAINERS new file mode 100644 index 0000000000..94036991be --- /dev/null +++ b/board/esd/meesc/MAINTAINERS @@ -0,0 +1,7 @@ +MEESC BOARD +M: Daniel Gorsulowski +S: Maintained +F: board/esd/meesc/ +F: include/configs/meesc.h +F: configs/meesc_defconfig +F: configs/meesc_dataflash_defconfig diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile index a7a16fe0a2..5d1673820d 100644 --- a/board/esd/meesc/Makefile +++ b/board/esd/meesc/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += meesc.o +obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 9bf6739081..c5994e0a4a 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -74,10 +75,10 @@ static void meesc_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif /* CONFIG_CMD_NAND */ diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile deleted file mode 100644 index b8452582be..0000000000 --- a/board/esd/ocrtc/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c deleted file mode 100644 index 6dcbd8b24c..0000000000 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - - -#if defined(CONFIG_CMD_BSP) - -/* - * Set device number on pci board - */ -int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int idx = 1; /* start at 1 (skip device 0) */ - pci_dev_t bdf = 0; - u32 addr; - - while (bdf >= 0) { - if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) { - break; - } - printf("Found device nr %d at %x!\n", idx-1, bdf); - pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); - addr &= ~0xf; - *(u32 *)addr = (bdf & 0x0000f800) >> 11; - printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr); - } - - return 0; -} -U_BOOT_CMD( - setdevice, 1, 1, do_setdevice, - "Set device number on pci adapter boards", - "" -); - - -/* - * Get device number on pci board - */ -int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 device; - char str[32]; - - device = *(u32 *)0x0; - device = 0x16 - device; /* calculate vxworks bp slot id */ - sprintf(str, "%d", device); - setenv("slot", str); - printf("Variabel slot set to %x\n", device); - - return 0; -} -U_BOOT_CMD( - getdevice, 1, 1, do_getdevice, - "Get device number and set slot env variable", - "" -); - -#endif diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c deleted file mode 100644 index 279746e57b..0000000000 --- a/board/esd/ocrtc/flash.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr (EBC0_CFGADDR, PB0CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - switch (size_b1) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); - mtdcr (EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr (EBC0_CFGADDR, PB1CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - switch (size_b1) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr (EBC0_CFGDATA, pbcr); - /* printf("PB0CR = %x\n", pbcr); */ - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c deleted file mode 100644 index b81596135b..0000000000 --- a/board/esd/ocrtc/ocrtc.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include "ocrtc.h" -#include -#include -#include - - -extern void lxt971_no_sleep(void); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: clear EBTC -> high-Z ebc signals between - * transfers, set device-paced timeout to 256 cycles - */ - mtebc (EBC0_CFG, 0x20400000); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (i == -1) { -#ifdef CONFIG_OCRTC - puts ("### No HW ID - assuming OCRTC"); -#endif -#ifdef CONFIG_ORSG - puts ("### No HW ID - assuming ORSG"); -#endif - } else { - puts (str); - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return (0); -} diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h deleted file mode 100644 index 029e27efa4..0000000000 --- a/board/esd/ocrtc/ocrtc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/otc570/Kconfig b/board/esd/otc570/Kconfig new file mode 100644 index 0000000000..55a2f70f40 --- /dev/null +++ b/board/esd/otc570/Kconfig @@ -0,0 +1,15 @@ +if TARGET_OTC570 + +config SYS_BOARD + default "otc570" + +config SYS_VENDOR + default "esd" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "otc570" + +endif diff --git a/board/esd/otc570/MAINTAINERS b/board/esd/otc570/MAINTAINERS new file mode 100644 index 0000000000..a7e165d8ba --- /dev/null +++ b/board/esd/otc570/MAINTAINERS @@ -0,0 +1,7 @@ +OTC570 BOARD +M: Daniel Gorsulowski +S: Maintained +F: board/esd/otc570/ +F: include/configs/otc570.h +F: configs/otc570_defconfig +F: configs/otc570_dataflash_defconfig diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile index 53179131c2..740bb0a282 100644 --- a/board/esd/otc570/Makefile +++ b/board/esd/otc570/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += otc570.o +obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index acc1b31b70..4751d0a9e9 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -82,10 +83,10 @@ static void otc570_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif /* CONFIG_CMD_NAND */ diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile deleted file mode 100644 index 9f01c56786..0000000000 --- a/board/esd/pci405/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ../common/misc.o cmd_pci405.o -SOBJS = writeibm.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) -# $(call cmd_link_o_target, $(OBJS)) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c deleted file mode 100644 index 55c20d02d3..0000000000 --- a/board/esd/pci405/cmd_pci405.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pci405.h" - -#if defined(CONFIG_CMD_BSP) - -/* - * Command loadpci: wait for signal from host and boot image. - */ -int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int *ptr = 0; - int count = 0; - int count2 = 0; - int i; - char addr[16]; - char str[] = "\\|/-"; - char *local_args[2]; - - /* - * Mark sync address - */ - ptr = 0; - *ptr = 0xffffffff; - puts("\nWaiting for image from pci host -"); - - /* - * Wait for host to write the start address - */ - while (*ptr == 0xffffffff) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - if (*ptr == PCI_RECONFIG_MAGIC) { - /* - * Save own pci configuration in PRAM - */ - memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_read_config_dword(PCIDEVID_405GP, i, ptr++); - } - ptr = (unsigned int *)PCI_REGS_ADDR; - *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); - - printf("\nStoring PCI Configuration Regs...\n"); - } else { - sprintf(addr, "%08x", *ptr); - - /* - * Boot image via bootm - */ - printf("\nBooting Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - local_args[0] = argv[0]; - local_args[1] = NULL; - do_bootm (cmdtp, 0, 1, local_args); - } - - return 0; -} -U_BOOT_CMD( - loadpci, 1, 1, do_loadpci, - "Wait for pci-image and boot it", - "" -); -#endif diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c deleted file mode 100644 index 113111d3a6..0000000000 --- a/board/esd/pci405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include -#include -#include - -#include "pci405.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Prototypes */ -unsigned long fpga_done_state(void); -unsigned long fpga_init_state(void); - -#if 0 -#define FPGA_DEBUG -#endif - -/* predefine these here */ -#define FPGA_DONE_STATE (fpga_done_state()) -#define FPGA_INIT_STATE (fpga_init_state()) - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE) -#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12) - -#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT) -#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12) - - -int board_revision(void) -{ - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Get version of PCI405 board from GPIO's - */ - - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */ - - /* - * Restore GPIO settings - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - switch (value) { - case 0x00100200: - /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ - return 1; - case 0x00000200: - /* CS2==0 && IRQ5==1 -> version 1.2 */ - return 2; - case 0x00000000: - /* CS2==0 && IRQ5==0 -> version 1.3 */ - return 3; -#if 0 /* not yet manufactured ! */ - case 0x00100000: - /* CS2==1 && IRQ5==0 -> version 1.4 */ - return 4; -#endif - default: - /* should not be reached! */ - return 0; - } -} - - -unsigned long fpga_done_state(void) -{ - if (gd->board_type < 2) { - return FPGA_DONE_STATE_V11; - } else { - return FPGA_DONE_STATE_V12; - } -} - - -unsigned long fpga_init_state(void) -{ - if (gd->board_type < 2) { - return FPGA_INIT_STATE_V11; - } else { - return FPGA_INIT_STATE_V12; - } -} - - -int board_early_init_f (void) -{ - unsigned long CPC0_CR0Reg; - - /* - * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) - */ - out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ - out_be32((void*)GPIO0_OR, 0); /* pull prg low */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive - * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive - * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive - * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive - * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * Setup GPIO pins (IRQ4/GPIO21 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000); - - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - unsigned int *ptr; - unsigned int *magic; - - /* - * On PCI-405 the environment is saved in eeprom! - * FPGA can be gzip compressed (malloc) and booted this late. - */ - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Check if magic for pci reconfig is written - */ - magic = (unsigned int *)0x00000004; - if (*magic == PCI_RECONFIG_MAGIC) { - /* - * Rewrite pci config regs (only after soft-reset with magic set) - */ - ptr = (unsigned int *)PCI_REGS_ADDR; - if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { - puts("Restoring PCI Configurations Regs!\n"); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); - } - } - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - *magic = 0; /* clear pci reconfig magic again */ - } - - /* - * Decrease PLB latency timeout and reduce priority of the PCI bridge master - */ -#define PCI0_BRDGOPT1 0x4a - pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); - - /* - * Enable fairness and high bus utilization - */ - mtdcr(PLB0_ACR, 0x98000000); - - free(dst); - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming PCI405"); - } else { - puts (str); - } - - gd->board_type = board_revision(); - printf(" (Rev 1.%ld", gd->board_type); - - if (gd->board_type >= 2) { - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Setup GPIO pins (Trace/GPIO1 to GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */ - if (value) { - puts(", 33 MHz PCI"); - } else { - puts(", 66 MHz PCI"); - } - } - - puts(")\n"); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#define UART1_MCR 0xef600404 -int wpeeprom(int wp) -{ - int wp_state = wp; - - if (wp == 1) { - out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02); - } else if (wp == 0) { - out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02); - } else { - if (in_8((void *)UART1_MCR) & 0x02) { - wp_state = 0; - } else { - wp_state = 1; - } - } - return wp_state; -} - -int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int wp = -1; - if (argc >= 2) { - if (argv[1][0] == '1') { - wp = 1; - } else if (argv[1][0] == '0') { - wp = 0; - } - } - - wp = wpeeprom(wp); - printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); - return 0; -} - -U_BOOT_CMD( - wpeeprom, 2, 1, do_wpeeprom, - "Check/Enable/Disable I2C EEPROM write protection", - "wpeeprom\n" - " - check I2C EEPROM write protection state\n" - "wpeeprom 1\n" - " - enable I2C EEPROM write protection\n" - "wpeeprom 0\n" - " - disable I2C EEPROM write protection" -); diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h deleted file mode 100644 index a62c9c2b0f..0000000000 --- a/board/esd/pci405/pci405.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PCI405_H_ -#define _PCI405_H_ - -#define PCI_REGS_LEN 0x100 -#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN) - -#define PCI_RECONFIG_MAGIC 0x07081967 - -#endif /* _PCI405_H_ */ diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S deleted file mode 100644 index 5925bc6ec0..0000000000 --- a/board/esd/pci405/writeibm.S +++ /dev/null @@ -1,227 +0,0 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code is dual-licensed. You may use it under the terms */ -/* of the GNU General Public License version 2, or under the license */ -/* below. */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*----------------------------------------------------------------------------- */ -#include - -#include -#include - -#include -#include - - - .globl write_without_sync -write_without_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start1: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - - b start1 - - blr /* never reached !!!! */ - - .globl write_with_sync -write_with_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start2: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - sync - - b start2 - - blr /* never reached !!!! */ - - .globl write_with_less_sync -write_with_less_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start2b: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 -/* sync */ - - b start2b - - blr /* never reached !!!! */ - - .globl write_with_more_sync -write_with_more_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start3: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - sync - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - sync - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id (PCIC0_SBSYSVID)*/ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - sync - - b start3 - - blr /* never reached !!!! */ diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile deleted file mode 100644 index 121f772806..0000000000 --- a/board/esd/pf5200/Makefile +++ /dev/null @@ -1,38 +0,0 @@ - -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -# ifneq ($(OBJTREE),$(SRCTREE)) -# $(shell mkdir -p $(obj)../common/xilinx_jtag) -# endif - -LIB = $(obj)lib$(BOARD).o - -# Objects for Xilinx JTAG programming (CPLD) -# CPLD = ../common/xilinx_jtag/lenval.o \ -# ../common/xilinx_jtag/micro.o \ -# ../common/xilinx_jtag/ports.o - -# COBJS = $(BOARD).o flash.o $(CPLD) -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c deleted file mode 100644 index e1b13bfc44..0000000000 --- a/board/esd/pf5200/flash.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0x00FF - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x0aaa -#define FLASH_ID1 0x00 -#define FLASH_ID2 0x01 -#define FLASH_ID3 0x0E -#define FLASH_ID4 0x0F - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV * addr, flash_info_t * info); -static void flash_reset(flash_info_t * info); -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init(void) -{ - unsigned long size = 0; - int i = 0; - extern void flash_preinit(void); - extern void flash_afterinit(uint, ulong, ulong); - - ulong flashbase = CONFIG_SYS_FLASH_BASE; - - flash_preinit(); - - /* There is only ONE FLASH device */ - memset(&flash_info[i], 0, sizeof(flash_info_t)); - flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]); - size += flash_info[i].size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - flash_afterinit(i, flash_info[i].start[0], flash_info[i].size); - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t * info) { - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) { - int i; - flash_info_t *info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - info = &flash_info[i]; - if ((info->size) && (info->start[0] <= base) - && (base <= info->start[0] + info->size - 1)) { - break; - } - } - return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info); -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info(flash_info_t * info) { - int i; - char *fmt; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMLV256U: - fmt = "29LV256M (256 Mbit)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf(fmt); - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, - info->sector_count); - printf(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - ulong size; - int erased; - ulong *flash = (unsigned long *)info->start[i]; - - if ((i % 5) == 0) { - printf("\n "); - } - - /* - * Check if whole sector is erased - */ - size = - (i != - (info->sector_count - 1)) ? (info->start[i + 1] - - info->start[i]) >> 2 : (info-> - start - [0] + - info-> - size - - info-> - start - [i]) - >> 2; - - for (flash = (unsigned long *)info->start[i], erased = 1; - (flash != (unsigned long *)info->start[i] + size) - && erased; flash++) { - erased = *flash == ~0x0UL; - } - printf(" %08lX %s %s", info->start[i], erased ? "E" : " ", - info->protect[i] ? "(RO)" : " "); - } - - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size(FPWV * addr, flash_info_t * info) { - int i; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. */ - /* This works for any bus width and any FLASH device width. */ - udelay(100); - switch (addr[FLASH_ID1] & 0x00ff) { - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) { - switch ((FPW) addr[FLASH_ID2]) { - case (FPW) AMD_ID_MIRROR: - /* MIRROR BIT FLASH, read more ID bytes */ - if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2 - && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) { - /* attention: only the first 16 MB will be used in u-boot */ - info->flash_id += FLASH_AMLV256U; - info->sector_count = 512; - info->size = 0x02000000; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = - (ulong) addr + 0x10000 * i; - } - break; - } - /* fall thru to here ! */ - default: - printf("unknown AMD device=%x %x %x", - (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3], - (FPW) addr[FLASH_ID4]); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0x800000; - break; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - } - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) { - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMLV256U: - break; - case FLASH_UNKNOWN: - default: - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - if (info->protect[sect] != 0) { /* protected, skip it */ - continue; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. */ - /* Let's wait 1 ms. */ - udelay(1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { - /* every second */ - putc('.'); - last = get_timer(0); - } - } - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { - /* every second */ - putc('.'); - last = get_timer(0); - } - flash_reset(info); /* reset to read mode */ - } - printf(" done\n"); - return (rcode); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) { - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *) (info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - res = 1; - } - } - return (res); -} diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h deleted file mode 100644 index 63a403231d..0000000000 --- a/board/esd/pf5200/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x705f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c deleted file mode 100644 index 7a9ed229ef..0000000000 --- a/board/esd/pf5200/pf5200.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * pf5200.c - main board support/init for the esd pf5200. - */ - -#include -#include -#include -#include -#include - -#include "mt46v16m16-75.h" - -void init_power_switch(void); - -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register: extended mode */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - - /* set tap delay */ - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); - - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(dramsize >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ - } else { -#if 0 - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ -#else - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(0x08000000 >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ -#endif - } - -#if 0 - /* find RAM size using SDRAM CS1 only */ - sdram_start(0); - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(1); - get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(0); -#endif - /* set SDRAM CS1 size according to the amount of RAM found */ - - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - - init_power_switch(); - return (dramsize); -} - -int checkboard(void) -{ - puts("Board: esd ParaFinder (pf5200)\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == 0x02000000) { - /* adjust mapping */ - *(vu_long *) MPC5XXX_BOOTCS_START = - *(vu_long *) MPC5XXX_CS0_START = - START_REG(CONFIG_SYS_BOOTCS_START | size); - *(vu_long *) MPC5XXX_BOOTCS_STOP = - *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) { - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset(void) -{ - debug("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -} - -void ide_set_reset(int idereset) -{ - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -} -#endif - -#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) -#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) - -#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) -#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) -#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) -#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) - -#define GPIO_WU6 0x40000000UL -#define GPIO_USB0 0x00010000UL -#define GPIO_USB9 0x08000000UL -#define GPIO_USB9S 0x00080000UL - -void init_power_switch(void) -{ - debug("init_power_switch\n"); - - /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; - __asm__ volatile ("sync"); - - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; - __asm__ volatile ("sync"); - } - *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */ - __asm__ volatile ("sync"); - - *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */ - __asm__ volatile ("sync"); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -void power_set_reset(int power) -{ - debug("ide_set_reset(%d)\n", power); - - if (power) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6; - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == - 0) { - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= - GPIO_USB0; - } - - } -} - -int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - power_set_reset(1); - return (0); -} - -U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", ""); - -int phypower(int flag) -{ - u32 addr; - vu_long *reg; - int status; - pci_dev_t dev; - - dev = PCI_BDF(0, 0x18, 0); - status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr); - if (status == 0) { - reg = (vu_long *) (addr + 0x00000040); - *reg |= 0x40000000; - __asm__ volatile ("sync"); - - reg = (vu_long *) (addr + 0x001000c); - *reg |= 0x20000000; - __asm__ volatile ("sync"); - - reg = (vu_long *) (addr + 0x0010004); - if (flag != 0) { - *reg &= ~0x20000000; - } else { - *reg |= 0x20000000; - } - __asm__ volatile ("sync"); - } - return (status); -} - -int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argv[1][0] == '0') - (void)phypower(0); - else - (void)phypower(1); - - return (0); -} - -U_BOOT_CMD(phypower, 2, 2, do_phypower, - "Switch power of ethernet phy", ""); - -int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int addr; - unsigned int size; - int i; - volatile unsigned long *ptr; - - addr = simple_strtol(argv[1], NULL, 16); - size = simple_strtol(argv[2], NULL, 16); - - printf("\nWriting at addr %08x, size %08x.\n", addr, size); - - while (1) { - ptr = (volatile unsigned long *)addr; - for (i = 0; i < (size >> 2); i++) { - *ptr++ = i; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - putc('.'); - } - return 0; -} - -U_BOOT_CMD(writepci, 3, 1, do_writepci, - "Write some data to pcibus", - " \n" - "" -); diff --git a/board/esd/plu405/Kconfig b/board/esd/plu405/Kconfig new file mode 100644 index 0000000000..b3082cb022 --- /dev/null +++ b/board/esd/plu405/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PLU405 + +config SYS_BOARD + default "plu405" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "PLU405" + +endif diff --git a/board/esd/plu405/MAINTAINERS b/board/esd/plu405/MAINTAINERS new file mode 100644 index 0000000000..ccb365843d --- /dev/null +++ b/board/esd/plu405/MAINTAINERS @@ -0,0 +1,6 @@ +PLU405 BOARD +M: Matthias Fuchs +S: Maintained +F: board/esd/plu405/ +F: include/configs/PLU405.h +F: configs/PLU405_defconfig diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile index 17dd09783b..6ffae677b1 100644 --- a/board/esd/plu405/Makefile +++ b/board/esd/plu405/Makefile @@ -5,29 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o \ +obj-y = plu405.o flash.o \ ../common/misc.o \ ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile deleted file mode 100644 index 225974d986..0000000000 --- a/board/esd/pmc405/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif - -LIB = $(obj)lib$(BOARD).o - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -COBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c deleted file mode 100644 index e67ff309df..0000000000 --- a/board/esd/pmc405/pmc405.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2005-2009 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: - * set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); - - /* - * Setup GPIO pins - */ - mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT | - CONFIG_SYS_FPGA_DONE | - CONFIG_SYS_XEREADY | - CONFIG_SYS_NONMONARCH | - CONFIG_SYS_REV1_2) << 5)); - - if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) { - /* rev 1.2 boards */ - mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE | - CONFIG_SYS_SELF_RST) << 5)); - } - - out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN); - /* setup for output */ - out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | - CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN); - - /* - * - check if rev1_2 is low, then: - * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST - * in TCR to assert INTA# or SELFRST# - */ - return 0; -} - -int misc_init_r (void) -{ - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* deassert EREADY# */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY); - return (0); -} - -ushort pmc405_pci_subsys_deviceid(void) -{ - ulong val; - - val = in_be32((void *)GPIO0_IR); - if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ - /* check monarch# signal */ - if (val & CONFIG_SYS_NONMONARCH) - return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; - return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH; - } - return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; -} - -/* - * Check Board Identity - */ -int checkboard (void) -{ - ulong val; - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) - puts ("### No HW ID - assuming PMC405"); - else - puts(str); - - val = in_be32((void *)GPIO0_IR); - if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ - puts(" rev1.2 ("); - if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */ - puts("non-"); - puts("monarch)"); - } else - puts(" <=rev1.1"); - - putc ('\n'); - - return 0; -} - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/pmc405de/Kconfig b/board/esd/pmc405de/Kconfig new file mode 100644 index 0000000000..4b05787a49 --- /dev/null +++ b/board/esd/pmc405de/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PMC405DE + +config SYS_BOARD + default "pmc405de" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "PMC405DE" + +endif diff --git a/board/esd/pmc405de/MAINTAINERS b/board/esd/pmc405de/MAINTAINERS new file mode 100644 index 0000000000..a891e23414 --- /dev/null +++ b/board/esd/pmc405de/MAINTAINERS @@ -0,0 +1,6 @@ +PMC405DE BOARD +M: Matthias Fuchs +S: Maintained +F: board/esd/pmc405de/ +F: include/configs/PMC405DE.h +F: configs/PMC405DE_defconfig diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile index 997f07ec11..b3f6dcd1e7 100644 --- a/board/esd/pmc405de/Makefile +++ b/board/esd/pmc405de/Makefile @@ -5,30 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS-y = $(BOARD).o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -COBJS-y += ../common/cmd_loadpci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = pmc405de.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index 4409ea6524..3e1713247d 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -300,7 +300,7 @@ int pci_pre_init(struct pci_controller *hose) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -318,6 +318,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_strerror(rc)); } } + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/pmc440/Kconfig b/board/esd/pmc440/Kconfig new file mode 100644 index 0000000000..df8bd65ab7 --- /dev/null +++ b/board/esd/pmc440/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PMC440 + +config SYS_BOARD + default "pmc440" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "PMC440" + +endif diff --git a/board/esd/pmc440/MAINTAINERS b/board/esd/pmc440/MAINTAINERS new file mode 100644 index 0000000000..32fb9baeef --- /dev/null +++ b/board/esd/pmc440/MAINTAINERS @@ -0,0 +1,6 @@ +PMC440 BOARD +M: Matthias Fuchs +S: Maintained +F: board/esd/pmc440/ +F: include/configs/PMC440.h +F: configs/PMC440_defconfig diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile index 6d6690a221..708e9d138e 100644 --- a/board/esd/pmc440/Makefile +++ b/board/esd/pmc440/Makefile @@ -5,32 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o cmd_pmc440.o sdram.o fpga.o \ +obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \ ../common/cmd_loadpci.o - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +extra-y += init.o diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 3481e46436..40b135f2ba 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -347,16 +347,16 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } - base = gd->bd->bi_memsize; + base = (u32)gd->ram_size; #if defined(CONFIG_LOGBUFFER) base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; #endif /* - * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE + * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE */ param = base - (pram << 10); printf("PARAM: @%08x\n", param); - debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base); + debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base); /* clear entire PA ram */ memset((void*)param, 0, (pram << 10)); diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index b7b62dd94d..f876da855b 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define USE_SP_CODE #ifdef USE_SP_CODE -Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = { +xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_init_fn, @@ -36,7 +36,7 @@ Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = { fpga_post_config_fn, }; #else -Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = { +xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, @@ -47,7 +47,7 @@ Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = { }; #endif -Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = { +xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = { ngcc_fpga_pre_config_fn, ngcc_fpga_pgm_fn, ngcc_fpga_clk_fn, @@ -57,7 +57,7 @@ Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = { ngcc_fpga_post_config_fn }; -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc fpga[CONFIG_FPGA_COUNT] = { XILINX_XC3S1200E_DESC( #ifdef USE_SP_CODE slave_parallel, diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index cc8030b5e5..1f26fad147 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -27,11 +27,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) -#else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) -#endif /* TLB entries for DDR2 SDRAM are generated dynamically */ @@ -71,31 +67,3 @@ tlbtab: /* TODO: what about high IO space */ tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 549b3b73ce..15c3151b84 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -12,7 +12,6 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include #include #include @@ -27,20 +26,21 @@ #endif #include #include +#include #include "fpga.h" #include "pmc440.h" DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; extern void __ft_board_setup(void *blob, bd_t *bd); ulong flash_get_size(ulong base, int banknum); -int pci_is_66mhz(void); +static int pci_is_66mhz(void); int is_monarch(void); -int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); +static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt); struct serial_device *default_serial_console(void) { @@ -57,23 +57,24 @@ struct serial_device *default_serial_console(void) if (((val & 0xf0000000) >> 29) != 7) return &eserial2_device; - ulong scratchreg = in_be32((void*)GPIO0_ISR3L); + ulong scratchreg = in_be32((void *)GPIO0_ISR3L); if (!(scratchreg & 0x80)) { /* mark scratchreg valid */ scratchreg = (scratchreg & 0xffffff00) | 0x80; + i2c_init_all(); + i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4); if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { scratchreg |= buf[2]; /* bringup delay for console */ - for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) { + for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++) udelay(1000); - } } else scratchreg |= 0x01; - out_be32((void*)GPIO0_ISR3L, scratchreg); + out_be32((void *)GPIO0_ISR3L, scratchreg); } if (scratchreg & 0x01) @@ -92,10 +93,7 @@ int board_early_init_f(void) mtdcr(EBC0_CFGADDR, EBC0_CFG); mtdcr(EBC0_CFGDATA, 0xf8400000); - /* - * Setup the GPIO pins - * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file - */ + /* Setup the GPIO pins */ out_be32((void *)GPIO0_OR, 0x40000102); out_be32((void *)GPIO0_TCR, 0x4c90011f); out_be32((void *)GPIO0_OSRL, 0x28051400); @@ -228,19 +226,11 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(EBC0_CFGADDR, PB2CR); -#else mtdcr(EBC0_CFGADDR, PB0CR); -#endif pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(EBC0_CFGADDR, PB2CR); -#else mtdcr(EBC0_CFGADDR, PB0CR); -#endif mtdcr(EBC0_CFGDATA, pbcr); /* @@ -266,7 +256,7 @@ int misc_init_r(void) * USB suff... */ if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){ + !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB2D0CR, usb2d0cr); @@ -333,16 +323,16 @@ int misc_init_r(void) mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000); - if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { /* enable power on USB socket */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); } printf("USB: Host\n"); } else if ((strcmp(act, "dev") == 0) || - (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; @@ -421,30 +411,31 @@ int misc_init_r(void) #endif /* turn off POST LED */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N); + out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N); /* turn on RUN LED */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N); return 0; } int is_monarch(void) { - if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH) + if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH) return 0; return 1; } -int pci_is_66mhz(void) +static int pci_is_66mhz(void) { - if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN) + if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN) return 1; return 0; } -int board_revision(void) +static int board_revision(void) { - return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); + return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); } int checkboard(void) @@ -502,7 +493,7 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ /* and enable region */ @@ -539,7 +530,8 @@ void pci_target_init(struct pci_controller *hose) if (is_monarch()) { /* BAR2: map FPGA registers behind system memory at 1GB */ - pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008); + pci_hose_write_config_dword(hose, 0, + PCI_BASE_ADDRESS_2, 0x40000008); } /* @@ -569,10 +561,10 @@ void pci_target_init(struct pci_controller *hose) CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); /* PCI configuration done: release ERREADY */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY); - out_be32((void*)GPIO1_TCR, - in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY); + out_be32((void *)GPIO1_TCR, + in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY); } else { /* Program the board's subsystem id/classcode */ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, @@ -602,14 +594,14 @@ void pci_master_init(struct pci_controller *hose) static void wait_for_pci_ready(void) { - if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) { + if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) { printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); while (1) { if (ctrlc()) { puts("abort\n"); break; } - if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) { + if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) { printf("done\n"); break; } @@ -648,34 +640,73 @@ int is_pci_host(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ #ifdef CONFIG_RESET_PHY_R -void reset_phy(void) +static int pmc440_setup_vsc8601(char *devname, int phy_addr, + unsigned short behavior, unsigned short method) { - char *s; - unsigned short val_method, val_behavior; + /* adjust LED behavior */ + if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) { + printf("Phy%d: register write access failed\n", phy_addr); + return -1; + } - /* special LED setup for NGCC/CANDES */ - if ((s = getenv("bd_type")) && - ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { - val_method = 0x0e0a; - val_behavior = 0x0cf2; - } else { - /* PMC440 standard type */ - val_method = 0x0e10; - val_behavior = 0x0cf0; + miiphy_write(devname, phy_addr, 0x11, 0x0010); + miiphy_write(devname, phy_addr, 0x11, behavior); + miiphy_write(devname, phy_addr, 0x10, method); + miiphy_write(devname, phy_addr, 0x1f, 0x0000); + + return 0; +} + +static int pmc440_setup_ksz9031(char *devname, int phy_addr) +{ + unsigned short id1, id2; + + if (miiphy_read(devname, phy_addr, 2, &id1) || + miiphy_read(devname, phy_addr, 3, &id2)) { + printf("Phy%d: cannot read id\n", phy_addr); + return -1; } - if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); + if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) { + printf("Phy%d: unexpected id\n", phy_addr); + return -1; } - if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); + /* MMD 2.08: adjust tx_clk pad skew */ + miiphy_write(devname, phy_addr, 0x0d, 2); + miiphy_write(devname, phy_addr, 0x0e, 8); + miiphy_write(devname, phy_addr, 0x0d, 0x4002); + miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5)); + + return 0; +} + +void reset_phy(void) +{ + char *s; + unsigned short val_method, val_behavior; + + if (gd->board_type < 4) { + /* special LED setup for NGCC/CANDES */ + s = getenv("bd_type"); + if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { + val_method = 0x0e0a; + val_behavior = 0x0cf2; + } else { + /* PMC440 standard type */ + val_method = 0x0e10; + val_behavior = 0x0cf0; + } + + /* boards up to rev. 1.3 use Vitesse VSC8601 phys */ + pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR, + val_method, val_behavior); + pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR, + val_method, val_behavior); + } else { + /* rev. 1.4 uses a Micrel KSZ9031 */ + pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR); + pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR); } } #endif @@ -736,7 +767,6 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, * We must write the address again when changing pages * because the address counter only increments within a page. */ - while (offset < end) { unsigned alen, len; unsigned maxlen; @@ -778,8 +808,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, return rcode; } -int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) +static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt) { unsigned end = offset + cnt; unsigned blk_off; @@ -821,16 +851,16 @@ int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, } #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) -int usb_board_init(void) +int board_usb_init(int index, enum usb_init_type init) { char *act = getenv("usbact"); int i; if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) + !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) /* enable power on USB socket */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); for (i=0; i<1000; i++) udelay(1000); @@ -841,19 +871,18 @@ int usb_board_init(void) int usb_board_stop(void) { /* disable power on USB socket */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N); return 0; } -int usb_board_init_fail(void) +int board_usb_cleanup(int index, enum usb_init_type init) { - usb_board_stop(); - return 0; + return usb_board_stop(); } #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -866,9 +895,11 @@ void ft_board_setup(void *blob, bd_t *bd) rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status", "disabled", sizeof("disabled"), 1); if (rc) { - printf("Unable to update property status in PCI node, err=%s\n", - fdt_strerror(rc)); + printf("Unable to update property status in PCI node, "); + printf("err=%s\n", fdt_strerror(rc)); } } + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds deleted file mode 100644 index bd801ccdc2..0000000000 --- a/board/esd/pmc440/u-boot-nand.lds +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - - /* Align to next NAND block */ - . = ALIGN(0x4000); - common/env_embedded.o (.ppcenv) - /* Keep some space here for redundant env and potential bad env blocks */ - . = ALIGN(0x10000); - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/tasreg/Makefile b/board/esd/tasreg/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/esd/tasreg/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/tasreg/config.mk b/board/esd/tasreg/config.mk deleted file mode 100644 index 40f7570c21..0000000000 --- a/board/esd/tasreg/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffc00000 diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c deleted file mode 100644 index 713888114f..0000000000 --- a/board/esd/tasreg/flash.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -/*#include */ -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include - - -/* Prototypes */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); - - -#if 0 -#define FPGA_DEBUG -#endif - -/* predefine these here for FPGA programming (before including fpga.c) */ -#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data) -#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE) -#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT) -#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */ -#define out32(a,b) /* nothing to do (gpio already configured) */ - - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int checkboard (void) { - ulong val; - uchar val8; - - puts ("Board: "); - puts("esd TASREG"); - val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; - printf(" (Switch=%1X)\n", val8); - - /* - * Set LED on - */ - val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED; - mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ - - return 0; -}; - - -phys_size_t initdram (int board_type) { - unsigned long junk = 0xa5a59696; - - /* - * Note: - * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 - */ - -#ifdef CONFIG_SYS_FAST_CLK - /* - * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 - */ - mbar_writeShort(MCFSIM_DCR, 0x8239); -#elif CONFIG_SYS_PLL_BYPASS - /* - * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 - */ - mbar_writeShort(MCFSIM_DCR, 0x8202); -#else - /* - * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) - */ - mbar_writeShort(MCFSIM_DCR, 0x8222); -#endif - - /* - * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), - * PM=1 (continuous page mode) - */ - - /* RE=0 (keep auto-refresh disabled while setting up registers) */ - mbar_writeLong(MCFSIM_DACR0, 0x00003324); - - /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ - mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); - - /** Precharge sequence **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ - out_be32((void *)0, junk); /* write to a memory location to init. precharge */ - udelay(0x10); /* Allow several Precharge cycles */ - - /** Refresh Sequence **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ - udelay(0x7d0); /* Allow gobs of refresh cycles */ - - /** Mode Register initialization **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ - out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */ - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - - -int testdram (void) { - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} - - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - uchar buf[8]; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * - */ - buf[0] = 0x00; - buf[1] = 0x32; - buf[2] = 0x3f; - i2c_write(0x38, 0, 0, buf, 3); - - return (0); -} - - -#if 1 /* test-only: board specific test commands */ -int i2c_probe(uchar addr); - -/* - */ -int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - - if (argc < 2) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - - printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr); - - for (;;) { - i2c_probe(addr); - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - return 0; -} -U_BOOT_CMD( - iploop, 2, 1, do_iploop, - "i2c probe loop ", - "" -); - -/* - */ -int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uchar buf[8]; - - out_be16((void *)0xe0000000, 0x4000); - - udelay(5000); /* wait for 5ms */ - - buf[0] = 0x10; - buf[1] = 0x07; - buf[2] = 0x03; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x01; - buf[2] = 0x80; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x02; - buf[2] = 0x03; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x03; - buf[2] = 0x29; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x04; - buf[2] = 0x00; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x05; - buf[2] = 0x00; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x07; - buf[2] = 0x02; - i2c_write(0x10, 0, 0, buf, 3); - - return 0; -} -U_BOOT_CMD( - codec, 1, 1, do_codec, - "Enable codec", - "" -); - -/* - */ -int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - ulong instr; - ulong cntrl; - ulong data; - uchar buf[8]; - - if (argc < 5) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - instr = simple_strtol (argv[2], NULL, 16); - cntrl = simple_strtol (argv[3], NULL, 16); - data = simple_strtol (argv[4], NULL, 16); - - buf[0] = (uchar)instr; - buf[1] = (uchar)cntrl; - buf[2] = (uchar)data; - i2c_write(addr, 0, 0, buf, 3); - - return 0; -} -U_BOOT_CMD( - saa, 5, 1, do_saa, - "Write to SAA1064 ", - "" -); - -/* - */ -int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - ulong data0; - ulong data1; - ulong data2; - ulong data3; - uchar buf[8]; - int cnt; - - if (argc < 3) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - cnt = simple_strtol (argv[2], NULL, 16); - data0 = simple_strtol (argv[3], NULL, 16); - data1 = simple_strtol (argv[4], NULL, 16); - data2 = simple_strtol (argv[5], NULL, 16); - data3 = simple_strtol (argv[6], NULL, 16); - - printf("Writing %d bytes to device %lx!\n", cnt, addr); - buf[0] = (uchar)data0; - buf[1] = (uchar)data1; - buf[2] = (uchar)data2; - buf[3] = (uchar)data3; - i2c_write(addr, 0, 0, buf, cnt); - - return 0; -} -U_BOOT_CMD( - iwrite, 6, 1, do_iwrite, - "Write n bytes to I2C-device", - "addr cnt data0 ... datan" -); - -/* - */ -int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - ulong cnt; - uchar buf[32]; - int i; - - if (argc < 3) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - cnt = simple_strtol (argv[2], NULL, 16); - - i2c_read(addr, 0, 0, buf, cnt); - printf("I2C Data:"); - for (i=0; i ", - "" -); - -/* - */ -int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - uchar buf[32]; - int cnt; - - if (argc < 2) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - cnt = 1; - - printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr); - - for (;;) { - i2c_read(addr, 0, 0, buf, cnt); - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(3000); - } - - return 0; -} -U_BOOT_CMD( - ireadl, 2, 1, do_ireadl, - "Read-loop from I2C ", - "" -); -#endif diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds deleted file mode 100644 index 7f9e41c6d1..0000000000 --- a/board/esd/tasreg/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig new file mode 100644 index 0000000000..b8d9432dcc --- /dev/null +++ b/board/esd/vme8349/Kconfig @@ -0,0 +1,12 @@ +if TARGET_VME8349 + +config SYS_BOARD + default "vme8349" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "vme8349" + +endif diff --git a/board/esd/vme8349/MAINTAINERS b/board/esd/vme8349/MAINTAINERS new file mode 100644 index 0000000000..a88ba13c30 --- /dev/null +++ b/board/esd/vme8349/MAINTAINERS @@ -0,0 +1,7 @@ +VME8349 BOARD +M: Reinhard Arlt +S: Maintained +F: board/esd/vme8349/ +F: include/configs/vme8349.h +F: configs/caddy2_defconfig +F: configs/vme8349_defconfig diff --git a/board/esd/vme8349/Makefile b/board/esd/vme8349/Makefile index 4dd47b7cdc..fa11d5d108 100644 --- a/board/esd/vme8349/Makefile +++ b/board/esd/vme8349/Makefile @@ -7,26 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o caddy.o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += vme8349.o caddy.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index 01365dcbd3..f8f1834b59 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -74,13 +74,15 @@ int board_eth_init(bd_t *bis) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile deleted file mode 100644 index 17dd09783b..0000000000 --- a/board/esd/voh405/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c deleted file mode 100644 index 23e81642e0..0000000000 --- a/board/esd/voh405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* logo bitmap data - gzip compressed and generated by bin2c */ -unsigned char logo_bmp_320[] = -{ -#include "logo_320_240_4bpp.c" -}; - -unsigned char logo_bmp_640[] = -{ -#include "logo_640_480_24bpp.c" -}; - - -/* - * include common lcd code (for esd boards) - */ -#include "../common/lcd.c" - -#include "../common/s1d13704_320_240_4bpp.h" -#include "../common/s1d13806_320_240_4bpp.h" -#include "../common/s1d13806_640_480_16bpp.h" - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - unsigned short *lcd_contrast = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4); - unsigned short *lcd_backlight = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - char *str; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_INIT pin - */ - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */ - udelay(1000); /* wait 1ms */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */ - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Set NAND-FLASH GPIO signals to default - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); - - /* - * Setup EEPROM write protection - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8(duart0_mcr, 0x08); - out_8(duart1_mcr, 0x08); - - /* - * Init lcd interface and display logo - */ - str = getenv("bd_type"); - if (strcmp(str, "voh405_bw") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - } else if (strcmp(str, "voh405_bwbw") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - lcd_setup(1, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_320_240_4bpp, - sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - } else if (strcmp(str, "voh405_bwc") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - lcd_setup(1, 0); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp_640, sizeof(logo_bmp_640)); - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } - - /* - * Set invert bit in small lcd controller - */ - out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2), - in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01); - - /* - * Set default contrast voltage on epson vga controller - */ - out_be16(lcd_contrast, 0x4646); - - /* - * Enable backlight - */ - out_be16(lcd_backlight, 0xffff); - - /* - * Enable external I2C bus - */ - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming VOH405"); - } else { - puts(str); - } - - if (getenv_f("bd_type", str, sizeof(str)) != -1) { - printf(" (%s)", str); - } else { - puts(" (Missing bd_type!)"); - } - - putc ('\n'); - - return 0; -} - -#ifdef CONFIG_IDE_RESET -#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL) -void ide_set_reset(int on) -{ - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - out_be16((void *)FPGA_MODE, - in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - out_be16((void *)FPGA_MODE, - in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET); - } -} -#endif /* CONFIG_IDE_RESET */ - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/vom405/Kconfig b/board/esd/vom405/Kconfig new file mode 100644 index 0000000000..ecdf8c9fea --- /dev/null +++ b/board/esd/vom405/Kconfig @@ -0,0 +1,12 @@ +if TARGET_VOM405 + +config SYS_BOARD + default "vom405" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "VOM405" + +endif diff --git a/board/esd/vom405/MAINTAINERS b/board/esd/vom405/MAINTAINERS new file mode 100644 index 0000000000..385f60a3a3 --- /dev/null +++ b/board/esd/vom405/MAINTAINERS @@ -0,0 +1,6 @@ +VOM405 BOARD +M: Matthias Fuchs +S: Maintained +F: board/esd/vom405/ +F: include/configs/VOM405.h +F: configs/VOM405_defconfig diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile index 0fd6fe53cb..7cf5c0224c 100644 --- a/board/esd/vom405/Makefile +++ b/board/esd/vom405/Makefile @@ -5,32 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif - -LIB = $(obj)lib$(BOARD).o - # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = vom405.o flash.o ../common/misc.o $(CPLD) diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile deleted file mode 100644 index 17dd09783b..0000000000 --- a/board/esd/wuh405/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c deleted file mode 100644 index 23e81642e0..0000000000 --- a/board/esd/wuh405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); - udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); - udelay(1000); /* wait 1ms */ - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8((void *)(DUART0_BA + 4), 0x08); - out_8((void *)(DUART1_BA + 4), 0x08); - out_8((void *)(DUART2_BA + 4), 0x08); - out_8((void *)(DUART3_BA + 4), 0x08); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming WUH405"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} diff --git a/board/esg/ima3-mx53/Kconfig b/board/esg/ima3-mx53/Kconfig new file mode 100644 index 0000000000..d73238f9a9 --- /dev/null +++ b/board/esg/ima3-mx53/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMA3_MX53 + +config SYS_BOARD + default "ima3-mx53" + +config SYS_VENDOR + default "esg" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "ima3-mx53" + +endif diff --git a/board/esg/ima3-mx53/MAINTAINERS b/board/esg/ima3-mx53/MAINTAINERS new file mode 100644 index 0000000000..96de0815c7 --- /dev/null +++ b/board/esg/ima3-mx53/MAINTAINERS @@ -0,0 +1,6 @@ +IMA3-MX53 BOARD +#M: - +S: Maintained +F: board/esg/ima3-mx53/ +F: include/configs/ima3-mx53.h +F: configs/ima3-mx53_defconfig diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile index f2cb873913..afb8925c74 100644 --- a/board/esg/ima3-mx53/Makefile +++ b/board/esg/ima3-mx53/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ima3-mx53.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ima3-mx53.o diff --git a/board/espt/Kconfig b/board/espt/Kconfig new file mode 100644 index 0000000000..0294926cf5 --- /dev/null +++ b/board/espt/Kconfig @@ -0,0 +1,9 @@ +if TARGET_ESPT + +config SYS_BOARD + default "espt" + +config SYS_CONFIG_NAME + default "espt" + +endif diff --git a/board/espt/MAINTAINERS b/board/espt/MAINTAINERS new file mode 100644 index 0000000000..fdbbc3eb45 --- /dev/null +++ b/board/espt/MAINTAINERS @@ -0,0 +1,6 @@ +ESPT BOARD +#M: - +S: Maintained +F: board/espt/ +F: include/configs/espt.h +F: configs/espt_defconfig diff --git a/board/espt/Makefile b/board/espt/Makefile index 107e544774..8a8a2c992b 100644 --- a/board/espt/Makefile +++ b/board/espt/Makefile @@ -7,25 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := espt.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := espt.o +obj-y += lowlevel_init.o diff --git a/board/esteem192e/Makefile b/board/esteem192e/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/esteem192e/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c deleted file mode 100644 index b54c61412a..0000000000 --- a/board/esteem192e/esteem192e.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Modified By Conn Clark to work with Esteem 192E 7/31/00 - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - * - * active, NOP, read, precharge, NOP */ - 0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00, - 0x11FFCC05, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * NOP, Program - */ - 0x0F0A8C34, 0x1F354C37, /* last */ - - _NOT_USED_, /* Not used */ - - /* - * Burst Read. (Offset 8 in UPMA RAM) - * active, NOP, read, NOP, NOP, NOP, NOP, NOP */ - 0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00, - 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - * active, NOP, write, NOP, precharge, NOP */ - 0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04, - 0x0FF74C04, 0x1FFFCC05, /* last */ - _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - * active, NOP, write, NOP, NOP, NOP, NOP, NOP */ - 0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00, - 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - * precharge, NOP, auto_ref, NOP, NOP, NOP */ - 0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, - 0x0FFFCCB4, 0x1FFFCC35, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x0FFB8C00, 0x1FF74C03, /* last */ - _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: Esteem 192E\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1; - - /* - * Explain frequency of refresh here - */ - - memctl->memc_mptpr = 0x0200; /* divide by 32 */ - - memctl->memc_mamr = 0x18003112; /*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */ - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Map cs 2 and 3 to the SDRAM banks 0 and 1 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; /* not defined yet */ - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - - /* perform SDRAM initializsation sequence */ - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */ - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - - memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */ - memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */ - -/* printf ("banks 0 and 1 are programed\n"); */ - - /* - * Check Bank 0 Memory Size for re-configuration - * - */ - size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1); - -/* printf ("bank 1 size %u\n",size_b1); */ - - if (size_b1 == 0) { - /* - * Adjust refresh rate if bank 0 isn't stuffed - */ - memctl->memc_mptpr = 0x0400; /* divide by 64 */ - memctl->memc_br3 &= 0x0FFFFFFFE; - - /* - * Adjust OR2 for size of bank 0 - */ - memctl->memc_or2 |= 7 * size_b0; - } else { - if (size_b0 < size_b1) { - memctl->memc_br2 &= 0x00007FFE; - memctl->memc_br3 &= 0x00007FFF; - - /* - * Adjust OR3 for size of bank 1 - */ - memctl->memc_or3 |= 15 * size_b1; - - /* - * Adjust OR2 for size of bank 0 - */ - memctl->memc_or2 |= 15 * size_b0; - memctl->memc_br2 += (size_b1 + 1); - } else { - memctl->memc_br3 &= 0x00007FFE; - - /* - * Adjust OR2 for size of bank 0 - */ - memctl->memc_or2 |= 15 * size_b0; - - /* - * Adjust OR3 for size of bank 1 - */ - memctl->memc_or3 |= 15 * size_b1; - memctl->memc_br3 += (size_b0 + 1); - } - } - - /* before leaving set all unused i/o pins to outputs */ - - /* - * --*Unused Pin List*-- - * - * group/port bit number - * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx - * PA 5,7,8,9,14,15 - * PB 22,23,31 - * PC 4,5,6,7,10,11,12,13,14,15 - * PD 5,6,7 - * - */ - - /* - * --*Pin Used for I/O List*-- - * - * port input bit number output bit number either - * PB 18,26,27 - * PD 3,4 8,9,10,11,12,13,14,15 - * - */ - - immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */ - immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */ - immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */ - immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */ - - immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */ - immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */ - immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */ - immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */ - - immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */ - immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */ - immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */ - immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */ - - immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */ - immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */ - immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */ - immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */ - - return (size_b0 + size_b1); -} diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c deleted file mode 100644 index a121104ca8..0000000000 --- a/board/esteem192e/flash.c +++ /dev/null @@ -1,1119 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#ifdef CONFIG_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xFFFF -#else -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -/*----------------------------------------------------------------------- - * Functions - */ - -ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info); - -#ifndef CONFIG_FLASH_16BIT -static int write_word (flash_info_t * info, ulong dest, ulong data); -#else -static int write_short (flash_info_t * info, ulong dest, ushort data); -#endif -/*int flash_write (uchar *, ulong, ulong); */ -/*flash_info_t *addr2info (ulong); */ - -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size ((volatile FLASH_WORD_SIZE *) - FLASH_BASE0_PRELIM, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20); - } - - size_b1 = - flash_get_size ((volatile FLASH_WORD_SIZE *) - FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1 << 20, size_b0, size_b0 << 20); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = CONFIG_SYS_FLASH_BASE | 0x00000801; /* (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */ - - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = - CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = - (CONFIG_SYS_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK); - /*((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; */ - - /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size ((volatile FLASH_WORD_SIZE - *) (CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - - 1, &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start adress table */ - if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x000E0000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00070000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - - } else { - - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } - - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - uchar *boottype; - uchar botboot[] = ", bottom boot sect)\n"; - uchar topboot[] = ", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - if (info->flash_id & 0x0001) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit%s", boottype); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit%s", boottype); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit%s", boottype); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit%s", boottype); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit%s", boottype); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit%s", boottype); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit%s", boottype); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit%s", boottype); - break; - case FLASH_INTEL800B: - printf ("INTEL28F800B (8 Mbit%s", boottype); - break; - case FLASH_INTEL800T: - printf ("INTEL28F800T (8 Mbit%s", boottype); - break; - case FLASH_INTEL160B: - printf ("INTEL28F160B (16 Mbit%s", boottype); - break; - case FLASH_INTEL160T: - printf ("INTEL28F160T (16 Mbit%s", boottype); - break; - case FLASH_INTEL320B: - printf ("INTEL28F320B (32 Mbit%s", boottype); - break; - case FLASH_INTEL320T: - printf ("INTEL28F320T (32 Mbit%s", boottype); - break; - -#if 0 /* enable when devices are available */ - - case FLASH_INTEL640B: - printf ("INTEL28F640B (64 Mbit%s", boottype); - break; - case FLASH_INTEL640T: - printf ("INTEL28F640T (64 Mbit%s", boottype); - break; -#endif - - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) -{ - short i; - ulong base = (ulong) addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - -#ifndef CONFIG_FLASH_16BIT - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if (addr[0x0000] != 0x00890089) { - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x0089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x0090; - - if (addr[0x0000] != 0x0089) { - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0090; -#endif - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - - } - - value = addr[1]; /* device ID */ - - switch (value) { - - case (AMD_ID_LV400T & FLASH_ID_MASK): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & FLASH_ID_MASK): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & FLASH_ID_MASK): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & FLASH_ID_MASK): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & FLASH_ID_MASK): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case (INTEL_ID_28F800B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800T; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F800B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F160B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 /* enable when devices are available */ - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start adress table */ - if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x000E0000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00070000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - - } else { - - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *) (info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) { - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - - volatile FLASH_WORD_SIZE *addr = - (volatile FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect, barf; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - ((info->flash_id > FLASH_AMD_COMP) && - ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - if (info->flash_id < FLASH_AMD_COMP) { -#ifndef CONFIG_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; -#endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); - while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != - (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; -#ifndef CONFIG_FLASH_16BIT - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while (!(addr[0] & 0x00800080)); /* wait for error or finish */ - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } - } -#else - addr = (vu_short *) (info->start[sect]); - addr[0] = 0x0020; - addr[0] = 0x00D0; - while (!(addr[0] & 0x0080)); /* wait for error or finish */ - if (addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if (barf) { - printf ("\nFlash error in sector at %lx\n", (unsigned long) addr); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if ((barf & 0x0030) == 0x0030) - printf ("Command Sequence error.\n"); - if ((barf & 0x0030) == 0x0020) - printf ("Block Erase error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - rcode = 1; - } else - printf ("."); - l_sect = sect; - } - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - - } - - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ -#ifndef CONFIG_FLASH_16BIT - ulong cp, wp, data; - int l; -#else - ulong cp, wp; - ushort data; -#endif - int i, rc; - -#ifndef CONFIG_FLASH_16BIT - - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); - -#else - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ -/* l = 0; used for debuging */ - while (cnt >= 2) { - data = 0; - for (i = 0; i < 2; ++i) { - data = (data << 8) | *src++; - } - -/* if(!l){ - printf("%x",data); - l = 1; - } used for debuging */ - - if ((rc = write_short (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_short (info, wp, data)); - - -#endif -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifndef CONFIG_FLASH_16BIT -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) (info->start[0]); - ulong start, barf; - int flag; - - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - if (info->flash_id > FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - *((vu_long *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - - if (info->flash_id > FLASH_AMD_COMP) { - - while ((*((vu_long *) dest) & 0x00800080) != - (data & 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - - while (!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } - printf ("\nFlash write error at address %lx\n", (unsigned long) dest); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if (barf & 0x0010) - printf ("Programming error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - return (2); - } - - - } - - return (0); - - } - -#else - -static int write_short (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) (info->start[0]); - ulong start, barf; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *) dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - /* intel stuff */ - while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - - if (addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf ("\nFlash write error at address %lx\n", - (unsigned long) dest); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if (barf & 0x0010) - printf ("Programming error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - return (2); - } - *addr = 0x00B0; - *addr = 0x0070; - while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - *addr = 0x00FF; - } - return (0); -} - -#endif -/*-----------------------------------------------------------------------*/ diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds deleted file mode 100644 index 87642d6b40..0000000000 --- a/board/esteem192e/u-boot.lds +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - net/libnet.o (.text*) - board/esteem192e/libesteem192e.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/etin/debris/Makefile b/board/etin/debris/Makefile deleted file mode 100644 index d7da042c05..0000000000 --- a/board/etin/debris/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o phantom.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c deleted file mode 100644 index 0308fef6cf..0000000000 --- a/board/etin/debris/debris.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2000 - * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Debris " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " ##Test not implemented yet##\n"); - return 0; -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -phys_size_t initdram (int board_type) -{ - int m, row, col, bank, i; - unsigned long start, end; - uint32_t mccr1; - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; - uint8_t mber = 0; - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */ - m = i2c_reg_read (0x50, 5); /* # of physical banks */ - row = i2c_reg_read (0x50, 3); /* # of rows */ - col = i2c_reg_read (0x50, 4); /* # of columns */ - bank = i2c_reg_read (0x50, 17); /* # of logical banks */ - - CONFIG_READ_WORD(MCCR1, mccr1); - mccr1 &= 0xffff0000; - - start = CONFIG_SYS_SDRAM_BASE; - end = start + (1 << (col + row + 3) ) * bank - 1; - - for (i = 0; i < m; i++) { - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; - if (i < 4) { - msar1 |= ((start >> 20) & 0xff) << i * 8; - emsar1 |= ((start >> 28) & 0xff) << i * 8; - mear1 |= ((end >> 20) & 0xff) << i * 8; - emear1 |= ((end >> 28) & 0xff) << i * 8; - } else { - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; - } - mber |= 1 << i; - start += (1 << (col + row + 3) ) * bank; - end += (1 << (col + row + 3) ) * bank; - } - for (; i < 8; i++) { - if (i < 4) { - msar1 |= 0xff << i * 8; - emsar1 |= 0x30 << i * 8; - mear1 |= 0xff << i * 8; - emear1 |= 0x30 << i * 8; - } else { - msar2 |= 0xff << (i-4) * 8; - emsar2 |= 0x30 << (i-4) * 8; - mear2 |= 0xff << (i-4) * 8; - emear2 |= 0x30 << (i-4) * 8; - } - } - - CONFIG_WRITE_WORD(MCCR1, mccr1); - CONFIG_WRITE_WORD(MSAR1, msar1); - CONFIG_WRITE_WORD(EMSAR1, emsar1); - CONFIG_WRITE_WORD(MEAR1, mear1); - CONFIG_WRITE_WORD(EMEAR1, emear1); - CONFIG_WRITE_WORD(MSAR2, msar2); - CONFIG_WRITE_WORD(EMSAR2, emsar2); - CONFIG_WRITE_WORD(MEAR2, mear2); - CONFIG_WRITE_WORD(EMEAR2, emear2); - CONFIG_WRITE_BYTE(MBER, mber); - - return (1 << (col + row + 3) ) * bank * m; -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_debris_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_debris_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -void *nvram_read(void *dest, const long src, size_t count) -{ - volatile uchar *d = (volatile uchar*) dest; - volatile uchar *s = (volatile uchar*) src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } - return dest; -} - -void nvram_write(long dest, const void *src, size_t count) -{ - volatile uchar *d = (volatile uchar*)dest; - volatile uchar *s = (volatile uchar*)src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } -} - -int misc_init_r(void) -{ - uchar ethaddr[6]; - - if (eth_getenv_enetaddr("ethaddr", ethaddr)) - /* Write ethernet addr in NVRAM for VxWorks */ - nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS, - ethaddr, 6); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c deleted file mode 100644 index 9d22aa2bd7..0000000000 --- a/board/etin/debris/flash.c +++ /dev/null @@ -1,705 +0,0 @@ -/* - * board/eva/flash.c - * - * (C) Copyright 2002 - * Sangmoon Kim, Etin Systems, dogoil@etinsys.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t); -int (*write_dword)(flash_info_t*, ulong, uint64_t); - -typedef uint64_t cfi_word; - -#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr)) - -#define cfi_write(flash, val, addr) \ - move64((cfi_word*)&val, \ - (cfi_word*)(flash->start[0] + addr)) - -#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x))) - -static void write32(unsigned long addr, uint32_t value) -{ - *(volatile uint32_t*)(addr) = value; - asm volatile("sync"); -} - -static uint32_t read32(unsigned long addr) -{ - uint32_t value; - value = *(volatile uint32_t*)addr; - asm volatile("sync"); - return value; -} - -static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr) -{ - uint32_t base = flash->start[0]; - uint32_t val=(cmd << 16) | cmd; - addr <<= 3; - write32(base + addr, val); - return addr; -} - -static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr) -{ - uint32_t base = flash->start[0]; - addr <<= 3; - return (uint16_t)read32(base + addr); -} - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static void move64(uint64_t *src, uint64_t *dest) -{ - asm volatile("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -} - -static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data) -{ - unsigned long start; - cfi_word status = 0; - - status = cfi_read(flash, dest); - data &= status; - - cfi_cmd(flash, 0x40, 0); - cfi_write(flash, data, dest); - - udelay(10); - start = get_timer (0); - for(;;) { - status = cfi_read(flash, dest); - status &= CMD(0x80); - if(status == CMD(0x80)) - break; - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - cfi_cmd(flash, 0xff, 0); - return 1; - } - udelay(1); - } - cfi_cmd(flash, 0xff, 0); - - return 0; -} - -static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data) -{ - ulong start; - cfi_word status = 0; - - status = cfi_read(flash, dest); - if(status != CMD(0xffff)) return 2; - - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - cfi_cmd(flash, 0xa0, 0x555); - - cfi_write(flash, data, dest); - - udelay(10); - start = get_timer (0); - status = ~data; - while(status != data) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - status = cfi_read(flash, dest); - udelay(1); - } - return 0; -} - -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); -} - -int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - int i, s, l, rc; - cfi_word data; - uint8_t *t = (uint8_t*)&data; - unsigned long base = flash->start[0]; - uint32_t msr; - - if (flash->flash_id == FLASH_UNKNOWN) - return 4; - - if (cnt == 0) - return 0; - - addr -= base; - - msr = get_msr(); - set_msr(msr|MSR_FP); - - wp = (addr & ~7); /* get lower word aligned address */ - - if((addr-wp) != 0) { - data = cfi_read(flash, wp); - s = addr & 7; - l = ( cnt < (8-s) ) ? cnt : (8-s); - for(i = 0; i < l; i++) - t[s+i] = *src++; - if ((rc = write_dword(flash, wp, data)) != 0) - goto DONE; - wp += 8; - cnt -= l; - } - - while (cnt >= 8) { - for (i = 0; i < 8; i++) - t[i] = *src++; - if ((rc = write_dword(flash, wp, data)) != 0) - goto DONE; - wp += 8; - cnt -= 8; - } - - if (cnt == 0) { - rc = 0; - goto DONE; - } - - data = cfi_read(flash, wp); - for(i = 0; i < cnt; i++) - t[i] = *src++; - rc = write_dword(flash, wp, data); -DONE: - set_msr(msr); - return rc; -} - -static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect) -{ - int sa; - int flag; - ulong start, last, now; - cfi_word status; - - flag = disable_interrupts(); - - sa = (flash->start[sect] - flash->start[0]); - write32(flash->start[sect], 0x00200020); - write32(flash->start[sect], 0x00d000d0); - - if (flag) - enable_interrupts(); - - udelay(1000); - start = get_timer (0); - last = start; - - for (;;) { - status = cfi_read(flash, sa); - status &= CMD(0x80); - if (status == CMD(0x80)) - break; - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - cfi_cmd(flash, 0xff, 0); - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - if ((now - last) > 1000) { - serial_putc ('.'); - last = now; - } - udelay(10); - } - cfi_cmd(flash, 0xff, 0); - return ERR_OK; -} - -static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) -{ - int sect; - int rc = ERR_OK; - - for (sect = s_first; sect <= s_last; sect++) { - if (flash->protect[sect] == 0) { - rc = cfi_erase_oneblock(flash, sect); - if (rc != ERR_OK) break; - } - } - printf (" done\n"); - return rc; -} - -static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) -{ - int sect; - cfi_word status; - int sa = -1; - int flag; - ulong start, last, now; - - flag = disable_interrupts(); - - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - cfi_cmd(flash, 0x80, 0x555); - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - for ( sect = s_first; sect <= s_last; sect++) { - if (flash->protect[sect] == 0) { - sa = flash->start[sect] - flash->start[0]; - write32(flash->start[sect], 0x00300030); - } - } - if (flag) - enable_interrupts(); - - if (sa < 0) - goto DONE; - - udelay (1000); - start = get_timer (0); - last = start; - for(;;) { - status = cfi_read(flash, sa); - if (status == CMD(0xffff)) - break; - - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - if ((now - last) > 1000) { - serial_putc ('.'); - last = now; - } - udelay(10); - } -DONE: - cfi_cmd(flash, 0xf0, 0); - - printf (" done\n"); - - return ERR_OK; -} - -int flash_erase (flash_info_t *flash, int s_first, int s_last) -{ - int sect; - int prot; - - if ((s_first < 0) || (s_first > s_last)) { - if (flash->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return ERR_NOT_ERASED; - } - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return ERR_NOT_ERASED; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) - if (flash->protect[sect]) prot++; - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf ("\n"); - - return do_flash_erase(flash, s_first, s_last); -} - -struct jedec_flash_info { - const uint16_t mfr_id; - const uint16_t dev_id; - const char *name; - const int DevSize; - const int InterfaceDesc; - const int NumEraseRegions; - const ulong regions[4]; -}; - -#define ERASEINFO(size,blocks) (size<<8)|(blocks-1) - -#define SIZE_1MiB 20 -#define SIZE_2MiB 21 -#define SIZE_4MiB 22 - -static const struct jedec_flash_info jedec_table[] = { - { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV800T, - name: "AMD AM29LV800T", - DevSize: SIZE_1MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,15), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV800B, - name: "AMD AM29LV800B", - DevSize: SIZE_1MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,15), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV160T, - name: "AMD AM29LV160T", - DevSize: SIZE_2MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,31), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV160B, - name: "AMD AM29LV160B", - DevSize: SIZE_2MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x04000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x08000,1), - ERASEINFO(0x10000,31) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV320T, - name: "AMD AM29LV320T", - DevSize: SIZE_4MiB, - NumEraseRegions: 2, - regions: {ERASEINFO(0x10000,63), - ERASEINFO(0x02000,8) - } - - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV320B, - name: "AMD AM29LV320B", - DevSize: SIZE_4MiB, - NumEraseRegions: 2, - regions: {ERASEINFO(0x02000,8), - ERASEINFO(0x10000,63) - } - } -}; - -static ulong cfi_init(uint32_t base, flash_info_t *flash) -{ - int sector; - int block; - int block_count; - int offset = 0; - int reverse = 0; - int primary; - int mfr_id; - int dev_id; - - flash->start[0] = base; - cfi_cmd(flash, 0xF0, 0); - cfi_cmd(flash, 0x98, 0); - if ( !( cfi_read_query(flash, 0x10) == 'Q' && - cfi_read_query(flash, 0x11) == 'R' && - cfi_read_query(flash, 0x12) == 'Y' )) { - cfi_cmd(flash, 0xff, 0); - return 0; - } - - flash->size = 1 << cfi_read_query(flash, 0x27); - flash->size *= 4; - block_count = cfi_read_query(flash, 0x2c); - primary = cfi_read_query(flash, 0x15); - if ( cfi_read_query(flash, primary + 4) == 0x30) - reverse = (cfi_read_query(flash, 0x1) & 0x01); - else - reverse = (cfi_read_query(flash, primary+15) == 3); - - flash->sector_count = 0; - - for ( block = reverse ? block_count - 1 : 0; - reverse ? block >= 0 : block < block_count; - reverse ? block-- : block ++) { - int sector_size = - (cfi_read_query(flash, 0x2d + block*4+2) | - (cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8; - int sector_count = - (cfi_read_query(flash, 0x2d + block*4+0) | - (cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1; - for(sector = 0; sector < sector_count; sector++) { - flash->start[flash->sector_count++] = base + offset; - offset += sector_size * 4; - } - } - mfr_id = cfi_read_query(flash, 0x00); - dev_id = cfi_read_query(flash, 0x01); - - cfi_cmd(flash, 0xff, 0); - - flash->flash_id = (mfr_id << 16) | dev_id; - - for (sector = 0; sector < flash->sector_count; sector++) { - write32(flash->start[sector], 0x00600060); - write32(flash->start[sector], 0x00d000d0); - } - cfi_cmd(flash, 0xff, 0); - - for (sector = 0; sector < flash->sector_count; sector++) - flash->protect[sector] = 0; - - do_flash_erase = cfi_erase; - write_dword = cfi_write_dword; - - return flash->size; -} - -static ulong jedec_init(unsigned long base, flash_info_t *flash) -{ - int i; - int block, block_count; - int sector, offset; - int mfr_id, dev_id; - flash->start[0] = base; - cfi_cmd(flash, 0xF0, 0x000); - cfi_cmd(flash, 0xAA, 0x555); - cfi_cmd(flash, 0x55, 0x2AA); - cfi_cmd(flash, 0x90, 0x555); - mfr_id = cfi_read_query(flash, 0x000); - dev_id = cfi_read_query(flash, 0x0001); - cfi_cmd(flash, 0xf0, 0x000); - - for(i=0; iflash_id = (mfr_id << 16) | dev_id; - flash->size = 1 << jedec_table[0].DevSize; - flash->size *= 4; - block_count = jedec_table[i].NumEraseRegions; - offset = 0; - flash->sector_count = 0; - for (block = 0; block < block_count; block++) { - int sector_size = jedec_table[i].regions[block]; - int sector_count = (sector_size & 0xff) + 1; - sector_size >>= 8; - for (sector=0; sectorstart[flash->sector_count++] = - base + offset; - offset += sector_size * 4; - } - } - break; - } - } - - for (sector = 0; sector < flash->sector_count; sector++) - flash->protect[sector] = 0; - - do_flash_erase = jedec_erase; - write_dword = jedec_write_dword; - - return flash->size; -} - -inline void mtibat1u(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 530, %0" :: "r" (x)); -} - -inline void mtibat1l(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 531, %0" :: "r" (x)); -} - -inline void mtdbat1u(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 538, %0" :: "r" (x)); -} - -inline void mtdbat1l(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 539, %0" :: "r" (x)); -} - -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - unsigned int msr; - - /* BAT1 */ - CONFIG_WRITE_WORD(ERCR3, 0x0C00000C); - CONFIG_WRITE_WORD(ERCR4, 0x0800000C); - msr = get_msr(); - set_msr(msr & ~(MSR_IR | MSR_DR)); - mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - set_msr(msr); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) - flash_info[i].flash_id = FLASH_UNKNOWN; - size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]); - if (!size) - size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) - printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - - return size; -} - -void flash_print_info (flash_info_t *flash) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *p; - - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - flash_init(); - } - - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (((flash->flash_id) >> 16) & 0xff) { - case 0x01: - printf ("AMD "); - break; - case 0x04: - printf("FUJITSU "); - break; - case 0x20: - printf("STM "); - break; - case 0xBF: - printf("SST "); - break; - case 0x89: - case 0xB0: - printf("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch ((flash->flash_id) & 0xffff) { - case (uint16_t)AMD_ID_LV800T: - printf ("AM29LV800T\n"); - break; - case (uint16_t)AMD_ID_LV800B: - printf ("AM29LV800B\n"); - break; - case (uint16_t)AMD_ID_LV160T: - printf ("AM29LV160T\n"); - break; - case (uint16_t)AMD_ID_LV160B: - printf ("AM29LV160B\n"); - break; - case (uint16_t)AMD_ID_LV320T: - printf ("AM29LV320T\n"); - break; - case (uint16_t)AMD_ID_LV320B: - printf ("AM29LV320B\n"); - break; - case (uint16_t)INTEL_ID_28F800C3T: - printf ("28F800C3T\n"); - break; - case (uint16_t)INTEL_ID_28F800C3B: - printf ("28F800C3B\n"); - break; - case (uint16_t)INTEL_ID_28F160C3T: - printf ("28F160C3T\n"); - break; - case (uint16_t)INTEL_ID_28F160C3B: - printf ("28F160C3B\n"); - break; - case (uint16_t)INTEL_ID_28F320C3T: - printf ("28F320C3T\n"); - break; - case (uint16_t)INTEL_ID_28F320C3B: - printf ("28F320C3B\n"); - break; - case (uint16_t)INTEL_ID_28F640C3T: - printf ("28F640C3T\n"); - break; - case (uint16_t)INTEL_ID_28F640C3B: - printf ("28F640C3B\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (flash->size >= (1 << 20)) { - printf (" Size: %ld MB in %d Sectors\n", - flash->size >> 20, flash->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", - flash->size >> 10, flash->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i = 0; i < flash->sector_count; ++i) { - /* Check if whole sector is erased*/ - if (i != (flash->sector_count-1)) - size = flash->start[i+1] - flash->start[i]; - else - size = flash->start[0] + flash->size - flash->start[i]; - - erased = 1; - p = (volatile unsigned long *)flash->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - flash->protect[i] ? "RO " : " "); - } - printf ("\n"); -} diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c deleted file mode 100644 index 3d5aa14086..0000000000 --- a/board/etin/debris/phantom.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * board/eva/phantom.c - * - * Phantom RTC device driver for EVA - * - * Author: Sangmoon Kim - * dogoil@etinsys.com - * - * Copyright 2002 Etinsys Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_DATE) - -#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8) - -#define RTC_YEAR ( RTC_BASE + 7 ) -#define RTC_MONTH ( RTC_BASE + 6 ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 ) -#define RTC_HOURS ( RTC_BASE + 3 ) -#define RTC_MINUTES ( RTC_BASE + 2 ) -#define RTC_SECONDS ( RTC_BASE + 1 ) -#define RTC_CENTURY ( RTC_BASE + 0 ) - -#define RTC_CONTROLA RTC_CENTURY -#define RTC_CONTROLB RTC_SECONDS -#define RTC_CONTROLC RTC_DAY_OF_WEEK - -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 - -#define RTC_CB_OSC_DISABLE 0x80 - -#define RTC_CC_BATTERY_FLAG 0x80 -#define RTC_CC_FREQ_TEST 0x40 - - -static int phantom_flag = -1; -static int century_flag = -1; - -static uchar rtc_read(unsigned int addr) -{ - return *(volatile unsigned char *)(addr); -} - -static void rtc_write(unsigned int addr, uchar val) -{ - *(volatile unsigned char *)(addr) = val; -} - -static unsigned char phantom_rtc_sequence[] = { - 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c -}; - -static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8]) -{ - int i, j; - unsigned char v; - unsigned char save = rtc_read(addr); - - for (j = 0; j < 8; j++) { - v = phantom_rtc_sequence[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - for (j = 0; j < 8; j++) { - v = 0; - for (i = 0; i < 8; i++) { - if(rtc_read(addr) & 1) - v |= 1 << i; - } - rtc[j] = v; - } - rtc_write(addr, save); - return rtc; -} - -static void phantom_rtc_write(int addr, unsigned char rtc[8]) -{ - int i, j; - unsigned char v; - unsigned char save = rtc_read(addr); - for (j = 0; j < 8; j++) { - v = phantom_rtc_sequence[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - for (j = 0; j < 8; j++) { - v = rtc[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - rtc_write(addr, save); -} - -static int get_phantom_flag(void) -{ - int i; - unsigned char rtc[8]; - - phantom_rtc_read(RTC_BASE, rtc); - - for(i = 1; i < 8; i++) { - if (rtc[i] != rtc[0]) - return 1; - } - return 0; -} - -void rtc_reset(void) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) { - unsigned char rtc[8]; - phantom_rtc_read(RTC_BASE, rtc); - if(rtc[4] & 0x30) { - printf( "real-time-clock was stopped. Now starting...\n" ); - rtc[4] &= 0x07; - phantom_rtc_write(RTC_BASE, rtc); - } - } else { - uchar reg_a, reg_b, reg_c; - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); - - reg_c = rtc_read( RTC_CONTROLC ); - if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) - printf( "RTC battery low. Clock setting may not be reliable.\n"); - } -} - -static int get_century_flag(void) -{ - int flag = 0; - int bcd, century; - bcd = rtc_read( RTC_CENTURY ); - century = bcd2bin( bcd & 0x3F ); - rtc_write( RTC_CENTURY, bin2bcd(century+1)); - if (bcd == rtc_read( RTC_CENTURY )) - flag = 1; - rtc_write( RTC_CENTURY, bcd); - return flag; -} - -int rtc_get( struct rtc_time *tmp) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) - { - unsigned char rtc[8]; - - phantom_rtc_read(RTC_BASE, rtc); - - tmp->tm_sec = bcd2bin(rtc[1] & 0x7f); - tmp->tm_min = bcd2bin(rtc[2] & 0x7f); - tmp->tm_hour = bcd2bin(rtc[3] & 0x1f); - tmp->tm_wday = bcd2bin(rtc[4] & 0x7); - tmp->tm_mday = bcd2bin(rtc[5] & 0x3f); - tmp->tm_mon = bcd2bin(rtc[6] & 0x1f); - tmp->tm_year = bcd2bin(rtc[7]) + 1900; - tmp->tm_yday = 0; - tmp->tm_isdst = 0; - - if( (rtc[3] & 0x80) && (rtc[3] & 0x40) ) tmp->tm_hour += 12; - if (tmp->tm_year < 1970) tmp->tm_year += 100; - } else { - uchar sec, min, hour; - uchar mday, wday, mon, year; - - int century; - - uchar reg_a; - - if (century_flag < 0) - century_flag = get_century_flag(); - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - century = rtc_read( RTC_CENTURY ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - if (century_flag) { - tmp->tm_year = bcd2bin( year ) + - ( bcd2bin( century & 0x3F ) * 100 ); - } else { - tmp->tm_year = bcd2bin( year ) + 1900; - if (tmp->tm_year < 1970) tmp->tm_year += 100; - } - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - } - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) { - uint year; - unsigned char rtc[8]; - - year = tmp->tm_year; - year -= (year < 2000) ? 1900 : 2000; - - rtc[0] = bin2bcd(0); - rtc[1] = bin2bcd(tmp->tm_sec); - rtc[2] = bin2bcd(tmp->tm_min); - rtc[3] = bin2bcd(tmp->tm_hour); - rtc[4] = bin2bcd(tmp->tm_wday); - rtc[5] = bin2bcd(tmp->tm_mday); - rtc[6] = bin2bcd(tmp->tm_mon); - rtc[7] = bin2bcd(year); - - phantom_rtc_write(RTC_BASE, rtc); - } else { - uchar reg_a; - if (century_flag < 0) - century_flag = get_century_flag(); - - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year up into century and year in century */ - if (century_flag) { - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); - reg_a &= 0xc0; - reg_a |= bin2bcd( tmp->tm_year / 100 ); - } else { - rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year - - ((tmp->tm_year < 2000) ? 1900 : 2000))); - } - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - } - - return 0; -} - -#endif diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/etin/debris/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/etin/kvme080/Makefile b/board/etin/kvme080/Makefile deleted file mode 100644 index c0271d0d60..0000000000 --- a/board/etin/kvme080/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o multiverse.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c deleted file mode 100644 index baf4cbc4da..0000000000 --- a/board/etin/kvme080/kvme080.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2005 - * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -int checkboard(void) -{ - puts ("Board: KVME080\n"); - return 0; -} - -unsigned long setdram(int m, int row, int col, int bank) -{ - int i; - unsigned long start, end; - uint32_t mccr1; - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; - uint8_t mber = 0; - - CONFIG_READ_WORD(MCCR1, mccr1); - mccr1 &= 0xffff0000; - - start = CONFIG_SYS_SDRAM_BASE; - end = start + (1 << (col + row + 3) ) * bank - 1; - - for (i = 0; i < m; i++) { - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; - if (i < 4) { - msar1 |= ((start >> 20) & 0xff) << i * 8; - emsar1 |= ((start >> 28) & 0xff) << i * 8; - mear1 |= ((end >> 20) & 0xff) << i * 8; - emear1 |= ((end >> 28) & 0xff) << i * 8; - } else { - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; - } - mber |= 1 << i; - start += (1 << (col + row + 3) ) * bank; - end += (1 << (col + row + 3) ) * bank; - } - for (; i < 8; i++) { - if (i < 4) { - msar1 |= 0xff << i * 8; - emsar1 |= 0x30 << i * 8; - mear1 |= 0xff << i * 8; - emear1 |= 0x30 << i * 8; - } else { - msar2 |= 0xff << (i-4) * 8; - emsar2 |= 0x30 << (i-4) * 8; - mear2 |= 0xff << (i-4) * 8; - emear2 |= 0x30 << (i-4) * 8; - } - } - - CONFIG_WRITE_WORD(MCCR1, mccr1); - CONFIG_WRITE_WORD(MSAR1, msar1); - CONFIG_WRITE_WORD(EMSAR1, emsar1); - CONFIG_WRITE_WORD(MEAR1, mear1); - CONFIG_WRITE_WORD(EMEAR1, emear1); - CONFIG_WRITE_WORD(MSAR2, msar2); - CONFIG_WRITE_WORD(EMSAR2, emsar2); - CONFIG_WRITE_WORD(MEAR2, mear2); - CONFIG_WRITE_WORD(EMEAR2, emear2); - CONFIG_WRITE_BYTE(MBER, mber); - - return (1 << (col + row + 3) ) * bank * m; -} - -phys_size_t initdram(int board_type) -{ - unsigned int msr; - long int size = 0; - - msr = mfmsr(); - mtmsr(msr & ~(MSR_IR | MSR_DR)); - mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000); - mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000); - mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000); - mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000); - mtmsr(msr); - - if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000)) - size = 0x20000000; /* 512MB */ - else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000)) - size = 0x10000000; /* 256MB */ - else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000)) - size = 0x10000000; /* 256MB */ - else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000)) - size = 0x08000000; /* 128MB */ - else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000)) - size = 0x08000000; /* 128MB */ - else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000)) - size = 0x04000000; /* 64MB */ - - msr = mfmsr(); - mtmsr(msr & ~(MSR_IR | MSR_DR)); - mtspr(IBAT2L, CONFIG_SYS_IBAT2L); - mtspr(IBAT2U, CONFIG_SYS_IBAT2U); - mtspr(DBAT2L, CONFIG_SYS_DBAT2L); - mtspr(DBAT2U, CONFIG_SYS_DBAT2U); - mtmsr(msr); - - return size; -} - -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_early_init_f(void) -{ - *(volatile unsigned char *)(0xff080120) = 0xfb; - - return 0; -} - -int board_early_init_r(void) -{ - unsigned int msr; - - CONFIG_WRITE_WORD(ERCR1, 0x95ff8000); - CONFIG_WRITE_WORD(ERCR3, 0x0c00000e); - CONFIG_WRITE_WORD(ERCR4, 0x0800000e); - - msr = mfmsr(); - mtmsr(msr & ~(MSR_IR | MSR_DR)); - mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - mtmsr(msr); - - return 0; -} - -extern int multiverse_init(void); - -int misc_init_r(void) -{ - multiverse_init(); - return 0; -} - -void *nvram_read(void *dest, const long src, size_t count) -{ - volatile uchar *d = (volatile uchar*) dest; - volatile uchar *s = (volatile uchar*) src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } - return dest; -} - -void nvram_write(long dest, const void *src, size_t count) -{ - volatile uchar *d = (volatile uchar*)dest; - volatile uchar *s = (volatile uchar*)src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/etin/kvme080/multiverse.c b/board/etin/kvme080/multiverse.c deleted file mode 100644 index 2bcfe2ea04..0000000000 --- a/board/etin/kvme080/multiverse.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * multiverse.c - * - * VME driver for Multiverse - * - * Author : Sangmoon Kim - * dogoil@etinsys.com - * - * Copyright 2005 ETIN SYSTEMS Co.,Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include "multiverse.h" - -static unsigned long vme_asi_addr; -static unsigned long vme_iack_addr; -static unsigned long pci_reg_addr; -static unsigned long vme_reg_addr; - -int multiv_reset(unsigned long base) -{ - writeb(0x09, base + VME_SLAVE32_AM); - writeb(0x39, base + VME_SLAVE24_AM); - writeb(0x29, base + VME_SLAVE16_AM); - writeb(0x2f, base + VME_SLAVE_REG_AM); - writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A); - writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A); - writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A); -#ifdef A32_SLV_WINDOW - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff, - base + VME_SLAVE32_MASK); - writeb(0x01, base + VME_SLAVE32_EN); - } else { - writeb(0xff, base + VME_SLAVE32_MASK); - writeb(0x00, base + VME_SLAVE32_EN); - } -#else - writeb(0xff, base + VME_SLAVE32_MASK); - writeb(0x00, base + VME_SLAVE32_EN); -#endif -#ifdef A24_SLV_WINDOW - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff, - base + VME_SLAVE24_MASK); - writeb(0x01, base + VME_SLAVE24_EN); - } else { - writeb(0xff, base + VME_SLAVE24_MASK); - writeb(0x00, base + VME_SLAVE24_EN); - } -#else - writeb(0xff, base + VME_SLAVE24_MASK); - writeb(0x00, base + VME_SLAVE24_EN); -#endif -#ifdef A16_SLV_WINDOW - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff, - base + VME_SLAVE16_MASK); - writeb(0x01, base + VME_SLAVE16_EN); - } else { - writeb(0xff, base + VME_SLAVE16_MASK); - writeb(0x00, base + VME_SLAVE16_EN); - } -#else - writeb(0xff, base + VME_SLAVE16_MASK); - writeb(0x00, base + VME_SLAVE16_EN); -#endif -#ifdef REG_SLV_WINDOW - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff, - base + VME_SLAVE_REG_MASK); - writeb(0x01, base + VME_SLAVE_REG_EN); - } else { - writeb(0xf8, base + VME_SLAVE_REG_MASK); - } -#else - writeb(0xf8, base + VME_SLAVE_REG_MASK); -#endif - writeb(0x09, base + VME_MASTER32_AM); - writeb(0x39, base + VME_MASTER24_AM); - writeb(0x29, base + VME_MASTER16_AM); - writeb(0x2f, base + VME_MASTER_REG_AM); - writel(0x00000000, base + VME_RMW_ADRS); - writeb(0x00, base + VME_IRQ); - writeb(0x00, base + VME_INT_EN); - writel(0x00000000, base + VME_IRQ1_REG); - writel(0x00000000, base + VME_IRQ2_REG); - writel(0x00000000, base + VME_IRQ3_REG); - writel(0x00000000, base + VME_IRQ4_REG); - writel(0x00000000, base + VME_IRQ5_REG); - writel(0x00000000, base + VME_IRQ6_REG); - writel(0x00000000, base + VME_IRQ7_REG); - return 0; -} - -void multiv_auto_slot_id(unsigned long base) -{ - __maybe_unused unsigned int vector; - int slot_id = 1; - if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) { - *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe; - writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ); - writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL, - base + VME_CTRL); - while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL); - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - while (readb(base + VME_INT) & 0x04) { - vector = *(volatile unsigned int*) - (vme_iack_addr + VME_IACK2); - *(unsigned char*)(vme_asi_addr + 0x7ffff) - = (slot_id << 3) & 0xff; - slot_id ++; - if (slot_id > 31) - break; - } - } - } -} - -int multiverse_init(void) -{ - int i; - pci_dev_t pdev; - unsigned int bar[6]; - - pdev = pci_find_device(0x1895, 0x0001, 0); - - if (pdev == 0) - return -1; - - for (i = 0; i < 6; i++) - pci_read_config_dword (pdev, - PCI_BASE_ADDRESS_0 + i * 4, &bar[i]); - - pci_reg_addr = bar[0]; - vme_reg_addr = bar[1] + 0x00F00000; - vme_iack_addr = bar[1] + 0x00200000; - vme_asi_addr = bar[3]; - - pci_write_config_dword (pdev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - writel(0xFF000000, pci_reg_addr + P_TA1); - writel(0x04, pci_reg_addr + P_IMG_CTRL1); - writel(0xf0000000, pci_reg_addr + P_TA2); - writel(0x04, pci_reg_addr + P_IMG_CTRL2); - writel(0xF1000000, pci_reg_addr + P_TA3); - writel(0x04, pci_reg_addr + P_IMG_CTRL3); - writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5); - writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5); - writel(0x04, pci_reg_addr + P_IMG_CTRL5); - - writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1); - writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1); - writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1); - writel(0x04, pci_reg_addr + W_IMG_CTRL1); - - writel(0xF0000000, pci_reg_addr + W_BA2); - writel(0xFF000000, pci_reg_addr + W_AM2); - writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2); - writel(0x04, pci_reg_addr + W_IMG_CTRL2); - - writel(0xFF000000, pci_reg_addr + W_BA3); - writel(0xFF000000, pci_reg_addr + W_AM3); - writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3); - writel(0x04, pci_reg_addr + W_IMG_CTRL3); - - writel(0x00000001, pci_reg_addr + W_ERR_CS); - writel(0x00000001, pci_reg_addr + P_ERR_CS); - - multiv_reset(vme_reg_addr); - writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D, - vme_reg_addr + VME_CTRL); - - multiv_auto_slot_id(vme_reg_addr); - - return 0; -} diff --git a/board/etin/kvme080/multiverse.h b/board/etin/kvme080/multiverse.h deleted file mode 100644 index b3b79b7ee3..0000000000 --- a/board/etin/kvme080/multiverse.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * multiverse.h - * - * VME driver for Multiverse - * - * Author : Sangmoon Kim - * dogoil@etinsys.com - * - * Copyright 2005 ETIN SYSTEMS Co.,Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MULTIVERSE_H__ -#define __MULTIVERSE_H__ - -#define VME_A32_MSTR_BUS 0x90000000 -#define VME_A32_MSTR_SIZE 0x01000000 - -#define VME_A32_SLV_SIZE 0x01000000 - -#define VME_A32_SLV_BUS 0x90000000 -#define VME_A24_SLV_BUS 0x00000000 -#define VME_A16_SLV_BUS 0x00000000 - -#define VME_A32_SLV_LOCAL 0x00000000 -#define VME_A24_SLV_LOCAL 0x00000000 -#define VME_A16_SLV_LOCAL 0x00000000 - -#define A32_SLV_WINDOW -#undef A24_SLV_WINDOW -#undef A16_SLV_WINDOW -#undef REG_SLV_WINDOW - -/* PCI Registers */ - -#define P_IMG_CTRL0 0x100 -#define P_BA0 0x104 -#define P_AM0 0x108 -#define P_TA0 0x10C -#define P_IMG_CTRL1 0x110 -#define P_BA1 0x114 -#define P_AM1 0x118 -#define P_TA1 0x11C -#define P_IMG_CTRL2 0x120 -#define P_BA2 0x124 -#define P_AM2 0x128 -#define P_TA2 0x12C -#define P_IMG_CTRL3 0x130 -#define P_BA3 0x134 -#define P_AM3 0x138 -#define P_TA3 0x13C -#define P_IMG_CTRL4 0x140 -#define P_BA4 0x144 -#define P_AM4 0x148 -#define P_TA4 0x14C -#define P_IMG_CTRL5 0x150 -#define P_BA5 0x154 -#define P_AM5 0x158 -#define P_TA5 0x15C -#define P_ERR_CS 0x160 -#define P_ERR_ADDR 0x164 -#define P_ERR_DATA 0x168 - -#define WB_CONF_SPC_BAR 0x180 -#define W_IMG_CTRL1 0x184 -#define W_BA1 0x188 -#define W_AM1 0x18C -#define W_TA1 0x190 -#define W_IMG_CTRL2 0x194 -#define W_BA2 0x198 -#define W_AM2 0x19C -#define W_TA2 0x1A0 -#define W_IMG_CTRL3 0x1A4 -#define W_BA3 0x1A8 -#define W_AM3 0x1AC -#define W_TA3 0x1B0 -#define W_IMG_CTRL4 0x1B4 -#define W_BA4 0x1B8 -#define W_AM4 0x1BC -#define W_TA4 0x1C0 -#define W_IMG_CTRL5 0x1C4 -#define W_BA5 0x1C8 -#define W_AM5 0x1CC -#define W_TA5 0x1D0 -#define W_ERR_CS 0x1D4 -#define W_ERR_ADDR 0x1D8 -#define W_ERR_DATA 0x1DC -#define CNF_ADDR 0x1E0 -#define CNF_DATA 0x1E4 -#define INT_ACK 0x1E8 -#define ICR 0x1EC -#define ISR 0x1F0 - -/* VME registers */ - -#define VME_SLAVE32_AM 0x03 -#define VME_SLAVE24_AM 0x02 -#define VME_SLAVE16_AM 0x01 -#define VME_SLAVE_REG_AM 0x00 -#define VME_SLAVE32_A 0x07 -#define VME_SLAVE24_A 0x06 -#define VME_SLAVE16_A 0x05 -#define VME_SLAVE_REG_A 0x04 -#define VME_SLAVE32_MASK 0x0B -#define VME_SLAVE24_MASK 0x0A -#define VME_SLAVE16_MASK 0x09 -#define VME_SLAVE_REG_MASK 0x08 -#define VME_SLAVE32_EN 0x0F -#define VME_SLAVE24_EN 0x0E -#define VME_SLAVE16_EN 0x0D -#define VME_SLAVE_REG_EN 0x0C -#define VME_MASTER32_AM 0x13 -#define VME_MASTER24_AM 0x12 -#define VME_MASTER16_AM 0x11 -#define VME_MASTER_REG_AM 0x10 -#define VME_RMW_ADRS 0x14 -#define VME_MBOX 0x18 -#define VME_STATUS 0x1E -#define VME_CTRL 0x1C -#define VME_IRQ 0x20 -#define VME_INT_EN 0x21 -#define VME_INT 0x22 -#define VME_IRQ1_REG 0x24 -#define VME_IRQ2_REG 0x28 -#define VME_IRQ3_REG 0x2C -#define VME_IRQ4_REG 0x30 -#define VME_IRQ5_REG 0x34 -#define VME_IRQ6_REG 0x38 -#define VME_IRQ7_REG 0x3C - -/* VME control register */ - -#define VME_CTRL_BRDRST 0x01 -#define VME_CTRL_SYSRST 0x02 -#define VME_CTRL_RMW 0x04 -#define VME_CTRL_SHORT_D 0x08 -#define VME_CTRL_SYSFAIL 0x10 -#define VME_CTRL_VOWN 0x20 -#define VME_CTRL_A16_REG_MODE 0x40 - -/* VME status register */ - -#define VME_STATUS_SYSCON 0x01 -#define VME_STATUS_SYSFAIL 0x02 -#define VME_STATUS_ACFAIL 0x04 -#define VME_STATUS_SYSRST 0x08 -#define VME_STATUS_VOWN 0x10 - -/* Interrupt types */ - -#define LVL1 0x0002 -#define LVL2 0x0004 -#define LVL3 0x0008 -#define LVL4 0x0010 -#define LVL5 0x0020 -#define LVL6 0x0040 -#define LVL7 0x0080 -#define MULTIVERSE_INTI_INT 0x0100 -#define MULTIVERSE_WB_INT 0x0200 -#define MULTIVERSE_PCI_INT 0x0400 - -/* interrupt acknowledge */ - -#define VME_IACK1 0x04 -#define VME_IACK2 0x08 -#define VME_IACK3 0x0c -#define VME_IACK4 0x10 -#define VME_IACK5 0x14 -#define VME_IACK6 0x18 -#define VME_IACK7 0x1c - -#endif /* __MULTIVERSE_H__ */ diff --git a/board/eukrea/cpu9260/Kconfig b/board/eukrea/cpu9260/Kconfig new file mode 100644 index 0000000000..9bd077b1ff --- /dev/null +++ b/board/eukrea/cpu9260/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CPU9260 + +config SYS_BOARD + default "cpu9260" + +config SYS_VENDOR + default "eukrea" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "cpu9260" + +endif diff --git a/board/eukrea/cpu9260/MAINTAINERS b/board/eukrea/cpu9260/MAINTAINERS new file mode 100644 index 0000000000..fb5aee80d5 --- /dev/null +++ b/board/eukrea/cpu9260/MAINTAINERS @@ -0,0 +1,13 @@ +CPU9260 BOARD +M: Eric Benard +S: Maintained +F: board/eukrea/cpu9260/ +F: include/configs/cpu9260.h +F: configs/cpu9260_defconfig +F: configs/cpu9260_128M_defconfig +F: configs/cpu9260_nand_defconfig +F: configs/cpu9260_nand_128M_defconfig +F: configs/cpu9G20_defconfig +F: configs/cpu9G20_128M_defconfig +F: configs/cpu9G20_nand_defconfig +F: configs/cpu9G20_nand_128M_defconfig diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile index bd89fe1f49..e34792ac42 100644 --- a/board/eukrea/cpu9260/Makefile +++ b/board/eukrea/cpu9260/Makefile @@ -13,25 +13,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += led.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += cpu9260.o +obj-y += led.o diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 5e1524e07b..01ecccb8c9 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -12,12 +12,12 @@ #include #include +#include #include #include #include #include #include -#include #include #include #include @@ -79,39 +79,24 @@ static void cpu9260_nand_hw_init(void) writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif #ifdef CONFIG_MACB static void cpu9260_macb_hw_init(void) { - unsigned long rstcmr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; /* Enable clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); - rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr); + at91_phy_reset(); at91_macb_hw_init(); } diff --git a/board/eukrea/cpuat91/Kconfig b/board/eukrea/cpuat91/Kconfig new file mode 100644 index 0000000000..b69e4c3f82 --- /dev/null +++ b/board/eukrea/cpuat91/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CPUAT91 + +config SYS_BOARD + default "cpuat91" + +config SYS_VENDOR + default "eukrea" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "cpuat91" + +endif diff --git a/board/eukrea/cpuat91/MAINTAINERS b/board/eukrea/cpuat91/MAINTAINERS new file mode 100644 index 0000000000..1f6bc798dc --- /dev/null +++ b/board/eukrea/cpuat91/MAINTAINERS @@ -0,0 +1,7 @@ +CPUAT91 BOARD +M: Eric Benard +S: Maintained +F: board/eukrea/cpuat91/ +F: include/configs/cpuat91.h +F: configs/cpuat91_defconfig +F: configs/cpuat91_ram_defconfig diff --git a/board/eukrea/cpuat91/Makefile b/board/eukrea/cpuat91/Makefile index ed9d3e7285..59b80c267c 100644 --- a/board/eukrea/cpuat91/Makefile +++ b/board/eukrea/cpuat91/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cpuat91.o diff --git a/board/evb64260/64260.h b/board/evb64260/64260.h deleted file mode 100644 index d106ced3c2..0000000000 --- a/board/evb64260/64260.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __64260_H__ -#define __64260_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_AACK_DELAY (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_TA_DELAY (1 << 15) -#define CPU_CONF_RD_OOO (1 << 16) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_FAST_CLK (1 << 23) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) -#define CPU_CONF_CONF_SB_DIS (1 << 28) -#define CPU_CONF_IO_SB_DIS (1 << 29) -#define CPU_CONF_CLK_SYNC (1 << 30) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64260_H__ */ diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile deleted file mode 100644 index 512f6d714b..0000000000 --- a/board/evb64260/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -SOBJS = misc.o -COBJS = $(BOARD).o flash.o serial.o memory.o pci.o \ - eth.o eth_addrtbl.o mpsc.o i2c.o \ - sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/evb64260/README b/board/evb64260/README deleted file mode 100644 index 74211dea43..0000000000 --- a/board/evb64260/README +++ /dev/null @@ -1,54 +0,0 @@ -This file contains status information for the port of U-Boot to the -Galileo Evaluation Board. - -Author: Josh Huber - Mission Critical Linux, Inc. - -The support for the Galileo Evaluation board is fairly minimal now. -It's sufficient to boot Linux, but doesn't provide too much more than -what's required to do this. - -Both DUART channels are supported (to use the second one, you have to -modify the board -- see the schematics for where to solder on the -devices module). The ethernet ports are supported, and the MPSC is -supported as a console driver. (keep in mind that the kernel has no -support for this yet) - -There are still occaisonal lockups with the MPSC console driver due to -(we think!) overrun problems. If you're looking for something stable -to use for Linux development, consider sticking with the DUART console -for now. - -Automatic memory sizing mostly works. We've had problems with some -combinations of memory. Please send us email if you're having trouble -with respect to the memory detection. - -Right now, only the 512k boot flash is supported. Support for the -16MB flash on the devices module is forthcoming. Right now the flash -is stored at the 256k boundry in flash, wasting a whole sector (64k!) -for environment data. This isn't really a big deal since we're not -using the 512k for anything else. (Just U-Boot and the environment) - -Finally, here is a sample output session: - -U-Boot 1.0.0-pre1 (Jun 6 2001 - 12:45:11) - -Initializing... - CPU: MPC7400 (altivec enabled) v2.9 - Board: EVB64260 - DRAM: 256 MB - FLASH: 512 kB - In: serial - Out: serial - Err: serial - -=> - -The default configuration should be correct for the evaluation board, -as it's shipped from Galileo. Keep in mind that the default baudrate -is set to 38400, 8N1. - -Good luck, and make sure to send any bugreports to us (or the -u-boot-users list). - -Josh diff --git a/board/evb64260/README.EVB-64260-750CX b/board/evb64260/README.EVB-64260-750CX deleted file mode 100644 index 5ea38eaea3..0000000000 --- a/board/evb64260/README.EVB-64260-750CX +++ /dev/null @@ -1,7 +0,0 @@ -The EVB-64260-750CX is quite similar to the EVB-64260-BP already -supported except the following differences: -* It has an IBM-750CXe soldiered on board instead of the slot-1 in the - BP. -* It has a single PCI male connector instead of the 4 PCI female - connectors on the BP. It also gets power trough the PCI connector. -* It has only a single DIMM slot instead of the 2 slots in the BP. diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt deleted file mode 100644 index 6cae9ea074..0000000000 --- a/board/evb64260/bootseq.txt +++ /dev/null @@ -1,94 +0,0 @@ -(cpu/mpc7xxx/start.S) - -start: - b boot_cold - -start_warm: - b boot_warm - - -boot_cold: -boot_warm: - clear bats - init l2 (if enabled) - init altivec (if enabled) - invalidate l2 (if enabled) - setup bats (from defines in config_EVB) - enable_addr_trans: (if MMU enabled) - enable MSR_IR and MSR_DR - jump to in_flash - -in_flash: - enable l1 dcache - gal_low_init: (board/evb64260/sdram_init.S) - config SDRAM (CFG, TIMING, DECODE) - init scratch regs (810 + 814) - - detect DIMM0 (bank 0 only) - config SDRAM_PARA0 to 256/512Mbit - bl sdram_op_mode - detect bank0 width - write scratch reg 810 - config SDRAM_PARA0 with results - config SDRAM_PARA1 with results - - detect DIMM1 (bank 2 only) - config SDRAM_PARA2 to 256/512Mbit - detect bank2 width - write scratch reg 814 - config SDRAM_PARA2 with results - config SDRAM_PARA3 with results - - setup device bus timings/width - setup boot device timings/width - - setup CPU_CONF (0x0) - setup cpu master control register 0x160 - setup PCI0 TIMEOUT - setup PCI1 TIMEOUT - setup PCI0 BAR - setup PCI1 BAR - - setup MPP control 0-3 - setup GPP level control - setup Serial ports multiplex - - setup stack pointer (r1) - setup GOT - call cpu_init_f - debug leds - board_init_f: (common/board.c) - board_early_init_f: - remap gt regs? - map PCI mem/io - map device space - clear out interrupts - init_timebase - env_init - serial_init - console_init_f - display_options - initdram: (board/evb64260/evb64260.c) - detect memory - for each bank: - dram_size() - setup PCI slave memory mappings - setup SCS - setup monitor - alloc board info struct - init bd struct - relocate_code: (cpu/mpc7xxx/start.S) - copy,got,clearbss - board_init_r(bd, dest_addr) (common/board.c) - setup bd function pointers - trap_init - flash_init: (board/evb64260/flash.c) - setup bd flash info - cpu_init_r: (cpu/mpc7xxx/cpu_init.c) - nothing - mem_malloc_init - malloc_bin_reloc - spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) - env_relocated - misc_init_r(bd): (board/evb64260/evb64260.c) - mpsc_init2 diff --git a/board/evb64260/ecctest.c b/board/evb64260/ecctest.c deleted file mode 100644 index 5d3679aa93..0000000000 --- a/board/evb64260/ecctest.c +++ /dev/null @@ -1,111 +0,0 @@ -indent: Standard input:27: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -#ifdef ECC_TEST -static inline void ecc_off (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000; -} - -static inline void ecc_on (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000; -} - -static int putshex (const char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - printf ("%02x", buf[i]); - } - return 0; -} - -static int char_memcpy (void *d, const void *s, int len) -{ - int i; - char *cd = d; - const char *cs = s; - - for (i = 0; i < len; i++) { - *(cd++) = *(cs++); - } - return 0; -} - -static int memory_test (char *buf) -{ - const char src[][16] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}, - {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, - 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}, - {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}, - {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, - 0x08, 0x08, 0x08, 0x08, 0x08, 0x08}, - {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, - {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, - {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}, - {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, - {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}, - {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}, - {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }; - const int foo[] = { 0 }; - int i, j, a; - - printf ("\ntest @ %d %p\n", foo[0], buf); - for (i = 0; i < 12; i++) { - for (a = 0; a < 8; a++) { - const char *s = src[i] + a; - int align = (unsigned) (s) & 0x7; - - /* ecc_off(); */ - memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - /* ecc_off(); */ - char_memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - } - } - - return 0; -} -#endif diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c deleted file mode 100644 index d7f63bddcb..0000000000 --- a/board/evb64260/eth.c +++ /dev/null @@ -1,805 +0,0 @@ -/************************************************************************** -Etherboot - BOOTP/TFTP Bootstrap Program -Skeleton NIC driver for Etherboot -***************************************************************************/ - -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file is a modified version from the Galileo polled mode - * network driver for the ethernet contained within the GT64260 - * chip. It has been modified to fit into the U-Boot framework, from - * the original (etherboot) setup. Also, additional cleanup and features - * were added. - * - * - Josh Huber - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "eth.h" -#include "eth_addrtbl.h" - -#if defined(CONFIG_CMD_NET) - -#define GT6426x_ETH_BUF_SIZE 1536 - -/* if you like verbose output, turn this on! */ -#undef DEBUG - -/* Restart autoneg if we detect link is up on phy init. */ - -/* - * The GT doc's say that after Rst is deasserted, and the PHY - * reports autoneg complete, it runs through its autoneg - * procedures. This doesn't seem to be the case for MII - * PHY's. To work around this check for link up && autoneg - * complete when initilizing the port. If they are both set, - * then restart PHY autoneg. Of course, it may be something - * completly different. - */ -#ifdef CONFIG_ETHER_PORT_MII -# define RESTART_AUTONEG -#endif - -/* do this if you dont want to use snooping */ -#define USE_SOFTWARE_CACHE_MANAGEMENT - -#ifdef USE_SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -/* bummer - w/o flush, nothing works, even with snooping - FIXME */ -/* #define FLUSH_DCACHE(a,b) */ -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif -struct eth_dev_s { - eth0_tx_desc_single *eth_tx_desc; - eth0_rx_desc_single *eth_rx_desc; - char *eth_tx_buffer; - char *eth_rx_buffer[NR]; - int tdn, rdn; - int dev; - unsigned int reg_base; -}; - - -#ifdef CONFIG_INTEL_LXT97X -/* for intel LXT972 */ -static const char ether_port_phy_addr[3]={0,1,2}; -#else -static const char ether_port_phy_addr[3]={4,5,6}; -#endif - -/* MII PHY access routines are common for all i/f, use gal_ent0 */ -#define GT6426x_MII_DEVNAME "gal_enet0" - -int gt6426x_miiphy_read(const char *devname, unsigned char phy, - unsigned char reg, unsigned short *val); - -static inline unsigned short -miiphy_read_ret(unsigned short phy, unsigned short reg) -{ - unsigned short val; - gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val); - return val; -} - - -/************************************************************************** -RESET - Reset adapter -***************************************************************************/ -void -gt6426x_eth_reset(void *v) -{ - /* we should do something here... - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = wp->priv; - */ - - printf ("RESET\n"); - /* put the card in its initial state */ -} - -static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) -{ -#ifdef DEBUG - printf("SMI interrupt: "); - - if(icr&0x20000000) { - printf("SMI done\n"); - } -#endif - - if(icr&0x10000000) { -#ifdef DEBUG - unsigned int psr; - - psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); - printf("PHY state change:\n" - " GT:%s:%s:%s:%s\n", - psr & 1 ? "100" : " 10", - psr & 8 ? " Link" : "nLink", - psr & 2 ? "FD" : "HD", - psr & 4 ? " FC" : "nFC"); - -#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ - { - unsigned short mii_11; - mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11); - - printf(" mii:%s:%s:%s:%s %s:%s %s\n", - mii_11 & (1 << 14) ? "100" : " 10", - mii_11 & (1 << 10) ? " Link" : "nLink", - mii_11 & (1 << 9) ? "FD" : "HD", - mii_11 & (1 << 4) ? " FC" : "nFC", - - mii_11 & (1 << 7) ? "ANc" : "ANnc", - mii_11 & (1 << 8) ? "AN" : "Manual", - "" - ); - } -#endif /* CONFIG_INTEL_LXT97X */ -#endif /* DEBUG */ - } -} - -static int -gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr) -{ - int eth_len=0; - char *eth_data; - - eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)]; - - INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); - - if (rx->command_status & 0x80000000) { - return 0; /* No packet received */ - } - - eth_len = (unsigned int) - (rx->buff_size_byte_count) & 0x0000ffff; - eth_data = (char *) p->eth_rx_buffer[p->rdn]; - -#ifdef DEBUG - if (eth_len) { - printf ("%s: Recived %d byte Packet @ 0x%p\n", - __FUNCTION__, eth_len, eth_data); - } -#endif - /* - * packet is now in: - * eth0_rx_buffer[RDN_ETH0]; - */ - - /* let the upper layer handle the packet */ - NetReceive ((uchar *)eth_data, eth_len); - - rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; - - - /* GT96100 Owner */ - rx->command_status = 0x80000000; - - FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); - - p->rdn ++; - if (p->rdn == NR) {p->rdn = 0;} - - sync(); - - /* Start Rx*/ - GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080); - -#ifdef DEBUG - { - int i; - for (i=0;i<12;i++) { - printf(" %02x", eth_data[i]); - } - } - printf(": %d bytes\n", eth_len); -#endif - INVALIDATE_DCACHE((unsigned int)eth_data, - (unsigned int)eth_data+eth_len); - return eth_len; -} - -/************************************************************************** -POLL - look for an rx frame, handle other conditions -***************************************************************************/ -int -gt6426x_eth_poll(void *v) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = wp->priv; - unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base); - - if(icr) { - GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0); -#ifdef DEBUG - printf("poll got ICR %08x\n", icr); -#endif - /* SMI done or PHY state change*/ - if(icr&0x30000000) gt6426x_handle_SMI(p, icr); - } - /* always process. We aren't using RX interrupts */ - return gt6426x_eth_receive(p, icr); -} - -/************************************************************************** -TRANSMIT - Transmit a frame -***************************************************************************/ -int gt6426x_eth_transmit(void *v, char *p, unsigned int s) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv; -#ifdef DEBUG - unsigned int old_command_stat,old_psr; -#endif - eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn]; - - /* wait for tx to be ready */ - INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); - while (tx->command_status & 0x80000000) { - int i; - for(i=0;i<1000;i++); - INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); - } - - GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base, - (unsigned int)tx); - -#ifdef DEBUG - printf("copying to tx_buffer [%p], length %x, desc = %p\n", - dev->eth_tx_buffer, s, dev->eth_tx_desc); -#endif - memcpy(dev->eth_tx_buffer, (char *) p, s); - - tx->buff_pointer = (uchar *)dev->eth_tx_buffer; - tx->bytecount_reserved = ((__u16)s) << 16; - - /* 31 - own - * 22 - gencrc - * 18:16 - pad, last, first */ - tx->command_status = (1<<31) | (1<<22) | (7<<16); -#if 0 - /* FEr #18 */ - tx->next_desc = NULL; -#else - tx->next_desc = - (struct eth0_tx_desc_struct *) - &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved; - - /* cpu owned */ - dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */ -#endif - -#ifdef DEBUG - old_command_stat=tx->command_status, - old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); -#endif - - FLUSH_DCACHE((unsigned int)tx, - (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]); - - FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s); - - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000); - -#ifdef DEBUG - { - unsigned int command_stat=0; - printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr); - /* wait for tx to be ready */ - do { - unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); - command_stat=tx->command_status; - if(command_stat!=old_command_stat || psr !=old_psr) { - printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr); - old_command_stat = command_stat; - old_psr = psr; - } - /* gt6426x_eth0_poll(); */ - } while (command_stat & 0x80000000); - - printf("sent %d byte frame\n", s); - - if((command_stat & (3<<15)) == 3) { - printf("frame had error (stat=%08x)\n", command_stat); - } - } -#endif - return 0; -} - -/************************************************************************** -DISABLE - Turn off ethernet interface -***************************************************************************/ -void -gt6426x_eth_disable(void *v) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; - - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000); -} - -/************************************************************************** -MII utilities - write: write to an MII register via SMI -***************************************************************************/ -int -gt6426x_miiphy_write(const char *devname, unsigned char phy, - unsigned char reg, unsigned short data) -{ - unsigned int temp= (reg<<21) | (phy<<16) | data; - - while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ - - GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); - return 0; -} - -/************************************************************************** -MII utilities - read: read from an MII register via SMI -***************************************************************************/ -int -gt6426x_miiphy_read(const char *devname, unsigned char phy, - unsigned char reg, unsigned short *val) -{ - unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; - - while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ - - GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); - - while(1) { - temp=GTREGREAD(ETHERNET_SMI_REGISTER); - if(temp & (1<<27)) break; /* wait for ReadValid */ - } - *val = temp & 0xffff; - - return 0; -} - -#ifdef DEBUG -/************************************************************************** -MII utilities - dump mii registers -***************************************************************************/ -static void -gt6426x_dump_mii(bd_t *bis, unsigned short phy) -{ - printf("mii reg 0 - 3: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x0), - miiphy_read_ret(phy, 0x1), - miiphy_read_ret(phy, 0x2), - miiphy_read_ret(phy, 0x3) - ); - printf(" 4 - 7: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x4), - miiphy_read_ret(phy, 0x5), - miiphy_read_ret(phy, 0x6), - miiphy_read_ret(phy, 0x7) - ); - printf(" 8: %04x\n", - miiphy_read_ret(phy, 0x8) - ); - printf(" 16-19: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x10), - miiphy_read_ret(phy, 0x11), - miiphy_read_ret(phy, 0x12), - miiphy_read_ret(phy, 0x13) - ); - printf(" 20,30: %04x %04x\n", - miiphy_read_ret(phy, 20), - miiphy_read_ret(phy, 30) - ); -} -#endif - -#ifdef RESTART_AUTONEG - -/* If link is up && autoneg compleate, and if - * GT and PHY disagree about link capabilitys, - * restart autoneg - something screwy with FD/HD - * unless we do this. */ -static void -check_phy_state(struct eth_dev_s *p) -{ - int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR); - int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); - - if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) { - int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) & - miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA); - int want; - - if (nego & LPA_100FULL) { - want = 0x3; - printf("MII: 100Base-TX, Full Duplex\n"); - } else if (nego & LPA_100HALF) { - want = 0x1; - printf("MII: 100Base-TX, Half Duplex\n"); - } else if (nego & LPA_10FULL) { - want = 0x2; - printf("MII: 10Base-T, Full Duplex\n"); - } else if (nego & LPA_10HALF) { - want = 0x0; - printf("MII: 10Base-T, Half Duplex\n"); - } else { - printf("MII: Unknown link-foo! %x\n", nego); - return; - } - - if ((psr & 0x3) != want) { - printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n", - psr & 0x3, want); - miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0, - miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9)); - udelay(10000); /* the EVB's GT takes a while to notice phy - went down and up */ - } - } -} -#endif - -/************************************************************************** -PROBE - Look for an adapter, this routine's visible to the outside -***************************************************************************/ -int -gt6426x_eth_probe(void *v, bd_t *bis) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; - int dev = p->dev; - unsigned int reg_base = p->reg_base; - unsigned long temp; - int i; - - if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS )) - { /* This should never happen */ - printf("%s: Invalid device %d\n", __FUNCTION__, dev ); - return 0; - } - -#ifdef DEBUG - printf ("%s: initializing %s\n", __FUNCTION__, wp->name ); - printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n", - GTREGREAD(COMM_UNIT_ARBITER_CONTROL), - GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER)); -#endif - - /* clear MIB counters */ - for(i=0;i<255; i++) - temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i); - -#ifdef CONFIG_INTEL_LXT97X - /* for intel LXT972 */ - - /* led 1: 0x1=txact - led 2: 0xc=link/rxact - led 3: 0x2=rxact (N/C) - strch: 0,2=30 ms, enable */ - miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22); - - /* 2.7ns port rise time */ - /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */ -#else - /* already set up in mpsc.c */ - /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */ - - /* already set up in sdram_init.S... */ - /* MPSC0, MPSC1, RMII */ - /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */ -#endif - GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER, - ether_port_phy_addr[0] | - (ether_port_phy_addr[1]<<5) | - (ether_port_phy_addr[2]<<10)); /* 2000 */ - - /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes) - * 9 - 1: RIFB - interrupt on frame boundaries only - * 6:7 - 00: big endian rx and tx - * 5:2 - 1111: 15 retries */ - GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base, - (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */ - -#ifndef USE_SOFTWARE_CACHE_MANAGEMENT - /* enable rx/tx desc/buffer cache snoop */ - GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, - &temp); /* f200 */ - temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30); - GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, - temp); -#endif - - /* 31 28 27 24 23 20 19 16 - * 0000 0000 0000 0000 [0004] - * 15 12 11 8 7 4 3 0 - * 1000 1101 0000 0000 [4d00] - * 20 - 0=MII 1=RMII - * 19 - 0=speed autoneg - * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE) - * 11 - no force link pass - * 10 - 1=disable fctl autoneg - * 8 - override prio ?? */ - temp = 0x00004d00; -#ifndef CONFIG_ETHER_PORT_MII - temp |= (1<<20); /* RMII */ -#endif - /* set En */ - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base, - temp); /* 2408 */ - - /* hardcode E1 also? */ - /* -- according to dox, this is safer due to extra pulldowns? */ - if (dev<2) { - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400, - temp); /* 2408 */ - } - - /* wake up MAC */ /* 2400 */ - GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp); - temp |= (1<<7); /* enable port */ -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - temp |= (1<<12); /* hash size 1/2k */ -#else - temp |= 1; /* promisc */ -#endif - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp); - /* 2400 */ - -#ifdef RESTART_AUTONEG - check_phy_state(p); -#endif - - printf("%s: Waiting for link up..\n", wp->name); - temp = 10 * 1000; - /* wait for link back up */ - while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8) - && (--temp > 0)){ - udelay(1000); /* wait 1 ms */ - } - if ( temp == 0) { - printf("%s: Failed!\n", wp->name); - return (0); - } - - printf("%s: OK!\n", wp->name); - - p->tdn = 0; - p->rdn = 0; - p->eth_tx_desc[p->tdn].command_status = 0; - - /* Initialize Rx Side */ - for (temp = 0; temp < NR; temp++) { - p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp]; - p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; - - /* GT96100 Owner */ - p->eth_rx_desc[temp].command_status = 0x80000000; - p->eth_rx_desc[temp].next_desc = - (struct eth0_rx_desc_struct *) - &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count; - } - - FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0], - (unsigned int)&p->eth_tx_desc[NR]); - FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0], - (unsigned int)&p->eth_rx_desc[NR]); - - GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_tx_desc); - GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_rx_desc); - GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_rx_desc); - -#ifdef DEBUG - printf ("\nRx descriptor pointer is %08x %08x\n", - GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base), - GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base)); - printf ("\n\n%08x %08x\n", - (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status); - - printf ("Descriptor dump:\n"); - printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status); - printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count); - printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer); - printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0)); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4)); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8)); - printf ("%08x\n\n", - *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc)); -#endif - -#ifdef DEBUG - gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]); -#endif - -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - { - unsigned int hashtable_base; - u8 *b = (u8 *)(wp->enetaddr); - u32 macH, macL; - - /* twist the MAC up into the way the discovery wants it */ - macH= (b[0]<<8) | b[1]; - macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5]; - - /* mode 0, size 0x800 */ - hashtable_base =initAddressTable(dev,0,1); - - if(!hashtable_base) { - printf("initAddressTable failed\n"); - return 0; - } - - addAddressTableEntry(dev, macH, macL, 1, 0); - GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base, - hashtable_base); - } -#endif - - /* Start Rx*/ - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080); - printf("%s: gt6426x eth device %d init success \n", wp->name, dev ); - return 1; -} - -/* enter all the galileo ethernet devs into MULTI-BOOT */ -void -gt6426x_eth_initialize(bd_t *bis) -{ - struct eth_device *dev; - struct eth_dev_s *p; - int devnum, x, temp; - char *s, *e, buf[64]; - -#ifdef DEBUG - printf( "\n%s\n", __FUNCTION ); -#endif - - for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) { - dev = calloc(sizeof(*dev), 1); - if (!dev) { - printf( "%s: gal_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf(dev->name, "gal_enet%d", devnum); - -#ifdef DEBUG - printf( "Initializing %s\n", dev->name ); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) - { - case 0: s = "ethaddr"; break; -#if (GAL_ETH_DEVS > 1) - case 1: s = "eth1addr"; break; -#endif -#if (GAL_ETH_DEVS > 2) - case 2: s = "eth2addr"; break; -#endif - default: /* this should never happen */ - printf( "%s: Invalid device number %d\n", - __FUNCTION__, devnum ); - return; - } - - temp = getenv_f(s, buf, sizeof(buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s ); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e+1 : e; - } - - dev->init = (void*)gt6426x_eth_probe; - dev->halt = (void*)gt6426x_eth_reset; - dev->send = (void*)gt6426x_eth_transmit; - dev->recv = (void*)gt6426x_eth_poll; - - p = calloc( sizeof(*p), 1 ); - dev->priv = (void*)p; - if (!p) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Private Device Structure"); - free(dev); - return; - } - - p->dev = devnum; - p->tdn=0; - p->rdn=0; - p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS; - - p->eth_tx_desc = - (eth0_tx_desc_single *) - (((unsigned int) malloc(sizeof (eth0_tx_desc_single) * - (NT+1)) & 0xfffffff0) + 0x10); - if (!p) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Tx Descriptor"); - free(dev); - return; - } - - p->eth_rx_desc = - (eth0_rx_desc_single *) - (((unsigned int) malloc(sizeof (eth0_rx_desc_single) * - (NR+1)) & 0xfffffff0) + 0x10); - if (!p->eth_rx_desc) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Rx Descriptor"); - free(dev); - free(p); - return; - } - - p->eth_tx_buffer = - (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); - if (!p->eth_tx_buffer) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Tx Bufffer"); - free(dev); - free(p); - free(p->eth_rx_desc); - return; - } - - for (temp = 0 ; temp < NR ; temp ++) { - p->eth_rx_buffer[temp] = - (char *) - (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); - if (!p->eth_rx_buffer[temp]) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Rx Buffers"); - free(dev); - free(p); - free(p->eth_tx_buffer); - free(p->eth_rx_desc); - free(p->eth_tx_desc); - while (temp >= 0) - free(p->eth_rx_buffer[--temp]); - return; - } - } - - - eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, - gt6426x_miiphy_read, gt6426x_miiphy_write); -#endif - } - -} -#endif diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h deleted file mode 100644 index 99581f0137..0000000000 --- a/board/evb64260/eth.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __GT6426x_ETH_H__ -#define __GT6426x_ETH_H__ - -#include -#include -#include -#include - -typedef struct eth0_tx_desc_struct { - volatile __u32 bytecount_reserved; - volatile __u32 command_status; - volatile struct eth0_tx_desc_struct * next_desc; - /* Note - the following will not work for 64 bit addressing */ - volatile unsigned char * buff_pointer; -} __attribute__ ((packed)) eth0_tx_desc_single; - -typedef struct eth0_rx_desc_struct { - volatile __u32 buff_size_byte_count; - volatile __u32 command_status; - volatile struct eth0_rx_desc_struct * next_desc; - volatile unsigned char * buff_pointer; -} __attribute__ ((packed)) eth0_rx_desc_single; - -#define NT 20 /* Number of Transmit buffers */ -#define NR 20 /* Number of Receive buffers */ -#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) /* 1600 */ -#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400 - -unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/ -unsigned int EVB64260_ETH0_irq; - -#define CLOSED 0 -#define OPENED 1 - -#define PORT_ETH0 0 - -extern eth0_tx_desc_single *eth0_tx_desc; -extern eth0_rx_desc_single *eth0_rx_desc; -extern char *eth0_tx_buffer; -extern char *eth0_rx_buffer[NR]; -extern char *eth_data; - -extern int gt6426x_eth_poll(void *v); -extern int gt6426x_eth_transmit(void *v, char *p, unsigned int s); -extern void gt6426x_eth_disable(void *v); -extern int gt6426x_eth_probe(void *v, bd_t *bis); - -#endif /* __GT64260x_ETH_H__ */ diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c deleted file mode 100644 index 8c2c17f962..0000000000 --- a/board/evb64260/eth_addrtbl.c +++ /dev/null @@ -1,218 +0,0 @@ -#include -#include -#include -#include -#include -#include "eth.h" -#include "eth_addrtbl.h" - -#define PRINTF printf - -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - -static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, }; -static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, }; -static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, }; -static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, }; - -static const u32 hashLength[2] = { - (0x8000), /* 8K * 4 entries */ - (0x8000 / 16), /* 512 * 4 entries */ -}; - -/* Initialize the address table for a port, if needed */ -unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector) -{ - unsigned int tableBase; - - if (port < 0 || port >= GAL_ETH_DEVS) { - printf ("%s: Invalid port number %d\n", __FUNCTION__, port); - return 0; - } - - if (hashMode > 1) { - printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port); - return 0; - } - - if (realAddrTableBase[port] && - (addressTableHashSize[port] != hashSizeSelector)) { - /* we have been here before, - * but now we want a different sized table - */ - free (realAddrTableBase[port]); - realAddrTableBase[port] = 0; - addressTableBase[port] = 0; - - } - - tableBase = (unsigned int) addressTableBase[port]; - /* we get called for every probe, so only do this once */ - if (!tableBase) { - int bytes = - hashLength[hashSizeSelector] * sizeof (addrTblEntry); - - realAddrTableBase[port] = - malloc (bytes + 64); - tableBase = (unsigned int)realAddrTableBase; - - if (!tableBase) { - printf ("%s: alloc memory failed \n", __FUNCTION__); - return 0; - } - - /* align to octal byte */ - if (tableBase & 63) - tableBase = (tableBase + 63) & ~63; - - addressTableHashMode[port] = hashMode; - addressTableHashSize[port] = hashSizeSelector; - addressTableBase[port] = (addrTblEntry *) tableBase; - - memset ((void *) tableBase, 0, bytes); - } - - return tableBase; -} - -/* - * ---------------------------------------------------------------------------- - * This function will calculate the hash function of the address. - * depends on the hash mode and hash size. - * Inputs - * macH - the 2 most significant bytes of the MAC address. - * macL - the 4 least significant bytes of the MAC address. - * hashMode - hash mode 0 or hash mode 1. - * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800) - * Outputs - * return the calculated entry. - */ -u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode) -{ - u32 hashResult; - u32 addrH; - u32 addrL; - u32 addr0; - u32 addr1; - u32 addr2; - u32 addr3; - u32 addrHSwapped; - u32 addrLSwapped; - - - addrH = NIBBLE_SWAPPING_16_BIT (macH); - addrL = NIBBLE_SWAPPING_32_BIT (macL); - - addrHSwapped = FLIP_4_BITS (addrH & 0xf) - + ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4) - + ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8) - + ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12); - - addrLSwapped = FLIP_4_BITS (addrL & 0xf) - + ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4) - + ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8) - + ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12) - + ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16) - + ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20) - + ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24) - + ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28); - - addrH = addrHSwapped; - addrL = addrLSwapped; - - if (hash_mode == 0) { - addr0 = (addrL >> 2) & 0x03f; - addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2; - addr2 = (addrL >> 15) & 0x1ff; - addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8); - } else { - addr0 = FLIP_6_BITS (addrL & 0x03f); - addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff)); - addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff); - addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) | - ((addrH & 0x1) << 8))); - } - - hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); - - if (HashSize == _8K_TABLE) { - hashResult = hashResult & 0xffff; - } else { - hashResult = hashResult & 0x07ff; - } - - return (hashResult); -} - - -/* - * ---------------------------------------------------------------------------- - * This function will add an entry to the address table. - * depends on the hash mode and hash size that was initialized. - * Inputs - * port - ETHERNET port number. - * macH - the 2 most significant bytes of the MAC address. - * macL - the 4 least significant bytes of the MAC address. - * skip - if 1, skip this address. - * rd - the RD field in the address table. - * Outputs - * address table entry is added. - * true if success. - * false if table full - */ -int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip) -{ - addrTblEntry *entry; - u32 newHi; - u32 newLo; - u32 i; - - newLo = (((macH >> 4) & 0xf) << 15) - | (((macH >> 0) & 0xf) << 11) - | (((macH >> 12) & 0xf) << 7) - | (((macH >> 8) & 0xf) << 3) - | (((macL >> 20) & 0x1) << 31) - | (((macL >> 16) & 0xf) << 27) - | (((macL >> 28) & 0xf) << 23) - | (((macL >> 24) & 0xf) << 19) - | (skip << SKIP_BIT) | (rd << 2) | VALID; - - newHi = (((macL >> 4) & 0xf) << 15) - | (((macL >> 0) & 0xf) << 11) - | (((macL >> 12) & 0xf) << 7) - | (((macL >> 8) & 0xf) << 3) - | (((macL >> 21) & 0x7) << 0); - - /* - * Pick the appropriate table, start scanning for free/reusable - * entries at the index obtained by hashing the specified MAC address - */ - entry = addressTableBase[port]; - entry += hashTableFunction (macH, macL, addressTableHashSize[port], - addressTableHashMode[port]); - for (i = 0; i < HOP_NUMBER; i++, entry++) { - if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) { - break; - } else { /* if same address put in same position */ - if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8)) - && (entry->hi == newHi)) { - break; - } - } - } - - if (i == HOP_NUMBER) { - PRINTF ("addGT64260addressTableEntry: table section is full\n"); - return false; - } - - /* - * Update the selected entry - */ - entry->hi = newHi; - entry->lo = newLo; - DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE); - return true; -} - -#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */ diff --git a/board/evb64260/eth_addrtbl.h b/board/evb64260/eth_addrtbl.h deleted file mode 100644 index 5a62c67e18..0000000000 --- a/board/evb64260/eth_addrtbl.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef _ADDRESS_TABLE_H -#define _ADDRESS_TABLE_H 1 - -/* - * ---------------------------------------------------------------------------- - * addressTable.h - this file has all the declarations of the address table - */ - -#define _8K_TABLE 0 -#define ADDRESS_TABLE_ALIGNMENT 8 -#define HASH_DEFAULT_MODE 14 -#define HASH_MODE 13 -#define HASH_SIZE 12 -#define HOP_NUMBER 12 -#define MAC_ADDRESS_STRING_SIZE 12 -#define MAC_ENTRY_SIZE sizeof(addrTblEntry) -#define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000 -#define PROMISCUOUS_MODE 0 -#define SKIP 1<<1 -#define SKIP_BIT 1 -#define VALID 1 - -/* - * ---------------------------------------------------------------------------- - * XXX_MIKE - potential sign-extension bugs lurk here... - */ -#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \ - | (((X) & 0x0f0f0f0f) << 4) ) - -#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \ - | (((X) & 0x00000f0f) << 4) ) - -#define FLIP_4_BITS(X) ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \ - | (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) ) - -#define FLIP_6_BITS(X) ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \ - | (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \ - | (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) ) - -#define FLIP_9_BITS(X) ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \ - | (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \ - | (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \ - | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) ) - -/* - * V: value we're operating on - * O: offset of rightmost bit in field - * W: width of field to shift - * S: distance to shift left - */ -#define MASK( fieldWidth ) ((1 << (fieldWidth)) - 1) -#define leftShiftedBitfield( V,O,W,S) (((V) & (MASK(W) << (O))) << (S)) -#define rightShiftedBitfield(V,O,W,S) (((u32)((V) & (MASK(W) << (O)))) >> (S)) - - -/* - * Push to main memory all cache lines associated with - * the specified range of virtual memory addresses - * - * A: Address of first byte in range to flush - * N: Number of bytes to flush - * Note - flush_dcache_range() does a "sync", does NOT invalidate - */ -#define DCACHE_FLUSH_N_SYNC( A, N ) flush_dcache_range( (A), ((A)+(N)) ) - - -typedef struct addressTableEntryStruct { - u32 hi; - u32 lo; -} addrTblEntry; - -u32 -uncachedPages( u32 pages ); -u32 -hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode ); - -unsigned int -initAddressTable( u32 port, u32 hashMode, u32 hashSize ); - -int -addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip ); - -#endif /* #ifndef _ADDRESS_TABLE_H */ diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c deleted file mode 100644 index 74f8819eac..0000000000 --- a/board/evb64260/evb64260.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * evb64260.c - main board support/init for the Galileo Eval board. - */ - -#include -#include <74xx_7xx.h> -#include -#include -#include -#include -#include -#include - -#include -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64260.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_ZUMA_V2 -extern void zuma_mbox_init(void); -#endif - -#undef DEBUG -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void -my_remap_gt_regs(u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -} - -static void -gt_pci_config(void) -{ - /* move PCI stuff out of the way - NTL */ - /* map PCI Host 0 */ - pciMapSpace(PCI_HOST0, PCI_REGION0, CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, CONFIG_SYS_PCI0_MEM_SIZE); - - pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0); - pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0); - pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0); - - pciMapSpace(PCI_HOST0, PCI_IO, CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE); - - /* map PCI Host 1 */ - pciMapSpace(PCI_HOST1, PCI_REGION0, CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, CONFIG_SYS_PCI1_MEM_SIZE); - - pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0); - pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0); - pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0); - - pciMapSpace(PCI_HOST1, PCI_IO, CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE); - - /* PCI interface settings */ - GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff); - GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff); - GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); - GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); - - -} - -/* Setup CPU interface paramaters */ -static void -gt_cpu_config(void) -{ - cpu_t cpu = get_cpu_type(); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD(CPU_CONFIGURATION); - - /* set the AACK delay bit - * see Res#14 */ - tmp |= CPU_CONF_AACK_DELAY; - tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */ - - /* Galileo claims this is necessary for all busses >= 100 MHz */ - tmp |= CPU_CONF_FAST_CLK; - - if (cpu == CPU_750CX) { - tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */ - tmp &= ~CPU_CONF_AP_VALID; - } else { - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - } - - /* this only works with the MPX bus */ - tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */ - tmp |= CPU_CONF_PIPELINE; - tmp |= CPU_CONF_TA_DELAY; - - GT_REG_WRITE(CPU_CONFIGURATION, tmp); - - /* CPU master control register */ - tmp = GTREGREAD(CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || - (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE(CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - my_remap_gt_regs(CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - - gt_pci_config(); - - /* mask all external interrupt sources */ - GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - - /* now, onto the configuration */ - GT_REG_WRITE(SDRAM_CONFIGURATION, CONFIG_SYS_SDRAM_CONFIG); - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM - * 1 - RTC - * 2 - UART - * 3 - Flash - * boot - BootCS - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - /* Zuma has no SRAM */ - sram_boot = 0; -#else - if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CONFIG_SYS_MONITOR_BASE) - sram_boot = 1; -#endif - - memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - - memoryMapDeviceSpace(DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); - memoryMapDeviceSpace(DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); - memoryMapDeviceSpace(DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); - - /* configure device timing */ -#ifdef CONFIG_SYS_DEV0_PAR - if (!sram_boot) - GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); -#endif - -#ifdef CONFIG_SYS_DEV1_PAR - GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); -#endif -#ifdef CONFIG_SYS_DEV2_PAR - GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); -#endif - -#ifdef CONFIG_EVB64260 -#ifdef CONFIG_SYS_32BIT_BOOT_PAR - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); -#endif -#else /* CONFIG_EVB64260 not defined */ - /* We are booting from 16-bit flash. - */ - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_16BIT_BOOT_PAR); -#endif - - gt_cpu_config(); - - /* MPP setup */ - GT_REG_WRITE(MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE(MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE(MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE(MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE(GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CONFIG_SYS_SERIAL_PORT_MUX); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r (void) -{ - icache_enable(); -#ifdef CONFIG_SYS_L2 - l2cache_enable(); -#endif - -#ifdef CONFIG_MPSC - mpsc_init2(); -#endif - -#ifdef CONFIG_ZUMA_V2 - zuma_mbox_init(); -#endif - return (0); -} - -void -after_reloc(ulong dest_addr) -{ - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - - if (memoryGetDeviceBaseAddress(DEVICE0) == CONFIG_SYS_MONITOR_BASE) { - memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace(BOOT_DEVICE, CONFIG_SYS_FLASH_BASE, _1M); - } - - /* now, jump to the main U-Boot board init code */ - board_init_r ((gd_t *)gd, dest_addr); - - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int -checkboard (void) -{ - puts ("Board: " CONFIG_SYS_BOARD_NAME "\n"); - return (0); -} - -/* utility functions */ -void -debug_led(int led, int mode) -{ -#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4) - volatile int *addr = NULL; - __maybe_unused int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x08000); - break; - - case 1: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x0c000); - break; - - case 2: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x14000); - break; - - case 1: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x18000); - break; - - case 2: - addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x1c000); - break; - } - } - WRITE_CHAR(addr, 0); - dummy = *addr; -#endif /* CONFIG_ZUMA_V2 */ -} - -void -display_mem_map(void) -{ - int i,j; - unsigned int base,size,width; - /* SDRAM */ - printf("SDRAM\n"); - for(i=0;i<=BANK3;i++) { - base = memoryGetBankBaseAddress(i); - size = memoryGetBankSize(i); - if(size !=0) - { - printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20); - } - } - - /* CPU's PCI windows */ - for(i=0;i<=PCI_HOST1;i++) { - printf("\nCPU's PCI %d windows\n", i); - base=pciGetSpaceBase(i,PCI_IO); - size=pciGetSpaceSize(i,PCI_IO); - printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20); - for(j=0;j<=PCI_REGION3;j++) { - base = pciGetSpaceBase(i,j); - size = pciGetSpaceSize(i,j); - printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base, - size>>20); - } - } - - /* Devices */ - printf("\nDEVICES\n"); - for(i=0;i<=DEVICE3;i++) { - base = memoryGetDeviceBaseAddress(i); - size = memoryGetDeviceSize(i); - width= memoryGetDeviceWidth(i) * 8; - printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", - i, base, size>>20, width); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize(BOOT_DEVICE); - width= memoryGetDeviceWidth(BOOT_DEVICE) * 8; - printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", - base, size>>20, width); -} - -int board_eth_init(bd_t *bis) -{ - gt6426x_eth_initialize(bis); - return 0; -} diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c deleted file mode 100644 index 88c43ff688..0000000000 --- a/board/evb64260/flash.c +++ /dev/null @@ -1,837 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * flash.c - flash support for the 512k, 8bit boot flash on the GEVB - * most of this file was based on the existing U-Boot - * flash drivers. - */ - -#include -#include -#include -#include -#include "intel_flash.h" - -#define FLASH_ROM 0xFFFD /* unknown flash type */ -#define FLASH_RAM 0xFFFE /* unknown flash type */ -#define FLASH_MAN_UNKNOWN 0xFFFF0000 - -/* #define DEBUG */ -/* #define FLASH_ID_OVERRIDE */ /* Hack to set type to 040B if ROM emulator is installed. - * Can be used to program a ROM in circuit if a programmer - * is not available by swapping the rom out. */ - -/* Intel flash commands */ -int flash_erase_intel(flash_info_t *info, int s_first, int s_last); -int write_word_intel(bank_addr_t addr, bank_word_t value); - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - unsigned int i; - unsigned long size_b0 = 0, size_b1 = 0; - unsigned long base, flash_size; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - flash_size = size_b0 + size_b1; - return flash_size; -} - -/*----------------------------------------------------------------------- - */ -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - int sector_size; - - if(!info->sector_count) return; - - /* set up sector start address table */ - switch(info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - case FLASH_28F128J3A: - case FLASH_28F640J3A: - case FLASH_RAM: - /* this chip has uniformly spaced sectors */ - sector_size=info->size/info->sector_count; - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sector_size); - break; - default: - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ - -flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base <= info->start[0] + info->size - 1) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64 Mbit)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128 Mbit)\n"); - break; - case FLASH_ROM: - printf ("ROM\n"); - break; - case FLASH_RAM: - printf ("RAM\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - puts (" Size: "); - print_size (info->size, ""); - printf (" in %d Sectors\n", info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd) -{ - /* supports 1x8, 1x16, and 2x16 */ - /* 2x8 and 4x8 are not supported */ - if(width==4) { - /* assuming chips are in 16 bit mode */ - /* 2x16 */ - unsigned long cmd32=(cmd<<16)|cmd; - *(volatile unsigned long *)(addr+offset*2)=cmd32; - } else if (width == 2) { - /* 1x16 */ - *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd; - } else { - /* 1x8 */ - *(volatile unsigned char *)(addr+offset)=cmd; - } -} - -static ulong -flash_get_size (int portwidth, vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr = (unsigned char *)addr; - volatile unsigned short *saddr = (unsigned short *)addr; - volatile unsigned long *laddr = (unsigned long *)addr; - char old[2], save; - ulong id, manu, base = (ulong)addr; - - info->portwidth=portwidth; - - save = *caddr; - - flash_cmd(portwidth,caddr,0,0xf0); - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - - old[0] = caddr[0]; - old[1] = caddr[1]; - - - if(old[0]!=0xf0) { - flash_cmd(portwidth,caddr,0,0xf0); - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - - if(*caddr==0xf0) { - /* this area is ROM */ - *caddr=save; -#ifndef FLASH_ID_OVERRIDE - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; -#else - info->flash_id = FLASH_MAN_AMD + FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; -#endif - flash_get_offsets(base, info); - return info->size; - } - } else { - *caddr=0; - - udelay(10); - - if(*caddr==0) { - /* this area is RAM */ - *caddr=save; - info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets(base, info); - return info->size; - } - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - } - - /* Write auto select command: read Manufacturer ID */ - flash_cmd(portwidth,caddr,0x555,0xAA); - flash_cmd(portwidth,caddr,0x2AA,0x55); - flash_cmd(portwidth,caddr,0x555,0x90); - - udelay(10); - - if ((caddr[0] == old[0]) && - (caddr[1] == old[1])) { - - /* this area is ROM */ -#ifndef FLASH_ID_OVERRIDE - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; -#else - info->flash_id = FLASH_MAN_AMD + FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; -#endif - flash_get_offsets(base, info); - return info->size; -#ifdef DEBUG - } else { - printf("%px%d: %02x:%02x -> %02x:%02x\n", - caddr, portwidth, old[0], old[1], - caddr[0], caddr[1]); -#endif - } - - switch(portwidth) { - case 1: - manu = caddr[0]; - manu |= manu<<16; - id = caddr[1]; - break; - case 2: - manu = saddr[0]; - manu |= manu<<16; - id = saddr[1]; - id |= id<<16; - break; - case 4: - manu = laddr[0]; - id = laddr[1]; - break; - default: - id = manu = -1; - break; - } - -#ifdef DEBUG - printf("\n%08lx:%08lx:%08lx\n", base, manu, id); - printf("%08lx %08lx %08lx %08lx\n", - laddr[0],laddr[1],laddr[2],laddr[3]); -#endif - - switch (manu) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("Unknown Mfr [%08lx]:%08lx\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (id) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth=1; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth=1; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth=1; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth=1; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth=1; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth=1; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; - break; - - case INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */ - info->chipwidth=2; - if(portwidth==4) info->size*=2; /* 2x16 */ - break; - - case INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */ - info->chipwidth=2; - if(portwidth==4) info->size*=2; /* 2x16 */ - break; - - default: - printf("Unknown id %lx:[%lx]\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->chipwidth=1; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets(base, info); - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_AM040) { - /* this chip has uniformly spaced sectors */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0)=0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - saddr = (volatile unsigned short *)(info->start[i]); - laddr = (volatile unsigned long *)(info->start[i]); - if(portwidth==1) - info->protect[i] = caddr[2] & 1; - else if(portwidth==2) - info->protect[i] = saddr[2] & 1; - else - info->protect[i] = laddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - - flash_cmd(portwidth,caddr,0,0xF0); /* reset bank */ - } - - return (info->size); -} - -/* TODO: 2x16 unsupported */ -int -flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = (uchar *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - /* TODO: 2x16 unsupported */ - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - for (sect = s_first; sect<=s_last; sect++) { - int sector_size=info->size/info->sector_count; - addr = (uchar *)(info->start[sect]); - memset((void *)addr, 0, sector_size); - } - return 0; - } - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL) { - return flash_erase_intel(info, - (unsigned short)s_first, - (unsigned short)s_last); - } - -#if 0 - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } -#endif - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_cmd(info->portwidth,addr,0x555,0xAA); - flash_cmd(info->portwidth,addr,0x2AA,0x55); - flash_cmd(info->portwidth,addr,0x555,0x80); - flash_cmd(info->portwidth,addr,0x555,0xAA); - flash_cmd(info->portwidth,addr,0x2AA,0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (uchar *)(info->start[sect]); - flash_cmd(info->portwidth,addr,0,0x30); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - /* broken for 2x16: TODO */ - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - flash_cmd(info->portwidth,addr,0,0xf0); - flash_cmd(info->portwidth,addr,0,0xf0); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -/* broken for 2x16: TODO */ -int -write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - memcpy((void *)addr, src, cnt); - return 0; - } - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -/* broken for 2x16: TODO */ -static int -write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *addr = (uchar *)(info->start[0]); - ulong start; - int flag, i; - - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - *(unsigned long *)dest=data; - return 0; - } - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - unsigned short low = data & 0xffff; - unsigned short hi = (data >> 16) & 0xffff; - int ret = write_word_intel((bank_addr_t)dest, hi); - - if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low); - - return ret; - } - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* first, perform an unlock bypass command to speed up flash writes */ - addr[0x555] = 0xAA; - addr[0x2AA] = 0x55; - addr[0x555] = 0x20; - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - addr[0] = 0xA0; - *(((char *)dest)+i) = data_ch[i]; - udelay(10); /* XXX */ - } - - /* we're done, now do an unlock bypass reset */ - addr[0] = 0x90; - addr[0] = 0x00; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c deleted file mode 100644 index 8119fced48..0000000000 --- a/board/evb64260/i2c.c +++ /dev/null @@ -1,310 +0,0 @@ -#include -#include -#include -#include -#include - -#define MAX_I2C_RETRYS 10 -#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ -#undef DEBUG_I2C - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -static void -i2c_init(int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualn = 0, actualm = 0; - unsigned int control, status; - unsigned int minmargin = 0xffffffff; - unsigned int tclk = 125000000; - - DP(puts("i2c_init\n")); - - for (n = 0 ; n < 8 ; n++) { - for (m = 0 ; m < 16 ; m++) { - power = 2 << n; /* power = 2^(n+1) */ - freq = tclk / (10 * (m + 1) * power); - if (speed > freq) - margin = speed - freq; - else - margin = freq - speed; - if (margin < minmargin) { - minmargin = margin; - actualn = n; - actualm = m; - } - } - } - - DP(puts("setup i2c bus\n")); - - /* Setup bus */ - - GT_REG_WRITE(I2C_SOFT_RESET, 0); - - DP(puts("udelay...\n")); - - udelay(I2C_DELAY); - - DP(puts("set baudrate\n")); - - GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualm << 3) | actualn); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - - udelay(I2C_DELAY * 10); - - DP(puts("read control, baudrate\n")); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - GT_REG_READ(I2C_CONTROL, &control); -} - -static uchar -i2c_start(void) -{ - unsigned int control, status; - int count = 0; - - DP(puts("i2c_start\n")); - - /* Set the start bit */ - - GT_REG_READ(I2C_CONTROL, &control); - control |= (0x1 << 5); - GT_REG_WRITE(I2C_CONTROL, control); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - - count = 0; - while ((status & 0xff) != 0x08) { - udelay(I2C_DELAY); - if (count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return status; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - return 0; -} - -static uchar -i2c_select_device(uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - int count = 0; - - DP(puts("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) - bits = 10; - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE(I2C_DATA, data); - /* assert the address */ - RESET_REG_BITS(I2C_CONTROL, BIT3); - - udelay(I2C_DELAY); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - udelay(I2C_DELAY); - if (count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return status; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - if (bits == 10) { - printf("10 bit I2C addressing not yet implemented\n"); - return 0xff; - } - - return 0; -} - -static uchar -i2c_get_data(uchar *return_data, int len) { - - unsigned int data, status = 0; - int count = 0; - - DP(puts("i2c_get_data\n")); - - while (len) { - - /* Get and return the data */ - - RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); - - udelay(I2C_DELAY * 5); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - udelay(I2C_DELAY); - if (count > 2) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return 0; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ(I2C_DATA, &data); - len--; - *return_data = (uchar)data; - return_data++; - } - RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3); - while ((status & 0xff) != 0x58) { - udelay(I2C_DELAY); - if (count > 200) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return status; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */ - - return 0; -} - -static uchar -i2c_write_data(unsigned int data, int len) -{ - unsigned int status; - int count = 0; - - DP(puts("i2c_write_data\n")); - - if (len > 4) - return -1; - - while (len) { - /* Set and assert the data */ - - GT_REG_WRITE(I2C_DATA, (unsigned int)data); - RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); - - udelay(I2C_DELAY); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay(I2C_DELAY); - if (count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return status; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - } - GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); - - udelay(I2C_DELAY * 10); - - return 0; -} - -static uchar -i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit) -{ - uchar status; - - DP(puts("i2c_set_dev_offset\n")); - - status = i2c_select_device(dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_write_data(offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} - -uchar -i2c_read(uchar dev_addr, unsigned int offset, int len, uchar *data, - int ten_bit) -{ - uchar status = 0; - unsigned int i2cfreq = 400000; - - DP(puts("i2c_read\n")); - - i2c_init(i2cfreq, 0); - - status = i2c_start(); - - if (status) { -#ifdef DEBUG_I2C - printf("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset(dev_addr, 0, 0); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to set offset: 0x%02x\n", status); -#endif - return status; - } - - i2c_init(i2cfreq, 0); - - status = i2c_start(); - if (status) { -#ifdef DEBUG_I2C - printf("Transaction restart failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_select_device(dev_addr, 1, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf("Address not acknowledged: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_get_data(data, len); - if (status) { -#ifdef DEBUG_I2C - printf("Data not received: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} diff --git a/board/evb64260/i2c.h b/board/evb64260/i2c.h deleted file mode 100644 index 9c21992524..0000000000 --- a/board/evb64260/i2c.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __I2C_H__ -#define __I2C_H__ - -/* function declarations */ -uchar i2c_read(uchar, unsigned int, int, uchar*, int); - -#endif diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c deleted file mode 100644 index 9acc3a0010..0000000000 --- a/board/evb64260/intel_flash.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00 - */ - -#include -#include -#include -#include -#include "intel_flash.h" - - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -static void -bank_reset(flash_info_t *info, int sect) -{ - bank_addr_t addrw, eaddrw; - - addrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(addrw); - - while (addrw < eaddrw) { -#ifdef FLASH_DEBUG - printf(" writing reset cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = BANK_CMD_RST; - addrw++; - } -} - -static void -bank_erase_init(flash_info_t *info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int flag; - -#ifdef FLASH_DEBUG - printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); - printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); - printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); - printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); - printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); - printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); - printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); -#endif - - saddrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(saddrw); - -#ifdef FLASH_DEBUG - printf("erasing sector %d, start addr = 0x%08lx " - "(bank next word addr = 0x%08lx)\n", sect, - (unsigned long)saddrw, (unsigned long)eaddrw); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts(); - - for (addrw = saddrw; addrw < eaddrw; addrw++) { -#ifdef FLASH_DEBUG - printf(" writing erase cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = BANK_CMD_ERASE1; - *addrw = BANK_CMD_ERASE2; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); -} - -static int -bank_erase_poll(flash_info_t *info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int sectdone, haderr; - - saddrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(saddrw); - - sectdone = 1; - haderr = 0; - - for (addrw = saddrw; addrw < eaddrw; addrw++) { - bank_word_t stat = *addrw; - -#ifdef FLASH_DEBUG - printf(" checking status at addr " - "0x%08x [0x%08x]\n", - (unsigned long)addrw, stat); -#endif - if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) - sectdone = 0; - else if ((stat & BANK_STAT_ERR) != 0) { - printf(" failed on sector %d " - "(stat = 0x%08x) at " - "address 0x%p\n", - sect, stat, addrw); - *addrw = BANK_CMD_CLR_STAT; - haderr = 1; - } - } - - if (haderr) - return (-1); - else - return (sectdone); -} - -int -write_word_intel(bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf("flash program failed (stat = 0x%08lx) " - "at address 0x%08lx\n", (ulong)stat, (ulong)addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -int -flash_erase_intel(flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - -#ifdef FLASH_DEBUG - printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info(info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sector%s will not be erased!\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init(info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer(start); - - do { - now = get_timer(start); - - if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll(info, sect); - - if (sectdone < 0) { - haderr = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset(info, sect); - } - } - return haderr; -} diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h deleted file mode 100644 index cc3a33965d..0000000000 --- a/board/evb64260/intel_flash.h +++ /dev/null @@ -1,160 +0,0 @@ -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* - * acceptable chips types are: - * - * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A - */ - -/* register addresses, valid only following an CHIP_CMD_RD_ID command */ -#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ -#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ -#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ -#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ - -/* Commands */ -#define CHIP_CMD_RST 0xFF /* reset flash */ -#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ -#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define CHIP_CMD_PROG 0x40 /* program word command */ -#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ -#define CHIP_STAT_VPPS 0x08 /* VPP Status */ -#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ -#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ - CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) - -/* ID and Lock Configuration */ -#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ -#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID - -/* dimensions */ -#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ -#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ -#define CHIP_NBLOCKS 128 -#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ -#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * The hymod board has 2 x 28F320J5 chips running in - * 16 bit mode, for a 32 bit wide bank. - */ - -typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ -typedef volatile bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ - -#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ -#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ - -#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) -#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) -#define BANK_NBLOCKS CHIP_NBLOCKS -#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) -#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) - -#define MAX_BANKS 1 /* only one bank possible */ - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_WIDTH - 1))) -#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ - (bank_size_t)(s) + (BANK_WIDTH - 1))) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_BLKSZ - 1))) -#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ - (bank_size_t)(s) + (BANK_BLKSZ - 1))) - -/* align bank addresses and sizes to bank boundaries */ -#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_SIZE - 1))) -#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ - (bank_size_t)(s) + (BANK_SIZE - 1))) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o)) - -/* get base address of bank b, given flash base address a */ -#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - (bank_size_t)(b) * BANK_SIZE) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - BANK_WIDTH) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - BANK_BLKSZ) -#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - BANK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - ((bank_size_t)(r) << BANK_WSHIFT)) - -/* make a bank address for each chip register address */ - -#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) -#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) -#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) -#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the bank_word_t type, and take into account the - * chip width and bank layout - */ - -#define BANK_FILL_WORD(o) ((bank_word_t)(o)) - -/* make a bank word value for each chip cmd/stat/rd value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) - -/* ID and Lock Configuration */ -#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) -#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) -#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) diff --git a/board/evb64260/local.h b/board/evb64260/local.h deleted file mode 100644 index 8a3f4b2944..0000000000 --- a/board/evb64260/local.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * include/local.h - local configuration options, board specific - */ - -#ifndef __LOCAL_H -#define __LOCAL_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* This tells U-Boot that the config options are compiled in */ -/* #undef ENV_IS_EMBEDDED */ -/* Don't touch this! U-Boot figures this out based on other - * magic. */ - -/* Uncomment and define any of the below options */ - -/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ - /* Note: If you defined CONFIG_EVB64260_750CX this */ - /* gets defined automatically. */ - -/* These want string arguments */ -/* #define CONFIG_BOOTARGS */ -/* #define CONFIG_BOOTCOMMAND */ -/* #define CONFIG_RAMBOOTCOMMAND */ -/* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CONFIG_SYS_AUTOLOAD */ -/* #define CONFIG_PREBOOT */ - -/* These don't */ - -/* #define CONFIG_BOOTDELAY */ -/* #define CONFIG_BAUDRATE */ -/* #define CONFIG_LOADS_ECHO */ -/* #define CONFIG_ETHADDR */ -/* #define CONFIG_ETH2ADDR */ -/* #define CONFIG_ETH3ADDR */ -/* #define CONFIG_IPADDR */ -/* #define CONFIG_SERVERIP */ -/* #define CONFIG_ROOTPATH */ -/* #define CONFIG_GATEWAYIP */ -/* #define CONFIG_NETMASK */ -/* #define CONFIG_HOSTNAME */ -/* #define CONFIG_BOOTFILE */ -/* #define CONFIG_LOADADDR */ - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:11:22:33:44:55 - -/* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:11:22:33:44:66 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:11:22:33:44:77 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ diff --git a/board/evb64260/memory.c b/board/evb64260/memory.c deleted file mode 100644 index e339854453..0000000000 --- a/board/evb64260/memory.c +++ /dev/null @@ -1,457 +0,0 @@ -/* Memory.c - Memory mappings and remapping functions */ - -/* Copyright - Galileo technology. */ - -/* modified by Josh Huber to clean some things up, and - * fit it into the U-Boot framework */ - -#include -#include - -/******************************************************************** -* memoryGetBankBaseAddress - Gets the base address of a memory bank -* - If the memory bank size is 0 then this base address has no meaning!!! -* -* -* INPUTS: MEMORY_BANK bank - The bank we ask for its base Address. -* OUTPUT: N/A -* RETURNS: Memory bank base address. -*********************************************************************/ -static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank) -{ - switch (bank) - { - case BANK0: - return SCS_0_LOW_DECODE_ADDRESS; - case BANK1: - return SCS_1_LOW_DECODE_ADDRESS; - case BANK2: - return SCS_2_LOW_DECODE_ADDRESS; - case BANK3: - return SCS_3_LOW_DECODE_ADDRESS; - } - return SCS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank) -{ - unsigned int base; - unsigned int regOffset=memoryGetBankRegOffset(bank); - - GT_REG_READ(regOffset,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* memoryGetDeviceBaseAddress - Gets the base address of a device. -* - If the device size is 0 then this base address has no meaning!!! -* -* -* INPUT: DEVICE device - The device we ask for its base address. -* OUTPUT: N/A -* RETURNS: Device base address. -*********************************************************************/ -static unsigned int memoryGetDeviceRegOffset(DEVICE device) -{ - switch (device) - { - case DEVICE0: - return CS_0_LOW_DECODE_ADDRESS; - case DEVICE1: - return CS_1_LOW_DECODE_ADDRESS; - case DEVICE2: - return CS_2_LOW_DECODE_ADDRESS; - case DEVICE3: - return CS_3_LOW_DECODE_ADDRESS; - case BOOT_DEVICE: - return BOOTCS_LOW_DECODE_ADDRESS; - } - return CS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetDeviceBaseAddress(DEVICE device) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset=memoryGetDeviceRegOffset(device); - - GT_REG_READ(regOffset, ®Base); - GT_REG_READ(regOffset+8, ®End); - - if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 20; - return regBase; -} - -/******************************************************************** -* memoryGetBankSize - Returns the size of a memory bank. -* -* -* INPUT: MEMORY_BANK bank - The bank we ask for its size. -* OUTPUT: N/A -* RETURNS: Memory bank size. -*********************************************************************/ -unsigned int memoryGetBankSize(MEMORY_BANK bank) -{ - unsigned int size,base; - unsigned int highValue; - unsigned int highAddress=memoryGetBankRegOffset(bank)+8; - - base = memoryGetBankBaseAddress(bank); - GT_REG_READ(highAddress,&highValue); - highValue = (highValue + 1) << 20; - if(base > highValue) - size=0; - else - size = highValue - base; - return size; -} - -/******************************************************************** -* memoryGetDeviceSize - Returns the size of a device memory space -* -* -* INPUT: DEVICE device - The device we ask for its base address. -* OUTPUT: N/A -* RETURNS: Size of a device memory space. -*********************************************************************/ -unsigned int memoryGetDeviceSize(DEVICE device) -{ - unsigned int size,base; - unsigned int highValue; - unsigned int highAddress=memoryGetDeviceRegOffset(device)+8; - - base = memoryGetDeviceBaseAddress(device); - GT_REG_READ(highAddress,&highValue); - if (highValue == 0xfff) - { - size = (~base) + 1; /* what the heck is this? */ - return size; - } - else - highValue = (highValue + 1) << 20; - - if(base > highValue) - size=0; - else - size = highValue - base; - return size; -} - -/******************************************************************** -* memoryGetDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width. -* The width is determine in registers: 'Device Parameters' -* registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device. -* at bits: [21:20]. -* -* INPUT: DEVICE device - Device number -* OUTPUT: N/A -* RETURNS: Device width in Bytes (1,2,4 or 8), 0 if error had occurred. -*********************************************************************/ -unsigned int memoryGetDeviceWidth(DEVICE device) -{ - unsigned int width; - unsigned int regValue; - - GT_REG_READ(DEVICE_BANK0PARAMETERS + device*4,®Value); - width = (regValue & 0x00300000) >> 20; - switch (width) - { - case 0: - return 1; - case 1: - return 2; - case 2: - return 4; - case 3: - return 8; - default: - return 0; - } -} - -bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength) -{ - unsigned int low=0xfff; - unsigned int high=0x0; - unsigned int regOffset=memoryGetBankRegOffset(bank); - - if(bankLength!=0) { - low = (bankBase >> 20) & 0xffff; - high=((bankBase+bankLength)>>20)-1; - } - -#ifdef DEBUG - { - unsigned int oldLow, oldHigh; - GT_REG_READ(regOffset,&oldLow); - GT_REG_READ(regOffset+8,&oldHigh); - - printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high); - } -#endif - - GT_REG_WRITE(regOffset,low); - GT_REG_WRITE(regOffset+8,high); - - return true; -} -bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength) -{ - /* TODO: what are appropriate "unmapped" values? */ - unsigned int low=0xfff; - unsigned int high=0x0; - unsigned int regOffset=memoryGetDeviceRegOffset(device); - - if(deviceLength != 0) { - low=deviceBase>>20; - high=((deviceBase+deviceLength)>>20)-1; - } else { - /* big problems in here... */ - /* this will HANG */ - } - - GT_REG_WRITE(regOffset,low); - GT_REG_WRITE(regOffset+8,high); - - return true; -} - - -/******************************************************************** -* memoryMapInternalRegistersSpace - Sets new base address for the internals -* registers. -* -* INPUTS: unsigned int internalRegBase - The new base address. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapInternalRegistersSpace(unsigned int internalRegBase) -{ - unsigned int currentValue; - unsigned int internalValue = internalRegBase; - - internalRegBase = (internalRegBase >> 20); - GT_REG_READ(INTERNAL_SPACE_DECODE,¤tValue); - internalRegBase = (currentValue & 0xffff0000) | internalRegBase; - GT_REG_WRITE(INTERNAL_SPACE_DECODE,internalRegBase); - INTERNAL_REG_BASE_ADDR = internalValue; - return true; -} - -/******************************************************************** -* memoryGetInternalRegistersSpace - Gets internal registers Base Address. -* -* INPUTS: unsigned int internalRegBase - The new base address. -* RETURNS: true on success, false on failure -*********************************************************************/ -unsigned int memoryGetInternalRegistersSpace(void) -{ - return INTERNAL_REG_BASE_ADDR; -} - -/******************************************************************** -* memorySetProtectRegion - This function modifys one of the 8 regions with -* one of the three protection mode. -* - Be advised to check the spec before modifying them. -* -* -* Inputs: CPU_PROTECT_REGION - one of the eight regions. -* CPU_ACCESS - general access. -* CPU_WRITE - read only access. -* CPU_CACHE_PROTECT - chache access. -* we defining CPU because there is another protect from the pci SIDE. -* Returns: false if one of the parameters is wrong and true else -*********************************************************************/ -bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memAccess, - MEMORY_ACCESS_WRITE memWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int protectHigh = baseAddress + regionLength; - - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,0x0000ffff); - GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,0); - return true; - } - baseAddress = (baseAddress & 0xfff00000) >> 20; - baseAddress = baseAddress | memAccess << 16 | memWrite << 17 - | cacheProtection << 18; - GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,baseAddress); - protectHigh = (protectHigh & 0xfff00000) >> 20; - GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,protectHigh - 1); - return true; -} - -/******************************************************************** -* memorySetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency. -* -* -* Inputs: SNOOP_REGION region - One of the four regions. -* SNOOP_TYPE snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* unsigned int baseAddress - Base Address of this region. -* unsigned int topAddress - Top Address of this region. -* Returns: false if one of the parameters is wrong and true else -*********************************************************************/ -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) ) - return false; - snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region; - snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region; - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); - GT_REG_WRITE(snoopXtopAddress,0); - return true; - } - baseAddress = baseAddress & 0xffff0000; - data = (baseAddress >> 16) | snoopType << 16; - GT_REG_WRITE(snoopXbaseAddress,data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); - return true; -} - -/******************************************************************** -* memoryRemapAddress - This fubction used for address remapping. -* -* -* Inputs: regOffset: remap register -* remapValue : -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue) -{ - unsigned int valueForReg; - valueForReg = (remapValue & 0xfff00000) >> 20; - GT_REG_WRITE(remapReg, valueForReg); - return true; -} - -/******************************************************************** -* memoryGetDeviceParam - This function used for getting device parameters from -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum) -{ - unsigned int valueOfReg; - unsigned int calcData; - - GT_REG_READ(DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg); - calcData = (0x7 & valueOfReg) + ((0x400000 & valueOfReg) >> 19); - deviceParam -> turnOff = calcData; /* Turn Off */ - - calcData = ((0x78 & valueOfReg) >> 3) + ((0x800000 & valueOfReg) >> 19); - deviceParam -> acc2First = calcData; /* Access To First */ - - calcData = ((0x780 & valueOfReg) >> 7) + ((0x1000000 & valueOfReg) >> 20); - deviceParam -> acc2Next = calcData; /* Access To Next */ - - calcData = ((0x3800 & valueOfReg) >> 11) + ((0x2000000 & valueOfReg) >> 22); - deviceParam -> ale2Wr = calcData; /* Ale To Write */ - - calcData = ((0x1c000 & valueOfReg) >> 14) + ((0x4000000 & valueOfReg) >> 23); - deviceParam -> wrLow = calcData; /* Write Active */ - - calcData = ((0xe0000 & valueOfReg) >> 17) + ((0x8000000 & valueOfReg) >> 24); - deviceParam -> wrHigh = calcData; /* Write High */ - - calcData = ((0x300000 & valueOfReg) >> 20); - switch (calcData) - { - case 0: - deviceParam -> deviceWidth = 1; /* one Byte - 8-bit */ - break; - case 1: - deviceParam -> deviceWidth = 2; /* two Bytes - 16-bit */ - break; - case 2: - deviceParam -> deviceWidth = 4; /* four Bytes - 32-bit */ - break; - case 3: - deviceParam -> deviceWidth = 8; /* eight Bytes - 64-bit */ - break; - default: - deviceParam -> deviceWidth = 1; - break; - } - return true; -} - -/******************************************************************** -* memorySetDeviceParam - This function used for setting device parameters to -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum) -{ - unsigned int valueForReg; - - if((deviceParam -> turnOff >= 0xf) || (deviceParam -> acc2First >= 0x1f) || - (deviceParam -> acc2Next >= 0x1f) || (deviceParam -> ale2Wr >= 0xf) || - (deviceParam -> wrLow >= 0xf) || (deviceParam -> wrHigh >= 0xf)) - return false; - valueForReg = (((deviceParam -> turnOff) & 0x7) | - (((deviceParam -> turnOff) & 0x8) << 19) | - (((deviceParam -> acc2First) & 0xf) << 3) | - (((deviceParam -> acc2First) & 0x10) << 19) | - (((deviceParam -> acc2Next) & 0xf) << 7) | - (((deviceParam -> acc2Next) & 0x10) << 20) | - (((deviceParam -> ale2Wr) & 0x7) << 11) | - (((deviceParam -> ale2Wr) & 0xf) << 22) | - (((deviceParam -> wrLow) & 0x7) << 14) | - (((deviceParam -> wrLow) & 0xf) << 23) | - (((deviceParam -> wrHigh) & 0x7) << 17) | - (((deviceParam -> wrHigh) & 0xf) << 24)); - /* insert the device width: */ - switch(deviceParam->deviceWidth) - { - case 1: - valueForReg = valueForReg | _8BIT; - break; - case 2: - valueForReg = valueForReg | _16BIT; - break; - case 4: - valueForReg = valueForReg | _32BIT; - break; - case 8: - valueForReg = valueForReg | _64BIT; - break; - default: - valueForReg = valueForReg | _8BIT; - break; - } - GT_REG_WRITE(DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg); - return true; -} diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S deleted file mode 100644 index f09528d429..0000000000 --- a/board/evb64260/misc.S +++ /dev/null @@ -1,182 +0,0 @@ -#include -#include <74xx_7xx.h> -#include - -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CONFIG_SYS_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CONFIG_SYS_MONITOR_LEN@h - ori r8, r8, CONFIG_SYS_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CONFIG_SYS_DFL_GT_REGS@h - ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - rlwinm r7, r4, 12, 16, 31 - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 - stw r18, 0x0(r18) - sync - blr diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c deleted file mode 100644 index 1a2ad20598..0000000000 --- a/board/evb64260/mpsc.c +++ /dev/null @@ -1,838 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpsc.c - driver for console over the MPSC. - */ - -#include -#include -#include - -#include -#include "mpsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -int (*mpsc_putchar)(char ch) = mpsc_putchar_early; - -static volatile unsigned int *rx_desc_base=NULL; -static unsigned int rx_desc_index=0; -static volatile unsigned int *tx_desc_base=NULL; -static unsigned int tx_desc_index=0; - -/* local function declarations */ -static int galmpsc_connect(int channel, int connect); -static int galmpsc_route_serial(int channel, int connect); -static int galmpsc_route_rx_clock(int channel, int brg); -static int galmpsc_route_tx_clock(int channel, int brg); -static int galmpsc_write_config_regs(int mpsc, int mode); -static int galmpsc_config_channel_regs(int mpsc); -static int galmpsc_set_char_length(int mpsc, int value); -static int galmpsc_set_stop_bit_length(int mpsc, int value); -static int galmpsc_set_parity(int mpsc, int value); -static int galmpsc_enter_hunt(int mpsc); -static int galmpsc_set_brkcnt(int mpsc, int value); -static int galmpsc_set_tcschar(int mpsc, int value); -static int galmpsc_set_snoop(int mpsc, int value); -static int galmpsc_shutdown(int mpsc); - -static int galsdma_set_RFT(int channel); -static int galsdma_set_SFM(int channel); -static int galsdma_set_rxle(int channel); -static int galsdma_set_txle(int channel); -static int galsdma_set_burstsize(int channel, unsigned int value); -static int galsdma_set_RC(int channel, unsigned int value); - -static int galbrg_set_CDV(int channel, int value); -static int galbrg_enable(int channel); -static int galbrg_disable(int channel); -static int galbrg_set_clksrc(int channel, int value); -static int galbrg_set_CUV(int channel, int value); - -static void galsdma_enable_rx(void); - -/* static int galbrg_reset(int channel); */ - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - - -/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */ -#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->arch.mirror_hack[0])) - -#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);} -#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M) - -#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);} -#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i]) - -/* make sure this isn't bigger than 16 long words (u-boot.h) */ -struct _tag_mirror_hack { - unsigned GALMPSC_PROTOCONF_REG_M[2]; /* 8008 */ - unsigned GALMPSC_CHANNELREG_1_M[2]; /* 800c */ - unsigned GALMPSC_CHANNELREG_2_M[2]; /* 8010 */ - unsigned GALBRG_0_CONFREG_M[2]; /* b200 */ - - unsigned GALMPSC_ROUTING_REGISTER_M; /* b400 */ - unsigned GALMPSC_RxC_ROUTE_M; /* b404 */ - unsigned GALMPSC_TxC_ROUTE_M; /* b408 */ - - unsigned int baudrate; /* current baudrate, for tsc delay calc */ -}; - -/* static struct _tag_mirror_hack *mh = NULL; */ - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int -mpsc_putchar_early(char ch) -{ - int mpsc=CHANNEL; - int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - galmpsc_set_tcschar(mpsc,ch); - GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int -mpsc_putchar_sdma(char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset((void *)p, 0, 8 * sizeof(unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int)ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int)&p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int)&p[0]; - p[11] = (unsigned int)&p[12]; -#endif - - FLUSH_DCACHE(&p[0], &p[8]); - - GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&p[0]); - GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&p[0]); - - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE(&p[1], &p[2]); - - while(p[1] & DESC_OWNER) { - udelay(100); - INVALIDATE_DCACHE(&p[1], &p[2]); - } - - return 0; -} - -char mpsc_getchar (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2, - CHANNEL, GALMPSC_REG_GAP); - temp |= (1 << 23); - GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2, CHANNEL, - GALMPSC_REG_GAP, temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - -int -mpsc_test_char(void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index*8]; - - INVALIDATE_DCACHE(&p[1], &p[2]); - - if (p[1] & DESC_OWNER) return 0; - else return 1; -} - -int -mpsc_init(int baud) -{ - memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack)); - MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff; - - /* BRG CONFIG */ - galbrg_set_baudrate(CHANNEL, baud); -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */ -#else - galbrg_set_clksrc(CHANNEL,0); -#endif - galbrg_set_CUV(CHANNEL, 0); - galbrg_enable(CHANNEL); - - /* Set up clock routing */ - galmpsc_connect(CHANNEL, GALMPSC_CONNECT); - galmpsc_route_serial(CHANNEL, GALMPSC_CONNECT); - galmpsc_route_rx_clock(CHANNEL, CHANNEL); - galmpsc_route_tx_clock(CHANNEL, CHANNEL); - - /* reset MPSC state */ - galmpsc_shutdown(CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle(CHANNEL); - galsdma_set_rxle(CHANNEL); - galsdma_set_RC(CHANNEL, 0xf); - galsdma_set_SFM(CHANNEL); - galsdma_set_RFT(CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs(CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs(CHANNEL); - galmpsc_set_char_length(CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - -void -mpsc_init2(void) -{ - int i; - - mpsc_putchar = mpsc_putchar_sdma; - - /* RX descriptors */ - rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) * - sizeof(unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int)rx_desc_base+32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */ - rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */ - rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i*8] = 0x00100000; - } - rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0]; - - FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]); - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) * - sizeof(unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int)tx_desc_base+32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i*8 + 5] = (unsigned int)0x23232323; - tx_desc_base[i*8 + 4] = (unsigned int)0x23232323; - tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4]; - tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8]; - tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i*8] = 0x00010001; - } - tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0]; - - FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]); - - udelay(100); - - galsdma_enable_rx(); - - return; -} - -int -galbrg_set_baudrate(int channel, int rate) -{ - int clock; - - galbrg_disable(channel); - -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - /* from tclk */ - clock = (CONFIG_SYS_BUS_CLK/(16*rate)) - 1; -#else - clock = (3686400/(16*rate)) - 1; -#endif - - galbrg_set_CDV(channel, clock); - - galbrg_enable(channel); - - MIRROR_HACK->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int -galbrg_set_CDV(int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp); - - return 0; -} - -static int -galbrg_enable(int channel) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp |= 0x00010000; - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_disable(int channel) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp &= 0xFFFEFFFF; - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_set_clksrc(int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP); - temp &= 0xFF83FFFF; - temp |= (value << 18); - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_set_CUV(int channel, int value) -{ - GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int -galbrg_reset(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int -galsdma_set_RFT(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_SFM(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_rxle(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_txle(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_RC(int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_burstsize(int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int -galmpsc_connect(int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int -galmpsc_route_serial(int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX); - - if ((channel == 0) && connect) - temp |= 0x00000100; - else if ((channel == 1) && connect) - temp |= 0x00001000; - else if ((channel == 0) && !connect) - temp &= ~0x00000100; - else - temp &= ~0x00001000; - - GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp); - - return 0; -} - -static int -galmpsc_route_rx_clock(int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE); - - if (channel == 0) - temp |= brg; - else - temp |= (brg << 8); - - GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp); - - return 0; -} - -static int -galmpsc_route_tx_clock(int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE); - - if (channel == 0) - temp |= brg; - else - temp |= (brg << 8); - - GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp); - - return 0; -} - -static int -galmpsc_write_config_regs(int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int -galmpsc_config_channel_regs(int mpsc) -{ - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0); - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1); - GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt(mpsc, 0x3); - galmpsc_set_tcschar(mpsc, 0xab); - - return 0; -} - -static int -galmpsc_set_brkcnt(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_tcschar(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_char_length(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_stop_bit_length(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); - temp |= (value << 14); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp); - - return 0; -} - -static int -galmpsc_set_parity(int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_enter_hunt(int mpsc) -{ - int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - temp |= 0x80000000; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); - - /* Should Poll on Enter Hunt bit, but the register is write-only */ - /* errata suggests pausing 100 system cycles */ - udelay(100); - - return 0; -} - - -static int -galmpsc_shutdown(int mpsc) -{ -#if 0 - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp); -#endif - - GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, - SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE(GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0); - - udelay(100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF, - 0x000000fc); - - udelay(100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - - udelay(100); - - return 0; -} - -static void -galsdma_enable_rx(void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt(CHANNEL); -} - -static int -galmpsc_set_snoop(int mpsc, int value) -{ - int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW; - int temp=GTREGREAD(reg); - if(value) - temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30); - else - temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30)); - GT_REG_WRITE(reg, temp); - return 0; -} diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h deleted file mode 100644 index 0747477fcb..0000000000 --- a/board/evb64260/mpsc.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_init2(void); -char mpsc_getchar(void); -int mpsc_test_char(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -extern int (*mpsc_putchar)(char ch); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c deleted file mode 100644 index 582f24c67b..0000000000 --- a/board/evb64260/pci.c +++ /dev/null @@ -1,760 +0,0 @@ -/* PCI.c - PCI functions */ - -/* Copyright - Galileo technology. */ - -#include -#include - -#include - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { -#ifdef CONFIG_ZUMA_V2 - {0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0}, - {0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0} -#else /* EVB??? This is a guess */ - {0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0}, - {0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0} -#endif -}; - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static unsigned int local_buses[] = { 0, 0 }; - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = PCI_BUS (pciDevNum); - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = PCI_BUS (pciDevNum); - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - if (pciDevNum == SELF) { /* This board */ - GT_REG_WRITE (pci_configuration_data[host], data); - } else { /* configuration Transaction over the pci. */ - - /* The PCI is working in LE Mode So it swap the Data. */ - GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data)); - } -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - if (pciDevNum == SELF) { /* This board */ - GT_REG_READ (pci_configuration_data[host], &data); - return data; - } else { /* The PCI is working in LE Mode So it swap the Data. */ - - GT_REG_READ (pci_configuration_data[host], &data); - return WORD_SWAP (data); - } -} - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 20) & 0xfff; - high = ((bankBase + bankLength) >> 20) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 20); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xfff) << 20; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - high &= 0xfff; - low &= 0xfff; - if (high <= low) - return 0; - return (high + 1 - low) << 20; -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + 4 * bank, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); -} - - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -/* - * - */ - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), value, - bus); - } - return 0; -} - -/* - * - */ - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - -#ifndef CONFIG_P3G4 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -#ifndef CONFIG_P3G4 - fixup_irq:gt_fixup_irq, -#endif - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -#ifndef CONFIG_P3G4 - fixup_irq:gt_fixup_irq, -#endif - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - -#ifndef CONFIG_P3G4 - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); -#endif - - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci0_hose.current_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - -#ifndef CONFIG_P3G4 - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); -#endif - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); -} diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c deleted file mode 100644 index 12b13083e7..0000000000 --- a/board/evb64260/sdram_init.c +++ /dev/null @@ -1,650 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include -#include -#include -#include -#include - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64260.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* #define DEBUG */ -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#define GB (1 << 30) - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; - int size; /* detected size, not from I2C but from dram_size() */ -} sdram_info_t; - -#ifdef DEBUG -void dump_dimm_info (struct sdram_info *d) -{ - static const char *ecc_legend[] = { "", " Parity", " ECC" }; - - printf ("dimm%s %sDRAM: %dMibytes:\n", - ecc_legend[d->ecc], - d->registered ? "R" : "", (d->size >> 20)); - printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n", - d->drb_size, d->tpar, d->tras_clocks, d->burst_len, - d->banks, d->slot); -} -#endif - -static int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - - return 0; -} - -#ifdef MAP_PCI -static int -memory_map_bank_pci (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ - PCI_HOST host; - - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } - return 0; -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -#ifdef CONFIG_ZUMA_V2 -static int check_dimm (uchar slot, sdram_info_t * info) -{ - /* assume 2 dimms, 2 banks each 256M - we dont have an - * dimm i2c so rely on the detection routines later */ - - memset (info, 0, sizeof (*info)); - - info->slot = slot; - info->banks = 2; /* Detect later */ - info->registered = 0; - info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit - but doesn't matter, both do same - thing in setup_sdram() */ - info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -#ifdef CONFIG_ECC - info->ecc = 0; /* Detect later */ -#endif /* CONFIG_ECC */ - return 0; -} - -#elif defined(CONFIG_P3G4) - -static int check_dimm (uchar slot, sdram_info_t * info) -{ - memset (info, 0, sizeof (*info)); - - if (slot) - return 0; - - info->slot = slot; - info->banks = 1; - info->registered = 0; - info->drb_size = 4; - info->tpar = 3; - info->tras_clocks = 6; - info->burst_len = 4; -#ifdef CONFIG_ECC - info->ecc = 2; -#endif - return 0; -} - -#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */ - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -static int check_dimm (uchar slot, sdram_info_t * info) -{ - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - uchar rows, cols, sdram_banks, supp_cal, width, cal_val; - ulong tmemclk; - uchar trp_clocks, trcd_clocks; - uchar data[128]; - - get_clocks (); - - tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */ - -#ifdef CONFIG_EVB64260_750CX - if (0 != slot) { - printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,"); - printf (" called with slot=%d insetad!\n", slot); - return 0; - } -#endif - DP (puts ("before i2c read\n")); - - ret = i2c_read (addr, 0, 128, data, 0); - - DP (puts ("after i2c read\n")); - - /* zero all the values */ - memset (info, 0, sizeof (*info)); - - if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); - return 0; - } - - /* first, do some sanity checks */ - if (data[2] != 0x4) { - printf ("Not SDRAM in slot %d\n", slot); - return 0; - } - - /* get various information */ - rows = data[3]; - cols = data[4]; - info->banks = data[5]; - sdram_banks = data[17]; - width = data[13] & 0x7f; - - DP (printf - ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks)); - - /* check if the memory is registered */ - if (data[21] & (BIT1 | BIT4)) - info->registered = 1; - -#ifdef CONFIG_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - info->ecc = (data[11] & 2) >> 1; -#endif - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (data[18] & 0x6) >> 1; - - /* compute the relevant clock values */ - trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk; - trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk; - info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk; - - DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n", - trp_clocks, trcd_clocks, info->tras_clocks)); - - /* try a CAS latency of 3 first... */ - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - DP (printf ("cal_val = %d\n", cal_val)); - - /* bummer, did't work... */ - if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); - return 0; - } - - /* get the largest delay -- these values need to all be the same - * see Res#6 */ - info->tpar = cal_val; - if (trp_clocks > info->tpar) - info->tpar = trp_clocks; - if (trcd_clocks > info->tpar) - info->tpar = trcd_clocks; - - DP (printf ("tpar set to: %d\n", info->tpar)); - -#ifdef CONFIG_SYS_BROKEN_CL2 - if (info->tpar == 2) { - info->tpar = 3; - DP (printf ("tpar fixed-up to: %d\n", info->tpar)); - } -#endif - /* compute the module DRB size */ - info->drb_size = - (((1 << (rows + cols)) * sdram_banks) * width) / _16M; - - DP (printf ("drb_size set to: %d\n", info->drb_size)); - - /* find the burst len */ - info->burst_len = data[16] & 0xf; - if ((info->burst_len & 8) == 8) { - info->burst_len = 1; - } else if ((info->burst_len & 4) == 4) { - info->burst_len = 0; - } else { - return 0; - } - - info->slot = slot; - return 0; -} -#endif /* ! CONFIG_ZUMA_V2 */ - -static int setup_sdram_common (sdram_info_t info[2]) -{ - ulong tmp; - int tpar = 2, tras_clocks = 5, registered = 1; - __maybe_unused int ecc = 2; - - if (!info[0].banks && !info[1].banks) - return 0; - - if (info[0].banks) { - if (info[0].tpar > tpar) - tpar = info[0].tpar; - if (info[0].tras_clocks > tras_clocks) - tras_clocks = info[0].tras_clocks; - if (!info[0].registered) - registered = 0; - if (info[0].ecc != 2) - ecc = 0; - } - - if (info[1].banks) { - if (info[1].tpar > tpar) - tpar = info[1].tpar; - if (info[1].tras_clocks > tras_clocks) - tras_clocks = info[1].tras_clocks; - if (!info[1].registered) - registered = 0; - if (info[1].ecc != 2) - ecc = 0; - } - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIGURATION); - - /* Turn on physical interleave if both DIMMs - * have even numbers of banks. */ - if ((info[0].banks == 0 || info[0].banks == 2) && - (info[1].banks == 0 || info[1].banks == 2)) { - /* physical interleave on */ - tmp &= ~(1 << 15); - } else { - /* physical interleave off */ - tmp |= (1 << 15); - } - - tmp |= (registered << 17); - - /* Use buffer 1 to return read data to the CPU - * See Res #12 */ - tmp |= (1 << 26); - - GT_REG_WRITE (SDRAM_CONFIGURATION, tmp); - DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION))); - - /* SDRAM timing */ - tmp = (((tpar == 3) ? 2 : 1) | - (((tpar == 3) ? 2 : 1) << 2) | - (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8)); - -#ifdef CONFIG_ECC - /* Setup ECC */ - if (ecc == 2) - tmp |= 1 << 13; -#endif /* CONFIG_ECC */ - - GT_REG_WRITE (SDRAM_TIMING, tmp); - DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n", - GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks)); - - /* SDRAM address decode register */ - /* program this with the default value */ - GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2); - DP (printf ("SDRAM decode: %08x\n", - GTREGREAD (SDRAM_ADDRESS_DECODE))); - - return 0; -} - -/* sets up the GT properly with information passed in */ -static int setup_sdram (sdram_info_t * info) -{ - ulong tmp; - ulong *addr = 0; - __maybe_unused ulong check; - int i; - - /* sanity checking */ - if (!info->banks) - return 0; - - /* ---------------------------- */ - /* Program the GT with the discovered data */ - - /* bank parameters */ - tmp = (0xf << 16); /* leave all virt bank pages open */ - - DP (printf ("drb_size: %d\n", info->drb_size)); - switch (info->drb_size) { - case 1: - tmp |= (1 << 14); - break; - case 4: - case 8: - tmp |= (2 << 14); - break; - case 16: - case 32: - tmp |= (3 << 14); - break; - default: - printf ("Error in dram size calculation\n"); - return 1; - } - - /* SDRAM bank parameters */ - /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ - GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp); - GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp); - DP (printf - ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, - info->slot * 2, (info->slot * 2) + 1, tmp)); - - /* set the SDRAM configuration for each bank */ - for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) { - DP (printf ("*** Running a MRS cycle for bank %d ***\n", i)); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ - GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3); - check = GTREGREAD (SDRAM_OPERATION_MODE); - - /* dummy write */ - *addr = 0; - - /* wait for the command to complete */ - while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0); - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION_MODE, 0); - check = GTREGREAD (SDRAM_OPERATION_MODE); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - DP (printf ("*** MRS cycle for bank %d done ***\n", i)); - } - - return 0; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* U-Boot interface function to SDRAM init - this is where all the - * controlling logic happens */ -phys_size_t initdram (int board_type) -{ - ulong checkbank[4] = {[0 ... 3] = 0 }; - int bank_no; - ulong total; - int nhr; - sdram_info_t dimm_info[2]; - - - /* first, use the SPD to get info about the SDRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SDRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - check_dimm (0, &dimm_info[0]); - - /* DIMM1 */ -#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */ - check_dimm (1, &dimm_info[1]); -#else /* CONFIG_EVB64260_750CX */ - memset (&dimm_info[1], 0, sizeof (sdram_info_t)); -#endif - - /* unmap all banks */ - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* Now, program the GT with the correct values */ - if (setup_sdram_common (dimm_info)) { - printf ("Setup common failed.\n"); - } - - if (setup_sdram (&dimm_info[0])) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (setup_sdram (&dimm_info[1])) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - total = 0; - if (dimm_info[0].banks > 0) - checkbank[0] = 1; - if (dimm_info[0].banks > 1) - checkbank[1] = 1; - if (dimm_info[0].banks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - if (dimm_info[1].banks > 0) - checkbank[2] = 1; - if (dimm_info[1].banks > 1) - checkbank[3] = 1; - if (dimm_info[1].banks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - /* Generic dram sizer: works even if we don't have i2c DIMMs, - * as long as the timing settings are more or less correct */ - - /* - * pass 1: size all the banks, using first bat (0-256M) - * limitation: we only support 256M per bank due to - * us only having 1 BAT for all DRAM - */ - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - DP (printf ("checking bank %d\n", bank_no)); - - memory_map_bank (bank_no, 0, GB / 4); - checkbank[bank_no] = dram_size (NULL, GB / 4); - memory_map_bank (bank_no, 0, 0); - - DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no])); - } - - /* - * pass 2: contiguously map each bank into physical address - * space. - */ - dimm_info[0].banks = dimm_info[1].banks = 0; - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - if (!checkbank[bank_no]) - continue; - - dimm_info[bank_no / 2].banks++; - dimm_info[bank_no / 2].size += checkbank[bank_no]; - - memory_map_bank (bank_no, total, checkbank[bank_no]); -#ifdef MAP_PCI - memory_map_bank_pci (bank_no, total, checkbank[bank_no]); -#endif - total += checkbank[bank_no]; - } - -#ifdef CONFIG_ECC -#ifdef CONFIG_ZUMA_V2 - /* - * We always enable ECC when bank 2 and 3 are unpopulated - * If we 2 or 3 are populated, we CAN'T support ECC. - * (Zuma boards only support ECC in banks 0 and 1; assume that - * in that configuration, ECC chips are mounted, even for stacked - * chips) - */ - if (checkbank[2] == 0 && checkbank[3] == 0) { - dimm_info[0].ecc = 2; - GT_REG_WRITE (SDRAM_TIMING, - GTREGREAD (SDRAM_TIMING) | (1 << 13)); - /* TODO: do we have to run MRS cycles again? */ - } -#endif /* CONFIG_ZUMA_V2 */ - - if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) { - puts ("[ECC] "); - } -#endif /* CONFIG_ECC */ - -#ifdef DEBUG - dump_dimm_info (&dimm_info[0]); - dump_dimm_info (&dimm_info[1]); -#endif - /* TODO: return at MOST 256M? */ - /* return total > GB/4 ? GB/4 : total; */ - return total; -} diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c deleted file mode 100644 index 3081fad21a..0000000000 --- a/board/evb64260/serial.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * serial.c - serial support for the gal ev board - */ - -/* supports both the 16650 duart and the MPSC */ - -#include -#include -#include -#include -#include - -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) -#include -#endif - -#include "serial.h" - -#include "mpsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) -const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1, - (NS16550_t) CONFIG_SYS_NS16550_COM2 }; -#endif - -#ifdef CONFIG_MPSC - -static int evb64260_serial_init(void) -{ -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; -#endif - - mpsc_init(gd->baudrate); - - /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CONFIG_SYS_INIT_CHAN1 - NS16550_reinit(COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif - return (0); -} - -static void evb64260_serial_putc(const char c) -{ - if (c == '\n') - mpsc_putchar('\r'); - - mpsc_putchar(c); -} - -static int evb64260_serial_getc(void) -{ - return mpsc_getchar(); -} - -static int evb64260_serial_tstc(void) -{ - return mpsc_test_char(); -} - -static void evb64260_serial_setbrg(void) -{ - galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate); -} - -#else /* ! CONFIG_MPSC */ - -static int evb64260_serial_init(void) -{ - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - (void)NS16550_init(COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - (void)NS16550_init(COM_PORTS[1], clock_divisor); -#endif - - return (0); -} - -static void evb64260_serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - - NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c); -} - -static int evb64260_serial_getc(void) -{ - return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -static int evb64260_serial_tstc(void) -{ - return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -static void evb64260_serial_setbrg(void) -{ - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - NS16550_reinit(COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif -} - -#endif /* CONFIG_MPSC */ - -static struct serial_device evb64260_serial_drv = { - .name = "evb64260_serial", - .start = evb64260_serial_init, - .stop = NULL, - .setbrg = evb64260_serial_setbrg, - .putc = evb64260_serial_putc, - .puts = default_serial_puts, - .getc = evb64260_serial_getc, - .tstc = evb64260_serial_tstc, -}; - -void evb64260_serial_initialize(void) -{ - serial_register(&evb64260_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &evb64260_serial_drv; -} - -#if defined(CONFIG_CMD_KGDB) -void -kgdb_serial_init(void) -{ -} - -void -putDebugChar (int c) -{ - serial_putc (c); -} - -void -putDebugStr (const char *str) -{ - serial_puts (str); -} - -int -getDebugChar (void) -{ - return serial_getc(); -} - -void -kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/evb64260/serial.h b/board/evb64260/serial.h deleted file mode 100644 index bac9253852..0000000000 --- a/board/evb64260/serial.h +++ /dev/null @@ -1,63 +0,0 @@ -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds deleted file mode 100644 index 712df6dd8f..0000000000 --- a/board/evb64260/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/74xx_7xx/start.o (.text*) - *(.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c deleted file mode 100644 index aa15fa015c..0000000000 --- a/board/evb64260/zuma_pbb.c +++ /dev/null @@ -1,220 +0,0 @@ -#include -#include - -#if defined(CONFIG_CMD_BSP) -#include -#endif - -#include -#include -#include "zuma_pbb.h" - -#undef DEBUG - -#define PAT_LO 0x00010203 -#define PAT_HI 0x04050607 - -static PBB_DMA_REG_MAP *zuma_pbb_reg = NULL; -static char test_buf1[2048]; -static char test_buf2[2048]; -void zuma_init_pbb(void); -int zuma_mbox_init(void); -int zuma_test_dma(int cmd, int size); - -int zuma_test_dma (int cmd, int size) -{ - static const char *const test_legend[] = { - "write", "verify", - "copy", "compare", - "write inc", "verify inc" - }; - register int i, j; - unsigned int p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff); - unsigned int p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff); - volatile unsigned int *ps = (unsigned int *) p1; - volatile unsigned int *pd = (unsigned int *) p2; - unsigned int funct, pat_lo = PAT_LO, pat_hi = PAT_HI; - DMA_INT_STATUS stat; - int ret = 0; - - if (!zuma_pbb_reg) { - printf ("not initted\n"); - return -1; - } - - if (cmd < 0 || cmd > 5) { - printf ("inv cmd %d\n", cmd); - return -1; - } - - if (cmd == 2 || cmd == 3) { - /* not implemented */ - return 0; - } - - if (size <= 0 || size > 1024) - size = 1024; - - size &= (~7); /* throw away bottom 3 bits */ - - p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff); - p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff); - - memset ((void *) p1, 0, size); - memset ((void *) p2, 0, size); - - for (i = 0; i < size / 4; i += 2) { - ps[i] = pat_lo; - ps[i + 1] = pat_hi; - if (cmd == 4 || cmd == 5) { - unsigned char *pl = (unsigned char *) &pat_lo; - unsigned char *ph = (unsigned char *) &pat_hi; - - for (j = 0; j < 4; j++) { - pl[j] += 8; - ph[j] += 8; - } - } - } - - funct = (1 << 31) | (cmd << 24) | (size); - - zuma_pbb_reg->int_mask.pci_bits.chan0 = - EOF_RX_FLAG | EOF_TX_FLAG | EOB_TX_FLAG; - - zuma_pbb_reg->debug_57 = PAT_LO; /* patl */ - zuma_pbb_reg->debug_58 = PAT_HI; /* path */ - - zuma_pbb_reg->debug_54 = cpu_to_le32 (p1); /* src 0x01b0 */ - zuma_pbb_reg->debug_55 = cpu_to_le32 (p2); /* dst 0x01b8 */ - zuma_pbb_reg->debug_56 = cpu_to_le32 (funct); /* func, 0x01c0 */ - - /* give DMA time to chew on things.. dont use DRAM or PCI */ - /* if you can avoid it. */ - do { - for (i = 0; i < 1000 * 10; i++); - } while (le32_to_cpu (zuma_pbb_reg->debug_56) & (1 << 31)); - - stat.word = zuma_pbb_reg->status.word; - zuma_pbb_reg->int_mask.word = 0; - - printf ("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0); - - printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56)); - printf ("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2], - ps[3]); - printf ("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2], - pd[3]); - printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56)); - - - if (cmd == 0 || cmd == 4) { - /* this is a write */ - if (!(stat.pci_bits.chan0 & EOF_RX_FLAG) || /* not done */ - (memcmp ((void *) ps, (void *) pd, size) != 0)) { /* cmp error */ - for (i = 0; i < size / 4; i += 2) { - if ((ps[i] != pd[i]) || (ps[i + 1] != pd[i + 1])) { - printf ("s @%p:%08x %08x\n", &ps[i], ps[i], ps[i + 1]); - printf ("d @%p:%08x %08x\n", &pd[i], pd[i], pd[i + 1]); - } - } - ret = -1; - } - } else { - /* this is a verify */ - if (!(stat.pci_bits.chan0 & EOF_TX_FLAG) || /* not done */ - (stat.pci_bits.chan0 & EOB_TX_FLAG)) { /* cmp error */ - printf ("%08x: %08x %08x\n", - le32_to_cpu (zuma_pbb_reg->debug_63), - zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62); - ret = -1; - } - } - - printf ("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size, - (ret == 0) ? "PASSED" : "FAILED"); - return 0; -} - -void zuma_init_pbb (void) -{ - unsigned int iobase; - pci_dev_t dev = - pci_find_device (VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); - - if (dev == -1) { - printf ("no zuma pbb\n"); - return; - } - - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase); - - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - - zuma_pbb_reg = (PBB_DMA_REG_MAP *)iobase; - - - if (!zuma_pbb_reg) { - printf ("zuma pbb bar none! (hah hah, get it?)\n"); - return; - } - - zuma_pbb_reg->int_mask.word = 0; - - printf ("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg, - zuma_pbb_reg->version.pci_bits.rev_major, - zuma_pbb_reg->version.pci_bits.rev_minor, - zuma_pbb_reg->timestamp); - -} - -#if defined(CONFIG_CMD_BSP) - -static int last_cmd = 4; /* write increment */ -static int last_size = 64; - -int -do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - zuma_init_pbb (); - return 0; -} - -int -do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc > 1) { - last_cmd = simple_strtoul (argv[1], NULL, 10); - } - if (argc > 2) { - last_size = simple_strtoul (argv[2], NULL, 10); - } - zuma_test_dma (last_cmd, last_size); - return 0; -} - -int -do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - zuma_mbox_init (); - return 0; -} - -U_BOOT_CMD( - zinit, 1, 0, do_zuma_init_pbb, - "init zuma pbb", - "\n" -); -U_BOOT_CMD( - zdtest, 3, 1, do_zuma_test_dma, - "run dma test", - "[cmd [count]]\n" - " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes" -); -U_BOOT_CMD( - zminit, 1, 0, do_zuma_init_mbox, - "init zuma mbox", - "\n" -); - -#endif diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h deleted file mode 100644 index 300b2fe8cc..0000000000 --- a/board/evb64260/zuma_pbb.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef ZUMA_PBB_H -#define ZUMA_PBB_H - -#define MAX_NUM_BUFFER_PER_RING 32 - -#ifdef __BIG_ENDIAN -#define cpu_bits _be_s_bits /* use with le32_to_cpu only */ -#define pci_bits _be_bits /* may contain swapped bytes, - but dont need le32_to_cpu */ -#endif - -#ifdef __LITTLE_ENDIAN -#define cpu_bits _le_bits -#define pci_bits _le_bits -#endif - -#define VENDOR_ID_ZUMA 0x1172 -#define DEVICE_ID_ZUMA_PBB 0x0004 - -#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */ -#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */ -#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */ -#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */ - -#define PBB_DMA_OWN_BIT 0x80000000 -#define PBB_DMA_LAST_BIT 0x40000000 - -#define EOF_RX_FLAG 1 /* bit 0 */ -#define EOB_RX_FLAG 2 /* bit 1 */ -#define EOF_TX_FLAG 4 /* bit 2 */ -#define EOB_TX_FLAG 8 /* bit 3 */ - -#define TX_MODE(m) (((m)&7) << 16) - -#define RX_DESC(i) (cs->rx_desc[i]) -#define TX_DESC(i) (cs->tx_desc[i]) - -#define RX_CONTROL(i) (RX_DESC(i).control.word) -#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size) -#define TX_CONTROL(i) (TX_DESC(i).control.word) - -#define RX_DATA_P(i) (&RX_DESC(i).ptr) -#define TX_DATA_P(i) (&TX_DESC(i).ptr) - -typedef volatile unsigned char V8; -typedef volatile unsigned short V16; -typedef volatile unsigned int V32; - -/* RAM descriptor layout */ -typedef struct _tag_dma_descriptor { - V32 ptr; - union { - struct { - V32 owner:1; - V32 last:1; - V32 reserved0: 10; - V32 tx_mode: 4; - - V32 reserved1: 5; - V32 size: 11; - } tx; - struct { - V32 owner:1; - V32 last:1; - V32 reserved0: 14; - - V32 reserved1: 5; - V32 size: 11; - } rx; - V32 word; - } control; -} DMA_DESCRIPTOR; - -/* - * NOTE: DO NOT USE structure to write non-word values... all registers - * MUST be written 4 bytes at a time in SI version 0. - * Non-word writes will result in "unaccessed" bytes written as zero. - * - * Byte reads are allowed. - * - * V32 pads are because the registers are spaced every 8 bytes (64 bits) - * - */ - -/* NOTE!!! 4 dwords */ -typedef struct _tag_dma_descriptor_ring { - DMA_DESCRIPTOR *base; - V32 pad1; /* skip high dword */ - volatile DMA_DESCRIPTOR *current; - V32 pad3; /* skip high dword */ -} DMA_DESCRIPTOR_RING; - -/* 1 dword */ -typedef union _tag_dma_generic { - struct { /* byte 3 2 1 0 */ - V32 chan7:4; /* bits 31-28 */ - V32 chan6:4; /* bits 27-24 */ - V32 chan5:4; /* bits 23-20 */ - V32 chan4:4; /* bits 19-16 */ - V32 chan3:4; /* bits 15-12 */ - V32 chan2:4; /* bits 11-8 */ - V32 chan1:4; /* bits 7-4 */ - V32 chan0:4; /* bits 3-0 */ - } _be_s_bits; - struct { /* byte 0 1 2 3 */ - V32 chan1:4; /* bits 7-4 */ - V32 chan0:4; /* bits 3-0 */ - V32 chan3:4; /* bits 15-12 */ - V32 chan2:4; /* bits 11-8 */ - V32 chan5:4; /* bits 23-20 */ - V32 chan4:4; /* bits 19-16 */ - V32 chan7:4; /* bits 31-28 */ - V32 chan6:4; /* bits 27-24 */ - } _be_bits; - struct { /* byte 0 1 2 3 */ - V32 chan0:4; /* bits 0-3 */ - V32 chan1:4; /* bits 4-7 */ - V32 chan2:4; /* bits 8-11 */ - V32 chan3:4; /* bits 12-15 */ - V32 chan4:4; /* bits 16-19 */ - V32 chan5:4; /* bits 20-23 */ - V32 chan6:4; /* bits 24-27 */ - V32 chan7:4; /* bits 28-31 */ - } _le_bits; - V8 byte[4]; - V32 word; -} DMA_RXTX_ENABLE, DMA_RX_DELETE, - DMA_INT_STATUS, DMA_INT_MASK, - DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK; - -/* 1 dword */ -typedef union _tag_dma_rx_timer{ - struct { - V32 res0:8; /* bits 32-24 */ - V32 res1:7; /* bits 23-17 */ - V32 enable:1; /* bit 16 */ - V32 value:16; /* bits 15-0 */ - } _be_s_bits; - struct { - /* crosses byte boundary. must use swap. */ - V32 s_value:16; /* bits 7-0,15-8 */ - V32 enable:1; /* bit 16 */ - V32 res1:7; /* bits 23-17 */ - V32 res0:8; /* bits 32-24 */ - } _be_bits; - struct { - V32 value:16; /* bits 0-15 */ - V32 enable:1; /* bit 16 */ - V32 res1:7; /* bits 17-23 */ - V32 res0:8; /* bits 24-32 */ - } _le_bits; - V8 byte[4]; - V32 word; -} DMA_RX_TIMER; - -/* NOTE!!!: 2 dwords */ -typedef struct _tag_dma_desc_level{ - union { - struct { - V32 res1:8; /* bits 31-24 */ - V32 res0:7; /* bits 23-17 */ - V32 write:1; /* bit 16 */ - V32 thresh:8; /* bits 15-8 */ - V32 level:8; /* bits 7-0 */ - } _be_s_bits; - struct { - V32 level:8; /* bits 7-0 */ - V32 thresh:8; /* bits 15-8 */ - V32 res0:7; /* bits 30-17 */ - V32 write:1; /* bit 16 */ - V32 res1:8; /* bits 31-24 */ - } _be_bits; - struct { - V32 level:8; /* bits 0-7 */ - V32 thresh:8; /* bits 8-15 */ - V32 write:1; /* bit 16 */ - V32 res0:7; /* bit 17-30 */ - V32 res1:8; /* bits 24-31 */ - } _le_bits; - V8 byte[4]; - V32 word; - } desc; - V32 pad1; -} DMA_DESC_LEVEL; - -typedef struct _tag_pbb_dma_reg_map { - /* 0-15 (0x000-0x078) */ - DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */ - - /* 16-31 (0x080-0x0f8) */ - DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */ - - /* 32/33 (0x100/0x108) */ - V32 reserved_32; - V32 pad_32; - V32 reserved_33; - V32 pad_33; - - /* 34 (0x110) */ - DMA_RXTX_ENABLE rxtx_enable; - V32 pad_34; - - /* 35 (0x118) */ - DMA_RX_DELETE rx_delete; - V32 pad_35; - - /* 36-38 (0x120-0x130) */ - DMA_INT_STATUS status; - V32 pad_36; - DMA_INT_STATUS last_status; - V32 pad_37; - DMA_INT_MASK int_mask; - V32 pad_38; - - /* 39/40 (0x138/0x140) */ - union { - /* NOTE!! 4 dwords */ - struct { - V32 channel_3:8; - V32 channel_2:8; - V32 channel_1:8; - V32 channel_0:8; - V32 pad1; - V32 channel_7:8; - V32 channel_6:8; - V32 channel_5:8; - V32 channel_4:8; - V32 pad3; - } _be_s_bits; - struct { - V32 channel_0:8; - V32 channel_1:8; - V32 channel_2:8; - V32 channel_3:8; - V32 pad1; - V32 channel_4:8; - V32 channel_5:8; - V32 channel_6:8; - V32 channel_7:8; - V32 pad3; - } _be_bits, _le_bits; - V8 byte[16]; - V32 word[4]; - } rx_size; - - /* 41/42 (0x148/0x150) */ - V32 reserved_41; - V32 pad_41; - V32 reserved_42; - V32 pad_42; - - /* 43/44 (0x158/0x160) */ - DMA_RX_LEVEL_STATUS rx_level_status; - V32 pad_43; - DMA_RX_LEVEL_INT_MASK rx_level_int_mask; - V32 pad_44; - - /* 45 (0x168) */ - DMA_RX_TIMER rx_timer; - V32 pad_45; - - /* 46 (0x170) */ - V32 reserved_46; - V32 pad_46; - - /* 47 (0x178) */ - V32 mbox_status; - V32 pad_47; - - /* 48/49 (0x180/0x188) */ - V32 mbox_out; - V32 pad_48; - V32 mbox_in; - V32 pad_49; - - /* 50 (0x190) */ - V32 config; - V32 pad_50; - - /* 51/52 (0x198/0x1a0) */ - V32 c2a_ctr; - V32 pad_51; - V32 a2c_ctr; - V32 pad_52; - - /* 53 (0x1a8) */ - union { - struct { - V32 rev_major:8; /* bits 31-24 */ - V32 rev_minor:8; /* bits 23-16 */ - V32 reserved:16; /* bits 15-0 */ - } _be_s_bits; - struct { - V32 s_reserved:16; /* bits 7-0, 15-8 */ - V32 rev_minor:8; /* bits 23-16 */ - V32 rev_major:8; /* bits 31-24 */ - } _be_bits; - struct { - V32 reserved:16; /* bits 0-15 */ - V32 rev_minor:8; /* bits 16-23 */ - V32 rev_major:8; /* bits 24-31 */ - } _le_bits; - V8 byte[4]; - V32 word; - } version; - V32 pad_53; - - /* 54-59 (0x1b0-0x1d8) */ - V32 debug_54; - V32 pad_54; - V32 debug_55; - V32 pad_55; - V32 debug_56; - V32 pad_56; - V32 debug_57; - V32 pad_57; - V32 debug_58; - V32 pad_58; - V32 debug_59; - V32 pad_59; - - /* 60 (0x1e0) */ - V32 timestamp; - V32 pad_60; - - /* 61-63 (0x1e8-0x1f8) */ - V32 debug_61; - V32 pad_61; - V32 debug_62; - V32 pad_62; - V32 debug_63; - V32 pad_63; - - /* 64-71 (0x200 - 0x238) */ - DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */ - - /* 72-98 (0x240 - 0x2f8) */ - /* reserved */ - - /* 96-127 (0x300 - 0x3f8) */ - /* mirrors (0x100 - 0x1f8) */ - -} PBB_DMA_REG_MAP; - - -#endif /* ZUMA_PBB_H */ diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c deleted file mode 100644 index 621c64cd82..0000000000 --- a/board/evb64260/zuma_pbb_mbox.c +++ /dev/null @@ -1,208 +0,0 @@ -#include -#include -#include -#include - -#include "zuma_pbb.h" -#include "zuma_pbb_mbox.h" - - -struct _zuma_mbox_dev zuma_mbox_dev; - - -static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data) -{ - unsigned int status, count = 0, i; - - status = (volatile int) le32_to_cpu(dev->sip->mbox_status); - - while ((status & OUT_PENDING) && count < 1000) { - count++; - for (i = 0; i < 1000; i++) - ; - status = (volatile int) le32_to_cpu(dev->sip->mbox_status); - } - if (count < 1000) { - /* if SET it means msg pending */ - /* printf("mbox real write %08x\n",data); */ - dev->sip->mbox_out = cpu_to_le32(data); - return 4; - } - - printf("mbox tx timeout\n"); - return 0; -} - -static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data) -{ - unsigned int status, count = 0, i; - - status = (volatile int) le32_to_cpu(dev->sip->mbox_status); - - while (!(status & IN_VALID) && count < 1000) { - count++; - for (i = 0; i < 1000; i++) - ; - status = (volatile int) le32_to_cpu(dev->sip->mbox_status); - } - if (count < 1000) { - /* if SET it means msg pending */ - *data = le32_to_cpu(dev->sip->mbox_in); - /*printf("mbox real read %08x\n", *data); */ - return 4; - } - printf("mbox rx timeout\n"); - return 0; -} - -static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) -{ - int ret; - - ret = zuma_mbox_write(&zuma_mbox_dev, out); - /*printf("write 0x%08x (%d bytes)\n", out, ret); */ - if (ret != 4) - return -1; - ret = zuma_mbox_read(&zuma_mbox_dev, in); - /*printf("read 0x%08x (%d bytes)\n", *in, ret); */ - if (ret != 4) - return -1; - return 0; -} - - -#define RET_IF_FAILED(x) if ((x) == -1) return -1 - -static int zuma_mbox_do_all_mailbox(void) -{ - unsigned int data_in; - unsigned short sdata_in; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); - memcpy(zuma_acc_mac + 2, &data_in, 4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); - sdata_in = data_in & 0xffff; - memcpy(zuma_acc_mac, &sdata_in, 2); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); - zuma_ip = data_in; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); - zuma_slot_bac = data_in >> 3; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); - zuma_console_baud = data_in & 0xffff; - zuma_debug_baud = data_in >> 16; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox - (ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); - memcpy(zuma_prv_mac + 2, &data_in, 4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox - (ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); - sdata_in = data_in & 0xffff; - memcpy(zuma_prv_mac, &sdata_in, 2); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); - - return 0; -} - - -static void zuma_mbox_dump(void) -{ - unsigned short s; - unsigned int i; - - memcpy(&s, &zuma_acc_mac, sizeof(s)); - memcpy(&i, &zuma_acc_mac[2], sizeof(i)); - printf("ACC MAC=%04x%08x\n", s, i); - - memcpy(&s, &zuma_prv_mac, sizeof(s)); - memcpy(&s, &zuma_prv_mac[2], sizeof(i)); - printf("PRV MAC=%04x%08x\n", s, i); - - printf("slot:bac=%d:%d\n", - (zuma_slot_bac >> 2) & 0xf, - zuma_slot_bac & 0x3); - - printf("BAUD1=%d BAUD2=%d\n", - zuma_console_baud, - zuma_debug_baud); -} - - -static void zuma_mbox_setenv(void) -{ - char *data, buf[32]; - unsigned char save = 0; - - data = getenv("baudrate"); - - if (!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { - sprintf(buf, "%6d", zuma_console_baud); - setenv("baudrate", buf); - save = 1; - printf("baudrate doesn't match from mbox\n"); - } - - ip_to_string(zuma_ip, buf); - setenv("ipaddr", buf); - - sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", - zuma_prv_mac[0], - zuma_prv_mac[1], - zuma_prv_mac[2], - zuma_prv_mac[3], zuma_prv_mac[4], zuma_prv_mac[5]); - setenv("ethaddr", buf); - - sprintf(buf, "%02x", zuma_slot_bac); - setenv("bacslot", buf); - - if (save) - saveenv(); -} - -/** - * zuma_mbox_init: - */ - -int zuma_mbox_init(void) -{ - unsigned int iobase; - - memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); - - zuma_mbox_dev.dev = - pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); - - if (zuma_mbox_dev.dev == -1) { - printf("no zuma pbb\n"); - return -1; - } - - pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); - - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - - zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) iobase; - - zuma_mbox_dev.sip->int_mask.word = 0; - - printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, - zuma_mbox_dev.sip->version.pci_bits.rev_major, - zuma_mbox_dev.sip->version.pci_bits.rev_minor, - zuma_mbox_dev.sip->timestamp); - - if (zuma_mbox_do_all_mailbox() == -1) { - printf("mailbox failed.. no ACC?\n"); - return -1; - } - - zuma_mbox_dump(); - - zuma_mbox_setenv(); - - return 0; -} diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h deleted file mode 100644 index b4a4c0cf7e..0000000000 --- a/board/evb64260/zuma_pbb_mbox.h +++ /dev/null @@ -1,43 +0,0 @@ -#define IN_VALID 1 -#define OUT_PENDING 2 - -enum { - ZUMA_MBOXMSG_DONE, - ZUMA_MBOXMSG_MACL, - ZUMA_MBOXMSG_MACH, - ZUMA_MBOXMSG_IP, - ZUMA_MBOXMSG_SLOT, - ZUMA_MBOXMSG_RESET, - ZUMA_MBOXMSG_BAUD, - ZUMA_MBOXMSG_START, - ZUMA_MBOXMSG_ENG_PRV_MACL, - ZUMA_MBOXMSG_ENG_PRV_MACH, - - MBOXMSG_LAST -}; - -struct zuma_mailbox_info { - unsigned char acc_mac[6]; - unsigned char prv_mac[6]; - unsigned int ip; - unsigned int slot_bac; - unsigned int console_baud; - unsigned int debug_baud; -}; - -struct _zuma_mbox_dev { - pci_dev_t dev; - PBB_DMA_REG_MAP *sip; - struct zuma_mailbox_info mailbox; -}; - -#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac -#define zuma_acc_mac zuma_mbox_dev.mailbox.acc_mac -#define zuma_ip zuma_mbox_dev.mailbox.ip -#define zuma_slot_bac zuma_mbox_dev.mailbox.slot_bac -#define zuma_console_baud zuma_mbox_dev.mailbox.console_baud -#define zuma_debug_baud zuma_mbox_dev.mailbox.debug_baud - - -extern struct _zuma_mbox_dev zuma_mbox_dev; -extern int zuma_mbox_init (void); diff --git a/board/exmeritus/hww1u1a/Makefile b/board/exmeritus/hww1u1a/Makefile deleted file mode 100644 index e441c14f9a..0000000000 --- a/board/exmeritus/hww1u1a/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_DDR_SPD) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c deleted file mode 100644 index 36d02ad5d8..0000000000 --- a/board/exmeritus/hww1u1a/ddr.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include - -#include -#include - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * We only support one DIMM, so according to the P2020 docs we should - * set the options as follows: - */ - popts->cs_local_opts[0].odt_rd_cfg = 0; - popts->cs_local_opts[0].odt_wr_cfg = 4; - popts->cs_local_opts[1].odt_rd_cfg = 0; - popts->cs_local_opts[1].odt_wr_cfg = 0; - popts->half_strength_driver_enable = 0; - - /* Manually configured for our static clock rate */ - popts->clk_adjust = 4; - popts->cpo_override = 4; - popts->write_data_delay = 2; - popts->twoT_en = 0; -} diff --git a/board/exmeritus/hww1u1a/gpios.h b/board/exmeritus/hww1u1a/gpios.h deleted file mode 100644 index 704dc630d3..0000000000 --- a/board/exmeritus/hww1u1a/gpios.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2010 eXMeritus, A Boeing Company - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */ -#define GPIO_CPU_ID (1UL << (31 - 8)) -#define GPIO_BLUE_LED (1UL << (31 - 9)) -#define GPIO_DIMM_RESET (1UL << (31 - 10)) -#define GPIO_USB_RESET (1UL << (31 - 11)) -#define GPIO_UNUSED_12 (1UL << (31 - 12)) -#define GPIO_GETH0_RESET (1UL << (31 - 13)) -#define GPIO_RS422_RE (1UL << (31 - 14)) -#define GPIO_RS422_DE (1UL << (31 - 15)) -#define IRQ_I2CINT (1UL << (31 - 20)) -#define IRQ_FANINT (1UL << (31 - 21)) -#define IRQ_DIMM_EVENT (1UL << (31 - 22)) - -#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET) - -/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ -#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0)) -#define GPIO_CPUA_CPU_READY (1UL << (31 - 1)) -#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2)) -#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3)) -#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */ -#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */ -#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */ -#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */ -#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16)) -#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17)) -#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18)) -#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19)) - -/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ -#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0)) -#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1)) -#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2)) -#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3)) -#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4)) -#define GPIO_CPUB_CPU_READY (1UL << (31 - 5)) -#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6)) -#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7)) -#define IRQ_CPUB_SD_1A (1UL << (31 - 16)) -#define IRQ_CPUB_SD_2B (1UL << (31 - 17)) -#define IRQ_CPUB_SD_2A (1UL << (31 - 18)) -#define IRQ_CPUB_SD_1B (1UL << (31 - 19)) - -/* If it isn't CPU A then it's CPU B */ -static inline unsigned int hww1u1a_is_cpu_a(void) -{ - return !mpc85xx_gpio_get(GPIO_CPU_ID); -} diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c deleted file mode 100644 index 9611f6d64e..0000000000 --- a/board/exmeritus/hww1u1a/hww1u1a.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright 2009-2011 eXMeritus, A Boeing Company - * Copyright 2007-2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gpios.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - unsigned int gpio_high = 0; - unsigned int gpio_low = 0; - unsigned int gpio_in = 0; - unsigned int i; - - puts("Board: HWW-1U-1A "); - - /* - * First just figure out which CPU we're on, then use that to - * configure the lists of other GPIOs to be programmed. - */ - mpc85xx_gpio_set_in(GPIO_CPU_ID); - if (hww1u1a_is_cpu_a()) { - puts("CPU A\n"); - - /* We want to turn on some LEDs */ - gpio_high |= GPIO_CPUA_CPU_READY; - gpio_low |= GPIO_CPUA_DEBUG_LED1; - gpio_low |= GPIO_CPUA_DEBUG_LED2; - - /* Disable the unused transmitters */ - gpio_low |= GPIO_CPUA_TDIS1A; - gpio_high |= GPIO_CPUA_TDIS1B; - gpio_low |= GPIO_CPUA_TDIS2A; - gpio_high |= GPIO_CPUA_TDIS2B; - } else { - puts("CPU B\n"); - - /* We want to turn on some LEDs */ - gpio_high |= GPIO_CPUB_CPU_READY; - gpio_low |= GPIO_CPUB_DEBUG_LED1; - gpio_low |= GPIO_CPUB_DEBUG_LED2; - - /* Enable the appropriate receivers */ - gpio_high |= GPIO_CPUB_RMUX_SEL0A; - gpio_high |= GPIO_CPUB_RMUX_SEL0B; - gpio_low |= GPIO_CPUB_RMUX_SEL1A; - gpio_low |= GPIO_CPUB_RMUX_SEL1B; - } - - /* These GPIOs are common */ - gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT; - gpio_low |= GPIO_RS422_RE; - gpio_high |= GPIO_RS422_DE; - - /* Ok, now go ahead and program all of those in one go */ - mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in, - gpio_high|gpio_low, - gpio_high); - - /* - * If things have been taken out of reset early (for example, by one - * of the BDI3000 debuggers), then we need to put them back in reset - * and delay a while before we continue. - */ - if (mpc85xx_gpio_get(GPIO_RESETS)) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - puts("Debugger detected... extra device reset enabled!\n"); - - /* Put stuff into reset and disable the DDR controller */ - mpc85xx_gpio_set_low(GPIO_RESETS); - out_be32(&ddr->sdram_cfg, 0x00000000); - - puts(" Waiting 1 sec for reset..."); - for (i = 0; i < 10; i++) { - udelay(100000); - puts("."); - } - puts("\n"); - } - - /* Now bring everything back out of reset again */ - mpc85xx_gpio_set_high(GPIO_RESETS); - return 0; -} - -/* - * This little shell function just returns whether or not it's CPU A. - * It can be used to select the right device-tree when booting, etc. - */ -int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - if (argc > 1) - cmd_usage(cmdtp); - - if (hww1u1a_is_cpu_a()) - return 0; - else - return 1; -} -U_BOOT_CMD( - test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a, - "Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board", - "" -); - -/* Create a prompt-like string: "uboot@HOSTNAME% " */ -#define PROMPT_PREFIX "uboot@exm" -#define PROMPT_SUFFIX "% " - -/* This function returns a PS1 prompt based on the serial number */ -static char *hww1u1a_prompt; -const char *hww1u1a_get_ps1(void) -{ - unsigned long len, i, j; - const char *serialnr; - - /* If our prompt was already set, just use that */ - if (hww1u1a_prompt) - return hww1u1a_prompt; - - /* Use our serial number if present, otherwise a default */ - serialnr = getenv("serial#"); - if (!serialnr || !serialnr[0]) - serialnr = "999999-X"; - - /* - * We will turn the serial number into a hostname by: - * (A) Delete all non-alphanumerics. - * (B) Lowercase all letters. - * (C) Prefix "exm". - * (D) Suffix "a" for CPU A and "b" for CPU B. - */ - for (i = 0, len = 0; serialnr[i]; i++) { - if (isalnum(serialnr[i])) - len++; - } - - len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */ - hww1u1a_prompt = malloc(len); - if (!hww1u1a_prompt) - return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX; - - /* Now actually fill it in */ - i = 0; - - /* Handle the prefix */ - for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++) - hww1u1a_prompt[i++] = PROMPT_PREFIX[j]; - - /* Now the serial# part of the hostname */ - for (j = 0; serialnr[j]; j++) - if (isalnum(serialnr[j])) - hww1u1a_prompt[i++] = tolower(serialnr[j]); - - /* Now the CPU id ("a" or "b") */ - hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b'; - - /* Finally the suffix */ - for (j = 0; j < sizeof(PROMPT_SUFFIX); j++) - hww1u1a_prompt[i++] = PROMPT_SUFFIX[j]; - - /* This should all have added up, but just in case */ - hww1u1a_prompt[len - 1] = '\0'; - - /* Now we're done */ - return hww1u1a_prompt; -} - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap bootflash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for FLASH */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - struct tsec_info_struct tsec_info[4]; - struct fsl_pq_mdio_info mdio_info; - - SET_STD_TSEC_INFO(tsec_info[0], 1); - SET_STD_TSEC_INFO(tsec_info[1], 2); - SET_STD_TSEC_INFO(tsec_info[2], 3); - - if (hww1u1a_is_cpu_a()) - tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA; - else - tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB; - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, 3); - return pci_eth_init(bis); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - FT_FSL_PCI_SETUP; -} diff --git a/board/exmeritus/hww1u1a/law.c b/board/exmeritus/hww1u1a/law.c deleted file mode 100644 index c7dc58d596..0000000000 --- a/board/exmeritus/hww1u1a/law.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/exmeritus/hww1u1a/tlb.c b/board/exmeritus/hww1u1a/tlb.c deleted file mode 100644 index 7f5a36f1eb..0000000000 --- a/board/exmeritus/hww1u1a/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Boot page */ - SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, - CONFIG_BPTR_VIRT_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, - CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* - * W**G* - FLASH (Will be *I*G* after relocation to RAM) - * - * This maps both SPI FLASH chips (128MByte per chip) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * *I*G* - PCI memory - * - * We have 1.5GB total PCI-E memory space to map and we want to use - * the minimum possible number of TLB entries. Since Book-E TLB - * entries are sized in powers of 4, we use 1GB + 256MB + 256MB. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, - CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* - * *I*G* - PCI I/O - * - * This one entry covers all 3 64k PCI-E I/O windows - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, - CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/fads/Makefile b/board/fads/Makefile deleted file mode 100644 index 4c70032306..0000000000 --- a/board/fads/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o lamp.o pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/fads/README b/board/fads/README deleted file mode 100644 index 0873682787..0000000000 --- a/board/fads/README +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2000 - * Dave Ellis, SIXNET, dge@sixnetio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -Using the Motorola MPC8XXFADS development board -=============================================== - -CONFIGURATIONS --------------- - -There are ready-to-use default configurations available for the -FADS823, FADS850SAR and FADS860T. The FADS860T configuration also -works for the 855T processor. - -LOADING U-Boot INTO FADS FLASH MEMORY --------------------------------------- - -MPC8BUG can load U-Boot into the FLASH memory using LOADF. - - loadf u-boot.srec 100000 - - -STARTING U-Boot FROM MPC8BUG ------------------------------ - -To start U-Boot from MPC8BUG: - -1. Reset the board: - reset :h - -2. Change BR0 and OR0 back to their values at reset: - rms memc br0 00000001 - rms memc or0 00000d34 - -3. Modify DER so MPC8BUG gets control only when it should: - rms der 2002000f - -4. Start as if from reset: - go 100 - -This is NOT exactly the same as starting U-Boot without -MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset. -After it does the reset it writes SYPCR (to disable the watchdog) -and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots -of other initialization). That is why it is necessary to set BR0 -and OR0 to map the FLASH everywhere. U-Boot can't turn on the -watchdog after that, since MPC8BUG has used the only chance to write -to SYPCR. - -Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets -U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T -processor (your mileage may vary). It is probably better (and a lot -easier) just to accept having the watchdog disabled when the debug -cable is connected. - -in MPC8BUG: - reset :h - rms memc br0 00000001 - rms memc or0 00000d34 - rms der 2000f - go 100 - -Now U-Boot is running with the MPC8BUG value for SYPCR. Use the -U-Boot 'reset' command to reset the board. - =>reset -Next, in MPC8BUG: - rms der 2000f - go - -Now U-Boot is running with the U-Boot value for SYPCR. diff --git a/board/fads/fads.c b/board/fads/fads.c deleted file mode 100644 index 3fe318f765..0000000000 --- a/board/fads/fads.c +++ /dev/null @@ -1,935 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define _NOT_USED_ 0xFFFFFFFF - -/* ========================================================================= */ - -#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ - -#if defined(CONFIG_DRAM_50MHZ) -/* 50MHz tables */ -static const uint dram_60ns[] = -{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04, - 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c, - 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44, - 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00, - 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint dram_70ns[] = -{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, - 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, - 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00, - 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04, - 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, - 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_60ns[] = -{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, - 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c, - 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c, - 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_70ns[] = -{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04, - 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c, - 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00, - 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00, - 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, - 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -#elif defined(CONFIG_DRAM_25MHZ) - -/* 25MHz tables */ - -static const uint dram_60ns[] = -{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint dram_70ns[] = -{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_60ns[] = -{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c, - 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48, - 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_70ns[] = -{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00, - 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00, - 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00, - 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00, - 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; -#else -#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ -#endif - -/* ------------------------------------------------------------------------- */ -static int _draminit (uint base, uint noMbytes, uint edo, uint delay) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* init upm */ - - switch (delay) { - case 70: - if (edo) { - upmconfig (UPMA, (uint *) edo_70ns, - sizeof (edo_70ns) / sizeof (uint)); - } else { - upmconfig (UPMA, (uint *) dram_70ns, - sizeof (dram_70ns) / sizeof (uint)); - } - - break; - - case 60: - if (edo) { - upmconfig (UPMA, (uint *) edo_60ns, - sizeof (edo_60ns) / sizeof (uint)); - } else { - upmconfig (UPMA, (uint *) dram_60ns, - sizeof (dram_60ns) / sizeof (uint)); - } - - break; - - default: - return -1; - } - - memctl->memc_mptpr = 0x0400; /* divide by 16 */ - - switch (noMbytes) { - case 4: /* 4 Mbyte uses only CS2 */ -#ifdef CONFIG_ADS - memctl->memc_mamr = 0xc0a21114; -#else - memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ -#endif - memctl->memc_or2 = 0xffc00800; /* 4M */ - break; - - case 8: /* 8 Mbyte uses both CS3 and CS2 */ - memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ - memctl->memc_or3 = 0xffc00800; /* 4M */ - memctl->memc_br3 = 0x00400081 + base; - memctl->memc_or2 = 0xffc00800; /* 4M */ - break; - - case 16: /* 16 Mbyte uses only CS2 */ -#ifdef CONFIG_ADS /* XXX: why PTA=0x60 only in 16M case? - NTL */ - memctl->memc_mamr = 0x60b21114; /* PTA 0x60 AMA 011 */ -#else - memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ -#endif - memctl->memc_or2 = 0xff000800; /* 16M */ - break; - - case 32: /* 32 Mbyte uses both CS3 and CS2 */ - memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ - memctl->memc_or3 = 0xff000800; /* 16M */ - memctl->memc_br3 = 0x01000081 + base; - memctl->memc_or2 = 0xff000800; /* 16M */ - break; - - default: - return -1; - } - - memctl->memc_br2 = 0x81 + base; /* use upma */ - - *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */ - - /* if no dimm is inserted, noMbytes is still detected as 8m, so - * sanity check top and bottom of memory */ - - /* check bytes / 2 because get_ram_size tests at base+bytes, which - * is not mapped */ - if (noMbytes == 8) - if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) { - *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */ - return -1; - } - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static void _dramdisable(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br2 = 0x00000000; - memctl->memc_br3 = 0x00000000; - - /* maybe we should turn off upma here or something */ -} -#endif /* !CONFIG_MPC885ADS */ - -/* ========================================================================= */ - -#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */ - -#if defined(CONFIG_SDRAM_100MHZ) - -/* ------------------------------------------------------------------------- */ -/* sdram table by Dan Malek */ - -/* This has the stretched early timing so the 50 MHz - * processor can make the 100 MHz timing. This will - * work at all processor speeds. - */ - -#ifdef SDRAM_ALT_INIT_SEQENCE -# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ -#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0 -# define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */ -# define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */ -#else -# define SDRAM_MxMR_PTx 195 -# define UPM_MRS_ADDR 0x11 -# define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */ -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -static const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04, - 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_, - - /* burst read. (offset 8 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04, - 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00, - 0x1ff77c45, - - /* precharge + MRS. (offset 11 in upm RAM) */ - 0xeffbbc04, 0x1ff77c34, 0xefeabc34, - 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write. (offset 18 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04, - 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write. (offset 20 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, - 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh. (offset 30 in upm RAM) */ - 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* exception. (offset 3c in upm RAM) */ - 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ }; - -#elif defined(CONFIG_SDRAM_50MHZ) - -/* ------------------------------------------------------------------------- */ -/* sdram table stolen from the fads manual */ -/* for chip MB811171622A-100 */ - -/* this table is for 32-50MHz operation */ -#ifdef SDRAM_ALT_INIT_SEQENCE -# define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ -# define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */ -# define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */ -# define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */ -# define SDRAM_MPTRVALUE 0x400 -#define SDRAM_MARVALUE 0x88 -#else -# define SDRAM_MxMR_PTx 128 -# define UPM_MRS_ADDR 0x5 -# define UPM_REFRESH_ADDR 0x30 -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -static const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* precharge + MRS. (offset 5 in upm RAM) */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -/* ------------------------------------------------------------------------- */ -#else -#error SDRAM not correctly configured -#endif -/* ------------------------------------------------------------------------- */ - -/* - * Memory Periodic Timer Prescaler - */ - -#define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */ -#define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */ - -/* ------------------------------------------------------------------------- */ -#ifdef SDRAM_ALT_INIT_SEQENCE -/* ------------------------------------------------------------------------- */ - -static int _initsdram(uint base, uint noMbytes) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = SDRAM_MPTPRVALUE; - - /* Configure the refresh (mostly). This needs to be - * based upon processor clock speed and optimized to provide - * the highest level of performance. For multiple banks, - * this time has to be divided by the number of banks. - * Although it is not clear anywhere, it appears the - * refresh steps through the chip selects for this UPM - * on each refresh cycle. - * We have to be careful changing - * UPM registers after we ask it to run these commands. - */ - - memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ - memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */ - - udelay(200); - - /* Now run the precharge/nop/mrs commands. - */ - - memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */ - /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */ - udelay(200); - - /* Run 8 refresh cycles */ - - memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/ - /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */ - - udelay(200); - - memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */ - memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */ - /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */ - - udelay(200); - - memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ - - memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); - memctl->memc_br4 = SDRAM_BR4VALUE | base; - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#else /* !SDRAM_ALT_INIT_SEQUENCE */ -/* ------------------------------------------------------------------------- */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -# define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -# define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -# define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -# define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MxMR settings for SDRAM - */ - -/* 8 column SDRAM */ -# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -/* 9 column SDRAM */ -# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -static int _initsdram(uint base, uint noMbytes) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = MPTPR_2BK_4K; - memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */ - - /* map CS 4 */ - memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); - memctl->memc_br4 = SDRAM_BR4VALUE | base; - - /* Perform SDRAM initilization */ -# ifdef UPM_NOP_ADDR /* not currently in UPM table */ - /* step 1: nop */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(0) | UPM_NOP_ADDR; -# endif - - /* step 2: delay */ - udelay(200); - -# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */ - /* step 3: precharge */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(4) | UPM_PRECHARGE_ADDR; -# endif - - /* step 4: refresh */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(2) | UPM_REFRESH_ADDR; - - /* - * note: for some reason, the UPM values we are using include - * precharge with MRS - */ - - /* step 5: mrs */ - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(1) | UPM_MRS_ADDR; - -# ifdef UPM_NOP_ADDR - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(0) | UPM_NOP_ADDR; -# endif - /* - * Enable refresh - */ - - memctl->memc_mbmr |= MBMR_PTBE; - return 0; -} -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -/* ------------------------------------------------------------------------- */ - -static void _sdramdisable(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br4 = 0x00000000; - - /* maybe we should turn off upmb here or something */ -} - -/* ------------------------------------------------------------------------- */ - -static int initsdram(uint base, uint *noMbytes) -{ - uint m = CONFIG_SYS_SDRAM_SIZE>>20; - - /* _initsdram needs access to sdram */ - *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */ - - if(!_initsdram(base, m)) - { - *noMbytes += m; - return 0; - } - else - { - *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */ - - _sdramdisable(); - - return -1; - } -} - -#endif /* CONFIG_FADS */ - -/* ========================================================================= */ - -phys_size_t initdram (int board_type) -{ - uint sdramsz = 0; /* size of sdram in Mbytes */ - uint m = 0; /* size of dram in Mbytes */ -#ifndef CONFIG_MPC885ADS - uint base = 0; /* base of dram in bytes */ - uint k, s; -#endif - -#ifdef CONFIG_FADS - if (!initsdram (0x00000000, &sdramsz)) { -#ifndef CONFIG_MPC885ADS - base = sdramsz << 20; -#endif - printf ("(%u MB SDRAM) ", sdramsz); - } -#endif -#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ - k = (*((uint *) BCSR2) >> 23) & 0x0f; - - switch (k & 0x3) { - /* "MCM36100 / MT8D132X" */ - case 0x00: - m = 4; - break; - - /* "MCM36800 / MT16D832X" */ - case 0x01: - m = 32; - break; - /* "MCM36400 / MT8D432X" */ - case 0x02: - m = 16; - break; - /* "MCM36200 / MT16D832X ?" */ - case 0x03: - m = 8; - break; - - } - - switch (k >> 2) { - case 0x02: - k = 70; - break; - - case 0x03: - k = 60; - break; - - default: - printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k); - k = 70; - } - -#ifdef CONFIG_FADS - /* the FADS is missing this bit, all rams treated as non-edo */ - s = 0; -#else - s = (*((uint *) BCSR2) >> 27) & 0x01; -#endif - - if (!_draminit (base, m, s, k)) { - printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : ""); - } else { - _dramdisable (); - m = 0; - } -#endif /* !CONFIG_MPC885ADS */ - m += sdramsz; /* add sdram size to total */ - - return (m << 20); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ========================================================================= */ - -/* - * Check Board Identity: - */ - -#if defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) -static void checkdboard(void) -{ - /* get db type from BCSR 3 */ - uint k = (*((uint *)BCSR3) >> 24) & 0x3f; - - puts (" with db "); - - switch(k) { - case 0x03 : - puts ("MPC823"); - break; - case 0x20 : - puts ("MPC801"); - break; - case 0x21 : - puts ("MPC850"); - break; - case 0x22 : - puts ("MPC821, MPC860 / MPC860SAR / MPC860T"); - break; - case 0x23 : - puts ("MPC860SAR"); - break; - case 0x24 : - case 0x2A : - puts ("MPC860T"); - break; - case 0x3F : - puts ("MPC850SAR"); - break; - default : printf("0x%x", k); - } -} -#endif /* defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) */ - -int checkboard (void) -{ -#if defined(CONFIG_MPC86xADS) - puts ("Board: MPC86xADS\n"); -#elif defined(CONFIG_MPC885ADS) - puts ("Board: MPC885ADS\n"); -#else /* Only old ADS/FADS have got revision ID in BCSR3 */ - uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) - | (((*((uint *) BCSR3) >> 19) & 1) << 2) - | (((*((uint *) BCSR3) >> 16) & 3)); - - puts ("Board: "); -#if defined(CONFIG_FADS) - puts ("FADS"); - checkdboard (); -#else - puts ("ADS"); -#endif - - puts (" rev "); - - switch (r) { -#if defined(CONFIG_ADS) - case 0x00: - puts ("ENG - this board sucks, check the errata, not supported\n"); - return -1; - case 0x01: - puts ("PILOT - warning, read errata \n"); - break; - case 0x02: - puts ("A - warning, read errata \n"); - break; - case 0x03: - puts ("B\n"); - break; -#else /* FADS */ - case 0x00: - puts ("ENG\n"); - break; - case 0x01: - puts ("PILOT\n"); - break; -#endif /* CONFIG_ADS */ - default: - printf ("unknown (0x%x)\n", r); - return -1; - } -#endif /* CONFIG_MPC86xADS */ - - return 0; -} - -/* ========================================================================= */ - -#if defined(CONFIG_CMD_PCMCIA) - -#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init(void) -{ - volatile pcmconf8xx_t *pcmp; - uint v, slota = 0, slotb = 0; - - /* - ** Enable the PCMCIA for a Flash card. - */ - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - -#if 0 - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR; - pcmp->pcmc_por0 = 0xc00ff05d; -#endif - - /* Set all slots to zero by default. */ - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; -#ifdef CONFIG_PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0x40; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0x40; -#endif - - /* enable PCMCIA buffers */ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - - /* Check if any PCMCIA card is plugged in. */ - -#ifdef CONFIG_PCMCIA_SLOT_A - slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ; -#endif - - if (!(slota || slotb)) { - printf("No card present\n"); - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; - return -1; - } - else - printf("Card present ("); - - v = 0; - - /* both the ADS and the FADS have a 5V keyed pcmcia connector (?) - ** - ** Paolo - Yes, but i have to insert some 3.3V card in that slot on - ** my FADS... :-) - */ - -#if defined(CONFIG_MPC86x) - switch ((pcmp->pcmc_pipr >> 30) & 3) -#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850) - switch ((pcmp->pcmc_pipr >> 14) & 3) -#endif - { - case 0x03 : - printf("5V"); - v = 5; - break; - case 0x01 : - printf("5V and 3V"); -#ifdef CONFIG_FADS - v = 3; /* User lower voltage if supported! */ -#else - v = 5; -#endif - break; - case 0x00 : - printf("5V, 3V and x.xV"); -#ifdef CONFIG_FADS - v = 3; /* User lower voltage if supported! */ -#else - v = 5; -#endif - break; - } - - switch (v) { -#ifdef CONFIG_FADS - case 3: - printf("; using 3V"); - /* - ** Enable 3 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCC1; - *((uint *)BCSR1) |= BCSR1_PCCVCC0; - break; -#endif - case 5: - printf("; using 5V"); -#ifdef CONFIG_ADS - /* - ** Enable 5 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCCON; -#endif -#ifdef CONFIG_FADS - /* - ** Enable 5 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCC0; - *((uint *)BCSR1) |= BCSR1_PCCVCC1; -#endif - break; - - default: - *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */ - - printf("; unknown voltage"); - return -1; - } - printf(")\n"); - /* disable pcmcia reset after a while */ - - udelay(20); - -#ifdef CONFIG_PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0; -#endif - - /* If you using a real hd you should give a short - * spin-up time. */ -#ifdef CONFIG_DISK_SPINUP_TIME - udelay(CONFIG_DISK_SPINUP_TIME); -#endif - - return 0; -} - -#endif - -/* ========================================================================= */ - -#ifdef CONFIG_SYS_PC_IDE_RESET - -void ide_set_reset(int on) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* - * Configure PC for IDE Reset Pin - */ - if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); - } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; - } - - /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET; -} - -#endif /* CONFIG_SYS_PC_IDE_RESET */ diff --git a/board/fads/fads.h b/board/fads/fads.h deleted file mode 100644 index 2550529c8d..0000000000 --- a/board/fads/fads.h +++ /dev/null @@ -1,476 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum, - * and Dan Malek - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * This header file contains values common to all FADS family boards. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * Flash Memory Map as used by U-Boot: - * - * Start Address Length - * +-----------------------+ 0xFE00_0000 Start of Flash ----------------- - * | | 0xFE00_0100 Reset Vector - * + + 0xFE0?_???? - * | U-Boot code | - * | | - * +-----------------------+ 0xFE04_0000 (sector border) - * | | - * | | - * | U-Boot environment | - * | | ^ - * | | | U-Boot - * +=======================+ 0xFE08_0000 (sector border) ----------------- - * | Available | | Applications - * | ... | v - * - *****************************************************************************/ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm" - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm fe080000" - -#undef CONFIG_BOOTARGS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if !defined(CONFIG_MPC885ADS) -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#endif - -/* - * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: - * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on - * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have - * got FEC so FEC is the default. - */ -#ifndef CONFIG_ADS -#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */ -#define CONFIG_FEC_ENET /* Use FEC ethernet */ -#else /* Old ADS has not got FEC option */ -#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */ -#undef CONFIG_FEC_ENET /* No FEC ethernet */ -#endif /* !CONFIG_ADS */ - -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#ifdef CONFIG_FEC_ENET -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -#if !defined(FADS_COMMANDS_ALREADY_DEFINED) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* #undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ -#define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ -/* - * 2048 SDRAM rows - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) -#elif defined(CONFIG_FADS) /* Old/new FADS */ -#define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ -#else /* Old ADS */ -#define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CONFIG_SYS_SDRAM_SIZE) -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ -#else -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif /* CONFIG_SYS_SDRAM_SIZE */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ - -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organization - */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#if defined(CONFIG_CMD_JFFS2) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3" -#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)" -*/ - -#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if defined(CONFIG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR SCCR_TBS - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register - *----------------------------------------------------------------------- - * Set to zero to prevent the processor from entering debug mode - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the entire - * address space, we have to set the memory controller differently. - * Normally, you write the option register first, and then enable the - * chip select by writing the base register. For CS0, you must write - * the base register first, followed by the option register. - */ - -/* - * Init Memory Controller: - * - * BR0/OR0 (Flash) - * BR1/OR1 (BCSR) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xFF080000) - -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V) - -/* values according to the manual */ - -#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* - * (F)ADS bitvalues by Helmut Buchsbaum - * - * See User's Manual for a proper - * description of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR1_PCCVCCON BCSR1_PCCVCC0 - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#if defined(CONFIG_MPC823) -#define BCSR4_USB_EN ((uint)0x08000000) -#define BCSR4_USB_SPEED ((uint)0x04000000) -#define BCSR4_VCCO ((uint)0x02000000) -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#elif defined(CONFIG_MPC850) -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#elif defined(CONFIG_MPC860SAR) -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#else /* MPC860T and other chips with FEC */ -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) -#endif - -/* BSCR5 exists on MPC86xADS and MPC885ADS only */ - -#define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000) - -#define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300) - -#define BCSR5_MII2_EN 0x40 -#define BCSR5_MII2_RST 0x20 -#define BCSR5_T1_RST 0x10 -#define BCSR5_ATM155_RST 0x08 -#define BCSR5_ATM25_RST 0x04 -#define BCSR5_MII1_EN 0x02 -#define BCSR5_MII1_RST 0x01 - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 - -#undef CONFIG_ATAPI -#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#endif -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 - -#define CONFIG_DISK_SPINUP_TIME 1000000 -/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */ diff --git a/board/fads/flash.c b/board/fads/flash.c deleted file mode 100644 index ea2f713ca6..0000000000 --- a/board/fads/flash.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define QUAD_ID(id) ((((ulong)(id) & 0xFF) << 24) | \ - (((ulong)(id) & 0xFF) << 16) | \ - (((ulong)(id) & 0xFF) << 8) | \ - (((ulong)(id) & 0xFF) << 0) \ - ) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - vu_long *bcsr = (vu_long *)BCSR_ADDR; - unsigned long pd_size, total_size, bsize, or_am; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - flash_info[i].sector_count = 0; - flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */ - } - - switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) { - case 2: - case 4: - case 6: - pd_size = 0x800000; - or_am = 0xFF800000; - break; - - case 5: - case 7: - pd_size = 0x400000; - or_am = 0xFFC00000; - break; - - case 8: - pd_size = 0x200000; - or_am = 0xFFE00000; - break; - - default: - pd_size = 0; - or_am = 0xFFE00000; - printf("## Unsupported flash detected by BCSR: 0x%08lX\n", bcsr[2]); - } - - total_size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && total_size < pd_size; ++i) { - bsize = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + total_size), - &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, bsize, bsize >> 20); - } - - total_size += bsize; - } - - if (total_size != pd_size) { - printf("## Detected flash size %lu conflicts with PD data %lu\n", - total_size, pd_size); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = or_am | CONFIG_SYS_OR_TIMING_FLASH; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) { -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - if (CONFIG_SYS_MONITOR_BASE >= flash_info[i].start[0]) - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[i]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - if (CONFIG_ENV_ADDR >= flash_info[i].start[0]) - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[i]); -#endif - } - - return total_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM080: - printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - * The following code can not run from flash! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - - switch (addr[0]) { - case QUAD_ID(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - - case QUAD_ID(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - switch (addr[1]) { /* device ID */ - case QUAD_ID(AMD_ID_F040B): - case QUAD_ID(AMD_ID_LV040B): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case QUAD_ID(AMD_ID_F080B): - info->flash_id += FLASH_AM080; - info->sector_count = 16; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif /* 0 */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = (ulong)addr + (i * 0x00040000); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *) (info->start[i]); - info->protect[i] = addr[2] & 1; - } - - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *) info->start[0]; - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return ERR_INVAL; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return ERR_UNKNOWN_FLASH_TYPE; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *) (info->start[l_sect]); - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) - { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *) info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return ERR_NOT_ERASED; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080)) - { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return ERR_TIMOUT; - } - } - return (0); -} diff --git a/board/fads/lamp.c b/board/fads/lamp.c deleted file mode 100644 index 4e58291c06..0000000000 --- a/board/fads/lamp.c +++ /dev/null @@ -1,47 +0,0 @@ -#include - -#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */ - -#include - -void -signal_delay(unsigned int n) -{ - while (n--); -} - -void -signal_on(void) -{ - *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */ -} - -void -signal_off(void) -{ - *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */ -} - -void -slow_blink(unsigned int n) -{ - while (n--) { - signal_on(); - signal_delay(0x00400000); - signal_off(); - signal_delay(0x00400000); - } -} - -void -fast_blink(unsigned int n) -{ - while (n--) { - signal_on(); - signal_delay(0x00100000); - signal_off(); - signal_delay(0x00100000); - } -} - -#endif /* !CONFIG_ADS */ diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c deleted file mode 100644 index 99fe0b4fb9..0000000000 --- a/board/fads/pcmcia.c +++ /dev/null @@ -1,84 +0,0 @@ -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#ifdef CONFIG_ADS -#define PCMCIA_BOARD_MSG "ADS" -#else -#define PCMCIA_BOARD_MSG "FADS" -#endif - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - u_long reg = 0; - - switch(vpp) { - case 0: reg = 0; break; - case 50: reg = 1; break; - case 120: reg = 2; break; - default: return 1; - } - - switch(vcc) { - case 0: reg = 0; break; -#ifdef CONFIG_ADS - case 50: reg = BCSR1_PCCVCCON; break; -#endif -#ifdef CONFIG_FADS - case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break; - case 50: reg = BCSR1_PCCVCC1; break; -#endif - default: return 1; - } - - /* first, turn off all power */ - -#ifdef CONFIG_ADS - *((uint *)BCSR1) |= BCSR1_PCCVCCON; -#endif -#ifdef CONFIG_FADS - *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1); -#endif - *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK; - - /* enable new powersettings */ - -#ifdef CONFIG_ADS - *((uint *)BCSR1) &= ~reg; -#endif -#ifdef CONFIG_FADS - *((uint *)BCSR1) |= reg; -#endif - - *((uint *)BCSR1) |= reg << 20; - - return 0; -} - -int pcmcia_hardware_enable(int slot) -{ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - return 0; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - return 0; -} -#endif - -#endif /* CONFIG_PCMCIA */ diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds deleted file mode 100644 index 3123a888f1..0000000000 --- a/board/fads/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - /*. = DEFINED(env_offset) ? env_offset : .;*/ - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/faraday/a320evb/Kconfig b/board/faraday/a320evb/Kconfig new file mode 100644 index 0000000000..02c42cb0a2 --- /dev/null +++ b/board/faraday/a320evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_A320EVB + +config SYS_BOARD + default "a320evb" + +config SYS_VENDOR + default "faraday" + +config SYS_SOC + default "a320" + +config SYS_CONFIG_NAME + default "a320evb" + +endif diff --git a/board/faraday/a320evb/MAINTAINERS b/board/faraday/a320evb/MAINTAINERS new file mode 100644 index 0000000000..f13b015bb4 --- /dev/null +++ b/board/faraday/a320evb/MAINTAINERS @@ -0,0 +1,6 @@ +A320EVB BOARD +M: Po-Yu Chuang +S: Maintained +F: board/faraday/a320evb/ +F: include/configs/a320evb.h +F: configs/a320evb_defconfig diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile index 7446945f6f..518ce3fcb4 100644 --- a/board/faraday/a320evb/Makefile +++ b/board/faraday/a320evb/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := a320evb.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := a320evb.o +obj-y += lowlevel_init.o diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/flagadm/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c deleted file mode 100644 index 343cb77409..0000000000 --- a/board/flagadm/flagadm.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#define _NOT_USED_ 0xFFFFFFFF - -/*Orginal table, GPL4 disabled*/ -const uint sdram_table[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00, - 0x1ff74c47, - /* Precharge */ - 0x1FF74C05, - _NOT_USED_, - _NOT_USED_, - /* burst read (offset 0x08 in upm ram) */ - 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00, - 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* single write (offset 0x18 in upm ram) */ - 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47, - /* Load moderegister */ - 0x1FF74C34, /*Precharge*/ - 0xEFEA8C34, /*NOP*/ - 0x1FB54C35, /*Load moderegister*/ - _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00, - 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - 0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04, - 0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - 0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* GPL5 driven every cycle */ -/* the display and the DSP */ -const uint dsp_disp_table[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004, - 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05, - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* single write (offset 0x18 in upm ram) */ - 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004, - 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05, - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -int checkboard (void) -{ - puts ("Board: FlagaDM V3.0\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; - - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - - udelay(100); - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = MPTPR_PTP_DIV16; - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X; - - /*Do the initialization of the SDRAM*/ - /*Start with the precharge cycle*/ - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(1) | MCR_MAD(0x5)); - - /*Then we need two refresh cycles*/ - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X; - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(2) | MCR_MAD(0x30)); - - /*Mode register programming*/ - memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/ - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(1) | MCR_MAD(0x1C)); - - /* That should do it, just enable the periodic refresh in burst of 4*/ - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X; - memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS); - - size_b0 = 16*1024*1024; - - /* - * No bank 1 or 3 - * invalidate bank - */ - memctl->memc_br1 = 0; - memctl->memc_br3 = 0; - - upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint)); - - memctl->memc_mbmr = MBMR_GPL_B4DIS; - - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - - return (size_b0); -} diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c deleted file mode 100644 index 46a2c9a266..0000000000 --- a/board/flagadm/flash.c +++ /dev/null @@ -1,687 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -ulong flash_recognize (vu_long *base); -int write_word (flash_info_t *info, ulong dest, ulong data); -void flash_get_geometry (vu_long *base, flash_info_t *info); -void flash_unprotect(flash_info_t *info); -int _flash_real_protect(flash_info_t *info, long idx, int on); - - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int i; - int rec; - - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br0 & ~(BR_BA_MSK)); - - rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE); - - if (rec == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - flash_info[0].size, flash_info[0].size<<20); - } - -#if CONFIG_SYS_FLASH_PROTECTION - /*Unprotect all the flash memory*/ - flash_unprotect(&flash_info[0]); -#endif - - *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff; - - return (flash_info[0].size); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_OFFSET, - CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - return (flash_info[0].size); -} - - -int flash_get_protect_status(flash_info_t * info, long idx) -{ - vu_short * base; - ushort res; - -#ifdef DEBUG - printf("\n Attempting to set protection info with %d sectors\n", info->sector_count); -#endif - - - base = (vu_short*)info->start[idx]; - - *(base) = 0xffff; - - *(base + 0x55) = 0x0098; - res = base[0x2]; - - *(base) = 0xffff; - - if(res != 0) - res = 1; - else - res = 0; - - return res; -} - -void flash_get_geometry (vu_long *base, flash_info_t *info) -{ - int i,j; - ulong ner = 0; - vu_short * sb = (vu_short*)base; - ulong offset = (ulong)base; - - /* Read Device geometry */ - - *sb = 0xffff; - - *sb = 0x0090; - - info->flash_id = ((ulong)base[0x0]); -#ifdef DEBUG - printf("Id is %x\n", (uint)(ulong)info->flash_id); -#endif - - *sb = 0xffff; - - *(sb+0x55) = 0x0098; - - info->size = 1 << (sb[0x27]); /* Read flash size */ - -#ifdef DEBUG - printf("Size is %x\n", (uint)(ulong)info->size); -#endif - - *sb = 0xffff; - - *(sb + 0x55) = 0x0098; - ner = sb[0x2c] ; /*Number of erase regions*/ - -#ifdef DEBUG - printf("Number of erase regions %x\n", (uint)ner); -#endif - - info->sector_count = 0; - - for(i = 0; i < ner; i++) - { - uint s; - uint count; - uint t1,t2,t3,t4; - - *sb = 0xffff; - - *(sb + 0x55) = 0x0098; - - t1 = sb[0x2d + i*4]; - t2 = sb[0x2e + i*4]; - t3 = sb[0x2f + i*4]; - t4 = sb[0x30 + i*4]; - - count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/ - s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/ - -#ifdef DEBUG - printf("count and size %x, %x\n", count, s); - printf("sector count for erase region %d is %d\n", i, count); -#endif - for(j = 0; j < count; j++) - { -#ifdef DEBUG - printf("%x, ", (uint)offset); -#endif - info->start[ info->sector_count + j] = offset; - offset += s; - } - info->sector_count += count; - } - - if ((offset - (ulong)base) != info->size) - printf("WARNING reported size %x does not match to calculted size %x.\n" - , (uint)info->size, (uint)(offset - (ulong)base) ); - - /* Next check if there are any sectors protected.*/ - - for(i = 0; i < info->sector_count; i++) - info->protect[i] = flash_get_protect_status(info, i); - - *sb = 0xffff; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return ; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case INTEL_MANUFACT & FLASH_VENDMASK: - printf ("Intel "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case INTEL_ID_28F320C3B & FLASH_TYPEMASK: - printf ("28F320RC3(4 MB)\n"); - break; - case INTEL_ID_28F320J3A: - printf("28F320J3A (4 MB)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 4) == 0) - printf ("\n "); - printf (" %02d %08lX%s", - i, info->start[i], - info->protect[i]!=0 ? " (RO)" : " " - ); - } - printf ("\n"); - return ; -} - -ulong flash_recognize (vu_long *base) -{ - ulong id; - ulong res = FLASH_UNKNOWN; - vu_short * sb = (vu_short*)base; - - *sb = 0xffff; - - *sb = 0x0090; - id = base[0]; - - switch (id & 0x00FF0000) - { - case (MT_MANUFACT & 0x00FF0000): /* MT or => Intel */ - case (INTEL_ALT_MANU & 0x00FF0000): - res = FLASH_MAN_INTEL; - break; - default: - res = FLASH_UNKNOWN; - } - - *sb = 0xffff; - - return res; -} - -/*-----------------------------------------------------------------------*/ -#define INTEL_FLASH_STATUS_BLS 0x02 -#define INTEL_FLASH_STATUS_PSS 0x04 -#define INTEL_FLASH_STATUS_VPPS 0x08 -#define INTEL_FLASH_STATUS_PS 0x10 -#define INTEL_FLASH_STATUS_ES 0x20 -#define INTEL_FLASH_STATUS_ESS 0x40 -#define INTEL_FLASH_STATUS_WSMS 0x80 - -int flash_decode_status_bits(char status) -{ - int err = 0; - - if(!(status & INTEL_FLASH_STATUS_WSMS)) { - printf("Busy\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_ESS) { - printf("Erase suspended\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_ES) { - printf("Error in block erase\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_PS) { - printf("Error in programming\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_VPPS) { - printf("Vpp low, operation aborted\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_PSS) { - printf("Program is suspended\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_BLS) { - printf("Attempting to program/erase a locked sector\n"); - err = -1; - } - - if((status & INTEL_FLASH_STATUS_PS) && - (status & INTEL_FLASH_STATUS_ES) && - (status & INTEL_FLASH_STATUS_ESS)) { - printf("A command sequence error\n"); - return -1; - } - - return err; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr; - int flag, prot, sect; - ulong start, now; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - char tmp; - - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Single Block Erase Command */ - *addr = 0x0020; - /* Confirm */ - *addr = 0x00D0; - /* Resume Command, as per errata update */ - *addr = 0x00D0; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - *addr = 0x70; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read the status */ - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - start) > 1000) { /* every second */ - putc ('.'); - } - udelay(100000); /* 100 ms */ - *addr = 0x0070; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read status */ - start = get_timer(0); - } - if( tmp & INTEL_FLASH_STATUS_ES ) - flash_decode_status_bits(tmp); - - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; /* Reset to read mode */ - } - } - - - printf (" done\n"); - return rcode; -} - -void flash_unprotect (flash_info_t *info) -{ - /*We can only unprotect the whole flash at once*/ - /*Therefore we must prevent the _flash_real_protect()*/ - /*from re-protecting sectors, that ware protected before */ - /*we called flash_real_protect();*/ - - int i; - - for(i = 0; i < info->sector_count; i++) - info->protect[i] = 0; - -#ifdef CONFIG_SYS_FLASH_PROTECTION - _flash_real_protect(info, 0, 0); -#endif -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_word (flash_info_t *info, ulong dest, ulong da) -{ - vu_short *addr = (vu_short *)dest; - ulong start; - char csr; - int flag; - int i; - union { - u32 data32; - u16 data16[2]; - } data; - - data.data32 = da; - - /* Check if Flash is (sufficiently) erased */ - if (((*addr & data.data16[0]) != data.data16[0]) || - ((*(addr+1) & data.data16[1]) != data.data16[1])) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for(i = 0; i < 2; i++) - { - /* Write Command */ - *addr = 0x0010; - - /* Write Data */ - *addr = data.data16[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - *addr = 0x0070; /*Read statusregister command */ - while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - *addr = 0x0070; /*Read statusregister command */ - } - if (csr & INTEL_FLASH_STATUS_PSS) { - printf ("CSR indicates write error (%0x) at %08lx\n", - csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x0050; - /* Reset to read array mode */ - *addr = 0xffff; - addr++; - } - - return (flag); -} - -int flash_real_protect(flash_info_t *info, long offset, int prot) -{ - int i, idx; - - for(idx = 0; idx < info->sector_count; idx++) - if(info->start[idx] == offset) - break; - - if(idx==info->sector_count) - return -1; - - if(prot == 0) { - /* Unprotect one sector, which means unprotect all flash - * and reprotect the other protected sectors. - */ - _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/ - info->protect[idx] = 0; - - for(i = 0; i < info->sector_count; i++) - if(info->protect[i]) - _flash_real_protect(info, i, 1); - } - else { - /* We can protect individual sectors */ - _flash_real_protect(info, idx, 1); - } - - for( i = 0; i < info->sector_count; i++) - info->protect[i] = flash_get_protect_status(info, i); - - return 0; -} - -int _flash_real_protect(flash_info_t *info, long idx, int prot) -{ - vu_short *addr; - int flag; - ushort cmd; - ushort tmp; - ulong now, start; - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { - printf ("Can't change protection for unknown flash type %08lx - aborted\n", - info->flash_id); - return -1; - } - - if(prot == 0) { - /*Unlock the sector*/ - cmd = 0x00D0; - } - else { - /*Lock the sector*/ - cmd = 0x0001; - } - - addr = (vu_short *)(info->start[idx]); - - /* If chip is busy, wait for it */ - start = get_timer(0); - *addr = 0x0070; /*Read status register command*/ - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ - while(!(tmp & INTEL_FLASH_STATUS_WSMS)) { - /*Write State Machine Busy*/ - /*Wait untill done or timeout.*/ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; /* Reset the chip */ - printf ("TTimeout\n"); - return 1; - } - *addr = 0x0070; - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ - start = get_timer(0); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Unlock block*/ - *addr = 0x0060; - - *addr = cmd; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - *addr = 0x0070; /*Read status register command*/ - tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */ - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - /* Write State Machine Busy */ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - start) > 1000) { /* every second */ - putc ('.'); - } - udelay(100000); /* 100 ms */ - *addr = 0x70; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read status */ - start = get_timer(0); - } - if( tmp & INTEL_FLASH_STATUS_PS ) - flash_decode_status_bits(tmp); - - *addr =0x0050; /*Clear status register*/ - - /* reset to read mode */ - *addr = 0xffff; - - return 0; -} diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds deleted file mode 100644 index 7ae91ffb2e..0000000000 --- a/board/flagadm/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug deleted file mode 100644 index b0091db0c6..0000000000 --- a/board/flagadm/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig new file mode 100644 index 0000000000..c7aab7521b --- /dev/null +++ b/board/freescale/b4860qds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_B4860QDS + +config SYS_BOARD + default "b4860qds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "B4860QDS" + +endif diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS new file mode 100644 index 0000000000..ac02bb7e48 --- /dev/null +++ b/board/freescale/b4860qds/MAINTAINERS @@ -0,0 +1,17 @@ +B4860QDS BOARD +#M: - +S: Maintained +F: board/freescale/b4860qds/ +F: include/configs/B4860QDS.h +F: configs/B4420QDS_defconfig +F: configs/B4420QDS_NAND_defconfig +F: configs/B4420QDS_SPIFLASH_defconfig +F: configs/B4860QDS_defconfig +F: configs/B4860QDS_NAND_defconfig +F: configs/B4860QDS_SPIFLASH_defconfig +F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig + +B4860QDS_SECURE_BOOT BOARD +M: Aneesh Bansal +S: Maintained +F: configs/B4860QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile index a864c0b72d..0acd2a9aa4 100644 --- a/board/freescale/b4860qds/Makefile +++ b/board/freescale/b4860qds/Makefile @@ -4,35 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += b4860qds.o +obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o +obj-$(CONFIG_PCI) += pci.o +endif + +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 86e44eae0b..6a8fca61a0 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -18,9 +19,12 @@ #include #include #include +#include #include "../common/qixis.h" #include "../common/vsc3316_3308.h" +#include "../common/idt8t49n222a_serdes_clk.h" +#include "../common/zm7300.h" #include "b4860qds.h" #include "b4860qds_qixis.h" #include "b4860qds_crossbar_con.h" @@ -35,8 +39,6 @@ int checkboard(void) char buf[64]; u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - unsigned int i; static const char *const freq[] = {"100", "125", "156.25", "161.13", "122.88", "122.88", "122.88"}; int clock; @@ -61,19 +63,6 @@ int checkboard(void) /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf)); - /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* * Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could @@ -107,12 +96,246 @@ int select_i2c_ch_pca(u8 ch) return 0; } +/* + * read_voltage from sensor on I2C bus + * We use average of 4 readings, waiting for 532us befor another reading + */ +#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ +#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ + +static inline int read_voltage(void) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + + for (i = 0; i < NUM_READINGS; i++) { + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%04x\n", vol_mon); + /* LSB = 4mv */ + voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; + udelay(WAIT_FOR_ADC); + } + /* calculate the average */ + voltage_read /= NUM_READINGS; + + return voltage_read; +} + +static int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 fusesr; + u8 vid; + int vdd_target, vdd_last; + int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */ + int ret; + unsigned int orig_i2c_speed; + unsigned long vdd_string_override; + char *vdd_string; + static const uint16_t vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + struct vdd_drive { + u8 vid; + unsigned voltage; + }; + + ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + printf("VID: I2c failed to switch channel\n"); + ret = -1; + goto exit; + } + + /* get the voltage ID from fuse status register */ + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; + if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + } + vdd_target = vdd[vid]; + debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n", + vid, vdd_target/10); + + /* check override variable for overriding VDD */ + vdd_string = getenv("b4qds_vdd_mv"); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + if (vdd_override >= 819 && vdd_override <= 1212) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + + if (vdd_target == 0) { + printf("VID: VID not used\n"); + ret = 0; + goto exit; + } + + /* + * Read voltage monitor to check real voltage. + * Voltage monitor LSB is 4mv. + */ + vdd_last = read_voltage(); + if (vdd_last < 0) { + printf("VID: abort VID adjustment\n"); + ret = -1; + goto exit; + } + + debug("VID: Core voltage is at %d mV\n", vdd_last); + ret = select_i2c_ch_pca(I2C_MUX_CH_DPM); + if (ret) { + printf("VID: I2c failed to switch channel to DPM\n"); + ret = -1; + goto exit; + } + + /* Round up to the value of step of Voltage regulator */ + voltage = roundup(vdd_target, ZM_STEP); + debug("VID: rounded up voltage = %d\n", voltage); + + /* lower the speed to 100kHz to access ZM7300 device */ + debug("VID: Setting bus speed to 100KHz if not already set\n"); + orig_i2c_speed = i2c_get_bus_speed(); + if (orig_i2c_speed != 100000) + i2c_set_bus_speed(100000); + + /* Read the existing level on board, if equal to requsted one, + no need to re-set */ + existing_voltage = zm_read_voltage(); + + /* allowing the voltage difference of one step 0.0125V acceptable */ + if ((existing_voltage >= voltage) && + (existing_voltage < (voltage + ZM_STEP))) { + debug("VID: voltage already set as requested,returning\n"); + ret = existing_voltage; + goto out; + } + debug("VID: Changing voltage for board from %dmV to %dmV\n", + existing_voltage/10, voltage/10); + + if (zm_disable_wp() < 0) { + ret = -1; + goto out; + } + /* Change Voltage: the change is done through all the steps in the + way, to avoid reset to the board due to power good signal fail + in big voltage change gap jump. + */ + if (existing_voltage > voltage) { + temp_voltage = existing_voltage - ZM_STEP; + while (temp_voltage >= voltage) { + ret = zm_write_voltage(temp_voltage); + if (ret == temp_voltage) { + temp_voltage -= ZM_STEP; + } else { + /* ZM7300 device failed to set + * the voltage */ + printf + ("VID:Stepping down vol failed:%dmV\n", + temp_voltage/10); + ret = -1; + goto out; + } + } + } else { + temp_voltage = existing_voltage + ZM_STEP; + while (temp_voltage < (voltage + ZM_STEP)) { + ret = zm_write_voltage(temp_voltage); + if (ret == temp_voltage) { + temp_voltage += ZM_STEP; + } else { + /* ZM7300 device failed to set + * the voltage */ + printf + ("VID:Stepping up vol failed:%dmV\n", + temp_voltage/10); + ret = -1; + goto out; + } + } + } + + if (zm_enable_wp() < 0) + ret = -1; + + /* restore the speed to 400kHz */ +out: debug("VID: Restore the I2C bus speed to %dKHz\n", + orig_i2c_speed/1000); + i2c_set_bus_speed(orig_i2c_speed); + if (ret < 0) + goto exit; + + ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + printf("VID: I2c failed to switch channel\n"); + ret = -1; + goto exit; + } + vdd_last = read_voltage(); + select_i2c_ch_pca(I2C_CH_DEFAULT); + + if (vdd_last > 0) + printf("VID: Core voltage %d mV\n", vdd_last); + else + ret = -1; + +exit: + if (re_enable) + enable_interrupts(); + return ret; +} + int configure_vsc3316_3308(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); unsigned int num_vsc16_con, num_vsc08_con; u32 serdes1_prtcl, serdes2_prtcl; int ret; + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; serdes1_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -133,6 +356,7 @@ int configure_vsc3316_3308(void) debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); switch (serdes1_prtcl) { + case 0x29: case 0x2a: case 0x2C: case 0x2D: @@ -164,7 +388,58 @@ int configure_vsc3316_3308(void) } break; + case 0x01: + case 0x02: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x2F: + case 0x30: + case 0x32: + case 0x33: + case 0x34: + case 0x39: + case 0x3A: + case 0x3C: + case 0x3D: + case 0x5C: + case 0x5D: + /* + * Configuration: + * SERDES: 1 + * Lanes: A,B: AURORA + * Lanes: C,d: SGMII + * Lanes: E,F,G,H: CPRI + */ + debug("Configuring crossbar for Aurora, SGMII 3 and 4," + " and CPRI. srds_prctl:%x\n", serdes1_prtcl); + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sfp_sgmii_aurora, + num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sfp_sgmii_aurora, + num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; + #ifdef CONFIG_PPC_B4420 + case 0x17: case 0x18: /* * Configuration: @@ -218,18 +493,21 @@ int configure_vsc3316_3308(void) return -1; } + num_vsc08_con = NUM_CON_VSC3308; + /* Configure VSC3308 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3308); switch (serdes2_prtcl) { +#ifdef CONFIG_PPC_B4420 + case 0x9d: +#endif case 0x9E: case 0x9A: case 0x98: - case 0xb2: + case 0x48: case 0x49: case 0x4E: - case 0x8D: + case 0x79: case 0x7A: - num_vsc08_con = NUM_CON_VSC3308; - /* Configure VSC3308 crossbar switch */ - ret = select_i2c_ch_pca(I2C_CH_VSC3308); if (!ret) { ret = vsc3308_config(VSC3308_TX_ADDRESS, vsc08_tx_amc, num_vsc08_con); @@ -243,6 +521,71 @@ int configure_vsc3316_3308(void) return ret; } break; + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0xb1: + case 0xb2: + if (!ret) { + /* + * Extract hwconfig from environment since environment + * is not setup properly yet + */ + getenv_f("hwconfig", buffer, sizeof(buffer)); + buf = buffer; + + if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", + "sfp_amc", "sfp", buf)) { +#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR + /* change default VSC3308 for XFI erratum */ + ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS, + vsc08_tx_sfp, num_vsc08_con); + if (ret) + return ret; + + ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS, + vsc08_rx_sfp, num_vsc08_con); + if (ret) + return ret; +#else + ret = vsc3308_config(VSC3308_TX_ADDRESS, + vsc08_tx_sfp, num_vsc08_con); + if (ret) + return ret; + + ret = vsc3308_config(VSC3308_RX_ADDRESS, + vsc08_rx_sfp, num_vsc08_con); + if (ret) + return ret; +#endif + } else { + ret = vsc3308_config(VSC3308_TX_ADDRESS, + vsc08_tx_amc, num_vsc08_con); + if (ret) + return ret; + + ret = vsc3308_config(VSC3308_RX_ADDRESS, + vsc08_rx_amc, num_vsc08_con); + if (ret) + return ret; + } + + } else { + return ret; + } + break; default: printf("WARNING:VSC crossbars programming not supported for: %x" " SerDes2 Protocol.\n", serdes2_prtcl); @@ -252,10 +595,411 @@ int configure_vsc3316_3308(void) return 0; } +static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num) +{ + u32 rst_err; + + /* Steps For SerDes PLLs reset and reconfiguration + * or PLL power-up procedure + */ + debug("CALIBRATE PLL:%d\n", pll_num); + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds_regs->bank[pll_num].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + + udelay(20); + + /* Check whether PLL has been locked or not */ + rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) & + SRDS_RSTCTL_RSTERR; + rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT; + debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err); + if (rst_err) + return rst_err; + + return rst_err; +} + +static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num) +{ + int ret = 0; + u32 fcap, dcbias, bcap, pllcr1, pllcr0; + + if (calibrate_pll(srds_regs, pll_num)) { + /* STEP 1 */ + /* Read fcap, dcbias and bcap value */ + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_FCAP; + fcap >>= SRDS_PLLSR2_FCAP_SHIFT; + bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_BCAP_EN; + bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; + setbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_DCBIAS; + dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; + debug("values of bcap:%x, fcap:%x and dcbias:%x\n", + bcap, fcap, dcbias); + if (fcap == 0 && bcap == 1) { + /* Step 3 */ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + if (calibrate_pll(srds_regs, pll_num)) { + /*save the fcap, dcbias and bcap values*/ + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) + & SRDS_PLLSR2_FCAP; + fcap >>= SRDS_PLLSR2_FCAP_SHIFT; + bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) + & SRDS_PLLSR2_BCAP_EN; + bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; + setbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + dcbias = in_be32 + (&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_DCBIAS; + dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; + + /* Step 4*/ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BYP_CAL); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + /* change the fcap and dcbias to the saved + * values from Step 3 */ + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_PLL_FCAP); + pllcr1 = (in_be32 + (&srds_regs->bank[pll_num].pllcr1)| + (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr1, + pllcr1); + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OVRD); + pllcr0 = (in_be32 + (&srds_regs->bank[pll_num].pllcr0)| + (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr0, + pllcr0); + ret = calibrate_pll(srds_regs, pll_num); + if (ret) + return ret; + } else { + goto out; + } + } else { /* Step 5 */ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + udelay(10); + /* Change the fcap, dcbias, and bcap to the + * values from Step 1 */ + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BYP_CAL); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_PLL_FCAP); + pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)| + (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr1, + pllcr1); + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OVRD); + pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)| + (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr0, + pllcr0); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + ret = calibrate_pll(srds_regs, pll_num); + if (ret) + return ret; + } + } +out: + return 0; +} + +static int check_serdes_pll_locks(void) +{ + serdes_corenet_t *srds1_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds2_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + int i, ret1, ret2; + + debug("\nSerDes1 Lock check\n"); + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + ret1 = check_pll_locks(srds1_regs, i); + if (ret1) { + printf("SerDes1, PLL:%d didnt lock\n", i); + return ret1; + } + } + debug("\nSerDes2 Lock check\n"); + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + ret2 = check_pll_locks(srds2_regs, i); + if (ret2) { + printf("SerDes2, PLL:%d didnt lock\n", i); + return ret2; + } + } + + return 0; +} + +int config_serdes1_refclks(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 serdes1_prtcl, lane; + unsigned int flag_sgmii_aurora_prtcl = 0; + int i; + int ret = 0; + + serdes1_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + if (!serdes1_prtcl) { + printf("SERDES1 is not enabled\n"); + return -1; + } + serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); + + /* To prevent generation of reset request from SerDes + * while changing the refclks, By setting SRDS_RST_MSK bit, + * SerDes reset event cannot cause a reset request + */ + setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + + /* Reconfigure IDT idt8t49n222a device for CPRI to work + * For this SerDes1's Refclk1 and refclk2 need to be set + * to 122.88MHz + */ + switch (serdes1_prtcl) { + case 0x29: + case 0x2A: + case 0x2C: + case 0x2D: + case 0x2E: + case 0x01: + case 0x02: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x2F: + case 0x30: + case 0x32: + case 0x33: + case 0x34: + case 0x39: + case 0x3A: + case 0x3C: + case 0x3D: + case 0x5C: + case 0x5D: + debug("Configuring idt8t49n222a for CPRI SerDes clks:" + " for srds_prctl:%x\n", serdes1_prtcl); + ret = select_i2c_ch_pca(I2C_CH_IDT); + if (!ret) { + ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1, + SERDES_REFCLK_122_88, + SERDES_REFCLK_122_88, 0); + if (ret) { + printf("IDT8T49N222A configuration failed.\n"); + goto out; + } else + debug("IDT8T49N222A configured.\n"); + } else { + goto out; + } + select_i2c_ch_pca(I2C_CH_DEFAULT); + + /* Change SerDes1's Refclk1 to 125MHz for on board + * SGMIIs or Aurora to work + */ + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl + (0, serdes1_prtcl, lane); + switch (lane_prtcl) { + case SGMII_FM1_DTSEC1: + case SGMII_FM1_DTSEC2: + case SGMII_FM1_DTSEC3: + case SGMII_FM1_DTSEC4: + case SGMII_FM1_DTSEC5: + case SGMII_FM1_DTSEC6: + case AURORA: + flag_sgmii_aurora_prtcl++; + break; + default: + break; + } + } + + if (flag_sgmii_aurora_prtcl) + QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); + + /* Steps For SerDes PLLs reset and reconfiguration after + * changing SerDes's refclks + */ + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + debug("For PLL%d reset and reconfiguration after" + " changing refclks\n", i+1); + clrbits_be32(&srds_regs->bank[i].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds_regs->bank[i].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + } + break; + default: + printf("WARNING:IDT8T49N222A configuration not" + " supported for:%x SerDes1 Protocol.\n", + serdes1_prtcl); + } + +out: + /* Clearing SRDS_RST_MSK bit as now + * SerDes reset event can cause a reset request + */ + clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + return ret; +} + +int config_serdes2_refclks(void) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *srds2_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + u32 serdes2_prtcl; + int ret = 0; + int i; + + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + if (!serdes2_prtcl) { + debug("SERDES2 is not enabled\n"); + return -ENODEV; + } + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); + + /* To prevent generation of reset request from SerDes + * while changing the refclks, By setting SRDS_RST_MSK bit, + * SerDes reset event cannot cause a reset request + */ + setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + + /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work + * For this SerDes2's Refclk1 need to be set to 100MHz + */ + switch (serdes2_prtcl) { +#ifdef CONFIG_PPC_B4420 + case 0x9d: +#endif + case 0x9E: + case 0x9A: + /* fallthrough */ + case 0xb1: + case 0xb2: + debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n", + serdes2_prtcl); + ret = select_i2c_ch_pca(I2C_CH_IDT); + if (!ret) { + ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2, + SERDES_REFCLK_100, + SERDES_REFCLK_156_25, 0); + if (ret) { + printf("IDT8T49N222A configuration failed.\n"); + goto out; + } else + debug("IDT8T49N222A configured.\n"); + } else { + goto out; + } + select_i2c_ch_pca(I2C_CH_DEFAULT); + + /* Steps For SerDes PLLs reset and reconfiguration after + * changing SerDes's refclks + */ + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + clrbits_be32(&srds2_regs->bank[i].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds2_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds2_regs->bank[i].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds2_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + + udelay(10); + } + break; + default: + printf("IDT configuration not supported for:%x S2 Protocol.\n", + serdes2_prtcl); + } + +out: + /* Clearing SRDS_RST_MSK bit as now + * SerDes reset event can cause a reset request + */ + clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + return ret; +} + int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); + int ret; + u32 svr = SVR_SOC_VER(get_svr()); + + /* Create law for MAPLE only for personalities having MAPLE */ + if ((svr == SVR_B4860) || (svr == SVR_B4440) || + (svr == SVR_B4420) || (svr == SVR_B4220)) { + set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, + LAW_TRGT_IF_MAPLE); + } /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -266,8 +1010,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -277,6 +1027,52 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0) < 0) + printf("Warning: Adjusting core voltage failed\n"); + + /* SerDes1 refclks need to be set again, as default clks + * are not suitable for CPRI and onboard SGMIIs to work + * simultaneously. + * This function will set SerDes1's Refclk1 and refclk2 + * as per SerDes1 protocols + */ + if (config_serdes1_refclks()) + printf("SerDes1 Refclks couldn't set properly.\n"); + else + printf("SerDes1 Refclks have been set.\n"); + + /* SerDes2 refclks need to be set again, as default clks + * are not suitable for PCIe SATA to work + * This function will set SerDes2's Refclk1 and refclk2 + * for SerDes2 protocols having PCIe in them + * for PCIe SATA to work + */ + ret = config_serdes2_refclks(); + if (!ret) + printf("SerDes2 Refclks have been set.\n"); + else if (ret == -ENODEV) + printf("SerDes disable, Refclks couldn't change.\n"); + else + printf("SerDes2 Refclk reconfiguring failed.\n"); + +#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A006475) + /* Rechecking the SerDes locks after all SerDes configurations + * are done, As SerDes PLLs may not lock reliably at 5 G VCO + * and at cold temperatures. + * Following sequence ensure the proper locking of SerDes PLLs. + */ + if (SVR_MAJ(get_svr()) == 1) { + if (check_serdes_pll_locks()) + printf("SerDes plls still not locked properly.\n"); + else + printf("SerDes plls have been locked well.\n"); + } +#endif /* Configure VSC3316 and VSC3308 crossbar switches */ if (configure_vsc3316_3308()) @@ -360,22 +1156,6 @@ static int serdes_refclock(u8 sw, u8 sdclk) return ret; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - case SRDS_PLLCR0_RFCK_SEL_161_13: - return "161.13"; - default: - return "122.88"; - } -} - #define NUM_SRDS_BANKS 2 int misc_init_r(void) @@ -415,7 +1195,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -441,6 +1221,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } /* diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h index 6e64745b0f..fcccb8f9b3 100644 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -13,10 +13,10 @@ static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, {5, 11}, {4, 5}, {2, 6}, {12, 9} }; -static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, +static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, +static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {2, 14}, {12, 15}, {-1, -1}, {-1, -1} }; @@ -24,8 +24,12 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {5, 14}, {4, 15}, {-1, -1}, {-1, -1} }; +static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1}, + {7, 8}, {9, 0}, {5, 14}, + {4, 15}, {2, 12}, {12, 13} }; + #ifdef CONFIG_PPC_B4420 -static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, +static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif @@ -35,10 +39,10 @@ static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, {11, 11}, {5, 10}, {6, 3}, {9, 12} }; -static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, +static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, +static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {14, 3}, {15, 12}, {-1, -1}, {-1, -1} }; @@ -46,8 +50,12 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {14, 11}, {15, 10}, {-1, -1}, {-1, -1} }; +static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1}, + {7, 8}, {1, 9}, {14, 11}, + {15, 10}, {13, 3}, {12, 12} }; + #ifdef CONFIG_PPC_B4420 -static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, +static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h index 2fabbc7b32..272afc1ae0 100644 --- a/board/freescale/b4860qds/b4860qds_qixis.h +++ b/board/freescale/b4860qds/b4860qds_qixis.h @@ -21,4 +21,9 @@ #define QIXIS_SRDS1CLK_122 0x5a #define QIXIS_SRDS1CLK_125 0x5e + +/* SGMII */ +#define PHY_BASE_ADDR 0x18 +#define PORT_NUM 0x04 +#define REGNUM 0x00 #endif diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg new file mode 100644 index 0000000000..05377bac5b --- /dev/null +++ b/board/freescale/b4860qds/b4_pbi.cfg @@ -0,0 +1,30 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg new file mode 100644 index 0000000000..597d3914ca --- /dev/null +++ b/board/freescale/b4860qds/b4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x2A_0x98 +140e0018 0f001218 00000000 00000000 +54980000 9000a000 e8104000 a9000000 +01000000 00000000 00000000 0001b1f8 +00000000 14000020 00000000 00000011 diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index b82b3d409e..2c17156586 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -9,11 +9,11 @@ #include #include #include +#include #include -#include -#include +#include +#include #include -#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,20 +31,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 2, /* ECC */ .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1071, - .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ - .tAA_ps = 13910, - .tWR_ps = 15000, - .tRCD_ps = 13910, - .tRRD_ps = 6000, - .tRP_ps = 13910, - .tRAS_ps = 34000, - .tRC_ps = 48910, - .tRFC_ps = 260000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1071, + .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ + .taa_ps = 13910, + .twr_ps = 15000, + .trcd_ps = 13910, + .trrd_ps = 6000, + .trp_ps = 13910, + .tras_ps = 34000, + .trc_ps = 48910, + .trfc_ps = 260000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 35000, + .tfaw_ps = 35000, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, @@ -71,7 +71,7 @@ struct board_specific_parameters { u32 wrlvl_ctl_3; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -129,7 +129,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -146,7 +146,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -179,6 +179,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); @@ -186,7 +187,9 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 19ca66e3d0..501d4b3aff 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -66,6 +66,7 @@ static void initialize_lane_to_slot(void) serdes2_prtcl); switch (serdes2_prtcl) { + case 0x17: case 0x18: /* * Configuration: @@ -111,7 +112,10 @@ static void initialize_lane_to_slot(void) * Lanes: A,B,C,D: PCI * Lanes: E,F,G,H: XAUI2 */ + case 0xb1: case 0xb2: + case 0x8c: + case 0x8d: /* * Configuration: * SERDES: 2 @@ -150,6 +154,8 @@ int board_eth_init(bd_t *bis) struct memac_mdio_info tg_memac_mdio_info; unsigned int i; unsigned int serdes1_prtcl, serdes2_prtcl; + int qsgmii; + struct mii_dev *bus; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); serdes1_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -192,34 +198,34 @@ int board_eth_init(bd_t *bis) * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and * 6 to on board SGMII phys */ - fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); switch (serdes1_prtcl) { + case 0x29: case 0x2a: /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ - debug("Setting phy addresses for FM1_DTSEC5: %x and" - "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); - /* Fixing Serdes clock by programming FPGA register */ - QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); + debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n", + CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, + CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); fm_info_set_phy_address(FM1_DTSEC5, - CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, - CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #ifdef CONFIG_PPC_B4420 + case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ - debug("Setting phy addresses for FM1_DTSEC3: %x and" - "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n", + CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, + CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); /* Fixing Serdes clock by programming FPGA register */ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #endif default: @@ -228,9 +234,10 @@ int board_eth_init(bd_t *bis) break; } switch (serdes2_prtcl) { + case 0x17: case 0x18: - debug("Setting phy addresses on SGMII Riser card for" - "FM1_DTSEC ports: \n"); + debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, @@ -240,9 +247,10 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); break; + case 0x48: case 0x49: - debug("Setting phy addresses on SGMII Riser card for" - "FM1_DTSEC ports: \n"); + debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, @@ -250,29 +258,37 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); break; - case 0x8d: + case 0xb1: case 0xb2: - debug("Setting phy addresses on SGMII Riser card for" - "FM1_DTSEC ports: \n"); + case 0x8c: + case 0x8d: + debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n", + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); + /* + * XFI does not need a PHY to work, but to make U-boot + * happy, assign a fake PHY address for a XFI port. + */ + fm_info_set_phy_address(FM1_10GEC1, 0); + fm_info_set_phy_address(FM1_10GEC2, 1); break; case 0x98: /* XAUI in Slot1 and Slot2 */ - debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n", + debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n", CONFIG_SYS_FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", + debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); break; case 0x9E: /* XAUI in Slot2 */ - debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", + debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); @@ -283,6 +299,22 @@ int board_eth_init(bd_t *bis) break; } + /*set PHY address for QSGMII Riser Card on slot2*/ + bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM); + + if (qsgmii) { + switch (serdes2_prtcl) { + case 0xb2: + case 0x8d: + fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); + break; + default: + break; + } + } + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; @@ -308,17 +340,20 @@ int board_eth_init(bd_t *bis) switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: fm_info_set_mdio(i, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); + miiphy_get_dev_by_name + (DEFAULT_FM_TGEC_MDIO_NAME)); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); break; default: - printf("Fman1: 10GSEC%u set to unknown interface %i\n", + printf("Fman1: TGEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } - cpu_eth_init(bis); #endif @@ -330,21 +365,82 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, { int phy; char alias[32]; + struct fixed_link f_link; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { phy = fm_info_get_phy_address(port); sprintf(alias, "phy_sgmii_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, alias); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + /* check if it's XFI interface for 10g */ + switch (prtcl2) { + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0xb1: + case 0xb2: + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + break; + case 0x98: /* XAUI interface */ + sprintf(alias, "phy_xaui_slot1"); + fdt_status_okay_by_alias(fdt, alias); + + sprintf(alias, "phy_xaui_slot2"); + fdt_status_okay_by_alias(fdt, alias); + break; + case 0x9e: /* XAUI interface */ + case 0x9a: + case 0x93: + case 0x91: + sprintf(alias, "phy_xaui_slot1"); + fdt_status_okay_by_alias(fdt, alias); + break; + case 0x97: /* XAUI interface */ + case 0xc3: + sprintf(alias, "phy_xaui_slot2"); + fdt_status_okay_by_alias(fdt, alias); + break; + default: + break; + } } } +/* + * Set status to disabled for unused ethernet node + */ void fdt_fixup_board_enet(void *fdt) { int i; char alias[32]; - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_NONE: sprintf(alias, "ethernet%u", i); diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c index 5b327ccee9..047c3cbb3f 100644 --- a/board/freescale/b4860qds/law.c +++ b/board/freescale/b4860qds/law.c @@ -17,9 +17,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_MAPLE_MEM_PHYS - SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE), -#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c new file mode 100644 index 0000000000..3aa5a780f4 --- /dev/null +++ b/board/freescale/b4860qds/spl.c @@ -0,0 +1,114 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "b4860qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((sysclk_conf & 0x0C) >> 2) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch (ddrclk_conf & 0x03) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); + env_relocate(); +#else + /* relocate environment function pointers etc. */ + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#endif + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_boot(); +#endif +} diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index f71aca4092..7b55b860d0 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -62,13 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for SRIO2. */ +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_SYS_SRIO1_MEM_PHYS /* *I*G* - SRIO1 */ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, @@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 17, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/bsc9131rdb/Kconfig b/board/freescale/bsc9131rdb/Kconfig new file mode 100644 index 0000000000..dd9f765d7d --- /dev/null +++ b/board/freescale/bsc9131rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BSC9131RDB + +config SYS_BOARD + default "bsc9131rdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "BSC9131RDB" + +endif diff --git a/board/freescale/bsc9131rdb/MAINTAINERS b/board/freescale/bsc9131rdb/MAINTAINERS new file mode 100644 index 0000000000..7cd8134aa7 --- /dev/null +++ b/board/freescale/bsc9131rdb/MAINTAINERS @@ -0,0 +1,9 @@ +BSC9131RDB BOARD +M: Poonam Aggrwal +S: Maintained +F: board/freescale/bsc9131rdb/ +F: include/configs/BSC9131RDB.h +F: configs/BSC9131RDB_NAND_defconfig +F: configs/BSC9131RDB_NAND_SYSCLK100_defconfig +F: configs/BSC9131RDB_SPIFLASH_defconfig +F: configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile index e1a7d8b092..b26d3a1e63 100644 --- a/board/freescale/bsc9131rdb/Makefile +++ b/board/freescale/bsc9131rdb/Makefile @@ -4,10 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -18,36 +14,14 @@ endif ifdef MINIMAL -COBJS-y += spl_minimal.o tlb.o law.o +obj-y += spl_minimal.o tlb.o law.o else -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o -#COBJS-y += bsc9131rdb_mux.o +obj-y += bsc9131rdb.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +#obj-y += bsc9131rdb_mux.o endif - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c index 7fe4ae74ea..75e114217b 100644 --- a/board/freescale/bsc9131rdb/bsc9131rdb.c +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -15,6 +15,9 @@ #include #include #include +#include +#include +#include #include @@ -50,7 +53,12 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -61,7 +69,12 @@ void ft_board_setup(void *blob, bd_t *bd) size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif fdt_fixup_dr_usb(blob, bd); + + return 0; } #endif diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c index a4161ad649..339c576256 100644 --- a/board/freescale/bsc9131rdb/ddr.c +++ b/board/freescale/bsc9131rdb/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include @@ -87,7 +87,7 @@ phys_size_t fixed_sdram(void) } ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { @@ -114,20 +114,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1870, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c index dd5ea95e33..bd8560b555 100644 --- a/board/freescale/bsc9131rdb/spl_minimal.c +++ b/board/freescale/bsc9131rdb/spl_minimal.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -20,7 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; */ static void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index 669fe8ad32..c8ecf5de59 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/board/freescale/bsc9132qds/Kconfig b/board/freescale/bsc9132qds/Kconfig new file mode 100644 index 0000000000..db3a1f1d47 --- /dev/null +++ b/board/freescale/bsc9132qds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BSC9132QDS + +config SYS_BOARD + default "bsc9132qds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "BSC9132QDS" + +endif diff --git a/board/freescale/bsc9132qds/MAINTAINERS b/board/freescale/bsc9132qds/MAINTAINERS new file mode 100644 index 0000000000..3de62d3f46 --- /dev/null +++ b/board/freescale/bsc9132qds/MAINTAINERS @@ -0,0 +1,25 @@ +BSC9132QDS BOARD +M: Naveen Burmi +S: Maintained +F: board/freescale/bsc9132qds/ +F: include/configs/BSC9132QDS.h +F: configs/BSC9132QDS_NAND_DDRCLK100_defconfig +F: configs/BSC9132QDS_NAND_DDRCLK133_defconfig +F: configs/BSC9132QDS_NOR_DDRCLK100_defconfig +F: configs/BSC9132QDS_NOR_DDRCLK133_defconfig +F: configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig +F: configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig +F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig +F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig + +BSC9132QDS_NAND_DDRCLK100_SECURE BOARD +M: Aneesh Bansal +S: Maintained +F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig +F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig +F: configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig +F: configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig +F: configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig +F: configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig +F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig +F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile index 330d35333e..2e4170f512 100644 --- a/board/freescale/bsc9132qds/Makefile +++ b/board/freescale/bsc9132qds/Makefile @@ -4,10 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -18,36 +14,13 @@ endif ifdef MINIMAL -COBJS-y += spl_minimal.o tlb.o law.o +obj-y += spl_minimal.o tlb.o law.o else - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o +obj-y += bsc9132qds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o endif - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README index 4a3dbfe5d4..f8377c9aa4 100644 --- a/board/freescale/bsc9132qds/README +++ b/board/freescale/bsc9132qds/README @@ -23,14 +23,14 @@ Overview ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - - OCNDMA with four bidirectional channels - - SysDMA with sixteen bidirectional channels + - OCNDMA with four bidirectional channels + - SysDMA with sixteen bidirectional channels - Interfaces - - Four-lane SerDes PHY + - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - - Two Common Public Radio Interface (CPRI) controller lanes + - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - - Enhanced secure digital (SD/MMC) host controller (eSDHC) + - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 457489416a..36a68dbc4d 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -17,10 +17,13 @@ #include #include #include -#include +#include #include #include -#include +#include +#include +#include +#include #ifdef CONFIG_PCI #include @@ -125,11 +128,32 @@ void board_config_serdes_mux(void) } } +/* Configure DSP DDR controller */ +void dsp_ddr_configure(void) +{ + /* + *There are separate DDR-controllers for DSP and PowerPC side DDR. + *copy the ddr controller settings from PowerPC side DDR controller + *to the DSP DDR controller as connected DDR memories are similar. + */ + struct ccsr_ddr __iomem *pa_ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr temp_ddr; + struct ccsr_ddr __iomem *dsp_ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; + + memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr)); + temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; + temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; + memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr)); + dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; +} + int board_early_init_r(void) { #ifndef CONFIG_SYS_NO_FLASH const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -140,8 +164,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -153,6 +183,7 @@ int board_early_init_r(void) 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); #endif board_config_serdes_mux(); + dsp_ddr_configure(); return 0; } @@ -326,7 +357,13 @@ void fdt_del_node_compat(void *blob, const char *compatible) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "cfi-flash", MTD_DEV_TYPE_NOR, }, + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -341,6 +378,9 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 porbmsr = in_be32(&gur->porbmsr); @@ -383,5 +423,7 @@ void ft_board_setup(void *blob, bd_t *bd) printf("\nRemove sim from hwconfig and reset\n"); } } + + return 0; } #endif diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c index 05bea8ad52..43f163a2c6 100644 --- a/board/freescale/bsc9132qds/ddr.c +++ b/board/freescale/bsc9132qds/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include @@ -109,7 +109,7 @@ phys_size_t fixed_sdram(void) strmhz(buf, ddr_freq)); ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { @@ -136,20 +136,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1870, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c index fed2edf44a..e10de9adcf 100644 --- a/board/freescale/bsc9132qds/law.c +++ b/board/freescale/bsc9132qds/law.c @@ -16,6 +16,14 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_FPGA_BASE_PHYS SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), #endif + SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, + LAW_TRGT_IF_DSP_CCSR), + SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, + LAW_TRGT_IF_OCN_DSP), + SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, + LAW_TRGT_IF_CLASS_DSP), + SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, + LAW_TRGT_IF_CLASS_DSP) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c index 2bf0a0cfa8..8f71431926 100644 --- a/board/freescale/bsc9132qds/spl_minimal.c +++ b/board/freescale/bsc9132qds/spl_minimal.c @@ -10,14 +10,15 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; static void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; #if CONFIG_DDR_CLK_FREQ == 100000000 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c index 6d82353416..07febc2b37 100644 --- a/board/freescale/bsc9132qds/tlb.c +++ b/board/freescale/bsc9132qds/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), @@ -41,6 +41,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), + /* CCSRBAR (DSP) */ + SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, + CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, + MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), + #ifndef CONFIG_SPL_BUILD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, diff --git a/board/freescale/c29xpcie/Kconfig b/board/freescale/c29xpcie/Kconfig new file mode 100644 index 0000000000..17369b8ca7 --- /dev/null +++ b/board/freescale/c29xpcie/Kconfig @@ -0,0 +1,12 @@ +if TARGET_C29XPCIE + +config SYS_BOARD + default "c29xpcie" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "C29XPCIE" + +endif diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS new file mode 100644 index 0000000000..33088396f5 --- /dev/null +++ b/board/freescale/c29xpcie/MAINTAINERS @@ -0,0 +1,10 @@ +C29XPCIE BOARD +M: Po Liu +S: Maintained +F: board/freescale/c29xpcie/ +F: include/configs/C29XPCIE.h +F: configs/C29XPCIE_defconfig +F: configs/C29XPCIE_NAND_defconfig +F: configs/C29XPCIE_SPIFLASH_defconfig +F: configs/C29XPCIE_NOR_SECBOOT_defconfig +F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile new file mode 100644 index 0000000000..818484a57d --- /dev/null +++ b/board/freescale/c29xpcie/Makefile @@ -0,0 +1,25 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ + +MINIMAL= +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +obj-y += spl_minimal.o tlb.o law.o +else +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif + +obj-y += c29xpcie.o +obj-y += cpld.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +endif diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README new file mode 100644 index 0000000000..3bc396b35a --- /dev/null +++ b/board/freescale/c29xpcie/README @@ -0,0 +1,100 @@ +Overview +========= +C29XPCIE board is a series of Freescale PCIe add-in cards to perform +as public key crypto accelerator or secure key management module. +It includes C293PCIE board, C293PCIE board and C291PCIE board. +The Freescale C29x family is a high performance crypto co-processor. +It combines a single e500v2 core with necessary SEC engines. +(maximum core frequency 1000/1200 MHz). + +The C29xPCIE board features are as follows: +Memory subsystem: + - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 64 Mbyte NOR flash single-chip memory + - 4 Gbyte NAND flash memory + - 1 Mbit AT24C1024 I2C EEPROM + - 16 Mbyte SPI memory + +Interfaces: + - 10/100/1000 BaseT Ethernet ports: + - eTSEC1, RGMII: one 10/100/1000 port + - eTSEC2, RGMII: one 10/100/1000 port + - DUART interface: + - DUART interface: supports two UARTs up to 115200 bps for + console display + +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging + +Physical Memory Map on C29xPCIE +=============================== +Address Start Address End Memory type +0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR +0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory +0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash +0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM +0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO +0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD +0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR + +Serial Port Configuration on C29xPCIE +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + +Settings of DIP-switch +====================== + SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash + SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash +Note: 1 stands for 'off', 0 stands for 'on' + +Build and program u-boot to NOR flash +================================== +1. Build u-boot.bin image example: + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make C293PCIE + +2. Program u-boot.bin into NOR flash + => tftp $loadaddr $uboot + => protect off eff40000 +$filesize + => erase eff40000 +$filesize + => cp.b $loadaddr eff40000 $filesize + +3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on. + +Alternate NOR bank +================== +There are four banks in C29XPCIE board, example to change bank booting: +1. Program u-boot.bin into alternate NOR bank + => tftp $loadaddr $uboot + => protect off e9f40000 +$filesize + => erase e9f40000 +$filesize + => cp.b $loadaddr e9f40000 $filesize + +2. Switch to alternate NOR bank + => cpld_cmd reset altbank [bank] + - [bank] bank value select 1-4 + - bank 1 on the flash 0x0000000~0x0ffffff + - bank 2 on the flash 0x1000000~0x1ffffff + - bank 3 on the flash 0x2000000~0x2ffffff + - bank 4 on the flash 0x3000000~0x3ffffff + or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again. + +Build and program u-boot to SPI flash +================================== +1. Build u-boot-spi.bin image + make C29xPCIE_SPIFLASH_config; make + Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin. + +2. Program u-boot-spi.bin into SPI flash + => tftp $loadaddr $uboot-spi + => sf erase 0 100000 + => sf write $loadaddr 0 $filesize + +3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on. diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c new file mode 100644 index 0000000000..d75770969b --- /dev/null +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -0,0 +1,156 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("Board: %sPCIe, ", cpu->name); + printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver)); + + return 0; +} + +int board_early_init_f(void) +{ + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned long flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 1; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_64M, 1); + + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif /* ifdef CONFIG_PCI */ + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[2]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + /* Register 1G MDIO bus */ + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void fdt_del_sec(void *blob, int offset) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0", + CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET + + offset * 0x20000)) >= 0) { + fdt_del_node(blob, nodeoff); + offset++; + } +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + struct cpu_type *cpu; + + cpu = gd->arch.cpu; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + +#if defined(CONFIG_PCI) + FT_FSL_PCI_SETUP; +#endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + if (cpu->soc_ver == SVR_C291) + fdt_del_sec(blob, 1); + else if (cpu->soc_ver == SVR_C292) + fdt_del_sec(blob, 2); + + return 0; +} +#endif diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c new file mode 100644 index 0000000000..37722daf5b --- /dev/null +++ b/board/freescale/c29xpcie/cpld.c @@ -0,0 +1,133 @@ +/** + * Copyright 2013 Freescale Semiconductor + * Author: Mingkai Hu + * Po Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include +#include +#include + +#include "cpld.h" +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(u8 banksel) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 reg11; + + reg11 = in_8(&cpld_data->flhcsr); + + switch (banksel) { + case 1: + out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1); + break; + case 2: + out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2); + break; + case 3: + out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3); + break; + case 4: + out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4); + break; + default: + printf("Invalid value! [1-4]\n"); + return; + } + + udelay(100); + do_reset(NULL, 0, 0, NULL); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + cpld_set_altbank(4); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1)); + printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2)); + printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver)); + printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver)); + printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon)); + printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr)); + printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr)); + printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick)); + printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr)); + printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr)); + printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr)); + printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor)); + printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1)); + printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2)); + printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3)); + printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4)); + putc('\n'); +} +#endif + +#ifndef CONFIG_SPL_BUILD +int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + unsigned char value; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (!strcmp(argv[2], "altbank") && argv[3]) { + value = (u8)simple_strtoul(argv[3], NULL, 16); + cpld_set_altbank(value); + } else if (!argv[2]) + cpld_set_defbank(); + else + cmd_usage(cmdtp); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, + "Reset the board using the CPLD sequencer", + "reset - hard reset to default bank 4\n" + "cpld_cmd reset altbank [bank]- reset to alternate bank\n" + " - [bank] bank value select 1-4\n" + " - bank 1 on the flash 0x0000000~0x0ffffff\n" + " - bank 2 on the flash 0x1000000~0x1ffffff\n" + " - bank 3 on the flash 0x2000000~0x2ffffff\n" + " - bank 4 on the flash 0x3000000~0x3ffffff\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); +#endif diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h new file mode 100644 index 0000000000..20862a3c03 --- /dev/null +++ b/board/freescale/c29xpcie/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * Author: Mingkai Hu + * Po Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */ + u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */ + u8 hwver; /* 0x2 - Hardware Version Register */ + u8 cpldver; /* 0x3 - Software Version Register */ + u8 res[12]; + u8 rstcon; /* 0x10 - Reset control register */ + u8 flhcsr; /* 0x11 - Flash control and status Register */ + u8 wdcsr; /* 0x12 - Watchdog control and status Register */ + u8 wdkick; /* 0x13 - Watchdog kick Register */ + u8 fancsr; /* 0x14 - Fan control and status Register */ + u8 ledcsr; /* 0x15 - LED control and status Register */ + u8 misccsr; /* 0x16 - Misc control and status Register */ + u8 bootor; /* 0x17 - Boot configure override Register */ + u8 bootcfg1; /* 0x18 - Boot configure 1 Register */ + u8 bootcfg2; /* 0x19 - Boot configure 2 Register */ + u8 bootcfg3; /* 0x1a - Boot configure 3 Register */ + u8 bootcfg4; /* 0x1b - Boot configure 4 Register */ +}; + +#define CPLD_BANKSEL_EN 0x02 +#define CPLD_BANKSEL_MASK 0x3f +#define CPLD_SELECT_BANK1 0xc0 +#define CPLD_SELECT_BANK2 0x80 +#define CPLD_SELECT_BANK3 0x40 +#define CPLD_SELECT_BANK4 0x00 diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c new file mode 100644 index 0000000000..7c915b036f --- /dev/null +++ b/board/freescale/c29xpcie/ddr.c @@ -0,0 +1,107 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include "cpld.h" + +#define C29XPCIE_HARDWARE_REVA 0x40 +/* + * Micron MT41J128M16HA-15E + * */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 536870912u, + .capacity = 536870912u, + .primary_sdram_width = 32, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1650, + .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ + .taa_ps = 14050, + .twr_ps = 15000, + .trcd_ps = 13500, + .trrd_ps = 75000, + .trp_ps = 13500, + .tras_ps = 40000, + .trc_ps = 49500, + .trfc_ps = 160000, + .twtr_ps = 75000, + .trtp_ps = 75000, + .refresh_rate_ps = 7800000, + .tfaw_ps = 30000, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + int i; + + popts->clk_adjust = 4; + popts->cpo_override = 0x1f; + popts->write_data_delay = 4; + popts->half_strength_driver_enable = 1; + popts->bstopre = 0x3cf; + popts->quad_rank_present = 1; + popts->rtt_override = 1; + popts->rtt_override_value = 1; + popts->dynamic_power = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x4; + popts->trwt_override = 1; + popts->trwt = 0; + + if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA) + popts->ecc_mode = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c new file mode 100644 index 0000000000..80e5fff7c5 --- /dev/null +++ b/board/freescale/c29xpcie/law.c @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K, + LAW_TRGT_IF_PLATFORM_SRAM), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c new file mode 100644 index 0000000000..2111711400 --- /dev/null +++ b/board/freescale/c29xpcie/spl.c @@ -0,0 +1,77 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + + /* relocate environment function pointers etc. */ + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_NAND_BOOT + puts("TPL\n"); +#else + puts("SPL\n"); +#endif + + nand_boot(); +} diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c new file mode 100644 index 0000000000..8f96b67e84 --- /dev/null +++ b/board/freescale/c29xpcie/spl_minimal.c @@ -0,0 +1,63 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot...\n"); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + puts("SPL\n"); + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c new file mode 100644 index 0000000000..c5abed0504 --- /dev/null +++ b/board/freescale/c29xpcie/tlb.c @@ -0,0 +1,85 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_SPL_BUILD + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + +#ifdef CONFIG_PCI + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256K, 1), +#endif +#endif + + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_64K, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64K, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, + CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000, + CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_256K, 1), + +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_256M, 1), +#endif + +#ifdef CONFIG_SYS_INIT_L2_ADDR + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index d451f6ff01..14af660087 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -5,14 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/freescale/common) -endif - -LIB = $(obj)libfreescale.o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -21,64 +13,63 @@ MINIMAL=y endif endif -ifndef MINIMAL -COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o -COBJS-$(CONFIG_FSL_VIA) += cds_via.o -COBJS-$(CONFIG_FMAN_ENET) += fman.o -COBJS-$(CONFIG_FSL_PIXIS) += pixis.o +ifdef MINIMAL +# necessary to create built-in.o +obj- := __dummy__.o +else +obj-$(CONFIG_FSL_CADMUS) += cadmus.o +obj-$(CONFIG_FSL_VIA) += cds_via.o +obj-$(CONFIG_FMAN_ENET) += fman.o +obj-$(CONFIG_FSL_PIXIS) += pixis.o ifndef CONFIG_SPL_BUILD -COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +obj-$(CONFIG_VID) += vid.o endif -COBJS-$(CONFIG_FSL_QIXIS) += qixis.o -COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o +obj-$(CONFIG_FSL_QIXIS) += qixis.o +obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o ifndef CONFIG_SPL_BUILD -COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o +obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o endif -COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o +obj-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o ifndef CONFIG_RAMBOOT_PBL -COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o +obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif -COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o -COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o -COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o +obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o -COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o -COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o -ifndef CONFIG_SPL_BUILD -COBJS-$(CONFIG_P1022DS) += ics307_clk.o +ifdef CONFIG_ARM +obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o +else +obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o endif -COBJS-$(CONFIG_P2020DS) += ics307_clk.o -COBJS-$(CONFIG_P3041DS) += ics307_clk.o -COBJS-$(CONFIG_P4080DS) += ics307_clk.o -COBJS-$(CONFIG_P5020DS) += ics307_clk.o -COBJS-$(CONFIG_P5040DS) += ics307_clk.o -COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o -# deal with common files for P-series corenet based devices -SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o -endif - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -SUBLIB := $(addprefix $(obj),$(SUBLIB-y)) - -$(LIB): $(obj).depend $(OBJS) $(SUBLIB) - $(call cmd_link_o_target, $(OBJS) $(SUBLIB)) +obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o -$(SUBLIB): $(obj).depend - $(MAKE) -C $(dir $(subst $(obj),,$@)) +obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o +obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o +obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o -######################################################################### +obj-$(CONFIG_MPC8536DS) += ics307_clk.o +obj-$(CONFIG_MPC8572DS) += ics307_clk.o +obj-$(CONFIG_P1022DS) += ics307_clk.o +obj-$(CONFIG_P2020DS) += ics307_clk.o +obj-$(CONFIG_P3041DS) += ics307_clk.o +obj-$(CONFIG_P4080DS) += ics307_clk.o +obj-$(CONFIG_P5020DS) += ics307_clk.o +obj-$(CONFIG_P5040DS) += ics307_clk.o +obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o +obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o +obj-$(CONFIG_ZM7300) += zm7300.o +obj-$(CONFIG_POWER_PFUZE100) += pfuze.o -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o -sinclude $(obj).depend +# deal with common files for P-series corenet based devices +obj-$(CONFIG_P2041RDB) += p_corenet/ +obj-$(CONFIG_P3041DS) += p_corenet/ +obj-$(CONFIG_P4080DS) += p_corenet/ +obj-$(CONFIG_P5020DS) += p_corenet/ +obj-$(CONFIG_P5040DS) += p_corenet/ -######################################################################### +obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o +endif diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c new file mode 100644 index 0000000000..6a406915b0 --- /dev/null +++ b/board/freescale/common/arm_sleep.c @@ -0,0 +1,95 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT) +#error " Deep sleep needs non-secure mode support. " +#else +#include +#endif +#include +#include + +#if defined(CONFIG_SOC_LS102XA) +#include +#endif + +#include "sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_le32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; + + flush_dcache_all(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + board_sleep_prepare(); + armv7_init_nonsec(); + cleanup_before_linux(); +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_le32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); + + return 0; +} diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c index 7772f9f99c..dad684773b 100644 --- a/board/freescale/common/cadmus.c +++ b/board/freescale/common/cadmus.c @@ -1,7 +1,7 @@ /* * Copyright 2004, 2011 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/board/freescale/common/cadmus.h b/board/freescale/common/cadmus.h index 959ea21714..7867192825 100644 --- a/board/freescale/common/cadmus.h +++ b/board/freescale/common/cadmus.h @@ -1,7 +1,7 @@ /* * Copyright 2004 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CADMUS_H_ diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 4cd804577b..571dfbbaad 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -1,7 +1,7 @@ /* * Copyright 2004 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -63,13 +63,14 @@ static void cds_pci_fixup(void *blob) } } -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); cds_pci_fixup(blob); #endif + + return 0; } #endif diff --git a/board/freescale/common/cds_via.c b/board/freescale/common/cds_via.c index 76631fa452..028b093ec4 100644 --- a/board/freescale/common/cds_via.c +++ b/board/freescale/common/cds_via.c @@ -1,7 +1,7 @@ /* * Copyright 2006 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c new file mode 100644 index 0000000000..2da627e1f9 --- /dev/null +++ b/board/freescale/common/dcu_sii9022a.c @@ -0,0 +1,153 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define PIXEL_CLK_LSB_REG 0x00 +#define PIXEL_CLK_MSB_REG 0x01 +#define VERT_FREQ_LSB_REG 0x02 +#define VERT_FREQ_MSB_REG 0x03 +#define TOTAL_PIXELS_LSB_REG 0x04 +#define TOTAL_PIXELS_MSB_REG 0x05 +#define TOTAL_LINES_LSB_REG 0x06 +#define TOTAL_LINES_MSB_REG 0x07 +#define TPI_INBUS_FMT_REG 0x08 +#define TPI_INPUT_FMT_REG 0x09 +#define TPI_OUTPUT_FMT_REG 0x0A +#define TPI_SYS_CTRL_REG 0x1A +#define TPI_PWR_STAT_REG 0x1E +#define TPI_AUDIO_HANDING_REG 0x25 +#define TPI_AUDIO_INTF_REG 0x26 +#define TPI_AUDIO_FREQ_REG 0x27 +#define TPI_SET_PAGE_REG 0xBC +#define TPI_SET_OFFSET_REG 0xBD +#define TPI_RW_ACCESS_REG 0xBE +#define TPI_TRANS_MODE_REG 0xC7 + +#define TPI_INBUS_CLOCK_RATIO_1 (1 << 6) +#define TPI_INBUS_FULL_PIXEL_WIDE (1 << 5) +#define TPI_INBUS_RISING_EDGE (1 << 4) +#define TPI_INPUT_CLR_DEPTH_8BIT (0 << 6) +#define TPI_INPUT_VRANGE_EXPAN_AUTO (0 << 2) +#define TPI_INPUT_CLR_RGB (0 << 0) +#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 << 6) +#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 << 2) +#define TPI_OUTPUT_CLR_HDMI_RGB (0 << 0) +#define TPI_SYS_TMDS_OUTPUT (0 << 4) +#define TPI_SYS_AV_NORAML (0 << 3) +#define TPI_SYS_AV_MUTE (1 << 3) +#define TPI_SYS_DVI_MODE (0 << 0) +#define TPI_SYS_HDMI_MODE (1 << 0) +#define TPI_PWR_STAT_MASK (3 << 0) +#define TPI_PWR_STAT_D0 (0 << 0) +#define TPI_AUDIO_PASS_BASIC (0 << 0) +#define TPI_AUDIO_INTF_I2S (2 << 6) +#define TPI_AUDIO_INTF_NORMAL (0 << 4) +#define TPI_AUDIO_TYPE_PCM (1 << 0) +#define TPI_AUDIO_SAMP_SIZE_16BIT (1 << 6) +#define TPI_AUDIO_SAMP_FREQ_44K (2 << 3) +#define TPI_SET_PAGE_SII9022A 0x01 +#define TPI_SET_OFFSET_SII9022A 0x82 +#define TPI_RW_EN_SRC_TERMIN (1 << 0) +#define TPI_TRANS_MODE_ENABLE (0 << 7) + +/* Programming of Silicon SIi9022a HDMI Transmitter */ +int dcu_set_dvi_encoder(struct fb_videomode *videomode) +{ + u8 temp; + u16 temp1, temp2; + u32 temp3; + + i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); + + /* Enable TPI transmitter mode */ + temp = TPI_TRANS_MODE_ENABLE; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1); + + /* Enter into D0 state, full operation */ + i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1); + temp &= ~TPI_PWR_STAT_MASK; + temp |= TPI_PWR_STAT_D0; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1); + + /* Enable source termination */ + temp = TPI_SET_PAGE_SII9022A; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1); + temp = TPI_SET_OFFSET_SII9022A; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1); + + i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1); + temp |= TPI_RW_EN_SRC_TERMIN; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1); + + /* Set TPI system control */ + temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1); + + /* Set pixel clock */ + temp1 = PICOS2KHZ(videomode->pixclock) / 10; + temp = (u8)(temp1 & 0xFF); + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1); + temp = (u8)(temp1 >> 8); + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1); + + /* Set total pixels per line */ + temp1 = videomode->hsync_len + videomode->left_margin + + videomode->xres + videomode->right_margin; + temp = (u8)(temp1 & 0xFF); + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1); + temp = (u8)(temp1 >> 8); + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1); + + /* Set total lines */ + temp2 = videomode->vsync_len + videomode->upper_margin + + videomode->yres + videomode->lower_margin; + temp = (u8)(temp2 & 0xFF); + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1); + temp = (u8)(temp2 >> 8); + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1); + + /* Set vertical frequency in Hz */ + temp3 = temp1 * temp2; + temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3; + temp1 = (u16)temp3 * 100; + temp = (u8)(temp1 & 0xFF); + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1); + temp = (u8)(temp1 >> 8); + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1); + + /* Set TPI input bus and pixel repetition data */ + temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE | + TPI_INBUS_RISING_EDGE; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1); + + /* Set TPI AVI Input format data */ + temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO | + TPI_INPUT_CLR_RGB; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1); + + /* Set TPI AVI Output format data */ + temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO | + TPI_OUTPUT_CLR_HDMI_RGB; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1); + + /* Set TPI audio configuration write data */ + temp = TPI_AUDIO_PASS_BASIC; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1); + + temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL | + TPI_AUDIO_TYPE_PCM; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1); + + temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; + i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1); + + return 0; +} diff --git a/board/freescale/common/dcu_sii9022a.h b/board/freescale/common/dcu_sii9022a.h new file mode 100644 index 0000000000..de76733b36 --- /dev/null +++ b/board/freescale/common/dcu_sii9022a.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DCU_HDMI_SII9022A__ +#define __DCU_HDMI_SII9022A__ + +/* Programming of Silicon SII9022A connector HDMI Transmitter*/ +int dcu_set_dvi_encoder(struct fb_videomode *videomode); + +#endif diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c new file mode 100644 index 0000000000..82ce870b13 --- /dev/null +++ b/board/freescale/common/diu_ch7301.c @@ -0,0 +1,136 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Authors: Priyanka Jain + * Wang Dongsheng + * + * This file is copied and modified from the original t1040qds/diu.c. + * Encoder can be used in T104x and LSx Platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F +#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 +#define I2C_DVI_PLL_DIVIDER_REG 0x34 +#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 +#define I2C_DVI_PLL_FILTER_REG 0x36 +#define I2C_DVI_TEST_PATTERN_REG 0x48 +#define I2C_DVI_POWER_MGMT_REG 0x49 +#define I2C_DVI_LOCK_STATE_REG 0x4D +#define I2C_DVI_SYNC_POLARITY_REG 0x56 + +/* + * Set VSYNC/HSYNC to active high. This is polarity of sync signals + * from DIU->DVI. The DIU default is active igh, so DVI is set to + * active high. + */ +#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 + +#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 +#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 +#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 +#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 +#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 +#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 + +/* Clear test pattern */ +#define I2C_DVI_TEST_PATTERN_VAL 0x18 +/* Exit Power-down mode */ +#define I2C_DVI_POWER_MGMT_VAL 0xC0 + +/* Monitor polarity is handled via DVI Sync Polarity Register */ +#define I2C_DVI_SYNC_POLARITY_VAL 0x00 + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock) +{ + int ret; + u8 temp; + + temp = I2C_DVI_TEST_PATTERN_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select proper dvi test pattern\n"); + return ret; + } + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, + 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi input data format\n"); + return ret; + } + + /* Set Sync polarity register */ + temp = I2C_DVI_SYNC_POLARITY_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi syc polarity\n"); + return ret; + } + + /* Set PLL registers based on pixel clock rate*/ + if (pixclock > 65000000) { + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } else { + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } + + temp = I2C_DVI_POWER_MGMT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi power mgmt\n"); + return ret; + } + + udelay(500); + + return 0; +} diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h new file mode 100644 index 0000000000..8b6ead0874 --- /dev/null +++ b/board/freescale/common/diu_ch7301.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DIU_HDMI_CH7301__ +#define __DIU_HDMI_CH7301__ + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock); + +#endif diff --git a/board/freescale/common/eeprom.h b/board/freescale/common/eeprom.h index 222405bb3b..efdba4e503 100644 --- a/board/freescale/common/eeprom.h +++ b/board/freescale/common/eeprom.h @@ -1,7 +1,7 @@ /* * Copyright 2004 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __EEPROM_H_ diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 6789efb9c3..e683be324a 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -67,7 +67,7 @@ unsigned long ics307_sysclk_calculator(unsigned long out_freq) continue; /* Calculate the temp out frequency */ tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); - diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out); + diff = max(out_freq, tmp_out) - min(out_freq, tmp_out); /* * calculate the percent, the precision is 1/1000 * If greater than 1/1000, continue diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c b/board/freescale/common/idt8t49n222a_serdes_clk.c new file mode 100644 index 0000000000..d347162277 --- /dev/null +++ b/board/freescale/common/idt8t49n222a_serdes_clk.c @@ -0,0 +1,207 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Author: Shaveta Leekha + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "idt8t49n222a_serdes_clk.h" + +#define DEVICE_ID_REG 0x00 + +static int check_pll_status(u8 idt_addr) +{ + u8 val = 0; + int ret; + + ret = i2c_read(idt_addr, 0x17, 1, &val, 1); + if (ret < 0) { + printf("IDT:0x%x could not read status register from device.\n", + idt_addr); + return ret; + } + + if (val & 0x04) { + debug("idt8t49n222a PLL is LOCKED: %x\n", val); + } else { + printf("idt8t49n222a PLL is not LOCKED: %x\n", val); + return -1; + } + + return 0; +} + +int set_serdes_refclk(u8 idt_addr, u8 serdes_num, + enum serdes_refclk refclk1, + enum serdes_refclk refclk2, u8 feedback) +{ + u8 dev_id = 0; + int i, ret; + + debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n", + idt_addr); + + ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1); + if (ret < 0) { + debug("IDT:0x%x could not read DEV_ID from device.\n", + idt_addr); + return ret; + } + + if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) { + debug("IDT: device at address 0x%x is not idt8t49n222a.\n", + idt_addr); + } + + if (serdes_num != 1 && serdes_num != 2) { + debug("serdes_num should be 1 for SerDes1 and" + " 2 for SerDes2.\n"); + return -1; + } + + if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88) + || (refclk1 != SERDES_REFCLK_122_88 + && refclk2 == SERDES_REFCLK_122_88)) { + debug("Only one refclk at 122.88MHz is not supported." + " Please set both refclk1 & refclk2 to 122.88MHz" + " or both not to 122.88MHz.\n"); + return -1; + } + + if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88 + && refclk1 != SERDES_REFCLK_125 + && refclk1 != SERDES_REFCLK_156_25) { + debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz" + " or 156.25MHz.\n"); + return -1; + } + + if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88 + && refclk2 != SERDES_REFCLK_125 + && refclk2 != SERDES_REFCLK_156_25) { + debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz" + " or 156.25MHz.\n"); + return -1; + } + + if (feedback != 0 && feedback != 1) { + debug("valid values for feedback are 0(default) or 1.\n"); + return -1; + } + + /* Configuring IDT for output refclks as + * Refclk1 = 122.88MHz Refclk2 = 122.88MHz + */ + if (refclk1 == SERDES_REFCLK_122_88 && + refclk2 == SERDES_REFCLK_122_88) { + printf("Setting refclk1:122.88 and refclk2:122.88\n"); + for (i = 0; i < NUM_IDT_REGS; i++) + i2c_reg_write(idt_addr, idt_conf_122_88[i][0], + idt_conf_122_88[i][1]); + + if (feedback) { + for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++) + i2c_reg_write(idt_addr, + idt_conf_122_88_feedback[i][0], + idt_conf_122_88_feedback[i][1]); + } + } + + if (refclk1 != SERDES_REFCLK_122_88 && + refclk2 != SERDES_REFCLK_122_88) { + for (i = 0; i < NUM_IDT_REGS; i++) + i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0], + idt_conf_not_122_88[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 100MHz Refclk2 = 125MHz + */ + if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) { + printf("Setting refclk1:100 and refclk2:125\n"); + i2c_reg_write(idt_addr, 0x11, 0x10); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 125MHz Refclk2 = 125MHz + */ + if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) { + printf("Setting refclk1:125 and refclk2:125\n"); + i2c_reg_write(idt_addr, 0x10, 0x10); + i2c_reg_write(idt_addr, 0x11, 0x10); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 125MHz Refclk2 = 100MHz + */ + if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) { + printf("Setting refclk1:125 and refclk2:100\n"); + i2c_reg_write(idt_addr, 0x10, 0x10); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 156.25MHz Refclk2 = 156.25MHz + */ + if (refclk1 == SERDES_REFCLK_156_25 && + refclk2 == SERDES_REFCLK_156_25) { + printf("Setting refclk1:156.25 and refclk2:156.25\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_156_25[i][0], + idt_conf_156_25[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 100MHz Refclk2 = 156.25MHz + */ + if (refclk1 == SERDES_REFCLK_100 && + refclk2 == SERDES_REFCLK_156_25) { + printf("Setting refclk1:100 and refclk2:156.25\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0], + idt_conf_100_156_25[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 125MHz Refclk2 = 156.25MHz + */ + if (refclk1 == SERDES_REFCLK_125 && + refclk2 == SERDES_REFCLK_156_25) { + printf("Setting refclk1:125 and refclk2:156.25\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0], + idt_conf_125_156_25[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 156.25MHz Refclk2 = 100MHz + */ + if (refclk1 == SERDES_REFCLK_156_25 && + refclk2 == SERDES_REFCLK_100) { + printf("Setting refclk1:156.25 and refclk2:100\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0], + idt_conf_156_25_100[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 156.25MHz Refclk2 = 125MHz + */ + if (refclk1 == SERDES_REFCLK_156_25 && + refclk2 == SERDES_REFCLK_125) { + printf("Setting refclk1:156.25 and refclk2:125\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0], + idt_conf_156_25_125[i][1]); + } + + /* waiting for maximum of 1 second if PLL doesn'r get locked + * initially. then check the status again. + */ + if (check_pll_status(idt_addr)) { + mdelay(1000); + if (check_pll_status(idt_addr)) + return -1; + } + + return 0; +} diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.h b/board/freescale/common/idt8t49n222a_serdes_clk.h new file mode 100644 index 0000000000..787bdd9ca4 --- /dev/null +++ b/board/freescale/common/idt8t49n222a_serdes_clk.h @@ -0,0 +1,107 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Author: Shaveta Leekha + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IDT8T49N222A_SERDES_CLK_H_ +#define __IDT8T49N222A_SERDES_CLK_H_ 1 + +#include +#include +#include "qixis.h" +#include "../b4860qds/b4860qds_qixis.h" +#include + +#define NUM_IDT_REGS 23 +#define NUM_IDT_REGS_FEEDBACK 12 +#define NUM_IDT_REGS_156_25 11 + +/* CLK */ +enum serdes_refclk { + SERDES_REFCLK_100, /* refclk 100Mhz */ + SERDES_REFCLK_122_88, /* refclk 122.88Mhz */ + SERDES_REFCLK_125, /* refclk 125Mhz */ + SERDES_REFCLK_156_25, /* refclk 156.25Mhz */ + SERDES_REFCLK_NONE = -1, +}; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 = 122.88MHz Refclk2 = 122.88MHz + */ +static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00}, + {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00}, + {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, + {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, + {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12}, + {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, + {0x16, 0xA0} }; + + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz + */ +static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00}, + {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00}, + {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, + {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, + {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14}, + {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, + {0x16, 0xA0} }; + +/* Reconfiguration values for some of IDT registers for + * Output Refclks: + * Refclk1 = 122.88MHz Refclk2 = 122.88MHz + * and with feedback as 1 + */ +static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7}, + {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07}, + {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B}, + {0x14, 0x00}, {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 156.25MHz Refclk2 : 156.25MHz + */ +static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 100MHz Refclk2 : 156.25MHz + */ +static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 125MHz Refclk2 : 156.25MHz + */ +static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 156.25MHz Refclk2 : 100MHz + */ +static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 156.25MHz Refclk2 : 125MHz + */ +static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +int set_serdes_refclk(u8 idt_addr, u8 serdes_num, + enum serdes_refclk refclk1, + enum serdes_refclk refclk2, u8 feedback); + +#endif /*__IDT8T49N222A_SERDES_CLK_H_ */ diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c new file mode 100644 index 0000000000..6154c9c458 --- /dev/null +++ b/board/freescale/common/ls102xa_stream_id.c @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) +{ + uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR; + int i; + + for (i = 0; i < num; i++) + out_be32(scfg + id[i].offset, id[i].stream_id); +} diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c new file mode 100644 index 0000000000..f924e7f482 --- /dev/null +++ b/board/freescale/common/mpc85xx_sleep.c @@ -0,0 +1,88 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + volatile u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_be32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; + + flush_dcache(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + + board_sleep_prepare(); + + l2cache_init(); +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif + enable_cpc(); +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_be32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + kernel_resume(); + + return 0; +} diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c new file mode 100644 index 0000000000..d7de9822d0 --- /dev/null +++ b/board/freescale/common/ns_access.c @@ -0,0 +1,30 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +{ + u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; + u32 *reg; + uint32_t val; + int i; + + for (i = 0; i < num; i++) { + reg = base + ns_dev[i].ind / 2; + val = in_be32(reg); + if (ns_dev[i].ind % 2 == 0) { + val &= 0x0000ffff; + val |= ns_dev[i].val << 16; + } else { + val &= 0xffff0000; + val |= ns_dev[i].val; + } + out_be32(reg, val); + } +} diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile index f37b25cf83..1f399d2496 100644 --- a/board/freescale/common/p_corenet/Makefile +++ b/board/freescale/common/p_corenet/Makefile @@ -4,12 +4,7 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = libp_corenet.o - -COBJS-y += law.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-y += tlb.o - -include $(TOPDIR)/post/rules.mk +obj-y += law.o +obj-$(CONFIG_PCI) += pci.o +obj-y += tlb.o diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c new file mode 100644 index 0000000000..2cd1794429 --- /dev/null +++ b/board/freescale/common/pfuze.c @@ -0,0 +1,54 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct pmic *pfuze_common_init(unsigned char i2cbus) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(i2cbus); + if (ret) + return NULL; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set SW1AB stanby volage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + + return p; +} diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h new file mode 100644 index 0000000000..7a4126cca0 --- /dev/null +++ b/board/freescale/common/pfuze.h @@ -0,0 +1,12 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PFUZE_BOARD_HELPER__ +#define __PFUZE_BOARD_HELPER__ + +struct pmic *pfuze_common_init(unsigned char i2cbus); + +#endif diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 5f7a67d057..1eb37866e3 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -63,7 +63,7 @@ int pib_init(void) #endif #if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS) +#if defined(CONFIG_MPC8569MDS) val8 = 0; i2c_write(0x20, 0x6, 1, &val8, 1); i2c_write(0x20, 0x7, 1, &val8, 1); diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 40ce6b082d..a49e3006d9 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -107,6 +107,26 @@ const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) return buf; } +#ifdef QIXIS_RST_FORCE_MEM +void board_assert_mem_reset(void) +{ + u8 rst; + + rst = QIXIS_READ(rst_frc[0]); + if (!(rst & QIXIS_RST_FORCE_MEM)) + QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM); +} + +void board_deassert_mem_reset(void) +{ + u8 rst; + + rst = QIXIS_READ(rst_frc[0]); + if (rst & QIXIS_RST_FORCE_MEM) + QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM); +} +#endif + void qixis_reset(void) { QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 26e2eeb2ff..52d20219ec 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -79,7 +79,9 @@ struct qixis { u8 clk_freq[6]; /* Clock Measurement Registers */ u8 res_c6[8]; u8 clk_base[2]; /* Clock Frequency Base Reg */ - u8 res_d0[16]; + u8 res_d0[8]; + u8 cms[2]; /* Core Management Space Address Register, 0xD8 */ + u8 res_c0[6]; u8 aux2[4]; /* Auxiliary Registers,0xE0 */ u8 res14[10]; u8 aux_ad; @@ -98,8 +100,15 @@ u8 qixis_read_i2c(unsigned int reg); void qixis_write_i2c(unsigned int reg, u8 value); #endif +#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) +#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) \ + qixis_write_i2c(offsetof(struct qixis, reg), value) +#else #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE_I2C(reg, value) \ diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index f6e2b2bbd6..022f38b117 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -16,6 +16,8 @@ #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50 +#define ESDHC_DEFAULT_ENVADDR 0x400 + int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) { u8 *tmp_buf; @@ -39,6 +41,33 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) /* Get the code size from offset 0x48 */ code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE); +#ifdef CONFIG_ESDHC_HC_BLK_ADDR + /* + * On soc BSC9131, BSC9132: + * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and + * code length of these soc specify the memory address in block address + * format. Block length is fixed to 512 bytes as per the SD High + * Capacity specification. + */ + u64 tmp; + + if (mmc->high_capacity) { + tmp = (u64)code_offset * blklen; + tmp += code_len * blklen; + } else + tmp = code_offset + code_len; + + if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) || + (tmp > 0xFFFFFFFFU)) + *env_addr = ESDHC_DEFAULT_ENVADDR; + else + *env_addr = tmp; + + free(tmp_buf); + + return 0; +#endif + *env_addr = code_offset + code_len; free(tmp_buf); diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h new file mode 100644 index 0000000000..c26c54264f --- /dev/null +++ b/board/freescale/common/sleep.h @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SLEEP_H +#define __SLEEP_H + +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) +#define DDR_BUFF_LEN 128 + +/* determine if it is a wakeup from deep sleep */ +bool is_warm_boot(void); + +/* disable console output */ +void fsl_dp_disable_console(void); + +/* clean up everything and jump to kernel */ +int fsl_dp_resume(void); +#endif diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index d7893644cd..5cb7570c8b 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -18,7 +18,11 @@ #endif #ifdef CONFIG_SYS_I2C_EEPROM_NXID -#define MAX_NUM_PORTS 23 +/* some boards with non-256-bytes EEPROM have special define */ +/* for MAX_NUM_PORTS in board-specific file */ +#ifndef MAX_NUM_PORTS +#define MAX_NUM_PORTS 16 +#endif #define NXID_VERSION 1 #endif @@ -54,8 +58,9 @@ static struct __attribute__ ((__packed__)) eeprom { u8 res_1[21]; /* 0x2b - 0x3f Reserved */ u8 mac_count; /* 0x40 Number of MAC addresses */ u8 mac_flag; /* 0x41 MAC table flags */ - u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */ - u32 crc; /* x+1 CRC32 checksum */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */ + u8 res_2[90]; /* 0xa2 - 0xfb Reserved */ + u32 crc; /* 0xfc - 0xff CRC32 checksum */ #endif } e; @@ -85,7 +90,7 @@ static void show_eeprom(void) /* EEPROM tag ID, either CCID or NXID */ #ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); + e.version); #else printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif @@ -109,7 +114,7 @@ static void show_eeprom(void) e.date[3] & 0x80 ? "PM" : ""); /* Show MAC addresses */ - for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) { + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { u8 *p = e.mac[i]; @@ -218,7 +223,7 @@ static int prog_eeprom(void) */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min((sizeof(e) - i), 8)); + p, min((int)(sizeof(e) - i), 8)); if (ret) break; udelay(5000); /* 5ms write cycle timing */ @@ -421,13 +426,13 @@ int mac_read_from_eeprom(void) if (read_eeprom()) { printf("Read failed.\n"); - return -1; + return 0; } if (!is_valid) { printf("Invalid ID (%02x %02x %02x %02x)\n", e.id[0], e.id[1], e.id[2], e.id[3]); - return -1; + return 0; } #ifdef CONFIG_SYS_I2C_EEPROM_NXID @@ -443,7 +448,7 @@ int mac_read_from_eeprom(void) crcp = (void *)&e + crc_offset; if (crc != be32_to_cpu(*crcp)) { printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc)); - return -1; + return 0; } #ifdef CONFIG_SYS_I2C_EEPROM_NXID @@ -456,7 +461,7 @@ int mac_read_from_eeprom(void) memset(e.mac[8], 0xff, 6); #endif - for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) { + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { char ethaddr[18]; @@ -480,7 +485,7 @@ int mac_read_from_eeprom(void) #ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); + e.version); #else printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c new file mode 100644 index 0000000000..6b8af14e7a --- /dev/null +++ b/board/freescale/common/vid.c @@ -0,0 +1,491 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "vid.h" + +DECLARE_GLOBAL_DATA_PTR; + +int __weak i2c_multiplexer_select_vid_channel(u8 channel) +{ + return 0; +} + +/* + * Compensate for a board specific voltage drop between regulator and SoC + * return a value in mV + */ +int __weak board_vdd_drop_compensation(void) +{ + return 0; +} + +/* + * Get the i2c address configuration for the IR regulator chip + * + * There are some variance in the RDB HW regarding the I2C address configuration + * for the IR regulator chip, which is likely a problem of external resistor + * accuracy. So we just check each address in a hopefully non-intrusive mode + * and use the first one that seems to work + * + * The IR chip can show up under the following addresses: + * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) + * 0x09 (Verified on T1040RDB-PA) + * 0x38 (Verified on T2080QDS, T2081QDS) + */ +static int find_ir_chip_on_i2c(void) +{ + int i2caddress; + int ret; + u8 byte; + int i; + const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; + + /* Check all the address */ + for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { + i2caddress = ir_i2c_addr[i]; + ret = i2c_read(i2caddress, + IR36021_MFR_ID_OFFSET, 1, (void *)&byte, + sizeof(byte)); + if ((ret >= 0) && (byte == IR36021_MFR_ID)) + return i2caddress; + } + return -1; +} + +/* Maximum loop count waiting for new voltage to take effect */ +#define MAX_LOOP_WAIT_NEW_VOL 100 +/* Maximum loop count waiting for the voltage to be stable */ +#define MAX_LOOP_WAIT_VOL_STABLE 100 +/* + * read_voltage from sensor on I2C bus + * We use average of 4 readings, waiting for WAIT_FOR_ADC before + * another reading + */ +#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ + +/* If an INA220 chip is available, we can use it to read back the voltage + * as it may have a higher accuracy than the IR chip for the same purpose + */ +#ifdef CONFIG_VOL_MONITOR_INA220 +#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ +#define ADC_MIN_ACCURACY 4 +#else +#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */ +#define ADC_MIN_ACCURACY 4 +#endif + +#ifdef CONFIG_VOL_MONITOR_INA220 +static int read_voltage_from_INA220(int i2caddress) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + u8 buf[2]; + + for (i = 0; i < NUM_READINGS; i++) { + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + I2C_VOL_MONITOR_BUS_V_OFFSET, 1, + (void *)&buf, 2); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + vol_mon = (buf[0] << 8) | buf[1]; + if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%04x\n", vol_mon); + /* LSB = 4mv */ + voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; + udelay(WAIT_FOR_ADC); + } + /* calculate the average */ + voltage_read /= NUM_READINGS; + + return voltage_read; +} +#endif + +/* read voltage from IR */ +#ifdef CONFIG_VOL_MONITOR_IR36021_READ +static int read_voltage_from_IR(int i2caddress) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + u8 buf; + + for (i = 0; i < NUM_READINGS; i++) { + ret = i2c_read(i2caddress, + IR36021_LOOP1_VOUT_OFFSET, + 1, (void *)&buf, 1); + if (ret) { + printf("VID: failed to read vcpu\n"); + return ret; + } + vol_mon = buf; + if (!vol_mon) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%02x\n", vol_mon); + /* Resolution is 1/128V. We scale up here to get 1/128mV + * and divide at the end + */ + voltage_read += vol_mon * 1000; + udelay(WAIT_FOR_ADC); + } + /* Scale down to the real mV as IR resolution is 1/128V, rounding up */ + voltage_read = DIV_ROUND_UP(voltage_read, 128); + + /* calculate the average */ + voltage_read /= NUM_READINGS; + + /* Compensate for a board specific voltage drop between regulator and + * SoC before converting into an IR VID value + */ + voltage_read -= board_vdd_drop_compensation(); + + return voltage_read; +} +#endif + +static int read_voltage(int i2caddress) +{ + int voltage_read; +#ifdef CONFIG_VOL_MONITOR_INA220 + voltage_read = read_voltage_from_INA220(i2caddress); +#elif defined CONFIG_VOL_MONITOR_IR36021_READ + voltage_read = read_voltage_from_IR(i2caddress); +#else + return -1; +#endif + return voltage_read; +} + +/* + * We need to calculate how long before the voltage stops to drop + * or increase. It returns with the loop count. Each loop takes + * several readings (WAIT_FOR_ADC) + */ +static int wait_for_new_voltage(int vdd, int i2caddress) +{ + int timeout, vdd_current; + + vdd_current = read_voltage(i2caddress); + /* wait until voltage starts to reach the target. Voltage slew + * rates by typical regulators will always lead to stable readings + * within each fairly long ADC interval in comparison to the + * intended voltage delta change until the target voltage is + * reached. The fairly small voltage delta change to any target + * VID voltage also means that this function will always complete + * within few iterations. If the timeout was ever reached, it would + * point to a serious failure in the regulator system. + */ + for (timeout = 0; + abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) && + timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) { + vdd_current = read_voltage(i2caddress); + } + if (timeout >= MAX_LOOP_WAIT_NEW_VOL) { + printf("VID: Voltage adjustment timeout\n"); + return -1; + } + return timeout; +} + +/* + * this function keeps reading the voltage until it is stable or until the + * timeout expires + */ +static int wait_for_voltage_stable(int i2caddress) +{ + int timeout, vdd_current, vdd; + + vdd = read_voltage(i2caddress); + udelay(NUM_READINGS * WAIT_FOR_ADC); + + /* wait until voltage is stable */ + vdd_current = read_voltage(i2caddress); + /* The maximum timeout is + * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC + */ + for (timeout = MAX_LOOP_WAIT_VOL_STABLE; + abs(vdd - vdd_current) > ADC_MIN_ACCURACY && + timeout > 0; timeout--) { + vdd = vdd_current; + udelay(NUM_READINGS * WAIT_FOR_ADC); + vdd_current = read_voltage(i2caddress); + } + if (timeout == 0) + return -1; + return vdd_current; +} + +#ifdef CONFIG_VOL_MONITOR_IR36021_SET +/* Set the voltage to the IR chip */ +static int set_voltage_to_IR(int i2caddress, int vdd) +{ + int wait, vdd_last; + int ret; + u8 vid; + + /* Compensate for a board specific voltage drop between regulator and + * SoC before converting into an IR VID value + */ + vdd += board_vdd_drop_compensation(); + vid = DIV_ROUND_UP(vdd - 245, 5); + + ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, + 1, (void *)&vid, sizeof(vid)); + if (ret) { + printf("VID: failed to write VID\n"); + return -1; + } + wait = wait_for_new_voltage(vdd, i2caddress); + if (wait < 0) + return -1; + debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); + + vdd_last = wait_for_voltage_stable(i2caddress); + if (vdd_last < 0) + return -1; + debug("VID: Current voltage is %d mV\n", vdd_last); + return vdd_last; +} +#endif + +static int set_voltage(int i2caddress, int vdd) +{ + int vdd_last = -1; + +#ifdef CONFIG_VOL_MONITOR_IR36021_SET + vdd_last = set_voltage_to_IR(i2caddress, vdd); +#else + #error Specific voltage monitor must be defined +#endif + return vdd_last; +} + +int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 fusesr; + u8 vid; + int vdd_target, vdd_current, vdd_last; + int ret, i2caddress; + unsigned long vdd_string_override; + char *vdd_string; + static const uint16_t vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + struct vdd_drive { + u8 vid; + unsigned voltage; + }; + + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID: I2C failed to switch channel\n"); + ret = -1; + goto exit; + } + ret = find_ir_chip_on_i2c(); + if (ret < 0) { + printf("VID: Could not find voltage regulator on I2C.\n"); + ret = -1; + goto exit; + } else { + i2caddress = ret; + debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); + } + + /* get the voltage ID from fuse status register */ + fusesr = in_be32(&gur->dcfg_fusesr); + /* + * VID is used according to the table below + * --------------------------------------- + * | DA_V | + * |-------------------------------------| + * | 5b00000 | 5b00001-5b11110 | 5b11111 | + * ---------------+---------+-----------------+---------| + * | D | 5b00000 | NO VID | VID = DA_V | NO VID | + * | A |----------+---------+-----------------+---------| + * | _ | 5b00001 |VID = | VID = |VID = | + * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| + * | _ | 5b11110 | | | | + * | A |----------+---------+-----------------+---------| + * | L | 5b11111 | No VID | VID = DA_V | NO VID | + * | T | | | | | + * ------------------------------------------------------ + */ + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; + } + vdd_target = vdd[vid]; + + /* check override variable for overriding VDD */ + vdd_string = getenv(CONFIG_VID_FLS_ENV); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + if (vdd_target == 0) { + debug("VID: VID not used\n"); + ret = 0; + goto exit; + } else { + /* divide and round up by 10 to get a value in mV */ + vdd_target = DIV_ROUND_UP(vdd_target, 10); + debug("VID: vid = %d mV\n", vdd_target); + } + + /* + * Read voltage monitor to check real voltage. + */ + vdd_last = read_voltage(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjustment\n"); + ret = -1; + goto exit; + } + vdd_current = vdd_last; + debug("VID: Core voltage is currently at %d mV\n", vdd_last); + /* + * Adjust voltage to at or one step above target. + * As measurements are less precise than setting the values + * we may run through dummy steps that cancel each other + * when stepping up and then down. + */ + while (vdd_last > 0 && + vdd_last < vdd_target) { + vdd_current += IR_VDD_STEP_UP; + vdd_last = set_voltage(i2caddress, vdd_current); + } + while (vdd_last > 0 && + vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { + vdd_current -= IR_VDD_STEP_DOWN; + vdd_last = set_voltage(i2caddress, vdd_current); + } + + if (vdd_last > 0) + printf("VID: Core voltage after adjustment is at %d mV\n", + vdd_last); + else + ret = -1; +exit: + if (re_enable) + enable_interrupts(); + return ret; +} + +static int print_vdd(void) +{ + int vdd_last, ret, i2caddress; + + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID : I2c failed to switch channel\n"); + return -1; + } + ret = find_ir_chip_on_i2c(); + if (ret < 0) { + printf("VID: Could not find voltage regulator on I2C.\n"); + return -1; + } else { + i2caddress = ret; + debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); + } + + /* + * Read voltage monitor to check real voltage. + */ + vdd_last = read_voltage(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjustment\n"); + return -1; + } + printf("VID: Core voltage is at %d mV\n", vdd_last); + + return 0; +} + +static int do_vdd_override(cmd_tbl_t *cmdtp, + int flag, int argc, + char * const argv[]) +{ + ulong override; + + if (argc < 2) + return CMD_RET_USAGE; + + if (!strict_strtoul(argv[1], 10, &override)) + adjust_vdd(override); /* the value is checked by callee */ + else + return CMD_RET_USAGE; + return 0; +} + +static int do_vdd_read(cmd_tbl_t *cmdtp, + int flag, int argc, + char * const argv[]) +{ + if (argc < 1) + return CMD_RET_USAGE; + print_vdd(); + + return 0; +} + +U_BOOT_CMD( + vdd_override, 2, 0, do_vdd_override, + "override VDD", + " - override with the voltage specified in mV, eg. 1050" +); + +U_BOOT_CMD( + vdd_read, 1, 0, do_vdd_read, + "read VDD", + " - Read the voltage specified in mV" +) diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h new file mode 100644 index 0000000000..a9c7bb4790 --- /dev/null +++ b/board/freescale/common/vid.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VID_H_ +#define __VID_H_ + +#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A +#define IR36021_LOOP1_VOUT_OFFSET 0x9A +#define IR36021_MFR_ID_OFFSET 0x92 +#define IR36021_MFR_ID 0x43 + +/* step the IR regulator in 5mV increments */ +#define IR_VDD_STEP_DOWN 5 +#define IR_VDD_STEP_UP 5 +int adjust_vdd(ulong vdd_override); + +#endif /* __VID_H_ */ diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c index 8a3dc33b66..dd9c37ebe8 100644 --- a/board/freescale/common/vsc3316_3308.c +++ b/board/freescale/common/vsc3316_3308.c @@ -13,7 +13,12 @@ #define INPUT_STATE_REG 0x13 #define GLOBAL_INPUT_ISE1 0x51 #define GLOBAL_INPUT_ISE2 0x52 +#define GLOBAL_INPUT_GAIN 0x53 #define GLOBAL_INPUT_LOS 0x55 +#define GLOBAL_OUTPUT_PE1 0x56 +#define GLOBAL_OUTPUT_PE2 0x57 +#define GLOBAL_OUTPUT_LEVEL 0x58 +#define GLOBAL_OUTPUT_TERMINATION 0x5A #define GLOBAL_CORE_CNTRL 0x5D #define OUTPUT_MODE_PAGE 0x23 #define CORE_CONTROL_PAGE 0x25 @@ -31,7 +36,7 @@ int vsc_if_enable(unsigned int vsc_addr) return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); } -int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], +int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], unsigned int num_con) { unsigned int i; @@ -92,6 +97,109 @@ int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], return 0; } +#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR +int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con) +{ + unsigned int i; + u8 rev_id = 0; + int ret; + + debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n", + vsc_addr); + + ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Configure Global Input ISE */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0); + i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0); + + /* Configure Tx/Rx Global Output PE1 */ + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0); + + /* Configure Tx/Rx Global Output PE2 */ + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0); + + /* Configure Tx/Rx Global Input GAIN */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F); + + /* Setting Global Input LOS threshold value */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0); + + /* Setting Global output termination */ + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0); + + /* Configure Tx/Rx Global Output level */ + if (vsc_addr == VSC3308_TX_ADDRESS) + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4); + else + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning off all the required input of the switch */ + for (i = 0; i < num_con; i++) + i2c_reg_write(vsc_addr, con_arr[i][0], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + i2c_reg_write(vsc_addr, 2, 0); + i2c_reg_write(vsc_addr, 3, 0); + } else { + i2c_reg_write(vsc_addr, 0, 0); + i2c_reg_write(vsc_addr, 1, 0); + } + + /* config output mode - page 0x23 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn off the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + i2c_reg_write(vsc_addr, 0, 0); + i2c_reg_write(vsc_addr, 1, 0); + } else { + i2c_reg_write(vsc_addr, 3, 0); + i2c_reg_write(vsc_addr, 4, 0); + } + + /* configure global core control register, Turn on Global core power */ + i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); + + vsc_wp_config(vsc_addr); + + return 0; +} +#endif + int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], unsigned int num_con) { diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h index 4003fcdb23..d722ea39d6 100644 --- a/board/freescale/common/vsc3316_3308.h +++ b/board/freescale/common/vsc3316_3308.h @@ -12,8 +12,12 @@ #include int vsc_if_enable(unsigned int vsc_addr); -int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], +int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], unsigned int num_con); +#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR +int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con); +#endif int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], unsigned int num_con); void vsc_wp_config(unsigned int vsc_addr); diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c new file mode 100644 index 0000000000..be5953ad2d --- /dev/null +++ b/board/freescale/common/zm7300.c @@ -0,0 +1,235 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power-One ZM7300 DPM */ +#include "zm7300.h" + +#define DPM_WP 0x96 +#define WRP_OPCODE 0x01 +#define WRM_OPCODE 0x02 +#define RRP_OPCODE 0x11 + +#define DPM_SUCCESS 0x01 +#define DPM_EXEC_FAIL 0x00 + +static const uint16_t hex_to_1_10mv[] = { + 5000, + 5125, + 5250, + 5375, + 5500, + 5625, + 5750, + 5875, + 6000, + 6125, + 6250, + 6375, + 6500, + 6625, + 6750, + 6875, + 7000, + 7125, + 7250, + 7375, + 7500, + 7625, + 7750, + 7875, + 8000, + 8125, + 8250, + 8375, + 8500, + 8625, + 8750, + 8875, + 9000, + 9125, + 9250, + 9375, + 9500, /* 0.95mV */ + 9625, + 9750, + 9875, + 10000, /* 1.0V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 11125, + 11250, + 11375, + 11500, + 11625, + 11750, + 11875, + 12000, + 12125, + 12250, + 12375, + 0, /* reserved */ +}; + + +/* Read Data d from Register r of POL p */ +u8 dpm_rrp(uchar r) +{ + u8 ret[5]; + + ret[0] = RRP_OPCODE; + /* POL is 0 */ + ret[1] = 0; + ret[2] = r; + i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2); + if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */ + debug("RRP_OPCODE returned success data is %x\n", ret[0]); + return ret[0]; + } else { + return -1; + } +} + +/* Write Data d into DPM register r (RAM) */ +int dpm_wrm(u8 r, u8 d) +{ + u8 ret[5]; + + ret[0] = WRM_OPCODE; + ret[1] = r; + ret[2] = d; + i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1); + if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ + debug("WRM_OPCODE returned success data is %x\n", ret[0]); + return ret[0]; + } else { + return -1; + } +} + +/* Write Data d into Register r of POL(s) a */ +int dpm_wrp(u8 r, u8 d) +{ + u8 ret[7]; + + ret[0] = WRP_OPCODE; + /* only POL0 is present */ + ret[1] = 0x01; + ret[2] = 0x00; + ret[3] = 0x00; + ret[4] = 0x00; + ret[5] = r; + ret[6] = d; + i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1); + if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ + debug("WRP_OPCODE returned success data is %x\n", ret[0]); + return 0; + } else { + return -1; + } +} + +/* Uses the DPM command RRP */ +u8 zm_read(uchar reg) +{ + u8 d; + d = dpm_rrp(reg); + return d; +} + +/* ZM_write -- + Steps: + a. Write data to the register + b. Read data from register and compare to written value + c. Return return_code & voltage_read +*/ +u8 zm_write(u8 reg, u8 data) +{ + u8 d; + + /* write data to register */ + dpm_wrp(reg, data); + + /* read register and compare to written value */ + d = dpm_rrp(reg); + if (d != data) { + printf("zm_write : Comparison register data failed\n"); + return -1; + } + + return d; +} + +/* zm_write_out_voltage + * voltage in 1/10 mV + */ +int zm_write_voltage(int voltage) +{ + u8 reg = 0x7, vid; + uint16_t voltage_read; + u8 ret; + + vid = (voltage - 5000) / ZM_STEP; + + ret = zm_write(reg, vid); + if (ret != -1) { + voltage_read = hex_to_1_10mv[ret]; + debug("voltage set to %dmV\n", voltage_read/10); + return voltage_read; + } + return -1; +} + +/* zm_read_out_voltage + * voltage in 1/10 mV + */ +int zm_read_voltage(void) +{ + u8 reg = 0x7; + u8 ret; + int voltage; + + ret = zm_read(reg); + if (ret != -1) { + voltage = hex_to_1_10mv[ret]; + debug("Voltage read is %dmV\n", voltage/10); + return voltage; + } else { + return -1; + } +} + +int zm_disable_wp() +{ + u8 new_wp_value; + + /* Disable using Write-Protect register 0x96 */ + new_wp_value = 0x8; + if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) { + printf("Disable Write-Protect register failed\n"); + return -1; + } + return 0; +} + +int zm_enable_wp() +{ + u8 orig_wp_value; + orig_wp_value = 0x0; + + /* Enable using Write-Protect register 0x96 */ + if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) { + printf("Enable Write-Protect register failed\n"); + return -1; + } + return 0; +} + diff --git a/board/freescale/common/zm7300.h b/board/freescale/common/zm7300.h new file mode 100644 index 0000000000..6b4d035970 --- /dev/null +++ b/board/freescale/common/zm7300.h @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ZM7300_H_ +#define __ZM7300_H 1_ + +#include +#include +#include +#include + +#define ZM_STEP 125 +int zm7300_set_voltage(int voltage_1_10mv); +int zm_write_voltage(int voltage); +int zm_read_voltage(void); +int zm_disable_wp(void); +int zm_enable_wp(void); + +#endif /* __ZM7300_H_ */ diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig new file mode 100644 index 0000000000..433f539d99 --- /dev/null +++ b/board/freescale/corenet_ds/Kconfig @@ -0,0 +1,51 @@ +if TARGET_P3041DS + +config SYS_BOARD + default "corenet_ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P3041DS" + +endif + +if TARGET_P4080DS + +config SYS_BOARD + default "corenet_ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P4080DS" + +endif + +if TARGET_P5020DS + +config SYS_BOARD + default "corenet_ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P5020DS" + +endif + +if TARGET_P5040DS + +config SYS_BOARD + default "corenet_ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P5040DS" + +endif diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS new file mode 100644 index 0000000000..745847cdba --- /dev/null +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -0,0 +1,30 @@ +CORENET_DS BOARD +#M: - +S: Maintained +F: board/freescale/corenet_ds/ +F: include/configs/P3041DS.h +F: configs/P3041DS_defconfig +F: configs/P3041DS_NAND_defconfig +F: configs/P3041DS_SDCARD_defconfig +F: configs/P3041DS_SECURE_BOOT_defconfig +F: configs/P3041DS_SPIFLASH_defconfig +F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig +F: include/configs/P4080DS.h +F: configs/P4080DS_defconfig +F: configs/P4080DS_SDCARD_defconfig +F: configs/P4080DS_SECURE_BOOT_defconfig +F: configs/P4080DS_SPIFLASH_defconfig +F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig +F: include/configs/P5020DS.h +F: configs/P5020DS_defconfig +F: configs/P5020DS_NAND_defconfig +F: configs/P5020DS_SDCARD_defconfig +F: configs/P5020DS_SECURE_BOOT_defconfig +F: configs/P5020DS_SPIFLASH_defconfig +F: configs/P5020DS_SRIO_PCIE_BOOT_defconfig +F: include/configs/P5040DS.h +F: configs/P5040DS_defconfig +F: configs/P5040DS_NAND_defconfig +F: configs/P5040DS_SDCARD_defconfig +F: configs/P5040DS_SPIFLASH_defconfig +F: configs/P5040DS_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 36813cbcec..9ade9472ea 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -6,33 +6,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-$(CONFIG_P3041DS) += eth_hydra.o -COBJS-$(CONFIG_P4080DS) += eth_p4080.o -COBJS-$(CONFIG_P5020DS) += eth_hydra.o -COBJS-$(CONFIG_P5040DS) += eth_superhydra.o -COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o -COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o -COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o -COBJS-$(CONFIG_P5040DS) += p5040ds_ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += corenet_ds.o +obj-y += ddr.o +obj-$(CONFIG_P3041DS) += eth_hydra.o +obj-$(CONFIG_P4080DS) += eth_p4080.o +obj-$(CONFIG_P5020DS) += eth_hydra.o +obj-$(CONFIG_P5040DS) += eth_superhydra.o +obj-$(CONFIG_P3041DS) += p3041ds_ddr.o +obj-$(CONFIG_P4080DS) += p4080ds_ddr.o +obj-$(CONFIG_P5020DS) += p5020ds_ddr.o +obj-$(CONFIG_P5040DS) += p5040ds_ddr.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index fffb0c817a..6f0fea1a35 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -27,8 +27,10 @@ int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \ + defined(CONFIG_P5040DS) unsigned int i; +#endif static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); @@ -47,19 +49,6 @@ int checkboard (void) else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); - /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the @@ -112,7 +101,7 @@ int board_early_init_f(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -123,8 +112,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ @@ -138,20 +133,6 @@ int board_early_init_r(void) return 0; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch(clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - default: - return "150"; - } -} - #define NUM_SRDS_BANKS 3 int misc_init_r(void) @@ -209,7 +190,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -232,4 +213,6 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index da284cde95..e7e893a1ae 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -56,14 +56,14 @@ phys_size_t fixed_sdram(void) ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); #if (CONFIG_NUM_DDR_CONTROLLERS == 2) memcpy(&ddr_cfg_regs, fixed_ddr_parm_1[i].ddr_settings, sizeof(ddr_cfg_regs)); ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); #endif /* @@ -114,7 +114,7 @@ struct board_specific_parameters { u32 wrlvl_start; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -217,7 +217,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -234,7 +234,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index a594efcada..396103f990 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -62,7 +62,7 @@ #ifdef CONFIG_FMAN_ENET -#define BRDCFG1_EMI1_SEL_MASK 0x70 +#define BRDCFG1_EMI1_SEL_MASK 0x78 #define BRDCFG1_EMI1_SEL_SLOT1 0x10 #define BRDCFG1_EMI1_SEL_SLOT2 0x20 #define BRDCFG1_EMI1_SEL_SLOT5 0x30 @@ -76,6 +76,8 @@ #define BRDCFG2_REG_GPIO_SEL 0x20 +#define PHY_BASE_ADDR 0x00 + /* * BRDCFG1 mask and value for each MAC * @@ -200,6 +202,8 @@ static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) if (!path) path = alias; + do_fixup_by_path(fdt, path, "reg", + &mux, sizeof(mux), 1); do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", &mux, sizeof(mux), 1); } @@ -248,11 +252,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, return; } - if (mux == BRDCFG1_EMI1_SEL_RGMII) { + if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) { /* RGMII */ /* The RGMII PHY is identified by the MAC connected to it */ sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); fdt_set_phy_handle(fdt, compat, addr, phy); + return; } /* If it's not RGMII or XGMII, it must be SGMII */ @@ -365,6 +370,7 @@ int board_eth_init(bd_t *bis) struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; + struct mii_dev *bus; printf("Initializing Fman\n"); @@ -470,6 +476,9 @@ int board_eth_init(bd_t *bis) } } + bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"); + set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR); + /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 597d0cbf2e..5cbec7f5f2 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include @@ -37,6 +37,9 @@ #define EMI1_MASK 0xc0000000 #define EMI2_MASK 0x30000000 +#define PHY_BASE_ADDR 0x00 +#define PHY_BASE_ADDR_SLOT5 0x10 + static int mdio_mux[NUM_FM_PORTS]; static char *mdio_names[16] = { @@ -290,6 +293,7 @@ int board_eth_init(bd_t *bis) int i; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; + struct mii_dev *bus; /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) @@ -370,6 +374,9 @@ int board_eth_init(bd_t *bis) break; } } + bus = mii_dev_for_muxval(EMI1_SLOT5); + set_sgmii_phy(bus, FM1_DTSEC1, + CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5); for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { int idx = i - FM1_10GEC1, lane, slot; @@ -435,6 +442,11 @@ int board_eth_init(bd_t *bis) } } + bus = mii_dev_for_muxval(EMI1_SLOT3); + set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); + bus = mii_dev_for_muxval(EMI1_SLOT4); + set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { int idx = i - FM2_10GEC1, lane, slot; switch (fm_info_get_enet_if(i)) { diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index fa07ff333e..ad1bffd74b 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -77,6 +77,12 @@ #define BRDCFG2_REG_GPIO_SEL 0x20 +/* SGMII */ +#define PHY_BASE_ADDR 0x00 +#define REGNUM 0x00 +#define PORT_NUM_FM1 0x04 +#define PORT_NUM_FM2 0x02 + /* * BRDCFG1 mask and value for each MAC * @@ -415,6 +421,9 @@ int board_eth_init(bd_t *bis) struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; + struct mii_dev *bus; + int qsgmii; + int phy_real_addr; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int srds_prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; @@ -449,6 +458,8 @@ int board_eth_init(bd_t *bis) "SUPER_HYDRA_FM1_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM2_SGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_FM3_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, "SUPER_HYDRA_FM1_TGEC_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, @@ -573,6 +584,42 @@ int board_eth_init(bd_t *bis) } } + bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"); + qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); + + if (qsgmii) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) { + if (fm_info_get_enet_if(i) == + PHY_INTERFACE_MODE_SGMII) { + phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1; + fm_info_set_phy_address(i, phy_real_addr); + } + } + switch (srds_prtcl) { + case 0x00: + case 0x03: + case 0x04: + case 0x06: + case 0x11: + case 0x2a: + case 0x34: + case 0x36: + fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2); + fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3); + break; + case 0x01: + case 0x02: + case 0x05: + case 0x07: + case 0x35: + fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0); + fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); + break; + default: + break; + } + } + /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the @@ -638,10 +685,22 @@ int board_eth_init(bd_t *bis) break; }; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO")); + if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { + super_hydra_mdio_set_mux( + "SUPER_HYDRA_FM3_SGMII_MDIO", + mdio_mux[i].mask, + mdio_mux[i].val); + fm_info_set_mdio(i, miiphy_get_dev_by_name( + "SUPER_HYDRA_FM3_SGMII_MDIO")); + } else { + super_hydra_mdio_set_mux( + "SUPER_HYDRA_FM2_SGMII_MDIO", + mdio_mux[i].mask, + mdio_mux[i].val); + fm_info_set_mdio(i, miiphy_get_dev_by_name( + "SUPER_HYDRA_FM2_SGMII_MDIO")); + } + break; case PHY_INTERFACE_MODE_RGMII: /* @@ -672,6 +731,11 @@ int board_eth_init(bd_t *bis) } } + bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"); + set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR); + bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO"); + set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR); + /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c index 5a8ed94b04..4dead9c045 100644 --- a/board/freescale/corenet_ds/p3041ds_ddr.c +++ b/board/freescale/corenet_ds/p3041ds_ddr.c @@ -7,7 +7,7 @@ */ #include -#include +#include fixed_ddr_parm_t fixed_ddr_parm_0[] = { {0, 0, NULL} diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index 844e1d736a..d572a5fbed 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -7,7 +7,7 @@ */ #include -#include +#include #define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 #define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c index e65de364d7..9aaf6db997 100644 --- a/board/freescale/corenet_ds/p5020ds_ddr.c +++ b/board/freescale/corenet_ds/p5020ds_ddr.c @@ -7,7 +7,7 @@ */ #include -#include +#include fixed_ddr_parm_t fixed_ddr_parm_0[] = { {0, 0, NULL} diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c index e65de364d7..9aaf6db997 100644 --- a/board/freescale/corenet_ds/p5040ds_ddr.c +++ b/board/freescale/corenet_ds/p5040ds_ddr.c @@ -7,7 +7,7 @@ */ #include -#include +#include fixed_ddr_parm_t fixed_ddr_parm_0[] = { {0, 0, NULL} diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig new file mode 100644 index 0000000000..119b955041 --- /dev/null +++ b/board/freescale/ls1021aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1021AQDS + +config SYS_BOARD + default "ls1021aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021aqds" + +endif diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS new file mode 100644 index 0000000000..661526b993 --- /dev/null +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -0,0 +1,12 @@ +LS1021AQDS BOARD +M: Alison Wang +S: Maintained +F: board/freescale/ls1021aqds/ +F: include/configs/ls1021aqds.h +F: configs/ls1021aqds_nor_defconfig +F: configs/ls1021aqds_ddr4_nor_defconfig +F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig +F: configs/ls1021aqds_nor_lpuart_defconfig +F: configs/ls1021aqds_sdcard_defconfig +F: configs/ls1021aqds_qspi_defconfig +F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile new file mode 100644 index 0000000000..ab0234412c --- /dev/null +++ b/board/freescale/ls1021aqds/Makefile @@ -0,0 +1,10 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o +obj-y += eth.o +obj-$(CONFIG_FSL_DCU_FB) += dcu.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README new file mode 100644 index 0000000000..c561776621 --- /dev/null +++ b/board/freescale/ls1021aqds/README @@ -0,0 +1,112 @@ +Overview +-------- +The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +------------------ +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine + - IPSec forwarding at up to 1Gbps + - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported + - Public key hardware accelerator + - True Random Number Generator (NIST Certified) + - Advanced Encryption Standard Accelerators (AESA) + - Data Encryption Standard Accelerators + - QUICC Engine ULite block + - Two universal communication controllers (TDM and HDLC) supporting 64 + multichannels, each running at 64 Kbps + - Support for 256 channels of HDLC + - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported + +LS1021AQDS board Overview +------------------------- + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM, of single-, dual- types. + - IFC/Local Bus + - NAND flash: 512M 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Three on-board RGMII 10/100/1G ethernet ports. + - FPGA + - Clocks + - System and DDR clock (SYSCLK, DDRCLK) + - SERDES clocks + - Power Supplies + - SDHC + - SDHC/SDXC connector + - Other IO + - Two Serial ports + - Three I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c new file mode 100644 index 0000000000..90f5bc0445 --- /dev/null +++ b/board/freescale/ls1021aqds/dcu.c @@ -0,0 +1,92 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "div64.h" +#include "../common/diu_ch7301.h" +#include "ls1021aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +unsigned int dcu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long long div; + + div = (unsigned long long)(gd->bus_clk / 1000); + div *= (unsigned long long)pixclock; + do_div(div, 1000000000); + + return div; +} + +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) +{ + const char *name; + unsigned int pixel_format; + int ret; + u8 ch; + + /* Mux I2C3+I2C4 as HSYNC+VSYNC */ + ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, + 1, &ch, 1); + if (ret) { + printf("Error: failed to read I2C @%02x\n", + CONFIG_SYS_I2C_QIXIS_ADDR); + return ret; + } + ch &= 0x1F; + ch |= 0xA0; + ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, + 1, &ch, 1); + if (ret) { + printf("Error: failed to write I2C @%02x\n", + CONFIG_SYS_I2C_QIXIS_ADDR); + return ret; + } + + if (strncmp(port, "hdmi", 4) == 0) { + unsigned long pixval; + + name = "HDMI"; + + pixval = 1000000000 / dcu_fb_videomode->pixclock; + pixval *= 1000; + + i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); + select_i2c_ch_pca9547(I2C_MUX_CH_CH7301); + diu_set_dvi_encoder(pixval); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + } else { + return 0; + } + + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; + fsl_dcu_init(xres, yres, pixel_format); + + return 0; +} diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c new file mode 100644 index 0000000000..6435bf9ad1 --- /dev/null +++ b/board/freescale/ls1021aqds/ddr.c @@ -0,0 +1,186 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->cswl_override = DDR_CSWL_CS0; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1071, + .caslat_x = 0xfe << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + static const char dimm_model[] = "Fixed DDR on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + udelay(1); +} +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) + puts("Initializing DDR....using SPD\n"); + dram_size = fsl_ddr_sdram(); +#else + dram_size = fsl_ddr_sdram_size(); +#endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + + return dram_size; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h new file mode 100644 index 0000000000..f819c99dba --- /dev/null +++ b/board/freescale/ls1021aqds/ddr.h @@ -0,0 +1,59 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,}, + {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c new file mode 100644 index 0000000000..be351befec --- /dev/null +++ b/board/freescale/ls1021aqds/eth.c @@ -0,0 +1,186 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file handles the board muxing between the RGMII/SGMII PHYs on + * Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb + * ports. The SGMII PHYs are provided by the standard Freescale four-port + * SGMII riser card. + * + * Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control + * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends + * on which port is used. The value for SGMII depends on which slot the riser + * is inserted in. + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/sgmii_riser.h" +#include "../common/qixis.h" + +#define EMI1_MASK 0x1f +#define EMI1_RGMII0 1 +#define EMI1_RGMII1 2 +#define EMI1_RGMII2 3 +#define EMI1_SGMII1 0x1c +#define EMI1_SGMII2 0x1d + +struct ls1021a_mdio { + struct mii_dev *realbus; +}; + +static void ls1021a_mux_mdio(int addr) +{ + u8 brdcfg4; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= EMI1_MASK; + + switch (addr) { + case EMI1_RGMII0: + brdcfg4 |= 0; + break; + case EMI1_RGMII1: + brdcfg4 |= 0x20; + break; + case EMI1_RGMII2: + brdcfg4 |= 0x40; + break; + case EMI1_SGMII1: + brdcfg4 |= 0x60; + break; + case EMI1_SGMII2: + brdcfg4 |= 0x80; + break; + default: + brdcfg4 |= 0xa0; + break; + } + + QIXIS_WRITE(brdcfg[4], brdcfg4); +} + +static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1021a_mdio *priv = bus->priv; + + ls1021a_mux_mdio(addr); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1021a_mdio *priv = bus->priv; + + ls1021a_mux_mdio(addr); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int ls1021a_mdio_reset(struct mii_dev *bus) +{ + struct ls1021a_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1021a_mdio_init(char *realbusname, char *fakebusname) +{ + struct ls1021a_mdio *lsmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate LS102xA MDIO bus\n"); + return -1; + } + + lsmdio = malloc(sizeof(*lsmdio)); + if (!lsmdio) { + printf("Failed to allocate LS102xA private data\n"); + free(bus); + return -1; + } + + bus->read = ls1021a_mdio_read; + bus->write = ls1021a_mdio_write; + bus->reset = ls1021a_mdio_reset; + sprintf(bus->name, fakebusname); + + lsmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!lsmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(lsmdio); + return -1; + } + + bus->priv = lsmdio; + + return mdio_register(bus); +} + +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[3]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode\n"); + tsec_info[num].flags |= TSEC_SGMII; + tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; + } else { + tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + } + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode\n"); + tsec_info[num].flags |= TSEC_SGMII; + tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; + } else { + tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_init(tsec_info, num); +#endif + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + /* Register the virtual MDIO front-ends */ + ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO"); + ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO"); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c new file mode 100644 index 0000000000..20eade4651 --- /dev/null +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -0,0 +1,601 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/sleep.h" +#include "../common/qixis.h" +#include "ls1021aqds_qixis.h" +#ifdef CONFIG_U_QE +#include "../../../drivers/qe/qe.h" +#endif + +#define PIN_MUX_SEL_CAN 0x03 +#define PIN_MUX_SEL_IIC2 0xa0 +#define PIN_MUX_SEL_RGMII 0x00 +#define PIN_MUX_SEL_SAI 0x0c +#define PIN_MUX_SEL_SDHC 0x00 + +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) +#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_CAN, + MUX_TYPE_IIC2, + MUX_TYPE_RGMII, + MUX_TYPE_SAI, + MUX_TYPE_SDHC, + MUX_TYPE_SD_PCI4, + MUX_TYPE_SD_PC_SA_SG_SG, + MUX_TYPE_SD_PC_SA_PC_SG, + MUX_TYPE_SD_PC_SG_SG, +}; + +enum { + GE0_CLK125, + GE2_CLK125, + GE1_CLK125, +}; + +int checkboard(void) +{ +#ifndef CONFIG_QSPI_BOOT + char buf[64]; +#endif +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) + u8 sw; +#endif + + puts("Board: LS1021AQDS\n"); + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#elif CONFIG_QSPI_BOOT + puts("QSPI\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFCCard\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + +#ifndef CONFIG_QSPI_BOOT + printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); +#endif + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int dram_init(void) +{ + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + gd->ram_size = initdram(0); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {CONFIG_SYS_FSL_ESDHC_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + +#ifdef CONFIG_TSEC_ENET + out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); +#endif + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + +#ifdef CONFIG_NAND_BOOT + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 porsr1, pinctl; + + /* + * There is LS1 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | + DCFG_CCSR_PORSR1_RCW_SRC_I2C); + out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + pinctl); +#endif + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + get_clocks(); + +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init_all(); +#endif + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + +void config_etseccm_source(int etsec_gtx_125_mux) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + + switch (etsec_gtx_125_mux) { + case GE0_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); + debug("etseccm set to GE0_CLK125\n"); + break; + + case GE2_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + debug("etseccm set to GE2_CLK125\n"); + break; + + case GE1_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); + debug("etseccm set to GE1_CLK125\n"); + break; + + default: + printf("Error! trying to set etseccm to invalid value\n"); + break; + } +} + +int config_board_mux(int ctrl_type) +{ + u8 reg12, reg14; + + reg12 = QIXIS_READ(brdcfg[12]); + reg14 = QIXIS_READ(brdcfg[14]); + + switch (ctrl_type) { + case MUX_TYPE_CAN: + config_etseccm_source(GE2_CLK125); + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); + break; + case MUX_TYPE_IIC2: + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); + break; + case MUX_TYPE_RGMII: + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); + break; + case MUX_TYPE_SAI: + config_etseccm_source(GE2_CLK125); + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); + break; + case MUX_TYPE_SDHC: + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); + break; + case MUX_TYPE_SD_PCI4: + reg12 = 0x38; + break; + case MUX_TYPE_SD_PC_SA_SG_SG: + reg12 = 0x01; + break; + case MUX_TYPE_SD_PC_SA_PC_SG: + reg12 = 0x01; + break; + case MUX_TYPE_SD_PC_SG_SG: + reg12 = 0x21; + break; + default: + printf("Wrong mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[12], reg12); + QIXIS_WRITE(brdcfg[14], reg14); + + return 0; +} + +int config_serdes_mux(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 cfg; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (cfg) { + case 0x0: + config_board_mux(MUX_TYPE_SD_PCI4); + break; + case 0x30: + config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); + break; + case 0x60: + config_board_mux(MUX_TYPE_SD_PC_SG_SG); + break; + case 0x70: + config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); + break; + default: + printf("SRDS1 prtcl:0x%x\n", cfg); + break; + } + + return 0; +} + +int misc_init_r(void) +{ + int conflict_flag; + + /* some signals can not enable simultaneous*/ + conflict_flag = 0; + if (hwconfig("sdhc")) + conflict_flag++; + if (hwconfig("iic2")) + conflict_flag++; + if (conflict_flag > 1) { + printf("WARNING: pin conflict !\n"); + return 0; + } + + conflict_flag = 0; + if (hwconfig("rgmii")) + conflict_flag++; + if (hwconfig("can")) + conflict_flag++; + if (hwconfig("sai")) + conflict_flag++; + if (conflict_flag > 1) { + printf("WARNING: pin conflict !\n"); + return 0; + } + + if (hwconfig("can")) + config_board_mux(MUX_TYPE_CAN); + else if (hwconfig("rgmii")) + config_board_mux(MUX_TYPE_RGMII); + else if (hwconfig("sai")) + config_board_mux(MUX_TYPE_SAI); + + if (hwconfig("iic2")) + config_board_mux(MUX_TYPE_IIC2); + else if (hwconfig("sdhc")) + config_board_mux(MUX_TYPE_SDHC); + +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif + return 0; +} + +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; +#endif + +struct smmu_stream_id dev_stream_id[] = { + { 0x100, 0x01, "ETSEC MAC1" }, + { 0x104, 0x02, "ETSEC MAC2" }, + { 0x108, 0x03, "ETSEC MAC3" }, + { 0x10c, 0x04, "PEX1" }, + { 0x110, 0x05, "PEX2" }, + { 0x114, 0x06, "qDMA" }, + { 0x118, 0x07, "SATA" }, + { 0x11c, 0x08, "USB3" }, + { 0x120, 0x09, "QE" }, + { 0x124, 0x0a, "eSDHC" }, + { 0x128, 0x0b, "eMA" }, + { 0x14c, 0x0c, "2D-ACE" }, + { 0x150, 0x0d, "USB2" }, + { 0x18c, 0x0e, "DEBUG" }, +}; + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to + * enable barrier transaction */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); + config_serdes_mux(); +#endif + + ls102xa_config_smmu_stream_id(dev_stream_id, + ARRAY_SIZE(dev_stream_id)); + +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + + return 0; +} + +#if defined(CONFIG_DEEP_SLEEP) +void board_sleep_prepare(void) +{ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to + * enable barrier transaction */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif + + return 0; +} + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h new file mode 100644 index 0000000000..8e482eb0b0 --- /dev/null +++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h @@ -0,0 +1,37 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1021AQDS_QIXIS_H__ +#define __LS1021AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1021AQDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define QIXIS_SRDS1CLK_100 0x0 + +#define QIXIS_DCU_BRDCFG5 0x55 + +#endif diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg new file mode 100644 index 0000000000..f1a1b63ab7 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_pbi.cfg @@ -0,0 +1,12 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg new file mode 100644 index 0000000000..222c71dcb6 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0608000a 00000000 00000000 00000000 +60000000 00407900 e0106a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000000..9d99bd862d --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000a 00000000 00000000 00000000 +60000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#60000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig new file mode 100644 index 0000000000..bc50b8d966 --- /dev/null +++ b/board/freescale/ls1021atwr/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1021ATWR + +config SYS_BOARD + default "ls1021atwr" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021atwr" + +endif diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS new file mode 100644 index 0000000000..e9f6f0a973 --- /dev/null +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -0,0 +1,10 @@ +LS1021ATWR BOARD +M: Alison Wang +S: Maintained +F: board/freescale/ls1021atwr/ +F: include/configs/ls1021atwr.h +F: configs/ls1021atwr_nor_defconfig +F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig +F: configs/ls1021atwr_nor_lpuart_defconfig +F: configs/ls1021atwr_sdcard_defconfig +F: configs/ls1021atwr_qspi_defconfig diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile new file mode 100644 index 0000000000..01296c04b2 --- /dev/null +++ b/board/freescale/ls1021atwr/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021atwr.o +obj-$(CONFIG_FSL_DCU_FB) += dcu.o diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README new file mode 100644 index 0000000000..d2821cbb6b --- /dev/null +++ b/board/freescale/ls1021atwr/README @@ -0,0 +1,109 @@ +Overview +-------- +The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +------------------ +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine + - IPSec forwarding at up to 1Gbps + - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported + - Public key hardware accelerator + - True Random Number Generator (NIST Certified) + - Advanced Encryption Standard Accelerators (AESA) + - Data Encryption Standard Accelerators + - QUICC Engine ULite block + - Two universal communication controllers (TDM and HDLC) supporting 64 + multichannels, each running at 64 Kbps + - Support for 256 channels of HDLC + - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported + +LS1021ATWR board Overview +------------------------- + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP SDRAM. + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Three on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, DDRCLK) + - SERDES clocks + - Power Supplies + - SDHC + - SDHC/SDXC connector + - Other IO + - One Serial port + - Three I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c new file mode 100644 index 0000000000..8fe4ccbeb4 --- /dev/null +++ b/board/freescale/ls1021atwr/dcu.c @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "div64.h" +#include "../common/dcu_sii9022a.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int dcu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long long div; + + div = (unsigned long long)(gd->bus_clk / 1000); + div *= (unsigned long long)pixclock; + do_div(div, 1000000000); + + return div; +} + +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) +{ + const char *name; + unsigned int pixel_format; + + if (strncmp(port, "twr_lcd", 4) == 0) { + name = "TWR_LCD_RGB card"; + } else { + name = "HDMI"; + dcu_set_dvi_encoder(dcu_fb_videomode); + } + + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; + fsl_dcu_init(xres, yres, pixel_format); + + return 0; +} diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c new file mode 100644 index 0000000000..bc8b00686c --- /dev/null +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -0,0 +1,666 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_U_QE +#include "../../../drivers/qe/qe.h" +#endif + + +DECLARE_GLOBAL_DATA_PTR; + +#define VERSION_MASK 0x00FF +#define BANK_MASK 0x0001 +#define CONFIG_RESET 0x1 +#define INIT_RESET 0x1 + +#define CPLD_SET_MUX_SERDES 0x20 +#define CPLD_SET_BOOT_BANK 0x40 + +#define BOOT_FROM_UPPER_BANK 0x0 +#define BOOT_FROM_LOWER_BANK 0x1 + +#define LANEB_SATA (0x01) +#define LANEB_SGMII1 (0x02) +#define LANEC_SGMII1 (0x04) +#define LANEC_PCIEX1 (0x08) +#define LANED_PCIEX2 (0x10) +#define LANED_SGMII2 (0x20) + +#define MASK_LANE_B 0x1 +#define MASK_LANE_C 0x2 +#define MASK_LANE_D 0x4 +#define MASK_SGMII 0x8 + +#define KEEP_STATUS 0x0 +#define NEED_RESET 0x1 + +struct cpld_data { + u8 cpld_ver; /* cpld revision */ + u8 cpld_ver_sub; /* cpld sub revision */ + u8 pcba_ver; /* pcb revision number */ + u8 system_rst; /* reset system by cpld */ + u8 soft_mux_on; /* CPLD override physical switches Enable */ + u8 cfg_rcw_src1; /* Reset config word 1 */ + u8 cfg_rcw_src2; /* Reset config word 2 */ + u8 vbank; /* Flash bank selection Control */ + u8 gpio; /* GPIO for TWR-ELEV */ + u8 i2c3_ifc_mux; + u8 mux_spi2; + u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ + u8 qe_lcd_mux; /* QE and LCD Selection */ + u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ + u8 global_rst; /* reset with init CPLD reg to default */ + u8 rev1; /* Reserved */ + u8 rev2; /* Reserved */ +}; + +#ifndef CONFIG_QSPI_BOOT +static void convert_serdes_mux(int type, int need_reset); + +void cpld_show(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", + in_8(&cpld_data->cpld_ver) & VERSION_MASK, + in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, + in_8(&cpld_data->pcba_ver) & VERSION_MASK, + in_8(&cpld_data->vbank) & BANK_MASK); + +#ifdef CONFIG_DEBUG + printf("soft_mux_on =%x\n", + in_8(&cpld_data->soft_mux_on)); + printf("cfg_rcw_src1 =%x\n", + in_8(&cpld_data->cfg_rcw_src1)); + printf("cfg_rcw_src2 =%x\n", + in_8(&cpld_data->cfg_rcw_src2)); + printf("vbank =%x\n", + in_8(&cpld_data->vbank)); + printf("gpio =%x\n", + in_8(&cpld_data->gpio)); + printf("i2c3_ifc_mux =%x\n", + in_8(&cpld_data->i2c3_ifc_mux)); + printf("mux_spi2 =%x\n", + in_8(&cpld_data->mux_spi2)); + printf("can3_usb2_mux =%x\n", + in_8(&cpld_data->can3_usb2_mux)); + printf("qe_lcd_mux =%x\n", + in_8(&cpld_data->qe_lcd_mux)); + printf("serdes_mux =%x\n", + in_8(&cpld_data->serdes_mux)); +#endif +} +#endif + +int checkboard(void) +{ + puts("Board: LS1021ATWR\n"); +#ifndef CONFIG_QSPI_BOOT + cpld_show(); +#endif + + return 0; +} + +void ddrmc_init(void) +{ + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + udelay(1); + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN); +} + +int dram_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + ddrmc_init(); +#endif + + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {CONFIG_SYS_FSL_ESDHC_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#ifndef CONFIG_QSPI_BOOT +int config_serdes_mux(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + + protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; + switch (protocol) { + case 0x10: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANED_PCIEX2 | + LANEC_PCIEX1, KEEP_STATUS); + break; + case 0x20: + convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); + convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + case 0x30: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + case 0x70: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + } + + return 0; +} +#endif + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + +#ifdef CONFIG_TSEC_ENET + out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); +#endif + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; +#endif + +struct smmu_stream_id dev_stream_id[] = { + { 0x100, 0x01, "ETSEC MAC1" }, + { 0x104, 0x02, "ETSEC MAC2" }, + { 0x108, 0x03, "ETSEC MAC3" }, + { 0x10c, 0x04, "PEX1" }, + { 0x110, 0x05, "PEX2" }, + { 0x114, 0x06, "qDMA" }, + { 0x118, 0x07, "SATA" }, + { 0x11c, 0x08, "USB3" }, + { 0x120, 0x09, "QE" }, + { 0x124, 0x0a, "eSDHC" }, + { 0x128, 0x0b, "eMA" }, + { 0x14c, 0x0c, "2D-ACE" }, + { 0x150, 0x0d, "USB2" }, + { 0x18c, 0x0e, "DEBUG" }, +}; + +int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); +#ifndef CONFIG_QSPI_BOOT + config_serdes_mux(); +#endif +#endif + + ls102xa_config_smmu_stream_id(dev_stream_id, + ARRAY_SIZE(dev_stream_id)); + +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif + + return 0; +} + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} + +#ifndef CONFIG_QSPI_BOOT +static void convert_flash_bank(char bank) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("Now switch to boot from flash bank %d.\n", bank); + cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; + cpld_data->vbank = bank; + + printf("Reset board to enable configuration.\n"); + cpld_data->system_rst = CONFIG_RESET; +} + +static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "0") == 0) + convert_flash_bank(BOOT_FROM_UPPER_BANK); + else if (strcmp(argv[1], "1") == 0) + convert_flash_bank(BOOT_FROM_LOWER_BANK); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + boot_bank, 2, 0, flash_bank_cmd, + "Flash bank Selection Control", + "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" +); + +static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + if (argc > 2) + return CMD_RET_USAGE; + if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) + cpld_data->system_rst = CONFIG_RESET; + else if (strcmp(argv[1], "init") == 0) + cpld_data->global_rst = INIT_RESET; + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + cpld_reset, 2, 0, cpld_reset_cmd, + "Reset via CPLD", + "conf\n" + " -reset with current CPLD configuration\n" + "init\n" + " -reset and initial CPLD configuration with default value" + +); + +static void convert_serdes_mux(int type, int need_reset) +{ + char current_serdes; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + current_serdes = cpld_data->serdes_mux; + + switch (type) { + case LANEB_SATA: + current_serdes &= ~MASK_LANE_B; + break; + case LANEB_SGMII1: + current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); + break; + case LANEC_SGMII1: + current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); + break; + case LANED_SGMII2: + current_serdes |= MASK_LANE_D; + break; + case LANEC_PCIEX1: + current_serdes |= MASK_LANE_C; + break; + case (LANED_PCIEX2 | LANEC_PCIEX1): + current_serdes |= MASK_LANE_C; + current_serdes &= ~MASK_LANE_D; + break; + default: + printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); + return; + } + + cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; + cpld_data->serdes_mux = current_serdes; + + if (need_reset == 1) { + printf("Reset board to enable configuration\n"); + cpld_data->system_rst = CONFIG_RESET; + } +} + +void print_serdes_mux(void) +{ + char current_serdes; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + current_serdes = cpld_data->serdes_mux; + + printf("Serdes Lane B: "); + if ((current_serdes & MASK_LANE_B) == 0) + printf("SATA,\n"); + else + printf("SGMII 1,\n"); + + printf("Serdes Lane C: "); + if ((current_serdes & MASK_LANE_C) == 0) + printf("SGMII 1,\n"); + else + printf("PCIe,\n"); + + printf("Serdes Lane D: "); + if ((current_serdes & MASK_LANE_D) == 0) + printf("PCIe,\n"); + else + printf("SGMII 2,\n"); + + printf("SGMII 1 is on lane "); + if ((current_serdes & MASK_SGMII) == 0) + printf("C.\n"); + else + printf("B.\n"); +} + +static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "sata") == 0) { + printf("Set serdes lane B to SATA.\n"); + convert_serdes_mux(LANEB_SATA, NEED_RESET); + } else if (strcmp(argv[1], "sgmii1b") == 0) { + printf("Set serdes lane B to SGMII 1.\n"); + convert_serdes_mux(LANEB_SGMII1, NEED_RESET); + } else if (strcmp(argv[1], "sgmii1c") == 0) { + printf("Set serdes lane C to SGMII 1.\n"); + convert_serdes_mux(LANEC_SGMII1, NEED_RESET); + } else if (strcmp(argv[1], "sgmii2") == 0) { + printf("Set serdes lane D to SGMII 2.\n"); + convert_serdes_mux(LANED_SGMII2, NEED_RESET); + } else if (strcmp(argv[1], "pciex1") == 0) { + printf("Set serdes lane C to PCIe X1.\n"); + convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); + } else if (strcmp(argv[1], "pciex2") == 0) { + printf("Set serdes lane C & lane D to PCIe X2.\n"); + convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); + } else if (strcmp(argv[1], "show") == 0) { + print_serdes_mux(); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + lane_bank, 2, 0, serdes_mux_cmd, + "Multiplexed function setting for SerDes Lanes", + "sata\n" + " -change lane B to sata\n" + "lane_bank sgmii1b\n" + " -change lane B to SGMII1\n" + "lane_bank sgmii1c\n" + " -change lane C to SGMII1\n" + "lane_bank sgmii2\n" + " -change lane D to SGMII2\n" + "lane_bank pciex1\n" + " -change lane C to PCIeX1\n" + "lane_bank pciex2\n" + " -change lane C & lane D to PCIeX2\n" + "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" +); +#endif diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg new file mode 100644 index 0000000000..f1a1b63ab7 --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg @@ -0,0 +1,12 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000000..9c3e3b080b --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000a 00000000 00000000 00000000 +20000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +00080000 881b7340 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#20000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#20084800 881b7340 00000000 00000000 diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2085a/Kconfig new file mode 100644 index 0000000000..f51afc8234 --- /dev/null +++ b/board/freescale/ls2085a/Kconfig @@ -0,0 +1,31 @@ +if TARGET_LS2085A_EMU + +config SYS_BOARD + default "ls2085a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-lsch3" + +config SYS_CONFIG_NAME + default "ls2085a_emu" + +endif + +if TARGET_LS2085A_SIMU + +config SYS_BOARD + default "ls2085a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-lsch3" + +config SYS_CONFIG_NAME + default "ls2085a_simu" + +endif diff --git a/board/freescale/ls2085a/MAINTAINERS b/board/freescale/ls2085a/MAINTAINERS new file mode 100644 index 0000000000..572c4b8446 --- /dev/null +++ b/board/freescale/ls2085a/MAINTAINERS @@ -0,0 +1,9 @@ +LS2085A BOARD +M: York Sun +S: Maintained +F: board/freescale/ls2085a/ +F: include/configs/ls2085a_emu.h +F: configs/ls2085a_emu_defconfig +F: configs/ls2085a_emu_D4_defconfig +F: include/configs/ls2085a_simu.h +F: configs/ls2085a_simu_defconfig diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile new file mode 100644 index 0000000000..701b35cd59 --- /dev/null +++ b/board/freescale/ls2085a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls2085a.o +obj-y += ddr.o diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README new file mode 100644 index 0000000000..b7023e1d48 --- /dev/null +++ b/board/freescale/ls2085a/README @@ -0,0 +1,16 @@ +Freescale ls2085a_emu + +This is a emulator target with limited peripherals. + +Memory map from core's view + +0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom +0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR +0x00_1800_0000 .. 0x00_181F_FFFF OCRAM +0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 +0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 +0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 +0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 + +Other addresses are either reserved, or not used directly by u-boot. +This list should be updated when more addresses are used. diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c new file mode 100644 index 0000000000..b4a3fc9a9e --- /dev/null +++ b/board/freescale/ls2085a/ddr.c @@ -0,0 +1,205 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; + + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + if (ctrl_num == CONFIG_DP_DDR_CTRL) { + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + } + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 1073741824u, + .capacity = 2147483648, + .primary_sdram_width = 64, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 937, + .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ + .taa_ps = 13090, + .twr_ps = 15000, + .trcd_ps = 13090, + .trrd_ps = 5000, + .trp_ps = 13090, + .tras_ps = 33000, + .trc_ps = 46090, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 25000, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing DDR...."); + + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + + return dram_size; +} + +void dram_init_banksize(void) +{ +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + phys_size_t dp_ddr_size; +#endif + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + } else { + gd->bd->bi_dram[0].size = gd->ram_size; + } + +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + CONFIG_DP_DDR_CTRL, + CONFIG_DP_DDR_NUM_CTRLS, + CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, + NULL, NULL, NULL); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } +#endif +} diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2085a/ddr.h new file mode 100644 index 0000000000..9958a68e3e --- /dev/null +++ b/board/freescale/ls2085a/ddr.h @@ -0,0 +1,86 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 2140, 0, 4, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +/* DP-DDR DIMM */ +static const struct board_specific_parameters udimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 2140, 0, 4, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 2140, 0, 5, 4, 0x0, 0x0}, + {2, 2140, 0, 5, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +/* DP-DDR DIMM */ +static const struct board_specific_parameters rdimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 2140, 0, 5, 4, 0x0, 0x0}, + {2, 2140, 0, 5, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm0, + udimm2, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm0, + rdimm2, +}; + + +#endif diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c new file mode 100644 index 0000000000..163a4c486a --- /dev/null +++ b/board/freescale/ls2085a/ls2085a.c @@ -0,0 +1,121 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + init_final_memctl_regs(); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + + return 0; +} + +int board_early_init_f(void) +{ + init_early_memctl_regs(); /* tighten IFC timing */ + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); + if (gd->bd->bi_dram[2].size) { + puts("\nDP-DDR "); + print_size(gd->bd->bi_dram[2].size, ""); + print_ddr_info(CONFIG_DP_DDR_CTRL); + } +} + +int dram_init(void) +{ + gd->ram_size = initdram(0); + + return 0; +} + +int timer_init(void) +{ + u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; + u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; + + out_le32(cltbenr, 0x1); /* enable cluster0 timebase */ + out_le32(cntcr, 0x1); /* enable clock for timer */ + + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +int board_eth_init(bd_t *bis) +{ + int error = 0; + +#ifdef CONFIG_SMC91111 + error = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + +#ifdef CONFIG_FSL_MC_ENET + error = cpu_eth_init(bis); +#endif + return error; +} + +#ifdef CONFIG_FSL_MC_ENET +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/fsl,dprc@0"); + if (get_mc_boot_status() == 0) + fdt_status_okay(fdt, offset); + else + fdt_status_fail(fdt, offset); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ + base = getenv_bootm_low(); + size = getenv_bootm_size(); + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_FSL_MC_ENET + fdt_fixup_board_enet(blob); +#endif + + return 0; +} +#endif diff --git a/board/freescale/m5208evbe/Kconfig b/board/freescale/m5208evbe/Kconfig new file mode 100644 index 0000000000..9b416afbdc --- /dev/null +++ b/board/freescale/m5208evbe/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5208EVBE + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5208evbe" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5208EVBE" + +endif diff --git a/board/freescale/m5208evbe/MAINTAINERS b/board/freescale/m5208evbe/MAINTAINERS new file mode 100644 index 0000000000..c9c3c882e6 --- /dev/null +++ b/board/freescale/m5208evbe/MAINTAINERS @@ -0,0 +1,6 @@ +M5208EVBE BOARD +#M: - +S: Maintained +F: board/freescale/m5208evbe/ +F: include/configs/M5208EVBE.h +F: configs/M5208EVBE_defconfig diff --git a/board/freescale/m5208evbe/Makefile b/board/freescale/m5208evbe/Makefile index d6be84f75f..1cb17fe39c 100644 --- a/board/freescale/m5208evbe/Makefile +++ b/board/freescale/m5208evbe/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5208evbe.o diff --git a/board/freescale/m52277evb/Kconfig b/board/freescale/m52277evb/Kconfig new file mode 100644 index 0000000000..c4278926a4 --- /dev/null +++ b/board/freescale/m52277evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M52277EVB + +config SYS_CPU + default "mcf5227x" + +config SYS_BOARD + default "m52277evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M52277EVB" + +endif diff --git a/board/freescale/m52277evb/MAINTAINERS b/board/freescale/m52277evb/MAINTAINERS new file mode 100644 index 0000000000..390f041183 --- /dev/null +++ b/board/freescale/m52277evb/MAINTAINERS @@ -0,0 +1,7 @@ +M52277EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m52277evb/ +F: include/configs/M52277EVB.h +F: configs/M52277EVB_defconfig +F: configs/M52277EVB_stmicro_defconfig diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile index d6be84f75f..6b3b8aee60 100644 --- a/board/freescale/m52277evb/Makefile +++ b/board/freescale/m52277evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m52277evb.o diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk deleted file mode 100644 index 0ffb0a204b..0000000000 --- a/board/freescale/m52277evb/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index f3337a3845..70121d9248 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -13,8 +13,8 @@ SECTIONS .text : { arch/m68k/cpu/mcf5227x/start.o (.text*) - arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text*) - arch/m68k/lib/libm68k.o (.text*) + arch/m68k/cpu/mcf5227x/built-in.o (.text*) + arch/m68k/lib/built-in.o (.text*) *(.text*) } diff --git a/board/freescale/m5235evb/Kconfig b/board/freescale/m5235evb/Kconfig new file mode 100644 index 0000000000..fc8341999a --- /dev/null +++ b/board/freescale/m5235evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5235EVB + +config SYS_CPU + default "mcf523x" + +config SYS_BOARD + default "m5235evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5235EVB" + +endif diff --git a/board/freescale/m5235evb/MAINTAINERS b/board/freescale/m5235evb/MAINTAINERS new file mode 100644 index 0000000000..f44422ea9d --- /dev/null +++ b/board/freescale/m5235evb/MAINTAINERS @@ -0,0 +1,7 @@ +M5235EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m5235evb/ +F: include/configs/M5235EVB.h +F: configs/M5235EVB_defconfig +F: configs/M5235EVB_Flash32_defconfig diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile index d6be84f75f..e77d9d95b1 100644 --- a/board/freescale/m5235evb/Makefile +++ b/board/freescale/m5235evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5235evb.o diff --git a/board/freescale/m5235evb/config.mk b/board/freescale/m5235evb/config.mk deleted file mode 100644 index 9ab4582bf8..0000000000 --- a/board/freescale/m5235evb/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -/*CONFIG_SYS_TEXT_BASE = 0xFFC00000*/ -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m5249evb/Kconfig b/board/freescale/m5249evb/Kconfig new file mode 100644 index 0000000000..0f624776b5 --- /dev/null +++ b/board/freescale/m5249evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5249EVB + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5249evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5249EVB" + +endif diff --git a/board/freescale/m5249evb/MAINTAINERS b/board/freescale/m5249evb/MAINTAINERS new file mode 100644 index 0000000000..c2273c35e1 --- /dev/null +++ b/board/freescale/m5249evb/MAINTAINERS @@ -0,0 +1,6 @@ +M5249EVB BOARD +#M: - +S: Maintained +F: board/freescale/m5249evb/ +F: include/configs/M5249EVB.h +F: configs/M5249EVB_defconfig diff --git a/board/freescale/m5249evb/Makefile b/board/freescale/m5249evb/Makefile index e7f4fb63b0..4267633f52 100644 --- a/board/freescale/m5249evb/Makefile +++ b/board/freescale/m5249evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5249evb.o diff --git a/board/freescale/m5253demo/Kconfig b/board/freescale/m5253demo/Kconfig new file mode 100644 index 0000000000..303d29bc23 --- /dev/null +++ b/board/freescale/m5253demo/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5253DEMO + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5253demo" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5253DEMO" + +endif diff --git a/board/freescale/m5253demo/MAINTAINERS b/board/freescale/m5253demo/MAINTAINERS new file mode 100644 index 0000000000..abe065e626 --- /dev/null +++ b/board/freescale/m5253demo/MAINTAINERS @@ -0,0 +1,6 @@ +M5253DEMO BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m5253demo/ +F: include/configs/M5253DEMO.h +F: configs/M5253DEMO_defconfig diff --git a/board/freescale/m5253demo/Makefile b/board/freescale/m5253demo/Makefile index 871865b6ee..62f3146fe3 100644 --- a/board/freescale/m5253demo/Makefile +++ b/board/freescale/m5253demo/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5253demo.o flash.o diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index 387e454cef..071701d234 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -56,14 +56,16 @@ ulong flash_init(void) int flash_get_offsets(ulong base, flash_info_t * info) { - int j, k; + int i; if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { info->start[0] = base; - for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) { - info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ; - info->protect[k] = 0; + info->protect[0] = 0; + for (i = 1; i < CONFIG_SYS_SST_SECT; i++) { + info->start[i] = info->start[i - 1] + + CONFIG_SYS_SST_SECTSZ; + info->protect[i] = 0; } } @@ -177,7 +179,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { FPWV *addr; int flag, prot, sect, count; - ulong type, start, last; + ulong type, start; int rcode = 0, flashtype = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -217,7 +219,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) flag = disable_interrupts(); start = get_timer(0); - last = start; if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) { if (prot == 0) { @@ -319,14 +320,13 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) { ulong wp, count; u16 data; - int rc, port_width; + int rc; if (info->flash_id == FLASH_UNKNOWN) return 4; /* get lower word aligned address */ wp = addr; - port_width = sizeof(FPW); /* handle unaligned start bytes */ if (wp & 1) { diff --git a/board/freescale/m5253evbe/Kconfig b/board/freescale/m5253evbe/Kconfig new file mode 100644 index 0000000000..d97b87c4ca --- /dev/null +++ b/board/freescale/m5253evbe/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5253EVBE + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5253evbe" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5253EVBE" + +endif diff --git a/board/freescale/m5253evbe/MAINTAINERS b/board/freescale/m5253evbe/MAINTAINERS new file mode 100644 index 0000000000..74acd1eee5 --- /dev/null +++ b/board/freescale/m5253evbe/MAINTAINERS @@ -0,0 +1,6 @@ +M5253EVBE BOARD +#M: Hayden Fraser +S: Orphan (since 2014-06) +F: board/freescale/m5253evbe/ +F: include/configs/M5253EVBE.h +F: configs/M5253EVBE_defconfig diff --git a/board/freescale/m5253evbe/Makefile b/board/freescale/m5253evbe/Makefile index e7f4fb63b0..8c55075c7a 100644 --- a/board/freescale/m5253evbe/Makefile +++ b/board/freescale/m5253evbe/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5253evbe.o diff --git a/board/freescale/m5271evb/Makefile b/board/freescale/m5271evb/Makefile deleted file mode 100644 index e7f4fb63b0..0000000000 --- a/board/freescale/m5271evb/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/m5271evb/config.mk b/board/freescale/m5271evb/config.mk deleted file mode 100644 index 957f584887..0000000000 --- a/board/freescale/m5271evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c deleted file mode 100644 index 5981a2711a..0000000000 --- a/board/freescale/m5271evb/m5271evb.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int checkboard (void) { - puts ("Board: Freescale M5271EVB\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - - int i; - - /* Enable Address lines 23-21 and lower 16bits of data path */ - mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 | - MCF_GPIO_AD_DATAL); - - /* Set CS2 pin to be SD_CS0 */ - mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) - | MCF_GPIO_PAR_CS_PAR_CS2); - - /* Configure SDRAM Control Pin Assignemnt Register */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 | - MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_11); - asm(" nop"); - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { - /* Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(2) - | MCF_SDRAMC_DCR_RC(0x2E)); - asm(" nop"); - - /* - * Initialize DACR0 - * - * CASL: 01 - * CBM: cmd at A20, bank select bits 21 and up - * PS: 32bit port size - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) - | MCF_SDRAMC_DACRn_CASL(1) - | MCF_SDRAMC_DACRn_CBM(3) - | MCF_SDRAMC_DACRn_PS(0)); - asm(" nop"); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M - | MCF_SDRAMC_DMRn_V); - asm(" nop"); - - /* Set IP bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_IP); - asm(" nop"); - - /* Wait at least 20ns to allow banks to precharge */ - for (i = 0; i < 5; i++) - asm(" nop"); - - /* Write to this block to initiate precharge */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; - asm(" nop"); - - /* Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_RE); - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 2000; i++) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_MRS); - asm(" nop"); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 2 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5; - asm(" nop"); - } - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds deleted file mode 100644 index 3defcd25c1..0000000000 --- a/board/freescale/m5271evb/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/freescale/m5272c3/Kconfig b/board/freescale/m5272c3/Kconfig new file mode 100644 index 0000000000..aee0b239b3 --- /dev/null +++ b/board/freescale/m5272c3/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5272C3 + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5272c3" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5272C3" + +endif diff --git a/board/freescale/m5272c3/MAINTAINERS b/board/freescale/m5272c3/MAINTAINERS new file mode 100644 index 0000000000..e58663096d --- /dev/null +++ b/board/freescale/m5272c3/MAINTAINERS @@ -0,0 +1,6 @@ +M5272C3 BOARD +#M: - +S: Maintained +F: board/freescale/m5272c3/ +F: include/configs/M5272C3.h +F: configs/M5272C3_defconfig diff --git a/board/freescale/m5272c3/Makefile b/board/freescale/m5272c3/Makefile index e7f4fb63b0..10a45f10fc 100644 --- a/board/freescale/m5272c3/Makefile +++ b/board/freescale/m5272c3/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5272c3.o diff --git a/board/freescale/m5275evb/Kconfig b/board/freescale/m5275evb/Kconfig new file mode 100644 index 0000000000..5a6de9c1c9 --- /dev/null +++ b/board/freescale/m5275evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5275EVB + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5275evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5275EVB" + +endif diff --git a/board/freescale/m5275evb/MAINTAINERS b/board/freescale/m5275evb/MAINTAINERS new file mode 100644 index 0000000000..4e6dbb12d9 --- /dev/null +++ b/board/freescale/m5275evb/MAINTAINERS @@ -0,0 +1,6 @@ +M5275EVB BOARD +#M: - +S: Maintained +F: board/freescale/m5275evb/ +F: include/configs/M5275EVB.h +F: configs/M5275EVB_defconfig diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile index d6be84f75f..d285c14598 100644 --- a/board/freescale/m5275evb/Makefile +++ b/board/freescale/m5275evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5275evb.o diff --git a/board/freescale/m5282evb/Kconfig b/board/freescale/m5282evb/Kconfig new file mode 100644 index 0000000000..2ffdd528f6 --- /dev/null +++ b/board/freescale/m5282evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5282EVB + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5282evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5282EVB" + +endif diff --git a/board/freescale/m5282evb/MAINTAINERS b/board/freescale/m5282evb/MAINTAINERS new file mode 100644 index 0000000000..305e748e74 --- /dev/null +++ b/board/freescale/m5282evb/MAINTAINERS @@ -0,0 +1,6 @@ +M5282EVB BOARD +#M: - +S: Maintained +F: board/freescale/m5282evb/ +F: include/configs/M5282EVB.h +F: configs/M5282EVB_defconfig diff --git a/board/freescale/m5282evb/Makefile b/board/freescale/m5282evb/Makefile index e7f4fb63b0..dab8f72e72 100644 --- a/board/freescale/m5282evb/Makefile +++ b/board/freescale/m5282evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5282evb.o diff --git a/board/freescale/m53017evb/Kconfig b/board/freescale/m53017evb/Kconfig new file mode 100644 index 0000000000..8ab89e52b2 --- /dev/null +++ b/board/freescale/m53017evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M53017EVB + +config SYS_CPU + default "mcf532x" + +config SYS_BOARD + default "m53017evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M53017EVB" + +endif diff --git a/board/freescale/m53017evb/MAINTAINERS b/board/freescale/m53017evb/MAINTAINERS new file mode 100644 index 0000000000..700b6f700a --- /dev/null +++ b/board/freescale/m53017evb/MAINTAINERS @@ -0,0 +1,6 @@ +M53017EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m53017evb/ +F: include/configs/M53017EVB.h +F: configs/M53017EVB_defconfig diff --git a/board/freescale/m53017evb/Makefile b/board/freescale/m53017evb/Makefile index d6be84f75f..bc4bf4a957 100644 --- a/board/freescale/m53017evb/Makefile +++ b/board/freescale/m53017evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m53017evb.o diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index ef21299ea9..de8d09bf66 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -12,9 +12,9 @@ SECTIONS /* Read-only sections, merged into text segment: */ .text : { - arch/m68k/cpu/mcf532x/start.o (.text*) - arch/m68k/cpu/mcf532x/libmcf532x.o (.text*) - arch/m68k/lib/libm68k.o (.text*) + arch/m68k/cpu/mcf532x/start.o (.text*) + arch/m68k/cpu/mcf532x/built-in.o (.text*) + arch/m68k/lib/built-in.o (.text*) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text*) diff --git a/board/freescale/m5329evb/Kconfig b/board/freescale/m5329evb/Kconfig new file mode 100644 index 0000000000..930fbba246 --- /dev/null +++ b/board/freescale/m5329evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5329EVB + +config SYS_CPU + default "mcf532x" + +config SYS_BOARD + default "m5329evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5329EVB" + +endif diff --git a/board/freescale/m5329evb/MAINTAINERS b/board/freescale/m5329evb/MAINTAINERS new file mode 100644 index 0000000000..f4f103a4c7 --- /dev/null +++ b/board/freescale/m5329evb/MAINTAINERS @@ -0,0 +1,7 @@ +M5329EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m5329evb/ +F: include/configs/M5329EVB.h +F: configs/M5329AFEE_defconfig +F: configs/M5329BFEE_defconfig diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile index 79aa8362ed..d8dbafaa8f 100644 --- a/board/freescale/m5329evb/Makefile +++ b/board/freescale/m5329evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o nand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5329evb.o nand.o diff --git a/board/freescale/m5373evb/Kconfig b/board/freescale/m5373evb/Kconfig new file mode 100644 index 0000000000..67d049d79e --- /dev/null +++ b/board/freescale/m5373evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5373EVB + +config SYS_CPU + default "mcf532x" + +config SYS_BOARD + default "m5373evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5373EVB" + +endif diff --git a/board/freescale/m5373evb/MAINTAINERS b/board/freescale/m5373evb/MAINTAINERS new file mode 100644 index 0000000000..5db0b34a66 --- /dev/null +++ b/board/freescale/m5373evb/MAINTAINERS @@ -0,0 +1,6 @@ +M5373EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m5373evb/ +F: include/configs/M5373EVB.h +F: configs/M5373EVB_defconfig diff --git a/board/freescale/m5373evb/Makefile b/board/freescale/m5373evb/Makefile index 79aa8362ed..d34e327597 100644 --- a/board/freescale/m5373evb/Makefile +++ b/board/freescale/m5373evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o nand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m5373evb.o nand.o diff --git a/board/freescale/m54418twr/Kconfig b/board/freescale/m54418twr/Kconfig new file mode 100644 index 0000000000..4199a3f549 --- /dev/null +++ b/board/freescale/m54418twr/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M54418TWR + +config SYS_CPU + default "mcf5445x" + +config SYS_BOARD + default "m54418twr" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M54418TWR" + +endif diff --git a/board/freescale/m54418twr/MAINTAINERS b/board/freescale/m54418twr/MAINTAINERS new file mode 100644 index 0000000000..f88aed99d6 --- /dev/null +++ b/board/freescale/m54418twr/MAINTAINERS @@ -0,0 +1,11 @@ +M54418TWR BOARD +#M: - +S: Maintained +F: board/freescale/m54418twr/ +F: include/configs/M54418TWR.h +F: configs/M54418TWR_defconfig +F: configs/M54418TWR_nand_mii_defconfig +F: configs/M54418TWR_nand_rmii_defconfig +F: configs/M54418TWR_nand_rmii_lowfreq_defconfig +F: configs/M54418TWR_serial_mii_defconfig +F: configs/M54418TWR_serial_rmii_defconfig diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile index dc40f300f9..371c04abe8 100644 --- a/board/freescale/m54418twr/Makefile +++ b/board/freescale/m54418twr/Makefile @@ -4,24 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m54418twr.o diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk index b306d031b9..07f52e0255 100644 --- a/board/freescale/m54418twr/config.mk +++ b/board/freescale/m54418twr/config.mk @@ -4,6 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m54451evb/Kconfig b/board/freescale/m54451evb/Kconfig new file mode 100644 index 0000000000..f460e51c9b --- /dev/null +++ b/board/freescale/m54451evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M54451EVB + +config SYS_CPU + default "mcf5445x" + +config SYS_BOARD + default "m54451evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M54451EVB" + +endif diff --git a/board/freescale/m54451evb/MAINTAINERS b/board/freescale/m54451evb/MAINTAINERS new file mode 100644 index 0000000000..52a2681080 --- /dev/null +++ b/board/freescale/m54451evb/MAINTAINERS @@ -0,0 +1,7 @@ +M54451EVB BOARD +#M: - +S: Maintained +F: board/freescale/m54451evb/ +F: include/configs/M54451EVB.h +F: configs/M54451EVB_defconfig +F: configs/M54451EVB_stmicro_defconfig diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile index d6be84f75f..700ea2a74c 100644 --- a/board/freescale/m54451evb/Makefile +++ b/board/freescale/m54451evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m54451evb.o diff --git a/board/freescale/m54451evb/config.mk b/board/freescale/m54451evb/config.mk deleted file mode 100644 index 0ffb0a204b..0000000000 --- a/board/freescale/m54451evb/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m54455evb/Kconfig b/board/freescale/m54455evb/Kconfig new file mode 100644 index 0000000000..096bce8312 --- /dev/null +++ b/board/freescale/m54455evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M54455EVB + +config SYS_CPU + default "mcf5445x" + +config SYS_BOARD + default "m54455evb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M54455EVB" + +endif diff --git a/board/freescale/m54455evb/MAINTAINERS b/board/freescale/m54455evb/MAINTAINERS new file mode 100644 index 0000000000..3788f5f87e --- /dev/null +++ b/board/freescale/m54455evb/MAINTAINERS @@ -0,0 +1,10 @@ +M54455EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m54455evb/ +F: include/configs/M54455EVB.h +F: configs/M54455EVB_defconfig +F: configs/M54455EVB_a66_defconfig +F: configs/M54455EVB_i66_defconfig +F: configs/M54455EVB_intel_defconfig +F: configs/M54455EVB_stm33_defconfig diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile index d6be84f75f..1c775fadb8 100644 --- a/board/freescale/m54455evb/Makefile +++ b/board/freescale/m54455evb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m54455evb.o diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk deleted file mode 100644 index 0ffb0a204b..0000000000 --- a/board/freescale/m54455evb/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m547xevb/Kconfig b/board/freescale/m547xevb/Kconfig new file mode 100644 index 0000000000..8cfe20ab8d --- /dev/null +++ b/board/freescale/m547xevb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5475EVB + +config SYS_CPU + default "mcf547x_8x" + +config SYS_BOARD + default "m547xevb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5475EVB" + +endif diff --git a/board/freescale/m547xevb/MAINTAINERS b/board/freescale/m547xevb/MAINTAINERS new file mode 100644 index 0000000000..9a8408d257 --- /dev/null +++ b/board/freescale/m547xevb/MAINTAINERS @@ -0,0 +1,12 @@ +M547XEVB BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m547xevb/ +F: include/configs/M5475EVB.h +F: configs/M5475AFE_defconfig +F: configs/M5475BFE_defconfig +F: configs/M5475CFE_defconfig +F: configs/M5475DFE_defconfig +F: configs/M5475EFE_defconfig +F: configs/M5475FFE_defconfig +F: configs/M5475GFE_defconfig diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile index d6be84f75f..816917734b 100644 --- a/board/freescale/m547xevb/Makefile +++ b/board/freescale/m547xevb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m547xevb.o diff --git a/board/freescale/m548xevb/Kconfig b/board/freescale/m548xevb/Kconfig new file mode 100644 index 0000000000..da924e3ce9 --- /dev/null +++ b/board/freescale/m548xevb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5485EVB + +config SYS_CPU + default "mcf547x_8x" + +config SYS_BOARD + default "m548xevb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "M5485EVB" + +endif diff --git a/board/freescale/m548xevb/MAINTAINERS b/board/freescale/m548xevb/MAINTAINERS new file mode 100644 index 0000000000..82ad9fdc60 --- /dev/null +++ b/board/freescale/m548xevb/MAINTAINERS @@ -0,0 +1,13 @@ +M548XEVB BOARD +M: TsiChung Liew +S: Maintained +F: board/freescale/m548xevb/ +F: include/configs/M5485EVB.h +F: configs/M5485AFE_defconfig +F: configs/M5485BFE_defconfig +F: configs/M5485CFE_defconfig +F: configs/M5485DFE_defconfig +F: configs/M5485EFE_defconfig +F: configs/M5485FFE_defconfig +F: configs/M5485GFE_defconfig +F: configs/M5485HFE_defconfig diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile index d6be84f75f..4483d15981 100644 --- a/board/freescale/m548xevb/Makefile +++ b/board/freescale/m548xevb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = m548xevb.o diff --git a/board/freescale/mpc5121ads/Kconfig b/board/freescale/mpc5121ads/Kconfig new file mode 100644 index 0000000000..f125f9e596 --- /dev/null +++ b/board/freescale/mpc5121ads/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC5121ADS + +config SYS_BOARD + default "mpc5121ads" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mpc5121ads" + +endif diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS new file mode 100644 index 0000000000..d4aab8fb51 --- /dev/null +++ b/board/freescale/mpc5121ads/MAINTAINERS @@ -0,0 +1,7 @@ +MPC5121ADS BOARD +#M: - +S: Maintained +F: board/freescale/mpc5121ads/ +F: include/configs/mpc5121ads.h +F: configs/mpc5121ads_defconfig +F: configs/mpc5121ads_rev2_defconfig diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile index b5cd5f734c..67cf55546b 100644 --- a/board/freescale/mpc5121ads/Makefile +++ b/board/freescale/mpc5121ads/Makefile @@ -5,27 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -$(shell mkdir -p $(OBJTREE)/board/freescale/common) - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mpc5121ads.o diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README index defcd6b469..741bc40382 100644 --- a/board/freescale/mpc5121ads/README +++ b/board/freescale/mpc5121ads/README @@ -1,7 +1,7 @@ To configure for the current (Rev 3.x) ADS5121 - make ads5121_config + make mpc5121ads_config This will automatically include PCI, the Real Time CLock, add backup flash ability and set the correct frequency and memory configuration. To configure for the older Rev 2 ADS5121 type (this will not have PCI) - make ads5121_rev2_config + make mpc5121ads_rev2_config diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 940978e649..40bd55dfba 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -275,8 +275,10 @@ int checkboard (void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/freescale/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile deleted file mode 100644 index 03917463bc..0000000000 --- a/board/freescale/mpc7448hpc2/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o tsi108_init.o -SOBJS := asm_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude ($obj).depend - -######################################################################### diff --git a/board/freescale/mpc7448hpc2/README b/board/freescale/mpc7448hpc2/README deleted file mode 100644 index cbb043e1d0..0000000000 --- a/board/freescale/mpc7448hpc2/README +++ /dev/null @@ -1,184 +0,0 @@ -Freescale MPC7448hpc2 (Taiga) board -=================================== - -Created 08/11/2006 Roy Zang --------------------------- -MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference -design, which is optimized for high speed throughput between the processor and -the memory, disk drive and Ethernet port subsystems. - -MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be -used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX -chassis. - -Building U-Boot ------------------- -The mpc7448hpc2 code base is known to compile using: - Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 - - $ make mpc7448hpc2_config - Configuring for mpc7448hpc2 board... - - $ make - -Memory Map ----------- - -The memory map is setup for Linux to operate properly. - -The mapping is: - - Range Start Range End Definition Size - - 0x0000_0000 0x7fff_ffff DDR 2G - 0xe000_0000 0xe7ff_ffff PCI Memory 128M - 0xfa00_0000 0xfaff_ffff PCI IO 16M - 0xfb00_0000 0xfbff_ffff PCI Config 16M - 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M - 0xfe00_0000 0xfeff_ffff PromJet 16M - 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M - 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M - -Using Flash ------------ - -The MPC7448hpc2 board has two "banks" of flash, each 8MB in size -(2^23 = 0x00800000). - -Note: the "bank" here refers to half of the flash. In fact, there is only one -bank of flash, which is divided into low and high half. Each is controlled by -the most significant bit of the address bus. The so called "bank" is only for -convenience. - -There is a switch which allows the "bank" to be selected. The switch -settings for updating flash are given below. - -The u-boot commands for copying the boot-bank into the secondary bank are -as follows: - - erase ff800000 ff880000 - cp.b ff000000 ff800000 80000 - -U-boot commands for downloading an image via tftp and flashing -it into the secondary bank: - - tftp 10000 - erase ff000000 ff080000 - cp.b 10000 ff000000 80000 - -After copying the image into the second bank of flash, be sure to toggle -SW3[4] on board before resetting the board in order to set the -secondary bank as the boot-bank. - -Board Switches ----------------------- - -Most switches on the board should not be changed. The most frequent -user-settable switches on the board are used to configure -the flash banks and determining the PCI frequency. - -SW1[1-5]: Processor core voltage - - 12345 Core Voltage - ----- - SW1=01111 1.000V. - SW1=01101 1.100V. - SW1=01011 1.200V. - SW1=01001 1.300V only for MPC7447A. - - -SW2[1-6]: CPU core frequency - - CPU Core Frequency (MHz) - Bus Frequency - 123456 100 133 167 200 Ratio - - ------ - SW2=101100 500 667 833 1000 5x - SW2=100100 550 733 917 1100 5.5x - SW2=110100 600 800 1000 1200 6x - SW2=010100 650 866 1083 1300 6.5x - SW2=001000 700 930 1167 1400 7x - SW2=000100 750 1000 1250 1500 7.5x - SW2=110000 800 1066 1333 1600 8x - SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A - SW2=011110 900 1200 1500 1800 9x - -This table shows only a subset of available frequency options; see the CPU -hardware specifications for more information. - -SW2[7-8]: Bus Protocol and CPU Reset Option - - 7 - - - SW2=0 System bus uses MPX bus protocol - SW2=1 System bus uses 60x bus protocol - - 8 - - - SW2=0 TSI108 can cause CPU reset - SW2=1 TSI108 can not cause CPU reset - -SW3[1-8] system options - - 123 - --- - SW3=xxx Connected to GPIO[0:2] on TSI108 - - 4 - - - SW3=0 CPU boots from low half of flash - SW3=1 CPU boots from high half of flash - - 5 - - - SW3=0 SATA and slot2 connected to PCI bus - SW3=1 Only slot1 connected to PCI bus - - 6 - - - SW3=0 USB connected to PCI bus - SW3=1 USB disconnected from PCI bus - - 7 - - - SW3=0 Flash is write protected - SW3=1 Flash is NOT write protected - - 8 - - - SW3=0 CPU will boot from flash - SW3=1 CPU will boot from PromJet - -SW4[1-3]: System bus frequency - - Bus Frequency (MHz) - --- - SW4=010 183 - SW4=011 100 - SW4=100 133 - SW4=101 166 only for MPC7447A - SW4=110 200 only for MPC7448 - others reserved - -SW4[4-6]: DDR2 SDRAM frequency - - Bus Frequency (MHz) - --- - SW4=000 external clock - SW4=011 system clock - SW4=100 133 - SW4=101 166 - SW4=110 200 - others reserved - -SW4[7-8]: PCI/PCI-X frequency control - 7 - - - SW4=0 PCI/PCI-X bus operates normally - SW4=1 PCI bus forced to PCI-33 mode - - 8 - - - SW4=0 PCI-X mode at 133 MHz allowed - SW4=1 PCI-X mode limited to 100 MHz diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S deleted file mode 100644 index 70315c31e4..0000000000 --- a/board/freescale/mpc7448hpc2/asm_init.S +++ /dev/null @@ -1,905 +0,0 @@ -/* - * (C) Copyright 2004-05; Tundra Semiconductor Corp. - * - * Added automatic detect of SDC settings - * Copyright (c) 2005 Freescale Semiconductor, Inc. - * Maintainer tie-fei.zang@freescale.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * FILENAME: asm_init.s - * - * Originator: Alex Bounine - * - * DESCRIPTION: - * Initialization code for the Tundra Tsi108 bridge chip - * - */ - -#include -#include - -#include -#include -#include - -#include - -/* - * Build Configuration Options - */ - -/* #define DISABLE_PBM disables usage of PB Master */ -/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ -/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ - -/* - * Hardcoded SDC settings - */ - -#ifdef SDC_HARDCODED_INIT - -/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ - -#define VAL_SD_REFRESH (0x61A) -#define VAL_SD_TIMING (0x0308336b) -#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ -#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ -#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ -#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ - -#endif /* SDC_HARDCODED_INIT */ - -/* - CPU Configuration: - - CPU Address and Data Parity enables. - -#define CPU_AP -#define CPU_DP -*/ - -/* - * Macros - * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are - * expected to work correctly for the CSR space within 32KB range. - * - * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. - * These macros are absolutely identical except their names. This difference - * is provided intentionally for better readable code. - */ - -#define LOAD_PTR(reg,const32) \ - addis reg,r0,const32@h; ori reg,reg,const32@l - -#define LOAD_U32(reg,const32) \ - addis reg,r0,const32@h; ori reg,reg,const32@l - -/* LOADMEM initializes a register with the contents of a specified 32-bit - * memory location, usually a CSR value. - */ - -#define LOAD_MEM(reg,addr32) \ - addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) - -#ifndef SDC_HARDCODED_INIT -sdc_clk_sync: - /* MHz: 0,0,183,100,133,167,200,233 */ - .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */ -#endif - -/* - * board_asm_init() - early initialization function. Coded to be portable to - * dual-CPU configuration. - * Checks CPU number and performs board HW initialization if called for CPU0. - * Registers used: r3,r4,r5,r6,r19,r29 - * - * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 - * and the rest of the board. Current implementation demonstrates two - * possible ways to identify CPU number: - * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. - * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. - */ - - .globl board_asm_init -board_asm_init: - mflr r19 /* Save LR to be able return later. */ - bl icache_enable /* Enable icache to reduce reads from flash. */ - -/* Initialize pointer to Tsi108 register space */ - - LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ - ori r4,r29,TSI108_PB_REG_OFFSET - -/* Check Processor Version Number */ - - mfspr r3, PVR - rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ - - cmpli 0,0,r3,0x8000 /* MPC74xx */ - bne cont_brd_init - - /* - * For MPC744x/5x enable extended BATs[4-7] - * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 - * to disable prefetch - */ - - mfspr r5, HID0 - oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ - ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ - mtspr HID0, r5 - isync - sync - - /* Adding code to disable external interventions in MPX bus mode */ - mfspr r3, 1014 - oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ - mtspr 1014, r3 - isync - sync - - /* Sri: code to enable FP unit */ - mfmsr r3 - ori r3, r3, 0x2000 - mtmsr r3 - isync - sync - - /* def CONFIG_DUAL_CPU - * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. - */ -#if(1) - mfspr r3,1014 /* read MSSCR0 */ - rlwinm. r3,r3,27,31,31 /* get processor ID number */ - mtspr SPRN_PIR,r3 /* Save CPU ID */ - sync - bne init_done - b do_tsi108_init - -cont_brd_init: - - /* An alternative method of checking the processor number (in addition - * to configuration using MSSCR0[ID] bit on MPC74xx). - * Good for IBM PPC750FX/GX. - */ - - lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ - rlwinm. r3,r3,24,31,31 /* get processor ID number */ - bne init_done -#else - -cont_brd_init: - -#endif /* CONFIG_DUAL_CPU */ - - /* Initialize Tsi108 chip */ - -do_tsi108_init: - - /* - * Adjust HLP/Flash parameters. By default after reset the HLP port is - * set to support slow devices. Better performance can be achived when - * an optimal parameters are used for specific EPROM device. - * NOTE: This should be performed ASAP for the emulation platform - * because it has 5MHz HLP clocking. - */ - -#ifdef CONFIG_TSI108EMU - ori r4,r29,TSI108_HLP_REG_OFFSET - LOAD_U32(r5,0x434422c0) - stw r5,0x08(r4) /* set HLP B0_CTRL0 */ - sync - LOAD_U32(r5,0xd0012000) - stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ - sync -#endif - - /* Initialize PB interface. */ - - ori r4,r29,TSI108_PB_REG_OFFSET - -#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE) - /* Relocate (if required) Tsi108 registers. Set new value for - * PB_REG_BAR: - * Note we are in the 32-bit address mode. - */ - LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ - stw r5,PB_REG_BAR(r4) - andis. r29,r5,0xFFFF - sync - ori r4,r29,TSI108_PB_REG_OFFSET -#endif - - /* Set PB Slave configuration register */ - - LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */ - lwz r3, PB_RSR(r4) /* get PB bus mode */ - xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ - rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ - stw r5,PB_SCR(r4) - sync - - /* Configure PB Arbiter */ - - lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ - li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ -#ifdef DISABLE_PBM - ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ -#endif - andc r5,r5,r3 /* Clear the masked bit fields */ - ori r5,r5,0x0001 /* Set pipeline depth */ - stw r5,PB_ARB_CTRL(r4) - -#if (0) /* currently using the default settings for PBM after reset */ - LOAD_U32(r5,0x) /* value for PB_MCR */ - stw r5,PB_MCR(r4) - sync - - LOAD_U32(r5,0x) /* value for PB_MCMD */ - stw r5,PB_MCMD(r4) - sync -#endif - - /* Disable or enable PVT based on processor bus frequency - * 1. Read CG_PWRUP_STATUS register field bits 18,17,16 - * 2. See if the value is < or > 133mhz (18:16 = 100) - * 3. If > enable PVT - */ - - LOAD_U32(r3,0xC0002234) - lwz r3,0(r3) - rlwinm r3,r3,16,29,31 - - cmpi 0,0,r3,0x0004 - bgt sdc_init - -#ifndef CONFIG_TSI108EMU - /* FIXME: Disable PB calibration control for any real Tsi108 board */ - li r5,0x0101 /* disable calibration control */ - stw r5,PB_PVT_CTRL2(r4) - sync -#endif - - /* Initialize SDRAM controller. */ - -sdc_init: - -#ifndef SDC_HARDCODED_INIT - /* get SDC clock prior doing sdram controller autoconfig */ - ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ - lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ - rlwinm r3,r3,12,29,31 /* r3 - SD clk */ - lis r5,sdc_clk_sync@h - ori r5,r5,sdc_clk_sync@l - /* Sri: At this point check if r3 = 001. If yes, - * the memory frequency should be same as the - * MPX bus frequency - */ - cmpi 0,0,r3,0x0001 - bne get_nsec - lwz r6, CG_PWRUP_STATUS(r4) - rlwinm r6,r6,16,29,31 - mr r3,r6 - -get_nsec: - rlwinm r3,r3,2,0,31 - lwzx r9,r5,r3 /* get SD clk rate in nSec */ - /* ATTN: r9 will be used by SPD routine */ -#endif /* !SDC_HARDCODED_INIT */ - - ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ - - /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ - - LOAD_U32(r5,0x00) - stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ -#ifdef ENABLE_SDRAM_ECC - li r5, 0x01 -#endif /* ENABLE_SDRAM_ECC */ - stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ - sync - -#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ - - /* First read the CG_PWRUP_STATUS register to get the - * memory speed from bits 22,21,20 - */ - - LOAD_U32(r3,0xC0002234) - lwz r3,0(r3) - rlwinm r3,r3,12,29,31 - - /* Now first check for 166, then 200, or default */ - - cmpi 0,0,r3,0x0005 - bne check_for_200mhz - - /* set values for 166 Mhz memory speed - * Set refresh rate and timing parameters - */ - LOAD_U32(r5,0x00000515) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,0x03073368) - stw r5,SD_TIMING(r4) - sync - - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync - - b sdc_init_done - -check_for_200mhz: - - cmpi 0,0,r3,0x0006 - bne set_default_values - - /* set values for 200Mhz memory speed - * Set refresh rate and timing parameters - */ - LOAD_U32(r5,0x0000061a) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,0x03083348) - stw r5,SD_TIMING(r4) - sync - - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync - - b sdc_init_done - -set_default_values: - - /* Set refresh rate and timing parameters */ - LOAD_U32(r5,VAL_SD_REFRESH) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,VAL_SD_TIMING) - stw r5,SD_TIMING(r4) - sync - - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ -#ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ -#endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync -#else /* !SDC_HARDCODED_INIT */ - bl tsi108_sdram_spd /* automatically detect SDC settings */ -#endif /* SDC_HARDCODED_INIT */ - -sdc_init_done: - -#ifdef DISABLE_PBM - LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ -#else - LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ -#endif /* DISABLE_PBM */ - -#ifdef CONFIG_TSI108EMU - oris r5,r5,0x0010 /* set EMULATION_MODE bit */ -#endif - - stw r5,SD_CTRL(r4) - eieio - sync - - /* Enable SDRAM access */ - - oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ - stw r5,SD_CTRL(r4) - sync - -wait_init_complete: - lwz r5,SD_STATUS(r4) - andi. r5,r5,0x0001 - /* wait until SDRAM initialization is complete */ - beq wait_init_complete - - /* Map SDRAM into the processor bus address space */ - - ori r4,r29,TSI108_PB_REG_OFFSET - - /* Setup BARs associated with direct path PB<->SDRAM */ - - /* PB_SDRAM_BAR1: - * provides a direct path to the main system memory (cacheable SDRAM) - */ - - /* BA=0,Size=512MB, ENable, No Addr.Translation */ - LOAD_U32(r5, 0x00000011) - stw r5,PB_SDRAM_BAR1(r4) - sync - - /* Make sure that PB_SDRAM_BAR1 decoder is set - * (to allow following immediate read from SDRAM) - */ - lwz r5,PB_SDRAM_BAR1(r4) - sync - - /* PB_SDRAM_BAR2: - * provides non-cacheable alias (via the direct path) to main - * system memory. - * Size = 512MB, ENable, Addr.Translation - ON, - * BA = 0x0_40000000, TA = 0x0_00000000 - */ - - LOAD_U32(r5, 0x40010011) - stw r5,PB_SDRAM_BAR2(r4) - sync - - /* Make sure that PB_SDRAM_BAR2 decoder is set - * (to allow following immediate read from SDRAM) - */ - lwz r5,PB_SDRAM_BAR2(r4) - sync - -init_done: - - /* All done. Restore LR and return. */ - mtlr r19 - blr - -#if (0) - /* - * init_cpu1 - * This routine enables CPU1 on the dual-processor system. - * Now there is only one processor in the system - */ - - .global enable_cpu1 -enable_cpu1: - - lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ - addi r3,r3,Tsi108_Base@l - lwz r3,0(r3) /* R3 = CSR Base Addr */ - ori r4,r3,TSI108_PB_REG_OFFSET - lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ - ori r3,r3,0x0200 /* Set M1_EN bit */ - stw r3,PB_ARB_CTRL(r4) - - blr -#endif - - /* - * enable_EI - * Enable CPU core external interrupt - */ - - .global enable_EI -enable_EI: - mfmsr r3 - ori r3,r3,0x8000 /* set EE bit */ - mtmsr r3 - blr - - /* - * disable_EI - * Disable CPU core external interrupt - */ - - .global disable_EI -disable_EI: - mfmsr r3 - li r4,-32768 /* aka "li r4,0x8000" */ - andc r3,r3,r4 /* clear EE bit */ - mtmsr r3 - blr - -#ifdef ENABLE_SDRAM_ECC - /* enables SDRAM ECC */ - - .global enable_ECC -enable_ECC: - ori r4,r29,TSI108_SD_REG_OFFSET - lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ - ori r3,r3,0x0001 /* Set ECC_EN bit */ - stw r3,SD_ECC_CTRL(r4) - blr - - /* - * clear_ECC_err - * Clears all pending SDRAM ECC errors - * (normally after SDRAM scrubbing/initialization) - */ - - .global clear_ECC_err -clear_ECC_err: - ori r4,r29,TSI108_SD_REG_OFFSET - ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ - stw r3,SD_INT_STATUS(r4) - blr - -#endif /* ENABLE_SDRAM_ECC */ - -#ifndef SDC_HARDCODED_INIT - - /* SDRAM SPD Support */ -#define SD_I2C_CTRL1 (0x400) -#define SD_I2C_CTRL2 (0x404) -#define SD_I2C_RD_DATA (0x408) -#define SD_I2C_WR_DATA (0x40C) - - /* - * SDRAM SPD Support Macros - */ - -#define SPD_DIMM0 (0x00000100) -#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ - -#define SPD_RDIMM (0x01) -#define SPD_UDIMM (0x02) - -#define SPD_CAS_3 0x8 -#define SPD_CAS_4 0x10 -#define SPD_CAS_5 0x20 - -#define ERR_NO_DIMM_FOUND (0xdb0) -#define ERR_TRAS_FAIL (0xdb1) -#define ERR_TRCD_FAIL (0xdb2) -#define ERR_TRP_FAIL (0xdb3) -#define ERR_TWR_FAIL (0xdb4) -#define ERR_UNKNOWN_PART (0xdb5) -#define ERR_NRANK_INVALID (0xdb6) -#define ERR_DIMM_SIZE (0xdb7) -#define ERR_ADDR_MODE (0xdb8) -#define ERR_RFRSH_RATE (0xdb9) -#define ERR_DIMM_TYPE (0xdba) -#define ERR_CL_VALUE (0xdbb) -#define ERR_TRFC_FAIL (0xdbc) - -/* READ_SPD requirements: - * byte - byte address in SPD device (0 - 255) - * r3 = will return data read from I2C Byte location - * r4 - unchanged (SDC base addr) - * r5 - clobbered in routine (I2C status) - * r10 - number of DDR slot where first SPD device is detected - */ - -#define READ_SPD(byte_num) \ - addis r3, 0, byte_num@l; \ - or r3, r3, r10; \ - ori r3, r3, 0x0A; \ - stw r3, SD_I2C_CTRL1(r4); \ - li r3, I2C_CNTRL2_START; \ - stw r3, SD_I2C_CTRL2(r4); \ - eieio; \ - sync; \ - li r3, 0x100; \ -1:; \ - addic. r3, r3, -1; \ - bne 1b; \ -2:; \ - lwz r5, SD_I2C_CTRL2(r4); \ - rlwinm. r3,r5,0,23,23; \ - bne 2b; \ - rlwinm. r3,r5,0,3,3; \ - lwz r3,SD_I2C_RD_DATA(r4) - -#define SPD_MIN_RFRSH (0x80) -#define SPD_MAX_RFRSH (0x85) - -refresh_rates: /* in nSec */ - .long 15625 /* Normal (0x80) */ - .long 3900 /* Reduced 0.25x (0x81) */ - .long 7800 /* Reduced 0.5x (0x82) */ - .long 31300 /* Extended 2x (0x83) */ - .long 62500 /* Extended 4x (0x84) */ - .long 125000 /* Extended 8x (0x85) */ - -/* - * tsi108_sdram_spd - * - * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data - * Uses registers: r4 - SDC base address (not changed) - * r9 - SDC clocking period in nSec - * Changes registers: r3,r5,r6,r7,r8,r10,r11 - */ - -tsi108_sdram_spd: - - li r10,SPD_DIMM0 - xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ - -do_first_dimm: - - /* Program Refresh Rate Register */ - - READ_SPD(12) /* get Refresh Rate */ - beq check_next_slot - li r5, ERR_RFRSH_RATE - cmpi 0,0,r3,SPD_MIN_RFRSH - ble spd_fail - cmpi 0,0,r3,SPD_MAX_RFRSH - bgt spd_fail - addi r3,r3,-SPD_MIN_RFRSH - rlwinm r3,r3,2,0,31 - lis r5,refresh_rates@h - ori r5,r5,refresh_rates@l - lwzx r5,r5,r3 /* get refresh rate in nSec */ - divwu r5,r5,r9 /* calculate # of SDC clocks */ - stw r5,SD_REFRESH(r4) /* Set refresh rate */ - sync - - /* Program SD Timing Register */ - - li r7, 0 /* clear r7 prior parameter collection */ - - READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ - beq spd_read_fail - li r5, ERR_DIMM_TYPE - cmpi 0,0,r3,SPD_UDIMM - beq do_cl - cmpi 0,0,r3,SPD_RDIMM - bne spd_fail - oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ - -do_cl: - READ_SPD(18) /* Get CAS Latency */ - beq spd_read_fail - li r5,ERR_CL_VALUE - andi. r6,r3,SPD_CAS_3 - beq cl_4 - li r6,3 - b set_cl -cl_4: - andi. r6,r3,SPD_CAS_4 - beq cl_5 - li r6,4 - b set_cl -cl_5: - andi. r6,r3,SPD_CAS_5 - beq spd_fail - li r6,5 -set_cl: - rlwimi r7,r6,24,5,7 - - READ_SPD(30) /* Get tRAS */ - beq spd_read_fail - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_tras - addi r6,r6,1 -set_tras: - li r5,ERR_TRAS_FAIL - cmpi 0,0,r6,0x0F /* max supported value */ - bgt spd_fail - rlwimi r7,r6,16,12,15 - - READ_SPD(29) /* Get tRCD */ - beq spd_read_fail - /* right shift tRCD by 2 bits as per DDR2 spec */ - rlwinm r3,r3,30,2,31 - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_trcd - addi r6,r6,1 -set_trcd: - li r5,ERR_TRCD_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,12,17,19 - - READ_SPD(27) /* Get tRP value */ - beq spd_read_fail - rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_trp - addi r6,r6,1 -set_trp: - li r5,ERR_TRP_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,8,21,23 - - READ_SPD(36) /* Get tWR value */ - beq spd_read_fail - rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_twr - addi r6,r6,1 -set_twr: - addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ - li r5,ERR_TWR_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,5,24,26 - - READ_SPD(42) /* Get tRFC */ - beq spd_read_fail - li r5, ERR_TRFC_FAIL - /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ - addi r3,r3,1 - rlwinm. r3,r3,31,1,31 /* divide by 2 */ - beq spd_fail - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 - beq set_trfc - addi r6,r6,1 -set_trfc: - cmpi 0,0,r6,0x1F /* max supported value */ - bgt spd_fail - rlwimi r7,r6,0,27,31 - - stw r7,SD_TIMING(r4) - sync - - /* - * The following two registers are set on per-DIMM basis. - * The SD_REFRESH and SD_TIMING settings are common for both DIMMS - */ - -do_each_dimm: - - /* Program SDRAM DIMM Control Register */ - - li r7, 0 /* clear r7 prior parameter collection */ - - READ_SPD(13) /* Get Primary SDRAM Width */ - beq spd_read_fail - cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ - beq do_nbank - oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ - -do_nbank: - READ_SPD(17) /* Get Number of banks on SDRAM device */ - beq spd_read_fail - /* Grendel only distinguish betw. 4 or 8-bank memory parts */ - li r5,ERR_UNKNOWN_PART /* non-supported memory part */ - cmpi 0,0,r3,4 - beq do_nrank - cmpi 0,0,r3,8 - bne spd_fail - ori r7,r7,0x1000 - -do_nrank: - READ_SPD(5) /* Get # of Ranks */ - beq spd_read_fail - li r5,ERR_NRANK_INVALID - andi. r6,r3,0x7 /* Use bits [2..0] only */ - beq do_addr_mode - cmpi 0,0,r6,1 - bgt spd_fail - rlwimi r7,r6,8,23,23 - -do_addr_mode: - READ_SPD(4) /* Get # of Column Addresses */ - beq spd_read_fail - li r5, ERR_ADDR_MODE - andi. r3,r3,0x0f /* cut off reserved bits */ - cmpi 0,0,r3,8 - ble spd_fail - cmpi 0,0,r3,15 - bgt spd_fail - addi r6,r3,-8 /* calculate ADDR_MODE parameter */ - rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ - -set_dimm_ctrl: -#ifdef SDC_AUTOPRECH_EN - oris r7,r7,0x0001 /* set auto precharge EN bit */ -#endif - ori r7,r7,1 /* set ENABLE bit */ - cmpi 0,0,r10,SPD_DIMM0 - bne 1f - stw r7,SD_D0_CTRL(r4) - sync - b set_dimm_bar -1: - stw r7,SD_D1_CTRL(r4) - sync - - - /* Program SDRAM DIMMx Base Address Register */ - -set_dimm_bar: - READ_SPD(5) /* get # of Ranks */ - beq spd_read_fail - andi. r7,r3,0x7 - addi r7,r7,1 - READ_SPD(31) /* Read DIMM rank density */ - beq spd_read_fail - rlwinm r5,r3,27,29,31 - rlwinm r6,r3,3,24,28 - or r5,r6,r5 /* r5 = Normalized Rank Density byte */ - lis r8, 0x0080 /* 128MB >> 4 */ - mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ - mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ - neg r7,r8 - rlwinm r7,r7,28,4,31 - or r7,r7,r11 /* set ADDR field */ - rlwinm r8,r8,12,20,31 - add r11,r11,r8 /* set Base Addr for next DIMM */ - - cmpi 0,0,r10,SPD_DIMM0 - bne set_dimm1_size - stw r7,SD_D0_BAR(r4) - sync - li r10,SPD_DIMM1 - READ_SPD(0) - bne do_each_dimm - b spd_done - -set_dimm1_size: - stw r7,SD_D1_BAR(r4) - sync -spd_done: - blr - -check_next_slot: - cmpi 0,0,r10,SPD_DIMM1 - beq spd_read_fail - li r10,SPD_DIMM1 - b do_first_dimm -spd_read_fail: - ori r3,r0,0xdead - b err_hung -spd_fail: - li r3,0x0bad - sync -err_hung: /* hang here for debugging */ - nop - nop - b err_hung - -#endif /* !SDC_HARDCODED_INIT */ diff --git a/board/freescale/mpc7448hpc2/config.mk b/board/freescale/mpc7448hpc2/config.mk deleted file mode 100644 index b2d6f7695e..0000000000 --- a/board/freescale/mpc7448hpc2/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2005 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c deleted file mode 100644 index 71b760c4a9..0000000000 --- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2005 Freescale Semiconductor, Inc. - * - * Roy Zang - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the Tsi108 Emul Board by avb@Tundra - */ - -/* - * board support/init functions for the - * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform). - */ - -#include -#include <74xx_7xx.h> -#include -#include - -#undef DEBUG - -DECLARE_GLOBAL_DATA_PTR; - -extern void tsi108_init_f (void); - -int display_mem_map (void); - -void after_reloc (ulong dest_addr) -{ - /* - * Jump to the main U-Boot board init code - */ - board_init_r ((gd_t *) gd, dest_addr); - /* NOTREACHED */ -} - -/* - * Check Board Identity: - * report board type - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); - return (l_type); -} - -/* - * Read Processor ID: - * - * report calling processor number - */ - -int read_pid (void) -{ - return 0; /* we are on single CPU platform for a while */ -} - -long int dram_size (int board_type) -{ - return 0x20000000; /* 256M bytes */ -} - -phys_size_t initdram (int board_type) -{ - return dram_size (board_type); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#if defined(CONFIG_TSI108_ETH) - rc = tsi108_eth_initialize(bis); -#endif - return rc; -} diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c deleted file mode 100644 index 9a1e4075bd..0000000000 --- a/board/freescale/mpc7448hpc2/tsi108_init.c +++ /dev/null @@ -1,652 +0,0 @@ -/***************************************************************************** - * (C) Copyright 2003; Tundra Semiconductor Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - *****************************************************************************/ - -/*---------------------------------------------------------------------------- - * FILENAME: tsi108_init.c - * - * Originator: Alex Bounine - * - * DESCRIPTION: - * Initialization code for the Tundra Tsi108 bridge chip - *---------------------------------------------------------------------------*/ - -#include -#include <74xx_7xx.h> -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern void mpicInit (int verbose); - -/* - * Configuration Options - */ - -typedef struct { - ulong upper; - ulong lower; -} PB2OCN_LUT_ENTRY; - -PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = { - /* 0 - 7 */ - {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */ - - /* 8 - 15 */ - {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */ - - /* 16 - 23 */ - {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */ - /* 24 - 31 */ - {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */ - {0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap + Translate) */ - {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */ - - {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */ - {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */ - {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */ - {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/ -}; - -#ifdef CONFIG_SYS_CLK_SPREAD -typedef struct { - ulong ctrl0; - ulong ctrl1; -} PLL_CTRL_SET; - -/* - * Clock Generator SPLL0 initialization values - * PLL0 configuration table for various PB_CLKO freq. - * Uses pre-calculated values for Fs = 30 kHz, D = 0.5% - * Fout depends on required PB_CLKO. Based on Fref = 33 MHz - */ - -static PLL_CTRL_SET pll0_config[8] = { - {0x00000000, 0x00000000}, /* 0: bypass */ - {0x00000000, 0x00000000}, /* 1: reserved */ - {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */ - {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */ - {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */ - {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */ - {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */ - {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */ -}; -#endif /* CONFIG_SYS_CLK_SPREAD */ - -/* - * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT - * (based on recommended Tsi108 reference clock 33MHz) - */ -static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 }; - -/* - * get_board_bus_clk () - * - * returns the bus clock in Hz. - */ -unsigned long get_board_bus_clk (void) -{ - ulong i; - - /* Detect PB clock freq. */ - i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); - i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ - - return pb_clk_sel[i] * 1000000; -} - -/* - * board_early_init_f () - * - * board-specific initialization executed from flash - */ - -int board_early_init_f (void) -{ - ulong i; - - gd->mem_clk = 0; - i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + - CG_PWRUP_STATUS); - i = (i >> 20) & 0x07; /* Get GD PLL multiplier */ - switch (i) { - case 0: /* external clock */ - printf ("Using external clock\n"); - break; - case 1: /* system clock */ - gd->mem_clk = gd->bus_clk; - break; - case 4: /* 133 MHz */ - case 5: /* 166 MHz */ - case 6: /* 200 MHz */ - gd->mem_clk = pb_clk_sel[i] * 1000000; - break; - default: - printf ("Invalid DDR2 clock setting\n"); - return -1; - } - printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000); - printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000); - return 0; -} - -/* - * board_early_init_r() - Tsi108 initialization function executed right after - * relocation. Contains code that cannot be executed from flash. - */ - -int board_early_init_r (void) -{ - ulong temp, i; - ulong reg_val; - volatile ulong *reg_ptr; - - reg_ptr = - (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); - - for (i = 0; i < 32; i++) { - *reg_ptr++ = 0x00000201; /* SWAP ENABLED */ - *reg_ptr++ = 0x00; - } - - __asm__ __volatile__ ("eieio"); - __asm__ __volatile__ ("sync"); - - /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, - 0x80000001); - __asm__ __volatile__ ("sync"); - - /* Make sure that OCN_BAR2 decoder is set (to allow following immediate - * read from SDRAM) - */ - - temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); - __asm__ __volatile__ ("sync"); - - /* - * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the - * processor bus address space. Immediately after reset LUT and address - * translation are disabled for this BAR. Now we have to initialize LUT - * and switch from the BOOT mode to the normal operation mode. - * - * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000 - * and covers 512MB of address space. To allow larger aperture we also - * have to relocate register window of Tsi108 - * - * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT - * mode. - * - * initialize pointer to LUT associated with PB_OCN_BAR1 - */ - reg_ptr = - (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); - - for (i = 0; i < 32; i++) { - *reg_ptr++ = pb2ocn_lut1[i].lower; - *reg_ptr++ = pb2ocn_lut1[i].upper; - } - - __asm__ __volatile__ ("sync"); - - /* Base addresses for CS0, CS1, CS2, CS3 */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, - 0x00000000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, - 0x00100000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, - 0x00200000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, - 0x00300000); - __asm__ __volatile__ ("sync"); - - /* Masks for HLP banks */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, - 0xFFF00000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, - 0xFFF00000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, - 0xFFF00000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, - 0xFFF00000); - __asm__ __volatile__ ("sync"); - - /* Set CTRL0 values for banks */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, - 0x7FFC44C2); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, - 0x7FFC44C0); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, - 0x7FFC44C0); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, - 0x7FFC44C2); - __asm__ __volatile__ ("sync"); - - /* Set banks to latched mode, enabled, and other default settings */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, - 0x7C0F2000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, - 0x7C0F2000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, - 0x7C0F2000); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, - 0x7C0F2000); - __asm__ __volatile__ ("sync"); - - /* - * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. - * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) - */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, - 0xE0000011); - __asm__ __volatile__ ("sync"); - - /* Make sure that OCN_BAR2 decoder is set (to allow following - * immediate read from SDRAM) - */ - - temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); - __asm__ __volatile__ ("sync"); - - /* - * SRI: At this point we have enabled the HLP banks. That means we can - * now read from the NVRAM and initialize the environment variables. - * We will over-ride the env_init called in board_init_f - * This is really a work-around because, the HLP bank 1 - * where NVRAM resides is not visible during board_init_f - * (arch/powerpc/lib/board.c) - * Alternatively, we could use the I2C EEPROM at start-up to configure - * and enable all HLP banks and not just HLP 0 as is being done for - * Taiga Rev. 2. - */ - - env_init (); - -#ifndef DISABLE_PBM - - /* - * For IBM processors we have to set Address-Only commands generated - * by PBM that are different from ones set after reset. - */ - - temp = get_cpu_type (); - - if ((CPU_750FX == temp) || (CPU_750GX == temp)) - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, - 0x00009955); -#endif /* DISABLE_PBM */ - -#ifdef CONFIG_PCI - /* - * Initialize PCI/X block - */ - - /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + - PCI_PFAB_BAR0_UPPER, 0); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, - 0xFB000001); - __asm__ __volatile__ ("sync"); - - /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ - - temp = in32(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); - - temp &= ~0xFF00; /* Clear the BUS_NUM field */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, - temp); - - /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, - 0); - __asm__ __volatile__ ("sync"); - - /* This register is on the PCI side to interpret the address it receives - * and maps it as a IO address. - */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, - 0x00000001); - __asm__ __volatile__ ("sync"); - - /* - * Map PCI/X Memory Space - * - * Transactions directed from OCM to PCI Memory Space are directed - * from PB to PCI - * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings). - * If address remapping is required the corresponding PCI_PFAB_MEM32 - * and PCI_PFAB_PFMx register groups have to be configured. - * - * Map the path from the PCI/X bus into the system memory - * - * The memory mapped window assotiated with PCI P2O_BAR2 provides - * access to the system memory without address remapping. - * All system memory is opened for accesses initiated by PCI/X bus - * masters. - * - * Initialize LUT associated with PCI P2O_BAR2 - * - * set pointer to LUT associated with PCI P2O_BAR2 - */ - - reg_ptr = - (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); - -#ifdef DISABLE_PBM - - /* In case when PBM is disabled (no HW supported cache snoopng on PB) - * P2O_BAR2 is directly mapped into the system memory without address - * translation. - */ - - reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */ - - for (i = 0; i < 32; i++) { - *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ - *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */ - } - - /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */ - reg_val = 0x00007500; -#else - - reg_val = 0x00000002; /* Destination port = PBM */ - - for (i = 0; i < 32; i++) { - *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ -/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ - *reg_ptr++ = 0x40000000; -/* offset = 16MB, address translation is enabled to allow byte swapping */ - reg_val += 0x01000000; - } - -/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */ - reg_val = 0x00007100; -#endif - - __asm__ __volatile__ ("eieio"); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, - reg_val); - __asm__ __volatile__ ("sync"); - - /* Set 64-bit PCI bus address for system memory - * ( 0 is the best choice for easy mapping) - */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, - 0x00000000); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, - 0x00000000); - __asm__ __volatile__ ("sync"); - -#ifndef DISABLE_PBM - /* - * The memory mapped window assotiated with PCI P2O_BAR3 provides - * access to the system memory using SDRAM OCN port and address - * translation. This is alternative way to access SDRAM from PCI - * required for Tsi108 emulation testing. - * All system memory is opened for accesses initiated by - * PCI/X bus masters. - * - * Initialize LUT associated with PCI P2O_BAR3 - * - * set pointer to LUT associated with PCI P2O_BAR3 - */ - reg_ptr = - (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); - - reg_val = 0x00000004; /* Destination port = SDC */ - - for (i = 0; i < 32; i++) { - *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */ - -/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ - *reg_ptr++ = 0; - -/* offset = 16MB, address translation is enabled to allow byte swapping */ - reg_val += 0x01000000; - } - - __asm__ __volatile__ ("eieio"); - __asm__ __volatile__ ("sync"); - - /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */ - - reg_val = - in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + - PCI_P2O_PAGE_SIZES); - reg_val &= ~0x00FF; - reg_val |= 0x0071; - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, - reg_val); - __asm__ __volatile__ ("sync"); - - /* Set 64-bit base PCI bus address for window (0x20000000) */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, - 0x00000000); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, - 0x20000000); - __asm__ __volatile__ ("sync"); - -#endif /* !DISABLE_PBM */ - -#ifdef ENABLE_PCI_CSR_BAR - /* open if required access to Tsi108 CSRs from the PCI/X bus */ - /* enable BAR0 on the PCI/X bus */ - reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); - reg_val |= 0x02; - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, - reg_val); - __asm__ __volatile__ ("sync"); - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, - 0x00000000); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, - CONFIG_SYS_TSI108_CSR_BASE); - __asm__ __volatile__ ("sync"); - -#endif - - /* - * Finally enable PCI/X Bus Master and Memory Space access - */ - - reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); - reg_val |= 0x06; - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); - __asm__ __volatile__ ("sync"); - -#endif /* CONFIG_PCI */ - - /* - * Initialize MPIC outputs (interrupt pins): - * Interrupt routing on the Grendel Emul. Board: - * PB_INT[0] -> INT (CPU0) - * PB_INT[1] -> INT (CPU1) - * PB_INT[2] -> MCP (CPU0) - * PB_INT[3] -> MCP (CPU1) - * Set interrupt controller outputs as Level_Sensitive/Active_Low - */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); - __asm__ __volatile__ ("sync"); - - /* - * Ensure that Machine Check exception is enabled - * We need it to support PCI Bus probing (configuration reads) - */ - - reg_val = mfmsr (); - mtmsr(reg_val | MSR_ME); - - return 0; -} - -/* - * Needed to print out L2 cache info - * used in the misc_init_r function - */ - -unsigned long get_l2cr (void) -{ - unsigned long l2controlreg; - asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):); - return l2controlreg; -} - -/* - * misc_init_r() - * - * various things to do after relocation - * - */ - -int misc_init_r (void) -{ -#ifdef CONFIG_SYS_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ - ulong i; - - /* Ensure that Spread-Spectrum is disabled */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); - - /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK - * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% - */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, - 0x002e0044); /* D = 0.25% */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, - 0x00000039); /* BWADJ */ - - /* Initialize PLL0: CG_PB_CLKO */ - /* Detect PB clock freq. */ - i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); - i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ - - out32 (CONFIG_SYS_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); - out32 (CONFIG_SYS_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); - - /* Wait and set SSEN for both PLL0 and 1 */ - udelay (1000); - out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, - 0x802e0044); /* D=0.25% */ - out32 (CONFIG_SYS_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, - 0x80000000 | pll0_config[i].ctrl0); -#endif /* CONFIG_SYS_CLK_SPREAD */ - -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif - printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000); - printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000); - - /* - * All the information needed to print the cache details is avaiblable - * at this point i.e. above call to l2cache_enable is the very last - * thing done with regards to enabling diabling the cache. - * So this seems like a good place to print all this information - */ - - printf ("CACHE: "); - switch (get_cpu_type()) { - case CPU_7447A: - printf ("L1 Instruction cache - 32KB 8-way"); - (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("L1 Data cache - 32KB 8-way"); - (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("Unified L2 cache - 512KB 8-way"); - (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("\n"); - break; - - case CPU_7448: - printf ("L1 Instruction cache - 32KB 8-way"); - (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("L1 Data cache - 32KB 8-way"); - (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - printf ("Unified L2 cache - 1MB 8-way"); - (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : - printf (" DISABLED\n"); - break; - default: - break; - } - return 0; -} diff --git a/board/freescale/mpc8260ads/Makefile b/board/freescale/mpc8260ads/Makefile deleted file mode 100644 index c91b0886f2..0000000000 --- a/board/freescale/mpc8260ads/Makefile +++ /dev/null @@ -1,29 +0,0 @@ - -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c deleted file mode 100644 index 4012d45868..0000000000 --- a/board/freescale/mpc8260ads/flash.c +++ /dev/null @@ -1,476 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * (C) Copyright 2003 Arabella Software Ltd. - * Yuli Barcohen - * Re-written to support multi-bank flash SIMMs. - * Added support for real protection and JFFS2. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x89898989 -#define INTEL_ALT 0xB0B0B0B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x10101010 -#define INTEL_ERASE 0x20202020 -#define INTEL_CLEAR 0x50505050 -#define INTEL_LOCKBIT 0x60606060 -#define INTEL_PROTECT 0x01010101 -#define INTEL_STATUS 0x70707070 -#define INTEL_READID 0x90909090 -#define INTEL_CONFIRM 0xD0D0D0D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x80808080 -#define INTEL_OK 0x80808080 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.) - * Up to 32MB of flash supported (up to 4 banks.) - * BCSR is used for flash presence detect (page 4-65 of the User's Manual) - * - * The following code can not run from flash! - */ -unsigned long flash_init (void) -{ - ulong size = 0, sect_start, sect_size = 0, bank_size; - ushort sect_count = 0; - int i, j, nbanks; - vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE; - vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; - - switch (bcsr[2] & 0xF) { - case 0: - nbanks = 4; - break; - case 1: - nbanks = 2; - break; - case 2: - nbanks = 1; - break; - default: /* Unsupported configurations */ - nbanks = CONFIG_SYS_MAX_FLASH_BANKS; - } - - if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS) - nbanks = CONFIG_SYS_MAX_FLASH_BANKS; - - for (i = 0; i < nbanks; i++) { - *addr = INTEL_READID; /* Read Intelligent Identifier */ - if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) { - switch (addr[1]) { - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - sect_count = 32; - sect_size = 0x40000; - break; - default: - flash_info[i].flash_id = FLASH_UNKNOWN; - sect_count = CONFIG_SYS_MAX_FLASH_SECT; - sect_size = - CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT; - } - } - else - flash_info[i].flash_id = FLASH_UNKNOWN; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n", - addr[0], addr[1], (ulong)addr); - size = 0; - *addr = INTEL_RESET; /* Reset bank to Read Array mode */ - break; - } - flash_info[i].sector_count = sect_count; - flash_info[i].size = bank_size = sect_size * sect_count; - size += bank_size; - sect_start = (ulong)addr; - for (j = 0; j < sect_count; j++) { - addr = (vu_long *)sect_start; - flash_info[i].start[j] = sect_start; - flash_info[i].protect[j] = (addr[2] == 0x01010101); - sect_start += sect_size; - } - *addr = INTEL_RESET; /* Reset bank to Read Array mode */ - addr = (vu_long *)sect_start; - } - - if (size == 0) { /* Unknown flash, fill with hard-coded values */ - sect_start = CONFIG_SYS_FLASH_BASE; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS; - flash_info[i].sector_count = sect_count; - for (j = 0; j < sect_count; j++) { - flash_info[i].start[j] = sect_start; - flash_info[i].protect[j] = 0; - sect_start += sect_size; - } - } - size = CONFIG_SYS_FLASH_SIZE; - } - else - for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - flash_info[i].sector_count = 0; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Clear Status Register */ - *addr = INTEL_CLEAR; - /* Single Block Erase Command */ - *addr = INTEL_ERASE; - /* Confirm */ - *addr = INTEL_CONFIRM; - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = INTEL_CONFIRM; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = INTEL_RESET; /* reset bank */ - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - if (*addr != INTEL_OK) { - printf("Block erase failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - *addr = INTEL_RESET; /* reset bank */ - return 1; - } - - /* reset to read mode */ - *addr = INTEL_RESET; - } - } - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - ulong start; - int rc = 0; - int flag; - vu_long *addr = (vu_long *)dest; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - - *addr = INTEL_CLEAR; /* Clear status register */ - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = INTEL_PROGRAM; - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - printf("Write timed out\n"); - rc = 1; - break; - } - } - if (*addr != INTEL_OK) { - printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr); - rc = 1; - } - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - rc = write_word(info, wp, data); - - return rc; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - ulong start; - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer(0); - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) - for (i = 0; i < info->sector_count; i++) - if (info->protect[i]) { - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000); - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c deleted file mode 100644 index b8c8ce9603..0000000000 --- a/board/freescale/mpc8260ads/mpc8260ads.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified during 2001 by - * Advanced Communications Technologies (Australia) Pty. Ltd. - * Howard Walker, Tuong Vu-Dinh - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Added support for the 16M dram simm on the 8260ads boards - * - * (C) Copyright 2003-2004 Arabella Software Ltd. - * Yuli Barcohen - * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init. - * - * Copyright (c) 2005 MontaVista Software, Inc. - * Vitaly Bordug - * Added support for PCI. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#endif -#ifdef CONFIG_OF_LIBFDT -#include -#include -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) -#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */ - /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */ - /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */ -#else - /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ - /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ -#else - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -void reset_phy (void) -{ - vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; - - /* Reset the PHY */ -#if CONFIG_SYS_PHY_ADDR == 0 - bcsr[1] &= ~(FETHIEN1 | FETH1_RST); - udelay(2); - bcsr[1] |= FETH1_RST; -#else - bcsr[3] &= ~(FETHIEN2 | FETH2_RST); - udelay(2); - bcsr[3] |= FETH2_RST; -#endif /* CONFIG_SYS_PHY_ADDR == 0 */ - udelay(1000); -#ifdef CONFIG_MII -#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS - /* - * Do not bypass Rx/Tx (de)scrambler (fix configuration error) - * Enable autonegotiation. - */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610); - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#else - /* - * Ethernet PHY is configured (by means of configuration pins) - * to work at 10Mb/s only. We reconfigure it using MII - * to advertise all capabilities, including 100Mb/s, and - * restart autonegotiation. - */ - - /* Advertise all capabilities */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1); - - /* Do not bypass Rx/Tx (de)scrambler */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER, 0x0000); - - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ -#endif /* CONFIG_MII */ -} - -#ifdef CONFIG_PCI -typedef struct pci_ic_s { - unsigned long pci_int_stat; - unsigned long pci_int_mask; -}pci_ic_t; -#endif - -int board_early_init_f (void) -{ - vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; - -#ifdef CONFIG_PCI - volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT; - - /* mask alll the PCI interrupts */ - pci_ic->pci_int_mask |= 0xfff00000; -#endif -#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1) - bcsr[1] &= ~RS232EN_1; -#endif -#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1) - bcsr[1] &= ~RS232EN_2; -#endif - -#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */ -#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS - if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */ -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ - { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; - } -#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */ - - return 0; -} - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) - -phys_size_t initdram (int board_type) -{ -#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS - long int msize = 32; -#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - long int msize = 64; -#else - long int msize = 16; -#endif - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *ramaddr, c = 0xff; - uint or; - uint psdmr; - uint psrt; - - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x00000002; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifdef CONFIG_SYS_LSDRAM_BASE - /* - Initialise local bus SDRAM only if the pins - are configured as local bus pins and not as PCI. - The configuration is determined by the HRCW. - */ - if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { - memctl->memc_lsrt = CONFIG_SYS_LSRT; -#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */ - memctl->memc_or3 = 0xFF803280; - memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861; -#else /* CS4 */ - memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861; -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000; - ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE; - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000; - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000; - } -#endif /* CONFIG_SYS_LSDRAM_BASE */ - - /* Init 60x bus SDRAM */ -#ifdef CONFIG_SPD_EEPROM - { - spd_eeprom_t spd; - uint pbi, bsel, rowst, lsb, tmp; - - i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd)); - - /* Bank-based interleaving is not supported for physical bank - sizes greater than 128MB which is encoded as 0x20 in SPD - */ - pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI; - msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */ - or = ~(msize - 1) << 20; /* SDAM */ - switch (spd.nbanks) { /* BPD */ - case 2: - bsel = 1; - break; - case 4: - bsel = 2; - or |= 0x00002000; - break; - case 8: - bsel = 3; - or |= 0x00004000; - break; - } - lsb = 3; /* For 64-bit port, lsb is 3 bits */ - - if (pbi) { /* Bus partition depends on interleaving */ - rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb); - or |= (rowst << 9); /* ROWST */ - } else { - rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb); - or |= ((rowst * 2 - 12) << 9); /* ROWST */ - } - or |= ((spd.nrow_addr - 9) << 6); /* NUMR */ - - psdmr = (pbi << 31); /* PBI */ - /* Bus multiplexing parameters */ - tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */ - psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */ - psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */ - - tmp = (31 - lsb - 10) - tmp; - /* Pin connected to SDA10 is (31 - lsb - 10). - rowst is multiplexed over (32 - (lsb + spd.nrow_addr)), - so (rowst + tmp) alternates with AP. - */ - if (pbi) /* Table 10-7 */ - psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */ - else - psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */ - - /* SDRAM device-specific parameters */ - tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */ - switch (tmp) { /* RFRC */ - case 1: - case 2: - psdmr |= (1 << 15); - break; - case 3: - case 4: - case 5: - case 6: - case 7: - case 8: - psdmr |= ((tmp - 2) << 15); - break; - default: - psdmr |= (7 << 15); - } - psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */ - psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */ - /* BL=0 because for 64-bit SDRAM burst length must be 4 */ - /* LDOTOPRE ??? */ - for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++) - tmp >>= 1; - switch (i) { /* WRC */ - case 0: - case 1: - psdmr |= (1 << 4); - break; - case 2: - case 3: - psdmr |= (i << 4); - break; - } - /* EAMUX=0 - no external address multiplexing */ - /* BUFCMD=0 - no external buffers */ - for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++) - tmp >>= 1; - psdmr |= i; /* CL */ - - switch (spd.refresh & 0x7F) { - case 1: - tmp = 3900; - break; - case 2: - tmp = 7800; - break; - case 3: - tmp = 31300; - break; - case 4: - tmp = 62500; - break; - case 5: - tmp = 125000; - break; - default: - tmp = 15625; - } - psrt = tmp / (1000000000 / CONFIG_8260_CLKIN * - ((memctl->memc_mptpr >> 8) + 1)) - 1; -#ifdef SPD_DEBUG - printf ("\nDIMM type: %-18.18s\n", spd.mpart); - printf ("SPD size: %d\n", spd.info_size); - printf ("EEPROM size: %d\n", 1 << spd.chip_size); - printf ("Memory type: %d\n", spd.mem_type); - printf ("Row addr: %d\n", spd.nrow_addr); - printf ("Column addr: %d\n", spd.ncol_addr); - printf ("# of rows: %d\n", spd.nrows); - printf ("Row density: %d\n", spd.row_dens); - printf ("# of banks: %d\n", spd.nbanks); - printf ("Data width: %d\n", - 256 * spd.dataw_msb + spd.dataw_lsb); - printf ("Chip width: %d\n", spd.primw); - printf ("Refresh rate: %02X\n", spd.refresh); - printf ("CAS latencies: %02X\n", spd.cas_lat); - printf ("Write latencies: %02X\n", spd.write_lat); - printf ("tRP: %d\n", spd.trp); - printf ("tRCD: %d\n", spd.trcd); - - printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt); -#endif /* SPD_DEBUG */ - } -#else /* !CONFIG_SPD_EEPROM */ - or = CONFIG_SYS_OR2; - psdmr = CONFIG_SYS_PSDMR; - psrt = CONFIG_SYS_PSRT; -#endif /* CONFIG_SPD_EEPROM */ - memctl->memc_psrt = psrt; - memctl->memc_or2 = or; - memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041; - ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE; - memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */ - *ramaddr = c; -#endif /* CONFIG_SYS_RAMBOOT */ - - /* return total 60x bus SDRAM size */ - return (msize * 1024 * 1024); -} - -int checkboard (void) -{ -#if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS - puts ("Board: Motorola MPC8260ADS\n"); -#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS - puts ("Board: Motorola MPC8266ADS\n"); -#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS - puts ("Board: Motorola PQ2FADS-ZU\n"); -#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - puts ("Board: Motorola MPC8272ADS\n"); -#else - puts ("Board: unknown\n"); -#endif - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif diff --git a/board/freescale/mpc8266ads/Makefile b/board/freescale/mpc8266ads/Makefile deleted file mode 100644 index d1d2ecb11b..0000000000 --- a/board/freescale/mpc8266ads/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mpc8266ads/flash.c b/board/freescale/mpc8266ads/flash.c deleted file mode 100644 index ef281944a1..0000000000 --- a/board/freescale/mpc8266ads/flash.c +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -#ifndef CONFIG_MPC8266ADS - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; -#endif - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ -#ifndef CONFIG_MPC8266ADS - bcsr->bd_ctrl |= BD_CTRL_FLWE; -#endif - - - for (i=0; imemc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br1 & ~(BR_BA_MSK)); -#endif - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - - value = addr[0] & 0x00FF00FF; - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - - *addr = 0xFFFFFF; /* reset bank to read array mode */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - /* Clear Status Register */ - *addr = 0x50505050; - /* Single Block Erase Command */ - *addr = 0x20202020; - /* Confirm */ - *addr = 0xD0D0D0D0; - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x80808080) != 0x80808080) { - if(*addr & 0x20202020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - } - } - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & 0x80808080) != 0x80808080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - /* Clear Status Register */ - *addr = 0x50505050; - - *addr = 0x60606060; - *addr = 0xd0d0d0d0; - - start = get_timer (0); - while(*addr != 0x80808080){ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - } - return 0; -} diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c deleted file mode 100644 index 1eeec3f724..0000000000 --- a/board/freescale/mpc8266ads/mpc8266ads.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * (C) Copyright 2001-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified during 2001 by - * Advanced Communications Technologies (Australia) Pty. Ltd. - * Howard Walker, Tuong Vu-Dinh - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Added support for the 16M dram simm on the 8260ads boards - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * PBI Page Based Interleaving - * PSDMR_PBI page based interleaving - * 0 bank based interleaving - * External Address Multiplexing (EAMUX) adds a clock to address cycles - * (this can help with marginal board layouts) - * PSDMR_EAMUX adds a clock - * 0 no extra clock - * Buffer Command (BUFCMD) adds a clock to command cycles. - * PSDMR_BUFCMD adds a clock - * 0 no extra clock - */ -#define CONFIG_PBI 0 -#define PESSIMISTIC_SDRAM 0 -#define EAMUX 0 /* EST requires EAMUX */ -#define BUFCMD 0 - - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -typedef struct bscr_ { - unsigned long bcsr0; - unsigned long bcsr1; - unsigned long bcsr2; - unsigned long bcsr3; - unsigned long bcsr4; - unsigned long bcsr5; - unsigned long bcsr6; - unsigned long bcsr7; -} bcsr_t; - -typedef struct pci_ic_s { - unsigned long pci_int_stat; - unsigned long pci_int_mask; -} pci_ic_t; - -void reset_phy(void) -{ - volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; - - /* reset the FEC port */ - bcsr->bcsr1 &= ~FETH_RST; - bcsr->bcsr1 |= FETH_RST; -} - - -int board_early_init_f(void) -{ - volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; - volatile pci_ic_t *pci_ic = (pci_ic_t *)CONFIG_SYS_PCI_INT; - - bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; - - /* mask all PCI interrupts */ - pci_ic->pci_int_mask |= 0xfff00000; - - return 0; -} - -int checkboard(void) -{ - puts("Board: Motorola MPC8266ADS\n"); - return 0; -} - -phys_size_t initdram(int board_type) -{ - /* Autoinit part stolen from board/sacsng/sacsng.c */ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0xff; - volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - uint psrt = 0x21; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char data; - u_char cksum; - int j; - - /* - * Keep the compiler from complaining about - * potentially uninitialized vars - */ - data_width = rows = banks = cols = caslatency = 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - cksum = data; - for (j = 1; j < 64; j++) { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ - i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - /*printf("addr %d = 0x%02x\n", j, data); */ - if (j == 5) - chipselects = data & 0x0F; - else if (j == 6) - data_width = data; - else if (j == 7) - data_width |= data << 8; - else if (j == 3) - rows = data & 0x0F; - else if (j == 4) - cols = data & 0x0F; - else if (j == 12) { - /* - * Refresh rate: this assumes the prescaler is set to - * approximately 0.39uSec per tick and the target - * refresh period is about 85% of maximum. - */ - switch (data & 0x7F) { - default: - case 0: - psrt = 0x21; /* 15.625uS */ - break; - case 1: - psrt = 0x07; /* 3.9uS */ - break; - case 2: - psrt = 0x0F; /* 7.8uS */ - break; - case 3: - psrt = 0x43; /* 31.3uS */ - break; - case 4: - psrt = 0x87; /* 62.5uS */ - break; - case 5: - psrt = 0xFF; /* 125uS */ - break; - } - } else if (j == 17) - banks = data; - else if (j == 18) { - caslatency = 3; /* default CL */ -#if (PESSIMISTIC_SDRAM) - if ((data & 0x04) != 0) - caslatency = 3; - else if ((data & 0x02) != 0) - caslatency = 2; - else if ((data & 0x01) != 0) - caslatency = 1; -#else - if ((data & 0x01) != 0) - caslatency = 1; - else if ((data & 0x02) != 0) - caslatency = 2; - else if ((data & 0x04) != 0) - caslatency = 3; -#endif - else { - printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", - data); - } - } else if (j == 63) { - if (data != cksum) { - printf("WARNING: Configuration data checksum failure:" - " is 0x%02x, calculated 0x%02x\n", - data, cksum); - } - } - cksum += data; - } - - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if (caslatency < 2) { - printf("CL was %d, forcing to 2\n", caslatency); - caslatency = 2; - } - if (rows > 14) { - printf("This doesn't look good, rows = %d, should be <= 14\n", - rows); - rows = 14; - } - if (cols > 11) { - printf("This doesn't look good, columns = %d, should be <= 11\n", - cols); - cols = 11; - } - - if ((data_width != 64) && (data_width != 72)) { - printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", - data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) - banks = 1; - else if (banks == 4) - banks = 2; - else if (banks == 8) - banks = 3; - - - sdram_size = 1 << (rows + cols + banks + width); - /* hack for high density memory (512MB per CS) */ - /* !!!!! Will ONLY work with Page Based Interleave !!!!! - ( PSDMR[PBI] = 1 ) - */ - /* - * memory actually has 11 column addresses, but the memory - * controller doesn't really care. - * - * the calculations that follow will however move the rows so - * that they are muxed one bit off if you use 11 bit columns. - * - * The solution is to tell the memory controller the correct - * size of the memory but change the number of columns to 10 - * afterwards. - * - * The 11th column addre will still be mucxed correctly onto - * the bus. - * - * Also be aware that the MPC8266ADS board Rev B has not - * connected Row address 13 to anything. - * - * The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) - */ - if (cols > 10) - cols = 10; - -#if (CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; -#else - rowst = 32 - (rows + banks + cols + width); -#endif - - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks - 1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - - /*printf("memctl->memc_or2 = 0x%08x\n", or); */ - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if (CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; -#else - sdam = cols + banks - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; -#endif -#if (PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK | - PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C | - PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency | - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ - (sdam << 24) | (bsma << 21) | (sda10 << 18); -#else - psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK | - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX | BUFCMD) | caslatency | - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ - (sdam << 24) | (bsma << 21) | (sda10 << 18); -#endif - /*printf("psdmr = 0x%08x\n", psdmr); */ - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set - * when we get here. The SDRAM can be accessed at the address - * CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_or2 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if (chipselects > 1) { - ramaddr += sdram_size; - - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; - memctl->memc_or3 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - } - - /* print info */ - printf("SDRAM configuration read from SPD\n"); - printf("\tSize per side = %dMB\n", sdram_size >> 20); - printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", - chipselects, 1 << (banks), cols, rows, data_width); - printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency); -#if (CONFIG_PBI == 0) /* bank-based interleaving */ - printf(", Using Bank Based Interleave\n"); -#else - printf(", Using Page Based Interleave\n"); -#endif - printf("\tTotal size: "); - - /* this delay only needed for original 16MB DIMM... - * Not needed for any other memory configuration */ - if ((sdram_size * chipselects) == (16 * 1024 * 1024)) - udelay(250000); - - return sdram_size * chipselects; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/freescale/mpc8308rdb/Kconfig b/board/freescale/mpc8308rdb/Kconfig new file mode 100644 index 0000000000..48d25e5a26 --- /dev/null +++ b/board/freescale/mpc8308rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8308RDB + +config SYS_BOARD + default "mpc8308rdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8308RDB" + +endif diff --git a/board/freescale/mpc8308rdb/MAINTAINERS b/board/freescale/mpc8308rdb/MAINTAINERS new file mode 100644 index 0000000000..07ff2abd13 --- /dev/null +++ b/board/freescale/mpc8308rdb/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8308RDB BOARD +M: Ilya Yanok +S: Maintained +F: board/freescale/mpc8308rdb/ +F: include/configs/MPC8308RDB.h +F: configs/MPC8308RDB_defconfig diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile index 31127f082b..ec2b85d9cd 100644 --- a/board/freescale/mpc8308rdb/Makefile +++ b/board/freescale/mpc8308rdb/Makefile @@ -7,24 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o sdram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mpc8308rdb.o sdram.o diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c index fba41fe504..93e1c50f39 100644 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -161,11 +161,13 @@ int misc_init_r(void) return 0; } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); fdt_fixup_esdhc(blob, bd); + + return 0; } #endif diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig new file mode 100644 index 0000000000..145608feab --- /dev/null +++ b/board/freescale/mpc8313erdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8313ERDB + +config SYS_BOARD + default "mpc8313erdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8313ERDB" + +endif diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS new file mode 100644 index 0000000000..807fb0b6e9 --- /dev/null +++ b/board/freescale/mpc8313erdb/MAINTAINERS @@ -0,0 +1,9 @@ +MPC8313ERDB BOARD +#M: - +S: Maintained +F: board/freescale/mpc8313erdb/ +F: include/configs/MPC8313ERDB.h +F: configs/MPC8313ERDB_33_defconfig +F: configs/MPC8313ERDB_66_defconfig +F: configs/MPC8313ERDB_NAND_33_defconfig +F: configs/MPC8313ERDB_NAND_66_defconfig diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile index b9fa864bb5..77fad7574a 100644 --- a/board/freescale/mpc8313erdb/Makefile +++ b/board/freescale/mpc8313erdb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o sdram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mpc8313erdb.o sdram.o diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 591a4c61d0..eac193e817 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -116,12 +116,14 @@ int misc_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif #else /* CONFIG_SPL_BUILD */ @@ -129,12 +131,12 @@ void board_init_f(ulong bootflag) { board_early_init_f(); NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); puts("NAND boot... "); init_timebase(); initdram(0); relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, - CONFIG_SYS_NAND_U_BOOT_RELOC); + CONFIG_SYS_NAND_U_BOOT_RELOC); } void board_init_r(gd_t *gd, ulong dest_addr) diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig new file mode 100644 index 0000000000..f76b0d1d6d --- /dev/null +++ b/board/freescale/mpc8315erdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8315ERDB + +config SYS_BOARD + default "mpc8315erdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8315ERDB" + +endif diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS new file mode 100644 index 0000000000..938c1527e0 --- /dev/null +++ b/board/freescale/mpc8315erdb/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8315ERDB BOARD +M: Dave Liu +S: Maintained +F: board/freescale/mpc8315erdb/ +F: include/configs/MPC8315ERDB.h +F: configs/MPC8315ERDB_defconfig diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile index b9fa864bb5..fbb68c579d 100644 --- a/board/freescale/mpc8315erdb/Makefile +++ b/board/freescale/mpc8315erdb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o sdram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mpc8315erdb.o sdram.o diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index e6f091fd2f..ed611c56c3 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -188,7 +188,7 @@ void fdt_tsec1_fixup(void *fdt, bd_t *bd) do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI @@ -196,6 +196,8 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_dr_usb(blob, bd); fdt_tsec1_fixup(blob, bd); + + return 0; } #endif diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig new file mode 100644 index 0000000000..acf8122196 --- /dev/null +++ b/board/freescale/mpc8323erdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8323ERDB + +config SYS_BOARD + default "mpc8323erdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8323ERDB" + +endif diff --git a/board/freescale/mpc8323erdb/MAINTAINERS b/board/freescale/mpc8323erdb/MAINTAINERS new file mode 100644 index 0000000000..05057c0c2d --- /dev/null +++ b/board/freescale/mpc8323erdb/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8323ERDB BOARD +M: Michael Barkowski +S: Maintained +F: board/freescale/mpc8323erdb/ +F: include/configs/MPC8323ERDB.h +F: configs/MPC8323ERDB_defconfig diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile index ff0dbf869d..f2e7497210 100644 --- a/board/freescale/mpc8323erdb/Makefile +++ b/board/freescale/mpc8323erdb/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mpc8323erdb.o diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 3dce3623a4..0a0152ad9e 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -172,12 +172,14 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig new file mode 100644 index 0000000000..e4cfa15a6f --- /dev/null +++ b/board/freescale/mpc832xemds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC832XEMDS + +config SYS_BOARD + default "mpc832xemds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC832XEMDS" + +endif diff --git a/board/freescale/mpc832xemds/MAINTAINERS b/board/freescale/mpc832xemds/MAINTAINERS new file mode 100644 index 0000000000..56d70733b4 --- /dev/null +++ b/board/freescale/mpc832xemds/MAINTAINERS @@ -0,0 +1,10 @@ +MPC832XEMDS BOARD +M: Dave Liu +S: Maintained +F: board/freescale/mpc832xemds/ +F: include/configs/MPC832XEMDS.h +F: configs/MPC832XEMDS_defconfig +F: configs/MPC832XEMDS_ATM_defconfig +F: configs/MPC832XEMDS_HOST_33_defconfig +F: configs/MPC832XEMDS_HOST_66_defconfig +F: configs/MPC832XEMDS_SLAVE_defconfig diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile index 0c6e556a6d..66763519af 100644 --- a/board/freescale/mpc832xemds/Makefile +++ b/board/freescale/mpc832xemds/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc832xemds.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index b7ea0e44c3..adf425486e 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -154,11 +154,13 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig new file mode 100644 index 0000000000..51f0b34f39 --- /dev/null +++ b/board/freescale/mpc8349emds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8349EMDS + +config SYS_BOARD + default "mpc8349emds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8349EMDS" + +endif diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS new file mode 100644 index 0000000000..141e77a94e --- /dev/null +++ b/board/freescale/mpc8349emds/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8349EMDS BOARD +M: Kim Phillips +S: Maintained +F: board/freescale/mpc8349emds/ +F: include/configs/MPC8349EMDS.h +F: configs/MPC8349EMDS_defconfig diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile index 9549badce4..5c315f9f68 100644 --- a/board/freescale/mpc8349emds/Makefile +++ b/board/freescale/mpc8349emds/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_FSL_DDR2) += ddr.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8349emds.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c index c66750e2e3..aae003d121 100644 --- a/board/freescale/mpc8349emds/ddr.c +++ b/board/freescale/mpc8349emds/ddr.c @@ -6,8 +6,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; @@ -15,7 +15,7 @@ struct board_specific_parameters { u32 clk_adjust; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -70,7 +70,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -86,7 +86,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp_highest->clk_adjust; popts->cpo_override = pbsp_highest->cpo; popts->write_data_delay = pbsp_highest->write_data_delay; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -97,5 +97,5 @@ found: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; - popts->DQS_config = 0; /* only true DQS signal is used on board */ + popts->dqs_config = 0; /* only true DQS signal is used on board */ } diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index ec48487294..02b5040ef4 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -12,8 +12,8 @@ #include #include #include -#ifdef CONFIG_FSL_DDR2 -#include +#ifdef CONFIG_SYS_FSL_DDR2 +#include #else #include #endif @@ -57,7 +57,7 @@ phys_size_t initdram (int board_type) /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) -#ifndef CONFIG_FSL_DDR2 +#ifndef CONFIG_SYS_FSL_DDR2 msize = spd_sdram() * 1024 * 1024; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) ddr_enable_ecc(msize); @@ -273,11 +273,13 @@ void spi_cs_deactivate(struct spi_slave *slave) #endif /* CONFIG_HARD_SPI */ #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig new file mode 100644 index 0000000000..ce3fffda7d --- /dev/null +++ b/board/freescale/mpc8349itx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8349ITX + +config SYS_BOARD + default "mpc8349itx" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8349ITX" + +endif diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS new file mode 100644 index 0000000000..d0388ad6e5 --- /dev/null +++ b/board/freescale/mpc8349itx/MAINTAINERS @@ -0,0 +1,8 @@ +MPC8349ITX BOARD +#M: - +S: Maintained +F: board/freescale/mpc8349itx/ +F: include/configs/MPC8349ITX.h +F: configs/MPC8349ITX_defconfig +F: configs/MPC8349ITX_LOWBOOT_defconfig +F: configs/MPC8349ITXGP_defconfig diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile index 9e3c891e17..e9092adba2 100644 --- a/board/freescale/mpc8349itx/Makefile +++ b/board/freescale/mpc8349itx/Makefile @@ -4,25 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8349itx.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 803d722806..22a1d99c88 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -378,11 +378,13 @@ int misc_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile deleted file mode 100644 index 0c6e556a6d..0000000000 --- a/board/freescale/mpc8360emds/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mpc8360emds/README b/board/freescale/mpc8360emds/README deleted file mode 100644 index 6afa753969..0000000000 --- a/board/freescale/mpc8360emds/README +++ /dev/null @@ -1,155 +0,0 @@ -Freescale MPC8360EMDS Board ------------------------------------------ -1. Board Switches and Jumpers -1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board - For some reason, the HW designers describe the switch settings - in terms of 0 and 1, and then map that to physical switches where - the label "On" refers to logic 0 and "Off" is logic 1. - - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the - bits may contribute to signals that are numbered based at 0, - and some of those signals may be high-bit-number-0 too. Heed - well the names and labels and do not get confused. - - "Off" == 1 - "On" == 0 - - SW18 is switch 18 as silk-screened onto the board. - SW4[8] is the bit labeled 8 on Switch 4. - SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. - SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3. - SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" - and bits labeled 8 is set as "Off". - -1.1 There are three type boards for MPC8360E silicon up to now, They are - - * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE) - * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT) - * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE) - -1.2 For all the MPC8360EMDS Board - - First, make sure the board default setting is consistent with the - document shipped with your board. Then apply the following setting: - SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus) - SW4[1-8]= 0011_0000 (Flash boot on local bus) - SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH) - SW10[1-8]= 0000_1000 (core PLL setting) - SW11[1-8]= 0000_0100 (SW11 is on the another side of the board) - JP6 1-2 - on board Oscillator: 66M - -1.3 Since different board/chip rev. combinations have AC timing issues, - u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default - by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers). - - When the rev2.x silicon mount on these boards, and if you are using - u-boot version after this patch, to make the ethernet interfaces usable, - and to enable RGMII-ID on your board, you have to setup the jumpers - correctly. - - * MPC8360E-MDS-PB PROTO - nothing to do - * MPC8360E-MDS-PB PILOT - JP9 and JP8 should be ON - * MPC8360EA-MDS-PB PROTO - JP2 and JP3 should be ON - -2. Memory Map - -2.1. The memory map should look pretty much like this: - - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M - 0xc000_0000 0xdfff_ffff Empty 512M - 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M - 0xe020_0000 0xe02f_ffff Empty 1M - 0xe030_0000 0xe03f_ffff PCI IO 1M - 0xe040_0000 0xefff_ffff Empty 252M - 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M - 0xf400_0000 0xf7ff_ffff Empty 64M - 0xf800_0000 0xf800_7fff BCSR on CS1 32K - 0xf800_8000 0xf800_ffff PIB CS4 32K - 0xf801_0000 0xf801_7fff PIB CS5 32K - 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M - - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC8360EMDS.h - - CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 - CONFIG_MPC8360 MPC8360 specific - CONFIG_MPC8360EMDS MPC8360EMDS board specific - -4. Compilation - - MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip). - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make MPC8360EMDS_XX_config - make - - MPC8360EMDS support ATM, PCI in host and slave mode. - - To make u-boot support ATM : - 1) Make MPC8360EMDS_XX_ATM_config - - To make u-boot support PCI host 66M : - 1) DIP SW support PCI mode as described in Section 1.1. - 2) Make MPC8360EMDS_XX_HOST_66_config - - To make u-boot support PCI host 33M : - 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1 - 2) Make MPC8360EMDS_XX_HOST_33_config - - To make u-boot support PCI slave 66M : - 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1 - 2) Make MPC8360EMDS_XX_SLAVE_config - - (where XX is: - 33 - 33.33MHz oscillator - 66 - 66MHz oscillator) - -5. Downloading and Flashing Images - -5.0 Download over serial line using Kermit: - - loadb - [Drop to kermit: - ^\c - send - c - ] - - - Or via tftp: - - tftp 10000 u-boot.bin - -5.1 Reflash U-boot Image using U-boot - - tftp 20000 u-boot.bin - protect off fef00000 fef3ffff - erase fef00000 fef3ffff - - cp.b 20000 fef00000 xxxx - - or - - cp.b 20000 fef00000 3ffff - - -You have to supply the correct byte count with 'xxxx' from the TFTP result log. -Maybe 3ffff will work too, that corresponds to the erased sectors. - - -6. Notes - 1) The console baudrate for MPC8360EMDS is 115200bps. diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c deleted file mode 100644 index 39a86dffe1..0000000000 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc. - * Dave Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_PCI) -#include -#endif -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif -#include -#include -#if defined(CONFIG_PQ_MDS_PIB) -#include "../common/pq-mds-pib.h" -#endif -#include "../../../drivers/qe/uec.h" - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* GETH1 */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {1, 6, 1, 0, 3}, /* TxD4 */ - {1, 7, 1, 0, 1}, /* TxD5 */ - {1, 9, 1, 0, 2}, /* TxD6 */ - {1, 10, 1, 0, 2}, /* TxD7 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 13, 2, 0, 1}, /* RxD4 */ - {1, 1, 2, 0, 2}, /* RxD5 */ - {1, 0, 2, 0, 2}, /* RxD6 */ - {1, 4, 2, 0, 2}, /* RxD7 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 16, 2, 0, 1}, /* RX_ER */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ - /* GETH2 */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {1, 2, 1, 0, 1}, /* TxD4 */ - {1, 3, 1, 0, 2}, /* TxD5 */ - {1, 5, 1, 0, 3}, /* TxD6 */ - {1, 8, 1, 0, 3}, /* TxD7 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 27, 2, 0, 1}, /* RxD4 */ - {1, 12, 2, 0, 2}, /* RxD5 */ - {1, 13, 2, 0, 3}, /* RxD6 */ - {1, 11, 2, 0, 2}, /* RxD7 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 30, 2, 0, 1}, /* RX_ER */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ - - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ - - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ -}; - -/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */ -static int board_handle_erratum2(void) -{ - const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - return REVID_MAJOR(immr->sysconf.spridr) == 2 && - REVID_MINOR(immr->sysconf.spridr) == 1; -} - -int board_early_init_f(void) -{ - const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[0xa] &= ~0x04; - - /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */ - if (REVID_MAJOR(immr->sysconf.spridr) == 2) - bcsr[0xe] = 0x30; - - /* Enable second UART */ - bcsr[0x9] &= ~0x01; - - if (board_handle_erratum2()) { - void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8); - - /* - * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) - * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) - */ - setbits_be32(immap, 0x0c003000); - - /* - * IMMR + 0x14AC[20:27] = 10101010 - * (data delay for both UCC's) - */ - clrsetbits_be32(immap + 4, 0xff0, 0xaa0); - } - return 0; -} - -int board_early_init_r(void) -{ - gd_t *gd; -#ifdef CONFIG_PQ_MDS_PIB - pib_init(); -#endif - /* - * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB - * So re-setup PCI MEM space used BAT5 after relocated to DDR - */ - gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { - write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); - write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); - } - - return 0; -} - -#ifdef CONFIG_UEC_ETH -static uec_info_t uec_info[] = { -#ifdef CONFIG_UEC_ETH1 - STD_UEC_INFO(1), -#endif -#ifdef CONFIG_UEC_ETH2 - STD_UEC_INFO(2), -#endif -}; - -int board_eth_init(bd_t *bd) -{ - if (board_handle_erratum2()) { - int i; - - for (i = 0; i < ARRAY_SIZE(uec_info); i++) { - uec_info[i].enet_interface_type = - PHY_INTERFACE_MODE_RGMII_RXID; - uec_info[i].speed = SPEED_1000; - } - } - return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); -} -#endif /* CONFIG_UEC_ETH */ - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif -int fixed_sdram(void); -static int sdram_init(unsigned int base); - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - u32 lbc_sdram_size; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize DDR ECC byte - */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - lbc_sdram_size = sdram_init(msize * 1024 * 1024); - if (!msize) - msize = lbc_sdram_size; - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE; - u32 ddr_size = msize << 20; - u32 ddr_size_log2 = __ilog2(ddr_size); - u32 half_ddr_size = ddr_size >> 1; - - im->sysconf.ddrlaw[0].bar = - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CONFIG_SYS_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif -#ifdef CONFIG_DDR_II - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; -#else - -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - im->ddr.csbnds[1].csbnds = - (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >> - CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG; - - im->ddr.cs_config[2] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL; - - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; -#endif - udelay(200); - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} -#endif /*!CONFIG_SYS_SPD_EEPROM */ - -int checkboard(void) -{ - puts("Board: Freescale MPC8360EMDS\n"); - return 0; -} - -/* - * if MPC8360EMDS is soldered with SDRAM - */ -#ifdef CONFIG_SYS_LB_SDRAM -/* - * Initialize SDRAM memory on the Local Bus. - */ - -static int sdram_init(unsigned int base) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - fsl_lbc_t *lbc = LBC_BASE_ADDR; - const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; - int rem = base % sdram_size; - uint *sdram_addr; - - /* window base address should be aligned to the window size */ - if (rem) - base = base - rem + sdram_size; - - /* - * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB - * After relocated to DDR, reuse BAT5 for PCI MEM space - */ - if (base > CONFIG_MAX_MEM_MAPPED) { - unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; - unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; - - /* Setup the BAT6 for SDRAM */ - write_bat(DBAT6, batu, batl); - write_bat(IBAT6, batu, batl); - } - - sdram_addr = (uint *)base; - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_br(2, base | CONFIG_SYS_BR2); - set_lbc_or(2, CONFIG_SYS_OR2); - immap->sysconf.lblaw[2].bar = base; - immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2; - - /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* - * We need do 8 times auto refresh operation. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; /* 1 times */ - udelay(100); - *sdram_addr = 0xff; /* 2 times */ - udelay(100); - *sdram_addr = 0xff; /* 3 times */ - udelay(100); - *sdram_addr = 0xff; /* 4 times */ - udelay(100); - *sdram_addr = 0xff; /* 5 times */ - udelay(100); - *sdram_addr = 0xff; /* 6 times */ - udelay(100); - *sdram_addr = 0xff; /* 7 times */ - udelay(100); - *sdram_addr = 0xff; /* 8 times */ - udelay(100); - - /* Mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - *(sdram_addr + 0xcc) = 0xff; - udelay(100); - - /* Normal operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* - * In non-aligned case we don't [normally] use that memory because - * there is a hole. - */ - if (rem) - return 0; - return CONFIG_SYS_LBC_SDRAM_SIZE; -} -#else -static int sdram_init(unsigned int base) { return 0; } -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -static void ft_board_fixup_qe_usb(void *blob, bd_t *bd) -{ - if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) - return; - - do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode", - "peripheral", sizeof("peripheral"), 1); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_board_fixup_qe_usb(blob, bd); - /* - * mpc8360ea pb mds errata 2: RGMII timing - * if on mpc8360ea rev. 2.1, - * change both ucc phy-connection-types from rgmii-id to rgmii-rxid - */ - if (board_handle_erratum2()) { - int nodeoffset; - const char *prop; - int path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { -#if defined(CONFIG_HAS_ETH0) - /* fixup UCC 1 if using rgmii-id mode */ - prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); - if (prop) { - path = fdt_path_offset(blob, prop); - prop = fdt_getprop(blob, path, - "phy-connection-type", 0); - if (prop && (strcmp(prop, "rgmii-id") == 0)) - fdt_fixup_phy_connection(blob, path, - PHY_INTERFACE_MODE_RGMII_RXID); - } -#endif -#if defined(CONFIG_HAS_ETH1) - /* fixup UCC 2 if using rgmii-id mode */ - prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); - if (prop) { - path = fdt_path_offset(blob, prop); - prop = fdt_getprop(blob, path, - "phy-connection-type", 0); - if (prop && (strcmp(prop, "rgmii-id") == 0)) - fdt_fixup_phy_connection(blob, path, - PHY_INTERFACE_MODE_RGMII_RXID); - } -#endif - } - } -} -#endif diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c deleted file mode 100644 index 71244df079..0000000000 --- a/board/freescale/mpc8360emds/pci.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI Configuration space access support for MPC83xx PCI Bridge - */ - -#include -#include -#include -#include -#include -#include -#include -#include "../common/pq-mds-pib.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -#ifdef CONFIG_MPC83XX_PCI2 -static struct pci_region pci2_regions[] = { - { - bus_start: CONFIG_SYS_PCI2_MEM_BASE, - phys_start: CONFIG_SYS_PCI2_MEM_PHYS, - size: CONFIG_SYS_PCI2_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI2_IO_BASE, - phys_start: CONFIG_SYS_PCI2_IO_PHYS, - size: CONFIG_SYS_PCI2_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI2_MMIO_BASE, - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, - size: CONFIG_SYS_PCI2_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; -#endif - -void pci_init_board(void) -#ifdef CONFIG_PCISLAVE -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; - struct pci_region *reg[] = { pci1_regions }; - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - - mpc83xx_pci_init(1, reg); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar0 = 0x0; - pci_ctrl[0].pibar0 = 0x0; - pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | PIWAR_IWS_4K; - - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 &= ~PIWAR_EN; - - pci_ctrl[0].pitar2 = 0x0; - pci_ctrl[0].pibar2 = 0x0; - pci_ctrl[0].piebar2 = 0x0; - pci_ctrl[0].piwar2 &= ~PIWAR_EN; - - /* Unlock the configuration bit */ - mpc83xx_pcislave_unlock(0); - printf("PCI: Agent mode enabled\n"); -} -#else -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; -#ifndef CONFIG_MPC83XX_PCI2 - struct pci_region *reg[] = { pci1_regions }; -#else - struct pci_region *reg[] = { pci1_regions, pci2_regions }; -#endif - - /* initialize the PCA9555PW IO expander on the PIB board */ - pib_init(); - -#if defined(CONFIG_PCI_66M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#elif defined(CONFIG_PCI_33M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | - OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; - printf("PCI clock is 33MHz\n"); -#else - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#endif - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - - udelay(2000); - -#ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg); -#else - mpc83xx_pci_init(2, reg); -#endif -} -#endif /* CONFIG_PCISLAVE */ diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile deleted file mode 100644 index 8895cd010a..0000000000 --- a/board/freescale/mpc8360erdk/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_CMD_NAND) += nand.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c deleted file mode 100644 index fef230bfbd..0000000000 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* MDIO */ - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - /* UCC1 - UEC (Gigabit) */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ - - /* UCC2 - UEC (Gigabit) */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ - - /* UCC7 - UEC */ - {4, 0, 1, 0, 1}, /* TxD0 */ - {4, 1, 1, 0, 1}, /* TxD1 */ - {4, 2, 1, 0, 1}, /* TxD2 */ - {4, 3, 1, 0, 1}, /* TxD3 */ - {4, 6, 2, 0, 1}, /* RxD0 */ - {4, 7, 2, 0, 1}, /* RxD1 */ - {4, 8, 2, 0, 1}, /* RxD2 */ - {4, 9, 2, 0, 1}, /* RxD3 */ - {4, 4, 1, 0, 1}, /* TX_EN */ - {4, 5, 1, 0, 1}, /* TX_ER */ - {4, 12, 2, 0, 1}, /* RX_DV */ - {4, 13, 2, 0, 1}, /* RX_ER */ - {4, 10, 2, 0, 1}, /* COL */ - {4, 11, 2, 0, 1}, /* CRS */ - {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */ - {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */ - - /* UCC4 - UEC */ - {1, 14, 1, 0, 1}, /* TxD0 */ - {1, 15, 1, 0, 1}, /* TxD1 */ - {1, 16, 1, 0, 1}, /* TxD2 */ - {1, 17, 1, 0, 1}, /* TxD3 */ - {1, 20, 2, 0, 1}, /* RxD0 */ - {1, 21, 2, 0, 1}, /* RxD1 */ - {1, 22, 2, 0, 1}, /* RxD2 */ - {1, 23, 2, 0, 1}, /* RxD3 */ - {1, 18, 1, 0, 1}, /* TX_EN */ - {1, 19, 1, 0, 2}, /* TX_ER */ - {1, 26, 2, 0, 1}, /* RX_DV */ - {1, 27, 2, 0, 1}, /* RX_ER */ - {1, 24, 2, 0, 1}, /* COL */ - {1, 25, 2, 0, 1}, /* CRS */ - {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */ - {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */ - - /* PCI1 */ - {5, 4, 2, 0, 3}, /* PCI_M66EN */ - {5, 5, 1, 0, 3}, /* PCI_INTA */ - {5, 6, 1, 0, 3}, /* PCI_RSTO */ - {5, 7, 3, 0, 3}, /* PCI_C_BE0 */ - {5, 8, 3, 0, 3}, /* PCI_C_BE1 */ - {5, 9, 3, 0, 3}, /* PCI_C_BE2 */ - {5, 10, 3, 0, 3}, /* PCI_C_BE3 */ - {5, 11, 3, 0, 3}, /* PCI_PAR */ - {5, 12, 3, 0, 3}, /* PCI_FRAME */ - {5, 13, 3, 0, 3}, /* PCI_TRDY */ - {5, 14, 3, 0, 3}, /* PCI_IRDY */ - {5, 15, 3, 0, 3}, /* PCI_STOP */ - {5, 16, 3, 0, 3}, /* PCI_DEVSEL */ - {5, 17, 0, 0, 0}, /* PCI_IDSEL */ - {5, 18, 3, 0, 3}, /* PCI_SERR */ - {5, 19, 3, 0, 3}, /* PCI_PERR */ - {5, 20, 3, 0, 3}, /* PCI_REQ0 */ - {5, 21, 2, 0, 3}, /* PCI_REQ1 */ - {5, 22, 2, 0, 3}, /* PCI_GNT2 */ - {5, 23, 3, 0, 3}, /* PCI_GNT0 */ - {5, 24, 1, 0, 3}, /* PCI_GNT1 */ - {5, 25, 1, 0, 3}, /* PCI_GNT2 */ - {5, 26, 0, 0, 0}, /* PCI_CLK0 */ - {5, 27, 0, 0, 0}, /* PCI_CLK1 */ - {5, 28, 0, 0, 0}, /* PCI_CLK2 */ - {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */ - {6, 0, 3, 0, 3}, /* PCI_AD0 */ - {6, 1, 3, 0, 3}, /* PCI_AD1 */ - {6, 2, 3, 0, 3}, /* PCI_AD2 */ - {6, 3, 3, 0, 3}, /* PCI_AD3 */ - {6, 4, 3, 0, 3}, /* PCI_AD4 */ - {6, 5, 3, 0, 3}, /* PCI_AD5 */ - {6, 6, 3, 0, 3}, /* PCI_AD6 */ - {6, 7, 3, 0, 3}, /* PCI_AD7 */ - {6, 8, 3, 0, 3}, /* PCI_AD8 */ - {6, 9, 3, 0, 3}, /* PCI_AD9 */ - {6, 10, 3, 0, 3}, /* PCI_AD10 */ - {6, 11, 3, 0, 3}, /* PCI_AD11 */ - {6, 12, 3, 0, 3}, /* PCI_AD12 */ - {6, 13, 3, 0, 3}, /* PCI_AD13 */ - {6, 14, 3, 0, 3}, /* PCI_AD14 */ - {6, 15, 3, 0, 3}, /* PCI_AD15 */ - {6, 16, 3, 0, 3}, /* PCI_AD16 */ - {6, 17, 3, 0, 3}, /* PCI_AD17 */ - {6, 18, 3, 0, 3}, /* PCI_AD18 */ - {6, 19, 3, 0, 3}, /* PCI_AD19 */ - {6, 20, 3, 0, 3}, /* PCI_AD20 */ - {6, 21, 3, 0, 3}, /* PCI_AD21 */ - {6, 22, 3, 0, 3}, /* PCI_AD22 */ - {6, 23, 3, 0, 3}, /* PCI_AD23 */ - {6, 24, 3, 0, 3}, /* PCI_AD24 */ - {6, 25, 3, 0, 3}, /* PCI_AD25 */ - {6, 26, 3, 0, 3}, /* PCI_AD26 */ - {6, 27, 3, 0, 3}, /* PCI_AD27 */ - {6, 28, 3, 0, 3}, /* PCI_AD28 */ - {6, 29, 3, 0, 3}, /* PCI_AD29 */ - {6, 30, 3, 0, 3}, /* PCI_AD30 */ - {6, 31, 3, 0, 3}, /* PCI_AD31 */ - - /* NAND */ - {4, 18, 2, 0, 0}, /* NAND_RYnBY */ - - /* DUART - UART2 */ - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ - - /* UCC5 - UART3 */ - {3, 0, 1, 0, 1}, /* UART3_TX */ - {3, 4, 1, 0, 1}, /* UART3_RTS */ - {3, 6, 2, 0, 1}, /* UART3_RX */ - {3, 12, 2, 0, 0}, /* UART3_CTS */ - {3, 13, 2, 0, 0}, /* UCC5_CD */ - - /* UCC6 - UART4 */ - {3, 14, 1, 0, 1}, /* UART4_TX */ - {3, 18, 1, 0, 1}, /* UART4_RTS */ - {3, 20, 2, 0, 1}, /* UART4_RX */ - {3, 26, 2, 0, 0}, /* UART4_CTS */ - {3, 27, 2, 0, 0}, /* UCC6_CD */ - - /* Fujitsu MB86277 (MINT) graphics controller */ - {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */ - {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */ - {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ - {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ - - /* AD7843 ADC/Touchscreen controller */ - {4, 14, 1, 0, 0}, /* SPI_nCS0 */ - {4, 28, 3, 0, 3}, /* SPI_MOSI */ - {4, 29, 3, 0, 3}, /* SPI_MISO */ - {4, 30, 3, 0, 3}, /* SPI_CLK */ - - /* Freescale QUICC Engine USB Host Controller (FHCI) */ - {1, 2, 1, 0, 3}, /* USBOE */ - {1, 3, 1, 0, 3}, /* USBTP */ - {1, 8, 1, 0, 1}, /* USBTN */ - {1, 9, 2, 1, 3}, /* USBRP */ - {1, 10, 2, 0, 3}, /* USBRXD */ - {1, 11, 2, 1, 3}, /* USBRN */ - {2, 20, 2, 0, 1}, /* CLK21 */ - {4, 20, 1, 0, 0}, /* SPEED */ - {4, 21, 1, 0, 0}, /* SUSPND */ - - /* END of table */ - {0, 0, 0, 0, QE_IOP_TAB_END}, -}; - -int board_early_init_r(void) -{ - void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); - u32 val; - - /* - * Because of errata in the UCCs, we have to write to the reserved - * registers to slow the clocks down. - */ - val = in_be32(reg); - /* UCC1 */ - val |= 0x00003000; - /* UCC2 */ - val |= 0x0c000000; - out_be32(reg, val); - - return 0; -} - -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; - udelay(200); - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} - -phys_size_t initdram(int board_type) -{ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - extern void ddr_enable_ecc(unsigned int dram_size); -#endif - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize DDR ECC byte - */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -int checkboard(void) -{ - puts("Board: Freescale/Logic MPC8360ERDK\n"); - return 0; -} - -static struct pci_region pci_regions[] = { - { - .bus_start = CONFIG_SYS_PCI1_MEM_BASE, - .phys_start = CONFIG_SYS_PCI1_MEM_PHYS, - .size = CONFIG_SYS_PCI1_MEM_SIZE, - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH, - }, - { - .bus_start = CONFIG_SYS_PCI1_MMIO_BASE, - .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS, - .size = CONFIG_SYS_PCI1_MMIO_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCI1_IO_BASE, - .phys_start = CONFIG_SYS_PCI1_IO_PHYS, - .size = CONFIG_SYS_PCI1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions, }; - -#if defined(CONFIG_PCI_33M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | - OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; - printf("PCI clock is 33MHz\n"); -#else - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#endif - - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - ft_pci_setup(blob, bd); -} -#endif diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c deleted file mode 100644 index 237c0c42e0..0000000000 --- a/board/freescale/mpc8360erdk/nand.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * MPC8360E-RDK support for the NAND on FSL UPM - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -static struct immap *im = (struct immap *)CONFIG_SYS_IMMR; - -static const u32 upm_array[] = { - 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ - 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */ - 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */ - 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */ - 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */ - 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */ - 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */ - 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */ - 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */ - 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */ - 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */ - 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */ - 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ -}; - -static void upm_setup(struct fsl_upm *upm) -{ - int i; - - /* write upm array */ - out_be32(upm->mxmr, MxMR_OP_WARR); - - for (i = 0; i < 64; i++) { - out_be32(upm->mdr, upm_array[i]); - out_8(upm->io_addr, 0x0); - } - - /* normal operation */ - out_be32(upm->mxmr, MxMR_OP_NORM); - while (in_be32(upm->mxmr) != MxMR_OP_NORM) - eieio(); -} - -static int dev_ready(int chip_nr) -{ - if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { - debug("nand ready\n"); - return 1; - } - - debug("nand busy\n"); - return 0; -} - -static struct fsl_upm_nand fun = { - .upm = { - .io_addr = (void *)CONFIG_SYS_NAND_BASE, - }, - .width = 8, - .upm_cmd_offset = 8, - .upm_addr_offset = 16, - .dev_ready = dev_ready, - .wait_flags = FSL_UPM_WAIT_RUN_PATTERN, - .chip_delay = 50, -}; - -int board_nand_init(struct nand_chip *nand) -{ - fun.upm.mxmr = &im->im_lbc.mamr; - fun.upm.mdr = &im->im_lbc.mdr; - fun.upm.mar = &im->im_lbc.mar; - - upm_setup(&fun.upm); - - return fsl_upm_nand_init(nand, &fun); -} diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig new file mode 100644 index 0000000000..20d29db099 --- /dev/null +++ b/board/freescale/mpc837xemds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC837XEMDS + +config SYS_BOARD + default "mpc837xemds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC837XEMDS" + +endif diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS new file mode 100644 index 0000000000..6ff1346206 --- /dev/null +++ b/board/freescale/mpc837xemds/MAINTAINERS @@ -0,0 +1,7 @@ +MPC837XEMDS BOARD +M: Dave Liu +S: Maintained +F: board/freescale/mpc837xemds/ +F: include/configs/MPC837XEMDS.h +F: configs/MPC837XEMDS_defconfig +F: configs/MPC837XEMDS_HOST_defconfig diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile index 0c6e556a6d..70b2147c3d 100644 --- a/board/freescale/mpc837xemds/Makefile +++ b/board/freescale/mpc837xemds/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc837xemds.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 0a3c9720d6..572913c7ac 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -329,7 +328,7 @@ static void ft_pci_fixup(void *blob, bd_t *bd) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); ft_tsec_fixup(blob, bd); @@ -341,5 +340,7 @@ void ft_board_setup(void *blob, bd_t *bd) ft_pci_fixup(blob, bd); ft_pcie_fixup(blob, bd); #endif + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xerdb/Kconfig b/board/freescale/mpc837xerdb/Kconfig new file mode 100644 index 0000000000..03415f9fc9 --- /dev/null +++ b/board/freescale/mpc837xerdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC837XERDB + +config SYS_BOARD + default "mpc837xerdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC837XERDB" + +endif diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS new file mode 100644 index 0000000000..81b4eed5ed --- /dev/null +++ b/board/freescale/mpc837xerdb/MAINTAINERS @@ -0,0 +1,6 @@ +MPC837XERDB BOARD +M: Sinan Akman +S: Maintained +F: board/freescale/mpc837xerdb/ +F: include/configs/MPC837XERDB.h +F: configs/MPC837XERDB_defconfig diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile index 0c6e556a6d..c2d0bc4302 100644 --- a/board/freescale/mpc837xerdb/Makefile +++ b/board/freescale/mpc837xerdb/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc837xerdb.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 9afdcaf7ae..e0a1031380 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -199,7 +199,7 @@ int misc_init_r(void) #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_pci_setup(blob, bd); @@ -207,5 +207,7 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); fdt_fixup_esdhc(blob, bd); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc8536ds/Kconfig b/board/freescale/mpc8536ds/Kconfig new file mode 100644 index 0000000000..1a6a9d4598 --- /dev/null +++ b/board/freescale/mpc8536ds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8536DS + +config SYS_BOARD + default "mpc8536ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8536DS" + +endif diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS new file mode 100644 index 0000000000..953072cdd0 --- /dev/null +++ b/board/freescale/mpc8536ds/MAINTAINERS @@ -0,0 +1,9 @@ +MPC8536DS BOARD +#M: - +S: Maintained +F: board/freescale/mpc8536ds/ +F: include/configs/MPC8536DS.h +F: configs/MPC8536DS_defconfig +F: configs/MPC8536DS_36BIT_defconfig +F: configs/MPC8536DS_SDCARD_defconfig +F: configs/MPC8536DS_SPIFLASH_defconfig diff --git a/board/freescale/mpc8536ds/Makefile b/board/freescale/mpc8536ds/Makefile index bbb492d9ee..e36492f501 100644 --- a/board/freescale/mpc8536ds/Makefile +++ b/board/freescale/mpc8536ds/Makefile @@ -6,27 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8536ds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index d10370c9f2..ebe3ba460c 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index a8bb2b29ac..7b0f461971 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,7 +1,7 @@ /* * Copyright 2008-2012 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include @@ -90,7 +90,7 @@ int checkboard (void) phys_size_t fixed_sdram (void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr; uint d_init; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; @@ -196,7 +196,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -207,8 +207,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 1; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ @@ -265,7 +271,7 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); @@ -279,5 +285,6 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_dr_usb(blob, bd); #endif + return 0; } #endif diff --git a/board/freescale/mpc8540ads/Kconfig b/board/freescale/mpc8540ads/Kconfig new file mode 100644 index 0000000000..35a8545547 --- /dev/null +++ b/board/freescale/mpc8540ads/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8540ADS + +config SYS_BOARD + default "mpc8540ads" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8540ADS" + +endif diff --git a/board/freescale/mpc8540ads/MAINTAINERS b/board/freescale/mpc8540ads/MAINTAINERS new file mode 100644 index 0000000000..acc48218d4 --- /dev/null +++ b/board/freescale/mpc8540ads/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8540ADS BOARD +#M: Kumar Gala +S: Orphan (since 2014-06) +F: board/freescale/mpc8540ads/ +F: include/configs/MPC8540ADS.h +F: configs/MPC8540ADS_defconfig diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile index 08dd14b64d..6f82c7f7ac 100644 --- a/board/freescale/mpc8540ads/Makefile +++ b/board/freescale/mpc8540ads/Makefile @@ -5,27 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8540ads.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 571137443e..41d4cfe738 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 7a84cd295a..1069e2c8c8 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -5,7 +5,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include @@ -68,7 +68,7 @@ local_bus_init(void) get_sys_info(&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ @@ -168,7 +168,8 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; @@ -217,8 +218,7 @@ pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int node, tmp[2]; const char *path; @@ -236,5 +236,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif } + + return 0; } #endif diff --git a/board/freescale/mpc8541cds/Kconfig b/board/freescale/mpc8541cds/Kconfig new file mode 100644 index 0000000000..034eab2544 --- /dev/null +++ b/board/freescale/mpc8541cds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8541CDS + +config SYS_BOARD + default "mpc8541cds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8541CDS" + +endif diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS new file mode 100644 index 0000000000..d421b1281b --- /dev/null +++ b/board/freescale/mpc8541cds/MAINTAINERS @@ -0,0 +1,7 @@ +MPC8541CDS BOARD +#M: Kumar Gala +S: Orphan (since 2014-06) +F: board/freescale/mpc8541cds/ +F: include/configs/MPC8541CDS.h +F: configs/MPC8541CDS_defconfig +F: configs/MPC8541CDS_legacy_defconfig diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile index 4f524b7b62..78af4b85fb 100644 --- a/board/freescale/mpc8541cds/Makefile +++ b/board/freescale/mpc8541cds/Makefile @@ -6,27 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8541cds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index 78d73b0ea8..d2ac6c4ad4 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 3d2dabd116..7b264dddd1 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -3,7 +3,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -250,7 +250,7 @@ local_bus_init(void) get_sys_info(&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ diff --git a/board/freescale/mpc8544ds/Kconfig b/board/freescale/mpc8544ds/Kconfig new file mode 100644 index 0000000000..c3e25b89a0 --- /dev/null +++ b/board/freescale/mpc8544ds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8544DS + +config SYS_BOARD + default "mpc8544ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8544DS" + +endif diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS new file mode 100644 index 0000000000..328be7fecc --- /dev/null +++ b/board/freescale/mpc8544ds/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8544DS BOARD +#M: - +S: Maintained +F: board/freescale/mpc8544ds/ +F: include/configs/MPC8544DS.h +F: configs/MPC8544DS_defconfig diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 009cceb5af..3359eea44f 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -6,27 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8544ds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index 94219b9471..aa30cabb03 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -49,7 +49,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index dfd8fa6522..66fb228a90 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -305,7 +305,7 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); @@ -314,5 +314,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig new file mode 100644 index 0000000000..09f3b0b766 --- /dev/null +++ b/board/freescale/mpc8548cds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8548CDS + +config SYS_BOARD + default "mpc8548cds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8548CDS" + +endif diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS new file mode 100644 index 0000000000..6f229227c0 --- /dev/null +++ b/board/freescale/mpc8548cds/MAINTAINERS @@ -0,0 +1,8 @@ +MPC8548CDS BOARD +#M: - +S: Maintained +F: board/freescale/mpc8548cds/ +F: include/configs/MPC8548CDS.h +F: configs/MPC8548CDS_defconfig +F: configs/MPC8548CDS_36BIT_defconfig +F: configs/MPC8548CDS_legacy_defconfig diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile index 4f524b7b62..f797df2273 100644 --- a/board/freescale/mpc8548cds/Makefile +++ b/board/freescale/mpc8548cds/Makefile @@ -6,27 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8548cds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index 996ffe206d..b31ea3432e 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 2f0b71bea1..ca9b43c6b6 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -3,7 +3,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8555cds/Kconfig b/board/freescale/mpc8555cds/Kconfig new file mode 100644 index 0000000000..04bd572212 --- /dev/null +++ b/board/freescale/mpc8555cds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8555CDS + +config SYS_BOARD + default "mpc8555cds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8555CDS" + +endif diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS new file mode 100644 index 0000000000..1ef669000f --- /dev/null +++ b/board/freescale/mpc8555cds/MAINTAINERS @@ -0,0 +1,7 @@ +MPC8555CDS BOARD +#M: Kumar Gala +S: Orphan (since 2014-06) +F: board/freescale/mpc8555cds/ +F: include/configs/MPC8555CDS.h +F: configs/MPC8555CDS_defconfig +F: configs/MPC8555CDS_legacy_defconfig diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile index 4f524b7b62..d32d005e88 100644 --- a/board/freescale/mpc8555cds/Makefile +++ b/board/freescale/mpc8555cds/Makefile @@ -6,27 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8555cds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index 78d73b0ea8..d2ac6c4ad4 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index d4e7abebd4..de5f5669e6 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -1,7 +1,7 @@ /* * Copyright 2004, 2011 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include @@ -248,7 +248,7 @@ local_bus_init(void) get_sys_info(&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ diff --git a/board/freescale/mpc8560ads/Kconfig b/board/freescale/mpc8560ads/Kconfig new file mode 100644 index 0000000000..828c068e9e --- /dev/null +++ b/board/freescale/mpc8560ads/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8560ADS + +config SYS_BOARD + default "mpc8560ads" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8560ADS" + +endif diff --git a/board/freescale/mpc8560ads/MAINTAINERS b/board/freescale/mpc8560ads/MAINTAINERS new file mode 100644 index 0000000000..96e6da2aad --- /dev/null +++ b/board/freescale/mpc8560ads/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8560ADS BOARD +#M: Kumar Gala +S: Orphan (since 2014-06) +F: board/freescale/mpc8560ads/ +F: include/configs/MPC8560ADS.h +F: configs/MPC8560ADS_defconfig diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile index 46e412b923..685168e08d 100644 --- a/board/freescale/mpc8560ads/Makefile +++ b/board/freescale/mpc8560ads/Makefile @@ -5,27 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8560ads.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 571137443e..41d4cfe738 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index a45a5583c9..f99d639b2f 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -5,7 +5,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -273,7 +273,7 @@ local_bus_init(void) get_sys_info(&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ @@ -373,7 +373,7 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; @@ -438,8 +438,7 @@ pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int node, tmp[2]; const char *path; @@ -457,5 +456,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif } + + return 0; } #endif diff --git a/board/freescale/mpc8568mds/Kconfig b/board/freescale/mpc8568mds/Kconfig new file mode 100644 index 0000000000..4e178c5039 --- /dev/null +++ b/board/freescale/mpc8568mds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8568MDS + +config SYS_BOARD + default "mpc8568mds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8568MDS" + +endif diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS new file mode 100644 index 0000000000..379d8cc1d5 --- /dev/null +++ b/board/freescale/mpc8568mds/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8568MDS BOARD +#M: - +S: Maintained +F: board/freescale/mpc8568mds/ +F: include/configs/MPC8568MDS.h +F: configs/MPC8568MDS_defconfig diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile index 4cd711f106..612fb51548 100644 --- a/board/freescale/mpc8568mds/Makefile +++ b/board/freescale/mpc8568mds/Makefile @@ -6,28 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += bcsr.o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8568mds.o +obj-y += bcsr.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c index 509bfc6894..4a6105cb1f 100644 --- a/board/freescale/mpc8568mds/bcsr.c +++ b/board/freescale/mpc8568mds/bcsr.c @@ -1,7 +1,7 @@ /* * Copyright 2007 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h index 3bfca479cb..215534e6c9 100644 --- a/board/freescale/mpc8568mds/bcsr.h +++ b/board/freescale/mpc8568mds/bcsr.h @@ -1,7 +1,7 @@ /* * Copyright 2007 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __BCSR_H_ diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index b1f4f1f848..6db92ef2da 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 2f9417fc77..a5c5d9dd1a 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -3,7 +3,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include @@ -345,10 +345,12 @@ void pci_init_board(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); FT_FSL_PCI_SETUP; + + return 0; } #endif diff --git a/board/freescale/mpc8569mds/Kconfig b/board/freescale/mpc8569mds/Kconfig new file mode 100644 index 0000000000..48718575ff --- /dev/null +++ b/board/freescale/mpc8569mds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8569MDS + +config SYS_BOARD + default "mpc8569mds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8569MDS" + +endif diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS new file mode 100644 index 0000000000..c181407f25 --- /dev/null +++ b/board/freescale/mpc8569mds/MAINTAINERS @@ -0,0 +1,7 @@ +MPC8569MDS BOARD +#M: - +S: Maintained +F: board/freescale/mpc8569mds/ +F: include/configs/MPC8569MDS.h +F: configs/MPC8569MDS_defconfig +F: configs/MPC8569MDS_ATM_defconfig diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile index ec318f0b1f..5f6e021759 100644 --- a/board/freescale/mpc8569mds/Makefile +++ b/board/freescale/mpc8569mds/Makefile @@ -6,28 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += bcsr.o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8569mds.o +obj-y += bcsr.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c index b9c32eca94..178d9f873d 100644 --- a/board/freescale/mpc8569mds/bcsr.c +++ b/board/freescale/mpc8569mds/bcsr.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2009 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h index a32bc3bea7..6f4d13961b 100644 --- a/board/freescale/mpc8569mds/bcsr.h +++ b/board/freescale/mpc8569mds/bcsr.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2009 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __BCSR_H_ diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index 68f686b7e6..ef404b1d6f 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 99b89d3a1f..836578f3cb 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -3,7 +3,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -231,7 +231,8 @@ int checkboard (void) #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; uint d_init; out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); @@ -513,7 +514,7 @@ void pci_init_board(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #if defined(CONFIG_SYS_UCC_RMII_MODE) int nodeoff, off, err; @@ -578,5 +579,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_board_fixup_esdhc(blob, bd); fdt_board_fixup_qe_uart(blob, bd); fdt_board_fixup_qe_usb(blob, bd); + + return 0; } #endif diff --git a/board/freescale/mpc8572ds/Kconfig b/board/freescale/mpc8572ds/Kconfig new file mode 100644 index 0000000000..38132cf3fe --- /dev/null +++ b/board/freescale/mpc8572ds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8572DS + +config SYS_BOARD + default "mpc8572ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8572DS" + +endif diff --git a/board/freescale/mpc8572ds/MAINTAINERS b/board/freescale/mpc8572ds/MAINTAINERS new file mode 100644 index 0000000000..4c9b968cd0 --- /dev/null +++ b/board/freescale/mpc8572ds/MAINTAINERS @@ -0,0 +1,7 @@ +MPC8572DS BOARD +M: York Sun +S: Maintained +F: board/freescale/mpc8572ds/ +F: include/configs/MPC8572DS.h +F: configs/MPC8572DS_defconfig +F: configs/MPC8572DS_36BIT_defconfig diff --git a/board/freescale/mpc8572ds/Makefile b/board/freescale/mpc8572ds/Makefile index 009cceb5af..902c900162 100644 --- a/board/freescale/mpc8572ds/Makefile +++ b/board/freescale/mpc8572ds/Makefile @@ -6,27 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8572ds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index a7ff668b1b..2bfc1a170c 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; @@ -17,7 +17,7 @@ struct board_specific_parameters { u32 clk_adjust; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -139,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -155,7 +155,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 1201d6bc3d..3f68cf496a 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -1,7 +1,7 @@ /* * Copyright 2007-2011 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include @@ -62,7 +62,7 @@ int checkboard (void) phys_size_t fixed_sdram (void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr; uint d_init; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; @@ -144,7 +144,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -155,8 +155,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ @@ -226,7 +232,7 @@ int board_eth_init(bd_t *bis) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -243,5 +249,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8610hpcd/Kconfig b/board/freescale/mpc8610hpcd/Kconfig new file mode 100644 index 0000000000..8f713beaa8 --- /dev/null +++ b/board/freescale/mpc8610hpcd/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8610HPCD + +config SYS_BOARD + default "mpc8610hpcd" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8610HPCD" + +endif diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS new file mode 100644 index 0000000000..de6ab89299 --- /dev/null +++ b/board/freescale/mpc8610hpcd/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8610HPCD BOARD +#M: - +S: Maintained +F: board/freescale/mpc8610hpcd/ +F: include/configs/MPC8610HPCD.h +F: configs/MPC8610HPCD_defconfig diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile index 2009914588..2613004f89 100644 --- a/board/freescale/mpc8610hpcd/Makefile +++ b/board/freescale/mpc8610hpcd/Makefile @@ -3,28 +3,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_FSL_DDR2) += ddr.o -COBJS-y += law.o - -COBJS-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mpc8610hpcd.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o +obj-y += law.o +obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 94219b9471..aa30cabb03 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -49,7 +49,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 1f09429a04..95e398c9f4 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -1,7 +1,7 @@ /* * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include @@ -143,7 +143,7 @@ phys_size_t fixed_sdram(void) { #if !defined(CONFIG_SYS_RAMBOOT) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; uint d_init; ddr->cs0_bnds = 0x0000001f; @@ -258,12 +258,13 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); FT_FSL_PCI_SETUP; + + return 0; } #endif diff --git a/board/freescale/mpc8641hpcn/Kconfig b/board/freescale/mpc8641hpcn/Kconfig new file mode 100644 index 0000000000..ae45d63337 --- /dev/null +++ b/board/freescale/mpc8641hpcn/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MPC8641HPCN + +config SYS_BOARD + default "mpc8641hpcn" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8641HPCN" + +endif diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS new file mode 100644 index 0000000000..97902475ba --- /dev/null +++ b/board/freescale/mpc8641hpcn/MAINTAINERS @@ -0,0 +1,7 @@ +MPC8641HPCN BOARD +#M: Kumar Gala +S: Orphan (since 2014-06) +F: board/freescale/mpc8641hpcn/ +F: include/configs/MPC8641HPCN.h +F: configs/MPC8641HPCN_defconfig +F: configs/MPC8641HPCN_36BIT_defconfig diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile index 0cbc0d0a90..86c70bcb9d 100644 --- a/board/freescale/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -5,26 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-$(CONFIG_FSL_DDR2) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude ($obj).depend - -######################################################################### +obj-y += mpc8641hpcn.o +obj-y += law.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 5d3575738a..7cd0395651 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; @@ -106,5 +106,5 @@ void fsl_ddr_board_options(memctl_options_t *popts, found: /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; } diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 46a543ebcc..94633b5c99 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include @@ -64,7 +64,7 @@ fixed_sdram(void) { #if !defined(CONFIG_SYS_RAMBOOT) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; @@ -119,12 +119,11 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int off; u64 *tmp; - u32 *addrcells; + int addrcells; ft_cpu_setup(blob, bd); @@ -136,12 +135,13 @@ ft_board_setup(void *blob, bd_t *bd) * which is defined by the "reg" property in the soc node. */ off = fdt_path_offset(blob, "/soc8641"); - addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); + addrcells = fdt_address_cells(blob, 0); tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); if (tmp) { u64 addr; - if (addrcells && (*addrcells == 1)) + + if (addrcells == 1) addr = *(u32 *)tmp; else addr = *tmp; @@ -152,6 +152,8 @@ ft_board_setup(void *blob, bd_t *bd) "in u-boot. This means your .dts might " "be old.\n"); } + + return 0; } #endif diff --git a/board/freescale/mx23evk/Kconfig b/board/freescale/mx23evk/Kconfig new file mode 100644 index 0000000000..51a8f9f773 --- /dev/null +++ b/board/freescale/mx23evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX23EVK + +config SYS_BOARD + default "mx23evk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "mx23evk" + +endif diff --git a/board/freescale/mx23evk/MAINTAINERS b/board/freescale/mx23evk/MAINTAINERS new file mode 100644 index 0000000000..b03ad6ae0a --- /dev/null +++ b/board/freescale/mx23evk/MAINTAINERS @@ -0,0 +1,6 @@ +MX23EVK BOARD +M: Otavio Salvador +S: Maintained +F: board/freescale/mx23evk/ +F: include/configs/mx23evk.h +F: configs/mx23evk_defconfig diff --git a/board/freescale/mx23evk/Makefile b/board/freescale/mx23evk/Makefile index 01e7de1210..c3a79ee004 100644 --- a/board/freescale/mx23evk/Makefile +++ b/board/freescale/mx23evk/Makefile @@ -5,27 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifndef CONFIG_SPL_BUILD -COBJS := mx23evk.o +obj-y := mx23evk.o else -COBJS := spl_boot.o +obj-y := spl_boot.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index 054ca0a93b..603f4dcfd1 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -129,7 +129,7 @@ void mxs_adjust_memory_params(uint32_t *dram_vals) dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG; } -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } diff --git a/board/freescale/mx25pdk/Kconfig b/board/freescale/mx25pdk/Kconfig new file mode 100644 index 0000000000..af06b4c827 --- /dev/null +++ b/board/freescale/mx25pdk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX25PDK + +config SYS_BOARD + default "mx25pdk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx25" + +config SYS_CONFIG_NAME + default "mx25pdk" + +endif diff --git a/board/freescale/mx25pdk/MAINTAINERS b/board/freescale/mx25pdk/MAINTAINERS new file mode 100644 index 0000000000..63221765c7 --- /dev/null +++ b/board/freescale/mx25pdk/MAINTAINERS @@ -0,0 +1,6 @@ +MX25PDK BOARD +M: Fabio Estevam +S: Maintained +F: board/freescale/mx25pdk/ +F: include/configs/mx25pdk.h +F: configs/mx25pdk_defconfig diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile index a01a27deaa..0b288f2588 100644 --- a/board/freescale/mx25pdk/Makefile +++ b/board/freescale/mx25pdk/Makefile @@ -6,25 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx25pdk.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx25pdk.o +obj-y += lowlevel_init.o diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index ebe3bcb6ed..71a395c226 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -138,7 +138,7 @@ int board_late_init(void) mx25pdk_fec_init(); - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; diff --git a/board/freescale/mx28evk/Kconfig b/board/freescale/mx28evk/Kconfig new file mode 100644 index 0000000000..39777bd70f --- /dev/null +++ b/board/freescale/mx28evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX28EVK + +config SYS_BOARD + default "mx28evk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "mx28evk" + +endif diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS new file mode 100644 index 0000000000..1caf5fb22a --- /dev/null +++ b/board/freescale/mx28evk/MAINTAINERS @@ -0,0 +1,9 @@ +MX28EVK BOARD +M: Fabio Estevam +S: Maintained +F: board/freescale/mx28evk/ +F: include/configs/mx28evk.h +F: configs/mx28evk_defconfig +F: configs/mx28evk_auart_console_defconfig +F: configs/mx28evk_nand_defconfig +F: configs/mx28evk_spi_defconfig diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile index d3634c1d4d..5956d34a4f 100644 --- a/board/freescale/mx28evk/Makefile +++ b/board/freescale/mx28evk/Makefile @@ -5,27 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifndef CONFIG_SPL_BUILD -COBJS := mx28evk.o +obj-y := mx28evk.o else -COBJS := iomux.o +obj-y := iomux.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README index 524f3fc494..f9d6324114 100644 --- a/board/freescale/mx28evk/README +++ b/board/freescale/mx28evk/README @@ -1,7 +1,7 @@ FREESCALE MX28EVK ================== -Supported hardware: only MX28EVK rev D is supported in U-boot. +Supported hardware: MX28EVK rev C and D are supported in U-boot. Files of the MX28EVK port -------------------------- @@ -23,17 +23,29 @@ To boot MX28EVK from an SD card, set the boot mode DIP switches as: * VDD 5V: To the left (off) * Hold Button: Down (off) +To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as: + + * Boot Mode Select: 0 0 1 0 (Boot from SSP2) + * JTAG PSWITCH RESET: To the right (reset disabled) + * Battery Source: Down + * Wall 5V: Up + * VDD 5V: To the left (off) + * Hold Button: Down (off) Environment Storage ------------------- -There are two targets for mx28evk: +There are three targets for mx28evk: + +"make mx28evk_config" - store environment variables into MMC + +or -"make mx28evk_config" - store enviroment variables into MMC +"make mx28evk_nand_config" - store environment variables into NAND flash or -"make mx28evk_nand_config" - store enviroment variables into NAND flash +"make mx28evk_spi_config" - store enviroment variables into SPI NOR flash Choose the target accordingly. @@ -41,6 +53,10 @@ Note: The mx28evk board does not come with a NAND flash populated from the factory. It comes with an empty slot (U23), which allows the insertion of a 48-pin TSOP flash device. -Follow the instructions from doc/README.mxs to generate a bootable SD card. +mx28evk does not come with SPI NOR flash populated from the factory either. +It is possible to solder a SOIC memory on U49 or use a DIP8 on J89. +To get SPI communication to work R320, R321,R322 and C178 need to be populated. +Look in the schematics for the proper component values. -Insert the SD card in slot 0, power up the board and U-boot will boot. +Follow the instructions from doc/README.mxs to generate a bootable SD card or +to generate a binary to be flashed into SPI NOR. diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 6ca842ba86..97c2376da1 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -200,7 +200,7 @@ void mxs_adjust_memory_params(uint32_t *dram_vals) dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; } -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index a307f27ef5..5005fe23dd 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -103,10 +103,12 @@ int board_eth_init(bd_t *bis) int ret; ret = cpu_eth_init(bis); + if (ret) + return ret; /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, - &clkctrl_regs->hw_clkctrl_enet); + &clkctrl_regs->hw_clkctrl_enet); /* Power-on FECs */ gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig new file mode 100644 index 0000000000..eeeb6f490f --- /dev/null +++ b/board/freescale/mx31ads/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX31ADS + +config SYS_BOARD + default "mx31ads" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx31" + +config SYS_CONFIG_NAME + default "mx31ads" + +endif diff --git a/board/freescale/mx31ads/MAINTAINERS b/board/freescale/mx31ads/MAINTAINERS new file mode 100644 index 0000000000..5f6ec268c7 --- /dev/null +++ b/board/freescale/mx31ads/MAINTAINERS @@ -0,0 +1,6 @@ +MX31ADS BOARD +#M: (resigned) Guennadi Liakhovetski +S: Orphan (since 2013-09) +F: board/freescale/mx31ads/ +F: include/configs/mx31ads.h +F: configs/mx31ads_defconfig diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile index b6c70b01e7..5e1440d596 100644 --- a/board/freescale/mx31ads/Makefile +++ b/board/freescale/mx31ads/Makefile @@ -4,25 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx31ads.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx31ads.o +obj-y += lowlevel_init.o diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index a6ef66eeab..8a4a8a2f07 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -5,7 +5,7 @@ * (C) Copyright 2002 * Gary Jennejohn, DENX Software Engineering, * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") @@ -22,11 +22,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/arm/cpu/arm1136/start.o (.text*) - board/freescale/mx31ads/libmx31ads.o (.text*) - arch/arm/lib/libarm.o (.text*) - net/libnet.o (.text*) - drivers/mtd/libmtd.o (.text*) + * (.vectors) + arch/arm/cpu/arm1136/start.o (.text*) + board/freescale/mx31ads/built-in.o (.text*) + arch/arm/lib/built-in.o (.text*) + net/built-in.o (.text*) + drivers/mtd/built-in.o (.text*) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o(.text*) @@ -69,7 +70,14 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; /* * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c @@ -90,13 +98,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .gnu.hash : { *(.gnu.hash) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/freescale/mx31pdk/Kconfig b/board/freescale/mx31pdk/Kconfig new file mode 100644 index 0000000000..055545c930 --- /dev/null +++ b/board/freescale/mx31pdk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX31PDK + +config SYS_BOARD + default "mx31pdk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx31" + +config SYS_CONFIG_NAME + default "mx31pdk" + +endif diff --git a/board/freescale/mx31pdk/MAINTAINERS b/board/freescale/mx31pdk/MAINTAINERS new file mode 100644 index 0000000000..ec2a32063b --- /dev/null +++ b/board/freescale/mx31pdk/MAINTAINERS @@ -0,0 +1,6 @@ +MX31PDK BOARD +M: Magnus Lilja +S: Maintained +F: board/freescale/mx31pdk/ +F: include/configs/mx31pdk.h +F: configs/mx31pdk_defconfig diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile index 860a8a658f..754b3ea93f 100644 --- a/board/freescale/mx31pdk/Makefile +++ b/board/freescale/mx31pdk/Makefile @@ -7,27 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifdef CONFIG_SPL_BUILD -SOBJS := lowlevel_init.o +obj-y += lowlevel_init.o endif -COBJS := mx31pdk.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mx31pdk.o diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 148b4f47a5..13b9d51dd1 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -85,7 +85,7 @@ int board_late_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return ret; diff --git a/board/freescale/mx35pdk/Kconfig b/board/freescale/mx35pdk/Kconfig new file mode 100644 index 0000000000..021d19e551 --- /dev/null +++ b/board/freescale/mx35pdk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX35PDK + +config SYS_BOARD + default "mx35pdk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx35" + +config SYS_CONFIG_NAME + default "mx35pdk" + +endif diff --git a/board/freescale/mx35pdk/MAINTAINERS b/board/freescale/mx35pdk/MAINTAINERS new file mode 100644 index 0000000000..540e943691 --- /dev/null +++ b/board/freescale/mx35pdk/MAINTAINERS @@ -0,0 +1,6 @@ +MX35PDK BOARD +M: Stefano Babic +S: Maintained +F: board/freescale/mx35pdk/ +F: include/configs/mx35pdk.h +F: configs/mx35pdk_defconfig diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile index 7caf52f115..5fa121912e 100644 --- a/board/freescale/mx35pdk/Makefile +++ b/board/freescale/mx35pdk/Makefile @@ -6,25 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx35pdk.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx35pdk.o +obj-y += lowlevel_init.o diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 427c83a8ff..12467a9ada 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -213,7 +213,7 @@ int board_late_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; @@ -251,14 +251,12 @@ int board_late_init(void) int board_eth_init(bd_t *bis) { - int rc = -ENODEV; #if defined(CONFIG_SMC911X) - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + if (rc) + return rc; #endif - - cpu_eth_init(bis); - - return rc; + return cpu_eth_init(bis); } #if defined(CONFIG_FSL_ESDHC) diff --git a/board/freescale/mx51evk/Kconfig b/board/freescale/mx51evk/Kconfig new file mode 100644 index 0000000000..f9b69cbd66 --- /dev/null +++ b/board/freescale/mx51evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX51EVK + +config SYS_BOARD + default "mx51evk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx51evk" + +endif diff --git a/board/freescale/mx51evk/MAINTAINERS b/board/freescale/mx51evk/MAINTAINERS new file mode 100644 index 0000000000..0e5f22c26b --- /dev/null +++ b/board/freescale/mx51evk/MAINTAINERS @@ -0,0 +1,6 @@ +MX51EVK BOARD +M: Stefano Babic +S: Maintained +F: board/freescale/mx51evk/ +F: include/configs/mx51evk.h +F: configs/mx51evk_defconfig diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile index c9b145527b..b2de2d88ab 100644 --- a/board/freescale/mx51evk/Makefile +++ b/board/freescale/mx51evk/Makefile @@ -6,25 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += mx51evk.o -COBJS-$(CONFIG_VIDEO) += mx51evk_video.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mx51evk.o +obj-$(CONFIG_VIDEO) += mx51evk_video.o diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index d01465ecae..c7c21f392b 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -112,7 +112,7 @@ static void setup_iomux_spi(void) #ifdef CONFIG_USB_EHCI_MX5 #define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7) #define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27) -#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 2) +#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1) #define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5) static void setup_usb_h1(void) @@ -174,7 +174,7 @@ static void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return; @@ -320,7 +320,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); @@ -340,11 +340,13 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx53ard/Kconfig b/board/freescale/mx53ard/Kconfig new file mode 100644 index 0000000000..41f46a04ac --- /dev/null +++ b/board/freescale/mx53ard/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX53ARD + +config SYS_BOARD + default "mx53ard" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx53ard" + +endif diff --git a/board/freescale/mx53ard/MAINTAINERS b/board/freescale/mx53ard/MAINTAINERS new file mode 100644 index 0000000000..7cc0e5e222 --- /dev/null +++ b/board/freescale/mx53ard/MAINTAINERS @@ -0,0 +1,6 @@ +MX53ARD BOARD +M: Fabio Estevam +S: Maintained +F: board/freescale/mx53ard/ +F: include/configs/mx53ard.h +F: configs/mx53ard_defconfig diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile index 8bcb21c713..0b7d8398c8 100644 --- a/board/freescale/mx53ard/Makefile +++ b/board/freescale/mx53ard/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx53ard.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx53ard.o diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index c960c44a61..8ba27288e3 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -166,7 +166,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); @@ -185,12 +185,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx53evk/Kconfig b/board/freescale/mx53evk/Kconfig new file mode 100644 index 0000000000..c226c1ca06 --- /dev/null +++ b/board/freescale/mx53evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX53EVK + +config SYS_BOARD + default "mx53evk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx53evk" + +endif diff --git a/board/freescale/mx53evk/MAINTAINERS b/board/freescale/mx53evk/MAINTAINERS new file mode 100644 index 0000000000..5c5f747cb8 --- /dev/null +++ b/board/freescale/mx53evk/MAINTAINERS @@ -0,0 +1,6 @@ +MX53EVK BOARD +M: Jason Liu +S: Maintained +F: board/freescale/mx53evk/ +F: include/configs/mx53evk.h +F: configs/mx53evk_defconfig diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile index f244069fb7..e03ac7946c 100644 --- a/board/freescale/mx53evk/Makefile +++ b/board/freescale/mx53evk/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx53evk.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx53evk.o diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 3b398b6d76..6ee6d73ed2 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -81,7 +81,7 @@ void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return; @@ -195,7 +195,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -214,12 +214,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx53loco/Kconfig b/board/freescale/mx53loco/Kconfig new file mode 100644 index 0000000000..5ca1672bf7 --- /dev/null +++ b/board/freescale/mx53loco/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX53LOCO + +config SYS_BOARD + default "mx53loco" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx53loco" + +endif diff --git a/board/freescale/mx53loco/MAINTAINERS b/board/freescale/mx53loco/MAINTAINERS new file mode 100644 index 0000000000..73b113e577 --- /dev/null +++ b/board/freescale/mx53loco/MAINTAINERS @@ -0,0 +1,6 @@ +MX53LOCO BOARD +M: Jason Liu +S: Maintained +F: board/freescale/mx53loco/ +F: include/configs/mx53loco.h +F: configs/mx53loco_defconfig diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile index 176a8b6e9f..70ac6db1f9 100644 --- a/board/freescale/mx53loco/Makefile +++ b/board/freescale/mx53loco/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += mx53loco.o -COBJS-$(CONFIG_VIDEO) += mx53loco_video.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += mx53loco.o +obj-$(CONFIG_VIDEO) += mx53loco_video.o diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index ae7eca85b0..efcf4b390d 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -30,24 +30,41 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) { - u32 size1, size2; + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); - gd->ram_size = size1 + size2; + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; return 0; } + void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; } u32 get_board_rev(void) @@ -169,7 +186,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -188,12 +205,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif @@ -225,6 +244,8 @@ static int power_init(void) if (!p) return -ENODEV; + setenv("fdt_file", "imx53-qsb.dtb"); + /* Set VDDA to 1.25V */ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); @@ -258,7 +279,7 @@ static int power_init(void) } if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; @@ -266,6 +287,8 @@ static int power_init(void) if (!p) return -ENODEV; + setenv("fdt_file", "imx53-qsrb.dtb"); + /* Set VDDGP to 1.25V for 1GHz on SW1 */ pmic_reg_read(p, REG_SW_0, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; @@ -343,6 +366,7 @@ int board_early_init_f(void) return 0; } +#if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { u32 cpurev; @@ -356,6 +380,7 @@ int print_cpuinfo(void) printf("Reset cause: %s\n", get_reset_cause()); return 0; } +#endif /* * Do not overwrite the console diff --git a/board/freescale/mx53smd/Kconfig b/board/freescale/mx53smd/Kconfig new file mode 100644 index 0000000000..1195d33d06 --- /dev/null +++ b/board/freescale/mx53smd/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX53SMD + +config SYS_BOARD + default "mx53smd" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx53smd" + +endif diff --git a/board/freescale/mx53smd/MAINTAINERS b/board/freescale/mx53smd/MAINTAINERS new file mode 100644 index 0000000000..8830321495 --- /dev/null +++ b/board/freescale/mx53smd/MAINTAINERS @@ -0,0 +1,6 @@ +MX53SMD BOARD +M: Fabio Estevam +S: Maintained +F: board/freescale/mx53smd/ +F: include/configs/mx53smd.h +F: configs/mx53smd_defconfig diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile index 488b2c8511..5da34c002d 100644 --- a/board/freescale/mx53smd/Makefile +++ b/board/freescale/mx53smd/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx53smd.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx53smd.o diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index d64c674e91..0963fd7b43 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -106,7 +106,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); @@ -121,12 +121,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(1)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig new file mode 100644 index 0000000000..4af33af185 --- /dev/null +++ b/board/freescale/mx6qarm2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6QARM2 + +config SYS_BOARD + default "mx6qarm2" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6qarm2" + +endif diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS new file mode 100644 index 0000000000..52cf7f935a --- /dev/null +++ b/board/freescale/mx6qarm2/MAINTAINERS @@ -0,0 +1,10 @@ +MX6QARM2 BOARD +M: Jason Liu +M: Ye Li +S: Maintained +F: board/freescale/mx6qarm2/ +F: include/configs/mx6qarm2.h +F: configs/mx6qarm2_defconfig +F: configs/mx6dlarm2_defconfig +F: configs/mx6qarm2_lpddr2_defconfig +F: configs/mx6dlarm2_lpddr2_defconfig diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile index bd37558475..79401f4edf 100644 --- a/board/freescale/mx6qarm2/Makefile +++ b/board/freescale/mx6qarm2/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx6qarm2.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx6qarm2.o diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index 710f34d9a5..c85bde510e 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. * Jason Liu * * SPDX-License-Identifier: GPL-2.0+ @@ -30,6 +30,185 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ +#ifdef CONFIG_MX6DQ_LPDDR2 +/* DCD */ +DATA 4 0x020C4018 0x60324 + +DATA 4 0x020E05a8 0x00003038 +DATA 4 0x020E05b0 0x00003038 +DATA 4 0x020E0524 0x00003038 +DATA 4 0x020E051c 0x00003038 + +DATA 4 0x020E0518 0x00003038 +DATA 4 0x020E050c 0x00003038 +DATA 4 0x020E05b8 0x00003038 +DATA 4 0x020E05c0 0x00003038 + +DATA 4 0x020E05ac 0x00000038 +DATA 4 0x020E05b4 0x00000038 +DATA 4 0x020E0528 0x00000038 +DATA 4 0x020E0520 0x00000038 + +DATA 4 0x020E0514 0x00000038 +DATA 4 0x020E0510 0x00000038 +DATA 4 0x020E05bc 0x00000038 +DATA 4 0x020E05c4 0x00000038 + +DATA 4 0x020E056c 0x00000038 +DATA 4 0x020E0578 0x00000038 +DATA 4 0x020E0588 0x00000038 +DATA 4 0x020E0594 0x00000038 + +DATA 4 0x020E057c 0x00000038 +DATA 4 0x020E0590 0x00000038 +DATA 4 0x020E0598 0x00000038 +DATA 4 0x020E058c 0x00000000 + +DATA 4 0x020E059c 0x00000038 +DATA 4 0x020E05a0 0x00000038 +DATA 4 0x020E0784 0x00000038 +DATA 4 0x020E0788 0x00000038 + +DATA 4 0x020E0794 0x00000038 +DATA 4 0x020E079c 0x00000038 +DATA 4 0x020E07a0 0x00000038 +DATA 4 0x020E07a4 0x00000038 + +DATA 4 0x020E07a8 0x00000038 +DATA 4 0x020E0748 0x00000038 +DATA 4 0x020E074c 0x00000038 +DATA 4 0x020E0750 0x00020000 + +DATA 4 0x020E0758 0x00000000 +DATA 4 0x020E0774 0x00020000 +DATA 4 0x020E078c 0x00000038 +DATA 4 0x020E0798 0x00080000 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b401c 0x00008000 + +DATA 4 0x021b085c 0x1b5f01ff +DATA 4 0x021b485c 0x1b5f01ff + +DATA 4 0x021b0800 0xa1390000 +DATA 4 0x021b4800 0xa1390000 + +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b4890 0x00400000 + +DATA 4 0x021b48bc 0x00055555 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b482c 0xf3333333 +DATA 4 0x021b4830 0xf3333333 +DATA 4 0x021b4834 0xf3333333 +DATA 4 0x021b4838 0xf3333333 + +DATA 4 0x021b0848 0x49383b39 +DATA 4 0x021b0850 0x30364738 +DATA 4 0x021b4848 0x3e3c3846 +DATA 4 0x021b4850 0x4c294b35 + +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x0 + +DATA 4 0x021b0858 0xf00 +DATA 4 0x021b4858 0xf00 + +DATA 4 0x021b08b8 0x800 +DATA 4 0x021b48b8 0x800 + +DATA 4 0x021b000c 0x555a61a5 +DATA 4 0x021b0004 0x20036 +DATA 4 0x021b0010 0x160e83 +DATA 4 0x021b0014 0xdd +DATA 4 0x021b0018 0x8174c +DATA 4 0x021b002c 0xf9f26d2 +DATA 4 0x021b0030 0x20e +DATA 4 0x021b0038 0x200aac +DATA 4 0x021b0008 0x0 + +DATA 4 0x021b0040 0x5f + +DATA 4 0x021b0000 0xc3010000 + +DATA 4 0x021b400c 0x555a61a5 +DATA 4 0x021b4004 0x20036 +DATA 4 0x021b4010 0x160e83 +DATA 4 0x021b4014 0xdd +DATA 4 0x021b4018 0x8174c +DATA 4 0x021b402c 0xf9f26d2 +DATA 4 0x021b4030 0x20e +DATA 4 0x021b4038 0x200aac +DATA 4 0x021b4008 0x0 + +DATA 4 0x021b4040 0x3f +DATA 4 0x021b4000 0xc3010000 + +DATA 4 0x021b001c 0x3f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0xc2018030 +DATA 4 0x021b001c 0x6028030 +DATA 4 0x021b001c 0x2038030 + +DATA 4 0x021b401c 0x3f8030 +DATA 4 0x021b401c 0xff0a8030 +DATA 4 0x021b401c 0xc2018030 +DATA 4 0x021b401c 0x6028030 +DATA 4 0x021b401c 0x2038030 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 + +DATA 4 0x021b0020 0x7800 +DATA 4 0x021b4020 0x7800 + +DATA 4 0x021b0818 0x0 +DATA 4 0x021b4818 0x0 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 + +DATA 4 0x021b08b8 0x800 +DATA 4 0x021b48b8 0x800 + +DATA 4 0x021b001c 0x0 +DATA 4 0x021b401c 0x0 + +DATA 4 0x021b0404 0x00011006 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +#else DATA 4 0x020e05a8 0x00000030 DATA 4 0x020e05b0 0x00000030 DATA 4 0x020e0524 0x00000030 @@ -142,12 +321,8 @@ DATA 4 0x021b48b8 0x00000800 DATA 4 0x021b001c 0x00000000 DATA 4 0x021b0404 0x00011006 -DATA 4 0x020e0010 0xF00000FF -DATA 4 0x020e0018 0x00070007 -DATA 4 0x020e001c 0x00070007 - DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 DATA 4 0x020c4078 0x00FFF300 @@ -159,3 +334,5 @@ DATA 4 0x020e0010 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F + +#endif /* CONFIG_MX6DQ_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg new file mode 100644 index 0000000000..ae8dcc626e --- /dev/null +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -0,0 +1,462 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + + + +#ifdef CONFIG_MX6DL_LPDDR2 + +/* IOMUX SETTINGS */ +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ +DATA 4 0x020E04bc 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ +DATA 4 0x020E04c0 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ +DATA 4 0x020E04c4 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ +DATA 4 0x020E04c8 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ +DATA 4 0x020E04cc 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ +DATA 4 0x020E04d0 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ +DATA 4 0x020E04d4 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ +DATA 4 0x020E04d8 0x00003028 + +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ +DATA 4 0x020E0470 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ +DATA 4 0x020E0474 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ +DATA 4 0x020E0478 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ +DATA 4 0x020E047c 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ +DATA 4 0x020E0480 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ +DATA 4 0x020E0484 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ +DATA 4 0x020E0488 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ +DATA 4 0x020E048c 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ +DATA 4 0x020E0464 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ +DATA 4 0x020E0490 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ +DATA 4 0x020E04ac 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ +DATA 4 0x020E04b0 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ +DATA 4 0x020E0494 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ +DATA 4 0x020E04a4 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ +DATA 4 0x020E04a8 0x00000038 +/* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 + * DSE can be configured using Group Control Register: + * IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ +DATA 4 0x020E04a0 0x00000000 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ +DATA 4 0x020E04b4 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ +DATA 4 0x020E04b8 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ +DATA 4 0x020E0764 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ +DATA 4 0x020E0770 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ +DATA 4 0x020E0778 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ +DATA 4 0x020E077c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ +DATA 4 0x020E0780 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ +DATA 4 0x020E0784 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ +DATA 4 0x020E078c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ +DATA 4 0x020E0748 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ +DATA 4 0x020E074c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ +DATA 4 0x020E076c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ +DATA 4 0x020E0750 0x00020000 +/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ +DATA 4 0x020E0754 0x00000000 +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ +DATA 4 0x020E0760 0x00020000 +/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ +DATA 4 0x020E0774 0x00080000 + +/* + * DDR Controller Registers + * + * Manufacturer: Mocron + * Device Part Number: MT42L64M64D2KH-18 + * Clock Freq.: 528MHz + * MMDC channels: Both MMDC0, MMDC1 + *Density per CS in Gb: 256M + * Chip Selects used: 2 + * Number of Banks: 8 + * Row address: 14 + * Column address: 9 + * Data bus width 32 + */ + +/* MMDC_P0_BASE_ADDR = 0x021b0000 */ +/* MMDC_P1_BASE_ADDR = 0x021b4000 */ + +/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ +DATA 4 0x021b001c 0x00008000 + +/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ +DATA 4 0x021b401c 0x00008000 + +/*LPDDR2 ZQ params */ +DATA 4 0x021b085c 0x1b5f01ff +DATA 4 0x021b485c 0x1b5f01ff + +/* Calibration setup. */ +/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ +DATA 4 0x021b0800 0xa1390003 + +/*ca bus abs delay */ +DATA 4 0x021b0890 0x00400000 +/*ca bus abs delay */ +DATA 4 0x021b4890 0x00400000 +/* values of 20,40,50,60,7f tried. no difference seen */ + +/* DDR_PHY_P1_MPWRCADL */ +DATA 4 0x021b48bc 0x00055555 + +/*frc_msr.*/ +DATA 4 0x021b08b8 0x00000800 +/*frc_msr.*/ +DATA 4 0x021b48b8 0x00000800 + +/* DDR_PHY_P0_MPREDQBY0DL3 */ +DATA 4 0x021b081c 0x33333333 +/* DDR_PHY_P0_MPREDQBY1DL3 */ +DATA 4 0x021b0820 0x33333333 +/* DDR_PHY_P0_MPREDQBY2DL3 */ +DATA 4 0x021b0824 0x33333333 +/* DDR_PHY_P0_MPREDQBY3DL3 */ +DATA 4 0x021b0828 0x33333333 +/* DDR_PHY_P1_MPREDQBY0DL3 */ +DATA 4 0x021b481c 0x33333333 +/* DDR_PHY_P1_MPREDQBY1DL3 */ +DATA 4 0x021b4820 0x33333333 +/* DDR_PHY_P1_MPREDQBY2DL3 */ +DATA 4 0x021b4824 0x33333333 +/* DDR_PHY_P1_MPREDQBY3DL3 */ +DATA 4 0x021b4828 0x33333333 + +/* + * Read and write data delay, per byte. + * For optimized DDR operation it is recommended to run mmdc_calibration + * on your board, and replace 4 delay register assigns with resulted values + * Note: + * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section + * should be skipped, or the write/read calibration comming after that + * will stall + * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. + */ + +DATA 4 0x021b0848 0x4b4b524f +DATA 4 0x021b4848 0x494f4c44 + +DATA 4 0x021b0850 0x3c3d303c +DATA 4 0x021b4850 0x3c343d38 + +/*dqs gating dis */ +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x0 + +/*clk delay */ +DATA 4 0x021b0858 0xa00 +/*clk delay */ +DATA 4 0x021b4858 0xa00 + +/*frc_msr */ +DATA 4 0x021b08b8 0x00000800 +/*frc_msr */ +DATA 4 0x021b48b8 0x00000800 +/* Calibration setup end */ + +/* Channel0 - startng address 0x80000000 */ +/* MMDC0_MDCFG0 */ +DATA 4 0x021b000c 0x34386145 + +/* MMDC0_MDPDC */ +DATA 4 0x021b0004 0x00020036 +/* MMDC0_MDCFG1 */ +DATA 4 0x021b0010 0x00100c83 +/* MMDC0_MDCFG2 */ +DATA 4 0x021b0014 0x000000Dc +/* MMDC0_MDMISC */ +DATA 4 0x021b0018 0x0000174C +/* MMDC0_MDRWD;*/ +DATA 4 0x021b002c 0x0f9f26d2 +/* MMDC0_MDOR */ +DATA 4 0x021b0030 0x0000020e +/* MMDC0_MDCFG3LP */ +DATA 4 0x021b0038 0x00190778 +/* MMDC0_MDOTC */ +DATA 4 0x021b0008 0x00000000 + +/* CS0_END */ +DATA 4 0x021b0040 0x0000005f +/* ROC */ +DATA 4 0x021b0404 0x0000000f + +/* MMDC0_MDCTL */ +DATA 4 0x021b0000 0xc3010000 + +/* Channel1 - starting address 0x10000000 */ +/* MMDC1_MDCFG0 */ +DATA 4 0x021b400c 0x34386145 + +/* MMDC1_MDPDC */ +DATA 4 0x021b4004 0x00020036 +/* MMDC1_MDCFG1 */ +DATA 4 0x021b4010 0x00100c83 +/* MMDC1_MDCFG2 */ +DATA 4 0x021b4014 0x000000Dc +/* MMDC1_MDMISC */ +DATA 4 0x021b4018 0x0000174C +/* MMDC1_MDRWD;*/ +DATA 4 0x021b402c 0x0f9f26d2 +/* MMDC1_MDOR */ +DATA 4 0x021b4030 0x0000020e +/* MMDC1_MDCFG3LP */ +DATA 4 0x021b4038 0x00190778 +/* MMDC1_MDOTC */ +DATA 4 0x021b4008 0x00000000 + +/* CS0_END */ +DATA 4 0x021b4040 0x0000003f + +/* MMDC1_MDCTL */ +DATA 4 0x021b4000 0xc3010000 + +/* Channel0 : Configure DDR device:*/ +/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ +DATA 4 0x021b001c 0x003f8030 +/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ +DATA 4 0x021b001c 0xff0a8030 +/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ +DATA 4 0x021b001c 0xa2018030 +/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ +DATA 4 0x021b001c 0x06028030 +/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ +DATA 4 0x021b001c 0x01038030 + +/* Channel1 : Configure DDR device:*/ +/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ +DATA 4 0x021b401c 0x003f8030 +/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ +DATA 4 0x021b401c 0xff0a8030 +/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ +DATA 4 0x021b401c 0xa2018030 +/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ +DATA 4 0x021b401c 0x06028030 +/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ +DATA 4 0x021b401c 0x01038030 + +/* MMDC0_MDREF */ +DATA 4 0x021b0020 0x00005800 +/* MMDC1_MDREF */ +DATA 4 0x021b4020 0x00005800 + +/* DDR_PHY_P0_MPODTCTRL */ +DATA 4 0x021b0818 0x0 +/* DDR_PHY_P1_MPODTCTRL */ +DATA 4 0x021b4818 0x0 + +/* + * calibration values based on calibration compare of 0x00ffff00: + * Note, these calibration values are based on Freescale's board + * May need to run calibration on target board to fine tune these + */ + +/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ +DATA 4 0x021b0800 0xa1310003 + +/* DDR_PHY_P0_MPMUR0, frc_msr */ +DATA 4 0x021b08b8 0x00000800 +/* DDR_PHY_P1_MPMUR0, frc_msr */ +DATA 4 0x021b48b8 0x00000800 + +/* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization is complete) + */ +DATA 4 0x021b001c 0x00000000 +/* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization is complete) + */ +DATA 4 0x021b401c 0x00000000 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +DATA 4 0x020e0010 0xF00000CF +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +#else /* CONFIG_MX6DL_LPDDR2 */ + +DATA 4 0x020e0798 0x000c0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x00370037 +DATA 4 0x021b4810 0x00370037 +DATA 4 0x021b083c 0x422f0220 +DATA 4 0x021b0840 0x021f0219 +DATA 4 0x021b483C 0x422f0220 +DATA 4 0x021b4840 0x022d022f +DATA 4 0x021b0848 0x47494b49 +DATA 4 0x021b4848 0x48484c47 +DATA 4 0x021b0850 0x39382b2f +DATA 4 0x021b4850 0x2f35312c +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 + +DATA 4 0x021b000c 0x40445323 +DATA 4 0x021b0010 0xb66e8c63 + +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00081740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00440e21 +#ifdef CONFIG_DDR_32BIT +DATA 4 0x021b0040 0x00000017 +DATA 4 0x021b0000 0xc3190000 +#else +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0xc31a0000 +#endif +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x0400803a +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803b +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x07208030 +DATA 4 0x021b001c 0x07208038 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00000007 +DATA 4 0x021b4818 0x00000007 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b4004 0x00011006 +DATA 4 0x021b001c 0x00000000 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +DATA 4 0x020e0010 0xF00000CF +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif /* CONFIG_MX6DL_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 4dae0231dc..89cb916de8 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include @@ -16,6 +16,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -32,58 +33,63 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); +#if defined(CONFIG_SOC_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ + defined(CONFIG_DDR_32BIT) + gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2; +#else + gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; +#endif return 0; } iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO_6_11, /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS0__GPIO6_IO11, /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; @@ -120,7 +126,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -140,13 +146,15 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif @@ -186,13 +194,10 @@ int fecmxc_mii_postcall(int phy) int board_eth_init(bd_t *bis) { struct eth_device *dev; - int ret; + int ret = cpu_eth_init(bis); - ret = cpu_eth_init(bis); - if (ret) { - printf("FEC MXC: %s:failed\n", __func__); + if (ret) return ret; - } dev = eth_get_dev_by_name("FEC"); if (!dev) { @@ -209,6 +214,43 @@ int board_eth_init(bd_t *bis) return 0; } +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_EIM_D22__USB_OTG_PWR, + MX6_PAD_GPIO_1__USB_OTG_ID, +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 1); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 0) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -222,12 +264,20 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } int checkboard(void) { +#ifdef CONFIG_SOC_MX6DL + puts("Board: MX6DL-Armadillo2\n"); +#else puts("Board: MX6Q-Armadillo2\n"); +#endif return 0; } diff --git a/board/freescale/mx6qsabreauto/Kconfig b/board/freescale/mx6qsabreauto/Kconfig new file mode 100644 index 0000000000..cc2a140c52 --- /dev/null +++ b/board/freescale/mx6qsabreauto/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6QSABREAUTO + +config SYS_BOARD + default "mx6qsabreauto" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6qsabreauto" + +endif diff --git a/board/freescale/mx6qsabreauto/MAINTAINERS b/board/freescale/mx6qsabreauto/MAINTAINERS new file mode 100644 index 0000000000..fb65ce4123 --- /dev/null +++ b/board/freescale/mx6qsabreauto/MAINTAINERS @@ -0,0 +1,7 @@ +MX6QSABREAUTO BOARD +M: Fabio Estevam +S: Maintained +F: board/freescale/mx6qsabreauto/ +F: include/configs/mx6qsabreauto.h +F: configs/mx6dlsabreauto_defconfig +F: configs/mx6qsabreauto_defconfig diff --git a/board/freescale/mx6qsabreauto/Makefile b/board/freescale/mx6qsabreauto/Makefile index e9c2eb4699..ac5bc81635 100644 --- a/board/freescale/mx6qsabreauto/Makefile +++ b/board/freescale/mx6qsabreauto/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx6qsabreauto.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx6qsabreauto.o diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg index 6d192a6b4b..16bf473164 100644 --- a/board/freescale/mx6qsabreauto/imximage.cfg +++ b/board/freescale/mx6qsabreauto/imximage.cfg @@ -29,119 +29,101 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 DATA 4 0x020e05a8 0x00000028 DATA 4 0x020e05b0 0x00000028 DATA 4 0x020e0524 0x00000028 DATA 4 0x020e051c 0x00000028 - DATA 4 0x020e0518 0x00000028 DATA 4 0x020e050c 0x00000028 DATA 4 0x020e05b8 0x00000028 DATA 4 0x020e05c0 0x00000028 - -DATA 4 0x020e05ac 0x00000028 -DATA 4 0x020e05b4 0x00000028 -DATA 4 0x020e0528 0x00000028 -DATA 4 0x020e0520 0x00000028 - -DATA 4 0x020e0514 0x00000028 -DATA 4 0x020e0510 0x00000028 -DATA 4 0x020e05bc 0x00000028 -DATA 4 0x020e05c4 0x00000028 - -DATA 4 0x020e056c 0x00000030 -DATA 4 0x020e0578 0x00000030 -DATA 4 0x020e0588 0x00000030 -DATA 4 0x020e0594 0x00000030 - -DATA 4 0x020e057c 0x00000030 -DATA 4 0x020e0590 0x00000030 -DATA 4 0x020e0598 0x00000030 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0774 0x00020000 DATA 4 0x020e0784 0x00000028 DATA 4 0x020e0788 0x00000028 - DATA 4 0x020e0794 0x00000028 DATA 4 0x020e079c 0x00000028 DATA 4 0x020e07a0 0x00000028 DATA 4 0x020e07a4 0x00000028 - DATA 4 0x020e07a8 0x00000028 DATA 4 0x020e0748 0x00000028 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - +DATA 4 0x020e05ac 0x00000028 +DATA 4 0x020e05b4 0x00000028 +DATA 4 0x020e0528 0x00000028 +DATA 4 0x020e0520 0x00000028 +DATA 4 0x020e0514 0x00000028 +DATA 4 0x020e0510 0x00000028 +DATA 4 0x020e05bc 0x00000028 +DATA 4 0x020e05c4 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43260335 +DATA 4 0x021b0840 0x031A030B +DATA 4 0x021b483c 0x4323033B +DATA 4 0x021b4840 0x0323026F +DATA 4 0x021b0848 0x483D4545 +DATA 4 0x021b4848 0x44433E48 +DATA 4 0x021b0850 0x41444840 +DATA 4 0x021b4850 0x4835483E DATA 4 0x021b081c 0x33333333 DATA 4 0x021b0820 0x33333333 DATA 4 0x021b0824 0x33333333 DATA 4 0x021b0828 0x33333333 - DATA 4 0x021b481c 0x33333333 DATA 4 0x021b4820 0x33333333 DATA 4 0x021b4824 0x33333333 DATA 4 0x021b4828 0x33333333 - +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x8A8F7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b0018 0x00001740 - DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x8A8F7975 -DATA 4 0x021b0010 0xFF538E64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x008F0E21 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008F1023 DATA 4 0x021b0040 0x00000047 DATA 4 0x021b0000 0x841A0000 - DATA 4 0x021b001c 0x04088032 DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00048031 DATA 4 0x021b001c 0x09408030 - DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b0800 0xA1380003 DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00000007 -DATA 4 0x021b4818 0x00000007 - -/* Calibration values based on ARD and 528MHz */ -DATA 4 0x021b083c 0x434B0358 -DATA 4 0x021b0840 0x033D033C -DATA 4 0x021b483c 0x03520362 -DATA 4 0x021b4840 0x03480318 -DATA 4 0x021b0848 0x41383A3C -DATA 4 0x021b4848 0x3F3C374A -DATA 4 0x021b0850 0x42434444 -DATA 4 0x021b4850 0x4932473A - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x001F001F -DATA 4 0x021b4810 0x001F001F - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 DATA 4 0x021b0004 0x00025576 - +DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabreauto/mx6dl.cfg b/board/freescale/mx6qsabreauto/mx6dl.cfg new file mode 100644 index 0000000000..89078e5653 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6dl.cfg @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000028 +DATA 4 0x020e04c0 0x00000028 +DATA 4 0x020e04c4 0x00000028 +DATA 4 0x020e04c8 0x00000028 +DATA 4 0x020e04cc 0x00000028 +DATA 4 0x020e04d0 0x00000028 +DATA 4 0x020e04d4 0x00000028 +DATA 4 0x020e04d8 0x00000028 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000028 +DATA 4 0x020e0770 0x00000028 +DATA 4 0x020e0778 0x00000028 +DATA 4 0x020e077c 0x00000028 +DATA 4 0x020e0780 0x00000028 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e078c 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e0470 0x00000028 +DATA 4 0x020e0474 0x00000028 +DATA 4 0x020e0478 0x00000028 +DATA 4 0x020e047c 0x00000028 +DATA 4 0x020e0480 0x00000028 +DATA 4 0x020e0484 0x00000028 +DATA 4 0x020e0488 0x00000028 +DATA 4 0x020e048c 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x42190217 +DATA 4 0x021b0840 0x017B017B +DATA 4 0x021b483c 0x4176017B +DATA 4 0x021b4840 0x015F016C +DATA 4 0x021b0848 0x4C4C4D4C +DATA 4 0x021b4848 0x4A4D4C48 +DATA 4 0x021b0850 0x3F3F3F40 +DATA 4 0x021b4850 0x3538382E +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020025 +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676B5313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006B1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025565 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index d454d64dec..c7a790f527 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -11,18 +11,25 @@ #include #include #include -#include +#include #include #include #include #include #include +#include #include #include #include #include #include #include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; @@ -41,8 +48,19 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PMIC 1 + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -50,86 +68,195 @@ int dram_init(void) return 0; } -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +static iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const enet_pads[] = { +static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ -struct i2c_pads_info i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, .gp = IMX_GPIO_NR(2, 30) }, .sda = { .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; +#ifndef CONFIG_SYS_FLASH_CFI /* * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, * Compass Sensor, Accelerometer, Res Touch */ -struct i2c_pads_info i2c_pad_info2 = { +static struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, .gp = IMX_GPIO_NR(1, 3) }, .sda = { .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, .gp = IMX_GPIO_NR(3, 18) } }; +#endif + +static iomux_v3_cfg_t const i2c3_pads[] = { + MX6_PAD_EIM_A24__GPIO5_IO04, +}; -iomux_v3_cfg_t const i2c3_pads[] = { - MX6_PAD_EIM_A24__GPIO_5_4, +static iomux_v3_cfg_t const port_exp[] = { + MX6_PAD_SD2_DAT0__GPIO1_IO15, }; -iomux_v3_cfg_t const port_exp[] = { - MX6_PAD_SD2_DAT0__GPIO_1_15, +/*Define for building port exp gpio, pin starts from 0*/ +#define PORTEXP_IO_NR(chip, pin) \ + ((chip << 5) + pin) + +/*Get the chip addr from a ioexp gpio*/ +#define PORTEXP_IO_TO_CHIP(gpio_nr) \ + (gpio_nr >> 5) + +/*Get the pin number from a ioexp gpio*/ +#define PORTEXP_IO_TO_PIN(gpio_nr) \ + (gpio_nr & 0x1f) + +static int port_exp_direction_output(unsigned gpio, int value) +{ + int ret; + + i2c_set_bus_num(2); + ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio)); + if (ret) + return ret; + + ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + return ret; + + ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (value << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + return ret; + + return 0; +} + +static iomux_v3_cfg_t const eimnor_pads[] = { + MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_OE__EIM_OE_B, + MX6_PAD_EIM_RW__EIM_RW, + MX6_PAD_EIM_CS0__EIM_CS0_B, }; +static void eimnor_cs_setup(void) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + writel(0x00020181, &weim_regs->cs0gcr1); + writel(0x00000001, &weim_regs->cs0gcr2); + writel(0x0a020000, &weim_regs->cs0rcr1); + writel(0x0000c000, &weim_regs->cs0rcr2); + writel(0x0804a240, &weim_regs->cs0wcr1); + writel(0x00000120, &weim_regs->wcr); + + set_chipselect_size(CS0_128); +} + +static void setup_iomux_eimnor(void) +{ + imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads)); + + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + + eimnor_cs_setup(); +} + static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); } -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS2__GPIO_6_15, +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS2__GPIO6_IO15, }; static void setup_iomux_uart(void) @@ -138,7 +265,7 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[1] = { {USDHC3_BASE_ADDR}, }; @@ -157,6 +284,63 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable ENFC_CLK_ROOT clock */ + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + int mx6_rgmii_rework(struct phy_device *phydev) { unsigned short val; @@ -192,15 +376,9 @@ int board_phy_config(struct phy_device *phydev) int board_eth_init(bd_t *bis) { - int ret; - setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return 0; + return cpu_eth_init(bis); } #define BOARD_REV_B 0x200 @@ -240,9 +418,69 @@ u32 get_board_rev(void) return (get_cpu_rev() & ~(0xF << 8)) | rev; } +#if defined(CONFIG_VIDEO_IPUV3) +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int board_early_init_f(void) { setup_iomux_uart(); +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif return 0; } @@ -257,11 +495,31 @@ int board_init(void) /* I2C 3 Steer */ gpio_direction_output(IMX_GPIO_NR(5, 4), 1); imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); +#ifndef CONFIG_SYS_FLASH_CFI setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - +#endif gpio_direction_output(IMX_GPIO_NR(1, 15), 1); imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp)); + setup_iomux_eimnor(); + return 0; +} + +#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + +int power_init_board(void) +{ + struct pmic *p; + + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; + return 0; } @@ -301,3 +559,57 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7) +#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1) + +iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_ENET_RX_ER__USB_OTG_ID, +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + if (on) + port_exp_direction_output(USB_OTG_PWR, 1); + else + port_exp_direction_output(USB_OTG_PWR, 0); + break; + case 1: + if (on) + port_exp_direction_output(USB_HOST1_PWR, 1); + else + port_exp_direction_output(USB_HOST1_PWR, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif diff --git a/board/freescale/mx6qsabrelite/Makefile b/board/freescale/mx6qsabrelite/Makefile deleted file mode 100644 index 141437c12f..0000000000 --- a/board/freescale/mx6qsabrelite/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx6qsabrelite.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 02dc289e0e..91ac10dc70 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -354,9 +354,9 @@ static void setup_buttons(void) int setup_sata(void) { - struct iomuxc_base_regs *const iomuxc_regs - = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + struct iomuxc *const iomuxc_regs = (void *)IOMUXC_BASE_ADDR; int ret = enable_sata_clock(); + if (ret) return ret; diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig new file mode 100644 index 0000000000..fa6ddb2292 --- /dev/null +++ b/board/freescale/mx6sabresd/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SABRESD + +config SYS_BOARD + default "mx6sabresd" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6sabresd" + +endif diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS new file mode 100644 index 0000000000..0011ec7b49 --- /dev/null +++ b/board/freescale/mx6sabresd/MAINTAINERS @@ -0,0 +1,8 @@ +MX6SABRESD BOARD +M: Fabio Estevam +S: Maintained +F: board/freescale/mx6sabresd/ +F: include/configs/mx6sabresd.h +F: configs/mx6dlsabresd_defconfig +F: configs/mx6qsabresd_defconfig +F: configs/mx6sabresd_spl_defconfig diff --git a/board/freescale/mx6sabresd/Makefile b/board/freescale/mx6sabresd/Makefile index 240fce99bd..cfca2ef79a 100644 --- a/board/freescale/mx6sabresd/Makefile +++ b/board/freescale/mx6sabresd/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx6sabresd.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx6sabresd.o diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg new file mode 100644 index 0000000000..f35f22ea82 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000030 +DATA 4 0x020e04c0 0x00000030 +DATA 4 0x020e04c4 0x00000030 +DATA 4 0x020e04c8 0x00000030 +DATA 4 0x020e04cc 0x00000030 +DATA 4 0x020e04d0 0x00000030 +DATA 4 0x020e04d4 0x00000030 +DATA 4 0x020e04d8 0x00000030 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000030 +DATA 4 0x020e0770 0x00000030 +DATA 4 0x020e0778 0x00000030 +DATA 4 0x020e077c 0x00000030 +DATA 4 0x020e0780 0x00000030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e0470 0x00000030 +DATA 4 0x020e0474 0x00000030 +DATA 4 0x020e0478 0x00000030 +DATA 4 0x020e047c 0x00000030 +DATA 4 0x020e0480 0x00000030 +DATA 4 0x020e0484 0x00000030 +DATA 4 0x020e0488 0x00000030 +DATA 4 0x020e048c 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x4220021F +DATA 4 0x021b0840 0x0207017E +DATA 4 0x021b483c 0x4201020C +DATA 4 0x021b4840 0x01660172 +DATA 4 0x021b0848 0x4A4D4E4D +DATA 4 0x021b4848 0x4A4F5049 +DATA 4 0x021b0850 0x3F3C3D31 +DATA 4 0x021b4850 0x3238372B +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x0002002D +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x3F435313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00431023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x0002556D +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg new file mode 100644 index 0000000000..bb6c60b4c3 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 + +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 + +DATA 4 0x020e05ac 0x00020030 +DATA 4 0x020e05b4 0x00020030 +DATA 4 0x020e0528 0x00020030 +DATA 4 0x020e0520 0x00020030 + +DATA 4 0x020e0514 0x00020030 +DATA 4 0x020e0510 0x00020030 +DATA 4 0x020e05bc 0x00020030 +DATA 4 0x020e05c4 0x00020030 + +DATA 4 0x020e056c 0x00020030 +DATA 4 0x020e0578 0x00020030 +DATA 4 0x020e0588 0x00020030 +DATA 4 0x020e0594 0x00020030 + +DATA 4 0x020e057c 0x00020030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 + +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 + +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 + +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0750 0x00020000 + +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0798 0x000C0000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b0018 0x00081740 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b002c 0x000026D2 + +DATA 4 0x021b0030 0x005A1023 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 + +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x0408803A +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803B +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038 + +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0800 0xA1380003 +DATA 4 0x021b4800 0xA1380003 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b4818 0x00022227 + +DATA 4 0x021b083c 0x434B0350 +DATA 4 0x021b0840 0x034C0359 +DATA 4 0x021b483c 0x434B0350 +DATA 4 0x021b4840 0x03650348 +DATA 4 0x021b0848 0x4436383B +DATA 4 0x021b4848 0x39393341 +DATA 4 0x021b0850 0x35373933 +DATA 4 0x021b4850 0x48254A36 + +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F + +DATA 4 0x021b480c 0x00440044 +DATA 4 0x021b4810 0x00440044 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b0404 0x00011006 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 288da292d5..215faa98fa 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -12,12 +12,24 @@ #include #include #include +#include #include #include +#include #include #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -32,36 +44,48 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PMIC 1 + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define DISP0_PWR_EN IMX_GPIO_NR(1, 21) + int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - + gd->ram_size = imx_ddr_size(); return 0; } -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const enet_pads[] = { +static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO_1_25, + MX6_PAD_ENET_CRS_DV__GPIO1_IO25, }; static void setup_iomux_enet(void) @@ -74,45 +98,125 @@ static void setup_iomux_enet(void) gpio_set_value(IMX_GPIO_NR(1, 25), 1); } -iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D2__GPIO_2_2, /* CD */ +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02, /* CD */ +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO2_IO00, /* CD */ +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D0__GPIO_2_0, /* CD */ +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW1__GPIO4_IO09, }; -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +static iomux_v3_cfg_t const rgb_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, + MX6_PAD_SD1_DAT3__GPIO1_IO21, +}; + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); + gpio_direction_output(DISP0_PWR_EN, 1); +} + +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} + +iomux_v3_cfg_t const pcie_pads[] = { + MX6_PAD_EIM_D19__GPIO3_IO19, /* POWER */ + MX6_PAD_GPIO_17__GPIO7_IO12, /* RESET */ +}; + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); +} + +iomux_v3_cfg_t const di0_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ }; static void setup_iomux_uart(void) @@ -152,7 +256,8 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; +#ifndef CONFIG_SPL_BUILD + int ret; int i; /* @@ -185,13 +290,53 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +#else + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; } - return status; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif } #endif @@ -228,22 +373,240 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int board_eth_init(bd_t *bis) +#if defined(CONFIG_VIDEO_IPUV3) +static void disable_lvds(struct display_info_t const *dev) { - int ret; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int reg = readl(&iomux->gpr[2]); + + reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_MASK); + + writel(reg, &iomux->gpr[2]); +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + disable_lvds(dev); + imx_enable_hdmi_phy(); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; + writel(reg, &iomux->gpr[2]); +} +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "SEIKO-WVGA", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ + imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK + | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ setup_iomux_enet(); + setup_pcie(); + + return cpu_eth_init(bis); +} + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_EIM_D22__USB_OTG_PWR, + MX6_PAD_ENET_RX_ER__USB_OTG_ID, +}; + +static iomux_v3_cfg_t const usb_hc1_pads[] = { + MX6_PAD_ENET_TXD1__GPIO1_IO29, +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + + imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, + ARRAY_SIZE(usb_hc1_pads)); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + if (on) + gpio_direction_output(IMX_GPIO_NR(1, 29), 1); + else + gpio_direction_output(IMX_GPIO_NR(1, 29), 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } return 0; } +#endif int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } @@ -253,9 +616,49 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } +int power_init_board(void) +{ + struct pmic *p; + unsigned int reg; + + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; + + /* Increase VGEN3 from 2.5 to 2.8V */ + pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ @@ -272,7 +675,6 @@ int board_late_init(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif - return 0; } @@ -281,3 +683,169 @@ int checkboard(void) puts("Board: MX6-SabreSD\n"); return 0; } + +#ifdef CONFIG_SPL_BUILD +#include +#include + +const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + .p0_mpdgctrl0 = 0x434B0350, + .p0_mpdgctrl1 = 0x034C0359, + .p1_mpdgctrl0 = 0x434B0350, + .p1_mpdgctrl1 = 0x03650348, + .p0_mprddlctl = 0x4436383B, + .p1_mprddlctl = 0x39393341, + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254A36, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +/* + * This section requires the differentiation between iMX6 Sabre boards, but + * for now, it will configure only for the mx6q variant. + */ +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = mem_ddr.width/32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig new file mode 100644 index 0000000000..d32da900a3 --- /dev/null +++ b/board/freescale/mx6slevk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SLEVK + +config SYS_BOARD + default "mx6slevk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6slevk" + +endif diff --git a/board/freescale/mx6slevk/MAINTAINERS b/board/freescale/mx6slevk/MAINTAINERS new file mode 100644 index 0000000000..18d31a8d8b --- /dev/null +++ b/board/freescale/mx6slevk/MAINTAINERS @@ -0,0 +1,7 @@ +MX6SLEVK BOARD +M: Fabio Estevam +S: Maintained +F: board/freescale/mx6slevk/ +F: include/configs/mx6slevk.h +F: configs/mx6slevk_defconfig +F: configs/mx6slevk_spinor_defconfig diff --git a/board/freescale/mx6slevk/Makefile b/board/freescale/mx6slevk/Makefile index bcd8e4a3c2..6e1971ee27 100644 --- a/board/freescale/mx6slevk/Makefile +++ b/board/freescale/mx6slevk/Makefile @@ -3,23 +3,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx6slevk.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mx6slevk.o diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 5b6ef81a4b..838ea6c0f0 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -13,11 +13,15 @@ #include #include #include +#include #include -#include +#include #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -29,6 +33,15 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ETH_PHY_RESET IMX_GPIO_NR(4, 21) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -41,6 +54,23 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc1_pads[] = { + /* 8 bit SD */ + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -48,33 +78,217 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec_pads[] = { + MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#ifdef CONFIG_MXC_SPI +static iomux_v3_cfg_t ecspi1_pads[] = { + MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1; +} + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} +#endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR}, +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); + + /* Reset LAN8720 PHY */ + gpio_direction_output(ETH_PHY_RESET , 0); + udelay(1000); + gpio_set_value(ETH_PHY_RESET, 1); +} + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, }; int board_mmc_getcd(struct mmc *mmc) { - return 1; /* Assume boot SD always present */ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize " + "mmc dev %d\n", i); + return ret; + } + } + + return 0; } +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + setup_iomux_fec(); + + return cpu_eth_init(bis); +} + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* clear gpr1[14], gpr1[18:17] to select anatop clock */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); + + return enable_fec_anatop_clock(ENET_50MHZ); +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OTG1 */ + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif return 0; } @@ -83,12 +297,15 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - return 0; -} +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif -u32 get_board_rev(void) -{ - return get_cpu_rev(); +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; } int checkboard(void) diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig new file mode 100644 index 0000000000..940983e932 --- /dev/null +++ b/board/freescale/mx6sxsabresd/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SXSABRESD + +config SYS_BOARD + default "mx6sxsabresd" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6sxsabresd" + +endif diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS new file mode 100644 index 0000000000..f52f300bed --- /dev/null +++ b/board/freescale/mx6sxsabresd/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SXSABRESD BOARD +M: Fabio Estevam +S: Maintained +F: board/freescale/mx6sxsabresd/ +F: include/configs/mx6sxsabresd.h +F: configs/mx6sxsabresd_defconfig diff --git a/board/freescale/mx6sxsabresd/Makefile b/board/freescale/mx6sxsabresd/Makefile new file mode 100644 index 0000000000..97dbfda517 --- /dev/null +++ b/board/freescale/mx6sxsabresd/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sxsabresd.o diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg new file mode 100644 index 0000000000..c862617094 --- /dev/null +++ b/board/freescale/mx6sxsabresd/imximage.cfg @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* Clock */ +DATA 4 0x020e032c 0x00000030 + +/* Address */ +DATA 4 0x020e0300 0x00000020 +DATA 4 0x020e02fc 0x00000020 +DATA 4 0x020e05f4 0x00000020 + +/* Control */ +DATA 4 0x020e0340 0x00000020 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000020 +DATA 4 0x020e0314 0x00000020 +DATA 4 0x020e0614 0x00000020 + +/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000028 +DATA 4 0x020e0334 0x00000028 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e033c 0x00000028 + +/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003 + +/* Write leveling */ +DATA 4 0x021b080c 0x00290025 +DATA 4 0x021b0810 0x00220022 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x41480144 +DATA 4 0x021b0840 0x01340130 + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x3C3E4244 +DATA 4 0x021b0850 0x34363638 + +/* Read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 + +/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00048031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c new file mode 100644 index 0000000000..5cc58ac868 --- /dev/null +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -0,0 +1,436 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* RST_B, used for power reset cycle */ + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const peri_3v3_pads[] = { + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const phy_control_pads[] = { + /* 25MHz Ethernet PHY Clock */ + MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + + /* ENET PHY Power */ + MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* AR8031 PHY Reset */ + MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg; + + /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + imx_iomux_v3_setup_multiple_pads(phy_control_pads, + ARRAY_SIZE(phy_control_pads)); + + /* Enable the ENET power, active low */ + gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); + + /* Reset AR8031 PHY */ + gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + + reg = readl(&anatop->pll_enet); + reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; + writel(reg, &anatop->pll_enet); + + return enable_fec_anatop_clock(ENET_125MHZ); +} + +int board_eth_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + setup_fec(); + + return cpu_eth_init(bis); +} + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +int power_init_board(void) +{ + struct pmic *p; + unsigned int reg; + + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; + + /* Enable power of VGEN5 3V3, needed for SD3 */ + pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= (LDOB_3_30V | (1 << LDO_EN)); + pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OGT1 */ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ + imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, + ARRAY_SIZE(peri_3v3_pads)); + + /* Active high for ncp692 */ + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /* Assume uSDHC2 is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = !gpio_get_value(USDHC4_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC3 + * mmc2 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +#ifdef CONFIG_FSL_QSPI + +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6SX SABRE SDB\n"); + + return 0; +} diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig new file mode 100644 index 0000000000..b0a7a8d9df --- /dev/null +++ b/board/freescale/p1010rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P1010RDB + +config SYS_BOARD + default "p1010rdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P1010RDB" + +endif diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS new file mode 100644 index 0000000000..db001437b1 --- /dev/null +++ b/board/freescale/p1010rdb/MAINTAINERS @@ -0,0 +1,33 @@ +P1010RDB BOARD +#M: - +S: Maintained +F: board/freescale/p1010rdb/ +F: include/configs/P1010RDB.h +F: configs/P1010RDB-PA_36BIT_NAND_defconfig +F: configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +F: configs/P1010RDB-PA_36BIT_NOR_defconfig +F: configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +F: configs/P1010RDB-PA_36BIT_SDCARD_defconfig +F: configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +F: configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +F: configs/P1010RDB-PA_NAND_defconfig +F: configs/P1010RDB-PA_NAND_SECBOOT_defconfig +F: configs/P1010RDB-PA_NOR_defconfig +F: configs/P1010RDB-PA_NOR_SECBOOT_defconfig +F: configs/P1010RDB-PA_SDCARD_defconfig +F: configs/P1010RDB-PA_SPIFLASH_defconfig +F: configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig +F: configs/P1010RDB-PB_36BIT_NAND_defconfig +F: configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +F: configs/P1010RDB-PB_36BIT_NOR_defconfig +F: configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +F: configs/P1010RDB-PB_36BIT_SDCARD_defconfig +F: configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +F: configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +F: configs/P1010RDB-PB_NAND_defconfig +F: configs/P1010RDB-PB_NAND_SECBOOT_defconfig +F: configs/P1010RDB-PB_NOR_defconfig +F: configs/P1010RDB-PB_NOR_SECBOOT_defconfig +F: configs/P1010RDB-PB_SDCARD_defconfig +F: configs/P1010RDB-PB_SPIFLASH_defconfig +F: configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile index bdd7d68edc..660d1bbc2a 100644 --- a/board/freescale/p1010rdb/Makefile +++ b/board/freescale/p1010rdb/Makefile @@ -4,10 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -18,29 +14,17 @@ endif ifdef MINIMAL -COBJS-y += spl_minimal.o tlb.o law.o +obj-y += spl_minimal.o tlb.o law.o else -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - +ifdef CONFIG_SPL_BUILD +obj-y += spl.o endif -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) +obj-y += p1010rdb.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +endif diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README deleted file mode 100644 index 7f18aaa1b2..0000000000 --- a/board/freescale/p1010rdb/README +++ /dev/null @@ -1,208 +0,0 @@ -Overview -========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB board features are as follows: -Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5” 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port via an external ULPI PHY to micro-AB connector - - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector - - FlexCAN ports: - - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - RJ45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM interface. - SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to POTS -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) - - -Physical Memory Map on P1010RDB -=============================== -Address Start Address End Memory type Attributes -0x0000_0000 0x3fff_ffff DDR 1G Cacheable -0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable -0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable -0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable -0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable -0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 -0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash -Note: 1 stands for 'on', 0 stands for 'off' - - -Setting of hwconfig -=================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn u-boot to NOR flash -================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -================== -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef80000 +$filesize - => erase eef80000 +$filesize - => cp.b $loadaddr eef80000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn u-boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - -Build and burn u-boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -Please contact your local field applications engineer or sales representative -to obtain related documents, such as P1010-RDB User Guide for details. diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA new file mode 100644 index 0000000000..cde246dde2 --- /dev/null +++ b/board/freescale/p1010rdb/README.P1010RDB-PA @@ -0,0 +1,208 @@ +Overview +========= +The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), +that addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB board features are as follows: +Memory subsystem: + - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32 Mbyte NOR flash single-chip memory + - 32 Mbyte NAND flash memory + - 256 Kbit M24256 I2C EEPROM + - 16 Mbyte SPI memory + - I2C Board EEPROM 128x8 bit memory + - SD/MMC connector to interface with the SD memory card +Interfaces: + - PCIe: + - Lane0: x1 mini-PCIe slot + - Lane1: x1 PCIe standard slot + - SATA: + - 1 internal SATA connector to 2.5” 160G SATA2 HDD + - 1 eSATA connector to rear panel + - 10/100/1000 BaseT Ethernet ports: + - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO + - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - USB 2.0 port: + - x1 USB2.0 port via an external ULPI PHY to micro-AB connector + - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector + - FlexCAN ports: + - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) + interface; + - DUART interface: + - DUART interface: supports two UARTs up to 115200 bps for + console display + - RJ45 connectors are used for these 2 UART ports. + - TDM + - 2 FXS ports connected via an external SLIC to the TDM interface. + SLIC is controllled via SPI. + - 1 FXO port connected via a relay to FXS for switchover to POTS +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging +IEEE Std. 1588 signals for test and measurement +Real-time clock on I2C bus +POR + - support critical POR setting changed via switch on board +PCB + - 6-layer routing (4-layer signals, 2-layer power and ground) + + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + + +Serial Port Configuration on P1010RDB +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + + +Settings of DIP-switch +====================== + SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash + SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash + SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash +Note: 1 stands for 'on', 0 stands for 'off' + + +Setting of hwconfig +=================== +If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or +"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: +setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" +By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection +is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM +instead of to CAN/UART1. + + +Build and burn u-boot to NOR flash +================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NOR + +2. Burn u-boot.bin into NOR flash + => tftp $loadaddr $uboot + => protect off eff40000 +$filesize + => erase eff40000 +$filesize + => cp.b $loadaddr eff40000 $filesize + +3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. + + +Alternate NOR bank +================== +1. Burn u-boot.bin into alternate NOR bank + => tftp $loadaddr $uboot + => protect off eef40000 +$filesize + => erase eef40000 +$filesize + => cp.b $loadaddr eef40000 $filesize + +2. Switch to alternate NOR bank + => mw.b ffb00009 1 + => reset + or set SW1[8]= ON + +SW1[8]= OFF: Upper bank used for booting start +SW1[8]= ON: Lower bank used for booting start +CPLD NOR bank selection register address 0xFFB00009 Bit[0]: +0 - boot from upper 4 sectors +1 - boot from lower 4 sectors + + +Build and burn u-boot to NAND flash +=================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NAND + +2. Burn u-boot-nand.bin into NAND flash + => tftp $loadaddr $uboot-nand + => nand erase 0 $filesize + => nand write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. + + +Build and burn u-boot to SPI flash +================================== +1. Build u-boot-spi.bin image + make P1010RDB_SPIFLASH_config; make + Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb + Download u-boot.bin to linux and you can find some config files + under /usr/share such as config_xx.dat. Do below command: + boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ + u-boot-spi.bin + to generate u-boot-spi.bin. + +2. Burn u-boot-spi.bin into SPI flash + => tftp $loadaddr $uboot-spi + => sf erase 0 100000 + => sf write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. + + +CPLD POR setting registers +========================== +1. Set POR switch selection register (addr 0xFFB00011) to 0. +2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with + proper values. + If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 + switch command by I2C. +3. Send reset command. + After reset, the new POR setting will be implemented. + +Two examples are given in below: +Switch from NOR to NAND boot with default frequency: + => i2c dev 0 + => i2c mw 18 1 f9 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00017 1 + => reset +Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): + => i2c dev 0 + => i2c mw 18 1 f1 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00014 2 + => mw.b ffb00015 5 + => mw.b ffb00016 3 + => mw.b ffb00017 f + => reset + + +Boot Linux from network using TFTP on P1010RDB +============================================== +Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + + +For more details, please refer to P1010RDB User Guide and access website +www.freescale.com diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB new file mode 100644 index 0000000000..c5d1419445 --- /dev/null +++ b/board/freescale/p1010rdb/README.P1010RDB-PB @@ -0,0 +1,188 @@ +Overview +========= +The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC. +P1010RDB-PB is a variation of previous P1010RDB-PA board. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that +addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB-PB board features are as following: +Memory subsystem: + - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32M bytes NOR flash single-chip memory + - 2G bytes NAND flash memory + - 16M bytes SPI memory + - 256K bit M24256 I2C EEPROM + - I2C Board EEPROM 128x8 bit memory + - SD/MMC connector to interface with the SD memory card +Interfaces: + - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII) + - PCIe 2.0: two x1 mini-PCIe slots + - SATA 2.0: two SATA interfaces + - USB 2.0: one USB interface + - FlexCAN: two FlexCAN interfaces (revision 2.0B) + - UART: one USB-to-Serial interface + - TDM: 2 FXS ports connected via an external SLIC to the TDM interface. + 1 FXO port connected via a relay to FXS for switchover to POTS + +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging + +POR: support critical POR setting changed via switch on board +PCB: 6-layer routing (4-layer signals, 2-layer power and ground) + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + + +Serial Port Configuration on P1010RDB +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + + +P1010RDB-PB default DIP-switch settings +======================================= +SW1[1:8]= 10101010 +SW2[1:8]= 11011000 +SW3[1:8]= 10010000 +SW4[1:4]= 1010 +SW5[1:8]= 11111010 + + +P1010RDB-PB boot mode settings via DIP-switch +============================================= +SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot +SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot +SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot +SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot +Note: 1 stands for 'on', 0 stands for 'off' + + +Switch P1010RDB-PB boot mode via software without setting DIP-switch +==================================================================== +=> run boot_bank0 (boot from NOR bank0) +=> run boot_bank1 (boot from NOR bank1) +=> run boot_nand (boot from NAND flash) +=> run boot_spi (boot from SPI flash) +=> run boot_sd (boot from SD card) + + +Frequency combination support on P1010RDB-PB +============================================= +SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s) +0101 1 1010 0 800 400 800 +1001 1 1010 0 800 400 667 +1010 1 1100 0 667 333 667 +1000 0 1010 0 533 266 667 +0101 1 1010 1 1000 400 800 +1001 1 1010 1 1000 400 667 + + +Setting of pin mux +================== +Since pins multiplexing, TDM and CAN are muxed with SPI flash. +SDHC is muxed with IFC. IFC and SPI flash are enabled by default. + +To enable TDM: +=> setenv hwconfig fsl_p1010mux:tdm_can=tdm +=> save;reset + +To enable FlexCAN: +=> setenv hwconfig fsl_p1010mux:tdm_can=can +=> save;reset + +To enable SDHC in case of NOR/NAND/SPI boot + a) For temporary use case in runtime without reboot system + run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. + + b) For long-term use case + set 'esdhc' in hwconfig and save it. + +To enable IFC in case of SD boot + a) For temporary use case in runtime without reboot system + run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. + + b) For long-term use case + set 'ifc' in hwconfig and save it. + + +Build images for different boot mode +==================================== +First setup cross compile environment on build host + $ export ARCH=powerpc + $ export CROSS_COMPILE=/powerpc-linux-gnu- + +1. For NOR boot + $ make P1010RDB-PB_NOR + +2. For NAND boot + $ make P1010RDB-PB_NAND + +3. For SPI boot + $ make P1010RDB-PB_SPIFLASH + +4. For SD boot + $ make P1010RDB-PB_SDCARD + + +Steps to program images to flash for different boot mode +======================================================== +1. NOR boot + => tftp 1000000 u-boot.bin + For bank0 + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + + For bank1 + => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize + set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + +2. NAND boot + => tftp 1000000 u-boot-nand.bin + => nand erase 0 $filesize; nand write $loadaddr 0 $filesize + Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board + +3. SPI boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin + 2) => tftp 1000000 u-boot-spi-combined.bin + 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000 + set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board + +4. SD boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin + 2) => tftp 1000000 u-boot-sd-combined.bin + 3) => mux sdhc + 4) => mmc write 1000000 0 1050 + set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board + + +Boot Linux from network using TFTP on P1010RDB-PB +================================================= +Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + + +For more details, please refer to P1010RDB-PB User Guide and access website +www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index aa8badab48..b0d95ea006 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include @@ -139,7 +139,7 @@ phys_size_t fixed_sdram(void) } ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { @@ -172,20 +172,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1875, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1875, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index 004512725f..ed41a056c5 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -9,11 +9,9 @@ #include struct law_entry law_table[] = { -#ifndef CONFIG_SDCARD SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 06aa8009b5..1cf0ab78b7 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -19,12 +19,10 @@ #include #include #include -#include +#include #include - -#ifndef CONFIG_SDCARD #include -#endif +#include DECLARE_GLOBAL_DATA_PTR; @@ -33,10 +31,30 @@ DECLARE_GLOBAL_DATA_PTR; #define MUX_CPLD_TDM 0x01 #define MUX_CPLD_SPICS0_FLASH 0x00 #define MUX_CPLD_SPICS0_SLIC 0x02 +#define PMUXCR1_IFC_MASK 0x00ffff00 +#define PMUXCR1_SDHC_MASK 0x00fff000 +#define PMUXCR1_SDHC_ENABLE 0x00555000 + +enum { + MUX_TYPE_IFC, + MUX_TYPE_SDHC, + MUX_TYPE_SPIFLASH, + MUX_TYPE_TDM, + MUX_TYPE_CAN, + MUX_TYPE_CS0_NOR, + MUX_TYPE_CS0_NAND, +}; + +enum { + I2C_READ_BANK, + I2C_READ_PCB_VER, +}; + +static uint sd_ifc_mux; -#ifndef CONFIG_SDCARD struct cpld_data { u8 cpld_ver; /* cpld revision */ +#if defined(CONFIG_P1010RDB_PA) u8 pcba_ver; /* pcb revision number */ u8 twindie_ddr3; u8 res1[6]; @@ -51,53 +69,18 @@ struct cpld_data { u8 por1; /* POR Options */ u8 por2; /* POR Options */ u8 por3; /* POR Options */ -}; - -void cpld_show(void) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - printf("CPLD: V%x.%x PCBA: V%x.0\n", - in_8(&cpld_data->cpld_ver) & 0xF0, - in_8(&cpld_data->cpld_ver) & 0x0F, - in_8(&cpld_data->pcba_ver) & 0x0F); - -#ifdef CONFIG_DEBUG - printf("twindie_ddr =%x\n", - in_8(&cpld_data->twindie_ddr3)); - printf("bank_sel =%x\n", - in_8(&cpld_data->bank_sel)); - printf("usb2_sel =%x\n", - in_8(&cpld_data->usb2_sel)); - printf("porsw_sel =%x\n", - in_8(&cpld_data->porsw_sel)); - printf("tdm_can_sel =%x\n", - in_8(&cpld_data->tdm_can_sel)); - printf("tdm_can_sel =%x\n", - in_8(&cpld_data->tdm_can_sel)); - printf("spi_cs0_sel =%x\n", - in_8(&cpld_data->spi_cs0_sel)); - printf("bcsr0 =%x\n", - in_8(&cpld_data->bcsr0)); - printf("bcsr1 =%x\n", - in_8(&cpld_data->bcsr1)); - printf("bcsr2 =%x\n", - in_8(&cpld_data->bcsr2)); - printf("bcsr3 =%x\n", - in_8(&cpld_data->bcsr3)); -#endif -} +#elif defined(CONFIG_P1010RDB_PB) + u8 rom_loc; #endif +}; int board_early_init_f(void) { ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); -#ifndef CONFIG_SDCARD struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); -#endif /* * Reset PCIe slots via GPIO4 */ @@ -109,9 +92,8 @@ int board_early_init_f(void) int board_early_init_r(void) { -#ifndef CONFIG_SDCARD const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -122,8 +104,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -133,7 +121,6 @@ int board_early_init_r(void) CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); -#endif return 0; } @@ -144,13 +131,199 @@ void pci_init_board(void) } #endif /* ifdef CONFIG_PCI */ +int config_board_mux(int ctrl_type) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u8 tmp; + +#if defined(CONFIG_P1010RDB_PA) + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + switch (ctrl_type) { + case MUX_TYPE_IFC: + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + tmp = 0xf0; + i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); + tmp = 0x01; + i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + tmp = 0xf0; + i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); + tmp = 0x05; + i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + break; + case MUX_TYPE_TDM: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + break; + case MUX_TYPE_CAN: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + break; + default: + break; + } +#elif defined(CONFIG_P1010RDB_PB) + uint orig_bus = i2c_get_bus_num(); + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + + switch (ctrl_type) { + case MUX_TYPE_IFC: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x80); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x80); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_TDM: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x82); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x82); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CAN: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x02); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x02); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CS0_NOR: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CS0_NAND: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + default: + break; + } + i2c_set_bus_num(orig_bus); +#endif + return 0; +} + +#ifdef CONFIG_P1010RDB_PB +int i2c_pca9557_read(int type) +{ + u8 val; + + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); + + switch (type) { + case I2C_READ_BANK: + val = (val & 0x10) >> 4; + break; + case I2C_READ_PCB_VER: + val = ((val & 0x60) >> 5) + 1; + break; + default: + break; + } + + return val; +} +#endif + int checkboard(void) { struct cpu_type *cpu; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 val; cpu = gd->arch.cpu; - printf("Board: %sRDB\n", cpu->name); +#if defined(CONFIG_P1010RDB_PA) + printf("Board: %sRDB-PA, ", cpu->name); +#elif defined(CONFIG_P1010RDB_PB) + printf("Board: %sRDB-PB, ", cpu->name); + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); + val = 0x0; /* no polarity inversion */ + i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); +#endif +#ifdef CONFIG_SDCARD + /* switch to IFC to read info from CPLD */ + config_board_mux(MUX_TYPE_IFC); +#endif + +#if defined(CONFIG_P1010RDB_PA) + val = (in_8(&cpld_data->pcba_ver) & 0xf); + printf("PCB: v%x.0\n", val); +#elif defined(CONFIG_P1010RDB_PB) + val = in_8(&cpld_data->cpld_ver); + printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); + printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); + val = in_8(&cpld_data->rom_loc) & 0xf; + puts("Boot from: "); + switch (val) { + case 0xf: + config_board_mux(MUX_TYPE_CS0_NOR); + printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); + break; + case 0xe: + puts("SDHC\n"); + val = 0x60; /* set pca9557 pin input/output */ + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); + break; + case 0x5: + config_board_mux(MUX_TYPE_IFC); + config_board_mux(MUX_TYPE_CS0_NAND); + puts("NAND\n"); + break; + case 0x6: + config_board_mux(MUX_TYPE_IFC); + puts("SPI\n"); + break; + default: + puts("unknown\n"); + break; + } +#endif return 0; } @@ -246,6 +419,16 @@ void fdt_del_sdhc(void *blob) } } +void fdt_del_ifc(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,ifc")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + void fdt_disable_uart1(void *blob) { int nodeoff; @@ -261,7 +444,7 @@ void fdt_disable_uart1(void *blob) } } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -289,9 +472,13 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_del_flexcan(blob); fdt_del_node_and_alias(blob, "ethernet2"); } -#ifndef CONFIG_SDCARD - /* disable sdhc due to sdhc bug */ - fdt_del_sdhc(blob); + + /* Delete IFC node as IFC pins are multiplexing with SDHC */ + if (sd_ifc_mux != MUX_TYPE_IFC) + fdt_del_ifc(blob); + else + fdt_del_sdhc(blob); + if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { fdt_del_tdm(blob); fdt_del_spi_slic(blob); @@ -309,14 +496,29 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_del_flexcan(blob); fdt_disable_uart1(blob); } + + return 0; +} #endif + +#ifdef CONFIG_SDCARD +int board_mmc_init(bd_t *bis) +{ + config_board_mux(MUX_TYPE_SDHC); + return -1; +} +#else +void board_reset(void) +{ + /* mux to IFC to enable CPLD for reset */ + if (sd_ifc_mux != MUX_TYPE_IFC) + config_board_mux(MUX_TYPE_IFC); } #endif -#ifndef CONFIG_SDCARD + int misc_init_r(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { @@ -324,7 +526,7 @@ int misc_init_r(void) MPC85xx_PMUXCR_CAN1_UART | MPC85xx_PMUXCR_CAN2_TDM | MPC85xx_PMUXCR_CAN2_UART); - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + config_board_mux(MUX_TYPE_CAN); } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | MPC85xx_PMUXCR_CAN1_UART); @@ -332,13 +534,39 @@ int misc_init_r(void) MPC85xx_PMUXCR_CAN1_TDM); clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + config_board_mux(MUX_TYPE_TDM); } else { /* defaultly spi_cs_sel to flash */ - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + config_board_mux(MUX_TYPE_SPIFLASH); } + if (hwconfig("esdhc")) + config_board_mux(MUX_TYPE_SDHC); + else if (hwconfig("ifc")) + config_board_mux(MUX_TYPE_IFC); + +#ifdef CONFIG_P1010RDB_PB + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); +#endif return 0; } -#endif + +static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "ifc") == 0) + config_board_mux(MUX_TYPE_IFC); + else if (strcmp(argv[1], "sdhc") == 0) + config_board_mux(MUX_TYPE_SDHC); + else + return CMD_RET_USAGE; + return 0; +} + +U_BOOT_CMD( + mux, 2, 0, pin_mux_cmd, + "configure multiplexing pin for IFC/SDHC bus in runtime", + "bus_type (e.g. mux sdhc)" +); diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c new file mode 100644 index 0000000000..11bd9cfccc --- /dev/null +++ b/board/freescale/p1010rdb/spl.c @@ -0,0 +1,108 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + console_init_f(); + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + +#ifdef CONFIG_P1010RDB_PB + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + + i2c_init_all(); + + gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("\nTertiary program loader running in sram..."); +#else + puts("\nSecond program loader running in sram..."); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 73289f3656..607957003d 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -10,83 +10,22 @@ #include #include #include -#include +#include #include #include DECLARE_GLOBAL_DATA_PTR; - -void sdram_init(void) -{ - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u32 ddr_ratio; - unsigned long ddr_freq_mhz; - - ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; - ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; - ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; - - /* mask off E bit */ - u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); - - __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - - if (ddr_freq_mhz < 700) { - __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); - } else { - __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); - } - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - - /* P1014 and it's derivatives support max 16bit DDR width */ - if (svr == SVR_P1014) { - __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); - __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); - /* For CS0_BNDS we divide the start and end address by 2, so we can just - * shift the entire register to achieve the desired result and the mask - * the value so we don't write reserved fields */ - __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); - } - - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - - set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); -} - void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif + /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; @@ -97,9 +36,6 @@ void board_init_f(ulong bootflag) puts("\nNAND boot... "); - /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -110,6 +46,7 @@ void board_init_f(ulong bootflag) void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); } diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 77a80435a2..af40f979d3 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), @@ -42,7 +42,6 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_1M, 1), #ifndef CONFIG_SPL_BUILD -#ifndef CONFIG_SDCARD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), @@ -51,7 +50,6 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 3, BOOKE_PAGESZ_16M, 1), -#endif #ifdef CONFIG_PCI /* *I*G* - PCI */ @@ -66,7 +64,6 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #endif -#ifndef CONFIG_SDCARD /* *I*G - Board CPLD */ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -75,12 +72,19 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), -#endif -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1) + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) #endif }; diff --git a/board/freescale/p1022ds/Kconfig b/board/freescale/p1022ds/Kconfig new file mode 100644 index 0000000000..f1792de8e3 --- /dev/null +++ b/board/freescale/p1022ds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P1022DS + +config SYS_BOARD + default "p1022ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P1022DS" + +endif diff --git a/board/freescale/p1022ds/MAINTAINERS b/board/freescale/p1022ds/MAINTAINERS new file mode 100644 index 0000000000..86aac365d3 --- /dev/null +++ b/board/freescale/p1022ds/MAINTAINERS @@ -0,0 +1,13 @@ +P1022DS BOARD +M: Timur Tabi +S: Maintained +F: board/freescale/p1022ds/ +F: include/configs/P1022DS.h +F: configs/P1022DS_defconfig +F: configs/P1022DS_36BIT_defconfig +F: configs/P1022DS_36BIT_NAND_defconfig +F: configs/P1022DS_36BIT_SDCARD_defconfig +F: configs/P1022DS_36BIT_SPIFLASH_defconfig +F: configs/P1022DS_NAND_defconfig +F: configs/P1022DS_SDCARD_defconfig +F: configs/P1022DS_SPIFLASH_defconfig diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index cfc05f7124..a5821277ef 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -4,10 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -18,29 +14,16 @@ endif ifdef MINIMAL -COBJS-y += spl_minimal.o tlb.o law.o +obj-y += spl_minimal.o tlb.o law.o else -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -COBJS-$(CONFIG_FSL_DIU_FB) += diu.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o endif +obj-y += p1022ds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_FSL_DIU_FB) += diu.o +endif diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c index a639861dae..09212bcee8 100644 --- a/board/freescale/p1022ds/ddr.c +++ b/board/freescale/p1022ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; @@ -17,7 +17,7 @@ struct board_specific_parameters { u32 clk_adjust; /* Range: 0-8 */ u32 cpo; /* Range: 2-31 */ u32 write_data_delay; /* Range: 0-6 */ - u32 force_2T; + u32 force_2t; }; /* @@ -72,7 +72,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -88,7 +88,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 3d1951cdba..d7dd478dff 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -249,7 +249,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -260,8 +260,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -326,7 +332,7 @@ static void ft_codec_setup(void *blob, const char *compatible) } } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -350,5 +356,7 @@ void ft_board_setup(void *blob, bd_t *bd) /* Update the WM8776 node's clock frequency property */ ft_codec_setup(blob, "wlf,wm8776"); + + return 0; } #endif diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c new file mode 100644 index 0000000000..7bd9d296ee --- /dev/null +++ b/board/freescale/p1022ds/spl.c @@ -0,0 +1,125 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "../common/ngpixis.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, sys_clk, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + +#ifdef CONFIG_SPL_SPI_BOOT + /* Enable the SPI */ + clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); +#endif + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + +#ifdef CONFIG_SYS_I2C + i2c_init_all(); +#else + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("Tertiary program loader running in sram..."); +#else + puts("Second program loader running in sram...\n"); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c index d150d95a2f..6c7e1ac3cb 100644 --- a/board/freescale/p1022ds/spl_minimal.c +++ b/board/freescale/p1022ds/spl_minimal.c @@ -9,54 +9,9 @@ #include #include #include -#include +#include -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -void sdram_init(void) -{ - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); -#endif - __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - - __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); - - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, - &ddr->sdram_cfg); - - in_be32(&ddr->sdram_cfg); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - in_be32(&ddr->sdram_cfg); - - set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); -} - const static u32 sysclk_tbl[] = { 66666000, 7499900, 83332500, 8999900, 99999000, 11111000, 12499800, 13333200 @@ -68,6 +23,10 @@ void board_init_f(ulong bootflag) u32 plat_ratio, sys_clk, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif /* for FPGA */ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); @@ -83,9 +42,6 @@ void board_init_f(ulong bootflag) puts("\nNAND boot... "); - /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -96,6 +52,7 @@ void board_init_f(ulong bootflag) void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); } diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index 2eef6adbfa..e7ae2e25b2 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -71,25 +71,32 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1), + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_1G, 1), + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1G, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16K, 1), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16K, 1), #endif +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1023rdb/Kconfig b/board/freescale/p1023rdb/Kconfig new file mode 100644 index 0000000000..1e4cd10c6c --- /dev/null +++ b/board/freescale/p1023rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P1023RDB + +config SYS_BOARD + default "p1023rdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P1023RDB" + +endif diff --git a/board/freescale/p1023rdb/MAINTAINERS b/board/freescale/p1023rdb/MAINTAINERS new file mode 100644 index 0000000000..c06bac6d0d --- /dev/null +++ b/board/freescale/p1023rdb/MAINTAINERS @@ -0,0 +1,6 @@ +P1023RDB BOARD +#M: - +S: Maintained +F: board/freescale/p1023rdb/ +F: include/configs/P1023RDB.h +F: configs/P1023RDB_defconfig diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile index edd2e6daa0..e4f1edf17d 100644 --- a/board/freescale/p1023rdb/Makefile +++ b/board/freescale/p1023rdb/Makefile @@ -4,27 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += p1023rdb.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c index ce406b2b82..d587df527a 100644 --- a/board/freescale/p1023rdb/ddr.c +++ b/board/freescale/p1023rdb/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include @@ -33,20 +33,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1875, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 18000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1875, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 18000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, @@ -86,4 +86,3 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; } } - diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c index b52b092069..56f561a505 100644 --- a/board/freescale/p1023rdb/p1023rdb.c +++ b/board/freescale/p1023rdb/p1023rdb.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -57,7 +57,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -68,8 +68,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -124,7 +130,7 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -141,5 +147,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_fman_ethernet(blob); + + return 0; } #endif diff --git a/board/freescale/p1023rds/Makefile b/board/freescale/p1023rds/Makefile deleted file mode 100644 index f987dc5650..0000000000 --- a/board/freescale/p1023rds/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright 2010-2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/p1023rds/README b/board/freescale/p1023rds/README deleted file mode 100644 index 685f5daa99..0000000000 --- a/board/freescale/p1023rds/README +++ /dev/null @@ -1,101 +0,0 @@ -Overview --------- -The P1023 process includes a performance optimized implementation of the -QorIQ data Path Acceleration Architecture (DPAA). This architecture -provides the infrastructure to support simplified sharing of networking -interfaces and accelerators by multiple CPU cores. P1023 is an e500 based -dual core SOC. - -P1023RDS board is a Low End Dual core platform supporting the P1023 -processor of QorIQ series. - -Building U-boot ---------------- -To build the u-boot for P1023RDS: -Configure to NOR boot: - make P1023RDS_config -Configure to NAND boot: - make P1023RDS_NAND_config -Build: - make - -Board Switches --------------- -Most switches on the board should not be changed. The most frequent -user-settable switches on the board are used to configure -the flash banks. - -J4: all open - -Default NOR flash boot switch setting: - Sw3[1:8]: off on on off on on off off - Sw4[1:8]: off off off on off off off off - Sw6[1:8]: off on off on off on on off - Sw7[1:8]: off on off off on off off off - Sw8[1:8]: on off off off off off off off - -For NAND flash boot,set -Sw4[1:4]: off on on on - -The default native ethernet setting is for RGMII mode. -To use SGMII mode, set -SW8[1:2]: OFF OFF -SW7[6:7]: ON ON - -Memory Map ----------- -0x0000_0000 0x7fff_ffff DDR 2G Cacheable -0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable -0xc000_0000 0xdfff_ffff PCI 512M non-cacheable -0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - -0xe000_0000 0xe003_ffff BCSR 256K BCSR -0xee00_0000 0xefff_ffff NOR flash 32M NOR flash -0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M -0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable -0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - -Flashing u-boot Images ---------------- -To program the image in the boot flash bank: -NOR flash boot: - => tftp 1000000 u-boot.bin - => protect off all - => erase eff80000 efffffff - => cp.b 1000000 eff80000 80000 - -NAND flash boot: - => tftp 1000000 u-boot-nand.bin - => nand erase 0 80000 - => nand write 1000000 0 80000 - -Firmware ucode location ---------------------------------- -Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work. -u-boot loads ucode FLASH. The location for ucode: -NOR Flash: 0xfe000000 -NAND Flash: 0x1f00000 - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/p1023rds.dts -or - make p1023rds.dtb ARCH=powerpc -in linux-2.6 directory. - -Booting Linux -------------- -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp c00000 p1023rds.dtb - bootm 1000000 2000000 c00000 diff --git a/board/freescale/p1023rds/bcsr.h b/board/freescale/p1023rds/bcsr.h deleted file mode 100644 index a9deb72f78..0000000000 --- a/board/freescale/p1023rds/bcsr.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * - * Authors: Chunhe Lan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __BCSR_H_ -#define __BCSR_H_ - -#include - -/* - * BCSR Bit definitions - * BCSR 15 * - 0 device insertion oriention - 1 stack processor present - 2 power supply shut down/normal operation - 3 I2C bus0 drive enable - 4 reserved - 5:7 I2C bus0 select - 5 - I2C_BUS_0_SS0 - 6 - I2C_BUS_0_SS1 - 7 - I2C_BUS_0_SS2 -*/ - -/* BCSR register base address is 0xFX000020 */ -#define BCSR_BASE_REG_OFFSET 0x20 -#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET) - -#define BCSR15_DEV_INS_ORI 0x80 -#define BCSR15_STACK_PRO_PRE 0x40 -#define BCSR15_POWER_SUPPLY 0x20 -#define BCSR15_I2C_BUS0_EN 0x10 -#define BCSR15_I2C_BUS0_SEG0 0x00 -#define BCSR15_I2C_BUS0_SEG1 0x04 -#define BCSR15_I2C_BUS0_SEG2 0x02 -#define BCSR15_I2C_BUS0_SEG3 0x06 -#define BCSR15_I2C_BUS0_SEG4 0x01 -#define BCSR15_I2C_BUS0_SEG5 0x05 -#define BCSR15_I2C_BUS0_SEG6 0x03 -#define BCSR15_I2C_BUS0_SEG7 0x07 -#define BCSR15_I2C_BUS0_SEG_CLR 0x07 -#define BCSR19_SGMII_SEL_L 0x01 - -/*BCSR Utils functions*/ -void fixup_i2c_bus0_sel_seg0(void); -#endif /* __BCSR_H_ */ diff --git a/board/freescale/p1023rds/law.c b/board/freescale/p1023rds/law.c deleted file mode 100644 index 92f5a3fcb5..0000000000 --- a/board/freescale/p1023rds/law.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M, - LAW_TRGT_IF_DPAA_SWP_SRAM), - /* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */ - SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c deleted file mode 100644 index 7c54b65c1d..0000000000 --- a/board/freescale/p1023rds/p1023rds.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * - * Authors: Roy Zang - * Chunhe Lan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "bcsr.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - fsl_lbc_t *lbc = LBC_BASE_ADDR; - - /* Set ABSWP to implement conversion of addresses in the LBC */ - setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - - return 0; -} - -int checkboard(void) -{ - u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; - - printf("Board: P1023 RDS\n"); - - clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR); - setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0); - - return 0; -} - -/* Fixed sdram init -- doesn't use serial presence detect. */ -phys_size_t fixed_sdram(void) -{ -#ifndef CONFIG_SYS_RAMBOOT - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); - - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); - out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); - out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_BCSR_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + BCSR region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash + bcsr */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - setup_portals(); - - return 0; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - return gd->bus_clk; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - return gd->mem_clk; -} - -int board_eth_init(bd_t *bis) -{ - u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; - ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_pq_mdio_info dtsec_mdio_info; - - /* - * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting - * is not correct. - */ - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - - fm_info_set_mdio(FM1_DTSEC1, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - fm_info_set_mdio(FM1_DTSEC2, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - - /* Make SERDES connected to SGMII by cleaing bcsr19[7] */ - if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) - clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L); - -#ifdef CONFIG_FMAN_ENET - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - /* By default NOR is on, and NAND is disabled */ -#ifdef CONFIG_NAND_U_BOOT - do_fixup_by_path_string(blob, "nor_flash", "status", "disabled"); - do_fixup_by_path_string(blob, "nand_flash", "status", "okay"); -#endif -#ifdef CONFIG_HAS_FSL_DR_USB - fdt_fixup_dr_usb(blob, bd); -#endif - - fdt_fixup_fman_ethernet(blob); -} -#endif diff --git a/board/freescale/p1023rds/tlb.c b/board/freescale/p1023rds/tlb.c deleted file mode 100644 index 8b2bf50799..0000000000 --- a/board/freescale/p1023rds/tlb.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_4M, 1), - -#ifndef CONFIG_NAND_SPL - /* *W*G* - BCSR and NOR flash on local bus*/ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_1M, 1), -#endif - - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_1M, 1), - -#ifdef CONFIG_SYS_RAMBOOT - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, - CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 12, BOOKE_PAGESZ_1G, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 13, BOOKE_PAGESZ_1G, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile deleted file mode 100644 index 36df225cf2..0000000000 --- a/board/freescale/p1_p2_rdb/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright 2009 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README deleted file mode 100644 index cb664a5bd7..0000000000 --- a/board/freescale/p1_p2_rdb/README +++ /dev/null @@ -1,145 +0,0 @@ -Overview --------- -P2020RDB is a Low End Dual core platform supporting the P2020 processor -of QorIQ series. P2020 is an e500 based dual core SOC. - -Building U-boot ------------ -To build the u-boot for P2020RDB: - make P2020RDB_config - make - -NOR Flash Banks ------------ -RDB board for P2020 has two flash banks. They are both present on boot. - -Booting by default is always from the boot bank at 0xef00_0000. - -Memory Map ----------- -0xef00_0000 - 0xef7f_ffff Alternate bank 8MB -0xe800_0000 - 0xefff_ffff Boot bank 8MB - -0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB -0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB - -Switch settings to boot from the NOR flash banks ------------------------------------------------- -SW4[8]=0 default NOR Flash bank -SW4[8]=1 Alternate NOR Flash bank - -Flashing Images ---------------- -To place a new u-boot image in the alternate flash bank and then boot -with that new image temporarily, use this: - tftp 1000000 u-boot.bin - erase ef780000 ef7fffff - cp.b 1000000 ef780000 80000 - -Now to boot from the alternate bank change the SW4[8] from 0 to 1. - -To program the image in the boot flash bank: - tftp 1000000 u-boot.bin - protect off all - erase eff80000 ffffffff - cp.b 1000000 eff80000 80000 - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts - -Booting Linux -------------- -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage.p2020rdb - tftp 2000000 rootfs.ext2.gz.uboot - tftp c00000 p2020rdb.dtb - bootm 1000000 2000000 c00000 - -Implementing AMP(Asymmetric MultiProcessing) ---------------------------------------------- -1. Build kernel image for core0: - - a. $ make 85xx/p1_p2_rdb_defconfig - - b. $ make menuconfig - - un-select "Processor support"-> - "Symetric multi-processing support" - - c. $ make uImage - - d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 - -2. Build kernel image for core1: - - a. $ make 85xx/p1_p2_rdb_defconfig - - b. $ make menuconfig - - Un-select "Processor support"-> - "Symetric multi-processing support" - - Select "Advanced setup" -> - "Prompt for advanced kernel configuration options" - - Select - "Set physical address where the kernel is loaded" - and set it to 0x20000000, assuming core1 will - start from 512MB. - - Select "Set custom page offset address" - - Select "Set custom kernel base address" - - Select "Set maximum low memory" - - "Exit" and save the selection. - - c. $ make uImage - - d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 - -3. Create dtb for core0: - - $ dtc -I dts -O dtb -f -b 0 - arch/powerpc/boot/dts/p2020rdb_camp_core0.dts > - /tftpboot/p2020rdb_camp_core0.dtb - -4. Create dtb for core1: - - $ dtc -I dts -O dtb -f -b 1 - arch/powerpc/boot/dts/p2020rdb_camp_core1.dts > - /tftpboot/p2020rdb_camp_core1.dtb - -5. Bring up two cores separately: - - a. Power on the board, under u-boot prompt: - => setenv - => setenv - => setenv bootargs root=/dev/ram rw console=ttyS0,115200 - b. Bring up core1's kernel first: - => setenv bootm_low 0x20000000 - => setenv bootm_size 0x10000000 - => tftp 21000000 uImage.core1 - => tftp 22000000 ramdiskfile - => tftp 20c00000 p2020rdb_camp_core1.dtb - => interrupts off - => bootm start 21000000 22000000 20c00000 - => bootm loados - => bootm ramdisk - => bootm fdt - => fdt boardsetup - => fdt chosen $initrd_start $initrd_end - => bootm prep - => cpu 1 release $bootm_low - $fdtaddr - - c. Bring up core0's kernel(on the same u-boot console): - => setenv bootm_low 0 - => setenv bootm_size 0x20000000 - => tftp 1000000 uImage.core0 - => tftp 2000000 ramdiskfile - => tftp c00000 p2020rdb_camp_core0.dtb - => bootm 1000000 2000000 c00000 - -Please note only core0 will run u-boot, core1 starts kernel directly -after "cpu release" command is issued. diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c deleted file mode 100644 index 0038077fcc..0000000000 --- a/board/freescale/p1_p2_rdb/ddr.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2009, 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000000 -#define CONFIG_SYS_DDR_TIMING_5 0x00000000 - -#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322 -#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca -#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_400 0x00480432 -#define CONFIG_SYS_DDR_MODE_2_400 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100 - -#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432 -#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce -#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_533 0x00040642 -#define CONFIG_SYS_DDR_MODE_2_533 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100 - -#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000 -#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 -#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 -#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_667 0x00040852 -#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00040852 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 - -fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram (void) -{ - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - size_t ddr_size; - struct cpu_type *cpu; - ulong ddr_freq, ddr_freq_mhz; - - cpu = gd->arch.cpu; - /* P1020 and it's derivatives support max 32bit DDR width */ - if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { - ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); - } else { - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - } -#if defined(CONFIG_SYS_RAMBOOT) - return ddr_size; -#endif - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - if(ddr_freq_mhz <= 400) - memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs)); - else if(ddr_freq_mhz <= 533) - memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs)); - else if(ddr_freq_mhz <= 667) - memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs)); - else if(ddr_freq_mhz <= 800) - memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); - else - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - /* P1020 and it's derivatives support max 32bit DDR width */ - if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { - ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; - ddr_cfg_regs.cs[0].bnds = 0x0000001F; - } - - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); - - set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); - return ddr_size; -} diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c deleted file mode 100644 index b60a27fd92..0000000000 --- a/board/freescale/p1_p2_rdb/law.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c deleted file mode 100644 index 3df557d6a3..0000000000 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define VSC7385_RST_SET 0x00080000 -#define SLIC_RST_SET 0x00040000 -#define SGMII_PHY_RST_SET 0x00020000 -#define PCIE_RST_SET 0x00010000 -#define RGMII_PHY_RST_SET 0x02000000 - -#define USB_RST_CLR 0x04000000 -#define USB2_PORT_OUT_EN 0x01000000 - -#define GPIO_DIR 0x060f0000 - -#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \ - SGMII_PHY_RST_SET | PCIE_RST_SET | \ - RGMII_PHY_RST_SET - -#define SYSCLK_MASK 0x00200000 -#define BOARDREV_MASK 0x10100000 -#define BOARDREV_C 0x00100000 -#define BOARDREV_D 0x00000000 - -#define SYSCLK_66 66666666 -#define SYSCLK_100 100000000 - -unsigned long get_board_sys_clk(ulong dummy) -{ - volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - u32 val_gpdat, sysclk_gpio; - - val_gpdat = in_be32(&pgpio->gpdat); - sysclk_gpio = val_gpdat & SYSCLK_MASK; - - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - - return 0; -} - -#ifdef CONFIG_MMC -int board_early_init_f (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | - MPC85xx_PMUXCR_SDHC_WP)); - return 0; -} -#endif - -int checkboard (void) -{ - u32 val_gpdat, board_rev_gpio; - volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - char board_rev = 0; - struct cpu_type *cpu; - - val_gpdat = in_be32(&pgpio->gpdat); - board_rev_gpio = val_gpdat & BOARDREV_MASK; - if (board_rev_gpio == BOARDREV_C) - board_rev = 'C'; - else if (board_rev_gpio == BOARDREV_D) - board_rev = 'D'; - else - panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio); - - cpu = gd->arch.cpu; - printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); - - setbits_be32(&pgpio->gpdir, GPIO_DIR); - -/* - * Bringing the following peripherals out of reset via GPIOs - * 0 = reset and 1 = out of reset - * GPIO12 - Reset to Ethernet Switch - * GPIO13 - Reset to SLIC/SLAC devices - * GPIO14 - Reset to SGMII_PHY_N - * GPIO15 - Reset to PCIe slots - * GPIO6 - Reset to RGMII PHY - * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset - */ - clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET); - - return 0; -} - -int misc_init_r(void) -{ -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR; - - setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN); - setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON); -#endif - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - unsigned int orig_bus = i2c_get_bus_num(); - u8 i2c_data; - - i2c_set_bus_num(1); - if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, - 1, &i2c_data, sizeof(i2c_data)) == 0) { - if (i2c_data & 0x2) - puts("NOR Flash Bank : Secondary\n"); - else - puts("NOR Flash Bank : Primary\n"); - - if (i2c_data & 0x1) { - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); - puts("SD/MMC : 8-bit Mode\n"); - puts("eSPI : Disabled\n"); - } else { - puts("SD/MMC : 4-bit Mode\n"); - puts("eSPI : Enabled\n"); - } - } else { - puts("Failed reading I2C Chip 0x18 on bus 1\n"); - } - i2c_set_bus_num(orig_bus); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_16M, 1); - rtc_reset(); - return 0; -} - - -#ifdef CONFIG_TSEC_ENET -int board_eth_init(bd_t *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - char *tmp; - unsigned int vscfw_addr; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } -#ifdef CONFIG_VSC7385_ENET -/* If a VSC7385 microcode image is present, then upload it. */ - if ((tmp = getenv ("vscfw_addr")) != NULL) { - vscfw_addr = simple_strtoul (tmp, NULL, 16); - printf("uploading VSC7385 microcode from %x\n", vscfw_addr); - if (vsc7385_upload_firmware((void *) vscfw_addr, - CONFIG_VSC7385_IMAGE_SIZE)) - puts("Failure uploading VSC7385 microcode.\n"); - } else - puts("No address specified for VSC7385 microcode.\n"); -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -extern void ft_pci_board_setup(void *blob); - -void ft_board_setup(void *blob, bd_t *bd) -{ - const char *soc_usb_compat = "fsl-usb2-dr"; - int err, usb1_off, usb2_off; - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - -#if defined(CONFIG_PCI) - ft_pci_board_setup(blob); -#endif /* #if defined(CONFIG_PCI) */ - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) - fdt_fixup_dr_usb(blob, bd); -#endif - -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) - /* Delete eLBC node as it is muxed with USB2 controller */ - if (hwconfig("usb2")) { - const char *soc_elbc_compat = "fsl,p1020-elbc"; - int off = fdt_node_offset_by_compatible(blob, -1, - soc_elbc_compat); - if (off < 0) { - printf("WARNING: could not find compatible node" - " %s: %s.\n", soc_elbc_compat, - fdt_strerror(off)); - return; - } - err = fdt_del_node(blob, off); - if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - soc_elbc_compat, fdt_strerror(err)); - } - return; - } -#endif - /* Delete USB2 node as it is muxed with eLBC */ - usb1_off = fdt_node_offset_by_compatible(blob, -1, - soc_usb_compat); - if (usb1_off < 0) { - printf("WARNING: could not find compatible node" - " %s: %s.\n", soc_usb_compat, - fdt_strerror(usb1_off)); - return; - } - usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, - soc_usb_compat); - if (usb2_off < 0) { - printf("WARNING: could not find compatible node" - " %s: %s.\n", soc_usb_compat, - fdt_strerror(usb2_off)); - return; - } - err = fdt_del_node(blob, usb2_off); - if (err < 0) - printf("WARNING: could not remove %s: %s.\n", - soc_usb_compat, fdt_strerror(err)); -} -#endif diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c deleted file mode 100644 index 76ef28b8c8..0000000000 --- a/board/freescale/p1_p2_rdb/pci.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void ft_pci_board_setup(void *blob) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c deleted file mode 100644 index bc98972e33..0000000000 --- a/board/freescale/p1_p2_rdb/tlb.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_16M, 1), - -#if defined(CONFIG_PCI) - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), - -#endif /* #if defined(CONFIG_PCI) */ - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), - - /* *I*G - VSC7385 Switch */ - SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_1M, 1), - -#if defined(CONFIG_SYS_RAMBOOT) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_1G, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig new file mode 100644 index 0000000000..d3352d2856 --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P1_P2_RDB_PC + +config SYS_BOARD + default "p1_p2_rdb_pc" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "p1_p2_rdb_pc" + +endif diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS new file mode 100644 index 0000000000..c2e924798e --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS @@ -0,0 +1,51 @@ +P1_P2_RDB_PC BOARD +#M: - +S: Maintained +F: board/freescale/p1_p2_rdb_pc/ +F: include/configs/p1_p2_rdb_pc.h +F: configs/P1020MBG-PC_defconfig +F: configs/P1020MBG-PC_36BIT_defconfig +F: configs/P1020MBG-PC_36BIT_SDCARD_defconfig +F: configs/P1020MBG-PC_SDCARD_defconfig +F: configs/P1020RDB-PC_defconfig +F: configs/P1020RDB-PC_36BIT_defconfig +F: configs/P1020RDB-PC_36BIT_NAND_defconfig +F: configs/P1020RDB-PC_36BIT_SDCARD_defconfig +F: configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +F: configs/P1020RDB-PC_NAND_defconfig +F: configs/P1020RDB-PC_SDCARD_defconfig +F: configs/P1020RDB-PC_SPIFLASH_defconfig +F: configs/P1020RDB-PD_defconfig +F: configs/P1020RDB-PD_NAND_defconfig +F: configs/P1020RDB-PD_SDCARD_defconfig +F: configs/P1020RDB-PD_SPIFLASH_defconfig +F: configs/P1020UTM-PC_defconfig +F: configs/P1020UTM-PC_36BIT_defconfig +F: configs/P1020UTM-PC_36BIT_SDCARD_defconfig +F: configs/P1020UTM-PC_SDCARD_defconfig +F: configs/P1021RDB-PC_defconfig +F: configs/P1021RDB-PC_36BIT_defconfig +F: configs/P1021RDB-PC_36BIT_NAND_defconfig +F: configs/P1021RDB-PC_36BIT_SDCARD_defconfig +F: configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +F: configs/P1021RDB-PC_NAND_defconfig +F: configs/P1021RDB-PC_SDCARD_defconfig +F: configs/P1021RDB-PC_SPIFLASH_defconfig +F: configs/P1024RDB_defconfig +F: configs/P1024RDB_36BIT_defconfig +F: configs/P1024RDB_NAND_defconfig +F: configs/P1024RDB_SDCARD_defconfig +F: configs/P1024RDB_SPIFLASH_defconfig +F: configs/P1025RDB_defconfig +F: configs/P1025RDB_36BIT_defconfig +F: configs/P1025RDB_NAND_defconfig +F: configs/P1025RDB_SDCARD_defconfig +F: configs/P1025RDB_SPIFLASH_defconfig +F: configs/P2020RDB-PC_defconfig +F: configs/P2020RDB-PC_36BIT_defconfig +F: configs/P2020RDB-PC_36BIT_NAND_defconfig +F: configs/P2020RDB-PC_36BIT_SDCARD_defconfig +F: configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +F: configs/P2020RDB-PC_NAND_defconfig +F: configs/P2020RDB-PC_SDCARD_defconfig +F: configs/P2020RDB-PC_SPIFLASH_defconfig diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index f8d0b35aba..a2a1f92ce8 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -4,10 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - MINIMAL= ifdef CONFIG_SPL_BUILD @@ -18,29 +14,16 @@ endif ifdef MINIMAL -COBJS-y += spl_minimal.o tlb.o law.o +obj-y += spl_minimal.o tlb.o law.o else - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - +ifdef CONFIG_SPL_BUILD +obj-y += spl.o endif -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +obj-y += p1_p2_rdb_pc.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +endif diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index 44377317dd..f4cc43fbfa 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -3,6 +3,7 @@ Overview P1_P2_RDB_PC represents a set of boards including P1020MSBG-PC P1020RDB-PC + P1020RDB-PD P1020UTM-PC P1021RDB-PC P1024RDB diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 9355536b35..946d5032e7 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include #include @@ -34,20 +34,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1870, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; #elif defined(CONFIG_P2020RDB) /* Micron MT41J128M16_15E */ @@ -65,22 +65,22 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1500, - .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */ - .tAA_ps = 13500, - .tWR_ps = 15000, - .tRCD_ps = 13500, - .tRRD_ps = 6000, - .tRP_ps = 13500, - .tRAS_ps = 36000, - .tRC_ps = 49500, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1500, + .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ + .taa_ps = 13500, + .twr_ps = 15000, + .trcd_ps = 13500, + .trrd_ps = 6000, + .trp_ps = 13500, + .tras_ps = 36000, + .trc_ps = 49500, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 30000, + .tfaw_ps = 30000, }; -#elif defined(CONFIG_P1020MBG) +#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) /* Micron MT41J512M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 2, @@ -96,22 +96,22 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1870, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; -#elif defined(CONFIG_P1020RDB) +#elif defined(CONFIG_P1020RDB_PC) /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" @@ -133,20 +133,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1875, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1875, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; #elif defined(CONFIG_P1024RDB) || \ defined(CONFIG_P1025RDB) @@ -171,20 +171,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1500, - .caslat_X = 0x3e << 4, /* 5,6,7,8,9 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 6000, - .tRP_ps = 13125, - .tRAS_ps = 36000, - .tRC_ps = 49125, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1500, + .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 6000, + .trp_ps = 13125, + .tras_ps = 36000, + .trc_ps = 49125, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 30000, + .tfaw_ps = 30000, }; #else #error Missing raw timing data for this board @@ -247,11 +247,11 @@ phys_size_t fixed_sdram(void) get_sys_info(&sysinfo); printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, sysinfo.freq_ddrbus)); ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 50553dacd9..3f47cfbb82 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -288,7 +288,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -299,8 +299,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ @@ -354,7 +360,7 @@ int board_eth_init(bd_t *bis) puts("No address specified for VSC7385 microcode.\n"); #endif - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); @@ -418,7 +424,7 @@ static void fdt_board_fixup_qe_pins(void *blob) #endif #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -453,17 +459,17 @@ void ft_board_setup(void *blob, bd_t *bd) int off = fdt_node_offset_by_compatible(blob, -1, soc_elbc_compat); if (off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_elbc_compat, - fdt_strerror(off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_elbc_compat); + return off; } err = fdt_del_node(blob, off); if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - soc_elbc_compat, fdt_strerror(err)); + printf("WARNING: could not remove %s\n", + soc_elbc_compat); + return err; } - return; + return 0; } #endif @@ -471,24 +477,23 @@ void ft_board_setup(void *blob, bd_t *bd) usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); if (usb1_off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_usb_compat, - fdt_strerror(usb1_off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_usb_compat); + return usb1_off; } usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat); if (usb2_off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_usb_compat, - fdt_strerror(usb2_off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_usb_compat); + return usb2_off; } err = fdt_del_node(blob, usb2_off); if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - soc_usb_compat, fdt_strerror(err)); + printf("WARNING: could not remove %s\n", soc_usb_compat); + return err; } + return 0; } #endif diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c new file mode 100644 index 0000000000..8d0d850480 --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -0,0 +1,122 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + +#ifdef CONFIG_SPL_SPI_BOOT + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = bus_clk; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + +#ifdef CONFIG_SYS_I2C + i2c_init_all(); +#else + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("Tertiary program loader running in sram..."); +#else + puts("Second program loader running in sram...\n"); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index ac07572c89..92437bc787 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -10,64 +10,19 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_INIT_L2_ADDR -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -static void sdram_init(void) -{ - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); -#endif - __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - - __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); - - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); - - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - - set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); -} -#endif - void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; -#ifndef CONFIG_QE - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); -#elif defined(CONFIG_P1021RDB) - par_io_t *par_io = (par_io_t *)&(gur->qe_par_io); + +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); #endif /* initialize selected port with appropriate baud rate */ @@ -80,35 +35,6 @@ void board_init_f(ulong bootflag) puts("\nNAND boot... "); -#ifndef CONFIG_QE - /* init DDR3 reset signal */ - __raw_writel(0x02000000, &pgpio->gpdir); - __raw_writel(0x00200000, &pgpio->gpodr); - __raw_writel(0x00000000, &pgpio->gpdat); - udelay(1000); - __raw_writel(0x00200000, &pgpio->gpdat); - udelay(1000); - __raw_writel(0x00000000, &pgpio->gpdir); -#elif defined(CONFIG_P1021RDB) - /* init DDR3 reset signal CE_PB8 */ - out_be32(&par_io[1].cpdir1, 0x00004000); - out_be32(&par_io[1].cpodr, 0x00800000); - out_be32(&par_io[1].cppar1, 0x00000000); - /* reset DDR3 */ - out_be32(&par_io[1].cpdat, 0x00800000); - udelay(1000); - out_be32(&par_io[1].cpdat, 0x00000000); - udelay(1000); - out_be32(&par_io[1].cpdat, 0x00800000); - /* disable the CE_PB8 */ - out_be32(&par_io[1].cpdir1, 0x00000000); -#endif - -#ifndef CONFIG_SYS_INIT_L2_ADDR - /* Initialize the DDR3 */ - sdram_init(); -#endif - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -118,6 +44,7 @@ void board_init_f(ulong bootflag) void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); } diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 93896dc719..1c0008b2e6 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -78,31 +78,34 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) -#ifdef CONFIG_SYS_INIT_L2_ADDR - /* L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_256K, 1), -#else +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) /* *I*G - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), -#ifdef CONFIG_P1020MBG +#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD) /* 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), #endif /* P1020MBG */ -#endif /* not L2 SRAM */ #endif /* RAMBOOT/SPL */ + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#if CONFIG_SYS_L2_SIZE >= (256 << 10) + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1) +#endif +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_twr/Kconfig b/board/freescale/p1_twr/Kconfig new file mode 100644 index 0000000000..8f9a8d4415 --- /dev/null +++ b/board/freescale/p1_twr/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P1_TWR + +config SYS_BOARD + default "p1_twr" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "p1_twr" + +endif diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS new file mode 100644 index 0000000000..c19d43616b --- /dev/null +++ b/board/freescale/p1_twr/MAINTAINERS @@ -0,0 +1,6 @@ +P1_TWR BOARD +#M: - +S: Maintained +F: board/freescale/p1_twr/ +F: include/configs/p1_twr.h +F: configs/TWR-P1025_defconfig diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile new file mode 100644 index 0000000000..70afac4088 --- /dev/null +++ b/board/freescale/p1_twr/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += p1_twr.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c new file mode 100644 index 0000000000..a2ce75a40d --- /dev/null +++ b/board/freescale/p1_twr/ddr.c @@ -0,0 +1,69 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Fixed sdram init -- doesn't use serial presence detect. */ +phys_size_t fixed_sdram(void) +{ + sys_info_t sysinfo; + char buf[32]; + size_t ddr_size; + fsl_ddr_cfg_regs_t ddr_cfg_regs = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, +#endif + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, + .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 + }; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freq_ddrbus)); + + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + + return ddr_size; +} diff --git a/board/freescale/p1_twr/law.c b/board/freescale/p1_twr/law.c new file mode 100644 index 0000000000..e79d8a4c13 --- /dev/null +++ b/board/freescale/p1_twr/law.c @@ -0,0 +1,16 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c new file mode 100644 index 0000000000..a40bea328b --- /dev/null +++ b/board/freescale/p1_twr/p1_twr.c @@ -0,0 +1,289 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCLK_64 64000000 +#define SYSCLK_66 66666666 + +unsigned long get_board_sys_clk(ulong dummy) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); + unsigned int cpdat_val = 0; + + /* Set-up up pin muxing based on board switch settings */ + cpdat_val = par_io[1].cpdat; + + /* Check switch setting for SYSCLK select (PB3) */ + if (cpdat_val & 0x10000000) + return SYSCLK_64; + else + return SYSCLK_66; + + return 0; +} + +#ifdef CONFIG_QE + +#define PCA_IOPORT_I2C_ADDR 0x23 +#define PCA_IOPORT_OUTPUT_CMD 0x2 +#define PCA_IOPORT_CFG_CMD 0x6 + +const qe_iop_conf_t qe_iop_conf_tab[] = { + +#ifdef CONFIG_TWR_P1025 + /* GPIO */ + {1, 0, 1, 0, 0}, + {1, 18, 1, 0, 0}, + + /* GPIO for switch options */ + {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */ + {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */ + {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */ + {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */ + + /* QE_MUX_MDC */ + {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ + + /* QE_MUX_MDIO */ + {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ + + /* UCC_1_MII */ + {0, 23, 2, 0, 2}, /* CLK12 */ + {0, 24, 2, 0, 1}, /* CLK9 */ + {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ + {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ + {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ + {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ + {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ + {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ + {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ + {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ + {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ + {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ + {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ + {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ + {0, 17, 2, 0, 2}, /* ENET1_CRS */ + {0, 16, 2, 0, 2}, /* ENET1_COL */ + + /* UCC_5_RMII */ + {1, 11, 2, 0, 1}, /* CLK13 */ + {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ + {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ + {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ + {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ + {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ + {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ + {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ + + /* TDMA - clock option is configured in OS based on board setting */ + {1, 23, 2, 0, 2}, /* TDMA_TXD */ + {1, 25, 2, 0, 2}, /* TDMA_RXD */ + {1, 26, 1, 0, 2}, /* TDMA_SYNC */ +#endif + + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ +}; +#endif + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); + + /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + + return 0; +} + +int checkboard(void) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u8 boot_status; + + printf("Board: %s\n", CONFIG_BOARDNAME); + + boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; + puts("rom_loc: "); + if (boot_status == PORBMSR_ROMLOC_NOR) + puts("nor flash"); + else if (boot_status == PORBMSR_ROMLOC_SDHC) + puts("sd"); + else + puts("unknown"); + puts("\n"); + + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + ccsr_gur_t *gur __attribute__((unused)) = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + printf("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + +#if defined(CONFIG_UEC_ETH) + /* QE0 and QE3 need to be exposed for UCC1 + * and UCC5 Eth mode (in PMUXCR register). + * Currently QE/LBC muxed pins assumed to be + * LBC for U-Boot and PMUXCR updated by OS if required */ + + uec_standard_init(bis); +#endif + + return pci_eth_init(bis); +} + +#if defined(CONFIG_QE) +static void fdt_board_fixup_qe_pins(void *blob) +{ + int node; + + if (!hwconfig("qe")) { + /* For QE and eLBC pins multiplexing, + * When don't use QE function, remove + * qe node from dt blob. + */ + node = fdt_path_offset(blob, "/qe"); + if (node >= 0) + fdt_del_node(blob, node); + } else { + /* For TWR Peripheral Modules - TWR-SER2 + * board only can support Signal Port MII, + * so delete one UEC node when use MII port. + */ + if (hwconfig("mii")) + node = fdt_path_offset(blob, "/qe/ucc@2400"); + else + node = fdt_path_offset(blob, "/qe/ucc@2000"); + if (node >= 0) + fdt_del_node(blob, node); + } + + return; +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + FT_FSL_PCI_SETUP; + +#ifdef CONFIG_QE + do_fixup_by_compat(blob, "fsl,qe", "status", "okay", + sizeof("okay"), 0); +#endif +#if defined(CONFIG_TWR_P1025) + fdt_board_fixup_qe_pins(blob); +#endif + fdt_fixup_dr_usb(blob, bd); + + return 0; +} +#endif diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c new file mode 100644 index 0000000000..308335c974 --- /dev/null +++ b/board/freescale/p1_twr/tlb.c @@ -0,0 +1,76 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_SPL_BUILD + /* W**G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_64M, 1), + + /* W**G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_PCI + /* *I*G* - PCI memory 1.5G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O effective: 192K */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), +#endif + +#endif + +#ifdef CONFIG_SYS_RAMBOOT + /* *I*G - eSDHC boot */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile deleted file mode 100644 index 2e6b6f6c95..0000000000 --- a/board/freescale/p2020come/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2009 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c deleted file mode 100644 index da804771fb..0000000000 --- a/board/freescale/p2020come/ddr.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2009, 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include - -#include -#include - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - if (ctrl_num) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - - if (!pdimm->n_ranks) - return; - - /* - * Set DDR_SDRAM_CLK_CNTL = 0x02800000 - * - * Clock is launched 5/8 applied cycle after address/command - */ - popts->clk_adjust = 5; -} diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c deleted file mode 100644 index 7048a0823e..0000000000 --- a/board/freescale/p2020come/law.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Create a dummy LAW entry for the DDR SDRAM which will be replaced when - * the DDR SPD setup code runs. - * - * This table would be empty, except that it is used before the BSS section is - * initialized, and therefore must have at least one entry to push it into - * the DATA section. - */ -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c deleted file mode 100644 index f777bb9d67..0000000000 --- a/board/freescale/p2020come/p2020come.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright 2009,2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_PCI) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void ft_pci_board_setup(void *blob) -{ - FT_FSL_PCI_SETUP; -} -#endif - -#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \ - SGMII_PHY_RST_SET | PCIE_RST_SET | \ - RGMII_PHY_RST_SET) - -#define SYSCLK_MASK 0x00200000 -#define BOARDREV_MASK 0x10100000 -#define BOARDREV_B 0x10100000 -#define BOARDREV_C 0x00100000 -#define BOARDREV_D 0x00000000 - -#define SYSCLK_66 66666666 -#define SYSCLK_50 50000000 -#define SYSCLK_100 100000000 - -unsigned long get_board_sys_clk(ulong dummy) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; - - ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; - switch (ddr_ratio) { - case 0x0C: - return SYSCLK_66; - case 0x0A: - case 0x08: - return SYSCLK_100; - default: - puts("ERROR: unknown DDR ratio\n"); - return SYSCLK_100; - } -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; - - ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; - switch (ddr_ratio) { - case 0x0C: - case 0x0A: - return SYSCLK_66; - case 0x08: - return SYSCLK_100; - default: - puts("ERROR: unknown DDR ratio\n"); - return SYSCLK_100; - } -} - -#ifdef CONFIG_MMC -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | - MPC85xx_PMUXCR_SDHC_WP)); - - /* All the device are enable except for SRIO12 */ - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO); - return 0; -} -#endif - -#define GPIO_DIR 0x0f3a0000 -#define GPIO_ODR 0x00000000 -#define GPIO_DAT 0x001a0000 - -int checkboard(void) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00); - - /* - * GPIO - * 0 - 3: CarryBoard Input; - * 4 - 7: CarryBoard Output; - * 8 : Mux as SDHC_CD (card detection) - * 9 : Mux as SDHC_WP - * 10 : Clear Watchdog timer - * 11 : LED Input - * 12 : Output to 1 - * 13 : Open Drain - * 14 : LED Output - * 15 : Switch Input - * - * Set GPIOs 11, 12, 14 to 1. - */ - out_be32(&pgpio->gpodr, GPIO_ODR); - mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT); - - puts("Board: Freescale COM Express P2020\n"); - return 0; -} - -#define M41ST85W_I2C_BUS 1 -#define M41ST85W_I2C_ADDR 0x68 -#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args) - -static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name) -{ - u8 data; - - if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) { - M41ST85W_ERROR("unable to read %s bit\n", name); - return; - } - - if (data & mask) { - data &= ~mask; - if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) { - M41ST85W_ERROR("unable to clear %s bit\n", name); - return; - } - } -} - -#define M41ST85W_REG_SEC2 0x01 -#define M41ST85W_REG_SEC2_ST 0x80 - -#define M41ST85W_REG_ALHOUR 0x0c -#define M41ST85W_REG_ALHOUR_HT 0x40 - -/* - * The P2020COME board has a STMicro M41ST85W RTC/watchdog - * at i2c bus 1 address 0x68. - */ -static void start_rtc(void) -{ - unsigned int bus = i2c_get_bus_num(); - - if (i2c_set_bus_num(M41ST85W_I2C_BUS)) { - M41ST85W_ERROR("unable to set i2c bus\n"); - goto out; - } - - /* ensure ST (stop) and HT (halt update) bits are cleared */ - m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST"); - m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT"); - -out: - /* reset the i2c bus */ - i2c_set_bus_num(bus); -} - -int board_early_init_r(void) -{ - start_rtc(); - return 0; -} - -#define M41ST85W_REG_WATCHDOG 0x09 -#define M41ST85W_REG_WATCHDOG_WDS 0x80 -#define M41ST85W_REG_WATCHDOG_BMB0 0x04 - -void board_reset(void) -{ - u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0; - - /* set the hardware watchdog timeout to 1/16 second, then hang */ - i2c_set_bus_num(M41ST85W_I2C_BUS); - i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1); - - while (1) - /* hang */; -} - -#ifdef CONFIG_TSEC_ENET -int board_eth_init(bd_t *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode."); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - -#if defined(CONFIG_PCI) - ft_pci_board_setup(blob); -#endif - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_HAS_FSL_DR_USB - fdt_fixup_dr_usb(blob, bd); -#endif -} -#endif diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c deleted file mode 100644 index 08a1e3433a..0000000000 --- a/board/freescale/p2020come/tlb.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#if defined(CONFIG_PCI) - /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * *I*G* - PCI I/O - * - * PCI3 => 0xFFC10000 - * PCI2 => 0xFFC2,0000 - * PCI1 => 0xFFC3,0000 - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), -#endif /* #if defined(CONFIG_PCI) */ - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile deleted file mode 100644 index 0967b28420..0000000000 --- a/board/freescale/p2020ds/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c deleted file mode 100644 index 59034f9f89..0000000000 --- a/board/freescale/p2020ds/ddr.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include - -#include -#include - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; - u32 force_2T; -}; - - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - * - * ranges for parameters: - * wr_data_delay = 0-6 - * clk adjust = 0-8 - * cpo 2-0x1E (30) - */ -static const struct board_specific_parameters dimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ -#ifdef CONFIG_FSL_DDR2 - {2, 549, 4, 0x1f, 2, 0}, - {2, 680, 4, 0x1f, 3, 0}, - {2, 850, 4, 0x1f, 4, 0}, - {1, 549, 4, 0x1f, 2, 0}, - {1, 680, 4, 0x1f, 3, 0}, - {1, 850, 4, 0x1f, 4, 0}, -#else - {2, 850, 6, 0x1f, 4, 0}, - {1, 850, 4, 0x1f, 4, 0}, -#endif - {} -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - int i; - - if (ctrl_num) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in - * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If - * there are two dimms in the controller, set odt_rd_cfg to 3 and - * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. - */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 1; - } - - pbsp = dimm0; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->twoT_en = pbsp_highest->force_2T; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - popts->wrlvl_en = 1; - /* Write leveling override */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xa; - popts->wrlvl_start = 0x8; - /* Rtt and Rtt_WR override */ - popts->rtt_override = 1; - popts->rtt_override_value = DDR3_RTT_120_OHM; - popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ -} diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c deleted file mode 100644 index 9cd4da9780..0000000000 --- a/board/freescale/p2020ds/law.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c deleted file mode 100644 index 1334f250eb..0000000000 --- a/board/freescale/p2020ds/p2020ds.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright 2007-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/ngpixis.h" -#include "../common/sgmii_riser.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ -#ifdef CONFIG_MMC - ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | - MPC85xx_PMUXCR_SDHC_WP)); -#endif - - return 0; -} - -int checkboard(void) -{ - u8 sw; - - printf("Board: P2020DS Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); - - sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); - sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - /* The lower two bits are the actual vbank number */ - printf("vBank: %d\n", sw & 3); - else - puts("Promjet\n"); - - return 0; -} - -#if !defined(CONFIG_DDR_SPD) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram(void) -{ - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - uint d_init; - - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; - ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL; - ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL; - ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1; - ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4; - ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5; - - if (!strcmp("performance", getenv("perf_mode"))) { - /* Performance Mode Values */ - - ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF; - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF; - ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF; - - asm("sync;isync"); - - udelay(500); - - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF; - } else { - /* Stable Mode Values */ - - ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - - /* ECC will be assumed in stable mode */ - ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; - ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; - ddr->err_sbe = CONFIG_SYS_DDR_SBE; - - asm("sync;isync"); - - udelay(500); - - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - } - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - d_init = 1; - debug("DDR - 1st controller: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) - udelay(1000); - debug("DDR: memory initialized\n\n"); - asm("sync; isync"); - udelay(500); -#endif - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE * 1024 * 1024, - LAW_TRGT_IF_DDR) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - }; - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} - -#endif - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - return 0; -} - -#ifdef CONFIG_TSEC_ENET -int board_eth_init(bd_t *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; -} - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - - return 0; - } - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_init(tsec_info, num); -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_HAS_FSL_DR_USB - fdt_fixup_dr_usb(blob, bd); -#endif - - FT_FSL_PCI_SETUP; - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_fdt_fixup(blob); -#endif -} -#endif diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c deleted file mode 100644 index 02da6e8c43..0000000000 --- a/board/freescale/p2020ds/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), - - SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4K, 1), - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_256K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig new file mode 100644 index 0000000000..78e11214a5 --- /dev/null +++ b/board/freescale/p2041rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P2041RDB + +config SYS_BOARD + default "p2041rdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P2041RDB" + +endif diff --git a/board/freescale/p2041rdb/MAINTAINERS b/board/freescale/p2041rdb/MAINTAINERS new file mode 100644 index 0000000000..d93cb0bebb --- /dev/null +++ b/board/freescale/p2041rdb/MAINTAINERS @@ -0,0 +1,11 @@ +P2041RDB BOARD +#M: - +S: Maintained +F: board/freescale/p2041rdb/ +F: include/configs/P2041RDB.h +F: configs/P2041RDB_defconfig +F: configs/P2041RDB_NAND_defconfig +F: configs/P2041RDB_SDCARD_defconfig +F: configs/P2041RDB_SECURE_BOOT_defconfig +F: configs/P2041RDB_SPIFLASH_defconfig +F: configs/P2041RDB_SRIO_PCIE_BOOT_defconfig diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile index 147f658b26..c74f4c62f8 100644 --- a/board/freescale/p2041rdb/Makefile +++ b/board/freescale/p2041rdb/Makefile @@ -6,27 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += cpld.o -COBJS-y += ddr.o -COBJS-y += eth.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += p2041rdb.o +obj-y += cpld.o +obj-y += ddr.o +obj-y += eth.o diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 292d0d39cf..9b5539fff3 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -18,8 +18,8 @@ Boot from NOR flash 2. Program image => tftp 1000000 u-boot.bin => protect off all - => erase eff80000 efffffff - => cp.b 1000000 eff80000 80000 + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 3. Program RCW => tftp 1000000 rcw.bin @@ -30,8 +30,8 @@ Boot from NOR flash 4. Program FMAN Firmware ucode => tftp 1000000 ucode.bin => protect off all - => erase ef000000 ef0fffff - => cp.b 1000000 ef000000 2000 + => erase eff00000 eff3ffff + => cp.b 1000000 eff00000 2000 5. Change DIP-switch SW1[1-5] = 10110 @@ -50,11 +50,11 @@ Boot from SDCard 3. Program the PBL image to SDCard => tftp 1000000 pbl_sd.bin => mmcinfo - => mmc write 1000000 8 441 + => mmc write 1000000 8 672 4. Program FMAN Firmware ucode => tftp 1000000 ucode.bin - => mmc write 1000000 46a 10 + => mmc write 1000000 690 10 5. Change DIP-switch SW1[1-5] = 01100 diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index 6d9a5de1c5..b8bbcdf2a8 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include struct board_specific_parameters { @@ -21,7 +21,7 @@ struct board_specific_parameters { u32 wrlvl_start; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -76,7 +76,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -93,7 +93,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 08d10bc9c8..e600bdbc2a 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -28,7 +28,6 @@ int checkboard(void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i; printf("Board: %sRDB, ", cpu->name); @@ -38,20 +37,6 @@ int checkboard(void) sw = CPLD_READ(fbank_sel); printf("vBank: %d\n", sw & 0x1); - /* - * Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* * Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could @@ -131,7 +116,7 @@ void board_config_lanes_mux(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -142,8 +127,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -170,20 +161,6 @@ unsigned long get_board_sys_clk(unsigned long dummy) } } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - default: - return "150"; - } -} - #define NUM_SRDS_BANKS 2 int misc_init_r(void) @@ -238,7 +215,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -262,4 +239,6 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); #endif + + return 0; } diff --git a/board/freescale/qemu-ppce500/Kconfig b/board/freescale/qemu-ppce500/Kconfig new file mode 100644 index 0000000000..236cd17f99 --- /dev/null +++ b/board/freescale/qemu-ppce500/Kconfig @@ -0,0 +1,12 @@ +if TARGET_QEMU_PPCE500 + +config SYS_BOARD + default "qemu-ppce500" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "qemu-ppce500" + +endif diff --git a/board/freescale/qemu-ppce500/MAINTAINERS b/board/freescale/qemu-ppce500/MAINTAINERS new file mode 100644 index 0000000000..77d0a4a13c --- /dev/null +++ b/board/freescale/qemu-ppce500/MAINTAINERS @@ -0,0 +1,6 @@ +QEMU-PPCE500 BOARD +M: Alexander Graf +S: Maintained +F: board/freescale/qemu-ppce500/ +F: include/configs/qemu-ppce500.h +F: configs/qemu-ppce500_defconfig diff --git a/board/freescale/qemu-ppce500/Makefile b/board/freescale/qemu-ppce500/Makefile new file mode 100644 index 0000000000..2d2749205f --- /dev/null +++ b/board/freescale/qemu-ppce500/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += qemu-ppce500.o diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c new file mode 100644 index 0000000000..a0fca0d880 --- /dev/null +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c @@ -0,0 +1,370 @@ +/* + * Copyright 2007,2009-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void *get_fdt_virt(void) +{ + return (void *)CONFIG_SYS_TMPVIRT; +} + +static uint64_t get_fdt_phys(void) +{ + return (uint64_t)(uintptr_t)gd->fdt_blob; +} + +static void map_fdt_as(int esel) +{ + u32 mas0, mas1, mas2, mas3, mas7; + uint64_t fdt_phys = get_fdt_phys(); + unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful; + unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful; + + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0); + mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb); + + write_tlb(mas0, mas1, mas2, mas3, mas7); +} + +uint64_t get_phys_ccsrbar_addr_early(void) +{ + void *fdt = get_fdt_virt(); + uint64_t r; + + /* + * To be able to read the FDT we need to create a temporary TLB + * map for it. + */ + map_fdt_as(10); + r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc")); + disable_tlb(10); + + return r; +} + +int board_early_init_f(void) +{ + return 0; +} + +int checkboard(void) +{ + return 0; +} + +static int pci_map_region(void *fdt, int pci_node, int range_id, + phys_size_t *ppaddr, pci_addr_t *pvaddr, + pci_size_t *psize, ulong *pmap_addr) +{ + uint64_t addr; + uint64_t size; + ulong map_addr; + int r; + + r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size); + if (r) + return r; + + if (ppaddr) + *ppaddr = addr; + if (psize) + *psize = size; + + if (!pmap_addr) + return 0; + + map_addr = *pmap_addr; + + /* Align map_addr */ + map_addr += size - 1; + map_addr &= ~(size - 1); + + if (map_addr + size >= CONFIG_SYS_PCI_MAP_END) + return -1; + + /* Map virtual memory for range */ + assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO)); + *pmap_addr = map_addr + size; + + if (pvaddr) + *pvaddr = map_addr; + + return 0; +} + +void pci_init_board(void) +{ + struct pci_controller *pci_hoses; + void *fdt = get_fdt_virt(); + int pci_node = -1; + int pci_num = 0; + int pci_count = 0; + ulong map_addr; + + puts("\n"); + + /* Start MMIO and PIO range maps above RAM */ + map_addr = CONFIG_SYS_PCI_MAP_START; + + /* Count and allocate PCI buses */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + while (pci_node != -FDT_ERR_NOTFOUND) { + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + pci_count++; + } + + if (pci_count) { + pci_hoses = malloc(sizeof(struct pci_controller) * pci_count); + } else { + printf("PCI: disabled\n\n"); + return; + } + + /* Spawn PCI buses based on device tree */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + while (pci_node != -FDT_ERR_NOTFOUND) { + struct fsl_pci_info pci_info = { }; + const fdt32_t *reg; + int r; + + reg = fdt_getprop(fdt, pci_node, "reg", NULL); + pci_info.regs = fdt_translate_address(fdt, pci_node, reg); + + /* Map MMIO range */ + r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL, + &pci_info.mem_size, &map_addr); + if (r) + break; + + /* Map PIO range */ + r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL, + &pci_info.io_size, &map_addr); + if (r) + break; + + /* + * The PCI framework finds virtual addresses for the buses + * through our address map, so tell it the physical addresses. + */ + pci_info.mem_bus = pci_info.mem_phys; + pci_info.io_bus = pci_info.io_phys; + + /* Instantiate */ + pci_info.pci_num = pci_num + 1; + + fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs); + printf("PCI: base address %lx\n", pci_info.regs); + + fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num); + + /* Jump to next PCI node */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + pci_num++; + } + + puts("\n"); +} + +int last_stage_init(void) +{ + void *fdt = get_fdt_virt(); + int len = 0; + const uint64_t *prop; + int chosen; + + chosen = fdt_path_offset(fdt, "/chosen"); + if (chosen < 0) { + printf("Couldn't find /chosen node in fdt\n"); + return -EIO; + } + + /* -kernel boot */ + prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len); + if (prop && (len >= 8)) + setenv_hex("qemu_kernel_addr", *prop); + + /* Give the user a variable for the host fdt */ + setenv_hex("fdt_addr_r", (ulong)fdt); + + return 0; +} + +static uint64_t get_linear_ram_size(void) +{ + void *fdt = get_fdt_virt(); + const void *prop; + int memory; + int len; + + memory = fdt_path_offset(fdt, "/memory"); + prop = fdt_getprop(fdt, memory, "reg", &len); + + if (prop && len >= 16) + return *(uint64_t *)(prop+8); + + panic("Couldn't determine RAM size"); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; + + return 0; +} +#endif + +void print_laws(void) +{ + /* We don't emulate LAWs yet */ +} + +phys_size_t fixed_sdram(void) +{ + return get_linear_ram_size(); +} + +phys_size_t fsl_ddr_sdram_size(void) +{ + return get_linear_ram_size(); +} + +void init_tlbs(void) +{ + phys_size_t ram_size; + + /* + * Create a temporary AS=1 map for the fdt + * + * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves + * which was only 4k big. This way we don't have to clear any other maps. + */ + map_fdt_as(0); + + /* Fetch RAM size from the fdt */ + ram_size = get_linear_ram_size(); + + /* And remove our fdt map again */ + disable_tlb(0); + + /* Create an internal map of manually created TLB maps */ + init_used_tlb_cams(); + + /* Create a dynamic AS=0 CCSRBAR mapping */ + assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + 1024 * 1024, TLB_MAP_IO)); + + /* Create a RAM map that spans all accessible RAM */ + setup_ddr_tlbs(ram_size >> 20); + + /* Create a map for the TLB */ + assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(), + 1024 * 1024, TLB_MAP_RAM)); +} + +void init_laws(void) +{ + /* We don't emulate LAWs yet */ +} + +static uint32_t get_cpu_freq(void) +{ + void *fdt = get_fdt_virt(); + int cpus_node = fdt_path_offset(fdt, "/cpus"); + int cpu_node = fdt_first_subnode(fdt, cpus_node); + const char *prop = "clock-frequency"; + return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); +} + +void get_sys_info(sys_info_t *sys_info) +{ + int freq = get_cpu_freq(); + + memset(sys_info, 0, sizeof(sys_info_t)); + sys_info->freq_systembus = freq; + sys_info->freq_ddrbus = freq; + sys_info->freq_processor[0] = freq; +} + +int get_clocks (void) +{ + sys_info_t sys_info; + + get_sys_info(&sys_info); + + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + gd->arch.lbc_clk = sys_info.freq_ddrbus; + + return 0; +} + +unsigned long get_tbclk (void) +{ + void *fdt = get_fdt_virt(); + int cpus_node = fdt_path_offset(fdt, "/cpus"); + int cpu_node = fdt_first_subnode(fdt, cpus_node); + const char *prop = "timebase-frequency"; + return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + sys_info_t sys_info; + get_sys_info(&sys_info); + return sys_info.freq_systembus; +} + +/* + * Return the number of cores on this SOC. + */ +int cpu_numcores(void) +{ + /* + * The QEMU u-boot target only needs to drive the first core, + * spinning and device tree nodes get driven by QEMU itself + */ + return 1; +} + +/* + * Return a 32-bit mask indicating which cores are present on this SOC. + */ +u32 cpu_mask(void) +{ + return (1 << cpu_numcores()) - 1; +} diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig new file mode 100644 index 0000000000..4d17798d5c --- /dev/null +++ b/board/freescale/t102xqds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T102XQDS + +config SYS_BOARD + default "t102xqds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T102xQDS" + +endif diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS new file mode 100644 index 0000000000..1ffccc4fd3 --- /dev/null +++ b/board/freescale/t102xqds/MAINTAINERS @@ -0,0 +1,12 @@ +T102XQDS BOARD +M: Shengzhou Liu +S: Maintained +F: board/freescale/t102xqds/ +F: include/configs/T102xQDS.h +F: configs/T1024QDS_defconfig +F: configs/T1024QDS_NAND_defconfig +F: configs/T1024QDS_SDCARD_defconfig +F: configs/T1024QDS_SPIFLASH_defconfig +F: configs/T1024QDS_D4_defconfig +F: configs/T1024QDS_SECURE_BOOT_defconfig +F: configs/T1024QDS_D4_SECURE_BOOT_defconfig diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile new file mode 100644 index 0000000000..d94f2307d9 --- /dev/null +++ b/board/freescale/t102xqds/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += t102xqds.o +obj-y += eth_t102xqds.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README new file mode 100644 index 0000000000..bb0f2805dc --- /dev/null +++ b/board/freescale/t102xqds/README @@ -0,0 +1,328 @@ +T1024 SoC Overview +------------------ +The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor +combines two or one 64-bit Power Architecture e5500 core respectively with high +performance datapath acceleration logic, and network peripheral bus interfaces +required for networking and telecommunications. This processor can be used in +applications such as enterprise WLAN access points, routers, switches, firewall +and other packet processing intensive small enterprise and branch office appliances, +and general-purpose embedded computing. Its high level of integration offers +significant performance benefits and greatly helps to simplify board design. + + +The T1024 SoC includes the following function and features: +- two e5500 cores, each with a private 256 KB L2 cache + - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) + - Three levels of instructions: User, supervisor, and hypervisor + - Independent boot and reset + - Secure boot capability +- 256 KB shared L3 CoreNet platform cache (CPC) +- Interconnect CoreNet platform + - CoreNet coherency manager supporting coherent and noncoherent transactions + with prioritization and bandwidth allocation amongst CoreNet endpoints + - 150 Gbps coherent read bandwidth +- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support +- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion management + - Cryptography Acceleration (SEC 5.x) + - IEEE 1588 support + - Hardware buffer management for buffer allocation and deallocation + - MACSEC on DPAA-based Ethernet ports +- Ethernet interfaces + - Four 1 Gbps Ethernet controllers +- Parallel Ethernet interfaces + - Two RGMII interfaces +- High speed peripheral interfaces + - Three PCI Express 2.0 controllers/ports running at up to 5 GHz + - One SATA controller supporting 1.5 and 3.0 Gb/s operation + - One QSGMII interface + - Four SGMII interface supporting 1000 Mbps + - Three SGMII interfaces supporting up to 2500 Mbps + - 10GbE XFI or 10Base-KR interface +- Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD interface (DIU) with 12 bit dual data rate +- Multicore programmable interrupt controller (PIC) +- Two 8-channel DMA engines +- Single source clocking implementation +- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) +- QUICC Engine block + - 32-bit RISC controller for flexible support of the communications peripherals + - Serial DMA channel for receive and transmit on all serial channels + - Two universal communication controllers, supporting TDM, HDLC, and UART + +T1023 Personality +------------------ +T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and +unavailable deep sleep. Rest of the blocks are almost same as T1024. +Differences between T1024 and T1023 +Feature T1024 T1023 +QUICC Engine: yes no +DIU: yes no +Deep Sleep: yes no +I2C controller: 4 3 +DDR: 64-bit 32-bit +IFC: 32-bit 28-bit + + +T1024QDS board Overview +----------------------- +- SERDES Connections + 4 lanes supporting the following: + - PCI Express: supports Gen 1 and Gen 2 + - SGMII 1G and SGMII 2.5G + - QSGMII + - XFI + - SATA 2.0 + - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors. + - Aurora debug with dedicated connectors. +- DDR Controller + - Supports up to 1600 MTPS data-rate. + - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card. + - Supports Single-, dual- or quad-rank DIMMs + - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT. +- IFC/Local Bus + - NAND Flash: 8-bit, async, up to 2GB + - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB + - NOR devices support 8 virtual banks + - Socketed to allow alternate devices + - GASIC: Simple (minimal) target within QIXIS FPGA + - PromJET rapid memory download support + - IFC Debug/Development card +- Ethernet + - Two on-board RGMII 10M/100M/1G ethernet ports. + - One QSGMII interface + - Four SGMII interface supporting 1Gbps + - Three SGMII interfaces supporting 2.5Gbps + - one 10Gbps XFI or 10Base-KR interface +- QIXIS System Logic FPGA + - Manages system power and reset sequencing. + - Manages the configurations of DUT, board, and clock for dynamic shmoo. + - Collects V-I-T data in background for code/power profiling. + - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion). + - General fault monitoring and logging. + - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off. +- Clocks + - System and DDR clock (SYSCLK, DDRCLK). + - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz. + - Software programmable in 1 MHz increments from 1-200 MHz. + - SERDES clocks + - Provides clocks to SerDes blocks and slots. + - 100 MHz, 125 MHz and 156.25 MHz options. + - Spread-spectrum option for 100 MHz. +- Power Supplies + - Dedicated PMBus regulator for VDD and VDDC. + - Adjustable from 0.7V to 1.3V at 35A + - VDD can be disabled independanty from VDDC for “deep sleep”. + - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A. + - VTT/MVREF automatically track operating voltage. + - Dedicated 2.5V VPP supply. + - Dedicated regulators/filters for AVDD supplies. + - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD. +- Video + - DIU supports video up to 1280x1024x32 bpp. + - Chrontel CH7201 for HDMI connection. + - TI DS90C387R for direct LCD connection. + - Raw (not encoded) video connector for testing or other encoders. +- USB + - Supports two USB 2.0 ports with integrated PHYs. + - Two type A ports with 5V@1.5A per port. + - Second port can be converted to OTG mini-AB. +- SDHC + For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features: + - upport for optional clock feedback paths. + - Support for optional high-speed voltage translation direction controls. + - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC. + - Support for eMMC memory devices. +- SPI + -On-board support of 3 different devices and sizes. +- Other IO + - Two Serial ports + - ProfiBus port + - Four I2C ports + + +Memory map on T1024QDS +---------------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128MB NOR Flash memory Map +-------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +SerDes clock vs DIP-switch settings +----------------------------------- +SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4] +0x6F 100MHz 125MHz 1101 +0xD6 100MHz 100MHz 1111 +0x99 156.25MHz 100MHz 1011 + + +T1024 Clock frequency +---------------------- +BIN Core DDR Platform FMan +Bin1: 1400MHz 1600MT/s 400MHz 700MHz +Bin2: 1200MHz 1600MT/s 400MHz 600MHz +Bin3: 1000MHz 1600MT/s 400MHz 500MHz + + + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T1024QDS_defconfig (For DDR3L, by default) + or make T1024QDS_D4_defconfig (For DDR4) + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot + + Switching between default bank0 and alternate bank4 on NOR flash + To change boot source to vbank4: + via software: run command 'qixis_reset altbank' in u-boot. + via DIP-switch: set SW6[1:4] = '0100' + + To change boot source to vbank0: + via software: run command 'qixis_reset' in u-boot. + via DIP-Switch: set SW6[1:4] = '0000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T1024QDS_NAND_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 $filesize + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T1024QDS_SPIFLASH_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 f0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T1024QDS_SDCARD_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SD/MMC card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin + => mmc write 1000000 0x820 80 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +DIU/QE-TDM/SDXC settings +------------------- +a) For TDM Riser: set pin_mux=tdm in hwconfig +b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig +c) For HDMI(DVI): set pin_mux=hdmi in hwconfig +d) For LCD(DFP): set pin_mux=lcd in hwconfig +e) For SDXC: set adaptor=sdxc in hwconfig + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (30KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T1024QDS +------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x100000 0x15FFFF u-boot env 8KB +0x160000 0x17FFFF FMAN Ucode 128KB +0x180000 0x19FFFF QE Firmware 128KB + + +SD Card memory Map on T1024QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + + +SPI Flash memory Map on T1024QDS +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + + +For more details, please refer to T1024QDS Reference Manual and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c new file mode 100644 index 0000000000..2d4d10f351 --- /dev/null +++ b/board/freescale/t102xqds/ddr.c @@ -0,0 +1,189 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * datarate_mhz_high values need to be in ascending order + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ +#if defined(CONFIG_SYS_FSL_DDR4) + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + struct cpu_type *cpu = gd->arch.cpu; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust according to the board ddr freqency and n_banks + * specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); + debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif + + /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, + * set DDR bus width to 32bit for T1023 + */ + if (cpu->soc_ver == SVR_T1023) + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; + +#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 + /* for DDR bus 32bit test on T1024 */ + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; +#endif +} + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + + return dram_size; +} diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c new file mode 100644 index 0000000000..7723f580db --- /dev/null +++ b/board/freescale/t102xqds/eth_t102xqds.c @@ -0,0 +1,442 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "../common/fman.h" +#include "t102xqds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT4 5 +#define EMI1_SLOT5 6 +#define EMI2 7 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "T1024QDS_MDIO_RGMII1", + "T1024QDS_MDIO_RGMII2", + "T1024QDS_MDIO_SLOT1", + "T1024QDS_MDIO_SLOT2", + "T1024QDS_MDIO_SLOT3", + "T1024QDS_MDIO_SLOT4", + "T1024QDS_MDIO_SLOT5", + "T1024QDS_MDIO_10GC", + "NULL", +}; + +/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +static u8 lane_to_slot[] = {2, 3, 4, 5}; + +static const char *t1024qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name; + + if (muxval > EMI2) + return NULL; + + name = t1024qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct t1024qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void t1024qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t1024qds_mdio *priv = bus->priv; + + t1024qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t1024qds_mdio *priv = bus->priv; + + t1024qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t1024qds_mdio_reset(struct mii_dev *bus) +{ + struct t1024qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t1024qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t1024qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t1024qds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t1024qds private data\n"); + free(bus); + return -1; + } + + bus->read = t1024qds_mdio_read; + bus->write = t1024qds_mdio_write; + bus->reset = t1024qds_mdio_reset; + sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + struct fixed_link f_link; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) { + if (port == FM1_DTSEC3) { + fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2"); + fdt_setprop(fdt, offset, "phy-connection-type", + "rgmii", 5); + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + } + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + if (port == FM1_DTSEC1) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_vsc8234_phy_s5"); + } else if (port == FM1_DTSEC2) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_vsc8234_phy_s4"); + } + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { + if (port == FM1_DTSEC3) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_aqr105_phy_s3"); + } + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2"); + break; + case FM1_DTSEC3: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3"); + break; + case FM1_DTSEC4: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4"); + break; + default: + break; + } + fdt_delprop(fdt, offset, "phy-connection-type"); + fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + /* XFI interface */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ +} + +/* + * This function reads RCW to check if Serdes1{A:D} is configured + * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (srds_s1) { + case 0x46: + case 0x47: + lane_to_slot[1] = 2; + break; + default: + break; + } +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); + + switch (srds_s1) { + case 0xd5: + case 0xd6: + /* QSGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC1, 0x8); + fm_info_set_phy_address(FM1_DTSEC2, 0x9); + fm_info_set_phy_address(FM1_DTSEC3, 0xa); + fm_info_set_phy_address(FM1_DTSEC4, 0xb); + break; + case 0x95: + case 0x99: + /* + * XFI does not need a PHY to work, but to avoid U-boot use + * default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to XFI + * MAC, and should not use a real XAUI PHY address, since + * MDIO can access it successfully, and then MDIO thinks the + * XAUI card is used for the XFI MAC, which will cause error. + */ + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x6f: + /* SGMII in Slot3, Slot4, Slot5 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x7f: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); + break; + case 0x47: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x77: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); + break; + case 0x5a: + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x6a: + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x5b: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x6b: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + break; + default: + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_2500_FM1_DTSEC1 + idx); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + } + + if (lane < 0) + break; + + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 5: + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII2; + else if (i == FM1_DTSEC4) + mdio_mux[i] = EMI1_RGMII1; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + idx = i - FM1_10GEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC1 + idx); + if (lane < 0) + break; + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c new file mode 100644 index 0000000000..b1c9d0187a --- /dev/null +++ b/board/freescale/t102xqds/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef QIXIS_BASE_PHYS + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t102xqds/pci.c b/board/freescale/t102xqds/pci.c new file mode 100644 index 0000000000..7369289618 --- /dev/null +++ b/board/freescale/t102xqds/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c new file mode 100644 index 0000000000..08aef6e159 --- /dev/null +++ b/board/freescale/t102xqds/spl.c @@ -0,0 +1,151 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "t102xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT) + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + u32 porsr1, pinctl; +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg new file mode 100644 index 0000000000..7b9e9b05f7 --- /dev/null +++ b/board/freescale/t102xqds/t1024_pbi.cfg @@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/freescale/t102xqds/t1024_rcw.cfg b/board/freescale/t102xqds/t1024_rcw.cfg new file mode 100644 index 0000000000..4b8f7194dc --- /dev/null +++ b/board/freescale/t102xqds/t1024_rcw.cfg @@ -0,0 +1,10 @@ +# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz +# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz + +# PBL preamble and RCW header for T1024QDS +aa55aa55 010e0100 +# Serdes protocol 0x6F +0810000e 00000000 00000000 00000000 +37800001 00000012 e8104000 21000000 +00000000 00000000 00000000 00030810 +00000000 036c5a00 00000000 00000006 diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c new file mode 100644 index 0000000000..708afcaebf --- /dev/null +++ b/board/freescale/t102xqds/t102xqds.c @@ -0,0 +1,407 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "t102xqds.h" +#include "t102xqds_qixis.h" +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + struct cpu_type *cpu = gd->arch.cpu; + static const char *const freq[] = {"100", "125", "156.25", "100.0"}; + int clock; + u8 sw = QIXIS_READ(arch); + + printf("Board: %sQDS, ", cpu->name); + printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); + printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFC Card\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + puts("SERDES Reference: "); + sw = QIXIS_READ(brdcfg[2]); + clock = (sw >> 6) & 3; + printf("Clock1=%sMHz ", freq[clock]); + clock = (sw >> 4) & 3; + printf("Clock2=%sMHz\n", freq[clock]); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static int board_mux_lane_to_slot(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + u8 brdcfg9; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + + brdcfg9 = QIXIS_READ(brdcfg[9]); + QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE); + + switch (srds_prtcl_s1) { + case 0: + /* SerDes1 is not enabled */ + break; + case 0xd5: + case 0x5b: + case 0x6b: + case 0x77: + case 0x6f: + case 0x7f: + QIXIS_WRITE(brdcfg[12], 0x8c); + break; + case 0x40: + QIXIS_WRITE(brdcfg[12], 0xfc); + break; + case 0xd6: + case 0x5a: + case 0x6a: + case 0x56: + QIXIS_WRITE(brdcfg[12], 0x88); + break; + case 0x47: + QIXIS_WRITE(brdcfg[12], 0xcc); + break; + case 0x46: + QIXIS_WRITE(brdcfg[12], 0xc8); + break; + case 0x95: + case 0x99: + brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE; + QIXIS_WRITE(brdcfg[9], brdcfg9); + QIXIS_WRITE(brdcfg[12], 0x8c); + break; + case 0x116: + QIXIS_WRITE(brdcfg[12], 0x00); + break; + case 0x115: + case 0x119: + case 0x129: + case 0x12b: + /* Aurora, PCIe, SGMII, SATA */ + QIXIS_WRITE(brdcfg[12], 0x04); + break; + default: + printf("WARNING: unsupported for SerDes Protocol %d\n", + srds_prtcl_s1); + return -1; + } + + return 0; +} + +#ifdef CONFIG_PPC_T1024 +static void board_mux_setup(void) +{ + u8 brdcfg15; + + brdcfg15 = QIXIS_READ(brdcfg[15]); + brdcfg15 &= ~BRDCFG15_DIUSEL_MASK; + + if (hwconfig_arg_cmp("pin_mux", "tdm")) { + /* Route QE_TDM multiplexed signals to TDM Riser slot */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM); + QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2); + QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & + ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM); + } else if (hwconfig_arg_cmp("pin_mux", "ucc")) { + /* to UCC (ProfiBus) interface */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC); + } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) { + /* to DVI (HDMI) encoder */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI); + } else if (hwconfig_arg_cmp("pin_mux", "lcd")) { + /* to DFP (LCD) encoder */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM | + BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD); + } + + if (hwconfig_arg_cmp("adaptor", "sdxc")) + /* Route SPI_CS multiplexed signals to SD slot */ + QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & + ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC); +} +#endif + +void board_retimer_ds125df111_init(void) +{ + u8 reg; + + /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); + reg = I2C_MUX_CH5; + i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); + + /* Access to Control/Shared register */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Read device revision and ID */ + i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast */ + reg = 0x0c; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Reset Channel Registers */ + i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); + reg |= 0x4; + i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); + reg |= 0x24; + i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); + + /* Select VCO Divider to full rate (000) */ + i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + reg &= 0x8f; + i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + + /* Select active PFD MUX input as re-timed data (001) */ + i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + reg &= 0x3f; + reg |= 0x20; + i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); + reg = 0xb2; + i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); + reg = 0x90; + i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); + reg = 0xb3; + i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); + reg = 0xcd; + i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +} + +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_SYS_FLASH_BASE + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + board_mux_lane_to_slot(); + board_retimer_ds125df111_init(); + + /* Increase IO drive strength to address FCS error on RGMII */ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +#define NUM_SRDS_PLL 2 +int misc_init_r(void) +{ +#ifdef CONFIG_PPC_T1024 + board_mux_setup(); +#endif + return 0; +} + +void fdt_fixup_spi_mux(void *blob) +{ + int nodeoff = 0; + + if (hwconfig_arg_cmp("pin_mux", "tdm")) { + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "eon,en25s64")) >= 0) { + fdt_del_node(blob, nodeoff); + } + } else { + /* remove tdm node */ + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "maxim,ds26522")) >= 0) { + fdt_del_node(blob, nodeoff); + } + } +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + fdt_fixup_spi_mux(blob); + + return 0; +} + +void qixis_dump_switch(void) +{ + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +} diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h new file mode 100644 index 0000000000..64ff62397d --- /dev/null +++ b/board/freescale/t102xqds/t102xqds.h @@ -0,0 +1,14 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T102x_QDS_H__ +#define __T102x_QDS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); +int select_i2c_ch_pca9547(u8 ch); + +#endif diff --git a/board/freescale/t102xqds/t102xqds_qixis.h b/board/freescale/t102xqds/t102xqds_qixis.h new file mode 100644 index 0000000000..a429fb7216 --- /dev/null +++ b/board/freescale/t102xqds/t102xqds_qixis.h @@ -0,0 +1,64 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T1024QDS_QIXIS_H__ +#define __T1024QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T1024/T1023 QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ +#define BRDCFG5_IMX_MASK 0xC0 +#define BRDCFG5_IMX_DIU 0x80 + +#define BRDCFG5_SPIRTE_MASK 0x07 +#define BRDCFG5_SPIRTE_TDM 0x01 +#define BRDCFG5_SPIRTE_SDHC 0x02 +#define BRDCFG9_XFI_TX_DISABLE 0x10 + +/* BRDCFG13[0:5] TDM configuration and setup */ +#define BRDCFG13_TDM_MASK 0xfc +#define BRDCFG13_TDM_INTERFACE 0x37 +#define BRDCFG13_HDLC_LOOPBACK 0x29 +#define BRDCFG13_TDM_LOOPBACK 0x31 + +/* BRDCFG15[3] controls LCD Panel Powerdown */ +#define BRDCFG15_LCDFM 0x20 +#define BRDCFG15_LCDPD 0x10 +#define BRDCFG15_LCDPD_MASK 0x10 +#define BRDCFG15_LCDPD_ENABLED 0x00 + +/* BRDCFG15[6:7] controls DIU MUX selction*/ +#define BRDCFG15_DIUSEL_MASK 0x03 +#define BRDCFG15_DIUSEL_HDMI 0x00 +#define BRDCFG15_DIUSEL_LCD 0x01 +#define BRDCFG15_DIUSEL_UCC 0x02 +#define BRDCFG15_DIUSEL_TDM 0x03 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e +#endif diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c new file mode 100644 index 0000000000..409e173999 --- /dev/null +++ b/board/freescale/t102xqds/tlb.c @@ -0,0 +1,117 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef QIXIS_BASE + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_4K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif + /* entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so if needed more, will use entry 16 later. + */ +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig new file mode 100644 index 0000000000..10d49f5831 --- /dev/null +++ b/board/freescale/t102xrdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T102XRDB + +config SYS_BOARD + default "t102xrdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T102xRDB" + +endif diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS new file mode 100644 index 0000000000..dc554d4d3a --- /dev/null +++ b/board/freescale/t102xrdb/MAINTAINERS @@ -0,0 +1,10 @@ +T102XRDB BOARD +M: Shengzhou Liu +S: Maintained +F: board/freescale/t102xrdb/ +F: include/configs/T102xRDB.h +F: configs/T1024RDB_defconfig +F: configs/T1024RDB_NAND_defconfig +F: configs/T1024RDB_SDCARD_defconfig +F: configs/T1024RDB_SPIFLASH_defconfig +F: configs/T1024RDB_SECURE_BOOT_defconfig diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile new file mode 100644 index 0000000000..a0cf8f6fbf --- /dev/null +++ b/board/freescale/t102xrdb/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += t102xrdb.o +obj-y += cpld.o +obj-y += eth_t102xrdb.o +obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README new file mode 100644 index 0000000000..2b17f50bae --- /dev/null +++ b/board/freescale/t102xrdb/README @@ -0,0 +1,258 @@ +T1024 SoC Overview +------------------ +The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor +combines two or one 64-bit Power Architecture e5500 core respectively with high +performance datapath acceleration logic, and network peripheral bus interfaces +required for networking and telecommunications. This processor can be used in +applications such as enterprise WLAN access points, routers, switches, firewall +and other packet processing intensive small enterprise and branch office appliances, +and general-purpose embedded computing. Its high level of integration offers +significant performance benefits and greatly helps to simplify board design. + + +The T1024 SoC includes the following function and features: +- two e5500 cores, each with a private 256 KB L2 cache + - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) + - Three levels of instructions: User, supervisor, and hypervisor + - Independent boot and reset + - Secure boot capability +- 256 KB shared L3 CoreNet platform cache (CPC) +- Interconnect CoreNet platform + - CoreNet coherency manager supporting coherent and noncoherent transactions + with prioritization and bandwidth allocation amongst CoreNet endpoints + - 150 Gbps coherent read bandwidth +- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support +- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion management + - Cryptography Acceleration (SEC 5.x) + - IEEE 1588 support + - Hardware buffer management for buffer allocation and deallocation + - MACSEC on DPAA-based Ethernet ports +- Ethernet interfaces + - Four 1 Gbps Ethernet controllers +- Parallel Ethernet interfaces + - Two RGMII interfaces +- High speed peripheral interfaces + - Three PCI Express 2.0 controllers/ports running at up to 5 GHz + - One SATA controller supporting 1.5 and 3.0 Gb/s operation + - One QSGMII interface + - Four SGMII interface supporting 1000 Mbps + - Three SGMII interfaces supporting up to 2500 Mbps + - 10GbE XFI or 10Base-KR interface +- Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD interface (DIU) with 12 bit dual data rate +- Multicore programmable interrupt controller (PIC) +- Two 8-channel DMA engines +- Single source clocking implementation +- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) +- QUICC Engine block + - 32-bit RISC controller for flexible support of the communications peripherals + - Serial DMA channel for receive and transmit on all serial channels + - Two universal communication controllers, supporting TDM, HDLC, and UART + +T1023 Personality +------------------ +T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and +unavailable deep sleep. Rest of the blocks are almost same as T1024. +Differences between T1024 and T1023 +Feature T1024 T1023 +QUICC Engine: yes no +DIU: yes no +Deep Sleep: yes no +I2C controller: 4 3 +DDR: 64-bit 32-bit +IFC: 32-bit 28-bit + + +T1024RDB board Overview +----------------------- + - Ethernet + - Two on-board 10M/100M/1G bps RGMII ethernet ports + - One on-board 10G bps Base-T port. + - DDR Memory + - Supports 64-bit 4GB DDR3L DIMM + - PCIe + - One on-board PCIe slot. + - Two on-board PCIe Mini-PCIe connectors. + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - NAND: 1GB 8-bit NAND flash + - CPLD: for system controlling with programable header on-board + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - one SD connector supporting 1.8V/3.3V via J53. + - SPI + - On-board 64MB SPI flash + - Other + - Two Serial ports + - Four I2C ports + + +Memory map on T1024RDB +---------------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128MB NOR Flash memory Map +-------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +T1024 Clock frequency +--------------------- +BIN Core DDR Platform FMan +Bin1: 1400MHz 1600MT/s 400MHz 700MHz +Bin2: 1200MHz 1600MT/s 400MHz 600MHz +Bin3: 1000MHz 1600MT/s 400MHz 500MHz + + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T1024RDB_defconfig + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + + Switching between default bank0 and alternate bank4 on NOR flash + To change boot source to vbank4: + via software: run command 'cpld reset altbank' in u-boot. + via DIP-switch: set SW3[5:7] = '100' + + To change boot source to vbank0: + via software: run command 'cpld reset' in u-boot. + via DIP-Switch: set SW3[5:7] = '000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T1024RDB_NAND_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 $filesize + => nand write 1000000 0 $filesize + set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T1024RDB_SPIFLASH_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 f0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T1024RDB_SDCARD_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SD/MMC card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin + => mmc write 1000000 0x820 80 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (30KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T1024RDB +------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB(2 block) +0x100000 0x17FFFF u-boot env 512KB(1 block) +0x180000 0x1FFFFF FMAN Ucode 512KB(1 block) +0x200000 0x27FFFF QE Firmware 512KB(1 block) + + +SD Card memory Map on T1024RDB +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + + +SPI Flash memory Map on T1024RDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + + +For more details, please refer to T1024RDB Reference Manual and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c new file mode 100644 index 0000000000..c03894a265 --- /dev/null +++ b/board/freescale/t102xrdb/cpld.c @@ -0,0 +1,103 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Freescale T1024RDB board-specific CPLD controlling supports. + * + * The following macros need to be defined: + */ + +#include +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" + "cpld dump - display the CPLD registers\n" + ); diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h new file mode 100644 index 0000000000..db50f818fb --- /dev/null +++ b/board/freescale/t102xrdb/cpld.h @@ -0,0 +1,49 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_csr; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#define CPLD_BOOT_SEL 0x80 + +#define CPLD_PCIE_SGMII_MUX 0x80 +#define CPLD_OVERRIDE_BOOT_EN 0x01 +#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */ diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c new file mode 100644 index 0000000000..a2a8f4ccf0 --- /dev/null +++ b/board/freescale/t102xrdb/ddr.c @@ -0,0 +1,173 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * datarate_mhz_high values need to be in ascending order + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + struct cpu_type *cpu = gd->arch.cpu; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust according to the board ddr freqency and n_banks + * specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); + debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); + + /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, + * force DDR bus width to 32bit for T1023 + */ + if (cpu->soc_ver == SVR_T1023) + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; + +#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 + /* for DDR bus 32bit test on T1024 */ + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; +#endif +} + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + + return dram_size; +} diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c new file mode 100644 index 0000000000..f611ff07e9 --- /dev/null +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -0,0 +1,124 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); + + switch (srds_s1) { + case 0x95: + /* set the on-board RGMII2 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + + /* set 10G XFI with Aquantia AQR105 PHY */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + break; + case 0x77: + case 0x135: + /* set the on-board 2.5G SGMII AQR105 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR); + break; + default: + printf("SerDes protocol 0x%x is not supported on T102xRDB\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_SGMII_2500: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) && + (port == FM1_DTSEC3)) { + fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); + fdt_setprop(fdt, offset, "phy-connection-type", + "sgmii-2500", 10); + fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ +} diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c new file mode 100644 index 0000000000..1c9235fa3b --- /dev/null +++ b/board/freescale/t102xrdb/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c new file mode 100644 index 0000000000..ba7041af95 --- /dev/null +++ b/board/freescale/t102xrdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c new file mode 100644 index 0000000000..1a3a996439 --- /dev/null +++ b/board/freescale/t102xrdb/spl.c @@ -0,0 +1,114 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg new file mode 100644 index 0000000000..7b9e9b05f7 --- /dev/null +++ b/board/freescale/t102xrdb/t1024_pbi.cfg @@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/freescale/t102xrdb/t1024_rcw.cfg b/board/freescale/t102xrdb/t1024_rcw.cfg new file mode 100644 index 0000000000..cd6f906396 --- /dev/null +++ b/board/freescale/t102xrdb/t1024_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1024RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x95 +#Core/DDR: 1400Mhz/1600MT/s with single source clock +0810000c 00000000 00000000 00000000 +4a800003 80000012 ec027000 21000000 +00000000 00000000 00000000 00030810 +00000000 0b005a08 00000000 00000006 diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c new file mode 100644 index 0000000000..e196f12ac7 --- /dev/null +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -0,0 +1,172 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "t102xrdb.h" +#include "cpld.h" +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + u8 reg; + + reg = CPLD_READ(flash_csr); + + if (reg & CPLD_BOOT_SEL) { + puts("NAND\n"); + } else { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + printf("NOR vBank%d\n", reg); + } +#endif + + puts("SERDES Reference Clocks:\n"); + if (srds_s1 == 0x95) + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + else + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]); + + return 0; +} + +static void board_mux_lane(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + u8 reg = CPLD_READ(misc_ctl_status); + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (srds_prtcl_s1 == 0x95) { + /* Route Lane B to PCIE */ + CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); + } else { + /* Route Lane B to SGMII */ + CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); + } + CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); +} + +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_SYS_FLASH_BASE + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + board_mux_lane(); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h new file mode 100644 index 0000000000..2f23579b8f --- /dev/null +++ b/board/freescale/t102xrdb/t102xrdb.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T1024_RDB_H__ +#define __T1024_RDB_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c new file mode 100644 index 0000000000..8269b3d725 --- /dev/null +++ b/board/freescale/t102xrdb/tlb.c @@ -0,0 +1,117 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif + /* entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so if needed more, will use entry 16 later. + */ +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t1040qds/Kconfig b/board/freescale/t1040qds/Kconfig new file mode 100644 index 0000000000..1bb1684011 --- /dev/null +++ b/board/freescale/t1040qds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T1040QDS + +config SYS_BOARD + default "t1040qds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T1040QDS" + +endif diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS new file mode 100644 index 0000000000..83f6b3ce3a --- /dev/null +++ b/board/freescale/t1040qds/MAINTAINERS @@ -0,0 +1,12 @@ +T1040QDS BOARD +M: Poonam Aggrwal +S: Maintained +F: board/freescale/t1040qds/ +F: include/configs/T1040QDS.h +F: configs/T1040QDS_defconfig +F: configs/T1040QDS_D4_defconfig + +T1040QDS_SECURE_BOOT BOARD +M: Aneesh Bansal +S: Maintained +F: configs/T1040QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile new file mode 100644 index 0000000000..19ed21b7df --- /dev/null +++ b/board/freescale/t1040qds/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += t1040qds.o +obj-y += ddr.o +obj-$(CONFIG_PCI) += pci.o +obj-y += law.o +obj-y += tlb.o +obj-y += eth.o +obj-y += diu.o diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README new file mode 100644 index 0000000000..8160ca0bc0 --- /dev/null +++ b/board/freescale/t1040qds/README @@ -0,0 +1,169 @@ +Overview +-------- +The T1040QDS is a Freescale reference board that hosts the T1040 SoC +(and variants). + +T1040 SoC Overview +------------------ +The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA +processor cores with high-performance data path acceleration architecture +and network peripheral interfaces required for networking & telecommunications. + +The T1040/T1042 SoC includes the following function and features: + + - Four e5500 cores, each with a private 256 KB L2 cache + - 256 KB shared L3 CoreNet platform cache (CPC) + - Interconnect CoreNet platform + - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion + management + - Cryptography Acceleration (SEC 5.0) + - RegEx Pattern Matching Acceleration (PME 2.2) + - IEEE Std 1588 support + - Hardware buffer management for buffer allocation and deallocation + - Ethernet interfaces + - Integrated 8-port Gigabit Ethernet switch (T1040 only) + - Four 1 Gbps Ethernet controllers + - Two RGMII interfaces or one RGMII and one MII interfaces + - High speed peripheral interfaces + - Four PCI Express 2.0 controllers running at up to 5 GHz + - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation + - Upto two QSGMII interface + - Upto six SGMII interface supporting 1000 Mbps + - One SGMII interface supporting upto 2500 Mbps + - Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD and HDMI interface (DIU) with 12 bit dual data rate + - TDM interface + - Multicore programmable interrupt controller (PIC) + - Two 8-channel DMA engines + - Single source clocking implementation + - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) + + T1040QDS board Overview + ----------------------- + - SERDES Connections, 8 lanes supporting: + — PCI Express: supporting Gen 1 and Gen 2; + — SGMII + — QSGMII + — SATA 2.0 + — Aurora debug with dedicated connectors (T1040 only) + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. + -IFC/Local Bus + - NAND flash: 8-bit, async, up to 2GB. + - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB + - GASIC: Simple (minimal) target within Qixis FPGA + - PromJET rapid memory download support + - Ethernet + - Two on-board RGMII 10/100/1G ethernet ports. + - PHY #0 remains powered up during deep-sleep (T1040 only) + - QIXIS System Logic FPGA + - Clocks + - System and DDR clock (SYSCLK, “DDRCLK”) + - SERDES clocks + - Power Supplies + - Video + - DIU supports video at up to 1280x1024x32bpp + - USB + - Supports two USB 2.0 ports with integrated PHYs + — Two type A ports with 5V@1.5A per port. + — Second port can be converted to OTG mini-AB + - SDHC + - SDHC port connects directly to an adapter card slot, featuring: + - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC + — Supporting eMMC memory devices + - SPI + - On-board support of 3 different devices and sizes + - Other IO + - Two Serial ports + - ProfiBus port + - Four I2C ports + +Memory map on T1040QDS +---------------------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 2GB + + +NOR Flash memory Map on T1040QDS +-------------------------------- + Start End Definition Size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +Various Software configurations/environment variables/commands +-------------------------------------------------------------- +The below commands apply to T1040QDS + +1. U-boot environment variable hwconfig + The default hwconfig is: + hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: + dr_mode=host,phy_type=utmi + Note: For USB gadget set "dr_mode=peripheral" + +2. FMAN Ucode versions + fsl_fman_ucode_t1040.bin + +3. Switching to alternate bank + Commands for switching to alternate bank. + + 1. To change from vbank0 to vbank4 + => qixis_reset altbank (it will boot using vbank4) + + 2.To change from vbank4 to vbank0 + => qixis reset (it will boot using vbank0) + +T1040 Personality +-------------------- + +T1022 Personality +-------------------- +T1022 is a reduced personality of T1040 with less core/clusters. + +T1042 Personality +-------------------- +T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit +Ethernet switch. Rest of the blocks are same as T1040 diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c new file mode 100644 index 0000000000..82402408a7 --- /dev/null +++ b/board/freescale/t1040qds/ddr.c @@ -0,0 +1,135 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + + return dram_size; +} diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h new file mode 100644 index 0000000000..a6e1673525 --- /dev/null +++ b/board/freescale/t1040qds/ddr.h @@ -0,0 +1,53 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c new file mode 100644 index 0000000000..0214224707 --- /dev/null +++ b/board/freescale/t1040qds/diu.c @@ -0,0 +1,97 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Author: Priyanka Jain + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "../common/diu_ch7301.h" +#include "t1040qds.h" +#include "t1040qds_qixis.h" + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +void diu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long speed_ccb, temp; + u32 pixval; + int ret = 0; + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + + /* Program HDMI encoder */ + /* Switch channel to DIU */ + select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + + /* Set dispaly encoder */ + ret = diu_set_dvi_encoder(temp); + if (ret) { + puts("Failed to set DVI encoder\n"); + return; + } + + /* Switch channel to default */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + + /* Program pixel clock */ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, + ((pixval << PXCK_BITS_START) & PXCK_MASK)); + /* enable clock*/ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | + ((pixval << PXCK_BITS_START) & PXCK_MASK)); +} + +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) +{ + u32 pixel_format; + u8 sw; + + /*Route I2C4 to DIU system as HSYNC/VSYNC*/ + sw = QIXIS_READ(brdcfg[5]); + QIXIS_WRITE(brdcfg[5], + ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); + + /*Configure Display ouput port as HDMI*/ + sw = QIXIS_READ(brdcfg[15]); + QIXIS_WRITE(brdcfg[15], + ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) + | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); + + + return fsl_diu_init(xres, yres, pixel_format, 0); +} diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c new file mode 100644 index 0000000000..8c8293426b --- /dev/null +++ b/board/freescale/t1040qds/eth.c @@ -0,0 +1,591 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * The RGMII PHYs are provided by the two on-board PHY connected to + * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board + * PHY or by the standard four-port SGMII riser card (VSC). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "../common/qixis.h" + +#include "t1040qds_qixis.h" + +#ifdef CONFIG_FMAN_ENET + /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks. + * Bank 1 -> Lanes A, B, C, D + * Bank 2 -> Lanes E, F, G, H + */ + + /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here + * means that the mapping must be determined dynamically, or that the lane + * maps to something other than a board slot. + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs + * housed. + */ +static int riser_phy_addr[] = { + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, +}; + +/* Slot2 does not have EMI connections */ +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII0 0 +#define EMI1_RGMII1 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#define EMI2 8 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "T1040_QDS_MDIO0", + "T1040_QDS_MDIO1", + "T1040_QDS_MDIO2", + "T1040_QDS_MDIO3", + "T1040_QDS_MDIO4", + "T1040_QDS_MDIO5", + "T1040_QDS_MDIO6", + "T1040_QDS_MDIO7", +}; + +struct t1040_qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static const char *t1040_qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t1040_qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +static void t1040_qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval <= 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t1040_qds_mdio_reset(struct mii_dev *bus) +{ + struct t1040_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t1040_qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t1040_qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t1040_qds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t1040_qds private data\n"); + free(bus); + return -1; + } + + bus->read = t1040_qds_mdio_read; + bus->write = t1040_qds_mdio_write; + bus->reset = t1040_qds_mdio_reset; + sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +/* + * Initialize the lane_to_slot[] array. + * + * On the T1040QDS board the mapping is controlled by ?? register. + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL) + >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + QIXIS_WRITE(cms[0], 0x07); + + switch (serdes1_prtcl) { + case 0x60: + case 0x66: + case 0x67: + case 0x69: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + break; + case 0x86: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + case 0x87: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x89: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[6] = 7; + lane_to_slot[7] = 7; + break; + case 0x8d: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0x8F: + case 0x85: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA5: + lane_to_slot[1] = 7; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA7: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[7] = 7; + break; + case 0xAA: + lane_to_slot[1] = 7; + lane_to_slot[6] = 7; + lane_to_slot[7] = 7; + break; + case 0x40: + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + default: + printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used, and we recalculate the offset anyway. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + * + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + phy_interface_t intf = fm_info_get_enet_if(port); + char phy[16]; + + /* The RGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_RGMII) { + sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + + /* The SGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_SGMII) { + int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + + port); + u8 slot; + if (lane < 0) + return; + slot = lane_to_slot[lane]; + if (slot) { + /* Slot housing a SGMII riser card */ + sprintf(phy, "phy_s%x_%02x", slot, + (fm_info_get_phy_address(port - FM1_DTSEC1)- + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i, lane, idx; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + + switch (mdio_mux[i]) { + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT5: + fdt_status_okay_by_alias(fdt, "emi1_slot5"); + break; + case EMI1_SLOT6: + fdt_status_okay_by_alias(fdt, "emi1_slot6"); + break; + case EMI1_SLOT7: + fdt_status_okay_by_alias(fdt, "emi1_slot7"); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC4) + fdt_status_okay_by_alias(fdt, "emi1_rgmii0"); + + if (i == FM1_DTSEC5) + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + break; + default: + break; + } + } +} +#endif /* #ifdef CONFIG_FMAN_ENET */ + +static void set_brdcfg9_for_gtx_clk(void) +{ + u8 brdcfg9; + brdcfg9 = QIXIS_READ(brdcfg[9]); +/* Initializing EPHY2 clock to RGMII mode */ + brdcfg9 &= ~(BRDCFG9_EPHY2_MASK); + brdcfg9 |= (BRDCFG9_EPHY2_VAL); + QIXIS_WRITE(brdcfg[9], brdcfg9); +} + +void t1040_handle_phy_interface_sgmii(int i) +{ + int lane, idx, slot; + idx = i - FM1_DTSEC1; + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + + if (lane < 0) + return; + slot = lane_to_slot[lane]; + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + if (FM1_DTSEC4 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC5 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + + mdio_mux[i] = EMI1_SLOT3; + + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 5: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 6: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 7: + if (FM1_DTSEC1 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC2 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + if (FM1_DTSEC3 == i) + fm_info_set_phy_address(i, riser_phy_addr[2]); + if (FM1_DTSEC5 == i) + fm_info_set_phy_address(i, riser_phy_addr[3]); + + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} +void t1040_handle_phy_interface_rgmii(int i) +{ + fm_info_set_phy_address(i, i == FM1_DTSEC5 ? + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 : + EMI1_RGMII0; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; +#ifdef CONFIG_VSC9953 + int lane; + int phy_addr; + phy_interface_t phy_int; + struct mii_dev *bus; +#endif + + printf("Initializing Fman\n"); + set_brdcfg9_for_gtx_clk(); + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); + + /* + * Program on board RGMII PHY addresses. If the SGMII Riser + * card used, we'll override the PHY address later. For any DTSEC that + * is RGMII, we'll also override its PHY address later. We assume that + * DTSEC4 and DTSEC5 are used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_mdio(i, NULL); + break; + case PHY_INTERFACE_MODE_SGMII: + t1040_handle_phy_interface_sgmii(i); + break; + + case PHY_INTERFACE_MODE_RGMII: + /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ + t1040_handle_phy_interface_rgmii(i); + break; + default: + break; + } + } + +#ifdef CONFIG_VSC9953 + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + lane = -1; + phy_addr = 0; + phy_int = PHY_INTERFACE_MODE_NONE; + switch (i) { + case 0: + case 1: + case 2: + case 3: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A); + /* PHYs connected over QSGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + + i; + phy_int = PHY_INTERFACE_MODE_QSGMII; + break; + } + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_SW1_MAC1 + i); + + if (lane < 0) + break; + + /* PHYs connected over QSGMII */ + if (i != 3 || lane_to_slot[lane] == 7) + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + + i; + else + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR; + phy_int = PHY_INTERFACE_MODE_SGMII; + break; + case 4: + case 5: + case 6: + case 7: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B); + /* PHYs connected over QSGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + + i - 4; + phy_int = PHY_INTERFACE_MODE_QSGMII; + break; + } + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_SW1_MAC1 + i); + /* PHYs connected over SGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + + i - 3; + phy_int = PHY_INTERFACE_MODE_SGMII; + } + break; + case 8: + if (serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1) < 0) + /* FM1@DTSEC1 is connected to SW1@PORT8 */ + vsc9953_port_enable(i); + break; + case 9: + if (serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC2) < 0) { + /* Enable L2 On MAC2 using SCFG */ + struct ccsr_scfg *scfg = (struct ccsr_scfg *) + CONFIG_SYS_MPC85xx_SCFG; + + out_be32(&scfg->esgmiiselcr, + in_be32(&scfg->esgmiiselcr) | + (0x80000000)); + vsc9953_port_enable(i); + } + break; + } + + if (lane >= 0) { + bus = mii_dev_for_muxval(lane_to_slot[lane]); + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_enable(i); + } + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + } + +#endif + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c new file mode 100644 index 0000000000..a2dc027e4b --- /dev/null +++ b/board/freescale/t1040qds/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef QIXIS_BASE_PHYS + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t1040qds/pci.c b/board/freescale/t1040qds/pci.c new file mode 100644 index 0000000000..c53e3b76a4 --- /dev/null +++ b/board/freescale/t1040qds/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg new file mode 100644 index 0000000000..10b1a6d179 --- /dev/null +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -0,0 +1,27 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cf0 00000000 +09000cf4 fffc0000 +09000cf8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg new file mode 100644 index 0000000000..0d0dfa5a46 --- /dev/null +++ b/board/freescale/t1040qds/t1040_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0a10000c 0c000000 00000000 00000000 +66000002 00000000 fc027000 01000000 +00000000 00000000 00000000 00030810 +00000000 03fc500f 00000000 00000000 diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c new file mode 100644 index 0000000000..eaca57fc5d --- /dev/null +++ b/board/freescale/t1040qds/t1040qds.c @@ -0,0 +1,293 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/sleep.h" +#include "../common/qixis.h" +#include "t1040qds.h" +#include "t1040qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + struct cpu_type *cpu = gd->arch.cpu; + static const char *const freq[] = {"100", "125", "156.25", "161.13", + "122.88", "122.88", "122.88"}; + int clock; + + printf("Board: %sQDS, ", cpu->name); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFCCard\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference: "); + sw = QIXIS_READ(brdcfg[2]); + clock = (sw >> 6) & 3; + printf("Clock1=%sMHz ", freq[clock]); + clock = (sw >> 4) & 3; + printf("Clock2=%sMHz\n", freq[clock]); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static void qe_board_setup(void) +{ + u8 brdcfg15, brdcfg9; + + if (hwconfig("qe") && hwconfig("tdm")) { + brdcfg15 = QIXIS_READ(brdcfg[15]); + /* + * TDMRiser uses QE-TDM + * Route QE_TDM signals to TDM Riser slot + */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); + } else if (hwconfig("qe") && hwconfig("uart")) { + brdcfg15 = QIXIS_READ(brdcfg[15]); + brdcfg9 = QIXIS_READ(brdcfg[9]); + /* + * Route QE_TDM signals to UCC + * ProfiBus controlled by UCC3 + */ + brdcfg15 &= 0xfc; + QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); + QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); + } +} + +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_SYS_FLASH_BASE + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +#define NUM_SRDS_BANKS 2 +int misc_init_r(void) +{ + u8 sw; + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[NUM_SRDS_BANKS] = { 0 }; + int i; + + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < NUM_SRDS_BANKS; i++) { + unsigned int clock = (sw >> (6 - 2 * i)) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + } + } + + puts("SerDes1"); + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 pllcr0 = srds_regs->bank[i].pllcr0; + u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("expects ref clk%d %sMHz, but actual is %sMHz\n", + i + 1, serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + qe_board_setup(); + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} + +void qixis_dump_switch(void) +{ + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +} + +int board_need_mem_reset(void) +{ + return 1; +} diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h new file mode 100644 index 0000000000..5041f379de --- /dev/null +++ b/board/freescale/t1040qds/t1040qds.h @@ -0,0 +1,14 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T1040_QDS_H__ +#define __T1040_QDS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); +int select_i2c_ch_pca9547(u8 ch); + +#endif diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h new file mode 100644 index 0000000000..cef8ad0bfa --- /dev/null +++ b/board/freescale/t1040qds/t1040qds_qixis.h @@ -0,0 +1,52 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T1040QDS_QIXIS_H__ +#define __T1040QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T1040QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ +#define BRDCFG5_IMX_MASK 0xC0 +#define BRDCFG5_IMX_DIU 0x80 + +/* BRDCFG9[2] controls EPHY2 Clock */ +#define BRDCFG9_EPHY2_MASK 0x20 +#define BRDCFG9_EPHY2_VAL 0x00 + +/* BRDCFG15[3] controls LCD Panel Powerdown*/ +#define BRDCFG15_LCDPD_MASK 0x10 +#define BRDCFG15_LCDPD_ENABLED 0x00 + +/* BRDCFG15[6:7] controls DIU MUX selction*/ +#define BRDCFG15_DIUSEL_MASK 0x03 +#define BRDCFG15_DIUSEL_HDMI 0x00 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e +#endif diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c new file mode 100644 index 0000000000..412c591f1c --- /dev/null +++ b/board/freescale/t1040qds/tlb.c @@ -0,0 +1,108 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef QIXIS_BASE + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_4K, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig new file mode 100644 index 0000000000..f28728d33d --- /dev/null +++ b/board/freescale/t104xrdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T104XRDB + +config SYS_BOARD + default "t104xrdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T104xRDB" + +endif diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS new file mode 100644 index 0000000000..13d9be9da8 --- /dev/null +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -0,0 +1,24 @@ +T104XRDB BOARD +M: Priyanka Jain +S: Maintained +F: board/freescale/t104xrdb/ +F: include/configs/T104xRDB.h +F: configs/T1040RDB_defconfig +F: configs/T1040RDB_NAND_defconfig +F: configs/T1040RDB_SPIFLASH_defconfig +F: configs/T1042RDB_defconfig +F: configs/T1042RDB_PI_defconfig +F: configs/T1042RDB_PI_NAND_defconfig +F: configs/T1042RDB_PI_SPIFLASH_defconfig + +T1040RDB_SDCARD BOARD +#M: - +S: Maintained +F: configs/T1040RDB_SDCARD_defconfig +F: configs/T1042RDB_PI_SDCARD_defconfig + +T1040RDB_SECURE_BOOT BOARD +M: Aneesh Bansal +S: Maintained +F: configs/T1040RDB_SECURE_BOOT_defconfig +F: configs/T1042RDB_SECURE_BOOT_defconfig diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile new file mode 100644 index 0000000000..b9ef17f903 --- /dev/null +++ b/board/freescale/t104xrdb/Makefile @@ -0,0 +1,18 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += t104xrdb.o +obj-y += cpld.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_FSL_DIU_FB)+= diu.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README new file mode 100644 index 0000000000..ac95b5e509 --- /dev/null +++ b/board/freescale/t104xrdb/README @@ -0,0 +1,286 @@ +Overview +-------- +The T1040RDB is a Freescale reference board that hosts the T1040 SoC +(and variants). Variants inclued T1042 presonality of T1040, in which +case T1040RDB can also be called T1042RDB. + +The T1042RDB is a Freescale reference board that hosts the T1042 SoC +(and variants). The board is similar to T1040RDB, T1040 is a reduced +personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). + +The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. +(a personality of T1040 SoC). The board is similar to T1040RDB but is +designed specially with low power features targeted for Printing Image Market. + +Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB +------------------------------------------------------------------------- +Board Si Protocol Targeted Market +------------------------------------------------------------------------- +T1040RDB T1040 0x66 Networking +T1040RDB T1042 0x86 Networking +T1042RDB_PI T1042 0x06 Printing & Imaging + + +T1040 SoC Overview +------------------ +The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA +processor cores with high-performance data path acceleration architecture +and network peripheral interfaces required for networking & telecommunications. + +The T1040/T1042 SoC includes the following function and features: + + - Four e5500 cores, each with a private 256 KB L2 cache + - 256 KB shared L3 CoreNet platform cache (CPC) + - Interconnect CoreNet platform + - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion + management + - Cryptography Acceleration (SEC 5.0) + - RegEx Pattern Matching Acceleration (PME 2.2) + - IEEE Std 1588 support + - Hardware buffer management for buffer allocation and deallocation + - Ethernet interfaces + - Integrated 8-port Gigabit Ethernet switch (T1040 only) + - Four 1 Gbps Ethernet controllers + - Two RGMII interfaces or one RGMII and one MII interfaces + - High speed peripheral interfaces + - Four PCI Express 2.0 controllers running at up to 5 GHz + - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation + - Upto two QSGMII interface + - Upto six SGMII interface supporting 1000 Mbps + - One SGMII interface supporting upto 2500 Mbps + - Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD and HDMI interface (DIU) with 12 bit dual data rate + - TDM interface + - Multicore programmable interrupt controller (PIC) + - Two 8-channel DMA engines + - Single source clocking implementation + - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) + +T1040 SoC Personalities +------------------------- + +T1022 Personality: +T1022 is a reduced personality of T1040 with less core/clusters. + +T1042 Personality: +T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit +Ethernet switch. Rest of the blocks are same as T1040 + + +T1040RDB board Overview +------------------------- + - SERDES Connections, 8 lanes information: + 1: None + 2: SGMII + 3: QSGMII + 4: QSGMII + 5: PCIe1 x1 slot + 6: mini PCIe connector + 7: mini PCIe connector + 8: SATA connector + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. + - IFC/Local Bus + - NAND flash: 1GB 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Two on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, “DDRCLK”) + - SERDES clocks + - Power Supplies + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - SDHC/SDXC connector + - SPI + - On-board 64MB SPI flash + - Other IO + - Two Serial ports + - Four I2C ports + +T1042RDB_PI board Overview +------------------------- + - SERDES Connections, 8 lanes information: + 1, 2, 3, 4 : PCIe x4 slot + 5: mini PCIe connector + 6: mini PCIe connector + 7: NA + 8: SATA connector + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. + - IFC/Local Bus + - NAND flash: 1GB 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Two on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, “DDRCLK”) + - SERDES clocks + - Video + - DIU supports video at up to 1280x1024x32bpp + - Power Supplies + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - SDHC/SDXC connector + - SPI + - On-board 64MB SPI flash + - Other IO + - Two Serial ports + - Four I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 2GB + + +NOR Flash memory Map +--------------------- + Start End Definition Size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +Various Software configurations/environment variables/commands +-------------------------------------------------------------- +The below commands apply to the board + +1. U-boot environment variable hwconfig + The default hwconfig is: + hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: + dr_mode=host,phy_type=utmi + Note: For USB gadget set "dr_mode=peripheral" + +2. FMAN Ucode versions + fsl_fman_ucode_t1040.bin + +3. Switching to alternate bank + Commands for switching to alternate bank. + + 1. To change from vbank0 to vbank4 + => cpld reset altbank (it will boot using vbank4) + + 2.To change from vbank4 to vbank0 + => cpld reset (it will boot using vbank0) + +NAND boot with 2 Stage boot loader +---------------------------------- +PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +u-boot(768 KB) from flash to DDR. +Finally SPL transer control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + + Run time view of SPL framework during boot :- + ----------------------------------------------- + Area | Address | +----------------------------------------------- + Secure boot | 0xFFFC0000 (32KB) | + headers | | + ----------------------------------------------- + GD, BD | 0xFFFC8000 (4KB) | + ----------------------------------------------- + ENV | 0xFFFC9000 (8KB) | + ----------------------------------------------- + HEAP | 0xFFFCB000 (30KB) | + ----------------------------------------------- + STACK | 0xFFFD8000 (22KB) | + ----------------------------------------------- + U-boot SPL | 0xFFFD8000 (160KB) | + ----------------------------------------------- + +NAND Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x180000 0x19FFFF u-boot env 128KB +0x280000 0x29FFFF FMAN Ucode 128KB +0x380000 0x39FFFF QE Firmware 128KB + +SD Card memory Map on T104xRDB +------------------------------------------ + Block #blocks Definition Size +0x008 2048 u-boot 1MB +0x800 0024 u-boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + +SPI Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + +Please note QE Firmware is only valid for T1040RDB + + +Switch Settings: (ON is 0, OFF is 1) +=============== +NAND boot SW setting: +SW1: 10001000 +SW2: 00111011 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111011 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111011 +SW3: 11100001 diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c new file mode 100644 index 0000000000..df0e348d4a --- /dev/null +++ b/board/freescale/t104xrdb/cpld.c @@ -0,0 +1,112 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + */ + +#include +#include +#include + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} +#endif + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h new file mode 100644 index 0000000000..0da9a0159b --- /dev/null +++ b/board/freescale/t104xrdb/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_ctl_status; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c new file mode 100644 index 0000000000..5aa11b12a4 --- /dev/null +++ b/board/freescale/t104xrdb/ddr.c @@ -0,0 +1,147 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "RAW timing DDR"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + +#else + dram_size = fsl_ddr_sdram_size(); +#endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + + return dram_size; +} diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h new file mode 100644 index 0000000000..09b30b9aac --- /dev/null +++ b/board/freescale/t104xrdb/ddr.h @@ -0,0 +1,78 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 2147483648u, + .capacity = 4294967296u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, /* ECC */ + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 1071, + .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 6000, + .trp_ps = 13125, + .tras_ps = 34000, + .trc_ps = 48125, + .trfc_ps = 260000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 35000, +}; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 + */ + {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, + {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 833, 4, 4, 6, 0x06060607, 0x08080807}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807}, + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c new file mode 100644 index 0000000000..3285bef546 --- /dev/null +++ b/board/freescale/t104xrdb/diu.c @@ -0,0 +1,84 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Author: Priyanka Jain + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/diu_ch7301.h" + +#include "cpld.h" +#include "t104xrdb.h" + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +void diu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long speed_ccb, temp; + u32 pixval; + int ret; + + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + + /* Program HDMI encoder */ + ret = diu_set_dvi_encoder(temp); + if (ret) { + puts("Failed to set DVI encoder\n"); + return; + } + + /* Program pixel clock */ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, + ((pixval << PXCK_BITS_START) & PXCK_MASK)); + + /* enable clock*/ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | + ((pixval << PXCK_BITS_START) & PXCK_MASK)); +} + +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) +{ + u32 pixel_format; + u8 sw; + + /*Configure Display ouput port as HDMI*/ + sw = CPLD_READ(sfp_ctl_status); + CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP)); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres); + + return fsl_diu_init(xres, yres, pixel_format, 0); +} diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c new file mode 100644 index 0000000000..7581a4cdd4 --- /dev/null +++ b/board/freescale/t104xrdb/eth.c @@ -0,0 +1,138 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + int phy_addr = 0; +#ifdef CONFIG_VSC9953 + phy_interface_t phy_int; + struct mii_dev *bus; +#endif + + printf("Initializing Fman\n"); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* + * Program on board RGMII, SGMII PHY addresses. + */ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { +#ifdef CONFIG_T1040RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1040RDB only supports SGMII on DTSEC3 */ + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_SGMII1_PHY_ADDR); + break; +#endif +#ifdef CONFIG_T1042RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */ + if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i)) + fm_info_set_phy_address(i, 0); + /* T1042RDB only supports SGMII on DTSEC3 */ + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_SGMII1_PHY_ADDR); + break; +#endif + case PHY_INTERFACE_MODE_RGMII: + if (FM1_DTSEC4 == i) + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + if (FM1_DTSEC5 == i) + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; + case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII || + fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE) + fm_info_set_mdio(i, NULL); + else + fm_info_set_mdio(i, + miiphy_get_dev_by_name( + DEFAULT_FM_MDIO_NAME)); + } + +#ifdef CONFIG_VSC9953 + /* SerDes configured for QSGMII */ + if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) { + for (i = 0; i < 4; i++) { + bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; + phy_int = PHY_INTERFACE_MODE_QSGMII; + + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + vsc9953_port_enable(i); + } + } + if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) { + for (i = 4; i < 8; i++) { + bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; + phy_int = PHY_INTERFACE_MODE_QSGMII; + + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + vsc9953_port_enable(i); + } + } + + /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */ + if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0) + vsc9953_port_enable(8); + + /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */ + if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) { + /* Enable L2 On MAC2 using SCFG */ + struct ccsr_scfg *scfg = (struct ccsr_scfg *) + CONFIG_SYS_MPC85xx_SCFG; + + out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | + (0x80000000)); + vsc9953_port_enable(9); + } +#endif + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c new file mode 100644 index 0000000000..2362d4324b --- /dev/null +++ b/board/freescale/t104xrdb/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c new file mode 100644 index 0000000000..c53e3b76a4 --- /dev/null +++ b/board/freescale/t104xrdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c new file mode 100644 index 0000000000..4e8735b9ff --- /dev/null +++ b/board/freescale/t104xrdb/spl.c @@ -0,0 +1,134 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) + u32 porsr1, pinctl; + u32 svr = get_svr(); +#endif + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) + if (IS_SVR_REV(svr, 1, 0)) { + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible + * during NAND boot because IFC signals > IFC_AD7 are not + * enabled. This workaround changes RCW source to make all + * signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) + | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), + pinctl); + } +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t104xrdb/t1040_rcw.cfg b/board/freescale/t104xrdb/t1040_rcw.cfg new file mode 100644 index 0000000000..3300c184a1 --- /dev/null +++ b/board/freescale/t104xrdb/t1040_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 e8106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_pi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_rcw.cfg new file mode 100644 index 0000000000..57de89ad0e --- /dev/null +++ b/board/freescale/t104xrdb/t1042_pi_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x06 +0c18000e 0e000000 00000000 00000000 +06000002 00400002 e8106000 01000000 +00000000 00000000 00000000 00030810 +00000000 01fe0a06 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_rcw.cfg new file mode 100644 index 0000000000..db4d52f397 --- /dev/null +++ b/board/freescale/t104xrdb/t1042_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 80000002 ec027000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg new file mode 100644 index 0000000000..b83b9b7a45 --- /dev/null +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -0,0 +1,36 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c new file mode 100644 index 0000000000..9cd5e157c4 --- /dev/null +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -0,0 +1,124 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" +#include "t104xrdb.h" +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + u8 sw; + + printf("Board: %sRDB\n", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + + sw = CPLD_READ(flash_ctl_status); + sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + + return 0; +} + +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_SYS_FLASH_BASE + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + + return 0; +} diff --git a/board/freescale/t104xrdb/t104xrdb.h b/board/freescale/t104xrdb/t104xrdb.h new file mode 100644 index 0000000000..e7cc0c7b5e --- /dev/null +++ b/board/freescale/t104xrdb/t104xrdb.h @@ -0,0 +1,13 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T104x_RDB_H__ +#define __T104x_RDB_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c new file mode 100644 index 0000000000..95c15aa596 --- /dev/null +++ b/board/freescale/t104xrdb/tlb.c @@ -0,0 +1,119 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig new file mode 100644 index 0000000000..4e329dddf3 --- /dev/null +++ b/board/freescale/t208xqds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T208XQDS + +config SYS_BOARD + default "t208xqds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T208xQDS" + +endif diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS new file mode 100644 index 0000000000..deda092a6a --- /dev/null +++ b/board/freescale/t208xqds/MAINTAINERS @@ -0,0 +1,20 @@ +T208XQDS BOARD +#M: - +S: Maintained +F: board/freescale/t208xqds/ +F: include/configs/T208xQDS.h +F: configs/T2080QDS_defconfig +F: configs/T2080QDS_NAND_defconfig +F: configs/T2080QDS_SDCARD_defconfig +F: configs/T2080QDS_SPIFLASH_defconfig +F: configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +F: configs/T2081QDS_defconfig +F: configs/T2081QDS_NAND_defconfig +F: configs/T2081QDS_SDCARD_defconfig +F: configs/T2081QDS_SPIFLASH_defconfig +F: configs/T2081QDS_SRIO_PCIE_BOOT_defconfig + +T2080QDS_SECURE_BOOT BOARD +M: Aneesh Bansal +S: Maintained +F: configs/T2080QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile new file mode 100644 index 0000000000..6cb72c9fd5 --- /dev/null +++ b/board/freescale/t208xqds/Makefile @@ -0,0 +1,19 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-$(CONFIG_T2080QDS) += t208xqds.o +obj-$(CONFIG_T2080QDS) += eth_t208xqds.o +obj-$(CONFIG_T2081QDS) += t208xqds.o +obj-$(CONFIG_T2081QDS) += eth_t208xqds.o +obj-$(CONFIG_PCI) += pci.o +endif + +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README new file mode 100755 index 0000000000..83060c10f3 --- /dev/null +++ b/board/freescale/t208xqds/README @@ -0,0 +1,274 @@ +The T2080QDS is a high-performance computing evaluation, development and +test platform supporting the T2080 QorIQ Power Architecture processor. + +T2080 SoC Overview +------------------ +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power +Architecture processor cores with high-performance datapath acceleration +logic and network and peripheral bus interfaces required for networking, +telecom/datacom, wireless infrastructure, and mil/aerospace applications. + +T2080 includes the following functions and features: + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz + - 2MB L2 cache and 512KB CoreNet platform cache (CPC) + - Hierarchical interconnect fabric + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + - 16 SerDes lanes up to 10.3125 GHz + - 8 Ethernet interfaces, supporting combinations of the following: + - Up to four 10 Gbps Ethernet MACs + - Up to eight 1 Gbps Ethernet MACs + - Up to four 2.5 Gbps Ethernet MACs + - High-speed peripheral interfaces + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz + - Additional peripheral interfaces + - Two serial ATA (SATA 2.0) controllers + - Two high-speed USB 2.0 controllers with integrated PHY + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) + - Enhanced serial peripheral interface (eSPI) + - Four I2C controllers + - Four 2-pin UARTs or two 4-pin UARTs + - Integrated Flash Controller supporting NAND and NOR flash + - Three eight-channel DMA engines + - Support for hardware virtualization and partitioning enforcement + - QorIQ Platform's Trust Architecture 2.0 + +Differences between T2080 and T2081 +----------------------------------- + Feature T2080 T2081 + 1G Ethernet numbers: 8 6 + 10G Ethernet numbers: 4 2 + SerDes lanes: 16 8 + Serial RapidIO,RMan: 2 no + SATA Controller: 2 no + Aurora: yes no + SoC Package: 896-pins 780-pins + + +T2080QDS feature overview +------------------------- +Processor: + - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz +Memory: + - Single memory controller capable of supporting DDR3 and DDR3-LV devices + - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support +Ethernet interfaces: + - Two 1Gbps RGMII on-board ports + - Four 10Gbps XFI on-board cages + - 1Gbps/2.5Gbps SGMII Riser card + - 10Gbps XAUI Riser card +Accelerator: + - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC +SerDes: + - 16 lanes up to 10.3125GHz + - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI +IFC: + - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA +eSPI: + - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) +USB: + - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) +PCIE: + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) +SATA: + - Two SATA 2.0 ports on-board +SRIO: + - Two Serial RapidIO 2.0 ports up to 5 GHz +eSDHC: + - Supports SD/SDHC/SDXC/eMMC Card +I2C: + - Four I2C controllers. +UART: + - Dual 4-pins UART serial ports +System Logic: + - QIXIS-II FPGA system controll +Debug Features: + - Support Legacy, COP/JTAG, Aurora, Event and EVT +XFI: + - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to + a on-board SFP+ cages, which to house optical module (fiber cable) or + direct attach cable(copper), the copper cable is used to emulate + 10GBASE-KR scenario. + So, for XFI usage, there are two scenarios, one will use fiber cable, + another will use copper cable. An hwconfig env "fsl_10gkr_copper" is + introduced to indicate a XFI port will use copper cable, and U-boot + will fixup the dtb accordingly. + It's used as: fsl_10gkr_copper:<10g_mac_name> + The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they + do not have to be coexist in hwconfig. If a MAC is listed in the env + "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable + will be used by default. + for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in + hwconfig, then both four XFI ports will use copper cable. + set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two + XFI ports will use copper cable, the other two XFI ports will use fiber + cable. +1000BASE-KX(1G-KX): + - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane + runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane + in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration + Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper + initialization. + Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC + 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a + MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1' + stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc. + For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in + hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode. + +System Memory map +---------------- + +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128M NOR Flash memory Map +------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T2080QDS_config + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot + + Switching between default bank0 and alternate bank4 on NOR flash + To change boot source to vbank4: + by software: run command 'qixis_reset altbank' in u-boot. + by DIP-switch: set SW6[1:4] = '0100' + + To change boot source to vbank0: + by software: run command 'qixis_reset' in u-boot. + by DIP-Switch: set SW6[1:4] = '0000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T2080QDS_NAND_config + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 $filesize + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T2080QDS_SPIFLASH_config + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 f0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T2080QDS_SDCARD_config + $ make + b. program u-boot-with-spl-pbl.bin to SD/MMC card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + => tftp 1000000 fsl_fman_ucode_T2080_xx.bin + => mmc write 1000000 0x820 80 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T2080QDS +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB (2 blocks) +0x100000 0x17FFFF u-boot env 512KB (1 block) +0x180000 0x1FFFFF FMAN ucode 512KB (1 block) + + +Micro SD Card memory Map on T2080QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB + + +SPI Flash memory Map on T2080QDS +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x11FFFF FMAN ucode 64KB + + +How to update the ucode of Freescale FMAN +----------------------------------------- +=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize + + +For more details, please refer to T2080QDS User Guide and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c new file mode 100644 index 0000000000..3348971b01 --- /dev/null +++ b/board/freescale/t208xqds/ddr.c @@ -0,0 +1,122 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + + return dram_size; +} diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h new file mode 100644 index 0000000000..9c26fdf3bd --- /dev/null +++ b/board/freescale/t208xqds/ddr.h @@ -0,0 +1,71 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09}, + {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a}, + {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c}, + {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d}, + {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d}, + {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c}, + {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + /* TODO: need tuning these parameters if RDIMM is used */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; +#endif diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c new file mode 100644 index 0000000000..b82e9e7540 --- /dev/null +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -0,0 +1,812 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "../common/fman.h" +#include "t208xqds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#if defined(CONFIG_T2080QDS) +#define EMI1_SLOT2 6 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI2 7 +#elif defined(CONFIG_T2081QDS) +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#define EMI2 8 +#endif + +#define PCCR1_SGMIIA_KX_MASK 0x00008000 +#define PCCR1_SGMIIB_KX_MASK 0x00004000 +#define PCCR1_SGMIIC_KX_MASK 0x00002000 +#define PCCR1_SGMIID_KX_MASK 0x00001000 +#define PCCR1_SGMIIE_KX_MASK 0x00000800 +#define PCCR1_SGMIIF_KX_MASK 0x00000400 +#define PCCR1_SGMIIG_KX_MASK 0x00000200 +#define PCCR1_SGMIIH_KX_MASK 0x00000100 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { +#if defined(CONFIG_T2080QDS) + "T2080QDS_MDIO_RGMII1", + "T2080QDS_MDIO_RGMII2", + "T2080QDS_MDIO_SLOT1", + "T2080QDS_MDIO_SLOT3", + "T2080QDS_MDIO_SLOT4", + "T2080QDS_MDIO_SLOT5", + "T2080QDS_MDIO_SLOT2", + "T2080QDS_MDIO_10GC", +#elif defined(CONFIG_T2081QDS) + "T2081QDS_MDIO_RGMII1", + "T2081QDS_MDIO_RGMII2", + "T2081QDS_MDIO_SLOT1", + "T2081QDS_MDIO_SLOT2", + "T2081QDS_MDIO_SLOT3", + "T2081QDS_MDIO_SLOT5", + "T2081QDS_MDIO_SLOT6", + "T2081QDS_MDIO_SLOT7", + "T2081QDS_MDIO_10GC", +#endif +}; + +/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ +#if defined(CONFIG_T2080QDS) +static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; +#elif defined(CONFIG_T2081QDS) +static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; +#endif + +static const char *t208xqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t208xqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct t208xqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void t208xqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval < 8) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t208xqds_mdio *priv = bus->priv; + + t208xqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t208xqds_mdio *priv = bus->priv; + + t208xqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t208xqds_mdio_reset(struct mii_dev *bus) +{ + struct t208xqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t208xqds_mdio_init(char *realbusname, u8 muxval) +{ + struct t208xqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t208xqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t208xqds private data\n"); + free(bus); + return -1; + } + + bus->read = t208xqds_mdio_read; + bus->write = t208xqds_mdio_write; + bus->reset = t208xqds_mdio_reset; + sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + int phy; + char alias[20]; + char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; + char buf[32] = "serdes-1,"; + struct fixed_link f_link; + int media_type = 0; + int off; + + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_T2080QDS + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); +#endif + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + phy = fm_info_get_phy_address(port); + switch (port) { +#if defined(CONFIG_T2080QDS) + case FM1_DTSEC1: + if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx1"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIH_KX_MASK); + break; + } + case FM1_DTSEC2: + if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx2"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIG_KX_MASK); + break; + } + case FM1_DTSEC9: + if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx9"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIE_KX_MASK); + break; + } + case FM1_DTSEC10: + if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx10"); + fdt_status_okay_by_alias(fdt, + "1gkx_pcs_mdio10"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIF_KX_MASK); + break; + } + if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (mdio_mux[port] == EMI1_SLOT3) { + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + } + break; + case FM1_DTSEC5: + if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx5"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); + sprintf(buf, "%s%s%s", buf, "lane-g,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIC_KX_MASK); + break; + } + case FM1_DTSEC6: + if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx6"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); + sprintf(buf, "%s%s%s", buf, "lane-h,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIID_KX_MASK); + break; + } + if (mdio_mux[port] == EMI1_SLOT1) { + sprintf(alias, "phy_sgmii_s1_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + } else if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } + break; +#elif defined(CONFIG_T2081QDS) + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (mdio_mux[port] == EMI1_SLOT3) { + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + } else if (mdio_mux[port] == EMI1_SLOT5) { + sprintf(alias, "phy_sgmii_s5_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot5"); + } else if (mdio_mux[port] == EMI1_SLOT6) { + sprintf(alias, "phy_sgmii_s6_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot6"); + } else if (mdio_mux[port] == EMI1_SLOT7) { + sprintf(alias, "phy_sgmii_s7_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot7"); + } + break; +#endif + default: + break; + } + if (media_type) { + /* set property for 1000BASE-KX in dtb */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, "lane-instance", buf); + } + + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + switch (srds_s1) { + case 0x66: /* XFI interface */ + case 0x6b: + case 0x6c: + case 0x6d: + case 0x71: + /* + * if the 10G is XFI, check hwconfig to see what is the + * media type, there are two types, fiber or copper, + * fix the dtb accordingly. + */ + switch (port) { + case FM1_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { + /* it's MAC9 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi9"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { + /* it's MAC10 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi10"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC3: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { + /* it's MAC1 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi1"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC4: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { + /* it's MAC2 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi2"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode[1]); + } + break; + default: + return; + } + + if (!media_type) { + /* fixed-link is used for XFI fiber cable */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + } else { + /* set property for copper cable */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, + "lane-instance", buf); + } + break; + default: + break; + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +/* + * This function reads RCW to check if Serdes1{A:H} is configured + * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (srds_s1) { +#if defined(CONFIG_T2080QDS) + case 0x51: + case 0x5f: + case 0x65: + case 0x6b: + case 0x71: + lane_to_slot[5] = 2; + lane_to_slot[6] = 2; + lane_to_slot[7] = 2; + break; + case 0xa6: + case 0x8e: + case 0x8f: + case 0x82: + case 0x83: + case 0xd3: + case 0xd9: + case 0xcb: + lane_to_slot[6] = 2; + lane_to_slot[7] = 2; + break; + case 0xda: + lane_to_slot[4] = 3; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; +#elif defined(CONFIG_T2081QDS) + case 0x6b: + lane_to_slot[4] = 1; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xca: + case 0xcb: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xf2: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[5] = 4; + lane_to_slot[6] = 3; + lane_to_slot[7] = 7; + break; +#endif + default: + break; + } +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); +#if defined(CONFIG_T2080QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); +#endif + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); +#if defined(CONFIG_T2081QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); +#endif + t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + else + fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x1b: + case 0x1c: + case 0x95: + case 0xa2: + case 0x94: + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x50: + case 0x51: + case 0x5e: + case 0x5f: + case 0x64: + case 0x65: + /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x66: + case 0x67: + /* + * XFI does not need a PHY to work, but to avoid U-boot use + * default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to XFI + * MAC, and should not use a real XAUI PHY address, since + * MDIO can access it successfully, and then MDIO thinks + * the XAUI card is used for the XFI MAC, which will cause + * error. + */ + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + fm_info_set_phy_address(FM1_10GEC3, 6); + fm_info_set_phy_address(FM1_10GEC4, 7); + break; + case 0x6a: + case 0x6b: + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + fm_info_set_phy_address(FM1_10GEC3, 6); + fm_info_set_phy_address(FM1_10GEC4, 7); + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0x6c: + case 0x6d: + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x70: + case 0x71: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0xa6: + case 0x8e: + case 0x8f: + case 0x82: + case 0x83: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0xa4: + case 0x96: + case 0x8a: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + break; +#if defined(CONFIG_T2080QDS) + case 0xd9: + case 0xd3: + case 0xcb: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; +#elif defined(CONFIG_T2081QDS) + case 0xca: + case 0xcb: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + /* SGMII in Slot5 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + /* SGMII in Slot6 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + /* SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + break; +#endif + case 0xf2: + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; +#if defined(CONFIG_T2081QDS) + case 5: + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 6: + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 7: + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; +#endif + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4 || FM1_DTSEC10) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + idx = i - FM1_10GEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + if (srds_s1 == 0x51) { + lane = serdes_get_first_lane(FSL_SRDS_1, + XAUI_FM1_MAC9 + idx); + } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { + lane = serdes_get_first_lane(FSL_SRDS_1, + HIGIG_FM1_MAC9 + idx); + } else { + if (i == FM1_10GEC1 || i == FM1_10GEC2) + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC9 + idx); + else + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC1 + idx); + } + + if (lane < 0) + break; + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + + if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || + (srds_s1 == 0x6a) || (srds_s1 == 0x70) || + (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || + (srds_s1 == 0x71)) { + /* As XFI is in cage intead of a slot, so + * ensure doesn't disable the corresponding port + */ + break; + } + + slot = lane_to_slot[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c new file mode 100644 index 0000000000..74e2a53a8f --- /dev/null +++ b/board/freescale/t208xqds/law.c @@ -0,0 +1,34 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef QIXIS_BASE_PHYS + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c new file mode 100644 index 0000000000..84a89dad4f --- /dev/null +++ b/board/freescale/t208xqds/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c new file mode 100644 index 0000000000..a71c617121 --- /dev/null +++ b/board/freescale/t208xqds/spl.c @@ -0,0 +1,137 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "t208xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg new file mode 100644 index 0000000000..52a1652a22 --- /dev/null +++ b/board/freescale/t208xqds/t2080_rcw.cfg @@ -0,0 +1,16 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s +#12100017 15000000 00000000 00000000 +#66150002 00008400 e8104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s +0c070012 0e000000 00000000 00000000 +66150002 00000000 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_rcw.cfg new file mode 100644 index 0000000000..a2d5ecf4ad --- /dev/null +++ b/board/freescale/t208xqds/t2081_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#Default SerDes Protocol: 0x6C +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +6c000002 00008000 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg new file mode 100644 index 0000000000..e200d926fb --- /dev/null +++ b/board/freescale/t208xqds/t208x_pbi.cfg @@ -0,0 +1,41 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c new file mode 100644 index 0000000000..7c89cd5ee9 --- /dev/null +++ b/board/freescale/t208xqds/t208xqds.c @@ -0,0 +1,478 @@ +/* + * Copyright 2009-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "../common/vid.h" +#include "t208xqds.h" +#include "t208xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[4] = { + "100.00MHZ(from 8T49N222A)", "125.00MHz", + "156.25MHZ", "100.00MHz" + }; + + printf("Board: %sQDS, ", cpu->name); + sw = QIXIS_READ(arch); + printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); + printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank%d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), + qixis_read_tag(buf), (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + puts("SERDES Reference Clocks:\n"); + sw = QIXIS_READ(brdcfg[2]); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], + freq[(sw >> 4) & 0x3]); + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], + freq[sw & 0x3]); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +int brd_mux_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; +#if defined(CONFIG_T2080QDS) + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; +#endif + + switch (srds_prtcl_s1) { + case 0: + /* SerDes1 is not enabled */ + break; +#if defined(CONFIG_T2080QDS) + case 0x1b: + case 0x1c: + case 0xa2: + /* SD1(A:D) => SLOT3 SGMII + * SD1(G:H) => SLOT1 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x1a); + break; + case 0x94: + case 0x95: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:H) => SLOT1 SGMII@1.25bps + */ + case 0x96: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C) => SFP Module, SGMII@3.125bps + * SD1(D) => SFP Module, SGMII@1.25bps + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x3a); + break; + case 0x50: + case 0x51: + /* SD1(A:D) => SLOT3 XAUI + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x15); + break; + case 0x66: + case 0x67: + /* SD1(A:D) => XFI cage + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xfe); + break; + case 0x6a: + case 0x6b: + /* SD1(A:D) => XFI cage + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xf1); + break; + case 0x6c: + case 0x6d: + /* SD1(A:B) => XFI cage + * SD1(C:D) => SLOT3 SGMII + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xda); + break; + case 0x6e: + /* SD1(A:B) => SFP Module, XFI + * SD1(C:D) => SLOT3 SGMII + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xd9); + break; + case 0xda: + /* SD1(A:H) => SLOT3 PCIe3 x8 + */ + QIXIS_WRITE(brdcfg[12], 0x0); + break; + case 0xc8: + /* SD1(A) => SLOT3 PCIe3 x1 + * SD1(B) => SFP Module, SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x79); + break; + case 0xab: + /* SD1(A:D) => SLOT3 PCIe3 x4 + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x1a); + break; +#elif defined(CONFIG_T2081QDS) + case 0x50: + case 0x51: + /* SD1(A:D) => SLOT2 XAUI + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x98); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x6a: + case 0x6b: + /* SD1(A:D) => XFI SFP Module + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x80); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x6c: + case 0x6d: + /* SD1(A:B) => XFI SFP Module + * SD1(C:D) => SLOT2 SGMII + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xe8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0xaa: + case 0xab: + /* SD1(A:D) => SLOT2 PCIe3 x4 + * SD1(F:H) => SLOT1 SGMI4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xf8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0xca: + case 0xcb: + /* SD1(A) => SLOT2 PCIe3 x1 + * SD1(B) => SLOT7 SGMII + * SD1(C) => SLOT6 SGMII + * SD1(D) => SLOT5 SGMII + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x80); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0xde: + case 0xdf: + /* SD1(A:D) => SLOT2 PCIe3 x4 + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F) => SLOT4 PCIe1 x1 + * SD1(G) => SLOT3 PCIe2 x1 + * SD1(H) => SLOT7 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x98); + QIXIS_WRITE(brdcfg[13], 0x25); + break; + case 0xf2: + /* SD1(A) => SLOT2 PCIe3 x1 + * SD1(B:D) => SLOT7 SGMII + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F) => SLOT4 PCIe1 x1 + * SD1(G) => SLOT3 PCIe2 x1 + * SD1(H) => SLOT7 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x81); + QIXIS_WRITE(brdcfg[13], 0xa5); + break; +#endif + default: + printf("WARNING: unsupported for SerDes1 Protocol %d\n", + srds_prtcl_s1); + return -1; + } + +#ifdef CONFIG_T2080QDS + switch (srds_prtcl_s2) { + case 0: + /* SerDes2 is not enabled */ + break; + case 0x01: + case 0x02: + /* SD2(A:H) => SLOT4 PCIe1 */ + QIXIS_WRITE(brdcfg[13], 0x10); + break; + case 0x15: + case 0x16: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:F) => SLOT5 PCIe2 + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0xb0); + break; + case 0x18: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:F) => SLOT5 Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x78); + break; + case 0x1f: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:H) => SLOT5 PCIe2 + */ + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x29: + case 0x2d: + case 0x2e: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:H) => SLOT5 SRIO1 + */ + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x36: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:F) => Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x78); + break; + default: + printf("WARNING: unsupported for SerDes2 Protocol %d\n", + srds_prtcl_s2); + return -1; + } +#endif + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + /* Disable remote I2C connection to qixis fpga */ + QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); + + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + brd_mux_lane_to_slot(); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("SYS Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: SYS clock measurement is invalid, "); + printf("using value from brdcfg1.\n"); + } +#endif + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("DDR Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: DDR clock measurement is invalid, "); + printf("using value from brdcfg1.\n"); + } +#endif + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} diff --git a/board/freescale/t208xqds/t208xqds.h b/board/freescale/t208xqds/t208xqds.h new file mode 100644 index 0000000000..39fcef28c3 --- /dev/null +++ b/board/freescale/t208xqds/t208xqds.h @@ -0,0 +1,13 @@ +/* + * Copyright 2011-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h new file mode 100644 index 0000000000..bdcdc12f59 --- /dev/null +++ b/board/freescale/t208xqds/t208xqds_qixis.h @@ -0,0 +1,49 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T208xQDS_QIXIS_H__ +#define __T208xQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T208xQDS */ + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e + + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ + +#define BRDCFG9_SFP_TX_EN 0x10 + +#define BRDCFG12_SD3EN_MASK 0x20 +#define BRDCFG12_SD3MX_MASK 0x08 +#define BRDCFG12_SD3MX_SLOT5 0x08 +#define BRDCFG12_SD3MX_SLOT6 0x00 +#define BRDCFG12_SD4EN_MASK 0x04 +#define BRDCFG12_SD4MX_MASK 0x03 +#define BRDCFG12_SD4MX_SLOT7 0x02 +#define BRDCFG12_SD4MX_SLOT8 0x01 +#define BRDCFG12_SD4MX_AURO_SATA 0x00 +#endif diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c new file mode 100644 index 0000000000..8d602989b2 --- /dev/null +++ b/board/freescale/t208xqds/tlb.c @@ -0,0 +1,153 @@ +/* + * Copyright 2008-2013 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD + /* *I*G* - PCIe 1, 0x80000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef QIXIS_BASE_PHYS + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig new file mode 100644 index 0000000000..845af3dd2f --- /dev/null +++ b/board/freescale/t208xrdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T208XRDB + +config SYS_BOARD + default "t208xrdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T208xRDB" + +endif diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS new file mode 100644 index 0000000000..16428798cd --- /dev/null +++ b/board/freescale/t208xrdb/MAINTAINERS @@ -0,0 +1,15 @@ +T208XRDB BOARD +#M: - +S: Maintained +F: board/freescale/t208xrdb/ +F: include/configs/T208xRDB.h +F: configs/T2080RDB_defconfig +F: configs/T2080RDB_NAND_defconfig +F: configs/T2080RDB_SDCARD_defconfig +F: configs/T2080RDB_SPIFLASH_defconfig +F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig + +T2080RDB_SECURE_BOOT BOARD +M: Aneesh Bansal +S: Maintained +F: configs/T2080RDB_SECURE_BOOT_defconfig diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile new file mode 100644 index 0000000000..9605f8b606 --- /dev/null +++ b/board/freescale/t208xrdb/Makefile @@ -0,0 +1,18 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-$(CONFIG_T2080RDB) += t208xrdb.o +obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o +obj-$(CONFIG_T2080RDB) += cpld.o +obj-$(CONFIG_PCI) += pci.o +endif + +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README new file mode 100644 index 0000000000..24484cd0ff --- /dev/null +++ b/board/freescale/t208xrdb/README @@ -0,0 +1,264 @@ +T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. +It can work in two mode: standalone mode and PCIe endpoint mode. + +T2080 SoC Overview +------------------ +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power +Architecture processor cores with high-performance datapath acceleration +logic and network and peripheral bus interfaces required for networking, +telecom/datacom, wireless infrastructure, and mil/aerospace applications. + +T2080 includes the following functions and features: + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz + - 2MB L2 cache and 512KB CoreNet platform cache (CPC) + - Hierarchical interconnect fabric + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + - 16 SerDes lanes up to 10.3125 GHz + - 8 Ethernet interfaces, supporting combinations of the following: + - Up to four 10 Gbps Ethernet MACs + - Up to eight 1 Gbps Ethernet MACs + - Up to four 2.5 Gbps Ethernet MACs + - High-speed peripheral interfaces + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz + - Additional peripheral interfaces + - Two serial ATA (SATA 2.0) controllers + - Two high-speed USB 2.0 controllers with integrated PHY + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) + - Enhanced serial peripheral interface (eSPI) + - Four I2C controllers + - Four 2-pin UARTs or two 4-pin UARTs + - Integrated Flash Controller supporting NAND and NOR flash + - Three eight-channel DMA engines + - Support for hardware virtualization and partitioning enforcement + - QorIQ Platform's Trust Architecture 2.0 + +Differences between T2080 and T2081 +----------------------------------- + Feature T2080 T2081 + 1G Ethernet numbers: 8 6 + 10G Ethernet numbers: 4 2 + SerDes lanes: 16 8 + Serial RapidIO,RMan: 2 no + SATA Controller: 2 no + Aurora: yes no + SoC Package: 896-pins 780-pins + + +T2080PCIe-RDB board Overview +---------------------------- + - SERDES Configuration + - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) + - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) + - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) + - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) + - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) + - SerDes-2 Lane G-H: to SATA1 & SATA2 + - Ethernet + - Two on-board 10M/100M/1G RGMII ethernet ports + - Two on-board 10Gbps XFI fiber ports + - Two on-board 10Gbps Base-T copper ports + - DDR Memory + - Supports 72bit 4GB DDR3-LP SODIMM + - PCIe + - One PCIe x4 gold-finger + - One PCIe x4 connector + - One PCIe x2 end-point device (C293 Crypto co-processor) + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - NAND: 1GB 8-bit NAND flash + - CPLD: for system controlling with programable header on-board + - SATA + - Two SATA 2.0 onnectors on-board + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - one TF-card connector on-board + - SPI + - On-board 64MB SPI flash + - Other + - Two Serial ports + - Four I2C ports + + +System Memory map +----------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128M NOR Flash memory Map +------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +T2080PCIe-RDB Ethernet Port Map +------------------------------- +Label In Uboot In Linux FMan Address Comments PHY +ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315) +ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315) +ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202) +ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202) +ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E) +ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E) + + +T2080PCIe-RDB Default DIP-Switch setting +---------------------------------------- +SW1[1:8] = '00010011' +SW2[1:8] = '10111111' +SW3[1:8] = '11100001' + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T2080RDB_config + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + + Switching between default bank and alternate bank on NOR flash + To change boot source to vbank4: + via software: run command 'cpld reset altbank' in u-boot. + via DIP-switch: set SW3[5:7] = '100' + + To change boot source to vbank0: + via software: run command 'cpld reset' in u-boot. + via DIP-Switch: set SW3[5:7] = '000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T2080RDB_NAND_config + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 d0000 + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T2080RDB_SPIFLASH_config + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 d0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T2080RDB_SDCARD_config + $ make + b. program u-boot-with-spl-pbl.bin to micro-SD/TF card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T2080RDB +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB (2 blocks) +0x100000 0x17FFFF u-boot env 512KB (1 block) +0x180000 0x1FFFFF FMAN ucode 512KB (1 block) +0x200000 0x27FFFF CS4315 ucode 512KB (1 block) + + +Micro SD Card memory Map on T2080RDB +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB +0x8a0 0512 CS4315 ucode 256KB + + +SPI Flash memory Map on T2080RDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x11FFFF FMAN ucode 64KB +0x120000 0x15FFFF CS4315 ucode 256KB + + +How to update the ucode of Cortina CS4315/CS4340 10G PHY +-------------------------------------------------------- +=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt +=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize + + +How to update the ucode of Freescale FMAN +----------------------------------------- +=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize + + +For more details, please refer to T2080PCIe-RDB User Guide and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c new file mode 100644 index 0000000000..4aa126be54 --- /dev/null +++ b/board/freescale/t208xrdb/cpld.c @@ -0,0 +1,71 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Freescale T2080RDB board-specific CPLD controlling supports. + */ + +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/* Set the boot bank to the alternate bank */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); +} + +/* Set the boot bank to the default bank */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); +} + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset: reset to default bank\n" + "cpld reset altbank: reset to alternate bank\n" +); diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h new file mode 100644 index 0000000000..3f1533888d --- /dev/null +++ b/board/freescale/t208xrdb/cpld.h @@ -0,0 +1,42 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * CPLD register set of T2080RDB board-specific. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - Chip ID1 register */ + u8 chip_id2; /* 0x01 - Chip ID2 register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl; /* 0x10 - Reset control Register */ + u8 flash_csr; /* 0x11 - Flash control and status register */ + u8 thermal_csr; /* 0x12 - Thermal control and status register */ + u8 led_csr; /* 0x13 - LED control and status register */ + u8 sfp_csr; /* 0x14 - SFP+ control and status register */ + u8 misc_csr; /* 0x15 - Misc control and status register */ + u8 boot_or; /* 0x16 - Boot config override register */ + u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ + u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ +} cpld_data_t; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#define CPLD_BOOT_SEL 0x80 diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c new file mode 100644 index 0000000000..8a26276273 --- /dev/null +++ b/board/freescale/t208xrdb/ddr.c @@ -0,0 +1,114 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + return dram_size; +} diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h new file mode 100644 index 0000000000..b6d406219e --- /dev/null +++ b/board/freescale/t208xrdb/ddr.h @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c new file mode 100644 index 0000000000..cbbc625831 --- /dev/null +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -0,0 +1,106 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x66: + case 0x6b: + fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); + fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); + fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); + break; + default: + printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c new file mode 100644 index 0000000000..eb82431e22 --- /dev/null +++ b/board/freescale/t208xrdb/law.c @@ -0,0 +1,34 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c new file mode 100644 index 0000000000..ba7041af95 --- /dev/null +++ b/board/freescale/t208xrdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c new file mode 100644 index 0000000000..9ae2b1e863 --- /dev/null +++ b/board/freescale/t208xrdb/spl.c @@ -0,0 +1,107 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg new file mode 100644 index 0000000000..e200d926fb --- /dev/null +++ b/board/freescale/t208xrdb/t2080_pbi.cfg @@ -0,0 +1,41 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg new file mode 100644 index 0000000000..59025eaf1e --- /dev/null +++ b/board/freescale/t208xrdb/t2080_rcw.cfg @@ -0,0 +1,16 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s +#120c0017 15000000 00000000 00000000 +#66150002 00008400 ec104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s +1206001b 15000000 00000000 00000000 +66150002 00000000 e8104000 c1000000 +00800000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c new file mode 100644 index 0000000000..341453bc74 --- /dev/null +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -0,0 +1,131 @@ +/* + * Copyright 2009-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "t208xrdb.h" +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + u8 reg; + + reg = CPLD_READ(flash_csr); + + if (reg & CPLD_BOOT_SEL) { + puts("NAND\n"); + } else { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + printf("NOR vBank%d\n", reg); + } +#endif + + puts("SERDES Reference Clocks:\n"); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h new file mode 100644 index 0000000000..13380d02a3 --- /dev/null +++ b/board/freescale/t208xrdb/t208xrdb.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c new file mode 100644 index 0000000000..2ebea36a5c --- /dev/null +++ b/board/freescale/t208xrdb/tlb.c @@ -0,0 +1,153 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD + /* *I*G* - PCIe 1, 0x80000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig new file mode 100644 index 0000000000..ab34b9ef4c --- /dev/null +++ b/board/freescale/t4qds/Kconfig @@ -0,0 +1,25 @@ +if TARGET_T4240EMU + +config SYS_BOARD + default "t4qds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T4240EMU" + +endif + +if TARGET_T4240QDS + +config SYS_BOARD + default "t4qds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T4240QDS" + +endif diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS new file mode 100644 index 0000000000..f88ee7df9e --- /dev/null +++ b/board/freescale/t4qds/MAINTAINERS @@ -0,0 +1,26 @@ +T4QDS BOARD +#M: - +S: Maintained +F: board/freescale/t4qds/ +F: include/configs/T4240QDS.h +F: configs/T4160QDS_defconfig +F: configs/T4160QDS_NAND_defconfig +F: configs/T4160QDS_SDCARD_defconfig +F: configs/T4160QDS_SPIFLASH_defconfig +F: configs/T4240QDS_defconfig +F: configs/T4240QDS_NAND_defconfig +F: configs/T4240QDS_SDCARD_defconfig +F: configs/T4240QDS_SPIFLASH_defconfig +F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig + +T4160QDS_SECURE_BOOT BOARD +M: Aneesh Bansal +S: Maintained +F: configs/T4160QDS_SECURE_BOOT_defconfig +F: configs/T4240QDS_SECURE_BOOT_defconfig + +T4240EMU BOARD +M: York Sun +S: Maintained +F: include/configs/T4240EMU.h +F: configs/T4240EMU_defconfig diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index 85df066906..4e8e5cb8e9 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -4,35 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-$(CONFIG_T4240QDS)+= eth.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-$(CONFIG_T4240QDS) += t4240qds.o +obj-$(CONFIG_T4240EMU) += t4240emu.o +obj-$(CONFIG_T4240QDS)+= eth.o +obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README new file mode 100644 index 0000000000..3962fee7f2 --- /dev/null +++ b/board/freescale/t4qds/README @@ -0,0 +1,194 @@ +Overview +-------- +The T4240QDS is a high-performance computing evaluation, development and test +platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is +optimized to support the high-bandwidth DDR3 memory ports, as well as the +highly-configurable SerDes ports. The system is lead-free and RoHS-compliant. + +Board Features + SERDES Connections + 32 lanes grouped into four 8-lane banks + Two “front side” banks dedicated to Ethernet + - High-speed crosspoint switch fabric on selected lanes + - Two PCI Express slots with side-band connector supporting + - SGMII + - XAUI + - HiGig + - I-pass connectors allow board-to-board and loopback support + Two “back side” banks dedicated to other protocols + - High-speed crosspoint switch fabric on all lanes + - Four PCI Express slots with side-band connector supporting + - PCI Express 3.0 + - SATA 2.0 + - SRIO 2.0 + - Supports 4X Aurora debug with two connectors + DDR Controllers + Three independant 64-bit DDR3 controllers + Supports rates of 1866 up to 2133 MHz data-rate + Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller + DDR power supplies 1.5V to all devices with automatic tracking of VTT. + Power software-switchable to 1.35V if software detects all DDR3LP devices. + MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and + 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time + increases by 1 clock. + + IFC/Local Bus + NAND flash: 8-bit, async or sync, up to 2GB. + NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB + NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB + - NOR devices support 16 virtual banks + GASIC: Minimal target within Qixis FPGA + PromJET rapid memory download support + Address demultiplexing handled within FPGA. + - Flexible demux allows 8 or 16 bit evaluation. + IFC Debug/Development card + - Support for 32-bit devices + Ethernet + Support two on-board RGMII 10/100/1G ethernet ports. + SGMII and XAUI support via SERDES block (see above). + 1588 support via Symmetricom board. + QIXIS System Logic FPGA + Manages system power and reset sequencing + Manages DUT, board, clock, etc. configuration for dynamic shmoo + Collects V-I-T data in background for code/power profiling. + Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) + General fault monitoring and logging + Runs from ATX “hot” power rails allowing operation while system is off. + Clocks + System and DDR clock (SYSCLK, “DDRCLK”) + - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz. + - Software selectable in 1MHz increments from 1-200MHz. + SERDES clocks + - Provides clocks to all SerDes blocks and slots + - 100, 125 and 156.25 MHz + Power Supplies + Dedicated regulators for VDD + - Adjustable from (0.7V to 1.3V at 80A + - Regulators can be controlled by VID and/or software + Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A + - VTT/MVREF automatically track operating voltage + Dedicated regulators/filters for AVDD supplies + Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc. + USB + Supports two USB 2.0 ports with integrated PHYs + - One type A, one type micro-AB with 1.0A power per port. + Other IO + eSDHC/MMC + - SDHC card slot + eSPI port + - High-speed serial flash + Two Serial port + Four I2C ports + XFI + XFI is supported on T4QDS-XFI board which removed slot3 and routed + four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or + direct attach cable(copper), the copper cable is used to emulate + 10GBASE-KR scenario. + So, for XFI usage, there are two scenarios, one will use fiber cable, + another will use copper cable. An hwconfig env "fsl_10gkr_copper" is + introduced to indicate a XFI port will use copper cable, and U-boot + will fixup the dtb accordingly. + It's used as: fsl_10gkr_copper:<10g_mac_name> + The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they + do not have to be coexist in hwconfig. If a MAC is listed in the env + "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable + will be used by default. + for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in + hwconfig, then both four XFI ports will use copper cable. + set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two + XFI ports will use copper cable, the other two XFI ports will use fiber + cable. + +Memory map +---------- +The addresses in brackets are physical addresses. + +0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) +0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory +0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers) +0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan +0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan +0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO +0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash +0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR +0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS +0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores + +The physical address of the last (boot page translation) varies with the actual DDR size. + +Voltage ID and VDD override +-------------------- +T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage +accordingly. The voltage can also be override by command vdd_override. The +syntax is + +vdd_override , eg. 1050 is for 1.050v. + +Upon success, the actual voltage will be read back. The value is checked +for safety and any invalid value will not adjust the voltage. + +Another way to override VDD is to use environmental variable, in case of using +command is too late for some debugging. The syntax is + +setenv t4240qds_vdd_mv +saveenv +reset + +The override voltage takes effect when booting. + +Note: voltage adjustment needs to be done step by step. Changing voltage too +rapidly may cause current surge. The voltage stepping is done by software. +Users can set the final voltage directly. + +2-stage NAND/SD boot loader +------------------------------- +PBL initializes the internal SRAM and copy SPL(160K) in SRAM. +SPL further initialise DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T4QDS +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x140000 0x15FFFF u-boot env 128KB +0x160000 0x17FFFF FMAN Ucode 128KB + +Micro SD Card memory Map on T4QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB + +Switch Settings: (ON is 1, OFF is 0) +=============== +NAND boot SW setting: +SW1[1:8] = 10000010 +SW2[1.1] = 0 +SW6[1:4] = 1001 + +SD boot SW setting: +SW1[1:8] = 00100000 +SW2[1.1] = 0 diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 058d62511f..7abd38def1 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -10,84 +10,13 @@ #include #include #include -#include -#include +#include +#include #include +#include "ddr.h" DECLARE_GLOBAL_DATA_PTR; -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2T; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {} -}; - -/* - * The three slots have slightly different timing. The center values are good - * for all slots. We use identical speed tables for them. In future use, if - * DIMMs require separated tables, make more entries as needed. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0}, - {4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0}, - {4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {} -}; - -/* - * The three slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) @@ -127,7 +56,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -146,7 +75,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -188,11 +117,15 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h new file mode 100644 index 0000000000..8183af78fe --- /dev/null +++ b/board/freescale/t4qds/ddr.h @@ -0,0 +1,108 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +#ifdef CONFIG_T4240QDS +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {} +}; + +#else /* CONFIG_T4240EMU */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, + {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0}, + {2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0}, + {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, + {} +}; +#endif /* CONFIG_T4240EMU */ + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + + +#endif diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index c771e17952..9b416b138a 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include @@ -23,6 +23,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "../common/fman.h" @@ -172,7 +173,14 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval) void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + int interface = fm_info_get_enet_if(port); + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: if (qsgmiiphy_fix[port]) @@ -259,6 +267,76 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, default: break; } + } else if (interface == PHY_INTERFACE_MODE_XGMII && + ((prtcl2 == 55) || (prtcl2 == 57))) { + /* + * if the 10G is XFI, check hwconfig to see what is the + * media type, there are two types, fiber or copper, + * fix the dtb accordingly. + */ + int media_type = 0; + struct fixed_link f_link; + char lane_mode[20] = {"10GBASE-KR"}; + char buf[32] = "serdes-2,"; + int off; + + switch (port) { + case FM1_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi1"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode); + } + break; + case FM1_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi2"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode); + } + break; + case FM2_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi3"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode); + } + break; + case FM2_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi4"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode); + } + break; + default: + return; + } + + if (!media_type) { + /* fixed-link is used for XFI fiber cable */ + fdt_delprop(blob, offset, "phy-handle"); + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + fdt_setprop(blob, offset, "fixed-link", &f_link, + sizeof(f_link)); + } else { + /* set property for copper cable */ + off = fdt_node_offset_by_compat_reg(blob, + "fsl,fman-memac-mdio", pa + 0x1000); + fdt_setprop_string(blob, off, "lane-instance", buf); + } } } @@ -272,6 +350,7 @@ void fdt_fixup_board_enet(void *fdt) for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: fdt_status_okay_by_alias(fdt, "emi1_slot1"); @@ -291,8 +370,23 @@ void fdt_fixup_board_enet(void *fdt) break; case PHY_INTERFACE_MODE_XGMII: /* check if it's XFI interface for 10g */ - if ((prtcl2 == 56) || (prtcl2 == 57)) { - fdt_status_okay_by_alias(fdt, "emi2_xfislot3"); + if ((prtcl2 == 55) || (prtcl2 == 57)) { + if (i == FM1_10GEC1 && hwconfig_sub( + "fsl_10gkr_copper", "fm1_10g1")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio1"); + if (i == FM1_10GEC2 && hwconfig_sub( + "fsl_10gkr_copper", "fm1_10g2")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio2"); + if (i == FM2_10GEC1 && hwconfig_sub( + "fsl_10gkr_copper", "fm2_10g1")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio3"); + if (i == FM2_10GEC2 && hwconfig_sub( + "fsl_10gkr_copper", "fm2_10g2")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio4"); break; } switch (i) { @@ -393,7 +487,7 @@ static void initialize_qsgmiiphy_fix(void) int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot; + int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -445,7 +539,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); break; + case 27: case 28: + case 35: case 36: /* SGMII in Slot1 and Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); @@ -454,13 +550,14 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][3]); fm_info_set_phy_address(FM1_DTSEC10, slot_qsgmii_phyaddr[1][2]); } break; + case 37: case 38: fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); @@ -468,23 +565,26 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, - slot_qsgmii_phyaddr[1][3]); - fm_info_set_phy_address(FM1_DTSEC10, slot_qsgmii_phyaddr[1][2]); + fm_info_set_phy_address(FM1_DTSEC10, + slot_qsgmii_phyaddr[1][3]); } break; + case 39: case 40: + case 45: case 46: + case 47: case 48: fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC10, - slot_qsgmii_phyaddr[1][3]); - fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][2]); + fm_info_set_phy_address(FM1_DTSEC9, + slot_qsgmii_phyaddr[1][3]); } fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); @@ -498,15 +598,31 @@ int board_eth_init(bd_t *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; - switch (fm_info_get_enet_if(i)) { + interface = fm_info_get_enet_if(i); + switch (interface) { case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_QSGMII) { + if (idx <= 3) + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + else + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_B); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + debug("FM1@DTSEC%u expects QSGMII in slot %u\n", + idx + 1, slot); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm1[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + } if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { @@ -541,13 +657,18 @@ int board_eth_init(bd_t *bis) idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, + if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { + /* A fake PHY address to make U-boot happy */ + fm_info_set_phy_address(i, i); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, XAUI_FM1_MAC9 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm1[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + } mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; @@ -565,12 +686,17 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); break; + case 6: case 7: + case 12: case 13: case 14: + case 15: case 16: + case 21: case 22: case 23: + case 24: case 25: case 26: /* XAUI/HiGig in Slot3, SGMII in Slot4 */ @@ -580,7 +706,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; + case 27: case 28: + case 35: case 36: /* SGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -592,6 +720,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); break; + case 37: case 38: /* QSGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -600,11 +729,14 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); - fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); - fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); + fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]); + fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]); break; + case 39: case 40: + case 45: case 46: + case 47: case 48: /* SGMII in Slot3 */ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); @@ -617,8 +749,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; + case 49: case 50: + case 51: case 52: + case 53: case 54: fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -626,7 +761,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; - case 56: + case 55: case 57: /* XFI in Slot3, SGMII in Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -641,15 +776,31 @@ int board_eth_init(bd_t *bis) for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { idx = i - FM2_DTSEC1; - switch (fm_info_get_enet_if(i)) { + interface = fm_info_get_enet_if(i); + switch (interface) { case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_2, + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_QSGMII) { + if (idx <= 3) + lane = serdes_get_first_lane(FSL_SRDS_2, + QSGMII_FM2_A); + else + lane = serdes_get_first_lane(FSL_SRDS_2, + QSGMII_FM2_B); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + debug("FM2@DTSEC%u expects QSGMII in slot %u\n", + idx + 1, slot); + } else { + lane = serdes_get_first_lane(FSL_SRDS_2, SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm2[lane]; - debug("FM2@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + debug("FM2@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + } if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { @@ -687,13 +838,18 @@ int board_eth_init(bd_t *bis) idx = i - FM2_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(FSL_SRDS_2, + if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { + /* A fake PHY address to make U-boot happy */ + fm_info_set_phy_address(i, i); + } else { + lane = serdes_get_first_lane(FSL_SRDS_2, XAUI_FM2_MAC9 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm2[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + } mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c index 63549df2aa..367783bfe4 100644 --- a/board/freescale/t4qds/law.c +++ b/board/freescale/t4qds/law.c @@ -19,7 +19,9 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif +#ifdef QIXIS_BASE_PHYS SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c new file mode 100644 index 0000000000..0c6156e7f0 --- /dev/null +++ b/board/freescale/t4qds/spl.c @@ -0,0 +1,141 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "t4240qds_qixis.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + +#ifdef CONFIG_SPL_NAND_BOOT + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c new file mode 100644 index 0000000000..54410943f2 --- /dev/null +++ b/board/freescale/t4qds/t4240emu.c @@ -0,0 +1,88 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + + printf("Board: %sEMU\n", cpu->name); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + + return 0; +} diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c new file mode 100644 index 0000000000..4f2cccd709 --- /dev/null +++ b/board/freescale/t4qds/t4240qds.c @@ -0,0 +1,894 @@ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "t4qds.h" +#include "t4240qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, + {8, 8}, {9, 9}, {14, 14}, {15, 15} }; + +static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, + {10, 10}, {11, 11}, {12, 12}, {13, 13} }; + +static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, + {10, 11}, {11, 10}, {12, 2}, {13, 3} }; + +static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, + {8, 9}, {9, 8}, {14, 1}, {15, 0} }; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + struct cpu_type *cpu = gd->arch.cpu; + unsigned int i; + + printf("Board: %sQDS, ", cpu->name); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < MAX_SERDES; i++) { + static const char * const freq[] = { + "100", "125", "156.25", "161.1328125"}; + unsigned int clock = (sw >> (6 - 2 * i)) & 3; + + printf("SERDES%u=%sMHz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +/* + * read_voltage from sensor on I2C bus + * We use average of 4 readings, waiting for 532us befor another reading + */ +#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ +#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ + +static inline int read_voltage(void) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + + for (i = 0; i < NUM_READINGS; i++) { + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%04x\n", vol_mon); + /* LSB = 4mv */ + voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; + udelay(WAIT_FOR_ADC); + } + /* calculate the average */ + voltage_read /= NUM_READINGS; + + return voltage_read; +} + +/* + * We need to calculate how long before the voltage starts to drop or increase + * It returns with the loop count. Each loop takes several readings (532us) + */ +static inline int wait_for_voltage_change(int vdd_last) +{ + int timeout, vdd_current; + + vdd_current = read_voltage(); + /* wait until voltage starts to drop */ + for (timeout = 0; abs(vdd_last - vdd_current) <= 4 && + timeout < 100; timeout++) { + vdd_current = read_voltage(); + } + if (timeout >= 100) { + printf("VID: Voltage adjustment timeout\n"); + return -1; + } + return timeout; +} + +/* + * argument 'wait' is the time we know the voltage difference can be measured + * this function keeps reading the voltage until it is stable + */ +static inline int wait_for_voltage_stable(int wait) +{ + int timeout, vdd_current, vdd_last; + + vdd_last = read_voltage(); + udelay(wait * NUM_READINGS * WAIT_FOR_ADC); + /* wait until voltage is stable */ + vdd_current = read_voltage(); + for (timeout = 0; abs(vdd_last - vdd_current) >= 4 && + timeout < 100; timeout++) { + vdd_last = vdd_current; + udelay(wait * NUM_READINGS * WAIT_FOR_ADC); + vdd_current = read_voltage(); + } + if (timeout >= 100) { + printf("VID: Voltage adjustment timeout\n"); + return -1; + } + + return vdd_current; +} + +static inline int set_voltage(u8 vid) +{ + int wait, vdd_last; + + vdd_last = read_voltage(); + QIXIS_WRITE(brdcfg[6], vid); + wait = wait_for_voltage_change(vdd_last); + if (wait < 0) + return -1; + debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); + wait = wait ? wait : 1; + + vdd_last = wait_for_voltage_stable(wait); + if (vdd_last < 0) + return -1; + debug("VID: Current voltage is %d mV\n", vdd_last); + + return vdd_last; +} + + +static int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 fusesr; + u8 vid, vid_current; + int vdd_target, vdd_current, vdd_last; + int ret; + unsigned long vdd_string_override; + char *vdd_string; + static const uint16_t vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + struct vdd_drive { + u8 vid; + unsigned voltage; + }; + + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID: I2c failed to switch channel\n"); + ret = -1; + goto exit; + } + + /* get the voltage ID from fuse status register */ + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; + if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + } + vdd_target = vdd[vid]; + + /* check override variable for overriding VDD */ + vdd_string = getenv("t4240qds_vdd_mv"); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + if (vdd_override >= 819 && vdd_override <= 1212) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + + if (vdd_target == 0) { + debug("VID: VID not used\n"); + ret = 0; + goto exit; + } else { + /* round up and divice by 10 to get a value in mV */ + vdd_target = DIV_ROUND_UP(vdd_target, 10); + debug("VID: vid = %d mV\n", vdd_target); + } + + /* + * Check current board VID setting + * Voltage regulator support output to 6.250mv step + * The highes voltage allowed for this board is (vid=0x40) 1.21250V + * the lowest is (vid=0x7f) 0.81875V + */ + vid_current = QIXIS_READ(brdcfg[6]); + vdd_current = 121250 - (vid_current - 0x40) * 625; + debug("VID: Current vid setting is (0x%x) %d mV\n", + vid_current, vdd_current/100); + + /* + * Read voltage monitor to check real voltage. + * Voltage monitor LSB is 4mv. + */ + vdd_last = read_voltage(); + if (vdd_last < 0) { + printf("VID: Could not read voltage sensor abort VID adjustment\n"); + ret = -1; + goto exit; + } + debug("VID: Core voltage is at %d mV\n", vdd_last); + /* + * Adjust voltage to at or 8mV above target. + * Each step of adjustment is 6.25mV. + * Stepping down too fast may cause over current. + */ + while (vdd_last > 0 && vid_current < 0x80 && + vdd_last > (vdd_target + 8)) { + vid_current++; + vdd_last = set_voltage(vid_current); + } + /* + * Check if we need to step up + * This happens when board voltage switch was set too low + */ + while (vdd_last > 0 && vid_current >= 0x40 && + vdd_last < vdd_target + 2) { + vid_current--; + vdd_last = set_voltage(vid_current); + } + if (vdd_last > 0) + printf("VID: Core voltage %d mV\n", vdd_last); + else + ret = -1; + +exit: + if (re_enable) + enable_interrupts(); + return ret; +} + +/* Configure Crossbar switches for Front-Side SerDes Ports */ +int config_frontside_crossbar_vsc3316(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + int ret; + + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); + if (ret) + return ret; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + switch (srds_prtcl_s1) { + case 37: + case 38: + /* swap first lane and third lane on slot1 */ + vsc3316_fsm1_tx[0][1] = 14; + vsc3316_fsm1_tx[6][1] = 0; + vsc3316_fsm1_rx[1][1] = 2; + vsc3316_fsm1_rx[6][1] = 13; + case 39: + case 40: + case 45: + case 46: + case 47: + case 48: + /* swap first lane and third lane on slot2 */ + vsc3316_fsm1_tx[2][1] = 8; + vsc3316_fsm1_tx[4][1] = 6; + vsc3316_fsm1_rx[2][1] = 10; + vsc3316_fsm1_rx[5][1] = 5; + default: + ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); + if (ret) + return ret; + break; + } + + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + switch (srds_prtcl_s2) { + case 37: + case 38: + /* swap first lane and third lane on slot3 */ + vsc3316_fsm2_tx[2][1] = 11; + vsc3316_fsm2_tx[5][1] = 4; + vsc3316_fsm2_rx[2][1] = 9; + vsc3316_fsm2_rx[4][1] = 7; + case 39: + case 40: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + /* swap first lane and third lane on slot4 */ + vsc3316_fsm2_tx[6][1] = 3; + vsc3316_fsm2_tx[1][1] = 12; + vsc3316_fsm2_rx[0][1] = 1; + vsc3316_fsm2_rx[6][1] = 15; + default: + ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); + if (ret) + return ret; + break; + } + + return 0; +} + +int config_backside_crossbar_mux(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s3, srds_prtcl_s4; + u8 brdcfg; + + srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS3_PRTCL; + srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; + switch (srds_prtcl_s3) { + case 0: + /* SerDes3 is not enabled */ + break; + case 1: + case 2: + case 9: + case 10: + /* SD3(0:7) => SLOT5(0:7) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD3MX_MASK; + brdcfg |= BRDCFG12_SD3MX_SLOT5; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + /* SD3(4:7) => SLOT6(0:3) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD3MX_MASK; + brdcfg |= BRDCFG12_SD3MX_SLOT6; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + default: + printf("WARNING: unsupported for SerDes3 Protocol %d\n", + srds_prtcl_s3); + return -1; + } + + srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS4_PRTCL; + srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; + switch (srds_prtcl_s4) { + case 0: + /* SerDes4 is not enabled */ + break; + case 1: + case 2: + /* 10b, SD4(0:7) => SLOT7(0:7) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_SLOT7; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + /* x1b, SD4(4:7) => SLOT8(0:3) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_SLOT8; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 18: + /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_AURO_SATA; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + default: + printf("WARNING: unsupported for SerDes4 Protocol %d\n", + srds_prtcl_s4); + return -1; + } + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + /* Disable remote I2C connection to qixis fpga */ + QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); + + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + /* Configure board SERDES ports crossbar */ + config_frontside_crossbar_vsc3316(); + config_backside_crossbar_mux(); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("SYS Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n"); + } +#endif + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("DDR Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n"); + } +#endif + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +int misc_init_r(void) +{ + u8 sw; + void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds_regs; + u32 actual[MAX_SERDES]; + u32 pllcr0, expected; + unsigned int i; + + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < MAX_SERDES; i++) { + unsigned int clock = (sw >> (6 - 2 * i)) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + case 3: + actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; + break; + } + } + + for (i = 0; i < MAX_SERDES; i++) { + srds_regs = srds_base + i * 0x1000; + pllcr0 = srds_regs->bank[0].pllcr0; + expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", + i + 1, serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} + +/* + * This function is called by bdinfo to print detail board information. + * As an exmaple for future board, we organize the messages into + * several sections. If applicable, the message is in the format of + * = + * It should aligned with normal output of bdinfo command. + * + * Voltage: Core, DDR and another configurable voltages + * Clock : Critical clocks which are not printed already + * RCW : RCW source if not printed already + * Misc : Other important information not in above catagories + */ +void board_detail(void) +{ + int i; + u8 brdcfg[16], dutcfg[16], rst_ctl; + int vdd, rcwsrc; + static const char * const clk[] = {"66.67", "100", "125", "133.33"}; + + for (i = 0; i < 16; i++) { + brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); + dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); + } + + /* Voltage secion */ + if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { + vdd = read_voltage(); + if (vdd > 0) + printf("Core voltage= %d mV\n", vdd); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + } + + printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); + + /* clock section */ + printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n", + clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]); + + /* RCW section */ + rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1); + puts("RCW source = "); + switch (rcwsrc) { + case 0x017: + case 0x01f: + puts("8-bit NOR\n"); + break; + case 0x027: + case 0x02F: + puts("16-bit NOR\n"); + break; + case 0x040: + puts("SDHC/eMMC\n"); + break; + case 0x044: + puts("SPI 16-bit addressing\n"); + break; + case 0x045: + puts("SPI 24-bit addressing\n"); + break; + case 0x048: + puts("I2C normal addressing\n"); + break; + case 0x049: + puts("I2C extended addressing\n"); + break; + case 0x108: + case 0x109: + case 0x10a: + case 0x10b: + puts("8-bit NAND, 2KB\n"); + break; + default: + if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f)) + puts("Hard-coded RCW\n"); + else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f)) + puts("8-bit NAND, 4KB\n"); + else + puts("unknown\n"); + break; + } + + /* Misc section */ + rst_ctl = QIXIS_READ(rst_ctl); + puts("HRESET_REQ = "); + switch (rst_ctl & 0x30) { + case 0x00: + puts("Ignored\n"); + break; + case 0x10: + puts("Assert HRESET\n"); + break; + case 0x30: + puts("Reset system\n"); + break; + default: + puts("N/A\n"); + break; + } +} + +/* + * Reverse engineering switch settings. + * Some bits cannot be figured out. They will be displayed as + * underscore in binary format. mask[] has those bits. + * Some bits are calculated differently than the actual switches + * if booting with overriding by FPGA. + */ +void qixis_dump_switch(void) +{ + int i; + u8 sw[9]; + + /* + * Any bit with 1 means that bit cannot be reverse engineered. + * It will be displayed as _ in binary format. + */ + static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f}; + char buf[10]; + u8 brdcfg[16], dutcfg[16]; + + for (i = 0; i < 16; i++) { + brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); + dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); + } + + sw[0] = dutcfg[0]; + sw[1] = (dutcfg[1] << 0x07) | + ((dutcfg[12] & 0xC0) >> 1) | + ((dutcfg[11] & 0xE0) >> 3) | + ((dutcfg[6] & 0x80) >> 6) | + ((dutcfg[1] & 0x80) >> 7); + sw[2] = ((brdcfg[1] & 0x0f) << 4) | + ((brdcfg[1] & 0x30) >> 2) | + ((brdcfg[1] & 0x40) >> 5) | + ((brdcfg[1] & 0x80) >> 7); + sw[3] = brdcfg[2]; + sw[4] = ((dutcfg[2] & 0x01) << 7) | + ((dutcfg[2] & 0x06) << 4) | + ((~QIXIS_READ(present)) & 0x10) | + ((brdcfg[3] & 0x80) >> 4) | + ((brdcfg[3] & 0x01) << 2) | + ((brdcfg[6] == 0x62) ? 3 : + ((brdcfg[6] == 0x5a) ? 2 : + ((brdcfg[6] == 0x5e) ? 1 : 0))); + sw[5] = ((brdcfg[0] & 0x0f) << 4) | + ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | + ((brdcfg[0] & 0x40) >> 5); + sw[6] = (brdcfg[11] & 0x20) | + ((brdcfg[5] & 0x02) << 3); + sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | + ((brdcfg[5] & 0x10) << 2); + sw[8] = ((brdcfg[12] & 0x08) << 4) | + ((brdcfg[12] & 0x03) << 5); + + puts("DIP switch (reverse-engineering)\n"); + for (i = 0; i < 9; i++) { + printf("SW%d = 0b%s (0x%02x)\n", + i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); + } +} + +static int do_vdd_adjust(cmd_tbl_t *cmdtp, + int flag, int argc, + char * const argv[]) +{ + ulong override; + + if (argc < 2) + return CMD_RET_USAGE; + if (!strict_strtoul(argv[1], 10, &override)) + adjust_vdd(override); /* the value is checked by callee */ + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + vdd_override, 2, 0, do_vdd_adjust, + "Override VDD", + "- override with the voltage specified in mV, eg. 1050" +); diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg index c598fb5afd..6126266a96 100644 --- a/board/freescale/t4qds/t4_pbi.cfg +++ b/board/freescale/t4qds/t4_pbi.cfg @@ -13,20 +13,6 @@ 09000d00 00000000 09000d04 fff80000 09000d08 81000012 -#workaround for IFC bus speed -091241c0 f03f3f3f -091241c4 ff003f3f -09124010 00000101 -09124130 0000000c -#workaround for SERDES A-006031 -090ea000 064740e6 -090ea020 064740e6 -090eb000 064740e6 -090eb020 064740e6 -090ec000 064740e6 -090ec020 064740e6 -090ed000 064740e6 -090ed020 064740e6 #Configure alternate space 09000010 00000000 09000014 ff000000 diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg index 6ac95ffd52..6f09a7bba2 100644 --- a/board/freescale/t4qds/t4_rcw.cfg +++ b/board/freescale/t4qds/t4_rcw.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 010e0100 -#serdes protocol 1_28_6_12 -14180019 0c101916 00000000 00000000 -04383060 30548c00 6c020000 19000000 -00000000 ee0000ee 00000000 000187fc -00000000 00000000 00000000 00000018 +#serdes protocol 1_27_5_11 +16070019 18101916 00000000 00000000 +04362858 30548c00 ec020000 f5000000 +00000000 ee0000ee 00000000 000307fc +00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c deleted file mode 100644 index aa6a217f39..0000000000 --- a/board/freescale/t4qds/t4qds.c +++ /dev/null @@ -1,851 +0,0 @@ -/* - * Copyright 2009-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/qixis.h" -#include "../common/vsc3316_3308.h" -#include "t4qds.h" -#include "t4240qds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, - {8, 8}, {9, 9}, {14, 14}, {15, 15} }; - -static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, - {10, 10}, {11, 11}, {12, 12}, {13, 13} }; - -static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, - {10, 11}, {11, 10}, {12, 2}, {13, 3} }; - -static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, - {8, 9}, {9, 8}, {14, 1}, {15, 0} }; - -int checkboard(void) -{ - char buf[64]; - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - unsigned int i; - - printf("Board: %sQDS, ", cpu->name); - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", - QIXIS_READ(id), QIXIS_READ(arch)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - - /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference Clocks: "); - sw = QIXIS_READ(brdcfg[2]); - for (i = 0; i < MAX_SERDES; i++) { - static const char *freq[] = { - "100", "125", "156.25", "161.1328125"}; - unsigned int clock = (sw >> (6 - 2 * i)) & 3; - - printf("SERDES%u=%sMHz ", i+1, freq[clock]); - } - puts("\n"); - - return 0; -} - -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - -/* - * read_voltage from sensor on I2C bus - * We use average of 4 readings, waiting for 532us befor another reading - */ -#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ -#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ - -static inline int read_voltage(void) -{ - int i, ret, voltage_read = 0; - u16 vol_mon; - - for (i = 0; i < NUM_READINGS; i++) { - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); - if (ret) { - printf("VID: failed to read core voltage\n"); - return ret; - } - if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { - printf("VID: Core voltage sensor error\n"); - return -1; - } - debug("VID: bus voltage reads 0x%04x\n", vol_mon); - /* LSB = 4mv */ - voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; - udelay(WAIT_FOR_ADC); - } - /* calculate the average */ - voltage_read /= NUM_READINGS; - - return voltage_read; -} - -/* - * We need to calculate how long before the voltage starts to drop or increase - * It returns with the loop count. Each loop takes several readings (532us) - */ -static inline int wait_for_voltage_change(int vdd_last) -{ - int timeout, vdd_current; - - vdd_current = read_voltage(); - /* wait until voltage starts to drop */ - for (timeout = 0; abs(vdd_last - vdd_current) <= 4 && - timeout < 100; timeout++) { - vdd_current = read_voltage(); - } - if (timeout >= 100) { - printf("VID: Voltage adjustment timeout\n"); - return -1; - } - return timeout; -} - -/* - * argument 'wait' is the time we know the voltage difference can be measured - * this function keeps reading the voltage until it is stable - */ -static inline int wait_for_voltage_stable(int wait) -{ - int timeout, vdd_current, vdd_last; - - vdd_last = read_voltage(); - udelay(wait * NUM_READINGS * WAIT_FOR_ADC); - /* wait until voltage is stable */ - vdd_current = read_voltage(); - for (timeout = 0; abs(vdd_last - vdd_current) >= 4 && - timeout < 100; timeout++) { - vdd_last = vdd_current; - udelay(wait * NUM_READINGS * WAIT_FOR_ADC); - vdd_current = read_voltage(); - } - if (timeout >= 100) { - printf("VID: Voltage adjustment timeout\n"); - return -1; - } - - return vdd_current; -} - -static inline int set_voltage(u8 vid) -{ - int wait, vdd_last; - - vdd_last = read_voltage(); - QIXIS_WRITE(brdcfg[6], vid); - wait = wait_for_voltage_change(vdd_last); - if (wait < 0) - return -1; - debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); - wait = wait ? wait : 1; - - vdd_last = wait_for_voltage_stable(wait); - if (vdd_last < 0) - return -1; - debug("VID: Current voltage is %d mV\n", vdd_last); - - return vdd_last; -} - - -static int adjust_vdd(ulong vdd_override) -{ - int re_enable = disable_interrupts(); - ccsr_gur_t __iomem *gur = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 fusesr; - u8 vid, vid_current; - int vdd_target, vdd_current, vdd_last; - int ret; - unsigned long vdd_string_override; - char *vdd_string; - static const uint16_t vdd[32] = { - 0, /* unused */ - 9875, /* 0.9875V */ - 9750, - 9625, - 9500, - 9375, - 9250, - 9125, - 9000, - 8875, - 8750, - 8625, - 8500, - 8375, - 8250, - 8125, - 10000, /* 1.0000V */ - 10125, - 10250, - 10375, - 10500, - 10625, - 10750, - 10875, - 11000, - 0, /* reserved */ - }; - struct vdd_drive { - u8 vid; - unsigned voltage; - }; - - ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); - if (ret) { - debug("VID: I2c failed to switch channel\n"); - ret = -1; - goto exit; - } - - /* get the voltage ID from fuse status register */ - fusesr = in_be32(&gur->dcfg_fusesr); - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_VID_MASK; - if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; - } - vdd_target = vdd[vid]; - - /* check override variable for overriding VDD */ - vdd_string = getenv("t4240qds_vdd_mv"); - if (vdd_override == 0 && vdd_string && - !strict_strtoul(vdd_string, 10, &vdd_string_override)) - vdd_override = vdd_string_override; - if (vdd_override >= 819 && vdd_override <= 1212) { - vdd_target = vdd_override * 10; /* convert to 1/10 mV */ - debug("VDD override is %lu\n", vdd_override); - } else if (vdd_override != 0) { - printf("Invalid value.\n"); - } - - if (vdd_target == 0) { - debug("VID: VID not used\n"); - ret = 0; - goto exit; - } else { - /* round up and divice by 10 to get a value in mV */ - vdd_target = DIV_ROUND_UP(vdd_target, 10); - debug("VID: vid = %d mV\n", vdd_target); - } - - /* - * Check current board VID setting - * Voltage regulator support output to 6.250mv step - * The highes voltage allowed for this board is (vid=0x40) 1.21250V - * the lowest is (vid=0x7f) 0.81875V - */ - vid_current = QIXIS_READ(brdcfg[6]); - vdd_current = 121250 - (vid_current - 0x40) * 625; - debug("VID: Current vid setting is (0x%x) %d mV\n", - vid_current, vdd_current/100); - - /* - * Read voltage monitor to check real voltage. - * Voltage monitor LSB is 4mv. - */ - vdd_last = read_voltage(); - if (vdd_last < 0) { - printf("VID: Could not read voltage sensor abort VID adjustment\n"); - ret = -1; - goto exit; - } - debug("VID: Core voltage is at %d mV\n", vdd_last); - /* - * Adjust voltage to at or 8mV above target. - * Each step of adjustment is 6.25mV. - * Stepping down too fast may cause over current. - */ - while (vdd_last > 0 && vid_current < 0x80 && - vdd_last > (vdd_target + 8)) { - vid_current++; - vdd_last = set_voltage(vid_current); - } - /* - * Check if we need to step up - * This happens when board voltage switch was set too low - */ - while (vdd_last > 0 && vid_current >= 0x40 && - vdd_last < vdd_target + 2) { - vid_current--; - vdd_last = set_voltage(vid_current); - } - if (vdd_last > 0) - printf("VID: Core voltage %d mV\n", vdd_last); - else - ret = -1; - -exit: - if (re_enable) - enable_interrupts(); - return ret; -} - -/* Configure Crossbar switches for Front-Side SerDes Ports */ -int config_frontside_crossbar_vsc3316(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - int ret; - - ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); - if (ret) - return ret; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - if (srds_prtcl_s1) { - ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); - if (ret) - return ret; - ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); - if (ret) - return ret; - } - - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - if (srds_prtcl_s2) { - ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); - if (ret) - return ret; - ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); - if (ret) - return ret; - } - - return 0; -} - -int config_backside_crossbar_mux(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s3, srds_prtcl_s4; - u8 brdcfg; - - srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS3_PRTCL; - srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; - switch (srds_prtcl_s3) { - case 0: - /* SerDes3 is not enabled */ - break; - case 2: - case 9: - case 10: - /* SD3(0:7) => SLOT5(0:7) */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD3MX_MASK; - brdcfg |= BRDCFG12_SD3MX_SLOT5; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - case 4: - case 6: - case 8: - case 12: - case 14: - case 16: - case 17: - case 19: - case 20: - /* SD3(4:7) => SLOT6(0:3) */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD3MX_MASK; - brdcfg |= BRDCFG12_SD3MX_SLOT6; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - default: - printf("WARNING: unsupported for SerDes3 Protocol %d\n", - srds_prtcl_s3); - return -1; - } - - srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS4_PRTCL; - srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; - switch (srds_prtcl_s4) { - case 0: - /* SerDes4 is not enabled */ - break; - case 2: - /* 10b, SD4(0:7) => SLOT7(0:7) */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD4MX_MASK; - brdcfg |= BRDCFG12_SD4MX_SLOT7; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - case 4: - case 6: - case 8: - /* x1b, SD4(4:7) => SLOT8(0:3) */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD4MX_MASK; - brdcfg |= BRDCFG12_SD4MX_SLOT8; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - case 10: - case 12: - case 14: - case 16: - case 18: - /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD4MX_MASK; - brdcfg |= BRDCFG12_SD4MX_AURO_SATA; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - default: - printf("WARNING: unsupported for SerDes4 Protocol %d\n", - srds_prtcl_s4); - return -1; - } - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - - /* Disable remote I2C connection to qixis fpga */ - QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); - - /* - * Adjust core voltage according to voltage ID - * This function changes I2C mux to channel 2. - */ - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - - /* Configure board SERDES ports crossbar */ - config_frontside_crossbar_vsc3316(); - config_backside_crossbar_mux(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT - /* use accurate clock measurement */ - int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); - u32 val; - - val = freq * base; - if (val) { - debug("SYS Clock measurement is: %d\n", val); - return val; - } else { - printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n"); - } -#endif - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT - /* use accurate clock measurement */ - int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); - u32 val; - - val = freq * base; - if (val) { - debug("DDR Clock measurement is: %d\n", val); - return val; - } else { - printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n"); - } -#endif - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - case SRDS_PLLCR0_RFCK_SEL_161_13: - return "161.1328125"; - default: - return "???"; - } -} - -int misc_init_r(void) -{ - u8 sw; - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 actual[MAX_SERDES]; - unsigned int i; - - sw = QIXIS_READ(brdcfg[2]); - for (i = 0; i < MAX_SERDES; i++) { - unsigned int clock = (sw >> (6 - 2 * i)) & 3; - switch (clock) { - case 0: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 2: - actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - case 3: - actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; - break; - } - } - - for (i = 0; i < MAX_SERDES; i++) { - u32 pllcr0 = srds_regs->bank[i].pllcr0; - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES%u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); - fdt_fixup_board_enet(blob); -#endif -} - -/* - * This function is called by bdinfo to print detail board information. - * As an exmaple for future board, we organize the messages into - * several sections. If applicable, the message is in the format of - * = - * It should aligned with normal output of bdinfo command. - * - * Voltage: Core, DDR and another configurable voltages - * Clock : Critical clocks which are not printed already - * RCW : RCW source if not printed already - * Misc : Other important information not in above catagories - */ -void board_detail(void) -{ - int i; - u8 brdcfg[16], dutcfg[16], rst_ctl; - int vdd, rcwsrc; - static const char * const clk[] = {"66.67", "100", "125", "133.33"}; - - for (i = 0; i < 16; i++) { - brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); - dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); - } - - /* Voltage secion */ - if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { - vdd = read_voltage(); - if (vdd > 0) - printf("Core voltage= %d mV\n", vdd); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - } - - printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); - - /* clock section */ - printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n", - clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]); - - /* RCW section */ - rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1); - puts("RCW source = "); - switch (rcwsrc) { - case 0x017: - case 0x01f: - puts("8-bit NOR\n"); - break; - case 0x027: - case 0x02F: - puts("16-bit NOR\n"); - break; - case 0x040: - puts("SDHC/eMMC\n"); - break; - case 0x044: - puts("SPI 16-bit addressing\n"); - break; - case 0x045: - puts("SPI 24-bit addressing\n"); - break; - case 0x048: - puts("I2C normal addressing\n"); - break; - case 0x049: - puts("I2C extended addressing\n"); - break; - case 0x108: - case 0x109: - case 0x10a: - case 0x10b: - puts("8-bit NAND, 2KB\n"); - break; - default: - if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f)) - puts("Hard-coded RCW\n"); - else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f)) - puts("8-bit NAND, 4KB\n"); - else - puts("unknown\n"); - break; - } - - /* Misc section */ - rst_ctl = QIXIS_READ(rst_ctl); - puts("HRESET_REQ = "); - switch (rst_ctl & 0x30) { - case 0x00: - puts("Ignored\n"); - break; - case 0x10: - puts("Assert HRESET\n"); - break; - case 0x30: - puts("Reset system\n"); - break; - default: - puts("N/A\n"); - break; - } -} - -/* - * Reverse engineering switch settings. - * Some bits cannot be figured out. They will be displayed as - * underscore in binary format. mask[] has those bits. - * Some bits are calculated differently than the actual switches - * if booting with overriding by FPGA. - */ -void qixis_dump_switch(void) -{ - int i; - u8 sw[9]; - - /* - * Any bit with 1 means that bit cannot be reverse engineered. - * It will be displayed as _ in binary format. - */ - static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f}; - char buf[10]; - u8 brdcfg[16], dutcfg[16]; - - for (i = 0; i < 16; i++) { - brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); - dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); - } - - sw[0] = dutcfg[0]; - sw[1] = (dutcfg[1] << 0x07) | \ - ((dutcfg[12] & 0xC0) >> 1) | \ - ((dutcfg[11] & 0xE0) >> 3) | \ - ((dutcfg[6] & 0x80) >> 6) | \ - ((dutcfg[1] & 0x80) >> 7); - sw[2] = ((brdcfg[1] & 0x0f) << 4) | \ - ((brdcfg[1] & 0x30) >> 2) | \ - ((brdcfg[1] & 0x40) >> 5) | \ - ((brdcfg[1] & 0x80) >> 7); - sw[3] = brdcfg[2]; - sw[4] = ((dutcfg[2] & 0x01) << 7) | \ - ((dutcfg[2] & 0x06) << 4) | \ - ((~QIXIS_READ(present)) & 0x10) | \ - ((brdcfg[3] & 0x80) >> 4) | \ - ((brdcfg[3] & 0x01) << 2) | \ - ((brdcfg[6] == 0x62) ? 3 : \ - ((brdcfg[6] == 0x5a) ? 2 : \ - ((brdcfg[6] == 0x5e) ? 1 : 0))); - sw[5] = ((brdcfg[0] & 0x0f) << 4) | \ - ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \ - ((brdcfg[0] & 0x40) >> 5); - sw[6] = (brdcfg[11] & 0x20) | - ((brdcfg[5] & 0x02) << 3); - sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \ - ((brdcfg[5] & 0x10) << 2); - sw[8] = ((brdcfg[12] & 0x08) << 4) | \ - ((brdcfg[12] & 0x03) << 5); - - puts("DIP switch (reverse-engineering)\n"); - for (i = 0; i < 9; i++) { - printf("SW%d = 0b%s (0x%02x)\n", - i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); - } -} - -static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong override; - - if (argc < 2) - return CMD_RET_USAGE; - if (!strict_strtoul(argv[1], 10, &override)) - adjust_vdd(override); /* the value is checked by callee */ - else - return CMD_RET_USAGE; - - return 0; -} - -U_BOOT_CMD( - vdd_override, 2, 0, do_vdd_adjust, - "Override VDD", - "- override with the voltage specified in mV, eg. 1050" -); diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index b27356a5f7..1e4d096f5f 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -120,9 +121,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif +#ifdef QIXIS_BASE_PHYS SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for @@ -134,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig new file mode 100644 index 0000000000..d93e4532ac --- /dev/null +++ b/board/freescale/t4rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T4240RDB + +config SYS_BOARD + default "t4rdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T4240RDB" + +endif diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS new file mode 100644 index 0000000000..845c1b6d66 --- /dev/null +++ b/board/freescale/t4rdb/MAINTAINERS @@ -0,0 +1,7 @@ +T4RDB BOARD +M: Chunhe Lan +S: Maintained +F: board/freescale/t4rdb/ +F: include/configs/T4240RDB.h +F: configs/T4160RDB_defconfig +F: configs/T4240RDB_defconfig diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile new file mode 100644 index 0000000000..3886e3ded1 --- /dev/null +++ b/board/freescale/t4rdb/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += cpld.o +obj-y += ddr.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c new file mode 100644 index 0000000000..d5f3812872 --- /dev/null +++ b/board/freescale/t4rdb/cpld.c @@ -0,0 +1,136 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include +#include +#include + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 val, curbank, altbank, override; + + val = CPLD_READ(vbank); + curbank = val & CPLD_BANK_SEL_MASK; + + switch (curbank) { + case CPLD_SELECT_BANK0: + altbank = CPLD_SELECT_BANK4; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + case CPLD_SELECT_BANK4: + altbank = CPLD_SELECT_BANK0; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + default: + printf("CPLD Altbank Fail: Invalid value!\n"); + return; + } +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 val; + + val = CPLD_DEFAULT_BANK; + + CPLD_WRITE(global_reset, val); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); + printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); + printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); + printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("software_on = 0x%02x\n", CPLD_READ(software_on)); + printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); + printf("res0 = 0x%02x\n", CPLD_READ(res0)); + printf("vbank = 0x%02x\n", CPLD_READ(vbank)); + printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); + printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); + printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); + printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); + printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); + printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); + printf("res1 = 0x%02x\n", CPLD_READ(res1)); + putc('\n'); +} +#endif + +#ifndef CONFIG_SPL_BUILD +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); +#endif diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h new file mode 100644 index 0000000000..0180082ca3 --- /dev/null +++ b/board/freescale/t4rdb/cpld.h @@ -0,0 +1,49 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ + u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ + u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ + u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ + u8 hw_ver; /* 0x04 - PCBA Version Register */ + u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ + u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ + u8 res0; /* 0x07 - not used */ + u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ + u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ + u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ + u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ + u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ + u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ + u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ + u8 res1; /* 0x0f - not used */ +}; + +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_EN 0x04 +#define CPLD_SYSTEM_RESET 0x01 +#define CPLD_SELECT_BANK0 0x00 +#define CPLD_SELECT_BANK4 0x04 +#define CPLD_DEFAULT_BANK 0x01 + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c new file mode 100644 index 0000000000..5a43c1bc78 --- /dev/null +++ b/board/freescale/t4rdb/ddr.c @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data\n" + "rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h new file mode 100644 index 0000000000..7b854767e7 --- /dev/null +++ b/board/freescale/t4rdb/ddr.h @@ -0,0 +1,78 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a}, + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09}, + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b}, + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a}, + {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, + {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a}, + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a}, + {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + + +#endif diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c new file mode 100644 index 0000000000..879bd1a347 --- /dev/null +++ b/board/freescale/t4rdb/eth.c @@ -0,0 +1,146 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "t4rdb.h" + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { + /* SGMII */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); + } else { + puts("Invalid SerDes1 protocol for T4240RDB\n"); + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { + /* SGMII && XFI */ + fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); + } else { + puts("Invalid SerDes2 protocol for T4240RDB\n"); + } + + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c new file mode 100644 index 0000000000..39818fc4f1 --- /dev/null +++ b/board/freescale/t4rdb/law.c @@ -0,0 +1,31 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c new file mode 100644 index 0000000000..6387a20cae --- /dev/null +++ b/board/freescale/t4rdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c new file mode 100644 index 0000000000..fac442bfc8 --- /dev/null +++ b/board/freescale/t4rdb/t4240rdb.c @@ -0,0 +1,145 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "t4rdb.h" +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + u8 sw; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + + puts("SERDES Reference Clocks:\n"); + printf(" SERDES1=100MHz SERDES2=156.25MHz\n" + " SERDES3=100MHz SERDES4=100MHz\n"); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} + +/* + * This function is called by bdinfo to print detail board information. + * As an exmaple for future board, we organize the messages into + * several sections. If applicable, the message is in the format of + * = + * It should aligned with normal output of bdinfo command. + * + * Voltage: Core, DDR and another configurable voltages + * Clock : Critical clocks which are not printed already + * RCW : RCW source if not printed already + * Misc : Other important information not in above catagories + */ +void board_detail(void) +{ + int rcwsrc; + + /* RCW section SW3[4] */ + rcwsrc = 0x0; + puts("RCW source = "); + switch (rcwsrc & 0x1) { + case 0x1: + puts("SDHC/eMMC\n"); + break; + default: + puts("I2C normal addressing\n"); + break; + } +} diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg new file mode 100644 index 0000000000..c9f8ced2a3 --- /dev/null +++ b/board/freescale/t4rdb/t4_pbi.cfg @@ -0,0 +1,31 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#slow mdio clock +095fc030 00008148 +095fd030 00808148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg new file mode 100644 index 0000000000..e46c7b25a5 --- /dev/null +++ b/board/freescale/t4rdb/t4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#serdes protocol 27_55_1_9 +16070019 18101916 00000000 00000000 +6c6e0848 00448c00 6c020000 f5000000 +00000000 ee0000ee 00000000 000287fc +00000000 50000000 00000000 00000028 diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h new file mode 100644 index 0000000000..fb25d43291 --- /dev/null +++ b/board/freescale/t4rdb/t4rdb.h @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T4RDB_H__ +#define __T4RDB_H__ + +#undef CONFIG_SYS_NUM_FM1_DTSEC +#undef CONFIG_SYS_NUM_FM2_DTSEC +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM2_DTSEC 4 + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c new file mode 100644 index 0000000000..474301e2a7 --- /dev/null +++ b/board/freescale/t4rdb/tlb.c @@ -0,0 +1,116 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 512K SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_512K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/titanium/Makefile b/board/freescale/titanium/Makefile deleted file mode 100644 index 29a98f60b3..0000000000 --- a/board/freescale/titanium/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := titanium.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig new file mode 100644 index 0000000000..ef091d6b2b --- /dev/null +++ b/board/freescale/vf610twr/Kconfig @@ -0,0 +1,15 @@ +if TARGET_VF610TWR + +config SYS_BOARD + default "vf610twr" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "vf610" + +config SYS_CONFIG_NAME + default "vf610twr" + +endif diff --git a/board/freescale/vf610twr/MAINTAINERS b/board/freescale/vf610twr/MAINTAINERS new file mode 100644 index 0000000000..f2997f05c3 --- /dev/null +++ b/board/freescale/vf610twr/MAINTAINERS @@ -0,0 +1,7 @@ +VF610TWR BOARD +M: Alison Wang +S: Maintained +F: board/freescale/vf610twr/ +F: include/configs/vf610twr.h +F: configs/vf610twr_defconfig +F: configs/vf610twr_nand_defconfig diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile index 1541fd67d1..20b4a6be6b 100644 --- a/board/freescale/vf610twr/Makefile +++ b/board/freescale/vf610twr/Makefile @@ -4,23 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := vf610twr.o diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 699ea7f010..b634965ad2 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -30,7 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; void setup_iomux_ddr(void) { static const iomux_v3_cfg_t ddr_pads[] = { - VF610_PAD_DDR_A15__DDR_A_15, VF610_PAD_DDR_A15__DDR_A_15, VF610_PAD_DDR_A14__DDR_A_14, VF610_PAD_DDR_A13__DDR_A_13, @@ -46,6 +45,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_A3__DDR_A_3, VF610_PAD_DDR_A2__DDR_A_2, VF610_PAD_DDR_A1__DDR_A_1, + VF610_PAD_DDR_A0__DDR_A_0, VF610_PAD_DDR_BA2__DDR_BA_2, VF610_PAD_DDR_BA1__DDR_BA_1, VF610_PAD_DDR_BA0__DDR_BA_0, @@ -77,6 +77,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_WE__DDR_WE_B, VF610_PAD_DDR_ODT1__DDR_ODT_0, VF610_PAD_DDR_ODT0__DDR_ODT_1, + VF610_PAD_DDR_RESETB, }; imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); @@ -89,30 +90,30 @@ void ddr_phy_init(void) writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); - writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]); + + /* LPDDR2 only parameter */ + writel(DDRMC_PHY_OFF, &ddrmr->phy[49]); writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]); + + /* Processor Pad ODT settings */ + writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]); } void ddr_ctrl_init(void) @@ -121,12 +122,12 @@ void ddr_ctrl_init(void) writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); - writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]); + writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]); - writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]); + writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); - writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) | - DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]); + writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4), + &ddrmr->cr[13]); writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); @@ -135,24 +136,23 @@ void ddr_ctrl_init(void) writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]); writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); - writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT | - DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); + writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); - writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]); + writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]); writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]); writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); - writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); - writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]); + writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); + writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]); writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); - writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]); + writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]); writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]); - writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]); + writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); @@ -165,37 +165,45 @@ void ddr_ctrl_init(void) writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); - writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]); + writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]); writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | - DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255), + DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64), &ddrmr->cr[74]); writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | DDRMC_CR75_PLEN, &ddrmr->cr[75]); writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | - DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]); + DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); - writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); - writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]); + writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12), + &ddrmr->cr[78]); + writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); - writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0, - &ddrmr->cr[87]); + writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]); writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); + writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]); + writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]); + writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]); - writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]); - writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]); - writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]); + writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, + &ddrmr->cr[102]); - writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), + writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]); + writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]); + writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]); + writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]); + writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]); + + writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]); writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]); @@ -206,22 +214,40 @@ void ddr_ctrl_init(void) &ddrmr->cr[121]); writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); - writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1), - &ddrmr->cr[123]); + writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]); writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); - writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]); + writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]); + writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]); + writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1), + &ddrmr->cr[138]); writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]); + writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]); + writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128), + &ddrmr->cr[143]); + writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | + DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3), + &ddrmr->cr[144]); + writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]); + writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]); + writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]); + writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]); + writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]); writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]); - writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), + DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]); + writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); + writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | + DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]); ddr_phy_init(); @@ -278,6 +304,59 @@ static void setup_iomux_i2c(void) imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); } +#ifdef CONFIG_NAND_VF610_NFC +static void setup_iomux_nfc(void) +{ + static const iomux_v3_cfg_t nfc_pads[] = { + VF610_PAD_PTD31__NF_IO15, + VF610_PAD_PTD30__NF_IO14, + VF610_PAD_PTD29__NF_IO13, + VF610_PAD_PTD28__NF_IO12, + VF610_PAD_PTD27__NF_IO11, + VF610_PAD_PTD26__NF_IO10, + VF610_PAD_PTD25__NF_IO9, + VF610_PAD_PTD24__NF_IO8, + VF610_PAD_PTD23__NF_IO7, + VF610_PAD_PTD22__NF_IO6, + VF610_PAD_PTD21__NF_IO5, + VF610_PAD_PTD20__NF_IO4, + VF610_PAD_PTD19__NF_IO3, + VF610_PAD_PTD18__NF_IO2, + VF610_PAD_PTD17__NF_IO1, + VF610_PAD_PTD16__NF_IO0, + VF610_PAD_PTB24__NF_WE_B, + VF610_PAD_PTB25__NF_CE0_B, + VF610_PAD_PTB27__NF_RE_B, + VF610_PAD_PTC26__NF_RB_B, + VF610_PAD_PTC27__NF_ALE, + VF610_PAD_PTC28__NF_CLE + }; + + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); +} +#endif + + +static void setup_iomux_qspi(void) +{ + static const iomux_v3_cfg_t qspi0_pads[] = { + VF610_PAD_PTD0__QSPI0_A_QSCK, + VF610_PAD_PTD1__QSPI0_A_CS0, + VF610_PAD_PTD2__QSPI0_A_DATA3, + VF610_PAD_PTD3__QSPI0_A_DATA2, + VF610_PAD_PTD4__QSPI0_A_DATA1, + VF610_PAD_PTD5__QSPI0_A_DATA0, + VF610_PAD_PTD7__QSPI0_B_QSCK, + VF610_PAD_PTD8__QSPI0_B_CS0, + VF610_PAD_PTD9__QSPI0_B_DATA3, + VF610_PAD_PTD10__QSPI0_B_DATA2, + VF610_PAD_PTD11__QSPI0_B_DATA1, + VF610_PAD_PTD12__QSPI0_B_DATA0, + }; + + imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); +} + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, @@ -321,7 +400,8 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | - CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); + CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | + CCM_CCGR2_QSPI0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, CCM_CCGR3_ANADIG_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, @@ -333,6 +413,8 @@ static void clock_init(void) CCM_CCGR7_SDHC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, + CCM_CCGR10_NFC_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); @@ -352,11 +434,17 @@ static void clock_init(void) CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, - CCM_CSCMR1_ESDHC1_CLK_SEL(3)); + CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | + CCM_CSCMR1_NFC_CLK_SEL(0)); clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, CCM_CSCDR1_RMII_CLK_EN); clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, - CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0)); + CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | + CCM_CSCDR2_NFC_EN); + clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, + CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | + CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | + CCM_CSCDR3_NFC_PRE_DIV(5)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(0)); } @@ -386,6 +474,10 @@ int board_early_init_f(void) setup_iomux_uart(); setup_iomux_enet(); setup_iomux_i2c(); + setup_iomux_qspi(); +#ifdef CONFIG_NAND_VF610_NFC + setup_iomux_nfc(); +#endif return 0; } diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile deleted file mode 100644 index d0d2add835..0000000000 --- a/board/friendlyarm/mini2440/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2012 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mini2440.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c deleted file mode 100644 index 59ed0548e7..0000000000 --- a/board/friendlyarm/mini2440/mini2440.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2009 - * Michel Pollet - * - * (C) Copyright 2012 - * Gabriel Huau - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include "mini2440.h" - -DECLARE_GLOBAL_DATA_PTR; - -static inline void pll_delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0" (loops)); -} - -int board_early_init_f(void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */ - clk_power->clkdivn = CLKDIVN_VAL; - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - /* some delay between MPLL and UPLL */ - pll_delay(100); - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - pll_delay(10000); - - return 0; -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* IOMUX Port H : UART Configuration */ - gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 | - IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2; - - gpio_direction_output(GPH8, 0); - gpio_direction_output(GPH9, 0); - gpio_direction_output(GPH10, 0); - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; - - return 0; -} - -int dram_init(void) -{ - struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl(); - - /* - * Configuring bus width and timing - * Initialize clocks for each bank 0..5 - * Bank 3 and 4 are used for DM9000 - */ - writel(BANK_CONF, &memctl->bwscon); - writel(B0_CONF, &memctl->bankcon[0]); - writel(B1_CONF, &memctl->bankcon[1]); - writel(B2_CONF, &memctl->bankcon[2]); - writel(B3_CONF, &memctl->bankcon[3]); - writel(B4_CONF, &memctl->bankcon[4]); - writel(B5_CONF, &memctl->bankcon[5]); - - /* Bank 6 and 7 are used for DRAM */ - writel(SDRAM_64MB, &memctl->bankcon[6]); - writel(SDRAM_64MB, &memctl->bankcon[7]); - - writel(MEM_TIMING, &memctl->refresh); - writel(BANKSIZE_CONF, &memctl->banksize); - writel(B6_MRSR, &memctl->mrsrb6); - writel(B7_MRSR, &memctl->mrsrb7); - - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_DRIVER_DM9000 - return dm9000_initialize(bis); -#else - return 0; -#endif -} diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h deleted file mode 100644 index db386eac01..0000000000 --- a/board/friendlyarm/mini2440/mini2440.h +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef __MINI2440_BOARD_CONF_H__ -#define __MINI2440_BOARD_CONF_H__ - -/* PLL Parameters */ -#define CLKDIVN_VAL 7 -#define M_MDIV 0x7f -#define M_PDIV 0x2 -#define M_SDIV 0x1 - -#define U_M_MDIV 0x38 -#define U_M_PDIV 0x2 -#define U_M_SDIV 0x2 - -/* BWSCON */ -#define DW8 0x0 -#define DW16 0x1 -#define DW32 0x2 -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW32) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* - * Bank Configuration - */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* 0clk */ -#define B0_PMC 0x0 /* normal */ - -#define B1_Tacs 0x0 -#define B1_Tcos 0x0 -#define B1_Tacc 0x7 -#define B1_Tcoh 0x0 -#define B1_Tah 0x0 -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0x0 -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x3 /* 4clk */ -#define B3_Tacp 0x0 -#define B3_PMC 0x0 - -#define B4_Tacs 0x0 -#define B4_Tcos 0x3 -#define B4_Tacc 0x7 -#define B4_Tcoh 0x1 -#define B4_Tah 0x3 -#define B4_Tacp 0x0 -#define B4_PMC 0x0 - -#define B5_Tacs 0x0 -#define B5_Tcos 0x0 -#define B5_Tacc 0x7 -#define B5_Tcoh 0x0 -#define B5_Tah 0x0 -#define B5_Tacp 0x0 -#define B5_PMC 0x0 - -/* - * SDRAM Configuration - */ -#define SDRAM_MT 0x3 /* SDRAM */ -#define SDRAM_Trcd 0x0 /* 2clk */ -#define SDRAM_SCAN_9 0x1 /* 9bit */ -#define SDRAM_SCAN_10 0x2 /* 10bit */ - -#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9)) - -/* - * Refresh Parameter - */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x1 /* 3clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x0 /* unused */ -#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */ - -/* - * MRSR Parameter - */ -#define BL 0x0 -#define BT 0x0 -#define CL 0x3 /* 3 clocks */ -#define TM 0x0 -#define WBL 0x0 - -/* - * BankSize Parameter - */ -#define BK76MAP 0x2 /* 128MB/128MB */ -#define SCLK_EN 0x1 /* SCLK active */ -#define SCKE_EN 0x1 /* SDRAM power down mode enable */ -#define BURST_EN 0x1 /* Burst enable */ - -/* - * Register values - */ -#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \ - (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \ - (B7_BWSCON<<28))) - -#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \ - (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)) -#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \ - (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)) -#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \ - (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)) -#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \ - (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)) -#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \ - (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)) -#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \ - (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)) - -#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \ - (Trc<<18) + (Tchr<<16) + REFCNT - -#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) -#define B6_MRSR (CL<<4) -#define B7_MRSR (CL<<4) - -#endif diff --git a/board/funkwerk/vovpn-gw/Makefile b/board/funkwerk/vovpn-gw/Makefile deleted file mode 100644 index 677a021170..0000000000 --- a/board/funkwerk/vovpn-gw/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o flash.o m88e6060.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/funkwerk/vovpn-gw/flash.c b/board/funkwerk/vovpn-gw/flash.c deleted file mode 100644 index 829514c179..0000000000 --- a/board/funkwerk/vovpn-gw/flash.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * ------------------------------------------ - * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3 - * and 28F128J3A flashs working in 8 Bit mode. - * - * Most of this code is taken from existing u-boot source code. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_READ_STATUS 0x70 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xd0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_SUSPEND_ERASE 0xb0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_WRITE_BUFF 0xe8 -#define FLASH_CMD_PROG_RESUME 0xd0 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xd0 -#define FLASH_STATUS_DONE 0x80 - -#define FLASH_WRITE_BUFFER_SIZE 32 - -#ifdef CONFIG_SYS_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xffff -#define FLASH_CMD_ADDR_SHIFT 0 -#else -#define FLASH_WORD_SIZE unsigned char -#define FLASH_ID_MASK 0xff -/* A0 is not used in either 8x or 16x for READ ID */ -#define FLASH_CMD_ADDR_SHIFT 1 -#endif - - -static unsigned long -flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - volatile FLASH_WORD_SIZE *p; - FLASH_WORD_SIZE value; - int i; - - addr[0] = FLASH_CMD_READ_ID; - - /* manufactor */ - value = addr[0 << FLASH_CMD_ADDR_SHIFT]; - switch (value) { - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - *addr = FLASH_CMD_RESET; - return (0); - - } - - /* device */ - value = addr[1 << FLASH_CMD_ADDR_SHIFT]; - switch (value) { - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - *addr = FLASH_CMD_RESET; - return (0); - } - - /* setup sectors */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count); - } - - /* check protected sectors */ - for (i = 0; i < info->sector_count; i++) { - p = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1; - } - - /* reset bank */ - *addr = FLASH_CMD_RESET; - return (info->size); -} - -unsigned long -flash_init(void) -{ - unsigned long size; - int i; - - for (i=0; i= CONFIG_SYS_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_FLASH, - CONFIG_SYS_MONITOR_FLASH+CONFIG_SYS_MONITOR_LEN-1, - &flash_info[0]); -#endif -#ifdef CONFIG_ENV_IS_IN_FLASH - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -void -flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320JA3 (32 Mbit)\n"); - break; - case FLASH_28F640J3A: printf ("28F640JA3 (64 Mbit)\n"); - break; - case FLASH_28F128J3A: printf ("28F128JA3 (128 Mbit)\n"); - break; - default: printf ("Unknown Chip Type"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - unsigned long start, now, last; - int flag, prot, sect; - volatile FLASH_WORD_SIZE *addr; - FLASH_WORD_SIZE status; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return (1); - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Cannot erase unknown flash - aborted\n"); - return (1); - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect]) { - continue; - } - - addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#ifdef DEBUG - printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]); -#endif - - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_BLOCK_ERASE; - *addr = FLASH_CMD_ERASE_CONFIRM; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Flash erase timeout at address %lx\n", info->start[sect]); - *addr = FLASH_CMD_SUSPEND_ERASE; - *addr = FLASH_CMD_RESET; - return (1); - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - *addr = FLASH_CMD_RESET; - } - printf (" done\n"); - return (0); -} - -static int -write_buff2( volatile FLASH_WORD_SIZE *dst, - volatile FLASH_WORD_SIZE *src, - unsigned long cnt ) -{ - unsigned long start; - FLASH_WORD_SIZE status; - int flag, i; - - start = get_timer (0); - while (1) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - dst[0] = FLASH_CMD_WRITE_BUFF; - if ((status = *dst) & FLASH_STATUS_DONE) { - break; - } - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (-1); - } - } - dst[0] = (FLASH_WORD_SIZE)(cnt - 1); - for (i=0; i CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = FLASH_CMD_RESET; - return (-1); - } - } - *addr = FLASH_CMD_RESET; - return (0); -} - -/* - * write_buff return values: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ -int -write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt) -{ - volatile FLASH_WORD_SIZE *addr, *dst; - unsigned long bcnt; - int flag, i; - - if (info->flash_id == FLASH_UNKNOWN) { - return (4); - } - - addr = (volatile FLASH_WORD_SIZE *)(info->start[0]); - dst = (volatile FLASH_WORD_SIZE *) udst; - -#ifdef CONFIG_SYS_FLASH_16BIT -#error NYI -#else - while (cnt > 0) { - /* Check if buffer write is possible */ - if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) { - bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt; - /* Check if Flash is (sufficiently) erased */ - for (i=0; istart[sector]); - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_PROTECT; - - if(prot) { - *addr = FLASH_CMD_PROTECT_SET; - } else { - *addr = FLASH_CMD_PROTECT_CLEAR; - } - - /* wait for error or finish */ - start = get_timer (0); - while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Flash protect timeout at address %lx\n", info->start[sector]); - addr[0] = FLASH_CMD_RESET; - return (1); - } - } - - /* Set software protect flag */ - info->protect[sector] = prot; - *addr = FLASH_CMD_RESET; - return (0); -} diff --git a/board/funkwerk/vovpn-gw/m88e6060.c b/board/funkwerk/vovpn-gw/m88e6060.c deleted file mode 100644 index 7aa9593426..0000000000 --- a/board/funkwerk/vovpn-gw/m88e6060.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * ------------------------------------------ - * Initialize Marvell M88E6060 Switch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#include "m88e6060.h" - -#if defined(CONFIG_CMD_NET) -static int prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 }; -static int phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 }; - -static m88x_regCfg_t prtCfg0[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x001e }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t prtCfg1[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x001d }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t prtCfg2[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x001b }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t prtCfg3[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x0017 }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t prtCfg4[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x000f }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t *prtCfg[M88X_PRT_CNT] = { - prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL -}; - -static m88x_regCfg_t phyCfgX[] = { - { 4, 0xfa1f, 0x01e0 }, - { 0, 0x213f, 0x1200 }, - { 24, 0x81ff, 0x1200 }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t *phyCfg[M88X_PHY_CNT] = { - phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL -}; - -#if 0 -static void -m88e6060_dump( int devAddr ) -{ - int i, j; - unsigned short val[6]; - - printf( "M88E6060 Register Dump\n" ); - printf( "====================================\n" ); - printf( "PortNo 0 1 2 3 4 5\n" ); - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] ); - printf( "STAT %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] ); - printf( "ID %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] ); - printf( "CNTL %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] ); - printf( "VLAN %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] ); - printf( "PAV %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] ); - printf( "RX %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] ); - printf( "TX %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - printf( "------------------------------------\n" ); - printf( "PhyNo 0 1 2 3 4\n" ); - for (i=0; i<9; i++) { - for (j=0; j<5; j++) { - miiphy_read( devAddr+phyTab[j],i,&val[j] ); - } - printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n", - i,val[0],val[1],val[2],val[3],val[4] ); - } - for (i=0x10; i<0x1d; i++) { - for (j=0; j<5; j++) { - miiphy_read( devAddr+phyTab[j],i,&val[j] ); - } - printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n", - i,val[0],val[1],val[2],val[3],val[4] ); - } -} -#endif - -int -m88e6060_initialize( int devAddr ) -{ - static char *_f = "m88e6060_initialize:"; - m88x_regCfg_t *p; - int err; - int i; - unsigned short val; - - /*** reset all phys into powerdown ************************************/ - for (i=0, err=0; ienetaddr - val = (ea[4] << 8) | ea[5]; - err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val ); - val = (ea[2] << 8) | ea[3]; - err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val ); - val = (ea[0] << 8) | ea[1]; -#undef ea - val &= 0xfeff; /* clear DiffAddr */ - err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val ); - if (err) { - printf( "%s [ERR] switch mac address register\n",_f ); - return( -1 ); - } - - /* !DiscardExcessive, MaxFrameSize, CtrMode */ - err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val ); - val &= 0xd870; - val |= 0x0500; - err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val ); - if (err) { - printf( "%s [ERR] switch global control register\n",_f ); - return( -1 ); - } - - /* LernDis off, ATUSize 1024, AgeTime 5min */ - err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val ); - val &= 0x000f; - val |= 0x2130; - err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val ); - if (err) { - printf( "%s [ERR] atu control register\n",_f ); - return( -1 ); - } - - /*** initialize ports *************************************************/ - for (i=0; ireg != -1) { - err = 0; - err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val ); - val &= p->msk; - val |= p->val; - err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val ); - if (err) { - printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg ); - /* XXX what todo */ - } - p++; - } - } - - /*** initialize phys **************************************************/ - for (i=0; ireg != -1) { - err = 0; - err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val ); - val &= p->msk; - val |= p->val; - err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val ); - if (err) { - printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg ); - /* XXX what todo */ - } - p++; - } - } - udelay(100000); - return( 0 ); -} -#endif diff --git a/board/funkwerk/vovpn-gw/m88e6060.h b/board/funkwerk/vovpn-gw/m88e6060.h deleted file mode 100644 index 5f7f6d11af..0000000000 --- a/board/funkwerk/vovpn-gw/m88e6060.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * ------------------------------------------ - * Initialize Marvell M88E6060 Switch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _INC_m88e6060_h_ -#define _INC_m88e6060_h_ - -/* ************************************************************************** */ -/* *** DEFINES ************************************************************** */ - -/* switch hw */ -#define M88X_PRT_CNT 6 -#define M88X_PHY_CNT 5 - -/* phy register offsets */ -#define M88X_PHY_CNTL 0x00 -#define M88X_PHY_STAT 0x00 -#define M88X_PHY_ID0 0x02 -#define M88X_PHY_ID1 0x03 -#define M88X_PHY_ANEG_ADV 0x04 -#define M88X_PHY_LPA 0x05 -#define M88X_PHY_ANEG_EXP 0x06 -#define M88X_PHY_NPT 0x07 -#define M88X_PHY_LPNP 0x08 - -/* port register offsets */ -#define M88X_PRT_STAT 0x00 -#define M88X_PRT_ID 0x03 -#define M88X_PRT_CNTL 0x04 -#define M88X_PRT_VLAN 0x06 -#define M88X_PRT_PAV 0x0b -#define M88X_PRT_RX 0x10 -#define M88X_PRT_TX 0x11 - -/* global/atu register offsets */ -#define M88X_GLB_STAT 0x00 -#define M88X_GLB_MAC01 0x01 -#define M88X_GLB_MAC23 0x02 -#define M88X_GLB_MAC45 0x03 -#define M88X_GLB_CNTL 0x04 -#define M88X_ATU_CNTL 0x0a -#define M88X_ATU_OP 0x0b - -/* id0 register - 0x02 */ -#define M88X_PHY_ID0_VALUE 0x0141 - -/* id1 register - 0x03 */ -#define M88X_PHY_ID1_VALUE 0x0c80 /* without revision ! */ - - -/* misc */ -#define M88E6060_ID ((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE) - -/* ************************************************************************** */ -/* *** TYPEDEFS ************************************************************* */ - -typedef struct { - int reg; - unsigned short msk; - unsigned short val; -} m88x_regCfg_t; - -/* ************************************************************************** */ -/* *** PROTOTYPES *********************************************************** */ - -extern int m88e6060_initialize( int ); - -#endif /* _INC_m88e6060_h_ */ diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c deleted file mode 100644 index d33563b8d8..0000000000 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#include "m88e6060.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */ - /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */ - /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */ - /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */ - /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */ - /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */ - /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */ - /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */ - /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */ - /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */ - /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */ - /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */ - /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */ - /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */ - /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */ - /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */ - /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */ - /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */ - /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */ - /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */ - /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */ - /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */ - /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */ - /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */ - /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */ - /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */ - /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */ - /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */ - /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */ - /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */ - /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */ - /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */ - /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */ - /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */ - /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */ - /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */ - /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */ - /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ - /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */ - /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */ - /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */ - /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */ - /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */ - /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ - } -}; - -void reset_phy (void) -{ - volatile ioport_t *iop; -#if defined(CONFIG_CMD_NET) - int i; - unsigned short val; -#endif - - iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0); - - /* Reset the PHY */ - iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */ -#if defined(CONFIG_CMD_NET) - udelay(20000); - iop->pdat |= 0x00080000; - for (i=0; i<100; i++) { - udelay(20000); - if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) { - break; - } - } - /* initialize switch */ - m88e6060_initialize( CONFIG_SYS_PHY_ADDR ); -#endif -} - -static unsigned long UPMATable[] = { - 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ - 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */ - 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ - 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ - 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ - 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ - 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */ -}; - -int board_early_init_f (void) -{ - volatile immap_t *immap; - volatile memctl8260_t *memctl; - volatile unsigned char *dummy; - int i; - - immap = (immap_t *) CONFIG_SYS_IMMR; - memctl = &immap->im_memctl; - -#if 0 - /* CS2-5 - DSP via UPMA */ - dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK); - memctl->memc_mar = 0; - memctl->memc_mamr = MxMR_OP_WARR; - for (i = 0; i < 64; i++) { - memctl->memc_mdr = UPMATable[i]; - *dummy = 0; - } - memctl->memc_mamr = 0x00044440; -#else - /* CS7 - DPRAM via UPMA */ - dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); - memctl->memc_mar = 0; - memctl->memc_mamr = MxMR_OP_WARR; - for (i = 0; i < 64; i++) { - memctl->memc_mdr = UPMATable[i]; - *dummy = 0; - } - memctl->memc_mamr = 0x00044440; -#endif - return 0; -} - -int misc_init_r (void) -{ - volatile ioport_t *iop; - __maybe_unused unsigned char temp; -#if 0 - /* DUMP UPMA RAM */ - volatile immap_t *immap; - volatile memctl8260_t *memctl; - volatile unsigned char *dummy; - unsigned char c; - int i; - - immap = (immap_t *) CONFIG_SYS_IMMR; - memctl = &immap->im_memctl; - - - dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); - memctl->memc_mar = 0; - memctl->memc_mamr = MxMR_OP_RARR; - for (i = 0; i < 64; i++) { - c = *dummy; - printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i, - memctl->memc_mamr, - memctl->memc_mar, - memctl->memc_mdr ); - } - memctl->memc_mamr = 0x00044440; -#endif - /* enable buffers (DSP, DPRAM) */ - iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0); - iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */ - - /* destroy DPRAM magic */ - *(volatile unsigned char *)0xf0500000 = 0x00; - - /* clear any pending DPRAM irq */ - temp = *(volatile unsigned char *)0xf05003ff; - - /* write module-id into DPRAM */ - *(volatile unsigned char *)0xf0500201 = 0x50; - - return 0; -} - -#if defined(CONFIG_HAVE_OWN_RESET) -int -do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile ioport_t *iop; - - iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2); - iop->pdat |= 0x00002000; /* PC18 = HW_RESET */ - return 1; -} -#endif /* CONFIG_HAVE_OWN_RESET */ - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) - -phys_size_t initdram (int board_type) -{ -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *immap; - volatile memctl8260_t *memctl; - volatile uchar *ramaddr; - int i; - uchar c; - - immap = (immap_t *) CONFIG_SYS_IMMR; - memctl = &immap->im_memctl; - ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE; - c = 0xff; - - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef; - immap->im_siu_conf.sc_tescr1 = 0x00000000; - immap->im_siu_conf.sc_tescr2 = 0x00000000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM; - - /* Precharge all banks */ - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000; - *ramaddr = c; - - /* CBR refresh */ - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *ramaddr = c; - - /* Mode Register write */ - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000; - *ramaddr = c; - - /* Refresh enable */ - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000; - *ramaddr = c; -#endif /* CONFIG_SYS_RAMBOOT */ - - return (CONFIG_SYS_SDRAM_SIZE); -} - -int checkboard (void) -{ -#ifdef CONFIG_CLKIN_66MHz - puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n"); -#else - puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n"); -#endif - return 0; -} diff --git a/board/g2000/Makefile b/board/g2000/Makefile deleted file mode 100644 index 0d202ac071..0000000000 --- a/board/g2000/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o strataflash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c deleted file mode 100644 index a64f946ab4..0000000000 --- a/board/g2000/g2000.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define MEM_MCOPT1_INIT_VAL 0x00800000 -#define MEM_RTR_INIT_VAL 0x04070000 -#define MEM_PMIT_INIT_VAL 0x07c00000 -#define MEM_MB0CF_INIT_VAL 0x00082001 -#define MEM_MB1CF_INIT_VAL 0x04082000 -#define MEM_SDTR1_INIT_VAL 0x00854005 -#define SDRAM0_CFG_ENABLE 0x80000000 - -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ - -int board_early_init_f (void) -{ -#if 0 /* test-only */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000010); - mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */ - mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ -#else - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ -#endif - -#if 1 /* test-only */ - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ -#endif - - return 0; -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ -#if defined(CONFIG_CMD_NAND) - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE); -#endif - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming G2000"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - - -/* ------------------------------------------------------------------------- - G2000 rev B is an embeded design. we don't read for spd of this version. - Doing static SDRAM controller configuration in the following section. - ------------------------------------------------------------------------- */ - -long int init_sdram_static_settings(void) -{ - /* disable memcontroller so updates work */ - mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL); - mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL); - mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL); - mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL); - mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL); - mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL); - - /* SDRAM have a power on delay, 500 micro should do */ - udelay(500); - mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE); - - return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ - } - - -phys_size_t initdram (int board_type) -{ - long int ret; - -/* flzt, we can still turn this on in the future */ -/* #ifdef CONFIG_SPD_EEPROM - ret = spd_sdram (); -#else - ret = init_sdram_static_settings(); -#endif -*/ - - ret = init_sdram_static_settings(); - - return ret; -} - -#if 0 /* test-only !!! */ -int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong ap, cr; - - printf("\nEBC registers for PPC405GP:\n"); - mfebc(PB0AP, ap); mfebc(PB0CR, cr); - printf("0: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(PB1AP, ap); mfebc(PB1CR, cr); - printf("1: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(PB2AP, ap); mfebc(PB2CR, cr); - printf("2: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(PB3AP, ap); mfebc(PB3CR, cr); - printf("3: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(PB4AP, ap); mfebc(PB4CR, cr); - printf("4: AP=%08lx CP=%08lx\n", ap, cr); - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpebc, 1, 1, do_dumpebc, - "Dump all EBC registers", - "" -); - - -int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - - printf("\nDevice Configuration Registers (DCR's) for PPC405GP:"); - for (i=0; i<=0x1e0; i++) { - if (!(i % 0x8)) { - printf("\n%04x ", i); - } - printf("%08lx ", get_dcr(i)); - } - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpdcr, 1, 1, do_dumpdcr, - "Dump all DCR registers", - "" -); - - -int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:"); - printf("\n%04x %08x ", 947, mfspr(947)); - printf("\n%04x %08x ", 9, mfspr(9)); - printf("\n%04x %08x ", 1014, mfspr(1014)); - printf("\n%04x %08x ", 1015, mfspr(1015)); - printf("\n%04x %08x ", 1010, mfspr(1010)); - printf("\n%04x %08x ", 957, mfspr(957)); - printf("\n%04x %08x ", 1008, mfspr(1008)); - printf("\n%04x %08x ", 1018, mfspr(1018)); - printf("\n%04x %08x ", 954, mfspr(954)); - printf("\n%04x %08x ", 950, mfspr(950)); - printf("\n%04x %08x ", 951, mfspr(951)); - printf("\n%04x %08x ", 981, mfspr(981)); - printf("\n%04x %08x ", 980, mfspr(980)); - printf("\n%04x %08x ", 982, mfspr(982)); - printf("\n%04x %08x ", 1012, mfspr(1012)); - printf("\n%04x %08x ", 1013, mfspr(1013)); - printf("\n%04x %08x ", 948, mfspr(948)); - printf("\n%04x %08x ", 949, mfspr(949)); - printf("\n%04x %08x ", 1019, mfspr(1019)); - printf("\n%04x %08x ", 979, mfspr(979)); - printf("\n%04x %08x ", 8, mfspr(8)); - printf("\n%04x %08x ", 945, mfspr(945)); - printf("\n%04x %08x ", 987, mfspr(987)); - printf("\n%04x %08x ", 287, mfspr(287)); - printf("\n%04x %08x ", 953, mfspr(953)); - printf("\n%04x %08x ", 955, mfspr(955)); - printf("\n%04x %08x ", 272, mfspr(272)); - printf("\n%04x %08x ", 273, mfspr(273)); - printf("\n%04x %08x ", 274, mfspr(274)); - printf("\n%04x %08x ", 275, mfspr(275)); - printf("\n%04x %08x ", 260, mfspr(260)); - printf("\n%04x %08x ", 276, mfspr(276)); - printf("\n%04x %08x ", 261, mfspr(261)); - printf("\n%04x %08x ", 277, mfspr(277)); - printf("\n%04x %08x ", 262, mfspr(262)); - printf("\n%04x %08x ", 278, mfspr(278)); - printf("\n%04x %08x ", 263, mfspr(263)); - printf("\n%04x %08x ", 279, mfspr(279)); - printf("\n%04x %08x ", 26, mfspr(26)); - printf("\n%04x %08x ", 27, mfspr(27)); - printf("\n%04x %08x ", 990, mfspr(990)); - printf("\n%04x %08x ", 991, mfspr(991)); - printf("\n%04x %08x ", 956, mfspr(956)); - printf("\n%04x %08x ", 284, mfspr(284)); - printf("\n%04x %08x ", 285, mfspr(285)); - printf("\n%04x %08x ", 986, mfspr(986)); - printf("\n%04x %08x ", 984, mfspr(984)); - printf("\n%04x %08x ", 256, mfspr(256)); - printf("\n%04x %08x ", 1, mfspr(1)); - printf("\n%04x %08x ", 944, mfspr(944)); - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpspr, 1, 1, do_dumpspr, - "Dump all SPR registers", - "" -); -#endif diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c deleted file mode 100644 index 93e2432ebf..0000000000 --- a/board/g2000/strataflash.c +++ /dev/null @@ -1,774 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CONFIG_SYS_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CONFIG_SYS_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;iportwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; iportwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; isector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t cptr; - int flag; - - cptr.cp = (uchar *)dest; - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - if (len & 0x1) { /* test-only: unaligned size */ - puts("\nUnalgined size!!!\n"); /* test-only */ - cnt++; - } - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/gaisler/gr_cpci_ax2000/Kconfig b/board/gaisler/gr_cpci_ax2000/Kconfig new file mode 100644 index 0000000000..c12a002179 --- /dev/null +++ b/board/gaisler/gr_cpci_ax2000/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GR_CPCI_AX2000 + +config SYS_BOARD + default "gr_cpci_ax2000" + +config SYS_CONFIG_NAME + default "gr_cpci_ax2000" + +endif diff --git a/board/gaisler/gr_cpci_ax2000/MAINTAINERS b/board/gaisler/gr_cpci_ax2000/MAINTAINERS new file mode 100644 index 0000000000..df55a4cc41 --- /dev/null +++ b/board/gaisler/gr_cpci_ax2000/MAINTAINERS @@ -0,0 +1,6 @@ +GR_CPCI_AX2000 BOARD +#M: - +S: Maintained +F: board/gaisler/gr_cpci_ax2000/ +F: include/configs/gr_cpci_ax2000.h +F: configs/gr_cpci_ax2000_defconfig diff --git a/board/gaisler/gr_cpci_ax2000/Makefile b/board/gaisler/gr_cpci_ax2000/Makefile index baa067d9df..a08e04dbe8 100644 --- a/board/gaisler/gr_cpci_ax2000/Makefile +++ b/board/gaisler/gr_cpci_ax2000/Makefile @@ -1,4 +1,3 @@ - # # (C) Copyright 2003-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -6,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -#flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := gr_cpci_ax2000.o diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk deleted file mode 100644 index e9c60286ce..0000000000 --- a/board/gaisler/gr_cpci_ax2000/config.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# (C) Copyright 2008 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# GR-CPCI-AX2000 board -# - -# U-BOOT IN FLASH -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# U-BOOT IN RAM or SDRAM with -nosram flag set when starting GRMON -#CONFIG_SYS_TEXT_BASE = 0x40000000 - -# U-BOOT IN SDRAM -#CONFIG_SYS_TEXT_BASE = 0x60000000 - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds deleted file mode 100644 index 6d9c90cd71..0000000000 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Linker script for Gaisler Research AB's GR-CPCI-AX2000 board - * with template design. - * - * (C) Copyright 2008 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") -OUTPUT_ARCH(sparc) -ENTRY(_start) -SECTIONS -{ - -/* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - - .text : { - _load_addr = .; - _text = .; - - *(.start) - arch/sparc/cpu/leon3/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ - . = ALIGN(8192); -/* PROM CODE, Will be relocated to the end of memory, - * no global data accesses please. - */ - __prom_start = .; - *(.prom.pgt) - *(.prom.data) - *(.prom.text) - . = ALIGN(16); - __prom_end = .; - *(.text) - *(.fixup) - *(.gnu.warning) -/* *(.got1)*/ - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - _etext = .; - - /* CMD Table */ - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - .data : - { - *(.data) - *(.data1) - *(.data.rel) - *(.data.rel.*) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = ALIGN(4); - __got_start = .; - .got : { - *(.got) -/* *(.data.rel) - *(.data.rel.local)*/ - . = ALIGN(16); - } - __got_end = .; - -/* .data.rel : { } */ - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(16); /* to speed clearing of bss up */ - } - __bss_end = . ; - __bss_end = . ; - PROVIDE (end = .); - -/* Relocated into main memory */ - - /* Start of main memory */ - /*. = 0x40000000;*/ - - .stack (NOLOAD) : { *(.stack) } - - /* PROM CODE */ - - /* global data in RAM passed to kernel after booting */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - -} diff --git a/board/gaisler/gr_ep2s60/Kconfig b/board/gaisler/gr_ep2s60/Kconfig new file mode 100644 index 0000000000..f49937c55a --- /dev/null +++ b/board/gaisler/gr_ep2s60/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GR_EP2S60 + +config SYS_BOARD + default "gr_ep2s60" + +config SYS_CONFIG_NAME + default "gr_ep2s60" + +endif diff --git a/board/gaisler/gr_ep2s60/MAINTAINERS b/board/gaisler/gr_ep2s60/MAINTAINERS new file mode 100644 index 0000000000..7acd5f44c6 --- /dev/null +++ b/board/gaisler/gr_ep2s60/MAINTAINERS @@ -0,0 +1,6 @@ +GR_EP2S60 BOARD +#M: - +S: Maintained +F: board/gaisler/gr_ep2s60/ +F: include/configs/gr_ep2s60.h +F: configs/gr_ep2s60_defconfig diff --git a/board/gaisler/gr_ep2s60/Makefile b/board/gaisler/gr_ep2s60/Makefile index baa067d9df..059a9c03c4 100644 --- a/board/gaisler/gr_ep2s60/Makefile +++ b/board/gaisler/gr_ep2s60/Makefile @@ -1,4 +1,3 @@ - # # (C) Copyright 2003-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -6,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -#flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := gr_ep2s60.o diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk deleted file mode 100644 index 6c31a17f8c..0000000000 --- a/board/gaisler/gr_ep2s60/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2008 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# Altera NIOS delopment board Stratix II edition, FPGA device EP2S60, -# with GRLIB Template design (GPL Open Source SPARC/LEON3) -# - -# U-BOOT IN FLASH -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# U-BOOT IN SDRAM -#CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds deleted file mode 100644 index 973603c7cc..0000000000 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Linker script for Gaisler Research AB's Template design - * for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA. - * - * (C) Copyright 2008 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") -OUTPUT_ARCH(sparc) -ENTRY(_start) -SECTIONS -{ - -/* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - - .text : { - _load_addr = .; - _text = .; - - *(.start) - arch/sparc/cpu/leon3/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ - . = ALIGN(8192); -/* PROM CODE, Will be relocated to the end of memory, - * no global data accesses please. - */ - __prom_start = .; - *(.prom.pgt) - *(.prom.data) - *(.prom.text) - . = ALIGN(16); - __prom_end = .; - *(.text) - *(.fixup) - *(.gnu.warning) -/* *(.got1)*/ - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - _etext = .; - - /* CMD Table */ - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - .data : - { - *(.data) - *(.data1) - *(.data.rel) - *(.data.rel.*) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = ALIGN(4); - __got_start = .; - .got : { - *(.got) -/* *(.data.rel) - *(.data.rel.local)*/ - . = ALIGN(16); - } - __got_end = .; - -/* .data.rel : { } */ - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(16); /* to speed clearing of bss up */ - } - __bss_end = . ; - __bss_end = . ; - PROVIDE (end = .); - -/* Relocated into main memory */ - - /* Start of main memory */ - /*. = 0x40000000;*/ - - .stack (NOLOAD) : { *(.stack) } - - /* PROM CODE */ - - /* global data in RAM passed to kernel after booting */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - -} diff --git a/board/gaisler/gr_xc3s_1500/Kconfig b/board/gaisler/gr_xc3s_1500/Kconfig new file mode 100644 index 0000000000..e695ba2cdd --- /dev/null +++ b/board/gaisler/gr_xc3s_1500/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GR_XC3S_1500 + +config SYS_BOARD + default "gr_xc3s_1500" + +config SYS_CONFIG_NAME + default "gr_xc3s_1500" + +endif diff --git a/board/gaisler/gr_xc3s_1500/MAINTAINERS b/board/gaisler/gr_xc3s_1500/MAINTAINERS new file mode 100644 index 0000000000..c4179d29c0 --- /dev/null +++ b/board/gaisler/gr_xc3s_1500/MAINTAINERS @@ -0,0 +1,6 @@ +GR_XC3S_1500 BOARD +#M: - +S: Maintained +F: board/gaisler/gr_xc3s_1500/ +F: include/configs/gr_xc3s_1500.h +F: configs/gr_xc3s_1500_defconfig diff --git a/board/gaisler/gr_xc3s_1500/Makefile b/board/gaisler/gr_xc3s_1500/Makefile index baa067d9df..302c4611e0 100644 --- a/board/gaisler/gr_xc3s_1500/Makefile +++ b/board/gaisler/gr_xc3s_1500/Makefile @@ -1,4 +1,3 @@ - # # (C) Copyright 2003-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -6,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -#flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := gr_xc3s_1500.o diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk deleted file mode 100644 index 3b59cca5e6..0000000000 --- a/board/gaisler/gr_xc3s_1500/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2007 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# GR-XC3S-1500 board -# - -# U-BOOT IN FLASH -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# U-BOOT IN RAM -#CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds deleted file mode 100644 index 1ed71f2659..0000000000 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Linker script for Gaisler Research AB's GR-XC3S-1500 board - * with template design. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") -OUTPUT_ARCH(sparc) -ENTRY(_start) -SECTIONS -{ - -/* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - - .text : { - _load_addr = .; - _text = .; - - *(.start) - arch/sparc/cpu/leon3/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ - . = ALIGN(8192); -/* PROM CODE, Will be relocated to the end of memory, - * no global data accesses please. - */ - __prom_start = .; - *(.prom.pgt) - *(.prom.data) - *(.prom.text) - . = ALIGN(16); - __prom_end = .; - *(.text) - *(.fixup) - *(.gnu.warning) -/* *(.got1)*/ - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - _etext = .; - - /* CMD Table */ - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - .data : - { - *(.data) - *(.data1) - *(.data.rel) - *(.data.rel.*) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = ALIGN(4); - __got_start = .; - .got : { - *(.got) -/* *(.data.rel) - *(.data.rel.local)*/ - . = ALIGN(16); - } - __got_end = .; - -/* .data.rel : { } */ - - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(16); /* to speed clearing of bss up */ - } - __bss_end = . ; - __bss_end = . ; - PROVIDE (end = .); - -/* Relocated into main memory */ - - /* Start of main memory */ - /*. = 0x40000000;*/ - - .stack (NOLOAD) : { *(.stack) } - - /* PROM CODE */ - - /* global data in RAM passed to kernel after booting */ - - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - -} diff --git a/board/gaisler/grsim/Kconfig b/board/gaisler/grsim/Kconfig new file mode 100644 index 0000000000..18598d3c2a --- /dev/null +++ b/board/gaisler/grsim/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GRSIM + +config SYS_BOARD + default "grsim" + +config SYS_CONFIG_NAME + default "grsim" + +endif diff --git a/board/gaisler/grsim/MAINTAINERS b/board/gaisler/grsim/MAINTAINERS new file mode 100644 index 0000000000..4b3312ef72 --- /dev/null +++ b/board/gaisler/grsim/MAINTAINERS @@ -0,0 +1,6 @@ +GRSIM BOARD +#M: - +S: Maintained +F: board/gaisler/grsim/ +F: include/configs/grsim.h +F: configs/grsim_defconfig diff --git a/board/gaisler/grsim/Makefile b/board/gaisler/grsim/Makefile index 2c0119e9c4..4c93bdae83 100644 --- a/board/gaisler/grsim/Makefile +++ b/board/gaisler/grsim/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := grsim.o diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk deleted file mode 100644 index d98ed54c07..0000000000 --- a/board/gaisler/grsim/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2007 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# GRSIM simulating a LEON3 GR-XC3S-1500 board -# - -# U-BOOT IN FLASH -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# U-BOOT IN RAM -#CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds deleted file mode 100644 index cdc83941ed..0000000000 --- a/board/gaisler/grsim/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Linker script for Gaisler Research AB's GRSIM LEON3 simulator. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") -OUTPUT_ARCH(sparc) -ENTRY(_start) -SECTIONS -{ - -/* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - - .text : { - _load_addr = .; - _text = .; - - *(.start) - arch/sparc/cpu/leon3/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ - . = ALIGN(8192); -/* PROM CODE, Will be relocated to the end of memory, - * no global data accesses please. - */ - __prom_start = .; - *(.prom.pgt) - *(.prom.data) - *(.prom.text) - . = ALIGN(16); - __prom_end = .; - *(.text) - *(.fixup) - *(.gnu.warning) -/* *(.got1)*/ - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - _etext = .; - - /* CMD Table */ - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - .data : - { - *(.data) - *(.data1) - *(.data.rel) - *(.data.rel.*) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = ALIGN(4); - __got_start = .; - .got : { - *(.got) -/* *(.data.rel) - *(.data.rel.local)*/ - . = ALIGN(16); - } - __got_end = .; - -/* .data.rel : { } */ - - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(16); /* to speed clearing of bss up */ - } - __bss_end = . ; - __bss_end = . ; - PROVIDE (end = .); - -/* Relocated into main memory */ - - /* Start of main memory */ - /*. = 0x40000000;*/ - - .stack (NOLOAD) : { *(.stack) } - - /* PROM CODE */ - - /* global data in RAM passed to kernel after booting */ - - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - -} diff --git a/board/gaisler/grsim_leon2/Kconfig b/board/gaisler/grsim_leon2/Kconfig new file mode 100644 index 0000000000..0d21a0a985 --- /dev/null +++ b/board/gaisler/grsim_leon2/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GRSIM_LEON2 + +config SYS_BOARD + default "grsim_leon2" + +config SYS_CONFIG_NAME + default "grsim_leon2" + +endif diff --git a/board/gaisler/grsim_leon2/MAINTAINERS b/board/gaisler/grsim_leon2/MAINTAINERS new file mode 100644 index 0000000000..bf4a95001b --- /dev/null +++ b/board/gaisler/grsim_leon2/MAINTAINERS @@ -0,0 +1,6 @@ +GRSIM_LEON2 BOARD +#M: - +S: Maintained +F: board/gaisler/grsim_leon2/ +F: include/configs/grsim_leon2.h +F: configs/grsim_leon2_defconfig diff --git a/board/gaisler/grsim_leon2/Makefile b/board/gaisler/grsim_leon2/Makefile index 2c0119e9c4..5468305caa 100644 --- a/board/gaisler/grsim_leon2/Makefile +++ b/board/gaisler/grsim_leon2/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := grsim_leon2.o diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk deleted file mode 100644 index 59e4e31690..0000000000 --- a/board/gaisler/grsim_leon2/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2007 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# GRSIM simulating a LEON2 board -# - -# RUN U-BOOT FROM PROM -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# RUN U-BOOT FROM RAM -#CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds deleted file mode 100644 index 1f038bca47..0000000000 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Linker script for Gaisler Research AB's GRSIM LEON2 simulator. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") -OUTPUT_ARCH(sparc) -ENTRY(_start) -SECTIONS -{ - -/* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - - .text : { - _load_addr = .; - _text = .; - - *(.start) - arch/sparc/cpu/leon2/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ - . = ALIGN(8192); -/* PROM CODE, Will be relocated to the end of memory, - * no global data accesses please. - */ - __prom_start = .; - *(.prom.pgt) - *(.prom.data) - *(.prom.text) - . = ALIGN(16); - __prom_end = .; - *(.text) - *(.fixup) - *(.gnu.warning) -/* *(.got1)*/ - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - _etext = .; - - /* CMD Table */ - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - .data : - { - *(.data) - *(.data1) - *(.data.rel) - *(.data.rel.*) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = ALIGN(4); - __got_start = .; - .got : { - *(.got) -/* *(.data.rel) - *(.data.rel.local)*/ - . = ALIGN(16); - } - __got_end = .; - -/* .data.rel : { } */ - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(16); /* to speed clearing of bss up */ - } - __bss_end = . ; - __bss_end = . ; - PROVIDE (end = .); - -/* Relocated into main memory */ - - /* Start of main memory */ - /*. = 0x40000000;*/ - - .stack (NOLOAD) : { *(.stack) } - - /* PROM CODE */ - - /* global data in RAM passed to kernel after booting */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - -} diff --git a/board/galaxy5200/Kconfig b/board/galaxy5200/Kconfig new file mode 100644 index 0000000000..31035811e9 --- /dev/null +++ b/board/galaxy5200/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GALAXY5200 + +config SYS_BOARD + default "galaxy5200" + +config SYS_CONFIG_NAME + default "galaxy5200" + +endif diff --git a/board/galaxy5200/MAINTAINERS b/board/galaxy5200/MAINTAINERS new file mode 100644 index 0000000000..614625d33f --- /dev/null +++ b/board/galaxy5200/MAINTAINERS @@ -0,0 +1,7 @@ +GALAXY5200 BOARD +#M: Eric Millbrandt +S: Orphan (since 2014-06) +F: board/galaxy5200/ +F: include/configs/galaxy5200.h +F: configs/galaxy5200_defconfig +F: configs/galaxy5200_LOWBOOT_defconfig diff --git a/board/galaxy5200/Makefile b/board/galaxy5200/Makefile index 4a7d872afa..e0fcd39515 100644 --- a/board/galaxy5200/Makefile +++ b/board/galaxy5200/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := galaxy5200.o diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c index 29e40eb58a..5d957b7e70 100644 --- a/board/galaxy5200/galaxy5200.c +++ b/board/galaxy5200/galaxy5200.c @@ -146,9 +146,11 @@ int checkboard(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t * bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig new file mode 100644 index 0000000000..c233e90c65 --- /dev/null +++ b/board/gateworks/gw_ventana/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GW_VENTANA + +config SYS_BOARD + default "gw_ventana" + +config SYS_VENDOR + default "gateworks" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "gw_ventana" + +endif diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS new file mode 100644 index 0000000000..b44fb4dc4b --- /dev/null +++ b/board/gateworks/gw_ventana/MAINTAINERS @@ -0,0 +1,6 @@ +GW_VENTANA BOARD +M: Tim Harvey +S: Maintained +F: board/gateworks/gw_ventana/ +F: include/configs/gw_ventana.h +F: configs/gwventana_defconfig diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile new file mode 100644 index 0000000000..33a1788f20 --- /dev/null +++ b/board/gateworks/gw_ventana/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Gateworks Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := gw_ventana.o gsc.o eeprom.o +obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o + diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README new file mode 100644 index 0000000000..888657cb0c --- /dev/null +++ b/board/gateworks/gw_ventana/README @@ -0,0 +1,83 @@ +U-Boot for the Gateworks Ventana Product Family boards + +This file contains information for the port of U-Boot to the Gateworks +Ventana Product family boards. + +1. Secondary Program Loader (SPL) +--------------------------------- + +The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading +an executable image from various boot devices. + +The Gateworks Ventana board config uses an SPL build configuration. This +will build the following artifacts from u-boot source: + - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program + Loader) boots. This detects CPU/DRAM configuration, configures + The DRAM controller, loads u-boot.img from the detected boot device, + and jumps to it. As this is booted from the PPL, it has an IVT/DCD + table. + - u-boot.img - The main u-boot core which is u-boot.bin with a image header. + + +2. Build +-------- + +To build U-Boot for the Gateworks Ventana product family: + + make gwventana_config + make + + +3. Boot source, boot from NAND +------------------------------ + +The i.MX6 BOOT ROM expects some structures that provide details of NAND layout +and bad block information (referred to as 'bootstreams') which are replicated +multiple times in NAND. The number of replications and their spacing (referred +to as search stride) is configurable through board strapping options and/or +eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In +addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two +copies of a bootloader in flash in the case that a bad block has corrupted one. +The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs +under Linux and operates on an MTD partition, must be used to program the +bootstream in order to setup this flash structure correctly. + +The Gateworks Ventana boards with NAND flash have been factory programmed +such that their eFUSE settings expect 2 copies of the boostream (this is +specified by providing kobs-ng with the --search_exponent=1 argument). Once in +Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL +with: + +kobs-ng init -v -x --search_exponent=1 SPL + +The kobs-ng application uses an imximage which contains the Image Vector Table +(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM +requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and +Discovered Bad Block Table (DBBT). The SPL build artifact from u-boot is +an imximage. + +The u-boot.img, which is the non SPL u-boot binary appended to a u-boot image +header must be programmed in the NAND flash boot device at an offset hard +coded in the SPL. For the Ventana boards, this has been chosen to be 14MB. +The image can be programmed from either u-boot or Linux: + +u-boot: +Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs) +Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \ + nand write ${loadaddr} uboot ${filesize} + +Linux: +nandwrite /dev/mtd1 u-boot.img + +The above assumes the default Ventana partitioning scheme which is configured +via the mtdparts env var: + - spl: 14MB + - uboot: 2M + - env: 1M + - rootfs: the rest + +This information is taken from: + http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH + +More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. + diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c new file mode 100644 index 0000000000..ab3bab847a --- /dev/null +++ b/board/gateworks/gw_ventana/eeprom.c @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include "gsc.h" +#include "ventana_eeprom.h" + +/* read ventana EEPROM, check for validity, and return baseboard type */ +int +read_eeprom(int bus, struct ventana_board_info *info) +{ + int i; + int chksum; + char baseboard; + int type; + unsigned char *buf = (unsigned char *)info; + + memset(info, 0, sizeof(*info)); + + /* + * On a board with a missing/depleted backup battery for GSC, the + * board may be ready to probe the GSC before its firmware is + * running. We will wait here indefinately for the GSC/EEPROM. + */ + while (1) { + if (0 == i2c_set_bus_num(bus) && + 0 == i2c_probe(GSC_EEPROM_ADDR)) + break; + mdelay(1); + } + + /* read eeprom config section */ + if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) { + puts("EEPROM: Failed to read EEPROM\n"); + return GW_UNKNOWN; + } + + /* sanity checks */ + if (info->model[0] != 'G' || info->model[1] != 'W') { + puts("EEPROM: Invalid Model in EEPROM\n"); + return GW_UNKNOWN; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) + chksum += buf[i]; + if ((info->chksum[0] != chksum>>8) || + (info->chksum[1] != (chksum&0xff))) { + puts("EEPROM: Failed EEPROM checksum\n"); + return GW_UNKNOWN; + } + + /* original GW5400-A prototype */ + baseboard = info->model[3]; + if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0) + baseboard = '0'; + + switch (baseboard) { + case '0': /* original GW5400-A prototype */ + type = GW54proto; + break; + case '1': + type = GW51xx; + break; + case '2': + type = GW52xx; + break; + case '3': + type = GW53xx; + break; + case '4': + type = GW54xx; + break; + case '5': + type = GW552x; + break; + default: + printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); + type = GW_UNKNOWN; + break; + } + return type; +} + +/* list of config bits that the bootloader will remove from dtb if not set */ +struct ventana_eeprom_config econfig[] = { + { "eth0", "ethernet0", EECONFIG_ETH0 }, + { "eth1", "ethernet1", EECONFIG_ETH1 }, + { "sata", "ahci0", EECONFIG_SATA }, + { "pcie", NULL, EECONFIG_PCIE}, + { "lvds0", NULL, EECONFIG_LVDS0 }, + { "lvds1", NULL, EECONFIG_LVDS1 }, + { "usb0", NULL, EECONFIG_USB0 }, + { "usb1", NULL, EECONFIG_USB1 }, + { "mmc0", NULL, EECONFIG_SD0 }, + { "mmc1", NULL, EECONFIG_SD1 }, + { "mmc2", NULL, EECONFIG_SD2 }, + { "mmc3", NULL, EECONFIG_SD3 }, + { "uart0", NULL, EECONFIG_UART0 }, + { "uart1", NULL, EECONFIG_UART1 }, + { "uart2", NULL, EECONFIG_UART2 }, + { "uart3", NULL, EECONFIG_UART3 }, + { "uart4", NULL, EECONFIG_UART4 }, + { "ipu0", NULL, EECONFIG_IPU0 }, + { "ipu1", NULL, EECONFIG_IPU1 }, + { "can0", NULL, EECONFIG_FLEXCAN }, + { "i2c0", NULL, EECONFIG_I2C0 }, + { "i2c1", NULL, EECONFIG_I2C1 }, + { "i2c2", NULL, EECONFIG_I2C2 }, + { "vpu", NULL, EECONFIG_VPU }, + { "csi0", NULL, EECONFIG_CSI0 }, + { "csi1", NULL, EECONFIG_CSI1 }, + { "spi0", NULL, EECONFIG_ESPCI0 }, + { "spi1", NULL, EECONFIG_ESPCI1 }, + { "spi2", NULL, EECONFIG_ESPCI2 }, + { "spi3", NULL, EECONFIG_ESPCI3 }, + { "spi4", NULL, EECONFIG_ESPCI4 }, + { "spi5", NULL, EECONFIG_ESPCI5 }, + { "gps", "pps", EECONFIG_GPS }, + { "hdmi_in", NULL, EECONFIG_HDMI_IN }, + { "hdmi_out", NULL, EECONFIG_HDMI_OUT }, + { "cvbs_in", NULL, EECONFIG_VID_IN }, + { "cvbs_out", NULL, EECONFIG_VID_OUT }, + { "nand", NULL, EECONFIG_NAND }, + { /* Sentinel */ } +}; + +#ifdef CONFIG_CMD_EECONFIG +static struct ventana_eeprom_config *get_config(const char *name) +{ + struct ventana_eeprom_config *cfg = econfig; + + while (cfg->name) { + if (0 == strcmp(name, cfg->name)) + return cfg; + cfg++; + } + return NULL; +} + +static u8 econfig_bytes[sizeof(ventana_info.config)]; +static int econfig_init = -1; + +int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct ventana_eeprom_config *cfg; + struct ventana_board_info *info = &ventana_info; + int i; + + if (argc < 2) + return CMD_RET_USAGE; + + /* initialize */ + if (econfig_init != 1) { + memcpy(econfig_bytes, info->config, sizeof(econfig_bytes)); + econfig_init = 1; + } + + /* list configs */ + if ((strncmp(argv[1], "list", 4) == 0)) { + cfg = econfig; + while (cfg->name) { + printf("%s: %d\n", cfg->name, + test_bit(cfg->bit, econfig_bytes) ? 1 : 0); + cfg++; + } + } + + /* save */ + else if ((strncmp(argv[1], "save", 4) == 0)) { + unsigned char *buf = (unsigned char *)info; + int chksum; + + /* calculate new checksum */ + memcpy(info->config, econfig_bytes, sizeof(econfig_bytes)); + for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) + chksum += buf[i]; + debug("old chksum:0x%04x\n", + (info->chksum[0] << 8) | info->chksum[1]); + debug("new chksum:0x%04x\n", chksum); + info->chksum[0] = chksum >> 8; + info->chksum[1] = chksum & 0xff; + + /* write new config data */ + if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info, + 1, econfig_bytes, sizeof(econfig_bytes))) { + printf("EEPROM: Failed updating config\n"); + return CMD_RET_FAILURE; + } + + /* write new config data */ + if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info, + 1, info->chksum, 2)) { + printf("EEPROM: Failed updating checksum\n"); + return CMD_RET_FAILURE; + } + + printf("Config saved to EEPROM\n"); + } + + /* get config */ + else if (argc == 2) { + cfg = get_config(argv[1]); + if (cfg) { + printf("%s: %d\n", cfg->name, + test_bit(cfg->bit, econfig_bytes) ? 1 : 0); + } else { + printf("invalid config: %s\n", argv[1]); + return CMD_RET_FAILURE; + } + } + + /* set config */ + else if (argc == 3) { + cfg = get_config(argv[1]); + if (cfg) { + if (simple_strtol(argv[2], NULL, 10)) { + test_and_set_bit(cfg->bit, econfig_bytes); + printf("Enabled %s\n", cfg->name); + } else { + test_and_clear_bit(cfg->bit, econfig_bytes); + printf("Disabled %s\n", cfg->name); + } + } else { + printf("invalid config: %s\n", argv[1]); + return CMD_RET_FAILURE; + } + } + + else + return CMD_RET_USAGE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + econfig, 3, 0, do_econfig, + "EEPROM configuration", + "list - list config\n" + "save - save config to EEPROM\n" + " - get config 'name'\n" + " [0|1] - set config 'name' to value\n" +); + +#endif /* CONFIG_CMD_EECONFIG */ diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c new file mode 100644 index 0000000000..a34a9a84c8 --- /dev/null +++ b/board/gateworks/gw_ventana/gsc.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include "gsc.h" + +#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100) + +/* + * The Gateworks System Controller will fail to ACK a master transaction if + * it is busy, which can occur during its 1HZ timer tick while reading ADC's. + * When this does occur, it will never be busy long enough to fail more than + * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with + * 3 retries. + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_read(chip, addr, alen, buf, len); + if (!ret) + break; + debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + return ret; +} + +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_write(chip, addr, alen, buf, len); + if (!ret) + break; + debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + mdelay(100); + return ret; +} + +#ifdef CONFIG_CMD_GSC +static void read_hwmon(const char *name, uint reg, uint size, uint low, + uint high) +{ + unsigned char buf[3]; + uint ui; + + printf("%-8s:", name); + memset(buf, 0, sizeof(buf)); + if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { + puts("fRD\n"); + } else { + ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); + if (ui == 0xffffff) + printf("invalid"); + else if (ui < low) + printf("%d Failed - Low", ui); + else if (ui > high) + printf("%d Failed - High", ui); + else + printf("%d", ui); + } + puts("\n"); +} + +int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *model = getenv("model"); + + i2c_set_bus_num(0); + read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000); + read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000); + read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500); + read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10)); + read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10)); + read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10)); + read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10)); + read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10)); + read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10)); + + switch (model[3]) { + case '1': /* GW51xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + break; + case '2': /* GW52xx */ + case '3': /* GW53xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + break; + case '4': /* GW54xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10)); + read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + break; + case '5': /* GW55xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + break; + } + return 0; +} + +U_BOOT_CMD(gsc, 1, 1, do_gsc, + "GSC test", + "" +); + +#endif /* CONFIG_CMD_GSC */ diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h new file mode 100644 index 0000000000..da970c39d6 --- /dev/null +++ b/board/gateworks/gw_ventana/gsc.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASSEMBLY__ + +/* i2c slave addresses */ +#define GSC_SC_ADDR 0x20 +#define GSC_RTC_ADDR 0x68 +#define GSC_HWMON_ADDR 0x29 +#define GSC_EEPROM_ADDR 0x51 + +/* System Controller registers */ +enum { + GSC_SC_CTRL0 = 0x00, + GSC_SC_CTRL1 = 0x01, + GSC_SC_STATUS = 0x0a, + GSC_SC_FWVER = 0x0e, +}; + +/* System Controller Control1 bits */ +enum { + GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */ +}; + +/* System Controller Interrupt bits */ +enum { + GSC_SC_IRQ_PB = 0, /* Pushbutton switch */ + GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */ + GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */ + GSC_SC_IRQ_GPIO = 4, /* GPIO change */ + GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */ + GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */ + GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */ +}; + +/* Hardware Monitor registers */ +enum { + GSC_HWMON_TEMP = 0x00, + GSC_HWMON_VIN = 0x02, + GSC_HWMON_VDD_3P3 = 0x05, + GSC_HWMON_VBATT = 0x08, + GSC_HWMON_VDD_5P0 = 0x0b, + GSC_HWMON_VDD_CORE = 0x0e, + GSC_HWMON_VDD_HIGH = 0x14, + GSC_HWMON_VDD_DDR = 0x17, + GSC_HWMON_VDD_SOC = 0x11, + GSC_HWMON_VDD_1P8 = 0x1d, + GSC_HWMON_VDD_2P5 = 0x23, + GSC_HWMON_VDD_1P0 = 0x20, +}; + +/* + * I2C transactions to the GSC are done via these functions which + * perform retries in the case of a busy GSC NAK'ing the transaction + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); +#endif + diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c new file mode 100644 index 0000000000..bb08cd272e --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -0,0 +1,1540 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gsc.h" +#include "ventana_eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO's common to all baseboards */ +#define GP_PHY_RST IMX_GPIO_NR(1, 30) +#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define GP_SD3_CD IMX_GPIO_NR(7, 0) +#define GP_RS232_EN IMX_GPIO_NR(2, 11) +#define GP_MSATA_SEL IMX_GPIO_NR(2, 8) + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) + + +/* + * EEPROM board info struct populated by read_eeprom so that we only have to + * read it once. + */ +struct ventana_board_info ventana_info; + +int board_type; + +/* UART1: Function varies per baseboard */ +iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +/* UART2: Serial Console */ +iomux_v3_cfg_t const uart2_pads[] = { + IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1: GSC */ +struct i2c_pads_info mx6q_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; +struct i2c_pads_info mx6dl_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ +struct i2c_pads_info mx6q_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; +struct i2c_pads_info mx6dl_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3: Misc/Expansion */ +struct i2c_pads_info mx6q_i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; +struct i2c_pads_info mx6dl_i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* MMC */ +iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* CD */ + IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), +}; + +/* ENET */ +iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* PHY nRST */ + IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), +}; + +/* NAND */ +iomux_v3_cfg_t const nfc_pads[] = { + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +#ifdef CONFIG_CMD_NAND +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nfc_pads); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +static void setup_iomux_enet(void) +{ + SETUP_IOMUX_PADS(enet_pads); + + /* toggle PHY_RST# */ + gpio_direction_output(GP_PHY_RST, 0); + mdelay(2); + gpio_set_value(GP_PHY_RST, 1); +} + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); + SETUP_IOMUX_PADS(uart2_pads); +} + +#ifdef CONFIG_USB_EHCI_MX6 +iomux_v3_cfg_t const usb_pads[] = { + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), + IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), + /* OTG PWR */ + IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), +}; + +int board_ehci_hcd_init(int port) +{ + struct ventana_board_info *info = &ventana_info; + + SETUP_IOMUX_PADS(usb_pads); + + /* Reset USB HUB (present on GW54xx/GW53xx) */ + switch (info->model[3]) { + case '3': /* GW53xx */ + case '5': /* GW552x */ + SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(1, 9), 1); + break; + case '4': /* GW54xx */ + SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); + gpio_direction_output(IMX_GPIO_NR(1, 16), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(1, 16), 1); + break; + } + + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + return 0; + gpio_set_value(GP_USB_OTG_PWR, on); + return 0; +} +#endif /* CONFIG_USB_EHCI_MX6 */ + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* Card Detect */ + gpio_direction_input(GP_SD3_CD); + return !gpio_get_value(GP_SD3_CD); +} + +int board_mmc_init(bd_t *bis) +{ + /* Only one USDHC controller on Ventana */ + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg.max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; +} + +static void setup_spi(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 19), 1); + SETUP_IOMUX_PADS(ecspi1_pads); +} +#endif + +/* configure eth0 PHY board-specific LED behavior */ +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* Marvel 88E1510 */ + if (phydev->phy_id == 0x1410dd1) { + /* + * Page 3, Register 16: LED[2:0] Function Control Register + * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link + * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity + */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); + val = phy_read(phydev, MDIO_DEVAD_NONE, 16); + val &= 0xff00; + val |= 0x0017; + phy_write(phydev, MDIO_DEVAD_NONE, 16, val); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + if (board_type != GW552x) + cpu_eth_init(bis); +#endif + +#ifdef CONFIG_CI_UDC + /* For otg ethernet*/ + usb_eth_initialize(bis); +#endif + + return 0; +} + +#if defined(CONFIG_VIDEO_IPUV3) + +static void enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return i2c_set_bus_num(dev->bus) == 0 && + i2c_probe(dev->addr) == 0; +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + + /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + + /* Enable Backlight */ + SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); + gpio_direction_output(IMX_GPIO_NR(1, 18), 1); +} + +struct display_info_t const displays[] = {{ + /* HDMI Output */ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <gpr[3]); + + /* Backlight CABEN on LVDS connector */ + SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); + gpio_direction_output(IMX_GPIO_NR(1, 10), 0); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Baseboard specific GPIO + */ + +/* common to add baseboards */ +static iomux_v3_cfg_t const gw_gpio_pads[] = { + /* MSATA_EN */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), +}; + +/* prototype */ +static iomux_v3_cfg_t const gwproto_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* PCICK_SSON */ + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + + /* GPS_SHDN */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* VID_PWR */ + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* GPS_SHDN */ + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), + /* USBOTG_SEL */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* VID_PWR */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* GPS_SHDN */ + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* MIPI_DIO */ + IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* PCICK_SSON */ + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw552x_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* MX6_DIO[4:9] */ + IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), + /* PCIEGBE1_OFF# */ + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), + /* PCIEGBE2_OFF# */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +/* + * each baseboard has 4 user configurable Digital IO lines which can + * be pinmuxed as a GPIO or in some cases a PWM + */ +struct dio_cfg { + iomux_v3_cfg_t gpio_padmux[2]; + unsigned gpio_param; + iomux_v3_cfg_t pwm_padmux[2]; + unsigned pwm_param; +}; + +struct ventana { + /* pinmux */ + iomux_v3_cfg_t const *gpio_pads; + int num_pads; + /* DIO pinmux/val */ + struct dio_cfg dio_cfg[4]; + /* various gpios (0 if non-existent) */ + int leds[3]; + int pcie_rst; + int mezz_pwren; + int mezz_irq; + int rs485en; + int gps_shdn; + int vidin_en; + int dioi2c_en; + int pcie_sson; + int usb_sel; + int wdis; +}; + +struct ventana gpio_cfg[] = { + /* GW5400proto */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(4, 7), + .mezz_irq = IMX_GPIO_NR(4, 9), + .rs485en = IMX_GPIO_NR(3, 24), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + }, + + /* GW51xx */ + { + .gpio_pads = gw51xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 2), + .vidin_en = IMX_GPIO_NR(5, 20), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW52xx */ + { + .gpio_pads = gw52xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + .usb_sel = IMX_GPIO_NR(1, 2), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW53xx */ + { + .gpio_pads = gw53xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW54xx */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .rs485en = IMX_GPIO_NR(7, 1), + .vidin_en = IMX_GPIO_NR(3, 31), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + .wdis = IMX_GPIO_NR(5, 17), + }, + + /* GW552x */ + { + .gpio_pads = gw552x_gpio_pads, + .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(2, 10), + { 0, 0 }, + 0 + }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + }, +}; + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + u32 reg; + + /* configure PFUZE100 PMIC */ + if (board_type == GW54xx || board_type == GW54proto) { + power_pfuze100_init(CONFIG_I2C_PMIC); + p = pmic_get("PFUZE100"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set VGEN1 to 1.5V and enable */ + pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | LDO_EN); + pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); + + /* Set SWBST to 5.0V and enable */ + pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); + reg |= (SWBST_5_00V | SWBST_MODE_AUTO); + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); + } + } + + /* configure LTC3676 PMIC */ + else { + power_ltc3676_init(CONFIG_I2C_PMIC); + p = pmic_get("LTC3676_PMIC"); + if (p && !pmic_probe(p)) { + puts("PMIC: LTC3676\n"); + /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ + if (is_cpu_type(MXC_CPU_MX6Q)) { + /* mask PGOOD during SW1 transition */ + reg = 0x1d | LTC3676_PGOOD_MASK; + pmic_reg_write(p, LTC3676_DVB1B, reg); + /* set SW1 (VDD_SOC) to 1259mV */ + reg = 0x1d; + pmic_reg_write(p, LTC3676_DVB1A, reg); + + /* mask PGOOD during SW3 transition */ + reg = 0x1d | LTC3676_PGOOD_MASK; + pmic_reg_write(p, LTC3676_DVB3B, reg); + /*set SW3 (VDD_ARM) to 1259mV */ + reg = 0x1d; + pmic_reg_write(p, LTC3676_DVB3A, reg); + } + } + } + + return 0; +} + +/* setup GPIO pinmux and default configuration per baseboard */ +static void setup_board_gpio(int board) +{ + struct ventana_board_info *info = &ventana_info; + const char *s; + char arg[10]; + size_t len; + int i; + int quiet = simple_strtol(getenv("quiet"), NULL, 10); + + if (board >= GW_UNKNOWN) + return; + + /* RS232_EN# */ + gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); + + /* MSATA Enable */ + if (is_cpu_type(MXC_CPU_MX6Q) && + test_bit(EECONFIG_SATA, info->config)) { + gpio_direction_output(GP_MSATA_SEL, + (hwconfig("msata")) ? 1 : 0); + } else { + gpio_direction_output(GP_MSATA_SEL, 0); + } + +#if !defined(CONFIG_CMD_PCI) + /* assert PCI_RST# (released by OS when clock is valid) */ + gpio_direction_output(gpio_cfg[board].pcie_rst, 0); +#endif + + /* turn off (active-high) user LED's */ + for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { + if (gpio_cfg[board].leds[i]) + gpio_direction_output(gpio_cfg[board].leds[i], 1); + } + + /* Expansion Mezzanine IO */ + if (gpio_cfg[board].mezz_pwren) + gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); + if (gpio_cfg[board].mezz_irq) + gpio_direction_input(gpio_cfg[board].mezz_irq); + + /* RS485 Transmit Enable */ + if (gpio_cfg[board].rs485en) + gpio_direction_output(gpio_cfg[board].rs485en, 0); + + /* GPS_SHDN */ + if (gpio_cfg[board].gps_shdn) + gpio_direction_output(gpio_cfg[board].gps_shdn, 1); + + /* Analog video codec power enable */ + if (gpio_cfg[board].vidin_en) + gpio_direction_output(gpio_cfg[board].vidin_en, 1); + + /* DIOI2C_DIS# */ + if (gpio_cfg[board].dioi2c_en) + gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); + + /* PCICK_SSON: disable spread-spectrum clock */ + if (gpio_cfg[board].pcie_sson) + gpio_direction_output(gpio_cfg[board].pcie_sson, 0); + + /* USBOTG Select (PCISKT or FrontPanel) */ + if (gpio_cfg[board].usb_sel) + gpio_direction_output(gpio_cfg[board].usb_sel, 0); + + /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ + if (gpio_cfg[board].wdis) + gpio_direction_output(gpio_cfg[board].wdis, 1); + + /* + * Configure DIO pinmux/padctl registers + * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions + */ + for (i = 0; i < 4; i++) { + struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; + iomux_v3_cfg_t ctrl = DIO_PAD_CFG; + unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; + + sprintf(arg, "dio%d", i); + if (!hwconfig(arg)) + continue; + s = hwconfig_subarg(arg, "padctrl", &len); + if (s) { + ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) + & 0x1ffff) | MUX_MODE_SION; + } + if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { + if (!quiet) { + printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, + (cfg->gpio_param/32)+1, + cfg->gpio_param%32, + cfg->gpio_param); + } + imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | + ctrl); + gpio_direction_input(cfg->gpio_param); + } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && + cfg->pwm_padmux) { + if (!quiet) + printf("DIO%d: pwm%d\n", i, cfg->pwm_param); + imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | + MUX_PAD_CTRL(ctrl)); + } + } + + if (!quiet) { + if (is_cpu_type(MXC_CPU_MX6Q) && + (test_bit(EECONFIG_SATA, info->config))) { + printf("MSATA: %s\n", (hwconfig("msata") ? + "enabled" : "disabled")); + } + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + } +} + +#if defined(CONFIG_CMD_PCI) +int imx6_pcie_toggle_reset(void) +{ + if (board_type < GW_UNKNOWN) { + uint pin = gpio_cfg[board_type].pcie_rst; + gpio_direction_output(pin, 0); + mdelay(50); + gpio_direction_output(pin, 1); + } + return 0; +} + +/* + * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its + * GPIO's as PERST# signals for its downstream ports - configure the GPIO's + * properly and assert reset for 100ms. + */ +void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, + unsigned short vendor, unsigned short device, + unsigned short class) +{ + u32 dw; + + debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); + if (vendor == PCI_VENDOR_ID_PLX && + (device & 0xfff0) == 0x8600 && + PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { + debug("configuring PLX 860X downstream PERST#\n"); + pci_hose_read_config_dword(hose, dev, 0x62c, &dw); + dw |= 0xaaa8; /* GPIO1-7 outputs */ + pci_hose_write_config_dword(hose, dev, 0x62c, dw); + + pci_hose_read_config_dword(hose, dev, 0x644, &dw); + dw |= 0xfe; /* GPIO1-7 output high */ + pci_hose_write_config_dword(hose, dev, 0x644, dw); + + mdelay(100); + } +} +#endif /* CONFIG_CMD_PCI */ + +#ifdef CONFIG_SERIAL_TAG +/* + * called when setting up ATAGS before booting kernel + * populate serialnum from the following (in order of priority): + * serial# env var + * eeprom + */ +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial = getenv("serial#"); + + if (serial) { + serialnr->high = 0; + serialnr->low = simple_strtoul(serial, NULL, 10); + } else if (ventana_info.model[0]) { + serialnr->high = 0; + serialnr->low = ventana_info.serial; + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif + +/* + * Board Support + */ + +/* called from SPL board_init_f() */ +int board_early_init_f(void) +{ + setup_iomux_uart(); + gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +int board_init(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrsetbits_le32(&iomuxc_regs->gpr[1], + IOMUXC_GPR1_OTG_ID_MASK, + IOMUXC_GPR1_OTG_ID_GPIO1); + + /* address of linux boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + if (is_cpu_type(MXC_CPU_MX6Q)) { + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); + } else { + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); + } + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + /* read Gateworks EEPROM into global struct (used later) */ + board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + + /* board-specifc GPIO iomux */ + SETUP_IOMUX_PADS(gw_gpio_pads); + if (board_type < GW_UNKNOWN) { + iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads; + int count = gpio_cfg[board_type].num_pads; + + imx_iomux_v3_setup_multiple_pads(p, count); + } + + return 0; +} + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) +/* + * called during late init (after relocation and after board_init()) + * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and + * EEPROM read. + */ +int checkboard(void) +{ + struct ventana_board_info *info = &ventana_info; + unsigned char buf[4]; + const char *p; + int quiet; /* Quiet or minimal output mode */ + + quiet = 0; + p = getenv("quiet"); + if (p) + quiet = simple_strtol(p, NULL, 10); + else + setenv("quiet", "0"); + + puts("\nGateworks Corporation Copyright 2014\n"); + if (info->model[0]) { + printf("Model: %s\n", info->model); + printf("MFGDate: %02x-%02x-%02x%02x\n", + info->mfgdate[0], info->mfgdate[1], + info->mfgdate[2], info->mfgdate[3]); + printf("Serial:%d\n", info->serial); + } else { + puts("Invalid EEPROM - board will not function fully\n"); + } + if (quiet) + return 0; + + /* Display GSC firmware revision/CRC/status */ + i2c_set_bus_num(CONFIG_I2C_GSC); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { + printf("GSC: v%d", buf[0]); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { + printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */ + printf(" 0x%02x", buf[0]); /* irq status */ + } + puts("\n"); + } + /* Display RTC */ + if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { + printf("RTC: %d\n", + buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); + } + + return 0; +} +#endif + +#ifdef CONFIG_CMD_BMODE +/* + * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 + * see Table 8-11 and Table 5-9 + * BOOT_CFG1[7] = 1 (boot from NAND) + * BOOT_CFG1[5] = 0 - raw NAND + * BOOT_CFG1[4] = 0 - default pad settings + * BOOT_CFG1[3:2] = 00 - devices = 1 + * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 + * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 + * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 + * BOOT_CFG2[0] = 0 - Reset time 12ms + */ +static const struct boot_mode board_boot_modes[] = { + /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + { NULL, 0 }, +}; +#endif + +/* late init */ +int misc_init_r(void) +{ + struct ventana_board_info *info = &ventana_info; + unsigned char reg; + + /* set env vars based on EEPROM data */ + if (ventana_info.model[0]) { + char str[16], fdt[36]; + char *p; + const char *cputype = ""; + int i; + + /* + * FDT name will be prefixed with CPU type. Three versions + * will be created each increasingly generic and bootloader + * env scripts will try loading each from most specific to + * least. + */ + if (is_cpu_type(MXC_CPU_MX6Q) || + is_cpu_type(MXC_CPU_MX6D)) + cputype = "imx6q"; + else if (is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO)) + cputype = "imx6dl"; + setenv("soctype", cputype); + if (8 << (ventana_info.nand_flash_size-1) >= 2048) + setenv("flash_layout", "large"); + else + setenv("flash_layout", "normal"); + memset(str, 0, sizeof(str)); + for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) + str[i] = tolower(info->model[i]); + if (!getenv("model")) + setenv("model", str); + if (!getenv("fdt_file")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file", fdt); + } + p = strchr(str, '-'); + if (p) { + *p++ = 0; + + setenv("model_base", str); + if (!getenv("fdt_file1")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file1", fdt); + } + if (board_type != GW552x) + str[4] = 'x'; + str[5] = 'x'; + str[6] = 0; + if (!getenv("fdt_file2")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file2", fdt); + } + } + + /* initialize env from EEPROM */ + if (test_bit(EECONFIG_ETH0, info->config) && + !getenv("ethaddr")) { + eth_setenv_enetaddr("ethaddr", info->mac0); + } + if (test_bit(EECONFIG_ETH1, info->config) && + !getenv("eth1addr")) { + eth_setenv_enetaddr("eth1addr", info->mac1); + } + + /* board serial-number */ + sprintf(str, "%6d", info->serial); + setenv("serial#", str); + } + + + /* setup baseboard specific GPIO pinmux and config */ + setup_board_gpio(board_type); + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + /* + * The Gateworks System Controller implements a boot + * watchdog (always enabled) as a workaround for IMX6 boot related + * errata such as: + * ERR005768 - no fix scheduled + * ERR006282 - fixed in silicon r1.2 + * ERR007117 - fixed in silicon r1.3 + * ERR007220 - fixed in silicon r1.3 + * ERR007926 - no fix scheduled + * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf + * + * Disable the boot watchdog and display/clear the timeout flag if set + */ + i2c_set_bus_num(CONFIG_I2C_GSC); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { + reg |= (1 << GSC_SC_CTRL1_WDDIS); + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + puts("Error: could not disable GSC Watchdog\n"); + } else { + puts("Error: could not disable GSC Watchdog\n"); + } + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { + if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ + puts("GSC boot watchdog timeout detected\n"); + reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ + gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); + } + } + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) + +/* + * called prior to booting kernel or by 'fdt boardsetup' command + * + * unless 'fdt_noauto' env var is set we will update the following in the DTB: + * - mtd partitions based on mtdparts/mtdids env + * - system-serial (board serial num from EEPROM) + * - board (full model from EEPROM) + * - peripherals removed from DTB if not loaded on board (per EEPROM config) + */ +int ft_board_setup(void *blob, bd_t *bd) +{ + struct ventana_board_info *info = &ventana_info; + struct ventana_eeprom_config *cfg; + struct node_info nodes[] = { + { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + const char *model = getenv("model"); + + if (getenv("fdt_noauto")) { + puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); + return 0; + } + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + + if (!model) { + puts("invalid board info: Leaving FDT fully enabled\n"); + return 0; + } + printf(" Adjusting FDT per EEPROM for %s...\n", model); + + /* board serial number */ + fdt_setprop(blob, 0, "system-serial", getenv("serial#"), + strlen(getenv("serial#")) + 1); + + /* board (model contains model from device-tree) */ + fdt_setprop(blob, 0, "board", info->model, + strlen((const char *)info->model) + 1); + + /* + * Peripheral Config: + * remove nodes by alias path if EEPROM config tells us the + * peripheral is not loaded on the board. + */ + if (getenv("fdt_noconfig")) { + puts(" Skiping periperhal config (fdt_noconfig defined)\n"); + return 0; + } + cfg = econfig; + while (cfg->name) { + if (!test_bit(cfg->bit, info->config)) { + fdt_del_node_and_alias(blob, cfg->dtalias ? + cfg->dtalias : cfg->name); + } + cfg++; + } + + return 0; +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ + diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c new file mode 100644 index 0000000000..97128127fb --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -0,0 +1,469 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ventana_eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ +#define I2C_GSC 0 +#define GSC_EEPROM_ADDR 0x51 +#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ +#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C1: GSC */ +static struct i2c_pads_info mx6q_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; +static struct i2c_pads_info mx6dl_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +static void i2c_setup_iomux(void) +{ + if (is_cpu_type(MXC_CPU_MX6Q)) + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); + else + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); +} + +/* configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + /* SDQS[0:7]: Differential input, 40 ohm */ + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41K128M16JT-125 */ +static struct mx6_ddr3_cfg mt41k128m16jt_125 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* MT41K256M16HA-125 */ +static struct mx6_ddr3_cfg mt41k256m16ha_125 = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * calibration - these are the various CPU/DDR3 combinations we support + */ + +static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl1 = 0x00140026, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl1 = 0x433C034D, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + +static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x003C003C, + .p0_mpwldectrl1 = 0x001F002A, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x42410244, + .p0_mpdgctrl1 = 0x4234023A, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x484A4C4B, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x33342B32, +}; + +static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl1 = 0x00140026, + .p1_mpwldectrl0 = 0x0021001C, + .p1_mpwldectrl1 = 0x0011001D, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl1 = 0x433C034D, + .p1_mpdgctrl0 = 0x032C0324, + .p1_mpdgctrl1 = 0x03310232, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + .p1_mprddlctl = 0x37343141, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, + .p1_mpwrdlctl = 0x42344438, +}; + +static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x003C003C, + .p0_mpwldectrl1 = 0x001F002A, + .p1_mpwldectrl0 = 0x00330038, + .p1_mpwldectrl1 = 0x0022003F, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x42410244, + .p0_mpdgctrl1 = 0x4234023A, + .p1_mpdgctrl0 = 0x022D022D, + .p1_mpdgctrl1 = 0x021C0228, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x484A4C4B, + .p1_mprddlctl = 0x4B4D4E4B, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x33342B32, + .p1_mpwrdlctl = 0x3933332B, +}; + +static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x001E001A, + .p0_mpwldectrl1 = 0x0026001F, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43370349, + .p0_mpdgctrl1 = 0x032D0327, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3D303639, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x32363934, +}; + +static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0X00220021, + .p0_mpwldectrl1 = 0X00200030, + .p1_mpwldectrl0 = 0X002D0027, + .p1_mpwldectrl1 = 0X00150026, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43330342, + .p0_mpdgctrl1 = 0x0339034A, + .p1_mpdgctrl0 = 0x032F0325, + .p1_mpdgctrl1 = 0x032F022E, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0X3A2E3437, + .p1_mprddlctl = 0X35312F3F, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0X33363B37, + .p1_mpwrdlctl = 0X40304239, +}; + +static void spl_dram_init(int width, int size_mb, int board_model) +{ + struct mx6_ddr3_cfg *mem = NULL; + struct mx6_mmdc_calibration *calib = NULL; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width/32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + /* + * MMDC Calibration requires the following data: + * mx6_mmdc_calibration - board-specific calibration (routing delays) + * these calibration values depend on board routing, SoC, and DDR + * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) + * mx6_ddr_cfg - chip specific timing/layout details + */ + if (width == 32 && size_mb == 512) { + mem = &mt41k128m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_128x32_mmdc_calib; + else + calib = &mx6sdl_128x32_mmdc_calib; + debug("2gB density\n"); + } else if (width == 64 && size_mb == 1024) { + mem = &mt41k128m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_128x64_mmdc_calib; + else + calib = &mx6sdl_128x64_mmdc_calib; + debug("2gB density\n"); + } else if (width == 32 && size_mb == 1024) { + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x32_mmdc_calib; + debug("4gB density\n"); + } else if (width == 64 && size_mb == 2048) { + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x64_mmdc_calib; + debug("4gB density\n"); + } + + if (!mem) { + puts("Error: Invalid Memory Configuration\n"); + hang(); + } + if (!calib) { + puts("Error: Invalid Board Calibration Configuration\n"); + hang(); + } + + if (is_cpu_type(MXC_CPU_MX6Q)) + mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, + &mx6dq_grp_ioregs); + else + mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, + &mx6sdl_grp_ioregs); + mx6_dram_cfg(&sysinfo, calib, mem); +} + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + struct ventana_board_info ventana_info; + int board_model; + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + i2c_setup_iomux(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* read/validate EEPROM info to determine board model and SDRAM cfg */ + board_model = read_eeprom(I2C_GSC, &ventana_info); + + /* provide some some default: 32bit 128MB */ + if (GW_UNKNOWN == board_model) { + ventana_info.sdram_width = 2; + ventana_info.sdram_size = 3; + } + + /* configure MMDC for SDRAM width/size and per-model calibration */ + spl_dram_init(8 << ventana_info.sdram_width, + 16 << ventana_info.sdram_size, + board_model); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h new file mode 100644 index 0000000000..af12711ac2 --- /dev/null +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _VENTANA_EEPROM_ +#define _VENTANA_EEPROM_ + +struct ventana_board_info { + u8 mac0[6]; /* 0x00: MAC1 */ + u8 mac1[6]; /* 0x06: MAC2 */ + u8 res0[12]; /* 0x0C: reserved */ + u32 serial; /* 0x18: Serial Number (read only) */ + u8 res1[4]; /* 0x1C: reserved */ + u8 mfgdate[4]; /* 0x20: MFG date (read only) */ + u8 res2[7]; /* 0x24 */ + /* sdram config */ + u8 sdram_size; /* 0x2B: (16 << n) MB */ + u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */ + u8 sdram_width; /* 0x2D: (8 << n) bit */ + /* cpu config */ + u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */ + u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */ + u8 model[16]; /* 0x30: model string */ + /* FLASH config */ + u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */ + u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */ + + /* Config1: SoC Peripherals */ + u8 config[8]; /* 0x42: loading options */ + + u8 res3[4]; /* 0x4A */ + + u8 chksum[2]; /* 0x4E */ +}; + +/* config bits */ +enum { + EECONFIG_ETH0, + EECONFIG_ETH1, + EECONFIG_HDMI_OUT, + EECONFIG_SATA, + EECONFIG_PCIE, + EECONFIG_SSI0, + EECONFIG_SSI1, + EECONFIG_LCD, + EECONFIG_LVDS0, + EECONFIG_LVDS1, + EECONFIG_USB0, + EECONFIG_USB1, + EECONFIG_SD0, + EECONFIG_SD1, + EECONFIG_SD2, + EECONFIG_SD3, + EECONFIG_UART0, + EECONFIG_UART1, + EECONFIG_UART2, + EECONFIG_UART3, + EECONFIG_UART4, + EECONFIG_IPU0, + EECONFIG_IPU1, + EECONFIG_FLEXCAN, + EECONFIG_MIPI_DSI, + EECONFIG_MIPI_CSI, + EECONFIG_TZASC0, + EECONFIG_TZASC1, + EECONFIG_I2C0, + EECONFIG_I2C1, + EECONFIG_I2C2, + EECONFIG_VPU, + EECONFIG_CSI0, + EECONFIG_CSI1, + EECONFIG_CAAM, + EECONFIG_MEZZ, + EECONFIG_RES1, + EECONFIG_RES2, + EECONFIG_RES3, + EECONFIG_RES4, + EECONFIG_ESPCI0, + EECONFIG_ESPCI1, + EECONFIG_ESPCI2, + EECONFIG_ESPCI3, + EECONFIG_ESPCI4, + EECONFIG_ESPCI5, + EECONFIG_RES5, + EECONFIG_RES6, + EECONFIG_GPS, + EECONFIG_SPIFL0, + EECONFIG_SPIFL1, + EECONFIG_GSPBATT, + EECONFIG_HDMI_IN, + EECONFIG_VID_OUT, + EECONFIG_VID_IN, + EECONFIG_NAND, + EECONFIG_RES8, + EECONFIG_RES9, + EECONFIG_RES10, + EECONFIG_RES11, + EECONFIG_RES12, + EECONFIG_RES13, + EECONFIG_RES14, + EECONFIG_RES15, +}; + +enum { + GW54proto, /* original GW5400-A prototype */ + GW51xx, + GW52xx, + GW53xx, + GW54xx, + GW552x, + GW_UNKNOWN, + GW_BADCRC, +}; + +/* config items */ +struct ventana_eeprom_config { + const char *name; /* name of item */ + const char *dtalias; /* name of dt node to remove if not set */ + int bit; /* bit within config */ +}; + +extern struct ventana_eeprom_config econfig[]; +extern struct ventana_board_info ventana_info; + +int read_eeprom(int bus, struct ventana_board_info *); + +#endif diff --git a/board/gdsys/405ep/Kconfig b/board/gdsys/405ep/Kconfig new file mode 100644 index 0000000000..20cb80fc2e --- /dev/null +++ b/board/gdsys/405ep/Kconfig @@ -0,0 +1,51 @@ +if TARGET_DLVISION_10G + +config SYS_BOARD + default "405ep" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "dlvision-10g" + +endif + +if TARGET_IO + +config SYS_BOARD + default "405ep" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "io" + +endif + +if TARGET_IOCON + +config SYS_BOARD + default "405ep" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "iocon" + +endif + +if TARGET_NEO + +config SYS_BOARD + default "405ep" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "neo" + +endif diff --git a/board/gdsys/405ep/MAINTAINERS b/board/gdsys/405ep/MAINTAINERS new file mode 100644 index 0000000000..14038804b8 --- /dev/null +++ b/board/gdsys/405ep/MAINTAINERS @@ -0,0 +1,12 @@ +405EP BOARD +M: Dirk Eibach +S: Maintained +F: board/gdsys/405ep/ +F: include/configs/dlvision-10g.h +F: configs/dlvision-10g_defconfig +F: include/configs/io.h +F: configs/io_defconfig +F: include/configs/iocon.h +F: configs/iocon_defconfig +F: include/configs/neo.h +F: configs/neo_defconfig diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile index 81d23c58b6..857ec04fa8 100644 --- a/board/gdsys/405ep/Makefile +++ b/board/gdsys/405ep/Makefile @@ -5,30 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-$(CONFIG_NEO) += neo.o -COBJS-$(CONFIG_IO) += io.o -COBJS-$(CONFIG_IOCON) += iocon.o -COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o - -COBJS := $(BOARD).o $(COBJS-y) -SOBJS = - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := 405ep.o +obj-$(CONFIG_NEO) += neo.o +obj-$(CONFIG_IO) += io.o +obj-$(CONFIG_IOCON) += iocon.o +obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index 9f84fb1869..3a51d864cd 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -17,6 +17,7 @@ #include "../common/osd.h" #include "../common/mclink.h" +#include "../common/phy.h" #include #include @@ -30,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) +#define MAX_MUX_CHANNELS 2 + enum { UNITTYPE_MAIN_SERVER = 0, UNITTYPE_MAIN_USER = 1, @@ -44,6 +47,8 @@ enum { HWVER_120 = 3, HWVER_200 = 4, HWVER_210 = 5, + HWVER_220 = 6, + HWVER_230 = 7, }; enum { @@ -73,6 +78,11 @@ enum { RAM_DDR3_32 = 1, }; +enum { + CARRIER_SPEED_1G = 0, + CARRIER_SPEED_2_5G = 1, +}; + enum { MCFPGA_DONE = 1 << 0, MCFPGA_INIT_N = 1 << 1, @@ -89,9 +99,6 @@ enum { unsigned int mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; -static int setup_88e1518(const char *bus, unsigned char addr); -static int verify_88e1518(const char *bus, unsigned char addr); - int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) { int res; @@ -156,7 +163,7 @@ int checkboard(void) return 0; } -static void print_fpga_info(unsigned int fpga) +static void print_fpga_info(unsigned int fpga, bool rgmii2_present) { u16 versions; u16 fpga_version; @@ -168,13 +175,15 @@ static void print_fpga_info(unsigned int fpga) unsigned feature_audio; unsigned feature_sysclock; unsigned feature_ramconfig; + unsigned feature_carrier_speed; unsigned feature_carriers; unsigned feature_video_channels; - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - FPGA_GET_REG(0, versions, &versions); - FPGA_GET_REG(0, fpga_version, &fpga_version); - FPGA_GET_REG(0, fpga_features, &fpga_features); + int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM; + + FPGA_GET_REG(fpga, versions, &versions); + FPGA_GET_REG(fpga, fpga_version, &fpga_version); + FPGA_GET_REG(fpga, fpga_features, &fpga_features); unit_type = (versions & 0xf000) >> 12; feature_compression = (fpga_features & 0xe000) >> 13; @@ -182,6 +191,7 @@ static void print_fpga_info(unsigned int fpga) feature_audio = (fpga_features & 0x0600) >> 9; feature_sysclock = (fpga_features & 0x0180) >> 7; feature_ramconfig = (fpga_features & 0x0060) >> 5; + feature_carrier_speed = fpga_features & (1<<4); feature_carriers = (fpga_features & 0x000c) >> 2; feature_video_channels = fpga_features & 0x0003; @@ -237,11 +247,21 @@ static void print_fpga_info(unsigned int fpga) printf(" HW-Ver 2.10,"); break; + case HWVER_220: + printf(" HW-Ver 2.20,"); + break; + + case HWVER_230: + printf(" HW-Ver 2.30,"); + break; + default: printf(" HW-Ver %d(not supported),", hardware_version); break; } + if (rgmii2_present) + printf(" RGMII2,"); } if (unit_type == UNITTYPE_VIDEO_USER) { @@ -334,7 +354,8 @@ static void print_fpga_info(unsigned int fpga) break; } - printf(", %d carrier(s)", feature_carriers); + printf(", %d carrier(s) %s", feature_carriers, + feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); printf(", %d video channel(s)\n", feature_video_channels); } @@ -343,11 +364,22 @@ int last_stage_init(void) { int slaves; unsigned int k; + unsigned int mux_ch; unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + u16 fpga_features; + int feature_carrier_speed; + bool ch0_rgmii2_present = false; - print_fpga_info(0); - osd_probe(0); + FPGA_GET_REG(0, fpga_features, &fpga_features); + feature_carrier_speed = fpga_features & (1<<4); + + if (!legacy) { + /* Turn on Parade DP501 */ + pca9698_direction_output(0x20, 9, 1); + + ch0_rgmii2_present = !pca9698_get_value(0x20, 30); + } /* wait for FPGA done */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { @@ -366,36 +398,41 @@ int last_stage_init(void) } } - if (!legacy) { + if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) { miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, bb_miiphy_write); - if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) { - printf("Fixup 88e1518 erratum on %s\n", - bb_miiphy_buses[0].name); - setup_88e1518(bb_miiphy_buses[0].name, 0); + for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { + if ((mux_ch == 1) && !ch0_rgmii2_present) + continue; + + setup_88e1518(bb_miiphy_buses[0].name, mux_ch); } } - /* wait for slave-PLLs to be up and running */ + /* give slave-PLLs and Parade DP501 some time to be up and running */ udelay(500000); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); mclink_fpgacount = 0; + print_fpga_info(0, ch0_rgmii2_present); + osd_probe(0); + if (slaves <= 0) return 0; mclink_fpgacount = slaves; for (k = 1; k <= slaves; ++k) { - print_fpga_info(k); + FPGA_GET_REG(k, fpga_features, &fpga_features); + feature_carrier_speed = fpga_features & (1<<4); + + print_fpga_info(k, false); osd_probe(k); - miiphy_register(bb_miiphy_buses[k].name, - bb_miiphy_read, bb_miiphy_write); - if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) { - printf("Fixup 88e1518 erratum on %s\n", - bb_miiphy_buses[k].name); + if (feature_carrier_speed == CARRIER_SPEED_1G) { + miiphy_register(bb_miiphy_buses[k].name, + bb_miiphy_read, bb_miiphy_write); setup_88e1518(bb_miiphy_buses[k].name, 0); } } @@ -562,7 +599,7 @@ static int mii_delay(struct bb_miiphy_bus *bus) struct bb_miiphy_bus bb_miiphy_buses[] = { { - .name = "trans1", + .name = "board0", .init = mii_dummy_init, .mdio_active = mii_mdio_active, .mdio_tristate = mii_mdio_tristate, @@ -573,7 +610,7 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { .priv = &fpga_mii[0], }, { - .name = "trans2", + .name = "board1", .init = mii_dummy_init, .mdio_active = mii_mdio_active, .mdio_tristate = mii_mdio_tristate, @@ -584,7 +621,7 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { .priv = &fpga_mii[1], }, { - .name = "trans3", + .name = "board2", .init = mii_dummy_init, .mdio_active = mii_mdio_active, .mdio_tristate = mii_mdio_tristate, @@ -595,7 +632,7 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { .priv = &fpga_mii[2], }, { - .name = "trans4", + .name = "board3", .init = mii_dummy_init, .mdio_active = mii_mdio_active, .mdio_tristate = mii_mdio_tristate, @@ -609,57 +646,3 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / sizeof(bb_miiphy_buses[0]); - -/* - * Workaround for erratum mentioned in 88E1518 release notes - */ - -static int verify_88e1518(const char *bus, unsigned char addr) -{ - u16 phy_id1, phy_id2; - - if (miiphy_read(bus, addr, 2, &phy_id1) || - miiphy_read(bus, addr, 3, &phy_id2)) { - printf("Error reading from the PHY addr=%02x\n", addr); - return -EIO; - } - - if ((phy_id1 != 0x0141) || ((phy_id2 & 0xfff0) != 0x0dd0)) - return -EINVAL; - - return 0; -} - -struct regfix_88e1518 { - u8 reg; - u16 data; -} regfix_88e1518[] = { - { 22, 0x00ff }, - { 17, 0x214b }, - { 16, 0x2144 }, - { 17, 0x0c28 }, - { 16, 0x2146 }, - { 17, 0xb233 }, - { 16, 0x214d }, - { 17, 0xcc0c }, - { 16, 0x2159 }, - { 22, 0x00fb }, - { 7, 0xc00d }, - { 22, 0x0000 }, -}; - -static int setup_88e1518(const char *bus, unsigned char addr) -{ - unsigned int k; - - for (k = 0; k < ARRAY_SIZE(regfix_88e1518); ++k) { - if (miiphy_write(bus, addr, - regfix_88e1518[k].reg, - regfix_88e1518[k].data)) { - printf("Error writing to the PHY addr=%02x\n", addr); - return -1; - } - } - - return 0; -} diff --git a/board/gdsys/405ex/Kconfig b/board/gdsys/405ex/Kconfig new file mode 100644 index 0000000000..52a8d89011 --- /dev/null +++ b/board/gdsys/405ex/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IO64 + +config SYS_BOARD + default "405ex" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "io64" + +endif diff --git a/board/gdsys/405ex/MAINTAINERS b/board/gdsys/405ex/MAINTAINERS new file mode 100644 index 0000000000..395b1ac102 --- /dev/null +++ b/board/gdsys/405ex/MAINTAINERS @@ -0,0 +1,6 @@ +405EX BOARD +M: Dirk Eibach +S: Maintained +F: board/gdsys/405ex/ +F: include/configs/io64.h +F: configs/io64_defconfig diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile index 9846823e28..a668460119 100644 --- a/board/gdsys/405ex/Makefile +++ b/board/gdsys/405ex/Makefile @@ -5,33 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-$(CONFIG_IO64) += io64.o - -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o - -COBJS := $(BOARD).o $(COBJS-y) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := 405ex.o +obj-$(CONFIG_IO64) += io64.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index 2f8e306261..3a075c471f 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -287,7 +287,7 @@ int last_stage_init(void) for (fpga = 0; fpga < 2; ++fpga) { for (k = 0; k < 32; ++k) { u16 status; - FPGA_GET_REG(k, ch[k].status_int, &status); + FPGA_GET_REG(fpga, ch[k].status_int, &status); if (!(status & (1 << 4))) { failed = 1; printf("fpga %d channel %d: no serdes lock\n", @@ -304,7 +304,7 @@ int last_stage_init(void) for (fpga = 0; fpga < 2; ++fpga) { for (k = 0; k < 32; ++k) { u16 status; - FPGA_GET_REG(k, hicb_ch[k].status_int, &status); + FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status); if (status) printf("fpga %d hicb %d: hicb status %04x\n", fpga, k, status); diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 216ad964af..49579434df 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -5,37 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) -endif - -LIB = $(obj)lib$(VENDOR).o - -COBJS-$(CONFIG_SYS_FPGA_COMMON) += fpga.o - -COBJS-$(CONFIG_IO) += miiphybb.o -COBJS-$(CONFIG_IO64) += miiphybb.o -COBJS-$(CONFIG_IOCON) += osd.o mclink.o -COBJS-$(CONFIG_DLVISION_10G) += osd.o -COBJS-$(CONFIG_CONTROLCENTERD) += dp501.o - -COBJS := $(COBJS-y) -SOBJS = - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o +obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o +obj-$(CONFIG_IO) += miiphybb.o +obj-$(CONFIG_IO64) += miiphybb.o +obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o +obj-$(CONFIG_DLVISION_10G) += osd.o +obj-$(CONFIG_CONTROLCENTERD) += dp501.o +obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c new file mode 100644 index 0000000000..e0c74fee80 --- /dev/null +++ b/board/gdsys/common/cmd_ioloop.c @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include + +enum { + STATE_TX_PACKET_BUILDING = 1<<0, + STATE_TX_TRANSMITTING = 1<<1, + STATE_TX_BUFFER_FULL = 1<<2, + STATE_TX_ERR = 1<<3, + STATE_RECEIVE_TIMEOUT = 1<<4, + STATE_PROC_RX_STORE_TIMEOUT = 1<<5, + STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6, + STATE_RX_DIST_ERR = 1<<7, + STATE_RX_LENGTH_ERR = 1<<8, + STATE_RX_FRAME_CTR_ERR = 1<<9, + STATE_RX_FCS_ERR = 1<<10, + STATE_RX_PACKET_DROPPED = 1<<11, + STATE_RX_DATA_LAST = 1<<12, + STATE_RX_DATA_FIRST = 1<<13, + STATE_RX_DATA_AVAILABLE = 1<<15, +}; + +enum { + CTRL_PROC_RECEIVE_ENABLE = 1<<12, + CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15, +}; + +enum { + IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5, + IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6, + IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7, + IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8, +}; + +struct io_generic_packet { + u16 target_address; + u16 source_address; + u8 packet_type; + u8 bc; + u16 packet_length; +} __attribute__((__packed__)); + +unsigned long long rx_ctr; +unsigned long long tx_ctr; +unsigned long long err_ctr; + +static void io_check_status(unsigned int fpga, u16 status, bool silent) +{ + u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | + STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR | + STATE_RX_PACKET_DROPPED | STATE_TX_ERR; + + if (!(status & mask)) { + FPGA_SET_REG(fpga, ep.rx_tx_status, status); + return; + } + + err_ctr++; + FPGA_SET_REG(fpga, ep.rx_tx_status, status); + + if (silent) + return; + + if (status & STATE_RX_PACKET_DROPPED) + printf("RX_PACKET_DROPPED, status %04x\n", status); + + if (status & STATE_RX_DIST_ERR) + printf("RX_DIST_ERR\n"); + if (status & STATE_RX_LENGTH_ERR) + printf("RX_LENGTH_ERR\n"); + if (status & STATE_RX_FRAME_CTR_ERR) + printf("RX_FRAME_CTR_ERR\n"); + if (status & STATE_RX_FCS_ERR) + printf("RX_FCS_ERR\n"); + + if (status & STATE_TX_ERR) + printf("TX_ERR\n"); +} + +static void io_send(unsigned int fpga, unsigned int size) +{ + unsigned int k; + struct io_generic_packet packet = { + .source_address = 1, + .packet_type = 1, + .packet_length = size, + }; + u16 *p = (u16 *)&packet; + + for (k = 0; k < sizeof(packet) / 2; ++k) + FPGA_SET_REG(fpga, ep.transmit_data, *p++); + + for (k = 0; k < (size + 1) / 2; ++k) + FPGA_SET_REG(fpga, ep.transmit_data, k); + + FPGA_SET_REG(fpga, ep.rx_tx_control, + CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER); + + tx_ctr++; +} + +static void io_receive(unsigned int fpga) +{ + unsigned int k = 0; + u16 rx_tx_status; + + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + while (rx_tx_status & STATE_RX_DATA_AVAILABLE) { + u16 rx; + + if (rx_tx_status & STATE_RX_DATA_LAST) + rx_ctr++; + + FPGA_GET_REG(fpga, ep.receive_data, &rx); + + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + ++k; + } +} + +static void io_reflect(unsigned int fpga) +{ + u16 buffer[128]; + + unsigned int k = 0; + unsigned int n; + u16 rx_tx_status; + + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + while (rx_tx_status & STATE_RX_DATA_AVAILABLE) { + FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]); + if (rx_tx_status & STATE_RX_DATA_LAST) + break; + + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + } + + if (!k) + return; + + for (n = 0; n < k; ++n) + FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]); + + FPGA_SET_REG(fpga, ep.rx_tx_control, + CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER); + + tx_ctr++; +} + +/* + * FPGA io-endpoint reflector + * + * Syntax: + * ioreflect {fpga} {reportrate} + */ +int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int fpga; + unsigned int rate = 0; + unsigned long long last_seen = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + fpga = simple_strtoul(argv[1], NULL, 10); + + /* + * If another parameter, it is the report rate in packets. + */ + if (argc > 2) + rate = simple_strtoul(argv[2], NULL, 10); + + /* enable receive path */ + FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); + + /* set device address to dummy 1*/ + FPGA_SET_REG(fpga, ep.device_address, 1); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + u16 top_int; + u16 rx_tx_status; + + FPGA_GET_REG(fpga, top_interrupt, &top_int); + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + io_check_status(fpga, rx_tx_status, true); + if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && + (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) + io_reflect(fpga); + + if (rate) { + if (!(tx_ctr % rate) && (tx_ctr != last_seen)) + printf("refl %llu, err %llu\n", tx_ctr, + err_ctr); + last_seen = tx_ctr; + } + + if (ctrlc()) + break; + } + + return 0; +} + +/* + * FPGA io-endpoint looptest + * + * Syntax: + * ioloop {fpga} {size} {rate} + */ +#define DISP_LINE_LEN 16 +int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int fpga; + unsigned int size; + unsigned int rate = 0; + + if (argc < 3) + return CMD_RET_USAGE; + + /* + * FPGA is specified since argc > 2 + */ + fpga = simple_strtoul(argv[1], NULL, 10); + + /* + * packet size is specified since argc > 2 + */ + size = simple_strtoul(argv[2], NULL, 10); + + /* + * If another parameter, it is the test rate in packets per second. + */ + if (argc > 3) + rate = simple_strtoul(argv[3], NULL, 10); + + /* enable receive path */ + FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); + + /* set device address to dummy 1*/ + FPGA_SET_REG(fpga, ep.device_address, 1); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + u16 top_int; + u16 rx_tx_status; + + FPGA_GET_REG(fpga, top_interrupt, &top_int); + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + io_check_status(fpga, rx_tx_status, false); + if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) + io_send(fpga, size); + if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) + io_receive(fpga); + + if (rate) { + if (ctrlc()) + break; + udelay(1000000 / rate); + if (!(tx_ctr % rate)) + printf("d %lld, tx %llu, rx %llu, err %llu\n", + tx_ctr - rx_ctr, tx_ctr, rx_ctr, + err_ctr); + } + } + + return 0; +} + +U_BOOT_CMD( + ioloop, 4, 0, do_ioloop, + "fpga io-endpoint looptest", + "fpga packetsize [packets/sec]" +); + +U_BOOT_CMD( + ioreflect, 3, 0, do_ioreflect, + "fpga io-endpoint reflector", + "fpga reportrate" +); diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 52f3ea167f..7eb15ed0ba 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -54,14 +54,39 @@ static void dp501_link_training(u8 addr) void dp501_powerup(u8 addr) { dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */ + dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/ i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */ dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */ dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */ i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */ dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */ dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */ + dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */ + +#ifdef CONFIG_SYS_DP501_VCAPCTRL0 + i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0); +#else i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */ +#endif + +#ifdef CONFIG_SYS_DP501_DIFFERENTIAL + i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */ + i2c_reg_write(addr + 2, 0x25, 0x04); + i2c_reg_write(addr + 2, 0x26, 0x10); +#else i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */ +#endif + + i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */ + i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */ + i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */ + i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */ + i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */ + i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */ + dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */ + i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */ + i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */ + i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */ if (dp501_detect_cable_adapter(addr)) { printf("DVI/HDMI cable adapter detected\n"); @@ -69,16 +94,6 @@ void dp501_powerup(u8 addr) dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */ } else { printf("no DVI/HDMI cable adapter detected\n"); - i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */ - i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */ - i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */ - i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */ - i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */ - i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */ - dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */ - i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */ - i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */ - i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */ dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */ dp501_link_training(addr); diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c new file mode 100644 index 0000000000..1d6eb7bd55 --- /dev/null +++ b/board/gdsys/common/ihs_mdio.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include + +#include "ihs_mdio.h" + +static int ihs_mdio_idle(struct mii_dev *bus) +{ + struct ihs_mdio_info *info = bus->priv; + u16 val; + unsigned int ctr = 0; + + do { + FPGA_GET_REG(info->fpga, mdio.control, &val); + udelay(100); + if (ctr++ > 10) + return -1; + } while (!(val & (1 << 12))); + + return 0; +} + +static int ihs_mdio_reset(struct mii_dev *bus) +{ + ihs_mdio_idle(bus); + + return 0; +} + +static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr, + int regnum) +{ + struct ihs_mdio_info *info = bus->priv; + u16 val; + + ihs_mdio_idle(bus); + + FPGA_SET_REG(info->fpga, mdio.control, + ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10)); + + /* wait for rx data available */ + udelay(100); + + FPGA_GET_REG(info->fpga, mdio.rx_data, &val); + + return val; +} + +static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr, + int regnum, u16 value) +{ + struct ihs_mdio_info *info = bus->priv; + + ihs_mdio_idle(bus); + + FPGA_SET_REG(info->fpga, mdio.address_data, value); + FPGA_SET_REG(info->fpga, mdio.control, + ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10)); + + return 0; +} + +int ihs_mdio_init(struct ihs_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate FSL MDIO bus\n"); + return -1; + } + + bus->read = ihs_mdio_read; + bus->write = ihs_mdio_write; + bus->reset = ihs_mdio_reset; + sprintf(bus->name, info->name); + + bus->priv = info; + + return mdio_register(bus); +} diff --git a/board/gdsys/common/ihs_mdio.h b/board/gdsys/common/ihs_mdio.h new file mode 100644 index 0000000000..64b4049378 --- /dev/null +++ b/board/gdsys/common/ihs_mdio.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IHS_MDIO_H_ +#define _IHS_MDIO_H_ + +struct ihs_mdio_info { + u32 fpga; + char *name; +}; + +int ihs_mdio_init(struct ihs_mdio_info *info); + +#endif diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index c49cd9a619..55ecdf1012 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -9,6 +9,7 @@ #include #include +#include "dp501.h" #include #define CH7301_I2C_ADDR 0x75 @@ -24,6 +25,8 @@ #define SIL1178_MASTER_I2C_ADDRESS 0x38 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 +#define DP501_I2C_ADDR 0x08 + #define PIXCLK_640_480_60 25180000 enum { @@ -54,51 +57,23 @@ u16 *buf; unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; -#ifdef CONFIG_SYS_CH7301 -int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; +#ifdef CONFIG_SYS_ICS8N3QV01_I2C +int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C; #endif -#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) -static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) -{ - u16 val; - - do { - FPGA_GET_REG(screen, extended_interrupt, &val); - } while (val & (1 << 12)); - - FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8)); - FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1)); -} +#ifdef CONFIG_SYS_CH7301_I2C +int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; +#endif -static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) -{ - unsigned int ctr = 0; - u16 val; - - do { - FPGA_GET_REG(screen, extended_interrupt, &val); - } while (val & (1 << 12)); - - FPGA_SET_REG(screen, extended_interrupt, 1 << 14); - FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg); - FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1)); - - FPGA_GET_REG(screen, extended_interrupt, &val); - while (!(val & (1 << 14))) { - udelay(100000); - if (ctr++ > 5) { - printf("iic receive timeout\n"); - break; - } - FPGA_GET_REG(screen, extended_interrupt, &val); - } +#ifdef CONFIG_SYS_SIL1178_I2C +int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C; +#endif - FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val); - return val >> 8; -} +#ifdef CONFIG_SYS_DP501_I2C +int dp501_i2c[] = CONFIG_SYS_DP501_I2C; #endif + #ifdef CONFIG_SYS_MPC92469AC static void mpc92469ac_calc_parameters(unsigned int fout, unsigned int *post_div, unsigned int *feedback_div) @@ -151,9 +126,9 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout) } #endif -#ifdef CONFIG_SYS_ICS8N3QV01 +#ifdef CONFIG_SYS_ICS8N3QV01_I2C -static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) +static unsigned int ics8n3qv01_get_fout_calc(unsigned index) { unsigned long long n; unsigned long long mint; @@ -164,11 +139,11 @@ static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) if (index > 3) return 0; - reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index); - reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index); - reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index); - reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index); - reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index); + reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index); + reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index); + reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index); + reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index); + reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index); mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20); mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1) @@ -216,7 +191,7 @@ static void ics8n3qv01_calc_parameters(unsigned int fout, *_n = n; } -static void ics8n3qv01_set(unsigned screen, unsigned int fout) +static void ics8n3qv01_set(unsigned int fout) { unsigned int n; unsigned int mint; @@ -226,7 +201,7 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) long long off_ppm; u8 reg0, reg4, reg8, reg12, reg18, reg20; - fout_calc = ics8n3qv01_get_fout_calc(screen, 1); + fout_calc = ics8n3qv01_get_fout_calc(1); off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000 / ICS8N3QV01_F_DEFAULT_1; printf(" PLL is off by %lld ppm\n", off_ppm); @@ -234,28 +209,28 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) / ICS8N3QV01_F_DEFAULT_1; ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n); - reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0; + reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0; reg0 |= (mint & 0x1f) << 1; reg0 |= (mfrac >> 17) & 0x01; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0); reg4 = mfrac >> 9; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4); reg8 = mfrac >> 1; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8); reg12 = mfrac << 7; reg12 |= n & 0x7f; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12); - reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03; + reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03; reg18 |= 0x20; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18); - reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f; + reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f; reg20 |= mint & (1 << 5); - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20); } #endif @@ -314,10 +289,9 @@ int osd_probe(unsigned screen) { u16 version; u16 features; - u8 value; -#ifdef CONFIG_SYS_CH7301 int old_bus = i2c_get_bus_num(); -#endif + bool pixclock_present = false; + bool output_driver_present = false; FPGA_GET_REG(0, osd.version, &version); FPGA_GET_REG(0, osd.features, &features); @@ -332,50 +306,76 @@ int osd_probe(unsigned screen) printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", screen, version/100, version%100, base_width, base_height); -#ifdef CONFIG_SYS_CH7301 - i2c_set_bus_num(ch7301_i2c[screen]); - value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); - if (value != 0x17) { - printf(" Probing CH7301 failed, DID %02x\n", value); - i2c_set_bus_num(old_bus); - return -1; - } - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); - i2c_set_bus_num(old_bus); -#endif + /* setup pixclock */ #ifdef CONFIG_SYS_MPC92469AC + pixclock_present = true; mpc92469ac_set(screen, PIXCLK_640_480_60); #endif -#ifdef CONFIG_SYS_ICS8N3QV01 - ics8n3qv01_set(screen, PIXCLK_640_480_60); +#ifdef CONFIG_SYS_ICS8N3QV01_I2C + i2c_set_bus_num(ics8n3qv01_i2c[screen]); + if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) { + ics8n3qv01_set(PIXCLK_640_480_60); + pixclock_present = true; + } #endif -#ifdef CONFIG_SYS_SIL1178 - value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02); - if (value != 0x06) { - printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value); - return -1; + if (!pixclock_present) + printf(" no pixelclock found\n"); + + /* setup output driver */ + +#ifdef CONFIG_SYS_CH7301_I2C + i2c_set_bus_num(ch7301_i2c[screen]); + if (!i2c_probe(CH7301_I2C_ADDR)) { + u8 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); + + if (value == 0x17) { + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); + output_driver_present = true; + } + } +#endif + +#ifdef CONFIG_SYS_SIL1178_I2C + i2c_set_bus_num(sil1178_i2c[screen]); + if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) { + if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) { + /* + * magic initialization sequence, + * adapted from datasheet + */ + i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); + output_driver_present = true; + } } - /* magic initialization sequence adapted from datasheet */ - fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); #endif - FPGA_SET_REG(screen, videocontrol, 0x0002); +#ifdef CONFIG_SYS_DP501_I2C + i2c_set_bus_num(dp501_i2c[screen]); + if (!i2c_probe(DP501_I2C_ADDR)) { + dp501_powerup(DP501_I2C_ADDR); + output_driver_present = true; + } +#endif + + if (!output_driver_present) + printf(" no output driver found\n"); + FPGA_SET_REG(screen, osd.control, 0x0049); FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); @@ -385,6 +385,8 @@ int osd_probe(unsigned screen) if (screen > max_osd_screen) max_osd_screen = screen; + i2c_set_bus_num(old_bus); + return 0; } diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c new file mode 100644 index 0000000000..fb92658178 --- /dev/null +++ b/board/gdsys/common/phy.c @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include + +enum { + MIICMD_SET, + MIICMD_MODIFY, + MIICMD_VERIFY_VALUE, + MIICMD_WAIT_FOR_VALUE, +}; + +struct mii_setupcmd { + u8 token; + u8 reg; + u16 data; + u16 mask; + u32 timeout; +}; + +/* + * verify we are talking to a 88e1518 + */ +struct mii_setupcmd verify_88e1518[] = { + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff }, + { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 }, +}; + +/* + * workaround for erratum mentioned in 88E1518 release notes + */ +struct mii_setupcmd fixup_88e1518[] = { + { MIICMD_SET, 22, 0x00ff }, + { MIICMD_SET, 17, 0x214b }, + { MIICMD_SET, 16, 0x2144 }, + { MIICMD_SET, 17, 0x0c28 }, + { MIICMD_SET, 16, 0x2146 }, + { MIICMD_SET, 17, 0xb233 }, + { MIICMD_SET, 16, 0x214d }, + { MIICMD_SET, 17, 0xcc0c }, + { MIICMD_SET, 16, 0x2159 }, + { MIICMD_SET, 22, 0x00fb }, + { MIICMD_SET, 7, 0xc00d }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * default initialization: + * - set RGMII receive timing to "receive clock transition when data stable" + * - set RGMII transmit timing to "transmit clock internally delayed" + * - set RGMII output impedance target to 78,8 Ohm + * - run output impedance calibration + * - set autonegotiation advertise to 1000FD only + */ +struct mii_setupcmd default_88e1518[] = { + { MIICMD_SET, 22, 0x0002 }, + { MIICMD_MODIFY, 21, 0x0030, 0x0030 }, + { MIICMD_MODIFY, 25, 0x0000, 0x0003 }, + { MIICMD_MODIFY, 24, 0x8000, 0x8000 }, + { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 }, + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_MODIFY, 4, 0x0000, 0x01e0 }, + { MIICMD_MODIFY, 9, 0x0200, 0x0300 }, +}; + +/* + * turn off CLK125 for PHY daughterboard + */ +struct mii_setupcmd ch1fix_88e1518[] = { + { MIICMD_SET, 22, 0x0002 }, + { MIICMD_MODIFY, 16, 0x0006, 0x0006 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * perform copper software reset + */ +struct mii_setupcmd swreset_88e1518[] = { + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, + { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 }, +}; + +/* + * special one for 88E1514: + * Force SGMII to Copper mode + */ +struct mii_setupcmd mii_to_copper_88e1514[] = { + { MIICMD_SET, 22, 0x0012 }, + { MIICMD_MODIFY, 20, 0x0001, 0x0007 }, + { MIICMD_MODIFY, 20, 0x8000, 0x8000 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * turn off SGMII auto-negotiation + */ +struct mii_setupcmd sgmii_autoneg_off_88e1518[] = { + { MIICMD_SET, 22, 0x0001 }, + { MIICMD_MODIFY, 0, 0x0000, 0x1000 }, + { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * invert LED2 polarity + */ +struct mii_setupcmd invert_led2_88e1514[] = { + { MIICMD_SET, 22, 0x0003 }, + { MIICMD_MODIFY, 17, 0x0030, 0x0010 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +static int process_setupcmd(const char *bus, unsigned char addr, + struct mii_setupcmd *setupcmd) +{ + int res; + u8 reg = setupcmd->reg; + u16 data = setupcmd->data; + u16 mask = setupcmd->mask; + u32 timeout = setupcmd->timeout; + u16 orig_data; + unsigned long start; + + debug("mii %s:%u reg %2u ", bus, addr, reg); + + switch (setupcmd->token) { + case MIICMD_MODIFY: + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + break; + debug("is %04x. (value %04x mask %04x) ", orig_data, data, + mask); + data = (orig_data & ~mask) | (data & mask); + /* fallthrough */ + case MIICMD_SET: + debug("=> %04x\n", data); + res = miiphy_write(bus, addr, reg, data); + break; + case MIICMD_VERIFY_VALUE: + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + break; + if ((orig_data & mask) != (data & mask)) + res = -1; + debug("(value %04x mask %04x) == %04x? %s\n", data, mask, + orig_data, res ? "FAIL" : "PASS"); + break; + case MIICMD_WAIT_FOR_VALUE: + res = -1; + start = get_timer(0); + while ((res != 0) && (get_timer(start) < timeout)) { + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + continue; + if ((orig_data & mask) != (data & mask)) + res = -1; + } + debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data, + mask, orig_data, res ? "FAIL" : "PASS", + get_timer(start)); + break; + default: + res = -1; + break; + } + + return res; +} + +static int process_setup(const char *bus, unsigned char addr, + struct mii_setupcmd *setupcmd, unsigned int count) +{ + int res = 0; + unsigned int k; + + for (k = 0; k < count; ++k) { + res = process_setupcmd(bus, addr, &setupcmd[k]); + if (res) { + printf("mii cmd %u on bus %s addr %u failed, aborting setup\n", + setupcmd[k].token, bus, addr); + break; + } + } + + return res; +} + +int setup_88e1518(const char *bus, unsigned char addr) +{ + int res; + + res = process_setup(bus, addr, + verify_88e1518, ARRAY_SIZE(verify_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + default_88e1518, ARRAY_SIZE(default_88e1518)); + if (res) + return res; + + if (addr) { + res = process_setup(bus, addr, + ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); + if (res) + return res; + } + + res = process_setup(bus, addr, + swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); + if (res) + return res; + + return 0; +} + +int setup_88e1514(const char *bus, unsigned char addr) +{ + int res; + + res = process_setup(bus, addr, + verify_88e1518, ARRAY_SIZE(verify_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + mii_to_copper_88e1514, + ARRAY_SIZE(mii_to_copper_88e1514)); + if (res) + return res; + + res = process_setup(bus, addr, + sgmii_autoneg_off_88e1518, + ARRAY_SIZE(sgmii_autoneg_off_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + invert_led2_88e1514, + ARRAY_SIZE(invert_led2_88e1514)); + if (res) + return res; + + res = process_setup(bus, addr, + default_88e1518, ARRAY_SIZE(default_88e1518)); + if (res) + return res; + + if (addr) { + res = process_setup(bus, addr, + ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); + if (res) + return res; + } + + res = process_setup(bus, addr, + swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); + if (res) + return res; + + return 0; +} diff --git a/board/gdsys/common/phy.h b/board/gdsys/common/phy.h new file mode 100644 index 0000000000..afbdc65a9e --- /dev/null +++ b/board/gdsys/common/phy.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PHY_H_ +#define _PHY_H_ + +int setup_88e1514(const char *bus, unsigned char addr); +int setup_88e1518(const char *bus, unsigned char addr); + +#endif diff --git a/board/gdsys/dlvision/Kconfig b/board/gdsys/dlvision/Kconfig new file mode 100644 index 0000000000..8db4fbeee5 --- /dev/null +++ b/board/gdsys/dlvision/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DLVISION + +config SYS_BOARD + default "dlvision" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "dlvision" + +endif diff --git a/board/gdsys/dlvision/MAINTAINERS b/board/gdsys/dlvision/MAINTAINERS new file mode 100644 index 0000000000..e4d40f8b98 --- /dev/null +++ b/board/gdsys/dlvision/MAINTAINERS @@ -0,0 +1,6 @@ +DLVISION BOARD +M: Dirk Eibach +S: Maintained +F: board/gdsys/dlvision/ +F: include/configs/dlvision.h +F: configs/dlvision_defconfig diff --git a/board/gdsys/dlvision/Makefile b/board/gdsys/dlvision/Makefile index 126365ba66..755eb4cef9 100644 --- a/board/gdsys/dlvision/Makefile +++ b/board/gdsys/dlvision/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = dlvision.o diff --git a/board/gdsys/gdppc440etx/Kconfig b/board/gdsys/gdppc440etx/Kconfig new file mode 100644 index 0000000000..1f21c89175 --- /dev/null +++ b/board/gdsys/gdppc440etx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GDPPC440ETX + +config SYS_BOARD + default "gdppc440etx" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "gdppc440etx" + +endif diff --git a/board/gdsys/gdppc440etx/MAINTAINERS b/board/gdsys/gdppc440etx/MAINTAINERS new file mode 100644 index 0000000000..cd8d1c6f8e --- /dev/null +++ b/board/gdsys/gdppc440etx/MAINTAINERS @@ -0,0 +1,6 @@ +GDPPC440ETX BOARD +M: Dirk Eibach +S: Maintained +F: board/gdsys/gdppc440etx/ +F: include/configs/gdppc440etx.h +F: configs/gdppc440etx_defconfig diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile index 1d80df8b74..7e3fc384d4 100644 --- a/board/gdsys/gdppc440etx/Makefile +++ b/board/gdsys/gdppc440etx/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = gdppc440etx.o +extra-y += init.o diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index 6ee7764448..04191dff1e 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -6,7 +6,7 @@ * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/gdsys/intip/Kconfig b/board/gdsys/intip/Kconfig new file mode 100644 index 0000000000..479bb1231c --- /dev/null +++ b/board/gdsys/intip/Kconfig @@ -0,0 +1,12 @@ +if TARGET_INTIP + +config SYS_BOARD + default "intip" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "intip" + +endif diff --git a/board/gdsys/intip/MAINTAINERS b/board/gdsys/intip/MAINTAINERS new file mode 100644 index 0000000000..c99d507364 --- /dev/null +++ b/board/gdsys/intip/MAINTAINERS @@ -0,0 +1,7 @@ +INTIP BOARD +M: Dirk Eibach +S: Maintained +F: board/gdsys/intip/ +F: include/configs/intip.h +F: configs/devconcenter_defconfig +F: configs/intip_defconfig diff --git a/board/gdsys/intip/Makefile b/board/gdsys/intip/Makefile index 415ec3298f..2fbc983e3e 100644 --- a/board/gdsys/intip/Makefile +++ b/board/gdsys/intip/Makefile @@ -5,29 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -SOBJS := init.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := intip.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +extra-y += init.o diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S index 5963180941..1fc2a2f3e8 100644 --- a/board/gdsys/intip/init.S +++ b/board/gdsys/intip/init.S @@ -6,7 +6,7 @@ * (C) Copyright 2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index ee6f9e06c3..8d01d8b116 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -206,7 +206,7 @@ int misc_init_r(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) extern void __ft_board_setup(void *blob, bd_t *bd); -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { __ft_board_setup(blob, bd); @@ -215,5 +215,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", "disabled", sizeof("disabled"), 1); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig new file mode 100644 index 0000000000..43e1663d19 --- /dev/null +++ b/board/gdsys/mpc8308/Kconfig @@ -0,0 +1,12 @@ +if TARGET_HRCON + +config SYS_BOARD + default "mpc8308" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "hrcon" + +endif diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS new file mode 100644 index 0000000000..a7853a59df --- /dev/null +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8308 BOARD +M: Dirk Eibach +S: Maintained +F: board/gdsys/mpc8308/ +F: include/configs/hrcon.h +F: configs/hrcon_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile new file mode 100644 index 0000000000..b5dfdbb190 --- /dev/null +++ b/board/gdsys/mpc8308/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mpc8308.o sdram.o +obj-$(CONFIG_HRCON) += hrcon.o diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c new file mode 100644 index 0000000000..e4434b3b6b --- /dev/null +++ b/board/gdsys/mpc8308/hrcon.c @@ -0,0 +1,677 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mpc8308.h" + +#include + +#include "../common/osd.h" +#include "../common/mclink.h" +#include "../common/phy.h" + +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_MUX_CHANNELS 2 + +enum { + UNITTYPE_MAIN_SERVER = 0, + UNITTYPE_MAIN_USER = 1, + UNITTYPE_VIDEO_SERVER = 2, + UNITTYPE_VIDEO_USER = 3, +}; + +enum { + UNITTYPEPCB_DVI = 0, + UNITTYPEPCB_DP_165 = 1, + UNITTYPEPCB_DP_300 = 2, + UNITTYPEPCB_HDMI = 3, +}; + +enum { + HWVER_100 = 0, + HWVER_110 = 1, +}; + +enum { + FPGA_HWVER_200 = 0, + FPGA_HWVER_210 = 1, +}; + +enum { + COMPRESSION_NONE = 0, + COMPRESSION_TYPE1_DELTA = 1, + COMPRESSION_TYPE1_TYPE2_DELTA = 3, +}; + +enum { + AUDIO_NONE = 0, + AUDIO_TX = 1, + AUDIO_RX = 2, + AUDIO_RXTX = 3, +}; + +enum { + SYSCLK_147456 = 0, +}; + +enum { + RAM_DDR2_32 = 0, + RAM_DDR3_32 = 1, +}; + +enum { + CARRIER_SPEED_1G = 0, + CARRIER_SPEED_2_5G = 1, +}; + +enum { + MCFPGA_DONE = 1 << 0, + MCFPGA_INIT_N = 1 << 1, + MCFPGA_PROGRAM_N = 1 << 2, + MCFPGA_UPDATE_ENABLE_N = 1 << 3, + MCFPGA_RESET_N = 1 << 4, +}; + +enum { + GPIO_MDC = 1 << 14, + GPIO_MDIO = 1 << 15, +}; + +unsigned int mclink_fpgacount; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) +{ + int res; + + switch (fpga) { + case 0: + out_le16(reg, data); + break; + default: + res = mclink_send(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_send reg %02lx data %04x returned %d\n", + regoff, data, res); + return res; + } + break; + } + + return 0; +} + +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) +{ + int res; + + switch (fpga) { + case 0: + *data = in_le16(reg); + break; + default: + if (fpga > mclink_fpgacount) + return -EINVAL; + res = mclink_receive(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_receive reg %02lx returned %d\n", + regoff, res); + return res; + } + } + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + bool hw_type_cat = pca9698_get_value(0x20, 20); + + puts("Board: "); + + printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void print_fpga_info(unsigned int fpga, bool rgmii2_present) +{ + u16 versions; + u16 fpga_version; + u16 fpga_features; + unsigned unit_type; + unsigned unit_type_pcb_video; + unsigned hardware_version; + unsigned feature_compression; + unsigned feature_osd; + unsigned feature_audio; + unsigned feature_sysclock; + unsigned feature_ramconfig; + unsigned feature_carrier_speed; + unsigned feature_carriers; + unsigned feature_video_channels; + + FPGA_GET_REG(fpga, versions, &versions); + FPGA_GET_REG(fpga, fpga_version, &fpga_version); + FPGA_GET_REG(fpga, fpga_features, &fpga_features); + + unit_type = (versions & 0xf000) >> 12; + unit_type_pcb_video = (versions & 0x01c0) >> 6; + feature_compression = (fpga_features & 0xe000) >> 13; + feature_osd = fpga_features & (1<<11); + feature_audio = (fpga_features & 0x0600) >> 9; + feature_sysclock = (fpga_features & 0x0180) >> 7; + feature_ramconfig = (fpga_features & 0x0060) >> 5; + feature_carrier_speed = fpga_features & (1<<4); + feature_carriers = (fpga_features & 0x000c) >> 2; + feature_video_channels = fpga_features & 0x0003; + + switch (unit_type) { + case UNITTYPE_MAIN_USER: + printf("Mainchannel"); + break; + + case UNITTYPE_VIDEO_USER: + printf("Videochannel"); + break; + + default: + printf("UnitType %d(not supported)", unit_type); + break; + } + + if (unit_type == UNITTYPE_MAIN_USER) { + hardware_version = + (!!pca9698_get_value(0x20, 24) << 0) + | (!!pca9698_get_value(0x20, 25) << 1) + | (!!pca9698_get_value(0x20, 26) << 2) + | (!!pca9698_get_value(0x20, 27) << 3) + | (!!pca9698_get_value(0x20, 28) << 4); + switch (hardware_version) { + case HWVER_100: + printf(" HW-Ver 1.00,"); + break; + + case HWVER_110: + printf(" HW-Ver 1.10,"); + break; + + default: + printf(" HW-Ver %d(not supported),", + hardware_version); + break; + } + if (rgmii2_present) + printf(" RGMII2,"); + } + + if (unit_type == UNITTYPE_VIDEO_USER) { + hardware_version = versions & 0x000f; + switch (hardware_version) { + case FPGA_HWVER_200: + printf(" HW-Ver 2.00,"); + break; + + case FPGA_HWVER_210: + printf(" HW-Ver 2.10,"); + break; + + default: + printf(" HW-Ver %d(not supported),", + hardware_version); + break; + } + } + + switch (unit_type_pcb_video) { + case UNITTYPEPCB_DVI: + printf(" DVI,"); + break; + + case UNITTYPEPCB_DP_165: + printf(" DP 165MPix/s,"); + break; + + case UNITTYPEPCB_DP_300: + printf(" DP 300MPix/s,"); + break; + + case UNITTYPEPCB_HDMI: + printf(" HDMI,"); + break; + } + + printf(" FPGA V %d.%02d\n features:", + fpga_version / 100, fpga_version % 100); + + + switch (feature_compression) { + case COMPRESSION_NONE: + printf(" no compression"); + break; + + case COMPRESSION_TYPE1_DELTA: + printf(" type1-deltacompression"); + break; + + case COMPRESSION_TYPE1_TYPE2_DELTA: + printf(" type1-deltacompression, type2-inlinecompression"); + break; + + default: + printf(" compression %d(not supported)", feature_compression); + break; + } + + printf(", %sosd", feature_osd ? "" : "no "); + + switch (feature_audio) { + case AUDIO_NONE: + printf(", no audio"); + break; + + case AUDIO_TX: + printf(", audio tx"); + break; + + case AUDIO_RX: + printf(", audio rx"); + break; + + case AUDIO_RXTX: + printf(", audio rx+tx"); + break; + + default: + printf(", audio %d(not supported)", feature_audio); + break; + } + + puts(",\n "); + + switch (feature_sysclock) { + case SYSCLK_147456: + printf("clock 147.456 MHz"); + break; + + default: + printf("clock %d(not supported)", feature_sysclock); + break; + } + + switch (feature_ramconfig) { + case RAM_DDR2_32: + printf(", RAM 32 bit DDR2"); + break; + + case RAM_DDR3_32: + printf(", RAM 32 bit DDR3"); + break; + + default: + printf(", RAM %d(not supported)", feature_ramconfig); + break; + } + + printf(", %d carrier(s) %s", feature_carriers, + feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); + + printf(", %d video channel(s)\n", feature_video_channels); +} + +int last_stage_init(void) +{ + int slaves; + unsigned int k; + unsigned int mux_ch; + unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; + u16 fpga_features; + bool hw_type_cat = pca9698_get_value(0x20, 20); + bool ch0_rgmii2_present = false; + + FPGA_GET_REG(0, fpga_features, &fpga_features); + + /* Turn on Parade DP501 */ + pca9698_direction_output(0x20, 10, 1); + + ch0_rgmii2_present = !pca9698_get_value(0x20, 30); + + /* wait for FPGA done */ + for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { + unsigned int ctr = 0; + + if (i2c_probe(mclink_controllers[k])) + continue; + + while (!(pca953x_get_val(mclink_controllers[k]) + & MCFPGA_DONE)) { + udelay(100000); + if (ctr++ > 5) { + printf("no done for mclink_controller %d\n", k); + break; + } + } + } + + if (hw_type_cat) { + miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, + bb_miiphy_write); + for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { + if ((mux_ch == 1) && !ch0_rgmii2_present) + continue; + + setup_88e1514(bb_miiphy_buses[0].name, mux_ch); + } + } + + /* give slave-PLLs and Parade DP501 some time to be up and running */ + udelay(500000); + + mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; + slaves = mclink_probe(); + mclink_fpgacount = 0; + + print_fpga_info(0, ch0_rgmii2_present); + osd_probe(0); + + if (slaves <= 0) + return 0; + + mclink_fpgacount = slaves; + + for (k = 1; k <= slaves; ++k) { + FPGA_GET_REG(k, fpga_features, &fpga_features); + + print_fpga_info(k, false); + osd_probe(k); + if (hw_type_cat) { + miiphy_register(bb_miiphy_buses[k].name, + bb_miiphy_read, bb_miiphy_write); + setup_88e1514(bb_miiphy_buses[k].name, 0); + } + } + + return 0; +} + +/* + * provide access to fpga gpios (for I2C bitbang) + * (these may look all too simple but make iocon.h much more readable) + */ +void fpga_gpio_set(unsigned int bus, int pin) +{ + FPGA_SET_REG(bus, gpio.set, pin); +} + +void fpga_gpio_clear(unsigned int bus, int pin) +{ + FPGA_SET_REG(bus, gpio.clear, pin); +} + +int fpga_gpio_get(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus, gpio.read, &val); + + return val & pin; +} + +void mpc8308_init(void) +{ + pca9698_direction_output(0x20, 4, 1); +} + +void mpc8308_set_fpga_reset(unsigned state) +{ + pca9698_set_value(0x20, 4, state ? 0 : 1); +} + +void mpc8308_setup_hw(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* + * set "startup-finished"-gpios + */ + setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); + setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); +} + +int mpc8308_get_fpga_done(unsigned fpga) +{ + return pca9698_get_value(0x20, 19); +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + + /* Enable cache snooping in eSDHC system configuration register */ + out_be32(&sysconf->sdhccr, 0x02000000); + + return fsl_esdhc_mmc_init(bd); +} +#endif + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0 }; + + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(1, pcie_reg); +} + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif + +/* + * FPGA MII bitbang implementation + */ + +struct fpga_mii { + unsigned fpga; + int mdio; +} fpga_mii[] = { + { 0, 1}, + { 1, 1}, + { 2, 1}, + { 3, 1}, +}; + +static int mii_dummy_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int mii_mdio_active(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (fpga_mii->mdio) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + return 0; +} + +static int mii_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + + return 0; +} + +static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + fpga_mii->mdio = v; + + return 0; +} + +static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + u16 gpio; + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); + + *v = ((gpio & GPIO_MDIO) != 0); + + return 0; +} + +static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); + + return 0; +} + +static int mii_delay(struct bb_miiphy_bus *bus) +{ + udelay(1); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "board0", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[0], + }, + { + .name = "board1", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[1], + }, + { + .name = "board2", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[2], + }, + { + .name = "board3", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[3], + }, +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c new file mode 100644 index 0000000000..4338a33126 --- /dev/null +++ b/board/gdsys/mpc8308/mpc8308.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "mpc8308.h" +#include + +#define REFLECTION_TESTPATTERN 0xdede +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) + +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI +#define REFLECTION_TESTREG reflection_low +#else +#define REFLECTION_TESTREG reflection_high +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int get_fpga_state(unsigned dev) +{ + return gd->arch.fpga_state[dev]; +} + +void print_fpga_state(unsigned dev) +{ + if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) + puts(" Waiting for FPGA-DONE timed out.\n"); + if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) + puts(" FPGA reflection test failed.\n"); +} + +int board_early_init_f(void) +{ + unsigned k; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] = 0; + + return 0; +} + +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] = 0; + + /* + * reset FPGA + */ + mpc8308_init(); + + mpc8308_set_fpga_reset(1); + + mpc8308_setup_hw(); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ctr = 0; + while (!mpc8308_get_fpga_done(k)) { + udelay(100000); + if (ctr++ > 5) { + gd->arch.fpga_state[k] |= + FPGA_STATE_DONE_FAILED; + break; + } + } + } + + udelay(10); + + mpc8308_set_fpga_reset(0); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + /* + * wait for fpga out of reset + */ + ctr = 0; + while (1) { + u16 val; + + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); + + FPGA_GET_REG(k, REFLECTION_TESTREG, &val); + if (val == REFLECTION_TESTPATTERN_INV) + break; + + udelay(100000); + if (ctr++ > 5) { + gd->arch.fpga_state[k] |= + FPGA_STATE_REFLECTION_FAILED; + break; + } + } + } + + return 0; +} diff --git a/board/gdsys/mpc8308/mpc8308.h b/board/gdsys/mpc8308/mpc8308.h new file mode 100644 index 0000000000..dc07d564eb --- /dev/null +++ b/board/gdsys/mpc8308/mpc8308.h @@ -0,0 +1,10 @@ +#ifndef __MPC8308_H_ +#define __MPC8308_H_ + +/* functions to be provided by board implementation */ +void mpc8308_init(void); +void mpc8308_set_fpga_reset(unsigned state); +void mpc8308_setup_hw(void); +int mpc8308_get_fpga_done(unsigned fpga); + +#endif /* __MPC8308_H_ */ diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c new file mode 100644 index 0000000000..0fce8cfbab --- /dev/null +++ b/board/gdsys/mpc8308/sdram.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * Authors: Nick.Spence@freescale.com + * Wilson.Lo@freescale.com + * scottwood@freescale.com + * + * This files is mostly identical to the original from + * board\freescale\mpc8315erdb\sdram.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + + /* Currently we use only one CS, so disable the other bank. */ + out_be32(&im->ddr.cs_config[1], 0); + + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + sync(); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + sync(); + + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); +} + +phys_size_t initdram(int board_type) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM */ + msize = fixed_sdram(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig new file mode 100644 index 0000000000..8514d086b9 --- /dev/null +++ b/board/gdsys/p1022/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CONTROLCENTERD + +config SYS_BOARD + default "p1022" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "controlcenterd" + +endif diff --git a/board/gdsys/p1022/MAINTAINERS b/board/gdsys/p1022/MAINTAINERS new file mode 100644 index 0000000000..5119fbb142 --- /dev/null +++ b/board/gdsys/p1022/MAINTAINERS @@ -0,0 +1,9 @@ +P1022 BOARD +M: Dirk Eibach +S: Maintained +F: board/gdsys/p1022/ +F: include/configs/controlcenterd.h +F: configs/controlcenterd_36BIT_SDCARD_defconfig +F: configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig +F: configs/controlcenterd_TRAILBLAZER_defconfig +F: configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig diff --git a/board/gdsys/p1022/Makefile b/board/gdsys/p1022/Makefile index 17f602f7ef..6e02447987 100644 --- a/board/gdsys/p1022/Makefile +++ b/board/gdsys/p1022/Makefile @@ -7,31 +7,9 @@ # any later version. # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -# COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += ddr.o -COBJS-y += tlb.o -COBJS-y += sdhc_boot.o -COBJS-$(CONFIG_CONTROLCENTERD) += controlcenterd.o controlcenterd-id.o - -COBJS-$(CONFIG_FSL_DIU_FB) += diu.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += law.o +obj-y += ddr.o +obj-y += tlb.o +obj-y += sdhc_boot.o +obj-$(CONFIG_CONTROLCENTERD) += controlcenterd.o controlcenterd-id.o +obj-$(CONFIG_FSL_DIU_FB) += diu.o diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index 3fca3c53b2..11d075c385 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include @@ -86,6 +86,11 @@ enum { ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60, }; +enum { + I2C_SOC_0 = 0, + I2C_SOC_1 = 1, +}; + struct key_program { uint32_t magic; uint32_t code_crc; @@ -231,7 +236,7 @@ static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) tmp_buf); if (!n) goto failure; - result = min(size, blk_len - ofs); + result = min(size, (int)(blk_len - ofs)); memcpy(dst, tmp_buf + ofs, result); dst += result; size -= result; @@ -731,7 +736,8 @@ do_bin_func: src_buf = buf; for (ptr = (uint8_t *)src_buf, i = 20; i > 0; i -= data_size, ptr += data_size) - memcpy(ptr, data, min(i, data_size)); + memcpy(ptr, data, + min_t(size_t, i, data_size)); } } bin_func(dst_reg->digest, src_buf, 20); @@ -926,11 +932,12 @@ static struct key_program *load_key_chunk(const char *ifname, struct key_program header; uint32_t crc; uint8_t buf[12]; - int i; + loff_t i; if (fs_set_blk_dev(ifname, dev_part_str, fs_type)) goto failure; - i = fs_read(path, (ulong)buf, 0, 12); + if (fs_read(path, (ulong)buf, 0, 12, &i) < 0) + goto failure; if (i < 12) goto failure; header.magic = get_unaligned_be32(buf); @@ -945,8 +952,9 @@ static struct key_program *load_key_chunk(const char *ifname, goto failure; if (fs_set_blk_dev(ifname, dev_part_str, fs_type)) goto failure; - i = fs_read(path, (ulong)result, 0, - sizeof(struct key_program) + header.code_size); + if (fs_read(path, (ulong)result, 0, + sizeof(struct key_program) + header.code_size, &i) < 0) + goto failure; if (i <= 0) goto failure; *result = header; @@ -1037,7 +1045,7 @@ static int second_stage_init(void) const char *image_path = "/ccdm.itb"; char *mac_path = NULL; ulong image_addr; - size_t image_size; + loff_t image_size; uint32_t err; printf("CCDM S2\n"); @@ -1079,10 +1087,11 @@ static int second_stage_init(void) image_addr = (ulong)get_image_location(); if (fs_set_blk_dev("mmc", mmcdev, FS_TYPE_EXT)) goto failure; - image_size = fs_read(image_path, image_addr, 0, 0); + if (fs_read(image_path, image_addr, 0, 0, &image_size) < 0) + goto failure; if (image_size <= 0) goto failure; - printf("CCDM image found on %s, %d bytes\n", mmcdev, image_size); + printf("CCDM image found on %s, %lld bytes\n", mmcdev, image_size); hmac_blob = load_key_chunk("mmc", mmcdev, FS_TYPE_EXT, mac_path); if (!hmac_blob) { @@ -1156,7 +1165,7 @@ static void ccdm_hang(void) int j; #endif - I2C_SET_BUS(0); + I2C_SET_BUS(I2C_SOC_0); pca9698_direction_output(0x22, 0, 0); /* Finder */ pca9698_direction_output(0x22, 4, 0); /* Status */ @@ -1189,8 +1198,8 @@ int startup_ccdm_id_module(void) int result = 0; unsigned int orig_i2c_bus; - orig_i2c_bus = I2C_GET_BUS(); - I2C_SET_BUS(1); + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(I2C_SOC_1); /* goto end; */ @@ -1216,7 +1225,7 @@ int startup_ccdm_id_module(void) failure: result = 1; end: - I2C_SET_BUS(orig_i2c_bus); + i2c_set_bus_num(orig_i2c_bus); if (result) ccdm_hang(); diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index 81c22bc94c..64d90dd3fd 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -221,11 +221,7 @@ void hw_watchdog_reset(void) #ifdef CONFIG_TRAILBLAZER int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int rcode = 0; - - if (run_command(getenv("bootcmd"), flag) < 0) - rcode = 1; - return rcode; + return run_command(getenv("bootcmd"), flag); } int board_early_init_r(void) @@ -330,7 +326,7 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -347,6 +343,8 @@ void ft_board_setup(void *blob, bd_t *bd) #endif FT_FSL_PCI_SETUP; + + return 0; } #endif @@ -386,9 +384,9 @@ static void hydra_initialize(void) fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); - versions = readl(fpga->versions); - fpga_version = readl(fpga->fpga_version); - fpga_features = readl(fpga->fpga_features); + versions = readl(&fpga->versions); + fpga_version = readl(&fpga->fpga_version); + fpga_features = readl(&fpga->fpga_features); hardware_version = versions & 0xf; feature_uart_channels = (fpga_features >> 6) & 0x1f; diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c index 4a652de430..7596736bfd 100644 --- a/board/gdsys/p1022/ddr.c +++ b/board/gdsys/p1022/ddr.c @@ -12,8 +12,8 @@ #include #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c index e4323181fc..fd0e910d7b 100644 --- a/board/gdsys/p1022/sdhc_boot.c +++ b/board/gdsys/p1022/sdhc_boot.c @@ -32,7 +32,7 @@ #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50 -int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr) +int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) { u8 *tmp_buf; u32 blklen, code_offset, code_len, n; diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile deleted file mode 100644 index 03551852e9..0000000000 --- a/board/gen860t/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o beeper.o fpga.o ioport.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/gen860t/README b/board/gen860t/README deleted file mode 100644 index 3ef8ae196e..0000000000 --- a/board/gen860t/README +++ /dev/null @@ -1,131 +0,0 @@ -This directory contains board specific code for a generic MPC860T based -embedded computer, called 'GEN860T'. The design is generic in the sense that -common, readily available components are used and that the architecture of the -system is relatively straightforward: - - One eight bit wide boot (FLASH) memory - 32 bit main memory using SDRAM - DOC 2000+ - Ethernet PHY - Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC. - Some other miscellaneous peripherals - -NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this -port. I guess the computer is not as generic as I first said 8) However, -these extras can be safely ignored. - -Given the GEN860T files, it should be pretty easy to reverse engineer the -hardware configuration, if that's useful to you. Hopefully, this code will -be useful to someone as a basis for a port to a new system or as a head start -on a custom design. If you end up using any of this, I would appreciate -hearing from you, especially if you discover bugs or find ways to improve the -quality of this U-Boot port. - -Here are the salient features of the system: -Clock : 33.3 Mhz oscillator -Processor core frequency : 66.6 Mhz if in 1:2:1 mode; can also run 1:1 -Bus frequency : 33.3 Mhz - -Main memory: - Type : SDRAM - Width : 32 bits - Size : 64 mibibytes - Chip : Two Micron MT48LC16M16A2TG-7E - CS : MPC860T CS1*/UPMA - UPMA CONNECTIONS: - SDRAM A10 : GPLA0* - SDRAM CAS* : GPLA2* - SDRAM WE* : GPLA3* - SDRAM RAS* : GPLA4* - -Boot memory: - Type : FLASH - Width : 8 bits - Size : 16 mibibytes - Chip : One Intel 28F128J3A (StrataFlash) - CS : MPC860T CS0*/GPCM (this is the "boot" chip select) - -EEPROM memory: - Type : Serial I2C EEPROM - Width : 8 bits - Size : 32 kibibytes - Chip : One Atmel AT25C256 - CS : 0x50 (external I2C address pins on device are tied to GND) - -Filesystem memory: - Type : NAND FLASH (Toshiba) - Width : 8 bits (i.e. interface to DOC is 8 bits) - Size : 32 mibibytes - Chip : One DiskOnCHip Millenium Plus (DOC 2000+) - CS : MPC860T CS2*/GPCM - -Network support: - MAC : MPC86OT FEC (Fast Ethernet Controller) - PHY : Intel LXT971A - MII Addr: 0x0 (hardwired on the board) - MII IRQ : - -Console: - RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter) - -Real Time Clock: - Type : Low power, I2C interface - Chip : Maxim DS1337 - CS : Address 0x68 on I2C bus - - The MPC860T's internal RTC has a defect in Mask rev D that increases - the current drain on the KAPWR line to 10 mA. Since this is an - unreasonable amount of current draw for a RTC, and Motorola does not - plan to fix this in future mask revisions, a serial (I2C) RTC that - works has been included instead. NOTE that the DS1337 can be - configured to output a 32768 Hz clock while the main power is on. - This clock output has been routed to the MPC860T's EXTAL pin to allow - the internal RTC to be used. NOTE also that due to yet another - defect in the rev D mask, the RTC does not operate reliably when the - internal RTC divisor is set to use a 32768 Hz reference. So just use - the I2C RTC. - -Miscellaneous: - Xilinx Virtex FPGA on CS3*/GPCM. - Virtex FPGA slave SelectMap interface on cs4*/UPMB. - Mil-Std 1553 databus interface on CS5*/GPCM. - Audio sounder (beeper) with digital volume control connected to SPKROUT. - -SC variant: - A reduced-feature version of the GEN860T port is also supported: GEN860T_SC. - The 'SC' variant only provides support for the Virtex FPGA, SDRAM main - memory, EEPROM and flash memory. The system clock frequency is reduced - to 24 MHz. - -Issues: - The DOC 2000+ returns 0x40 as its device ID when probed using the method - desxribed in the DOC datasheet. Unfortunately, the U-Boot DOC driver - does not recognize this device. As of this writing, it seems that MTD - does not support the DOC 2000+ either. - -Status: - Everything appears to work except DOC support. As of this writing, - David Woodhouse has stated on the MTD mailing list that he has no - knowledge of the DOC Millineum Plus and therfore there is no support - in MTD for this device. I wish I had known this sooner :( - -The GEN860T board specific files and configuration is based on the work -of others who have contributed to U-Boot. The copyright and license notices -of these authors have been retained wherever their code has been reused. -All new code to support the GEN860T board is: - - (C) Copyright 2001-2003 - Keith Outwater (keith_outwater@mvis.com) - -and the following license applies: - -SPDX-License-Identifier: GPL-2.0+ - -Thanks to Wolfgang Denk for a great software package and to everyone -who contributed to its development. - -Keith Outwater -Sr. Staff Engineer -Microvision, Inc. - - diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c deleted file mode 100644 index 0bebca98b1..0000000000 --- a/board/gen860t/beeper.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2002 - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * Basic beeper support for the GEN860T board. The GEN860T includes - * an audio sounder driven by a Phillips TDA8551 amplifier. The - * TDA8551 features a digital volume control which uses a "trinary" - * input (high/high-Z/low) to set volume. The 860's SPKROUT pin - * drives the amplifier input. - */ - -/* - * Initialize beeper-related hardware. Initialize timer 1 for use with - * the beeper. Use 66 MHz internal clock with prescale of 33 to get - * 1 uS period per count. - * FIXME: we should really compute the prescale based on the reported - * core clock frequency. - */ -void init_beeper (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1; - immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK) - | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN; - immap->im_cpmtimer.cpmt_tcn1 = 0; - immap->im_cpmtimer.cpmt_ter1 = 0xffff; - immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1; -} - -/* - * Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit - * is mostly arbitrary, but the beeper isn't really much good beyond this - * frequency. - */ -void set_beeper_frequency (uint frequency) -{ -#define FREQ_LIMIT 2500 - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Compute timer ticks given desired frequency. The timer is set up - * to count 0.5 uS per tick and it takes two ticks per cycle (Hz). - */ - if (frequency > FREQ_LIMIT) - frequency = FREQ_LIMIT; - frequency = 1000000 / frequency; - immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency; -} - -/* - * Turn the beeper on - */ -void beeper_on (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1; -} - -/* - * Turn the beeper off - */ -void beeper_off (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1; -} - -/* - * Increase or decrease the beeper volume. Volume can be set - * from off to full in 64 steps. To increase volume, the output - * pin is actively driven high, then returned to tristate. - * To decrease volume, output a low on the port pin (no need to - * change pin mode to tristate) then output a high to go back to - * tristate. - */ -void set_beeper_volume (int steps) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - int i; - - if (steps >= 0) { - for (i = 0; i < (steps >= 64 ? 64 : steps); i++) { - immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19); - udelay (1); - immap->im_cpm.cp_pbodr |= (0x80000000 >> 19); - udelay (1); - } - } else { - for (i = 0; i > (steps <= -64 ? -64 : steps); i--) { - immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19); - udelay (1); - immap->im_cpm.cp_pbdat |= (0x80000000 >> 19); - udelay (1); - } - } -} - -/* - * Check the environment to see if the beeper needs beeping. - * Controlled by a sequence of the form: - * freq/delta volume/on time/off time;... where: - * freq = frequency in Hz (0 - 2500) - * delta volume = volume steps up or down (-64 <= vol <= 64) - * on time = time in mS - * off time = time in mS - * - * Return 1 on success, 0 on failure - */ -int do_beeper (char *sequence) -{ -#define DELIMITER ';' - - int args[4]; - int i; - int val; - char *p = sequence; - char *tp; - - /* - * Parse the control sequence. This is a really simple parser - * without any real error checking. You can probably blow it - * up really easily. - */ - if (*p == '\0' || !isdigit (*p)) { - printf ("%s:%d: null or invalid string (%s)\n", - __FILE__, __LINE__, p); - return 0; - } - - i = 0; - while (*p != '\0') { - while (*p != DELIMITER) { - if (i > 3) - i = 0; - val = (int) simple_strtol (p, &tp, 0); - if (tp == p) { - printf ("%s:%d: no digits or bad format\n", - __FILE__, __LINE__); - return 0; - } else { - args[i] = val; - } - - i++; - if (*tp == DELIMITER) - p = tp; - else - p = ++tp; - } - p++; - - /* - * Well, we got something that has a chance of being correct - */ -#if 0 - for (i = 0; i < 4; i++) { - printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, - args[i]); - } - printf ("\n"); -#endif - set_beeper_frequency (args[0]); - set_beeper_volume (args[1]); - beeper_on (); - udelay (1000 * args[2]); - beeper_off (); - udelay (1000 * args[3]); - } - return 1; -} diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h deleted file mode 100644 index 0734fcab0f..0000000000 --- a/board/gen860t/beeper.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2002 - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void init_beeper(void); -void set_beeper_frequency(uint frequency); -void beeper_on(void); -void beeper_off(void); -void set_beeper_volume(int steps); -int do_beeper(char *sequence); diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c deleted file mode 100644 index 8433d5d2cf..0000000000 --- a/board/gen860t/flash.c +++ /dev/null @@ -1,628 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvsi.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/* - * Use buffered writes to flash by default - they are about 32x faster than - * single byte writes. - */ -#ifndef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#define CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#endif - -/* - * Max time to wait (in mS) for flash device to allocate a write buffer. - */ -#ifndef CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT -#define CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT 100 -#endif - -/* - * These functions support a single Intel StrataFlash device (28F128J3A) - * in byte mode only!. The flash routines are very basic and simple - * since there isn't really any remapping necessary. - */ - -/* - * Intel SCS (Scalable Command Set) command definitions - * (taken from 28F128J3A datasheet) - */ -#define SCS_READ_CMD 0xff -#define SCS_READ_ID_CMD 0x90 -#define SCS_QUERY_CMD 0x98 -#define SCS_READ_STATUS_CMD 0x70 -#define SCS_CLEAR_STATUS_CMD 0x50 -#define SCS_WRITE_BUF_CMD 0xe8 -#define SCS_PROGRAM_CMD 0x40 -#define SCS_BLOCK_ERASE_CMD 0x20 -#define SCS_BLOCK_ERASE_RESUME_CMD 0xd0 -#define SCS_PROGRAM_RESUME_CMD 0xd0 -#define SCS_BLOCK_ERASE_SUSPEND_CMD 0xb0 -#define SCS_SET_BLOCK_LOCK_CMD 0x60 -#define SCS_CLR_BLOCK_LOCK_CMD 0x60 - -/* - * SCS status/extended status register bit definitions - */ -#define SCS_SR7 0x80 -#define SCS_XSR7 0x80 - -/*---------------------------------------------------------------------*/ -#if 0 -#define DEBUG_FLASH -#endif - -#ifdef DEBUG_FLASH -#define PRINTF(fmt,args...) printf(fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data8 (flash_info_t *info, ulong dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * Initialize the flash memory. - */ -unsigned long -flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - for (i= 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* - * The gen860t board only has one FLASH memory device, so the - * FLASH Bank configuration is done statically. - */ - PRINTF("\n## Get flash bank 1 size @ 0x%08x\n", FLASH_BASE0_PRELIM); - size_b0 = flash_get_size((vu_char *)FLASH_BASE0_PRELIM, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - flash_info[0].flash_id,size_b0, size_b0 << 20); - } - - PRINTF("## Before remap:\n" - " BR0: 0x%08x OR0: 0x%08x\n BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* - * Remap FLASH according to real size - */ - memctl->memc_or0 |= (-size_b0 & 0xFFFF8000); - memctl->memc_br0 |= (CONFIG_SYS_FLASH_BASE & BR_BA_MSK); - - PRINTF("## After remap:\n" - " BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); - - /* - * Re-do sizing to get full correct info - */ - size_b0 = flash_get_size ((vu_char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* - * Monitor protection is ON by default - */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* - * Environment protection ON by default - */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0); - return (size_b0); -} - - -/*----------------------------------------------------------------------- - * Fill in the FLASH offset table - */ -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 1024 * 128; - } - return; - - default: - printf ("Don't know sector offsets for FLASH" - " type 0x%lx\n", info->flash_id); - return; - } -} - - -/*----------------------------------------------------------------------- - * Display FLASH device info - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("Intel "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1024 * 1024)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - * Get size and other information for a FLASH device. - * NOTE: The following code cannot be run from FLASH! - */ -static -ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ -#define NO_FLASH 0 - - vu_char value[2]; - - /* - * Try to read the manufacturer ID - */ - addr[0] = SCS_READ_CMD; - addr[0] = SCS_READ_ID_CMD; - value[0] = addr[0]; - value[1] = addr[2]; - addr[0] = SCS_READ_CMD; - - PRINTF("Manuf. ID @ 0x%08lx: 0x%02x\n", (ulong)addr, value[0]); - switch (value[0]) { - case (INTEL_MANUFACT & 0xff): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (NO_FLASH); - } - - /* - * Read the device ID - */ - PRINTF("Device ID @ 0x%08lx: 0x%02x\n", (ulong)(&addr[2]), value[1]); - switch (value[1]) { - case (INTEL_ID_28F128J3A & 0xff): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 16 * 1024 * 1024; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (NO_FLASH); - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - * Erase the specified sectors in the specified FLASH device - */ -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* - * Start erase on unprotected sectors - */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (uchar *)(info->start[sect]); - vu_char status; - - /* - * Disable interrupts which might cause a timeout - */ - flag = disable_interrupts(); - - *addr = SCS_CLEAR_STATUS_CMD; - *addr = SCS_BLOCK_ERASE_CMD; - *addr = SCS_BLOCK_ERASE_RESUME_CMD; - - /* - * Re-enable interrupts if necessary - */ - if (flag) - enable_interrupts(); - - /* - * Wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = SCS_BLOCK_ERASE_SUSPEND_CMD; - *addr = SCS_READ_CMD; - return 1; - } - - /* - * Show that we're waiting - */ - if ((now - last) > 1000) { /* 1 second */ - putc ('.'); - last = now; - } - } - *addr = SCS_READ_CMD; - } - } - printf (" done\n"); - return 0; -} - - -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -/* - * Allocate a flash buffer, fill it with data and write it to the flash. - * 0 - OK - * 1 - Timeout on buffer request - * - * NOTE: After the last call to this function, WSM status needs to be checked! - */ -static int -write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p, - uint count) -{ - vu_char *block_addr_p = NULL; - vu_char *start_addr_p = NULL; - ulong blocksize = info_p->size / (ulong)info_p->sector_count; - - int i; - uint time = get_timer(0); - - PRINTF("%s:%d: src: 0x%p dest: 0x%p count: %d\n", - __FUNCTION__, __LINE__, src_p, dest_p, count); - - /* - * What block are we in? We already know that the source address is - * in the flash address range, but we also can't cross a block boundary. - * We assume that the block does not cross a boundary (we'll check before - * calling this function). - */ - for (i = 0; i < info_p->sector_count; ++i) { - if ( ((ulong)dest_p >= info_p->start[i]) && - ((ulong)dest_p < (info_p->start[i] + blocksize)) ) { - PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n", - __FUNCTION__, __LINE__, dest_p, i, info_p->start[i]); - block_addr_p = (vu_char *)info_p->start[i]; - break; - } - } - - /* - * Request a buffer - */ - *block_addr_p = SCS_WRITE_BUF_CMD; - while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) { - if (get_timer(time) > CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT) { - PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, - CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT); - return 1; - } - *block_addr_p = SCS_WRITE_BUF_CMD; - } - - /* - * Fill the buffer with data - */ - start_addr_p = dest_p; - *block_addr_p = count - 1; /* flash device wants count - 1 */ - PRINTF("%s:%d: Fill buffer at block addr 0x%p\n", - __FUNCTION__, __LINE__, block_addr_p); - for (i = 0; i < count; i++) { - *start_addr_p++ = *src_p++; - } - - /* - * Flush buffer to flash - */ - *block_addr_p = SCS_PROGRAM_RESUME_CMD; -#if 1 - time = get_timer(0); - while ((*block_addr_p & SCS_SR7) != SCS_SR7) { - if (get_timer(time) > CONFIG_SYS_FLASH_WRITE_TOUT) { - PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, CONFIG_SYS_FLASH_WRITE_TOUT); - return 1; - } - } - -#endif - return 0; -} -#endif - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ -int -write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count) -{ - int rc = 0; -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#define FLASH_WRITE_BUF_SIZE 0x00000020 /* 32 bytes */ - int i; - uint bufs; - ulong buf_count; - vu_char *sp; - vu_char *dp; -#else - ulong wp; -#endif - - PRINTF("\n%s:%d: src: 0x%.8lx dest: 0x%.8lx size: %d (0x%.8lx)\n", - __FUNCTION__, __LINE__, (ulong)src_p, addr, (uint)count, count); - - if (info_p->flash_id == FLASH_UNKNOWN) { - return 4; - } - -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER - sp = src_p; - dp = (uchar *)addr; - - /* - * For maximum performance, we want to align the start address to - * the beginning of a write buffer boundary (i.e. A4-A0 of the - * start address = 0). See how many bytes are required to get to a - * write-buffer-aligned address. If that number is non-zero, do - * non buffered writes of the non-aligned data. By doing non-buffered - * writes, we avoid the problem of crossing a block (sector) boundary - * with buffered writes. - */ - buf_count = FLASH_WRITE_BUF_SIZE - (addr & (FLASH_WRITE_BUF_SIZE - 1)); - if (buf_count == FLASH_WRITE_BUF_SIZE) { /* already on a boundary */ - buf_count = 0; - } - if (buf_count > count) { /* not a full buffers worth of data to write */ - buf_count = count; - } - count -= buf_count; - - PRINTF("%s:%d: Write buffer alignment count = %ld\n", - __FUNCTION__, __LINE__, buf_count); - while (buf_count-- >= 1) { - if ((rc = write_data8(info_p, (ulong)dp++, *sp++)) != 0) { - return (rc); - } - } - - PRINTF("%s:%d: count = %ld\n", __FUNCTION__, __LINE__, count); - if (count == 0) { /* all done */ - PRINTF("%s:%d: Less than 1 buffer (%d) worth of bytes\n", - __FUNCTION__, __LINE__, FLASH_WRITE_BUF_SIZE); - return (rc); - } - - /* - * Now that we are write buffer aligned, write full or partial buffers. - * The fact that we are write buffer aligned automatically avoids - * crossing a block address during a write buffer operation. - */ - bufs = count / FLASH_WRITE_BUF_SIZE; - PRINTF("%s:%d: %d (0x%x) buffers to write\n", __FUNCTION__, __LINE__, - bufs, bufs); - while (bufs >= 1) { - rc = write_flash_buffer8(info_p, sp, dp, FLASH_WRITE_BUF_SIZE); - if (rc != 0) { - PRINTF("%s:%d: ** Error writing buf %d\n", - __FUNCTION__, __LINE__, bufs); - return (rc); - } - bufs--; - sp += FLASH_WRITE_BUF_SIZE; - dp += FLASH_WRITE_BUF_SIZE; - } - - /* - * Do the leftovers - */ - i = count % FLASH_WRITE_BUF_SIZE; - PRINTF("%s:%d: %d (0x%x) leftover bytes\n", __FUNCTION__, __LINE__, i, i); - if (i > 0) { - rc = write_flash_buffer8(info_p, sp, dp, i); - } - - sp = (vu_char*)info_p->start[0]; - *sp = SCS_READ_CMD; - return (rc); - -#else - wp = addr; - while (count-- >= 1) { - if((rc = write_data8(info_p, wp++, *src_p++)) != 0) - return (rc); - } - return 0; -#endif -} - - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_data8 (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - vu_char status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = SCS_PROGRAM_CMD; - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = SCS_READ_CMD; - return (1); - } - } - *addr = SCS_READ_CMD; - return (0); -} - -/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c deleted file mode 100644 index b7984dd0fe..0000000000 --- a/board/gen860t/fpga.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the GEN860T computer - */ - -#include -#include -#include -#include "fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_FPGA) - -#if 0 -#define GEN860T_FPGA_DEBUG -#endif - -#ifdef GEN860T_FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * Port bit numbers for the Selectmap controls - */ -#define FPGA_INIT_BIT_NUM 22 /* PB22 */ -#define FPGA_RESET_BIT_NUM 11 /* PC11 */ -#define FPGA_DONE_BIT_NUM 16 /* PB16 */ -#define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */ - -/* Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - */ -Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_init_fn, - fpga_err_fn, - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - fpga_read_data_fn, - fpga_write_data_fn, - fpga_busy_fn, - fpga_abort_fn, - fpga_post_config_fn -}; - -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Virtex2, - slave_selectmap, - XILINX_XC2V3000_SIZE, - (void *) &fpga_fns, - 0} -}; - -/* - * Display FPGA revision information - */ -void print_fpga_revision (void) -{ - vu_long *rev_p = (vu_long *) 0x60000008; - - printf ("FPGA Revision 0x%.8lx" - " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n", - *rev_p, - ((*rev_p >> 28) & 0xf), - ((*rev_p >> 20) & 0xff), - ((*rev_p >> 12) & 0xff), - ((*rev_p >> 8) & 0xf), (*rev_p & 0xff)); -} - - -/* - * Perform a simple test of the FPGA to processor interface using the FPGA's - * inverting bus test register. The great thing about doing a read/write - * test on a register that inverts it's contents is that you avoid any - * problems with bus charging. - * Return 0 on failure, 1 on success. - */ -int test_fpga_ibtr (void) -{ - vu_long *ibtr_p = (vu_long *) 0x60000010; - vu_long readback; - vu_long compare; - int i; - int j; - int k; - int pass = 1; - - static const ulong bitpattern[] = { - 0xdeadbeef, /* magic ID pattern for debug */ - 0x00000001, /* single bit */ - 0x00000003, /* two adjacent bits */ - 0x00000007, /* three adjacent bits */ - 0x0000000F, /* four adjacent bits */ - 0x00000005, /* two non-adjacent bits */ - 0x00000015, /* three non-adjacent bits */ - 0x00000055, /* four non-adjacent bits */ - 0xaaaaaaaa, /* alternating 1/0 */ - }; - - for (i = 0; i < 1024; i++) { - for (j = 0; j < 31; j++) { - for (k = 0; - k < sizeof (bitpattern) / sizeof (bitpattern[0]); - k++) { - *ibtr_p = compare = (bitpattern[k] << j); - readback = *ibtr_p; - if (readback != ~compare) { - printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback); - pass = 0; - break; - } - } - if (!pass) - break; - } - if (!pass) - break; - } - if (pass) { - printf ("FPGA inverting bus test passed\n"); - print_fpga_revision (); - } else { - printf ("** FPGA inverting bus test failed\n"); - } - return pass; -} - - -/* - * Set the active-low FPGA reset signal. - */ -void fpga_reset (int assert) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__); - if (assert) { - immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF ("asserted\n"); - } else { - immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF ("deasserted\n"); - } -} - - -/* - * Initialize the SelectMap interface. We assume that the mode and the - * initial state of all of the port pins have already been set! - */ -void fpga_selectmap_init (void) -{ - PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, - __LINE__); - fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ -} - - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -int gen860t_init_fpga (void) -{ - int i; - - PRINTF ("%s:%d: Initialize FPGA interface\n", - __FUNCTION__, __LINE__); - fpga_init (); - fpga_selectmap_init (); - - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { - PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); - fpga_add (fpga_xilinx, &fpga[i]); - } - return 1; -} - - -/* - * Set the FPGA's active-low SelectMap program line to the specified level - */ -int fpga_pgm_fn (int assert, int flush, int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); - - if (assert) { - immap->im_ioport.iop_padat &= - ~(0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF ("asserted\n"); - } else { - immap->im_ioport.iop_padat |= - (0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF ("deasserted\n"); - } - return assert; -} - - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int fpga_init_fn (int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__); - if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { - PRINTF ("high\n"); - return 0; - } else { - PRINTF ("low\n"); - return 1; - } -} - - -/* - * Test the state of the active-high FPGA DONE pin - */ -int fpga_done_fn (int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__); - if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) { - PRINTF ("high\n"); - return FPGA_SUCCESS; - } else { - PRINTF ("low\n"); - return FPGA_FAIL; - } -} - - -/* - * Read FPGA SelectMap data. - */ -int fpga_read_data_fn (unsigned char *data, int cookie) -{ - vu_char *p = (vu_char *) SELECTMAP_BASE; - - *data = *p; -#if 0 - PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data); -#endif - return (int) data; -} - - -/* - * Write data to the FPGA SelectMap port - */ -int fpga_write_data_fn (unsigned char data, int flush, int cookie) -{ - vu_char *p = (vu_char *) SELECTMAP_BASE; - -#if 0 - PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data); -#endif - *p = data; - return (int) data; -} - - -/* - * Abort and FPGA operation - */ -int fpga_abort_fn (int cookie) -{ - PRINTF ("%s:%d: FPGA program sequence aborted\n", - __FUNCTION__, __LINE__); - return FPGA_FAIL; -} - - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int fpga_pre_config_fn (int cookie) -{ - PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset(true); - return 0; -} - - -/* - * FPGA post configuration function. Blip the FPGA reset line and then see if - * the FPGA appears to be running. - */ -int fpga_post_config_fn (int cookie) -{ - int rc; - - PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); - fpga_reset(true); - udelay (1000); - fpga_reset(false); - udelay (1000); - - /* - * Use the FPGA,s inverting bus test register to do a simple test of the - * processor interface. - */ - rc = test_fpga_ibtr (); - return rc; -} - - -/* - * Clock, chip select and write signal assert functions and error check - * and busy functions. These are only stubs because the GEN860T selectmap - * interface handles sequencing of control signals automatically (it uses - * a memory-mapped interface to the FPGA SelectMap port). The design of - * the interface guarantees that the SelectMap port cannot be overrun so - * no busy check is needed. A configuration error is signalled by INIT - * going low during configuration, so there is no need for a separate error - * function. - */ -int fpga_clk_fn (int assert_clk, int flush, int cookie) -{ - return assert_clk; -} - -int fpga_cs_fn (int assert_cs, int flush, int cookie) -{ - return assert_cs; -} - -int fpga_wr_fn (int assert_write, int flush, int cookie) -{ - return assert_write; -} - -int fpga_err_fn (int cookie) -{ - return 0; -} - -int fpga_busy_fn (int cookie) -{ - return 0; -} -#endif diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h deleted file mode 100644 index 95c15c4f63..0000000000 --- a/board/gen860t/fpga.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the GEN860T computer - */ - -extern int gen860t_init_fpga(void); -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_err_fn(int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_cs_fn(int assert_cs, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_read_data_fn(unsigned char *data, int cookie); -extern int fpga_write_data_fn(unsigned char data, int flush, int cookie); -extern int fpga_busy_fn(int cookie); -extern int fpga_abort_fn(int cookie ); -extern int fpga_pre_config_fn(int cookie ); -extern int fpga_post_config_fn(int cookie ); diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c deleted file mode 100644 index fe139f4920..0000000000 --- a/board/gen860t/gen860t.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include "beeper.h" -#include "fpga.h" -#include "ioport.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_STATUS_LED -#include -#endif - -#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII) -#include -#endif - -#if 0 -#define GEN860T_DEBUG -#endif - -#ifdef GEN860T_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * The following UPM init tables were generated automatically by - * Motorola's MCUINIT program. See the README file for UPM to - * SDRAM pin assignments if you want to type this data into - * MCUINIT in order to reverse engineer the waveforms. - */ - -/* - * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices - * (UPMA) and Virtex FPGA SelectMap interface (UPMB). - * NOTE that unused areas of the table are used to hold NOP, precharge - * and mode register set sequences. - * - */ -#define UPMA_NOP_ADDR 0x5 -#define UPMA_PRECHARGE_ADDR 0x6 -#define UPMA_MRS_ADDR 0x12 - -#define UPM_SINGLE_READ_ADDR 0x00 -#define UPM_BURST_READ_ADDR 0x08 -#define UPM_SINGLE_WRITE_ADDR 0x18 -#define UPM_BURST_WRITE_ADDR 0x20 -#define UPM_REFRESH_ADDR 0x30 - -const uint sdram_upm_table[] = { - /* single read (offset 0x00 in upm ram) */ - 0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05, - 0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff, - /* burst read (offset 0x08 in upm ram) */ - 0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00, - 0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff, - 0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4, - 0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff, - /* single write (offset 0x18 in upm ram) */ - 0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst write (offset 0x20 in upm ram) */ - 0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00, - 0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* refresh (offset 0x30 in upm ram) */ - 0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84, - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* exception (offset 0x3C in upm ram) */ -}; - -const uint selectmap_upm_table[] = { - /* single read (offset 0x00 in upm ram) */ - 0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00, - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst read (offset 0x08 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* single write (offset 0x18 in upm ram) */ - 0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst write (offset 0x20 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* refresh (offset 0x30 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* exception (offset 0x3C in upm ram) */ - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff -}; - -/* - * Check board identity. Always successful (gives information only) - */ -int checkboard (void) -{ - char *s; - char buf[64]; - int i; - - i = getenv_f("board_id", buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (s) { - printf ("%s ", s); - } else { - printf (" "); - } - - i = getenv_f("serial#", buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (s) { - printf ("S/N %s\n", s); - } else { - printf ("S/N \n"); - } - - printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk)); - printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk)); - return (0); -} - -/* - * Initialize SDRAM - */ -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - upmconfig (UPMA, - (uint *) sdram_upm_table, - sizeof (sdram_upm_table) / sizeof (uint) - ); - - /* - * Setup MAMR register - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - /* - * Map CS1* to SDRAM bank - */ - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; - - /* - * Perform SDRAM initialization sequence: - * 1. Apply at least one NOP command - * 2. 100 uS delay (JEDEC standard says 200 uS) - * 3. Issue 4 precharge commands - * 4. Perform two refresh cycles - * 5. Program mode register - * - * Program SDRAM for standard operation, sequential burst, burst length - * of 4, CAS latency of 2. - */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (0) | UPMA_NOP_ADDR; - udelay (200); - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (4) | UPMA_PRECHARGE_ADDR; - - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (2) | UPM_REFRESH_ADDR; - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (1) | UPMA_MRS_ADDR; - - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (0) | UPMA_NOP_ADDR; - /* - * Enable refresh - */ - memctl->memc_mamr |= MAMR_PTAE; - - return (SDRAM_SIZE); -} - -/* - * Disk On Chip (DOC) Millenium initialization. - * The DOC lives in the CS2* space - */ -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - printf ("Probing at 0x%.8x: ", DOC_BASE); - doc_probe (DOC_BASE); -} -#endif - -/* - * Miscellaneous intialization - */ -int misc_init_r (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - /* - * Set up UPMB to handle the Virtex FPGA SelectMap interface - */ - upmconfig (UPMB, (uint *) selectmap_upm_table, - sizeof (selectmap_upm_table) / sizeof (uint)); - - memctl->memc_mbmr = 0x0; - - config_mpc8xx_ioports (immr); - -#if defined(CONFIG_CMD_MII) - mii_init (); -#endif - -#if defined(CONFIG_FPGA) - gen860t_init_fpga (); -#endif - return 0; -} - -/* - * Final init hook before entering command loop. - */ -int last_stage_init (void) -{ -#if !defined(CONFIG_SC) - char buf[256]; - int i; - - /* - * Turn the beeper volume all the way down in case this is a warm boot. - */ - set_beeper_volume (-64); - init_beeper (); - - /* - * Read the environment to see what to do with the beeper - */ - i = getenv_f("beeper", buf, sizeof (buf)); - if (i > 0) { - do_beeper (buf); - } -#endif - return 0; -} - -/* - * Stub to make POST code happy. Can't self-poweroff, so just hang. - */ -void board_poweroff (void) -{ - puts ("### Please power off the board ###\n"); - while (1); -} diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c deleted file mode 100644 index 7cd209b7ac..0000000000 --- a/board/gen860t/ioport.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "ioport.h" - -#if 0 -#define IOPORT_DEBUG -#endif - -#ifdef IOPORT_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * The ioport configuration table. - */ -const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { - /* - * Port A configuration - * Pin Signal Type Active Initial state - * PA7 fpgaProgramLowOut Out Low High - * PA1 fpgaCoreVoltageFailLow In Low N/A - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ - /* PA15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA9 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 1*/ - /* PA8 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 1*/ - /* PA7 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaProgramLow */ - /* PA6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA5 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 0*/ - /* PA4 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 0*/ - /* PA3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA2 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PA1 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaCoreVoltageFail*/ -#else - /* PA1 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PA0 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, - - /* - * Port B configuration - * Pin Signal Type Active Initial state - * PB14 docBusyLowIn In Low X - * PB15 gpio1Sig Out High Low - * PB16 fpgaDoneBi In High X - * PB17 swBitOkLowOut Out Low High - * PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z) - * PB22 fpgaInitLowBi In Low X - * PB23 batteryOkSig In High X - * PB31 pulseCatcherClr Out High 0 - */ - { /* conf ppar psor pdir podr pdat pint function */ -#if !defined(CONFIG_SC) - /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#else - /* PB31 */ { 1, 0, 0, 1, 0, 0, 0 }, /* pulseCatcherClr */ -#endif - /* PB30 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB29 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB28 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB27 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB26 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB25 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB24 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PB23 */ { 1, 0, 0, 0, 0, 0, 0 }, /* batteryOk */ -#else - /* PB23 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PB22 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaInitLowBi */ - /* PB21 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB20 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PB19 */ { 1, 0, 0, 1, 1, 1, 0 }, /* speakerVol */ -#else - /* PB19 */ { 0, 0, 0, 1, 1, 1, 0 }, /* */ -#endif - /* PB18 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 0, 0, 1, 0, 1, 0 }, /* swBitOkLow */ - /* PB16 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaDone */ - /* PB15 */ { 1, 0, 0, 1, 0, 0, 0 }, /* gpio1 */ -#if !defined(CONFIG_SC) - /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */ -#else - /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ -#endif - }, - - /* - * Port C configuration - * Pin Signal Type Active Initial state - * PC4 i2cBus1EnSig Out High High - * PC5 i2cBus2EnSig Out High High - * PC6 gpio0Sig Out High Low - * PC8 i2cBus3EnSig Out High High - * PC10 i2cBus4EnSig Out High High - * PC11 fpgaResetLowOut Out Low High - * PC12 systemBitOkIn In High X - * PC15 selfDreqLow In Low X - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */ - /* PC14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */ -#else - /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */ -#if !defined(CONFIG_SC) - /* PC10 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus4EnSig */ -#else - /* PC10 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* PC9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PC8 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus3EnSig */ -#else - /* PC8 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* PC7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC6 */ { 1, 0, 0, 1, 0, 1, 0 }, /* gpio0 */ -#if !defined(CONFIG_SC) - /* PC5 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus2EnSig */ - /* PC4 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus1EnSig */ -#else - /* PC5 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ - /* PC4 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, - - /* - * Port D configuration - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD8 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD5 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD4 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - } -}; - -/* - * Configure the MPC8XX I/O ports per the ioport configuration table - * (taken from ./arch/powerpc/cpu/mpc8260/cpu_init.c) - */ -void config_mpc8xx_ioports (volatile immap_t * immr) -{ - int portnum; - - for (portnum = 0; portnum < NUM_PORTS; portnum++) { - uint pmsk = 0, ppar = 0, psor = 0, pdir = 0; - uint podr = 0, pdat = 0, pint = 0; - uint msk = 1; - mpc8xx_iop_conf_t *iopc = - (mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0]; - mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS; - - /* - * For all ports except port B, ignore the two don't care entries - * in the configuration tables. - */ - if (portnum != 1) { - iopc = (mpc8xx_iop_conf_t *) & - iop_conf_tab[portnum][2]; - } - - /* - * NOTE: index 0 refers to pin 17, index 17 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - if (iopc->pint) - pint |= msk; - } - msk <<= 1; - iopc++; - } - - PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__, - portnum); -#ifdef IOPORT_DEBUG - switch (portnum) { - case 0: - printf ("(A)\n"); - break; - case 1: - printf ("(B)\n"); - break; - case 2: - printf ("(C)\n"); - break; - case 3: - printf ("(D)\n"); - break; - default: - printf ("(?)\n"); - break; - } -#endif - PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n" - " pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n", - ppar, pdir, podr, pdat, psor, pint, pmsk); - - /* - * Have to handle the ioports on a port-by-port basis since there - * are three different flavors. - */ - if (pmsk != 0) { - uint tpmsk = ~pmsk; - - if (0 == portnum) { /* port A */ - immr->im_ioport.iop_papar &= tpmsk; - immr->im_ioport.iop_padat = - (immr->im_ioport. - iop_padat & tpmsk) | pdat; - immr->im_ioport.iop_padir = - (immr->im_ioport. - iop_padir & tpmsk) | pdir; - immr->im_ioport.iop_paodr = - (immr->im_ioport. - iop_paodr & tpmsk) | podr; - immr->im_ioport.iop_papar |= ppar; - } else if (1 == portnum) { /* port B */ - immr->im_cpm.cp_pbpar &= tpmsk; - immr->im_cpm.cp_pbdat = - (immr->im_cpm. - cp_pbdat & tpmsk) | pdat; - immr->im_cpm.cp_pbdir = - (immr->im_cpm. - cp_pbdir & tpmsk) | pdir; - immr->im_cpm.cp_pbodr = - (immr->im_cpm. - cp_pbodr & tpmsk) | podr; - immr->im_cpm.cp_pbpar |= ppar; - } else if (2 == portnum) { /* port C */ - immr->im_ioport.iop_pcpar &= tpmsk; - immr->im_ioport.iop_pcdat = - (immr->im_ioport. - iop_pcdat & tpmsk) | pdat; - immr->im_ioport.iop_pcdir = - (immr->im_ioport. - iop_pcdir & tpmsk) | pdir; - immr->im_ioport.iop_pcint = - (immr->im_ioport. - iop_pcint & tpmsk) | pint; - immr->im_ioport.iop_pcso = - (immr->im_ioport. - iop_pcso & tpmsk) | psor; - immr->im_ioport.iop_pcpar |= ppar; - } else if (3 == portnum) { /* port D */ - immr->im_ioport.iop_pdpar &= tpmsk; - immr->im_ioport.iop_pddat = - (immr->im_ioport. - iop_pddat & tpmsk) | pdat; - immr->im_ioport.iop_pddir = - (immr->im_ioport. - iop_pddir & tpmsk) | pdir; - immr->im_ioport.iop_pdpar |= ppar; - } - } - } - - PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x" - " paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_papar, immr->im_ioport.iop_padir, - immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat); - PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x" - " pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__, - immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir, - immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat); - PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x" - " pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ", - __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat, - immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint); - PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x" - " pddat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); -} diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h deleted file mode 100644 index 4ac2aa4dd8..0000000000 --- a/board/gen860t/ioport.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define NUM_PORTS 4 -#define PORT_BITS 18 - -/* - * This structure provides configuration information for one port pin. - * We include all fields needed to initialize any of the ioports. - */ -typedef struct { - unsigned char conf:1; /* If 1, configure this port */ - unsigned char ppar:1; /* Port Pin Assignment Register */ - unsigned char psor:1; /* Port Special Options Register */ - unsigned char pdir:1; /* Port Data Direction Register */ - unsigned char podr:1; /* Port Open Drain Register */ - unsigned char pdat:1; /* Port Data Register */ - unsigned char pint:1; /* Port Interrupt Register */ -} mpc8xx_iop_conf_t; - -extern void config_mpc8xx_ioports(volatile immap_t *immr); diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds deleted file mode 100644 index 7a4a7637e8..0000000000 --- a/board/gen860t/u-boot-flashenv.lds +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Linker command file for the GEN860T board when the environment is - * stored in flash memory. - * - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* - * Read-only sections, merged into text segment: - */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* - * Read-write section, merged into data segment: - */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data: - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); - - .ppcenv: - { - . = env_offset; - common/env_embedded.o - } -} diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds deleted file mode 100644 index 3371c0a3ee..0000000000 --- a/board/gen860t/u-boot.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Linker command file for the GEN860T board. - * - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* - * Read-only sections, merged into text segment: - */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* - * Read-write section, merged into data segment: - */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/genesi/mx51_efikamx/Kconfig b/board/genesi/mx51_efikamx/Kconfig new file mode 100644 index 0000000000..355702a4b6 --- /dev/null +++ b/board/genesi/mx51_efikamx/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX51_EFIKAMX + +config SYS_BOARD + default "mx51_efikamx" + +config SYS_VENDOR + default "genesi" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx51_efikamx" + +endif diff --git a/board/genesi/mx51_efikamx/MAINTAINERS b/board/genesi/mx51_efikamx/MAINTAINERS new file mode 100644 index 0000000000..f1398c4926 --- /dev/null +++ b/board/genesi/mx51_efikamx/MAINTAINERS @@ -0,0 +1,7 @@ +MX51_EFIKAMX BOARD +#M: - +S: Maintained +F: board/genesi/mx51_efikamx/ +F: include/configs/mx51_efikamx.h +F: configs/mx51_efikamx_defconfig +F: configs/mx51_efikasb_defconfig diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile index 7ede567e0a..87f5f9ede1 100644 --- a/board/genesi/mx51_efikamx/Makefile +++ b/board/genesi/mx51_efikamx/Makefile @@ -10,23 +10,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := efikamx.o efikamx-usb.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := efikamx.o efikamx-usb.o diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 76753f90f6..6ba55cd08a 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -152,6 +153,11 @@ static iomux_v3_cfg_t const efikamx_spi_pads[] = { * PMIC configuration */ #ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 1) ? 121 : -1; +} + static void power_init(void) { unsigned int val; @@ -159,7 +165,7 @@ static void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return; diff --git a/board/genietv/Makefile b/board/genietv/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/genietv/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/genietv/flash.c b/board/genietv/flash.c deleted file mode 100644 index 5f57978a33..0000000000 --- a/board/genietv/flash.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info); -static int write_word(flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets(ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - /* Setup offsets */ - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return size_b0; -} - -/*----------------------------------------------------------------------- - * Fix this to support variable sector sizes -*/ -static void flash_get_offsets(ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - if (info->size >> 20) { - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - } else { - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); - } - - puts(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - puts("\n "); - - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - putc('\n'); - return; -} -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr; - char value; - - caddr = (volatile unsigned char *)addr ; - - /* Write auto select command: read Manufacturer ID */ - - debug("Base address is: %8p\n", caddr); - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - value = caddr[0]; - - debug("Manufact ID: %02x\n", value); - - switch (value) { - case 0x1: /* AMD_MANUFACT */ - info->flash_id = FLASH_MAN_AMD; - break; - case 0x4: /* FUJ_MANUFACT */ - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = caddr[1]; /* device ID */ - - debug("Device ID: %02x\n", value); - - switch (value) { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, &flash_info[0]); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address, - * (A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ - } - - return info->size; -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - - while ((addr[0] & 0xFF) != 0xFF) { - - now = get_timer(start); - - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return write_word(info, wp, data); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *cdest, *cdata; - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - ulong start; - int flag, count = 4 ; - - cdest = (volatile unsigned char *)dest ; - cdata = (volatile unsigned char *)&data ; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return 2; - - while (count--) { - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *cdest = *cdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*cdest ^ *cdata) & 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - - cdata++ ; - cdest++ ; - } - return 0; -} diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c deleted file mode 100644 index 0a015ea2de..0000000000 --- a/board/genietv/genietv.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * genietv/genietv.c - * - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 02800000 -> 0287ffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - LON (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - * - * Ports are configured as follows: - * - * PA7 - SDRAM banks enable - */ - -#include -#include - -#define CONFIG_SYS_PA7 0x0100 - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00, - 0x1FFDDC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMB RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMB RAM) - */ - 0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMB RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMB RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity - */ - -int checkboard (void) -{ - puts ("Board: GenieTV\n"); - return 0; -} - -#if 0 -static void PrintState (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &im->im_memctl; - - printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, - memctl->memc_or0); - printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, - memctl->memc_or1); - printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, - memctl->memc_or2); -} -#endif - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &im->im_memctl; - long int size_b0, size_b1, size8; - - /* Enable SDRAM */ - - /* Configuring PA7 for general purpouse output pin */ - im->im_ioport.iop_papar &= ~CONFIG_SYS_PA7; /* 0 = general purpouse */ - im->im_ioport.iop_padir |= CONFIG_SYS_PA7; /* 1 = output */ - - /* Enable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat |= CONFIG_SYS_PA7; /* value of PA7 */ - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; - - upmconfig (UPMB, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - - memctl->memc_or1 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - - memctl->memc_or2 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - - /* perform SDRAM initialization sequence */ - memctl->memc_mar = 0x00000088; - - memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */ - - memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */ - - /* Execute refresh 8 times */ - memctl->memc_mbmr = (CONFIG_SYS_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X; - - memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */ - - memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */ - - /* Execute refresh 4 times */ - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - -#if 0 - PrintState (); -#endif -/* printf ("\nChecking bank1..."); */ - size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - size_b0 = size8; - -/* printf ("\nChecking bank2..."); */ - size_b1 = - dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - /* - * Final mapping: map bigger bank first - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + - (size_b0 & BR_BA_MSK); - } else { - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - /* adjust refresh rate depending on SDRAM type, one bank */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - } - - /* If no memory detected, disable SDRAM */ - if ((size_b0 + size_b1) == 0) { - printf ("disabling SDRAM!\n"); - /* Disable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat &= ~CONFIG_SYS_PA7; /* value of PA7 */ - } -/* else */ -/* printf("done! (%08lx)\n", size_b0 + size_b1); */ - -#if 0 - PrintState (); -#endif - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mbmr_value, long int *base, - long int maxsize) -{ - long size; - - /*memctl->memc_mbmr = mbmr_value; */ - - size = get_ram_size (base, maxsize); - - if (size) { -/* printf("(%08lx)", size); */ - } else { - printf ("(0)"); - } - - return (size); -} - -#if defined(CONFIG_CMD_PCMCIA) - -#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char *) CONFIG_SYS_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init (void) -{ - volatile pcmconf8xx_t *pcmp; - uint v, slota, slotb; - - /* - ** Enable the PCMCIA for a Flash card. - */ - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); - -#if 0 - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR; - pcmp->pcmc_por0 = 0xc00ff05d; -#endif - - /* Set all slots to zero by default. */ - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; -#ifdef PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0x40; -#endif -#ifdef PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0x40; -#endif - - /* Check if any PCMCIA card is luged in. */ - slota = (pcmp->pcmc_pipr & 0x18000000) == 0; - slotb = (pcmp->pcmc_pipr & 0x00001800) == 0; - - if (!(slota || slotb)) { - printf ("No card present\n"); -#ifdef PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0; -#endif -#ifdef PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0; -#endif - return -1; - } else - printf ("Unknown card ("); - - v = 0; - - switch ((pcmp->pcmc_pipr >> 14) & 3) { - case 0x00: - printf ("5V"); - v = 5; - break; - case 0x01: - printf ("5V and 3V"); - v = 3; - break; - case 0x03: - printf ("5V, 3V and x.xV"); - v = 3; - break; - } - - switch (v) { - case 3: - printf ("; using 3V"); - /* Enable 3 volt Vcc. */ - - break; - - default: - printf ("; unknown voltage"); - return -1; - } - printf (")\n"); - /* disable pcmcia reset after a while */ - - udelay (20); - - pcmp->pcmc_pgcrb = 0; - - /* If you using a real hd you should give a short - * spin-up time. */ -#ifdef CONFIG_DISK_SPINUP_TIME - udelay (CONFIG_DISK_SPINUP_TIME); -#endif - - return 0; -} -#endif diff --git a/board/genietv/genietv.h b/board/genietv/genietv.h deleted file mode 100644 index 7c95b566f9..0000000000 --- a/board/genietv/genietv.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 02800000 -> 0287ffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - LON (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - * - * Ports are configured as follows: - * - * PA7 - SDRAM banks enable - */ diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds deleted file mode 100644 index e217f06819..0000000000 --- a/board/genietv/u-boot.lds +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/libgeneric.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - board/genietv/libgenietv.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) - *(.text.do_load_serial*) - *(.text.do_mem_*) - *(.text.do_bootm*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug deleted file mode 100644 index cc8cd3a631..0000000000 --- a/board/genietv/u-boot.lds.debug +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig new file mode 100644 index 0000000000..33a31f311f --- /dev/null +++ b/board/google/chromebook_link/Kconfig @@ -0,0 +1,41 @@ +if TARGET_CHROMEBOOK_LINK + +config SYS_BOARD + default "chromebook_link" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "chromebook_link" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select HAVE_ACPI_RESUME + select MARK_GRAPHICS_MEM_WRCOMB + select BOARD_ROMSIZE_KB_8192 + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + default y + +config SYS_CAR_ADDR + hex + default 0xff7e0000 + +config SYS_CAR_SIZE + hex + default 0x20000 + +endif diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS new file mode 100644 index 0000000000..bc253a2ba7 --- /dev/null +++ b/board/google/chromebook_link/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK LINK BOARD +M: Simon Glass +S: Maintained +F: board/google/chromebook_link/ +F: include/configs/chromebook_link.h +F: configs/chromebook_link_defconfig diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile new file mode 100644 index 0000000000..a133c2e894 --- /dev/null +++ b/board/google/chromebook_link/Makefile @@ -0,0 +1,15 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += link.o diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c new file mode 100644 index 0000000000..9978e92006 --- /dev/null +++ b/board/google/chromebook_link/link.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +int arch_early_init_r(void) +{ + if (cros_ec_board_init()) + return -1; + + return 0; +} + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ + .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ + .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ + .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ + .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ + .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ + .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ + .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ + .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ + .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ + .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio36 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_map link_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +int board_early_init_f(void) +{ + ich_gpio_set_gpio_map(&link_gpio_map); + + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} diff --git a/board/google/common/Makefile b/board/google/common/Makefile new file mode 100644 index 0000000000..b38bc14ff6 --- /dev/null +++ b/board/google/common/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += early_init.o diff --git a/board/google/common/early_init.S b/board/google/common/early_init.S new file mode 100644 index 0000000000..7017185d06 --- /dev/null +++ b/board/google/common/early_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + /* Enable post codes to EC */ +#ifdef CONFIG_EARLY_POST_CROS_EC + mov $0x1b, %ecx + rdmsr + and $0x100, %eax + test %eax, %eax + je 1f + + mov $0x8000f8f0, %eax + mov $0xcf8, %dx + out %eax, (%dx) + mov $0xfed1c001, %eax + mov $0xcfc, %dx + out %eax, (%dx) + mov $0xfed1f410, %esp + mov (%esp), %eax + and $0xfffffffb, %eax + mov %eax, (%esp) +1: +#endif + jmp early_board_init_ret diff --git a/board/gumstix/duovero/Kconfig b/board/gumstix/duovero/Kconfig new file mode 100644 index 0000000000..2f8558aaf3 --- /dev/null +++ b/board/gumstix/duovero/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DUOVERO + +config SYS_BOARD + default "duovero" + +config SYS_VENDOR + default "gumstix" + +config SYS_CONFIG_NAME + default "duovero" + +endif diff --git a/board/gumstix/duovero/MAINTAINERS b/board/gumstix/duovero/MAINTAINERS new file mode 100644 index 0000000000..87cd4e670c --- /dev/null +++ b/board/gumstix/duovero/MAINTAINERS @@ -0,0 +1,6 @@ +DUOVERO BOARD +M: Ash Charles +S: Maintained +F: board/gumstix/duovero/ +F: include/configs/duovero.h +F: configs/duovero_defconfig diff --git a/board/gumstix/duovero/Makefile b/board/gumstix/duovero/Makefile new file mode 100644 index 0000000000..f738c58d04 --- /dev/null +++ b/board/gumstix/duovero/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := duovero.o diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c new file mode 100644 index 0000000000..81d6c82219 --- /dev/null +++ b/board/gumstix/duovero/duovero.c @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2013 + * Gumstix Inc. + * Maintainer: Ash Charles + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "duovero_mux_data.h" + +#define WIFI_EN 43 + +#if defined(CONFIG_CMD_NET) +#define SMSC_NRESET 45 +static void setup_net_chip(void); +#endif + +#ifdef CONFIG_USB_EHCI +#include +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: duovero\n" +}; + +struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000; + +/** + * @brief board_init + * + * @return 0 + */ +int board_init(void) +{ + gpmc_init(); + + gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/** + * @brief misc_init_r - Configure board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ + int ret = 0; + u8 val; + + /* wifi setup: first enable 32Khz clock from 6030 pmic */ + val = 0xe1; + ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1); + if (ret) + printf("Failed to enable 32Khz clock to wifi module\n"); + + /* then setup WIFI_EN as an output pin and send reset pulse */ + if (!gpio_request(WIFI_EN, "")) { + gpio_direction_output(WIFI_EN, 0); + gpio_set_value(WIFI_EN, 1); + udelay(1); + gpio_set_value(WIFI_EN, 0); + udelay(1); + gpio_set_value(WIFI_EN, 1); + } + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif + return 0; +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} +#endif + + +#if defined(CONFIG_CMD_NET) + +#define GPMC_SIZE_16M 0xF +#define GPMC_BASEADDR_MASK 0x3F +#define GPMC_CS_ENABLE 0x1 + +static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs, + u32 base, u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + + /* + * Enable the config. size is the CS size and goes in + * bits 11:8. We set bit 6 to enable this CS and the base + * address goes into bits 5:0. + */ + writel((size << 8) | (GPMC_CS_ENABLE << 6) | + ((base >> 24) & GPMC_BASEADDR_MASK), + &cs->config7); + + sdelay(2000); +} + +/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x2a001203 +#define NET_LAN9221_GPMC_CONFIG2 0x000a0a02 +#define NET_LAN9221_GPMC_CONFIG3 0x00020200 +#define NET_LAN9221_GPMC_CONFIG4 0x0a030a03 +#define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a +#define NET_LAN9221_GPMC_CONFIG6 0x8a070707 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + +/* GPMC definitions for LAN9221 chips on expansion boards */ +static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + /*CONFIG7- computed as params */ +}; + +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, + GPMC_SIZE_16M); + + /* Make GPIO SMSC_NRESET as output pin and send reset pulse */ + if (!gpio_request(SMSC_NRESET, "")) { + gpio_direction_output(SMSC_NRESET, 0); + gpio_set_value(SMSC_NRESET, 1); + udelay(1); + gpio_set_value(SMSC_NRESET, 0); + udelay(1); + gpio_set_value(SMSC_NRESET, 1); + } +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +#ifdef CONFIG_USB_EHCI + +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int ret; + unsigned int utmi_clk; + u32 auxclk, altclksrc; + + /* Now we can enable our port clocks */ + utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL); + utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; + setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk); + + auxclk = readl(&scrm->auxclk3); + /* Select sys_clk */ + auxclk &= ~AUXCLK_SRCSELECT_MASK; + auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; + /* Set the divisor to 2 */ + auxclk &= ~AUXCLK_CLKDIV_MASK; + auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; + /* Request auxilary clock #3 */ + auxclk |= AUXCLK_ENABLE_MASK; + writel(auxclk, &scrm->auxclk3); + + altclksrc = readl(&scrm->altclksrc); + + /* Activate alternate system clock supplier */ + altclksrc &= ~ALTCLKSRC_MODE_MASK; + altclksrc |= ALTCLKSRC_MODE_ACTIVE; + + /* enable clocks */ + altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK; + + writel(altclksrc, &scrm->altclksrc); + + ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); + if (ret < 0) + return ret; + + return 0; +} + +int ehci_hcd_stop(int index) +{ + return omap_ehci_hcd_stop(); +} +#endif + +/* + * get_board_rev() - get board revision + */ +u32 get_board_rev(void) +{ + return 0x20; +} diff --git a/board/gumstix/duovero/duovero_mux_data.h b/board/gumstix/duovero/duovero_mux_data.h new file mode 100644 index 0000000000..1be247b874 --- /dev/null +++ b/board/gumstix/duovero/duovero_mux_data.h @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2012 + * Gumstix Incorporated, + * Maintainer: Ash Charles + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _DUOVERO_MUX_DATA_H_ +#define _DUOVERO_MUX_DATA_H_ + +#include + +const struct pad_conf_entry core_padconf_array_essential[] = { + {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ + {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ + {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ + {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ + {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ + {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ + {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ + {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ + {UART3_RX_IRRX, (PTU | IEN | M0)}, /* uart3_rx */ + {UART3_TX_IRTX, (M0)} /* uart3_tx */ +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ +}; + +const struct pad_conf_entry core_padconf_array_non_essential[] = { + {GPMC_AD0, (PTU | IEN | M0)}, /* gpmc_ad0 */ + {GPMC_AD1, (PTU | IEN | M0)}, /* gpmc_ad1 */ + {GPMC_AD2, (PTU | IEN | M0)}, /* gpmc_ad2 */ + {GPMC_AD3, (PTU | IEN | M0)}, /* gpmc_ad3 */ + {GPMC_AD4, (PTU | IEN | M0)}, /* gpmc_ad4 */ + {GPMC_AD5, (PTU | IEN | M0)}, /* gpmc_ad5 */ + {GPMC_AD6, (PTU | IEN | M0)}, /* gpmc_ad6 */ + {GPMC_AD7, (PTU | IEN | M0)}, /* gpmc_ad7 */ + {GPMC_AD8, (PTU | IEN | M0)}, /* gpmc_ad8 */ + {GPMC_AD9, (PTU | IEN | M0)}, /* gpmc_ad9 */ + {GPMC_AD10, (PTU | IEN | M0)}, /* gpmc_ad10 */ + {GPMC_AD11, (PTU | IEN | M0)}, /* gpmc_ad11 */ + {GPMC_AD12, (PTU | IEN | M0)}, /* gpmc_ad12 */ + {GPMC_AD13, (PTU | IEN | M0)}, /* gpmc_ad13 */ + {GPMC_AD14, (PTU | IEN | M0)}, /* gpmc_ad14 */ + {GPMC_AD15, (PTU | IEN | M0)}, /* gpmc_ad15 */ + {GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */ + {GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */ + {GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */ + {GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */ + {GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */ + {GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */ + {GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */ + {GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */ + {GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */ + {GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */ + {GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */ + {GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */ + {GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */ + {GPMC_NCS3, (PTU | IEN | M3)}, /* gpio_53 */ + {C2C_DATA12, (PTU | M0)}, /* gpmc_ncs4 */ + {C2C_DATA13, (PTU | M0)}, /* gpmc_ncs5 - eth_cs */ + {GPMC_NWP, (PTU | IEN | M0)}, /* gpmc_nwp */ + {GPMC_CLK, (PTU | IEN | M0)}, /* gpmc_clk */ + {GPMC_NADV_ALE, (PTU | M0)}, /* gpmc_nadv_ale */ + {GPMC_NBE0_CLE, (PTU | M0)}, /* gpmc_nbe0_cle */ + {GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */ + {GPMC_WAIT0, (PTU | IEN | M0)}, /* gpmc_wait0 */ + {GPMC_WAIT1, (PTU | IEN | M0)}, /* gpio_62 - usbh_nreset */ + {GPMC_NOE, (PTU | M0)}, /* gpmc_noe */ + {GPMC_NWE, (PTU | M0)}, /* gpmc_nwe */ + {HDMI_HPD, (PTD | IEN | M3)}, /* gpio_63 - hdmi_hpd */ + {HDMI_CEC, (PTU | IEN | M0)}, /* hdmi_cec */ + {HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */ + {HDMI_DDC_SDA, (IEN | M0)}, /* hdmi_ddc_sda */ + {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ + {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ + {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ + {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ + {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ + {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ + {CSI21_DX3, (IEN | M0)}, /* csi21_dx3 */ + {CSI21_DY3, (IEN | M0)}, /* csi21_dy3 */ + {CSI21_DX4, (IEN | M0)}, /* csi21_dx4 */ + {CSI21_DY4, (IEN | M0)}, /* csi21_dy4 */ + {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ + {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ + {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ + {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ + {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ + {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ + {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ + {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ + {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ + {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_96 - usbh_cpen */ + {USBB1_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_97 - usbh_reset */ + {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ + {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ + {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ + {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ + {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ + {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ + {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ + {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ + {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ + {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ + {UART2_RTS, (M0)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ + {UART2_TX, (M0)}, /* uart2_tx */ + {HDQ_SIO, (M0)}, /* hdq-sio */ + {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ + {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ + {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ + {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ + {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ + {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ + {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | PTU | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ + {USBB2_ULPITLL_CLK, (PTU | IEN | M3)}, /* gpio_157 - start_adc */ + {USBB2_ULPITLL_STP, (PTU | IEN | M3)}, /* gpio_158 - spi_nirq */ + {USBB2_ULPITLL_DIR, (PTU | IEN | M3)}, /* gpio_159 - bt_nreset */ + {USBB2_ULPITLL_NXT, (PTU | IEN | M3)}, /* gpio_160 - audio_pwron*/ + {USBB2_ULPITLL_DAT0, (PTU | IEN | M3)}, /* gpio_161 - bid_0 */ + {USBB2_ULPITLL_DAT1, (PTU | IEN | M3)}, /* gpio_162 - bid_1 */ + {USBB2_ULPITLL_DAT2, (PTU | IEN | M3)}, /* gpio_163 - bid_2 */ + {USBB2_ULPITLL_DAT3, (PTU | IEN | M3)}, /* gpio_164 - bid_3 */ + {USBB2_ULPITLL_DAT4, (PTU | IEN | M3)}, /* gpio_165 - bid_4 */ + {USBB2_ULPITLL_DAT5, (PTU | IEN | M3)}, /* gpio_166 - ts_irq*/ + {USBB2_ULPITLL_DAT6, (PTU | IEN | M3)}, /* gpio_167 - gps_pps */ + {USBB2_ULPITLL_DAT7, (PTU | IEN | M3)}, /* gpio_168 */ + {USBB2_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_170 */ + {UNIPRO_TX1, (PTU | IEN | M3)}, /* gpio_173 */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_BOOT0, (M0)}, /* sys_boot0 */ + {SYS_BOOT1, (M0)}, /* sys_boot1 */ + {SYS_BOOT2, (M0)}, /* sys_boot2 */ + {SYS_BOOT3, (M0)}, /* sys_boot3 */ + {SYS_BOOT4, (M0)}, /* sys_boot4 */ + {SYS_BOOT5, (M0)}, /* sys_boot5 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU16, (PTU | IEN | M3)}, /* gpio_27 */ + {DPM_EMU17, (PTU | IEN | M3)}, /* gpio_28 */ + {DPM_EMU18, (PTU | IEN | M3)}, /* gpio_29 */ + {DPM_EMU19, (PTU | IEN | M3)}, /* gpio_30 */ +}; + +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { + {PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */ + {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */ + {PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */ +}; + + +#endif /* _DUOVERO_MUX_DATA_H_ */ diff --git a/board/gumstix/pepper/Kconfig b/board/gumstix/pepper/Kconfig new file mode 100644 index 0000000000..6f94612fe2 --- /dev/null +++ b/board/gumstix/pepper/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PEPPER + +config SYS_BOARD + default "pepper" + +config SYS_VENDOR + default "gumstix" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "pepper" + +endif diff --git a/board/gumstix/pepper/MAINTAINERS b/board/gumstix/pepper/MAINTAINERS new file mode 100644 index 0000000000..ae860ecf1a --- /dev/null +++ b/board/gumstix/pepper/MAINTAINERS @@ -0,0 +1,6 @@ +PEPPER BOARD +M: Ash Charles +S: Maintained +F: board/gumstix/pepper/ +F: include/configs/pepper.h +F: configs/pepper_defconfig diff --git a/board/gumstix/pepper/Makefile b/board/gumstix/pepper/Makefile new file mode 100644 index 0000000000..ecb1d61669 --- /dev/null +++ b/board/gumstix/pepper/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += mux.o +endif + +obj-y += board.o diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c new file mode 100644 index 0000000000..f644f8188b --- /dev/null +++ b/board/gumstix/pepper/board.c @@ -0,0 +1,202 @@ +/* + * Board functions for Gumstix Pepper and AM335x-based boards + * + * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ + * Based on board/ti/am335x/board.c from Texas Instruments, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static const struct ddr_data ddr2_data = { + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr2_cmd_ctrl_data = { + .cmd0csratio = MT47H128M16RT25E_RATIO, + + .cmd1csratio = MT47H128M16RT25E_RATIO, + + .cmd2csratio = MT47H128M16RT25E_RATIO, +}; + +static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, + .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, + .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, + .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, + .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + config_ddr(266, &ioregs, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); +} +#endif + +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + + return 0; +} + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + const char *devname; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + + /* + * + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the KSZ9021 PHY. Since we only support a single ethernet + * device in U-Boot, we only do this for the current instance. + */ + devname = miiphy_get_current_dev(); + /* max rx/tx clock delay, min rx/tx control delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8104); + miiphy_write(devname, 0x0, 0xc, 0xa0a0); + + /* min rx data delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8105); + miiphy_write(devname, 0x0, 0x0c, 0x0000); + + /* min tx data delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8106); + miiphy_write(devname, 0x0, 0x0c, 0x0000); + + return n; +} +#endif diff --git a/board/gumstix/pepper/board.h b/board/gumstix/pepper/board.h new file mode 100644 index 0000000000..0512735a7b --- /dev/null +++ b/board/gumstix/pepper/board.h @@ -0,0 +1,19 @@ +/* + * Gumstix Pepper and AM335x-based boards information header + * + * Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * We must be able to enable uart0, for initial output. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/gumstix/pepper/mux.c b/board/gumstix/pepper/mux.c new file mode 100644 index 0000000000..50b12666d6 --- /dev/null +++ b/board/gumstix/pepper/mux.c @@ -0,0 +1,78 @@ +/* + * Muxing for Gumstix Pepper and AM335x-based boards + * + * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */ + {OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */ + {OFFSET(xdma_event_intr1), MODE(3)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +/* + * Do board-specific muxes. + */ +void enable_board_pin_mux(void) +{ + /* I2C0 */ + configure_module_pin_mux(i2c0_pin_mux); + /* SD Card */ + configure_module_pin_mux(mmc0_pin_mux); + /* Ethernet pinmux. */ + configure_module_pin_mux(rgmii1_pin_mux); +} diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile deleted file mode 100644 index ff9bd0f646..0000000000 --- a/board/gw8260/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := gw8260.o flash.o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c deleted file mode 100644 index 0c4a9439f8..0000000000 --- a/board/gw8260/flash.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the flash routines for the GW8260 board. - * - * - * - * MODULE DEPENDENCY: - * None - * - * - * RESTRICTIONS/LIMITATIONS: - * - * Only supports the following flash devices: - * AMD 29F080B - * AMD 29F016D - * - * Copyright (c) 2001, Advent Networks, Inc. - * - */ -/*********************************************************************/ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*********************************************************************/ -/* functions */ -/*********************************************************************/ - -/* - * NAME: flash_init() - initializes flash banks - * - * DESCRIPTION: - * This function initializes the flash bank(s). - * - * RETURNS: - * The size in bytes of the flash - * - * RESTRICTIONS/LIMITATIONS: - * - * - */ -unsigned long flash_init(void) -{ - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* for now, only support the 4 MB Flash SIMM */ - (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, - &flash_info[0]); - /* - * protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#ifndef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; /*size */ -} - -/*********************************************************************/ -/* NAME: flash_print_info() - prints flash imformation */ -/* */ -/* DESCRIPTION: */ -/* This function prints the flash information. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* */ -/* OUTPUTS: */ -/* Displays flash information to console */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*********************************************************************/ -/* The following code cannot be run from FLASH! */ -/*********************************************************************/ - -/*********************************************************************/ -/* NAME: flash_get_size() - detects the flash size */ -/* */ -/* DESCRIPTION: */ -/* 1) Reads vendor ID and devices ID from the flash devices. */ -/* 2) Initializes flash info struct. */ -/* 3) Return the flash size */ -/* */ -/* INPUTS: */ -/* vu_long *addr - pointer to start of flash */ -/* flash_info_t *info - flash information structure */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* Size of the flash in bytes, or 0 if device id is unknown. */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Only supports the following devices: */ -/* AM29F080D */ -/* AM29F016D */ -/* */ -/*********************************************************************/ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor, devid; - ulong base = (ulong)addr; - - /*printf("addr = %08lx\n", (unsigned long)addr); */ - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0x0000] = 0xf0f0f0f0; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - udelay (1000); - - vendor = addr[0]; - /*printf("vendor = %08lx\n", vendor); */ - if (vendor != 0x01010101) { - info->size = 0; - goto out; - } - - devid = addr[1]; - /*printf("devid = %08lx\n", devid); */ - - if ((devid & 0xff) == AMD_ID_F080B) { - info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B; - /* we have 16 sectors with 64KB each x 4 */ - info->sector_count = 16; - info->size = 4 * info->sector_count * 64*1024; - } else if ((devid & 0xff) == AMD_ID_F016D){ - info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F016D; - /* we have 32 sectors with 64KB each x 4 */ - info->sector_count = 32; - info->size = 4 * info->sector_count * 64*1024; - } else { - info->size = 0; - goto out; - } - /*printf("sector count = %08x\n", info->sector_count); */ - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* reset command */ - addr = (vu_long *)info->start[0]; - - out: - addr[0] = 0xf0f0f0f0; - - /*printf("size = %08x\n", info->size); */ - return info->size; -} - -/*********************************************************************/ -/* NAME: flash_erase() - erases flash by sector */ -/* */ -/* DESCRIPTION: */ -/* This function erases flash sectors starting for s_first to */ -/* s_last. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* int s_first - first sector to erase */ -/* int s_last - last sector to erase */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* Returns 0 for success, 1 for failure. */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*********************************************************************/ -/* NAME: write_buff() - writes a buffer to flash */ -/* */ -/* DESCRIPTION: */ -/* This function copies a buffer, *src, to flash. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* uchar *src - pointer to buffer to write to flash */ -/* ulong addr - address to start write at */ -/* ulong cnt - number of bytes to write to flash */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - OK */ -/* 1 - write timeout */ -/* 2 - Flash not erased */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; (i < 4) && (cnt > 0); ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; (cnt == 0) && (i < 4); ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; (i < 4) && (cnt > 0); ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; (i < 4); ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*********************************************************************/ -/* NAME: write_word() - writes a word to flash */ -/* */ -/* DESCRIPTION: */ -/* This writes a single word to flash. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* ulong dest - address to write */ -/* ulong data - data to write */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - OK */ -/* 1 - write timeout */ -/* 2 - Flash not erased */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} -/*********************************************************************/ -/* End of flash.c */ -/*********************************************************************/ diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c deleted file mode 100644 index f0ed16cd93..0000000000 --- a/board/gw8260/gw8260.c +++ /dev/null @@ -1,639 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the board routines for the GW8260 board. - * - * MODULE DEPENDENCY: - * None - * - * RESTRICTIONS/LIMITATIONS: - * None - * - * Copyright (c) 2001, Advent Networks, Inc. - */ -/*********************************************************************/ - -#include -#include -#include - -/* - * I/O Port configuration table - * - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* TP14 */ - /* PA30 */ { 1, 1, 1, 1, 0, 0 }, /* US_RTS */ - /* PA29 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_DATA */ - /* PA28 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_CLK */ - /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* TP12 */ - /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* IO_STATUS */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CLOCK */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CONFIG */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DONE */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DATA */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD1 */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD3 */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE7 */ - /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE6 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE5 */ - /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE4 */ - /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE3 */ - /* PA8 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE2 */ - /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* LSSI_IN */ - /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE0 */ - /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* DEMOD_RESET_ */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* MOD_RESET_ */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* IO_RESET */ - /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* TX_ENABLE */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* RX_LOCK */ - /* PA0 */ { 1, 0, 0, 1, 0, 1 } /* MPC_RESET_ */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FETH0_TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD3 */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD2 */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD1 */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD0 */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD0 */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD1 */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD2 */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD3 */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD3 */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD2 */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD1 */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD0 */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD0 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD1 */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD2 */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD3 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_RESET_ */ - /* PC30 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_PAUSE_ */ - /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW1 */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW0 */ - /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* TP13 */ - /* PC26 */ { 1, 0, 0, 0, 0, 0 }, /* RXDECDFLG */ - /* PC25 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFAIL */ - /* PC24 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFLG */ - /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* WD_TCL */ - /* PC22 */ { 1, 0, 0, 1, 0, 0 }, /* WD_EN */ - /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* US_TXCLK */ - /* PC20 */ { 1, 0, 0, 0, 0, 0 }, /* DS_RXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_TX_CLK */ - /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* TX_SHUTDOWN_ */ - /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* RS_232_DTR_ */ - /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* TXERR */ - /* PC12 */ { 1, 0, 0, 1, 0, 1 }, /* FETH1_MDDIS */ - /* PC11 */ { 1, 0, 0, 1, 0, 1 }, /* FETH0_MDDIS */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */ - /* PC9 */ { 1, 0, 0, 1, 1, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 1, 1 }, /* SER_NUM */ - /* PC7 */ { 1, 1, 0, 0, 0, 0 }, /* US_CTS */ - /* PC6 */ { 1, 1, 0, 0, 0, 0 }, /* DS_CD_ */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* FETH1_PWRDWN */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* FETH0_PWRDWN */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED2 */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED1 */ - /* PC0 */ { 1, 0, 0, 1, 0, 1 }, /* MPULED0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SCL */ - /* PD13 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED7 */ - /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED6 */ - /* PD11 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED5 */ - /* PD10 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED4 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* RS232_TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* RD232_RXD */ - /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/*********************************************************************/ -/* NAME: checkboard() - Displays the board type and serial number */ -/* */ -/* OUTPUTS: */ -/* Displays the board type and serial number */ -/* */ -/* RETURNS: */ -/* Always returns 1 */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: Advent Networks gw8260\n"); - - if (i > 0) { - printf("SN: %s\n", buf); - } - return 0; -} - - -#if defined (CONFIG_SYS_DRAM_TEST) -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_SDRAM_BASE; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_SDRAM_BASE; - const unsigned int size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_SDRAM_BASE; - const unsigned long size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata, runaddress, runwalk; - - rundata = getenv_yesno("testdramdata") == 1; - runaddress = getenv_yesno("testdramaddress") == 1; - runwalk = getenv_yesno("testdramwalk") == 1; - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM ... "); - } -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - if (mem_test_data () == 1) { - return 1; - } - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - if (mem_test_address () == 1) { - return 1; - } - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - if (mem_test_walk () == 1) { - return 1; - } - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed"); - } - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/*********************************************************************/ -/* NAME: initdram() - initializes SDRAM controller */ -/* */ -/* DESCRIPTION: */ -/* Initializes the MPC8260's SDRAM controller. */ -/* */ -/* INPUTS: */ -/* CONFIG_SYS_IMMR - MPC8260 Internal memory map */ -/* CONFIG_SYS_SDRAM_BASE - Physical start address of SDRAM */ -/* CONFIG_SYS_PSDMR - SDRAM mode register */ -/* CONFIG_SYS_MPTPR - Memory refresh timer prescaler register */ -/* CONFIG_SYS_SDRAM0_SIZE - SDRAM size */ -/* */ -/* RETURNS: */ -/* SDRAM size in bytes */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); - ulong psdmr = CONFIG_SYS_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr = c; - } - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* return total ram size */ - return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024); -} - -/*********************************************************************/ -/* End of gw8260.c */ -/*********************************************************************/ diff --git a/board/h2200/Kconfig b/board/h2200/Kconfig new file mode 100644 index 0000000000..c0e0c1e763 --- /dev/null +++ b/board/h2200/Kconfig @@ -0,0 +1,9 @@ +if TARGET_H2200 + +config SYS_BOARD + default "h2200" + +config SYS_CONFIG_NAME + default "h2200" + +endif diff --git a/board/h2200/MAINTAINERS b/board/h2200/MAINTAINERS new file mode 100644 index 0000000000..b66ff515cf --- /dev/null +++ b/board/h2200/MAINTAINERS @@ -0,0 +1,6 @@ +H2200 BOARD +M: Lukasz Dalek +S: Maintained +F: board/h2200/ +F: include/configs/h2200.h +F: configs/h2200_defconfig diff --git a/board/h2200/Makefile b/board/h2200/Makefile index 26bf14483f..e516e916b4 100644 --- a/board/h2200/Makefile +++ b/board/h2200/Makefile @@ -6,31 +6,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := h2200.o -LIB = $(obj)lib$(BOARD).o +extra-y := h2200-header.bin -COBJS := h2200.o - -SRCS := $(COBJS:.o=.c) h2200-header.S -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) $(obj)h2200-header.bin - -$(obj)h2200-header.o: h2200-header.S - $(CC) $(CFLAGS) -c -o $@ $< - -$(obj)h2200-header.bin: $(obj)h2200-header.o +$(obj)/h2200-header.bin: $(obj)/h2200-header.o $(OBJCOPY) -O binary $< $@ - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/hale/tt01/Kconfig b/board/hale/tt01/Kconfig new file mode 100644 index 0000000000..af9828a4bf --- /dev/null +++ b/board/hale/tt01/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TT01 + +config SYS_BOARD + default "tt01" + +config SYS_VENDOR + default "hale" + +config SYS_SOC + default "mx31" + +config SYS_CONFIG_NAME + default "tt01" + +endif diff --git a/board/hale/tt01/MAINTAINERS b/board/hale/tt01/MAINTAINERS new file mode 100644 index 0000000000..2f582be8f3 --- /dev/null +++ b/board/hale/tt01/MAINTAINERS @@ -0,0 +1,6 @@ +TT01 BOARD +M: Helmut Raiger +S: Maintained +F: board/hale/tt01/ +F: include/configs/tt01.h +F: configs/tt01_defconfig diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile index afdc2c1213..e06a040422 100644 --- a/board/hale/tt01/Makefile +++ b/board/hale/tt01/Makefile @@ -6,30 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o -COBJS := tt01.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := tt01.o +obj-y += lowlevel_init.o diff --git a/board/hermes/Makefile b/board/hermes/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/hermes/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/hermes/flash.c b/board/hermes/flash.c deleted file mode 100644 index 38d3cd3955..0000000000 --- a/board/hermes/flash.c +++ /dev/null @@ -1,444 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_byte (flash_info_t *info, ulong dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - uchar value; - vu_char *caddr = (vu_char *)addr; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0AAA] = 0xAA; - caddr[0x0555] = 0x55; - caddr[0x0AAA] = 0x90; - - value = caddr[0]; - switch (value) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = caddr[2]; /* device ID */ - - switch (value) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[4] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *)info->start[0]; - - *caddr = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_char *addr = (vu_char*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0x80; - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char*)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_char*)(info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0xA0; - - *((vu_char *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c deleted file mode 100644 index 6126b73442..0000000000 --- a/board/hermes/hermes.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) bootstage_mark(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static ulong board_init (void); -static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, - uchar * msg); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00, - 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (HERMES...) - * - * Return code for board revision and network speed - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - - if (l < 0 || strncmp(buf, "HERMES", 6)) { - puts ("### No HW ID - assuming HERMES-PRO"); - } else { - for (i = 0; i < l; i++) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - } - - gd->board_type = board_init (); - - printf (" Rev. %ld.x\n", (gd->board_type >> 16)); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = 0x0400; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 1 to the SDRAM banks at preliminary address - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - /* HERMES-PRO boards have only one bank SDRAM */ - - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mamr = 0xD0802114; - memctl->memc_mcr = 0x80002105; - udelay (1); - memctl->memc_mamr = 0xD0802118; - memctl->memc_mcr = 0x80002130; - udelay (1); - memctl->memc_mamr = 0xD0802114; - memctl->memc_mcr = 0x80002106; - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define PB_LED_3 0x00020000 /* Status LED's */ -#define PB_LED_2 0x00010000 -#define PB_LED_1 0x00008000 -#define PB_LED_0 0x00004000 - -#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3) - -#define PC_REP_SPD1 0x00000800 -#define PC_REP_SPD0 0x00000400 - -#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */ - -#define PB_MAI_4 0x00000010 /* Configuration */ -#define PB_MAI_3 0x00000008 -#define PB_MAI_2 0x00000004 -#define PB_MAI_1 0x00000002 -#define PB_MAI_0 0x00000001 - -#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4) - - -#define PC_REP_MGRPRS 0x0200 -#define PC_REP_SPD 0x0040 /* Select 100 Mbps */ -#define PC_REP_RES 0x0004 -#define PC_BIT14 0x0002 /* ??? */ -#define PC_BIT15 0x0001 /* ??? ENDSL ?? */ - -/* ------------------------------------------------------------------------- */ - -static ulong board_init (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - ulong reg, revision, speed = 100; - int ethspeed; - char *s; - - if ((s = getenv ("ethspeed")) != NULL) { - if (strcmp (s, "100") == 0) { - ethspeed = 100; - } else if (strcmp (s, "10") == 0) { - ethspeed = 10; - } else { - ethspeed = 0; - } - } else { - ethspeed = 0; - } - - /* Configure Port B Output Pins => 0x0003cc3F */ - reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 | - PB_MAI_ALL; - immr->im_cpm.cp_pbpar &= ~reg; - immr->im_cpm.cp_pbodr &= ~reg; - immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */ - immr->im_cpm.cp_pbdir |= reg; - - /* Check hardware revision */ - if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) { - /* - * Revision 3.x hardware - */ - revision = 3; - - immr->im_ioport.iop_pcdat = 0x0240; - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */ - immr->im_ioport.iop_pcdat |= PC_REP_RES; - } else { - immr->im_ioport.iop_pcdat = 0x0002; - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */ - - if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) { - /* - * Revision 2.x hardware: PC9 connected to PB21 - */ - revision = 2; - - if (ethspeed == 0) { - /* both 10 and 100 Mbps allowed: - * select 10 Mbps and autonegotiation - */ - puts (" [10+100]"); - immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */ - speed = 10; - } else if (ethspeed == 10) { - /* we are asked for 10 Mbps, - * so select 10 Mbps - */ - puts (" [10]"); - immr->im_cpm.cp_pbdat = 0; /* ??? */ - speed = 10; - } else { - /* anything else: - * select 100 Mbps - */ - puts (" [100]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1; - /* SPD1:SPD0 = 1:1 - 100 Mbps */ - speed = 100; - } - immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14); - - /* must be run from RAM */ - /* start_lxt980 (speed); */ - /*************************/ - } else { - /* - * Revision 1.x hardware - */ - revision = 1; - - immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */ - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */ - - if (ethspeed == 0) { - /* both 10 and 100 Mbps allowed: - * select 100 Mbps and autonegotiation - */ - puts (" [10+100]"); - immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */ - immr->im_ioport.iop_pcdat |= PC_REP_SPD; - } else if (ethspeed == 10) { - /* we are asked for 10 Mbps, - * so select 10 Mbps - */ - puts (" [10]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */ - } else { - /* anything else: - * select 100 Mbps - */ - puts (" [100]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1; - /* SPD1:SPD0 = 1:1 - 100 Mbps */ - immr->im_ioport.iop_pcdat |= PC_REP_SPD; - } - - immr->im_ioport.iop_pcdat |= PC_REP_RES; - } - } - SHOW_BOOT_PROGRESS(BOOTSTAGE_ID_CHECK_MAGIC); - - return ((revision << 16) | (speed & 0xFFFF)); -} - -/* ------------------------------------------------------------------------- */ - -#define SCC_SM 1 /* Index => SCC2 */ -#define PROFF PROFF_SCC2 - -#define SMI_MSGLEN 8 /* Length of SMI Messages */ - -#define PHYGPCR_ADDR 0x109 /* Port Enable */ -#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */ -#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */ -#define RPRESET_ADDR 0x144 /* Repeater Reset */ - -#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */ -#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */ -#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */ -#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */ -#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */ - -/* ------------------------------------------------------------------------- */ - -/* - * Must run from RAM: - * uses parameter RAM area which is used for stack while running from ROM - */ -void hermes_start_lxt980 (int speed) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm); - volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]); - volatile cbd_t *bd; - volatile hdlc_pram_t *hp; - uchar smimsg[SMI_MSGLEN]; - ushort phypcrval; - uint bd_off; - int pnr; - - printf ("LXT9880: %3d Mbps\n", speed); - - immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */ - immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */ - immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */ - immr->im_ioport.iop_padir |= 0x4000; - - /* get temporary BD; no need for permanent alloc */ - bd_off = dpram_base_align (8); - - bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off); - - bd->cbd_bufaddr = 0; - bd->cbd_datlen = 0; - bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC; - - /* init. baudrate generator BRG4 */ - cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */ - - cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */ - cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */ - - /* init SCC_SM register */ - sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */ - sp->scc_todr = 0x0000; - sp->scc_dsr = 0x7e7e; - - /* init. SCC_SM parameter area */ - hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF]; - - hp->tbase = bd_off; /* offset from beginning of DPRAM */ - - hp->rfcr = 0x18; - hp->tfcr = 0x18; - hp->mrblr = 10; - - hp->c_mask = 0x0000f0b8; - hp->c_pres = 0x0000ffff; - - hp->disfc = 0; - hp->crcec = 0; - hp->abtsc = 0; - hp->nmarc = 0; - hp->retrc = 0; - - hp->mflr = 10; - - hp->rfthr = 1; - - hp->hmask = 0; - hp->haddr1 = 0; - hp->haddr2 = 0; - hp->haddr3 = 0; - hp->haddr4 = 0; - - cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */ - while (cp->cp_cpcr & CPM_CR_FLG); - - /* clear all outstanding SCC events */ - sp->scc_scce = ~0; - - /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */ - sp->scc_gsmrh = 0; - sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 | - SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC; - -#if 0 - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (RPRESET_ADDR << 4) & 0xf0; - smimsg[3] = RPRESET_ADDR >> 4; - smimsg[4] = 0x01; - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); -#endif - - smimsg[0] = 0x7f; /* BROADCAST */ - smimsg[1] = 0x34; /* ASSIGN HUB ID */ - smimsg[2] = 0x00; - smimsg[3] = 0x00; - smimsg[4] = 0x00; /* HUB ID = 0 */ - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - smimsg[0] = 0x7f; /* BROADCAST */ - smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */ - smimsg[2] = 0x00; /* ADDRESS = 0 */ - smimsg[3] = 0x00; - smimsg[4] = 0x00; /* DATA = 0 */ - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - if (speed == 100) { - phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */ - } else { - phypcrval = 0; /* 10 MBIT, disable autoneg. */ - } - - /* send MSGs */ - for (pnr = 0; pnr < 8; pnr++) { - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0; - smimsg[3] = (PHYPCR_ADDR + pnr) >> 4; - smimsg[4] = (unsigned char) (phypcrval & 0xff); - smimsg[5] = (unsigned char) (phypcrval >> 8); - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - } - - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0; - smimsg[3] = PHYGPCR_ADDR >> 4; - smimsg[4] = 0xff; /* enable port 1-8 */ - smimsg[5] = 0x01; /* enable MII1 (0x01) */ - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0; - smimsg[3] = LEDPCR_ADDR >> 4; - smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */ - smimsg[5] = 0xaa; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - /* - * Disable Transmitter (so that we can free the BD, too) - */ - sp->scc_gsmrl &= ~SCC_GSMRL_ENT; -} - -/* ------------------------------------------------------------------------- */ - -static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, - uchar * msg) -{ -#ifdef DEBUG - unsigned hub, chip, cmd, length, addr; - - hub = msg[0] & 0x1F; - chip = msg[0] >> 5; - cmd = msg[1] & 0x1F; - length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3); - addr = (msg[2] >> 4) | (msg[3] << 4); - - printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: " - "%02x %02x %02x %02x\n", - hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]); -#endif /* DEBUG */ - - bd->cbd_bufaddr = (uint) msg; - bd->cbd_datlen = SMI_MSGLEN; - bd->cbd_sc |= BD_SC_READY; - - /* wait for msg transmitted */ - while ((sp->scc_scce & 0x0002) == 0); - /* clear all events */ - sp->scc_scce = ~0; -} - -/* ------------------------------------------------------------------------- */ - -void show_boot_progress (int status) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* let things compatible */ - if (status < -BOOTSTAGE_ID_POST_FAIL_R) - status = -1; - status ^= 0x0F; - status = (status & 0x0F) << 14; - immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status; -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds deleted file mode 100644 index 9419f83a70..0000000000 --- a/board/hermes/u-boot.lds +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - board/hermes/libhermes.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug deleted file mode 100644 index f34c07ba2b..0000000000 --- a/board/hermes/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - arch/powerpc/cpu/mpc8xx/interrupts.o (.text) - arch/powerpc/lib/time.o (.text) - arch/powerpc/lib/ticks.o (.text) - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/hidden_dragon/Makefile b/board/hidden_dragon/Makefile deleted file mode 100644 index 9d46b9b0da..0000000000 --- a/board/hidden_dragon/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/hidden_dragon/README b/board/hidden_dragon/README deleted file mode 100644 index 529fe2be0e..0000000000 --- a/board/hidden_dragon/README +++ /dev/null @@ -1,60 +0,0 @@ -U-Boot for Hidden Dragon board ------------------------------- - -Hidden Dragon is a MPC824x-based board by Motorola. For the most -part it is similar to Sandpoint8245 board. So unless otherwise -mentioned, the codes in this directory are adapted from ../sandpoint -directory. - -Apparently there are very few of this board out there. Even Motorola -website does not have any info on it. - -RAM: - start = 0x0000 0000 - size = 0x0200 0000 (32 MB) - -Flash: - BANK ONE: - start = 0xFFE0 0000 - size = 0x0020 0000 (2 MB) - flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits) - flash sectors = 16K, 2x8K, 32K, 31x64K - - BANK TWO: - NONE - -The processor interrupt vectors reside on the first 256 bytes -starting from address 0xFFF00000. The "reset vector" (first -instruction executed after reset) is located on 0xFFF0 0100. - -U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the second sector of the first flash bank, starting from -0xFFE04000 until 0xFFE06000 (8KB). - -Network: - - RTL8139 chip on the base board (SUPPORTED) - - RTL8129 chip on the processor board (NOT SUPPORTED) - -Serial: - - Two NS16550 compatible UART on the processor board (SUPPORTED) - - One NS16550 compatible UART on the base board (UNTESTED) - -Misc: - VIA686A PCI SuperIO peripheral controller - - 2 USB ports (UNTESTED) - - 2 PS2 ports (UNTESTED) - - Parallel port (UNTESTED) - - IDE & floppy interface (UNTESTED) - - S3 Savage4 video card (UNTESTED) - -TODO: ------ -- Support for the VIA686A based peripherals -- The RTL8139 driver frequently gives rx error. -- Support for RTL8129 network controller. (Why is the support removed from - rtl8139.c driver?) - -(C) Copyright 2004 -Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S deleted file mode 100644 index 5a9b924ef9..0000000000 --- a/board/hidden_dragon/early_init.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Thomas Koeller, tkoeller@gmx.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ 1 -#endif - -#include -#include -#include -#include -#include - -#if defined(USE_DINK32) - /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) -#else - #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) -#endif - - .text - - /* Values to program into memory controller registers */ -tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT - .long MCCR3 - .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \ - (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT) - .long MCCR4 - .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \ - (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \ - (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) - .long MSAR1 - .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR1 - .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MSAR2 - .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR2 - .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR1 - .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR1 - .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR2 - .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR2 - .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long 0 - - - /* - * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This - * must be done in assembly, since we have no stack at this point. - */ - .global early_init_f -early_init_f: - mflr r10 - - /* basic memory controller configuration */ - lis r3, CONFIG_ADDR_HIGH - lis r4, CONFIG_DATA_HIGH - bl lab -lab: mflr r5 - lwzu r0, tbl - lab(r5) -loop: lwz r1, 4(r5) - stwbrx r0, 0, r3 - eieio - stwbrx r1, 0, r4 - eieio - lwzu r0, 8(r5) - cmpli cr0, 0, r0, 0 - bne cr0, loop - - /* set bank enable bits */ - lis r0, MBER@h - ori r0, 0, MBER@l - li r1, CONFIG_SYS_BANK_ENABLE - stwbrx r0, 0, r3 - eieio - stb r1, 0(r4) - eieio - - /* delay loop */ - lis r0, 0x0003 - mtctr r0 -delay: bdnz delay - - /* enable memory controller */ - lis r0, MCCR1@h - ori r0, 0, MCCR1@l - stwbrx r0, 0, r3 - eieio - lwbrx r0, 0, r4 - oris r0, 0, MCCR1_MEMGO@h - stwbrx r0, 0, r4 - eieio - - /* set up stack pointer */ - lis r1, CONFIG_SYS_INIT_SP_OFFSET@h - ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l - - mtlr r10 - blr diff --git a/board/hidden_dragon/flash.c b/board/hidden_dragon/flash.c deleted file mode 100644 index fc91a03aed..0000000000 --- a/board/hidden_dragon/flash.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * (C) Copyright 2004 - * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com - * - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*flash command address offsets*/ - -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) - __attribute__ ((const)); - -typedef struct { - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = { - {(FLASH_WORD_SIZE) AMD_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for (p = &chip_map[0]; - p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if (p->extval == chip) { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for (p = &mfct_map[0]; - p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if (p->extval == mfct) { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - -unsigned long flash_init (void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - /* Enable writes to Hidden Dragon flash */ - { - register unsigned char temp; - - CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, - temp); - temp &= ~0x20; /* clear BIOSWP bit */ - CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, - temp); - } - - for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE *const flash = - (FLASH_WORD_SIZE *) base_address; - - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; - __asm__ __volatile__ ("sync"); - - pflinfo->flash_id = - flash_id (flash[0x0], flash[0x2 + 14 * i]); - - switch (pflinfo->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for (j = 0; j < 8; j++) { - pflinfo->start[j] = - base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for (j = 1; j < 16; j++) { - pflinfo->start[j + 3] = - base_address + 0x00010000 * j; - } - break; - default: - /* The chip used is not listed in flash_id - TODO: Change this to explicitly detect the flash type - */ - { - int sector_addr = base_address; - - pflinfo->size = 0x00200000; - pflinfo->sector_count = 35; - pflinfo->start[0] = sector_addr; - sector_addr += 0x4000; /* 16K */ - pflinfo->start[1] = sector_addr; - sector_addr += 0x2000; /* 8K */ - pflinfo->start[2] = sector_addr; - sector_addr += 0x2000; /* 8K */ - pflinfo->start[3] = sector_addr; - sector_addr += 0x8000; /* 32K */ - - for (j = 4; j < 35; j++) { - pflinfo->start[j] = sector_addr; - sector_addr += 0x10000; /* 64K */ - } - } - break; - } - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__ ("sync"); - } - - /* only have 1 bank */ - return flash_info[0].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) - && erased; flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + - ((info->start[sect] - - info->start[0]) << sh8b)); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c deleted file mode 100644 index 8d47f37955..0000000000 --- a/board/hidden_dragon/hidden_dragon.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2004 - * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com - * - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Hidden Dragon " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " ##Test not implemented yet##\n"); - /* TODO: Implement board test */ - return 0; -} - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_hidden_dragon_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_hidden_dragon_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/hidden_dragon/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/highbank/MAINTAINERS b/board/highbank/MAINTAINERS new file mode 100644 index 0000000000..69ddeddd60 --- /dev/null +++ b/board/highbank/MAINTAINERS @@ -0,0 +1,6 @@ +HIGHBANK BOARD +M: Rob Herring +S: Maintained +F: board/highbank/ +F: include/configs/highbank.h +F: configs/highbank_defconfig diff --git a/board/highbank/Makefile b/board/highbank/Makefile index 3aa134ab49..d3eb23220b 100644 --- a/board/highbank/Makefile +++ b/board/highbank/Makefile @@ -5,29 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := highbank.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := highbank.o diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 8cdcea8aac..fc2385cf31 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -9,16 +9,24 @@ #include #include -#include +#include #include +#define HB_AHCI_BASE 0xffe08000 + #define HB_SREG_A9_PWR_REQ 0xfff3cf00 #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 +#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20 + #define HB_PWR_SUSPEND 0 #define HB_PWR_SOFT_RESET 1 #define HB_PWR_HARD_RESET 2 #define HB_PWR_SHUTDOWN 3 +#define PWRDOM_STAT_SATA 0x80000000 +#define PWRDOM_STAT_PCI 0x40000000 +#define PWRDOM_STAT_EMMC 0x20000000 + DECLARE_GLOBAL_DATA_PTR; /* @@ -43,14 +51,24 @@ int board_eth_init(bd_t *bis) return rc; } +#ifdef CONFIG_SCSI_AHCI_PLAT +void scsi_init(void) +{ + u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); + + if (reg & PWRDOM_STAT_SATA) { + ahci_init(HB_AHCI_BASE); + scsi_scan(1); + } +} +#endif + +#ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { char envbuffer[16]; u32 boot_choice; - ahci_init(0xffe08000); - scsi_scan(1); - boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff; sprintf(envbuffer, "bootcmd%d", boot_choice); if (getenv(envbuffer)) { @@ -61,6 +79,7 @@ int misc_init_r(void) return 0; } +#endif int dram_init(void) { @@ -74,6 +93,24 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; } +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *fdt, bd_t *bd) +{ + static const char disabled[] = "disabled"; + u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); + + if (!(reg & PWRDOM_STAT_SATA)) + do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status", + disabled, sizeof(disabled), 1); + + if (!(reg & PWRDOM_STAT_EMMC)) + do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status", + disabled, sizeof(disabled), 1); + + return 0; +} +#endif + void reset_cpu(ulong addr) { writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); diff --git a/board/htkw/mcx/Kconfig b/board/htkw/mcx/Kconfig new file mode 100644 index 0000000000..25ba548dab --- /dev/null +++ b/board/htkw/mcx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MCX + +config SYS_BOARD + default "mcx" + +config SYS_VENDOR + default "htkw" + +config SYS_CONFIG_NAME + default "mcx" + +endif diff --git a/board/htkw/mcx/MAINTAINERS b/board/htkw/mcx/MAINTAINERS new file mode 100644 index 0000000000..c5f88733d2 --- /dev/null +++ b/board/htkw/mcx/MAINTAINERS @@ -0,0 +1,6 @@ +MCX BOARD +M: Ilya Yanok +S: Maintained +F: board/htkw/mcx/ +F: include/configs/mcx.h +F: configs/mcx_defconfig diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile index 641e61e708..20149ba809 100644 --- a/board/htkw/mcx/Makefile +++ b/board/htkw/mcx/Makefile @@ -6,21 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := mcx.o diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 653d7ea71d..4330cf0ddb 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -40,9 +40,10 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); } int ehci_hcd_stop(int index) diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h index 703dbeccfd..d6c5df203e 100644 --- a/board/htkw/mcx/mcx.h +++ b/board/htkw/mcx/mcx.h @@ -325,8 +325,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \ - /* SYS_nRESWARM */\ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ @@ -341,7 +339,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ diff --git a/board/hymod/Makefile b/board/hymod/Makefile deleted file mode 100644 index 6e9f436acb..0000000000 --- a/board/hymod/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c deleted file mode 100644 index e54640f2d2..0000000000 --- a/board/hymod/bsp.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01 - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/*----------------------------------------------------------------------- - * Board Special Commands: FPGA load/store, EEPROM erase - */ - -#if defined(CONFIG_CMD_BSP) - -#define LOAD_SUCCESS 0 -#define LOAD_FAIL_NOCONF 1 -#define LOAD_FAIL_NOINIT 2 -#define LOAD_FAIL_NODONE 3 - -#define STORE_SUCCESS 0 - -/* - * Programming the Hymod FPGAs - * - * The 8260 io port config table is set up so that the INIT pin is - * held Low (Open Drain output 0) - this will delay the automatic - * Power-On config until INIT is released (by making it an input). - * - * If the FPGA has been programmed before, then the assertion of PROGRAM - * will initiate configuration (i.e. it begins clearing the RAM). - * - * When the FPGA is ready to receive configuration data (either after - * releasing INIT after Power-On, or after asserting PROGRAM), it will - * pull INIT high. - * - * Notes from Paul Dunn: - * - * 1. program pin should be forced low for >= 300ns - * (about 20 bus clock cycles minimum). - * - * 2. then wait for init to go high, which signals - * that the FPGA has cleared its internal memory - * and is ready to load - * - * 3. perform load writes of entire config file - * - * 4. wait for done to go high, which should be - * within a few bus clock cycles. If done has not - * gone high after reasonable period, then load - * has not worked (wait several ms?) - */ - -int -fpga_load(int mezz, const uchar *addr, ulong size) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - xlx_info_t *fp; - xlx_iopins_t *fpgaio; - volatile uchar *fpgabase; - volatile uint cnt; - const uchar *eaddr = addr + size; - int result; - - if (mezz) - fp = &cp->mezz.xlx[0]; - else - fp = &cp->main.xlx[0]; - - if (!fp->mmap.prog.exists) - return (LOAD_FAIL_NOCONF); - - fpgabase = (uchar *)fp->mmap.prog.base; - fpgaio = &fp->iopins; - - /* set enable HIGH if required */ - if (fpgaio->enable_pin.flag) - iopin_set_high (&fpgaio->enable_pin); - - /* ensure INIT is released (set it to be an input) */ - iopin_set_in (&fpgaio->init_pin); - - /* toggle PROG Low then High (will already be Low after Power-On) */ - iopin_set_low (&fpgaio->prog_pin); - udelay (1); /* minimum 300ns - 1usec should do it */ - iopin_set_high (&fpgaio->prog_pin); - - /* wait for INIT High */ - cnt = 0; - while (!iopin_is_high (&fpgaio->init_pin)) - if (++cnt == 10000000) { - result = LOAD_FAIL_NOINIT; - goto done; - } - - /* write configuration data */ - while (addr < eaddr) - *fpgabase = *addr++; - - /* wait for DONE High */ - cnt = 0; - while (!iopin_is_high (&fpgaio->done_pin)) - if (++cnt == 100000000) { - result = LOAD_FAIL_NODONE; - goto done; - } - - /* success */ - result = LOAD_SUCCESS; - - done: - - if (fpgaio->enable_pin.flag) - iopin_set_low (&fpgaio->enable_pin); - - return (result); -} - -/* ------------------------------------------------------------------------- */ -int -do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - uchar *addr, *save_addr; - ulong size; - int mezz, arg, result; - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strcmp (argv[1], "info") == 0) { - printf ("\nHymod FPGA Info...\n"); - printf ("\t\t\t\tAddress\t\tSize\n"); - printf ("\tMain Configuration:\t0x%08x\t%d\n", - FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE); - printf ("\tMain Register:\t\t0x%08x\t%d\n", - FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE); - printf ("\tMain Port:\t\t0x%08x\t%d\n", - FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE); - printf ("\tMezz Configuration:\t0x%08x\t%d\n", - FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE); - return 0; - } - break; - - case 3: - if (strcmp (argv[1], "store") == 0) { - addr = (uchar *) simple_strtoul (argv[2], NULL, 16); - - save_addr = addr; -#if 0 - /* fpga readback unimplemented */ - while (more readback data) - *addr++ = *fpga; - result = error ? STORE_FAIL_XXX : STORE_SUCCESS; -#else - result = STORE_SUCCESS; -#endif - - if (result == STORE_SUCCESS) { - printf ("SUCCEEDED (%d bytes)\n", - addr - save_addr); - return 0; - } else - printf ("FAILED (%d bytes)\n", - addr - save_addr); - return 1; - } - break; - - case 4: - if (strcmp (argv[1], "tftp") == 0) { - copy_filename (BootFile, argv[2], sizeof (BootFile)); - load_addr = simple_strtoul (argv[3], NULL, 16); - NetBootFileXferSize = 0; - - if (NetLoop(TFTPGET) <= 0) { - printf ("tftp transfer failed - aborting " - "fgpa load\n"); - return 1; - } - - if (NetBootFileXferSize == 0) { - printf ("can't determine file size - " - "aborting fpga load\n"); - return 1; - } - - printf ("File transfer succeeded - " - "beginning fpga load..."); - - result = fpga_load (0, (uchar *) load_addr, - NetBootFileXferSize); - - if (result == LOAD_SUCCESS) { - printf ("SUCCEEDED\n"); - return 0; - } else if (result == LOAD_FAIL_NOCONF) - printf ("FAILED (no CONF)\n"); - else if (result == LOAD_FAIL_NOINIT) - printf ("FAILED (no INIT)\n"); - else - printf ("FAILED (no DONE)\n"); - return 1; - - } - /* fall through ... */ - - case 5: - if (strcmp (argv[1], "load") == 0) { - if (argc == 5) { - if (strcmp (argv[2], "main") == 0) - mezz = 0; - else if (strcmp (argv[2], "mezz") == 0) - mezz = 1; - else { - printf ("FPGA type must be either " - "`main' or `mezz'\n"); - return 1; - } - arg = 3; - } else { - mezz = 0; - arg = 2; - } - - addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16); - size = (ulong) simple_strtoul (argv[arg], NULL, 16); - - result = fpga_load (mezz, addr, size); - - if (result == LOAD_SUCCESS) { - printf ("SUCCEEDED\n"); - return 0; - } else if (result == LOAD_FAIL_NOCONF) - printf ("FAILED (no CONF)\n"); - else if (result == LOAD_FAIL_NOINIT) - printf ("FAILED (no INIT)\n"); - else - printf ("FAILED (no DONE)\n"); - return 1; - } - break; - - default: - break; - } - - return cmd_usage(cmdtp); -} -U_BOOT_CMD( - fpga, 6, 1, do_fpga, - "FPGA sub-system", - "load [type] addr size\n" - " - write the configuration data at memory address `addr',\n" - " size `size' bytes, into the FPGA of type `type' (either\n" - " `main' or `mezz', default `main'). e.g.\n" - " `fpga load 100000 7d8f'\n" - " loads the main FPGA with config data at address 100000\n" - " HEX, size 7d8f HEX (32143 DEC) bytes\n" - "fpga tftp file addr\n" - " - transfers `file' from the tftp server into memory at\n" - " address `addr', then writes the entire file contents\n" - " into the main FPGA\n" - "fpga store addr\n" - " - read configuration data from the main FPGA (the mezz\n" - " FPGA is write-only), into address `addr'. There must be\n" - " enough memory available at `addr' to hold all the config\n" - " data - the size of which is determined by VC:???\n" - "fpga info\n" - " - print information about the Hymod FPGA, namely the\n" - " memory addresses at which the four FPGA local bus\n" - " address spaces appear in the physical address space" -); -/* ------------------------------------------------------------------------- */ -int -do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - uchar data[HYMOD_EEPROM_SIZE]; - uint addr = CONFIG_SYS_I2C_EEPROM_ADDR; - - switch (argc) { - - case 1: - addr |= HYMOD_EEOFF_MAIN; - break; - - case 2: - if (strcmp (argv[1], "main") == 0) { - addr |= HYMOD_EEOFF_MAIN; - break; - } - if (strcmp (argv[1], "mezz") == 0) { - addr |= HYMOD_EEOFF_MEZZ; - break; - } - /* fall through ... */ - - default: - return cmd_usage(cmdtp); - } - - memset (data, 0, HYMOD_EEPROM_SIZE); - - eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE); - - return 0; -} -U_BOOT_CMD( - eeclear, 1, 0, do_eecl, - "Clear the eeprom on a Hymod board", - "[type]\n" - " - write zeroes into the EEPROM on the board of type `type'\n" - " (`type' is either `main' or `mezz' - default `main')\n" - " Note: the EEPROM write enable jumper must be installed" -); - -/* ------------------------------------------------------------------------- */ - -int -do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ -#if 0 - int rc; -#endif -#ifdef CONFIG_ETHER_LOOPBACK_TEST - extern void eth_loopback_test (void); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - - printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n"); - -#if 0 - /* Load FPGA with test program */ - - printf ("Loading test FPGA program ..."); - - rc = fpga_load (0, test_bitfile, sizeof (test_bitfile)); - - switch (rc) { - - case LOAD_SUCCESS: - printf (" SUCCEEDED\n"); - break; - - case LOAD_FAIL_NOCONF: - printf (" FAILED (no configuration space defined)\n"); - return 1; - - case LOAD_FAIL_NOINIT: - printf (" FAILED (timeout - no INIT signal seen)\n"); - return 1; - - case LOAD_FAIL_NODONE: - printf (" FAILED (timeout - no DONE signal seen)\n"); - return 1; - - default: - printf (" FAILED (unknown return code from fpga_load\n"); - return 1; - } - - /* run Local Bus <=> Xilinx tests */ - - /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */ - - /* run SDRAM test */ -#endif - -#ifdef CONFIG_ETHER_LOOPBACK_TEST - /* run Ethernet test */ - eth_loopback_test (); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - - return 0; -} - -#endif diff --git a/board/hymod/config.mk b/board/hymod/config.mk deleted file mode 100644 index abcd2d50ac..0000000000 --- a/board/hymod/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# HYMOD boards -# - -PLATFORM_CPPFLAGS += -I$(TOPDIR) - -OBJCFLAGS = --remove-section=.ppcenv diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c deleted file mode 100644 index ffb0df1976..0000000000 --- a/board/hymod/eeprom.c +++ /dev/null @@ -1,678 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* imports from fetch.c */ -extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); - -/* imports from input.c */ -extern int hymod_get_serno (const char *); - -/* this is relative to the root of the server's tftp directory */ -static char *def_bddb_cfgdir = "/hymod/bddb"; - -static int -hymod_eeprom_load (int which, hymod_eeprom_t *ep) -{ - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - unsigned offset = 0; - uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp; - hymod_eehdr_t hdr; - ulong len, crc; - - memset (ep, 0, sizeof *ep); - - eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr)); - offset += sizeof (hdr); - - if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER || - (len = hdr.len) > HYMOD_EEPROM_MAXLEN) - return (0); - - eeprom_read (dev_addr, offset, data, len); - offset += len; - - eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong)); - offset += sizeof (ulong); - - if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc) - return (0); - - ep->ver = hdr.ver; - dp = data; edp = dp + len; - - for (;;) { - ulong rtyp; - uchar rlen, *rdat; - - rtyp = *dp++; - if ((rtyp & 0x80) == 0) - rlen = *dp++; - else { - uchar islarge = rtyp & 0x40; - - rtyp = ((rtyp & 0x3f) << 8) | *dp++; - if (islarge) { - rtyp = (rtyp << 8) | *dp++; - rtyp = (rtyp << 8) | *dp++; - } - - rlen = *dp++; - rlen = (rlen << 8) | *dp++; - if (islarge) { - rlen = (rlen << 8) | *dp++; - rlen = (rlen << 8) | *dp++; - } - } - - if (rtyp == 0) - break; - - rdat = dp; - dp += rlen; - - if (dp > edp) /* error? */ - break; - - switch (rtyp) { - - case HYMOD_EEREC_SERNO: /* serial number */ - if (rlen == sizeof (ulong)) - ep->serno = \ - ((ulong)rdat[0] << 24) | \ - ((ulong)rdat[1] << 16) | \ - ((ulong)rdat[2] << 8) | \ - (ulong)rdat[3]; - break; - - case HYMOD_EEREC_DATE: /* date */ - if (rlen == sizeof (hymod_date_t)) { - ep->date.year = ((ushort)rdat[0] << 8) | \ - (ushort)rdat[1]; - ep->date.month = rdat[2]; - ep->date.day = rdat[3]; - } - break; - - case HYMOD_EEREC_BATCH: /* batch */ - if (rlen <= HYMOD_MAX_BATCH) - memcpy (ep->batch, rdat, ep->batchlen = rlen); - break; - - case HYMOD_EEREC_TYPE: /* board type */ - if (rlen == 1) - ep->bdtype = *rdat; - break; - - case HYMOD_EEREC_REV: /* board revision */ - if (rlen == 1) - ep->bdrev = *rdat; - break; - - case HYMOD_EEREC_SDRAM: /* sdram size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) { - int i; - - for (i = 0; i < rlen; i++) - ep->sdramsz[i] = rdat[i]; - ep->nsdram = rlen; - } - break; - - case HYMOD_EEREC_FLASH: /* flash size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) { - int i; - - for (i = 0; i < rlen; i++) - ep->flashsz[i] = rdat[i]; - ep->nflash = rlen; - } - break; - - case HYMOD_EEREC_ZBT: /* zbt ram size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) { - int i; - - for (i = 0; i < rlen; i++) - ep->zbtsz[i] = rdat[i]; - ep->nzbt = rlen; - } - break; - - case HYMOD_EEREC_XLXTYP: /* xilinx fpga type(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].type = rdat[i]; - ep->nxlx = rlen; - } - break; - - case HYMOD_EEREC_XLXSPD: /* xilinx fpga speed(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].speed = rdat[i]; - } - break; - - case HYMOD_EEREC_XLXTMP: /* xilinx fpga temperature(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].temp = rdat[i]; - } - break; - - case HYMOD_EEREC_XLXGRD: /* xilinx fpga grade(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].grade = rdat[i]; - } - break; - - case HYMOD_EEREC_CPUTYP: /* CPU type */ - if (rlen == 1) - ep->mpc.type = *rdat; - break; - - case HYMOD_EEREC_CPUSPD: /* CPU speed */ - if (rlen == 1) - ep->mpc.cpuspd = *rdat; - break; - - case HYMOD_EEREC_CPMSPD: /* CPM speed */ - if (rlen == 1) - ep->mpc.cpmspd = *rdat; - break; - - case HYMOD_EEREC_BUSSPD: /* bus speed */ - if (rlen == 1) - ep->mpc.busspd = *rdat; - break; - - case HYMOD_EEREC_HSTYPE: /* hs-serial chip type */ - if (rlen == 1) - ep->hss.type = *rdat; - break; - - case HYMOD_EEREC_HSCHIN: /* num hs-serial input chans */ - if (rlen == 1) - ep->hss.nchin = *rdat; - break; - - case HYMOD_EEREC_HSCHOUT: /* num hs-serial output chans */ - if (rlen == 1) - ep->hss.nchout = *rdat; - break; - - default: /* ignore */ - break; - } - } - - return (1); -} - -/* maps an ascii "name=value" into a binary eeprom data record */ -typedef - struct _eerec_map { - char *name; - uint type; - uchar *(*handler) \ - (struct _eerec_map *, uchar *, uchar *, uchar *); - uint length; - uint maxlen; - } -eerec_map_t; - -static uchar * -uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - char *eval; - ulong lval; - - lval = simple_strtol ((char *)val, &eval, 10); - - if ((uchar *)eval == val || *eval != '\0') { - printf ("%s rec (%s) is not a valid uint\n", rp->name, val); - return (NULL); - } - - if (dp + 2 + rp->length > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = rp->length; - - switch (rp->length) { - - case 1: - if (lval >= 256) { - printf ("%s rec value (%lu) out of range (0-255)\n", - rp->name, lval); - return (NULL); - } - *dp++ = lval; - break; - - case 2: - if (lval >= 65536) { - printf ("%s rec value (%lu) out of range (0-65535)\n", - rp->name, lval); - return (NULL); - } - *dp++ = lval >> 8; - *dp++ = lval; - break; - - case 4: - *dp++ = lval >> 24; - *dp++ = lval >> 16; - *dp++ = lval >> 8; - *dp++ = lval; - break; - - default: - printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length); - return (NULL); - } - - return (dp); -} - -static uchar * -date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - hymod_date_t date; - char *p = (char *)val; - char *ep; - ulong lval; - - lval = simple_strtol (p, &ep, 10); - if (ep == p || *ep++ != '-') { -bad_date: - printf ("%s rec (%s) is not a valid date\n", rp->name, val); - return (NULL); - } - if (lval >= 65536) - goto bad_date; - date.year = lval; - - lval = simple_strtol (p = ep, &ep, 10); - if (ep == p || *ep++ != '-' || lval == 0 || lval > 12) - goto bad_date; - date.month = lval; - - lval = simple_strtol (p = ep, &ep, 10); - if (ep == p || *ep != '\0' || lval == 0 || lval > 31) - goto bad_date; - date.day = lval; - - if (dp + 2 + rp->length > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = rp->length; - *dp++ = date.year >> 8; - *dp++ = date.year; - *dp++ = date.month; - *dp++ = date.day; - - return (dp); -} - -static uchar * -string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - uint len; - - if ((len = strlen ((char *)val)) > rp->maxlen) { - printf ("%s rec (%s) string is too long (%d>%d)\n", - rp->name, val, len, rp->maxlen); - return (NULL); - } - - if (dp + 2 + len > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = len; - memcpy (dp, val, len); - dp += len; - - return (dp); -} - -static uchar * -bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - uchar bytes[HYMOD_MAX_BYTES], nbytes, *p; - char *ep; - - for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) { - ulong lval; - - lval = simple_strtol ((char *)p, &ep, 10); - if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \ - lval >= 256) { - printf ("%s rec (%s) byte array has invalid uint\n", - rp->name, val); - return (NULL); - } - if (nbytes >= HYMOD_MAX_BYTES) { - printf ("%s rec (%s) byte array too long\n", - rp->name, val); - return (NULL); - } - bytes[nbytes++] = lval; - - if (*ep != '\0') - ep++; - } - - if (dp + 2 + nbytes > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = nbytes; - memcpy (dp, bytes, nbytes); - dp += nbytes; - - return (dp); -} - -static eerec_map_t eerec_map[] = { - /* name type handler len max */ - { "serno", HYMOD_EEREC_SERNO, uint_handler, 4, 0 }, - { "date", HYMOD_EEREC_DATE, date_handler, 4, 0 }, - { "batch", HYMOD_EEREC_BATCH, string_handler, 0, HYMOD_MAX_BATCH }, - { "type", HYMOD_EEREC_TYPE, uint_handler, 1, 0 }, - { "rev", HYMOD_EEREC_REV, uint_handler, 1, 0 }, - { "sdram", HYMOD_EEREC_SDRAM, bytes_handler, 0, HYMOD_MAX_SDRAM }, - { "flash", HYMOD_EEREC_FLASH, bytes_handler, 0, HYMOD_MAX_FLASH }, - { "zbt", HYMOD_EEREC_ZBT, bytes_handler, 0, HYMOD_MAX_ZBT }, - { "xlxtyp", HYMOD_EEREC_XLXTYP, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxspd", HYMOD_EEREC_XLXSPD, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxtmp", HYMOD_EEREC_XLXTMP, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxgrd", HYMOD_EEREC_XLXGRD, bytes_handler, 0, HYMOD_MAX_XLX }, - { "cputyp", HYMOD_EEREC_CPUTYP, uint_handler, 1, 0 }, - { "cpuspd", HYMOD_EEREC_CPUSPD, uint_handler, 1, 0 }, - { "cpmspd", HYMOD_EEREC_CPMSPD, uint_handler, 1, 0 }, - { "busspd", HYMOD_EEREC_BUSSPD, uint_handler, 1, 0 }, - { "hstype", HYMOD_EEREC_HSTYPE, uint_handler, 1, 0 }, - { "hschin", HYMOD_EEREC_HSCHIN, uint_handler, 1, 0 }, - { "hschout", HYMOD_EEREC_HSCHOUT, uint_handler, 1, 0 }, -}; - -static int neerecs = sizeof eerec_map / sizeof eerec_map[0]; - -static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp; - -static int -eerec_callback (uchar *name, uchar *val) -{ - eerec_map_t *rp; - - for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++) - if (strcmp ((char *)name, rp->name) == 0) - break; - - if (rp >= &eerec_map[neerecs]) - return (0); - - if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL) - return (0); - - return (1); -} - -static int -hymod_eeprom_fetch(int which, char *filename, ulong addr) -{ - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0]; - ulong crc; - - memset (hp, 0, sizeof *hp); - hp->id = HYMOD_EEPROM_ID; - hp->ver = HYMOD_EEPROM_VER; - - dp = sdp = (uchar *)(hp + 1); - edp = dp + HYMOD_EEPROM_MAXLEN; - - if (fetch_and_parse (filename, addr, eerec_callback) == 0) - return (0); - - hp->len = dp - sdp; - - crc = crc32 (0, data, dp - data); - memcpy (dp, &crc, sizeof (ulong)); - dp += sizeof (ulong); - - eeprom_write (dev_addr, 0, data, dp - data); - - return (1); -} - -static char *type_vals[] = { - "NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY" -}; - -static char *xlxtyp_vals[] = { - "NONE", "XCV300E", "XCV400E", "XCV600E" -}; - -static char *xlxspd_vals[] = { - "NONE", "6", "7", "8" -}; - -static char *xlxtmp_vals[] = { - "NONE", "COM", "IND" -}; - -static char *xlxgrd_vals[] = { - "NONE", "NORMAL", "ENGSAMP" -}; - -static char *cputyp_vals[] = { - "NONE", "MPC8260" -}; - -static char *clk_vals[] = { - "NONE", "33", "66", "100", "133", "166", "200" -}; - -static char *hstype_vals[] = { - "NONE", "AMCC-S2064A" -}; - -static void -print_mem (char *l, char *s, uchar n, uchar a[]) -{ - if (n > 0) { - if (n == 1) - printf ("%s%dMB %s", s, 1 << (a[0] - 20), l); - else { - ulong t = 0; - int i; - - for (i = 0; i < n; i++) - t += 1 << (a[i] - 20); - - printf ("%s%luMB %s (%d banks:", s, t, l, n); - - for (i = 0; i < n; i++) - printf ("%dMB%s", - 1 << (a[i] - 20), - (i == n - 1) ? ")" : ","); - } - } - else - printf ("%sNO %s", s, l); -} - -void -hymod_eeprom_print (hymod_eeprom_t *ep) -{ - int i; - - printf (" Hymod %s board, rev %03d\n", - type_vals[ep->bdtype], ep->bdrev); - - printf (" serial #: %010lu, date %04d-%02d-%02d", - ep->serno, ep->date.year, ep->date.month, ep->date.day); - if (ep->batchlen > 0) - printf (", batch \"%.*s\"", ep->batchlen, ep->batch); - puts ("\n"); - - switch (ep->bdtype) { - - case HYMOD_BDTYPE_IO: - case HYMOD_BDTYPE_CLP: - case HYMOD_BDTYPE_DSP: - printf (" Motorola %s CPU, speeds: %s/%s/%s", - cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd], - clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]); - - print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz); - - print_mem ("FLASH", ", ", ep->nflash, ep->flashsz); - - puts ("\n"); - - print_mem ("ZBT", " ", ep->nzbt, ep->zbtsz); - - if (ep->nxlx > 0) { - hymod_xlx_t *xp; - - if (ep->nxlx == 1) { - xp = &ep->xlx[0]; - printf (", Xilinx %s FPGA (%s/%s/%s)", - xlxtyp_vals[xp->type], - xlxspd_vals[xp->speed], - xlxtmp_vals[xp->temp], - xlxgrd_vals[xp->grade]); - } - else { - printf (", %d Xilinx FPGAs (", ep->nxlx); - for (i = 0; i < ep->nxlx; i++) { - xp = &ep->xlx[i]; - printf ("%s[%s/%s/%s]%s", - xlxtyp_vals[xp->type], - xlxspd_vals[xp->speed], - xlxtmp_vals[xp->temp], - xlxgrd_vals[xp->grade], - (i == ep->nxlx - 1) ? ")" : ", "); - } - } - } - else - puts(", NO FPGAs"); - - puts ("\n"); - - if (ep->hss.type > 0) - printf (" High Speed Serial: " - "%s, %d input%s, %d output%s\n", - hstype_vals[ep->hss.type], - ep->hss.nchin, - (ep->hss.nchin == 1 ? "" : "s"), - ep->hss.nchout, - (ep->hss.nchout == 1 ? "" : "s")); - break; - - case HYMOD_BDTYPE_INPUT: - case HYMOD_BDTYPE_ALTINPUT: - case HYMOD_BDTYPE_DISPLAY: - break; - - default: - /* crap! */ - printf (" UNKNOWN BOARD TYPE: %d\n", ep->bdtype); - break; - } -} - -int -hymod_eeprom_read (int which, hymod_eeprom_t *ep) -{ - char *label = which ? "mezzanine" : "main"; - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - char filename[50], prompt[50], *dir; - int serno, count = 0, rc; - - rc = eeprom_probe (dev_addr, 0); - - if (rc > 0) { - printf ("*** probe for eeprom failed with code %d\n", rc); - return (0); - } - - if (rc < 0) - return (rc); - - sprintf (prompt, "Enter %s board serial number: ", label); - - if ((dir = getenv ("bddb_cfgdir")) == NULL) - dir = def_bddb_cfgdir; - - for (;;) { - int rc; - - if (hymod_eeprom_load (which, ep)) - return (1); - - printf ("*** %s board EEPROM contents are %sinvalid\n", - label, count == 0 ? "" : "STILL "); - - puts ("*** will fetch from server (Ctrl-C to abort)\n"); - - serno = hymod_get_serno (prompt); - - if (serno < 0) { - if (serno == -1) - puts ("\n*** interrupted!"); - else - puts ("\n*** timeout!"); - puts (" - ignoring eeprom contents\n"); - return (0); - } - - sprintf (filename, "%s/%010d.cfg", dir, serno); - - printf ("*** fetching %s board EEPROM contents from server\n", - label); - - rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR); - - if (rc == 0) { - puts ("*** fetch failed - ignoring eeprom contents\n"); - return (0); - } - - count++; - } -} diff --git a/board/hymod/env.c b/board/hymod/env.c deleted file mode 100644 index 66c5115b21..0000000000 --- a/board/hymod/env.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* imports from fetch.c */ -extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); - -/* this is relative to the root of the server's tftp directory */ -static char *def_global_env_path = "/hymod/global_env"; - -static int -env_callback (uchar *name, uchar *value) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver; - int override = 1, append = 0, remove = 0, nnl, ovl, nvl; - - nn = (char *)name; - - if (*nn == '-') { - override = 0; - nn++; - } - - while (isblank(*nn)) - nn++; - - if ((nnl = strlen (nn)) == 0) { - printf ("Empty name in global env file\n"); - return (0); - } - - if ((c = nn[nnl - 1]) == '+' || c == '-') { - if (c == '+') - append = 1; - else - remove = 1; - nn[--nnl] = '\0'; - } - - while (nnl > 0 && isblank(nn[nnl - 1])) - nn[--nnl] = '\0'; - if (nnl == 0) { - printf ("Empty name in global env file\n"); - return (0); - } - - p = (char *)value; - q = nv; - - while (isblank(*p)) - p++; - - nvl = strlen (p); - while (nvl > 0 && isblank(p[nvl - 1])) - p[--nvl] = '\0'; - - while ((*q = *p++) != '\0') { - if (*q == '%') { - switch (*p++) { - - case '\0': /* whoops - back up */ - p--; - break; - - case '%': /* a single percent character */ - q++; - break; - - case 's': /* main board serial number as string */ - q += sprintf (q, "%010lu", - cp->main.eeprom.serno); - break; - - case 'S': /* main board serial number as number */ - q += sprintf (q, "%lu", cp->main.eeprom.serno); - break; - - default: /* ignore any others */ - break; - } - } - else - q++; - } - - if ((nvl = q - nv) == 0) { - setenv (nn, NULL); - return (1); - } - - if ((curver = getenv ("global_env_version")) == NULL) - curver = "unknown"; - - if ((newver = getenv ("new_genv_version")) == NULL || \ - strcmp (curver, newver) == 0) { - if (strcmp (nn, "version") == 0) - setenv ("new_genv_version", nv); - return (1); - } - - if ((p = getenv (nn)) != NULL) { - - strcpy (ov, p); - ovl = strlen (ov); - - if (append) { - - if (strstr (ov, nv) == NULL) { - - printf ("Appending '%s' to env var '%s'\n", - nv, nn); - - while (nvl >= 0) { - nv[ovl + 1 + nvl] = nv[nvl]; - nvl--; - } - - nv[ovl] = ' '; - - while (--ovl >= 0) - nv[ovl] = ov[ovl]; - - setenv (nn, nv); - } - - return (1); - } - - if (remove) { - - if (strstr (ov, nv) != NULL) { - - printf ("Removing '%s' from env var '%s'\n", - nv, nn); - - while ((p = strstr (ov, nv)) != NULL) { - q = p + nvl; - if (*q == ' ') - q++; - strcpy(p, q); - } - - setenv (nn, ov); - } - - return (1); - } - - if (!override || strcmp (ov, nv) == 0) - return (1); - - printf ("Re-setting env cmd '%s' from '%s' to '%s'\n", - nn, ov, nv); - } - else - printf ("Setting env cmd '%s' to '%s'\n", nn, nv); - - setenv (nn, nv); - return (1); -} - -void -hymod_check_env (void) -{ - char *p, *path, *curver, *newver; - int firsttime = 0, needsave = 0; - - if (getenv ("global_env_loaded") == NULL) { - puts ("*** global environment has never been loaded\n"); - puts ("*** fetching from server"); - firsttime = 1; - } - else if ((p = getenv ("always_check_env")) != NULL && - strcmp (p, "yes") == 0) - puts ("*** checking for updated global environment"); - else - return; - - puts (" (Control-C to Abort)\n"); - - if ((path = getenv ("global_env_path")) == NULL || *path == '\0') - path = def_global_env_path; - - if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) { - puts ("*** Fetch of global environment failed!\n"); - return; - } - - if ((newver = getenv ("new_genv_version")) == NULL) { - puts ("*** Version number not set - contents ignored!\n"); - return; - } - - if ((curver = getenv ("global_env_version")) == NULL || \ - strcmp (curver, newver) != 0) { - setenv ("global_env_version", newver); - needsave = 1; - } - else - printf ("*** Global environment up-to-date (ver %s)\n", curver); - - setenv ("new_genv_version", NULL); - - if (firsttime) { - setenv ("global_env_loaded", "yes"); - needsave = 1; - } - - if (needsave) - puts ("\n*** Remember to run the 'saveenv' " - "command to save the changes\n\n"); -} diff --git a/board/hymod/fetch.c b/board/hymod/fetch.c deleted file mode 100644 index da9373ffb0..0000000000 --- a/board/hymod/fetch.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* imports from input.c */ -extern int hymod_get_ethaddr (void); - -int -fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *)) -{ - char *ethaddr; - uchar *fp, *efp; - int rc, count = 0; - - while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') { - - printf ("*** Ethernet address is%s not set\n", - count == 0 ? "" : " STILL"); - - if ((rc = hymod_get_ethaddr ()) < 0) { - if (rc == -1) - puts ("\n*** interrupted!"); - else - puts ("\n*** timeout!"); - printf (" - fetch of '%s' aborted\n", fn); - return (0); - } - - count++; - } - - copy_filename (BootFile, fn, sizeof (BootFile)); - load_addr = addr; - NetBootFileXferSize = 0; - - if (NetLoop(TFTPGET) == 0) { - printf ("tftp transfer of file '%s' failed\n", fn); - return (0); - } - - if (NetBootFileXferSize == 0) { - printf ("can't determine size of file '%s'\n", fn); - return (0); - } - - fp = (uchar *)load_addr; - efp = fp + NetBootFileXferSize; - - do { - uchar *name, *value; - - if (*fp == '#' || *fp == '\n') { - /* skip this line */ - while (fp < efp && *fp++ != '\n') - ; - continue; - } - - name = fp; - - while (fp < efp && *fp != '=' && *fp != '\n') - fp++; - if (fp >= efp) - break; - if (*fp == '\n') { - fp++; - continue; - } - *fp++ = '\0'; - - value = fp; - - while (fp < efp && *fp != '\n') - fp++; - if (fp[-1] == '\r') - fp[-1] = '\0'; - *fp++ = '\0'; /* ok if we go off the end here */ - - if ((*cback)(name, value) == 0) - return (0); - - } while (fp < efp); - - return (1); -} diff --git a/board/hymod/flash.c b/board/hymod/flash.c deleted file mode 100644 index 02e519c695..0000000000 --- a/board/hymod/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 - */ - -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/*----------------------------------------------------------------------- - */ - -/* - * probe for flash bank at address "base" and store info about it - * in the flash_info entry "fip". Fatal error if nothing there. - */ -static void -bank_probe (flash_info_t *fip, volatile bank_addr_t base) -{ - volatile bank_addr_t addr; - bank_word_t word; - int i; - - /* reset the flash */ - *base = BANK_CMD_RST; - - /* put flash into read id mode */ - *base = BANK_CMD_RD_ID; - - /* check the manufacturer id - must be intel */ - word = *BANK_REG_MAN_CODE (base); - if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff)) - panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx", - (unsigned long)word, (unsigned long)base); - - /* check the device id */ - word = *BANK_REG_DEV_CODE (base); - switch (word) { - - case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5; - fip->sector_count = 32; - break; - - case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5; - fip->sector_count = 64; - break; - - case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A; - fip->sector_count = 32; - break; - - case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A; - fip->sector_count = 64; - break; - - case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A; - fip->sector_count = 128; - break; - - default: - panic ("\nbad device code (0x%08lx) at addr 0x%08lx", - (unsigned long)word, (unsigned long)base); - } - - if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT) - panic ("\ntoo many sectors (%d) in flash at address 0x%08lx", - fip->sector_count, (unsigned long)base); - - addr = base; - for (i = 0; i < fip->sector_count; i++) { - fip->start[i] = (unsigned long)addr; - fip->protect[i] = 0; - addr = BANK_ADDR_NEXT_BLK (addr); - } - - fip->size = (bank_size_t)addr - (bank_size_t)base; - - /* reset the flash */ - *base = BANK_CMD_RST; -} - -static void -bank_reset (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - -#ifdef FLASH_DEBUG - printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr); -#endif - - *addr = BANK_CMD_RST; -} - -static void -bank_erase_init (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - int flag; - -#ifdef FLASH_DEBUG - printf ("erasing sector %d, addr = 0x%08lx\n", - sect, (unsigned long)addr); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts (); - -#ifdef FLASH_DEBUG - printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr); -#endif - *addr = BANK_CMD_ERASE1; - *addr = BANK_CMD_ERASE2; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); -} - -static int -bank_erase_poll (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - bank_word_t stat = *addr; - -#ifdef FLASH_DEBUG - printf ("checking status at addr 0x%08lx [0x%08lx]\n", - (unsigned long)addr, (unsigned long)stat); -#endif - - if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) { - if ((stat & BANK_STAT_ERR) != 0) { - printf ("failed on sector %d [0x%08lx] at " - "address 0x%08lx\n", sect, - (unsigned long)stat, (unsigned long)addr); - *addr = BANK_CMD_CLR_STAT; - return (-1); - } - else - return (1); - } - else - return (0); -} - -static int -bank_write_word (volatile bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf ("flash program failed [0x%08lx] at address 0x%08lx\n", - (unsigned long)stat, (unsigned long)addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - int i; - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J5: printf ("28F320J5 (32 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F640J5: printf ("28F640J5 (64 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F320J3A: printf ("28F320J3A (32 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F128J3A: printf ("28F320J3A (128 Mbit, 2 x 16bit)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -/*----------------------------------------------------------------------- - */ - -int -flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - int rcode = 0; - -#ifdef FLASH_DEBUG - printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info (info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sector%s will not be erased\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init (info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer (start); - - do { - now = get_timer (start); - - if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - rcode = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll (info, sect); - - if (sectdone < 0) { - haderr = 1; - rcode = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset (info, sect); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Program failed - */ -static int -write_word (flash_info_t *info, ulong dest, ulong data) -{ - /* Check if Flash is (sufficiently) erased */ - if ((*(ulong *)dest & data) != data) - return (2); - - return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Program failed - */ - -int -write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/hymod/flash.h b/board/hymod/flash.h deleted file mode 100644 index 6ea282341f..0000000000 --- a/board/hymod/flash.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen, CSIRO-MIT, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* Commands */ -#define ISF_CMD_RST 0xFF /* reset flash */ -#define ISF_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define ISF_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define ISF_CMD_RD_STAT 0x70 /* read the status register */ -#define ISF_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define ISF_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define ISF_CMD_PROG 0x40 /* program word command */ -#define ISF_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define ISF_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define ISF_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define ISF_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define ISF_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define ISF_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define ISF_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define ISF_STAT_DPS 0x02 /* Device Protect Status */ -#define ISF_STAT_VPPS 0x08 /* VPP Status */ -#define ISF_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define ISF_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define ISF_STAT_ESS 0x40 /* Erase Suspend Status */ -#define ISF_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define ISF_STAT_ERR (ISF_STAT_VPPS | ISF_STAT_DPS | \ - ISF_STAT_ECLBS | ISF_STAT_PSLBS) - -/* register addresses, valid only following an ISF_CMD_RD_ID command */ -#define ISF_REG_MAN_CODE 0x00 /* manufacturer code */ -#define ISF_REG_DEV_CODE 0x01 /* device code */ -#define ISF_REG_BLK_LCK 0x02 /* block lock configuration */ -#define ISF_REG_MST_LCK 0x03 /* master lock configuration */ - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * this code requires that the flash on any Hymod board appear as a bank - * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase - * sectors (or blocks), running in x16 bit mode and connected side-by-side - * to make a 32-bit wide bus. - */ - -typedef unsigned long bank_word_t; -typedef bank_word_t bank_blk_t[64 * 1024]; - -#define BANK_FILL_WORD(b) (((bank_word_t)(b) << 16) | (bank_word_t)(b)) - -#ifdef EXAMPLE - -/* theoretically the following examples should also work */ - -/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */ -typedef unsigned char bank_word_t; -typedef bank_word_t bank_blk_t[128 * 1024]; -#define BANK_FILL_WORD(b) ((bank_word_t)(b)) - -/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */ -typedef unsigned long long bank_word_t; -typedef bank_word_t bank_blk_t[32 * 1024]; -#define BANK_FILL_WORD(b) ( \ - ((bank_word_t)(b) << 48) \ - ((bank_word_t)(b) << 32) \ - ((bank_word_t)(b) << 16) \ - ((bank_word_t)(b) << 0) \ - ) - -#endif /* EXAMPLE */ - -/* the sizes of these two types should probably be the same */ -typedef bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(sizeof (bank_word_t) - 1))) -#define BANK_SIZE_WORD_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_word_t) - 1) \ - & ~(sizeof (bank_word_t) - 1)) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(sizeof (bank_blk_t) - 1))) -#define BANK_SIZE_BLK_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \ - & ~(sizeof (bank_blk_t) - 1)) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) ((bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o))) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - sizeof (bank_word_t)) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - sizeof (bank_blk_t)) - -/* get bank address of register r given a bank base address a and block num b */ -#define BANK_ADDR_REG(a, b, r) BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \ - (bank_size_t)(b) * sizeof (bank_blk_t)), \ - (bank_size_t)(r) * sizeof (bank_word_t)) - -/* make a bank word value for each StrataFlash value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(ISF_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(ISF_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(ISF_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(ISF_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(ISF_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(ISF_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(ISF_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(ISF_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(ISF_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(ISF_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(ISF_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(ISF_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(ISF_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(ISF_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(ISF_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(ISF_STAT_ERR) - -/* make a bank register address for each StrataFlash register address */ - -#define BANK_REG_MAN_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE) -#define BANK_REG_DEV_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE) -#define BANK_REG_BLK_LCK(a, b) BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK) -#define BANK_REG_MST_LCK(a) BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK) diff --git a/board/hymod/global_env b/board/hymod/global_env deleted file mode 100644 index ac12fd7f18..0000000000 --- a/board/hymod/global_env +++ /dev/null @@ -1,145 +0,0 @@ -# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE - -# (C) Copyright 2001 -# Murray Jensen, CSIRO-MIT, -# -# SPDX-License-Identifier: GPL-2.0+ - -# -# global_env -# -# file used by Hymod boards to initialise the u-boot non-volatile -# environment when u-boot is first run (it determines this by the -# absence of the environment variable "global_env_loaded") -# -# format of this file is: -# -# 1. blank lines and lines beginning with '#' are ignored -# 2. all other lines must have the form = -# 3. if a percent appears anywhere, it is replaced like so: -# -# %s serial number of the main board (10 digit zero filled) -# %S serial number of the main board (plain number) -# %% a percentage character -# ... otherwise the %x is discarded -# -# if first character in is a dash ('-'), then an existing env var -# will not be overwritten (the dash is removed). i.e. it is only set if -# it does not exist -# -# if last character in is a plus ('+'), then will be appended -# to any existing env var (the plus is ignored). Duplicates of are -# removed. -# -# similarly, if the last character in is a minus ('-'), then any -# occurences of in the current value of will removed (the -# minus is ignored). -# -# leading and trailing whitespace is removed in both and -# (after processing any initial or final plus/minus in ). -# - -# MISCELLANEOUS PARAMETERS - -# version must always come first -version=4 - -# set the ip address based on the main board serial number -ipaddr=192.168.1.%S -serverip=192.168.1.254 - -# stop auto execute after tftp (not a very good name really) -autostart=no - -# setting this to "yes" forces the global_env file to be loaded and processed -# if the current version is different to the version in the file -always_check_env=no - -# BOOTING COMMANDS AND PARAMETERS - -# command to run when "auto-booting" -bootcmd=bootm 40080000 - -# how long the "countdown" to automatically running "bootcmd" is -bootdelay=2 - -# how long before it "times out" console input and attempts to run "bootcmd" -bootretry=5 - -# arguments passed to the boot program (i.e. linux kernel) via register 6 -# the linux kernel (v2.4) uses the following registers: -# r3 - address of board information structure -# r4 - address of initial ramdisk image (0 means no initrd) -# r5 - size of initial ramdisk image -# r6 - address of command line string --bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro - -# these four are for hymod linux integrated into our Sun network -bootargs+=serialno=%S -bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4 -bootargs+=nfsclient -bootargs+=automount - -# start a web server by default -bootargs+=webserver - -# give negotiation time to finish -bootargs+=netsleep=5 - -# then our ciscos don't pass packets for 25-30 secs after that, so -# pinging the server until it responds prevents network connections -# from failing... -bootargs+=netping - -# these are old bootargs - we don't need them anymore -bootargs-=preload=unix,i2c-cpm,i2c-dev -bootargs-=ramdisk_size=32768 -bootargs-=ramdisk_size=24576 - -# FLASH MANIPULATION COMMANDS - -# -# 16M flash, 64 x 256K sectors, mapped at address 0x40000000 -# -# Sector(s) Address Size Description -# -# 0 - 0 0x40000000 256K boot code -# 1 - 1 0x40040000 256K non volatile environment -# 2 - 4 0x40080000 768K linux kernel image -# 5 - 7 0x40140000 768K alternate linux kernel image -# 8 - 47 0x40200000 10M linux initial ramdisk image -# 48 - 63 0x40c00000 4M ramdisk image for applications -# - -fetchboot=tftp 100000 /hymod/u-boot.bin -eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0 -copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0 -cmpboot=cmp.b 100000 40000000 40000 -newboot=run fetchboot eraseboot copyboot cmpboot - -fetchlinux=tftp 100000 /hymod/linux.bin -eraselinux=erase 1:2-4 -copylinux=cp.b 100000 40080000 ${filesize} -cmplinux=cmp.b 100000 40080000 ${filesize} -newlinux=run fetchlinux eraselinux copylinux cmplinux - -fetchaltlinux=tftp 100000 /hymod/altlinux.bin -erasealtlinux=erase 1:5-7 -copyaltlinux=cp.b 100000 40140000 ${filesize} -cmpaltlinux=cmp.b 100000 40140000 ${filesize} -newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux - -fetchroot=tftp 100000 /hymod/root.bin -eraseroot=erase 1:8-47 -copyroot=cp.b 100000 40200000 ${filesize} -cmproot=cmp.b 100000 40200000 ${filesize} -newroot=run fetchroot eraseroot copyroot cmproot - -fetchard=tftp 100000 /hymod/apprd.bin -eraseard=erase 1:48-63 -copyard=cp.b 100000 40c00000 ${filesize} -cmpard=cmp.b 100000 40c00000 ${filesize} -newapprd=run fetchard eraseard copyard cmpard - -# pass above map to linux mtd driver -bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod) diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c deleted file mode 100644 index 5fec914f5a..0000000000 --- a/board/hymod/hymod.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* imports from eeprom.c */ -extern int hymod_eeprom_read (int, hymod_eeprom_t *); -extern void hymod_eeprom_print (hymod_eeprom_t *); - -/* imports from env.c */ -extern void hymod_check_env (void); - -/* ------------------------------------------------------------------------- */ - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */ - { 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */ - { 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */ - { 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */ - { 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */ - { 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */ - { 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */ - { 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */ - { 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */ - { 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */ - { 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */ - { 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */ - { 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */ - { 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */ - { 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */ - { 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */ - { 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */ - { 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */ - { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */ - { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */ - { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */ - { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */ - }, - - /* Port B configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */ - { 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */ - { 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */ - { 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */ - { 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */ - { 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */ - { 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */ - { 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */ - { 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */ - { 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */ - { 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */ - { 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */ - { 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */ - { 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */ - { 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */ - }, - - /* Port C configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */ - { 0, 0, 0, 0, 0, 0 }, /* PC30: ? */ - { 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */ - { 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */ - { 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */ - { 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */ - { 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */ - { 0, 0, 0, 0, 0, 0 }, /* PC24: ? */ - { 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */ - { 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */ - { 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */ - { 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */ - { 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */ - { 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */ - { 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */ - { 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */ - { 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */ - { 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */ - { 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */ - { 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */ - { 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */ - { 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */ - { 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */ - { 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */ - { 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */ - { 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */ - { 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */ - }, - - /* Port D configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */ - { 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */ - { 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */ - { 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */ - { 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */ - { 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */ - { 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */ - { 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */ - { 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */ - { 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */ - { 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */ - { 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */ - { 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */ - { 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */ - { 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */ - { 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */ - { 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */ - { 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */ - { 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */ - { 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */ - { 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */ - { 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */ - { 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */ - { 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */ - { 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */ - { 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */ - { 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */ - { 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */ - { 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * AMI FS6377 Clock Generator configuration table - * - * the "fs6377_regs[]" table entries correspond to FS6377 registers - * 0 - 15 (total of 16 bytes). - * - * the data is written to the FS6377 via the i2c bus using address in - * "fs6377_addr" (address is 7 bits - R/W bit not included). - * - * The fs6377 has four clock outputs: A, B, C and D. - * - * Outputs C and D can each provide two different clock outputs C1/D1 or - * C2/D2 depending on the state of the SEL_CD input which is connected to - * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0) - * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2. - * - * PA11 defaults to output low (or 0) in the i/o port config table above. - * - * Output A provides a 100MHz for the High Speed Serial chips. Output B - * provides a 3.6864MHz clock for more accurate asynchronous serial bit - * rates. Output C is routed to the mezzanine connector but is currently - * unused - both C1 and C2 are set to 16MHz. Output D is used by both the - * alt-input and display mezzanine boards for their video chips. The - * alt-input board requires a clock of 24.576MHz and this is available on - * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this - * is available on D2 (PA11=SEL_CD=1). - * - * So the default is a clock suitable for the alt-input board. PA11 is toggled - * later in misc_init_r(), if a display board is detected. - */ - -uchar fs6377_addr = 0x5c; - -uchar fs6377_regs[16] = { - 12, 75, 64, 25, 144, 128, 25, 192, - 0, 16, 135, 192, 224, 64, 64, 192 -}; - -/* ------------------------------------------------------------------------- */ - -/* - * special board initialisation, after clocks and timebase have been - * set up but before environment and serial are initialised. - * - * added so that very early initialisations can be done using the i2c - * driver (which requires the clocks, to calculate the dividers, and - * the timebase, for udelay()) - */ - -int -board_postclk_init (void) -{ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* - * Initialise the FS6377 clock chip - * - * the secondary address is the register number from where to - * start the write - I want to write all the registers - * - * don't bother checking return status - we have no console yet - * to print it on, nor any RAM to store it in - it will be obvious - * if this doesn't work - */ - (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs, - sizeof (fs6377_regs)); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: Hardwired to HYMOD - */ - -int -checkboard (void) -{ - puts ("Board: HYMOD\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * miscellaneous (early - while running in flash) initialisations. - */ - -#define _NOT_USED_ 0xFFFFFFFF - -uint upmb_table[] = { - /* Read Single Beat (RSS) - offset 0x00 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Read Burst (RBS) - offset 0x08 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Single Beat (WSS) - offset 0x18 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Burst (WSS) - offset 0x20 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Refresh Timer (PTS) - offset 0x30 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Exception Condition (EXS) - offset 0x3c */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -uint upmc_table[] = { - /* Read Single Beat (RSS) - offset 0x00 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Read Burst (RBS) - offset 0x08 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Single Beat (WSS) - offset 0x18 */ - 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000, - 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Burst (WSS) - offset 0x20 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Refresh Timer (PTS) - offset 0x30 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Exception Condition (EXS) - offset 0x3c */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -int -misc_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - printf ("UPMs: "); - - upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]); - memctl->memc_mbmr = CONFIG_SYS_MBMR; - - upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]); - memctl->memc_mcmr = CONFIG_SYS_MCMR; - - printf ("configured\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t -initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); - ulong psdmr = CONFIG_SYS_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - return (CONFIG_SYS_SDRAM_SIZE << 20); -} - -/* ------------------------------------------------------------------------- */ -/* miscellaneous initialisations after relocation into ram (misc_init_r) */ -/* */ -/* loads the data in the main board and mezzanine board eeproms into */ -/* the hymod configuration struct stored in the board information area. */ -/* */ -/* if the contents of either eeprom is invalid, prompts for a serial */ -/* number (and an ethernet address if required) then fetches a file */ -/* containing information to be stored in the eeprom from the tftp server */ -/* (the file name is based on the serial number and a built-in path) */ - -int -last_stage_init (void) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - int rc; - -#ifdef CONFIG_BOOT_RETRY_TIME - /* - * we use the readline () function, but we also want - * command timeout enabled - */ - init_cmd_timeout (); -#endif - - memset ((void *) cp, 0, sizeof (*cp)); - - /* set up main board config info */ - - rc = hymod_eeprom_read (0, &cp->main.eeprom); - - puts ("EEPROM:main..."); - if (rc < 0) - puts ("NOT PRESENT\n"); - else if (rc == 0) - puts ("INVALID\n"); - else { - cp->main.eeprom.valid = 1; - - printf ("OK (ver %u)\n", cp->main.eeprom.ver); - hymod_eeprom_print (&cp->main.eeprom); - - /* - * hard-wired assumption here: all hymod main boards will have - * one xilinx fpga, with the interrupt line connected to IRQ2 - * - * One day, this might be based on the board type - */ - - cp->main.xlx[0].mmap.prog.exists = 1; - cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE; - cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE; - - cp->main.xlx[0].mmap.reg.exists = 1; - cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE; - cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE; - - cp->main.xlx[0].mmap.port.exists = 1; - cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE; - cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE; - - cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT; - cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN; - cp->main.xlx[0].iopins.prog_pin.flag = 1; - cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT; - cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN; - cp->main.xlx[0].iopins.init_pin.flag = 1; - cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT; - cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN; - cp->main.xlx[0].iopins.done_pin.flag = 1; -#ifdef FPGA_MAIN_ENABLE_PORT - cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT; - cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN; - cp->main.xlx[0].iopins.enable_pin.flag = 1; -#endif - - cp->main.xlx[0].irq = FPGA_MAIN_IRQ; - } - - /* set up mezzanine board config info */ - - rc = hymod_eeprom_read (1, &cp->mezz.eeprom); - - puts ("EEPROM:mezz..."); - if (rc < 0) - puts ("NOT PRESENT\n"); - else if (rc == 0) - puts ("INVALID\n"); - else { - cp->main.eeprom.valid = 1; - - printf ("OK (ver %u)\n", cp->mezz.eeprom.ver); - hymod_eeprom_print (&cp->mezz.eeprom); - } - - cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc)); - - hymod_check_env (); - - return (0); -} - -#ifdef CONFIG_SHOW_ACTIVITY -void board_show_activity (ulong timebase) -{ -#ifdef CONFIG_SYS_HYMOD_DBLEDS - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8260_t *iop = &immr->im_ioport; - static int shift = 0; - - if ((timestamp % CONFIG_SYS_HZ) == 0) { - if (++shift > 3) - shift = 0; - iop->iop_pdatd = - (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift)); - } -#endif /* CONFIG_SYS_HYMOD_DBLEDS */ -} - -void show_activity(int arg) -{ -} -#endif /* CONFIG_SHOW_ACTIVITY */ diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h deleted file mode 100644 index 2c58bfb6e0..0000000000 --- a/board/hymod/hymod.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _HYMOD_H_ -#define _HYMOD_H_ - -#include -#ifdef CONFIG_8260 -#include -#endif - -/* - * hymod configuration data - passed by boot code via the board information - * structure (only U-Boot has support for this at the moment) - * - * there are three types of data passed up from the boot monitor. the first - * (type hymod_eeprom_t) is the eeprom data that was read off both the main - * (or mother) board and the mezzanine board (if any). this data defines how - * many Xilinx fpgas are on each board, and their types (among other things). - * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where - * in the physical address space the various Xilinx fpga access regions have - * been mapped by the boot rom. the third type of data (type xlx_iopins_t, - * one per Xilinx fpga) defines which io port pins are connected to the various - * signals required to program a Xilinx fpga. - * - * A ram/flash "bank" refers to memory controlled by the same chip select. - * - * the eeprom contents are defined as in technical note #2 - basically, - * a header, zero or more records in no particular order, and a 32 bit crc - * a record is 1 or more type bytes, a length byte and "length" bytes. - */ - -#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */ -#define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */ -#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */ - -/* eeprom header */ -typedef - struct { - unsigned char id; /* eeprom id byte */ - unsigned char :1; - unsigned char ver:7; /* eeprom contents version number */ - unsigned long len; /* total # of bytes btw hdr and crc */ - } -hymod_eehdr_t; - -/* maximum number of bytes available for eeprom data records */ -#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \ - - sizeof (hymod_eehdr_t) \ - - sizeof (unsigned long)) - -/* eeprom data record */ -typedef - union { - struct { - unsigned char topbit:1; - unsigned char type:7; - unsigned char len; - unsigned char data[1]; /* variable length */ - } small; - struct { - unsigned short topbit:1; - unsigned short nxtbit:1; - unsigned short type:14; - unsigned short len; - unsigned char data[1]; /* variable length */ - } medium; - struct { - unsigned long topbit:1; - unsigned long nxtbit:1; - unsigned long type:30; - unsigned long len; - unsigned char data[1]; /* variable length */ - } large; - } -hymod_eerec_t; - -#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */ -#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */ - -/* eeprom record types */ -#define HYMOD_EEREC_SERNO 1 /* serial number */ -#define HYMOD_EEREC_DATE 2 /* date */ -#define HYMOD_EEREC_BATCH 3 /* batch id */ -#define HYMOD_EEREC_TYPE 4 /* board type */ -#define HYMOD_EEREC_REV 5 /* revision number */ -#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */ -#define HYMOD_EEREC_FLASH 7 /* flash sizes */ -#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */ -#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */ -#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */ -#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */ -#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */ -#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */ -#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */ -#define HYMOD_EEREC_BUSSPD 15 /* bus speed */ -#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */ -#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */ -#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */ -#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */ - -/* some dimensions */ -#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */ -#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */ -#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */ -#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */ -#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */ - -#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */ - -/* board types */ -#define HYMOD_BDTYPE_NONE 0 /* information not present */ -#define HYMOD_BDTYPE_IO 1 /* I/O main board */ -#define HYMOD_BDTYPE_CLP 2 /* CLP main board */ -#define HYMOD_BDTYPE_DSP 3 /* DSP main board */ -#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */ -#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */ -#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */ -#define HYMOD_BDTYPE_MAX 7 /* first invalid value */ - -/* Xilinx fpga types */ -#define HYMOD_XTYP_NONE 0 /* information not present */ -#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */ -#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */ -#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */ -#define HYMOD_XTYP_MAX 4 /* first invalid value */ - -/* Xilinx fpga speeds */ -#define HYMOD_XSPD_NONE 0 /* information not present */ -#define HYMOD_XSPD_SIX 1 -#define HYMOD_XSPD_SEVEN 2 -#define HYMOD_XSPD_EIGHT 3 -#define HYMOD_XSPD_MAX 4 /* first invalid value */ - -/* Xilinx fpga temperatures */ -#define HYMOD_XTMP_NONE 0 /* information not present */ -#define HYMOD_XTMP_COM 1 -#define HYMOD_XTMP_IND 2 -#define HYMOD_XTMP_MAX 3 /* first invalid value */ - -/* Xilinx fpga grades */ -#define HYMOD_XTMP_NONE 0 /* information not present */ -#define HYMOD_XTMP_NORMAL 1 -#define HYMOD_XTMP_ENGSAMP 2 -#define HYMOD_XTMP_MAX 3 /* first invalid value */ - -/* CPU types */ -#define HYMOD_CPUTYPE_NONE 0 /* information not present */ -#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */ -#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */ - -/* CPU/BUS/CPM clock speeds */ -#define HYMOD_CLKSPD_NONE 0 /* information not present */ -#define HYMOD_CLKSPD_33MHZ 1 -#define HYMOD_CLKSPD_66MHZ 2 -#define HYMOD_CLKSPD_100MHZ 3 -#define HYMOD_CLKSPD_133MHZ 4 -#define HYMOD_CLKSPD_166MHZ 5 -#define HYMOD_CLKSPD_200MHZ 6 -#define HYMOD_CLKSPD_MAX 7 /* first invalid value */ - -/* high speed serial chip types */ -#define HYMOD_HSSTYPE_NONE 0 /* information not present */ -#define HYMOD_HSSTYPE_AMCC52064 1 -#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */ - -/* a date (yyyy-mm-dd) */ -typedef - struct { - unsigned short year; - unsigned char month; - unsigned char day; - } -hymod_date_t; - -/* describes a Xilinx fpga */ -typedef - struct { - unsigned char type; /* chip type */ - unsigned char speed; /* chip speed rating */ - unsigned char temp; /* chip temperature rating */ - unsigned char grade; /* chip grade */ - } -hymod_xlx_t; - -/* describes a Motorola embedded processor */ -typedef - struct { - unsigned char type; /* CPU type */ - unsigned char cpuspd; /* speed of the PowerPC core */ - unsigned char busspd; /* speed of the system and 60x bus */ - unsigned char cpmspd; /* speed of the CPM co-processor */ - } -hymod_mpc_t; - -/* info about high-speed (1Gbit) serial interface */ -typedef - struct { - unsigned char type; /* high-speed serial chip type */ - unsigned char nchin; /* number of input channels mounted */ - unsigned char nchout; /* number of output channels mounted */ - } -hymod_hss_t; - -/* - * this defines the contents of the serial eeprom that exists on every - * hymod board, including mezzanine boards (the serial eeprom will be - * faked for early development boards that don't have one) - */ - -typedef - struct { - unsigned char valid:1; /* contents of this struct is valid */ - unsigned char ver:7; /* eeprom contents version */ - unsigned char bdtype; /* board type */ - unsigned char bdrev; /* board revision */ - unsigned char batchlen; /* length of batch string below */ - unsigned long serno; /* serial number */ - hymod_date_t date; /* manufacture date */ - unsigned char batch[32]; /* manufacturer specific batch id */ - unsigned char nsdram; /* # of ram "banks" */ - unsigned char nflash; /* # of flash "banks" */ - unsigned char nzbt; /* # of ZBT rams */ - unsigned char nxlx; /* # of Xilinx fpgas */ - unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */ - unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */ - unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */ - hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */ - hymod_mpc_t mpc; /* Motorola MPC CPU info */ - hymod_hss_t hss; /* high-speed serial info */ - } -hymod_eeprom_t; - -/* - * this defines a region in the processor's physical address space - */ -typedef - struct { - unsigned long exists:1; /* 1 if the region exists, 0 if not */ - unsigned long size:31; /* size in bytes */ - unsigned long base; /* base address */ - } -xlx_prgn_t; - -/* - * this defines where the various Xilinx fpga access regions are mapped - * into the physical address space of the processor - */ -typedef - struct { - xlx_prgn_t prog; /* program access region */ - xlx_prgn_t reg; /* register access region */ - xlx_prgn_t port; /* port access region */ - } -xlx_mmap_t; - -/* - * this defines which 8260 i/o port pins are connected to the various - * signals required for programming a Xilinx fpga - */ -typedef - struct { - iopin_t prog_pin; /* assert for >= 300ns to program */ - iopin_t init_pin; /* goes high when fpga is cleared */ - iopin_t done_pin; /* goes high when program is done */ - iopin_t enable_pin; /* some fpgas need enabling */ - } -xlx_iopins_t; - -/* all info about one Xilinx chip */ -typedef - struct { - xlx_mmap_t mmap; - xlx_iopins_t iopins; - unsigned long irq:8; /* h/w intr req number for this fpga */ - } -xlx_info_t; - -/* all info about one hymod board */ -typedef - struct { - hymod_eeprom_t eeprom; - xlx_info_t xlx[HYMOD_MAX_XLX]; - } -hymod_board_t; - -/* - * this defines the configuration information of a hymod board-set - * (main board + possible mezzanine board). In future, there may be - * more than one mezzanine board (stackable?) - if so, add a "mezz2" - * field, and so on... or make mezz an array? - */ -typedef - struct { - unsigned long ver:8; /* version control */ - hymod_board_t main; /* main board info */ - hymod_board_t mezz; /* mezzanine board info */ - unsigned long crc; /* ensures kernel and boot prom agree */ - } -hymod_conf_t; - -#endif /* _HYMOD_H_ */ diff --git a/board/hymod/input.c b/board/hymod/input.c deleted file mode 100644 index 184902cde5..0000000000 --- a/board/hymod/input.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -int -hymod_get_serno (const char *prompt) -{ - for (;;) { - int n, serno; - char *p; - -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout (); -#endif - - n = readline (prompt); - - if (n < 0) - return (n); - - if (n == 0) - continue; - - serno = (int) simple_strtol (console_buffer, &p, 10); - - if (p > console_buffer && *p == '\0' && serno > 0) - return (serno); - - printf ("Invalid number (%s) - please re-enter\n", - console_buffer); - } -} - -int -hymod_get_ethaddr (void) -{ - for (;;) { - int n; - -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout (); -#endif - - n = readline ("Enter board ethernet address: "); - - if (n < 0) - return (n); - - if (n == 0) - continue; - - if (n == 17) { - int i; - char *p, *q; - - /* see if it looks like an ethernet address */ - - p = console_buffer; - - for (i = 0; i < 6; i++) { - char term = (i == 5 ? '\0' : ':'); - - (void)simple_strtol (p, &q, 16); - - if ((q - p) != 2 || *q++ != term) - break; - - p = q; - } - - if (i == 6) { - /* it looks ok - set it */ - printf ("Setting ethernet addr to %s\n", - console_buffer); - - setenv ("ethaddr", console_buffer); - - puts ("Remember to do a 'saveenv' to " - "make it permanent\n"); - - return (0); - } - } - - printf ("Invalid ethernet addr (%s) - please re-enter\n", - console_buffer); - } -} diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds deleted file mode 100644 index 1dfd2b20f7..0000000000 --- a/board/hymod/u-boot.lds +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8260/start.o (.text) -/* - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; -*/ - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug deleted file mode 100644 index b9c84c77d6..0000000000 --- a/board/hymod/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ibf-dsp561/Kconfig b/board/ibf-dsp561/Kconfig new file mode 100644 index 0000000000..acf5d7c6f9 --- /dev/null +++ b/board/ibf-dsp561/Kconfig @@ -0,0 +1,9 @@ +if TARGET_IBF_DSP561 + +config SYS_BOARD + default "ibf-dsp561" + +config SYS_CONFIG_NAME + default "ibf-dsp561" + +endif diff --git a/board/ibf-dsp561/MAINTAINERS b/board/ibf-dsp561/MAINTAINERS new file mode 100644 index 0000000000..dfd0f9095f --- /dev/null +++ b/board/ibf-dsp561/MAINTAINERS @@ -0,0 +1,6 @@ +IBF-DSP561 BOARD +M: I-SYST Micromodule +S: Maintained +F: board/ibf-dsp561/ +F: include/configs/ibf-dsp561.h +F: configs/ibf-dsp561_defconfig diff --git a/board/ibf-dsp561/Makefile b/board/ibf-dsp561/Makefile index 099bcaf999..5b05ba8003 100644 --- a/board/ibf-dsp561/Makefile +++ b/board/ibf-dsp561/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ibf-dsp561.o diff --git a/board/icecube/Makefile b/board/icecube/Makefile deleted file mode 100644 index 4ff6b2d995..0000000000 --- a/board/icecube/Makefile +++ /dev/null @@ -1,29 +0,0 @@ - -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/icecube/README b/board/icecube/README deleted file mode 100644 index 5252bc9767..0000000000 --- a/board/icecube/README +++ /dev/null @@ -1,13 +0,0 @@ ---------------------------------------------------------------------------- -Build target Flash address | BDI "go" command | Reset Vector ---------------------------------------------------------------------------- -Lite5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100 -Lite5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100 -Lite5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 -icecube_5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100 -icecube_5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100 -icecube_5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 -icecube_5200_DDR 0xFFF00000 | 0xFFF00100 | 0xFFF00100 -icecube_5200_DDR_LOWBOOT 0xFF800000 | 0xFF800100 | 0x00000100 -icecube_5200_DDR_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 ---------------------------------------------------------------------------- diff --git a/board/icecube/README.Lite5200B_low_power b/board/icecube/README.Lite5200B_low_power deleted file mode 100644 index 5b04fbba72..0000000000 --- a/board/icecube/README.Lite5200B_low_power +++ /dev/null @@ -1,22 +0,0 @@ -Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM) ----------------------------------------------------------- - -Low-power mode as described in Lite5200B User's Manual, means that -with support of MC68HLC908QT1 microcontroller (refered to as QT), -everything but the SDRAM can be powered down. This brings -maximum power saving, while one can still restore previous state -quickly. - -Quick overview where U-Boot comes into the picture: -- OS saves device states -- OS saves wakeup handler address to physical 0x0, puts SDRAM into - self-refresh and signals to QT, it should power down the board -- / board is sleeping here / -- someone presses SW4 (connected to QT) -- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up, - so get SDRAM out of self-refresh and transfer control to OS - wakeup handler -- OS restores device states - -This was tested on Linux with USB and Ethernet in use. Adding -support for other devices is an OS issue. diff --git a/board/icecube/flash.c b/board/icecube/flash.c deleted file mode 100644 index a044e8f24a..0000000000 --- a/board/icecube/flash.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#ifndef CONFIG_FLASH_CFI_DRIVER -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - extern void flash_preinit(void); - extern void flash_afterinit(ulong); - ulong flashbase = CONFIG_SYS_FLASH_BASE; - - flash_preinit(); - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - memset(&flash_info[i], 0, sizeof(flash_info_t)); - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - size += flash_info[i].size; - flashbase += 0x800000; - } -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - - flash_afterinit(size); - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && - info->start[0] <= base && base <= info->start[0] + info->size - 1) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDLV065D: - fmt = "29LV065 (64 Mbit, uniform sectors)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - FPWV* addr2; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { - - case (FPW)AMD_ID_LV065D: - info->flash_id += FLASH_AMDLV065D; - info->sector_count = 128; - info->size = 0x00800000; - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = (ulong)addr + (i * 0x10000); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - /* test for real flash at bank 1 */ - addr2 = (FPW *)((ulong)addr | 0x800000); - if (addr2 != addr && - ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) { - /* Seems 2 banks are the same space (8Mb chip is installed, - * J24 in default position (CS0)). Disable this (first) bank. - */ - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDLV065D: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} -#endif /*CONFIG_FLASH_CFI_DRIVER*/ diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c deleted file mode 100644 index a99416b3aa..0000000000 --- a/board/icecube/icecube.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_LITE5200B) -#include "mt46v32m16.h" -#else -# if defined(CONFIG_MPC5200_DDR) -# include "mt46v16m16-75.h" -# else -#include "mt48lc16m16a2-75.h" -# endif -#endif - -#ifdef CONFIG_LITE5200B_PM -/* u-boot part of low-power mode implementation */ -#define SAVED_ADDR (*(void **)0x00000000) -#define PSC2_4 0x02 - -void lite5200b_wakeup(void) -{ - unsigned char wakeup_pin; - void (*linux_wakeup)(void); - - /* check PSC2_4, if it's down "QT" is signaling we have a wakeup - * from low power mode */ - *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4; - __asm__ volatile ("sync"); - - wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I; - if (wakeup_pin & PSC2_4) - return; - - /* acknowledge to "QT" - * by holding pin at 1 for 10 uS */ - *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4; - __asm__ volatile ("sync"); - *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4; - __asm__ volatile ("sync"); - udelay(10); - - /* put ram out of self-refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */ - __asm__ volatile ("sync"); - *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */ - __asm__ volatile ("sync"); - *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */ - __asm__ volatile ("sync"); - udelay(10); /* wait a bit */ - - /* jump back to linux kernel code */ - linux_wakeup = SAVED_ADDR; - printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n", - (unsigned long)linux_wakeup); - linux_wakeup(); -} -#else -#define lite5200b_wakeup() -#endif - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - lite5200b_wakeup(); - - return dramsize + dramsize2; -} - -int checkboard (void) -{ -#if defined (CONFIG_LITE5200B) - puts ("Board: Freescale Lite5200B\n"); -#else - puts ("Board: Motorola MPC5200 (IceCube)\n"); -#endif - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == 0x800000) { /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CONFIG_SYS_BOOTCS_START | size); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -} -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h deleted file mode 100644 index 919876fd63..0000000000 --- a/board/icecube/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x705f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h deleted file mode 100644 index a200bc78e8..0000000000 --- a/board/icecube/mt46v32m16.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/icecube/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/icpdas/lp8x4x/Kconfig b/board/icpdas/lp8x4x/Kconfig new file mode 100644 index 0000000000..3e87c4016b --- /dev/null +++ b/board/icpdas/lp8x4x/Kconfig @@ -0,0 +1,12 @@ +if TARGET_LP8X4X + +config SYS_BOARD + default "lp8x4x" + +config SYS_VENDOR + default "icpdas" + +config SYS_CONFIG_NAME + default "lp8x4x" + +endif diff --git a/board/icpdas/lp8x4x/MAINTAINERS b/board/icpdas/lp8x4x/MAINTAINERS new file mode 100644 index 0000000000..90a82e3fe4 --- /dev/null +++ b/board/icpdas/lp8x4x/MAINTAINERS @@ -0,0 +1,6 @@ +LP8X4X BOARD +M: Sergey Yanovich +S: Maintained +F: board/icpdas/lp8x4x/ +F: include/configs/lp8x4x.h +F: configs/lp8x4x_defconfig diff --git a/board/icpdas/lp8x4x/Makefile b/board/icpdas/lp8x4x/Makefile index 270bcac9af..88e0606e1e 100644 --- a/board/icpdas/lp8x4x/Makefile +++ b/board/icpdas/lp8x4x/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := lp8x4x.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := lp8x4x.o diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c index 1b68ef332a..a136dc4c37 100644 --- a/board/icpdas/lp8x4x/lp8x4x.c +++ b/board/icpdas/lp8x4x/lp8x4x.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -58,17 +59,26 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_CMD_USB -int usb_board_init(void) +int board_usb_init(int index, enum usb_init_type init) { - writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); + if (index !=0 || init != USB_INIT_HOST) + return -1; + + writel(readl(CKEN) | CKEN10_USBHOST, CKEN); + + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); + udelay(11); + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); while (readl(UHCHR) & UHCHR_FSBIR) continue; /* required by checkpath.pl */ + writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); + writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA); + writel(readl(UHCRHDA) | 0x800, UHCRHDA); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); @@ -82,19 +92,10 @@ int usb_board_init(void) /* Set port power control mask bits, only 3 ports. */ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - return 0; } -void usb_board_init_fail(void) -{ - return; -} - -void usb_board_stop(void) +int usb_board_stop(void) { writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); @@ -103,32 +104,25 @@ void usb_board_stop(void) writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); + writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR); + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); - return; + return 0; } -#endif -#ifdef CONFIG_DRIVER_DM9000 -void lp8x4x_eth1_mac_init(void) +int board_usb_cleanup(int index, enum usb_init_type init) { - u8 eth1addr[8]; - int i; - u8 reg; - - eth_getenv_enetaddr_by_index("eth", 1, eth1addr); - if (!is_valid_ether_addr(eth1addr)) - return; - - for (i = 0, reg = 0x10; i < 6; i++, reg++) { - writeb(reg, (u8 *)(DM9000_IO_2)); - writeb(eth1addr[i], (u8 *)(DM9000_DATA_2)); - } + if (index !=0 || init != USB_INIT_HOST) + return -1; + + return usb_board_stop(); } +#endif +#ifdef CONFIG_DRIVER_DM9000 int board_eth_init(bd_t *bis) { - lp8x4x_eth1_mac_init(); return dm9000_initialize(bis); } #endif diff --git a/board/icu862/Makefile b/board/icu862/Makefile deleted file mode 100644 index e1ac275ccd..0000000000 --- a/board/icu862/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/icu862/flash.c b/board/icu862/flash.c deleted file mode 100644 index a84ab99f35..0000000000 --- a/board/icu862/flash.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, - size_b0 >> 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - /* ICU862 Board has only one Flash Bank */ - flash_info[0].size = size_b0; - - return size_b0; - -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) { - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00040000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: puts ("AMD "); break; - case FLASH_MAN_FUJ: puts ("FUJITSU "); break; - case FLASH_MAN_BM: puts ("BRIGHT MICRO "); break; - default: puts ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: puts ("AM29LV033C (32 Mbit)\n"); - break; - default: puts ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - puts ("\n "); - } - - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - - puts ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; -#if 0 - ulong base = (ulong)addr; -#endif - uchar value; - - /* Write auto select command: read Manufacturer ID */ -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; -#endif - - value = addr[0]; - - switch (value + (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = addr[1]; /* device ID */ - - switch ((unsigned long)value) { - case AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV033C: - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - flash_get_offsets ((ulong)addr, &flash_info[0]); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); -#if 1 - /* We don't know why it happens, but on ICU Board * - * for AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if ( i == 32 ) { - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - } -#endif - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; -#if 0 - *addr = 0x00F000F0; /* reset bank */ -#else - *addr = 0xF0F0F0F0; /* reset bank */ -#endif - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - puts ("- missing\n"); - } else { - puts ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - puts ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - puts ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); -#if 0 - addr[0] = 0x00300030; -#else - addr[0] = 0x30303030; -#endif - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); -#if 0 - while ((addr[0] & 0x00800080) != 0x00800080) -#else - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) -#endif - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - puts ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#if 0 - addr[0] = 0x00F000F0; /* reset bank */ -#else - addr[0] = 0xF0F0F0F0; /* reset bank */ -#endif - - puts (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; -#endif - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); -#if 0 - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) -#else - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) -#endif - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c deleted file mode 100644 index 4c0e919739..0000000000 --- a/board/icu862/icu862.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Memory Controller Using - * - * CS0 - Flash memory (0x40000000) - * CS1 - SDRAM (0x00000000} - * CS2 - S/UNI Ultra ATM155 - * CS3 - IDT 77106 ATM25 - * CS4 - DSP HPI - * CS5 - E1/T1 Interface device - * CS6 - PCMCIA device - * CS7 - PCMCIA device - */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -const uint sdram_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* MRS initialization (offset 5) */ - - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: ICU862 Board\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - unsigned long reg; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 to the SDRAM bank at - * preliminary address - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (200); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c deleted file mode 100644 index dbe3c3cf72..0000000000 --- a/board/icu862/pcmcia.c +++ /dev/null @@ -1,262 +0,0 @@ -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "ICU862" - -static void cfg_port_B (void) -{ - volatile cpm8xx_t *cp; - uint reg; - - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* - * Configure Port B for TPS2205 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - reg = cp->cp_pbdat; - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */ - TPS2205_SHDN); /* enable switch */ - cp->cp_pbdat = reg; - - cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS); - - reg = cp->cp_pbdir & ~(TPS2205_INPUTS); - cp->cp_pbdir = reg | TPS2205_OUTPUTS; - - debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", - cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); -} - -int pcmcia_hardware_enable(int slot) -{ - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, pipr, mask; - int i; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */ - cfg_port_B (); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - reg = cp->cp_pbdat; - if ((pipr & mask) == mask) { - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC3); /* 3V off */ - reg &= ~(TPS2205_VCC5); /* 5V on */ - puts (" 5.0V card found: "); - } else { - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC5); /* 5V off */ - reg &= ~(TPS2205_VCC3); /* 3V on */ - puts (" 3.3V card found: "); - } - - debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n", - reg, - (reg & TPS2205_VCC3) ? "off" : "on", - (reg & TPS2205_VCC5) ? "off" : "on", - (reg & TPS2205_VPP_PGM) ? "off" : "on", - (reg & TPS2205_VPP_VCC) ? "off" : "on" ); - - cp->cp_pbdat = reg; - - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if ((cp->cp_pbdat & TPS2205_OC) == 0) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - cp->cp_pbdat &= ~(TPS2205_SHDN); - return (1); - } - udelay (100); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* Shut down */ - cp->cp_pbdat &= ~(TPS2205_SHDN); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_port_B (); /* Enables switch, but all in Hi-Z */ - - reg = cp->cp_pbdat; - - switch(vcc) { - case 0: break; /* Switch off */ - case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */ - case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */ - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - cp->cp_pbdat = reg; - -#ifdef DEBUG -{ - char *s; - - if ((reg & TPS2205_VCC3) == 0) { - s = "at 3.3V"; - } else if ((reg & TPS2205_VCC5) == 0) { - s = "at 5.0V"; - } else { - s = "down"; - } - printf ("PCMCIA powered %s\n", s); -} -#endif - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds deleted file mode 100644 index 00f63d2232..0000000000 --- a/board/icu862/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug deleted file mode 100644 index c7c6116b8b..0000000000 --- a/board/icu862/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/idmr/Makefile b/board/idmr/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/idmr/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/idmr/config.mk b/board/idmr/config.mk deleted file mode 100644 index 840a37e856..0000000000 --- a/board/idmr/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xff800000 diff --git a/board/idmr/flash.c b/board/idmr/flash.c deleted file mode 100644 index 52eb105c32..0000000000 --- a/board/idmr/flash.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE 0x800000 -#define EN29LV640 0x227e227e - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (EN29LV640 & FLASH_TYPEMASK): - printf ("EN29LV640 (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (EN29LV640 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + 0x10000 * j; - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, prot, sect; - int rc = ERR_OK; - int chip1; - ulong start; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - printf("Waiting 10 ms..."); - udelay (10000); - -/* for (i = 0; i < 10 * 1000 * 1000; ++i) - asm(" nop"); -*/ - - printf("done\n"); - if (iflag) - enable_interrupts (); - - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - int chip1; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c deleted file mode 100644 index 73660d802d..0000000000 --- a/board/idmr/idmr.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int checkboard (void) { - puts ("Board: iDMR\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - int i; - - /* - * After reset, CS0 is configured to cover entire address space. We - * need to configure it to its proper values, so that writes to - * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do - * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual). - */ - - /* Flash chipselect, CS0 */ - /* ;CSAR0: Flash at 0xFF800000 */ - mbar_writeShort(0x0080, 0xFF80); - - /* CSCR0: Flash 6 waits, 16bit */ - mbar_writeShort(0x008A, 0x1980); - - /* CSMR0: Flash 8MB, R/W, valid */ - mbar_writeLong(0x0084, 0x007F0001); - - - /* - * SDRAM configuration proper - */ - - /* - * Address/Data Pin Assignment Reg.: enable address lines 23-21; do - * not enable data pins D[15:0], as we have 16 bit port to SDRAM - */ - mbar_writeByte(MCF_GPIO_PAR_AD, - MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | - MCF_GPIO_AD_ADDR21); - - /* No need to configure BS pins - reset values are OK */ - - /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */ - mbar_writeByte(MCF_GPIO_PAR_CS, 0x00); - - /* SDRAM Control Pin Assignment Reg. */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, - MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */ - MCF_GPIO_SDRAM_SDWE | - MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | - MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_01); - - /* - * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5 - * iterations will do, but we do 10 just to be safe. - */ - for (i = 0; i < 10; ++i) - asm(" nop"); - - - /* 1. Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */ - MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */ - - - /* - * 2. Initialize DACR0 - * - * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1) - * CBM: cmd at A20, bank select bits 21 and up - * PS: 16 bit - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) | - MCF_SDRAMC_DACRn_BA(0x00) | - MCF_SDRAMC_DACRn_CASL(0x03) | - MCF_SDRAMC_DACRn_CBM(0x03) | - MCF_SDRAMC_DACRn_PS(0x03)); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M | - MCF_SDRAMC_DMRn_V); - - - /* 3. Set IP bit in DACR to initiate PALL command */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_IP); - - /* Write to this block to initiate precharge */ - *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5; - - /* - * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We - * wait a wee longer, just to be safe. - */ - for (i = 0; i < 5; ++i) - asm(" nop"); - - - /* 4. Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_RE); - - /* - * Wait for at least 8 auto refresh cycles to occur, i.e. at least - * 781 bus cycles. - */ - for (i = 0; i < 1000; ++i) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_MRS); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 3 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds deleted file mode 100644 index 4071f70d45..0000000000 --- a/board/idmr/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ids/ids8313/Kconfig b/board/ids/ids8313/Kconfig new file mode 100644 index 0000000000..d165b4be7a --- /dev/null +++ b/board/ids/ids8313/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IDS8313 + +config SYS_BOARD + default "ids8313" + +config SYS_VENDOR + default "ids" + +config SYS_CONFIG_NAME + default "ids8313" + +endif diff --git a/board/ids/ids8313/MAINTAINERS b/board/ids/ids8313/MAINTAINERS new file mode 100644 index 0000000000..c5b2f9ed0a --- /dev/null +++ b/board/ids/ids8313/MAINTAINERS @@ -0,0 +1,6 @@ +IDS8313 BOARD +M: Heiko Schocher +S: Maintained +F: board/ids/ids8313/ +F: include/configs/ids8313.h +F: configs/ids8313_defconfig diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile new file mode 100644 index 0000000000..56cfd403f4 --- /dev/null +++ b/board/ids/ids8313/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2013 +# Heiko Schocher, DENX Software Engineering, +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ids8313.o diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c new file mode 100644 index 0000000000..e7838dcd2a --- /dev/null +++ b/board/ids/ids8313/ids8313.c @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (c) 2011 IDS GmbH, Germany + * ids8313.c - ids8313 board support. + * + * Sergej Stepanov + * Based on board/freescale/mpc8313erdb/mpc8313erdb.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +/** CPLD contains the info about: + * - board type: *pCpld & 0xF0 + * - hw-revision: *pCpld & 0x0F + * - cpld-revision: *pCpld+1 + */ +int checkboard(void) +{ + char *pcpld = (char *)CONFIG_SYS_CPLD_BASE; + u8 u8Vers = readb(pcpld); + u8 u8Revs = readb(pcpld + 1); + + printf("Board: "); + switch (u8Vers & 0xF0) { + case '\x40': + printf("CU73X"); + break; + case '\x50': + printf("CC73X"); + break; + default: + printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs); + return 0; + } + printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n", + u8Vers & 0x0F, u8Revs & 0xFF); + return 0; +} + +/* + * fixed sdram init + */ +int fixed_sdram(unsigned long config) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE << 20; + +#ifndef CONFIG_SYS_RAMBOOT + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + sync(); + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + udelay(50000); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], config); + + /* currently we use only one CS, so disable the other banks */ + out_be32(&im->ddr.cs_config[1], 0); + out_be32(&im->ddr.cs_config[2], 0); + out_be32(&im->ddr.cs_config[3], 0); + + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); + + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + sync(); + udelay(300); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + /* now check the real size */ + disable_addr_trans(); + msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + enable_addr_trans(); +#endif + return msize; +} + +static int setup_sdram(void) +{ + u32 msize = CONFIG_SYS_DDR_SIZE << 20; + long int size_01, size_02; + + size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG); + size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256); + + if (size_01 > size_02) + msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG); + else + msize = size_02; + + return msize; +} + +phys_size_t initdram(int board_type) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + fsl_lbc_t *lbc = &im->im_lbc; + u32 msize = 0; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + msize = setup_sdram(); + + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + sync(); + + return msize; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + + return 0; +} +#endif + +/* gpio mask for spi_cs */ +#define IDSCPLD_SPI_CS_MASK 0x00000001 +/* spi_cs multiplexed through cpld */ +#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf) + +#if defined(CONFIG_MISC_INIT_R) +/* srp umcr mask for rts */ +#define IDSUMCR_RTS_MASK 0x04 +int misc_init_r(void) +{ + /*srp*/ + duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0]; + duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1]; + + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; + + /* deactivate spi_cs channels */ + out_8(spi_base, 0); + /* deactivate the spi_cs */ + setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK); + /*srp - deactivate rts*/ + out_8(&uart1->umcr, IDSUMCR_RTS_MASK); + out_8(&uart2->umcr, IDSUMCR_RTS_MASK); + + + gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE; + return 0; +} +#endif + +#ifdef CONFIG_MPC8XXX_SPI +/* + * The following are used to control the SPI chip selects + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && ((cs >= 0) && (cs <= 2)); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; + + /* select the spi_cs channel */ + out_8(spi_base, 1 << slave->cs); + /* activate the spi_cs */ + clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; + + /* select the spi_cs channel */ + out_8(spi_base, 1 << slave->cs); + /* deactivate the spi_cs */ + setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); +} +#endif /* CONFIG_HARD_SPI */ diff --git a/board/ids8247/Makefile b/board/ids8247/Makefile deleted file mode 100644 index b2009e6eb1..0000000000 --- a/board/ids8247/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Heiko Schocher, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c deleted file mode 100644 index de6b8fbd9b..0000000000 --- a/board/ids8247/ids8247.c +++ /dev/null @@ -1,390 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ - /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */ -#else /* normal I/O port pins */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ -#endif - /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ - /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ - /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ - /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */ - /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */ - /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */ - /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */ - /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */ - /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */ - /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */ - /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */ - /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */ - /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */ -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */ -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: IDS 8247\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - long psize; - - psize = 16 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2, - (uchar *) CONFIG_SYS_SDRAM_BASE); -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -int misc_init_r (void) -{ - gd->bd->bi_flashstart = 0xff800000; - return 0; -} - -#if defined(CONFIG_CMD_NAND) -#include -#include -#include - -static u8 hwctl; - -static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) { - hwctl |= 0x1; - writeb(0x00, (this->IO_ADDR_W + 0x0a)); - } else { - hwctl &= ~0x1; - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if ( ctrl & NAND_ALE ) { - hwctl |= 0x2; - writeb(0x00, (this->IO_ADDR_W + 0x09)); - } else { - hwctl &= ~0x2; - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if ( (ctrl & NAND_NCE) != NAND_NCE) - writeb(0x00, (this->IO_ADDR_W + 0x0c)); - else - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); - -} - -static u_char ids_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - - return readb(this->IO_ADDR_R); -} - -static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *nand = mtd->priv; - int i; - - for (i = 0; i < len; i++) { - if (hwctl & 0x1) - writeb(buf[i], (nand->IO_ADDR_W + 0x02)); - else if (hwctl & 0x2) - writeb(buf[i], (nand->IO_ADDR_W + 0x01)); - else - writeb(buf[i], nand->IO_ADDR_W); - } -} - -static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - int i; - - for (i = 0; i < len; i++) { - buf[i] = readb(this->IO_ADDR_R); - } -} - -static int ids_nand_dev_ready(struct mtd_info *mtd) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); - return 1; -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->ecc.mode = NAND_ECC_SOFT; - - /* Reference hardware control function */ - nand->cmd_ctrl = ids_nand_hwctrl; - nand->read_byte = ids_nand_read_byte; - nand->write_buf = ids_nand_write_buf; - nand->read_buf = ids_nand_read_buf; - nand->dev_ready = ids_nand_dev_ready; - nand->chip_delay = 12; - - return 0; -} - -#endif /* CONFIG_CMD_NAND */ - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup( blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/ifm/ac14xx/Kconfig b/board/ifm/ac14xx/Kconfig new file mode 100644 index 0000000000..97e80d5ddd --- /dev/null +++ b/board/ifm/ac14xx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AC14XX + +config SYS_BOARD + default "ac14xx" + +config SYS_VENDOR + default "ifm" + +config SYS_CONFIG_NAME + default "ac14xx" + +endif diff --git a/board/ifm/ac14xx/MAINTAINERS b/board/ifm/ac14xx/MAINTAINERS new file mode 100644 index 0000000000..8fd74e516e --- /dev/null +++ b/board/ifm/ac14xx/MAINTAINERS @@ -0,0 +1,6 @@ +AC14XX BOARD +M: Anatolij Gustschin +S: Maintained +F: board/ifm/ac14xx/ +F: include/configs/ac14xx.h +F: configs/ac14xx_defconfig diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile index f78fe13d35..55def60417 100644 --- a/board/ifm/ac14xx/Makefile +++ b/board/ifm/ac14xx/Makefile @@ -4,25 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ac14xx.o diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c index 0fbdfdbf71..5d2ab2fad3 100644 --- a/board/ifm/ac14xx/ac14xx.c +++ b/board/ifm/ac14xx/ac14xx.c @@ -608,8 +608,10 @@ int checkboard(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/ifm/o2dnt2/Kconfig b/board/ifm/o2dnt2/Kconfig new file mode 100644 index 0000000000..e9d32ddc54 --- /dev/null +++ b/board/ifm/o2dnt2/Kconfig @@ -0,0 +1,77 @@ +if TARGET_O2D + +config SYS_BOARD + default "o2dnt2" + +config SYS_VENDOR + default "ifm" + +config SYS_CONFIG_NAME + default "o2d" + +endif + +if TARGET_O2D300 + +config SYS_BOARD + default "o2dnt2" + +config SYS_VENDOR + default "ifm" + +config SYS_CONFIG_NAME + default "o2d300" + +endif + +if TARGET_O2DNT2 + +config SYS_BOARD + default "o2dnt2" + +config SYS_VENDOR + default "ifm" + +config SYS_CONFIG_NAME + default "o2dnt2" + +endif + +if TARGET_O2I + +config SYS_BOARD + default "o2dnt2" + +config SYS_VENDOR + default "ifm" + +config SYS_CONFIG_NAME + default "o2i" + +endif + +if TARGET_O2MNT + +config SYS_BOARD + default "o2dnt2" + +config SYS_VENDOR + default "ifm" + +config SYS_CONFIG_NAME + default "o2mnt" + +endif + +if TARGET_O3DNT + +config SYS_BOARD + default "o2dnt2" + +config SYS_VENDOR + default "ifm" + +config SYS_CONFIG_NAME + default "o3dnt" + +endif diff --git a/board/ifm/o2dnt2/MAINTAINERS b/board/ifm/o2dnt2/MAINTAINERS new file mode 100644 index 0000000000..002f89e729 --- /dev/null +++ b/board/ifm/o2dnt2/MAINTAINERS @@ -0,0 +1,20 @@ +O2DNT2 BOARD +M: Anatolij Gustschin +S: Maintained +F: board/ifm/o2dnt2/ +F: include/configs/o2d.h +F: configs/O2D_defconfig +F: include/configs/o2d300.h +F: configs/O2D300_defconfig +F: include/configs/o2dnt2.h +F: configs/O2DNT2_defconfig +F: configs/O2DNT2_RAMBOOT_defconfig +F: include/configs/o2i.h +F: configs/O2I_defconfig +F: include/configs/o2mnt.h +F: configs/O2MNT_defconfig +F: configs/O2MNT_O2M110_defconfig +F: configs/O2MNT_O2M112_defconfig +F: configs/O2MNT_O2M113_defconfig +F: include/configs/o3dnt.h +F: configs/O3DNT_defconfig diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile index 1dd3fe9555..64d6ba8c55 100644 --- a/board/ifm/o2dnt2/Makefile +++ b/board/ifm/o2dnt2/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := o2dnt2.o diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c index 6716ffc9d0..ca09767d28 100644 --- a/board/ifm/o2dnt2/o2dnt2.c +++ b/board/ifm/o2dnt2/o2dnt2.c @@ -364,7 +364,7 @@ int update_flash_size(int flash_size) } #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int phy_addr = CONFIG_PHY_ADDR; char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; @@ -380,5 +380,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif /* fix up the phy address */ do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig new file mode 100644 index 0000000000..4c06d0c0d8 --- /dev/null +++ b/board/imgtec/malta/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MALTA + +config SYS_BOARD + default "malta" + +config SYS_VENDOR + default "imgtec" + +config SYS_CONFIG_NAME + default "malta" + +endif diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS new file mode 100644 index 0000000000..a0b3284992 --- /dev/null +++ b/board/imgtec/malta/MAINTAINERS @@ -0,0 +1,7 @@ +MALTA BOARD +M: Paul Burton +S: Maintained +F: board/imgtec/malta/ +F: include/configs/malta.h +F: configs/malta_defconfig +F: configs/maltael_defconfig diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile new file mode 100644 index 0000000000..19dd3a3c3b --- /dev/null +++ b/board/imgtec/malta/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = malta.o +obj-y += lowlevel_init.o +obj-y += superio.o diff --git a/board/imgtec/malta/flash-malta-boot.tcl b/board/imgtec/malta/flash-malta-boot.tcl new file mode 100644 index 0000000000..0eedf07ace --- /dev/null +++ b/board/imgtec/malta/flash-malta-boot.tcl @@ -0,0 +1,40 @@ +# +# Copyright (C) 2013 Imagination Technologies +# +# Programs a MIPS Malta boot flash with a flat binary image. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +proc flash-boot { binfile } { + puts "flash monitor binary $binfile" + config Coherent on + config CoherencyDuringLoad on + + if {[endian]=="big"} { + puts "CPU in BE mode" + flash device sharp_16x32_be; + } else { + puts "CPU in LE mode" + flash device sharp_16x32; + } + + flash clear all; + flash set 0xBE000000..0xBE0FFFFF + flash erase sector 0xbe000000; + flash erase sector 0xbe020000; + flash erase sector 0xbe040000; + flash erase sector 0xbe060000; + flash erase sector 0xbe080000; + flash erase sector 0xbe0a0000; + flash erase sector 0xbe0c0000; + flash erase sector 0xbe0e0000; + puts "finished erasing boot flash"; + + puts "programming flash, please be patient" + load bin 0xbe000000 $binfile size4 + + flash clear all + config CoherencyDuringLoad off + puts "finished programming boot flash"; +} diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S new file mode 100644 index 0000000000..ae09c27d07 --- /dev/null +++ b/board/imgtec/malta/lowlevel_init.S @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_SYS_BIG_ENDIAN +#define CPU_TO_GT32(_x) ((_x)) +#else +#define CPU_TO_GT32(_x) ( \ + (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ + (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) +#endif + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + /* disable any L2 cache for now */ + sync + mfc0 t0, CP0_CONFIG, 2 + ori t0, t0, 0x1 << 12 + mtc0 t0, CP0_CONFIG, 2 + + /* detect the core card */ + li t0, KSEG1ADDR(MALTA_REVISION) + lw t0, 0(t0) + srl t0, t0, MALTA_REVISION_CORID_SHF + andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ + MALTA_REVISION_CORID_SHF) + + /* core cards using the gt64120 system controller */ + li t1, MALTA_REVISION_CORID_CORE_LV + beq t0, t1, _gt64120 + + /* core cards using the MSC01 system controller */ + li t1, MALTA_REVISION_CORID_CORE_FPGA6 + beq t0, t1, _msc01 + nop + + /* unknown system controller */ + b . + nop + + /* + * Load BAR registers of GT64120 as done by YAMON + * + * based on a patch sent by Antony Pavlov + * to the barebox mailing list. + * The subject of the original patch: + * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' + * URL: + * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html + * + * based on write_bootloader() in qemu.git/hw/mips_malta.c + * see GT64120 manual and qemu.git/hw/gt64xxx.c for details + */ +_gt64120: + /* move GT64120 registers from 0x14000000 to 0x1be00000 */ + li t1, KSEG1ADDR(GT_DEF_BASE) + li t0, CPU_TO_GT32(0xdf000000) + sw t0, GT_ISD_OFS(t1) + + /* setup MEM-to-PCI0 mapping */ + li t1, KSEG1ADDR(MALTA_GT_BASE) + + /* setup PCI0 io window to 0x18000000-0x181fffff */ + li t0, CPU_TO_GT32(0xc0000000) + sw t0, GT_PCI0IOLD_OFS(t1) + li t0, CPU_TO_GT32(0x40000000) + sw t0, GT_PCI0IOHD_OFS(t1) + + /* setup PCI0 mem windows */ + li t0, CPU_TO_GT32(0x80000000) + sw t0, GT_PCI0M0LD_OFS(t1) + li t0, CPU_TO_GT32(0x3f000000) + sw t0, GT_PCI0M0HD_OFS(t1) + + li t0, CPU_TO_GT32(0xc1000000) + sw t0, GT_PCI0M1LD_OFS(t1) + li t0, CPU_TO_GT32(0x5e000000) + sw t0, GT_PCI0M1HD_OFS(t1) + + jr ra + nop + + /* + * + */ +_msc01: + /* setup peripheral bus controller clock divide */ + li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE) + li t1, 0x1 << MSC01_PBC_CLKCFG_SHF + sw t1, MSC01_PBC_CLKCFG_OFS(t0) + + /* tweak peripheral bus controller timings */ + li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \ + (0x1 << MSC01_PBC_CS0TIM_CAT_SHF) + sw t1, MSC01_PBC_CS0TIM_OFS(t0) + li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \ + (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \ + (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \ + (0x2 << MSC01_PBC_CS0RW_WAT_SHF) + sw t1, MSC01_PBC_CS0RW_OFS(t0) + lw t1, MSC01_PBC_CS0CFG_OFS(t0) + li t2, MSC01_PBC_CS0CFG_DTYP_MSK + and t1, t2 + ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \ + (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \ + (0x10 << MSC01_PBC_CS0CFG_WS_SHF) + sw t1, MSC01_PBC_CS0CFG_OFS(t0) + + /* setup basic address decode */ + li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE) + li t1, 0x0 + li t2, -CONFIG_SYS_MEM_SIZE + sw t1, MSC01_BIU_MCBAS1L_OFS(t0) + sw t2, MSC01_BIU_MCMSK1L_OFS(t0) + sw t1, MSC01_BIU_MCBAS2L_OFS(t0) + sw t2, MSC01_BIU_MCMSK2L_OFS(t0) + + /* initialise IP1 - unused */ + li t1, MALTA_MSC01_IP1_BASE + li t2, -MALTA_MSC01_IP1_SIZE + sw t1, MSC01_BIU_IP1BAS1L_OFS(t0) + sw t2, MSC01_BIU_IP1MSK1L_OFS(t0) + sw t1, MSC01_BIU_IP1BAS2L_OFS(t0) + sw t2, MSC01_BIU_IP1MSK2L_OFS(t0) + + /* initialise IP2 - PCI */ + li t1, MALTA_MSC01_IP2_BASE1 + li t2, -MALTA_MSC01_IP2_SIZE1 + sw t1, MSC01_BIU_IP2BAS1L_OFS(t0) + sw t2, MSC01_BIU_IP2MSK1L_OFS(t0) + li t1, MALTA_MSC01_IP2_BASE2 + li t2, -MALTA_MSC01_IP2_SIZE2 + sw t1, MSC01_BIU_IP2BAS2L_OFS(t0) + sw t2, MSC01_BIU_IP2MSK2L_OFS(t0) + + /* initialise IP3 - peripheral bus controller */ + li t1, MALTA_MSC01_IP3_BASE + li t2, -MALTA_MSC01_IP3_SIZE + sw t1, MSC01_BIU_IP3BAS1L_OFS(t0) + sw t2, MSC01_BIU_IP3MSK1L_OFS(t0) + sw t1, MSC01_BIU_IP3BAS2L_OFS(t0) + sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) + + /* setup PCI memory */ + li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE) + li t1, MALTA_MSC01_PCIMEM_BASE + li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK + li t3, MALTA_MSC01_PCIMEM_MAP + sw t1, MSC01_PCI_SC2PMBASL_OFS(t0) + sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0) + sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0) + + /* setup PCI I/O */ + li t1, MALTA_MSC01_PCIIO_BASE + li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK + li t3, MALTA_MSC01_PCIIO_MAP + sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0) + sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0) + sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) + + /* setup PCI_BAR0 memory window */ + li t1, -CONFIG_SYS_MEM_SIZE + sw t1, MSC01_PCI_BAR0_OFS(t0) + + /* setup PCI to SysCon/CPU translation */ + sw t1, MSC01_PCI_P2SCMSKL_OFS(t0) + sw zero, MSC01_PCI_P2SCMAPL_OFS(t0) + + /* setup PCI vendor & device IDs */ + li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \ + (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF) + sw t1, MSC01_PCI_HEAD0_OFS(t0) + + /* setup PCI subsystem vendor & device IDs */ + sw t1, MSC01_PCI_HEAD11_OFS(t0) + + /* setup PCI class, revision */ + li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \ + (0x1 << MSC01_PCI_HEAD2_REV_SHF) + sw t1, MSC01_PCI_HEAD2_OFS(t0) + + /* ensure a sane setup */ + sw zero, MSC01_PCI_HEAD3_OFS(t0) + sw zero, MSC01_PCI_HEAD4_OFS(t0) + sw zero, MSC01_PCI_HEAD5_OFS(t0) + sw zero, MSC01_PCI_HEAD6_OFS(t0) + sw zero, MSC01_PCI_HEAD7_OFS(t0) + sw zero, MSC01_PCI_HEAD8_OFS(t0) + sw zero, MSC01_PCI_HEAD9_OFS(t0) + sw zero, MSC01_PCI_HEAD10_OFS(t0) + sw zero, MSC01_PCI_HEAD12_OFS(t0) + sw zero, MSC01_PCI_HEAD13_OFS(t0) + sw zero, MSC01_PCI_HEAD14_OFS(t0) + sw zero, MSC01_PCI_HEAD15_OFS(t0) + + /* setup PCI command register */ + li t1, (PCI_COMMAND_FAST_BACK | \ + PCI_COMMAND_SERR | \ + PCI_COMMAND_PARITY | \ + PCI_COMMAND_MASTER | \ + PCI_COMMAND_MEMORY) + sw t1, MSC01_PCI_HEAD1_OFS(t0) + + /* setup PCI byte swapping */ +#ifdef CONFIG_SYS_BIG_ENDIAN + li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \ + (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF) + sw t1, MSC01_PCI_SWAP_OFS(t0) +#else + sw zero, MSC01_PCI_SWAP_OFS(t0) +#endif + + /* enable PCI host configuration cycles */ + lw t1, MSC01_PCI_CFG_OFS(t0) + li t2, MSC01_PCI_CFG_RA_MSK | \ + MSC01_PCI_CFG_G_MSK | \ + MSC01_PCI_CFG_EN_MSK + or t1, t1, t2 + sw t1, MSC01_PCI_CFG_OFS(t0) + + jr ra + nop diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c new file mode 100644 index 0000000000..79562f79a8 --- /dev/null +++ b/board/imgtec/malta/malta.c @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * Copyright (C) 2013 Imagination Technologies + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "superio.h" + +enum core_card { + CORE_UNKNOWN, + CORE_LV, + CORE_FPGA6, +}; + +enum sys_con { + SYSCON_UNKNOWN, + SYSCON_GT64120, + SYSCON_MSC01, +}; + +static void malta_lcd_puts(const char *str) +{ + int i; + void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); + + /* print up to 8 characters of the string */ + for (i = 0; i < min((int)strlen(str), 8); i++) { + __raw_writel(str[i], reg); + reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; + } + + /* fill the rest of the display with spaces */ + for (; i < 8; i++) { + __raw_writel(' ', reg); + reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; + } +} + +static enum core_card malta_core_card(void) +{ + u32 corid, rev; + + rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); + corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; + + switch (corid) { + case MALTA_REVISION_CORID_CORE_LV: + return CORE_LV; + + case MALTA_REVISION_CORID_CORE_FPGA6: + return CORE_FPGA6; + + default: + return CORE_UNKNOWN; + } +} + +static enum sys_con malta_sys_con(void) +{ + switch (malta_core_card()) { + case CORE_LV: + return SYSCON_GT64120; + + case CORE_FPGA6: + return SYSCON_MSC01; + + default: + return SYSCON_UNKNOWN; + } +} + +phys_size_t initdram(int board_type) +{ + return CONFIG_SYS_MEM_SIZE; +} + +int checkboard(void) +{ + enum core_card core; + + malta_lcd_puts("U-boot"); + puts("Board: MIPS Malta"); + + core = malta_core_card(); + switch (core) { + case CORE_LV: + puts(" CoreLV"); + break; + + case CORE_FPGA6: + puts(" CoreFPGA6"); + break; + + default: + puts(" CoreUnknown"); + } + + putc('\n'); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +void _machine_restart(void) +{ + void __iomem *reset_base; + + reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); + __raw_writel(GORESET, reset_base); + mdelay(1000); +} + +int board_early_init_f(void) +{ + void *io_base; + + /* choose correct PCI I/O base */ + switch (malta_sys_con()) { + case SYSCON_GT64120: + io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE); + break; + + case SYSCON_MSC01: + io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); + break; + + default: + return -1; + } + + /* setup FDC37M817 super I/O controller */ + malta_superio_init(io_base); + + return 0; +} + +int misc_init_r(void) +{ + rtc_reset(); + + return 0; +} + +struct serial_device *default_serial_console(void) +{ + switch (malta_sys_con()) { + case SYSCON_GT64120: + return &eserial1_device; + + default: + case SYSCON_MSC01: + return &eserial2_device; + } +} + +void pci_init_board(void) +{ + pci_dev_t bdf; + u32 val32; + u8 val8; + + switch (malta_sys_con()) { + case SYSCON_GT64120: + set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); + + gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), + 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, + 0x10000000, 0x10000000, 128 * 1024 * 1024, + 0x00000000, 0x00000000, 0x20000); + break; + + default: + case SYSCON_MSC01: + set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE)); + + msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), + 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, + MALTA_MSC01_PCIMEM_MAP, + CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), + MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, + 0x00000000, MALTA_MSC01_PCIIO_SIZE); + break; + } + + bdf = pci_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_0, 0); + if (bdf == -1) + panic("Failed to find PIIX4 PCI bridge\n"); + + /* setup PCI interrupt routing */ + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); + + /* mux SERIRQ onto SERIRQ pin */ + pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); + val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; + pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); + + /* enable SERIRQ - Linux currently depends upon this */ + pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); + val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; + pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); + + bdf = pci_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB, 0); + if (bdf == -1) + panic("Failed to find PIIX4 IDE controller\n"); + + /* enable bus master & IO access */ + val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_dword(bdf, PCI_COMMAND, val32); + + /* set latency */ + pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40); + + /* enable IDE/ATA */ + pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI, + PCI_CFG_PIIX4_IDETIM_IDE); + pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, + PCI_CFG_PIIX4_IDETIM_IDE); +} diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c new file mode 100644 index 0000000000..eaa14df39e --- /dev/null +++ b/board/imgtec/malta/superio.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * Setup code for the FDC37M817 super I/O controller + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define SIO_CONF_PORT 0x3f0 +#define SIO_DATA_PORT 0x3f1 + +enum sio_conf_key { + SIOCONF_DEVNUM = 0x07, + SIOCONF_ACTIVATE = 0x30, + SIOCONF_ENTER_SETUP = 0x55, + SIOCONF_BASE_HIGH = 0x60, + SIOCONF_BASE_LOW = 0x61, + SIOCONF_PRIMARY_INT = 0x70, + SIOCONF_EXIT_SETUP = 0xaa, + SIOCONF_MODE = 0xf0, +}; + +static struct { + u8 key; + u8 data; +} sio_config[] = { + /* tty0 */ + { SIOCONF_DEVNUM, 0x04 }, + { SIOCONF_BASE_HIGH, 0x03 }, + { SIOCONF_BASE_LOW, 0xf8 }, + { SIOCONF_MODE, 0x02 }, + { SIOCONF_PRIMARY_INT, 0x04 }, + { SIOCONF_ACTIVATE, 0x01 }, + + /* tty1 */ + { SIOCONF_DEVNUM, 0x05 }, + { SIOCONF_BASE_HIGH, 0x02 }, + { SIOCONF_BASE_LOW, 0xf8 }, + { SIOCONF_MODE, 0x02 }, + { SIOCONF_PRIMARY_INT, 0x03 }, + { SIOCONF_ACTIVATE, 0x01 }, +}; + +void malta_superio_init(void *io_base) +{ + unsigned i; + + /* enter config state */ + writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT); + + /* configure peripherals */ + for (i = 0; i < ARRAY_SIZE(sio_config); i++) { + writeb(sio_config[i].key, io_base + SIO_CONF_PORT); + writeb(sio_config[i].data, io_base + SIO_DATA_PORT); + } + + /* exit config state */ + writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT); +} diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h new file mode 100644 index 0000000000..1450da56dd --- /dev/null +++ b/board/imgtec/malta/superio.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * Setup code for the FDC37M817 super I/O controller + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOARD_MALTA_SUPERIO_H__ +#define __BOARD_MALTA_SUPERIO_H__ + +extern void malta_superio_init(void *io_base); + +#endif /* __BOARD_MALTA_SUPERIO_H__ */ diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig new file mode 100644 index 0000000000..d3d202556d --- /dev/null +++ b/board/imx31_phycore/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX31_PHYCORE + +config SYS_BOARD + default "imx31_phycore" + +config SYS_SOC + default "mx31" + +config SYS_CONFIG_NAME + default "imx31_phycore" + +endif diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS new file mode 100644 index 0000000000..41f6cae81b --- /dev/null +++ b/board/imx31_phycore/MAINTAINERS @@ -0,0 +1,11 @@ +IMX31_PHYCORE BOARD +#M: - +S: Maintained +F: board/imx31_phycore/ +F: include/configs/imx31_phycore.h +F: configs/imx31_phycore_defconfig + +IMX31_PHYCORE_EET BOARD +#M: (resigned) Guennadi Liakhovetski +S: Orphan (since 2013-09) +F: configs/imx31_phycore_eet_defconfig diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile index 5aaf766a0d..e781c13936 100644 --- a/board/imx31_phycore/Makefile +++ b/board/imx31_phycore/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := imx31_phycore.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := imx31_phycore.o +obj-y += lowlevel_init.o diff --git a/board/in-circuit/grasshopper/Kconfig b/board/in-circuit/grasshopper/Kconfig new file mode 100644 index 0000000000..30e3855ae0 --- /dev/null +++ b/board/in-circuit/grasshopper/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GRASSHOPPER + +config SYS_BOARD + default "grasshopper" + +config SYS_VENDOR + default "in-circuit" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "grasshopper" + +endif diff --git a/board/in-circuit/grasshopper/MAINTAINERS b/board/in-circuit/grasshopper/MAINTAINERS new file mode 100644 index 0000000000..db8bd0a546 --- /dev/null +++ b/board/in-circuit/grasshopper/MAINTAINERS @@ -0,0 +1,6 @@ +GRASSHOPPER BOARD +M: Andreas Bießmann +S: Maintained +F: board/in-circuit/grasshopper/ +F: include/configs/grasshopper.h +F: configs/grasshopper_defconfig diff --git a/board/in-circuit/grasshopper/Makefile b/board/in-circuit/grasshopper/Makefile index 1930e89cf1..04576358fd 100644 --- a/board/in-circuit/grasshopper/Makefile +++ b/board/in-circuit/grasshopper/Makefile @@ -7,23 +7,4 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += grasshopper.o diff --git a/board/incaip/Makefile b/board/incaip/Makefile deleted file mode 100644 index ed7370f9a6..0000000000 --- a/board/incaip/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o -SOBJS = lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/incaip/README b/board/incaip/README deleted file mode 100644 index 132915292e..0000000000 --- a/board/incaip/README +++ /dev/null @@ -1,57 +0,0 @@ - -Flash programming on the INCA-IP board is complicated because of the -EBU swapping unit. A BDI2000 can be used for flash programming only -if the EBU swapping unit is enabled; otherwise it will not detect the -flash memory. But the EBU swapping unit is disadbled after reset, so -if you program some code to flash with the swapping unit on, it will -not be runnable with the swapping unit off. - -The consequence is that you have to write a pre-swapped image to -flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is -provided in the "tools/" directory. Use it as follows: - - bash$ ./inca-swap-bytes u-boot.bin.swp - -Note that the current BDI config file _disables_ the EBU swapping -unit for the flash bank 0. To enable it, (this is required for the -BDI flash commands to work) uncomment the following line in the -config file: - - ;WM32 0xb8000260 0x404161ff ; Swapping unit enabled - -and comment out - - WM32 0xb8000260 0x004161ff ; Swapping unit disabled - -Alternatively, you can use "mm 0xb8000260 " commands to -enable/disable the swapping unit manually. - -Just for reference, here is the complete sequence of actions we took -to install a U-Boot image into flash. - - 1. ./inca-swap-bytes u-boot.bin.swp - - 2. From BDI: - - mm 0xb8000260 0x404161ff - erase 0xb0000000 - erase 0xb0010000 - prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin - mm 0xb8000260 0x004161ff - go 0xb0000000 - - -Ethernet autonegotiation needs some time to complete. Instead of -delaying the boot process in all cases, we just start the -autonegotiation process when U-Boot comes up and that is all. Most -likely, it will complete by the time the network transfer is -attempted for the first time. In the worst case, if a transfer is -attempted before the autonegotiation is complete, just a single -packet would be lost resulting in a single timeout error, and then -the transfer would proceed normally. So the time that we would have -lost unconditionally waiting for the autonegotiation to complete, we -have to wait only if the file transfer is started immediately after -reset. We've verified that this works for all the clock -configurations. - -(C) 2003 Wolfgang Denk diff --git a/board/incaip/config.mk b/board/incaip/config.mk deleted file mode 100644 index e854f8e655..0000000000 --- a/board/incaip/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# INCA-IP board with MIPS 4Kc CPU core -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xB0000000 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80100000 diff --git a/board/incaip/flash.c b/board/incaip/flash.c deleted file mode 100644 index a786ac9327..0000000000 --- a/board/incaip/flash.c +++ /dev/null @@ -1,655 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#if 0 -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa -#else -#define FLASH_CYCLE1 0x0554 -#define FLASH_CYCLE2 0x02ab -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; - ulong * buscon = (ulong *) - ((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2); - - /* Disable write protection */ - *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS; - -#if 1 - memset(&flash_info[i], 0, sizeof(flash_info_t)); -#endif - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[1] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c deleted file mode 100644 index 911fb63fcd..0000000000 --- a/board/incaip/incaip.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -extern uint incaip_get_cpuclk(void); - -void _machine_restart(void) -{ - *INCA_IP_WDT_RST_REQ = 0x3f; -} - -static ulong max_sdram_size(void) -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CONFIG_SYS_DW 2 - - /* The only supported number of SDRAM banks is 4. - */ -#define CONFIG_SYS_NB 4 - - ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB; - - return size; -} - -phys_size_t initdram(int board_type) -{ - int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - */ - if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *INCA_IP_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *INCA_IP_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} - -int checkboard (void) -{ - unsigned long chipid = *INCA_IP_WDT_CHIPID; - int part_num; - - puts ("Board: INCA-IP "); - part_num = (chipid >> 12) & 0xffff; - switch (part_num) { - case 0xc0: - printf ("Standard Version, "); - break; - case 0xc1: - printf ("Basic Version, "); - break; - default: - printf ("Unknown Part Number 0x%x ", part_num); - break; - } - - printf ("Chip V1.%ld, ", (chipid >> 28)); - - printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000); - - set_io_port_base(0); - - return 0; -} - -#if defined(CONFIG_INCA_IP_SWITCH) -int board_eth_init(bd_t *bis) -{ - return inca_switch_initialize(bis); -} -#endif diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S deleted file mode 100644 index 702f9e0aa0..0000000000 --- a/board/incaip/lowlevel_init.S +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Memory sub-system initialization code for INCA-IP development board. - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -#define EBU_MODUL_BASE 0xB8000200 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0100(value) -#define MC_ERRADDR(value) 0x0108(value) -#define MC_IOGP(value) 0x0800(value) -#define MC_SELFRFSH(value) 0x0A00(value) -#define MC_CTRLENA(value) 0x1000(value) -#define MC_MRSCODE(value) 0x1008(value) -#define MC_CFGDW(value) 0x1010(value) -#define MC_CFGPB0(value) 0x1018(value) -#define MC_LATENCY(value) 0x1038(value) -#define MC_TREFRESH(value) 0x1040(value) - -#define CGU_MODUL_BASE 0xBF107000 -#define CGU_PLL1CR(value) 0x0008(value) -#define CGU_DIVCR(value) 0x0010(value) -#define CGU_MUXCR(value) 0x0014(value) -#define CGU_PLL1SR(value) 0x000C(value) - - .set noreorder - - -/* - * void ebu_init(long) - * - * a0 has the clock value we are going to run at - */ - .globl ebu_init - .ent ebu_init -ebu_init: -__ebu_init: - - li t1, EBU_MODUL_BASE - li t2, 0xA0000041 - sw t2, EBU_ADDSEL0(t1) - li t2, 0xA0800041 - sw t2, EBU_ADDSEL2(t1) - li t2, 0xBE0000F1 - sw t2, EBU_ADDSEL1(t1) - - li t3, 100000000 - beq a0, t3, 1f - nop - li t3, 133000000 - beq a0, t3, 2f - nop - li t3, 150000000 - beq a0, t3, 2f - nop - b 3f - nop - - /* 100 MHz */ -1: - li t2, 0x8841417D - sw t2, EBU_BUSCON0(t1) - sw t2, EBU_BUSCON2(t1) - li t2, 0x684142BD - b 3f - sw t2, EBU_BUSCON1(t1) /* delay slot */ - - /* 133 or 150 MHz */ -2: - li t2, 0x8841417E - sw t2, EBU_BUSCON0(t1) - sw t2, EBU_BUSCON2(t1) - li t2, 0x684143FD - sw t2, EBU_BUSCON1(t1) -3: - jr ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: -__cgu_init: - - li t1, CGU_MODUL_BASE - - li t3, 100000000 - beq a0, t3, 1f - nop - li t3, 133000000 - beq a0, t3, 2f - nop - li t3, 150000000 - beq a0, t3, 3f - nop - b 5f - nop - - /* 100 MHz clock */ -1: - li t2, 0x80000014 - sw t2, CGU_DIVCR(t1) - li t2, 0x80000000 - sw t2, CGU_MUXCR(t1) - li t2, 0x800B0001 - b 5f - sw t2, CGU_PLL1CR(t1) /* delay slot */ - - /* 133 MHz clock */ -2: - li t2, 0x80000054 - sw t2, CGU_DIVCR(t1) - li t2, 0x80000000 - sw t2, CGU_MUXCR(t1) - li t2, 0x800B0001 - b 5f - sw t2, CGU_PLL1CR(t1) /* delay slot */ - - /* 150 MHz clock */ -3: - li t2, 0x80000017 - sw t2, CGU_DIVCR(t1) - li t2, 0xC00B0001 - sw t2, CGU_PLL1CR(t1) - li t3, 0x80000000 -4: - lw t2, CGU_PLL1SR(t1) - and t2, t2, t3 - beq t2, zero, 4b - nop - li t2, 0x80000001 - sw t2, CGU_MUXCR(t1) -5: - jr ra - nop - - .end cgu_init - - -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: -__sdram_init: - - li t1, MC_MODUL_BASE - -#if 0 - /* Disable memory controller before changing any of its registers */ - sw zero, MC_CTRLENA(t1) -#endif - - li t2, 100000000 - beq a0, t2, 1f - nop - li t2, 133000000 - beq a0, t2, 2f - nop - li t2, 150000000 - beq a0, t2, 3f - nop - b 5f - nop - - /* 100 MHz clock */ -1: - /* Set clock ratio (clkrat=1:1, rddel=3) */ - li t2, 0x00000003 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 100MHz) */ - li t2, 0x0000061A - b 4f - sw t2, MC_TREFRESH(t1) - - /* 133 MHz clock */ -2: - /* Set clock ratio (clkrat=1:1, rddel=3) */ - li t2, 0x00000003 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 133MHz) */ - li t2, 0x00000822 - b 4f - sw t2, MC_TREFRESH(t1) - - /* 150 MHz clock */ -3: - /* Set clock ratio (clkrat=3:2, rddel=4) */ - li t2, 0x00000014 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 150MHz) */ - li t2, 0x00000927 - sw t2, MC_TREFRESH(t1) - -4: - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 /* CL = 2 */ - sw t2, MC_MRSCODE(t1) - - /* Set word width to 16 bit */ - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014C9 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00026325 /* BC PC100 */ - sw t2, MC_LATENCY(t1) - -5: - /* Finally enable the controller */ - li t2, 0x00000001 - sw t2, MC_CTRLENA(t1) - - jr ra - nop - - .end sdram_init - - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - - /* Disable Watchdog. - */ - la t9, disable_incaip_wdt - jalr t9 - nop - - /* EBU, CGU and SDRAM Initialization. - */ - li a0, CONFIG_CPU_CLOCK_RATE - move t0, ra - - /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init() - * modify t0 and a0. - */ - bal __cgu_init - nop - bal __ebu_init - nop - bal __sdram_init - nop - move ra, t0 - - jr ra - nop - - .end lowlevel_init diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig new file mode 100644 index 0000000000..94a41f01a5 --- /dev/null +++ b/board/inka4x0/Kconfig @@ -0,0 +1,9 @@ +if TARGET_INKA4X0 + +config SYS_BOARD + default "inka4x0" + +config SYS_CONFIG_NAME + default "inka4x0" + +endif diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS new file mode 100644 index 0000000000..246b2d4d69 --- /dev/null +++ b/board/inka4x0/MAINTAINERS @@ -0,0 +1,6 @@ +INKA4X0 BOARD +M: Detlev Zundel +S: Maintained +F: board/inka4x0/ +F: include/configs/inka4x0.h +F: configs/inka4x0_defconfig diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile index 14ddfa5ebf..c9a3540799 100644 --- a/board/inka4x0/Makefile +++ b/board/inka4x0/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o inkadiag.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := inka4x0.o inkadiag.o diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h deleted file mode 100644 index f16f450d01..0000000000 --- a/board/inka4x0/hyb25d512160bf-5.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index fc3333efe4..0a32f0e1b9 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -14,7 +14,7 @@ * (C) Copyright 2003-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig new file mode 100644 index 0000000000..762663a001 --- /dev/null +++ b/board/intel/crownbay/Kconfig @@ -0,0 +1,21 @@ +if TARGET_CROWNBAY + +config SYS_BOARD + default "crownbay" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "queensbay" + +config SYS_CONFIG_NAME + default "crownbay" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_QUEENSBAY + select BOARD_ROMSIZE_KB_1024 + +endif diff --git a/board/intel/crownbay/MAINTAINERS b/board/intel/crownbay/MAINTAINERS new file mode 100644 index 0000000000..1eb68693df --- /dev/null +++ b/board/intel/crownbay/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL CROWNBAY BOARD +M: Bin Meng +S: Maintained +F: board/intel/crownbay/ +F: include/configs/crownbay.h +F: configs/crownbay_defconfig diff --git a/board/intel/crownbay/Makefile b/board/intel/crownbay/Makefile new file mode 100644 index 0000000000..aeb219b4e5 --- /dev/null +++ b/board/intel/crownbay/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014, Bin Meng +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += crownbay.o start.o diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c new file mode 100644 index 0000000000..2a254efe3d --- /dev/null +++ b/board/intel/crownbay/crownbay.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, 4) + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/intel/crownbay/start.S b/board/intel/crownbay/start.S new file mode 100644 index 0000000000..cf92b4c0b3 --- /dev/null +++ b/board/intel/crownbay/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/intercontrol/digsy_mtc/Kconfig b/board/intercontrol/digsy_mtc/Kconfig new file mode 100644 index 0000000000..1cf2275d81 --- /dev/null +++ b/board/intercontrol/digsy_mtc/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DIGSY_MTC + +config SYS_BOARD + default "digsy_mtc" + +config SYS_VENDOR + default "intercontrol" + +config SYS_CONFIG_NAME + default "digsy_mtc" + +endif diff --git a/board/intercontrol/digsy_mtc/MAINTAINERS b/board/intercontrol/digsy_mtc/MAINTAINERS new file mode 100644 index 0000000000..c83ebcdab9 --- /dev/null +++ b/board/intercontrol/digsy_mtc/MAINTAINERS @@ -0,0 +1,9 @@ +DIGSY_MTC BOARD +M: Werner Pfister +S: Maintained +F: board/intercontrol/digsy_mtc/ +F: include/configs/digsy_mtc.h +F: configs/digsy_mtc_defconfig +F: configs/digsy_mtc_RAMBOOT_defconfig +F: configs/digsy_mtc_rev5_defconfig +F: configs/digsy_mtc_rev5_RAMBOOT_defconfig diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile index 877be48d61..44b7c0ae43 100644 --- a/board/intercontrol/digsy_mtc/Makefile +++ b/board/intercontrol/digsy_mtc/Makefile @@ -1,27 +1,6 @@ - # # Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o cmd_mtc.o -COBJS-$(CONFIG_VIDEO) += cmd_disp.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := digsy_mtc.o cmd_mtc.o +obj-$(CONFIG_VIDEO) += cmd_disp.o diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c index 584372521b..4ab71609c0 100644 --- a/board/intercontrol/digsy_mtc/digsy_mtc.c +++ b/board/intercontrol/digsy_mtc/digsy_mtc.c @@ -454,7 +454,7 @@ int update_flash_size (int flash_size) } #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int phy_addr = CONFIG_PHY_ADDR; char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; @@ -478,5 +478,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif /* fix up the phy address */ do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/iomega/iconnect/Kconfig b/board/iomega/iconnect/Kconfig new file mode 100644 index 0000000000..e56b029416 --- /dev/null +++ b/board/iomega/iconnect/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ICONNECT + +config SYS_BOARD + default "iconnect" + +config SYS_VENDOR + default "iomega" + +config SYS_CONFIG_NAME + default "iconnect" + +endif diff --git a/board/iomega/iconnect/MAINTAINERS b/board/iomega/iconnect/MAINTAINERS new file mode 100644 index 0000000000..167cf074b9 --- /dev/null +++ b/board/iomega/iconnect/MAINTAINERS @@ -0,0 +1,6 @@ +ICONNECT BOARD +M: Luka Perkov +S: Maintained +F: board/iomega/iconnect/ +F: include/configs/iconnect.h +F: configs/iconnect_defconfig diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile index 8809c46bb4..65e357ac95 100644 --- a/board/iomega/iconnect/Makefile +++ b/board/iomega/iconnect/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := iconnect.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := iconnect.o diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index 45ff2940ef..086a473e88 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "iconnect.h" @@ -22,9 +22,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(ICONNECT_OE_VAL_LOW, - ICONNECT_OE_VAL_HIGH, - ICONNECT_OE_LOW, ICONNECT_OE_HIGH); + mvebu_config_gpio(ICONNECT_OE_VAL_LOW, + ICONNECT_OE_VAL_HIGH, + ICONNECT_OE_LOW, ICONNECT_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -36,7 +36,7 @@ int board_early_init_f(void) MPP5_NF_IO7, MPP6_SYSRST_OUTn, /* Reset signal */ MPP7_GPO, - MPP8_TW_SDA, /* I2C */ + MPP8_TW_SDA, /* I2C */ MPP9_TW_SCK, /* I2C */ MPP10_UART0_TXD, MPP11_UART0_RXD, @@ -87,7 +87,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg index 3c63a03d3f..f4260fa504 100644 --- a/board/iomega/iconnect/kwbimage.cfg +++ b/board/iomega/iconnect/kwbimage.cfg @@ -20,7 +20,7 @@ NAND_PAGE_SIZE 0x0800 # Configure RGMII-0 interface pad voltage to 1.8V DATA 0xffd100e0 0x1b1b1b9b -#Dram initalization for SINGLE x16 CL=5 @ 400MHz +# Dram initalization for SINGLE x16 CL=5 @ 400MHz DATA 0xffd01400 0x43000c30 # DDR Configuration register # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) # bit23-14: 0x0, @@ -87,7 +87,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode # bit6-4: 0x4, CL=5 # bit7: 0x0, TestMode=0 normal # bit8: 0x0, DLL reset=0 normal -# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit11-9: 0x6, auto-precharge write recovery # bit12: 0x0, PD must be zero # bit31-13: 0x0, required diff --git a/board/ip04/Kconfig b/board/ip04/Kconfig new file mode 100644 index 0000000000..670bf89922 --- /dev/null +++ b/board/ip04/Kconfig @@ -0,0 +1,9 @@ +if TARGET_IP04 + +config SYS_BOARD + default "ip04" + +config SYS_CONFIG_NAME + default "ip04" + +endif diff --git a/board/ip04/MAINTAINERS b/board/ip04/MAINTAINERS new file mode 100644 index 0000000000..c37b0110f2 --- /dev/null +++ b/board/ip04/MAINTAINERS @@ -0,0 +1,6 @@ +IP04 BOARD +#M: Brent Kandetzki +S: Orphan (since 2014-06) +F: board/ip04/ +F: include/configs/ip04.h +F: configs/ip04_defconfig diff --git a/board/ip04/Makefile b/board/ip04/Makefile index 1d23b23f49..caba16f199 100644 --- a/board/ip04/Makefile +++ b/board/ip04/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ip04.o diff --git a/board/ip04/config.mk b/board/ip04/config.mk index ae2ea0b747..ab0fbecab9 100644 --- a/board/ip04/config.mk +++ b/board/ip04/config.mk @@ -7,10 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c index c8ae5128b0..ae52633426 100644 --- a/board/ip04/ip04.c +++ b/board/ip04/ip04.c @@ -13,7 +13,6 @@ #include #include #include -#include int checkboard(void) { @@ -33,7 +32,7 @@ int misc_init_r(void) uchar enetaddr[6]; if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(enetaddr); + eth_random_addr(enetaddr); eth_setenv_enetaddr("ethaddr", enetaddr); } diff --git a/board/ip860/Makefile b/board/ip860/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/ip860/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ip860/flash.c b/board/ip860/flash.c deleted file mode 100644 index 542b0c8086..0000000000 --- a/board/ip860/flash.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - bcsr->bd_ctrl |= BD_CTRL_FLWE; - - for (i=0; imemc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br1 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* all possible flash types - * (28F016SV, 28F160S3, 28F320S3) - * have the same erase block size: 64 kB per chip, - * of 128 kB per bank - */ - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - - value = addr[0]; - switch (value) { - case (MT_MANUFACT & 0x00FF00FF): /* MT or => Intel */ - case (INTEL_ALT_MANU & 0x00FF00FF): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 2x4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - - *addr = 0xFFFFFF; /* reset bank to read array mode */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Single Block Erase Command */ - *addr = 0x20202020; - /* Confirm */ - *addr = 0xD0D0D0D0; - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while ((*addr & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - } - } - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x00400040) { -printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - - return (flag); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c deleted file mode 100644 index 4e3b1b5a84..0000000000 --- a/board/ip860/ip860.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -unsigned long ip860_get_dram_size(void); -unsigned long ip860_get_clk_freq (void); -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -/* ------------------------------------------------------------------------- */ -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - -/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */ - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * Test ID string (IP860...) - */ - -int checkboard (void) -{ - unsigned char *s, *e; - unsigned char buf[64]; - int i; - - puts ("Board: "); - - i = getenv_f("serial#", (char *)buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (!s || strncmp ((char *)s, "IP860", 5)) { - puts ("### No HW ID - assuming IP860"); - } else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - - for (; s < e; ++s) { - putc (*s); - } - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - ulong refresh_val; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh - */ - if (ip860_get_clk_freq() == 50000000) - { - memctl->memc_mptpr = 0x0400; - refresh_val = 0xC3000000; - } - else - { - memctl->memc_mptpr = 0x0200; - refresh_val = 0x9C000000; - } - - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 to the SDRAM address - */ - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - - /* IP860 boards have only one bank SDRAM */ - - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mamr = 0x00804114 | refresh_val; - memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */ - udelay(1); - memctl->memc_mamr = 0x00804118 | refresh_val; - memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */ - - - udelay (1000); - - /* - * Check SDRAM Memory Size - */ - if (ip860_get_dram_size() == 16) - size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE); - else - size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE); - - udelay (1000); - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - /* - * Also, map other memory to correct position - */ - -#if (defined(CONFIG_SYS_OR1) && defined(CONFIG_SYS_BR1_PRELIM)) - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; -#endif - -#if defined(CONFIG_SYS_OR3) && defined(CONFIG_SYS_BR3) - memctl->memc_or3 = CONFIG_SYS_OR3; - memctl->memc_br3 = CONFIG_SYS_BR3; -#endif - -#if defined(CONFIG_SYS_OR4) && defined(CONFIG_SYS_BR4) - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; -#endif - -#if defined(CONFIG_SYS_OR5) && defined(CONFIG_SYS_BR5) - memctl->memc_or5 = CONFIG_SYS_OR5; - memctl->memc_br5 = CONFIG_SYS_BR5; -#endif - -#if defined(CONFIG_SYS_OR6) && defined(CONFIG_SYS_BR6) - memctl->memc_or6 = CONFIG_SYS_OR6; - memctl->memc_br6 = CONFIG_SYS_BR6; -#endif - -#if defined(CONFIG_SYS_OR7) && defined(CONFIG_SYS_BR7) - memctl->memc_or7 = CONFIG_SYS_OR7; - memctl->memc_br7 = CONFIG_SYS_BR7; -#endif - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -void reset_phy (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - ulong mask = PB_ENET_RESET | PB_ENET_JABD; - ulong reg; - - /* Make sure PHY is not in low-power mode */ - immr->im_cpm.cp_pbpar &= ~(mask); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(mask); /* active output */ - - /* Set JABD low (no JABber Disable), - * and RESET high (Reset PHY) - */ - reg = immr->im_cpm.cp_pbdat; - reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET; - immr->im_cpm.cp_pbdat = reg; - - /* now drive outputs */ - immr->im_cpm.cp_pbdir |= mask; /* output */ - udelay (1000); - /* - * Release RESET signal - */ - immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET); - udelay (1000); -} - -/* ------------------------------------------------------------------------- */ - -unsigned long ip860_get_clk_freq(void) -{ - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; - ulong temp; - uchar sysclk; - - if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */ - sysclk = (bcsr->bd_rev & 0x18) >> 3; - else - sysclk = 0x00; - - switch (sysclk) - { - case 0x00: - temp = 50000000; - break; - - case 0x01: - temp = 80000000; - break; - - default: - temp = 50000000; - break; - } - - return (temp); - -} - - -/* ------------------------------------------------------------------------- */ - -unsigned long ip860_get_dram_size(void) -{ - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; - ulong temp; - uchar dram_size; - - if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */ - dram_size = (bcsr->bd_rev & 0xE0) >> 5; - else - dram_size = 0x00; /* default is 16 MB */ - - switch (dram_size) - { - case 0x00: - temp = 16; - break; - - case 0x01: - temp = 32; - break; - - default: - temp = 16; - break; - } - - return (temp); - -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/ip860/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug deleted file mode 100644 index e561bb4824..0000000000 --- a/board/ip860/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - arch/powerpc/cpu/mpc8xx/interrupts.o (.text) - arch/powerpc/lib/time.o (.text) - arch/powerpc/lib/ticks.o (.text) -/** - . = env_offset; - common/env_embedded.o(.text) -**/ - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ipek01/Kconfig b/board/ipek01/Kconfig new file mode 100644 index 0000000000..34e094d79d --- /dev/null +++ b/board/ipek01/Kconfig @@ -0,0 +1,9 @@ +if TARGET_IPEK01 + +config SYS_BOARD + default "ipek01" + +config SYS_CONFIG_NAME + default "ipek01" + +endif diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS new file mode 100644 index 0000000000..060f8a5a22 --- /dev/null +++ b/board/ipek01/MAINTAINERS @@ -0,0 +1,6 @@ +IPEK01 BOARD +M: Wolfgang Grandegger +S: Maintained +F: board/ipek01/ +F: include/configs/ipek01.h +F: configs/ipek01_defconfig diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile index 3acd06bba7..a786ab2118 100644 --- a/board/ipek01/Makefile +++ b/board/ipek01/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ipek01.o diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c index d44c4bf669..2078f53769 100644 --- a/board/ipek01/ipek01.c +++ b/board/ipek01/ipek01.c @@ -196,10 +196,12 @@ void pci_init_board (void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup (void *blob, bd_t * bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/iphase4539/Makefile b/board/iphase4539/Makefile deleted file mode 100644 index 52c03198a7..0000000000 --- a/board/iphase4539/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 Wolfgang Grandegger -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/iphase4539/README b/board/iphase4539/README deleted file mode 100644 index c5146d9b18..0000000000 --- a/board/iphase4539/README +++ /dev/null @@ -1,358 +0,0 @@ - -This file contains basic information on the port of U-Boot to IPHASE4539 -(Interphase 4539 T1/E1/J1 PMC Communications Controller). -All the changes fit in the common U-Boot infrastructure, providing a new -IPHASE4539-specific entry in makefiles. To build U-Boot for IPHASE4539, -type "make IPHASE4539_config", edit the "include/config_IPHASE4539.h" -file if necessary, then type "make". - - -Common file modifications: --------------------------- - -The following common files have been modified by this project: -(starting from the ppcboot-1.1.5/ directory) - -MAKEALL - IPHASE4539 entry added -Makefile - IPHASE4539_config entry added - - -New files: ----------- - -The following new files have been added by this project: -(starting from the ppcboot-1.1.5/ directory) - -board/iphase4539/ - board-specific directory -board/iphase4539/Makefile - board-specific makefile -board/iphase4539/config.mk - config file -board/iphase4539/flash.c - flash driver (for AM29LV033C) -board/iphase4539/ppcboot.lds - linker script -board/iphase4539/iphase4539.c - ioport and memory initialization -include/config_IPHASE4539.h - main configuration file - - -New configuration options: --------------------------- - -CONFIG_IPHASE4539 - - Main board-specific option (should be defined for IPHASE4539). - - -Acceptance criteria tests: --------------------------- - -The following tests have been conducted to validate the port of U-Boot -to IPHASE4539: - -1. Operation on serial console: - -With SMC1 defined as console in the main configuration file, the U-Boot -output appeared on the serial terminal connected to the 2.5mm stereo jack -connector as follows: - ------------------------------------------------------------------------------- -=> help -base - print or set address offset -bdinfo - print Board Info structure -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -cmp - memory compare -coninfo - print console devices and informations -cp - memory copy -crc32 - checksum calculation -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -icache - enable or disable instruction cache -iminfo - print header information for application image -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loop - infinite loop on address range -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sleep - delay execution for some time -source - run script from memory -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -version - print monitor version -? - alias for 'help' -=> ------------------------------------------------------------------------------- - - -2. Flash driver operation - -The following sequence was performed to test the "flinfo" command: - ------------------------------------------------------------------------------- -=> flinfo - -Bank # 1: AMD AM29LV033C (32 Mbit, uniform sectors) - Size: 4 MB in 64 Sectors - Sector Start Addresses: - FF800000 (RO) FF810000 (RO) FF820000 FF830000 FF840000 - FF850000 FF860000 FF870000 FF880000 FF890000 - FF8A0000 FF8B0000 FF8C0000 FF8D0000 FF8E0000 - FF8F0000 FF900000 FF910000 FF920000 FF930000 - FF940000 FF950000 FF960000 FF970000 FF980000 - FF990000 FF9A0000 FF9B0000 FF9C0000 FF9D0000 - FF9E0000 FF9F0000 FFA00000 FFA10000 FFA20000 - FFA30000 FFA40000 FFA50000 FFA60000 FFA70000 - FFA80000 FFA90000 FFAA0000 FFAB0000 FFAC0000 - FFAD0000 FFAE0000 FFAF0000 FFB00000 (RO) FFB10000 (RO) - FFB20000 (RO) FFB30000 (RO) FFB40000 FFB50000 FFB60000 - FFB70000 FFB80000 FFB90000 FFBA0000 FFBB0000 - FFBC0000 FFBD0000 FFBE0000 FFBF0000 ------------------------------------------------------------------------------- - -Note: the Hardware Configuration Word (HWC) of the 8260 is on the -first sector of the flash and should not be touched. The U-Boot -environment variables are stored on second sector and U-Boot -starts at the address 0xFFB00000. - - -The following sequence was performed to test the erase command: - ------------------------------------------------------------------------------- -=> cp 0 ff880000 10 -Copy to Flash... done -=> md ff880000 20 -ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x -ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x -ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. -ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x -ff880040: ffffffff ffffffff ffffffff ffffffff ................ -ff880050: ffffffff ffffffff ffffffff ffffffff ................ -ff880060: ffffffff ffffffff ffffffff ffffffff ................ -ff880070: ffffffff ffffffff ffffffff ffffffff ................ -=> erase ff880000 ff88ffff -Erase Flash from 0xff880000 to 0xff88ffff -.. done -Erased 1 sectors -=> md ff880000 -ff880000: ffffffff ffffffff ffffffff ffffffff ................ -ff880010: ffffffff ffffffff ffffffff ffffffff ................ -ff880020: ffffffff ffffffff ffffffff ffffffff ................ -ff880030: ffffffff ffffffff ffffffff ffffffff ................ -ff880040: ffffffff ffffffff ffffffff ffffffff ................ -ff880050: ffffffff ffffffff ffffffff ffffffff ................ -ff880060: ffffffff ffffffff ffffffff ffffffff ................ -ff880070: ffffffff ffffffff ffffffff ffffffff ................ -=> cp 0 ff880000 10 -Copy to Flash... done -=> md ff880000 20 -ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x -ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x -ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. -ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x -ff880040: ffffffff ffffffff ffffffff ffffffff ................ -ff880050: ffffffff ffffffff ffffffff ffffffff ................ -ff880060: ffffffff ffffffff ffffffff ffffffff ................ -ff880070: ffffffff ffffffff ffffffff ffffffff ................ -=> erase 1:8 -Erase Flash Sectors 8-8 in Bank # 1 -.. done -=> md ff880000 20 -ff880000: ffffffff ffffffff ffffffff ffffffff ................ -ff880010: ffffffff ffffffff ffffffff ffffffff ................ -ff880020: ffffffff ffffffff ffffffff ffffffff ................ -ff880030: ffffffff ffffffff ffffffff ffffffff ................ -ff880040: ffffffff ffffffff ffffffff ffffffff ................ -ff880050: ffffffff ffffffff ffffffff ffffffff ................ -ff880060: ffffffff ffffffff ffffffff ffffffff ................ -ff880070: ffffffff ffffffff ffffffff ffffffff ................ -=> cp 0 ff880000 10 -Copy to Flash... done -=> cp 0 ff890000 10 -=> md ff880000 20 -ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x -ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x -ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. -ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x -ff880040: ffffffff ffffffff ffffffff ffffffff ................ -ff880050: ffffffff ffffffff ffffffff ffffffff ................ -ff880060: ffffffff ffffffff ffffffff ffffffff ................ -ff880070: ffffffff ffffffff ffffffff ffffffff ................ -=> md ff890000 -ff890000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x -ff890010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x -ff890020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. -ff890030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x -ff890040: ffffffff ffffffff ffffffff ffffffff ................ -ff890050: ffffffff ffffffff ffffffff ffffffff ................ -ff890060: ffffffff ffffffff ffffffff ffffffff ................ -ff890070: ffffffff ffffffff ffffffff ffffffff ................ -=> erase 1:8-9 -Erase Flash Sectors 8-9 in Bank # 1 -.... done -=> md ff880000 20 -ff880000: ffffffff ffffffff ffffffff ffffffff ................ -ff880010: ffffffff ffffffff ffffffff ffffffff ................ -ff880020: ffffffff ffffffff ffffffff ffffffff ................ -ff880030: ffffffff ffffffff ffffffff ffffffff ................ -ff880040: ffffffff ffffffff ffffffff ffffffff ................ -ff880050: ffffffff ffffffff ffffffff ffffffff ................ -ff880060: ffffffff ffffffff ffffffff ffffffff ................ -ff880070: ffffffff ffffffff ffffffff ffffffff ................ -=> md ff890000 -ff890000: ffffffff ffffffff ffffffff ffffffff ................ -ff890010: ffffffff ffffffff ffffffff ffffffff ................ -ff890020: ffffffff ffffffff ffffffff ffffffff ................ -ff890030: ffffffff ffffffff ffffffff ffffffff ................ -ff890040: ffffffff ffffffff ffffffff ffffffff ................ -ff890050: ffffffff ffffffff ffffffff ffffffff ................ -ff890060: ffffffff ffffffff ffffffff ffffffff ................ -ff890070: ffffffff ffffffff ffffffff ffffffff ................ -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test the Flash programming commands: - ------------------------------------------------------------------------------- -=> erase ff880000 ff88ffff -Erase Flash from 0xff880000 to 0xff88ffff -.. done -Erased 1 sectors -=> cp 0 ff880000 10 -Copy to Flash... done -=> md 0 20 -00000000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x -00000010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x -00000020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. -00000030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x -00000040: 3c83c000 2c040000 40823378 7c0000a6 <...,...@.3x|... -00000050: 60000030 7c1b03a6 3c00c000 600035ec `..0|...<...`.5. -00000060: 7c1a03a6 4c000064 00000000 00000000 |...L..d........ -00000070: 00000000 00000000 00000000 00000000 ................ -=> md ff880000 20 -ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x -ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x -ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. -ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x -ff880040: ffffffff ffffffff ffffffff ffffffff ................ -ff880050: ffffffff ffffffff ffffffff ffffffff ................ -ff880060: ffffffff ffffffff ffffffff ffffffff ................ -ff880070: ffffffff ffffffff ffffffff ffffffff ................ -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test storage of the environment -variables in Flash: - ------------------------------------------------------------------------------- -=> setenv foo bar -=> saveenv -Un-Protected 1 sectors -Erasing Flash... -.. done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=> reset -... -=> printenv -... -foo=bar -... -Environment size: 339/65532 bytes -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test image download and run over -Ethernet interface (both interfaces were tested): - ------------------------------------------------------------------------------- -=> tftpboot 40000 hello_world.bin -ARP broadcast 1 -TFTP from server 10.0.0.1; our IP address is 10.0.0.8 -Filename 'hello_world.bin'. -Load address: 0x40000 -Loading: ############# -done -Bytes transferred = 65932 (1018c hex) -=> go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> ------------------------------------------------------------------------------- - - -3. Known Problems - -None for the moment. - - ----------------------------------------------------------------------------- -U-Boot and Linux for Interphase 4539 T1/E1/J1 PMC Communications Controller ----------------------------------------------------------------------------- - -U-Boot: - - Configure and make U-Boot: - - $ cd /u-boot - $ make IPHASE4539_config - $ make dep - $ make - $ cp -p u-boot.bin /tftpboot - - Load u-boot.bin into the Flash memory at 0xffb00000. - - -Linux: - - Configure and make Linux: - - $ cd /linux-2.4 - $ make IPHASE4539_config - $ make oldconfig - $ make dep - $ make uImage - $ cp -p arch/powerpc/mbxboot/uImage /tftpboot - - Load uImage via tftp and boot it. - - -Flash organisation: - - The following preliminary layout of the Flash memory - is defined: - - 0xff800000 ( 0 - 64 kB): Hardware Configuration Word. - 0xff810000 ( 64 kB - 128 kB): U-Boot Environment. - 0xff820000 ( 128 kB - 3 MB): RAMdisk. - 0xffb00000 ( 3 MB - 3328 kB): U-Boot. - 0xffb40000 (3328 KB - 4 MB): Linux Kernel. - - -For further information concerning U-Boot and Linux please consult -the "DENX U-Boot and Linux Guide". - - -(C) 2002 Wolfgang Grandegger, DENX Software Engineering, wg@denx.de -=================================================================== diff --git a/board/iphase4539/flash.c b/board/iphase4539/flash.c deleted file mode 100644 index d3122edf21..0000000000 --- a/board/iphase4539/flash.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Adapted for Interphase 4539 by Wolfgang Grandegger . - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -extern int hwc_flash_size(void); -static ulong flash_get_size (u32 addr, flash_info_t *info); -static int flash_get_offsets (u32 base, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_reset (u32 addr); - -#define out8(a,v) *(volatile unsigned char*)(a) = v -#define in8(a) *(volatile unsigned char*)(a) -#define in32(a) *(volatile unsigned long*)(a) -#define iobarrier_rw() eieio() - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long flash_size = 0; - unsigned long bank_size; - unsigned int bank = 0; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = 0; - flash_info[i].size = 0; - } - - /* Initialise the BOOT Flash */ - if (bank == CONFIG_SYS_MAX_FLASH_BANKS) { - puts ("Warning: not all Flashes are initialised !"); - return flash_size; - } - - bank_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info + bank); - if (bank_size) { -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MAX_FLASH_SIZE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - flash_info + bank); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - flash_info + bank); -#endif - - /* HWC protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x10000 - 1, - flash_info + bank); - - flash_size += bank_size; - bank++; - } else { - puts ("Warning: the BOOT Flash is not initialised !"); - } - - return flash_size; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (u32 addr, flash_info_t *info) -{ - volatile uchar value; -#if 0 - int i; -#endif - - /* Write auto select command: read Manufacturer ID */ - out8(addr + 0x0555, 0xAA); - iobarrier_rw(); - udelay(10); - out8(addr + 0x02AA, 0x55); - iobarrier_rw(); - udelay(10); - out8(addr + 0x0555, 0x90); - iobarrier_rw(); - udelay(10); - - value = in8(addr); - iobarrier_rw(); - udelay(10); - switch (value | (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - return 0; - } - - value = in8(addr + 1); /* device ID */ - iobarrier_rw(); - - switch (value) { - case AMD_ID_LV033C: - info->flash_id += FLASH_AM033C; - info->size = hwc_flash_size(); - if (info->size > CONFIG_SYS_MAX_FLASH_SIZE) { - printf("U-Boot supports only %d MB\n", - CONFIG_SYS_MAX_FLASH_SIZE); - info->size = CONFIG_SYS_MAX_FLASH_SIZE; - } - info->sector_count = info->size / 0x10000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - return (0); /* => no or unknown flash */ - - } - - if (!flash_get_offsets (addr, info)) { - flash_reset (addr); - return 0; - } - -#if 0 - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - value = in8(info->start[i] + 2); - iobarrier_rw(); - info->protect[i] = (value & 1) != 0; - } -#endif - - /* - * Reset bank to read mode - */ - flash_reset (addr); - - return (info->size); -} - -static int flash_get_offsets (u32 base, flash_info_t *info) -{ - unsigned int i, size; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM033C: - /* set sector offsets for uniform sector type */ - size = info->size / info->sector_count; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * size; - } - break; - default: - return 0; - } - - return 1; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile u32 addr = info->start[0]; - int flag, prot, sect, l_sect; - ulong start, now, last; - - if (s_first < 0 || s_first > s_last) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN || - info->flash_id > FLASH_AMD_COMP) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x80); - iobarrier_rw(); - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = info->start[sect]; - out8(addr, 0x30); - iobarrier_rw(); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = info->start[l_sect]; - while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - iobarrier_rw(); - } - -DONE: - /* reset to read mode */ - flash_reset (info->start[0]); - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile u32 addr = info->start[0]; - ulong start; - int flag, i; - - /* Check if Flash is (sufficiently) erased */ - if ((in32(dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* first, perform an unlock bypass command to speed up flash writes */ - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x20); - iobarrier_rw(); - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - out8(addr, 0xA0); - iobarrier_rw(); - out8(dest+i, data_ch[i]); - iobarrier_rw(); - udelay(10); /* XXX */ - } - - /* we're done, now do an unlock bypass reset */ - out8(addr, 0x90); - iobarrier_rw(); - out8(addr, 0x00); - iobarrier_rw(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((in32(dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - iobarrier_rw(); - } - - flash_reset (addr); - - return (0); -} - -/* - * Reset bank to read mode - */ -static void flash_reset (u32 addr) -{ - out8(addr, 0xF0); /* reset bank */ - iobarrier_rw(); -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM033C: printf ("AM29LV033C (32 Mbit, uniform sectors)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size % 0x100000 == 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size / 0x100000, info->sector_count); - } - else if (info->size % 0x400 == 0) { - printf (" Size: %ld KB in %d Sectors\n", - info->size / 0x400, info->sector_count); - } - else { - printf (" Size: %ld B in %d Sectors\n", - info->size, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c deleted file mode 100644 index d40d2b661d..0000000000 --- a/board/iphase4539/iphase4539.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -int hwc_flash_size (void); -int hwc_local_sdram_size (void); -int hwc_main_sdram_size (void); -int hwc_serial_number (void); -int hwc_mac_address (char *str); -int hwc_manufact_date (char *str); -int seeprom_read (int addr, uchar * data, int size); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - * - * The port definitions are taken from the old firmware (see - * also SYS/H/4539.H): - * - * ppar psor pdir podr pdat - * PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0 - * PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290 - * PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d - * PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9 - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - {0, 1, 0, 0, 0, 0}, /* PA31 FCC1_TXENB SLAVE */ - {0, 1, 0, 1, 0, 0}, /* PA30 FCC1_TXCLAV SLAVE */ - {0, 1, 0, 1, 0, 0}, /* PA29 FCC1_TXSOC */ - {0, 1, 0, 0, 0, 0}, /* PA28 FCC1_RXENB SLAVE */ - {0, 1, 0, 0, 0, 0}, /* PA27 FCC1_RXSOC */ - {0, 1, 0, 1, 0, 0}, /* PA26 FCC1_RXCLAV SLAVE */ - {0, 1, 0, 1, 0, 1}, /* PA25 FCC1_TXD0 */ - {0, 1, 0, 1, 0, 1}, /* PA24 FCC1_TXD1 */ - {0, 1, 0, 1, 0, 1}, /* PA23 FCC1_TXD2 */ - {0, 1, 0, 1, 0, 1}, /* PA22 FCC1_TXD3 */ - {0, 1, 0, 1, 0, 1}, /* PA21 FCC1_TXD4 */ - {0, 1, 0, 1, 0, 1}, /* PA20 FCC1_TXD5 */ - {0, 1, 0, 1, 0, 1}, /* PA19 FCC1_TXD6 */ - {0, 1, 0, 1, 0, 1}, /* PA18 FCC1_TXD7 */ - {0, 1, 0, 0, 0, 0}, /* PA17 FCC1_RXD7 */ - {0, 1, 0, 0, 0, 0}, /* PA16 FCC1_RXD6 */ - {0, 1, 0, 0, 0, 0}, /* PA15 FCC1_RXD5 */ - {0, 1, 0, 0, 0, 0}, /* PA14 FCC1_RXD4 */ - {0, 1, 0, 0, 0, 0}, /* PA13 FCC1_RXD3 */ - {0, 1, 0, 0, 0, 0}, /* PA12 FCC1_RXD2 */ - {0, 1, 0, 0, 0, 0}, /* PA11 FCC1_RXD1 */ - {0, 1, 0, 0, 0, 0}, /* PA10 FCC1_RXD0 */ - {0, 1, 1, 1, 0, 1}, /* PA9 TDMA1_L1TXD */ - {0, 1, 1, 0, 0, 0}, /* PA8 TDMA1_L1RXD */ - {0, 0, 0, 0, 0, 0}, /* PA7 CONFIG0 */ - {0, 1, 1, 0, 0, 1}, /* PA6 TDMA1_L1RSYNC */ - {0, 0, 0, 1, 0, 0}, /* PA5 FCC2:RxAddr[2] */ - {0, 0, 0, 1, 0, 0}, /* PA4 FCC2:RxAddr[1] */ - {0, 0, 0, 1, 0, 0}, /* PA3 FCC2:RxAddr[0] */ - {0, 0, 0, 1, 0, 0}, /* PA2 FCC2:TxAddr[0] */ - {0, 0, 0, 1, 0, 0}, /* PA1 FCC2:TxAddr[1] */ - {0, 0, 0, 1, 0, 0} /* PA0 FCC2:TxAddr[2] */ - }, - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - {0, 0, 0, 1, 0, 0}, /* PB31 FCC2_RXSOC */ - {0, 0, 0, 1, 0, 0}, /* PB30 FCC2_TXSOC */ - {0, 0, 0, 1, 0, 0}, /* PB29 FCC2_RXCLAV */ - {0, 0, 0, 0, 0, 0}, /* PB28 CONFIG2 */ - {0, 1, 1, 0, 0, 1}, /* PB27 FCC2_TXD0 */ - {0, 1, 1, 0, 0, 0}, /* PB26 FCC2_TXD1 */ - {0, 0, 0, 1, 0, 0}, /* PB25 FCC2_TXD4 */ - {0, 1, 1, 0, 0, 1}, /* PB24 FCC2_TXD5 */ - {0, 0, 0, 1, 0, 0}, /* PB23 FCC2_TXD6 */ - {0, 1, 0, 1, 0, 1}, /* PB22 FCC2_TXD7 */ - {0, 1, 0, 0, 0, 0}, /* PB21 FCC2_RXD7 */ - {0, 1, 0, 0, 0, 0}, /* PB20 FCC2_RXD6 */ - {0, 1, 0, 0, 0, 0}, /* PB19 FCC2_RXD5 */ - {0, 0, 0, 1, 0, 0}, /* PB18 FCC2_RXD4 */ - {1, 1, 0, 0, 0, 0}, /* PB17 FCC3_RX_DV */ - {1, 1, 0, 0, 0, 0}, /* PB16 FCC3_RX_ER */ - {1, 1, 0, 1, 0, 0}, /* PB15 FCC3_TX_ER */ - {1, 1, 0, 1, 0, 0}, /* PB14 FCC3_TX_EN */ - {1, 1, 0, 0, 0, 0}, /* PB13 FCC3_COL */ - {1, 1, 0, 0, 0, 0}, /* PB12 FCC3_CRS */ - {1, 1, 0, 0, 0, 0}, /* PB11 FCC3_RXD3 */ - {1, 1, 0, 0, 0, 0}, /* PB10 FCC3_RXD2 */ - {1, 1, 0, 0, 0, 0}, /* PB9 FCC3_RXD1 */ - {1, 1, 0, 0, 0, 0}, /* PB8 FCC3_RXD0 */ - {1, 1, 0, 1, 0, 1}, /* PB7 FCC3_TXD0 */ - {1, 1, 0, 1, 0, 1}, /* PB6 FCC3_TXD1 */ - {1, 1, 0, 1, 0, 1}, /* PB5 FCC3_TXD2 */ - {1, 1, 0, 1, 0, 1}, /* PB4 FCC3_TXD3 */ - {0, 0, 0, 0, 0, 0}, /* PB3 */ - {0, 0, 0, 0, 0, 0}, /* PB2 */ - {0, 0, 0, 0, 0, 0}, /* PB1 */ - {0, 0, 0, 0, 0, 0}, /* PB0 */ - }, - /* Port C configuration */ - { /* conf ppar psor pdir podr pdat */ - {0, 1, 0, 0, 0, 1}, /* PC31 CLK1 */ - {0, 0, 0, 1, 0, 0}, /* PC30 U1MASTER_N */ - {0, 1, 0, 0, 0, 1}, /* PC29 CLK3 */ - {0, 0, 0, 1, 0, 1}, /* PC28 -MT90220_RST */ - {0, 1, 0, 0, 0, 1}, /* PC27 CLK5 */ - {0, 0, 0, 1, 0, 1}, /* PC26 -QUADFALC_RST */ - {0, 1, 1, 1, 0, 1}, /* PC25 BRG4 */ - {1, 0, 0, 1, 0, 0}, /* PC24 MDIO */ - {1, 0, 0, 1, 0, 0}, /* PC23 MDC */ - {0, 1, 0, 0, 0, 1}, /* PC22 CLK10 */ - {0, 0, 0, 1, 0, 0}, /* PC21 */ - {0, 1, 0, 0, 0, 1}, /* PC20 CLK12 */ - {0, 1, 0, 0, 0, 1}, /* PC19 CLK13 */ - {1, 1, 0, 0, 0, 1}, /* PC18 CLK14 */ - {0, 1, 0, 0, 0, 0}, /* PC17 CLK15 */ - {1, 1, 0, 0, 0, 1}, /* PC16 CLK16 */ - {0, 1, 1, 0, 0, 0}, /* PC15 FCC1_TXADDR0 SLAVE */ - {0, 1, 1, 0, 0, 0}, /* PC14 FCC1_RXADDR0 SLAVE */ - {0, 1, 1, 0, 0, 0}, /* PC13 FCC1_TXADDR1 SLAVE */ - {0, 1, 1, 0, 0, 0}, /* PC12 FCC1_RXADDR1 SLAVE */ - {0, 0, 0, 1, 0, 0}, /* PC11 FCC2_RXD2 */ - {0, 0, 0, 1, 0, 0}, /* PC10 FCC2_RXD3 */ - {0, 0, 0, 1, 0, 1}, /* PC9 LTMODE */ - {0, 0, 0, 1, 0, 1}, /* PC8 SELSYNC */ - {0, 1, 1, 0, 0, 0}, /* PC7 FCC1_TXADDR2 SLAVE */ - {0, 1, 1, 0, 0, 0}, /* PC6 FCC1_RXADDR2 SLAVE */ - {0, 0, 0, 1, 0, 0}, /* PC5 FCC2_TXCLAV MASTER */ - {0, 0, 0, 1, 0, 0}, /* PC4 FCC2_RXENB MASTER */ - {0, 0, 0, 1, 0, 0}, /* PC3 FCC2_TXD2 */ - {0, 0, 0, 1, 0, 0}, /* PC2 FCC2_TXD3 */ - {0, 0, 0, 0, 0, 1}, /* PC1 PTMC -PTEENB */ - {0, 0, 0, 1, 0, 1}, /* PC0 COMCLK_N */ - }, - /* Port D configuration */ - { /* conf ppar psor pdir podr pdat */ - {0, 0, 0, 1, 0, 1}, /* PD31 -CAM_RST */ - {0, 0, 0, 1, 0, 0}, /* PD30 FCC2_TXENB */ - {0, 1, 1, 0, 0, 0}, /* PD29 FCC1_RXADDR3 SLAVE */ - {0, 1, 1, 0, 0, 1}, /* PD28 TDMC1_L1TXD */ - {0, 1, 1, 0, 0, 0}, /* PD27 TDMC1_L1RXD */ - {0, 1, 1, 0, 0, 1}, /* PD26 TDMC1_L1RSYNC */ - {0, 0, 0, 1, 0, 1}, /* PD25 LED0 -OFF */ - {0, 0, 0, 1, 0, 1}, /* PD24 LED5 -OFF */ - {1, 0, 0, 1, 0, 1}, /* PD23 -LXT971_RST */ - {0, 1, 1, 0, 0, 1}, /* PD22 TDMA2_L1TXD */ - {0, 1, 1, 0, 0, 0}, /* PD21 TDMA2_L1RXD */ - {0, 1, 1, 0, 0, 1}, /* PD20 TDMA2_L1RSYNC */ - {0, 0, 0, 1, 0, 0}, /* PD19 FCC2_TXADDR3 */ - {0, 0, 0, 1, 0, 0}, /* PD18 FCC2_RXADDR3 */ - {0, 1, 0, 1, 0, 0}, /* PD17 BRG2 */ - {0, 0, 0, 1, 0, 0}, /* PD16 */ - {0, 0, 0, 1, 0, 0}, /* PD15 PT2TO1 */ - {0, 0, 0, 1, 0, 1}, /* PD14 PT4TO3 */ - {0, 0, 0, 1, 0, 1}, /* PD13 -SWMODE */ - {0, 0, 0, 1, 0, 1}, /* PD12 -PTMODE */ - {0, 0, 0, 1, 0, 0}, /* PD11 FCC2_RXD0 */ - {0, 0, 0, 1, 0, 0}, /* PD10 FCC2_RXD1 */ - {1, 1, 0, 1, 0, 1}, /* PD9 SMC1_SMTXD */ - {1, 1, 0, 0, 0, 1}, /* PD8 SMC1_SMRXD */ - {0, 1, 1, 0, 0, 0}, /* PD7 FCC1_TXADDR3 SLAVE */ - {0, 0, 0, 1, 0, 0}, /* PD6 IMAMODE */ - {0, 0, 0, 0, 0, 0}, /* PD5 CONFIG2 */ - {0, 1, 0, 1, 0, 0}, /* PD4 BRG8 */ - {0, 0, 0, 0, 0, 0}, /* PD3 */ - {0, 0, 0, 0, 0, 0}, /* PD2 */ - {0, 0, 0, 0, 0, 0}, /* PD1 */ - {0, 0, 0, 0, 0, 0}, /* PD0 */ - } -}; - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *base; - ulong maxsize; - int i; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - immap->im_siu_conf.sc_ppc_acr = 0x00000026; - immap->im_siu_conf.sc_ppc_alrh = 0x01276345; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x00000000; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - immap->im_siu_conf.sc_ltescr1 = 0x00004000; - - /* Init Main SDRAM */ -#define OP_VALUE 0x404A241A -#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF); - base = (uchar *) CONFIG_SYS_SDRAM_BASE; - memctl->memc_psdmr = 0x28000000 | OP_VALUE_M; - *base = 0xFF; - memctl->memc_psdmr = 0x08000000 | OP_VALUE_M; - for (i = 0; i < 8; i++) - *base = 0xFF; - memctl->memc_psdmr = 0x18000000 | OP_VALUE_M; - *(base + 0x110) = 0xFF; - memctl->memc_psdmr = OP_VALUE; - memctl->memc_lsdmr = 0x4086A522; - *base = 0xFF; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2; - - maxsize = get_ram_size((long *)base, maxsize); - - memctl->memc_or1 |= ~(maxsize - 1); - - if (maxsize != hwc_main_sdram_size ()) - printf ("Oops: memory test has not found all memory!\n"); -#endif - - icache_enable (); - /* return total ram size of SDRAM */ - return (maxsize); -} - -int checkboard (void) -{ - char string[32]; - - hwc_manufact_date (string); - - printf ("Board: Interphase 4539 (#%d %s)\n", - hwc_serial_number (), - string); - -#ifdef DEBUG - printf ("Manufacturing date: %s\n", string); - printf ("Serial number : %d\n", hwc_serial_number ()); - printf ("FLASH size : %d MB\n", hwc_flash_size () >> 20); - printf ("Main SDRAM size : %d MB\n", hwc_main_sdram_size () >> 20); - printf ("Local SDRAM size : %d MB\n", hwc_local_sdram_size () >> 20); - hwc_mac_address (string); - printf ("MAC address : %s\n", string); -#endif - - return 0; -} - -int misc_init_r (void) -{ - char *s, str[32]; - int num; - - if ((s = getenv ("serial#")) == NULL && - (num = hwc_serial_number ()) != -1) { - sprintf (str, "%06d", num); - setenv ("serial#", str); - } - if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) { - setenv ("ethaddr", str); - } - return (0); -} - -/*************************************************************** - * We take some basic Hardware Configuration Parameter from the - * Serial EEPROM conected to the PSpan bridge. We keep it as - * simple as possible. - */ -int hwc_flash_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte >> 2) & 0x3) { - case 0x1: - return 0x0400000; - break; - case 0x2: - return 0x0800000; - break; - case 0x3: - return 0x1000000; - default: - return 0x0100000; - } - } - return -1; -} -int hwc_local_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte & 0x03)) { - case 0x1: - return 0x0800000; - case 0x2: - return 0x1000000; - default: - return 0; /* not present */ - } - } - return -1; -} -int hwc_main_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x41, &byte, sizeof (byte))) { - return 0x1000000 << ((byte >> 5) & 0x7); - } - return -1; -} -int hwc_serial_number (void) -{ - int sn = -1; - - if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { - sn = cpu_to_le32 (sn); - } - return sn; -} -int hwc_mac_address (char *str) -{ - char mac[6]; - - if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { - sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } else { - strcpy (str, "ERROR"); - return -1; - } - return 0; -} -int hwc_manufact_date (char *str) -{ - uchar byte; - int value; - - if (seeprom_read (0x92, &byte, sizeof (byte))) - goto out; - value = byte; - if (seeprom_read (0x93, &byte, sizeof (byte))) - goto out; - value += byte << 8; - sprintf (str, "%02d/%02d/%04d", - value & 0x1F, (value >> 5) & 0xF, - 1980 + ((value >> 9) & 0x1FF)); - return 0; - - out: - strcpy (str, "ERROR"); - return -1; -} - -#define PSPAN_ADDR 0xF0020000 -#define EEPROM_REG 0x408 -#define EEPROM_READ_CMD 0xA000 -#define PSPAN_WRITE(a,v) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() -#define PSPAN_READ(a) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) - -int seeprom_read (int addr, uchar * data, int size) -{ - ulong val, cmd; - int i; - - for (i = 0; i < size; i++) { - - cmd = EEPROM_READ_CMD; - cmd |= ((addr + i) << 24) & 0xff000000; - - /* Wait for ACT to authorize write */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Write command */ - PSPAN_WRITE (EEPROM_REG, cmd); - - /* Wait for data to be valid */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - /* Do it twice, first read might be erratic */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Read error */ - if (val & 0x00000040) { - return -1; - } else { - data[i] = (val >> 16) & 0xff; - } - } - return 0; -} diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig new file mode 100644 index 0000000000..e989e4b15c --- /dev/null +++ b/board/isee/igep0033/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AM335X_IGEP0033 + +config SYS_BOARD + default "igep0033" + +config SYS_VENDOR + default "isee" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "am335x_igep0033" + +endif diff --git a/board/isee/igep0033/MAINTAINERS b/board/isee/igep0033/MAINTAINERS new file mode 100644 index 0000000000..d162d7792e --- /dev/null +++ b/board/isee/igep0033/MAINTAINERS @@ -0,0 +1,6 @@ +IGEP0033 BOARD +M: Enric Balletbo i Serra +S: Maintained +F: board/isee/igep0033/ +F: include/configs/am335x_igep0033.h +F: configs/am335x_igep0033_defconfig diff --git a/board/isee/igep0033/Makefile b/board/isee/igep0033/Makefile index 75f1b856d8..fc985b45b6 100644 --- a/board/isee/igep0033/Makefile +++ b/board/isee/igep0033/Makefile @@ -6,33 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifdef CONFIG_SPL_BUILD -COBJS := mux.o +obj-y += mux.o endif -COBJS += board.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += board.o diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index c0f0c0db43..9f8fcf2c1c 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -1,5 +1,5 @@ /* - * Board functions for IGEP COM AQUILA/CYGNUS based boards + * Board functions for IGEP COM AQUILA based boards * * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * @@ -27,11 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - -/* MII mode defines */ -#define RMII_MODE_ENABLE 0x4D - static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifdef CONFIG_SPL_BUILD @@ -40,20 +35,16 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = K4B2G1646EBIH9_WR_DQS, .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE, .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = K4B2G1646EBIH9_RATIO, - .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, .cmd1csratio = K4B2G1646EBIH9_RATIO, - .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, .cmd2csratio = K4B2G1646EBIH9_RATIO, - .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, }; @@ -66,60 +57,47 @@ static struct emif_regs ddr3_emif_reg_data = { .zq_config = K4B2G1646EBIH9_ZQ_CFG, .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, }; -#endif -/* - * Early system init of muxing and clocks. - */ -void s_init(void) -{ - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 400, OSC-1, 1, -1, -1, -1, -1}; - /* Enable RTC32K clock */ - rtc32k_enable(); +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} +void set_uart_mux_conf(void) +{ enable_uart0_pin_mux(); +} - uart_soft_reset(); - gd = &gdata; - - preloader_console_init(); - - /* Configure board pin mux */ +void set_mux_conf_regs(void) +{ enable_board_pin_mux(); +} - config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, +const struct ctrl_ioregs ioregs = { + .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + config_ddr(400, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gpmc_init(); @@ -138,7 +116,7 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; @@ -155,6 +133,7 @@ static struct cpsw_platform_data cpsw_data = { .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, @@ -181,7 +160,8 @@ int board_eth_init(bd_t *bis) eth_setenv_enetaddr("ethaddr", mac_addr); } - writel(RMII_MODE_ENABLE, &cdev->miisel); + writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN), + &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) @@ -192,4 +172,3 @@ int board_eth_init(bd_t *bis) return ret; } #endif - diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h index a6f17e3dd9..a11d7ab86d 100644 --- a/board/isee/igep0033/board.h +++ b/board/isee/igep0033/board.h @@ -1,5 +1,5 @@ /* - * IGEP COM AQUILA/CYGNUS boards information header + * IGEP COM AQUILA boards information header * * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * diff --git a/board/isee/igep0033/mux.c b/board/isee/igep0033/mux.c index 16f4addf3d..e86277663d 100644 --- a/board/isee/igep0033/mux.c +++ b/board/isee/igep0033/mux.c @@ -86,4 +86,3 @@ void enable_board_pin_mux(void) /* Ethernet pinmux. */ configure_module_pin_mux(rmii1_pin_mux); } - diff --git a/board/isee/igep00x0/Kconfig b/board/isee/igep00x0/Kconfig new file mode 100644 index 0000000000..aa46882b05 --- /dev/null +++ b/board/isee/igep00x0/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_IGEP00X0 + +config SYS_BOARD + default "igep00x0" + +config SYS_VENDOR + default "isee" + +config SYS_CONFIG_NAME + default "omap3_igep00x0" + +endif diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS new file mode 100644 index 0000000000..3fc2c6cb9a --- /dev/null +++ b/board/isee/igep00x0/MAINTAINERS @@ -0,0 +1,14 @@ +IGEP00X0 BOARD +M: Enric Balletbo i Serra +S: Maintained +F: board/isee/igep00x0/ +F: include/configs/omap3_igep00x0.h +F: configs/igep0020_defconfig +F: configs/igep0030_defconfig +F: configs/igep0032_defconfig + +IGEP0020_NAND BOARD +#M: - +S: Maintained +F: configs/igep0020_nand_defconfig +F: configs/igep0030_nand_defconfig diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile index 9ad0213bc6..68b151c3c5 100644 --- a/board/isee/igep00x0/Makefile +++ b/board/isee/igep00x0/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := igep00x0.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := igep00x0.o diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 77a9bc6c27..693fce741a 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -5,10 +5,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include +#include #include #include #include -#include #include #include #include @@ -31,6 +33,17 @@ static const u32 gpmc_lan_config[] = { }; #endif +static const struct ns16550_platdata igep_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(igep_uart) = { + "serial_omap", + &igep_serial +}; + /* * Routine: board_init * Description: Early hardware init. @@ -41,22 +54,13 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif + return 0; } -#if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD) -void show_boot_progress(int val) -{ - if (val < 0) { - /* something went wrong */ - return; - } - - if (!gpio_request(IGEP00X0_GPIO_LED, "")) - gpio_direction_output(IGEP00X0_GPIO_LED, 1); -} -#endif - #ifdef CONFIG_SPL_BUILD /* * Routine: omap_rev_string @@ -138,6 +142,25 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + +void set_fdt(void) +{ + switch (gd->bd->bi_arch_number) { + case MACH_TYPE_IGEP0020: + setenv("dtbfile", "omap3-igep0020.dtb"); + break; + case MACH_TYPE_IGEP0030: + setenv("dtbfile", "omap3-igep0030.dtb"); + break; + } +} + /* * Routine: misc_init_r * Description: Configure board specific parts @@ -150,6 +173,8 @@ int misc_init_r(void) dieid_num_r(); + set_fdt(); + return 0; } diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 181f81f2a1..3c7ff9b148 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -7,14 +7,6 @@ #ifndef _IGEP00X0_H_ #define _IGEP00X0_H_ -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) -#define IGEP00X0_GPIO_LED 27 -#endif - -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) -#define IGEP00X0_GPIO_LED 16 -#endif - const omap3_sysinfo sysinfo = { DDR_STACKED, #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) diff --git a/board/ispan/Makefile b/board/ispan/Makefile deleted file mode 100644 index 07fa3f3a2f..0000000000 --- a/board/ispan/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c deleted file mode 100644 index c610c3bd7e..0000000000 --- a/board/ispan/ispan.c +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Interphase iSPAN Communications Controllers - * (453x and others). Tested on 4532. - * - * Derived from iSPAN 4539 port (iphase4539) by - * Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * I/O Ports configuration table - * - * If conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) -#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3) - -const iop_conf_t iop_conf_tab[4][32] = { - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */ - /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */ - /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */ - /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */ - /* PD5 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -#define PSPAN_ADDR 0xF0020000 -#define EEPROM_REG 0x408 -#define EEPROM_READ_CMD 0xA000 -#define PSPAN_WRITE(a,v) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() -#define PSPAN_READ(a) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) - -static int seeprom_read (int addr, uchar * data, int size) -{ - ulong val, cmd; - int i; - - for (i = 0; i < size; i++) { - - cmd = EEPROM_READ_CMD; - cmd |= ((addr + i) << 24) & 0xff000000; - - /* Wait for ACT to authorize write */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Write command */ - PSPAN_WRITE (EEPROM_REG, cmd); - - /* Wait for data to be valid */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - /* Do it twice, first read might be erratic */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Read error */ - if (val & 0x00000040) { - return -1; - } else { - data[i] = (val >> 16) & 0xff; - } - } - return 0; -} - -/*************************************************************** - * We take some basic Hardware Configuration Parameter from the - * Serial EEPROM conected to the PSpan bridge. We keep it as - * simple as possible. - */ -#ifdef DEBUG -static int hwc_flash_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte >> 2) & 0x3) { - case 0x1: - return 0x0400000; - break; - case 0x2: - return 0x0800000; - break; - case 0x3: - return 0x1000000; - default: - return 0x0100000; - } - } - return -1; -} - -static int hwc_local_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte & 0x03)) { - case 0x1: - return 0x0800000; - case 0x2: - return 0x1000000; - default: - return 0; /* not present */ - } - } - return -1; -} -#endif /* DEBUG */ - -static int hwc_main_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x41, &byte, sizeof (byte))) { - return 0x1000000 << ((byte >> 5) & 0x7); - } - return -1; -} - -static int hwc_serial_number (void) -{ - int sn = -1; - - if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { - sn = cpu_to_le32 (sn); - } - return sn; -} - -static int hwc_mac_address (char *str) -{ - char mac[6]; - - if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { - sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } else { - strcpy (str, "ERROR"); - return -1; - } - return 0; -} - -static int hwc_manufact_date (char *str) -{ - uchar byte; - int value; - - if (seeprom_read (0x92, &byte, sizeof (byte))) - goto out; - value = byte; - if (seeprom_read (0x93, &byte, sizeof (byte))) - goto out; - value += byte << 8; - sprintf (str, "%02d/%02d/%04d", - value & 0x1F, (value >> 5) & 0xF, - 1980 + ((value >> 9) & 0x1FF)); - return 0; - -out: - strcpy (str, "ERROR"); - return -1; -} - -static int hwc_board_type (char **str) -{ - ushort id = 0; - - if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) { - switch (id) { - case 0x9080: - *str = "4532-002"; - break; - case 0x9081: - *str = "4532-001"; - break; - case 0x9082: - *str = "4532-000"; - break; - default: - *str = "Unknown"; - } - } else { - *str = "Unknown"; - } - - return id; -} - -phys_size_t initdram (int board_type) -{ - long maxsize = hwc_main_sdram_size(); - -#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE) - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *base; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x00000026; - immap->im_siu_conf.sc_ppc_alrh = 0x01276345; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x00000000; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - immap->im_siu_conf.sc_ltescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* Initialise 60x bus SDRAM */ - base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110); - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or1 = CONFIG_SYS_60x_OR; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR; - - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000; - *base = 0xFF; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *base = 0xFF; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000; - *base = 0xFF; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000; - - /* Initialise local bus SDRAM */ - base = (uchar *)CONFIG_SYS_LSDRAM_BASE; - memctl->memc_lsrt = CONFIG_SYS_LSRT; - memctl->memc_or2 = CONFIG_SYS_LOC_OR; - memctl->memc_br2 = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR; - - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000; - *base = 0xFF; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *base = 0xFF; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000; - *base = 0xFF; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2; - - maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize); - - memctl->memc_or1 |= ~(maxsize - 1); - - if (maxsize != hwc_main_sdram_size()) - puts("Oops: memory test has not found all memory!\n"); -#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */ - - /* Return total RAM size (size of 60x SDRAM) */ - return maxsize; -} - -int checkboard(void) -{ - char string[32], *id; - - hwc_manufact_date(string); - hwc_board_type(&id); - printf("Board: Interphase iSPAN %s (#%d %s)\n", - id, hwc_serial_number(), string); -#ifdef DEBUG - printf("Manufacturing date: %s\n", string); - printf("Serial number : %d\n", hwc_serial_number()); - printf("FLASH size : %d MB\n", hwc_flash_size() >> 20); - printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20); - printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20); - hwc_mac_address(string); - printf("MAC address : %s\n", string); -#endif - return 0; -} - -int misc_init_r(void) -{ - char *s, str[32]; - int num; - - if ((s = getenv("serial#")) == NULL && - (num = hwc_serial_number()) != -1) { - sprintf(str, "%06d", num); - setenv("serial#", str); - } - if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) { - setenv("ethaddr", str); - } - - return 0; -} diff --git a/board/ivm/Makefile b/board/ivm/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/ivm/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ivm/flash.c b/board/ivm/flash.c deleted file mode 100644 index 14d3aee821..0000000000 --- a/board/ivm/flash.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \ - BR_MS_GPCM | BR_PS_16 | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_MT: - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00020000); - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - return; - - case FLASH_MAN_SST: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00002000); - } - return; - - case FLASH_MAN_AMD: - case FLASH_MAN_FUJ: - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - return; - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", - info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_MT: printf ("MT "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n"); - break; - case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n"); - break; - case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n"); - break; - case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n"); - break; - case FLASH_28F008S5: printf ("28F008S5 (1M = 64K x 16)\n"); - break; - case FLASH_28F400_T: printf ("28F400B3 (4Mbit, top boot sector)\n"); - break; - case FLASH_28F400_B: printf ("28F400B3 (4Mbit, bottom boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - ushort value; - vu_short *saddr = (vu_short *)addr; - - /* Read Manufacturer ID */ - saddr[0] = 0x0090; - value = saddr[0]; - - switch (value) { - case (AMD_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (SST_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_SST; - break; - case (STM_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_STM; - break; - case (MT_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_MT; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - saddr[0] = 0x00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = saddr[1]; /* device ID */ - - switch (value) { - case (AMD_ID_LV400T & 0xFFFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0xFFFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0xFFFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0xFFFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & 0xFFFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0xFFFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFFFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & 0xFFFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case (SST_ID_xF200A & 0xFFFF): - info->flash_id += FLASH_SST200A; - info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */ - info->size = 0x00080000; - break; - case (SST_ID_xF400A & 0xFFFF): - info->flash_id += FLASH_SST400A; - info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */ - info->size = 0x00100000; - break; - case (SST_ID_xF800A & 0xFFFF): - info->flash_id += FLASH_SST800A; - info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */ - info->size = 0x00200000; - break; /* => 2 MB */ - case (STM_ID_x800AB & 0xFFFF): - info->flash_id += FLASH_STM800AB; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - case (MT_ID_28F400_T & 0xFFFF): - info->flash_id += FLASH_28F400_T; - info->sector_count = 7; - info->size = 0x00080000; - break; /* => 512 kB */ - case (MT_ID_28F400_B & 0xFFFF): - info->flash_id += FLASH_28F400_B; - info->sector_count = 7; - info->size = 0x00080000; - break; /* => 512 kB */ - default: - info->flash_id = FLASH_UNKNOWN; - saddr[0] = 0x00FF; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - saddr[0] = 0x00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) { - printf ("Can erase only MT flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *)(info->start[sect]); - unsigned short status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x0050; /* clear status register */ - *addr = 0x0020; /* erase setup */ - *addr = 0x00D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & 0x0080) != 0x0080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0x00FF; /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = 0x00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 2 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= FLASH_WIDTH) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0x00FF; /* restore read mode */ - return (1); - } - } - - *addr = 0x00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c deleted file mode 100644 index 3bdbdd17d3..0000000000 --- a/board/ivm/ivm.c +++ /dev/null @@ -1,382 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#ifdef CONFIG_STATUS_LED -# include -#endif - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * 50 MHz SHARC access using UPM A - */ -const uint sharc_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -/* - * 50 MHz SDRAM access using UPM B - */ -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */ - _NOT_USED_, - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00, - 0xE1BBBC04, 0x1FF77C45, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84, - 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ -#ifdef CONFIG_IVMS8 - puts ("Board: IVMS8\n"); -#endif -#ifdef CONFIG_IVML24 - puts ("Board: IVM-L8/24\n"); -#endif - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - long int size_b0; - - /* enable SDRAM clock ("switch on" SDRAM) */ - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* active output */ - immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE; /* output */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE; /* assert SDRAM CLKE */ - udelay (1); - - /* - * Map controller bank 1 for ELIC SACCO - */ - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; - - /* - * Map controller bank 2 for ELIC EPIC - */ - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - - /* - * Configure UPMA for SHARC - */ - upmconfig (UPMA, (uint *) sharc_table, - sizeof (sharc_table) / sizeof (uint)); - -#if defined(CONFIG_IVML24) - /* - * Map controller bank 4 for HDLC Address space - */ - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; -#endif - - /* - * Map controller bank 5 for SHARC - */ - memctl->memc_or5 = CONFIG_SYS_OR5; - memctl->memc_br5 = CONFIG_SYS_BR5; - - memctl->memc_mamr = 0x00001000; - - /* - * Configure UPMB for SDRAM - */ - upmconfig (UPMB, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ - - udelay (200); - memctl->memc_mcr = 0x80806105; /* precharge */ - udelay (1); - memctl->memc_mcr = 0x80806106; /* load mode register */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - - memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ - - /* - * Check Bank 0 Memory Size for re-configuration - */ - size_b0 = - dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - memctl->memc_mbmr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -void reset_phy (void) -{ - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* active output */ - immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN; /* output */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (1000); - - /* - * RESET is implemented by a positive pulse of at least 1 us - * at the reset pin. - * - * Configure RESET pins for NS DP83843 PHY, and RESET chip. - * - * Note: The RESET pin is high active, but there is an - * inverter on the SPD823TS board... - */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET); - immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET; - /* assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET); - udelay (10); - /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET; - udelay (10); -} - -/* ------------------------------------------------------------------------- */ - -void show_boot_progress (int status) -{ -#if defined(CONFIG_STATUS_LED) -# if defined(STATUS_LED_YELLOW) - status_led_set (STATUS_LED_YELLOW, - (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF); -# endif /* STATUS_LED_YELLOW */ -# if defined(STATUS_LED_BOOT) - if (status == BOOTSTAGE_ID_DECOMP_IMAGE) - status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF); -# endif /* STATUS_LED_BOOT */ -#endif /* CONFIG_STATUS_LED */ -} - -/* ------------------------------------------------------------------------- */ - -void ide_set_reset (int on) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int i; - - /* - * Configure PC for IDE Reset Pin - */ - if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); - -#ifdef CONFIG_SYS_PB_12V_ENABLE - /* 12V Enable output OFF */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE); - - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE); - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE); - immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE; - - /* wait 500 ms for the voltage to stabilize */ - for (i = 0; i < 500; ++i) - udelay(1000); -#endif /* CONFIG_SYS_PB_12V_ENABLE */ - } else { /* release RESET */ -#ifdef CONFIG_SYS_PB_12V_ENABLE - /* 12V Enable output ON */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE; -#endif /* CONFIG_SYS_PB_12V_ENABLE */ - -#ifdef CONFIG_SYS_PB_IDE_MOTOR - /* configure IDE Motor voltage monitor pin as input */ - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR); - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR); - immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR); - -/* wait up to 1 s for the motor voltage to stabilize */ - for (i = 0; i < 1000; ++i) { - if ((immr->im_cpm.cp_pbdat - & CONFIG_SYS_PB_IDE_MOTOR) != 0) - break; - udelay(1000); - } - - if (i == 1000) { /* Timeout */ - printf("\nWarning: 5V for IDE Motor missing\n"); -#ifdef CONFIG_STATUS_LED -#ifdef STATUS_LED_YELLOW - status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON); -#endif -#ifdef STATUS_LED_GREEN - status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF); -#endif -#endif /* CONFIG_STATUS_LED */ - } -#endif /* CONFIG_SYS_PB_IDE_MOTOR */ - - immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; - } - - /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET; -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds deleted file mode 100644 index 3d4fc8a2f5..0000000000 --- a/board/ivm/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug deleted file mode 100644 index 1dd207b7f0..0000000000 --- a/board/ivm/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/jornada/Kconfig b/board/jornada/Kconfig new file mode 100644 index 0000000000..195bc26f9e --- /dev/null +++ b/board/jornada/Kconfig @@ -0,0 +1,9 @@ +if TARGET_JORNADA + +config SYS_BOARD + default "jornada" + +config SYS_CONFIG_NAME + default "jornada" + +endif diff --git a/board/jornada/MAINTAINERS b/board/jornada/MAINTAINERS new file mode 100644 index 0000000000..c77d745720 --- /dev/null +++ b/board/jornada/MAINTAINERS @@ -0,0 +1,6 @@ +JORNADA BOARD +M: Kristoffer Ericson +S: Maintained +F: board/jornada/ +F: include/configs/jornada.h +F: configs/jornada_defconfig diff --git a/board/jornada/Makefile b/board/jornada/Makefile index 57cc460991..6a6fbf3551 100644 --- a/board/jornada/Makefile +++ b/board/jornada/Makefile @@ -7,25 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := jornada.o -SOBJS := setup.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := jornada.o +obj-y += setup.o diff --git a/board/jornada/setup.S b/board/jornada/setup.S index 1fafa2ab28..da9f00646d 100644 --- a/board/jornada/setup.S +++ b/board/jornada/setup.S @@ -5,7 +5,7 @@ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * 2004 (c) MontaVista Software, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/board/jse/Kconfig b/board/jse/Kconfig new file mode 100644 index 0000000000..48905fa76f --- /dev/null +++ b/board/jse/Kconfig @@ -0,0 +1,9 @@ +if TARGET_JSE + +config SYS_BOARD + default "jse" + +config SYS_CONFIG_NAME + default "JSE" + +endif diff --git a/board/jse/MAINTAINERS b/board/jse/MAINTAINERS new file mode 100644 index 0000000000..818a5a0be4 --- /dev/null +++ b/board/jse/MAINTAINERS @@ -0,0 +1,6 @@ +JSE BOARD +M: Stephen Williams +S: Maintained +F: board/jse/ +F: include/configs/JSE.h +F: configs/JSE_defconfig diff --git a/board/jse/Makefile b/board/jse/Makefile index c891040dc9..feac3a8834 100644 --- a/board/jse/Makefile +++ b/board/jse/Makefile @@ -8,25 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o sdram.o flash.o host_bridge.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = jse.o sdram.o flash.o host_bridge.o +obj-y += init.o diff --git a/board/jse/init.S b/board/jse/init.S index bccc7e0992..4e449fef20 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -1,28 +1,6 @@ -/*------------------------------------------------------------------------+ */ -/* */ -/* This source code is dual-licensed. You may use it under the terms */ -/* of the GNU General Public License version 2, or under the license */ -/* below. */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------- */ - +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /*------------------------------------------------------------------------- */ /* Function: ext_bus_cntlr_init */ /* Description: Initializes the External Bus Controller for the external */ diff --git a/board/jupiter/Kconfig b/board/jupiter/Kconfig new file mode 100644 index 0000000000..d71acbbc4d --- /dev/null +++ b/board/jupiter/Kconfig @@ -0,0 +1,9 @@ +if TARGET_JUPITER + +config SYS_BOARD + default "jupiter" + +config SYS_CONFIG_NAME + default "jupiter" + +endif diff --git a/board/jupiter/MAINTAINERS b/board/jupiter/MAINTAINERS new file mode 100644 index 0000000000..5a79a616cc --- /dev/null +++ b/board/jupiter/MAINTAINERS @@ -0,0 +1,6 @@ +JUPITER BOARD +M: Heiko Schocher +S: Maintained +F: board/jupiter/ +F: include/configs/jupiter.h +F: configs/jupiter_defconfig diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile index ea0b9b4d3a..4d3ef9ed7a 100644 --- a/board/jupiter/Makefile +++ b/board/jupiter/Makefile @@ -1,4 +1,3 @@ - # # (C) Copyright 2003-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -6,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := jupiter.o diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index 78e4b5d1e9..8856393686 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -283,9 +283,10 @@ void ide_set_reset (int idereset) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/karo/common/Makefile b/board/karo/common/Makefile index 8e22489c3d..05c1d343a0 100644 --- a/board/karo/common/Makefile +++ b/board/karo/common/Makefile @@ -1,50 +1,13 @@ # -# (C) Copyright 2012 Lothar Waßmann +# (C) Copyright 2012-2015 Lothar Waßmann # -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) -endif - -LIB = $(obj)lib$(VENDOR).o - ifeq ($(CONFIG_SPL_BUILD),) - COBJS-$(CONFIG_OF_BOARD_SETUP) += fdt.o - COBJS-$(CONFIG_SPLASH_SCREEN) += splashimage.o + obj-$(CONFIG_OF_LIBFDT) += fdt.o + obj-$(CONFIG_SPLASH_SCREEN) += splashimage.o endif -COBJS-$(CONFIG_CMD_NAND) += nand.o -COBJS-$(CONFIG_ENV_IS_IN_MMC) += mmc.o -COBJS-y += env.o -COBJS := $(COBJS-y) -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -all: $(LIB) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_CMD_NAND) += nand.o +obj-$(CONFIG_ENV_IS_IN_MMC) += mmc.o +obj-y += env.o diff --git a/board/karo/common/karo.h b/board/karo/common/karo.h index d078828d11..d4f5cdb9e8 100644 --- a/board/karo/common/karo.h +++ b/board/karo/common/karo.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. * */ + +#include + struct fb_videomode; #ifdef CONFIG_SYS_LVDS_IF @@ -155,3 +158,5 @@ static inline int karo_load_part(const char *part, void *addr, size_t len) return karo_load_mmc_part(part, addr, len); return ret; } + +#define DIV_ROUND(n, d) (((n) + (d) / 2) / (d)) diff --git a/board/karo/common/mmc.c b/board/karo/common/mmc.c index be42decbf4..0048bfb4af 100644 --- a/board/karo/common/mmc.c +++ b/board/karo/common/mmc.c @@ -163,12 +163,19 @@ int karo_load_mmc_part(const char *part, void *addr, size_t len) debug("Read %u (%u) byte from partition '%s' @ offset 0x"LBAF"\n", ret * mmc->read_bl_len, len, part, part_info.start); } else if (partnum == 0) { - int len_read; - - printf("Reading file %s from mmc partition %d\n", part, 0); - len_read = fs_read(part, (ulong)addr, 0, 0); - if (len_read < 0) - printf("Read from %s failed: %d\n", part, len_read); + loff_t len_read; + + debug("Reading file %s from mmc partition %d\n", part, + partnum); + ret = fs_read(part, (ulong)addr, 0, len, &len_read); + if (ret < 0) { + printf("Failed to read %u byte from mmc partition %d\n", + len, partnum); + goto out; + } + if (len_read < len) { + printf("Read only %llu of %u bytes\n", (u64)len_read, len); + } } else { ret = partnum; goto out; diff --git a/board/karo/common/nand.c b/board/karo/common/nand.c index c982901c7f..6d303f01d8 100644 --- a/board/karo/common/nand.c +++ b/board/karo/common/nand.c @@ -56,8 +56,8 @@ int karo_load_nand_part(const char *part, void *addr, size_t len) return ret; } - debug("Found partition '%s': offset=%08x size=%08x\n", - part, part_info->offset, part_info->size); + debug("Found partition '%s': offset=%08llx size=%08llx\n", + part, (u64)part_info->offset, (u64)part_info->size); if (part_info->size < len) len = part_info->size; @@ -70,8 +70,8 @@ int karo_load_nand_part(const char *part, void *addr, size_t len) return ret; } - debug("Read %u byte from partition '%s' @ offset %08x\n", - len, part, part_info->offset); + debug("Read %u byte from partition '%s' @ offset %08llx\n", + len, part, (u64)part_info->offset); return 0; } diff --git a/board/karo/tk71/Kconfig b/board/karo/tk71/Kconfig new file mode 100644 index 0000000000..7b3d548667 --- /dev/null +++ b/board/karo/tk71/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TK71 + +config SYS_BOARD + default "tk71" + +config SYS_VENDOR + default "karo" + +config SYS_CONFIG_NAME + default "tk71" + +endif diff --git a/board/karo/tk71/MAINTAINERS b/board/karo/tk71/MAINTAINERS new file mode 100644 index 0000000000..ac85d6b44c --- /dev/null +++ b/board/karo/tk71/MAINTAINERS @@ -0,0 +1,6 @@ +TK71 BOARD +#M: - +S: Maintained +F: board/karo/tk71/ +F: include/configs/tk71.h +F: configs/tk71_defconfig diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile index f23b56d878..0e0df770f7 100644 --- a/board/karo/tk71/Makefile +++ b/board/karo/tk71/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := tk71.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := tk71.o diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c index ed0575cb05..35546d24e8 100644 --- a/board/karo/tk71/tk71.c +++ b/board/karo/tk71/tk71.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include @@ -26,9 +26,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(TK71_OE_VAL_LOW, - TK71_OE_VAL_HIGH, - TK71_OE_LOW, TK71_OE_HIGH); + mvebu_config_gpio(TK71_OE_VAL_LOW, + TK71_OE_VAL_HIGH, + TK71_OE_LOW, TK71_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { @@ -97,7 +97,7 @@ int board_init(void) gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/karo/tx25/Kconfig b/board/karo/tx25/Kconfig new file mode 100644 index 0000000000..42746c1c0f --- /dev/null +++ b/board/karo/tx25/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TX25 + +config SYS_BOARD + default "tx25" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "mx25" + +config SYS_CONFIG_NAME + default "tx25" + +endif diff --git a/board/karo/tx25/MAINTAINERS b/board/karo/tx25/MAINTAINERS new file mode 100644 index 0000000000..2defe342ff --- /dev/null +++ b/board/karo/tx25/MAINTAINERS @@ -0,0 +1,6 @@ +TX25 BOARD +M: John Rigby +S: Maintained +F: board/karo/tx25/ +F: include/configs/tx25.h +F: configs/tx25_defconfig diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile index 257cdd21e4..add5dd3669 100644 --- a/board/karo/tx25/Makefile +++ b/board/karo/tx25/Makefile @@ -5,26 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifdef CONFIG_SPL_BUILD -SOBJS := lowlevel_init.o +obj-y += lowlevel_init.o endif -COBJS := tx25.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += tx25.o diff --git a/board/karo/tx28/Kconfig b/board/karo/tx28/Kconfig new file mode 100644 index 0000000000..7c18a451e8 --- /dev/null +++ b/board/karo/tx28/Kconfig @@ -0,0 +1,74 @@ +if TARGET_TX28 + +config SYS_BOARD + default "tx28" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "tx28" + +config TX28 + bool + default y + select SPL + select SOC_MX28 + select APBH_DMA + select APBH_DMA_BURST + select APBH_DMA_BURST8 + select CC_OPTIMIZE_LIBS_FOR_SPEED + select CMD_BMP if LCD + select CMD_NAND_TRIMFFS if CMD_NAND + select CMD_ROMUPDATE if !SPL_BUILD + select FDT_FIXUP_PARTITIONS if OF_LIBFDT + select GET_FEC_MAC_ADDR_FROM_IIM if FEC_MXC + select LIB_RAND + select MTD_PARTITIONS if CMD_NAND + select MTD_DEVICE if CMD_NAND + select SYS_NAND_USE_FLASH_BBT if NAND + +config TARGET_TX28_40X1_NOENV + bool + select TX28 + +config TARGET_TX28_40X2 + bool + select TX28 + +config TARGET_TX28_40X2_NOENV + bool + select TX28 + +config TARGET_TX28_40X3 + bool + select TX28 + +config TARGET_TX28_40X3_NOENV + bool + select TX28 + +config TARGET_TX28_41X0 + bool + select TX28 + +config TARGET_TX28_41X0_NOENV + bool + select TX28 + +choice + prompt "U-Boot image variant" + default TX28_UBOOT + +config TX28_UBOOT + bool "Standard U-Boot image" + +config TX28_UBOOT_NOENV + bool "U-Boot using only built-in environment" + +endchoice + +endif diff --git a/board/karo/tx28/Makefile b/board/karo/tx28/Makefile index e7931405f3..3c8d7f057e 100644 --- a/board/karo/tx28/Makefile +++ b/board/karo/tx28/Makefile @@ -1,53 +1,9 @@ # -# (C) Copyright 2009 DENX Software Engineering -# Author: John Rigby +# (C) Copyright 2015 Lothar Waßmann # -# See file CREDITS for list of people who contributed to this -# project. +# SPDX-License-Identifier: GPL-2.0+ # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := tx28.o -ifeq ($(CONFIG_SPL_BUILD),y) - COBJS += spl_boot.o -else -ifeq ($(CONFIG_CMD_ROMUPDATE),y) - COBJS += flash.o -endif -endif - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -$(obj)u-boot.db: u-boot.db.in - sed "s:@@BUILD_DIR@@:${BUILD_DIR:-.}/:" $< > $@ - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend -######################################################################### +obj-y += tx28.o +obj-$(CONFIG_SPL_BUILD) += spl_boot.o +obj-$(CONFIG_CMD_ROMUPDATE) += flash.o diff --git a/board/karo/tx28/config.mk b/board/karo/tx28/config.mk index c3beb5d27a..0d3b1fd220 100644 --- a/board/karo/tx28/config.mk +++ b/board/karo/tx28/config.mk @@ -2,11 +2,14 @@ CONFIG_SYS_TEXT_BASE := 0x40100000 CONFIG_SPL_TEXT_BASE := 0x00000000 +__HAVE_ARCH_GENERIC_BOARD := y + LOGO_BMP = logos/karo.bmp PLATFORM_CPPFLAGS += -Werror +PLATFORM_CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE) ifneq ($(CONFIG_SPL_BUILD),y) - ALL-y += $(obj)u-boot.sb + ALL-y += $(obj)/u-boot.sb endif CONFIG_SYS_NAND_BLOCK_SIZE := 131072 diff --git a/board/karo/tx28/flash.c b/board/karo/tx28/flash.c index 792df78e3e..4aa3bc921e 100644 --- a/board/karo/tx28/flash.c +++ b/board/karo/tx28/flash.c @@ -24,7 +24,7 @@ #include #include -#include +#include #include #include #include @@ -74,8 +74,7 @@ struct mx28_fcb { #define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) static nand_info_t *mtd = &nand_info[0]; - -extern void *_start; +static bool doit; #define BIT(v,n) (((v) >> (n)) & 0x1) @@ -303,20 +302,25 @@ static int write_fcb(void *buf, int block) return 0; } - ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); - if (ret) { - printf("Failed to erase FCB block %u\n", block); - return ret; + if (doit) { + ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); + if (ret) { + printf("Failed to erase FCB block %u\n", block); + return ret; + } } printf("Writing FCB to block %d @ %08llx\n", block, (u64)block * mtd->erasesize); - chip->select_chip(mtd, 0); - ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1); - if (ret) { - printf("Failed to write FCB to block %u: %d\n", block, ret); + if (doit) { + chip->select_chip(mtd, 0); + ret = chip->write_page(mtd, chip, 0, mtd->writesize, + buf, 1, page, 0, 1); + if (ret) { + printf("Failed to write FCB to block %u: %d\n", block, ret); + } + chip->select_chip(mtd, -1); } - chip->select_chip(mtd, -1); return ret; } @@ -326,13 +330,21 @@ static int write_fcb(void *buf, int block) (b##_start_block <= a##_end_block && \ b##_end_block >= a##_start_block)) -#define fail_if_overlap(a,b,m1,m2) do { \ - if (chk_overlap(a, b)) { \ +#define fail_if_overlap(a,b,m1,m2) do { \ + if (!doit) \ + printf("check: %s[%lu..%lu] <> %s[%lu..%lu]\n", \ + m1, a##_start_block, a##_end_block, \ + m2, b##_start_block, b##_end_block); \ + if (a##_end_block < a##_start_block) \ + printf("Invalid start/end block # for %s\n", m1); \ + if (b##_end_block < b##_start_block) \ + printf("Invalid start/end block # for %s\n", m2); \ + if (chk_overlap(a, b)) { \ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \ - m1, a##_start_block, a##_end_block, \ - m2, b##_start_block, b##_end_block); \ - return -EINVAL; \ - } \ + m1, a##_start_block, a##_end_block, \ + m2, b##_start_block, b##_end_block); \ + return -EINVAL; \ + } \ } while (0) static int tx28_prog_uboot(void *addr, int start_block, int skip, @@ -350,25 +362,28 @@ static int tx28_prog_uboot(void *addr, int start_block, int skip, printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, erase_opts.offset + erase_opts.length - 1); - ret = nand_erase_opts(mtd, &erase_opts); - if (ret) { - printf("Failed to erase flash: %d\n", ret); - return ret; + if (doit) { + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } } - printf("Programming flash @ %08llx..%08llx from %p\n", - (u64)start_block * mtd->erasesize, - (u64)start_block * mtd->erasesize + size - 1, addr); - actual = size; - ret = nand_write_skip_bad(mtd, prg_start, &actual, NULL, - prg_length, addr, WITH_DROP_FFS); - if (ret) { - printf("Failed to program flash: %d\n", ret); - return ret; - } - if (actual < size) { - printf("Could only write %u of %u bytes\n", actual, size); - return -EIO; + printf("Programming flash @ %08x..%08x from %p\n", + prg_start, prg_start + size - 1, addr); + if (doit) { + actual = size; + ret = nand_write_skip_bad(mtd, prg_start, &actual, NULL, + prg_length, addr, WITH_DROP_FFS); + if (ret) { + printf("Failed to program flash: %d\n", ret); + return ret; + } + if (actual < size) { + printf("Could only write %u of %u bytes\n", actual, size); + return -EIO; + } } return 0; } @@ -386,7 +401,6 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) int ret; const unsigned long fcb_start_block = 0, fcb_end_block = 0; int erase_size = mtd->erasesize; - int page_size = mtd->writesize; void *buf; char *load_addr; char *file_size; @@ -419,6 +433,7 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (ret) return ret; + doit = true; for (optind = 1; optind < argc; optind++) { char *endp; @@ -471,6 +486,8 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) mtd_num_blocks - 1); return -EINVAL; } + } else if (strcmp(argv[optind], "-n") == 0) { + doit = false; } else if (argv[optind][0] == '-') { printf("Unrecognized option %s\n", argv[optind]); return -EINVAL; @@ -487,7 +504,14 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) return -EINVAL; } if (argc - optind < 2 && file_size == NULL) { - printf("WARNING: Image size not specified; overwriting whole uboot partition\n"); + if (uboot_part) { + printf("WARNING: Image size not specified; overwriting whole '%s' partition\n", + uboot_part); + printf("This will only work, if there are no bad blocks inside this partition!\n"); + } else { + printf("ERROR: Image size must be specified\n"); + return -EINVAL; + } } if (argc > optind) { load_addr = NULL; @@ -507,13 +531,10 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) size = simple_strtoul(file_size, NULL, 16); printf("Using default file size %08x\n", size); } - if (size > 0) { + if (size > 0) fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize); - } else { - fw_num_blocks = part_info->size / mtd->erasesize - - extra_blocks; - size = fw_num_blocks * mtd->erasesize; - } + else + fw_num_blocks = 0; if (uboot_part) { ret = find_dev_and_part(uboot_part, &dev, &part_num, @@ -525,6 +546,8 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } fw1_start_block = part_info->offset / mtd->erasesize; max_len1 = part_info->size; + if (size == 0) + fw_num_blocks = max_len1 / mtd->erasesize; } else { max_len1 = (fw_num_blocks + extra_blocks) * mtd->erasesize; } @@ -539,6 +562,12 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } fw2_start_block = redund_part_info->offset / mtd->erasesize; max_len2 = redund_part_info->size; + if (fw2_start_block == fcb_start_block) { + fw2_start_block++; + max_len2 -= mtd->erasesize; + } + if (size == 0) + fw_num_blocks = max_len2 / mtd->erasesize; } else if (fw2_set) { max_len2 = (fw_num_blocks + extra_blocks) * mtd->erasesize; } else { @@ -548,8 +577,9 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fw1_skip = find_contig_space(fw1_start_block, fw_num_blocks, max_len1 / mtd->erasesize); if (fw1_skip < 0) { - printf("Could not find %lu contiguous good blocks for fw image\n", - fw_num_blocks); + printf("Could not find %lu contiguous good blocks for fw image in blocks %lu..%lu\n", + fw_num_blocks, fw1_start_block, + fw1_start_block + max_len1 / mtd->erasesize - 1); if (uboot_part) { #ifdef CONFIG_ENV_IS_IN_NAND if (part_info->offset <= CONFIG_ENV_OFFSET + TOTAL_ENV_SIZE) { @@ -567,7 +597,10 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } return -ENOSPC; } - fw1_end_block = fw1_start_block + fw1_skip + fw_num_blocks - 1; + if (extra_blocks) + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + else + fw1_end_block = fw1_start_block + fw_num_blocks + fw1_skip - 1; if (fw2_set && fw2_start_block == 0) fw2_start_block = fw1_end_block + 1; @@ -575,8 +608,9 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fw2_skip = find_contig_space(fw2_start_block, fw_num_blocks, max_len2 / mtd->erasesize); if (fw2_skip < 0) { - printf("Could not find %lu contiguous good blocks for redundant fw image\n", - fw_num_blocks); + printf("Could not find %lu contiguous good blocks for redundant fw image in blocks %lu..%lu\n", + fw_num_blocks, fw2_start_block, + fw2_start_block + max_len2 / mtd->erasesize - 1); if (redund_part) { printf("Increase the size of the '%s' partition or use a different partition\n", redund_part); @@ -588,7 +622,10 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } else { fw2_skip = 0; } - fw2_end_block = fw2_start_block + fw2_skip + fw_num_blocks - 1; + if (extra_blocks) + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + else + fw2_end_block = fw2_start_block + fw_num_blocks + fw2_skip - 1; #ifdef CONFIG_ENV_IS_IN_NAND fail_if_overlap(fcb, env, "FCB", "Environment"); @@ -602,49 +639,44 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) #endif fail_if_overlap(fw1, fw2, "FW1", "FW2"); } + fw1_start_block += fw1_skip; + fw2_start_block += fw2_skip; - buf = malloc(erase_size); + buf = memalign(SZ_128K, erase_size); if (buf == NULL) { printf("Failed to allocate buffer\n"); return -ENOMEM; } - fcb = create_fcb(buf, fw1_start_block + fw1_skip, - fw2_start_block + fw2_skip, fw_num_blocks); + fcb = create_fcb(buf, fw1_start_block, + fw2_start_block, fw_num_blocks); if (IS_ERR(fcb)) { printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); - free(buf); - return PTR_ERR(fcb); + ret = PTR_ERR(fcb); + goto out; } encode_hamming_13_8(fcb, (void *)fcb + 512, 512); ret = write_fcb(buf, fcb_start_block); - free(buf); if (ret) { printf("Failed to write FCB to block %lu\n", fcb_start_block); return ret; } - if (size & (page_size - 1)) { - memset(addr + size, 0xff, size & (page_size - 1)); - size = ALIGN(size, page_size); - } - printf("Programming U-Boot image from %p to block %lu @ %08llx\n", - addr, fw1_start_block + fw1_skip, - (u64)(fw1_start_block + fw1_skip) * mtd->erasesize); + addr, fw1_start_block, (u64)fw1_start_block * mtd->erasesize); ret = tx28_prog_uboot(addr, fw1_start_block, fw1_skip, size, max_len1); - if (fw2_start_block == 0) { - return ret; - } + if (ret || fw2_start_block == 0) + goto out; printf("Programming redundant U-Boot image to block %lu @ %08llx\n", - fw2_start_block + fw2_skip, - (u64)(fw2_start_block + fw2_skip) * mtd->erasesize); + fw2_start_block, (u64)fw2_start_block * mtd->erasesize); ret = tx28_prog_uboot(addr, fw2_start_block, fw2_skip, fw_num_blocks, max_len2); +out: + free(buf); return ret; } @@ -652,12 +684,13 @@ U_BOOT_CMD(romupdate, 11, 0, do_update, "Creates an FCB data structure and writes an U-Boot image to flash", "[-f {|block#}] [-r [{|block#}]] [-e #] [
] []\n" "\t-f \twrite bootloader image to partition \n" - "\t-f #\twrite bootloader image at block # (decimal)\n" - "\t-r\twrite redundant bootloader image at next free block after first image\n" + "\t-f #\t\twrite bootloader image at block # (decimal)\n" + "\t-r\t\twrite redundant bootloader image at next free block after first image\n" "\t-r \twrite redundant bootloader image to partition \n" - "\t-r #\twrite redundant bootloader image at block # (decimal)\n" - "\t-e #\tspecify number of redundant blocks per boot loader image\n" - "\t\tonly valid if -f or -r specify a flash address rather than a partition name\n" - "\t
\tRAM address of bootloader image (default: ${fileaddr}\n" - "\t\tlength of bootloader image in RAM (default: ${filesize}" + "\t-r #\t\twrite redundant bootloader image at block # (decimal)\n" + "\t-e #\t\tspecify number of redundant blocks per boot loader image\n" + "\t\t\t(only valid if -f or -r specify a flash address rather than a partition name)\n" + "\t-n\t\tshow what would be done without actually updating the flash\n" + "\t
\tRAM address of bootloader image (default: ${fileaddr})\n" + "\t\tlength of bootloader image in RAM (default: ${filesize})" ); diff --git a/board/karo/tx28/spl_boot.c b/board/karo/tx28/spl_boot.c index 58335ff6f0..41367c2cab 100644 --- a/board/karo/tx28/spl_boot.c +++ b/board/karo/tx28/spl_boot.c @@ -219,9 +219,10 @@ static void tx28_stk5_led_on(void) gpio_direction_output(MX28_PAD_ENET0_RXD3__GPIO_4_10, 1); } -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads)); + mxs_common_spl_init(arg, resptr, + tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads)); tx28_stk5_lcd_init(); tx28_stk5_led_on(); } @@ -277,7 +278,7 @@ static uint32_t tx28_dram_vals[] = { /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004, /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000, /* 2f0 */ 0x00000000, 0x00000000, -#elif CONFIG_SDRAM_SIZE == SZ_128M +#elif CONFIG_SYS_SDRAM_SIZE == SZ_128M /* TX28-40x0: MT47H64M16HR-3 */ /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -327,7 +328,7 @@ static uint32_t tx28_dram_vals[] = { /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004, /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000, /* 2f0 */ 0x00000000, 0x00000000, -#elif CONFIG_SDRAM_SIZE == SZ_256M +#elif CONFIG_SYS_SDRAM_SIZE == SZ_256M /* TX28-40x2: MEM2G16D2DABG */ /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/board/karo/tx28/tx28.c b/board/karo/tx28/tx28.c index e140e22d51..2e7ec77a10 100644 --- a/board/karo/tx28/tx28.c +++ b/board/karo/tx28/tx28.c @@ -54,11 +54,11 @@ DECLARE_GLOBAL_DATA_PTR; #define STK5_CAN_XCVR_GPIO MX28_PAD_LCD_D00__GPIO_1_0 static const struct gpio tx28_gpios[] = { - { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", }, - { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", }, - { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", }, - { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", }, - { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", }, + { TX28_USBH_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBH VBUSEN", }, + { TX28_USBH_OC_GPIO, GPIOFLAG_INPUT, "USBH OC", }, + { TX28_USBOTG_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUSEN", }, + { TX28_USBOTG_OC_GPIO, GPIOFLAG_INPUT, "USBOTG OC", }, + { TX28_USBOTG_ID_GPIO, GPIOFLAG_INPUT, "USBOTG ID", }, }; static const iomux_cfg_t tx28_pads[] = { @@ -100,7 +100,7 @@ static const iomux_cfg_t tx28_pads[] = { /* provide at least _some_ sort of randomness */ #define MAX_LOOPS 100 -static u32 random; +static u32 random __attribute__((section("data"))); static inline void random_init(void) { @@ -200,7 +200,7 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_FEC_MXC #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM -#ifdef CONFIG_FEC_MXC_MULTI +#ifndef CONFIG_TX28_S #define FEC_MAX_IDX 1 #else #define FEC_MAX_IDX 0 @@ -256,6 +256,46 @@ static int fec_get_mac_addr(int index) eth_setenv_enetaddr(env_name, mac); return 0; } + +static inline int tx28_fec1_enabled(void) +{ + const char *status; + int off; + + if (!gd->fdt_blob) + return 0; + + off = fdt_path_offset(gd->fdt_blob, "ethernet1"); + if (off < 0) + return 0; + + status = fdt_getprop(gd->fdt_blob, off, "status", NULL); + return status && (strcmp(status, "okay") == 0); +} + +static void tx28_init_mac(void) +{ + int ret; + + ret = fec_get_mac_addr(0); + if (ret < 0) { + printf("Failed to read FEC0 MAC address from OCOTP\n"); + return; + } +#ifdef CONFIG_TX28_S + if (tx28_fec1_enabled()) { + ret = fec_get_mac_addr(1); + if (ret < 0) { + printf("Failed to read FEC1 MAC address from OCOTP\n"); + return; + } + } +#endif +} +#else +static inline void tx28_init_mac(void) +{ +} #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */ static const iomux_cfg_t tx28_fec_pads[] = { @@ -292,7 +332,7 @@ int board_eth_init(bd_t *bis) return ret; } -#ifdef CONFIG_FEC_MXC_MULTI +#ifndef CONFIG_TX28_S if (getenv("ethaddr")) { ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { @@ -319,6 +359,10 @@ int board_eth_init(bd_t *bis) #endif return 0; } +#else +static inline void tx28_init_mac(void) +{ +} #endif /* CONFIG_FEC_MXC */ enum { @@ -364,7 +408,7 @@ vidinfo_t panel_info = { .vl_col = 1600, .vl_row = 1200, - .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ .cmap = tx28_cmap, }; @@ -578,9 +622,9 @@ static const iomux_cfg_t stk5_lcd_pads[] = { }; static const struct gpio stk5_lcd_gpios[] = { - { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { TX28_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX28_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX28_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; extern void video_hw_init(void *lcdbase); @@ -728,7 +772,7 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR16; break; default: - panel_info.vl_bpix = LCD_COLOR24; + panel_info.vl_bpix = LCD_COLOR32; } p->pixclock = KHZ2PICOS(refresh * @@ -794,47 +838,11 @@ static void stk5v5_board_init(void) stk5_board_init(); /* init flexcan transceiver enable GPIO */ - gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOF_OUTPUT_INIT_HIGH, + gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "Flexcan Transceiver"); mxs_iomux_setup_pad(STK5_CAN_XCVR_GPIO); } -int tx28_fec1_enabled(void) -{ - const char *status; - int off; - - if (!gd->fdt_blob) - return 0; - - off = fdt_path_offset(gd->fdt_blob, "ethernet1"); - if (off < 0) - return 0; - - status = fdt_getprop(gd->fdt_blob, off, "status", NULL); - return status && (strcmp(status, "okay") == 0); -} - -static void tx28_init_mac(void) -{ - int ret; - - ret = fec_get_mac_addr(0); - if (ret < 0) { - printf("Failed to read FEC0 MAC address from OCOTP\n"); - return; - } -#ifdef CONFIG_FEC_MXC_MULTI - if (tx28_fec1_enabled()) { - ret = fec_get_mac_addr(1); - if (ret < 0) { - printf("Failed to read FEC1 MAC address from OCOTP\n"); - return; - } - } -#endif -} - int board_late_init(void) { int ret = 0; @@ -908,7 +916,7 @@ int checkboard(void) const char *dlm = ""; printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX, - CONFIG_SDRAM_SIZE / SZ_128M + + CONFIG_SYS_SDRAM_SIZE / SZ_128M + CONFIG_SYS_NAND_BLOCKS / 2048 * 2); printf("POWERUP Source: "); @@ -982,7 +990,7 @@ static const char *tx28_touchpanels[] = { "fsl,imx28-lradc", }; -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { const char *baseboard = getenv("baseboard"); int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); @@ -990,9 +998,10 @@ void ft_board_setup(void *blob, bd_t *bd) int ret; ret = fdt_increase_size(blob, 4096); - if (ret) + if (ret) { printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); - + return ret; + } #ifdef CONFIG_TX28_S /* TX28-41xx (aka TX28S) has no external RTC * and no I2C GPIO extender @@ -1011,5 +1020,7 @@ void ft_board_setup(void *blob, bd_t *bd) karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply"); karo_fdt_fixup_flexcan(blob, stk5_v5); karo_fdt_update_fb_mode(blob, video_mode); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/karo/tx48/Kconfig b/board/karo/tx48/Kconfig new file mode 100644 index 0000000000..ea17d4c87b --- /dev/null +++ b/board/karo/tx48/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TX48 + +config SYS_BOARD + default "tx48" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "tx48" + +endif diff --git a/board/karo/tx48/Makefile b/board/karo/tx48/Makefile index 685af9de56..405e8ca315 100644 --- a/board/karo/tx48/Makefile +++ b/board/karo/tx48/Makefile @@ -1,46 +1,11 @@ # -# Makefile +# (C) Copyright 2015 Lothar Waßmann # -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# SPDX-License-Identifier: GPL-2.0+ # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation version 2. -# -# This program is distributed "as is" WITHOUT ANY WARRANTY of any -# kind, whether express or implied; without even the implied warranty -# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).o - -ifeq ($(CONFIG_SPL_BUILD),) - COBJS := tx48.o +ifneq ($(CONFIG_SPL_BUILD),y) + obj-y += tx48.o else - COBJS := spl.o + obj-y += spl.o endif - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/karo/tx48/spl.c b/board/karo/tx48/spl.c index 1b17586bde..2d71d498d9 100644 --- a/board/karo/tx48/spl.c +++ b/board/karo/tx48/spl.c @@ -342,7 +342,7 @@ static struct pin_mux tx48_pins[] = { static struct gpio tx48_gpios[] = { /* configure this pin early to prevent flicker of the LCD */ - { TX48_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { TX48_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; static struct pin_mux tx48_mmc_pins[] = { diff --git a/board/karo/tx48/tx48.c b/board/karo/tx48/tx48.c index 8bc8bc51a6..da17a32f54 100644 --- a/board/karo/tx48/tx48.c +++ b/board/karo/tx48/tx48.c @@ -337,9 +337,9 @@ static const struct pin_mux tx48_i2c_pads[] = { }; static const struct gpio tx48_gpios[] = { - { AM33XX_GPIO_NR(3, 5), GPIOF_INPUT, "I2C1_SDA", }, - { AM33XX_GPIO_NR(3, 6), GPIOF_INPUT, "I2C1_SCL", }, - { AM33XX_GPIO_NR(3, 8), GPIOF_OUTPUT_INIT_LOW, "ETH_PHY_RESET", }, + { AM33XX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "I2C1_SDA", }, + { AM33XX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "I2C1_SCL", }, + { AM33XX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "ETH_PHY_RESET", }, }; static const struct pin_mux stk5_pads[] = { @@ -356,8 +356,8 @@ static const struct pin_mux stk5_pads[] = { }; static const struct gpio stk5_gpios[] = { - { TX48_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, - { TX48_MMC_CD_GPIO, GPIOF_INPUT, "MMC0 CD", }, + { TX48_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + { TX48_MMC_CD_GPIO, GPIOFLAG_INPUT, "MMC0 CD", }, }; static const struct pin_mux stk5_lcd_pads[] = { @@ -386,9 +386,9 @@ static const struct pin_mux stk5_lcd_pads[] = { }; static const struct gpio stk5_lcd_gpios[] = { - { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { AM33XX_GPIO_NR(1, 19), GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", }, + { AM33XX_GPIO_NR(1, 22), GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", }, + { AM33XX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; static const struct pin_mux stk5v5_pads[] = { @@ -397,7 +397,7 @@ static const struct pin_mux stk5v5_pads[] = { }; static const struct gpio stk5v5_gpios[] = { - { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", }, + { AM33XX_GPIO_NR(0, 22), GPIOFLAG_OUTPUT_INIT_HIGH, "CAN XCVR", }, }; #ifdef CONFIG_LCD @@ -407,7 +407,7 @@ vidinfo_t panel_info = { .vl_col = 1366, .vl_row = 768, - .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ .cmap = tx48_cmap, }; @@ -773,7 +773,7 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR16; break; default: - panel_info.vl_bpix = LCD_COLOR24; + panel_info.vl_bpix = LCD_COLOR32; } p->pixclock = KHZ2PICOS(refresh * @@ -1136,7 +1136,7 @@ static const char *tx48_touchpanels[] = { "ti,am3359-tscadc", }; -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { const char *baseboard = getenv("baseboard"); int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); @@ -1144,9 +1144,10 @@ void ft_board_setup(void *blob, bd_t *bd) int ret; ret = fdt_increase_size(blob, 4096); - if (ret) + if (ret) { printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); - + return ret; + } fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); fdt_fixup_ethernet(blob); @@ -1164,5 +1165,7 @@ void ft_board_setup(void *blob, bd_t *bd) karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34, "interrupt-parent"); } + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/karo/tx51/Kconfig b/board/karo/tx51/Kconfig new file mode 100644 index 0000000000..8f0105199d --- /dev/null +++ b/board/karo/tx51/Kconfig @@ -0,0 +1,31 @@ +if TARGET_TX51_8XX0 + +config SYS_BOARD + default "tx51" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "tx51-8xx0" + +endif + +if TARGET_TX51_8XX1_2 + +config SYS_BOARD + default "tx51" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "tx51-8xx1_2" + +endif diff --git a/board/karo/tx51/Makefile b/board/karo/tx51/Makefile index 53c68a2bf5..ee5627b782 100644 --- a/board/karo/tx51/Makefile +++ b/board/karo/tx51/Makefile @@ -1,46 +1,7 @@ # -# (C) Copyright 2009 DENX Software Engineering -# Author: John Rigby +# (C) Copyright 2015 Lothar Waßmann # -# See file CREDITS for list of people who contributed to this -# project. +# SPDX-License-Identifier: GPL-2.0+ # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LDSCRIPT := $(BOARDDIR)/u-boot.lds - -LIB = $(obj)lib$(BOARD).o - -COBJS := tx51.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend -######################################################################### +obj-y += tx51.o lowlevel_init.o diff --git a/board/karo/tx51/config.mk b/board/karo/tx51/config.mk index 899890754f..127325fd03 100644 --- a/board/karo/tx51/config.mk +++ b/board/karo/tx51/config.mk @@ -1,5 +1,6 @@ # stack is allocated below CONFIG_SYS_TEXT_BASE CONFIG_SYS_TEXT_BASE := 0x90100000 +__HAVE_ARCH_GENERIC_BOARD := y PLATFORM_CPPFLAGS += -Werror LOGO_BMP = logos/karo.bmp diff --git a/board/karo/tx51/tx51.c b/board/karo/tx51/tx51.c index f8b8c3ffd5..6bb463243a 100644 --- a/board/karo/tx51/tx51.c +++ b/board/karo/tx51/tx51.c @@ -120,29 +120,29 @@ static iomux_v3_cfg_t tx51_pads[] = { static const struct gpio tx51_gpios[] = { /* RESET_OUT */ - { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", }, + { TX51_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "RESET_OUT", }, /* FEC PHY control GPIOs */ - { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */ - { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */ - { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */ + { TX51_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */ + { TX51_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */ + { TX51_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */ /* FEC PHY strap pins */ - { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */ - { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */ - { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */ - { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */ - { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */ - { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */ - { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ + { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */ + { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */ + { IMX_GPIO_NR(2, 23), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */ + { IMX_GPIO_NR(2, 27), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */ + { IMX_GPIO_NR(2, 28), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */ + { IMX_GPIO_NR(3, 10), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */ + { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ /* module internal I2C bus */ - { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", }, - { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", }, + { IMX_GPIO_NR(4, 17), GPIOFLAG_INPUT, "I2C1 SDA", }, + { IMX_GPIO_NR(4, 16), GPIOFLAG_INPUT, "I2C1 SCL", }, /* Unconnected pins */ - { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", }, - { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", }, + { IMX_GPIO_NR(1, 0), GPIOFLAG_OUTPUT_INIT_LOW, "N/C", }, + { IMX_GPIO_NR(1, 1), GPIOFLAG_OUTPUT_INIT_LOW, "N/C", }, }; /* @@ -394,7 +394,7 @@ int board_mmc_init(bd_t *bis) cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); ret = gpio_request_one(cfg->cd_gpio, - GPIOF_INPUT, "MMC CD"); + GPIOFLAG_INPUT, "MMC CD"); if (ret) { printf("Error %d requesting GPIO%d_%d\n", ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); @@ -451,15 +451,15 @@ static iomux_v3_cfg_t tx51_fec_pads[] = { #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5)) static struct gpio tx51_fec_gpios[] = { - { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", }, - { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */ - { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */ - { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */ - { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */ + { TX51_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY POWER", }, + { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */ + { IMX_GPIO_NR(2, 23), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */ + { IMX_GPIO_NR(2, 27), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */ + { IMX_GPIO_NR(2, 28), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */ #if PHYAD4 - { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ + { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ #else - { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ + { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ #endif }; @@ -538,13 +538,13 @@ static const iomux_v3_cfg_t stk5_pads[] = { }; static const struct gpio stk5_gpios[] = { - { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + { TX51_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, - { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", }, - { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", }, - { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", }, - { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, - { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", }, + { IMX_GPIO_NR(1, 4), GPIOFLAG_OUTPUT_INIT_LOW, "ULPI PHY clk enable", }, + { IMX_GPIO_NR(1, 6), GPIOFLAG_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "ULPI PHY reset", }, + { IMX_GPIO_NR(1, 8), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, + { IMX_GPIO_NR(1, 9), GPIOFLAG_INPUT, "USBH1 OC", }, }; #ifdef CONFIG_LCD @@ -554,7 +554,7 @@ vidinfo_t panel_info = { .vl_col = 1600, .vl_row = 1200, - .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ .cmap = tx51_cmap, }; @@ -777,9 +777,9 @@ static const iomux_v3_cfg_t stk5_lcd_pads[] = { }; static const struct gpio stk5_lcd_gpios[] = { - { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { TX51_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX51_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX51_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; void lcd_ctrl_init(void *lcdbase) @@ -929,7 +929,7 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR16; break; default: - panel_info.vl_bpix = LCD_COLOR24; + panel_info.vl_bpix = LCD_COLOR32; } p->pixclock = KHZ2PICOS(refresh * @@ -1118,15 +1118,16 @@ static const char *tx51_touchpanels[] = { "edt,edt-ft5x06", }; -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { const char *video_mode = karo_get_vmode(getenv("video_mode")); int ret; ret = fdt_increase_size(blob, 4096); - if (ret) + if (ret) { printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); - + return ret; + } fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); fdt_fixup_ethernet(blob); @@ -1134,5 +1135,7 @@ void ft_board_setup(void *blob, bd_t *bd) ARRAY_SIZE(tx51_touchpanels)); karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply"); karo_fdt_update_fb_mode(blob, video_mode); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/karo/tx53/Kconfig b/board/karo/tx53/Kconfig new file mode 100644 index 0000000000..2c30f58cc1 --- /dev/null +++ b/board/karo/tx53/Kconfig @@ -0,0 +1,94 @@ +if TARGET_TX53 + +config SYS_BOARD + default "tx53" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "tx53" + +config TX53 + bool + default y + select CC_OPTIMIZE_LIBS_FOR_SPEED + select CMD_BMP if LCD + select CMD_BOOTCE + select CMD_BOOTZ + select CMD_CACHE + select CMD_I2C if I2C + select CMD_MEMINFO + select CMD_MEMTEST + select CMD_MMC + select CMD_NAND + select CMD_NAND_TRIMFFS + select CMD_ROMUPDATE + select CMD_TIME + select DM + select DM_GPIO + select FDT_FIXUP_PARTITIONS if OF_LIBFDT + select GET_FEC_MAC_ADDR_FROM_IIM + select IMX_WATCHDOG + select LIB_RAND + select MMC + select MTD_PARTITIONS + select MTD_DEVICE + select NAND + select NAND_MXC + select OF_LIBFDT + select OF_BOARD_SETUP + select PHYLIB + select PHY_SMSC + select SOC_MX53 + select SYS_I2C + select SYS_I2C_MXC + select SYS_NAND_USE_FLASH_BBT if NAND_MXC + +# +# variables selected depending on module variant +# + +config SYS_LVDS_IF + bool + +choice + prompt "TX53 module variant" + +config TARGET_TX53_X030 + bool "TX53-8030 and TX53-1030" + +config TARGET_TX53_X130 + bool "TX53-8130 and TX53-1330" + select SYS_LVDS_IF + +config TARGET_TX53_X131 + bool "TX53-8131 and TX53-1331" + select SYS_LVDS_IF + +config TARGET_TX53_1232 + bool "TX53-1232" + +endchoice + +config NR_DRAM_BANKS + int + default 2 if TARGET_TX53_1232 || TARGET_TX53_X131 + default 1 + +choice + prompt "U-Boot image variant" + +config TX53_UBOOT + bool "Standard U-Boot image" + +config TX53_UBOOT_NOENV + bool "U-Boot using only built-in environment" + select ENV_IS_NOWHERE + +endchoice + +endif diff --git a/board/karo/tx53/Makefile b/board/karo/tx53/Makefile index 9ac5e7ca9c..7500ab63be 100644 --- a/board/karo/tx53/Makefile +++ b/board/karo/tx53/Makefile @@ -1,42 +1,10 @@ # -# (C) Copyright 2012 Lothar Waßmann +# (C) Copyright 2015 Lothar Waßmann # -# See file CREDITS for list of people who contributed to this -# project. +# SPDX-License-Identifier: GPL-2.0+ # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -include $(TOPDIR)/config.mk LDSCRIPT := $(BOARDDIR)/u-boot.lds -LIB = $(obj)lib$(BOARD).o - -COBJS := tx53.o -ifeq ($(CONFIG_CMD_ROMUPDATE),y) - COBJS += flash.o -endif -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += lowlevel_init.o tx53.o +obj-$(CONFIG_CMD_ROMUPDATE) += flash.o diff --git a/board/karo/tx53/config.mk b/board/karo/tx53/config.mk index e765c3a0dd..09d6709dfe 100644 --- a/board/karo/tx53/config.mk +++ b/board/karo/tx53/config.mk @@ -1,5 +1,7 @@ # stack is allocated below CONFIG_SYS_TEXT_BASE -CONFIG_SYS_TEXT_BASE := 0x70100000 +CONFIG_SYS_TEXT_BASE := 0x700ff000 +__HAVE_ARCH_GENERIC_BOARD := y PLATFORM_CPPFLAGS += -Werror LOGO_BMP = logos/karo.bmp +OBJCOPYFLAGS += -j .pad diff --git a/board/karo/tx53/flash.c b/board/karo/tx53/flash.c index d111633e90..76e994cd95 100644 --- a/board/karo/tx53/flash.c +++ b/board/karo/tx53/flash.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2014 Lothar Waßmann + * Copyright (C) 2011-2015 Lothar Waßmann * * See file CREDITS for list of people who contributed to this * project. @@ -103,7 +103,7 @@ static struct mx53_fcb *create_fcb(void *buf, int fw1_start_block, fcb = buf; memset(fcb, 0x00, sizeof(*fcb)); - memset(fcb + 1, 0xff, mtd->erasesize - sizeof(*fcb)); + memset(fcb + 1, 0xff, SZ_1K - sizeof(*fcb)); strncpy((char *)&fcb->fingerprint, "FCB ", 4); fcb->version = 1; @@ -172,7 +172,8 @@ static int write_fcb(void *buf, int block) (u64)block * mtd->erasesize); if (doit) { chip->select_chip(mtd, 0); - ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1); + ret = chip->write_page(mtd, chip, 0, mtd->writesize, + buf, 1, page, 0, 0); if (ret) { printf("Failed to write FCB to block %u: %d\n", block, ret); } @@ -211,9 +212,9 @@ static int tx53_prog_uboot(void *addr, int start_block, int skip, nand_erase_options_t erase_opts = { 0, }; size_t actual; size_t prg_length = max_len - skip * mtd->erasesize; - int prg_start = start_block * mtd->erasesize; + int prg_start = (start_block + skip) * mtd->erasesize; - erase_opts.offset = (start_block - skip) * mtd->erasesize; + erase_opts.offset = start_block * mtd->erasesize; erase_opts.length = max_len; erase_opts.quiet = 1; @@ -258,8 +259,8 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) int ret; const unsigned long fcb_start_block = 0, fcb_end_block = 0; int erase_size = mtd->erasesize; - int page_size = mtd->writesize; void *buf; + size_t buf_size; char *load_addr; char *file_size; size_t size = 0; @@ -404,14 +405,6 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } fw1_start_block = part_info->offset / mtd->erasesize; max_len1 = part_info->size; - /* - * Skip one block, if the U-Boot image resides in the - * same partition as the FCB - */ - if (fw1_start_block == fcb_start_block) { - fw1_start_block++; - max_len1 -= mtd->erasesize; - } if (size == 0) fw_num_blocks = max_len1 / mtd->erasesize; } else { @@ -497,7 +490,6 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fail_if_overlap(fcb, env, "FCB", "Environment"); fail_if_overlap(fw1, env, "FW1", "Environment"); #endif - fail_if_overlap(fw1, fcb, "FW1", "FCB"); if (fw2_set) { fail_if_overlap(fw2, fcb, "FW2", "FCB"); #ifdef CONFIG_ENV_IS_IN_NAND @@ -508,43 +500,57 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fw1_start_block += fw1_skip; fw2_start_block += fw2_skip; - buf = malloc(erase_size); + buf_size = fw_num_blocks * erase_size; + buf = memalign(erase_size, buf_size); if (buf == NULL) { printf("Failed to allocate buffer\n"); return -ENOMEM; } + /* copy U-Boot image to buffer */ + memcpy(buf, addr, size); + memset(buf + size, 0xff, buf_size - size); + fcb = create_fcb(buf, fw1_start_block, fw2_start_block, fw_num_blocks); if (IS_ERR(fcb)) { printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); - free(buf); - return PTR_ERR(fcb); + ret = PTR_ERR(fcb); + goto out; } - ret = write_fcb(buf, fcb_start_block); - free(buf); - if (ret) { - printf("Failed to write FCB to block %lu\n", fcb_start_block); - return ret; - } + if (fw1_start_block == fcb_start_block) { + printf("Programming FCB + U-Boot image from %p to block %lu @ %08llx\n", + buf, fw1_start_block, (u64)fw1_start_block * mtd->erasesize); + ret = tx53_prog_uboot(buf, fw1_start_block, fw1_skip, size, + max_len1); + } else { + printf("Programming U-Boot image from %p to block %lu @ %08llx\n", + buf, fw1_start_block, (u64)fw1_start_block * mtd->erasesize); + ret = tx53_prog_uboot(buf, fw1_start_block, fw1_skip, size, + max_len1); + if (ret) + goto out; - if (size & (page_size - 1)) { - memset(addr + size, 0xff, size & (page_size - 1)); - size = ALIGN(size, page_size); - } + memset(buf + sizeof(*fcb), 0xff, + mtd->writesize - sizeof(*fcb)); - printf("Programming U-Boot image from %p to block %lu @ %08llx\n", - addr, fw1_start_block, (u64)fw1_start_block * mtd->erasesize); - ret = tx53_prog_uboot(addr, fw1_start_block, fw1_skip, size, - max_len1); + ret = write_fcb(buf, fcb_start_block); + if (ret) { + printf("Failed to write FCB to block %lu\n", fcb_start_block); + return ret; + } + memset(buf, 0xff, SZ_1K); + } if (ret || fw2_start_block == 0) - return ret; + goto out; printf("Programming redundant U-Boot image to block %lu @ %08llx\n", fw2_start_block, (u64)fw2_start_block * mtd->erasesize); - ret = tx53_prog_uboot(addr, fw2_start_block, fw2_skip, size, + ret = tx53_prog_uboot(buf, fw2_start_block, fw2_skip, size, max_len2); +out: + free(buf); return ret; } diff --git a/board/karo/tx53/lowlevel_init.S b/board/karo/tx53/lowlevel_init.S index 32a2ec722e..ad43e481ac 100644 --- a/board/karo/tx53/lowlevel_init.S +++ b/board/karo/tx53/lowlevel_init.S @@ -1,5 +1,7 @@ #include +#include #include +#include #include #define DEBUG_LED_BIT 20 @@ -85,6 +87,8 @@ dcd_start: .error "DCD too large!" .endif dcd_end: + .section ".pad" + .section ".text" .endm #define MXC_DCD_CMD_WRT(type, flags) \ @@ -365,22 +369,7 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (tODTLon << 12) | \ (tODTLoff << 4)) -fcb_start: - b _start - .word 0x20424346 /* "FCB " marker */ - .word 0x01 /* FCB version number */ - .org 0x68 - .word 0x0 /* primary image starting page number */ - .word 0x0 /* secondary image starting page number */ - .org 0x78 - .word 0x0 /* DBBT start page (0 == NO DBBT) */ - .word 0 /* Bad block marker offset in main area (unused) */ - .org 0xac - .word 0 /* BI Swap disabled */ - .word 0 /* Bad Block marker offset in spare area */ -fcb_end: - - .org 0x400 + .section ".ivt" ivt_header: .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) app_start_addr: @@ -393,12 +382,12 @@ boot_data_ptr: self_ptr: .word ivt_header app_code_csf: - .word 0x0 + .word __csf_data .word 0x0 boot_data: - .long fcb_start + .long CONFIG_SYS_TEXT_BASE image_len: - .long __uboot_img_end - fcb_start + .long __uboot_img_len plugin: .word 0 ivt_end: @@ -415,7 +404,12 @@ dcd_hdr: MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffcf) MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000) MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff) +#ifdef CONFIG_SECURE_BOOT + /* enable Sahara */ + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x0000c000) +#else MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000) +#endif MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033) MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f) MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000) diff --git a/board/karo/tx53/tx53.c b/board/karo/tx53/tx53.c index 9df8126ad4..299a647b16 100644 --- a/board/karo/tx53/tx53.c +++ b/board/karo/tx53/tx53.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -59,6 +60,7 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP) char __uboot_img_end[0] __attribute__((section(".__uboot_img_end"))); +char __csf_data[0] __attribute__((section(".__csf_data"))); static iomux_v3_cfg_t tx53_pads[] = { /* NAND flash pads are set up in lowlevel_init.S */ @@ -105,10 +107,10 @@ static iomux_v3_cfg_t tx53_pads[] = { }; static const struct gpio tx53_gpios[] = { - { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, - { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, - { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, - { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, + { TX53_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", }, + { TX53_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, + { TX53_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", }, + { TX53_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, }; /* @@ -444,9 +446,6 @@ int board_early_init_f(void) { struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR; - gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios)); - imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads)); - writel(0x77777777, AIPS1_BASE_ADDR + 0x00); writel(0x77777777, AIPS1_BASE_ADDR + 0x04); @@ -475,6 +474,8 @@ int board_early_init_f(void) writel(0xfff00000, &ccm_regs->CCGR7); writel(0x00000000, &ccm_regs->cmeor); + imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads)); + return 0; } @@ -482,6 +483,11 @@ int board_init(void) { int ret; + ret = gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios)); + if (ret < 0) { + printf("Failed to request tx53_gpios: %d\n", ret); + } + /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; @@ -628,7 +634,7 @@ int board_mmc_init(bd_t *bis) cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); ret = gpio_request_one(cfg->cd_gpio, - GPIOF_INPUT, "MMC CD"); + GPIOFLAG_INPUT, "MMC CD"); if (ret) { printf("Error %d requesting GPIO%d_%d\n", ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); @@ -747,12 +753,12 @@ static const iomux_v3_cfg_t stk5_pads[] = { }; static const struct gpio stk5_gpios[] = { - { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + { TX53_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, - { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, - { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, - { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, - { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, + { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, + { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", }, + { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, }; #ifdef CONFIG_LCD @@ -762,7 +768,7 @@ vidinfo_t panel_info = { .vl_col = 1600, .vl_row = 1200, - .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ .cmap = tx53_cmap, }; @@ -833,7 +839,6 @@ static struct fb_videomode tx53_fb_modes[] = { .upper_margin = 2, .vsync_len = 10, .lower_margin = 2, - .sync = FB_SYNC_CLK_LAT_FALL, }, { /* Emerging ET0500G0DH6 800 x 480 display. @@ -1022,9 +1027,9 @@ static const iomux_v3_cfg_t stk5_lcd_pads[] = { }; static const struct gpio stk5_lcd_gpios[] = { - { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { TX53_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX53_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX53_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; void lcd_ctrl_init(void *lcdbase) @@ -1055,13 +1060,14 @@ void lcd_ctrl_init(void *lcdbase) } karo_fdt_move_fdt(); - lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt); if (video_mode == NULL) { debug("Disabling LCD\n"); lcd_enabled = 0; return; } + + lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt); vm = video_mode; if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) { p = &fb_mode; @@ -1183,7 +1189,7 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR16; break; default: - panel_info.vl_bpix = LCD_COLOR24; + panel_info.vl_bpix = LCD_COLOR32; } p->pixclock = KHZ2PICOS(refresh * @@ -1283,7 +1289,7 @@ static void stk5v5_board_init(void) { stk5_board_init(); - gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, + gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH, "Flexcan Transceiver"); imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21); } @@ -1374,6 +1380,9 @@ exit: gpio_set_value(TX53_RESET_OUT_GPIO, 1); clear_ctrlc(); + + get_hab_status(); + return ret; } @@ -1422,7 +1431,7 @@ static const char *tx53_touchpanels[] = { "eeti,egalax_ts", }; -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { const char *baseboard = getenv("baseboard"); int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); @@ -1430,9 +1439,10 @@ void ft_board_setup(void *blob, bd_t *bd) int ret; ret = fdt_increase_size(blob, 4096); - if (ret) + if (ret) { printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); - + return ret; + } if (stk5_v5) karo_fdt_enable_node(blob, "stk5led", 0); @@ -1445,5 +1455,7 @@ void ft_board_setup(void *blob, bd_t *bd) karo_fdt_fixup_flexcan(blob, stk5_v5); tx53_fixup_rtc(blob); karo_fdt_update_fb_mode(blob, video_mode); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/karo/tx53/u-boot.lds b/board/karo/tx53/u-boot.lds index 9276d3b130..392a9ef42a 100644 --- a/board/karo/tx53/u-boot.lds +++ b/board/karo/tx53/u-boot.lds @@ -27,11 +27,17 @@ SECTIONS . = 0x00000000; .text : { - KEEP(board/karo/tx53/lowlevel_init.o (.text*)) + __uboot_img_start = .; + . = 0x400; + __ivt_start = .; + KEEP(*(.ivt*)) + . = 0x1000; + __ivt_end = .; *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) *(.text*) - } + } = 0xadde01f0 . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } @@ -39,9 +45,9 @@ SECTIONS . = ALIGN(4); .data : { *(.data*) + . = ALIGN(4); } - . = ALIGN(4); .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } @@ -67,17 +73,30 @@ SECTIONS *(.__rel_dyn_end) } - /* Workaround for an apparent bug in i.MX53 ROM Code, - * that skips loading the last block if it doesn't - * end on a 4KiB boundary. - */ - . = ALIGN(4096); + .pad : + { + /* Workaround for a bug in i.MX53 ROM Code, + * which skips loading the last block if it doesn't + * end on a 4KiB boundary. + */ + *(.pad) + . = ALIGN(4096); + } = 0x01f0adde + + _image_binary_end = . + (__ivt_end - __uboot_img_start); + .uboot_img_end : { - *(.__uboot_img_end) + KEEP(*(.__uboot_img_end)) } - _end = .; + . = CONFIG_SYS_TEXT_BASE + 0x70000; + .csf_data : + { + *(.__csf_data) + . = . + 0x2000; + } + __uboot_img_len = . - __uboot_img_start; /* * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c @@ -97,13 +116,18 @@ SECTIONS .bss_end __bss_limit (OVERLAY) : { KEEP(*(.__bss_end)); } - - /DISCARD/ : { *(.bss*) } + + .dynsym _image_binary_end : { *(.dynsym) } + /DISCARD/ : { *(.debug*) } + /DISCARD/ : { *(.note*) } + /DISCARD/ : { *(.comment*) } + /DISCARD/ : { *(.dynbss) } /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu.hash) } /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } } diff --git a/board/karo/tx6/Kconfig b/board/karo/tx6/Kconfig new file mode 100644 index 0000000000..091efde26c --- /dev/null +++ b/board/karo/tx6/Kconfig @@ -0,0 +1,145 @@ +if TARGET_TX6 + +config SYS_BOARD + default "tx6" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "tx6" + +config TX6 + bool + default y + select CMD_BMP if LCD + select CMD_BOOTCE + select CMD_BOOTZ + select CMD_CACHE + select CMD_I2C if I2C + select CMD_MEMTEST + select CMD_MMC + select CMD_TIME + select DM + select DM_GPIO + select LIB_RAND + select PHYLIB + select SYS_I2C + select SYS_I2C_MXC + select GET_FEC_MAC_ADDR_FROM_IIM + select OF_BOARD_SETUP + select OF_LIBFDT + +config TX6_NAND + bool + default ! TX6_EMMC + select CMD_NAND + select CMD_NAND_TRIMFFS + select CMD_MTDPARTS + select CMD_ROMUPDATE + select FDT_FIXUP_PARTITIONS if OF_LIBFDT + select MTD_PARTITIONS + select NAND + select NAND_MXS + select NAND_MXS_NO_BBM_SWAP + select SYS_NAND_USE_FLASH_BBT + select APBH_DMA + select APBH_DMA_BURST + select APBH_DMA_BURST8 + select MTD_DEVICE + +config TX6_EMMC + bool + select SUPPORT_EMMC_BOOT + +# +# variables selected depending on module variant +# +config SYS_LVDS_IF + bool + +config SYS_SDRAM_BUS_WIDTH_16 + bool + +config SYS_SDRAM_BUS_WIDTH_32 + bool + + +choice + prompt "TX6 module variant" + +config TARGET_TX6Q_10X0 + bool "TX6Q-1010 and TX6Q-1030" + select SOC_MX6Q + +config TARGET_TX6Q_1020 + bool "TX6Q-1020" + select SOC_MX6Q + select TX6_EMMC + +config TARGET_TX6Q_11X0 + bool "TX6Q-1110 and TX6Q-1130" + select SOC_MX6Q + select SYS_LVDS_IF + +config TARGET_TX6S_8034 + bool "TX6S-8034" + select SOC_MX6S + select SYS_SDRAM_BUS_WIDTH_16 + +config TARGET_TX6S_8035 + bool "TX6S-8035" + select SOC_MX6S + select TX6_EMMC + select SYS_SDRAM_BUS_WIDTH_32 + +config TARGET_TX6U_80X0 + bool "TX6U-8010 and TX6U-8030" + select SOC_MX6DL + +config TARGET_TX6U_8011 + bool "TX6U-8011" + select SOC_MX6DL + select SYS_SDRAM_BUS_WIDTH_32 + +config TARGET_TX6U_8012 + bool "TX6U-8012" + select SOC_MX6DL + +config TARGET_TX6U_81X0 + bool "TX6U-8110 and TX6U-8130" + select SOC_MX6DL + select SYS_LVDS_IF + +config TARGET_TX6U_8111 + bool "TX6U-8111" + select SOC_MX6DL + select SYS_SDRAM_BUS_WIDTH_32 + select SYS_LVDS_IF + +config TARGET_TX6U_8033 + bool "TX6U-8033" + select SOC_MX6DL + select TX6_EMMC + +endchoice + +choice + prompt "U-Boot image variant" + default TX6_UBOOT + +config TX6_UBOOT + bool "Standard U-Boot image" + +config TX6_UBOOT_MFG + bool "U-Boot image for use with Freescale's MfGTool" + +config TX6_UBOOT_NOENV + bool "U-Boot using only built-in environment" + +endchoice + +endif diff --git a/board/karo/tx6/Makefile b/board/karo/tx6/Makefile index dd845bf14f..74d5c0cd18 100644 --- a/board/karo/tx6/Makefile +++ b/board/karo/tx6/Makefile @@ -1,34 +1,14 @@ # -# (C) Copyright 2009 DENX Software Engineering -# Author: John Rigby +# (C) Copyright 2015 Lothar Waßmann # # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +LDSCRIPT := $(BOARDDIR)/u-boot.lds -LIB = $(obj)lib$(BOARD).o +obj-y += lowlevel_init.o pmic.o tx6qdl.o +obj-$(CONFIG_LTC3676) += ltc3676.o +obj-$(CONFIG_RN5T567) += rn5t567.o +obj-$(CONFIG_RN5T618) += rn5t618.o -COBJS-y := tx6qdl.o -COBJS-$(CONFIG_LTC3676) += ltc3676.o -COBJS-$(CONFIG_RN5T567) += rn5t567.o -COBJS-$(CONFIG_RN5T618) += rn5t618.o -COBJS-y += pmic.o -COBJS-$(CONFIG_CMD_ROMUPDATE) += flash.o - -SOBJS-y := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_CMD_ROMUPDATE) += flash.o diff --git a/board/karo/tx6/config.mk b/board/karo/tx6/config.mk index c8af7c793e..acb0cd0d51 100644 --- a/board/karo/tx6/config.mk +++ b/board/karo/tx6/config.mk @@ -1,12 +1,19 @@ # stack is allocated below CONFIG_SYS_TEXT_BASE -CONFIG_SYS_TEXT_BASE := 0x10100000 +#CONFIG_SYS_TEXT_BASE := 0x10100000 +#CONFIG_SYS_TEXT_BASE := 0x177ff000 +CONFIG_SYS_TEXT_BASE := 0x100ff000 + +OBJCOPYFLAGS += -j .pad LOGO_BMP = logos/karo.bmp #PLATFORM_CPPFLAGS += -DDEBUG #PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable PLATFORM_CPPFLAGS += -Werror +ifneq ($(CONFIG_SECURE_BOOT),) + PLATFORM_CPPFLAGS += -DCONFIG_SECURE_BOOT +endif -ifeq ($(CONFIG_NO_NAND),) +ifeq ($(CONFIG_TX6_NAND),y) # calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size CONFIG_SYS_NAND_BLOCK_SIZE := 131072 ifeq ($(CONFIG_SYS_NAND_BLOCKS),) @@ -52,4 +59,4 @@ PLATFORM_CPPFLAGS += -DCONFIG_SYS_MMC_BOOT_PART_SIZE=$(CONFIG_SYS_MMC_BOOT_PART_ PLATFORM_CPPFLAGS += -DCONFIG_ENV_OFFSET=$(shell printf "0x%x" $(CONFIG_ENV_OFFSET)) PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_OFFSET=$(shell printf "0x%x" $(CONFIG_SYS_DTB_OFFSET)) PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_BLKNO=$(shell printf "0x%x" `expr $(CONFIG_SYS_DTB_OFFSET) / 512`) -endif # CONFIG_NO_NAND +endif # CONFIG_TX6_NAND diff --git a/board/karo/tx6/flash.c b/board/karo/tx6/flash.c index ce90c4e6c9..d57c994707 100644 --- a/board/karo/tx6/flash.c +++ b/board/karo/tx6/flash.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012-2014 Lothar Waßmann + * Copyright (C) 2012-2015 Lothar Waßmann * * See file CREDITS for list of people who contributed to this * project. @@ -24,7 +24,7 @@ #include #include -#include +#include #include #include #include @@ -91,11 +91,27 @@ struct mx6_dbbt { u32 bb_num[2040 / 4]; }; +struct mx6_ivt { + u32 magic; + u32 app_start_addr; + u32 rsrvd1; + void *dcd; + void *boot_data; + void *self; + void *csf; + u32 rsrvd2; +}; + +struct mx6_boot_data { + void *start; + u32 length; + u32 plugin; +}; + #define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) static nand_info_t *mtd = &nand_info[0]; - -extern void *_start; +static bool doit; #define BIT(v,n) (((v) >> (n)) & 0x1) @@ -198,7 +214,8 @@ static int find_contig_space(int block, int num_blocks, int max_blocks) return -ENOSPC; } -#define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n) +#define offset_of(p, m) ((void *)&(p)->m - (void *)(p)) +#define pr_fcb_val(p, n) debug("%-24s[%02x]=%08x(%d)\n", #n, offset_of(p, n), (p)->n, (p)->n) static struct mx6_fcb *create_fcb(void *buf, int fw1_start_block, int fw2_start_block, int fw_num_blocks) @@ -327,83 +344,49 @@ static int write_fcb(void *buf, int block) return 0; } - ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); - if (ret) { - printf("Failed to erase FCB block %u\n", block); - return ret; + if (doit) { + ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); + if (ret) { + printf("Failed to erase FCB block %u\n", block); + return ret; + } } printf("Writing FCB to block %d @ %08llx\n", block, (u64)block * mtd->erasesize); - chip->select_chip(mtd, 0); - ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1); - if (ret) { - printf("Failed to write FCB to block %u: %d\n", block, ret); + if (doit) { + chip->select_chip(mtd, 0); + ret = chip->write_page(mtd, chip, 0, mtd->writesize, + buf, 1, page, 0, 1); + if (ret) { + printf("Failed to write FCB to block %u: %d\n", block, ret); + } + chip->select_chip(mtd, -1); } - chip->select_chip(mtd, -1); return ret; } -struct mx6_ivt { - u32 magic; - u32 entry; - u32 rsrvd1; - void *dcd; - void *boot_data; - void *self; - void *csf; - u32 rsrvd2; -}; - -struct mx6_boot_data { - u32 start; - u32 length; - u32 plugin; -}; - -static int find_ivt(void *buf) -{ - struct mx6_ivt *ivt_hdr = buf + 0x400; - - if ((ivt_hdr->magic & 0xff0000ff) != 0x400000d1) - return 0; - - return 1; -} - -static inline void *reloc(void *dst, void *base, void *ptr) -{ - return dst + (ptr - base); -} - -static int patch_ivt(void *buf, size_t fsize) -{ - struct mx6_ivt *ivt_hdr = buf + 0x400; - struct mx6_boot_data *boot_data; - - if (!find_ivt(buf)) { - printf("No IVT found in image at %p\n", buf); - return -EINVAL; - } - boot_data = reloc(ivt_hdr, ivt_hdr->self, ivt_hdr->boot_data); - boot_data->length = fsize; - - return 0; -} - #define chk_overlap(a,b) \ ((a##_start_block <= b##_end_block && \ a##_end_block >= b##_start_block) || \ (b##_start_block <= a##_end_block && \ b##_end_block >= a##_start_block)) -#define fail_if_overlap(a,b,m1,m2) do { \ - if (chk_overlap(a, b)) { \ +#define fail_if_overlap(a,b,m1,m2) do { \ + if (!doit) \ + printf("check: %s[%lu..%lu] <> %s[%lu..%lu]\n", \ + m1, a##_start_block, a##_end_block, \ + m2, b##_start_block, b##_end_block); \ + if (a##_end_block < a##_start_block) \ + printf("Invalid start/end block # for %s\n", m1); \ + if (b##_end_block < b##_start_block) \ + printf("Invalid start/end block # for %s\n", m2); \ + if (chk_overlap(a, b)) { \ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \ - m1, a##_start_block, a##_end_block, \ - m2, b##_start_block, b##_end_block); \ - return -EINVAL; \ - } \ + m1, a##_start_block, a##_end_block, \ + m2, b##_start_block, b##_end_block); \ + return -EINVAL; \ + } \ } while (0) static int tx6_prog_uboot(void *addr, int start_block, int skip, @@ -421,25 +404,28 @@ static int tx6_prog_uboot(void *addr, int start_block, int skip, printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, erase_opts.offset + erase_opts.length - 1); - ret = nand_erase_opts(mtd, &erase_opts); - if (ret) { - printf("Failed to erase flash: %d\n", ret); - return ret; + if (doit) { + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } } - printf("Programming flash @ %08llx..%08llx from %p\n", - (u64)start_block * mtd->erasesize, - (u64)start_block * mtd->erasesize + size - 1, addr); - actual = size; - ret = nand_write_skip_bad(mtd, prg_start, &actual, NULL, - prg_length, addr, WITH_DROP_FFS); - if (ret) { - printf("Failed to program flash: %d\n", ret); - return ret; - } - if (actual < size) { - printf("Could only write %u of %u bytes\n", actual, size); - return -EIO; + printf("Programming flash @ %08x..%08x from %p\n", + prg_start, prg_start + size - 1, addr); + if (doit) { + actual = size; + ret = nand_write_skip_bad(mtd, prg_start, &actual, NULL, + prg_length, addr, WITH_DROP_FFS); + if (ret) { + printf("Failed to program flash: %d\n", ret); + return ret; + } + if (actual < size) { + printf("Could only write %u of %u bytes\n", actual, size); + return -EIO; + } } return 0; } @@ -457,7 +443,6 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) int ret; const unsigned long fcb_start_block = 0, fcb_end_block = 0; int erase_size = mtd->erasesize; - int page_size = mtd->writesize; void *buf; char *load_addr; char *file_size; @@ -490,6 +475,7 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (ret) return ret; + doit = true; for (optind = 1; optind < argc; optind++) { char *endp; @@ -542,6 +528,8 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) mtd_num_blocks - 1); return -EINVAL; } + } else if (strcmp(argv[optind], "-n") == 0) { + doit = false; } else if (argv[optind][0] == '-') { printf("Unrecognized option %s\n", argv[optind]); return -EINVAL; @@ -558,7 +546,14 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) return -EINVAL; } if (argc - optind < 2 && file_size == NULL) { - printf("WARNING: Image size not specified; overwriting whole uboot partition\n"); + if (uboot_part) { + printf("WARNING: Image size not specified; overwriting whole '%s' partition\n", + uboot_part); + printf("This will only work, if there are no bad blocks inside this partition!\n"); + } else { + printf("ERROR: Image size must be specified\n"); + return -EINVAL; + } } if (argc > optind) { load_addr = NULL; @@ -578,13 +573,10 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) size = simple_strtoul(file_size, NULL, 16); printf("Using default file size %08x\n", size); } - if (size > 0) { + if (size > 0) fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize); - } else { - fw_num_blocks = part_info->size / mtd->erasesize - - extra_blocks; - size = fw_num_blocks * mtd->erasesize; - } + else + fw_num_blocks = 0; if (uboot_part) { ret = find_dev_and_part(uboot_part, &dev, &part_num, @@ -596,6 +588,8 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } fw1_start_block = part_info->offset / mtd->erasesize; max_len1 = part_info->size; + if (size == 0) + fw_num_blocks = max_len1 / mtd->erasesize; } else { max_len1 = (fw_num_blocks + extra_blocks) * mtd->erasesize; } @@ -610,6 +604,12 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } fw2_start_block = redund_part_info->offset / mtd->erasesize; max_len2 = redund_part_info->size; + if (fw2_start_block == fcb_start_block) { + fw2_start_block++; + max_len2 -= mtd->erasesize; + } + if (size == 0) + fw_num_blocks = max_len2 / mtd->erasesize; } else if (fw2_set) { max_len2 = (fw_num_blocks + extra_blocks) * mtd->erasesize; } else { @@ -619,8 +619,9 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fw1_skip = find_contig_space(fw1_start_block, fw_num_blocks, max_len1 / mtd->erasesize); if (fw1_skip < 0) { - printf("Could not find %lu contiguous good blocks for fw image\n", - fw_num_blocks); + printf("Could not find %lu contiguous good blocks for fw image in blocks %lu..%lu\n", + fw_num_blocks, fw1_start_block, + fw1_start_block + max_len1 / mtd->erasesize - 1); if (uboot_part) { #ifdef CONFIG_ENV_IS_IN_NAND if (part_info->offset <= CONFIG_ENV_OFFSET + TOTAL_ENV_SIZE) { @@ -638,7 +639,10 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } return -ENOSPC; } - fw1_end_block = fw1_start_block + fw1_skip + fw_num_blocks - 1; + if (extra_blocks) + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + else + fw1_end_block = fw1_start_block + fw_num_blocks + fw1_skip - 1; if (fw2_set && fw2_start_block == 0) fw2_start_block = fw1_end_block + 1; @@ -646,8 +650,9 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fw2_skip = find_contig_space(fw2_start_block, fw_num_blocks, max_len2 / mtd->erasesize); if (fw2_skip < 0) { - printf("Could not find %lu contiguous good blocks for redundant fw image\n", - fw_num_blocks); + printf("Could not find %lu contiguous good blocks for redundant fw image in blocks %lu..%lu\n", + fw_num_blocks, fw2_start_block, + fw2_start_block + max_len2 / mtd->erasesize - 1); if (redund_part) { printf("Increase the size of the '%s' partition or use a different partition\n", redund_part); @@ -659,7 +664,10 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } else { fw2_skip = 0; } - fw2_end_block = fw2_start_block + fw2_skip + fw_num_blocks - 1; + if (extra_blocks) + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + else + fw2_end_block = fw2_start_block + fw_num_blocks + fw2_skip - 1; #ifdef CONFIG_ENV_IS_IN_NAND fail_if_overlap(fcb, env, "FCB", "Environment"); @@ -673,53 +681,44 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) #endif fail_if_overlap(fw1, fw2, "FW1", "FW2"); } + fw1_start_block += fw1_skip; + fw2_start_block += fw2_skip; - buf = malloc(erase_size); + buf = memalign(SZ_128K, erase_size); if (buf == NULL) { printf("Failed to allocate buffer\n"); return -ENOMEM; } - fcb = create_fcb(buf, fw1_start_block + fw1_skip, - fw2_start_block + fw2_skip, fw_num_blocks); + fcb = create_fcb(buf, fw1_start_block, + fw2_start_block, fw_num_blocks); if (IS_ERR(fcb)) { printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); - free(buf); - return PTR_ERR(fcb); + ret = PTR_ERR(fcb); + goto out; } encode_hamming_13_8(fcb, (void *)fcb + 512, 512); ret = write_fcb(buf, fcb_start_block); - free(buf); if (ret) { printf("Failed to write FCB to block %lu\n", fcb_start_block); return ret; } - ret = patch_ivt(addr, size); - if (ret) { - return ret; - } - - if (size & (page_size - 1)) { - memset(addr + size, 0xff, size & (page_size - 1)); - size = ALIGN(size, page_size); - } printf("Programming U-Boot image from %p to block %lu @ %08llx\n", - addr, fw1_start_block + fw1_skip, - (u64)(fw1_start_block + fw1_skip) * mtd->erasesize); + buf, fw1_start_block, (u64)fw1_start_block * mtd->erasesize); ret = tx6_prog_uboot(addr, fw1_start_block, fw1_skip, size, max_len1); - if (fw2_start_block == 0) { - return ret; - } + if (ret || fw2_start_block == 0) + goto out; printf("Programming redundant U-Boot image to block %lu @ %08llx\n", - fw2_start_block + fw2_skip, - (u64)(fw2_start_block + fw2_skip) * mtd->erasesize); - ret = tx6_prog_uboot(addr, fw2_start_block, fw2_skip, fw_num_blocks, + fw2_start_block, (u64)fw2_start_block * mtd->erasesize); + ret = tx6_prog_uboot(addr, fw2_start_block, fw2_skip, size, max_len2); +out: + free(buf); return ret; } @@ -727,12 +726,13 @@ U_BOOT_CMD(romupdate, 11, 0, do_update, "Creates an FCB data structure and writes an U-Boot image to flash", "[-f {|block#}] [-r [{|block#}]] [-e #] [
] []\n" "\t-f \twrite bootloader image to partition \n" - "\t-f #\twrite bootloader image at block # (decimal)\n" - "\t-r\twrite redundant bootloader image at next free block after first image\n" + "\t-f #\t\twrite bootloader image at block # (decimal)\n" + "\t-r\t\twrite redundant bootloader image at next free block after first image\n" "\t-r \twrite redundant bootloader image to partition \n" - "\t-r #\twrite redundant bootloader image at block # (decimal)\n" - "\t-e #\tspecify number of redundant blocks per boot loader image\n" - "\t\tonly valid if -f or -r specify a flash address rather than a partition name\n" - "\t
\tRAM address of bootloader image (default: ${fileaddr}\n" - "\t\tlength of bootloader image in RAM (default: ${filesize}" + "\t-r #\t\twrite redundant bootloader image at block # (decimal)\n" + "\t-e #\t\tspecify number of redundant blocks per boot loader image\n" + "\t\t\t(only valid if -f or -r specify a flash address rather than a partition name)\n" + "\t-n\t\tshow what would be done without actually updating the flash\n" + "\t
\tRAM address of bootloader image (default: ${fileaddr})\n" + "\t\tlength of bootloader image in RAM (default: ${filesize})" ); diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index 3161c227f3..561a1d1457 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -1,5 +1,7 @@ #include +#include #include +#include #include #include @@ -87,6 +89,8 @@ dcd_start: .error "DCD too large!" .endif dcd_end: + .section ".pad" + .section ".text" .endm #define MXC_DCD_CMD_WRT(type, flags) \ @@ -107,6 +111,7 @@ dcd_end: #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) +#define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000) .macro CK_VAL, name, clks, offs, max .iflt \clks - \offs @@ -157,7 +162,7 @@ dcd_end: #define ADDR_MIRROR 0 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3 -/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */ +/* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */ #if SDRAM_CLK > 666 && SDRAM_CLK <= 800 #define CL_VAL 11 #define CWL_VAL 8 @@ -180,26 +185,26 @@ dcd_end: /* MDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ -CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ -CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ -NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */ +CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */ CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ /* MDCFG1 0x10 */ -CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ -CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ -NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ -CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */ +CK_VAL tRCD, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */ +CK_VAL tRP, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */ +NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */ +CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */ CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ /* MDCFG2 0x14 */ -CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ /* (Jedec Standard) */ CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ -CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */ +CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */ /* MDOR 0x30 */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ @@ -207,8 +212,8 @@ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) m #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) /* MDOTC 0x08 */ -CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ -CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ +CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */ +CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */ CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */ @@ -313,11 +318,14 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 ((PHYS_SDRAM_1_WIDTH / 32) << 16) | \ ((-1) << (32 - BANK_ADDR_BITS))) +#define MDMISC_WALAT(n) (((n) & 3) << 16) +#define MDMISC_RALAT(n) (((n) & 7) << 6) + #define MDMISC_VAL ((ADDR_MIRROR << 19) | \ - (WALAT << 16) | \ + MDMISC_WALAT(WALAT) | \ (BI_ON << 12) | \ (0x3 << 9) | \ - (RALAT << 6) | \ + MDMISC_RALAT(RALAT) | \ (DDR_TYPE << 3)) #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) @@ -329,6 +337,7 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (tODTLon << 12) | \ (tODTLoff << 4)) + .section ".ivt" ivt_header: .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) app_start_addr: @@ -341,12 +350,16 @@ boot_data_ptr: self_ptr: .word ivt_header app_code_csf: +#ifdef CONFIG_SECURE_BOOT + .word __csf_data +#else .word 0x0 +#endif .word 0x0 boot_data: - .long _start + .long CONFIG_SYS_TEXT_BASE image_len: - .long CONFIG_U_BOOT_IMG_SIZE + .long __uboot_img_len plugin: .word 0 ivt_end: @@ -399,7 +412,9 @@ ivt_end: #define MMDC1_MDRWD 0x021b002c #define MMDC1_MDOR 0x021b0030 #define MMDC1_MDASP 0x021b0040 + #define MMDC1_MAPSR 0x021b0404 + #define MMDC1_MPZQHWCTRL 0x021b0800 #define MMDC1_MPWLGCR 0x021b0808 #define MMDC1_MPWLDECTRL0 0x021b080c @@ -432,6 +447,7 @@ ivt_end: #if PHYS_SDRAM_1_WIDTH == 64 #define MMDC2_MDPDC 0x021b4004 + #define MMDC2_MPWLGCR 0x021b4808 #define MMDC2_MPWLDECTRL0 0x021b480c #define MMDC2_MPWLDECTRL1 0x021b4810 @@ -468,15 +484,21 @@ ivt_end: #define MMDC2_MPSWDRDR5 0x021b48ac #define MMDC2_MPSWDRDR6 0x021b48b0 #define MMDC2_MPSWDRDR7 0x021b48b4 +#define MMDC2_MPMUR0 0x021b48b8 #endif -#ifdef CONFIG_MX6Q +#ifdef CONFIG_SOC_MX6Q #define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e00a0 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x020e0248 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e02ac #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e02c0 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e02c4 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x020e02c8 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e02d4 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e02d8 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02dc @@ -493,6 +515,10 @@ ivt_end: #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0310 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0314 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e0318 + +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x020e03b4 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e050c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0514 @@ -537,6 +563,9 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e05bc #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e05c0 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e05c4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x020e0618 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x020e061c +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x020e06b0 #define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750 @@ -561,17 +590,27 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8 + #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920 + +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c +#define TX6_I2C1_SEL_INP_VAL 1 #endif -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) #define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e0154 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x020e0214 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e032c #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e0314 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e0318 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x020e031c #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e0270 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e026c #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02a8 @@ -588,6 +627,10 @@ ivt_end: #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0298 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e029c #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e02a0 + +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x020e0524 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e04d0 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0484 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0480 @@ -632,6 +675,9 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e0488 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e04d8 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e048c +#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x020e05e4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x020e05e8 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x020e0704 #define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750 @@ -648,15 +694,37 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8 + #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e08f8 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e08fc + +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c +#define TX6_I2C1_SEL_INP_VAL 1 #endif dcd_hdr: MXC_DCD_START MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + /* setup I2C pads for PMIC */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, 0x00000016) + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, 0x00000011) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, 0x0000f079) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, 0x0000f079) + MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL) + MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL) + + /* ENET_REF_CLK */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO16, 0x00000012) + /* ETN PHY nRST */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, 0x00000015) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, 0x000030b0) + /* ETN PHY Power */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, 0x00000015) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, 0x000030b0) /* RESET_OUT GPIO_7_12 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */ @@ -681,7 +749,7 @@ dcd_hdr: /* UART1 pad config */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */ -#ifdef CONFIG_MX6Q +#ifdef CONFIG_SOC_MX6Q MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */ #else MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002) /* UART1 RXD INPUT_SEL */ @@ -782,7 +850,7 @@ dcd_hdr: /* DDRHYS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000) -#ifdef CONFIG_MX6Q +#ifdef CONFIG_SOC_MX6Q /* TERM_CTL[0..7] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK) @@ -815,7 +883,11 @@ dcd_hdr: /* MDCTL */ MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000) +#if BANK_ADDR_BITS > 1 + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (3 << 30)) +#else + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (1 << 30)) +#endif MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL) @@ -825,7 +897,6 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL) MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL) MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0) - MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0) MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* CS0 MRS: */ @@ -849,7 +920,7 @@ dcd_hdr: /* DDR3 calibration */ MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */ - MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001007) + MXC_DCD_ITEM(MMDC1_MAPSR, 1) /* ZQ calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */ @@ -871,6 +942,10 @@ dcd_hdr: #define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0) #define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0) /* Write leveling */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_RALAT(~0) | MDMISC_WALAT(~0)) /* increase WALAT/RALAT to max. */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0)) MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0)) @@ -893,30 +968,28 @@ dcd_hdr: MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ +#define MPMUR_FRC_MSR (1 << 11) + MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) #ifdef DO_DDR_CALIB - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, (1 << 30) | (1 << 28) | (0 << 23)) /* choose 32 wait cycles and start DQS calib. */ + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_ANY_CLR, MMDC1_MPDGCTRL0, 0x10001000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) #else /* DO_DDR_CALIB */ -#define MPMUR_FRC_MSR (1 << 11) MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160) MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f) MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150) MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a) + MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) #endif /* DO_DDR_CALIB */ + MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) /* DRAM_SDQS[0..7] pad config */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK) @@ -957,6 +1030,7 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f) MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f) MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) #endif /* DO_DDR_CALIB */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ #if BANK_ADDR_BITS > 1 @@ -964,9 +1038,8 @@ dcd_hdr: #endif MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b) MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */ - MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006) + MXC_DCD_ITEM(MMDC1_MAPSR, (16 << 8)) MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1) - MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1) /* MDSCR: Normal operation */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000) diff --git a/board/karo/tx6/ltc3676.c b/board/karo/tx6/ltc3676.c index c659bc8114..3f692d3fd6 100644 --- a/board/karo/tx6/ltc3676.c +++ b/board/karo/tx6/ltc3676.c @@ -18,7 +18,9 @@ #include #include #include +#include +#include "../common/karo.h" #include "pmic.h" #define LTC3676_BUCK1 0x01 diff --git a/board/karo/tx6/pmic.c b/board/karo/tx6/pmic.c index 2743dadd32..a29a74bd17 100644 --- a/board/karo/tx6/pmic.c +++ b/board/karo/tx6/pmic.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. * */ - #include #include #include @@ -36,15 +35,23 @@ static struct { #endif }; -int tx6_pmic_init(void) +int tx6_pmic_init(int addr) { int ret = -ENODEV; int i; + debug("Probing for I2C dev 0x%02x\n", addr); for (i = 0; i < ARRAY_SIZE(i2c_addrs); i++) { - ret = i2c_probe(i2c_addrs[i].addr); + u8 i2c_addr = i2c_addrs[i].addr; + + if (i2c_addr != addr) + continue; + + debug("Probing for I2C dev 0x%02x\n", i2c_addr); + ret = i2c_probe(i2c_addr); if (ret == 0) { - i2c_addrs[i].init(i2c_addrs[i].addr); + debug("Initializing PMIC at I2C addr 0x%02x\n", i2c_addr); + ret = i2c_addrs[i].init(i2c_addr); break; } } diff --git a/board/karo/tx6/pmic.h b/board/karo/tx6/pmic.h index 4786eefc9b..1b301b7c4a 100644 --- a/board/karo/tx6/pmic.h +++ b/board/karo/tx6/pmic.h @@ -19,4 +19,4 @@ int ltc3676_pmic_setup(uchar addr); int rn5t618_pmic_setup(uchar addr); int rn5t567_pmic_setup(uchar addr); -int tx6_pmic_init(void); +int tx6_pmic_init(int addr); diff --git a/board/karo/tx6/rn5t567.c b/board/karo/tx6/rn5t567.c index 6f791374b4..913dd2c274 100644 --- a/board/karo/tx6/rn5t567.c +++ b/board/karo/tx6/rn5t567.c @@ -18,6 +18,7 @@ #include #include +#include "../common/karo.h" #include "pmic.h" #define RN5T567_NOETIMSET 0x11 diff --git a/board/karo/tx6/rn5t618.c b/board/karo/tx6/rn5t618.c index 19aba871af..8737e767f0 100644 --- a/board/karo/tx6/rn5t618.c +++ b/board/karo/tx6/rn5t618.c @@ -18,6 +18,7 @@ #include #include +#include "../common/karo.h" #include "pmic.h" #define RN5T618_NOETIMSET 0x11 diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c index 4f35fd7770..1d09de4ac6 100644 --- a/board/karo/tx6/tx6qdl.c +++ b/board/karo/tx6/tx6qdl.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,8 @@ #include "../common/karo.h" #include "pmic.h" +#define __data __attribute__((section(".data"))) + #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6) #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1) @@ -48,6 +51,8 @@ #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) +#define TX6_I2C1_SCL_GPIO IMX_GPIO_NR(3, 21) +#define TX6_I2C1_SDA_GPIO IMX_GPIO_NR(3, 28) #ifdef CONFIG_MX6_TEMPERATURE_MIN #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN @@ -64,76 +69,77 @@ DECLARE_GLOBAL_DATA_PTR; #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) -static const iomux_v3_cfg_t tx6qdl_pads[] = { -#ifndef CONFIG_NO_NAND - /* NAND flash pads */ - MX6_PAD_NANDF_CLE__RAWNAND_CLE, - MX6_PAD_NANDF_ALE__RAWNAND_ALE, - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN, - MX6_PAD_NANDF_RB0__RAWNAND_READY0, - MX6_PAD_NANDF_CS0__RAWNAND_CE0N, - MX6_PAD_SD4_CMD__RAWNAND_RDN, - MX6_PAD_SD4_CLK__RAWNAND_WRN, - MX6_PAD_NANDF_D0__RAWNAND_D0, - MX6_PAD_NANDF_D1__RAWNAND_D1, - MX6_PAD_NANDF_D2__RAWNAND_D2, - MX6_PAD_NANDF_D3__RAWNAND_D3, - MX6_PAD_NANDF_D4__RAWNAND_D4, - MX6_PAD_NANDF_D5__RAWNAND_D5, - MX6_PAD_NANDF_D6__RAWNAND_D6, - MX6_PAD_NANDF_D7__RAWNAND_D7, +enum { + MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0) +}; + +char __uboot_img_end[0] __attribute__((section(".__uboot_img_end"))); +#ifdef CONFIG_SECURE_BOOT +char __csf_data[0] __attribute__((section(".__csf_data"))); #endif + +static const iomux_v3_cfg_t const tx6qdl_pads[] = { /* RESET_OUT */ - MX6_PAD_GPIO_17__GPIO_7_12, + MX6_PAD_GPIO_17__GPIO7_IO12, /* UART pads */ #if CONFIG_MXC_UART_BASE == UART1_BASE - MX6_PAD_SD3_DAT7__UART1_TXD, - MX6_PAD_SD3_DAT6__UART1_RXD, - MX6_PAD_SD3_DAT1__UART1_RTS, - MX6_PAD_SD3_DAT0__UART1_CTS, + MX6_PAD_SD3_DAT7__UART1_TX_DATA, + MX6_PAD_SD3_DAT6__UART1_RX_DATA, + MX6_PAD_SD3_DAT1__UART1_RTS_B, + MX6_PAD_SD3_DAT0__UART1_CTS_B, #endif #if CONFIG_MXC_UART_BASE == UART2_BASE - MX6_PAD_SD4_DAT4__UART2_RXD, - MX6_PAD_SD4_DAT7__UART2_TXD, - MX6_PAD_SD4_DAT5__UART2_RTS, - MX6_PAD_SD4_DAT6__UART2_CTS, + MX6_PAD_SD4_DAT4__UART2_RX_DATA, + MX6_PAD_SD4_DAT7__UART2_TX_DATA, + MX6_PAD_SD4_DAT5__UART2_RTS_B, + MX6_PAD_SD4_DAT6__UART2_CTS_B, #endif #if CONFIG_MXC_UART_BASE == UART3_BASE - MX6_PAD_EIM_D24__UART3_TXD, - MX6_PAD_EIM_D25__UART3_RXD, - MX6_PAD_SD3_RST__UART3_RTS, - MX6_PAD_SD3_DAT3__UART3_CTS, + MX6_PAD_EIM_D24__UART3_TX_DATA, + MX6_PAD_EIM_D25__UART3_RX_DATA, + MX6_PAD_SD3_RST__UART3_RTS_B, + MX6_PAD_SD3_DAT3__UART3_CTS_B, #endif /* internal I2C */ MX6_PAD_EIM_D28__I2C1_SDA, MX6_PAD_EIM_D21__I2C1_SCL, /* FEC PHY GPIO functions */ - MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */ - MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */ - MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */ + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */ + MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */ + MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */ }; -static const iomux_v3_cfg_t tx6qdl_fec_pads[] = { +static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = { /* FEC functions */ MX6_PAD_ENET_MDC__ENET_MDC, MX6_PAD_ENET_MDIO__ENET_MDIO, - MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, + MX6_PAD_GPIO_16__ENET_REF_CLK, MX6_PAD_ENET_RX_ER__ENET_RX_ER, MX6_PAD_ENET_CRS_DV__ENET_RX_EN, - MX6_PAD_ENET_RXD1__ENET_RDATA_1, - MX6_PAD_ENET_RXD0__ENET_RDATA_0, + MX6_PAD_ENET_RXD1__ENET_RX_DATA1, + MX6_PAD_ENET_RXD0__ENET_RX_DATA0, MX6_PAD_ENET_TX_EN__ENET_TX_EN, - MX6_PAD_ENET_TXD1__ENET_TDATA_1, - MX6_PAD_ENET_TXD0__ENET_TDATA_0, + MX6_PAD_ENET_TXD1__ENET_TX_DATA1, + MX6_PAD_ENET_TXD0__ENET_TX_DATA0, }; -static const struct gpio tx6qdl_gpios[] = { - { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, - { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, - { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, - { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, +static const iomux_v3_cfg_t const tx6_i2c_pads[] = { + /* internal I2C */ + MX6_PAD_EIM_D28__I2C1_SDA, + MX6_PAD_EIM_D21__I2C1_SCL, +}; + +static const struct gpio const tx6qdl_gpios[] = { + /* These two entries are used to forcefully reinitialize the I2C bus */ + { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", }, + { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", }, + + { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", }, + { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, + { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", }, + { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, }; /* @@ -200,7 +206,7 @@ static void print_reset_cause(void) printf("\n"); } -static const char *tx6_mod_suffix; +static const char __data *tx6_mod_suffix; static void tx6qdl_print_cpuinfo(void) { @@ -240,9 +246,6 @@ static void tx6qdl_print_cpuinfo(void) int board_early_init_f(void) { - gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios)); - imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads)); - return 0; } @@ -251,11 +254,162 @@ static bool tx6_temp_check_enabled = true; #else #define tx6_temp_check_enabled 0 #endif +static int pmic_addr __data; + +#if defined(CONFIG_SOC_MX6Q) +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c +#define I2C1_SEL_INPUT_VAL 0 +#endif +#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c +#define I2C1_SEL_INPUT_VAL 1 +#endif + +#define GPIO_DR 0 +#define GPIO_DIR 4 +#define GPIO_PSR 8 + +static const struct i2c_gpio_regs { + const char *label; + u32 gpio; + unsigned long gpio_base; + unsigned long muxctl; + unsigned long padctl; + unsigned long sel_input; +} tx6_i2c_iomux_regs[] = { + { + .label = "PMIC SCL", + .gpio = TX6_I2C1_SCL_GPIO, + .gpio_base = GPIO3_BASE_ADDR, + .muxctl = IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, + .padctl = IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, + .sel_input = IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, + }, { + .label = "PMIC SDA", + .gpio = TX6_I2C1_SDA_GPIO, + .gpio_base = GPIO3_BASE_ADDR, + .muxctl = IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, + .padctl = IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, + .sel_input = IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, + }, +}; + +static inline u32 __tx6_readl(void *addr, + const char *fn, int ln) +{ + u32 val = readl(addr); + debug("%s@%d: read %08x from %p\n", fn, ln, val, addr); + return val; +} +#undef readl +#define readl(a) __tx6_readl((void *)(a), __func__, __LINE__) + +static inline void __tx6_writel(u32 val, void *addr, + const char *fn, int ln) +{ + debug("%s@%d: writing %08x to %p\n", fn, ln, val, addr); + writel(val, addr); +} +#undef writel +#define writel(v, a) __tx6_writel(v, (void *)(a), __func__, __LINE__) + +static void tx6_i2c_recover(void) +{ + int i; + int bad = 0; + int failed = 0; +#define MAX_TRIES 100 + + debug("Clearing I2C bus\n"); + + for (i = 0; i < ARRAY_SIZE(tx6_i2c_iomux_regs); i++) { + int gpio = tx6_i2c_iomux_regs[i].gpio; + u32 gpio_mask = 1 << (gpio % 32); + + void *gpio_base = (void *)tx6_i2c_iomux_regs[i].gpio_base; + + if ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0) { + int retries = MAX_TRIES; + + bad++; + printf("%s (GPIO%u_%u) is not HIGH\n", + tx6_i2c_iomux_regs[i].label, + gpio / 32 + 1, gpio % 32); + writel(readl(gpio_base + GPIO_DR) | gpio_mask, + gpio_base + GPIO_DR); + writel(readl(gpio_base + GPIO_DIR) | gpio_mask, + gpio_base + GPIO_DIR); + writel(0x15, tx6_i2c_iomux_regs[i].muxctl); + writel(0x0f079, tx6_i2c_iomux_regs[i].padctl); + writel(I2C1_SEL_INPUT_VAL, tx6_i2c_iomux_regs[i].sel_input); + if ((readl(gpio_base + GPIO_DR) & gpio_mask) == 0) + hang(); + if ((readl(gpio_base + GPIO_DIR) & gpio_mask) == 0) + hang(); + while ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0 && + retries-- > 0) { + udelay(100); + } + writel(readl(gpio_base + GPIO_DIR) & ~gpio_mask, + gpio_base + GPIO_DIR); + + if ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0) { + printf("Failed to force %s (GPIO%u_%u) HIGH\n", + tx6_i2c_iomux_regs[i].label, + gpio / 32 + 1, gpio % 32); + failed++; + } else if (retries < MAX_TRIES) { + printf("%s (GPIO%u_%u) forced HIGH after %u loops\n", + tx6_i2c_iomux_regs[i].label, + gpio / 32 + 1, gpio % 32, + MAX_TRIES - retries); + } + } else { + debug("%s (GPIO%u_%u) is HIGH\n", + tx6_i2c_iomux_regs[i].label, + gpio / 32 + 1, gpio % 32); + } + } + debug("Setting up I2C Pads\n"); + imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads, + ARRAY_SIZE(tx6_i2c_pads)); + if (bad) { + if (failed) + printf("I2C bus recovery FAILED\n"); + else + printf("I2C bus recovery succeeded\n"); + } +} + +#define pr_reg(b, n) debug("%12s@%p=%08x\n", #n, (void *)(b) + (n), readl((b) + (n))) + +static inline void dump_regs(void) +{ + pr_reg(GPIO3_BASE_ADDR, GPIO_DR); + pr_reg(GPIO3_BASE_ADDR, GPIO_DIR); + pr_reg(GPIO3_BASE_ADDR, GPIO_PSR); +} int board_init(void) { int ret; + ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios)); + if (ret < 0) { + printf("Failed to request tx6qdl_gpios: %d\n", ret); + } + imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads)); + /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; gd->bd->bi_arch_number = -1; @@ -268,12 +422,12 @@ int board_init(void) #ifndef CONFIG_MX6_TEMPERATURE_HOT tx6_temp_check_enabled = false; #endif - return 1; + return 0; } - ret = tx6_pmic_init(); + ret = tx6_pmic_init(pmic_addr); if (ret) { - printf("Failed to setup PMIC voltages\n"); + printf("Failed to setup PMIC voltages: %d\n", ret); hang(); } return 0; @@ -283,7 +437,7 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); + PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS); return 0; } @@ -299,43 +453,44 @@ void dram_init_banksize(void) #endif } -#ifdef CONFIG_CMD_MMC -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ +#ifdef CONFIG_FSL_ESDHC +#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST) static const iomux_v3_cfg_t mmc0_pads[] = { - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), /* SD1 CD */ - MX6_PAD_SD3_CMD__GPIO_7_2, + MX6_PAD_SD3_CMD__GPIO7_IO02, }; static const iomux_v3_cfg_t mmc1_pads[] = { - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), /* SD2 CD */ - MX6_PAD_SD3_CLK__GPIO_7_3, + MX6_PAD_SD3_CLK__GPIO7_IO03, }; -#ifdef CONFIG_MMC_BOOT_SIZE +#ifdef CONFIG_TX6_EMMC static const iomux_v3_cfg_t mmc3_pads[] = { - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), /* eMMC RESET */ - MX6_PAD_NANDF_ALE__USDHC4_RST, + MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | + PAD_CTL_DSE_40ohm), }; #endif @@ -346,7 +501,7 @@ static struct tx6_esdhc_cfg { struct fsl_esdhc_cfg cfg; int cd_gpio; } tx6qdl_esdhc_cfg[] = { -#ifdef CONFIG_MMC_BOOT_SIZE +#ifdef CONFIG_TX6_EMMC { .pads = mmc3_pads, .num_pads = ARRAY_SIZE(mmc3_pads), @@ -413,7 +568,7 @@ int board_mmc_init(bd_t *bis) if (cfg->cd_gpio >= 0) { ret = gpio_request_one(cfg->cd_gpio, - GPIOF_INPUT, "MMC CD"); + GPIOFLAG_INPUT, "MMC CD"); if (ret) { printf("Error %d requesting GPIO%d_%d\n", ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); @@ -452,7 +607,8 @@ int board_eth_init(bd_t *bis) /* delay at least 21ms for the PHY internal POR signal to deassert */ udelay(22000); - imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads)); + imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, + ARRAY_SIZE(tx6qdl_fec_pads)); /* Deassert RESET to the external phy */ gpio_set_value(TX6_FEC_RST_GPIO, 1); @@ -463,6 +619,24 @@ int board_eth_init(bd_t *bis) return ret; } + +static void tx6_init_mac(void) +{ + u8 mac[ETH_ALEN]; + + imx_get_mac_from_fuse(-1, mac); + if (!is_valid_ether_addr(mac)) { + printf("No valid MAC address programmed\n"); + return; + } + + printf("MAC addr from fuse: %pM\n", mac); + eth_setenv_enetaddr("ethaddr", mac); +} +#else +static inline void tx6_init_mac(void) +{ +} #endif /* CONFIG_FEC_MXC */ enum { @@ -508,37 +682,37 @@ void show_activity(int arg) static const iomux_v3_cfg_t stk5_pads[] = { /* SW controlled LED on STK5 baseboard */ - MX6_PAD_EIM_A18__GPIO_2_20, + MX6_PAD_EIM_A18__GPIO2_IO20, /* I2C bus on DIMM pins 40/41 */ MX6_PAD_GPIO_6__I2C3_SDA, MX6_PAD_GPIO_3__I2C3_SCL, /* TSC200x PEN IRQ */ - MX6_PAD_EIM_D26__GPIO_3_26, + MX6_PAD_EIM_D26__GPIO3_IO26, /* EDT-FT5x06 Polytouch panel */ - MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */ - MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */ - MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */ + MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */ + MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */ + MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */ /* USBH1 */ - MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */ - MX6_PAD_EIM_D30__GPIO_3_30, /* OC */ + MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */ + MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */ /* USBOTG */ - MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */ - MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */ - MX6_PAD_GPIO_8__GPIO_1_8, /* OC */ + MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */ + MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */ + MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */ }; static const struct gpio stk5_gpios[] = { - { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, - { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", }, - { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, - { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, - { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, - { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, + { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", }, + { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, + { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", }, + { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, }; #ifdef CONFIG_LCD @@ -548,7 +722,7 @@ vidinfo_t panel_info = { .vl_col = 1920, .vl_row = 1080, - .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ .cmap = tx6_cmap, }; @@ -619,7 +793,6 @@ static struct fb_videomode tx6_fb_modes[] = { .upper_margin = 2, .vsync_len = 10, .lower_margin = 2, - .sync = FB_SYNC_CLK_LAT_FALL, }, { /* Emerging ET0500G0DH6 800 x 480 display. @@ -738,9 +911,9 @@ void lcd_enable(void) */ lcd_is_enabled = 0; - karo_load_splashimage(1); - if (lcd_enabled) { + karo_load_splashimage(1); + debug("Switching LCD on\n"); gpio_set_value(TX6_LCD_PWR_GPIO, 1); udelay(100); @@ -772,49 +945,49 @@ void lcd_panel_disable(void) static const iomux_v3_cfg_t stk5_lcd_pads[] = { /* LCD RESET */ - MX6_PAD_EIM_D29__GPIO_3_29, + MX6_PAD_EIM_D29__GPIO3_IO29, /* LCD POWER_ENABLE */ - MX6_PAD_EIM_EB3__GPIO_2_31, + MX6_PAD_EIM_EB3__GPIO2_IO31, /* LCD Backlight (PWM) */ - MX6_PAD_GPIO_1__GPIO_1_1, + MX6_PAD_GPIO_1__GPIO1_IO01, #ifndef CONFIG_SYS_LVDS_IF /* Display */ - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */ - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */ + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ #endif }; static const struct gpio stk5_lcd_gpios[] = { - { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; void lcd_ctrl_init(void *lcdbase) @@ -972,7 +1145,7 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR16; break; default: - panel_info.vl_bpix = LCD_COLOR24; + panel_info.vl_bpix = LCD_COLOR32; } p->pixclock = KHZ2PICOS(refresh * @@ -1064,7 +1237,13 @@ void lcd_ctrl_init(void *lcdbase) static void stk5_board_init(void) { - gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + int ret; + + ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + if (ret < 0) { + printf("Failed to request stk5_gpios: %d\n", ret); + return; + } imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); } @@ -1075,11 +1254,18 @@ static void stk5v3_board_init(void) static void stk5v5_board_init(void) { + int ret; + stk5_board_init(); - gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, + ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH, "Flexcan Transceiver"); - imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21); + if (ret) { + printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret); + return; + } + + imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21); } static void tx6qdl_set_cpu_clock(void) @@ -1103,24 +1289,17 @@ static void tx6qdl_set_cpu_clock(void) } } -static void tx6_init_mac(void) -{ - u8 mac[ETH_ALEN]; - - imx_get_mac_from_fuse(-1, mac); - if (!is_valid_ether_addr(mac)) { - printf("No valid MAC address programmed\n"); - return; - } - - printf("MAC addr from fuse: %pM\n", mac); - eth_setenv_enetaddr("ethaddr", mac); -} - int board_late_init(void) { int ret = 0; const char *baseboard; +#if 1 + /* override secure_boot fuse */ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs; + + writel(0x12, &fuse->cfg5); +#endif env_cleanup(); @@ -1173,17 +1352,17 @@ exit: return ret; } -#ifdef CONFIG_NO_NAND -#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2) -#else /* CONFIG_NO_NAND */ +#ifdef CONFIG_TX6_NAND #define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1) -#endif /* CONFIG_NO_NAND */ - -#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH -#define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1) #else -#define TX6_DDR_SZ 2 +#ifdef CONFIG_MMC_BOOT_SIZE +#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2) +#else +#define TX6_FLASH_SZ 2 #endif +#endif /* CONFIG_TX6_NAND */ + +#define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1) static char tx6_mem_table[] = { '4', /* 256MiB SDRAM 16bit; 128MiB NAND */ @@ -1222,37 +1401,54 @@ static struct { { 0x33, 3, }, }; -static int tx6_get_mod_rev(void) +static int tx6_get_mod_rev(unsigned int pmic_id) +{ + if (pmic_id < ARRAY_SIZE(tx6_mod_revs)) + return tx6_mod_revs[pmic_id].rev; + + return 0; +} + +static int tx6_pmic_probe(void) { int i; + tx6_i2c_recover(); + i2c_init_all(); + for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) { - int ret = i2c_probe(tx6_mod_revs[i].addr); + u8 i2c_addr = tx6_mod_revs[i].addr; + int ret = i2c_probe(i2c_addr); + if (ret == 0) { - debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr); - return tx6_mod_revs[i].rev; + debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr); + return i; } - debug("I2C probe returned %d for addr %02x\n", ret, - tx6_mod_revs[i].addr); + debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr); } - return 0; + return -EINVAL; } int checkboard(void) { u32 cpurev = get_cpu_rev(); int cpu_variant = (cpurev >> 12) & 0xff; + int pmic_id; tx6qdl_print_cpuinfo(); - i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */); + pmic_id = tx6_pmic_probe(); + if (pmic_id >= 0) + pmic_addr = tx6_mod_revs[pmic_id].addr; printf("Board: Ka-Ro TX6%s-%d%d%d%c\n", tx6_mod_suffix, cpu_variant == MXC_CPU_MX6Q ? 1 : 8, - is_lvds(), tx6_get_mod_rev(), + is_lvds(), tx6_get_mod_rev(pmic_id), tx6_mem_suffix()); + get_hab_status(); + return 0; } @@ -1284,7 +1480,7 @@ static const char *tx6_touchpanels[] = { "eeti,egalax_ts", }; -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { const char *baseboard = getenv("baseboard"); int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); @@ -1292,9 +1488,10 @@ void ft_board_setup(void *blob, bd_t *bd) int ret; ret = fdt_increase_size(blob, 4096); - if (ret) + if (ret) { printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); - + return ret; + } if (stk5_v5) karo_fdt_enable_node(blob, "stk5led", 0); @@ -1307,5 +1504,7 @@ void ft_board_setup(void *blob, bd_t *bd) karo_fdt_fixup_flexcan(blob, stk5_v5); karo_fdt_update_fb_mode(blob, video_mode); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/karo/tx6/u-boot.lds b/board/karo/tx6/u-boot.lds index f845810b28..c4e0e2158c 100644 --- a/board/karo/tx6/u-boot.lds +++ b/board/karo/tx6/u-boot.lds @@ -27,12 +27,17 @@ SECTIONS . = 0x00000000; .text : { + __uboot_img_start = .; + . = 0x400; + __ivt_start = .; + KEEP(*(.ivt*)) + . = 0x1000; + __ivt_end = .; *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) - . = 0x400; - KEEP(board/karo/tx6/lowlevel_init.o (.text*)) *(.text*) - } + } = 0xadde01f0 . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } @@ -40,9 +45,9 @@ SECTIONS . = ALIGN(4); .data : { *(.data*) + . = ALIGN(4); } - . = ALIGN(4); .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } @@ -68,7 +73,28 @@ SECTIONS *(.__rel_dyn_end) } - _end = .; + .pad : + { + *(.pad) + . = ALIGN(4096); + } = 0x01f0adde + + _image_binary_end = . + (__ivt_end - __uboot_img_start); + + .uboot_img_end : + { + KEEP(*(.__uboot_img_end)) + } + +#ifdef CONFIG_SECURE_BOOT + . = CONFIG_SYS_TEXT_BASE + 0x70000; + .csf_data : + { + *(.__csf_data) + . = . + 0x2000; + } +#endif + __uboot_img_len = . - __uboot_img_start; /* * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c @@ -88,13 +114,18 @@ SECTIONS .bss_end __bss_limit (OVERLAY) : { KEEP(*(.__bss_end)); } - - /DISCARD/ : { *(.bss*) } + + .dynsym _image_binary_end : { *(.dynsym) } + /DISCARD/ : { *(.debug*) } + /DISCARD/ : { *(.note*) } + /DISCARD/ : { *(.comment*) } + /DISCARD/ : { *(.dynbss) } /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu.hash) } /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } } diff --git a/board/karo/txa5/Kconfig b/board/karo/txa5/Kconfig new file mode 100644 index 0000000000..5daac1f258 --- /dev/null +++ b/board/karo/txa5/Kconfig @@ -0,0 +1,93 @@ +if TARGET_TXA5 + +config SYS_BOARD + default "txa5" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "txa5" + +config TXA5 + bool + default y + select CC_OPTIMIZE_LIBS_FOR_SPEED + select CMD_BMP if LCD + select CMD_BOOTCE + select CMD_BOOTZ + select CMD_CACHE + select CMD_I2C if I2C + select CMD_MEMINFO + select CMD_MEMTEST + select CMD_MMC + select CMD_TIME + select DM + select DM_GPIO +# select GET_FEC_MAC_ADDR_FROM_IIM +# select IMX_WATCHDOG + select MMC + select OF_LIBFDT + select OF_BOARD_SETUP + select PHYLIB +# select PHY_SMSC +# select SYS_I2C +# select SYS_I2C_MXC + +config TXA5_NAND + bool + select TXA5 + select CMD_NAND + select CMD_NAND_TRIMFFS + select CMD_ROMUPDATE + select ENV_IS_IN_NAND if !TXA5_UBOOT_NOENV + select FDT_FIXUP_PARTITIONS if OF_LIBFDT + select MTD_PARTITIONS + select MTD_DEVICE + select NAND + select NAND_ATMEL + select SYS_NAND_USE_FLASH_BBT + +config TXA5_EMMC + bool + select TXA5 + select SUPPORT_EMMC_BOOT + select ENV_IS_IN_MMC if !TXA5_UBOOT_NOENV + +choice + prompt "TXA5 module variant" + +config TARGET_TXA5_5010 + bool "TXA5-5010 (NAND)" + select TXA5_NAND + +config TARGET_TXA5_5011 + bool "TXA5-5011 (eMMC)" + select TXA5_EMMC + +endchoice + +# +# variables selected depending on module variant +# + +config NR_DRAM_BANKS + int + default 1 + +choice + prompt "U-Boot image variant" + +config TXA5_UBOOT + bool "Standard U-Boot image" + +config TXA5_UBOOT_NOENV + bool "U-Boot using only built-in environment" + select ENV_IS_NOWHERE + +endchoice + +endif diff --git a/board/karo/txa5/MAINTAINERS b/board/karo/txa5/MAINTAINERS new file mode 100644 index 0000000000..decabee994 --- /dev/null +++ b/board/karo/txa5/MAINTAINERS @@ -0,0 +1,7 @@ +Ka-Ro TXA5 SoM +M: Lothar Waßmann +S: Maintained +F: board/karo/txa5/ +F: include/configs/txa5.h +F: configs/txa5-5010_defconfig +F: configs/txa5-5011_defconfig diff --git a/board/karo/txa5/Makefile b/board/karo/txa5/Makefile new file mode 100644 index 0000000000..b9c372cc7d --- /dev/null +++ b/board/karo/txa5/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Lothar Waßmann +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += txa5.o diff --git a/board/karo/txa5/txa5.c b/board/karo/txa5/txa5.c new file mode 100644 index 0000000000..ce40c1cc28 --- /dev/null +++ b/board/karo/txa5/txa5.c @@ -0,0 +1,884 @@ +/* + * Copyright (C) 2015 Lothar Waßmann + * based on: board/atmel/sama5d4_xplained/sama5d4_xplained.c + * Copyright (C) 2014 Atmel Bo Shen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + +#define TXA5_LCD_RST_GPIO GPIO_PIN_PA(25) +#define TXA5_LCD_PWR_GPIO GPIO_PIN_PB(15) +#define TXA5_LCD_BACKLIGHT_GPIO GPIO_PIN_PA(24) + +#define TXA5_ETH_RST_GPIO GPIO_PIN_PD(30) +//#define TXA5_ETH_PWR_GPIO GPIO_PIN_BU(7) +#define TXA5_ETH_INT_GPIO GPIO_PIN_PE(1) + +#define TXA5_LED_GPIO GPIO_PIN_PD(29) + +DECLARE_GLOBAL_DATA_PTR; + +static int wdreset; + +#ifdef CONFIG_NAND_ATMEL +static void txa5_nand_hw_init(void) +{ + struct at91_smc *smc = (void *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ +} +#endif + +static inline void txa5_serial0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTD, 10, 1); /* CTS0 */ + at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART0); +} + +static inline void txa5_serial1_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 14, 1); /* CTS1 */ + at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS1 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART1); +} + +static inline void txa5_serial3_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 5, 1); /* CTS3 */ + at91_set_b_periph(AT91_PIO_PORTE, 24, 0); /* RTS3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void txa5_mci1_hw_init(void) +{ + at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the interanl pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + + /* SD Card Detect */ + at91_set_pio_input(AT91_PIO_PORTE, 6, 1); + at91_set_pio_deglitch(AT91_PIO_PORTE, 6, 1); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI1); +} +#endif + +#ifdef CONFIG_MACB +void txa5_macb0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + + at91_set_pio_input(AT91_PIO_PORTE, 1, 0); /* IRQ */ + at91_set_pio_deglitch(AT91_PIO_PORTE, 1, 1); + + at91_set_pio_output(AT91_PIO_PORTD, 30, 0); /* PHY RESET */ + at91_set_pio_pullup(AT91_PIO_PORTD, 30, 1); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC0); +} +#endif + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + +#ifdef CONFIG_USART_ID +#if CONFIG_USART_ID == ATMEL_ID_USART0 + txa5_serial0_hw_init(); +#elif CONFIG_USART_ID == ATMEL_ID_USART1 + txa5_serial1_hw_init(); +#elif CONFIG_USART_ID == ATMEL_ID_USART3 +#else +#error No console UART defined +#endif + txa5_serial3_hw_init(); +#endif /* CONFIG_USART_ID */ + + return 0; +} + +/* called with default environment! */ +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + txa5_nand_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + txa5_mci1_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif /* CONFIG_GENERIC_ATMEL_MCI */ + +#ifdef CONFIG_MACB +int board_eth_init(bd_t *bis) +{ + int ret; + + txa5_macb0_hw_init(); + + /* delay at least 21ms for the PHY internal POR signal to deassert */ + udelay(22000); + + /* Deassert RESET to the external phy */ + at91_set_gpio_value(TXA5_ETH_RST_GPIO, 1); + + ret = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); + + return ret; +} +#endif + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif +#define MAC_ID0_HI (void *)0xfc060040 +#define MAC_ID0_LO (void *)0xfc060044 + +static void txa5_init_mac(void) +{ + uint8_t mac_addr[ETH_ALEN]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = __raw_readl(MAC_ID0_LO); + mac_hi = __raw_readl(MAC_ID0_HI); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi >> 8) & 0xFF; + mac_addr[2] = (mac_hi >> 16) & 0xFF; + mac_addr[3] = (mac_hi >> 24) & 0xFF; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo >> 8) & 0xFF; + + if (!is_valid_ether_addr(mac_addr)) { + printf("No valid MAC address programmed\n"); + return; + } + printf("MAC addr from fuse: %pM\n", mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + at91_set_gpio_value(TXA5_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + at91_set_gpio_value(TXA5_LED_GPIO, 0); + } else { + at91_set_gpio_value(TXA5_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 2048, + .vl_row = 2048, + .vl_bpix = LCD_COLOR16, + .vl_tft = 1, + .mmio = (void *)ATMEL_BASE_LCDC, +}; + +#define FB_SYNC_OE_LOW_ACT (1 << 31) +#define FB_SYNC_CLK_LAT_FALL (1 << 30) + +static struct fb_videomode txa5_fb_modes[] = { + { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETV570 640 x 480 display. Syncs low active, + * DE high active, 115.2 mm x 86.4 mm display area + * VGA compatible timing + */ + .name = "ETV570", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 114, + .hsync_len = 30, + .right_margin = 16, + .upper_margin = 32, + .vsync_len = 3, + .lower_margin = 10, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0350G0DH6 320 x 240 display. + * 70.08 mm x 52.56 mm display area. + */ + .name = "ET0350", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68 - 34, + .hsync_len = 34, + .right_margin = 20, + .upper_margin = 18 - 3, + .vsync_len = 3, + .lower_margin = 4, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0430G0DH6 480 x 272 display. + * 95.04 mm x 53.856 mm display area. + */ + .name = "ET0430", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = KHZ2PICOS(9000), + .left_margin = 2, + .hsync_len = 41, + .right_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + .lower_margin = 2, + }, + { + /* Emerging ET0500G0DH6 800 x 480 display. + * 109.6 mm x 66.4 mm display area. + */ + .name = "ET0500", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETQ570G0DH6 320 x 240 display. + * 115.2 mm x 86.4 mm display area. + */ + .name = "ETQ570", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 38, + .hsync_len = 30, + .right_margin = 30, + .upper_margin = 16, /* 15 according to datasheet */ + .vsync_len = 3, /* TVP -> 1>x>5 */ + .lower_margin = 4, /* 4.5 according to datasheet */ + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0700G0DH6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET0700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* unnamed entry for assigning parameters parsed from 'video_mode' string */ + .refresh = 60, + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, +}; + +static int lcd_enabled = 1; +static int lcd_bl_polarity; +int lcd_output_bpp; + +static int lcd_backlight_polarity(void) +{ + return lcd_bl_polarity; +} + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + if (lcd_enabled) { + karo_load_splashimage(1); + + debug("Switching LCD on\n"); + at91_set_gpio_value(TXA5_LCD_PWR_GPIO, 1); + udelay(100); + at91_set_gpio_value(TXA5_LCD_RST_GPIO, 1); + udelay(300000); + at91_set_gpio_value(TXA5_LCD_BACKLIGHT_GPIO, + lcd_backlight_polarity()); + } +} + +void lcd_disable(void) +{ +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + debug("Switching LCD off\n"); + at91_set_gpio_value(TXA5_LCD_BACKLIGHT_GPIO, + !lcd_backlight_polarity()); + at91_set_gpio_value(TXA5_LCD_PWR_GPIO, 0); + at91_set_gpio_value(TXA5_LCD_RST_GPIO, 0); + } +} + +static void txa5_lcd_panel_setup(struct fb_videomode *fb) +{ + panel_info.vl_clk = PICOS2KHZ(fb->pixclock) * 1000; + + panel_info.vl_col = fb->xres; + panel_info.vl_left_margin = fb->left_margin; + panel_info.vl_hsync_len = fb->hsync_len; + panel_info.vl_right_margin = fb->right_margin; + + panel_info.vl_row = fb->yres; + panel_info.vl_upper_margin = fb->upper_margin; + panel_info.vl_vsync_len = fb->vsync_len; + panel_info.vl_lower_margin = fb->lower_margin; + + if (!(fb->sync & FB_SYNC_HOR_HIGH_ACT)) + panel_info.vl_sync |= LCDC_LCDCFG5_HSPOL; + if (!(fb->sync & FB_SYNC_VERT_HIGH_ACT)) + panel_info.vl_sync |= LCDC_LCDCFG5_VSPOL; + if (fb->sync & FB_SYNC_OE_LOW_ACT) + panel_info.vl_sync |= LCDC_LCDCFG5_DISPPOL; + + panel_info.vl_clk_pol = !!(fb->sync & FB_SYNC_CLK_LAT_FALL); +} + +static void txa5_lcd_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_set_pio_output(AT91_PIO_PORTA, 25, 0); /* LCD RST */ + at91_set_pio_output(AT91_PIO_PORTB, 15, 0); /* LCD PWR */ + + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf("2015 Ka-Ro electronics GmbH\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; +#ifdef CONFIG_NAND_ATMEL + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; +#endif + lcd_printf("%ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, nand_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ + +unsigned int has_lcdc(void) +{ + int color_depth = 16; + const char *video_mode = karo_get_vmode(getenv("video_mode")); + const char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = &txa5_fb_modes[0]; + struct fb_videomode fb_mode; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + int lcd_bus_width; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return 0; + } + + if (had_ctrlc() || wdreset) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + setenv("splashimage", NULL); + return 0; + } + + karo_fdt_move_fdt(); + + if (video_mode == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return 0; + } + + lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt); + vm = video_mode; + if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) { + p = &fb_mode; + debug("Using video mode from FDT\n"); + vm += strlen(vm); + if (fb_mode.xres > panel_info.vl_col || + fb_mode.yres > panel_info.vl_row) { + printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n", + fb_mode.xres, fb_mode.yres, + panel_info.vl_col, panel_info.vl_row); + lcd_enabled = 0; + return 0; + } + } + if (p->name != NULL) + debug("Trying compiled-in video modes\n"); + while (p->name != NULL) { + if (strcmp(p->name, vm) == 0) { + debug("Using video mode: '%s'\n", p->name); + vm += strlen(vm); + break; + } + p++; + } + if (*vm != '\0') + debug("Trying to decode video_mode: '%s'\n", vm); + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + panel_info.vl_col = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + panel_info.vl_row = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 16: + color_depth = val; + break; + + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (*vm != '\0') + vm++; + } + } + if (p->xres == 0 || p->yres == 0) { + printf("Invalid video mode: %s\n", getenv("video_mode")); + lcd_enabled = 0; + printf("Supported video modes are:"); + for (p = &txa5_fb_modes[0]; p->name != NULL; p++) { + printf(" %s", p->name); + } + printf("\n"); + return 0; + } + if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) { + printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n", + p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); + lcd_enabled = 0; + return 0; + } + panel_info.vl_col = p->xres; + panel_info.vl_row = p->yres; + + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) / + 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); + + if (p != &fb_mode) { + int ret; + + debug("Creating new display-timing node from '%s'\n", + video_mode); + ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p); + if (ret) + printf("Failed to create new display-timing node from '%s': %d\n", + video_mode, ret); + } + + txa5_lcd_hw_init(); + + lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24); + switch (lcd_bus_width) { + case 16: + case 18: + case 24: + lcd_output_bpp = lcd_bus_width; + break; + + default: + lcd_enabled = 0; + printf("Invalid LCD bus width: %d\n", lcd_bus_width); + return 0; + } + if (karo_load_splashimage(0) == 0) { + debug("Initializing FB driver\n"); + txa5_lcd_panel_setup(p); + return 1; + } else { + debug("Skipping initialization of LCD controller\n"); + return 0; + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ +#if 0 + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + txa5_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads)); +#endif +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + +#if 0 + gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios)); + txa5_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads)); +#endif +} + +/* called with environment from NAND or MMC */ +int board_late_init(void) +{ + int ret = 0; + const char *baseboard; + + env_cleanup(); + +// txa5_set_cpu_clock(); + + if (had_ctrlc()) + setenv_ulong("safeboot", 1); +#if 0 + else if (prm_rstst & PRM_RSTST_WDT1_RST) + setenv_ulong("wdreset", 1); +#endif + else + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + goto exit; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + ret = -EINVAL; + } + +exit: + txa5_init_mac(); + clear_ctrlc(); + return ret; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +static struct node_info nodes[] = { + { "atmel,sama5d4-nand", MTD_DEV_TYPE_NAND, }, +}; +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +static const char *txa5_touchpanels[] = { + "ti,tsc2007", + "edt,edt-ft5x06", + "eeti,egalax_ts", +}; + +int ft_board_setup(void *blob, bd_t *bd) +{ + const char *baseboard = getenv("baseboard"); + int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); + const char *video_mode = karo_get_vmode(getenv("video_mode")); + int ret; + + ret = fdt_increase_size(blob, 4096); + if (ret) { + printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); + return ret; + } + if (stk5_v5) + karo_fdt_enable_node(blob, "stk5led", 0); + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob, txa5_touchpanels, + ARRAY_SIZE(txa5_touchpanels)); +// karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply"); +// karo_fdt_fixup_flexcan(blob, stk5_v5); + karo_fdt_update_fb_mode(blob, video_mode); + + return 0; +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 86b81102e9..b9aff1a84d 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include @@ -24,10 +24,6 @@ #include "common.h" #include -#if !defined(CONFIG_MPC83xx) -static void i2c_write_start_seq(void); -#endif - DECLARE_GLOBAL_DATA_PTR; /* @@ -78,7 +74,6 @@ int set_km_env(void) } #if defined(CONFIG_SYS_I2C_INIT_BOARD) -#if !defined(CONFIG_MPC83xx) static void i2c_write_start_seq(void) { set_sda(1); @@ -101,21 +96,6 @@ static void i2c_write_start_seq(void) */ int i2c_make_abort(void) { - -#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; - - /* - * disable I2C controller first, otherwhise it thinks we want to - * talk to the slave port... - */ - clrbits_8(&i2c->i2c_i2mod, 0x01); - - /* Set the PortPins to GPIO */ - setports(1); -#endif - int scl_state = 0; int sda_state = 0; int i = 0; @@ -148,13 +128,8 @@ int i2c_make_abort(void) set_sda(1); get_sda(); -#if defined(CONFIG_HARD_I2C) - /* Set the PortPins back to use for I2C */ - setports(0); -#endif return ret; } -#endif /** * i2c_init_board - reset i2c bus. When the board is powercycled during a @@ -167,6 +142,7 @@ void i2c_init_board(void) } #endif +#if defined(CONFIG_KM_COMMON_ETH_INIT) int board_eth_init(bd_t *bis) { if (ethernet_present()) @@ -174,6 +150,7 @@ int board_eth_init(bd_t *bis) return -1; } +#endif /* * do_setboardid command @@ -226,7 +203,7 @@ U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid", "read out bid and " * application and in the init scripts (?) * return 0 in case of match, 1 if not match or error */ -int do_checkboardidhwk(cmd_tbl_t *cmdtp, int flag, int argc, +static int do_checkboardidhwk(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { unsigned long ivmbid = 0, ivmhwkey = 0; @@ -367,7 +344,7 @@ U_BOOT_CMD(km_checkbidhwk, 2, 0, do_checkboardidhwk, * if the testpin of the board is asserted, return 1 * * else return 0 */ -int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc, +static int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { int testpin = 0; @@ -383,6 +360,7 @@ int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc, testboot = (testpin != 0) && (s); if (verbose) { printf("testpin = %d\n", testpin); + /* cppcheck-suppress nullPointer */ printf("test_bank = %s\n", s ? s : "not set"); printf("boot test app : %s\n", (testboot) ? "yes" : "no"); } diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index aabd3a85b7..b6b19ccb8e 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -6,11 +6,11 @@ */ #include -#include +#include #include #include "common.h" -int ivm_calc_crc(unsigned char *buf, int len) +static int ivm_calc_crc(unsigned char *buf, int len) { const unsigned short crc_tab[16] = { 0x0000, 0xCC01, 0xD801, 0x1400, @@ -120,7 +120,7 @@ static int ivm_findinventorystring(int type, /* Look for the requested number of CR. */ while ((cr != nr) && (addr < INVENTORYDATASIZE)) { - if ((buf[addr] == '\r')) + if (buf[addr] == '\r') cr++; addr++; } @@ -236,7 +236,7 @@ static int ivm_analyze_block2(unsigned char *buf, int len) return 0; } -int ivm_analyze_eeprom(unsigned char *buf, int len) +static int ivm_analyze_eeprom(unsigned char *buf, int len) { unsigned short val; unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; diff --git a/board/keymile/km82xx/Kconfig b/board/keymile/km82xx/Kconfig new file mode 100644 index 0000000000..c9a093ce02 --- /dev/null +++ b/board/keymile/km82xx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KM82XX + +config SYS_BOARD + default "km82xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "km82xx" + +endif diff --git a/board/keymile/km82xx/MAINTAINERS b/board/keymile/km82xx/MAINTAINERS new file mode 100644 index 0000000000..50e06b261c --- /dev/null +++ b/board/keymile/km82xx/MAINTAINERS @@ -0,0 +1,7 @@ +KM82XX BOARD +M: Holger Brunck +S: Maintained +F: board/keymile/km82xx/ +F: include/configs/km82xx.h +F: configs/mgcoge_defconfig +F: configs/mgcoge3ne_defconfig diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile index bc428dff8a..20f193ab1d 100644 --- a/board/keymile/km82xx/Makefile +++ b/board/keymile/km82xx/Makefile @@ -5,27 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o ../common/common.o ../common/ivm.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := km82xx.o ../common/common.o ../common/ivm.o diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index dfbfab8136..bf84676b9b 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -300,11 +300,9 @@ phys_size_t initdram(int board_type) out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT); out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); -#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ psize = probe_sdram(memctl); -#endif /* CONFIG_SYS_RAMBOOT */ icache_enable(); @@ -460,8 +458,10 @@ static void setports(int gpio) } #endif #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig new file mode 100644 index 0000000000..d6c594c96a --- /dev/null +++ b/board/keymile/km83xx/Kconfig @@ -0,0 +1,38 @@ +if TARGET_KM8360 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "km8360" + +endif + +if TARGET_SUVD3 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "suvd3" + +endif + +if TARGET_TUXX1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "tuxx1" + +endif diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS new file mode 100644 index 0000000000..cee7e0898f --- /dev/null +++ b/board/keymile/km83xx/MAINTAINERS @@ -0,0 +1,19 @@ +KM83XX BOARD +M: Holger Brunck +S: Maintained +F: board/keymile/km83xx/ +F: include/configs/km8360.h +F: configs/kmcoge5ne_defconfig +F: configs/kmeter1_defconfig +F: include/configs/tuxx1.h +F: configs/kmopti2_defconfig +F: include/configs/suvd3.h +F: configs/kmvect1_defconfig +F: configs/suvd3_defconfig +F: configs/tuge1_defconfig +F: configs/tuxx1_defconfig + +KMSUPX5 BOARD +M: Heiko Schocher +S: Maintained +F: configs/kmsupx5_defconfig diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile index 073a7838d1..6c3268853e 100644 --- a/board/keymile/km83xx/Makefile +++ b/board/keymile/km83xx/Makefile @@ -5,27 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS += $(BOARD).o ../common/common.o ../common/ivm.o $(BOARD)_i2c.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index cd861c9f12..1da0dcb9d8 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -225,6 +225,11 @@ static struct mv88e_sw_reg extsw_conf[] = { { PORT(5), 0x1A, 0xADB1 }, /* port 6, unused, this port has no phy */ { PORT(6), PORT_CTRL, PORT_DIS }, + /* + * Errata Fix: 1.9V Output from Internal 1.8V Regulator, + * acc . MV-S300889-00D.pdf , clause 4.5 + */ + { PORT(5), 0x1A, 0xADB1 }, }; #endif @@ -277,7 +282,7 @@ int last_stage_init(void) return 0; } -int fixed_sdram(void) +static int fixed_sdram(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; @@ -354,9 +359,11 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig new file mode 100644 index 0000000000..3476780847 --- /dev/null +++ b/board/keymile/km_arm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KM_KIRKWOOD + +config SYS_BOARD + default "km_arm" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "km_kirkwood" + +endif diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS new file mode 100644 index 0000000000..079c803677 --- /dev/null +++ b/board/keymile/km_arm/MAINTAINERS @@ -0,0 +1,14 @@ +KM_ARM BOARD +M: Valentin Longchamp +S: Maintained +F: board/keymile/km_arm/ +F: include/configs/km_kirkwood.h +F: configs/km_kirkwood_defconfig +F: configs/km_kirkwood_128m16_defconfig +F: configs/km_kirkwood_pci_defconfig +F: configs/kmcoge5un_defconfig +F: configs/kmnusa_defconfig +F: configs/kmsugp1_defconfig +F: configs/kmsuv31_defconfig +F: configs/mgcoge3un_defconfig +F: configs/portl2_defconfig diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index 0f2018d734..a17d8d963a 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -6,31 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o ../common/common.o ../common/ivm.o +obj-y := km_arm.o ../common/common.o ../common/ivm.o ifdef CONFIG_KM_FPGA_CONFIG -COBJS += fpga_config.o +obj-y += fpga_config.o endif - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index cbfc7d2175..51a3cfe647 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -189,6 +189,31 @@ int wait_for_fpga_config(void) return 0; } +#if defined(KM_PCIE_RESET_MPP7) + +#define KM_PEX_RST_GPIO_PIN 7 +int fpga_reset(void) +{ + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe reset through GPIO7: "); + /* apply PCIe reset via GPIO */ + kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1); + kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1); + kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0); + udelay(1000*10); + kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1); + + printf(" done\n"); + + return 0; +} + +#else + #define PRST1 0x4 #define PCIE_RST 0x10 #define TRAFFIC_RST 0x04 @@ -219,6 +244,7 @@ int fpga_reset(void) return 0; } +#endif /* the FPGA was configured, we configure the BOCO2 so that the EEPROM * is available from the Bobcat SPI bus */ diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 481876b2ed..1c7c108cb5 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include "../common/common.h" @@ -46,7 +46,11 @@ static const u32 kwmpp_config[] = { MPP4_NF_IO6, MPP5_NF_IO7, MPP6_SYSRST_OUTn, +#if defined(KM_PCIE_RESET_MPP7) + MPP7_GPO, +#else MPP7_PEX_RST_OUTn, +#endif #if defined(CONFIG_SYS_I2C_SOFT) MPP8_GPIO, /* SDA */ MPP9_GPIO, /* SCL */ @@ -102,7 +106,7 @@ static const u32 kwmpp_config[] = { /* * Wait for startup OK from mgcoge3ne */ -int startup_allowed(void) +static int startup_allowed(void) { unsigned char buf; @@ -164,7 +168,6 @@ static int initialize_unit_leds(void) return 0; } -#if defined(CONFIG_BOOTCOUNT_LIMIT) static void set_bootcount_addr(void) { uchar buf[32]; @@ -173,7 +176,6 @@ static void set_bootcount_addr(void) sprintf((char *)buf, "0x%x", bootcountaddr); setenv("bootcountaddr", (char *)buf); } -#endif int misc_init_r(void) { @@ -210,9 +212,7 @@ int misc_init_r(void) initialize_unit_leds(); set_km_env(); -#if defined(CONFIG_BOOTCOUNT_LIMIT) set_bootcount_addr(); -#endif return 0; } @@ -222,11 +222,11 @@ int board_early_init_f(void) u32 tmp; /* set the 2 bitbang i2c pins as output gpios */ - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); + tmp = readl(MVEBU_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); #endif /* adjust SDRAM size for bank 0 */ - kw_sdram_size_adjust(0); + mvebu_sdram_size_adjust(0); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -234,7 +234,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; /* * The KM_FLASH_GPIO_PIN switches between using a @@ -322,15 +322,15 @@ void reset_phy(void) return; /* RGMII clk transition on data stable */ - if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) + if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) printf("Error reading PHY spec ctrl reg\n"); - if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n"); /* leds setup */ - if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n"); /* reset the phy */ @@ -343,7 +343,7 @@ void reset_phy(void) #if defined(CONFIG_KM_NUSA) struct mv88e_sw_reg extsw_conf[] = { /* - * port 0, PIGGY4, autoneg + * port 0, PIGGY4, autoneg * first the fix for the 1000Mbits Autoneg, this is from * a Marvell errata, the regs are undocumented */ diff --git a/board/keymile/kmp204x/Kconfig b/board/keymile/kmp204x/Kconfig new file mode 100644 index 0000000000..7b45a13cfb --- /dev/null +++ b/board/keymile/kmp204x/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KMP204X + +config SYS_BOARD + default "kmp204x" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmp204x" + +endif diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS new file mode 100644 index 0000000000..93b6bad0a8 --- /dev/null +++ b/board/keymile/kmp204x/MAINTAINERS @@ -0,0 +1,7 @@ +KMP204X BOARD +M: Valentin Longchamp +S: Maintained +F: board/keymile/kmp204x/ +F: include/configs/kmp204x.h +F: configs/kmcoge4_defconfig +F: configs/kmlion1_defconfig diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile new file mode 100644 index 0000000000..c57ca08e14 --- /dev/null +++ b/board/keymile/kmp204x/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2001-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \ + ../common/common.o ../common/ivm.o diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c new file mode 100644 index 0000000000..34ac6979bd --- /dev/null +++ b/board/keymile/kmp204x/ddr.c @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + + /* automatic calibration for nb of cycles between read and DQS pre */ + popts->cpo_override = 0xFF; + + /* 1/2 clk delay between wr command and data strobe */ + popts->write_data_delay = 4; + /* clk lauched 1/2 applied cylcle after address command */ + popts->clk_adjust = 4; + /* 1T timing: command/address held for only 1 cycle */ + popts->twot_en = 0; + + /* we have only one module, half str should be OK */ + popts->half_strength_driver_enable = 1; + + /* wrlvl values overriden as recommended by ddr init func */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x6; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing with SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + return dram_size; +} diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c new file mode 100644 index 0000000000..a0731055a2 --- /dev/null +++ b/board/keymile/kmp204x/eth.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#ifdef CONFIG_FMAN_ENET + struct fsl_pq_mdio_info dtsec_mdio_info; + + printf("Initializing Fman\n"); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + /* DTESC1/2 don't have a PHY, they are temporarily disabled + * so that u-boot doesn't try to unsuccessfuly enable them */ + fm_disable_port(FM1_DTSEC1); + fm_disable_port(FM1_DTSEC2); + + /* + * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf + * This is the debug interface, the only one used in u-boot + */ + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + fm_info_set_mdio(FM1_DTSEC5, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + + ret = cpu_eth_init(bis); + + /* reenable DTSEC1/2 for later (kernel) */ + fm_enable_port(FM1_DTSEC1); + fm_enable_port(FM1_DTSEC2); +#endif + + return ret; +} + +#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL) + +#define mv88E1118_PAGE_REG 22 + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) { + /* driver config is good */ + if (phydev->drv->config) + phydev->drv->config(phydev); + + /* but we still need to fix the LEDs */ + phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003); + phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840); + phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000); + } + + return 0; +} +#endif diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c new file mode 100644 index 0000000000..a74f75bad4 --- /dev/null +++ b/board/keymile/kmp204x/kmp204x.c @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * Copyright 2011,2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/common.h" +#include "kmp204x.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME); + + return 0; +} + +/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c + * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines + * For I2C only the low state is activly driven and high state is pulled-up + * by a resistor. Therefore the deblock GPIOs are used + * -> as an active output to drive a low state + * -> as an open-drain input to have a pulled-up high state + */ + +/* QRIO GPIOs used for deblocking */ +#define DEBLOCK_PORT1 GPIO_A +#define DEBLOCK_SCL1 20 +#define DEBLOCK_SDA1 21 + +/* By default deblock GPIOs are floating */ +static void i2c_deblock_gpio_cfg(void) +{ + /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ + qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1); + qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1); + + qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0); + qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0); +} + +void set_sda(int state) +{ + qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state); +} + +void set_scl(int state) +{ + qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state); +} + +int get_sda(void) +{ + return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1); +} + +int get_scl(void) +{ + return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1); +} + + +#define ZL30158_RST 8 +#define BFTIC4_RST 0 +#define RSTRQSR1_WDT_RR 0x00200000 +#define RSTRQSR1_SW_RR 0x00100000 + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + bool cpuwd_flag = false; + + /* configure mode for uP reset request */ + qrio_uprstreq(UPREQ_CORE_RST); + + /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ + setbits_be32(&gur->ddrclkdr, 0x001f000f); + + /* set reset reason according CPU register */ + if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) == + RSTRQSR1_WDT_RR) + cpuwd_flag = true; + + qrio_cpuwd_flag(cpuwd_flag); + /* clear CPU bits by writing 1 */ + setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR); + + /* set the BFTIC's prstcfg to reset at power-up and unit reset only */ + qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); + /* and enable WD on it */ + qrio_wdmask(BFTIC4_RST, true); + + /* set the ZL30138's prstcfg to reset at power-up only */ + qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST); + /* and take it out of reset as soon as possible (needed for Hooper) */ + qrio_prst(ZL30158_RST, false, false); + + return 0; +} + +int board_early_init_r(void) +{ + int ret = 0; + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + set_liodns(); + setup_portals(); + + ret = trigger_fpga_config(); + if (ret) + printf("error triggering PCIe FPGA config\n"); + + /* enable the Unit LED (red) & Boot LED (on) */ + qrio_set_leds(); + + /* enable Application Buffer */ + qrio_enable_app_buffer(); + + return ret; +} + +unsigned long get_board_sys_clk(unsigned long dummy) +{ + return 66666666; +} + +#define ETH_FRONT_PHY_RST 15 +#define QSFP2_RST 11 +#define QSFP1_RST 10 +#define ZL30343_RST 9 + +int misc_init_f(void) +{ + /* configure QRIO pis for i2c deblocking */ + i2c_deblock_gpio_cfg(); + + /* configure the front phy's prstcfg and take it out of reset */ + qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + qrio_prst(ETH_FRONT_PHY_RST, false, false); + + /* set the ZL30343 prstcfg to reset at power-up only */ + qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST); + /* and enable the WD on it */ + qrio_wdmask(ZL30343_RST, true); + + /* set the QSFPs' prstcfg to reset at power-up and unit rst only */ + qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST); + + /* and enable the WD on them */ + qrio_wdmask(QSFP1_RST, true); + qrio_wdmask(QSFP2_RST, true); + + return 0; +} + +#define NUM_SRDS_BANKS 2 + +int misc_init_r(void) +{ + serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100, + SRDS_PLLCR0_RFCK_SEL_125}; + unsigned int i; + + /* check SERDES reference clocks */ + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 actual = in_be32(®s->bank[i].pllcr0); + actual &= SRDS_PLLCR0_RFCK_SEL_MASK; + if (actual != expected[i]) { + printf("Warning: SERDES bank %u expects reference \ + clock %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected[i]), + serdes_clock_to_string(actual)); + } + } + + return 0; +} + +#if defined(CONFIG_HUSH_INIT_VAR) +int hush_init_var(void) +{ + ivm_read_eeprom(); + return 0; +} +#endif + +#if defined(CONFIG_LAST_STAGE_INIT) + +int last_stage_init(void) +{ +#if defined(CONFIG_KMCOGE4) + /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */ + struct bfticu_iomap *bftic4 = + (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE; + u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK; + + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + setenv("actual_bank", "0"); + } +#endif + set_km_env(); + + return 0; +} +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +void fdt_fixup_fman_mac_addresses(void *blob) +{ + int node, i, ret; + char *tmp, *end; + unsigned char mac_addr[6]; + + /* get the mac addr from env */ + tmp = getenv("ethaddr"); + if (!tmp) { + printf("ethaddr env variable not defined\n"); + return; + } + for (i = 0; i < 6; i++) { + mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + + /* find the correct fdt ethernet path and correct it */ + node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return; + } + ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return; + } +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_fman_mac_addresses(blob); +#endif + + return 0; +} + +#if defined(CONFIG_POST) + +/* DIC26_SELFTEST GPIO used to start factory test sw */ +#define SELFTEST_PORT GPIO_A +#define SELFTEST_PIN 31 + +int post_hotkeys_pressed(void) +{ + qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN); + return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN); +} +#endif diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h new file mode 100644 index 0000000000..e90e8abd43 --- /dev/null +++ b/board/keymile/kmp204x/kmp204x.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* QRIO GPIO ports */ +#define GPIO_A 0x40 +#define GPIO_B 0x60 + +int qrio_get_gpio(u8 port_off, u8 gpio_nr); +void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val); +void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value); +void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value); +void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr); + +#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0 +#define PRSTCFG_POWUP_UNIT_RST 0x1 +#define PRSTCFG_POWUP_RST 0x3 + +void qrio_prst(u8 bit, bool en, bool wden); +void qrio_wdmask(u8 bit, bool wden); +void qrio_prstcfg(u8 bit, u8 mode); +void qrio_set_leds(void); +void qrio_enable_app_buffer(void); +void qrio_cpuwd_flag(bool flag); +int qrio_reset_reason(void); + +#define UPREQ_UNIT_RST 0x0 +#define UPREQ_CORE_RST 0x1 + +void qrio_uprstreq(u8 mode); + +void pci_of_setup(void *blob, bd_t *bd); diff --git a/board/keymile/kmp204x/law.c b/board/keymile/kmp204x/law.c new file mode 100644 index 0000000000..75d69e8b48 --- /dev/null +++ b/board/keymile/kmp204x/law.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), +#endif + SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS + SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#endif +#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS + SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg new file mode 100644 index 0000000000..1e0a171d88 --- /dev/null +++ b/board/keymile/kmp204x/pbi.cfg @@ -0,0 +1,76 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Configure ALTCBAR for DCSR -> DCSR@89000000 +091380c0 000009C4 +09000010 00000000 +091380c0 000009C4 +09000014 00000000 +091380c0 000009C4 +09000018 81d00000 +#Workaround for A-004849 +091380c0 000009C4 +890B0050 00000002 +091380c0 000009C4 +890B0054 00000002 +091380c0 000009C4 +890B0058 00000002 +091380c0 000009C4 +890B005C 00000002 +091380c0 000009C4 +890B0090 00000002 +091380c0 000009C4 +890B0094 00000002 +091380c0 000009C4 +890B0098 00000002 +091380c0 000009C4 +890B009C 00000002 +091380c0 000009C4 +890B0108 00000012 +091380c0 000009C4 +#Workaround for A-006559 needed for rev 2.0 of P2041 silicon +89021008 0000f000 +091380c0 000009C4 +89021028 0000f000 +091380c0 000009C4 +89021048 0000f000 +091380c0 000009C4 +89021068 0000f000 +091380c0 000009C4 +#Flush PBL data +09138000 00000000 +#Disable ALTCBAR +09000018 00000000 +091380c0 000009C4 +#Initialize CPC1 as 1MB SRAM +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 27170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c new file mode 100644 index 0000000000..2b0b054a11 --- /dev/null +++ b/board/keymile/kmp204x/pci.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * Copyright 2007-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "kmp204x.h" + +#define PROM_SEL_L 11 +/* control the PROM_SEL_L signal*/ +static void toggle_fpga_eeprom_bus(bool cpu_own) +{ + qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own); +} + +#define CONF_SEL_L 10 +#define FPGA_PROG_L 19 +#define FPGA_DONE 18 +#define FPGA_INIT_L 17 + +int trigger_fpga_config(void) +{ + int ret = 0, init_l; + /* approx 10ms */ + u32 timeout = 10000; + + /* make sure the FPGA_can access the EEPROM */ + toggle_fpga_eeprom_bus(false); + + /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */ + qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0); + + /* trigger the config start */ + qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0); + + /* small delay for INIT_L line */ + udelay(10); + + /* wait for FPGA_INIT to be asserted */ + do { + init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L); + if (timeout-- == 0) { + printf("FPGA_INIT timeout\n"); + ret = -EFAULT; + break; + } + udelay(10); + } while (init_l); + + /* deassert FPGA_PROG, config should start */ + qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1); + + return ret; +} + +/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */ +static int wait_for_fpga_config(void) +{ + int ret = 0, done; + /* approx 5 s */ + u32 timeout = 500000; + + printf("PCIe FPGA config:"); + do { + done = qrio_get_gpio(GPIO_A, FPGA_DONE); + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + ret = -EFAULT; + goto err_out; + } + udelay(10); + } while (!done); + + printf(" done\n"); + +err_out: + /* deactive CONF_SEL and give the CPU conf EEPROM access */ + qrio_set_gpio(GPIO_A, CONF_SEL_L, 1); + toggle_fpga_eeprom_bus(true); + + return ret; +} + +#define PCIE_SW_RST 14 +#define PEXHC_RST 13 +#define HOOPER_RST 12 + +void pci_init_board(void) +{ + qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + + /* wait for the PCIe FPGA to be configured + * it has been triggered earlier in board_early_init_r */ + if (wait_for_fpga_config()) + printf("error finishing PCIe FPGA config\n"); + + qrio_prst(PCIE_SW_RST, false, false); + qrio_prst(PEXHC_RST, false, false); + qrio_prst(HOOPER_RST, false, false); + /* Hooper is not direcly PCIe capable */ + mdelay(50); + + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c new file mode 100644 index 0000000000..edf3bf11a8 --- /dev/null +++ b/board/keymile/kmp204x/qrio.c @@ -0,0 +1,207 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include "../common/common.h" +#include "kmp204x.h" + +/* QRIO GPIO register offsets */ +#define DIRECT_OFF 0x18 +#define GPRT_OFF 0x1c + +int qrio_get_gpio(u8 port_off, u8 gpio_nr) +{ + u32 gprt; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + gprt = in_be32(qrio_base + port_off + GPRT_OFF); + + return (gprt >> gpio_nr) & 1U; +} + +void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) +{ + u32 gprt, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + gprt = in_be32(qrio_base + port_off + GPRT_OFF); + if (value) + gprt |= mask; + else + gprt &= ~mask; + + out_be32(qrio_base + port_off + GPRT_OFF, gprt); +} + +void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + direct |= mask; + out_be32(qrio_base + port_off + DIRECT_OFF, direct); + + qrio_set_gpio(port_off, gpio_nr, value); +} + +void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + direct &= ~mask; + out_be32(qrio_base + port_off + DIRECT_OFF, direct); +} + +void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) +{ + u32 direct, mask; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + mask = 1U << gpio_nr; + + direct = in_be32(qrio_base + port_off + DIRECT_OFF); + if (val == 0) + /* set to output -> GPIO drives low */ + direct |= mask; + else + /* set to input -> GPIO floating */ + direct &= ~mask; + + out_be32(qrio_base + port_off + DIRECT_OFF, direct); +} + +#define WDMASK_OFF 0x16 + +void qrio_wdmask(u8 bit, bool wden) +{ + u16 wdmask; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + wdmask = in_be16(qrio_base + WDMASK_OFF); + + if (wden) + wdmask |= (1 << bit); + else + wdmask &= ~(1 << bit); + + out_be16(qrio_base + WDMASK_OFF, wdmask); +} + +#define PRST_OFF 0x1a + +void qrio_prst(u8 bit, bool en, bool wden) +{ + u16 prst; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + qrio_wdmask(bit, wden); + + prst = in_be16(qrio_base + PRST_OFF); + + if (en) + prst &= ~(1 << bit); + else + prst |= (1 << bit); + + out_be16(qrio_base + PRST_OFF, prst); +} + +#define PRSTCFG_OFF 0x1c + +void qrio_prstcfg(u8 bit, u8 mode) +{ + u32 prstcfg; + u8 i; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + prstcfg = in_be32(qrio_base + PRSTCFG_OFF); + + for (i = 0; i < 2; i++) { + if (mode & (1< + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + /* TLB 1 */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + /* QRIO */ + SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_64K, 1), + /* *I*G* - PCI1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + /* *I*G* - PCI3 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_512M, 1), + /* *I*G* - PCI1&3 I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_128K, 1), +#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS + /* LBAPP1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), +#endif +#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS + /* LBAPP2 */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), +#endif + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_32K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/keymile/scripts/develop-arm.txt b/board/keymile/scripts/develop-arm.txt index 922afea277..d3c974f1f9 100644 --- a/board/keymile/scripts/develop-arm.txt +++ b/board/keymile/scripts/develop-arm.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=true diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index a6bb1b1d4a..a80812a5d0 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -3,6 +3,7 @@ bootcmd=run ${subbootcmds} configure=run set_uimage; km_setboardid && saveenv && reset subbootcmds=tftpfdt tftpkernel nfsargs add_default boot nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch} +tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} toolchain=/opt/eldk rootfssize=0 diff --git a/board/keymile/scripts/develop-ppc_82xx.txt b/board/keymile/scripts/develop-ppc_82xx.txt index 909f6a3cee..d3c974f1f9 100644 --- a/board/keymile/scripts/develop-ppc_82xx.txt +++ b/board/keymile/scripts/develop-ppc_82xx.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/develop-ppc_8xx.txt b/board/keymile/scripts/develop-ppc_8xx.txt index 909f6a3cee..d3c974f1f9 100644 --- a/board/keymile/scripts/develop-ppc_8xx.txt +++ b/board/keymile/scripts/develop-ppc_8xx.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/ramfs-arm.txt b/board/keymile/scripts/ramfs-arm.txt index 79974f1b70..87e984e179 100644 --- a/board/keymile/scripts/ramfs-arm.txt +++ b/board/keymile/scripts/ramfs-arm.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=true diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index 8a8d287558..d79ad2e21b 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -1,5 +1,5 @@ addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}" -actual_bank=-1 +boot_bank=-1 altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot @@ -7,6 +7,7 @@ nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} configure=run set_uimage; km_setboardid && saveenv && reset rootfsfile=${hostname}/rootfsImage setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} +tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage set_uimage=printenv uimage || setenv uimage uImage diff --git a/board/keymile/scripts/ramfs-ppc_82xx.txt b/board/keymile/scripts/ramfs-ppc_82xx.txt index 970927a2fa..87e984e179 100644 --- a/board/keymile/scripts/ramfs-ppc_82xx.txt +++ b/board/keymile/scripts/ramfs-ppc_82xx.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/ramfs-ppc_8xx.txt b/board/keymile/scripts/ramfs-ppc_8xx.txt index 970927a2fa..87e984e179 100644 --- a/board/keymile/scripts/ramfs-ppc_8xx.txt +++ b/board/keymile/scripts/ramfs-ppc_8xx.txt @@ -1,2 +1 @@ setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/kmc/kzm9g/Kconfig b/board/kmc/kzm9g/Kconfig new file mode 100644 index 0000000000..f163efd989 --- /dev/null +++ b/board/kmc/kzm9g/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KZM9G + +config SYS_BOARD + default "kzm9g" + +config SYS_VENDOR + default "kmc" + +config SYS_CONFIG_NAME + default "kzm9g" + +endif diff --git a/board/kmc/kzm9g/MAINTAINERS b/board/kmc/kzm9g/MAINTAINERS new file mode 100644 index 0000000000..411efd1e31 --- /dev/null +++ b/board/kmc/kzm9g/MAINTAINERS @@ -0,0 +1,7 @@ +KZM9G BOARD +M: Nobuhiro Iwamatsu +M: Tetsuyuki Kobayashi +S: Maintained +F: board/kmc/kzm9g/ +F: include/configs/kzm9g.h +F: configs/kzm9g_defconfig diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile index 62fb3779ed..7989884940 100644 --- a/board/kmc/kzm9g/Makefile +++ b/board/kmc/kzm9g/Makefile @@ -5,30 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := kzm9g.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj) .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := kzm9g.o diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index b669ffefec..ea36fa4e19 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -289,7 +289,6 @@ void adjust_core_voltage(void) { u8 data; - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); data = 0x35; i2c_set_bus_num(0); i2c_write(0x40, 3, 1, &data, 1); diff --git a/board/korat/Kconfig b/board/korat/Kconfig new file mode 100644 index 0000000000..f434dea7f3 --- /dev/null +++ b/board/korat/Kconfig @@ -0,0 +1,9 @@ +if TARGET_KORAT + +config SYS_BOARD + default "korat" + +config SYS_CONFIG_NAME + default "korat" + +endif diff --git a/board/korat/MAINTAINERS b/board/korat/MAINTAINERS new file mode 100644 index 0000000000..8b968461f2 --- /dev/null +++ b/board/korat/MAINTAINERS @@ -0,0 +1,7 @@ +KORAT BOARD +M: Larry Johnson +S: Maintained +F: board/korat/ +F: include/configs/korat.h +F: configs/korat_defconfig +F: configs/korat_perm_defconfig diff --git a/board/korat/Makefile b/board/korat/Makefile index 0e95230bf0..63914bc13b 100644 --- a/board/korat/Makefile +++ b/board/korat/Makefile @@ -5,27 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = korat.o +extra-y += init.o diff --git a/board/korat/config.mk b/board/korat/config.mk index f8dba2baae..42e0060094 100644 --- a/board/korat/config.mk +++ b/board/korat/config.mk @@ -23,5 +23,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000 endif ifndef CONFIG_KORAT_PERMANENT -LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds +LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds endif diff --git a/board/korat/init.S b/board/korat/init.S index 23557fe34d..20c5bddf6b 100644 --- a/board/korat/init.S +++ b/board/korat/init.S @@ -1,6 +1,6 @@ /* * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/korat/korat.c b/board/korat/korat.c index 8b83000509..d9ab2fd421 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -610,7 +610,7 @@ void pci_target_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { u32 val[4]; int rc; @@ -627,5 +627,7 @@ void ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update property NOR mapping, err=%s\n", fdt_strerror(rc)); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/kosagi/novena/Kconfig b/board/kosagi/novena/Kconfig new file mode 100644 index 0000000000..94f1754a47 --- /dev/null +++ b/board/kosagi/novena/Kconfig @@ -0,0 +1,15 @@ +if TARGET_KOSAGI_NOVENA + +config SYS_BOARD + default "novena" + +config SYS_VENDOR + default "kosagi" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "novena" + +endif diff --git a/board/kosagi/novena/MAINTAINERS b/board/kosagi/novena/MAINTAINERS new file mode 100644 index 0000000000..d3471c2d65 --- /dev/null +++ b/board/kosagi/novena/MAINTAINERS @@ -0,0 +1,6 @@ +NOVENA BOARD +M: Marek Vasut +S: Maintained +F: board/kosagi/novena/ +F: include/configs/novena.h +F: configs/novena_defconfig diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile new file mode 100644 index 0000000000..6893b6311d --- /dev/null +++ b/board/kosagi/novena/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Marek Vasut +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := novena_spl.o +else +obj-y := novena.o +obj-$(CONFIG_VIDEO_IPUV3) += video.o +endif diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c new file mode 100644 index 0000000000..69f5be3b9c --- /dev/null +++ b/board/kosagi/novena/novena.c @@ -0,0 +1,269 @@ +/* + * Novena board support + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "novena.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * GPIO button + */ +#ifdef CONFIG_KEYBOARD +static struct input_config button_input; + +static int novena_gpio_button_read_keys(struct input_config *input) +{ + int key = KEY_ENTER; + if (gpio_get_value(NOVENA_BUTTON_GPIO)) + return 0; + input_send_keycodes(&button_input, &key, 1); + return 1; +} + +static int novena_gpio_button_getc(struct stdio_dev *dev) +{ + return input_getc(&button_input); +} + +static int novena_gpio_button_tstc(struct stdio_dev *dev) +{ + return input_tstc(&button_input); +} + +static int novena_gpio_button_init(struct stdio_dev *dev) +{ + gpio_direction_input(NOVENA_BUTTON_GPIO); + input_set_delays(&button_input, 250, 250); + return 0; +} + +int drv_keyboard_init(void) +{ + int error; + struct stdio_dev dev = { + .name = "button", + .flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM, + .start = novena_gpio_button_init, + .getc = novena_gpio_button_getc, + .tstc = novena_gpio_button_tstc, + }; + + error = input_init(&button_input, 0); + if (error) { + debug("%s: Cannot set up input\n", __func__); + return -1; + } + button_input.read_keys = novena_gpio_button_read_keys; + + error = input_stdio_register(&dev); + if (error) + return error; + + return 0; +} +#endif + +/* + * SDHC + */ +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC3_BASE_ADDR, 0, 4 }, /* Micro SD */ + { USDHC2_BASE_ADDR, 0, 4 }, /* Big SD */ +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + /* There is no CD for a microSD card, assume always present. */ + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + return 1; + else + return !gpio_get_value(NOVENA_SD_CD); +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + /* There is no WP for a microSD card, assume always read-write. */ + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + return 0; + else + return gpio_get_value(NOVENA_SD_WP); +} + + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + int index; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + /* Big SD write-protect and card-detect */ + gpio_direction_input(NOVENA_SD_WP); + gpio_direction_input(NOVENA_SD_CD); + + for (index = 0; index < ARRAY_SIZE(usdhc_cfg); index++) { + status = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (status) + return status; + } + + return status; +} +#endif + +int board_early_init_f(void) +{ +#if defined(CONFIG_VIDEO_IPUV3) + setup_display_clock(); +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_VIDEO_IPUV3) + setup_display_lvds(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: Novena 4x\n"); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + u32 reg; + int ret; + + power_pfuze100_init(1); + p = pmic_get("PFUZE100"); + if (!p) + return -EINVAL; + + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set SWBST to 5.0V and enable (for USB) */ + pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); + reg |= (SWBST_5_00V | SWBST_MODE_AUTO); + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); + + return 0; +} + +/* EEPROM configuration data */ +struct novena_eeprom_data { + uint8_t signature[6]; + uint8_t version; + uint8_t reserved; + uint32_t serial; + uint8_t mac[6]; + uint16_t features; +}; + +int misc_init_r(void) +{ + struct novena_eeprom_data data; + uchar *datap = (uchar *)&data; + const char *signature = "Novena"; + int ret; + + /* If 'ethaddr' is already set, do nothing. */ + if (getenv("ethaddr")) + return 0; + + /* EEPROM is at bus 2. */ + ret = i2c_set_bus_num(2); + if (ret) { + puts("Cannot select EEPROM I2C bus.\n"); + return 0; + } + + /* EEPROM is at address 0x56. */ + ret = eeprom_read(0x56, 0, datap, sizeof(data)); + if (ret) { + puts("Cannot read I2C EEPROM.\n"); + return 0; + } + + /* Check EEPROM signature. */ + if (memcmp(data.signature, signature, 6)) { + puts("Invalid I2C EEPROM signature.\n"); + return 0; + } + + /* Set ethernet address from EEPROM. */ + eth_setenv_enetaddr("ethaddr", data.mac); + + return ret; +} diff --git a/board/kosagi/novena/novena.h b/board/kosagi/novena/novena.h new file mode 100644 index 0000000000..8f11583c2d --- /dev/null +++ b/board/kosagi/novena/novena.h @@ -0,0 +1,33 @@ +/* + * Novena board support + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOARD_KOSAGI_NOVENA_NOVENA_H__ +#define __BOARD_KOSAGI_NOVENA_NOVENA_H__ + +#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) +#define NOVENA_BACKLIGHT_PWM_GPIO IMX_GPIO_NR(4, 29) +#define NOVENA_BACKLIGHT_PWR_GPIO IMX_GPIO_NR(4, 15) +#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14) +#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) +#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) +#define NOVENA_ITE6251_PWR_GPIO IMX_GPIO_NR(5, 28) +#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) +#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) +#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) +#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22) +#define NOVENA_SD_CD IMX_GPIO_NR(1, 4) +#define NOVENA_SD_WP IMX_GPIO_NR(1, 2) + +#define NOVENA_IT6251_I2C_BUS 2 +#define NOVENA_IT6251_CHIPADDR 0x5c +#define NOVENA_IT6251_LVDSADDR 0x5e + +void setup_display_clock(void); +void setup_display_lvds(void); + +#endif /* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */ diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c new file mode 100644 index 0000000000..b1688e0295 --- /dev/null +++ b/board/kosagi/novena/novena_spl.c @@ -0,0 +1,613 @@ +/* + * Novena SPL + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "novena.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PHY_CFG_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_HYS) + +#define RGMII_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL \ + (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define BUTTON_PAD_CTRL \ + (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* + * Audio + */ +static iomux_v3_cfg_t audio_pads[] = { + /* AUD_PWRON */ + MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_audio(void) +{ + imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads)); + gpio_direction_output(NOVENA_AUDIO_PWRON, 1); +} + +/* + * ENET + */ +static iomux_v3_cfg_t enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* pin 35, PHY_AD2 */ + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 32, MODE0 */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 31, MODE1 */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 28, MODE2 */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 27, MODE3 */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + /* pin 33, CLK125_EN */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), + + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t enet_pads2[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + + /* Assert Ethernet PHY nRST */ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + + /* + * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset + * de-assertion. The intention is to use weak signal drivers (pull-ups) + * to prevent the conflict between PHY pins becoming outputs after + * reset and imx6 still driving the pins. The issue is described in PHY + * datasheet, p.14 + */ + gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */ + gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */ + + /* Following reset timing (p.53, fig.8 from the PHY datasheet) */ + mdelay(10); + + /* De-assert Ethernet PHY nRST */ + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + + /* PHY is now configured, connect FEC to the pads */ + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + + /* + * PHY datasheet recommends on p.53 to wait at least 100us after reset + * before using MII, so we enforce the delay here + */ + udelay(100); +} + +/* + * FPGA + */ +static iomux_v3_cfg_t fpga_pads[] = { + /* FPGA_RESET_N */ + MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_fpga(void) +{ + imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads)); + gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0); +} + +/* + * GPIO Button + */ +static iomux_v3_cfg_t button_pads[] = { + /* Debug */ + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads)); +} + +/* + * I2C + */ +/* + * I2C1: + * 0x1d ... MMA7455L + * 0x30 ... SO-DIMM temp sensor + * 0x44 ... STMPE610 + * 0x50 ... SO-DIMM ID + */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* + * I2C2: + * 0x08 ... PMIC + * 0x3a ... HDMI DCC + * 0x50 ... HDMI DCC + */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + +/* + * I2C3: + * 0x11 ... ES8283 + * 0x50 ... LCD EDID + * 0x56 ... EEPROM + */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +static void novena_spl_setup_iomux_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +} + +/* + * PCI express + */ +#ifdef CONFIG_CMD_PCI +static iomux_v3_cfg_t pcie_pads[] = { + /* "Reset" pin */ + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* "Power on" pin */ + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* "Wake up" pin (input) */ + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* "Disable endpoint" (rfkill) pin */ + MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); + + /* Ensure PCIe is powered down */ + gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0); + + /* Put the card into reset */ + gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0); + + /* Input signal to wake system from mPCIe card */ + gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO); + + /* Drive RFKILL high, to ensure the radio is turned on */ + gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1); +} +#else +static inline void novena_spl_setup_iomux_pcie(void) {} +#endif + +/* + * SDHC + */ +static iomux_v3_cfg_t usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static iomux_v3_cfg_t usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_sdhc(void) +{ + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + + /* Big SD write-protect and card-detect */ + gpio_direction_input(IMX_GPIO_NR(1, 2)); + gpio_direction_input(IMX_GPIO_NR(1, 4)); +} + +/* + * SPI + */ +#ifdef CONFIG_MXC_SPI +static iomux_v3_cfg_t ecspi3_pads[] = { + /* SS1 */ + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); + /* De-assert the nCS */ + gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1); + gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1); + gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1); +} +#else +static void novena_spl_setup_iomux_spi(void) {} +#endif + +/* + * UART + */ +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + +}; + +static void novena_spl_setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +/* + * Video + */ +#ifdef CONFIG_VIDEO +static iomux_v3_cfg_t hdmi_pads[] = { + /* "Ghost HPD" pin */ + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* LCD_PWR_CTL */ + MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LCD_BL_ON */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPIO_PWM1 */ + MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void novena_spl_setup_iomux_video(void) +{ + imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads)); + gpio_direction_input(NOVENA_HDMI_GHOST_HPD); +} +#else +static inline void novena_spl_setup_iomux_video(void) {} +#endif + +/* + * SPL boots from uSDHC card + */ +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg = { + USDHC3_BASE_ADDR, 0, 4 +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* There is no CD for a microSD card, assume always present. */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} +#endif + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020038, + .dram_sdclk_1 = 0x00020038, + .dram_cas = 0x00000038, + .dram_ras = 0x00000038, + .dram_reset = 0x00000038, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00000038, + .dram_sdodt1 = 0x00000038, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000038, + .dram_sdqs2 = 0x00000038, + .dram_sdqs3 = 0x00000038, + .dram_sdqs4 = 0x00000038, + .dram_sdqs5 = 0x00000038, + .dram_sdqs6 = 0x00000038, + .dram_sdqs7 = 0x00000038, + + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00000038, + .dram_dqm1 = 0x00000038, + .dram_dqm2 = 0x00000038, + .dram_dqm3 = 0x00000038, + .dram_dqm4 = 0x00000038, + .dram_dqm5 = 0x00000038, + .dram_dqm6 = 0x00000038, + .dram_dqm7 = 0x00000038, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs novena_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* Disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000038, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000038, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000038, + .grp_b1ds = 0x00000038, + .grp_b2ds = 0x00000038, + .grp_b3ds = 0x00000038, + .grp_b4ds = 0x00000038, + .grp_b5ds = 0x00000038, + .grp_b6ds = 0x00000038, + .grp_b7ds = 0x00000038, +}; + +static struct mx6_mmdc_calibration novena_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00420048, + .p0_mpwldectrl1 = 0x006f0059, + .p1_mpwldectrl0 = 0x005a0104, + .p1_mpwldectrl1 = 0x01070113, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x437c040b, + .p0_mpdgctrl1 = 0x0413040e, + .p1_mpdgctrl0 = 0x444f0446, + .p1_mpdgctrl1 = 0x044d0422, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4c424249, + .p1_mprddlctl = 0x4e48414f, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x42414641, + .p1_mpwrdlctl = 0x46374b43, +}; + +static struct mx6_ddr_sysinfo novena_ddr_info = { + /* Width of data bus: 0=16, 1=32, 2=64 */ + .dsize = 2, + /* Config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* Single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 3, /* Write additional latency */ + .ralat = 7, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +static struct mx6_ddr3_cfg elpida_4gib_1600 = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 16, + .coladdr = 10, + .pagesz = 2, + .trcd = 1300, + .trcmin = 4900, + .trasmin = 3590, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* setup GP timer */ + timer_init(); + +#ifdef CONFIG_BOARD_POSTCLK_INIT + board_postclk_init(); +#endif +#ifdef CONFIG_FSL_ESDHC + get_clocks(); +#endif + + /* Setup IOMUX and configure basics. */ + novena_spl_setup_iomux_audio(); + novena_spl_setup_iomux_buttons(); + novena_spl_setup_iomux_enet(); + novena_spl_setup_iomux_fpga(); + novena_spl_setup_iomux_i2c(); + novena_spl_setup_iomux_pcie(); + novena_spl_setup_iomux_sdhc(); + novena_spl_setup_iomux_spi(); + novena_spl_setup_iomux_uart(); + novena_spl_setup_iomux_video(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Start the DDR DRAM */ + mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs); + mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c new file mode 100644 index 0000000000..3bb1b7180b --- /dev/null +++ b/board/kosagi/novena/video.c @@ -0,0 +1,456 @@ +/* + * Novena video output support + * + * IT6251 code based on code Copyright (C) 2014 Sean Cross + * from https://github.com/xobs/novena-linux.git commit + * 3d85836ee1377d445531928361809612aa0a18db + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "novena.h" + +#define IT6251_VENDOR_ID_LOW 0x00 +#define IT6251_VENDOR_ID_HIGH 0x01 +#define IT6251_DEVICE_ID_LOW 0x02 +#define IT6251_DEVICE_ID_HIGH 0x03 +#define IT6251_SYSTEM_STATUS 0x0d +#define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0) +#define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1) +#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2) +#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3) +#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4) +#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5) +#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6) +#define IT6251_REF_STATE 0x0e +#define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0) +#define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1) +#define IT6251_REF_STATE_CR_PATTERN (1 << 2) +#define IT6251_REF_STATE_EQ_PATTERN (1 << 3) +#define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4) +#define IT6251_REF_STATE_MUTED (1 << 5) + +#define IT6251_REG_PCLK_CNT_LOW 0x57 +#define IT6251_REG_PCLK_CNT_HIGH 0x58 + +#define IT6521_RETRY_MAX 20 + +static int it6251_is_stable(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + const unsigned int laddr = NOVENA_IT6251_LVDSADDR; + int status; + int clkcnt; + int rpclkcnt; + int refstate; + + rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) | + ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00); + debug("RPCLKCnt: %d\n", rpclkcnt); + + status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS); + debug("System status: 0x%02x\n", status); + + clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) | + ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) & + 0x0f00); + debug("Clock: 0x%02x\n", clkcnt); + + refstate = i2c_reg_read(laddr, IT6251_REF_STATE); + debug("Ref Link State: 0x%02x\n", refstate); + + if ((refstate & 0x1f) != 0) + return 0; + + /* If video is muted, that's a failure */ + if (refstate & IT6251_REF_STATE_MUTED) + return 0; + + if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE)) + return 0; + + return 1; +} + +static int it6251_ready(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + + /* Test if the IT6251 came out of reset by reading ID regs. */ + if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15) + return 0; + if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca) + return 0; + if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51) + return 0; + if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62) + return 0; + + return 1; +} + +static void it6251_program_regs(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + const unsigned int laddr = NOVENA_IT6251_LVDSADDR; + + i2c_reg_write(caddr, 0x05, 0x00); + mdelay(1); + + /* set LVDSRX address, and enable */ + i2c_reg_write(caddr, 0xfd, 0xbc); + i2c_reg_write(caddr, 0xfe, 0x01); + + /* + * LVDSRX + */ + /* This write always fails, because the chip goes into reset */ + /* reset LVDSRX */ + i2c_reg_write(laddr, 0x05, 0xff); + i2c_reg_write(laddr, 0x05, 0x00); + + /* reset LVDSRX PLL */ + i2c_reg_write(laddr, 0x3b, 0x42); + i2c_reg_write(laddr, 0x3b, 0x43); + + /* something with SSC PLL */ + i2c_reg_write(laddr, 0x3c, 0x08); + /* don't swap links, but writing reserved registers */ + i2c_reg_write(laddr, 0x0b, 0x88); + + /* JEIDA, 8-bit depth 0x11, orig 0x42 */ + i2c_reg_write(laddr, 0x2c, 0x01); + /* "reserved" */ + i2c_reg_write(laddr, 0x32, 0x04); + /* "reserved" */ + i2c_reg_write(laddr, 0x35, 0xe0); + /* "reserved" + clock delay */ + i2c_reg_write(laddr, 0x2b, 0x24); + + /* reset LVDSRX pix clock */ + i2c_reg_write(laddr, 0x05, 0x02); + i2c_reg_write(laddr, 0x05, 0x00); + + /* + * DPTX + */ + /* set for two lane mode, normal op, no swapping, no downspread */ + i2c_reg_write(caddr, 0x16, 0x02); + + /* some AUX channel EDID magic */ + i2c_reg_write(caddr, 0x23, 0x40); + + /* power down lanes 3-0 */ + i2c_reg_write(caddr, 0x5c, 0xf3); + + /* enable DP scrambling, change EQ CR phase */ + i2c_reg_write(caddr, 0x5f, 0x06); + + /* color mode RGB, pclk/2 */ + i2c_reg_write(caddr, 0x60, 0x02); + /* dual pixel input mode, no EO swap, no RGB swap */ + i2c_reg_write(caddr, 0x61, 0x04); + /* M444B24 video format */ + i2c_reg_write(caddr, 0x62, 0x01); + + /* vesa range / not interlace / vsync high / hsync high */ + i2c_reg_write(caddr, 0xa0, 0x0F); + + /* hpd event timer set to 1.6-ish ms */ + i2c_reg_write(caddr, 0xc9, 0xf5); + + /* more reserved magic */ + i2c_reg_write(caddr, 0xca, 0x4d); + i2c_reg_write(caddr, 0xcb, 0x37); + + /* enhanced framing mode, auto video fifo reset, video mute disable */ + i2c_reg_write(caddr, 0xd3, 0x03); + + /* "vidstmp" and some reserved stuff */ + i2c_reg_write(caddr, 0xd4, 0x45); + + /* queue number -- reserved */ + i2c_reg_write(caddr, 0xe7, 0xa0); + /* info frame packets and reserved */ + i2c_reg_write(caddr, 0xe8, 0x33); + /* more AVI stuff */ + i2c_reg_write(caddr, 0xec, 0x00); + + /* select PC master reg for aux channel? */ + i2c_reg_write(caddr, 0x23, 0x42); + + /* send PC request commands */ + i2c_reg_write(caddr, 0x24, 0x00); + i2c_reg_write(caddr, 0x25, 0x00); + i2c_reg_write(caddr, 0x26, 0x00); + + /* native aux read */ + i2c_reg_write(caddr, 0x2b, 0x00); + /* back to internal */ + i2c_reg_write(caddr, 0x23, 0x40); + + /* voltage swing level 3 */ + i2c_reg_write(caddr, 0x19, 0xff); + /* pre-emphasis level 3 */ + i2c_reg_write(caddr, 0x1a, 0xff); + + /* start link training */ + i2c_reg_write(caddr, 0x17, 0x01); +} + +static int it6251_init(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + int reg; + int tries, retries = 0; + + for (retries = 0; retries < IT6521_RETRY_MAX; retries++) { + /* Program the chip. */ + it6251_program_regs(); + + /* Wait for video stable. */ + for (tries = 0; tries < 100; tries++) { + reg = i2c_reg_read(caddr, 0x17); + /* Test Link CFG, STS, LCS read done. */ + if ((reg & 0xe0) != 0xe0) { + /* Not yet, wait a bit more. */ + mdelay(2); + continue; + } + + /* Test if the video input is stable. */ + if (it6251_is_stable()) + return 0; + } + /* + * If we couldn't stabilize, requeue and try again, + * because it means that the LVDS channel isn't + * stable yet. + */ + printf("Display didn't stabilize.\n"); + printf("This may be because the LVDS port is still in powersave mode.\n"); + mdelay(50); + } + + return -EINVAL; +} + +static void enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int lvds_enabled; + +static void enable_lvds(struct display_info_t const *dev) +{ + if (lvds_enabled) + return; + + /* ITE IT6251 power enable. */ + gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0); + mdelay(10); + gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1); + mdelay(20); + lvds_enabled = 1; +} + +static int detect_lvds(struct display_info_t const *dev) +{ + int ret, loops = 250; + + enable_lvds(dev); + + ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); + if (ret) { + puts("Cannot select IT6251 I2C bus.\n"); + return 0; + } + + /* Wait up-to ~250 mS for the LVDS to come up. */ + while (--loops) { + ret = it6251_ready(); + if (ret) + return ret; + + mdelay(1); + } + + return 0; +} + +struct display_info_t const displays[] = { + { + /* HDMI Output */ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + }, + }, { + /* LVDS Output: N133HSE-EA1 Rev. C1 */ + .bus = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_lvds, + .enable = enable_lvds, + .mode = { + .name = "Chimei-FHD", + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 15384, + .left_margin = 148, + .right_margin = 88, + .upper_margin = 36, + .lower_margin = 4, + .hsync_len = 44, + .vsync_len = 5, + .sync = FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, + }, + }, +}; + +size_t display_count = ARRAY_SIZE(displays); + +static void enable_vpll(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int timeout = 100000; + + setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_DIV_SELECT | + BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, + BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | + BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1)); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_BYPASS, + BM_ANADIG_PLL_VIDEO_ENABLE); +} + +void setup_display_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + enable_ipu_clock(); + enable_vpll(); + imx_setup_hdmi(); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + /* Switch LDB DI0 to PLL5 (Video PLL) */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, + (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); + + /* LDB clock div by 3.5 */ + clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + /* DI0 clock derived from ldb_di0_clk */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + ); + + /* Enable both LVDS channels, both connected to DI0. */ + writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA | + IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_SPLIT_MODE_EN_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_LVDS1_MUX_CTL_MASK, + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) + ); +} + +void setup_display_lvds(void) +{ + int ret; + + ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); + if (ret) { + puts("Cannot select LVDS-to-eDP I2C bus.\n"); + return; + } + + /* The IT6251 should be ready now, if it's not, it's not connected. */ + ret = it6251_ready(); + if (!ret) + return; + + /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */ + ret = it6251_init(); + if (!ret) { + /* Backlight power enable. */ + gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1); + /* PWM backlight pin, always on for full brightness. */ + gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1); + } +} diff --git a/board/kup/Makefile b/board/kup/Makefile deleted file mode 100644 index 05be72f484..0000000000 --- a/board/kup/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o kup.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/kup/common/flash.c b/board/kup/common/flash.c deleted file mode 100644 index 77c7b6ca88..0000000000 --- a/board/kup/common/flash.c +++ /dev/null @@ -1,499 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -#define CONFIG_FLASH_16BIT - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - vu_short *s_addr=(vu_short*)addr; - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x0090; - - value = s_addr[0]; - value = value|(value<<16); - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = s_addr[1]; - value = value|(value<<16); - - switch (value) { - case FUJI_ID_29F800BA: - info->flash_id += FLASH_AM400T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - s_addr = (volatile unsigned short *)(info->start[i]); - info->protect[i] = s_addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - s_addr = (volatile unsigned short *)info->start[0]; - *s_addr = 0x00F0; /* reset bank */ - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect; - ulong start, now, last; -#ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short*)addr; -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } -/*#ifndef CONFIG_FLASH_16BIT - ulong type; - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return; - } -#endif*/ - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ -#ifdef CONFIG_FLASH_16BIT - vu_short *s_sect_addr = (vu_short*)(info->start[sect]); -#else - vu_long *sect_addr = (vu_long*)(info->start[sect]); -#endif - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#ifdef CONFIG_FLASH_16BIT - - /*printf("\ns_sect_addr=%x",s_sect_addr);*/ - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x0080; - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_sect_addr[0] = 0x0030; -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00800080; - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - sect_addr[0] = 0x00300030; -#endif - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#ifdef CONFIG_FLASH_16BIT - while ((s_sect_addr[0] & 0x0080) != 0x0080) { -#else - while ((sect_addr[0] & 0x00800080) != 0x00800080) { -#endif - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - } - } - - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#ifdef CONFIG_FLASH_16BIT - s_addr[0] = 0x00F0; /* reset bank */ -#else - addr[0] = 0x00F000F0; /* reset bank */ -#endif - - printf (" done\n"); - return 0; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - -#ifdef CONFIG_FLASH_16BIT - vu_short high_data; - vu_short low_data; - vu_short *s_addr = (vu_short*)addr; -#endif - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - -#ifdef CONFIG_FLASH_16BIT - /* Write the 16 higher-bits */ - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - high_data = ((data>>16) & 0x0000ffff); - - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x00A0; - - *((vu_short *)dest) = high_data; - - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - - /* Write the 16 lower-bits */ -#endif - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#ifdef CONFIG_FLASH_16BIT - dest += 0x2; - low_data = (data & 0x0000ffff); - - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x00A0; - *((vu_short *)dest) = low_data; - -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00A000A0; - *((vu_long *)dest) = data; -#endif - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - -#ifdef CONFIG_FLASH_16BIT - while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { -#else - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { -#endif - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c deleted file mode 100644 index 03ab018c89..0000000000 --- a/board/kup/common/kup.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2004 - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include "kup.h" -#include - - -int misc_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf8xx_t *siu = &immap->im_siu_conf; - - while (in_be32(&siu->sc_sipend) & 0x20000000) { - debug("waiting for 5V VCC\n"); - } - - /* RS232 / RS485 default is RS232 */ - clrbits_be16(&immap->im_ioport.iop_padat, PA_RS485); - clrbits_be16(&immap->im_ioport.iop_papar, PA_RS485); - clrbits_be16(&immap->im_ioport.iop_paodr, PA_RS485); - setbits_be16(&immap->im_ioport.iop_padir, PA_RS485); - - /* IO Reset min 1 msec */ - setbits_be16(&immap->im_ioport.iop_padat, - (PA_RESET_IO_01 | PA_RESET_IO_02)); - clrbits_be16(&immap->im_ioport.iop_papar, - (PA_RESET_IO_01 | PA_RESET_IO_02)); - clrbits_be16(&immap->im_ioport.iop_paodr, - (PA_RESET_IO_01 | PA_RESET_IO_02)); - setbits_be16(&immap->im_ioport.iop_padir, - (PA_RESET_IO_01 | PA_RESET_IO_02)); - udelay(1000); - clrbits_be16(&immap->im_ioport.iop_padat, - (PA_RESET_IO_01 | PA_RESET_IO_02)); - return (0); -} - -#ifdef CONFIG_IDE_LED -void ide_led(uchar led, uchar status) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* We have one led for both pcmcia slots */ - if (status) - clrbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW); - else - setbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW); -} -#endif - -void poweron_key(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - clrbits_be16(&immap->im_ioport.iop_pcpar, PC_SWITCH1); - clrbits_be16(&immap->im_ioport.iop_pcdir, PC_SWITCH1); - - if (in_be16(&immap->im_ioport.iop_pcdat) & (PC_SWITCH1)) - setenv("key1", "off"); - else - setenv("key1", "on"); -} diff --git a/board/kup/common/kup.h b/board/kup/common/kup.h deleted file mode 100644 index a1369aed62..0000000000 --- a/board/kup/common/kup.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004 - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __KUP_H -#define __KUP_H - -#define PA_8 0x0080 -#define PA_9 0x0040 -#define PA_10 0x0020 -#define PA_11 0x0010 -#define PA_12 0x0008 - -#define PB_14 0x00020000 -#define PB_15 0x00010000 -#define PB_16 0x00008000 -#define PB_17 0x00004000 - -#define PC_4 0x0800 -#define PC_5 0x0400 -#define PC_9 0x0040 - -#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ -#define PA_LED_YELLOW PA_8 -#define PA_RESET_IO_01 PA_9 /* Reset left IO */ -#define PA_RESET_IO_02 PA_10 /* Reset right IO */ -#define PB_PROG_IO_01 PB_15 /* Program left IO */ -#define PB_PROG_IO_02 PB_16 /* Program right IO */ -#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off */ -#define PB_LCD_PWM PB_17 /* PB 17 */ -#define PC_SWITCH1 PC_9 /* Reboot switch */ - - -extern void poweron_key(void); -extern void load_sernum_ethaddr(void); - -#endif /* __KUP_H */ diff --git a/board/kup/common/load_sernum_ethaddr.c b/board/kup/common/load_sernum_ethaddr.c deleted file mode 100644 index 20fe799cdc..0000000000 --- a/board/kup/common/load_sernum_ethaddr.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/*----------------------------------------------------------------------- - * Process Hardware Information Block: - * - * If we boot on a system fresh from factory, check if the Hardware - * Information Block exists and save the information it contains. - * - * The KUP Hardware Information Block is defined as - * follows: - * - located in first flash bank - * - starts at offset CONFIG_SYS_HWINFO_OFFSET - * - size CONFIG_SYS_HWINFO_SIZE - * - * Internal structure: - * - sequence of ASCII character lines - * - fields separated by - * - last field terminated by NUL character (0x00) - * - * Fields in Hardware Information Block: - * 1) Module Type - * 2) MAC Address - * 3) .... - */ - - -#define ETHADDR_TOKEN "ethaddr=" -#define LCD_TOKEN "lcd=" - -void load_sernum_ethaddr (void) -{ - unsigned char *hwi; - char *var; - unsigned char hwi_stack[CONFIG_SYS_HWINFO_SIZE]; - char *p; - - hwi = (unsigned char *) (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); - if (*((unsigned long *) hwi) != (unsigned long) CONFIG_SYS_HWINFO_MAGIC) { - printf ("HardwareInfo not found!\n"); - return; - } - memcpy (hwi_stack, hwi, CONFIG_SYS_HWINFO_SIZE); - - /* - ** ethaddr - */ - var = strstr ((char *)hwi_stack, ETHADDR_TOKEN); - if (var) { - var += sizeof (ETHADDR_TOKEN) - 1; - p = strchr (var, '\r'); - if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) { - *p = '\0'; - setenv ("ethaddr", var); - *p = '\r'; - } - } - /* - ** lcd - */ - var = strstr ((char *)hwi_stack, LCD_TOKEN); - if (var) { - var += sizeof (LCD_TOKEN) - 1; - p = strchr (var, '\r'); - if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) { - *p = '\0'; - setenv ("lcd", var); - *p = '\r'; - } - } -} diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c deleted file mode 100644 index 61ba586e17..0000000000 --- a/board/kup/common/pcmcia.c +++ /dev/null @@ -1,221 +0,0 @@ -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "KUP" - -#define KUP4K_PCMCIA_B_3V3 (0x00020000) - -int pcmcia_hardware_enable(int slot) -{ - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(slot); - pcmp->pcmc_per &= ~PCMCIA_MASK(slot); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - udelay(2500); - - /* - * Configure Port B pins for - * 3 Volts enable - */ - if (slot) { /* Slot A is built-in */ - cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; - cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; - /* remove all power */ - cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ - } - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot); - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { - puts (" 5.0V card found: NOT SUPPORTED !!!\n"); - } else { - if(slot) - cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; - puts (" 3.3V card found: "); - } -#if 0 - /* VCC switch error flag, PCMCIA slot INPACK_ pin */ - cp->cp_pbdir &= ~(0x0020 | 0x0010); - cp->cp_pbpar &= ~(0x0020 | 0x0010); - udelay(500000); -#endif - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* remove all power */ - if (slot) - cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " \ - PCMCIA_BOARD_MSG \ - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - if (!slot) /* Slot A is not configurable */ - return 0; - - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug ("PCMCIA power OFF\n"); - /* - * Configure Port B pins for - * 3 Volts enable - */ - cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; - cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; - /* remove all power */ - cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ - - switch(vcc) { - case 0: break; - case 33: - cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; - debug ("PCMCIA powered at 3.3V\n"); - break; - case 50: - debug ("PCMCIA: 5Volt vcc not supported\n"); - break; - default: - puts("PCMCIA: vcc not supported"); - break; - } - udelay(10000); - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4))) - ? "only 5 V --> NOT SUPPORTED" - : "can do 3.3V"); - - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile deleted file mode 100644 index 8ab0664443..0000000000 --- a/board/kup/kup4k/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c deleted file mode 100644 index a4c199859c..0000000000 --- a/board/kup/kup4k/kup4k.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "../common/kup.h" -#include - -static unsigned char swapbyte(unsigned char c); -static int read_diag(void); - -DECLARE_GLOBAL_DATA_PTR; - -/* ----------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ----------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - uchar rev,mod,tmp,pcf,ak_rev,ak_mod; - - /* - * Init ChipSelect #4 (CAN + HW-Latch) - */ - out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); - out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); - - /* - * Init ChipSelect #5 (S1D13768) - */ - out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5); - out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5); - - tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR)); - rev = (tmp & 0xF8) >> 3; - mod = (tmp & 0x07); - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - if (read_diag()) - gd->flags &= ~GD_FLG_SILENT; - - printf("Board: KUP4K Rev %d.%d AK:",rev,mod); - /* - * TI Application report: Before using the IO as an input, - * a high must be written to the IO first - */ - pcf = 0xFF; - i2c_write(0x21, 0, 0 , &pcf, 1); - if (i2c_read(0x21, 0, 0, &pcf, 1)) { - puts("n/a\n"); - } else { - ak_rev = (pcf & 0xF8) >> 3; - ak_mod = (pcf & 0x07); - printf("%d.%d\n", ak_rev, ak_mod); - } - return 0; -} - -/* ----------------------------------------------------------------------- */ - - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size = 0; - uchar *latch, rev, tmp; - - /* - * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision - * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB - */ - out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); - out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); - - latch = (uchar *)0x90000200; - tmp = swapbyte(*latch); - rev = (tmp & 0xF8) >> 3; - - upmconfig(UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - - out_be32(&memctl->memc_mar, 0x00000088); - /* no refresh yet */ - if(rev >= 7) { - out_be32(&memctl->memc_mamr, - CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE))); - } else { - out_be32(&memctl->memc_mamr, - CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE))); - } - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - /* SDRAM bank 0 */ - out_be32(&memctl->memc_mcr, 0x80002105); - udelay(1); - out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */ - udelay(1); - out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ - udelay(1); - - /* SDRAM bank 1 */ - out_be32(&memctl->memc_mcr, 0x80004105); - udelay(1); - out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */ - udelay(1); - out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ - udelay(1); - - /* SDRAM bank 2 */ - out_be32(&memctl->memc_mcr, 0x80006105); - udelay(1); - out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */ - udelay(1); - out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ - udelay(1); - - setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ - udelay(1000); - - out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - udelay(1000); - if(rev >= 7) { - size = 32 * 3 * 1024 * 1024; - out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL); - out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL); - out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL); - out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL); - out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL); - out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL); - } else { - size = 16 * 3 * 1024 * 1024; - out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL); - out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL); - out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL); - out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL); - out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL); - out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL); - } - return (size); -} - -/* ----------------------------------------------------------------------- */ - - -int misc_init_r(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#ifdef CONFIG_IDE_LED - /* Configure PA8 as output port */ - setbits_be16(&immap->im_ioport.iop_padir, PA_8); - setbits_be16(&immap->im_ioport.iop_paodr, PA_8); - clrbits_be16(&immap->im_ioport.iop_papar, PA_8); - setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */ -#endif - load_sernum_ethaddr(); - setenv("hw","4k"); - poweron_key(); - return (0); -} - - -static int read_diag(void) -{ - int diag; - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */ - clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ - setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */ - clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ - setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */ - udelay(500); - if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) { - clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */ - udelay(500); - if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4) - diag = 0; - else - diag = 1; - } else { - diag = 0; - } - clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */ - return (diag); -} - -static unsigned char swapbyte(unsigned char c) -{ - unsigned char result = 0; - int i = 0; - - for(i = 0; i < 8; ++i) { - result = result << 1; - result |= (c & 1); - c = c >> 1; - } - return result; -} - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/kup/kup4k/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug deleted file mode 100644 index 0ea27e8759..0000000000 --- a/board/kup/kup4k/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile deleted file mode 100644 index 8ab0664443..0000000000 --- a/board/kup/kup4x/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c deleted file mode 100644 index 0e51bd1c89..0000000000 --- a/board/kup/kup4x/kup4x.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "../common/kup.h" -#include - - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - uchar latch, rev, mod; - - /* - * Init ChipSelect #4 (CAN + HW-Latch) - */ - out_be32(&memctl->memc_or4, 0xFFFF8926); - out_be32(&memctl->memc_br4, 0x90000401); - - latch = in_8( (unsigned char *) LATCH_ADDR); - rev = (latch & 0xF8) >> 3; - mod = (latch & 0x03); - - printf("Board: KUP4X Rev %d.%d\n", rev, mod); - - return 0; -} - - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - - out_be32(&memctl->memc_mar, 0x00000088); - - out_be32(&memctl->memc_mamr, - CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - /* SDRAM bank 0 */ - out_be32(&memctl->memc_mcr, 0x80002105); - udelay(1); - out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */ - udelay(1); - out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ - udelay(1); - - /* SDRAM bank 1 */ - out_be32(&memctl->memc_mcr, 0x80004105); - udelay(1); - out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */ - udelay(1); - out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ - udelay(1); - - /* SDRAM bank 2 */ - out_be32(&memctl->memc_mcr, 0x80006105); - udelay(1); - out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */ - udelay(1); - out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ - udelay(1); - - /* SDRAM bank 3 */ - out_be32(&memctl->memc_mcr, 0x8000C105); - udelay(1); - out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */ - udelay(1); - out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */ - udelay(1); - - setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ - - udelay(1000); - /* 4 x 16 MB */ - out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - udelay(1000); - out_be32(&memctl->memc_or1, 0xFF000A00); - out_be32(&memctl->memc_br1, 0x00000081); - out_be32(&memctl->memc_or2, 0xFE000A00); - out_be32(&memctl->memc_br2, 0x01000081); - out_be32(&memctl->memc_or3, 0xFD000A00); - out_be32(&memctl->memc_br3, 0x02000081); - out_be32(&memctl->memc_or6, 0xFC000A00); - out_be32(&memctl->memc_br6, 0x03000081); - udelay(10000); - - return (4 * 16 * 1024 * 1024); -} - -int misc_init_r(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#ifdef CONFIG_IDE_LED - /* Configure PA8 as output port */ - setbits_be16(&immap->im_ioport.iop_padir, PA_8); - setbits_be16(&immap->im_ioport.iop_paodr, PA_8); - clrbits_be16(&immap->im_ioport.iop_papar, PA_8); - setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */ -#endif - load_sernum_ethaddr(); - setenv("hw", "4x"); - poweron_key(); - return 0; -} diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/kup/kup4x/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug deleted file mode 100644 index 0ea27e8759..0000000000 --- a/board/kup/kup4x/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/linkstation/Makefile b/board/linkstation/Makefile deleted file mode 100644 index 98f283e399..0000000000 --- a/board/linkstation/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -OBJS = $(BOARD).o ide.o hwctl.o avr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(OBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/linkstation/avr.c b/board/linkstation/avr.c deleted file mode 100644 index 62e586ba09..0000000000 --- a/board/linkstation/avr.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * avr.c - * - * AVR functions - * - * Copyright (C) 2006 Mihai Georgian - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include - -/* Button codes from the AVR */ -#define PWRR 0x20 /* Power button release */ -#define PWRP 0x21 /* Power button push */ -#define RESR 0x22 /* Reset button release */ -#define RESP 0x23 /* Reset button push */ -#define AVRINIT 0x33 /* Init complete */ -#define AVRRESET 0x31 /* Reset request */ - -/* LED commands */ -#define PWRBLINKSTRT '[' /* Blink power LED */ -#define PWRBLINKSTOP 'Z' /* Solid power LED */ -#define HDDLEDON 'W' /* HDD LED on */ -#define HDDLEDOFF 'V' /* HDD LED off */ -#define HDDBLINKSTRT 'Y' /* HDD LED start blink */ -#define HDDBLINKSTOP 'X' /* HDD LED stop blink */ - -/* Timings for LEDs blinking to show choice */ -#define PULSETIME 250 /* msecs */ -#define LONGPAUSE (5 * PULSETIME) - -/* Button press times */ -#define PUSHHOLD 1000 /* msecs */ -#define NOBUTTON (6 * (LONGPAUSE+PULSETIME)) - -/* Boot and console choices */ -#define MAX_BOOT_CHOICE 3 - -static char *consoles[] = { - "serial", -#if defined(CONFIG_NETCONSOLE) - "nc", -#endif -}; -#define MAX_CONS_CHOICE (sizeof(consoles)/sizeof(char *)) - -#if !defined(CONFIG_NETCONSOLE) -#define DEF_CONS_CHOICE 0 -#else -#define DEF_CONS_CHOICE 1 -#endif - -#define perror(fmt, args...) printf("%s: " fmt, __FUNCTION__ , ##args) - -extern void miconCntl_SendCmd(unsigned char dat); -extern void miconCntl_DisWDT(void); - -static int boot_stop; - -static int boot_choice = 1; -static int cons_choice = DEF_CONS_CHOICE; - -static char envbuffer[16]; - -void init_AVR_DUART (void) -{ - NS16550_t AVR_port = (NS16550_t) CONFIG_SYS_NS16550_COM2; - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / 9600; - - /* - * AVR port init sequence taken from - * the original Linkstation init code - * Normal U-Boot serial reinit doesn't - * work because the AVR uses even parity - */ - AVR_port->lcr = 0x00; - AVR_port->ier = 0x00; - AVR_port->lcr = UART_LCR_BKSE; - AVR_port->dll = clock_divisor & 0xff; - AVR_port->dlm = (clock_divisor >> 8) & 0xff; - AVR_port->lcr = UART_LCR_WLS_8 | UART_LCR_PEN | UART_LCR_EPS; - AVR_port->mcr = 0x00; - AVR_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR; - - miconCntl_DisWDT(); - - boot_stop = 0; - miconCntl_SendCmd(PWRBLINKSTRT); -} - -static inline int avr_tstc(void) -{ - return (NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2)); -} - -static inline char avr_getc(void) -{ - return (NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2)); -} - -static int push_timeout(char button_code) -{ - ulong push_start = get_timer(0); - while (get_timer(push_start) <= PUSHHOLD) - if (avr_tstc() && avr_getc() == button_code) - return 0; - return 1; -} - -static void next_boot_choice(void) -{ - ulong return_start; - ulong pulse_start; - int on_times; - int button_on; - int led_state; - char c; - - button_on = 0; - return_start = get_timer(0); - - on_times = boot_choice; - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - pulse_start = get_timer(0); - - while (get_timer(return_start) <= NOBUTTON || button_on) { - if (avr_tstc()) { - c = avr_getc(); - if (c == PWRP) - button_on = 1; - else if (c == PWRR) { - button_on = 0; - return_start = get_timer(0); - if (++boot_choice > MAX_BOOT_CHOICE) - boot_choice = 1; - sprintf(envbuffer, "bootcmd%d", boot_choice); - if (getenv(envbuffer)) { - sprintf(envbuffer, "run bootcmd%d", boot_choice); - setenv("bootcmd", envbuffer); - } - on_times = boot_choice; - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - pulse_start = get_timer(0); - } else { - perror("Unexpected code: 0x%02X\n", c); - } - } - if (on_times && get_timer(pulse_start) > PULSETIME) { - if (led_state == 1) { - --on_times; - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - } else { - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - } - pulse_start = get_timer(0); - } - if (!on_times && get_timer(pulse_start) > LONGPAUSE) { - on_times = boot_choice; - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - pulse_start = get_timer(0); - } - } - if (led_state) - miconCntl_SendCmd(HDDLEDOFF); -} - -void next_cons_choice(int console) -{ - ulong return_start; - ulong pulse_start; - int on_times; - int button_on; - int led_state; - char c; - - button_on = 0; - cons_choice = console; - return_start = get_timer(0); - - on_times = cons_choice+1; - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - pulse_start = get_timer(0); - - while (get_timer(return_start) <= NOBUTTON || button_on) { - if (avr_tstc()) { - c = avr_getc(); - if (c == RESP) - button_on = 1; - else if (c == RESR) { - button_on = 0; - return_start = get_timer(0); - cons_choice = (cons_choice + 1) % MAX_CONS_CHOICE; - console_assign(stdin, consoles[cons_choice]); - console_assign(stdout, consoles[cons_choice]); - console_assign(stderr, consoles[cons_choice]); - on_times = cons_choice+1; - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - pulse_start = get_timer(0); - } else { - perror("Unexpected code: 0x%02X\n", c); - } - } - if (on_times && get_timer(pulse_start) > PULSETIME) { - if (led_state == 0) { - --on_times; - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - } else { - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - } - pulse_start = get_timer(0); - } - if (!on_times && get_timer(pulse_start) > LONGPAUSE) { - on_times = cons_choice+1; - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - pulse_start = get_timer(0); - } - } - if (led_state); - miconCntl_SendCmd(HDDLEDOFF); -} - -int avr_input(void) -{ - char avr_button; - - if (!avr_tstc()) - return 0; - - avr_button = avr_getc(); - switch (avr_button) { - case PWRP: - if (push_timeout(PWRR)) { - /* Timeout before power button release */ - boot_stop = ~boot_stop; - if (boot_stop) - miconCntl_SendCmd(PWRBLINKSTOP); - else - miconCntl_SendCmd(PWRBLINKSTRT); - /* Wait for power button release */ - while (avr_getc() != PWRR) - ; - } else - /* Power button released */ - next_boot_choice(); - break; - case RESP: - /* Wait for Reset button release */ - while (avr_getc() != RESR) - ; - next_cons_choice(cons_choice); - break; - case AVRINIT: - return 0; - default: - perror("Unexpected code: 0x%02X\n", avr_button); - return 0; - } - if (boot_stop) - return (-3); - else - return (-2); -} - -void avr_StopBoot(void) -{ - boot_stop = ~0; - miconCntl_SendCmd(PWRBLINKSTOP); -} diff --git a/board/linkstation/hwctl.c b/board/linkstation/hwctl.c deleted file mode 100644 index d2090be1ad..0000000000 --- a/board/linkstation/hwctl.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * hwctl.c - * - * LinkStation HW Control Driver - * - * Copyright (C) 2001-2004 BUFFALO INC. - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL), incorporated herein by reference. - * Drivers based on or derived from this code fall under the GPL and must - * retain the authorship, copyright and license notice. This file is not - * a complete program and may only be used when the entire operating - * system is licensed under the GPL. - * - */ - -#include -#include -#include -#include - -#define AVR_PORT CONFIG_SYS_NS16550_COM2 - -/* 2005.5.10 BUFFALO add */ -/*--------------------------------------------------------------*/ -static inline void miconCntl_SendUart(unsigned char dat) -{ - out_8((unsigned char *)AVR_PORT, dat); - mdelay(1); -} - -/*--------------------------------------------------------------*/ -void miconCntl_SendCmd(unsigned char dat) -{ - int i; - - for (i=0; i<4; i++){ - miconCntl_SendUart(dat); - } -} - -/*--------------------------------------------------------------*/ -void miconCntl_FanLow(void) -{ -#ifdef CONFIG_HTGL - miconCntl_SendCmd(0x5C); -#endif -} - -/*--------------------------------------------------------------*/ -void miconCntl_FanHigh(void) -{ -#ifdef CONFIG_HTGL - miconCntl_SendCmd(0x5D); -#endif -} - -/*--------------------------------------------------------------*/ -/* 1000Mbps */ -void miconCntl_Eth1000M(int up) -{ -#ifdef CONFIG_HTGL - if (up) - miconCntl_SendCmd(0x93); - else - miconCntl_SendCmd(0x92); -#else - if (up) - miconCntl_SendCmd(0x5D); - else - miconCntl_SendCmd(0x5C); -#endif -} - -/*--------------------------------------------------------------*/ -/* 100Mbps */ -void miconCntl_Eth100M(int up) -{ -#ifdef CONFIG_HTGL - if (up) - miconCntl_SendCmd(0x91); - else - miconCntl_SendCmd(0x90); -#else - if (up) - miconCntl_SendCmd(0x5C); -#endif -} - -/*--------------------------------------------------------------*/ -/* 10Mbps */ -void miconCntl_Eth10M(int up) -{ -#ifdef CONFIG_HTGL - if (up) - miconCntl_SendCmd(0x8F); - else - miconCntl_SendCmd(0x8E); -#else - if (up) - miconCntl_SendCmd(0x5C); -#endif -} - -/*--------------------------------------------------------------*/ -/* */ -void miconCntl_5f(void) -{ - miconCntl_SendCmd(0x5F); - mdelay(100); -} - -/*--------------------------------------------------------------*/ -/* "reboot start" signal */ -void miconCntl_Reboot(void) -{ - miconCntl_SendCmd(0x43); -} - -/*--------------------------------------------------------------*/ -/* Disable watchdog timer */ -void miconCntl_DisWDT(void) -{ - miconCntl_SendCmd(0x41); /* A */ - miconCntl_SendCmd(0x46); /* F */ - miconCntl_SendCmd(0x4A); /* J */ - miconCntl_SendCmd(0x3E); /* > */ - miconCntl_SendCmd(0x56); /* V */ - miconCntl_SendCmd(0x3E); /* > */ - miconCntl_SendCmd(0x5A); /* Z */ - miconCntl_SendCmd(0x56); /* V */ - miconCntl_SendCmd(0x4B); /* K */ -} diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c deleted file mode 100644 index 7b3fe65cff..0000000000 --- a/board/linkstation/ide.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* ide.c - ide support functions */ - - -#include - -#ifdef CONFIG_CMD_IDE -#include -#include -#include - -#define IT8212_PCI_CpuCONTROL 0x5e -#define IT8212_PCI_PciModeCONTROL 0x50 -#define IT8212_PCI_IdeIoCONFIG 0x40 -#define IT8212_PCI_IdeBusSkewCONTROL 0x4c -#define IT8212_PCI_IdeDrivingCURRENT 0x42 - -extern struct pci_controller hose; - -int ide_preinit (void) -{ - int status; - pci_dev_t devbusfn; - int l; - - status = 1; - for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { - ide_bus_offset[l] = -ATA_STATUS; - } - devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0); - if (devbusfn == -1) - devbusfn = pci_find_device(PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0); - if (devbusfn != -1) { - u32 ide_bus_offset32; - - status = 0; - - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - &ide_bus_offset32); - ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe; - ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, - ide_bus_offset[0] & 0xfffffffe, - PCI_REGION_IO); - if (CONFIG_SYS_IDE_MAXBUS > 1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, - (u32 *) &ide_bus_offset[1]); - ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, - ide_bus_offset[1] & 0xfffffffe, - PCI_REGION_IO); - } - } - - if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) { - pci_write_config_byte(devbusfn, IT8212_PCI_CpuCONTROL, 0x01); - pci_write_config_byte(devbusfn, IT8212_PCI_PciModeCONTROL, 0x00); - pci_write_config_word(devbusfn, PCI_COMMAND, 0x0047); -#ifdef CONFIG_IT8212_SECONDARY_ENABLE - pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0xA0F3); -#else - pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0x8031); -#endif - pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204); -/* __LS_COMMENT__ BUFFALO changed 2004.11.10 changed for EMI */ - pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */ - pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00); - } - - return (status); -} - -void ide_set_reset (int flag) { - return; -} - -#endif /* CONFIG_CMD_IDE */ diff --git a/board/linkstation/linkstation.c b/board/linkstation/linkstation.c deleted file mode 100644 index 75cda8681f..0000000000 --- a/board/linkstation/linkstation.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * linkstation.c - * - * Misc LinkStation specific functions - * - * Copyright (C) 2006 Mihai Georgian - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_PCI -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern void init_AVR_DUART(void); - -int checkboard (void) -{ - char *p; - bd_t *bd = gd->bd; - - init_AVR_DUART(); - - if ((p = getenv ("console_nr")) != NULL) { - unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; - - bd->bi_baudrate &= ~3; - bd->bi_baudrate |= con_nr & 3; - } - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE)); -} - -/* - * Initialize PCI Devices - */ -#ifdef CONFIG_PCI - -#ifndef CONFIG_PCI_PNP - -static struct pci_config_table pci_linkstation_config_table[] = { - /* vendor, device, class */ - /* bus, dev, func */ - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0b, 0, /* AN983B or RTL8110S */ - /* ethernet controller */ - pci_cfgfunc_config_device, { PCI_ETH_IOADDR, - PCI_ETH_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0c, 0, /* SII680 or IT8211AF */ - /* ide controller */ - pci_cfgfunc_config_device, { PCI_IDE_IOADDR, - PCI_IDE_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0e, 0, /* D720101 USB controller, 1st USB 1.1 */ - pci_cfgfunc_config_device, { PCI_USB0_IOADDR, - PCI_USB0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0e, 1, /* D720101 USB controller, 2nd USB 1.1 */ - pci_cfgfunc_config_device, { PCI_USB1_IOADDR, - PCI_USB1_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0e, 2, /* D720101 USB controller, USB 2.0 */ - pci_cfgfunc_config_device, { PCI_USB2_IOADDR, - PCI_USB2_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_linkstation_config_table, -#endif -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); - - /* Reset USB 1.1 */ - /* Haven't seen any change without these on a HG, maybe it is - * needed on other models */ - out_le32((volatile unsigned*)(PCI_USB0_MEMADDR + 8), 1); - out_le32((volatile unsigned*)(PCI_USB1_MEMADDR + 8), 1); -} -#endif /* CONFIG_PCI */ - -#define UART_DCR 0x80004511 -int board_early_init_f (void) -{ - /* set DUART mode */ - out_8((volatile u8*)UART_DCR, 1); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/logicpd/am3517evm/Kconfig b/board/logicpd/am3517evm/Kconfig new file mode 100644 index 0000000000..901f6094bb --- /dev/null +++ b/board/logicpd/am3517evm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AM3517_EVM + +config SYS_BOARD + default "am3517evm" + +config SYS_VENDOR + default "logicpd" + +config SYS_CONFIG_NAME + default "am3517_evm" + +endif diff --git a/board/logicpd/am3517evm/MAINTAINERS b/board/logicpd/am3517evm/MAINTAINERS new file mode 100644 index 0000000000..7f03ac12ee --- /dev/null +++ b/board/logicpd/am3517evm/MAINTAINERS @@ -0,0 +1,6 @@ +AM3517EVM BOARD +M: Vaibhav Hiremath +S: Maintained +F: board/logicpd/am3517evm/ +F: include/configs/am3517_evm.h +F: configs/am3517_evm_defconfig diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile index 2b4f0b6b2b..73b11dfbf0 100644 --- a/board/logicpd/am3517evm/Makefile +++ b/board/logicpd/am3517evm/Makefile @@ -8,21 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := am3517evm.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := am3517evm.o diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 1cabc80b8a..24be6eabfc 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define AM3517_IP_SW_RESET 0x48002598 +#define CPGMACSS_SW_RST (1 << 1) + /* * Routine: board_init * Description: Early hardware init. @@ -98,14 +102,42 @@ static void am3517_evm_musb_init(void) */ int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + volatile unsigned int ctr; + u32 reset; + +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif dieid_num_r(); am3517_evm_musb_init(); + /* activate PHY reset */ + gpio_direction_output(30, 0); + gpio_set_value(30, 0); + + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* deactivate PHY reset */ + gpio_set_value(30, 1); + + /* allow the PHY to stabilize and settle down */ + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* ensure that the module is out of reset */ + reset = readl(AM3517_IP_SW_RESET); + reset &= (~CPGMACSS_SW_RST); + writel(reset,AM3517_IP_SW_RESET); + return 0; } @@ -143,4 +175,3 @@ int board_eth_init(bd_t *bis) return n; } #endif - diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 704af847a7..a6a55eef49 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -315,7 +315,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ /*SYS_nRESWARM */\ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ /* - GPIO30 */\ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ /* - PEN_IRQ */\ @@ -333,7 +333,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/logicpd/imx27lite/Kconfig b/board/logicpd/imx27lite/Kconfig new file mode 100644 index 0000000000..c7de2e3814 --- /dev/null +++ b/board/logicpd/imx27lite/Kconfig @@ -0,0 +1,31 @@ +if TARGET_IMX27LITE + +config SYS_BOARD + default "imx27lite" + +config SYS_VENDOR + default "logicpd" + +config SYS_SOC + default "mx27" + +config SYS_CONFIG_NAME + default "imx27lite" + +endif + +if TARGET_MAGNESIUM + +config SYS_BOARD + default "imx27lite" + +config SYS_VENDOR + default "logicpd" + +config SYS_SOC + default "mx27" + +config SYS_CONFIG_NAME + default "magnesium" + +endif diff --git a/board/logicpd/imx27lite/MAINTAINERS b/board/logicpd/imx27lite/MAINTAINERS new file mode 100644 index 0000000000..a7b22ac049 --- /dev/null +++ b/board/logicpd/imx27lite/MAINTAINERS @@ -0,0 +1,12 @@ +IMX27LITE BOARD +M: Wolfgang Denk +S: Maintained +F: board/logicpd/imx27lite/ +F: include/configs/imx27lite.h +F: configs/imx27lite_defconfig + +MAGNESIUM BOARD +M: Heiko Schocher +S: Maintained +F: include/configs/magnesium.h +F: configs/magnesium_defconfig diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile index c42bd4c15c..50a3da62ed 100644 --- a/board/logicpd/imx27lite/Makefile +++ b/board/logicpd/imx27lite/Makefile @@ -5,24 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := imx27lite.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := imx27lite.o +obj-y += lowlevel_init.o diff --git a/board/logicpd/imx31_litekit/Kconfig b/board/logicpd/imx31_litekit/Kconfig new file mode 100644 index 0000000000..d90f854a18 --- /dev/null +++ b/board/logicpd/imx31_litekit/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX31_LITEKIT + +config SYS_BOARD + default "imx31_litekit" + +config SYS_VENDOR + default "logicpd" + +config SYS_SOC + default "mx31" + +config SYS_CONFIG_NAME + default "imx31_litekit" + +endif diff --git a/board/logicpd/imx31_litekit/MAINTAINERS b/board/logicpd/imx31_litekit/MAINTAINERS new file mode 100644 index 0000000000..8e3608e0af --- /dev/null +++ b/board/logicpd/imx31_litekit/MAINTAINERS @@ -0,0 +1,6 @@ +IMX31_LITEKIT BOARD +#M: - +S: Maintained +F: board/logicpd/imx31_litekit/ +F: include/configs/imx31_litekit.h +F: configs/imx31_litekit_defconfig diff --git a/board/logicpd/imx31_litekit/Makefile b/board/logicpd/imx31_litekit/Makefile index 33cacacc5f..3fd71c8deb 100644 --- a/board/logicpd/imx31_litekit/Makefile +++ b/board/logicpd/imx31_litekit/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := imx31_litekit.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := imx31_litekit.o +obj-y += lowlevel_init.o diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig new file mode 100644 index 0000000000..03d272a806 --- /dev/null +++ b/board/logicpd/omap3som/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_LOGIC + +config SYS_BOARD + default "omap3som" + +config SYS_VENDOR + default "logicpd" + +config SYS_CONFIG_NAME + default "omap3_logic" + +endif diff --git a/board/logicpd/omap3som/MAINTAINERS b/board/logicpd/omap3som/MAINTAINERS new file mode 100644 index 0000000000..ffe2201b28 --- /dev/null +++ b/board/logicpd/omap3som/MAINTAINERS @@ -0,0 +1,6 @@ +OMAP3SOM BOARD +M: Peter Barada +S: Maintained +F: board/logicpd/omap3som/ +F: include/configs/omap3_logic.h +F: configs/omap3_logic_defconfig diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile index f8393fa045..87b86ad254 100644 --- a/board/logicpd/omap3som/Makefile +++ b/board/logicpd/omap3som/Makefile @@ -5,22 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := omap3logic.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := omap3logic.o diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 075fe949ae..609edf1e5c 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -128,6 +128,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #ifdef CONFIG_SMC911X /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ static const u32 gpmc_lan92xx_config[] = { @@ -230,6 +237,6 @@ void set_muxconf_regs(void) MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); } diff --git a/board/logicpd/zoom1/Kconfig b/board/logicpd/zoom1/Kconfig new file mode 100644 index 0000000000..d76cb663f7 --- /dev/null +++ b/board/logicpd/zoom1/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_ZOOM1 + +config SYS_BOARD + default "zoom1" + +config SYS_VENDOR + default "logicpd" + +config SYS_CONFIG_NAME + default "omap3_zoom1" + +endif diff --git a/board/logicpd/zoom1/MAINTAINERS b/board/logicpd/zoom1/MAINTAINERS new file mode 100644 index 0000000000..338b965deb --- /dev/null +++ b/board/logicpd/zoom1/MAINTAINERS @@ -0,0 +1,6 @@ +ZOOM1 BOARD +M: Nishanth Menon +S: Maintained +F: board/logicpd/zoom1/ +F: include/configs/omap3_zoom1.h +F: configs/omap3_zoom1_defconfig diff --git a/board/logicpd/zoom1/Makefile b/board/logicpd/zoom1/Makefile index 4afca20feb..7da0da031a 100644 --- a/board/logicpd/zoom1/Makefile +++ b/board/logicpd/zoom1/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := zoom1.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := zoom1.o diff --git a/board/logicpd/zoom1/config.mk b/board/logicpd/zoom1/config.mk index f5a19edd8f..c7ebfd9e69 100644 --- a/board/logicpd/zoom1/config.mk +++ b/board/logicpd/zoom1/config.mk @@ -14,4 +14,3 @@ # (mem base + reserved) # For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 9846f24661..d39203a917 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -15,9 +15,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include #include #include #include +#include #include #include #include @@ -26,6 +29,31 @@ DECLARE_GLOBAL_DATA_PTR; +/* gpmc_cfg is initialized by gpmc_init and we use it here */ +extern struct gpmc *gpmc_cfg; + +/* GPMC definitions for Ethenet Controller LAN9211 */ +static const u32 gpmc_lab_enet[] = { + ZOOM1_ENET_GPMC_CONF1, + ZOOM1_ENET_GPMC_CONF2, + ZOOM1_ENET_GPMC_CONF3, + ZOOM1_ENET_GPMC_CONF4, + ZOOM1_ENET_GPMC_CONF5, + ZOOM1_ENET_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +static const struct ns16550_platdata zoom1_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(zoom1_uart) = { + "serial_omap", + &zoom1_serial +}; + /* * Routine: board_init * Description: Early hardware init. @@ -33,6 +61,9 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* CS1 is Ethernet LAN9211 */ + enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1], + DEBUG_BASE, GPMC_SIZE_16M); /* board id for Linux */ gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP; /* boot param addr */ @@ -78,15 +109,36 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} #endif #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); + +#ifdef CONFIG_SMC911X +#define STR_ENV_ETHADDR "ethaddr" + + struct eth_device *dev; + uchar eth_addr[6]; + + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { + dev = eth_get_dev_by_index(0); + if (dev) { + eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); + } else { + printf("zoom1: Couldn't get eth device\n"); + rc = -1; + } + } #endif + return rc; } #endif diff --git a/board/logicpd/zoom1/zoom1.h b/board/logicpd/zoom1/zoom1.h index 62ef94f376..3a943dfc01 100644 --- a/board/logicpd/zoom1/zoom1.h +++ b/board/logicpd/zoom1/zoom1.h @@ -17,6 +17,13 @@ const omap3_sysinfo sysinfo = { "NAND", }; +#define ZOOM1_ENET_GPMC_CONF1 0x00611000 +#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01 +#define ZOOM1_ENET_GPMC_CONF3 0x00080803 +#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09 +#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F +#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4 + /* * IEN - Input Enable * IDIS - Input Disable @@ -94,13 +101,13 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ diff --git a/board/logicpd/zoom2/Makefile b/board/logicpd/zoom2/Makefile deleted file mode 100644 index b1fbbbd0bb..0000000000 --- a/board/logicpd/zoom2/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-y += debug_board.o -COBJS-y += zoom2_serial.o -COBJS-$(CONFIG_STATUS_LED) += led.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/logicpd/zoom2/config.mk b/board/logicpd/zoom2/config.mk deleted file mode 100644 index 1c382f7189..0000000000 --- a/board/logicpd/zoom2/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2009 -# Texas Instruments, -# -# Zoom II uses OMAP3 (ARM-CortexA8) CPU -# see http://www.ti.com/ for more information on Texas Instruments -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Physical Address: -# 0x80000000 (bank0) -# 0xA0000000 (bank1) -# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/logicpd/zoom2/debug_board.c b/board/logicpd/zoom2/debug_board.c deleted file mode 100644 index 071f41074b..0000000000 --- a/board/logicpd/zoom2/debug_board.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include - -#define DEBUG_BOARD_CONNECTED 1 -#define DEBUG_BOARD_NOT_CONNECTED 0 - -static int debug_board_connected = DEBUG_BOARD_CONNECTED; - -static void zoom2_debug_board_detect (void) -{ - int val = 0; - - if (!gpio_request(158, "")) { - /* - * GPIO to query for debug board - * 158 db board query - */ - gpio_direction_input(158); - val = gpio_get_value(158); - } - - if (!val) - debug_board_connected = DEBUG_BOARD_NOT_CONNECTED; -} - -int zoom2_debug_board_connected (void) -{ - static int first_time = 1; - - if (first_time) { - zoom2_debug_board_detect (); - first_time = 0; - } - return debug_board_connected; -} diff --git a/board/logicpd/zoom2/led.c b/board/logicpd/zoom2/led.c deleted file mode 100644 index 5d37ac15f2..0000000000 --- a/board/logicpd/zoom2/led.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include - -static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; - -/* - * GPIO LEDs - * 173 red - * 154 blue - * 61 blue2 - */ -#define ZOOM2_LED_RED 173 -#define ZOOM2_LED_BLUE 154 -#define ZOOM2_LED_BLUE2 61 - -void red_led_off(void) -{ - /* red */ - if (!gpio_request(ZOOM2_LED_RED, "")) { - gpio_direction_output(ZOOM2_LED_RED, 0); - gpio_set_value(ZOOM2_LED_RED, 0); - } - saved_state[STATUS_LED_RED] = STATUS_LED_OFF; -} - -void blue_led_off(void) -{ - /* blue */ - if (!gpio_request(ZOOM2_LED_BLUE, "")) { - gpio_direction_output(ZOOM2_LED_BLUE, 0); - gpio_set_value(ZOOM2_LED_BLUE, 0); - } - - /* blue 2 */ - if (!gpio_request(ZOOM2_LED_BLUE2, "")) { - gpio_direction_output(ZOOM2_LED_BLUE2, 0); - gpio_set_value(ZOOM2_LED_BLUE2, 0); - } - saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; -} - -void red_led_on(void) -{ - blue_led_off(); - - /* red */ - if (!gpio_request(ZOOM2_LED_RED, "")) { - gpio_direction_output(ZOOM2_LED_RED, 0); - gpio_set_value(ZOOM2_LED_RED, 1); - } - saved_state[STATUS_LED_RED] = STATUS_LED_ON; -} - -void blue_led_on(void) -{ - red_led_off(); - - /* blue */ - if (!gpio_request(ZOOM2_LED_BLUE, "")) { - gpio_direction_output(ZOOM2_LED_BLUE, 0); - gpio_set_value(ZOOM2_LED_BLUE, 1); - } - - /* blue 2 */ - if (!gpio_request(ZOOM2_LED_BLUE2, "")) { - gpio_direction_output(ZOOM2_LED_BLUE2, 0); - gpio_set_value(ZOOM2_LED_BLUE2, 1); - } - - saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; -} - -void __led_init (led_id_t mask, int state) -{ - __led_set (mask, state); -} - -void __led_toggle (led_id_t mask) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE]) - blue_led_off(); - else - blue_led_on(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) - red_led_off(); - else - red_led_on(); - } -} - -void __led_set (led_id_t mask, int state) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == state) - blue_led_on(); - else - blue_led_off(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == state) - red_led_on(); - else - red_led_off(); - } -} diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c deleted file mode 100644 index e14de04695..0000000000 --- a/board/logicpd/zoom2/zoom2.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * Derived from Zoom1 code by - * Nishanth Menon - * Sunil Kumar - * Shashi Ranjan - * Richard Woodruff - * Syed Mohammed Khasim - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include "zoom2.h" -#include "zoom2_serial.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * This the the zoom2, board specific, gpmc configuration for the - * quad uart on the debug board. The more general gpmc configurations - * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c - * - * The details of the setting of the serial gpmc setup are not available. - * The values were provided by another party. - */ -static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { - 0x00011000, - 0x001F1F01, - 0x00080803, - 0x1D091D09, - 0x041D1F1F, - 0x1D0904C4, 0 -}; - -/* Used to track the revision of the board */ -static zoom2_revision revision = ZOOM2_REVISION_UNKNOWN; - -/* - * Routine: zoom2_get_revision - * Description: Return the revision of the Zoom2 this code is running on. - */ -zoom2_revision zoom2_get_revision(void) -{ - return revision; -} - -/* - * Routine: zoom2_identify - * Description: Detect which version of Zoom2 we are running on. - */ -void zoom2_identify(void) -{ - /* - * To check for production board vs beta board, - * check if gpio 94 is clear. - * - * No way yet to check for alpha board identity. - * Alpha boards were produced in very limited quantities - * and they are not commonly used. They are mentioned here - * only for completeness. - */ - if (!gpio_request(94, "")) { - unsigned int val; - - gpio_direction_input(94); - val = gpio_get_value(94); - - if (val) - revision = ZOOM2_REVISION_BETA; - else - revision = ZOOM2_REVISION_PRODUCTION; - } - - printf("Board revision "); - switch (revision) { - case ZOOM2_REVISION_PRODUCTION: - printf("Production\n"); - break; - case ZOOM2_REVISION_BETA: - printf("Beta\n"); - break; - default: - printf("Unknown\n"); - break; - } -} - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init (void) -{ - u32 *gpmc_config; - - gpmc_init (); /* in SRAM or SDRAM, finish GPMC */ - - /* Configure console support on zoom2 */ - gpmc_config = gpmc_serial_TL16CP754C; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3], - SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M); - - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - -#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set (STATUS_LED_BOOT, STATUS_LED_ON); -#endif - return 0; -} - -/* - * Routine: misc_init_r - * Description: Configure zoom board specific configurations - */ -int misc_init_r(void) -{ - zoom2_identify(); - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - dieid_num_r(); - - /* - * Board Reset - * The board is reset by holding the the large button - * on the top right side of the main board for - * eight seconds. - * - * There are reported problems of some beta boards - * continously resetting. For those boards, disable resetting. - */ - if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision()) - twl4030_power_reset_init(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs (void) -{ - /* platform specific muxes */ - MUX_ZOOM2 (); -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/logicpd/zoom2/zoom2.h b/board/logicpd/zoom2/zoom2.h deleted file mode 100644 index 850c790a08..0000000000 --- a/board/logicpd/zoom2/zoom2.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * Derived from: board/omap3/zoom1/zoom1.h - * Nishanth Menon - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _BOARD_ZOOM2_H_ -#define _BOARD_ZOOM2_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Zoom2 ", - "NAND", -}; - -typedef enum { - ZOOM2_REVISION_UNKNOWN = 0, - ZOOM2_REVISION_ALPHA, - ZOOM2_REVISION_BETA, - ZOOM2_REVISION_PRODUCTION -} zoom2_revision; - -zoom2_revision zoom2_get_revision(void); - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_ZOOM2() \ - /* SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ -/* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /* GPMC_nCS1 */\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /* GPMC_nCS2 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /* GPMC_nCS3 */\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /* GPMC_nCS4 */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /* GPMC_nCS6 */\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /* GPMC_nCS7 */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /* GPMC_nWP */\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /* GPMC_WAIT0 */\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /* GPMC_WAIT1 */\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /* GPMC_WAIT2 */\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /* GPMC_WAIT3 */\ -/* IDCC modem Power On */\ - MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /* GPIO_110 */\ - MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /* GPIO_103 */\ -/* GPMC CS7 has LAN9211 device */\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /* LAN9221 */\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M0)) /* MCSPI1_CS2 */\ -/* GPMC CS3 has Serial TL16CP754C device */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPMC_nCS3 */\ -/* Toggle Reset pin of TL16CP754C device */\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTU | EN | M4)) /* GPIO_152 */\ - udelay(10);\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M4)) /* GPIO_152 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */\ -/* LEDS */\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M4)) /* GPIO_173 red */\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | EN | M4)) /* GPIO_154 blue */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | EN | M4)) /* GPIO_61 blue2 */ - -#endif /* _BOARD_ZOOM2_H_ */ diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c deleted file mode 100644 index 2959276116..0000000000 --- a/board/logicpd/zoom2/zoom2_serial.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - * - * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c - */ - -#include -#include -#include -#include -#include "zoom2_serial.h" - -int quad_init_dev (unsigned long base) -{ - /* - * The Quad UART is on the debug board. - * Check if the debug board is attached before using the UART - */ - if (zoom2_debug_board_connected ()) { - NS16550_t com_port = (NS16550_t) base; - int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 / - CONFIG_BAUDRATE; - - /* - * Zoom2 has a board specific initialization of its UART. - * This generic initialization has been copied from - * drivers/serial/ns16550.c. The macros have been expanded. - * - * Do the following instead of - * - * NS16550_init (com_port, clock_divisor); - */ - com_port->ier = 0x00; - - /* - * On Zoom2 board Set pre-scalar to 1 - * CLKSEL is GND => MCR[7] is 1 => preslr is 4 - * So change the prescl to 1 - */ - com_port->lcr = 0xBF; - com_port->fcr |= 0x10; - com_port->mcr &= 0x7F; - - /* This is generic ns16550.c setup */ - com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCR_8N1; - com_port->mcr = UART_MCR_DTR | UART_MCR_RTS; - com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | - UART_FCR_TXSR; - com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCR_8N1; - } - /* - * We have to lie here, otherwise the board init code will hang - * on the check - */ - return 0; -} - -void quad_putc_dev (unsigned long base, const char c) -{ - if (zoom2_debug_board_connected ()) { - - if (c == '\n') - quad_putc_dev (base, '\r'); - - NS16550_putc ((NS16550_t) base, c); - } else { - usbtty_putc(c); - } -} - -void quad_puts_dev (unsigned long base, const char *s) -{ - if (zoom2_debug_board_connected ()) { - while ((s != NULL) && (*s != '\0')) - quad_putc_dev (base, *s++); - } else { - usbtty_puts(s); - } -} - -int quad_getc_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) - return NS16550_getc ((NS16550_t) base); - - return usbtty_getc(); -} - -int quad_tstc_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) - return NS16550_tstc ((NS16550_t) base); - - return usbtty_tstc(); -} - -void quad_setbrg_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) { - - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / - CONFIG_BAUDRATE; - - NS16550_reinit ((NS16550_t) base, clock_divisor); - } -} - -QUAD_INIT (0) -QUAD_INIT (1) -QUAD_INIT (2) -QUAD_INIT (3) - -struct serial_device *default_serial_console(void) -{ - switch (ZOOM2_DEFAULT_SERIAL_DEVICE) { - case 0: return &zoom2_serial_device0; - case 1: return &zoom2_serial_device1; - case 2: return &zoom2_serial_device2; - case 3: return &zoom2_serial_device3; - } -} diff --git a/board/logicpd/zoom2/zoom2_serial.h b/board/logicpd/zoom2/zoom2_serial.h deleted file mode 100644 index 82244521ac..0000000000 --- a/board/logicpd/zoom2/zoom2_serial.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ZOOM2_SERIAL_H -#define ZOOM2_SERIAL_H - -#include - -extern int zoom2_debug_board_connected (void); - -#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */ - -#define QUAD_BASE_0 SERIAL_TL16CP754C_BASE -#define QUAD_BASE_1 (SERIAL_TL16CP754C_BASE + 0x100) -#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200) -#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300) - -#define QUAD_INIT(n) \ -int quad_init_##n(void) \ -{ \ - return quad_init_dev(QUAD_BASE_##n); \ -} \ -void quad_setbrg_##n(void) \ -{ \ - quad_setbrg_dev(QUAD_BASE_##n); \ -} \ -void quad_putc_##n(const char c) \ -{ \ - quad_putc_dev(QUAD_BASE_##n, c); \ -} \ -void quad_puts_##n(const char *s) \ -{ \ - quad_puts_dev(QUAD_BASE_##n, s); \ -} \ -int quad_getc_##n(void) \ -{ \ - return quad_getc_dev(QUAD_BASE_##n); \ -} \ -int quad_tstc_##n(void) \ -{ \ - return quad_tstc_dev(QUAD_BASE_##n); \ -} \ -struct serial_device zoom2_serial_device##n = \ -{ \ - .name = __stringify(n), \ - .start = quad_init_##n, \ - .stop = NULL, \ - .setbrg = quad_setbrg_##n, \ - .getc = quad_getc_##n, \ - .tstc = quad_tstc_##n, \ - .putc = quad_putc_##n, \ - .puts = quad_puts_##n, \ -}; - -#endif /* ZOOM2_SERIAL_H */ diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile deleted file mode 100644 index 7b7f51a7bb..0000000000 --- a/board/lubbock/Makefile +++ /dev/null @@ -1,28 +0,0 @@ - -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := lubbock.o flash.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c deleted file mode 100644 index f6bb22c2e4..0000000000 --- a/board/lubbock/flash.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c deleted file mode 100644 index 0daff9abf1..0000000000 --- a/board/lubbock/lubbock.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Configure GPIO6 and GPIO8 as OUT, AF1. */ - setbits_le32(GPDR0, (1 << 6) | (1 << 8)); - clrsetbits_le32(GAFR0_L, (3 << 12) | (3 << 16), (1 << 12) | (1 << 16)); - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile deleted file mode 100644 index e1ac275ccd..0000000000 --- a/board/lwmon/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/lwmon/README.keybd b/board/lwmon/README.keybd deleted file mode 100644 index 5e5144e569..0000000000 --- a/board/lwmon/README.keybd +++ /dev/null @@ -1,126 +0,0 @@ - -Tastaturabfrage: - -Die Implementierung / Decodierung beruht auf den Angaben aus dem Do- -kument "PIC LWE-Tastatur" in der Fassung vom 9. 3. 2001, insbesonde- -re Tabelle 3 im Kapitel 4.3 Tastencodes. In U-Boot werden die vom -Keyboard-Controller gelesenen Daten hexadezimal codiert in der auto- -matisch angelegten Environment-Variablen "keybd" übergeben. Ist kei- -ne Taste gedrückt worden, steht dort: - - keybd=000000000000000000 - -Der decodierte Tastencode ("keybd") kann mit den "bootargs" an den -Linux-Kernel übergeben und dort z. B. in einem Device-Treiber oder -einer Applikation ausgewertet werden. - - -Sonderfunktionen beim Booten: - -Es lassen sich eine oder mehrere (beliebig viele) Tasten oder Tasten- -kombinationen definieren, die Sonderfunktionen auslösen, wenn diese -Tasten beim Booten (Reset) gedrückt sind. - -Wird eine eingestellte Taste bzw. Tastenkombination erkannt, so wird -in U-Boot noch vor dem Start des "Countdown" und somit vor jedem an- -deren Kommando der Inhalt einer dieser Taste bzw. Tastenkombination -zugeordneten Environment-Variablen ausführen. - - -Die Environment-Variable "magic_keys" wird als Liste von Zeichen ver- -standen, die als Suffix an den Namen "key_magic" angefügt werden und -so die Namen der Environment-Variablen definieren, mit denen die -Tasten (-kombinationen) festgelegt werden: - -Ist "magic_keys" NICHT definiert, so wird nur die in der Environment- -Variablen "key_magic" codierte Tasten (-kombination) geprüft, und -ggf. der Inhalt der Environment-Variablen "key_cmd" ausgeführt (ge- -nauer: der Inhalt von "key_cmd" wird der Variablen "preboot" zugewie- -sen, die ausgeführt wird, unmittelbar bevor die interaktive Kommando- -interpretation beginnt). - -Enthält "magic_keys" z. B. die Zeichenkette "0123CB*", so werden -nacheinander folgende Aktionen ausgeführt: - - prüfe Tastencode ggf. führe aus Kommando - in Variable in Variable - ----------------------------------- - key_magic0 ==> key_cmd0 - key_magic1 ==> key_cmd1 - key_magic2 ==> key_cmd2 - key_magic3 ==> key_cmd3 - key_magicC ==> key_cmdC - key_magicB ==> key_cmdB - key_magicA ==> key_cmdA - key_magic* ==> key_cmd* - -Hinweis: sobald ein aktivierter Tastencode erkannt wurde, wird die -Bearbeitung abgebrochen; es wird daher höchstens eines der definier- -ten Kommandos ausgeführt, wobei die Priorität durch die Suchreihen- -folge festgelegt wird, also durch die Reihenfolge der Zeichen in der -Varuiablen "magic_keys". - - -Die Codierung der Tasten, die beim Booten gedrückt werden müssen, um -eine Funktion auszulösen, erfolgt nach der Tastaturtabelle. - -Die Definitionen - - => setenv key_magic0 3a+3b - => setenv key_cmd0 setenv bootdelay 30 - -bedeuten dementsprechend, daß die Tasten mit den Codes 0x3A (Taste -"F1") und 0x3B (Taste "F2") gleichzeitig gedrückt werden müssen. Sie -können dort eine beliebige Tastenkombination eintragen (jeweils 2 -Zeichen für die Hex-Codes der Tasten, und '+' als Trennzeichen). - -Wird die eingestellte Tastenkombination erkannt, so wird in U-Boot -noch vor dem Start des "Countdown" und somit vor jedem anderen Kom- -mando das angebene Kommando ausgeführt und somit ein langes Boot- -Delay eingetragen. - -Praktisch könnten Sie also in U-Boot "bootdelay" auf 0 setzen und -somit stets ohne jede User-Interaktion automatisch booten, außer, -wenn die beiden Tasten "F1" und "F2" beim Booten gedrückt werden: -dann würde ein Boot-Delay von 30 Sekunden eingefügt. - - -Hinweis: dem Zeichen '#' kommt innerhalb von "magic_keys" eine beson- -dere Bedeutung zu: die dadurch definierte Key-Sequenz schaltet den -Monitor in den "Debug-Modus" - das bedeutet zunächst, daß alle weite- -ren Meldungen von U-Boot über das LCD-Display ausgegeben werden; -außerdem kann man durch das mit dieser Tastenkombination verknüpfte -Kommando z. B. die Linux-Bootmeldungen ebenfalls auf das LCD-Display -legen, so daß der Boot-Vorgang direkt und ohne weitere Hilfsmittel -analysiert werden kann. - -Beispiel: - -In U-Boot werden folgende Environment-Variablen gesetzt und abgespei- -chert: - -(1) => setenv magic_keys 01234#X -(2) => setenv key_cmd# setenv addfb setenv bootargs \\${bootargs} console=tty0 console=ttyS1,\\${baudrate} -(3) => setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\${serverip}:\${rootpath} -(4) => setenv addip setenv bootargs \${bootargs} ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off panic=1 -(5) => setenv addfb setenv bootargs \${bootargs} console=ttyS1,\${baudrate} -(6) => setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm - -Hierbei wird die Linux Commandline (in der Variablen "bootargs") im -Boot-Kommando "bootcmd" (6) schrittweise zusammengesetzt: zunächst -werden die für Root-Filesystem über NFS erforderlichen Optionen ge- -setzt ("run nfsargs", vgl. (3)), dann die Netzwerkkonfiguration an- -gefügt ("run addip", vgl. (4)), und schließlich die Systemconsole -definiert ("run addfb"). - -Dabei wird im Normalfall die Definition (5) verwendt; wurde aller- -dings beim Reset die entsprechende Taste gedrückt gehalten, so wird -diese Definition bei der Ausführung des in (2) definierten Kommandos -überschrieben, so daß Linux die Bootmeldungen auch über das Frame- -buffer-Device (=LCD-Display) ausgibt. - -Beachten Sie die Verdoppelung der '\'-Escapes in der Definition von -"key_cmd#" - diese ist erforderlich, weil der String _zweimal_ inter- -pretiert wird: das erste Mal bei der Eingabe von "key_cmd#", das -zweite Mal, wenn der String (als Inhalt von "preboot") ausgeführt -wird. diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c deleted file mode 100644 index cb60c418a1..0000000000 --- a/board/lwmon/flash.c +++ /dev/null @@ -1,632 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* #define DEBUG */ - -#include -#include - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, ulong data); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - debug ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH | - OR_CSNT_SAM | OR_ACS_DIV1; - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH | - OR_CSNT_SAM | OR_ACS_DIV1; - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_PS_32 | BR_V; - - debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_info[1].size = size_b1; - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - memctl->memc_or1 = 0; /* invalidate bank */ - - debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000 * 2; /* 128k * 2 chips per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", - info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - ulong value; - - /* Read Manufacturer ID */ - addr[0] = 0x00900090; - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * 2; - break; /* => 8 MB */ - - case INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000 * 2; - break; /* => 16 MB */ - - case INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000 * 2; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = 0x00FF00FF; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x00600060; /* clear lock bit setup */ - *addr = 0x00D000D0; /* clear lock bit confirm */ - - udelay (1000); - /* This takes awfully long - up to 50 ms and more */ - while (((status = *addr) & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0x00FF00FF; /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - udelay (1000); /* to trigger the watchdog */ - } - - *addr = 0x00500050; /* clear status register */ - *addr = 0x00200020; /* erase setup */ - *addr = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0x00B000B0; /* suspend erase */ - *addr = 0x00FF00FF; /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - udelay (1000); /* to trigger the watchdog */ - } - - *addr = 0x00FF00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 4 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= FLASH_WIDTH) { - i = CONFIG_SYS_FLASH_BUFFER_SIZE > cnt ? - (cnt & ~(FLASH_WIDTH - 1)) : CONFIG_SYS_FLASH_BUFFER_SIZE; - if((rc = write_data_buf(info, wp, src,i)) != 0) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - while (cnt >= FLASH_WIDTH) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i tout) { - printf("Flash %s timeout at address %p\n", prompt, addr); - *addr = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - if (flash_status_check(addr, CONFIG_SYS_FLASH_WRITE_TOUT, "write") != 0) { - return (1); - } - - *addr = 0x00FF00FF; /* restore read mode */ - - return (0); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -/*----------------------------------------------------------------------- - * Write a buffer to Flash, returns: - * 0 - OK - * 1 - write timeout - */ -static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - vu_long *addr = (vu_long *)dest; - int sector; - int cnt; - int retcode; - vu_long * src = (vu_long *)cp; - vu_long * dst = (vu_long *)dest; - - /* find sector */ - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(dest >= info->start[sector]) - break; - } - - *addr = 0x00500050; /* clear status */ - *addr = 0x00e800e8; /* write buffer */ - - if((retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT, - "write to buffer")) == 0) { - cnt = len / FLASH_WIDTH; - *addr = (cnt-1) | ((cnt-1) << 16); - while(cnt-- > 0) { - *dst++ = *src++; - } - *addr = 0x00d000d0; /* write buffer confirm */ - retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT, - "buffer write"); - } - *addr = 0x00FF00FF; /* restore read mode */ - *addr = 0x00500050; /* clear status */ - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ - -/*----------------------------------------------------------------------- - */ diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c deleted file mode 100644 index 225b1ef258..0000000000 --- a/board/lwmon/lwmon.c +++ /dev/null @@ -1,1071 +0,0 @@ -/*********************************************************************** - * -M* Modul: lwmon.c -M* -M* Content: LWMON specific U-Boot commands. - * - * (C) Copyright 2001, 2002 - * DENX Software Engineering - * Wolfgang Denk, wd@denx.de - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - ***********************************************************************/ - -/*---------------------------- Headerfiles ----------------------------*/ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include /* for strdup */ - -DECLARE_GLOBAL_DATA_PTR; - -/*------------------------ Local prototypes ---------------------------*/ -static long int dram_size (long int, long int *, long int); -static void kbd_init (void); -static int compare_magic (uchar *kbd_data, uchar *str); - - -/*--------------------- Local macros and constants --------------------*/ -#define _NOT_USED_ 0xFFFFFFFF - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void); -extern void disable_putc(void); -#endif /* CONFIG_MODEM_SUPPORT */ - -/* - * 66 MHz SDRAM access using UPM A - */ -const uint sdram_table[] = -{ -#if defined(CONFIG_SYS_MEMORY_75) || defined(CONFIG_SYS_MEMORY_8E) - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, -#endif -#ifdef CONFIG_SYS_MEMORY_7E - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00, - 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, -#endif -}; - -/* - * Check Board Identity: - * - */ - -/*********************************************************************** -F* Function: int checkboard (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int - 0 is always returned - * -Z* Intention: This function is the checkboard() method implementation -Z* for the lwmon board. Only a standard message is printed. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int checkboard (void) -{ - puts ("Board: LICCON Konsole LCD3\n"); - return (0); -} - -/*********************************************************************** -F* Function: phys_size_t initdram (int board_type) P*A*Z* - * -P* Parameters: int board_type -P* - Usually type of the board - ignored here. -P* -P* Returnvalue: long int -P* - Size of initialized memory - * -Z* Intention: This function is the initdram() method implementation -Z* for the lwmon board. -Z* The memory controller is initialized to access the -Z* DRAM. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - long int size_b0; - long int size8, size9; - int i; - - /* - * Configure UPMA for SDRAM - */ - upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = CONFIG_SYS_MAR; - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - /* initialize memory address register */ - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ - udelay (200); /* 0x80006105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05); - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); - - udelay (1); /* 0x80006106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06); - - memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */ - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE3_PRELIM; - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL | MAMR_PTAE; - udelay (500); - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE; - udelay (500); - } - - /* - * Final mapping: - */ - - memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | - OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - udelay (1000); - - return (size_b0); -} - -/*********************************************************************** -F* Function: static long int dram_size (long int mamr_value, -F* long int *base, -F* long int maxsize) P*A*Z* - * -P* Parameters: long int mamr_value -P* - Value for MAMR for the test -P* long int *base -P* - Base address for the test -P* long int maxsize -P* - Maximum size to test for -P* -P* Returnvalue: long int -P* - Size of probed memory - * -Z* Intention: Check memory range for valid RAM. A simple memory test -Z* determines the actually available RAM size between -Z* addresses `base' and `base + maxsize'. Some (not all) -Z* hardware errors are detected: -Z* - short between address lines -Z* - short between data lines - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#ifndef PB_ENET_TENA -# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#endif - -/*********************************************************************** -F* Function: int board_early_init_f (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: This function is the board_early_init_f() method implementation -Z* for the lwmon board. -Z* Disable Ethernet TENA on Port B. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int board_early_init_f (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* Disable Ethernet TENA on Port B - * Necessary because of pull up in COM3 port. - * - * This is just a preliminary fix, intended to turn off TENA - * as soon as possible to avoid noise on the network. Once - * I2C is running we will make sure the interface is - * correctly initialized. - */ - immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA; - immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA; - immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA; /* set to 0 = disabled */ - immr->im_cpm.cp_pbdir |= PB_ENET_TENA; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/*********************************************************************** -F* Function: void reset_phy (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: none - * -Z* Intention: Reset the PHY. In the lwmon case we do this by the -Z* signaling the PIC I/O expander. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -void reset_phy (void) -{ - uchar c; - -#ifdef DEBUG - printf ("### Switch on Ethernet for SCC2 ###\n"); -#endif - c = pic_read (0x61); -#ifdef DEBUG - printf ("Old PIC read: reg_61 = 0x%02x\n", c); -#endif - c |= 0x40; /* disable COM3 */ - c &= ~0x80; /* enable Ethernet */ - pic_write (0x61, c); -#ifdef DEBUG - c = pic_read (0x61); - printf ("New PIC read: reg_61 = 0x%02x\n", c); -#endif - udelay (1000); -} - - -/*------------------------- Keyboard controller -----------------------*/ -/* command codes */ -#define KEYBD_CMD_READ_KEYS 0x01 -#define KEYBD_CMD_READ_VERSION 0x02 -#define KEYBD_CMD_READ_STATUS 0x03 -#define KEYBD_CMD_RESET_ERRORS 0x10 - -/* status codes */ -#define KEYBD_STATUS_MASK 0x3F -#define KEYBD_STATUS_H_RESET 0x20 -#define KEYBD_STATUS_BROWNOUT 0x10 -#define KEYBD_STATUS_WD_RESET 0x08 -#define KEYBD_STATUS_OVERLOAD 0x04 -#define KEYBD_STATUS_ILLEGAL_WR 0x02 -#define KEYBD_STATUS_ILLEGAL_RD 0x01 - -/* Number of bytes returned from Keyboard Controller */ -#define KEYBD_VERSIONLEN 2 /* version information */ -#define KEYBD_DATALEN 9 /* normal key scan data */ - -/* maximum number of "magic" key codes that can be assigned */ - -static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; - -static uchar *key_match (uchar *); - -#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ - -/*********************************************************************** -F* Function: int board_postclk_init (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: This function is the board_postclk_init() method implementation -Z* for the lwmon board. - * - ***********************************************************************/ -int board_postclk_init (void) -{ - kbd_init(); - -#ifdef CONFIG_MODEM_SUPPORT - if (key_pressed()) { - disable_putc(); /* modem doesn't understand banner etc */ - gd->do_mdm_init = 1; - } -#endif - - return (0); -} - -struct serial_device * default_serial_console (void) -{ - return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device; -} - -static void kbd_init (void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar tmp_data[KEYBD_DATALEN]; - uchar val, errcd; - int i; - - i2c_set_bus_num(0); - - gd->arch.kbd_status = 0; - - /* Forced by PIC. Delays <= 175us loose */ - udelay(1000); - - /* Read initial keyboard error code */ - val = KEYBD_CMD_READ_STATUS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, &errcd, 1); - /* clear unused bits */ - errcd &= KEYBD_STATUS_MASK; - /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ - errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); - if (errcd) { - gd->arch.kbd_status |= errcd << 8; - } - /* Reset error code and verify */ - val = KEYBD_CMD_RESET_ERRORS; - i2c_write (kbd_addr, 0, 0, &val, 1); - udelay(1000); /* delay NEEDED by keyboard PIC !!! */ - - val = KEYBD_CMD_READ_STATUS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, &val, 1); - - val &= KEYBD_STATUS_MASK; /* clear unused bits */ - if (val) { /* permanent error, report it */ - gd->arch.kbd_status |= val; - return; - } - - /* - * Read current keyboard state. - * - * After the error reset it may take some time before the - * keyboard PIC picks up a valid keyboard scan - the total - * scan time is approx. 1.6 ms (information by Martin Rajek, - * 28 Sep 2002). We read a couple of times for the keyboard - * to stabilize, using a big enough delay. - * 10 times should be enough. If the data is still changing, - * we use what we get :-( - */ - - memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ - for (i=0; i<10; ++i) { - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { - /* consistent state, done */ - break; - } - /* remeber last state, delay, and retry */ - memcpy (tmp_data, kbd_data, KEYBD_DATALEN); - udelay (5000); - } -} - -/*********************************************************************** -F* Function: int misc_init_r (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned, even in the case of a keyboard -P* error. - * -Z* Intention: This function is the misc_init_r() method implementation -Z* for the lwmon board. -Z* The keyboard controller is initialized and the result -Z* of a read copied to the environment variable "keybd". -Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for -Z* this key, and if found display to the LCD will be enabled. -Z* The keys in "keybd" are checked against the magic -Z* keycommands defined in the environment. -Z* See also key_match(). - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int misc_init_r (void) -{ - uchar kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - uchar kbd_init_status = gd->arch.kbd_status >> 8; - uchar kbd_status = gd->arch.kbd_status; - uchar val; - char *str; - int i; - - if (kbd_init_status) { - printf ("KEYBD: Error %02X\n", kbd_init_status); - } - if (kbd_status) { /* permanent error, report it */ - printf ("*** Keyboard error code %02X ***\n", kbd_status); - sprintf (keybd_env, "%02X", kbd_status); - setenv ("keybd", keybd_env); - return 0; - } - - /* - * Now we know that we have a working keyboard, so disable - * all output to the LCD except when a key press is detected. - */ - - if ((console_assign (stdout, "serial") < 0) || - (console_assign (stderr, "serial") < 0)) { - printf ("Can't assign serial port as output device\n"); - } - - /* Read Version */ - val = KEYBD_CMD_READ_VERSION; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); - printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); - - /* Read current keyboard state */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - } - setenv ("keybd", keybd_env); - - str = strdup ((char *)key_match (kbd_data)); /* decode keys */ -#ifdef KEYBD_SET_DEBUGMODE - if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ - if ((console_assign (stdout, "lcd") < 0) || - (console_assign (stderr, "lcd") < 0)) { - printf ("Can't assign LCD display as output device\n"); - } - } -#endif /* KEYBD_SET_DEBUGMODE */ -#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ - setenv ("preboot", str); /* set or delete definition */ -#endif /* CONFIG_PREBOOT */ - if (str != NULL) { - free (str); - } - return (0); -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -static int compare_magic (uchar *kbd_data, uchar *str) -{ - uchar compare[KEYBD_DATALEN-1]; - char *nxt; - int i; - - /* Don't include modifier byte */ - memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); - - for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { - uchar c; - int k; - - c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); - - if (str == (uchar *)nxt) { /* invalid character */ - break; - } - - /* - * Check if this key matches the input. - * Set matches to zero, so they match only once - * and we can find duplicates or extra keys - */ - for (k = 0; k < sizeof(compare); ++k) { - if (compare[k] == '\0') /* only non-zero entries */ - continue; - if (c == compare[k]) { /* found matching key */ - compare[k] = '\0'; - break; - } - } - if (k == sizeof(compare)) { - return -1; /* unmatched key */ - } - } - - /* - * A full match leaves no keys in the `compare' array, - */ - for (i = 0; i < sizeof(compare); ++i) { - if (compare[i]) - { - return -1; - } - } - - return 0; -} - -/*********************************************************************** -F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* - * -P* Parameters: uchar *kbd_data -P* - The keys to match against our magic definitions -P* -P* Returnvalue: uchar * -P* - != NULL: Pointer to the corresponding command(s) -P* NULL: No magic is about to happen - * -Z* Intention: Check if pressed key(s) match magic sequence, -Z* and return the command string associated with that key(s). -Z* -Z* If no key press was decoded, NULL is returned. -Z* -Z* Note: the first character of the argument will be -Z* overwritten with the "magic charcter code" of the -Z* decoded key(s), or '\0'. -Z* -Z* Note: the string points to static environment data -Z* and must be saved before you call any function that -Z* modifies the environment. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -static uchar *key_match (uchar *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - uchar *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can pe appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); -#if 0 - printf ("### Check magic \"%s\"\n", magic); -#endif - if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - - cmd = getenv (cmd_name); -#if 0 - printf ("### Set PREBOOT to $(%s): \"%s\"\n", - cmd_name, cmd ? cmd : "<>"); -#endif - *kbd_data = *suffix; - return ((uchar *)cmd); - } - } -#if 0 - printf ("### Delete PREBOOT\n"); -#endif - *kbd_data = '\0'; - return (NULL); -} -#endif /* CONFIG_PREBOOT */ - -#ifdef CONFIG_LCD_INFO -#include -#include -#include - -void lcd_show_board_info(void) -{ - char temp[32]; - - lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); - lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); - lcd_printf (" Wolfgang DENK, wd@denx.de\n"); -#ifdef CONFIG_LCD_INFO_BELOW_LOGO - lcd_printf ("MPC823 CPU at %s MHz\n", - strmhz(temp, gd->cpu_clk)); - lcd_printf (" %ld MB RAM, %ld MB Flash\n", - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); -#else - /* leave one blank line */ - lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n", - strmhz(temp, gd->cpu_clk), - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); -#endif /* CONFIG_LCD_INFO_BELOW_LOGO */ -} -#endif /* CONFIG_LCD_INFO */ - -/*---------------Board Special Commands: PIC read/write ---------------*/ - -#if defined(CONFIG_CMD_BSP) -/*********************************************************************** -F* Function: int do_pic (cmd_tbl_t *cmdtp, int flag, -F* int argc, char * const argv[]) P*A*Z* - * -P* Parameters: cmd_tbl_t *cmdtp -P* - Pointer to our command table entry -P* int flag -P* - If the CMD_FLAG_REPEAT bit is set, then this call is -P* a repetition -P* int argc -P* - Argument count -P* char * const argv[] -P* - Array of the actual arguments -P* -P* Returnvalue: int -P* - 0 The command was handled successfully -P* 1 An error occurred - * -Z* Intention: Implement the "pic [read|write]" commands. -Z* The read subcommand takes one argument, the register, -Z* whereas the write command takes two, the register and -Z* the new value. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uchar reg, val; - - switch (argc) { - case 3: /* PIC read reg */ - if (strcmp (argv[1], "read") != 0) - break; - - reg = simple_strtoul (argv[2], NULL, 16); - - printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg)); - - return 0; - case 4: /* PIC write reg val */ - if (strcmp (argv[1], "write") != 0) - break; - - reg = simple_strtoul (argv[2], NULL, 16); - val = simple_strtoul (argv[3], NULL, 16); - - printf ("PIC write: reg %02x val 0x%02x: %02x => ", - reg, val, pic_read (reg)); - pic_write (reg, val); - printf ("%02x\n\n", pic_read (reg)); - return 0; - default: - break; - } - return cmd_usage(cmdtp); -} -U_BOOT_CMD( - pic, 4, 1, do_pic, - "read and write PIC registers", - "read reg - read PIC register `reg'\n" - "pic write reg val - write value `val' to PIC register `reg'" -); - -/*********************************************************************** -F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, -F* int argc, char * const argv[]) P*A*Z* - * -P* Parameters: cmd_tbl_t *cmdtp -P* - Pointer to our command table entry -P* int flag -P* - If the CMD_FLAG_REPEAT bit is set, then this call is -P* a repetition -P* int argc -P* - Argument count -P* char * const argv[] -P* - Array of the actual arguments -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: Implement the "kbd" command. -Z* The keyboard status is read. The result is printed on -Z* the console and written into the "keybd" environment -Z* variable. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uchar kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - uchar val; - int i; - -#if 0 /* Done in kbd_init */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - puts ("Keys:"); - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - printf (" %02x", kbd_data[i]); - } - putc ('\n'); - setenv ("keybd", keybd_env); - return 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "read keyboard status", - "" -); - -/* Read and set LSB switch */ -#define CONFIG_SYS_PC_TXD1_ENA 0x0008 /* PC.12 */ - -/*********************************************************************** -F* Function: int do_lsb (cmd_tbl_t *cmdtp, int flag, -F* int argc, char * const argv[]) P*A*Z* - * -P* Parameters: cmd_tbl_t *cmdtp -P* - Pointer to our command table entry -P* int flag -P* - If the CMD_FLAG_REPEAT bit is set, then this call is -P* a repetition -P* int argc -P* - Argument count -P* char * const argv[] -P* - Array of the actual arguments -P* -P* Returnvalue: int -P* - 0 The command was handled successfully -P* 1 An error occurred - * -Z* Intention: Implement the "lsb [on|off]" commands. -Z* The lsb is switched according to the first parameter by -Z* by signaling the PIC I/O expander. -Z* Called with no arguments, the current setting is -Z* printed. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uchar val; - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - switch (argc) { - case 1: /* lsb - print setting */ - val = pic_read (0x60); - printf ("LSB is o%s\n", (val & 0x20) ? "n" : "ff"); - return 0; - case 2: /* lsb on or lsb off - set switch */ - val = pic_read (0x60); - - if (strcmp (argv[1], "on") == 0) { - val |= 0x20; - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA); - immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_TXD1_ENA; - immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA; - } else if (strcmp (argv[1], "off") == 0) { - val &= ~0x20; - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA); - immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_TXD1_ENA); - immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA; - } else { - break; - } - pic_write (0x60, val); - return 0; - default: - break; - } - return cmd_usage(cmdtp); -} - -U_BOOT_CMD( - lsb, 2, 1, do_lsb, - "check and set LSB switch", - "on - switch LSB on\n" - "lsb off - switch LSB off\n" - "lsb - print current setting" -); - -#endif - -/*----------------------------- Utilities -----------------------------*/ -/*********************************************************************** -F* Function: uchar pic_read (uchar reg) P*A*Z* - * -P* Parameters: uchar reg -P* - Register to read -P* -P* Returnvalue: uchar -P* - Value read from register - * -Z* Intention: Read a register from the PIC I/O expander. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -uchar pic_read (uchar reg) -{ - return (i2c_reg_read (CONFIG_SYS_I2C_PICIO_ADDR, reg)); -} - -/*********************************************************************** -F* Function: void pic_write (uchar reg, uchar val) P*A*Z* - * -P* Parameters: uchar reg -P* - Register to read -P* uchar val -P* - Value to write -P* -P* Returnvalue: none - * -Z* Intention: Write to a register on the PIC I/O expander. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -void pic_write (uchar reg, uchar val) -{ - i2c_reg_write (CONFIG_SYS_I2C_PICIO_ADDR, reg, val); -} - -/*---------------------- Board Control Functions ----------------------*/ -/*********************************************************************** -F* Function: void board_poweroff (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: none - * -Z* Intention: Turn off the battery power and loop endless, so this -Z* should better be the last function you call... - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -void board_poweroff (void) -{ - /* Turn battery off */ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13)); - - while (1); -} - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar val; - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - return (compare_magic(kbd_data, (uchar *)CONFIG_MODEM_KEY_MAGIC) == 0); -} -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar val; - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); -} -#endif diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c deleted file mode 100644 index b9894cf011..0000000000 --- a/board/lwmon/pcmcia.c +++ /dev/null @@ -1,234 +0,0 @@ -#include -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "LWMON" - -/* #define's for MAX1604 Power Switch */ -#define MAX1604_OP_SUS 0x80 -#define MAX1604_VCCBON 0x40 -#define MAX1604_VCC_35 0x20 -#define MAX1604_VCCBHIZ 0x10 -#define MAX1604_VPPBON 0x08 -#define MAX1604_VPPBPBPGM 0x04 -#define MAX1604_VPPBHIZ 0x02 -/* reserved 0x01 */ - -int pcmcia_hardware_enable(int slot) -{ - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - uchar val; - - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - /* Switch on PCMCIA port in PIC register 0x60 */ - reg = pic_read (0x60); - debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); - reg &= ~0x10; - /* reg |= 0x08; Vpp not needed */ - pic_write (0x60, reg); -#ifdef DEBUG - reg = pic_read (0x60); - printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); -#endif - udelay(10000); - - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { - val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */ - puts (" 5.0V card found: "); - } else { - val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */ - puts (" 3.3V card found: "); - } - - /* switch VCC on */ - val |= MAX1604_OP_SUS | MAX1604_VCCBON; - i2c_set_bus_num(0); - i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); - - udelay(500000); - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - uchar val; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* remove all power, put output in high impedance state */ - val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - /* Switch off PCMCIA port in PIC register 0x60 */ - reg = pic_read (0x60); - debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); - reg |= 0x10; - reg &= ~0x08; - pic_write (0x60, reg); -#ifdef DEBUG - reg = pic_read (0x60); - printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); -#endif - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile pcmconf8xx_t *pcmp; - u_long reg; - uchar val; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Turn off all power (switch to high impedance) - */ - debug ("PCMCIA power OFF\n"); - val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; - i2c_set_bus_num(0); - i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); - - val = 0; - switch(vcc) { - case 0: break; - case 33: val = MAX1604_VCC_35; break; - case 50: break; - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); - if (val) { - debug ("PCMCIA powered at %sV\n", - (val & MAX1604_VCC_35) ? "3.3" : "5.0"); - } else { - debug ("PCMCIA powered down\n"); - } - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds deleted file mode 100644 index 90e2e2ed0c..0000000000 --- a/board/lwmon/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug deleted file mode 100644 index 75a1337170..0000000000 --- a/board/lwmon/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/lwmon5/Kconfig b/board/lwmon5/Kconfig new file mode 100644 index 0000000000..90566d825b --- /dev/null +++ b/board/lwmon5/Kconfig @@ -0,0 +1,9 @@ +if TARGET_LWMON5 + +config SYS_BOARD + default "lwmon5" + +config SYS_CONFIG_NAME + default "lwmon5" + +endif diff --git a/board/lwmon5/MAINTAINERS b/board/lwmon5/MAINTAINERS new file mode 100644 index 0000000000..7402ab6758 --- /dev/null +++ b/board/lwmon5/MAINTAINERS @@ -0,0 +1,7 @@ +LWMON5 BOARD +M: Stefan Roese +S: Maintained +F: board/lwmon5/ +F: include/configs/lwmon5.h +F: configs/lcd4_lwmon5_defconfig +F: configs/lwmon5_defconfig diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile index 05cb635c9f..02478ca0c8 100644 --- a/board/lwmon5/Makefile +++ b/board/lwmon5/Makefile @@ -5,27 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o kbd.o sdram.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = lwmon5.o kbd.o sdram.o +extra-y += init.o diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S index 94274a7248..e5207c2b40 100644 --- a/board/lwmon5/init.S +++ b/board/lwmon5/init.S @@ -4,7 +4,7 @@ * * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 4e4a5944de..e9aa0b77de 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -527,6 +527,9 @@ void spl_board_init(void) */ board_early_init_f(); + /* enable the LSB transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); + /* * Clear resets */ diff --git a/board/manroland/hmi1001/Makefile b/board/manroland/hmi1001/Makefile deleted file mode 100644 index 3acd06bba7..0000000000 --- a/board/manroland/hmi1001/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/manroland/hmi1001/hmi1001.c b/board/manroland/hmi1001/hmi1001.c deleted file mode 100644 index 781f10b861..0000000000 --- a/board/manroland/hmi1001/hmi1001.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * (C) Copyright 2003-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - uint svr, pvr; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - -/* return dramsize + dramsize2; */ - return dramsize; -} - -int checkboard (void) -{ - puts ("Board: HMI1001\n"); - return 0; -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -#define S1_ROT 0xf0 -#define S2_Q 0x40 -#define S2_M 0x20 - -struct kbd_data_t { - char s1; - char s2; -}; - -struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) -{ - kbd_data->s1 = *((volatile uchar*)(CONFIG_SYS_STATUS1_BASE)); - kbd_data->s2 = *((volatile uchar*)(CONFIG_SYS_STATUS2_BASE)); - - return kbd_data; -} - -static int compare_magic (const struct kbd_data_t *kbd_data, char *str) -{ - char s1 = str[0]; - char s2; - - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (((S1_ROT & kbd_data->s1) >> 4) != s1) - return -1; - - s2 = (S2_Q | S2_M) & kbd_data->s2; - - switch (str[1]) { - case 'q': - case 'Q': - if (s2 == S2_Q) - return -1; - break; - case 'm': - case 'M': - if (s2 == S2_M) - return -1; - break; - case '\0': - if (s2 == (S2_Q | S2_M)) - return 0; - default: - return -1; - } - - if (str[2]) - return -1; - - return 0; -} - -static char *key_match (const struct kbd_data_t *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - char *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can be appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; *suffix || - suffix == kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - - if (compare_magic(kbd_data, getenv(magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - cmd = getenv (cmd_name); - - return (cmd); - } - } - - return (NULL); -} - -#endif /* CONFIG_PREBOOT */ - -int misc_init_r (void) -{ -#ifdef CONFIG_PREBOOT - struct kbd_data_t kbd_data; - /* Decode keys */ - char *str = strdup (key_match (get_keys (&kbd_data))); - /* Set or delete definition */ - setenv ("preboot", str); - free (str); -#endif /* CONFIG_PREBOOT */ - - return 0; -} - -int board_early_init_r (void) -{ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE); - *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE); - return 0; -} -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif diff --git a/board/manroland/mucmc52/Makefile b/board/manroland/mucmc52/Makefile deleted file mode 100644 index 0bec8af8d5..0000000000 --- a/board/manroland/mucmc52/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2008 -# Heiko Schocher, DENX Software Engineering, hs@denx.de. -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/manroland/mucmc52/mucmc52.c b/board/manroland/mucmc52/mucmc52.c deleted file mode 100644 index 63dc2ad5fa..0000000000 --- a/board/manroland/mucmc52/mucmc52.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL, - (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); - __asm__ volatile ("sync"); - - /* precharge all banks */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_EMODE)); - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, - (SDRAM_MODE | 0x04000000)); - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - __asm__ volatile ("sync"); - - /* auto refresh */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL, - (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); - __asm__ volatile ("sync"); - - /* set mode register */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_MODE)); - __asm__ volatile ("sync"); - - /* normal operation */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL, - (SDRAM_CONTROL | hi_addr_bit)); - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start (0); - test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start (0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, (dramsize + 0x0000001c));/*512MB*/ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start (0); - test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); - if (!dramsize) { - sdram_start (1); - test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); - } - if (test1 > test2) { - sdram_start (0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, - (dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1))); - } else { - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG) & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04); - __asm__ volatile ("sync"); - } - - return dramsize + dramsize2; -} - -int checkboard (void) -{ - puts ("Board: MUC.MC-52 HW WDT "); -#if defined(CONFIG_HW_WATCHDOG) - puts ("enabled\n"); -#else - puts ("disabled\n"); -#endif - return 0; -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -#define S1_ROT 0xf0 -#define S2_Q 0x40 -#define S2_M 0x20 - -struct kbd_data_t { - char s1; - char s2; -}; - -struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) -{ - kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE); - kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE); - - return kbd_data; -} - -static int compare_magic (const struct kbd_data_t *kbd_data, char *str) -{ - char s1 = str[0]; - char s2; - - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (((S1_ROT & kbd_data->s1) >> 4) != s1) - return -1; - - s2 = (S2_Q | S2_M) & kbd_data->s2; - - switch (str[1]) { - case 'q': - case 'Q': - if (s2 == S2_Q) - return -1; - break; - case 'm': - case 'M': - if (s2 == S2_M) - return -1; - break; - case '\0': - if (s2 == (S2_Q | S2_M)) - return 0; - default: - return -1; - } - - if (str[2]) - return -1; - - return 0; -} - -static char *key_match (const struct kbd_data_t *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - char *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can be appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; *suffix || - suffix == kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - - if (compare_magic(kbd_data, getenv(magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - cmd = getenv (cmd_name); - - return (cmd); - } - } - - return (NULL); -} - -#endif /* CONFIG_PREBOOT */ - -int misc_init_r (void) -{ -#ifdef CONFIG_PREBOOT - struct kbd_data_t kbd_data; - /* Decode keys */ - char *str = strdup (key_match (get_keys (&kbd_data))); - /* Set or delete definition */ - setenv ("preboot", str); - free (str); -#endif /* CONFIG_PREBOOT */ - - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' '); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' '); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' '); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' '); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' '); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' '); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' '); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' '); - - return 0; -} - -int board_early_init_r (void) -{ - out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1); - out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE)); - out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE)); - out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP, - STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)); - out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP, - STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)); - return 0; -} - -int last_stage_init (void) -{ - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M'); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U'); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C'); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.'); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M'); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C'); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5'); - out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2'); - - return 0; -} - -#if defined(CONFIG_HW_WATCHDOG) -#define GPT_OUT_0 0x00000027 -#define GPT_OUT_1 0x00000037 -void hw_watchdog_reset (void) -{ - /* Trigger HW Watchdog with TIMER_0 */ - out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_1); - out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_0); -} -#endif - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init (struct pci_controller *); - -void pci_init_board (void) -{ - pci_mpc5xxx_init (&hose); -} -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/manroland/uc100/Makefile b/board/manroland/uc100/Makefile deleted file mode 100644 index fe15aefa7e..0000000000 --- a/board/manroland/uc100/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -#COBJS = $(BOARD).o flash.o pcmcia.o -COBJS = $(BOARD).o pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/manroland/uc100/pcmcia.c b/board/manroland/uc100/pcmcia.c deleted file mode 100644 index db3821a5e4..0000000000 --- a/board/manroland/uc100/pcmcia.c +++ /dev/null @@ -1,192 +0,0 @@ -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if (defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "UC100" - -/* - * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board. - * This leads to board-hangup! (sr, 8 Dez. 2004) - */ -static void cfg_ports (void) -{ - volatile immap_t *immap; - - immap = (immap_t *)CONFIG_SYS_IMMR; - - /* - * Configure Port A for MAX1602 PC-Card Power-Interface Switch - */ - immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */ - immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */ - - debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n", - immap->im_ioport.iop_papar, immap->im_ioport.iop_padir, - immap->im_ioport.iop_padat); -} - -int pcmcia_hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CONFIG_SYS_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ - cfg_ports (); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - if ((reg & mask) == mask) - puts (" 5.0V card found: "); - else - puts (" 3.3V card found: "); - - /* switch VCC on */ - immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */ - - udelay(10000); - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* switch VCC off */ - immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */ - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_ports (); /* Enables switch, but all in Hi-Z */ - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds deleted file mode 100644 index 47f2de8e64..0000000000 --- a/board/manroland/uc100/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/manroland/uc100/uc100.c b/board/manroland/uc100/uc100.c deleted file mode 100644 index 31f08dda7b..0000000000 --- a/board/manroland/uc100/uc100.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#if 0 -#define DEBUG -#endif - -#include -#include -#include -#include - -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/*********************************************************************/ -/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */ -/*********************************************************************/ -const uint sdram_init_upm_table[] = { - /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */ - /* NOP - Precharge - AutoRefr - NOP - NOP */ - /* NOP - AutoRefr - NOP */ - /* NOP - NOP - LoadModeR - NOP - Active */ - /* Position of Single Read */ - 0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04, - 0x0ffffc04, 0x0ff5fc04, 0x0ffffc04, - - /* Burst Read. (offset 8 in UPMA RAM) */ - /* Cycle lent for Initialisation WV */ - 0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Single Write. (offset 18 in UPMA RAM) */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Burst Write. (offset 20 in UPMA RAM) */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh (offset 30 in UPMA RAM) */ - 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04, - 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception. (offset 3c in UPMA RAM) */ - 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; - -/*********************************************************************/ -/* UPMA initilization table. */ -/*********************************************************************/ -const uint sdram_upm_table[] = { - /* single read. (offset 0 in UPMA RAM) */ - 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */ - - /* Burst Read. (offset 8 in UPMA RAM) */ - 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00, - 0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Single Write. (offset 18 in UPMA RAM) */ - 0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04, - 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Burst Write. (offset 20 in UPMA RAM) */ - 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00, - 0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh (offset 30 in UPMA RAM) */ - 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04, - 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception. (offset 3c in UPMA RAM) */ - 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */ -}; - -/*********************************************************************/ -/* UPMB initilization table. */ -/*********************************************************************/ -const uint mpm_upm_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001, - 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* burst read. (Offset 8 in upm RAM) */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* single write. (Offset 0x18 in upm RAM) */ - 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004, - 0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, - - /* burst write. (Offset 0x20 in upm RAM) */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh cycle, offset 0x30 */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception, 0ffset 0x3C */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; - - -int board_switch(void) -{ - volatile pcmconf8xx_t *pcmp; - - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - return ((pcmp->pcmc_pipr >> 24) & 0xf); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming UC100"); - } else { - puts(str); - } - - printf (" (SWITCH=%1X)\n", board_switch()); - - return 0; -} - - -/* - * Initialize SDRAM - */ -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /*---------------------------------------------------------------------*/ - /* Initialize the UPMA/UPMB registers with the appropriate table. */ - /*---------------------------------------------------------------------*/ - upmconfig (UPMA, (uint *) sdram_init_upm_table, - sizeof (sdram_init_upm_table) / sizeof (uint)); - upmconfig (UPMB, (uint *) mpm_upm_table, - sizeof (mpm_upm_table) / sizeof (uint)); - - /*---------------------------------------------------------------------*/ - /* Memory Periodic Timer Prescaler: divide by 16 */ - /*---------------------------------------------------------------------*/ - memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */ - - memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */ - memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL; - - /*---------------------------------------------------------------------*/ - /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */ - /* for SDRAM */ - /* */ - /* NOTE: The refresh rate in MAMR reg is set according to the lowest */ - /* clock rate (16.67MHz) to allow proper operation for all ADS */ - /* clock frequencies. */ - /*---------------------------------------------------------------------*/ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - /*-------------------------------------------------------------------*/ - /* Wait at least 200 usec for DRAM to stabilize, this magic number */ - /* obtained from the init code. */ - /*-------------------------------------------------------------------*/ - udelay(200); - - memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08; - - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - - /*---------------------------------------------------------------------*/ - /* run MRS command in location 5-8 of UPMB. */ - /*---------------------------------------------------------------------*/ - memctl->memc_mar = 0x88; - /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */ - - memctl->memc_mcr = 0x80002100; - /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */ - - udelay(200); - - /*---------------------------------------------------------------------*/ - /* Initialisation for normal access WV */ - /*---------------------------------------------------------------------*/ - - /*---------------------------------------------------------------------*/ - /* Initialize the UPMA register with the appropriate table. */ - /*---------------------------------------------------------------------*/ - upmconfig (UPMA, (uint *) sdram_upm_table, - sizeof (sdram_upm_table) / sizeof (uint)); - - /*---------------------------------------------------------------------*/ - /* rerstore MBMR value (4-beat refresh burst.) */ - /*---------------------------------------------------------------------*/ - memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */ - - udelay(200); - - return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */ -} - - -int misc_init_r (void) -{ - uchar val; - - /* - * Make sure that RTC has clock output enabled (triggers watchdog!) - */ - val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D); - val |= 0x80; - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val); - - /* - * Configure PHY to setup LED's correctly and use 100MBit, FD - */ - mii_init(); - - /* disable auto-negotiation, 100mbit, full-duplex */ - fec8xx_miiphy_write(NULL, 0, MII_BMCR, 0x2100); - - /* set LED's to Link, Transmit, Receive */ - fec8xx_miiphy_write(NULL, 0, MII_NWAYTEST, 0x4122); - - return 0; -} diff --git a/board/manroland/uc101/Makefile b/board/manroland/uc101/Makefile deleted file mode 100644 index 3acd06bba7..0000000000 --- a/board/manroland/uc101/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/manroland/uc101/uc101.c b/board/manroland/uc101/uc101.c deleted file mode 100644 index 6e1246ecac..0000000000 --- a/board/manroland/uc101/uc101.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * (C) Copyright 2006 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* some SIMPLE GPIO Pins */ -#define GPIO_USB_8 (31-12) -#define GPIO_USB_7 (31-13) -#define GPIO_USB_6 (31-14) -#define GPIO_USB_0 (31-15) -#define GPIO_PSC3_7 (31-18) -#define GPIO_PSC3_6 (31-19) -#define GPIO_PSC3_1 (31-22) -#define GPIO_PSC3_0 (31-23) - -/* some simple Interrupt GPIO Pins */ -#define GPIO_PSC3_8 2 -#define GPIO_USB1_9 3 - -#define GPT_OUT_0 0x00000027 -#define GPT_OUT_1 0x00000037 -#define GPT_DISABLE 0x00000000 /* GPT pin disabled */ - -#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \ - pgpio->simple_ddr |= (1 << n); \ - pgpio->simple_gpioe |= (1 << n); \ - } - -#define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \ - pgpio->simple_gpioe |= (1 << n); \ - } - -#define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \ - (pgpio->simple_dvo | (1 << n)) : \ - (pgpio->simple_dvo & ~(1 << n)) ) - -#define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1) -#define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1) - -#define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \ - (pgpio->sint_dvo | (1 << n)) : \ - (pgpio->sint_dvo & ~(1 << n)) ) - -#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \ - pgpio->sint_ddr |= (1 << n); \ - GP_SINT_SET_O(n, v); \ - pgpio->sint_gpioe |= (1 << n); \ - } - -#define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \ - pgpio->sint_gpioe |= (1 << n); \ - } - -#define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1) -#define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1) - -#define GP_TIMER_ENABLE_O(n, v) ( \ - ((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \ - GPT_OUT_1 : \ - GPT_OUT_0 ) - -#define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v) - -#define GP_TIMER_GET_O(n, v) ( \ - (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4) - -#define GP_TIMER_GET_I(n, v) ( \ - (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8) - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - -/* return dramsize + dramsize2; */ - return dramsize; -} - -int checkboard (void) -{ - puts ("Board: MAN UC101\n"); - /* clear the Display */ - *(char *)(CONFIG_SYS_DISP_CWORD) = 0x80; - return 0; -} - -static void init_ports (void) -{ - volatile struct mpc5xxx_gpio *pgpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */ - GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */ - GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */ - GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */ - GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */ - GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */ - GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */ - GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */ - GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */ - GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */ - GP_TIMER_ENABLE_O(4, 0); /* LED H4 */ - GP_TIMER_ENABLE_O(5, 0); /* LED H5 */ - GP_TIMER_ENABLE_O(3, 0); /* LED HB */ - GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */ -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -struct kbd_data_t { - char s1; -}; - -struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) -{ - volatile struct mpc5xxx_gpio *pgpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \ - GP_SIMP_GET_I(GPIO_USB_7) << 2 | \ - GP_SIMP_GET_I(GPIO_USB_6) << 1 | \ - GP_SIMP_GET_I(GPIO_USB_0) << 0; - return kbd_data; -} - -static int compare_magic (const struct kbd_data_t *kbd_data, char *str) -{ - char s1 = str[0]; - - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (s1 != kbd_data->s1) return -1; - return 0; -} - -static char *key_match (const struct kbd_data_t *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - char *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can be appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; *suffix || - suffix == kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - - if (compare_magic(kbd_data, getenv(magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - cmd = getenv (cmd_name); - - return (cmd); - } - } - - return (NULL); -} - -#endif /* CONFIG_PREBOOT */ - -int misc_init_r (void) -{ - /* Init the I/O ports */ - init_ports (); - -#ifdef CONFIG_PREBOOT - struct kbd_data_t kbd_data; - /* Decode keys */ - char *str = strdup (key_match (get_keys (&kbd_data))); - /* Set or delete definition */ - setenv ("preboot", str); - free (str); -#endif /* CONFIG_PREBOOT */ - return 0; -} - -int board_early_init_r (void) -{ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE); - *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE); - /* Interbus enable it here ?? */ - *(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1; - return 0; -} -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ - /* Trigger HW Watchdog with TIMER_0 */ - *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1; - *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0; -} -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/matrix_vision/common/Makefile b/board/matrix_vision/common/Makefile deleted file mode 100644 index 8593a8633e..0000000000 --- a/board/matrix_vision/common/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) -endif - -LIB = $(obj)lib$(VENDOR).o - -COBJS-y = mv_common.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c deleted file mode 100644 index 70133b5118..0000000000 --- a/board/matrix_vision/common/mv_common.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_ENV_IS_NOWHERE -static char* entries_to_keep[] = { - "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt", - "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr", - "static_ipaddr", "static_netmask", "static_gateway", - "syslog", "watchdog", "netboot", "evo8serialnumber" }; - -#define MV_MAX_ENV_ENTRY_LENGTH 64 -#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep) - -void mv_reset_environment(void) -{ - int i; - char *s[MV_KEEP_ENTRIES]; - char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH]; - - printf("\n*** RESET ENVIRONMENT ***\n"); - - memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH); - for (i = 0; i < MV_KEEP_ENTRIES; i++) { - s[i] = getenv(entries_to_keep[i]); - if (s[i]) { - printf("save '%s' : %s\n", entries_to_keep[i], s[i]); - strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH); - } - } - - gd->env_valid = 0; - env_relocate(); - - for (i = 0; i < MV_KEEP_ENTRIES; i++) { - if (s[i]) { - printf("restore '%s' : %s\n", entries_to_keep[i], s[i]); - setenv(entries_to_keep[i], s[i]); - } - } - - saveenv(); -} -#endif - -int mv_load_fpga(void) -{ - int result; - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (getenv("skip_fpga")) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - return -1; - } - printf("loading FPGA\n"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - if (!data_size) { - printf("fpgadatasize invalid -> FPGA _not_ loaded !\n"); - return -1; - } - - result = fpga_load(0, fpga_data, data_size); - if (!result) - bootstage_mark(BOOTSTAGE_ID_START); - - return result; -} - -u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - if ((ptr = getenv("dhcp_vendor-class-identifier"))) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - if ((ptr = getenv("dhcp_client_id"))) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - - return e; -} - -u8 *dhcp_vendorex_proc(u8 *popt) -{ - return NULL; -} diff --git a/board/matrix_vision/common/mv_common.h b/board/matrix_vision/common/mv_common.h deleted file mode 100644 index 369394356c..0000000000 --- a/board/matrix_vision/common/mv_common.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright 2008 Matrix Vision GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -extern int mv_load_fpga(void); -extern void mv_reset_environment(void); diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile deleted file mode 100644 index 4df8ce20f9..0000000000 --- a/board/matrix_vision/mergerbox/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o pci.o fpga.o sm107.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/matrix_vision/mergerbox/README b/board/matrix_vision/mergerbox/README deleted file mode 100644 index 1994b65be1..0000000000 --- a/board/matrix_vision/mergerbox/README +++ /dev/null @@ -1,59 +0,0 @@ -Matrix Vision MergerBox ------------------------ - -1. Board Description - - The MergerBox is a 120x160mm single board computing platform - for 3D Full-HD digital video processing. - - Power Supply is 10-32VDC. - -2 System Components - -2.1 CPU - Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. - 256 MByte DDR-II memory @ 333MHz data rate. - 64 MByte Nor Flash on local bus. - 1 GByte Nand Flash on FCM. - 1 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F with 4-Port hub. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. - 2 PCIe x1 busses on local mPCIe and cutom expansion connector. - 2 SATA host ports. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 Graphics - SM107 emebedded video controller driving a 5" 800x480 TFT panel. - Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. - -2.3 FPGA - Altera Cyclone-IV EP4C115 with several PCI DMA engines. - Connects to 7x Gennum 3G-SDI transceivers as video interconnect - as well as a HDMI v1.4 compliant output for 3D monitoring. - Utilizes two more DDR-II controllers providing 256MB memory. - -2.4 I2C - Bus1: - AD7418 @ 0x50 for voltage/temp. monitoring. - SX8650 @ 0x90 touch controller for HMI. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - Bus2: - mPCIe SMBus - SiI9022A @ 0x72/0xC0 HDMI transmitter. - TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. - LMH1983 @ 0xCA video PLL. - DS1338C @ 0xD0 real-time clock with embedded crystal. - 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. - -3 Flash layout. - - reset vector is 0x00000100, i.e. low boot. - - 00000000 u-boot binary. - 00100000 FPGA raw bit file. - 00300000 FIT image holding kernel, dtb and rescue squashfs. - 03d00000 u-boot environment. - 03e00000 splash image - - mtd partitions are propagated to linux kernel via device tree blob. diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c deleted file mode 100644 index 57552c1ae6..0000000000 --- a/board/matrix_vision/mergerbox/fpga.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2011 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mergerbox_init_fpga(void) -{ - debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - dvo &= ~FPGA_CONFIG; - gpio->dat = dvo; - udelay(5); - dvo |= FPGA_CONFIG; - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h deleted file mode 100644 index dbe9bff25f..0000000000 --- a/board/matrix_vision/mergerbox/fpga.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mergerbox_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mergerbox/mergerbox.c b/board/matrix_vision/mergerbox/mergerbox.c deleted file mode 100644 index 5c891d1283..0000000000 --- a/board/matrix_vision/mergerbox/mergerbox.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static void setup_serdes(void) -{ - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram(void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -phys_size_t initdram(int board_type) -{ - u32 msize; - - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize_log2; - - msize = CONFIG_SYS_DDR_SIZE; - msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__("sync"); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); -#endif - setup_serdes(); - - return msize << 20; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision MergerBox\n"); - - return 0; -} - -int misc_init_r(void) -{ - u16 dim; - int result; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1]; - unsigned char mac[6], mac_verify[6]; - char *s = getenv("reset_env"); - - for (dim = 10; dim < 180; dim += 5) { - mergerbox_tft_dim(dim); - udelay(100000); - } - - if (s) - mv_reset_environment(); - - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac)); - - /* check if Matrix Vision prefix present and export to env */ - if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) { - printf("valid MAC found in eeprom: %pM\n", mac); - eth_setenv_enetaddr("ethaddr", mac); - } else { - printf("no valid MAC found in eeprom.\n"); - - /* no: check the env */ - if (!eth_getenv_enetaddr("ethaddr", mac)) { - printf("no valid MAC found in env either.\n"); - /* TODO: ask for valid MAC */ - } else { - printf("valid MAC found in env: %pM\n", mac); - printf("updating MAC in eeprom.\n"); - - do { - result = test_and_clear_bit(20, &gpio->dat); - if (result) - printf("unprotect EEPROM failed !\n"); - udelay(20000); - } while(result); - - i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6); - udelay(20000); - - do { - result = test_and_set_bit(20, &gpio->dat); - if (result) - printf("protect EEPROM failed !\n"); - udelay(20000); - } while(result); - - printf("verify MAC %pM ... ", mac); - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6); - - if (!strncmp((char *)mac, (char *)mac_verify, 6)) - printf("ok.\n"); - else - /* TODO: retry or do something useful */ - printf("FAILED (got %pM) !\n", mac_verify); - } - } - - return 0; -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~TFT_SPI_CPLD_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= TFT_SPI_CPLD_CS; -} - -/* control backlight pwm (display brightness). - * allow values 0-250 with 0 = turn off and 250 = max brightness - */ -void mergerbox_tft_dim(u16 value) -{ - struct spi_slave *slave; - u16 din; - u16 dout = 0; - - if (value > 0 && value < 250) - dout = 0x4000 | value; - - slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH); - spi_claim_bus(slave); - spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END); - spi_release_bus(slave); - spi_free_slave(slave); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - fdt_fixup_dr_usb(blob, bd); - ft_pci_setup(blob, bd); -} diff --git a/board/matrix_vision/mergerbox/mergerbox.h b/board/matrix_vision/mergerbox/mergerbox.h deleted file mode 100644 index 53eab28f3d..0000000000 --- a/board/matrix_vision/mergerbox/mergerbox.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MERGERBOX_H__ -#define __MERGERBOX_H__ - -#define MV_GPIO - -/* - * GPIO Bank 1 - */ -#define TFT_SPI_EN (0x80000000>>0) -#define FPGA_CONFIG (0x80000000>>1) -#define FPGA_STATUS (0x80000000>>2) -#define FPGA_CONF_DONE (0x80000000>>3) -#define FPGA_DIN (0x80000000>>4) -#define FPGA_CCLK (0x80000000>>5) -#define MAN_RST (0x80000000>>6) -#define FPGA_SYS_RST (0x80000000>>7) -#define WD_WDI (0x80000000>>8) -#define TFT_RST (0x80000000>>9) -#define HISCON_GPIO1 (0x80000000>>10) -#define HISCON_GPIO2 (0x80000000>>11) -#define B2B_GPIO2 (0x80000000>>12) -#define CCU_GPIN (0x80000000>>13) -#define CCU_GPOUT (0x80000000>>14) -#define TFT_GPIO0 (0x80000000>>15) -#define TFT_GPIO1 (0x80000000>>16) -#define TFT_GPIO2 (0x80000000>>17) -#define TFT_GPIO3 (0x80000000>>18) -#define B2B_GPIO0 (0x80000000>>19) -#define B2B_GPIO1 (0x80000000>>20) -#define TFT_SPI_CPLD_CS (0x80000000>>21) -#define TFT_SPI_CS (0x80000000>>22) -#define CCU_PWR_EN (0x80000000>>23) -#define B2B_GPIO3 (0x80000000>>24) -#define CCU_PWR_STAT (0x80000000>>25) - -#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS) -#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \ - TFT_SPI_CPLD_CS) -#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST) - -/* - * GPIO Bank 2 - */ -#define SPI_FLASH_WP (0x80000000>>10) -#define SYS_EEPROM_WP (0x80000000>>11) -#define SPI_FLASH_CS (0x80000000>>22) - -#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_ODE 0 - -void mergerbox_tft_dim(u16 value); - -#endif diff --git a/board/matrix_vision/mergerbox/pci.c b/board/matrix_vision/mergerbox/pci.c deleted file mode 100644 index 480f3ed387..0000000000 --- a/board/matrix_vision/mergerbox/pci.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static struct pci_region pci_regions[] = { - { - .bus_start = CONFIG_SYS_PCI_MEM_BASE, - .phys_start = CONFIG_SYS_PCI_MEM_PHYS, - .size = CONFIG_SYS_PCI_MEM_SIZE, - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - .bus_start = CONFIG_SYS_PCI_MMIO_BASE, - .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, - .size = CONFIG_SYS_PCI_MMIO_SIZE, - .flags = PCI_REGION_MEM - }, - { - .bus_start = CONFIG_SYS_PCI_IO_BASE, - .phys_start = CONFIG_SYS_PCI_IO_PHYS, - .size = CONFIG_SYS_PCI_IO_SIZE, - .flags = PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - - volatile gpio83xx_t *gpio; - gpio = (gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO1_DAT; - gpio->odr = MV_GPIO1_ODE; - gpio->dir = MV_GPIO1_OUT; - - gpio = (gpio83xx_t *)&immr->gpio[1]; - - gpio->dat = MV_GPIO2_DAT; - gpio->odr = MV_GPIO2_ODE; - gpio->dir = MV_GPIO2_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - - mergerbox_init_fpga(); - mv_load_fpga(); - - mergerbox_tft_dim(0); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - udelay(2000); - - mpc83xx_pci_init(1, reg); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(2, pcie_reg); -} diff --git a/board/matrix_vision/mergerbox/sm107.c b/board/matrix_vision/mergerbox/sm107.c deleted file mode 100644 index d24f926269..0000000000 --- a/board/matrix_vision/mergerbox/sm107.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "../common/mv_common.h" - -#ifdef CONFIG_VIDEO -static const SMI_REGS init_regs_800x480[] = { - /* set endianess to little endian */ - {0x0005c, 0x00000000}, - /* PCI drive 12mA */ - {0x00004, 0x42401001}, - /* current clock */ - {0x0003c, 0x310a1818}, - /* clocks for pm0... */ - {0x00040, 0x0002184f}, - {0x00044, 0x2a1a0a01}, - /* GPIO */ - {0x10008, 0x00000000}, - {0x1000C, 0x00000000}, - /* panel control regs */ - {0x80000, 0x0f017106}, - {0x80004, 0x0}, - {0x80008, 0x0}, - {0x8000C, 0x00000000}, - {0x80010, 0x0c800c80}, - /* width 0x320 */ - {0x80014, 0x03200000}, - /* height 0x1e0 */ - {0x80018, 0x01E00000}, - {0x8001C, 0x0}, - {0x80020, 0x01df031f}, - {0x80024, 0x041f031f}, - {0x80028, 0x00800347}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00000000}, - /* ZV[0:7] */ - {0x00008, 0x00ff0000}, - /* 24-Bit TFT */ - {0x0000c, 0x3f000000}, - {0, 0} -}; - -/* - * Returns SM107 register base address. First thing called in the driver. - */ -unsigned int board_video_init(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, - (u32 *)&addr); - return addr & 0xfffffffe; - } - - return 0; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen(unsigned int base) -{ -} - -/* - * Returns SM107 framebuffer address - */ -unsigned int board_video_get_fb(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, - (u32 *)&addr); - addr &= 0xfffffffe; -#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET - addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; -#endif - return addr; - } - - printf("board_video_get_fb(): FAILED\n"); - - return 0; -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs(void) -{ - return init_regs_800x480; -} - -int board_get_width(void) -{ - return 800; -} - -int board_get_height(void) -{ - return 480; -} -#endif diff --git a/board/matrix_vision/mvbc_p/Makefile b/board/matrix_vision/mvbc_p/Makefile deleted file mode 100644 index 84add28d40..0000000000 --- a/board/matrix_vision/mvbc_p/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2008 -# Matrix-Vision GmbH, info@matrix-vision.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o fpga.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend diff --git a/board/matrix_vision/mvbc_p/README.mvbc_p b/board/matrix_vision/mvbc_p/README.mvbc_p deleted file mode 100644 index a691137550..0000000000 --- a/board/matrix_vision/mvbc_p/README.mvbc_p +++ /dev/null @@ -1,73 +0,0 @@ -Matrix Vision mvBlueCOUGAR-P (mvBC-P) -------------------------------------- - -1. Board Description - - The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera - with main focus on GigEVision protocol in combination with local image - preprocessing. - - Power Supply is either VDC 48V or Pover over Ethernet (PoE). - -2 System Components - -2.1 CPU - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. - 64MB SDRAM @ 133MHz. - 8 MByte Nor Flash on local bus. - 1 serial ports. Console running on ttyS0 @ 115200 8N1. - -2.2 PCI - PCI clock fixed at 66MHz. Arbitration inside FPGA. - Intel GD82541ER network MAC/PHY and FPGA connected. - -2.3 FPGA - Altera Cyclone-II EP2C8 with PCI DMA engine. - Connects to Matrix Vision specific CCD/CMOS sensor interface. - Utilizes 64MB Nand Flash. - -2.3.1 I/O @ FPGA - 2 Outputs : photo coupler - 2 Inputs : photo coupler - -2.4 I2C - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0x00000100, i.e. "LOWBOOT". - - FF800000 u-boot - FF840000 u-boot script image - FF850000 redundant u-boot script image - FF860000 FPGA raw bit file - FF8A0000 tbd. - FF900000 root FS - FFC00000 kernel - FFFC0000 device tree blob - FFFD0000 redundant device tree blob - FFFE0000 environment - FFFF0000 redundant environment - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF840000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c deleted file mode 100644 index b88f43f3e3..0000000000 --- a/board/matrix_vision/mvbc_p/fpga.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "fpga.h" -#include "mvbc_p.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C8_SIZE, - (void *) &altera_fns, - NULL, -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvbc_p_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->simple_dvo = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->simple_ival & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->sint_ival & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->simple_dvo = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val) -{ - int i; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - for (i=0; i<8; i++) { - dvo &= ~FPGA_CCLK; - gpio->simple_dvo = dvo; - dvo &= ~FPGA_DIN; - if (val & 1) - dvo |= FPGA_DIN; - gpio->simple_dvo = dvo; - dvo |= FPGA_CCLK; - gpio->simple_dvo = dvo; - val >>= 1; - } - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i]); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h deleted file mode 100644 index 96d34654c9..0000000000 --- a/board/matrix_vision/mvbc_p/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvbc_p_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c deleted file mode 100644 index 8faebeeebe..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2007 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" -#include "mvbc_p.h" -#include "../common/mv_common.h" - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start (int hi_addr) -{ - long hi_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit); - - /* precharge all banks */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit); - - /* precharge all banks */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit); - - /* auto refresh */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit); - - /* set mode register */ - out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); -} - -phys_addr_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong test1, - test2; - - /* setup SDRAM chip selects */ - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); - - /* setup config registers */ - out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - if (dramsize < (1 << 20)) - dramsize = 0; - - if (dramsize > 0) - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - else - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0); - - return dramsize; -} - -void mvbc_init_gpio(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG); - - out_be32(&gpio->simple_ddr, SIMPLE_DDR); - out_be32(&gpio->simple_dvo, SIMPLE_DVO); - out_be32(&gpio->simple_ode, SIMPLE_ODE); - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); - - out_8(&gpio->sint_ode, SINT_ODE); - out_8(&gpio->sint_ddr, SINT_DDR); - out_8(&gpio->sint_dvo, SINT_DVO); - out_8(&gpio->sint_inten, SINT_INTEN); - out_be16(&gpio->sint_itype, SINT_ITYPE); - out_8(&gpio->sint_gpioe, SINT_GPIOEN); - - out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE); - out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR); - out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO); - out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN); - - printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe); - printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe); -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (!s) { - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - udelay(50000); - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - udelay(50000); - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - } - printf(" === FACTORY RESET ===\n"); - mv_reset_environment(); - saveenv(); - - return -1; -} - -int checkboard(void) -{ - mvbc_init_gpio(); - printf("Board: Matrix Vision mvBlueCOUGAR-P\n"); - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1); -} - -void flash_afterinit(ulong size) -{ - out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START | - size)); - out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START | - size)); - out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, - size)); - out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, - size)); -} - -void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line = 0xff; - char *s = getenv("pci_latency"); - u32 base; - u8 val = 0; - - if (s) - val = simple_strtoul(s, NULL, 16); - - if (PCI_BUS(dev) == 0) { - switch (PCI_DEV (dev)) { - case 0xa: /* FPGA */ - line = 3; - pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base); - printf("found FPGA - enable arbitration\n"); - writel(0x03, (u32*)(base + 0x80c0)); - writel(0xf0, (u32*)(base + 0x8080)); - if (val) - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); - break; - case 0xb: /* LAN */ - line = 2; - if (val) - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); - break; - case 0x1a: - break; - default: - printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev)); - break; - } - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line); - } -} - -struct pci_controller hose = { - fixup_irq:pci_mvbc_fixup_irq -}; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - mvbc_p_init_fpga(); - mv_load_fpga(); - pci_mpc5xxx_init(&hose); -} - -void show_boot_progress(int val) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - switch(val) { - case BOOTSTAGE_ID_START: /* FPGA ok */ - setbits_be32(&gpio->simple_dvo, LED_G0); - break; - case BOOTSTAGE_ID_NET_ETH_INIT: - setbits_be32(&gpio->simple_dvo, LED_G1); - break; - case BOOTSTAGE_ID_COPY_RAMDISK: - setbits_be32(&gpio->simple_dvo, LED_Y); - break; - case BOOTSTAGE_ID_RUN_OS: - setbits_be32(&gpio->simple_dvo, LED_R); - break; - default: - break; - } - -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h deleted file mode 100644 index be1542b773..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0 -#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1 -#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2 -#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3 -#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4 - -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 -#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 - -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 -#define FACT_RST MPC5XXX_GPIO_WKUP_6 -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 - -#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \ - FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI) -#define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R) -#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \ - FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\ - WD_WDI | COP_PRESENT) - -#define SINT_ODE 0 -#define SINT_DDR 0 -#define SINT_DVO 0 -#define SINT_INTEN 0 -#define SINT_ITYPE 0 -#define SINT_GPIOEN (FPGA_STATUS) - -#define WKUP_ODE (MAN_RST) -#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS) -#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS) -#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY) - -#endif diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript deleted file mode 100644 index 9b21f30ece..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p_autoscript +++ /dev/null @@ -1,48 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1 -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${oprofile} = yes; -then -setenv addprofile setenv bootargs \${bootargs} profile=\${profile} -fi -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile deleted file mode 100644 index b65728092d..0000000000 --- a/board/matrix_vision/mvblm7/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o pci.o fpga.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - @mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/matrix_vision/mvblm7/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7 deleted file mode 100644 index a0686f7fa5..0000000000 --- a/board/matrix_vision/mvblm7/README.mvblm7 +++ /dev/null @@ -1,84 +0,0 @@ -Matrix Vision mvBlueLYNX-M7 (mvBL-M7) -------------------------------------- - -1. Board Description - - The mvBL-M7 is a 120x120mm single board computing platform - with strong focus on stereo image processing applications. - - Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) - on any port (requires add-on board). - -2 System Components - -2.1 CPU - Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. - 512MByte DDR-II memory @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 SD-Card slot connected to SPI. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 PCI - A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. - -2.3 FPGA - Altera Cyclone-II EP2C20/35 with PCI DMA engines. - Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. - Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. - -2.3.1 I/O @ FPGA - 2x8 Outputs : Infineon High-Side Switches to Main Supply. - 2x8 Inputs : Programmable input threshold + trigger capabilities - 2 dedicated flash interfaces for illuminator boards. - Cross trigger for chaining several boards. - -2.4 I2C - Bus1: - MAX5381 DAC @ 0x60 for 1st digital input threshold. - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - 1st image sensor interface (slave addresses depend on sensor) - Bus2: - MAX5381 DAC @ 0x60 for 2nd digital input threshold. - 2nd image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0xFFF00100, i.e. "HIGHBOOT". - - FF800000 environment - FF802000 redundant environment - FF804000 u-boot script image - FF806000 redundant u-boot script image - FF808000 device tree blob - FF80A000 redundant device tree blob - FF80C000 tbd. - FF80E000 tbd. - FF810000 kernel - FFC00000 root FS - FFF00000 u-boot - FFF80000 FPGA raw bit file - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF804000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvblm7/bootscript b/board/matrix_vision/mvblm7/bootscript deleted file mode 100644 index dc385fde79..0000000000 --- a/board/matrix_vision/mvblm7/bootscript +++ /dev/null @@ -1,43 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c deleted file mode 100644 index c0c5bedb2a..0000000000 --- a/board/matrix_vision/mvblm7/fpga.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "fpga.h" -#include "mvblm7.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvblm7_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - fpga_debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - fpga_debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - fpga_debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h deleted file mode 100644 index b480c09b24..0000000000 --- a/board/matrix_vision/mvblm7/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvblm7_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c deleted file mode 100644 index f3c16a3e9c..0000000000 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif - -#include "../common/mv_common.h" -#include "mvblm7.h" - -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - char *s = getenv("ddr_size"); - - msize = CONFIG_SYS_DDR_SIZE; - if (s) { - u32 env_ddr_size = simple_strtoul(s, NULL, 10); - if (env_ddr_size == 512) - msize = 512; - } - - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - - asm("sync;isync"); - udelay(600); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - asm("sync;isync"); - udelay(500); - - return msize; -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); - - /* return total bus RAM size(bytes) */ - return msize * 1024 * 1024; -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - mv_reset_environment(); - } - - return 0; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} - -#ifdef CONFIG_HARD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~MVBLM7_MMC_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= ~MVBLM7_MMC_CS; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} - -#endif diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h deleted file mode 100644 index de9fec7fb8..0000000000 --- a/board/matrix_vision/mvblm7/mvblm7.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define MV_GPIO - -#define FPGA_CONFIG 0x80000000 -#define FPGA_CCLK 0x40000000 -#define FPGA_DIN 0x20000000 -#define FPGA_STATUS 0x10000000 -#define FPGA_CONF_DONE 0x08000000 - -#define WD_WDI 0x00400000 -#define WD_TS 0x00200000 -#define MAN_RST 0x00100000 - -#define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) -#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) - -#endif diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c deleted file mode 100644 index f14837ad40..0000000000 --- a/board/matrix_vision/mvblm7/pci.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif -#include -#include -#include -#include "mvblm7.h" -#include "fpga.h" -#include "../common/mv_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - int i; - volatile immap_t *immr; - volatile pcictrl83xx_t *pci_ctrl; - volatile gpio83xx_t *gpio; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - struct pci_region *reg[] = { pci_regions }; - - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) &immr->clk; - pci_ctrl = immr->pci_ctrl; - pci_law = immr->sysconf.pcilaw; - gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO_DAT; - gpio->odr = MV_GPIO_ODE; - gpio->dir = MV_GPIO_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - mvblm7_init_fpga(); - mv_load_fpga(); - - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); - - /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ - clk->occr = 0xc0000000; - - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - - for (i = 0; i < 1000; ++i) - udelay(1000); - - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} diff --git a/board/matrix_vision/mvblx/Kconfig b/board/matrix_vision/mvblx/Kconfig new file mode 100644 index 0000000000..adbc20a934 --- /dev/null +++ b/board/matrix_vision/mvblx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_MVBLX + +config SYS_BOARD + default "mvblx" + +config SYS_VENDOR + default "matrix_vision" + +config SYS_CONFIG_NAME + default "omap3_mvblx" + +endif diff --git a/board/matrix_vision/mvblx/MAINTAINERS b/board/matrix_vision/mvblx/MAINTAINERS new file mode 100644 index 0000000000..2f9a1532cb --- /dev/null +++ b/board/matrix_vision/mvblx/MAINTAINERS @@ -0,0 +1,6 @@ +MVBLX BOARD +M: Michael Jones +S: Maintained +F: board/matrix_vision/mvblx/ +F: include/configs/omap3_mvblx.h +F: configs/omap3_mvblx_defconfig diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile index 169376136a..c056ebaf78 100644 --- a/board/matrix_vision/mvblx/Makefile +++ b/board/matrix_vision/mvblx/Makefile @@ -5,27 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y += mvblx.o fpga.o +obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o -LIB = $(obj)lib$(BOARD).o - -COBJS-y += mvblx.o fpga.o -COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o -COBJS := $(COBJS-y) - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -CFLAGS += -Werror - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ccflags-y += -Werror diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c index a69359fa1d..c9d615b79a 100644 --- a/board/matrix_vision/mvblx/mvblx.c +++ b/board/matrix_vision/mvblx/mvblx.c @@ -94,6 +94,12 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); + twl4030_power_mmc_init(1); +} #endif #if defined(CONFIG_CMD_NET) diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c index 1a2ac8d6c8..db42987010 100644 --- a/board/matrix_vision/mvblx/sys_eeprom.c +++ b/board/matrix_vision/mvblx/sys_eeprom.c @@ -348,7 +348,7 @@ int mac_read_from_eeprom(void) if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) && memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { - char ethaddr[9]; + char ethaddr[18]; sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", e.mac[0], diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile deleted file mode 100644 index 0e53e8df21..0000000000 --- a/board/matrix_vision/mvsmr/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2008 -# Matrix-Vision GmbH, info@matrix-vision.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o fpga.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - @mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend diff --git a/board/matrix_vision/mvsmr/README.mvsmr b/board/matrix_vision/mvsmr/README.mvsmr deleted file mode 100644 index 8e34cb7838..0000000000 --- a/board/matrix_vision/mvsmr/README.mvsmr +++ /dev/null @@ -1,55 +0,0 @@ -Matrix Vision mvSMR -------------------- - -1. Board Description - - The mvSMR is a 75x130mm single image processing board used - in automation. Power Supply is 24VDC. - -2 System Components - -2.1 CPU - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. - 64MB DDR-I @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - -2.2 PCI - PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core. - -2.3 FPGA - Xilinx Spartan-3 XC3S200 with PCI DMA engine. - Connects to Matrix Vision specific CCD/CMOS sensor interface. - -2.4 I2C - EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0x00000100, i.e. "LOWBOOT". - - FF800000 u-boot - FF806000 u-boot script image - FF808000 u-boot environment - FF840000 FPGA raw bit file - FF880000 root FS - FFF00000 kernel - -4 Booting - - On startup the bootscript @ FF806000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript deleted file mode 100644 index 02c802c8c7..0000000000 --- a/board/matrix_vision/mvsmr/bootscript +++ /dev/null @@ -1,42 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}' -setenv ramkernel 'setenv kernel_boot ${loadaddr}' -setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}' -setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}' -setenv bootfromflash run flashkernel cpird addcons boot24 -setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel' -if test ${console} = yes; -then -setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8' -else -setenv addcons 'setenv bootargs ${bootargs} console=tty0' -fi -setenv set_static_ip 'setenv ipaddr ${static_ipaddr}' -setenv set_static_nm 'setenv netmask ${static_netmask}' -setenv set_static_gw 'setenv gatewayip ${static_gateway}' -setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}' -if test ${servicemode} != yes; -then - echo "=== forced flash mode ===" - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash -fi -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip bootfromnet addcons boot24 - else - echo "=== netboot failed ===" - fi - fi - echo "=== bootfromflash ===" - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c deleted file mode 100644 index 88035a9e9e..0000000000 --- a/board/matrix_vision/mvsmr/fpga.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2010 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include "fpga.h" -#include "mvsmr.h" - -Xilinx_Spartan3_Slave_Serial_fns fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_clk_fn, - fpga_init_fn, - fpga_done_fn, - fpga_wr_fn, - 0 -}; - -Xilinx_desc spartan3 = { - Xilinx_Spartan2, - slave_serial, - XILINX_XC3S200_SIZE, - (void *) &fpga_fns, - 0, -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvsmr_init_fpga(void) -{ - fpga_init(); - fpga_add(fpga_xilinx, &spartan3); - - return 1; -} - -int fpga_init_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (in_be32(&gpio->simple_ival) & FPGA_CONFIG) - return 0; - - return 1; -} - -int fpga_done_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - int result = 0; - - udelay(10); - if (in_be32(&gpio->simple_ival) & FPGA_DONE) - result = 1; - - return result; -} - -int fpga_pgm_fn(int assert, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (!assert) - setbits_8(&gpio->sint_dvo, FPGA_STATUS); - else - clrbits_8(&gpio->sint_dvo, FPGA_STATUS); - - return assert; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (assert_clk) - setbits_be32(&gpio->simple_dvo, FPGA_CCLK); - else - clrbits_be32(&gpio->simple_dvo, FPGA_CCLK); - - return assert_clk; -} - -int fpga_wr_fn(int assert_write, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (assert_write) - setbits_be32(&gpio->simple_dvo, FPGA_DIN); - else - clrbits_be32(&gpio->simple_dvo, FPGA_DIN); - - return assert_write; -} - -int fpga_pre_config_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - setbits_8(&gpio->sint_dvo, FPGA_STATUS); - - return 0; -} diff --git a/board/matrix_vision/mvsmr/fpga.h b/board/matrix_vision/mvsmr/fpga.h deleted file mode 100644 index 7ef878bd44..0000000000 --- a/board/matrix_vision/mvsmr/fpga.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvsmr_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_pre_config_fn(int cookie); diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c deleted file mode 100644 index 2c513897f8..0000000000 --- a/board/matrix_vision/mvsmr/mvsmr.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2010 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" -#include "mvsmr.h" -#include "../common/mv_common.h" - -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x715f0f00 -#define SDRAM_CONFIG1 0xd3722930 -#define SDRAM_CONFIG2 0x46770000 - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start(int hi_addr) -{ - long hi_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | - hi_bit); - - /* precharge all banks */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | - hi_bit); - - /* set mode register: extended mode */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); - - /* precharge all banks */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | - hi_bit); - - /* auto refresh */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | - hi_bit); - - /* set mode register */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); -} - -phys_addr_t initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, - test2; - - /* setup SDRAM chip selects */ - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); - - /* setup config registers */ - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - if (dramsize < (1 << 20)) - dramsize = 0; - - if (dramsize > 0) - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - else - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0); - - return dramsize; -} - -void mvsmr_init_gpio(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG)); - - out_be32(&gpio->simple_ddr, SIMPLE_DDR); - out_be32(&gpio->simple_dvo, SIMPLE_DVO); - out_be32(&gpio->simple_ode, SIMPLE_ODE); - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); - - out_8(&gpio->sint_ode, SINT_ODE); - out_8(&gpio->sint_ddr, SINT_DDR); - out_8(&gpio->sint_dvo, SINT_DVO); - out_8(&gpio->sint_inten, SINT_INTEN); - out_be16(&gpio->sint_itype, SINT_ITYPE); - out_8(&gpio->sint_gpioe, SINT_GPIOEN); - - out_8(&wu_gpio->ode, WKUP_ODE); - out_8(&wu_gpio->ddr, WKUP_DIR); - out_8(&wu_gpio->dvo, WKUP_DO); - out_8(&wu_gpio->enable, WKUP_EN); - - out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */ - out_be32(&timers->gpt1.emsr, 0x00000234); - out_be32(&timers->gpt2.emsr, 0x00000234); - out_be32(&timers->gpt3.emsr, 0x00000234); - out_be32(&timers->gpt4.emsr, 0x00000234); - out_be32(&timers->gpt5.emsr, 0x00000234); - out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */ - out_be32(&timers->gpt7.emsr, 0x00000024); -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - printf(" === FACTORY RESET ===\n"); - mv_reset_environment(); - saveenv(); - } - - return -1; -} - -void mvsmr_get_dbg_present(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - if (in_be32(&gpio->simple_ival) & COP_PRESENT) { - setenv("dbg_present", "no\0"); - setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0"); - } else { - setenv("dbg_present", "yes\0"); - setenv("bootstopkey", "s\0"); - setbits_8(&psc->command, PSC_RX_ENABLE); - } -} - -void mvsmr_get_service_mode(void) -{ - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - if (in_8(&wu_gpio->ival) & SERVICE_MODE) - setenv("servicemode", "no\0"); - else - setenv("servicemode", "yes\0"); -} - -int mvsmr_get_mac(void) -{ - unsigned char mac[6]; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - if (in_8(&wu_gpio->ival) & LAN_PRSNT) { - setenv("lan_present", "no\0"); - return -1; - } else - setenv("lan_present", "yes\0"); - - i2c_read(0x50, 0, 1, mac, 6); - - eth_setenv_enetaddr("ethaddr", mac); - - return 0; -} - -int checkboard(void) -{ - mvsmr_init_gpio(); - printf("Board: Matrix Vision mvSMR\n"); - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1); -} - -void flash_afterinit(ulong size) -{ - out_be32((u32 *)MPC5XXX_BOOTCS_START, - START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32 *)MPC5XXX_CS0_START, - START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32 *)MPC5XXX_BOOTCS_STOP, - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); - out_be32((u32 *)MPC5XXX_CS0_STOP, - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); -} - -struct pci_controller hose; - -void pci_init_board(void) -{ - mvsmr_get_dbg_present(); - mvsmr_get_service_mode(); - mvsmr_init_fpga(); - mv_load_fpga(); - pci_mpc5xxx_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - if (!mvsmr_get_mac()) - return cpu_eth_init(bis); - - return pci_eth_init(bis); -} diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h deleted file mode 100644 index b8320f1e6e..0000000000 --- a/board/matrix_vision/mvsmr/mvsmr.h +++ /dev/null @@ -1,43 +0,0 @@ -#include - -extern void pci_mpc5xxx_init(struct pci_controller *); - -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 -#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 -#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5 -#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6 -#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7 -#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8 -#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9 - -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 -#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6 -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 -#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4 -#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4 - -#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\ - S_FPGA_CCLK) -#define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG) -#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\ - S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT) - -#define SINT_ODE 0x1 -#define SINT_DDR 0x3 -#define SINT_DVO 0x1 -#define SINT_INTEN 0 -#define SINT_ITYPE 0 -#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG) - -#define WKUP_ODE (MAN_RST | S_FPGA_STATUS) -#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS) -#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS) -#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\ - FLASH_RBY | UART_EN1 | LAN_PRSNT) diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds deleted file mode 100644 index 08ce014aac..0000000000 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2010 - * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the first two sectors (=8KB) of our S29GL flash chip */ - arch/powerpc/cpu/mpc5xxx/start.o (.text*) - arch/powerpc/cpu/mpc5xxx/traps.o (.text*) - board/matrix_vision/common/libmatrix_vision.o (.text*) - - /* This is only needed to force failure if size of above code will ever */ - /* increase and grow into reserved space. */ - . = ALIGN(0x2000); /* location counter has to be 0x4000 now */ - . += 0x4000; /* ->0x8000, i.e. move to env_offset */ - - . = env_offset; /* ld error as soon as above ALIGN misplaces lc */ - common/env_embedded.o (.ppcenv) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig new file mode 100644 index 0000000000..d833ca0e25 --- /dev/null +++ b/board/maxbcm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MAXBCM + +config SYS_BOARD + default "maxbcm" + +config SYS_SOC + default "armada-xp" + +config SYS_CONFIG_NAME + default "maxbcm" + +endif diff --git a/board/maxbcm/MAINTAINERS b/board/maxbcm/MAINTAINERS new file mode 100644 index 0000000000..3c8af21216 --- /dev/null +++ b/board/maxbcm/MAINTAINERS @@ -0,0 +1,6 @@ +MAXBCM BOARD +M: Stefan Roese +S: Maintained +F: board/maxbcm/ +F: include/configs/maxbcm.h +F: configs/maxbcm_defconfig diff --git a/board/maxbcm/Makefile b/board/maxbcm/Makefile new file mode 100644 index 0000000000..37c17d6d29 --- /dev/null +++ b/board/maxbcm/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := maxbcm.o diff --git a/board/maxbcm/binary.0 b/board/maxbcm/binary.0 new file mode 100644 index 0000000000..17bfad99dc --- /dev/null +++ b/board/maxbcm/binary.0 @@ -0,0 +1,17 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. + +In a few weeks, mainline U-Boot will get support to generate the +bin_hdr with the DDR training code itself. By implementing this code +as SPL U-Boot. Then this file will not be needed any more and will +get removed. + diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg new file mode 100644 index 0000000000..5a3bc67c1c --- /dev/null +++ b/board/maxbcm/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/maxbcm/binary.0 0000005b 00000068 diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c new file mode 100644 index 0000000000..7fc83ee820 --- /dev/null +++ b/board/maxbcm/maxbcm.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Base addresses for the external device chip selects */ +#define DEV_CS0_BASE 0xe0000000 +#define DEV_CS1_BASE 0xe1000000 +#define DEV_CS2_BASE 0xe2000000 +#define DEV_CS3_BASE 0xe3000000 + +/* Needed for dynamic (board-specific) mbus configuration */ +extern struct mvebu_mbus_state mbus_state; + +int board_early_init_f(void) +{ + /* + * Don't configure MPP (pin multiplexing) and GPIO here, + * its already done in bin_hdr + */ + + /* + * Setup some board specific mbus address windows + */ + mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0); + mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); + mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2); + mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: maxBCM\n"); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E6185 switch */ +void reset_phy(void) +{ + u16 devadr = CONFIG_PHY_BASE_ADDR; + char *name = "neta0"; + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* todo: fill this with the real setup / config code */ + + printf("88E6185 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile deleted file mode 100644 index 1097314052..0000000000 --- a/board/mbx8xx/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o vpd.o pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mbx8xx/README b/board/mbx8xx/README deleted file mode 100644 index c889fe9791..0000000000 --- a/board/mbx8xx/README +++ /dev/null @@ -1,68 +0,0 @@ -IMPORTANT NOTE - read before defining CONFIG_SYS_USE_OSCCLK in your board - config file!!! - - -WARNING: Wrong settings of this parameter have the potential to -damage hardware by running the MBX's CPU at frequencies that exceed -it's rating and/or overdriving the it's SPLL! - - -Ramblings: -1) Motorola offered 12 different variants of the MBX, 6 823s and 6 860s. -2) Of these 12 variants, only 2 were entry level boards. -3) I believe that the 2 entry level boards were the only ones that - used OSCM clocking. I can't be completely certain of this at this - point. -4) Motorola never offered an MBX that ran faster than 50Mhz. -5) The 10, non-entry level boards, ran at 40Mhz. -6) The EXTCLK input has a minimum clock of 15Mhz for the 823/860. -7) Motorola no longer sells MBXs. - -Based on this information, I can surmise that the default power-on -reset clocking was one of the following three options. - -Multiplier SPLL Options ------------------------------------- -513 OSCM is SPLL input -5 OSCM is SPLL input -1 EXTCLK is SPLL input - -The forth option: - -5 EXTCLK is SPLL input - -is not possible on MBXs. This is because the minimum EXTCLK input -frequency is 15Mhz. 5 * 15Mhz = 75 Mhz. There was no variant that ran -above 50 Mhz. - -The board I have borrowed definitely uses a multiplier of 1 for -EXTCLK and runs at 40Mhz. I even went so far as to put a scope on it. - -One of the two default OSCM modes are most likely what was used on -the entry level boards to cheapen them by eliminating the external -crystal oscillator. - -To add insult to injury, the stupid 860 PLPRCR register retains it's -multiplication factor through hard resets. You can't clear it out -because it is battery backed and once it is set wrong, it stays -wrong. The only way to reset it, so that it takes on it's default -multiplier is to disconnect all power including external, batteries, -as well discharging caps on the board. This precludes the fact that -your 860 may be quite DEAD by this time! - -If you don't setup the multiplication factor for boards that use the -OSCM input, they won't run correctly, but at least they won't be -dead. - -Addtionally, there is no good way to determine the clock input source -from CPU register data. The only way to deal with this is either hard -code it, determine the correct value with some rather NASTY timing -loops, or try to grok it from external data sources. Motorola -firmware opts for the NASTY timing loops, but needs to configure the -serial ports to do so. - - -You may have a legitimate need to define CONFIG_SYS_USE_OSCCLK if your -MBX8xx board is using the OSCM clocking mode. - -You better know what you are doing here. diff --git a/board/mbx8xx/csr.h b/board/mbx8xx/csr.h deleted file mode 100644 index 937060973e..0000000000 --- a/board/mbx8xx/csr.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __csr_h -#define __csr_h - -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Control and Status Register definitions for the MBX - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* bits for control register #1 / status register #1 */ -#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */ -#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */ -#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */ -#define CSR1_TPEN 0x10 /* TP manually selected */ -#define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */ -#define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */ -#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */ -#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */ - -/* bits for control register #2 */ -#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ -#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ -#define CR2_BRDFAIL 0x08 /* Board fail */ -#define CR2_SWS1 0x04 /* Software Status #2 LED */ -#define CR2_SWS2 0x02 /* Software Status #2 LED */ -#define CR2_QSPANRST 0x01 /* Reset QSPAN */ - -/* bits for status register #2 */ -#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ -#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ -#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */ -#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */ -#define SR2_RDY 0x02 /* Flash programming status bit */ -#define SR2_FT 0x01 /* Reserved for Factory test purposes */ - -#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE)) -#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1)) - -#endif /* __csr_h */ diff --git a/board/mbx8xx/dimm.h b/board/mbx8xx/dimm.h deleted file mode 100644 index b40f112356..0000000000 --- a/board/mbx8xx/dimm.h +++ /dev/null @@ -1,98 +0,0 @@ -#ifndef __dimm_h -#define __dimm_h - -/* - * Module name: %M% - * Description: - * Serial Presence Detect Definitions Module - * SCCS identification: %I% - * Branch: %B% - * Sequence: %S% - * Date newest applied delta was created (MM/DD/YY): %G% - * Time newest applied delta was created (HH:MM:SS): %U% - * SCCS file name %F% - * Fully qualified SCCS file name: - * %P% - * Copyright: - * (C) COPYRIGHT MOTOROLA, INC. 1996 - * ALL RIGHTS RESERVED - * Notes: - * 1. All data was taken from an IBM application note titled - * "Serial Presence Detect Definitions". - * History: - * Date Who - * - * 10/24/96 Rob Baxter - * Initial release. - * - */ - -/* - * serial PD byte assignment address map (256 byte EEPROM) - */ -typedef struct dimm -{ - uchar n_bytes; /* 00 number of bytes written/used */ - uchar t_bytes; /* 01 total number of bytes in serial PD device */ - uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */ - uchar n_row; /* 03 number of rows */ - uchar n_col; /* 04 number of columns */ - uchar n_banks; /* 05 number of banks */ - uchar data_w_lo; /* 06 data width */ - uchar data_w_hi; /* 07 data width */ - uchar ifl; /* 08 interface levels */ - uchar a_ras; /* 09 RAS access */ - uchar a_cas; /* 0A CAS access */ - uchar ct; /* 0B configuration type (non-parity/parity/ECC) */ - uchar refresh_rt; /* 0C refresh rate/type */ - uchar p_dram_o; /* 0D primary DRAM organization */ - uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */ - uchar reserved[17]; /* 0F reserved fields for future offerings */ - uchar ss_info[32]; /* 20 superset information (may be used in the future) */ - uchar m_info[64]; /* 40 manufacturer information (optional) */ - uchar unused[128]; /* 80 unused storage locations */ -} dimm_t; - -/* - * memory type definitions - */ -#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */ -#define DIMM_MT_EDO 2 /* EDO (extended data out) */ -#define DIMM_MT_PN 3 /* pipelined nibble */ -#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */ - -/* - * row addresses definitions - */ -#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */ -#define DIMM_RA_MASK 0x7f /* number of row addresses mask */ - -/* - * module interface levels definitions - */ -#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */ -#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */ -#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */ -#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */ -#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */ - -/* - * DIMM configuration type definitions - */ -#define DIMM_CT_NONE 0 /* none */ -#define DIMM_CT_PARITY 1 /* parity */ -#define DIMM_CT_ECC 2 /* ECC */ - -/* - * row addresses definitions - */ -#define DIMM_RRT_SR (1<<7) /* self refresh flag */ -#define DIMM_RRT_MASK 0x7f /* refresh rate mask */ -#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */ -#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */ -#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */ -#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */ -#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */ -#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */ - -#endif /* __dimm_h */ diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c deleted file mode 100644 index fa07152cc8..0000000000 --- a/board/mbx8xx/flash.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AM290[48]0B devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include "vpd.h" - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size, totsize; - int i; - ulong addr; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - return (totsize); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id >> 16) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - - vendor = addr[0]; - devid = addr[1] & 0xff; - - /* only support AMD */ - if (vendor != 0x01010101) { - return 0; - } - - vendor &= 0xf; - devid &= 0xff; - - if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 8; - info->size = info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 16; - info->size = 4 * info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F016D) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = 4 * info->sector_count * 0x10000; - } - else { - printf ("## Unknown Flash Type: %08lx\n", devid); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0XAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0XAAAAAAAA; - addr[0x02AA] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c deleted file mode 100644 index 75b0bb8fe6..0000000000 --- a/board/mbx8xx/mbx8xx.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Board specific routines for the MBX - * - * - initialisation - * - interface to VPD data (mac address, clock speeds) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include "dimm.h" -#include "vpd.h" -#include "csr.h" - -/* ------------------------------------------------------------------------- */ - -static const uint sdram_table_40[] = { - /* DRAM - single read. (offset 0 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, - 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst read. (offset 8 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - single write. (offset 18 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst write. (offset 20 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* refresh (offset 30 in upm RAM) - */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* exception. (offset 3c in upm RAM) - */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, -}; - -static const uint sdram_table_50[] = { - /* DRAM - single read. (offset 0 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, - 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst read. (offset 8 in upm RAM) - */ - 0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04, - /* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */ - 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, - 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04, - /* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */ - 0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005, - - /* DRAM - single write. (offset 18 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, - 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst write. (offset 20 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* refresh (offset 30 in upm RAM) - */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* exception. (offset 3c in upm RAM) - */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, -}; - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_SYS_USE_OSCCLK -static unsigned int get_reffreq(void); -#endif -static unsigned int board_get_cpufreq(void); - -void mbx_init (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - ulong speed, plprcr, sccr; - ulong br0_32 = memctl->memc_br0 & 0x400; - - /* real-time clock status and control register */ - immr->im_sitk.sitk_rtcsck = KAPWR_KEY; - immr->im_sit.sit_rtcsc = 0x00C3; - - /* SIEL and SIMASK Registers (see MBX PRG 2-3) */ - immr->im_siu_conf.sc_simask = 0x00000000; - immr->im_siu_conf.sc_siel = 0xAAAA0000; - immr->im_siu_conf.sc_tesr = 0xFFFFFFFF; - - /* - * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus: - * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h) - * 2. RAM Specs (see dimm.h) - * 2. DIMM Specs (see dimm.h) - */ - vpd_init (); - - /* system clock and reset control register */ - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - sccr = immr->im_clkrst.car_sccr; - sccr &= SCCR_MASK; - sccr |= CONFIG_SYS_SCCR; - immr->im_clkrst.car_sccr = sccr; - - speed = board_get_cpufreq (); - -#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) - plprcr = CONFIG_SYS_PLPRCR; -#else - plprcr = immr->im_clkrst.car_plprcr; - plprcr &= PLPRCR_MF_MSK; /* isolate MF field */ - plprcr |= CONFIG_SYS_PLPRCR; /* reset control bits */ -#endif - -#ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */ - plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20; -#endif - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - immr->im_clkrst.car_plprcr = plprcr; - - /* - * preliminary setup of memory controller: - * - map Flash, otherwise configuration/status - * registers won't be accessible when read - * by board_init_f. - * - map NVRAM and configuation/status registers. - * - map pci registers. - * - DON'T map ram yet, this is done in initdram(). - */ - switch (speed / 1000000) { - case 40: - memctl->memc_br0 = 0xFE000000 | br0_32 | 1; - memctl->memc_or0 = 0xFF800930; - memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920; - memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; - break; - case 50: - memctl->memc_br0 = 0xFE000000 | br0_32 | 1; - memctl->memc_or0 = 0xFF800940; - memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930; - memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; - break; - default: - hang (); - break; - } -#ifdef CONFIG_USE_PCI - memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR; - memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001; - memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR; - memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001; -#endif - /* - * FIXME: I do not understand why I have to call this to - * initialise the control register here before booting from - * the PCMCIA card but if I do not the Linux kernel falls - * over in a big heap. If you can answer this question I - * would like to know about it. - */ - board_ether_init(); -} - -void board_serial_init (void) -{ - MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS); -} - -void board_ether_init (void) -{ - MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN); - MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS; -} - -static unsigned int board_get_cpufreq (void) -{ -#ifndef CONFIG_8xx_GCLK_FREQ - vpd_packet_t *packet; - ulong *p; - - packet = vpd_find_packet (VPD_PID_ICS); - p = (ulong *)packet->data; - return *p; -#else - return((unsigned int)CONFIG_8xx_GCLK_FREQ ); -#endif /* CONFIG_8xx_GCLK_FREQ */ -} - -#ifdef CONFIG_SYS_USE_OSCCLK -static unsigned int get_reffreq (void) -{ - vpd_packet_t *packet; - ulong *p; - - packet = vpd_find_packet (VPD_PID_RCS); - p = (ulong *)packet->data; - return *p; -} -#endif - -static void board_get_enetaddr(uchar *addr) -{ - int i; - vpd_packet_t *packet; - - packet = vpd_find_packet (VPD_PID_EA); - for (i = 0; i < 6; i++) - addr[i] = packet->data[i]; -} - -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - vpd_packet_t *packet; - int i; - const char *const fmt = - "\n *** Warning: Low Battery Status - %s Battery ***"; - - puts ("Board: "); - - packet = vpd_find_packet (VPD_PID_PID); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - packet = vpd_find_packet (VPD_PID_MT); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - serial_putc ('('); - packet = vpd_find_packet (VPD_PID_FAN); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - serial_putc (')'); - - if (!(MBX_CSR2 & SR2_BATGD)) - printf (fmt, "On-Board"); - if (!(MBX_CSR2 & SR2_NVBATGD)) - printf (fmt, "NVRAM"); - - serial_putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -static ulong get_ramsize (dimm_t * dimm) -{ - ulong size = 0; - - if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3 - || dimm->fmt == 4) { - size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks * - ((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8); - } - - return size; -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long ram_sz = 0; - unsigned long dimm_sz = 0; - dimm_t vpd_dimm, vpd_dram; - unsigned int speed = board_get_cpufreq () / 1000000; - - if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) { - dimm_sz = get_ramsize (&vpd_dimm); - } - if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) { - ram_sz = get_ramsize (&vpd_dram); - } - - /* - * Only initialize memory controller when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - ulong dimm_bank; - ulong br0_32 = memctl->memc_br0 & 0x400; - - switch (speed) { - case 40: - upmconfig (UPMA, (uint *) sdram_table_40, - sizeof (sdram_table_40) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000; - memctl->memc_or7 = 0xff800930; - memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; - break; - case 50: - upmconfig (UPMA, (uint *) sdram_table_50, - sizeof (sdram_table_50) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100; - memctl->memc_or7 = 0xff800940; - memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; - break; - default: - hang (); - break; - } - - /* now map ram and dimm, largest one first */ - dimm_bank = dimm_sz / 2; - if (!dimm_sz) { - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_br2 = 0; - memctl->memc_br3 = 0; - } else if (ram_sz > dimm_bank) { - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81; - memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \ - | 0x81; - } else { - memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81; - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81; - } - } - - return ram_sz + dimm_sz; -} diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c deleted file mode 100644 index 497e260a0a..0000000000 --- a/board/mbx8xx/pcmcia.c +++ /dev/null @@ -1,156 +0,0 @@ -#include -#include -#include - -#include "csr.h" - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -/* A lot of this has been taken from the RPX code in this file it works from me. - I have added the voltage selection for the MBX board. */ - -/* MBX voltage bit in control register #2 */ -#define CR2_VPP12 ((uchar)0x10) -#define CR2_VPPVDD ((uchar)0x20) -#define CR2_VDD5 ((uchar)0x40) -#define CR2_VDD3 ((uchar)0x80) - -#define PCMCIA_BOARD_MSG "MBX860" - -int pcmcia_voltage_set (int slot, int vcc, int vpp) -{ - uchar reg = 0; - - debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10); - - switch (vcc) { - case 0: - break; - case 33: - reg |= CR2_VDD3; - break; - case 50: - reg |= CR2_VDD5; - break; - default: - return 1; - } - - switch (vpp) { - case 0: - break; - case 33: - case 50: - if (vcc == vpp) { - reg |= CR2_VPPVDD; - } else { - return 1; - } - break; - case 120: - reg |= CR2_VPP12; - break; - default: - return 1; - } - - /* first, turn off all power */ - MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL); - - /* enable new powersettings */ - MBX_CSR2 |= reg; - debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2); - - return (0); -} - -int pcmcia_hardware_enable (int slot) -{ - volatile pcmconf8xx_t *pcmp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", - 'A' + slot); - - udelay (10000); - - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - udelay (500); - - /* remove all power */ - pcmcia_voltage_set (slot, 0, 0); - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, - (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", - (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); - - if ((reg & mask) == mask) { - pcmcia_voltage_set (_slot_, 50, 0); - printf (" 5.0V card found: "); - } else { - pcmcia_voltage_set (_slot_, 33, 0); - printf (" 3.3V card found: "); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX (_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - - udelay (250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); - } - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable (int slot) -{ - return 0; /* No hardware to disable */ -} -#endif - -#endif /* CONFIG_PCMCIA */ diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/mbx8xx/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug deleted file mode 100644 index 7cfed1f1d5..0000000000 --- a/board/mbx8xx/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/vpd.c b/board/mbx8xx/vpd.c deleted file mode 100644 index 1ba754ee23..0000000000 --- a/board/mbx8xx/vpd.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Code in faintly related to linux/arch/powerpc/8xx_io: - * MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net). - * - * This file implements functions to read the MBX's Vital Product Data - * (VPD). I can't use the more general i2c code in mpc8xx/... since I need - * the VPD at a time where there is no RAM available yet. Hence the VPD is - * read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD). - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#ifdef CONFIG_8xx -#include -#endif -#include "vpd.h" - -/* Location of receive/transmit buffer descriptors - * Allocate one transmit bd and one receive bd. - * IIC_BD_FREE points to free bd space which we'll use as tx buffer. - */ -#define IIC_BD_TX1 (BD_IIC_START + 0*sizeof(cbd_t)) -#define IIC_BD_TX2 (BD_IIC_START + 1*sizeof(cbd_t)) -#define IIC_BD_RX (BD_IIC_START + 2*sizeof(cbd_t)) -#define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t)) - -/* FIXME -- replace 0x2000 with offsetof */ -#define VPD_P ((vpd_t *)(CONFIG_SYS_IMMR + 0x2000 + CONFIG_SYS_DPRAMVPD)) - -/* transmit/receive buffers */ -#define IIC_RX_LENGTH 128 - -#define WITH_MICROCODE_PATCH - -vpd_packet_t * vpd_find_packet(u_char ident) -{ - vpd_packet_t *packet; - vpd_t *vpd = VPD_P; - - packet = (vpd_packet_t *)&vpd->packets; - while ((packet->identifier != ident) && packet->identifier != 0xFF) - { - packet = (vpd_packet_t *)((char *)packet + packet->size + 2); - } - return packet; -} - -void vpd_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); - volatile iic_t *iip; -#ifdef WITH_MICROCODE_PATCH - ulong reloc = 0; -#endif - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - - /* - * kludge: when running from flash, no microcode patch can be - * installed. However, the DPMEM usually contains non-zero - * garbage at the relocatable patch base location, so lets clear - * it now. This way the rest of the code can support the microcode - * patch dynamically. - */ - if ((ulong)vpd_init & 0xff000000) - iip->iic_rpbase = 0; - -#ifdef WITH_MICROCODE_PATCH - /* Check for and use a microcode relocation patch. */ - if ((reloc = iip->iic_rpbase)) - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - /* Initialize Port B IIC pins */ - cp->cp_pbpar |= 0x00000030; - cp->cp_pbdir |= 0x00000030; - cp->cp_pbodr |= 0x00000030; - - i2c->i2c_i2mod = 0x04; /* filter clock */ - i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */ - i2c->i2c_i2brg = 0x07; /* make clock run maximum slow */ - i2c->i2c_i2cmr = 0x00; /* disable interrupts */ - i2c->i2c_i2cer = 0x1f; /* clear events */ - i2c->i2c_i2com = 0x01; /* configure i2c to work as master */ - - if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE) - { - hang(); - } -} - - -/* Read from I2C. - * This is a two step process. First, we send the "dummy" write - * to set the device offset for the read. Second, we perform - * the read operation. - */ -int vpd_read(uint iic_device, uchar *buf, int count, int offset) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); - volatile iic_t *iip; - volatile cbd_t *tbdf1, *tbdf2, *rbdf; - uchar *tb; - uchar event; -#ifdef WITH_MICROCODE_PATCH - ulong reloc = 0; -#endif - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; -#ifdef WITH_MICROCODE_PATCH - /* Check for and use a microcode relocation patch. */ - if ((reloc = iip->iic_rpbase)) - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1]; - tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2]; - rbdf = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX]; - - /* Send a "dummy write" operation. This is a write request with - * only the offset sent, followed by another start condition. - * This will ensure we start reading from the first location - * of the EEPROM. - */ - tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE]; - tb[0] = iic_device & 0xfe; /* device address */ - tb[1] = offset; /* offset */ - tbdf1->cbd_bufaddr = (uint)tb; - tbdf1->cbd_datlen = 2; - tbdf1->cbd_sc = 0x8400; - - tb += 2; - tb[0] = iic_device | 1; /* device address */ - tbdf2->cbd_bufaddr = (uint)tb; - tbdf2->cbd_datlen = count+1; - tbdf2->cbd_sc = 0xbc00; - - rbdf->cbd_bufaddr = (uint)buf; - rbdf->cbd_datlen = 0; - rbdf->cbd_sc = 0xb000; - - iip->iic_tbase = IIC_BD_TX1; - iip->iic_tbptr = IIC_BD_TX1; - iip->iic_rbase = IIC_BD_RX; - iip->iic_rbptr = IIC_BD_RX; - iip->iic_rfcr = 0x15; - iip->iic_tfcr = 0x15; - iip->iic_mrblr = count; - iip->iic_rstate = 0; - iip->iic_tstate = 0; - - i2c->i2c_i2cer = 0x1f; /* clear event mask */ - i2c->i2c_i2mod |= 1; /* enable iic operation */ - i2c->i2c_i2com |= 0x80; /* start master */ - - /* wait for IIC transfer */ - do { - __asm__ volatile ("eieio"); - event = i2c->i2c_i2cer; - } while (event == 0); - - if ((event & 0x10) || (event & 0x04)) { - count = -1; - goto bailout; - } - -bailout: - i2c->i2c_i2mod &= ~1; /* turn off iic operation */ - i2c->i2c_i2cer = 0x1f; /* clear event mask */ - - return count; -} diff --git a/board/mbx8xx/vpd.h b/board/mbx8xx/vpd.h deleted file mode 100644 index 1d9eb7fe20..0000000000 --- a/board/mbx8xx/vpd.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef __vpd_h -#define __vpd_h - -/* - * Module name: %M% - * Description: - * Vital Product Data (VPD) Header Module - * SCCS identification: %I% - * Branch: %B% - * Sequence: %S% - * Date newest applied delta was created (MM/DD/YY): %G% - * Time newest applied delta was created (HH:MM:SS): %U% - * SCCS file name %F% - * Fully qualified SCCS file name: - * %P% - * Copyright: - * (C) COPYRIGHT MOTOROLA, INC. 1996 - * ALL RIGHTS RESERVED - * Notes: - * History: - * Date Who - * - * 10/24/96 Rob Baxter - * Initial release. - * - */ - -#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */ - -/* - * packet tuple identifiers - * - * 0x0D - 0xBF reserved - * 0xC0 - 0xFE user defined - */ -#define VPD_PID_GI 0x00 /* guaranteed illegal */ -#define VPD_PID_PID 0x01 /* product identifier (ASCII) */ -#define VPD_PID_FAN 0x02 /* factory assembly-number (ASCII) */ -#define VPD_PID_SN 0x03 /* serial-number (ASCII) */ -#define VPD_PID_PCO 0x04 /* product configuration options(binary) */ -#define VPD_PID_ICS 0x05 /* internal clock speed in HZ (integer) */ -#define VPD_PID_ECS 0x06 /* external clock speed in HZ (integer) */ -#define VPD_PID_RCS 0x07 /* reference clock speed in HZ(integer) */ -#define VPD_PID_EA 0x08 /* ethernet address (binary) */ -#define VPD_PID_MT 0x09 /* microprocessor type (ASCII) */ -#define VPD_PID_CRC 0x0A /* EEPROM CRC (integer) */ -#define VPD_PID_FMC 0x0B /* FLASH memory configuration (binary) */ -#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */ -#define VPD_PID_TERM 0xFF /* termination */ - -/* - * VPD structure (format) - */ -#define VPD_EYE_SIZE 8 /* eyecatcher size */ -typedef struct vpd_header -{ - uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */ - ushort size; /* size of EEPROM */ -} vpd_header_t; - -#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t)) -typedef struct vpd -{ - vpd_header_t header; /* header */ - uchar packets[VPD_DATA_SIZE]; /* data */ -} vpd_t; - -/* - * packet tuple structure (format) - */ -typedef struct vpd_packet -{ - uchar identifier; /* identifier (PIDs above) */ - uchar size; /* size of the following data area */ - uchar data[1]; /* data (size is dependent upon PID) */ -} vpd_packet_t; - -/* - * MBX product configuration options bit definitions - * - * Notes: - * 1. The bit numbering is reversed in perspective with the C compiler. - */ -#define PCO_BBRAM (1<<0) /* battery-backed RAM (BBRAM) and socket */ -#define PCO_BOOTROM (1<<1) /* boot ROM and socket (i.e., socketed FLASH) */ -#define PCO_KAPWR (1<<2) /* keep alive power source (lithium battey) and control circuit */ -#define PCO_ENET_TP (1<<3) /* ethernet twisted pair (TP) connector (RJ45) */ -#define PCO_ENET_AUI (1<<4) /* ethernet attachment unit interface (AUI) header */ -#define PCO_PCMCIA (1<<5) /* PCMCIA socket */ -#define PCO_DIMM (1<<6) /* DIMM module socket */ -#define PCO_DTT (1<<7) /* digital thermometer and thermostat (DTT) device */ -#define PCO_LCD (1<<8) /* liquid crystal display (LCD) device */ -#define PCO_PCI (1<<9) /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */ -#define PCO_PCIO (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */ -#define PCO_EIDE (1<<11) /* enhanced IDE (EIDE) header */ -#define PCO_FDC (1<<12) /* floppy disk controller (FDC) header */ -#define PCO_LPT_8XX (1<<13) /* parallel port header via MPC8xx */ -#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */ - -/* - * FLASH memory configuration packet data - */ -typedef struct vpd_fmc -{ - ushort mid; /* manufacturer's idenitfier */ - ushort did; /* manufacturer's device idenitfier */ - uchar ddw; /* device data width (e.g., 8-bits, 16-bits) */ - uchar nod; /* number of devices present */ - uchar noc; /* number of columns */ - uchar cw; /* column width in bits */ - uchar wedw; /* write/erase data width */ -} vpd_fmc_t; - -/* function prototypes */ -extern void vpd_init(void); -extern int vpd_read(uint iic_device, uchar *buf, int count, int offset); -extern vpd_packet_t *vpd_find_packet(u_char ident); - -#endif /* __vpd_h */ diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile deleted file mode 100644 index 5019b315f6..0000000000 --- a/board/mcc200/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o lcd.o auto_update.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c deleted file mode 100644 index 2f622b0846..0000000000 --- a/board/mcc200/auto_update.c +++ /dev/null @@ -1,526 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SYS_HUSH_PARSER -#include -#endif - - -#ifdef CONFIG_AUTO_UPDATE - -#ifndef CONFIG_USB_OHCI -#error "must define CONFIG_USB_OHCI" -#endif - -#ifndef CONFIG_USB_STORAGE -#error "must define CONFIG_USB_STORAGE" -#endif - -#ifndef CONFIG_SYS_HUSH_PARSER -#error "must define CONFIG_SYS_HUSH_PARSER" -#endif - -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" -#endif - -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - -/* possible names of files on the USB stick. */ -#define AU_FIRMWARE "u-boot.img" -#define AU_KERNEL "kernel.img" -#define AU_ROOTFS "rootfs.img" - -struct flash_layout { - long start; - long end; -}; - -/* layout of the FLASH. ST = start address, ND = end address. */ -#define AU_FL_FIRMWARE_ST 0xfC000000 -#define AU_FL_FIRMWARE_ND 0xfC03FFFF -#define AU_FL_KERNEL_ST 0xfC0C0000 -#define AU_FL_KERNEL_ND 0xfC1BFFFF -#define AU_FL_ROOTFS_ST 0xFC1C0000 -#define AU_FL_ROOTFS_ND 0xFCFBFFFF - -static int au_usb_stor_curr_dev; /* current device */ - -/* index of each file in the following arrays */ -#define IDX_FIRMWARE 0 -#define IDX_KERNEL 1 -#define IDX_ROOTFS 2 - -/* max. number of files which could interest us */ -#define AU_MAXFILES 3 - -/* pointers to file names */ -char *aufile[AU_MAXFILES] = { - AU_FIRMWARE, - AU_KERNEL, - AU_ROOTFS -}; - -/* sizes of flash areas for each file */ -long ausize[AU_MAXFILES] = { - (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST, - (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST, - (AU_FL_ROOTFS_ND + 1) - AU_FL_ROOTFS_ST, -}; - -/* array of flash areas start and end addresses */ -struct flash_layout aufl_layout[AU_MAXFILES] = { - { AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND, }, - { AU_FL_KERNEL_ST, AU_FL_KERNEL_ND, }, - { AU_FL_ROOTFS_ST, AU_FL_ROOTFS_ND, }, -}; - -ulong totsize; - -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x00200000) - -/* the root file system is the largest image */ -#define MAX_LOADSZ ausize[IDX_ROOTFS] - -/*i2c address of the keypad status*/ -#define I2C_PSOC_KEYPAD_ADDR 0x53 - -/* keypad mask */ -#define KEYPAD_ROW 2 -#define KEYPAD_COL 2 -#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF) -#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8) - -/* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); -extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int); -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); -extern int u_boot_hush_start(void); -#ifdef CONFIG_PROGRESSBAR -extern void show_progress(int, int); -extern void lcd_puts (char *); -extern void lcd_enable(void); -#endif - -int au_check_cksum_valid(int idx, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if (nbytes != image_get_image_size (hdr)) { - printf ("Image %s bad total SIZE\n", aufile[idx]); - return -1; - } - /* check the data CRC */ - if (!image_check_dcrc (hdr)) { - printf ("Image %s bad data checksum\n", aufile[idx]); - return -1; - } - return 0; -} - -int au_check_header_valid(int idx, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum, fsize; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); - printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM); - printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); - printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); -#endif - if (nbytes < image_get_header_size ()) { - printf ("Image %s bad header SIZE\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { - printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* check the hdr CRC */ - if (!image_check_hcrc (hdr)) { - printf ("Image %s bad header checksum\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* check the type - could do this all in one gigantic if() */ - if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if ((idx == IDX_ROOTFS) && - (!image_check_type (hdr, IH_TYPE_RAMDISK) && - !image_check_type (hdr, IH_TYPE_FILESYSTEM))) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* recycle checksum */ - checksum = image_get_data_size (hdr); - - fsize = checksum + image_get_header_size (); - /* for kernel and ramdisk the image header must also fit into flash */ - if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK)) - checksum += image_get_header_size (); - - /* check the size does not exceed space in flash. HUSH scripts */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* Update with the real filesize */ - ausize[idx] = fsize; - - return checksum; /* return size to be written to flash */ -} - -int au_do_update(int idx, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; - addr += 8; - parse_string_outer(addr, FLAG_PARSE_SEMICOLON); - return 0; - } - - start = aufl_layout[idx].start; - end = aufl_layout[idx].end; - - /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) { -#undef AU_UPDATE_TEST -#ifdef AU_UPDATE_TEST - /* erase it where Linux goes */ - start = aufl_layout[1].start; - end = aufl_layout[1].end; -#endif - flash_sect_protect(0, start, end); - } - - /* - * erase the address range. - */ - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); - mdelay(100); -#ifdef CONFIG_PROGRESSBAR - show_progress(end - start, totsize); -#endif - - /* strip the header - except for the kernel and ramdisk */ - if (image_check_type (hdr, IH_TYPE_KERNEL) || - image_check_type (hdr, IH_TYPE_RAMDISK)) { - addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); - } else { - addr = (char *)((char *)hdr + image_get_header_size ()); -#ifdef AU_UPDATE_TEST - /* copy it to where Linux goes */ - if (idx == IDX_FIRMWARE) - start = aufl_layout[1].start; -#endif - off = 0; - nbytes = image_get_data_size (hdr); - } - - /* copy the data from RAM to FLASH */ - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write(addr, start, nbytes); - if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); - return -1; - } - -#ifdef CONFIG_PROGRESSBAR - show_progress(nbytes, totsize); -#endif - - /* check the data CRC of the copy */ - if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) != - image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) - flash_sect_protect(1, start, end); - return 0; -} - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int do_auto_update(void) -{ - block_dev_desc_t *stor_dev; - long sz; - int i, res = 0, cnt, old_ctrlc; - char *env; - long start, end; - -#if 0 /* disable key-press detection to speed up boot-up time */ - uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0}; - - /* - * Read keypad status - */ - i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2); - mdelay(500); - i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2); - - /* - * Check keypad - */ - if ( !(keypad_status1[1] & KEYPAD_MASK_LO) || - (keypad_status1[1] != keypad_status2[1])) { - return 0; - } - -#endif - au_usb_stor_curr_dev = -1; - /* start USB */ - if (usb_stop() < 0) { - debug ("usb_stop failed\n"); - return -1; - } - if (usb_init() < 0) { - debug ("usb_init failed\n"); - return -1; - } - /* - * check whether a storage device is attached (assume that it's - * a USB memory stick, since nothing else should be attached). - */ - au_usb_stor_curr_dev = usb_stor_scan(0); - if (au_usb_stor_curr_dev == -1) { - debug ("No device found. Not initialized?\n"); - res = -1; - goto xit; - } - /* check whether it has a partition table */ - stor_dev = get_dev("usb", 0); - if (stor_dev == NULL) { - debug ("uknown device type\n"); - res = -1; - goto xit; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to use USB %d:%d for fatls\n", - au_usb_stor_curr_dev, 1); - res = -1; - goto xit; - } - if (file_fat_detectfs() != 0) { - debug ("file_fat_detectfs failed\n"); - } - - /* - * now check whether start and end are defined using environment - * variables. - */ - start = -1; - end = 0; - env = getenv("firmware_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("firmware_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_FIRMWARE] = (end + 1) - start; - aufl_layout[IDX_FIRMWARE].start = start; - aufl_layout[IDX_FIRMWARE].end = end; - } - start = -1; - end = 0; - env = getenv("kernel_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("kernel_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_KERNEL] = (end + 1) - start; - aufl_layout[IDX_KERNEL].start = start; - aufl_layout[IDX_KERNEL].end = end; - } - start = -1; - end = 0; - env = getenv("rootfs_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("rootfs_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_ROOTFS] = (end + 1) - start; - aufl_layout[IDX_ROOTFS].start = start; - aufl_layout[IDX_ROOTFS].end = end; - } - - /* make certain that HUSH is runnable */ - u_boot_hush_start(); - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); - - /* validate the images first */ - for (i = 0; i < AU_MAXFILES; i++) { - ulong imsize; - /* just read the header */ - sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ()); - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - ausize[i] = 0; - continue; - } - /* au_check_header_valid() updates ausize[] */ - if ((imsize = au_check_header_valid(i, sz)) < 0) { - debug ("%s header not valid\n", aufile[i]); - continue; - } - /* totsize accounts for image size and flash erase size */ - totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start)); - } - -#ifdef CONFIG_PROGRESSBAR - if (totsize) { - lcd_puts(" Update in progress\n"); - lcd_enable(); - } -#endif - - /* just loop thru all the possible files */ - for (i = 0; i < AU_MAXFILES && totsize; i++) { - if (!ausize[i]) { - continue; - } - sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]); - - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - - if (sz != ausize[i]) { - printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz); - continue; - } - - if (sz <= 0 || sz <= image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - continue; - } - if (au_check_cksum_valid(i, sz) < 0) { - debug ("%s checksum not valid\n", aufile[i]); - continue; - } - /* this is really not a good idea, but it's what the */ - /* customer wants. */ - cnt = 0; - do { - res = au_do_update(i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); - break; - } - cnt++; -#ifdef AU_TEST_ONLY - } while (res < 0 && cnt < (AU_MAXFILES + 1)); - if (cnt < (AU_MAXFILES + 1)) -#else - } while (res < 0); -#endif - } - - /* restore the old state */ - disable_ctrlc(old_ctrlc); -#ifdef CONFIG_PROGRESSBAR - if (totsize) { - if (!res) { - lcd_puts("\n Update completed\n"); - } else { - lcd_puts("\n Update error\n"); - } - lcd_enable(); - } -#endif - xit: - usb_stop(); - return res; -} -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c deleted file mode 100644 index c911445d97..0000000000 --- a/board/mcc200/lcd.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifdef CONFIG_LCD - -#undef SWAPPED_LCD /* For the previous h/w version */ -/* - * The name of the device used for communication - * with the PSoC. - */ -#define PSOC_PSC MPC5XXX_PSC2 -#define PSOC_BAUD 230400UL - -#define RTS_ASSERT 1 -#define RTS_NEGATE 0 -#define CTS_ASSERT 1 -#define CTS_NEGATE 0 - -/* - * Dimensions in pixels - */ -#define LCD_WIDTH 160 -#define LCD_HEIGHT 100 - -/* - * Dimensions in bytes - */ -#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3) - -#if LCD_BPP != LCD_MONOCHROME -#error "MCC200 support only monochrome displays (1 bpp)!" -#endif - -#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */ -#define PSOC_WAIT_TIME 10 /* usec */ - -#include -#define FONT_WIDTH VIDEO_FONT_WIDTH - -DECLARE_GLOBAL_DATA_PTR; - -/* - * LCD information - */ -vidinfo_t panel_info = { - LCD_WIDTH, LCD_HEIGHT, LCD_BPP -}; - - -/* - * The device we use to communicate with PSoC - */ -int serial_inited = 0; - -/* - * Imported functions to support the PSoC protocol - */ -extern int serial_init_dev (unsigned long dev_base); -extern void serial_setrts_dev (unsigned long dev_base, int s); -extern int serial_getcts_dev (unsigned long dev_base); -extern void serial_putc_raw_dev(unsigned long dev_base, const char c); - -/* - * Just stubs for our driver, needed for compiling compabilty with - * the common LCD driver code. - */ -void lcd_initcolregs (void) -{ -} - -void lcd_ctrl_init (void *lcdbase) -{ -} - -/* - * Function sends the contents of the frame-buffer to the LCD - */ -void lcd_enable (void) -{ - int i, retries, fb_size; - - if (!serial_inited) { - unsigned long baud; - - baud = gd->baudrate; - gd->baudrate = PSOC_BAUD; - serial_init_dev(PSOC_PSC); - gd->baudrate = baud; - serial_setrts_dev (PSOC_PSC, RTS_ASSERT); - serial_inited = 1; - } - - /* - * Implement PSoC communication protocol: - * 1. Assert RTS, wait CTS assertion - * 2. Transmit data - * 3. Negate RTS, wait CTS negation - */ - - /* 1 */ - serial_setrts_dev (PSOC_PSC, RTS_ASSERT); - for (retries = PSOC_RETRIES; retries; retries--) { - if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT) - break; - udelay (PSOC_WAIT_TIME); - } - if (!retries) { - printf ("%s Error: PSoC doesn't respond on " - "RTS ASSERT\n", __FUNCTION__); - } - - /* 2 */ - fb_size = panel_info.vl_row * (panel_info.vl_col >> 3); - -#if !defined(SWAPPED_LCD) - for (i=0; ifb_base)[i]); - } -#else - { - int x, y, pwidth; - char *p = (char *)gd->fb_base; - - pwidth = ((panel_info.vl_col+7) >> 3); - for (y=0; y>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F)); - } - } - } -#endif - - /* 3 */ - serial_setrts_dev (PSOC_PSC, RTS_NEGATE); - for (retries = PSOC_RETRIES; retries; retries--) { - if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE) - break; - udelay (PSOC_WAIT_TIME); - } - - return; -} -#ifdef CONFIG_PROGRESSBAR - -void show_progress (int size, int tot) -{ - int cnt; - int i; - static int rc = 0; - - rc += size; - - cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot; - - rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH); - - for (i = 0; i < cnt; i++) { - lcd_putc(0xdc); - } - - if (cnt) { - lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */ - } -} - -#endif - -int bmp_display(ulong addr, int x, int y) -{ - int ret; - bmp_image_t *bmp = (bmp_image_t *)addr; - - if (!bmp) { - printf("There is no valid bmp file at the given address\n"); - return 1; - } - - ret = lcd_display_bitmap((ulong)bmp, x, y); - - if ((unsigned long)bmp != addr) - free(bmp); - - return ret; -} - -#endif /* CONFIG_LCD */ diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c deleted file mode 100644 index 706886b84a..0000000000 --- a/board/mcc200/mcc200.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* Two MT48LC8M32B2 for 32 MB */ -/* #include "mt48lc8m32b2-6-7.h" */ - -/* One MT48LC16M32S2 for 64 MB */ -/* #include "mt48lc16m32s2-75.h" */ -#if defined (CONFIG_MCC200_SDRAM) -#include "mt48lc16m16a2-75.h" -#else -#include "mt46v16m16-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -extern int do_auto_update(void); -ulong flash_get_size (ulong base, int banknum); - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); - - udelay(10); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - return dramsize + dramsize2; -} - -int checkboard (void) -{ -#if defined(CONFIG_PRS200) - puts ("Board: PRS200\n"); -#else - puts ("Board: MCC200\n"); -#endif - return 0; -} - -int misc_init_r (void) -{ - ulong flash_sup_end, snum; - - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) { - /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(gd->bd->bi_flashstart); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - } - - if (gd->bd->bi_flashsize > (32 << 20)) { - /* Unprotect the upper bank of the Flash */ - *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6); - flash_protect (FLAG_PROTECT_CLEAR, - flash_info[0].start[0] + flash_info[0].size / 2, - (flash_info[0].start[0] - 1) + flash_info[0].size, - &flash_info[0]); - *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); - printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); - flash_info[0].size = 32 << 20; - for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); - flash_info[0].start[snum] < flash_sup_end; - snum++); - flash_info[0].sector_count = snum; - } - -#ifdef CONFIG_AUTO_UPDATE - do_auto_update(); -#endif - return (0); -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -} -#endif - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h deleted file mode 100644 index 9068fbf36f..0000000000 --- a/board/mcc200/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/mcc200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/mcc200/mt48lc16m32s2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h deleted file mode 100644 index 13aebbd8af..0000000000 --- a/board/mcc200/mt48lc8m32b2-6-7.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ - -#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ -#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ -#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ -#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig new file mode 100644 index 0000000000..288a1aeb70 --- /dev/null +++ b/board/micronas/vct/Kconfig @@ -0,0 +1,36 @@ +if TARGET_VCT + +config SYS_BOARD + default "vct" + +config SYS_VENDOR + default "micronas" + +config SYS_CONFIG_NAME + default "vct" + +menu "vct board options" + +choice + prompt "Board variant" + +config VCT_PLATINUM + bool "Enable VCT_PLATINUM" + +config VCT_PLATINUMAVC + bool "Enable VCT_PLATINUMAVC" + +config VCT_PREMIUM + bool "Enable VCT_PLATINUMAVC" + +endchoice + +config VCT_ONENAND + bool "Enable VCT_ONENAND" + +config VCT_SMALL_IMAGE + bool "Enable VCT_SMALL_IMAGE" + +endmenu + +endif diff --git a/board/micronas/vct/MAINTAINERS b/board/micronas/vct/MAINTAINERS new file mode 100644 index 0000000000..cbaa585134 --- /dev/null +++ b/board/micronas/vct/MAINTAINERS @@ -0,0 +1,17 @@ +VCT BOARD +#M: - +S: Maintained +F: board/micronas/vct/ +F: include/configs/vct.h +F: configs/vct_platinum_defconfig +F: configs/vct_platinum_onenand_defconfig +F: configs/vct_platinum_onenand_small_defconfig +F: configs/vct_platinum_small_defconfig +F: configs/vct_platinumavc_defconfig +F: configs/vct_platinumavc_onenand_defconfig +F: configs/vct_platinumavc_onenand_small_defconfig +F: configs/vct_platinumavc_small_defconfig +F: configs/vct_premium_defconfig +F: configs/vct_premium_onenand_defconfig +F: configs/vct_premium_onenand_small_defconfig +F: configs/vct_premium_small_defconfig diff --git a/board/micronas/vct/Makefile b/board/micronas/vct/Makefile index ff35a5a402..ed28cb81bf 100644 --- a/board/micronas/vct/Makefile +++ b/board/micronas/vct/Makefile @@ -4,32 +4,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-y += ebi.o -COBJS-$(CONFIG_VCT_NOR) += ebi_nor_flash.o -COBJS-$(CONFIG_VCT_ONENAND) += ebi_onenand.o -COBJS-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o -COBJS-y += gpio.o -COBJS-y += top.o -COBJS-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := vct.o +obj-y += ebi.o +obj-$(CONFIG_VCT_NOR) += ebi_nor_flash.o +obj-$(CONFIG_VCT_ONENAND) += ebi_onenand.o +obj-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o +obj-y += gpio.o +obj-y += top.o +obj-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk index 0f004e0ee0..354d918474 100644 --- a/board/micronas/vct/config.mk +++ b/board/micronas/vct/config.mk @@ -8,8 +8,6 @@ # vct_xxx boards with MIPS 4Kc CPU core # -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - ifndef CONFIG_SYS_TEXT_BASE CONFIG_SYS_TEXT_BASE = 0x87000000 endif diff --git a/board/mimc/mimc200/Kconfig b/board/mimc/mimc200/Kconfig new file mode 100644 index 0000000000..18736d7f96 --- /dev/null +++ b/board/mimc/mimc200/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MIMC200 + +config SYS_BOARD + default "mimc200" + +config SYS_VENDOR + default "mimc" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "mimc200" + +endif diff --git a/board/mimc/mimc200/MAINTAINERS b/board/mimc/mimc200/MAINTAINERS new file mode 100644 index 0000000000..6cb51dd3cb --- /dev/null +++ b/board/mimc/mimc200/MAINTAINERS @@ -0,0 +1,6 @@ +MIMC200 BOARD +M: Mark Jackson +S: Maintained +F: board/mimc/mimc200/ +F: include/configs/mimc200.h +F: configs/mimc200_defconfig diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile index 955a9c558b..5c30c0dbca 100644 --- a/board/mimc/mimc200/Makefile +++ b/board/mimc/mimc200/Makefile @@ -3,23 +3,4 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mimc200.o diff --git a/board/miromico/hammerhead/Kconfig b/board/miromico/hammerhead/Kconfig new file mode 100644 index 0000000000..1f09ef782e --- /dev/null +++ b/board/miromico/hammerhead/Kconfig @@ -0,0 +1,15 @@ +if TARGET_HAMMERHEAD + +config SYS_BOARD + default "hammerhead" + +config SYS_VENDOR + default "miromico" + +config SYS_SOC + default "at32ap700x" + +config SYS_CONFIG_NAME + default "hammerhead" + +endif diff --git a/board/miromico/hammerhead/MAINTAINERS b/board/miromico/hammerhead/MAINTAINERS new file mode 100644 index 0000000000..a87ceeeb73 --- /dev/null +++ b/board/miromico/hammerhead/MAINTAINERS @@ -0,0 +1,6 @@ +HAMMERHEAD BOARD +M: Alex Raimondi +S: Maintained +F: board/miromico/hammerhead/ +F: include/configs/hammerhead.h +F: configs/hammerhead_defconfig diff --git a/board/miromico/hammerhead/Makefile b/board/miromico/hammerhead/Makefile index 3a2a8eba01..638a9df930 100644 --- a/board/miromico/hammerhead/Makefile +++ b/board/miromico/hammerhead/Makefile @@ -3,23 +3,4 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := hammerhead.o diff --git a/board/mosaixtech/icon/Kconfig b/board/mosaixtech/icon/Kconfig new file mode 100644 index 0000000000..3145a061c6 --- /dev/null +++ b/board/mosaixtech/icon/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ICON + +config SYS_BOARD + default "icon" + +config SYS_VENDOR + default "mosaixtech" + +config SYS_CONFIG_NAME + default "icon" + +endif diff --git a/board/mosaixtech/icon/MAINTAINERS b/board/mosaixtech/icon/MAINTAINERS new file mode 100644 index 0000000000..f3af072243 --- /dev/null +++ b/board/mosaixtech/icon/MAINTAINERS @@ -0,0 +1,6 @@ +ICON BOARD +M: Stefan Roese +S: Maintained +F: board/mosaixtech/icon/ +F: include/configs/icon.h +F: configs/icon_defconfig diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile index 23a8631eb0..d554a8bcb9 100644 --- a/board/mosaixtech/icon/Makefile +++ b/board/mosaixtech/icon/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -SOBJS = init.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := icon.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +extra-y += init.o diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S index ad12d7c9d3..c28a3a38a1 100644 --- a/board/mosaixtech/icon/init.S +++ b/board/mosaixtech/icon/init.S @@ -2,7 +2,7 @@ * (C) Copyright 2009-2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig new file mode 100644 index 0000000000..f624f6c95f --- /dev/null +++ b/board/motionpro/Kconfig @@ -0,0 +1,9 @@ +if TARGET_MOTIONPRO + +config SYS_BOARD + default "motionpro" + +config SYS_CONFIG_NAME + default "motionpro" + +endif diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS new file mode 100644 index 0000000000..2f8b5cb580 --- /dev/null +++ b/board/motionpro/MAINTAINERS @@ -0,0 +1,6 @@ +MOTIONPRO BOARD +#M: - +S: Maintained +F: board/motionpro/ +F: include/configs/motionpro.h +F: configs/motionpro_defconfig diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile index 4a7d872afa..898a384c39 100644 --- a/board/motionpro/Makefile +++ b/board/motionpro/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := motionpro.o diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index a6235e5394..4d0ebaab74 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -185,9 +185,11 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/mousse/Makefile b/board/mousse/Makefile deleted file mode 100644 index 9566cc86b2..0000000000 --- a/board/mousse/Makefile +++ /dev/null @@ -1,28 +0,0 @@ - -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o m48t59y.o pci.o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mousse/README b/board/mousse/README deleted file mode 100644 index d5dda7a8e7..0000000000 --- a/board/mousse/README +++ /dev/null @@ -1,346 +0,0 @@ - -U-Boot for MOUSSE/MPC8240 (KAHLUA) ----------------------------------- -James Dougherty (jfd@broadcom.com), 09/10/01 - -The Broadcom/Vooha Mousse board is a 3U Compact PCI system board -which uses the MPC8240, a 64MB SDRAM SIMM, and has onboard -DEC 21143, NS16550 UART, an SGS M48T59Y TOD, and 4MB FLASH. -See also: http://www.vooha.com/ - -* NVRAM setenv/printenv/savenv supported. -* Date Command -* Serial Console support -* Network support -* FLASH of kernel images is supported. -* FLASH of U-Boot to onboard and PLCC boot region. -* Kernel command line options from NVRAM is supported. -* IP PNP options supported. - -U-Boot Loading... - - -U-Boot 1.0.5 (Sep 10 2001 - 00:22:25) - -CPU: MPC8240 Revision 1.1 at 198 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B) -Built: Sep 10 2001 at 01:01:50 -MPLD: Revision 127 -Local Bus: 33 MHz -RTC: M48T589 TOD/NVRAM (8176) bytes - Current date/time: 9/10/2001 0:18:52 -DRAM: 64 MB -FLASH: 1.960 MB -PCI: scanning bus0 ... - bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE - 00 00 00 1057 0003 060000 11 00000008 00000000 01 00 - 00 0d 00 1011 0019 020000 41 80000001 80000000 01 01 - 00 0e 00 105a 4d38 018000 01 a0000001 a0001001 01 03 -In: serial -Out: serial -Err: serial - -Hit any key to stop autoboot: 0 -=> - -I. Root FileSystem/IP Configuration - -bootcmd=tftp 100000 vmlinux.img;bootm -bootdelay=3 -baudrate=9600 -ipaddr= -netmask= -hostname= -serverip= -ethaddr=00:00:10:20:30:44 -nfsroot=:/boot/root-fs -gateway= -root=/dev/nfs -stdin=serial -stdout=serial -stderr=serial - -NVRAM environment variables. - -use the command: - -setenv - -type "saveenv" to write to NVRAM. - - -II. To boot from a hard drive: - -setenv root /dev/hda1 - - -III. IP options which configure the network: - -ipaddr= -netmask= -hostname=mousse -ethaddr=00:00:10:20:30:44 -gateway= - - -IV. IP Options which configure NFS Root/Boot Support - -root=/dev/nfs -serverip= -nfsroot=:/boot/root-fs - -V. U-Boot Image Support - -The U-Boot boot loader assumes that after you build -your kernel (vmlinux), you will create a U-Boot image -using the following commands or script: - -#!/bin/csh -/bin/touch vmlinux.img -/bin/rm vmlinux.img -set path=($TOOLBASE/bin $path) -set path=($U_BOOT/tools $path) -powerpc-linux-objcopy -S -O binary vmlinux vmlinux.bin -gzip -vf vmlinux.bin -mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 -n vmlinux.bin.gz -d vmlinux.bin.gz vmlinux.img -ls -l vmlinux.img - - -VI. ONBOARD FLASH Support - -FLASH support is provided for the onboard FLASH chip Bootrom area. -U-Boot is loaded into either the ROM boot region of the FLASH chip, -after first being boot-strapped from a pre-progammed AMD29F040 PLCC -bootrom. The PLCC needs to be programmed with a ROM burner using -AMD 29F040 ROM parts and the u-boot.bin or u-boot.hex (S-Record) -images. - -The PLCC overlays this same region of flash as the onboard FLASH, -the jumper J100 is a chip-select for which flash chip you want to -progam. When jumper J100 is connected to pins 2-3, you boot from -PLCC FLASH. - -To bringup a system, simply flash a flash an AMD29F040 PLCC -bootrom, and put this in the PLCC socket. Move jumper J100 to -pins 2-3 and boot from the PLCC. - - -Now, while the system is running, move Jumper J100 to -pins 1-2 and follow the procedure below to FLASH a bootrom -(u-boot.bin) image into the onboard bootrom region (AMD29LV160DB): - -tftp 100000 u-boot.bin -protect off FFF00000 FFF7FFFF -erase FFF00000 FFF7FFFF -cp.b 100000 FFF00000 \${filesize}\ - - -Here is an example: - -=>tftp 100000 u-boot.bin -eth_halt -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 123220 (1e154 hex) -eth_halt -=>protect off FFF00000 FFF7FFFF -Un-Protected 8 sectors -=>erase FFF00000 FFF7FFFF -Erase Flash from 0xfff00000 to 0xfff7ffff -Erase FLASH[PLCC_BOOT] -8 sectors:........ done -Erased 8 sectors -=>cp.b 100000 FFF00000 1e154 -Copy to Flash... FLASH[PLCC_BOOT]:..done -=> - - -B. FLASH RAMDISK REGION - -FLASH support is provided for an Onboard 512K RAMDISK region. - -TThe following commands will FLASH a bootrom (u-boot.bin) image -into the onboard FLASH region (AMD29LV160DB 2MB FLASH): - -tftp 100000 u-boot.bin -protect off FFF80000 FFFFFFFF -erase FFF80000 FFFFFFFF -cp.b 100000 FFF80000 \${filesize}\ - - -C. FLASH KERNEL REGION (960KB) - -FLASH support is provided for the 960KB onboard FLASH1 segment. -This allows flashing of kernel images which U-Boot can load -and run (standalone) from the onboard FLASH chip. It also assumes - -The following commands will FLASH a kernel image to 0xffe10000 - -tftp 100000 vmlinux.img -protect off FFE10000 FFEFFFFF -erase FFE10000 FFEFFFFF -cp.b 100000 FFE10000 \${filesize}\ -reset - -Here is an example: - - -=>tftp 100000 vmlinux.img -eth_halt -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -TFTP from server 209.128.93.133; our IP address is 209.128.93.138 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: ##################################################################################################################################################### -done -Bytes transferred = 760231 (b99a7 hex) -eth_halt -=>protect off FFE10000 FFEFFFFF -Un-Protected 15 sectors -=>erase FFE10000 FFEFFFFF -Erase Flash from 0xffe10000 to 0xffefffff -Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done -Erased 15 sectors -=>cp.b 100000 FFE10000 b99a7 -Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done -=> - - -When finished, use the command: - -bootm ffe10000 - -to start the kernel. - -Finally, to make this the default boot command, use -the following commands: - -setenv bootcmd bootm ffe10000 -savenv - -to make it automatically boot the kernel from FLASH. - - -To go back to development mode (NFS boot) - -setenv bootcmd tftp 100000 vmlinux.img\;bootm -savenv - - -=>tftp 100000 vmlinux.img -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: #################################################################################################################################################### -done -Bytes transferred = 752717 (b7c4d hex) -eth_halt -=>protect off FFE10000 FFEFFFFF -Un-Protected 15 sectors -=>erase FFE10000 FFEFFFFF -Erase Flash from 0xffe10000 to 0xffefffff -Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done -Erased 15 sectors -=>cp.b 100000 FFE10000 b7c4d -Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done -=>bootm ffe10000 -## Booting image at ffe10000 ... - Image Name: vmlinux.bin.gz - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 752653 Bytes = 735 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Total memory = 64MB; using 0kB for hash table (at 00000000) -Linux version 2.4.2_hhl20 (jfd@atlantis) (gcc version 2.95.2 19991024 (release)) #597 Wed Sep 5 23:23:23 PDT 2001 -cpu0: MPC8240/KAHLUA : MOUSSE Platform : 64MB RAM: MPLD Rev. 7f -Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com) -IP PNP: 802.3 Ethernet Address=<0:0:10:20:30:44> -NOTICE: mounting root file system via NFS -On node 0 totalpages: 16384 -zone(0): 16384 pages. -zone(1): 0 pages. -zone(2): 0 pages. -time_init: decrementer frequency = 16.665914 MHz -time_init: MPC8240 PCI Bus frequency = 33.331828 MHz -Calibrating delay loop... 133.12 BogoMIPS -Memory: 62436k available (1336k kernel code, 500k data, 88k init, 0k highmem) -Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes) -Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) -Page-cache hash table entries: 16384 (order: 4, 65536 bytes) -Inode-cache hash table entries: 4096 (order: 3, 32768 bytes) -POSIX conformance testing by UNIFIX -PCI: Probing PCI hardware -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Initializing RT netlink socket -Starting kswapd v1.8 -pty: 256 Unix98 ptys configured -block: queued sectors max/low 41394kB/13798kB, 128 slots per queue -Uniform Multi-Platform E-IDE driver Revision: 6.31 -ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -PDC20262: IDE controller on PCI bus 00 dev 70 -PDC20262: chipset revision 1 -PDC20262: not 100% native mode: will probe irqs later -PDC20262: ROM enabled at 0x000d0000 -PDC20262: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode. -PDC20262: FORCING BURST BIT 0x00 -> 0x01 ACTIVE -PDC20262: irq=3 dev->irq=3 - ide0: BM-DMA at 0xbfff00-0xbfff07, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0xbfff08-0xbfff0f, BIOS settings: hdc:pio, hdd:pio -hda: WDC WD300AB-00BVA0, ATA DISK drive -hdc: SONY CD-RW CRX160E, ATAPI CD/DVD-ROM drive -ide0 at 0xbfff78-0xbfff7f,0xbfff76 on irq 3 -ide1 at 0xbfff68-0xbfff6f,0xbfff66 on irq 3 -hda: 58633344 sectors (30020 MB) w/2048KiB Cache, CHS=58168/16/63, UDMA(66) -hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache -Uniform CD-ROM driver Revision: 3.12 -Partition check: - /dev/ide/host0/bus0/target0/lun0: p1 p2 -hd: unable to get major 3 for hard disk -udf: registering filesystem -loop: loaded (max 8 devices) -Serial driver version 5.02 (2000-08-09) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled -ttyS00 at 0xffe08080 (irq = 4) is a ST16650 -Linux Tulip driver version 0.9.13a (January 20, 2001) -eth0: Digital DS21143 Tulip rev 65 at 0xbfff80, EEPROM not present, 00:00:10:20:30:44, IRQ 1. -eth0: MII transceiver #0 config 3000 status 7829 advertising 01e1. -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 4096 bind 4096) -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -devfs: v0.102 (20000622) Richard Gooch (rgooch@atnf.csiro.au) -devfs: boot_options: 0x0 -VFS: Mounted root (nfs filesystem). -Mounted devfs on /dev -Freeing unused kernel memory: 88k init 4k openfirmware -eth0: Setting full-duplex based on MII#0 link partner capability of 45e1. -INIT: version 2.78 booting -INIT: Entering runlevel: 2 - - -Welcome to Linux/PPC -MPC8240/MOUSSE - - -mousse login: root -Password: -PAM_unix[13]: (login) session opened for user root by LOGIN(uid=0) -Last login: Thu Sep 6 00:16:51 2001 on console - - -Welcome to Linux/PPC -MPC8240/MOUSSE - - -mousse# diff --git a/board/mousse/flash.c b/board/mousse/flash.c deleted file mode 100644 index acedcb1aa1..0000000000 --- a/board/mousse/flash.c +++ /dev/null @@ -1,917 +0,0 @@ -/* - * MOUSSE/MPC8240 Board definitions. - * Flash Routines for MOUSSE onboard AMD29LV106DB devices - * - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "mousse.h" -#include "flash.h" - -int flashLibDebug = 0; -int flashLibInited = 0; - -#define OK 0 -#define ERROR -1 -#define STATUS int -#define PRINTF if (flashLibDebug) printf -#if 0 -#define PRIVATE static -#else -#define PRIVATE -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define SLEEP_DELAY 166 -#define FLASH_SECTOR_SIZE (64*1024) -/*********************************************************************** - * - * Virtual Flash Devices on Mousse board - * - * These must be kept in sync with the definitions in flashLib.h. - * - ***********************************************************************/ - -PRIVATE flash_dev_t flashDev[] = { - /* Bank 0 sector SA0 (16 kB) */ - { "SA0",FLASH0_BANK, FLASH0_SEG0_START, 1, 14, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA1 (8 kB) */ - { "SA1", FLASH0_BANK, FLASH0_SEG0_START + 0x4000, 1, 13, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA2 (8 kB) */ - { "SA2", FLASH0_BANK, FLASH0_SEG0_START + 0x6000, 1, 13, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA3 is occluded by Mousse I/O devices */ - /* Bank 0 sectors SA4-SA18, after Mousse devices up to PLCC (960 kB) */ - { "KERNEL", FLASH0_BANK, FLASH0_SEG1_START, 15, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sectors SA19-SA26, jumper can occlude this by PLCC (512 kB) */ - /* This is where the Kahlua boot vector and boot ROM code resides. */ - { "BOOT",FLASH0_BANK, FLASH0_SEG2_START, 8, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sectors SA27-SA34 (512 kB) */ - { "RAMDISK",FLASH0_BANK, FLASH0_SEG3_START, 8, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, -}; - -int flashDevCount = (sizeof (flashDev) / sizeof (flashDev[0])); - -#define DEV(no) (&flashDev[no]) -#define DEV_NO(dev) ((dev) - flashDev) - -/*********************************************************************** - * - * Private Flash Routines - * - ***********************************************************************/ - -/* - * The convention is: - * - * "addr" is always the PROM raw address, which is the address of an - * 8-bit quantity for flash 0 and 16-bit quantity for flash 1. - * - * "pos" is always a logical byte position from the PROM beginning. - */ - -#define FLASH0_ADDR(dev, addr) \ - ((unsigned char *) ((dev)->base + (addr))) - -#define FLASH0_WRITE(dev, addr, value) \ - (*FLASH0_ADDR(dev, addr) = (value)) - -#define FLASH0_READ(dev, addr) \ - (*FLASH0_ADDR(dev, addr)) - -PRIVATE int flashCheck (flash_dev_t * dev) -{ - if (!flashLibInited) { - printf ("flashCheck: flashLib not initialized\n"); - return ERROR; - } - - if (dev < &flashDev[0] || dev >= &flashDev[flashDevCount]) { - printf ("flashCheck: Bad dev parameter\n"); - return ERROR; - } - - if (!dev->found) { - printf ("flashCheck: Device %d not available\n", DEV_NO (dev)); - return ERROR; - } - - return OK; -} - -PRIVATE void flashReset (flash_dev_t * dev) -{ - PRINTF ("flashReset: dev=%d\n", DEV_NO (dev)); - - if (dev->bank == FLASH0_BANK) { - FLASH0_WRITE (dev, 0x555, 0xaa); - FLASH0_WRITE (dev, 0xaaa, 0x55); - FLASH0_WRITE (dev, 0x555, 0xf0); - } - - udelay (SLEEP_DELAY); - - PRINTF ("flashReset: done\n"); -} - -PRIVATE int flashProbe (flash_dev_t * dev) -{ - int rv, deviceID, vendorID; - - PRINTF ("flashProbe: dev=%d\n", DEV_NO (dev)); - - if (dev->bank != FLASH0_BANK) { - rv = ERROR; - goto DONE; - } - - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0x90); - - udelay (SLEEP_DELAY); - - vendorID = FLASH0_READ (dev, 0); - deviceID = FLASH0_READ (dev, 2); - - FLASH0_WRITE (dev, 0, 0xf0); - - PRINTF ("flashProbe: vendor=0x%x device=0x%x\n", vendorID, deviceID); - - if (vendorID == dev->vendorID && deviceID == dev->deviceID) - rv = OK; - else - rv = ERROR; - - DONE: - PRINTF ("flashProbe: rv=%d\n", rv); - - return rv; -} - -PRIVATE int flashWait (flash_dev_t * dev, int addr, int expect, int erase) -{ - int rv = ERROR; - int i, data; - int polls; - -#if 0 - PRINTF ("flashWait: dev=%d addr=0x%x expect=0x%x erase=%d\n", - DEV_NO (dev), addr, expect, erase); -#endif - - if (dev->bank != FLASH0_BANK) { - rv = ERROR; - goto done; - } - - if (erase) - polls = FLASH_ERASE_SECTOR_TIMEOUT; /* Ticks */ - else - polls = FLASH_PROGRAM_POLLS; /* Loops */ - - for (i = 0; i < polls; i++) { - if (erase) - udelay (SLEEP_DELAY); - - data = FLASH0_READ (dev, addr); - - if (((data ^ expect) & 0x80) == 0) { - rv = OK; - goto done; - } - - if (data & 0x20) { - /* - * If the 0x20 bit has come on, it could actually be because - * the operation succeeded, so check the done bit again. - */ - - data = FLASH0_READ (dev, addr); - - if (((data ^ expect) & 0x80) == 0) { - rv = OK; - goto done; - } - - printf ("flashWait: Program error (dev: %d, addr: 0x%x)\n", - DEV_NO (dev), addr); - - flashReset (dev); - rv = ERROR; - goto done; - } - } - - printf ("flashWait: Timeout %s (dev: %d, addr: 0x%x)\n", - erase ? "erasing sector" : "programming byte", - DEV_NO (dev), addr); - - done: - -#if 0 - PRINTF ("flashWait: rv=%d\n", rv); -#endif - - return rv; -} - -/*********************************************************************** - * - * Public Flash Routines - * - ***********************************************************************/ - -STATUS flashLibInit (void) -{ - int i; - - PRINTF ("flashLibInit: devices=%d\n", flashDevCount); - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - /* - * For bank 1, probe both without and with byte swappage, - * so that this module works on both old and new Mousse boards. - */ - - flashReset (dev); - - if (flashProbe (dev) != ERROR) - dev->found = 1; - - flashReset (dev); - - if (flashProbe (dev) != ERROR) - dev->found = 1; - - dev->swap = 0; - - if (dev->found) { - PRINTF ("\n FLASH %s[%d]: iobase=0x%x - %d sectors %d KB", - flashDev[i].name, i, flashDev[i].base, - flashDev[i].sectors, - (flashDev[i].sectors * FLASH_SECTOR_SIZE) / 1024); - - } - } - - flashLibInited = 1; - - PRINTF ("flashLibInit: done\n"); - - return OK; -} - -STATUS flashEraseSector (flash_dev_t * dev, int sector) -{ - int pos, addr; - - PRINTF ("flashErasesector: dev=%d sector=%d\n", DEV_NO (dev), sector); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (sector < 0 || sector >= dev->sectors) { - printf ("flashEraseSector: Sector out of range (dev: %d, sector: %d)\n", DEV_NO (dev), sector); - return ERROR; - } - - pos = FLASH_SECTOR_POS (dev, sector); - - if (dev->bank != FLASH0_BANK) { - return ERROR; - } - - addr = pos; - - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0x80); - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, addr, 0x30); - - return flashWait (dev, addr, 0xff, 1); -} - -/* - * Note: it takes about as long to flash all sectors together with Chip - * Erase as it does to flash them one at a time (about 30 seconds for 2 - * MB). Also since we want to be able to treat subsets of sectors as if - * they were complete devices, we don't use Chip Erase. - */ - -STATUS flashErase (flash_dev_t * dev) -{ - int sector; - - PRINTF ("flashErase: dev=%d sectors=%d\n", DEV_NO (dev), dev->sectors); - - if (flashCheck (dev) == ERROR) - return ERROR; - - for (sector = 0; sector < dev->sectors; sector++) { - if (flashEraseSector (dev, sector) == ERROR) - return ERROR; - } - return OK; -} - -/* - * Read and write bytes - */ - -STATUS flashRead (flash_dev_t * dev, int pos, char *buf, int len) -{ - int addr, words; - - PRINTF ("flashRead: dev=%d pos=0x%x buf=0x%x len=0x%x\n", - DEV_NO (dev), pos, (int) buf, len); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashRead: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - return ERROR; - } - - if (len == 0) - return OK; - - if (dev->bank == FLASH0_BANK) { - addr = pos; - words = len; - - PRINTF ("flashRead: memcpy(0x%x, 0x%x, 0x%x)\n", - (int) buf, (int) FLASH0_ADDR (dev, pos), len); - - memcpy (buf, FLASH0_ADDR (dev, addr), words); - - } - PRINTF ("flashRead: rv=OK\n"); - - return OK; -} - -STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len) -{ - int addr, words; - - PRINTF ("flashWrite: dev=%d pos=0x%x buf=0x%x len=0x%x\n", - DEV_NO (dev), pos, (int) buf, len); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashWrite: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - return ERROR; - } - - if (len == 0) - return OK; - - if (dev->bank == FLASH0_BANK) { - unsigned char tmp; - - addr = pos; - words = len; - - while (words--) { - tmp = *buf; - if (~FLASH0_READ (dev, addr) & tmp) { - printf ("flashWrite: Attempt to program 0 to 1 " - "(dev: %d, addr: 0x%x, data: 0x%x)\n", - DEV_NO (dev), addr, tmp); - return ERROR; - } - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0xa0); - FLASH0_WRITE (dev, addr, tmp); - if (flashWait (dev, addr, tmp, 0) < 0) - return ERROR; - buf++; - addr++; - } - } - - PRINTF ("flashWrite: rv=OK\n"); - - return OK; -} - -/* - * flashWritable returns true if a range contains all F's. - */ - -STATUS flashWritable (flash_dev_t * dev, int pos, int len) -{ - int addr, words; - int rv = ERROR; - - PRINTF ("flashWritable: dev=%d pos=0x%x len=0x%x\n", - DEV_NO (dev), pos, len); - - if (flashCheck (dev) == ERROR) - goto done; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashWritable: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - goto done; - } - - if (len == 0) { - rv = 1; - goto done; - } - - if (dev->bank == FLASH0_BANK) { - addr = pos; - words = len; - - while (words--) { - if (FLASH0_READ (dev, addr) != 0xff) { - rv = 0; - goto done; - } - addr++; - } - } - - rv = 1; - - done: - PRINTF ("flashWrite: rv=%d\n", rv); - return rv; -} - - -/* - * NOTE: the below code cannot run from FLASH!!! - */ -/*********************************************************************** - * - * Flash Diagnostics - * - ***********************************************************************/ - -STATUS flashDiag (flash_dev_t * dev) -{ - unsigned int *buf = 0; - int i, len, sector; - int rv = ERROR; - - if (flashCheck (dev) == ERROR) - return ERROR; - - printf ("flashDiag: Testing device %d, " - "base: 0x%x, %d sectors @ %d kB = %d kB\n", - DEV_NO (dev), dev->base, - dev->sectors, - 1 << (dev->lgSectorSize - 10), - dev->sectors << (dev->lgSectorSize - 10)); - - len = 1 << dev->lgSectorSize; - - printf ("flashDiag: Erasing\n"); - - if (flashErase (dev) == ERROR) { - printf ("flashDiag: Erase failed\n"); - goto done; - } - printf ("%d bytes requested ...\n", len); - buf = malloc (len); - printf ("allocated %d bytes ...\n", len); - if (buf == 0) { - printf ("flashDiag: Out of memory\n"); - goto done; - } - - /* - * Write unique counting pattern to each sector - */ - - for (sector = 0; sector < dev->sectors; sector++) { - printf ("flashDiag: Write sector %d\n", sector); - - for (i = 0; i < len / 4; i++) - buf[i] = sector << 24 | i; - - if (flashWrite (dev, - sector << dev->lgSectorSize, - (char *) buf, len) == ERROR) { - printf ("flashDiag: Write failed (dev: %d, sector: %d)\n", - DEV_NO (dev), sector); - goto done; - } - } - - /* - * Verify - */ - - for (sector = 0; sector < dev->sectors; sector++) { - printf ("flashDiag: Verify sector %d\n", sector); - - if (flashRead (dev, - sector << dev->lgSectorSize, - (char *) buf, len) == ERROR) { - printf ("flashDiag: Read failed (dev: %d, sector: %d)\n", - DEV_NO (dev), sector); - goto done; - } - - for (i = 0; i < len / 4; i++) { - if (buf[i] != (sector << 24 | i)) { - printf ("flashDiag: Verify error " - "(dev: %d, sector: %d, offset: 0x%x)\n", - DEV_NO (dev), sector, i); - printf ("flashDiag: Expected 0x%08x, got 0x%08x\n", - sector << 24 | i, buf[i]); - - goto done; - } - } - } - - printf ("flashDiag: Erasing\n"); - - if (flashErase (dev) == ERROR) { - printf ("flashDiag: Final erase failed\n"); - goto done; - } - - rv = OK; - - done: - if (buf) - free (buf); - - if (rv == OK) - printf ("flashDiag: Device %d passed\n", DEV_NO (dev)); - else - printf ("flashDiag: Device %d failed\n", DEV_NO (dev)); - - return rv; -} - -STATUS flashDiagAll (void) -{ - int i; - int rv = OK; - - PRINTF ("flashDiagAll: devices=%d\n", flashDevCount); - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found && flashDiag (dev) == ERROR) - rv = ERROR; - } - - if (rv == OK) - printf ("flashDiagAll: Passed\n"); - else - printf ("flashDiagAll: Failed because of earlier errors\n"); - - return OK; -} - - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - flash_dev_t *dev = NULL; - - flashLibInit (); - - /* - * Provide info for FLASH (up to 960K) of Kernel Image data. - */ - dev = FLASH_DEV_BANK0_LOW; - flash_info[FLASH_BANK_KERNEL].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_KERNEL].sector_count = dev->sectors; - flash_info[FLASH_BANK_KERNEL].size = - flash_info[FLASH_BANK_KERNEL].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_KERNEL].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_KERNEL].size; - - /* - * Provide info for 512K PLCC FLASH ROM (U-Boot) - */ - dev = FLASH_DEV_BANK0_BOOT; - flash_info[FLASH_BANK_BOOT].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_BOOT].sector_count = dev->sectors; - flash_info[FLASH_BANK_BOOT].size = - flash_info[FLASH_BANK_BOOT].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_BOOT].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_BOOT].size; - - - /* - * Provide info for 512K FLASH0 segment (U-Boot) - */ - dev = FLASH_DEV_BANK0_HIGH; - flash_info[FLASH_BANK_AUX].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_AUX].sector_count = dev->sectors; - flash_info[FLASH_BANK_AUX].size = - flash_info[FLASH_BANK_AUX].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_AUX].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_AUX].size; - - - return size; -} - -/* - * Get flash device from U-Boot flash info. - */ -flash_dev_t *getFlashDevFromInfo (flash_info_t * info) -{ - int i; - - if (!info) - return NULL; - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found && (dev->base == info->start[0])) - return dev; - } - printf ("ERROR: notice, no FLASH mapped at address 0x%x\n", - (unsigned int) info->start[0]); - return NULL; -} - -ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - int i; - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found) { - if (dev->base == (unsigned int) addr) { - info->flash_id = (dev->vendorID << 16) | dev->deviceID; - info->sector_count = dev->sectors; - info->size = info->sector_count * FLASH_SECTOR_SIZE; - return dev->sectors * FLASH_SECTOR_SIZE; - } - } - } - return 0; -} - -void flash_print_info (flash_info_t * info) -{ - int i; - unsigned int chip; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - chip = (unsigned int) info->flash_id & 0x000000ff; - - switch (chip) { - - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - - case AMD_ID_LV160B: - case FLASH_AM160LV: - case 0x49: - printf ("AM29LV160B (16 Mbit / 2M x 8bit)\n"); - break; - - default: - printf ("Unknown Chip Type:0x%x\n", chip); - break; - } - - printf (" Size: %ld bytes in %d Sectors\n", - info->size, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[FIRST_SECTOR] + i * FLASH_SECTOR_SIZE, - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - - -/* - * Erase a range of flash sectors. - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - flash_dev_t *dev = NULL; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - dev = getFlashDevFromInfo (info); - if (dev) { - printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors); - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - printf ("."); - if (ERROR == flashEraseSector (dev, sect)) { - printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name); - return 1; - } - } - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - - flash_dev_t *dev = getFlashDevFromInfo (info); - int addr = dest - info->start[0]; - - if (!dev) - return 1; - - if (OK != flashWrite (dev, addr, (char *) &data, sizeof (ulong))) { - printf ("ERROR: could not write to addr=0x%x, data=0x%x\n", - (unsigned int) addr, (unsigned) data); - return 1; - } - - if ((addr % FLASH_SECTOR_SIZE) == 0) - printf ("."); - - - PRINTF ("write_word:0x%x, base=0x%x, addr=0x%x, data=0x%x\n", - (unsigned) info->start[0], - (unsigned) dest, - (unsigned) (dest - info->start[0]), (unsigned) data); - - return (0); -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - flash_dev_t *dev = getFlashDevFromInfo (info); - - if (dev) { - printf ("FLASH[%s]:", dev->name); - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); - } - return 1; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mousse/flash.h b/board/mousse/flash.h deleted file mode 100644 index b7e4619c01..0000000000 --- a/board/mousse/flash.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef FLASH_LIB_H -#define FLASH_LIB_H - -#include - -/* PIO operations max */ -#define FLASH_PROGRAM_POLLS 100000 - -/* 10 Seconds default */ -#define FLASH_ERASE_SECTOR_TIMEOUT (10*1000 /*SEC*/ ) - -/* Flash device info structure */ -typedef struct flash_dev_s { - char name[24]; /* Bank Name */ - int bank; /* Bank 0 or 1 */ - unsigned int base; /* Base address */ - int sectors; /* Sector count */ - int lgSectorSize; /* Log2(usable bytes/sector) */ - int vendorID; /* Expected vendor ID */ - int deviceID; /* Expected device ID */ - int found; /* Set if found by flashLibInit */ - int swap; /* Set for bank 1 if byte swap req'd */ -} flash_dev_t; - -#define FLASH_MAX_POS(dev) \ - ((dev)->sectors << (dev)->lgSectorSize) - -#define FLASH_SECTOR_POS(dev, sector) \ - ((sector) << (dev)->lgSectorSize) - -/* AMD 29F040 */ -#define FLASH0_BANK 0 -#define FLASH0_VENDOR_ID 0x01 -#define FLASH0_DEVICE_ID 0x49 - -/* AMD29LV160DB */ -#define FLASH1_BANK 1 -#define FLASH1_VENDOR_ID 0x0001 -#define FLASH1_DEVICE_ID 0x2249 - -extern flash_dev_t flashDev[]; -extern int flashDevCount; - -/* - * Device pointers - * - * These must be kept in sync with the table in flashLib.c. - */ -#define FLASH_DEV_BANK0_SA0 (&flashDev[0]) -#define FLASH_DEV_BANK0_SA1 (&flashDev[1]) -#define FLASH_DEV_BANK0_SA2 (&flashDev[2]) -#define FLASH_DEV_BANK0_LOW (&flashDev[3]) /* 960K */ -#define FLASH_DEV_BANK0_BOOT (&flashDev[4]) /* PLCC */ -#define FLASH_DEV_BANK0_HIGH (&flashDev[5]) /* 512K PLCC shadow */ - -unsigned long flash_init(void); -int flashEraseSector(flash_dev_t *dev, int sector); -int flashErase(flash_dev_t *dev); -int flashRead(flash_dev_t *dev, int pos, char *buf, int len); -int flashWrite(flash_dev_t *dev, int pos, char *buf, int len); -int flashWritable(flash_dev_t *dev, int pos, int len); -int flashDiag(flash_dev_t *dev); -int flashDiagAll(void); - -ulong flash_get_size (vu_long *addr, flash_info_t *info); -void flash_print_info (flash_info_t *info); -int flash_erase (flash_info_t *info, int s_first, int s_last); -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); - -/* - * Flash info indices. - */ -#define FLASH_BANK_KERNEL 0 -#define FLASH_BANK_BOOT 1 -#define FLASH_BANK_AUX 2 -#define FIRST_SECTOR 0 - -#endif /* !FLASH_LIB_H */ diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c deleted file mode 100644 index 9a70dbeab1..0000000000 --- a/board/mousse/m48t59y.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and - * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) - * registers which are used to set/get the internal date/time functions. - * - * This module implements Y2K compliance by taking full year numbers - * and translating back and forth from the TOD 2-digit year. - * - * NOTE: for proper interaction with an operating system, the TOD should - * be used to store Universal Coordinated Time (GMT) and timezone - * conversions should be used. - * - * Here is a diagram of the memory layout: - * - * +---------------------------------------------+ 0xffe0a000 - * | Non-volatile memory | . - * | | . - * | (8176 bytes of Non-volatile memory) | . - * | | . - * +---------------------------------------------+ 0xffe0bff0 - * | Flags | - * +---------------------------------------------+ 0xffe0bff1 - * | Unused | - * +---------------------------------------------+ 0xffe0bff2 - * | Alarm Seconds | - * +---------------------------------------------+ 0xffe0bff3 - * | Alarm Minutes | - * +---------------------------------------------+ 0xffe0bff4 - * | Alarm Date | - * +---------------------------------------------+ 0xffe0bff5 - * | Interrupts | - * +---------------------------------------------+ 0xffe0bff6 - * | WatchDog | - * +---------------------------------------------+ 0xffe0bff7 - * | Calibration | - * +---------------------------------------------+ 0xffe0bff8 - * | Seconds | - * +---------------------------------------------+ 0xffe0bff9 - * | Minutes | - * +---------------------------------------------+ 0xffe0bffa - * | Hours | - * +---------------------------------------------+ 0xffe0bffb - * | Day | - * +---------------------------------------------+ 0xffe0bffc - * | Date | - * +---------------------------------------------+ 0xffe0bffd - * | Month | - * +---------------------------------------------+ 0xffe0bffe - * | Year (2 digits only) | - * +---------------------------------------------+ 0xffe0bfff - */ -#include -#include -#include "mousse.h" - -/* - * Imported from mousse.h: - * - * TOD_REG_BASE Base of m48t59y TOD registers - * SYS_TOD_UNPROTECT() Disable NVRAM write protect - * SYS_TOD_PROTECT() Re-enable NVRAM write protect - */ - -#define YEAR 0xf -#define MONTH 0xe -#define DAY 0xd -#define DAY_OF_WEEK 0xc -#define HOUR 0xb -#define MINUTE 0xa -#define SECOND 0x9 -#define CONTROL 0x8 -#define WATCH 0x7 -#define INTCTL 0x6 -#define WD_DATE 0x5 -#define WD_HOUR 0x4 -#define WD_MIN 0x3 -#define WD_SEC 0x2 -#define _UNUSED 0x1 -#define FLAGS 0x0 - -#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) - -int m48_tod_init(void) -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] = 0; - M48_ADDR[WATCH] = 0; - M48_ADDR[INTCTL] = 0; - - /* - * If the oscillator is currently stopped (as on a new part shipped - * from the factory), start it running. - * - * Here is an example of the TOD bytes on a brand new M48T59Y part: - * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 - */ - - if (M48_ADDR[SECOND] & 0x80) - M48_ADDR[SECOND] = 0; - - /* Is battery low */ - if ( M48_ADDR[FLAGS] & 0x10) { - printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); - } - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * m48_tod_set - */ - -static int to_bcd(int value) -{ - return value / 10 * 16 + value % 10; -} - -static int from_bcd(int value) -{ - return value / 16 * 10 + value % 16; -} - -static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ -{ - static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; - y -= m < 3; - return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_set(int year, /* 1980-2079 */ - int month, /* 01-12 */ - int day, /* 01-31 */ - int hour, /* 00-23 */ - int minute, /* 00-59 */ - int second) /* 00-59 */ - -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ - - M48_ADDR[YEAR] = to_bcd(year % 100); - M48_ADDR[MONTH] = to_bcd(month); - M48_ADDR[DAY] = to_bcd(day); - M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; - M48_ADDR[HOUR] = to_bcd(hour); - M48_ADDR[MINUTE] = to_bcd(minute); - M48_ADDR[SECOND] = to_bcd(second); - - M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_get(int *year, /* 1980-2079 */ - int *month, /* 01-12 */ - int *day, /* 01-31 */ - int *hour, /* 00-23 */ - int *minute, /* 00-59 */ - int *second) /* 00-59 */ -{ - int y; - - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ - - y = from_bcd(M48_ADDR[YEAR]); - *year = y < 80 ? 2000 + y : 1900 + y; - *month = from_bcd(M48_ADDR[MONTH]); - *day = from_bcd(M48_ADDR[DAY]); - /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ - *hour = from_bcd(M48_ADDR[HOUR]); - *minute = from_bcd(M48_ADDR[MINUTE]); - *second = from_bcd(M48_ADDR[SECOND] & 0x7f); - - M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -int m48_tod_get_second(void) -{ - return from_bcd(M48_ADDR[SECOND] & 0x7f); -} - -/* - * Watchdog function - * - * If usec is 0, the watchdog timer is disarmed. - * - * If usec is non-zero, the watchdog timer is armed (or re-armed) for - * approximately usec microseconds (if the exact requested usec is - * not supported by the chip, the next higher available value is used). - * - * Minimum watchdog timeout = 62500 usec - * Maximum watchdog timeout = 124 sec (124000000 usec) - */ - -void m48_watchdog_arm(int usec) -{ - int mpy, res; - - SYS_TOD_UNPROTECT(); - - if (usec == 0) { - res = 0; - mpy = 0; - } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ - res = 0; - mpy = (usec + 62499) / 62500; - } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ - res = 1; - mpy = (usec + 249999) / 250000; - } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ - res = 2; - mpy = (usec + 999999) / 1000000; - } else { /* Resolution: 4s up to 124s */ - res = 3; - mpy = (usec + 3999999) / 4000000; - if (mpy > 31) - mpy = 31; - } - - M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ - mpy << 2 | - res); - - SYS_TOD_PROTECT(); -} - -/* - * U-Boot RTC support. - */ -int -rtc_get( struct rtc_time *tmp ) -{ - m48_tod_get(&tmp->tm_year, - &tmp->tm_mon, - &tmp->tm_mday, - &tmp->tm_hour, - &tmp->tm_min, - &tmp->tm_sec); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - m48_tod_set(tmp->tm_year, /* 1980-2079 */ - tmp->tm_mon, /* 01-12 */ - tmp->tm_mday, /* 01-31 */ - tmp->tm_hour, /* 00-23 */ - tmp->tm_min, /* 00-59 */ - tmp->tm_sec); /* 00-59 */ - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -void -rtc_reset (void) -{ - m48_tod_init(); -} diff --git a/board/mousse/m48t59y.h b/board/mousse/m48t59y.h deleted file mode 100644 index 2c7c092d14..0000000000 --- a/board/mousse/m48t59y.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __M48_T59_Y_H -#define __M48_T59_Y_H - -/* - * M48 T59Y -Timekeeping Battery backed SRAM. - */ - -int m48_tod_init(void); - -int m48_tod_set(int year, - int month, - int day, - int hour, - int minute, - int second); - -int m48_tod_get(int *year, - int *month, - int *day, - int *hour, - int *minute, - int *second); - -int m48_tod_get_second(void); - -void m48_watchdog_arm(int usec); - -#endif /*!__M48_T59_Y_H */ diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c deleted file mode 100644 index e1724e657d..0000000000 --- a/board/mousse/mousse.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * MOUSSE Board Support - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty, jfd@cs.stanford.edu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include "mousse.h" -#include "m48t59y.h" -#include - - -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - - puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - printf ("MPLD: Revision %d\n", SYS_REVID_GET ()); - printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); - - return 0; -} - -int checkflash (void) -{ - printf ("checkflash\n"); - flash_init (); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return CONFIG_SYS_RAM_SIZE; -} - - -void get_tod (void) -{ - int year, month, day, hour, minute, second; - - m48_tod_get (&year, &month, &day, &hour, &minute, &second); - - printf (" Current date/time: %d/%d/%d %d:%d:%d \n", - month, day, year, hour, minute, second); - -} - -/* - * EPIC, PCI, and I/O devices. - * Initialize Mousse Platform, probe for PCI devices, - * Query configuration parameters if not set. - */ -int misc_init_f (void) -{ - m48_tod_init (); /* Init SGS M48T59Y TOD/NVRAM */ - printf ("RTC: M48T589 TOD/NVRAM (%d) bytes\n", TOD_NVRAM_SIZE); - get_tod (); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h deleted file mode 100644 index 7802ab9d7c..0000000000 --- a/board/mousse/mousse.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * MOUSSE/MPC8240 Board definitions. - * For more info, see http://www.vooha.com/ - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MOUSSE_H -#define __MOUSSE_H - -/* System addresses */ - -#define PCI_SPECIAL_BASE 0xfe000000 -#define PCI_SPECIAL_SIZE 0x01000000 - -/* PORTX Device Addresses for Mousse */ - -#define PORTX_DEV_BASE 0xff000000 -#define PORTX_DEV_SIZE 0x01000000 - -#define ENET_DEV_BASE 0x80000000 - -#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000) -#define PLD_REG(off) (*(volatile unsigned char *) \ - (PLD_REG_BASE + (off))) - -#define PLD_REVID_B1 0x7f -#define PLD_REVID_B2 0x01 - -/* MPLD */ -#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ -#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) -#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) -#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) -#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) -#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) -#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) -#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) - -/* SGS M48T59Y */ -#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000) -#define TOD_REG_BASE (TOD_BASE | 0x1ff0) -#define TOD_NVRAM_BASE TOD_BASE -#define TOD_NVRAM_SIZE 0x1ff0 -#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) - -/* NS16552 SIO */ -#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80)) -#define N_SIO_CHANNELS 2 -#define N_COM_PORTS N_SIO_CHANNELS - -/* - * On-board Dec21143 PCI Ethernet - * Note: The PCI MBAR chosen here was used from MPC8240UM which states - * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS] - * is set, then PCI memory maps 1-1 with this address range in the - * correct byte order. - */ -#define PCI_ENET_IOADDR 0x80000000 -#define PCI_ENET_MEMADDR 0x80000000 - -/* - * Flash Memory Layout - * - * 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB - * sector SA3 is obscured by the 32 kB serial/TOD access space, and - * the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC - * containing the fixed boot ROM. (If the 512 kB PLCC is - * deconfigured by jumper, this window to Flash Bank 0 becomes - * visible, but it still contains the fixed boot code and should be - * considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8 - * kB), and SA2 (8 kB) are currently unused. - * - * 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully - * usable, but it's a 16-bit wide device on a 64-bit bus. Therefore - * 16-bit words only exist at addresses that are multiples of 8. All - * PROM data and control addresses must be multiplied by 8. - * - * See flashMap.c for description of flash filesystem layout. - */ - -/* - * FLASH memory address space: 8-bit wide FLASH memory spaces. - */ -#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */ -#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */ -#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */ - -#define FLASH0_SEG1_START 0xffe10000 /* 1MB - 64Kb FLASH0 seg */ -#define FLASH0_SEG1_END 0xffefffff /* 960 kB */ -#define FLASH0_SEG1_SIZE 0x000f0000 - -#define FLASH0_SEG2_START 0xfff00000 /* Boot Loader stored here */ -#define FLASH0_SEG2_END 0xfff7ffff /* 512 kB FLASH0/PLCC seg */ -#define FLASH0_SEG2_SIZE 0x00080000 - -#define FLASH0_SEG3_START 0xfff80000 /* 512 kB FLASH0 seg */ -#define FLASH0_SEG3_END 0xffffffff -#define FLASH0_SEG3_SIZE 0x00080000 - -/* Where Kahlua starts */ -#define FLASH_RESET_VECT 0xfff00100 - -/* - * CHRP / PREP (MAP A/B) definitions. - */ - -#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ -#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ -/* MPC107 (MPC8240 internal EUMBBAR mapped) */ -#define CHRP_REG_ADDR 0xfec00000 /* MPC106 Config, Map B */ -#define CHRP_REG_DATA 0xfee00000 /* MPC106 Config, Map B */ - -/* - * Mousse PCI IDSEL Assignments (Device Number) - */ -#define MOUSSE_IDSEL_ENET 13 /* On-board 21143 Ethernet */ -#define MOUSSE_IDSEL_LPCI 14 /* On-board PCI slot */ -#define MOUSSE_IDSEL_82371 15 /* That other thing */ -#define MOUSSE_IDSEL_CPCI2 31 /* CPCI slot 2 */ -#define MOUSSE_IDSEL_CPCI3 30 /* CPCI slot 3 */ -#define MOUSSE_IDSEL_CPCI4 29 /* CPCI slot 4 */ -#define MOUSSE_IDSEL_CPCI5 28 /* CPCI slot 5 */ -#define MOUSSE_IDSEL_CPCI6 27 /* CPCI slot 6 */ - -/* - * Mousse Interrupt Mapping: - * - * IRQ1 Enet (intA|intB|intC|intD) - * IRQ2 CPCI intA (See below) - * IRQ3 Local PCI slot intA|intB|intC|intD - * IRQ4 COM1 Serial port (Actually higher addressed port on duart) - * - * PCI Interrupt Mapping in CPCI chassis: - * - * | CPCI Slot - * | 1 (CPU) 2 3 4 5 6 - * -----------+--------+-------+-------+-------+-------+-------+ - * intA | X X X - * intB | X X X - * intC | X X X - * intD | X X X - */ - - -#define EPIC_VECTOR_EXT0 0 -#define EPIC_VECTOR_EXT1 1 -#define EPIC_VECTOR_EXT2 2 -#define EPIC_VECTOR_EXT3 3 -#define EPIC_VECTOR_EXT4 4 -#define EPIC_VECTOR_TM0 16 -#define EPIC_VECTOR_TM1 17 -#define EPIC_VECTOR_TM2 18 -#define EPIC_VECTOR_TM3 19 -#define EPIC_VECTOR_I2C 20 -#define EPIC_VECTOR_DMA0 21 -#define EPIC_VECTOR_DMA1 22 -#define EPIC_VECTOR_I2O 23 - - -#define INT_VEC_IRQ0 0 -#define INT_NUM_IRQ0 INT_VEC_IRQ0 -#define MOUSSE_IRQ_ENET EPIC_VECTOR_EXT1 /* Hardwired */ -#define MOUSSE_IRQ_CPCI EPIC_VECTOR_EXT2 /* Hardwired */ -#define MOUSSE_IRQ_LPCI EPIC_VECTOR_EXT3 /* Hardwired */ -#define MOUSSE_IRQ_DUART EPIC_VECTOR_EXT4 /* Hardwired */ - -/* Onboard DEC 21143 Ethernet */ -#define PCI_ENET_MEMADDR 0x80000000 -#define PCI_ENET_IOADDR 0x80000000 - -/* Some other PCI device */ -#define PCI_SLOT_MEMADDR 0x81000000 -#define PCI_SLOT_IOADDR 0x81000000 - -/* Promise ATA66 PCI Device (ATA controller) */ -#define PROMISE_MBAR0 0xa0000000 -#define PROMISE_MBAR1 (PROMISE_MBAR0 + 0x1000) -#define PROMISE_MBAR2 (PROMISE_MBAR0 + 0x2000) -#define PROMISE_MBAR3 (PROMISE_MBAR0 + 0x3000) -#define PROMISE_MBAR4 (PROMISE_MBAR0 + 0x4000) -#define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000) - -/* ATA/66 Controller offsets */ -#define CONFIG_SYS_ATA_BASE_ADDR PROMISE_MBAR0 -#define CONFIG_SYS_IDE_MAXBUS 2 /* ide0/ide1 */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 2 drives per controller */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x3000 -/* - * Definitions for accessing IDE controller registers - */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET (0x1000) - -/* - * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS - * are defined in config.h and Makefile. - * All definitions for these constants must be identical. - */ -#define ROM_BASE_ADRS 0xfff00000 /* base address of ROM */ -#define ROM_TEXT_ADRS (ROM_BASE_ADRS+0x0100) /* with PC & SP */ -#define ROM_WARM_ADRS (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */ -#define ROM_SIZE 0x00080000 /* 512KB ROM space */ -#define RAM_LOW_ADRS 0x00010000 /* RAM address for vxWorks */ -#define RAM_HIGH_ADRS 0x00c00000 /* RAM address for bootrom */ - -/* - * NVRAM configuration - * NVRAM is implemented via the SGS Thomson M48T59Y - * 64Kbit (8Kbx8) Timekeeper SRAM. - * This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information. - */ - -#define NV_RAM_ADRS TOD_NVRAM_BASE -#define NV_RAM_INTRVL 1 -#define NV_RAM_WR_ENBL SYS_TOD_UNPROTECT() -#define NV_RAM_WR_DSBL SYS_TOD_PROTECT() - -#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */ -#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */ -#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/ -#define NV_OFF_MACADDR 0x0400 /* 21143 MAC address (6b) */ -#define NV_OFF_ACTIVEBOOT 0x0406 /* Active boot string, 0 to 2 (1b) */ -#define NV_OFF_UNUSED1 0x0407 /* Unused (1b) */ -#define NV_OFF_BINDFIX 0x0408 /* See sysLib.c:sysBindFix() (1b) */ -#define NV_OFF_UNUSED2 0x0409 /* Unused (7b) */ -#define NV_OFF_TIMEZONE 0x0410 /* TIMEZONE env var (64b) */ -#define NV_OFF_VXWORKS_END 0x07FF /* 2047 VxWorks Total */ -#define NV_OFF_U_BOOT 0x0800 /* 2048 U-Boot boot-loader */ -#define NV_OFF_U_BOOT_ADDR (TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/ -#define NV_U_BOOT_ENV_SIZE 2048 /* 2K - U-Boot Total */ -#define NV_OFF__next_free (NV_U_BOOT_ENVSIZE +1) -#define NV_RAM_SIZE 8176 /* NVRAM End */ - -#endif /* __MOUSSE_H */ diff --git a/board/mousse/pci.c b/board/mousse/pci.c deleted file mode 100644 index a64144b130..0000000000 --- a/board/mousse/pci.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge - */ -#include -#include -#include - -#include "mousse.h" - -/* - * Promise ATA/66 support. - */ -#define XFER_PIO_4 0x0C /* 0000|1100 */ -#define XFER_PIO_3 0x0B /* 0000|1011 */ -#define XFER_PIO_2 0x0A /* 0000|1010 */ -#define XFER_PIO_1 0x09 /* 0000|1001 */ -#define XFER_PIO_0 0x08 /* 0000|1000 */ -#define XFER_PIO_SLOW 0x00 /* 0000|0000 */ - -/* Promise Regs */ -#define REG_A 0x01 -#define REG_B 0x02 -#define REG_C 0x04 -#define REG_D 0x08 - -void -pdc202xx_decode_registers (unsigned char registers, unsigned char value) -{ - unsigned char bit = 0, bit1 = 0, bit2 = 0; - switch(registers) { - case REG_A: - bit2 = 0; - printf(" A Register "); - if (value & 0x80) printf("SYNC_IN "); - if (value & 0x40) printf("ERRDY_EN "); - if (value & 0x20) printf("IORDY_EN "); - if (value & 0x10) printf("PREFETCH_EN "); - if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; } - printf("PIO(A) = %d ", bit2); - break; - case REG_B: - bit1 = 0;bit2 = 0; - printf(" B Register "); - if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; } - if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; } - if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; } - printf("DMA(B) = %d ", bit1 >> 5); - if (value & 0x10) printf("PIO_FORCED/PB4 "); - if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; } - printf("PIO(B) = %d ", bit2); - break; - case REG_C: - bit2 = 0; - printf(" C Register "); - if (value & 0x80) printf("DMARQp "); - if (value & 0x40) printf("IORDYp "); - if (value & 0x20) printf("DMAR_EN "); - if (value & 0x10) printf("DMAW_EN "); - - if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; } - printf("DMA(C) = %d ", bit2); - break; - case REG_D: - printf(" D Register "); - break; - default: - return; - } - printf("\n %s ", (registers & REG_D) ? "DP" : - (registers & REG_C) ? "CP" : - (registers & REG_B) ? "BP" : - (registers & REG_A) ? "AP" : "ERROR"); - for (bit=128;bit>0;bit/=2) - printf("%s", (value & bit) ? "1" : "0"); - printf("\n"); -} - -/* - * Promise ATA/66 Support: configure Promise ATA66 card in specified mode. - */ -int -pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed) -{ - unsigned short drive_conf; - int err = 0; - unsigned char drive_pci, AP, BP, CP, DP; - unsigned char TA = 0, TB = 0; - - switch (drive) { - case 0: drive_pci = 0x60; break; - case 1: drive_pci = 0x64; break; - case 2: drive_pci = 0x68; break; - case 3: drive_pci = 0x6c; break; - default: return -1; - } - - pci_read_config_word(dev, drive_pci, &drive_conf); - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - pci_read_config_byte(dev, (drive_pci)|0x03, &DP); - - if ((AP & 0x0F) || (BP & 0x07)) { - /* clear PIO modes of lower 8421 bits of A Register */ - pci_write_config_byte(dev, (drive_pci), AP & ~0x0F); - pci_read_config_byte(dev, (drive_pci), &AP); - - /* clear PIO modes of lower 421 bits of B Register */ - pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - } - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - - switch(speed) { - case XFER_PIO_4: TA = 0x01; TB = 0x04; break; - case XFER_PIO_3: TA = 0x02; TB = 0x06; break; - case XFER_PIO_2: TA = 0x03; TB = 0x08; break; - case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; - case XFER_PIO_0: - default: TA = 0x09; TB = 0x13; break; - } - - pci_write_config_byte(dev, (drive_pci), AP|TA); - pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB); - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - pci_read_config_byte(dev, (drive_pci)|0x03, &DP); - - -#ifdef PDC202XX_DEBUG - pdc202xx_decode_registers(REG_A, AP); - pdc202xx_decode_registers(REG_B, BP); - pdc202xx_decode_registers(REG_C, CP); - pdc202xx_decode_registers(REG_D, DP); -#endif - return err; -} -/* - * Show/Init PCI devices on the specified bus number. - */ - -void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned int line; - - switch(PCI_DEV(dev)) { - case 0x0d: - line = 0x00000101; - break; - - case 0x0e: - default: - line = 0x00000303; - break; - } - - pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line); -} - -void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned short vendorId; - unsigned int mbar0, cmd; - int bar, a; - - pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId); - - if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){ - /* PDC 202xx card is handled differently, it is a bootable - * device and needs all 5 MBAR's configured - */ - for(bar = 0; bar < 5; bar++){ - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0); - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); -#ifdef DEBUG - printf(" ATA_bar[%d] = %dbytes\n", bar, - ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1); -#endif - } - - /* Program all BAR's */ - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, PROMISE_MBAR2); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, PROMISE_MBAR3); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, PROMISE_MBAR4); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, PROMISE_MBAR5); - - for(bar = 0; bar < 5; bar++){ - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); -#ifdef DEBUG - printf(" ATA_bar[%d]@0x%x\n", bar, mbar0); -#endif - } - - /* Enable ROM Expansion base */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1); - - /* Io enable, Memory enable, master enable */ - pci_read_config_dword(dev, PCI_COMMAND, &cmd); - cmd &= ~0xffff0000; - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config_dword(dev, PCI_COMMAND, cmd); - - /* Breath some life into the controller */ - for( a = 0; a < 4; a++) - pdc202xx_tune_chipset(dev, a, XFER_PIO_0); - } -} - -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00, - pci_mousse_setup_pdc202xx }, -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00, - pci_cfgfunc_config_device, {PCI_ENET_IOADDR, - PCI_ENET_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_SLOT_IOADDR, - PCI_SLOT_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, -#endif - { } -}; - -struct pci_controller hose = { - config_table: pci_sandpoint_config_table, - fixup_irq: pci_mousse_fixup_irq, -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds deleted file mode 100644 index f49161c67f..0000000000 --- a/board/mousse/u-boot.lds +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram deleted file mode 100644 index c0281311c5..0000000000 --- a/board/mousse/u-boot.lds.ram +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems Ltd. robt@flyingpig.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -MEMORY { - ram (!rx) : org = 0x00000000 , LENGTH = 8M - code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000) - rom (rx) : org = 0xfff00000 , LENGTH = 512K -} - -SECTIONS -{ - _f_init = .; - PROVIDE(_f_init = .); - _f_init_rom = .; - PROVIDE(_f_init_rom = .); - - .init : { - arch/powerpc/cpu/mpc824x/start.o (.text) - *(.init) - } > ram - _init_size = SIZEOF(.init); - PROVIDE(_init_size = SIZEOF(.init)); - - ENTRY(_start) - -/* _ftext = .; - _ftext_rom = .; - _text_size = SIZEOF(.text); - */ - .text : { - *(.text) - *(.got1) - } > ram - .rodata : { *(.rodata) } > ram - .dtors : { *(.dtors) } > ram - .data : { *(.data) } > ram - .sdata : { *(.sdata) } > ram - .sdata2 : { *(.sdata2) - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } > ram - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .sbss : { *(.sbss) } > ram - .sbss2 : { *(.sbss2) } > ram - .bss : { *(.bss) } > ram - .debug : { *(.debug) } > ram - .line : { *(.line) } > ram - .symtab : { *(.symtab) } > ram - .shrstrtab : { *(.shstrtab) } > ram - .strtab : { *(.strtab) } > ram - /* .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } > ram - */ - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } > ram - __stop___ex_table = .; - - - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } > ram - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom deleted file mode 100644 index f162ae365b..0000000000 --- a/board/mousse/u-boot.lds.rom +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text) - common/board.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o (.text) - - *(.text) - - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mpc8308_p1m/Kconfig b/board/mpc8308_p1m/Kconfig new file mode 100644 index 0000000000..b7e39dafbc --- /dev/null +++ b/board/mpc8308_p1m/Kconfig @@ -0,0 +1,9 @@ +if TARGET_MPC8308_P1M + +config SYS_BOARD + default "mpc8308_p1m" + +config SYS_CONFIG_NAME + default "mpc8308_p1m" + +endif diff --git a/board/mpc8308_p1m/MAINTAINERS b/board/mpc8308_p1m/MAINTAINERS new file mode 100644 index 0000000000..80d8de7711 --- /dev/null +++ b/board/mpc8308_p1m/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8308_P1M BOARD +M: Ilya Yanok +S: Maintained +F: board/mpc8308_p1m/ +F: include/configs/mpc8308_p1m.h +F: configs/mpc8308_p1m_defconfig diff --git a/board/mpc8308_p1m/Makefile b/board/mpc8308_p1m/Makefile index 31127f082b..fb8ca3a007 100644 --- a/board/mpc8308_p1m/Makefile +++ b/board/mpc8308_p1m/Makefile @@ -7,24 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o sdram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mpc8308_p1m.o sdram.o diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c index 2009e62a1a..688cc12a6c 100644 --- a/board/mpc8308_p1m/mpc8308_p1m.c +++ b/board/mpc8308_p1m/mpc8308_p1m.c @@ -62,10 +62,12 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); + + return 0; } #endif diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c index 1b5487b144..99de2cad66 100644 --- a/board/mpl/common/kbd.c +++ b/board/mpl/common/kbd.c @@ -204,8 +204,6 @@ int drv_isa_kbd_init (void) memset (&kbddev, 0, sizeof(kbddev)); strcpy(kbddev.name, DEVNAME); kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbddev.putc = NULL ; - kbddev.puts = NULL ; kbddev.getc = kbd_getc ; kbddev.tstc = kbd_testc ; @@ -250,7 +248,7 @@ void kbd_put_queue(char data) } /* test if a character is in the queue */ -int kbd_testc(void) +int kbd_testc(struct stdio_dev *dev) { if(in_pointer==out_pointer) return(0); /* no data */ @@ -258,7 +256,7 @@ int kbd_testc(void) return(1); } /* gets the character from the queue */ -int kbd_getc(void) +int kbd_getc(struct stdio_dev *dev) { char c; while(in_pointer==out_pointer); diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h index 7b19b37259..b549e20ea4 100644 --- a/board/mpl/common/kbd.h +++ b/board/mpl/common/kbd.h @@ -8,8 +8,10 @@ #ifndef _KBD_H_ #define _KBD_H_ -extern int kbd_testc(void); -extern int kbd_getc(void); +struct stdio_dev; + +int kbd_testc(struct stdio_dev *sdev); +int kbd_getc(struct stdio_dev *sdev); extern void kbd_interrupt(void); extern char *kbd_initialize(void); diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index f9bb6ab2bc..cd969cb518 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -1,25 +1,6 @@ -/*-----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of -| the GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1995 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+-----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /* * Adapted for PIP405 03.07.01 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index ff7ce828c6..5590be1962 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -584,7 +584,7 @@ void handle_usb_interrupt(void) /* init uhci */ -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { unsigned char temp; int busdevfunc; @@ -640,118 +640,9 @@ static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {} static void usb_display_Req(unsigned short req) {} #endif -static unsigned char root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.0 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x01, /* __u8 iManufacturer; */ - 0x00, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static unsigned char root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - - -static unsigned char root_hub_hub_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x02, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - +#define WANT_USB_ROOT_HUB_HUB_DES +#include +#undef WANT_USB_ROOT_HUB_HUB_DES /* * Root Hub Control Pipe (interrupt Pipes are not supported) diff --git a/board/mpl/mip405/Kconfig b/board/mpl/mip405/Kconfig new file mode 100644 index 0000000000..48ba91a529 --- /dev/null +++ b/board/mpl/mip405/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MIP405 + +config SYS_BOARD + default "mip405" + +config SYS_VENDOR + default "mpl" + +config SYS_CONFIG_NAME + default "MIP405" + +endif diff --git a/board/mpl/mip405/MAINTAINERS b/board/mpl/mip405/MAINTAINERS new file mode 100644 index 0000000000..b323e5ab22 --- /dev/null +++ b/board/mpl/mip405/MAINTAINERS @@ -0,0 +1,7 @@ +MIP405 BOARD +M: Denis Peter +S: Maintained +F: board/mpl/mip405/ +F: include/configs/MIP405.h +F: configs/MIP405_defconfig +F: configs/MIP405T_defconfig diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 4eb997f164..5bcf130501 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -5,32 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o cmd_mip405.o \ +obj-y = mip405.o cmd_mip405.o \ ../common/pci.o \ ../common/usb_uhci.o \ ../common/common_util.o - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += init.o diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 39a1d6829a..2ea2e29c3b 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -1,26 +1,6 @@ -/*------------------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of - * the GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-------------------------------------------------------------------------------*/ - +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /*----------------------------------------------------------------------------- * Function: ext_bus_cntlr_init * Description: Initializes the External Bus Controller for the external @@ -39,7 +19,6 @@ * Bank 6 - not used * Bank 7 - PLD Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig new file mode 100644 index 0000000000..b141da3984 --- /dev/null +++ b/board/mpl/pati/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PATI + +config SYS_BOARD + default "pati" + +config SYS_VENDOR + default "mpl" + +config SYS_CONFIG_NAME + default "PATI" + +endif diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS new file mode 100644 index 0000000000..19ad05d274 --- /dev/null +++ b/board/mpl/pati/MAINTAINERS @@ -0,0 +1,6 @@ +PATI BOARD +#M: - +S: Maintained +F: board/mpl/pati/ +F: include/configs/PATI.h +F: configs/PATI_defconfig diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile index bddf012a00..9822082612 100644 --- a/board/mpl/pati/Makefile +++ b/board/mpl/pati/Makefile @@ -5,28 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o cmd_pati.o \ +obj-y := pati.o cmd_pati.o \ ../common/common_util.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 8ca9bb31d0..b9d88ee17e 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -311,6 +311,11 @@ void user_led1(int led_on) sysconf->sc_sgpiodt2=reg; /* Data register */ } +int board_early_init_f(void) +{ + spi_init_f(); + return 0; +} /**************************************************************** * Last Stage Init @@ -445,7 +450,7 @@ void pci_con_put_it(const char c) PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA); } -void pci_con_putc(const char c) +void pci_con_putc(struct stdio_dev *dev, const char c) { pci_con_put_it(c); if(c == '\n') @@ -453,7 +458,7 @@ void pci_con_putc(const char c) } -int pci_con_getc(void) +int pci_con_getc(struct stdio_dev *dev) { int res; int diff; @@ -473,14 +478,14 @@ int pci_con_getc(void) return res; } -int pci_con_tstc(void) +int pci_con_tstc(struct stdio_dev *dev) { if(r_ptr==(volatile int)w_ptr) return 0; return 1; } -void pci_con_puts (const char *s) +void pci_con_puts(struct stdio_dev *dev, const char *s) { while (*s) { pci_con_putc(*s); diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h index af34b86c31..459c14381d 100644 --- a/board/mpl/pati/pci_eeprom.h +++ b/board/mpl/pati/pci_eeprom.h @@ -1,4 +1,3 @@ - #ifndef __PCI_EEPROM_H_ #define __PCI_EEPROM_H_ 1 diff --git a/board/mpl/pip405/Kconfig b/board/mpl/pip405/Kconfig new file mode 100644 index 0000000000..f485367410 --- /dev/null +++ b/board/mpl/pip405/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PIP405 + +config SYS_BOARD + default "pip405" + +config SYS_VENDOR + default "mpl" + +config SYS_CONFIG_NAME + default "PIP405" + +endif diff --git a/board/mpl/pip405/MAINTAINERS b/board/mpl/pip405/MAINTAINERS new file mode 100644 index 0000000000..9b3b974602 --- /dev/null +++ b/board/mpl/pip405/MAINTAINERS @@ -0,0 +1,6 @@ +PIP405 BOARD +M: Denis Peter +S: Maintained +F: board/mpl/pip405/ +F: include/configs/PIP405.h +F: configs/PIP405_defconfig diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 0d40d3ab5f..0a3d059e9c 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -5,34 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o cmd_pip405.o \ +obj-y = pip405.o cmd_pip405.o \ ../common/pci.o \ ../common/isa.o \ ../common/kbd.o \ ../common/usb_uhci.o \ ../common/common_util.o - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += init.o diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index b77517fd5a..292393ec43 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -1,26 +1,6 @@ -/*------------------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of - * the GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-------------------------------------------------------------------------------*/ - +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /*----------------------------------------------------------------------------- * Function: ext_bus_cntlr_init * Description: Initializes the External Bus Controller for the external @@ -39,7 +19,6 @@ * Bank 6 - used to switch on the 12V for the Multipurpose socket * Bank 7 - Config Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/board/mpl/vcma9/Kconfig b/board/mpl/vcma9/Kconfig new file mode 100644 index 0000000000..a1564521b2 --- /dev/null +++ b/board/mpl/vcma9/Kconfig @@ -0,0 +1,15 @@ +if TARGET_VCMA9 + +config SYS_BOARD + default "vcma9" + +config SYS_VENDOR + default "mpl" + +config SYS_SOC + default "s3c24x0" + +config SYS_CONFIG_NAME + default "VCMA9" + +endif diff --git a/board/mpl/vcma9/MAINTAINERS b/board/mpl/vcma9/MAINTAINERS new file mode 100644 index 0000000000..3817436d55 --- /dev/null +++ b/board/mpl/vcma9/MAINTAINERS @@ -0,0 +1,6 @@ +VCMA9 BOARD +M: David Müller +S: Maintained +F: board/mpl/vcma9/ +F: include/configs/VCMA9.h +F: configs/VCMA9_defconfig diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index a6f924d09a..175a19fa36 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -5,30 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif +obj-y := ../common/common_util.o +obj-y += vcma9.o cmd_vcma9.o -LIB = $(obj)lib$(BOARD).o - -COBJS := ../common/common_util.o -COBJS += $(BOARD).o cmd_$(BOARD).o - -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += lowlevel_init.o diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index b889cf94af..ee9b7a9d3e 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -197,13 +197,10 @@ #define REFCNT_266 0 /**************************************/ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: /* use r0 to relocate DATA read/write to flash rather than memory ! */ - ldr r0, _TEXT_BASE + ldr r0, =CONFIG_SYS_TEXT_BASE ldr r13, =BWSCON /* enable minimal access to PLD */ @@ -232,7 +229,7 @@ lowlevel_init: bne 0b /* PLD access is now possible */ - /* r3 = SDRAMDATA + /* r3 = SDRAMDATA */ /* r13 = pointer to MEM controller regs */ ldr r1, =PLD_BASE mov r4, #SDRAMENTRY_SIZE diff --git a/board/mpr2/Kconfig b/board/mpr2/Kconfig new file mode 100644 index 0000000000..54176e8f6f --- /dev/null +++ b/board/mpr2/Kconfig @@ -0,0 +1,9 @@ +if TARGET_MPR2 + +config SYS_BOARD + default "mpr2" + +config SYS_CONFIG_NAME + default "mpr2" + +endif diff --git a/board/mpr2/MAINTAINERS b/board/mpr2/MAINTAINERS new file mode 100644 index 0000000000..beedf8dda6 --- /dev/null +++ b/board/mpr2/MAINTAINERS @@ -0,0 +1,6 @@ +MPR2 BOARD +M: Mark Jonas +S: Maintained +F: board/mpr2/ +F: include/configs/mpr2.h +F: configs/mpr2_defconfig diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile index 7920b01b49..b6cdeb4efa 100644 --- a/board/mpr2/Makefile +++ b/board/mpr2/Makefile @@ -15,25 +15,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mpr2.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := mpr2.o +obj-y += lowlevel_init.o diff --git a/board/ms7720se/Kconfig b/board/ms7720se/Kconfig new file mode 100644 index 0000000000..83313279b3 --- /dev/null +++ b/board/ms7720se/Kconfig @@ -0,0 +1,9 @@ +if TARGET_MS7720SE + +config SYS_BOARD + default "ms7720se" + +config SYS_CONFIG_NAME + default "ms7720se" + +endif diff --git a/board/ms7720se/MAINTAINERS b/board/ms7720se/MAINTAINERS new file mode 100644 index 0000000000..96a80f4e31 --- /dev/null +++ b/board/ms7720se/MAINTAINERS @@ -0,0 +1,6 @@ +MS7720SE BOARD +M: Yoshihiro Shimoda +S: Maintained +F: board/ms7720se/ +F: include/configs/ms7720se.h +F: configs/ms7720se_defconfig diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile index 219649cd6b..1819c4c10d 100644 --- a/board/ms7720se/Makefile +++ b/board/ms7720se/Makefile @@ -12,25 +12,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ms7720se.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ms7720se.o +obj-y += lowlevel_init.o diff --git a/board/ms7722se/Kconfig b/board/ms7722se/Kconfig new file mode 100644 index 0000000000..39027c9864 --- /dev/null +++ b/board/ms7722se/Kconfig @@ -0,0 +1,9 @@ +if TARGET_MS7722SE + +config SYS_BOARD + default "ms7722se" + +config SYS_CONFIG_NAME + default "ms7722se" + +endif diff --git a/board/ms7722se/MAINTAINERS b/board/ms7722se/MAINTAINERS new file mode 100644 index 0000000000..61614baece --- /dev/null +++ b/board/ms7722se/MAINTAINERS @@ -0,0 +1,7 @@ +MS7722SE BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/ms7722se/ +F: include/configs/ms7722se.h +F: configs/ms7722se_defconfig diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile index e73ceb284f..9f7af78738 100644 --- a/board/ms7722se/Makefile +++ b/board/ms7722se/Makefile @@ -9,25 +9,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ms7722se.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ms7722se.o +obj-y += lowlevel_init.o diff --git a/board/ms7750se/Kconfig b/board/ms7750se/Kconfig new file mode 100644 index 0000000000..2c0b88c775 --- /dev/null +++ b/board/ms7750se/Kconfig @@ -0,0 +1,9 @@ +if TARGET_MS7750SE + +config SYS_BOARD + default "ms7750se" + +config SYS_CONFIG_NAME + default "ms7750se" + +endif diff --git a/board/ms7750se/MAINTAINERS b/board/ms7750se/MAINTAINERS new file mode 100644 index 0000000000..e23a53247c --- /dev/null +++ b/board/ms7750se/MAINTAINERS @@ -0,0 +1,7 @@ +MS7750SE BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/ms7750se/ +F: include/configs/ms7750se.h +F: configs/ms7750se_defconfig diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile index 481c8bb954..a8e3ca0acf 100644 --- a/board/ms7750se/Makefile +++ b/board/ms7750se/Makefile @@ -4,25 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).o - -COBJS := ms7750se.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ms7750se.o +obj-y += lowlevel_init.o diff --git a/board/muas3001/Makefile b/board/muas3001/Makefile deleted file mode 100644 index b4b784a742..0000000000 --- a/board/muas3001/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c deleted file mode 100644 index 42b0a035c7..0000000000 --- a/board/muas3001/muas3001.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -#include -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */ - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_PWRDWN */ - /* PA24 */ { 1, 0, 0, 1, 0, 1 }, /* ETH_RESET */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_SLEEP */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* MDIO */ - /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */ - /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */ - /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */ - /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ - /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */ - /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */ - /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */ - /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */ - /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */ - /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */ - /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */ - /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */ - /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */ - /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RxD */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB12 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TxD */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 1, 1, 1, 1, 0, 0 }, /* Timer1 OUT */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC RxCLK 11 */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC TxCLK 12 */ - /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW1 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW0 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* SPA_TX_EN */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ - /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */ - /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else - /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */ -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or1; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size ((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - long psize; -#ifndef CONFIG_SYS_RAMBOOT - long sizelittle, sizebig; -#endif - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE, - (uchar *) CONFIG_SYS_SDRAM_BASE); - sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG, - (uchar *) CONFIG_SYS_SDRAM_BASE); - if (sizelittle < sizebig) { - psize = sizebig; - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE, - (uchar *) CONFIG_SYS_SDRAM_BASE); - } -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -int checkboard (void) -{ - puts ("Board: MUAS3001\n"); - - return 0; -} - -/* - * Early board initalization. - */ -int board_early_init_r (void) -{ - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -/* - * update "memory" property in the blob - */ -void ft_blob_update (void *blob, bd_t *bd) -{ - int ret, nodeoffset = 0; - ulong flash_data[4] = {0}; - ulong speed = 0; - - /* update Flash addr, size */ - flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE); - flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE); - nodeoffset = fdt_path_offset (blob, "/localbus"); - if (nodeoffset >= 0) { - ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data, - sizeof (flash_data)); - if (ret < 0) - printf ("ft_blob_update): cannot set /localbus/ranges " - "property err:%s\n", fdt_strerror(ret)); - } else { - /* memory node is required in dts */ - printf ("ft_blob_update(): cannot find /localbus node " - "err:%s\n", fdt_strerror (nodeoffset)); - } - - /* baudrate */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); - if (nodeoffset >= 0) { - speed = cpu_to_be32 (bd->bi_baudrate); - ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed, - sizeof (unsigned long)); - if (ret < 0) - printf ("ft_blob_update): cannot set /soc/cpm/serial/current-speed " - "property err:%s\n", fdt_strerror (ret)); - } else { - /* baudrate is required in dts */ - printf ("ft_blob_update(): cannot find /soc/cpm/smc2/current-speed node " - "err:%s\n", fdt_strerror (nodeoffset)); - } -} - -void ft_board_setup (void *blob, bd_t *bd) -{ - ft_cpu_setup (blob, bd); - ft_blob_update (blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/munices/Kconfig b/board/munices/Kconfig new file mode 100644 index 0000000000..019aaae3e9 --- /dev/null +++ b/board/munices/Kconfig @@ -0,0 +1,9 @@ +if TARGET_MUNICES + +config SYS_BOARD + default "munices" + +config SYS_CONFIG_NAME + default "munices" + +endif diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS new file mode 100644 index 0000000000..50d3e7ebda --- /dev/null +++ b/board/munices/MAINTAINERS @@ -0,0 +1,6 @@ +MUNICES BOARD +#M: - +S: Maintained +F: board/munices/ +F: include/configs/munices.h +F: configs/munices_defconfig diff --git a/board/munices/Makefile b/board/munices/Makefile index 97fc2b6ce4..d16e2a1fa2 100644 --- a/board/munices/Makefile +++ b/board/munices/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := munices.o diff --git a/board/munices/munices.c b/board/munices/munices.c index 319fa8cba4..23d0f56bd6 100644 --- a/board/munices/munices.c +++ b/board/munices/munices.c @@ -146,9 +146,10 @@ void pci_init_board(void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/musenki/Makefile b/board/musenki/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/musenki/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/musenki/README b/board/musenki/README deleted file mode 100644 index 084ab54ff7..0000000000 --- a/board/musenki/README +++ /dev/null @@ -1,298 +0,0 @@ -U-Boot for a Musenki M-3/M-1 board ---------------------------- - -Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each. - -In board's notation, bank 0 is the one at the address of 0xFF800000 -and bank 1 is the one at the address of 0xFF000000. - -On power-up the processor jumps to the address of 0xFFF00100, the last -megabyte of the bank 0 of flash. - -Thus, U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the address of 0xFF800000. - -There is a Davicom 9102A on-board, but I don't have it working yet. - -U-Boot test results --------------------- - -x.x Operation on all available serial consoles - -x.x.x CONFIG_CONS_INDEX 1 - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> help -base - print or set address offset -bdinfo - print Board Info structure -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -cmp - memory compare -coninfo - print console devices and informations -cp - memory copy -crc32 - checksum calculation -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -icache - enable or disable instruction cache -iminfo - print header information for application image -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loop - infinite loop on address range -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -source - run script from memory -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -version - print monitor version -? - alias for 'help' - - -x.x.x CONFIG_CONS_INDEX 2 - -**** NOT TESTED **** - -x.x Flash Driver Operation - - -Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> -=> md ff800000 -ff800000: 46989bf8 626f6f74 636d643d 626f6f74 F...bootcmd=boot -ff800010: 6d204646 38323030 30300062 6f6f7464 m FF820000.bootd -ff800020: 656c6179 3d350062 61756472 6174653d elay=5.baudrate= -ff800030: 39363030 00636c6f 636b735f 696e5f6d 9600.clocks_in_m -ff800040: 687a3d31 00737464 696e3d73 65726961 hz=1.stdin=seria -ff800050: 6c007374 646f7574 3d736572 69616c00 l.stdout=serial. -ff800060: 73746465 72723d73 65726961 6c006970 stderr=serial.ip -ff800070: 61646472 3d313932 2e313638 2e302e34 addr=192.168.0.4 -ff800080: 32007365 72766572 69703d31 39322e31 2.serverip=192.1 -ff800090: 36382e30 2e380000 00000000 00000000 68.0.8.......... -ff8000a0: 00000000 00000000 00000000 00000000 ................ -ff8000b0: 00000000 00000000 00000000 00000000 ................ -ff8000c0: 00000000 00000000 00000000 00000000 ................ -ff8000d0: 00000000 00000000 00000000 00000000 ................ -ff8000e0: 00000000 00000000 00000000 00000000 ................ -ff8000f0: 00000000 00000000 00000000 00000000 ................ -=> protect off ff800000 ff81ffff -Un-Protected 1 sectors -=> erase ff800000 ff81ffff -Erase Flash from 0xff800000 to 0xff81ffff - done -Erased 1 sectors -=> md ff800000 -ff800000: ffffffff ffffffff ffffffff ffffffff ................ -ff800010: ffffffff ffffffff ffffffff ffffffff ................ -ff800020: ffffffff ffffffff ffffffff ffffffff ................ -ff800030: ffffffff ffffffff ffffffff ffffffff ................ -ff800040: ffffffff ffffffff ffffffff ffffffff ................ -ff800050: ffffffff ffffffff ffffffff ffffffff ................ -ff800060: ffffffff ffffffff ffffffff ffffffff ................ -ff800070: ffffffff ffffffff ffffffff ffffffff ................ -ff800080: ffffffff ffffffff ffffffff ffffffff ................ -ff800090: ffffffff ffffffff ffffffff ffffffff ................ -ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ - -x.x.x Information - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> flinfo - -Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32) - Size: 4 MB in 32 Sectors - Sector Start Addresses: - FF800000 (RO) FF820000 FF840000 FF860000 FF880000 - FF8A0000 FF8C0000 FF8E0000 FF900000 FF920000 - FF940000 FF960000 FF980000 FF9A0000 FF9C0000 - FF9E0000 FFA00000 FFA20000 FFA40000 FFA60000 - FFA80000 FFAA0000 FFAC0000 FFAE0000 FFB00000 - FFB20000 FFB40000 FFB60000 FFB80000 FFBA0000 - FFBC0000 FFBE0000 - -Bank # 2: missing or unknown FLASH type -=> - - -x.x.x Flash Programming - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> -=> -=> -=> protect off ff800000 ff81ffff -Un-Protected 1 sectors -=> cp 0 ff800000 20 -Copy to Flash... done -=> md ff800000 -ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc 7.3.3.3L3.1.3.5. -ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc 3...0.....3.1.6. -ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec 3.;.1.3.....3.3. -ff800030: 234c33ec 32cc22cc 33883bdc 534433cc #L3.2.".3.;.SD3. -ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc 3.0.1.2.3.3.3.3. -ff800050: 33cc13dc 334c534c b1c433d8 128c13cc 3...3LSL..3..... -ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc 7.6.3.3.......w. -ff800070: 314c0adc 139c30ed 33cc334c 33c833ec 1L....0.3.3L3.3. -ff800080: ffffffff ffffffff ffffffff ffffffff ................ -ff800090: ffffffff ffffffff ffffffff ffffffff ................ -ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ - - -x.x.x Storage of environment variables in flash - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=bootm FF820000 -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 106/16380 bytes -=> setenv myvar 1234 -=> saveenv -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=> reset - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=bootm FF820000 -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -myvar=1234 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 117/16380 bytes - -x.x Image Download and run over serial port - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> loads -## Ready for S-Record download ... - -## First Load Addr = 0x00040000 -## Last Load Addr = 0x00050177 -## Total Size = 0x00010178 = 65912 Bytes -## Start Addr = 0x00040004 -=> go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 - - -x.x Image download and run over ethernet interface - -untested (not working yet, actually) diff --git a/board/musenki/flash.c b/board/musenki/flash.c deleted file mode 100644 index 080ec7fc3d..0000000000 --- a/board/musenki/flash.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data (flash_info_t *info, uchar *dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/* - * don't ask. its stupid, but more than one soul has had to live with this mistake - * "swaptab[i]" is the value of "i" with the bits reversed. - */ - -#define MUSENKI_BROKEN_FLASH 1 - -#ifdef MUSENKI_BROKEN_FLASH -unsigned char swaptab[256] = { - 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, - 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, - 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, - 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, - 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, - 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, - 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, - 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, - 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, - 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, - 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, - 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, - 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, - 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, - 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, - 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, - 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, - 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, - 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, - 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, - 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, - 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, - 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, - 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, - 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, - 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, - 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, - 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, - 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, - 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, - 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, - 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff, -}; - -#define BS(b) (swaptab[b]) - -#else - -#define BS(b) (b) - -#endif - -#define BYTEME(x) ((x) & 0xFF) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, monitor_flash_len); - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE); - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - flash_info[1].size = size_b1; - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; /* 128k per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ - vu_char manuf, device; - - addr[0] = BS(0x90); - manuf = BS(addr[0]); - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf); - - switch (manuf) { - case BYTEME(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case BYTEME(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case BYTEME(SST_MANUFACT): - info->flash_id = FLASH_MAN_SST; - break; - case BYTEME(STM_MANUFACT): - info->flash_id = FLASH_MAN_STM; - break; - case BYTEME(INTEL_MANUFACT): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ - return 0; /* no or unknown flash */ - } - - device = BS(addr[2]); /* device ID */ - - DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device); - - switch (device) { - case BYTEME(INTEL_ID_28F320J3A): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case BYTEME(INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case BYTEME(INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ - return 0; /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = BS(0xFF); /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (vu_char *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x50); /* clear status register */ - *addr = BS(0x20); /* erase setup */ - *addr = BS(0xD0); /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = BS(0xB0); /* suspend erase */ - *addr = BS(0xFF); /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = BS(0xFF); /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 1 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - uchar *wp = (uchar *)addr; - int rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - while (cnt > 0) { - if ((rc = write_data(info, wp, *src)) != 0) { - return rc; - } - wp++; - src++; - cnt--; - } - - return cnt; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, uchar *dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((BS(*addr) & data) != data) { - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x40); /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - start = get_timer (0); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = BS(0xFF); /* restore read mode */ - return 1; - } - } - - *addr = BS(0xFF); /* restore read mode */ - - return 0; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c deleted file mode 100644 index aa92fc4281..0000000000 --- a/board/musenki/musenki.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -int checkboard (void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; - -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { -#if 0 - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - 0x0, 0x0, 0x0, /* unknown eth0 divice */ - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - 0x0, 0x0, 0x0, /* unknown eth1 device */ - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, -#endif - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/mvblue/Makefile b/board/mvblue/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/mvblue/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c deleted file mode 100644 index 5dd658ff8a..0000000000 --- a/board/mvblue/flash.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2001-2003 - * - * Changes for MATRIX Vision mvBLUE devices - * MATRIX Vision GmbH / hg,as info@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#if 0 - #define mvdebug(p) printf ##p -#else - #define mvdebug(p) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define FLASH_BUS_WIDTH 8 - -#if (FLASH_BUS_WIDTH==32) - #define FLASH_DATA_MASK 0xffffffff - #define FLASH_SHIFT 1 - #define FDT vu_long -#elif (FLASH_BUS_WIDTH==16) - #define FLASH_DATA_MASK 0xff - #define FLASH_SHIFT 0 - #define FDT vu_short -#elif (FLASH_BUS_WIDTH==8) - #define FLASH_DATA_MASK 0xff - #define FLASH_SHIFT 0 - #define FDT vu_char -#else - #error FLASH_BUS_WIDTH undefined -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *address, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - for (i=0; iflash_id & FLASH_BTYPE) - { /* bottom boot sector types - these are the useful ones! */ - /* set sector offsets for bottom boot block type */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) - { /* AMDLV320B has 8 x 8k bottom boot sectors */ - for (i = 0; i < 8; i++) /* +8k */ - info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); - for (; i < info->sector_count; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT); - } - else - { /* other types have 4 bottom boot sectors (16,8,8,32) */ - i = 0; - info->start[i++] = base + 0x00000000; /* - */ - info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */ - info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */ - info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */ - info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */ - for (; i < info->sector_count; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT); - } - } - else - { /* top boot sector types - not so useful */ - /* set sector offsets for top boot block type */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) - { /* AMDLV320T has 8 x 8k top boot sectors */ - for (i = 0; i < info->sector_count - 8; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); - for (; i < info->sector_count; i++) /* +8k */ - info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); - } - else - { /* other types have 4 top boot sectors (32,8,8,16) */ - for (i = 0; i < info->sector_count - 4; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); - - info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */ - info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */ - info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */ - info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */ - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_STM: printf ("ST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK) -#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK) -#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK) -#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK) -#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK) -#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK) -#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK) -#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK) -#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK) - -#if (FLASH_BUS_WIDTH >= 16) - #define AUTOSELECT_ADDR1 0x0555 - #define AUTOSELECT_ADDR2 0x02AA - #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 -#else - #define AUTOSELECT_ADDR1 0x0AAA - #define AUTOSELECT_ADDR2 0x0555 - #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 -#endif - -#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK) - -#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK) - - -static ulong flash_get_size (vu_long *address, flash_info_t *info) -{ - short i; - FDT value; - FDT *addr = (FDT *)address; - - ulong base = (ulong)address; - addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1; - addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2; - addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3; - __asm__ __volatile__("sync"); - - udelay(180); - - value = addr[0]; /* manufacturer ID */ - switch (value) { - case AMD_MANUFACT_MVS: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT_MVS: - info->flash_id = FLASH_MAN_FUJ; - break; - case STM_MANUFACT_MVS: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } -#if (FLASH_BUS_WIDTH >= 16) - value = addr[1]; /* device ID */ -#else - value = addr[2]; /* device ID */ -#endif - - switch (value) { - case AMD_ID_LV160T_MVS: - info->flash_id += FLASH_AM160T; - info->sector_count = 37; - info->size = (0x00200000 << FLASH_SHIFT); - break; /* => 2 or 4 MB */ - - case AMD_ID_LV160B_MVS: - info->flash_id += FLASH_AM160B; - info->sector_count = 37; - info->size = (0x00200000 << FLASH_SHIFT); - break; /* => 2 or 4 MB */ - - case AMD_ID_LV320T_MVS: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8 MB */ - - case AMD_ID_LV320B_MVS: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8MB */ - - case STM_ID_W320DT_MVS: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8 MB */ - - case STM_ID_W320DB_MVS: - info->flash_id += FLASH_STMW320DB; - info->sector_count = 67; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - flash_get_offsets (base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (FDT *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (FDT *)info->start[0]; - *addr = RESET_BANK_DATA; /* reset bank */ - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -#if (FLASH_BUS_WIDTH >= 16) - #define ERASE_ADDR1 0x0555 - #define ERASE_ADDR2 0x02AA -#else - #define ERASE_ADDR1 0x0AAA - #define ERASE_ADDR2 0x0555 -#endif - -#define ERASE_ADDR3 ERASE_ADDR1 -#define ERASE_ADDR4 ERASE_ADDR1 -#define ERASE_ADDR5 ERASE_ADDR2 - -#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK) -#define ERASE_DATA4 ERASE_DATA1 -#define ERASE_DATA5 ERASE_DATA2 - -#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK) -#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK) -#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK) - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FDT *addr = (FDT *)(info->start[0]); - - int prot, sect, l_sect, flag; - ulong start, now, last; - - __asm__ __volatile__ ("sync"); - addr[0] = 0xf0; - udelay(1000); - - printf("\nflash_erase: first = %d @ 0x%08lx\n", s_first, info->start[s_first] ); - printf(" last = %d @ 0x%08lx\n", s_last , info->start[s_last ] ); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ERASE_ADDR1] = ERASE_DATA1; - addr[ERASE_ADDR2] = ERASE_DATA2; - addr[ERASE_ADDR3] = ERASE_DATA3; - addr[ERASE_ADDR4] = ERASE_DATA4; - addr[ERASE_ADDR5] = ERASE_DATA5; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { - addr = (FDT *)(info->start[sect]); - addr[0] = ERASE_SECTOR_DATA; - l_sect = sect; - } - } - - if (flag) - enable_interrupts(); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FDT *)(info->start[l_sect]); - - while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#define BUFF_INC 4 - ulong cp, wp, data; - int i, l, rc; - - mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt)); - - wp = (addr & ~3); /* get lower word aligned address */ - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - mvdebug ((" handle unaligned start bytes (cnt = 0x%08lx)\n", cnt)); - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= BUFF_INC) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i= 16) - #define WRITE_ADDR1 0x0555 - #define WRITE_ADDR2 0x02AA -#else - #define WRITE_ADDR1 0x0AAA - #define WRITE_ADDR2 0x0555 - #define WRITE_ADDR3 WRITE_ADDR1 -#endif - -#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK) - -#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_char (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - printf(" *** ERROR: Flash not erased !\n"); - return (2); - } - flag = disable_interrupts(); - - addr[WRITE_ADDR1] = WRITE_DATA1; - addr[WRITE_ADDR2] = WRITE_DATA2; - addr[WRITE_ADDR3] = WRITE_DATA3; - *((vu_char *)dest) = data; - - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - addr = (vu_char *)dest; - while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - printf(" *** ERROR: Flash write timeout !"); - return (1); - } - } - mvdebug (("-write_byte\n")); - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - int i, - result = 0; - - mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest)); - for ( i=0; (i < 4) && (result == 0); i++, dest+=1 ) - result = write_char (info, dest, (data >> (8*(3-i))) & 0xff ); - mvdebug (("-write_word\n")); - return result; -} -/*---------------------------------------------------------------- */ diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c deleted file mode 100644 index 69abb06251..0000000000 --- a/board/mvblue/mvblue.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * GNU General Public License for more details. - * - * MATRIX Vision GmbH / June 2002-Nov 2003 - * Andre Schwarz - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_PCI -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -u32 get_BoardType (void); - -#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \ - | ((d&0x1f)<<11) \ - | ((f&0x7)<<7) \ - | (r&0xfc) ) - -int mv_pci_read (int bus, int dev, int func, int reg) -{ - *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg); - asm ("sync"); - return cpu_to_le32 (*(u32 *) (0xfee00cfc)); -} - -u32 get_BoardType () -{ - return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1); -} - -void init_2nd_DUART (void) -{ - NS16550_t console = (NS16550_t) CONFIG_SYS_NS16550_COM2; - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE; - - *(u8 *) (0xfc004511) = 0x1; - NS16550_init (console, clock_divisor); -} -void hw_watchdog_reset (void) -{ - if (get_BoardType () == 0) { - *(u32 *) (0xff000005) = 0; - asm ("sync"); - } -} -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - u32 BoardType = get_BoardType (); - char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" }; - char *p; - bd_t *bd = gd->bd; - - hw_watchdog_reset (); - - printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION); - printf (" Found %s running at %s MHz memory clock.\n", - BoardName[BoardType], strmhz (buf, busfreq)); - - init_2nd_DUART (); - - if ((p = getenv ("console_nr")) != NULL) { - unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; - - bd->bi_baudrate &= ~3; - bd->bi_baudrate |= con_nr & 3; - } - return 0; -} - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_prep (u8 * e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - if ((ptr = getenv ("dhcp_vendor-class-identifier"))) { - *e++ = 60; - *e++ = strlen (ptr); - while (*ptr) - *e++ = *ptr++; - } - /* my DHCP_CLIENT_IDENTIFIER = 61 */ - if ((ptr = getenv ("dhcp_client_id"))) { - *e++ = 61; - *e++ = strlen (ptr); - while (*ptr) - *e++ = *ptr++; - } - return e; -} - -u8 *dhcp_vendorex_proc (u8 * popt) -{ - return NULL; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Initialize PCI Devices - */ -#ifdef CONFIG_PCI -void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev) -{ - u32 cnt; - - printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev), - PCI_FUNC (dev)); - for (cnt = 0; cnt < 6; cnt++) - pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt), - 0x0); - printf ("done\n"); -} - -void duart_setup (u32 base, u16 divisor) -{ - printf ("duart setup ..."); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x80); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 0), divisor & 0xff); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 1), divisor >> 8); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x03); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 4), 0x03); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 2), 0x07); - printf ("done\n"); -} - -void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose, - pci_dev_t bridge, unsigned char irq) -{ - pci_dev_t d; - unsigned char bus; - unsigned short vendor, class; - - pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus); - for (d = PCI_BDF (bus, 0, 0); - d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1, - PCI_MAX_PCI_FUNCTIONS - 1); - d += PCI_BDF (0, 0, 1)) { - pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor); - if (vendor != 0xffff && vendor != 0x0000) { - pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE, - &class); - if (class == PCI_CLASS_BRIDGE_PCI) - pci_mvblue_fixup_irq_behind_bridge (hose, d, - irq); - else - pci_hose_write_config_byte (hose, d, - PCI_INTERRUPT_LINE, - irq); - } - } -} - -#define MV_MAX_PCI_BUSSES 3 -#define SLOT0_IRQ 3 -#define SLOT1_IRQ 4 -void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line = 0xff; - unsigned short class; - - if (PCI_BUS (dev) == 0) { - switch (PCI_DEV (dev)) { - case 0xd: - if (get_BoardType () == 0) { - line = 1; - } else - /* mvBL */ - line = 2; - break; - case 0xe: - /* mvBB: IDE */ - line = 2; - pci_hose_write_config_byte (hose, dev, 0x8a, 0x20); - break; - case 0xf: - /* mvBB: Slot0 (Grabber) */ - pci_hose_read_config_word (hose, dev, - PCI_CLASS_DEVICE, &class); - if (class == PCI_CLASS_BRIDGE_PCI) { - pci_mvblue_fixup_irq_behind_bridge (hose, dev, - SLOT0_IRQ); - line = 0xff; - } else - line = SLOT0_IRQ; - break; - case 0x10: - /* mvBB: Slot1 */ - pci_hose_read_config_word (hose, dev, - PCI_CLASS_DEVICE, &class); - if (class == PCI_CLASS_BRIDGE_PCI) { - pci_mvblue_fixup_irq_behind_bridge (hose, dev, - SLOT1_IRQ); - line = 0xff; - } else - line = SLOT1_IRQ; - break; - default: - printf ("***pci_scan: illegal dev = 0x%08x\n", - PCI_DEV (dev)); - line = 0xff; - break; - } - pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, - line); - } -} - -struct pci_controller hose = { - fixup_irq:pci_mvblue_fixup_irq -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} -#endif diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds deleted file mode 100644 index 121354bfeb..0000000000 --- a/board/mvblue/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2001-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text*) - lib/libgeneric.o (.text*) - net/libnet.o (.text*) - drivers/pci/libpci.o (.text*) - arch/powerpc/cpu/mpc824x/libmpc824x.o (.text*) - board/mvblue/libmvblue.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile deleted file mode 100644 index e34e18217f..0000000000 --- a/board/mx1ads/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# -# board/mx1ads/Makefile -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (c) Copyright 2004 -# Techware Information Technology, Inc. -# http://www.techware.com.tw/ -# -# Ming-Len Wu -# -# SPDX-License-Identifier: GPL-2.0+ - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx1ads.o syncflash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S deleted file mode 100644 index d1e472a933..0000000000 --- a/board/mx1ads/lowlevel_init.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * board/mx1ads/lowlevel_init.S - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#define SDCTL0 0x221000 -#define SDCTL1 0x221004 - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: -/* memory controller init */ - - ldr r1, =SDCTL0 - -/* Set Precharge Command */ - - ldr r3, =0x92120200 -/* ldr r3, =0x92120251 -*/ - str r3, [r1] - -/* Issue Precharge All Commad */ - ldr r3, =0x8200000 - ldr r2, [r3] - -/* Set AutoRefresh Command */ - ldr r3, =0xA2120200 - str r3, [r1] - -/* Issue AutoRefresh Command */ - ldr r3, =0x8000000 - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - -/* Set Mode Register */ - ldr r3, =0xB2120200 - str r3, [r1] - -/* Issue Mode Register Command */ - ldr r3, =0x08111800 /* Mode Register Value */ - ldr r2, [r3] - -/* Set Normal Mode */ - ldr r3, =0x82124200 - str r3, [r1] - -/* everything is fine now */ - mov pc, lr diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c deleted file mode 100644 index 4266048981..0000000000 --- a/board/mx1ads/mx1ads.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * board/mx1ads/mx1ads.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -/*#include */ -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -#if 0 - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -#endif - -/* - * Miscellaneous platform dependent initialisations - */ - -void SetAsynchMode (void) -{ - __asm__ ("mrc p15,0,r0,c1,c0,0 \n" - "mov r2, #0xC0000000 \n" - "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n"); -} - -static u32 mc9328sid; - -int board_early_init_f(void) -{ - mc9328sid = SIDR; - - GPCR = 0x000003AB; /* I/O pad driving strength */ - - /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ -/* MX1_CS1L = 0x11110601; */ - - MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ - -/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and - * BCLK divider to 2 (i.e. BCLK to 48 MHz) - */ - CSCR = 0xAF000403; - - CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ - CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ - -/* setup cs4 for cs8900 ethernet */ - - CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ - CS4L = 0x00001501; - - GIUS (0) &= 0xFF3FFFFF; - GPR (0) &= 0xFF3FFFFF; - - readl(0x1500000C); - readl(0x1500000C); - - SetAsynchMode (); - - icache_enable (); - dcache_enable (); - -/* set PERCLKs */ - PCDR = 0x00000055; /* set PERCLKS */ - -/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes - * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place - * all sources selected as normal interrupt - */ - -/* MX1_INTTYPEH = 0; - MX1_INTTYPEL = 0; -*/ - return 0; -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; - - gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ - - return 0; -} - -int board_late_init (void) -{ - - setenv ("stdout", "serial"); - setenv ("stderr", "serial"); - - switch (mc9328sid) { - case 0x0005901d: - printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - case 0x04d4c01d: - printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - case 0x00d4c01d: - printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - - default: - printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n", - mc9328sid); - break; - } - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c deleted file mode 100644 index 5d685338fb..0000000000 --- a/board/mx1ads/syncflash.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * board/mx1ads/syncflash.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -/*#include */ -#include - -typedef unsigned long * p_u32; - -/* 4Mx16x2 IAM=0 CSD1 */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Following Setting is for CSD1 */ -#define SFCTL 0x00221004 -#define reg_SFCTL __REG(SFCTL) - -#define SYNCFLASH_A10 (0x00100000) - -#define CMD_NORMAL (0x81020300) /* Normal Mode */ -#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ -#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ -#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ -#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ -#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) - -#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ - -/* LCR Command */ -#define LCR_READSTATUS (0x0001C000) /* 0x70 */ -#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ -#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ -#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ -#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ - -/* Get Status register */ -u32 SF_SR(void) { - u32 tmp; - - reg_SFCTL = CMD_PROGRAM; - tmp = __REG(CONFIG_SYS_FLASH_BASE); - - reg_SFCTL = CMD_NORMAL; - - reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR); - - return tmp; -} - -/* check if SyncFlash is ready */ -u8 SF_Ready(void) { - u32 tmp; - - tmp = SF_SR(); - - if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { - printf ("SyncFlash Error code %08x\n",tmp); - }; - - if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { - printf ("SyncFlash Error code %08x\n",tmp); - }; - - if (tmp == 0x00800080) /* Test Bit 7 of SR */ - return 1; - else - return 0; -} - -/* Issue the precharge all command */ -void SF_PrechargeAll(void) { - - /* Set Precharge Command */ - reg_SFCTL = CMD_PREC; - /* Issue Precharge All Command */ - __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); -} - -/* set SyncFlash to normal mode */ -void SF_Normal(void) { - - SF_PrechargeAll(); - - reg_SFCTL = CMD_NORMAL; -} - -/* Erase SyncFlash */ -void SF_Erase(u32 RowAddress) { - - reg_SFCTL = CMD_NORMAL; - __REG(RowAddress); - - reg_SFCTL = CMD_PREC; - __REG(RowAddress); - - reg_SFCTL = CMD_LCR; /* Set LCR mode */ - __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ - - reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ - __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ - - while(!SF_Ready()); -} - -void SF_NvmodeErase(void) { - SF_PrechargeAll(); - - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ - - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ - - while(!SF_Ready()); -} - -void SF_NvmodeWrite(void) { - SF_PrechargeAll(); - - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ - - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ -} - -/****************************************************************************************/ - -ulong flash_init(void) { - int i, j; - -/* Turn on CSD1 for negating RESETSF of SyncFLash */ - - reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ - udelay(200); - - reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ - __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ - - SF_Normal(); - - i = 0; - - flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000; - } - - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - - return FLASH_BANK_SIZE; -} - -void flash_print_info (flash_info_t *info) { - - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FLASH_MAN_MT & FLASH_VENDMASK): - printf("Micron: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): - printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses: "); - - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) - printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*-----------------------------------------------------------------------*/ - -int flash_erase (flash_info_t *info, int s_first, int s_last) { - int iflag, cflag, prot, sect; - int rc = ERR_OK; - -/* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) - return ERR_INVAL; - - if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("protected!\n"); - return ERR_PROTECTED; - } -/* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status(); - icache_disable(); - iflag = disable_interrupts(); - -/* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - -/* arm simple, non interrupt dependent timer */ - - get_timer(0); - - SF_NvmodeErase(); - SF_NvmodeWrite(); - - SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect)); - SF_Normal(); - - printf("ok.\n"); - } - - if (ctrlc()) - printf("User Interrupt!\n"); - - if (iflag) - enable_interrupts(); - - if (cflag) - icache_enable(); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { - int i; - - for(i = 0; i < cnt; i += 4) { - - SF_PrechargeAll(); - - reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ - __REG(addr + i) = __REG((u32)src + i); - - while(!SF_Ready()); - } - - SF_Normal(); - - return ERR_OK; -} diff --git a/board/netphone/Makefile b/board/netphone/Makefile deleted file mode 100644 index 4d86589d8e..0000000000 --- a/board/netphone/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o phone_console.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/netphone/flash.c b/board/netphone/flash.c deleted file mode 100644 index 91bd968379..0000000000 --- a/board/netphone/flash.c +++ /dev/null @@ -1,513 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; -#if CONFIG_NETPHONE_VERSION == 2 - unsigned long size1; -#endif - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - -#if CONFIG_NETPHONE_VERSION == 2 - size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]); - if (size1 > 0) { - if (flash_info[1].flash_id == FLASH_UNKNOWN) - printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20); - - /* Remap FLASH according to real size */ - memctl->memc_or4 = CONFIG_SYS_OR_TIMING_FLASH | (-size1 & 0xFFFF8000); - memctl->memc_br4 = (CONFIG_SYS_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size1 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE4, &flash_info[1]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE4, &flash_info[1]); - - size += size1; - } else - memctl->memc_br4 &= ~BR_V; -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c deleted file mode 100644 index 053bdf1416..0000000000 --- a/board/netphone/netphone.c +++ /dev/null @@ -1,690 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include -#include -#include -#include - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -#if CONFIG_NETPHONE_VERSION == 2 -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; -#endif - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, - BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK _B(28) -#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_DIRVAL 0 - -#if CONFIG_NETPHONE_VERSION == 1 -#define PC_GP_INMASK _BW(12) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) -#elif CONFIG_NETPHONE_VERSION == 2 -#define PC_GP_INMASK (_BW(13) | _BW(15)) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) -#endif -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL (_BW(10) | _BW(11)) -#define PC_SP_DIRVAL 0 - -#if CONFIG_NETPHONE_VERSION == 1 -#define PE_GP_INMASK _B(31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) -#elif CONFIG_NETPHONE_VERSION == 2 -#define PE_GP_INMASK _BR(28, 31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) -#endif -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* NAND chip select */ -#if CONFIG_NETPHONE_VERSION == 1 - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#elif CONFIG_NETPHONE_VERSION == 2 - upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); - memctl->memc_mamr = 0; /* all clear */ -#endif - - /* DSP chip select */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - -#if CONFIG_NETPHONE_VERSION == 1 - memctl->memc_br4 &= ~BR_V; -#endif - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; - - return 0; -} - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#ifdef CONFIG_SHOW_ACTIVITY - -static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */ - -/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */ -void board_show_activity(ulong timestamp) -{ - if (left_to_poll > -PHONE_CONSOLE_POLL_HZ) - --left_to_poll; -} - -extern void phone_console_do_poll(void); - -static void do_poll(void) -{ - unsigned int base; - - while (left_to_poll <= 0) { - phone_console_do_poll(); - base = left_to_poll + PHONE_CONSOLE_POLL_HZ; - do { - left_to_poll = base; - } while (base != left_to_poll); - } -} - -/* called when looping */ -void show_activity(int arg) -{ - do_poll(); -} - -#endif - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return drv_phone_init(); -} - -int last_stage_init(void) -{ - int i; - -#if CONFIG_NETPHONE_VERSION == 2 - /* assert peripheral reset */ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); - for (i = 0; i < 10; i++) - udelay(1000); - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12); -#endif - reset_phys(); - - /* check in order to enable the local console */ - left_to_poll = PHONE_CONSOLE_POLL_HZ; - i = CONFIG_SYS_HZ * 2; - while (i > 0) { - - if (tstc()) { - getc(); - break; - } - - do_poll(); - - if (drv_phone_use_me()) { - status_led_set(0, STATUS_LED_ON); - while (!drv_phone_is_idle()) { - do_poll(); - udelay(1000000 / CONFIG_SYS_HZ); - } - - console_assign(stdin, "phone"); - console_assign(stdout, "phone"); - console_assign(stderr, "phone"); - setenv("bootdelay", "-1"); - break; - } - - udelay(1000000 / CONFIG_SYS_HZ); - i--; - left_to_poll--; - } - left_to_poll = PHONE_CONSOLE_POLL_HZ; - - return 0; -} diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c deleted file mode 100644 index 2c25ffe8d1..0000000000 --- a/board/netphone/phone_console.c +++ /dev/null @@ -1,1128 +0,0 @@ -/* - * (C) Copyright 2004 Intracom S.A. - * Pantelis Antoniou - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * phone_console.c - * - * A phone based console - * - * Virtual display of 80x24 characters. - * The actual display is much smaller and panned to show the virtual one. - * Input is made by a numeric keypad utilizing the input method of - * mobile phones. Sorry no T9 lexicons... - * - */ - -#include - -#include -#include -#include - -#include - -/*************************************************************************************************/ - -#define ROWS 24 -#define COLS 80 - -#define REFRESH_HZ (CONFIG_SYS_HZ/50) /* refresh every 20ms */ -#define BLINK_HZ (CONFIG_SYS_HZ/2) /* cursor blink every 500ms */ - -/*************************************************************************************************/ - -#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat -#define DISPLAY_BACKLIT_MASK 0x0010 - -/*************************************************************************************************/ - -#define KP_STABLE_HZ (CONFIG_SYS_HZ/100) /* stable for 10ms */ -#define KP_REPEAT_DELAY_HZ (CONFIG_SYS_HZ/4) /* delay before repeat 250ms */ -#define KP_REPEAT_HZ (CONFIG_SYS_HZ/20) /* repeat every 50ms */ -#define KP_FORCE_DELAY_HZ (CONFIG_SYS_HZ/2) /* key was force pressed */ -#define KP_IDLE_DELAY_HZ (CONFIG_SYS_HZ/2) /* key was released and idle */ - -#if CONFIG_NETPHONE_VERSION == 1 -#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_RXD_MASK 0x0008 - -#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_TXD_MASK 0x0004 - -#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_CLK_MASK 0x0001 -#elif CONFIG_NETPHONE_VERSION == 2 -#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_RXD_MASK 0x00000008 - -#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_TXD_MASK 0x00000004 - -#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_CLK_MASK 0x00000002 -#endif - -#define KP_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) -#define KP_CS_MASK 0x00000010 - -#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK) - -#define KP_SPI_TXD(x) \ - do { \ - if (x) \ - KP_SPI_TXD_PORT |= KP_SPI_TXD_MASK; \ - else \ - KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \ - } while(0) - -#define KP_SPI_CLK(x) \ - do { \ - if (x) \ - KP_SPI_CLK_PORT |= KP_SPI_CLK_MASK; \ - else \ - KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \ - } while(0) - -#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK) - -#define KP_SPI_BIT_DELAY() /* no delay */ - -#define KP_CS(x) \ - do { \ - if (x) \ - KP_CS_PORT |= KP_CS_MASK; \ - else \ - KP_CS_PORT &= ~KP_CS_MASK; \ - } while(0) - -#define KP_ROWS 7 -#define KP_COLS 4 - -#define KP_ROWS_MASK ((1 << KP_ROWS) - 1) -#define KP_COLS_MASK ((1 << KP_COLS) - 1) - -#define SCAN 0 -#define SCAN_FILTER 1 -#define SCAN_COL 2 -#define SCAN_COL_FILTER 3 -#define PRESSED 4 - -#define KP_F1 0 /* leftmost dot (tab) */ -#define KP_F2 1 /* middle left dot */ -#define KP_F3 2 /* up */ -#define KP_F4 3 /* middle right dot */ -#define KP_F5 4 /* rightmost dot */ -#define KP_F6 5 /* C */ -#define KP_F7 6 /* left */ -#define KP_F8 7 /* down */ -#define KP_F9 8 /* right */ -#define KP_F10 9 /* enter */ -#define KP_F11 10 /* R */ -#define KP_F12 11 /* save */ -#define KP_F13 12 /* redial */ -#define KP_F14 13 /* speaker */ -#define KP_F15 14 /* unused */ -#define KP_F16 15 /* unused */ - -#define KP_RELEASE -1 /* key depressed */ -#define KP_FORCE -2 /* key was pressed for more than force hz */ -#define KP_IDLE -3 /* key was released and idle */ - -#define KP_1 '1' -#define KP_2 '2' -#define KP_3 '3' -#define KP_4 '4' -#define KP_5 '5' -#define KP_6 '6' -#define KP_7 '7' -#define KP_8 '8' -#define KP_9 '9' -#define KP_0 '0' -#define KP_STAR '*' -#define KP_HASH '#' - -/*************************************************************************************************/ - -static int curs_disabled; -static int curs_col, curs_row; -static int disp_col, disp_row; - -static int width, height; - -/* the simulated vty buffer */ -static char vty_buf[ROWS * COLS]; -static char last_visible_buf[ROWS * COLS]; /* worst case */ -static char *last_visible_curs_ptr; -static int last_visible_curs_rev; -static int blinked_state; -static int last_input_mode; -static int refresh_time; -static int blink_time; -static char last_fast_punct; - -/*************************************************************************************************/ - -#define IM_SMALL 0 -#define IM_CAPITAL 1 -#define IM_NUMBER 2 - -static int input_mode; -static char fast_punct; -static int tab_indicator; -static const char *fast_punct_list = ",.:;*"; - -static const char *input_mode_txt[] = { "abc", "ABC", "123" }; - -static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|"; -static const char *whspace = " 0\n"; -/* per mode character select (for 2-9) */ -static const char *digits_sel[2][8] = { - { /* small */ - "abc2", /* 2 */ - "def3", /* 3 */ - "ghi4", /* 4 */ - "jkl5", /* 5 */ - "mno6", /* 6 */ - "pqrs7", /* 7 */ - "tuv8", /* 8 */ - "wxyz9", /* 9 */ - }, { /* capital */ - "ABC2", /* 2 */ - "DEF3", /* 3 */ - "GHI4", /* 4 */ - "JKL5", /* 5 */ - "MNO6", /* 6 */ - "PQRS7", /* 7 */ - "TUV8", /* 8 */ - "WXYZ9", /* 9 */ - } -}; - -/*****************************************************************************/ - -static void update(void); -static void ensure_visible(int col, int row, int dx, int dy); - -static void console_init(void) -{ - curs_disabled = 0; - curs_col = 0; - curs_row = 0; - - disp_col = 0; - disp_row = 0; - - input_mode = IM_SMALL; - fast_punct = ','; - last_fast_punct = '\0'; - refresh_time = REFRESH_HZ; - blink_time = BLINK_HZ; - - memset(vty_buf, ' ', sizeof(vty_buf)); - - memset(last_visible_buf, ' ', sizeof(last_visible_buf)); - last_visible_curs_ptr = NULL; - last_input_mode = -1; - last_visible_curs_rev = 0; - - blinked_state = 0; - - sed156x_init(); - width = sed156x_text_width; - height = sed156x_text_height - 1; - - tab_indicator = 0; -} - -/*****************************************************************************/ - -void phone_putc(const char c); - -/*****************************************************************************/ - -static int queued_char = -1; -static int enabled = 0; - -/*****************************************************************************/ - -/* flush buffers */ -int phone_start(void) -{ - console_init(); - - update(); - sed156x_sync(); - - enabled = 1; - queued_char = 'U' - '@'; - - /* backlit on */ - DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK; - - return 0; -} - -int phone_stop(void) -{ - enabled = 0; - - sed156x_clear(); - sed156x_sync(); - - /* backlit off */ - DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK; - - return 0; -} - -void phone_puts(const char *s) -{ - int count = strlen(s); - - while (count--) - phone_putc(*s++); -} - -int phone_tstc(void) -{ - return queued_char >= 0 ? 1 : 0; -} - -int phone_getc(void) -{ - int r; - - if (queued_char < 0) - return -1; - - r = queued_char; - queued_char = -1; - - return r; -} - -/*****************************************************************************/ - -int drv_phone_init(void) -{ - struct stdio_dev console_dev; - - console_init(); - - memset(&console_dev, 0, sizeof(console_dev)); - strcpy(console_dev.name, "phone"); - console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ - console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - console_dev.start = phone_start; - console_dev.stop = phone_stop; - console_dev.putc = phone_putc; /* 'putc' function */ - console_dev.puts = phone_puts; /* 'puts' function */ - console_dev.tstc = phone_tstc; /* 'tstc' function */ - console_dev.getc = phone_getc; /* 'getc' function */ - - if (stdio_register(&console_dev) == 0) - return 1; - - return 0; -} - -static int use_me; - -int drv_phone_use_me(void) -{ - return use_me; -} - -static void kp_do_poll(void); - -void phone_console_do_poll(void) -{ - int i, x, y; - - kp_do_poll(); - - if (enabled) { - /* do the blink */ - blink_time -= PHONE_CONSOLE_POLL_HZ; - if (blink_time <= 0) { - blink_time += BLINK_HZ; - if (last_visible_curs_ptr) { - i = last_visible_curs_ptr - last_visible_buf; - x = i % width; y = i / width; - sed156x_reverse_at(x, y, 1); - last_visible_curs_rev ^= 1; - } - } - - /* do the refresh */ - refresh_time -= PHONE_CONSOLE_POLL_HZ; - if (refresh_time <= 0) { - refresh_time += REFRESH_HZ; - sed156x_sync(); - } - } - -} - -static int last_scancode = -1; -static int forced_scancode = 0; -static int input_state = -1; -static int input_scancode = -1; -static int input_selected_char = -1; -static char input_covered_char; - -static void putchar_at_cursor(char c) -{ - vty_buf[curs_row * COLS + curs_col] = c; - ensure_visible(curs_col, curs_row, 1, 1); -} - -static char getchar_at_cursor(void) -{ - return vty_buf[curs_row * COLS + curs_col]; -} - -static void queue_input_char(char c) -{ - if (c <= 0) - return; - - queued_char = c; -} - -static void terminate_input(void) -{ - if (input_state < 0) - return; - - if (input_selected_char >= 0) - queue_input_char(input_selected_char); - - input_state = -1; - input_selected_char = -1; - putchar_at_cursor(input_covered_char); - - curs_disabled = 0; - blink_time = BLINK_HZ; - update(); -} - -static void handle_enabled_scancode(int scancode) -{ - char c; - int new_disp_col, new_disp_row; - const char *sel; - - - switch (scancode) { - - /* key was released */ - case KP_RELEASE: - forced_scancode = 0; - break; - - /* key was forced */ - case KP_FORCE: - - switch (last_scancode) { - case '#': - if (input_mode == IM_NUMBER) { - input_mode = IM_CAPITAL; - /* queue backspace to erase # */ - queue_input_char('\b'); - } else { - input_mode = IM_NUMBER; - fast_punct = '*'; - } - update(); - break; - - case '0': case '1': - case '2': case '3': case '4': case '5': - case '6': case '7': case '8': case '9': - - if (input_state < 0) - break; - - input_selected_char = last_scancode; - putchar_at_cursor((char)input_selected_char); - terminate_input(); - - break; - - default: - break; - } - - break; - - /* release and idle */ - case KP_IDLE: - input_scancode = -1; - if (input_state < 0) - break; - terminate_input(); - break; - - /* change input mode */ - case '#': - if (last_scancode == '#') /* no repeat */ - break; - - if (input_mode == IM_NUMBER) { - input_scancode = scancode; - input_state = 0; - input_selected_char = scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - break; - } - - if (input_mode == IM_SMALL) - input_mode = IM_CAPITAL; - else - input_mode = IM_SMALL; - - update(); - break; - - case '*': - /* no repeat */ - if (last_scancode == scancode) - break; - - if (input_state >= 0) - terminate_input(); - - input_scancode = fast_punct; - input_state = 0; - input_selected_char = input_scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - - break; - - case '0': case '1': - case '2': case '3': case '4': case '5': - case '6': case '7': case '8': case '9': - - /* no repeat */ - if (last_scancode == scancode) - break; - - if (input_mode == IM_NUMBER) { - input_scancode = scancode; - input_state = 0; - input_selected_char = scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - break; - } - - if (input_state >= 0 && input_scancode != scancode) - terminate_input(); - - if (input_state < 0) { - curs_disabled = 1; - input_scancode = scancode; - input_state = 0; - input_covered_char = getchar_at_cursor(); - } else - input_state++; - - if (scancode == '0') - sel = whspace; - else if (scancode == '1') - sel = punct; - else - sel = digits_sel[input_mode][scancode - '2']; - c = *(sel + input_state); - if (c == '\0') { - input_state = 0; - c = *sel; - } - - input_selected_char = (int)c; - putchar_at_cursor((char)input_selected_char); - update(); - - break; - - /* move visible display */ - case KP_F3: case KP_F8: case KP_F7: case KP_F9: - - new_disp_col = disp_col; - new_disp_row = disp_row; - - switch (scancode) { - /* up */ - case KP_F3: - if (new_disp_row <= 0) - break; - new_disp_row--; - break; - - /* down */ - case KP_F8: - if (new_disp_row >= ROWS - height) - break; - new_disp_row++; - break; - - /* left */ - case KP_F7: - if (new_disp_col <= 0) - break; - new_disp_col--; - break; - - /* right */ - case KP_F9: - if (new_disp_col >= COLS - width) - break; - new_disp_col++; - break; - } - - /* no change? */ - if (disp_col == new_disp_col && disp_row == new_disp_row) - break; - - disp_col = new_disp_col; - disp_row = new_disp_row; - update(); - - break; - - case KP_F6: /* backspace */ - /* inputing something; no backspace sent, just cancel input */ - if (input_state >= 0) { - input_selected_char = -1; /* cancel */ - terminate_input(); - break; - } - queue_input_char('\b'); - break; - - case KP_F10: /* enter */ - /* inputing something; first cancel input */ - if (input_state >= 0) - terminate_input(); - queue_input_char('\r'); - break; - - case KP_F11: /* R -> Ctrl-C (abort) */ - if (input_state >= 0) - terminate_input(); - queue_input_char('C' - 'Q'); /* ctrl-c */ - break; - - case KP_F5: /* F% -> Ctrl-U (clear line) */ - if (input_state >= 0) - terminate_input(); - queue_input_char('U' - 'Q'); /* ctrl-c */ - break; - - - case KP_F1: /* tab */ - /* inputing something; first cancel input */ - if (input_state >= 0) - terminate_input(); - queue_input_char('\t'); - break; - - case KP_F2: /* change fast punct */ - sel = strchr(fast_punct_list, fast_punct); - if (sel == NULL) - sel = &fast_punct_list[0]; - sel++; - if (*sel == '\0') - sel = &fast_punct_list[0]; - fast_punct = *sel; - update(); - break; - - - } - - if (scancode != KP_FORCE && scancode != KP_IDLE) /* don't record forced or idle scancode */ - last_scancode = scancode; -} - -static void scancode_action(int scancode) -{ -#if 0 - if (scancode == KP_RELEASE) - printf(" RELEASE\n"); - else if (scancode == KP_FORCE) - printf(" FORCE\n"); - else if (scancode == KP_IDLE) - printf(" IDLE\n"); - else if (scancode < 32) - printf(" F%d", scancode + 1); - else - printf(" %c", (char)scancode); - printf("\n"); -#endif - - if (enabled) { - handle_enabled_scancode(scancode); - return; - } - - if (scancode == KP_FORCE && last_scancode == '*') - use_me = 1; - - last_scancode = scancode; -} - -/**************************************************************************************/ - -/* update the display; make sure to update only the differences */ -static void update(void) -{ - int i; - char *s, *e, *t, *r, *b, *cp; - - if (input_mode != last_input_mode) - sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3); - - if (tab_indicator == 0) { - sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2); - tab_indicator = 1; - } - - if (fast_punct != last_fast_punct) - sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1); - - if (curs_disabled || - curs_col < disp_col || curs_col >= (disp_col + width) || - curs_row < disp_row || curs_row >= (disp_row + height)) { - cp = NULL; - } else - cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col); - - - /* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */ - - /* clear previous cursor */ - if (last_visible_curs_ptr && last_visible_curs_rev == 0) { - i = last_visible_curs_ptr - last_visible_buf; - sed156x_reverse_at(i % width, i / width, 1); - } - - b = vty_buf + disp_row * COLS + disp_col; - t = last_visible_buf; - for (i = 0; i < height; i++) { - s = b; - e = b + width; - /* update only the differences */ - do { - while (s < e && *s == *t) { - s++; - t++; - } - if (s == e) /* no more */ - break; - - /* find run */ - r = s; - while (s < e && *s != *t) - *t++ = *s++; - - /* and update */ - sed156x_output_at(r - b, i, r, s - r); - - } while (s < e); - - b += COLS; - } - - /* set cursor */ - if (cp) { - last_visible_curs_ptr = cp; - i = last_visible_curs_ptr - last_visible_buf; - sed156x_reverse_at(i % width, i / width, 1); - last_visible_curs_rev = 0; - } else { - last_visible_curs_ptr = NULL; - } - - last_input_mode = input_mode; - last_fast_punct = fast_punct; -} - -/* ensure visibility; the trick is to minimize the screen movement */ -static void ensure_visible(int col, int row, int dx, int dy) -{ - int x1, y1, x2, y2, a1, b1, a2, b2; - - /* clamp visible region */ - if (col < 0) { - dx -= col; - col = 0; - if (dx <= 0) - dx = 1; - } - - if (row < 0) { - dy -= row; - row = 0; - if (dy <= 0) - dy = 1; - } - - if (col + dx > COLS) - dx = COLS - col; - - if (row + dy > ROWS) - dy = ROWS - row; - - - /* move to easier to use vars */ - x1 = disp_col; y1 = disp_row; - x2 = x1 + width; y2 = y1 + height; - a1 = col; b1 = row; - a2 = a1 + dx; b2 = b1 + dy; - - /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ - - if (a2 > x2) { - /* move to the right */ - x2 = a2; - x1 = x2 - width; - if (x1 < 0) { - x1 = 0; - x2 = width; - } - } else if (a1 < x1) { - /* move to the left */ - x1 = a1; - x2 = x1 + width; - if (x2 > COLS) { - x2 = COLS; - x1 = x2 - width; - } - } - - if (b2 > y2) { - /* move down */ - y2 = b2; - y1 = y2 - height; - if (y1 < 0) { - y1 = 0; - y2 = height; - } - } else if (b1 < y1) { - /* move up */ - y1 = b1; - y2 = y1 + width; - if (y2 > ROWS) { - y2 = ROWS; - y1 = y2 - height; - } - } - - /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ - - /* no movement? */ - if (disp_col == x1 && disp_row == y1) - return; - - disp_col = x1; - disp_row = y1; -} - -/**************************************************************************************/ - -static void newline(void) -{ - curs_col = 0; - if (curs_row + 1 < ROWS) - curs_row++; - else { - memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1)); - memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS); - } -} - -void phone_putc(const char c) -{ - int i; - - if (input_mode != -1) { - input_selected_char = -1; - terminate_input(); - } - - curs_disabled = 1; - update(); - - blink_time = BLINK_HZ; - - switch (c) { - case '\a': /* ignore bell */ - case '\r': /* ignore carriage return */ - break; - - case '\n': /* next line */ - newline(); - ensure_visible(curs_col, curs_row, 1, 1); - break; - - case 9: /* tab 8 */ - /* move to tab */ - i = curs_col; - i |= 0x0008; - i &= ~0x0007; - - if (i < COLS) - curs_col = i; - else - newline(); - - ensure_visible(curs_col, curs_row, 1, 1); - break; - - case 8: /* backspace */ - if (curs_col <= 0) - break; - curs_col--; - - /* make sure that we see a couple of characters before */ - if (curs_col > 4) - ensure_visible(curs_col - 4, curs_row, 4, 1); - else - ensure_visible(curs_col, curs_row, 1, 1); - - break; - - default: /* draw the char */ - putchar_at_cursor(c); - - /* - * check for newline - */ - if (curs_col + 1 < COLS) - curs_col++; - else - newline(); - - ensure_visible(curs_col, curs_row, 1, 1); - - break; - } - - curs_disabled = 0; - blink_time = BLINK_HZ; - update(); -} - -/**************************************************************************************/ - -static inline unsigned int kp_transfer(unsigned int val) -{ - unsigned int rx; - int b; - - rx = 0; b = 8; - while (--b >= 0) { - KP_SPI_TXD(val & 0x80); - val <<= 1; - KP_SPI_CLK_TOGGLE(); - KP_SPI_BIT_DELAY(); - rx <<= 1; - if (KP_SPI_RXD()) - rx |= 1; - KP_SPI_CLK_TOGGLE(); - KP_SPI_BIT_DELAY(); - } - - return rx; -} - -unsigned int kp_data_transfer(unsigned int val) -{ - KP_SPI_CLK(1); - KP_CS(0); - val = kp_transfer(val); - KP_CS(1); - - return val; -} - -unsigned int kp_get_col_mask(unsigned int row_mask) -{ - unsigned int val, col_mask; - - val = 0x80 | (row_mask & 0x7F); - (void)kp_data_transfer(val); -#if CONFIG_NETPHONE_VERSION == 1 - col_mask = kp_data_transfer(val) & 0x0F; -#elif CONFIG_NETPHONE_VERSION == 2 - col_mask = ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & 0x0f; - /* XXX FUCK FUCK FUCK FUCK FUCK!!!! */ - col_mask = ((col_mask & 0x08) >> 3) | /* BKBR1 */ - ((col_mask & 0x04) << 1) | /* BKBR2 */ - (col_mask & 0x02) | /* BKBR3 */ - ((col_mask & 0x01) << 2); /* BKBR4 */ - -#endif - /* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */ - - return col_mask; -} - -/**************************************************************************************/ - -static const int kp_scancodes[KP_ROWS * KP_COLS] = { - KP_F1, KP_F3, KP_F4, KP_F2, - KP_F6, KP_F8, KP_F9, KP_F7, - KP_1, KP_3, KP_F11, KP_2, - KP_4, KP_6, KP_F12, KP_5, - KP_7, KP_9, KP_F13, KP_8, - KP_STAR, KP_HASH, KP_F14, KP_0, - KP_F5, KP_F15, KP_F16, KP_F10, -}; - -static const int kp_repeats[KP_ROWS * KP_COLS] = { - 0, 1, 0, 0, - 0, 1, 1, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 0, 0, 0, 1, -}; - -static int kp_state = SCAN; -static int kp_last_col_mask; -static int kp_cur_row, kp_cur_col; -static int kp_scancode; -static int kp_stable; -static int kp_repeat; -static int kp_repeat_time; -static int kp_force_time; -static int kp_idle_time; - -static void kp_do_poll(void) -{ - unsigned int col_mask; - int col; - - switch (kp_state) { - case SCAN: - if (kp_idle_time > 0) { - kp_idle_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_idle_time <= 0) - scancode_action(KP_IDLE); - } - - col_mask = kp_get_col_mask(KP_ROWS_MASK); - if (col_mask == KP_COLS_MASK) - break; /* nothing */ - kp_last_col_mask = col_mask; - kp_stable = 0; - kp_state = SCAN_FILTER; - break; - - case SCAN_FILTER: - col_mask = kp_get_col_mask(KP_ROWS_MASK); - if (col_mask != kp_last_col_mask) { - kp_state = SCAN; - break; - } - - kp_stable += PHONE_CONSOLE_POLL_HZ; - if (kp_stable < KP_STABLE_HZ) - break; - - kp_cur_row = 0; - kp_stable = 0; - kp_state = SCAN_COL; - - (void)kp_get_col_mask(1 << kp_cur_row); - break; - - case SCAN_COL: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask == KP_COLS_MASK) { - if (++kp_cur_row >= KP_ROWS) { - kp_state = SCAN; - break; - } - kp_get_col_mask(1 << kp_cur_row); - break; - } - kp_last_col_mask = col_mask; - kp_stable = 0; - kp_state = SCAN_COL_FILTER; - break; - - case SCAN_COL_FILTER: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) { - kp_state = SCAN; - break; - } - - kp_stable += PHONE_CONSOLE_POLL_HZ; - if (kp_stable < KP_STABLE_HZ) - break; - - for (col = 0; col < KP_COLS; col++) - if ((col_mask & (1 << col)) == 0) - break; - kp_cur_col = col; - kp_state = PRESSED; - kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col]; - kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col]; - - if (kp_repeat) - kp_repeat_time = KP_REPEAT_DELAY_HZ; - kp_force_time = KP_FORCE_DELAY_HZ; - - scancode_action(kp_scancode); - - break; - - case PRESSED: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask != kp_last_col_mask) { - kp_state = SCAN; - scancode_action(KP_RELEASE); - kp_idle_time = KP_IDLE_DELAY_HZ; - break; - } - - if (kp_repeat) { - kp_repeat_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_repeat_time <= 0) { - kp_repeat_time += KP_REPEAT_HZ; - scancode_action(kp_scancode); - } - } - - if (kp_force_time > 0) { - kp_force_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_force_time <= 0) - scancode_action(KP_FORCE); - } - - break; - } -} - -/**************************************************************************************/ - -int drv_phone_is_idle(void) -{ - return kp_state == SCAN; -} diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/netphone/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug deleted file mode 100644 index a198cf9520..0000000000 --- a/board/netphone/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netta/Makefile b/board/netta/Makefile deleted file mode 100644 index 3b5408868e..0000000000 --- a/board/netta/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/netta/codec.c b/board/netta/codec.c deleted file mode 100644 index e303aa4780..0000000000 --- a/board/netta/codec.c +++ /dev/null @@ -1,1481 +0,0 @@ -/* - * CODEC - */ - -#include -#include - -#include "mpc8xx.h" - -/***********************************************/ - -#define MAX_DUSLIC 4 - -#define NUM_CHANNELS 2 -#define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS) - -/***********************************************/ - -#define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */ -#define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */ -#define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */ -#define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */ - -#define COP_READ_CH_0 0xC5 -#define COP_READ_CH_1 0xCD -#define COP_WRITE_CH_0 0x45 -#define COP_WRITE_CH_1 0x4D - -#define POP_READ_CH_0 0xC6 -#define POP_READ_CH_1 0xCE -#define POP_WRITE_CH_0 0x46 -#define POP_WRITE_CH_1 0x4E - -#define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */ -#define RST_CMD_DUSLIC_CH_A 0x41 -#define RST_CMD_DUSLIC_CH_B 0x49 - -#define PCM_RESYNC_CMD_CH_A 0x42 -#define PCM_RESYNC_CMD_CH_B 0x4A - -#define ACTIVE_HOOK_LEV_4 0 -#define ACTIVE_HOOK_LEV_12 1 - -#define SLIC_P_NORMAL 0x01 - -/************************************************/ - -#define CODSP_WR 0x00 -#define CODSP_RD 0x80 -#define CODSP_OP 0x40 -#define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3) -#define CODSP_M(x) ((unsigned char)(x) & 7) -#define CODSP_CMD(x) ((unsigned char)(x) & 7) - -/************************************************/ - -/* command indication ops */ -#define CODSP_M_SLEEP_PWRDN 7 -#define CODSP_M_PWRDN_HIZ 0 -#define CODSP_M_ANY_ACT 2 -#define CODSP_M_RING 5 -#define CODSP_M_ACT_MET 6 -#define CODSP_M_GND_START 4 -#define CODSP_M_RING_PAUSE 1 - -/* single byte commands */ -#define CODSP_CMD_SOFT_RESET CODSP_CMD(0) -#define CODSP_CMD_RESET_CH CODSP_CMD(1) -#define CODSP_CMD_RESYNC CODSP_CMD(2) - -/* two byte commands */ -#define CODSP_CMD_SOP CODSP_CMD(4) -#define CODSP_CMD_COP CODSP_CMD(5) -#define CODSP_CMD_POP CODSP_CMD(6) - -/************************************************/ - -/* read as 4-bytes */ -#define CODSP_INTREG_INT_CH 0x80000000 -#define CODSP_INTREG_HOOK 0x40000000 -#define CODSP_INTREG_GNDK 0x20000000 -#define CODSP_INTREG_GNDP 0x10000000 -#define CODSP_INTREG_ICON 0x08000000 -#define CODSP_INTREG_VRTLIM 0x04000000 -#define CODSP_INTREG_OTEMP 0x02000000 -#define CODSP_INTREG_SYNC_FAIL 0x01000000 -#define CODSP_INTREG_LM_THRES 0x00800000 -#define CODSP_INTREG_READY 0x00400000 -#define CODSP_INTREG_RSTAT 0x00200000 -#define CODSP_INTREG_LM_OK 0x00100000 -#define CODSP_INTREG_IO4_DU 0x00080000 -#define CODSP_INTREG_IO3_DU 0x00040000 -#define CODSP_INTREG_IO2_DU 0x00020000 -#define CODSP_INTREG_IO1_DU 0x00010000 -#define CODSP_INTREG_DTMF_OK 0x00008000 -#define CODSP_INTREG_DTMF_KEY4 0x00004000 -#define CODSP_INTREG_DTMF_KEY3 0x00002000 -#define CODSP_INTREG_DTMF_KEY2 0x00001000 -#define CODSP_INTREG_DTMF_KEY1 0x00000800 -#define CODSP_INTREG_DTMF_KEY0 0x00000400 -#define CODSP_INTREG_UTDR_OK 0x00000200 -#define CODSP_INTREG_UTDX_OK 0x00000100 -#define CODSP_INTREG_EDSP_FAIL 0x00000080 -#define CODSP_INTREG_CIS_BOF 0x00000008 -#define CODSP_INTREG_CIS_BUF 0x00000004 -#define CODSP_INTREG_CIS_REQ 0x00000002 -#define CODSP_INTREG_CIS_ACT 0x00000001 - -/************************************************/ - -/* ======== SOP REG ADDRESSES =======*/ - -#define REVISION_ADDR 0x00 -#define PCMC1_ADDR 0x05 -#define XCR_ADDR 0x06 -#define INTREG1_ADDR 0x07 -#define INTREG2_ADDR 0x08 -#define INTREG3_ADDR 0x09 -#define INTREG4_ADDR 0x0A -#define LMRES1_ADDR 0x0D -#define MASK_ADDR 0x11 -#define IOCTL3_ADDR 0x14 -#define BCR1_ADDR 0x15 -#define BCR2_ADDR 0x16 -#define BCR3_ADDR 0x17 -#define BCR4_ADDR 0x18 -#define BCR5_ADDR 0x19 -#define DSCR_ADDR 0x1A -#define LMCR1_ADDR 0x1C -#define LMCR2_ADDR 0x1D -#define LMCR3_ADDR 0x1E -#define OFR1_ADDR 0x1F -#define PCMR1_ADDR 0x21 -#define PCMX1_ADDR 0x25 -#define TSTR3_ADDR 0x2B -#define TSTR4_ADDR 0x2C -#define TSTR5_ADDR 0x2D - -/* ========= POP REG ADDRESSES ========*/ - -#define CIS_DAT_ADDR 0x00 - -#define LEC_LEN_ADDR 0x3A -#define LEC_POWR_ADDR 0x3B -#define LEC_DELP_ADDR 0x3C -#define LEC_DELQ_ADDR 0x3D -#define LEC_GAIN_XI_ADDR 0x3E -#define LEC_GAIN_RI_ADDR 0x3F -#define LEC_GAIN_XO_ADDR 0x40 -#define LEC_RES_1_ADDR 0x41 -#define LEC_RES_2_ADDR 0x42 - -#define NLP_POW_LPF_ADDR 0x30 -#define NLP_POW_LPS_ADDR 0x31 -#define NLP_BN_LEV_X_ADDR 0x32 -#define NLP_BN_LEV_R_ADDR 0x33 -#define NLP_BN_INC_ADDR 0x34 -#define NLP_BN_DEC_ADDR 0x35 -#define NLP_BN_MAX_ADDR 0x36 -#define NLP_BN_ADJ_ADDR 0x37 -#define NLP_RE_MIN_ERLL_ADDR 0x38 -#define NLP_RE_EST_ERLL_ADDR 0x39 -#define NLP_SD_LEV_X_ADDR 0x3A -#define NLP_SD_LEV_R_ADDR 0x3B -#define NLP_SD_LEV_BN_ADDR 0x3C -#define NLP_SD_LEV_RE_ADDR 0x3D -#define NLP_SD_OT_DT_ADDR 0x3E -#define NLP_ERL_LIN_LP_ADDR 0x3F -#define NLP_ERL_LEC_LP_ADDR 0x40 -#define NLP_CT_LEV_RE_ADDR 0x41 -#define NLP_CTRL_ADDR 0x42 - -#define UTD_CF_H_ADDR 0x4B -#define UTD_CF_L_ADDR 0x4C -#define UTD_BW_H_ADDR 0x4D -#define UTD_BW_L_ADDR 0x4E -#define UTD_NLEV_ADDR 0x4F -#define UTD_SLEV_H_ADDR 0x50 -#define UTD_SLEV_L_ADDR 0x51 -#define UTD_DELT_ADDR 0x52 -#define UTD_RBRK_ADDR 0x53 -#define UTD_RTIME_ADDR 0x54 -#define UTD_EBRK_ADDR 0x55 -#define UTD_ETIME_ADDR 0x56 - -#define DTMF_LEV_ADDR 0x30 -#define DTMF_TWI_ADDR 0x31 -#define DTMF_NCF_H_ADDR 0x32 -#define DTMF_NCF_L_ADDR 0x33 -#define DTMF_NBW_H_ADDR 0x34 -#define DTMF_NBW_L_ADDR 0x35 -#define DTMF_GAIN_ADDR 0x36 -#define DTMF_RES1_ADDR 0x37 -#define DTMF_RES2_ADDR 0x38 -#define DTMF_RES3_ADDR 0x39 - -#define CIS_LEV_H_ADDR 0x43 -#define CIS_LEV_L_ADDR 0x44 -#define CIS_BRS_ADDR 0x45 -#define CIS_SEIZ_H_ADDR 0x46 -#define CIS_SEIZ_L_ADDR 0x47 -#define CIS_MARK_H_ADDR 0x48 -#define CIS_MARK_L_ADDR 0x49 -#define CIS_LEC_MODE_ADDR 0x4A - -/*=====================================*/ - -#define HOOK_LEV_ACT_START_ADDR 0x89 -#define RO1_START_ADDR 0x70 -#define RO2_START_ADDR 0x95 -#define RO3_START_ADDR 0x96 - -#define TG1_FREQ_START_ADDR 0x38 -#define TG1_GAIN_START_ADDR 0x39 -#define TG1_BANDPASS_START_ADDR 0x3B -#define TG1_BANDPASS_END_ADDR 0x3D - -#define TG2_FREQ_START_ADDR 0x40 -#define TG2_GAIN_START_ADDR 0x41 -#define TG2_BANDPASS_START_ADDR 0x43 -#define TG2_BANDPASS_END_ADDR 0x45 - -/*====================================*/ - -#define PCM_HW_B 0x80 -#define PCM_HW_A 0x00 -#define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */ -#define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */ -#define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */ - -#define RX_LEV_ADDR 0x28 -#define TX_LEV_ADDR 0x30 -#define Ik1_ADDR 0x83 - -#define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */ -#define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */ -#define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */ - -/* Mark the start byte of Duslic parameters that we use with configurator */ -#define Ik1_START_BYTE 3 -#define RX_LEV_START_BYTE 0 -#define TX_LEV_START_BYTE 0 - -/************************************************/ - -#define INTREG4_CIS_ACT (1 << 0) - -#define BCR1_SLEEP 0x20 -#define BCR1_REVPOL 0x10 -#define BCR1_ACTR 0x08 -#define BCR1_ACTL 0x04 -#define BCR1_SLIC_MASK 0x03 - -#define BCR2_HARD_POL_REV 0x40 -#define BCR2_TTX 0x20 -#define BCR2_TTX_12K 0x10 -#define BCR2_HIMAN 0x08 -#define BCR2_PDOT 0x01 - -#define BCR3_PCMX_EN (1 << 4) - -#define BCR5_DTMF_EN (1 << 0) -#define BCR5_DTMF_SRC (1 << 1) -#define BCR5_LEC_EN (1 << 2) -#define BCR5_LEC_OUT (1 << 3) -#define BCR5_CIS_EN (1 << 4) -#define BCR5_CIS_AUTO (1 << 5) -#define BCR5_UTDX_EN (1 << 6) -#define BCR5_UTDR_EN (1 << 7) - -#define DSCR_TG1_EN (1 << 0) -#define DSCR_TG2_EN (1 << 1) -#define DSCR_PTG (1 << 2) -#define DSCR_COR8 (1 << 3) -#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4) - -#define CIS_LEC_MODE_CIS_V23 (1 << 0) -#define CIS_LEC_MODE_CIS_FRM (1 << 1) -#define CIS_LEC_MODE_NLP_EN (1 << 2) -#define CIS_LEC_MODE_UTDR_SUM (1 << 4) -#define CIS_LEC_MODE_UTDX_SUM (1 << 5) -#define CIS_LEC_MODE_LEC_FREEZE (1 << 6) -#define CIS_LEC_MODE_LEC_ADAPT (1 << 7) - -#define TSTR4_COR_64 (1 << 5) - -#define TSTR3_AC_DLB_8K (1 << 2) -#define TSTR3_AC_DLB_32K (1 << 3) -#define TSTR3_AC_DLB_4M (1 << 5) - - -#define LMCR1_TEST_EN (1 << 7) -#define LMCR1_LM_EN (1 << 6) -#define LMCR1_LM_THM (1 << 5) -#define LMCR1_LM_ONCE (1 << 2) -#define LMCR1_LM_MASK (1 << 1) - -#define LMCR2_LM_RECT (1 << 5) -#define LMCR2_LM_SEL_VDD 0x0D -#define LMCR2_LM_SEL_IO3 0x0A -#define LMCR2_LM_SEL_IO4 0x0B -#define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F - -#define LMCR3_RTR_SEL (1 << 6) - -#define LMCR3_RNG_OFFSET_NONE 0x00 -#define LMCR3_RNG_OFFSET_1 0x01 -#define LMCR3_RNG_OFFSET_2 0x02 -#define LMCR3_RNG_OFFSET_3 0x03 - -#define TSTR5_DC_HOLD (1 << 3) - -/************************************************/ - -#define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */ -#define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */ -#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */ -#define DIVIDER_RATIO_ACCURx100 (22 * 100) -#define V_AD_x10000 10834L /* VAD = 1.0834 */ -#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */ -#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */ - -#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/ -#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */ -#define K_INTDC_RECT_OFF 2 /* 2^2 */ -#define RNG_FREQ 25 -#define SAMPLING_FREQ (2000L) -#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */ -#define HOOK_THRESH_RING_START_ADDR 0x8B -#define RING_PARAMS_START_ADDR 0x70 - -#define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */ -#define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */ -#define MAX_V_RING_MEANx100 50 -#define TARGET_V_RING_RMSx100 2720 -#define V_RMS_RING_MAX_DIFFx100 250 - -#define LM_OK_SRC_IRG_2 (1 << 4) - -/************************************************/ - -#define PORTB (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define PORTC (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define PORTD (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) - -#define _PORTD_SET(mask, state) \ - do { \ - if (state) \ - PORTD |= mask; \ - else \ - PORTD &= ~mask; \ - } while (0) - -#define _PORTB_SET(mask, state) \ - do { \ - if (state) \ - PORTB |= mask; \ - else \ - PORTB &= ~mask; \ - } while (0) - -#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0) -#define _PORTB_GET(mask) (!!(PORTB & mask)) - -#define _PORTC_GET(mask) (!!(PORTC & mask)) - -/* port B */ -#define SPI_RXD (1 << (31 - 28)) -#define SPI_TXD (1 << (31 - 29)) -#define SPI_CLK (1 << (31 - 30)) - -/* port C */ -#define COM_HOOK1 (1 << (15 - 9)) -#define COM_HOOK2 (1 << (15 - 10)) - -#ifndef CONFIG_NETTA_SWAPHOOK - -#define COM_HOOK3 (1 << (15 - 11)) -#define COM_HOOK4 (1 << (15 - 12)) - -#else - -#define COM_HOOK3 (1 << (15 - 12)) -#define COM_HOOK4 (1 << (15 - 11)) - -#endif - -/* port D */ -#define SPIENC1 (1 << (15 - 9)) -#define SPIENC2 (1 << (15 - 10)) -#define SPIENC3 (1 << (15 - 11)) -#define SPIENC4 (1 << (15 - 14)) - -#define SPI_DELAY() udelay(1) - -static inline unsigned int __SPI_Transfer(unsigned int tx) -{ - unsigned int rx; - int b; - - rx = 0; b = 8; - while (--b >= 0) { - _PORTB_SET(SPI_TXD, tx & 0x80); - tx <<= 1; - _PORTB_TGL(SPI_CLK); - SPI_DELAY(); - rx <<= 1; - rx |= _PORTB_GET(SPI_RXD); - _PORTB_TGL(SPI_CLK); - SPI_DELAY(); - } - - return rx; -} - -static const char *codsp_dtmf_map = "D1234567890*#ABC"; - -static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 }; -static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 }; - -static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen) -{ - unsigned int rx; - int i; - - /* just some sanity checks */ - if (cmd == 0 || cmdlen < 0) - return -1; - - _PORTD_SET(spienc_mask_tab[duslic_id], 0); - - /* first 2 bytes are without response */ - i = 2; - while (i-- > 0 && cmdlen-- > 0) - __SPI_Transfer(*cmd++); - - while (cmdlen-- > 0) { - rx = __SPI_Transfer(*cmd++); - if (res != 0 && reslen-- > 0) - *res++ = (unsigned char)rx; - } - if (res != 0) { - while (reslen-- > 0) - *res++ = __SPI_Transfer(0xFF); - } - - _PORTD_SET(spienc_mask_tab[duslic_id], 1); - - return 0; -} - -/****************************************************************************/ - -void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m) -{ - unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m); - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_reset_chip(int duslic_id) -{ - static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_reset_channel(int duslic_id, int channel) -{ - unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_resync_channel(int duslic_id, int channel) -{ - unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -/****************************************************************************/ - -void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = val; - - codsp_send(duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val) -{ - unsigned char cmd[4]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = (unsigned char)(val >> 8); - cmd[3] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 4, 0, 0); -} - -void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val) -{ - unsigned char cmd[6]; - - cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = (unsigned char)(val >> 24); - cmd[3] = (unsigned char)(val >> 16); - cmd[4] = (unsigned char)(val >> 8); - cmd[5] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 6, 0, 0); -} - -unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[3]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 2); - - return res[1]; -} - -unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 3); - - return ((unsigned short)res[1] << 8) | res[2]; -} - -unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[5]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 5); - - return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4]; -} - -/****************************************************************************/ - -void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block) -{ - unsigned char cmd[10]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - memcpy(cmd + 2, block, 8); - codsp_send(duslic_id, cmd, 10, 0, 0); -} - -void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - cmd[2] = val; - codsp_send(duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val) -{ - unsigned char cmd[4]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - cmd[2] = (unsigned char)(val >> 8); - cmd[3] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 4, 0, 0); -} - -void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block) -{ - unsigned char cmd[2]; - unsigned char res[9]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - codsp_send(duslic_id, cmd, 2, res, 9); - memcpy(block, res + 1, 8); -} - -unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr) -{ - unsigned char cmd[2]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - codsp_send(duslic_id, cmd, 2, res, 2); - return res[1]; -} - -unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - - codsp_send(duslic_id, cmd, 2, res, 3); - - return ((unsigned short)res[1] << 8) | res[2]; -} - -/****************************************************************************/ - -#define MAX_POP_BLOCK 50 - -void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr, - const unsigned char *block, int len) -{ - unsigned char cmd[2 + MAX_POP_BLOCK]; - - if (len > MAX_POP_BLOCK) /* truncate */ - len = MAX_POP_BLOCK; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = addr; - memcpy (cmd + 2, block, len); - codsp_send (duslic_id, cmd, 2 + len, 0, 0); -} - -void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno, - unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = val; - - codsp_send (duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno, - unsigned short val) -{ - unsigned char cmd[4]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = (unsigned char) (val >> 8); - cmd[3] = (unsigned char) val; - - codsp_send (duslic_id, cmd, 4, 0, 0); -} - -void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno, - unsigned int val) -{ - unsigned char cmd[6]; - - cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = (unsigned char) (val >> 24); - cmd[3] = (unsigned char) (val >> 16); - cmd[4] = (unsigned char) (val >> 8); - cmd[5] = (unsigned char) val; - - codsp_send (duslic_id, cmd, 6, 0, 0); -} - -unsigned char codsp_read_pop_char (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[3]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 2); - - return res[1]; -} - -unsigned short codsp_read_pop_short (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 3); - - return ((unsigned short) res[1] << 8) | res[2]; -} - -unsigned int codsp_read_pop_int (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[5]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 5); - - return (((unsigned int) res[1] << 24) | - ((unsigned int) res[2] << 16) | - ((unsigned int) res[3] << 8) | - res[4] ); -} -/****************************************************************************/ - -struct _coeffs { - unsigned char addr; - unsigned char values[8]; -}; - -struct _coeffs ac_coeffs[11] = { - { 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */ - { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */ - { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */ - { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */ - { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */ - { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */ - { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */ - { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */ - { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */ - { 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */ - { 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */ -}; - -struct _coeffs ac_coeffs_0dB[11] = { - { 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} }, - { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} }, - { 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} }, - { 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} }, - { 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} }, - { 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} }, - { 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} }, - { 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} }, - { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, - { 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} }, - { 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} } -}; - -struct _coeffs dc_coeffs[9] = { - { 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */ - { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */ - { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */ - { 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */ - { 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */ - { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */ - { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */ - { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */ - { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */ -}; - -void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size) -{ - int i; - - for (i = 0; i < tab_size; i++) - codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values); -} - -#define SS_OPEN_CIRCUIT 0 -#define SS_RING_PAUSE 1 -#define SS_ACTIVE 2 -#define SS_ACTIVE_HIGH 3 -#define SS_ACTIVE_RING 4 -#define SS_RINGING 5 -#define SS_ACTIVE_WITH_METERING 6 -#define SS_ONHOOKTRNSM 7 -#define SS_STANDBY 8 -#define SS_MAX 8 - -static void codsp_set_slic(int duslic_id, int channel, int state) -{ - unsigned char v; - - v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR); - - switch (state) { - - case SS_ACTIVE: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_ACTIVE_HIGH: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL)); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_ACTIVE_RING: - case SS_ONHOOKTRNSM: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_STANDBY: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR)); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN); - break; - - case SS_OPEN_CIRCUIT: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ); - break; - - case SS_RINGING: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING); - break; - - case SS_RING_PAUSE: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE); - break; - } -} - -const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 }; -const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 }; - -void retrieve_slic_state(int slic_id) -{ - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - - /* Retrieve the state of the SLICs */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); - - /* Program Default Hook Ring thresholds */ - codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values); - - /* Now program Hook Threshold while Ring and ac RingTrip to max values */ - codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values); - - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - udelay(40000); -} - -int wait_level_metering_finish(int duslic_id, int channel) -{ - int cnt; - - for (cnt = 0; cnt < 1000 && - (codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { } - - return cnt != 1000; -} - -int measure_on_hook_voltages(int slic_id, long *vdd, - long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v) -{ - short LM_Result, Offset_Compensation; /* Signed 16 bit */ - long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ; - unsigned char err_mask = 0; - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - int i; - - /* measure VDD */ - /* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */ - codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD); - - /* Activate Test Mode ==> To Enable DC Hold !!! */ - /* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */ - /* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ; /* VDDx100 */ - - *vdd = VDD; - - VDD_diff = VDD - TARGET_VDDx100; - - if (VDD_diff < 0) - VDD_diff = -VDD_diff; - - if (VDD_diff > VDD_MAX_DIFFx100) - err_mask |= 1; - - Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100; - - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */ - - udelay(40000); - - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - *v_oh_H = V_out; - - Vout_diff = V_out - TARGET_ONHOOK_BATH_x100; - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_OUT_BATH_MAX_DIFFx100) - err_mask |= 2; - - codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */ - - udelay(40000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - - V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - *v_oh_L = V_out; - - Vout_diff = V_out - TARGET_ONHOOK_BATL_x100; - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_OUT_BATL_MAX_DIFFx100) - err_mask |= 4; - - /* perform ring tests */ - - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE); - - /* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/ - codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz); - - /* By Default RO1 is selected when ringing RNG-OFFSET = 00 */ - - /* Now program Hook Threshold while Ring and ac RingTrip to max values */ - for(i = 0; i < sizeof(Max_HookRingTh); i++) - codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]); - - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */ - - /* select source for the levelmeter to be IO4-IO3 */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3); - - udelay(40000); - - /* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */ - codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF); - - udelay(10000); - - /* Enable LevelMeter to Integrate only once (Rectifier Disabled) */ - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */ - - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */ - - /* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */ - Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES); - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - - /* Now programm Integrator Offset Registers !!! */ - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation); - - codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */ - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */ - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */ - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - if (V_out < 0) - V_out= -V_out; - - if (V_out > MAX_V_RING_MEANx100) - err_mask |= 8; - - *ring_mean_v = V_out; - } else { - err_mask |= 8; - *ring_mean_v = 0; - } - } else { - err_mask |= 8; - *ring_mean_v = 0; - } - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */ - - /* Now Enable Rectifier */ - /* select source for the levelmeter to be IO4-IO3 */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, - LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT); - - /* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */ - codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON); - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES); - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - - /* Now programm Integrator Offset Registers !!! */ - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation); - - /* Be sure that a Ring is generated !!!! */ - codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */ - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/ - - V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */ - if (V_out < 0) - V_out = -V_out; - - Vout_diff = (V_out - TARGET_V_RING_RMSx100); - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_RMS_RING_MAX_DIFFx100) - err_mask |= 16; - - *ring_rms_v = V_out; - } else { - err_mask |= 16; - *ring_rms_v = 0; - } - } else { - err_mask |= 16; - *ring_rms_v = 0; - } - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - retrieve_slic_state(slic_id); - - return(err_mask); -} - -int test_dtmf(int slic_id) -{ - unsigned char code; - unsigned char b; - unsigned int intreg; - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - - for (code = 0; code < 16; code++) { - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN); - udelay(80000); - - intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); - if ((intreg & CODSP_INTREG_INT_CH) == 0) - break; - - if ((intreg & CODSP_INTREG_DTMF_OK) == 0 || - codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code]) - break; - - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN)); - - udelay(80000); - - intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */ - } - - if (code != 16) { - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */ - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN)); - return(1); - } - - return(0); -} - -void data_up_persist_time(int duslic_id, int channel, int time_ms) -{ - unsigned char b; - - b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR); - b = (b & 0x0F) | ((time_ms & 0x0F) << 4); - codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b); -} - -static void program_dtmf_params(int duslic_id, int channel) -{ - unsigned char b; - - codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10); - codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C); - codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79); - codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10); - codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02); - codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB); - codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91); - codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00); - codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00); - codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00); - - b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR); - codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN); -} - -static void codsp_channel_full_reset(int duslic_id, int channel) -{ - - program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs)); - program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs)); - - /* program basic configuration registers */ - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01); - codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41); - codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43); - codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00); - - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */ - - program_dtmf_params(duslic_id, channel); - - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */ - - data_up_persist_time(duslic_id, channel, 4); - - codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */ - - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); -} - -static int codsp_chip_full_reset(int duslic_id) -{ - int i, cnt; - int intreg[NUM_CHANNELS]; - unsigned char pcm_resync; - unsigned char revision; - - codsp_reset_chip(duslic_id); - - udelay(2000); - - for (i = 0; i < NUM_CHANNELS; i++) - intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR); - - udelay(1500); - - if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) { - printf("_HOOK(%d) stayed low\n", duslic_id); - return -1; - } - - for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) { - if (intreg[i] & CODSP_INTREG_SYNC_FAIL) - pcm_resync |= 1 << i; - } - - for (cnt = 0; cnt < 5 && pcm_resync; cnt++) { - for (i = 0; i < NUM_CHANNELS; i++) - codsp_resync_channel(duslic_id, i); - - udelay(2000); - - pcm_resync = 0; - - for (i = 0; i < NUM_CHANNELS; i++) { - if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL) - pcm_resync |= 1 << i; - } - } - - if (cnt == 5) { - printf("PCM_Resync(%u) not completed\n", duslic_id); - return -2; - } - - revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR); - printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F); - - codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */ - - for (i = 0; i < NUM_CHANNELS; i++) { - codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01); - codsp_channel_full_reset(duslic_id, i); - } - - return 0; -} - -int slic_self_test(int duslic_mask) -{ - int slic; - int i; - int r; - long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v; - const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" }; - int error = 0; - - for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */ - if (duslic_mask & (1 << (slic >> 1))) { - r = measure_on_hook_voltages(slic, &vdd, - &v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v); - - printf("SLIC %u measured voltages (x100):\n\t" - "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n", - slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v); - - if (r != 0) - error |= 1 << slic; - - for (i = 0; i < 5; i++) - if (r & (1 << i)) - printf("\t%s out of range\n", err_txt[i]); - } - } - - for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */ - if (duslic_mask & (1 << (slic >> 1))) { - printf("SLIC %u VOICE PATH...CHECKING", slic); - printf("\rSLIC %u VOICE PATH...%s\n", slic, - (r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED "); - - if (r != 0) - error |= 1 << slic; - } - } - - return(error); -} - -#if defined(CONFIG_NETTA_ISDN) - -#define SPIENS1 (1 << (31 - 15)) -#define SPIENS2 (1 << (31 - 19)) - -static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 }; -int s_initialized = 0; - -static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value) -{ - unsigned int rx, v; - - _PORTB_SET(spiens_mask_tab[s_id], 0); - - rx = __SPI_Transfer(address); - - switch (address & 0xF0) { - case 0x60: /* write byte register */ - case 0x70: - rx = __SPI_Transfer(value); - break; - - case 0xE0: /* read R6 register */ - v = __SPI_Transfer(0); - - rx = (rx << 8) | v; - - break; - - case 0xF0: /* read byte register */ - rx = __SPI_Transfer(0); - - break; - } - - _PORTB_SET(spiens_mask_tab[s_id], 1); - - return rx; -} - -static void s_write_BR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - - address = 0x70 | (regno & 15); - val &= 0xff; - - (void)s_transfer_internal(s_id, address, val); -} - -static void s_write_OR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - - address = 0x70 | (regno & 15); - val &= 0xff; - - (void)s_transfer_internal(s_id, address, val); -} - -static void s_write_NR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - - address = (regno & 7) << 4; - val &= 0xf; - - (void)s_transfer_internal(s_id, address | val, 0x00); -} - -#define BR7_IFR 0x08 /* IDL2 free run */ -#define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */ - -#define BR15_OVRL_REG_EN 0x80 -#define OR7_D3VR 0x80 /* disable 3V regulator */ - -#define OR8_TEME 0x10 /* TE mode enable */ -#define OR8_MME 0x08 /* master mode enable */ - -void s_initialize(void) -{ - int s_id; - - for (s_id = 0; s_id < 2; s_id++) { - s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB); - s_write_BR(s_id, 15, BR15_OVRL_REG_EN); - s_write_OR(s_id, 8, OR8_TEME | OR8_MME); - s_write_OR(s_id, 7, OR7_D3VR); - s_write_OR(s_id, 6, 0); - s_write_BR(s_id, 15, 0); - s_write_NR(s_id, 3, 0); - } -} - -#endif - -int board_post_codec(int flags) -{ - int j; - int r; - int duslic_mask; - - printf("board_post_dsp\n"); - -#if defined(CONFIG_NETTA_ISDN) - if (s_initialized == 0) { - s_initialize(); - s_initialized = 1; - - printf("s_initialized\n"); - - udelay(20000); - } -#endif - duslic_mask = 0; - - for (j = 0; j < MAX_DUSLIC; j++) { - if (codsp_chip_full_reset(j) < 0) - printf("Error initializing DuSLIC#%d\n", j); - else - duslic_mask |= 1 << j; - } - - if (duslic_mask != 0) { - printf("Testing SLICs...\n"); - - r = slic_self_test(duslic_mask); - for (j = 0; j < MAX_SLICS; j++) { - if (duslic_mask & (1 << (j >> 1))) - printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK"); - } - } - printf("DuSLIC self test finished\n"); - - return 0; /* return -1 on error */ -} diff --git a/board/netta/dsp.c b/board/netta/dsp.c deleted file mode 100644 index cd576476ec..0000000000 --- a/board/netta/dsp.c +++ /dev/null @@ -1,1208 +0,0 @@ -/* - * Intracom TI6711/TI6412 DSP - */ - -#include -#include - -#include "mpc8xx.h" - -struct ram_range { - u32 start; - u32 size; -}; - -#if defined(CONFIG_NETTA_6412) - -static const struct ram_range int_ram[] = { - { 0x00000000U, 0x00040000U }, -}; - -static const struct ram_range ext_ram[] = { - { 0x80000000U, 0x00100000U }, -}; - -static const struct ram_range ranges[] = { - { 0x00000000U, 0x00040000U }, - { 0x80000000U, 0x00100000U }, -}; - -static inline u16 bit_invert(u16 d) -{ - register u8 i; - register u16 r; - register u16 bit; - - r = 0; - for (i = 0; i < 16; i++) { - bit = d & (1 << i); - if (bit != 0) - r |= 1 << (15 - i); - } - return r; -} - -#else - -static const struct ram_range int_ram[] = { - { 0x00000000U, 0x00010000U }, -}; - -static const struct ram_range ext_ram[] = { - { 0x80000000U, 0x00100000U }, -}; - -static const struct ram_range ranges[] = { - { 0x00000000U, 0x00010000U }, - { 0x80000000U, 0x00100000U }, -}; - -#endif - -/*******************************************************************************************************/ - -static inline int addr_in_int_ram(u32 addr) -{ - int i; - - for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++) - if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size) - return 1; - - return 0; -} - -static inline int addr_in_ext_ram(u32 addr) -{ - int i; - - for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++) - if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size) - return 1; - - return 0; -} - -/*******************************************************************************************************/ - -#define DSP_HPIC 0x0 -#define DSP_HPIA 0x4 -#define DSP_HPID1 0x8 -#define DSP_HPID2 0xC - -static u32 dummy_delay; -static volatile u32 *ti6711_delay = &dummy_delay; - -static inline void dsp_go_slow(void) -{ - volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl; -#if defined(CONFIG_NETTA_6412) - memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX; -#else - memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX; -#endif - memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX; - - ti6711_delay = (u32 *)DUMMY_BASE; -} - -static inline void dsp_go_fast(void) -{ - volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl; -#if defined(CONFIG_NETTA_6412) - memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; -#else - memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK; -#endif - memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; - - ti6711_delay = &dummy_delay; -} - -/*******************************************************************************************************/ - -static inline void dsp_delay(void) -{ - /* perform ti6711_delay chip select read to have a small delay */ - (void) *(volatile u32 *)ti6711_delay; -} - -static inline u16 dsp_read_hpic(void) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*((volatile u16 *)DSP_BASE)); -#else - return *((volatile u16 *)DSP_BASE); -#endif -} - -static inline void dsp_write_hpic(u16 val) -{ -#if defined(CONFIG_NETTA_6412) - *((volatile u16 *)DSP_BASE) = bit_invert(val); -#else - *((volatile u16 *)DSP_BASE) = val; -#endif -} - -static inline void dsp_reset(void) -{ -#if defined(CONFIG_NETTA_6412) - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15)); - udelay(500); - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15)); - udelay(500); -#else - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7)); - udelay(250); - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7)); - udelay(250); -#endif -} - -static inline u32 dsp_read_hpic_word(u32 addr) -{ - u32 val; - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - - val = ((u32) bit_invert(p[0]) << 16); - /* dsp_delay(); */ - - val |= bit_invert(p[1]); - /* dsp_delay(); */ -#else - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - - val = ((u32) p[0] << 16); - dsp_delay(); - - val |= p[1]; - dsp_delay(); -#endif - return val; -} - -static inline u16 dsp_read_hpic_hi_hword(u32 addr) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr)); -#else - return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr); -#endif -} - -static inline u16 dsp_read_hpic_lo_hword(u32 addr) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2)); -#else - return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2); -#endif -} - -static inline void dsp_wait_hrdy(void) -{ - int i; - - i = 0; -#if defined(CONFIG_NETTA_6412) - while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) { -#else - while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { -#endif - dsp_delay(); - i++; - } -} - -static inline void dsp_write_hpic_word(u32 addr, u32 val) -{ - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - p[0] = bit_invert((u16)(val >> 16)); - /* dsp_delay(); */ - - p[1] = bit_invert((u16)val); - /* dsp_delay(); */ -#else - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - p[0] = (u16)(val >> 16); - dsp_delay(); - - p[1] = (u16)val; - dsp_delay(); -#endif -} - -static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h) -{ -#if defined(CONFIG_NETTA_6412) - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h); -#else - - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h; -#endif -} - -static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l) -{ -#if defined(CONFIG_NETTA_6412) - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l); -#else - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l; -#endif -} - -/********************************************************************/ - -static inline void c62_write_word(u32 addr, u32 val) -{ - dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - - dsp_wait_hrdy(); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); - - /* dsp_wait_hrdy(); - dsp_delay(); */ -#endif - dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif -} - -static u32 c62_read_word(u32 addr) -{ - u32 val; - - dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - - /* FETCH */ -#if defined(CONFIG_NETTA_6412) - dsp_write_hpic_word(DSP_HPIC, 0x00100010); -#else - dsp_write_hpic(0x10); - dsp_delay(); -#endif - dsp_wait_hrdy(); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16; -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); - - /* dsp_wait_hrdy(); - dsp_delay(); */ -#endif - val |= dsp_read_hpic_lo_hword(DSP_HPID2); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - return val; -} - -static inline void c62_read(u32 addr, u32 *buffer, int numdata) -{ - int i; - - if (numdata <= 0) - return; - - for (i = 0; i < numdata; i++) { - *buffer++ = c62_read_word(addr); - addr += 4; - } -} - -static inline u32 c62_checksum(u32 addr, int numdata) -{ - int i; - u32 chksum; - - chksum = 0; - for (i = 0; i < numdata; i++) { - chksum += c62_read_word(addr); - addr += 4; - } - - return chksum; -} - -static inline void c62_write(u32 addr, const u32 *buffer, int numdata) -{ - int i; - - if (numdata <= 0) - return; - - for (i = 0; i < numdata; i++) { - c62_write_word(addr, *buffer++); - addr += 4; - } -} - -static inline int c62_write_word_validated(u32 addr, u32 val) -{ - c62_write_word(addr, val); - return c62_read_word(addr) == val ? 0 : -1; -} - -static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata) -{ - int i, r; - - if (numdata <= 0) - return 0; - - for (i = 0; i < numdata; i++) { - r = c62_write_word_validated(addr, *buffer++); - if (r < 0) - return r; - addr += 4; - } - return 0; -} - -#if defined(CONFIG_NETTA_6412) - -#define DRAM_REGS_BASE 0x1800000 - -#define GBLCTL DRAM_REGS_BASE -#define CECTL1 (DRAM_REGS_BASE + 0x4) -#define CECTL0 (DRAM_REGS_BASE + 0x8) -#define CECTL2 (DRAM_REGS_BASE + 0x10) -#define CECTL3 (DRAM_REGS_BASE + 0x14) -#define SDCTL (DRAM_REGS_BASE + 0x18) -#define SDTIM (DRAM_REGS_BASE + 0x1C) -#define SDEXT (DRAM_REGS_BASE + 0x20) -#define SESEC1 (DRAM_REGS_BASE + 0x44) -#define SESEC0 (DRAM_REGS_BASE + 0x48) -#define SESEC2 (DRAM_REGS_BASE + 0x50) -#define SESEC3 (DRAM_REGS_BASE + 0x54) - -#define MAR128 0x1848200 -#define MAR129 0x1848204 - -void dsp_dram_initialize(void) -{ - c62_write_word(GBLCTL, 0x120E4); - c62_write_word(CECTL1, 0x18); - c62_write_word(CECTL0, 0xD0); - c62_write_word(CECTL2, 0x18); - c62_write_word(CECTL3, 0x18); - c62_write_word(SDCTL, 0x47115000); - c62_write_word(SDTIM, 1536); - c62_write_word(SDEXT, 0x534A9); -#if 0 - c62_write_word(SESEC1, 0); - c62_write_word(SESEC0, 0); - c62_write_word(SESEC2, 0); - c62_write_word(SESEC3, 0); -#endif - c62_write_word(MAR128, 1); - c62_write_word(MAR129, 0); -} - -#endif - -static inline void dsp_init_hpic(void) -{ - int i; - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - dsp_go_fast(); -#else - dsp_go_slow(); -#endif - i = 0; -#if defined(CONFIG_NETTA_6412) - while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) { -#else - while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { -#endif - dsp_delay(); - i++; - } - - if (i == 1000) - printf("HRDY stuck\n"); - - dsp_delay(); - - /* write control register */ - p = (volatile u16 *)DSP_BASE; - p[0] = 0x0000; - dsp_delay(); - p[1] = 0x0000; - dsp_delay(); - -#if !defined(CONFIG_NETTA_6412) - dsp_go_fast(); -#endif -} - -/***********************************************************************************************************/ - -#if !defined(CONFIG_NETTA_6412) - -static const u8 bootstrap_rbin[5084] = { - 0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, - 0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, - 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, - 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, - 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(too short header)\n"); - return -1; - } - - chksum = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] << 8) | (u32)s[ 7]; - rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] << 8) | (u32)s[11]; - s += 12; l -= 12; - - hdr = s; - s += 8 * rangenr; l -= 8 * rangenr; - data = s; - - /* validate bootstrap image */ - h = hdr; s = data; chksum2 = 0; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - - /* too short */ - if (l < length) { - printf("bootstrap image corrupted. (too short data)\n"); - return -1; - } - l -= length; - - j = (int)length / 4; - while (j-- > 0) { - chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] << 8) | (u32)s[3]; - s += 4; - } - } - - /* checksum must match */ - if (chksum != chksum2) { - printf("bootstrap image corrupted. (checksum error)\n"); - return -1; - } - - /* nothing must be left */ - if (l != 0) { - printf("bootstrap image corrupted. (garbage at the end)\n"); - return -1; - } - - /* write the image */ - h = hdr; - s = data; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - c62_write(start, (u32 *)s, length / 4); - s += length; - } - - /* and now validate checksum */ - h = hdr; - s = data; - chksum2 = 0; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - chksum2 += c62_checksum(start, length / 4); - s += length; - } - - /* checksum must match */ - if (chksum != chksum2) { - printf("bootstrap in DSP memory is corrupted\n"); - return -1; - } - - return 0; -} - -struct host_init { - u32 master_mode; - struct { - u8 port_id; - u8 slot_id; - } ch_serial_map[32]; - u32 clk_divider[2]; - /* pll */ - u32 initmode; - u32 pllm; - u32 div[4]; - u32 oscdiv1; - u32 unused[10]; -}; - -const struct host_init hi_default = { - .master_mode = -#if !defined(CONFIG_NETTA_ISDN) - -1, -#else - 0, -#endif - - .ch_serial_map = { - [ 0] = { .port_id = 2, .slot_id = 16 }, - [ 1] = { .port_id = 2, .slot_id = 17 }, - [ 2] = { .port_id = 2, .slot_id = 18 }, - [ 3] = { .port_id = 2, .slot_id = 19 }, - [ 4] = { .port_id = 2, .slot_id = 20 }, - [ 5] = { .port_id = 2, .slot_id = 21 }, - [ 6] = { .port_id = 2, .slot_id = 22 }, - [ 7] = { .port_id = 2, .slot_id = 23 }, - [ 8] = { .port_id = 2, .slot_id = 24 }, - [ 9] = { .port_id = 2, .slot_id = 25 }, - [10] = { .port_id = 2, .slot_id = 26 }, - [11] = { .port_id = 2, .slot_id = 27 }, - [12] = { .port_id = 2, .slot_id = 28 }, - [13] = { .port_id = 2, .slot_id = 29 }, - [14] = { .port_id = 2, .slot_id = 30 }, - [15] = { .port_id = 2, .slot_id = 31 }, - }, - - /* - dsp_clk(xin, pllm) = xin * pllm - serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1) - */ - - .clk_divider = { - [0] = 47, /* must be 2048Hz */ - [1] = 47, - }, - - .initmode = 1, - .pllm = -#if !defined(CONFIG_NETTA_ISDN) - 8, /* for =~ 25MHz 8 */ -#else - 4, -#endif - .div = { - [0] = 0x8000, - [1] = 0x8000, /* for =~ 25MHz 0x8000 */ - [2] = 0x8001, /* for =~ 25MHz 0x8001 */ - [3] = 0x8001, /* for =~ 25MHz 0x8001 */ - }, - - .oscdiv1 = 0, -}; - -static void hi_write(const struct host_init *hi) -{ - u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)]; - u32 *s; - u32 chksum; - int i; - - memset(hi_buf, 0, sizeof(hi_buf)); - - s = hi_buf; - s++; - *s++ = hi->master_mode; - for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++) - *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) | - ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id; - - for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++) - *s++ = hi->clk_divider[i]; - - *s++ = hi->initmode; - *s++ = hi->pllm; - for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++) - *s++ = hi->div[i]; - *s++ = hi->oscdiv1; - - chksum = 0; - for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++) - chksum += hi_buf[i]; - hi_buf[0] = -chksum; - - c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0])); -} - -static void run_bootstrap(void) -{ - dsp_go_slow(); - - hi_write(&hi_default); - - /* signal interrupt */ - dsp_write_hpic(0x0002); - dsp_delay(); - - dsp_go_fast(); -} - -#endif - -/***********************************************************************************************************/ - -int board_post_dsp(int flags) -{ - u32 ramS, ramE; - u32 data, data2; - int i, j, k; -#if !defined(CONFIG_NETTA_6412) - int r; -#endif - dsp_reset(); - dsp_init_hpic(); -#if !defined(CONFIG_NETTA_6412) - dsp_go_slow(); -#endif - data = 0x11223344; - dsp_write_hpic_word(DSP_HPIA, data); - data2 = dsp_read_hpic_word(DSP_HPIA); - if (data2 != 0x11223344) { - printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); - goto err; - } - - data = 0xFFEEDDCC; - dsp_write_hpic_word(DSP_HPIA, data); - data2 = dsp_read_hpic_word(DSP_HPIA); - if (data2 != 0xFFEEDDCC) { - printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); - goto err; - } -#if defined(CONFIG_NETTA_6412) - dsp_dram_initialize(); -#else - r = load_bootstrap(); - if (r < 0) { - printf("BOOTSTRAP: ** ERROR ** failed to load\n"); - goto err; - } - - run_bootstrap(); - - dsp_go_fast(); -#endif - printf(" "); - - /* test RAMs */ - for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) { - - ramS = ranges[k].start; - ramE = ranges[k].start + ranges[k].size; - - for (j = 0; j < 3; j++) { - - printf("\b\b\b\bR%d.%d", k, j); - - for (i = ramS; i < ramE; i += 4) { - - data = 0; - switch (j) { - case 0: data = 0xAA55AA55; break; - case 1: data = 0x55AA55AA; break; - case 2: data = (u32)i; break; - } - - c62_write_word(i, data); - data2 = c62_read_word(i); - if (data != data2) { - printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2); - goto err; - } - } - } - } - - printf("\b\b\b\b \b\b\b\bOK\n"); -#if !defined(CONFIG_NETTA_6412) - /* XXX assume that this works */ - load_bootstrap(); - run_bootstrap(); - dsp_go_fast(); -#endif - return 0; - -err: - return -1; -} - -int board_dsp_reset(void) -{ -#if !defined(CONFIG_NETTA_6412) - int r; -#endif - dsp_reset(); - dsp_init_hpic(); -#if defined(CONFIG_NETTA_6412) - dsp_dram_initialize(); -#else - dsp_go_slow(); - r = load_bootstrap(); - if (r < 0) - return r; - - run_bootstrap(); - dsp_go_fast(); -#endif - return 0; -} diff --git a/board/netta/flash.c b/board/netta/flash.c deleted file mode 100644 index d6902a6938..0000000000 --- a/board/netta/flash.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netta/netta.c b/board/netta/netta.c deleted file mode 100644 index bfd51e7c3b..0000000000 --- a/board/netta/netta.c +++ /dev/null @@ -1,558 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include -#include - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NETTA" -#if defined(CONFIG_NETTA_ISDN) - " with ISDN support" -#endif -#if defined(CONFIG_NETTA_6412) - " (DSP:TI6412)" -#else - " (DSP:TI6711)" -#endif - "\n" - ); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define A10_AAAA 0x00000000 -#define A10_AAA0 0x00200000 -#define A10_AAA1 0x00300000 -#define A10_000A 0x00800000 -#define A10_0000 0x00A00000 -#define A10_0001 0x00B00000 -#define A10_111A 0x00C00000 -#define A10_1110 0x00E00000 -#define A10_1111 0x00F00000 - -#define RAS_0000 0x00000000 -#define RAS_0001 0x00040000 -#define RAS_1110 0x00080000 -#define RAS_1111 0x000C0000 - -#define CAS_0000 0x00000000 -#define CAS_0001 0x00010000 -#define CAS_1110 0x00020000 -#define CAS_1111 0x00030000 - -#define WE_0000 0x00000000 -#define WE_0001 0x00004000 -#define WE_1110 0x00008000 -#define WE_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - -#if 0 - printf("check 0\n"); - check_ram(( 0 << 20), (2 << 20)); - printf("check 16\n"); - check_ram((16 << 20), (2 << 20)); - printf("check 32\n"); - check_ram((32 << 20), (2 << 20)); - printf("check 48\n"); - check_ram((48 << 20), (2 << 20)); -#endif - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r(void) -{ - return(0); -} - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, - BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -extern int board_dsp_reset(void); - -int last_stage_init(void) -{ - int r; - - reset_phys(); - r = board_dsp_reset(); - if (r < 0) - printf("*** WARNING *** DSP reset failed (run diagnostics)\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11)) -#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15)) -#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5)) -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK (_B(28) | _B(31)) -#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31)) -#define PB_SP_DIRVAL 0 - -#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15)) -#define PC_GP_OUTMASK (_BW(6) | _BW(12)) -#define PC_SP_MASK (_BW(4) | _BW(8)) -#define PC_SOVAL 0 -#define PC_INTVAL _BW(7) -#define PC_GP_OUTVAL (_BW(6) | _BW(12)) -#define PC_SP_DIRVAL 0 - -#define PD_GP_INMASK 0 -#define PD_GP_OUTMASK _BWR(3, 15) -#define PD_SP_MASK 0 - -#if defined(CONFIG_NETTA_6412) - -#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15)) - -#else - -#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11)) - -#endif - -#define PD_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* CS1: NAND chip select */ - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ; - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#if !defined(CONFIG_NETTA_6412) - /* CS2: DSP */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); -#else - /* CS6: DSP */ - memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); - memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); -#endif - /* CS4: External register chip select */ - memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); - memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); - - /* CS5: dummy for accurate delay */ - memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2); - memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - ioport->iop_pddat = PD_GP_OUTVAL; - ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; - ioport->iop_pdpar = PD_SP_MASK; - - /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */ - - return 0; -} - -#if defined(CONFIG_CMD_PCMCIA) - -int pcmcia_init(void) -{ - return 0; -} - -#endif - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c deleted file mode 100644 index 3fa1925f4c..0000000000 --- a/board/netta/pcmcia.c +++ /dev/null @@ -1,346 +0,0 @@ -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -#define PCMCIA_BOARD_MSG "NETTA" - -static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) }; - -static void cfg_vppd(int no) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) - return; - - mask = vppd_masks[no]; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_vppd(int no, int what) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) - return; - - mask = vppd_masks[no]; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) }; - -static void cfg_vccd(int no) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) - return; - - mask = vccd_masks[no]; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_vccd(int no, int what) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) - return; - - mask = vccd_masks[no]; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static const unsigned short oc_mask = _BW(8); - -static void cfg_oc(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask = oc_mask; - - immap->im_ioport.iop_pcdir &= ~mask; - immap->im_ioport.iop_pcso &= ~mask; - immap->im_ioport.iop_pcint &= ~mask; - immap->im_ioport.iop_pcpar &= ~mask; -} - -static int get_oc(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask = oc_mask; - int what; - - what = !!(immap->im_ioport.iop_pcdat & mask);; - return what; -} - -static const unsigned short shdn_mask = _BW(12); - -static void cfg_shdn(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - mask = shdn_mask; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_shdn(int what) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - mask = shdn_mask; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static void cfg_ports (void) -{ - cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ - cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ - cfg_shdn(); - cfg_oc(); - - /* - * Configure Port A for TPS2211 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - set_vppd(0, 1); set_vppd(1, 1); - set_vccd(0, 0); set_vccd(1, 0); - set_shdn(1); - - udelay(100000); -} - -int pcmcia_hardware_enable(int slot) -{ - volatile pcmconf8xx_t *pcmp; - uint reg, pipr, mask; - int i; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ - cfg_ports (); - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - if ((pipr & mask) == mask) { - set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ - set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ - puts (" 5.0V card found: "); - } else { - set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ - set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ - puts (" 3.3V card found: "); - } - - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if (!get_oc()) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ - return (1); - } - udelay (100); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - /* All voltages off / Hi-Z */ - set_vppd(0, 1); set_vppd(1, 1); - set_vccd(0, 1); set_vccd(1, 1); - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_ports (); /* Enables switch, but all in Hi-Z */ - - set_vppd(0, 1); set_vppd(1, 1); - - switch(vcc) { - case 0: - break; /* Switch off */ - - case 33: - set_vccd(0, 1); set_vccd(1, 0); - break; - - case 50: - set_vccd(0, 0); set_vccd(1, 1); - break; - - default: - goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/netta/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug deleted file mode 100644 index a198cf9520..0000000000 --- a/board/netta/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netta2/Makefile b/board/netta2/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/netta2/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/netta2/flash.c b/board/netta2/flash.c deleted file mode 100644 index 133f36d98c..0000000000 --- a/board/netta2/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c deleted file mode 100644 index 362a3c782c..0000000000 --- a/board/netta2/netta2.c +++ /dev/null @@ -1,624 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include -#include - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -#if CONFIG_NETTA2_VERSION == 2 -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; -#endif - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, - BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK _B(28) -#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_DIRVAL 0 - -#if CONFIG_NETTA2_VERSION == 1 -#define PC_GP_INMASK _BW(12) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) -#elif CONFIG_NETTA2_VERSION == 2 -#define PC_GP_INMASK (_BW(13) | _BW(15)) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) -#endif -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL (_BW(10) | _BW(11)) -#define PC_SP_DIRVAL 0 - -#if CONFIG_NETTA2_VERSION == 1 -#define PE_GP_INMASK _B(31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) -#elif CONFIG_NETTA2_VERSION == 2 -#define PE_GP_INMASK _BR(28, 31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) -#endif -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* NAND chip select */ -#if CONFIG_NETTA2_VERSION == 1 - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#elif CONFIG_NETTA2_VERSION == 2 - upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); - memctl->memc_mamr = 0; /* all clear */ -#endif - - /* DSP chip select */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - -#if CONFIG_NETTA2_VERSION == 1 - memctl->memc_br4 &= ~BR_V; -#endif - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; - - return 0; -} - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return 0; -} - -int last_stage_init(void) -{ -#if CONFIG_NETTA2_VERSION == 2 - int i; -#endif - -#if CONFIG_NETTA2_VERSION == 2 - /* assert peripheral reset */ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); - for (i = 0; i < 10; i++) - udelay(1000); - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12); -#endif - reset_phys(); - - return 0; -} diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/netta2/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug deleted file mode 100644 index a198cf9520..0000000000 --- a/board/netta2/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netvia/Makefile b/board/netvia/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/netvia/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/netvia/flash.c b/board/netvia/flash.c deleted file mode 100644 index 14888f84ba..0000000000 --- a/board/netvia/flash.c +++ /dev/null @@ -1,495 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c deleted file mode 100644 index 2857a4f4c4..0000000000 --- a/board/netvia/netvia.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetVia board - */ - -#include -#include "mpc8xx.h" - -/****************************************************************/ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -/* last value written to the external register; we cannot read back */ -unsigned int last_er_val; -#endif - -/****************************************************************/ - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define A10_AAAA 0x00000000 -#define A10_AAA0 0x00200000 -#define A10_AAA1 0x00300000 -#define A10_000A 0x00800000 -#define A10_0000 0x00A00000 -#define A10_0001 0x00B00000 -#define A10_111A 0x00C00000 -#define A10_1110 0x00E00000 -#define A10_1111 0x00F00000 - -#define RAS_0000 0x00000000 -#define RAS_0001 0x00040000 -#define RAS_1110 0x00080000 -#define RAS_1111 0x000C0000 - -#define CAS_0000 0x00000000 -#define CAS_0001 0x00010000 -#define CAS_1110 0x00020000 -#define CAS_1111 0x00030000 - -#define WE_0000 0x00000000 -#define WE_0001 0x00004000 -#define WE_1110 0x00008000 -#define WE_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -const uint sdram_table[0x40] = { - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, - - /* REG */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ETX ID string (ETX_xxx...) - * - * Return 1 always. - */ - -int checkboard(void) -{ -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 - printf ("NETVIA v1\n"); -#else - printf ("NETVIA v2+\n"); -#endif - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -#define MAR_SDRAM_INIT 0x000000C8LU - -#define MCR_OP(x) ((unsigned long)((x) & 3) << (31-1)) -#define MCR_OP_MASK MCR_OP(3) - -#define MCR_UM(x) ((unsigned long)((x) & 1) << (31 - 8)) -#define MCR_UM_MASK MCR_UM(1) -#define MCR_UM_UPMA MCR_UM(0) -#define MCR_UM_UPMB MCR_UM(1) - -#define MCR_MB(x) ((unsigned long)((x) & 7) << (31 - 18)) -#define MCR_MB_MASK MCR_MB(7) -#define MCR_MB_CS(x) MCR_MB(x) - -#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23)) -#define MCR_MCLF_MASK MCR_MCLF(15) - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0) */ - udelay(1); - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay(1000); - - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL; - - size = SDRAM_MAX_SIZE; - - udelay(10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r(void) -{ -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - last_er_val = 0xffffffff; -#endif - return(0); -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(5) | _BWR(14, 15)) -#define PA_SP_MASK (_BW(4) | _BWR(6, 13)) -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL _BW(5) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK _B(28) -#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) -#define PB_SP_MASK _BR(22, 25) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) -#define PB_SP_DIRVAL 0 - -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 - -#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13)) -#define PC_GP_OUTMASK _BW(12) -#define PC_SP_MASK (_BW(4) | _BW(8)) -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL 0 -#define PC_SP_DIRVAL 0 - -#define PD_GP_INMASK 0 -#define PD_GP_OUTMASK _BWR(3, 15) -#define PD_SP_MASK 0 -#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15)) -#define PD_SP_DIRVAL 0 - -#elif CONFIG_NETVIA_VERSION >= 2 - -#define PC_GP_INMASK (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15)) -#define PC_GP_OUTMASK (_BW(6) | _BW(12)) -#define PC_SP_MASK (_BW(4) | _BW(8)) -#define PC_SOVAL 0 -#define PC_INTVAL _BW(7) -#define PC_GP_OUTVAL (_BW(6) | _BW(12)) -#define PC_SP_DIRVAL 0 - -#define PD_GP_INMASK 0 -#define PD_GP_OUTMASK _BWR(3, 15) -#define PD_SP_MASK 0 -#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(9) | _BW(11)) -#define PD_SP_DIRVAL 0 - -#else -#error Unknown NETVIA board version. -#endif - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* DSP0 chip select */ - memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - - /* DSP1 chip select */ - memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - - /* FPGA chip select */ - memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK); - memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - /* NAND chip select */ - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); - - /* kill this chip select */ - memctl->memc_br2 &= ~BR_V; /* invalid */ - - /* external reg chip select */ - memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); - memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); -#endif - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - ioport->iop_pddat = PD_GP_OUTVAL; - ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; - ioport->iop_pdpar = PD_SP_MASK; - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - /* external register init */ - *(volatile uint *)ER_BASE = 0xFFFFFFFF; -#endif - - return 0; -} diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/netvia/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug deleted file mode 100644 index 5bbf1c5535..0000000000 --- a/board/netvia/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/nokia/rx51/Kconfig b/board/nokia/rx51/Kconfig new file mode 100644 index 0000000000..ec6a571a22 --- /dev/null +++ b/board/nokia/rx51/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NOKIA_RX51 + +config SYS_BOARD + default "rx51" + +config SYS_VENDOR + default "nokia" + +config SYS_CONFIG_NAME + default "nokia_rx51" + +endif diff --git a/board/nokia/rx51/MAINTAINERS b/board/nokia/rx51/MAINTAINERS new file mode 100644 index 0000000000..8bdddc1d83 --- /dev/null +++ b/board/nokia/rx51/MAINTAINERS @@ -0,0 +1,6 @@ +RX51 BOARD +M: Pali Rohár +S: Maintained +F: board/nokia/rx51/ +F: include/configs/nokia_rx51.h +F: configs/nokia_rx51_defconfig diff --git a/board/nokia/rx51/Makefile b/board/nokia/rx51/Makefile index 2772a24dc6..8d4d97b9a9 100644 --- a/board/nokia/rx51/Makefile +++ b/board/nokia/rx51/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -SOBJS-y := lowlevel_init.o - -COBJS := $(sort $(COBJS-y)) -SOBJS := $(sort $(SOBJS-y)) -SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.S) -OBJS := $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := rx51.o +obj-y += lowlevel_init.o diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 3e419efe39..08fcaf21b3 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -422,8 +422,12 @@ int misc_init_r(void) /* * Cortex-A8(r1p0..r1p2) errata 430973 workaround * Set IBE bit in Auxiliary Control Register + * + * Call this routine only on real secure device + * Qemu does not implement secure PPA and crash */ - omap3_update_aux_cr_secure_rx51(1 << 6, 0); + if (get_device_type() == HS_DEVICE) + omap3_update_aux_cr_secure_rx51(1 << 6, 0); return 0; } @@ -585,7 +589,7 @@ static void rx51_kp_fill(u8 k, u8 mods) * Routine: rx51_kp_tstc * Description: Test if key was pressed (from buffer). */ -int rx51_kp_tstc(void) +int rx51_kp_tstc(struct stdio_dev *sdev) { u8 c, r, dk, i; u8 intr; @@ -641,10 +645,10 @@ int rx51_kp_tstc(void) * Routine: rx51_kp_getc * Description: Get last pressed key (from buffer). */ -int rx51_kp_getc(void) +int rx51_kp_getc(struct stdio_dev *sdev) { keybuf_head %= KEYBUF_SIZE; - while (!rx51_kp_tstc()) + while (!rx51_kp_tstc(sdev)) WATCHDOG_RESET(); return keybuf[keybuf_head++]; } @@ -659,3 +663,9 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); + twl4030_power_mmc_init(1); +} diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h index 4a230dd596..0d2f0a54c5 100644 --- a/board/nokia/rx51/rx51.h +++ b/board/nokia/rx51/rx51.h @@ -22,8 +22,6 @@ struct emu_hal_params_rx51 { u32 param4; }; -int print_cpuinfo(void); - /* * IEN - Input Enable * IDIS - Input Disable diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig new file mode 100644 index 0000000000..23f7c945f5 --- /dev/null +++ b/board/nvidia/beaver/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAVER + +config SYS_BOARD + default "beaver" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "beaver" + +endif diff --git a/board/nvidia/beaver/MAINTAINERS b/board/nvidia/beaver/MAINTAINERS new file mode 100644 index 0000000000..26bcacc8ec --- /dev/null +++ b/board/nvidia/beaver/MAINTAINERS @@ -0,0 +1,7 @@ +BEAVER BOARD +M: Tom Warren +M: Stephen Warren +S: Maintained +F: board/nvidia/beaver/ +F: include/configs/beaver.h +F: configs/beaver_defconfig diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile index 9510f607ab..1f7c31d64b 100644 --- a/board/nvidia/beaver/Makefile +++ b/board/nvidia/beaver/Makefile @@ -14,25 +14,4 @@ # along with this program. If not, see . # -include $(TOPDIR)/config.mk - -$(shell mkdir -p $(obj)../cardhu) - -LIB = $(obj)lib$(BOARD).o - -COBJS = ../cardhu/cardhu.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = ../cardhu/cardhu.o diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig new file mode 100644 index 0000000000..63ace66aa7 --- /dev/null +++ b/board/nvidia/cardhu/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CARDHU + +config SYS_BOARD + default "cardhu" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "cardhu" + +endif diff --git a/board/nvidia/cardhu/MAINTAINERS b/board/nvidia/cardhu/MAINTAINERS new file mode 100644 index 0000000000..d3c3e368c1 --- /dev/null +++ b/board/nvidia/cardhu/MAINTAINERS @@ -0,0 +1,6 @@ +CARDHU BOARD +M: Tom Warren +S: Maintained +F: board/nvidia/cardhu/ +F: include/configs/cardhu.h +F: configs/cardhu_defconfig diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile index 4a92d7a86d..3f9b55f6a7 100644 --- a/board/nvidia/cardhu/Makefile +++ b/board/nvidia/cardhu/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cardhu.o diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index 47e7abedf1..1540526a61 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -6,10 +6,14 @@ */ #include +#include #include #include +#include +#include #include "pinmux-config-cardhu.h" #include +#include #define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3 @@ -20,14 +24,14 @@ */ void pinmux_init(void) { - pinmux_config_table(tegra3_pinmux_common, + pinmux_config_pingrp_table(tegra3_pinmux_common, ARRAY_SIZE(tegra3_pinmux_common)); - pinmux_config_table(unused_pins_lowpower, + pinmux_config_pingrp_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); /* Initialize any non-default pad configs (APB_MISC_GP regs) */ - padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl)); + pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl)); } #if defined(CONFIG_TEGRA_MMC) @@ -37,17 +41,23 @@ void pinmux_init(void) */ void board_sdmmc_voltage_init(void) { + struct udevice *dev; uchar reg, data_buffer[1]; + int ret; int i; - i2c_set_bus_num(0); /* PMU is on bus 0 */ + ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); + if (ret) { + debug("%s: Cannot find PMIC I2C chip\n", __func__); + return; + } /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */ data_buffer[0] = 0x65; reg = 0x32; for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + if (dm_i2c_write(dev, reg, data_buffer, 1)) udelay(100); } @@ -56,7 +66,7 @@ void board_sdmmc_voltage_init(void) reg = 0x67; for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + if (dm_i2c_write(dev, reg, data_buffer, 1)) udelay(100); } } @@ -76,3 +86,52 @@ void pin_mux_mmc(void) board_sdmmc_voltage_init(); } #endif /* MMC */ + +#ifdef CONFIG_PCI_TEGRA +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + u8 addr, data[1]; + int err; + + err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); + if (err) { + debug("failed to find PMU bus\n"); + return err; + } + + /* TPS659110: LDO1_REG = 1.05V, ACTIVE */ + data[0] = 0x15; + addr = 0x30; + + err = dm_i2c_write(dev, addr, data, 1); + if (err) { + debug("failed to set VDD supply\n"); + return err; + } + + /* GPIO: PEX = 3.3V */ + err = gpio_request(GPIO_PL7, "PEX"); + if (err < 0) + return err; + + gpio_direction_output(GPIO_PL7, 1); + + /* TPS659110: LDO2_REG = 1.05V, ACTIVE */ + data[0] = 0x15; + addr = 0x31; + + err = dm_i2c_write(dev, addr, data, 1); + if (err) { + debug("failed to set AVDD supply\n"); + return err; + } + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} +#endif /* PCI */ diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h index 51d2b9425c..255e4cd82b 100644 --- a/board/nvidia/cardhu/pinmux-config-cardhu.h +++ b/board/nvidia/cardhu/pinmux-config-cardhu.h @@ -17,9 +17,9 @@ #ifndef _PINMUX_CONFIG_CARDHU_H_ #define _PINMUX_CONFIG_CARDHU_H_ -#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ { \ - .pingroup = PINGRP_##_pingroup, \ + .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ @@ -29,9 +29,9 @@ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } -#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ { \ - .pingroup = PINGRP_##_pingroup, \ + .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ @@ -41,9 +41,9 @@ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } -#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ { \ - .pingroup = PINGRP_##_pingroup, \ + .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ @@ -53,293 +53,293 @@ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ } -#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ { \ - .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ .slwf = _slwf, \ .slwr = _slwr, \ .drvup = _drvup, \ .drvdn = _drvdn, \ - .lpmd = PGRP_LPMD_##_lpmd, \ - .schmt = PGRP_SCHMT_##_schmt, \ - .hsm = PGRP_HSM_##_hsm, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ } -static struct pingroup_config tegra3_pinmux_common[] = { +static struct pmux_pingrp_config tegra3_pinmux_common[] = { /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT), /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), /* I2C4 pinmux */ - I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), /* Power I2C pinmux */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT), - LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), - DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */ - DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ - DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ - DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), + LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */ + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ + DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ + DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), /* KBC keys */ - DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), /* GPIOs */ /* SDMMC1 CD gpio */ - DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), /* SDMMC1 WP gpio */ - LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), /* Touch panel GPIO */ /* Touch IRQ */ - DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT), /* Touch RESET */ - DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT), /* Power rails GPIO */ - DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), - LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), }; -static struct pingroup_config unused_pins_lowpower[] = { - DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT), +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), }; -static struct padctrl_config cardhu_padctrl[] = { - /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ +static struct pmux_drvgrp_config cardhu_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), }; diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile index 6215cafe25..e3b2651570 100644 --- a/board/nvidia/common/Makefile +++ b/board/nvidia/common/Makefile @@ -1,30 +1,4 @@ # Copyright (c) 2011 The Chromium OS Authors. # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) -endif - -LIB = $(obj)lib$(VENDOR).o - -include common.mk - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +include $(src)/common.mk diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 126e56e97a..80ef8fdcb2 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -31,64 +32,42 @@ #endif #ifdef CONFIG_USB_EHCI_TEGRA #include -#include +#include #endif #ifdef CONFIG_TEGRA_MMC #include #include #endif +#include #include #include #include "emc.h" DECLARE_GLOBAL_DATA_PTR; -const struct tegra_sysinfo sysinfo = { - CONFIG_TEGRA_BOARD_STRING +#ifdef CONFIG_SPL_BUILD +/* TODO(sjg@chromium.org): Remove once SPL supports device tree */ +U_BOOT_DEVICE(tegra_gpios) = { + "gpio_tegra" }; - -#ifndef CONFIG_SPL_BUILD -/* - * Routine: timer_init - * Description: init the timestamp and lastinc value - */ -int timer_init(void) -{ - return 0; -} #endif -void __pin_mux_usb(void) -{ -} - -void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb"))); - -void __pin_mux_spi(void) -{ -} - -void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); - -void __gpio_early_init_uart(void) -{ -} +const struct tegra_sysinfo sysinfo = { + CONFIG_TEGRA_BOARD_STRING +}; -void gpio_early_init_uart(void) -__attribute__((weak, alias("__gpio_early_init_uart"))); +__weak void pinmux_init(void) {} +__weak void pin_mux_usb(void) {} +__weak void pin_mux_spi(void) {} +__weak void gpio_early_init_uart(void) {} +__weak void pin_mux_display(void) {} -void __pin_mux_nand(void) +#if defined(CONFIG_TEGRA_NAND) +__weak void pin_mux_nand(void) { funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); } - -void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand"))); - -void __pin_mux_display(void) -{ -} - -void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display"))); +#endif /* * Routine: power_det_init @@ -117,9 +96,8 @@ int board_init(void) clock_init(); clock_verify(); -#ifdef CONFIG_FDT_SPI +#ifdef CONFIG_TEGRA_SPI pin_mux_spi(); - spi_init(); #endif #ifdef CONFIG_PWM_TEGRA @@ -136,10 +114,6 @@ int board_init(void) power_det_init(); #ifdef CONFIG_SYS_I2C_TEGRA -#ifndef CONFIG_SYS_I2C_INIT_BOARD -#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards" -#endif - i2c_init_board(); # ifdef CONFIG_TEGRA_PMU if (pmu_set_nominal()) debug("Failed to select nominal voltages\n"); @@ -153,8 +127,9 @@ int board_init(void) #ifdef CONFIG_USB_EHCI_TEGRA pin_mux_usb(); - board_usb_init(gd->fdt_blob); + usb_process_devicetree(gd->fdt_blob); #endif + #ifdef CONFIG_LCD tegra_lcd_check_next_stage(gd->fdt_blob, 0); #endif @@ -163,6 +138,8 @@ int board_init(void) pin_mux_nand(); #endif + tegra_xusb_padctl_init(gd->fdt_blob); + #ifdef CONFIG_TEGRA_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ warmboot_save_sdram_params(); @@ -183,9 +160,7 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); int board_early_init_f(void) { -#if !defined(CONFIG_TEGRA20) pinmux_init(); -#endif board_init_uart_f(); /* Initialize periph GPIOs */ @@ -209,12 +184,10 @@ int board_late_init(void) } #if defined(CONFIG_TEGRA_MMC) -void __pin_mux_mmc(void) +__weak void pin_mux_mmc(void) { } -void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc"))); - /* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk index d9bcb85401..9a9b5298c7 100644 --- a/board/nvidia/common/common.mk +++ b/board/nvidia/common/common.mk @@ -1,3 +1,3 @@ # common options for all tegra boards -COBJS-y += ../../nvidia/common/board.o -COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o +obj-y += ../../nvidia/common/board.o +obj-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c index 8124f8aafd..8c62f36a7b 100644 --- a/board/nvidia/common/emc.c +++ b/board/nvidia/common/emc.c @@ -5,6 +5,7 @@ */ #include +#include "emc.h" #include #include #include diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig new file mode 100644 index 0000000000..96eaa01cf8 --- /dev/null +++ b/board/nvidia/dalmore/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DALMORE + +config SYS_BOARD + default "dalmore" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "dalmore" + +endif diff --git a/board/nvidia/dalmore/MAINTAINERS b/board/nvidia/dalmore/MAINTAINERS new file mode 100644 index 0000000000..fe86375ca9 --- /dev/null +++ b/board/nvidia/dalmore/MAINTAINERS @@ -0,0 +1,6 @@ +DALMORE BOARD +M: Tom Warren +S: Maintained +F: board/nvidia/dalmore/ +F: include/configs/dalmore.h +F: configs/dalmore_defconfig diff --git a/board/nvidia/dalmore/Makefile b/board/nvidia/dalmore/Makefile index 699b9f6cc6..7cdff9c61b 100644 --- a/board/nvidia/dalmore/Makefile +++ b/board/nvidia/dalmore/Makefile @@ -14,23 +14,4 @@ # along with this program. If not, see . # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dalmore.o diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 2c23a29db7..d7c1a695ff 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include "pinmux-config-dalmore.h" @@ -29,17 +30,18 @@ */ void pinmux_init(void) { - pinmux_config_table(tegra114_pinmux_set_nontristate, + pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate, ARRAY_SIZE(tegra114_pinmux_set_nontristate)); - pinmux_config_table(tegra114_pinmux_common, + pinmux_config_pingrp_table(tegra114_pinmux_common, ARRAY_SIZE(tegra114_pinmux_common)); - pinmux_config_table(unused_pins_lowpower, + pinmux_config_pingrp_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); /* Initialize any non-default pad configs (APB_MISC_GP regs) */ - padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl)); + pinmux_config_drvgrp_table(dalmore_padctrl, + ARRAY_SIZE(dalmore_padctrl)); } #if defined(CONFIG_TEGRA_MMC) @@ -49,18 +51,21 @@ void pinmux_init(void) */ void board_sdmmc_voltage_init(void) { + struct udevice *dev; uchar reg, data_buffer[1]; int ret; - ret = i2c_set_bus_num(0);/* PMU is on bus 0 */ - if (ret) - printf("%s: i2c_set_bus_num returned %d\n", __func__, ret); + ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); + if (ret) { + debug("%s: Cannot find PMIC I2C chip\n", __func__); + return; + } /* TPS65913: LDO9_VOLTAGE = 3.3V */ data_buffer[0] = 0x31; reg = 0x61; - ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1); + ret = dm_i2c_write(dev, reg, data_buffer, 1); if (ret) printf("%s: PMU i2c_write %02X<-%02X returned %d\n", __func__, reg, data_buffer[0], ret); @@ -69,7 +74,7 @@ void board_sdmmc_voltage_init(void) data_buffer[0] = 0x01; reg = 0x60; - ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1); + ret = dm_i2c_write(dev, reg, data_buffer, 1); if (ret) printf("%s: PMU i2c_write %02X<-%02X returned %d\n", __func__, reg, data_buffer[0], ret); @@ -78,7 +83,12 @@ void board_sdmmc_voltage_init(void) data_buffer[0] = 0x03; reg = 0x14; - ret = i2c_write(BAT_I2C_ADDRESS, reg, 1, data_buffer, 1); + ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, 1, &dev); + if (ret) { + debug("%s: Cannot find charger I2C chip\n", __func__); + return; + } + ret = dm_i2c_write(dev, reg, data_buffer, 1); if (ret) printf("%s: BAT i2c_write %02X<-%02X returned %d\n", __func__, reg, data_buffer[0], ret); diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 8c05a1517c..891ac07dd9 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -17,9 +17,9 @@ #ifndef _PINMUX_CONFIG_DALMORE_H_ #define _PINMUX_CONFIG_DALMORE_H_ -#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ { \ - .pingroup = PINGRP_##_pingroup, \ + .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ @@ -29,9 +29,9 @@ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } -#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ { \ - .pingroup = PINGRP_##_pingroup, \ + .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ @@ -41,9 +41,9 @@ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } -#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ +#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ { \ - .pingroup = PINGRP_##_pingroup, \ + .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ @@ -53,9 +53,9 @@ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } -#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ +#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ { \ - .pingroup = PINGRP_##_pingroup, \ + .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ @@ -65,9 +65,9 @@ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ } -#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ +#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ { \ - .pingroup = PINGRP_##_pingroup, \ + .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ @@ -79,156 +79,156 @@ #define USB_PINMUX CEC_PINMUX -#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ { \ - .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ .slwf = _slwf, \ .slwr = _slwr, \ .drvup = _drvup, \ .drvdn = _drvdn, \ - .lpmd = PGRP_LPMD_##_lpmd, \ - .schmt = PGRP_SCHMT_##_schmt, \ - .hsm = PGRP_HSM_##_hsm, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ } -static struct pingroup_config tegra114_pinmux_common[] = { +static struct pmux_pingrp_config tegra114_pinmux_common[] = { /* EXTPERIPH1 pinmux */ - DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), /* I2S0 pinmux */ - DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), /* I2S1 pinmux */ - DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), /* I2S3 pinmux */ - DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), /* CLDVFS pinmux */ - DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT), /* ULPI pinmux */ - DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA4, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, OUTPUT), /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* VI pinmux */ - VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), /* VI_ALT1 pinmux */ - VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), /* VGP4 pinmux */ - VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + VI_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTD pinmux */ - DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), /* SPI4 pinmux */ - DEFAULT_PINMUX(GMI_AD5, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD6, SPI4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD7, SPI4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_CS6_N, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WR_N, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS6_N_PI3, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, SPI4, NORMAL, NORMAL, INPUT), /* PWM1 pinmux */ - DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), /* SOC pinmux */ - DEFAULT_PINMUX(GMI_CS1_N, SOC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_OE_N, SOC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_CS1_N_PJ2, SOC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, SOC, NORMAL, TRISTATE, INPUT), /* EXTPERIPH2 pinmux */ - DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT), /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT), /* SDMMC4 pinmux */ - DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT), /* BLINK pinmux */ - DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), /* KBC pinmux */ - DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), /*Audio Codec*/ - DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT), /* UARTA pinmux */ - DEFAULT_PINMUX(KB_ROW10, UARTA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT), /* I2CPWR pinmux (I2C5) */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* SYSCLK pinmux */ - DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), /* RTCK pinmux */ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), @@ -249,121 +249,121 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), /* EXTPERIPH3 pinmux */ - DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTB pinmux */ - DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), /* IRDA pinmux */ - DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT), /* UARTC pinmux */ - DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), /* OWR pinmux */ - DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), /* CEC pinmux */ - CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), /* I2C4 pinmux */ - DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), - DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), /* USB pinmux */ - USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* nct */ - DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_X6_AUD_PX6, SPI6, UP, TRISTATE, INPUT), }; -static struct pingroup_config unused_pins_lowpower[] = { - DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT), - DEFAULT_PINMUX(USB_VBUS_EN1, RSVD3, DOWN, TRISTATE, OUTPUT), +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(USB_VBUS_EN1_PN5, RSVD3, DOWN, TRISTATE, OUTPUT), }; /* Initially setting all used GPIO's to non-TRISTATE */ -static struct pingroup_config tegra114_pinmux_set_nontristate[] = { - DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_X5_AUD, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_W3_AUD, SPI6, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_X1_AUD, RSVD3, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(DAP3_FS, I2S2, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP3_DIN, I2S2, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP3_SCLK, I2S2, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(GPIO_PBB3, RSVD3, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PBB5, RSVD3, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PBB6, RSVD3, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PBB7, RSVD3, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PCC1, RSVD3, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC2, RSVD3, DOWN, NORMAL, INPUT), - - DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD10, GMI, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD11, GMI, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD12, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD13, GMI, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD8, GMI, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_ADV_N, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CLK, GMI, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_CS0_N, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS2_N, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS3_N, GMI, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_CS4_N, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS7_N, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_DQS, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_IORDY, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WP_N, GMI, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(SDMMC1_WP_N, SPI4, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT), - - DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW3, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW6, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(CLK3_REQ, RSVD3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT), - - DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), +static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = { + DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X6_AUD_PX6, RSVD3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X1_AUD_PX1, RSVD3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PBB3, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB5, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB6, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB7, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PCC1, RSVD3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10_PH2, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, GMI, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_DQS_P_PJ3, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC1_WP_N_PV3, SPI4, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, USB, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT), }; -static struct padctrl_config dalmore_padctrl[] = { - /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ +static struct pmux_drvgrp_config dalmore_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), }; diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts deleted file mode 100644 index b115f87821..0000000000 --- a/board/nvidia/dts/tegra20-harmony.dts +++ /dev/null @@ -1,105 +0,0 @@ -/dts-v1/; - -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Harmony evaluation board"; - compatible = "nvidia,harmony", "nvidia,tegra20"; - - aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5004000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000200"; - }; - - memory { - reg = <0x00000000 0x40000000>; - }; - - host1x { - status = "okay"; - dc@54200000 { - status = "okay"; - rgb { - status = "okay"; - nvidia,panel = <&lcd_panel>; - }; - }; - }; - - serial@70006300 { - clock-frequency = < 216000000 >; - }; - - nand-controller@70008000 { - nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ - nvidia,width = <8>; - nvidia,timing = <26 100 20 80 20 10 12 10 70>; - nand@0 { - reg = <0>; - compatible = "hynix,hy27uf4g2b", "nand-flash"; - }; - }; - - i2c@7000c000 { - status = "disabled"; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - - usb@c5000000 { - status = "disabled"; - }; - - usb@c5004000 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ - }; - - sdhci@c8000200 { - status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ - bus-width = <8>; - }; - - lcd_panel: panel { - clock = <42430000>; - xres = <1024>; - yres = <600>; - left-margin = <138>; - right-margin = <34>; - hsync-len = <136>; - lower-margin = <4>; - upper-margin = <21>; - vsync-len = <4>; - hsync-active-high; - vsyncx-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 0 0>; - nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */ - nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ - nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ - nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */ - nvidia,panel-timings = <0 0 200 0 0>; - }; -}; diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts deleted file mode 100644 index 1a526bab64..0000000000 --- a/board/nvidia/dts/tegra20-ventana.dts +++ /dev/null @@ -1,91 +0,0 @@ -/dts-v1/; - -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Ventana evaluation board"; - compatible = "nvidia,ventana", "nvidia,tegra20"; - - aliases { - usb0 = "/usb@c5008000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000400"; - }; - - memory { - reg = <0x00000000 0x40000000>; - }; - - host1x { - status = "okay"; - dc@54200000 { - status = "okay"; - rgb { - status = "okay"; - nvidia,panel = <&lcd_panel>; - }; - }; - }; - - serial@70006300 { - clock-frequency = < 216000000 >; - }; - - i2c@7000c000 { - status = "disabled"; - }; - - i2c@7000c400 { - status = "disabled"; - }; - - i2c@7000c500 { - status = "disabled"; - }; - - i2c@7000d000 { - status = "disabled"; - }; - - usb@c5000000 { - status = "disabled"; - }; - - usb@c5004000 { - status = "disabled"; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - }; - - lcd_panel: panel { - clock = <72072000>; - xres = <1366>; - yres = <768>; - left-margin = <58>; - right-margin = <58>; - hsync-len = <58>; - lower-margin = <4>; - upper-margin = <4>; - vsync-len = <4>; - hsync-active-high; - vsync-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 2 0>; - nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */ - nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ - nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ - nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */ - nvidia,panel-timings = <0 0 200 0 0>; - }; -}; diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts deleted file mode 100644 index a7cc93e93f..0000000000 --- a/board/nvidia/dts/tegra30-beaver.dts +++ /dev/null @@ -1,77 +0,0 @@ -/dts-v1/; - -#include "tegra30.dtsi" - -/ { - model = "NVIDIA Beaver"; - compatible = "nvidia,beaver", "nvidia,tegra30"; - - aliases { - i2c0 = "/i2c@7000d000"; - i2c1 = "/i2c@7000c000"; - i2c2 = "/i2c@7000c400"; - i2c3 = "/i2c@7000c500"; - i2c4 = "/i2c@7000c700"; - sdhci0 = "/sdhci@78000600"; - sdhci1 = "/sdhci@78000000"; - usb0 = "/usb@7d008000"; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x7ff00000>; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@1 { - compatible = "winbond,w25q32"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - - sdhci@78000000 { - status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - }; - - usb@7d008000 { - nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */ - status = "okay"; - }; -}; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts deleted file mode 100644 index ea2cf76ff3..0000000000 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ /dev/null @@ -1,72 +0,0 @@ -/dts-v1/; - -#include "tegra30.dtsi" - -/ { - model = "NVIDIA Cardhu"; - compatible = "nvidia,cardhu", "nvidia,tegra30"; - - aliases { - i2c0 = "/i2c@7000d000"; - i2c1 = "/i2c@7000c000"; - i2c2 = "/i2c@7000c400"; - i2c3 = "/i2c@7000c500"; - i2c4 = "/i2c@7000c700"; - sdhci0 = "/sdhci@78000600"; - sdhci1 = "/sdhci@78000000"; - usb0 = "/usb@7d008000"; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - sdhci@78000000 { - status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - }; - - usb@7d008000 { - nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */ - status = "okay"; - }; -}; diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig new file mode 100644 index 0000000000..328c94677d --- /dev/null +++ b/board/nvidia/harmony/Kconfig @@ -0,0 +1,12 @@ +if TARGET_HARMONY + +config SYS_BOARD + default "harmony" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "harmony" + +endif diff --git a/board/nvidia/harmony/MAINTAINERS b/board/nvidia/harmony/MAINTAINERS new file mode 100644 index 0000000000..f3508edc3f --- /dev/null +++ b/board/nvidia/harmony/MAINTAINERS @@ -0,0 +1,6 @@ +HARMONY BOARD +M: Tom Warren +S: Maintained +F: board/nvidia/harmony/ +F: include/configs/harmony.h +F: configs/harmony_defconfig diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile index a55c1f92e0..222b025e9c 100644 --- a/board/nvidia/harmony/Makefile +++ b/board/nvidia/harmony/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := harmony.o diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index b74c219347..c892a25751 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -25,28 +25,28 @@ void pin_mux_mmc(void) funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT); /* For power GPIO PI6 */ - pinmux_tristate_disable(PINGRP_ATA); + pinmux_tristate_disable(PMUX_PINGRP_ATA); /* For CD GPIO PH2 */ - pinmux_tristate_disable(PINGRP_ATD); + pinmux_tristate_disable(PMUX_PINGRP_ATD); /* For power GPIO PT3 */ - pinmux_tristate_disable(PINGRP_DTB); + pinmux_tristate_disable(PMUX_PINGRP_DTB); /* For CD GPIO PI5 */ - pinmux_tristate_disable(PINGRP_ATC); + pinmux_tristate_disable(PMUX_PINGRP_ATC); } #endif void pin_mux_usb(void) { funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); - pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); - pinmux_tristate_disable(PINGRP_CDEV2); + pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PMUX_PINGRP_CDEV2); /* USB2 PHY reset GPIO */ - pinmux_tristate_disable(PINGRP_UAC); + pinmux_tristate_disable(PMUX_PINGRP_UAC); } void pin_mux_display(void) { - pinmux_set_func(PINGRP_SDC, PMUX_FUNC_PWM); - pinmux_tristate_disable(PINGRP_SDC); + pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_SDC); } diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig new file mode 100644 index 0000000000..d90a74ea38 --- /dev/null +++ b/board/nvidia/jetson-tk1/Kconfig @@ -0,0 +1,12 @@ +if TARGET_JETSON_TK1 + +config SYS_BOARD + default "jetson-tk1" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "jetson-tk1" + +endif diff --git a/board/nvidia/jetson-tk1/MAINTAINERS b/board/nvidia/jetson-tk1/MAINTAINERS new file mode 100644 index 0000000000..a5c687d149 --- /dev/null +++ b/board/nvidia/jetson-tk1/MAINTAINERS @@ -0,0 +1,6 @@ +JETSON-TK1 BOARD +M: Stephen Warren +S: Maintained +F: board/nvidia/jetson-tk1/ +F: include/configs/jetson-tk1.h +F: configs/jetson-tk1_defconfig diff --git a/board/nvidia/jetson-tk1/Makefile b/board/nvidia/jetson-tk1/Makefile new file mode 100644 index 0000000000..0f054117c4 --- /dev/null +++ b/board/nvidia/jetson-tk1/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ../venice2/as3722_init.o +obj-y += jetson-tk1.o diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c new file mode 100644 index 0000000000..daa74a4be0 --- /dev/null +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include +#include + +#include "pinmux-config-jetson-tk1.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_set_tristate_input_clamping(); + + gpio_config_table(jetson_tk1_gpio_inits, + ARRAY_SIZE(jetson_tk1_gpio_inits)); + + pinmux_config_pingrp_table(jetson_tk1_pingrps, + ARRAY_SIZE(jetson_tk1_pingrps)); + + pinmux_config_drvgrp_table(jetson_tk1_drvgrps, + ARRAY_SIZE(jetson_tk1_drvgrps)); +} + +#ifdef CONFIG_PCI_TEGRA +int tegra_pcie_board_init(void) +{ + struct udevice *pmic; + int err; + + err = as3722_init(&pmic); + if (err) { + error("failed to initialize AS3722 PMIC: %d\n", err); + return err; + } + + err = as3722_sd_enable(pmic, 4); + if (err < 0) { + error("failed to enable SD4: %d\n", err); + return err; + } + + err = as3722_sd_set_voltage(pmic, 4, 0x24); + if (err < 0) { + error("failed to set SD4 voltage: %d\n", err); + return err; + } + + err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH | + AS3722_GPIO_INVERT); + if (err < 0) { + error("failed to configure GPIO#1 as output: %d\n", err); + return err; + } + + err = as3722_gpio_direction_output(pmic, 2, 1); + if (err < 0) { + error("failed to set GPIO#2 high: %d\n", err); + return err; + } + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} +#endif /* PCI */ diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h new file mode 100644 index 0000000000..de4eb35598 --- /dev/null +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_JETSON_TK1_H_ +#define _PINMUX_CONFIG_JETSON_TK1_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(C7, IN), + GPIO_INIT(G0, OUT0), + GPIO_INIT(G1, OUT0), + GPIO_INIT(G2, IN), + GPIO_INIT(G3, IN), + GPIO_INIT(H2, OUT0), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, IN), + GPIO_INIT(H5, OUT0), + GPIO_INIT(H6, IN), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I4, OUT0), + GPIO_INIT(I5, IN), + GPIO_INIT(I6, IN), + GPIO_INIT(J0, IN), + GPIO_INIT(J2, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, IN), + GPIO_INIT(K3, IN), + GPIO_INIT(K4, OUT0), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, OUT0), + GPIO_INIT(N7, IN), + GPIO_INIT(O0, IN), + GPIO_INIT(O1, IN), + GPIO_INIT(O2, IN), + GPIO_INIT(O3, IN), + GPIO_INIT(O4, IN), + GPIO_INIT(O5, IN), + GPIO_INIT(O6, OUT0), + GPIO_INIT(O7, IN), + GPIO_INIT(P0, OUT0), + GPIO_INIT(P1, OUT0), + GPIO_INIT(P2, OUT0), + GPIO_INIT(Q0, IN), + GPIO_INIT(Q1, IN), + GPIO_INIT(Q2, IN), + GPIO_INIT(Q5, IN), + GPIO_INIT(Q6, IN), + GPIO_INIT(Q7, IN), + GPIO_INIT(R0, OUT0), + GPIO_INIT(R1, OUT0), + GPIO_INIT(R2, OUT0), + GPIO_INIT(R4, IN), + GPIO_INIT(R5, OUT0), + GPIO_INIT(R7, IN), + GPIO_INIT(S0, IN), + GPIO_INIT(S3, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, IN), + GPIO_INIT(S6, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(U0, OUT0), + GPIO_INIT(U1, IN), + GPIO_INIT(U2, IN), + GPIO_INIT(U3, OUT0), + GPIO_INIT(U4, OUT0), + GPIO_INIT(U5, IN), + GPIO_INIT(U6, IN), + GPIO_INIT(V0, IN), + GPIO_INIT(V1, IN), + GPIO_INIT(W2, IN), + GPIO_INIT(W3, IN), + GPIO_INIT(X1, OUT0), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, OUT0), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(BB5, OUT0), + GPIO_INIT(BB6, OUT0), + GPIO_INIT(BB7, OUT0), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC2, IN), + GPIO_INIT(CC5, OUT0), + GPIO_INIT(EE1, OUT0), + GPIO_INIT(FF1, OUT0), + GPIO_INIT(FF2, IN), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ + PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), + PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_JETSON_TK1_H */ diff --git a/board/nvidia/nyan-big/Kconfig b/board/nvidia/nyan-big/Kconfig new file mode 100644 index 0000000000..341c8d75c2 --- /dev/null +++ b/board/nvidia/nyan-big/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NYAN_BIG + +config SYS_BOARD + default "nyan-big" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "nyan-big" + +endif diff --git a/board/nvidia/nyan-big/MAINTAINERS b/board/nvidia/nyan-big/MAINTAINERS new file mode 100644 index 0000000000..ff74627af2 --- /dev/null +++ b/board/nvidia/nyan-big/MAINTAINERS @@ -0,0 +1,6 @@ +NORRIN BOARD +M: Allen Martin +S: Maintained +F: board/nvidia/nyan-big/ +F: include/configs/nyan-big.h +F: configs/nyan-big_defconfig diff --git a/board/nvidia/nyan-big/Makefile b/board/nvidia/nyan-big/Makefile new file mode 100644 index 0000000000..cd2f61dc9d --- /dev/null +++ b/board/nvidia/nyan-big/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ../venice2/as3722_init.o +obj-y += nyan-big.o diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c new file mode 100644 index 0000000000..d4d2496639 --- /dev/null +++ b/board/nvidia/nyan-big/nyan-big.c @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "pinmux-config-nyan-big.h" + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + gpio_config_table(nyan_big_gpio_inits, + ARRAY_SIZE(nyan_big_gpio_inits)); + + pinmux_config_pingrp_table(nyan_big_pingrps, + ARRAY_SIZE(nyan_big_pingrps)); + + pinmux_config_drvgrp_table(nyan_big_drvgrps, + ARRAY_SIZE(nyan_big_drvgrps)); +} diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h new file mode 100644 index 0000000000..9c5fbaa7aa --- /dev/null +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_NYAN_BIG_H_ +#define _PINMUX_CONFIG_NYAN_BIG_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config nyan_big_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A0, IN), + GPIO_INIT(C7, IN), + GPIO_INIT(G0, IN), + GPIO_INIT(G1, IN), + GPIO_INIT(G2, IN), + GPIO_INIT(G3, IN), + GPIO_INIT(H2, IN), + GPIO_INIT(H4, IN), + GPIO_INIT(H6, IN), + GPIO_INIT(H7, OUT1), + GPIO_INIT(I0, IN), + GPIO_INIT(I1, IN), + GPIO_INIT(I5, OUT1), + GPIO_INIT(I6, IN), + GPIO_INIT(I7, IN), + GPIO_INIT(J0, IN), + GPIO_INIT(J7, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, IN), + GPIO_INIT(K4, OUT0), + GPIO_INIT(K6, OUT0), + GPIO_INIT(K7, IN), + GPIO_INIT(N7, IN), + GPIO_INIT(P2, OUT0), + GPIO_INIT(Q0, IN), + GPIO_INIT(Q2, IN), + GPIO_INIT(Q3, IN), + GPIO_INIT(Q6, IN), + GPIO_INIT(Q7, IN), + GPIO_INIT(R0, OUT0), + GPIO_INIT(R1, IN), + GPIO_INIT(R4, IN), + GPIO_INIT(R7, IN), + GPIO_INIT(S3, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S7, IN), + GPIO_INIT(T1, IN), + GPIO_INIT(U4, IN), + GPIO_INIT(U5, IN), + GPIO_INIT(U6, IN), + GPIO_INIT(V0, IN), + GPIO_INIT(W3, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +static const struct pmux_pingrp_config nyan_big_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ + PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config nyan_big_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_NYAN_BIG_H */ diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig new file mode 100644 index 0000000000..0924bde480 --- /dev/null +++ b/board/nvidia/seaboard/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SEABOARD + +config SYS_BOARD + default "seaboard" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "seaboard" + +endif diff --git a/board/nvidia/seaboard/MAINTAINERS b/board/nvidia/seaboard/MAINTAINERS new file mode 100644 index 0000000000..7926ca19a8 --- /dev/null +++ b/board/nvidia/seaboard/MAINTAINERS @@ -0,0 +1,6 @@ +SEABOARD BOARD +M: Tom Warren +S: Maintained +F: board/nvidia/seaboard/ +F: include/configs/seaboard.h +F: configs/seaboard_defconfig diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile index a55c1f92e0..9171418467 100644 --- a/board/nvidia/seaboard/Makefile +++ b/board/nvidia/seaboard/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := seaboard.o diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index ef4e481c75..11472ebaf2 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -22,7 +23,7 @@ void gpio_early_init_uart(void) #ifndef CONFIG_SPL_BUILD gpio_request(GPIO_PI3, NULL); #endif - gpio_direction_output(GPIO_PI3, 0); + tegra_spl_gpio_direction_output(GPIO_PI3, 0); } #endif @@ -37,14 +38,14 @@ void pin_mux_mmc(void) funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT); /* For power GPIO PI6 */ - pinmux_tristate_disable(PINGRP_ATA); + pinmux_tristate_disable(PMUX_PINGRP_ATA); /* For CD GPIO PI5 */ - pinmux_tristate_disable(PINGRP_ATC); + pinmux_tristate_disable(PMUX_PINGRP_ATC); } #endif void pin_mux_usb(void) { /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ - pinmux_tristate_disable(PINGRP_SLXK); + pinmux_tristate_disable(PMUX_PINGRP_SLXK); } diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig new file mode 100644 index 0000000000..6905f0014e --- /dev/null +++ b/board/nvidia/venice2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_VENICE2 + +config SYS_BOARD + default "venice2" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "venice2" + +endif diff --git a/board/nvidia/venice2/MAINTAINERS b/board/nvidia/venice2/MAINTAINERS new file mode 100644 index 0000000000..221df654d7 --- /dev/null +++ b/board/nvidia/venice2/MAINTAINERS @@ -0,0 +1,6 @@ +VENICE2 BOARD +M: Tom Warren +S: Maintained +F: board/nvidia/venice2/ +F: include/configs/venice2.h +F: configs/venice2_defconfig diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/venice2/Makefile new file mode 100644 index 0000000000..5fac5ab1f8 --- /dev/null +++ b/board/nvidia/venice2/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += as3722_init.o +obj-y += venice2.o diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c new file mode 100644 index 0000000000..960fea7ee7 --- /dev/null +++ b/board/nvidia/venice2/as3722_init.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "as3722_init.h" + +/* AS3722-PMIC-specific early init code - get CPU rails up, etc */ + +void tegra_i2c_ll_write_addr(uint addr, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(addr, ®->cmd_addr0); + writel(config, ®->cnfg); +} + +void tegra_i2c_ll_write_data(uint data, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(data, ®->cmd_data1); + writel(config, ®->cnfg); +} + +void pmic_enable_cpu_vdd(void) +{ + debug("%s entry\n", __func__); + + /* Don't need to set up VDD_CORE - already done - by OTP */ + + debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); + /* + * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.0V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__); + /* + * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.0V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__); + /* + * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.2V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__); + /* + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. + * First set it to bypass 3.3V straight thru, then enable the regulator + * + * NOTE: We do this early because doing it later seems to hose the CPU + * power rail/partition startup. Need to debug. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); +} diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h new file mode 100644 index 0000000000..992b11f643 --- /dev/null +++ b/board/nvidia/venice2/as3722_init.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* AS3722-PMIC-specific early init regs */ + +#define AS3722_I2C_ADDR 0x80 + +#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */ +#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */ +#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */ +#define AS3722_SDCONTROL_REG 0x4D + +#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */ +#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */ +#define AS3722_LDCONTROL_REG 0x4E + +#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NYAN_BIG) +#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG) +#else +#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG) +#endif +#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) + +#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) +#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) + +#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) +#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) + +#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG) +#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG) + +#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG) +#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG) + +#define I2C_SEND_2_BYTES 0x0A02 + +void pmic_enable_cpu_vdd(void); diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h new file mode 100644 index 0000000000..bf8e3fd965 --- /dev/null +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_VENICE2_H_ +#define _PINMUX_CONFIG_VENICE2_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config venice2_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A0, IN), + GPIO_INIT(C7, IN), + GPIO_INIT(G0, IN), + GPIO_INIT(G1, IN), + GPIO_INIT(G2, IN), + GPIO_INIT(G3, IN), + GPIO_INIT(H2, IN), + GPIO_INIT(H4, IN), + GPIO_INIT(H5, OUT0), + GPIO_INIT(H6, IN), + GPIO_INIT(H7, OUT1), + GPIO_INIT(I0, IN), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I4, OUT0), + GPIO_INIT(I5, OUT1), + GPIO_INIT(I6, IN), + GPIO_INIT(J0, IN), + GPIO_INIT(J7, IN), + GPIO_INIT(K0, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, IN), + GPIO_INIT(K3, IN), + GPIO_INIT(K4, OUT0), + GPIO_INIT(K6, OUT0), + GPIO_INIT(K7, IN), + GPIO_INIT(N7, IN), + GPIO_INIT(O2, IN), + GPIO_INIT(O5, IN), + GPIO_INIT(O6, OUT0), + GPIO_INIT(O7, IN), + GPIO_INIT(P2, OUT0), + GPIO_INIT(Q0, IN), + GPIO_INIT(Q2, IN), + GPIO_INIT(Q3, IN), + GPIO_INIT(Q6, IN), + GPIO_INIT(Q7, IN), + GPIO_INIT(R0, OUT0), + GPIO_INIT(R1, IN), + GPIO_INIT(R4, IN), + GPIO_INIT(S0, IN), + GPIO_INIT(S3, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S7, IN), + GPIO_INIT(T1, IN), + GPIO_INIT(U4, IN), + GPIO_INIT(U5, IN), + GPIO_INIT(U6, IN), + GPIO_INIT(V0, IN), + GPIO_INIT(V1, IN), + GPIO_INIT(W3, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X7, OUT0), + GPIO_INIT(CC5, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +static const struct pmux_pingrp_config venice2_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ + PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU1, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config venice2_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_VENICE2_H */ diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c new file mode 100644 index 0000000000..c56ef129d6 --- /dev/null +++ b/board/nvidia/venice2/venice2.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "pinmux-config-venice2.h" + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_set_tristate_input_clamping(); + + gpio_config_table(venice2_gpio_inits, + ARRAY_SIZE(venice2_gpio_inits)); + + pinmux_config_pingrp_table(venice2_pingrps, + ARRAY_SIZE(venice2_pingrps)); + + pinmux_config_drvgrp_table(venice2_drvgrps, + ARRAY_SIZE(venice2_drvgrps)); +} diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig new file mode 100644 index 0000000000..c1ad7b7671 --- /dev/null +++ b/board/nvidia/ventana/Kconfig @@ -0,0 +1,12 @@ +if TARGET_VENTANA + +config SYS_BOARD + default "ventana" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "ventana" + +endif diff --git a/board/nvidia/ventana/MAINTAINERS b/board/nvidia/ventana/MAINTAINERS new file mode 100644 index 0000000000..285b84dbdc --- /dev/null +++ b/board/nvidia/ventana/MAINTAINERS @@ -0,0 +1,7 @@ +VENTANA BOARD +M: Tom Warren +M: Stephen Warren +S: Maintained +F: board/nvidia/ventana/ +F: include/configs/ventana.h +F: configs/ventana_defconfig diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile index 9c2349dc6a..f67044f2cf 100644 --- a/board/nvidia/ventana/Makefile +++ b/board/nvidia/ventana/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -$(shell mkdir -p $(obj)../seaboard) - -LIB = $(obj)lib$(BOARD).o - -COBJS = ../seaboard/seaboard.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = ../seaboard/seaboard.o diff --git a/board/nvidia/whistler/Kconfig b/board/nvidia/whistler/Kconfig new file mode 100644 index 0000000000..5febc07777 --- /dev/null +++ b/board/nvidia/whistler/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WHISTLER + +config SYS_BOARD + default "whistler" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "whistler" + +endif diff --git a/board/nvidia/whistler/MAINTAINERS b/board/nvidia/whistler/MAINTAINERS new file mode 100644 index 0000000000..66e2c8d082 --- /dev/null +++ b/board/nvidia/whistler/MAINTAINERS @@ -0,0 +1,7 @@ +WHISTLER BOARD +M: Tom Warren +M: Stephen Warren +S: Maintained +F: board/nvidia/whistler/ +F: include/configs/whistler.h +F: configs/whistler_defconfig diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile index 4a92d7a86d..b54c5fd338 100644 --- a/board/nvidia/whistler/Makefile +++ b/board/nvidia/whistler/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := whistler.o diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 3e9d3d9f10..3476f1159f 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -21,23 +22,26 @@ */ void pin_mux_mmc(void) { + struct udevice *dev; uchar val; int ret; /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ - ret = i2c_set_bus_num(0); - if (ret) - printf("i2c_set_bus_num failed: %d\n", ret); + ret = i2c_get_chip_for_busnum(0, 0x3c, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX8907B I2C chip\n", __func__); + return; + } val = 0x29; - ret = i2c_write(0x3c, 0x46, 1, &val, 1); + ret = dm_i2c_write(dev, 0x46, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); val = 0x00; - ret = i2c_write(0x3c, 0x45, 1, &val, 1); + ret = dm_i2c_write(dev, 0x45, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); val = 0x1f; - ret = i2c_write(0x3c, 0x44, 1, &val, 1); + ret = dm_i2c_write(dev, 0x44, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); @@ -49,6 +53,7 @@ void pin_mux_mmc(void) /* this is a weak define that we are overriding */ void pin_mux_usb(void) { + struct udevice *dev; uchar val; int ret; @@ -59,15 +64,17 @@ void pin_mux_usb(void) */ /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */ - ret = i2c_set_bus_num(0); - if (ret) - printf("i2c_set_bus_num failed: %d\n", ret); + ret = i2c_get_chip_for_busnum(0, 0x20, 1, &dev); + if (ret) { + printf("%s: Cannot find TAC6416 I2C chip\n", __func__); + return; + } val = 0x03; - ret = i2c_write(0x20, 2, 1, &val, 1); + ret = dm_i2c_write(dev, 2, &val, 1); if (ret) printf("i2c_write 0 0x20 2 failed: %d\n", ret); val = 0xfc; - ret = i2c_write(0x20, 6, 1, &val, 1); + ret = dm_i2c_write(dev, 6, &val, 1); if (ret) printf("i2c_write 0 0x20 6 failed: %d\n", ret); } diff --git a/board/nx823/Makefile b/board/nx823/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/nx823/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/nx823/flash.c b/board/nx823/flash.c deleted file mode 100644 index fbe17dd966..0000000000 --- a/board/nx823/flash.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); break; - default: printf ("Unknown Chip Type\n"); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0x00AA00AA; - addr[0x2AAA] = (FPW)0x00550055; - addr[0x5555] = (FPW)0x00900090; - - value = addr[0]; - - switch (value) { - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (FPW)INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0x00B000B0; /* suspend erase */ - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* save sernum if needed */ - if (addr >= CONFIG_SYS_FLASH_SN_SECTOR && addr < CONFIG_SYS_FLASH_SN_BASE) - { - u_long dest = CONFIG_SYS_FLASH_SN_BASE; - u_short *sn = (u_short *)gd->bd->bi_sernum; - - printf("(saving sernum)"); - for (i=0; i<4; i++) - { - if ((rc = write_data(info, dest, sn[i])) != 0) { - return (rc); - } - dest += port_width; - } - } - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= port_width) { - data = 0; - for (i=0; i 0x800) - { - putc('.'); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW)0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c deleted file mode 100644 index d49fa8ca21..0000000000 --- a/board/nx823/nx823.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static long int dram_size (long int, long int *, long int); - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { -#if (MPC8XX_SPEED <= 50000000L) - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07, - 0xFFFFFFFF, - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FE7F434, 0xEFABE834, 0x1FA7D435, - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF -#else - - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800, - 0x1FF7F447, - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF7F434, 0xEFEBE834, 0x1FB7D435, - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - printf ("Board: Nexus NX823"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Up to 2 Banks of 64Mbit x 2 devices - * Initial builds only have 1 - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - memctl->memc_mar = 0x00000088; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - udelay (200); - - /* - * Map controller SDRAM bank 1 - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); -/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | - CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | - BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br1 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | - CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | - BR_V) - + size_b0; - } else { - unsigned long reg; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -int misc_init_r (void) -{ - int i; - char tmp[50]; - uchar ethaddr[6]; - bd_t *bd = gd->bd; - ulong *my_sernum = (unsigned long *)&bd->bi_sernum; - - /* load unique serial number */ - for (i = 0; i < 8; ++i) - bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i); - - /* save env variables according to sernum */ - sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]); - setenv ("serial#", tmp); - - if (!eth_getenv_enetaddr("ethaddr", ethaddr)) { - ethaddr[0] = 0x10; - ethaddr[1] = 0x20; - ethaddr[2] = 0x30; - ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2]; - ethaddr[4] = bd->bi_sernum[5]; - ethaddr[5] = bd->bi_sernum[6]; - } - - return 0; -} diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds deleted file mode 100644 index 7ae91ffb2e..0000000000 --- a/board/nx823/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug deleted file mode 100644 index b0091db0c6..0000000000 --- a/board/nx823/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/olimex/mx23_olinuxino/Kconfig b/board/olimex/mx23_olinuxino/Kconfig new file mode 100644 index 0000000000..0b151c9bb8 --- /dev/null +++ b/board/olimex/mx23_olinuxino/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX23_OLINUXINO + +config SYS_BOARD + default "mx23_olinuxino" + +config SYS_VENDOR + default "olimex" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "mx23_olinuxino" + +endif diff --git a/board/olimex/mx23_olinuxino/MAINTAINERS b/board/olimex/mx23_olinuxino/MAINTAINERS new file mode 100644 index 0000000000..25f4a10e9a --- /dev/null +++ b/board/olimex/mx23_olinuxino/MAINTAINERS @@ -0,0 +1,6 @@ +MX23_OLINUXINO BOARD +M: Marek Vasut +S: Maintained +F: board/olimex/mx23_olinuxino/ +F: include/configs/mx23_olinuxino.h +F: configs/mx23_olinuxino_defconfig diff --git a/board/olimex/mx23_olinuxino/Makefile b/board/olimex/mx23_olinuxino/Makefile index c735e359c3..133114c08d 100644 --- a/board/olimex/mx23_olinuxino/Makefile +++ b/board/olimex/mx23_olinuxino/Makefile @@ -5,27 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifndef CONFIG_SPL_BUILD -COBJS := mx23_olinuxino.o +obj-y := mx23_olinuxino.o else -COBJS := spl_boot.o +obj-y := spl_boot.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index e2a03a110b..65cbbf15b7 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -30,13 +30,25 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + return 0; +} + #ifdef CONFIG_CMD_USB - /* Enable LAN9512 */ +int board_ehci_hcd_init(int port) +{ + /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */ gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1); -#endif + udelay(100); + return 0; +} +int board_ehci_hcd_exit(int port) +{ + /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */ + gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0); return 0; } +#endif int dram_init(void) { diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 0a6630395d..de3b0e4c8b 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -85,7 +85,37 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), }; -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} + +/* Fine-tune the DRAM configuration. */ +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* Enable Auto Precharge. */ + dram_vals[3] |= 1 << 8; + /* Enable Fast Writes. */ + dram_vals[5] |= 1 << 8; + /* tEMRS = 3*tCK */ + dram_vals[10] &= ~(0x3 << 8); + dram_vals[10] |= (0x3 << 8); + /* CASLAT = 3*tCK */ + dram_vals[11] &= ~(0x3 << 0); + dram_vals[11] |= (0x3 << 0); + /* tCKE = 1*tCK */ + dram_vals[12] &= ~(0x7 << 0); + dram_vals[12] |= (0x1 << 0); + /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ + dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0)); + dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0); + /* tDAL = 6*tCK */ + dram_vals[15] &= ~(0xf << 16); + dram_vals[15] |= (0x6 << 16); + /* tREF = 1040*tCK */ + dram_vals[26] &= ~0xffff; + dram_vals[26] |= 0x0410; + /* tRAS_MAX = 9334*tCK */ + dram_vals[32] &= ~0xffff; + dram_vals[32] |= 0x2475; } diff --git a/board/omicron/calimain/Kconfig b/board/omicron/calimain/Kconfig new file mode 100644 index 0000000000..1ec48e6b55 --- /dev/null +++ b/board/omicron/calimain/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CALIMAIN + +config SYS_BOARD + default "calimain" + +config SYS_VENDOR + default "omicron" + +config SYS_CONFIG_NAME + default "calimain" + +endif diff --git a/board/omicron/calimain/MAINTAINERS b/board/omicron/calimain/MAINTAINERS new file mode 100644 index 0000000000..f6e37a24b3 --- /dev/null +++ b/board/omicron/calimain/MAINTAINERS @@ -0,0 +1,7 @@ +CALIMAIN BOARD +M: Manfred Rudigier +M: Christian Riesch +S: Maintained +F: board/omicron/calimain/ +F: include/configs/calimain.h +F: configs/calimain_defconfig diff --git a/board/omicron/calimain/Makefile b/board/omicron/calimain/Makefile index 16e390d80b..59c118d074 100644 --- a/board/omicron/calimain/Makefile +++ b/board/omicron/calimain/Makefile @@ -7,23 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := calimain.o diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c index dd28915cdc..32f2b20183 100644 --- a/board/omicron/calimain/calimain.c +++ b/board/omicron/calimain/calimain.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/openrisc/openrisc-generic/Kconfig b/board/openrisc/openrisc-generic/Kconfig new file mode 100644 index 0000000000..cd2a94f025 --- /dev/null +++ b/board/openrisc/openrisc-generic/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OPENRISC_GENERIC + +config SYS_BOARD + default "openrisc-generic" + +config SYS_VENDOR + default "openrisc" + +config SYS_CONFIG_NAME + default "openrisc-generic" + +endif diff --git a/board/openrisc/openrisc-generic/MAINTAINERS b/board/openrisc/openrisc-generic/MAINTAINERS new file mode 100644 index 0000000000..c8dbc742e2 --- /dev/null +++ b/board/openrisc/openrisc-generic/MAINTAINERS @@ -0,0 +1,6 @@ +OPENRISC-GENERIC BOARD +M: Stefan Kristiansson +S: Maintained +F: board/openrisc/openrisc-generic/ +F: include/configs/openrisc-generic.h +F: configs/openrisc-generic_defconfig diff --git a/board/openrisc/openrisc-generic/Makefile b/board/openrisc/openrisc-generic/Makefile index bd15345b29..342bc80450 100644 --- a/board/openrisc/openrisc-generic/Makefile +++ b/board/openrisc/openrisc-generic/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := openrisc-generic.o diff --git a/board/openrisc/openrisc-generic/or1ksim.cfg b/board/openrisc/openrisc-generic/or1ksim.cfg index 9926093a40..2bd8642932 100644 --- a/board/openrisc/openrisc-generic/or1ksim.cfg +++ b/board/openrisc/openrisc-generic/or1ksim.cfg @@ -20,8 +20,8 @@ the simulator. not found too, it reverts to the built-in default configuration. NOTE: Users should not rely on the built-in configuration, since the - default configuration may differ between version. - Rather create a configuration file that sets all critical values. + default configuration may differ between version. + Rather create a configuration file that sets all critical values. This file may contain (standard C) comments only - no // support. @@ -306,7 +306,7 @@ end debug = 0-9 0 : no debug messages 1-9: debug message level. - higher numbers produce more messages + higher numbers produce more messages profile = 0/1 '0': don't generate profiling file 'sim.profile' @@ -375,11 +375,11 @@ end Core Verification. enabled = 0/1 - '0': disbable VAPI server - '1': enable/start VAPI server + '0': disbable VAPI server + '1': enable/start VAPI server server_port = - TCP/IP port to start VAPI server on + TCP/IP port to start VAPI server on log_enabled = 0/1 '0': disable VAPI requests logging @@ -565,56 +565,56 @@ end This section configures the UARTs enabled = <0|1> - Enable/disable the peripheral. By default if it is enabled. + Enable/disable the peripheral. By default if it is enabled. baseaddr = - address of first UART register for this device + address of first UART register for this device channel = : - The channel parameter indicates the source of received UART characters - and the sink for transmitted UART characters. + The channel parameter indicates the source of received UART characters + and the sink for transmitted UART characters. - The can be either "file", "xterm", "tcp", "fd", or "tty" - (without quotes). + The can be either "file", "xterm", "tcp", "fd", or "tty" + (without quotes). - A) To send/receive characters from a pair of files, use a file - channel: + A) To send/receive characters from a pair of files, use a file + channel: - channel=file:, + channel=file:, B) To create an interactive terminal window, use an xterm channel: - channel=xterm:[]* + channel=xterm:[]* C) To create a bidirectional tcp socket which one could, for example, - access via telnet, use a tcp channel: + access via telnet, use a tcp channel: - channel=tcp: + channel=tcp: D) To cause the UART to read/write from existing numeric file - descriptors, use an fd channel: + descriptors, use an fd channel: - channel=fd:, + channel=fd:, - E) To connect the UART to a physical serial port, create a tty - channel: + E) To connect the UART to a physical serial port, create a tty + channel: channel=tty:device=/dev/ttyS0,baud=9600 irq = - irq number for this device + irq number for this device 16550 = 0/1 - '0': this device is a UART16450 - '1': this device is a UART16550 + '0': this device is a UART16450 + '1': this device is a UART16550 jitter = - in msecs... time to block, -1 to disable it + in msecs... time to block, -1 to disable it vapi_id = - VAPI id of this instance + VAPI id of this instance */ section uart @@ -634,16 +634,16 @@ end This section configures the DMAs enabled = <0|1> - Enable/disable the peripheral. By default if it is enabled. + Enable/disable the peripheral. By default if it is enabled. baseaddr = - address of first DMA register for this device + address of first DMA register for this device irq = - irq number for this device + irq number for this device vapi_id = - VAPI id of this instance + VAPI id of this instance */ section dma @@ -658,37 +658,37 @@ end This section configures the ETHERNETs enabled = <0|1> - Enable/disable the peripheral. By default if it is enabled. + Enable/disable the peripheral. By default if it is enabled. baseaddr = - address of first ethernet register for this device + address of first ethernet register for this device dma = - which controller is this ethernet "connected" to + which controller is this ethernet "connected" to irq = - ethernet mac IRQ level + ethernet mac IRQ level rtx_type = - use 0 - file interface, 1 - socket interface + use 0 - file interface, 1 - socket interface rx_channel = - DMA channel used for RX + DMA channel used for RX tx_channel = - DMA channel used for TX + DMA channel used for TX rxfile = "" - filename, where to read data from + filename, where to read data from txfile = "" - filename, where to write data to + filename, where to write data to sockif = "" - interface name of ethernet socket + interface name of ethernet socket vapi_id = - VAPI id of this instance + VAPI id of this instance */ section ethernet @@ -711,16 +711,16 @@ end This section configures the GPIOs enabled = <0|1> - Enable/disable the peripheral. By default if it is enabled. + Enable/disable the peripheral. By default if it is enabled. baseaddr = - address of first GPIO register for this device + address of first GPIO register for this device irq = - irq number for this device + irq number for this device base_vapi_id = - first VAPI id of this instance + first VAPI id of this instance GPIO uses 8 consecutive VAPI IDs */ @@ -736,19 +736,19 @@ end This section configures the VGA/LCD controller enabled = <0|1> - Enable/disable the peripheral. By default if it is enabled. + Enable/disable the peripheral. By default if it is enabled. baseaddr = - address of first VGA register + address of first VGA register irq = - irq number for this device + irq number for this device refresh_rate = - number of cycles between screen dumps + number of cycles between screen dumps filename = "" - template name for generated names (e.g. "primary" produces "primary0023.bmp") + template name for generated names (e.g. "primary" produces "primary0023.bmp") */ section vga @@ -825,39 +825,39 @@ end This section configures the ATA/ATAPI host controller baseaddr = - address of first ATA register + address of first ATA register enabled = <0|1> - Enable/disable the peripheral. By default if it is enabled. + Enable/disable the peripheral. By default if it is enabled. irq = - irq number for this device + irq number for this device debug = - debug level for ata models. + debug level for ata models. 0: no debug messages 1: verbose messages 3: normal messages (more messages than verbose) - 5: debug messages (normal debug messages) + 5: debug messages (normal debug messages) 7: flow control messages (debug statemachine flows) 9: low priority message (display everything the code does) dev_type0/1 = - ata device 0 type - 0: NO_CONNeCT: none (not connected) + ata device 0 type + 0: NO_CONNeCT: none (not connected) 1: FILE : simulated harddisk 2: LOCAL : local system harddisk dev_file0/1 = "" - filename for simulated ATA device + filename for simulated ATA device valid only if dev_type0 == 1 dev_size0/1 = - size of simulated hard-disk (in MBytes) + size of simulated hard-disk (in MBytes) valid only if dev_type0 == 1 dev_packet0/1 = - 0: simulated ATA device does NOT implement PACKET command feature set + 0: simulated ATA device does NOT implement PACKET command feature set 1: simulated ATA device does implement PACKET command feature set FIXME: irq number diff --git a/board/overo/Kconfig b/board/overo/Kconfig new file mode 100644 index 0000000000..74572a62be --- /dev/null +++ b/board/overo/Kconfig @@ -0,0 +1,9 @@ +if TARGET_OMAP3_OVERO + +config SYS_BOARD + default "overo" + +config SYS_CONFIG_NAME + default "omap3_overo" + +endif diff --git a/board/overo/MAINTAINERS b/board/overo/MAINTAINERS new file mode 100644 index 0000000000..8f089e87f8 --- /dev/null +++ b/board/overo/MAINTAINERS @@ -0,0 +1,6 @@ +OVERO BOARD +M: Steve Sakoman +S: Maintained +F: board/overo/ +F: include/configs/omap3_overo.h +F: configs/omap3_overo_defconfig diff --git a/board/overo/Makefile b/board/overo/Makefile index 694f317800..910948455b 100644 --- a/board/overo/Makefile +++ b/board/overo/Makefile @@ -5,22 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := overo.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -######################################################################### -sinclude $(obj).depend +obj-y := overo.o diff --git a/board/overo/overo.c b/board/overo/overo.c index a6e2e935a7..b7f85e711b 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -13,6 +13,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include #include #include #include @@ -21,17 +23,23 @@ #include #include #include -#include #include #include #include "overo.h" +#ifdef CONFIG_USB_EHCI +#include +#include +#endif + DECLARE_GLOBAL_DATA_PTR; #define TWL4030_I2C_BUS 0 #define EXPANSION_EEPROM_I2C_BUS 2 #define EXPANSION_EEPROM_I2C_ADDRESS 0x51 +#define GUMSTIX_EMPTY_EEPROM 0x0 + #define GUMSTIX_SUMMIT 0x01000200 #define GUMSTIX_TOBI 0x02000200 #define GUMSTIX_TOBI_DUO 0x03000200 @@ -40,6 +48,11 @@ DECLARE_GLOBAL_DATA_PTR; #define GUMSTIX_CHESTNUT43 0x06000200 #define GUMSTIX_PINTO 0x07000200 #define GUMSTIX_GALLOP43 0x08000200 +#define GUMSTIX_ALTO35 0x09000200 +#define GUMSTIX_STAGECOACH 0x0A000200 +#define GUMSTIX_THUMBO 0x0B000200 +#define GUMSTIX_TURTLECORE 0x0C000200 +#define GUMSTIX_ARBOR43C 0x0D000200 #define ETTUS_USRP_E 0x01000300 @@ -52,21 +65,17 @@ static struct { char fab_revision[8]; char env_var[16]; char env_setting[64]; -} expansion_config; +} expansion_config = {0x0}; -#if defined(CONFIG_CMD_NET) -static void setup_net_chip(void); -#endif +static const struct ns16550_platdata overo_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; -/* GPMC definitions for LAN9221 chips on Tobi expansion boards */ -static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, - /*CONFIG7- computed as params */ +U_BOOT_DEVICE(overo_uart) = { + "serial_omap", + &overo_serial }; /* @@ -92,7 +101,7 @@ int get_board_revision(void) { int revision; -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX unsigned char data; /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ @@ -142,16 +151,23 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = MICRON_V_MCFG_165(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + case REVISION_4: + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = HYNIX_V_MCFG_165(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_165; - timings->ctrlb = HYNIX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ + timings->mcfg = MCFG(512 << 20, 15); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; default: timings->mcfg = MICRON_V_MCFG_165(128 << 20); @@ -202,6 +218,9 @@ int get_sdio2_config(void) */ unsigned int get_expansion_id(void) { + if (expansion_config.device_vendor != 0x0) + return expansion_config.device_vendor; + i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */ @@ -225,13 +244,11 @@ unsigned int get_expansion_id(void) */ int misc_init_r(void) { + unsigned int expansion_id; + twl4030_power_init(); twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); -#if defined(CONFIG_CMD_NET) - setup_net_chip(); -#endif - printf("Board revision: %d\n", get_board_revision()); switch (get_sdio2_config()) { @@ -247,68 +264,119 @@ int misc_init_r(void) puts("Unable to detect mmc2 connection type\n"); } - switch (get_expansion_id()) { + expansion_id = get_expansion_id(); + switch (expansion_id) { case GUMSTIX_SUMMIT: printf("Recognized Summit expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "dvi"); + setenv("expansionname", "summit"); break; case GUMSTIX_TOBI: printf("Recognized Tobi expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "dvi"); + setenv("expansionname", "tobi"); break; case GUMSTIX_TOBI_DUO: printf("Recognized Tobi Duo expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); - /* second lan chip */ - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], - 0x2B000000, GPMC_SIZE_16M); + MUX_GUMSTIX(); break; case GUMSTIX_PALO35: printf("Recognized Palo35 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "lcd35"); break; case GUMSTIX_PALO43: printf("Recognized Palo43 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "lcd43"); + setenv("expansionname", "palo43"); break; case GUMSTIX_CHESTNUT43: printf("Recognized Chestnut43 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); setenv("defaultdisplay", "lcd43"); + setenv("expansionname", "chestnut43"); break; case GUMSTIX_PINTO: printf("Recognized Pinto expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); break; case GUMSTIX_GALLOP43: printf("Recognized Gallop43 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); + setenv("defaultdisplay", "lcd43"); + setenv("expansionname", "gallop43"); + break; + case GUMSTIX_ALTO35: + printf("Recognized Alto35 expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_GUMSTIX(); + MUX_ALTO35(); + setenv("defaultdisplay", "lcd35"); + setenv("expansionname", "alto35"); + break; + case GUMSTIX_STAGECOACH: + printf("Recognized Stagecoach expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_GUMSTIX(); + break; + case GUMSTIX_THUMBO: + printf("Recognized Thumbo expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_GUMSTIX(); + break; + case GUMSTIX_TURTLECORE: + printf("Recognized Turtlecore expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_GUMSTIX(); + break; + case GUMSTIX_ARBOR43C: + printf("Recognized Arbor43C expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_GUMSTIX(); + MUX_ARBOR43C(); setenv("defaultdisplay", "lcd43"); break; case ETTUS_USRP_E: printf("Recognized Ettus Research USRP-E (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); + MUX_GUMSTIX(); MUX_USRP_E(); setenv("defaultdisplay", "dvi"); break; case GUMSTIX_NO_EEPROM: - puts("No EEPROM on expansion board\n"); + case GUMSTIX_EMPTY_EEPROM: + puts("No or empty EEPROM on expansion board\n"); + MUX_GUMSTIX(); + setenv("expansionname", "tobi"); break; default: - puts("Unrecognized expansion board\n"); + printf("Unrecognized expansion board 0x%08x\n", expansion_id); + break; } if (expansion_config.content == 1) @@ -316,6 +384,11 @@ int misc_init_r(void) dieid_num_r(); + if (get_cpu_family() == CPU_OMAP34XX) + setenv("boardname", "overo"); + else + setenv("boardname", "overo-storm"); + return 0; } @@ -330,7 +403,18 @@ void set_muxconf_regs(void) MUX_OVERO(); } -#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SPL_BUILD) +/* GPMC definitions for LAN9221 chips on Tobi expansion boards */ +static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + /*CONFIG7- computed as params */ +}; + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -340,10 +424,6 @@ static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - /* first lan chip */ - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, - GPMC_SIZE_16M); - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ @@ -351,7 +431,14 @@ static void setup_net_chip(void) /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, &ctrl_base->gpmc_nadv_ale); +} +/* + * Routine: reset_net_chip + * Description: Reset the Ethernet hardware. + */ +static void reset_net_chip(void) +{ /* Make GPIO 64 as output pin and send a magic pulse through it */ if (!gpio_request(64, "")) { gpio_direction_output(64, 0); @@ -362,16 +449,42 @@ static void setup_net_chip(void) gpio_set_value(64, 1); } } -#endif int board_eth_init(bd_t *bis) { + unsigned int expansion_id; int rc = 0; + #ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + expansion_id = get_expansion_id(); + switch (expansion_id) { + case GUMSTIX_TOBI_DUO: + /* second lan chip */ + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], + 0x2B000000, GPMC_SIZE_16M); + /* no break */ + case GUMSTIX_TOBI: + case GUMSTIX_CHESTNUT43: + case GUMSTIX_STAGECOACH: + case GUMSTIX_NO_EEPROM: + case GUMSTIX_EMPTY_EEPROM: + /* first lan chip */ + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + 0x2C000000, GPMC_SIZE_16M); + + setup_net_chip(); + reset_net_chip(); + + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + break; + default: + break; + } #endif + return rc; } +#endif #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) @@ -379,3 +492,39 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0, -1, -1); } #endif + +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + +#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED +}; + +#define GUMSTIX_GPIO_USBH_CPEN 168 +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + /* Enable USB power */ + if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen")) + gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1); + + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + /* Disable USB power */ + gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0); + gpio_free(GUMSTIX_GPIO_USBH_CPEN); + + return omap_ehci_hcd_stop(); +} + +#endif /* CONFIG_USB_EHCI */ diff --git a/board/overo/overo.h b/board/overo/overo.h index 88e197dee2..d0edf86365 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -21,6 +21,8 @@ const omap3_sysinfo sysinfo = { #define REVISION_0 0x0 #define REVISION_1 0x1 #define REVISION_2 0x2 +#define REVISION_3 0x3 +#define REVISION_4 0x4 /* * IEN - Input Enable @@ -99,13 +101,9 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\ /* - MMC1_WP*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\ MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\ @@ -115,45 +113,11 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - /* - SMSC911X_NRES*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ /*CAMERA*/\ MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\ MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ @@ -166,13 +130,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ - /* - PEN_DOWN*/\ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ /*Audio Interface */\ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ @@ -206,14 +165,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\ @@ -226,7 +178,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\ /*Serial Interface*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\ /* BT_NRESET*/\ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\ @@ -253,14 +204,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\ - /* - LAN_INTR */\ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\ @@ -279,21 +222,9 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ /* - W2W_NRESET*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\ @@ -367,6 +298,85 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ +#define MUX_GUMSTIX() \ + /*GPMC*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\ + /* - CAM_IRQ*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + /* - SMSC911X_NRES*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ + /* - PEN_DOWN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\ + /* - LAN_INTR */\ + /*Control and debug */\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ + #define MUX_OVERO_SDIO2_DIRECT() \ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ @@ -403,4 +413,20 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\ +#define MUX_ALTO35() \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-BTN*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\ + MUX_VAL(CP(UART1_RX), (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175*/\ + +#define MUX_ARBOR43C() \ + MUX_VAL(CP(CSI2_DX1), (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*GPIO_170-BUTTON */\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-CAP IRQ*/\ + #endif diff --git a/board/palmld/Kconfig b/board/palmld/Kconfig new file mode 100644 index 0000000000..3111295719 --- /dev/null +++ b/board/palmld/Kconfig @@ -0,0 +1,9 @@ +if TARGET_PALMLD + +config SYS_BOARD + default "palmld" + +config SYS_CONFIG_NAME + default "palmld" + +endif diff --git a/board/palmld/MAINTAINERS b/board/palmld/MAINTAINERS new file mode 100644 index 0000000000..7d21b7b3eb --- /dev/null +++ b/board/palmld/MAINTAINERS @@ -0,0 +1,6 @@ +PALMLD BOARD +M: Marek Vasut +S: Maintained +F: board/palmld/ +F: include/configs/palmld.h +F: configs/palmld_defconfig diff --git a/board/palmld/Makefile b/board/palmld/Makefile index 44a8ad8e01..ea93ca88e2 100644 --- a/board/palmld/Makefile +++ b/board/palmld/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := palmld.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := palmld.o diff --git a/board/palmtc/Kconfig b/board/palmtc/Kconfig new file mode 100644 index 0000000000..3eb7198837 --- /dev/null +++ b/board/palmtc/Kconfig @@ -0,0 +1,9 @@ +if TARGET_PALMTC + +config SYS_BOARD + default "palmtc" + +config SYS_CONFIG_NAME + default "palmtc" + +endif diff --git a/board/palmtc/MAINTAINERS b/board/palmtc/MAINTAINERS new file mode 100644 index 0000000000..57b6a22e49 --- /dev/null +++ b/board/palmtc/MAINTAINERS @@ -0,0 +1,6 @@ +PALMTC BOARD +M: Marek Vasut +S: Maintained +F: board/palmtc/ +F: include/configs/palmtc.h +F: configs/palmtc_defconfig diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile index a87eb81fb8..b4a682d24d 100644 --- a/board/palmtc/Makefile +++ b/board/palmtc/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := palmtc.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := palmtc.o diff --git a/board/palmtreo680/Kconfig b/board/palmtreo680/Kconfig new file mode 100644 index 0000000000..b5fdb9a361 --- /dev/null +++ b/board/palmtreo680/Kconfig @@ -0,0 +1,9 @@ +if TARGET_PALMTREO680 + +config SYS_BOARD + default "palmtreo680" + +config SYS_CONFIG_NAME + default "palmtreo680" + +endif diff --git a/board/palmtreo680/MAINTAINERS b/board/palmtreo680/MAINTAINERS new file mode 100644 index 0000000000..b0ff9d0283 --- /dev/null +++ b/board/palmtreo680/MAINTAINERS @@ -0,0 +1,6 @@ +PALMTREO680 BOARD +#M: Mike Dunn +S: Orphan (since 2014-06) +F: board/palmtreo680/ +F: include/configs/palmtreo680.h +F: configs/palmtreo680_defconfig diff --git a/board/palmtreo680/Makefile b/board/palmtreo680/Makefile index 34ffb99d0c..4f79e4bf11 100644 --- a/board/palmtreo680/Makefile +++ b/board/palmtreo680/Makefile @@ -6,29 +6,4 @@ # This file is released under the terms of GPL v2 and any later version. # See the file COPYING in the root directory of the source tree for details. -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := palmtreo680.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := palmtreo680.o diff --git a/board/palmtreo680/README b/board/palmtreo680/README index 159f1f69dc..c8799c6ab1 100644 --- a/board/palmtreo680/README +++ b/board/palmtreo680/README @@ -30,7 +30,6 @@ go wrong, but please tell me what happened exactly. For that matter, I'd love to hear from you if you succeed. - Details on the SPL ================== @@ -51,7 +50,6 @@ IPL has already loaded to its correct SDRAM address, and then loads the remainder of u-boot and jumps to it. - The docg4's "reliable mode" =========================== @@ -79,7 +77,6 @@ module parameter), but not reading. However, the u-boot docg4_spl driver does read in reliable mode, in the same fashion as the IPL. - Details on the IPL and its data format ====================================== @@ -105,7 +102,6 @@ For the sake of simplicity and uniformity, the u-boot SPL mimics the operation of the IPL, and expects the image to be stored in the same format. - Instructions on Programming u-boot to flash =========================================== @@ -117,7 +113,6 @@ remainder of this document describes in detail how to program u-boot to the flash using Linux running on the Treo. - Hardware Prerequisites ====================== @@ -136,7 +131,6 @@ A Linux desktop PC. to flash, you'll really want to use a Linux PC. - Treo-side Software Prerequisites ================================ @@ -152,7 +146,6 @@ Linux bootloader for PalmOS: parameters passed to the kernel. - Linux kernel: The kernel on the Treo 680 is still a little rough around the edges, and the @@ -200,7 +193,6 @@ Linux kernel: and /dev/mtd2 for these partitions, respectively. Ensure that your root file system at least has /dev/mtd1 if you are not running udev or mdev. - Userspace Utilities: In addition to everything necessary to provide a useful userspace environment @@ -221,19 +213,16 @@ Userspace Utilities: from the mtd-utils package. - Desktop PC-side Software Prerequisites ====================================== Terminal emulator application: minicom, kermit, etc. - Linux kernel: Compiled with CONFIG_USB_SERIAL enabled. Build this as a module. - Recommended (Not directly related to u-boot) ============================================ @@ -275,7 +264,6 @@ configure the usb0 interface on the desktop.) Use the nfs 'nolock' option when mounting to avoid the need to run a portmapper like rpcbind. - Preliminaries ============= @@ -397,7 +385,6 @@ forget to copy the file to permanent storage, such as an mmc card. If all of the above went well, you can now program u-boot. - Programming u-boot ================== @@ -438,7 +425,6 @@ four blocks in /dev/mtd1; i.e., at offsets 0x00000, 0x40000, 0x80000, 0xc0000. Shutdown linux, remove and re-insert the battery, hold your breath... - Enjoying u-boot =============== @@ -478,7 +464,6 @@ support for reliable mode in u-boot's docg4 flash driver. This should be corrected soon. - Customizing =========== @@ -511,7 +496,6 @@ in flash did not seem worth the cost of a 256k flash block. But adding this should be straightforward. - Restoring PalmOS ================ @@ -568,7 +552,6 @@ modprobe docg4 ignore_badblocks=1 || exit 1 dd if=$1 bs=1 skip=$file_ofs count=540672 | nandwrite -o -n -s 0x80000 $2 - || exit 1 modprobe -r docg4 - TODO ==== @@ -578,4 +561,3 @@ TODO - U-boot command that will write a new image to the bootloader partition in flash. - Linux FTD support. - diff --git a/board/pandora/Kconfig b/board/pandora/Kconfig new file mode 100644 index 0000000000..0b33818008 --- /dev/null +++ b/board/pandora/Kconfig @@ -0,0 +1,9 @@ +if TARGET_OMAP3_PANDORA + +config SYS_BOARD + default "pandora" + +config SYS_CONFIG_NAME + default "omap3_pandora" + +endif diff --git a/board/pandora/MAINTAINERS b/board/pandora/MAINTAINERS new file mode 100644 index 0000000000..e12351735c --- /dev/null +++ b/board/pandora/MAINTAINERS @@ -0,0 +1,6 @@ +PANDORA BOARD +M: Grazvydas Ignotas +S: Maintained +F: board/pandora/ +F: include/configs/omap3_pandora.h +F: configs/omap3_pandora_defconfig diff --git a/board/pandora/Makefile b/board/pandora/Makefile index 6e75133bf3..918b65691d 100644 --- a/board/pandora/Makefile +++ b/board/pandora/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := pandora.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := pandora.o diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 146dcea4e1..59b5a7e2cd 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -126,4 +126,9 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} #endif diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h index cbf4186f71..268b92998f 100644 --- a/board/pandora/pandora.h +++ b/board/pandora/pandora.h @@ -310,7 +310,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ /*JTAG*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig new file mode 100644 index 0000000000..251db6ab63 --- /dev/null +++ b/board/pb1x00/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PB1X00 + +config SYS_BOARD + default "pb1x00" + +config SYS_SOC + default "au1x00" + +config SYS_CONFIG_NAME + default "pb1x00" + +endif diff --git a/board/pb1x00/MAINTAINERS b/board/pb1x00/MAINTAINERS new file mode 100644 index 0000000000..8326cc78cc --- /dev/null +++ b/board/pb1x00/MAINTAINERS @@ -0,0 +1,6 @@ +PB1X00 BOARD +#M: - +S: Maintained +F: board/pb1x00/ +F: include/configs/pb1x00.h +F: configs/pb1000_defconfig diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile index ed7370f9a6..647eb85d74 100644 --- a/board/pb1x00/Makefile +++ b/board/pb1x00/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o -SOBJS = lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = pb1x00.o flash.o +obj-y += lowlevel_init.o diff --git a/board/pcs440ep/Kconfig b/board/pcs440ep/Kconfig new file mode 100644 index 0000000000..5b280f6e77 --- /dev/null +++ b/board/pcs440ep/Kconfig @@ -0,0 +1,9 @@ +if TARGET_PCS440EP + +config SYS_BOARD + default "pcs440ep" + +config SYS_CONFIG_NAME + default "pcs440ep" + +endif diff --git a/board/pcs440ep/MAINTAINERS b/board/pcs440ep/MAINTAINERS new file mode 100644 index 0000000000..6eccc854f9 --- /dev/null +++ b/board/pcs440ep/MAINTAINERS @@ -0,0 +1,6 @@ +PCS440EP BOARD +M: Stefan Roese +S: Maintained +F: board/pcs440ep/ +F: include/configs/pcs440ep.h +F: configs/pcs440ep_defconfig diff --git a/board/pcs440ep/Makefile b/board/pcs440ep/Makefile index 851859d045..4fc24d6c5d 100644 --- a/board/pcs440ep/Makefile +++ b/board/pcs440ep/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = pcs440ep.o flash.o +extra-y += init.o diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk index 1e761284e4..b90d5d0ec1 100644 --- a/board/pcs440ep/config.mk +++ b/board/pcs440ep/config.mk @@ -10,7 +10,7 @@ # # Check the U-Boot Image with a SHA1 checksum -ALL-y += $(obj)u-boot.sha1 +ALL-y += u-boot.sha1 PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S index 33a0f4e15e..c0e83de257 100644 --- a/board/pcs440ep/init.S +++ b/board/pcs440ep/init.S @@ -2,7 +2,7 @@ * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 0a934fb2cf..267c001435 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -2,7 +2,7 @@ * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/pdm360ng/Kconfig b/board/pdm360ng/Kconfig new file mode 100644 index 0000000000..33173a0a2a --- /dev/null +++ b/board/pdm360ng/Kconfig @@ -0,0 +1,9 @@ +if TARGET_PDM360NG + +config SYS_BOARD + default "pdm360ng" + +config SYS_CONFIG_NAME + default "pdm360ng" + +endif diff --git a/board/pdm360ng/MAINTAINERS b/board/pdm360ng/MAINTAINERS new file mode 100644 index 0000000000..5c99f59e8f --- /dev/null +++ b/board/pdm360ng/MAINTAINERS @@ -0,0 +1,6 @@ +PDM360NG BOARD +M: Michael Weiss +S: Maintained +F: board/pdm360ng/ +F: include/configs/pdm360ng.h +F: configs/pdm360ng_defconfig diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile index 76f5be45f5..99201a41f6 100644 --- a/board/pdm360ng/Makefile +++ b/board/pdm360ng/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := pdm360ng.o diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index 15f8f3163d..81f3024ed9 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -477,7 +477,7 @@ static unsigned char edid_buf[128] = { }; #endif -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { u32 val[8]; int rc, i = 0; @@ -526,6 +526,8 @@ void ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update flash reg property, err=%s\n", fdt_strerror(rc)); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig new file mode 100644 index 0000000000..3a3eab8576 --- /dev/null +++ b/board/phytec/pcm030/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PCM030 + +config SYS_BOARD + default "pcm030" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "pcm030" + +endif diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS new file mode 100644 index 0000000000..4e2ab0d64e --- /dev/null +++ b/board/phytec/pcm030/MAINTAINERS @@ -0,0 +1,7 @@ +PCM030 BOARD +M: Jon Smirl +S: Maintained +F: board/phytec/pcm030/ +F: include/configs/pcm030.h +F: configs/pcm030_defconfig +F: configs/pcm030_LOWBOOT_defconfig diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile index 4a7d872afa..2bb49dc7aa 100644 --- a/board/phytec/pcm030/Makefile +++ b/board/phytec/pcm030/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := pcm030.o diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c index ce515d834c..ed41de13d4 100644 --- a/board/phytec/pcm030/pcm030.c +++ b/board/phytec/pcm030/pcm030.c @@ -164,9 +164,11 @@ void pci_init_board(void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t * bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig new file mode 100644 index 0000000000..2cc0d8872d --- /dev/null +++ b/board/phytec/pcm051/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PCM051 + +config SYS_BOARD + default "pcm051" + +config SYS_VENDOR + default "phytec" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "pcm051" + +endif diff --git a/board/phytec/pcm051/MAINTAINERS b/board/phytec/pcm051/MAINTAINERS new file mode 100644 index 0000000000..18ea636a83 --- /dev/null +++ b/board/phytec/pcm051/MAINTAINERS @@ -0,0 +1,7 @@ +PCM051 BOARD +M: Lars Poeschel +S: Maintained +F: board/phytec/pcm051/ +F: include/configs/pcm051.h +F: configs/pcm051_rev1_defconfig +F: configs/pcm051_rev3_defconfig diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile index cb2b999025..ecb1d61669 100644 --- a/board/phytec/pcm051/Makefile +++ b/board/phytec/pcm051/Makefile @@ -6,33 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifdef CONFIG_SPL_BUILD -COBJS := mux.o +obj-y += mux.o endif -COBJS += board.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += board.o diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 6291d03bac..1071662ea9 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -30,11 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - /* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0xA #define RMII_RGMII2_MODE_ENABLE 0x49 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; @@ -44,25 +40,39 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* DDR RAM defines */ #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +#ifdef CONFIG_REV1 +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J256M8HX15E_RATIO, - .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, .cmd1csratio = MT41J256M8HX15E_RATIO, - .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, .cmd2csratio = MT41J256M8HX15E_RATIO, - .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, }; @@ -76,66 +86,80 @@ static struct emif_regs ddr3_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, }; -#endif -/* - * early system init of muxing and clocks. - */ -void s_init(void) +void sdram_init(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif + config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#else +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; - /* - * WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - /* Enable RTC32K clock */ - rtc32k_enable(); + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - enable_uart0_pin_mux(); - uart_soft_reset(); + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; - gd = &gdata; +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; - preloader_console_init(); +void sdram_init(void) +{ + config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#endif +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ /* Initalize the board header */ enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); enable_board_pin_mux(); - - config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } @@ -152,13 +176,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RGMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RGMII, }, }; @@ -175,6 +199,7 @@ static struct cpsw_platform_data cpsw_data = { .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, diff --git a/board/pm520/Makefile b/board/pm520/Makefile deleted file mode 100644 index 4ff6b2d995..0000000000 --- a/board/pm520/Makefile +++ /dev/null @@ -1,29 +0,0 @@ - -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/pm520/flash.c b/board/pm520/flash.c deleted file mode 100644 index 89c9f02644..0000000000 --- a/board/pm520/flash.c +++ /dev/null @@ -1,659 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) (x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) (x) -#endif - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x00890089 -#define INTEL_ALT 0x00B000B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); -static void flash_sync_real_protect (flash_info_t * info); -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - extern void flash_preinit(void); - extern void flash_afterinit(ulong, ulong); - ulong flashbase = CONFIG_SYS_FLASH_BASE; - - flash_preinit(); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - memset(&flash_info[i], 0, sizeof(flash_info_t)); - flash_get_size ((FPW *) flashbase, &flash_info[i]); - flash_get_offsets (flash_info[i].start[0], &flash_info[i]); - break; - default: - panic ("configured to many flash banks!\n"); - break; - } - size += flash_info[i].size; - - /* get the h/w and s/w protection status in sync */ - flash_sync_real_protect(&flash_info[i]); - } - - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#ifndef CONFIG_BOOT_ROM - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0] ); -#endif -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); -#endif - - flash_afterinit(flash_info[0].start[0], flash_info[0].size); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256J3A: - printf ("28F256J3A\n"); - break; - - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - - case FLASH_28F320J3A: - printf ("28F320J3A\n"); - break; - - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - udelay(100); - - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F256J3A: - info->flash_id += FLASH_28F256J3A; - /* In U-Boot we support only 32 MB (no bank-switching) */ - info->sector_count = 256 / 2; - info->size = 0x04000000 / 2; - info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000; - break; /* => 32 MB */ - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000; - break; /* => 32 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03000000; - break; /* => 16 MB */ - - case (FPW) INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x800000; - info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03800000; - break; /* => 8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* - * This function gets the u-boot flash sector protection status - * (flash_info_t.protect[]) in sync with the sector protection - * status stored in hardware. - */ -static void flash_sync_real_protect (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - - case FLASH_28F256J3A: - case FLASH_28F128J3A: - case FLASH_28F640J3A: - case FLASH_28F320J3A: - for (i = 0; i < info->sector_count; ++i) { - info->protect[i] = intel_sector_protected(info, i); - } - break; - default: - /* no h/w protect support */ - break; - } -} - - -/* - * checks if "sector" in bank "info" is protected. Should work on intel - * strata flash chips 28FxxxJ3x in 8-bit mode. - * Returns 1 if sector is protected (or timed-out while trying to read - * protection status), 0 if it is not. - */ -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) -{ - FPWV *addr; - FPWV *lock_conf_addr; - ulong start; - unsigned char ret; - - /* - * first, wait for the WSM to be finished. The rationale for - * waiting for the WSM to become idle for at most - * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy - * because of: (1) erase, (2) program or (3) lock bit - * configuration. So we just wait for the longest timeout of - * the (1)-(3), i.e. the erase timeout. - */ - - /* wait at least 35ns (W12) before issuing Read Status Register */ - udelay(1); - addr = (FPWV *) info->start[sector]; - *addr = (FPW) INTEL_STATUS; - - start = get_timer (0); - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - printf("WSM busy too long, can't get prot status\n"); - return 1; - } - } - - /* issue the Read Identifier Codes command */ - *addr = (FPW) INTEL_READID; - - /* wait at least 35ns (W12) before reading */ - udelay(1); - - /* Intel example code uses offset of 2 for 16 bit flash */ - lock_conf_addr = (FPWV *) info->start[sector] + 2; - ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; - - /* put flash back in read mode */ - *addr = (FPW) INTEL_RESET; - - return ret; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - - if (flag) - enable_interrupts(); - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - int flag; - int rcode = 0; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rcode = 1; - break; - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - if (flag) - enable_interrupts(); - - return rcode; -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect (flash_info_t *info, long sector, int prot) -{ - ulong start; - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer(0); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - * WARNING: code below re-locks sectors only for one bank (info). - * This causes problems on boards where several banks share - * the same chip, as sectors in othere banks will be unlocked - * but not re-locked. It works fine on pm520 though, as there - * is only one chip and one bank. - */ - if (!prot) - { - for (i = 0; i < info->sector_count; i++) - { - if (info->protect[i]) - { - start = get_timer(0); - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) - { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) - { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - /* - * get the s/w sector protection status in sync with the h/w, - * in case something went wrong during the re-locking. - */ - flash_sync_real_protect(info); /* resets flash to read mode */ - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h deleted file mode 100644 index 9068fbf36f..0000000000 --- a/board/pm520/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/pm520/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c deleted file mode 100644 index 4ec4505e8d..0000000000 --- a/board/pm520/pm520.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize + dramsize2; -} - -int checkboard (void) -{ - puts ("Board: MicroSys PM520 \n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong start, ulong size) -{ -#if defined(CONFIG_BOOT_ROM) - /* adjust mapping */ - *(vu_long *)MPC5XXX_CS1_START = - START_REG(start); - *(vu_long *)MPC5XXX_CS1_STOP = - STOP_REG(start, size); -#else - /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(start); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(start, size); -#endif -} - - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -int misc_init_r (void) -{ - /* adjust flash start */ - gd->bd->bi_flashstart = flash_info[0].start[0]; - return (0); -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -} -#endif - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/pm826/Makefile b/board/pm826/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/pm826/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/pm826/flash.c b/board/pm826/flash.c deleted file mode 100644 index e8d4176e37..0000000000 --- a/board/pm826/flash.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write query command sequence and test FLASH answer - */ - baseaddr[0] = 0x00980098; - baseaddr[1] = 0x00980098; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F640C3B: - info->flash_id = FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3 or 640C3) - */ - for (i = 0; i < info->sector_count; i++) { - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* protect monitor and environment sectors - */ - -#ifndef CONFIG_BOOT_ROM - /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE - * but we shouldn't protect it. - */ - -# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -# endif -#endif /* CONFIG_BOOT_ROM */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 M, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 M, bottom sector)\n"); - break; - case FLASH_28F640C3B: - printf ("28F640C3B (64 M, bottom sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, cc = cnt, res = 0; - - - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c deleted file mode 100644 index 93bb1b4615..0000000000 --- a/board/pm826/pm826.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -#ifdef CONFIG_ETHER_ON_FCC2 -#error "SCC1 conflicts with FCC2" -#endif - /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ -#else - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ -#endif - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ - /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ - /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ - /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: PM826\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - ulong size8, size9; -#endif - ulong psize = 32 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL) "); - } -#endif - return (psize); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/pm828/Makefile b/board/pm828/Makefile deleted file mode 100644 index e9558412e1..0000000000 --- a/board/pm828/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/pm828/flash.c b/board/pm828/flash.c deleted file mode 100644 index 9a00a66858..0000000000 --- a/board/pm828/flash.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write query command sequence and test FLASH answer - */ - baseaddr[0] = 0x00980098; - baseaddr[1] = 0x00980098; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F640C3B: - info->flash_id = FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3 or 640c3) - */ - for (i = 0; i < info->sector_count; i++) { - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* protect monitor and environment sectors - */ - -#ifndef CONFIG_BOOT_ROM - /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE - * but we shouldn't protect it. - */ - -# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -# endif -#endif /* CONFIG_BOOT_ROM */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 M, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 M, bottom sector)\n"); - break; - case FLASH_28F640C3B: - printf ("28F640C3B (64 M, bottom sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, cc = cnt, res = 0; - - - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c deleted file mode 100644 index f446543fed..0000000000 --- a/board/pm828/pm828.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -#ifdef CONFIG_ETHER_ON_FCC2 -#error "SCC1 conflicts with FCC2" -#endif - /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ -#else - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ -#endif - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ - /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ - /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ - /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: PM828\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile ulong cnt, val; - volatile ulong *addr; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - int i; - ulong save[32]; /* to make test non-destructive */ - ulong maxsize; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - /* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - i = 0; - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = (volatile ulong *) base + cnt; /* pointer arith! */ - save[i++] = *addr; - *addr = ~cnt; - } - - addr = (volatile ulong *) base; - save[i] = *addr; - *addr = 0; - - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; /* pointer arith! */ - val = *addr; - *addr = save[--i]; - if (val != ~cnt) { - /* Write the actual size to ORx - */ - *orx_ptr = orx | ~(cnt * sizeof (long) - 1); - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - ulong size8, size9; -#endif - ulong psize = 32 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL) "); - } -#endif - return (psize); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/pn62/Makefile b/board/pn62/Makefile deleted file mode 100644 index 5fa6fc8ca6..0000000000 --- a/board/pn62/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o cmd_pn62.o misc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c deleted file mode 100644 index a0326b40d6..0000000000 --- a/board/pn62/cmd_pn62.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "pn62.h" - -#if defined(CONFIG_CMD_BSP) - -/* - * Command led: controls the various LEDs 0..11 on the PN62 card. - */ -int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned int number, function; - - if (argc != 3) - return cmd_usage(cmdtp); - - number = simple_strtoul(argv[1], NULL, 10); - if (number > PN62_LED_MAX) - return 1; - - function = simple_strtoul(argv[2], NULL, 16); - set_led(number, function); - return 0; -} -U_BOOT_CMD( - led , 3, 1, do_led, - "set LED 0..11 on the PN62 board", - "i fun" - " - set 'i'th LED to function 'fun'" -); - -/* - * Command loadpci: loads a image over PCI. - */ -#define CMD_MOVE_WINDOW 0x1 -#define CMD_BOOT_IMAGE 0x2 - -int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *s; - ulong addr = 0, count = 0; - u32 off; - int cmd, rcode = 0; - - /* pre-set load_addr */ - if ((s = getenv("loadaddr")) != NULL) { - addr = simple_strtoul(s, NULL, 16); - } - - switch (argc) { - case 1: - break; - case 2: - addr = simple_strtoul(argv[1], NULL, 16); - break; - default: - return cmd_usage(cmdtp); - } - - printf ("## Ready for image download ...\n"); - - show_startup_phase(12); - - while (1) { - /* Alive indicator */ - i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY); - - /* Toggle status LEDs */ - cmd = (count / 200) % 4; /* downscale */ - set_led(4, cmd == 0 ? LED_1 : LED_0); - set_led(5, cmd == 1 ? LED_1 : LED_0); - set_led(6, cmd == 2 ? LED_1 : LED_0); - set_led(7, cmd == 3 ? LED_1 : LED_0); - udelay(1000); - count++; - - cmd = i2155x_read_scrapad(BOOT_CMD); - - if (cmd == BOOT_CMD_MOVE) { - off = i2155x_read_scrapad(BOOT_DATA); - off += addr; - i2155x_set_bar_base(3, off); - printf ("## BAR3 Addr moved = 0x%08x\n", off); - i2155x_write_scrapad(BOOT_CMD, ~cmd); - show_startup_phase(13); - } - else if (cmd == BOOT_CMD_BOOT) { - set_led(4, LED_1); - set_led(5, LED_1); - set_led(6, LED_1); - set_led(7, LED_1); - - i2155x_write_scrapad(BOOT_CMD, ~cmd); - show_startup_phase(14); - break; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - printf("\nAbort\n"); - return 0; - } - - } - - /* Repoint to the default shared memory */ - i2155x_set_bar_base(3, PN62_SMEM_DEFAULT); - - load_addr = addr; - printf ("## Start Addr = 0x%08lx\n", addr); - - show_startup_phase(15); - - /* Loading ok, check if we should attempt an auto-start */ - if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) { - char *local_args[2]; - local_args[0] = argv[0]; - local_args[1] = NULL; - - printf ("Automatic boot of image at addr 0x%08lX ...\n", - load_addr); - rcode = do_bootm (cmdtp, 0, 1, local_args); - } - - return rcode; -} - -U_BOOT_CMD( - loadpci, 2, 1, do_loadpci, - "load binary file over PCI", - "[addr]\n" - " - load binary file over PCI to address 'addr'" -); - -#endif diff --git a/board/pn62/misc.c b/board/pn62/misc.c deleted file mode 100644 index 98e0dfa518..0000000000 --- a/board/pn62/misc.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include "pn62.h" - -typedef struct { - pci_dev_t devno; - volatile u32 *csr; - -} i2155x_t; - -static i2155x_t i2155x = { 0, NULL }; - -static struct pci_device_id i2155x_ids[] = { - { 0x1011, 0x0046 }, /* i21554 */ - { 0x8086, 0xb555 } /* i21555 */ -}; - -int i2155x_init(void) -{ - pci_dev_t devno; - u32 val; - int i; - - /* - * Find the Intel bridge. - */ - if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) { - printf("Error: Intel bridge 2155x not found!\n"); - return -1; - } - i2155x.devno = devno; - - /* - * Get auto-configured base address for CSR access. - */ - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val); - if (val & PCI_BASE_ADDRESS_SPACE_IO) { - val &= PCI_BASE_ADDRESS_IO_MASK; - i2155x.csr = (volatile u32 *)(_IO_BASE + val); - } else { - val &= PCI_BASE_ADDRESS_MEM_MASK; - i2155x.csr = (volatile u32 *)val; - } - - /* - * Translate downstream memory 2 (bar3) to base of shared memory. - */ - i2155x_set_bar_base(3, PN62_SMEM_DEFAULT); - - /* - * Enable memory space, I/O space and bus master bits - * in both Primary and Secondary command registers. - */ - val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO; - pci_write_config_word(devno, 0x44, val); - pci_write_config_word(devno, 0x04, val); - - /* - * Clear scratchpad registers. - */ - for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) { - i2155x_write_scrapad(i, 0x0); - } - - /* - * Set interrupt line for Linux. - */ - pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3); - - return 0; -} - -/* - * Access the Scratchpad registers 0..7 of the Intel bridge. - */ -void i2155x_write_scrapad(int idx, u32 val) -{ - if (idx >= 0 && idx < I2155X_SCRAPAD_MAX) - out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val); - else - printf("i2155x_write_scrapad: invalid index\n"); -} - -u32 i2155x_read_scrapad(int idx) -{ - if (idx >= 0 && idx < I2155X_SCRAPAD_MAX) - return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx); - else - printf("i2155x_read_scrapad: invalid index\n"); - return -1; -} - -void i2155x_set_bar_base(int bar, u32 base) -{ - if (bar >= 2 && bar <= 4) { - pci_write_config_dword(i2155x.devno, - I2155X_BAR2_BASE + (bar - 2) * 4, - base); - } -} - -/* - * Read Vital Product Data (VPD) from the Serial EPROM attached - * to the Intel bridge. - */ -int i2155x_read_vpd(int offset, int size, unsigned char *data) -{ - int i, n; - u16 val16; - - for (i = 0; i < size; i++) { - pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR, - offset + i - I2155X_VPD_START); - for (n = 10000; n > 0; n--) { - pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16); - if ((val16 & 0x8000) != 0) /* wait for completion */ - break; - udelay(100); - } - if (n == 0) { - printf("i2155x_read_vpd: TIMEOUT\n"); - return -1; - } - - pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]); - } - - return i; -} - -static struct pci_device_id am79c95x_ids [] = { - { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, - { } -}; - - -/* - * Initialize the AMD ethernet controllers. - */ -int am79c95x_init(void) -{ - pci_dev_t devno; - int i; - - /* - * Set interrupt line for Linux. - */ - for (i = 0; i < 2; i++) { - if ((devno = pci_find_devices(am79c95x_ids, i)) < 0) - break; - pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i); - } - if (i < 2) - printf("Error: Only %d AMD Ethernet Controller found!\n", i); - - return 0; -} - - -void set_led(unsigned int number, unsigned int function) -{ - volatile u8 *addr; - - if ((number >= 0) && (number < PN62_LED_MAX) && - (function >= 0) && (function <= LED_LAST_FUNCTION)) { - addr = (volatile u8 *)(PN62_LED_BASE + number * 8); - out_8(addr, function&0xff); - } -} - -/* - * Show fatal error indicated by Kinght Rider(tm) effect - * in LEDS 0-7. LEDS 8-11 contain 4 bit error code. - * Note: this function will not terminate. - */ -void fatal_error(unsigned int error_code) -{ - int i, d; - - for (i = 0; i < 12; i++) { - set_led(i, LED_0); - } - - /* - * Write error code. - */ - set_led(8, (error_code & 0x01) ? LED_1 : LED_0); - set_led(9, (error_code & 0x02) ? LED_1 : LED_0); - set_led(10, (error_code & 0x04) ? LED_1 : LED_0); - set_led(11, (error_code & 0x08) ? LED_1 : LED_0); - - /* - * Yay - Knight Rider effect! - */ - while(1) { - unsigned int delay = 2000; - - for (i = 0; i < 8; i++) { - set_led(i, LED_1); - for (d = 0; d < delay; d++); - set_led(i, LED_0); - } - - for (i = 7; i > 0; i--) { - set_led(i, LED_1); - for (d = 0; d < delay; d++); - set_led(i, LED_0); - } - } -} diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c deleted file mode 100644 index 81829dd75f..0000000000 --- a/board/pn62/pn62.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include "pn62.h" - -DECLARE_GLOBAL_DATA_PTR; - -static int get_serial_number (char *string, int size); -static void get_mac_address(int id, u8 *mac); - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int phase) -{ - /* - * Show phases of the bootm command on the front panel - * LEDs and the scratchpad register #3 as well. We use - * blinking LEDs for logical "1". - */ - if (phase > 0) { - set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0); - set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0); - set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0); - set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0); - } - i2155x_write_scrapad (BOOT_STATUS, phase); - if (phase < 0) - i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR); -} -#endif - -void show_startup_phase (int phase) -{ - /* - * Show the phase of U-Boot startup on the front panel - * LEDs and the scratchpad register #3 as well. - */ - if (phase > 0) { - set_led (8, (phase & 0x1) ? LED_1 : LED_0); - set_led (9, (phase & 0x2) ? LED_1 : LED_0); - set_led (10, (phase & 0x4) ? LED_1 : LED_0); - set_led (11, (phase & 0x8) ? LED_1 : LED_0); - } - i2155x_write_scrapad (BOOT_STATUS, phase); - if (phase < 0) - i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR); -} - -int checkboard (void) -{ - show_startup_phase (1); - puts ("Board: PN62\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - show_startup_phase (2); - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg (MEAR1); - emear1 = mpc824x_mpc107_getreg (EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg (MEAR1, mear1); - mpc824x_mpc107_setreg (EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices. We rely on auto-configuration. - */ -#ifndef CONFIG_PCI_PNP -#error "CONFIG_PCI_PNP is not defined, please correct!" -#endif - -struct pci_controller hose = { -}; - -void pci_init_board (void) -{ - show_startup_phase (4); - pci_mpc824x_init (&hose); - - show_startup_phase (5); - i2155x_init (); - show_startup_phase (6); - am79c95x_init (); - show_startup_phase (7); -} - -int misc_init_r (void) -{ - char str[20]; - u8 mac[6]; - - show_startup_phase (8); - /* - * Get serial number and ethernet addresses if not already defined - * and update the board info structure and the environment. - */ - if (getenv ("serial#") == NULL && - get_serial_number (str, strlen (str)) > 0) { - setenv ("serial#", str); - } - show_startup_phase (9); - - if (!eth_getenv_enetaddr("ethaddr", mac)) { - get_mac_address(0, mac); - eth_setenv_enetaddr("ethaddr", mac); - } - show_startup_phase (10); - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", mac)) { - get_mac_address(1, mac); - eth_setenv_enetaddr("eth1addr", mac); - } -#endif /* CONFIG_HAS_ETH1 */ - show_startup_phase (11); - - /* Tell everybody that U-Boot is up and runnig */ - i2155x_write_scrapad (0, 0x12345678); - return (0); -} - -static int get_serial_number (char *string, int size) -{ - int i; - char c; - - if (size < I2155X_VPD_SN_SIZE) - size = I2155X_VPD_SN_SIZE; - for (i = 0; i < (size - 1); i++) { - i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c); - if (c == '\0') - break; - string[i] = c; - } - string[i] = '\0'; /* make sure it's terminated */ - - return i; -} - -static void get_mac_address(int id, u8 *mac) -{ - i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h deleted file mode 100644 index 10290c3142..0000000000 --- a/board/pn62/pn62.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PN62_H_ -#define _PN62_H_ - -/* - * Definitions for the Intel Bridge 21554 or 21555. - */ -#define I2155X_VPD_ADDR 0xe6 -#define I2155X_VPD_DATA 0xe8 - -#define I2155X_VPD_START 0x80 -#define I2155X_VPD_SN_START 0x80 -#define I2155X_VPD_SN_SIZE 0x10 -#define I2155X_VPD_MAC0_START 0x90 -#define I2155X_VPD_MAC1_START 0x96 - -#define I2155X_SCRAPAD_ADDR 0xa8 -#define I2155X_SCRAPAD_MAX 8 - -#define I2155X_BAR2_BASE 0x98 -#define I2155X_BAR3_BASE 0x9c -#define I2155X_BAR4_BASE 0xa0 - -#define I2155X_BAR2_SETUP 0xb0 -#define I2155X_BAR3_SETUP 0xb4 -#define I2155X_BAR4_SETUP 0xb8 - -/* - * Interrupt request numbers - */ -#define PN62_IRQ_HOST 0x0 -#define PN62_IRQ_PLX9054 0x1 -#define PN62_IRQ_ETH0 0x2 -#define PN62_IRQ_ETH1 0x3 -#define PN62_IRQ_COM1 0x4 -#define PN62_IRQ_COM2 0x4 - -/* - * Miscellaneous definitons. - */ -#define PN62_SMEM_DEFAULT 0x1f00000 - -/* - * Definitions for boot protocol using Scratchpad registers. - */ -#define BOOT_DONE 0 -#define BOOT_DONE_CLEAR 0x00dead00 -#define BOOT_DONE_ERROR 0xbad0dead -#define BOOT_DONE_U_BOOT 0x12345678 -#define BOOT_DONE_LINUX 0x87654321 -#define BOOT_CMD 1 -#define BOOT_CMD_MOVE 0x1 -#define BOOT_CMD_BOOT 0x2 -#define BOOT_DATA 2 -#define BOOT_PROTO 3 -#define BOOT_PROTO_READY 0x23456789 -#define BOOT_PROTO_CLEAR 0x00000000 -#define BOOT_STATUS 4 - -/* - * LED Definitions: - */ -#define PN62_LED_BASE 0xff800300 -#define PN62_LED_MAX 12 - -/* - * LED0 - 7 mounted on top of board, D1 - D8 - * LED8 - 11 upper four LEDs on the front panel of the board. - */ -#define LED_0 0x00 /* OFF */ -#define LED_1 0x01 /* ON */ -#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */ -#define LED_nSLOW_CLOCK 0x03 /* inverse of above */ -#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */ -#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */ - -/* - * LED's currently setup in AMD79C973 device as the following: - * LED0 100Mbit - * LED1 LNKSE - * LED2 TX Activity - * LED3 RX Activity - */ -#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */ -#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */ -#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */ -#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */ -#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */ -#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */ -#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */ -#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */ -#define LED_STROBE0 0x10 /* Processor Strobe 0 */ -#define LED_STROBE1 0x11 /* Processor Strobe 1 */ -#define LED_STROBE2 0x12 /* Processor Strobe 2 */ -#define LED_STROBE3 0x13 /* Processor Strobe 3 */ -#define LED_STROBE4 0x14 /* Processor Strobe 4 */ -#define LED_STROBE5 0x15 /* Processor Strobe 5 */ -#define LED_STROBE6 0x16 /* Processor Strobe 6 */ -#define LED_STROBE7 0x17 /* Processor Strobe 7 */ -#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */ -#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */ -#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */ -#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */ -#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */ -#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */ -#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */ -#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */ -#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */ -#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */ -#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */ -#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */ -#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */ -#define LED_UART0_CS 0x25 /* UART 0 Chip Select */ -#define LED_UART1_CS 0x26 /* UART 1 Chip Select */ -#define LED_SRAM_CS 0x27 /* SRAM Chip Select */ -#define LED_SRAM_WR 0x28 /* SRAM WR Signal */ -#define LED_SRAM_RD 0x29 /* SRAM RD Signal */ -#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */ -#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */ -#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */ -#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */ -#define LED_LAST_FUNCTION LED_HOST_INT /* last function */ - -/* - * Forward declarations - */ -int i2155x_init (void); -void i2155x_write_scrapad(int idx, u32 val); -u32 i2155x_read_scrapad (int idx); -void i2155x_set_bar_base (int bar, u32 addr); -int i2155x_read_vpd (int offset, int size, unsigned char *data); - -int am79c95x_init (void); - -void set_led (unsigned int number, unsigned int function); -void fatal_error (unsigned int error_code); -void show_startup_phase (int phase); - - -#endif /* _PN62_H_ */ diff --git a/board/ppcag/bg0900/Kconfig b/board/ppcag/bg0900/Kconfig new file mode 100644 index 0000000000..d7f2368a23 --- /dev/null +++ b/board/ppcag/bg0900/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BG0900 + +config SYS_BOARD + default "bg0900" + +config SYS_VENDOR + default "ppcag" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "bg0900" + +endif diff --git a/board/ppcag/bg0900/MAINTAINERS b/board/ppcag/bg0900/MAINTAINERS new file mode 100644 index 0000000000..853c0d59c8 --- /dev/null +++ b/board/ppcag/bg0900/MAINTAINERS @@ -0,0 +1,6 @@ +BG0900 BOARD +M: Marek Vasut +S: Maintained +F: board/ppcag/bg0900/ +F: include/configs/bg0900.h +F: configs/bg0900_defconfig diff --git a/board/ppcag/bg0900/Makefile b/board/ppcag/bg0900/Makefile new file mode 100644 index 0000000000..74c6db5b15 --- /dev/null +++ b/board/ppcag/bg0900/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y := bg0900.o +else +obj-y := spl_boot.o +endif diff --git a/board/ppcag/bg0900/bg0900.c b/board/ppcag/bg0900/bg0900.c new file mode 100644 index 0000000000..06612fa34d --- /dev/null +++ b/board/ppcag/bg0900/bg0900.c @@ -0,0 +1,86 @@ +/* + * PPC-AG BG0900 board + * + * Copyright (C) 2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + + /* BG0900 uses ENET_CLK PAD to drive FEC clock */ + writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, + &clkctrl_regs->hw_clkctrl_enet); + + /* Reset FEC PHYs */ + gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); + udelay(200); + gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); + + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + puts("FEC MXS: Unable to init FEC0\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC0"); + if (!dev) { + puts("FEC MXS: Unable to get FEC0 device entry\n"); + return -EINVAL; + } + + return ret; +} + +#endif diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c new file mode 100644 index 0000000000..a04c9553e4 --- /dev/null +++ b/board/ppcag/bg0900/spl_boot.c @@ -0,0 +1,153 @@ +/* + * PPC-AG BG0900 Boot setup + * + * Copyright (C) 2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) + +const iomux_cfg_t iomux_setup[] = { + /* DUART */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, + + /* FEC0 */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + /* FEC0 Reset */ + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* SPI2 (for SPI flash) */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* + * DDR Controller Registers + * Manufacturer: Winbond + * Device Part Number: W972GG6JB-25I + * Clock Freq.: 200MHz + * Density: 2Gb + * Chip Selects: 1 + * Number of Banks: 8 + * Row address: 14 + * Column address: 10 + */ + + dram_vals[0x74 / 4] = 0x0102010A; + dram_vals[0x98 / 4] = 0x04005003; + dram_vals[0x9c / 4] = 0x090000c8; + + dram_vals[0xa8 / 4] = 0x0036b009; + dram_vals[0xac / 4] = 0x03270612; + + dram_vals[0xb0 / 4] = 0x02020202; + dram_vals[0xb4 / 4] = 0x00c80029; + + dram_vals[0xc0 / 4] = 0x00011900; + + dram_vals[0x12c / 4] = 0x07400300; + dram_vals[0x130 / 4] = 0x07400300; + dram_vals[0x2c4 / 4] = 0x02030303; +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile deleted file mode 100644 index c6abc77cee..0000000000 --- a/board/ppmc7xx/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -SOBJS := init.o - -COBJS := ppmc7xx.o pci.o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c deleted file mode 100644 index e7242271dd..0000000000 --- a/board/ppmc7xx/flash.c +++ /dev/null @@ -1,494 +0,0 @@ -/* - * flash.c - * ------- - * - * Flash programming routines for the Wind River PPMC 74xx/7xx - * based on flash.c from the TQM8260 board. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - */ - -#include -#include -#include <74xx_7xx.h> - -#define DWORD unsigned long long - -/* Local function prototypes */ -static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata); -static void write_via_fpu (volatile DWORD* addr, DWORD* data); - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -void flash_reset (void) -{ - unsigned long msr; - DWORD cmd_reset = 0x00F000F000F000F0LL; - - if (flash_info[0].flash_id != FLASH_UNKNOWN) { - msr = get_msr (); - set_msr (msr | MSR_FP); - - write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset ); - - set_msr (msr); - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (ulong baseaddr, flash_info_t * info) -{ - int i; - unsigned long msr; - DWORD flashtest; - DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, - 0x0090009000900090LL }; - - /* Enable FPU */ - msr = get_msr (); - set_msr (msr | MSR_FP); - - /* Write auto-select command sequence */ - write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] ); - write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] ); - write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] ); - - /* Restore FPU */ - set_msr (msr); - - /* Read manufacturer ID */ - flashtest = *(volatile DWORD*)baseaddr; - switch ((int)flashtest) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - /* No, faulty or unknown flash */ - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); - } - - /* Read device ID */ - flashtest = *(volatile DWORD*)(baseaddr + 8); - switch ((long)flashtest) { - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00400000; - break; - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; - break; - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00800000; - break; - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00800000; - break; - case AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x01000000; - break; - case AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x01000000; - break; - case AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x01000000; - break; - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x02000000; - break; - default: - /* Unknown flash type */ - info->flash_id = FLASH_UNKNOWN; - return (0); - } - - if ((long)flashtest == AMD_ID_LV640U) { - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - } else if (info->flash_id & FLASH_BTYPE) { - /* set up sector start adress table (bottom sector type) */ - info->start[0] = baseaddr + 0x00000000; - info->start[1] = baseaddr + 0x00010000; - info->start[2] = baseaddr + 0x00018000; - info->start[3] = baseaddr + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; - } - } else { - /* set up sector start adress table (top sector type) */ - i = info->sector_count - 1; - info->start[i--] = baseaddr + info->size - 0x00010000; - info->start[i--] = baseaddr + info->size - 0x00018000; - info->start[i--] = baseaddr + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = baseaddr + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset (); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* - * protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - printf ("29LV800T (8 M, top sector)\n"); - break; - case FLASH_AM800B: - printf ("29LV800T (8 M, bottom sector)\n"); - break; - case FLASH_AM160T: - printf ("29LV160T (16 M, top sector)\n"); - break; - case FLASH_AM160B: - printf ("29LV160B (16 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: - printf ("29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: - printf ("29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: - printf ("29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: - printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: - printf ("29LV640D (64 M, uniform sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned long msr; - DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, - 0x0080008000800080LL, 0x00AA00AA00AA00AALL, - 0x0055005500550055LL, 0x0030003000300030LL }; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Enable FPU */ - msr = get_msr(); - set_msr ( msr | MSR_FP ); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] ); - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] ); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* Restore FPU */ - set_msr (msr); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL ) - != 0x0080008000800080LL ) - { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++; - if ((rc = write_dword (info, dp, bb)) != 0) { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword (info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : *(char*)(dp + i); - } - return (write_dword (info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) -{ - ulong start; - unsigned long msr; - int flag, i; - DWORD data; - DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, - 0x00A000A000A000A0LL }; - - for (data = 0, i = 0; i < 8; i++) - data = (data << 8) + *pdata++; - - /* Check if Flash is (sufficiently) erased */ - if ((*(DWORD*)dest & data) != data) { - return (2); - } - - /* Enable FPU */ - msr = get_msr(); - set_msr( msr | MSR_FP ); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] ); - write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] ); - write_via_fpu ((DWORD*)dest, &data ); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* Restore FPU */ - set_msr(msr); - - /* data polling for D7 */ - start = get_timer (0); - while (*(volatile DWORD*)dest != data ) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu (volatile DWORD* addr, DWORD* data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); - __asm__ __volatile__ ("eieio"); -} diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S deleted file mode 100644 index 99a818ad02..0000000000 --- a/board/ppmc7xx/init.S +++ /dev/null @@ -1,336 +0,0 @@ -/* - * init.S - * ------ - * - * Wind River PPMC 7xx/74xx init code. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - * - * NOTE: The following code was generated automatically by Workbench - * from the ppmc7400_107.reg register file. - */ - -#include - - -.globl board_asm_init -board_asm_init: - - lis r4,0xFEC0 - ori r4,r4,0x0000 - lis r5,0xFEE0 - ori r5,r5,0x0000 - lis r3,0x8000 # ADDR_00 - ori r3,r3,0x0000 - stwbrx r3,0,r4 - li r3,0x1057 # VENDOR - li r8, 0x0 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_02 - ori r3,r3,0x0002 - stwbrx r3,0,r4 - li r3,0x0004 # ID - li r8, 0x2 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_04 - ori r3,r3,0x0004 - stwbrx r3,0,r4 - li r3,0x0006 # PCICMD - li r8, 0x0 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_06 - ori r3,r3,0x0006 - stwbrx r3,0,r4 - li r3,0x00A0 # PCISTAT - li r8, 0x2 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_08 - ori r3,r3,0x0008 - stwbrx r3,0,r4 - li r3,0x10 # REVID - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_09 - ori r3,r3,0x0009 - stwbrx r3,0,r4 - li r3,0x00 # PROGIR - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_0A - ori r3,r3,0x000A - stwbrx r3,0,r4 - li r3,0x00 # SUBCCODE - stb r3,0x2(r5) - lis r3,0x8000 # ADDR_0B - ori r3,r3,0x000B - stwbrx r3,0,r4 - li r3,0x06 # PBCCR - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_0C - ori r3,r3,0x000C - stwbrx r3,0,r4 - li r3,0x08 # PCLSR - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_0D - ori r3,r3,0x000D - stwbrx r3,0,r4 - li r3,0x00 # PLTR - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_0E - ori r3,r3,0x000E - stwbrx r3,0,r4 - li r3,0x00 # HEADTYPE - stb r3,0x2(r5) - lis r3,0x8000 # ADDR_0F - ori r3,r3,0x000F - stwbrx r3,0,r4 - li r3,0x00 # BISTCTRL - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_10 - ori r3,r3,0x0010 - stwbrx r3,0,r4 - lis r3,0x0000 # LMBAR - ori r3,r3,0x0008 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_14 - ori r3,r3,0x0014 - stwbrx r3,0,r4 - lis r3,0xF000 # PCSRBAR - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_3C - ori r3,r3,0x003C - stwbrx r3,0,r4 - li r3,0x00 # ILR - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_3D - ori r3,r3,0x003D - stwbrx r3,0,r4 - li r3,0x01 # INTPIN - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_3E - ori r3,r3,0x003E - stwbrx r3,0,r4 - li r3,0x00 # MIN_GNT - stb r3,0x2(r5) - lis r3,0x8000 # ADDR_3F - ori r3,r3,0x003F - stwbrx r3,0,r4 - li r3,0x00 # MAX_LAT - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_40 - ori r3,r3,0x0040 - stwbrx r3,0,r4 - li r3,0x00 # BUSNB - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_41 - ori r3,r3,0x0041 - stwbrx r3,0,r4 - li r3,0x00 # SBUSNB - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_46 - ori r3,r3,0x0046 - stwbrx r3,0,r4 -# li r3,0xE080 # PCIARB - li r3,-0x1F80 # PCIARB - li r8, 0x2 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_70 - ori r3,r3,0x0070 - stwbrx r3,0,r4 - li r3,0x0000 # PMCR1 - li r8, 0x0 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_72 - ori r3,r3,0x0072 - stwbrx r3,0,r4 - li r3,0xC0 # PMCR2 - stb r3,0x2(r5) - lis r3,0x8000 # ADDR_73 - ori r3,r3,0x0073 - stwbrx r3,0,r4 - li r3,0xEF # ODCR - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_74 - ori r3,r3,0x0074 - stwbrx r3,0,r4 - li r3,0x7D00 # CLKDCR - li r8, 0x0 - sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_76 - ori r3,r3,0x0076 - stwbrx r3,0,r4 - li r3,0x00 # MDCR - stb r3,0x2(r5) - lis r6,0xFCE0 - ori r6,r6,0x0000 # r6 is the EUMBAR Base Address - lis r3,0x8000 # ADDR_78 - ori r3,r3,0x0078 - stwbrx r3,0,r4 - lis r3,0xFCE0 # EUMBBAR - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_80 - ori r3,r3,0x0080 - stwbrx r3,0,r4 - lis r3,0xFFFF # MSADDR1 - ori r3,r3,0x4000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_84 - ori r3,r3,0x0084 - stwbrx r3,0,r4 - lis r3,0xFFFF # MSADDR2 - ori r3,r3,0xFFFF - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_88 - ori r3,r3,0x0088 - stwbrx r3,0,r4 - lis r3,0x0303 # EMSADDR1 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_8C - ori r3,r3,0x008C - stwbrx r3,0,r4 - lis r3,0x0303 # EMSADDR2 - ori r3,r3,0x0303 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_90 - ori r3,r3,0x0090 - stwbrx r3,0,r4 - lis r3,0xFFFF # EMEADDR1 - ori r3,r3,0x7F3F - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_94 - ori r3,r3,0x0094 - stwbrx r3,0,r4 - lis r3,0xFFFF # EMEADDR2 - ori r3,r3,0xFFFF - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_98 - ori r3,r3,0x0098 - stwbrx r3,0,r4 - lis r3,0x0303 # EXTEMEM1 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_9C - ori r3,r3,0x009C - stwbrx r3,0,r4 - lis r3,0x0303 # EXTEMEM2 - ori r3,r3,0x0303 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_A0 - ori r3,r3,0x00A0 - stwbrx r3,0,r4 - li r3,0x03 # MEMBNKEN - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_A3 - ori r3,r3,0x00A3 - stwbrx r3,0,r4 - li r3,0x00 # MEMPMODE - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_B8 - ori r3,r3,0x00B8 - stwbrx r3,0,r4 - li r3,0x00 # ECCCNT - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_B9 - ori r3,r3,0x00B9 - stwbrx r3,0,r4 - li r3,0x00 # ECCTRG - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C0 - ori r3,r3,0x00C0 - stwbrx r3,0,r4 - li r3,0xFF # ERRENR1 - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_C1 - ori r3,r3,0x00C1 - stwbrx r3,0,r4 - li r3,0x00 # ERRDR1 - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C3 - ori r3,r3,0x00C3 - stwbrx r3,0,r4 - li r3,0x50 # IPBESR - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_C4 - ori r3,r3,0x00C4 - stwbrx r3,0,r4 - li r3,0xBF # ERRENR2 - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_C5 - ori r3,r3,0x00C5 - stwbrx r3,0,r4 - li r3,0x00 # ERRDR2 - stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C7 - ori r3,r3,0x00C7 - stwbrx r3,0,r4 - li r3,0x00 # PCIBESR - stb r3,0x3(r5) - lis r3,0x8000 # ADDR_C8 - ori r3,r3,0x00C8 - stwbrx r3,0,r4 - lis r3,0x0000 # BERRADDR - ori r3,r3,0xE0FE - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_E0 - ori r3,r3,0x00E0 - stwbrx r3,0,r4 - li r3,0xC0 # AMBOR - stb r3,0x0(r5) - lis r3,0x8000 # ADDR_F4 - ori r3,r3,0x00F4 - stwbrx r3,0,r4 - lis r3,0x0000 # MCCR2 - ori r3,r3,0x020C - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_F8 - ori r3,r3,0x00F8 - stwbrx r3,0,r4 - lis r3,0x0230 # MCCR3 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_FC - ori r3,r3,0x00FC - stwbrx r3,0,r4 - lis r3,0x2532 # MCCR4 - ori r3,r3,0x2220 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_F0 - ori r3,r3,0x00F0 - stwbrx r3,0,r4 - lis r3,0xFFC8 # MCCR1 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_A8 - ori r3,r3,0x00A8 - stwbrx r3,0,r4 - lis r3,0xFF14 # PICR1 - ori r3,r3,0x1CC8 - li r8, 0x0 - stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_AC - ori r3,r3,0x00AC - stwbrx r3,0,r4 - lis r3,0x0000 # PICR2 - ori r3,r3,0x0000 - li r8, 0x0 - stwbrx r3,r8,r5 - - blr diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c deleted file mode 100644 index d81a41aadc..0000000000 --- a/board/ppmc7xx/pci.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI initialisation for the MPC10x. - */ - -#include -#include -#include - -#ifdef CONFIG_PCI - -struct pci_controller local_hose; - -void pci_init_board(void) -{ - struct pci_controller* hose = (struct pci_controller *)&local_hose; - u16 reg16; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI_MEM_BUS, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_ISA_MEM_BUS, - CONFIG_SYS_ISA_MEM_PHYS, - CONFIG_SYS_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CONFIG_SYS_PCI_IO_BUS, - CONFIG_SYS_PCI_IO_PHYS, - CONFIG_SYS_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CONFIG_SYS_ISA_IO_BUS, - CONFIG_SYS_ISA_IO_PHYS, - CONFIG_SYS_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - MPC106_REG_ADDR, - MPC106_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* Initialises the MPC10x PCI Configuration regs. */ - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* Clear non-reserved bits in status register */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); -} - -#endif /* CONFIG_PCI */ diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c deleted file mode 100644 index 432d366a40..0000000000 --- a/board/ppmc7xx/ppmc7xx.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * ppmc7xx.c - * --------- - * - * Main board-specific routines for Wind River PPMC 7xx/74xx board. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - */ - -#include -#include -#include - - -/* Define some MPC107 (memory controller) registers */ -#define MPC107_EUMB_GCR 0xfce41020 -#define MPC107_EUMB_IACKR 0xfce600a0 - - -/* Function prototypes */ -extern void _start(void); - - -/* - * initdram() - * - * This function normally initialises the (S)DRAM of the system. For this board - * the SDRAM was already initialised by board_asm_init (see init.S) so we just - * return the size of RAM. - */ -phys_size_t initdram( int board_type ) -{ - return CONFIG_SYS_SDRAM_SIZE; -} - - -/* - * after_reloc() - * - * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives - * us an opportunity to do some additional setup before the rest of the system - * is initialised. We don't need to do anything, so we just call board_init_r() - * which should never return. - */ -void after_reloc( ulong dest_addr, gd_t* gd ) -{ - /* Jump to the main U-Boot board init code */ - board_init_r( gd, dest_addr ); -} - - -/* - * checkboard() - * - * We could do some board level checks here, such as working out what version - * it is, but for this board we simply display it's name (on the console). - */ -int checkboard( void ) -{ - puts( "Board: Wind River PPMC 7xx/74xx\n" ); - return 0; -} - - -/* - * misc_init_r - * - * Used for other setup which needs to be done late in the bring-up phase. - */ -int misc_init_r( void ) -{ - /* Reset the EPIC and clear pending interrupts */ - out32r(MPC107_EUMB_GCR, 0xa0000000); - while( in32r( MPC107_EUMB_GCR ) & 0x80000000 ); - out32r( MPC107_EUMB_GCR, 0x20000000 ); - while( in32r( MPC107_EUMB_IACKR ) != 0xff ); - - /* Enable the I-Cache */ - icache_enable(); - - return 0; -} - - -/* - * do_reset() - * - * Shell command to reset the board. - */ -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf( "Resetting...\n" ); - - /* Disabe and invalidate cache */ - icache_disable(); - dcache_disable(); - - /* Jump to cold reset point (in RAM) */ - _start(); - - /* Should never get here */ - while(1) - ; - - return 1; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile deleted file mode 100644 index d0e543cf29..0000000000 --- a/board/ppmc8260/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ppmc8260.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c deleted file mode 100644 index f0f29b2f68..0000000000 --- a/board/ppmc8260/ppmc8260.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_A1:L1TSYNC */ - /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* TDN_A1:L1RSYNC */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_A1:L1CLK0 */ - /* PB15 */ { 1, 0, 0, 1, 0, 1 }, /* /FETHRST */ - /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* FETHDIS */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_B1:L1CLK0 */ - /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TXD */ - /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RXD */ - /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TSYNC */ - /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RSYNC */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* CLK4 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* CLK7 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[0] */ - /* PC14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[0] */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[1] */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[1] */ - /* PC11 */ { 1, 1, 0, 1, 0, 0 }, /* TDM_D1:L1CLK0 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[2]*/ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[2] */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DACK */ - /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DONE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DREQ */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DREQ */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[3] */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_C1:L1RSYNC */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TXD */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RXD */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TSYNC */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RSYNC*/ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1:TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:RXD */ - /* PD7 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:SMSYN */ - /* PD6 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DACK */ - /* PD5 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DONE */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: Wind River PPMC8260\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0xff; - volatile uchar *ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE); - volatile uchar *ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE); - ulong psdmr = CONFIG_SYS_PSDMR; - volatile uchar *ramaddr2 = (uchar *) (CONFIG_SYS_SDRAM2_BASE); - ulong lsdmr = CONFIG_SYS_LSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr0++ = c; - *ramaddr1++ = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr0++ = c; - *ramaddr1++ = c; - } - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE + 0x110); - ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE + 0x110); - *ramaddr0 = c; - *ramaddr1 = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr0 = c; - *ramaddr1 = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; - *ramaddr2++ = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr2++ = c; - } - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; - *ramaddr2++ = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr2 = c; -#endif - - /* return total ram size */ - return ((CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) * 1024 * 1024); -} - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ -#ifdef CONFIG_SYS_LED_BASE - uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1); - uchar ss; - uchar tmp[64]; - int res; - - if ((ds != 0) && (ds != 0xff)) { - res = getenv_f("ethaddr", (char *)tmp, sizeof (tmp)); - if (res > 0) { - ss = ((ds >> 4) & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[15] = ss; - - ss = (ds & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[16] = ss; - - tmp[17] = '\0'; - setenv ("ethaddr", (char *)tmp); - /* set the led to show the address */ - *((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds; - } - } -#endif /* CONFIG_SYS_LED_BASE */ - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ diff --git a/board/ppmc8260/strataflash.c b/board/ppmc8260/strataflash.c deleted file mode 100644 index 3f4fcb93eb..0000000000 --- a/board/ppmc8260/strataflash.c +++ /dev/null @@ -1,736 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CONFIG_SYS_FLASH_BASE; - size = 0; - - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;iportwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; iportwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; isector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/pr1/Kconfig b/board/pr1/Kconfig new file mode 100644 index 0000000000..fb04648716 --- /dev/null +++ b/board/pr1/Kconfig @@ -0,0 +1,9 @@ +if TARGET_PR1 + +config SYS_BOARD + default "pr1" + +config SYS_CONFIG_NAME + default "pr1" + +endif diff --git a/board/pr1/MAINTAINERS b/board/pr1/MAINTAINERS new file mode 100644 index 0000000000..23fdbc7a76 --- /dev/null +++ b/board/pr1/MAINTAINERS @@ -0,0 +1,6 @@ +PR1 BOARD +M: Dimitar Penev +S: Maintained +F: board/pr1/ +F: include/configs/pr1.h +F: configs/pr1_defconfig diff --git a/board/pr1/Makefile b/board/pr1/Makefile index f023abfee4..4f375a8b5c 100644 --- a/board/pr1/Makefile +++ b/board/pr1/Makefile @@ -11,24 +11,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := pr1.o diff --git a/board/pr1/config.mk b/board/pr1/config.mk deleted file mode 100644 index 5c18d5c9e4..0000000000 --- a/board/pr1/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) Switchfin Org. -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/prodrive/alpr/Kconfig b/board/prodrive/alpr/Kconfig new file mode 100644 index 0000000000..543b4557ee --- /dev/null +++ b/board/prodrive/alpr/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ALPR + +config SYS_BOARD + default "alpr" + +config SYS_VENDOR + default "prodrive" + +config SYS_CONFIG_NAME + default "alpr" + +endif diff --git a/board/prodrive/alpr/MAINTAINERS b/board/prodrive/alpr/MAINTAINERS new file mode 100644 index 0000000000..31baabb67e --- /dev/null +++ b/board/prodrive/alpr/MAINTAINERS @@ -0,0 +1,6 @@ +ALPR BOARD +M: Stefan Roese +S: Maintained +F: board/prodrive/alpr/ +F: include/configs/alpr.h +F: configs/alpr_defconfig diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile index 5345df8c9f..812d041ef2 100644 --- a/board/prodrive/alpr/Makefile +++ b/board/prodrive/alpr/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o fpga.o nand.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = alpr.o fpga.o nand.o +extra-y += init.o diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 56533dfadb..31c1ab5d0f 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -2,7 +2,7 @@ * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S index 0f24a19b7f..7ff7a59170 100644 --- a/board/prodrive/alpr/init.S +++ b/board/prodrive/alpr/init.S @@ -2,7 +2,7 @@ * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index 50e8d82b4b..5427de5634 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -93,6 +93,7 @@ static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; @@ -103,6 +104,7 @@ static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len return 0; } +#endif static int alpr_nand_dev_ready(struct mtd_info *mtd) { @@ -128,7 +130,9 @@ int board_nand_init(struct nand_chip *nand) nand->read_byte = alpr_nand_read_byte; nand->write_buf = alpr_nand_write_buf; nand->read_buf = alpr_nand_read_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) nand->verify_buf = alpr_nand_verify_buf; +#endif nand->dev_ready = alpr_nand_dev_ready; return 0; diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c deleted file mode 100644 index 9954051852..0000000000 --- a/board/prodrive/common/flash.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Functions - */ -static int write_word(flash_info_t *info, ulong dest, ulong data); - -void flash_print_info(flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("ST "); break; - case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n"); - break; - case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - short n; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - - value = addr2[CONFIG_SYS_FLASH_READ0]; - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: - info->flash_id = FLASH_MAN_EXCEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020: - info->flash_id += FLASH_SST020; - info->sector_count = 64; - info->size = 0x00040000; - break; /* => 256 kB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040: - info->flash_id += FLASH_SST040; - info->sector_count = 128; - info->size = 0x00080000; - break; /* => 512 kB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00001000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) - info->protect[i] = 0; - else - info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) - if (info->protect[sect]) - prot++; - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - flag = 0; - } - - /* data polling for D7 */ - start = get_timer (0); - while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } else { - if (sect == s_first) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - } - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) - data = (data << 8) | *src++; - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return (0); - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} diff --git a/board/prodrive/common/fpga.c b/board/prodrive/common/fpga.c deleted file mode 100644 index 9dce131376..0000000000 --- a/board/prodrive/common/fpga.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2001-2004 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#ifdef FPGA_DEBUG -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -#define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/ -#define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output) */ -#define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output) */ -#define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input) */ -#define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input) */ - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ - -#ifndef OLD_VAL -# define OLD_VAL 0 -#endif - -#if 0 /* test-only */ -#define FPGA_WRITE_1 { \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 ); /* set clock to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ -#else -#define FPGA_WRITE_1 { \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 );} /* set data to 1 */ -#endif - -static int fpga_boot(unsigned char *fpgadata, int size) -{ - int i,index,len; - int count; - int j; - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = fpgadata[index]; - DBG("FPGA: %s\n", &(fpgadata[index+1])); - index += len+3; - } - - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) && - (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff)) - break; /* preamble found */ - else - index++; - } - - DBG("FPGA: configdata starts at position 0x%x\n",index); - DBG("FPGA: length of fpga-data %d\n", size-index); - - /* - * Setup port pins for fpga programming - */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */ - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA(0 | FPGA_CLK | FPGA_DATA); /* set prog active */ - - /* Wait for FPGA init line low */ - count = 0; - while (FPGA_INIT_STATE) { - udelay(1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - /* deassert PROGRAM* */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set prog inactive */ - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(FPGA_INIT_STATE)) { - udelay(1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - DBG("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - - /* - * Load uncompressed image into fpga - */ - for (i=index; i 3) { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - DBG("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/prodrive/p3mx/64460.h b/board/prodrive/p3mx/64460.h deleted file mode 100644 index 9cf7feea58..0000000000 --- a/board/prodrive/p3mx/64460.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * main board support/init for the Galileo Eval board DB64460. - */ - -#ifndef __64460_H__ -#define __64460_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64460_H__ */ diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile deleted file mode 100644 index 63ee945d2a..0000000000 --- a/board/prodrive/p3mx/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../Marvell/common) -endif - -LIB = $(obj)lib$(BOARD).o - -SOBJS = misc.o -COBJS = $(BOARD).o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \ - ../../Marvell/common/i2c.o ../../Marvell/common/memory.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/prodrive/p3mx/eth.h b/board/prodrive/p3mx/eth.h deleted file mode 100644 index d5fe3cb5d3..0000000000 --- a/board/prodrive/p3mx/eth.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64360_ETH_H__ -#define __EVB64360_ETH_H__ - -#include -#include -#include -#include - - -int db64360_eth0_poll(void); -int db64360_eth0_transmit(unsigned int s, volatile char *p); -void db64360_eth0_disable(void); -bool network_start(bd_t *bis); - -int mv6446x_eth_initialize(bd_t *); - -#endif /* __EVB64360_ETH_H__ */ diff --git a/board/prodrive/p3mx/misc.S b/board/prodrive/p3mx/misc.S deleted file mode 100644 index 233fd83bcc..0000000000 --- a/board/prodrive/p3mx/misc.S +++ /dev/null @@ -1,245 +0,0 @@ -#include -#include <74xx_7xx.h> -#include "version.h" - -#include -#include - -#include -#include - -#include "../../Marvell/include/mv_gen_reg.h" - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CONFIG_SYS_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CONFIG_SYS_MONITOR_LEN@h - ori r8, r8, CONFIG_SYS_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CONFIG_SYS_DFL_GT_REGS@h - ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ -/* rlwinm r7, r4, 8, 16, 31 - rlwinm r7, r4, 12, 16, 31 */ /* original */ - rlwinm r7, r4, 16, 16, 31 - /* -----------------------------------------------------*/ - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - lis r3, CONFIG_SYS_INT_SRAM_BASE@h - ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l - rlwinm r3, r3, 16, 16, 31 - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTEGRATED_SRAM_BASE_ADDR - stwbrx r3, r5, r4 - -2: lwbrx r6, r5, r4 - cmp cr0, r3, r6 - bne 2b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0_relocated -led_on0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC80 - ori r18, r18, 0x8000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_off0_relocated -led_off0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC81 - ori r18, r18, 0x4000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off0 -led_off0: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x4000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off1 -led_off1: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off2 -led_off2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c deleted file mode 100644 index 97d09093bf..0000000000 --- a/board/prodrive/p3mx/mpsc.c +++ /dev/null @@ -1,997 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64460 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include -#include -#include - -#include -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../../Marvell/include/memory.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ - /* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - - /* Enable MPSC-Window0 for DRAM Bank 0 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress(0), - memoryGetBankSize(0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - - /* Enable MPSC-Window1 for DRAM Bank 1 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64460_SDMA_DRAM_CS_1_TARGET, - 0, - memoryGetBankBaseAddress(1), - memoryGetBankSize(1)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - - /* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64460_SDMA_DRAM_CS_2_TARGET, - 0, - memoryGetBankBaseAddress(2), - memoryGetBankSize(2)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - - /* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64460_SDMA_DRAM_CS_3_TARGET, - 0, - memoryGetBankBaseAddress(3), - memoryGetBankSize(3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - - /* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - - /* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - - /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); - - /* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - - /* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#else - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64460 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* true for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/prodrive/p3mx/mpsc.h b/board/prodrive/p3mx/mpsc.h deleted file mode 100644 index 241f28a31a..0000000000 --- a/board/prodrive/p3mx/mpsc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../../Marvell/include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c deleted file mode 100644 index ebd93c0288..0000000000 --- a/board/prodrive/p3mx/mv_eth.c +++ /dev/null @@ -1,3291 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include -#include -#include -#include - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* PHY DFCDL Registers */ -#define ETH_PHY_DFCDL_CONFIG0_REG 0x2100 -#define ETH_PHY_DFCDL_CONFIG1_REG 0x2104 -#define ETH_PHY_DFCDL_ADDR_REG 0x2110 -#define ETH_PHY_DFCDL_DATA0_REG 0x2114 - -#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ -#define PHY_UPDATE_TIMEOUT 10000 - -#undef MV64460_CHECKSUM_OFFLOAD -/************************************************************************* -* The first part is the high level driver of the gigE ethernet ports. * -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64460_RX_QUEUE_FILL_ON_TASK - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64460_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64460_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64460 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -/* Static function declarations */ -static int mv64460_eth_real_open (struct eth_device *eth); -static int mv64460_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64460_eth_update_stat (struct eth_device *dev); -bool db64460_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64460_eth_receive (struct eth_device *dev); - -int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length); - -int mv_miiphy_read(const char *devname, unsigned char phy_addr, - unsigned char phy_reg, unsigned short *value); -int mv_miiphy_write(const char *devname, unsigned char phy_addr, - unsigned char phy_reg, unsigned short value); - -int phy_setup_aneg (char *devname, unsigned char addr); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64460_eth_print_stat (struct eth_device *dev); -#endif - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64460_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32); -} -#endif - -/********************************************************************** - * mv64460_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ -void mv64460_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64460_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64460_eth - * - **********************************************************************/ -int db64460_eth_probe (struct eth_device *dev) -{ - return ((int) db64460_eth_start (dev)); -} - -int db64460_eth_poll (struct eth_device *dev) -{ - return mv64460_eth_receive (dev); -} - -int db64460_eth_transmit(struct eth_device *dev, void *packet, int length) -{ - mv64460_eth_xmit (dev, packet, length); - return 0; -} - -void db64460_eth_disable (struct eth_device *dev) -{ - mv64460_eth_stop (dev); -} - -#define DFCDL(write,read) ((write << 6) | read) -unsigned int ethDfcdls[] = { - DFCDL(0,0), DFCDL(1,1), DFCDL(2,2), DFCDL(3,3), - DFCDL(4,4), DFCDL(5,5), DFCDL(6,6), DFCDL(7,7), - DFCDL(8,8), DFCDL(9,9), DFCDL(10,10), DFCDL(11,11), - DFCDL(12,12), DFCDL(13,13), DFCDL(14,14), DFCDL(15,15), - DFCDL(16,16), DFCDL(17,17), DFCDL(18,18), DFCDL(19,19), - DFCDL(20,20), DFCDL(21,21), DFCDL(22,22), DFCDL(23,23), - DFCDL(24,24), DFCDL(25,25), DFCDL(26,26), DFCDL(27,27), - DFCDL(28,28), DFCDL(29,29), DFCDL(30,30), DFCDL(31,31), - DFCDL(32,32), DFCDL(33,33), DFCDL(34,34), DFCDL(35,35), - DFCDL(36,36), DFCDL(37,37), DFCDL(38,38), DFCDL(39,39), - DFCDL(40,40), DFCDL(41,41), DFCDL(42,42), DFCDL(43,43), - DFCDL(44,44), DFCDL(45,45), DFCDL(46,46), DFCDL(47,47), - DFCDL(48,48), DFCDL(49,49), DFCDL(50,50), DFCDL(51,51), - DFCDL(52,52), DFCDL(53,53), DFCDL(54,54), DFCDL(55,55), - DFCDL(56,56), DFCDL(57,57), DFCDL(58,58), DFCDL(59,59), - DFCDL(60,60), DFCDL(61,61), DFCDL(62,62), DFCDL(63,63), -}; - -void mv_eth_phy_init (void) -{ - int i; - - MV_REG_WRITE (ETH_PHY_DFCDL_ADDR_REG, 0); - - for (i = 0; i < 64; i++) { - MV_REG_WRITE (ETH_PHY_DFCDL_DATA0_REG, ethDfcdls[i]); - } - - MV_REG_WRITE (ETH_PHY_DFCDL_CONFIG0_REG, 0x300000); -} - -void mv6446x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - /* P3M750 only - * Set RGMII clock drives strength - */ - temp = MV_REG_READ(0x20A0); - temp |= 0x04000080; - MV_REG_WRITE(0x20A0, temp); - - mv_eth_phy_init(); - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - case 1: - s = "eth1addr"; - break; - case 2: - s = "eth2addr"; - break; - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64460_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64460_eth_transmit; - dev->recv = (void *) db64460_eth_poll; - - ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *)ethernet_private; - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64460_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64460_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - case 1: - s = "eth1addr"; - break; - case 2: - s = "eth2addr"; - break; - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64460_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64460_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - miiphy_register(dev->name, mv_miiphy_read, mv_miiphy_write); - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64460_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64460_eth_open (struct eth_device *dev) -{ - return (mv64460_eth_real_open (dev)); -} - -/* Helper function for mv64460_eth_open */ -static int mv64460_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - ushort reg_short; - int speed; - int duplex; - int i; - int reg; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x1 + (port_num << 1); - reg = ethernet_private->port_phy_addr; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - -#if defined(CONFIG_PHY_RESET) - /* - * Reset the phy, only if its the first time through - * otherwise, just check the speeds & feeds - */ - if (port_private->first_init == 0) { - port_private->first_init = 1; - ethernet_phy_reset (port_num); - - /* Start/Restart autonegotiation */ - phy_setup_aneg (dev->name, reg); - udelay (1000); - } -#endif /* defined(CONFIG_PHY_RESET) */ - - miiphy_read (dev->name, reg, MII_BMSR, ®_short); - - /* - * Wait if PHY is capable of autonegotiation and autonegotiation is not complete - */ - if ((reg_short & BMSR_ANEGCAPABLE) - && !(reg_short & BMSR_ANEGCOMPLETE)) { - puts ("Waiting for PHY auto negotiation to complete"); - i = 0; - while (!(reg_short & BMSR_ANEGCOMPLETE)) { - /* - * Timeout reached ? - */ - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); - break; - } - - if ((i++ % 1000) == 0) { - putc ('.'); - } - udelay (1000); /* 1 ms */ - miiphy_read (dev->name, reg, MII_BMSR, ®_short); - - } - puts (" done\n"); - udelay (500000); /* another 500 ms (results in faster booting) */ - } - - speed = miiphy_speed (dev->name, reg); - duplex = miiphy_duplex (dev->name, reg); - - printf ("ENET Speed is %d Mbps - %s duplex connection\n", - (int) speed, (duplex == HALF) ? "HALF" : "FULL"); - - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - -static int mv64460_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64460_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64460_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64460_eth_stop (struct eth_device *dev) -{ - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64460_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64460_eth_stop */ - -static int mv64460_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - mv64460_eth_free_tx_rings (dev); - mv64460_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64460_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - -/********************************************************************** - * mv64460_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - pkt_info.return_info = 0; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - return 1; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - return 0; /* success */ -} - -/********************************************************************** - * mv64460_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64460_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) { -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - if(pkt_info.buf_ptr != 0){ - for(i=0; i < pkt_info.byte_cnt; i++){ - if((i % 4) == 0){ - printf("\n0x"); - } - printf("%02x", ((char*)pkt_info.buf_ptr)[i]); - } - printf("\n"); - } - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf ("RX: pkt_info.buf_ptr = %x\n", pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX: Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64460_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64460_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - - mv64460_eth_update_stat (dev); - - return port_private->stats; -} - -/********************************************************************** - * mv64460_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - (void)eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - (void)eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64460_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64460_eth_start (struct eth_device *dev) -{ - return (mv64460_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - } else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) { - (void)MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); - } - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/***********************************************************/ -/* (Re)start autonegotiation */ -/***********************************************************/ -int phy_setup_aneg (char *devname, unsigned char addr) -{ - unsigned short ctl, adv; - - /* Setup standard advertise */ - miiphy_read (devname, addr, MII_ADVERTISE, &adv); - adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | - LPA_100FULL | LPA_100HALF | LPA_10FULL | - LPA_10HALF); - miiphy_write (devname, addr, MII_ADVERTISE, adv); - - miiphy_read (devname, addr, MII_CTRL1000, &adv); - adv |= (0x0300); - miiphy_write (devname, addr, MII_CTRL1000, adv); - - /* Start/Restart aneg */ - miiphy_read (devname, addr, MII_BMCR, &ctl); - ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); - miiphy_write (devname, addr, MII_BMCR, ctl); - - return 0; -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * - *******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - eth_port_read_smi_reg (eth_port_num, 20, &phy_reg_data); - phy_reg_data |= 0x0083; /* Set bit 7 to 1 for different RGMII timing */ - eth_port_write_smi_reg (eth_port_num, 20, phy_reg_data); - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -int mv_miiphy_read(const char *devname, unsigned char phy_addr, - unsigned char phy_reg, unsigned short *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return 0; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -int mv_miiphy_write(const char *devname, unsigned char phy_addr, - unsigned char phy_reg, unsigned short value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return 0; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/prodrive/p3mx/mv_eth.h b/board/prodrive/p3mx/mv_eth.h deleted file mode 100644 index fbda0daa12..0000000000 --- a/board/prodrive/p3mx/mv_eth.h +++ /dev/null @@ -1,815 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64460_ETH_H__ -#define __DB64460_ETH_H__ - -#include -#include -#include -#include -#include -#include "mv_regs.h" -#include -#include "../../Marvell/include/core.h" - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64460_TX_QUEUE_NUM 1 -#define MV64460_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE -#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE -#else -#define MV64460_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE -#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE -#else -#define MV64460_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64460_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64460_TX_BUFFER_SIZE 1600 -#endif - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64460_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - - /* to buffer area aligned */ - char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - - int first_init; -}; - -int mv64460_eth_init (struct eth_device *dev); -int mv64460_eth_stop (struct eth_device *dev); -int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length); -int mv64460_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64460_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64460_ETH_ */ diff --git a/board/prodrive/p3mx/mv_regs.h b/board/prodrive/p3mx/mv_regs.h deleted file mode 100644 index becd42116c..0000000000 --- a/board/prodrive/p3mx/mv_regs.h +++ /dev/null @@ -1,1109 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** -* gt64460r.h - GT-64460 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64460 - -/* Supported by the Atlantis */ -#define MV64460_INCLUDE_PCI_1 -#define MV64460_INCLUDE_PCI_0_ARBITER -#define MV64460_INCLUDE_PCI_1_ARBITER -#define MV64460_INCLUDE_SNOOP_SUPPORT -#define MV64460_INCLUDE_P2P -#define MV64460_INCLUDE_ETH_PORT_2 -#define MV64460_INCLUDE_CPU_MAPPING -#define MV64460_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64460_CS_0_BASE_ADDR 0x008 -#define MV64460_CS_0_SIZE 0x010 -#define MV64460_CS_1_BASE_ADDR 0x208 -#define MV64460_CS_1_SIZE 0x210 -#define MV64460_CS_2_BASE_ADDR 0x018 -#define MV64460_CS_2_SIZE 0x020 -#define MV64460_CS_3_BASE_ADDR 0x218 -#define MV64460_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64460_PCI_0_IO_BASE_ADDR 0x048 -#define MV64460_PCI_0_IO_SIZE 0x050 -#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64460_PCI_0_MEMORY0_SIZE 0x060 -#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64460_PCI_0_MEMORY1_SIZE 0x088 -#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64460_PCI_0_MEMORY2_SIZE 0x260 -#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64460_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64460_PCI_1_IO_BASE_ADDR 0x090 -#define MV64460_PCI_1_IO_SIZE 0x098 -#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64460_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64460_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64460_CPU_CONFIG 0x000 -#define MV64460_CPU_MODE 0x120 -#define MV64460_CPU_MASTER_CONTROL 0x160 -#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64460_SMP_WHO_AM_I 0x200 -#define MV64460_SMP_CPU0_DOORBELL 0x214 -#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64460_SMP_CPU1_DOORBELL 0x224 -#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64460_SMP_SEMAPHOR0 0x244 -#define MV64460_SMP_SEMAPHOR1 0x24c -#define MV64460_SMP_SEMAPHOR2 0x254 -#define MV64460_SMP_SEMAPHOR3 0x25c -#define MV64460_SMP_SEMAPHOR4 0x264 -#define MV64460_SMP_SEMAPHOR5 0x26c -#define MV64460_SMP_SEMAPHOR6 0x274 -#define MV64460_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64460_CPU_ERROR_ADDR_LOW 0x070 -#define MV64460_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64460_CPU_ERROR_DATA_LOW 0x128 -#define MV64460_CPU_ERROR_DATA_HIGH 0x130 -#define MV64460_CPU_ERROR_PARITY 0x138 -#define MV64460_CPU_ERROR_CAUSE 0x140 -#define MV64460_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64460_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64460_SRAM_CONFIG 0x380 -#define MV64460_SRAM_TEST_MODE 0X3F4 -#define MV64460_SRAM_ERROR_CAUSE 0x388 -#define MV64460_SRAM_ERROR_ADDR 0x390 -#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64460_SRAM_ERROR_DATA_LOW 0x398 -#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64460_SDRAM_CONFIG 0x1400 -#define MV64460_D_UNIT_CONTROL_LOW 0x1404 -#define MV64460_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64460_D_UNIT_MMASK 0x14B0 -#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64460_SDRAM_ADDR_CONTROL 0x1410 -#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64460_SDRAM_OPERATION 0x1418 -#define MV64460_SDRAM_MODE 0x141c -#define MV64460_EXTENDED_DRAM_MODE 0x1420 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64460_SDRAM_ERROR_ADDR 0x1450 -#define MV64460_SDRAM_RECEIVED_ECC 0x1448 -#define MV64460_SDRAM_CALCULATED_ECC 0x144c -#define MV64460_SDRAM_ECC_CONTROL 0x1454 -#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64460_DFCDL_CONFIG0 0x1480 -#define MV64460_DFCDL_CONFIG1 0x1484 -#define MV64460_DLL_WRITE 0x1488 -#define MV64460_DLL_READ 0x148c -#define MV64460_SRAM_ADDR 0x1490 -#define MV64460_SRAM_DATA0 0x1494 -#define MV64460_SRAM_DATA1 0x1498 -#define MV64460_SRAM_DATA2 0x149c -#define MV64460_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64460_DUNIT_DEBUG_LOW 0x1460 -#define MV64460_DUNIT_DEBUG_HIGH 0x1464 -#define MV64460_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64460_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64460_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64460_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64460_DEVICE_ERROR_ADDR 0x4d8 -#define MV64460_DEVICE_ERROR_DATA 0x4dc -#define MV64460_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64460_DEVICE_DEBUG_LOW 0x4e4 -#define MV64460_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64460_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64460_PCI_0_COMMAND 0xc00 -#define MV64460_PCI_1_COMMAND 0xc80 -#define MV64460_PCI_0_MODE 0xd00 -#define MV64460_PCI_1_MODE 0xd80 -#define MV64460_PCI_0_RETRY 0xc04 -#define MV64460_PCI_1_RETRY 0xc84 -#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64460_PCI_0_P2P_CONFIG 0x1d14 -#define MV64460_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64460_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64460_PCI_1_CONFIG_ADDR 0xc78 -#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64460_PCI_0_SERR_MASK 0xc28 -#define MV64460_PCI_1_SERR_MASK 0xca8 -#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64460_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64460_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64460_PCI_0_ERROR_MASK 0x1d5c -#define MV64460_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64460_PCI_0_MMASK 0X1D24 -#define MV64460_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64460_PCI_STATUS_AND_COMMAND 0x004 -#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64460_PCI_VPD_ADDR 0x048 -#define MV64460_PCI_VPD_DATA 0x04c -#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64460_PCI_X_COMMAND 0x060 -#define MV64460_PCI_X_STATUS 0x064 -#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64460_ETH_PHY_ADDR_REG 0x2000 -#define MV64460_ETH_SMI_REG 0x2004 -#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64460_ETH_BAR_0 0x2200 -#define MV64460_ETH_BAR_1 0x2208 -#define MV64460_ETH_BAR_2 0x2210 -#define MV64460_ETH_BAR_3 0x2218 -#define MV64460_ETH_BAR_4 0x2220 -#define MV64460_ETH_BAR_5 0x2228 -#define MV64460_ETH_SIZE_REG_0 0x2204 -#define MV64460_ETH_SIZE_REG_1 0x220c -#define MV64460_ETH_SIZE_REG_2 0x2214 -#define MV64460_ETH_SIZE_REG_3 0x221c -#define MV64460_ETH_SIZE_REG_4 0x2224 -#define MV64460_ETH_SIZE_REG_5 0x222c -#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64460_CUNIT_SIZE0 0xf204 -#define MV64460_CUNIT_SIZE1 0xf20c -#define MV64460_CUNIT_SIZE2 0xf214 -#define MV64460_CUNIT_SIZE3 0xf21c -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64460_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64460_CUNIT_CONFIG_REG 0xb40c -#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64460_CUNIT_DEBUG_LOW 0xf340 -#define MV64460_CUNIT_DEBUG_HIGH 0xf344 -#define MV64460_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64460_MPSC_ROUTING_REG 0xb400 -#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64460_SDMA_CAUSE_REG 0xb800 -#define MV64460_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64460_SDMA_SRAM_TARGET 0x0003 -#define MV64460_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64460_PCI_0_TARGET 0x0003 -#define MV64460_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64460_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64460_BRG_CAUSE_REG 0xb834 -#define MV64460_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_CONTROL 0x840 -#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64460_DMA_CHANNEL1_CONTROL 0x844 -#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64460_DMA_CHANNEL2_CONTROL 0x848 -#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64460_DMA_CHANNEL3_CONTROL 0x84C -#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64460_DMA_BASE_ADDR_REG0 0xa00 -#define MV64460_DMA_BASE_ADDR_REG1 0xa08 -#define MV64460_DMA_BASE_ADDR_REG2 0xa10 -#define MV64460_DMA_BASE_ADDR_REG3 0xa18 -#define MV64460_DMA_BASE_ADDR_REG4 0xa20 -#define MV64460_DMA_BASE_ADDR_REG5 0xa28 -#define MV64460_DMA_BASE_ADDR_REG6 0xa30 -#define MV64460_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64460_DMA_SIZE_REG0 0xa04 -#define MV64460_DMA_SIZE_REG1 0xa0c -#define MV64460_DMA_SIZE_REG2 0xa14 -#define MV64460_DMA_SIZE_REG3 0xa1c -#define MV64460_DMA_SIZE_REG4 0xa24 -#define MV64460_DMA_SIZE_REG5 0xa2c -#define MV64460_DMA_SIZE_REG6 0xa34 -#define MV64460_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64460_DMA_ARBITER_CONTROL 0x860 -#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64460_DMA_ERROR_ADDR 0x8c8 -#define MV64460_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64460_DMA_DEBUG_LOW 0x8e0 -#define MV64460_DMA_DEBUG_HIGH 0x8e4 -#define MV64460_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64460_TIMER_COUNTER0 0x850 -#define MV64460_TIMER_COUNTER1 0x854 -#define MV64460_TIMER_COUNTER2 0x858 -#define MV64460_TIMER_COUNTER3 0x85C -#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64460_WATCHDOG_CONFIG_REG 0xb410 -#define MV64460_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64460_I2C_SLAVE_ADDR 0xc000 -#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64460_I2C_DATA 0xc004 -#define MV64460_I2C_CONTROL 0xc008 -#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64460_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64460_GPP_IO_CONTROL 0xf100 -#define MV64460_GPP_LEVEL_CONTROL 0xf110 -#define MV64460_GPP_VALUE 0xf104 -#define MV64460_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64460_GPP_INTERRUPT_MASK0 0xf10c -#define MV64460_GPP_INTERRUPT_MASK1 0xf114 -#define MV64460_GPP_VALUE_SET 0xf118 -#define MV64460_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64460_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64460_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64460_MPP_CONTROL0 0xf000 -#define MV64460_MPP_CONTROL1 0xf004 -#define MV64460_MPP_CONTROL2 0xf008 -#define MV64460_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64460_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64460_SERIAL_INIT_CONTROL 0xf328 -#define MV64460_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64460rh */ diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c deleted file mode 100644 index 28c4ebad97..0000000000 --- a/board/prodrive/p3mx/p3mx.c +++ /dev/null @@ -1,838 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on original work by - * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. - * Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com - * modifications for the cpci750 by reinhard.arlt@esd-electronics.com - * modifications for the P3M750 by roel.loeffen@prodrive.nl - */ - -/* - * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448. - */ - -#include -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include -#include - -#include "eth.h" -#include "mpsc.h" -#include "64460.h" -#include "mv_regs.h" -#include "p3mx.h" - -DECLARE_GLOBAL_DATA_PTR; - -#undef DEBUG -/*#define DEBUG */ - -#ifdef CONFIG_PCI -#define MAP_PCI -#endif /* of CONFIG_PCI */ - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -extern flash_info_t flash_info[]; - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; -int display_mem_map (void); -void set_led(int); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, */ - /* FuncNum 10:8, RegNum 7:2 */ - - /* - * In PCIX mode devices provide their own bus and device numbers. - * We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the - * bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | - (1 << 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen: - * add write to pci remap registers for 64460. - * in 64360 when writing to pci base go and overide remap automaticaly, - * in 64460 it doesn't - */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - - /* ronen: - * update the pci internal registers base address. - */ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CONFIG_SYS_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - /* set the SINGLE_CPU bit see MV64460 */ -#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - tmp &= ~CPU_CONF_AACK_DELAY_2; - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - tmp |= CPU_CONF_PIPELINE; - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - /* set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in >MV6436x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - - /* Device and Boot bus settings - */ - memoryMapDeviceSpace(DEVICE0, 0, 0); - GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0); - memoryMapDeviceSpace(DEVICE1, 0, 0); - GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0); - memoryMapDeviceSpace(DEVICE2, 0, 0); - GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0); - memoryMapDeviceSpace(DEVICE3, 0, 0); - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0); - - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR); - - gt_cpu_config(); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - - set_led(LED_RED); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - u8 val; - - icache_enable (); -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - mpsc_sdma_init (); - mpsc_init2 (); -#endif - - /* - * Enable trickle changing in RTC upon powerup - * No diode, 250 ohm series resistor - */ - val = 0xa5; - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1); - - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE); - -/* display_mem_map(); */ - - /* now, jump to the main U-Boot board init code */ - set_led(LED_GREEN); - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* - * Check Board Identity: - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: %s", CONFIG_SYS_BOARD_NAME); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -void set_led(int col) -{ - int tmp; - int on_pin; - int off_pin; - - /* Program Mpp[22] as Gpp[22] - * Program Mpp[23] as Gpp[23] - */ - tmp = GTREGREAD(MPP_CONTROL2); - tmp &= 0x00ffffff; - GT_REG_WRITE(MPP_CONTROL2,tmp); - - /* Program Gpp[22] and Gpp[23] as output - */ - tmp = GTREGREAD(GPP_IO_CONTROL); - tmp |= 0x00C00000; - GT_REG_WRITE(GPP_IO_CONTROL, tmp); - - /* Program Gpp[22] and Gpp[23] as active high - */ - tmp = GTREGREAD(GPP_LEVEL_CONTROL); - tmp &= 0xff3fffff; - GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp); - - switch(col) { - default: - case LED_OFF : - on_pin = 0; - off_pin = ((1 << 23) | (1 << 22)); - break; - case LED_RED : - on_pin = (1 << 23); - off_pin = (1 << 22); - break; - case LED_GREEN : - on_pin = (1 << 22); - off_pin = (1 << 23); - break; - case LED_ORANGE : - on_pin = ((1 << 23) | (1 << 22)); - off_pin = 0; - break; - } - - /* Set output Gpp[22] and Gpp[23] - */ - tmp = GTREGREAD(GPP_VALUE); - tmp |= on_pin; - tmp &= ~off_pin; - GT_REG_WRITE(GPP_VALUE, tmp); -} - -int display_mem_map (void) -{ - int i; - unsigned int base, size, width; -#ifdef CONFIG_PCI - int j; -#endif - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } -#ifdef CONFIG_PCI - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - /* ronen currently only first PCI MEM is used 3 */ - for (j = 0; j <= PCI_REGION0; j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", - j, base, size >> 20); - } - } -#endif /* of CONFIG_PCI */ - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n", - base, size >> 20, width); - - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CONFIG_SYS_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; - const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) - pmem[i] = i; - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; - const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata = 0; - int runaddress = 0; - int runwalk = 0; - -#ifdef CONFIG_SYS_DRAM_TEST_DATA - rundata = getenv_yesno("testdramdata") == 1; -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - runaddress = getenv_yesno("testdramaddress") == 1; -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - runwalk = getenv_yesno("testdramwalk") == 1; -#endif - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) - printf ("Testing RAM from 0x%08x to 0x%08x ... " - "(don't panic... that will take a moment !!!!)\n", - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) - printf ("passed\n"); - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -int board_eth_init(bd_t *bis) -{ - return mv6446x_eth_initialize(bis); -} diff --git a/board/prodrive/p3mx/p3mx.h b/board/prodrive/p3mx/p3mx.h deleted file mode 100644 index e6518cb592..0000000000 --- a/board/prodrive/p3mx/p3mx.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2005 - * - * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. roel.loeffen@prodrive.nl - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __P3MX_H__ -#define __P3MX_H__ - -#define LED_OFF 1 -#define LED_GREEN 2 -#define LED_RED 3 -#define LED_ORANGE 4 - -#endif /* __P3MX_H__ */ diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c deleted file mode 100644 index 56cdfc2959..0000000000 --- a/board/prodrive/p3mx/pci.c +++ /dev/null @@ -1,1003 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PCI.c - PCI functions */ - - -#include -#ifdef CONFIG_PCI -#include - -#include "../../Marvell/include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - -#ifdef CONFIG_USE_CPCIDVI -typedef struct { - unsigned int base; - unsigned int init; -} GT_CPCIDVI_ROM_T; - -static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; -#endif - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 MHz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 MHz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 MHz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - -#ifdef CONFIG_USE_CPCIDVI -static void gt_setup_cpcidvi (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - u32 bar_value, pci_response; - - pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); - pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); - pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value); - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00)); - pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0); - pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value); - pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01); - gt_cpcidvi_rom.base = bar_value & 0xffffff00; - gt_cpcidvi_rom.init = 1; -} - -unsigned char gt_cpcidvi_in8(unsigned int offset) -{ - unsigned char data; - - if (gt_cpcidvi_rom.init == 0) { - return(0); - } - data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); - return(data); -} - -void gt_cpcidvi_out8(unsigned int offset, unsigned char data) -{ - unsigned int off; - - if (gt_cpcidvi_rom.init == 0) { - return; - } - off = data; - off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; - in8(off); - return; -} -#endif - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { -#ifdef CONFIG_USE_CPCIDVI - {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi}, -#endif - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; -#ifdef CONFIG_PCI_PNP - unsigned int bar; -#endif -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif -#ifdef CONFIG_USE_CPCIDVI - gt_cpcidvi_rom.init = 0; - gt_cpcidvi_rom.base = 0; -#endif - - pci0_hose.config_table = gt_config_table; - pci1_hose.config_table = gt_config_table; - -#ifdef CONFIG_USE_CPCIDVI - gt_config_table[0].config_device = gt_setup_cpcidvi; -#endif - gt_config_table[1].config_device = gt_setup_ide; - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */ - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci0_hose); - pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); -#endif -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci1_hose); - pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar); -#endif - pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} -#endif /* of CONFIG_PCI */ diff --git a/board/prodrive/p3mx/ppc_error_no.h b/board/prodrive/p3mx/ppc_error_no.h deleted file mode 100644 index 58a68b5d89..0000000000 --- a/board/prodrive/p3mx/ppc_error_no.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus - */ -#ifndef _MV_PPC_ERRNO_H -#define _MV_PPC_ERRNO_H - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Arg list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ -#define EDEADLOCK 58 /* File locking deadlock error */ -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ - -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - -/* Should never be seen by user programs */ -#define ERESTARTSYS 512 -#define ERESTARTNOINTR 513 -#define ERESTARTNOHAND 514 /* restart if no handler.. */ -#define ENOIOCTLCMD 515 /* No ioctl command */ - -#define _LAST_ERRNO 515 - -#endif diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c deleted file mode 100644 index 4a42fa3546..0000000000 --- a/board/prodrive/p3mx/sdram_init.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * adaption for the Marvell DB64460 Board - * Ingo Assmus (ingo.assmus@keymile.com) - *************************************************************************/ - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "../../Marvell/common/i2c.h" -#include "64460.h" -#include "mv_regs.h" - -DECLARE_GLOBAL_DATA_PTR; - -#undef DEBUG -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -int set_dfcdlInit (void); /* setup delay line of Mv64460 */ -int mvDmaIsChannelActive (int); -int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); -int mvDmaTransfer (int, ulong, ulong, ulong, ulong); - -#define D_CACHE_FLUSH_LINE(addr, offset) \ - { \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ - } - -int memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#if defined (MAP_PCI) && defined (CONFIG_PCI) - PCI_HOST host; -#endif - -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - -#if defined (MAP_PCI) && defined (CONFIG_PCI) - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } -#endif - - return 0; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - DP (printf - ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - - return maxsize; -} - -#define SDRAM_NORMAL 0x0 -#define SDRAM_PRECHARGE_ALL 0x1 -#define SDRAM_REFRESH_ALL 0x2 -#define SDRAM_MODE_REG_SETUP 0x3 -#define SDRAM_XTEN_MODE_REG_SETUP 0x4 -#define SDRAM_NOP 0x5 -#define SDRAM_SELF_REFRESH 0x7 - -phys_size_t initdram (int board_type) -{ - int tmp; - int start; - ulong size; - ulong memSpaceAttr; - ulong dest; - - /* first disable all banks */ - memory_map_bank(0, 0, 0); - memory_map_bank(1, 0, 0); - memory_map_bank(2, 0, 0); - memory_map_bank(3, 0, 0); - - /* calibrate delay lines */ - set_dfcdlInit(); - - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* SDRAM controller configuration */ -#ifdef CONFIG_MV64460_ECC - GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58201400); /* 0x1400 */ -#else - GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58200400); /* 0x1400 */ -#endif - GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW, 0xC3000540); /* 0x1404 */ - GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH, 0x0300F777); /* 0x1424 */ - GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW, 0x01712220); /* 0x1408 */ - GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D); /* 0x140C */ - GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL, 0x00000012); /* 0x1410 */ - GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL, 0x00000001); /* 0x1414 */ - - /* SDRAM drive strength */ - GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */ - GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */ - GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000); /* 0x14C4 */ - GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008); /* 0x14C4 */ - - /* setup SDRAM device registers */ - - /* precharge all */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* enable DLL */ - GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000); /* 0x1420 */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* reset DLL */ - GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132); /* 0x141C */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* precharge all */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* wait for 2 auto refresh commands */ - udelay(20); - - /* un-reset DLL */ - GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032); /* 0x141C */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* wait 200 cycles */ - udelay(2); /* FIXME make this dynamic for the system clock */ - - /* SDRAM init done */ - memory_map_bank(0, CONFIG_SYS_SDRAM_BASE, (256 << 20)); -#ifdef CONFIG_SYS_SDRAM1_BASE - memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20)); -#endif - - /* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4 - */ - tmp = GTREGREAD(MV64460_D_UNIT_MMASK); /* 0x14B0 */ - GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2); - - start = (0 << 20); -#ifdef CONFIG_P3M750 - size = (512 << 20); -#elif defined (CONFIG_P3M7448) - size = (128 << 20); -#endif - -#ifdef CONFIG_MV64460_ECC - memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8; - mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size); - for (dest = start; dest < start + size; dest += _8M) { - mvDmaTransfer (0, start, dest, _8M, - BIT8 /*DMA_DTL_128BYTES */ | - BIT3 /*DMA_HOLD_SOURCE_ADDR */ | - BIT11 /*DMA_BLOCK_TRANSFER_MODE */ ); - while (mvDmaIsChannelActive (0)); - } -#endif - - return (size); -} - -void board_add_ram_info(int use_default) -{ - u32 val; - - puts(" (CL="); - switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) { - case 0x2: - puts("2"); - break; - case 0x3: - puts("3"); - break; - case 0x5: - puts("1.5"); - break; - case 0x6: - puts("2.5"); - break; - } - - val = GTREGREAD(MV64460_SDRAM_CONFIG); - - puts(", ECC "); - if (val & 0x00001000) - puts("enabled)"); - else - puts("not enabled)"); -} - -/* - * mvDmaIsChannelActive - Check if IDMA channel is active - * - * channel = IDMA channel number from 0 to 7 - */ -int mvDmaIsChannelActive (int channel) -{ - ulong data; - - data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel); - if (data & BIT14) /* activity status */ - return 1; - - return 0; -} - -/* - * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding - * map. - * - * memSpace = IDMA memory window number from 0 to 7 - * trg_if = Target interface: - * 0x0 DRAM - * 0x1 Device Bus - * 0x2 Integrated SDRAM (or CPU bus 60x only) - * 0x3 PCI0 - * 0x4 PCI1 - * attr = IDMA attributes (see MV datasheet) - * base_addr = Sets up memory window for transfers - * - */ -int mvDmaSetMemorySpace (ulong memSpace, - ulong trg_if, - ulong attr, ulong base_addr, ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (base_addr % size != 0) - return 0; - - if (size >= 0x10000) { /* 64K */ - size &= 0xffff0000; - base_addr = (base_addr & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8, - (base_addr | trg_if | attr)); - GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << memSpace))); - return 1; - } - - return 0; -} - -/* - * mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4 - * DMA channels. - * - * channel = IDMA channel number from 0 to 3 - * destAddr = Destination address - * sourceAddr = Source address - * size = Size in bytes - * command = See MV datasheet - * - */ -int mvDmaTransfer (int channel, ulong sourceAddr, - ulong destAddr, ulong size, ulong command) -{ - ulong engOffReg = 0; /* Engine Offset Register */ - - if (size > 0xffff) - command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */ - command = command | ((command >> 6) & 0x7); - engOffReg = channel * 4; - GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr); - command = command | - BIT12 | /* DMA_CHANNEL_ENABLE */ - BIT9; /* DMA_NON_CHAIN_MODE */ - /* Activate DMA channel By writting to mvDmaControlRegister */ - GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command); - return 1; -} - -/**************************************************************************************** - * SDRAM INIT * - * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * - * This procedure fits only the Atlantis * - * * - ***************************************************************************************/ - -/**************************************************************************************** - * DFCDL initialize MV643xx Design Considerations * - * * - ***************************************************************************************/ -int set_dfcdlInit (void) -{ - int i; - - /* Values from MV64460 User Manual */ - unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083, - 0x000000c4, 0x00000105, 0x00000146, 0x00000187, - 0x000001c8, 0x00000209, 0x0000024a, 0x0000028b, - 0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f, - 0x000003d0, 0x00000411, 0x00000452, 0x00000493, - 0x000004d4, 0x00000515, 0x00000556, 0x00000597, - 0x000005d8, 0x00000619, 0x0000065a, 0x0000069b, - 0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f, - 0x000007e0, 0x00000821, 0x00000862, 0x000008a3, - 0x000008e4, 0x00000925, 0x00000966, 0x000009a7, - 0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab, - 0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf, - 0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3, - 0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7, - 0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb, - 0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf }; - - for (i = 0; i < 64; i++) - GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]); - GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ - - return (0); -} diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c deleted file mode 100644 index 89040a899e..0000000000 --- a/board/prodrive/p3mx/serial.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * modified for cpci750 board by - * Reinhard Arlt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * serial.c - serial support for esd cpci750 board - */ - -/* supports the MPSC */ - -#include -#include -#include -#include - -#include "../../Marvell/include/memory.h" -#include "serial.h" - -#include "mpsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -static int p3mx_serial_init(void) -{ - mpsc_init (gd->baudrate); - - return (0); -} - -static void p3mx_serial_putc(const char c) -{ - if (c == '\n') - mpsc_putchar ('\r'); - - mpsc_putchar (c); -} - -static int p3mx_serial_getc(void) -{ - return mpsc_getchar (); -} - -static int p3mx_serial_tstc(void) -{ - return mpsc_test_char (); -} - -static void p3mx_serial_setbrg(void) -{ - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); -} - -static struct serial_device p3mx_serial_drv = { - .name = "p3mx_serial", - .start = p3mx_serial_init, - .stop = NULL, - .setbrg = p3mx_serial_setbrg, - .putc = p3mx_serial_putc, - .puts = default_serial_puts, - .getc = p3mx_serial_getc, - .tstc = p3mx_serial_tstc, -}; - -void p3mx_serial_initialize(void) -{ - serial_register(&p3mx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &p3mx_serial_drv; -} - -#if defined(CONFIG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/prodrive/p3mx/serial.h b/board/prodrive/p3mx/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/prodrive/p3mx/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/prodrive/p3p440/Kconfig b/board/prodrive/p3p440/Kconfig new file mode 100644 index 0000000000..cf53aac57b --- /dev/null +++ b/board/prodrive/p3p440/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P3P440 + +config SYS_BOARD + default "p3p440" + +config SYS_VENDOR + default "prodrive" + +config SYS_CONFIG_NAME + default "p3p440" + +endif diff --git a/board/prodrive/p3p440/MAINTAINERS b/board/prodrive/p3p440/MAINTAINERS new file mode 100644 index 0000000000..68fd1a98a0 --- /dev/null +++ b/board/prodrive/p3p440/MAINTAINERS @@ -0,0 +1,6 @@ +P3P440 BOARD +M: Stefan Roese +S: Maintained +F: board/prodrive/p3p440/ +F: include/configs/p3p440.h +F: configs/p3p440_defconfig diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile index 1d80df8b74..d62f75d3e7 100644 --- a/board/prodrive/p3p440/Makefile +++ b/board/prodrive/p3p440/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = p3p440.o +extra-y += init.o diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S index 8f4c1cc01e..35b1afab85 100644 --- a/board/prodrive/p3p440/init.S +++ b/board/prodrive/p3p440/init.S @@ -4,7 +4,7 @@ * * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index bcbc179460..929e8eb1a5 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -4,7 +4,7 @@ * * Copyright (C) 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h index 9375688286..a164f95feb 100644 --- a/board/prodrive/p3p440/p3p440.h +++ b/board/prodrive/p3p440/p3p440.h @@ -2,7 +2,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __P3P440_H__ diff --git a/board/prodrive/pdnb3/Makefile b/board/prodrive/pdnb3/Makefile deleted file mode 100644 index 5e4a909589..0000000000 --- a/board/prodrive/pdnb3/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := flash.o pdnb3.o nand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c deleted file mode 100644 index 75b5d0544a..0000000000 --- a/board/prodrive/pdnb3/flash.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#if !defined(CONFIG_FLASH_CFI_DRIVER) - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/* - * Prototypes - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); - -static inline ulong ld(ulong x) -{ - ulong k = 0; - - while (x >>= 1) - ++k; - - return k; -} - -unsigned long flash_init(void) -{ - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i - -#if defined(CONFIG_CMD_NAND) - -#include - -struct pdnb3_ndfc_regs { - uchar cmd; - uchar wait; - uchar addr; - uchar term; - uchar data; -}; - -static u8 hwctl; -static struct pdnb3_ndfc_regs *pdnb3_ndfc; - -#define readb(addr) *(volatile u_char *)(addr) -#define readl(addr) *(volatile u_long *)(addr) -#define writeb(d,addr) *(volatile u_char *)(addr) = (d) - -/* - * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to - * the NAND devices. The NDFC has command, address and data registers that - * when accessed will set up the NAND flash pins appropriately. We'll use the - * hwcontrol function to save the configuration in a global variable. - * We can then use this information in the read and write functions to - * determine which NDFC register to access. - * - * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte). - */ -static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - if ( (ctrl & NAND_NCE) != NAND_NCE) - writeb(0x00, &(pdnb3_ndfc->term)); - } - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - - -static u_char pdnb3_nand_read_byte(struct mtd_info *mtd) -{ - return readb(&(pdnb3_ndfc->data)); -} - -static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - if (hwctl & 0x1) - writeb(buf[i], &(pdnb3_ndfc->cmd)); - else if (hwctl & 0x2) - writeb(buf[i], &(pdnb3_ndfc->addr)); - else - writeb(buf[i], &(pdnb3_ndfc->data)); - } -} - -static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - buf[i] = readb(&(pdnb3_ndfc->data)); -} - -static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - if (buf[i] != readb(&(pdnb3_ndfc->data))) - return i; - - return 0; -} - -static int pdnb3_nand_dev_ready(struct mtd_info *mtd) -{ - /* - * Blocking read to wait for NAND to be ready - */ - readb(&(pdnb3_ndfc->wait)); - - /* - * Return always true - */ - return 1; -} - -int board_nand_init(struct nand_chip *nand) -{ - pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE; - - nand->ecc.mode = NAND_ECC_SOFT; - - /* Set address of NAND IO lines (Using Linear Data Access Region) */ - nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); - nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); - /* Reference hardware control function */ - nand->cmd_ctrl = pdnb3_nand_hwcontrol; - nand->read_byte = pdnb3_nand_read_byte; - nand->write_buf = pdnb3_nand_write_buf; - nand->read_buf = pdnb3_nand_read_buf; - nand->verify_buf = pdnb3_nand_verify_buf; - nand->dev_ready = pdnb3_nand_dev_ready; - return 0; -} -#endif diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c deleted file mode 100644 index fa320da2d4..0000000000 --- a/board/prodrive/pdnb3/pdnb3.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* predefine these here for FPGA programming (before including fpga.c) */ -#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data) -#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE) -#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT) -#define OLD_VAL old_val - -static unsigned long old_val = 0; - -/* - * include common fpga code (for prodrive boards) - */ -#include "../common/fpga.c" - -/* - * Miscelaneous platform dependent initialisations - */ -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET); - - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING); - - /* - * Setup GPIO's for FPGA programming - */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE); - - /* - * Setup GPIO's for interrupts - */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT); - - /* - * Setup GPIO's for 33MHz clock output - */ - *IXP425_GPIO_GPCLKR = 0x01FF0000; - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M); - - /* - * Setup other chip select's - */ - *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1; - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: PDNB3"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -int do_fpga_boot(unsigned char *fpgadata) -{ - unsigned char *dst; - int status; - int index; - int i; - ulong len = CONFIG_SYS_MALLOC_LEN; - - /* - * Setup GPIO's for FPGA programming - */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); - - /* - * Save value so no readback is required upon programming - */ - old_val = *IXP425_GPIO_GPOUTR; - - /* - * First try to decompress fpga image (gzip compressed?) - */ - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf("Error: Image has to be gzipp'ed!\n"); - return -1; - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=5; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc('\n'); - - free(dst); - - /* - * Reset FPGA - */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET); - udelay(10); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); - - return (0); -} - -int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - - if (argc < 2) - return cmd_usage(cmdtp); - - addr = simple_strtoul(argv[1], NULL, 16); - - return do_fpga_boot((unsigned char *)addr); -} - -U_BOOT_CMD( - fpga, 2, 0, do_fpga, - "boot FPGA", - "address size\n - boot FPGA with gzipped image at
" -); - -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) -extern struct pci_controller hose; -extern void pci_ixp_init(struct pci_controller * hose); - -void pci_init_board(void) -{ - extern void pci_ixp_init (struct pci_controller *hose); - - pci_ixp_init(&hose); -} -#endif diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c deleted file mode 100644 index 409a7a82fb..0000000000 --- a/board/psyent/common/AMDLV065D.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#if defined(CONFIG_NIOS) -#include -#else -#include -#endif - -#define SECTSZ (64 * 1024) -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------*/ -unsigned long flash_init (void) -{ - int i; - unsigned long addr; - flash_info_t *fli = &flash_info[0]; - - fli->size = CONFIG_SYS_FLASH_SIZE; - fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - - addr = CONFIG_SYS_FLASH_BASE; - for (i = 0; i < fli->sector_count; ++i) { - fli->start[i] = addr; - addr += SECTSZ; - fli->protect[i] = 1; - } - - return (CONFIG_SYS_FLASH_SIZE); -} -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - int erased; - unsigned long *addr; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - erased = 1; - addr = (unsigned long *) info->start[i]; - for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) { - if ( readl(addr++) != (unsigned long)-1) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - unsigned char *addr = (unsigned char *) info->start[0]; - unsigned char *addr2; - int prot, sect; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (unsigned char *) info->start[sect]; - writeb (0xaa, addr); - writeb (0x55, addr); - writeb (0x80, addr); - writeb (0xaa, addr); - writeb (0x55, addr); - writeb (0x30, addr2); - /* Now just wait for 0xff & provide some user - * feedback while we wait. - */ - start = get_timer (0); - while ( readb (addr2) != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - } - } - printf ("\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - - vu_char *cmd = (vu_char *) info->start[0]; - vu_char *dst = (vu_char *) addr; - unsigned char b; - ulong start; - - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((readb (dst) & b) != b) { - printf ("%02x : %02x\n", readb (dst), b); - return (2); - } - - writeb (0xaa, cmd); - writeb (0x55, cmd); - writeb (0xa0, cmd); - writeb (dst, b); - - /* Verify write */ - start = get_timer (0); - while (readb (dst) != b) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - dst++; - src++; - cnt--; - } - - return (0); -} diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile deleted file mode 100644 index 68c18b95c7..0000000000 --- a/board/psyent/pci5441/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COMOBJS := ../common/AMDLV065D.o - -COBJS := $(BOARD).o $(COMOBJS) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk deleted file mode 100644 index 00ff743c96..0000000000 --- a/board/psyent/pci5441/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# (C) Copyright 2004, Psyent Corporation -# Scott McNutt -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0x018e0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/psyent/pci5441/pci5441.c b/board/psyent/pci5441/pci5441.c deleted file mode 100644 index 6d619e5128..0000000000 --- a/board/psyent/pci5441/pci5441.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Psyent PCI-5441\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (0); -} diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile deleted file mode 100644 index 0e704a5a5f..0000000000 --- a/board/psyent/pk1c20/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COMOBJS := ../common/AMDLV065D.o - -COBJS := $(BOARD).o led.o $(COMOBJS) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk deleted file mode 100644 index 7b0810a302..0000000000 --- a/board/psyent/pk1c20/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# (C) Copyright 2004, Psyent Corporation -# Scott McNutt -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0x01fc0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c deleted file mode 100644 index 639170f7fd..0000000000 --- a/board/psyent/pk1c20/led.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* The LED port is configured as output only, so we - * must track the state manually. - */ -static led_id_t val = 0; - -void __led_init (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_set (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_toggle (led_id_t mask) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - val ^= mask; - writel (val, &pio->data); -} diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c deleted file mode 100644 index 0b4c9f8ac1..0000000000 --- a/board/psyent/pk1c20/pk1c20.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Psyent PK-1C20\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/pxa255_idp/Kconfig b/board/pxa255_idp/Kconfig new file mode 100644 index 0000000000..544831199d --- /dev/null +++ b/board/pxa255_idp/Kconfig @@ -0,0 +1,9 @@ +if TARGET_PXA255_IDP + +config SYS_BOARD + default "pxa255_idp" + +config SYS_CONFIG_NAME + default "pxa255_idp" + +endif diff --git a/board/pxa255_idp/MAINTAINERS b/board/pxa255_idp/MAINTAINERS new file mode 100644 index 0000000000..24d723602c --- /dev/null +++ b/board/pxa255_idp/MAINTAINERS @@ -0,0 +1,6 @@ +PXA255_IDP BOARD +M: Cliff Brake +S: Maintained +F: board/pxa255_idp/ +F: include/configs/pxa255_idp.h +F: configs/pxa255_idp_defconfig diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile index a57165cccb..59d696741d 100644 --- a/board/pxa255_idp/Makefile +++ b/board/pxa255_idp/Makefile @@ -1,4 +1,3 @@ - # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -6,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := pxa_idp.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := pxa_idp.o diff --git a/board/qemu-malta/Makefile b/board/qemu-malta/Makefile deleted file mode 100644 index 70603414f4..0000000000 --- a/board/qemu-malta/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S deleted file mode 100644 index fa0b6a7d13..0000000000 --- a/board/qemu-malta/lowlevel_init.S +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2013 Gabor Juhos - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include - -#include -#include -#include - -#ifdef CONFIG_SYS_BIG_ENDIAN -#define CPU_TO_GT32(_x) ((_x)) -#else -#define CPU_TO_GT32(_x) ( \ - (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ - (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) -#endif - - .text - .set noreorder - .set mips32 - - .globl lowlevel_init -lowlevel_init: - - /* - * Load BAR registers of GT64120 as done by YAMON - * - * based on a patch sent by Antony Pavlov - * to the barebox mailing list. - * The subject of the original patch: - * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' - * URL: - * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html - * - * based on write_bootloader() in qemu.git/hw/mips_malta.c - * see GT64120 manual and qemu.git/hw/gt64xxx.c for details - */ - - /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - li t1, KSEG1ADDR(GT_DEF_BASE) - li t0, CPU_TO_GT32(0xdf000000) - sw t0, GT_ISD_OFS(t1) - - /* setup MEM-to-PCI0 mapping */ - li t1, KSEG1ADDR(MALTA_GT_BASE) - - /* setup PCI0 io window to 0x18000000-0x181fffff */ - li t0, CPU_TO_GT32(0xc0000000) - sw t0, GT_PCI0IOLD_OFS(t1) - li t0, CPU_TO_GT32(0x40000000) - sw t0, GT_PCI0IOHD_OFS(t1) - - /* setup PCI0 mem windows */ - li t0, CPU_TO_GT32(0x80000000) - sw t0, GT_PCI0M0LD_OFS(t1) - li t0, CPU_TO_GT32(0x3f000000) - sw t0, GT_PCI0M0HD_OFS(t1) - - li t0, CPU_TO_GT32(0xc1000000) - sw t0, GT_PCI0M1LD_OFS(t1) - li t0, CPU_TO_GT32(0x5e000000) - sw t0, GT_PCI0M1HD_OFS(t1) - - jr ra - nop diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c deleted file mode 100644 index 7eddf1ce66..0000000000 --- a/board/qemu-malta/qemu-malta.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2013 Gabor Juhos - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include - -#include -#include -#include -#include - -phys_size_t initdram(int board_type) -{ - return CONFIG_SYS_MEM_SIZE; -} - -int checkboard(void) -{ - puts("Board: MIPS Malta CoreLV (Qemu)\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -void _machine_restart(void) -{ - void __iomem *reset_base; - - reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); - __raw_writel(GORESET, reset_base); -} - -void pci_init_board(void) -{ - set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); - - gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), - 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, - 0x10000000, 0x10000000, 128 * 1024 * 1024, - 0x00000000, 0x00000000, 0x20000); -} diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig new file mode 100644 index 0000000000..18d78b5100 --- /dev/null +++ b/board/qemu-mips/Kconfig @@ -0,0 +1,10 @@ +if TARGET_QEMU_MIPS + +config SYS_BOARD + default "qemu-mips" + +config SYS_CONFIG_NAME + default "qemu-mips" if 32BIT + default "qemu-mips64" if 64BIT + +endif diff --git a/board/qemu-mips/MAINTAINERS b/board/qemu-mips/MAINTAINERS new file mode 100644 index 0000000000..334f9d8ee9 --- /dev/null +++ b/board/qemu-mips/MAINTAINERS @@ -0,0 +1,14 @@ +QEMU-MIPS BOARD +M: Vlad Lungu +S: Maintained +F: board/qemu-mips/ +F: include/configs/qemu-mips.h +F: configs/qemu_mips_defconfig + +QEMU_MIPSEL BOARD +#M: - +S: Maintained +F: configs/qemu_mipsel_defconfig +F: include/configs/qemu-mips64.h +F: configs/qemu_mips64_defconfig +F: configs/qemu_mips64el_defconfig diff --git a/board/qemu-mips/Makefile b/board/qemu-mips/Makefile index 70603414f4..8040573ff9 100644 --- a/board/qemu-mips/Makefile +++ b/board/qemu-mips/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = qemu-mips.o +obj-y += lowlevel_init.o diff --git a/board/quad100hd/Makefile b/board/quad100hd/Makefile deleted file mode 100644 index 9b936d06a8..0000000000 --- a/board/quad100hd/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o nand.o -SOBJS = - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c deleted file mode 100644 index 47bbb6b262..0000000000 --- a/board/quad100hd/nand.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2008 - * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#if defined(CONFIG_CMD_NAND) -#include -#include -#include - -/* - * hardware specific access to control-lines - */ -static void quad100hd_hwcontrol(struct mtd_info *mtd, - int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE)); - gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE)); - gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE)); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int quad100hd_nand_ready(struct mtd_info *mtd) -{ - return gpio_read_in_bit(CONFIG_SYS_NAND_RDY); -} - -/* - * Main initialization routine - */ -int board_nand_init(struct nand_chip *nand) -{ - /* Set address of hardware control function */ - nand->cmd_ctrl = quad100hd_hwcontrol; - nand->dev_ready = quad100hd_nand_ready; - nand->ecc.mode = NAND_ECC_SOFT; - /* 15 us command delay time */ - nand->chip_delay = 20; - - /* Return happy */ - return 0; -} -#endif /* CONFIG_CMD_NAND */ diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c deleted file mode 100644 index bb14ca7056..0000000000 --- a/board/quad100hd/quad100hd.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2008 - * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. - * - * Based in part on board/icecube/icecube.c from PPCBoot - * (C) Copyright 2003 Intrinsyc Software - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* taken from PPCBoot */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); - mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */ - mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - - mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */ - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); -#ifdef DISPLAY_BOARD_INFO - sys_info_t sysinfo; -#endif - - puts("Board: Quad100hd"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - -#ifdef DISPLAY_BOARD_INFO - /* taken from ppcboot */ - get_sys_info(&sysinfo); - - printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz); - printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); - printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); - printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); - printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv * - 1000000)); - printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000); -#endif - - return 0; -} diff --git a/board/quantum/Makefile b/board/quantum/Makefile deleted file mode 100644 index b7497a0d7c..0000000000 --- a/board/quantum/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o fpga.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c deleted file mode 100644 index 4bd391a546..0000000000 --- a/board/quantum/fpga.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* The DEBUG define must be before common to enable debugging */ -#undef DEBUG -#include -#include -#include -#include "fpga.h" -/* ------------------------------------------------------------------------- */ - -#define MAX_ONES 226 - -/* MPC850 port D */ -#define PD(bit) (1 << (15 - (bit))) -# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */ -# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */ -# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */ -# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */ -# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */ - - -/* DDR 0 - input, 1 - output */ -#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */ - - -#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data) -#define GET_FPGA immr->im_ioport.iop_pddat - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - - -int fpga_boot (unsigned char *fpgadata, int size) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int i, index, len; - int count; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - int j; - unsigned char data; -#else - unsigned char b; - int bit; -#endif - - debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size); - - /* display infos on fpgaimage */ - printf ("FPGA:"); - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf (" %s", &(fpgadata[index + 1])); - index += len + 3; - } - printf ("\n"); - - - index = 0; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - debug ("FPGA: configdata starts at position 0x%x\n", index); - debug ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ - immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR; - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA init line low */ - count = 0; - while (GET_FPGA & FPGA_INIT) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(GET_FPGA & FPGA_INIT)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - debug ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if ((i % 1024) == 0) - printf ("%6d out of %6d\r", i, size); /* let them know we are alive */ -#endif - - data = fpgadata[i]; - for (j = 0; j < 8; j++) { - if ((data & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - data <<= 1; - } - } - /* add some 0xff to the end of the file */ - for (i = 0; i < 8; i++) { - data = 0xff; - for (j = 0; j < 8; j++) { - if ((data & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - data <<= 1; - } - } -#else - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif - debug ("\n\n"); - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(GET_FPGA & FPGA_DONE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - debug ("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h deleted file mode 100644 index a9f4086297..0000000000 --- a/board/quantum/fpga.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the QUANTUM computer - */ -int fpga_boot(unsigned char *fpgadata, int size); - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c deleted file mode 100644 index 17e3fc2679..0000000000 --- a/board/quantum/quantum.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include "fpga.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -unsigned long flash_init (void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - * (Initialization code at 0x36) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board QUANTUM, Serial No: "); - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - putc ('\n'); - return (0); /* success */ -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size, - * 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - /* - * Final mapping: - */ - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - udelay (1000); - - return (size9); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ulong *addr; - ulong cnt, val, size; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = (volatile ulong *)(base + cnt); /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = (volatile ulong *)base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - /* Restore the original data before leaving the function. - */ - *addr = save[i]; - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - *addr = save[--i]; - } - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *)(base + cnt); /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - size = cnt * sizeof (long); - /* Restore the original data before returning - */ - for (cnt <<= 1; cnt <= maxsize / sizeof (long); - cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - *addr = save[--i]; - } - return (size); - } - } - return (maxsize); -} - -/* - * Miscellaneous intialization - */ -int misc_init_r (void) -{ - char *fpga_data_str = getenv ("fpgadata"); - char *fpga_size_str = getenv ("fpgasize"); - void *fpga_data; - int fpga_size; - int status; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int flash_size; - - /* Remap FLASH according to real size */ - flash_size = flash_init (); - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - if (fpga_data_str && fpga_size_str) { - fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16); - fpga_size = simple_strtoul (fpga_size_str, NULL, 10); - - status = fpga_boot (fpga_data, fpga_size); - if (status != 0) { - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - } - } - return 0; -} diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/quantum/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug deleted file mode 100644 index b2c562c33d..0000000000 --- a/board/quantum/u-boot.lds.debug +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile deleted file mode 100644 index 4720ac8132..0000000000 --- a/board/r360mpi/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/r360mpi/flash.c b/board/r360mpi/flash.c deleted file mode 100644 index 996a22e5a8..0000000000 --- a/board/r360mpi/flash.c +++ /dev/null @@ -1,468 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* #define DEBUG */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - FPW value; - - /* Make sure Block Lock Bits get cleared */ - addr[0] = (FPW) 0x00FF00FF; - addr[0] = (FPW) 0x00600060; - addr[0] = (FPW) 0x00D000D0; - addr[0] = (FPW) 0x00FF00FF; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - value = addr[0]; - - debug("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); - - switch (value) { - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), value); - - switch (value) { - case (FPW) INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - - int i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c deleted file mode 100644 index a939b31d47..0000000000 --- a/board/r360mpi/pcmcia.c +++ /dev/null @@ -1,232 +0,0 @@ -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "R360MPI" - -int pcmcia_hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CONFIG_SYS_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Ports A, B & C pins for - * 5 Volts Enable and 3 Volts enable - */ - immap->im_ioport.iop_pcpar &= ~(0x0400); - immap->im_ioport.iop_pcso &= ~(0x0400);/* - immap->im_ioport.iop_pcdir |= 0x0400;*/ - - immap->im_ioport.iop_papar &= ~(0x0200);/* - immap->im_ioport.iop_padir |= 0x0200;*/ -#if 0 - immap->im_ioport.iop_pbpar &= ~(0xC000); - immap->im_ioport.iop_pbdir &= ~(0xC000); -#endif - /* remove all power */ - - immap->im_ioport.iop_pcdat |= 0x0400; - immap->im_ioport.iop_padat |= 0x0200; - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { - immap->im_ioport.iop_pcdat &= ~(0x4000); - puts (" 5.0V card found: "); - } else { - immap->im_ioport.iop_padat &= ~(0x0002); - puts (" 3.3V card found: "); - } - immap->im_ioport.iop_pcdir |= 0x0400; - immap->im_ioport.iop_padir |= 0x0200; -#if 0 - /* VCC switch error flag, PCMCIA slot INPACK_ pin */ - cp->cp_pbdir &= ~(0x0020 | 0x0010); - cp->cp_pbpar &= ~(0x0020 | 0x0010); - udelay(500000); -#endif - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - volatile immap_t *immap; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CONFIG_SYS_IMMR; - - /* remove all power */ - immap->im_ioport.iop_pcdat |= 0x0400; - immap->im_ioport.iop_padat |= 0x0200; - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Ports A & C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn off all power - */ - debug ("PCMCIA power OFF\n"); - immap->im_ioport.iop_pcpar &= ~(0x0400); - immap->im_ioport.iop_pcso &= ~(0x0400);/* - immap->im_ioport.iop_pcdir |= 0x0400;*/ - - immap->im_ioport.iop_papar &= ~(0x0200);/* - immap->im_ioport.iop_padir |= 0x0200;*/ - - immap->im_ioport.iop_pcdat |= 0x0400; - immap->im_ioport.iop_padat |= 0x0200; - - reg = 0; - switch(vcc) { - case 0: break; - case 33: reg |= 0x0200; break; - case 50: reg |= 0x0400; break; - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - if (reg & 0x0200) - immap->im_ioport.iop_pcdat &= !reg; - if (reg & 0x0400) - immap->im_ioport.iop_padat &= !reg; - immap->im_ioport.iop_pcdir |= 0x0200; - immap->im_ioport.iop_padir |= 0x0400; - if (reg) { - debug ("PCMCIA powered at %sV\n", - (reg&0x0400) ? "5.0" : "3.3"); - } else { - debug ("PCMCIA powered down\n"); - } - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CCONFIG_PCMCIA */ diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c deleted file mode 100644 index d06aea7a28..0000000000 --- a/board/r360mpi/r360mpi.c +++ /dev/null @@ -1,403 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include /* for strdup */ - - -/* - * Memory Controller Using - * - * CS0 - Flash memory (0x40000000) - * CS1 - FLASH memory (0x????????) - * CS2 - SDRAM (0x00000000) - * CS3 - - * CS4 - - * CS5 - - * CS6 - PCMCIA device - * CS7 - PCMCIA device - */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -const uint sdram_table[]= -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* MRS initialization (offset 5) */ - - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: R360 MPI Board\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - unsigned long reg; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 2 to the SDRAM bank at - * preliminary address - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (200); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 2 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - -#ifdef CONFIG_CAN_DRIVER - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; /* switch GPLB_5 to GPLA_5 */ - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMB; -#endif - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, - long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -void r360_i2c_lcd_write (uchar data0, uchar data1) -{ - if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) { - printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1); - } -} - -/* ------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------- - * Keyboard Controller - */ - -/* Number of bytes returned from Keyboard Controller */ -#define KEYBD_KEY_MAX 16 /* maximum key number */ -#define KEYBD_DATALEN ((KEYBD_KEY_MAX + 7) / 8) /* normal key scan data */ - -static uchar *key_match (uchar *); - -int misc_init_r (void) -{ - char kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - char *str; - int i; - - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN); - - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - } - setenv ("keybd", keybd_env); - - str = strdup ((char *)key_match ((uchar *)keybd_env)); /* decode keys */ - -#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ - setenv ("preboot", str); /* set or delete definition */ -#endif /* CONFIG_PREBOOT */ - if (str != NULL) { - free (str); - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Check if pressed key(s) match magic sequence, - * and return the command string associated with that key(s). - * - * If no key press was decoded, NULL is returned. - * - * Note: the first character of the argument will be overwritten with - * the "magic charcter code" of the decoded key(s), or '\0'. - * - * - * Note: the string points to static environment data and must be - * saved before you call any function that modifies the environment. - */ -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -static uchar *key_match (uchar * kbd_str) -{ - uchar magic[sizeof (kbd_magic_prefix) + 1]; - uchar cmd_name[sizeof (kbd_command_prefix) + 1]; - uchar *str, *suffix; - uchar *kbd_magic_keys; - char *cmd; - - /* - * The following string defines the characters that can pe appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) { - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; - *suffix || suffix == kbd_magic_keys; - ++suffix) { - sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix); - -#if 0 - printf ("### Check magic \"%s\"\n", magic); -#endif - - if ((str = (uchar *)getenv ((char *)magic)) != 0) { - -#if 0 - printf ("### Compare \"%s\" \"%s\"\n", - kbd_str, str); -#endif - if (strcmp ((char *)kbd_str, (char *)str) == 0) { - sprintf ((char *)cmd_name, "%s%c", - kbd_command_prefix, - *suffix); - - if ((cmd = getenv ((char *)cmd_name)) != 0) { -#if 0 - printf ("### Set PREBOOT to $(%s): \"%s\"\n", - cmd_name, cmd); -#endif - return ((uchar *)cmd); - } - } - } - } - } -#if 0 - printf ("### Delete PREBOOT\n"); -#endif - *kbd_str = '\0'; - return (NULL); -} -#endif /* CONFIG_PREBOOT */ - -/* Read Keyboard status */ -int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar keybd_env[2 * KEYBD_DATALEN + 1]; - int i; - - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* Read keys */ - i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN); - - puts ("Keys:"); - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]); - printf (" %02x", kbd_data[i]); - } - putc ('\n'); - setenv ("keybd", (char *)keybd_env); - return 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "read keyboard status", - "" -); diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds deleted file mode 100644 index 5f69bc4ebe..0000000000 --- a/board/r360mpi/u-boot.lds +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); - . = ALIGN(128 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } -} diff --git a/board/raidsonic/ib62x0/Kconfig b/board/raidsonic/ib62x0/Kconfig new file mode 100644 index 0000000000..129aac8b6d --- /dev/null +++ b/board/raidsonic/ib62x0/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IB62X0 + +config SYS_BOARD + default "ib62x0" + +config SYS_VENDOR + default "raidsonic" + +config SYS_CONFIG_NAME + default "ib62x0" + +endif diff --git a/board/raidsonic/ib62x0/MAINTAINERS b/board/raidsonic/ib62x0/MAINTAINERS new file mode 100644 index 0000000000..423aa0cf25 --- /dev/null +++ b/board/raidsonic/ib62x0/MAINTAINERS @@ -0,0 +1,6 @@ +IB62X0 BOARD +M: Luka Perkov +S: Maintained +F: board/raidsonic/ib62x0/ +F: include/configs/ib62x0.h +F: configs/ib62x0_defconfig diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile index 9d24ad0061..c3b4e69239 100644 --- a/board/raidsonic/ib62x0/Makefile +++ b/board/raidsonic/ib62x0/Makefile @@ -6,24 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ib62x0.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ib62x0.o diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 976ba4ce94..f01fb1c6e7 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include "ib62x0.h" @@ -24,9 +24,9 @@ int board_early_init_f(void) * There are maximum 64 gpios controlled through 2 sets of registers * the below configuration configures mainly initial LED status */ - kw_config_gpio(IB62x0_OE_VAL_LOW, - IB62x0_OE_VAL_HIGH, - IB62x0_OE_LOW, IB62x0_OE_HIGH); + mvebu_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); /* Set SATA activity LEDs to default off */ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG); @@ -62,7 +62,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg index 596071f9b3..ec00c15af3 100644 --- a/board/raidsonic/ib62x0/kwbimage.cfg +++ b/board/raidsonic/ib62x0/kwbimage.cfg @@ -11,7 +11,7 @@ # # Boot Media configurations -BOOT_FROM nand # change from nand to uart if building UART image +BOOT_FROM nand NAND_ECC_MODE default NAND_PAGE_SIZE 0x0800 @@ -21,12 +21,12 @@ NAND_PAGE_SIZE 0x0800 # Configure RGMII-0 interface pad voltage to 1.8V DATA 0xffd100e0 0x1b1b1b9b -#Dram initalization for SINGLE x16 CL=5 @ 400MHz +# Dram initalization for SINGLE x16 CL=5 @ 400MHz DATA 0xffd01400 0x43000c30 # DDR Configuration register # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) # bit23-14: 0x0, -# bit24: 0x1, enable exit self refresh mode on DDR access -# bit25: 0x1, required +# bit24: 0x1, enable exit self refresh mode on DDR access +# bit25: 0x1, required # bit29-26: 0x0, # bit31-30: 0x1, @@ -64,10 +64,10 @@ DATA 0xffd01410 0x0000000c # DDR Address Control # bit3-2: 11, Cs0size (1Gb) # bit5-4: 00, Cs1width (x8) # bit7-6: 11, Cs1size (1Gb) -# bit9-8: 00, Cs2width (nonexistent -# bit11-10: 00, Cs2size (nonexistent -# bit13-12: 00, Cs3width (nonexistent -# bit15-14: 00, Cs3size (nonexistent +# bit9-8: 00, Cs2width (nonexistent) +# bit11-10: 00, Cs2size (nonexistent) +# bit13-12: 00, Cs3width (nonexistent) +# bit15-14: 00, Cs3size (nonexistent) # bit16: 0, Cs0AddrSel # bit17: 0, Cs1AddrSel # bit18: 0, Cs2AddrSel @@ -88,7 +88,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode # bit6-4: 0x4, CL=5 # bit7: 0x0, TestMode=0 normal # bit8: 0x0, DLL reset=0 normal -# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit11-9: 0x6, auto-precharge write recovery # bit12: 0x0, PD must be zero # bit31-13: 0x0, required @@ -148,8 +148,8 @@ DATA 0xffd0149c 0x0000e803 # CPU ODT Control DATA 0xffd01480 0x00000001 # DDR Initialization Control # bit0: 0x1, enable DDR init upon this register write -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register +DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register # End of Header extension DATA 0x0 0x0 diff --git a/board/raspberrypi/rpi/Kconfig b/board/raspberrypi/rpi/Kconfig new file mode 100644 index 0000000000..6a538cfac5 --- /dev/null +++ b/board/raspberrypi/rpi/Kconfig @@ -0,0 +1,15 @@ +if TARGET_RPI + +config SYS_BOARD + default "rpi" + +config SYS_VENDOR + default "raspberrypi" + +config SYS_SOC + default "bcm2835" + +config SYS_CONFIG_NAME + default "rpi" + +endif diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS new file mode 100644 index 0000000000..6dcb7bd24e --- /dev/null +++ b/board/raspberrypi/rpi/MAINTAINERS @@ -0,0 +1,6 @@ +RPI BOARD +M: Stephen Warren +S: Maintained +F: board/raspberrypi/rpi/ +F: include/configs/rpi.h +F: configs/rpi_defconfig diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile new file mode 100644 index 0000000000..c53c92b1dd --- /dev/null +++ b/board/raspberrypi/rpi/Makefile @@ -0,0 +1,15 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +obj-y := rpi.o diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c new file mode 100644 index 0000000000..c18271fce8 --- /dev/null +++ b/board/raspberrypi/rpi/rpi.c @@ -0,0 +1,324 @@ +/* + * (C) Copyright 2012-2013 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct bcm2835_gpio_platdata gpio_platdata = { + .base = BCM2835_GPIO_BASE, +}; + +U_BOOT_DEVICE(bcm2835_gpios) = { + .name = "gpio_bcm2835", + .platdata = &gpio_platdata, +}; + +static const struct pl01x_serial_platdata serial_platdata = { + .base = 0x20201000, + .type = TYPE_PL011, + .clock = 3000000, +}; + +U_BOOT_DEVICE(bcm2835_serials) = { + .name = "serial_pl01x", + .platdata = &serial_platdata, +}; + +struct msg_get_arm_mem { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; + u32 end_tag; +}; + +struct msg_get_board_rev { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_board_rev get_board_rev; + u32 end_tag; +}; + +struct msg_get_mac_address { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_mac_address get_mac_address; + u32 end_tag; +}; + +struct msg_set_power_state { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_set_power_state set_power_state; + u32 end_tag; +}; + +struct msg_get_clock_rate { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_clock_rate get_clock_rate; + u32 end_tag; +}; + +/* See comments in mbox.h for data source */ +static const struct { + const char *name; + const char *fdtfile; + bool has_onboard_eth; +} models[] = { + [0] = { + "Unknown model", + "bcm2835-rpi-other.dtb", + false, + }, + [BCM2835_BOARD_REV_B_I2C0_2] = { + "Model B (no P5)", + "bcm2835-rpi-b-i2c0.dtb", + true, + }, + [BCM2835_BOARD_REV_B_I2C0_3] = { + "Model B (no P5)", + "bcm2835-rpi-b-i2c0.dtb", + true, + }, + [BCM2835_BOARD_REV_B_I2C1_4] = { + "Model B", + "bcm2835-rpi-b.dtb", + true, + }, + [BCM2835_BOARD_REV_B_I2C1_5] = { + "Model B", + "bcm2835-rpi-b.dtb", + true, + }, + [BCM2835_BOARD_REV_B_I2C1_6] = { + "Model B", + "bcm2835-rpi-b.dtb", + true, + }, + [BCM2835_BOARD_REV_A_7] = { + "Model A", + "bcm2835-rpi-a.dtb", + false, + }, + [BCM2835_BOARD_REV_A_8] = { + "Model A", + "bcm2835-rpi-a.dtb", + false, + }, + [BCM2835_BOARD_REV_A_9] = { + "Model A", + "bcm2835-rpi-a.dtb", + false, + }, + [BCM2835_BOARD_REV_B_REV2_d] = { + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", + true, + }, + [BCM2835_BOARD_REV_B_REV2_e] = { + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", + true, + }, + [BCM2835_BOARD_REV_B_REV2_f] = { + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", + true, + }, + [BCM2835_BOARD_REV_B_PLUS] = { + "Model B+", + "bcm2835-rpi-b-plus.dtb", + true, + }, + [BCM2835_BOARD_REV_CM] = { + "Compute Module", + "bcm2835-rpi-cm.dtb", + false, + }, + [BCM2835_BOARD_REV_A_PLUS] = { + "Model A+", + "bcm2835-rpi-a-plus.dtb", + false, + }, +}; + +u32 rpi_board_rev = 0; + +int dram_init(void) +{ + ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16); + int ret; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + printf("bcm2835: Could not query ARM memory size\n"); + return -1; + } + + gd->ram_size = msg->get_arm_mem.body.resp.mem_size; + + return 0; +} + +static void set_fdtfile(void) +{ + const char *fdtfile; + + if (getenv("fdtfile")) + return; + + fdtfile = models[rpi_board_rev].fdtfile; + setenv("fdtfile", fdtfile); +} + +static void set_usbethaddr(void) +{ + ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16); + int ret; + + if (!models[rpi_board_rev].has_onboard_eth) + return; + + if (getenv("usbethaddr")) + return; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + printf("bcm2835: Could not query MAC address\n"); + /* Ignore error; not critical */ + return; + } + + eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac); + + return; +} + +int misc_init_r(void) +{ + set_fdtfile(); + set_usbethaddr(); + return 0; +} + +static int power_on_module(u32 module) +{ + ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16); + int ret; + + BCM2835_MBOX_INIT_HDR(msg_pwr); + BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state, + SET_POWER_STATE); + msg_pwr->set_power_state.body.req.device_id = module; + msg_pwr->set_power_state.body.req.state = + BCM2835_MBOX_SET_POWER_STATE_REQ_ON | + BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, + &msg_pwr->hdr); + if (ret) { + printf("bcm2835: Could not set module %u power state\n", + module); + return -1; + } + + return 0; +} + +static void get_board_rev(void) +{ + ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16); + int ret; + const char *name; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + printf("bcm2835: Could not query board revision\n"); + /* Ignore error; not critical */ + return; + } + + rpi_board_rev = msg->get_board_rev.body.resp.rev; + if (rpi_board_rev >= ARRAY_SIZE(models)) { + printf("RPI: Board rev %u outside known range\n", + rpi_board_rev); + rpi_board_rev = 0; + } + if (!models[rpi_board_rev].name) { + printf("RPI: Board rev %u unknown\n", rpi_board_rev); + rpi_board_rev = 0; + } + + name = models[rpi_board_rev].name; + printf("RPI model: %s\n", name); +} + +int board_init(void) +{ + get_board_rev(); + + gd->bd->bi_boot_params = 0x100; + + return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); +} + +int board_mmc_init(bd_t *bis) +{ + ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16); + int ret; + + power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI); + + BCM2835_MBOX_INIT_HDR(msg_clk); + BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE); + msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr); + if (ret) { + printf("bcm2835: Could not query eMMC clock rate\n"); + return -1; + } + + return bcm2835_sdhci_init(BCM2835_SDHCI_BASE, + msg_clk->get_clock_rate.body.resp.rate_hz); +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* + * For now, we simply always add the simplefb DT node. Later, we + * should be more intelligent, and e.g. only do this if no enabled DT + * node exists for the "real" graphics driver. + */ + lcd_dt_simplefb_add_node(blob); + + return 0; +} diff --git a/board/raspberrypi/rpi_b/Makefile b/board/raspberrypi/rpi_b/Makefile deleted file mode 100644 index 9d0c377c1b..0000000000 --- a/board/raspberrypi/rpi_b/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c deleted file mode 100644 index 16d442aa62..0000000000 --- a/board/raspberrypi/rpi_b/rpi_b.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2012-2013 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct msg_get_arm_mem { - struct bcm2835_mbox_hdr hdr; - struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; - u32 end_tag; -}; - -struct msg_get_clock_rate { - struct bcm2835_mbox_hdr hdr; - struct bcm2835_mbox_tag_get_clock_rate get_clock_rate; - u32 end_tag; -}; - -int dram_init(void) -{ - ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16); - int ret; - - BCM2835_MBOX_INIT_HDR(msg); - BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY); - - ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); - if (ret) { - printf("bcm2835: Could not query ARM memory size\n"); - return -1; - } - - gd->ram_size = msg->get_arm_mem.body.resp.mem_size; - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = 0x100; - - return 0; -} - -int board_mmc_init(void) -{ - ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16); - int ret; - - BCM2835_MBOX_INIT_HDR(msg_clk); - BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE); - msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC; - - ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr); - if (ret) { - printf("bcm2835: Could not query eMMC clock rate\n"); - return -1; - } - - return bcm2835_sdhci_init(BCM2835_SDHCI_BASE, - msg_clk->get_clock_rate.body.resp.rate_hz); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - /* - * For now, we simply always add the simplefb DT node. Later, we - * should be more intelligent, and e.g. only do this if no enabled DT - * node exists for the "real" graphics driver. - */ - lcd_dt_simplefb_add_node(blob); -} diff --git a/board/rattler/Makefile b/board/rattler/Makefile deleted file mode 100644 index c573be952c..0000000000 --- a/board/rattler/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c deleted file mode 100644 index f7fb349f71..0000000000 --- a/board/rattler/rattler.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Analogue&Micro Rattler boards family. - * Tested on Rattler8248. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */ - /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */ - /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ - /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */ - /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -phys_size_t initdram(int board_type) -{ - long int msize = CONFIG_SYS_SDRAM_SIZE; - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE; - uchar c = 0xFF; - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or1 = CONFIG_SYS_SDRAM_OR; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BR; - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* !CONFIG_SYS_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40); - return 0; -} diff --git a/board/rbc823/Makefile b/board/rbc823/Makefile deleted file mode 100644 index 6e47cb5a26..0000000000 --- a/board/rbc823/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o kbd.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c deleted file mode 100644 index 8a2265263c..0000000000 --- a/board/rbc823/flash.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* - * Functions - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info); -static int write_word(flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets(ulong base, flash_info_t *info); - -unsigned long flash_init(void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - /* Setup offsets */ - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return size_b0; -} - -/*----------------------------------------------------------------------- - * Fix this to support variable sector sizes -*/ -static void flash_get_offsets(ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - if (info->size >> 20) { - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - } else { - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); - } - - puts(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - puts("\n "); - - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - putc('\n'); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr; - char value; - - caddr = (volatile unsigned char *)addr ; - - /* Write auto select command: read Manufacturer ID */ - - debug("Base address is: %8p\n", caddr); - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - value = caddr[0]; - - debug("Manufact ID: %02x\n", value); - - switch (value) { - case 0x01: /*AMD_MANUFACT*/ - info->flash_id = FLASH_MAN_AMD; - break; - - case 0x04: /*FUJ_MANUFACT*/ - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = caddr[1]; /* device ID */ - - debug("Device ID: %02x\n", value); - - switch (value) { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, &flash_info[0]); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address, - * (A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ - } - - return info->size; -} - - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - - while ((addr[0] & 0xFF) != 0xFF) { - now = get_timer(start); - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return write_word(info, wp, data); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *cdest, *cdata; - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - ulong start; - int flag, count = 4 ; - - cdest = (volatile unsigned char *)dest ; - cdata = (volatile unsigned char *)&data ; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest)&data) != data) - return 2; - - while (count--) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *cdest = *cdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*cdest ^ *cdata) & 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - - cdata++ ; - cdest++ ; - } - return 0; -} diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c deleted file mode 100644 index b35509ab39..0000000000 --- a/board/rbc823/kbd.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Modified by Udi Finkelstein - * - * This file includes communication routines for SMC1 that can run even if - * SMC2 have already been initialized. - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define SMC_INDEX 0 -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 - -#define RBC823_KBD_BAUDRATE 38400 -#define CPM_KEYBOARD_BASE 0x1000 -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -void smc1_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG2 to SMC1, BRG1 to SMC2 - */ - - cp->cp_simode = 0x00001000; - - cp->cp_brgc2 = - (((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN; -} - -int smc1_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CONFIG_SYS_SDSR - im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CONFIG_SYS_SDMR - im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - - /* Use Port B for SMC1 instead of other functions. - */ - cp->cp_pbpar |= 0x000000c0; - cp->cp_pbdir &= ~0x000000c0; - cp->cp_pbodr &= ~0x000000c0; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - -#ifdef CONFIG_SYS_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; -#else - dpaddr = CPM_KEYBOARD_BASE ; -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - smc1_setbrg (); - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -void smc1_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *)tbdf->cbd_bufaddr; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (tbdf->cbd_sc & BD_SC_READY) { - WATCHDOG_RESET (); - __asm__("eieio"); - } -} - -int smc1_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -int smc1_tstc(void) -{ - volatile cbd_t *rbdf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -/* search for keyboard and register it if found */ -int drv_keyboard_init(void) -{ - int error = 0; - struct stdio_dev kbd_dev; - - if (0) { - /* register the keyboard */ - memset (&kbd_dev, 0, sizeof(struct stdio_dev)); - strcpy(kbd_dev.name, "kbd"); - kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbd_dev.putc = NULL; - kbd_dev.puts = NULL; - kbd_dev.getc = smc1_getc; - kbd_dev.tstc = smc1_tstc; - error = stdio_register (&kbd_dev); - } else { - lcd_is_enabled = 0; - lcd_disable(); - } - return error; -} diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c deleted file mode 100644 index f276e5e5f5..0000000000 --- a/board/rbc823/rbc823.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include "mpc8xx.h" -#include - -extern int kbd_init(void); -extern int drv_kbd_init(void); - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x1FF7FC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -const uint static_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04, - 0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04, - 0xFFFFFC04, 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04, - 0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Return 1 for "L" type, 0 else. - */ - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - if (i < 0 || strncmp(buf, "TQM8", 4)) { - printf ("### No HW ID - assuming RBC823\n"); - return (0); - } - - puts(buf); - putc('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * 1 Bank of 64Mbit x 2 devices - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - memctl->memc_mar = 0x00000088; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - udelay (200); - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; - udelay (200); - memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */ - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM, - SDRAM_MAX_SIZE); - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -#ifdef CONFIG_CMD_DOC -void doc_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMB, (uint *) static_table, - sizeof (static_table) / sizeof (uint)); - memctl->memc_mbmr = MAMR_DSA_1_CYCL; - - doc_probe (FLASH_BASE1_PRELIM); -} -#endif diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds deleted file mode 100644 index 191f9eb837..0000000000 --- a/board/rbc823/u-boot.lds +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - lib/libgeneric.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/renesas/MigoR/Kconfig b/board/renesas/MigoR/Kconfig new file mode 100644 index 0000000000..25b170ac07 --- /dev/null +++ b/board/renesas/MigoR/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MIGOR + +config SYS_BOARD + default "MigoR" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "MigoR" + +endif diff --git a/board/renesas/MigoR/MAINTAINERS b/board/renesas/MigoR/MAINTAINERS new file mode 100644 index 0000000000..21ee5e2754 --- /dev/null +++ b/board/renesas/MigoR/MAINTAINERS @@ -0,0 +1,6 @@ +MIGOR BOARD +#M: - +S: Maintained +F: board/renesas/MigoR/ +F: include/configs/MigoR.h +F: configs/MigoR_defconfig diff --git a/board/renesas/MigoR/Makefile b/board/renesas/MigoR/Makefile index 7725c449cd..b4691a1165 100644 --- a/board/renesas/MigoR/Makefile +++ b/board/renesas/MigoR/Makefile @@ -9,25 +9,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := migo_r.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := migo_r.o +obj-y += lowlevel_init.o diff --git a/board/renesas/alt/Kconfig b/board/renesas/alt/Kconfig new file mode 100644 index 0000000000..957962de20 --- /dev/null +++ b/board/renesas/alt/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ALT + +config SYS_BOARD + default "alt" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "alt" + +endif diff --git a/board/renesas/alt/MAINTAINERS b/board/renesas/alt/MAINTAINERS new file mode 100644 index 0000000000..6ec140b225 --- /dev/null +++ b/board/renesas/alt/MAINTAINERS @@ -0,0 +1,6 @@ +ALT BOARD +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/alt/ +F: include/configs/alt.h +F: configs/alt_defconfig diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile new file mode 100644 index 0000000000..6904e39b12 --- /dev/null +++ b/board/renesas/alt/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/alt/Makefile +# +# Copyright (C) 2014 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := alt.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c new file mode 100644 index 0000000000..8cc17e9581 --- /dev/null +++ b/board/renesas/alt/alt.c @@ -0,0 +1,161 @@ +/* + * board/renesas/alt/alt.c + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* QoS */ + qos_init(); +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF2_MSTP719 (1 << 19) +#define ETHER_MSTP813 (1 << 13) +#define IIC1_MSTP323 (1 << 23) +#define MMC0_MSTP315 (1 << 15) + +int board_early_init_f(void) +{ + /* TMU */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF2 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + /* IIC1 / sh-i2c ch1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); + +#ifdef CONFIG_SH_MMCIF + /* MMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); +#endif + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7794_pinmux_init(); + + /* Ether Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ8, NULL); + + /* PHY reset */ + gpio_request(GPIO_GP_1_24, NULL); + gpio_direction_output(GPIO_GP_1_24, 0); + mdelay(20); + gpio_set_value(GPIO_GP_1_24, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else + return 0; +#endif +} + +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_SH_MMCIF + gpio_request(GPIO_GP_4_31, NULL); + gpio_set_value(GPIO_GP_4_31, 1); + + ret = mmcif_mmc_init(); +#endif + return ret; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(1); /* PowerIC connected to ch1 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c new file mode 100644 index 0000000000..f0b349f18f --- /dev/null +++ b/board/renesas/alt/qos.c @@ -0,0 +1,950 @@ +/* + * board/renesas/alt/qos.c + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +/* QoS version 0.11 */ + +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x1F0D0B0A, &s3c->s3crorr); + writel(0x1F0D0B09, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80928092, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x0000202A, &qos_addr->dbtmval2); + writel(0x00001FBD, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x00002043, &qos_addr->dbtmval2); + writel(0x00002030, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002031, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20000800, CCI_400_MAXOT_1); + writel(0x20000800, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/alt/qos.h b/board/renesas/alt/qos.h new file mode 100644 index 0000000000..9a6c0461be --- /dev/null +++ b/board/renesas/alt/qos.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif diff --git a/board/renesas/ap325rxa/Kconfig b/board/renesas/ap325rxa/Kconfig new file mode 100644 index 0000000000..c8f2de2959 --- /dev/null +++ b/board/renesas/ap325rxa/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AP325RXA + +config SYS_BOARD + default "ap325rxa" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "ap325rxa" + +endif diff --git a/board/renesas/ap325rxa/MAINTAINERS b/board/renesas/ap325rxa/MAINTAINERS new file mode 100644 index 0000000000..bdc49c5ec9 --- /dev/null +++ b/board/renesas/ap325rxa/MAINTAINERS @@ -0,0 +1,7 @@ +AP325RXA BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/ap325rxa/ +F: include/configs/ap325rxa.h +F: configs/ap325rxa_defconfig diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile index 0597d0fc5e..ff72de902c 100644 --- a/board/renesas/ap325rxa/Makefile +++ b/board/renesas/ap325rxa/Makefile @@ -8,25 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ap325rxa.o cpld-ap325rxa.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ap325rxa.o cpld-ap325rxa.o +obj-y += lowlevel_init.o diff --git a/board/renesas/ecovec/Kconfig b/board/renesas/ecovec/Kconfig new file mode 100644 index 0000000000..08cde83356 --- /dev/null +++ b/board/renesas/ecovec/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ECOVEC + +config SYS_BOARD + default "ecovec" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "ecovec" + +endif diff --git a/board/renesas/ecovec/MAINTAINERS b/board/renesas/ecovec/MAINTAINERS new file mode 100644 index 0000000000..439b528de9 --- /dev/null +++ b/board/renesas/ecovec/MAINTAINERS @@ -0,0 +1,7 @@ +ECOVEC BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/ecovec/ +F: include/configs/ecovec.h +F: configs/ecovec_defconfig diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile index f2a02f81b5..943fa4760d 100644 --- a/board/renesas/ecovec/Makefile +++ b/board/renesas/ecovec/Makefile @@ -4,26 +4,5 @@ # # SPDX-License-Identifier: GPL-2.0+ - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ecovec.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ecovec.o +obj-y += lowlevel_init.o diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c index e2d365a187..d862d997e5 100644 --- a/board/renesas/ecovec/ecovec.c +++ b/board/renesas/ecovec/ecovec.c @@ -41,7 +41,7 @@ static void debug_led(u8 led) int board_late_init(void) { u8 mac[6]; - char env_mac[17]; + char env_mac[18]; udelay(1000); @@ -57,8 +57,7 @@ int board_late_init(void) outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */ + i2c_set_bus_num(1); /* Use I2C 1 */ /* Read MAC address */ i2c_read(0x50, 0x10, 0, mac, 6); @@ -77,7 +76,7 @@ int board_init(void) { /* LED (PTG) */ - outw((inw(PGCR) & ~0xFF) | 0x66, PGCR); + outw((inw(PGCR) & ~0xFF) | 0x55, PGCR); outw((inw(HIZCRA) & ~0x02), HIZCRA); debug_led(1 << 0); @@ -98,7 +97,7 @@ int board_init(void) /* USB host */ outw((inw(PBCR) & ~0x300) | 0x100, PBCR); outb((inb(PBDR) & ~0x10) | 0x10, PBDR); - outl(inl(MSTPCR2) & 0x100000, MSTPCR2); + outl(inl(MSTPCR2) & ~0x100000, MSTPCR2); outw(0x0600, UPONCR0); debug_led(1 << 3); diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S index eeebdd245f..e4c40c8616 100644 --- a/board/renesas/ecovec/lowlevel_init.S +++ b/board/renesas/ecovec/lowlevel_init.S @@ -20,7 +20,7 @@ lowlevel_init: - /* jump to 0xA0020000 if bit 1 of PVDR_A */ + /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */ mov.l PVDR_A, r1 mov.l PVDR_D, r2 mov.b @r1, r0 diff --git a/board/renesas/gose/Kconfig b/board/renesas/gose/Kconfig new file mode 100644 index 0000000000..930a44559e --- /dev/null +++ b/board/renesas/gose/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GOSE + +config SYS_BOARD + default "gose" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "gose" + +endif diff --git a/board/renesas/gose/MAINTAINERS b/board/renesas/gose/MAINTAINERS new file mode 100644 index 0000000000..cad5be99b1 --- /dev/null +++ b/board/renesas/gose/MAINTAINERS @@ -0,0 +1,6 @@ +ALT BOARD +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/gose/ +F: include/configs/gose.h +F: configs/gose_defconfig diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile new file mode 100644 index 0000000000..2dac748efb --- /dev/null +++ b/board/renesas/gose/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/alt/Makefile +# +# Copyright (C) 2014 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := gose.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c new file mode 100644 index 0000000000..677b976aaf --- /dev/null +++ b/board/renesas/gose/gose.c @@ -0,0 +1,146 @@ +/* + * board/renesas/gose/gose.c + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 1.5GHz */ + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + + /* QoS */ + qos_init(); +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF0_MSTP721 (1 << 21) +#define ETHER_MSTP813 (1 << 13) + +int board_early_init_f(void) +{ + /* TMU0 */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF0 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + return 0; +} + +#define PUPR5 0xE6060114 +#define PUPR5_ETH 0x3FFC0000 +#define PUPR5_ETH_MAGIC (1 << 27) + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7793_pinmux_init(); + + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); + gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); + + gpio_direction_output(GPIO_GP_5_22, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_22, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ + +int board_eth_init(bd_t *bis) +{ + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + +#ifdef CONFIG_SH_ETHER + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); +#endif + + return ret; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(2); /* PowerIC connected to ch2 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c new file mode 100644 index 0000000000..64e52cf3a4 --- /dev/null +++ b/board/renesas/gose/qos.c @@ -0,0 +1,1155 @@ +/* + * board/renesas/gose/qos.c + * This file is gose QoS setting. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +/* QoS version 0.20 */ +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x00000000, &s3c->s3cadsplcr); + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0C0A08, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00200000, &mxi->mxs3cracr); + writel(0x00200000, &mxi->mxs3cwacr); + writel(0x00200000, &mxi->mxaxiracr); + writel(0x00200000, &mxi->mxaxiwacr); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000C, &mxi_qos->vspdu1); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002299, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/gose/qos.h b/board/renesas/gose/qos.h new file mode 100644 index 0000000000..ffd404797d --- /dev/null +++ b/board/renesas/gose/qos.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif diff --git a/board/renesas/koelsch/Kconfig b/board/renesas/koelsch/Kconfig new file mode 100644 index 0000000000..6475f02b66 --- /dev/null +++ b/board/renesas/koelsch/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KOELSCH + +config SYS_BOARD + default "koelsch" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "koelsch" + +endif diff --git a/board/renesas/koelsch/MAINTAINERS b/board/renesas/koelsch/MAINTAINERS new file mode 100644 index 0000000000..5267b9fadf --- /dev/null +++ b/board/renesas/koelsch/MAINTAINERS @@ -0,0 +1,6 @@ +KOELSCH BOARD +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/koelsch/ +F: include/configs/koelsch.h +F: configs/koelsch_defconfig diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile new file mode 100644 index 0000000000..c10bba5682 --- /dev/null +++ b/board/renesas/koelsch/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/koelsch/Makefile +# +# Copyright (C) 2013 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := koelsch.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c new file mode 100644 index 0000000000..10fa571d07 --- /dev/null +++ b/board/renesas/koelsch/koelsch.c @@ -0,0 +1,162 @@ +/* + * board/renesas/koelsch/koelsch.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 1.5GHz */ + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + + /* QoS */ + qos_init(); +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF0_MSTP721 (1 << 21) +#define ETHER_MSTP813 (1 << 13) + +int board_early_init_f(void) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF0 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + return 0; +} + +/* LSI pin pull-up control */ +#define PUPR5 0xe6060114 +#define PUPR5_ETH 0x3FFC0000 +#define PUPR5_ETH_MAGIC (1 << 27) +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7791_pinmux_init(); + + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); + gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); + + gpio_direction_output(GPIO_GP_5_22, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_22, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else + return 0; +#endif +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +/* koelsch has KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) +{ + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(2); /* PowerIC connected to ch2 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c new file mode 100644 index 0000000000..d293e3d7fc --- /dev/null +++ b/board/renesas/koelsch/qos.c @@ -0,0 +1,1311 @@ +/* + * board/renesas/koelsch/qos.c + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include +#include +#include +#include +#include + +/* QoS version 0.240 for ES1 and version 0.334 for ES2 */ +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_1_QOS_R0_BASE, + [DBSC3_01] = DBSC3_1_QOS_R1_BASE, + [DBSC3_02] = DBSC3_1_QOS_R2_BASE, + [DBSC3_03] = DBSC3_1_QOS_R3_BASE, + [DBSC3_04] = DBSC3_1_QOS_R4_BASE, + [DBSC3_05] = DBSC3_1_QOS_R5_BASE, + [DBSC3_06] = DBSC3_1_QOS_R6_BASE, + [DBSC3_07] = DBSC3_1_QOS_R7_BASE, + [DBSC3_08] = DBSC3_1_QOS_R8_BASE, + [DBSC3_09] = DBSC3_1_QOS_R9_BASE, + [DBSC3_10] = DBSC3_1_QOS_R10_BASE, + [DBSC3_11] = DBSC3_1_QOS_R11_BASE, + [DBSC3_12] = DBSC3_1_QOS_R12_BASE, + [DBSC3_13] = DBSC3_1_QOS_R13_BASE, + [DBSC3_14] = DBSC3_1_QOS_R14_BASE, + [DBSC3_15] = DBSC3_1_QOS_R15_BASE, +}; + +static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_1_QOS_W0_BASE, + [DBSC3_01] = DBSC3_1_QOS_W1_BASE, + [DBSC3_02] = DBSC3_1_QOS_W2_BASE, + [DBSC3_03] = DBSC3_1_QOS_W3_BASE, + [DBSC3_04] = DBSC3_1_QOS_W4_BASE, + [DBSC3_05] = DBSC3_1_QOS_W5_BASE, + [DBSC3_06] = DBSC3_1_QOS_W6_BASE, + [DBSC3_07] = DBSC3_1_QOS_W7_BASE, + [DBSC3_08] = DBSC3_1_QOS_W8_BASE, + [DBSC3_09] = DBSC3_1_QOS_W9_BASE, + [DBSC3_10] = DBSC3_1_QOS_W10_BASE, + [DBSC3_11] = DBSC3_1_QOS_W11_BASE, + [DBSC3_12] = DBSC3_1_QOS_W12_BASE, + [DBSC3_13] = DBSC3_1_QOS_W13_BASE, + [DBSC3_14] = DBSC3_1_QOS_W14_BASE, + [DBSC3_15] = DBSC3_1_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + writel(0x20042004, DBSC3_1_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + if (IS_R8A7791_ES2()) { + /* Linear All mode */ + /* writel(0x00000000, &s3c->s3cadsplcr); */ + /* Linear Linear 0x7000 to 0x7800 mode */ + writel(0x00BF1B0C, &s3c->s3cadsplcr); + /* Split Linear 0x6800 t 0x7000 mode */ + /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */ + /* Ssplit All mode */ + /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */ + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0C0A08, &s3c->s3cworr); + } else { + writel(0x00FF1B1D, &s3c->s3cadsplcr); + writel(0x1F0D0C0C, &s3c->s3crorr); + writel(0x1F0D0C0A, &s3c->s3cworr); + } + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC1 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC1 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000C, &mxi_qos->vspdu1); + writel(0x0000000E, &mxi_qos->du0); + writel(0x0000000D, &mxi_qos->du1); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002299, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x00001FF0, &axi_qos->qosctset0); + else + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) + writel(0x00002001, &axi_qos->qosthres2); + else + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000000, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/koelsch/qos.h b/board/renesas/koelsch/qos.h new file mode 100644 index 0000000000..9a6c0461be --- /dev/null +++ b/board/renesas/koelsch/qos.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif diff --git a/board/renesas/lager/Kconfig b/board/renesas/lager/Kconfig new file mode 100644 index 0000000000..e990c2019c --- /dev/null +++ b/board/renesas/lager/Kconfig @@ -0,0 +1,12 @@ +if TARGET_LAGER + +config SYS_BOARD + default "lager" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "lager" + +endif diff --git a/board/renesas/lager/MAINTAINERS b/board/renesas/lager/MAINTAINERS new file mode 100644 index 0000000000..a09868614a --- /dev/null +++ b/board/renesas/lager/MAINTAINERS @@ -0,0 +1,6 @@ +LAGER BOARD +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/lager/ +F: include/configs/lager.h +F: configs/lager_defconfig diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile new file mode 100644 index 0000000000..8d034611a4 --- /dev/null +++ b/board/renesas/lager/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/lager/Makefile +# +# Copyright (C) 2013 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := lager.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c new file mode 100644 index 0000000000..d1e29d2cec --- /dev/null +++ b/board/renesas/lager/lager.c @@ -0,0 +1,191 @@ +/* + * board/renesas/lager/lager.c + * This file is lager board support. + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 1.4GHz */ + if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { + u32 stat = 0; + u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) + << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + + do { + stat = readl(PLLECR) & PLL0ST; + } while (stat == 0x0); + } + + /* QoS(Quality-of-Service) Init */ + qos_init(); +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF0_MSTP721 (1 << 21) +#define ETHER_MSTP813 (1 << 13) +#define MMC1_MSTP305 (1 << 5) + +int board_early_init_f(void) +{ + /* TMU0 */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + /* SCIF0 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + /* eMMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305); + + return 0; +} + +DECLARE_GLOBAL_DATA_PTR; +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7790_pinmux_init(); + + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REF_CLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ + gpio_direction_output(GPIO_GP_5_31, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_31, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ + int ret = -ENODEV; + +#ifdef CONFIG_SH_ETHER + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + +#endif + + return ret; +} + +/* lager has KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) +{ + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_SH_MMCIF + gpio_request(GPIO_FN_MMC1_D0, NULL); + gpio_request(GPIO_FN_MMC1_D1, NULL); + gpio_request(GPIO_FN_MMC1_D2, NULL); + gpio_request(GPIO_FN_MMC1_D3, NULL); + gpio_request(GPIO_FN_MMC1_D4, NULL); + gpio_request(GPIO_FN_MMC1_D5, NULL); + gpio_request(GPIO_FN_MMC1_D6, NULL); + gpio_request(GPIO_FN_MMC1_D7, NULL); + gpio_request(GPIO_FN_MMC1_CLK, NULL); + gpio_request(GPIO_FN_MMC1_CMD, NULL); + + ret = mmcif_mmc_init(); +#endif + return ret; +} + + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(3); /* PowerIC connected to ch3 */ + i2c_init(400000, 0); + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c new file mode 100644 index 0000000000..dec37d2bf9 --- /dev/null +++ b/board/renesas/lager/qos.c @@ -0,0 +1,2388 @@ +/* + * board/renesas/lager/qos.c + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +/* QoS version 0.955 for ES1 and version 0.963 for ES2 */ +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +/* QoS version 0.955 for ES1 */ +static void qos_init_es1(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x80FF1C1E, &s3c->s3cadsplcr); + writel(0x1F060505, &s3c->s3crorr); + writel(0x1F020100, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00800080, &s3c_qos->s3cqos0); + writel(0x22000010, &s3c_qos->s3cqos1); + writel(0x22002200, &s3c_qos->s3cqos2); + writel(0x2F002200, &s3c_qos->s3cqos3); + writel(0x2F002F00, &s3c_qos->s3cqos4); + writel(0x22000010, &s3c_qos->s3cqos5); + writel(0x22002200, &s3c_qos->s3cqos6); + writel(0x2F002200, &s3c_qos->s3cqos7); + writel(0x2F002F00, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00800080, &s3c_qos->s3cqos0); + writel(0x22000010, &s3c_qos->s3cqos1); + writel(0x22002200, &s3c_qos->s3cqos2); + writel(0x2F002200, &s3c_qos->s3cqos3); + writel(0x2F002F00, &s3c_qos->s3cqos4); + writel(0x22000010, &s3c_qos->s3cqos5); + writel(0x22002200, &s3c_qos->s3cqos6); + writel(0x2F002200, &s3c_qos->s3cqos7); + writel(0x2F002F00, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80918099, &s3c_qos->s3cqos0); + writel(0x20410010, &s3c_qos->s3cqos1); + writel(0x200A2023, &s3c_qos->s3cqos2); + writel(0x20502001, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20410FFF, &s3c_qos->s3cqos5); + writel(0x200A2023, &s3c_qos->s3cqos6); + writel(0x20502001, &s3c_qos->s3cqos7); + writel(0x20142032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00810089, &s3c_qos->s3cqos0); + writel(0x20410001, &s3c_qos->s3cqos1); + writel(0x200A2023, &s3c_qos->s3cqos2); + writel(0x20502001, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20410FFF, &s3c_qos->s3cqos5); + writel(0x200A2023, &s3c_qos->s3cqos6); + writel(0x20502001, &s3c_qos->s3cqos7); + writel(0x20142032, &s3c_qos->s3cqos8); + + writel(0x00200808, &s3c->s3carcr11); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000203, &qos_addr->dblgcnt); + writel(0x00002064, &qos_addr->dbtmval0); + writel(0x00002048, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00002019, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002019, &qos_addr->dbthres0); + writel(0x00002019, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000000, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000203, &qos_addr->dblgcnt); + writel(0x00002064, &qos_addr->dbtmval0); + writel(0x00002048, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00002019, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002019, &qos_addr->dbthres0); + writel(0x00002019, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000000, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00B800C0, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + writel(0x00200000, &mxi->mxs3cracr); + writel(0x00200000, &mxi->mxs3cwacr); + writel(0x00200000, &mxi->mxaxiracr); + writel(0x00200000, &mxi->mxaxiwacr); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000C, &mxi_qos->vspdu1); + writel(0x0000000D, &mxi_qos->du0); + writel(0x0000000D, &mxi_qos->du1); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200A, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200A, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002002, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002002, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002002, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200A, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200A, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002005, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002005, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002005, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002005, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002003, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200D, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x0000200F, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002001, &axi_qos->qosctset0); + writel(0x00002009, &axi_qos->qosctset1); + writel(0x00002003, &axi_qos->qosctset2); + writel(0x00002003, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002018, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000200C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002007, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002006, &axi_qos->qosthres0); + writel(0x00002001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000000, &axi_qos->qosqon); +} + +/* QoS version 0.963 for ES2 */ +static void qos_init_es2(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x80000000, &s3c->s3cadsplcr); + writel(0x1F060504, &s3c->s3crorr); + writel(0x1F060503, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80928092, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + writel(0x00200808, &s3c->s3carcr11); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00B800C0, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000C, &mxi_qos->vspdu1); + writel(0x0000000E, &mxi_qos->du0); + writel(0x0000000E, &mxi_qos->du1); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002299, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020dc, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020dc, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} + +void qos_init(void) +{ + if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) + qos_init_es2(); + else + qos_init_es1(); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/lager/qos.h b/board/renesas/lager/qos.h new file mode 100644 index 0000000000..9a6c0461be --- /dev/null +++ b/board/renesas/lager/qos.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif diff --git a/board/renesas/r0p7734/Kconfig b/board/renesas/r0p7734/Kconfig new file mode 100644 index 0000000000..7f24f41b8f --- /dev/null +++ b/board/renesas/r0p7734/Kconfig @@ -0,0 +1,12 @@ +if TARGET_R0P7734 + +config SYS_BOARD + default "r0p7734" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "r0p7734" + +endif diff --git a/board/renesas/r0p7734/MAINTAINERS b/board/renesas/r0p7734/MAINTAINERS new file mode 100644 index 0000000000..c169ad7ecc --- /dev/null +++ b/board/renesas/r0p7734/MAINTAINERS @@ -0,0 +1,7 @@ +R0P7734 BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/r0p7734/ +F: include/configs/r0p7734.h +F: configs/r0p7734_defconfig diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile index 24933cc491..1f24d92962 100644 --- a/board/renesas/r0p7734/Makefile +++ b/board/renesas/r0p7734/Makefile @@ -3,25 +3,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := r0p7734.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := r0p7734.o +obj-y += lowlevel_init.o diff --git a/board/renesas/r2dplus/Kconfig b/board/renesas/r2dplus/Kconfig new file mode 100644 index 0000000000..6597870a86 --- /dev/null +++ b/board/renesas/r2dplus/Kconfig @@ -0,0 +1,12 @@ +if TARGET_R2DPLUS + +config SYS_BOARD + default "r2dplus" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "r2dplus" + +endif diff --git a/board/renesas/r2dplus/MAINTAINERS b/board/renesas/r2dplus/MAINTAINERS new file mode 100644 index 0000000000..58877c509e --- /dev/null +++ b/board/renesas/r2dplus/MAINTAINERS @@ -0,0 +1,7 @@ +R2DPLUS BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/r2dplus/ +F: include/configs/r2dplus.h +F: configs/r2dplus_defconfig diff --git a/board/renesas/r2dplus/Makefile b/board/renesas/r2dplus/Makefile index f0023abe86..acffb6d319 100644 --- a/board/renesas/r2dplus/Makefile +++ b/board/renesas/r2dplus/Makefile @@ -4,25 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).o - -COBJS := r2dplus.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := r2dplus.o +obj-y += lowlevel_init.o diff --git a/board/renesas/r7780mp/Kconfig b/board/renesas/r7780mp/Kconfig new file mode 100644 index 0000000000..050cc4cc0f --- /dev/null +++ b/board/renesas/r7780mp/Kconfig @@ -0,0 +1,12 @@ +if TARGET_R7780MP + +config SYS_BOARD + default "r7780mp" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "r7780mp" + +endif diff --git a/board/renesas/r7780mp/MAINTAINERS b/board/renesas/r7780mp/MAINTAINERS new file mode 100644 index 0000000000..56ec21fd32 --- /dev/null +++ b/board/renesas/r7780mp/MAINTAINERS @@ -0,0 +1,7 @@ +R7780MP BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/r7780mp/ +F: include/configs/r7780mp.h +F: configs/r7780mp_defconfig diff --git a/board/renesas/r7780mp/Makefile b/board/renesas/r7780mp/Makefile index c95ac12f4d..8dab4358cd 100644 --- a/board/renesas/r7780mp/Makefile +++ b/board/renesas/r7780mp/Makefile @@ -5,25 +5,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := r7780mp.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := r7780mp.o +obj-y += lowlevel_init.o diff --git a/board/renesas/rcar-gen2-common/common.c b/board/renesas/rcar-gen2-common/common.c new file mode 100644 index 0000000000..0103f42bd5 --- /dev/null +++ b/board/renesas/rcar-gen2-common/common.c @@ -0,0 +1,59 @@ +/* + * board/renesas/rcar-gen2-common/common.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#define TSTR0 0x04 +#define TSTR0_STR0 0x01 + +static struct mstp_ctl mstptbl[] = { + { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA, + RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA }, + { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA, + RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA }, + { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA, + RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA }, + { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA, + RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA }, + { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA, + RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA }, + { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA, + RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA }, + /* No MSTP6 */ + { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA, + RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA }, + { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA, + RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA }, + { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA, + RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA }, + { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA, + RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA }, + { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA, + RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA }, +}; + +void arch_preboot_os(void) +{ + int i; + + /* stop TMU0 */ + mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); + + /* Stop module clock */ + for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { + mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis, + mstptbl[i].s_ena); + mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis, + mstptbl[i].r_ena); + } +} diff --git a/board/renesas/rsk7203/Kconfig b/board/renesas/rsk7203/Kconfig new file mode 100644 index 0000000000..10b8786411 --- /dev/null +++ b/board/renesas/rsk7203/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RSK7203 + +config SYS_BOARD + default "rsk7203" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "rsk7203" + +endif diff --git a/board/renesas/rsk7203/MAINTAINERS b/board/renesas/rsk7203/MAINTAINERS new file mode 100644 index 0000000000..18d36634cf --- /dev/null +++ b/board/renesas/rsk7203/MAINTAINERS @@ -0,0 +1,7 @@ +RSK7203 BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/rsk7203/ +F: include/configs/rsk7203.h +F: configs/rsk7203_defconfig diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile index 13ffa4f8b5..16acfaf40a 100644 --- a/board/renesas/rsk7203/Makefile +++ b/board/renesas/rsk7203/Makefile @@ -6,25 +6,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).o - -OBJS := rsk7203.o -SOBJS := lowlevel_init.o - -LIB := $(addprefix $(obj),$(LIB)) -OBJS := $(addprefix $(obj),$(OBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := rsk7203.o +obj-y += lowlevel_init.o diff --git a/board/renesas/rsk7264/Kconfig b/board/renesas/rsk7264/Kconfig new file mode 100644 index 0000000000..755d2896fb --- /dev/null +++ b/board/renesas/rsk7264/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RSK7264 + +config SYS_BOARD + default "rsk7264" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "rsk7264" + +endif diff --git a/board/renesas/rsk7264/MAINTAINERS b/board/renesas/rsk7264/MAINTAINERS new file mode 100644 index 0000000000..f6202b70d9 --- /dev/null +++ b/board/renesas/rsk7264/MAINTAINERS @@ -0,0 +1,6 @@ +RSK7264 BOARD +M: Phil Edworthy +S: Maintained +F: board/renesas/rsk7264/ +F: include/configs/rsk7264.h +F: configs/rsk7264_defconfig diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile index 476de43069..7ada697c88 100644 --- a/board/renesas/rsk7264/Makefile +++ b/board/renesas/rsk7264/Makefile @@ -3,23 +3,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).o - -OBJS := rsk7264.o -SOBJS := lowlevel_init.o - -LIB := $(addprefix $(obj),$(LIB)) -OBJS := $(addprefix $(obj),$(OBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := rsk7264.o +obj-y += lowlevel_init.o diff --git a/board/renesas/rsk7269/Kconfig b/board/renesas/rsk7269/Kconfig new file mode 100644 index 0000000000..ab5cd0e38f --- /dev/null +++ b/board/renesas/rsk7269/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RSK7269 + +config SYS_BOARD + default "rsk7269" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "rsk7269" + +endif diff --git a/board/renesas/rsk7269/MAINTAINERS b/board/renesas/rsk7269/MAINTAINERS new file mode 100644 index 0000000000..698fbdb1df --- /dev/null +++ b/board/renesas/rsk7269/MAINTAINERS @@ -0,0 +1,6 @@ +RSK7269 BOARD +#M: - +S: Maintained +F: board/renesas/rsk7269/ +F: include/configs/rsk7269.h +F: configs/rsk7269_defconfig diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile index 1a015573d1..0f053d8fa6 100644 --- a/board/renesas/rsk7269/Makefile +++ b/board/renesas/rsk7269/Makefile @@ -4,23 +4,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).o - -OBJS := rsk7269.o -SOBJS := lowlevel_init.o - -LIB := $(addprefix $(obj),$(LIB)) -OBJS := $(addprefix $(obj),$(OBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := rsk7269.o +obj-y += lowlevel_init.o diff --git a/board/renesas/sh7752evb/Kconfig b/board/renesas/sh7752evb/Kconfig new file mode 100644 index 0000000000..7f40888336 --- /dev/null +++ b/board/renesas/sh7752evb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SH7752EVB + +config SYS_BOARD + default "sh7752evb" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "sh7752evb" + +endif diff --git a/board/renesas/sh7752evb/MAINTAINERS b/board/renesas/sh7752evb/MAINTAINERS new file mode 100644 index 0000000000..9840477d7d --- /dev/null +++ b/board/renesas/sh7752evb/MAINTAINERS @@ -0,0 +1,6 @@ +SH7752EVB BOARD +#M: - +S: Maintained +F: board/renesas/sh7752evb/ +F: include/configs/sh7752evb.h +F: configs/sh7752evb_defconfig diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile index 70009ec8fd..856af81385 100644 --- a/board/renesas/sh7752evb/Makefile +++ b/board/renesas/sh7752evb/Makefile @@ -3,21 +3,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sh7752evb.o spi-boot.o -SOBJS := lowlevel_init.o - -$(LIB): $(obj).depend $(COBJS) $(SOBJS) - $(call cmd_link_o_target, $(COBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sh7752evb.o spi-boot.o +obj-y += lowlevel_init.o diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c index 5eedbf8ce6..3aad532367 100644 --- a/board/renesas/sh7752evb/sh7752evb.c +++ b/board/renesas/sh7752evb/sh7752evb.c @@ -9,6 +9,7 @@ #include #include #include +#include #include int checkboard(void) diff --git a/board/renesas/sh7753evb/Kconfig b/board/renesas/sh7753evb/Kconfig new file mode 100644 index 0000000000..be889248a8 --- /dev/null +++ b/board/renesas/sh7753evb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SH7753EVB + +config SYS_BOARD + default "sh7753evb" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "sh7753evb" + +endif diff --git a/board/renesas/sh7753evb/MAINTAINERS b/board/renesas/sh7753evb/MAINTAINERS new file mode 100644 index 0000000000..b6c85eedab --- /dev/null +++ b/board/renesas/sh7753evb/MAINTAINERS @@ -0,0 +1,6 @@ +SH7753EVB BOARD +#M: - +S: Maintained +F: board/renesas/sh7753evb/ +F: include/configs/sh7753evb.h +F: configs/sh7753evb_defconfig diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile new file mode 100644 index 0000000000..f7c8e949f9 --- /dev/null +++ b/board/renesas/sh7753evb/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2012 Yoshihiro Shimoda +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := sh7753evb.o spi-boot.o +obj-y += lowlevel_init.o diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S new file mode 100644 index 0000000000..21987a51e8 --- /dev/null +++ b/board/renesas/sh7753evb/lowlevel_init.S @@ -0,0 +1,416 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +.macro or32, addr, data + mov.l \addr, r1 + mov.l \data, r0 + mov.l @r1, r2 + or r2, r0 + mov.l r0, @r1 +.endm + +.macro wait_DBCMD + mov.l DBWAIT_A, r0 + mov.l @r0, r1 +.endm + + .global lowlevel_init + .section .spiboot1.text + .align 2 + +lowlevel_init: + mov #0, r14 + mova 2f, r0 + mov.l PC_MASK, r1 + tst r0, r1 + bf 2f + + bra exit_pmb + nop + + .align 2 + +/* If CPU runs on SDRAM (PC=0x5???????) or not. */ +PC_MASK: .long 0x20000000 + +2: + mov #1, r14 + + mov.l EXPEVT_A, r0 + mov.l @r0, r0 + mov.l EXPEVT_POWER_ON_RESET, r1 + cmp/eq r0, r1 + bt 1f + + /* + * If EXPEVT value is manual reset or tlb multipul-hit, + * initialization of DBSC3 is not necessary. + */ + bra exit_ddr + nop + +1: + /*------- Reset -------*/ + write32 MRSTCR0_A, MRSTCR0_D + write32 MRSTCR1_A, MRSTCR1_D + + /* For Core Reset */ + mov.l DBACEN_A, r0 + mov.l @r0, r0 + cmp/eq #0, r0 + bt 3f + + /* + * If DBACEN == 1(DBSC was already enabled), we have to avoid the + * initialization of DDR3-SDRAM. + */ + bra exit_ddr + nop + +3: + /*------- DBSC3 -------*/ + /* oscillation stabilization time */ + wait_timer WAIT_OSC_TIME + + /* step 3 */ + write32 DBKIND_A, DBKIND_D + + /* step 4 */ + write32 DBCONF_A, DBCONF_D + write32 DBTR0_A, DBTR0_D + write32 DBTR1_A, DBTR1_D + write32 DBTR2_A, DBTR2_D + write32 DBTR3_A, DBTR3_D + write32 DBTR4_A, DBTR4_D + write32 DBTR5_A, DBTR5_D + write32 DBTR6_A, DBTR6_D + write32 DBTR7_A, DBTR7_D + write32 DBTR8_A, DBTR8_D + write32 DBTR9_A, DBTR9_D + write32 DBTR10_A, DBTR10_D + write32 DBTR11_A, DBTR11_D + write32 DBTR12_A, DBTR12_D + write32 DBTR13_A, DBTR13_D + write32 DBTR14_A, DBTR14_D + write32 DBTR15_A, DBTR15_D + write32 DBTR16_A, DBTR16_D + write32 DBTR17_A, DBTR17_D + write32 DBTR18_A, DBTR18_D + write32 DBTR19_A, DBTR19_D + write32 DBRNK0_A, DBRNK0_D + write32 DBADJ0_A, DBADJ0_D + write32 DBADJ2_A, DBADJ2_D + + /* step 5 */ + write32 DBCMD_A, DBCMD_RSTL_VAL + wait_timer WAIT_30US + + /* step 6 */ + write32 DBCMD_A, DBCMD_PDEN_VAL + + /* step 7 */ + write32 DBPDCNT3_A, DBPDCNT3_D + + /* step 8 */ + write32 DBPDCNT1_A, DBPDCNT1_D + write32 DBPDCNT2_A, DBPDCNT2_D + write32 DBPDLCK_A, DBPDLCK_D + write32 DBPDRGA_A, DBPDRGA_D + write32 DBPDRGD_A, DBPDRGD_D + + /* step 9 */ + wait_timer WAIT_30US + + /* step 10 */ + write32 DBPDCNT0_A, DBPDCNT0_D + + /* step 11 */ + wait_timer WAIT_30US + wait_timer WAIT_30US + + /* step 12 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + wait_DBCMD + + /* step 13 */ + write32 DBCMD_A, DBCMD_RSTH_VAL + wait_DBCMD + + /* step 14 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + + /* step 15 */ + write32 DBCMD_A, DBCMD_PDXT_VAL + + /* step 16 */ + write32 DBCMD_A, DBCMD_MRS2_VAL + + /* step 17 */ + write32 DBCMD_A, DBCMD_MRS3_VAL + + /* step 18 */ + write32 DBCMD_A, DBCMD_MRS1_VAL + + /* step 19 */ + write32 DBCMD_A, DBCMD_MRS0_VAL + write32 DBPDNCNF_A, DBPDNCNF_D + + /* step 20 */ + write32 DBCMD_A, DBCMD_ZQCL_VAL + + write32 DBCMD_A, DBCMD_REF_VAL + write32 DBCMD_A, DBCMD_REF_VAL + wait_DBCMD + + /* step 21 */ + write32 DBCALTR_A, DBCALTR_D + + /* step 22 */ + write32 DBRFCNF0_A, DBRFCNF0_D + write32 DBRFCNF1_A, DBRFCNF1_D + write32 DBRFCNF2_A, DBRFCNF2_D + + /* step 23 */ + write32 DBCALCNF_A, DBCALCNF_D + + /* step 24 */ + write32 DBRFEN_A, DBRFEN_D + write32 DBCMD_A, DBCMD_SRXT_VAL + + /* step 25 */ + write32 DBACEN_A, DBACEN_D + + /* step 26 */ + wait_DBCMD + + bra exit_ddr + nop + + .align 2 + +EXPEVT_A: .long 0xff000024 +EXPEVT_POWER_ON_RESET: .long 0x00000000 + +/*------- Reset -------*/ +MRSTCR0_A: .long 0xffd50030 +MRSTCR0_D: .long 0xfe1ffe7f +MRSTCR1_A: .long 0xffd50034 +MRSTCR1_D: .long 0xfff3ffff + +/*------- DBSC3 -------*/ +DBCMD_A: .long 0xfe800018 +DBKIND_A: .long 0xfe800020 +DBCONF_A: .long 0xfe800024 +DBTR0_A: .long 0xfe800040 +DBTR1_A: .long 0xfe800044 +DBTR2_A: .long 0xfe800048 +DBTR3_A: .long 0xfe800050 +DBTR4_A: .long 0xfe800054 +DBTR5_A: .long 0xfe800058 +DBTR6_A: .long 0xfe80005c +DBTR7_A: .long 0xfe800060 +DBTR8_A: .long 0xfe800064 +DBTR9_A: .long 0xfe800068 +DBTR10_A: .long 0xfe80006c +DBTR11_A: .long 0xfe800070 +DBTR12_A: .long 0xfe800074 +DBTR13_A: .long 0xfe800078 +DBTR14_A: .long 0xfe80007c +DBTR15_A: .long 0xfe800080 +DBTR16_A: .long 0xfe800084 +DBTR17_A: .long 0xfe800088 +DBTR18_A: .long 0xfe80008c +DBTR19_A: .long 0xfe800090 +DBRNK0_A: .long 0xfe800100 +DBPDCNT0_A: .long 0xfe800200 +DBPDCNT1_A: .long 0xfe800204 +DBPDCNT2_A: .long 0xfe800208 +DBPDCNT3_A: .long 0xfe80020c +DBPDLCK_A: .long 0xfe800280 +DBPDRGA_A: .long 0xfe800290 +DBPDRGD_A: .long 0xfe8002a0 +DBADJ0_A: .long 0xfe8000c0 +DBADJ2_A: .long 0xfe8000c8 +DBRFCNF0_A: .long 0xfe8000e0 +DBRFCNF1_A: .long 0xfe8000e4 +DBRFCNF2_A: .long 0xfe8000e8 +DBCALCNF_A: .long 0xfe8000f4 +DBRFEN_A: .long 0xfe800014 +DBACEN_A: .long 0xfe800010 +DBWAIT_A: .long 0xfe80001c +DBCALTR_A: .long 0xfe8000f8 +DBPDNCNF_A: .long 0xfe800180 + +WAIT_OSC_TIME: .long 6000 +WAIT_30US: .long 13333 + +DBCMD_RSTL_VAL: .long 0x20000000 +DBCMD_PDEN_VAL: .long 0x1000d73c +DBCMD_WAIT_VAL: .long 0x0000d73c +DBCMD_RSTH_VAL: .long 0x2100d73c +DBCMD_PDXT_VAL: .long 0x110000c8 +DBCMD_MRS0_VAL: .long 0x28000930 +DBCMD_MRS1_VAL: .long 0x29000004 +DBCMD_MRS2_VAL: .long 0x2a000008 +DBCMD_MRS3_VAL: .long 0x2b000000 +DBCMD_ZQCL_VAL: .long 0x03000200 +DBCMD_REF_VAL: .long 0x0c000000 +DBCMD_SRXT_VAL: .long 0x19000000 +DBKIND_D: .long 0x00000007 +DBCONF_D: .long 0x0f030a01 +DBTR0_D: .long 0x00000007 +DBTR1_D: .long 0x00000006 +DBTR2_D: .long 0x00000000 +DBTR3_D: .long 0x00000007 +DBTR4_D: .long 0x00070007 +DBTR5_D: .long 0x0000001b +DBTR6_D: .long 0x00000014 +DBTR7_D: .long 0x00000004 +DBTR8_D: .long 0x00000014 +DBTR9_D: .long 0x00000004 +DBTR10_D: .long 0x00000008 +DBTR11_D: .long 0x00000007 +DBTR12_D: .long 0x0000000e +DBTR13_D: .long 0x000000a0 +DBTR14_D: .long 0x00060006 +DBTR15_D: .long 0x00000003 +DBTR16_D: .long 0x00160002 +DBTR17_D: .long 0x000c0000 +DBTR18_D: .long 0x00000200 +DBTR19_D: .long 0x00000040 +DBRNK0_D: .long 0x00000001 +DBPDCNT0_D: .long 0x00000001 +DBPDCNT1_D: .long 0x00000001 +DBPDCNT2_D: .long 0x00000000 +DBPDCNT3_D: .long 0x00004010 +DBPDLCK_D: .long 0x0000a55a +DBPDRGA_D: .long 0x00000028 +DBPDRGD_D: .long 0x00017100 + +DBADJ0_D: .long 0x00010000 +DBADJ2_D: .long 0x18061806 +DBRFCNF0_D: .long 0x000001ff +DBRFCNF1_D: .long 0x00081040 +DBRFCNF2_D: .long 0x00000000 +DBCALCNF_D: .long 0x0000ffff +DBRFEN_D: .long 0x00000001 +DBACEN_D: .long 0x00000001 +DBCALTR_D: .long 0x08200820 +DBPDNCNF_D: .long 0x00000001 + + .align 2 +exit_ddr: +#if defined(CONFIG_SH_32BIT) + /*------- set PMB -------*/ + write32 PASCR_A, PASCR_29BIT_D + write32 MMUCR_A, MMUCR_D + + /***************************************************************** + * ent virt phys v sz c wt + * 0 0xa0000000 0x00000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + */ + write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D + write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D + + write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D + + write32 PASCR_A, PASCR_INIT + mov.l DUMMY_ADDR, r0 + icbi @r0 +#endif /* if defined(CONFIG_SH_32BIT) */ + +exit_pmb: + /* CPU is running on ILRAM? */ + mov r14, r0 + tst #1, r0 + bt 1f + + mov.l _stack_ilram, r15 + mov.l _spiboot_main, r0 +100: bsrf r0 + nop + + .align 2 +_spiboot_main: .long (spiboot_main - (100b + 4)) +_stack_ilram: .long 0xe5204000 + +1: + write32 CCR_A, CCR_D + + rts + nop + + .align 2 + +#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) +PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) +PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) +PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) +PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) +PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) +PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) +PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) +PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) +PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) +PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) +PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) +PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) +PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) + +PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_NOT_USE_D: .long 0x00000000 + +PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) + +/* ppn ub v s1 s0 c wt */ +PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) + +PASCR_A: .long 0xff000070 +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */ + +CCR_A: .long CCR +CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c new file mode 100644 index 0000000000..9f6494561c --- /dev/null +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +int checkboard(void) +{ + puts("BOARD: SH7753 EVB\n"); + + return 0; +} + +static void init_gpio(void) +{ + struct gpio_regs *gpio = GPIO_BASE; + struct sermux_regs *sermux = SERMUX_BASE; + + /* GPIO */ + writew(0x0000, &gpio->pacr); /* GETHER */ + writew(0x0001, &gpio->pbcr); /* INTC */ + writew(0x0000, &gpio->pccr); /* PWMU, INTC */ + writew(0x0000, &gpio->pdcr); /* SPI0 */ + writew(0xeaff, &gpio->pecr); /* GPIO */ + writew(0x0000, &gpio->pfcr); /* WDT */ + writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ + writew(0x0000, &gpio->phcr); /* SPI1 */ + writew(0x0000, &gpio->picr); /* SDHI */ + writew(0x0000, &gpio->pjcr); /* SCIF4 */ + writew(0x0003, &gpio->pkcr); /* SerMux */ + writew(0x0000, &gpio->plcr); /* SerMux */ + writew(0x0000, &gpio->pmcr); /* RIIC */ + writew(0x0000, &gpio->pncr); /* USB, SGPIO */ + writew(0x0000, &gpio->pocr); /* SGPIO */ + writew(0xd555, &gpio->pqcr); /* GPIO */ + writew(0x0000, &gpio->prcr); /* RIIC */ + writew(0x0000, &gpio->pscr); /* RIIC */ + writew(0x0000, &gpio->ptcr); /* STATUS */ + writeb(0x00, &gpio->pudr); + writew(0x5555, &gpio->pucr); /* Debug LED */ + writew(0x0000, &gpio->pvcr); /* RSPI */ + writew(0x0000, &gpio->pwcr); /* EVC */ + writew(0x0000, &gpio->pxcr); /* LBSC */ + writew(0x0000, &gpio->pycr); /* LBSC */ + writew(0x0000, &gpio->pzcr); /* eMMC */ + writew(0xfe00, &gpio->psel0); + writew(0x0000, &gpio->psel1); + writew(0x3000, &gpio->psel2); + writew(0xff00, &gpio->psel3); + writew(0x771f, &gpio->psel4); + writew(0x0ffc, &gpio->psel5); + writew(0x00ff, &gpio->psel6); + writew(0xfc00, &gpio->psel7); + + writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ +} + +static void init_usb_phy(void) +{ + struct usb_common_regs *common0 = USB0_COMMON_BASE; + struct usb_common_regs *common1 = USB1_COMMON_BASE; + struct usb0_phy_regs *phy = USB0_PHY_BASE; + struct usb1_port_regs *port = USB1_PORT_BASE; + struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; + + writew(0x0100, &phy->reset); /* set reset */ + /* port0 = USB0, port1 = USB1 */ + writew(0x0002, &phy->portsel); + writel(0x0001, &port->port1sel); /* port1 = Host */ + writew(0x0111, &phy->reset); /* clear reset */ + + writew(0x4000, &common0->suspmode); + writew(0x4000, &common1->suspmode); + +#if defined(__LITTLE_ENDIAN) + writel(0x00000000, &align->ehcidatac); + writel(0x00000000, &align->ohcidatac); +#endif +} + +static void init_gether_mdio(void) +{ + struct gpio_regs *gpio = GPIO_BASE; + + writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); + writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ +} + +static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) +{ + struct ether_mac_regs *ether; + unsigned char mac[6]; + unsigned long val; + + eth_parse_enetaddr(mac_string, mac); + + if (!channel) + ether = GETHER0_MAC_BASE; + else + ether = GETHER1_MAC_BASE; + + val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; + writel(val, ðer->mahr); + val = (mac[4] << 8) | mac[5]; + writel(val, ðer->malr); +} + +/***************************************************************** + * This PMB must be set on this timing. The lowlevel_init is run on + * Area 0(phys 0x00000000), so we have to map it. + * + * The new PMB table is following: + * ent virt phys v sz c wt + * 0 0xa0000000 0x40000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 2 0xb0000000 0x50000000 1 128M 0 1 + * 3 0xb8000000 0x58000000 1 128M 0 1 + * 4 0x80000000 0x40000000 1 128M 1 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + * 6 0x90000000 0x50000000 1 128M 1 1 + * 7 0x98000000 0x58000000 1 128M 1 1 + */ +static void set_pmb_on_board_init(void) +{ + struct mmu_regs *mmu = MMU_BASE; + + /* clear ITLB */ + writel(0x00000004, &mmu->mmucr); + + /* delete PMB for SPIBOOT */ + writel(0, PMB_ADDR_BASE(0)); + writel(0, PMB_DATA_BASE(0)); + + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ + /* ppn ub v s1 s0 c wt */ + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); + writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); + writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); + writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); + writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); + writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); + writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); + writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); + writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); +} + +int board_init(void) +{ + struct gether_control_regs *gether = GETHER_CONTROL_BASE; + + init_gpio(); + set_pmb_on_board_init(); + + /* Sets TXnDLY to B'010 */ + writel(0x00000202, &gether->gbecont); + + init_usb_phy(); + init_gether_mdio(); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + struct gpio_regs *gpio = GPIO_BASE; + + writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); + writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ + udelay(1); + writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ + udelay(200); + + return mmcif_mmc_init(); +} + +static int get_sh_eth_mac_raw(unsigned char *buf, int size) +{ + struct spi_flash *spi; + int ret; + + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (spi == NULL) { + printf("%s: spi_flash probe failed.\n", __func__); + return 1; + } + + ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf); + if (ret) { + printf("%s: spi_flash read failed.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + return 0; +} + +static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) +{ + memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)], + SH7753EVB_ETHERNET_MAC_SIZE); + mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ + + return 0; +} + +static void init_ethernet_mac(void) +{ + char mac_string[64]; + char env_string[64]; + int i; + unsigned char *buf; + + buf = malloc(256); + if (!buf) { + printf("%s: malloc failed.\n", __func__); + return; + } + get_sh_eth_mac_raw(buf, 256); + + /* Gigabit Ethernet */ + for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + if (i == 0) + setenv("ethaddr", mac_string); + else { + sprintf(env_string, "eth%daddr", i); + setenv(env_string, mac_string); + } + set_mac_to_sh_giga_eth_register(i, mac_string); + } + + free(buf); +} + +int board_late_init(void) +{ + init_ethernet_mac(); + + return 0; +} + +int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i, ret; + char mac_string[256]; + struct spi_flash *spi; + unsigned char *buf; + + if (argc != 3) { + buf = malloc(256); + if (!buf) { + printf("%s: malloc failed.\n", __func__); + return 1; + } + + get_sh_eth_mac_raw(buf, 256); + + /* print current MAC address */ + for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + printf("GETHERC ch%d = %s\n", i, mac_string); + } + free(buf); + return 0; + } + + /* new setting */ + memset(mac_string, 0xff, sizeof(mac_string)); + sprintf(mac_string, "%s\t%s", + argv[1], argv[2]); + + /* write MAC data to SPI rom */ + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!spi) { + printf("%s: spi_flash probe failed.\n", __func__); + return 1; + } + + ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, + SH7753EVB_SPI_SECTOR_SIZE); + if (ret) { + printf("%s: spi_flash erase failed.\n", __func__); + return 1; + } + + ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, + sizeof(mac_string), mac_string); + if (ret) { + printf("%s: spi_flash write failed.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + puts("The writing of the MAC address to SPI ROM was completed.\n"); + + return 0; +} + +U_BOOT_CMD( + write_mac, 3, 1, do_write_mac, + "write MAC address for GETHERC", + "[GETHERC ch0] [GETHERC ch1]\n" +); diff --git a/board/renesas/sh7753evb/spi-boot.c b/board/renesas/sh7753evb/spi-boot.c new file mode 100644 index 0000000000..21903d9c7b --- /dev/null +++ b/board/renesas/sh7753evb/spi-boot.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define CONFIG_SPI_ADDR 0x00000000 +#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000) +#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE) + +#define SPIWDMADR 0xFE001018 +#define SPIWDMCNTR 0xFE001020 +#define SPIDMCOR 0xFE001028 +#define SPIDMINTSR 0xFE001188 +#define SPIDMINTMR 0xFE001190 + +#define SPIDMINTSR_DMEND 0x00000004 + +#define TBR 0xFE002000 +#define RBR 0xFE002000 + +#define CR1 0xFE002008 +#define CR2 0xFE002010 +#define CR3 0xFE002018 +#define CR4 0xFE002020 +#define CR7 0xFE002038 +#define CR8 0xFE002040 + +/* CR1 */ +#define SPI_TBE 0x80 +#define SPI_TBF 0x40 +#define SPI_RBE 0x20 +#define SPI_RBF 0x10 +#define SPI_PFONRD 0x08 +#define SPI_SSDB 0x04 +#define SPI_SSD 0x02 +#define SPI_SSA 0x01 + +/* CR2 */ +#define SPI_RSTF 0x80 +#define SPI_LOOPBK 0x40 +#define SPI_CPOL 0x20 +#define SPI_CPHA 0x10 +#define SPI_L1M0 0x08 + +/* CR4 */ +#define SPI_TBEI 0x80 +#define SPI_TBFI 0x40 +#define SPI_RBEI 0x20 +#define SPI_RBFI 0x10 +#define SPI_SpiS0 0x02 +#define SPI_SSS 0x01 + +/* CR7 */ +#define CR7_IDX_OR12 0x12 +#define OR12_ADDR32 0x00000001 + +#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val +#define spi_read(addr) (*(volatile unsigned long *)(addr)) + +/* M25P80 */ +#define M25_READ 0x03 +#define M25_READ_4BYTE 0x13 + +extern void bss_start(void); + +#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) +static void __uses_spiboot2 spi_reset(void) +{ + int timeout = 0x00100000; + + /* Make sure the last transaction is finalized */ + spi_write(0x00, CR3); + spi_write(0x02, CR1); + while (!(spi_read(CR4) & SPI_SpiS0)) { + if (timeout-- < 0) + break; + } + spi_write(0x00, CR1); + + spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ + spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); + + spi_write(0, SPIDMCOR); +} + +static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, + unsigned long len) +{ + spi_write(CR7_IDX_OR12, CR7); + if (spi_read(CR8) & OR12_ADDR32) { + /* 4-bytes address mode */ + spi_write(M25_READ_4BYTE, TBR); + spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */ + } else { + /* 3-bytes address mode */ + spi_write(M25_READ, TBR); + } + spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */ + spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */ + spi_write(addr & 0xFF, TBR); /* ADDR7-0 */ + + spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); + spi_write((unsigned long)buf, SPIWDMADR); + spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); + spi_write(1, SPIDMCOR); + + spi_write(0xff, CR3); + spi_write(spi_read(CR1) | SPI_SSDB, CR1); + spi_write(spi_read(CR1) | SPI_SSA, CR1); + + while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) + ; + + /* Nagate SP0-SS0 */ + spi_write(0, CR1); +} + +void __uses_spiboot2 spiboot_main(void) +{ + /* + * This code rounds len up for SPIWDMCNTR. We should set it to 0 in + * lower 5-bits. + */ + void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; + volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0; + + spi_reset(); + spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len); + + _start(); +} diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds new file mode 100644 index 0000000000..053df642ea --- /dev/null +++ b/board/renesas/sh7753evb/u-boot.lds @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu + * + * Copyright (C) 2012 + * Yoshihiro Shimoda + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + KEEP(arch/sh/cpu/sh4/start.o (.text)) + *(.spiboot1.text) + *(.spiboot2.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss (NOLOAD) : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (__bss_end = .); +} diff --git a/board/renesas/sh7757lcr/Kconfig b/board/renesas/sh7757lcr/Kconfig new file mode 100644 index 0000000000..3fba80ddca --- /dev/null +++ b/board/renesas/sh7757lcr/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SH7757LCR + +config SYS_BOARD + default "sh7757lcr" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "sh7757lcr" + +endif diff --git a/board/renesas/sh7757lcr/MAINTAINERS b/board/renesas/sh7757lcr/MAINTAINERS new file mode 100644 index 0000000000..20aca678a6 --- /dev/null +++ b/board/renesas/sh7757lcr/MAINTAINERS @@ -0,0 +1,6 @@ +SH7757LCR BOARD +#M: - +S: Maintained +F: board/renesas/sh7757lcr/ +F: include/configs/sh7757lcr.h +F: configs/sh7757lcr_defconfig diff --git a/board/renesas/sh7757lcr/Makefile b/board/renesas/sh7757lcr/Makefile index 4bb6068a9d..1fa3992e1d 100644 --- a/board/renesas/sh7757lcr/Makefile +++ b/board/renesas/sh7757lcr/Makefile @@ -3,21 +3,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sh7757lcr.o spi-boot.o -SOBJS := lowlevel_init.o - -$(LIB): $(obj).depend $(COBJS) $(SOBJS) - $(call cmd_link_o_target, $(COBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sh7757lcr.o spi-boot.o +obj-y += lowlevel_init.o diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c index 1464f48b43..ddcf275f6e 100644 --- a/board/renesas/sh7757lcr/sh7757lcr.c +++ b/board/renesas/sh7757lcr/sh7757lcr.c @@ -9,6 +9,7 @@ #include #include #include +#include #include int checkboard(void) diff --git a/board/renesas/sh7763rdp/Kconfig b/board/renesas/sh7763rdp/Kconfig new file mode 100644 index 0000000000..101d2b5a32 --- /dev/null +++ b/board/renesas/sh7763rdp/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SH7763RDP + +config SYS_BOARD + default "sh7763rdp" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "sh7763rdp" + +endif diff --git a/board/renesas/sh7763rdp/MAINTAINERS b/board/renesas/sh7763rdp/MAINTAINERS new file mode 100644 index 0000000000..6ee8f9f87b --- /dev/null +++ b/board/renesas/sh7763rdp/MAINTAINERS @@ -0,0 +1,7 @@ +SH7763RDP BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/sh7763rdp/ +F: include/configs/sh7763rdp.h +F: configs/sh7763rdp_defconfig diff --git a/board/renesas/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile index b311bcd032..cbf38bbc18 100644 --- a/board/renesas/sh7763rdp/Makefile +++ b/board/renesas/sh7763rdp/Makefile @@ -8,25 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sh7763rdp.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sh7763rdp.o +obj-y += lowlevel_init.o diff --git a/board/renesas/sh7785lcr/Kconfig b/board/renesas/sh7785lcr/Kconfig new file mode 100644 index 0000000000..e204c76ef5 --- /dev/null +++ b/board/renesas/sh7785lcr/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SH7785LCR + +config SYS_BOARD + default "sh7785lcr" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "sh7785lcr" + +endif diff --git a/board/renesas/sh7785lcr/MAINTAINERS b/board/renesas/sh7785lcr/MAINTAINERS new file mode 100644 index 0000000000..17578e036a --- /dev/null +++ b/board/renesas/sh7785lcr/MAINTAINERS @@ -0,0 +1,7 @@ +SH7785LCR BOARD +#M: - +S: Maintained +F: board/renesas/sh7785lcr/ +F: include/configs/sh7785lcr.h +F: configs/sh7785lcr_defconfig +F: configs/sh7785lcr_32bit_defconfig diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile index e577d566a9..e8cfb053ce 100644 --- a/board/renesas/sh7785lcr/Makefile +++ b/board/renesas/sh7785lcr/Makefile @@ -3,25 +3,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o +obj-y += lowlevel_init.o diff --git a/board/ronetix/pm9261/Kconfig b/board/ronetix/pm9261/Kconfig new file mode 100644 index 0000000000..a4934c582e --- /dev/null +++ b/board/ronetix/pm9261/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PM9261 + +config SYS_BOARD + default "pm9261" + +config SYS_VENDOR + default "ronetix" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "pm9261" + +endif diff --git a/board/ronetix/pm9261/MAINTAINERS b/board/ronetix/pm9261/MAINTAINERS new file mode 100644 index 0000000000..a09b6c0734 --- /dev/null +++ b/board/ronetix/pm9261/MAINTAINERS @@ -0,0 +1,6 @@ +PM9261 BOARD +M: Ilko Iliev +S: Maintained +F: board/ronetix/pm9261/ +F: include/configs/pm9261.h +F: configs/pm9261_defconfig diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile index f627eaa383..3860283a3b 100644 --- a/board/ronetix/pm9261/Makefile +++ b/board/ronetix/pm9261/Makefile @@ -10,26 +10,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += led.o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += pm9261.o +obj-y += led.o +obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index 223a516179..cc4c2a072b 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -8,9 +8,9 @@ */ #include +#include #include #include -#include void coloured_LED_init(void) { @@ -19,11 +19,11 @@ void coloured_LED_init(void) /* Enable clock */ writel(1 << ATMEL_ID_PIOC, &pmc->pcer); - at91_set_pio_output(CONFIG_RED_LED, 1); - at91_set_pio_output(CONFIG_GREEN_LED, 1); - at91_set_pio_output(CONFIG_YELLOW_LED, 1); + gpio_direction_output(CONFIG_RED_LED, 1); + gpio_direction_output(CONFIG_GREEN_LED, 1); + gpio_direction_output(CONFIG_YELLOW_LED, 1); - at91_set_pio_value(CONFIG_RED_LED, 0); - at91_set_pio_value(CONFIG_GREEN_LED, 1); - at91_set_pio_value(CONFIG_YELLOW_LED, 1); + gpio_set_value(CONFIG_RED_LED, 0); + gpio_set_value(CONFIG_GREEN_LED, 1); + gpio_set_value(CONFIG_YELLOW_LED, 1); } diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index a2a569b0cd..1f7679a240 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -9,8 +9,9 @@ */ #include -#include +#include #include +#include #include #include #include @@ -73,10 +74,10 @@ static void pm9261_nand_hw_init(void) &pmc->pcer); /* Configure RDY/BSY */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ @@ -116,20 +117,20 @@ static void pm9261_dm9000_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/ronetix/pm9263/Kconfig b/board/ronetix/pm9263/Kconfig new file mode 100644 index 0000000000..339a6ea169 --- /dev/null +++ b/board/ronetix/pm9263/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PM9263 + +config SYS_BOARD + default "pm9263" + +config SYS_VENDOR + default "ronetix" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "pm9263" + +endif diff --git a/board/ronetix/pm9263/MAINTAINERS b/board/ronetix/pm9263/MAINTAINERS new file mode 100644 index 0000000000..f26e82acee --- /dev/null +++ b/board/ronetix/pm9263/MAINTAINERS @@ -0,0 +1,6 @@ +PM9263 BOARD +M: Ilko Iliev +S: Maintained +F: board/ronetix/pm9263/ +F: include/configs/pm9263.h +F: configs/pm9263_defconfig diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile index 7cb6f0fba5..43ea599c4f 100644 --- a/board/ronetix/pm9263/Makefile +++ b/board/ronetix/pm9263/Makefile @@ -10,26 +10,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += pm9263.o -COBJS-y += led.o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += pm9263.o +obj-y += led.o +obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c index 44e3430900..bfc2310b0e 100644 --- a/board/ronetix/pm9263/led.c +++ b/board/ronetix/pm9263/led.c @@ -8,9 +8,9 @@ */ #include +#include #include #include -#include void coloured_LED_init(void) { @@ -19,9 +19,9 @@ void coloured_LED_init(void) /* Enable clock */ writel(1 << ATMEL_ID_PIOB, &pmc->pcer); - at91_set_pio_output(CONFIG_RED_LED, 1); - at91_set_pio_output(CONFIG_GREEN_LED, 1); + gpio_direction_output(CONFIG_RED_LED, 1); + gpio_direction_output(CONFIG_GREEN_LED, 1); - at91_set_pio_value(CONFIG_RED_LED, 0); - at91_set_pio_value(CONFIG_GREEN_LED, 1); + gpio_set_value(CONFIG_RED_LED, 0); + gpio_set_value(CONFIG_GREEN_LED, 1); } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 48eba99d00..1b00f08835 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -9,8 +9,9 @@ */ #include -#include +#include #include +#include #include #include #include @@ -67,10 +68,10 @@ static void pm9263_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif @@ -114,20 +115,20 @@ static void pm9263_macb_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/ronetix/pm9g45/Kconfig b/board/ronetix/pm9g45/Kconfig new file mode 100644 index 0000000000..65fc5c4838 --- /dev/null +++ b/board/ronetix/pm9g45/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PM9G45 + +config SYS_BOARD + default "pm9g45" + +config SYS_VENDOR + default "ronetix" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "pm9g45" + +endif diff --git a/board/ronetix/pm9g45/MAINTAINERS b/board/ronetix/pm9g45/MAINTAINERS new file mode 100644 index 0000000000..255a357fa9 --- /dev/null +++ b/board/ronetix/pm9g45/MAINTAINERS @@ -0,0 +1,6 @@ +PM9G45 BOARD +M: Ilko Iliev +S: Maintained +F: board/ronetix/pm9g45/ +F: include/configs/pm9g45.h +F: configs/pm9g45_defconfig diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile index 2810fcf8d7..0a00279900 100644 --- a/board/ronetix/pm9g45/Makefile +++ b/board/ronetix/pm9g45/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += pm9g45.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += pm9g45.o diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 5bb5a3c102..15aa4acd11 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -12,8 +12,9 @@ */ #include -#include +#include #include +#include #include #include #include @@ -66,11 +67,11 @@ static void pm9g45_nand_hw_init(void) #ifdef CONFIG_SYS_NAND_READY_PIN /* Configure RDY/BSY */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); #endif /* Enable NandFlash */ - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile deleted file mode 100644 index 3c08959dc5..0000000000 --- a/board/rpxsuper/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := rpxsuper.o flash.o mii_phy.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c deleted file mode 100644 index 24bcd7c0a3..0000000000 --- a/board/rpxsuper/flash.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD 29F080B devices - * Added support for 64bit and AMD 29DL323B - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define RD_SWP32(x) in_le32((volatile u32*)x) - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* for now, only support the 4 MB Flash SIMM */ - (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, - &flash_info[0]); - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#ifndef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD "); - break; - case (FUJ_MANUFACT & FLASH_VENDMASK): - printf ("FUJITSU "); - break; - case (SST_MANUFACT & FLASH_VENDMASK): - printf ("SST "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_DL323B & FLASH_TYPEMASK): - printf("AM29DL323B (32 MBit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor[2], devid[2]; - ulong base = (ulong)addr; - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0] = 0xf0f0f0f0; - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x90909090; - addr[1] = 0xf0f0f0f0; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x90909090; - udelay (1000); - - vendor[0] = RD_SWP32(&addr[0]); - vendor[1] = RD_SWP32(&addr[1]); - if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) { - info->size = 0; - goto out; - } - - devid[0] = RD_SWP32(&addr[2]); - devid[1] = RD_SWP32(&addr[3]); - - if (devid[0] == AMD_ID_DL323B) { - /* - * we have 2 Banks - * Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte - * Bank 2 (48 Sectors): 23-70=64kbyte - */ - info->flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_DL323B & FLASH_TYPEMASK); - info->sector_count = 71; - info->size = 4 * (8 * 8 + 63 * 64) * 1024; - } - else { - info->size = 0; - goto out; - } - - /* set up sector start address table */ - for (i = 0; i < 8; i++) { - info->start[i] = base + (i * 0x8000); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address */ - addr = (volatile unsigned long *)(info->start[i]); - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x90909090; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x90909090; - udelay (1000); - base = RD_SWP32(&addr[4]); - base |= RD_SWP32(&addr[5]); - info->protect[i] = base & 0x00010001 ? 1 : 0; - } - addr = (vu_long*)info->start[0]; - -out: - /* reset command */ - addr[0] = 0xf0f0f0f0; - addr[1] = 0xf0f0f0f0; - - return info->size; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x80808080; - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x80808080; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - addr[1] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ( (addr[0] & 0x80808080) != 0x80808080 || - (addr[1] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - addr[1] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if ((dest & 0x00000004) == 0) { - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0xA0A0A0A0; - } - else { - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0xA0A0A0A0; - } - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c deleted file mode 100644 index 12e23f487f..0000000000 --- a/board/rpxsuper/mii_phy.c +++ /dev/null @@ -1,107 +0,0 @@ -#include -#include -#include "rpxsuper.h" - -#define MII_MDIO 0x01 -#define MII_MDCK 0x02 -#define MII_MDIR 0x04 - -void -mii_discover_phy(void) -{ - int known; - unsigned short phy_reg; - unsigned long phy_id; - - known = 0; - printf("Discovering phy @ 0: "); - phy_id = mii_phy_read(2) << 16; - phy_id |= mii_phy_read(3); - if ((phy_id & 0xFFFFFC00) == 0x00137800) { - printf("Level One "); - if ((phy_id & 0x000003F0) == 0xE0) { - printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); - known = 1; - } - else printf("unknown type\n"); - } - else printf("unknown OUI = 0x%08lX\n", phy_id); - - phy_reg = mii_phy_read(1); - if (!(phy_reg & 0x0004)) printf("Link is down\n"); - if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); - if (phy_reg & 0x0002) printf("Jabber condition detected\n"); - if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); - - if (known) { - phy_reg = mii_phy_read(17); - if (phy_reg & 0x0400) - printf("Phy operating at %d MBit/s in %s-duplex mode\n", - phy_reg & 0x4000 ? 100 : 10, - phy_reg & 0x0200 ? "full" : "half"); - else - printf("bad link!!\n"); -/* -left off: no link, green 100MBit, yellow 10MBit -right off: no activity, green full-duplex, yellow half-duplex -*/ - mii_phy_write(20, 0x0452); - } -} - -unsigned short -mii_phy_read(unsigned short reg) -{ - int i; - unsigned short tmp, val = 0, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x6002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - regs->bcsr4 |= MII_MDIR; - for (i = 0; i < 16; i++) { - val <<= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); - if (regs->bcsr4 & MII_MDIO) val |= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); - } - return val; -} - -void -mii_phy_write(unsigned short reg, unsigned short val) -{ - int i; - unsigned short tmp, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x5002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (val & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - val <<= 1; - } -} diff --git a/board/rpxsuper/readme b/board/rpxsuper/readme deleted file mode 100644 index 21267bdd8c..0000000000 --- a/board/rpxsuper/readme +++ /dev/null @@ -1,30 +0,0 @@ -Hi, - -so this is the port to the Embedded Planet RPX Super Board. - -ATTENTION -This code is only tested on the AY-Version, which is an early release with some -hardware bugs. The main problem is that this board uses the default Hard Reset -Configuration Word and not the 4 bytes located at start of FLASH because at -0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be -carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low -byte. - -The icache can only manually be enabled after reset. -The FLASH and main SDRAM is working with icache enabled. -The local SDRAM can only be used as data memory when icache is enabled. -If U-Boot runs in local SDRAM, TFTP does not work. -The functions in mii_phy.c are all working. Call mii_phy_discover() out of -eth_init() and solve the linker error. -I2C, RTC/NVRAM and PCMCIA are not working yet. - -TODO -The 32MB local SDRAM is working but not shown in the startup messages of -U-Boot. If you locate U-Boot or any other program to this area it won't run. -Turning the ichache off does not solve this problem. - -As I won't buy another RPX Super there might be some little work to do for you -getting this U-Boot port running on the final board. - - -frank.morauf@salzbrenner.com diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c deleted file mode 100644 index dc558707fa..0000000000 --- a/board/rpxsuper/rpxsuper.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "rpxsuper.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ - /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Setup CS4 to enable the Board Control/Status registers. - * Otherwise the smcs won't work. -*/ -int board_early_init_f (void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */ - regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */ - return 0; -} - -void -reset_phy(void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - regs->bcsr4 = 0xC3; -} - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - printf ("Board: Embedded Planet RPX Super, Revision %d\n", - regs->bcsr0 >> 4); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr; - ulong psdmr, lsdmr, bcr; - long size = 0; - int i; - - psdmr = CONFIG_SYS_PSDMR; - lsdmr = CONFIG_SYS_LSDMR; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - size = CONFIG_SYS_SDRAM0_SIZE; - bcr = immap->im_siu_conf.sc_bcr; - immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE); - memctl->memc_psrt = CONFIG_SYS_PSRT; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - immap->im_siu_conf.sc_bcr = bcr; - -#ifndef CONFIG_SYS_RAMBOOT -/* size += CONFIG_SYS_SDRAM1_SIZE; */ - ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE); - memctl->memc_lsrt = CONFIG_SYS_LSRT; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; -#endif - - /* return total ram size */ - return (size * 1024 * 1024); -} diff --git a/board/rpxsuper/rpxsuper.h b/board/rpxsuper/rpxsuper.h deleted file mode 100644 index af31060a7b..0000000000 --- a/board/rpxsuper/rpxsuper.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __RPX8260_H__ -#define __RPX8260_H__ - -typedef struct tt_rpx_regs -{ - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; - volatile unsigned char bcsr6; - volatile unsigned char bcsr7; - volatile unsigned char bcsr8; - volatile unsigned char bcsr9; - volatile unsigned char bcsr10; - volatile unsigned char bcsr11; - volatile unsigned char bcsr12; - volatile unsigned char bcsr13; - volatile unsigned char bcsr14; - volatile unsigned char bcsr15; -} t_rpx_regs; -typedef t_rpx_regs* tp_rpx_regs; - -#endif diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile deleted file mode 100644 index 8799b50b0a..0000000000 --- a/board/rsdproto/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := rsdproto.o flash.o -SOBJS := flash_asm.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c deleted file mode 100644 index 37326d587a..0000000000 --- a/board/rsdproto/flash.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AM290[48]0B devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* flash hardware ids */ -#define VENDOR_AMD 0x0001 -#define AMD_29DL323C_B 0x2253 - -/* Define this to include autoselect sequence in flash_init(). Does NOT - * work when executing from flash itself, so this should be turned - * on only when debugging the RAM version. - */ -#undef WITH_AUTOSELECT - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if 1 -#define D(x) -#else -#define D(x) printf x -#endif - -/*----------------------------------------------------------------------- - * Functions - */ - -static unsigned char write_ull(flash_info_t *info, - unsigned long address, - volatile unsigned long long data); - -/* from flash_asm.S */ -extern void ull_write(unsigned long long volatile *address, - unsigned long long volatile *data); -extern void ull_read(unsigned long long volatile *address, - unsigned long long volatile *data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong addr; - -#ifdef WITH_AUTOSELECT - { - unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH; - unsigned long long f_command, vendor, device; - /* Perform Autoselect */ - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0090009000900090ULL; - ull_write(&f_addr[0x555], &f_command); - ull_read(&f_addr[0], &vendor); - vendor &= 0xffff; - ull_read(&f_addr[1], &device); - device &= 0xffff; - f_command = 0x00F000F000F000F0ULL; - ull_write(&f_addr[0x555], &f_command); - if (vendor != VENDOR_AMD || device != AMD_29DL323C_B) - return 0; - } -#endif - - /* Init: no FLASHes known */ - for (i=0; i= PHYS_FLASH - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[1]); -#endif - - return flash_info[0].size + flash_info[1].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id >> 16) { - case VENDOR_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_29DL323C_B: - printf ("AM29DL323CB (32 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start; - unsigned long long volatile *f_addr; - unsigned long long volatile f_command; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0080008000800080ULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (l_sect = -1, sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - - f_addr = - (unsigned long long *)(info->start[sect]); - f_command = 0x0030003000300030ULL; - ull_write(f_addr, &f_command); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - do - { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) - { /* write reset command, command address is unimportant */ - /* this command turns the flash back to read mode */ - f_addr = - (unsigned long long *)(info->start[l_sect]); - f_command = 0x00F000F000F000F0ULL; - ull_write(f_addr, &f_command); - printf (" timeout\n"); - return 1; - } - } while(*f_addr != 0xFFFFFFFFFFFFFFFFULL); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - unsigned long cp, wp; - unsigned long long data; - int i, l, rc; - - wp = (addr & ~7); /* get lower long long aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<8; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_ull(info, wp, data)) != 0) { - return rc; - } - wp += 4; - } - - /* - * handle long long aligned part - */ - while (cnt >= 8) { - data = 0; - for (i=0; i<8; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_ull(info, wp, data)) != 0) { - return rc; - } - wp += 8; - cnt -= 8; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<8; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return write_ull(info, wp, data); -} - -/*--------------------------------------------------------------------------- -* -* FUNCTION NAME: write_ull -* -* DESCRIPTION: writes 8 bytes to flash -* -* EXTERNAL EFFECT: nothing -* -* PARAMETERS: 32 bit long pointer to address, 64 bit long pointer to data -* -* RETURNS: 0 if OK, 1 if timeout, 4 if parameter error -*--------------------------------------------------------------------------*/ - -static unsigned char write_ull(flash_info_t *info, - unsigned long address, - volatile unsigned long long data) -{ - static unsigned long long f_command; - static unsigned long long *f_addr; - ulong start; - - /* address muss be 8-aligned! */ - if (address & 0x7) - return ERR_ALIGN; - - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x00A000A000A000A0ULL; - ull_write(&f_addr[0x555], &f_command); - - f_addr = (unsigned long long *)address; - f_command = data; - ull_write(f_addr, &f_command); - - start = get_timer (0); - do - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - { - /* write reset command, command address is unimportant */ - /* this command turns the flash back to read mode */ - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00F000F000F000F0ULL; - ull_write(f_addr, &f_command); - return ERR_TIMOUT; - } - } while(*((unsigned long long *)address) != data); - - return 0; -} diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S deleted file mode 100644 index 557cac0279..0000000000 --- a/board/rsdproto/flash_asm.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * -*- mode:c -*- - * - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * void ull_write(unsigned long long volatile *address, - * unsigned long long volatile *data) - * r3 = address - * r4 = data - * - * void ull_read(unsigned long long volatile *address, - * unsigned long long volatile *data) - * r3 = address - * r4 = data - * - * Uses the floating point unit to read and write 64 bit wide - * data (unsigned long long) on the 60x bus. This is necessary - * because all 4 flash chips use the /WE line from byte lane 0 - * - * IMPORTANT: data should always be 8-aligned, otherwise an exception will - * occur. - */ - -#include -#include - - .globl ull_write -ull_write: - lfd 0,0(r4) - stfd 0,0(r3) - blr - - .globl ull_read -ull_read: - lfd 0, 0(r3) - stfd 0, 0(r4) - blr diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c deleted file mode 100644 index 1e85c2710d..0000000000 --- a/board/rsdproto/rsdproto.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* define to initialise the SDRAM on the local bus */ -#undef INIT_LOCAL_BUS_SDRAM - -/* I2C Bus adresses for PPC & Protocol board */ -#define PPC8260_I2C_ADR 0x30 /*(0)011.0000 */ -#define LM84_PPC_I2C_ADR 0x2A /*(0)010.1010 */ -#define LM84_SHARC_I2C_ADR 0x29 /*(0)010.1001 */ -#define VIRTEX_I2C_ADR 0x25 /*(0)010.0101 */ -#define X24645_PPC_I2C_ADR 0x00 /*(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */ -#define RS5C372_PPC_I2C_ADR 0x32 /*(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!! */ - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, - /* PA29 */ { 0, 0, 0, 0, 0, 0 }, - /* PA28 */ { 0, 0, 0, 0, 0, 0 }, - /* PA27 */ { 0, 0, 0, 0, 0, 0 }, - /* PA26 */ { 0, 0, 0, 0, 0, 0 }, - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, - /* PA21 */ { 0, 0, 0, 0, 0, 0 }, - /* PA20 */ { 0, 0, 0, 0, 0, 0 }, - /* PA19 */ { 0, 0, 0, 0, 0, 0 }, - /* PA18 */ { 0, 0, 0, 0, 0, 0 }, - /* PA17 */ { 0, 0, 0, 0, 0, 0 }, - /* PA16 */ { 0, 0, 0, 0, 0, 0 }, - /* PA15 */ { 0, 0, 0, 0, 0, 0 }, - /* PA14 */ { 0, 0, 0, 0, 0, 0 }, - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, - /* PA9 */ { 0, 0, 0, 0, 0, 0 }, - /* PA8 */ { 0, 0, 0, 0, 0, 0 }, - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, - /* PA0 */ { 0, 0, 0, 0, 0, 0 } - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, - /* PC0 */ { 0, 0, 0, 0, 0, 0 } - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -struct tm { - unsigned int tm_sec; - unsigned int tm_min; - unsigned int tm_hour; - unsigned int tm_wday; - unsigned int tm_mday; - unsigned int tm_mon; - unsigned int tm_year; -}; - -void read_RS5C372_time (struct tm *timedate) -{ - unsigned char buffer[8]; - - if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { - timedate->tm_sec = bcd2bin (buffer[0]); - timedate->tm_min = bcd2bin (buffer[1]); - timedate->tm_hour = bcd2bin (buffer[2]); - timedate->tm_wday = bcd2bin (buffer[3]); - timedate->tm_mday = bcd2bin (buffer[4]); - timedate->tm_mon = bcd2bin (buffer[5]); - timedate->tm_year = bcd2bin (buffer[6]) + 2000; - } else { - /*printf("i2c error %02x\n", rc); */ - memset (timedate, 0, sizeof (struct tm)); - } -} - -/* ------------------------------------------------------------------------- */ - -int read_LM84_temp (int address) -{ - unsigned char buffer[8]; - /*int rc;*/ - - if (! i2c_read (address, 0, 1, buffer, 1)) { - return (int) buffer[0]; - } else { - /*printf("i2c error %02x\n", rc); */ - return -42; - } -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - struct tm timedate; - unsigned int ppctemp, prottemp; - - puts ("Board: Rohde & Schwarz 8260 Protocol Board\n"); - - /* initialise i2c */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - read_RS5C372_time (&timedate); - printf (" Time: %02d:%02d:%02d\n", - timedate.tm_hour, timedate.tm_min, timedate.tm_sec); - printf (" Date: %02d-%02d-%04d\n", - timedate.tm_mday, timedate.tm_mon, timedate.tm_year); - ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR); - prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR); - printf (" Temp: PPC %d C, Protocol Board %d C\n", - ppctemp, prottemp); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations while still - * running in flash - */ - -int misc_init_f (void) -{ - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifdef INIT_LOCAL_BUS_SDRAM - volatile uchar *ramaddr8; -#endif - volatile ulong *ramaddr32; - ulong sdmr; - int i; - - /* - * Only initialize SDRAM when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x02; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - /* - * Program local/60x bus Transfer Error Status and Control Regs: - * Disable parity errors - */ - immap->im_siu_conf.sc_tescr1 = 0x00040000; - immap->im_siu_conf.sc_ltescr1 = 0x00040000; - - /* - * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2) - * - * The appropriate BRx/ORx registers have already - * been set when we get here (see cpu_init_f). The - * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - memctl->memc_mptpr = 0x2000; - memctl->memc_mar = 0x0200; -#ifdef INIT_LOCAL_BUS_SDRAM - /* initialise local bus ram - * - * (using the PSRMR_ definitions is NOT an error here - * - the LSDMR has the same fields as the PSDMR!) - */ - memctl->memc_lsrt = 0x0b; - memctl->memc_lurt = 0x00; - ramaddr = (uchar *) PHYS_SDRAM_LOCAL; - sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); - memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA; - *ramaddr = 0xff; - for (i = 0; i < 8; i++) { - memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR; - *ramaddr = 0xff; - } - memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW; - *ramaddr = 0xff; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM; -#endif - /* initialise 60x bus ram */ - memctl->memc_psrt = 0x0b; - memctl->memc_purt = 0x08; - ramaddr32 = (ulong *) PHYS_SDRAM_60X; - sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); - memctl->memc_psdmr = sdmr | PSDMR_OP_PREA; - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - } - memctl->memc_psdmr = sdmr | PSDMR_OP_MRW; - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - } - - /* return the size of the 60x bus ram */ - return PHYS_SDRAM_60X_SIZE; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations after monitor - * has been relocated into ram - */ - -int misc_init_r (void) -{ - printf ("misc_init_r\n"); - return (0); -} diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds deleted file mode 100644 index 44bcd19fb1..0000000000 --- a/board/rsdproto/u-boot.lds +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc8260/start.o (.text) - *(.text) - *(.got1) - /*. = env_offset; */ - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile deleted file mode 100644 index 940a0168fd..0000000000 --- a/board/sacsng/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sacsng.o flash.o clkinit.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c deleted file mode 100644 index 2a28037dc3..0000000000 --- a/board/sacsng/clkinit.c +++ /dev/null @@ -1,1009 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. - * Jon Diekema - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include "clkinit.h" - -DECLARE_GLOBAL_DATA_PTR; - -int Daq64xSampling = 0; - - -void Daq_BRG_Reset(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr |= CPM_BRG_RST; - *brg_ptr &= ~CPM_BRG_RST; -} - -void Daq_BRG_Disable(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr &= ~CPM_BRG_EN; -} - -void Daq_BRG_Enable(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr |= CPM_BRG_EN; -} - -uint Daq_BRG_Get_Div16(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - if (*brg_ptr & CPM_BRG_DIV16) { - /* DIV16 active */ - return true; - } - else { - /* DIV16 inactive */ - return false; - } -} - -void Daq_BRG_Set_Div16(uint brg, uint div16) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - if (div16) { - /* DIV16 active */ - *brg_ptr |= CPM_BRG_DIV16; - } - else { - /* DIV16 inactive */ - *brg_ptr &= ~CPM_BRG_DIV16; - } -} - -uint Daq_BRG_Get_Count(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - uint brg_cnt; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - /* Get the clock divider - * - * Note: A clock divider of 0 means divide by 1, - * therefore we need to add 1 to the count. - */ - brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT; - brg_cnt++; - if (*brg_ptr & CPM_BRG_DIV16) { - brg_cnt *= 16; - } - - return (brg_cnt); -} - -void Daq_BRG_Set_Count(uint brg, uint brg_cnt) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - /* - * Note: A clock divider of 0 means divide by 1, - * therefore we need to subtract 1 from the count. - */ - if (brg_cnt > 4096) { - /* Prescale = Divide by 16 */ - *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) | - (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT); - *brg_ptr |= CPM_BRG_DIV16; - } - else { - /* Prescale = Divide by 1 */ - *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) | - ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT); - *brg_ptr &= ~CPM_BRG_DIV16; - } -} - -uint Daq_BRG_Get_ExtClk(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT); -} - -char* Daq_BRG_Get_ExtClk_Description(uint brg) -{ - uint extc; - - extc = Daq_BRG_Get_ExtClk(brg); - - switch (brg + 1) { - case 1: - case 2: - case 5: - case 6: { - switch (extc) { - case 0: { - return ("BRG_INT"); - } - case 1: { - return ("CLK3"); - } - case 2: { - return ("CLK5"); - } - } - return ("??1245??"); - } - case 3: - case 4: - case 7: - case 8: { - switch (extc) { - case 0: { - return ("BRG_INT"); - } - case 1: { - return ("CLK9"); - } - case 2: { - return ("CLK15"); - } - } - return ("??3478??"); - } - } - return ("??9876??"); -} - -void Daq_BRG_Set_ExtClk(uint brg, uint extc) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) | - ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK); -} - -uint Daq_BRG_Rate(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - uint brg_cnt; - uint brg_freq = 0; - - brg_ptr = (uint *)&immr->im_brgc1; - brg_ptr += brg; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg_ptr += (brg - 4); - } - - brg_cnt = Daq_BRG_Get_Count(brg); - - switch (Daq_BRG_Get_ExtClk(brg)) { - case CPM_BRG_EXTC_CLK3: - case CPM_BRG_EXTC_CLK5: { - brg_freq = brg_cnt; - break; - } - default: { - brg_freq = (uint)BRG_INT_CLK / brg_cnt; - } - } - return (brg_freq); -} - -uint Daq_Get_SampleRate(void) -{ - /* - * Read the BRG's to return the actual sample rate. - */ - return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR)); -} - -void Daq_Init_Clocks(int sample_rate, int sample_64x) -{ - volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */); - uint mclk_divisor; /* MCLK divisor */ - int flag; /* Interrupt state */ - - /* Save off the clocking data */ - Daq64xSampling = sample_64x; - - /* - * Limit the sample rate to some sensible values. - */ - if (sample_rate > MAX_64x_SAMPLE_RATE) { - sample_rate = MAX_64x_SAMPLE_RATE; - } - if (sample_rate < MIN_SAMPLE_RATE) { - sample_rate = MIN_SAMPLE_RATE; - } - - /* - * Initialize the MCLK/SCLK/LRCLK baud rate generators. - */ - - /* Setup MCLK */ - Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK); - - /* Setup SCLK */ -# ifdef RUN_SCLK_ON_BRG_INT - Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK); -# else - Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9); -# endif - - /* Setup LRCLK */ -# ifdef RUN_LRCLK_ON_BRG_INT - Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK); -# else - Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5); -# endif - - /* - * Dynamically adjust MCLK based on the new sample rate. - */ - - /* Compute the divisors */ - mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR); - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* Setup MCLK */ - Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor); - - /* Setup SCLK */ -# ifdef RUN_SCLK_ON_BRG_INT - Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR); -# else - Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR); -# endif - -# ifdef RUN_LRCLK_ON_BRG_INT - Daq_BRG_Set_Count(LRCLK_BRG, - mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR); -# else - Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR); -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } - - /* Enable the clock drivers */ - iopa->pdat &= ~SLRCLK_EN_MASK; -} - -void Daq_Stop_Clocks(void) - -{ -#ifdef TIGHTEN_UP_BRG_TIMING - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - register uint mclk_brg; /* MCLK BRG value */ - register uint sclk_brg; /* SCLK BRG value */ - register uint lrclk_brg; /* LRCLK BRG value */ - unsigned long flag; /* Interrupt flags */ -#endif - -# ifdef TIGHTEN_UP_BRG_TIMING - /* - * Obtain MCLK BRG reset/disabled value - */ -# if (MCLK_BRG == 0) - mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 1) - mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 2) - mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 3) - mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 4) - mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 5) - mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 6) - mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 7) - mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Obtain SCLK BRG reset/disabled value - */ -# if (SCLK_BRG == 0) - sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 1) - sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 2) - sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 3) - sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 4) - sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 5) - sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 6) - sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 7) - sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Obtain LRCLK BRG reset/disabled value - */ -# if (LRCLK_BRG == 0) - lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 1) - lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 2) - lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 3) - lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 4) - lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 5) - lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 6) - lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 7) - lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* - * Set reset on MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg; -# endif - - /* - * Set reset on SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg; -# endif - - /* - * Set reset on LRCLK BRG - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = lrclk_brg; -# endif - - /* - * Clear reset on MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Clear reset on SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Clear reset on LRCLK BRG - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } -# else - /* - * Reset the clocks - */ - Daq_BRG_Reset(MCLK_BRG); - Daq_BRG_Reset(SCLK_BRG); - Daq_BRG_Reset(LRCLK_BRG); -# endif -} - -void Daq_Start_Clocks(int sample_rate) - -{ -#ifdef TIGHTEN_UP_BRG_TIMING - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - register uint mclk_brg; /* MCLK BRG value */ - register uint sclk_brg; /* SCLK BRG value */ - register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */ - register uint real_lrclk_brg; /* Permanent LRCLK BRG value */ - uint lrclk_brg; /* LRCLK BRG value */ - unsigned long flags; /* Interrupt flags */ - uint sclk_cnt; /* SCLK count */ - uint delay_cnt; /* Delay count */ -#endif - -# ifdef TIGHTEN_UP_BRG_TIMING - /* - * Obtain the enabled MCLK BRG value - */ -# if (MCLK_BRG == 0) - mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 1) - mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 2) - mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 3) - mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 4) - mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 5) - mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 6) - mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 7) - mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* - * Obtain the enabled SCLK BRG value - */ -# if (SCLK_BRG == 0) - sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 1) - sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 2) - sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 3) - sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 4) - sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 5) - sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 6) - sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 7) - sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* - * Obtain the enabled LRCLK BRG value - */ -# if (LRCLK_BRG == 0) - lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 1) - lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 2) - lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 3) - lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 4) - lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 5) - lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 6) - lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 7) - lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* Save off the real LRCLK value */ - real_lrclk_brg = lrclk_brg; - - /* Obtain the current SCLK count */ - sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1; - - /* Compute the delay as a function of SCLK count */ - delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6; - if (DaqSampleRate == 43402) { - delay_cnt++; - } - - /* Clear out the count */ - temp_lrclk_brg = sclk_brg & ~0x00001FFE; - - /* Insert the count */ - temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE; - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* - * Enable MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg; -# endif - - /* - * Enable SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg; -# endif - - /* - * Enable LRCLK BRG (1st time - temporary) - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = temp_lrclk_brg; -# endif - - /* - * Enable LRCLK BRG (2nd time - permanent) - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = real_lrclk_brg; -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } -# else - /* - * Enable the clocks - */ - Daq_BRG_Enable(LRCLK_BRG); - Daq_BRG_Enable(SCLK_BRG); - Daq_BRG_Enable(MCLK_BRG); -# endif -} - -void Daq_Display_Clocks(void) - -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint mclk_divisor; /* Detected MCLK divisor */ - uint sclk_divisor; /* Detected SCLK divisor */ - - printf("\nBRG:\n"); - if (immr->im_brgc4 != 0) { - printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n", - immr->im_brgc4, - (uint)&(immr->im_brgc4), - Daq_BRG_Get_Count(3), - Daq_BRG_Get_ExtClk(3), - Daq_BRG_Get_ExtClk_Description(3)); - } - if (immr->im_brgc8 != 0) { - printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n", - immr->im_brgc8, - (uint)&(immr->im_brgc8), - Daq_BRG_Get_Count(7), - Daq_BRG_Get_ExtClk(7), - Daq_BRG_Get_ExtClk_Description(7)); - } - if (immr->im_brgc6 != 0) { - printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n", - immr->im_brgc6, - (uint)&(immr->im_brgc6), - Daq_BRG_Get_Count(5), - Daq_BRG_Get_ExtClk(5), - Daq_BRG_Get_ExtClk_Description(5)); - } - if (immr->im_brgc1 != 0) { - printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n", - immr->im_brgc1, - (uint)&(immr->im_brgc1), - Daq_BRG_Get_Count(0), - Daq_BRG_Get_ExtClk(0), - Daq_BRG_Get_ExtClk_Description(0)); - } - if (immr->im_brgc2 != 0) { - printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n", - immr->im_brgc2, - (uint)&(immr->im_brgc2), - Daq_BRG_Get_Count(1), - Daq_BRG_Get_ExtClk(1), - Daq_BRG_Get_ExtClk_Description(1)); - } - if (immr->im_brgc3 != 0) { - printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n", - immr->im_brgc3, - (uint)&(immr->im_brgc3), - Daq_BRG_Get_Count(2), - Daq_BRG_Get_ExtClk(2), - Daq_BRG_Get_ExtClk_Description(2)); - } - if (immr->im_brgc5 != 0) { - printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n", - immr->im_brgc5, - (uint)&(immr->im_brgc5), - Daq_BRG_Get_Count(4), - Daq_BRG_Get_ExtClk(4), - Daq_BRG_Get_ExtClk_Description(4)); - } - if (immr->im_brgc7 != 0) { - printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n", - immr->im_brgc7, - (uint)&(immr->im_brgc7), - Daq_BRG_Get_Count(6), - Daq_BRG_Get_ExtClk(6), - Daq_BRG_Get_ExtClk_Description(6)); - } - -# ifdef RUN_SCLK_ON_BRG_INT - mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG); -# else - mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG); -# endif -# ifdef RUN_LRCLK_ON_BRG_INT - sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG); -# else - sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG); -# endif - - printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor); - printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n", - Daq_BRG_Rate(MCLK_BRG), - mclk_divisor, - mclk_divisor * sclk_divisor); -# ifdef RUN_SCLK_ON_BRG_INT - printf("\tSCLK %8d Hz, or %3dx LRCLK\n", - Daq_BRG_Rate(SCLK_BRG), - sclk_divisor); -# else - printf("\tSCLK %8d Hz, or %3dx LRCLK\n", - Daq_BRG_Rate(MCLK_BRG) / mclk_divisor, - sclk_divisor); -# endif -# ifdef RUN_LRCLK_ON_BRG_INT - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(LRCLK_BRG)); -# else -# ifdef RUN_SCLK_ON_BRG_INT - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(SCLK_BRG) / sclk_divisor); -# else - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor)); -# endif -# endif - printf("\n"); -} diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h deleted file mode 100644 index 3f759dd48f..0000000000 --- a/board/sacsng/clkinit.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. - * Jon Diekema - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */ - -#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */ -#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */ -#define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */ - -#define KHZ ((uint)1000) -#define MHZ ((uint)(1000 * KHZ)) - -#define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */ -#define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */ -#define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */ - /* 0 == BRG1 (used for SMC1) */ - /* 1 == BRG2 (used for SMC2) */ - /* 2 == BRG3 (used for SCC1) */ - /* 3 == BRG4 (MCLK) */ - /* 4 == BRG5 */ - /* 5 == BRG6 (LRCLK) */ - /* 6 == BRG7 */ - /* 7 == BRG8 (SCLK) */ - -#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */ -#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128) - /* LRCLK = SCLK / SCLK_DIVISOR */ - -#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */ -#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */ - /* The 8260 (Mask B.3) seems to have */ - /* problems generating SCLK from MCLK */ - /* via CLK9. */ -#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */ - /* The 8260 (Mask B.3) seems to have */ - /* problems generating LRCLK from SCLK */ - -#define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */ - /* to wait for the clock to stabilize */ - -#define CPM_CLK (gd->bd->bi_cpmfreq) -#define DFBRG 4 -#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG) - /* BRG = CPM * 2 / DFBRG (Sect 9.8) */ - /* BRG = CPM * 2 / 4 */ - /* BRG = CPM / 2 */ - -#define CPM_BRG_EXTC_MASK ((uint)0x0000C000) -#define CPM_BRG_EXTC_SHIFT 14 - -#define CPM_BRG_DIV16_MASK ((uint)0x00000001) -#define CPM_BRG_DIV16_SHIFT 1 - -#define CPM_BRG_EXTC_BRGCLK 0 -#define CPM_BRG_EXTC_CLK3 1 -#define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3 -#define CPM_BRG_EXTC_CLK5 2 -#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5 - -#define IM_BRGC1 ((uint *)0xf00119f0) -#define IM_BRGC2 ((uint *)0xf00119f4) -#define IM_BRGC3 ((uint *)0xf00119f8) -#define IM_BRGC4 ((uint *)0xf00119fc) -#define IM_BRGC5 ((uint *)0xf00115f0) -#define IM_BRGC6 ((uint *)0xf00115f4) -#define IM_BRGC7 ((uint *)0xf00115f8) -#define IM_BRGC8 ((uint *)0xf00115fc) - -/* - * External declarations - */ - -extern int Daq64xSampling; - -extern void Daq_BRG_Reset(uint brg); -extern void Daq_BRG_Run(uint brg); - -extern void Daq_BRG_Disable(uint brg); -extern void Daq_BRG_Enable(uint brg); - -extern uint Daq_BRG_Get_Div16(uint brg); -extern void Daq_BRG_Set_Div16(uint brg, uint div16); - -extern uint Daq_BRG_Get_Count(uint brg); -extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt); - -extern uint Daq_BRG_Get_ExtClk(uint brg); -extern char* Daq_BRG_Get_ExtClk_Description(uint brg); -extern void Daq_BRG_Set_ExtClk(uint brg, uint extc); - -extern uint Daq_BRG_Rate(uint brg); - -extern uint Daq_Get_SampleRate(void); - -extern void Daq_Init_Clocks(int sample_rate, int sample_64x); -extern void Daq_Stop_Clocks(void); -extern void Daq_Start_Clocks(int sample_rate); -extern void Daq_Display_Clocks(void); diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c deleted file mode 100644 index 686fb225dc..0000000000 --- a/board/sacsng/flash.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -#undef DEBUG - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif -#ifndef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_short *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - /* - * We only report the primary flash for U-Boot's use. - */ - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - short i; - ushort value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0x9090; - __asm__ __volatile__(" sync\n "); - - value = addr[0]; -#ifdef DEBUG - printf("Flash manufacturer 0x%04X\n", value); -#endif - - if(value == (ushort)AMD_MANUFACT) { - info->flash_id = FLASH_MAN_AMD; - } else if (value == (ushort)FUJ_MANUFACT) { - info->flash_id = FLASH_MAN_FUJ; - } else { -#ifdef DEBUG - printf("Unknown flash manufacturer 0x%04X\n", value); -#endif - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ -#ifdef DEBUG - printf("Flash type 0x%04X\n", value); -#endif - - if(value == (ushort)AMD_ID_LV400T) { - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; /* => 0.5 MB */ - } else if(value == (ushort)AMD_ID_LV400B) { - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; /* => 0.5 MB */ - } else if(value == (ushort)AMD_ID_LV800T) { - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MB */ - } else if(value == (ushort)AMD_ID_LV800B) { - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MB */ - } else if(value == (ushort)AMD_ID_LV160T) { - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MB */ - } else if(value == (ushort)AMD_ID_LV160B) { - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MB */ - } else if(value == (ushort)AMD_ID_LV320T) { - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; /* => 4 MB */ - } else if(value == (ushort)AMD_ID_LV320B) { - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; /* => 4 MB */ - } else { -#ifdef DEBUG - printf("Unknown flash type 0x%04X\n", value); - info->size = CONFIG_SYS_FLASH_SIZE; -#else - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ -#endif - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i - 3) * 0x00010000); - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + (i * 0x00010000); - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned short *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned short *)info->start[0]; - - } - - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0x8080; - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - __asm__ __volatile__(" sync\n "); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x3030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short*)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short*)info->start[0]; - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start; - int flag; - int j; - - /* Check if Flash is (sufficiently) erased */ - if (((*(vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* The original routine was designed to write 32 bit words to - * 32 bit wide memory. We have 16 bit wide memory so we do - * two writes. We write the LSB first at dest+2 and then the - * MSB at dest (lousy big endian). - */ - dest += 2; - for(j = 0; j < 2; j++) { - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0xA0A0; - __asm__ __volatile__(" sync\n "); - - *((vu_short *)dest) = (ushort)data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while (*(vu_short *)dest != (ushort)data) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - dest -= 2; - data >>= 16; - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/sacsng/ioconfig.h b/board/sacsng/ioconfig.h deleted file mode 100644 index ac8f152e1f..0000000000 --- a/board/sacsng/ioconfig.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * I/O Port configuration table - * - * If conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#ifdef SKIP -#undef SKIP -#endif - -#ifdef CONF -#undef CONF -#endif - -#ifdef DIN -#undef DIN -#endif - -#ifdef DOUT -#undef DOUT -#endif - -#ifdef GPIO -#undef GPIO -#endif - -#ifdef SPEC -#undef SPEC -#endif - -#ifdef ACTV -#undef ACTV -#endif - -#ifdef OPEN -#undef OPEN -#endif - -#define SKIP 0 /* SKIP over this port */ -#define CONF 1 /* CONFiguration the port */ - -#define DIN 0 /* PDIRx 0: Direction IN */ -#define DOUT 1 /* PDIRx 1: Direction OUT */ - -#define GPIO 0 /* PPARx 0: General Purpose I/O */ -#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */ - /* i.e. the port has a SPECial use. */ - -#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */ -#define OPEN 1 /* PODRx 1: OPEN-drain driver */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS8* */ - /* PA30 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS7* */ - /* PA29 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS6* */ - /* PA28 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS5* */ - /* PA27 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS4* */ - /* PA26 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS3* */ - /* PA25 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS2* */ - /* PA24 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS1* */ - /* PA23 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* ODIS_EN* */ - /* PA22 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED2_EN* */ - /* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */ - /* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */ - /* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */ - /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */ - /* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */ - /* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */ - /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */ - /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */ - /* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */ - /* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */ - /* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */ - /* PA9 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3ACDC* */ - /* PA8 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3TEDS* */ - /* PA7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3XTDS* */ - /* PA6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2ACDC* */ - /* PA5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2TEDS* */ - /* PA4 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2XTDS* */ - /* PA3 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PA2 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1ACDC* */ - /* PA1 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1TEDS* */ - /* PA0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 } /* MTRX_1XTDS* */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TX_ER */ - /* PB30 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_DV */ - /* PB29 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* FCC2 MII_TX_EN */ - /* PB28 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_ER */ - /* PB27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_COL */ - /* PB26 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_CRS */ - /* PB25 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD3 */ - /* PB24 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD2 */ - /* PB23 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD1 */ - /* PB22 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD0 */ - /* PB21 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD0 */ - /* PB20 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD1 */ - /* PB19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD2 */ - /* PB18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD3 */ - /* PB17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB14 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDC1, BSDATA_ADC12 */ - /* PB13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB12 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCC1, LRCLK */ - /* PB11 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1TXDD1, RSDATA_DAC12 */ - /* PB10 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDD1, BSDATA_ADC34 */ - /* PB9 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB8 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCD1, LRCLK */ - /* PB7 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* XCITE_SHDN */ - /* PB5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* TRIGGER */ - /* PB4 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* ARM */ - /* PB3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC30 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC29 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK3, MCLK */ - /* PC28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* TOUT2* */ -#ifdef QQQ - /* PC28 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TOUT2* */ -#endif - /* PC27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK5, SCLK */ - /* PC26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC25 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK7, SCLK */ - /* PC24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC23 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK9, MCLK */ - /* PC22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC21 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO6 (LRCLK) */ - /* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */ - /* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */ - /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */ - /* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */ - /* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB3 */ - /* PC11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* TDM_STRB4 */ - /* PC9 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN3 */ - /* PC8 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN2 */ - /* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */ - /* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */ - /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */ - /* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */ - /* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */ - /* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */ - /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SCC1_RX */ - /* PD30 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SCC1_TX */ - /* PD29 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD27 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD25 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD23 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD21 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_ADC_CS* */ - /* PD19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_DAC_CS* */ -#if defined(CONFIG_SOFT_SPI) - /* PD18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_CLK */ - /* PD17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_MOSI */ - /* PD16 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* SPI_MISO */ -#else - /* PD18 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_CLK */ - /* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */ - /* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */ -#endif -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */ - /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SDA */ - /* PD14 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SDA */ - /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SCL */ -#endif -#endif - /* PD13 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB1 */ - /* PD12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB2 */ - /* PD11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* BRGO4 (MCLK) */ - /* PD9 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC1_TX */ - /* PD8 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SMC1_RX */ - /* PD7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD4 */ { CONF, SPEC, 1, DOUT, ACTV, 1 }, /* SMC2_RX */ - /* PD3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */ - } -}; diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c deleted file mode 100644 index 91c4987c95..0000000000 --- a/board/sacsng/sacsng.c +++ /dev/null @@ -1,848 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. - * Gerald Van Baren - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -#include -#endif - -#ifdef CONFIG_ETHER_LOOPBACK_TEST -extern void eth_loopback_test(void); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -#include "clkinit.h" -#include "ioconfig.h" /* I/O configuration table */ - -/* - * PBI Page Based Interleaving - * PSDMR_PBI page based interleaving - * 0 bank based interleaving - * External Address Multiplexing (EAMUX) adds a clock to address cycles - * (this can help with marginal board layouts) - * PSDMR_EAMUX adds a clock - * 0 no extra clock - * Buffer Command (BUFCMD) adds a clock to command cycles. - * PSDMR_BUFCMD adds a clock - * 0 no extra clock - */ -#define CONFIG_PBI PSDMR_PBI -#define PESSIMISTIC_SDRAM 0 -#define EAMUX 0 /* EST requires EAMUX */ -#define BUFCMD 0 - -/* - * ADC/DAC Defines: - */ -#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */ -#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */ -#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */ -#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */ -#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */ - -/* - * ADC Defines: - */ -#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */ -#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */ - -#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */ -#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */ - -#define ADC_VREF_CAP 100 /* VREF capacitor in uF */ -#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */ -#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */ -#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500) - /* Wait at least 4100 LRCLK's */ - -#define ADC_REG1_FRAME_START 0x80 /* Frame start */ -#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */ -#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */ -#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */ - -#define ADC_REG2_128x 0x80 /* Oversample at 128x */ -#define ADC_REG2_CAL 0x40 /* System calibration enable */ -#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */ -#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */ -#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */ -#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */ -#define ADC_REG2_DFS 0x02 /* Digital format select */ -#define ADC_REG2_MUTE 0x01 /* Mute */ - -#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */ -#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */ -#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */ -#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */ -#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */ -#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */ -#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */ - -/* - * DAC Defines: - */ - -#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */ - -#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */ -#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */ -#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */ - -#define DAC_REG1_AMUTE 0x80 /* Auto-mute */ - -#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */ -#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */ -#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */ -#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */ -#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */ -#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */ - -#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */ -#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */ -#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */ -#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */ - -#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */ -#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */ -#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */ -#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */ - -#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */ -#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */ -#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */ -#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */ -#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */ -#define DAC_REG5_FREEZE 0x04 /* Freeze */ -#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */ -#define DAC_REG5_RESERVED 0x01 /* Reserved */ - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - printf("SACSng\n"); - - return 0; -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); - uint psdmr = CONFIG_SYS_PSDMR; - int i; - uint psrt = 14; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ - -#ifdef SDRAM_SPD_ADDR - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char data; - u_char cksum; - int j; -#endif - -#ifdef SDRAM_SPD_ADDR - /* Keep the compiler from complaining about potentially uninitialized vars */ - data_width = chipselects = rows = banks = cols = caslatency = psrt = - 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - cksum = data; - for (j = 1; j < 64; j++) { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ - i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - if (j == 5) - chipselects = data & 0x0F; - else if (j == 6) - data_width = data; - else if (j == 7) - data_width |= data << 8; - else if (j == 3) - rows = data & 0x0F; - else if (j == 4) - cols = data & 0x0F; - else if (j == 12) { - /* - * Refresh rate: this assumes the prescaler is set to - * approximately 1uSec per tick. - */ - switch (data & 0x7F) { - default: - case 0: - psrt = 14; /* 15.625uS */ - break; - case 1: - psrt = 2; /* 3.9uS */ - break; - case 2: - psrt = 6; /* 7.8uS */ - break; - case 3: - psrt = 29; /* 31.3uS */ - break; - case 4: - psrt = 60; /* 62.5uS */ - break; - case 5: - psrt = 120; /* 125uS */ - break; - } - } else if (j == 17) - banks = data; - else if (j == 18) { - caslatency = 3; /* default CL */ -#if(PESSIMISTIC_SDRAM) - if ((data & 0x04) != 0) - caslatency = 3; - else if ((data & 0x02) != 0) - caslatency = 2; - else if ((data & 0x01) != 0) - caslatency = 1; -#else - if ((data & 0x01) != 0) - caslatency = 1; - else if ((data & 0x02) != 0) - caslatency = 2; - else if ((data & 0x04) != 0) - caslatency = 3; -#endif - else { - printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data); - } - } else if (j == 63) { - if (data != cksum) { - printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum); - } - } - cksum += data; - } - - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if (caslatency < 2) { - printf("WARNING: CL was %d, forcing to 2\n", caslatency); - caslatency = 2; - } - if (rows > 14) { - printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", - rows); - rows = 14; - } - if (cols > 11) { - printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", - cols); - cols = 11; - } - - if ((data_width != 64) && (data_width != 72)) { - printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", - data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) - banks = 1; - else if (banks == 4) - banks = 2; - else if (banks == 8) - banks = 3; - - sdram_size = 1 << (rows + cols + banks + width); - -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; -#else - rowst = 32 - (rows + banks + cols + width); -#endif - - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks - 1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - memctl->memc_or2 = or; - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; -#else - sdam = cols - 6; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; -#endif -#if(PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK | - PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C | - PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency | - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ - (sdam << 24) | (bsma << 21) | (sda10 << 18); -#else - psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK | - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX | BUFCMD) | - caslatency | ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ - (sdam << 24) | (bsma << 21) | (sda10 << 18); -#endif -#endif - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if (chipselects > 1) { - ramaddr += sdram_size; - - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; - memctl->memc_or3 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - } - - /* return total ram size */ - return (sdram_size * chipselects); -} - -/*----------------------------------------------------------------------- - * Board Control Functions - */ -void board_poweroff(void) -{ - while (1); /* hang forever */ -} - - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r(void) -{ - /* - * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. - */ - volatile ioport_t *iopa = - ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ ); - volatile ioport_t *iop = - ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); - - int reg; /* I2C register value */ - char *ep; /* Environment pointer */ - char str_buf[12]; /* sprintf output buffer */ - int sample_rate; /* ADC/DAC sample rate */ - int sample_64x; /* Use 64/4 clocking for the ADC/DAC */ - int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ - int right_just; /* Is the data to the DAC right justified? */ - int mclk_divide; /* MCLK Divide */ - int quiet; /* Quiet or minimal output mode */ - - quiet = 0; - - if ((ep = getenv("quiet")) != NULL) - quiet = simple_strtol(ep, NULL, 10); - else - setenv("quiet", "0"); - - /* - * SACSng custom initialization: - * Start the ADC and DAC clocks, since the Crystal parts do not - * work on the I2C bus until the clocks are running. - */ - - sample_rate = INITIAL_SAMPLE_RATE; - if ((ep = getenv("DaqSampleRate")) != NULL) - sample_rate = simple_strtol(ep, NULL, 10); - - sample_64x = INITIAL_SAMPLE_64X; - sample_128x = INITIAL_SAMPLE_128X; - if ((ep = getenv("Daq64xSampling")) != NULL) { - sample_64x = simple_strtol(ep, NULL, 10); - if (sample_64x) - sample_128x = 0; - else - sample_128x = 1; - } else { - if ((ep = getenv("Daq128xSampling")) != NULL) { - sample_128x = simple_strtol(ep, NULL, 10); - if (sample_128x) - sample_64x = 0; - else - sample_64x = 1; - } - } - - /* - * Stop the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has really stopped. - */ - Daq_Stop_Clocks(); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - /* - * Initialize the clocks with the new rates - */ - Daq_Init_Clocks(sample_rate, sample_64x); - sample_rate = Daq_Get_SampleRate(); - - /* - * Start the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has become stable. - */ - Daq_Start_Clocks(sample_rate); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - sprintf(str_buf, "%d", sample_rate); - setenv("DaqSampleRate", str_buf); - - if (sample_64x) { - setenv("Daq64xSampling", "1"); - setenv("Daq128xSampling", NULL); - } else { - setenv("Daq64xSampling", NULL); - setenv("Daq128xSampling", "1"); - } - - /* - * Display the ADC/DAC clocking information - */ - if (!quiet) - Daq_Display_Clocks(); - - /* - * Determine the DAC data justification - */ - - right_just = INITIAL_RIGHT_JUST; - if ((ep = getenv("DaqDACRightJustified")) != NULL) - right_just = simple_strtol(ep, NULL, 10); - - sprintf(str_buf, "%d", right_just); - setenv("DaqDACRightJustified", str_buf); - - /* - * Determine the DAC MCLK Divide - */ - - mclk_divide = INITIAL_MCLK_DIVIDE; - if ((ep = getenv("DaqDACMClockDivide")) != NULL) - mclk_divide = simple_strtol(ep, NULL, 10); - - sprintf(str_buf, "%d", mclk_divide); - setenv("DaqDACMClockDivide", str_buf); - - /* - * Initializing the I2C address in the Crystal A/Ds: - * - * 1) Wait for VREF cap to settle (10uSec per uF) - * 2) Release pullup on SDATA - * 3) Write the I2C address to register 6 - * 4) Enable address matching by setting the MSB in register 7 - */ - - if (!quiet) - printf("Initializing the ADC...\n"); - - udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ - - iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */ - ADC_REG7_ADDR_ENABLE); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F; - if (reg != I2C_ADC_1_ADDR) { - printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_1_ADDR); - } - - iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - /* set address (do not set ADDREN yet) */ - i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); - - i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F; - if (reg != I2C_ADC_2_ADDR) { - printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_2_ADDR); - } - - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */ - ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_CAL | - ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); - - udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */ - - /* - * Now that we have synchronized the ADC's, enable address - * selection on the second ADC as well as the first. - */ - i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE); - - /* - * Initialize the Crystal DAC - * - * Two of the config lines are used for I2C so we have to set them - * to the proper initialization state without inadvertantly - * sending an I2C "start" sequence. When we bring the I2C back to - * the normal state, we send an I2C "stop" sequence. - */ - if (!quiet) - printf("Initializing the DAC...\n"); - - /* - * Bring the I2C clock and data lines low for initialization - */ - I2C_SCL(0); - I2C_DELAY; - I2C_SDA(0); - I2C_ACTIVE; - I2C_DELAY; - - /* Reset the DAC */ - iopa->pdat &= ~DAC_RST_MASK; - udelay(DAC_RESET_DELAY); - - /* Release the DAC reset */ - iopa->pdat |= DAC_RST_MASK; - udelay(DAC_INITIAL_DELAY); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - DAC_REG5_POWER_DOWN | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Cause the DAC to: - * Auto-mute disabled - * . Format 0, left justified 24 bits - * . Format 3, right justified 24 bits - * No de-emphasis - * . Single speed mode - * . Double speed mode - */ - i2c_reg_write(I2C_DAC_ADDR, 0x01, - (right_just ? DAC_REG1_RIGHT_JUST_24BIT : - DAC_REG1_LEFT_JUST_24_BIT) | - DAC_REG1_DEM_NO | - (sample_rate >= - 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE)); - - sprintf(str_buf, "%d", - sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE); - setenv("DaqDACFunctionalMode", str_buf); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Remove power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Create a I2C stop condition: - * low->high on data while clock is high. - */ - I2C_SCL(1); - I2C_DELAY; - I2C_SDA(1); - I2C_DELAY; - I2C_TRISTATE; - - if (!quiet) - printf("\n"); -#ifdef CONFIG_ETHER_LOOPBACK_TEST - /* - * Run the Ethernet loopback test - */ - eth_loopback_test(); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -#ifdef CONFIG_SHOW_BOOT_PROGRESS - /* - * Turn off the RED fail LED now that we are up and running. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_OFF); -#endif - - return 0; -} - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -/* - * Show boot status: flash the LED if something goes wrong, indicating - * that last thing that worked and thus, by implication, what is broken. - * - * This stores the last OK value in RAM so this will not work properly - * before RAM is initialized. Since it is being used for indicating - * boot status (i.e. after RAM is initialized), that is OK. - */ -static void flash_code(uchar number, uchar modulo, uchar digits) -{ - int j; - - /* - * Recursively do upper digits. - */ - if (digits > 1) - flash_code(number / modulo, modulo, digits - 1); - - number = number % modulo; - - /* - * Zero is indicated by one long flash (dash). - */ - if (number == 0) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(1000000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } else { - /* - * Non-zero is indicated by short flashes, one per count. - */ - for (j = 0; j < number; j++) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(100000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } - } - /* - * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total - */ - udelay(700000); -} - -static int last_boot_progress; - -void show_boot_progress(int status) -{ - int i, j; - - if (status > 0) { - last_boot_progress = status; - } else { - /* - * If a specific failure code is given, flash this code - * else just use the last success code we've seen - */ - if (status < -1) - last_boot_progress = -status; - - /* - * Flash this code 5 times - */ - for (j = 0; j < 5; j++) { - /* - * Houston, we have a problem. - * Blink the last OK status which indicates where things failed. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - flash_code(last_boot_progress, 5, 3); - - /* - * Delay 5 seconds between repetitions, - * with the fault LED blinking - */ - for (i = 0; i < 5; i++) { - status_led_set(STATUS_LED_RED, - STATUS_LED_OFF); - udelay(500000); - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - udelay(500000); - } - } - - /* - * Reset the board to retry initialization. - */ - do_reset(NULL, 0, 0, NULL); - } -} -#endif /* CONFIG_SHOW_BOOT_PROGRESS */ - - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#if defined(CONFIG_CMD_SPI) - -#define SPI_ADC_CS_MASK 0x00000800 -#define SPI_DAC_CS_MASK 0x00001000 - -static const u32 cs_mask[] = { - SPI_ADC_CS_MASK, - SPI_DAC_CS_MASK, -}; - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile ioport_t *iopd = - ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ ); - - iopd->pdat &= ~cs_mask[slave->cs]; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile ioport_t *iopd = - ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ ); - - iopd->pdat |= cs_mask[slave->cs]; -} - -#endif - -#endif /* CONFIG_MISC_INIT_R */ diff --git a/board/samsung/arndale/Kconfig b/board/samsung/arndale/Kconfig new file mode 100644 index 0000000000..b620974ba0 --- /dev/null +++ b/board/samsung/arndale/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ARNDALE + +config SYS_BOARD + default "arndale" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "arndale" + +endif diff --git a/board/samsung/arndale/MAINTAINERS b/board/samsung/arndale/MAINTAINERS new file mode 100644 index 0000000000..7dc17854d1 --- /dev/null +++ b/board/samsung/arndale/MAINTAINERS @@ -0,0 +1,6 @@ +ARNDALE BOARD +M: Chander Kashyap +S: Maintained +F: board/samsung/arndale/ +F: include/configs/arndale.h +F: configs/arndale_defconfig diff --git a/board/samsung/arndale/Makefile b/board/samsung/arndale/Makefile new file mode 100644 index 0000000000..be2b3662ad --- /dev/null +++ b/board/samsung/arndale/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2013 Samsung Electronics +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += arndale_spl.o + +ifndef CONFIG_SPL_BUILD +obj-y += arndale.o +endif diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c new file mode 100644 index 0000000000..881d080522 --- /dev/null +++ b/board/samsung/arndale/arndale.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB_EHCI_EXYNOS +int board_usb_init(int index, enum usb_init_type init) +{ + /* Configure gpios for usb 3503 hub: + * disconnect, toggle reset and connect + */ + gpio_request(EXYNOS5_GPIO_D17, "usb_connect"); + gpio_request(EXYNOS5_GPIO_X35, "usb_reset"); + gpio_direction_output(EXYNOS5_GPIO_D17, 0); + gpio_direction_output(EXYNOS5_GPIO_X35, 0); + + gpio_direction_output(EXYNOS5_GPIO_X35, 1); + gpio_direction_output(EXYNOS5_GPIO_D17, 1); + + return 0; +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + return 0; +} + +int dram_init(void) +{ + int i; + u32 addr; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); + } + return 0; +} + +int power_init_board(void) +{ + set_ps_hold_ctrl(); + return 0; +} + +void dram_init_banksize(void) +{ + int i; + u32 addr, size; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); + + gd->bd->bi_dram[i].start = addr; + gd->bd->bi_dram[i].size = size; + } +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + int ret; + /* dwmmc initializattion for available channels */ + ret = exynos_dwmmc_init(gd->fdt_blob); + if (ret) + debug("dwmmc init failed\n"); + + return ret; +} +#endif + +static int board_uart_init(void) +{ + int err = 0, uart_id; + + for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { + err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); + if (err) { + debug("UART%d not configured\n", + (uart_id - PERIPH_ID_UART0)); + return err; + } + } + return err; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int err; + + err = board_uart_init(); + if (err) { + debug("UART init failed\n"); + return err; + } + return err; +} +#endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("\nBoard: Arndale\n"); + + return 0; +} +#endif + +#ifdef CONFIG_S5P_PA_SYSRAM +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + writel(addr, CONFIG_S5P_PA_SYSRAM); + + /* make sure this write is really executed */ + __asm__ volatile ("dsb\n"); +} +#endif diff --git a/board/samsung/arndale/arndale_spl.c b/board/samsung/arndale/arndale_spl.c new file mode 100644 index 0000000000..2949c0828d --- /dev/null +++ b/board/samsung/arndale/arndale_spl.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirM", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 1000, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .mem_manuf = MEM_MANUF_SAMSUNG, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* Will hang if SIGNATURE dont match */ + while (1) + ; + } + + return &machine_param; +} diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 9e48a7b6e5..93347ef000 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -5,23 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o +obj-$(CONFIG_USBDOWNLOAD_GADGET) += gadget.o +obj-$(CONFIG_MISC_COMMON) += misc.o -LIB = $(obj)libsamsung.o - -COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_BOARD_COMMON) += board.o +endif diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c new file mode 100644 index 0000000000..8b4c8e9a9d --- /dev/null +++ b/board/samsung/common/board.c @@ -0,0 +1,357 @@ +/* + * (C) Copyright 2013 SAMSUNG Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +__weak int exynos_early_init_f(void) +{ + return 0; +} + +__weak int exynos_power_init(void) +{ + return 0; +} + +#if defined CONFIG_EXYNOS_TMU +/* Boot Time Thermal Analysis for SoC temperature threshold breach */ +static void boot_temp_check(void) +{ + int temp; + + switch (tmu_monitor(&temp)) { + case TMU_STATUS_NORMAL: + break; + case TMU_STATUS_TRIPPED: + /* + * Status TRIPPED ans WARNING means corresponding threshold + * breach + */ + puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); + set_ps_hold_ctrl(); + hang(); + break; + case TMU_STATUS_WARNING: + puts("EXYNOS_TMU: WARNING! Temperature very high\n"); + break; + case TMU_STATUS_INIT: + /* + * TMU_STATUS_INIT means something is wrong with temperature + * sensing and TMU status was changed back from NORMAL to INIT. + */ + puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); + break; + default: + debug("EXYNOS_TMU: Unknown TMU state\n"); + } +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); +#if defined CONFIG_EXYNOS_TMU + if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { + debug("%s: Failed to init TMU\n", __func__); + return -1; + } + boot_temp_check(); +#endif + + return exynos_init(); +} + +int dram_init(void) +{ + int i; + u32 addr; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); + } + return 0; +} + +void dram_init_banksize(void) +{ + int i; + u32 addr, size; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); + + gd->bd->bi_dram[i].start = addr; + gd->bd->bi_dram[i].size = size; + } +} + +static int board_uart_init(void) +{ + int err, uart_id, ret = 0; + + for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { + err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); + if (err) { + debug("UART%d not configured\n", + (uart_id - PERIPH_ID_UART0)); + ret |= err; + } + } + return ret; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int err; +#ifdef CONFIG_BOARD_TYPES + set_board_type(); +#endif + err = board_uart_init(); + if (err) { + debug("UART init failed\n"); + return err; + } + +#ifdef CONFIG_SYS_I2C_INIT_BOARD + board_i2c_init(gd->fdt_blob); +#endif + +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB) +/* + * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs + * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve + * FB memory at a very early stage. So, we need to fill panel_info.vl_col, + * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called. + */ + err = exynos_lcd_early_init(gd->fdt_blob); + if (err) { + debug("LCD early init failed\n"); + return err; + } +#endif + + return exynos_early_init_f(); +} +#endif + +#if defined(CONFIG_POWER) +int power_init_board(void) +{ + set_ps_hold_ctrl(); + + return exynos_power_init(); +} +#endif + +#ifdef CONFIG_OF_CONTROL +#ifdef CONFIG_SMC911X +static int decode_sromc(const void *blob, struct fdt_sromc *config) +{ + int err; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); + if (node < 0) { + debug("Could not find SROMC node\n"); + return node; + } + + config->bank = fdtdec_get_int(blob, node, "bank", 0); + config->width = fdtdec_get_int(blob, node, "width", 2); + + err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, + FDT_SROM_TIMING_COUNT); + if (err < 0) { + debug("Could not decode SROMC configuration Error: %s\n", + fdt_strerror(err)); + return -FDT_ERR_NOTFOUND; + } + return 0; +} +#endif + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + u32 smc_bw_conf, smc_bc_conf; + struct fdt_sromc config; + fdt_addr_t base_addr; + int node; + + node = decode_sromc(gd->fdt_blob, &config); + if (node < 0) { + debug("%s: Could not find sromc configuration\n", __func__); + return 0; + } + node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); + if (node < 0) { + debug("%s: Could not find lan9215 configuration\n", __func__); + return 0; + } + + /* We now have a node, so any problems from now on are errors */ + base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); + if (base_addr == FDT_ADDR_T_NONE) { + debug("%s: Could not find lan9215 address\n", __func__); + return -1; + } + + /* Ethernet needs data bus width of 16 bits */ + if (config.width != 2) { + debug("%s: Unsupported bus width %d\n", __func__, + config.width); + return -1; + } + smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) + | SROMC_BYTE_ENABLE(config.bank); + + smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | + SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | + SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | + SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | + SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | + SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | + SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); + + /* Select and configure the SROMC bank */ + exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); + s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); + return smc911x_initialize(0, base_addr); +#endif + return 0; +} + +#ifdef CONFIG_GENERIC_MMC +static int init_mmc(void) +{ +#ifdef CONFIG_SDHCI + return exynos_mmc_init(gd->fdt_blob); +#else + return 0; +#endif +} + +static int init_dwmmc(void) +{ +#ifdef CONFIG_DWMMC + return exynos_dwmmc_init(gd->fdt_blob); +#else + return 0; +#endif +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + if (get_boot_mode() == BOOT_MODE_SD) { + ret = init_mmc(); + ret |= init_dwmmc(); + } else { + ret = init_dwmmc(); + ret |= init_mmc(); + } + + if (ret) + debug("mmc init failed\n"); + + return ret; +} +#endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + const char *board_info; + + board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + printf("Board: %s\n", board_info ? board_info : "unknown"); +#ifdef CONFIG_BOARD_TYPES + board_info = get_board_type(); + + printf("Model: %s\n", board_info ? board_info : "unknown"); +#endif + return 0; +} +#endif +#endif /* CONFIG_OF_CONTROL */ + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + stdio_print_current_devices(); + + if (cros_ec_get_error()) { + /* Force console on */ + gd->flags &= ~GD_FLG_SILENT; + + printf("cros-ec communications failure %d\n", + cros_ec_get_error()); + puts("\nPlease reset with Power+Refresh\n\n"); + panic("Cannot init cros-ec device"); + return -1; + } + return 0; +} +#endif + +int arch_early_init_r(void) +{ +#ifdef CONFIG_CROS_EC + if (cros_ec_board_init()) { + printf("%s: Failed to init EC\n", __func__); + return 0; + } +#endif + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_SET_DFU_ALT_INFO + set_dfu_alt_info(); +#endif +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif +#ifdef CONFIG_LCD_MENU + keys_init(); + check_boot_mode(); +#endif +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif + return 0; +} +#endif diff --git a/board/samsung/common/dfu_sample_env.txt b/board/samsung/common/dfu_sample_env.txt new file mode 100644 index 0000000000..d6ee8a228a --- /dev/null +++ b/board/samsung/common/dfu_sample_env.txt @@ -0,0 +1,9 @@ +mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0 +rootfstype=ext4 +loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage +mmcdev=0 +mmcbootpart=2 +mmcrootpart=5 +console=console=ttySAC2,115200n8 +bootcmd=run mmcboot +dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2 diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds index 8e3b73ecf7..4a933c87e9 100644 --- a/board/samsung/common/exynos-uboot-spl.lds +++ b/board/samsung/common/exynos-uboot-spl.lds @@ -21,6 +21,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sram @@ -42,7 +43,11 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - _end = .; + + .end : + { + *(.__end) + } >.sram .bss : { diff --git a/board/samsung/common/gadget.c b/board/samsung/common/gadget.c new file mode 100644 index 0000000000..6a1e57f164 --- /dev/null +++ b/board/samsung/common/gadget.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + if (!strcmp(name, "usb_dnl_thor")) { + put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor); + put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct); + } else if (!strcmp(name, "usb_dnl_ums")) { + put_unaligned(CONFIG_G_DNL_UMS_VENDOR_NUM, &dev->idVendor); + put_unaligned(CONFIG_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); + } else { + put_unaligned(CONFIG_G_DNL_VENDOR_NUM, &dev->idVendor); + put_unaligned(CONFIG_G_DNL_PRODUCT_NUM, &dev->idProduct); + } + return 0; +} diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c new file mode 100644 index 0000000000..4538ac7f2a --- /dev/null +++ b/board/samsung/common/misc.c @@ -0,0 +1,451 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SET_DFU_ALT_INFO +void set_dfu_alt_info(void) +{ + size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN; + ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size); + char *alt_info = "Settings not found!"; + char *status = "error!\n"; + char *alt_setting; + char *alt_sep; + int offset = 0; + + puts("DFU alt info setting: "); + + alt_setting = get_dfu_alt_boot(); + if (alt_setting) { + setenv("dfu_alt_boot", alt_setting); + offset = snprintf(buf, buf_size, "%s", alt_setting); + } + + alt_setting = get_dfu_alt_system(); + if (alt_setting) { + if (offset) + alt_sep = ";"; + else + alt_sep = ""; + + offset += snprintf(buf + offset, buf_size - offset, + "%s%s", alt_sep, alt_setting); + } + + if (offset) { + alt_info = buf; + status = "done\n"; + } + + setenv("dfu_alt_info", alt_info); + puts(status); +} +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +void set_board_info(void) +{ + char info[64]; + + snprintf(info, ARRAY_SIZE(info), "%u.%u", (s5p_cpu_rev & 0xf0) >> 4, + s5p_cpu_rev & 0xf); + setenv("soc_rev", info); + + snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id); + setenv("soc_id", info); + +#ifdef CONFIG_REVISION_TAG + snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev()); + setenv("board_rev", info); +#endif +#ifdef CONFIG_OF_LIBFDT + const char *bdtype = ""; + const char *bdname = CONFIG_SYS_BOARD; + +#ifdef CONFIG_BOARD_TYPES + bdtype = get_board_type(); + sprintf(info, "%s%s", bdname, bdtype); + setenv("boardname", info); +#endif + snprintf(info, ARRAY_SIZE(info), "%s%x-%s%s.dtb", + CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype); + setenv("fdtfile", info); +#endif +} +#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ + +#ifdef CONFIG_LCD_MENU +static int power_key_pressed(u32 reg) +{ + struct pmic *pmic; + u32 status; + u32 mask; + + pmic = pmic_get(KEY_PWR_PMIC_NAME); + if (!pmic) { + printf("%s: Not found\n", KEY_PWR_PMIC_NAME); + return 0; + } + + if (pmic_probe(pmic)) + return 0; + + if (reg == KEY_PWR_STATUS_REG) + mask = KEY_PWR_STATUS_MASK; + else + mask = KEY_PWR_INTERRUPT_MASK; + + if (pmic_reg_read(pmic, reg, &status)) + return 0; + + return !!(status & mask); +} + +static int key_pressed(int key) +{ + int value; + + switch (key) { + case KEY_POWER: + value = power_key_pressed(KEY_PWR_INTERRUPT_REG); + break; + case KEY_VOLUMEUP: + value = !gpio_get_value(KEY_VOL_UP_GPIO); + break; + case KEY_VOLUMEDOWN: + value = !gpio_get_value(KEY_VOL_DOWN_GPIO); + break; + default: + value = 0; + break; + } + + return value; +} + +static int check_keys(void) +{ + int keys = 0; + + if (key_pressed(KEY_POWER)) + keys += KEY_POWER; + if (key_pressed(KEY_VOLUMEUP)) + keys += KEY_VOLUMEUP; + if (key_pressed(KEY_VOLUMEDOWN)) + keys += KEY_VOLUMEDOWN; + + return keys; +} + +/* + * 0 BOOT_MODE_INFO + * 1 BOOT_MODE_THOR + * 2 BOOT_MODE_UMS + * 3 BOOT_MODE_DFU + * 4 BOOT_MODE_EXIT + */ +static char * +mode_name[BOOT_MODE_EXIT + 1][2] = { + {"DEVICE", ""}, + {"THOR", "thor"}, + {"UMS", "ums"}, + {"DFU", "dfu"}, + {"GPT", "gpt"}, + {"ENV", "env"}, + {"EXIT", ""}, +}; + +static char * +mode_info[BOOT_MODE_EXIT + 1] = { + "info", + "downloader", + "mass storage", + "firmware update", + "restore", + "default", + "and run normal boot" +}; + +static char * +mode_cmd[BOOT_MODE_EXIT + 1] = { + "", + "thor 0 mmc 0", + "ums 0 mmc 0", + "dfu 0 mmc 0", + "gpt write mmc 0 $partitions", + "env default -a; saveenv", + "", +}; + +static void display_board_info(void) +{ +#ifdef CONFIG_GENERIC_MMC + struct mmc *mmc = find_mmc_device(0); +#endif + vidinfo_t *vid = &panel_info; + + lcd_position_cursor(4, 4); + + lcd_printf("%s\n\t", U_BOOT_VERSION); + lcd_puts("\n\t\tBoard Info:\n"); +#ifdef CONFIG_SYS_BOARD + lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD); +#endif +#ifdef CONFIG_REVISION_TAG + lcd_printf("\tBoard rev: %u\n", get_board_rev()); +#endif + lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS); + lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M); + +#ifdef CONFIG_GENERIC_MMC + if (mmc) { + if (!mmc->capacity) + mmc_init(mmc); + + lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M); + } +#endif + if (vid) + lcd_printf("\tDisplay resolution: %u x % u\n", + vid->vl_col, vid->vl_row); + + lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix); +} + +static int mode_leave_menu(int mode) +{ + char *exit_option; + char *exit_reset = "reset"; + char *exit_back = "back"; + cmd_tbl_t *cmd; + int cmd_result; + int leave; + + lcd_clear(); + + switch (mode) { + case BOOT_MODE_EXIT: + return 1; + case BOOT_MODE_INFO: + display_board_info(); + exit_option = exit_back; + leave = 0; + break; + default: + cmd = find_cmd(mode_name[mode][1]); + if (cmd) { + printf("Enter: %s %s\n", mode_name[mode][0], + mode_info[mode]); + lcd_printf("\n\n\t%s %s\n", mode_name[mode][0], + mode_info[mode]); + lcd_puts("\n\tDo not turn off device before finish!\n"); + + cmd_result = run_command(mode_cmd[mode], 0); + + if (cmd_result == CMD_RET_SUCCESS) { + printf("Command finished\n"); + lcd_clear(); + lcd_printf("\n\n\t%s finished\n", + mode_name[mode][0]); + + exit_option = exit_reset; + leave = 1; + } else { + printf("Command error\n"); + lcd_clear(); + lcd_printf("\n\n\t%s command error\n", + mode_name[mode][0]); + + exit_option = exit_back; + leave = 0; + } + } else { + lcd_puts("\n\n\tThis mode is not supported.\n"); + exit_option = exit_back; + leave = 0; + } + } + + lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option); + + /* Clear PWR button Rising edge interrupt status flag */ + power_key_pressed(KEY_PWR_INTERRUPT_REG); + + /* Wait for PWR key */ + while (!key_pressed(KEY_POWER)) + mdelay(1); + + lcd_clear(); + return leave; +} + +static void display_download_menu(int mode) +{ + char *selection[BOOT_MODE_EXIT + 1]; + int i; + + for (i = 0; i <= BOOT_MODE_EXIT; i++) + selection[i] = "[ ]"; + + selection[mode] = "[=>]"; + + lcd_clear(); + lcd_printf("\n\n\t\tDownload Mode Menu\n\n"); + + for (i = 0; i <= BOOT_MODE_EXIT; i++) + lcd_printf("\t%s %s - %s\n\n", selection[i], + mode_name[i][0], + mode_info[i]); +} + +static void download_menu(void) +{ + int mode = 0; + int last_mode = 0; + int run; + int key = 0; + int timeout = 15; /* sec */ + int i; + + display_download_menu(mode); + + lcd_puts("\n"); + + /* Start count if no key is pressed */ + while (check_keys()) + continue; + + while (timeout--) { + lcd_printf("\r\tNormal boot will start in: %2.d seconds.", + timeout); + + /* about 1000 ms in for loop */ + for (i = 0; i < 10; i++) { + mdelay(100); + key = check_keys(); + if (key) + break; + } + if (key) + break; + } + + if (!key) { + lcd_clear(); + return; + } + + while (1) { + run = 0; + + if (mode != last_mode) + display_download_menu(mode); + + last_mode = mode; + mdelay(200); + + key = check_keys(); + switch (key) { + case KEY_POWER: + run = 1; + break; + case KEY_VOLUMEUP: + if (mode > 0) + mode--; + break; + case KEY_VOLUMEDOWN: + if (mode < BOOT_MODE_EXIT) + mode++; + break; + default: + break; + } + + if (run) { + if (mode_leave_menu(mode)) + run_command("reset", 0); + + display_download_menu(mode); + } + } + + lcd_clear(); +} + +void check_boot_mode(void) +{ + int pwr_key; + + pwr_key = power_key_pressed(KEY_PWR_STATUS_REG); + if (!pwr_key) + return; + + /* Clear PWR button Rising edge interrupt status flag */ + power_key_pressed(KEY_PWR_INTERRUPT_REG); + + if (key_pressed(KEY_VOLUMEUP)) + download_menu(); + else if (key_pressed(KEY_VOLUMEDOWN)) + mode_leave_menu(BOOT_MODE_THOR); +} + +void keys_init(void) +{ + /* Set direction to input */ + gpio_request(KEY_VOL_UP_GPIO, "volume-up"); + gpio_request(KEY_VOL_DOWN_GPIO, "volume-down"); + gpio_direction_input(KEY_VOL_UP_GPIO); + gpio_direction_input(KEY_VOL_DOWN_GPIO); +} +#endif /* CONFIG_LCD_MENU */ + +#ifdef CONFIG_CMD_BMP +void draw_logo(void) +{ + int x, y; + ulong addr; + + addr = panel_info.logo_addr; + if (!addr) { + error("There is no logo data."); + return; + } + + if (panel_info.vl_width >= panel_info.logo_width) { + x = ((panel_info.vl_width - panel_info.logo_width) >> 1); + x += panel_info.logo_x_offset; /* For X center align */ + } else { + x = 0; + printf("Warning: image width is bigger than display width\n"); + } + + if (panel_info.vl_height >= panel_info.logo_height) { + y = ((panel_info.vl_height - panel_info.logo_height) >> 1); + y += panel_info.logo_y_offset; /* For Y center align */ + } else { + y = 0; + printf("Warning: image height is bigger than display height\n"); + } + + bmp_display(addr, x, y); +} +#endif /* CONFIG_CMD_BMP */ diff --git a/board/samsung/common/multi_i2c.c b/board/samsung/common/multi_i2c.c index 4fce987540..71c32c0b6e 100644 --- a/board/samsung/common/multi_i2c.c +++ b/board/samsung/common/multi_i2c.c @@ -8,17 +8,26 @@ #include #include +#ifndef CONFIG_SOFT_I2C_I2C10_SCL +#define CONFIG_SOFT_I2C_I2C10_SCL 0 +#endif + +#ifndef CONFIG_SOFT_I2C_I2C10_SDA +#define CONFIG_SOFT_I2C_I2C10_SDA 0 +#endif + /* Handle multiple I2C buses instances */ int get_multi_scl_pin(void) { - unsigned int bus = I2C_GET_BUS(); + unsigned int bus = i2c_get_bus_num(); switch (bus) { - case I2C_0: /* I2C_0 definition - compatibility layer */ - case I2C_5: + case I2C_0: return CONFIG_SOFT_I2C_I2C5_SCL; - case I2C_9: + case I2C_1: return CONFIG_SOFT_I2C_I2C9_SCL; + case I2C_2: + return CONFIG_SOFT_I2C_I2C10_SCL; default: printf("I2C_%d not supported!\n", bus); }; @@ -28,14 +37,15 @@ int get_multi_scl_pin(void) int get_multi_sda_pin(void) { - unsigned int bus = I2C_GET_BUS(); + unsigned int bus = i2c_get_bus_num(); switch (bus) { - case I2C_0: /* I2C_0 definition - compatibility layer */ - case I2C_5: + case I2C_0: return CONFIG_SOFT_I2C_I2C5_SDA; - case I2C_9: + case I2C_1: return CONFIG_SOFT_I2C_I2C9_SDA; + case I2C_2: + return CONFIG_SOFT_I2C_I2C10_SDA; default: printf("I2C_%d not supported!\n", bus); }; diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts deleted file mode 100644 index 7832e4edda..0000000000 --- a/board/samsung/dts/exynos5250-snow.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * SAMSUNG Snow board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -/include/ "exynos5250.dtsi" - -/ { - model = "Google Snow"; - compatible = "google,snow", "samsung,exynos5250"; - - aliases { - i2c0 = "/i2c@12c60000"; - i2c1 = "/i2c@12c70000"; - i2c2 = "/i2c@12c80000"; - i2c3 = "/i2c@12c90000"; - i2c4 = "/i2c@12ca0000"; - i2c5 = "/i2c@12cb0000"; - i2c6 = "/i2c@12cc0000"; - i2c7 = "/i2c@12cd0000"; - spi0 = "/spi@12d20000"; - spi1 = "/spi@12d30000"; - spi2 = "/spi@12d40000"; - spi3 = "/spi@131a0000"; - spi4 = "/spi@131b0000"; - mmc0 = "/mmc@12200000"; - mmc1 = "/mmc@12210000"; - mmc2 = "/mmc@12220000"; - mmc3 = "/mmc@12230000"; - serial0 = "/serial@12C30000"; - console = "/serial@12C30000"; - }; - - i2c4: i2c@12ca0000 { - cros-ec@1e { - reg = <0x1e>; - compatible = "google,cros-ec"; - i2c-max-frequency = <100000>; - ec-interrupt = <&gpio 782 1>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - }; - }; - - spi@131b0000 { - spi-max-frequency = <1000000>; - spi-deactivate-delay = <100>; - cros-ec@0 { - reg = <0>; - compatible = "google,cros-ec"; - spi-max-frequency = <5000000>; - ec-interrupt = <&gpio 782 1>; - optimise-flash-write; - status = "disabled"; - }; - }; - - sound@12d60000 { - samsung,i2s-epll-clock-frequency = <192000000>; - samsung,i2s-sampling-rate = <48000>; - samsung,i2s-bits-per-sample = <16>; - samsung,i2s-channels = <2>; - samsung,i2s-lr-clk-framesize = <256>; - samsung,i2s-bit-clk-framesize = <32>; - samsung,codec-type = "max98095"; - }; - - i2c@12cd0000 { - soundcodec@22 { - reg = <0x22>; - compatible = "maxim,max98095-codec"; - }; - }; - - i2c@12c60000 { - pmic@9 { - reg = <0x9>; - compatible = "maxim,max77686_pmic"; - }; - }; - - mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; - samsung,removable = <0>; - }; - - mmc@12210000 { - status = "disabled"; - }; - - mmc@12220000 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; - samsung,removable = <1>; - }; - - mmc@12230000 { - status = "disabled"; - }; - - tmu@10060000 { - samsung,min-temp = <25>; - samsung,max-temp = <125>; - samsung,start-warning = <95>; - samsung,start-tripping = <105>; - samsung,hw-tripping = <110>; - samsung,efuse-min-value = <40>; - samsung,efuse-value = <55>; - samsung,efuse-max-value = <100>; - samsung,slope = <274761730>; - samsung,dc-value = <25>; - }; - - cros-ec-keyb { - compatible = "google,cros-ec-keyb"; - google,key-rows = <8>; - google,key-columns = <13>; - google,repeat-delay-ms = <240>; - google,repeat-rate-ms = <30>; - google,ghost-filter; - /* - * Keymap entries take the form of 0xRRCCKKKK where - * RR=Row CC=Column KKKK=Key Code - * The values below are for a US keyboard layout and - * are taken from the Linux driver. Note that the - * 102ND key is not used for US keyboards. - */ - linux,keymap = < - /* CAPSLCK F1 B F10 */ - 0x0001003a 0x0002003b 0x00030030 0x00040044 - /* N = R_ALT ESC */ - 0x00060031 0x0008000d 0x000a0064 0x01010001 - /* F4 G F7 H */ - 0x0102003e 0x01030022 0x01040041 0x01060023 - /* ' F9 BKSPACE L_CTRL */ - 0x01080028 0x01090043 0x010b000e 0x0200001d - /* TAB F3 T F6 */ - 0x0201000f 0x0202003d 0x02030014 0x02040040 - /* ] Y 102ND [ */ - 0x0205001b 0x02060015 0x02070056 0x0208001a - /* F8 GRAVE F2 5 */ - 0x02090042 0x03010029 0x0302003c 0x03030006 - /* F5 6 - \ */ - 0x0304003f 0x03060007 0x0308000c 0x030b002b - /* R_CTRL A D F */ - 0x04000061 0x0401001e 0x04020020 0x04030021 - /* S K J ; */ - 0x0404001f 0x04050025 0x04060024 0x04080027 - /* L ENTER Z C */ - 0x04090026 0x040b001c 0x0501002c 0x0502002e - /* V X , M */ - 0x0503002f 0x0504002d 0x05050033 0x05060032 - /* L_SHIFT / . SPACE */ - 0x0507002a 0x05080035 0x05090034 0x050B0039 - /* 1 3 4 2 */ - 0x06010002 0x06020004 0x06030005 0x06040003 - /* 8 7 0 9 */ - 0x06050009 0x06060008 0x0608000b 0x0609000a - /* L_ALT DOWN RIGHT Q */ - 0x060a0038 0x060b006c 0x060c006a 0x07010010 - /* E R W I */ - 0x07020012 0x07030013 0x07040011 0x07050017 - /* U R_SHIFT P O */ - 0x07060016 0x07070036 0x07080019 0x07090018 - /* UP LEFT */ - 0x070b0067 0x070c0069>; - }; -}; diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig new file mode 100644 index 0000000000..cbbf5a9315 --- /dev/null +++ b/board/samsung/goni/Kconfig @@ -0,0 +1,15 @@ +if TARGET_S5P_GONI + +config SYS_BOARD + default "goni" + +config SYS_VENDOR + default "samsung" + +config SYS_SOC + default "s5pc1xx" + +config SYS_CONFIG_NAME + default "s5p_goni" + +endif diff --git a/board/samsung/goni/MAINTAINERS b/board/samsung/goni/MAINTAINERS new file mode 100644 index 0000000000..248ec3cc0c --- /dev/null +++ b/board/samsung/goni/MAINTAINERS @@ -0,0 +1,6 @@ +GONI BOARD +M: Robert Baldyga +S: Maintained +F: board/samsung/goni/ +F: include/configs/s5p_goni.h +F: configs/s5p_goni_defconfig diff --git a/board/samsung/goni/Makefile b/board/samsung/goni/Makefile index cd91d66076..2cdc21d851 100644 --- a/board/samsung/goni/Makefile +++ b/board/samsung/goni/Makefile @@ -8,25 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := goni.o onenand.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := goni.o onenand.o +obj-y += lowlevel_init.o diff --git a/board/samsung/goni/config.mk b/board/samsung/goni/config.mk deleted file mode 100644 index e1cadbceed..0000000000 --- a/board/samsung/goni/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (C) 2010 Samsung Electronics -# Kyungmin Park -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# On S5PC100 we use the 128 MiB OneDRAM bank at -# -# 0x30000000 to 0x35000000 (80MiB) -# 0x38000000 to 0x40000000 (128MiB) -# -# On S5PC110 we use the 128 MiB OneDRAM bank at -# -# 0x30000000 to 0x35000000 (80MiB) -# 0x40000000 to 0x50000000 (256MiB) -# -CONFIG_SYS_TEXT_BASE = 0x34800000 diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index c05801d3fe..58cf96eaa8 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -7,32 +7,51 @@ */ #include -#include +#include #include #include #include #include #include +#include +#include +#include + DECLARE_GLOBAL_DATA_PTR; -static struct s5pc110_gpio *s5pc110_gpio; +u32 get_board_rev(void) +{ + return 0; +} int board_init(void) { /* Set Initial global variables */ - s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE; - gd->bd->bi_arch_number = MACH_TYPE_GONI; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; } +#ifdef CONFIG_SYS_I2C_INIT_BOARD +void i2c_init_board(void) +{ + gpio_request(S5PC110_GPIO_J43, "i2c_clk"); + gpio_request(S5PC110_GPIO_J40, "i2c_data"); + gpio_direction_output(S5PC110_GPIO_J43, 1); + gpio_direction_output(S5PC110_GPIO_J40, 1); +} +#endif + int power_init_board(void) { int ret; - ret = pmic_init(I2C_5); + /* + * For PMIC the I2C bus is named as I2C5, but it is connected + * to logical I2C adapter 0 + */ + ret = pmic_init(I2C_0); if (ret) return ret; @@ -68,10 +87,11 @@ int checkboard(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - int i; + int i, ret, ret_sd = 0; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1); + gpio_request(S5PC110_GPIO_J27, "massmemory_en"); + gpio_direction_output(S5PC110_GPIO_J27, 1); /* * MMC0 GPIO @@ -80,18 +100,48 @@ int board_mmc_init(bd_t *bis) * GPG0[2] SD_0_CDn -> Not used * GPG0[3:6] SD_0_DATA[0:3] */ - for (i = 0; i < 7; i++) { - if (i == 2) + for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) { + if (i == S5PC110_GPIO_G02) continue; /* GPG0[0:6] special function 2 */ - s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); + gpio_cfg_pin(i, 0x2); /* GPG0[0:6] pull disable */ - s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + + ret = s5p_mmc_init(0, 4); + if (ret) + error("MMC: Failed to init MMC:0.\n"); + + /* + * SD card (T_FLASH) detect and init + * T_FLASH_DETECT: EINT28: GPH3[4] input mode + */ + gpio_request(S5PC110_GPIO_H34, "t_flash_detect"); + gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT); + gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP); + + if (!gpio_get_value(S5PC110_GPIO_H34)) { + for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++) { + if (i == S5PC110_GPIO_G22) + continue; + + /* GPG2[0:6] special function 2 */ + gpio_cfg_pin(i, 0x2); + /* GPG2[0:6] pull disable */ + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + /* GPG2[0:6] drv 4x */ + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + + ret_sd = s5p_mmc_init(2, 4); + if (ret_sd) + error("MMC: Failed to init SD card (MMC:2).\n"); } - return s5p_mmc_init(0, 4); + return ret & ret_sd; } #endif @@ -139,4 +189,20 @@ struct s3c_plat_otg_data s5pc110_otg_data = { .regs_otg = S5PC110_OTG_BASE, .usb_phy_ctrl = S5PC110_USB_PHY_CONTROL, }; + +int board_usb_init(int index, enum usb_init_type init) +{ + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc110_otg_data); +} +#endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif + return 0; +} #endif diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 726211a336..d52bc09f8d 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -22,9 +22,6 @@ * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on */ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: mov r11, lr diff --git a/board/samsung/goni/mem_setup.S b/board/samsung/goni/mem_setup.S deleted file mode 100644 index 5dc980cf5b..0000000000 --- a/board/samsung/goni/mem_setup.S +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electrnoics - * Minkyu Kang - * Kyungmin Park - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - cmp r7, r8 - - ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000 - ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000 - ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000 - - /* DLL parameter setting */ - ldr r1, =0x50101000 - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - ldr r1, =0x000000f4 - str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET - strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET - ldreq r1, =0x0 - streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET - - /* DLL on */ - ldr r1, =0x50101002 - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - - /* DLL start */ - ldr r1, =0x50101003 - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - - mov r2, #0x4000 -wait: subs r2, r2, #0x1 - cmp r2, #0x0 - bne wait - - cmp r7, r8 - /* Force value locking for DLL off */ - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - - /* DLL off */ - ldr r1, =0x50101009 - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - - /* auto refresh off */ - ldr r1, =0xff001010 | (1 << 7) - ldr r2, =0xff001010 | (1 << 7) - str r1, [r0, #0x000] @ CONCONTROL_OFFSET - strne r2, [r6, #0x000] @ CONCONTROL_OFFSET - - /* - * Burst Length 4, 2 chips, 32-bit, LPDDR - * OFF: dynamic self refresh, force precharge, dynamic power down off - */ - ldr r1, =0x00212100 - ldr r2, =0x00212100 - str r1, [r0, #0x004] @ MEMCONTROL_OFFSET - strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET - - /* - * Note: - * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only) - * So finally Bank1 OneDRAM should address start at at 0x3000'0000 - */ - - /* - * DMC0: CS0 : S5PC100/S5PC110 - * 0x30 -> 0x30000000 - * 0xf8 -> 0x37FFFFFF - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - * [ 7:4 ] 2: 14 bits - * [ 3:0 ] 2: 4 banks - */ - ldr r3, =0x30f80222 - ldr r4, =0x40f00222 -swap_memory: - str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET - str r4, [r0, #0x00C] @ dummy write - - /* - * DMC1: CS0 : S5PC110 - * 0x40 -> 0x40000000 - * 0xf8 -> 0x47FFFFFF (1Gib) - * 0x40 -> 0x40000000 - * 0xf0 -> 0x4FFFFFFF (2Gib) - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - Col (1Gib) - * [11:8 ] 3: 10 bits - Col (2Gib) - * [ 7:4 ] 2: 14 bits - Row - * [ 3:0 ] 2: 4 banks - */ - /* Default : 2GiB */ - ldr r4, =0x40f01322 @ 2Gib: MCP B - ldr r5, =0x50f81312 @ dummy: MCP D - cmp r9, #1 - ldreq r4, =0x40f81222 @ 1Gib: MCP A - cmp r9, #3 - ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D - cmp r9, #4 - ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E - - cmp r7, r8 - strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET - strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET - - /* - * DMC0: CS1: S5PC100 - * 0x38 -> 0x38000000 - * 0xf8 -> 0x3fFFFFFF - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - * [ 7:4 ] 2: 14 bits - * [ 3:0 ] 2: 4 banks - */ - eoreq r3, r3, #0x08000000 - streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET - - ldr r1, =0x20000000 - str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET - strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET - strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET - - /* - * S5PC100: - * DMC: CS0: 166MHz - * CS1: 166MHz - * S5PC110: - * DMC0: CS0: 166MHz - * DMC1: CS0: 200MHz - * - * 7.8us * 200MHz %LE %LONG1560(0x618) - * 7.8us * 166MHz %LE %LONG1294(0x50E) - * 7.8us * 133MHz %LE %LONG1038(0x40E), - * 7.8us * 100MHz %LE %LONG780(0x30C), - */ - ldr r1, =0x0000050E - str r1, [r0, #0x030] @ TIMINGAREF_OFFSET - ldrne r1, =0x00000618 - strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET - - ldr r1, =0x14233287 - str r1, [r0, #0x034] @ TIMINGROW_OFFSET - ldrne r1, =0x182332c8 - strne r1, [r6, #0x034] @ TIMINGROW_OFFSET - - ldr r1, =0x12130005 - str r1, [r0, #0x038] @ TIMINGDATA_OFFSET - ldrne r1, =0x13130005 - strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET - - ldr r1, =0x0E140222 - str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET - ldrne r1, =0x0E180222 - strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET - - /* chip0 Deselect */ - ldr r1, =0x07000000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip0 PALL */ - ldr r1, =0x01000000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip0 REFA */ - ldr r1, =0x05000000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - /* chip0 REFA */ - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip0 MRS */ - ldr r1, =0x00000032 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip0 EMRS */ - ldr r1, =0x00020020 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 Deselect */ - ldr r1, =0x07100000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 PALL */ - ldr r1, =0x01100000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 REFA */ - ldr r1, =0x05100000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - /* chip1 REFA */ - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 MRS */ - ldr r1, =0x00100032 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 EMRS */ - ldr r1, =0x00120020 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* auto refresh on */ - ldr r1, =0xFF002030 | (1 << 7) - str r1, [r0, #0x000] @ CONCONTROL_OFFSET - strne r1, [r6, #0x000] @ CONCONTROL_OFFSET - - /* PwrdnConfig */ - ldr r1, =0x00100002 - str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET - strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET - - ldr r1, =0x00212113 - str r1, [r0, #0x004] @ MEMCONTROL_OFFSET - strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET - - /* Skip when S5PC110 */ - bne 1f - - /* Check OneDRAM access area at s5pc100 */ - ldreq r3, =0x38f80222 - ldreq r1, =0x37ffff00 - str r3, [r1] - ldr r2, [r1] - cmp r2, r3 - beq swap_memory -1: - mov pc, lr - - .ltorg diff --git a/board/samsung/odroid/Kconfig b/board/samsung/odroid/Kconfig new file mode 100644 index 0000000000..8b52a0d589 --- /dev/null +++ b/board/samsung/odroid/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID + +config SYS_BOARD + default "odroid" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "odroid" + +endif diff --git a/board/samsung/odroid/MAINTAINERS b/board/samsung/odroid/MAINTAINERS new file mode 100644 index 0000000000..2131d365ce --- /dev/null +++ b/board/samsung/odroid/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID BOARD +M: Przemyslaw Marczak +S: Maintained +F: board/samsung/odroid/ +F: include/configs/odroid.h +F: configs/odroid_defconfig diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile new file mode 100644 index 0000000000..b98aaeb101 --- /dev/null +++ b/board/samsung/odroid/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# Przemyslaw Marczak +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid.o diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c new file mode 100644 index 0000000000..e3517f2eb2 --- /dev/null +++ b/board/samsung/odroid/odroid.c @@ -0,0 +1,513 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "setup.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_BOARD_TYPES +/* Odroid board types */ +enum { + ODROID_TYPE_U3, + ODROID_TYPE_X2, + ODROID_TYPES, +}; + +void set_board_type(void) +{ + /* Set GPA1 pin 1 to HI - enable XCL205 output */ + writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON); + writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4); + writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8); + writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc); + + /* Set GPC1 pin 2 to IN - check XCL205 output state */ + writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON); + writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8); + + /* XCL205 - needs some latch time */ + sdelay(200000); + + /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */ + if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN)) + gd->board_type = ODROID_TYPE_X2; + else + gd->board_type = ODROID_TYPE_U3; +} + +const char *get_board_type(void) +{ + const char *board_type[] = {"u3", "x2"}; + + return board_type[gd->board_type]; +} +#endif + +#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(void) +{ + return getenv("dfu_alt_system"); +} + +char *get_dfu_alt_boot(void) +{ + char *alt_boot; + + switch (get_boot_mode()) { + case BOOT_MODE_SD: + alt_boot = CONFIG_DFU_ALT_BOOT_SD; + break; + case BOOT_MODE_EMMC: + case BOOT_MODE_EMMC_SD: + alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; + break; + default: + alt_boot = NULL; + break; + } + return alt_boot; +} +#endif + +static void board_clock_init(void) +{ + unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; + struct exynos4x12_clock *clk = (struct exynos4x12_clock *) + samsung_get_base_clock(); + + /* + * CMU_CPU clocks src to MPLL + * Bit values: 0 ; 1 + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL + */ + clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) | + MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1); + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) | + MUX_MPLL_USER_SEL_C(1); + + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + /* Wait for mux change */ + while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) + continue; + + /* Set APLL to 1000MHz */ + clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); + set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); + + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); + + /* Wait for PLL to be locked */ + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CMU_CPU clocks src to APLL */ + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) | + MUX_MPLL_USER_SEL_C(1); + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + /* Wait for mux change */ + while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) + continue; + + set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) | + PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) | + APLL_RATIO(0) | CORE2_RATIO(0); + /* + * Set dividers for MOUTcore = 1000 MHz + * coreout = MOUT / (ratio + 1) = 1000 MHz (0) + * corem0 = armclk / (ratio + 1) = 333 MHz (2) + * corem1 = armclk / (ratio + 1) = 166 MHz (5) + * periph = armclk / (ratio + 1) = 1000 MHz (0) + * atbout = MOUT / (ratio + 1) = 200 MHz (4) + * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) + * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) + * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) + */ + clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | + PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) | + APLL_RATIO(7) | CORE2_RATIO(7); + + clrsetbits_le32(&clk->div_cpu0, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) + continue; + + /* + * For MOUThpm = 1000 MHz (MOUTapll) + * doutcopy = MOUThpm / (ratio + 1) = 200 (4) + * sclkhpm = doutcopy / (ratio + 1) = 200 (4) + * cores_out = armclk / (ratio + 1) = 200 (4) + */ + clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); + set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); + + clrsetbits_le32(&clk->div_cpu1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING) + continue; + + /* + * Set CMU_DMC clocks src to APLL + * Bit values: 0 ; 1 + * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL + * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL + * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL + * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT + * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) + * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL + * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL + * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1 + */ + clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | + MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) | + MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) | + MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); + set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) | + MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) | + MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); + + clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); + + /* Wait for mux change */ + while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) + continue; + + /* Set MPLL to 800MHz */ + set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); + + /* Wait for PLL to be locked */ + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Switch back CMU_DMC mux */ + set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) | + MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) | + MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0); + + clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); + + /* Wait for mux change */ + while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) + continue; + + /* CLK_DIV_DMC0 */ + clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | + DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); + /* + * For: + * MOUTdmc = 800 MHz + * MOUTdphy = 800 MHz + * + * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) + * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) + * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) + * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) + * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) + * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) + */ + set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | + DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); + + clrsetbits_le32(&clk->div_dmc0, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING) + continue; + + /* CLK_DIV_DMC1 */ + clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | + C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); + /* + * For: + * MOUTg2d = 800 MHz + * MOUTc2c = 800 Mhz + * MOUTpwi = 108 MHz + * + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) + * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) + * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) + */ + set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); + + clrsetbits_le32(&clk->div_dmc1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING) + continue; + + /* CLK_SRC_PERIL0 */ + clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | + UART3_SEL(15) | UART4_SEL(15); + /* + * Set CLK_SRC_PERIL0 clocks src to MPLL + * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0); + * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL); + * 8(SCLK_VPLL) + * + * Set all to SCLK_MPLL_USER_T + */ + set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) | + UART4_SEL(6); + + clrsetbits_le32(&clk->src_peril0, clr, set); + + /* CLK_DIV_PERIL0 */ + clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | + UART3_RATIO(15) | UART4_RATIO(15); + /* + * For MOUTuart0-4: 800MHz + * + * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) + */ + set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | + UART3_RATIO(7) | UART4_RATIO(7); + + clrsetbits_le32(&clk->div_peril0, clr, set); + + while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING) + continue; + + /* CLK_DIV_FSYS1 */ + clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | + MMC1_PRE_RATIO(255); + /* + * For MOUTmmc0-3 = 800 MHz (MPLL) + * + * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) + * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) + * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) + * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) + */ + set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | + MMC1_PRE_RATIO(1); + + clrsetbits_le32(&clk->div_fsys1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) + continue; + + /* CLK_DIV_FSYS2 */ + clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | + MMC3_PRE_RATIO(255); + /* + * For MOUTmmc0-3 = 800 MHz (MPLL) + * + * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) + * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) + * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) + * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) + */ + set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | + MMC3_PRE_RATIO(1); + + clrsetbits_le32(&clk->div_fsys2, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING) + continue; + + /* CLK_DIV_FSYS3 */ + clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); + /* + * For MOUTmmc4 = 800 MHz (MPLL) + * + * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) + * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) + */ + set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); + + clrsetbits_le32(&clk->div_fsys3, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING) + continue; + + return; +} + +static void board_gpio_init(void) +{ + /* eMMC Reset Pin */ + gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset"); + + gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); + gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); + gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); + + /* Enable FAN (Odroid U3) */ + gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control"); + + gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); + gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); + gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); + + /* OTG Vbus output (Odroid U3+) */ + gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus"); + + gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); + gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); + gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); + + /* OTG INT (Odroid U3+) */ + gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT"); + + gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); + gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); + gpio_direction_input(EXYNOS4X12_GPIO_X31); + + /* Blue LED (Odroid X2/U2/U3) */ + gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED"); + + gpio_direction_output(EXYNOS4X12_GPIO_C10, 0); + +#ifdef CONFIG_CMD_USB + /* USB3503A Reference frequency */ + gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq"); + + /* USB3503A Connect */ + gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect"); + + /* USB3503A Reset */ + gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset"); +#endif +} + +static int pmic_init_max77686(void) +{ + struct pmic *p = pmic_get("MAX77686_PMIC"); + + if (pmic_probe(p)) + return -ENODEV; + + /* Set LDO Voltage */ + max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */ + max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */ + max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */ + + return 0; +} + +int exynos_early_init_f(void) +{ + board_clock_init(); + + return 0; +} + +int exynos_init(void) +{ + /* The last MB of memory is reserved for secure firmware */ + gd->ram_size -= SZ_1M; + gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M; + + board_gpio_init(); + + return 0; +} + +int exynos_power_init(void) +{ + pmic_init(0); + pmic_init_max77686(); + + return 0; +} + +#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{ + struct pmic *p_pmic; + + p_pmic = pmic_get("MAX77686_PMIC"); + if (!p_pmic) + return -ENODEV; + + if (pmic_probe(p_pmic)) + return -1; + + if (on) + return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON); + else + return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM); +} + +struct s3c_plat_otg_data s5pc210_otg_data = { + .phy_control = s5pc210_phy_control, + .regs_phy = EXYNOS4X12_USBPHY_BASE, + .regs_otg = EXYNOS4X12_USBOTG_BASE, + .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, + .usb_flags = PHY0_SLEEP, +}; +#endif + +#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB) + +int board_usb_init(int index, enum usb_init_type init) +{ +#ifdef CONFIG_CMD_USB + struct pmic *p_pmic; + + /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/ + /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */ + if (gd->board_type == ODROID_TYPE_U3) + gpio_direction_output(EXYNOS4X12_GPIO_X30, 0); + else + gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); + + /* Disconnect, Reset, Connect */ + gpio_direction_output(EXYNOS4X12_GPIO_X34, 0); + gpio_direction_output(EXYNOS4X12_GPIO_X35, 0); + gpio_direction_output(EXYNOS4X12_GPIO_X35, 1); + gpio_direction_output(EXYNOS4X12_GPIO_X34, 1); + + /* Power off and on BUCK8 for LAN9730 */ + debug("LAN9730 - Turning power buck 8 OFF and ON.\n"); + + p_pmic = pmic_get("MAX77686_PMIC"); + if (p_pmic && !pmic_probe(p_pmic)) { + max77686_set_buck_voltage(p_pmic, 8, 750000); + max77686_set_buck_voltage(p_pmic, 8, 3300000); + } + +#endif + + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc210_otg_data); +} +#endif + +void reset_misc(void) +{ + /* Reset eMMC*/ + gpio_set_value(EXYNOS4X12_GPIO_K12, 0); + mdelay(10); + gpio_set_value(EXYNOS4X12_GPIO_K12, 1); +} diff --git a/board/samsung/odroid/setup.h b/board/samsung/odroid/setup.h new file mode 100644 index 0000000000..3e48dada27 --- /dev/null +++ b/board/samsung/odroid/setup.h @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ODROIDU3_SETUP__ +#define __ODROIDU3_SETUP__ + +/* A/M PLL_CON0 */ +#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31) + +/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16) +#define MUX_HPM_SEL(x) (((x) & 0x1) << 20) +#define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) + +#define MUX_STAT_CHANGING 0x100 + +/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define HPM_SEL(x) (((x) & 0x7) << 20) +#define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24) +#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \ + CORE_SEL(MUX_STAT_CHANGING) | \ + HPM_SEL(MUX_STAT_CHANGING) | \ + MPLL_USER_SEL_C(MUX_STAT_CHANGING)) + +/* CLK_DIV_CPU0 */ +#define CORE_RATIO(x) ((x) & 0x7) +#define COREM0_RATIO(x) (((x) & 0x7) << 4) +#define COREM1_RATIO(x) (((x) & 0x7) << 8) +#define PERIPH_RATIO(x) (((x) & 0x7) << 12) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define CORE2_RATIO(x) (((x) & 0x7) << 28) + +/* CLK_DIV_STAT_CPU0 */ +#define DIV_CORE(x) ((x) & 0x1) +#define DIV_COREM0(x) (((x) & 0x1) << 4) +#define DIV_COREM1(x) (((x) & 0x1) << 8) +#define DIV_PERIPH(x) (((x) & 0x1) << 12) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_CORE2(x) (((x) & 0x1) << 28) + +#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \ + DIV_COREM0(DIV_STAT_CHANGING) | \ + DIV_COREM1(DIV_STAT_CHANGING) | \ + DIV_PERIPH(DIV_STAT_CHANGING) | \ + DIV_ATB(DIV_STAT_CHANGING) | \ + DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ + DIV_APLL(DIV_STAT_CHANGING) | \ + DIV_CORE2(DIV_STAT_CHANGING)) + +/* CLK_DIV_CPU1 */ +#define COPY_RATIO(x) ((x) & 0x7) +#define HPM_RATIO(x) (((x) & 0x7) << 4) +#define CORES_RATIO(x) (((x) & 0x7) << 8) + +/* CLK_DIV_STAT_CPU1 */ +#define DIV_COPY(x) ((x) & 0x7) +#define DIV_HPM(x) (((x) & 0x1) << 4) +#define DIV_CORES(x) (((x) & 0x1) << 8) + +#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \ + DIV_HPM(DIV_STAT_CHANGING) | \ + DIV_CORES(DIV_STAT_CHANGING)) + +/* CLK_SRC_DMC */ +#define MUX_C2C_SEL(x) ((x) & 0x1) +#define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4) +#define MUX_DPHY_SEL(x) (((x) & 0x1) << 8) +#define MUX_MPLL_SEL(x) (((x) & 0x1) << 12) +#define MUX_PWI_SEL(x) (((x) & 0xf) << 16) +#define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20) +#define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24) +#define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28) + +/* CLK_MUX_STAT_DMC */ +#define C2C_SEL(x) (((x)) & 0x7) +#define DMC_BUS_SEL(x) (((x) & 0x7) << 4) +#define DPHY_SEL(x) (((x) & 0x7) << 8) +#define MPLL_SEL(x) (((x) & 0x7) << 12) +/* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */ +#define G2D_ACP0_SEL(x) (((x) & 0x7) << 20) +#define G2D_ACP1_SEL(x) (((x) & 0x7) << 24) +#define G2D_ACP_SEL(x) (((x) & 0x7) << 28) + +#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \ + DMC_BUS_SEL(MUX_STAT_CHANGING) | \ + DPHY_SEL(MUX_STAT_CHANGING) | \ + MPLL_SEL(MUX_STAT_CHANGING) |\ + G2D_ACP0_SEL(MUX_STAT_CHANGING) | \ + G2D_ACP1_SEL(MUX_STAT_CHANGING) | \ + G2D_ACP_SEL(MUX_STAT_CHANGING)) + +/* CLK_DIV_DMC0 */ +#define ACP_RATIO(x) ((x) & 0x7) +#define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4) +#define DPHY_RATIO(x) (((x) & 0x7) << 8) +#define DMC_RATIO(x) (((x) & 0x7) << 12) +#define DMCD_RATIO(x) (((x) & 0x7) << 16) +#define DMCP_RATIO(x) (((x) & 0x7) << 20) + +/* CLK_DIV_STAT_DMC0 */ +#define DIV_ACP(x) ((x) & 0x1) +#define DIV_ACP_PCLK(x) (((x) & 0x1) << 4) +#define DIV_DPHY(x) (((x) & 0x1) << 8) +#define DIV_DMC(x) (((x) & 0x1) << 12) +#define DIV_DMCD(x) (((x) & 0x1) << 16) +#define DIV_DMCP(x) (((x) & 0x1) << 20) + +#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \ + DIV_ACP_PCLK(DIV_STAT_CHANGING) | \ + DIV_DPHY(DIV_STAT_CHANGING) | \ + DIV_DMC(DIV_STAT_CHANGING) | \ + DIV_DMCD(DIV_STAT_CHANGING) | \ + DIV_DMCP(DIV_STAT_CHANGING)) + +/* CLK_DIV_DMC1 */ +#define G2D_ACP_RATIO(x) ((x) & 0xf) +#define C2C_RATIO(x) (((x) & 0x7) << 4) +#define PWI_RATIO(x) (((x) & 0xf) << 8) +#define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12) +#define DVSEM_RATIO(x) (((x) & 0x7f) << 16) +#define DPM_RATIO(x) (((x) & 0x7f) << 24) + +/* CLK_DIV_STAT_DMC1 */ +#define DIV_G2D_ACP(x) ((x) & 0x1) +#define DIV_C2C(x) (((x) & 0x1) << 4) +#define DIV_PWI(x) (((x) & 0x1) << 8) +#define DIV_C2C_ACLK(x) (((x) & 0x1) << 12) +#define DIV_DVSEM(x) (((x) & 0x1) << 16) +#define DIV_DPM(x) (((x) & 0x1) << 24) + +#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \ + DIV_C2C(DIV_STAT_CHANGING) | \ + DIV_PWI(DIV_STAT_CHANGING) | \ + DIV_C2C_ACLK(DIV_STAT_CHANGING) | \ + DIV_DVSEM(DIV_STAT_CHANGING) | \ + DIV_DPM(DIV_STAT_CHANGING)) + +/* Set CLK_SRC_PERIL0 */ +#define UART4_SEL(x) (((x) & 0xf) << 16) +#define UART3_SEL(x) (((x) & 0xf) << 12) +#define UART2_SEL(x) (((x) & 0xf) << 8) +#define UART1_SEL(x) (((x) & 0xf) << 4) +#define UART0_SEL(x) ((x) & 0xf) + +/* Set CLK_DIV_PERIL0 */ +#define UART4_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 4) +#define UART0_RATIO(x) ((x) & 0xf) + +/* Set CLK_DIV_STAT_PERIL0 */ +#define DIV_UART4(x) (((x) & 0x1) << 16) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART0(x) ((x) & 0x1) + +#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ + DIV_UART3(DIV_STAT_CHANGING) | \ + DIV_UART2(DIV_STAT_CHANGING) | \ + DIV_UART1(DIV_STAT_CHANGING) | \ + DIV_UART0(DIV_STAT_CHANGING)) + +/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0xf) +#define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8) +#define MMC1_RATIO(x) (((x) & 0xf) << 16) +#define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24) + +/* CLK_DIV_STAT_FSYS1 */ +#define DIV_MMC0(x) ((x) & 1) +#define DIV_MMC0_PRE(x) (((x) & 1) << 8) +#define DIV_MMC1(x) (((x) & 1) << 16) +#define DIV_MMC1_PRE(x) (((x) & 1) << 24) + +#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ + DIV_MMC0_PRE(DIV_STAT_CHANGING) | \ + DIV_MMC1(DIV_STAT_CHANGING) | \ + DIV_MMC1_PRE(DIV_STAT_CHANGING)) + +/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO(x) ((x) & 0xf) +#define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8) +#define MMC3_RATIO(x) (((x) & 0xf) << 16) +#define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24) + +/* CLK_DIV_STAT_FSYS2 */ +#define DIV_MMC2(x) ((x) & 0x1) +#define DIV_MMC2_PRE(x) (((x) & 0x1) << 8) +#define DIV_MMC3(x) (((x) & 0x1) << 16) +#define DIV_MMC3_PRE(x) (((x) & 0x1) << 24) + +#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \ + DIV_MMC2_PRE(DIV_STAT_CHANGING) | \ + DIV_MMC3(DIV_STAT_CHANGING) | \ + DIV_MMC3_PRE(DIV_STAT_CHANGING)) + +/* CLK_DIV_FSYS3 */ +#define MMC4_RATIO(x) ((x) & 0x7) +#define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8) + +/* CLK_DIV_STAT_FSYS3 */ +#define DIV_MMC4(x) ((x) & 0x1) +#define DIV_MMC4_PRE(x) (((x) & 0x1) << 8) + +#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \ + DIV_MMC4_PRE(DIV_STAT_CHANGING)) + +/* XCL205 GPIO config - Odroid U3 */ +#define XCL205_GPIO_BASE EXYNOS4X12_GPIO_PART1_BASE +#define XCL205_EN_GPIO_OFFSET 0x20 /* GPA1 */ +#define XCL205_EN_GPIO_PIN 1 +#define XCL205_EN_GPIO_CON (XCL205_GPIO_BASE + \ + XCL205_EN_GPIO_OFFSET) +#define XCL205_EN_GPIO_CON_CFG (S5P_GPIO_OUTPUT << \ + 4 * XCL205_EN_GPIO_PIN) +#define XCL205_EN_GPIO_DAT_CFG (0x1 << XCL205_EN_GPIO_PIN) +#define XCL205_EN_GPIO_PUD_CFG (S5P_GPIO_PULL_UP << \ + 2 * XCL205_EN_GPIO_PIN) +#define XCL205_EN_GPIO_DRV_CFG (S5P_GPIO_DRV_4X << \ + 2 * XCL205_EN_GPIO_PIN) + +#define XCL205_STATE_GPIO_OFFSET 0x80 /* GPC1 */ +#define XCL205_STATE_GPIO_PIN 2 +#define XCL205_STATE_GPIO_CON (XCL205_GPIO_BASE + \ + XCL205_STATE_GPIO_OFFSET) +#define XCL205_STATE_GPIO_DAT XCL205_STATE_GPIO_CON + 0x4 +#define XCL205_STATE_GPIO_CON_CFG (S5P_GPIO_INPUT << \ + 4 * XCL205_STATE_GPIO_PIN) +#define XCL205_STATE_GPIO_PUD_CFG (S5P_GPIO_PULL_NONE << \ + 2 * XCL205_STATE_GPIO_PIN) + +#ifdef CONFIG_BOARD_TYPES +extern void sdelay(unsigned long); +#endif + +#endif /*__ODROIDU3_SETUP__ */ diff --git a/board/samsung/origen/Kconfig b/board/samsung/origen/Kconfig new file mode 100644 index 0000000000..63e3efe21c --- /dev/null +++ b/board/samsung/origen/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ORIGEN + +config SYS_BOARD + default "origen" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "origen" + +endif diff --git a/board/samsung/origen/MAINTAINERS b/board/samsung/origen/MAINTAINERS new file mode 100644 index 0000000000..8bf373e05d --- /dev/null +++ b/board/samsung/origen/MAINTAINERS @@ -0,0 +1,6 @@ +ORIGEN BOARD +M: Chander Kashyap +S: Maintained +F: board/samsung/origen/ +F: include/configs/origen.h +F: configs/origen_defconfig diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index 0b1ae1bb51..1add9fe626 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -4,38 +4,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -ifndef CONFIG_SPL_BUILD -COBJS += origen.o -endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -ALL +=$(obj).depend $(LIB) - ifdef CONFIG_SPL_BUILD -ALL += $(OBJTREE)/tools/mk$(BOARD)spl -endif +# necessary to create built-in.o +obj- := __dummy__.o -all: $(ALL) +hostprogs-y := tools/mkorigenspl +always := $(hostprogs-y) -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -ifdef CONFIG_SPL_BUILD -$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c - $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +# omit -O2 option to suppress +# warning: dereferencing type-punned pointer will break strict-aliasing rules +# +# TODO: +# Fix the root cause in tools/mkorigenspl.c and delete the following work-around +$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS)) +else +obj-y += origen.o endif - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index 15f77cacbd..99a2facd1e 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -6,134 +6,33 @@ #include #include +#include #include -#include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; -int board_init(void) +u32 get_board_rev(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } -static int board_uart_init(void) +int exynos_init(void) { - int err; - - err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); - if (err) { - debug("UART0 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); - if (err) { - debug("UART1 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); - if (err) { - debug("UART2 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - if (err) { - debug("UART3 not configured\n"); - return err; - } - return 0; } -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) +int board_usb_init(int index, enum usb_init_type init) { - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } - return err; -} -#endif - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) - + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) - + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) - + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - return 0; } -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ - PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ - PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ - PHYS_SDRAM_4_SIZE); -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) +#ifdef CONFIG_BOARD_EARLY_INIT_F +int exynos_early_init_f(void) { - printf("\nBoard: ORIGEN\n"); return 0; } #endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); - - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); - - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); - } - - err = s5p_mmc_init(2, 4); - return err; -} -#endif diff --git a/board/samsung/origen/tools/mkv310_image.c b/board/samsung/origen/tools/mkorigenspl.c similarity index 100% rename from board/samsung/origen/tools/mkv310_image.c rename to board/samsung/origen/tools/mkorigenspl.c diff --git a/board/samsung/smdk2410/Kconfig b/board/samsung/smdk2410/Kconfig new file mode 100644 index 0000000000..e987b6496f --- /dev/null +++ b/board/samsung/smdk2410/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SMDK2410 + +config SYS_BOARD + default "smdk2410" + +config SYS_VENDOR + default "samsung" + +config SYS_SOC + default "s3c24x0" + +config SYS_CONFIG_NAME + default "smdk2410" + +endif diff --git a/board/samsung/smdk2410/MAINTAINERS b/board/samsung/smdk2410/MAINTAINERS new file mode 100644 index 0000000000..12a25e8660 --- /dev/null +++ b/board/samsung/smdk2410/MAINTAINERS @@ -0,0 +1,6 @@ +SMDK2410 BOARD +M: David Müller +S: Maintained +F: board/samsung/smdk2410/ +F: include/configs/smdk2410.h +F: configs/smdk2410_defconfig diff --git a/board/samsung/smdk2410/Makefile b/board/samsung/smdk2410/Makefile index f52d0cd2de..1939a217a1 100644 --- a/board/samsung/smdk2410/Makefile +++ b/board/samsung/smdk2410/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := smdk2410.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := smdk2410.o +obj-y += lowlevel_init.o diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S index c7b78fd103..5de04f10e9 100644 --- a/board/samsung/smdk2410/lowlevel_init.S +++ b/board/samsung/smdk2410/lowlevel_init.S @@ -110,16 +110,13 @@ #define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ /**************************************/ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: /* memory control configuration */ /* make r0 relative the current location so that it */ /* reads SMRDATA out of FLASH rather than memory ! */ ldr r0, =SMRDATA - ldr r1, _TEXT_BASE + ldr r1, =CONFIG_SYS_TEXT_BASE sub r0, r0, r1 ldr r1, =BWSCON /* Bus Width Status Controller */ add r2, r0, #13*4 diff --git a/board/samsung/smdk5250/Kconfig b/board/samsung/smdk5250/Kconfig new file mode 100644 index 0000000000..698ee9125c --- /dev/null +++ b/board/samsung/smdk5250/Kconfig @@ -0,0 +1,25 @@ +if TARGET_SMDK5250 + +config SYS_BOARD + default "smdk5250" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "smdk5250" + +endif + +if TARGET_SNOW + +config SYS_BOARD + default "smdk5250" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "snow" + +endif diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS new file mode 100644 index 0000000000..070593e266 --- /dev/null +++ b/board/samsung/smdk5250/MAINTAINERS @@ -0,0 +1,12 @@ +SMDK5250 BOARD +M: Chander Kashyap +S: Maintained +F: board/samsung/smdk5250/ +F: include/configs/smdk5250.h +F: configs/smdk5250_defconfig + +SNOW BOARD +M: Akshay Saraswat +S: Maintained +F: include/configs/snow.h +F: configs/snow_defconfig diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile index 0463079935..3d96b077b4 100644 --- a/board/samsung/smdk5250/Makefile +++ b/board/samsung/smdk5250/Makefile @@ -4,35 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS += smdk5250_spl.o +obj-y += smdk5250_spl.o ifndef CONFIG_SPL_BUILD -ifdef CONFIG_OF_CONTROL -COBJS += exynos5-dt.o -else -COBJS += smdk5250.o -endif +obj-y += exynos5-dt.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -ALL := $(obj).depend $(LIB) - -all: $(ALL) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index bb4a82f449..53ff7061d7 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -5,145 +5,46 @@ */ #include -#include #include #include #include #include #include #include +#include #include #include -#include #include #include #include #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; -#if defined CONFIG_EXYNOS_TMU -/* - * Boot Time Thermal Analysis for SoC temperature threshold breach - */ -static void boot_temp_check(void) -{ - int temp; - - switch (tmu_monitor(&temp)) { - /* Status TRIPPED ans WARNING means corresponding threshold breach */ - case TMU_STATUS_TRIPPED: - puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); - set_ps_hold_ctrl(); - hang(); - break; - case TMU_STATUS_WARNING: - puts("EXYNOS_TMU: WARNING! Temperature very high\n"); - break; - /* - * TMU_STATUS_INIT means something is wrong with temperature sensing - * and TMU status was changed back from NORMAL to INIT. - */ - case TMU_STATUS_INIT: - default: - debug("EXYNOS_TMU: Unknown TMU state\n"); - } -} -#endif - -struct local_info { - struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ - int cros_ec_err; /* Error for cros_ec, 0 if ok */ -}; - -static struct local_info local; - -#ifdef CONFIG_USB_EHCI_EXYNOS -int board_usb_vbus_init(void) -{ - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - - /* Enable VBUS power switch */ - s5p_gpio_direction_output(&gpio1->x2, 6, 1); - - /* VBUS turn ON time */ - mdelay(3); - - return 0; -} -#endif - #ifdef CONFIG_SOUND_MAX98095 -static void board_enable_audio_codec(void) +static void board_enable_audio_codec(void) { - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Enable MAX98095 Codec */ - s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); + gpio_request(EXYNOS5_GPIO_X17, "max98095_enable"); + gpio_direction_output(EXYNOS5_GPIO_X17, 1); + gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); } #endif -struct cros_ec_dev *board_get_cros_ec_dev(void) +int exynos_init(void) { - return local.cros_ec_dev; -} - -static int board_init_cros_ec_devices(const void *blob) -{ - local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); - if (local.cros_ec_err) - return -1; /* Will report in board_late_init() */ - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); - -#if defined CONFIG_EXYNOS_TMU - if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { - debug("%s: Failed to init TMU\n", __func__); - return -1; - } - boot_temp_check(); -#endif - -#ifdef CONFIG_EXYNOS_SPI - spi_init(); -#endif - - if (board_init_cros_ec_devices(gd->fdt_blob)) - return -1; - -#ifdef CONFIG_USB_EHCI_EXYNOS - board_usb_vbus_init(); -#endif #ifdef CONFIG_SOUND_MAX98095 board_enable_audio_codec(); #endif return 0; } -int dram_init(void) -{ - int i; - u32 addr; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); - } - return 0; -} - #if defined(CONFIG_POWER) +#ifdef CONFIG_POWER_MAX77686 static int pmic_reg_update(struct pmic *p, int reg, uint regval) { u32 val; @@ -163,14 +64,10 @@ static int pmic_reg_update(struct pmic *p, int reg, uint regval) return 0; } -int power_init_board(void) +static int max77686_init(void) { struct pmic *p; - set_ps_hold_ctrl(); - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (pmic_init(I2C_PMIC)) return -1; @@ -258,195 +155,152 @@ int power_init_board(void) return 0; } -#endif - -void dram_init_banksize(void) -{ - int i; - u32 addr, size; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); +#endif /* CONFIG_POWER_MAX77686 */ - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; - } -} - -static int decode_sromc(const void *blob, struct fdt_sromc *config) +int exynos_power_init(void) { - int err; - int node; - - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); - if (node < 0) { - debug("Could not find SROMC node\n"); - return node; - } + int ret = 0; - config->bank = fdtdec_get_int(blob, node, "bank", 0); - config->width = fdtdec_get_int(blob, node, "width", 2); +#ifdef CONFIG_POWER_MAX77686 + ret = max77686_init(); + if (ret) + return ret; +#endif +#ifdef CONFIG_POWER_TPS65090 + /* + * The TPS65090 may not be in the device tree. If so, it is not + * an error. + */ + ret = tps65090_init(); + if (ret == 0 || ret == -ENODEV) + return 0; +#endif - err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, - FDT_SROM_TIMING_COUNT); - if (err < 0) { - debug("Could not decode SROMC configuration Error: %s\n", - fdt_strerror(err)); - return -FDT_ERR_NOTFOUND; - } - return 0; + return ret; } +#endif /* CONFIG_POWER */ -int board_eth_init(bd_t *bis) +#ifdef CONFIG_LCD +static int board_dp_bridge_setup(void) { -#ifdef CONFIG_SMC911X - u32 smc_bw_conf, smc_bc_conf; - struct fdt_sromc config; - fdt_addr_t base_addr; - int node; + const int max_tries = 10; + int num_tries, node; - node = decode_sromc(gd->fdt_blob, &config); - if (node < 0) { - debug("%s: Could not find sromc configuration\n", __func__); - return 0; - } - node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); + /* + * TODO(sjg): Use device tree for GPIOs when exynos GPIO + * numbering patch is in mainline. + */ + debug("%s\n", __func__); + node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460); if (node < 0) { - debug("%s: Could not find lan9215 configuration\n", __func__); - return 0; + debug("%s: No node for DP bridge in device tree\n", __func__); + return -ENODEV; } - /* We now have a node, so any problems from now on are errors */ - base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) { - debug("%s: Could not find lan9215 address\n", __func__); - return -1; - } + /* Setup the GPIOs */ - /* Ethernet needs data bus width of 16 bits */ - if (config.width != 2) { - debug("%s: Unsupported bus width %d\n", __func__, - config.width); - return -1; - } - smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) - | SROMC_BYTE_ENABLE(config.bank); - - smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | - SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | - SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | - SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | - SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | - SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | - SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); - - /* Select and configure the SROMC bank */ - exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); - s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); - return smc911x_initialize(0, base_addr); -#endif - return 0; -} + /* PD is ACTIVE_LOW, and initially de-asserted */ + gpio_request(EXYNOS5_GPIO_Y25, "dp_bridge_pd"); + gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE); + gpio_direction_output(EXYNOS5_GPIO_Y25, 1); -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - const char *board_name; + /* Reset is ACTIVE_LOW */ + gpio_request(EXYNOS5_GPIO_X15, "dp_bridge_reset"); + gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE); + gpio_direction_output(EXYNOS5_GPIO_X15, 0); - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (board_name == NULL) - printf("\nUnknown Board\n"); - else - printf("\nBoard: %s\n", board_name); + udelay(10); + gpio_set_value(EXYNOS5_GPIO_X15, 1); - return 0; -} -#endif + gpio_request(EXYNOS5_GPIO_X07, "dp_bridge_hpd"); + gpio_direction_input(EXYNOS5_GPIO_X07); -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int ret; - /* dwmmc initializattion for available channels */ - ret = exynos_dwmmc_init(gd->fdt_blob); - if (ret) - debug("dwmmc init failed\n"); + /* + * We need to wait for 90ms after bringing up the bridge since there + * is a phantom "high" on the HPD chip during its bootup. The phantom + * high comes within 7ms of de-asserting PD and persists for at least + * 15ms. The real high comes roughly 50ms after PD is de-asserted. The + * phantom high makes it hard for us to know when the NXP chip is up. + */ + mdelay(90); - return ret; -} -#endif + for (num_tries = 0; num_tries < max_tries; num_tries++) { + /* Check HPD. If it's high, we're all good. */ + if (gpio_get_value(EXYNOS5_GPIO_X07)) + return 0; -static int board_uart_init(void) -{ - int err, uart_id, ret = 0; - - for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { - err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); - if (err) { - debug("UART%d not configured\n", - (uart_id - PERIPH_ID_UART0)); - ret |= err; - } + debug("%s: eDP bridge failed to come up; try %d of %d\n", + __func__, num_tries, max_tries); } - return ret; -} -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(gd->fdt_blob); -#endif - return err; + /* Immediately go into bridge reset if the hp line is not high */ + return -ENODEV; } -#endif -#ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); + gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight"); + gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_B20, 1); /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); + gpio_request(EXYNOS5_GPIO_X15, "lcd_power"); + gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_X15, 1); /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); } void exynos_set_dp_phy(unsigned int onoff) { set_dp_phy_ctrl(onoff); } + +void exynos_backlight_on(unsigned int on) +{ + debug("%s(%u)\n", __func__, on); + + if (!on) + return; + +#ifdef CONFIG_POWER_TPS65090 + int ret; + + ret = tps65090_fet_enable(1); /* Enable FET1, backlight */ + if (ret) + return; + + /* T5 in the LCD timing spec (defined as > 10ms) */ + mdelay(10); + + /* board_dp_backlight_pwm */ + gpio_direction_output(EXYNOS5_GPIO_B20, 1); + + /* T6 in the LCD timing spec (defined as > 10ms) */ + mdelay(10); + + /* board_dp_backlight_en */ + gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en"); + gpio_direction_output(EXYNOS5_GPIO_X30, 1); #endif +} -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) +void exynos_lcd_power_on(void) { - stdio_print_current_devices(); + int ret; - if (local.cros_ec_err) { - /* Force console on */ - gd->flags &= ~GD_FLG_SILENT; + debug("%s\n", __func__); - printf("cros-ec communications failure %d\n", - local.cros_ec_err); - puts("\nPlease reset with Power+Refresh\n\n"); - panic("Cannot init cros-ec device"); - return -1; - } - return 0; +#ifdef CONFIG_POWER_TPS65090 + /* board_dp_lcd_vdd */ + tps65090_fet_enable(6); /* Enable FET6, lcd panel */ +#endif + + ret = board_dp_bridge_setup(); + if (ret && ret != -ENODEV) + printf("LCD bridge failed to enable: %d\n", ret); } + #endif diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S deleted file mode 100644 index 9003e2d007..0000000000 --- a/board/samsung/smdk5250/lowlevel_init.S +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Lowlevel setup for SMDK5250 board based on S5PC520 - * - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - - .globl lowlevel_init -lowlevel_init: - - /* use iRAM stack in bl2 */ - ldr sp, =CONFIG_IRAM_STACK - stmdb r13!, {ip,lr} - - /* check reset status */ - ldr r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET) - ldr r1, [r0] - - /* AFTR wakeup reset */ - ldr r2, =S5P_CHECK_DIDLE - cmp r1, r2 - beq exit_wakeup - - /* LPA wakeup reset */ - ldr r2, =S5P_CHECK_LPA - cmp r1, r2 - beq exit_wakeup - - /* Sleep wakeup reset */ - ldr r2, =S5P_CHECK_SLEEP - cmp r1, r2 - beq wakeup_reset - - /* - * If U-boot is already running in RAM, no need to relocate U-Boot. - * Memory controller must be configured before relocating U-Boot - * in ram. - */ - ldr r0, =0x0ffffff /* r0 <- Mask Bits*/ - bic r1, pc, r0 /* pc <- current addr of code */ - /* r1 <- unmasked bits of pc */ - ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ - bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ - cmp r1, r2 /* compare r1, r2 */ - beq 1f /* r0 == r1 then skip sdram init */ - - /* init system clock */ - bl system_clock_init - - /* Memory initialize */ - bl mem_ctrl_init - -1: - bl arch_cpu_init - bl tzpc_init - ldmia r13!, {ip,pc} - -wakeup_reset: - bl system_clock_init - bl mem_ctrl_init - bl arch_cpu_init - bl tzpc_init - -exit_wakeup: - /* Load return address and jump to kernel */ - ldr r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET) - - /* r1 = physical address of exynos5_cpu_resume function*/ - ldr r1, [r0] - - /* Jump to kernel */ - mov pc, r1 - nop - nop diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c deleted file mode 100644 index 97fe0adf54..0000000000 --- a/board/samsung/smdk5250/smdk5250.c +++ /dev/null @@ -1,438 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_USB_EHCI_EXYNOS -int board_usb_vbus_init(void) -{ - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - - /* Enable VBUS power switch */ - s5p_gpio_direction_output(&gpio1->x2, 6, 1); - - /* VBUS turn ON time */ - mdelay(3); - - return 0; -} -#endif - -#ifdef CONFIG_SOUND_MAX98095 -static void board_enable_audio_codec(void) -{ - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - - /* Enable MAX98095 Codec */ - s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); - -#ifdef CONFIG_EXYNOS_SPI - spi_init(); -#endif -#ifdef CONFIG_USB_EHCI_EXYNOS - board_usb_vbus_init(); -#endif -#ifdef CONFIG_SOUND_MAX98095 - board_enable_audio_codec(); -#endif - return 0; -} - -int dram_init(void) -{ - int i; - u32 addr; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); - } - return 0; -} - -#if defined(CONFIG_POWER) -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - - set_ps_hold_ctrl(); - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1_05V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif - -void dram_init_banksize(void) -{ - int i; - u32 addr, size; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; - } -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - u32 smc_bw_conf, smc_bc_conf; - struct fdt_sromc config; - fdt_addr_t base_addr; - - /* Non-FDT configuration - bank number and timing parameters*/ - config.bank = CONFIG_ENV_SROM_BANK; - config.width = 2; - - config.timing[FDT_SROM_TACS] = 0x01; - config.timing[FDT_SROM_TCOS] = 0x01; - config.timing[FDT_SROM_TACC] = 0x06; - config.timing[FDT_SROM_TCOH] = 0x01; - config.timing[FDT_SROM_TAH] = 0x0C; - config.timing[FDT_SROM_TACP] = 0x09; - config.timing[FDT_SROM_PMC] = 0x01; - base_addr = CONFIG_SMC911X_BASE; - - /* Ethernet needs data bus width of 16 bits */ - if (config.width != 2) { - debug("%s: Unsupported bus width %d\n", __func__, - config.width); - return -1; - } - smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) - | SROMC_BYTE_ENABLE(config.bank); - - smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\ - SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\ - SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\ - SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\ - SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\ - SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\ - SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); - - /* Select and configure the SROMC bank */ - exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); - s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); - return smc911x_initialize(0, base_addr); -#endif - return 0; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("\nBoard: SMDK5250\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int err, ret = 0, index, bus_width; - u32 base; - - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - ret |= err; - - /*EMMC: dwmmc Channel-0 with 8 bit bus width */ - index = 0; - base = samsung_get_base_mmc() + (0x10000 * index); - bus_width = 8; - err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL); - if (err) - debug("dwmmc Channel-0 init failed\n"); - ret |= err; - - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - ret |= err; - - /*SD: dwmmc Channel-2 with 4 bit bus width */ - index = 2; - base = samsung_get_base_mmc() + (0x10000 * index); - bus_width = 4; - err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL); - if (err) - debug("dwmmc Channel-2 init failed\n"); - ret |= err; - - return ret; -} -#endif - -static int board_uart_init(void) -{ - int err, uart_id, ret = 0; - - for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { - err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); - if (err) { - debug("UART%d not configured\n", - (uart_id - PERIPH_ID_UART0)); - ret |= err; - } - } - return ret; -} - -void board_i2c_init(const void *blob) -{ - int i; - - for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) { - exynos_pinmux_config((PERIPH_ID_I2C0 + i), - PINMUX_FLAG_NONE); - } -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(NULL); -#endif - return err; -} -#endif - -#ifdef CONFIG_LCD -void exynos_cfg_lcd_gpio(void) -{ - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - - /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); - - /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); - - /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); -} - -void exynos_set_dp_phy(unsigned int onoff) -{ - set_dp_phy_ctrl(onoff); -} - -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 2560, - .vl_row = 1600, - .vl_width = 2560, - .vl_height = 1600, - .vl_clkp = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */ - - /* wDP panel timing infomation */ - .vl_hspw = 32, - .vl_hbpd = 80, - .vl_hfpd = 48, - - .vl_vspw = 6, - .vl_vbpd = 37, - .vl_vfpd = 3, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .dp_enabled = 1, -}; - -static struct edp_device_info edp_info = { - .disp_info = { - .h_res = 2560, - .h_sync_width = 32, - .h_back_porch = 80, - .h_front_porch = 48, - .v_res = 1600, - .v_sync_width = 6, - .v_back_porch = 37, - .v_front_porch = 3, - .v_sync_rate = 60, - }, - .lt_info = { - .lt_status = DP_LT_NONE, - }, - .video_info = { - .master_mode = 0, - .bist_mode = DP_DISABLE, - .bist_pattern = NO_PATTERN, - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - }, -}; - -static struct exynos_dp_platform_data dp_platform_data = { - .edp_dev_info = &edp_info, -}; - -void init_panel_info(vidinfo_t *vid) -{ - vid->rgb_mode = MODE_RGB_P; - exynos_set_dp_platform_data(&dp_platform_data); -} -#endif diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig new file mode 100644 index 0000000000..a9d62fffa5 --- /dev/null +++ b/board/samsung/smdk5420/Kconfig @@ -0,0 +1,51 @@ +if TARGET_ODROID_XU3 + +config SYS_BOARD + default "smdk5420" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "odroid_xu3" + +endif + +if TARGET_PEACH_PI + +config SYS_BOARD + default "smdk5420" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "peach-pi" + +endif + +if TARGET_PEACH_PIT + +config SYS_BOARD + default "smdk5420" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "peach-pit" + +endif + +if TARGET_SMDK5420 + +config SYS_BOARD + default "smdk5420" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "smdk5420" + +endif diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS new file mode 100644 index 0000000000..1423f83995 --- /dev/null +++ b/board/samsung/smdk5420/MAINTAINERS @@ -0,0 +1,10 @@ +SMDK5420 BOARD +M: Akshay Saraswat +S: Maintained +F: board/samsung/smdk5420/ +F: include/configs/peach-pit.h +F: configs/peach-pit_defconfig +F: include/configs/smdk5420.h +F: configs/smdk5420_defconfig +F: include/configs/peach-pi.h +F: configs/peach-pi_defconfig diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile new file mode 100644 index 0000000000..c2f8886c99 --- /dev/null +++ b/board/samsung/smdk5420/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2013 Samsung Electronics +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += smdk5420_spl.o + +ifndef CONFIG_SPL_BUILD +obj-y += smdk5420.o +endif diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c new file mode 100644 index 0000000000..1aca9fabd9 --- /dev/null +++ b/board/samsung/smdk5420/smdk5420.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int exynos_init(void) +{ + return 0; +} + +#ifdef CONFIG_LCD +static int has_edp_bridge(void) +{ + int node; + + node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625); + + /* No node for bridge in device tree. */ + if (node <= 0) + return 0; + + /* Default is with bridge ic */ + return 1; +} + +void exynos_lcd_power_on(void) +{ + int ret; + +#ifdef CONFIG_POWER_TPS65090 + ret = tps65090_init(); + if (ret < 0) { + printf("%s: tps65090_init() failed\n", __func__); + return; + } + + tps65090_fet_enable(6); +#endif + + mdelay(5); + + /* TODO(ajaykumar.rs@samsung.com): Use device tree */ + gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#"); + gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */ + mdelay(10); + gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#"); + gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */ + gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd"); + gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */ + gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE); + + if (has_edp_bridge()) + if (parade_init(gd->fdt_blob)) + printf("%s: ps8625_init() failed\n", __func__); +} + +void exynos_backlight_on(unsigned int onoff) +{ + /* For PWM */ + gpio_request(EXYNOS5420_GPIO_B20, "backlight_on"); + gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1)); + gpio_set_value(EXYNOS5420_GPIO_B20, 1); + +#ifdef CONFIG_POWER_TPS65090 + tps65090_fet_enable(1); +#endif +} +#endif + +int board_get_revision(void) +{ + return 0; +} diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c new file mode 100644 index 0000000000..73359f784c --- /dev/null +++ b/board/samsung/smdk5420/smdk5420_spl.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirM", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 900, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .mem_manuf = MEM_MANUF_SAMSUNG, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* Will hang if SIGNATURE dont match */ + while (1) + ; + } + + return &machine_param; +} diff --git a/board/samsung/smdkc100/Kconfig b/board/samsung/smdkc100/Kconfig new file mode 100644 index 0000000000..d2157b4d05 --- /dev/null +++ b/board/samsung/smdkc100/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SMDKC100 + +config SYS_BOARD + default "smdkc100" + +config SYS_VENDOR + default "samsung" + +config SYS_SOC + default "s5pc1xx" + +config SYS_CONFIG_NAME + default "smdkc100" + +endif diff --git a/board/samsung/smdkc100/MAINTAINERS b/board/samsung/smdkc100/MAINTAINERS new file mode 100644 index 0000000000..39949e4dc7 --- /dev/null +++ b/board/samsung/smdkc100/MAINTAINERS @@ -0,0 +1,6 @@ +SMDKC100 BOARD +M: Minkyu Kang +S: Maintained +F: board/samsung/smdkc100/ +F: include/configs/smdkc100.h +F: configs/smdkc100_defconfig diff --git a/board/samsung/smdkc100/Makefile b/board/samsung/smdkc100/Makefile index 7d4e984e3a..0bcf4e5de5 100644 --- a/board/samsung/smdkc100/Makefile +++ b/board/samsung/smdkc100/Makefile @@ -8,26 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := smdkc100.o -COBJS-$(CONFIG_SAMSUNG_ONENAND) += onenand.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := smdkc100.o +obj-$(CONFIG_SAMSUNG_ONENAND) += onenand.o +obj-y += lowlevel_init.o diff --git a/board/samsung/smdkc100/config.mk b/board/samsung/smdkc100/config.mk deleted file mode 100644 index 3a08bb17a5..0000000000 --- a/board/samsung/smdkc100/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (C) 2008 # Samsung Elecgtronics -# Kyungmin Park -# - -# On S5PC100 we use the 128 MiB OneDRAM bank at -# -# 0x30000000 to 0x35000000 (80MiB) -# 0x38000000 to 0x40000000 (128MiB) -# -# On S5PC110 we use the 128 MiB OneDRAM bank at -# -# 0x30000000 to 0x35000000 (80MiB) -# 0x40000000 to 0x48000000 (128MiB) -# -CONFIG_SYS_TEXT_BASE = 0x34800000 diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 4df0974af5..65e6b7a73a 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -17,9 +17,6 @@ * r5 has zero always */ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: mov r9, lr diff --git a/board/samsung/smdkc100/mem_setup.S b/board/samsung/smdkc100/mem_setup.S deleted file mode 100644 index 2f2df0b7eb..0000000000 --- a/board/samsung/smdkc100/mem_setup.S +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx - * - * Copyright (C) 2009 Samsung Electrnoics - * Inki Dae - * Heungjun Kim - * Minkyu Kang - * Kyungmin Park - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - ldr r6, =S5PC100_DMC_BASE @ 0xE6000000 - - /* DLL parameter setting */ - ldr r1, =0x50101000 - str r1, [r6, #0x018] @ PHYCONTROL0 - ldr r1, =0xf4 - str r1, [r6, #0x01C] @ PHYCONTROL1 - ldr r1, =0x0 - str r1, [r6, #0x020] @ PHYCONTROL2 - - /* DLL on */ - ldr r1, =0x50101002 - str r1, [r6, #0x018] @ PHYCONTROL0 - - /* DLL start */ - ldr r1, =0x50101003 - str r1, [r6, #0x018] @ PHYCONTROL0 - - /* Force value locking for DLL off */ - str r1, [r6, #0x018] @ PHYCONTROL0 - - /* DLL off */ - ldr r1, =0x50101001 - str r1, [r6, #0x018] @ PHYCONTROL0 - - /* auto refresh off */ - ldr r1, =0xff001010 - str r1, [r6, #0x000] @ CONCONTROL - - /* - * Burst Length 4, 2 chips, 32-bit, LPDDR - * OFF: dynamic self refresh, force precharge, dynamic power down off - */ - ldr r1, =0x00212100 - str r1, [r6, #0x004] @ MEMCONTROL - - /* - * Note: - * If Bank0 has OneDRAM we place it at 0x2800'0000 - * So finally Bank1 should address start at at 0x2000'0000 - */ - mov r4, #0x0 - -swap_memory: - /* - * Bank0 - * 0x30 -> 0x30000000 - * 0xf8 -> 0x37FFFFFF - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - * [ 7:4 ] 2: 14 bits - * [ 3:0 ] 2: 4 banks - */ - ldr r1, =0x30f80222 - /* if r4 is 1, swap the bank */ - cmp r4, #0x1 - orreq r1, r1, #0x08000000 - str r1, [r6, #0x008] @ MEMCONFIG0 - - /* - * Bank1 - * 0x38 -> 0x38000000 - * 0xf8 -> 0x3fFFFFFF - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - * [ 7:4 ] 2: 14 bits - * [ 3:0 ] 2: 4 banks - */ - ldr r1, =0x38f80222 - /* if r4 is 1, swap the bank */ - cmp r4, #0x1 - biceq r1, r1, #0x08000000 - str r1, [r6, #0x00c] @ MEMCONFIG1 - - ldr r1, =0x20000000 - str r1, [r6, #0x014] @ PRECHCONFIG - - /* - * FIXME: Please verify these values - * 7.8us * 166MHz %LE %LONG1294(0x50E) - * 7.8us * 133MHz %LE %LONG1038(0x40E), - * 7.8us * 100MHz %LE %LONG780(0x30C), - * 7.8us * 20MHz %LE %LONG156(0x9C), - * 7.8us * 10MHz %LE %LONG78(0x4E) - */ - ldr r1, =0x0000050e - str r1, [r6, #0x030] @ TIMINGAREF - - /* 166 MHz */ - ldr r1, =0x0c233287 - str r1, [r6, #0x034] @ TIMINGROW - - /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */ - ldr r1, =0x32330303 - str r1, [r6, #0x038] @ TIMINGDATA - - /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */ - ldr r1, =0x04141433 - str r1, [r6, #0x03C] @ TIMINGPOWER - - /* chip0 Deselect */ - ldr r1, =0x07000000 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip0 PALL */ - ldr r1, =0x01000000 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip0 REFA */ - ldr r1, =0x05000000 - str r1, [r6, #0x010] @ DIRECTCMD - /* chip0 REFA */ - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */ - ldr r1, =0x00000032 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip1 Deselect */ - ldr r1, =0x07100000 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip1 PALL */ - ldr r1, =0x01100000 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip1 REFA */ - ldr r1, =0x05100000 - str r1, [r6, #0x010] @ DIRECTCMD - /* chip1 REFA */ - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */ - ldr r1, =0x00100032 - str r1, [r6, #0x010] @ DIRECTCMD - - /* auto refresh on */ - ldr r1, =0xff002030 - str r1, [r6, #0x000] @ CONCONTROL - - /* PwrdnConfig */ - ldr r1, =0x00100002 - str r1, [r6, #0x028] @ PWRDNCONFIG - - /* BL%LE %LONG */ - ldr r1, =0xff212100 - str r1, [r6, #0x004] @ MEMCONTROL - - - /* Try to test memory area */ - cmp r4, #0x1 - beq 1f - - mov r4, #0x1 - ldr r1, =0x37ffff00 - str r4, [r1] - str r4, [r1, #0x4] @ dummy write - ldr r0, [r1] - cmp r0, r4 - bne swap_memory - -1: - mov pc, lr - - .ltorg diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 860c851b25..66b6a9801f 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -7,9 +7,9 @@ */ #include +#include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -21,11 +21,8 @@ static void smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; - struct s5pc100_gpio *const gpio = - (struct s5pc100_gpio *)samsung_get_base_gpio(); - /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/samsung/smdkv310/Kconfig b/board/samsung/smdkv310/Kconfig new file mode 100644 index 0000000000..a6fd657697 --- /dev/null +++ b/board/samsung/smdkv310/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SMDKV310 + +config SYS_BOARD + default "smdkv310" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "smdkv310" + +endif diff --git a/board/samsung/smdkv310/MAINTAINERS b/board/samsung/smdkv310/MAINTAINERS new file mode 100644 index 0000000000..1e058cb504 --- /dev/null +++ b/board/samsung/smdkv310/MAINTAINERS @@ -0,0 +1,6 @@ +SMDKV310 BOARD +M: Chander Kashyap +S: Maintained +F: board/samsung/smdkv310/ +F: include/configs/smdkv310.h +F: configs/smdkv310_defconfig diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile index 5806f0e399..de0da167be 100644 --- a/board/samsung/smdkv310/Makefile +++ b/board/samsung/smdkv310/Makefile @@ -4,38 +4,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -ifndef CONFIG_SPL_BUILD -COBJS += smdkv310.o -endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -ALL := $(obj).depend $(LIB) - ifdef CONFIG_SPL_BUILD -ALL += $(OBJTREE)/tools/mk$(BOARD)spl -endif +# necessary to create built-in.o +obj- := __dummy__.o -all: $(ALL) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -ifdef CONFIG_SPL_BUILD -$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c - $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +hostprogs-y := tools/mksmdkv310spl +always := $(hostprogs-y) +else +obj-y += smdkv310.o endif - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 81a306082d..cb7f9b0ac8 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -5,25 +5,23 @@ */ #include +#include #include #include #include -#include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; static void smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); @@ -38,9 +36,6 @@ static void smc9115_pre_init(void) int board_init(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - smc9115_pre_init(); gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); @@ -103,21 +98,21 @@ int board_mmc_init(bd_t *bis) * GPK2[2] SD_2_CDn * GPK2[3:6] SD_2_DATA[0:3](2) */ - for (i = 0; i < 7; i++) { + for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) { /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + gpio_set_drv(i, S5P_GPIO_DRV_4X); /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); continue; } /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + gpio_set_pull(i, S5P_GPIO_PULL_UP); } err = s5p_mmc_init(2, 4); return err; diff --git a/board/samsung/smdkv310/tools/mkv310_image.c b/board/samsung/smdkv310/tools/mksmdkv310spl.c similarity index 100% rename from board/samsung/smdkv310/tools/mkv310_image.c rename to board/samsung/smdkv310/tools/mksmdkv310spl.c diff --git a/board/samsung/trats/Kconfig b/board/samsung/trats/Kconfig new file mode 100644 index 0000000000..7e8377bb94 --- /dev/null +++ b/board/samsung/trats/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TRATS + +config SYS_BOARD + default "trats" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "trats" + +endif diff --git a/board/samsung/trats/MAINTAINERS b/board/samsung/trats/MAINTAINERS new file mode 100644 index 0000000000..1b219b4cfe --- /dev/null +++ b/board/samsung/trats/MAINTAINERS @@ -0,0 +1,6 @@ +TRATS BOARD +M: Lukasz Majewski +S: Maintained +F: board/samsung/trats/ +F: include/configs/trats.h +F: configs/trats_defconfig diff --git a/board/samsung/trats/Makefile b/board/samsung/trats/Makefile index 5c78517b8d..5dc8a1f7d1 100644 --- a/board/samsung/trats/Makefile +++ b/board/samsung/trats/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += trats.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += trats.o diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index c8698f30df..e163e45a58 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -10,22 +10,21 @@ #include #include #include +#include #include -#include -#include #include #include -#include #include #include #include #include #include #include -#include #include #include #include +#include +#include #include #include "setup.h" @@ -44,10 +43,8 @@ u32 get_board_rev(void) static void check_hw_revision(void); struct s3c_plat_otg_data s5pc210_otg_data; -int board_init(void) +int exynos_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR; - check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev); @@ -56,17 +53,20 @@ int board_init(void) void i2c_init_board(void) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); + int err; /* I2C_5 -> PMIC */ - s5p_gpio_direction_output(&gpio1->b, 7, 1); - s5p_gpio_direction_output(&gpio1->b, 6, 1); - /* I2C_9 -> FG */ - s5p_gpio_direction_output(&gpio2->y4, 0, 1); - s5p_gpio_direction_output(&gpio2->y4, 1, 1); + err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE); + if (err) { + debug("I2C%d not configured\n", (I2C_5)); + return; + } + + /* I2C_8 -> FG */ + gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk"); + gpio_request(EXYNOS4_GPIO_Y41, "i2c_data"); + gpio_direction_output(EXYNOS4_GPIO_Y40, 1); + gpio_direction_output(EXYNOS4_GPIO_Y41, 1); } static void trats_low_power_mode(void) @@ -276,12 +276,19 @@ static int pmic_init_max8997(void) return 0; } -int power_init_board(void) +int exynos_power_init(void) { int chrg, ret; struct power_battery *pb; struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; + /* + * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected + * to logical I2C adapter 0 + * + * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected + * to logical I2C adapter 1 + */ ret = pmic_init(I2C_5); ret |= pmic_init_max8997(); ret |= power_fg_init(I2C_9); @@ -327,7 +334,7 @@ int power_init_board(void) if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { puts("No battery detected\n"); - return -1; + return 0; } p_fg->fg->fg_battery_check(p_fg, p_bat); @@ -338,45 +345,26 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + - get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + - get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -} - static unsigned int get_hw_revision(void) { - struct exynos4_gpio_part1 *gpio = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); int hwrev = 0; + char str[10]; int i; /* hw_rev[3:0] == GPE1[3:0] */ for (i = 0; i < 4; i++) { - s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); - s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); + int pin = i + EXYNOS4_GPIO_E10; + + sprintf(str, "hw_rev%d", i); + gpio_request(pin, str); + gpio_cfg_pin(pin, S5P_GPIO_INPUT); + gpio_set_pull(pin, S5P_GPIO_PULL_NONE); } udelay(1); for (i = 0; i < 4; i++) - hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); + hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i); debug("hwrev 0x%x\n", hwrev); @@ -392,55 +380,6 @@ static void check_hw_revision(void) board_rev |= hwrev; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tTRATS\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - struct exynos4_gpio_part2 *gpio = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int err; - - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ - s5p_gpio_direction_output(&gpio->k0, 2, 1); - s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - else - err = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio->x3, 4)) { - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - else - err = s5p_mmc_init(2, 4); - } - - return err; -} -#endif #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) @@ -488,20 +427,26 @@ struct s3c_plat_otg_data s5pc210_otg_data = { .usb_flags = PHY0_SLEEP, }; -void board_usb_init(void) +int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - s3c_udc_probe(&s5pc210_otg_data); + return s3c_udc_probe(&s5pc210_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + struct pmic *muic = pmic_get("MAX8997_MUIC"); + if (!muic) + return 0; + + return !!muic->chrg->chrg_type(muic); } #endif static void pmic_reset(void) { - struct exynos4_gpio_part2 *gpio = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - s5p_gpio_direction_output(&gpio->x0, 7, 1); - s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); + gpio_direction_output(EXYNOS4_GPIO_X07, 1); + gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE); } static void board_clock_init(void) @@ -576,38 +521,20 @@ static void board_power_init(void) writel(0, (unsigned int)&pwr->arm_core1_configuration); } -static void board_uart_init(void) +static void exynos_uart_init(void) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int i; - - /* - * UART2 GPIOs - * GPA1CON[0] = UART_2_RXD(2) - * GPA1CON[1] = UART_2_TXD(2) - * GPA1CON[2] = I2C_3_SDA (3) - * GPA1CON[3] = I2C_3_SCL (3) - */ - - for (i = 0; i < 4; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); - } - /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ - s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); - s5p_gpio_direction_output(&gpio2->y4, 7, 1); + gpio_request(EXYNOS4_GPIO_Y47, "uart_sel"); + gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP); + gpio_direction_output(EXYNOS4_GPIO_Y47, 1); } -int board_early_init_f(void) +int exynos_early_init_f(void) { wdt_stop(); pmic_reset(); board_clock_init(); - board_uart_init(); + exynos_uart_init(); board_power_init(); return 0; @@ -615,17 +542,15 @@ int board_early_init_f(void) void exynos_reset_lcd(void) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - s5p_gpio_direction_output(&gpio2->y4, 5, 1); + gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); + gpio_direction_output(EXYNOS4_GPIO_Y45, 1); udelay(10000); - s5p_gpio_direction_output(&gpio2->y4, 5, 0); + gpio_direction_output(EXYNOS4_GPIO_Y45, 0); udelay(10000); - s5p_gpio_direction_output(&gpio2->y4, 5, 1); + gpio_direction_output(EXYNOS4_GPIO_Y45, 1); } -static int lcd_power(void) +int lcd_power(void) { int ret = 0; struct pmic *p = pmic_get("MAX8997_PMIC"); @@ -648,46 +573,7 @@ static int lcd_power(void) return 0; } -static struct mipi_dsim_config dsim_config = { - .e_interface = DSIM_VIDEO, - .e_virtual_ch = DSIM_VIRTUAL_CH_0, - .e_pixel_format = DSIM_24BPP_888, - .e_burst_mode = DSIM_BURST_SYNC_EVENT, - .e_no_data_lane = DSIM_DATA_LANE_4, - .e_byte_clk = DSIM_PLL_OUT_DIV8, - .hfp = 1, - - .p = 3, - .m = 120, - .s = 1, - - /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ - .pll_stable_time = 500, - - /* escape clk : 10MHz */ - .esc_clk = 20 * 1000000, - - /* stop state holding counter after bta change count 0 ~ 0xfff */ - .stop_holding_cnt = 0x7ff, - /* bta timeout 0 ~ 0xff */ - .bta_timeout = 0xff, - /* lp rx timeout 0 ~ 0xffff */ - .rx_timeout = 0xffff, -}; - -static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { - .lcd_panel_info = NULL, - .dsim_config = &dsim_config, -}; - -static struct mipi_dsim_lcd_device mipi_lcd_device = { - .name = "s6e8ax0", - .id = -1, - .bus_id = 0, - .platform_data = (void *)&s6e8ax0_platform_data, -}; - -static int mipi_power(void) +int mipi_power(void) { int ret = 0; struct pmic *p = pmic_get("MAX8997_PMIC"); @@ -710,119 +596,13 @@ static int mipi_power(void) return 0; } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 720, - .vl_row = 1280, - .vl_width = 720, - .vl_height = 1280, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ - - /* s6e8ax0 Panel infomation */ - .vl_hspw = 5, - .vl_hbpd = 10, - .vl_hfpd = 10, - - .vl_vspw = 2, - .vl_vbpd = 1, - .vl_vfpd = 13, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .mipi_enabled = 1, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_lcd_misc_init(vidinfo_t *vid) { - vid->logo_on = 1, - vid->resolution = HD_RESOLUTION, - vid->rgb_mode = MODE_RGB_P, - #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif - mipi_lcd_device.reverse_panel = 1; - - strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); - s6e8ax0_platform_data.lcd_power = lcd_power; - s6e8ax0_platform_data.mipi_power = mipi_power; - s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; - s6e8ax0_platform_data.lcd_panel_info = (void *)vid; - exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); +#ifdef CONFIG_S6E8AX0 s6e8ax0_init(); - exynos_set_dsim_platform_data(&s6e8ax0_platform_data); - setenv("lcdinfo", "lcd=s6e8ax0"); -} - -#ifdef CONFIG_USB_GADGET_MASS_STORAGE -static int ums_read_sector(struct ums_device *ums_dev, - ulong start, lbaint_t blkcnt, void *buf) -{ - if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num, - start + ums_dev->offset, blkcnt, buf) != blkcnt) - return -1; - - return 0; -} - -static int ums_write_sector(struct ums_device *ums_dev, - ulong start, lbaint_t blkcnt, const void *buf) -{ - if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num, - start + ums_dev->offset, blkcnt, buf) != blkcnt) - return -1; - - return 0; -} - -static void ums_get_capacity(struct ums_device *ums_dev, - long long int *capacity) -{ - long long int tmp_capacity; - - tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size) - * SECTOR_SIZE); - *capacity = ums_dev->mmc->capacity - tmp_capacity; -} - -static struct ums_board_info ums_board = { - .read_sector = ums_read_sector, - .write_sector = ums_write_sector, - .get_capacity = ums_get_capacity, - .name = "TRATS UMS disk", - .ums_dev = { - .mmc = NULL, - .dev_num = 0, - .offset = 0, - .part_size = 0. - }, -}; - -struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset, - unsigned int part_size) -{ - struct mmc *mmc; - - mmc = find_mmc_device(dev_num); - if (!mmc) - return NULL; - - ums_board.ums_dev.mmc = mmc; - ums_board.ums_dev.dev_num = dev_num; - ums_board.ums_dev.offset = offset; - ums_board.ums_dev.part_size = part_size; - - return &ums_board; -} #endif +} diff --git a/board/samsung/trats2/Kconfig b/board/samsung/trats2/Kconfig new file mode 100644 index 0000000000..5670e14fae --- /dev/null +++ b/board/samsung/trats2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TRATS2 + +config SYS_BOARD + default "trats2" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "trats2" + +endif diff --git a/board/samsung/trats2/MAINTAINERS b/board/samsung/trats2/MAINTAINERS new file mode 100644 index 0000000000..70183002f6 --- /dev/null +++ b/board/samsung/trats2/MAINTAINERS @@ -0,0 +1,6 @@ +TRATS2 BOARD +M: Lukasz Majewski +S: Maintained +F: board/samsung/trats2/ +F: include/configs/trats2.h +F: configs/trats2_defconfig diff --git a/board/samsung/trats2/Makefile b/board/samsung/trats2/Makefile new file mode 100644 index 0000000000..f501761a41 --- /dev/null +++ b/board/samsung/trats2/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2000 - 2013 Samsung Electronics Co., Ltd. All rights reserved. +# Sanghee Kim +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := trats2.o diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c new file mode 100644 index 0000000000..a7377497e5 --- /dev/null +++ b/board/samsung/trats2/trats2.c @@ -0,0 +1,433 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved. + * Sanghee Kim + * Piotr Wilczek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned int board_rev = -1; + +static inline u32 get_model_rev(void); + +static void check_hw_revision(void) +{ + int modelrev = 0; + char str[12]; + int i; + + /* + * GPM1[1:0]: MODEL_REV[1:0] + * Don't set as pull-none for these N/C pin. + * TRM say that it may cause unexcepted state and leakage current. + * and pull-none is only for output function. + */ + for (i = 0; i < 2; i++) { + int pin = i + EXYNOS4X12_GPIO_M10; + + sprintf(str, "model_rev%d", i); + gpio_request(pin, str); + gpio_cfg_pin(pin, S5P_GPIO_INPUT); + } + + /* GPM1[5:2]: HW_REV[3:0] */ + for (i = 0; i < 4; i++) { + int pin = i + EXYNOS4X12_GPIO_M12; + + sprintf(str, "hw_rev%d", i); + gpio_request(pin, str); + gpio_cfg_pin(pin, S5P_GPIO_INPUT); + gpio_set_pull(pin, S5P_GPIO_PULL_NONE); + } + + /* GPM1[1:0]: MODEL_REV[1:0] */ + for (i = 0; i < 2; i++) + modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i); + + /* board_rev[15:8] = model */ + board_rev = modelrev << 8; +} + +u32 get_board_rev(void) +{ + return board_rev; +} + +static inline u32 get_model_rev(void) +{ + return (board_rev >> 8) & 0xff; +} + +static void board_external_gpio_init(void) +{ + /* + * some pins which in alive block are connected with external pull-up + * but it's default setting is pull-down. + * if that pin set as input then that floated + */ + + gpio_set_pull(EXYNOS4X12_GPIO_X02, S5P_GPIO_PULL_NONE); /* PS_ALS_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X04, S5P_GPIO_PULL_NONE); /* TSP_nINT */ + gpio_set_pull(EXYNOS4X12_GPIO_X07, S5P_GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ + gpio_set_pull(EXYNOS4X12_GPIO_X15, S5P_GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ + gpio_set_pull(EXYNOS4X12_GPIO_X20, S5P_GPIO_PULL_NONE); /* VOL_UP */ + gpio_set_pull(EXYNOS4X12_GPIO_X21, S5P_GPIO_PULL_NONE); /* VOL_DOWN */ + gpio_set_pull(EXYNOS4X12_GPIO_X23, S5P_GPIO_PULL_NONE); /* FUEL_ALERT */ + gpio_set_pull(EXYNOS4X12_GPIO_X24, S5P_GPIO_PULL_NONE); /* ADC_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X27, S5P_GPIO_PULL_NONE); /* nPOWER */ + gpio_set_pull(EXYNOS4X12_GPIO_X30, S5P_GPIO_PULL_NONE); /* WPC_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X35, S5P_GPIO_PULL_NONE); /* OK_KEY */ + gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE); /* HDMI_HPD */ +} + +#ifdef CONFIG_SYS_I2C_INIT_BOARD +static void board_init_i2c(void) +{ + int err; + + /* I2C_7 */ + err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE); + if (err) { + debug("I2C%d not configured\n", (I2C_7)); + return; + } + + /* I2C_8 */ + gpio_request(EXYNOS4X12_GPIO_F14, "i2c8_clk"); + gpio_request(EXYNOS4X12_GPIO_F15, "i2c8_data"); + gpio_direction_output(EXYNOS4X12_GPIO_F14, 1); + gpio_direction_output(EXYNOS4X12_GPIO_F15, 1); + + /* I2C_9 */ + gpio_request(EXYNOS4X12_GPIO_M21, "i2c9_clk"); + gpio_request(EXYNOS4X12_GPIO_M20, "i2c9_data"); + gpio_direction_output(EXYNOS4X12_GPIO_M21, 1); + gpio_direction_output(EXYNOS4X12_GPIO_M20, 1); +} +#endif + +#ifdef CONFIG_SYS_I2C_SOFT +int get_soft_i2c_scl_pin(void) +{ + if (I2C_ADAP_HWNR) + return EXYNOS4X12_GPIO_M21; /* I2C9 */ + else + return EXYNOS4X12_GPIO_F14; /* I2C8 */ +} + +int get_soft_i2c_sda_pin(void) +{ + if (I2C_ADAP_HWNR) + return EXYNOS4X12_GPIO_M20; /* I2C9 */ + else + return EXYNOS4X12_GPIO_F15; /* I2C8 */ +} +#endif + +int exynos_early_init_f(void) +{ + board_external_gpio_init(); + + return 0; +} + +static int pmic_init_max77686(void); + +int exynos_init(void) +{ + struct exynos4_power *pwr = + (struct exynos4_power *)samsung_get_base_power(); + + check_hw_revision(); + printf("HW Revision:\t0x%04x\n", board_rev); + + /* + * First bootloader on the TRATS2 platform uses + * INFORM4 and INFORM5 registers for recovery + * + * To indicate correct boot chain - those two + * registers must be cleared out + */ + writel(0, &pwr->inform4); + writel(0, &pwr->inform5); + + return 0; +} + +int exynos_power_init(void) +{ + int chrg; + struct power_battery *pb; + struct pmic *p_chrg, *p_muic, *p_fg, *p_bat; + +#ifdef CONFIG_SYS_I2C_INIT_BOARD + board_init_i2c(); +#endif + pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */ + pmic_init_max77686(); + pmic_init_max77693(I2C_10); /* I2C adapter 10 - bus name soft1 */ + power_muic_init(I2C_10); /* I2C adapter 10 - bus name soft1 */ + power_fg_init(I2C_9); /* I2C adapter 9 - bus name soft0 */ + power_bat_init(0); + + p_chrg = pmic_get("MAX77693_PMIC"); + if (!p_chrg) { + puts("MAX77693_PMIC: Not found\n"); + return -ENODEV; + } + + p_muic = pmic_get("MAX77693_MUIC"); + if (!p_muic) { + puts("MAX77693_MUIC: Not found\n"); + return -ENODEV; + } + + p_fg = pmic_get("MAX77693_FG"); + if (!p_fg) { + puts("MAX17042_FG: Not found\n"); + return -ENODEV; + } + + if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0) + puts("No battery detected\n"); + + p_bat = pmic_get("BAT_TRATS2"); + if (!p_bat) { + puts("BAT_TRATS2: Not found\n"); + return -ENODEV; + } + + p_fg->parent = p_bat; + p_chrg->parent = p_bat; + p_muic->parent = p_bat; + + p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); + + pb = p_bat->pbat; + chrg = p_muic->chrg->chrg_type(p_muic); + debug("CHARGER TYPE: %d\n", chrg); + + if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { + puts("No battery detected\n"); + return 0; + } + + p_fg->fg->fg_battery_check(p_fg, p_bat); + + if (pb->bat->state == CHARGE && chrg == CHARGER_USB) + puts("CHARGE Battery !\n"); + + return 0; +} + +#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{ + int ret = 0; + unsigned int val; + struct pmic *p, *p_pmic, *p_muic; + + p_pmic = pmic_get("MAX77686_PMIC"); + if (!p_pmic) + return -ENODEV; + + if (pmic_probe(p_pmic)) + return -1; + + p_muic = pmic_get("MAX77693_MUIC"); + if (!p_muic) + return -ENODEV; + + if (pmic_probe(p_muic)) + return -1; + + if (on) { + ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON); + if (ret) + return -1; + + p = pmic_get("MAX77693_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + /* SAFEOUT */ + ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val); + if (ret) + return -1; + + val |= MAX77693_ENSAFEOUT1; + ret = pmic_reg_write(p, MAX77693_SAFEOUT, val); + if (ret) + return -1; + + /* PATH: USB */ + ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1, + MAX77693_MUIC_CTRL1_DN1DP2); + + } else { + ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM); + if (ret) + return -1; + + /* PATH: UART */ + ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1, + MAX77693_MUIC_CTRL1_UT1UR2); + } + + if (ret) + return -1; + + return 0; +} + +struct s3c_plat_otg_data s5pc210_otg_data = { + .phy_control = s5pc210_phy_control, + .regs_phy = EXYNOS4X12_USBPHY_BASE, + .regs_otg = EXYNOS4X12_USBOTG_BASE, + .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, + .usb_flags = PHY0_SLEEP, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc210_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + struct pmic *muic = pmic_get("MAX77693_MUIC"); + if (!muic) + return 0; + + return !!muic->chrg->chrg_type(muic); +} +#endif + +static int pmic_init_max77686(void) +{ + struct pmic *p = pmic_get("MAX77686_PMIC"); + + if (pmic_probe(p)) + return -1; + + /* BUCK/LDO Output Voltage */ + max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 VTF_2.8V */ + max77686_set_ldo_voltage(p, 23, 3300000); /* LDO23 TSP_AVDD_3.3V*/ + max77686_set_ldo_voltage(p, 24, 1800000); /* LDO24 TSP_VDD_1.8V */ + + /* BUCK/LDO Output Mode */ + max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */ + max77686_set_buck_mode(p, 2, OPMODE_ON); /* BUCK2 VARM_1.0V_AP */ + max77686_set_buck_mode(p, 3, OPMODE_ON); /* BUCK3 VINT_1.0V_AP */ + max77686_set_buck_mode(p, 4, OPMODE_ON); /* BUCK4 VG3D_1.0V_AP */ + max77686_set_buck_mode(p, 5, OPMODE_ON); /* BUCK5 VMEM_1.2V_AP */ + max77686_set_buck_mode(p, 6, OPMODE_ON); /* BUCK6 VCC_SUB_1.35V*/ + max77686_set_buck_mode(p, 7, OPMODE_ON); /* BUCK7 VCC_SUB_2.0V */ + max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */ + max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/ + + max77686_set_ldo_mode(p, 1, OPMODE_LPM); /* LDO1 VALIVE_1.0V_AP*/ + max77686_set_ldo_mode(p, 2, OPMODE_STANDBY); /* LDO2 VM1M2_1.2V_AP */ + max77686_set_ldo_mode(p, 3, OPMODE_LPM); /* LDO3 VCC_1.8V_AP */ + max77686_set_ldo_mode(p, 4, OPMODE_LPM); /* LDO4 VCC_2.8V_AP */ + max77686_set_ldo_mode(p, 5, OPMODE_OFF); /* LDO5_VCC_1.8V_IO */ + max77686_set_ldo_mode(p, 6, OPMODE_STANDBY); /* LDO6 VMPLL_1.0V_AP */ + max77686_set_ldo_mode(p, 7, OPMODE_STANDBY); /* LDO7 VPLL_1.0V_AP */ + max77686_set_ldo_mode(p, 8, OPMODE_LPM); /* LDO8 VMIPI_1.0V_AP */ + max77686_set_ldo_mode(p, 9, OPMODE_OFF); /* CAM_ISP_MIPI_1.2*/ + max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/ + max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/ + max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/ + max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */ + max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */ + max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/ + max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/ + max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/ + max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/ + max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */ + max77686_set_ldo_mode(p, 20, OPMODE_ON); /* LDO20 VDDQ_PRE_1.8V*/ + max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */ + max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/ + max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/ + max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */ + max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */ + max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/ + + return 0; +} + +/* + * LCD + */ + +#ifdef CONFIG_LCD +int mipi_power(void) +{ + struct pmic *p = pmic_get("MAX77686_PMIC"); + + /* LDO8 VMIPI_1.0V_AP */ + max77686_set_ldo_mode(p, 8, OPMODE_ON); + /* LDO10 VMIPI_1.8V_AP */ + max77686_set_ldo_mode(p, 10, OPMODE_ON); + + return 0; +} + +void exynos_lcd_power_on(void) +{ + struct pmic *p = pmic_get("MAX77686_PMIC"); + + /* LCD_2.2V_EN: GPC0[1] */ + gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en"); + gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP); + gpio_direction_output(EXYNOS4X12_GPIO_C01, 1); + + /* LDO25 VCC_3.1V_LCD */ + pmic_probe(p); + max77686_set_ldo_voltage(p, 25, 3100000); + max77686_set_ldo_mode(p, 25, OPMODE_LPM); +} + +void exynos_reset_lcd(void) +{ + /* reset lcd */ + gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset"); + gpio_direction_output(EXYNOS4X12_GPIO_F21, 0); + udelay(10); + gpio_set_value(EXYNOS4X12_GPIO_F21, 1); +} + +void exynos_lcd_misc_init(vidinfo_t *vid) +{ +#ifdef CONFIG_TIZEN + get_tizen_logo_info(vid); +#endif +#ifdef CONFIG_S6E8AX0 + s6e8ax0_init(); +#endif +} +#endif /* LCD */ diff --git a/board/samsung/universal_c210/Kconfig b/board/samsung/universal_c210/Kconfig new file mode 100644 index 0000000000..e692668115 --- /dev/null +++ b/board/samsung/universal_c210/Kconfig @@ -0,0 +1,12 @@ +if TARGET_S5PC210_UNIVERSAL + +config SYS_BOARD + default "universal_c210" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "s5pc210_universal" + +endif diff --git a/board/samsung/universal_c210/MAINTAINERS b/board/samsung/universal_c210/MAINTAINERS new file mode 100644 index 0000000000..676067813b --- /dev/null +++ b/board/samsung/universal_c210/MAINTAINERS @@ -0,0 +1,6 @@ +UNIVERSAL_C210 BOARD +M: Przemyslaw Marczak +S: Maintained +F: board/samsung/universal_c210/ +F: include/configs/s5pc210_universal.h +F: configs/s5pc210_universal_defconfig diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile index 42bde81278..4ceeeb62b5 100644 --- a/board/samsung/universal_c210/Makefile +++ b/board/samsung/universal_c210/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := universal.o onenand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := universal.o onenand.o diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 2e1dba6a48..df4671394f 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -12,21 +12,20 @@ #include #include #include -#include -#include #include #include -#include #include #include +#include #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; unsigned int board_rev; u32 get_board_rev(void) @@ -41,11 +40,15 @@ static int get_hwrev(void) static void init_pmic_lcd(void); -int power_init_board(void) +int exynos_power_init(void) { int ret; - ret = pmic_init(I2C_5); + /* + * For PMIC the I2C bus is named as I2C5, but it is connected + * to logical I2C adapter 0 + */ + ret = pmic_init(I2C_0); if (ret) return ret; @@ -54,22 +57,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -} - static unsigned short get_adc_value(int channel) { struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); @@ -154,71 +141,6 @@ static void check_hw_revision(void) board_rev |= hwrev; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tUniversal C210\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int err; - - switch (get_hwrev()) { - case 0: - /* - * Set the low to enable LDO_EN - * But when you use the test board for eMMC booting - * you should set it HIGH since it removes the inverter - */ - /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - s5p_gpio_direction_output(&gpio1->e3, 6, 0); - break; - default: - /* - * Default reset state is High and there's no inverter - * But set it as HIGH to ensure - */ - /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - s5p_gpio_direction_output(&gpio1->e1, 3, 1); - break; - } - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - else - err = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - else - err = s5p_mmc_init(2, 4); - } - - return err; - -} -#endif - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { @@ -266,59 +188,18 @@ struct s3c_plat_otg_data s5pc210_otg_data = { }; #endif -int board_early_init_f(void) -{ - wdt_stop(); - - return 0; -} - -#ifdef CONFIG_SOFT_SPI -static void soft_spi_init(void) +int board_usb_init(int index, enum usb_init_type init) { - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK, - CONFIG_SOFT_SPI_MODE & SPI_CPOL); - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1); - gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO); - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc210_otg_data); } -void spi_cs_activate(struct spi_slave *slave) +int exynos_early_init_f(void) { - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); - SPI_SCL(1); - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void universal_spi_scl(int bit) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit); -} - -void universal_spi_sda(int bit) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit); -} + wdt_stop(); -int universal_spi_read(void) -{ - return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO); + return 0; } -#endif static void init_pmic_lcd(void) { @@ -374,46 +255,50 @@ void exynos_cfg_lcd_gpio(void) for (i = 0; i < 8; i++) { /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2)); /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE); /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); } - for (i = 0; i < f3_end; i++) { + for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) { /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(2)); /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + gpio_set_rate(i, S5P_GPIO_DRV_SLOW); } /* gpio pad configuration for LCD reset. */ - s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT); + gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); + gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT); +} - spi_init(); +int mipi_power(void) +{ + return 0; } void exynos_reset_lcd(void) { - s5p_gpio_set_value(&gpio2->y4, 5, 1); + gpio_set_value(EXYNOS4_GPIO_Y45, 1); udelay(10000); - s5p_gpio_set_value(&gpio2->y4, 5, 0); + gpio_set_value(EXYNOS4_GPIO_Y45, 0); udelay(10000); - s5p_gpio_set_value(&gpio2->y4, 5, 1); + gpio_set_value(EXYNOS4_GPIO_Y45, 1); udelay(100); } @@ -431,39 +316,6 @@ void exynos_lcd_power_on(void) pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON); } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 480, - .vl_row = 800, - .vl_width = 480, - .vl_height = 800, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - - .vl_bpix = 5, /* Bits per pixel */ - - /* LD9040 LCD Panel */ - .vl_hspw = 2, - .vl_hbpd = 16, - .vl_hfpd = 16, - - .vl_vspw = 2, - .vl_vbpd = 8, - .vl_vfpd = 8, - .vl_cmd_allow_len = 0xf, - - .win_id = 0, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 10000, - .reset_delay = 10000, - .interface_mode = FIMD_RGB_INTERFACE, - .mipi_enabled = 0, -}; - void exynos_cfg_ldo(void) { ld9040_cfg_ldo(); @@ -474,12 +326,49 @@ void exynos_enable_ldo(unsigned int onoff) ld9040_enable_ldo(onoff); } -void init_panel_info(vidinfo_t *vid) +int exynos_init(void) { - vid->logo_on = 1; - vid->resolution = HD_RESOLUTION; - vid->rgb_mode = MODE_RGB_P; + char buf[16]; + + gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; + + switch (get_hwrev()) { + case 0: + /* + * Set the low to enable LDO_EN + * But when you use the test board for eMMC booting + * you should set it HIGH since it removes the inverter + */ + /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ + gpio_request(EXYNOS4_GPIO_E36, "ldo_en"); + gpio_direction_output(EXYNOS4_GPIO_E36, 0); + break; + default: + /* + * Default reset state is High and there's no inverter + * But set it as HIGH to ensure + */ + /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ + gpio_request(EXYNOS4_GPIO_E13, "massmemory_en"); + gpio_direction_output(EXYNOS4_GPIO_E13, 1); + break; + } + + /* Request soft I2C gpios */ + sprintf(buf, "soft_i2c_scl"); + gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf); + sprintf(buf, "soft_i2c_sda"); + gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf); + + check_hw_revision(); + printf("HW Revision:\t0x%x\n", board_rev); + + return 0; +} + +void exynos_lcd_misc_init(vidinfo_t *vid) +{ #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif @@ -490,20 +379,3 @@ void init_panel_info(vidinfo_t *vid) setenv("lcdinfo", "lcd=ld9040"); } - -int board_init(void) -{ - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - - gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - -#ifdef CONFIG_SOFT_SPI - soft_spi_init(); -#endif - check_hw_revision(); - printf("HW Revision:\t0x%x\n", board_rev); - - return 0; -} diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS new file mode 100644 index 0000000000..10d88a28a6 --- /dev/null +++ b/board/sandbox/MAINTAINERS @@ -0,0 +1,6 @@ +SANDBOX BOARD +M: Simon Glass +S: Maintained +F: board/sandbox/ +F: include/configs/sandbox.h +F: configs/sandbox_defconfig diff --git a/board/sandbox/Makefile b/board/sandbox/Makefile new file mode 100644 index 0000000000..a0b9880d6e --- /dev/null +++ b/board/sandbox/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := sandbox.o diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox new file mode 100644 index 0000000000..3c0df17845 --- /dev/null +++ b/board/sandbox/README.sandbox @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Native Execution of U-Boot +========================== + +The 'sandbox' architecture is designed to allow U-Boot to run under Linux on +almost any hardware. To achieve this it builds U-Boot (so far as possible) +as a normal C application with a main() and normal C libraries. + +All of U-Boot's architecture-specific code therefore cannot be built as part +of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test +all the generic code, not specific to any one architecture. The idea is to +create unit tests which we can run to test this upper level code. + +CONFIG_SANDBOX is defined when building a native board. + +The board name is 'sandbox' but the vendor name is unset, so there is a +single board in board/sandbox. + +CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian +machines. + +Note that standalone/API support is not available at present. + + +Basic Operation +--------------- + +To run sandbox U-Boot use something like: + + make sandbox_defconfig all + ./u-boot + +Note: + If you get errors about 'sdl-config: Command not found' you may need to + install libsdl1.2-dev or similar to get SDL support. Alternatively you can + build sandbox without SDL (i.e. no display/keyboard support) by removing + the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using: + + make sandbox_defconfig all NO_SDL=1 + ./u-boot + + +U-Boot will start on your computer, showing a sandbox emulation of the serial +console: + + +U-Boot 2014.04 (Mar 20 2014 - 19:06:00) + +DRAM: 128 MiB +Using default environment + +In: serial +Out: lcd +Err: lcd +=> + +You can issue commands as your would normally. If the command you want is +not supported you can add it to include/configs/sandbox.h. + +To exit, type 'reset' or press Ctrl-C. + + +Console / LCD support +--------------------- + +Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the +sandbox with LCD and keyboard emulation, using something like: + + ./u-boot -d u-boot.dtb -l + +This will start U-Boot with a window showing the contents of the LCD. If +that window has the focus then you will be able to type commands as you +would on the console. You can adjust the display settings in the device +tree file - see arch/sandbox/dts/sandbox.dts. + + +Command-line Options +-------------------- + +Various options are available, mostly for test purposes. Use -h to see +available options. Some of these are described below. + +The terminal is normally in what is called 'raw-with-sigs' mode. This means +that you can use arrow keys for command editing and history, but if you +press Ctrl-C, U-Boot will exit instead of handling this as a keypress. + +Other options are 'raw' (so Ctrl-C is handled within U-Boot) and 'cooked' +(where the terminal is in cooked mode and cursor keys will not work, Ctrl-C +will exit). + +As mentioned above, -l causes the LCD emulation window to be shown. + +A device tree binary file can be provided with -d. If you edit the source +(it is stored at arch/sandbox/dts/sandbox.dts) you must rebuild U-Boot to +recreate the binary file. + +To execute commands directly, use the -c option. You can specify a single +command, or multiple commands separated by a semicolon, as is normal in +U-Boot. Be careful with quoting as the shall will normally process and +swallow quotes. When -c is used, U-Boot exists after the command is complete, +but you can force it to go to interactive mode instead with -i. + + +Memory Emulation +---------------- + +Memory emulation is supported, with the size set by CONFIG_SYS_SDRAM_SIZE. +The -m option can be used to read memory from a file on start-up and write +it when shutting down. This allows preserving of memory contents across +test runs. You can tell U-Boot to remove the memory file after it is read +(on start-up) with the --rm_memory option. + +To access U-Boot's emulated memory within the code, use map_sysmem(). This +function is used throughout U-Boot to ensure that emulated memory is used +rather than the U-Boot application memory. This provides memory starting +at 0 and extending to the size of the emulation. + + +Storing State +------------- + +With sandbox you can write drivers which emulate the operation of drivers on +real devices. Some of these drivers may want to record state which is +preserved across U-Boot runs. This is particularly useful for testing. For +example, the contents of a SPI flash chip should not disappear just because +U-Boot exits. + +State is stored in a device tree file in a simple format which is driver- +specific. You then use the -s option to specify the state file. Use -r to +make U-Boot read the state on start-up (otherwise it starts empty) and -w +to write it on exit (otherwise the stored state is left unchanged and any +changes U-Boot made will be lost). You can also use -n to tell U-Boot to +ignore any problems with missing state. This is useful when first running +since the state file will be empty. + +The device tree file has one node for each driver - the driver can store +whatever properties it likes in there. See 'Writing Sandbox Drivers' below +for more details on how to get drivers to read and write their state. + + +Running and Booting +------------------- + +Since there is no machine architecture, sandbox U-Boot cannot actually boot +a kernel, but it does support the bootm command. Filesystems, memory +commands, hashing, FIT images, verified boot and many other features are +supported. + +When 'bootm' runs a kernel, sandbox will exit, as U-Boot does on a real +machine. Of course in this case, no kernel is run. + +It is also possible to tell U-Boot that it has jumped from a temporary +previous U-Boot binary, with the -j option. That binary is automatically +removed by the U-Boot that gets the -j option. This allows you to write +tests which emulate the action of chain-loading U-Boot, typically used in +a situation where a second 'updatable' U-Boot is stored on your board. It +is very risky to overwrite or upgrade the only U-Boot on a board, since a +power or other failure will brick the board and require return to the +manufacturer in the case of a consumer device. + + +Supported Drivers +----------------- + +U-Boot sandbox supports these emulations: + +- Block devices +- Chrome OS EC +- GPIO +- Host filesystem (access files on the host from within U-Boot) +- Keyboard (Chrome OS) +- LCD +- Serial (for console only) +- Sound (incomplete - see sandbox_sdl_sound_init() for details) +- SPI +- SPI flash +- TPM (Trusted Platform Module) + +Notable omissions are networking and I2C. + +A wide range of commands is implemented. Filesystems which use a block +device are supported. + +Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports +driver model (CONFIG_DM) and associated commands. + + +SPI Emulation +------------- + +Sandbox supports SPI and SPI flash emulation. + +This is controlled by the spi_sf argument, the format of which is: + + bus:cs:device:file + + bus - SPI bus number + cs - SPI chip select number + device - SPI device emulation name + file - File on disk containing the data + +For example: + + dd if=/dev/zero of=spi.bin bs=1M count=4 + ./u-boot --spi_sf 0:0:M25P16:spi.bin + +With this setup you can issue SPI flash commands as normal: + +=>sf probe +SF: Detected M25P16 with page size 64 KiB, total 2 MiB +=>sf read 0 0 10000 +SF: 65536 bytes @ 0x0 Read: OK +=> + +Since this is a full SPI emulation (rather than just flash), you can +also use low-level SPI commands: + +=>sspi 0:0 32 9f +FF202015 + +This is issuing a READ_ID command and getting back 20 (ST Micro) part +0x2015 (the M25P16). + +Drivers are connected to a particular bus/cs using sandbox's state +structure (see the 'spi' member). A set of operations must be provided +for each driver. + + +Configuration settings for the curious are: + +CONFIG_SANDBOX_SPI_MAX_BUS + The maximum number of SPI buses supported by the driver (default 1). + +CONFIG_SANDBOX_SPI_MAX_CS + The maximum number of chip selects supported by the driver + (default 10). + +CONFIG_SPI_IDLE_VAL + The idle value on the SPI bus + + +Writing Sandbox Drivers +----------------------- + +Generally you should put your driver in a file containing the word 'sandbox' +and put it in the same directory as other drivers of its type. You can then +implement the same hooks as the other drivers. + +To access U-Boot's emulated memory, use map_sysmem() as mentioned above. + +If your driver needs to store configuration or state (such as SPI flash +contents or emulated chip registers), you can use the device tree as +described above. Define handlers for this with the SANDBOX_STATE_IO macro. +See arch/sandbox/include/asm/state.h for documentation. In short you provide +a node name, compatible string and functions to read and write the state. +Since writing the state can expand the device tree, you may need to use +state_setprop() which does this automatically and avoids running out of +space. See existing code for examples. + + +Testing +------- + +U-Boot sandbox can be used to run various tests, mostly in the test/ +directory. These include: + + command_ut + - Unit tests for command parsing and handling + compression + - Unit tests for U-Boot's compression algorithms, useful for + security checking. It supports gzip, bzip2, lzma and lzo. + driver model + - test/dm/test-dm.sh to run these. + image + - Unit tests for images: + test/image/test-imagetools.sh - multi-file images + test/image/test-fit.py - FIT images + tracing + - test/trace/test-trace.sh tests the tracing system (see README.trace) + verified boot + - See test/vboot/vboot_test.sh for this + +If you change or enhance any of the above subsystems, you shold write or +expand a test and include it with your patch series submission. Test +coverage in U-Boot is limited, as we need to work to improve it. + +Note that many of these tests are implemented as commands which you can +run natively on your board if desired (and enabled). + +It would be useful to have a central script to run all of these. + +-- +Simon Glass +Updated 22-Mar-14 diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c new file mode 100644 index 0000000000..e4d4e021bc --- /dev/null +++ b/board/sandbox/sandbox.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * Pointer to initial global data area + * + * Here we initialize it. + */ +gd_t *gd; + +/* Add a simple GPIO device */ +U_BOOT_DEVICE(gpio_sandbox) = { + .name = "gpio_sandbox", +}; + +void flush_cache(unsigned long start, unsigned long size) +{ +} + +unsigned long timer_read_counter(void) +{ + return os_get_nsec() / 1000; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_VIDEO_SANDBOX_SDL + int ret; + + ret = sandbox_lcd_sdl_early_init(); + if (ret) { + puts("Could not init sandbox LCD emulation\n"); + return ret; + } +#endif + + return 0; +} +#endif + +int arch_early_init_r(void) +{ +#ifdef CONFIG_CROS_EC + if (cros_ec_board_init()) { + printf("%s: Failed to init EC\n", __func__); + return 0; + } +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + if (cros_ec_get_error()) { + /* Force console on */ + gd->flags &= ~GD_FLG_SILENT; + + printf("cros-ec communications failure %d\n", + cros_ec_get_error()); + puts("\nPlease reset with Power+Refresh\n\n"); + panic("Cannot init cros-ec device"); + return -1; + } + return 0; +} +#endif diff --git a/board/sandbox/sandbox/Makefile b/board/sandbox/sandbox/Makefile deleted file mode 100644 index 3d490b8ef8..0000000000 --- a/board/sandbox/sandbox/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (c) 2011 The Chromium OS Authors. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sandbox/sandbox/README.sandbox b/board/sandbox/sandbox/README.sandbox deleted file mode 100644 index bcb2f330fa..0000000000 --- a/board/sandbox/sandbox/README.sandbox +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -Native Execution of U-Boot -========================== - -The 'sandbox' architecture is designed to allow U-Boot to run under Linux on -almost any hardware. To achieve this it builds U-Boot (so far as possible) -as a normal C application with a main() and normal C libraries. - -All of U-Boot's architecture-specific code therefore cannot be built as part -of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test -all the generic code, not specific to any one architecture. The idea is to -create unit tests which we can run to test this upper level code. - -CONFIG_SANDBOX is defined when building a native board. - -The chosen vendor and board names are also 'sandbox', so there is a single -board in board/sandbox/sandbox. - -CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian -machines. - -Note that standalone/API support is not available at present. - -The serial driver is a very simple implementation which reads and writes to -the console. It does not set the terminal into raw mode, so cursor keys and -history will not work yet. - - -Tests ------ - -So far we have no tests, but when we do these will be documented here. diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c deleted file mode 100644 index f471cb7212..0000000000 --- a/board/sandbox/sandbox/sandbox.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include - -/* - * Pointer to initial global data area - * - * Here we initialize it. - */ -gd_t *gd; - -void flush_cache(unsigned long start, unsigned long size) -{ -} - -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} - -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -ulong get_timer(ulong base) -{ - return (os_get_nsec() / 1000000) - base; -} - -int timer_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - return 0; -} diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c deleted file mode 100644 index 81d65dd5bc..0000000000 --- a/board/sandburst/common/flash.c +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * Ported from Ebony flash support - * Travis B. Sawyer - * Sandburst Corporation - */ -#include -#include -#include - - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xfff80000} /* Boot Flash */ -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; - } - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); - - /* Write auto select command: read Manufacturer ID */ - udelay(10000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - udelay(1000); - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - udelay(1000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - udelay(1000); - - value = addr2[0]; - - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; /* => 512 kb */ - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* reset to return to reading data */ - addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - DEBUGF("Erasing sector %p\n", addr2); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c deleted file mode 100644 index b579812ccf..0000000000 --- a/board/sandburst/common/sb_common.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include "sb_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -long int fixed_sdram (void); - -/************************************************************************* - * metrobox_get_master - * - * PRI_N - active low signal. If the GPIO pin is low we are the master - * - ************************************************************************/ -int sbcommon_get_master(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { - return 0; - } - else { - return 1; - } -} - -/************************************************************************* - * metrobox_secondary_present - * - * Figure out if secondary/slave board is present - * - ************************************************************************/ -int sbcommon_secondary_present(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) - return 0; - else - return 1; -} - -/************************************************************************* - * sbcommon_get_serial_number - * - * Retrieve the board serial number via the mac address in eeprom - * - ************************************************************************/ -unsigned short sbcommon_get_serial_number(void) -{ - unsigned char buff[0x100]; - unsigned short sernum; - - /* Get the board serial number from eeprom */ - /* Initialize I2C */ - i2c_set_bus_num(0); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - memcpy(&sernum, &buff[0xF4], 2); - sernum /= 32; - - return (sernum); -} - -/************************************************************************* - * sbcommon_fans - * - * Spin up fans 2 & 3 to get some air moving. OS will take care - * of the rest. This is mostly a precaution... - * - * Assumes i2c bus 1 is ready. - * - ************************************************************************/ -void sbcommon_fans(void) -{ - /* - * Attempt to turn on 2 of the fans... - * Need to go through the bridge - */ - i2c_set_bus_num(1); - puts ("FANS: "); - - /* select fan4 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x08); /* val = bus 4 */ - - /* Turn on FAN 4 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 4 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan3 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x04); /* val = bus 3 */ - - /* Turn on FAN 3 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 3 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan2 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x02); /* val = bus 4 */ - - /* Turn on FAN 2 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 2 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan1 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x01); /* val = bus 0 */ - - /* Turn on FAN 1 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 1 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - puts ("on\n"); - i2c_set_bus_num(0); - - return; - -} - -/************************************************************************* - * initdram - * - * Initialize sdram - * - ************************************************************************/ -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -/************************************************************************* - * testdram - * - * - ************************************************************************/ -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing SDRAM: "); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("OK\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * board_get_enetaddr - * - * Get the ethernet MAC address for the management ethernet from the - * strap EEPROM. Note that is the BASE address for the range of - * external ethernet MACs on the board. The base + 31 is the actual - * mgmt mac address. - * - ************************************************************************/ - -void board_get_enetaddr(int macaddr_idx, uchar *enet) -{ - int i; - unsigned short tmp; - unsigned char buff[0x100], *cp; - - if (0 == macaddr_idx) { - - /* Initialize I2C */ - i2c_set_bus_num(0); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - cp = &buff[0xF0]; - - for (i = 0; i < 6; i++,cp++) - enet[i] = *cp; - - memcpy(&tmp, &enet[4], 2); - tmp += 31; - memcpy(&enet[4], &tmp, 2); - - } else { - enet[0] = 0x02; - enet[1] = 0x00; - enet[2] = 0x00; - enet[3] = 0x00; - enet[4] = 0x00; - if (1 == sbcommon_get_master() ) { - /* Master/Primary card */ - enet[5] = 0x01; - } else { - /* Slave/Secondary card */ - enet [5] = 0x02; - } - } - - return; -} - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - - return (ctrlc()); -} -#endif diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h deleted file mode 100644 index 8716eacd84..0000000000 --- a/board/sandburst/common/sb_common.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __SBCOMMON_H__ -#define __SBCOMMON_H__ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include - -/* - * GPIO Settings - */ -/* Chassis settings */ -#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */ -#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */ - -/* Debug LEDs */ -#define SBCOMMON_GPIO_DBGLED_0 0x00000400 -#define SBCOMMON_GPIO_DBGLED_1 0x00000200 -#define SBCOMMON_GPIO_DBGLED_2 0x00100000 -#define SBCOMMON_GPIO_DBGLED_3 0x00000100 - -#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3) - -#define SBCOMMON_GPIO_SYS_FAULT 0x00000080 -#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040 -#define SBCOMMON_GPIO_SYS_STATUS 0x00000020 - -#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS) - -#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3 | \ - SBCOMMON_GPIO_SYS_STATUS) - -typedef struct ppc440_gpio_regs { - volatile unsigned long out; - volatile unsigned long tri_state; - volatile unsigned long dummy[4]; - volatile unsigned long open_drain; - volatile unsigned long in; -} __attribute__((packed)) ppc440_gpio_regs_t; - -int sbcommon_get_master(void); -int sbcommon_secondary_present(void); -unsigned short sbcommon_get_serial_number(void); -void sbcommon_fans(void); -void board_get_enetaddr(int macaddr_idx, uchar *enet); - -#endif /* __SBCOMMON_H__ */ diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile deleted file mode 100644 index af758f947e..0000000000 --- a/board/sandburst/karef/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Sandburst Corporation -# Travis B. Sawyer -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -# TBS: add for debugging purposes -BUILDUSER := $(shell whoami) -FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) - -CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' -# TBS: end debugging - - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o ../common/flash.o ../common/sb_common.o - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk deleted file mode 100644 index b73986d3f2..0000000000 --- a/board/sandburst/karef/config.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2005 -# Sandburst Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# Sandburst Corporation Metrobox Reference Design -# Travis B. Sawyer -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h deleted file mode 100644 index cc501c99d9..0000000000 --- a/board/sandburst/karef/hal_ka_of_auto.h +++ /dev/null @@ -1,324 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_of - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_OF_AUTO_H -#define HAL_KA_OF_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'ofem' - */ - -/* ---- Block instance addressing (for block-select) */ -#define OFEM_BLOCK_ADDR_BIT_L 6 -#define OFEM_BLOCK_ADDR_BIT_H 9 -#define OFEM_BLOCK_ADDR_WIDTH 4 - -#define OFEM_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define OFEM_REG_ADDR_BIT_L 2 -#define OFEM_REG_ADDR_BIT_H 5 -#define OFEM_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31 -#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31 -#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018 -#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008 -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_OF_AUTO_H */ diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h deleted file mode 100644 index db1cec246a..0000000000 --- a/board/sandburst/karef/hal_ka_sc_auto.h +++ /dev/null @@ -1,836 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_sc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_SC_AUTO_H -#define HAL_KA_SC_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'scan' - */ - -/* ---- Block instance addressing (for block-select) */ -#define SCAN_BLOCK_ADDR_BIT_L 7 -#define SCAN_BLOCK_ADDR_BIT_H 9 -#define SCAN_BLOCK_ADDR_WIDTH 3 - -#define SCAN_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define SCAN_REG_ADDR_BIT_L 2 -#define SCAN_REG_ADDR_BIT_H 6 -#define SCAN_REG_ADDR_WIDTH 5 - - -/* ================================================================ - * ---- Register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 -#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 -#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 -#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c -#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 -#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 -#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 -#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 -#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_SC_AUTO_H */ diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S deleted file mode 100644 index 61c5d07964..0000000000 --- a/board/sandburst/karef/init.S +++ /dev/null @@ -1,39 +0,0 @@ -/* -* Copyright (C) 2005 Sandburst Corporation - * SPDX-License-Identifier: GPL-2.0+ -*/ -/* - * Ported from Ebony init.S by Travis B. Sawyer - */ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c deleted file mode 100644 index 683d68b933..0000000000 --- a/board/sandburst/karef/karef.c +++ /dev/null @@ -1,595 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "karef.h" -#include "karef_version.h" -#include -#include -#include -#include -#include -#include "../common/sb_common.h" -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) -#include -#endif - -void fpga_init (void); - -KAREF_BOARD_ID_ST board_id_as[] = -{ - {"Undefined"}, /* Not specified */ - {"Kamino Reference Design"}, - {"Reserved"}, /* Reserved for future use */ - {"Reserved"}, /* Reserved for future use */ -}; - -KAREF_BOARD_ID_ST ofem_board_id_as[] = -{ - {"Undefined"}, - {"1x10 + 10x2"}, - {"Reserved"}, - {"Reserved"}, -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(SDR0_PFC0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB0AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB1AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB2AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | KaRef Scan FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB5AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB4AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | OFEM FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB3AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB6AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB7AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000000); /* all non- critical */ - mtdcr (UIC1PR, 0xfffffe03); /* polarity */ - mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ - mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffff83ff); /* polarity */ - mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); - mtdcr (UIC0TR, 0x00000000); - mtdcr (UIC0VR, 0x00000001); - - fpga_init(); - - return 0; -} - - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0; - unsigned char ofem_brd_rev, ofem_brd_id; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - - scan_id = (unsigned char)((karef_ps->revision_ul & - SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT); - - scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT); - - brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT); - - ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - - ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT); - - if (0xF != ofem_brd_id) { - ofem_id = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT); - - ofem_rev = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT); - } - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - - printf ("Board: Sandburst Corporation Kamino Reference Design " - "Serial Number: %d\n", sernum); - printf ("%s\n", KAREF_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev); - printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id); - if(0xF != ofem_brd_id) { - printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev); - printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev); - } - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on fans 3 & 4 */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - uchar enetaddr[6]; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", KAREF_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", - U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; - karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - } - -#ifdef CONFIG_HAS_ETH0 - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(0, enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - board_get_enetaddr(1, enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH2 - if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { - board_get_enetaddr(2, enetaddr); - eth_setenv_enetaddr("eth2addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH3 - if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { - board_get_enetaddr(3, enetaddr); - eth_setenv_enetaddr("eth3addr", enetaddr); - } -#endif - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - KAREF_FPGA_REGS_ST *karef_ps; - /* TODO: ide reset */ - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - - if (on) { - karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } else { - karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - unsigned char ofem_id; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - tmp = - SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK; - - karef_ps->reset_ul = tmp; - - /* - * Wait a bit to allow the ofem fpga to get its brains - */ - udelay(5000); - - /* - * Check to see if the ofem is there - */ - ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - if(0xF != ofem_id) { - tmp = - SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; - - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - ofem_ps->reset_ul = tmp; - - ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; - } - - karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT; - - asm("eieio"); - - return; -} - -int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.70.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d " - "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:" - "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000"); - - saveenv(); - - return(1); -} - -int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, - "Set environment to factory defaults", ""); - -U_BOOT_CMD(karecover, 1, 1, karefRecover, - "Set environment to allow for fs recovery", ""); diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h deleted file mode 100644 index eb9c314aa9..0000000000 --- a/board/sandburst/karef/karef.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __KAREF_H__ -#define __KAREF_H__ -/* - * (C) Copyright 2005 - * Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Ka Reference Design OFEM FPGA Registers & definitions */ -#include "hal_ka_sc_auto.h" -#include "hal_ka_of_auto.h" - -typedef struct karef_board_id_s { - const char name[40]; -} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST; - -/* SCAN FPGA */ -typedef struct karef_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ - volatile unsigned long scan_from0_ul; /* Read Only */ - volatile unsigned long scan_from1_ul; /* Read Only */ - volatile unsigned long scan_to0_ul; /* Read/Write */ - volatile unsigned long scan_to1_ul; /* Read/Write */ - volatile unsigned long scan_control_ul; /* Read/Write */ - volatile unsigned long pll_control_ul; /* Read/Write */ - volatile unsigned long core_clock_cnt_ul; /* Read/Write */ - volatile unsigned long dr_clock_cnt_ul; /* Read/Write */ - volatile unsigned long spi_clock_cnt_ul; /* Read/Write */ - volatile unsigned long brdout_data_ul; /* Read/Write */ - volatile unsigned long brdout_enable_ul; /* Read/Write */ - volatile unsigned long brdin_data_ul; /* Read Only */ - volatile unsigned long misc_ul; /* Read/Write */ -} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST; - -/* OFEM FPGA */ -typedef struct ofem_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */ -} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST; - - -#endif /* __KAREF_H__ */ diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h deleted file mode 100644 index 5226e7a4ec..0000000000 --- a/board/sandburst/karef/karef_version.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _KAREF_VERSION_H_ -#define _KAREF_VERSION_H_ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#define KAREF_U_BOOT_REL_STR "Release 0.0.7" -#endif diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug deleted file mode 100644 index c17c8b939b..0000000000 --- a/board/sandburst/karef/u-boot.lds.debug +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/sandburst/karef/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile deleted file mode 100644 index 163f2b98da..0000000000 --- a/board/sandburst/metrobox/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -# TBS: add for debugging purposes -BUILDUSER := $(shell whoami) -FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) - -CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' -# TBS: end debugging - - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o ../common/flash.o ../common/sb_common.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk deleted file mode 100644 index 23190c8673..0000000000 --- a/board/sandburst/metrobox/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h deleted file mode 100644 index c99b38ca06..0000000000 --- a/board/sandburst/metrobox/hal_xc_auto.h +++ /dev/null @@ -1,553 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip xc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_XC_AUTO_H -#define HAL_XC_AUTO_H - -/* ---------------------------------------------------------------- - * For block: 'xcvr_cntl' - */ - -/* ---- Block instance addressing (for block-select) */ -#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6 -#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9 -#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4 - -#define XCVR_CNTL_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define XCVR_CNTL_REG_ADDR_BIT_L 2 -#define XCVR_CNTL_REG_ADDR_BIT_H 5 -#define XCVR_CNTL_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004 -#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024 -#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_XC_AUTO_H */ diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S deleted file mode 100644 index 13e340eece..0000000000 --- a/board/sandburst/metrobox/init.S +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (C) 2005 -* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c deleted file mode 100644 index 5bc7f2f433..0000000000 --- a/board/sandburst/metrobox/metrobox.c +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Copyright (c) 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include "metrobox.h" -#include "metrobox_version.h" -#include -#include -#include -#include -#include -#include "../common/sb_common.h" -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) -#include -#endif - -void fpga_init (void); - -METROBOX_BOARD_ID_ST board_id_as[] = -{ {"Undefined"}, /* Not specified */ - {"2x10Gb"}, /* 2 ports, 10 GbE */ - {"20x1Gb"}, /* 20 ports, 1 GbE */ - {"Reserved"}, /* Reserved for future use */ -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(SDR0_PFC0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB0AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB1AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB2AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | OPTO & OFEM FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB3AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A for metrobox - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB4AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Metrobox MAC B Initialize bank 5 with default values. - | KA REF FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB5AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB6AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB7AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000000); /* all non- critical */ - mtdcr (UIC1PR, 0xfffffe03); /* polarity */ - mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ - mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffff83ff); /* polarity */ - mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); - mtdcr (UIC0TR, 0x00000000); - mtdcr (UIC0VR, 0x00000001); - - fpga_init(); - - return 0; -} - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char opto_rev, opto_id; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - opto_id = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT); - - brd_rev = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT); - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); - printf ("%s\n", METROBOX_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); - printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name); - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on fans */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - uchar enetaddr[6]; - unsigned char opto_rev; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", METROBOX_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", - U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - if(0x12 <= opto_rev) { - opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK; - } - } - -#ifdef CONFIG_HAS_ETH0 - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(0, enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - board_get_enetaddr(1, enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH2 - if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { - board_get_enetaddr(2, enetaddr); - eth_setenv_enetaddr("eth2addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH3 - if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { - board_get_enetaddr(3, enetaddr); - eth_setenv_enetaddr("eth3addr", enetaddr); - } -#endif - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - if (on) { /* assert RESET */ - opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } else { /* release RESET */ - opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - OPTO_FPGA_REGS_ST *opto_ps; - unsigned char opto_rev; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - /* - * Take appropriate hw bits out of reset - */ - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - tmp = - SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK; - opto_ps->reset_ul = tmp; - /* - * Turn on the 'Slow Blink' for the System Error Led. - * Ensure FPGA rev is up to at least rev 0x12 - */ - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - if(0x12 <= opto_rev) { - opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT; - } - - asm("eieio"); - - return; -} - -int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.60.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d " - "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1" - ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000"); - - saveenv(); - - - return(1); -} - -int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none", - sernum, sernum); - - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, - "Set environment to factory defaults", ""); - -U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, - "Set environment to allow for fs recovery", ""); diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h deleted file mode 100644 index d64f496c9a..0000000000 --- a/board/sandburst/metrobox/metrobox.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __METROBOX_H__ -#define __METROBOX_H__ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -typedef struct metrobox_board_id_s { - const char name[40]; -} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST; - - -/* Metrobox Opto-FPGA registers and definitions */ -#include "hal_xc_auto.h" -typedef struct opto_fpga_regs_s { - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ -} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST; - -#endif /* __METROBOX_H__ */ diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h deleted file mode 100644 index 8264f56d6e..0000000000 --- a/board/sandburst/metrobox/metrobox_version.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _METROBOX_VERSION_H_ -#define _METROBOX_VERSION_H_ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#define METROBOX_U_BOOT_REL_STR "Release 2.0.3" - -#endif diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug deleted file mode 100644 index 7ff09c0671..0000000000 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/sandburst/metrobox/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sandisk/sansa_fuze_plus/Kconfig b/board/sandisk/sansa_fuze_plus/Kconfig new file mode 100644 index 0000000000..ab4a29255c --- /dev/null +++ b/board/sandisk/sansa_fuze_plus/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SANSA_FUZE_PLUS + +config SYS_BOARD + default "sansa_fuze_plus" + +config SYS_VENDOR + default "sandisk" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "sansa_fuze_plus" + +endif diff --git a/board/sandisk/sansa_fuze_plus/MAINTAINERS b/board/sandisk/sansa_fuze_plus/MAINTAINERS new file mode 100644 index 0000000000..ccfd399708 --- /dev/null +++ b/board/sandisk/sansa_fuze_plus/MAINTAINERS @@ -0,0 +1,6 @@ +SANSA_FUZE_PLUS BOARD +M: Marek Vasut +S: Maintained +F: board/sandisk/sansa_fuze_plus/ +F: include/configs/sansa_fuze_plus.h +F: configs/sansa_fuze_plus_defconfig diff --git a/board/sandisk/sansa_fuze_plus/Makefile b/board/sandisk/sansa_fuze_plus/Makefile new file mode 100644 index 0000000000..667600d020 --- /dev/null +++ b/board/sandisk/sansa_fuze_plus/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y := sfp.o +else +obj-y := spl_boot.o +endif diff --git a/board/sandisk/sansa_fuze_plus/sfp.c b/board/sandisk/sansa_fuze_plus/sfp.c new file mode 100644 index 0000000000..a3865ad56a --- /dev/null +++ b/board/sandisk/sansa_fuze_plus/sfp.c @@ -0,0 +1,388 @@ +/* + * SanDisk Sansa Fuze Plus board + * + * Copyright (C) 2013 Marek Vasut + * + * Hardware investigation done by: + * + * Amaury Pouly + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#ifdef CONFIG_CMD_MMC +static int xfi3_mmc_cd(int id) +{ + switch (id) { + case 0: + /* The SSP_DETECT is inverted on this board. */ + return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1); + case 1: + /* Internal eMMC always present */ + return 1; + default: + return 0; + } +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* MicroSD slot */ + gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1); + gpio_direction_output(MX23_PAD_GPMI_D08__GPIO_0_8, 0); + ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd); + if (ret) + return ret; + + /* Internal eMMC */ + gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0); + ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd); + + return ret; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +const iomux_cfg_t iomux_lcd_gpio[] = { + MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__GPIO_1_6 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__GPIO_1_7 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__GPIO_1_8 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__GPIO_1_9 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__GPIO_1_10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__GPIO_1_11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__GPIO_1_12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__GPIO_1_13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__GPIO_1_14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__GPIO_1_15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RS__GPIO_1_19 | MUX_CONFIG_LCD, + MX23_PAD_LCD_WR__GPIO_1_20 | MUX_CONFIG_LCD, + MX23_PAD_LCD_CS__GPIO_1_21 | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__GPIO_1_23 | MUX_CONFIG_LCD, +}; + +const iomux_cfg_t iomux_lcd_lcd[] = { + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, + MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, + MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, +}; + +static int mxsfb_read_register(uint32_t reg, uint32_t *value) +{ + iomux_cfg_t mux; + uint32_t val = 0; + int i; + + /* Mangle the register offset. */ + reg = ((reg & 0xff) << 1) | (((reg >> 8) & 0xff) << 10); + + /* + * The SmartLCD interface on MX233 can only do WRITE operation + * via the LCDIF controller. Implement the READ operation by + * fiddling with bits. + */ + mxs_iomux_setup_multiple_pads(iomux_lcd_gpio, + ARRAY_SIZE(iomux_lcd_gpio)); + + gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1); + gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1); + gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1); + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); + + for (i = 0; i < 18; i++) { + mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); + gpio_direction_output(mux, 0); + } + + udelay(2); + gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 0); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 0); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 0); + udelay(1); + + for (i = 0; i < 18; i++) { + mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); + gpio_direction_output(mux, (reg >> i) & 1); + } + udelay(1); + + gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1); + udelay(3); + + for (i = 0; i < 18; i++) { + mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); + gpio_direction_input(mux); + } + udelay(2); + + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); + udelay(3); + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0); + udelay(2); + + for (i = 0; i < 18; i++) { + mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); + val |= !!gpio_get_value(mux) << i; + } + udelay(1); + + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1); + udelay(1); + + mxs_iomux_setup_multiple_pads(iomux_lcd_lcd, + ARRAY_SIZE(iomux_lcd_lcd)); + + /* Demangle the register value. */ + *value = ((val >> 1) & 0xff) | ((val >> 2) & 0xff00); + + writel(val, 0x2000); + return 0; +} + +static int mxsfb_write_byte(uint32_t payload, const unsigned int data) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + const unsigned int timeout = 0x10000; + + /* What is going on here I do not know. FIXME */ + payload = ((payload & 0xff) << 1) | (((payload >> 8) & 0xff) << 10); + + if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, + timeout)) + return -ETIMEDOUT; + + writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | + (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET), + ®s->hw_lcdif_transfer_count); + + writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN, + ®s->hw_lcdif_ctrl_clr); + + if (data) + writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set); + + writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); + + if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, + timeout)) + return -ETIMEDOUT; + + writel(payload, ®s->hw_lcdif_data); + return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, + timeout); +} + +static void mxsfb_write_register(uint32_t reg, uint32_t data) +{ + mxsfb_write_byte(reg, 0); + mxsfb_write_byte(data, 1); +} + +static const struct { + uint8_t reg; + uint8_t delay; + uint16_t val; +} lcd_regs[] = { + { 0xe5, 0 , 0x78f0 }, + { 0xe3, 0 , 0x3008 }, + { 0xe7, 0 , 0x0012 }, + { 0xef, 0 , 0x1231 }, + { 0x00, 0 , 0x0001 }, + { 0x01, 0 , 0x0100 }, + { 0x02, 0 , 0x0700 }, + { 0x03, 0 , 0x1030 }, + { 0x04, 0 , 0x0000 }, + { 0x08, 0 , 0x0207 }, + { 0x09, 0 , 0x0000 }, + { 0x0a, 0 , 0x0000 }, + { 0x0c, 0 , 0x0000 }, + { 0x0d, 0 , 0x0000 }, + { 0x0f, 0 , 0x0000 }, + { 0x10, 0 , 0x0000 }, + { 0x11, 0 , 0x0007 }, + { 0x12, 0 , 0x0000 }, + { 0x13, 20 , 0x0000 }, + /* Wait 20 mS here. */ + { 0x10, 0 , 0x1290 }, + { 0x11, 50 , 0x0007 }, + /* Wait 50 mS here. */ + { 0x12, 50 , 0x0019 }, + /* Wait 50 mS here. */ + { 0x13, 0 , 0x1700 }, + { 0x29, 50 , 0x0014 }, + /* Wait 50 mS here. */ + { 0x20, 0 , 0x0000 }, + { 0x21, 0 , 0x0000 }, + { 0x30, 0 , 0x0504 }, + { 0x31, 0 , 0x0007 }, + { 0x32, 0 , 0x0006 }, + { 0x35, 0 , 0x0106 }, + { 0x36, 0 , 0x0202 }, + { 0x37, 0 , 0x0504 }, + { 0x38, 0 , 0x0500 }, + { 0x39, 0 , 0x0706 }, + { 0x3c, 0 , 0x0204 }, + { 0x3d, 0 , 0x0202 }, + { 0x50, 0 , 0x0000 }, + { 0x51, 0 , 0x00ef }, + { 0x52, 0 , 0x0000 }, + { 0x53, 0 , 0x013f }, + { 0x60, 0 , 0xa700 }, + { 0x61, 0 , 0x0001 }, + { 0x6a, 0 , 0x0000 }, + { 0x2b, 50 , 0x000d }, + /* Wait 50 mS here. */ + { 0x90, 0 , 0x0011 }, + { 0x92, 0 , 0x0600 }, + { 0x93, 0 , 0x0003 }, + { 0x95, 0 , 0x0110 }, + { 0x97, 0 , 0x0000 }, + { 0x98, 0 , 0x0000 }, + { 0x07, 0 , 0x0173 }, +}; + +void board_mxsfb_system_setup(void) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + uint32_t id; + int i; + + /* Switch the LCDIF into System-Mode */ + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE | + LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr); + + /* To program the LCD, switch to 18bit bus + 18bit data. */ + clrsetbits_le32(®s->hw_lcdif_ctrl, + LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK, + LCDIF_CTRL_WORD_LENGTH_18BIT | + LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT); + + mxsfb_read_register(0, &id); + writel(id, 0x2004); + + /* Restart the SmartLCD controller */ + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_set); + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_clr); + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_set); + mdelay(50); + + /* Program the SmartLCD controller */ + writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set); + + writel((0x02 << LCDIF_TIMING_CMD_HOLD_OFFSET) | + (0x02 << LCDIF_TIMING_CMD_SETUP_OFFSET) | + (0x02 << LCDIF_TIMING_DATA_HOLD_OFFSET) | + (0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET), + ®s->hw_lcdif_timing); + + /* + * ILI9325 init and configuration sequence. + */ + for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) { + mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val); + if (lcd_regs[i].delay) + mdelay(lcd_regs[i].delay); + } + /* Turn on Framebuffer Upload Mode */ + mxsfb_write_byte(0x22, 0); + + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT, + ®s->hw_lcdif_ctrl_set); + + /* Operate the framebuffer in 16bit mode. */ + clrsetbits_le32(®s->hw_lcdif_ctrl, + LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK, + LCDIF_CTRL_WORD_LENGTH_16BIT | + LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT); +} +#endif + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* Turn on PWM backlight */ + gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + usb_eth_initialize(bis); + return 0; +} diff --git a/board/sandisk/sansa_fuze_plus/spl_boot.c b/board/sandisk/sansa_fuze_plus/spl_boot.c new file mode 100644 index 0000000000..825be829c7 --- /dev/null +++ b/board/sandisk/sansa_fuze_plus/spl_boot.c @@ -0,0 +1,140 @@ +/* + * SanDisk Sansa Fuze Plus setup + * + * Copyright (C) 2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* EMI */ + MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, + + MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + + MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, + MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, + MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + + MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D08__GPIO_0_8 | MUX_CONFIG_SSP, + + MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D04__SSP2_DATA4 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D05__SSP2_DATA5 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D06__SSP2_DATA6 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D07__SSP2_DATA7 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP, + MX23_PAD_GPMI_WRN__SSP2_SCK | + (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL), + MX23_PAD_PWM3__GPIO_1_29 | MUX_CONFIG_SSP, + + /* PWM -- FIXME */ + MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP, +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* mDDR configuration values */ + const uint32_t regs[] = { + 0x01010001, 0x00010000, 0x01000000, 0x00000001, + 0x00010101, 0x00000001, 0x00010000, 0x01000001, + 0x01010000, 0x00000001, 0x07000200, 0x04070203, + 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, + 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, + 0x03061323, 0x0000000a, 0x00080008, 0x00200020, + 0x00200020, 0x00200020, 0x000003f7, 0x00000000, + 0x00000000, 0x00000000, 0x00000020, 0x00000000, + 0x001023cd, 0x20410010, 0x00006665, 0x00000000, + 0x00000101, 0x00000001, 0x00000000, 0x00000000, + }; + memcpy(dram_vals, regs, sizeof(regs)); +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/sandpoint/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sandpoint/README b/board/sandpoint/README deleted file mode 100644 index a2e0831f33..0000000000 --- a/board/sandpoint/README +++ /dev/null @@ -1,413 +0,0 @@ -This port of U-Boot will run on a Motorola Sandpoint 3 development -system equipped with a Unity X4 PPMC card (MPC8240 CPU) only. It is a -snapshot of work in progress and far from being completed. In order -to run it on the target system, it has to be downloaded using the -DINK32 monitor program that came with your Sandpoint system. Please -note that DINK32 does not accept the S-Record file created by the -U-Boot build process unmodified, because it contains CR/LF line -terminators. You have to strip the CR characters first. There is a -tiny script named 'dinkdl' I created for this purpose. - -The Sandpoint port is based on the work of Rob Taylor, who does not -seem to maintain it any more. I can be reached by mail as -tkoeller@gmx.net. - -Thomas Koeller - - - - -The port was tested on a Sandpoint 8240 X3 board, with U-Boot -installed in the flash memory of the CPU card. Please use the -following DIP switch settings: - -Motherboard: - -SW1.1: on SW1.2: on SW1.3: on SW1.4: on -SW1.5: on SW1.6: on SW1.7: on SW1.8: on - -SW2.1: on SW2.2: on SW2.3: on SW2.4: on -SW2.5: on SW2.6: on SW2.7: on SW2.8: on - - -CPU Card: - -SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on -SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF - -SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF -SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on - - -The followind detailed description of installation and initial steps -with U-Boot and QNX was provided by Jim Sandoz : - - -Directions for installing U-Boot on Sandpoint+Unity8240 -using the Abatron BDI2000 BDM/JTAG debugger ... - -Background and Reference info: -http://u-boot.sourceforge.net/ -http://www.abatron.ch/ -http://www.abatron.ch/BDI/bdihw.html -http://www.abatron.ch/DataSheets/BDI2000.pdf -http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf -http://e-www.motorola.com/collateral/SPX3UM.pdf -http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf - - -Connection Diagram: - =========== - === ===== |----- | -| | <---------------> | | | | | -|PC | rs232 | BDI |=============[] | | -| | |2000 | BDM probe | | | -| | <---------------> | | |----- | - === ethernet ===== | | - | | - =========== - Sandpoint X3 with - Unity 8240 proc - - -PART 1) - DIP Switch Settings: - -Sandpoint X3 8240 processor board DIP switch settings, with -U-Boot to be installed in the flash memory of the CPU card: - -Motorola Sandpoint X3 Motherboard: -SW1.1: on SW1.2: on SW1.3: on SW1.4: on -SW1.5: on SW1.6: on SW1.7: on SW1.8: on -SW2.1: on SW2.2: on SW2.3: on SW2.4: on -SW2.5: on SW2.6: on SW2.7: on SW2.8: on - -Motorola Unity 8240 CPU Card: -SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on -SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF -SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF -SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on - - -PART 2) - Connect the BDI2000 Cable to the Sandpoint/Unity 8240: - -BDM Pin 1 on the Unity 8240 processor board is towards the -PCI PMC connectors, or away from the socketed SDRAM, i.e.: - - ==================== - | ---------------- | - | | SDRAM | | - | | | | - | ---------------- | - | |~| | - | |B| ++++++ | - | |D| + uP + | - | |M| +8240+ | - | ~ 1 ++++++ | - | | - | | - | | - | PMC conn ====== | - | ===== ====== | - | | - ==================== - - -PART 3) - Setting up the BDI2000, and preparing for TCP/IP network comms: - -Connect the BDI2000 to the PC using the supplied serial cable. -Download the BDI2000 software and install it using setup.exe. - -[Note: of course you can also use the Linux command line tool -"bdisetup" to configure your BDI2000 - the sources are included on -the floppy disk that comes with your BDI2000. Just in case you don't -have any Windows PC's - like me :-) -- wd ] - -Power up the BDI2000; then follow directions to assign the IP -address and related network information. Note that U-Boot -will be loaded to the Sandpoint via tftp. You need to either -use the Abatron-provided tftp application or provide a tftp -server (e.g. Linux/Solaris/*BSD) somewhere on your network. -Once the IP address etc are assigned via the RS232 port, -further communication with the BDI2000 will happen via the -ethernet connection. - -PART 4) - Making a TCP/IP network connection to the Abatron BDI2000: - -Telnet to the Abatron BDI2000. Assuming that all of the -networking info was loaded via RS232 correctly, you will see -the following (scrolling): - -- TARGET: waiting for target Vcc -- TARGET: waiting for target Vcc - - -PART 5) - Power up the target Sandpoint: -If the BDM connections are correct, the following will now appear: - -- TARGET: waiting for target Vcc -- TARGET: waiting for target Vcc -- TARGET: processing power-up delay -- TARGET: processing user reset request -- BDI asserts HRESET -- Reset JTAG controller passed -- Bypass check: 0x55 => 0xAA -- Bypass check: 0x55 => 0xAA -- JTAG exists check passed -- Target PVR is 0x00810101 -- COP status is 0x01 -- Check running state passed -- BDI scans COP freeze command -- BDI removes HRESET -- COP status is 0x05 -- Check stopped state passed -- Check LSRL length passed -- BDI sets breakpoint at 0xFFF00100 -- BDI resumes program execution -- Waiting for target stop passed -- TARGET: Target PVR is 0x00810101 -- TARGET: reseting target passed -- TARGET: processing target startup .... -- TARGET: processing target startup passed -BDI> - - -PART 6) - Erase the current contents of the flash memory: - -BDI>era 0xFFF00000 - Erasing flash at 0xfff00000 - Erasing flash passed -BDI>era 0xFFF04000 - Erasing flash at 0xfff04000 - Erasing flash passed -BDI>era 0xFFF06000 - Erasing flash at 0xfff06000 - Erasing flash passed -BDI>era 0xFFF08000 - Erasing flash at 0xfff08000 - Erasing flash passed -BDI>era 0xFFF10000 - Erasing flash at 0xfff10000 - Erasing flash passed -BDI>era 0xFFF20000 - Erasing flash at 0xfff20000 - Erasing flash passed - - -PART 7) - Program the flash memory with the U-Boot image: - -BDI>prog 0xFFF00000 u-boot.bin bin - Programming u-boot.bin , please wait .... - Programming flash passed - - -PART 8) - Connect PC to Sandpoint: -Using a crossover serial cable, attach the PC serial port to the -Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud. - - -PART 9) - Reset the Unity and begin U-Boot execution: - -BDI>reset -- TARGET: processing user reset request -- TARGET: Target PVR is 0x00810101 -- TARGET: reseting target passed -- TARGET: processing target init list .... -- TARGET: processing target init list passed - -BDI>go - -Now see output from U-Boot running, sent via serial port: - -U-Boot 1.1.4 (Jan 23 2002 - 18:29:19) - -CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: Sandpoint 8240 Unity -DRAM: 64 MB -FLASH: 2 MB -PCI: scanning bus0 ... - bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE - 00 00 00 1057 0003 060000 13 00000008 00000000 01 00 - 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00 - 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00 -In: serial -Out: serial -Err: serial -=> - - -PART 10) - Set and save any required environmental variables, examples of some: - -=> setenv ethaddr 00:03:47:97:D0:79 -=> setenv bootfile your_qnx_image_here -=> setenv hostname sandpointX -=> setenv netmask 255.255.255.0 -=> setenv ipaddr 192.168.0.11 -=> setenv serverip 192.168.0.10 -=> setenv gatewayip=192.168.0.1 -=> saveenv -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> - -**** Example environment: **** - -=> printenv -baudrate=9600 -bootfile=telemetry -hostname=sp1 -ethaddr=00:03:47:97:E4:6B -load=tftp 100000 u-boot.bin -update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv -filesize=1f304 -gatewayip=145.17.228.1 -netmask=255.255.255.0 -ipaddr=145.17.228.42 -serverip=145.17.242.46 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 332/8188 bytes -=> - -here's some text useful stuff for cut-n-paste: -setenv hostname sandpoint1 -setenv netmask 255.255.255.0 -setenv ipaddr 145.17.228.81 -setenv serverip 145.17.242.46 -setenv gatewayip 145.17.228.1 -saveenv - -PART 11) - Test U-Boot by tftp'ing new U-Boot, overwriting current: - -=> protect off all -Un-Protect Flash Bank # 1 -=> tftp 100000 u-boot.bin -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 127628 (1f28c hex) -=> era all -Erase Flash Bank # 1 - done -Erase Flash Bank # 2 - missing -=> cp.b 0x100000 FFF00000 1f28c -Copy to Flash... done -=> saveenv -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> reset - -You can put these commands into some environment variables; - -=> setenv load tftp 100000 u-boot.bin -=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv -=> saveenv - -Then you just have to type "run load" then "run update" - -=> run load -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 127748 (1f304 hex) -=> run update -Un-Protect Flash Bank # 1 -Un-Protect Flash Bank # 2 -Erase Flash from 0xfff00000 to 0xfff3ffff - done -Erased 7 sectors -Copy to Flash... done -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> - - -PART 12) - Load OS image (ELF format) via U-Boot using tftp - - -=> tftp 800000 sandpoint-simple.elf -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'sandpoint-simple.elf'. -Load address: 0x800000 -Loading: ################################################################# - ################################################################# - ################################################################# - ######################## -done -Bytes transferred = 1120284 (11181c hex) -==> - -PART 13) - Begin OS image execution: (note that unless you have the -serial parameters of your OS image set to 9600 (i.e. same as -the U-Boot binary) you will get garbage here until you change -the serial communications speed. - -=> bootelf 800000 -Loading @ 0x001f0100 (1120028 bytes) -## Starting application at 0x001f1d28 ... -Replace init_hwinfo() with a board specific version - -Loading QNX6.... - -Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1 -<...loader and kernel messages snipped...> - -Welcome to Neutrino on the Sandpoint -# - - -other information: - -CVS Retrieval Notes: - -U-Boot's SourceForge CVS repository can be checked out -through anonymous (pserver) CVS with the following -instruction set. The module you wish to check out must -be specified as the modulename. When prompted for a -password for anonymous, simply press the Enter key. - -cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login - -cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot diff --git a/board/sandpoint/dinkdl b/board/sandpoint/dinkdl deleted file mode 100644 index f281452eb3..0000000000 --- a/board/sandpoint/dinkdl +++ /dev/null @@ -1,2 +0,0 @@ -#! /bin/bash -tr -d "\r" <$1 >/dev/tts/1 diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S deleted file mode 100644 index 5a9b924ef9..0000000000 --- a/board/sandpoint/early_init.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Thomas Koeller, tkoeller@gmx.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ 1 -#endif - -#include -#include -#include -#include -#include - -#if defined(USE_DINK32) - /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) -#else - #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) -#endif - - .text - - /* Values to program into memory controller registers */ -tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT - .long MCCR3 - .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \ - (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT) - .long MCCR4 - .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \ - (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \ - (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) - .long MSAR1 - .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR1 - .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MSAR2 - .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR2 - .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR1 - .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR1 - .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR2 - .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR2 - .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long 0 - - - /* - * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This - * must be done in assembly, since we have no stack at this point. - */ - .global early_init_f -early_init_f: - mflr r10 - - /* basic memory controller configuration */ - lis r3, CONFIG_ADDR_HIGH - lis r4, CONFIG_DATA_HIGH - bl lab -lab: mflr r5 - lwzu r0, tbl - lab(r5) -loop: lwz r1, 4(r5) - stwbrx r0, 0, r3 - eieio - stwbrx r1, 0, r4 - eieio - lwzu r0, 8(r5) - cmpli cr0, 0, r0, 0 - bne cr0, loop - - /* set bank enable bits */ - lis r0, MBER@h - ori r0, 0, MBER@l - li r1, CONFIG_SYS_BANK_ENABLE - stwbrx r0, 0, r3 - eieio - stb r1, 0(r4) - eieio - - /* delay loop */ - lis r0, 0x0003 - mtctr r0 -delay: bdnz delay - - /* enable memory controller */ - lis r0, MCCR1@h - ori r0, 0, MCCR1@l - stwbrx r0, 0, r3 - eieio - lwbrx r0, 0, r4 - oris r0, 0, MCCR1_MEMGO@h - stwbrx r0, 0, r4 - eieio - - /* set up stack pointer */ - lis r1, CONFIG_SYS_INIT_SP_OFFSET@h - ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l - - mtlr r10 - blr diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c deleted file mode 100644 index 1ab668ce8a..0000000000 --- a/board/sandpoint/flash.c +++ /dev/null @@ -1,748 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); -#if 0 -static void flash_get_offsets (ulong base, flash_info_t *info); -#endif /* 0 */ - -/*flash command address offsets*/ - -#if 0 -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) -#else -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) -#endif - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -#if 0 -static int byte_parity_odd(unsigned char x) __attribute__ ((const)); -#endif /* 0 */ -static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const)); - -typedef struct -{ - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -#if 0 -static int -byte_parity_odd(unsigned char x) -{ - x ^= x >> 4; - x ^= x >> 2; - x ^= x >> 1; - return (x & 0x1) != 0; -} -#endif /* 0 */ - - -static unsigned long -flash_id(unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = - { - {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = - { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if(p->extval == chip) - { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if(p->extval == mfct) - { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - - -unsigned long -flash_init(void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) - { - flash_info_t * const pflinfo = &flash_info[i]; - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - /* Enable writes to Sandpoint flash */ - { - register unsigned char temp; - CONFIG_READ_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); - temp &= ~0x20; /* clear BIOSWP bit */ - CONFIG_WRITE_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); - } - - for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) - { - flash_info_t * const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address; -#if 0 - volatile FLASH_WORD_SIZE * addr2; -#endif -#if 0 - /* write autoselect sequence */ - flash[0x5555] = 0xaa; - flash[0x2aaa] = 0x55; - flash[0x5555] = 0x90; -#else - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; -#endif - __asm__ __volatile__("sync"); - -#if 0 - pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]); -#else - pflinfo->flash_id = flash_id(flash[0x0], flash[0x2 + 14 * i]); -#endif - - switch(pflinfo->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for(j = 0; j < 8; j++) - { - pflinfo->start[j] = base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for(j = 1; j < 16; j++) - { - pflinfo->start[j+3] = base_address + 0x00010000 * j; - } -#if 0 - /* check for protected sectors */ - for (j = 0; j < pflinfo->sector_count; j++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]); - if (pflinfo->flash_id & FLASH_MAN_SST) - pflinfo->protect[j] = 0; - else - pflinfo->protect[j] = addr2[2] & 1; - } -#endif - break; - } - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__("sync"); - } - - return flash_info[0].size + flash_info[1].size; -} - -#if 0 -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) - { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ -void -flash_print_info(flash_info_t *info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if(info->flash_id != FLASH_UNKNOWN) - { - switch(info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: mfct = "AMD"; break; - case FLASH_MAN_FUJ: mfct = "FUJITSU"; break; - case FLASH_MAN_STM: mfct = "STM"; break; - case FLASH_MAN_SST: mfct = "SST"; break; - case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break; - case FLASH_MAN_INTEL: mfct = "Intel"; break; - } - - switch(info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break; - case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break; - case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break; - case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break; - case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break; - case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break; - case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break; - case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break; - case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break; - case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break; - case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break; - } - } - - printf( - "\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, - type, - info->size >> 10, - info->sector_count - ); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) - { - unsigned long size; - unsigned int erased; - unsigned long * flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = - (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for( - flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++ - ) - erased = *flash == ~0x0UL; - - printf( - "%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", - info->protect[i] ? "RO" : " " - ); - } - - puts("\n"); - return; -} - -#if 0 - -/* - * The following code cannot be run from FLASH! - */ -ulong -flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - printf("flash_get_size: \n"); - /* Write auto select command: read Manufacturer ID */ - eieio(); - addr2[ADDR0] = (FLASH_WORD_SIZE)0xAA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x55; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x90; - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - printf("recognised manufacturer"); - - value = addr2[ADDR3]; /* device ID */ - debug ("\ndev_code=%x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf("flash id %lx; sector count %x, size %lx\n", info->flash_id,info->sector_count,info->size); - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) - { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if (info->flash_id & FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -#endif - - -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[sect] - info->start[0]) << sh8b)); - if (info->flash_id & FLASH_MAN_SST) - { - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ - } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[l_sect] - info->start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c deleted file mode 100644 index 16237bd524..0000000000 --- a/board/sandpoint/sandpoint.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Sandpoint " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " Unity ##Test not implemented yet##\n"); - return 0; -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/sandpoint/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds deleted file mode 100644 index cd9f07c511..0000000000 --- a/board/sandpoint/u-boot.lds +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2001-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc824x/start.o (.text*) - *(.text.v*printf) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sbc405/Kconfig b/board/sbc405/Kconfig new file mode 100644 index 0000000000..4e7e843f46 --- /dev/null +++ b/board/sbc405/Kconfig @@ -0,0 +1,9 @@ +if TARGET_SBC405 + +config SYS_BOARD + default "sbc405" + +config SYS_CONFIG_NAME + default "sbc405" + +endif diff --git a/board/sbc405/MAINTAINERS b/board/sbc405/MAINTAINERS new file mode 100644 index 0000000000..2abad25997 --- /dev/null +++ b/board/sbc405/MAINTAINERS @@ -0,0 +1,6 @@ +SBC405 BOARD +#M: - +S: Maintained +F: board/sbc405/ +F: include/configs/sbc405.h +F: configs/sbc405_defconfig diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile index 0d202ac071..3f2b0e24ca 100644 --- a/board/sbc405/Makefile +++ b/board/sbc405/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o strataflash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = sbc405.o strataflash.o diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c index c6d8e99c09..7ddc97c5ea 100644 --- a/board/sbc405/strataflash.c +++ b/board/sbc405/strataflash.c @@ -2,7 +2,7 @@ * (C) Copyright 2002 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/sbc8349/Kconfig b/board/sbc8349/Kconfig new file mode 100644 index 0000000000..129d6b92ec --- /dev/null +++ b/board/sbc8349/Kconfig @@ -0,0 +1,9 @@ +if TARGET_SBC8349 + +config SYS_BOARD + default "sbc8349" + +config SYS_CONFIG_NAME + default "sbc8349" + +endif diff --git a/board/sbc8349/MAINTAINERS b/board/sbc8349/MAINTAINERS new file mode 100644 index 0000000000..af95c1dd0d --- /dev/null +++ b/board/sbc8349/MAINTAINERS @@ -0,0 +1,8 @@ +SBC8349 BOARD +M: Paul Gortmaker +S: Maintained +F: board/sbc8349/ +F: include/configs/sbc8349.h +F: configs/sbc8349_defconfig +F: configs/sbc8349_PCI_33_defconfig +F: configs/sbc8349_PCI_66_defconfig diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile index 9a5b84a5a7..3b2c389484 100644 --- a/board/sbc8349/Makefile +++ b/board/sbc8349/Makefile @@ -4,26 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += sbc8349.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/sbc8349/README b/board/sbc8349/README index 2c35919f28..e2d60cc530 100644 --- a/board/sbc8349/README +++ b/board/sbc8349/README @@ -50,7 +50,7 @@ is a summary of that information: trying to preserve your old environment settings and user flash). - Set the start address of the erase/flash process to FF80_0000 - Set the target RAM required to 64kB. - - Select sectors for erasing (see note on enviroment below) + - Select sectors for erasing (see note on environment below) - Select Erase and Reprogram. Note that some versions of the register files used with Workbench diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 89da47ed12..72786d2ace 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -214,11 +214,13 @@ void sdram_init(void) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/sbc8548/Kconfig b/board/sbc8548/Kconfig new file mode 100644 index 0000000000..626cbdf2ab --- /dev/null +++ b/board/sbc8548/Kconfig @@ -0,0 +1,9 @@ +if TARGET_SBC8548 + +config SYS_BOARD + default "sbc8548" + +config SYS_CONFIG_NAME + default "sbc8548" + +endif diff --git a/board/sbc8548/MAINTAINERS b/board/sbc8548/MAINTAINERS new file mode 100644 index 0000000000..ba1f2475ea --- /dev/null +++ b/board/sbc8548/MAINTAINERS @@ -0,0 +1,10 @@ +SBC8548 BOARD +M: Paul Gortmaker +S: Maintained +F: board/sbc8548/ +F: include/configs/sbc8548.h +F: configs/sbc8548_defconfig +F: configs/sbc8548_PCI_33_defconfig +F: configs/sbc8548_PCI_33_PCIE_defconfig +F: configs/sbc8548_PCI_66_defconfig +F: configs/sbc8548_PCI_66_PCIE_defconfig diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index ecffaa9033..4c9b6cd60c 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -8,27 +8,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR2) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += sbc8548.o +obj-y += law.o +obj-y += tlb.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 9508561133..24cc776a25 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -9,8 +9,8 @@ #include #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -91,7 +91,8 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); out_be32(&ddr->cs0_bnds, 0x0000007f); out_be32(&ddr->cs1_bnds, 0x008000ff); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index dee8710316..25329e4473 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -7,7 +7,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include @@ -65,8 +65,8 @@ local_bus_init(void) get_sys_info(&sysinfo); - lbc_mhz = sysinfo.freqLocalBus / 1000000; - clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus; + lbc_mhz = sysinfo.freq_localbus / 1000000; + clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus; debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz); @@ -301,12 +301,14 @@ int last_stage_init(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_FSL_PCI_INIT FT_FSL_PCI_SETUP; #endif + + return 0; } #endif diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig new file mode 100644 index 0000000000..8dfc90cf8b --- /dev/null +++ b/board/sbc8641d/Kconfig @@ -0,0 +1,9 @@ +if TARGET_SBC8641D + +config SYS_BOARD + default "sbc8641d" + +config SYS_CONFIG_NAME + default "sbc8641d" + +endif diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS new file mode 100644 index 0000000000..a50b541ffe --- /dev/null +++ b/board/sbc8641d/MAINTAINERS @@ -0,0 +1,6 @@ +SBC8641D BOARD +M: Paul Gortmaker +S: Maintained +F: board/sbc8641d/ +F: include/configs/sbc8641d.h +F: configs/sbc8641d_defconfig diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile index 0cbc0d0a90..a9b20266bc 100644 --- a/board/sbc8641d/Makefile +++ b/board/sbc8641d/Makefile @@ -5,26 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-$(CONFIG_FSL_DDR2) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude ($obj).depend - -######################################################################### +obj-y += sbc8641d.o +obj-y += law.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index 996ffe206d..b31ea3432e 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 3a4815499f..6bdf1a28e9 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -9,7 +9,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include @@ -93,7 +93,7 @@ long int fixed_sdram (void) { #if !defined(CONFIG_SYS_RAMBOOT) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + volatile struct ccsr_ddr *ddr = &immap->im_ddr1; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; @@ -111,7 +111,7 @@ long int fixed_sdram (void) ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; + ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; @@ -142,7 +142,7 @@ long int fixed_sdram (void) ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; - ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; + ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT; ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL; @@ -173,11 +173,13 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup (void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); FT_FSL_PCI_SETUP; + + return 0; } #endif diff --git a/board/sc3/Kconfig b/board/sc3/Kconfig new file mode 100644 index 0000000000..88a6d86d8b --- /dev/null +++ b/board/sc3/Kconfig @@ -0,0 +1,9 @@ +if TARGET_SC3 + +config SYS_BOARD + default "sc3" + +config SYS_CONFIG_NAME + default "sc3" + +endif diff --git a/board/sc3/MAINTAINERS b/board/sc3/MAINTAINERS new file mode 100644 index 0000000000..b86c6e6012 --- /dev/null +++ b/board/sc3/MAINTAINERS @@ -0,0 +1,6 @@ +SC3 BOARD +M: Heiko Schocher +S: Maintained +F: board/sc3/ +F: include/configs/sc3.h +F: configs/sc3_defconfig diff --git a/board/sc3/Makefile b/board/sc3/Makefile index 7369072617..c1d163ee42 100644 --- a/board/sc3/Makefile +++ b/board/sc3/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o sc3nand.o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = sc3.o sc3nand.o +obj-y += init.o diff --git a/board/sc3/init.S b/board/sc3/init.S index 635236835a..097aa4a5e7 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -1,36 +1,9 @@ -/*------------------------------------------------------------------------------+ - * - * This souce code has been made available to you by EuroDesign - * (www.eurodsn.de). It's based on the original IBM source code, so - * this follows: - * - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *------------------------------------------------------------------------------- */ - +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/scb9328/Kconfig b/board/scb9328/Kconfig new file mode 100644 index 0000000000..68e99ea2e3 --- /dev/null +++ b/board/scb9328/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SCB9328 + +config SYS_BOARD + default "scb9328" + +config SYS_SOC + default "imx" + +config SYS_CONFIG_NAME + default "scb9328" + +endif diff --git a/board/scb9328/MAINTAINERS b/board/scb9328/MAINTAINERS new file mode 100644 index 0000000000..0917266afd --- /dev/null +++ b/board/scb9328/MAINTAINERS @@ -0,0 +1,6 @@ +SCB9328 BOARD +M: Torsten Koschorrek +S: Maintained +F: board/scb9328/ +F: include/configs/scb9328.h +F: configs/scb9328_defconfig diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile index 779507d081..0b08f1a871 100644 --- a/board/scb9328/Makefile +++ b/board/scb9328/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := scb9328.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := scb9328.o flash.o +obj-y += lowlevel_init.o diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c index e3a582f3dc..73bfa00eed 100644 --- a/board/scb9328/flash.c +++ b/board/scb9328/flash.c @@ -72,8 +72,10 @@ static FLASH_BUS_RET flash_status_reg (void) FLASH_BUS *addr = (FLASH_BUS *) 0; + /* cppcheck-suppress nullPointer */ *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + /* cppcheck-suppress nullPointer */ return *addr; } diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h index 77498b6e1d..5596d27133 100644 --- a/board/scb9328/intel.h +++ b/board/scb9328/intel.h @@ -2,28 +2,7 @@ * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the ETC s.r.o. nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause * * Written by Marcel Telka , 2002. * diff --git a/board/schulercontrol/sc_sps_1/Kconfig b/board/schulercontrol/sc_sps_1/Kconfig new file mode 100644 index 0000000000..2461d0cc50 --- /dev/null +++ b/board/schulercontrol/sc_sps_1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SC_SPS_1 + +config SYS_BOARD + default "sc_sps_1" + +config SYS_VENDOR + default "schulercontrol" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "sc_sps_1" + +endif diff --git a/board/schulercontrol/sc_sps_1/MAINTAINERS b/board/schulercontrol/sc_sps_1/MAINTAINERS new file mode 100644 index 0000000000..74849cdfaf --- /dev/null +++ b/board/schulercontrol/sc_sps_1/MAINTAINERS @@ -0,0 +1,6 @@ +SC_SPS_1 BOARD +M: Marek Vasut +S: Maintained +F: board/schulercontrol/sc_sps_1/ +F: include/configs/sc_sps_1.h +F: configs/sc_sps_1_defconfig diff --git a/board/schulercontrol/sc_sps_1/Makefile b/board/schulercontrol/sc_sps_1/Makefile index 81482e30da..df72fc9f55 100644 --- a/board/schulercontrol/sc_sps_1/Makefile +++ b/board/schulercontrol/sc_sps_1/Makefile @@ -5,27 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifndef CONFIG_SPL_BUILD -COBJS := sc_sps_1.o +obj-y := sc_sps_1.o else -COBJS := spl_boot.o +obj-y := spl_boot.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/schulercontrol/sc_sps_1/spl_boot.c b/board/schulercontrol/sc_sps_1/spl_boot.c index 1fe9224e5a..60195c3a7d 100644 --- a/board/schulercontrol/sc_sps_1/spl_boot.c +++ b/board/schulercontrol/sc_sps_1/spl_boot.c @@ -138,9 +138,9 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED, }; -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } void mxs_adjust_memory_params(uint32_t *dram_vals) diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile deleted file mode 100644 index b9fa864bb5..0000000000 --- a/board/sheldon/simpc8313/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o sdram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sheldon/simpc8313/README.simpc8313 b/board/sheldon/simpc8313/README.simpc8313 deleted file mode 100644 index b362c6aeea..0000000000 --- a/board/sheldon/simpc8313/README.simpc8313 +++ /dev/null @@ -1,80 +0,0 @@ -Sheldon Instruments SIMPC8313 Board ------------------------------------------ - -1. Board Switches and Jumpers - - S2 is used to set CFG_RESET_SOURCE. - - To boot the image in Large page NAND flash, use these DIP - switch settings for S2: - - +----------+ ON - | * * **** | - | * * | - +----------+ - 12345678 - - To boot the image in Small page NAND flash, use these DIP - switch settings for S2: - - +----------+ ON - | *** **** | - | * | - +----------+ - 12345678 - (where the '*' indicates the position of the tab of the switch.) - -2. Memory Map - The memory map looks like this: - - 0x0000_0000 0x1fff_ffff DDR 512M - 0x8000_0000 0x8fff_ffff PCI MEM 256M - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M - 0xe000_0000 0xe00f_ffff IMMR 1M - 0xe200_0000 0xe20f_ffff PCI IO 16M - 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K - or - 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K - 0xff00_0000 0xff00_7fff FPGA (CS1) 1M - -3. Compilation - - Assuming you're using BASH (or similar) as your shell: - - export CROSS_COMPILE=your-cross-compiler-prefix- - make distclean - make SIMPC8313_LP_config - (or make SIMPC8313_SP_config, depending on the page size - of your NAND flash) - make - -4. Downloading and Flashing Images - -4.1 Reflash U-boot Image using U-boot - - =>run update_uboot - - You may want to try - =>tftp $loadaddr $uboot - first, to make sure that the TFTP load will succeed before it - goes ahead and wipes out your current firmware. And of course, - if the new u-boot doesn't boot, you can plug the board into - your PCI slot and with the supplied driver and sample app - you can reburn a working u-boot. - -4.2 Downloading and Booting Linux Kernel - - Ensure that all networking-related environment variables are set - properly (including ipaddr, serverip, gatewayip (if needed), - netmask, ethaddr, eth1addr, fdtfile, and bootfile). - - =>tftp $loadaddr uImage - =>nand write $loadaddr kernel $filesize - =>tftp $loadaddr $fdtfile - =>nand write $loadaddr 7e0000 1800 - - =>boot - -5 Notes - - The console baudrate for SIMPC8313 is 115200bps. diff --git a/board/sheldon/simpc8313/config.mk b/board/sheldon/simpc8313/config.mk deleted file mode 100644 index d1b4e2eeb6..0000000000 --- a/board/sheldon/simpc8313/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -ifdef CONFIG_NAND_LP -PAD_TO = 0xFFF20000 -else -PAD_TO = 0xFFF04000 -endif diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c deleted file mode 100644 index 7c12fe851c..0000000000 --- a/board/sheldon/simpc8313/sdram.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * Copyright (C) Sheldon Instruments, Inc. 2008 - * - * Author: Ron Madrid - * - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static long fixed_sdram(void); - -#if defined(CONFIG_NAND_SPL) -void si_wait_i2c(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - - while (!(__raw_readb(&im->i2c[0].sr) & 0x02)) - ; - - __raw_writeb(0x00, &im->i2c[0].sr); - - sync(); - - return; -} - -void si_read_i2c(u32 lbyte, int count, u8 *buffer) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 i; - u8 chip = 0x50 << 1; /* boot sequencer I2C */ - u32 ubyte = (lbyte & 0xff00) >> 8; - - lbyte &= 0xff; - - /* - * Set up controller - */ - __raw_writeb(0x3f, &im->i2c[0].fdr); - __raw_writeb(0x00, &im->i2c[0].adr); - __raw_writeb(0x00, &im->i2c[0].sr); - __raw_writeb(0x00, &im->i2c[0].dr); - - while (__raw_readb(&im->i2c[0].sr) & 0x20) - ; - - /* - * Writing address to device - */ - __raw_writeb(0xb0, &im->i2c[0].cr); - sync(); - __raw_writeb(chip, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xb0, &im->i2c[0].cr); - sync(); - __raw_writeb(ubyte, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(lbyte, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xb4, &im->i2c[0].cr); - sync(); - __raw_writeb(chip + 1, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xa0, &im->i2c[0].cr); - sync(); - - /* - * Dummy read - */ - __raw_readb(&im->i2c[0].dr); - - si_wait_i2c(); - - /* - * Read actual data - */ - for (i = 0; i < count; i++) - { - if (i == (count - 2)) /* Reached next to last byte, No ACK */ - __raw_writeb(0xa8, &im->i2c[0].cr); - if (i == (count - 1)) /* Reached last byte, STOP */ - __raw_writeb(0x88, &im->i2c[0].cr); - - /* Read byte of data */ - buffer[i] = __raw_readb(&im->i2c[0].dr); - - if (i == (count - 1)) - break; - si_wait_i2c(); - } - - return; -} -#endif /* CONFIG_NAND_SPL */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbc_t *lbc = &im->im_lbc; - u32 msize; - - if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar); - - msize = fixed_sdram(); - - /* Local Bus setup lbcr and mrtpr */ - __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr); - __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr); - sync(); - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -/************************************************************************* - * fixed sdram init -- reads values from boot sequencer I2C - ************************************************************************/ -static long fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msizelog2, msize = 1; -#if defined(CONFIG_NAND_SPL) - u32 i; - const u8 bytecount = 135; - u8 buffer[bytecount]; - u32 addr, data; - - si_read_i2c(0, bytecount, buffer); - - for (i = 18; i < bytecount; i += 7){ - addr = (u32)buffer[i]; - addr <<= 8; - addr |= (u32)buffer[i + 1]; - addr <<= 2; - data = (u32)buffer[i + 2]; - data <<= 8; - data |= (u32)buffer[i + 3]; - data <<= 8; - data |= (u32)buffer[i + 4]; - data <<= 8; - data |= (u32)buffer[i + 5]; - - __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr)); - } - - sync(); - - /* enable DDR controller */ - __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg); -#endif /* (CONFIG_NAND_SPL) */ - - msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1); - msize <<= (msizelog2 - 20); - - return msize; -} diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c deleted file mode 100644 index 31406fa66d..0000000000 --- a/board/sheldon/simpc8313/simpc8313.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * Copyright (C) Sheldon Instruments, Inc. 2008 - * - * Author: Ron Madrid - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_NAND_SPL -int checkboard(void) -{ - puts("Board: Sheldon Instruments SIMPC8313\n"); - return 0; -} - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions }; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - clk->occr |= 0xe0000000; - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} - -/* - * Miscellaneous late-boot configurations - */ -int misc_init_r(void) -{ - int rc = 0; - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - fsl_lbc_t *lbus = &immap->im_lbc; - u32 *mxmr = &lbus->mamr; /* Pointer to mamr */ - - /* UPM Table Configuration Code */ - static uint UPMATable[] = { - /* Read Single-Beat (RSS) */ - 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Read Burst (RBS) */ - 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c, - 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Write Single-Beat (WSS) */ - 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Write Burst (WBS) */ - 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00, - 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c, - 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Refresh Timer (RTS) */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Exception Condition (EXS) */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 - }; - - upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); - - /* Set LUPWAIT to be active low and enabled */ - out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS); - - return rc; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif -#else /* CONFIG_NAND_SPL */ -void board_init_f(ulong bootflag) -{ - NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - puts("NAND boot... "); - init_timebase(); - initdram(0); - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (gd->flags & GD_FLG_SILENT) - return; - - if (c == '\n') - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); - - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); -} -#endif diff --git a/board/shmin/Kconfig b/board/shmin/Kconfig new file mode 100644 index 0000000000..467580c67b --- /dev/null +++ b/board/shmin/Kconfig @@ -0,0 +1,9 @@ +if TARGET_SHMIN + +config SYS_BOARD + default "shmin" + +config SYS_CONFIG_NAME + default "shmin" + +endif diff --git a/board/shmin/MAINTAINERS b/board/shmin/MAINTAINERS new file mode 100644 index 0000000000..5dee37bdf7 --- /dev/null +++ b/board/shmin/MAINTAINERS @@ -0,0 +1,7 @@ +SHMIN BOARD +M: Nobuhiro Iwamatsu +M: Nobuhiro Iwamatsu +S: Maintained +F: board/shmin/ +F: include/configs/shmin.h +F: configs/shmin_defconfig diff --git a/board/shmin/Makefile b/board/shmin/Makefile index 0377723f23..daf36deed0 100644 --- a/board/shmin/Makefile +++ b/board/shmin/Makefile @@ -6,25 +6,5 @@ # # SPDX-License-Identifier: GPL-2.0+ -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).o - -OBJS := shmin.o -SOBJS := lowlevel_init.o - -LIB := $(addprefix $(obj),$(LIB)) -OBJS := $(addprefix $(obj),$(OBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := shmin.o +obj-y += lowlevel_init.o diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c new file mode 100644 index 0000000000..cc0ac6b0bd --- /dev/null +++ b/board/siemens/common/board.c @@ -0,0 +1,187 @@ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/board/ti/am335x/board.c + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_set_bus_num(0); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + spl_siemens_board_init(); + board_init_ddr(); + + return; +} +#endif /* #ifdef CONFIG_SPL_BUILD */ + +#ifndef CONFIG_SPL_BUILD +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif /* defined(CONFIG_HW_WATCHDOG) */ + i2c_set_bus_num(0); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_FACTORYSET + factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); +#endif + gpmc_init(); + +#ifdef CONFIG_VIDEO + board_video_init(); +#endif + + return 0; +} +#endif /* #ifndef CONFIG_SPL_BUILD */ + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +#ifndef CONFIG_SPL_BUILD +#if defined(BOARD_DFU_BUTTON_GPIO) +/* + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +static int +do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int button = 0; + int gpio; + + gpio = BOARD_DFU_BUTTON_GPIO; + gpio_request(gpio, "DFU"); + gpio_direction_input(gpio); + if (gpio_get_value(gpio)) + button = 1; + else + button = 0; + + gpio_free(gpio); + + return button; +} + +U_BOOT_CMD( + dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, + "Return the status of the DFU button", + "" +); +#endif +/* + * This command sets led + * Input - name of led + * value of led + * Returns - 1 if input does not match + * 0 if led was set + */ +static int +do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int gpio = 0; + if (argc != 3) + goto exit; +#if defined(BOARD_STATUS_LED) + if (!strcmp(argv[1], "stat")) + gpio = BOARD_STATUS_LED; +#endif +#if defined(BOARD_DFU_BUTTON_LED) + if (!strcmp(argv[1], "dfu")) + gpio = BOARD_DFU_BUTTON_LED; +#endif + /* If argument does not mach exit */ + if (gpio == 0) + goto exit; + gpio_request(gpio, ""); + gpio_direction_output(gpio, 1); + if (!strcmp(argv[2], "1")) + gpio_set_value(gpio, 1); + else + gpio_set_value(gpio, 0); + return 0; +exit: + return 1; +} + +U_BOOT_CMD( + led, CONFIG_SYS_MAXARGS, 2, do_setled, + "Set led on or off", + "dfu val - set dfu led\nled stat val - set status led" +); + +static int +do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("\n\n\n Go into infinite loop\n\n\n"); + while (1) + ; + return 0; +}; + +U_BOOT_CMD( + testwdt, CONFIG_SYS_MAXARGS, 1, do_usertestwdt, + "Sends U-Boot into infinite loop", + "" +); +#endif /* !CONFIG_SPL_BUILD */ diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c new file mode 100644 index 0000000000..7baac3dda6 --- /dev/null +++ b/board/siemens/common/factoryset.c @@ -0,0 +1,322 @@ +/* + * + * Read FactorySet information from EEPROM into global structure. + * (C) Copyright 2013 Siemens Schweiz AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#if !defined(CONFIG_SPL_BUILD) + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "factoryset.h" + +#define EEPR_PG_SZ 0x80 +#define EEPROM_FATORYSET_OFFSET 0x400 +#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ + +/* Global variable that contains necessary information from FactorySet */ +struct factorysetcontainer factory_dat; + +#define fact_get_char(i) *((char *)&eeprom_buf[i]) + +static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2) +{ + if (s1 == NULL) + return -1; + + while (*s1 == fact_get_char(i2++)) + if (*s1++ == '=') + return i2; + + if (*s1 == '\0' && fact_get_char(i2-1) == '=') + return i2; + + return -1; +} + +static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name, + uchar *buf, int len) +{ + int i, nxt = 0; + + for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) { + int val, n; + + for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) { + if (nxt >= size) + return -1; + } + + val = fact_match(eeprom_buf, (uchar *)name, i); + if (val < 0) + continue; + + /* found; copy out */ + for (n = 0; n < len; ++n, ++buf) { + *buf = fact_get_char(val++); + if (*buf == '\0') + return n; + } + + if (n) + *--buf = '\0'; + + printf("env_buf [%d bytes] too small for value of \"%s\"\n", + len, name); + + return n; + } + return -1; +} + +static +int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record, + uchar *name, uchar *buf, int len) +{ + int ret = -1; + int i, nxt = 0; + int c; + unsigned char end = 0xff; + unsigned char tmp; + + for (i = 0; fact_get_char(i) != end; i = nxt) { + nxt = i + 1; + if (fact_get_char(i) == '>') { + int pos; + int endpos; + int z; + int level = 0; + + c = strncmp((char *)&eeprom_buf[i + 1], (char *)record, + strlen((char *)record)); + if (c == 0) { + /* record found */ + pos = i + strlen((char *)record) + 2; + nxt = pos; + /* search for "<" */ + c = -1; + for (z = pos; fact_get_char(z) != end; z++) { + if (fact_get_char(z) == '<') { + if (level == 0) { + endpos = z; + nxt = endpos; + c = 0; + break; + } else { + level--; + } + } + if (fact_get_char(z) == '>') + level++; + } + } else { + continue; + } + if (c == 0) { + /* end found -> call get_factory_val */ + tmp = eeprom_buf[endpos]; + eeprom_buf[endpos] = end; + ret = get_factory_val(&eeprom_buf[pos], + endpos - pos, name, buf, len); + /* fix buffer */ + eeprom_buf[endpos] = tmp; + debug("%s: %s.%s = %s\n", + __func__, record, name, buf); + return ret; + } + } + } + return ret; +} + +int factoryset_read_eeprom(int i2c_addr) +{ + int i, pages = 0, size = 0; + unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH]; + unsigned char *cp, *cp1; + +#if defined(CONFIG_DFU_FUNCTION) + factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM; + factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM; +#endif + if (i2c_probe(i2c_addr)) + goto err; + + if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr))) + goto err; + + if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) { + printf("FactorySet is not right in eeprom.\n"); + return 1; + } + + /* get FactorySet size */ + size = (hdr[2] << 8) + hdr[3] + sizeof(hdr); + if (size > 0x3bfa) + size = 0x3bfa; + + pages = size / EEPR_PG_SZ; + + /* + * read the eeprom using i2c + * I can not read entire eeprom in once, so separate into several + * times. Furthermore, fetch eeprom take longer time, so we fetch + * data after every time we got a record from eeprom + */ + debug("Read eeprom page :\n"); + for (i = 0; i < pages; i++) + if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2, + eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ)) + goto err; + + if (size % EEPR_PG_SZ) + if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2, + eeprom_buf + (pages * EEPR_PG_SZ), + (size % EEPR_PG_SZ))) + goto err; + + /* we do below just for eeprom align */ + for (i = 0; i < size; i++) + if (eeprom_buf[i] == '\n') + eeprom_buf[i] = 0; + + /* skip header */ + size -= sizeof(hdr); + cp = (uchar *)eeprom_buf + sizeof(hdr); + + /* get mac address */ + get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac", + buf, MAX_STRING_LENGTH); + cp1 = buf; + for (i = 0; i < 6; i++) { + factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16); + cp1 += 3; + } + +#if defined(CONFIG_DFU_FUNCTION) + /* read vid and pid for dfu mode */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"vid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_vendor_id = simple_strtoul((char *)buf, + NULL, 16); + } + + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"pid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_product_id = simple_strtoul((char *)buf, + NULL, 16); + } + printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id, + factory_dat.usb_product_id); +#endif +#if defined(CONFIG_VIDEO) + if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1", + (uchar *)"name", factory_dat.disp_name, + MAX_STRING_LENGTH)) { + debug("display name: %s\n", factory_dat.disp_name); + } +#endif + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"num", factory_dat.serial, + MAX_STRING_LENGTH)) { + debug("serial number: %s\n", factory_dat.serial); + } + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"ver", buf, + MAX_STRING_LENGTH)) { + factory_dat.version = simple_strtoul((char *)buf, + NULL, 16); + debug("version number: %d\n", factory_dat.version); + } + /* Get ASN from factory set if available */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"id", factory_dat.asn, + MAX_STRING_LENGTH)) { + debug("factoryset asn: %s\n", factory_dat.asn); + } else { + factory_dat.asn[0] = 0; + } + /* Get COMP/ver from factory set if available */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP", + (uchar *)"ver", + factory_dat.comp_version, + MAX_STRING_LENGTH)) { + debug("factoryset COMP/ver: %s\n", factory_dat.comp_version); + } else { + strcpy((char *)factory_dat.comp_version, "1.0"); + } + + return 0; + +err: + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; +} + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static int factoryset_mac_setenv(void) +{ + uint8_t mac_addr[6]; + + debug("FactorySet: Set mac address\n"); + if (is_valid_ether_addr(factory_dat.mac)) { + memcpy(mac_addr, factory_dat.mac, 6); + } else { + uint32_t mac_hi, mac_lo; + + debug("Warning: FactorySet: not set. Fallback to E-fuse\n"); + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (!is_valid_ether_addr(mac_addr)) { + printf("Warning: ethaddr not set by FactorySet or E-fuse. Set variable to overcome this.\n"); + return -1; + } + } + + eth_setenv_enetaddr("ethaddr", mac_addr); + return 0; +} + +int factoryset_setenv(void) +{ + int ret = 0; + + if (factoryset_mac_setenv() < 0) + ret = -1; + + return ret; +} + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor); + put_unaligned(factory_dat.usb_product_id, &dev->idProduct); + g_dnl_set_serialnumber((char *)factory_dat.serial); + + return 0; +} + +int g_dnl_get_board_bcd_device_number(int gcnum) +{ + return factory_dat.version; +} +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h new file mode 100644 index 0000000000..3f23d5ebf4 --- /dev/null +++ b/board/siemens/common/factoryset.h @@ -0,0 +1,31 @@ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FACTORYSET_H +#define __FACTORYSET_H + +#define MAX_STRING_LENGTH 32 + +struct factorysetcontainer { + uchar mac[6]; + int usb_vendor_id; + int usb_product_id; + int pxm50; +#if defined(CONFIG_VIDEO) + unsigned char disp_name[MAX_STRING_LENGTH]; +#endif + unsigned char serial[MAX_STRING_LENGTH]; + int version; + uchar asn[MAX_STRING_LENGTH]; + uchar comp_version[MAX_STRING_LENGTH]; +}; + +int factoryset_read_eeprom(int i2c_addr); +int factoryset_setenv(void); +extern struct factorysetcontainer factory_dat; + +#endif /* __FACTORYSET_H */ diff --git a/board/siemens/corvus/Kconfig b/board/siemens/corvus/Kconfig new file mode 100644 index 0000000000..7b505aac36 --- /dev/null +++ b/board/siemens/corvus/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CORVUS + +config SYS_BOARD + default "corvus" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "corvus" + +endif diff --git a/board/siemens/corvus/MAINTAINERS b/board/siemens/corvus/MAINTAINERS new file mode 100644 index 0000000000..59176aae57 --- /dev/null +++ b/board/siemens/corvus/MAINTAINERS @@ -0,0 +1,6 @@ +CORVUS BOARD +M: Heiko Schocher +S: Maintained +F: board/siemens/corvus/ +F: include/configs/corvus.h +F: configs/corvus_defconfig diff --git a/board/siemens/corvus/Makefile b/board/siemens/corvus/Makefile new file mode 100644 index 0000000000..f3ebf77f1b --- /dev/null +++ b/board/siemens/corvus/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for siemens CORVUS (AT91SAM9G45) based board +# (C) Copyright 2013 Siemens AG +# +# Based on: +# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c new file mode 100644 index 0000000000..f3f6dae459 --- /dev/null +++ b/board/siemens/corvus/board.c @@ -0,0 +1,282 @@ +/* + * Board functions for Siemens CORVUS (AT91SAM9G45) based board + * (C) Copyright 2013 Siemens AG + * + * Based on: + * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include +#endif +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void corvus_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOA); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); +} + +#if defined(CONFIG_SPL_BUILD) +#include +#include + +void at91_spl_board_init(void) +{ + /* + * For on the sam9m10g45ek board, the chip wm9711 stay in the test + * mode, so it need do some action to exit mode. + */ + at91_set_gpio_output(AT91_PIN_PD7, 0); + at91_set_gpio_output(AT91_PIN_PD8, 0); + at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); + at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + + corvus_nand_hw_init(); + + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PB7, 1); + + /* check if button is pressed */ + if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { + u32 boot_device; + + debug("Recovery button pressed\n"); + boot_device = spl_boot_device(); + switch (boot_device) { +#ifdef CONFIG_SPL_NAND_SUPPORT + case BOOT_DEVICE_NAND: + nand_init(); + spl_nand_erase_one(0, 0); + break; +#endif + } + } +} + +#include +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DQMS_SHARED | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3); + ddr2->rtr = 0x24b; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ + 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ + 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddr ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + writel(0x4, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&mat->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; + writel(csa, &mat->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_CS6, &ddr2); +} +#endif + +#ifdef CONFIG_CMD_USB +static void taurus_usb_hw_init(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIODE); + + at91_set_gpio_output(AT91_PIN_PD1, 0); + at91_set_gpio_output(AT91_PIN_PD3, 0); +} +#endif + +#ifdef CONFIG_MACB +static void corvus_macb_hw_init(void) +{ + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); + + at91_phy_reset(); + + /* Re-enable pull-up */ + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); + + /* And the pins. */ + at91_macb_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + corvus_nand_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SPI + at91_spi0_hw_init(1 << 4); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + corvus_macb_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + taurus_usb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); +#endif + return rc; +} + +/* SPI chip select control */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < 2; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + switch (slave->cs) { + case 1: + at91_set_gpio_output(AT91_PIN_PB18, 0); + break; + case 0: + default: + at91_set_gpio_output(AT91_PIN_PB3, 0); + break; + } +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + switch (slave->cs) { + case 1: + at91_set_gpio_output(AT91_PIN_PB18, 1); + break; + case 0: + default: + at91_set_gpio_output(AT91_PIN_PB3, 1); + break; + } +} diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig new file mode 100644 index 0000000000..d138ecea9d --- /dev/null +++ b/board/siemens/draco/Kconfig @@ -0,0 +1,31 @@ +if TARGET_DRACO + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "draco" + +endif + +if TARGET_DXR2 + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "dxr2" + +endif diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS new file mode 100644 index 0000000000..f6b68ca400 --- /dev/null +++ b/board/siemens/draco/MAINTAINERS @@ -0,0 +1,8 @@ +DRACO BOARD +M: Roger Meier +S: Maintained +F: board/siemens/draco/ +F: include/configs/draco.h +F: configs/draco_defconfig +F: include/configs/dxr2.h +F: configs/dxr2_defconfig diff --git a/board/siemens/draco/Makefile b/board/siemens/draco/Makefile new file mode 100644 index 0000000000..f15993216b --- /dev/null +++ b/board/siemens/draco/Makefile @@ -0,0 +1,21 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := mux.o +endif + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-y += ../common/factoryset.o +endif diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c new file mode 100644 index 0000000000..ede73baf3e --- /dev/null +++ b/board/siemens/draco/board.c @@ -0,0 +1,292 @@ +/* + * Board functions for TI AM335X based draco board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * + * Board functions for TI AM335X based boards + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static struct draco_baseboard_id __attribute__((section(".data"))) settings; + +#if DDR_PLL_FREQ == 303 +/* Default@303MHz-i0 */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, + 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32, + 0x0000093B, 0x0000014A, + "default name @303MHz \0", + "default marking \0", +}; +#elif DDR_PLL_FREQ == 400 +/* Default@400MHz-i0 */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab, + 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232, + 0x00000618, 0x0000014A, + "default name @400MHz \0", + "default marking \0", +}; +#endif + +static void set_default_ddr3_timings(void) +{ + printf("Set default DDR3 settings\n"); + settings.ddr3 = ddr3_default; +} + +static void print_ddr3_timings(void) +{ + printf("\nDDR3\n"); + printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); + printf("device:\t\t%s\n", settings.ddr3.manu_name); + printf("marking:\t%s\n", settings.ddr3.manu_marking); + printf("timing parameters\n"); + printf("diff\teeprom\tdefault\n"); + PRINTARGS(magic); + PRINTARGS(version); + PRINTARGS(ddr3_sratio); + PRINTARGS(iclkout); + + PRINTARGS(dt0rdsratio0); + PRINTARGS(dt0wdsratio0); + PRINTARGS(dt0fwsratio0); + PRINTARGS(dt0wrsratio0); + + PRINTARGS(sdram_tim1); + PRINTARGS(sdram_tim2); + PRINTARGS(sdram_tim3); + + PRINTARGS(emif_ddr_phy_ctlr_1); + + PRINTARGS(sdram_config); + PRINTARGS(ref_ctrl); + PRINTARGS(ioctr_val); +} + +static void print_chip_data(void) +{ + printf("\nCPU BOARD\n"); + printf("device: \t'%s'\n", settings.chip.sdevname); + printf("hw version: \t'%s'\n", settings.chip.shwver); +} +#endif /* CONFIG_SPL_BUILD */ + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; + } + +#ifdef CONFIG_SPL_BUILD + /* Read Siemens eeprom data (DDR3) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, + (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); + set_default_ddr3_timings(); + } + /* Read Siemens eeprom data (CHIP) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, + (uchar *)&settings.chip, sizeof(settings.chip))) + printf("Could not read chip settings\n"); + + if (ddr3_default.magic == settings.ddr3.magic && + ddr3_default.version == settings.ddr3.version) { + printf("Using DDR3 settings from EEPROM\n"); + } else { + if (ddr3_default.magic != settings.ddr3.magic) + printf("Warning: No valid DDR3 data in eeprom.\n"); + if (ddr3_default.version != settings.ddr3.version) + printf("Warning: DDR3 data version does not match.\n"); + + printf("Using default settings\n"); + set_default_ddr3_timings(); + } + + if (MAGIC_CHIP == settings.chip.magic) + print_chip_data(); + else + printf("Warning: No chip data in eeprom\n"); + + print_ddr3_timings(); +#endif + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs draco_ddr3_emif_reg_data = { + .zq_config = 0x50074BE4, +}; + +struct ddr_data draco_ddr3_data = { +}; + +struct cmd_control draco_ddr3_cmd_ctrl_data = { +}; + +struct ctrl_ioregs draco_ddr3_ioregs = { +}; + + /* pass values from eeprom */ + draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; + draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; + draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; + draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = + settings.ddr3.emif_ddr_phy_ctlr_1; + draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; + + draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; + draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; + draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; + draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; + + draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; + draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; + draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; + + draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, + + config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data, + &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + + factoryset_setenv(); + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} + +static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + /* Reset SMSC LAN9303 switch for default configuration */ + gpio_request(GPIO_LAN9303_NRST, "nRST"); + gpio_direction_output(GPIO_LAN9303_NRST, 0); + /* assert active low reset for 200us */ + udelay(200); + gpio_set_value(GPIO_LAN9303_NRST, 1); + + return 0; +}; + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset, + "Reset LAN9303 switch via its reset pin", + "" +); +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + omap_nand_switch_ecc(1, 8); + + return 0; +} +#endif + +#include "../common/board.c" diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h new file mode 100644 index 0000000000..ff8ab764c5 --- /dev/null +++ b/board/siemens/draco/board.h @@ -0,0 +1,72 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \ + settings.ddr3.x, ddr3_default.x +#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y)) +#define MAGIC_CHIP 0x50494843 + +/* Automatic generated definition */ +/* Wed, 16 Apr 2014 16:50:41 +0200 */ +/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ +struct ddr3_data { + unsigned int magic; /* 0x33524444 */ + unsigned int version; /* 0x56312e35 */ + unsigned short int ddr3_sratio; /* 0x0080 */ + unsigned short int iclkout; /* 0x0000 */ + unsigned short int dt0rdsratio0; /* 0x003A */ + unsigned short int dt0wdsratio0; /* 0x003F */ + unsigned short int dt0fwsratio0; /* 0x009F */ + unsigned short int dt0wrsratio0; /* 0x0079 */ + unsigned int sdram_tim1; /* 0x0888A39B */ + unsigned int sdram_tim2; /* 0x26247FDA */ + unsigned int sdram_tim3; /* 0x501F821F */ + unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ + unsigned int sdram_config; /* 0x61A44A32 */ + unsigned int ref_ctrl; /* 0x0000093B */ + unsigned int ioctr_val; /* 0x0000014A */ + char manu_name[32]; /* "default@303MHz \0" */ + char manu_marking[32]; /* "default \0" */ +}; + +struct chip_data { + unsigned int magic; + char sdevname[16]; + char shwver[7]; +}; + +struct draco_baseboard_id { + struct ddr3_data ddr3; + struct chip_data chip; +}; + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c new file mode 100644 index 0000000000..eaa3c70798 --- /dev/null +++ b/board/siemens/draco/mux.c @@ -0,0 +1,272 @@ +/* + * pinmux setup for siemens draco board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux gpios_pin_mux[] = { + /* DFU button GPIO0_27*/ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)}, + {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ + {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ + /* Triacs in HW Rev 2 */ + {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/ + {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/ + {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/ + /* Triacs initial HW Rev */ + {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */ + {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */ + {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */ + {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */ + {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */ + {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */ + {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */ + {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */ + /* Remaining pins that were not used in this file */ + {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS}, + /* nRST for SMSC LAN9303 switch - GPIO2_24 */ + {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */ + {-1}, +}; + +static struct module_pin_mux ethernet_pin_mux[] = { + {OFFSET(mii1_col), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + enable_uart3_pin_mux(); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ethernet_pin_mux); + configure_module_pin_mux(gpios_pin_mux); +} diff --git a/board/siemens/pxm2/Kconfig b/board/siemens/pxm2/Kconfig new file mode 100644 index 0000000000..62604ecb39 --- /dev/null +++ b/board/siemens/pxm2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PXM2 + +config SYS_BOARD + default "pxm2" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "pxm2" + +endif diff --git a/board/siemens/pxm2/MAINTAINERS b/board/siemens/pxm2/MAINTAINERS new file mode 100644 index 0000000000..fa734c9c11 --- /dev/null +++ b/board/siemens/pxm2/MAINTAINERS @@ -0,0 +1,6 @@ +PXM2 BOARD +M: Roger Meier +S: Maintained +F: board/siemens/pxm2/ +F: include/configs/pxm2.h +F: configs/pxm2_defconfig diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile new file mode 100644 index 0000000000..f15993216b --- /dev/null +++ b/board/siemens/pxm2/Makefile @@ -0,0 +1,21 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := mux.o +endif + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-y += ../common/factoryset.o +endif diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c new file mode 100644 index 0000000000..264ba025b7 --- /dev/null +++ b/board/siemens/pxm2/board.c @@ -0,0 +1,465 @@ +/* + * Board functions for TI AM335X based pxm2 board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../drivers/video/da8xx-fb.h" +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" +#include "pmic.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs pxm2_ddr3_emif_reg_data = { + .sdram_config = 0x41805332, + .sdram_tim1 = 0x666b3c9, + .sdram_tim2 = 0x243631ca, + .sdram_tim3 = 0x33f, + .emif_ddr_phy_ctlr_1 = 0x100005, + .zq_config = 0, + .ref_ctrl = 0x81a, +}; + +struct ddr_data pxm2_ddr3_data = { + .datardsratio0 = 0x81204812, + .datawdsratio0 = 0, + .datafwsratio0 = 0x8020080, + .datawrsratio0 = 0x4010040, +}; + +struct cmd_control pxm2_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x80, + .cmd0iclkout = 0, + .cmd1csratio = 0x80, + .cmd1iclkout = 0, + .cmd2csratio = 0x80, + .cmd2iclkout = 0, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = DDR_IOCTRL_VAL, + .cm1ioctl = DDR_IOCTRL_VAL, + .cm2ioctl = DDR_IOCTRL_VAL, + .dt0ioctl = DDR_IOCTRL_VAL, + .dt1ioctl = DDR_IOCTRL_VAL, +}; + + config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, + &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); +} + +/* + * voltage switching for MPU frequency switching. + * @module = mpu - 0, core - 1 + * @vddx_op_vol_sel = vdd voltage to set + */ + +#define MPU 0 +#define CORE 1 + +int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf[4]; + unsigned int reg_offset; + + if (module == MPU) + reg_offset = PMIC_VDD1_OP_REG; + else + reg_offset = PMIC_VDD2_OP_REG; + + /* Select VDDx OP */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_CMD_MASK; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + /* Configure VDDx OP Voltage */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_SEL_MASK; + buf[0] |= vddx_op_vol_sel; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel) + return 1; + + return 0; +} + +#define OSC (V_OSCK/1000000) + +const struct dpll_params dpll_mpu_pxm2 = { + 720, OSC-1, 1, -1, -1, -1, -1}; + +void spl_siemens_board_init(void) +{ + uchar buf[4]; + /* + * pxm2 PMIC code. All boards currently want an MPU voltage + * of 1.2625V and CORE voltage of 1.1375V to operate at + * 720MHz. + */ + if (i2c_probe(PMIC_CTRL_I2C_ADDR)) + return; + + /* VDD1/2 voltage selection register access by control i/f */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + /* Frequency switching for OPP 120 */ + if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || + voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { + printf("voltage update failed\n"); + } +} +#endif /* if def CONFIG_SPL_BUILD */ + +int read_eeprom(void) +{ + /* nothing ToDo here for this board */ + + return 0; +} + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + int n = 0; +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#ifdef CONFIG_FACTORYSET + int rv; + if (!is_valid_ether_addr(factory_dat.mac)) + printf("Error: no valid mac address\n"); + else + eth_setenv_enetaddr("ethaddr", factory_dat.mac); +#endif /* #ifdef CONFIG_FACTORYSET */ + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* AUO G156XW01 V1 */ + [0] = { + .name = "AUO_G156XW01_V1", + .width = 1376, + .height = 768, + .hfp = 14, + .hbp = 64, + .hsw = 56, + .vfp = 1, + .vbp = 28, + .vsw = 3, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* AUO B101EVN06 V0 */ + [1] = { + .name = "AUO_B101EVN06_V0", + .width = 1280, + .height = 800, + .hfp = 52, + .hbp = 84, + .hsw = 36, + .vfp = 3, + .vbp = 14, + .vsw = 6, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* + * Settings from factoryset + * stored in EEPROM + */ + [2] = { + .name = "factoryset", + .width = 0, + .height = 0, + .hfp = 0, + .hbp = 0, + .hsw = 0, + .vfp = 0, + .vbp = 0, + .vsw = 0, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, +}; + +static const struct display_panel disp_panel = { + WVGA, + 32, + 16, + COLOR_ACTIVE, +}; + +static const struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 32, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_backlight(void) +{ + set_gpio(BOARD_LCD_POWER, 1); + set_gpio(BOARD_BACK_LIGHT, 1); + set_gpio(BOARD_TOUCH_POWER, 1); + return 0; +} + +static int enable_pwm(void) +{ + struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE; + struct pwmss_ecap_regs *ecap; + int ticks = PWM_TICKS; + int duty = PWM_DUTY; + + ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE; + /* enable clock */ + setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN); + /* TimeStam Counter register */ + writel(0xdb9, &ecap->tsctr); + /* config period */ + writel(ticks - 1, &ecap->cap3); + writel(ticks - 1, &ecap->cap1); + setbits_le16(&ecap->ecctl2, + (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0)); + /* config duty */ + writel(duty, &ecap->cap2); + writel(duty, &ecap->cap4); + /* start */ + setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN); + return 0; +} + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->epwmss0clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + writel(0x0, &cmdpll->clklcdcpixelclk); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + + return 0; +} + +static int board_video_init(void) +{ + conf_disp_pll(24, 1); + if (factory_dat.pxm50) + da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp); + else + da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp); + + enable_pwm(); + enable_backlight(); + + return 0; +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int ret; + + omap_nand_switch_ecc(1, 8); + +#ifdef CONFIG_FACTORYSET + if (factory_dat.asn[0] != 0) { + char tmp[2 * MAX_STRING_LENGTH + 2]; + + if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0) + factory_dat.pxm50 = 1; + else + factory_dat.pxm50 = 0; + sprintf(tmp, "%s_%s", factory_dat.asn, + factory_dat.comp_version); + ret = setenv("boardid", tmp); + if (ret) + printf("error setting board id\n"); + } else { + factory_dat.pxm50 = 1; + ret = setenv("boardid", "PXM50_1.0"); + if (ret) + printf("error setting board id\n"); + } + debug("PXM50: %d\n", factory_dat.pxm50); +#endif + + return 0; +} +#endif + +#include "../common/board.c" diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h new file mode 100644 index 0000000000..03626129de --- /dev/null +++ b/board/siemens/pxm2/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c new file mode 100644 index 0000000000..c64b0d23d5 --- /dev/null +++ b/board/siemens/pxm2/mux.c @@ -0,0 +1,186 @@ +/* + * pinmux setup for siemens pxm2 board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */ + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */ + {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */ + {-1}, +}; +#endif + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +#ifndef CONFIG_NO_ETH +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */ + {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */ + {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; +#endif + +#ifdef CONFIG_MMC +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */ + {-1}, +}; +#endif + +static struct module_pin_mux lcdc_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */ + {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */ + {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */ + {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */ + {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */ + {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */ + {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */ + {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */ + {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */ + {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */ + {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */ + {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */ + {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */ + {-1}, +}; + +static struct module_pin_mux ecap0_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/ + {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */ + {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */ + {-1}, +}; +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#endif +#ifndef CONFIG_NO_ETH + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); +#endif +#ifdef CONFIG_MMC + configure_module_pin_mux(mmc0_pin_mux); +#endif + configure_module_pin_mux(lcdc_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(ecap0_pin_mux); +} diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h new file mode 100644 index 0000000000..c6347e5129 --- /dev/null +++ b/board/siemens/pxm2/pmic.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef PMIC_H +#define PMIC_H + +/* + * The PMIC on this board is a TPS65910. + */ + +#define PMIC_SR_I2C_ADDR 0x12 +#define PMIC_CTRL_I2C_ADDR 0x2D +/* PMIC Register offsets */ +#define PMIC_VDD1_REG 0x21 +#define PMIC_VDD1_OP_REG 0x22 +#define PMIC_VDD2_REG 0x24 +#define PMIC_VDD2_OP_REG 0x25 +#define PMIC_DEVCTRL_REG 0x3f + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define PMIC_VGAIN_SEL_MASK (0x3 << 6) +#define PMIC_ILMAX_MASK (0x1 << 5) +#define PMIC_TSTEP_MASK (0x7 << 2) +#define PMIC_ST_MASK (0x3) + +#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6) +#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6) +#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define PMIC_REG_ILMAX_1_0_A (0x0 << 5) +#define PMIC_REG_ILMAX_1_5_A (0x1 << 5) + +#define PMIC_REG_TSTEP_ (0x0 << 2) +#define PMIC_REG_TSTEP_12_5 (0x1 << 2) +#define PMIC_REG_TSTEP_9_4 (0x2 << 2) +#define PMIC_REG_TSTEP_7_5 (0x3 << 2) +#define PMIC_REG_TSTEP_6_25 (0x4 << 2) +#define PMIC_REG_TSTEP_4_7 (0x5 << 2) +#define PMIC_REG_TSTEP_3_12 (0x6 << 2) +#define PMIC_REG_TSTEP_2_5 (0x7 << 2) + +#define PMIC_REG_ST_OFF (0x0) +#define PMIC_REG_ST_ON_HI_POW (0x1) +#define PMIC_REG_ST_OFF_1 (0x2) +#define PMIC_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define PMIC_OP_REG_SEL (0x7F) + +#define PMIC_OP_REG_CMD_MASK (0x1 << 7) +#define PMIC_OP_REG_CMD_OP (0x0 << 7) +#define PMIC_OP_REG_CMD_SR (0x1 << 7) + +#define PMIC_OP_REG_SEL_MASK (0x7F) +#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +#endif diff --git a/board/siemens/rut/Kconfig b/board/siemens/rut/Kconfig new file mode 100644 index 0000000000..3371077662 --- /dev/null +++ b/board/siemens/rut/Kconfig @@ -0,0 +1,15 @@ +if TARGET_RUT + +config SYS_BOARD + default "rut" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "rut" + +endif diff --git a/board/siemens/rut/MAINTAINERS b/board/siemens/rut/MAINTAINERS new file mode 100644 index 0000000000..8c1b77059b --- /dev/null +++ b/board/siemens/rut/MAINTAINERS @@ -0,0 +1,6 @@ +RUT BOARD +M: Roger Meier +S: Maintained +F: board/siemens/rut/ +F: include/configs/rut.h +F: configs/rut_defconfig diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile new file mode 100644 index 0000000000..f15993216b --- /dev/null +++ b/board/siemens/rut/Makefile @@ -0,0 +1,21 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := mux.o +endif + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-y += ../common/factoryset.o +endif diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c new file mode 100644 index 0000000000..fb840f7ed2 --- /dev/null +++ b/board/siemens/rut/board.c @@ -0,0 +1,493 @@ +/* + * Board functions for TI AM335X based rut board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" +#include "../../../drivers/video/da8xx-fb.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs rut_ddr3_emif_reg_data = { + .sdram_config = 0x61C04AB2, + .sdram_tim1 = 0x0888A39B, + .sdram_tim2 = 0x26337FDA, + .sdram_tim3 = 0x501F830F, + .emif_ddr_phy_ctlr_1 = 0x6, + .zq_config = 0x50074BE4, + .ref_ctrl = 0x93B, +}; + +struct ddr_data rut_ddr3_data = { + .datardsratio0 = 0x3b, + .datawdsratio0 = 0x85, + .datafwsratio0 = 0x100, + .datawrsratio0 = 0xc1, +}; + +struct cmd_control rut_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x40, + .cmd0iclkout = 1, + .cmd1csratio = 0x40, + .cmd1iclkout = 1, + .cmd2csratio = 0x40, + .cmd2iclkout = 1, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = RUT_IOCTRL_VAL, + .cm1ioctl = RUT_IOCTRL_VAL, + .cm2ioctl = RUT_IOCTRL_VAL, + .dt0ioctl = RUT_IOCTRL_VAL, + .dt1ioctl = RUT_IOCTRL_VAL, +}; + + config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data, + &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); +} + +static int request_and_pulse_reset(int gpio, const char *name) +{ + int ret; + const int delay_us = 2000; /* 2ms */ + + ret = gpio_request(gpio, name); + if (ret < 0) { + printf("%s: Unable to request %s\n", __func__, name); + goto err; + } + + ret = gpio_direction_output(gpio, 0); + if (ret < 0) { + printf("%s: Unable to set %s as output\n", __func__, name); + goto err_free_gpio; + } + + udelay(delay_us); + + gpio_set_value(gpio, 1); + + return 0; + +err_free_gpio: + gpio_free(gpio); +err: + return ret; +} + +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) +#define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18) +#define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18) +#define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19) + +#define REQUEST_AND_PULSE_RESET(N) \ + request_and_pulse_reset(N, #N); + +static void spl_siemens_board_init(void) +{ + REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO); + REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO); + REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO); +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if defined(CONFIG_DRIVER_TI_CPSW) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + +#ifndef CONFIG_SPL_BUILD + factoryset_setenv(); +#endif + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_HW_WATCHDOG) +static bool hw_watchdog_init_done; +static int hw_watchdog_trigger_level; + +void hw_watchdog_reset(void) +{ + if (!hw_watchdog_init_done) + return; + + hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1; + gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); +} + +void hw_watchdog_init(void) +{ + gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger"); + gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); + + hw_watchdog_reset(); + + hw_watchdog_init_done = 1; +} +#endif /* defined(CONFIG_HW_WATCHDOG) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */ + [0] = { + .name = "KWH043MC17-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */ + [1] = { + .name = "KWH043ST20-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */ + [2] = { + .name = "MI0430VT-1", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, +}; + +static const struct display_panel disp_panels[] = { + [0] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [1] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [2] = { + WVGA, + 24, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, +}; + +static const struct lcd_ctrl_config lcd_cfgs[] = { + [0] = { + &disp_panels[0], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [1] = { + &disp_panels[1], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [2] = { + &disp_panels[2], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 24, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; +#endif + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->spi1clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + writel(0x64, &cmwkup->resv6[3]); /* 0x50 */ + writel(0x800, &cmwkup->resv6[2]); /* 0x4c */ + writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK, + &cmwkup->clkmoddplldisp); /* 0x98 */ +#endif + return 0; +} + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_lcd(void) +{ + unsigned char buf[1]; + + set_gpio(BOARD_LCD_RESET, 0); + mdelay(1); + set_gpio(BOARD_LCD_RESET, 1); + mdelay(1); + + /* spi lcd init */ + kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0); + + /* backlight on */ + buf[0] = 0xf; + i2c_write(0x24, 0x7, 1, buf, 1); + buf[0] = 0x3f; + i2c_write(0x24, 0x8, 1, buf, 1); + return 0; +} + +int arch_early_init_r(void) +{ + enable_lcd(); + return 0; +} + +static int board_video_init(void) +{ + int i; + int anzdisp = ARRAY_SIZE(lcd_panels); + int display = 1; + + for (i = 0; i < anzdisp; i++) { + if (strncmp((const char *)factory_dat.disp_name, + lcd_panels[i].name, + strlen((const char *)factory_dat.disp_name)) == 0) { + printf("DISPLAY: %s\n", factory_dat.disp_name); + break; + } + } + if (i == anzdisp) { + i = 1; + printf("%s: %s not found, using default %s\n", __func__, + factory_dat.disp_name, lcd_panels[i].name); + } + conf_disp_pll(24, 1); + da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display], + lcd_cfgs[display].bpp); + + return 0; +} +#endif /* ifdef CONFIG_VIDEO */ + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int ret; + char tmp[2 * MAX_STRING_LENGTH + 2]; + + omap_nand_switch_ecc(1, 8); + + if (factory_dat.asn[0] != 0) + sprintf(tmp, "%s_%s", factory_dat.asn, + factory_dat.comp_version); + else + sprintf(tmp, "QMX7.E38_4.0"); + + ret = setenv("boardid", tmp); + if (ret) + printf("error setting board id\n"); + + return 0; +} +#endif + +#include "../common/board.c" diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h new file mode 100644 index 0000000000..03626129de --- /dev/null +++ b/board/siemens/rut/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c new file mode 100644 index 0000000000..1eced013c7 --- /dev/null +++ b/board/siemens/rut/mux.c @@ -0,0 +1,347 @@ +/* + * pinmux setup for siemens rut board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux ddr_pin_mux[] = { + {OFFSET(ddr_resetn), (MODE(0))}, + {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ck), (MODE(0))}, + {OFFSET(ddr_nck), (MODE(0))}, + {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_odt), (MODE(0))}, + {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(gpmc_ad8), (MODE(1))}, + {OFFSET(gpmc_ad9), (MODE(1))}, + {OFFSET(gpmc_ad10), (MODE(1))}, + {OFFSET(gpmc_ad11), (MODE(1))}, + {OFFSET(gpmc_ad12), (MODE(1))}, + {OFFSET(gpmc_ad13), (MODE(1))}, + {OFFSET(gpmc_ad14), (MODE(1))}, + {OFFSET(gpmc_ad15), (MODE(1))}, + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_vsync), (MODE(0))}, + {OFFSET(lcd_hsync), (MODE(0))}, + {OFFSET(lcd_pclk), (MODE(0))}, + {OFFSET(lcd_ac_bias_en), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii_pin_mux[] = { + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mii1_col), (MODE(7) | RXACTIVE)}, + {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_fsr), (MODE(7))}, + {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)}, + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux usb1_pin_mux[] = { + {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux spi1_pin_mux[] = { + {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux jtag_pin_mux[] = { + {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, + {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux ainx_pin_mux[] = { + {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux rtc_pin_mux[] = { + {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux gpmc_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux pmic_pin_mux[] = { + {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux osc_pin_mux[] = { + {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux pwm_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(gpmc_a2), (MODE(6))}, + {OFFSET(gpmc_a3), (MODE(6))}, + {-1}, +}; + +static struct module_pin_mux emu_pin_mux[] = { + {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux vref_pin_mux[] = { + {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux misc_pin_mux[] = { + {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(ddr_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mii_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(usb1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(jtag_pin_mux); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ainx_pin_mux); + configure_module_pin_mux(rtc_pin_mux); + configure_module_pin_mux(gpmc_pin_mux); + configure_module_pin_mux(pmic_pin_mux); + configure_module_pin_mux(osc_pin_mux); + configure_module_pin_mux(pwm_pin_mux); + configure_module_pin_mux(emu_pin_mux); + configure_module_pin_mux(vref_pin_mux); + configure_module_pin_mux(misc_pin_mux); +} diff --git a/board/siemens/taurus/Kconfig b/board/siemens/taurus/Kconfig new file mode 100644 index 0000000000..c07d244bc3 --- /dev/null +++ b/board/siemens/taurus/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TAURUS + +config SYS_BOARD + default "taurus" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "taurus" + +endif diff --git a/board/siemens/taurus/MAINTAINERS b/board/siemens/taurus/MAINTAINERS new file mode 100644 index 0000000000..74e3518e0d --- /dev/null +++ b/board/siemens/taurus/MAINTAINERS @@ -0,0 +1,7 @@ +TAURUS BOARD +M: Heiko Schocher +S: Maintained +F: board/siemens/taurus/ +F: include/configs/taurus.h +F: configs/axm_defconfig +F: configs/taurus_defconfig diff --git a/board/siemens/taurus/Makefile b/board/siemens/taurus/Makefile new file mode 100644 index 0000000000..a26fb92147 --- /dev/null +++ b/board/siemens/taurus/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for Siemens TAURUS (AT91SAM9G20) based board +# (C) Copyright 2013 Siemens AG +# +# Based on: +# U-Boot file: board/atmel/at91sam9260ek/Makefile +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += taurus.o diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c new file mode 100644 index 0000000000..013dac2e2f --- /dev/null +++ b/board/siemens/taurus/taurus.c @@ -0,0 +1,246 @@ +/* + * Board functions for Siemens TAURUS (AT91SAM9G20) based boards + * (C) Copyright Siemens AG + * + * Based on: + * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void taurus_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +#if defined(CONFIG_SPL_BUILD) +#include +#include +#include + +void matrix_init(void) +{ + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + + writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) + | AT91_MATRIX_SLOT_CYCLE_(0x40), + &mat->scfg[3]); +} + +void at91_spl_board_init(void) +{ + taurus_nand_hw_init(); + at91_spi0_hw_init(TAURUS_SPI_MASK); + + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PA31, 1); + + /* check if button is pressed */ + if (at91_get_gpio_value(AT91_PIN_PA31) == 0) { + struct spi_flash *flash; + + debug("Recovery button pressed\n"); + nand_init(); + spl_nand_erase_one(0, 0); + flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + 0, + CONFIG_SF_DEFAULT_SPEED, + SPI_MODE_3); + if (!flash) { + puts("no flash\n"); + } else { + puts("erase spi flash sector 0\n"); + spi_flash_erase(flash, 0, + CONFIG_SYS_NAND_U_BOOT_SIZE); + } + } +} + +void mem_init(void) +{ + struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct sdramc_reg setting; + + at91_sdram_hw_init(); + setting.cr = (AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_CAS_3 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_DBW_32 | + AT91_SDRAMC_TWR_VAL(3) | + AT91_SDRAMC_TRC_VAL(9) | + AT91_SDRAMC_TRP_VAL(3) | + AT91_SDRAMC_TRCD_VAL(3) | + AT91_SDRAMC_TRAS_VAL(6) | + AT91_SDRAMC_TXSR_VAL(10)); + setting.mdr = AT91_SDRAMC_MD_SDRAM; + setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + + + writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | + AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, + &ma->ebicsa); + sdramc_initialize(ATMEL_BASE_CS1, &setting); +} +#endif + +#ifdef CONFIG_MACB +static void taurus_macb_hw_init(void) +{ + /* Enable EMAC clock */ + at91_periph_clk_enable(ATMEL_ID_EMAC0); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0); + + at91_phy_reset(); + + at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */ + + /* Re-enable pull-up */ + at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1); + + /* Initialize EMAC=MACB hardware */ + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI); +} +#endif + +int board_early_init_f(void) +{ + /* Enable clocks for all PIOs */ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + + at91_seriald_hw_init(); + + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + taurus_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + taurus_macb_hw_init(); +#endif + at91_spi0_hw_init(TAURUS_SPI_MASK); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); +#endif + return rc; +} diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig new file mode 100644 index 0000000000..f2e1098f62 --- /dev/null +++ b/board/silica/pengwyn/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PENGWYN + +config SYS_BOARD + default "pengwyn" + +config SYS_VENDOR + default "silica" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "pengwyn" + +endif diff --git a/board/silica/pengwyn/MAINTAINERS b/board/silica/pengwyn/MAINTAINERS new file mode 100644 index 0000000000..14ef7750c5 --- /dev/null +++ b/board/silica/pengwyn/MAINTAINERS @@ -0,0 +1,6 @@ +PENGWYN BOARD +M: Lothar Felten +S: Maintained +F: board/silica/pengwyn/ +F: include/configs/pengwyn.h +F: configs/pengwyn_defconfig diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile new file mode 100644 index 0000000000..804ac379db --- /dev/null +++ b/board/silica/pengwyn/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c new file mode 100644 index 0000000000..ee88b6f399 --- /dev/null +++ b/board/silica/pengwyn/board.c @@ -0,0 +1,207 @@ +/* + * board.c + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#if defined(CONFIG_SPL_BUILD) + +/* DDR3 RAM timings */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K128MJT187E_RD_DQS, + .datawdsratio0 = MT41K128MJT187E_WR_DQS, + .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE, + .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K128MJT187E_RATIO, + .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd1csratio = MT41K128MJT187E_RATIO, + .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd2csratio = MT41K128MJT187E_RATIO, + .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K128MJT187E_EMIF_SDCFG, + .ref_ctrl = MT41K128MJT187E_EMIF_SDREF, + .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1, + .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2, + .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3, + .zq_config = MT41K128MJT187E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr_266 = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_303 = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_400 = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + /* + * The pengwyn board uses the TPS650250 PMIC without I2C + * interface and will output the following fixed voltages: + * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu) + * VLDO1=1V8 (IO) VLDO2=1V8(IO) + * Vcore=1V1 is fixed, generated by TPS62231 + */ + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* 720MHz cpu, this might change on newer board revisions */ + dpll_mpu_opp100.m = MPUPLL_M_720; + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + /* future configs can return other clock settings */ + return &dpll_ddr_303; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + config_ddr(303, &ddr3_ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#endif /* if CONFIG_SPL_BUILD */ + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + printf(" not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + return n; + } + + writel(MII_MODE_ENABLE, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* if CONFIG_DRIVER_TI_CPSW */ diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h new file mode 100644 index 0000000000..05addf6bb2 --- /dev/null +++ b/board/silica/pengwyn/board.h @@ -0,0 +1,15 @@ +/* + * board.h + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); + +#endif diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c new file mode 100644 index 0000000000..c8be440a20 --- /dev/null +++ b/board/silica/pengwyn/mux.c @@ -0,0 +1,98 @@ +/* + * mux.c + * + * Copyright (C) 2013 Lothar Felten + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "board.h" + +/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */ +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */ + +/* I2C pins C16(scl)/C17(sda) */ +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */ + {-1}, +}; + +/* MMC0 pins */ +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +/* MII pins */ +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +/* NAND pins */ +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux() +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(nand_pin_mux); +} diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/sixnet/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c deleted file mode 100644 index 75bc3eb3d3..0000000000 --- a/board/sixnet/flash.c +++ /dev/null @@ -1,774 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -/* environment.h defines the various CONFIG_ENV_... values in terms - * of whichever ones are given in the configuration file. - */ -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t *info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b; - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b); - } - - /* Remap FLASH according to real size, so only at proper address */ - memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b); - - /* Do this again (was done already in flast_get_size), just - * in case we move it when remap the FLASH. - */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#ifdef CONFIG_SYS_FLASH_PROTECTION - /* read the hardware protection status (if any) into the - * protection array in flash_info. - */ - flash_sync_real_protect(&flash_info[0]); -#endif - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (top boot sector type) */ - for (i = 0; i < info->sector_count - 3; i++) - info->start[i] = base + (i * sect_size); - i = info->sector_count - 1; - info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2); - info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2); - info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - fmt = "29LV800B%s (8 Mbit, %s)\n"; - break; - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { - - case (FPW)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MiB */ - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect(flash_info_t *info) -{ - FPWV *addr = (FPWV *)(info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW)0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *)(info->start[i]); - info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - case FLASH_AM800T: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00800080; /* erase mode */ - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c deleted file mode 100644 index 2d3a7b3358..0000000000 --- a/board/sixnet/fpgadata.c +++ /dev/null @@ -1,1719 +0,0 @@ - 0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff, - 0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9, - 0xff, 0xef, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf0, - 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xcf, - 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, - 0x7f, 0x7b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x77, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x86, 0xf6, 0xf0, 0xff, - 0xf0, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x7f, - 0xc1, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xf8, 0xff, 0xff, 0xf6, 0xf0, 0xff, 0xff, - 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x0f, 0x7f, 0xff, - 0xff, 0xff, 0xff, 0x8f, 0x7f, - 0xff, 0xf8, 0xf7, 0x8f, 0xcf, 0xf0, 0xf6, 0xff, - 0xff, 0xef, 0xff, 0xfb, 0x7f, 0x2f, 0x1f, 0x71, - 0xf5, 0xff, 0xff, 0xef, 0x7f, - 0xff, 0x7f, 0xff, 0xf7, 0xf6, 0xfe, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xf7, 0x7f, 0x77, 0xf7, 0xff, 0xfb, - 0x0f, 0xff, 0xf0, 0xff, 0xff, 0x7f, 0xff, 0xff, - 0xfe, 0xff, 0x8f, 0x7f, 0xf1, - 0xff, 0xff, 0xfa, 0xce, 0xff, 0xfd, 0xff, 0xff, - 0x9f, 0xff, 0x8e, 0xff, 0xf0, 0xbf, 0x7f, 0xf5, - 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0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x8f, 0x3f, - 0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff, - 0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f, - 0xf1, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xbf, 0xbf, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff, - 0xdf, 0xff, 0x7f, 0xff, 0xbf, - 0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff, - 0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1, - 0xff, 0xef, 0xff, 0x7f, 0xff, diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c deleted file mode 100644 index 06b2083558..0000000000 --- a/board/sixnet/sixnet.c +++ /dev/null @@ -1,578 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Dave Ellis, SIXNET, dge@sixnetio.com. - * Based on code by: - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * and other contributors to U-Boot. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include /* for eth_init() */ -#include -#include "sixnet.h" -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -static long ram_size(ulong *, long); - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int status) -{ -#if defined(CONFIG_STATUS_LED) -# if defined(STATUS_LED_BOOT) - if (status == BOOTSTAGE_ID_RUN_OS) { - /* ready to transfer to kernel, make sure LED is proper state */ - status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE); - } -# endif /* STATUS_LED_BOOT */ -#endif /* CONFIG_STATUS_LED */ -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * returns 0 if recognized, -1 if unknown - */ - -int checkboard (void) -{ - puts ("Board: SIXNET SXNI855T\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_PCMCIA) -#error "SXNI855T has no PCMCIA port" -#endif - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -/* UPMB table for dual UART. */ - -/* this table is for 50MHz operation, it should work at all lower speeds */ -const uint duart_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04, - 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05, - - /* burst read. (offset 8 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04, - 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05, - - /* burst write. (offset 20 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, -}; - -/* Load FPGA very early in boot sequence, since it must be - * loaded before the 16C2550 serial channels can be used as - * console channels. - * - * Note: Much of the configuration is not complete. The - * stack is in DPRAM since SDRAM has not been initialized, - * so the stack must be kept small. Global variables - * are still in FLASH, so they cannot be written. - * Only the FLASH, DPRAM, immap and FPGA can be addressed, - * the other chip selects may not have been initialized. - * The clocks have been initialized, so udelay() can be - * used. - */ -#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */ -#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */ -#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */ -#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */ - -int board_postclk_init (void) -{ - - /* the data to load to the XCSxxXL FPGA */ - static const unsigned char fpgadata[] = { -# include "fpgadata.c" - }; - - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; -#define porta (immap->im_ioport.iop_padat) - const unsigned char* pdata; - - /* /INITFPGA and DONEFPGA signals are inputs */ - immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE); - - /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */ - porta &= ~FPGA_PROGRAM_L; - - /* Set FPGA as an output */ - immap->im_ioport.iop_padir |= FPGA_PROGRAM_L; - - /* delay a little to make sure FPGA sees it, really - * only need less than a microsecond. - */ - udelay(10); - - /* unassert /PROGRAM */ - porta |= FPGA_PROGRAM_L; - - /* delay while FPGA does last erase, indicated by - * /INITFPGA going high. This should happen within a - * few milliseconds. - */ - /* ### FIXME - a timeout check would be good, maybe flash - * the status LED to indicate the error? - */ - while ((porta & FPGA_INIT_L) == 0) - ; /* waiting */ - - /* write program data to FPGA at the programming address - * so extra /CS1 strobes at end of configuration don't actually - * write to any registers. - */ - fpga = 0xff; /* first write is ignored */ - fpga = 0xff; /* fill byte */ - fpga = 0xff; /* fill byte */ - fpga = 0x4f; /* preamble code */ - fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */ - fpga = 0x4b; /* field check code */ - - pdata = fpgadata; - /* while no error write out each of the 28 byte frames */ - while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L - && pdata < fpgadata + sizeof(fpgadata)) { - - fpga = 0x4f; /* preamble code */ - - /* 21 bytes of data in a frame */ - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); - - fpga = 0x4b; /* field check code */ - fpga = 0xff; /* extended write cycle */ - fpga = 0x4b; /* extended write cycle - * (actually 0x4b from bitgen.exe) - */ - fpga = 0xff; /* extended write cycle */ - fpga = 0xff; /* extended write cycle */ - fpga = 0xff; /* extended write cycle */ - } - - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - -#if 0 /* ### FIXME */ - /* If didn't load all the data or FPGA_DONE is low the load failed. - * Maybe someday stop here and flash the status LED? The console - * is not configured, so can't print an error message. Can't write - * global variables to set a flag (except gd?). - * For now it must work. - */ -#endif - - /* Now that the FPGA is loaded, set up the Dual UART chip - * selects. Must be done here since it may be used as the console. - */ - upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint)); - - memctl->memc_mbmr = DUART_MBMR; - memctl->memc_or5 = DUART_OR_VALUE; - memctl->memc_br5 = DUART_BR5_VALUE; - memctl->memc_or6 = DUART_OR_VALUE; - memctl->memc_br6 = DUART_BR6_VALUE; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* base address for SRAM, assume 32-bit port, valid */ -#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V) - -/* up to 64MB - will be adjusted for actual size */ -#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \ - | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) -/* - * Miscellaneous platform dependent initializations after running in RAM. - */ - -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - bd_t *bd = gd->bd; - uchar enetaddr[6]; - - memctl->memc_or2 = NVRAM_OR_PRELIM; - memctl->memc_br2 = NVRAM_BR_VALUE; - - /* Is there any SRAM? Is it 16 or 32 bits wide? */ - - /* First look for 32-bit SRAM */ - bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE); - - if (bd->bi_sramsize == 0) { - /* no 32-bit SRAM, but there could be 16-bit SRAM since - * it would report size 0 when configured for 32-bit bus. - * Try again with a 16-bit bus. - */ - memctl->memc_br2 |= BR_PS_16; - bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE); - } - - if (bd->bi_sramsize == 0) { - memctl->memc_br2 = 0; /* disable select since nothing there */ - } - else { - /* adjust or2 for actual size of SRAM */ - memctl->memc_or2 |= ORMASK(bd->bi_sramsize); - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10); - } - - - /* set standard MPC8xx clock so kernel will see the time - * even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - struct rtc_time tmp; - - rtc_get(&tmp); /* get time from DS1306 RTC */ - - /* convert to seconds since 1970 */ - tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday, - tmp.tm_hour, tmp.tm_min, tmp.tm_sec); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - /* set up ethernet address for SCC ethernet. If eth1addr - * is present it gets a unique address, otherwise it - * shares the FEC address. - */ - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - eth_getenv_enetaddr("ethaddr", enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } - - return (0); -} - -#if defined(CONFIG_CMD_NAND) -void nand_init(void) -{ - unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - * - * The memory size MUST be a power of 2 for this to work. - * - * The only memory modified is 8 bytes at offset 0. This is important - * since for the SRAM this location is reserved for autosizing, so if - * it is modified and the board is reset before ram_size() completes - * no damage is done. Normally even the memory at 0 is preserved. The - * higher SRAM addresses may contain battery backed RAM disk data which - * must never be corrupted. - */ - -static long ram_size(ulong *base, long maxsize) -{ - volatile long *test_addr; - volatile ulong *base_addr = base; - ulong ofs; /* byte offset from base_addr */ - ulong save; /* to make test non-destructive */ - ulong save2; /* to make test non-destructive */ - long ramsize = -1; /* size not determined yet */ - - save = *base_addr; /* save value at 0 so can restore */ - save2 = *(base_addr+1); /* save value at 4 so can restore */ - - /* is any SRAM present? */ - *base_addr = 0x5555aaaa; - - /* It is important to drive the data bus with different data so - * it doesn't remember the value and look like RAM that isn't there. - */ - *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */ - - if (*base_addr != 0x5555aaaa) - ramsize = 0; /* no RAM present, or defective */ - else { - *base_addr = 0xaaaa5555; - *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */ - if (*base_addr != 0xaaaa5555) - ramsize = 0; /* no RAM present, or defective */ - } - - /* now size it if any is present */ - for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) { - test_addr = (long*)((long)base_addr + ofs); /* location to test */ - - *base_addr = ~*test_addr; - if (*base_addr == *test_addr) - ramsize = ofs; /* wrapped back to 0, so this is the size */ - } - - *base_addr = save; /* restore value at 0 */ - *(base_addr+1) = save2; /* restore value at 4 */ - return (ramsize); -} - -/* ------------------------------------------------------------------------- */ -/* sdram table based on the FADS manual */ -/* for chip MB811171622A-100 */ - -/* this table is for 50MHz operation, it should work at all lower speeds */ - -const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* precharge and Mode Register Set initialization (offset 5). - * This is also entered at offset 6 to do Mode Register Set - * without the precharge. - */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - /* FADS had 0x1f27fc04, ... - * but most other boards have 0x1f07fc04, which - * sets GPL0 from A11MPC to 0 1/4 clock earlier, - * like the single read. - * This seems better so I am going with the change. - */ - 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; - -/* ------------------------------------------------------------------------- */ - -#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */ - -/* precharge and set Mode Register */ -#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */ - -/* set Mode Register, no precharge */ -#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */ - -/* runs refresh loop twice so get 8 refresh cycles */ -#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */ - -/* MAMR values work in either mamr or mbmr */ -#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \ - ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \ - | MAMR_DSA_1_CYCL /* 1 cycle disable */ \ - | MAMR_RLFA_1X /* Read loop 1 time */ \ - | MAMR_WLFA_1X /* Write loop 1 time */ \ - | MAMR_TLFA_4X) /* Timer loop 4 times */ -/* 8 column SDRAM */ -#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \ - | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \ - | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */ - -/* 9 column SDRAM */ -#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \ - | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \ - | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */ - -/* base address 0, 32-bit port, SDRAM UPM, valid */ -#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V) - -/* up to 256MB, SAM, G5LS - will be adjusted for actual size */ -#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS) - -/* This is the Mode Select Register value for the SDRAM. - * Burst length: 4 - * Burst Type: sequential - * CAS Latency: 2 - * Write Burst Length: burst - */ -#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */ - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - uint size_sdram = 0; - uint size_sdram9 = 0; - uint base = 0; /* SDRAM must start at 0 */ - int i; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Configure the refresh (mostly). This needs to be - * based upon processor clock speed and optimized to provide - * the highest level of performance. - * - * Preliminary prescaler for refresh. - * This value is selected for four cycles in 31.2 us, - * which gives 8192 cycles in 64 milliseconds. - * This may be too fast, but works for any memory. - * It is adjusted to 4096 cycles in 64 milliseconds if - * possible once we know what memory we have. - * - * We have to be careful changing UPM registers after we - * ask it to run these commands. - * - * PTA - periodic timer period for our design is - * 50 MHz x 31.2us - * --------------- = 195 - * 1 x 8 x 1 - * - * 50MHz clock - * 31.2us refresh interval - * SCCR[DFBRG] 0 - * PTP divide by 8 - * 1 chip select - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */ - memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */ - - /* The SDRAM Mode Register value is shifted left 2 bits since - * A30 and A31 don't connect to the SDRAM for 32-bit wide memory. - */ - memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */ - udelay(200); /* SDRAM needs 200uS before set it up */ - - /* Now run the precharge/nop/mrs commands. */ - memctl->memc_mcr = SDRAM_MCR_PRE; - udelay(2); - - /* Run 8 refresh cycles (2 sets of 4) */ - memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */ - udelay(2); - - /* some brands want Mode Register set after the refresh - * cycles. This shouldn't hurt anything for the brands - * that were happy with the first time we set it. - */ - memctl->memc_mcr = SDRAM_MCR_MRS; - udelay(2); - - memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */ - memctl->memc_or3 = SDRAM_OR_PRELIM; - memctl->memc_br3 = SDRAM_BR_VALUE + base; - - /* Some brands need at least 10 DRAM accesses to stabilize. - * It wont hurt the brands that don't. - */ - for (i=0; i<10; ++i) { - volatile ulong *addr = (volatile ulong *)base; - ulong val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* Check SDRAM memory Size in 8 column mode. - * For a 9 column memory we will get half the actual size. - */ - size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE); - - /* Check SDRAM memory Size in 9 column mode. - * For an 8 column memory we will see at most 4 megabytes. - */ - memctl->memc_mamr = SDRAM_MAMR_9COL; - size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE); - - if (size_sdram < size_sdram9) /* leave configuration at 9 columns */ - size_sdram = size_sdram9; - else /* go back to 8 columns */ - memctl->memc_mamr = SDRAM_MAMR_8COL; - - /* adjust or3 for actual size of SDRAM - */ - memctl->memc_or3 |= ORMASK(size_sdram); - - /* Adjust refresh rate depending on SDRAM type. - * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave - * it at the current (fast) rate. - * For 16, 64 and 128 MBit half the rate will do. - */ - if (size_sdram <= 32 * 1024 * 1024) - memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */ - - return (size_sdram); -} diff --git a/board/sixnet/sixnet.h b/board/sixnet/sixnet.h deleted file mode 100644 index 046c9de39e..0000000000 --- a/board/sixnet/sixnet.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds deleted file mode 100644 index 7ee2012c41..0000000000 --- a/board/sixnet/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/snmc/qs850/Makefile b/board/snmc/qs850/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/snmc/qs850/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c deleted file mode 100644 index 2fc23f2f1d..0000000000 --- a/board/snmc/qs850/flash.c +++ /dev/null @@ -1,600 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF - -/*----------------------------------------------------------------------- - * Functions - */ -/* stolen from esteem192e/flash.c */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); - -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - volatile FLASH_WORD_SIZE* flash_base; - - /* Init: no FLASHes known */ - for (i=0; isize / (info->sector_count - 8 + 1); - small_sect_size = large_sect_size / 8; - - if (info->flash_id & FLASH_BTYPE) { - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 7; i++) { - info->start[i] = base; - base += small_sect_size; - } - - for (; i < info->sector_count; i++) { - info->start[i] = base; - base += large_sect_size; - } - } - else - { - /* set sector offsets for top boot block type */ - for (i = 0; i < (info->sector_count - 8); i++) { - info->start[i] = base; - base += large_sect_size; - } - - for (; i < info->sector_count; i++) { - info->start[i] = base; - base += small_sect_size; - } - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar botboot[]=", bottom boot sect)\n"; - uchar topboot[]=", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - if (info->flash_id & 0x0001 ) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit%s",boottype); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit%s",boottype); - break; - case FLASH_AMDL163T: - printf ("AM29DL163T (16 Mbit%s",boottype); - break; - case FLASH_AMDL163B: - printf ("AM29DL163B (16 Mbit%s",boottype); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit%s",boottype); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit%s",boottype); - break; - case FLASH_AMDL323T: - printf ("AM29DL323T (32 Mbit%s",boottype); - break; - case FLASH_AMDL323B: - printf ("AM29DL323B (32 Mbit%s",boottype); - break; - case FLASH_AMDL322T: - printf ("AM29DL322T (32 Mbit%s",boottype); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if(addr[0x0000] != 0x00890089){ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL163T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL163T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL163B & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL163B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL323T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_DL323B & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_DL322T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - default: - /* FIXME*/ - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP) ) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); - while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != - (0x00800080&FLASH_ID_MASK) ) - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - return (0); -} diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c deleted file mode 100644 index dc4a4768cd..0000000000 --- a/board/snmc/qs850/qs850.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation, dnevil@snmc.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04, - 0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00, - 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00, - 0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04, - 0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04, - 0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37 -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (QS850, QS823, ...) - * - * Always return 1 - */ -#if defined(CONFIG_QS850) -#define BOARD_IDENTITY "QS850" -#elif defined(CONFIG_QS823) -#define BOARD_IDENTITY "QS823" -#else -#define BOARD_IDENTITY "QS???" -#endif - -int checkboard (void) -{ - char *s, *e; - char buf[64]; - int i; - - i = getenv_f("serial#", buf, sizeof(buf)); - s = (i>0) ? buf : NULL; - - if (!s || strncmp(s, BOARD_IDENTITY, 5)) { - puts ("### No HW ID - assuming " BOARD_IDENTITY); - } else { - for (e=s; *e; ++e) { - if (*e == ' ') - break; - } - - for ( ; sim_memctl; - long int size; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Prescaler for refresh - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* - * Map controller bank 1 to the SDRAM address - */ - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; - udelay(1000); - - /* perform SDRAM initialization sequence */ - memctl->memc_mamr = CONFIG_SYS_16M_MAMR; - udelay(100); - - /* Program the SDRAM's Mode Register */ - memctl->memc_mar = SDRAM_MODE_REG; - - /* Run the Prechard Pattern at 0x3C */ - memctl->memc_mcr = UPMA_RUN(1,0x3c); - udelay(1); - - /* Run the Refresh program residing at MAD index 0x30 */ - /* This contains the CBR Refresh command with a loop */ - /* The SDRAM must be refreshed at least 2 times */ - /* Please note a value of zero = 16 loops */ - memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30); - udelay(1); - - /* Run the Exception program residing at MAD index 0x3E */ - /* This contains the Write Mode Register command */ - /* The Write Mode Register command uses the value written to MAR */ - memctl->memc_mcr = UPMA_RUN(1,0x3e); - - udelay (1000); - - /* - * Check for 32M SDRAM Memory Size - */ - size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE, - (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE); - udelay (1000); - - /* - * Check for 16M SDRAM Memory Size - */ - if (size != SDRAM_32M_MAX_SIZE) { - size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE, - (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); - udelay (1000); - } - - udelay(10000); - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds deleted file mode 100644 index 667dc54e17..0000000000 --- a/board/snmc/qs850/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/snmc/qs860t/Makefile b/board/snmc/qs860t/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/snmc/qs860t/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c deleted file mode 100644 index c24d9792de..0000000000 --- a/board/snmc/qs860t/flash.c +++ /dev/null @@ -1,1099 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#ifdef CONFIG_SYS_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xFFFF -#else -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -/* stolen from esteem192e/flash.c */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); - -#ifndef CONFIG_SYS_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data); -#else -static int write_short (flash_info_t *info, ulong dest, ushort data); -#endif -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i=0; iflash_id & FLASH_TYPEMASK) == INTEL_ID_28F320J3A || - (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F640J3A || - (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F128J3A) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * info->size/info->sector_count); - } - } - else if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_SYS_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x000E0000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00070000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_SYS_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } else { - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar botboot[]=", bottom boot sect)\n"; - uchar topboot[]=", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - if (info->flash_id & 0x0001 ) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); - break; - case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); - break; - case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); - break; - case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); - break; - case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); - break; - case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); - break; - case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit%s",boottype); - break; - -#if 0 /* enable when devices are available */ - - case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); - break; - case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); - break; -#endif - case INTEL_ID_28F320J3A: printf ("INTEL28F320JA3 (32 Mbit%s",boottype); - break; - case INTEL_ID_28F640J3A: printf ("INTEL28F640JA3 (64 Mbit%s",boottype); - break; - case INTEL_ID_28F128J3A: printf ("INTEL28F128JA3 (128 Mbit%s",boottype); - break; - - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - -#ifndef CONFIG_SYS_FLASH_16BIT - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if(addr[0x0000] != 0x00890089){ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x0089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x0090; - - if(addr[0x0000] != 0x0089){ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0090; -#endif - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - - } - - value = addr[1]; /* device ID */ - - switch (value) { - - case (AMD_ID_LV400T & FLASH_ID_MASK): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & FLASH_ID_MASK): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & FLASH_ID_MASK): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & FLASH_ID_MASK): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & FLASH_ID_MASK): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case (AMD_ID_DL322T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F800B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800T; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F800B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F160B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 /* enable when devices are available */ - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ -#endif - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 32 MBit */ - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 64 MBit */ - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 128 MBit */ - - default: - /* FIXME*/ - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - - volatile FLASH_WORD_SIZE *addr = - (volatile FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect, barf; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - ((info->flash_id > FLASH_AMD_COMP) && - ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - if (info->flash_id < FLASH_AMD_COMP) { -#ifndef CONFIG_SYS_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; -#endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); - while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != - (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; -#ifndef CONFIG_SYS_FLASH_16BIT - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while (!(addr[0] & 0x00800080)); /* wait for error or finish */ - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } - } -#else - addr = (vu_short *) (info->start[sect]); - addr[0] = 0x0020; - addr[0] = 0x00D0; - while (!(addr[0] & 0x0080)); /* wait for error or finish */ - if (addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if (barf) { - printf ("\nFlash error in sector at %lx\n", - (unsigned long) addr); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if ((barf & 0x0030) == 0x0030) - printf ("Command Sequence error.\n"); - if ((barf & 0x0030) == 0x0020) - printf ("Block Erase error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - rcode = 1; - } else - printf ("."); - l_sect = sect; - } - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - - } - - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ - -/*flash_info_t *addr2info (ulong addr) -{ - flash_info_t *info; - int i; - - for (i=0, info=&flash_info[0]; i= info->start[0]) && - (addr < (info->start[0] + info->size)) ) { - return (info); - } - } - - return (NULL); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash. - * Make sure all target addresses are within Flash bounds, - * and no protected sectors are hit. - * Returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - target range includes protected sectors - * 8 - target address not in Flash memory - */ - -/*int flash_write (uchar *src, ulong addr, ulong cnt) -{ - int i; - ulong end = addr + cnt - 1; - flash_info_t *info_first = addr2info (addr); - flash_info_t *info_last = addr2info (end ); - flash_info_t *info; - - if (cnt == 0) { - return (0); - } - - if (!info_first || !info_last) { - return (8); - } - - for (info = info_first; info <= info_last; ++info) { - ulong b_end = info->start[0] + info->size;*/ /* bank end addr */ -/* short s_end = info->sector_count - 1; - for (i=0; isector_count; ++i) { - ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; - - if ((end >= info->start[i]) && (addr < e_addr) && - (info->protect[i] != 0) ) { - return (4); - } - } - } - -*/ /* finally write data to flash */ -/* for (info = info_first; info <= info_last && cnt>0; ++info) { - ulong len; - - len = info->start[0] + info->size - addr; - if (len > cnt) - len = cnt; - if ((i = write_buff(info, src, addr, len)) != 0) { - return (i); - } - cnt -= len; - addr += len; - src += len; - } - return (0); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#ifndef CONFIG_SYS_FLASH_16BIT - ulong cp, wp, data; - int l; -#else - ulong cp, wp; - ushort data; -#endif - int i, rc; - -#ifndef CONFIG_SYS_FLASH_16BIT - - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); - -#else - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ -/* l = 0; used for debuging */ - while (cnt >= 2) { - data = 0; - for (i=0; i<2; ++i) { - data = (data << 8) | *src++; - } - -/* if(!l){ - printf("%x",data); - l = 1; - } used for debuging */ - - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_short(info, wp, data)); - - -#endif -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifndef CONFIG_SYS_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start,barf; - int flag; - - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id > FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id > FLASH_AMD_COMP) { - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } else { - while(!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - - if( addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if( barf ) { - barf >>=16; - } else { - barf = addr[0] & 0x0000003A; - } - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - } - - return (0); -} - -#else - -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start,barf; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - /* intel stuff */ - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); - } - - if( addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - *addr = 0x00B0; - *addr = 0x0070; - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); - } - *addr = 0x00FF; - } - return (0); -} - -#endif - -/*-----------------------------------------------------------------------*/ diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c deleted file mode 100644 index 7ff99459b7..0000000000 --- a/board/snmc/qs860t/qs860t.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation, dnevil@snmc.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04 -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (QS860T...) - * - * Always return 1 - */ - -int checkboard (void) -{ - char *s, *e; - char buf[64]; - int i; - - i = getenv_f("serial#", buf, sizeof(buf)); - s = (i>0) ? buf : NULL; - - if (!s || strncmp(s, "QS860T", 6)) { - puts ("### No HW ID - assuming QS860T"); - } else { - for (e=s; *e; ++e) { - if (*e == ' ') - break; - } - - for ( ; sim_memctl; - long int size; - - upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Prescaler for refresh - */ - memctl->memc_mptpr = 0x0400; - - /* - * Map controller bank 2 to the SDRAM address - */ - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - udelay(200); - - /* perform SDRAM initialization sequence */ - memctl->memc_mbmr = CONFIG_SYS_16M_MBMR; - udelay(100); - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = 0x80804105; /* run precharge pattern */ - udelay(1); - - /* Run two refresh cycles on SDRAM */ - memctl->memc_mbmr = 0x18802118; - memctl->memc_mcr = 0x80804130; - memctl->memc_mbmr = 0x18802114; - memctl->memc_mcr = 0x80804106; - - udelay (1000); - -#if 0 - /* - * Check for 64M SDRAM Memory Size - */ - size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE); - udelay (1000); - - /* - * Check for 16M SDRAM Memory Size - */ - if (size != SDRAM_64M_MAX_SIZE) { -#endif - size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); - udelay (1000); -#if 0 - } - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; -#endif - - - udelay(10000); - - -#if 0 - - /* - * Also, map other memory to correct position - */ - - /* - * Map the 8M Intel Flash device to chip select 1 - */ - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; - - - /* - * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg - * to chip select 3 - */ - memctl->memc_or3 = CONFIG_SYS_OR3; - memctl->memc_br3 = CONFIG_SYS_BR3; - - /* - * Map chip selects 4, 5, 6, & 7 for external expansion connector - */ - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - - memctl->memc_or5 = CONFIG_SYS_OR5; - memctl->memc_br5 = CONFIG_SYS_BR5; - - memctl->memc_or6 = CONFIG_SYS_OR6; - memctl->memc_br6 = CONFIG_SYS_BR6; - - memctl->memc_or7 = CONFIG_SYS_OR7; - memctl->memc_br7 = CONFIG_SYS_BR7; - -#endif - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mbmr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mbmr = mbmr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/snmc/qs860t/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/socrates/Kconfig b/board/socrates/Kconfig new file mode 100644 index 0000000000..ca945c278d --- /dev/null +++ b/board/socrates/Kconfig @@ -0,0 +1,9 @@ +if TARGET_SOCRATES + +config SYS_BOARD + default "socrates" + +config SYS_CONFIG_NAME + default "socrates" + +endif diff --git a/board/socrates/MAINTAINERS b/board/socrates/MAINTAINERS new file mode 100644 index 0000000000..293b8e6d01 --- /dev/null +++ b/board/socrates/MAINTAINERS @@ -0,0 +1,6 @@ +SOCRATES BOARD +#M: - +S: Maintained +F: board/socrates/ +F: include/configs/socrates.h +F: configs/socrates_defconfig diff --git a/board/socrates/Makefile b/board/socrates/Makefile index c2e282b952..79bda718d5 100644 --- a/board/socrates/Makefile +++ b/board/socrates/Makefile @@ -7,30 +7,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o -# - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-y += nand.o -COBJS-y += sdram.o -COBJS-$(CONFIG_FSL_DDR2) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += socrates.o +obj-y += law.o +obj-y += tlb.o +obj-y += nand.o +obj-y += sdram.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index e9db476f48..6bad4da394 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 3802c7ec7a..73944780bf 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -18,7 +18,9 @@ static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); static u_char sc_nand_read_byte(struct mtd_info *mtd); static u16 sc_nand_read_word(struct mtd_info *mtd); static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); +#endif static int sc_nand_device_ready(struct mtd_info *mtdinfo); #define FPGA_NAND_CMD_MASK (0x7 << 28) @@ -100,6 +102,7 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) /** * sc_nand_verify_buf - Verify chip data against buffer * @mtd: MTD device structure @@ -116,6 +119,7 @@ static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) } return 0; } +#endif /** * sc_nand_device_ready - Check the NAND device is ready for next command. @@ -174,7 +178,9 @@ int board_nand_init(struct nand_chip *nand) nand->read_word = sc_nand_read_word; nand->write_buf = sc_nand_write_buf; nand->read_buf = sc_nand_read_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) nand->verify_buf = sc_nand_verify_buf; +#endif return 0; } diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 313efae90f..aebd02f76c 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include @@ -24,7 +24,8 @@ */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); /* * Disable memory controller. diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 97fd0e4bd1..953a43ff31 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -143,7 +143,7 @@ void local_bus_init (void) get_sys_info (&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv; /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ if (lbc_mhz >= 66) @@ -218,8 +218,7 @@ int board_early_init_r (void) #endif /* CONFIG_BOARD_EARLY_INIT_R */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { u32 val[12]; int rc, i = 0; @@ -251,6 +250,8 @@ ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update localbus ranges, err=%s\n", fdt_strerror(rc)); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/solidrun/hummingboard/Kconfig b/board/solidrun/hummingboard/Kconfig new file mode 100644 index 0000000000..36b79045bc --- /dev/null +++ b/board/solidrun/hummingboard/Kconfig @@ -0,0 +1,15 @@ +if TARGET_HUMMINGBOARD + +config SYS_BOARD + default "hummingboard" + +config SYS_VENDOR + default "solidrun" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "hummingboard" + +endif diff --git a/board/solidrun/hummingboard/MAINTAINERS b/board/solidrun/hummingboard/MAINTAINERS new file mode 100644 index 0000000000..c0c062a8bd --- /dev/null +++ b/board/solidrun/hummingboard/MAINTAINERS @@ -0,0 +1,6 @@ +HUMMINGBOARD BOARD +M: Jon Nettleton +S: Maintained +F: board/solidrun/hummingboard/ +F: include/configs/hummingboard.h +F: configs/hummingboard_solo_defconfig diff --git a/board/solidrun/hummingboard/Makefile b/board/solidrun/hummingboard/Makefile new file mode 100644 index 0000000000..042a2f0766 --- /dev/null +++ b/board/solidrun/hummingboard/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices +# Copyright (C) 2013, Jon Nettleton +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := hummingboard.o diff --git a/board/solidrun/hummingboard/README b/board/solidrun/hummingboard/README new file mode 100644 index 0000000000..cfd62d40be --- /dev/null +++ b/board/solidrun/hummingboard/README @@ -0,0 +1,40 @@ +U-Boot for SolidRun Hummingboard +-------------------------------- + +This file contains information for the port of U-Boot to the Hummingboard. + +For more details about Hummingboard, please refer to: +http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware + +(Carrier-One was the previous name of Hummingboard). + +Building U-boot for Hummingboard +-------------------------------- + +To build U-Boot for the Hummingboard Solo version: + +$ make hummingboard_solo_config +$ make + +Flashing U-boot into the SD card +-------------------------------- + +- After the 'make' command completes, the generated 'u-boot.imx' binary must be +flashed into the SD card: + +$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync + +(Note - the SD card node may vary, so adjust this as needed). + +Also, a more detailed explanation on how to format the SD card is available +at doc/README.imximage. + +- Insert the micro SD card into the slot located in the bottom of the board + +- Connect a 3.3V USB to serial converter cable to the host PC. The MX6 UART +signals are available in the 26 pin connector as shown at: +http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware +(Check for "26 pin header layout"). + +- Power up the board via USB cable (CON201) and U-boot messages will appear in +the serial console. diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c new file mode 100644 index 0000000000..52c384bdd4 --- /dev/null +++ b/board/solidrun/hummingboard/hummingboard.c @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton . + * + * Authors: Fabio Estevam + Jon Nettleton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ETH_PHY_RESET IMX_GPIO_NR(4, 15) + +int dram_init(void) +{ + gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + { USDHC2_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* SD card is the boot medium, so always present */ +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 reset */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + /* AR8035 interrupt */ + MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPIO16 -> AR8035 25MHz */ + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + gpio_direction_output(ETH_PHY_RESET, 0); + mdelay(2); + gpio_set_value(ETH_PHY_RESET, 1); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int ret = enable_fec_anatop_clock(ENET_25MHZ); + if (ret) + return ret; + + /* set gpr1[ENET_CLK_SEL] */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + setup_iomux_enet(); + + return cpu_eth_init(bis); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Hummingboard\n"); + + return 0; +} diff --git a/board/solidrun/hummingboard/solo.cfg b/board/solidrun/hummingboard/solo.cfg new file mode 100644 index 0000000000..28dd75065e --- /dev/null +++ b/board/solidrun/hummingboard/solo.cfg @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 Jon Nettleton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "../mx6-microsom/ddr-800mhz-32bit-setup.cfg" +#include "../mx6-microsom/800mhz_2x128mx16.cfg" +#include "../mx6-microsom/clocks.cfg" diff --git a/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg new file mode 100644 index 0000000000..40747abbdb --- /dev/null +++ b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* ZQ Calibrations */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 +/* write leveling */ +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052 +/* + * DQS gating, read delay, write delay calibration values + * based on calibration compare of 0x00ffff00 + */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034 +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +/* Complete calibration by forced measurement */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* + * MMDC init: + * in DDR3, 32-bit mode, only MMDC0 is initiated: + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63 + +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +/* CS0_END - 0x2fffffff, 512M */ +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 + +/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */ +DATA 4, 0x021b0400, 0x11420000 + +/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */ +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 + +/* + * Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C + * MR2 + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032 +/* MR3 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +/* MR1 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 +/* MR0 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +/* final DDR setup */ +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/solidrun/mx6-microsom/clocks.cfg b/board/solidrun/mx6-microsom/clocks.cfg new file mode 100644 index 0000000000..12888113fb --- /dev/null +++ b/board/solidrun/mx6-microsom/clocks.cfg @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg new file mode 100644 index 0000000000..f92fc19de4 --- /dev/null +++ b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +/* DDR IO TYPE */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* Clock */ +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 +/* Address */ +DATA 4, MX6_IOM_DRAM_CAS, 0x00000010 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000010 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010 +/* Control */ +DATA 4, MX6_IOM_DRAM_RESET, 0x00000010 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010 + +/* + * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS, + * CMOS mode saves power, but have less timing margin in case of DDR + * timing issue on your board you can try DDR_MODE: [= 0x00020000] + */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 + +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 + +/* + * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS, + * CMOS mode saves power, but have less timing margin in case of DDR + * timing issue on your board you can try DDR_MODE: [= 0x00020000] + */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile deleted file mode 100644 index cadacee792..0000000000 --- a/board/spc1920/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o hpi.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c deleted file mode 100644 index c593837ad6..0000000000 --- a/board/spc1920/hpi.c +++ /dev/null @@ -1,596 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Host Port Interface (HPI) - */ - -/* debug levels: - * 0 : errors - * 1 : usefull info - * 2 : lots of info - * 3 : noisy - */ - -#define DEBUG 0 - -#include -#include -#include - -#include "pld.h" -#include "hpi.h" - -#define _NOT_USED_ 0xFFFFFFFF - -/* original table: - * - inserted loops to achieve long CS low and high Periods (~217ns) - * - move cs high 2/4 to the right - */ -const uint dsp_table_slow[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x8fffdc04, 0x0fffdc84, 0x0fffdc84, 0x0fffdc00, - 0x3fffdc04, 0xffffdc84, 0xffffdc84, 0xffffdc05, - - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write (offset 0x18 in upm ram) */ - 0x8fffd004, 0x0fffd084, 0x0fffd084, 0x3fffd000, - 0xffffd084, 0xffffd084, 0xffffd005, _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* dsp hpi upm ram table - * works fine for noninc access, failes on incremental. - * - removed first word - */ -const uint dsp_table_fast[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x8fffdc04, 0x0fffdc04, 0x0fffdc00, 0x3fffdc04, - 0xffffdc05, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write (offset 0x18 in upm ram) */ - 0x8fffd004, 0x0fffd004, 0x3fffd000, 0xffffd005, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -#ifdef CONFIG_SPC1920_HPI_TEST -#undef HPI_TEST_OSZI - -#define HPI_TEST_CHUNKSIZE 0x1000 -#define HPI_TEST_PATTERN 0x00000000 -#define HPI_TEST_START 0x0 -#define HPI_TEST_END 0x30000 - -#define TINY_AUTOINC_DATA_SIZE 16 /* 32bit words */ -#define TINY_AUTOINC_BASE_ADDR 0x0 - -static int hpi_activate(void); -#if 0 -static void hpi_inactivate(void); -#endif -static void dsp_reset(void); - -static int hpi_write_inc(u32 addr, u32 *data, u32 count); -static int hpi_read_inc(u32 addr, u32 *buf, u32 count); -static int hpi_write_noinc(u32 addr, u32 data); -static u32 hpi_read_noinc(u32 addr); - -int hpi_test(void); -static int hpi_write_addr_test(u32 addr); -static int hpi_read_write_test(u32 addr, u32 data); -#ifdef DO_TINY_TEST -static int hpi_tiny_autoinc_test(void); -#endif /* DO_TINY_TEST */ -#endif /* CONFIG_SPC1920_HPI_TEST */ - - -/* init the host port interface on UPMA */ -int hpi_init(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint)); - udelay(100); - - memctl->memc_mamr = CONFIG_SYS_MAMR; - memctl->memc_or3 = CONFIG_SYS_OR3; - memctl->memc_br3 = CONFIG_SYS_BR3; - - /* reset dsp */ - dsp_reset(); - - /* activate hpi switch*/ - pld->dsp_hpi_on = 0x1; - - udelay(100); - - return 0; -} - -#ifdef CONFIG_SPC1920_HPI_TEST -/* activate the Host Port interface */ -static int hpi_activate(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - /* turn on hpi */ - pld->dsp_hpi_on = 0x1; - - udelay(5); - - /* turn on the power EN_DSP_POWER high*/ - /* currently always on TBD */ - - /* setup hpi control register */ - HPI_HPIC_1 = (u16) 0x0008; - HPI_HPIC_2 = (u16) 0x0008; - - udelay(100); - - return 0; -} - -#if 0 -/* turn off the host port interface */ -static void hpi_inactivate(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - /* deactivate hpi */ - pld->dsp_hpi_on = 0x0; - - /* reset the dsp */ - /* pld->dsp_reset = 0x0; */ - - /* turn off the power EN_DSP_POWER# high*/ - /* currently always on TBD */ - -} -#endif - -/* reset the DSP */ -static void dsp_reset(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - pld->dsp_reset = 0x1; - pld->dsp_hpi_on = 0x0; - - udelay(300000); - - pld->dsp_reset = 0x0; - pld->dsp_hpi_on = 0x1; -} - - -/* write using autoinc (count is number of 32bit words) */ -static int hpi_write_inc(u32 addr, u32 *data, u32 count) -{ - int i; - u16 addr1, addr2; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* write address */ - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - debug("writing from data=0x%lx to 0x%lx\n", - (ulong)data, (ulong)(data+count)); - - for(i=0; i> 16) & 0xffff); - HPI_HPID_INC_2 = (u16) (data[i] & 0xffff); - debug("hpi_write_inc: data1=0x%x, data2=0x%x\n", - (u16) ((data[i] >> 16) & 0xffff), - (u16) (data[i] & 0xffff)); - } -#if 0 - while(data_ptr < (u16*) (data + count)) { - HPI_HPID_INC_1 = *(data_ptr++); - HPI_HPID_INC_2 = *(data_ptr++); - } -#endif - - /* return number of bytes written */ - return count; -} - -/* - * read using autoinc (count is number of 32bit words) - */ -static int hpi_read_inc(u32 addr, u32 *buf, u32 count) -{ - int i; - u16 addr1, addr2, data1, data2; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* write address */ - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - for(i=0; i> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* printf("hpi_write_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */ - - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - data1 = (u16) ((data >> 16) & 0xffff); - data2 = (u16) (data & 0xffff); - - /* printf("hpi_write_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */ - - HPI_HPID_NOINC_1 = data1; - HPI_HPID_NOINC_2 = data2; - - return 0; -} - -/* read from non- auto inc regs */ -static u32 hpi_read_noinc(u32 addr) -{ - u16 addr1, addr2, data1, data2; - u32 ret; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - /* printf("hpi_read_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */ - - data1 = HPI_HPID_NOINC_1; - data2 = HPI_HPID_NOINC_2; - - /* printf("hpi_read_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */ - - ret = (((u32) data1) << 16) | (data2 & 0xffff); - return ret; - -} - -/* - * Host Port Interface Tests - */ - -#ifndef HPI_TEST_OSZI -/* main test function */ -int hpi_test(void) -{ - int err = 0; - u32 i, ii, pattern, tmp; - - pattern = HPI_TEST_PATTERN; - - u32 test_data[HPI_TEST_CHUNKSIZE]; - u32 read_data[HPI_TEST_CHUNKSIZE]; - - debug("hpi_test: activating hpi..."); - hpi_activate(); - debug("OK.\n"); - -#if 0 - /* Dump the first 1024 bytes - * - */ - for(i=0; i<1024; i+=4) { - if(i%16==0) - printf("\n0x%08x: ", i); - printf("0x%08x ", hpi_read_noinc(i)); - } -#endif - - /* HPIA read-write test - * - */ - debug("hpi_test: starting HPIA read-write tests...\n"); - err |= hpi_write_addr_test(0xdeadc0de); - err |= hpi_write_addr_test(0xbeefd00d); - err |= hpi_write_addr_test(0xabcd1234); - err |= hpi_write_addr_test(0xaaaaaaaa); - if(err) { - debug("hpi_test: HPIA read-write tests: *** FAILED ***\n"); - return -1; - } - debug("hpi_test: HPIA read-write tests: OK\n"); - - - /* read write test using nonincremental data regs - * - */ - debug("hpi_test: starting nonincremental tests...\n"); - for(i=HPI_TEST_START; i> 16)); /* First HW is most significant */ - HPI_HPIA_2 = ((u16) addr); - - read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2); - - if(read_back == addr) { - debug(" hpi_write_addr_test OK: written=0x%x, read=0x%x\n", - addr, read_back); - return 0; - } else { - debug(" hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n", - addr, read_back); - return -1; - } - - return 0; -} - -/* test if a simple read/write sequence succeeds */ -static int hpi_read_write_test(u32 addr, u32 data) -{ - u32 read_back; - - hpi_write_noinc(addr, data); - read_back = hpi_read_noinc(addr); - - if(read_back == data) { - debug(" hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back); - return 0; - } else { - debug(" hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back); - return -1; - } - - return 0; -} - -#ifdef DO_TINY_TEST -static int hpi_tiny_autoinc_test(void) -{ - int i; - u32 read_data[TINY_AUTOINC_DATA_SIZE]; - u32 read_data_noinc[TINY_AUTOINC_DATA_SIZE]; - - unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = { - 0x11112222, 0x33334444, 0x55556666, 0x77778888, - 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111, - 0x00010002, 0x00030004, 0x00050006, 0x00070008, - 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001 - }; - - printf(" writing to autoinc...\n"); - hpi_write_inc(TINY_AUTOINC_BASE_ADDR, dummy_data, TINY_AUTOINC_DATA_SIZE); - - printf(" reading from autoinc...\n"); - hpi_read_inc(TINY_AUTOINC_BASE_ADDR, read_data, TINY_AUTOINC_DATA_SIZE); - - printf(" reading from noinc for comparison...\n"); - for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) - read_data_noinc[i] = hpi_read_noinc(TINY_AUTOINC_BASE_ADDR+i*4); - - for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) { - printf(" written=0x%x, read(inc)=0x%x, read(noinc)=0x%x\n", - dummy_data[i], read_data[i], read_data_noinc[i]); - } - return 0; -} -#endif /* DO_TINY_TEST */ - -#endif /* CONFIG_SPC1920_HPI_TEST */ diff --git a/board/spc1920/hpi.h b/board/spc1920/hpi.h deleted file mode 100644 index db67672a8e..0000000000 --- a/board/spc1920/hpi.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -int hpi_init(void); - -#ifdef CONFIG_SPC1920_HPI_TEST -int hpi_test(void); -#endif diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h deleted file mode 100644 index 5beb71b5cc..0000000000 --- a/board/spc1920/pld.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __PLD_H__ -#define __PLD_H__ - -typedef struct spc1920_pld { - uchar com1_en; - uchar dsp_reset; - uchar dsp_hpi_on; - uchar superv_mode; - uchar codec_dsp_power_en; - uchar clk3_select; - uchar clk4_select; -} spc1920_pld_t; - -#endif /* __PLD_H__ */ diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c deleted file mode 100644 index 1775433f0d..0000000000 --- a/board/spc1920/spc1920.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "pld.h" -#include "hpi.h" - -#define _NOT_USED_ 0xFFFFFFFF - -static long int dram_size (long int, long int *, long int); - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMB RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMB RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMB RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */ - - long int size_b0; - long int size8, size9; - int i; - - /* - * Configure UPMB for SDRAM - */ - upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - udelay(100); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = CONFIG_SYS_MAR; - - /* - * Map controller bank 1 to the SDRAM bank at preliminary address. - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - /* initialize memory address register */ - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ - udelay (200); /* 0x80006105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05); - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06); - - memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { - volatile unsigned long *addr = - (volatile unsigned long *) CONFIG_SYS_SDRAM_BASE; - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; - memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE; - udelay (500); - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; - udelay (500); - } - - /* - * Final mapping: - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | - OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; - udelay (1000); - - /* initalize the DSP Host Port Interface */ - hpi_init(); - - /* FRAM Setup */ - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - udelay(1000); - - return (size_b0); -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int mbmr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mbmr = mbmr_value; - - return (get_ram_size (base, maxsize)); -} - - -/************* other stuff ******************/ - - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* Set Go/NoGo led (PA15) to color red */ - immap->im_ioport.iop_papar &= ~0x1; - immap->im_ioport.iop_paodr &= ~0x1; - immap->im_ioport.iop_padir |= 0x1; - immap->im_ioport.iop_padat |= 0x1; - -#if 0 - /* Turn on LED PD9 */ - immap->im_ioport.iop_pdpar &= ~(0x0040); - immap->im_ioport.iop_pddir |= 0x0040; - immap->im_ioport.iop_pddat |= 0x0040; -#endif - - /* - * Enable console on SMC1. This requires turning on - * the com2_en signal and SMC1_DISABLE - */ - - /* SMC1_DISABLE: PB17 */ - immap->im_cpm.cp_pbodr &= ~0x4000; - immap->im_cpm.cp_pbpar &= ~0x4000; - immap->im_cpm.cp_pbdir |= 0x4000; - immap->im_cpm.cp_pbdat &= ~0x4000; - - /* COM2_EN: PD10 */ - immap->im_ioport.iop_pdpar &= ~0x0020; - immap->im_ioport.iop_pddir &= ~0x4000; - immap->im_ioport.iop_pddir |= 0x0020; - immap->im_ioport.iop_pddat |= 0x0020; - - -#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */ - immap->im_cpm.cp_simode |= 0x7000; - immap->im_cpm.cp_simode &= ~(0x8000); -#endif - - return 0; -} - -int last_stage_init(void) -{ -#ifdef CONFIG_SPC1920_HPI_TEST - printf("CMB1920 Host Port Interface Test: %s\n", - hpi_test() ? "Failed!" : "OK"); -#endif - return 0; -} - -int checkboard (void) -{ - puts("Board: SPC1920\n"); - return 0; -} diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/spc1920/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/spd8xx/Makefile b/board/spd8xx/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/spd8xx/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/spd8xx/flash.c b/board/spd8xx/flash.c deleted file mode 100644 index 4a332e037b..0000000000 --- a/board/spd8xx/flash.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - /* All Speech Design board memory (DRAM and EPROM) initialisation is - done in dram_init(). - The caller of ths function here expects the total size and will hang, - if we give here back 0. So we return the EPROM size. */ - - return (1024 * 1024); /* 1 MB */ -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - printf("no FLASH memory in MPC823TS board\n"); - return; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - return 1; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c deleted file mode 100644 index d3320bb9a3..0000000000 --- a/board/spd8xx/spd8xx.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sharc_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - puts ("Board: SPD823TS\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; - -#if 0 - /* - * Map controller bank 2 to the SRAM bank at preliminary address. - */ - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; -#endif - - /* - * Map controller bank 4 to the PER8 bank. - */ - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - -#if 0 - /* Configure SHARC at UMA */ - upmconfig (UPMA, (uint *) sharc_table, - sizeof (sharc_table) / sizeof (uint)); - /* Map controller bank 5 to the SHARC */ - memctl->memc_or5 = CONFIG_SYS_OR5; - memctl->memc_br5 = CONFIG_SYS_BR5; -#endif - - memctl->memc_mamr = 0x00001000; - - /* Configure SDRAM at UMB */ - upmconfig (UPMB, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ - - udelay (200); - memctl->memc_mcr = 0x80806105; - udelay (1); - memctl->memc_mcr = 0x80806130; - udelay (1); - memctl->memc_mcr = 0x80806130; - udelay (1); - memctl->memc_mcr = 0x80806106; - - memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ - - /* - * Check Bank 0 Memory Size for re-configuration - */ - size_b0 = - dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mbmr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -void reset_phy (void) -{ - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - ushort sreg; - - /* Configure extra port pins for NS DP83843 PHY */ - immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO); - - sreg = immr->im_ioport.iop_padir; - sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */ - sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */ - immr->im_ioport.iop_padir = sreg; - - immr->im_ioport.iop_padat &= ~(PA_ENET_MDC); /* set MDC = 0 */ - - /* - * RESET in implemented by a positive pulse of at least 1 us - * at the reset pin. - * - * Configure RESET pins for NS DP83843 PHY, and RESET chip. - * - * Note: The RESET pin is high active, but there is an - * inverter on the SPD823TS board... - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET); - immr->im_ioport.iop_pcdir |= PC_ENET_RESET; - /* assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET); - udelay (10); - /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat |= PC_ENET_RESET; - udelay (10); -} - -/* ------------------------------------------------------------------------- */ - -void ide_set_reset (int on) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Configure PC for IDE Reset Pin - */ - if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); - } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; - } - - /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET; -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds deleted file mode 100644 index 2a68934c32..0000000000 --- a/board/spd8xx/u-boot.lds +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - *(.text.v*printf) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug deleted file mode 100644 index 7cfed1f1d5..0000000000 --- a/board/spd8xx/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile index 6e397eeff0..b0ba320481 100644 --- a/board/spear/common/Makefile +++ b/board/spear/common/Makefile @@ -5,30 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o +else +obj-y := spr_misc.o +obj-y += spr_lowlevel_init.o endif - -LIB = $(obj)lib$(VENDOR).o - -ifndef CONFIG_SPL_BUILD -COBJS := spr_misc.o -SOBJS := spr_lowlevel_init.o -endif - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/spear/spear300/Kconfig b/board/spear/spear300/Kconfig new file mode 100644 index 0000000000..27360f32e4 --- /dev/null +++ b/board/spear/spear300/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SPEAR300 + +config SYS_BOARD + default "spear300" + +config SYS_VENDOR + default "spear" + +config SYS_SOC + default "spear" + +config SYS_CONFIG_NAME + default "spear3xx_evb" + +endif diff --git a/board/spear/spear300/MAINTAINERS b/board/spear/spear300/MAINTAINERS new file mode 100644 index 0000000000..07152aefba --- /dev/null +++ b/board/spear/spear300/MAINTAINERS @@ -0,0 +1,13 @@ +SPEAR300 BOARD +M: Vipin Kumar +S: Maintained +F: board/spear/spear300/ +F: include/configs/spear3xx_evb.h +F: configs/spear300_defconfig + +SPEAR300_NAND BOARD +#M: - +S: Maintained +F: configs/spear300_nand_defconfig +F: configs/spear300_usbtty_defconfig +F: configs/spear300_usbtty_nand_defconfig diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile index 63ff1d5e56..84d05e332e 100644 --- a/board/spear/spear300/Makefile +++ b/board/spear/spear300/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := spear300.o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := spear300.o diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index e25aba2f28..6b6bd9f29d 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/spear310/Kconfig b/board/spear/spear310/Kconfig new file mode 100644 index 0000000000..0c95fa35a0 --- /dev/null +++ b/board/spear/spear310/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SPEAR310 + +config SYS_BOARD + default "spear310" + +config SYS_VENDOR + default "spear" + +config SYS_SOC + default "spear" + +config SYS_CONFIG_NAME + default "spear3xx_evb" + +endif diff --git a/board/spear/spear310/MAINTAINERS b/board/spear/spear310/MAINTAINERS new file mode 100644 index 0000000000..4f9aa15b83 --- /dev/null +++ b/board/spear/spear310/MAINTAINERS @@ -0,0 +1,15 @@ +SPEAR310 BOARD +M: Vipin Kumar +S: Maintained +F: board/spear/spear310/ +F: include/configs/spear3xx_evb.h +F: configs/spear310_defconfig + +SPEAR310_NAND BOARD +#M: - +S: Maintained +F: configs/spear310_nand_defconfig +F: configs/spear310_pnor_defconfig +F: configs/spear310_usbtty_defconfig +F: configs/spear310_usbtty_nand_defconfig +F: configs/spear310_usbtty_pnor_defconfig diff --git a/board/spear/spear310/Makefile b/board/spear/spear310/Makefile index 5664097a7e..3a2e3ac086 100644 --- a/board/spear/spear310/Makefile +++ b/board/spear/spear310/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := spear310.o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := spear310.o diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 70f9aa16ea..a4c6a8edb0 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear320/Kconfig b/board/spear/spear320/Kconfig new file mode 100644 index 0000000000..df176230f4 --- /dev/null +++ b/board/spear/spear320/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SPEAR320 + +config SYS_BOARD + default "spear320" + +config SYS_VENDOR + default "spear" + +config SYS_SOC + default "spear" + +config SYS_CONFIG_NAME + default "spear3xx_evb" + +endif diff --git a/board/spear/spear320/MAINTAINERS b/board/spear/spear320/MAINTAINERS new file mode 100644 index 0000000000..bf7809230f --- /dev/null +++ b/board/spear/spear320/MAINTAINERS @@ -0,0 +1,15 @@ +SPEAR320 BOARD +M: Vipin Kumar +S: Maintained +F: board/spear/spear320/ +F: include/configs/spear3xx_evb.h +F: configs/spear320_defconfig + +SPEAR320_NAND BOARD +#M: - +S: Maintained +F: configs/spear320_nand_defconfig +F: configs/spear320_pnor_defconfig +F: configs/spear320_usbtty_defconfig +F: configs/spear320_usbtty_nand_defconfig +F: configs/spear320_usbtty_pnor_defconfig diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile index 986e495c70..f01116e6b1 100644 --- a/board/spear/spear320/Makefile +++ b/board/spear/spear320/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := spear320.o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := spear320.o diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index f6b1fdd0e6..ab732a724c 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear600/Kconfig b/board/spear/spear600/Kconfig new file mode 100644 index 0000000000..d562e64f07 --- /dev/null +++ b/board/spear/spear600/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SPEAR600 + +config SYS_BOARD + default "spear600" + +config SYS_VENDOR + default "spear" + +config SYS_SOC + default "spear" + +config SYS_CONFIG_NAME + default "spear6xx_evb" + +endif diff --git a/board/spear/spear600/MAINTAINERS b/board/spear/spear600/MAINTAINERS new file mode 100644 index 0000000000..ddcd11a873 --- /dev/null +++ b/board/spear/spear600/MAINTAINERS @@ -0,0 +1,13 @@ +SPEAR600 BOARD +M: Vipin Kumar +S: Maintained +F: board/spear/spear600/ +F: include/configs/spear6xx_evb.h +F: configs/spear600_defconfig + +SPEAR600_NAND BOARD +#M: - +S: Maintained +F: configs/spear600_nand_defconfig +F: configs/spear600_usbtty_defconfig +F: configs/spear600_usbtty_nand_defconfig diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile index 123512b516..7abfb9ad50 100644 --- a/board/spear/spear600/Makefile +++ b/board/spear/spear600/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifndef CONFIG_SPL_BUILD -COBJS := spear600.o +obj-y := spear600.o endif -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index e996a0e381..8472002f74 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DW_AUTONEG) interface = PHY_INTERFACE_MODE_GMII; #endif - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/x600/Kconfig b/board/spear/x600/Kconfig new file mode 100644 index 0000000000..6a1c5c7b40 --- /dev/null +++ b/board/spear/x600/Kconfig @@ -0,0 +1,15 @@ +if TARGET_X600 + +config SYS_BOARD + default "x600" + +config SYS_VENDOR + default "spear" + +config SYS_SOC + default "spear" + +config SYS_CONFIG_NAME + default "x600" + +endif diff --git a/board/spear/x600/MAINTAINERS b/board/spear/x600/MAINTAINERS new file mode 100644 index 0000000000..bff6824945 --- /dev/null +++ b/board/spear/x600/MAINTAINERS @@ -0,0 +1,6 @@ +X600 BOARD +M: Stefan Roese +S: Maintained +F: board/spear/x600/ +F: include/configs/x600.h +F: configs/x600_defconfig diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile index 5524e4f5b1..18d3dd2e6f 100644 --- a/board/spear/x600/Makefile +++ b/board/spear/x600/Makefile @@ -5,27 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -ifndef CONFIG_SPL_BUILD -COBJS := fpga.o $(BOARD).o +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o +else +obj-y := fpga.o x600.o endif -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c index c06c994777..b256222e18 100644 --- a/board/spear/x600/fpga.c +++ b/board/spear/x600/fpga.c @@ -163,7 +163,7 @@ static int fpga_wr_fn(int assert_write, int flush, int cookie) return assert_write; } -static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = { +static xilinx_spartan3_slave_serial_fns x600_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, @@ -173,7 +173,7 @@ static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = { fpga_post_config_fn, }; -static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +static xilinx_desc fpga[CONFIG_FPGA_COUNT] = { XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0) }; diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index 044d2049ef..b8edfcd071 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -67,31 +67,32 @@ void board_nand_init(void) fsmc_nand_init(nand); } -int designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) +int board_phy_config(struct phy_device *phydev) { /* Extended PHY control 1, select GMII */ - mii_write(dev, phy_addr, 23, 0x0020); + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); /* Software reset necessary after GMII mode selction */ - dw_reset_phy(dev); + phy_reset(phydev); /* Enable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0001); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); /* 17e: Enhanced LED behavior, needs to be written twice */ - mii_write(dev, phy_addr, 17, 0x09ff); - mii_write(dev, phy_addr, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); /* 16e: Enhanced LED method select */ - mii_write(dev, phy_addr, 16, 0xe0ea); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); /* Disable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); /* Enable clock output pin */ - mii_write(dev, phy_addr, 18, 0x0049); + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } @@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis) { int ret = 0; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + if (designware_initialize(CONFIG_SPEAR_ETHBASE, PHY_INTERFACE_MODE_GMII) >= 0) ret++; diff --git a/board/st-ericsson/snowball/Kconfig b/board/st-ericsson/snowball/Kconfig new file mode 100644 index 0000000000..0b3a0cca6c --- /dev/null +++ b/board/st-ericsson/snowball/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SNOWBALL + +config SYS_BOARD + default "snowball" + +config SYS_VENDOR + default "st-ericsson" + +config SYS_SOC + default "u8500" + +config SYS_CONFIG_NAME + default "snowball" + +endif diff --git a/board/st-ericsson/snowball/MAINTAINERS b/board/st-ericsson/snowball/MAINTAINERS new file mode 100644 index 0000000000..132fc524ba --- /dev/null +++ b/board/st-ericsson/snowball/MAINTAINERS @@ -0,0 +1,6 @@ +SNOWBALL BOARD +M: Mathieu Poirier +S: Maintained +F: board/st-ericsson/snowball/ +F: include/configs/snowball.h +F: configs/snowball_defconfig diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile index d6f45df3a5..f0605e2bcd 100644 --- a/board/st-ericsson/snowball/Makefile +++ b/board/st-ericsson/snowball/Makefile @@ -4,30 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +ccflags-y += -D__RELEASE -D__STN_8500 -CFLAGS += -D__RELEASE -D__STN_8500 -LIB = $(obj)lib$(BOARD).o - -COBJS := snowball.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := snowball.o diff --git a/board/st-ericsson/u8500/Kconfig b/board/st-ericsson/u8500/Kconfig new file mode 100644 index 0000000000..909f30db4b --- /dev/null +++ b/board/st-ericsson/u8500/Kconfig @@ -0,0 +1,15 @@ +if TARGET_U8500_HREF + +config SYS_BOARD + default "u8500" + +config SYS_VENDOR + default "st-ericsson" + +config SYS_SOC + default "u8500" + +config SYS_CONFIG_NAME + default "u8500_href" + +endif diff --git a/board/st-ericsson/u8500/MAINTAINERS b/board/st-ericsson/u8500/MAINTAINERS new file mode 100644 index 0000000000..e2581eb2e4 --- /dev/null +++ b/board/st-ericsson/u8500/MAINTAINERS @@ -0,0 +1,6 @@ +U8500 BOARD +#M: - +S: Maintained +F: board/st-ericsson/u8500/ +F: include/configs/u8500_href.h +F: configs/u8500_href_defconfig diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile index 4b901d25e8..d6c4280475 100644 --- a/board/st-ericsson/u8500/Makefile +++ b/board/st-ericsson/u8500/Makefile @@ -4,25 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +ccflags-y += -D__RELEASE -D__STN_8500 -CFLAGS += -D__RELEASE -D__STN_8500 -LIB = $(obj)lib$(BOARD).o - -COBJS := u8500_href.o gpio.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := u8500_href.o gpio.o diff --git a/board/st/nhk8815/Kconfig b/board/st/nhk8815/Kconfig new file mode 100644 index 0000000000..94547dc118 --- /dev/null +++ b/board/st/nhk8815/Kconfig @@ -0,0 +1,12 @@ +if NOMADIK_NHK8815 + +config SYS_BOARD + default "nhk8815" + +config SYS_VENDOR + default "st" + +config SYS_CONFIG_NAME + default "nhk8815" + +endif diff --git a/board/st/nhk8815/MAINTAINERS b/board/st/nhk8815/MAINTAINERS new file mode 100644 index 0000000000..72c3a8d903 --- /dev/null +++ b/board/st/nhk8815/MAINTAINERS @@ -0,0 +1,8 @@ +NHK8815 BOARD +M: Nomadik Linux Team +M: Alessandro Rubini +S: Maintained +F: board/st/nhk8815/ +F: include/configs/nhk8815.h +F: configs/nhk8815_defconfig +F: configs/nhk8815_onenand_defconfig diff --git a/board/st/nhk8815/Makefile b/board/st/nhk8815/Makefile index b1c6197e0b..dd56944db1 100644 --- a/board/st/nhk8815/Makefile +++ b/board/st/nhk8815/Makefile @@ -9,25 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := nhk8815.o -SOBJS := - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := nhk8815.o diff --git a/board/st/stv0991/Kconfig b/board/st/stv0991/Kconfig new file mode 100644 index 0000000000..007712f9c6 --- /dev/null +++ b/board/st/stv0991/Kconfig @@ -0,0 +1,15 @@ +if TARGET_STV0991 + +config SYS_BOARD + default "stv0991" + +config SYS_VENDOR + default "st" + +config SYS_SOC + default "stv0991" + +config SYS_CONFIG_NAME + default "stv0991" + +endif diff --git a/board/st/stv0991/MAINTAINERS b/board/st/stv0991/MAINTAINERS new file mode 100644 index 0000000000..e7a2ccaa1f --- /dev/null +++ b/board/st/stv0991/MAINTAINERS @@ -0,0 +1,6 @@ +STV0991 APPLICATION BOARD +M: Vikas Manocha +S: Maintained +F: board/st/stv0991/ +F: include/configs/stv0991.h +F: configs/stv0991_defconfig diff --git a/board/st/stv0991/Makefile b/board/st/stv0991/Makefile new file mode 100644 index 0000000000..fb5169a3c5 --- /dev/null +++ b/board/st/stv0991/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := stv0991.o diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c new file mode 100644 index 0000000000..f465699b55 --- /dev/null +++ b/board/st/stv0991/stv0991.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct gpio_regs *const gpioa_regs = + (struct gpio_regs *) GPIOA_BASE_ADDR; + +static const struct pl01x_serial_platdata serial_platdata = { + .base = 0x80406000, + .type = TYPE_PL011, + .clock = 2700 * 1000, +}; + +U_BOOT_DEVICE(stv09911_serials) = { + .name = "serial_pl01x", + .platdata = &serial_platdata, +}; + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int progress) +{ + printf("%i\n", progress); +} +#endif + +void enable_eth_phy(void) +{ + /* Set GPIOA_06 pad HIGH (Appli board)*/ + writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir); + writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data); +} +int board_eth_enable(void) +{ + stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4); + clock_setup(ETH_CLOCK_CFG); + enable_eth_phy(); + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + board_eth_enable(); + return 0; +} + +int board_uart_init(void) +{ + stv0991_pinmux_config(UART_GPIOC_30_31); + clock_setup(UART_CLOCK_CFG); + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + board_uart_init(); + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0) + ret++; +#endif + return ret; +} +#endif diff --git a/board/stx/stxgp3/Kconfig b/board/stx/stxgp3/Kconfig new file mode 100644 index 0000000000..910b31b24f --- /dev/null +++ b/board/stx/stxgp3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_STXGP3 + +config SYS_BOARD + default "stxgp3" + +config SYS_VENDOR + default "stx" + +config SYS_CONFIG_NAME + default "stxgp3" + +endif diff --git a/board/stx/stxgp3/MAINTAINERS b/board/stx/stxgp3/MAINTAINERS new file mode 100644 index 0000000000..bd5743c7de --- /dev/null +++ b/board/stx/stxgp3/MAINTAINERS @@ -0,0 +1,6 @@ +STXGP3 BOARD +#M: Dan Malek +S: Orphan (since 2014-06) +F: board/stx/stxgp3/ +F: include/configs/stxgp3.h +F: configs/stxgp3_defconfig diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile index 0b0f26e724..78e2d6c96f 100644 --- a/board/stx/stxgp3/Makefile +++ b/board/stx/stxgp3/Makefile @@ -5,28 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-y += flash.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += stxgp3.o +obj-y += law.o +obj-y += tlb.o +obj-y += flash.o +obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c index 571137443e..41d4cfe738 100644 --- a/board/stx/stxgp3/ddr.c +++ b/board/stx/stxgp3/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index e5e8311099..c80d5259ce 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -9,7 +9,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/stx/stxssa/Kconfig b/board/stx/stxssa/Kconfig new file mode 100644 index 0000000000..bd47b04444 --- /dev/null +++ b/board/stx/stxssa/Kconfig @@ -0,0 +1,12 @@ +if TARGET_STXSSA + +config SYS_BOARD + default "stxssa" + +config SYS_VENDOR + default "stx" + +config SYS_CONFIG_NAME + default "stxssa" + +endif diff --git a/board/stx/stxssa/MAINTAINERS b/board/stx/stxssa/MAINTAINERS new file mode 100644 index 0000000000..b7cc89bf73 --- /dev/null +++ b/board/stx/stxssa/MAINTAINERS @@ -0,0 +1,7 @@ +STXSSA BOARD +#M: Dan Malek +S: Orphan (since 2014-06) +F: board/stx/stxssa/ +F: include/configs/stxssa.h +F: configs/stxssa_defconfig +F: configs/stxssa_4M_defconfig diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile index 8757a71a82..b1d4b0a270 100644 --- a/board/stx/stxssa/Makefile +++ b/board/stx/stxssa/Makefile @@ -5,27 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += stxssa.o +obj-y += law.o +obj-y += tlb.o +obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c index 56c87b2fc6..1ccd4c5183 100644 --- a/board/stx/stxssa/ddr.c +++ b/board/stx/stxssa/ddr.c @@ -9,8 +9,8 @@ #include #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -37,7 +37,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index e69e2662c8..6e4eed86a5 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -9,7 +9,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include @@ -233,9 +233,11 @@ reset_phy(void) } #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/stx/stxxtc/Makefile b/board/stx/stxxtc/Makefile deleted file mode 100644 index e7f4fb63b0..0000000000 --- a/board/stx/stxxtc/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/stx/stxxtc/README.stxxtc b/board/stx/stxxtc/README.stxxtc deleted file mode 100644 index 7d9d4d3a2e..0000000000 --- a/board/stx/stxxtc/README.stxxtc +++ /dev/null @@ -1,59 +0,0 @@ - - -First, some build notes on the Silicon Turnkey eXpress XTc. - -This board has both 87x/88x procesor options at various -frequencies. The configuration file has some macros for setting -the clock speed, not all have been tested. They all have -a 10MHz input clock. Please do not check in a configuration -file that selects a high speed not available on all processors. -We chose the 66MHz core and bus speed, which should be OK on -all boards. If you have a processor, lucky you! :-) -Just build a new configuration with that speed, check -the macro configuration to ensure it's correct. If the -macro is updated, please check that in, but keep default -processor speed. - -The board is likely to have more than 1Mbyte of NOR boot flash. -It was also configured with a high boot vector (Dan's fault) -so the standard 8xx mapping doesn't work well. We had to move -the addresses around a little bit so one copy would work. The -flash got fragmented, and we are working on a better solution. -There is an "xtc.cfg" floating around for the BDI2000, use -that for programming a new version of U-Boot. You can probably -find it on the Silicon Turnkey eXpress (www.silicontkx.com), -Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de) -servers. - -The board will also have various SDRAM sizes, but the code -should automatically determine the amount of memory. - -There are a couple of different board versions, visually -they use different BGA or surface mount memory parts. However, -they are logically the same board. - -Now, some operational notes. - -The board has the option of sporting two FEC Ethernet ports. -The second port isn't configured to be automatically available -because it would cause U-Boot to generate a board data structure -(the bd_t) with multiple MAC addresses and be incompatible with -standard 8xx kernel builds. You can use/test the second FEC -in U-Boot by assigning an 'eth1addr' and selecting the second -FEC as the port to use. - -Since this is just a development board and not a product, STx -does not assign unique MAC addresses. We just pilfer the -"default" ones used by Wolfgang on some other boards. Please -ensure you assign unique MAC addresses when using these boards. - -The serial port baud rate is 38400, because that's the way -I like it :-) - -Thanks to Pantelis for lots of the work on this board port. - -Have Fun! - - -- Dan - -15 August 2005 diff --git a/board/stx/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c deleted file mode 100644 index 1996efb664..0000000000 --- a/board/stx/stxxtc/stxxtc.c +++ /dev/null @@ -1,592 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2005 - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * U-Boot port on STx XTc board - * Mostly copied from Netta - */ - -#include -#include - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include -#endif - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Silicon Turnkey eXpress XTc\n"); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 9 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - u32 d1, d2; - - upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - d1 = 0x12345678; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - miiphy_read("FEC", phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK _BW(6) -#define PA_GP_OUTMASK (_BW(7)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(7)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK 0 -#define PB_GP_OUTMASK (_B(23)) -#define PB_SP_MASK 0 -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(23)) -#define PB_SP_DIRVAL 0 - -#define PC_GP_INMASK 0 -#define PC_GP_OUTMASK (_BW(15)) - -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL 0 -#define PC_SP_DIRVAL 0 - -#define PE_GP_INMASK 0 -#define PE_GP_OUTMASK 0 -#define PE_GP_OUTVAL 0 - -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - (void)ioport; - (void)cpm; -#if 1 - /* NAND chip select */ - upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB); - memctl->memc_mbmr = 0; /* all clear */ -#endif - - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - -#if 1 - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; -#endif - - return 0; -} - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return 0; -} - -int last_stage_init(void) -{ - reset_phys(); - - return 0; -} diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/stx/stxxtc/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug deleted file mode 100644 index a198cf9520..0000000000 --- a/board/stx/stxxtc/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig new file mode 100644 index 0000000000..4a2158988f --- /dev/null +++ b/board/sunxi/Kconfig @@ -0,0 +1,392 @@ +if ARCH_SUNXI + +choice + prompt "Sunxi SoC Variant" + +config MACH_SUN4I + bool "sun4i (Allwinner A10)" + select CPU_V7 + select SUPPORT_SPL + +config MACH_SUN5I + bool "sun5i (Allwinner A13)" + select CPU_V7 + select SUPPORT_SPL + +config MACH_SUN6I + bool "sun6i (Allwinner A31)" + select CPU_V7 + select SUPPORT_SPL + +config MACH_SUN7I + bool "sun7i (Allwinner A20)" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN8I + bool "sun8i (Allwinner A23)" + select CPU_V7 + select SUPPORT_SPL + +endchoice + +config DRAM_CLK + int "sunxi dram clock speed" + default 312 if MACH_SUN6I || MACH_SUN8I + default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + ---help--- + Set the dram clock speed, valid range 240 - 480, must be a multiple + of 24. + +if MACH_SUN5I || MACH_SUN7I +config DRAM_MBUS_CLK + int "sunxi mbus clock speed" + default 300 + ---help--- + Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. + +endif + +config DRAM_ZQ + int "sunxi dram zq value" + default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I + default 127 if MACH_SUN7I + ---help--- + Set the dram zq value. + +if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I +config DRAM_EMR1 + int "sunxi dram emr1 value" + default 0 if MACH_SUN4I + default 4 if MACH_SUN5I || MACH_SUN7I + ---help--- + Set the dram controller emr1 value. + +config DRAM_ODT_EN + int "sunxi dram odt_en value" + default 0 + ---help--- + Set the dram controller odt_en parameter. This can be used to + enable/disable the ODT feature. + +config DRAM_TPR3 + hex "sunxi dram tpr3 value" + default 0 + ---help--- + Set the dram controller tpr3 parameter. This parameter configures + the delay on the command lane and also phase shifts, which are + applied for sampling incoming read data. The default value 0 + means that no phase/delay adjustments are necessary. Properly + configuring this parameter increases reliability at high DRAM + clock speeds. + +config DRAM_DQS_GATING_DELAY + hex "sunxi dram dqs_gating_delay value" + default 0 + ---help--- + Set the dram controller dqs_gating_delay parmeter. Each byte + encodes the DQS gating delay for each byte lane. The delay + granularity is 1/4 cycle. For example, the value 0x05060606 + means that the delay is 5 quarter-cycles for one lane (1.25 + cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. + The default value 0 means autodetection. The results of hardware + autodetection are not very reliable and depend on the chip + temperature (sometimes producing different results on cold start + and warm reboot). But the accuracy of hardware autodetection + is usually good enough, unless running at really high DRAM + clocks speeds (up to 600MHz). If unsure, keep as 0. + +choice + prompt "sunxi dram timings" + default DRAM_TIMINGS_VENDOR_MAGIC + ---help--- + Select the timings of the DDR3 chips. + +config DRAM_TIMINGS_VENDOR_MAGIC + bool "Magic vendor timings from Android" + ---help--- + The same DRAM timings as in the Allwinner boot0 bootloader. + +config DRAM_TIMINGS_DDR3_1066F_1333H + bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" + ---help--- + Use the timings of the standard JEDEC DDR3-1066F speed bin for + DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin + for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips + used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 + or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm + that down binning to DDR3-1066F is supported (because DDR3-1066F + uses a bit faster timings than DDR3-1333H). + +config DRAM_TIMINGS_DDR3_800E_1066G_1333J + bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" + ---help--- + Use the timings of the slowest possible JEDEC speed bin for the + selected DRAM_CLK. Depending on the DRAM_CLK value, it may be + DDR3-800E, DDR3-1066G or DDR3-1333J. + +endchoice + +endif + +config SYS_CONFIG_NAME + default "sun4i" if MACH_SUN4I + default "sun5i" if MACH_SUN5I + default "sun6i" if MACH_SUN6I + default "sun7i" if MACH_SUN7I + default "sun8i" if MACH_SUN8I + +config SYS_BOARD + default "sunxi" + +config SYS_SOC + default "sunxi" + +config SPL_FEL + bool "SPL/FEL mode support" + depends on SPL + default n + +config UART0_PORT_F + bool "UART0 on MicroSD breakout board" + depends on SPL_FEL + default n + ---help--- + Repurpose the SD card slot for getting access to the UART0 serial + console. Primarily useful only for low level u-boot debugging on + tablets, where normal UART0 is difficult to access and requires + device disassembly and/or soldering. As the SD card can't be used + at the same time, the system can be only booted in the FEL mode. + Only enable this if you really know what you are doing. + +config FDTFILE + string "Default fdtfile env setting for this board" + +config OLD_SUNXI_KERNEL_COMPAT + boolean "Enable workarounds for booting old kernels" + default n + ---help--- + Set this to enable various workarounds for old kernels, this results in + sub-optimal settings for newer kernels, only enable if needed. + +config MMC0_CD_PIN + string "Card detect pin for mmc0" + default "" + ---help--- + Set the card detect pin for mmc0, leave empty to not use cd. This + takes a string in the format understood by sunxi_name_to_gpio, e.g. + PH1 for pin 1 of port H. + +config MMC1_CD_PIN + string "Card detect pin for mmc1" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC2_CD_PIN + string "Card detect pin for mmc2" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC3_CD_PIN + string "Card detect pin for mmc3" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC_SUNXI_SLOT_EXTRA + int "mmc extra slot number" + default -1 + ---help--- + sunxi builds always enable mmc0, some boards also have a second sdcard + slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable + support for this. + +config USB0_VBUS_PIN + string "Vbus enable pin for usb0 (otg)" + default "" + ---help--- + Set the Vbus enable pin for usb0 (otg). This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config USB1_VBUS_PIN + string "Vbus enable pin for usb1 (ehci0)" + default "PH6" if MACH_SUN4I || MACH_SUN7I + default "PH27" if MACH_SUN6I + ---help--- + Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes + a string in the format understood by sunxi_name_to_gpio, e.g. + PH1 for pin 1 of port H. + +config USB2_VBUS_PIN + string "Vbus enable pin for usb2 (ehci1)" + default "PH3" if MACH_SUN4I || MACH_SUN7I + default "PH24" if MACH_SUN6I + ---help--- + See USB1_VBUS_PIN help text. + +config VIDEO + boolean "Enable graphical uboot console on HDMI, LCD or VGA" + default y + ---help--- + Say Y here to add support for using a cfb console on the HDMI, LCD + or VGA output found on most sunxi devices. See doc/README.video for + info on how to select the video output and mode. + +config VIDEO_HDMI + boolean "HDMI output support" + depends on VIDEO && !MACH_SUN8I + default y + ---help--- + Say Y here to add support for outputting video over HDMI. + +config VIDEO_VGA + boolean "VGA output support" + depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) + default n + ---help--- + Say Y here to add support for outputting video over VGA. + +config VIDEO_VGA_VIA_LCD + boolean "VGA via LCD controller support" + depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) + default n + ---help--- + Say Y here to add support for external DACs connected to the parallel + LCD interface driving a VGA connector, such as found on the + Olimex A13 boards. + +config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH + boolean "Force sync active high for VGA via LCD controller support" + depends on VIDEO_VGA_VIA_LCD + default n + ---help--- + Say Y here if you've a board which uses opendrain drivers for the vga + hsync and vsync signals. Opendrain drivers cannot generate steep enough + positive edges for a stable video output, so on boards with opendrain + drivers the sync signals must always be active high. + +config VIDEO_VGA_EXTERNAL_DAC_EN + string "LCD panel power enable pin" + depends on VIDEO_VGA_VIA_LCD + default "" + ---help--- + Set the enable pin for the external VGA DAC. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_MODE + string "LCD panel timing details" + depends on VIDEO + default "" + ---help--- + LCD panel timing details string, leave empty if there is no LCD panel. + This is in drivers/video/videomodes.c: video_get_params() format, e.g. + x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 + +config VIDEO_LCD_DCLK_PHASE + int "LCD panel display clock phase" + depends on VIDEO + default 1 + ---help--- + Select LCD panel display clock phase shift, range 0-3. + +config VIDEO_LCD_POWER + string "LCD panel power enable pin" + depends on VIDEO + default "" + ---help--- + Set the power enable pin for the LCD panel. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_BL_EN + string "LCD panel backlight enable pin" + depends on VIDEO + default "" + ---help--- + Set the backlight enable pin for the LCD panel. This takes a string in the + the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of + port H. + +config VIDEO_LCD_BL_PWM + string "LCD panel backlight pwm pin" + depends on VIDEO + default "" + ---help--- + Set the backlight pwm pin for the LCD panel. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_BL_PWM_ACTIVE_LOW + bool "LCD panel backlight pwm is inverted" + depends on VIDEO + default y + ---help--- + Set this if the backlight pwm output is active low. + + +# Note only one of these may be selected at a time! But hidden choices are +# not supported by Kconfig +config VIDEO_LCD_IF_PARALLEL + bool + +config VIDEO_LCD_IF_LVDS + bool + + +choice + prompt "LCD panel support" + depends on VIDEO + ---help--- + Select which type of LCD panel to support. + +config VIDEO_LCD_PANEL_PARALLEL + bool "Generic parallel interface LCD panel" + select VIDEO_LCD_IF_PARALLEL + +config VIDEO_LCD_PANEL_LVDS + bool "Generic lvds interface LCD panel" + select VIDEO_LCD_IF_LVDS + +config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 + bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" + select VIDEO_LCD_SSD2828 + select VIDEO_LCD_IF_PARALLEL + ---help--- + 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 + +config VIDEO_LCD_PANEL_HITACHI_TX18D42VM + bool "Hitachi tx18d42vm LCD panel" + select VIDEO_LCD_HITACHI_TX18D42VM + select VIDEO_LCD_IF_LVDS + ---help--- + 7.85" 1024x768 Hitachi tx18d42vm LCD panel support + +endchoice + + +config USB_MUSB_SUNXI + bool "Enable sunxi OTG / DRC USB controller in host mode" + default n + ---help--- + Say y here to enable support for the sunxi OTG / DRC USB controller + used on almost all sunxi boards. Note currently u-boot can only have + one usb host controller enabled at a time, so enabling this on boards + which also use the ehci host controller will result in build errors. + +config USB_KEYBOARD + boolean "Enable USB keyboard support" + default y + ---help--- + Say Y here to add support for using a USB keyboard (typically used + in combination with a graphical console). + +config GMAC_TX_DELAY + int "GMAC Transmit Clock Delay Chain" + default 0 + ---help--- + Set the GMAC Transmit Clock Delay Chain value. + +endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS new file mode 100644 index 0000000000..faa413cb06 --- /dev/null +++ b/board/sunxi/MAINTAINERS @@ -0,0 +1,118 @@ +SUNXI BOARD +M: Hans de Goede +S: Maintained +F: board/sunxi/ +F: include/configs/sun4i.h +F: configs/A10-OLinuXino-Lime_defconfig +F: configs/ba10_tv_box_defconfig +F: configs/Chuwi_V7_CW0825_defconfig +F: configs/Cubieboard_defconfig +F: configs/Hyundai_A7HD_defconfig +F: configs/Mele_A1000_defconfig +F: configs/Mele_M3_defconfig +F: configs/Mini-X_defconfig +F: configs/mk802_defconfig +F: configs/mk802ii_defconfig +F: include/configs/sun5i.h +F: configs/A10s-OLinuXino-M_defconfig +F: configs/A13-OLinuXino_defconfig +F: configs/A13-OLinuXinoM_defconfig +F: configs/Auxtek-T004_defconfig +F: configs/mk802_a10s_defconfig +F: configs/r7-tv-dongle_defconfig +F: include/configs/sun6i.h +F: configs/CSQ_CS908_defconfig +F: configs/Mele_M9_defconfig +F: include/configs/sun7i.h +F: configs/A20-OLinuXino_MICRO_defconfig +F: configs/Bananapi_defconfig +F: configs/Bananapro_defconfig +F: configs/i12-tvbox_defconfig +F: configs/Linksprite_pcDuino3_defconfig +F: configs/Linksprite_pcDuino3_fdt_defconfig +F: configs/qt840a_defconfig +F: include/configs/sun8i.h +F: configs/Ippo_q8h_v1_2_defconfig + +A20-OLINUXINO-LIME BOARD +M: FUKAUMI Naoki +S: Maintained +F: board/sunxi/dram_a20_olinuxino_l.c +F: configs/A20-OLinuXino-Lime_defconfig + +A20-OLINUXINO-LIME2 BOARD +M: Iain Paton +S: Maintained +F: board/sunxi/dram_a20_olinuxino_l2.c +F: configs/A20-OLinuXino-Lime2_defconfig + +COLOMBUS BOARD +M: Maxime Ripard +S: Maintained +F: configs/Colombus_defconfig + +CUBIEBOARD2 BOARD +M: Ian Campbell +M: Hans de Goede +S: Maintained +F: include/configs/sun7i.h +F: configs/Cubieboard2_defconfig +F: configs/Cubieboard2_FEL_defconfig +F: configs/Cubietruck_defconfig +F: configs/Cubietruck_FEL_defconfig + +GEMEI-G9 TABLET +M: Priit Laes +S: Maintained +F: configs/sunxi_Gemei_G9_defconfig + +HUMMINGBIRD-A31 BOARD +M: Chen-Yu Tsai +S: Maintained +F: configs/Hummingbird_A31_defconfig + +INET-86VS BOARD +M: Michal Suchanek +S: Maintained +F: board/sunxi/dram_inet_86vs.c +F: configs/Inet_86VS_defconfig + +IPPO-Q8H-V5 BOARD +M: Chen-Yu Tsai +S: Maintained +F: configs/Ippo_q8h_v5_defconfig + +LINKSPRITE-PCDUINO BOARD +M: Zoltan Herpai +S: Maintained +F: configs/Linksprite_pcDuino_defconfig + +LINKSPRITE-PCDUINO3-NANO BOARD +M: Adam Sampson +S: Maintained +F: configs/Linksprite_pcDuino3_Nano_defconfig + +MARSBOARD-A10 BOARD +M: Aleksei Mamlin +S: Maintained +F: configs/Marsboard_A10_defconfig + +MELE M5 BOARD +M: Ian Campbell +S: Maintained +F: configs/Mele_M5_defconfig + +MSI-PRIMO73 BOARD +M: Siarhei Siamashka +S: Maintained +F: configs/MSI_Primo73_defconfig + +MSI-PRIMO81 BOARD +M: Siarhei Siamashka +S: Maintained +F: configs/MSI_Primo81_defconfig + +TZX-Q8-713B7 BOARD +M: Paul Kocialkowski +S: Maintained +F: configs/TZX-Q8-713B7_defconfig diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile new file mode 100644 index 0000000000..43766e0ef4 --- /dev/null +++ b/board/sunxi/Makefile @@ -0,0 +1,16 @@ +# +# (C) Copyright 2012 Henrik Nordstrom +# +# Based on some other board Makefile +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += board.o +obj-$(CONFIG_SUNXI_GMAC) += gmac.o +obj-$(CONFIG_SUNXI_AHCI) += ahci.o +obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o +obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o +obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c new file mode 100644 index 0000000000..b7f0dda205 --- /dev/null +++ b/board/sunxi/ahci.c @@ -0,0 +1,87 @@ +#include +#include +#include +#include +#include +#include + +#define AHCI_PHYCS0R 0x00c0 +#define AHCI_PHYCS1R 0x00c4 +#define AHCI_PHYCS2R 0x00c8 +#define AHCI_RWCR 0x00fc + +/* This magic PHY initialisation was taken from the Allwinner releases + * and Linux driver, but is completely undocumented. + */ +static int sunxi_ahci_phy_init(u32 base) +{ + u8 *reg_base = (u8 *)base; + u32 reg_val; + int timeout; + + writel(0, reg_base + AHCI_RWCR); + mdelay(5); + + setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); + clrsetbits_le32(reg_base + AHCI_PHYCS0R, + (0x7 << 24), + (0x5 << 24) | (0x1 << 23) | (0x1 << 18)); + clrsetbits_le32(reg_base + AHCI_PHYCS1R, + (0x3 << 16) | (0x1f << 8) | (0x3 << 6), + (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); + setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); + clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); + clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); + clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); + mdelay(5); + + setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); + + timeout = 250; /* Power up takes approx 50 us */ + for (;;) { + reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); + if (reg_val == (0x2 << 28)) + break; + if (--timeout == 0) { + printf("AHCI PHY power up failed.\n"); + return -EIO; + } + udelay(1); + }; + + setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); + + timeout = 100; /* Calibration takes approx 10 us */ + for (;;) { + reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); + if (reg_val == 0x0) + break; + if (--timeout == 0) { + printf("AHCI PHY calibration failed.\n"); + return -EIO; + } + udelay(1); + } + + mdelay(15); + + writel(0x7, reg_base + AHCI_RWCR); + + return 0; +} + +void scsi_init(void) +{ + printf("SUNXI SCSI INIT\n"); +#ifdef CONFIG_SATAPWR + gpio_request(CONFIG_SATAPWR, "satapwr"); + gpio_direction_output(CONFIG_SATAPWR, 1); + /* Give attached sata device time to power-up to avoid link timeouts */ + mdelay(500); +#endif + + if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0) + return; + + ahci_init(SUNXI_SATA_BASE); +} diff --git a/board/sunxi/board.c b/board/sunxi/board.c new file mode 100644 index 0000000000..b70e00ce6b --- /dev/null +++ b/board/sunxi/board.c @@ -0,0 +1,267 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Some board init for the Allwinner A10-evb board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#ifdef CONFIG_AXP152_POWER +#include +#endif +#ifdef CONFIG_AXP209_POWER +#include +#endif +#ifdef CONFIG_AXP221_POWER +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* add board specific code here */ +int board_init(void) +{ + int id_pfr1; + + gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); + + asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); + debug("id_pfr1: 0x%08x\n", id_pfr1); + /* Generic Timer Extension available? */ + if ((id_pfr1 >> 16) & 0xf) { + debug("Setting CNTFRQ\n"); + /* CNTFRQ == 24 MHz */ + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); + } + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); + + return 0; +} + +#ifdef CONFIG_GENERIC_MMC +static void mmc_pinmux_setup(int sdc) +{ + unsigned int pin; + + switch (sdc) { + case 0: + /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */ + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 1: + /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */ + for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 2: + /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 3: + /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */ + for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + default: + printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); + break; + } +} + +int board_mmc_init(bd_t *bis) +{ + __maybe_unused struct mmc *mmc0, *mmc1; + __maybe_unused char buf[512]; + + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); + mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); + if (!mmc0) + return -1; + +#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); + mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); + if (!mmc1) + return -1; +#endif + +#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 + /* + * Both mmc0 and mmc2 are bootable, figure out where we're booting + * from. Try mmc0 first, just like the brom does. + */ + if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && + mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { + buf[12] = 0; + if (strcmp(&buf[4], "eGON.BT0") == 0) + return 0; + } + + /* no bootable card in mmc0, so we must be booting from mmc2, swap */ + mmc0->block_dev.dev = 1; + mmc1->block_dev.dev = 0; +#endif + + return 0; +} +#endif + +void i2c_init_board(void) +{ + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0); + clock_twi_onoff(0, 1); +} + +#ifdef CONFIG_SPL_BUILD +void sunxi_board_init(void) +{ + int power_failed = 0; + unsigned long ramsize; + +#ifdef CONFIG_AXP152_POWER + power_failed = axp152_init(); + power_failed |= axp152_set_dcdc2(1400); + power_failed |= axp152_set_dcdc3(1500); + power_failed |= axp152_set_dcdc4(1250); + power_failed |= axp152_set_ldo2(3000); +#endif +#ifdef CONFIG_AXP209_POWER + power_failed |= axp209_init(); + power_failed |= axp209_set_dcdc2(1400); + power_failed |= axp209_set_dcdc3(1250); + power_failed |= axp209_set_ldo2(3000); + power_failed |= axp209_set_ldo3(2800); + power_failed |= axp209_set_ldo4(2800); +#endif +#ifdef CONFIG_AXP221_POWER + power_failed = axp221_init(); + power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); + power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */ + power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ +#ifdef CONFIG_MACH_SUN6I + power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ +#else + power_failed |= axp221_set_dcdc4(0); /* A23:unused */ +#endif + power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ + power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); + power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); + power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); + power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); + power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); + power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); +#endif + + printf("DRAM:"); + ramsize = sunxi_dram_init(); + printf(" %lu MiB\n", ramsize >> 20); + if (!ramsize) + hang(); + + /* + * Only clock up the CPU to full speed if we are reasonably + * assured it's being powered with suitable core voltage + */ + if (!power_failed) + clock_set_pll1(CONFIG_CLK_FULL_SPEED); + else + printf("Failed to set core voltage! Can't set CPU frequency\n"); +} +#endif + +#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 6, + .ram_bits = 11, +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_MUSB_HOST) + .mode = MUSB_HOST, +#else + .mode = MUSB_PERIPHERAL, +#endif + .config = &musb_config, + .power = 250, + .platform_ops = &sunxi_musb_ops, +}; +#endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + unsigned int sid[4]; + + if (!getenv("ethaddr") && sunxi_get_sid(sid) == 0 && + sid[0] != 0 && sid[3] != 0) { + uint8_t mac_addr[6]; + + mac_addr[0] = 0x02; /* Non OUI / registered MAC address */ + mac_addr[1] = (sid[0] >> 0) & 0xff; + mac_addr[2] = (sid[3] >> 24) & 0xff; + mac_addr[3] = (sid[3] >> 16) & 0xff; + mac_addr[4] = (sid[3] >> 8) & 0xff; + mac_addr[5] = (sid[3] >> 0) & 0xff; + + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) + musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); +#endif + return 0; +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_VIDEO_DT_SIMPLEFB + return sunxi_simplefb_setup(blob); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c new file mode 100644 index 0000000000..09e0c9ae2e --- /dev/null +++ b/board/sunxi/dram_sun4i_auto.c @@ -0,0 +1,35 @@ +#include +#include + +static struct dram_para dram_para = { + .clock = CONFIG_DRAM_CLK, + .type = 3, + .rank_num = 1, + .density = 0, + .io_width = 0, + .bus_width = 0, + .zq = CONFIG_DRAM_ZQ, + .odt_en = CONFIG_DRAM_ODT_EN, + .size = 0, +#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC + .cas = 6, + .tpr0 = 0x30926692, + .tpr1 = 0x1090, + .tpr2 = 0x1a0c8, + .emr2 = 0, +#else +# include "dram_timings_sun4i.h" + .active_windowing = 1, +#endif + .tpr3 = CONFIG_DRAM_TPR3, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = CONFIG_DRAM_EMR1, + .emr3 = 0, + .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c new file mode 100644 index 0000000000..e52d54c32e --- /dev/null +++ b/board/sunxi/dram_sun5i_auto.c @@ -0,0 +1,38 @@ +/* DRAM parameters for auto dram configuration on sun5i and sun7i */ + +#include +#include + +static struct dram_para dram_para = { + .clock = CONFIG_DRAM_CLK, + .mbus_clock = CONFIG_DRAM_MBUS_CLK, + .type = 3, + .rank_num = 1, + .density = 0, + .io_width = 0, + .bus_width = 0, + .zq = CONFIG_DRAM_ZQ, + .odt_en = CONFIG_DRAM_ODT_EN, + .size = 0, +#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC + .cas = 9, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .emr2 = 0x10, +#else +# include "dram_timings_sun4i.h" + .active_windowing = 1, +#endif + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = CONFIG_DRAM_EMR1, + .emr3 = 0, + .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_timings_sun4i.h b/board/sunxi/dram_timings_sun4i.h new file mode 100644 index 0000000000..29b934da63 --- /dev/null +++ b/board/sunxi/dram_timings_sun4i.h @@ -0,0 +1,205 @@ +/* This file is automatically generated, do not edit */ + +#if defined(CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H) +# if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */ + .cas = 6, + .tpr0 = 0x268e5590, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x288f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */ + .cas = 7, + .tpr0 = 0x2ab06690, + .tpr1 = 0xa0a8, + .tpr2 = 0x22a00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */ + .cas = 7, + .tpr0 = 0x2cb16690, + .tpr1 = 0xa0b0, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */ + .cas = 7, + .tpr0 = 0x30b26690, + .tpr1 = 0xa0b8, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */ + .cas = 7, + .tpr0 = 0x30b27790, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */ + .cas = 7, + .tpr0 = 0x32b27790, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */ + .cas = 7, + .tpr0 = 0x34d37790, + .tpr1 = 0xa0d0, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */ + .cas = 7, + .tpr0 = 0x36d47790, + .tpr1 = 0xa0d8, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */ + .cas = 9, + .tpr0 = 0x36b488b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2b600, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */ + .cas = 9, + .tpr0 = 0x38b488b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */ + .cas = 9, + .tpr0 = 0x3ab588b4, + .tpr1 = 0xa0d0, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */ + .cas = 9, + .tpr0 = 0x3cb699b4, + .tpr1 = 0xa0d8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */ + .cas = 9, + .tpr0 = 0x3eb799b4, + .tpr1 = 0xa0e8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333H @648MHz, timings: 9-9-9-24 */ + .cas = 9, + .tpr0 = 0x42b899b4, + .tpr1 = 0xa0f0, + .tpr2 = 0x2c200, + .emr2 = 0x10, +# else +# error CONFIG_DRAM_CLK is set too high +# endif +#elif defined(CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J) +# if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */ + .cas = 6, + .tpr0 = 0x268e6690, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 384 /* DDR3-800E @384MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 396 /* DDR3-800E @396MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */ + .cas = 8, + .tpr0 = 0x2cb07790, + .tpr1 = 0xa0a8, + .tpr2 = 0x22a00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066G @432MHz, timings: 8-7-7-17 */ + .cas = 8, + .tpr0 = 0x2eb17790, + .tpr1 = 0xa0b0, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066G @456MHz, timings: 8-7-7-18 */ + .cas = 8, + .tpr0 = 0x30b27790, + .tpr1 = 0xa0b8, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066G @468MHz, timings: 8-8-8-18 */ + .cas = 8, + .tpr0 = 0x32b28890, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066G @480MHz, timings: 8-8-8-18 */ + .cas = 8, + .tpr0 = 0x34b28890, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066G @504MHz, timings: 8-8-8-19 */ + .cas = 8, + .tpr0 = 0x36d38890, + .tpr1 = 0xa0d0, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066G @528MHz, timings: 8-8-8-20 */ + .cas = 8, + .tpr0 = 0x38d48890, + .tpr1 = 0xa0d8, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333J @540MHz, timings: 10-9-9-20 */ + .cas = 10, + .tpr0 = 0x38b499b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2b600, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333J @552MHz, timings: 10-9-9-20 */ + .cas = 10, + .tpr0 = 0x3ab499b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333J @576MHz, timings: 10-9-9-21 */ + .cas = 10, + .tpr0 = 0x3cb599b4, + .tpr1 = 0xa0d0, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333J @600MHz, timings: 10-9-9-22 */ + .cas = 10, + .tpr0 = 0x3eb699b4, + .tpr1 = 0xa0d8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333J @624MHz, timings: 10-10-10-23 */ + .cas = 10, + .tpr0 = 0x40b7aab4, + .tpr1 = 0xa0e8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333J @648MHz, timings: 10-10-10-24 */ + .cas = 10, + .tpr0 = 0x44b8aab4, + .tpr1 = 0xa0f0, + .tpr2 = 0x2c200, + .emr2 = 0x10, +# else +# error CONFIG_DRAM_CLK is set too high +# endif +#else +# error CONFIG_DRAM_TIMINGS_* is not defined +#endif diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c new file mode 100644 index 0000000000..8849132627 --- /dev/null +++ b/board/sunxi/gmac.c @@ -0,0 +1,90 @@ +#include +#include +#include +#include +#include +#include +#include + +int sunxi_gmac_initialize(bd_t *bis) +{ + int pin; + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set up clock gating */ +#ifndef CONFIG_MACH_SUN6I + setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); +#else + setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); +#endif + + /* Set MII clock */ +#ifdef CONFIG_RGMII + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + CCM_GMAC_CTRL_GPIT_RGMII); + setbits_le32(&ccm->gmac_clk_cfg, + CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); +#else + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | + CCM_GMAC_CTRL_GPIT_MII); +#endif + +#ifndef CONFIG_MACH_SUN6I + /* Configure pin mux settings for GMAC */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { +#ifdef CONFIG_RGMII + /* skip unused pins in RGMII mode */ + if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) + continue; +#endif + sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } +#elif defined CONFIG_RGMII + /* Configure sun6i RGMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } +#elif defined CONFIG_GMII + /* Configure sun6i GMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 2); + } +#else + /* Configure sun6i MII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); +#endif + +#ifdef CONFIG_RGMII + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); +#elif defined CONFIG_GMII + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII); +#else + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); +#endif +} diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile deleted file mode 100644 index 871865b6ee..0000000000 --- a/board/svm_sc8xx/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c deleted file mode 100644 index 8a04de80b3..0000000000 --- a/board/svm_sc8xx/flash.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t *info, ulong dest, ulong data); - -#ifdef CONFIG_BOOT_8B -static int my_in_8(unsigned char *addr); -static void my_out_8(unsigned char *addr, int val); -#endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16(unsigned short *addr); -static void my_out_be16(unsigned short *addr, int val); -#endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32(unsigned *addr); -static void my_out_be32(unsigned *addr, int val); -#endif -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - size_b0 = 0; - size_b1 = 0; - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - -#ifdef CONFIG_SYS_DOC_BASE -#ifndef CONFIG_FEL8xx_AT - /* 32k bytes */ - memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); - memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401; -#else - /* 32k bytes */ - memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); - memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401; -#endif -#endif -#if defined(CONFIG_BOOT_8B) - size_b0 = 0x80000; /* 512 K */ - - flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040; - flash_info[0].sector_count = 8; - flash_info[0].size = 0x00080000; - - /* set up sector start address table */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + (i * 0x10000); - - /* protect all sectors */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; - -#elif defined(CONFIG_BOOT_16B) - size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ - - flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B; - flash_info[0].sector_count = 67; - flash_info[0].size = 0x00400000; - - /* set up sector start address table */ - flash_info[0].start[0] = 0x40000000; - flash_info[0].start[1] = 0x40000000 + 0x4000; - flash_info[0].start[2] = 0x40000000 + 0x6000; - flash_info[0].start[3] = 0x40000000 + 0x8000; - - for (i = 4; i < flash_info[0].sector_count; i++) { - flash_info[0].start[i] = - 0x40000000 + 0x10000 + ((i - 4) * 0x10000); - } - - /* protect all sectors */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; -#endif - -#ifdef CONFIG_BOOT_32B - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, - &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - size_b1 = flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - if (size_b1 > size_b0) { - printf("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1 << 20, size_b0, size_b0 << 20); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - - return 0; - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | - (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | - (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + - size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + - size_b0), &flash_info[1]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE + size_b0, - &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - -#endif /* CONFIG_BOOT_32B */ - - return size_b0 + size_b1; -} - - -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *) (info->start[0]); - int flag, prot, sect, l_sect, in_mid, in_did; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if defined(CONFIG_BOOT_8B) - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0x90); - - in_mid = my_in_8((unsigned char *)addr); - in_did = my_in_8((unsigned char *)((ulong)addr + 1)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_8((unsigned char *)addr, 0xf0); - udelay(1); - - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0x80); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - /*addr[0] = 0x00300030; */ - my_out_8((unsigned char *)((ulong)addr), 0x30); - l_sect = sect; - } - } -#elif defined(CONFIG_BOOT_16B) - my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + (0x554)), 0x55); - my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0x90); - in_mid = my_in_be16((unsigned short *)addr); - in_did = my_in_be16((unsigned short *)((ulong)addr + 2)); - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - my_out_be16((unsigned short *)addr, 0xf0); - udelay(1); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0x80); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - my_out_be16((unsigned short *)((ulong)addr), 0x30); - l_sect = sect; - } - } - -#elif defined(CONFIG_BOOT_32B) - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x90); - - in_mid = my_in_be32((unsigned *)addr); - in_did = my_in_be32((unsigned *)((ulong)addr + 4)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_be32((unsigned *) addr, 0xf0); - udelay(1); - - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x80); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - my_out_be32((unsigned *)((ulong)addr), 0x00300030); - l_sect = sect; - } - } - -#else -#error CONFIG_BOOT_(size)B missing. -#endif - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_long *) (info->start[l_sect]); -#if defined(CONFIG_BOOT_8B) - while ((my_in_8((unsigned char *) addr) & 0x80) != 0x80) -#elif defined(CONFIG_BOOT_16B) - while ((my_in_be16((unsigned short *) addr) & 0x0080) != 0x0080) -#elif defined(CONFIG_BOOT_32B) - while ((my_in_be32((unsigned *) addr) & 0x00800080) != 0x00800080) -#else -#error CONFIG_BOOT_(size)B missing. -#endif - { - now = get_timer(start); - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *) info->start[0]; - -#if defined(CONFIG_BOOT_8B) - my_out_8((unsigned char *) addr, 0xf0); -#elif defined(CONFIG_BOOT_16B) - my_out_be16((unsigned short *) addr, 0x00f0); -#elif defined(CONFIG_BOOT_32B) - my_out_be32((unsigned *) addr, 0x00F000F0); /* reset bank */ -#else -#error CONFIG_BOOT_(size)B missing. -#endif - printf(" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return write_word(info, wp, data); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - ulong addr = (ulong) (info->start[0]); - ulong start; - int flag; - ulong i; - int data_short[2]; - - /* Check if Flash is (sufficiently) erased */ - if (((ulong)*(ulong *)dest & data) != data) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#if defined(CONFIG_BOOT_8B) -#ifdef DEBUG - { - int in_mid, in_did; - - my_out_8((unsigned char *) (addr + 0x555), 0xaa); - my_out_8((unsigned char *) (addr + 0x2aa), 0x55); - my_out_8((unsigned char *) (addr + 0x555), 0x90); - - in_mid = my_in_8((unsigned char *) addr); - in_did = my_in_8((unsigned char *) (addr + 1)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_8((unsigned char *) addr, 0xf0); - udelay(1); - } -#endif - { - int data_ch[4]; - - data_ch[0] = (int) ((data >> 24) & 0xff); - data_ch[1] = (int) ((data >> 16) & 0xff); - data_ch[2] = (int) ((data >> 8) & 0xff); - data_ch[3] = (int) (data & 0xff); - - for (i = 0; i < 4; i++) { - my_out_8((unsigned char *) (addr + 0x555), 0xaa); - my_out_8((unsigned char *) (addr + 0x2aa), 0x55); - my_out_8((unsigned char *) (addr + 0x555), 0xa0); - my_out_8((unsigned char *) (dest + i), data_ch[i]); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - while ((my_in_8((unsigned char *)(dest + i))) != - (data_ch[i])) { - if (get_timer(start) > - CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } /* for */ - } -#elif defined(CONFIG_BOOT_16B) - data_short[0] = (int) (data >> 16) & 0xffff; - data_short[1] = (int) data & 0xffff; - for (i = 0; i < 2; i++) { - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xa0); - my_out_be16((unsigned short *)(dest + (i * 2)), - data_short[i]); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - while ((my_in_be16((unsigned short *)(dest + (i * 2)))) != - (data_short[i])) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - } -#elif defined(CONFIG_BOOT_32B) - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } -#endif - return 0; -} - -#ifdef CONFIG_BOOT_8B -static int my_in_8(unsigned char *addr) -{ - int ret; - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_8(unsigned char *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16(unsigned short *addr) -{ - int ret; - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_be16(unsigned short *addr, int val) -{ - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32(unsigned *addr) -{ - unsigned ret; - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_be32(unsigned *addr, int val) -{ - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c deleted file mode 100644 index a508595abf..0000000000 --- a/board/svm_sc8xx/svm_sc8xx.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ -const uint sdram_table[] = -{ -/*----------------- - UPM A contents: ------------------ */ -/*--------------------------------------------------- - Read Single Beat Cycle. Offset 0 in the RAM array. ----------------------------------------------------- */ -0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 , -0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 , -/*------------------------------------------------ - Read Burst Cycle. Offset 0x8 in the RAM array. ------------------------------------------------- */ -0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, -0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, -/*------------------------------------------------------- - Write Single Beat Cycle. Offset 0x18 in the RAM array -------------------------------------------------------- */ -0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 , -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*------------------------------------------------- - Write Burst Cycle. Offset 0x20 in the RAM array -------------------------------------------------- */ -0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, -0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*------------------------------------------------------------------------ - Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array ------------------------------------------------------------------------- */ -0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, -0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*----------- -* Exception: -* ----------- */ -0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff , -}; - -/* ------------------------------------------------------------------------- */ -/* - * Check Board Identity: - * - * Test ID string (SVM8...) - * - * Return 1 for "SC8xx" type, 0 else. - */ - -int checkboard(void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - if (l < 0 || strncmp(buf, "SVM8", 4)) { - printf("### No HW ID - assuming SVM SC8xx\n"); - return (0); - } - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - - putc('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#if defined (CONFIG_SDRAM_16M) - memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xff000a00; - size_b0 = 0x01000000; -#elif defined (CONFIG_SDRAM_32M) - memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xfe000a00; - size_b0 = 0x02000000; -#elif defined (CONFIG_SDRAM_64M) - memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xfc000a00; - size_b0 = 0x04000000; -#else -#error SDRAM size configuration missing. -#endif - memctl->memc_br1 = 0x00000081; - udelay(200); - return (size_b0 ); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds deleted file mode 100644 index 49226251b2..0000000000 --- a/board/svm_sc8xx/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/libgeneric.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) - board/svm_sc8xx/libsvm_sc8xx.o (.text*) - *(.text.*printf) - *(.text.do_mem_*) - *(.text.flash*) - *(.text.run_command) - *(.text.main_loop) - *(.text.srec_decode) - - . = env_offset; - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug deleted file mode 100644 index b2c562c33d..0000000000 --- a/board/svm_sc8xx/u-boot.lds.debug +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/synopsys/Kconfig b/board/synopsys/Kconfig new file mode 100644 index 0000000000..f614f88cc6 --- /dev/null +++ b/board/synopsys/Kconfig @@ -0,0 +1,19 @@ +if TARGET_ARCANGEL4 + +config SYS_VENDOR + default "synopsys" + +config SYS_CONFIG_NAME + default "arcangel4" + +endif + +if TARGET_ARCANGEL4_BE + +config SYS_VENDOR + default "synopsys" + +config SYS_CONFIG_NAME + default "arcangel4-be" + +endif diff --git a/board/synopsys/MAINTAINERS b/board/synopsys/MAINTAINERS new file mode 100644 index 0000000000..720edd8893 --- /dev/null +++ b/board/synopsys/MAINTAINERS @@ -0,0 +1,7 @@ +- BOARD +M: Alexey Brodkin +S: Maintained +F: include/configs/arcangel4.h +F: configs/arcangel4_defconfig +F: include/configs/arcangel4-be.h +F: configs/arcangel4-be_defconfig diff --git a/board/synopsys/axs101/Kconfig b/board/synopsys/axs101/Kconfig new file mode 100644 index 0000000000..79e5400ea8 --- /dev/null +++ b/board/synopsys/axs101/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AXS101 + +config SYS_BOARD + default "axs101" + +config SYS_VENDOR + default "synopsys" + +config SYS_CONFIG_NAME + default "axs101" + +endif diff --git a/board/synopsys/axs101/MAINTAINERS b/board/synopsys/axs101/MAINTAINERS new file mode 100644 index 0000000000..481bbcc207 --- /dev/null +++ b/board/synopsys/axs101/MAINTAINERS @@ -0,0 +1,6 @@ +AXS101 BOARD +M: Alexey Brodkin +S: Maintained +F: board/synopsys/axs101/ +F: include/configs/axs101.h +F: configs/axs101_defconfig diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile new file mode 100644 index 0000000000..f0965f7841 --- /dev/null +++ b/board/synopsys/axs101/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += axs101.o +obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c new file mode 100644 index 0000000000..d1271ffcca --- /dev/null +++ b/board/synopsys/axs101/axs101.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_mmc_init(bd_t *bis) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + memset(host, 0, sizeof(struct dwmci_host)); + host->name = "Synopsys Mobile storage"; + host->ioaddr = (void *)ARC_DWMMC_BASE; + host->buswidth = 4; + host->dev_index = 0; + host->bus_hz = 25000000; + + add_dwmci(host, 52000000, 400000); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + if (designware_initialize(ARC_DWGMAC_BASE, + PHY_INTERFACE_MODE_RGMII) >= 0) + return 1; + + return 0; +} diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c new file mode 100644 index 0000000000..ff35286c6e --- /dev/null +++ b/board/synopsys/axs101/nand.c @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define BUS_WIDTH 8 /* AXI data bus width in bytes */ + +/* DMA buffer descriptor bits & masks */ +#define BD_STAT_OWN (1 << 31) +#define BD_STAT_BD_FIRST (1 << 3) +#define BD_STAT_BD_LAST (1 << 2) +#define BD_SIZES_BUFFER1_MASK 0xfff + +#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST) + +/* Controller command flags */ +#define B_WFR (1 << 19) /* 1b - Wait for ready */ +#define B_LC (1 << 18) /* 1b - Last cycle */ +#define B_IWC (1 << 13) /* 1b - Interrupt when complete */ + +/* NAND cycle types */ +#define B_CT_ADDRESS (0x0 << 16) /* Address operation */ +#define B_CT_COMMAND (0x1 << 16) /* Command operation */ +#define B_CT_WRITE (0x2 << 16) /* Write operation */ +#define B_CT_READ (0x3 << 16) /* Write operation */ + +enum nand_isr_t { + NAND_ISR_DATAREQUIRED = 0, + NAND_ISR_TXUNDERFLOW, + NAND_ISR_TXOVERFLOW, + NAND_ISR_DATAAVAILABLE, + NAND_ISR_RXUNDERFLOW, + NAND_ISR_RXOVERFLOW, + NAND_ISR_TXDMACOMPLETE, + NAND_ISR_RXDMACOMPLETE, + NAND_ISR_DESCRIPTORUNAVAILABLE, + NAND_ISR_CMDDONE, + NAND_ISR_CMDAVAILABLE, + NAND_ISR_CMDERROR, + NAND_ISR_DATATRANSFEROVER, + NAND_ISR_NONE +}; + +enum nand_regs_t { + AC_FIFO = 0, /* address and command fifo */ + IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */ + INT_STATUS = 0x118, /* interrupt status register */ + INT_CLR_STATUS = 0x120, /* interrupt clear status register */ +}; + +struct nand_bd { + uint32_t status; /* DES0 */ + uint32_t sizes; /* DES1 */ + uint32_t buffer_ptr0; /* DES2 */ + uint32_t buffer_ptr1; /* DES3 */ +}; + +#define NAND_REG_WRITE(r, v) \ + writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r)) +#define NAND_REG_READ(r) \ + readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r)) + +static struct nand_bd *bd; /* DMA buffer descriptors */ + +/** + * axs101_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static uint32_t nand_flag_is_set(uint32_t flag) +{ + uint32_t reg = NAND_REG_READ(INT_STATUS); + + if (reg & (1 << NAND_ISR_CMDERROR)) + return 0; + + if (reg & (1 << flag)) { + NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag); + return 1; + } + + return 0; +} + +/** + * axs101_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + struct bounce_buffer bbstate; + + bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ); + + /* Setup buffer descriptor */ + writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); + writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); + writel(bbstate.bounce_buffer, &bd->buffer_ptr0); + writel(0, &bd->buffer_ptr1); + + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)bd, + (unsigned long)bd + sizeof(struct nand_bd)); + + /* Issue "write" command */ + NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1)); + + /* Wait for NAND command and DMA to complete */ + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; + while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE)) + ; + + bounce_buffer_stop(&bbstate); +} + +/** + * axs101_nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store data + * @len: number of bytes to read + */ +static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct bounce_buffer bbstate; + + bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE); + + /* Setup buffer descriptor */ + writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); + writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); + writel(bbstate.bounce_buffer, &bd->buffer_ptr0); + writel(0, &bd->buffer_ptr1); + + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)bd, + (unsigned long)bd + sizeof(struct nand_bd)); + + /* Issue "read" command */ + NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1)); + + /* Wait for NAND command and DMA to complete */ + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; + while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE)) + ; + + bounce_buffer_stop(&bbstate); +} + +/** + * axs101_nand_read_byte - read one byte from the chip + * @mtd: MTD device structure + */ +static u_char axs101_nand_read_byte(struct mtd_info *mtd) +{ + u8 byte; + + axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); + return byte; +} + +/** + * axs101_nand_read_word - read one word from the chip + * @mtd: MTD device structure + */ +static u16 axs101_nand_read_word(struct mtd_info *mtd) +{ + u16 word; + + axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); + return word; +} + +/** + * axs101_nand_hwcontrol - NAND control functions wrapper. + * @mtd: MTD device structure + * @cmd: Command + */ +static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, + unsigned int ctrl) +{ + if (cmd == NAND_CMD_NONE) + return; + + cmd = cmd & 0xff; + + switch (ctrl & (NAND_ALE | NAND_CLE)) { + /* Address */ + case NAND_ALE: + cmd |= B_CT_ADDRESS; + break; + + /* Command */ + case NAND_CLE: + cmd |= B_CT_COMMAND | B_WFR; + + break; + + default: + debug("%s: unknown ctrl %#x\n", __func__, ctrl); + } + + NAND_REG_WRITE(AC_FIFO, cmd | B_LC); + while (!nand_flag_is_set(NAND_ISR_CMDDONE)) + ; +} + +int board_nand_init(struct nand_chip *nand) +{ + bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN, + sizeof(struct nand_bd)); + + /* Set buffer descriptor address in IDMAC */ + NAND_REG_WRITE(IDMAC_BDADDR, bd); + + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = axs101_nand_hwcontrol; + nand->read_byte = axs101_nand_read_byte; + nand->read_word = axs101_nand_read_word; + nand->write_buf = axs101_nand_write_buf; + nand->read_buf = axs101_nand_read_buf; + + return 0; +} diff --git a/board/syteco/jadecpu/Kconfig b/board/syteco/jadecpu/Kconfig new file mode 100644 index 0000000000..6e9392e21f --- /dev/null +++ b/board/syteco/jadecpu/Kconfig @@ -0,0 +1,15 @@ +if TARGET_JADECPU + +config SYS_BOARD + default "jadecpu" + +config SYS_VENDOR + default "syteco" + +config SYS_SOC + default "mb86r0x" + +config SYS_CONFIG_NAME + default "jadecpu" + +endif diff --git a/board/syteco/jadecpu/MAINTAINERS b/board/syteco/jadecpu/MAINTAINERS new file mode 100644 index 0000000000..b53e7cad42 --- /dev/null +++ b/board/syteco/jadecpu/MAINTAINERS @@ -0,0 +1,6 @@ +JADECPU BOARD +M: Matthias Weisser +S: Maintained +F: board/syteco/jadecpu/ +F: include/configs/jadecpu.h +F: configs/jadecpu_defconfig diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile index 8e96c5e44a..74264361e5 100644 --- a/board/syteco/jadecpu/Makefile +++ b/board/syteco/jadecpu/Makefile @@ -9,25 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += jadecpu.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += jadecpu.o +obj-y += lowlevel_init.o diff --git a/board/syteco/zmx25/Kconfig b/board/syteco/zmx25/Kconfig new file mode 100644 index 0000000000..59a415d65f --- /dev/null +++ b/board/syteco/zmx25/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ZMX25 + +config SYS_BOARD + default "zmx25" + +config SYS_VENDOR + default "syteco" + +config SYS_SOC + default "mx25" + +config SYS_CONFIG_NAME + default "zmx25" + +endif diff --git a/board/syteco/zmx25/MAINTAINERS b/board/syteco/zmx25/MAINTAINERS new file mode 100644 index 0000000000..90f9fab7b8 --- /dev/null +++ b/board/syteco/zmx25/MAINTAINERS @@ -0,0 +1,6 @@ +ZMX25 BOARD +M: Matthias Weisser +S: Maintained +F: board/syteco/zmx25/ +F: include/configs/zmx25.h +F: configs/zmx25_defconfig diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile index 8c289bde30..d5edb48ab8 100644 --- a/board/syteco/zmx25/Makefile +++ b/board/syteco/zmx25/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += zmx25.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += zmx25.o +obj-y += lowlevel_init.o diff --git a/board/t3corp/Kconfig b/board/t3corp/Kconfig new file mode 100644 index 0000000000..82ed4c95b8 --- /dev/null +++ b/board/t3corp/Kconfig @@ -0,0 +1,9 @@ +if TARGET_T3CORP + +config SYS_BOARD + default "t3corp" + +config SYS_CONFIG_NAME + default "t3corp" + +endif diff --git a/board/t3corp/MAINTAINERS b/board/t3corp/MAINTAINERS new file mode 100644 index 0000000000..eaf28c4a9d --- /dev/null +++ b/board/t3corp/MAINTAINERS @@ -0,0 +1,6 @@ +T3CORP BOARD +M: Stefan Roese +S: Maintained +F: board/t3corp/ +F: include/configs/t3corp.h +F: configs/t3corp_defconfig diff --git a/board/t3corp/Makefile b/board/t3corp/Makefile index 093457f591..928d895d50 100644 --- a/board/t3corp/Makefile +++ b/board/t3corp/Makefile @@ -5,29 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -SOBJS := init.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := t3corp.o +obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +extra-y += init.o diff --git a/board/t3corp/init.S b/board/t3corp/init.S index 70c455ab3d..7ae9c43924 100644 --- a/board/t3corp/init.S +++ b/board/t3corp/init.S @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/taskit/stamp9g20/Kconfig b/board/taskit/stamp9g20/Kconfig new file mode 100644 index 0000000000..3139f9af86 --- /dev/null +++ b/board/taskit/stamp9g20/Kconfig @@ -0,0 +1,15 @@ +if TARGET_STAMP9G20 + +config SYS_BOARD + default "stamp9g20" + +config SYS_VENDOR + default "taskit" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "stamp9g20" + +endif diff --git a/board/taskit/stamp9g20/MAINTAINERS b/board/taskit/stamp9g20/MAINTAINERS new file mode 100644 index 0000000000..a91c1960cb --- /dev/null +++ b/board/taskit/stamp9g20/MAINTAINERS @@ -0,0 +1,7 @@ +STAMP9G20 BOARD +M: Markus Hubig +S: Maintained +F: board/taskit/stamp9g20/ +F: include/configs/stamp9g20.h +F: configs/portuxg20_defconfig +F: configs/stamp9g20_defconfig diff --git a/board/taskit/stamp9g20/Makefile b/board/taskit/stamp9g20/Makefile index 3909447de5..d015e0f740 100644 --- a/board/taskit/stamp9g20/Makefile +++ b/board/taskit/stamp9g20/Makefile @@ -13,25 +13,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += stamp9g20.o -COBJS-y += led.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += stamp9g20.o +obj-y += led.o diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c index 704a63bad8..27cdf77f01 100644 --- a/board/taskit/stamp9g20/stamp9g20.c +++ b/board/taskit/stamp9g20/stamp9g20.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -67,8 +66,6 @@ static void stamp9G20_nand_hw_init(void) static void stamp9G20_macb_hw_init(void) { struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ at91_set_gpio_output(AT91_PIN_PA26, 0); @@ -91,33 +88,7 @@ static void stamp9G20_macb_hw_init(void) pin_to_mask(AT91_PIN_PA28), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) & - ~AT91_RSTC_MR_URSTEN), &rstc->mr); - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end of hardware reset */ - unsigned long start = get_timer(0); - unsigned long timeout = 1000; /* 1000ms */ - - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { - - /* avoid shutdown by watchdog */ - WATCHDOG_RESET(); - mdelay(10); - - /* timeout for not getting stuck in an endless loop */ - if (get_timer(start) >= timeout) { - puts("*** ERROR: Timeout waiting for PHY reset!\n"); - break; - }; - }; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig new file mode 100644 index 0000000000..84b243e352 --- /dev/null +++ b/board/tbs/tbs2910/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TBS2910 + +config SYS_BOARD + default "tbs2910" + +config SYS_VENDOR + default "tbs" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "tbs2910" + +endif diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS new file mode 100644 index 0000000000..bf176553d2 --- /dev/null +++ b/board/tbs/tbs2910/MAINTAINERS @@ -0,0 +1,6 @@ +TBS2910 BOARD +M: Soeren Moch +S: Maintained +F: board/tbs/tbs2910/ +F: configs/tbs2910_defconfig +F: include/configs/tbs2910.h diff --git a/board/tbs/tbs2910/Makefile b/board/tbs/tbs2910/Makefile new file mode 100644 index 0000000000..9d9eb8722d --- /dev/null +++ b/board/tbs/tbs2910/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Soeren Moch +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tbs2910.o diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c new file mode 100644 index 0000000000..dfa430e4ab --- /dev/null +++ b/board/tbs/tbs2910/tbs2910.c @@ -0,0 +1,397 @@ +/* + * Copyright (C) 2014 Soeren Moch + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +DECLARE_GLOBAL_DATA_PTR; + +#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +#ifdef CONFIG_SYS_I2C +/* I2C1, SGTL5000 */ +static struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +/* I2C2 HDMI */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3, CON11, DS1307, PCIe_SMB */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 6) + } +}; +#endif /* CONFIG_SYS_I2C */ + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 PHY Reset */ + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pcie_pads[] = { + /* W_DISABLE# */ + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + /* PERST# */ + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int dram_init(void) +{ + gd->ram_size = 2048ul * 1024 * 1024; + return 0; +} + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8035 PHY */ + gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 25), 1); +} + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + /* + * (U-boot device node) (Physical Port) + * mmc0 SD2 + * mmc1 SD3 + * mmc2 eMMC + */ + int i, ret; + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + return 0; +} +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_VIDEO_IPUV3 +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + /* 1024x768@60Hz (VESA)*/ + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + s32 timeout = 100000; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); + writel(reg, &ccm->analog_pll_video); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; + writel(reg, &ccm->analog_pll_video); + + /* select video pll for ldb_di0_clk */ + reg = readl(&ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); + writel(reg, &ccm->cs2cdr); + + /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */ + reg = readl(&ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &ccm->cscmr2); + + /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */ + reg = readl(&ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + setup_pcie(); + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif +#ifdef CONFIG_DWC_AHSATA + setup_sata(); +#endif +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: TBS2910 Matrix ARM mini PC\n"); + return 0; +} diff --git a/board/tcm-bf518/Kconfig b/board/tcm-bf518/Kconfig new file mode 100644 index 0000000000..558c2fe495 --- /dev/null +++ b/board/tcm-bf518/Kconfig @@ -0,0 +1,9 @@ +if TARGET_TCM_BF518 + +config SYS_BOARD + default "tcm-bf518" + +config SYS_CONFIG_NAME + default "tcm-bf518" + +endif diff --git a/board/tcm-bf518/MAINTAINERS b/board/tcm-bf518/MAINTAINERS new file mode 100644 index 0000000000..169012269f --- /dev/null +++ b/board/tcm-bf518/MAINTAINERS @@ -0,0 +1,6 @@ +TCM-BF518 BOARD +#M: Bluetechnix Tinyboards +S: Orphan (since 2014-03) +F: board/tcm-bf518/ +F: include/configs/tcm-bf518.h +F: configs/tcm-bf518_defconfig diff --git a/board/tcm-bf518/Makefile b/board/tcm-bf518/Makefile index b7275f49fe..2e029f5ce8 100644 --- a/board/tcm-bf518/Makefile +++ b/board/tcm-bf518/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := tcm-bf518.o diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk deleted file mode 100644 index f1ef9bf682..0000000000 --- a/board/tcm-bf518/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 diff --git a/board/tcm-bf518/tcm-bf518.c b/board/tcm-bf518/tcm-bf518.c index 5964059dd1..5d25fcd0a9 100644 --- a/board/tcm-bf518/tcm-bf518.c +++ b/board/tcm-bf518/tcm-bf518.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -47,7 +46,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/tcm-bf537/Kconfig b/board/tcm-bf537/Kconfig new file mode 100644 index 0000000000..e0127c641e --- /dev/null +++ b/board/tcm-bf537/Kconfig @@ -0,0 +1,9 @@ +if TARGET_TCM_BF537 + +config SYS_BOARD + default "tcm-bf537" + +config SYS_CONFIG_NAME + default "tcm-bf537" + +endif diff --git a/board/tcm-bf537/MAINTAINERS b/board/tcm-bf537/MAINTAINERS new file mode 100644 index 0000000000..1cd48451df --- /dev/null +++ b/board/tcm-bf537/MAINTAINERS @@ -0,0 +1,6 @@ +TCM-BF537 BOARD +#M: Bluetechnix Tinyboards +S: Orphan (since 2014-03) +F: board/tcm-bf537/ +F: include/configs/tcm-bf537.h +F: configs/tcm-bf537_defconfig diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile index 57b0a7c83d..93a01e4a3c 100644 --- a/board/tcm-bf537/Makefile +++ b/board/tcm-bf537/Makefile @@ -9,24 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o gpio_cfi_flash.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := tcm-bf537.o gpio_cfi_flash.o diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk index 973d357559..7f9138b09b 100644 --- a/board/tcm-bf537/config.mk +++ b/board/tcm-bf537/config.mk @@ -7,9 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c index 38aaae6870..a4f0f7121b 100644 --- a/board/tcm-bf537/tcm-bf537.c +++ b/board/tcm-bf537/tcm-bf537.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,7 +31,7 @@ static void board_init_enetaddr(char *var) return; printf("Warning: %s: generating 'random' MAC address\n", var); - bfin_gen_rand_mac(enetaddr); + eth_random_addr(enetaddr); eth_setenv_enetaddr(var, enetaddr); } diff --git a/board/technexion/tao3530/Kconfig b/board/technexion/tao3530/Kconfig new file mode 100644 index 0000000000..27bc91f8ca --- /dev/null +++ b/board/technexion/tao3530/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TAO3530 + +config SYS_BOARD + default "tao3530" + +config SYS_VENDOR + default "technexion" + +config SYS_CONFIG_NAME + default "tao3530" + +endif diff --git a/board/technexion/tao3530/MAINTAINERS b/board/technexion/tao3530/MAINTAINERS new file mode 100644 index 0000000000..ad02b46f70 --- /dev/null +++ b/board/technexion/tao3530/MAINTAINERS @@ -0,0 +1,11 @@ +TAO3530 BOARD +M: Stefan Roese +S: Maintained +F: board/technexion/tao3530/ +F: include/configs/tao3530.h +F: configs/omap3_ha_defconfig + +TAO3530 BOARD +M: Tapani Utriainen +S: Maintained +F: configs/tao3530_defconfig diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile new file mode 100644 index 0000000000..2aff38311c --- /dev/null +++ b/board/technexion/tao3530/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tao3530.o diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c new file mode 100644 index 0000000000..744ff44008 --- /dev/null +++ b/board/technexion/tao3530/tao3530.c @@ -0,0 +1,222 @@ +/* + * Maintainer : + * Tapani Utriainen + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "tao3530.h" + +DECLARE_GLOBAL_DATA_PTR; + +int tao3530_revision(void) +{ + int ret = 0; + + /* char *label argument is unused in gpio_request() */ + ret = gpio_request(65, ""); + if (ret) { + puts("Error: GPIO 65 not available\n"); + goto out; + } + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); + + ret = gpio_request(1, ""); + if (ret) { + puts("Error: GPIO 1 not available\n"); + goto out2; + } + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4)); + + ret = gpio_direction_input(65); + if (ret) { + puts("Error: GPIO 65 not available for input\n"); + goto out3; + } + + ret = gpio_direction_input(1); + if (ret) { + puts("Error: GPIO 1 not available for input\n"); + goto out3; + } + + ret = gpio_get_value(65) << 1 | gpio_get_value(1); + +out3: + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0)); + gpio_free(1); +out2: + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); + gpio_free(65); +out: + + return ret; +} + +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + /* + * Switch baseboard LED to red upon power-on + */ + MUX_OMAP3_HA(); + + /* Request a gpio before using it */ + gpio_request(111, ""); + /* Sets the gpio as output and its value to 1, switch LED to red */ + gpio_direction_output(111, 1); +#endif + + if (tao3530_revision() < 3) { + /* 256MB / Bank */ + timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */ + timings->ctrla = HYNIX_V_ACTIMA_165; + timings->ctrlb = HYNIX_V_ACTIMB_165; + } else { + /* 128MB / Bank */ + timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */ + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + } + + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +} +#endif + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + + twl4030_power_init(); + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + + /* Configure GPIOs to output */ + /* GPIO23 */ + writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); + writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + + /* Set GPIOs */ + writel(GPIO10 | GPIO8 | GPIO2 | GPIO1, + &gpio6_base->setdataout); + writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + + switch (tao3530_revision()) { + case 0: + puts("TAO-3530 REV Reserve 1\n"); + break; + case 1: + puts("TAO-3530 REV Reserve 2\n"); + break; + case 2: + puts("TAO-3530 REV Cx\n"); + break; + case 3: + puts("TAO-3530 REV Ax/Bx\n"); + break; + default: + puts("Unknown board revision\n"); + } + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_TAO3530(); +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + MUX_OMAP3_HA(); +#endif +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + + return 0; +} +#endif + +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + +#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +/* Call usb_stop() before starting the kernel */ +void show_boot_progress(int val) +{ + if (val == BOOTSTAGE_ID_RUN_OS) + usb_stop(); +} + +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED +}; + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(int index) +{ + return omap_ehci_hcd_stop(); +} +#endif /* CONFIG_USB_EHCI */ diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h new file mode 100644 index 0000000000..4a94399fc9 --- /dev/null +++ b/board/technexion/tao3530/tao3530.h @@ -0,0 +1,371 @@ +/* + * (C) Copyright TechNexion 2010 + * Edward Lin + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _TAO3530_H_ +#define _TAO3530_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + "HEAD acoustics OMAP3-HA", +#else + "OMAP3 TAO-3530 board", +#endif + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_TAO3530() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \ + /* - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) \ + /* MMC2 WLAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ + /*LocalBus LAN Reset*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \ + /*LocalBus LAN IRQ*/\ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) \ + /* USB EHCI (port 2) */\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) \ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) \ + /* - VIO_1V8*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) + +#define MUX_OMAP3_HA() \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M4)) /* GPIO_111 */ + +#endif diff --git a/board/technexion/twister/Kconfig b/board/technexion/twister/Kconfig new file mode 100644 index 0000000000..4c0ace8edd --- /dev/null +++ b/board/technexion/twister/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TWISTER + +config SYS_BOARD + default "twister" + +config SYS_VENDOR + default "technexion" + +config SYS_CONFIG_NAME + default "twister" + +endif diff --git a/board/technexion/twister/MAINTAINERS b/board/technexion/twister/MAINTAINERS new file mode 100644 index 0000000000..1ce2b37026 --- /dev/null +++ b/board/technexion/twister/MAINTAINERS @@ -0,0 +1,6 @@ +TWISTER BOARD +M: Stefano Babic +S: Maintained +F: board/technexion/twister/ +F: include/configs/twister.h +F: configs/twister_defconfig diff --git a/board/technexion/twister/Makefile b/board/technexion/twister/Makefile index 641e61e708..2a910211fd 100644 --- a/board/technexion/twister/Makefile +++ b/board/technexion/twister/Makefile @@ -6,21 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := twister.o diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index cd91d8fea0..a4aed3ba8b 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #ifdef CONFIG_USB_EHCI #include @@ -51,9 +53,10 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); } int ehci_hcd_stop(int index) diff --git a/board/technexion/twister/twister.h b/board/technexion/twister/twister.h index 62fbfdfed6..e286bd4522 100644 --- a/board/technexion/twister/twister.h +++ b/board/technexion/twister/twister.h @@ -337,7 +337,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/teejet/mt_ventoux/Kconfig b/board/teejet/mt_ventoux/Kconfig new file mode 100644 index 0000000000..fd7196a6f9 --- /dev/null +++ b/board/teejet/mt_ventoux/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MT_VENTOUX + +config SYS_BOARD + default "mt_ventoux" + +config SYS_VENDOR + default "teejet" + +config SYS_CONFIG_NAME + default "mt_ventoux" + +endif diff --git a/board/teejet/mt_ventoux/MAINTAINERS b/board/teejet/mt_ventoux/MAINTAINERS new file mode 100644 index 0000000000..d23464c20f --- /dev/null +++ b/board/teejet/mt_ventoux/MAINTAINERS @@ -0,0 +1,6 @@ +MT_VENTOUX BOARD +M: Stefano Babic +S: Maintained +F: board/teejet/mt_ventoux/ +F: include/configs/mt_ventoux.h +F: configs/mt_ventoux_defconfig diff --git a/board/teejet/mt_ventoux/Makefile b/board/teejet/mt_ventoux/Makefile index 641e61e708..66f56fd219 100644 --- a/board/teejet/mt_ventoux/Makefile +++ b/board/teejet/mt_ventoux/Makefile @@ -6,21 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := mt_ventoux.o diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index b4e01d1562..b4a0a72bd0 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -102,9 +102,10 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); } int ehci_hcd_stop(int index) @@ -189,7 +190,7 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie) return assert_clk; } -Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { +xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, @@ -199,7 +200,7 @@ Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { fpga_post_config_fn, }; -Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, +xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, (void *)&mt_ventoux_fpga_fns, 0); /* Initialize the FPGA */ diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h index aba71a84bf..bc85ad4350 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.h +++ b/board/teejet/mt_ventoux/mt_ventoux.h @@ -339,7 +339,7 @@ const omap3_sysinfo sysinfo = { /* gpio_10 */\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig new file mode 100644 index 0000000000..1ddbb2c67c --- /dev/null +++ b/board/ti/am335x/Kconfig @@ -0,0 +1,40 @@ +if TARGET_AM335X_EVM + +config SYS_BOARD + default "am335x" + +config SYS_VENDOR + default "ti" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "am335x_evm" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0 as for example the IDK + uses UART3 so enter 4 here. + +config NOR + bool "Support for NOR flash" + help + The AM335x SoC supports having a NOR flash connected to the GPMC. + In practice this is seen as a NOR flash module connected to the + "memory cape" for the BeagleBone family. + +config NOR_BOOT + bool "Support for booting from NOR flash" + depends on NOR + help + Enabling this will make a U-Boot binary that is capable of being + booted via NOR. In this case we will enable certain pinmux early + as the ROM only partially sets up pinmux. We also default to using + NOR for environment. +endif diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS new file mode 100644 index 0000000000..d166fa0be3 --- /dev/null +++ b/board/ti/am335x/MAINTAINERS @@ -0,0 +1,17 @@ +AM335X BOARD +M: Tom Rini +S: Maintained +F: board/ti/am335x/ +F: include/configs/am335x_evm.h +F: configs/am335x_boneblack_defconfig +F: configs/am335x_boneblack_vboot_defconfig +F: configs/am335x_evm_defconfig +F: configs/am335x_evm_nor_defconfig +F: configs/am335x_evm_norboot_defconfig +F: configs/am335x_evm_spiboot_defconfig +F: configs/am335x_evm_uart1_defconfig +F: configs/am335x_evm_uart2_defconfig +F: configs/am335x_evm_uart3_defconfig +F: configs/am335x_evm_uart4_defconfig +F: configs/am335x_evm_uart5_defconfig +F: configs/am335x_evm_usbspl_defconfig diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index cb2b999025..804ac379db 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -6,33 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -ifdef CONFIG_SPL_BUILD -COBJS := mux.o +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o endif -COBJS += board.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += board.o diff --git a/board/ti/am335x/README b/board/ti/am335x/README new file mode 100644 index 0000000000..19e0eccbac --- /dev/null +++ b/board/ti/am335x/README @@ -0,0 +1,205 @@ +Summary +======= + +This document covers various features of the 'am335x_evm' build, and some of +the related build targets (am335x_evm_uartN, etc). + +Hardware +======== + +The binary produced by this board supports, based on parsing of the EEPROM +documented in TI's reference designs: +- AM335x GP EVM +- AM335x EVM SK +- Beaglebone White +- Beaglebone Black + +Customization +============= + +Given that all of the above boards are reference platforms (and the +Beaglebone platforms are OSHA), it is likely that this platform code and +configuration will be used as the basis of a custom platform. It is +worth noting that aside from things such as NAND or MMC only being +required if a custom platform makes use of these blocks, the following +are required, depending on design: + +- GPIO is only required if DDR3 power is controlled in a way similar to + EVM SK +- SPI is only required for SPI flash, or exposing the SPI bus. + +The following blocks are required: +- I2C, to talk with the PMIC and ensure that we do not run afoul of + errata 1.0.24. + +When removing options as part of customization, +CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your +needs and to remove no longer relevant options as in some cases we +define additional text blocks (such as for NAND or DFU strings). Also +note that all of the SPL options are grouped together, rather than with +the IP blocks, so both areas will need their choices updated to reflect +the custom design. + +NAND +==== + +The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In +this example to program the NAND we assume that an SD card has been +inserted with the files to write in the first SD slot and that mtdparts +have been configured correctly for the board. All images are first loaded +into memory, then written to NAND. + +Step-1: Building u-boot for NAND boot + Set following CONFIGxx options for NAND device. + CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page + CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page + CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block + CONFIG_SYS_NAND_ECCPOS ECC map for NAND page + CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) + +Step-2: Flashing NAND via MMC/SD + # select BOOTSEL to MMC/SD boot and boot from MMC/SD card + U-Boot # mmc rescan + # erase flash + U-Boot # nand erase.chip + U-Boot # env default -f -a + U-Boot # saveenv + # flash MLO. Redundant copies of MLO are kept for failsafe + U-Boot # load mmc 0 0x82000000 MLO + U-Boot # nand write 0x82000000 0x00000 0x20000 + U-Boot # nand write 0x82000000 0x20000 0x20000 + U-Boot # nand write 0x82000000 0x40000 0x20000 + U-Boot # nand write 0x82000000 0x60000 0x20000 + # flash u-boot.img + U-Boot # load mmc 0 0x82000000 u-boot.img + U-Boot # nand write 0x82000000 0x80000 0x60000 + # flash kernel image + U-Boot # load mmc 0 0x82000000 uImage + U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize} + # flash filesystem image + U-Boot # load mmc 0 0x82000000 filesystem.img + U-Boot # nand write 0x82000000 ${loadaddress} 0x300000 + +Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. + The device should boot from images flashed on NAND device. + +NOR +=== + +The Beaglebone White can be equipped with a "memory cape" that in turn can +have a NOR module plugged into it. In this case it is then possible to +program and boot from NOR. Note that due to how U-Boot is designed we +must build a specific version of U-Boot that knows we have NOR flash. This +build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot' +build that will assume that the environment is on NOR rather than NAND. In +the following example we assume that and SD card has been populated with +MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the +'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a +binary must be written to the start of NOR, with no header or similar +prepended. In the following example we use a size of 512KiB (0x80000) +as that is how much space we set aside before the environment, as per +the config file. + +U-Boot # mmc rescan +U-Boot # load mmc 0 ${loadaddr} u-boot.bin +U-Boot # protect off 08000000 +80000 +U-Boot # erase 08000000 +80000 +U-Boot # cp.b ${loadaddr} 08000000 ${filesize} + +Falcon Mode +=========== + +The default build includes "Falcon Mode" (see doc/README.falcon) via NAND, +eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is +to read a 'c' on the console while in SPL at any point prior to loading the +OS payload (so as soon as possible) to opt to booting full U-Boot. Also +note that while one can program Falcon Mode "in place" great care needs to +be taken by the user to not 'brick' their setup. As these are all eval +boards with multiple boot methods, recovery should not be an issue in this +worst-case however. + +Falcon Mode: eMMC +================= + +The recommended layout in this case is: + +MMC BLOCKS |--------------------------------| LOCATION IN BYTES +0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000 +0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000 +0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000 +0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000 +0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000 +0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000 +0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000 + +Note that when we run 'spl export' it will prepare to boot the kernel. +This includes relocation of the uImage from where we loaded it to the entry +point defined in the header. As these locations overlap by default, it +would leave us with an image that if written to MMC will not boot, so +instead of using the loadaddr variable we use 0x81000000 in the following +example. In this example we are loading from the network, for simplicity, +and assume a valid partition table already exists and 'mmc dev' has already +been run to select the correct device. Also note that if you previously +had a FAT partition (such as on a Beaglebone Black) it is not enough to +write garbage into the area, you must delete it from the partition table +first. + +# Ensure we are able to talk with this mmc device +U-Boot # mmc rescan +U-Boot # tftp 81000000 am335x/MLO +# Write to two of the backup locations ROM uses +U-Boot # mmc write 81000000 100 100 +U-Boot # mmc write 81000000 200 100 +# Write U-Boot to the location set in the config +U-Boot # tftp 81000000 am335x/u-boot.img +U-Boot # mmc write 81000000 300 400 +# Load kernel and device tree into memory, perform export +U-Boot # tftp 81000000 am335x/uImage +U-Boot # run findfdt +U-Boot # tftp ${fdtaddr} am335x/${fdtfile} +U-Boot # run mmcargs +U-Boot # spl export fdt 81000000 - ${fdtaddr} +# Write the updated device tree to MMC +U-Boot # mmc write ${fdtaddr} 80 80 +# Write the uImage to MMC +U-Boot # mmc write 81000000 900 2000 + +Falcon Mode: FAT SD cards +========================= + +In this case the additional file is written to the filesystem. In this +example we assume that the uImage and device tree to be used are already on +the FAT filesystem (only the uImage MUST be for this to function +afterwards) along with a Falcon Mode aware MLO and the FAT partition has +already been created and marked bootable: + +U-Boot # mmc rescan +# Load kernel and device tree into memory, perform export +U-Boot # load mmc 0:1 ${loadaddr} uImage +U-Boot # run findfdt +U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile} +U-Boot # run mmcargs +U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} + +This will print a number of lines and then end with something like: + Using Device Tree in place at 80f80000, end 80f85928 + Using Device Tree in place at 80f80000, end 80f88928 +So then you: + +U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928 + +Falcon Mode: NAND +================= + +In this case the additional data is written to another partition of the +NAND. In this example we assume that the uImage and device tree to be are +already located on the NAND somewhere (such as filesystem or mtd partition) +along with a Falcon Mode aware MLO written to the correct locations for +booting and mtdparts have been configured correctly for the board: + +U-Boot # nand read ${loadaddr} kernel +U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb +U-Boot # run nandargs +U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} +U-Boot # nand erase.part u-boot-spl-os +U-Boot # nand write ${fdtaddr} u-boot-spl-os diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 7138d739e4..0739e6021a 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -19,64 +19,31 @@ #include #include #include +#include #include #include #include #include #include #include +#include +#include +#include +#include +#include #include "board.h" DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - -/* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0x3A - /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -static struct am335x_baseboard_id __attribute__((section (".data"))) header; - -static inline int board_is_bone(void) -{ - return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); -} - -static inline int board_is_bone_lt(void) -{ - return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); -} - -static inline int board_is_evm_sk(void) -{ - return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); -} - -static inline int board_is_idk(void) -{ - return !strncmp(header.config, "SKU#02", 6); -} - -static int __maybe_unused board_is_gp_evm(void) -{ - return !strncmp("A33515BB", header.name, 8); -} - -int board_is_evm_15_or_later(void) -{ - return (!strncmp("A33515BB", header.name, 8) && - strncmp("1.5", header.version, 3) <= 0); -} - /* * Read header information from EEPROM into global structure. */ -static int read_eeprom(void) +static int read_eeprom(struct am335x_baseboard_id *header) { /* Check if baseboard eeprom is available */ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { @@ -86,28 +53,28 @@ static int read_eeprom(void) } /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, - sizeof(header))) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct am335x_baseboard_id))) { puts("Could not read the EEPROM; something fundamentally" " wrong on the I2C bus.\n"); return -EIO; } - if (header.magic != 0xEE3355AA) { + if (header->magic != 0xEE3355AA) { /* * read the eeprom using i2c again, * but use only a 1 byte address */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, - (uchar *)&header, sizeof(header))) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct am335x_baseboard_id))) { puts("Could not read the EEPROM; something " "fundamentally wrong on the I2C bus.\n"); return -EIO; } - if (header.magic != 0xEE3355AA) { + if (header->magic != 0xEE3355AA) { printf("Incorrect magic number (0x%x) in EEPROM\n", - header.magic); + header->magic); return -EINVAL; } } @@ -115,48 +82,19 @@ static int read_eeprom(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr2_data = { - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | - (MT47H128M16RT25E_RD_DQS<<20) | - (MT47H128M16RT25E_RD_DQS<<10) | - (MT47H128M16RT25E_RD_DQS<<0)), - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | - (MT47H128M16RT25E_WR_DQS<<20) | - (MT47H128M16RT25E_WR_DQS<<10) | - (MT47H128M16RT25E_WR_DQS<<0)), - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | - (MT47H128M16RT25E_PHY_WRLVL<<20) | - (MT47H128M16RT25E_PHY_WRLVL<<10) | - (MT47H128M16RT25E_PHY_WRLVL<<0)), - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | - (MT47H128M16RT25E_PHY_GATELVL<<20) | - (MT47H128M16RT25E_PHY_GATELVL<<10) | - (MT47H128M16RT25E_PHY_GATELVL<<0)), - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | - (MT47H128M16RT25E_PHY_WR_DATA<<20) | - (MT47H128M16RT25E_PHY_WR_DATA<<10) | - (MT47H128M16RT25E_PHY_WR_DATA<<0)), - .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, - .datadldiff0 = PHY_DLL_LOCK_DIFF, + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; static const struct emif_regs ddr2_emif_reg_data = { @@ -173,7 +111,6 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = MT41J128MJT125_WR_DQS, .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct ddr_data ddr3_beagleblack_data = { @@ -181,7 +118,6 @@ static const struct ddr_data ddr3_beagleblack_data = { .datawdsratio0 = MT41K256M16HA125E_WR_DQS, .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct ddr_data ddr3_evm_data = { @@ -189,48 +125,38 @@ static const struct ddr_data ddr3_evm_data = { .datawdsratio0 = MT41J512M8RH125_WR_DQS, .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J128MJT125_RATIO, - .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd1csratio = MT41J128MJT125_RATIO, - .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd2csratio = MT41J128MJT125_RATIO, - .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, }; static const struct cmd_control ddr3_evm_cmd_ctrl_data = { .cmd0csratio = MT41J512M8RH125_RATIO, - .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, .cmd1csratio = MT41J512M8RH125_RATIO, - .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, .cmd2csratio = MT41J512M8RH125_RATIO, - .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, }; @@ -270,76 +196,258 @@ static struct emif_regs ddr3_evm_emif_reg_data = { int spl_start_uboot(void) { /* break into full u-boot on 'c' */ - return (serial_tstc() && serial_getc() == 'c'); -} + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; #endif + return 0; +} #endif -/* - * early system init of muxing and clocks. - */ -void s_init(void) +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_bone_black = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif + struct am335x_baseboard_id header; + int mpu_vdd; - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + if (board_is_bone(&header) || board_is_bone_lt(&header)) { + /* BeagleBone PMIC Code */ + int usb_cur_lim; + + /* + * Only perform PMIC configurations if board rev > A1 + * on Beaglebone White + */ + if (board_is_bone(&header) && !strncmp(header.version, + "00A1", 4)) + return; + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * On Beaglebone White we need to ensure we have AC power + * before increasing the frequency. + */ + if (board_is_bone(&header)) { + uchar pmic_status_reg; + if (tps65217_reg_read(TPS65217_STATUS, + &pmic_status_reg)) + return; + if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { + puts("No AC power, disabling frequency switch\n"); + return; + } + } + + /* + * Override what we have detected since we know if we have + * a Beaglebone Black it supports 1GHz. + */ + if (board_is_bone_lt(&header)) + dpll_mpu_opp100.m = MPUPLL_M_1000; + + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_POWER_PATH, + usb_cur_lim, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* + * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. + * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. + */ + if (board_is_bone(&header)) { + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } else { + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } else { + int sil_rev; + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) + return; + + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, + dpll_mpu_opp100.m); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) + return; -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + } + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + struct am335x_baseboard_id header; - /* Enable RTC32K clock */ - rtc32k_enable(); + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); -#ifdef CONFIG_SERIAL1 + if (board_is_evm_sk(&header)) + return &dpll_ddr_evm_sk; + else if (board_is_bone_lt(&header)) + return &dpll_ddr_bone_black; + else if (board_is_evm_15_or_later(&header)) + return &dpll_ddr_evm_sk; + else + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ +#if CONFIG_CONS_INDEX == 1 enable_uart0_pin_mux(); -#endif /* CONFIG_SERIAL1 */ -#ifdef CONFIG_SERIAL2 +#elif CONFIG_CONS_INDEX == 2 enable_uart1_pin_mux(); -#endif /* CONFIG_SERIAL2 */ -#ifdef CONFIG_SERIAL3 +#elif CONFIG_CONS_INDEX == 3 enable_uart2_pin_mux(); -#endif /* CONFIG_SERIAL3 */ -#ifdef CONFIG_SERIAL4 +#elif CONFIG_CONS_INDEX == 4 enable_uart3_pin_mux(); -#endif /* CONFIG_SERIAL4 */ -#ifdef CONFIG_SERIAL5 +#elif CONFIG_CONS_INDEX == 5 enable_uart4_pin_mux(); -#endif /* CONFIG_SERIAL5 */ -#ifdef CONFIG_SERIAL6 +#elif CONFIG_CONS_INDEX == 6 enable_uart5_pin_mux(); -#endif /* CONFIG_SERIAL6 */ +#endif +} - uart_soft_reset(); +void set_mux_conf_regs(void) +{ + __maybe_unused struct am335x_baseboard_id header; - gd = &gdata; + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); - preloader_console_init(); + enable_board_pin_mux(&header); +} - /* Initalize the board header */ - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) +const struct ctrl_ioregs ioregs_evmsk = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_bonelt = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_evm15 = { + .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + __maybe_unused struct am335x_baseboard_id header; + + if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); - enable_board_pin_mux(&header); - if (board_is_evm_sk()) { + if (board_is_evm_sk(&header)) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. * This is safe enough to do on older revs. @@ -348,36 +456,36 @@ void s_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } - if (board_is_evm_sk()) - config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + if (board_is_evm_sk(&header)) + config_ddr(303, &ioregs_evmsk, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); - else if (board_is_bone_lt()) - config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, + else if (board_is_bone_lt(&header)) + config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); - else if (board_is_evm_15_or_later()) - config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, + else if (board_is_evm_15_or_later(&header)) + config_ddr(303, &ioregs_evm15, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else - config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, + config_ddr(266, &ioregs, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) - puts("Could not get board ID.\n"); - - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); - +#endif return 0; } @@ -386,6 +494,10 @@ int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG char safe_string[HDR_NAME_LEN + 1]; + struct am335x_baseboard_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); /* Now set variables based on the header. */ strncpy(safe_string, (char *)header.name, sizeof(header.name)); @@ -414,12 +526,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, }, }; @@ -435,6 +547,7 @@ static struct cpsw_platform_data cpsw_data = { .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, @@ -442,13 +555,28 @@ static struct cpsw_platform_data cpsw_data = { }; #endif -#if defined(CONFIG_DRIVER_TI_CPSW) || \ - (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +/* + * This function will: + * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr + * in the environment + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ + && defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; + __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); @@ -470,12 +598,31 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_DRIVER_TI_CPSW - if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { + + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + if (board_is_bone(&header) || board_is_bone_lt(&header) || + board_is_idk(&header)) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { - writel(RGMII_MODE_ENABLE, &cdev->miisel); + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } @@ -499,7 +646,7 @@ int board_eth_init(bd_t *bis) #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 - if (board_is_evm_sk() || board_is_gp_evm()) { + if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { const char *devname; devname = miiphy_get_current_dev(); diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index 9fea1f15a6..bc700d56fe 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -29,6 +29,37 @@ struct am335x_baseboard_id { char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; }; +static inline int board_is_bone(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_bone_lt(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(struct am335x_baseboard_id *header) +{ + return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); +} + +static inline int board_is_idk(struct am335x_baseboard_id *header) +{ + return !strncmp(header->config, "SKU#02", 6); +} + +static inline int board_is_gp_evm(struct am335x_baseboard_id *header) +{ + return !strncmp("A33515BB", header->name, HDR_NAME_LEN); +} + +static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) +{ + return (board_is_gp_evm(header) && + strncmp("1.5", header->version, 3) <= 0); +} + /* * We have three pin mux functions that must exist. We must be able to enable * uart0, for initial output and i2c0 to read the main EEPROM. We then have a diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 02837082cb..680f6560f2 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -171,24 +171,77 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +#ifdef CONFIG_NAND static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ +#endif + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ {-1}, }; +#elif defined(CONFIG_NOR) +static struct module_pin_mux bone_norcape_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ + {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ + {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ + {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ + {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ + {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ + {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ + {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ + {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ + {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ + {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ + {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ + {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ + {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ + {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ + {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ + {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ + {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ + {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ + {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ + {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ + {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ + {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ + {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ + {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ + {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ + {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ + {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ + {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ + {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ + {-1}, +}; +#endif + +#if defined(CONFIG_NOR_BOOT) +void enable_norboot_pin_mux(void) +{ + configure_module_pin_mux(bone_norcape_pin_mux); +} +#endif void enable_uart0_pin_mux(void) { @@ -262,13 +315,19 @@ static unsigned short detect_daughter_board_profile(void) void enable_board_pin_mux(struct am335x_baseboard_id *header) { /* Do board-specific muxes. */ - if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) { + if (board_is_bone(header)) { /* Beaglebone pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) + configure_module_pin_mux(bone_norcape_pin_mux); +#else configure_module_pin_mux(mmc1_pin_mux); - } else if (!strncmp(header->config, "SKU#01", 6)) { +#endif + } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); @@ -277,33 +336,36 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); /* Profiles 2 & 3 don't have NAND */ +#ifdef CONFIG_NAND if (profile & ~(PROFILE_2 | PROFILE_3)) configure_module_pin_mux(nand_pin_mux); +#endif else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } - } else if (!strncmp(header->config, "SKU#02", 6)) { - /* - * Industrial Motor Control (IDK) - * note: IDK console is on UART3 by default. - * So u-boot mus be build with CONFIG_SERIAL4 and - * CONFIG_CONS_INDEX=4 - */ + } else if (board_is_idk(header)) { + /* Industrial Motor Control (IDK) */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_no_cd_pin_mux); - } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) { + } else if (board_is_evm_sk(header)) { /* Starter Kit EVM */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux_sk_evm); - } else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) { + } else if (board_is_bone_lt(header)) { /* Beaglebone LT pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT) + configure_module_pin_mux(bone_norcape_pin_mux); +#else configure_module_pin_mux(mmc1_pin_mux); +#endif } else { puts("Unknown board, cannot configure pinmux."); hang(); diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds new file mode 100644 index 0000000000..78f294af40 --- /dev/null +++ b/board/ti/am335x/u-boot.lds @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/ti/am335x/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .gnu.hash : { *(.gnu.hash) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} diff --git a/board/ti/am3517crane/Kconfig b/board/ti/am3517crane/Kconfig new file mode 100644 index 0000000000..ad025a3228 --- /dev/null +++ b/board/ti/am3517crane/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AM3517_CRANE + +config SYS_BOARD + default "am3517crane" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am3517_crane" + +endif diff --git a/board/ti/am3517crane/MAINTAINERS b/board/ti/am3517crane/MAINTAINERS new file mode 100644 index 0000000000..cbc3213ec5 --- /dev/null +++ b/board/ti/am3517crane/MAINTAINERS @@ -0,0 +1,6 @@ +AM3517CRANE BOARD +M: Nagendra T S +S: Maintained +F: board/ti/am3517crane/ +F: include/configs/am3517_crane.h +F: configs/am3517_crane_defconfig diff --git a/board/ti/am3517crane/Makefile b/board/ti/am3517crane/Makefile index d9ab72a620..9da795de95 100644 --- a/board/ti/am3517crane/Makefile +++ b/board/ti/am3517crane/Makefile @@ -8,21 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := am3517crane.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := am3517crane.o diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index 5eb97ff378..a649697257 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -43,8 +43,8 @@ int board_init(void) */ int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif dieid_num_r(); diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h index e131c8fb99..6289ca787c 100644 --- a/board/ti/am3517crane/am3517crane.h +++ b/board/ti/am3517crane/am3517crane.h @@ -284,7 +284,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\ /*JTAG*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig new file mode 100644 index 0000000000..8d1c16883d --- /dev/null +++ b/board/ti/am43xx/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AM43XX_EVM + +config SYS_BOARD + default "am43xx" + +config SYS_VENDOR + default "ti" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "am43xx_evm" + +endif diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS new file mode 100644 index 0000000000..d375278bed --- /dev/null +++ b/board/ti/am43xx/MAINTAINERS @@ -0,0 +1,7 @@ +AM43XX BOARD +M: Lokesh Vutla +S: Maintained +F: board/ti/am43xx/ +F: include/configs/am43xx_evm.h +F: configs/am43xx_evm_defconfig +F: configs/am43xx_evm_qspiboot_defconfig diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile new file mode 100644 index 0000000000..36ecb302c1 --- /dev/null +++ b/board/ti/am43xx/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c new file mode 100644 index 0000000000..67036709f1 --- /dev/null +++ b/board/ti/am43xx/board.c @@ -0,0 +1,740 @@ +/* + * board.c + * + * Board functions for TI AM43XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(struct am43xx_board_id *header) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM\n"); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->magic); + return -EINVAL; + } + } + + strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); + am43xx_board_name[sizeof(header->name)] = 0; + + strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); + am43xx_board_rev[sizeof(header->version)] = 0; + + return 0; +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +#define NUM_OPPS 6 + +const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ + {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ + {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ + {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { + {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ + {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ + {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ + {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { + {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ + {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ + {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { + {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ + {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ + {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params gp_evm_dpll_ddr = { + 50, 2, 1, -1, 2, -1, -1}; + +static const struct dpll_params idk_dpll_ddr = { + 400, 23, 1, -1, 2, -1, -1 +}; + +const struct ctrl_ioregs ioregs_lpddr2 = { + .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x1, +}; + +const struct emif_regs emif_regs_lpddr2 = { + .sdram_config = 0x808012BA, + .ref_ctrl = 0x0000040D, + .sdram_tim1 = 0xEA86B411, + .sdram_tim2 = 0x103A094A, + .sdram_tim3 = 0x0F6BA37F, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E284006, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_ddr_ext_phy_ctrl_1 = 0x04010040, + .emif_ddr_ext_phy_ctrl_2 = 0x00500050, + .emif_ddr_ext_phy_ctrl_3 = 0x00500050, + .emif_ddr_ext_phy_ctrl_4 = 0x00500050, + .emif_ddr_ext_phy_ctrl_5 = 0x00500050, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0xc163, +}; + +const struct emif_regs ddr3_emif_regs_400Mhz = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00400040, + .emif_ddr_ext_phy_ctrl_3 = 0x00400040, + .emif_ddr_ext_phy_ctrl_4 = 0x00400040, + .emif_ddr_ext_phy_ctrl_5 = 0x00400040, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_beta = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000065, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_production = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { + .sdram_config = 0x638413b2, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0e084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x89, + .emif_ddr_ext_phy_ctrl_3 = 0x90, + .emif_ddr_ext_phy_ctrl_4 = 0x8e, + .emif_ddr_ext_phy_ctrl_5 = 0x8d, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x80000000, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { + .sdram_config = 0x61a11b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1 = 0x00008009, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000040, + .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, + .emif_ddr_ext_phy_ctrl_4 = 0x00000051, + .emif_ddr_ext_phy_ctrl_5 = 0x00000051, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000405, + .emif_prio_class_serv_map = 0x00000000, + .emif_connect_id_serv_1_map = 0x00000000, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x00ffffff +}; + +/* + * get_sys_clk_index : returns the index of the sys_clk read from + * ctrl status register. This value is either + * read from efuse or sysboot pins. + */ +static u32 get_sys_clk_index(void) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + u32 ind = readl(&ctrl->statusreg), src; + + src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; + if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ + return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> + CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); + else /* Value read from SYS BOOT pins */ + return ((ind & CTRL_SYSBOOT_15_14_MASK) >> + CTRL_SYSBOOT_15_14_SHIFT); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + int ind = get_sys_clk_index(); + + if (board_is_eposevm()) + return &epos_evm_dpll_ddr[ind]; + else if (board_is_gpevm() || board_is_sk()) + return &gp_evm_dpll_ddr; + else if (board_is_idk()) + return &idk_dpll_ddr; + + printf(" Board '%s' not supported\n", am43xx_board_name); + return NULL; +} + + +/* + * get_opp_offset: + * Returns the index for safest OPP of the device to boot. + * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. + * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. + * This data is read from dev_attribute register which is e-fused. + * A'1' in bit indicates OPP disabled and not available, a '0' indicates + * OPP available. Lowest OPP starts with min_off. So returning the + * bit with rightmost '0'. + */ +static int get_opp_offset(int max_off, int min_off) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + int opp, offset, i; + + /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ + opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; + + for (i = max_off; i >= min_off; i--) { + offset = opp & (1 << i); + if (!offset) + return i; + } + + return min_off; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); + u32 ind = get_sys_clk_index(); + + return &dpll_mpu[ind][opp]; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_core[ind]; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_per[ind]; +} + +void scale_vcores_generic(u32 m) +{ + int mpu_vdd; + + if (i2c_probe(TPS65218_CHIP_PM)) + return; + + switch (m) { + case 1000: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; + break; + case 800: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; + break; + case 720: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; + break; + case 600: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; + break; + case 300: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; + break; + default: + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set DCDC1 (CORE) voltage to 1.1V */ + if (tps65218_voltage_update(TPS65218_DCDC1, + TPS65218_DCDC_VOLT_SEL_1100MV)) { + printf("%s failure\n", __func__); + return; + } + + /* Set DCDC2 (MPU) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { + printf("%s failure\n", __func__); + return; + } +} + +void scale_vcores_idk(u32 m) +{ + int mpu_vdd; + + if (i2c_probe(TPS62362_I2C_ADDR)) + return; + + switch (m) { + case 1000: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; + break; + case 800: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; + break; + case 720: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; + break; + case 600: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; + break; + case 300: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; + break; + default: + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set VDD_MPU voltage */ + if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { + printf("%s failure\n", __func__); + return; + } +} + +void scale_vcores(void) +{ + const struct dpll_params *mpu_params; + struct am43xx_board_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Get the frequency */ + mpu_params = get_dpll_mpu_params(); + + if (board_is_idk()) + scale_vcores_idk(mpu_params->m); + else + scale_vcores_generic(mpu_params->m); +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +static void enable_vtt_regulator(void) +{ + u32 temp; + + /* enable module */ + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); + + /* enable output for GPIO5_7 */ + writel(GPIO_SETDATAOUT(7), + AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(7)); + writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); +} + +void sdram_init(void) +{ + /* + * EPOS EVM has 1GB LPDDR2 connected to EMIF. + * GP EMV has 1GB DDR3 connected to EMIF + * along with VTT regulator. + */ + if (board_is_eposevm()) { + config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + } else if (board_is_evm_14_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_production, 0); + } else if (board_is_evm_12_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_beta, 0); + } else if (board_is_gpevm()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz, 0); + } else if (board_is_sk()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_sk_emif_regs_400Mhz, 0); + } else if (board_is_idk()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_idk_emif_regs_400Mhz, 0); + } +} +#endif + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + + if (board_is_idk()) { + power_tps62362_init(I2C_PMIC); + p = pmic_get("TPS62362"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS62362\n"); + } else { + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS65218\n"); + } + + return 0; +} + +int board_init(void) +{ + struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; + u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, + modena_init0_bw_integer, modena_init0_watermark_0; + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + + /* Clear all important bits for DSS errata that may need to be tweaked*/ + mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & + MREQPRIO_0_SAB_INIT0_MASK; + + mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; + + modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & + BW_LIMITER_BW_FRAC_MASK; + + modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & + BW_LIMITER_BW_INT_MASK; + + modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & + BW_LIMITER_BW_WATERMARK_MASK; + + /* Setting MReq Priority of the DSS*/ + mreqprio_0 |= 0x77; + + /* + * Set L3 Fast Configuration Register + * Limiting bandwith for ARM core to 700 MBPS + */ + modena_init0_bw_fractional |= 0x10; + modena_init0_bw_integer |= 0x3; + + writel(mreqprio_0, &cdev->mreqprio_0); + writel(mreqprio_1, &cdev->mreqprio_1); + + writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); + writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); + writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + char safe_string[HDR_NAME_LEN + 1]; + struct am43xx_board_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Now set variables based on the header. */ + strncpy(safe_string, (char *)header.name, sizeof(header.name)); + safe_string[sizeof(header.name)] = 0; + setenv("board_name", safe_string); + + strncpy(safe_string, (char *)header.version, sizeof(header.version)); + safe_string[sizeof(header.version)] = 0; + setenv("board_rev", safe_string); +#endif + return 0; +} +#endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +static void cpsw_control(int enabled) +{ + /* Additional controls can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 16, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("ethaddr")) { + puts(" not set. Validating first E-fuse MAC\n"); + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + if (board_is_eposevm()) { + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[0].phy_addr = 16; + } else if (board_is_sk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 4; + cpsw_slaves[1].phy_addr = 5; + } else if (board_is_idk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 0; + } else { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 0; + } + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + + return rv; +} +#endif diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h new file mode 100644 index 0000000000..eb9493e191 --- /dev/null +++ b/board/ti/am43xx/board.h @@ -0,0 +1,74 @@ +/* + * board.h + * + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include + +static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; +static char *const am43xx_board_rev = (char *)AM4372_BOARD_VERSION_START; + +/* + * TI AM437x EVMs define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 + +struct am43xx_board_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +static inline int board_is_eposevm(void) +{ + return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN); +} + +static inline int board_is_gpevm(void) +{ + return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN); +} + +static inline int board_is_sk(void) +{ + return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN); +} + +static inline int board_is_idk(void) +{ + return !strncmp(am43xx_board_name, "AM43_IDK", HDR_NAME_LEN); +} + +static inline int board_is_evm_14_or_later(void) +{ + return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0); +} + +static inline int board_is_evm_12_or_later(void) +{ + return (board_is_gpevm() && strncmp("1.2", am43xx_board_rev, 3) <= 0); +} + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); +#endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c new file mode 100644 index 0000000000..510477dad9 --- /dev/null +++ b/board/ti/am43xx/mux.c @@ -0,0 +1,153 @@ +/* + * mux.c + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "board.h" + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ + {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */ + {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */ + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */ + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {-1}, +}; + +static struct module_pin_mux mdio_pin_mux[] = { + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */ + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux gpio5_7_pin_mux[] = { + {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */ + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ +#endif + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */ + {-1}, +}; +#endif + +static __maybe_unused struct module_pin_mux qspi_pin_mux[] = { + {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ + {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ + {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ + {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */ + {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */ + {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mdio_pin_mux); + + if (board_is_gpevm()) { + configure_module_pin_mux(gpio5_7_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#endif + } else if (board_is_sk() || board_is_idk()) { + configure_module_pin_mux(rgmii1_pin_mux); +#if defined(CONFIG_NAND) + printf("Error: NAND flash not present on this board\n"); +#endif + configure_module_pin_mux(qspi_pin_mux); + } else if (board_is_eposevm()) { + configure_module_pin_mux(rmii1_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#else + configure_module_pin_mux(qspi_pin_mux); +#endif + } +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} diff --git a/board/ti/beagle/Kconfig b/board/ti/beagle/Kconfig new file mode 100644 index 0000000000..c2eff9e71b --- /dev/null +++ b/board/ti/beagle/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_BEAGLE + +config SYS_BOARD + default "beagle" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "omap3_beagle" + +endif diff --git a/board/ti/beagle/MAINTAINERS b/board/ti/beagle/MAINTAINERS new file mode 100644 index 0000000000..2225fb63b0 --- /dev/null +++ b/board/ti/beagle/MAINTAINERS @@ -0,0 +1,6 @@ +BEAGLE BOARD +M: Tom Rini +S: Maintained +F: board/ti/beagle/ +F: include/configs/omap3_beagle.h +F: configs/omap3_beagle_defconfig diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile index 3018f6c63a..7a858be5e4 100644 --- a/board/ti/beagle/Makefile +++ b/board/ti/beagle/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := $(BOARD).o -COBJS-$(CONFIG_STATUS_LED) += led.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := beagle.o +obj-$(CONFIG_STATUS_LED) += led.o diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 36f73457ac..7b37fbe299 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -14,6 +14,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include #ifdef CONFIG_STATUS_LED #include #endif @@ -70,6 +72,17 @@ static struct { char env_setting[64]; } expansion_config; +static const struct ns16550_platdata beagle_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(beagle_uart) = { + "serial_omap", + &beagle_serial +}; + /* * Routine: board_init * Description: Early hardware init. @@ -103,22 +116,22 @@ int board_init(void) */ static int get_board_revision(void) { - int revision; - - if (!gpio_request(171, "") && - !gpio_request(172, "") && - !gpio_request(173, "")) { - - gpio_direction_input(171); - gpio_direction_input(172); - gpio_direction_input(173); - - revision = gpio_get_value(173) << 2 | - gpio_get_value(172) << 1 | - gpio_get_value(171); - } else { - printf("Error: unable to acquire board revision GPIOs\n"); - revision = -1; + static int revision = -1; + + if (revision == -1) { + if (!gpio_request(171, "rev0") && + !gpio_request(172, "rev1") && + !gpio_request(173, "rev2")) { + gpio_direction_input(171); + gpio_direction_input(172); + gpio_direction_input(173); + + revision = gpio_get_value(173) << 2 | + gpio_get_value(172) << 1 | + gpio_get_value(171); + } else { + printf("Error: unable to acquire board revision GPIOs\n"); + } } return revision; @@ -166,8 +179,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; } - case REVISION_XM_A: - case REVISION_XM_B: + case REVISION_XM_AB: case REVISION_XM_C: if (pop_mfr == 0) { /* 256MB DDR */ @@ -240,8 +252,7 @@ static void beagle_display_init(void) case REVISION_C4: omap3_dss_panel_config(&dvid_cfg); break; - case REVISION_XM_A: - case REVISION_XM_B: + case REVISION_XM_AB: case REVISION_XM_C: default: omap3_dss_panel_config(&dvid_cfg_xm); @@ -260,12 +271,11 @@ static void beagle_dvi_pup(void) case REVISION_AXBX: case REVISION_CX: case REVISION_C4: - case REVISION_XM_A: - gpio_request(170, ""); + gpio_request(170, "dvi"); gpio_direction_output(170, 0); gpio_set_value(170, 1); break; - case REVISION_XM_B: + case REVISION_XM_AB: case REVISION_XM_C: default: #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3) @@ -319,9 +329,13 @@ int misc_init_r(void) struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; + bool generate_fake_mac = false; + u32 value; /* Enable i2c2 pullup resisters */ - writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1); + value = readl(&prog_io_base->io1); + value &= ~(PRG_I2C2_PULLUPRESX); + writel(value, &prog_io_base->io1); switch (get_board_revision()) { case REVISION_AXBX: @@ -343,25 +357,16 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); break; - case REVISION_XM_A: - printf("Beagle xM Rev A\n"); - setenv("beaglerev", "xMA"); - MUX_BEAGLE_XM(); - /* Set VAUX2 to 1.8V for EHCI PHY */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, - TWL4030_PM_RECEIVER_VAUX2_VSEL_18, - TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); - break; - case REVISION_XM_B: - printf("Beagle xM Rev B\n"); - setenv("beaglerev", "xMB"); + case REVISION_XM_AB: + printf("Beagle xM Rev A/B\n"); + setenv("beaglerev", "xMAB"); MUX_BEAGLE_XM(); /* Set VAUX2 to 1.8V for EHCI PHY */ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, TWL4030_PM_RECEIVER_VAUX2_VSEL_18, TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); + generate_fake_mac = true; break; case REVISION_XM_C: printf("Beagle xM Rev C\n"); @@ -372,6 +377,7 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_VAUX2_VSEL_18, TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); + generate_fake_mac = true; break; default: printf("Beagle unknown 0x%02x\n", get_board_revision()); @@ -381,6 +387,7 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_VAUX2_VSEL_18, TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); + generate_fake_mac = true; } switch (get_expansion_id()) { @@ -468,8 +475,7 @@ int misc_init_r(void) twl4030_power_init(); switch (get_board_revision()) { - case REVISION_XM_A: - case REVISION_XM_B: + case REVISION_XM_AB: twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); break; default: @@ -500,6 +506,13 @@ int misc_init_r(void) musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); #endif + if (generate_fake_mac) { + u32 id[4]; + + get_dieid(id); + usb_fake_mac_from_die_id(id); + } + return 0; } @@ -521,6 +534,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) /* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) @@ -535,9 +555,10 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED }; -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); } int ehci_hcd_stop(int index) diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index 76be3589e0..6dd2ffe558 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -23,8 +23,7 @@ const omap3_sysinfo sysinfo = { #define REVISION_AXBX 0x7 #define REVISION_CX 0x6 #define REVISION_C4 0x5 -#define REVISION_XM_A 0x0 -#define REVISION_XM_B 0x1 +#define REVISION_XM_AB 0x0 #define REVISION_XM_C 0x2 /* diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c index 89b8dd3c3c..a913a4c84a 100644 --- a/board/ti/beagle/led.c +++ b/board/ti/beagle/led.c @@ -27,47 +27,46 @@ void green_led_on(void) } #endif +static int get_led_gpio(led_id_t mask) +{ +#ifdef STATUS_LED_BIT + if (STATUS_LED_BIT & mask) + return BEAGLE_LED_USR0; +#endif +#ifdef STATUS_LED_BIT1 + if (STATUS_LED_BIT1 & mask) + return BEAGLE_LED_USR1; +#endif + + return 0; +} + void __led_init (led_id_t mask, int state) { - __led_set (mask, state); + int toggle_gpio; + + toggle_gpio = get_led_gpio(mask); + + if (toggle_gpio && !gpio_request(toggle_gpio, "led")) + __led_set(mask, state); } void __led_toggle (led_id_t mask) { - int state, toggle_gpio = 0; -#ifdef STATUS_LED_BIT - if (!toggle_gpio && STATUS_LED_BIT & mask) - toggle_gpio = BEAGLE_LED_USR0; -#endif -#ifdef STATUS_LED_BIT1 - if (!toggle_gpio && STATUS_LED_BIT1 & mask) - toggle_gpio = BEAGLE_LED_USR1; -#endif + int state, toggle_gpio; + + toggle_gpio = get_led_gpio(mask); if (toggle_gpio) { - if (!gpio_request(toggle_gpio, "")) { - gpio_direction_output(toggle_gpio, 0); - state = gpio_get_value(toggle_gpio); - gpio_set_value(toggle_gpio, !state); - } + state = gpio_get_value(toggle_gpio); + gpio_direction_output(toggle_gpio, !state); } } void __led_set (led_id_t mask, int state) { -#ifdef STATUS_LED_BIT - if (STATUS_LED_BIT & mask) { - if (!gpio_request(BEAGLE_LED_USR0, "")) { - gpio_direction_output(BEAGLE_LED_USR0, 0); - gpio_set_value(BEAGLE_LED_USR0, state); - } - } -#endif -#ifdef STATUS_LED_BIT1 - if (STATUS_LED_BIT1 & mask) { - if (!gpio_request(BEAGLE_LED_USR1, "")) { - gpio_direction_output(BEAGLE_LED_USR1, 0); - gpio_set_value(BEAGLE_LED_USR1, state); - } - } -#endif + int toggle_gpio; + + toggle_gpio = get_led_gpio(mask); + if (toggle_gpio) + gpio_direction_output(toggle_gpio, state); } diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig new file mode 100644 index 0000000000..a305ff1044 --- /dev/null +++ b/board/ti/beagle_x15/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15 + +config SYS_BOARD + default "beagle_x15" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "beagle_x15" + +endif diff --git a/board/ti/beagle_x15/MAINTAINERS b/board/ti/beagle_x15/MAINTAINERS new file mode 100644 index 0000000000..3f84defcee --- /dev/null +++ b/board/ti/beagle_x15/MAINTAINERS @@ -0,0 +1,6 @@ +BEAGLE X15 +M: Felipe Balbi +S: Maintained +F: board/ti/beagle_x15/ +F: include/configs/beagle_x15.h +F: configs/beagle_x15_defconfig diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile new file mode 100644 index 0000000000..5cd6873f5e --- /dev/null +++ b/board/ti/beagle_x15/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c new file mode 100644 index 0000000000..db96e347e7 --- /dev/null +++ b/board/ti/beagle_x15/board.c @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mux_data.h" + +#ifdef CONFIG_DRIVER_TI_CPSW +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: BeagleBoard x15\n" +}; + +static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { + .dmm_lisa_map_3 = 0x80740300, + .is_ma_present = 0x1 +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &beagle_x15_lisa_regs; +} + +static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xceef266b, + .sdram_tim2 = 0x328f7fda, + .sdram_tim3 = 0x027f88a8, + .read_idle_ctrl = 0x00050001, + .zq_config = 0x0007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0e24400a, + .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00740074, + .emif_ddr_ext_phy_ctrl_3 = 0x00780078, + .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, + .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { + 0x00800080, + 0x00360036, + 0x00340034, + 0x00360036, + 0x00350035, + 0x00350035, + + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + + 0x00430043, + 0x003e003e, + 0x004a004a, + 0x00470047, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040 +}; + +static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xceef266b, + .sdram_tim2 = 0x328f7fda, + .sdram_tim3 = 0x027f88a8, + .read_idle_ctrl = 0x00050001, + .zq_config = 0x0007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0e24400a, + .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00820082, + .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, + .emif_ddr_ext_phy_ctrl_4 = 0x00800080, + .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { + 0x00800080, + 0x00370037, + 0x00390039, + 0x00360036, + 0x00370037, + 0x00350035, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x00540054, + 0x00540054, + 0x004e004e, + 0x004c004c, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040 +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + switch (emif_nr) { + case 1: + *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; + break; + case 2: + *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; + break; + } +} + +void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{ + switch (emif_nr) { + case 1: + *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); + break; + case 2: + *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); + break; + } +} + +struct vcores_data beagle_x15_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS45, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS6, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS45, + .iva.pmic = &tps659038, +}; + +void hw_data_init(void) +{ + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &beagle_x15_volts; + *ctrl = &dra7xx_ctrl; +} + +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +int board_late_init(void) +{ + init_sata(0); + /* + * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds + * This is the POWERHOLD-in-Low behavior. + */ + palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); + return 0; +} + +static void do_set_mux32(u32 base, + struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 2, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif + +#ifdef CONFIG_USB_XHCI_OMAP +int board_usb_init(int index, enum usb_init_type init) +{ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, + OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M); + + return 0; +} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h new file mode 100644 index 0000000000..2294abec71 --- /dev/null +++ b/board/ti/beagle_x15/mux_data.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_ + +#include + +const struct pad_conf_entry core_padconf_array_essential[] = { + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ + {RGMII0_TXC, (M0) }, + {RGMII0_TXCTL, (M0) }, + {RGMII0_TXD3, (M0) }, + {RGMII0_TXD2, (M0) }, + {RGMII0_TXD1, (M0) }, + {RGMII0_TXD0, (M0) }, + {RGMII0_RXC, (IEN | M0) }, + {RGMII0_RXCTL, (IEN | M0) }, + {RGMII0_RXD3, (IEN | M0) }, + {RGMII0_RXD2, (IEN | M0) }, + {RGMII0_RXD1, (IEN | M0) }, + {RGMII0_RXD0, (IEN | M0) }, + {USB1_DRVVBUS, (M0 | FSC) }, + {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ +}; +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig new file mode 100644 index 0000000000..3bbd86644d --- /dev/null +++ b/board/ti/dra7xx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DRA7XX_EVM + +config SYS_BOARD + default "dra7xx" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "dra7xx_evm" + +endif diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS new file mode 100644 index 0000000000..5ec67697cf --- /dev/null +++ b/board/ti/dra7xx/MAINTAINERS @@ -0,0 +1,8 @@ +DRA7XX BOARD +M: Lokesh Vutla +S: Maintained +F: board/ti/dra7xx/ +F: include/configs/dra7xx_evm.h +F: configs/dra7xx_evm_defconfig +F: configs/dra7xx_evm_qspiboot_defconfig +F: configs/dra7xx_evm_uart3_defconfig diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile index e558f4c89f..434e8d128e 100644 --- a/board/ti/dra7xx/Makefile +++ b/board/ti/dra7xx/Makefile @@ -5,29 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := evm.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := evm.o diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README new file mode 100644 index 0000000000..533da01a34 --- /dev/null +++ b/board/ti/dra7xx/README @@ -0,0 +1,26 @@ +Summary +======= + +This document covers various features of the 'dra7xx_evm' build and some +related uses. + +eMMC boot partition use +======================= + +It is possible, depending on SYSBOOT configuration to boot from the eMMC +boot partitions using (name depending on documentation referenced) +Alternative Boot operation mode or Boot Sequence Option 1/2. In this +example we load MLO and u-boot.img from the build into DDR and then use +'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to +set boot0 as the boot device. +U-Boot # setenv autoload no +U-Boot # usb start +U-Boot # dhcp +U-Boot # mmc dev 1 1 +U-Boot # tftp ${loadaddr} dra7xx/MLO +U-Boot # mmc write ${loadaddr} 0 100 +U-Boot # tftp ${loadaddr} dra7xx/u-boot.img +U-Boot # mmc write ${loadaddr} 300 400 +U-Boot # mmc bootbus 1 2 0 2 +U-Boot # mmc partconf 1 1 1 0 +U-Boot # mmc rst-function 1 1 diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 8190e4bafb..65222419eb 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -12,23 +12,66 @@ */ #include #include +#include +#include +#include #include #include +#include +#include #include "mux_data.h" -#ifdef CONFIG_USB_EHCI -#include -#include -#include +#ifdef CONFIG_DRIVER_TI_CPSW +#include #endif DECLARE_GLOBAL_DATA_PTR; +/* GPIO 7_11 */ +#define GPIO_DDR_VTT_EN 203 + const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; +/* + * Adjust I/O delays on the Tx control and data lines of each MAC port. This + * is a workaround in order to work properly with the DP83865 PHYs on the EVM. + * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we + * essentially need to counteract the DRA7xx internal delay, and we do this + * by delaying the control and data lines. If not using this PHY, you probably + * don't need to do this stuff! + */ +static void dra7xx_adj_io_delay(const struct io_delay *io_dly) +{ + int i = 0; + u32 reg_val; + u32 delta; + u32 coarse; + u32 fine; + + writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); + + while(io_dly[i].addr) { + writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, + io_dly[i].addr); + delta = io_dly[i].dly; + reg_val = readl(io_dly[i].addr) & 0x3ff; + coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); + coarse = (coarse > 0x1F) ? (0x1F) : (coarse); + fine = (reg_val & 0x1F) + (delta & 0x1F); + fine = (fine > 0x1F) ? (0x1F) : (fine); + reg_val = CFG_IO_DELAY_ACCESS_PATTERN | + CFG_IO_DELAY_LOCK_MASK | + ((coarse << 5) | (fine)); + writel(reg_val, io_dly[i].addr); + i++; + } + + writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); +} + /** * @brief board_init * @@ -42,20 +85,14 @@ int board_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - return 0; -} - -/** - * @brief misc_init_r - Configure EVM board specific configurations - * such as power configurations, ethernet initialization as phase2 of - * boot sequence - * - * @return 0 - */ -int misc_init_r(void) +int board_late_init(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (omap_revision() == DRA722_ES1_0) + setenv("board_name", "dra72x"); + else + setenv("board_name", "dra7xx"); +#endif return 0; } @@ -85,3 +122,171 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +extern u32 *const omap_si_rev; + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 2, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 3, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + const struct io_delay io_dly[] = { + {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, + {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, + {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, + {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, + {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, + {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, + {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, + {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, + {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, + {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, + {0} + }; + + /* Adjust IO delay for RGMII tx path */ + dra7xx_adj_io_delay(io_dly); + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + if (*omap_si_rev == DRA722_ES1_0) + cpsw_data.active_slave = 1; + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +/* VTT regulator enable */ +static inline void vtt_regulator_enable(void) +{ + if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) + return; + + /* Do not enable VTT for DRA722 */ + if (omap_revision() == DRA722_ES1_0) + return; + + /* + * EVM Rev G and later use gpio7_11 for DDR3 termination. + * This is safe enough to do on older revs. + */ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); +} + +int board_early_init_f(void) +{ + vtt_regulator_enable(); + return 0; +} +#endif diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index ec8342276b..48240779c9 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -21,6 +21,37 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ +#if defined(CONFIG_NOR) + /* NOR only pin-mux */ + {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */ + {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */ + {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */ + {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */ + {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */ + {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */ + {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */ + {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */ + {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */ + {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */ + {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */ + {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */ + {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */ + {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */ + {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */ + {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */ + {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */ + {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */ + {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */ + {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */ + {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */ + {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */ + {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */ + {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */ + {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */ + {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */ + {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */ +#else + /* eMMC pinmux */ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ @@ -31,11 +62,83 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ +#endif +#if (CONFIG_CONS_INDEX == 1) {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ +#elif (CONFIG_CONS_INDEX == 3) + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ +#endif {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ + {RGMII0_TXC, (M0) }, + {RGMII0_TXCTL, (M0) }, + {RGMII0_TXD3, (M0) }, + {RGMII0_TXD2, (M0) }, + {RGMII0_TXD1, (M0) }, + {RGMII0_TXD0, (M0) }, + {RGMII0_RXC, (IEN | M0) }, + {RGMII0_RXCTL, (IEN | M0) }, + {RGMII0_RXD3, (IEN | M0) }, + {RGMII0_RXD2, (IEN | M0) }, + {RGMII0_RXD1, (IEN | M0) }, + {RGMII0_RXD0, (IEN | M0) }, + {VIN2A_D12, (M3) }, + {VIN2A_D13, (M3) }, + {VIN2A_D14, (M3) }, + {VIN2A_D15, (M3) }, + {VIN2A_D16, (M3) }, + {VIN2A_D17, (M3) }, + {VIN2A_D18, (IEN | M3)}, + {VIN2A_D19, (IEN | M3)}, + {VIN2A_D20, (IEN | M3)}, + {VIN2A_D21, (IEN | M3)}, + {VIN2A_D22, (IEN | M3)}, + {VIN2A_D23, (IEN | M3)}, +#if defined(CONFIG_NAND) || defined(CONFIG_NOR) + /* NAND / NOR pin-mux */ + {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ + {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */ + {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */ + {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */ + {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */ + {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */ + {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */ + {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */ + {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */ + {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */ + {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */ + {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */ + {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */ + {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */ + {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */ + {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */ + {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */ + {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */ + {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */ + {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */ + {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */ + {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */ + /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */ +#else + /* QSPI pin-mux */ + {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ + {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ + {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ + {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ + {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ + {GPMC_A18, (M1)}, /* QSPI1_SCLK */ + {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */ + {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ + {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ + {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ +#endif /* CONFIG_NAND || CONFIG_NOR */ + {USB2_DRVVBUS, (M0 | IEN | FSC) }, + {SPI1_CS1, (PEN | IDIS | M14) }, }; #endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/board/ti/evm/Kconfig b/board/ti/evm/Kconfig new file mode 100644 index 0000000000..f02aa31a91 --- /dev/null +++ b/board/ti/evm/Kconfig @@ -0,0 +1,38 @@ +if TARGET_OMAP3_EVM + +config SYS_BOARD + default "evm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "omap3_evm" + +endif + +if TARGET_OMAP3_EVM_QUICK_MMC + +config SYS_BOARD + default "evm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "omap3_evm_quick_mmc" + +endif + +if TARGET_OMAP3_EVM_QUICK_NAND + +config SYS_BOARD + default "evm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "omap3_evm_quick_nand" + +endif diff --git a/board/ti/evm/MAINTAINERS b/board/ti/evm/MAINTAINERS new file mode 100644 index 0000000000..d0b27882bc --- /dev/null +++ b/board/ti/evm/MAINTAINERS @@ -0,0 +1,14 @@ +EVM BOARD +M: Tom Rini +S: Maintained +F: board/ti/evm/ +F: include/configs/omap3_evm.h +F: configs/omap3_evm_defconfig + +OMAP3_EVM_QUICK_MMC BOARD +#M: - +S: Maintained +F: include/configs/omap3_evm_quick_mmc.h +F: configs/omap3_evm_quick_mmc_defconfig +F: include/configs/omap3_evm_quick_nand.h +F: configs/omap3_evm_quick_nand_defconfig diff --git a/board/ti/evm/Makefile b/board/ti/evm/Makefile index 0f8cf446ba..b88ab8f517 100644 --- a/board/ti/evm/Makefile +++ b/board/ti/evm/Makefile @@ -5,21 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := evm.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-y := evm.o diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index c71c218529..3f93d9cbe2 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include "evm.h" @@ -146,8 +147,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif #if defined(CONFIG_CMD_NET) @@ -264,3 +265,10 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0, -1, -1); } #endif + +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h index f50193d99a..91e9b88c54 100644 --- a/board/ti/evm/evm.h +++ b/board/ti/evm/evm.h @@ -300,7 +300,7 @@ static void reset_net_chip(void); MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig new file mode 100644 index 0000000000..384b175e9c --- /dev/null +++ b/board/ti/ks2_evm/Kconfig @@ -0,0 +1,38 @@ +if TARGET_K2E_EVM + +config SYS_BOARD + default "ks2_evm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "k2e_evm" + +endif + +if TARGET_K2HK_EVM + +config SYS_BOARD + default "ks2_evm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "k2hk_evm" + +endif + +if TARGET_K2L_EVM + +config SYS_BOARD + default "ks2_evm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "k2l_evm" + +endif diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS new file mode 100644 index 0000000000..87c36c9d14 --- /dev/null +++ b/board/ti/ks2_evm/MAINTAINERS @@ -0,0 +1,10 @@ +KS2_EVM BOARD +M: Vitaly Andrianov +S: Maintained +F: board/ti/ks2_evm/ +F: include/configs/k2hk_evm.h +F: configs/k2hk_evm_defconfig +F: include/configs/k2e_evm.h +F: configs/k2e_evm_defconfig +F: include/configs/k2l_evm.h +F: configs/k2l_evm_defconfig diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile new file mode 100644 index 0000000000..071dbee180 --- /dev/null +++ b/board/ti/ks2_evm/Makefile @@ -0,0 +1,15 @@ +# +# KS2-EVM: board Makefile +# (C) Copyright 2012-2014 +# Texas Instruments Incorporated, +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o +obj-y += ddr3_cfg.o +obj-$(CONFIG_K2HK_EVM) += board_k2hk.o +obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o +obj-$(CONFIG_K2E_EVM) += board_k2e.o +obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o +obj-$(CONFIG_K2L_EVM) += board_k2l.o +obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README new file mode 100644 index 0000000000..9ee90a4f9d --- /dev/null +++ b/board/ti/ks2_evm/README @@ -0,0 +1,171 @@ +U-Boot port for Texas Instruments Keystone II EVM boards +======================================================== + +Author: Murali Karicheri + +This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards. +Documentation for this board can be found at +http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx +https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html +https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html + +The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K. +More details on these SoCs are available at company websites + K2K: http://www.ti.com/product/tci6638k2k + K2H: http://www.ti.com/product/tci6638k2h + +The K2E SoC details are available at + http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + +The K2L SoC details are available at + http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf + +Board configuration: +==================== + +Some of the peripherals that are configured by u-boot ++------+-------+-------+-----------+-----------+-------+-------+----+ +| |DDR3 |NAND |MSM SRAM |ETH ports |UART |I2C |SPI | ++------+-------+-------+-----------+-----------+-------+-------+----+ +|K2HK |2 |512MB |6MB |4(2) |2 |3 |3 | +|K2E |4 |512MB |2MB |8(2) |2 |3 |3 | +|K2L |2 |512MB |2MB |4(2) |4 |3 |3 | ++------+-------+-------+-----------+-----------+-------+-------+----+ + +There are only 2 eth port installed on the boards. + +There are separate PLLs to drive clocks to Tetris ARM and Peripherals. +To bring up SMP Linux on this board, there is a boot monitor +code that will be installed in MSMC SRAM. There is command available +to install this image from u-boot. + +The port related files can be found at following folders + keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ + EVMs board files: board/ti/k2s_evm/ + +Board configuration files: +include/configs/k2hk_evm.h +include/configs/k2e_evm.h +include/configs/k2l_evm.h +include/configs/k2l_evm.h + +As u-boot is migrating to Kconfig there is also board defconfig files +configs/k2e_evm_defconfig +configs/k2hk_evm_defconfig +configs/k2l_evm_defconfig + +Supported boot modes: + - SPI NOR boot + - AEMIF NAND boot + +Supported image formats: + - u-boot.bin: for loading and running u-boot.bin through Texas instruments + code composure studio (CCS) + - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot + +Build instructions: +=================== +Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly. +Don't forget to add ARCH=arm and CROSS_COMPILE. + +To build u-boot.bin + >make k2hk_evm_defconfig + >make u-boot-spi.gph + +To build u-boot-spi.gph + >make k2hk_evm_defconfig + >make u-boot-spi.gph + +To build u-boot-nand.gph + >make k2hk_evm_defconfig + >make u-boot-nand.gph + +Load and Run U-Boot on keystone EVMs using CCS +========================================= + +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin +on EVM. See instructions at below link for installing CCS on a Windows PC. +http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# +Installing_Code_Composer_Studio +Use u-boot.bin from the build folder for loading and running u-boot binary +on EVM. Follow instructions at +K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup +K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup +K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup + +to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" +and Power ON the EVM. Follow instructions to connect serial port of EVM to +PC and start TeraTerm or Hyper Terminal. + +Start CCS on a Windows machine and Launch Target +configuration as instructed at http://processors.wiki.ti.com/index.php/ +MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. +The instructions provided in the above link uses a script for +loading the u-boot binary on the target EVM. Instead do the following:- + +1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D + is connected: Unknown)" at the debug window (This is created once Target + configuration is launched) and select "Connect Target". +2. Once target connect is successful, choose Tools->Load Memory option from the + top level menu. At the Load Memory window, choose the file u-boot.bin + through "Browse" button and click "next >" button. In the next window, enter + Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" + button. +3. Click View -> Registers from the top level menu to view registers window. +4. From Registers, window expand "Core Registers" to view PC. Edit PC value + to be 0xc001000. From the "Run" top level menu, select "Free Run" +5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as + below and type any key to stop autoboot as instructed := + +U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) + +I2C: ready +Detected SO-DIMM [SQR-SD3T-2G1333SED] +DRAM: 1.1 GiB +NAND: 512 MiB +Net: K2HK_EMAC +Warning: K2HK_EMAC using MAC address from net device +, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 +Hit any key to stop autoboot: 0 + +SPI NOR Flash programming instructions +====================================== +U-Boot image can be flashed to first 512KB of the NOR flash using following +instructions: + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L + EVM using CCS", but using address 0x87000000. +4. Free Run the target as described earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv addr_uboot 0x87000000 + setenv filesize + run burn_uboot_spi + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "SPI Little Endian Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/*_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. + +AEMIF NAND Flash programming instructions +====================================== +U-Boot image can be flashed to first 1024KB of the NAND flash using following +instructions: + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as described earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv filesize + run burn_uboot_nand + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "ARM NAND Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/*_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c new file mode 100644 index 0000000000..04ec675103 --- /dev/null +++ b/board/ti/ks2_evm/board.c @@ -0,0 +1,260 @@ +/* + * Keystone : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "board.h" +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct aemif_config aemif_configs[] = { + { /* CS0 */ + .mode = AEMIF_MODE_NAND, + .wr_setup = 0xf, + .wr_strobe = 0x3f, + .wr_hold = 7, + .rd_setup = 0xf, + .rd_strobe = 0x3f, + .rd_hold = 7, + .turn_around = 3, + .width = AEMIF_WIDTH_8, + }, +}; + +int dram_init(void) +{ + ddr3_init(); + + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); + ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +int get_eth_env_param(char *env_name) +{ + char *env; + int res = -1; + + env = getenv(env_name); + if (env) + res = simple_strtol(env, NULL, 0); + + return res; +} + +int board_eth_init(bd_t *bis) +{ + int j; + int res; + int port_num; + char link_type_name[32]; + + /* By default, select PA PLL clock as PA clock source */ + if (psc_enable_module(KS2_LPSC_PA)) + return -1; + if (psc_enable_module(KS2_LPSC_CPGMAC)) + return -1; + if (psc_enable_module(KS2_LPSC_CRYPTO)) + return -1; + pass_pll_pa_clk_enable(); + + port_num = get_num_eth_ports(); + + for (j = 0; j < port_num; j++) { + sprintf(link_type_name, "sgmii%d_link_type", j); + res = get_eth_env_param(link_type_name); + if (res >= 0) + eth_priv_cfg[j].sgmii_link_type = res; + + keystone2_emac_initialize(ð_priv_cfg[j]); + } + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ + spl_init_keystone_plls(); + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ +#if defined(CONFIG_SPL_SPI_LOAD) + return BOOT_DEVICE_SPI; +#else + puts("Unknown boot device\n"); + hang(); +#endif +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + int lpae; + char *env; + char *endp; + int nbanks; + u64 size[2]; + u64 start[2]; + int nodeoffset; + u32 ddr3a_size; + int unitrd_fixup = 0; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + env = getenv("uinitrd_fixup"); + unitrd_fixup = env && simple_strtol(env, NULL, 0); + + ddr3a_size = 0; + if (lpae) { + env = getenv("ddr3a_size"); + if (env) + ddr3a_size = simple_strtol(env, NULL, 10); + if ((ddr3a_size != 8) && (ddr3a_size != 4)) + ddr3a_size = 0; + } + + nbanks = 1; + start[0] = bd->bi_dram[0].start; + size[0] = bd->bi_dram[0].size; + + /* adjust memory start address for LPAE */ + if (lpae) { + start[0] -= CONFIG_SYS_SDRAM_BASE; + start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + } + + if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { + size[1] = ((u64)ddr3a_size - 2) << 30; + start[1] = 0x880000000; + nbanks++; + } + + /* reserve memory at start of bank */ + env = getenv("mem_reserve_head"); + if (env) { + start[0] += ustrtoul(env, &endp, 0); + size[0] -= ustrtoul(env, &endp, 0); + } + + env = getenv("mem_reserve"); + if (env) + size[0] -= ustrtoul(env, &endp, 0); + + fdt_fixup_memory_banks(blob, start, size, nbanks); + + /* Fix up the initrd */ + if (lpae && unitrd_fixup) { + int err; + u32 *prop1, *prop2; + u64 initrd_start, initrd_end; + + nodeoffset = fdt_path_offset(blob, "/chosen"); + if (nodeoffset >= 0) { + prop1 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-start", NULL); + prop2 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-end", NULL); + if (prop1 && prop2) { + initrd_start = __be32_to_cpu(*prop1); + initrd_start -= CONFIG_SYS_SDRAM_BASE; + initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start = __cpu_to_be64(initrd_start); + initrd_end = __be32_to_cpu(*prop2); + initrd_end -= CONFIG_SYS_SDRAM_BASE; + initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end = __cpu_to_be64(initrd_end); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-start"); + if (err < 0) + puts("error deleting initrd-start\n"); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-end"); + if (err < 0) + puts("error deleting initrd-end\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-start", + &initrd_start, + sizeof(initrd_start)); + if (err < 0) + puts("error adding initrd-start\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-end", + &initrd_end, + sizeof(initrd_end)); + if (err < 0) + puts("error adding linux,initrd-end\n"); + } + } + } + + return 0; +} + +void ft_board_setup_ex(void *blob, bd_t *bd) +{ + int lpae; + u64 size; + char *env; + u64 *reserve_start; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + + if (lpae) { + /* + * the initrd and other reserved memory areas are + * embedded in in the DTB itslef. fix up these addresses + * to 36 bit format + */ + reserve_start = (u64 *)((char *)blob + + fdt_off_mem_rsvmap(blob)); + while (1) { + *reserve_start = __cpu_to_be64(*reserve_start); + size = __cpu_to_be64(*(reserve_start + 1)); + if (size) { + *reserve_start -= CONFIG_SYS_SDRAM_BASE; + *reserve_start += + CONFIG_SYS_LPAE_SDRAM_BASE; + *reserve_start = + __cpu_to_be64(*reserve_start); + } else { + break; + } + reserve_start += 2; + } + } + + ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); +} +#endif diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h new file mode 100644 index 0000000000..2bbd79245b --- /dev/null +++ b/board/ti/ks2_evm/board.h @@ -0,0 +1,20 @@ +/* + * K2HK EVM : Board common header + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KS2_BOARD +#define _KS2_BOARD + +#include + +extern struct eth_priv_t eth_priv_cfg[]; + +int get_num_eth_ports(void); +void spl_init_keystone_plls(void); + +#endif diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c new file mode 100644 index 0000000000..43dfc48a53 --- /dev/null +++ b/board/ti/ks2_evm/board_k2e.c @@ -0,0 +1,131 @@ +/* + * K2E EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 100000000, + [alt_core_clk] = 100000000, + [pa_clk] = 100000000, + [ddr3_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, +}; + +static struct pll_init_data core_pll_config[] = { + CORE_PLL_800, + CORE_PLL_850, + CORE_PLL_1000, + CORE_PLL_1250, + CORE_PLL_1350, + CORE_PLL_1400, + CORE_PLL_1500, +}; + +static struct pll_init_data pa_pll_config = + PASS_PLL_1000; + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2E_EMAC0", + .rx_flow = 0, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2E_EMAC1", + .rx_flow = 8, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2E_EMAC2", + .rx_flow = 16, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC3", + .rx_flow = 24, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC4", + .rx_flow = 32, + .phy_addr = 4, + .slave_port = 5, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC5", + .rx_flow = 40, + .phy_addr = 5, + .slave_port = 6, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC6", + .rx_flow = 48, + .phy_addr = 6, + .slave_port = 7, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC7", + .rx_flow = 56, + .phy_addr = 7, + .slave_port = 8, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_800, +}; + +void spl_init_keystone_plls(void) +{ + init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); +} +#endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c new file mode 100644 index 0000000000..ed181f44b8 --- /dev/null +++ b/board/ti/ks2_evm/board_k2hk.c @@ -0,0 +1,114 @@ +/* + * K2HK EVM : Board initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 122880000, + [alt_core_clk] = 125000000, + [pa_clk] = 122880000, + [tetris_clk] = 125000000, + [ddr3a_clk] = 100000000, + [ddr3b_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_srio_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, + [rp1_clk] = 123456789 +}; + +static struct pll_init_data core_pll_config[] = { + CORE_PLL_799, + CORE_PLL_999, + CORE_PLL_1200, +}; + +static struct pll_init_data tetris_pll_config[] = { + TETRIS_PLL_800, + TETRIS_PLL_1000, + TETRIS_PLL_1200, + TETRIS_PLL_1350, + TETRIS_PLL_1400, +}; + +static struct pll_init_data pa_pll_config = + PASS_PLL_983; + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2HK_EMAC", + .rx_flow = 22, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC1", + .rx_flow = 23, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC2", + .rx_flow = 24, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2HK_EMAC3", + .rx_flow = 25, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + + speed = get_max_arm_speed(); + init_pll(&tetris_pll_config[speed]); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_799, + TETRIS_PLL_500, +}; + +void spl_init_keystone_plls(void) +{ + init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); +} +#endif diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c new file mode 100644 index 0000000000..729a193239 --- /dev/null +++ b/board/ti/ks2_evm/board_k2l.c @@ -0,0 +1,110 @@ +/* + * K2L EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 122880000, + [alt_core_clk] = 100000000, + [pa_clk] = 122880000, + [tetris_clk] = 122880000, + [ddr3_clk] = 100000000, + [pcie_clk] = 100000000, + [sgmii_clk] = 156250000, + [usb_clk] = 100000000, +}; + +static struct pll_init_data core_pll_config[] = { + CORE_PLL_799, + CORE_PLL_1000, + CORE_PLL_1198, +}; + +static struct pll_init_data tetris_pll_config[] = { + TETRIS_PLL_799, + TETRIS_PLL_1000, + TETRIS_PLL_1198, + TETRIS_PLL_1352, + TETRIS_PLL_1401, +}; + +static struct pll_init_data pa_pll_config = + PASS_PLL_983; + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2L_EMAC", + .rx_flow = 0, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2L_EMAC1", + .rx_flow = 8, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2L_EMAC2", + .rx_flow = 16, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2L_EMAC3", + .rx_flow = 32, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + + speed = get_max_arm_speed(); + init_pll(&tetris_pll_config[speed]); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_799, + TETRIS_PLL_491, +}; + +void spl_init_keystone_plls(void) +{ + init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); +} +#endif diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c new file mode 100644 index 0000000000..ab44676793 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -0,0 +1,206 @@ +/* + * Keystone2: DDR3 configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* DDR3 PHY configuration data with 1600M rate, 8GB size */ +struct ddr3_phy_config ddr3phy_1600_8g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, 8GB size */ +struct ddr3_emif_config ddr3_1600_8g = { + .sdcfg = 0x6200CE6Aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001869ul, +}; + +#ifdef CONFIG_K2HK_EVM +/* DDR3 PHY configuration data with 1333M rate, and 2GB size */ +struct ddr3_phy_config ddr3phy_1333_2g = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */ +struct ddr3_emif_config ddr3_1333_2g = { + .sdcfg = 0x62008C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001457ul, +}; +#endif + +#ifdef CONFIG_K2E_EVM +/* DDR3 PHY configuration data with 1600M rate, and 4GB size */ +struct ddr3_phy_config ddr3phy_1600_4g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x08861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x9D9CBB66ul, + .dtpr1 = 0x12840300ul, + .dtpr2 = 0x5002D200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */ +struct ddr3_emif_config ddr3_1600_4g = { + .sdcfg = 0x6200CE62ul, + .sdtim1 = 0x166C9855ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x421DFF53ul, + .sdtim4 = 0x543F07FFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; +#endif + +struct ddr3_phy_config ddr3phy_1600_2g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x9D5CBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x5002D200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +struct ddr3_emif_config ddr3_1600_2g = { + .sdcfg = 0x6200CE62ul, + .sdtim1 = 0x166C9855ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF53ul, + .sdtim4 = 0x543F0CFFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; + +int ddr3_get_dimm_params(char *dimm_name) +{ + int ret; + int old_bus; + u8 spd_params[256]; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, spd_params, 256); + + i2c_set_bus_num(old_bus); + + dimm_name[0] = '\0'; + + if (ret) { + puts("Cannot read DIMM params\n"); + return 1; + } + + /* + * We need to convert spd data to dimm parameters + * and to DDR3 EMIF and PHY regirsters values. + * For now we just return DIMM type string value. + * Caller may use this value to choose appropriate + * a pre-set DDR3 configuration + */ + + strncpy(dimm_name, (char *)&spd_params[0x80], 18); + dimm_name[18] = '\0'; + + return 0; +} diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h new file mode 100644 index 0000000000..5bd786cff8 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -0,0 +1,27 @@ +/* + * Keystone2: DDR3 configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR3_CFG_H +#define __DDR3_CFG_H + +extern struct ddr3_phy_config ddr3phy_1600_8g; +extern struct ddr3_emif_config ddr3_1600_8g; + +extern struct ddr3_phy_config ddr3phy_1333_2g; +extern struct ddr3_emif_config ddr3_1333_2g; + +extern struct ddr3_phy_config ddr3phy_1600_4g; +extern struct ddr3_emif_config ddr3_1600_4g; + +extern struct ddr3_phy_config ddr3phy_1600_2g; +extern struct ddr3_emif_config ddr3_1600_2g; + +int ddr3_get_dimm_params(char *dimm_name); + +#endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c new file mode 100644 index 0000000000..40fd96607d --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -0,0 +1,55 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "ddr3_cfg.h" +#include + +static int ddr3_size; +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +void ddr3_init(void) +{ + char dimm_name[32]; + + if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) + init_pll(&ddr3_400); + + ddr3_get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + /* 8G SO-DIMM */ + ddr3_size = 8; + printf("DRAM: 8 GiB\n"); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); + } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) { + /* 4G SO-DIMM */ + ddr3_size = 4; + printf("DRAM: 4 GiB\n"); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); + } +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c new file mode 100644 index 0000000000..a1c3d05f8e --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -0,0 +1,104 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "ddr3_cfg.h" +#include +#include + +static int ddr3_size; + +struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); +struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); + +void ddr3_init(void) +{ + char dimm_name[32]; + + ddr3_get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + init_pll(&ddr3a_400); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1600_8g); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1600_8g); + } + + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_8g); + printf("DRAM: Capacity 8 GiB (includes reported below)\n"); + ddr3_size = 8; + } else { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_1600_8g.sdcfg |= 0x1000; + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_8g); + printf("DRAM: Capacity 4 GiB (includes reported below)\n"); + ddr3_size = 4; + } + } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { + init_pll(&ddr3a_333); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3phy_1333_2g.zq0cr1 |= 0x10000; + ddr3phy_1333_2g.zq1cr1 |= 0x10000; + ddr3phy_1333_2g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1333_2g); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1333_2g); + } + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_2g); + ddr3_size = 2; + printf("DRAM: 2 GiB"); + } else { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); + ddr3_1333_2g.sdcfg |= 0x1000; + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_2g); + ddr3_size = 1; + printf("DRAM: 1 GiB"); + } + } else { + printf("Unknown SO-DIMM. Cannot configure DDR3\n"); + while (1) + ; + } + + /* Apply the workaround for PG 1.0 and 1.1 Silicons */ + if (cpu_revision() <= 1) + ddr3_err_reset_workaround(); +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c new file mode 100644 index 0000000000..15a14f2aaf --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2l.c @@ -0,0 +1,38 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "ddr3_cfg.h" +#include + +static int ddr3_size; +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +void ddr3_init(void) +{ + init_pll(&ddr3_400); + + /* No SO-DIMM, 2GB discreet DDR */ + printf("DRAM: 2 GiB\n"); + ddr3_size = 2; + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/board/ti/omap1510inn/Makefile b/board/ti/omap1510inn/Makefile deleted file mode 100644 index ad5a7eb94e..0000000000 --- a/board/ti/omap1510inn/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := omap1510innovator.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ti/omap1510inn/config.mk b/board/ti/omap1510inn/config.mk deleted file mode 100644 index 67fe0bdf8f..0000000000 --- a/board/ti/omap1510inn/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# TI Innovator board with OMAP1510 (ARM925T) cpu -# see http://www.ti.com/ for more information on Texas Insturments -# -# Innovator has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - - -CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap1510inn/lowlevel_init.S b/board/ti/omap1510inn/lowlevel_init.S deleted file mode 100644 index 4d3ec39a65..0000000000 --- a/board/ti/omap1510inn/lowlevel_init.S +++ /dev/null @@ -1,380 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * - * -- Some bits of code used from rrload's head_OMAP1510.s -- - * Copyright (C) 2002 RidgeRun, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#if defined(CONFIG_OMAP1510) -#include <./configs/omap1510.h> -#endif - -#define OMAP1510_CLKS ((1< - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void flash__init (void); -static void ether__init (void); - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* arch number of OMAP 1510-Board */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - -/* kk - this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ - /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ - - /* setup gpio direction to match board (no floats!) */ - /**gdir = 0xCFF9; */ - /**mdir = 0x103F; */ - - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -static void flash__init (void) -{ -#define CS0_CHIP_SELECT_REG 0xfffecc10 -#define CS3_CHIP_SELECT_REG 0xfffecc1c -#define EMIFS_GlB_Config_REG 0xfffecc0c - - { - unsigned int regval; - - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - regval = regval | 0x0001; /* Turn off write protection for flash devices. */ - if (regval & 0x0002) { - regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ - /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ - /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ - /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ - } - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; - } -} - - -/****************************** - Routine: - Description: -******************************/ -static void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0800000b - /* take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - */ - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); -} - - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/ti/omap5912osk/Makefile b/board/ti/omap5912osk/Makefile deleted file mode 100644 index b2727de687..0000000000 --- a/board/ti/omap5912osk/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := omap5912osk.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ti/omap5912osk/config.mk b/board/ti/omap5912osk/config.mk deleted file mode 100644 index 5b8d952ba6..0000000000 --- a/board/ti/omap5912osk/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002-2004 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# (C) Copyright 2004 -# Texas Instruments, -# Rishi Bhattacharya -# -# TI OSK board with OMAP5912 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# OSK has 1 bank of 32 MB SDRAM -# Physical Address: -# 1000'0000 to 1200'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# When running from RAM use address 1108'0000, otherwise when -# booting from NOR flash link to address 0000'0000. -# - -CONFIG_SYS_TEXT_BASE = 0x00000000 -#CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S deleted file mode 100644 index cad0a5acd8..0000000000 --- a/board/ti/omap5912osk/lowlevel_init.S +++ /dev/null @@ -1,481 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - - /*------------------------------------------------------* - * Ensure i-cache is enabled * - * To configure TC regs without fetching instruction * - *------------------------------------------------------*/ - mrc p15, 0, r0, c1, c0 - orr r0, r0, #0x1000 - mcr p15, 0, r0, c1, c0 - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - mov r1, #0x1000 - ldr r0, REG_ARM_SYSST - - mov r2, #0 -1: cmp r2, #1 - streqh r1, [r0] - add r2, r2, #1 - cmp r2, #0x100 /* wait for any bubbles to finish */ - bne 1b - - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - /* Set memory timings corresponding to the new clock speed */ - ldr r3, VAL_SDRAM_CONFIG_SDF0 - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - mov r0, #0x10000000 /* Load physical SDRAM base. */ - mov r1, pc /* Get current execution location. */ - cmp r1, r0 /* Compare. */ - bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ - - /* identify the device revision, -- TMX or TMP(TMS) */ - ldr r0, REG_DEVICE_ID - ldr r1, [r0] - - ldr r0, VAL_DEVICE_ID_TMP - mov r1, r1, lsl #15 - mov r1, r1, lsr #16 - cmp r0, r1 - bne skip_TMP_Patch - - /* Enable TMP/TMS device new features */ - mov r0, #1 - ldr r1, REG_TC_EMIFF_DOUBLER - str r0, [r1] - - /* Enable new ac parameters */ - mov r0, #0x0b - ldr r1, REG_SDRAM_CONFIG2 - str r0, [r1] - - ldr r3, VAL_SDRAM_CONFIG_SDF1 - -skip_TMP_Patch: - - /* - * Delay for SDRAM initialization. - */ - mov r0, #0x1800 /* value should be checked */ -3: - subs r0, r0, #0x1 /* Decrement count */ - bne 3b - - /* - * Set SDRAM control values. Disable refresh before MRS command. - */ - - /* mobile ddr operation */ - ldr r0, REG_SDRAM_OPERATION - mov r2, #07 - str r2, [r0] - - /* config register */ - ldr r0, REG_SDRAM_CONFIG - str r3, [r0] - - /* manual command register */ - ldr r0, REG_SDRAM_MANUAL_CMD - - /* issue set cke high */ - mov r1, #CMD_SDRAM_CKE_SET_HIGH - str r1, [r0] - - /* issue nop */ - mov r1, #CMD_SDRAM_NOP - str r1, [r0] - - mov r2, #0x0100 -waitMDDR1: - subs r2, r2, #1 - bne waitMDDR1 /* delay loop */ - - /* issue precharge */ - mov r1, #CMD_SDRAM_PRECHARGE - str r1, [r0] - - /* issue autorefresh x 2 */ - mov r1, #CMD_SDRAM_AUTOREFRESH - str r1, [r0] - str r1, [r0] - - /* mrs register ddr mobile */ - ldr r0, REG_SDRAM_MRS - mov r1, #0x33 - str r1, [r0] - - /* emrs1 low-power register */ - ldr r0, REG_SDRAM_EMRS1 - /* self refresh on all banks */ - mov r1, #0 - str r1, [r0] - - ldr r0, REG_DLL_URD_CONTROL - ldr r1, DLL_URD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_LRD_CONTROL - ldr r1, DLL_LRD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_WRT_CONTROL - ldr r1, DLL_WRT_CONTROL_VAL - str r1, [r0] - - /* delay loop */ - mov r0, #0x0100 -waitMDDR2: - subs r0, r0, #1 - bne waitMDDR2 - - /* - * Delay for SDRAM initialization. - */ - mov r0, #0x1800 -4: - subs r0, r0, #1 /* Decrement count. */ - bne 4b - b common_tc - -skip_sdram: - ldr r0, REG_SDRAM_CONFIG - str r3, [r0] - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - - ldr r1, VAL_TC_EMIFS_DWS - ldr r0, REG_TC_EMIFS_DWS - str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */ - -#ifdef CONFIG_H2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* - * Setup a temporary stack - */ - ldr sp, SRAM_STACK - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - - /* - * Save the old lr(passed in ip) and the current lr to stack - */ - push {ip, lr} - - /* - * go setup pll, mux, memory - */ - bl s_init - pop {ip, pc} - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_DEVICE_ID: /* 32 bits */ - .word 0xfffe2004 -REG_TC_EMIFS_CONFIG: - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c -REG_TC_EMIFS_DWS: /* 32 bits */ - .word 0xfffecc40 -#ifdef CONFIG_H2_OMAP1610 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 - -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 -REG_SDRAM_CONFIG2: - .word 0xfffecc3c -REG_TC_EMIFF_DOUBLER: /* 32 bits */ - .word 0xfffecc60 - -/* Operation register */ -REG_SDRAM_OPERATION: - .word 0xfffecc80 - -/* Manual command register */ -REG_SDRAM_MANUAL_CMD: - .word 0xfffecc84 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_MRS: - .word 0xfffecc70 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_EMRS1: - .word 0xfffecc78 - -/* WRT DLL register */ -REG_DLL_WRT_CONTROL: - .word 0xfffecc68 -DLL_WRT_CONTROL_VAL: - .word 0x03f00002 /* Phase of 72deg, write offset +31 */ - -/* URD DLL register */ -REG_DLL_URD_CONTROL: - .word 0xfffeccc0 -DLL_URD_CONTROL_VAL: - .word 0x00800002 /* Phase of 72deg, read offset +31 */ - -/* LRD DLL register */ -REG_DLL_LRD_CONTROL: - .word 0xfffecccc -DLL_LRD_CONTROL_VAL: - .word 0x00800002 /* read offset +31 */ - -REG_WATCHDOG: - .word 0xfffec808 -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -REG_MPU_LOAD_TIMER: - .word 0xfffec504 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -/* 96 MHz Samsung Mobile DDR */ -/* Original setting for TMX device */ -VAL_SDRAM_CONFIG_SDF0: - .word 0x0014e6fe - -/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */ -VAL_SDRAM_CONFIG_SDF1: - .word 0x0114e6fe - -VAL_ARM_CKCTL: - .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */ -VAL_DPLL1_CTL: - .word 0x2830 - -#ifdef CONFIG_OSK_OMAP5912 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x002130b0 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00001133 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x000055f0 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88013141 -VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */ - .word 0x000000c0 -VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */ - .word 0xb65f -#endif - -#ifdef CONFIG_H2_OMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x00203331 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x8180fff3 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0xf800f22a -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88013141 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_ARM_IDLECT1: - .word 0x00000400 -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -SRAM_STACK: - .word CONFIG_SYS_INIT_SP_ADDR - -/* command values */ -.equ CMD_SDRAM_NOP, 0x00000000 -.equ CMD_SDRAM_PRECHARGE, 0x00000001 -.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 -.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c deleted file mode 100644 index e402649132..0000000000 --- a/board/ti/omap5912osk/omap5912osk.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * (C) Copyright 2004 - * Texas Instruments, - * Rishi Bhattacharya - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - flash__init(); - ether__init(); - - return 0; -} - -void s_init(void) -{ - /* Configure MUX settings */ - set_muxconf_regs (); - peripheral_power_enable (); - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -#define EMIFS_GlB_Config_REG 0xfffecc0c - unsigned int regval; - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0480000b - int i; - - *((volatile unsigned short *) 0xfffece08) = 0x03FF; - *((volatile unsigned short *) 0xfffb3824) = 0x8000; - *((volatile unsigned short *) 0xfffb3830) = 0x0000; - *((volatile unsigned short *) 0xfffb3834) = 0x0009; - *((volatile unsigned short *) 0xfffb3838) = 0x0009; - *((volatile unsigned short *) 0xfffb3818) = 0x0002; - *((volatile unsigned short *) 0xfffb382C) = 0x0048; - *((volatile unsigned short *) 0xfffb3824) = 0x8603; - udelay (3); - for (i=0;i<2000;i++); - *((volatile unsigned short *) 0xfffb381C) = 0x6610; - udelay (30); - for (i=0;i<10000;i++); - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); - - -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* setup for UART1 */ - *MuxConfReg &= ~(0x02000000); /* bit 25 */ - /* setup for UART2 */ - *MuxConfReg &= ~(0x01000000); /* bit 24 */ - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x08000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); - /*setup mux for UART3 */ - *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ - *MuxConfReg &= ~0x0000003e; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); - /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ - /* hardware will actually use TX and RTS based on bit 25 in */ - /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ - *MuxConfReg |= 0x00201000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); - /* setup for UART2 */ - /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ - /* hardware will actually use TX and RTS based on bit 24 in */ - /* FUNC_MUX_CTRL_0. */ - *MuxConfReg |= 0x09000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D); - *MuxConfReg |= 0x00000020; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); - *MuxConfReg = 0x00000000; - /* mux setup for SD/MMC driver */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); - *MuxConfReg &= 0xFFFE0FFF; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 13 for MMC2 XOR_CLK */ - *MuxConfReg &= ~(0x00002000); - /* bit 29 for UART 1 */ - *MuxConfReg &= ~(0x00002000); - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ - *MuxConfReg |= 0x000C0000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); - *MuxConfReg &= ~(0x00000070); - *MuxConfReg &= ~(0x00000008); - *MuxConfReg |= 0x00000003; - *MuxConfReg |= 0x00000180; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 17, software controls VBUS */ - *MuxConfReg &= ~(0x00020000); - /* Enable USB 48 and 12M clocks */ - *MuxConfReg |= 0x00000200; - *MuxConfReg &= ~(0x00000180); - /*2.75V for MMCSDIO1 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); - *MuxConfReg = 0x00001FE7; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); - *MuxConfReg = 0x00000000; - /* Turn on UART2 48 MHZ clock */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - *MuxConfReg |= 0x40000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); - /* setup for USB VBus detection OMAP161x */ - *MuxConfReg |= 0x00040000; /* bit 18 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - /* PullUps for SD/MMC driver */ - *MuxConfReg |= ~(0xFFFE0FFF); - MuxConfReg = - (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); - *MuxConfReg = COMP_MODE_ENABLE; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ -#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) -#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) - - *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: OSK5912"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/ti/omap5_uevm/Kconfig b/board/ti/omap5_uevm/Kconfig new file mode 100644 index 0000000000..aa13844544 --- /dev/null +++ b/board/ti/omap5_uevm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP5_UEVM + +config SYS_BOARD + default "omap5_uevm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "omap5_uevm" + +endif diff --git a/board/ti/omap5_uevm/MAINTAINERS b/board/ti/omap5_uevm/MAINTAINERS new file mode 100644 index 0000000000..280ea2f91f --- /dev/null +++ b/board/ti/omap5_uevm/MAINTAINERS @@ -0,0 +1,6 @@ +OMAP5_UEVM BOARD +M: Lokesh Vutla +S: Maintained +F: board/ti/omap5_uevm/ +F: include/configs/omap5_uevm.h +F: configs/omap5_uevm_defconfig diff --git a/board/ti/omap5_uevm/Makefile b/board/ti/omap5_uevm/Makefile index 2ab40e3ecf..b88ab8f517 100644 --- a/board/ti/omap5_uevm/Makefile +++ b/board/ti/omap5_uevm/Makefile @@ -5,29 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := evm.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := evm.o diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README new file mode 100644 index 0000000000..970e2eceb7 --- /dev/null +++ b/board/ti/omap5_uevm/README @@ -0,0 +1,25 @@ +Summary +======= + +This document covers various features of the 'omap5_uevm' build and some +related uses. + +eMMC boot partition use +======================= + +It is possible, depending on SYSBOOT configuration to boot from the eMMC +boot partitions using (name depending on documentation referenced) +Alternative Boot operation mode or Boot Sequence Option 1/2. In this +example we load MLO and u-boot.img from the build into DDR and then use +'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to +set boot0 as the boot device. +U-Boot # setenv autoload no +U-Boot # usb start +U-Boot # dhcp +U-Boot # mmc dev 1 1 +U-Boot # tftp ${loadaddr} omap5uevm/MLO +U-Boot # mmc write ${loadaddr} 0 100 +U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img +U-Boot # mmc write ${loadaddr} 300 400 +U-Boot # mmc bootbus 1 2 0 2 +U-Boot # mmc partconf 1 1 1 0 diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index ea83e6c3e7..833ffe9943 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -10,13 +10,47 @@ #include #include #include +#include #include "mux_data.h" +#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) +#include +#include +#include +#include +#include +#include +#include + +#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) +#define DIE_ID_REG_OFFSET 0x200 + +#endif + DECLARE_GLOBAL_DATA_PTR; const struct omap_sysinfo sysinfo = { - "Board: OMAP5430 EVM\n" + "Board: OMAP5432 uEVM\n" +}; + +/** + * @brief tca642x_init - uEVM default values for the GPIO expander + * input reg, output reg, polarity reg, configuration reg + */ +struct tca642x_bank_info tca642x_init[] = { + { .input_reg = 0x00, + .output_reg = 0x04, + .polarity_reg = 0x00, + .configuration_reg = 0x80 }, + { .input_reg = 0x00, + .output_reg = 0x00, + .polarity_reg = 0x00, + .configuration_reg = 0xff }, + { .input_reg = 0x00, + .output_reg = 0x00, + .polarity_reg = 0x00, + .configuration_reg = 0x40 }, }; /** @@ -30,6 +64,8 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); + return 0; } @@ -38,6 +74,35 @@ int board_eth_init(bd_t *bis) return 0; } +#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) +static void enable_host_clocks(void) +{ + int auxclk; + int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK | + OPTFCLKEN_HSIC480M_P3_CLK | + OPTFCLKEN_HSIC60M_P2_CLK | + OPTFCLKEN_HSIC480M_P2_CLK | + OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK); + + /* Enable port 2 and 3 clocks*/ + setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); + + /* Enable port 2 and 3 usb host ports tll clocks*/ + setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, + (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE)); +#ifdef CONFIG_USB_XHCI_OMAP + /* Enable the USB OTG Super speed clocks */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, + (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW)); +#endif + + auxclk = readl((*prcm)->scrm_auxclk1); + /* Request auxilary clock */ + auxclk |= AUXCLK_ENABLE_MASK; + writel(auxclk, (*prcm)->scrm_auxclk1); +} +#endif + /** * @brief misc_init_r - Configure EVM board specific configurations * such as power configurations, ethernet initialization as phase2 of @@ -47,9 +112,21 @@ int board_eth_init(bd_t *bis) */ int misc_init_r(void) { + int reg; + u32 id[4]; + #ifdef CONFIG_PALMAS_POWER palmas_init_settings(); #endif + + reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET; + + id[0] = readl(reg); + id[1] = readl(reg + 0x8); + id[2] = readl(reg + 0xC); + id[3] = readl(reg + 0x10); + usb_fake_mac_from_die_id(id); + return 0; } @@ -66,19 +143,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { @@ -87,3 +151,65 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, + .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, +}; + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int ret; + + enable_host_clocks(); + + ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); + if (ret < 0) { + puts("Failed to initialize ehci\n"); + return ret; + } + + return 0; +} + +int ehci_hcd_stop(void) +{ + int ret; + + ret = omap_ehci_hcd_stop(); + return ret; +} + +void usb_hub_reset_devices(int port) +{ + /* The LAN9730 needs to be reset after the port power has been set. */ + if (port == 3) { + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0); + udelay(10); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1); + } +} +#endif + +#ifdef CONFIG_USB_XHCI_OMAP +/** + * @brief board_usb_init - Configure EVM board specific configurations + * for the LDO's and clocks for the USB blocks. + * + * @return 0 + */ +int board_usb_init(int index, enum usb_init_type init) +{ + int ret; +#ifdef CONFIG_PALMAS_USB_SS_PWR + ret = palmas_enable_ss_ldo(); +#endif + + enable_host_clocks(); + + return 0; +} +#endif diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h index 36b723e6cc..de7ce9fe0b 100644 --- a/board/ti/omap5_uevm/mux_data.h +++ b/board/ti/omap5_uevm/mux_data.h @@ -40,7 +40,10 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ - + {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ + {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ + {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */ + {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */ }; const struct pad_conf_entry wkup_padconf_array_essential[] = { @@ -48,240 +51,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ {SYS_32K, (IEN | M0)}, /* SYS_32K */ - -}; - -const struct pad_conf_entry core_padconf_array_non_essential[] = { - - {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ - {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ - {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ - {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ - {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ - {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ - {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ - {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ - {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ - {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ - {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ - {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ - {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ - {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ - {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ - {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ - {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ - {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ - {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ - {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ - {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ - {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ - {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ - {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ - {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ - {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ - {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ - {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ - {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ - {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ - {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ - {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ - {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ - {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ - {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ - {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ - {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ - {HSI1_CADATA, (M6)}, /* GPIO3_71 */ - {UART1_TX, (M0)}, /* UART1_TX */ - {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ - {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ - {UART1_RTS, (M0)}, /* UART1_RTS */ - {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ - {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ - {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ - {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ - {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ - {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ - {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ - {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ - {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ - {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ - {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ - {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ - {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ - {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ - {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ - {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ - {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ - {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ - {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ - {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ - {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ - {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ - {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ - {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ - {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ - {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ - {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ - {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ - {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ - {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ - {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ - {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ - {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ - {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ - {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ - {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ - {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ - {RFBI_RE, (M4)}, /* KBD_COL4 */ - {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ - {RFBI_DATA8, (M4)}, /* KBD_COL3 */ - {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ - {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ - {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ - {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ - {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ - {RFBI_DATA14, (M4)}, /* KBD_COL7 */ - {RFBI_DATA15, (M4)}, /* KBD_COL6 */ - {GPIO6_182, (M6)}, /* GPIO6_182 */ - {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ - {GPIO6_184, (M4)}, /* KBD_COL2 */ - {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ - {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ - {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ - {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ - {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ - {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ - {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ - {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ - {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ - {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ - {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ - {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ - {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ - {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ - {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ - {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ - {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ - {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ - {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ - {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ - {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ - {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ - {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ - {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ - {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ - {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ - {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ - {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ - {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ - {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ - {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ - {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ - {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ - {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ - {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ - {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ - {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ - {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ - {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ - {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ - {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ - {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ - {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ - {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ - {CAM_STROBE, (M0)}, /* CAM_STROBE */ - {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ - {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ - {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ - {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ - {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ - {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ - {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ - {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ - {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ - {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ - {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ - {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ - {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ - {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ - {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ - {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ - {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ - {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ - {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ - {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ - {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ - {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ - {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ - {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ - {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ - {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ - {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ - {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ - {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ - {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ - {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ - {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ - {UART5_TX, (M0)}, /* UART5_TX */ - {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ - {UART5_RTS, (M0)}, /* UART5_RTS */ - {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ - {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ - {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ - {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ - {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ - {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ - {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ - {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ - {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ - {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ - {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ - {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ - {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ - {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ - {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ - {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ - {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ - {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - -/* - * This pad keeps C2C Module always enabled. - * Putting this in safe mode do not cause the issue. - * C2C driver could enable this mux setting if needed. - */ - {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ - {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ - {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ - {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ - {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ - {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ - {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ - {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ - {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ - {JTAG_TDO, (M0)}, /* JTAG_TDO */ - {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ - {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ - {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ - {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ - {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ - {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ - {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ - {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ - {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ - {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ - {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ - {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ - {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ - {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ - {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ + {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */ }; diff --git a/board/ti/omap730p2/Makefile b/board/ti/omap730p2/Makefile deleted file mode 100644 index 37a4d3418b..0000000000 --- a/board/ti/omap730p2/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := omap730p2.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ti/omap730p2/README.omap730p2 b/board/ti/omap730p2/README.omap730p2 deleted file mode 100644 index 7c70916120..0000000000 --- a/board/ti/omap730p2/README.omap730p2 +++ /dev/null @@ -1,91 +0,0 @@ - - u-boot for the TI OMAP730 Perseus2 - - Dave Peverley, MPC-Data Limited - http://www.mpc-data.co.uk - - -Overview : - - As the OMAP730 is similar to the OMAP1610 in many ways, this port was based -on the u-boot port to the OMAP1610 Innovator. Supported features are : - - - Serial terminal support - - Onboard NOR Flash - - Ethernet via the seperate debug board - - Tested on Rev4 and Rev5 boards - - It has also been tested to work correctly when built with a 'standard' GCC -3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain. - - -Hardware Configuration : - - The main dips on the P2 board should be set to 2,3,7 and 9 on with all -others off. On the debug board, dips 1 and 7 should be on with the rest off. -The serial console has been set up to run from the DB9 connector on the -P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit. - - It should be noted that the P2 board has NOR flash that is addressable via -either CS0 or CS3. This mode can be changed via DIP9 on the P2 board. - - -Installing u-boot for the P2 : - - You can simply build u-boot for the Perseus by following the instructions -in the main readme file. The target configuration is "omap730p2_config". -Once u-boot has been built, you should strip the executable so it can be -loaded via CCS (which cant cope with the symbols in the ELF binary) : - $ cp u-boot u-boot.out - $ arm-linux-strip u-boot.out - - The method we've used for installing u-boot the first time on a P2 is -as follows : - -1) Configure TI Code Composer Studio to connect to the P2 board via JTAG - as described in the Users Guide. - -2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU - and run the "init_mmu" GEL script. - -3) Use the "Load Program" option to send the u-boot.out file to the P2 and - run. - - At this point, u-boot should run and you will see the boot menu on your -serial terminal. You can then load the u-boot image to memory : - - # loadb 0x10000000 - - Send the "u-boot.bin" binary via the serial using Kermit. Once loaded -you can self-flash u-boot : - - # protect off 1:0 - # erase 1:0 - # cp.b 0x10000000 0x0 0x20000 - - You should now be able to reset the board and run u-boot from flash. - - -Alternative flash option : - - Sometimes, if you've been silly, you can get the board into a state where -whats in flash has upset the board so much that you can no longer connect -to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode -of the P2 so that you boot from RAM instead of NOR flash. This moves NOR -flash up to 0x0C000000. You can build a special version of u-boot to -utilise this by the following config : - - $ make omap730p2_cs0boot_config - - If you load this up via CCS it will detect flash at its alternate location -and allow you to programme your u-boot image (which, remember must be built -for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work -fine again. - - -Errata : - -1) It's been observed that sometimes the tftp transfer of kernels to the - board can have checksum errors or stall. This appears to be an issue - with the lan91c96.c driver, and can normally be worked around by - resetting the board and trying again. diff --git a/board/ti/omap730p2/config.mk b/board/ti/omap730p2/config.mk deleted file mode 100644 index 86188204ea..0000000000 --- a/board/ti/omap730p2/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Innovator has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - -CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap730p2/flash.c b/board/ti/omap730p2/flash.c deleted file mode 100644 index 56f981c47b..0000000000 --- a/board/ti/omap730p2/flash.c +++ /dev/null @@ -1,463 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - - if (flag) - enable_interrupts(); - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag, rc = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = 1; - goto done; - } - } -done: - *addr = (FPW)0x00FF00FF; /* restore read mode */ - if (flag) - enable_interrupts(); - return rc; -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ti/omap730p2/lowlevel_init.S b/board/ti/omap730p2/lowlevel_init.S deleted file mode 100644 index 795c495372..0000000000 --- a/board/ti/omap730p2/lowlevel_init.S +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003-2004 - * - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited - * (http://www.mpc-data.co.uk) - * - * TODO : Tidy up and change to use system register defines - * from omap730.h where possible. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#if defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - /* Save callers address in r11 - r11 must never be modified */ - mov r11, lr - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - /* I supposedly need to enable the dsp clock before switching */ - mov r1, #0x1000 - ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 -1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ - bne 1b - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - /* Set memory timings corresponding to the new clock speed */ - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - /* Compare physical SDRAM base & current execution location. */ - and r0, pc, #0xF0000000 - /* Compare. */ - cmp r0, #0 - /* Skip over EMIF-fast initialization if running from SDRAM. */ - bne skip_sdram - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 /* value should be checked */ -3: - subs r3, r3, #0x1 /* Decrement count */ - bne 3b - - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - - ldr r0, REG_SDRAM_MRS_LEGACY - ldr r1, SDRAM_MRS_VAL - str r1, [r0] - -skip_sdram: - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - ldr r1, VAL_TC_EMIFS_CS2_CONFIG - ldr r0, REG_TC_EMIFS_CS2_CONFIG - str r1, [r0] /* Chip Select 2 */ - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - - /* 48MHz clock request for UART1 */ - ldr r1, PERSEUS2_CONFIG_BASE - ldrh r0, [r1, #CONFIG_PCC_CONF] - orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R - strh r0, [r1, #CONFIG_PCC_CONF] - - /* Initialize public and private rheas - * - set access factor 2 on both rhea / strobe - * - disable write buffer on strb0, enable write buffer on strb1 - */ - - ldr R0, REG_RHEA_PUB_CTL - ldr R1, REG_RHEA_PRIV_CTL - ldr R2, VAL_RHEA_CTL - strh R2, [R0] - strh R2, [R1] - mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */ - strh R3, [R0, #0x08] /* arm rhea control reg */ - strh R3, [R1, #0x08] - - /* enable IRQ and FIQ */ - - mrs r4, CPSR - bic r4, r4, #IRQ_MASK - bic r4, r4, #FIQ_MASK - msr CPSR, r4 - - /* set TAP CONF to TRI EMULATION */ - - ldr r1, [r0, #CONFIG_MODE2] - bic r1, r1, #0x18 - orr r1, r1, #0x10 - str r1, [r0, #CONFIG_MODE2] - - /* set tdbgen to 1 */ - - ldr r0, PERSEUS2_CONFIG_BASE - ldr r1, [r0, #CONFIG_MODE1] - mov r2, #0x10000 - orr r1, r1, r2 - str r1, [r0, #CONFIG_MODE1] - -#ifdef CONFIG_P2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* back to arch calling code */ - mov pc, r11 - - /* the literal pools origin */ - .ltorg - -REG_TC_EMIFS_CONFIG: /* 32 bits */ - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c - -#ifdef CONFIG_P2_OMAP730 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 - -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 - -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 - -REG_SDRAM_MRS_LEGACY: - .word 0xfffecc24 - -REG_WATCHDOG: - .word 0xfffec808 - -REG_MPU_LOAD_TIMER: - .word 0xfffec504 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 - -/* Public and private rhea bridge registers definition */ - -REG_RHEA_PUB_CTL: - .word 0xFFFECA00 - -REG_RHEA_PRIV_CTL: - .word 0xFFFED300 - -/* EMIFF SDRAM Configuration register - - self refresh disable - - auto refresh enabled - - SDRAM type 64 Mb, 16 bits bus 4 banks - - power down enabled - - SDRAM clock disabled - */ -SDRAM_CONFIG_VAL: - .word 0x0C017DF4 - -/* Burst full page length ; cas latency = 3 */ -SDRAM_MRS_VAL: - .word 0x00000037 - -VAL_ARM_CKCTL: - .word 0x6505 -VAL_DPLL1_CTL: - .word 0x3412 - -#ifdef CONFIG_P2_OMAP730 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x0000FFF3 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_ARM_IDLECT1: - .word 0x00000400 -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -VAL_RHEA_CTL: - .word 0xFF22 - -/* Config Register vals */ -PERSEUS2_CONFIG_BASE: - .word 0xFFFE1000 - -.equ CONFIG_PCC_CONF, 0xB4 -.equ CONFIG_MODE1, 0x10 -.equ CONFIG_MODE2, 0x14 -.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A - -/* misc values */ -.equ IRQ_MASK, 0x80 /* IRQ mask value */ -.equ FIQ_MASK, 0x40 /* FIQ mask value */ diff --git a/board/ti/omap730p2/omap730p2.c b/board/ti/omap730p2/omap730p2.c deleted file mode 100644 index 48dc82699e..0000000000 --- a/board/ti/omap730p2/omap730p2.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#if defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int test_boot_mode(void); -void spin_up_leds(void); -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define FLASH_ON_CS0 1 -#define FLASH_ON_CS3 0 - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -int test_boot_mode(void) -{ - /* Check for CS0 and CS3 address decode swapping */ - if (*((volatile int *)EMIFS_CONFIG) & 0x00000002) - return(FLASH_ON_CS3); - else - return(FLASH_ON_CS0); -} - -/* Toggle backup LED indication */ -void toggle_backup_led(void) -{ - static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */ - volatile unsigned int *IOConfReg; - - - IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT); - - if (backupLEDState != 0) { - *IOConfReg &= (0xFFFFEFFF); - backupLEDState = 0; - } else { - *IOConfReg |= (0x00001000); - backupLEDState = 1; - } -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* arch number of OMAP 730 P2 Board - Same as the Innovator! */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - /* Configure MUX settings */ - set_muxconf_regs (); - - peripheral_power_enable (); - - /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */ - toggle_backup_led(); - - /* Hold GSM in reset until needed */ - *((volatile unsigned short *)M_CTL) &= ~1; - - /* - * CSx timings, GPIO Mux ... setup - */ - - /* Flash: CS0 timings setup */ - *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3; - *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088; - - /* Ethernet support trough the debug board */ - /* CS1 timings setup */ - *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3; - *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000; - - /* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - - return 0; -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ - unsigned int regval; - - regval = *((volatile unsigned int *) EMIFS_CONFIG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_CONFIG) = regval; -} - -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define LAN_RESET_REGISTER 0x0400001c - - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; - udelay (100); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); - - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - udelay (100); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); - -#define ETH_CONTROL_REG 0x0400030b - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (100); -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - - /* - * Backup LED Indication - */ - - /* Configure MUXed pin. Mode 6: GPIO_140 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10); - *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */ - *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */ - - /* Configure GPIO_140 as output */ - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL); - *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */ - - /* - * Configure GPIOs for battery charge & feedback - */ - - /* Configure MUXed pin. Mode 6: GPIO_35 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); - *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */ - *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */ - - /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5); - *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */ - *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */ - - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL); - *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */ - *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */ - - /* - * Allow battery charge - */ - - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT); - *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */ - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9); - *MuxConfReg &= 0x1FFFFFFF; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ - volatile unsigned int *MuxConfReg; - - - /* Set up pins used by UART */ - - /* Start UART clock (48MHz) */ - MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG); - *MuxConfReg &= (0xFFFFFFF7); - *MuxConfReg |= (0x00000008); - - /* Get the UART pin in mode0 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); - *MuxConfReg &= (0xFF1FFFFF); - *MuxConfReg &= (0xF1FFFFFF); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/ti/panda/Kconfig b/board/ti/panda/Kconfig new file mode 100644 index 0000000000..8f277b612a --- /dev/null +++ b/board/ti/panda/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP4_PANDA + +config SYS_BOARD + default "panda" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "omap4_panda" + +endif diff --git a/board/ti/panda/MAINTAINERS b/board/ti/panda/MAINTAINERS new file mode 100644 index 0000000000..2142368271 --- /dev/null +++ b/board/ti/panda/MAINTAINERS @@ -0,0 +1,6 @@ +PANDA BOARD +M: Lokesh Vutla +S: Maintained +F: board/ti/panda/ +F: include/configs/omap4_panda.h +F: configs/omap4_panda_defconfig diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile index 1e489d20b6..c89f80d806 100644 --- a/board/ti/panda/Makefile +++ b/board/ti/panda/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := panda.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := panda.o diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index e838ffd954..783ba3576f 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -122,6 +122,82 @@ int get_board_revision(void) return board_id; } +/** + * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES + * + * + * Detect if we are running on B3 version of ES panda board, + * This can be done by reading the level of GPIO 171 and checking the + * processor revisions. + * GPIO171: 1 => Panda ES Rev B3 + * + * Return : return 1 if Panda ES Rev B3 , else return 0 + */ +u8 is_panda_es_rev_b3(void) +{ + int processor_rev = omap_revision(); + int ret = 0; + + if ((processor_rev >= OMAP4460_ES1_0 && + processor_rev <= OMAP4460_ES1_1)) { + + /* Setup the mux for the common board ID pins (gpio 171) */ + writew((IEN | M3), + (*ctrl)->control_padconf_core_base + UNIPRO_TX0); + + /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */ + ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO); + } + return ret; +} + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +/* + * emif_get_reg_dump() - emif_get_reg_dump strong function + * + * @emif_nr - emif base + * @regs - reg dump of timing values + * + * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c + */ +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + u32 omap4_rev = omap_revision(); + + /* Same devices and geometry on both EMIFs */ + if (omap4_rev == OMAP4430_ES1_0) + *regs = &emif_regs_elpida_380_mhz_1cs; + else if (omap4_rev == OMAP4430_ES2_0) + *regs = &emif_regs_elpida_200_mhz_2cs; + else if (omap4_rev == OMAP4430_ES2_3) + *regs = &emif_regs_elpida_400_mhz_1cs; + else if (omap4_rev < OMAP4470_ES1_0) { + if(is_panda_es_rev_b3()) + *regs = &emif_regs_elpida_400_mhz_1cs; + else + *regs = &emif_regs_elpida_400_mhz_2cs; + } + else + *regs = &emif_regs_elpida_400_mhz_1cs; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs + **dmm_lisa_regs) +{ + u32 omap_rev = omap_revision(); + + if (omap_rev == OMAP4430_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; + else if (omap_rev == OMAP4430_ES2_3) + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else if (omap_rev < OMAP4460_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; +} + +#endif + /** * @brief misc_init_r - Configure Panda board specific configurations * such as power configurations, ethernet initialization as phase2 of @@ -133,6 +209,7 @@ int misc_init_r(void) { int phy_type; u32 auxclk, altclksrc; + u32 id[4]; /* EHCI is not supported on ES1.0 */ if (omap_revision() == OMAP4430_ES1_0) @@ -186,6 +263,12 @@ int misc_init_r(void) writel(altclksrc, &scrm->altclksrc); + id[0] = readl(STD_FUSE_DIE_ID_0); + id[1] = readl(STD_FUSE_DIE_ID_1); + id[2] = readl(STD_FUSE_DIE_ID_2); + id[3] = readl(STD_FUSE_DIE_ID_3); + usb_fake_mac_from_die_id(id); + return 0; } @@ -208,36 +291,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential_4430, - sizeof(core_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - else - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential_4460, - sizeof(core_padconf_array_non_essential_4460) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { @@ -253,7 +306,8 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { int ret; unsigned int utmi_clk; @@ -261,9 +315,9 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) /* Now we can enable our port clocks */ utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL); utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; - sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk); + setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk); - ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); + ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); if (ret < 0) return ret; diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index fb83eac9be..53c7080979 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -84,190 +84,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (M3)}, /* gpio_46 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ - {UART2_RTS, (M7)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ - {UART2_TX, (M7)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4430[] = { - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4460[] = { - {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ - {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ -}; - #endif /* _PANDA_MUX_DATA_H_ */ diff --git a/board/ti/sdp3430/Kconfig b/board/ti/sdp3430/Kconfig new file mode 100644 index 0000000000..7e73d99aba --- /dev/null +++ b/board/ti/sdp3430/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_SDP3430 + +config SYS_BOARD + default "sdp3430" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "omap3_sdp3430" + +endif diff --git a/board/ti/sdp3430/MAINTAINERS b/board/ti/sdp3430/MAINTAINERS new file mode 100644 index 0000000000..943c196d9f --- /dev/null +++ b/board/ti/sdp3430/MAINTAINERS @@ -0,0 +1,6 @@ +SDP3430 BOARD +M: Nishanth Menon +S: Maintained +F: board/ti/sdp3430/ +F: include/configs/omap3_sdp3430.h +F: configs/omap3_sdp3430_defconfig diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile index e72485c4b4..753f09979c 100644 --- a/board/ti/sdp3430/Makefile +++ b/board/ti/sdp3430/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sdp.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sdp.o diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c index 957940d53f..7171363e76 100644 --- a/board/ti/sdp3430/sdp.c +++ b/board/ti/sdp3430/sdp.c @@ -195,4 +195,9 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} #endif diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h index 2acb302591..0e631897e3 100644 --- a/board/ti/sdp3430/sdp.h +++ b/board/ti/sdp3430/sdp.h @@ -265,7 +265,7 @@ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ diff --git a/board/ti/sdp4430/Kconfig b/board/ti/sdp4430/Kconfig new file mode 100644 index 0000000000..5826d8fd0b --- /dev/null +++ b/board/ti/sdp4430/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP4_SDP4430 + +config SYS_BOARD + default "sdp4430" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "omap4_sdp4430" + +endif diff --git a/board/ti/sdp4430/MAINTAINERS b/board/ti/sdp4430/MAINTAINERS new file mode 100644 index 0000000000..ac4d0ccc19 --- /dev/null +++ b/board/ti/sdp4430/MAINTAINERS @@ -0,0 +1,6 @@ +SDP4430 BOARD +M: Lokesh Vutla +S: Maintained +F: board/ti/sdp4430/ +F: include/configs/omap4_sdp4430.h +F: configs/omap4_sdp4430_defconfig diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile index c522a2b84e..79e67b6e96 100644 --- a/board/ti/sdp4430/Makefile +++ b/board/ti/sdp4430/Makefile @@ -5,27 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sdp.o +obj-y := sdp.o ifndef CONFIG_SPL_BUILD -COBJS += cmd_bat.o +obj-y += cmd_bat.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 25daaa9ffb..1e9ef9e38b 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -28,7 +28,6 @@ int board_init(void) { gpmc_init(); - gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ return 0; @@ -66,33 +65,14 @@ void set_muxconf_regs_essential(void) sizeof(wkup_padconf_array_essential) / sizeof(struct pad_conf_entry)); - if (omap_revision() >= OMAP4460_ES1_0) + if ((omap_revision() >= OMAP4460_ES1_0) && + (omap_revision() < OMAP4470_ES1_0)) do_set_mux((*ctrl)->control_padconf_wkup_base, wkup_padconf_array_essential_4460, sizeof(wkup_padconf_array_essential_4460) / sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) { - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - } -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 4394dbaa48..9a9efe7a54 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -65,201 +65,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (M1)}, /* dsi1_te0 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ - {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ - {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ - {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ - {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ - {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ -}; - #endif /* _SDP4430_MUX_DATA_H */ diff --git a/board/ti/ti814x/Kconfig b/board/ti/ti814x/Kconfig new file mode 100644 index 0000000000..2960099a8e --- /dev/null +++ b/board/ti/ti814x/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TI814X_EVM + +config SYS_BOARD + default "ti814x" + +config SYS_VENDOR + default "ti" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "ti814x_evm" + +endif diff --git a/board/ti/ti814x/MAINTAINERS b/board/ti/ti814x/MAINTAINERS new file mode 100644 index 0000000000..e39b253d25 --- /dev/null +++ b/board/ti/ti814x/MAINTAINERS @@ -0,0 +1,6 @@ +TI814X BOARD +M: Matt Porter +S: Maintained +F: board/ti/ti814x/ +F: include/configs/ti814x_evm.h +F: configs/ti814x_evm_defconfig diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile index 6059e203f3..93155de533 100644 --- a/board/ti/ti814x/Makefile +++ b/board/ti/ti814x/Makefile @@ -6,33 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifdef CONFIG_SPL_BUILD -COBJS := mux.o +obj-y := mux.o endif -COBJS += evm.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += evm.o diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 17fba5aecd..54b3dfb82c 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -27,41 +27,18 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPL_BUILD -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#endif - static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* UART Defines */ #ifdef CONFIG_SPL_BUILD -static void uart_enable(void) -{ - /* UART softreset */ - uart_soft_reset(); -} - -static void wdt_disable(void) -{ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; -} - static const struct cmd_control evm_ddr2_cctrl_data = { .cmd0csratio = 0x80, - .cmd0dldiff = 0x04, .cmd0iclkout = 0x00, .cmd1csratio = 0x80, - .cmd1dldiff = 0x04, .cmd1iclkout = 0x00, .cmd2csratio = 0x80, - .cmd2dldiff = 0x04, .cmd2iclkout = 0x00, }; @@ -97,71 +74,40 @@ static const struct ddr_data evm_ddr2_data = { .datagiratio0 = ((0<<10) | (0<<0)), .datafwsratio0 = ((0x90<<10) | (0x90<<0)), .datawrsratio0 = ((0x50<<10) | (0x50<<0)), - .datauserank0delay = 1, - .datadldiff0 = 0x4, }; -#endif -/* - * early system init of muxing and clocks. - */ -void s_init(void) +void set_uart_mux_conf(void) { -#ifdef CONFIG_SPL_BUILD - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - wdt_disable(); - - /* Enable timer */ - timer_init(); - - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - /* Set UART pins */ enable_uart0_pin_mux(); +} +void set_mux_conf_regs(void) +{ /* Set MMC pins */ enable_mmc1_pin_mux(); /* Set Ethernet pins */ enable_enet_pin_mux(); +} - /* Enable UART */ - uart_enable(); - - gd = &gdata; - - preloader_console_init(); - +void sdram_init(void) +{ config_dmm(&evm_lisa_map_regs); - config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); - config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } @@ -186,12 +132,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x50, .sliver_reg_ofs = 0x700, - .phy_id = 1, + .phy_addr = 1, }, { .slave_reg_ofs = 0x90, .sliver_reg_ofs = 0x740, - .phy_id = 0, + .phy_addr = 0, }, }; @@ -207,6 +153,7 @@ static struct cpsw_platform_data cpsw_data = { .ale_entries = 1024, .host_port_reg_ofs = 0x28, .hw_stats_reg_ofs = 0x400, + .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig new file mode 100644 index 0000000000..95973b47f1 --- /dev/null +++ b/board/ti/ti816x/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TI816X_EVM + +config SYS_BOARD + default "ti816x" + +config SYS_VENDOR + default "ti" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "ti816x_evm" + +endif diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS new file mode 100644 index 0000000000..d3de144bc2 --- /dev/null +++ b/board/ti/ti816x/MAINTAINERS @@ -0,0 +1,6 @@ +TI816X BOARD +#M: - +S: Maintained +F: board/ti/ti816x/ +F: include/configs/ti816x_evm.h +F: configs/ti816x_evm_defconfig diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile new file mode 100644 index 0000000000..f1cc3d5616 --- /dev/null +++ b/board/ti/ti816x/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (C) 2013, Adeneo Embedded +# Antoine Tenart, +# +# Based on TI-PSP-04.00.02.14 : +# +# Copyright (C) 2009, Texas Instruments, Incorporated +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := evm.o diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c new file mode 100644 index 0000000000..b6bf16236f --- /dev/null +++ b/board/ti/ti816x/evm.c @@ -0,0 +1,216 @@ +/* + * evm.c + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +static struct module_pin_mux mmc_pin_mux[] = { + { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, + { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { -1 }, +}; + +const struct dmm_lisa_map_regs evm_lisa_map_regs = { + .dmm_lisa_map_0 = 0x00000000, + .dmm_lisa_map_1 = 0x00000000, + .dmm_lisa_map_2 = 0x80640300, + .dmm_lisa_map_3 = 0xC0640320, +}; + +/* + * DDR2 related definitions + */ +#ifdef CONFIG_TI816X_EVM_DDR2 +static struct ddr_data ddr2_data = { + .datardsratio0 = ((0x40<<10) | (0x40<<0)), + .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)), + .datawiratio0 = ((0x0<<10) | (0x0<<0)), + .datagiratio0 = ((0x0<<10) | (0x0<<0)), + .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)), + .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)), +}; + +static struct cmd_control ddr2_ctrl = { + .cmd0csratio = 0x80, + .cmd0iclkout = 0x00, + + .cmd1csratio = 0x80, + .cmd1iclkout = 0x00, + + .cmd2csratio = 0x80, + .cmd2iclkout = 0x00, + +}; + +static struct emif_regs ddr2_emif0_regs = { + .sdram_config = 0x43801A3A, + .ref_ctrl = 0x10000C30, + .sdram_tim1 = 0x0AAB15E2, + .sdram_tim2 = 0x423631D2, + .sdram_tim3 = 0x0080032F, + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ +}; + +static struct emif_regs ddr2_emif1_regs = { + .sdram_config = 0x43801A3A, + .ref_ctrl = 0x10000C30, + .sdram_tim1 = 0x0AAB15E2, + .sdram_tim2 = 0x423631D2, + .sdram_tim3 = 0x0080032F, + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ +}; +#endif + +/* + * DDR3 related definitions + */ + +#if defined(CONFIG_TI816X_DDR_PLL_400) +#define RD_DQS 0x03B +#define WR_DQS 0x0A6 +#define RD_DQS_GATE 0x12A +#define EMIF_SDCFG 0x62A41032 +#define EMIF_SDREF 0x10000C30 +#define EMIF_TIM1 0x0CCCE524 +#define EMIF_TIM2 0x30308023 +#define EMIF_TIM3 0x009F82CF +#define EMIF_PHYCFG 0x0000010B +#elif defined(CONFIG_TI816X_DDR_PLL_531) +#define RD_DQS 0x039 +#define WR_DQS 0x0B4 +#define RD_DQS_GATE 0x13D +#define EMIF_SDCFG 0x62A51832 +#define EMIF_SDREF 0x1000102E +#define EMIF_TIM1 0x0EF136AC +#define EMIF_TIM2 0x30408063 +#define EMIF_TIM3 0x009F83AF +#define EMIF_PHYCFG 0x0000010C +#elif defined(CONFIG_TI816X_DDR_PLL_675) +#define RD_DQS 0x039 +#define WR_DQS 0x091 +#define RD_DQS_GATE 0x196 +#define EMIF_SDCFG 0x62A63032 +#define EMIF_SDREF 0x10001491 +#define EMIF_TIM1 0x13358875 +#define EMIF_TIM2 0x5051806C +#define EMIF_TIM3 0x009F84AF +#define EMIF_PHYCFG 0x0000010F +#elif defined(CONFIG_TI816X_DDR_PLL_796) +#define RD_DQS 0x035 +#define WR_DQS 0x093 +#define RD_DQS_GATE 0x1B3 +#define EMIF_SDCFG 0x62A73832 +#define EMIF_SDREF 0x10001841 +#define EMIF_TIM1 0x1779C9FE +#define EMIF_TIM2 0x50608074 +#define EMIF_TIM3 0x009F857F +#define EMIF_PHYCFG 0x00000110 +#endif + +static struct ddr_data ddr3_data = { + .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), + .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), + .datawiratio0 = ((0x20<<10) | 0x20<<0), + .datagiratio0 = ((0x20<<10) | 0x20<<0), + .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), + .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), +}; + +static const struct cmd_control ddr3_ctrl = { + .cmd0csratio = 0x100, + .cmd0iclkout = 0x001, + + .cmd1csratio = 0x100, + .cmd1iclkout = 0x001, + + .cmd2csratio = 0x100, + .cmd2iclkout = 0x001, +}; + +static const struct emif_regs ddr3_emif0_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +}; + +static const struct emif_regs ddr3_emif1_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +}; + +void set_uart_mux_conf(void) {} + +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(mmc_pin_mux); +} + +void sdram_init(void) +{ + config_dmm(&evm_lisa_map_regs); + +#ifdef CONFIG_TI816X_EVM_DDR2 + if (CONFIG_TI816X_USE_EMIF0) { + ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); + config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, + 0); + } + + if (CONFIG_TI816X_USE_EMIF1) { + ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); + config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, + 1); + } +#endif + +#ifdef CONFIG_TI816X_EVM_DDR3 + if (CONFIG_TI816X_USE_EMIF0) + config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, + 0); + + if (CONFIG_TI816X_USE_EMIF1) + config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, + 1); +#endif +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/ti/tnetv107xevm/Kconfig b/board/ti/tnetv107xevm/Kconfig new file mode 100644 index 0000000000..637f20e847 --- /dev/null +++ b/board/ti/tnetv107xevm/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TNETV107X_EVM + +config SYS_BOARD + default "tnetv107xevm" + +config SYS_VENDOR + default "ti" + +config SYS_SOC + default "tnetv107x" + +config SYS_CONFIG_NAME + default "tnetv107x_evm" + +endif diff --git a/board/ti/tnetv107xevm/MAINTAINERS b/board/ti/tnetv107xevm/MAINTAINERS new file mode 100644 index 0000000000..8a92c6bf87 --- /dev/null +++ b/board/ti/tnetv107xevm/MAINTAINERS @@ -0,0 +1,6 @@ +TNETV107XEVM BOARD +#M: Chan-Taek Park +S: Orphan (since 2014-06) +F: board/ti/tnetv107xevm/ +F: include/configs/tnetv107x_evm.h +F: configs/tnetv107x_evm_defconfig diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile index 5b82e483b5..0a6128f85f 100644 --- a/board/ti/tnetv107xevm/Makefile +++ b/board/ti/tnetv107xevm/Makefile @@ -2,27 +2,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS += sdb_board.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -.PHONY: all - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += sdb_board.o diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c index a95434b5ef..a84ec84bae 100644 --- a/board/ti/tnetv107xevm/sdb_board.c +++ b/board/ti/tnetv107xevm/sdb_board.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig new file mode 100644 index 0000000000..e3bd4569d6 --- /dev/null +++ b/board/timll/devkit3250/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DEVKIT3250 + +config SYS_BOARD + default "devkit3250" + +config SYS_VENDOR + default "timll" + +config SYS_SOC + default "lpc32xx" + +config SYS_CONFIG_NAME + default "devkit3250" + +endif diff --git a/board/timll/devkit3250/MAINTAINERS b/board/timll/devkit3250/MAINTAINERS new file mode 100644 index 0000000000..cb93563fed --- /dev/null +++ b/board/timll/devkit3250/MAINTAINERS @@ -0,0 +1,6 @@ +DEVKIT3250 BOARD +M: Vladimir Zapolskiy +S: Maintained +F: board/timll/devkit3250/ +F: include/configs/devkit3250.h +F: configs/devkit3250_defconfig diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile index a1e69ad501..472298637f 100644 --- a/board/timll/devkit3250/Makefile +++ b/board/timll/devkit3250/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := devkit3250.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := devkit3250.o diff --git a/board/timll/devkit8000/Kconfig b/board/timll/devkit8000/Kconfig new file mode 100644 index 0000000000..3c63ced9a1 --- /dev/null +++ b/board/timll/devkit8000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DEVKIT8000 + +config SYS_BOARD + default "devkit8000" + +config SYS_VENDOR + default "timll" + +config SYS_CONFIG_NAME + default "devkit8000" + +endif diff --git a/board/timll/devkit8000/MAINTAINERS b/board/timll/devkit8000/MAINTAINERS new file mode 100644 index 0000000000..c490757d68 --- /dev/null +++ b/board/timll/devkit8000/MAINTAINERS @@ -0,0 +1,6 @@ +DEVKIT8000 BOARD +M: Thomas Weber +S: Maintained +F: board/timll/devkit8000/ +F: include/configs/devkit8000.h +F: configs/devkit8000_defconfig diff --git a/board/timll/devkit8000/Makefile b/board/timll/devkit8000/Makefile index 553e699200..104b63b570 100644 --- a/board/timll/devkit8000/Makefile +++ b/board/timll/devkit8000/Makefile @@ -8,23 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := devkit8000.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := devkit8000.o diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index bcbee73d5d..4d07313432 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -17,6 +17,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include #include #include #include @@ -43,6 +45,17 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = { 0 }; +static const struct ns16550_platdata devkit8000_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(devkit8000_uart) = { + "serial_omap", + &devkit8000_serial +}; + /* * Routine: board_init * Description: Early hardware init. @@ -124,6 +137,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD) /* * Routine: board_eth_init diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig new file mode 100644 index 0000000000..f1dcda5927 --- /dev/null +++ b/board/toradex/apalis_t30/Kconfig @@ -0,0 +1,12 @@ +if TARGET_APALIS_T30 + +config SYS_BOARD + default "apalis_t30" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "apalis_t30" + +endif diff --git a/board/toradex/apalis_t30/MAINTAINERS b/board/toradex/apalis_t30/MAINTAINERS new file mode 100644 index 0000000000..01bc73e46d --- /dev/null +++ b/board/toradex/apalis_t30/MAINTAINERS @@ -0,0 +1,7 @@ +Apalis T30 +M: Marcel Ziswiler +S: Maintained +F: board/toradex/apalis_t30/ +F: include/configs/apalis_t30.h +F: configs/apalis_t30_defconfig +F: arch/arm/dts/tegra30-apalis.dtb diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile new file mode 100644 index 0000000000..a968e6b79e --- /dev/null +++ b/board/toradex/apalis_t30/Makefile @@ -0,0 +1,6 @@ +# Copyright (c) 2014 Marcel Ziswiler +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/board/nvidia/common/common.mk + +obj-y += apalis_t30.o diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c new file mode 100644 index 0000000000..624421496a --- /dev/null +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2014 + * Marcel Ziswiler + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinmux-config-apalis_t30.h" + +#define PMU_I2C_ADDRESS 0x2D +#define MAX_I2C_RETRY 3 + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra3_pinmux_common, + ARRAY_SIZE(tegra3_pinmux_common)); + + pinmux_config_pingrp_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + pinmux_config_drvgrp_table(apalis_t30_padctrl, + ARRAY_SIZE(apalis_t30_padctrl)); +} + +#ifdef CONFIG_PCI_TEGRA +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + u8 addr, data[1]; + int err; + + err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); + if (err) { + debug("%s: Cannot find PMIC I2C chip\n", __func__); + return err; + } + /* TPS659110: VDD2_OP_REG = 1.05V */ + data[0] = 0x27; + addr = 0x25; + + err = dm_i2c_write(dev, addr, data, 1); + if (err) { + debug("failed to set VDD supply\n"); + return err; + } + + /* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */ + data[0] = 0x0D; + addr = 0x24; + + err = dm_i2c_write(dev, addr, data, 1); + if (err) { + debug("failed to enable VDD supply\n"); + return err; + } + + /* TPS659110: LDO6_REG = 1.1V, ACTIVE */ + data[0] = 0x0D; + addr = 0x35; + + err = dm_i2c_write(dev, addr, data, 1); + if (err) { + debug("failed to set AVDD supply\n"); + return err; + } + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} +#endif /* CONFIG_PCI_TEGRA */ diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h new file mode 100644 index 0000000000..c988d395c1 --- /dev/null +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2014, Marcel Ziswiler + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _PINMUX_CONFIG_APALIS_T30_H_ +#define _PINMUX_CONFIG_APALIS_T30_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config tegra3_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, NORMAL, NORMAL, INPUT), + + /* SDMMC4 pinmux (eMMC) */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + /* UARTA RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), + LV_PINMUX(VI_D0_PT4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PU1, RSVD1, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PU2, RSVD1, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PU3, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, PWM3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9 + */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT), + + /* GPIOs */ + DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT), + /* multiplexed KB_COL0 */ + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, TRISTATE, OUTPUT), + + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, INPUT), +}; + +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, NAND, DOWN, TRISTATE, OUTPUT), +}; + +static struct pmux_drvgrp_config apalis_t30_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_APALIS_T30_H_ */ diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig new file mode 100644 index 0000000000..949407a042 --- /dev/null +++ b/board/toradex/colibri_pxa270/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COLIBRI_PXA270 + +config SYS_BOARD + default "colibri_pxa270" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri_pxa270" + +endif diff --git a/board/toradex/colibri_pxa270/MAINTAINERS b/board/toradex/colibri_pxa270/MAINTAINERS new file mode 100644 index 0000000000..b378d7be5a --- /dev/null +++ b/board/toradex/colibri_pxa270/MAINTAINERS @@ -0,0 +1,6 @@ +COLIBRI_PXA270 BOARD +M: Marek Vasut +S: Maintained +F: board/toradex/colibri_pxa270/ +F: include/configs/colibri_pxa270.h +F: configs/colibri_pxa270_defconfig diff --git a/board/toradex/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile index 60f4097bf0..57cfe9b789 100644 --- a/board/toradex/colibri_pxa270/Makefile +++ b/board/toradex/colibri_pxa270/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := colibri_pxa270.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := colibri_pxa270.o diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index c1e2562348..8d95e4d174 100644 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -13,6 +13,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int dram_init(void) } #ifdef CONFIG_CMD_USB -int usb_board_init(void) +int board_usb_init(int index, enum usb_init_type init) { writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), @@ -70,9 +71,9 @@ int usb_board_init(void) return 0; } -void usb_board_init_fail(void) +int board_usb_cleanup(int index, enum usb_init_type init) { - return; + return 0; } void usb_board_stop(void) diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20-common/colibri_t20-common.c index 823d0de5e4..58a9916f0a 100644 --- a/board/toradex/colibri_t20-common/colibri_t20-common.c +++ b/board/toradex/colibri_t20-common/colibri_t20-common.c @@ -18,12 +18,12 @@ void colibri_t20_common_pin_mux_usb(void) /* module internal USB bus to connect ethernet chipset */ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); /* ULPI reference clock output */ - pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); - pinmux_tristate_disable(PINGRP_CDEV2); + pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PMUX_PINGRP_CDEV2); /* PHY reset GPIO */ - pinmux_tristate_disable(PINGRP_UAC); + pinmux_tristate_disable(PMUX_PINGRP_UAC); /* VBus GPIO */ - pinmux_tristate_disable(PINGRP_DTE); + pinmux_tristate_disable(PMUX_PINGRP_DTE); } #endif diff --git a/board/toradex/colibri_t20_iris/Kconfig b/board/toradex/colibri_t20_iris/Kconfig new file mode 100644 index 0000000000..4bf727809e --- /dev/null +++ b/board/toradex/colibri_t20_iris/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COLIBRI_T20_IRIS + +config SYS_BOARD + default "colibri_t20_iris" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri_t20_iris" + +endif diff --git a/board/toradex/colibri_t20_iris/MAINTAINERS b/board/toradex/colibri_t20_iris/MAINTAINERS new file mode 100644 index 0000000000..c68955bfa9 --- /dev/null +++ b/board/toradex/colibri_t20_iris/MAINTAINERS @@ -0,0 +1,6 @@ +COLIBRI_T20_IRIS BOARD +M: Lucas Stach +S: Maintained +F: board/toradex/colibri_t20_iris/ +F: include/configs/colibri_t20_iris.h +F: configs/colibri_t20_iris_defconfig diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile index 40789f89f1..ebeac70ea1 100644 --- a/board/toradex/colibri_t20_iris/Makefile +++ b/board/toradex/colibri_t20_iris/Makefile @@ -4,28 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -$(shell mkdir -p $(obj)../../nvidia/common) -$(shell mkdir -p $(obj)../colibri_t20-common) - -LIB = $(obj)lib$(BOARD).o - -COBJS := ../../nvidia/common/board.o -COBJS += ../colibri_t20-common/colibri_t20-common.o -COBJS += $(BOARD).o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ../../nvidia/common/board.o +obj-y += ../colibri_t20-common/colibri_t20-common.o +obj-y += colibri_t20_iris.o diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c index f5f0475b89..49c74f34f1 100644 --- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c +++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c @@ -19,7 +19,7 @@ void pin_mux_usb(void) colibri_t20_common_pin_mux_usb(); /* USB 1 aka Tegra USB port 3 VBus*/ - pinmux_tristate_disable(PINGRP_SPIG); + pinmux_tristate_disable(PMUX_PINGRP_SPIG); } #endif @@ -31,6 +31,6 @@ void pin_mux_usb(void) void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); - pinmux_tristate_disable(PINGRP_GMB); + pinmux_tristate_disable(PMUX_PINGRP_GMB); } #endif diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig new file mode 100644 index 0000000000..3e436a2d3f --- /dev/null +++ b/board/toradex/colibri_t30/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COLIBRI_T30 + +config SYS_BOARD + default "colibri_t30" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri_t30" + +endif diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS new file mode 100644 index 0000000000..73b8e5d099 --- /dev/null +++ b/board/toradex/colibri_t30/MAINTAINERS @@ -0,0 +1,7 @@ +Colibri T30 +M: Stefan Agner +S: Maintained +F: board/toradex/colibri_t30/ +F: include/configs/colibri_t30.h +F: configs/colibri_t30_defconfig +F: arch/arm/dts/tegra30-colibri.dtb diff --git a/board/toradex/colibri_t30/Makefile b/board/toradex/colibri_t30/Makefile new file mode 100644 index 0000000000..3d58a4b2c1 --- /dev/null +++ b/board/toradex/colibri_t30/Makefile @@ -0,0 +1,6 @@ +# Copyright (c) 2013-2014 Stefan Agner +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/board/nvidia/common/common.mk + +obj-y += colibri_t30.o diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c new file mode 100644 index 0000000000..f4bc7d8728 --- /dev/null +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2014 + * Stefan Agner + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "pinmux-config-colibri_t30.h" +#include +#include + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra3_pinmux_common, + ARRAY_SIZE(tegra3_pinmux_common)); + + pinmux_config_pingrp_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + pinmux_config_drvgrp_table(colibri_t30_padctrl, + ARRAY_SIZE(colibri_t30_padctrl)); +} + +/* + * Enable AX88772B USB to LAN controller + */ +void pin_mux_usb(void) +{ + /* Reset ASIX using LAN_RESET */ + gpio_request(GPIO_PDD0, "LAN_RESET"); + gpio_direction_output(GPIO_PDD0, 0); + udelay(5); + gpio_set_value(GPIO_PDD0, 1); +} diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h new file mode 100644 index 0000000000..4e73c0762e --- /dev/null +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2013-2014, Stefan Agner + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _PINMUX_CONFIG_COLIBRI_T30_H_ +#define _PINMUX_CONFIG_COLIBRI_T30_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config tegra3_pinmux_common[] = { + /* SDMMC1 disabled */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, RSVD1, NORMAL, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT), + + /* SDMMC4 pinmux (eMMC) */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + DEFAULT_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT), + + /* I2C3 pinmux, muliplexed with KB_ROW13/KB_ROW14 */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + /* UARTA RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), + LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */ + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ + DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT), + + + /* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */ + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, TRISTATE, INPUT), + + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* KBC keys */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT), + + /* SDMMC2 pinmux */ + DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + + /* LAN_RESET */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), + + /* LAN_VBUS */ + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), + + /* GPIOs */ + /* SDMMC1 CD gpio */ + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), + /* SDMMC1 WP gpio */ + LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), + + /* Touch panel GPIO */ + /* Touch IRQ */ + DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT), + + /* Touch RESET */ + DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT), + + /* Power rails GPIO */ + DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), + + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), +}; + +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), +}; + +static struct pmux_drvgrp_config colibri_t30_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_COLIBRI_T30_H_ */ diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts deleted file mode 100644 index c0e54af886..0000000000 --- a/board/toradex/dts/tegra20-colibri_t20_iris.dts +++ /dev/null @@ -1,45 +0,0 @@ -/dts-v1/; - -#include "tegra20.dtsi" - -/ { - model = "Toradex Colibri T20"; - compatible = "toradex,t20", "nvidia,tegra20"; - - aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; - usb2 = "/usb@c5004000"; - sdhci0 = "/sdhci@c8000600"; - }; - - usb@c5000000 { - dr_mode = "otg"; - }; - - usb@c5004000 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */ - nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */ - }; - - usb@c5008000 { - nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */ - }; - - nand-controller@70008000 { - nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */ - nvidia,width = <8>; - nvidia,timing = <15 100 25 80 25 10 15 10 100>; - - nand@0 { - reg = <0>; - compatible = "nand-flash"; - }; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio 23 1>; /* gpio PC7 */ - bus-width = <4>; - }; -}; diff --git a/board/total5200/Makefile b/board/total5200/Makefile deleted file mode 100644 index 5c22b70f94..0000000000 --- a/board/total5200/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o sdram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h deleted file mode 100644 index 068a9a6ee0..0000000000 --- a/board/total5200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h deleted file mode 100644 index 037741722a..0000000000 --- a/board/total5200/mt48lc32m16a2-75.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Micron MT48LC32M16A2-75 is compatible to: - * - Infineon HYB39S512160AT-75 - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x514F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c deleted file mode 100644 index dbe358773b..0000000000 --- a/board/total5200/sdram.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include "sdram.h" - -#ifndef CONFIG_SYS_RAMBOOT -static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - if (sdram_conf->ddr) { - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000; - __asm__ volatile ("sync"); - } - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; - __asm__ volatile ("sync"); - - if (sdram_conf->ddr) { - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay; - __asm__ volatile ("sync"); - } - - /* find RAM size using SDRAM CS0 only */ - mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - mpc5xxx_sdram_start(sdram_conf, 0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (test1 > test2) { - mpc5xxx_sdram_start(sdram_conf, 0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize + dramsize2; -} diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h deleted file mode 100644 index 3758f5c986..0000000000 --- a/board/total5200/sdram.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -typedef struct { - ulong ddr; - ulong mode; - ulong emode; - ulong control; - ulong config1; - ulong config2; - ulong tapdelay; -} sdram_conf_t; - -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf); diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c deleted file mode 100644 index 345a186b2e..0000000000 --- a/board/total5200/total5200.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include "sdram.h" - -#if CONFIG_TOTAL5200_REV==2 -#include "mt48lc32m16a2-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -phys_size_t initdram (int board_type) -{ - sdram_conf_t sdram_conf; - - sdram_conf.ddr = SDRAM_DDR; - sdram_conf.mode = SDRAM_MODE; - sdram_conf.emode = 0; - sdram_conf.control = SDRAM_CONTROL; - sdram_conf.config1 = SDRAM_CONFIG1; - sdram_conf.config2 = SDRAM_CONFIG2; - sdram_conf.tapdelay = 0; - return mpc5xxx_sdram_init (&sdram_conf); -} - -int checkboard (void) -{ -#if CONFIG_TOTAL5200_REV==2 - puts ("Board: Total5200 Rev.2 "); -#else - puts ("Board: Total5200 "); -#endif - - /* - * Retrieve FPGA Revision. - */ - printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400)); - - /* - * Take all peripherals in power-up mode. - */ -#if CONFIG_TOTAL5200_REV==2 - *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70; -#else - *(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70; -#endif - - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -/* IRDA_1 aka PSC6_3 (pin C13) */ -#define GPIO_IRDA_1 0x20000000UL - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1; - *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1; - } else { - *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1; - } -} -#endif - -#ifdef CONFIG_VIDEO_SED13806 -#include - -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SED13806_8BPP -#error CONFIG_VIDEO_SED13806_8BPP not supported. -#endif /* CONFIG_VIDEO_SED13806_8BPP */ - -#ifdef CONFIG_VIDEO_SED13806_16BPP -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x00}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x00}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; -#endif /* CONFIG_VIDEO_SED13806_16BPP */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* Return text to be printed besides the logo. */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { -#if CONFIG_TOTAL5200_REV==1 - strcpy (info, " Total5200"); -#elif CONFIG_TOTAL5200_REV==2 - strcpy (info, " Total5200 Rev.2"); -#else -#error CONFIG_TOTAL5200_REV must be 1 or 2. -#endif - } else { - info [0] = '\0'; - } -} -#endif - -/* Returns SED13806 base address. First thing called in the driver. */ -unsigned int board_video_init (void) -{ - return CONFIG_SYS_LCD_BASE; -} - -/* Called after initializing the SED13806 and before clearing the screen. */ -void board_validate_screen (unsigned int base) -{ -} - -/* Return a pointer to the initialization sequence. */ -const S1D_REGS *board_get_regs (void) -{ - return init_regs; -} - -int board_get_width (void) -{ - return DISPLAY_WIDTH; -} - -int board_get_height (void) -{ - return DISPLAY_HEIGHT; -} - -#endif /* CONFIG_VIDEO_SED13806 */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig new file mode 100644 index 0000000000..0e4cd69a2d --- /dev/null +++ b/board/tqc/tqm5200/Kconfig @@ -0,0 +1,51 @@ +if TARGET_AEV + +config SYS_BOARD + default "tqm5200" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "aev" + +endif + +if TARGET_CHARON + +config SYS_BOARD + default "tqm5200" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "charon" + +endif + +if TARGET_TB5200 + +config SYS_BOARD + default "tqm5200" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TB5200" + +endif + +if TARGET_TQM5200 + +config SYS_BOARD + default "tqm5200" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM5200" + +endif diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS new file mode 100644 index 0000000000..d3eb543140 --- /dev/null +++ b/board/tqc/tqm5200/MAINTAINERS @@ -0,0 +1,26 @@ +TQM5200 BOARD +#M: - +S: Maintained +F: board/tqc/tqm5200/ +F: include/configs/aev.h +F: configs/aev_defconfig +F: include/configs/TQM5200.h +F: configs/cam5200_defconfig +F: configs/cam5200_niosflash_defconfig +F: configs/fo300_defconfig +F: configs/MiniFAP_defconfig +F: include/configs/TB5200.h +F: configs/TB5200_defconfig +F: configs/TB5200_B_defconfig +F: configs/TQM5200_defconfig +F: configs/TQM5200_B_defconfig +F: configs/TQM5200_B_HIGHBOOT_defconfig +F: configs/TQM5200_STK100_defconfig +F: configs/TQM5200S_defconfig +F: configs/TQM5200S_HIGHBOOT_defconfig + +CHARON BOARD +M: Heiko Schocher +S: Maintained +F: include/configs/charon.h +F: configs/charon_defconfig diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile index 619e43f94d..80c1eba87c 100644 --- a/board/tqc/tqm5200/Makefile +++ b/board/tqc/tqm5200/Makefile @@ -5,27 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -cam5200_flash.o: cam5200_flash.c - $(CC) $(CFLAGS) -c -o $@ $< - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index d5a8a979d5..e9363ea394 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -8,7 +8,7 @@ * (C) Copyright 2004-2006 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -863,12 +863,14 @@ int board_get_height (void) #endif /* CONFIG_VIDEO_SM501 */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #if defined(CONFIG_VIDEO) fdt_add_edid(blob, "smi,sm501", edid_buf); #endif + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile deleted file mode 100644 index b92acdb34b..0000000000 --- a/board/tqc/tqm8260/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../tqm8xx/) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/tqc/tqm8260/README b/board/tqc/tqm8260/README deleted file mode 100644 index 93b55068f5..0000000000 --- a/board/tqc/tqm8260/README +++ /dev/null @@ -1,415 +0,0 @@ - -This file contains basic information on the port of U-Boot to TQM8260. -All the changes fit in the common U-Boot infrastructure, providing a -new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260, -type "make TQM8260_config", edit the "include/config_TQM8260.h" file -if necessary, then type "make". - - -Common file modifications: --------------------------- - -The following common files have been modified by this project: -(starting from the ppcboot-0.9.3/ directory) - -MAKEALL - TQM8260 entry added -Makefile - TQM8260_config entry added -arch/powerpc/cpu/mpc8260/Makefile - soft_i2c.o module added -arch/powerpc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious - bug fixed (fcr -> scr) -arch/powerpc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added -include/flash.h - added definitions for the AM29LV640D Flash chip - - -New files: ----------- - -The following new files have been added by this project: -(starting from the ppcboot-0.9.3/ directory) - -board/tqm8260/ - board-specific directory -board/tqm8260/Makefile - board-specific makefile -board/tqm8260/config.mk - config file -board/tqm8260/flash.c - flash driver (for AM29LV640D) -board/tqm8260/ppcboot.lds - linker script -board/tqm8260/tqm8260.c - ioport and memory initialization -arch/powerpc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver -include/config_TQM8260.h - main configuration file - - -New configuration options: --------------------------- - -CONFIG_TQM8260 - - Main board-specific option (should be defined for TQM8260). - -CONFIG_82xx_CONS_SMC1 - - If defined, SMC1 will be used as the console - -CONFIG_82xx_CONS_SMC2 - - If defined, SMC2 will be used as the console - -CONFIG_SYS_INIT_LOCAL_SDRAM - - If defined, the SDRAM on the local bus will be initialized and - mapped at BR2. - - -Acceptance criteria tests: --------------------------- - -The following tests have been conducted to validate the port of U-Boot -to TQM8260: - -1. Operation on serial console: - -With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file, -the U-Boot output appeared on the serial terminal connected to COM1 as -follows: - ------------------------------------------------------------------------------- -=> help -go - start application at address 'addr' -run - run commands in an environment variable -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -rarpboot- boot image via network using RARP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -loads - load S-Record file over serial line -loadb - load binary file over serial line (kermit mode) -md - memory display -mm - memory modify (auto-incrementing) -nm - memory modify (constant address) -mw - memory write (fill) -cp - memory copy -cmp - memory compare -crc32 - checksum calculation -base - print or set address offset -printenv- print environment variables -setenv - set environment variables -saveenv - save environment variables to persistent storage -protect - enable or disable FLASH write protection -erase - erase FLASH memory -flinfo - print FLASH memory information -bdinfo - print Board Info structure -iminfo - print header information for application image -coninfo - print console devices and informations -eeprom - EEPROM sub-system -loop - infinite loop on address range -mtest - simple RAM test -icache - enable or disable instruction cache -dcache - enable or disable data cache -reset - Perform RESET of the CPU -echo - echo args to console -version - print monitor version -help - print online help -? - alias for 'help' -=> ------------------------------------------------------------------------------- - - -2. Flash driver operation - -The following sequence was performed to test the "flinfo" command: - ------------------------------------------------------------------------------- -=> flinfo - -Bank # 1: AMD 29LV640D (64 M, uniform sector) - Size: 32 MB in 128 Sectors - Sector Start Addresses: - 40000000 40040000 (RO) 40080000 400C0000 40100000 - 40140000 40180000 401C0000 40200000 40240000 - 40280000 402C0000 40300000 40340000 40380000 - 403C0000 40400000 40440000 40480000 404C0000 - 40500000 40540000 40580000 405C0000 40600000 - 40640000 40680000 406C0000 40700000 40740000 - 40780000 407C0000 40800000 40840000 40880000 - 408C0000 40900000 40940000 40980000 409C0000 - 40A00000 40A40000 40A80000 40AC0000 40B00000 - 40B40000 40B80000 40BC0000 40C00000 40C40000 - 40C80000 40CC0000 40D00000 40D40000 40D80000 - 40DC0000 40E00000 40E40000 40E80000 40EC0000 - 40F00000 40F40000 40F80000 40FC0000 41000000 - 41040000 41080000 410C0000 41100000 41140000 - 41180000 411C0000 41200000 41240000 41280000 - 412C0000 41300000 41340000 41380000 413C0000 - 41400000 41440000 41480000 414C0000 41500000 - 41540000 41580000 415C0000 41600000 41640000 - 41680000 416C0000 41700000 41740000 41780000 - 417C0000 41800000 41840000 41880000 418C0000 - 41900000 41940000 41980000 419C0000 41A00000 - 41A40000 41A80000 41AC0000 41B00000 41B40000 - 41B80000 41BC0000 41C00000 41C40000 41C80000 - 41CC0000 41D00000 41D40000 41D80000 41DC0000 - 41E00000 41E40000 41E80000 41EC0000 41F00000 - 41F40000 41F80000 41FC0000 -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test the erase command: - ------------------------------------------------------------------------------- -=> cp 0 40080000 10 -Copy to Flash... done -=> erase 40080000 400bffff -Erase Flash from 0x40080000 to 0x400bffff -.. done -Erased 1 sectors -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> cp 0 40080000 10 -Copy to Flash... done -=> erase 1:2 -Erase Flash Sectors 2-2 in Bank # 1 -.. done -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> cp 0 40080000 10 -Copy to Flash... done -=> cp 0 400c0000 10 -Copy to Flash... done -=> erase 1:2-3 -Erase Flash Sectors 2-3 in Bank # 1 -... done -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> md 400c0000 -400c0000: ffffffff ffffffff ffffffff ffffffff ................ -400c0010: ffffffff ffffffff ffffffff ffffffff ................ -400c0020: ffffffff ffffffff ffffffff ffffffff ................ -400c0030: ffffffff ffffffff ffffffff ffffffff ................ -400c0040: ffffffff ffffffff ffffffff ffffffff ................ -400c0050: ffffffff ffffffff ffffffff ffffffff ................ -400c0060: ffffffff ffffffff ffffffff ffffffff ................ -400c0070: ffffffff ffffffff ffffffff ffffffff ................ -400c0080: ffffffff ffffffff ffffffff ffffffff ................ -400c0090: ffffffff ffffffff ffffffff ffffffff ................ -400c00a0: ffffffff ffffffff ffffffff ffffffff ................ -400c00b0: ffffffff ffffffff ffffffff ffffffff ................ -400c00c0: ffffffff ffffffff ffffffff ffffffff ................ -400c00d0: ffffffff ffffffff ffffffff ffffffff ................ -400c00e0: ffffffff ffffffff ffffffff ffffffff ................ -400c00f0: ffffffff ffffffff ffffffff ffffffff ................ -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test the Flash programming commands: - ------------------------------------------------------------------------------- -=> erase 40080000 400bffff -Erase Flash from 0x40080000 to 0x400bffff -.. done -Erased 1 sectors -=> cp 0 40080000 10 -Copy to Flash... done -=> md 0 -00000000: 00000000 00000104 61100200 01000000 ........a....... -00000010: 00000000 00000000 81140000 82000100 ................ -00000020: 01080000 00004000 22800000 00000600 ......@."....... -00000030: 00200800 00000000 10000100 00008000 . .............. -00000040: 00812000 00000200 00020000 80000000 .. ............. -00000050: 00028001 00001000 00040400 00000200 ................ -00000060: 20480000 00000000 20090000 00142000 H...... ..... . -00000070: 00000000 00004000 24210000 10000000 ......@.$!...... -00000080: 02440002 10000000 00200008 00000000 .D....... ...... -00000090: 02440900 00000000 30a40000 00004400 .D......0.....D. -000000a0: 04420800 00000000 00000040 00020000 .B.........@.... -000000b0: 05020000 00100000 00060000 00000000 ................ -000000c0: 00400000 00000000 00080000 00040000 .@.............. -000000d0: 10400000 00800004 00000000 00000200 .@.............. -000000e0: 80890000 00010004 00080000 00000020 ............... -000000f0: 08000000 10000000 00010000 00000000 ................ -=> md 40080000 -40080000: 00000000 00000104 61100200 01000000 ........a....... -40080010: 00000000 00000000 81140000 82000100 ................ -40080020: 01080000 00004000 22800000 00000600 ......@."....... -40080030: 00200800 00000000 10000100 00008000 . .............. -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test storage of the environment -variables in Flash: - ------------------------------------------------------------------------------- -=> setenv foo bar -=> saveenv -Un-Protected 1 sectors -Erasing Flash... -.. done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=> reset -... -=> printenv -bootdelay=CONFIG_BOOTDELAY -baudrate=9600 -ipaddr=192.168.4.7 -serverip=192.168.4.1 -ethaddr=66:55:44:33:22:11 -foo=bar -stdin=serial -stdout=serial -stderr=serial - -Environment size: 170/262140 bytes -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test image download and run over -Ethernet interface (both interfaces were tested): - ------------------------------------------------------------------------------- -=> tftpboot 40000 hello_world.bin -ARP broadcast 1 -TFTP from server 192.168.2.2; our IP address is 192.168.2.7 -Filename 'hello_world.bin'. -Load address: 0x40000 -Loading: ############# -done -Bytes transferred = 65912 (10178 hex) -=> go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test eeprom read/write commands: - ------------------------------------------------------------------------------- -=> md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|... -000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|... -000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L -000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=> eeprom write 40000 0 40 - -EEPROM write: addr 00040000 off 0000 count 64 ... done -=> mw 50000 0 1000 -=> eeprom read 50000 0 40 - -EEPROM read: addr 00050000 off 0000 count 64 ... done -=> md 50000 -00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00050010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x -00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00050040: 00000000 00000000 00000000 00000000 ................ -00050050: 00000000 00000000 00000000 00000000 ................ -00050060: 00000000 00000000 00000000 00000000 ................ -00050070: 00000000 00000000 00000000 00000000 ................ -00050080: 00000000 00000000 00000000 00000000 ................ -00050090: 00000000 00000000 00000000 00000000 ................ -000500a0: 00000000 00000000 00000000 00000000 ................ -000500b0: 00000000 00000000 00000000 00000000 ................ -000500c0: 00000000 00000000 00000000 00000000 ................ -000500d0: 00000000 00000000 00000000 00000000 ................ -000500e0: 00000000 00000000 00000000 00000000 ................ -000500f0: 00000000 00000000 00000000 00000000 ................ -=> ------------------------------------------------------------------------------- - - -Patch per Mon, 06 Aug 2001 17:57:27: - -- upgraded Flash support (added support for the following chips: - AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B) -- BCR tweakage for the 8260 bus mode -- SIUMCR tweakage enabling the MI interrupt (IRQ7) - -To simplify switching between the bus modes, a new configuration -option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h" -file. If it is defined, BCR will be configured for the 60x mode, -otherwise - for the 8260 mode. - -Concerning the SIUMCR modification: it's hard to predict whether it -will induce any problems on the other (60x mode) board. However, the -problems (if they appear) should be easy to notice - if the board -does not boot, it's most likely caused by the DPPC configuration in -SIUMCR. diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c deleted file mode 100644 index c361f188f7..0000000000 --- a/board/tqc/tqm8260/tqm8260.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - - if (i < 0 || strncmp(buf, "TQM82", 5)) { - puts ("### No HW ID - assuming TQM8260\n"); - return (0); - } - - puts (buf); - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - long size8, size9; -#endif - long psize, lsize; - - psize = 16 * 1024 * 1024; - lsize = 0; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#if 0 /* Just for debugging */ -#define prt_br_or(brX,orX) do { \ - ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ - ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ - printf ("\n" \ - #brX " 0x%08x " #orX " 0x%08x " \ - "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ - memctl->memc_ ## brX, memctl->memc_ ## orX, \ - start, start+sizem, (sizem+1)>>20); \ - } while (0) - prt_br_or (br0, or0); - prt_br_or (br1, or1); - prt_br_or (br2, or2); - prt_br_or (br3, or3); -#endif - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - - /* Local SDRAM setup: - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CONFIG_SYS_LSRT; - size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) SDRAM_BASE2_PRELIM); - - if (size8 < size9) { - lsize = size9; - printf ("Local:9COL - %ld MB) using ", lsize >> 20); - } else { - lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - printf ("Local:8COL - %ld MB) using ", lsize >> 20); - } - -#if 0 - /* Set up BR2 so that the local SDRAM goes - * right after the 60x SDRAM - */ - memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | - (CONFIG_SYS_SDRAM_BASE + psize); -#endif -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile deleted file mode 100644 index 58f1b65ff6..0000000000 --- a/board/tqc/tqm8272/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2001-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../tqm8xx/) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c deleted file mode 100644 index fa257b7f3a..0000000000 --- a/board/tqc/tqm8272/nand.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "tqm8272.h" - -/* UPM pattern for bus clock = 66.7 MHz */ -static const uint upmTable67[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 100 MHz */ -static const uint upmTable100[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 133.3 MHz */ -static const uint upmTable133[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -static int chipsel = 0; - -#if defined(CONFIG_CMD_NAND) - -#include -#include - -static u8 hwctl = 0; - -static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - - if (hwctl & 0x1) { - WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS); - } else if (hwctl & 0x2) { - WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS); - } else { - WRITE_NAND(byte, base); - } -} - -static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - } - if (cmd != NAND_CMD_NONE) - upmnand_write_byte (mtd, cmd); -} - -static u_char upmnand_read_byte(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - - return READ_NAND(base); -} - -static int tqm8272_dev_ready(struct mtd_info *mtdinfo) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); \ - return 1; -} - -#ifndef CONFIG_NAND_SPL -static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - buf[i] = *base; -} - -static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - *base = buf[i]; -} - -static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i < len; i++) - if (buf[i] != *base) - return -1; - return 0; -} -#endif /* #ifndef CONFIG_NAND_SPL */ - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - chipsel = chip; -} - -int board_nand_init(struct nand_chip *nand) -{ - static int UpmInit = 0; - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - - if (hwinf.nand == 0) return -1; - - /* Setup the UPM */ - if (UpmInit == 0) { - switch (hwinf.busclk_real) { - case 100000000: - upmconfig (UPMB, (uint *) upmTable100, - sizeof (upmTable100) / sizeof (uint)); - break; - case 133333333: - upmconfig (UPMB, (uint *) upmTable133, - sizeof (upmTable133) / sizeof (uint)); - break; - default: - upmconfig (UPMB, (uint *) upmTable67, - sizeof (upmTable67) / sizeof (uint)); - break; - } - UpmInit = 1; - } - - /* Setup the memctrl */ - memctl->memc_or3 = CONFIG_SYS_NAND_OR; - memctl->memc_br3 = CONFIG_SYS_NAND_BR; - memctl->memc_mbmr = (MxMR_OP_NORM); - - nand->ecc.mode = NAND_ECC_SOFT; - - nand->cmd_ctrl = upmnand_hwcontrol; - nand->read_byte = upmnand_read_byte; - nand->dev_ready = tqm8272_dev_ready; - -#ifndef CONFIG_NAND_SPL - nand->write_buf = tqm8272_write_buf; - nand->read_buf = tqm8272_read_buf; - nand->verify_buf = tqm8272_verify_buf; -#endif - - /* - * Select required NAND chip - */ - board_nand_select_device(nand, 0); - return 0; -} - -#endif diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c deleted file mode 100644 index 334fd6d74b..0000000000 --- a/board/tqc/tqm8272/tqm8272.c +++ /dev/null @@ -1,944 +0,0 @@ -/* - * (C) Copyright 2006 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include -#include -#ifdef CONFIG_PCI -#include -#include -#endif -#include "tqm8272.h" - -#if 0 -#define deb_printf(fmt,arg...) \ - printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) -#else -#define deb_printf(fmt,arg...) \ - do { } while (0) -#endif - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -unsigned long board_get_cpu_clk_f (void); -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */ - /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* UPM pattern for slow init */ -static const uint upmTableSlow[] = -{ - /* Offset UPM Read Single RAM array entry */ - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, - /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry */ - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80, - /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for fast init */ -static const uint upmTableFast[] = -{ - /* Offset UPM Read Single RAM array entry */ - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, - /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry */ - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00, - /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - - puts ("Board: "); - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - puts (p); - } else { - puts ("No HWIB assuming TQM8272"); - } - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -static int get_cas_latency (void) -{ - /* get it from the option -ts in CIB */ - /* default is 3 */ - int ret = 3; - int pos = 0; - char *p = (char *) CIB_INFO_START_ADDR; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return ret; - } - if (*p == '-') { - if ((p[1] == 't') && (p[2] == 's')) { - return (p[4] - '0'); - } - } - p++; - pos++; - } - return ret; -} -#endif - -static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) -{ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - int clk = board_get_cpu_clk_f (); - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); - int cas; - - sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \ - PSDMR_BUFCMD); - if (busmode) { - switch (clk) { - case 66666666: - sdmr |= (PSDMR_RFRC_66MHZ_60X | \ - PSDMR_PRETOACT_66MHZ_60X | \ - PSDMR_WRC_66MHZ_60X | \ - PSDMR_BUFCMD_66MHZ_60X); - break; - case 100000000: - sdmr |= (PSDMR_RFRC_100MHZ_60X | \ - PSDMR_PRETOACT_100MHZ_60X | \ - PSDMR_WRC_100MHZ_60X | \ - PSDMR_BUFCMD_100MHZ_60X); - break; - - } - } else { - switch (clk) { - case 66666666: - sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \ - PSDMR_PRETOACT_66MHZ_SINGLE | \ - PSDMR_WRC_66MHZ_SINGLE | \ - PSDMR_BUFCMD_66MHZ_SINGLE); - break; - case 100000000: - sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \ - PSDMR_PRETOACT_100MHZ_SINGLE | \ - PSDMR_WRC_100MHZ_SINGLE | \ - PSDMR_BUFCMD_100MHZ_SINGLE); - break; - case 133333333: - sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \ - PSDMR_PRETOACT_133MHZ_SINGLE | \ - PSDMR_WRC_133MHZ_SINGLE | \ - PSDMR_BUFCMD_133MHZ_SINGLE); - break; - } - } - cas = get_cas_latency(); - sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK); - sdmr |= cas; - sdmr |= ((cas - 1) << 6); - return sdmr; -#else - return sdmr; -#endif -} - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base, int col) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - sdmr = set_sdram_timing (sdmr_ptr, sdmr, col); - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - long size8, size9; -#endif - long psize; - - psize = 16 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 8); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 9); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 8); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - - -static inline int scanChar (char *p, int len, unsigned long *number) -{ - int akt = 0; - - *number = 0; - while (akt < len) { - if ((*p >= '0') && (*p <= '9')) { - *number *= 10; - *number += *p - '0'; - p += 1; - } else { - if (*p == '-') return akt; - return -1; - } - akt ++; - } - return akt; -} - -static int dump_hwib(void) -{ - HWIB_INFO *hw = &hwinf; - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - if (i < 0) - buf[0] = '\0'; - - if (hw->OK) { - printf ("HWIB on %x\n", HWIB_INFO_START_ADDR); - printf ("serial : %s\n", buf); - printf ("ethaddr: %s\n", hw->ethaddr); - printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr); - printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs); - printf ("CPU : %lu\n", hw->cpunr); - printf ("CAN : %d\n", hw->can); - if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom); - else printf ("No EEprom\n"); - if (hw->nand) { - printf ("NAND : %x\n", hw->nand); - printf ("NAND CS: %d\n", hw->nand_cs); - } else { printf ("No NAND\n");} - printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII")); - printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \ - "60x" : "Single PQII")); - printf ("Option : %lx\n", hw->option); - printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no")); - printf ("CPM Clk: %d\n", hw->cpmcl); - printf ("CPU Clk: %d\n", hw->cpucl); - printf ("Bus Clk: %d\n", hw->buscl); - if (hw->busclk_real_ok) { - printf (" real Clk: %d\n", hw->busclk_real); - } - printf ("CAS : %d\n", get_cas_latency()); - } else { - printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR); - } - return 0; -} - -static inline int search_real_busclk (int *clk) -{ - int part = 0, pos = 0; - char *p = (char *) CIB_INFO_START_ADDR; - int ok = 0; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return 0; - } - switch (part) { - default: - if (*p == '-') { - ++part; - } - break; - case 3: - if (*p == '-') { - ++part; - break; - } - if (*p == 'b') { - ok = 1; - p++; - break; - } - if (ok) { - switch (*p) { - case '6': - *clk = 66666666; - return 1; - break; - case '1': - if (p[1] == '3') { - *clk = 133333333; - } else { - *clk = 100000000; - } - return 1; - break; - } - } - break; - } - p++; - } - return 0; -} - -int analyse_hwib (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int anz; - int part = 1, i = 0, pos = 0; - HWIB_INFO *hw = &hwinf; - - deb_printf(" %s pointer: %p\n", __FUNCTION__, p); - /* Head = TQM */ - if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - deb_printf("No HWIB\n"); - return -1; - } - p += 3; - if (scanChar (p, 4, &hw->cpunr) < 0) { - deb_printf("No CPU\n"); - return -2; - } - p +=4; - - hw->flash = 0x200000 << (*p - 'A'); - p++; - hw->flash_nr = *p - '0'; - p++; - - hw->ram = 0x2000000 << (*p - 'A'); - p++; - if (*p == '2') { - hw->ram_cs = 2; - p++; - } - - if (*p == 'A') hw->can = 1; - if (*p == 'B') hw->can = 2; - p +=1; - p +=1; /* connector */ - if (*p != '0') { - hw->eeprom = 0x1000 << (*p - 'A'); - } - p++; - - if ((*p < '0') || (*p > '9')) { - /* NAND before z-option */ - hw->nand = 0x8000000 << (*p - 'A'); - p++; - hw->nand_cs = *p - '0'; - p += 2; - } - /* z-option */ - anz = scanChar (p, 4, &hw->option); - if (anz < 0) { - deb_printf("No option\n"); - return -3; - } - if (hw->option & 0x8) hw->Bus = 1; - p += anz; - if (*p != '-') { - deb_printf("No -\n"); - return -4; - } - p++; - /* C option */ - if (*p == 'E') { - hw->SecEng = 1; - p++; - } - switch (*p) { - case 'M': hw->cpucl = 266666666; - break; - case 'P': hw->cpucl = 300000000; - break; - case 'T': hw->cpucl = 400000000; - break; - default: - deb_printf("No CPU Clk: %c\n", *p); - return -5; - break; - } - p++; - switch (*p) { - case 'I': hw->cpmcl = 200000000; - break; - case 'M': hw->cpmcl = 300000000; - break; - default: - deb_printf("No CPM Clk\n"); - return -6; - break; - } - p++; - switch (*p) { - case 'B': hw->buscl = 66666666; - break; - case 'E': hw->buscl = 100000000; - break; - case 'F': hw->buscl = 133333333; - break; - default: - deb_printf("No BUS Clk\n"); - return -7; - break; - } - p++; - - hw->OK = 1; - /* search MAC Address */ - while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return 0; - } - switch (part) { - default: - if (*p == ' ') { - ++part; - i = 0; - } - break; - case 3: /* Copy MAC address */ - if (*p == ' ') { - ++part; - i = 0; - break; - } - hw->ethaddr[i++] = *p; - if ((i % 3) == 2) - hw->ethaddr[i++] = ':'; - break; - - } - p++; - } - - hw->busclk_real_ok = search_real_busclk (&hw->busclk_real); - return 0; -} - -#if defined(CONFIG_GET_CPU_STR_F) -/* !! This routine runs from Flash */ -char get_cpu_str_f (char *buf) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int i = 0; - - buf[i++] = 'M'; - buf[i++] = 'P'; - buf[i++] = 'C'; - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - buf[i++] = *&p[3]; - buf[i++] = *&p[4]; - buf[i++] = *&p[5]; - buf[i++] = *&p[6]; - } else { - buf[i++] = '8'; - buf[i++] = '2'; - buf[i++] = '7'; - buf[i++] = 'x'; - } - buf[i++] = 0; - return 0; -} -#endif - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -/* !! This routine runs from Flash */ -unsigned long board_get_cpu_clk_f (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int i = 0; - - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - if (search_real_busclk (&i)) - return i; - } - return CONFIG_8260_CLKIN; -} -#endif - -#if CONFIG_BOARD_EARLY_INIT_R - -static int can_test (unsigned long off) -{ - volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); - - *(base + 0x17) = 'T'; - *(base + 0x18) = 'Q'; - *(base + 0x19) = 'M'; - if ((*(base + 0x17) != 'T') || - (*(base + 0x18) != 'Q') || - (*(base + 0x19) != 'M')) { - return 0; - } - return 1; -} - -static int can_config_one (unsigned long off) -{ - volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); - volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02); - volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f); - unsigned char temp; - - *cpu_if = 0x45; - temp = *ctrl; - temp |= 0x40; - *ctrl = temp; - *clkout = 0x20; - temp = *ctrl; - temp &= ~0x40; - *ctrl = temp; - return 0; -} - -static int can_config (void) -{ - int ret = 0; - can_config_one (0); - if (hwinf.can == 2) { - can_config_one (0x100); - } - /* make Test if they really there */ - ret += can_test (0); - ret += can_test (0x100); - return ret; -} - -static int init_can (void) -{ - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - int count = 0; - - if ((hwinf.OK) && (hwinf.can)) { - memctl->memc_or4 = CONFIG_SYS_CAN_OR; - memctl->memc_br4 = CONFIG_SYS_CAN_BR; - /* upm Init */ - upmconfig (UPMC, (uint *) upmTableFast, - sizeof (upmTableFast) / sizeof (uint)); - memctl->memc_mcmr = (MxMR_DSx_3_CYCL | - MxMR_GPL_x4DIS | - MxMR_RLFx_2X | - MxMR_WLFx_2X | - MxMR_OP_NORM); - /* can configure */ - count = can_config (); - printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE); - if (hwinf.can != count) printf("!!! difference to HWIB\n"); - } else { - printf ("CAN: No\n"); - } - return 0; -} - -int board_early_init_r(void) -{ - analyse_hwib (); - init_can (); - return 0; -} -#endif - -int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - dump_hwib (); - return 0; -} - -U_BOOT_CMD( - hwib, 1, 1, do_hwib_dump, - "dump HWIB'", - "" -); - -#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE -static int get_flash_timing (void) -{ - /* get it from the option -tf in CIB */ - /* default is 0x00000c84 */ - int ret = 0x00000c84; - int pos = 0; - int nr = 0; - char *p = (char *) CIB_INFO_START_ADDR; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return ret; - } - if (*p == '-') { - if ((p[1] == 't') && (p[2] == 'f')) { - p += 6; - ret = 0; - while (nr < 8) { - if ((*p >= '0') && (*p <= '9')) { - ret *= 0x10; - ret += *p - '0'; - p += 1; - nr ++; - } else if ((*p >= 'A') && (*p <= 'F')) { - ret *= 10; - ret += *p - '7'; - p += 1; - nr ++; - } else { - if (nr < 8) return 0x00000c84; - return ret; - } - } - } - } - p++; - pos++; - } - return ret; -} - -/* Update the Flash_Size and the Flash Timing */ -int update_flash_size (int flash_size) -{ - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - unsigned long reg; - unsigned long tim; - - /* I must use reg, otherwise the board hang */ - reg = memctl->memc_or0; - reg &= ~ORxU_AM_MSK; - reg |= MEG_TO_AM(flash_size >> 20); - tim = get_flash_timing (); - reg &= ~0xfff; - reg |= (tim & 0xfff); - memctl->memc_or0 = reg; - return 0; -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -int board_early_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; - return 0; -} - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm8272/tqm8272.h b/board/tqc/tqm8272/tqm8272.h deleted file mode 100644 index 2205d51b06..0000000000 --- a/board/tqc/tqm8272/tqm8272.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TQM8272_HEADER_H -#define _TQM8272_HEADER_H - -#define _NOT_USED_ 0xFFFFFFFF - -typedef struct{ - int Bus; - int flash; - int flash_nr; - int ram; - int ram_cs; - int nand; - int nand_cs; - int eeprom; - int can; - unsigned long cpunr; - unsigned long option; - int SecEng; - int cpucl; - int cpmcl; - int buscl; - int busclk_real_ok; - int busclk_real; - unsigned char OK; - unsigned char ethaddr[20]; -} HWIB_INFO; - -static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, - 0, 0, 0, 0, 0, 0}; -#endif /* __CONFIG_H */ diff --git a/board/tqc/tqm834x/Kconfig b/board/tqc/tqm834x/Kconfig new file mode 100644 index 0000000000..028b8466e8 --- /dev/null +++ b/board/tqc/tqm834x/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TQM834X + +config SYS_BOARD + default "tqm834x" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM834x" + +endif diff --git a/board/tqc/tqm834x/MAINTAINERS b/board/tqc/tqm834x/MAINTAINERS new file mode 100644 index 0000000000..543ab1b552 --- /dev/null +++ b/board/tqc/tqm834x/MAINTAINERS @@ -0,0 +1,6 @@ +TQM834X BOARD +#M: - +S: Maintained +F: board/tqc/tqm834x/ +F: include/configs/TQM834x.h +F: configs/TQM834x_defconfig diff --git a/board/tqc/tqm834x/Makefile b/board/tqc/tqm834x/Makefile index 0692bb181f..12edc9af06 100644 --- a/board/tqc/tqm834x/Makefile +++ b/board/tqc/tqm834x/Makefile @@ -7,26 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += tqm834x.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 814fcb2657..d891a3844c 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -414,12 +414,14 @@ static void set_ddr_config(void) { } #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif /* CONFIG_PCI */ + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/tqc/tqm8xx/Kconfig b/board/tqc/tqm8xx/Kconfig new file mode 100644 index 0000000000..857fedb8be --- /dev/null +++ b/board/tqc/tqm8xx/Kconfig @@ -0,0 +1,155 @@ +if TARGET_TQM823L + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM823L" + +endif + +if TARGET_TQM823M + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM823M" + +endif + +if TARGET_TQM850L + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM850L" + +endif + +if TARGET_TQM850M + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM850M" + +endif + +if TARGET_TQM855L + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM855L" + +endif + +if TARGET_TQM855M + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM855M" + +endif + +if TARGET_TQM860L + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM860L" + +endif + +if TARGET_TQM860M + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM860M" + +endif + +if TARGET_TQM862L + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM862L" + +endif + +if TARGET_TQM862M + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM862M" + +endif + +if TARGET_TQM866M + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM866M" + +endif + +if TARGET_TQM885D + +config SYS_BOARD + default "tqm8xx" + +config SYS_VENDOR + default "tqc" + +config SYS_CONFIG_NAME + default "TQM885D" + +endif diff --git a/board/tqc/tqm8xx/MAINTAINERS b/board/tqc/tqm8xx/MAINTAINERS new file mode 100644 index 0000000000..f3ddc6a530 --- /dev/null +++ b/board/tqc/tqm8xx/MAINTAINERS @@ -0,0 +1,31 @@ +TQM8XX BOARD +M: Wolfgang Denk +S: Maintained +F: board/tqc/tqm8xx/ +F: include/configs/TQM823L.h +F: configs/TQM823L_defconfig +F: configs/TQM823L_LCD_defconfig +F: include/configs/TQM823M.h +F: configs/TQM823M_defconfig +F: include/configs/TQM850L.h +F: configs/TQM850L_defconfig +F: include/configs/TQM850M.h +F: configs/TQM850M_defconfig +F: include/configs/TQM855L.h +F: configs/TQM855L_defconfig +F: include/configs/TQM855M.h +F: configs/TQM855M_defconfig +F: include/configs/TQM860L.h +F: configs/TQM860L_defconfig +F: include/configs/TQM860M.h +F: configs/TQM860M_defconfig +F: include/configs/TQM862L.h +F: configs/TQM862L_defconfig +F: include/configs/TQM862M.h +F: configs/TQM862M_defconfig +F: include/configs/TQM866M.h +F: configs/TQM866M_defconfig +F: include/configs/TQM885D.h +F: configs/TQM885D_defconfig +F: configs/TTTech_defconfig +F: configs/wtk_defconfig diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile index 787ecc2b2d..2651a2f99f 100644 --- a/board/tqc/tqm8xx/Makefile +++ b/board/tqc/tqm8xx/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o load_sernum_ethaddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = tqm8xx.o load_sernum_ethaddr.o diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 9ce2a5739f..6d17830575 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -118,9 +118,7 @@ int checkboard (void) break; putc (buf[i]); } -#ifdef CONFIG_VIRTLAB2 - puts (" (Virtlab2)"); -#endif + putc ('\n'); return (0); @@ -512,14 +510,6 @@ int misc_init_r (void) immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ # endif -#ifdef CONFIG_NSCU - /* wake up ethernet module */ - immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ - immap->im_ioport.iop_pcdir |= 0x0004; /* output */ - immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ - immap->im_ioport.iop_pcdat |= 0x0004; /* enable */ -#endif /* CONFIG_NSCU */ - return (0); } #endif /* CONFIG_MISC_INIT_R */ @@ -674,55 +664,11 @@ void ft_blob_update (void *blob, bd_t *bd) } } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); ft_blob_update(blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ - -/* ---------------------------------------------------------------------------- */ -/* TK885D specific initializaion */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_TK885D -#include -int last_stage_init(void) -{ - const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY}; - unsigned short reg; - int ret, i = 100; - char *s; - - mii_init(); - /* Without this delay 0xff is read from the UART buffer later in - * abortboot() and autoboot is aborted */ - udelay(10000); - while (tstc() && i--) - (void)getc(); - - /* Check if auto-negotiation is prohibited */ - s = getenv("phy_auto_nego"); - - if (!s || !strcmp(s, "on")) - /* Nothing to do - autonegotiation by default */ - return 0; - - for (i = 0; i < 2; i++) { - ret = miiphy_read("FEC", phy[i], MII_BMCR, ®); - if (ret) { - printf("Cannot read BMCR on PHY %d\n", phy[i]); - return 0; - } - /* Auto-negotiation off, hard set full duplex, 100Mbps */ - ret = miiphy_write("FEC", phy[i], - MII_BMCR, (reg | BMCR_SPEED100 | - BMCR_FULLDPLX) & ~BMCR_ANENABLE); - if (ret) { - printf("Cannot write BMCR on PHY %d\n", phy[i]); - return 0; - } - } return 0; } -#endif +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 1d905e9421..b77ae56c51 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -18,13 +18,13 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) - board/tqc/tqm8xx/libtqm8xx.o (.text*) - disk/libdisk.o (.text*) - drivers/net/libnet.o (.text*) - drivers/pcmcia/libpcmcia.o (.text.pcmcia_on) - drivers/pcmcia/libpcmcia.o (.text.pcmcia_hardware_enable) + arch/powerpc/cpu/mpc8xx/built-in.o (.text*) + arch/powerpc/lib/built-in.o (.text*) + board/tqc/tqm8xx/built-in.o (.text*) + disk/built-in.o (.text*) + drivers/net/built-in.o (.text*) + drivers/built-in.o (.text.pcmcia_on) + drivers/built-in.o (.text.pcmcia_hardware_enable) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv*) diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig new file mode 100644 index 0000000000..f8b3d1fd40 --- /dev/null +++ b/board/tqc/tqma6/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TQMA6 + +config SYS_BOARD + default "tqma6" + +config SYS_VENDOR + default "tqc" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "tqma6" + +endif diff --git a/board/tqc/tqma6/MAINTAINERS b/board/tqc/tqma6/MAINTAINERS new file mode 100644 index 0000000000..91cd244499 --- /dev/null +++ b/board/tqc/tqma6/MAINTAINERS @@ -0,0 +1,6 @@ +TQ SYSTEMS TQMA6 BOARD +M: Markus Niebel +S: Maintained +F: board/tqc/tqma6/ +F: include/configs/tqma6.h +F: configs/tqma6*_defconfig diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile new file mode 100644 index 0000000000..9ee6920abe --- /dev/null +++ b/board/tqc/tqma6/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2014, Markus Niebel +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tqma6.o + +obj-$(CONFIG_MBA6) += tqma6_mba6.o diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README new file mode 100644 index 0000000000..2c012e7b75 --- /dev/null +++ b/board/tqc/tqma6/README @@ -0,0 +1,35 @@ +U-Boot for the TQ Systems TQMa6 modules + +This file contains information for the port of +U-Boot to the TQ Systems TQMa6 modules. + +1. Boot source +-------------- + +The following boot source is supported: + +- SD/eMMC +- SPI NOR + +2. Building +------------ + +To build U-Boot for the TQ Systems TQMa6 modules: + + make tqma6___config + make + +x is a placeholder for the CPU variant +q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D) +s - means i.MX6S: TQMa6S (i.MX6S) + +baseboard is a placeholder for the boot device +mmc - means eMMC +spi - mean SPI NOR + +This gives the following configurations: + +tqma6q_mba6_mmc_config +tqma6q_mba6_spi_config +tqma6s_mba6_mmc_config +tqma6s_mba6_spi_config diff --git a/board/tqc/tqma6/clocks.cfg b/board/tqc/tqma6/clocks.cfg new file mode 100644 index 0000000000..d9dd273a2b --- /dev/null +++ b/board/tqc/tqma6/clocks.cfg @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013, 2014 Markus Niebel + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c new file mode 100644 index 0000000000..c9e163e7d5 --- /dev/null +++ b/board/tqc/tqma6/tqma6.c @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tqma6_bb.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static const uint16_t tqma6_emmc_dsr = 0x0100; + +/* eMMC on USDHCI3 always present */ +static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL), + /* eMMC reset */ + NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL), +}; + +/* + * According to board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 eMMC (SD3) on TQMa6 + * mmc1 .. n optional slots used on baseboard + */ +struct fsl_esdhc_cfg tqma6_usdhc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 1; + else + ret = tqma6_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 0; + else + ret = tqma6_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads, + ARRAY_SIZE(tqma6_usdhc3_pads)); + tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) { + puts("Warning: failed to initialize eMMC dev\n"); + } else { + struct mmc *mmc = find_mmc_device(0); + if (mmc) + mmc_set_dsr(mmc, tqma6_emmc_dsr); + } + + tqma6_bb_board_mmc_init(bis); + + return 0; +} + +static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = { + /* SS1 */ + NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), +}; + +#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19) + +static unsigned const tqma6_ecspi1_cs[] = { + TQMA6_SF_CS_GPIO, +}; + +static void tqma6_iomuxc_spi(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i) + gpio_direction_output(tqma6_ecspi1_cs[i], 1); + imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads, + ARRAY_SIZE(tqma6_ecspi1_pads)); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return ((bus == CONFIG_SF_DEFAULT_BUS) && + (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1; +} + +static struct i2c_pads_info tqma6_i2c3_pads = { + /* I2C3: on board LM75, M24C64, */ + .scl = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 6) + } +}; + +static void tqma6_setup_i2c(void) +{ + int ret; + /* + * use logical index for bus, e.g. I2C1 -> 0 + * warn on error + */ + ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); + if (ret) + printf("setup I2C3 failed: %d\n", ret); +} + +int board_early_init_f(void) +{ + return tqma6_bb_board_early_init_f(); +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + tqma6_iomuxc_spi(); + tqma6_setup_i2c(); + + tqma6_bb_board_init(); + + return 0; +} + +static const char *tqma6_get_boardname(void) +{ + u32 cpurev = get_cpu_rev(); + + switch ((cpurev & 0xFF000) >> 12) { + case MXC_CPU_MX6SOLO: + return "TQMa6S"; + break; + case MXC_CPU_MX6DL: + return "TQMa6DL"; + break; + case MXC_CPU_MX6D: + return "TQMa6D"; + break; + case MXC_CPU_MX6Q: + return "TQMa6Q"; + break; + default: + return "??"; + }; +} + +int board_late_init(void) +{ + struct pmic *p; + u32 reg; + + setenv("board_name", tqma6_get_boardname()); + + /* + * configure PFUZE100 PMIC: + * TODO: should go to power_init_board if bus switching is + * fixed in generic power code + */ + power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS); + p = pmic_get("PFUZE100"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + } + + tqma6_bb_board_late_init(); + + return 0; +} + +int checkboard(void) +{ + printf("Board: %s on a %s\n", tqma6_get_boardname(), + tqma6_bb_get_boardname()); + return 0; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +int ft_board_setup(void *blob, bd_t *bd) +{ + /* bring in eMMC dsr settings */ + do_fixup_by_path_u32(blob, + "/soc/aips-bus@02100000/usdhc@02198000", + "dsr", tqma6_emmc_dsr, 2); + tqma6_bb_ft_board_setup(blob, bd); + + return 0; +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6_bb.h b/board/tqc/tqma6/tqma6_bb.h new file mode 100644 index 0000000000..fb7b4626a1 --- /dev/null +++ b/board/tqc/tqma6/tqma6_bb.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2013, 2014 TQ Systems + * Author: Markus Niebel + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TQMA6_BB__ +#define __TQMA6_BB__ + +#include + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc); +int tqma6_bb_board_mmc_getcd(struct mmc *mmc); +int tqma6_bb_board_mmc_init(bd_t *bis); + +int tqma6_bb_board_early_init_f(void); +int tqma6_bb_board_init(void); +int tqma6_bb_board_late_init(void); +int tqma6_bb_checkboard(void); + +const char *tqma6_bb_get_boardname(void); +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, bd_t *bd); +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +#endif diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c new file mode 100644 index 0000000000..bfbe8db11c --- /dev/null +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tqma6_bb.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#if defined(CONFIG_SOC_MX6Q) + +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac + +#elif defined(CONFIG_SOC_MX6S) + +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 + +#else + +#error "need to define target CPU" + +#endif + +#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm) +#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm) +#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_34ohm) +#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_60ohm) + +/* disable on die termination for RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000 +/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000 +/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000 + +#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25) + +static iomux_v3_cfg_t const mba6_enet_pads[] = { + NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL), + + NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL, + ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL), + /* + * these pins are also used for config strapping by phy + */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL, + ENET_RX_PAD_CTRL), + /* KSZ9031 PHY Reset */ + NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL), +}; + +static void mba6_setup_iomuxc_enet(void) +{ + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, + (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, + (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + + imx_iomux_v3_setup_multiple_pads(mba6_enet_pads, + ARRAY_SIZE(mba6_enet_pads)); + + /* Reset PHY */ + gpio_direction_output(ENET_PHY_RESET_GPIO , 0); + /* Need delay 10ms after power on according to KSZ9031 spec */ + udelay(1000 * 10); + gpio_set_value(ENET_PHY_RESET_GPIO, 1); + /* + * KSZ9031 manual: 100 usec wait time after reset before communication + * over MDIO + * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on + * reset before the phy sees a high level + */ + udelay(200); +} + +static iomux_v3_cfg_t const mba6_uart2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL), +}; + +static void mba6_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads, + ARRAY_SIZE(mba6_uart2_pads)); +} + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2) + +int tqma6_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = !gpio_get_value(USDHC2_CD_GPIO); + + return ret; +} + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = gpio_get_value(USDHC2_WP_GPIO); + + return ret; +} + +static struct fsl_esdhc_cfg mba6_usdhc_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 4, +}; + +static iomux_v3_cfg_t const mba6_usdhc2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL), + /* CD */ + NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL), + /* WP */ + NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL), +}; + +int tqma6_bb_board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads, + ARRAY_SIZE(mba6_usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_input(USDHC2_WP_GPIO); + + mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg)) + puts("Warning: failed to initialize SD\n"); + + return 0; +} + +static struct i2c_pads_info mba6_i2c1_pads = { +/* I2C1: MBa6x */ + .scl = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 26) + } +}; + +static void mba6_setup_i2c(void) +{ + int ret; + /* + * use logical index for bus, e.g. I2C1 -> 0 + * warn on error + */ + ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads); + if (ret) + printf("setup I2C1 failed: %d\n", ret); +} + + +static iomux_v3_cfg_t const mba6_ecspi1_pads[] = { + NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL), +}; + +static unsigned const mba6_ecspi1_cs[] = { + IMX_GPIO_NR(3, 24), + IMX_GPIO_NR(3, 25), +}; + +static void mba6_setup_iomuxc_spi(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i) + gpio_direction_output(mba6_ecspi1_cs[i], 1); + imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads, + ARRAY_SIZE(mba6_ecspi1_pads)); +} + +int board_phy_config(struct phy_device *phydev) +{ +/* + * optimized pad skew values depends on CPU variant on the TQMa6x module: + * i.MX6Q/D or i.MX6DL/S + */ +#if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6Q) +#define MBA6X_KSZ9031_CTRL_SKEW 0x0032 +#define MBA6X_KSZ9031_CLK_SKEW 0x03ff +#define MBA6X_KSZ9031_RX_SKEW 0x3333 +#define MBA6X_KSZ9031_TX_SKEW 0x2036 +#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) +#define MBA6X_KSZ9031_CTRL_SKEW 0x0030 +#define MBA6X_KSZ9031_CLK_SKEW 0x03ff +#define MBA6X_KSZ9031_RX_SKEW 0x3333 +#define MBA6X_KSZ9031_TX_SKEW 0x2052 +#else +#error +#endif + /* min rx/tx ctrl delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_CTRL_SKEW); + /* min rx delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_RX_SKEW); + /* max tx delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_TX_SKEW); + /* rx/tx clk skew */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_CLK_SKEW); + + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy */ + phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR), + PHY_INTERFACE_MODE_RGMII); + + if (!phydev) { + free(bus); + puts("No phy found\n"); + return 0; + } + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + puts("FEC MXC: probe failed\n"); + free(phydev); + free(bus); + } + + return 0; +} + +int tqma6_bb_board_early_init_f(void) +{ + mba6_setup_iomuxc_uart(); + + return 0; +} + +int tqma6_bb_board_init(void) +{ + mba6_setup_i2c(); + mba6_setup_iomuxc_spi(); + /* do it here - to have reset completed */ + mba6_setup_iomuxc_enet(); + + return 0; +} + +int tqma6_bb_board_late_init(void) +{ + return 0; +} + +const char *tqma6_bb_get_boardname(void) +{ + return "MBa6x"; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, bd_t *bd) +{ + /* TBD */ +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6q.cfg b/board/tqc/tqma6/tqma6q.cfg new file mode 100644 index 0000000000..f54dff7bf2 --- /dev/null +++ b/board/tqc/tqma6/tqma6q.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6Q/D DDR config Rev. 0100B */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/board/tqc/tqma6/tqma6s.cfg b/board/tqc/tqma6/tqma6s.cfg new file mode 100644 index 0000000000..24d4e2f562 --- /dev/null +++ b/board/tqc/tqma6/tqma6s.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6S DDR config Rev. 0100B */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014 +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/board/trizepsiv/Kconfig b/board/trizepsiv/Kconfig new file mode 100644 index 0000000000..56b255709a --- /dev/null +++ b/board/trizepsiv/Kconfig @@ -0,0 +1,9 @@ +if TARGET_TRIZEPSIV + +config SYS_BOARD + default "trizepsiv" + +config SYS_CONFIG_NAME + default "trizepsiv" + +endif diff --git a/board/trizepsiv/MAINTAINERS b/board/trizepsiv/MAINTAINERS new file mode 100644 index 0000000000..ba48c2e2e0 --- /dev/null +++ b/board/trizepsiv/MAINTAINERS @@ -0,0 +1,7 @@ +TRIZEPSIV BOARD +M: Stefano Babic +S: Maintained +F: board/trizepsiv/ +F: include/configs/trizepsiv.h +F: configs/polaris_defconfig +F: configs/trizepsiv_defconfig diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile index e71625ef40..c49686fc60 100644 --- a/board/trizepsiv/Makefile +++ b/board/trizepsiv/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := conxs.o eeprom.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := conxs.o eeprom.o diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index c0c318f328..1ddf05dcdd 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -21,6 +21,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -42,7 +43,7 @@ extern struct serial_device serial_stuart_device; * Miscelaneous platform dependent initialisations */ -int usb_board_init(void) +int board_usb_init(int index, enum usb_init_type init) { writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), @@ -69,9 +70,9 @@ int usb_board_init(void) return 0; } -void usb_board_init_fail(void) +int board_usb_cleanup(int index, enum usb_init_type init) { - return; + return 0; } void usb_board_stop(void) diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c index d8195b6d75..1318edc5d6 100644 --- a/board/trizepsiv/eeprom.c +++ b/board/trizepsiv/eeprom.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/ttcontrol/vision2/Kconfig b/board/ttcontrol/vision2/Kconfig new file mode 100644 index 0000000000..cacd2c5dfe --- /dev/null +++ b/board/ttcontrol/vision2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_VISION2 + +config SYS_BOARD + default "vision2" + +config SYS_VENDOR + default "ttcontrol" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "vision2" + +endif diff --git a/board/ttcontrol/vision2/MAINTAINERS b/board/ttcontrol/vision2/MAINTAINERS new file mode 100644 index 0000000000..cfc9903c71 --- /dev/null +++ b/board/ttcontrol/vision2/MAINTAINERS @@ -0,0 +1,6 @@ +VISION2 BOARD +M: Stefano Babic +S: Maintained +F: board/ttcontrol/vision2/ +F: include/configs/vision2.h +F: configs/vision2_defconfig diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile index dc4bbf2770..c3e1e87f3d 100644 --- a/board/ttcontrol/vision2/Makefile +++ b/board/ttcontrol/vision2/Makefile @@ -6,23 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := vision2.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := vision2.o diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg index 4e6583ac76..c74973edec 100644 --- a/board/ttcontrol/vision2/imximage_hynix.cfg +++ b/board/ttcontrol/vision2/imximage_hynix.cfg @@ -124,7 +124,7 @@ DATA 4 0x73fa889c 0x00000000 /* ESDCTL0: Enable controller */ DATA 4 0x83fd9000 0x83220000 -/* Init DRAM on CS0 / +/* Init DRAM on CS0 */ /* ESDSCR: Precharge command */ DATA 4 0x83fd9014 0x04008008 /* ESDSCR: Refresh command */ diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index b4d3994158..247991d588 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -144,6 +145,11 @@ static void setup_uart(void) } #ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 1) ? 121 : -1; +} + void spi_io_init(void) { static const iomux_v3_cfg_t spi_pads[] = { diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000000..1ac0aec773 --- /dev/null +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + diff --git a/board/udoo/Kconfig b/board/udoo/Kconfig new file mode 100644 index 0000000000..970f39f0f7 --- /dev/null +++ b/board/udoo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_UDOO + +config SYS_BOARD + default "udoo" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "udoo" + +endif diff --git a/board/udoo/MAINTAINERS b/board/udoo/MAINTAINERS new file mode 100644 index 0000000000..ee8b61e37e --- /dev/null +++ b/board/udoo/MAINTAINERS @@ -0,0 +1,6 @@ +UDOO BOARD +M: Fabio Estevam +S: Maintained +F: board/udoo/ +F: include/configs/udoo.h +F: configs/udoo_quad_defconfig diff --git a/board/udoo/Makefile b/board/udoo/Makefile new file mode 100644 index 0000000000..80efadaf0d --- /dev/null +++ b/board/udoo/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := udoo.o diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg new file mode 100644 index 0000000000..9cd1af128f --- /dev/null +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg new file mode 100644 index 0000000000..78cbe17db4 --- /dev/null +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c new file mode 100644 index 0000000000..e9236d444c --- /dev/null +++ b/board/udoo/udoo.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define WDT_EN IMX_GPIO_NR(5, 4) +#define WDT_TRG IMX_GPIO_NR(3, 19) + +int dram_init(void) +{ + gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19, +}; + +int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* + * Bug: Apparently uDoo does not works with Gigabit switches... + * Limiting speed to 10/100Mbps, and setting master mode, seems to + * be the only way to have a successfull PHY auto negotiation. + * How to fix: Understand why Linux kernel do not have this issue. + */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + return 0; +} + +static iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* RGMII reset */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Ethernet power supply */ + MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + udelay(20); + gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */ + + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */ + + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + udelay(1000); + + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */ + + /* Need 100ms delay to exit from reset. */ + udelay(1000 * 100); + + gpio_free(IMX_GPIO_NR(6, 24)); + gpio_free(IMX_GPIO_NR(6, 25)); + gpio_free(IMX_GPIO_NR(6, 27)); + gpio_free(IMX_GPIO_NR(6, 28)); + gpio_free(IMX_GPIO_NR(6, 29)); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +static void setup_iomux_wdog(void) +{ + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + gpio_direction_output(WDT_TRG, 0); + gpio_direction_output(WDT_EN, 1); + gpio_direction_input(WDT_TRG); +} + +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Always present */ +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg.max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} + +int board_early_init_f(void) +{ + setup_iomux_wdog(); + setup_iomux_uart(); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: Udoo\n"); + + return 0; +} diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg new file mode 100644 index 0000000000..8d7ff25f7f --- /dev/null +++ b/board/udoo/udoo.cfg @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/utx8245/Makefile b/board/utx8245/Makefile deleted file mode 100644 index 4cf57cea79..0000000000 --- a/board/utx8245/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Gregory E. Allen, gallen@arlut.utexas.edu -# Matthew E. Karger, karger@arlut.utexas.edu -# Applied Research Laboratories, The University of Texas at Austin -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c deleted file mode 100644 index 1dfcb41513..0000000000 --- a/board/utx8245/flash.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ -#define MAIN_SECT_SIZE 0x10000 -#define SECT_SIZE_32KB 0x8000 -#define SECT_SIZE_8KB 0x2000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static int write_word (flash_info_t * info, ulong dest, ulong data); -#if 0 -static void write_via_fpu (vu_long * addr, ulong * data); -#endif -static __inline__ unsigned long get_msr (void); -static __inline__ void set_msr (unsigned long msr); - -/*flash command address offsets*/ -#define ADDR0 (0x555) -#define ADDR1 (0xAAA) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*---------------------------------------------------------------------*/ -/*#define DEBUG_FLASH 1 */ - -/*---------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - int i; /* flash bank counter */ - int j; /* flash device sector counter */ - int k; /* flash size calculation loop counter */ - int N; /* pow(2,N) is flash size, but we don't have */ - ulong total_size = 0, device_size = 1; - unsigned char manuf_id, device_id; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - vu_char *addr = (vu_char *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0x555] = 0xAA; /* get manuf/device info command */ - addr[0x2AA] = 0x55; /* 3-cycle command */ - addr[0x555] = 0x90; - - manuf_id = addr[0]; /* read back manuf/device info */ - device_id = addr[1]; - - addr[0x55] = 0x98; /* CFI command */ - N = addr[0x27]; /* read back device_size = pow(2,N) */ - - for (k = 0; k < N; k++) /* calculate device_size = pow(2,N) */ - device_size *= 2; - - flash_info[i].size = device_size; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - -#if defined DEBUG_FLASH - printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id); -#endif - /* find out what kind of flash we are using */ - if ((manuf_id == (uchar) (AMD_MANUFACT)) - && (device_id == AMD_ID_LV033C)) { - flash_info[i].flash_id = - ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | - (FLASH_AM033C & FLASH_TYPEMASK); - - /* set individual sector start addresses */ - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - } - } - - else if ((manuf_id == (uchar) (AMD_MANUFACT)) && - (device_id == AMD_ID_LV116DT)) { - flash_info[i].flash_id = - ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | - (FLASH_AM160T & FLASH_TYPEMASK); - - /* set individual sector start addresses */ - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - - if (j < (CONFIG_SYS_MAX_FLASH_SECT - 3)) { - flash_info[i].start[j] = - (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - } else if (j == (CONFIG_SYS_MAX_FLASH_SECT - 3)) { - flash_info[i].start[j] = - (flash_info[i].start[j - 1] + SECT_SIZE_32KB); - - } else { - flash_info[i].start[j] = - (flash_info[i].start[j - 1] + SECT_SIZE_8KB); - } - } - } - - else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFF; - goto Done; - } - -#if defined DEBUG_FLASH - printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id); -#endif - - addr[0] = 0xFF; - - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - total_size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - Done: - return total_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM033C: - type = "AM29LV033C (32 Mbit, uniform sector size)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> - start[sect] - - info-> - start[0]) << - sh8b)); - - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else { - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ -#if 0 -static void write_via_fpu (vu_long * addr, ulong * data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); -} -#endif - -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); -} diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c deleted file mode 100644 index 69d19e39e9..0000000000 --- a/board/utx8245/utx8245.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#define SAVE_SZ 32 - - -int checkboard(void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; -} - - -phys_size_t initdram(int board_type) -{ - long size; - long new_bank0_end; - long new_bank1_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size/2 - 1; - new_bank1_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - - mear1 = (mear1 & 0xFFFF0000) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - ((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8); - emear1 = (emear1 & 0xFFFF0000) | - ((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - ((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8); - - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - - -/* - * Initialize PCI Devices, report devices found. - */ - -static struct pci_config_table pci_utx8245_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR, - PCI_FIREWIRE_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, -#endif /*CONFIG_PCI_PNP*/ - { } -}; - - -static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - if (PCI_DEV(dev) == 11) - /* assign serial interrupt line 9 (int25) to FireWire */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25); - - else if (PCI_DEV(dev) == 12) - /* assign serial interrupt line 8 (int24) to Ethernet */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24); - - else if (PCI_DEV(dev) == 14) - /* assign serial interrupt line 0 (int16) to PMC slot 0 */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16); - - else if (PCI_DEV(dev) == 15) - /* assign serial interrupt line 1 (int17) to PMC slot 1 */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17); -} - -static struct pci_controller utx8245_hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_utx8245_config_table, - fixup_irq: pci_utx8245_fixup_irq, - write_byte: pci_hose_write_config_byte -#endif /*CONFIG_PCI_PNP*/ -}; - -void pci_init_board (void) -{ - pci_mpc824x_init(&utx8245_hose); - - icache_enable(); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/v37/Makefile b/board/v37/Makefile deleted file mode 100644 index 1284818686..0000000000 --- a/board/v37/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/v37/flash.c b/board/v37/flash.c deleted file mode 100644 index 5b34af249b..0000000000 --- a/board/v37/flash.c +++ /dev/null @@ -1,543 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips); -static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id); -static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - short manu, dev_id; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b0); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE0 - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_get_id_long((void*)CONFIG_SYS_FLASH_BASE1,&manu,&dev_id); - - size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE1, &flash_info[1],1); - - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b1); - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0+size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips) -{ - int i, addr_shift; - vu_short *addr = (vu_short*)base; - - addr[0x555] = 0x00AA ; - addr[0xAAA] = 0x0055 ; - addr[0x555] = 0x0090 ; - - addr_shift = (two_chips ? 2 : 1 ); - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + (0x00000000<start[1] = base + (0x00002000<start[2] = base + (0x00003000<start[3] = base + (0x00004000<sector_count; i++) { - info->start[i] = base + ((i-3) * (0x00008000<sector_count - 1; - info->start[i--] = base + info->size - (0x00002000<start[i--] = base + info->size - (0x00003000<start[i--] = base + info->size - (0x00004000<= 0; i--) { - info->start[i] = base + i * (0x00008000<sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (vu_short *)(info->start[i]); - info->protect[i] = addr[1<start[0]; - *addr = 0xF0F0; /* reset bank */ -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_TOSH: printf ("TOSHIBA "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id) -{ - vu_short *addr = (vu_short*)ptr; - - addr[0x555] = 0x00AA ; - addr[0xAAA] = 0x0055 ; - addr[0x555] = 0x0090 ; - - *ptr_manuf = addr[0]; - *ptr_dev_id = addr[1]; - - addr[0] = 0xf0f0; /* return to normal */ -} - -static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id) -{ - vu_short *addr = (vu_short*)ptr; - vu_short *addr1, *addr2, *addr3; - - addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); - addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) ); - addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); - - *addr1 = 0xAAAA; - *addr2 = 0x5555; - *addr3 = 0x9090; - - *ptr_manuf = addr[0]; - *ptr_dev_id = addr[2]; - - addr[0] = 0xf0f0; /* return to normal */ -} - -static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info) -{ - switch (manu) { - case ((short)AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case ((short)FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case ((short)TOSH_MANUFACT): - info->flash_id = FLASH_MAN_TOSH; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - - switch (dev_id) { - case ((short)TOSH_ID_FVT160): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 1 MB */ - - case ((short)TOSH_ID_FVB160): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV400T): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV400B): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV800T): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case ((short)AMD_ID_LV800B): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case ((short)AMD_ID_LV160T): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 4 MB */ - - case ((short)AMD_ID_LV160B): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = (vu_short)0xAAAAAAAA; - addr[0xAAA] = (vu_short)0x55555555; - addr[0x555] = (vu_short)0x80808080; - addr[0x555] = (vu_short)0xAAAAAAAA; - addr[0xAAA] = (vu_short)0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect]) ; - addr[0] = (vu_short)0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short *)(info->start[l_sect]); - while ((addr[0] & 0x8080) != 0x8080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = (vu_short)0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short *)(info->start[0]); - vu_short sdata; - - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* First write upper 16 bits */ - sdata = (short)(data>>16); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = 0xAAAA; - addr[0xAAA] = 0x5555; - addr[0x555] = 0xA0A0; - - *((vu_short *)dest) = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - /* Now write lower 16 bits */ - sdata = (short)(data&0xffff); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = 0xAAAA; - addr[0xAAA] = 0x5555; - addr[0x555] = 0xA0A0; - - *((vu_short *)dest + 1) = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds deleted file mode 100644 index 6e19b3f458..0000000000 --- a/board/v37/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2003-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/v37/v37.c b/board/v37/v37.c deleted file mode 100644 index 438117e60c..0000000000 --- a/board/v37/v37.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (void); - -/* ------------------------------------------------------------------------- */ - -#define MBYTE (1024*1024) -#define DRAM_DELAY 0x00000379 /* DRAM delay count */ -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000, - 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, - - /* burst read. (Offset 8 in upm RAM) */ - 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000, - 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* single write. (Offset 0x18 in upm RAM) */ - 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* burst write. (Offset 0x20 in upm RAM) */ - 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000, - 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh cycle, offset 0x30 */ - 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception, 0ffset 0x3C */ - 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Return 1 for now. - * - */ - -int checkboard (void) -{ - printf("Marel V37\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long temp; - volatile int delay_cnt; - long int ramsize; - - ramsize = dram_size(); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = 0x400 ; - - if( ramsize == 32*MBYTE ) - temp = 0xd0904110; - else /* 16MB */ - temp = 0xd0802110; - - memctl->memc_mbmr = temp; - - upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Map controller banks 2 to the SDRAM bank */ - memctl->memc_or2 = 0xA00 | (0 - ramsize); - memctl->memc_br2 = 0xC1; - - memctl->memc_mbmr = temp | 0x08; - memctl->memc_mcr = 0x80804130; - - delay_cnt = 0; - while( delay_cnt++ < DRAM_DELAY ) - ; - - /* Run MRS command in location 5-8 of UPMB */ - - memctl->memc_mbmr = temp | 0x04; - memctl->memc_mar = 0x88; - - memctl->memc_mcr = 0x80804105; - - delay_cnt = 0; - while( delay_cnt++ < DRAM_DELAY ) - ; - -#ifdef CONFIG_CAN_DRIVER - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMA; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMA; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMA; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMA; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMA; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMA; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMA; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMA; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMA; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMA; -#endif /* CONFIG_CAN_DRIVER */ - - return (dram_size()); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Find size of RAM from configuration pins. - * The input pins that contain the memory size are also the debug port - * pins. Normally they are configured as debug port pins. To be able - * to read the memory configuration, we must deactivate the debug port - * and enable the pcmcia input pins. Then return the register to - * previous state. - */ - -static long int dram_size () -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile sysconf8xx_t *siu = &immap->im_siu_conf; - volatile pcmconf8xx_t *pcm = &immap->im_pcmcia; - long int i, memory=1; - unsigned long siu_mcr; - - siu_mcr = siu->sc_siumcr; - siu->sc_siumcr = siu_mcr & 0xFF9FFFFF; - for(i=0; i<10; i++) i = i; - - memory = (pcm->pcmc_pipr>>12) & 0x3; - - siu->sc_siumcr = siu_mcr; - - switch( memory ) - { - case 1: - return( 32*MBYTE ); - case 2: - return( 64*MBYTE ); - default: - break; - } - return( 16*MBYTE ); -} diff --git a/board/v38b/Kconfig b/board/v38b/Kconfig new file mode 100644 index 0000000000..653bfc1c3b --- /dev/null +++ b/board/v38b/Kconfig @@ -0,0 +1,9 @@ +if TARGET_V38B + +config SYS_BOARD + default "v38b" + +config SYS_CONFIG_NAME + default "v38b" + +endif diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS new file mode 100644 index 0000000000..d1a6ae6b2f --- /dev/null +++ b/board/v38b/MAINTAINERS @@ -0,0 +1,6 @@ +V38B BOARD +#M: - +S: Maintained +F: board/v38b/ +F: include/configs/v38b.h +F: configs/v38b_defconfig diff --git a/board/v38b/Makefile b/board/v38b/Makefile index 5c8bb6f505..a20a5ef0e9 100644 --- a/board/v38b/Makefile +++ b/board/v38b/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o ethaddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := v38b.o ethaddr.o diff --git a/board/ve8313/Kconfig b/board/ve8313/Kconfig new file mode 100644 index 0000000000..a63744b154 --- /dev/null +++ b/board/ve8313/Kconfig @@ -0,0 +1,9 @@ +if TARGET_VE8313 + +config SYS_BOARD + default "ve8313" + +config SYS_CONFIG_NAME + default "ve8313" + +endif diff --git a/board/ve8313/MAINTAINERS b/board/ve8313/MAINTAINERS new file mode 100644 index 0000000000..e3ca3325fc --- /dev/null +++ b/board/ve8313/MAINTAINERS @@ -0,0 +1,6 @@ +VE8313 BOARD +M: Heiko Schocher +S: Maintained +F: board/ve8313/ +F: include/configs/ve8313.h +F: configs/ve8313_defconfig diff --git a/board/ve8313/Makefile b/board/ve8313/Makefile index ff0dbf869d..41258f9722 100644 --- a/board/ve8313/Makefile +++ b/board/ve8313/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ve8313.o diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index c4feef8196..7f24a30688 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -192,11 +192,13 @@ void pci_init_board(void) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/vpac270/Kconfig b/board/vpac270/Kconfig new file mode 100644 index 0000000000..1701b35d12 --- /dev/null +++ b/board/vpac270/Kconfig @@ -0,0 +1,9 @@ +if TARGET_VPAC270 + +config SYS_BOARD + default "vpac270" + +config SYS_CONFIG_NAME + default "vpac270" + +endif diff --git a/board/vpac270/MAINTAINERS b/board/vpac270/MAINTAINERS new file mode 100644 index 0000000000..1c627657ba --- /dev/null +++ b/board/vpac270/MAINTAINERS @@ -0,0 +1,8 @@ +VPAC270 BOARD +M: Marek Vasut +S: Maintained +F: board/vpac270/ +F: include/configs/vpac270.h +F: configs/vpac270_nor_128_defconfig +F: configs/vpac270_nor_256_defconfig +F: configs/vpac270_ond_256_defconfig diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile index a138aa4da7..ad7f7d8d66 100644 --- a/board/vpac270/Makefile +++ b/board/vpac270/Makefile @@ -6,27 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - ifndef CONFIG_SPL_BUILD -COBJS := vpac270.o +obj-y := vpac270.o else -COBJS := onenand.o +obj-y := onenand.o endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 7eac4975ba..a10ea71e9d 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -19,9 +19,11 @@ SECTIONS . = CONFIG_SPL_TEXT_BASE; .text.0 : { + *(.vectors) arch/arm/cpu/pxa/start.o (.text*) - board/vpac270/libvpac270.o (.text*) - drivers/mtd/onenand/libonenand.o (.text*) + arch/arm/lib/built-in.o (.text*) + board/vpac270/built-in.o (.text*) + drivers/mtd/onenand/built-in.o (.text*) } @@ -53,7 +55,12 @@ SECTIONS . = ALIGN(0x800); - _end = .; + .end : + { + *(.__end) + } + + _image_binary_end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; @@ -62,13 +69,13 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 616736f5c4..8d777df846 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -13,6 +13,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -66,7 +67,7 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_CMD_USB -int usb_board_init(void) +int board_usb_init(int index, enum usb_init_type init) { writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), @@ -97,9 +98,9 @@ int usb_board_init(void) return 0; } -void usb_board_init_fail(void) +int board_usb_cleanup(int index, enum usb_init_type init) { - return; + return 0; } void usb_board_stop(void) diff --git a/board/w7o/Kconfig b/board/w7o/Kconfig new file mode 100644 index 0000000000..fd1b422318 --- /dev/null +++ b/board/w7o/Kconfig @@ -0,0 +1,19 @@ +if TARGET_W7OLMC + +config SYS_BOARD + default "w7o" + +config SYS_CONFIG_NAME + default "W7OLMC" + +endif + +if TARGET_W7OLMG + +config SYS_BOARD + default "w7o" + +config SYS_CONFIG_NAME + default "W7OLMG" + +endif diff --git a/board/w7o/MAINTAINERS b/board/w7o/MAINTAINERS new file mode 100644 index 0000000000..bfedee5748 --- /dev/null +++ b/board/w7o/MAINTAINERS @@ -0,0 +1,8 @@ +W7O BOARD +M: Erik Theisen +S: Maintained +F: board/w7o/ +F: include/configs/W7OLMC.h +F: configs/W7OLMC_defconfig +F: include/configs/W7OLMG.h +F: configs/W7OLMG_defconfig diff --git a/board/w7o/Makefile b/board/w7o/Makefile index 85bebaccca..955de50e4f 100644 --- a/board/w7o/Makefile +++ b/board/w7o/Makefile @@ -8,26 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \ +obj-y = w7o.o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \ watchdog.o -SOBJS = init.o post1.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += init.o post1.o diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c index bbb85f39ef..879cb6133c 100644 --- a/board/w7o/cmd_vpd.c +++ b/board/w7o/cmd_vpd.c @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/w7o/errors.h b/board/w7o/errors.h index dfb4558bd1..05540fb2d2 100644 --- a/board/w7o/errors.h +++ b/board/w7o/errors.h @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ERRORS_H_ #define _ERRORS_H_ diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c index 77e0a18022..a27e8ab88f 100644 --- a/board/w7o/fpga.c +++ b/board/w7o/fpga.c @@ -4,7 +4,7 @@ * and * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c index 25fbb55c8e..8f4fe310d7 100644 --- a/board/w7o/fsboot.c +++ b/board/w7o/fsboot.c @@ -8,12 +8,11 @@ #include #include #include +#include /* * FIXME: Add code to test image and it's header. */ -extern int valid_elf_image (unsigned long addr); - static int image_check(ulong addr) { diff --git a/board/w7o/init.S b/board/w7o/init.S index b3aadcace3..dfde149956 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -1,31 +1,9 @@ -/****************************************************************************** - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/w7o/post1.S b/board/w7o/post1.S index 8a1b9e6909..aae5387212 100644 --- a/board/w7o/post1.S +++ b/board/w7o/post1.S @@ -4,7 +4,7 @@ * and * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* * Description: @@ -13,8 +13,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/w7o/post2.c b/board/w7o/post2.c index f16f9a191c..76b65975ce 100644 --- a/board/w7o/post2.c +++ b/board/w7o/post2.c @@ -4,7 +4,7 @@ * and * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/wandboard/Kconfig b/board/wandboard/Kconfig new file mode 100644 index 0000000000..3928566715 --- /dev/null +++ b/board/wandboard/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WANDBOARD + +config SYS_BOARD + default "wandboard" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "wandboard" + +endif diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS new file mode 100644 index 0000000000..b986980437 --- /dev/null +++ b/board/wandboard/MAINTAINERS @@ -0,0 +1,8 @@ +WANDBOARD BOARD +M: Fabio Estevam +S: Maintained +F: board/wandboard/ +F: include/configs/wandboard.h +F: configs/wandboard_dl_defconfig +F: configs/wandboard_quad_defconfig +F: configs/wandboard_solo_defconfig diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile index d4782e0c79..5b50ecaf22 100644 --- a/board/wandboard/Makefile +++ b/board/wandboard/Makefile @@ -4,23 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := wandboard.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := wandboard.o diff --git a/board/wandboard/README b/board/wandboard/README index 498db2fd47..1f678e16a9 100644 --- a/board/wandboard/README +++ b/board/wandboard/README @@ -3,8 +3,8 @@ U-Boot for Wandboard This file contains information for the port of U-Boot to the Wandboard. -Wandboard is a development board that has two variants: one version based -on mx6 dual lite and another one based on mx6 solo. +Wandboard is a development board that has three variants based on the following +SoCs: mx6 quad, mx6 dual lite and mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 2b9d4baaa0..18158806f5 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2014 O.S. Systems Software LTDA. * * Author: Fabio Estevam * @@ -15,16 +16,19 @@ #include #include #include +#include #include +#include #include -#include +#include #include #include -#include #include #include #include -#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -39,6 +43,10 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) @@ -51,50 +59,50 @@ int dram_init(void) } static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* Carrier MicroSD Card Detect */ - MX6_PAD_GPIO_2__GPIO_1_2, + MX6_PAD_GPIO_2__GPIO1_IO02, }; static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SOM MicroSD Card Detect */ - MX6_PAD_EIM_DA9__GPIO_3_9, + MX6_PAD_EIM_DA9__GPIO3_IO09, }; static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6_PAD_EIM_D29__GPIO_3_29, + MX6_PAD_EIM_D29__GPIO3_IO29, }; static void setup_iomux_uart(void) @@ -136,7 +144,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; u32 index = 0; /* @@ -165,13 +173,15 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } static int mx6_rgmii_rework(struct phy_device *phydev) @@ -208,98 +218,142 @@ int board_phy_config(struct phy_device *phydev) } #if defined(CONFIG_VIDEO_IPUV3) -static void enable_hdmi(void) -{ - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg; - reg = readb(&hdmi->phy_conf0); - reg |= HDMI_PHY_CONF0_PDZ_MASK; - writeb(reg, &hdmi->phy_conf0); - - udelay(3000); - reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - writeb(reg, &hdmi->phy_conf0); - udelay(3000); - reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - writeb(reg, &hdmi->phy_conf0); - writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); -} +struct i2c_pads_info i2c2_pad_info = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; -static struct fb_videomode const hdmi = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED +static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */ + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 + | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */ + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */ + + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + + MX6_PAD_SD4_DAT2__GPIO2_IO10, /* DISP0_BKLEN */ + MX6_PAD_SD4_DAT3__GPIO2_IO11, /* DISP0_VDDEN */ }; -int board_video_skip(void) +static void do_enable_hdmi(struct display_info_t const *dev) { - int ret; - - ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); + imx_enable_hdmi_phy(); +} - if (ret) - printf("HDMI cannot be configured: %d\n", ret); +static int detect_i2c(struct display_info_t const *dev) +{ + return (0 == i2c_set_bus_num(dev->bus)) && + (0 == i2c_probe(dev->addr)); +} - enable_hdmi(); +static void enable_fwadapt_7wvga(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + fwadapt_7wvga_pads, + ARRAY_SIZE(fwadapt_7wvga_pads)); - return ret; + gpio_direction_output(IMX_GPIO_NR(2, 10), 1); + gpio_direction_output(IMX_GPIO_NR(2, 11), 1); } +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 1, + .addr = 0x10, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_fwadapt_7wvga, + .mode = { + .name = "FWBADAPT-LCD-F07A-0102", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33260, + .left_margin = 128, + .right_margin = 128, + .upper_margin = 22, + .lower_margin = 22, + .hsync_len = 1, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; int reg; - /* Turn on IPU clock */ - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; - writel(reg, &mxc_ccm->CCGR3); - - /* Turn on HDMI PHY clock */ - reg = readl(&mxc_ccm->CCGR2); - reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK - | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; - writel(reg, &mxc_ccm->CCGR2); - - /* clear HDMI PHY reset */ - writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + enable_ipu_clock(); + imx_setup_hdmi(); reg = readl(&mxc_ccm->chsccdr); - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK - | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK - | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) - | (CHSCCDR_PODF_DIVIDE_BY_3 - << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) - | (CHSCCDR_IPU_PRE_CLK_540M_PFD - << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); + + /* Disable LCD backlight */ + imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20); + gpio_direction_input(IMX_GPIO_NR(4, 20)); } #endif /* CONFIG_VIDEO_IPUV3 */ int board_eth_init(bd_t *bis) { - int ret; - setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return 0; + return cpu_eth_init(bis); } int board_early_init_f(void) @@ -343,6 +397,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info); + return 0; } diff --git a/board/woodburn/Kconfig b/board/woodburn/Kconfig new file mode 100644 index 0000000000..4699526cfd --- /dev/null +++ b/board/woodburn/Kconfig @@ -0,0 +1,25 @@ +if TARGET_WOODBURN + +config SYS_BOARD + default "woodburn" + +config SYS_SOC + default "mx35" + +config SYS_CONFIG_NAME + default "woodburn" + +endif + +if TARGET_WOODBURN_SD + +config SYS_BOARD + default "woodburn" + +config SYS_SOC + default "mx35" + +config SYS_CONFIG_NAME + default "woodburn_sd" + +endif diff --git a/board/woodburn/MAINTAINERS b/board/woodburn/MAINTAINERS new file mode 100644 index 0000000000..4fbf6bb88b --- /dev/null +++ b/board/woodburn/MAINTAINERS @@ -0,0 +1,12 @@ +WOODBURN BOARD +M: Stefano Babic +S: Maintained +F: board/woodburn/ +F: include/configs/woodburn.h +F: configs/woodburn_defconfig + +WOODBURN_SD BOARD +#M: - +S: Maintained +F: include/configs/woodburn_sd.h +F: configs/woodburn_sd_defconfig diff --git a/board/woodburn/Makefile b/board/woodburn/Makefile index 89e1f2499c..db2b2d54ed 100644 --- a/board/woodburn/Makefile +++ b/board/woodburn/Makefile @@ -6,25 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := woodburn.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := woodburn.o +obj-y += lowlevel_init.o diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c index 2744514435..3da61a4c3d 100644 --- a/board/woodburn/woodburn.c +++ b/board/woodburn/woodburn.c @@ -137,9 +137,6 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); - /* Set global data pointer. */ - gd = &gdata; - preloader_console_init(); timer_init(); diff --git a/board/xaeniax/Kconfig b/board/xaeniax/Kconfig new file mode 100644 index 0000000000..519e21fb9a --- /dev/null +++ b/board/xaeniax/Kconfig @@ -0,0 +1,9 @@ +if TARGET_XAENIAX + +config SYS_BOARD + default "xaeniax" + +config SYS_CONFIG_NAME + default "xaeniax" + +endif diff --git a/board/xaeniax/MAINTAINERS b/board/xaeniax/MAINTAINERS new file mode 100644 index 0000000000..44bb5883f2 --- /dev/null +++ b/board/xaeniax/MAINTAINERS @@ -0,0 +1,6 @@ +XAENIAX BOARD +#M: - +S: Maintained +F: board/xaeniax/ +F: include/configs/xaeniax.h +F: configs/xaeniax_defconfig diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile index 1081eb4ec3..e5f116debb 100644 --- a/board/xaeniax/Makefile +++ b/board/xaeniax/Makefile @@ -5,23 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := xaeniax.o flash.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := xaeniax.o flash.o diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 2e5f1c522f..65d321abdd 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -5,34 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) -endif - -LIB = $(obj)lib$(VENDOR).o - -COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o -COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o -COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o -COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o -COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o -COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o -COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o +obj-$(CONFIG_MPC8572) += fsl_8xxx_clk.o +obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o +obj-$(CONFIG_P2020) += fsl_8xxx_clk.o +obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o +obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o +obj-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c index 57ff0005b5..2a604d448b 100644 --- a/board/xes/common/fsl_8xxx_clk.c +++ b/board/xes/common/fsl_8xxx_clk.c @@ -1,7 +1,7 @@ /* * Copyright 2008 Extreme Engineering Solutions, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c index dfd6946b5f..2899e1117d 100644 --- a/board/xes/common/fsl_8xxx_misc.c +++ b/board/xes/common/fsl_8xxx_misc.c @@ -1,7 +1,7 @@ /* * Copyright 2008 Extreme Engineering Solutions, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/xes/common/fsl_8xxx_misc.h b/board/xes/common/fsl_8xxx_misc.h index 90e0f45ff7..106bb233a4 100644 --- a/board/xes/common/fsl_8xxx_misc.h +++ b/board/xes/common/fsl_8xxx_misc.h @@ -1,7 +1,7 @@ /* * Copyright 2008 Extreme Engineering Solutions, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __FSL_8XXX_MISC_H___ diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 625594d1b1..510f638ffe 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -2,7 +2,7 @@ * Copyright 2008 Extreme Engineering Solutions, Inc. * Copyright 2007-2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/xes/xpedite1000/Kconfig b/board/xes/xpedite1000/Kconfig new file mode 100644 index 0000000000..4d0ab2f66e --- /dev/null +++ b/board/xes/xpedite1000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_XPEDITE1000 + +config SYS_BOARD + default "xpedite1000" + +config SYS_VENDOR + default "xes" + +config SYS_CONFIG_NAME + default "xpedite1000" + +endif diff --git a/board/xes/xpedite1000/MAINTAINERS b/board/xes/xpedite1000/MAINTAINERS new file mode 100644 index 0000000000..055ce6abce --- /dev/null +++ b/board/xes/xpedite1000/MAINTAINERS @@ -0,0 +1,6 @@ +XPEDITE1000 BOARD +M: Peter Tyser +S: Maintained +F: board/xes/xpedite1000/ +F: include/configs/xpedite1000.h +F: configs/xpedite1000_defconfig diff --git a/board/xes/xpedite1000/Makefile b/board/xes/xpedite1000/Makefile index 1d80df8b74..308de91c9d 100644 --- a/board/xes/xpedite1000/Makefile +++ b/board/xes/xpedite1000/Makefile @@ -5,25 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = xpedite1000.o +extra-y += init.o diff --git a/board/xes/xpedite517x/Kconfig b/board/xes/xpedite517x/Kconfig new file mode 100644 index 0000000000..91bbd22451 --- /dev/null +++ b/board/xes/xpedite517x/Kconfig @@ -0,0 +1,12 @@ +if TARGET_XPEDITE517X + +config SYS_BOARD + default "xpedite517x" + +config SYS_VENDOR + default "xes" + +config SYS_CONFIG_NAME + default "xpedite517x" + +endif diff --git a/board/xes/xpedite517x/MAINTAINERS b/board/xes/xpedite517x/MAINTAINERS new file mode 100644 index 0000000000..26e0acccb0 --- /dev/null +++ b/board/xes/xpedite517x/MAINTAINERS @@ -0,0 +1,6 @@ +XPEDITE517X BOARD +M: Peter Tyser +S: Maintained +F: board/xes/xpedite517x/ +F: include/configs/xpedite517x.h +F: configs/xpedite517x_defconfig diff --git a/board/xes/xpedite517x/Makefile b/board/xes/xpedite517x/Makefile index 0105aa1915..d88c3d4b9a 100644 --- a/board/xes/xpedite517x/Makefile +++ b/board/xes/xpedite517x/Makefile @@ -5,26 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude ($obj).depend - -######################################################################### +obj-y += xpedite517x.o +obj-y += ddr.o +obj-y += law.o diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c index 53cb156fd5..fd602ea7e0 100644 --- a/board/xes/xpedite517x/ddr.c +++ b/board/xes/xpedite517x/ddr.c @@ -2,13 +2,13 @@ * Copyright 2009 Extreme Engineering Solutions, Inc. * Copyright 2007-2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include -#include -#include +#include +#include void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) { diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 1782042510..0028870db0 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include #include @@ -69,11 +69,13 @@ phys_size_t initdram(int board_type) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_board_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/xes/xpedite520x/Kconfig b/board/xes/xpedite520x/Kconfig new file mode 100644 index 0000000000..9c0c2461fd --- /dev/null +++ b/board/xes/xpedite520x/Kconfig @@ -0,0 +1,12 @@ +if TARGET_XPEDITE520X + +config SYS_BOARD + default "xpedite520x" + +config SYS_VENDOR + default "xes" + +config SYS_CONFIG_NAME + default "xpedite520x" + +endif diff --git a/board/xes/xpedite520x/MAINTAINERS b/board/xes/xpedite520x/MAINTAINERS new file mode 100644 index 0000000000..f7bd437cc6 --- /dev/null +++ b/board/xes/xpedite520x/MAINTAINERS @@ -0,0 +1,6 @@ +XPEDITE520X BOARD +M: Peter Tyser +S: Maintained +F: board/xes/xpedite520x/ +F: include/configs/xpedite520x.h +F: configs/xpedite520x_defconfig diff --git a/board/xes/xpedite520x/Makefile b/board/xes/xpedite520x/Makefile index 6c1b85b03b..14841b9c87 100644 --- a/board/xes/xpedite520x/Makefile +++ b/board/xes/xpedite520x/Makefile @@ -7,27 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += xpedite520x.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c index 3671cb8af9..5c5eadc93f 100644 --- a/board/xes/xpedite520x/ddr.c +++ b/board/xes/xpedite520x/ddr.c @@ -9,8 +9,8 @@ #include #include -#include -#include +#include +#include void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) { diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c index aa9e99d108..6a3df52391 100644 --- a/board/xes/xpedite520x/xpedite520x.c +++ b/board/xes/xpedite520x/xpedite520x.c @@ -70,11 +70,13 @@ int board_early_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_board_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/xes/xpedite537x/Kconfig b/board/xes/xpedite537x/Kconfig new file mode 100644 index 0000000000..35b3917a6d --- /dev/null +++ b/board/xes/xpedite537x/Kconfig @@ -0,0 +1,12 @@ +if TARGET_XPEDITE537X + +config SYS_BOARD + default "xpedite537x" + +config SYS_VENDOR + default "xes" + +config SYS_CONFIG_NAME + default "xpedite537x" + +endif diff --git a/board/xes/xpedite537x/MAINTAINERS b/board/xes/xpedite537x/MAINTAINERS new file mode 100644 index 0000000000..b6123acc0f --- /dev/null +++ b/board/xes/xpedite537x/MAINTAINERS @@ -0,0 +1,6 @@ +XPEDITE537X BOARD +M: Peter Tyser +S: Maintained +F: board/xes/xpedite537x/ +F: include/configs/xpedite537x.h +F: configs/xpedite537x_defconfig diff --git a/board/xes/xpedite537x/Makefile b/board/xes/xpedite537x/Makefile index 64f996f5a9..2dca0d7517 100644 --- a/board/xes/xpedite537x/Makefile +++ b/board/xes/xpedite537x/Makefile @@ -7,27 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += xpedite537x.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c index 0daa189103..56b5a187d8 100644 --- a/board/xes/xpedite537x/ddr.c +++ b/board/xes/xpedite537x/ddr.c @@ -2,14 +2,14 @@ * Copyright 2008 Extreme Engineering Solutions, Inc. * Copyright 2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include -#include -#include +#include +#include void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) { @@ -210,7 +210,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int datarate; get_sys_info(&sysinfo); - datarate = sysinfo.freqDDRBus / 1000 / 1000; + datarate = sysinfo.freq_ddrbus / 1000 / 1000; for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { if ((bopts[i].datarate_mhz_low <= datarate) && diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c index aaa87b268d..41419feb17 100644 --- a/board/xes/xpedite537x/xpedite537x.c +++ b/board/xes/xpedite537x/xpedite537x.c @@ -1,7 +1,7 @@ /* * Copyright 2008 Extreme Engineering Solutions, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -72,11 +72,13 @@ int board_early_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_board_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/xes/xpedite550x/Kconfig b/board/xes/xpedite550x/Kconfig new file mode 100644 index 0000000000..1b00137a48 --- /dev/null +++ b/board/xes/xpedite550x/Kconfig @@ -0,0 +1,12 @@ +if TARGET_XPEDITE550X + +config SYS_BOARD + default "xpedite550x" + +config SYS_VENDOR + default "xes" + +config SYS_CONFIG_NAME + default "xpedite550x" + +endif diff --git a/board/xes/xpedite550x/MAINTAINERS b/board/xes/xpedite550x/MAINTAINERS new file mode 100644 index 0000000000..017f368757 --- /dev/null +++ b/board/xes/xpedite550x/MAINTAINERS @@ -0,0 +1,6 @@ +XPEDITE550X BOARD +M: Peter Tyser +S: Maintained +F: board/xes/xpedite550x/ +F: include/configs/xpedite550x.h +F: configs/xpedite550x_defconfig diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile index c9b2deaf59..1a3fe7635d 100644 --- a/board/xes/xpedite550x/Makefile +++ b/board/xes/xpedite550x/Makefile @@ -4,27 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += xpedite550x.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 993ae800f3..0c0605e3a9 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -2,14 +2,14 @@ * Copyright 2010 Extreme Engineering Solutions, Inc. * Copyright 2007-2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include -#include -#include +#include +#include void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address) { @@ -108,7 +108,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; - popts->twoT_en = 0; + popts->twot_en = 0; break; } pbsp++; diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c index 161dc2d90a..1f05150d0f 100644 --- a/board/xes/xpedite550x/xpedite550x.c +++ b/board/xes/xpedite550x/xpedite550x.c @@ -1,7 +1,7 @@ /* * Copyright 2010 Extreme Engineering Solutions, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -72,11 +72,13 @@ int board_early_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_board_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig new file mode 100644 index 0000000000..461d7dce2c --- /dev/null +++ b/board/xilinx/microblaze-generic/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MICROBLAZE_GENERIC + +config SYS_BOARD + default "microblaze-generic" + +config SYS_VENDOR + default "xilinx" + +config SYS_CONFIG_NAME + default "microblaze-generic" + +endif diff --git a/board/xilinx/microblaze-generic/MAINTAINERS b/board/xilinx/microblaze-generic/MAINTAINERS new file mode 100644 index 0000000000..6796d4d51a --- /dev/null +++ b/board/xilinx/microblaze-generic/MAINTAINERS @@ -0,0 +1,6 @@ +MICROBLAZE-GENERIC BOARD +M: Michal Simek +S: Maintained +F: board/xilinx/microblaze-generic/ +F: include/configs/microblaze-generic.h +F: configs/microblaze-generic_defconfig diff --git a/board/xilinx/microblaze-generic/Makefile b/board/xilinx/microblaze-generic/Makefile index 6a25ce6c18..22c8bef117 100644 --- a/board/xilinx/microblaze-generic/Makefile +++ b/board/xilinx/microblaze-generic/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = microblaze-generic.o diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index be7154ea14..42a8d0c400 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -3,7 +3,7 @@ * * Michal SIMEK * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* This is a board specific file. It's OK to include board specific diff --git a/board/xilinx/ml507/.gitignore b/board/xilinx/ml507/.gitignore deleted file mode 100644 index f6418a0c50..0000000000 --- a/board/xilinx/ml507/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/config.tmp diff --git a/board/xilinx/ml507/Kconfig b/board/xilinx/ml507/Kconfig new file mode 100644 index 0000000000..d580a7beaf --- /dev/null +++ b/board/xilinx/ml507/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ML507 + +config SYS_BOARD + default "ml507" + +config SYS_VENDOR + default "xilinx" + +config SYS_CONFIG_NAME + default "ml507" + +endif diff --git a/board/xilinx/ml507/MAINTAINERS b/board/xilinx/ml507/MAINTAINERS new file mode 100644 index 0000000000..8b40f44500 --- /dev/null +++ b/board/xilinx/ml507/MAINTAINERS @@ -0,0 +1,7 @@ +ML507 BOARD +M: Ricardo Ribalda +S: Maintained +F: board/xilinx/ml507/ +F: include/configs/ml507.h +F: configs/ml507_defconfig +F: configs/ml507_flash_defconfig diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile index 51b777c234..9a3809f3c0 100644 --- a/board/xilinx/ml507/Makefile +++ b/board/xilinx/ml507/Makefile @@ -6,6 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -COBJS += $(BOARD).o +obj-y += ml507.o -include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile +include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/xilinx/ppc405-generic/.gitignore b/board/xilinx/ppc405-generic/.gitignore deleted file mode 100644 index b644f59941..0000000000 --- a/board/xilinx/ppc405-generic/.gitignore +++ /dev/null @@ -1 +0,0 @@ -config.tmp diff --git a/board/xilinx/ppc405-generic/Kconfig b/board/xilinx/ppc405-generic/Kconfig new file mode 100644 index 0000000000..dfbc07b425 --- /dev/null +++ b/board/xilinx/ppc405-generic/Kconfig @@ -0,0 +1,12 @@ +if TARGET_XILINX_PPC405_GENERIC + +config SYS_BOARD + default "ppc405-generic" + +config SYS_VENDOR + default "xilinx" + +config SYS_CONFIG_NAME + default "xilinx-ppc405-generic" + +endif diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS new file mode 100644 index 0000000000..2b0c98dc8b --- /dev/null +++ b/board/xilinx/ppc405-generic/MAINTAINERS @@ -0,0 +1,7 @@ +PPC405-GENERIC BOARD +M: Ricardo Ribalda +S: Maintained +F: board/xilinx/ppc405-generic/ +F: include/configs/xilinx-ppc405-generic.h +F: configs/xilinx-ppc405-generic_defconfig +F: configs/xilinx-ppc405-generic_flash_defconfig diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile index cc161ae39d..c9da870657 100644 --- a/board/xilinx/ppc405-generic/Makefile +++ b/board/xilinx/ppc405-generic/Makefile @@ -9,27 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../xilinx/ppc405-generic) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o diff --git a/board/xilinx/ppc440-generic/.gitignore b/board/xilinx/ppc440-generic/.gitignore deleted file mode 100644 index f6418a0c50..0000000000 --- a/board/xilinx/ppc440-generic/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/config.tmp diff --git a/board/xilinx/ppc440-generic/Kconfig b/board/xilinx/ppc440-generic/Kconfig new file mode 100644 index 0000000000..d40783a28f --- /dev/null +++ b/board/xilinx/ppc440-generic/Kconfig @@ -0,0 +1,12 @@ +if TARGET_XILINX_PPC440_GENERIC + +config SYS_BOARD + default "ppc440-generic" + +config SYS_VENDOR + default "xilinx" + +config SYS_CONFIG_NAME + default "xilinx-ppc440-generic" + +endif diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS new file mode 100644 index 0000000000..2d0b11af91 --- /dev/null +++ b/board/xilinx/ppc440-generic/MAINTAINERS @@ -0,0 +1,7 @@ +PPC440-GENERIC BOARD +M: Ricardo Ribalda +S: Maintained +F: board/xilinx/ppc440-generic/ +F: include/configs/xilinx-ppc440-generic.h +F: configs/xilinx-ppc440-generic_defconfig +F: configs/xilinx-ppc440-generic_flash_defconfig diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index 597afdee67..0acd95d6e4 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -9,28 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../xilinx/ppc440-generic) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o -SOBJS += ../../xilinx/ppc440-generic/init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o +extra-y += ../../xilinx/ppc440-generic/init.o diff --git a/board/xilinx/zynq/.gitignore b/board/xilinx/zynq/.gitignore new file mode 100644 index 0000000000..7c36bc963f --- /dev/null +++ b/board/xilinx/zynq/.gitignore @@ -0,0 +1,2 @@ +ps7_init.[ch] +ps7_init_gpl.[ch] diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS new file mode 100644 index 0000000000..382e921e70 --- /dev/null +++ b/board/xilinx/zynq/MAINTAINERS @@ -0,0 +1,7 @@ +ZYNQ BOARD +M: Michal Simek +M: Jagannadha Sutradharudu Teki +S: Maintained +F: board/xilinx/zynq/ +F: include/configs/zynq*.h +F: configs/zynq_*_defconfig diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 98a5046f45..3b1eb4f74a 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -5,31 +5,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-y := board.o -LIB = $(obj)lib$(BOARD).o +# Please copy ps7_init_gpl.c/h from hw project to this directory +obj-$(CONFIG_SPL_BUILD) += \ + $(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c), ps7_init_gpl.o, \ + $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o legacy.o)) -COBJS-y := board.o - -COBJS := $(sort $(COBJS-y)) - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +# Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes +CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 4bb140e29e..738c31c6ee 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -1,10 +1,13 @@ /* * (C) Copyright 2012 Michal Simek * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include +#include #include #include #include @@ -12,19 +15,24 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_FPGA -Xilinx_desc fpga; +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static xilinx_desc fpga; /* It can be done differently */ -Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); +static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); +static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) { -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) u32 idcode; idcode = zynq_slcr_get_idcode(); @@ -33,21 +41,29 @@ int board_init(void) case XILINX_ZYNQ_7010: fpga = fpga010; break; + case XILINX_ZYNQ_7015: + fpga = fpga015; + break; case XILINX_ZYNQ_7020: fpga = fpga020; break; case XILINX_ZYNQ_7030: fpga = fpga030; break; + case XILINX_ZYNQ_7035: + fpga = fpga035; + break; case XILINX_ZYNQ_7045: fpga = fpga045; break; + case XILINX_ZYNQ_7100: + fpga = fpga100; + break; } #endif - icache_enable(); - -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif @@ -55,25 +71,69 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { + case ZYNQ_BM_NOR: + setenv("modeboot", "norboot"); + break; + case ZYNQ_BM_SD: + setenv("modeboot", "sdboot"); + break; + case ZYNQ_BM_JTAG: + setenv("modeboot", "jtagboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board:\tXilinx Zynq\n"); + return 0; +} +#endif -#ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { u32 ret = 0; +#ifdef CONFIG_XILINX_AXIEMAC + ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, + XILINX_AXIDMA_BASEADDR); +#endif +#ifdef CONFIG_XILINX_EMACLITE + u32 txpp = 0; + u32 rxpp = 0; +# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + txpp = 1; +# endif +# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG + rxpp = 1; +# endif + ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, + txpp, rxpp); +#endif + #if defined(CONFIG_ZYNQ_GEM) # if defined(CONFIG_ZYNQ_GEM0) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, - CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); + CONFIG_ZYNQ_GEM_PHY_ADDR0, + CONFIG_ZYNQ_GEM_EMIO0); # endif # if defined(CONFIG_ZYNQ_GEM1) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, - CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); + CONFIG_ZYNQ_GEM_PHY_ADDR1, + CONFIG_ZYNQ_GEM_EMIO1); # endif #endif return ret; } -#endif #ifdef CONFIG_CMD_MMC int board_mmc_init(bd_t *bd) @@ -94,7 +154,28 @@ int board_mmc_init(bd_t *bd) int dram_init(void) { +#ifdef CONFIG_OF_CONTROL + int node; + fdt_addr_t addr; + fdt_size_t size; + const void *blob = gd->fdt_blob; + + node = fdt_node_offset_by_prop_value(blob, -1, "device_type", + "memory", 7); + if (node == -FDT_ERR_NOTFOUND) { + debug("ZYNQ DRAM: Can't get memory node\n"); + return -1; + } + addr = fdtdec_get_addr_size(blob, node, "reg", &size); + if (addr == FDT_ADDR_T_NONE || size == 0) { + debug("ZYNQ DRAM: Can't get base address or size\n"); + return -1; + } + gd->ram_size = size; +#else gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#endif + zynq_ddrc_init(); return 0; } diff --git a/board/xilinx/zynq/legacy.c b/board/xilinx/zynq/legacy.c new file mode 100644 index 0000000000..4ae913eefe --- /dev/null +++ b/board/xilinx/zynq/legacy.c @@ -0,0 +1,2 @@ + +#warning usage of ps7_init files is deprecated please use ps7_init_gpl diff --git a/board/xilinx/zynq/xil_io.h b/board/xilinx/zynq/xil_io.h new file mode 100644 index 0000000000..1eccf8d91d --- /dev/null +++ b/board/xilinx/zynq/xil_io.h @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H + +/* + * This empty file is here because ps7_init_gpl.c exported by hw project + * has #include "xil_io.h" line. + */ + +#endif /* XIL_IO_H */ diff --git a/board/zeus/Kconfig b/board/zeus/Kconfig new file mode 100644 index 0000000000..67796508f3 --- /dev/null +++ b/board/zeus/Kconfig @@ -0,0 +1,9 @@ +if TARGET_ZEUS + +config SYS_BOARD + default "zeus" + +config SYS_CONFIG_NAME + default "zeus" + +endif diff --git a/board/zeus/MAINTAINERS b/board/zeus/MAINTAINERS new file mode 100644 index 0000000000..3118710cd4 --- /dev/null +++ b/board/zeus/MAINTAINERS @@ -0,0 +1,6 @@ +ZEUS BOARD +M: Stefan Roese +S: Maintained +F: board/zeus/ +F: include/configs/zeus.h +F: configs/zeus_defconfig diff --git a/board/zeus/Makefile b/board/zeus/Makefile index 8d133e24a0..aa3658a370 100644 --- a/board/zeus/Makefile +++ b/board/zeus/Makefile @@ -5,25 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o update.o -SOBJS = - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y = zeus.o update.o diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig new file mode 100644 index 0000000000..c6635040a3 --- /dev/null +++ b/board/zipitz2/Kconfig @@ -0,0 +1,9 @@ +if TARGET_ZIPITZ2 + +config SYS_BOARD + default "zipitz2" + +config SYS_CONFIG_NAME + default "zipitz2" + +endif diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS new file mode 100644 index 0000000000..55b0f6406c --- /dev/null +++ b/board/zipitz2/MAINTAINERS @@ -0,0 +1,6 @@ +ZIPITZ2 BOARD +M: Marek Vasut +S: Maintained +F: board/zipitz2/ +F: include/configs/zipitz2.h +F: configs/zipitz2_defconfig diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile index eed343b97a..855f6bcda8 100644 --- a/board/zipitz2/Makefile +++ b/board/zipitz2/Makefile @@ -1,4 +1,3 @@ - # # Copyright (C) 2009 # Marek Vasut @@ -8,23 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := zipitz2.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := zipitz2.o diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile deleted file mode 100644 index c573be952c..0000000000 --- a/board/zpc1900/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c deleted file mode 100644 index fed4934afd..0000000000 --- a/board/zpc1900/zpc1900.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003-2005 Arabella Software Ltd. - * Yuli Barcohen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE -void *nvram_read(void *dest, long src, size_t count) -{ - return memcpy(dest, (const void *)src, count); -} - -void nvram_write(long dest, const void *src, size_t count) -{ - vu_char *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555); - vu_char *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA); - vu_char *d = (vu_char *)dest; - const uchar *s = (const uchar *)src; - - /* Unprotect the EEPROM */ - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0x80; - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0x20; - udelay(10000); - - /* Write the data to the EEPROM */ - while (count--) { - *d++ = *s++; - while (*(d - 1) != *(s - 1)) - /* wait */; - } - - /* Protect the EEPROM */ - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0xA0; - udelay(10000); -} -#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */ - -phys_size_t initdram(int board_type) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr; - uchar c = 0xFF; - long int msize = CONFIG_SYS_SDRAM_SIZE; - int i; - - if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ - immap->im_clkrst.car_sccr |= SCCR_PCI_MODE; - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; - } - -#ifndef CONFIG_SYS_RAMBOOT - immap->im_siu_conf.sc_ppc_acr = 0x03; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifdef CONFIG_SYS_LSDRAM_BASE - /* - Initialise local bus SDRAM only if the pins - are configured as local bus pins and not as PCI. - */ - if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { - memctl->memc_lsrt = CONFIG_SYS_LSRT; - memctl->memc_or4 = CONFIG_SYS_LSDRAM_OR; - memctl->memc_br4 = CONFIG_SYS_LSDRAM_BR; - ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA; - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW; - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN; - } -#endif /* CONFIG_SYS_LSDRAM_BASE */ - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or2 = CONFIG_SYS_PSDRAM_OR; - memctl->memc_br2 = CONFIG_SYS_PSDRAM_BR; - /* - * The mode data for Mode Register Write command must appear on - * the address lines during a mode-set cycle. It is driven by - * the memory controller, in single PowerQUICC II mode, - * according to PSDMR[CL] and PSDMR[BL] fields. In - * 60x-compatible mode, software must drive the correct value on - * the address lines. BL=0 because for 64-bit port size burst - * length must be 4. - */ - ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE | - ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10); - memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* CONFIG_SYS_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40); - return 0; -} diff --git a/boards.cfg b/boards.cfg deleted file mode 100644 index 3aeec25fe2..0000000000 --- a/boards.cfg +++ /dev/null @@ -1,1237 +0,0 @@ -# -# List of boards -# -# Syntax: -# white-space separated list of entries; -# each entry has the fields documented below. -# -# Unused fields can be specified as "-", or omitted if they -# are the last field on the line. -# -# Lines starting with '#' are comments. -# Blank lines are ignored. -# -# The CPU field takes the form: -# cpu[:spl_cpu] -# If spl_cpu is specified the make variable CPU will be set to this -# during the SPL build. -# -# The options field takes the form: -# [:comma separated config options] -# Each config option has the form (value defaults to "1"): -# option[=value] -# So if you have: -# FOO:HAS_BAR,BAZ=64 -# The file include/configs/FOO.h will be used, and these defines created: -# #define CONFIG_HAS_BAR 1 -# #define CONFIG_BAZ 64 -# -# The list should be ordered according to the following fields, -# from most to least significant: -# -# ARCH, CPU, SoC, Vendor, Target -# -# To keep the list sorted, use something like -# :.,$! sort -bdf -k2,2 -k3,3 -k6,6 -k5,5 -k1,1 -# -# To reformat the list, use something like -# :.,$! column -t -# -# Target ARCH CPU Board name Vendor SoC Options -########################################################################################################### - -integratorcp_cm1136 arm arm1136 integrator armltd - integratorcp:CM1136 -imx31_phycore arm arm1136 - - mx31 -imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET -qong arm arm1136 - davedenx mx31 -mx31ads arm arm1136 - freescale mx31 -mx31pdk arm arm1136 - freescale mx31 -tt01 arm arm1136 - hale mx31 -imx31_litekit arm arm1136 - logicpd mx31 -flea3 arm arm1136 - CarMediaLab mx35 -mx35pdk arm arm1136 - freescale mx35 -woodburn arm arm1136 - - mx35 -woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg -tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x -rpi_b arm arm1176 rpi_b raspberrypi bcm2835 -integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T -integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T -integratorcp_cm920t arm arm920t integrator armltd - integratorcp:CM920T -a320evb arm arm920t - faraday a320 -at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek -at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT -eb_cpux9k2 arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2 -eb_cpux9k2_ram arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2:RAMBOOT -cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91 -cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT -mx1ads arm arm920t - - imx -scb9328 arm arm920t - - imx -cm4008 arm arm920t - - ks8695 -cm41xx arm arm920t - - ks8695 -mini2440 arm arm920t mini2440 friendlyarm s3c24x0 -VCMA9 arm arm920t vcma9 mpl s3c24x0 -smdk2410 arm arm920t - samsung s3c24x0 -omap1510inn arm arm925t - ti -integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_S -integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S -aspenite arm arm926ejs - Marvell armada100 -gplugd arm arm926ejs - Marvell armada100 -afeb9260 arm arm926ejs - - at91 -at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 -at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 -at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH -at91sam9261ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 -at91sam9261ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 -at91sam9261ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH -at91sam9263ek_dataflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH -at91sam9263ek_dataflash_cs0 arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH -at91sam9263ek_nandflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH -at91sam9263ek_norflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH -at91sam9263ek_norflash_boot arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH -at91sam9g10ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 -at91sam9g10ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 -at91sam9g10ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH -at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 -at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 -at91sam9g20ek_mmc arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_MMC -at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH -at91sam9g20ek_2mmc_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH -at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH -at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH -at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH -at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH -at91sam9x5ek_dataflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH -at91sam9x5ek_spiflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH -at91sam9x5ek_mmc arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC -at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 -at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 -at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH -at91sam9n12ek_nandflash arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH -at91sam9n12ek_spiflash arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH -at91sam9n12ek_mmc arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC -snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 -snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 -vl_ma2sc arm arm926ejs vl_ma2sc BuS at91 -vl_ma2sc_ram arm arm926ejs vl_ma2sc BuS at91 vl_ma2sc:RAMLOAD -sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM -sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH -tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM -tny_a9260_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH -tny_a9g20_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_EEPROM -tny_a9g20_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH -ethernut5 arm arm926ejs ethernut5 egnite at91 ethernut5:AT91SAM9XE -top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000 -top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000 -meesc arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_NANDFLASH -meesc_dataflash arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_DATAFLASH -otc570 arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_NANDFLASH -otc570_dataflash arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_DATAFLASH -cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 -cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M -cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT -cpu9260_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M,NANDBOOT -cpu9G20 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20 -cpu9G20_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M -cpu9G20_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,NANDBOOT -cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT -pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261 -pm9263 arm arm926ejs pm9263 ronetix at91 pm9263:AT91SAM9263 -pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45 -portuxg20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20,PORTUXG20 -stamp9g20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20 -cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx -da830evm arm arm926ejs da8xxevm davinci davinci -da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 -da850evm arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH -da850evm_direct_nor arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT -davinci_dm355evm arm arm926ejs dm355evm davinci davinci -davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci -davinci_dm365evm arm arm926ejs dm365evm davinci davinci -davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci davinci_dm6467evm:REFCLK_FREQ=27000000 -davinci_dm6467Tevm arm arm926ejs dm6467evm davinci davinci davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 -davinci_dvevm arm arm926ejs dvevm davinci davinci -davinci_schmoogie arm arm926ejs schmoogie davinci davinci -davinci_sffsdr arm arm926ejs sffsdr davinci davinci -davinci_sonata arm arm926ejs sonata davinci davinci -ea20 arm arm926ejs ea20 davinci davinci -hawkboard arm arm926ejs da8xxevm davinci davinci -hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT -enbw_cmc arm arm926ejs enbw_cmc enbw davinci -calimain arm arm926ejs calimain omicron davinci -pogo_e02 arm arm926ejs - cloudengines kirkwood -dns325 arm arm926ejs - d-link kirkwood -iconnect arm arm926ejs - iomega kirkwood -lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 -lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL -km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI -kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA -kmsuv31 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_SUV31 -mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN -kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN -portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 -d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2 -inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 -net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 -netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2 -netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 -netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2 -netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 -wireless_space arm arm926ejs wireless_space LaCie kirkwood -dreamplug arm arm926ejs - Marvell kirkwood -guruplug arm arm926ejs - Marvell kirkwood -mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood -openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE -openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT -openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE -rd6281a arm arm926ejs - Marvell kirkwood -sheevaplug arm arm926ejs - Marvell kirkwood -ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood -dockstar arm arm926ejs - Seagate kirkwood -goflexhome arm arm926ejs - Seagate kirkwood -tk71 arm arm926ejs tk71 karo kirkwood -devkit3250 arm arm926ejs devkit3250 timll lpc32xx -jadecpu arm arm926ejs jadecpu syteco mb86r0x -mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg -tx25 arm arm926ejs tx25 karo mx25 -tx28-40x1 arm arm926ejs tx28 karo mxs tx28:TX28,SDRAM_SIZE=SZ_128M -tx28-40x1_noenv arm arm926ejs tx28 karo mxs tx28:TX28,SDRAM_SIZE=SZ_128M,ENV_IS_NOWHERE -tx28-40x2 arm arm926ejs tx28 karo mxs tx28:TX28,SDRAM_SIZE=SZ_256M -tx28-40x2_noenv arm arm926ejs tx28 karo mxs tx28:TX28,SDRAM_SIZE=SZ_256M,ENV_IS_NOWHERE -tx28-40x3 arm arm926ejs tx28 karo mxs tx28:TX28,SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048 -tx28-40x3_noenv arm arm926ejs tx28 karo mxs tx28:TX28,SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048,ENV_IS_NOWHERE -tx28-41x0 arm arm926ejs tx28 karo mxs tx28:TX28_S,SDRAM_SIZE=SZ_64M -tx28-41x0_noenv arm arm926ejs tx28 karo mxs tx28:TX28_S,SDRAM_SIZE=SZ_64M,ENV_IS_NOWHERE -zmx25 arm arm926ejs zmx25 syteco mx25 -imx27lite arm arm926ejs imx27lite logicpd mx27 -magnesium arm arm926ejs imx27lite logicpd mx27 -mx23_olinuxino arm arm926ejs mx23_olinuxino olimex mxs mx23_olinuxino -apx4devkit arm arm926ejs apx4devkit bluegiga mxs apx4devkit -mx23evk arm arm926ejs mx23evk freescale mxs mx23evk -m28evk arm arm926ejs m28evk denx mxs m28evk -mx28evk arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_MMC -mx28evk_nand arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_NAND -sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs -nhk8815 arm arm926ejs nhk8815 st nomadik -nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND -omap5912osk arm arm926ejs - ti omap -omap730p2 arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT -omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2:CS0_BOOT -omap730p2_cs3boot arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT -edminiv2 arm arm926ejs - LaCie orion5x -dkb arm arm926ejs - Marvell pantheon -spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300 -spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand -spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty -spear300_usbtty_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty,nand -spear310 arm arm926ejs spear310 spear spear spear3xx_evb:spear310 -spear310_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,FLASH_PNOR -spear310_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,nand -spear310_usbtty arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty -spear310_usbtty_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,FLASH_PNOR -spear310_usbtty_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,nand -spear320 arm arm926ejs spear320 spear spear spear3xx_evb:spear320 -spear320_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,FLASH_PNOR -spear320_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,nand -spear320_usbtty arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty -spear320_usbtty_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,FLASH_PNOR -spear320_usbtty_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,nand -spear600 arm arm926ejs spear600 spear spear spear6xx_evb:spear600 -spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand -spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty -spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand -x600 arm arm926ejs - spear spear x600 -versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB -versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB -versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB -integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES -integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES -vexpress_ca15_tc2 arm armv7 vexpress armltd -vexpress_ca5x2 arm armv7 vexpress armltd -vexpress_ca9x4 arm armv7 vexpress armltd -am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 -am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT -am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 -am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 -am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4 -am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 -am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 -am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT -ti814x_evm arm armv7 ti814x ti am33xx -pcm051 arm armv7 pcm051 phytec am33xx pcm051 -sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC -sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH -sama5d3xek_spiflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH -tx48 arm armv7 tx48 karo am33xx tx48:SYS_MPU_CLK=720,SYS_DDR_CLK=400 -highbank arm armv7 highbank - highbank -m53evk arm armv7 m53evk denx mx5 m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg -mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg -mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg -mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg -mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg -mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg -ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg -cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q -tx51-8xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1 -tx51-8xx1_2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2 -tx53-x030 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1 -tx53-x130 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1,SYS_LVDS_IF -tx53-x131 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_LVDS_IF -tx53-1232 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_SDRAM_SIZE=SZ_2G -tx6q-10x0 arm armv7 tx6 karo mx6 tx6:MX6Q -tx6q-10x0_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG -tx6q-10x0_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE -tx6q-1020 arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_IN_MMC,MMC_BOOT_SIZE=4096,NO_NAND,TX6_REV=0x2 -tx6q-1020_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_IN_MMC,MMC_BOOT_SIZE=4096,NO_NAND,MFG,TX6_REV=0x2 -tx6q-1020_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE,MMC_BOOT_SIZE=4096,NO_NAND,TX6_REV=0x2 -tx6q-1033 arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_IN_MMC,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 -tx6q-1033_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_IN_MMC,MFG,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 -tx6q-1033_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 -tx6q-11x0 arm armv7 tx6 karo mx6 tx6:MX6Q,SYS_LVDS_IF -tx6q-11x0_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG,SYS_LVDS_IF -tx6q-11x0_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE,SYS_LVDS_IF -tx6s-8034 arm armv7 tx6 karo mx6 tx6:MX6S,SYS_SDRAM_BUS_WIDTH=16,TX6_REV=0x3 -tx6s-8034_mfg arm armv7 tx6 karo mx6 tx6:MX6S,MFG,SYS_SDRAM_BUS_WIDTH=16,TX6_REV=0x3 -tx6s-8034_noenv arm armv7 tx6 karo mx6 tx6:MX6S,ENV_IS_NOWHERE,SYS_SDRAM_BUS_WIDTH=16,TX6_REV=0x3 -tx6s-8035 arm armv7 tx6 karo mx6 tx6:MX6S,ENV_IS_IN_MMC,MMC_BOOT_SIZE=1024,NO_NAND,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x3 -tx6s-8035_mfg arm armv7 tx6 karo mx6 tx6:MX6S,ENV_IS_IN_MMC,MFG,MMC_BOOT_SIZE=1024,NO_NAND,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x3 -tx6s-8035_noenv arm armv7 tx6 karo mx6 tx6:MX6S,ENV_IS_NOWHERE,MMC_BOOT_SIZE=1024,NO_NAND,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x3 -tx6u-80x0 arm armv7 tx6 karo mx6 tx6:MX6DL -tx6u-80x0_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,MFG -tx6u-80x0_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE -tx6u-8011 arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x1 -tx6u-8011_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,MFG,TX6_REV=0x1 -tx6u-8011_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,ENV_IS_NOWHERE,TX6_REV=0x1 -tx6u-8012 arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_NAND_BLOCKS=2048,TX6_REV=0x1 -tx6u-8012_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_NAND_BLOCKS=2048,MFG,TX6_REV=0x1 -tx6u-8012_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_NAND_BLOCKS=2048,ENV_IS_NOWHERE,TX6_REV=0x1 -tx6u-81x0 arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_LVDS_IF -tx6u-81x0_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,MFG,SYS_LVDS_IF -tx6u-81x0_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE,SYS_LVDS_IF -tx6u-8111 arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF,TX6_REV=0x1 -tx6u-8111_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,MFG,SYS_LVDS_IF,TX6_REV=0x1 -tx6u-8111_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,ENV_IS_NOWHERE,SYS_LVDS_IF,TX6_REV=0x1 -tx6u-8033 arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_IN_MMC,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 -tx6u-8033_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_IN_MMC,MFG,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 -tx6u-8033_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 -mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg -mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q -mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg -mx6dlsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL -mx6qsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q -mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL -titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg -vf610twr arm armv7 vf610twr freescale vf610 vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg -eco5pk arm armv7 eco5pk 8dtech omap3 -nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 -nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 -nitrogen6q arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 -nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 -nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 -nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 -wandboard_dl arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 -wandboard_quad arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 -wandboard_solo arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 -omap3_overo arm armv7 overo - omap3 -omap3_pandora arm armv7 pandora - omap3 -dig297 arm armv7 dig297 comelit omap3 -cm_t35 arm armv7 cm_t35 compulab omap3 -igep0020 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND -igep0020_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND -igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND -igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND -igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND -igep0033 arm armv7 igep0033 isee am33xx -am3517_evm arm armv7 am3517evm logicpd omap3 -mt_ventoux arm armv7 mt_ventoux teejet omap3 -omap3_zoom1 arm armv7 zoom1 logicpd omap3 -omap3_zoom2 arm armv7 zoom2 logicpd omap3 -omap3_logic arm armv7 omap3som logicpd omap3 -omap3_mvblx arm armv7 mvblx matrix_vision omap3 -am3517_crane arm armv7 am3517crane ti omap3 -omap3_beagle arm armv7 beagle ti omap3 -omap3_evm arm armv7 evm ti omap3 -omap3_evm_quick_mmc arm armv7 evm ti omap3 -omap3_evm_quick_nand arm armv7 evm ti omap3 -omap3_sdp3430 arm armv7 sdp3430 ti omap3 -devkit8000 arm armv7 devkit8000 timll omap3 -mcx arm armv7 mcx htkw omap3 -tricorder arm armv7 tricorder corscience omap3 -twister arm armv7 twister technexion omap3 -nokia_rx51 arm armv7 rx51 nokia omap3 -omap4_panda arm armv7 panda ti omap4 -omap4_sdp4430 arm armv7 sdp4430 ti omap4 -omap5_uevm arm armv7 omap5_uevm ti omap5 -dra7xx_evm arm armv7 dra7xx ti omap5 -s5p_goni arm armv7 goni samsung s5pc1xx -smdkc100 arm armv7 smdkc100 samsung s5pc1xx -origen arm armv7 origen samsung exynos -s5pc210_universal arm armv7 universal_c210 samsung exynos -snow arm armv7 smdk5250 samsung exynos -smdk5250 arm armv7 smdk5250 samsung exynos -smdkv310 arm armv7 smdkv310 samsung exynos -trats arm armv7 trats samsung exynos -harmony arm armv7:arm720t harmony nvidia tegra20 -seaboard arm armv7:arm720t seaboard nvidia tegra20 -ventana arm armv7:arm720t ventana nvidia tegra20 -whistler arm armv7:arm720t whistler nvidia tegra20 -cardhu arm armv7:arm720t cardhu nvidia tegra30 -beaver arm armv7:arm720t beaver nvidia tegra30 -dalmore arm armv7:arm720t dalmore nvidia tegra114 -colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20 -u8500_href arm armv7 u8500 st-ericsson u8500 -snowball arm armv7 snowball st-ericsson u8500 -kzm9g arm armv7 kzm9g kmc rmobile -armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile -zynq arm armv7 zynq xilinx zynq -zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC -socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga -actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 -actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB -actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 -actux1_8_32 arm ixp actux1 - - actux1:FLASH1X8,RAM_32MB -actux2 arm ixp -actux3 arm ixp -actux4 arm ixp -dvlhost arm ixp -pdnb3 arm ixp pdnb3 prodrive -scpu arm ixp pdnb3 prodrive - pdnb3:SCPU -balloon3 arm pxa -h2200 arm pxa -lp8x4x arm pxa lp8x4x icpdas -lubbock arm pxa -palmld arm pxa -palmtc arm pxa -palmtreo680 arm pxa -polaris arm pxa trizepsiv - - trizepsiv:POLARIS -pxa255_idp arm pxa -trizepsiv arm pxa -vpac270_nor_128 arm pxa vpac270 - - vpac270:NOR,RAM_128M -vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M -vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M -xaeniax arm pxa -zipitz2 arm pxa -colibri_pxa270 arm pxa - toradex -jornada arm sa1100 -plutux arm armv7:arm720t plutux avionic-design tegra20 -medcom-wide arm armv7:arm720t medcom-wide avionic-design tegra20 -tec arm armv7:arm720t tec avionic-design tegra20 -paz00 arm armv7:arm720t paz00 compal tegra20 -trimslice arm armv7:arm720t trimslice compulab tegra20 -atngw100 avr32 at32ap - atmel at32ap700x -atngw100mkii avr32 at32ap - atmel at32ap700x -atstk1002 avr32 at32ap atstk1000 atmel at32ap700x -atstk1003 avr32 at32ap atstk1000 atmel at32ap700x -atstk1004 avr32 at32ap atstk1000 atmel at32ap700x -atstk1006 avr32 at32ap atstk1000 atmel at32ap700x -favr-32-ezkit avr32 at32ap - earthlcd at32ap700x -grasshopper avr32 at32ap - in-circuit at32ap700x -mimc200 avr32 at32ap - mimc at32ap700x -hammerhead avr32 at32ap - miromico at32ap700x -bct-brettl2 blackfin blackfin -bf506f-ezkit blackfin blackfin -bf518f-ezbrd blackfin blackfin -bf525-ucr2 blackfin blackfin -bf526-ezbrd blackfin blackfin -bf527-ad7160-eval blackfin blackfin -bf527-ezkit blackfin blackfin -bf527-ezkit-v2 blackfin blackfin bf527-ezkit - - bf527-ezkit:BF527_EZKIT_REV_2_1 -bf527-sdp blackfin blackfin -bf533-ezkit blackfin blackfin -bf533-stamp blackfin blackfin -bf537-minotaur blackfin blackfin -bf537-pnav blackfin blackfin -bf537-srv1 blackfin blackfin -bf537-stamp blackfin blackfin -bf538f-ezkit blackfin blackfin -bf548-ezkit blackfin blackfin -bf561-acvilon blackfin blackfin -bf561-ezkit blackfin blackfin -bf609-ezkit blackfin blackfin -blackstamp blackfin blackfin -blackvme blackfin blackfin -br4 blackfin blackfin -cm-bf527 blackfin blackfin -cm-bf533 blackfin blackfin -cm-bf537e blackfin blackfin -cm-bf537u blackfin blackfin -cm-bf548 blackfin blackfin -cm-bf561 blackfin blackfin -dnp5370 blackfin blackfin -ibf-dsp561 blackfin blackfin -ip04 blackfin blackfin -pr1 blackfin blackfin -tcm-bf518 blackfin blackfin -tcm-bf537 blackfin blackfin -M52277EVB m68k mcf5227x m52277evb freescale - M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 -M52277EVB_stmicro m68k mcf5227x m52277evb freescale - M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 -M5235EVB m68k mcf523x m5235evb freescale - M5235EVB:SYS_TEXT_BASE=0xFFE00000 -M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 -cobra5272 m68k mcf52x2 cobra5272 - -idmr m68k mcf52x2 -eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 -eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 -TASREG m68k mcf52x2 tasreg esd -M5208EVBE m68k mcf52x2 m5208evbe freescale -M5249EVB m68k mcf52x2 m5249evb freescale -M5253DEMO m68k mcf52x2 m5253demo freescale -M5253EVBE m68k mcf52x2 m5253evbe freescale -M5271EVB m68k mcf52x2 m5271evb freescale -M5272C3 m68k mcf52x2 m5272c3 freescale -M5275EVB m68k mcf52x2 m5275evb freescale -M5282EVB m68k mcf52x2 m5282evb freescale -astro_mcf5373l m68k mcf532x mcf5373l astro -M53017EVB m68k mcf532x m53017evb freescale -M5329AFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=0 -M5329BFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=16 -M5373EVB m68k mcf532x m5373evb freescale - M5373EVB:NANDFLASH_SIZE=16 -M54418TWR m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -M54418TWR_nand_mii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -M54418TWR_nand_rmii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -M54418TWR_nand_rmii_lowfreq m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -M54418TWR_serial_mii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -M54418TWR_serial_rmii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -M54451EVB m68k mcf5445x m54451evb freescale - M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 -M54451EVB_stmicro m68k mcf5445x m54451evb freescale - M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 -M54455EVB m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 -M54455EVB_a66 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 -M54455EVB_i66 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 -M54455EVB_intel m68k mcf5445x m54455evb freescale - M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 -M54455EVB_stm33 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 -M5475AFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 -M5475BFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 -M5475CFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL -M5475DFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL -M5475EFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL -M5475FFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 -M5475GFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 -M5485AFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 -M5485BFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 -M5485CFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL -M5485DFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL -M5485EFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL -M5485FFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 -M5485GFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 -M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO -microblaze-generic microblaze microblaze microblaze-generic xilinx -qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN -qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN -qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN -qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN -qemu_malta mips mips32 qemu-malta - - qemu-malta:MIPS32,SYS_BIG_ENDIAN -qemu_maltael mips mips32 qemu-malta - - qemu-malta:MIPS32,SYS_LITTLE_ENDIAN -vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM -vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC -vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND -vct_platinumavc_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE -vct_platinumavc_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE -vct_platinum_onenand mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_ONENAND -vct_platinum_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -vct_platinum_small mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_SMALL_IMAGE -vct_premium mips mips32 vct micronas - vct:VCT_PREMIUM -vct_premium_onenand mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND -vct_premium_onenand_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE -vct_premium_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE -dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000 -dbau1100 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1100 -dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500 -dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550 -dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN -pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000 -incaip mips mips32 incaip - incaip -incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000 -incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 -incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000 -adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101 -adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101 -adp-ag102 nds32 n1213 adp-ag102 AndesTech ag102 -nios2-generic nios2 nios2 nios2-generic altera -PCI5441 nios2 nios2 pci5441 psyent -PK1C20 nios2 nios2 pk1c20 psyent -openrisc-generic openrisc or1200 openrisc-generic openrisc - -EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260 -EVB64260_750CX powerpc 74xx_7xx evb64260 - - EVB64260 -P3G4 powerpc 74xx_7xx evb64260 -ppmc7xx powerpc 74xx_7xx -ZUMA powerpc 74xx_7xx evb64260 -ELPPC powerpc 74xx_7xx elppc eltec -CPCI750 powerpc 74xx_7xx cpci750 esd -mpc7448hpc2 powerpc 74xx_7xx mpc7448hpc2 freescale -DB64360 powerpc 74xx_7xx db64360 Marvell -DB64460 powerpc 74xx_7xx db64460 Marvell -p3m7448 powerpc 74xx_7xx p3mx prodrive - p3mx:P3M7448 -p3m750 powerpc 74xx_7xx p3mx prodrive - p3mx:P3M750 -pdm360ng powerpc mpc512x -aria powerpc mpc512x - davedenx -mecp5123 powerpc mpc512x - esd -mpc5121ads powerpc mpc512x mpc5121ads freescale -mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2 -ac14xx powerpc mpc512x ac14xx ifm -cmi_mpc5xx powerpc mpc5xx cmi -PATI powerpc mpc5xx pati mpl -a3m071 powerpc mpc5xxx a3m071 -a4m072 powerpc mpc5xxx a4m072 -a4m2k powerpc mpc5xxx a3m071 - - a3m071:A4M2K -BC3450 powerpc mpc5xxx bc3450 -canmb powerpc mpc5xxx -cm5200 powerpc mpc5xxx -galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200 -galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT -icecube_5200 powerpc mpc5xxx icecube - - IceCube -icecube_5200_DDR powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR -icecube_5200_DDR_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -icecube_5200_DDR_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -icecube_5200_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF000000 -icecube_5200_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000 -inka4x0 powerpc mpc5xxx -ipek01 powerpc mpc5xxx -jupiter powerpc mpc5xxx -Lite5200 powerpc mpc5xxx icecube - - IceCube -lite5200b powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B -lite5200b_LOWBOOT powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 -lite5200b_PM powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM -Lite5200_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF000000 -Lite5200_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000 -mcc200 powerpc mpc5xxx mcc200 - - mcc200 -mcc200_COM12 powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12 -mcc200_COM12_highboot powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 -mcc200_COM12_highboot_SDRAM powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -mcc200_COM12_SDRAM powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,MCC200_SDRAM -mcc200_highboot powerpc mpc5xxx mcc200 - - mcc200:SYS_TEXT_BASE=0xFFF00000 -mcc200_highboot_SDRAM powerpc mpc5xxx mcc200 - - mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -mcc200_SDRAM powerpc mpc5xxx mcc200 - - mcc200:MCC200_SDRAM -motionpro powerpc mpc5xxx -munices powerpc mpc5xxx -PM520 powerpc mpc5xxx pm520 -PM520_DDR powerpc mpc5xxx pm520 - - PM520:MPC5200_DDR -PM520_ROMBOOT powerpc mpc5xxx pm520 - - PM520:BOOT_ROM -PM520_ROMBOOT_DDR powerpc mpc5xxx pm520 - - PM520:MPC5200_DDR,BOOT_ROM -prs200 powerpc mpc5xxx mcc200 - - mcc200:PRS200,MCC200_SDRAM -prs200_DDR powerpc mpc5xxx mcc200 - - mcc200:PRS200 -prs200_highboot powerpc mpc5xxx mcc200 - - mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -prs200_highboot_DDR powerpc mpc5xxx mcc200 - - mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 -Total5200 powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=1 -Total5200_lowboot powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 -Total5200_Rev2 powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=2 -Total5200_Rev2_lowboot powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 -v38b powerpc mpc5xxx -EVAL5200 powerpc mpc5xxx top5200 emk - TOP5200:EVAL5200 -MINI5200 powerpc mpc5xxx top5200 emk - TOP5200:MINI5200 -TOP5200 powerpc mpc5xxx top5200 emk - TOP5200:TOP5200 -cpci5200 powerpc mpc5xxx - esd -mecp5200 powerpc mpc5xxx - esd -pf5200 powerpc mpc5xxx - esd -O2D powerpc mpc5xxx o2dnt2 ifm - o2d -O2D300 powerpc mpc5xxx o2dnt2 ifm - o2d300 -O2DNT2 powerpc mpc5xxx o2dnt2 ifm - o2dnt2 -O2DNT2_RAMBOOT powerpc mpc5xxx o2dnt2 ifm - o2dnt2:SYS_TEXT_BASE=0x00100000 -O2I powerpc mpc5xxx o2dnt2 ifm - o2i -O2MNT powerpc mpc5xxx o2dnt2 ifm - o2mnt -O2MNT_O2M110 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M110" -O2MNT_O2M112 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M112" -O2MNT_O2M113 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M113" -O3DNT powerpc mpc5xxx o2dnt2 ifm - o3dnt -digsy_mtc powerpc mpc5xxx digsy_mtc intercontrol -digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000 -digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:DIGSY_REV5 -digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 -hmi1001 powerpc mpc5xxx - manroland -mucmc52 powerpc mpc5xxx - manroland -uc101 powerpc mpc5xxx - manroland -MVBC_P powerpc mpc5xxx mvbc_p matrix_vision - MVBC_P:MVBC_P -MVSMR powerpc mpc5xxx mvsmr matrix_vision -pcm030 powerpc mpc5xxx pcm030 phytec - pcm030 -pcm030_LOWBOOT powerpc mpc5xxx pcm030 phytec - pcm030:SYS_TEXT_BASE=0xFF000000 -aev powerpc mpc5xxx tqm5200 tqc -cam5200 powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B -cam5200_niosflash powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH -charon powerpc mpc5xxx tqm5200 tqc - charon -fo300 powerpc mpc5xxx tqm5200 tqc - TQM5200:FO300 -MiniFAP powerpc mpc5xxx tqm5200 tqc - TQM5200:MINIFAP -TB5200 powerpc mpc5xxx tqm5200 tqc -TB5200_B powerpc mpc5xxx tqm5200 tqc - TB5200:TQM5200_B -TQM5200 powerpc mpc5xxx tqm5200 tqc - TQM5200: -TQM5200_B powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B -TQM5200_B_HIGHBOOT powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 -TQM5200S powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,TQM5200S -TQM5200S_HIGHBOOT powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 -TQM5200_STK100 powerpc mpc5xxx tqm5200 tqc - TQM5200:STK52XX_REV100 -A3000 powerpc mpc824x a3000 -CPC45 powerpc mpc824x cpc45 - - CPC45 -CPC45_ROMBOOT powerpc mpc824x cpc45 - - CPC45:BOOT_ROM -CU824 powerpc mpc824x cu824 -eXalion powerpc mpc824x eXalion -HIDDEN_DRAGON powerpc mpc824x hidden_dragon -linkstation_HGLAN powerpc mpc824x linkstation - - linkstation:HGLAN=1 -MOUSSE powerpc mpc824x mousse -MUSENKI powerpc mpc824x musenki -MVBLUE powerpc mpc824x mvblue -PN62 powerpc mpc824x pn62 -Sandpoint8240 powerpc mpc824x sandpoint -Sandpoint8245 powerpc mpc824x sandpoint -utx8245 powerpc mpc824x -debris powerpc mpc824x - etin -kvme080 powerpc mpc824x - etin -atc powerpc mpc8260 -cogent_mpc8260 powerpc mpc8260 cogent -CPU86 powerpc mpc8260 cpu86 - - CPU86 -CPU86_ROMBOOT powerpc mpc8260 cpu86 - - CPU86:BOOT_ROM -CPU87 powerpc mpc8260 cpu87 - - CPU87 -CPU87_ROMBOOT powerpc mpc8260 cpu87 - - CPU87:BOOT_ROM -ep8248 powerpc mpc8260 ep8248 -ep8248E powerpc mpc8260 ep8248 - - ep8248 -ep8260 powerpc mpc8260 -ep82xxm powerpc mpc8260 -gw8260 powerpc mpc8260 -hymod powerpc mpc8260 -IDS8247 powerpc mpc8260 ids8247 -IPHASE4539 powerpc mpc8260 iphase4539 -ISPAN powerpc mpc8260 ispan -ISPAN_REVB powerpc mpc8260 ispan - - ISPAN:SYS_REV_B -muas3001 powerpc mpc8260 muas3001 -muas3001_dev powerpc mpc8260 muas3001 - - muas3001:MUAS_DEV_BOARD -PM825 powerpc mpc8260 pm826 - - PM826:PCI,SYS_TEXT_BASE=0xFF000000 -PM825_BIGFLASH powerpc mpc8260 pm826 - - PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 -PM825_ROMBOOT powerpc mpc8260 pm826 - - PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -PM825_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 -PM826 powerpc mpc8260 pm826 - - PM826:SYS_TEXT_BASE=0xFF000000 -PM826_BIGFLASH powerpc mpc8260 pm826 - - PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 -PM826_ROMBOOT powerpc mpc8260 pm826 - - PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -PM826_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 -PM828 powerpc mpc8260 pm828 - - PM828 -PM828_PCI powerpc mpc8260 pm828 - - PM828:PCI -PM828_ROMBOOT powerpc mpc8260 pm828 - - PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -PM828_ROMBOOT_PCI powerpc mpc8260 pm828 - - PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -ppmc8260 powerpc mpc8260 -Rattler powerpc mpc8260 rattler - - Rattler -Rattler8248 powerpc mpc8260 rattler - - Rattler:MPC8248 -RPXsuper powerpc mpc8260 rpxsuper -rsdproto powerpc mpc8260 -sacsng powerpc mpc8260 -ZPC1900 powerpc mpc8260 zpc1900 -MPC8260ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS -MPC8260ADS_33MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 -MPC8260ADS_33MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 -MPC8260ADS_40MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 -MPC8260ADS_40MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 -MPC8260ADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 -MPC8266ADS powerpc mpc8260 mpc8266ads freescale -MPC8272ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS -MPC8272ADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 -PQ2FADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS -PQ2FADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 -PQ2FADS-VR powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 -PQ2FADS-VR_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 -PQ2FADS-ZU powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS -PQ2FADS-ZU_66MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 -PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 -PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 -VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz -mgcoge powerpc mpc8260 km82xx keymile - km82xx:MGCOGE -mgcoge3ne powerpc mpc8260 km82xx keymile - km82xx:MGCOGE3NE -TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz -TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz -TQM8260_AB powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x -TQM8260_AC powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x -TQM8260_AD powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x -TQM8260_AE powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,266MHz -TQM8260_AF powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x -TQM8260_AG powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz -TQM8260_AH powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x -TQM8260_AI powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x -TQM8265_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8265,300MHz,BUSMODE_60x -TQM8272 powerpc mpc8260 tqm8272 tqc -mpc8308_p1m powerpc mpc83xx -sbc8349 powerpc mpc83xx sbc8349 - - sbc8349 -sbc8349_PCI_33 powerpc mpc83xx sbc8349 - - sbc8349:PCI,PCI_33M -sbc8349_PCI_66 powerpc mpc83xx sbc8349 - - sbc8349:PCI,PCI_66M -ve8313 powerpc mpc83xx ve8313 -caddy2 powerpc mpc83xx vme8349 esd - vme8349:CADDY2 -vme8349 powerpc mpc83xx vme8349 esd - vme8349 -MPC8308RDB powerpc mpc83xx mpc8308rdb freescale -MPC8313ERDB_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ -MPC8313ERDB_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ -MPC8313ERDB_NAND_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ,NAND -MPC8313ERDB_NAND_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ,NAND -MPC8315ERDB powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB -MPC8315ERDB_NAND powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB:NAND_U_BOOT -MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale -MPC832XEMDS powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS: -MPC832XEMDS_ATM powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 -MPC832XEMDS_HOST_33 powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 -MPC832XEMDS_HOST_66 powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 -MPC832XEMDS_SLAVE powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCISLAVE -MPC8349EMDS powerpc mpc83xx mpc8349emds freescale -MPC8349ITX powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX -MPC8349ITXGP powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 -MPC8349ITX_LOWBOOT powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 -MPC8360EMDS_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ -MPC8360EMDS_33_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 -MPC8360EMDS_33_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 -MPC8360EMDS_33_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 -MPC8360EMDS_33_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE -MPC8360EMDS_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ -MPC8360EMDS_66_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 -MPC8360EMDS_66_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 -MPC8360EMDS_66_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 -MPC8360EMDS_66_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE -MPC8360ERDK powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK -MPC8360ERDK_33 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK:CLKIN_33MHZ -MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK -MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS -MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI -MPC837XERDB powerpc mpc83xx mpc837xerdb freescale -kmcoge5ne powerpc mpc83xx km83xx keymile - km8360:KMCOGE5NE -kmeter1 powerpc mpc83xx km83xx keymile - km8360:KMETER1 -MERGERBOX powerpc mpc83xx mergerbox matrix_vision -MVBLM7 powerpc mpc83xx mvblm7 matrix_vision -SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP -SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP -TQM834x powerpc mpc83xx tqm834x tqc -suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3 -kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1 -tuge1 powerpc mpc83xx km83xx keymile - tuxx1:TUGE1 -tuxx1 powerpc mpc83xx km83xx keymile - tuxx1:TUXX1 -kmopti2 powerpc mpc83xx km83xx keymile - tuxx1:KMOPTI2 -kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KMSUPX5 -sbc8548 powerpc mpc85xx sbc8548 - - sbc8548 -sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33 -sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE -sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66 -sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE -socrates powerpc mpc85xx socrates -HWW1U1A powerpc mpc85xx hww1u1a exmeritus -MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS -MPC8536DS_36BIT powerpc mpc85xx mpc8536ds freescale - MPC8536DS:36BIT -MPC8536DS_NAND powerpc mpc85xx mpc8536ds freescale - MPC8536DS:NAND -MPC8536DS_SDCARD powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SDCARD -MPC8536DS_SPIFLASH powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SPIFLASH -MPC8540ADS powerpc mpc85xx mpc8540ads freescale -MPC8541CDS powerpc mpc85xx mpc8541cds freescale - MPC8541CDS -MPC8541CDS_legacy powerpc mpc85xx mpc8541cds freescale - MPC8541CDS:LEGACY -MPC8544DS powerpc mpc85xx mpc8544ds freescale -MPC8548CDS powerpc mpc85xx mpc8548cds freescale - MPC8548CDS -MPC8548CDS_36BIT powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:36BIT -MPC8548CDS_legacy powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:LEGACY -MPC8555CDS powerpc mpc85xx mpc8555cds freescale - MPC8555CDS -MPC8555CDS_legacy powerpc mpc85xx mpc8555cds freescale - MPC8555CDS:LEGACY -MPC8560ADS powerpc mpc85xx mpc8560ads freescale -MPC8568MDS powerpc mpc85xx mpc8568mds freescale -MPC8569MDS powerpc mpc85xx mpc8569mds freescale - MPC8569MDS -MPC8569MDS_ATM powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:ATM -MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:NAND -MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS -MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT -MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND -P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND -P1010RDB_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT -P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT -P1010RDB_36BIT_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SECURE_BOOT -P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD -P1010RDB_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH -P1010RDB_36BIT_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT -P1010RDB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND -P1010RDB_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT -P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB -P1010RDB_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SECURE_BOOT -P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD -P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH -P1010RDB_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT -P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB -P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT -P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD -P1011RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SPIFLASH -P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND -P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD -P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH -P1020MBG-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG -P1020MBG-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,36BIT -P1020MBG-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT -P1020MBG-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,SDCARD -P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB -P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT -P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD -P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH -P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND -P1020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB -P1020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT -P1020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,NAND -P1020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SDCARD -P1020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SPIFLASH -P1020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,NAND -P1020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SDCARD -P1020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SPIFLASH -P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD -P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH -P1020UTM-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM -P1020UTM-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT -P1020UTM-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD -P1020UTM-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,SDCARD -P1021RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB -P1021RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT -P1021RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,NAND -P1021RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD -P1021RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH -P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,NAND -P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD -P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH -P1022DS powerpc mpc85xx p1022ds freescale -P1022DS_NAND powerpc mpc85xx p1022ds freescale - P1022DS:NAND -P1022DS_36BIT_NAND powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,NAND -P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH -P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH -P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD -P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SDCARD -P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT -P1023RDB powerpc mpc85xx p1023rdb freescale - P1023RDB -P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS -P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND -P1024RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB -P1024RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,36BIT -P1024RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,NAND -P1024RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,SDCARD -P1024RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,SPIFLASH -P1025RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB -P1025RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,36BIT -P1025RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,NAND -P1025RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SDCARD -P1025RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SPIFLASH -P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB -P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT -P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD -P2010RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SPIFLASH -P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND -P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD -P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH -P2020COME_SDCARD powerpc mpc85xx p2020come freescale - P2020COME:SDCARD -P2020COME_SPIFLASH powerpc mpc85xx p2020come freescale - P2020COME:SPIFLASH -P2020DS powerpc mpc85xx p2020ds freescale -P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT -P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 -P2020DS_SDCARD powerpc mpc85xx p2020ds freescale - P2020DS:SDCARD -P2020DS_SPIFLASH powerpc mpc85xx p2020ds freescale - P2020DS:SPIFLASH -P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB -P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT -P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD -P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SPIFLASH -P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND -P2020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB -P2020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT -P2020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,NAND -P2020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD -P2020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH -P2020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,NAND -P2020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,SDCARD -P2020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,SPIFLASH -P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD -P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH -P2041RDB powerpc mpc85xx p2041rdb freescale -P2041RDB_NAND powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT -P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -P2041RDB_SRIO_PCIE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -P3041DS powerpc mpc85xx corenet_ds freescale -P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT -P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -P3041DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -P4080DS powerpc mpc85xx corenet_ds freescale -P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT -P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -P4080DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -P5020DS powerpc mpc85xx corenet_ds freescale -P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT -P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -P5040DS powerpc mpc85xx corenet_ds freescale -P5040DS_NAND powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -P5040DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -P5040DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH -BSC9131RDB_SPIFLASH_SYSCLK100 powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 -BSC9131RDB_NAND powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND -BSC9131RDB_NAND_SYSCLK100 powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 -BSC9132QDS_NOR_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 -BSC9132QDS_NOR_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 -BSC9132QDS_NAND_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 -BSC9132QDS_NAND_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 -BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 -BSC9132QDS_SDCARD_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 -BSC9132QDS_SPIFLASH_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 -BSC9132QDS_SPIFLASH_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 -controlcenterd_36BIT_SDCARD powerpc mpc85xx p1022 gdsys - controlcenterd:36BIT,SDCARD -controlcenterd_36BIT_SDCARD_DEVELOP powerpc mpc85xx p1022 gdsys - controlcenterd:36BIT,SDCARD,DEVELOP -controlcenterd_TRAILBLAZER powerpc mpc85xx p1022 gdsys - controlcenterd:TRAILBLAZER,SPIFLASH -controlcenterd_TRAILBLAZER_DEVELOP powerpc mpc85xx p1022 gdsys - controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP -stxgp3 powerpc mpc85xx stxgp3 stx -stxssa powerpc mpc85xx stxssa stx - stxssa -stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M -T4240QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240 -T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -T4160QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160 -T4160QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -T4160QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860 -B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -B4860QDS_SRIO_PCIE_BOOT powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -B4420QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420 -B4420QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -B4420QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -xpedite520x powerpc mpc85xx - xes -xpedite537x powerpc mpc85xx - xes -xpedite550x powerpc mpc85xx - xes -sbc8641d powerpc mpc86xx -MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale -MPC8641HPCN powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN -MPC8641HPCN_36BIT powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN:PHYS_64BIT -xpedite517x powerpc mpc86xx - xes -Adder powerpc mpc8xx adder -Adder87x powerpc mpc8xx adder - - Adder -AdderII powerpc mpc8xx adder - - Adder:MPC852T -AdderUSB powerpc mpc8xx adder - - Adder -ADS860 powerpc mpc8xx fads -cogent_mpc8xx powerpc mpc8xx cogent -ESTEEM192E powerpc mpc8xx esteem192e -FADS823 powerpc mpc8xx fads -FADS850SAR powerpc mpc8xx fads -FADS860T powerpc mpc8xx fads -FLAGADM powerpc mpc8xx flagadm -GEN860T powerpc mpc8xx gen860t -GEN860T_SC powerpc mpc8xx gen860t - - GEN860T:SC -GENIETV powerpc mpc8xx genietv -hermes powerpc mpc8xx -ICU862 powerpc mpc8xx icu862 -ICU862_100MHz powerpc mpc8xx icu862 - - ICU862:100MHz -IP860 powerpc mpc8xx ip860 -IVML24 powerpc mpc8xx ivm - - IVML24:IVML24_16M -IVML24_128 powerpc mpc8xx ivm - - IVML24:IVML24_32M -IVML24_256 powerpc mpc8xx ivm - - IVML24:IVML24_64M -IVMS8 powerpc mpc8xx ivm - - IVMS8:IVMS8_16M -IVMS8_128 powerpc mpc8xx ivm - - IVMS8:IVMS8_32M -IVMS8_256 powerpc mpc8xx ivm - - IVMS8:IVMS8_64M -lwmon powerpc mpc8xx -MBX powerpc mpc8xx mbx8xx -MBX860T powerpc mpc8xx mbx8xx -MPC86xADS powerpc mpc8xx fads -MPC885ADS powerpc mpc8xx fads -NETPHONE powerpc mpc8xx netphone - - NETPHONE:NETPHONE_VERSION=1 -NETPHONE_V2 powerpc mpc8xx netphone - - NETPHONE:NETPHONE_VERSION=2 -NETTA powerpc mpc8xx netta - - NETTA -NETTA2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=1 -NETTA2_V2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=2 -NETTA_6412 powerpc mpc8xx netta - - NETTA:NETTA_6412=1 -NETTA_6412_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 -NETTA_ISDN powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1 -NETTA_ISDN_6412 powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_6412=1 -NETTA_ISDN_6412_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 -NETTA_ISDN_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 -NETTA_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_SWAPHOOK=1 -NETVIA powerpc mpc8xx netvia - - NETVIA:NETVIA_VERSION=1 -NETVIA_V2 powerpc mpc8xx netvia - - NETVIA:NETVIA_VERSION=2 -NX823 powerpc mpc8xx nx823 -quantum powerpc mpc8xx -R360MPI powerpc mpc8xx r360mpi -RBC823 powerpc mpc8xx rbc823 -RPXClassic powerpc mpc8xx -RPXlite powerpc mpc8xx -RPXlite_DW powerpc mpc8xx RPXlite_dw - - RPXlite_DW -RPXlite_DW_64 powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz -RPXlite_DW_64_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 -RPXlite_DW_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:LCD,NEC_NL6448BC20 -RPXlite_DW_NVRAM powerpc mpc8xx RPXlite_dw - - RPXlite_DW:ENV_IS_IN_NVRAM -RPXlite_DW_NVRAM_64 powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM -RPXlite_DW_NVRAM_64_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -RPXlite_DW_NVRAM_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -RRvision powerpc mpc8xx -RRvision_LCD powerpc mpc8xx RRvision - - RRvision:LCD,SHARP_LQ104V7DS01 -spc1920 powerpc mpc8xx -SPD823TS powerpc mpc8xx spd8xx -svm_sc8xx powerpc mpc8xx -SXNI855T powerpc mpc8xx sixnet -v37 powerpc mpc8xx -MHPC powerpc mpc8xx mhpc eltec -TOP860 powerpc mpc8xx top860 emk -KUP4K powerpc mpc8xx kup4k kup -KUP4X powerpc mpc8xx kup4x kup -ELPT860 powerpc mpc8xx elpt860 LEOX -uc100 powerpc mpc8xx - manroland -QS823 powerpc mpc8xx qs850 snmc -QS850 powerpc mpc8xx qs850 snmc -QS860T powerpc mpc8xx qs860t snmc -stxxtc powerpc mpc8xx stxxtc stx -FPS850L powerpc mpc8xx tqm8xx tqc -FPS860L powerpc mpc8xx tqm8xx tqc -NSCU powerpc mpc8xx tqm8xx tqc -SM850 powerpc mpc8xx tqm8xx tqc -TK885D powerpc mpc8xx tqm8xx tqc -TQM823L powerpc mpc8xx tqm8xx tqc -TQM823L_LCD powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,NEC_NL6448BC20 -TQM823M powerpc mpc8xx tqm8xx tqc -TQM850L powerpc mpc8xx tqm8xx tqc -TQM850M powerpc mpc8xx tqm8xx tqc -TQM855L powerpc mpc8xx tqm8xx tqc -TQM855M powerpc mpc8xx tqm8xx tqc -TQM860L powerpc mpc8xx tqm8xx tqc -TQM860M powerpc mpc8xx tqm8xx tqc -TQM862L powerpc mpc8xx tqm8xx tqc -TQM862M powerpc mpc8xx tqm8xx tqc -TQM866M powerpc mpc8xx tqm8xx tqc -TQM885D powerpc mpc8xx tqm8xx tqc -TTTech powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ104V7DS01 -virtlab2 powerpc mpc8xx tqm8xx tqc -wtk powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ065T9DR51U -csb272 powerpc ppc4xx -csb472 powerpc ppc4xx -G2000 powerpc ppc4xx g2000 -JSE powerpc ppc4xx jse -korat powerpc ppc4xx -korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT -lwmon5 powerpc ppc4xx -lcd4_lwmon5 powerpc ppc4xx lwmon5 - - lwmon5:LCD4_LWMON5 -pcs440ep powerpc ppc4xx -quad100hd powerpc ppc4xx -sbc405 powerpc ppc4xx -sc3 powerpc ppc4xx -t3corp powerpc ppc4xx -W7OLMC powerpc ppc4xx w7o -W7OLMG powerpc ppc4xx w7o -zeus powerpc ppc4xx -acadia powerpc ppc4xx - amcc -acadia_nand powerpc ppc4xx acadia amcc - acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 -arches powerpc ppc4xx canyonlands amcc - canyonlands:ARCHES -bamboo powerpc ppc4xx - amcc -bamboo_nand powerpc ppc4xx bamboo amcc - bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 -bluestone powerpc ppc4xx - amcc -bubinga powerpc ppc4xx - amcc -canyonlands powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS -canyonlands_nand powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 -ebony powerpc ppc4xx - amcc -glacier powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER -glacier_nand powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 -haleakala powerpc ppc4xx kilauea amcc - kilauea:HALEAKALA -haleakala_nand powerpc ppc4xx kilauea amcc - kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 -katmai powerpc ppc4xx - amcc -kilauea powerpc ppc4xx kilauea amcc - kilauea:KILAUEA -kilauea_nand powerpc ppc4xx kilauea amcc - kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 -luan powerpc ppc4xx - amcc -makalu powerpc ppc4xx - amcc -ocotea powerpc ppc4xx - amcc -rainier powerpc ppc4xx sequoia amcc - sequoia:RAINIER -rainier_nand powerpc ppc4xx sequoia amcc - sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 -rainier_ramboot powerpc ppc4xx sequoia amcc - sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds -redwood powerpc ppc4xx - amcc -sequoia powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA -sequoia_nand powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 -sequoia_ramboot powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds -sycamore powerpc ppc4xx walnut amcc - walnut -taihu powerpc ppc4xx - amcc -taishan powerpc ppc4xx - amcc -walnut powerpc ppc4xx walnut amcc -yellowstone powerpc ppc4xx yosemite amcc - yosemite:YELLOWSTONE -yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE -yucca powerpc ppc4xx - amcc -fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o -fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o -v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o -v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o -CRAYL1 powerpc ppc4xx L1 cray -CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1 -CATcenter_25 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 -CATcenter_33 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -PPChameleonEVB powerpc ppc4xx PPChameleonEVB dave -PPChameleonEVB_BA_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 -PPChameleonEVB_BA_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 -PPChameleonEVB_HI_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 -PPChameleonEVB_HI_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 -PPChameleonEVB_ME_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 -PPChameleonEVB_ME_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -APC405 powerpc ppc4xx apc405 esd -AR405 powerpc ppc4xx ar405 esd -ASH405 powerpc ppc4xx ash405 esd -CANBT powerpc ppc4xx canbt esd -CMS700 powerpc ppc4xx cms700 esd -CPCI2DP powerpc ppc4xx cpci2dp esd -CPCI405 powerpc ppc4xx cpci405 esd -CPCI4052 powerpc ppc4xx cpci405 esd -CPCI405AB powerpc ppc4xx cpci405 esd -CPCI405DT powerpc ppc4xx cpci405 esd -CPCIISER4 powerpc ppc4xx cpciiser4 esd -DP405 powerpc ppc4xx dp405 esd -DU405 powerpc ppc4xx du405 esd -DU440 powerpc ppc4xx du440 esd -HH405 powerpc ppc4xx hh405 esd -HUB405 powerpc ppc4xx hub405 esd -OCRTC powerpc ppc4xx ocrtc esd -PCI405 powerpc ppc4xx pci405 esd -PLU405 powerpc ppc4xx plu405 esd -PMC405 powerpc ppc4xx pmc405 esd -PMC405DE powerpc ppc4xx pmc405de esd -PMC440 powerpc ppc4xx pmc440 esd -VOH405 powerpc ppc4xx voh405 esd -VOM405 powerpc ppc4xx vom405 esd -WUH405 powerpc ppc4xx wuh405 esd -devconcenter powerpc ppc4xx intip gdsys - intip:DEVCONCENTER -dlvision powerpc ppc4xx - gdsys -dlvision-10g powerpc ppc4xx 405ep gdsys -gdppc440etx powerpc ppc4xx - gdsys -intip powerpc ppc4xx intip gdsys - intip:INTIB -io powerpc ppc4xx 405ep gdsys -io64 powerpc ppc4xx 405ex gdsys -iocon powerpc ppc4xx 405ep gdsys -neo powerpc ppc4xx 405ep gdsys -icon powerpc ppc4xx - mosaixtech -MIP405 powerpc ppc4xx mip405 mpl -MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T -PIP405 powerpc ppc4xx pip405 mpl -alpr powerpc ppc4xx - prodrive -p3p440 powerpc ppc4xx - prodrive -KAREF powerpc ppc4xx karef sandburst -METROBOX powerpc ppc4xx metrobox sandburst -xpedite1000 powerpc ppc4xx - xes -ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o -ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o -xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 -xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC -xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 -xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC -sandbox sandbox sandbox sandbox sandbox - -rsk7203 sh sh2 rsk7203 renesas - -rsk7264 sh sh2 rsk7264 renesas - -rsk7269 sh sh2 rsk7269 renesas - -mpr2 sh sh3 mpr2 - - -ms7720se sh sh3 ms7720se - - -shmin sh sh3 shmin - - -espt sh sh4 espt - - -ms7722se sh sh4 ms7722se - - -ms7750se sh sh4 ms7750se - - -ap325rxa sh sh4 ap325rxa renesas - -ecovec sh sh4 ecovec renesas - -MigoR sh sh4 MigoR renesas - -r2dplus sh sh4 r2dplus renesas - -r7780mp sh sh4 r7780mp renesas - -sh7752evb sh sh4 sh7752evb renesas - -sh7757lcr sh sh4 sh7757lcr renesas - -sh7763rdp sh sh4 sh7763rdp renesas - -sh7785lcr sh sh4 sh7785lcr renesas - -sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1 -r0p7734 sh sh4 r0p7734 renesas - -ap_sh4a_4a sh sh4 ap_sh4a_4a alphaproject - -grsim_leon2 sparc leon2 - gaisler -gr_cpci_ax2000 sparc leon3 - gaisler -gr_ep2s60 sparc leon3 - gaisler -grsim sparc leon3 - gaisler -gr_xc3s_1500 sparc leon3 - gaisler -coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000 -# Target ARCH CPU Board name Vendor SoC Options -######################################################################################################################## diff --git a/common/Kconfig b/common/Kconfig new file mode 100644 index 0000000000..da18c7ae77 --- /dev/null +++ b/common/Kconfig @@ -0,0 +1,505 @@ +menu "Command line interface" + depends on !SPL_BUILD + +config HUSH_PARSER + bool "Use hush shell" + select SYS_HUSH_PARSER + help + This option enables the "hush" shell (from Busybox) as command line + interpreter, thus enabling powerful command line syntax like + if...then...else...fi conditionals or `&&' and '||' + constructs ("shell scripts"). + + If disabled, you get the old, much simpler behaviour with a somewhat + smaller memory footprint. + +config SYS_HUSH_PARSER + bool + help + Backward compatibility. + +comment "Commands" + +menu "Info commands" + +config CMD_BDI + bool "bdinfo" + default y + help + Print board info + +config CMD_CONSOLE + bool "coninfo" + default y + help + Print console devices and information. + +config CMD_LICENSE + bool "license" + help + Print GPL license text + +endmenu + +menu "Boot commands" + +config CMD_BOOTD + bool "bootd" + default y + help + Run the command stored in the environment "bootcmd", i.e. + "bootd" does the same thing as "run bootcmd". + +config CMD_BOOTM + bool "bootm" + default y + help + Boot an application image from the memory. + +config CMD_BOOTZ + bool "bootz" + default y + help + Boot a Linux kernel zImage. + +config CMD_BOOTCE + bool "bootce" + help + Boot a WindowsCE image. + +config CMD_GO + bool "go" + default y + help + Start an application at a given address. + +config CMD_RUN + bool "run" + default y + help + Run the command in the given environment variable. + +config CMD_IMI + bool "iminfo" + default y + help + Print header information for application image. + +config CMD_IMLS + bool "imls" + default !SYS_NO_FLASH + help + List all images found in flash + +config CMD_XIMG + bool "imxtract" + default y + help + Extract a part of a multi-image. + +endmenu + +menu "DTB support" + +config OF_LIBFDT + bool "Enable FDT commands" + +config OF_BOARD_SETUP + bool "Support DT modifications by board code" + depends on OF_LIBFDT + +endmenu + +menu "Environment commands" + +config CMD_EXPORTENV + bool "env export" + default y + help + Export environments. + +config CMD_IMPORTENV + bool "env import" + default y + help + Import environments. + +config CMD_EDITENV + bool "editenv" + default y + help + Edit environment variable. + +config CMD_SAVEENV + bool "saveenv" + default y + help + Run the command in the given environment variable. + +endmenu + +menu "Memory commands" + +config CMD_MEMORY + bool "md, mm, nm, mw, cp, cmp, base, loop" + default y + help + Memeory commands. + md - memory display + mm - memory modify (auto-incrementing address) + nm - memory modify (constant address) + mw - memory write (fill) + cp - memory copy + cmp - memory compare + base - print or set address offset + loop - initinite loop on address range + +config CMD_CRC32 + bool "crc32" + default y + help + Compute CRC32. + +config LOOPW + bool "loopw" + help + Infinite write loop on address range + +config CMD_MEMTEST + bool "crc32" + help + Simple RAM read/write test. + +config CMD_MX_CYCLIC + bool "mdc, mwc" + help + mdc - memory display cyclic + mwc - memory write cyclic + +config CMD_MEMINFO + bool "meminfo" + help + Display memory information. + +endmenu + +menu "Device access commands" + +config CMD_LOADB + bool "loadb" + default y + help + Load a binary file over serial line. + +config CMD_LOADS + bool "loads" + default y + help + Load an S-Record file over serial line + +config CMD_FLASH + bool "flinfo, erase, protect" + default y if !SYS_NO_FLASH + help + NOR flash support. + flinfo - print FLASH memory information + erase - FLASH memory + protect - enable or disable FLASH write protection + +config MTD_DEVICE + bool "MTD device support" + +config CMD_MTDPARTS + bool "MTD partitioning support" + default y + depends on MTD_DEVICE && (CMD_FLASH || CMD_NAND) + +config CMD_NAND + bool "nand" + help + NAND support. + +config CMD_NAND_TRIMFFS + bool "Enable nand write.trimffs command" + help + Enable command to leave page sized runs of 0xff patterns in + erased state rather than overwriting them. This is required + for using NAND flash filesystems on NAND controllers with + a non-0xff ECC code for all 0xff data. + +config CMD_ROMUPDATE + bool + depends on NAND + +config CMD_MMC + bool "mmc/sd" + select PARTITIONS + help + MMC/SD support. + +config CMD_SPI + bool "sspi" + help + SPI utility command. + +config CMD_I2C + bool "i2c" + help + I2C support. + +config CMD_USB + bool "usb" + help + USB support. + +config CMD_FPGA + bool "fpga" + default y + help + FPGA support. + +endmenu + + +menu "Shell scripting commands" + +config CMD_ECHO + bool "echo" + default y + help + Echo args to console + +config CMD_ITEST + bool "itest" + default y + help + Return true/false on integer compare. + +config CMD_SOURCE + bool "source" + default y + help + Run script from memory + +endmenu + +menu "Network commands" + +config CMD_NET + bool "bootp, tftpboot" + default y + help + Network commands. + bootp - boot image via network using BOOTP/TFTP protocol + tftpboot - boot image via network using TFTP protocol + +config CMD_TFTPPUT + bool "tftp put" + help + TFTP put command, for uploading files to a server + +config CMD_TFTPSRV + bool "tftpsrv" + help + Act as a TFTP server and boot the first received file + +config CMD_RARP + bool "rarpboot" + help + Boot image via network using RARP/TFTP protocol + +config CMD_DHCP + bool "dhcp" + help + Boot image via network using DHCP/TFTP protocol + +if CMD_DHCP + +menu "DHCP options" + +config BOOTP_BOOTFILESIZE + bool "obtain bootfile size from DHCP" + +config BOOTP_BOOTPATH + bool "obtain bootfile path from DHCP" + +config BOOTP_DNS + bool "obtain DNS server IP address from DHCP" + +config BOOTP_DNS2 + bool "store secondary DNS IP address in dnsip2" + +config BOOTP_GATEWAY + bool "obtain gateway IP address from DHCP" + +config BOOTP_ID_CACHE_SIZE + int "DHCP transaction ID cache size" + default 4 + help + BOOTP packets are uniquely identified using a 32-bit ID. The + server will copy the ID from client requests to responses and + U-Boot will use this to determine if it is the destination of + an incoming response. Some servers will check that addresses + aren't in use before handing them out (usually using an ARP + ping) and therefore take up to a few hundred milliseconds to + respond. Network congestion may also influence the time it + takes for a response to make it back to the client. If that + time is too long, U-Boot will retransmit requests. In order + to allow earlier responses to still be accepted after these + retransmissions, U-Boot's BOOTP client keeps a small cache of + IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this + cache. The default is to keep IDs for up to four outstanding + requests. Increasing this will allow U-Boot to accept offers + from a BOOTP client in networks with unusually high latency. + +config BOOTP_MAY_FAIL + bool "Do not start over, if DHCP server is not available" + help + If the DHCP server is not found after the configured retry + count, the call will fail instead of starting over. This + can be used to fail over to Link-local IP address + configuration if the DHCP server is not available. + +config BOOTP_NISDOMAIN + bool "obtain NIS domain from DHCP" + +config BOOTP_NTPSERVER + bool "obtain NTP server IP address from DHCP" + +config BOOTP_RANDOM_DELAY + bool "Use a (pseudo) random delay between DHCP retries" + select LIB_RAND + +config BOOTP_RANDOM_ID + bool "Generate a (pseudo) random transaction ID" + select LIB_RAND + +config BOOTP_SEND_HOSTNAME + bool "send hostname in DHCP request" + +config BOOTP_SUBNETMASK + bool "obtain subnet mask from DHCP" + +config BOOTP_TIMEOFFSET + bool "obtain from DHCP" + +config BOOTP_VENDOREX + bool "obtain from DHCP" + +endmenu + +endif + +config CMD_NFS + bool "nfs" + default y + help + Boot image via network using NFS protocol. + +config CMD_PING + bool "ping" + help + Send ICMP ECHO_REQUEST to network host + +config CMD_CDP + bool "cdp" + help + Perform CDP network configuration + +config CMD_SNTP + bool "sntp" + help + Synchronize RTC via network + +config CMD_DNS + bool "dns" + help + Lookup the IP of a hostname + +config CMD_LINK_LOCAL + bool "linklocal" + help + Acquire a network IP address using the link-local protocol + +config CMD_MII + bool "MII register access" + help + Support reading/writing ETH PHY registers via MII bus + +endmenu + +menu "Misc commands" + +config CMD_CACHE + bool "cache control" + help + Enable commands to switch data cache on/off. + +config CMD_TIME + bool "time" + help + Run commands and summarize execution time. + +config CMD_FUSE + bool "fuse read/write" + help + eFuse reading and programming support + +# TODO: rename to CMD_SLEEP +config CMD_MISC + bool "sleep" + default y + help + Delay execution for some time + +config CMD_TIMER + bool "timer" + help + Access the system timer. + +config CMD_SETGETDCR + bool "getdcr, setdcr, getidcr, setidcr" + depends on 4xx + default y + help + getdcr - Get an AMCC PPC 4xx DCR's value + setdcr - Set an AMCC PPC 4xx DCR's value + getidcr - Get a register value via indirect DCR addressing + setidcr - Set a register value via indirect DCR addressing + +endmenu + +endmenu + +menu "Environment configuration settings" + +choice + prompt "Select environment non-volatile storage" + +config ENV_IS_NOWHERE + bool "do not store environment" + +config ENV_IS_IN_NAND + bool "store environment in NAND" + depends on NAND + +config ENV_IS_IN_MMC + bool "store environment in MMC" + depends on MMC + +config ENV_IS_IN_SPI_FLASH + bool "store environment in SPI flash" + +endchoice + +endmenu + +menu "Display configuration" + +config LCD + bool "LCD support" + +config DISPLAY_BOARDINFO + bool "Display board info" + +endmenu diff --git a/common/Makefile b/common/Makefile index ca8b5f6931..fcdb749fd6 100644 --- a/common/Makefile +++ b/common/Makefile @@ -5,272 +5,274 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libcommon.o - # core ifndef CONFIG_SPL_BUILD -COBJS-y += main.o -COBJS-y += command.o -COBJS-y += exports.o -COBJS-y += hash.o -COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o -COBJS-y += s_record.o -COBJS-y += xyzModem.o -COBJS-y += cmd_disk.o +obj-y += main.o +obj-y += exports.o +obj-y += hash.o +ifdef CONFIG_SYS_HUSH_PARSER +obj-y += cli_hush.o +endif + +# This option is not just y/n - it can have a numeric value +ifdef CONFIG_BOOTDELAY +obj-y += autoboot.o +endif + +# This option is not just y/n - it can have a numeric value +ifdef CONFIG_BOOT_RETRY_TIME +obj-y += bootretry.o +endif # boards -COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o -COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o +obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o +obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o # core command -COBJS-y += cmd_boot.o -COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o -COBJS-y += cmd_help.o -COBJS-y += cmd_version.o +obj-y += cmd_boot.o +obj-$(CONFIG_CMD_BOOTM) += cmd_bootm.o bootm.o bootm_os.o +obj-y += cmd_help.o +obj-y += cmd_version.o # environment -COBJS-y += env_attr.o -COBJS-y += env_callback.o -COBJS-y += env_flags.o -COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o -COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o -XCOBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o -COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o -XCOBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o -COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o -COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o -COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o -COBJS-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o -COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o -COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o -COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o -COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o -COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o -COBJS-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o -COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o +obj-y += env_attr.o +obj-y += env_callback.o +obj-y += env_flags.o +obj-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o +obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o +extra-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o +obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o +extra-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o +obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o +obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o +obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o +obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o +obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o +obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o +obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o +obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o +obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o +obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o +obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o # command -COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o -COBJS-$(CONFIG_SOURCE) += cmd_source.o -COBJS-$(CONFIG_CMD_SOURCE) += cmd_source.o -COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o -COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o -COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o -COBJS-$(CONFIG_CMD_BOOTCE) += cmd_bootce.o -COBJS-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o -COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o -COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o -COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o -COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o -COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o -COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o -COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o -COBJS-$(CONFIG_CMD_DATE) += cmd_date.o -COBJS-$(CONFIG_CMD_SOUND) += cmd_sound.o +obj-$(CONFIG_CMD_AES) += cmd_aes.o +obj-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o +obj-$(CONFIG_SOURCE) += cmd_source.o +obj-$(CONFIG_CMD_SOURCE) += cmd_source.o +obj-$(CONFIG_CMD_BDI) += cmd_bdinfo.o +obj-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o +obj-$(CONFIG_CMD_BMP) += cmd_bmp.o +obj-$(CONFIG_CMD_BOOTCE) += cmd_bootce.o +obj-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o +obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o +obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o +obj-$(CONFIG_CMD_CACHE) += cmd_cache.o +obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o +obj-$(CONFIG_CMD_CLK) += cmd_clk.o +obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o +obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o +obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o +obj-$(CONFIG_CMD_DATE) += cmd_date.o +obj-$(CONFIG_CMD_DEMO) += cmd_demo.o +obj-$(CONFIG_CMD_SOUND) += cmd_sound.o ifdef CONFIG_4xx -COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o +obj-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o endif ifdef CONFIG_POST -COBJS-$(CONFIG_CMD_DIAG) += cmd_diag.o +obj-$(CONFIG_CMD_DIAG) += cmd_diag.o endif -COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o -COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o -COBJS-$(CONFIG_CMD_ECHO) += cmd_echo.o -COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o -COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o -COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o -COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o -COBJS-$(CONFIG_CMD_EXT4) += cmd_ext4.o -COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o -COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o -COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o -COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o -COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o -COBJS-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o -COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o +obj-$(CONFIG_CMD_DISPLAY) += cmd_display.o +obj-$(CONFIG_CMD_DTT) += cmd_dtt.o +obj-$(CONFIG_CMD_ECHO) += cmd_echo.o +obj-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o +obj-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o +obj-$(CONFIG_CMD_ELF) += cmd_elf.o +obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o +obj-$(CONFIG_CMD_EXT4) += cmd_ext4.o +obj-$(CONFIG_CMD_EXT2) += cmd_ext2.o +obj-$(CONFIG_CMD_FAT) += cmd_fat.o +obj-$(CONFIG_CMD_FDC) += cmd_fdc.o +obj-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o +obj-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o +obj-$(CONFIG_CMD_FLASH) += cmd_flash.o ifdef CONFIG_FPGA -COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o +obj-$(CONFIG_CMD_FPGA) += cmd_fpga.o endif -COBJS-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o -COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o -COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o -COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o -COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o -COBJS-$(CONFIG_CMD_IIM) += cmd_iim.o -COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o -COBJS-$(CONFIG_CMD_HASH) += cmd_hash.o -COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o -COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o -COBJS-$(CONFIG_CMD_INI) += cmd_ini.o -COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o -COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o -COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o -COBJS-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o -COBJS-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o -COBJS-$(CONFIG_CMD_LED) += cmd_led.o -COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o -COBJS-y += cmd_load.o -COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o -COBJS-$(CONFIG_ID_EEPROM) += cmd_mac.o -COBJS-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o -COBJS-$(CONFIG_CMD_MEMORY) += cmd_mem.o -COBJS-$(CONFIG_CMD_IO) += cmd_io.o -COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o -COBJS-$(CONFIG_MII) += miiphyutil.o -COBJS-$(CONFIG_CMD_MII) += miiphyutil.o -COBJS-$(CONFIG_PHYLIB) += miiphyutil.o -COBJS-$(CONFIG_CMD_MII) += cmd_mii.o +obj-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o +obj-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o +obj-$(CONFIG_CMD_FUSE) += cmd_fuse.o +obj-$(CONFIG_CMD_GETTIME) += cmd_gettime.o +obj-$(CONFIG_CMD_GPIO) += cmd_gpio.o +obj-$(CONFIG_CMD_I2C) += cmd_i2c.o +obj-$(CONFIG_CMD_IOTRACE) += cmd_iotrace.o +obj-$(CONFIG_CMD_HASH) += cmd_hash.o +obj-$(CONFIG_CMD_IDE) += cmd_ide.o +obj-$(CONFIG_CMD_IMMAP) += cmd_immap.o +obj-$(CONFIG_CMD_INI) += cmd_ini.o +obj-$(CONFIG_CMD_IRQ) += cmd_irq.o +obj-$(CONFIG_CMD_ITEST) += cmd_itest.o +obj-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o +obj-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o +obj-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o +obj-$(CONFIG_CMD_LED) += cmd_led.o +obj-$(CONFIG_CMD_LICENSE) += cmd_license.o +obj-y += cmd_load.o +obj-$(CONFIG_LOGBUFFER) += cmd_log.o +obj-$(CONFIG_ID_EEPROM) += cmd_mac.o +obj-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o +obj-$(CONFIG_CMD_MEMORY) += cmd_mem.o +obj-$(CONFIG_CMD_IO) += cmd_io.o +obj-$(CONFIG_CMD_MFSL) += cmd_mfsl.o +obj-$(CONFIG_MII) += miiphyutil.o +obj-$(CONFIG_CMD_MII) += miiphyutil.o +obj-$(CONFIG_PHYLIB) += miiphyutil.o +obj-$(CONFIG_CMD_MII) += cmd_mii.o ifdef CONFIG_PHYLIB -COBJS-$(CONFIG_CMD_MII) += cmd_mdio.o +obj-$(CONFIG_CMD_MII) += cmd_mdio.o endif -COBJS-$(CONFIG_CMD_MISC) += cmd_misc.o -COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o -COBJS-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o -COBJS-$(CONFIG_MP) += cmd_mp.o -COBJS-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o -COBJS-$(CONFIG_CMD_NAND) += cmd_nand.o -COBJS-$(CONFIG_CMD_NET) += cmd_net.o -COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o -COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o -COBJS-$(CONFIG_CMD_PART) += cmd_part.o -COBJS-$(CONFIG_CMD_PATA) += cmd_pata.o +obj-$(CONFIG_CMD_MISC) += cmd_misc.o +obj-$(CONFIG_CMD_MMC) += cmd_mmc.o +obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o +obj-$(CONFIG_MP) += cmd_mp.o +obj-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o +obj-$(CONFIG_CMD_NAND) += cmd_nand.o +obj-$(CONFIG_CMD_NET) += cmd_net.o +obj-$(CONFIG_CMD_ONENAND) += cmd_onenand.o +obj-$(CONFIG_CMD_OTP) += cmd_otp.o +obj-$(CONFIG_CMD_PART) += cmd_part.o ifdef CONFIG_PCI -COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o +obj-$(CONFIG_CMD_PCI) += cmd_pci.o +endif +obj-y += cmd_pcmcia.o +obj-$(CONFIG_CMD_PORTIO) += cmd_portio.o +obj-$(CONFIG_CMD_PXE) += cmd_pxe.o +obj-$(CONFIG_CMD_READ) += cmd_read.o +obj-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o +obj-$(CONFIG_CMD_REISER) += cmd_reiser.o +obj-$(CONFIG_SANDBOX) += cmd_sandbox.o +obj-$(CONFIG_CMD_SATA) += cmd_sata.o +obj-$(CONFIG_CMD_SF) += cmd_sf.o +obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o +obj-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o +obj-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o +obj-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o +obj-$(CONFIG_CMD_SPI) += cmd_spi.o +obj-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o +obj-$(CONFIG_CMD_STRINGS) += cmd_strings.o +obj-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o +obj-$(CONFIG_CMD_TIME) += cmd_time.o +obj-$(CONFIG_CMD_TRACE) += cmd_trace.o +obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o +obj-$(CONFIG_CMD_TPM) += cmd_tpm.o +obj-$(CONFIG_CMD_TSI148) += cmd_tsi148.o +obj-$(CONFIG_CMD_UBI) += cmd_ubi.o +obj-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o +obj-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o +obj-$(CONFIG_CMD_UNZIP) += cmd_unzip.o +ifdef CONFIG_LZMA +obj-$(CONFIG_CMD_LZMADEC) += cmd_lzmadec.o endif -COBJS-y += cmd_pcmcia.o -COBJS-$(CONFIG_CMD_PORTIO) += cmd_portio.o -COBJS-$(CONFIG_CMD_PXE) += cmd_pxe.o -COBJS-$(CONFIG_CMD_READ) += cmd_read.o -COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o -COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o -COBJS-$(CONFIG_SANDBOX) += cmd_sandbox.o -COBJS-$(CONFIG_CMD_SATA) += cmd_sata.o -COBJS-$(CONFIG_CMD_SF) += cmd_sf.o -COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o -COBJS-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o -COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o -COBJS-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o -COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o -COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o -COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o -COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o -COBJS-$(CONFIG_CMD_TIME) += cmd_time.o -COBJS-$(CONFIG_CMD_TRACE) += cmd_trace.o -COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o -COBJS-$(CONFIG_CMD_TPM) += cmd_tpm.o -COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o -COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o -COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o -COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o -COBJS-$(CONFIG_CMD_UNZIP) += cmd_unzip.o ifdef CONFIG_CMD_USB -COBJS-y += cmd_usb.o -COBJS-y += usb.o usb_hub.o -COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o +obj-y += cmd_usb.o +obj-y += usb.o usb_hub.o +obj-$(CONFIG_USB_STORAGE) += usb_storage.o endif -COBJS-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o -COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o -COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o -COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o -COBJS-$(CONFIG_CMD_ZIP) += cmd_zip.o -COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o +obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o +obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o + +obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o +obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o +obj-$(CONFIG_CMD_XIMG) += cmd_ximg.o +obj-$(CONFIG_YAFFS2) += cmd_yaffs2.o +obj-$(CONFIG_CMD_SPL) += cmd_spl.o +obj-$(CONFIG_CMD_ZIP) += cmd_zip.o +obj-$(CONFIG_CMD_ZFS) += cmd_zfs.o # others -COBJS-$(CONFIG_BOOTSTAGE) += bootstage.o -COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o -COBJS-y += flash.o -COBJS-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o -COBJS-$(CONFIG_I2C_EDID) += edid.o -COBJS-$(CONFIG_KALLSYMS) += kallsyms.o -COBJS-y += splash.o -COBJS-$(CONFIG_LCD) += lcd.o -COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o -COBJS-$(CONFIG_MENU) += menu.o -COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o -COBJS-$(CONFIG_UPDATE_TFTP) += update.o -COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o -COBJS-$(CONFIG_CMD_DFU) += cmd_dfu.o -COBJS-$(CONFIG_CMD_GPT) += cmd_gpt.o +obj-$(CONFIG_BOOTSTAGE) += bootstage.o +obj-$(CONFIG_CONSOLE_MUX) += iomux.o +obj-y += flash.o +obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o +obj-$(CONFIG_I2C_EDID) += edid.o +obj-$(CONFIG_KALLSYMS) += kallsyms.o +obj-y += splash.o +obj-$(CONFIG_LCD) += lcd.o lcd_console.o +obj-$(CONFIG_LYNXKDI) += lynxkdi.o +obj-$(CONFIG_MENU) += menu.o +obj-$(CONFIG_MODEM_SUPPORT) += modem.o +obj-$(CONFIG_UPDATE_TFTP) += update.o +obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o +obj-$(CONFIG_CMD_DFU) += cmd_dfu.o +obj-$(CONFIG_CMD_GPT) += cmd_gpt.o endif ifdef CONFIG_SPL_BUILD -COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o -COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o -COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o +obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o +obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o +obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o +ifdef CONFIG_SPL_USB_HOST_SUPPORT +obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o +obj-$(CONFIG_USB_STORAGE) += usb_storage.o +endif +ifdef CONFIG_SPL_SATA_SUPPORT +obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o +endif # environment -COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o -COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o -COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o -ifneq ($(CONFIG_SPL_NET_SUPPORT),y) -COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o -COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o -COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o -COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o -COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o -else -COBJS-y += env_nowhere.o +ifdef CONFIG_SPL_ENV_SUPPORT +obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o +obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o +obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o +obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o +obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o +obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o +obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o +obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o +obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o endif endif # core command -COBJS-y += cmd_nvedit.o +obj-y += cmd_nvedit.o #environment -COBJS-y += env_common.o +obj-y += env_common.o #others -ifdef CONFIG_DDR_SPD -SPD := y -endif -ifdef CONFIG_SPD_EEPROM -SPD := y +obj-$(CONFIG_DDR_SPD) += ddr_spd.o +obj-$(CONFIG_SPD_EEPROM) += ddr_spd.o +obj-$(CONFIG_HWCONFIG) += hwconfig.o +obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o +obj-y += console.o +obj-$(CONFIG_CROS_EC) += cros_ec.o +obj-y += dlmalloc.o +ifdef CONFIG_SYS_MALLOC_F_LEN +obj-y += malloc_simple.o endif -COBJS-$(SPD) += ddr_spd.o -COBJS-$(CONFIG_HWCONFIG) += hwconfig.o -COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o -COBJS-y += console.o -COBJS-y += dlmalloc.o -COBJS-y += image.o -COBJS-$(CONFIG_OF_LIBFDT) += image-fdt.o -COBJS-$(CONFIG_FIT) += image-fit.o -COBJS-$(CONFIG_FIT_SIGNATURE) += image-sig.o -COBJS-y += memsize.o -COBJS-y += stdio.o - - -COBJS := $(sort $(COBJS-y)) -XCOBJS := $(sort $(XCOBJS-y)) -SRCS := $(COBJS:.o=.c) $(XCOBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -XOBJS := $(addprefix $(obj),$(XCOBJS)) - -CPPFLAGS += -I.. - -all: $(LIB) $(XOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -$(obj)env_embedded.o: $(src)env_embedded.c $(obj)../tools/envcrc - $(CC) $(AFLAGS) -Wa,--no-warn \ - -DENV_CRC=$(shell $(obj)../tools/envcrc) \ - -c -o $@ $(src)env_embedded.c - -$(obj)../tools/envcrc: - $(MAKE) -C ../tools +obj-y += image.o +obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o +obj-$(CONFIG_OF_LIBFDT) += image-fdt.o +obj-$(CONFIG_FIT) += image-fit.o +obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o +obj-$(CONFIG_IO_TRACE) += iotrace.o +obj-y += memsize.o +obj-y += stdio.o -# SEE README.arm-unaligned-accesses -$(obj)cmd_bmp.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) -$(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) -$(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) -ifneq ($(CONFIG_CMD_BMP)$(CONFIG_SPLASH_SCREEN),) -$(obj)lcd.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +# This option is not just y/n - it can have a numeric value +ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV +obj-y += aboot.o +obj-y += fb_mmc.o endif -######################################################################### +obj-$(CONFIG_CMD_BLOB) += cmd_blob.o -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +# We always have this since drivers/ddr/fs/interactive.c needs it +obj-y += cli_simple.o -sinclude $(obj).depend +obj-y += cli.o +obj-y += cli_readline.o +obj-y += command.o +obj-y += s_record.o +obj-y += xyzModem.o +obj-y += cmd_disk.o -######################################################################### +CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null) diff --git a/common/aboot.c b/common/aboot.c new file mode 100644 index 0000000000..fba8e3e683 --- /dev/null +++ b/common/aboot.c @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2009, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved. + * Portions Copyright 2014 Broadcom Corporation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of The Linux Foundation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * NOTE: + * Although it is very similar, this license text is not identical + * to the "BSD-3-Clause", therefore, DO NOT MODIFY THIS LICENSE TEXT! + */ + +#include +#include +#include +#include +#include +#include + +void write_sparse_image(block_dev_desc_t *dev_desc, + disk_partition_t *info, const char *part_name, + void *data, unsigned sz) +{ + lbaint_t blk; + lbaint_t blkcnt; + lbaint_t blks; + uint32_t bytes_written = 0; + unsigned int chunk; + unsigned int chunk_data_sz; + uint32_t *fill_buf = NULL; + uint32_t fill_val; + sparse_header_t *sparse_header; + chunk_header_t *chunk_header; + uint32_t total_blocks = 0; + int i; + + /* Read and skip over sparse image header */ + sparse_header = (sparse_header_t *) data; + + data += sparse_header->file_hdr_sz; + if (sparse_header->file_hdr_sz > sizeof(sparse_header_t)) + { + /* + * Skip the remaining bytes in a header that is longer than + * we expected. + */ + data += (sparse_header->file_hdr_sz - sizeof(sparse_header_t)); + } + + debug("=== Sparse Image Header ===\n"); + debug("magic: 0x%x\n", sparse_header->magic); + debug("major_version: 0x%x\n", sparse_header->major_version); + debug("minor_version: 0x%x\n", sparse_header->minor_version); + debug("file_hdr_sz: %d\n", sparse_header->file_hdr_sz); + debug("chunk_hdr_sz: %d\n", sparse_header->chunk_hdr_sz); + debug("blk_sz: %d\n", sparse_header->blk_sz); + debug("total_blks: %d\n", sparse_header->total_blks); + debug("total_chunks: %d\n", sparse_header->total_chunks); + + /* verify sparse_header->blk_sz is an exact multiple of info->blksz */ + if (sparse_header->blk_sz != + (sparse_header->blk_sz & ~(info->blksz - 1))) { + printf("%s: Sparse image block size issue [%u]\n", + __func__, sparse_header->blk_sz); + fastboot_fail("sparse image block size issue"); + return; + } + + puts("Flashing Sparse Image\n"); + + /* Start processing chunks */ + blk = info->start; + for (chunk=0; chunktotal_chunks; chunk++) + { + /* Read and skip over chunk header */ + chunk_header = (chunk_header_t *) data; + data += sizeof(chunk_header_t); + + if (chunk_header->chunk_type != CHUNK_TYPE_RAW) { + debug("=== Chunk Header ===\n"); + debug("chunk_type: 0x%x\n", chunk_header->chunk_type); + debug("chunk_data_sz: 0x%x\n", chunk_header->chunk_sz); + debug("total_size: 0x%x\n", chunk_header->total_sz); + } + + if (sparse_header->chunk_hdr_sz > sizeof(chunk_header_t)) + { + /* + * Skip the remaining bytes in a header that is longer + * than we expected. + */ + data += (sparse_header->chunk_hdr_sz - + sizeof(chunk_header_t)); + } + + chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz; + blkcnt = chunk_data_sz / info->blksz; + switch (chunk_header->chunk_type) + { + case CHUNK_TYPE_RAW: + if (chunk_header->total_sz != + (sparse_header->chunk_hdr_sz + chunk_data_sz)) + { + fastboot_fail( + "Bogus chunk size for chunk type Raw"); + return; + } + + if (blk + blkcnt > info->start + info->size) { + printf( + "%s: Request would exceed partition size!\n", + __func__); + fastboot_fail( + "Request would exceed partition size!"); + return; + } + + blks = dev_desc->block_write(dev_desc->dev, blk, blkcnt, + data); + if (blks != blkcnt) { + printf("%s: Write failed " LBAFU "\n", + __func__, blks); + fastboot_fail("flash write failure"); + return; + } + blk += blkcnt; + bytes_written += blkcnt * info->blksz; + total_blocks += chunk_header->chunk_sz; + data += chunk_data_sz; + break; + + case CHUNK_TYPE_FILL: + if (chunk_header->total_sz != + (sparse_header->chunk_hdr_sz + sizeof(uint32_t))) + { + fastboot_fail( + "Bogus chunk size for chunk type FILL"); + return; + } + + fill_buf = (uint32_t *) + memalign(ARCH_DMA_MINALIGN, + ROUNDUP(info->blksz, + ARCH_DMA_MINALIGN)); + if (!fill_buf) + { + fastboot_fail( + "Malloc failed for: CHUNK_TYPE_FILL"); + return; + } + + fill_val = *(uint32_t *)data; + data = (char *) data + sizeof(uint32_t); + + for (i = 0; i < (info->blksz / sizeof(fill_val)); i++) + fill_buf[i] = fill_val; + + if (blk + blkcnt > info->start + info->size) { + printf( + "%s: Request would exceed partition size!\n", + __func__); + fastboot_fail( + "Request would exceed partition size!"); + return; + } + + for (i = 0; i < blkcnt; i++) { + blks = dev_desc->block_write(dev_desc->dev, + blk, 1, fill_buf); + if (blks != 1) { + printf( + "%s: Write failed, block # " LBAFU "\n", + __func__, blkcnt); + fastboot_fail("flash write failure"); + free(fill_buf); + return; + } + blk++; + } + bytes_written += blkcnt * info->blksz; + total_blocks += chunk_data_sz / sparse_header->blk_sz; + + free(fill_buf); + break; + + case CHUNK_TYPE_DONT_CARE: + blk += blkcnt; + total_blocks += chunk_header->chunk_sz; + break; + + case CHUNK_TYPE_CRC32: + if (chunk_header->total_sz != + sparse_header->chunk_hdr_sz) + { + fastboot_fail( + "Bogus chunk size for chunk type Dont Care"); + return; + } + total_blocks += chunk_header->chunk_sz; + data += chunk_data_sz; + break; + + default: + printf("%s: Unknown chunk type: %x\n", __func__, + chunk_header->chunk_type); + fastboot_fail("Unknown chunk type"); + return; + } + } + + debug("Wrote %d blocks, expected to write %d blocks\n", + total_blocks, sparse_header->total_blks); + printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name); + + if (total_blocks != sparse_header->total_blks) + fastboot_fail("sparse image write failure"); + + fastboot_okay(""); + return; +} diff --git a/common/autoboot.c b/common/autoboot.c new file mode 100644 index 0000000000..c27cc2c751 --- /dev/null +++ b/common/autoboot.c @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_DELAY_STOP_STR 32 + +#ifndef DEBUG_BOOTKEYS +#define DEBUG_BOOTKEYS 0 +#endif +#define debug_bootkeys(fmt, args...) \ + debug_cond(DEBUG_BOOTKEYS, fmt, ##args) + +/* Stored value of bootdelay, used by autoboot_command() */ +static int stored_bootdelay; + +/*************************************************************************** + * Watch for 'delay' seconds for autoboot stop or autoboot delay string. + * returns: 0 - no key string, allow autoboot 1 - got key string, abort + */ +# if defined(CONFIG_AUTOBOOT_KEYED) +static int abortboot_keyed(int bootdelay) +{ + int abort = 0; + uint64_t etime = endtick(bootdelay); + struct { + char *str; + u_int len; + int retry; + } + delaykey[] = { + { .str = getenv("bootdelaykey"), .retry = 1 }, + { .str = getenv("bootdelaykey2"), .retry = 1 }, + { .str = getenv("bootstopkey"), .retry = 0 }, + { .str = getenv("bootstopkey2"), .retry = 0 }, + }; + + char presskey[MAX_DELAY_STOP_STR]; + u_int presskey_len = 0; + u_int presskey_max = 0; + u_int i; + +#ifndef CONFIG_ZERO_BOOTDELAY_CHECK + if (bootdelay == 0) + return 0; +#endif + +# ifdef CONFIG_AUTOBOOT_PROMPT + printf(CONFIG_AUTOBOOT_PROMPT); +# endif + +# ifdef CONFIG_AUTOBOOT_DELAY_STR + if (delaykey[0].str == NULL) + delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR; +# endif +# ifdef CONFIG_AUTOBOOT_DELAY_STR2 + if (delaykey[1].str == NULL) + delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2; +# endif +# ifdef CONFIG_AUTOBOOT_STOP_STR + if (delaykey[2].str == NULL) + delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR; +# endif +# ifdef CONFIG_AUTOBOOT_STOP_STR2 + if (delaykey[3].str == NULL) + delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2; +# endif + + for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) { + delaykey[i].len = delaykey[i].str == NULL ? + 0 : strlen(delaykey[i].str); + delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ? + MAX_DELAY_STOP_STR : delaykey[i].len; + + presskey_max = presskey_max > delaykey[i].len ? + presskey_max : delaykey[i].len; + + debug_bootkeys("%s key:<%s>\n", + delaykey[i].retry ? "delay" : "stop", + delaykey[i].str ? delaykey[i].str : "NULL"); + } + + /* In order to keep up with incoming data, check timeout only + * when catch up. + */ + do { + if (tstc()) { + if (presskey_len < presskey_max) { + presskey[presskey_len++] = getc(); + } else { + for (i = 0; i < presskey_max - 1; i++) + presskey[i] = presskey[i + 1]; + + presskey[i] = getc(); + } + } + + for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) { + if (delaykey[i].len > 0 && + presskey_len >= delaykey[i].len && + memcmp(presskey + presskey_len - + delaykey[i].len, delaykey[i].str, + delaykey[i].len) == 0) { + debug_bootkeys("got %skey\n", + delaykey[i].retry ? "delay" : + "stop"); + + /* don't retry auto boot */ + if (!delaykey[i].retry) + bootretry_dont_retry(); + abort = 1; + } + } + } while (!abort && get_ticks() <= etime); + + if (!abort) + debug_bootkeys("key timeout\n"); + +#ifdef CONFIG_SILENT_CONSOLE + if (abort) + gd->flags &= ~GD_FLG_SILENT; +#endif + + return abort; +} + +# else /* !defined(CONFIG_AUTOBOOT_KEYED) */ + +#ifdef CONFIG_MENUKEY +static int menukey; +#endif + +static int abortboot_normal(int bootdelay) +{ + int abort = 0; + unsigned long ts; + +#ifdef CONFIG_MENUPROMPT + printf(CONFIG_MENUPROMPT); +#else + if (bootdelay >= 0) + printf("Hit any key to stop autoboot: %2d ", bootdelay); +#endif + +#if defined CONFIG_ZERO_BOOTDELAY_CHECK + /* + * Check if key already pressed + * Don't check if bootdelay < 0 + */ + if (bootdelay >= 0) { + if (tstc()) { /* we got a key press */ + (void) getc(); /* consume input */ + puts("\b\b\b 0"); + abort = 1; /* don't auto boot */ + } + } +#endif + + while ((bootdelay > 0) && (!abort)) { + --bootdelay; + /* delay 1000 ms */ + ts = get_timer(0); + do { + if (tstc()) { /* we got a key press */ + abort = 1; /* don't auto boot */ + bootdelay = 0; /* no more delay */ +# ifdef CONFIG_MENUKEY + menukey = getc(); +# else + (void) getc(); /* consume input */ +# endif + break; + } + udelay(10000); + } while (!abort && get_timer(ts) < 1000); + + printf("\b\b\b%2d ", bootdelay); + } + + putc('\n'); + +#ifdef CONFIG_SILENT_CONSOLE + if (abort) + gd->flags &= ~GD_FLG_SILENT; +#endif + + return abort; +} +# endif /* CONFIG_AUTOBOOT_KEYED */ + +static int abortboot(int bootdelay) +{ +#ifdef CONFIG_AUTOBOOT_KEYED + return abortboot_keyed(bootdelay); +#else + return abortboot_normal(bootdelay); +#endif +} + +static void process_fdt_options(const void *blob) +{ +#if defined(CONFIG_OF_CONTROL) + ulong addr; + + /* Add an env variable to point to a kernel payload, if available */ + addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0); + if (addr) + setenv_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); + + /* Add an env variable to point to a root disk, if available */ + addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0); + if (addr) + setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); +#endif /* CONFIG_OF_CONTROL */ +} + +const char *bootdelay_process(void) +{ + char *s; + int bootdelay; +#ifdef CONFIG_BOOTCOUNT_LIMIT + unsigned long bootcount = 0; + unsigned long bootlimit = 0; +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + +#ifdef CONFIG_BOOTCOUNT_LIMIT + bootcount = bootcount_load(); + bootcount++; + bootcount_store(bootcount); + setenv_ulong("bootcount", bootcount); + bootlimit = getenv_ulong("bootlimit", 10, 0); +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + + s = getenv("bootdelay"); + bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; + +#ifdef CONFIG_OF_CONTROL + bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", + bootdelay); +#endif + + debug("### main_loop entered: bootdelay=%d\n\n", bootdelay); + +#if defined(CONFIG_MENU_SHOW) + bootdelay = menu_show(bootdelay); +#endif + bootretry_init_cmd_timeout(); + +#ifdef CONFIG_POST + if (gd->flags & GD_FLG_POSTFAIL) { + s = getenv("failbootcmd"); + } else +#endif /* CONFIG_POST */ +#ifdef CONFIG_BOOTCOUNT_LIMIT + if (bootlimit && (bootcount > bootlimit)) { + printf("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n", + (unsigned)bootlimit); + s = getenv("altbootcmd"); + } else +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + s = getenv("bootcmd"); + + process_fdt_options(gd->fdt_blob); + stored_bootdelay = bootdelay; + + return s; +} + +void autoboot_command(const char *s) +{ + debug("### main_loop: bootcmd=\"%s\"\n", s ? s : ""); + + if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) { +#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) + int prev = disable_ctrlc(1); /* disable Control C checking */ +#endif + + run_command_list(s, -1, 0); + +#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) + disable_ctrlc(prev); /* restore Control C checking */ +#endif + } + +#ifdef CONFIG_MENUKEY + if (menukey == CONFIG_MENUKEY) { + s = getenv("menucmd"); + if (s) + run_command_list(s, -1, 0); + } +#endif /* CONFIG_MENUKEY */ +} diff --git a/common/board_f.c b/common/board_f.c index 0ada1afe16..c172ea1acb 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #if defined(CONFIG_CMD_IDE) @@ -33,17 +34,18 @@ #ifdef CONFIG_MPC5xxx #include #endif +#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#include +#endif #include #include #include +#include #include #include #include #include -#ifdef CONFIG_MP -#include -#endif #include #ifdef CONFIG_X86 #include @@ -52,6 +54,7 @@ #ifdef CONFIG_SANDBOX #include #endif +#include #include /* @@ -78,25 +81,15 @@ DECLARE_GLOBAL_DATA_PTR; ************************************************************************ * May be supplied by boards if desired */ -inline void __coloured_LED_init(void) {} -void coloured_LED_init(void) - __attribute__((weak, alias("__coloured_LED_init"))); -inline void __red_led_on(void) {} -void red_led_on(void) __attribute__((weak, alias("__red_led_on"))); -inline void __red_led_off(void) {} -void red_led_off(void) __attribute__((weak, alias("__red_led_off"))); -inline void __green_led_on(void) {} -void green_led_on(void) __attribute__((weak, alias("__green_led_on"))); -inline void __green_led_off(void) {} -void green_led_off(void) __attribute__((weak, alias("__green_led_off"))); -inline void __yellow_led_on(void) {} -void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on"))); -inline void __yellow_led_off(void) {} -void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off"))); -inline void __blue_led_on(void) {} -void blue_led_on(void) __attribute__((weak, alias("__blue_led_on"))); -inline void __blue_led_off(void) {} -void blue_led_off(void) __attribute__((weak, alias("__blue_led_off"))); +__weak void coloured_LED_init(void) {} +__weak void red_led_on(void) {} +__weak void red_led_off(void) {} +__weak void green_led_on(void) {} +__weak void green_led_off(void) {} +__weak void yellow_led_on(void) {} +__weak void yellow_led_off(void) {} +__weak void blue_led_on(void) {} +__weak void blue_led_off(void) {} /* * Why is gd allocated a register? Prior to reloc it might be better to @@ -113,9 +106,14 @@ void blue_led_off(void) __attribute__((weak, alias("__blue_led_off"))); * Could the CONFIG_SPL_BUILD infection become a flag in gd? */ -#if defined(CONFIG_WATCHDOG) +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) static int init_func_watchdog_init(void) { +# if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \ + defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ + defined(CONFIG_SH)) + hw_watchdog_init(); +# endif puts(" Watchdog enabled\n"); WATCHDOG_RESET(); @@ -130,14 +128,11 @@ int init_func_watchdog_reset(void) } #endif /* CONFIG_WATCHDOG */ -void __board_add_ram_info(int use_default) +__weak void board_add_ram_info(int use_default) { /* please define platform specific board_add_ram_info() */ } -void board_add_ram_info(int) - __attribute__ ((weak, alias("__board_add_ram_info"))); - static int init_baud_rate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); @@ -147,17 +142,19 @@ static int init_baud_rate(void) static int display_text_info(void) { #ifndef CONFIG_SANDBOX - ulong bss_start, bss_end; + ulong bss_start, bss_end, text_base; -#ifdef CONFIG_SYS_SYM_OFFSETS - bss_start = _bss_start_ofs + _TEXT_BASE; - bss_end = _bss_end_ofs + _TEXT_BASE; -#else bss_start = (ulong)&__bss_start; bss_end = (ulong)&__bss_end; + +#ifdef CONFIG_SYS_TEXT_BASE + text_base = CONFIG_SYS_TEXT_BASE; +#else + text_base = CONFIG_SYS_MONITOR_BASE; #endif - debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n", - CONFIG_SYS_TEXT_BASE, bss_start, bss_end); + + debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", + text_base, bss_start, bss_end); #endif #ifdef CONFIG_MODEM_SUPPORT @@ -177,7 +174,7 @@ static int announce_dram_init(void) return 0; } -#ifdef CONFIG_PPC +#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) static int init_func_ram(void) { #ifdef CONFIG_BOARD_TYPES @@ -198,7 +195,7 @@ static int init_func_ram(void) static int show_dram_config(void) { - ulong size; + unsigned long long size; #ifdef CONFIG_NR_DRAM_BANKS int i; @@ -223,18 +220,7 @@ static int show_dram_config(void) return 0; } -ulong get_effective_memsize(void) -{ -#ifndef CONFIG_VERY_BIG_RAM - return gd->ram_size; -#else - /* limit stack to what we can reasonable map */ - return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); -#endif -} - -void __dram_init_banksize(void) +__weak void dram_init_banksize(void) { #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; @@ -242,14 +228,15 @@ void __dram_init_banksize(void) #endif } -void dram_init_banksize(void) - __attribute__((weak, alias("__dram_init_banksize"))); - #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) static int init_func_i2c(void) { puts("I2C: "); +#ifdef CONFIG_SYS_I2C + i2c_init_all(); +#else i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif puts("ready\n"); return 0; } @@ -275,10 +262,12 @@ static int zero_global_data(void) static int setup_mon_len(void) { -#ifdef CONFIG_SYS_SYM_OFFSETS - gd->mon_len = _bss_end_ofs; +#ifdef __ARM__ + gd->mon_len = (ulong)&__bss_end - (ulong)_start; #elif defined(CONFIG_SANDBOX) gd->mon_len = (ulong)&_end - (ulong)_init; +#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) + gd->mon_len = CONFIG_SYS_MONITOR_LEN; #else /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; @@ -291,47 +280,46 @@ __weak int arch_cpu_init(void) return 0; } -#ifdef CONFIG_OF_HOSTFILE - -#define CHECK(x) err = (x); if (err) goto failed; - -/* Create an empty device tree blob */ -static int make_empty_fdt(void *fdt) +__weak unsigned long get_timer_masked(void) { - int err; - - CHECK(fdt_create(fdt, 256)); - CHECK(fdt_finish_reservemap(fdt)); - CHECK(fdt_begin_node(fdt, "")); - CHECK(fdt_end_node(fdt)); - CHECK(fdt_finish(fdt)); - - return 0; -failed: - printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); - return -EACCES; + return get_timer(0); } +#ifdef CONFIG_OF_HOSTFILE + static int read_fdt_from_file(void) { struct sandbox_state *state = state_get_current(); + const char *fname = state->fdt_fname; void *blob; - int size; + loff_t size; int err; + int fd; blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0); if (!state->fdt_fname) { - err = make_empty_fdt(blob); + err = fdt_create_empty_tree(blob, 256); if (!err) goto done; - return err; + printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); + return -EINVAL; } - err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX); - if (err) + + err = os_get_filesize(fname, &size); + if (err < 0) { + printf("Failed to file FDT file '%s'\n", fname); return err; - size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0); - if (size < 0) + } + fd = os_open(fname, OS_O_RDONLY); + if (fd < 0) { + printf("Failed to open FDT file '%s'\n", fname); + return -EACCES; + } + if (os_read(fd, blob, size) != size) { + os_close(fd); return -EIO; + } + os_close(fd); done: gd->fdt_blob = blob; @@ -343,9 +331,10 @@ done: #ifdef CONFIG_SANDBOX static int setup_ram_buf(void) { - gd->arch.ram_buf = os_malloc(CONFIG_SYS_SDRAM_SIZE); - assert(gd->arch.ram_buf); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + struct sandbox_state *state = state_get_current(); + + gd->arch.ram_buf = state->ram_buf; + gd->ram_size = state->ram_size; return 0; } @@ -353,25 +342,23 @@ static int setup_ram_buf(void) static int setup_fdt(void) { -#ifdef CONFIG_OF_EMBED +#ifdef CONFIG_OF_CONTROL +# ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd->fdt_blob = _binary_dt_dtb_start; -#elif defined CONFIG_OF_SEPARATE + gd->fdt_blob = __dtb_dt_begin; +# elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ -# ifdef CONFIG_SYS_SYM_OFFSETS - gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE); -# else gd->fdt_blob = (ulong *)&_end; -# endif -#elif defined(CONFIG_OF_HOSTFILE) +# elif defined(CONFIG_OF_HOSTFILE) if (read_fdt_from_file()) { puts("Failed to read control FDT\n"); return -1; } -#endif +# endif /* Allow the early environment to override the fdt address */ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, (uintptr_t)gd->fdt_blob); +#endif return 0; } @@ -458,7 +445,7 @@ static int reserve_round_4k(void) static int reserve_mmu(void) { /* reserve TLB table */ - gd->arch.tlb_size = 4096 * 4; + gd->arch.tlb_size = PGTABLE_SIZE; gd->relocaddr -= gd->arch.tlb_size; /* round down to next 64 kB limit */ @@ -497,8 +484,9 @@ static int reserve_trace(void) return 0; } -#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \ - && !defined(CONFIG_ARM) && !defined(CONFIG_X86) +#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ + !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ + !defined(CONFIG_BLACKFIN) static int reserve_video(void) { /* reserve memory for video display (always full pages) */ @@ -543,11 +531,13 @@ static int reserve_malloc(void) /* (permanently) allocate a Board Info struct */ static int reserve_board(void) { - gd->start_addr_sp -= sizeof(bd_t); - gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); - memset(gd->bd, '\0', sizeof(bd_t)); - debug("Reserving %zu Bytes for Board Info at: %08lx\n", - sizeof(bd_t), gd->start_addr_sp); + if (!gd->bd) { + gd->start_addr_sp -= sizeof(bd_t); + gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); + memset(gd->bd, '\0', sizeof(bd_t)); + debug("Reserving %zu Bytes for Board Info at: %08lx\n", + sizeof(bd_t), gd->start_addr_sp); + } return 0; } #endif @@ -610,7 +600,7 @@ static int reserve_stacks(void) * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack() * to handle this and put in arch/xxx/lib/stack.c */ -# ifdef CONFIG_ARM +# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) # ifdef CONFIG_USE_IRQ gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", @@ -656,7 +646,7 @@ static int setup_board_part1(void) bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif -#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif @@ -728,14 +718,6 @@ static int init_post(void) } #endif -static int setup_baud_rate(void) -{ - /* Ick, can we get rid of this line? */ - gd->bd->bi_baudrate = gd->baudrate; - - return 0; -} - static int setup_dram_config(void) { /* Ram is board specific, so move it to board code ... */ @@ -756,7 +738,13 @@ static int reloc_fdt(void) static int setup_reloc(void) { +#ifdef CONFIG_SYS_TEXT_BASE +#ifndef CONFIG_ARM gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; +#else + gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; +#endif +#endif memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); debug("Relocation Offset is: %08lx\n", gd->reloc_off); @@ -768,7 +756,7 @@ static int setup_reloc(void) } /* ARM calls relocate_code from its crt0.S */ -#if !defined(CONFIG_ARM) +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) static int jump_to_copy(void) { @@ -788,8 +776,6 @@ static int jump_to_copy(void) * (CPU cache) */ board_init_f_r_trampoline(gd->start_addr_sp); -#elif defined(CONFIG_SANDBOX) - board_init_r(gd->new_gd, 0); #else relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); #endif @@ -806,33 +792,56 @@ static int mark_bootstage(void) return 0; } -static init_fnc_t init_sequence_f[] = { -#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ - !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ - !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86) - zero_global_data, +static int initf_malloc(void) +{ +#ifdef CONFIG_SYS_MALLOC_F_LEN + assert(gd->malloc_base); /* Set up by crt0.S */ + gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN; + gd->malloc_ptr = 0; +#endif + + return 0; +} + +static int initf_dm(void) +{ +#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) + int ret; + + ret = dm_init_and_scan(true); + if (ret) + return ret; #endif + + return 0; +} + +/* Architecture-specific memory reservation */ +__weak int reserve_arch(void) +{ + return 0; +} + +static init_fnc_t init_sequence_f[] = { #ifdef CONFIG_SANDBOX setup_ram_buf, #endif setup_mon_len, setup_fdt, +#ifdef CONFIG_TRACE trace_early_init, +#endif + initf_malloc, #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) /* TODO: can this go into arch_cpu_init()? */ probecpu, #endif arch_cpu_init, /* basic arch cpu dependent setup */ -#ifdef CONFIG_X86 - cpu_init_f, /* TODO(sjg@chromium.org): remove */ -# ifdef CONFIG_OF_CONTROL - find_fdt, /* TODO(sjg@chromium.org): remove */ -# endif -#endif mark_bootstage, #ifdef CONFIG_OF_CONTROL fdtdec_check_fdt, #endif + initf_dm, #if defined(CONFIG_BOARD_EARLY_INIT_F) board_early_init_f, #endif @@ -846,7 +855,7 @@ static init_fnc_t init_sequence_f[] = { /* TODO: can we rename this to timer_init()? */ init_timebase, #endif -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || defined(CONFIG_BLACKFIN) timer_init, /* initialize timer */ #endif #ifdef CONFIG_SYS_ALLOC_DPRAM @@ -879,24 +888,22 @@ static init_fnc_t init_sequence_f[] = { #endif display_options, /* say that we are here */ display_text_info, /* show debugging info if required */ -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) prt_8260_rsr, prt_8260_clks, -#endif /* CONFIG_8260 */ +#endif /* CONFIG_MPC8260 */ #if defined(CONFIG_MPC83xx) prt_83xx_rsr, #endif #ifdef CONFIG_PPC checkcpu, #endif -#if defined(CONFIG_DISPLAY_CPUINFO) print_cpuinfo, /* display cpu info (and speed) */ -#endif #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ #if defined(CONFIG_DISPLAY_BOARDINFO) - checkboard, /* display board info */ + show_board_info, #endif INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) @@ -908,17 +915,13 @@ static init_fnc_t init_sequence_f[] = { #endif #if defined(CONFIG_HARD_SPI) init_func_spi, -#endif -#ifdef CONFIG_X86 - dram_init_f, /* configure available RAM banks */ - calculate_relocation_address, #endif announce_dram_init, /* TODO: unify all these dram functions? */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_X86) dram_init, /* configure available RAM banks */ #endif -#ifdef CONFIG_PPC +#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) init_func_ram, #endif #ifdef CONFIG_POST @@ -947,6 +950,10 @@ static init_fnc_t init_sequence_f[] = { * - board info struct */ setup_dest_addr, +#if defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) + /* Blackfin u-boot monitor should be on top of the ram */ + reserve_uboot, +#endif #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) reserve_logbuffer, #endif @@ -963,11 +970,14 @@ static init_fnc_t init_sequence_f[] = { #endif reserve_trace, /* TODO: Why the dependency on CONFIG_8xx? */ -#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \ - && !defined(CONFIG_ARM) && !defined(CONFIG_X86) +#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ + !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ + !defined(CONFIG_BLACKFIN) reserve_video, #endif +#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) reserve_uboot, +#endif #ifndef CONFIG_SPL_BUILD reserve_malloc, reserve_board, @@ -975,6 +985,7 @@ static init_fnc_t init_sequence_f[] = { setup_machine, reserve_global_data, reserve_fdt, + reserve_arch, reserve_stacks, setup_dram_config, show_dram_config, @@ -983,7 +994,6 @@ static init_fnc_t init_sequence_f[] = { INIT_FUNC_WATCHDOG_RESET setup_board_part2, #endif - setup_baud_rate, display_new_sp, #ifdef CONFIG_SYS_EXTBDINFO setup_board_extra, @@ -991,7 +1001,12 @@ static init_fnc_t init_sequence_f[] = { INIT_FUNC_WATCHDOG_RESET reloc_fdt, setup_reloc, -#ifndef CONFIG_ARM +#ifdef CONFIG_X86 + copy_uboot_to_ram, + clear_bss, + do_elf_reloc_fixups, +#endif +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) jump_to_copy, #endif NULL, @@ -999,18 +1014,32 @@ static init_fnc_t init_sequence_f[] = { void board_init_f(ulong boot_flags) { -#ifndef CONFIG_X86 +#ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA + /* + * For some archtectures, global data is initialized and used before + * calling this function. The data should be preserved. For others, + * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack + * here to host global data until relocation. + */ gd_t data; gd = &data; + + /* + * Clear global data before it is accessed at debug print + * in initcall_run_list. Otherwise the debug print probably + * get the wrong vaule of gd->have_console. + */ + zero_global_data(); #endif gd->flags = boot_flags; + gd->have_console = 0; if (initcall_run_list(init_sequence_f)) hang(); -#ifndef CONFIG_ARM +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) /* NOTREACHED - jump_to_copy() does not return */ hang(); #endif @@ -1036,9 +1065,6 @@ void board_init_f(ulong boot_flags) */ static init_fnc_t init_sequence_f_r[] = { init_cache_f_r, - copy_uboot_to_ram, - clear_bss, - do_elf_reloc_fixups, NULL, }; diff --git a/common/board_info.c b/common/board_info.c new file mode 100644 index 0000000000..42d0641294 --- /dev/null +++ b/common/board_info.c @@ -0,0 +1,35 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int __weak checkboard(void) +{ + printf("Board: Unknown\n"); + return 0; +} + +/* + * If the root node of the DTB has a "model" property, show it. + * If CONFIG_OF_CONTROL is disabled or the "model" property is missing, + * fall back to checkboard(). + */ +int show_board_info(void) +{ +#ifdef CONFIG_OF_CONTROL + DECLARE_GLOBAL_DATA_PTR; + const char *model; + + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + + if (model) { + printf("Model: %s\n", model); + return 0; + } +#endif + + return checkboard(); +} diff --git a/common/board_r.c b/common/board_r.c index 86ca1cbbd4..68a9448b55 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -18,6 +18,7 @@ #ifdef CONFIG_HAS_DATAFLASH #include #endif +#include #include #include #if defined(CONFIG_CMD_IDE) @@ -51,13 +52,15 @@ #ifdef CONFIG_X86 #include #endif +#include #include +#include DECLARE_GLOBAL_DATA_PTR; ulong monitor_flash_len; -int __board_flash_wp_on(void) +__weak int board_flash_wp_on(void) { /* * Most flashes can't be detected when write protection is enabled, @@ -67,16 +70,10 @@ int __board_flash_wp_on(void) return 0; } -int board_flash_wp_on(void) - __attribute__ ((weak, alias("__board_flash_wp_on"))); - -void __cpu_secondary_init_r(void) +__weak void cpu_secondary_init_r(void) { } -void cpu_secondary_init_r(void) - __attribute__ ((weak, alias("__cpu_secondary_init_r"))); - static int initr_secondary_cpu(void) { /* @@ -102,7 +99,8 @@ static int initr_trace(void) static int initr_reloc(void) { - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + /* tell others: relocation done */ + gd->flags |= GD_FLG_RELOC | GD_FLG_FULL_MALLOC_INIT; bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); return 0; @@ -128,9 +126,9 @@ __weak int fixup_cpu(void) static int initr_reloc_global_data(void) { -#ifdef CONFIG_SYS_SYM_OFFSETS - monitor_flash_len = _end_ofs; -#elif !defined(CONFIG_SANDBOX) +#ifdef __ARM__ + monitor_flash_len = _end - __image_copy_start; +#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2) monitor_flash_len = (ulong)&__init_end - gd->relocaddr; #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) @@ -256,6 +254,10 @@ static int initr_malloc(void) { ulong malloc_start; +#ifdef CONFIG_SYS_MALLOC_F_LEN + debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr, + gd->malloc_ptr / 1024); +#endif /* The malloc area is immediately below the monitor copy in DRAM */ malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN; mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN), @@ -263,6 +265,24 @@ static int initr_malloc(void) return 0; } +#ifdef CONFIG_SYS_NONCACHED_MEMORY +static int initr_noncached(void) +{ + noncached_init(); + return 0; +} +#endif + +#ifdef CONFIG_DM +static int initr_dm(void) +{ + /* Save the pre-reloc driver model and start a new one */ + gd->dm_root_f = gd->dm_root; + gd->dm_root = NULL; + return dm_init_and_scan(false); +} +#endif + __weak int power_init_board(void) { return 0; @@ -279,26 +299,14 @@ static int initr_flash(void) { ulong flash_size = 0; bd_t *bd = gd->bd; - int ok; puts("Flash: "); - if (board_flash_wp_on()) { + if (board_flash_wp_on()) printf("Uninitialized - Write Protect On\n"); - /* Since WP is on, we can't find real size. Set to 0 */ - ok = 1; - } else { + else flash_size = flash_init(); - ok = flash_size > 0; - } - if (!ok) { - puts("*** failed ***\n"); -#ifdef CONFIG_PPC - /* Why does PPC do this? */ - hang(); -#endif - return -1; - } + print_size(flash_size, ""); #ifdef CONFIG_SYS_FLASH_CHECKSUM /* @@ -337,7 +345,7 @@ static int initr_flash(void) } #endif -#ifdef CONFIG_PPC +#if defined(CONFIG_PPC) && !defined(CONFIG_DM_SPI) static int initr_spi(void) { /* PPC does this here */ @@ -353,7 +361,7 @@ static int initr_spi(void) #ifdef CONFIG_CMD_NAND /* go init the NAND */ -int initr_nand(void) +static int initr_nand(void) { puts("NAND: "); nand_init(); @@ -363,7 +371,7 @@ int initr_nand(void) #if defined(CONFIG_CMD_ONENAND) /* go init the NAND */ -int initr_onenand(void) +static int initr_onenand(void) { puts("NAND: "); onenand_init(); @@ -372,7 +380,7 @@ int initr_onenand(void) #endif #ifdef CONFIG_GENERIC_MMC -int initr_mmc(void) +static int initr_mmc(void) { puts("MMC: "); mmc_initialize(gd->bd); @@ -381,7 +389,7 @@ int initr_mmc(void) #endif #ifdef CONFIG_HAS_DATAFLASH -int initr_dataflash(void) +static int initr_dataflash(void) { AT91F_DataflashInit(); dataflash_print_info(); @@ -442,24 +450,6 @@ static int initr_env(void) return 0; } -#ifdef CONFIG_HERMES -static int initr_hermes(void) -{ - if ((gd->board_type >> 16) == 2) - gd->bd->bi_ethspeed = gd->board_type & 0xFFFF; - else - gd->bd->bi_ethspeed = 0xFFFF; - return 0; -} - -static int initr_hermes_start(void) -{ - if (gd->bd->bi_ethspeed != 0xFFFF) - hermes_start_lxt980((int) gd->bd->bi_ethspeed); - return 0; -} -#endif - #ifdef CONFIG_SC3 /* TODO: with new initcalls, move this into the driver */ extern void sc3_read_eeprom(void); @@ -486,21 +476,6 @@ static int initr_api(void) } #endif -#ifdef CONFIG_DISPLAY_BOARDINFO_LATE -static int show_model_r(void) -{ - /* Put this here so it appears on the LCD, now it is ready */ -# ifdef CONFIG_OF_CONTROL - const char *model; - - model = (char *)fdt_getprop(gd->fdt_blob, 0, "model", NULL); - printf("Model: %s\n", model ? model : ""); -# else - checkboard(); -# endif -} -#endif - /* enable exceptions */ #ifdef CONFIG_ARM static int initr_enable_interrupts(void) @@ -557,21 +532,19 @@ static int initr_status_led(void) #if defined(CONFIG_CMD_SCSI) static int initr_scsi(void) { - /* Not supported properly on ARM yet */ -#ifndef CONFIG_ARM puts("SCSI: "); scsi_init(); -#endif return 0; } -#endif /* CONFIG_CMD_NET */ +#endif #if defined(CONFIG_CMD_DOC) static int initr_doc(void) { puts("DOC: "); doc_init(); + return 0; } #endif @@ -648,7 +621,7 @@ int initr_mem(void) /* Also take the logbuffer into account (pram is in kB) */ pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; # endif - sprintf(memsz, "%ldk", (gd->ram_size / 1024) - pram); + sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram)); setenv("mem", memsz); return 0; @@ -673,17 +646,6 @@ static int initr_kbd(void) } #endif -#ifdef CONFIG_MODEM_SUPPORT -static int initr_modem(void) -{ - /* TODO: with new initcalls, move this into the driver */ - extern int do_mdm_init; - - do_mdm_init = gd->do_mdm_init; - return 0; -} -#endif - static int run_main_loop(void) { #ifdef CONFIG_SANDBOX @@ -710,6 +672,21 @@ init_fnc_t init_sequence_r[] = { /* TODO: could x86/PPC have this also perhaps? */ #ifdef CONFIG_ARM initr_caches, +#endif + initr_reloc_global_data, +#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) + initr_unlock_ram_in_cache, +#endif + initr_barrier, + initr_malloc, +#ifdef CONFIG_SYS_NONCACHED_MEMORY + initr_noncached, +#endif + bootstage_relocate, +#ifdef CONFIG_DM + initr_dm, +#endif +#ifdef CONFIG_ARM board_init, /* Setup chipselects */ #endif /* @@ -721,7 +698,7 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CLOCKS set_cpu_clk_info, /* Setup clock information */ #endif - initr_reloc_global_data, + stdio_init_tables, initr_serial, initr_announce, INIT_FUNC_WATCHDOG_RESET @@ -745,9 +722,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_SYS_DELAYED_ICACHE initr_icache_enable, #endif -#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) - initr_unlock_ram_in_cache, -#endif #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do early PCI configuration _before_ the flash gets initialised, @@ -758,9 +732,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_WINBOND_83C553 initr_w83c553f, #endif - initr_barrier, - initr_malloc, - bootstage_relocate, #ifdef CONFIG_ARCH_EARLY_INIT_R arch_early_init_r, #endif @@ -769,7 +740,7 @@ init_fnc_t init_sequence_r[] = { initr_flash, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_PPC) || defined(CONFIG_X86) +#if defined(CONFIG_PPC) /* initialize higher level parts of CPU like time base and timers */ cpu_init_r, #endif @@ -797,9 +768,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_SC3 initr_sc3_read_eeprom, #endif -#ifdef CONFIG_HERMES - initr_hermes, -#endif #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) mac_read_from_eeprom, #endif @@ -810,33 +778,27 @@ init_fnc_t init_sequence_r[] = { */ initr_pci, #endif - stdio_init, + stdio_add_devices, initr_jumptable, #ifdef CONFIG_API initr_api, #endif console_init_r, /* fully init console as a device */ #ifdef CONFIG_DISPLAY_BOARDINFO_LATE - show_model_r, + show_board_info, #endif #ifdef CONFIG_ARCH_MISC_INIT arch_misc_init, /* miscellaneous arch-dependent init */ #endif #ifdef CONFIG_MISC_INIT_R misc_init_r, /* miscellaneous platform-dependent init */ -#endif -#ifdef CONFIG_HERMES - initr_hermes_start, #endif INIT_FUNC_WATCHDOG_RESET #ifdef CONFIG_CMD_KGDB initr_kgdb, -#endif -#ifdef CONFIG_X86 - board_early_init_r, #endif interrupt_init, -#if defined(CONFIG_ARM) || defined(CONFIG_x86) +#if defined(CONFIG_ARM) initr_enable_interrupts, #endif #ifdef CONFIG_X86 @@ -894,18 +856,25 @@ init_fnc_t init_sequence_r[] = { #endif #ifdef CONFIG_PS2KBD initr_kbd, -#endif -#ifdef CONFIG_MODEM_SUPPORT - initr_modem, #endif run_main_loop, }; void board_init_r(gd_t *new_gd, ulong dest_addr) { -#ifndef CONFIG_X86 +#ifdef CONFIG_NEEDS_MANUAL_RELOC + int i; +#endif + +#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) gd = new_gd; #endif + +#ifdef CONFIG_NEEDS_MANUAL_RELOC + for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++) + init_sequence_r[i] += gd->reloc_off; +#endif + if (initcall_run_list(init_sequence_r)) hang(); diff --git a/common/bootm.c b/common/bootm.c new file mode 100644 index 0000000000..e2dc16486b --- /dev/null +++ b/common/bootm.c @@ -0,0 +1,942 @@ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef USE_HOSTCC +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_CMD_USB) +#include +#endif +#else +#include "mkimage.h" +#endif + +#include +#include +#include + +#ifndef CONFIG_SYS_BOOTM_LEN +/* use 8MByte as default max gunzip size */ +#define CONFIG_SYS_BOOTM_LEN 0x800000 +#endif + +#define IH_INITRD_ARCH IH_ARCH_DEFAULT + +#ifndef USE_HOSTCC + +DECLARE_GLOBAL_DATA_PTR; + +static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[], bootm_headers_t *images, + ulong *os_data, ulong *os_len); + +#ifdef CONFIG_LMB +static void boot_start_lmb(bootm_headers_t *images) +{ + ulong mem_start; + phys_size_t mem_size; + + lmb_init(&images->lmb); + + mem_start = getenv_bootm_low(); + mem_size = getenv_bootm_size(); + + lmb_add(&images->lmb, (phys_addr_t)mem_start, mem_size); + + arch_lmb_reserve(&images->lmb); + board_lmb_reserve(&images->lmb); +} +#else +#define lmb_reserve(lmb, base, size) +static inline void boot_start_lmb(bootm_headers_t *images) { } +#endif + +static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + memset((void *)&images, 0, sizeof(images)); + images.verify = getenv_yesno("verify"); + + boot_start_lmb(&images); + + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_START, "bootm_start"); + images.state = BOOTM_STATE_START; + + return 0; +} + +static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + const void *os_hdr; + bool ep_found = false; + int ret; + + /* get kernel image header, start address and length */ + os_hdr = boot_get_kernel(cmdtp, flag, argc, argv, + &images, &images.os.image_start, &images.os.image_len); + if (images.os.image_len == 0) { + puts("ERROR: can't get kernel image!\n"); + return 1; + } + + /* get image parameters */ + switch (genimg_get_format(os_hdr)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) + case IMAGE_FORMAT_LEGACY: + images.os.type = image_get_type(os_hdr); + images.os.comp = image_get_comp(os_hdr); + images.os.os = image_get_os(os_hdr); + + images.os.end = image_get_image_end(os_hdr); + images.os.load = image_get_load(os_hdr); + images.os.arch = image_get_arch(os_hdr); + break; +#endif +#if defined(CONFIG_FIT) + case IMAGE_FORMAT_FIT: + if (fit_image_get_type(images.fit_hdr_os, + images.fit_noffset_os, + &images.os.type)) { + puts("Can't get image type!\n"); + bootstage_error(BOOTSTAGE_ID_FIT_TYPE); + return 1; + } + + if (fit_image_get_comp(images.fit_hdr_os, + images.fit_noffset_os, + &images.os.comp)) { + puts("Can't get image compression!\n"); + bootstage_error(BOOTSTAGE_ID_FIT_COMPRESSION); + return 1; + } + + if (fit_image_get_os(images.fit_hdr_os, images.fit_noffset_os, + &images.os.os)) { + puts("Can't get image OS!\n"); + bootstage_error(BOOTSTAGE_ID_FIT_OS); + return 1; + } + + if (fit_image_get_arch(images.fit_hdr_os, + images.fit_noffset_os, + &images.os.arch)) { + puts("Can't get image ARCH!\n"); + return 1; + } + + images.os.end = fit_get_end(images.fit_hdr_os); + + if (fit_image_get_load(images.fit_hdr_os, images.fit_noffset_os, + &images.os.load)) { + puts("Can't get image load address!\n"); + bootstage_error(BOOTSTAGE_ID_FIT_LOADADDR); + return 1; + } + break; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + case IMAGE_FORMAT_ANDROID: + images.os.type = IH_TYPE_KERNEL; + images.os.comp = IH_COMP_NONE; + images.os.os = IH_OS_LINUX; + + images.os.end = android_image_get_end(os_hdr); + images.os.load = android_image_get_kload(os_hdr); + images.ep = images.os.load; + ep_found = true; + break; +#endif + default: + puts("ERROR: unknown image format type!\n"); + return 1; + } + + /* If we have a valid setup.bin, we will use that for entry (x86) */ + if (images.os.arch == IH_ARCH_I386 || + images.os.arch == IH_ARCH_X86_64) { + ulong len; + + ret = boot_get_setup(&images, IH_ARCH_I386, &images.ep, &len); + if (ret < 0 && ret != -ENOENT) { + puts("Could not find a valid setup.bin for x86\n"); + return 1; + } + /* Kernel entry point is the setup.bin */ + } else if (images.legacy_hdr_valid) { + images.ep = image_get_ep(&images.legacy_hdr_os_copy); +#if defined(CONFIG_FIT) + } else if (images.fit_uname_os) { + int ret; + + ret = fit_image_get_entry(images.fit_hdr_os, + images.fit_noffset_os, &images.ep); + if (ret) { + puts("Can't get entry point property!\n"); + return 1; + } +#endif + } else if (!ep_found) { + puts("Could not find kernel entry point!\n"); + return 1; + } + + if (images.os.type == IH_TYPE_KERNEL_NOLOAD) { + images.os.load = images.os.image_start; + images.ep += images.os.load; + } + + images.os.start = (ulong)os_hdr; + + return 0; +} + +static int bootm_find_ramdisk(int flag, int argc, char * const argv[]) +{ + int ret; + + /* find ramdisk */ + ret = boot_get_ramdisk(argc, argv, &images, IH_INITRD_ARCH, + &images.rd_start, &images.rd_end); + if (ret) { + puts("Ramdisk image is corrupt or invalid\n"); + return 1; + } + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) +static int bootm_find_fdt(int flag, int argc, char * const argv[]) +{ + int ret; + + /* find flattened device tree */ + ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images, + &images.ft_addr, &images.ft_len); + if (ret) { + puts("Could not find a valid device tree\n"); + return 1; + } + + set_working_fdt_addr(images.ft_addr); + + return 0; +} +#endif + +int bootm_find_ramdisk_fdt(int flag, int argc, char * const argv[]) +{ + if (bootm_find_ramdisk(flag, argc, argv)) + return 1; + +#if defined(CONFIG_OF_LIBFDT) + if (bootm_find_fdt(flag, argc, argv)) + return 1; +#endif + + return 0; +} + +static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (((images.os.type == IH_TYPE_KERNEL) || + (images.os.type == IH_TYPE_KERNEL_NOLOAD) || + (images.os.type == IH_TYPE_MULTI)) && + (images.os.os == IH_OS_LINUX || + images.os.os == IH_OS_VXWORKS)) + return bootm_find_ramdisk_fdt(flag, argc, argv); + + return 0; +} +#endif /* USE_HOSTC */ + +/** + * print_decomp_msg() - Print a suitable decompression/loading message + * + * @type: OS type (IH_OS_...) + * @comp_type: Compression type being used (IH_COMP_...) + * @is_xip: true if the load address matches the image start + */ +static void print_decomp_msg(int comp_type, int type, bool is_xip) +{ + const char *name = genimg_get_type_name(type); + + if (comp_type == IH_COMP_NONE) + printf(" %s %s ... ", is_xip ? "XIP" : "Loading", name); + else + printf(" Uncompressing %s ... ", name); +} + +/** + * handle_decomp_error() - display a decompression error + * + * This function tries to produce a useful message. In the case where the + * uncompressed size is the same as the available space, we can assume that + * the image is too large for the buffer. + * + * @comp_type: Compression type being used (IH_COMP_...) + * @uncomp_size: Number of bytes uncompressed + * @unc_len: Amount of space available for decompression + * @ret: Error code to report + * @return BOOTM_ERR_RESET, indicating that the board must be reset + */ +static int handle_decomp_error(int comp_type, size_t uncomp_size, + size_t unc_len, int ret) +{ + const char *name = genimg_get_comp_name(comp_type); + + if (uncomp_size >= unc_len) + printf("Image too large: increase CONFIG_SYS_BOOTM_LEN\n"); + else + printf("%s: uncompress error %d\n", name, ret); + + /* + * The decompression routines are now safe, so will not write beyond + * their bounds. Probably it is not necessary to reset, but maintain + * the current behaviour for now. + */ + printf("Must RESET board to recover\n"); +#ifndef USE_HOSTCC + bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); +#endif + + return BOOTM_ERR_RESET; +} + +int bootm_decomp_image(int comp, ulong load, ulong image_start, int type, + void *load_buf, void *image_buf, ulong image_len, + uint unc_len, ulong *load_end) +{ + int ret = 0; + + *load_end = load; + print_decomp_msg(comp, type, load == image_start); + + /* + * Load the image to the right place, decompressing if needed. After + * this, image_len will be set to the number of uncompressed bytes + * loaded, ret will be non-zero on error. + */ + switch (comp) { + case IH_COMP_NONE: + if (load == image_start) + break; + if (image_len <= unc_len) + memmove_wd(load_buf, image_buf, image_len, CHUNKSZ); + else + ret = 1; + break; +#ifdef CONFIG_GZIP + case IH_COMP_GZIP: { + ret = gunzip(load_buf, unc_len, image_buf, &image_len); + break; + } +#endif /* CONFIG_GZIP */ +#ifdef CONFIG_BZIP2 + case IH_COMP_BZIP2: { + uint size = unc_len; + + /* + * If we've got less than 4 MB of malloc() space, + * use slower decompression algorithm which requires + * at most 2300 KB of memory. + */ + ret = BZ2_bzBuffToBuffDecompress(load_buf, &size, + image_buf, image_len, + CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); + image_len = size; + break; + } +#endif /* CONFIG_BZIP2 */ +#ifdef CONFIG_LZMA + case IH_COMP_LZMA: { + SizeT lzma_len = unc_len; + + ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len, + image_buf, image_len); + image_len = lzma_len; + break; + } +#endif /* CONFIG_LZMA */ +#ifdef CONFIG_LZO + case IH_COMP_LZO: { + size_t size = unc_len; + + ret = lzop_decompress(image_buf, image_len, load_buf, &size); + image_len = size; + break; + } +#endif /* CONFIG_LZO */ + default: + printf("Unimplemented compression type %d\n", comp); + return BOOTM_ERR_UNIMPLEMENTED; + } + + if (ret) + return handle_decomp_error(comp, image_len, unc_len, ret); + *load_end = load + image_len; + + puts("OK\n"); + + return 0; +} + +#ifndef USE_HOSTCC +static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, + int boot_progress) +{ + image_info_t os = images->os; + ulong load = os.load; + ulong blob_start = os.start; + ulong blob_end = os.end; + ulong image_start = os.image_start; + ulong image_len = os.image_len; + bool no_overlap; + void *load_buf, *image_buf; + int err; + + load_buf = map_sysmem(load, 0); + image_buf = map_sysmem(os.image_start, image_len); + err = bootm_decomp_image(os.comp, load, os.image_start, os.type, + load_buf, image_buf, image_len, + CONFIG_SYS_BOOTM_LEN, load_end); + if (err) { + bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); + return err; + } + flush_cache(load, (*load_end - load) * sizeof(ulong)); + + debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end); + bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED); + + no_overlap = (os.comp == IH_COMP_NONE && load == image_start); + + if (!no_overlap && (load < blob_end) && (*load_end > blob_start)) { + debug("images.os.start = 0x%lX, images.os.end = 0x%lx\n", + blob_start, blob_end); + debug("images.os.load = 0x%lx, load_end = 0x%lx\n", load, + *load_end); + + /* Check what type of image this is. */ + if (images->legacy_hdr_valid) { + if (image_get_type(&images->legacy_hdr_os_copy) + == IH_TYPE_MULTI) + puts("WARNING: legacy format multi component image overwritten\n"); + return BOOTM_ERR_OVERLAP; + } else { + puts("ERROR: new format image overwritten - must RESET the board to recover\n"); + bootstage_error(BOOTSTAGE_ID_OVERWRITTEN); + return BOOTM_ERR_RESET; + } + } + + return 0; +} + +/** + * bootm_disable_interrupts() - Disable interrupts in preparation for load/boot + * + * @return interrupt flag (0 if interrupts were disabled, non-zero if they were + * enabled) + */ +ulong bootm_disable_interrupts(void) +{ + ulong iflag; + + /* + * We have reached the point of no return: we are going to + * overwrite all exception vector code, so we cannot easily + * recover from any failures any more... + */ + iflag = disable_interrupts(); +#ifdef CONFIG_NETCONSOLE + /* Stop the ethernet stack if NetConsole could have left it up */ + eth_halt(); + eth_unregister(eth_get_dev()); +#endif + +#if defined(CONFIG_CMD_USB) + /* + * turn off USB to prevent the host controller from writing to the + * SDRAM while Linux is booting. This could happen (at least for OHCI + * controller), because the HCCA (Host Controller Communication Area) + * lies within the SDRAM and the host controller writes continously to + * this area (as busmaster!). The HccaFrameNumber is for example + * updated every 1 ms within the HCCA structure in SDRAM! For more + * details see the OpenHCI specification. + */ + usb_stop(); +#endif + return iflag; +} + +#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) + +#define CONSOLE_ARG "console=" +#define CONSOLE_ARG_LEN (sizeof(CONSOLE_ARG) - 1) + +static void fixup_silent_linux(void) +{ + char *buf; + const char *env_val; + char *cmdline = getenv("bootargs"); + int want_silent; + + /* + * Only fix cmdline when requested. The environment variable can be: + * + * no - we never fixup + * yes - we always fixup + * unset - we rely on the console silent flag + */ + want_silent = getenv_yesno("silent_linux"); + if (want_silent == 0) + return; + else if (want_silent == -1 && !(gd->flags & GD_FLG_SILENT)) + return; + + debug("before silent fix-up: %s\n", cmdline); + if (cmdline && (cmdline[0] != '\0')) { + char *start = strstr(cmdline, CONSOLE_ARG); + + /* Allocate space for maximum possible new command line */ + buf = malloc(strlen(cmdline) + 1 + CONSOLE_ARG_LEN + 1); + if (!buf) { + debug("%s: out of memory\n", __func__); + return; + } + + if (start) { + char *end = strchr(start, ' '); + int num_start_bytes = start - cmdline + CONSOLE_ARG_LEN; + + strncpy(buf, cmdline, num_start_bytes); + if (end) + strcpy(buf + num_start_bytes, end); + else + buf[num_start_bytes] = '\0'; + } else { + sprintf(buf, "%s %s", cmdline, CONSOLE_ARG); + } + env_val = buf; + } else { + buf = NULL; + env_val = CONSOLE_ARG; + } + + setenv("bootargs", env_val); + debug("after silent fix-up: %s\n", env_val); + free(buf); +} +#endif /* CONFIG_SILENT_CONSOLE */ + +/** + * Execute selected states of the bootm command. + * + * Note the arguments to this state must be the first argument, Any 'bootm' + * or sub-command arguments must have already been taken. + * + * Note that if states contains more than one flag it MUST contain + * BOOTM_STATE_START, since this handles and consumes the command line args. + * + * Also note that aside from boot_os_fn functions and bootm_load_os no other + * functions we store the return value of in 'ret' may use a negative return + * value, without special handling. + * + * @param cmdtp Pointer to bootm command table entry + * @param flag Command flags (CMD_FLAG_...) + * @param argc Number of subcommand arguments (0 = no arguments) + * @param argv Arguments + * @param states Mask containing states to run (BOOTM_STATE_...) + * @param images Image header information + * @param boot_progress 1 to show boot progress, 0 to not do this + * @return 0 if ok, something else on error. Some errors will cause this + * function to perform a reboot! If states contains BOOTM_STATE_OS_GO + * then the intent is to boot an OS, so this function will not return + * unless the image type is standalone. + */ +int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int states, bootm_headers_t *images, int boot_progress) +{ + boot_os_fn *boot_fn; + ulong iflag = 0; + int ret = 0, need_boot_fn; + + images->state |= states; + + /* + * Work through the states and see how far we get. We stop on + * any error. + */ + if (states & BOOTM_STATE_START) + ret = bootm_start(cmdtp, flag, argc, argv); + + if (!ret && (states & BOOTM_STATE_FINDOS)) + ret = bootm_find_os(cmdtp, flag, argc, argv); + + if (!ret && (states & BOOTM_STATE_FINDOTHER)) { + ret = bootm_find_other(cmdtp, flag, argc, argv); + argc = 0; /* consume the args */ + } + + /* Load the OS */ + if (!ret && (states & BOOTM_STATE_LOADOS)) { + ulong load_end; + + iflag = bootm_disable_interrupts(); + ret = bootm_load_os(images, &load_end, 0); + if (ret == 0) + lmb_reserve(&images->lmb, images->os.load, + (load_end - images->os.load)); + else if (ret && ret != BOOTM_ERR_OVERLAP) + goto err; + else if (ret == BOOTM_ERR_OVERLAP) + ret = 0; +#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) + if (images->os.os == IH_OS_LINUX) + fixup_silent_linux(); +#endif + } + + /* Relocate the ramdisk */ +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH + if (!ret && (states & BOOTM_STATE_RAMDISK)) { + ulong rd_len = images->rd_end - images->rd_start; + + ret = boot_ramdisk_high(&images->lmb, images->rd_start, + rd_len, &images->initrd_start, &images->initrd_end); + if (!ret) { + setenv_hex("initrd_start", images->initrd_start); + setenv_hex("initrd_end", images->initrd_end); + } + } +#endif +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB) + if (!ret && (states & BOOTM_STATE_FDT)) { + boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); + ret = boot_relocate_fdt(&images->lmb, &images->ft_addr, + &images->ft_len); + } +#endif + + /* From now on, we need the OS boot function */ + if (ret) + return ret; + boot_fn = bootm_os_get_boot_func(images->os.os); + need_boot_fn = states & (BOOTM_STATE_OS_CMDLINE | + BOOTM_STATE_OS_BD_T | BOOTM_STATE_OS_PREP | + BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO); + if (boot_fn == NULL && need_boot_fn) { + if (iflag) + enable_interrupts(); + printf("ERROR: booting os '%s' (%d) is not supported\n", + genimg_get_os_name(images->os.os), images->os.os); + bootstage_error(BOOTSTAGE_ID_CHECK_BOOT_OS); + return 1; + } + + /* Call various other states that are not generally used */ + if (!ret && (states & BOOTM_STATE_OS_CMDLINE)) + ret = boot_fn(BOOTM_STATE_OS_CMDLINE, argc, argv, images); + if (!ret && (states & BOOTM_STATE_OS_BD_T)) + ret = boot_fn(BOOTM_STATE_OS_BD_T, argc, argv, images); + if (!ret && (states & BOOTM_STATE_OS_PREP)) + ret = boot_fn(BOOTM_STATE_OS_PREP, argc, argv, images); + +#ifdef CONFIG_TRACE + /* Pretend to run the OS, then run a user command */ + if (!ret && (states & BOOTM_STATE_OS_FAKE_GO)) { + char *cmd_list = getenv("fakegocmd"); + + ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_FAKE_GO, + images, boot_fn); + if (!ret && cmd_list) + ret = run_command_list(cmd_list, -1, flag); + } +#endif + + /* Check for unsupported subcommand. */ + if (ret) { + puts("subcommand not supported\n"); + return ret; + } + + /* Now run the OS! We hope this doesn't return */ + if (!ret && (states & BOOTM_STATE_OS_GO)) + ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_GO, + images, boot_fn); + + /* Deal with any fallout */ +err: + if (iflag) + enable_interrupts(); + + if (ret == BOOTM_ERR_UNIMPLEMENTED) + bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL); + else if (ret == BOOTM_ERR_RESET) + do_reset(cmdtp, flag, argc, argv); + + return ret; +} + +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) +/** + * image_get_kernel - verify legacy format kernel image + * @img_addr: in RAM address of the legacy format image to be verified + * @verify: data CRC verification flag + * + * image_get_kernel() verifies legacy image integrity and returns pointer to + * legacy image header if image verification was completed successfully. + * + * returns: + * pointer to a legacy image header if valid image was found + * otherwise return NULL + */ +static image_header_t *image_get_kernel(ulong img_addr, int verify) +{ + image_header_t *hdr = (image_header_t *)img_addr; + + if (!image_check_magic(hdr)) { + puts("Bad Magic Number\n"); + bootstage_error(BOOTSTAGE_ID_CHECK_MAGIC); + return NULL; + } + bootstage_mark(BOOTSTAGE_ID_CHECK_HEADER); + + if (!image_check_hcrc(hdr)) { + puts("Bad Header Checksum\n"); + bootstage_error(BOOTSTAGE_ID_CHECK_HEADER); + return NULL; + } + + bootstage_mark(BOOTSTAGE_ID_CHECK_CHECKSUM); + image_print_contents(hdr); + + if (verify) { + puts(" Verifying Checksum ... "); + if (!image_check_dcrc(hdr)) { + printf("Bad Data CRC\n"); + bootstage_error(BOOTSTAGE_ID_CHECK_CHECKSUM); + return NULL; + } + puts("OK\n"); + } + bootstage_mark(BOOTSTAGE_ID_CHECK_ARCH); + + if (!image_check_target_arch(hdr)) { + printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr)); + bootstage_error(BOOTSTAGE_ID_CHECK_ARCH); + return NULL; + } + return hdr; +} +#endif + +/** + * boot_get_kernel - find kernel image + * @os_data: pointer to a ulong variable, will hold os data start address + * @os_len: pointer to a ulong variable, will hold os data length + * + * boot_get_kernel() tries to find a kernel image, verifies its integrity + * and locates kernel data. + * + * returns: + * pointer to image header if valid image was found, plus kernel start + * address and length, otherwise NULL + */ +static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[], bootm_headers_t *images, + ulong *os_data, ulong *os_len) +{ +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) + image_header_t *hdr; +#endif + ulong img_addr; + const void *buf; + const char *fit_uname_config = NULL; + const char *fit_uname_kernel = NULL; +#if defined(CONFIG_FIT) + int os_noffset; +#endif + + img_addr = genimg_get_kernel_addr_fit(argc < 1 ? NULL : argv[0], + &fit_uname_config, + &fit_uname_kernel); + + bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC); + + /* copy from dataflash if needed */ + img_addr = genimg_get_image(img_addr); + + /* check image type, for FIT images get FIT kernel node */ + *os_data = *os_len = 0; + buf = map_sysmem(img_addr, 0); + switch (genimg_get_format(buf)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) + case IMAGE_FORMAT_LEGACY: + printf("## Booting kernel from Legacy Image at %08lx ...\n", + img_addr); + hdr = image_get_kernel(img_addr, images->verify); + if (!hdr) + return NULL; + bootstage_mark(BOOTSTAGE_ID_CHECK_IMAGETYPE); + + /* get os_data and os_len */ + switch (image_get_type(hdr)) { + case IH_TYPE_KERNEL: + case IH_TYPE_KERNEL_NOLOAD: + *os_data = image_get_data(hdr); + *os_len = image_get_data_size(hdr); + break; + case IH_TYPE_MULTI: + image_multi_getimg(hdr, 0, os_data, os_len); + break; + case IH_TYPE_STANDALONE: + *os_data = image_get_data(hdr); + *os_len = image_get_data_size(hdr); + break; + default: + printf("Wrong Image Type for %s command\n", + cmdtp->name); + bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE); + return NULL; + } + + /* + * copy image header to allow for image overwrites during + * kernel decompression. + */ + memmove(&images->legacy_hdr_os_copy, hdr, + sizeof(image_header_t)); + + /* save pointer to image header */ + images->legacy_hdr_os = hdr; + + images->legacy_hdr_valid = 1; + bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE); + break; +#endif +#if defined(CONFIG_FIT) + case IMAGE_FORMAT_FIT: + os_noffset = fit_image_load(images, img_addr, + &fit_uname_kernel, &fit_uname_config, + IH_ARCH_DEFAULT, IH_TYPE_KERNEL, + BOOTSTAGE_ID_FIT_KERNEL_START, + FIT_LOAD_IGNORED, os_data, os_len); + if (os_noffset < 0) + return NULL; + + images->fit_hdr_os = map_sysmem(img_addr, 0); + images->fit_uname_os = fit_uname_kernel; + images->fit_uname_cfg = fit_uname_config; + images->fit_noffset_os = os_noffset; + break; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + case IMAGE_FORMAT_ANDROID: + printf("## Booting Android Image at 0x%08lx ...\n", img_addr); + if (android_image_get_kernel(buf, images->verify, + os_data, os_len)) + return NULL; + break; +#endif + default: + printf("Wrong Image Format for %s command\n", cmdtp->name); + bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO); + return NULL; + } + + debug(" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n", + *os_data, *os_len, *os_len); + + return buf; +} +#else /* USE_HOSTCC */ + +void memmove_wd(void *to, void *from, size_t len, ulong chunksz) +{ + memmove(to, from, len); +} + +static int bootm_host_load_image(const void *fit, int req_image_type) +{ + const char *fit_uname_config = NULL; + ulong data, len; + bootm_headers_t images; + int noffset; + ulong load_end; + uint8_t image_type; + uint8_t imape_comp; + void *load_buf; + int ret; + + memset(&images, '\0', sizeof(images)); + images.verify = 1; + noffset = fit_image_load(&images, (ulong)fit, + NULL, &fit_uname_config, + IH_ARCH_DEFAULT, req_image_type, -1, + FIT_LOAD_IGNORED, &data, &len); + if (noffset < 0) + return noffset; + if (fit_image_get_type(fit, noffset, &image_type)) { + puts("Can't get image type!\n"); + return -EINVAL; + } + + if (fit_image_get_comp(fit, noffset, &imape_comp)) { + puts("Can't get image compression!\n"); + return -EINVAL; + } + + /* Allow the image to expand by a factor of 4, should be safe */ + load_buf = malloc((1 << 20) + len * 4); + ret = bootm_decomp_image(imape_comp, 0, data, image_type, load_buf, + (void *)data, len, CONFIG_SYS_BOOTM_LEN, + &load_end); + free(load_buf); + + if (ret && ret != BOOTM_ERR_UNIMPLEMENTED) + return ret; + + return 0; +} + +int bootm_host_load_images(const void *fit, int cfg_noffset) +{ + static uint8_t image_types[] = { + IH_TYPE_KERNEL, + IH_TYPE_FLATDT, + IH_TYPE_RAMDISK, + }; + int err = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(image_types); i++) { + int ret; + + ret = bootm_host_load_image(fit, image_types[i]); + if (!err && ret && ret != -ENOENT) + err = ret; + } + + /* Return the first error we found */ + return err; +} + +#endif /* ndef USE_HOSTCC */ diff --git a/common/bootm_os.c b/common/bootm_os.c new file mode 100644 index 0000000000..72477f0b81 --- /dev/null +++ b/common/bootm_os.c @@ -0,0 +1,508 @@ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int do_bootm_standalone(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + char *s; + int (*appl)(int, char *const[]); + + /* Don't start if "autostart" is set to "no" */ + s = getenv("autostart"); + if ((s != NULL) && !strcmp(s, "no")) { + setenv_hex("filesize", images->os.image_len); + return 0; + } + appl = (int (*)(int, char * const []))images->ep; + appl(argc, argv); + return 0; +} + +/*******************************************************************/ +/* OS booting routines */ +/*******************************************************************/ + +#if defined(CONFIG_BOOTM_NETBSD) || defined(CONFIG_BOOTM_PLAN9) +static void copy_args(char *dest, int argc, char * const argv[], char delim) +{ + int i; + + for (i = 0; i < argc; i++) { + if (i > 0) + *dest++ = delim; + strcpy(dest, argv[i]); + dest += strlen(argv[i]); + } +} +#endif + +#ifdef CONFIG_BOOTM_NETBSD +static int do_bootm_netbsd(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*loader)(bd_t *, image_header_t *, char *, char *); + image_header_t *os_hdr, *hdr; + ulong kernel_data, kernel_len; + char *consdev; + char *cmdline; + + if (flag != BOOTM_STATE_OS_GO) + return 0; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("NetBSD"); + return 1; + } +#endif + hdr = images->legacy_hdr_os; + + /* + * Booting a (NetBSD) kernel image + * + * This process is pretty similar to a standalone application: + * The (first part of an multi-) image must be a stage-2 loader, + * which in turn is responsible for loading & invoking the actual + * kernel. The only differences are the parameters being passed: + * besides the board info strucure, the loader expects a command + * line, the name of the console device, and (optionally) the + * address of the original image header. + */ + os_hdr = NULL; + if (image_check_type(&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) { + image_multi_getimg(hdr, 1, &kernel_data, &kernel_len); + if (kernel_len) + os_hdr = hdr; + } + + consdev = ""; +#if defined(CONFIG_8xx_CONS_SMC1) + consdev = "smc1"; +#elif defined(CONFIG_8xx_CONS_SMC2) + consdev = "smc2"; +#elif defined(CONFIG_8xx_CONS_SCC2) + consdev = "scc2"; +#elif defined(CONFIG_8xx_CONS_SCC3) + consdev = "scc3"; +#endif + + if (argc > 0) { + ulong len; + int i; + + for (i = 0, len = 0; i < argc; i += 1) + len += strlen(argv[i]) + 1; + cmdline = malloc(len); + copy_args(cmdline, argc, argv, ' '); + } else { + cmdline = getenv("bootargs"); + if (cmdline == NULL) + cmdline = ""; + } + + loader = (void (*)(bd_t *, image_header_t *, char *, char *))images->ep; + + printf("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n", + (ulong)loader); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + /* + * NetBSD Stage-2 Loader Parameters: + * arg[0]: pointer to board info data + * arg[1]: image load address + * arg[2]: char pointer to the console device to use + * arg[3]: char pointer to the boot arguments + */ + (*loader)(gd->bd, os_hdr, consdev, cmdline); + + return 1; +} +#endif /* CONFIG_BOOTM_NETBSD*/ + +#ifdef CONFIG_LYNXKDI +static int do_bootm_lynxkdi(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + image_header_t *hdr = &images->legacy_hdr_os_copy; + + if (flag != BOOTM_STATE_OS_GO) + return 0; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("Lynx"); + return 1; + } +#endif + + lynxkdi_boot((image_header_t *)hdr); + + return 1; +} +#endif /* CONFIG_LYNXKDI */ + +#ifdef CONFIG_BOOTM_RTEMS +static int do_bootm_rtems(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(bd_t *); + + if (flag != BOOTM_STATE_OS_GO) + return 0; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("RTEMS"); + return 1; + } +#endif + + entry_point = (void (*)(bd_t *))images->ep; + + printf("## Transferring control to RTEMS (at address %08lx) ...\n", + (ulong)entry_point); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + /* + * RTEMS Parameters: + * r3: ptr to board info data + */ + (*entry_point)(gd->bd); + + return 1; +} +#endif /* CONFIG_BOOTM_RTEMS */ + +#if defined(CONFIG_BOOTM_OSE) +static int do_bootm_ose(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + + if (flag != BOOTM_STATE_OS_GO) + return 0; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("OSE"); + return 1; + } +#endif + + entry_point = (void (*)(void))images->ep; + + printf("## Transferring control to OSE (at address %08lx) ...\n", + (ulong)entry_point); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + /* + * OSE Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif /* CONFIG_BOOTM_OSE */ + +#if defined(CONFIG_BOOTM_PLAN9) +static int do_bootm_plan9(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + char *s; + + if (flag != BOOTM_STATE_OS_GO) + return 0; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("Plan 9"); + return 1; + } +#endif + + /* See README.plan9 */ + s = getenv("confaddr"); + if (s != NULL) { + char *confaddr = (char *)simple_strtoul(s, NULL, 16); + + if (argc > 0) { + copy_args(confaddr, argc, argv, '\n'); + } else { + s = getenv("bootargs"); + if (s != NULL) + strcpy(confaddr, s); + } + } + + entry_point = (void (*)(void))images->ep; + + printf("## Transferring control to Plan 9 (at address %08lx) ...\n", + (ulong)entry_point); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + /* + * Plan 9 Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif /* CONFIG_BOOTM_PLAN9 */ + +#if defined(CONFIG_BOOTM_VXWORKS) && \ + (defined(CONFIG_PPC) || defined(CONFIG_ARM)) + +void do_bootvx_fdt(bootm_headers_t *images) +{ +#if defined(CONFIG_OF_LIBFDT) + int ret; + char *bootline; + ulong of_size = images->ft_len; + char **of_flat_tree = &images->ft_addr; + struct lmb *lmb = &images->lmb; + + if (*of_flat_tree) { + boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); + + ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); + if (ret) + return; + + ret = fdt_add_subnode(*of_flat_tree, 0, "chosen"); + if ((ret >= 0 || ret == -FDT_ERR_EXISTS)) { + bootline = getenv("bootargs"); + if (bootline) { + ret = fdt_find_and_setprop(*of_flat_tree, + "/chosen", "bootargs", + bootline, + strlen(bootline) + 1, 1); + if (ret < 0) { + printf("## ERROR: %s : %s\n", __func__, + fdt_strerror(ret)); + return; + } + } + } else { + printf("## ERROR: %s : %s\n", __func__, + fdt_strerror(ret)); + return; + } + } +#endif + + boot_prep_vxworks(images); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + +#if defined(CONFIG_OF_LIBFDT) + printf("## Starting vxWorks at 0x%08lx, device tree at 0x%08lx ...\n", + (ulong)images->ep, (ulong)*of_flat_tree); +#else + printf("## Starting vxWorks at 0x%08lx\n", (ulong)images->ep); +#endif + + boot_jump_vxworks(images); + + puts("## vxWorks terminated\n"); +} + +static int do_bootm_vxworks(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + if (flag != BOOTM_STATE_OS_GO) + return 0; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("VxWorks"); + return 1; + } +#endif + + do_bootvx_fdt(images); + + return 1; +} +#endif + +#if defined(CONFIG_CMD_ELF) +static int do_bootm_qnxelf(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + char *local_args[2]; + char str[16]; + + if (flag != BOOTM_STATE_OS_GO) + return 0; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("QNX"); + return 1; + } +#endif + + sprintf(str, "%lx", images->ep); /* write entry-point into string */ + local_args[0] = argv[0]; + local_args[1] = str; /* and provide it via the arguments */ + do_bootelf(NULL, 0, 2, local_args); + + return 1; +} +#endif + +#ifdef CONFIG_INTEGRITY +static int do_bootm_integrity(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + + if (flag != BOOTM_STATE_OS_GO) + return 0; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("INTEGRITY"); + return 1; + } +#endif + + entry_point = (void (*)(void))images->ep; + + printf("## Transferring control to INTEGRITY (at address %08lx) ...\n", + (ulong)entry_point); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + /* + * INTEGRITY Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif + +#ifdef CONFIG_BOOTM_OPENRTOS +static int do_bootm_openrtos(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + + if (flag != BOOTM_STATE_OS_GO) + return 0; + + entry_point = (void (*)(void))images->ep; + + printf("## Transferring control to OpenRTOS (at address %08lx) ...\n", + (ulong)entry_point); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + /* + * OpenRTOS Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif + +static boot_os_fn *boot_os[] = { + [IH_OS_U_BOOT] = do_bootm_standalone, +#ifdef CONFIG_BOOTM_LINUX + [IH_OS_LINUX] = do_bootm_linux, +#endif +#ifdef CONFIG_BOOTM_NETBSD + [IH_OS_NETBSD] = do_bootm_netbsd, +#endif +#ifdef CONFIG_LYNXKDI + [IH_OS_LYNXOS] = do_bootm_lynxkdi, +#endif +#ifdef CONFIG_BOOTM_RTEMS + [IH_OS_RTEMS] = do_bootm_rtems, +#endif +#if defined(CONFIG_BOOTM_OSE) + [IH_OS_OSE] = do_bootm_ose, +#endif +#if defined(CONFIG_BOOTM_PLAN9) + [IH_OS_PLAN9] = do_bootm_plan9, +#endif +#if defined(CONFIG_BOOTM_VXWORKS) && \ + (defined(CONFIG_PPC) || defined(CONFIG_ARM)) + [IH_OS_VXWORKS] = do_bootm_vxworks, +#endif +#if defined(CONFIG_CMD_ELF) + [IH_OS_QNX] = do_bootm_qnxelf, +#endif +#ifdef CONFIG_INTEGRITY + [IH_OS_INTEGRITY] = do_bootm_integrity, +#endif +#ifdef CONFIG_BOOTM_OPENRTOS + [IH_OS_OPENRTOS] = do_bootm_openrtos, +#endif +}; + +/* Allow for arch specific config before we boot */ +__weak void arch_preboot_os(void) +{ + /* please define platform specific arch_preboot_os() */ +} + +int boot_selected_os(int argc, char * const argv[], int state, + bootm_headers_t *images, boot_os_fn *boot_fn) +{ + arch_preboot_os(); + boot_fn(state, argc, argv, images); + + /* Stand-alone may return when 'autostart' is 'no' */ + if (images->os.type == IH_TYPE_STANDALONE || + state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */ + return 0; + bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED); +#ifdef DEBUG + puts("\n## Control returned to monitor - resetting...\n"); +#endif + return BOOTM_ERR_RESET; +} + +boot_os_fn *bootm_os_get_boot_func(int os) +{ +#ifdef CONFIG_NEEDS_MANUAL_RELOC + static bool relocated; + + if (!relocated) { + int i; + + /* relocate boot function table */ + for (i = 0; i < ARRAY_SIZE(boot_os); i++) + if (boot_os[i] != NULL) + boot_os[i] += gd->reloc_off; + + relocated = true; + } +#endif + return boot_os[os]; +} diff --git a/common/bootretry.c b/common/bootretry.c new file mode 100644 index 0000000000..2d82798cd0 --- /dev/null +++ b/common/bootretry.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifndef CONFIG_BOOT_RETRY_MIN +#define CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME +#endif + +static uint64_t endtime; /* must be set, default is instant timeout */ +static int retry_time = -1; /* -1 so can call readline before main_loop */ + +/*************************************************************************** + * initialize command line timeout + */ +void bootretry_init_cmd_timeout(void) +{ + char *s = getenv("bootretry"); + + if (s != NULL) + retry_time = (int)simple_strtol(s, NULL, 10); + else + retry_time = CONFIG_BOOT_RETRY_TIME; + + if (retry_time >= 0 && retry_time < CONFIG_BOOT_RETRY_MIN) + retry_time = CONFIG_BOOT_RETRY_MIN; +} + +/*************************************************************************** + * reset command line timeout to retry_time seconds + */ +void bootretry_reset_cmd_timeout(void) +{ + endtime = endtick(retry_time); +} + +int bootretry_tstc_timeout(void) +{ + while (!tstc()) { /* while no incoming data */ + if (retry_time >= 0 && get_ticks() > endtime) + return -ETIMEDOUT; + WATCHDOG_RESET(); + } + + return 0; +} + +void bootretry_dont_retry(void) +{ + retry_time = -1; +} diff --git a/common/bouncebuf.c b/common/bouncebuf.c index 9eece6d758..054d9e0302 100644 --- a/common/bouncebuf.c +++ b/common/bouncebuf.c @@ -23,7 +23,7 @@ static int addr_aligned(struct bounce_buffer *state) /* Check if length is aligned */ if (state->len != state->len_aligned) { - debug("Unaligned buffer length %d\n", state->len); + debug("Unaligned buffer length %zu\n", state->len); return 0; } diff --git a/common/cli.c b/common/cli.c new file mode 100644 index 0000000000..075ae9dc4a --- /dev/null +++ b/common/cli.c @@ -0,0 +1,221 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Run a command using the selected parser. + * + * @param cmd Command to run + * @param flag Execution flags (CMD_FLAG_...) + * @return 0 on success, or != 0 on error. + */ +int run_command(const char *cmd, int flag) +{ +#ifndef CONFIG_SYS_HUSH_PARSER + /* + * cli_run_command can return 0 or 1 for success, so clean up + * its result. + */ + if (cli_simple_run_command(cmd, flag) == -1) + return 1; + + return 0; +#else + int hush_flags = FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP; + + if (flag & CMD_FLAG_ENV) + hush_flags |= FLAG_CONT_ON_NEWLINE; + return parse_string_outer(cmd, hush_flags); +#endif +} + +/* + * Run a command using the selected parser, and check if it is repeatable. + * + * @param cmd Command to run + * @param flag Execution flags (CMD_FLAG_...) + * @return 0 (not repeatable) or 1 (repeatable) on success, -1 on error. + */ +int run_command_repeatable(const char *cmd, int flag) +{ +#ifndef CONFIG_SYS_HUSH_PARSER + return cli_simple_run_command(cmd, flag); +#else + /* + * parse_string_outer() returns 1 for failure, so clean up + * its result. + */ + if (parse_string_outer(cmd, + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP)) + return -1; + + return 0; +#endif +} + +int run_command_list(const char *cmd, int len, int flag) +{ + int need_buff = 1; + char *buff = (char *)cmd; /* cast away const */ + int rcode = 0; + + if (len == -1) { + len = strlen(cmd); +#ifdef CONFIG_SYS_HUSH_PARSER + /* hush will never change our string */ + need_buff = 0; +#else + /* the built-in parser will change our string if it sees \n */ + need_buff = strchr(cmd, '\n') != NULL; +#endif + } + if (need_buff) { + buff = malloc(len + 1); + if (!buff) + return 1; + memcpy(buff, cmd, len); + buff[len] = '\0'; + } +#ifdef CONFIG_SYS_HUSH_PARSER + rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON); +#else + /* + * This function will overwrite any \n it sees with a \0, which + * is why it can't work with a const char *. Here we are making + * using of internal knowledge of this function, to avoid always + * doing a malloc() which is actually required only in a case that + * is pretty rare. + */ + rcode = cli_simple_run_command_list(buff, flag); + if (need_buff) + free(buff); +#endif + + return rcode; +} + +/****************************************************************************/ + +#if defined(CONFIG_CMD_RUN) +int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + + if (argc < 2) + return CMD_RET_USAGE; + + for (i = 1; i < argc; ++i) { + char *arg; + + arg = getenv(argv[i]); + if (arg == NULL) { + printf("## Error: \"%s\" not defined\n", argv[i]); + return 1; + } + + if (run_command(arg, flag | CMD_FLAG_ENV) != 0) + return 1; + } + return 0; +} +#endif + +#ifdef CONFIG_OF_CONTROL +bool cli_process_fdt(const char **cmdp) +{ + /* Allow the fdt to override the boot command */ + char *env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd"); + if (env) + *cmdp = env; + /* + * If the bootsecure option was chosen, use secure_boot_cmd(). + * Always use 'env' in this case, since bootsecure requres that the + * bootcmd was specified in the FDT too. + */ + return fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0) != 0; +} + +/* + * Runs the given boot command securely. Specifically: + * - Doesn't run the command with the shell (run_command or parse_string_outer), + * since that's a lot of code surface that an attacker might exploit. + * Because of this, we don't do any argument parsing--the secure boot command + * has to be a full-fledged u-boot command. + * - Doesn't check for keypresses before booting, since that could be a + * security hole; also disables Ctrl-C. + * - Doesn't allow the command to return. + * + * Upon any failures, this function will drop into an infinite loop after + * printing the error message to console. + */ +void cli_secure_boot_cmd(const char *cmd) +{ + cmd_tbl_t *cmdtp; + int rc; + + if (!cmd) { + printf("## Error: Secure boot command not specified\n"); + goto err; + } + + /* Disable Ctrl-C just in case some command is used that checks it. */ + disable_ctrlc(1); + + /* Find the command directly. */ + cmdtp = find_cmd(cmd); + if (!cmdtp) { + printf("## Error: \"%s\" not defined\n", cmd); + goto err; + } + + /* Run the command, forcing no flags and faking argc and argv. */ + rc = (cmdtp->cmd)(cmdtp, 0, 1, (char **)&cmd); + + /* Shouldn't ever return from boot command. */ + printf("## Error: \"%s\" returned (code %d)\n", cmd, rc); + +err: + /* + * Not a whole lot to do here. Rebooting won't help much, since we'll + * just end up right back here. Just loop. + */ + hang(); +} +#endif /* CONFIG_OF_CONTROL */ + +void cli_loop(void) +{ +#ifdef CONFIG_SYS_HUSH_PARSER + parse_file_outer(); + /* This point is never reached */ + for (;;); +#else + cli_simple_loop(); +#endif /*CONFIG_SYS_HUSH_PARSER*/ +} + +void cli_init(void) +{ +#ifdef CONFIG_SYS_HUSH_PARSER + u_boot_hush_start(); +#endif + +#if defined(CONFIG_HUSH_INIT_VAR) + hush_init_var(); +#endif +} diff --git a/common/cli_hush.c b/common/cli_hush.c new file mode 100644 index 0000000000..296542f4c2 --- /dev/null +++ b/common/cli_hush.c @@ -0,0 +1,3689 @@ +/* + * sh.c -- a prototype Bourne shell grammar parser + * Intended to follow the original Thompson and Ritchie + * "small and simple is beautiful" philosophy, which + * incidentally is a good match to today's BusyBox. + * + * Copyright (C) 2000,2001 Larry Doolittle + * + * Credits: + * The parser routines proper are all original material, first + * written Dec 2000 and Jan 2001 by Larry Doolittle. + * The execution engine, the builtins, and much of the underlying + * support has been adapted from busybox-0.49pre's lash, + * which is Copyright (C) 2000 by Lineo, Inc., and + * written by Erik Andersen , . + * That, in turn, is based in part on ladsh.c, by Michael K. Johnson and + * Erik W. Troan, which they placed in the public domain. I don't know + * how much of the Johnson/Troan code has survived the repeated rewrites. + * Other credits: + * b_addchr() derived from similar w_addchar function in glibc-2.2 + * setup_redirect(), redirect_opt_num(), and big chunks of main() + * and many builtins derived from contributions by Erik Andersen + * miscellaneous bugfixes from Matt Kraai + * + * There are two big (and related) architecture differences between + * this parser and the lash parser. One is that this version is + * actually designed from the ground up to understand nearly all + * of the Bourne grammar. The second, consequential change is that + * the parser and input reader have been turned inside out. Now, + * the parser is in control, and asks for input as needed. The old + * way had the input reader in control, and it asked for parsing to + * take place as needed. The new way makes it much easier to properly + * handle the recursion implicit in the various substitutions, especially + * across continuation lines. + * + * Bash grammar not implemented: (how many of these were in original sh?) + * $@ (those sure look like weird quoting rules) + * $_ + * ! negation operator for pipes + * &> and >& redirection of stdout+stderr + * Brace Expansion + * Tilde Expansion + * fancy forms of Parameter Expansion + * aliases + * Arithmetic Expansion + * <(list) and >(list) Process Substitution + * reserved words: case, esac, select, function + * Here Documents ( << word ) + * Functions + * Major bugs: + * job handling woefully incomplete and buggy + * reserved word execution woefully incomplete and buggy + * to-do: + * port selected bugfixes from post-0.49 busybox lash - done? + * finish implementing reserved words: for, while, until, do, done + * change { and } from special chars to reserved words + * builtins: break, continue, eval, return, set, trap, ulimit + * test magic exec + * handle children going into background + * clean up recognition of null pipes + * check setting of global_argc and global_argv + * control-C handling, probably with longjmp + * follow IFS rules more precisely, including update semantics + * figure out what to do with backslash-newline + * explain why we use signal instead of sigaction + * propagate syntax errors, die on resource errors? + * continuation lines, both explicit and implicit - done? + * memory leak finding and plugging - done? + * more testing, especially quoting rules and redirection + * document how quoting rules not precisely followed for variable assignments + * maybe change map[] to use 2-bit entries + * (eventually) remove all the printf's + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define __U_BOOT__ +#ifdef __U_BOOT__ +#include /* malloc, free, realloc*/ +#include /* isalpha, isdigit */ +#include /* readline */ +#include +#include +#include +#include /* find_cmd */ +#ifndef CONFIG_SYS_PROMPT_HUSH_PS2 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif +#endif +#ifndef __U_BOOT__ +#include /* isalpha, isdigit */ +#include /* getpid */ +#include /* getenv, atoi */ +#include /* strchr */ +#include /* popen etc. */ +#include /* glob, of course */ +#include /* va_list */ +#include +#include +#include /* should be pretty obvious */ + +#include /* ulimit */ +#include +#include +#include + +/* #include */ + +#if 1 +#include "busybox.h" +#include "cmdedit.h" +#else +#define applet_name "hush" +#include "standalone.h" +#define hush_main main +#undef CONFIG_FEATURE_SH_FANCY_PROMPT +#define BB_BANNER +#endif +#endif +#define SPECIAL_VAR_SYMBOL 03 +#define SUBSTED_VAR_SYMBOL 04 +#ifndef __U_BOOT__ +#define FLAG_EXIT_FROM_LOOP 1 +#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ +#define FLAG_REPARSING (1 << 2) /* >= 2nd pass */ + +#endif + +#ifdef __U_BOOT__ +DECLARE_GLOBAL_DATA_PTR; + +#define EXIT_SUCCESS 0 +#define EOF -1 +#define syntax() syntax_err() +#define xstrdup strdup +#define error_msg printf +#else +typedef enum { + REDIRECT_INPUT = 1, + REDIRECT_OVERWRITE = 2, + REDIRECT_APPEND = 3, + REDIRECT_HEREIS = 4, + REDIRECT_IO = 5 +} redir_type; + +/* The descrip member of this structure is only used to make debugging + * output pretty */ +struct {int mode; int default_fd; char *descrip;} redir_table[] = { + { 0, 0, "()" }, + { O_RDONLY, 0, "<" }, + { O_CREAT|O_TRUNC|O_WRONLY, 1, ">" }, + { O_CREAT|O_APPEND|O_WRONLY, 1, ">>" }, + { O_RDONLY, -1, "<<" }, + { O_RDWR, 1, "<>" } +}; +#endif + +typedef enum { + PIPE_SEQ = 1, + PIPE_AND = 2, + PIPE_OR = 3, + PIPE_BG = 4, +} pipe_style; + +/* might eventually control execution */ +typedef enum { + RES_NONE = 0, + RES_IF = 1, + RES_THEN = 2, + RES_ELIF = 3, + RES_ELSE = 4, + RES_FI = 5, + RES_FOR = 6, + RES_WHILE = 7, + RES_UNTIL = 8, + RES_DO = 9, + RES_DONE = 10, + RES_XXXX = 11, + RES_IN = 12, + RES_SNTX = 13 +} reserved_style; +#define FLAG_END (1<, but protected with __USE_GNU */ +#endif + +/* "globals" within this file */ +static uchar *ifs; +static char map[256]; +#ifndef __U_BOOT__ +static int fake_mode; +static int interactive; +static struct close_me *close_me_head; +static const char *cwd; +static struct pipe *job_list; +static unsigned int last_bg_pid; +static unsigned int last_jobid; +static unsigned int shell_terminal; +static char *PS1; +static char *PS2; +struct variables shell_ver = { "HUSH_VERSION", "0.01", 1, 1, 0 }; +struct variables *top_vars = &shell_ver; +#else +static int flag_repeat = 0; +static int do_repeat = 0; +static struct variables *top_vars = NULL ; +#endif /*__U_BOOT__ */ + +#define B_CHUNK (100) +#define B_NOSPAC 1 + +typedef struct { + char *data; + int length; + int maxlen; + int quote; + int nonnull; +} o_string; +#define NULL_O_STRING {NULL,0,0,0,0} +/* used for initialization: + o_string foo = NULL_O_STRING; */ + +/* I can almost use ordinary FILE *. Is open_memstream() universally + * available? Where is it documented? */ +struct in_str { + const char *p; +#ifndef __U_BOOT__ + char peek_buf[2]; +#endif + int __promptme; + int promptmode; +#ifndef __U_BOOT__ + FILE *file; +#endif + int (*get) (struct in_str *); + int (*peek) (struct in_str *); +}; +#define b_getch(input) ((input)->get(input)) +#define b_peek(input) ((input)->peek(input)) + +#ifndef __U_BOOT__ +#define JOB_STATUS_FORMAT "[%d] %-22s %.40s\n" + +struct built_in_command { + char *cmd; /* name */ + char *descr; /* description */ + int (*function) (struct child_prog *); /* function ptr */ +}; +#endif + +/* define DEBUG_SHELL for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG_SHELL +#endif + +/* This should be in utility.c */ +#ifdef DEBUG_SHELL +#ifndef __U_BOOT__ +static void debug_printf(const char *format, ...) +{ + va_list args; + va_start(args, format); + vfprintf(stderr, format, args); + va_end(args); +} +#else +#define debug_printf(fmt,args...) printf (fmt ,##args) +#endif +#else +static inline void debug_printf(const char *format, ...) { } +#endif +#define final_printf debug_printf + +#ifdef __U_BOOT__ +static void syntax_err(void) { + printf("syntax error\n"); +} +#else +static void __syntax(char *file, int line) { + error_msg("syntax error %s:%d", file, line); +} +#define syntax() __syntax(__FILE__, __LINE__) +#endif + +#ifdef __U_BOOT__ +static void *xmalloc(size_t size); +static void *xrealloc(void *ptr, size_t size); +#else +/* Index of subroutines: */ +/* function prototypes for builtins */ +static int builtin_cd(struct child_prog *child); +static int builtin_env(struct child_prog *child); +static int builtin_eval(struct child_prog *child); +static int builtin_exec(struct child_prog *child); +static int builtin_exit(struct child_prog *child); +static int builtin_export(struct child_prog *child); +static int builtin_fg_bg(struct child_prog *child); +static int builtin_help(struct child_prog *child); +static int builtin_jobs(struct child_prog *child); +static int builtin_pwd(struct child_prog *child); +static int builtin_read(struct child_prog *child); +static int builtin_set(struct child_prog *child); +static int builtin_shift(struct child_prog *child); +static int builtin_source(struct child_prog *child); +static int builtin_umask(struct child_prog *child); +static int builtin_unset(struct child_prog *child); +static int builtin_not_written(struct child_prog *child); +#endif +/* o_string manipulation: */ +static int b_check_space(o_string *o, int len); +static int b_addchr(o_string *o, int ch); +static void b_reset(o_string *o); +static int b_addqchr(o_string *o, int ch, int quote); +#ifndef __U_BOOT__ +static int b_adduint(o_string *o, unsigned int i); +#endif +/* in_str manipulations: */ +static int static_get(struct in_str *i); +static int static_peek(struct in_str *i); +static int file_get(struct in_str *i); +static int file_peek(struct in_str *i); +#ifndef __U_BOOT__ +static void setup_file_in_str(struct in_str *i, FILE *f); +#else +static void setup_file_in_str(struct in_str *i); +#endif +static void setup_string_in_str(struct in_str *i, const char *s); +#ifndef __U_BOOT__ +/* close_me manipulations: */ +static void mark_open(int fd); +static void mark_closed(int fd); +static void close_all(void); +#endif +/* "run" the final data structures: */ +static char *indenter(int i); +static int free_pipe_list(struct pipe *head, int indent); +static int free_pipe(struct pipe *pi, int indent); +/* really run the final data structures: */ +#ifndef __U_BOOT__ +static int setup_redirects(struct child_prog *prog, int squirrel[]); +#endif +static int run_list_real(struct pipe *pi); +#ifndef __U_BOOT__ +static void pseudo_exec(struct child_prog *child) __attribute__ ((noreturn)); +#endif +static int run_pipe_real(struct pipe *pi); +/* extended glob support: */ +#ifndef __U_BOOT__ +static int globhack(const char *src, int flags, glob_t *pglob); +static int glob_needed(const char *s); +static int xglob(o_string *dest, int flags, glob_t *pglob); +#endif +/* variable assignment: */ +static int is_assignment(const char *s); +/* data structure manipulation: */ +#ifndef __U_BOOT__ +static int setup_redirect(struct p_context *ctx, int fd, redir_type style, struct in_str *input); +#endif +static void initialize_context(struct p_context *ctx); +static int done_word(o_string *dest, struct p_context *ctx); +static int done_command(struct p_context *ctx); +static int done_pipe(struct p_context *ctx, pipe_style type); +/* primary string parsing: */ +#ifndef __U_BOOT__ +static int redirect_dup_num(struct in_str *input); +static int redirect_opt_num(o_string *o); +static int process_command_subs(o_string *dest, struct p_context *ctx, struct in_str *input, int subst_end); +static int parse_group(o_string *dest, struct p_context *ctx, struct in_str *input, int ch); +#endif +static char *lookup_param(char *src); +static char *make_string(char **inp, int *nonnull); +static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input); +#ifndef __U_BOOT__ +static int parse_string(o_string *dest, struct p_context *ctx, const char *src); +#endif +static int parse_stream(o_string *dest, struct p_context *ctx, struct in_str *input0, int end_trigger); +/* setup: */ +static int parse_stream_outer(struct in_str *inp, int flag); +#ifndef __U_BOOT__ +static int parse_string_outer(const char *s, int flag); +static int parse_file_outer(FILE *f); +#endif +#ifndef __U_BOOT__ +/* job management: */ +static int checkjobs(struct pipe* fg_pipe); +static void insert_bg_job(struct pipe *pi); +static void remove_bg_job(struct pipe *pi); +#endif +/* local variable support */ +static char **make_list_in(char **inp, char *name); +static char *insert_var_value(char *inp); +static char *insert_var_value_sub(char *inp, int tag_subst); + +#ifndef __U_BOOT__ +/* Table of built-in functions. They can be forked or not, depending on + * context: within pipes, they fork. As simple commands, they do not. + * When used in non-forking context, they can change global variables + * in the parent shell process. If forked, of course they can not. + * For example, 'unset foo | whatever' will parse and run, but foo will + * still be set at the end. */ +static struct built_in_command bltins[] = { + {"bg", "Resume a job in the background", builtin_fg_bg}, + {"break", "Exit for, while or until loop", builtin_not_written}, + {"cd", "Change working directory", builtin_cd}, + {"continue", "Continue for, while or until loop", builtin_not_written}, + {"env", "Print all environment variables", builtin_env}, + {"eval", "Construct and run shell command", builtin_eval}, + {"exec", "Exec command, replacing this shell with the exec'd process", + builtin_exec}, + {"exit", "Exit from shell()", builtin_exit}, + {"export", "Set environment variable", builtin_export}, + {"fg", "Bring job into the foreground", builtin_fg_bg}, + {"jobs", "Lists the active jobs", builtin_jobs}, + {"pwd", "Print current directory", builtin_pwd}, + {"read", "Input environment variable", builtin_read}, + {"return", "Return from a function", builtin_not_written}, + {"set", "Set/unset shell local variables", builtin_set}, + {"shift", "Shift positional parameters", builtin_shift}, + {"trap", "Trap signals", builtin_not_written}, + {"ulimit","Controls resource limits", builtin_not_written}, + {"umask","Sets file creation mask", builtin_umask}, + {"unset", "Unset environment variable", builtin_unset}, + {".", "Source-in and run commands in a file", builtin_source}, + {"help", "List shell built-in commands", builtin_help}, + {NULL, NULL, NULL} +}; + +static const char *set_cwd(void) +{ + if(cwd==unknown) + cwd = NULL; /* xgetcwd(arg) called free(arg) */ + cwd = xgetcwd((char *)cwd); + if (!cwd) + cwd = unknown; + return cwd; +} + +/* built-in 'eval' handler */ +static int builtin_eval(struct child_prog *child) +{ + char *str = NULL; + int rcode = EXIT_SUCCESS; + + if (child->argv[1]) { + str = make_string(child->argv + 1); + parse_string_outer(str, FLAG_EXIT_FROM_LOOP | + FLAG_PARSE_SEMICOLON); + free(str); + rcode = last_return_code; + } + return rcode; +} + +/* built-in 'cd ' handler */ +static int builtin_cd(struct child_prog *child) +{ + char *newdir; + if (child->argv[1] == NULL) + newdir = getenv("HOME"); + else + newdir = child->argv[1]; + if (chdir(newdir)) { + printf("cd: %s: %s\n", newdir, strerror(errno)); + return EXIT_FAILURE; + } + set_cwd(); + return EXIT_SUCCESS; +} + +/* built-in 'env' handler */ +static int builtin_env(struct child_prog *dummy) +{ + char **e = environ; + if (e == NULL) return EXIT_FAILURE; + for (; *e; e++) { + puts(*e); + } + return EXIT_SUCCESS; +} + +/* built-in 'exec' handler */ +static int builtin_exec(struct child_prog *child) +{ + if (child->argv[1] == NULL) + return EXIT_SUCCESS; /* Really? */ + child->argv++; + pseudo_exec(child); + /* never returns */ +} + +/* built-in 'exit' handler */ +static int builtin_exit(struct child_prog *child) +{ + if (child->argv[1] == NULL) + exit(last_return_code); + exit (atoi(child->argv[1])); +} + +/* built-in 'export VAR=value' handler */ +static int builtin_export(struct child_prog *child) +{ + int res = 0; + char *name = child->argv[1]; + + if (name == NULL) { + return (builtin_env(child)); + } + + name = strdup(name); + + if(name) { + char *value = strchr(name, '='); + + if (!value) { + char *tmp; + /* They are exporting something without an =VALUE */ + + value = get_local_var(name); + if (value) { + size_t ln = strlen(name); + + tmp = realloc(name, ln+strlen(value)+2); + if(tmp==NULL) + res = -1; + else { + sprintf(tmp+ln, "=%s", value); + name = tmp; + } + } else { + /* bash does not return an error when trying to export + * an undefined variable. Do likewise. */ + res = 1; + } + } + } + if (res<0) + perror_msg("export"); + else if(res==0) + res = set_local_var(name, 1); + else + res = 0; + free(name); + return res; +} + +/* built-in 'fg' and 'bg' handler */ +static int builtin_fg_bg(struct child_prog *child) +{ + int i, jobnum; + struct pipe *pi=NULL; + + if (!interactive) + return EXIT_FAILURE; + /* If they gave us no args, assume they want the last backgrounded task */ + if (!child->argv[1]) { + for (pi = job_list; pi; pi = pi->next) { + if (pi->jobid == last_jobid) { + break; + } + } + if (!pi) { + error_msg("%s: no current job", child->argv[0]); + return EXIT_FAILURE; + } + } else { + if (sscanf(child->argv[1], "%%%d", &jobnum) != 1) { + error_msg("%s: bad argument '%s'", child->argv[0], child->argv[1]); + return EXIT_FAILURE; + } + for (pi = job_list; pi; pi = pi->next) { + if (pi->jobid == jobnum) { + break; + } + } + if (!pi) { + error_msg("%s: %d: no such job", child->argv[0], jobnum); + return EXIT_FAILURE; + } + } + + if (*child->argv[0] == 'f') { + /* Put the job into the foreground. */ + tcsetpgrp(shell_terminal, pi->pgrp); + } + + /* Restart the processes in the job */ + for (i = 0; i < pi->num_progs; i++) + pi->progs[i].is_stopped = 0; + + if ( (i=kill(- pi->pgrp, SIGCONT)) < 0) { + if (i == ESRCH) { + remove_bg_job(pi); + } else { + perror_msg("kill (SIGCONT)"); + } + } + + pi->stopped_progs = 0; + return EXIT_SUCCESS; +} + +/* built-in 'help' handler */ +static int builtin_help(struct child_prog *dummy) +{ + struct built_in_command *x; + + printf("\nBuilt-in commands:\n"); + printf("-------------------\n"); + for (x = bltins; x->cmd; x++) { + if (x->descr==NULL) + continue; + printf("%s\t%s\n", x->cmd, x->descr); + } + printf("\n\n"); + return EXIT_SUCCESS; +} + +/* built-in 'jobs' handler */ +static int builtin_jobs(struct child_prog *child) +{ + struct pipe *job; + char *status_string; + + for (job = job_list; job; job = job->next) { + if (job->running_progs == job->stopped_progs) + status_string = "Stopped"; + else + status_string = "Running"; + + printf(JOB_STATUS_FORMAT, job->jobid, status_string, job->text); + } + return EXIT_SUCCESS; +} + + +/* built-in 'pwd' handler */ +static int builtin_pwd(struct child_prog *dummy) +{ + puts(set_cwd()); + return EXIT_SUCCESS; +} + +/* built-in 'read VAR' handler */ +static int builtin_read(struct child_prog *child) +{ + int res; + + if (child->argv[1]) { + char string[BUFSIZ]; + char *var = 0; + + string[0] = 0; /* In case stdin has only EOF */ + /* read string */ + fgets(string, sizeof(string), stdin); + chomp(string); + var = malloc(strlen(child->argv[1])+strlen(string)+2); + if(var) { + sprintf(var, "%s=%s", child->argv[1], string); + res = set_local_var(var, 0); + } else + res = -1; + if (res) + fprintf(stderr, "read: %m\n"); + free(var); /* So not move up to avoid breaking errno */ + return res; + } else { + do res=getchar(); while(res!='\n' && res!=EOF); + return 0; + } +} + +/* built-in 'set VAR=value' handler */ +static int builtin_set(struct child_prog *child) +{ + char *temp = child->argv[1]; + struct variables *e; + + if (temp == NULL) + for(e = top_vars; e; e=e->next) + printf("%s=%s\n", e->name, e->value); + else + set_local_var(temp, 0); + + return EXIT_SUCCESS; +} + + +/* Built-in 'shift' handler */ +static int builtin_shift(struct child_prog *child) +{ + int n=1; + if (child->argv[1]) { + n=atoi(child->argv[1]); + } + if (n>=0 && nargv[1] == NULL) + return EXIT_FAILURE; + + /* XXX search through $PATH is missing */ + input = fopen(child->argv[1], "r"); + if (!input) { + error_msg("Couldn't open file '%s'", child->argv[1]); + return EXIT_FAILURE; + } + + /* Now run the file */ + /* XXX argv and argc are broken; need to save old global_argv + * (pointer only is OK!) on this stack frame, + * set global_argv=child->argv+1, recurse, and restore. */ + mark_open(fileno(input)); + status = parse_file_outer(input); + mark_closed(fileno(input)); + fclose(input); + return (status); +} + +static int builtin_umask(struct child_prog *child) +{ + mode_t new_umask; + const char *arg = child->argv[1]; + char *end; + if (arg) { + new_umask=strtoul(arg, &end, 8); + if (*end!='\0' || end == arg) { + return EXIT_FAILURE; + } + } else { + printf("%.3o\n", (unsigned int) (new_umask=umask(0))); + } + umask(new_umask); + return EXIT_SUCCESS; +} + +/* built-in 'unset VAR' handler */ +static int builtin_unset(struct child_prog *child) +{ + /* bash returned already true */ + unset_local_var(child->argv[1]); + return EXIT_SUCCESS; +} + +static int builtin_not_written(struct child_prog *child) +{ + printf("builtin_%s not written\n",child->argv[0]); + return EXIT_FAILURE; +} +#endif + +static int b_check_space(o_string *o, int len) +{ + /* It would be easy to drop a more restrictive policy + * in here, such as setting a maximum string length */ + if (o->length + len > o->maxlen) { + char *old_data = o->data; + /* assert (data == NULL || o->maxlen != 0); */ + o->maxlen += max(2*len, B_CHUNK); + o->data = realloc(o->data, 1 + o->maxlen); + if (o->data == NULL) { + free(old_data); + } + } + return o->data == NULL; +} + +static int b_addchr(o_string *o, int ch) +{ + debug_printf("b_addchr: %c %d %p\n", ch, o->length, o); + if (b_check_space(o, 1)) return B_NOSPAC; + o->data[o->length] = ch; + o->length++; + o->data[o->length] = '\0'; + return 0; +} + +static void b_reset(o_string *o) +{ + o->length = 0; + o->nonnull = 0; + if (o->data != NULL) *o->data = '\0'; +} + +static void b_free(o_string *o) +{ + b_reset(o); + free(o->data); + o->data = NULL; + o->maxlen = 0; +} + +/* My analysis of quoting semantics tells me that state information + * is associated with a destination, not a source. + */ +static int b_addqchr(o_string *o, int ch, int quote) +{ + if (quote && strchr("*?[\\",ch)) { + int rc; + rc = b_addchr(o, '\\'); + if (rc) return rc; + } + return b_addchr(o, ch); +} + +#ifndef __U_BOOT__ +static int b_adduint(o_string *o, unsigned int i) +{ + int r; + char *p = simple_itoa(i); + /* no escape checking necessary */ + do r=b_addchr(o, *p++); while (r==0 && *p); + return r; +} +#endif + +static int static_get(struct in_str *i) +{ + int ch = *i->p++; + if (ch=='\0') return EOF; + return ch; +} + +static int static_peek(struct in_str *i) +{ + return *i->p; +} + +#ifndef __U_BOOT__ +static inline void cmdedit_set_initial_prompt(void) +{ +#ifndef CONFIG_FEATURE_SH_FANCY_PROMPT + PS1 = NULL; +#else + PS1 = getenv("PS1"); + if(PS1==0) + PS1 = "\\w \\$ "; +#endif +} + +static inline void setup_prompt_string(int promptmode, char **prompt_str) +{ + debug_printf("setup_prompt_string %d ",promptmode); +#ifndef CONFIG_FEATURE_SH_FANCY_PROMPT + /* Set up the prompt */ + if (promptmode == 1) { + free(PS1); + PS1=xmalloc(strlen(cwd)+4); + sprintf(PS1, "%s %s", cwd, ( geteuid() != 0 ) ? "$ ":"# "); + *prompt_str = PS1; + } else { + *prompt_str = PS2; + } +#else + *prompt_str = (promptmode==1)? PS1 : PS2; +#endif + debug_printf("result %s\n",*prompt_str); +} +#endif + +static void get_user_input(struct in_str *i) +{ +#ifndef __U_BOOT__ + char *prompt_str; + static char the_command[BUFSIZ]; + + setup_prompt_string(i->promptmode, &prompt_str); +#ifdef CONFIG_FEATURE_COMMAND_EDITING + /* + ** enable command line editing only while a command line + ** is actually being read; otherwise, we'll end up bequeathing + ** atexit() handlers and other unwanted stuff to our + ** child processes (rob@sysgo.de) + */ + cmdedit_read_input(prompt_str, the_command); +#else + fputs(prompt_str, stdout); + fflush(stdout); + the_command[0]=fgetc(i->file); + the_command[1]='\0'; +#endif + fflush(stdout); + i->p = the_command; +#else + int n; + static char the_command[CONFIG_SYS_CBSIZE + 1]; + + bootretry_reset_cmd_timeout(); + i->__promptme = 1; + if (i->promptmode == 1) { + n = cli_readline(CONFIG_SYS_PROMPT); + } else { + n = cli_readline(CONFIG_SYS_PROMPT_HUSH_PS2); + } +#ifdef CONFIG_BOOT_RETRY_TIME + if (n == -2) { + puts("\nTimeout waiting for command\n"); +# ifdef CONFIG_RESET_TO_RETRY + do_reset(NULL, 0, 0, NULL); +# else +# error "This currently only works with CONFIG_RESET_TO_RETRY enabled" +# endif + } +#endif + if (n == -1 ) { + flag_repeat = 0; + i->__promptme = 0; + } + n = strlen(console_buffer); + console_buffer[n] = '\n'; + console_buffer[n+1]= '\0'; + if (had_ctrlc()) flag_repeat = 0; + clear_ctrlc(); + do_repeat = 0; + if (i->promptmode == 1) { + if (console_buffer[0] == '\n'&& flag_repeat == 0) { + strcpy(the_command,console_buffer); + } + else { + if (console_buffer[0] != '\n') { + strcpy(the_command,console_buffer); + flag_repeat = 1; + } + else { + do_repeat = 1; + } + } + i->p = the_command; + } + else { + if (console_buffer[0] != '\n') { + if (strlen(the_command) + strlen(console_buffer) + < CONFIG_SYS_CBSIZE) { + n = strlen(the_command); + the_command[n-1] = ' '; + strcpy(&the_command[n],console_buffer); + } + else { + the_command[0] = '\n'; + the_command[1] = '\0'; + flag_repeat = 0; + } + } + if (i->__promptme == 0) { + the_command[0] = '\n'; + the_command[1] = '\0'; + } + i->p = console_buffer; + } +#endif +} + +/* This is the magic location that prints prompts + * and gets data back from the user */ +static int file_get(struct in_str *i) +{ + int ch; + + ch = 0; + /* If there is data waiting, eat it up */ + if (i->p && *i->p) { + ch = *i->p++; + } else { + /* need to double check i->file because we might be doing something + * more complicated by now, like sourcing or substituting. */ +#ifndef __U_BOOT__ + if (i->__promptme && interactive && i->file == stdin) { + while(! i->p || (interactive && strlen(i->p)==0) ) { +#else + while(! i->p || strlen(i->p)==0 ) { +#endif + get_user_input(i); + } + i->promptmode=2; +#ifndef __U_BOOT__ + i->__promptme = 0; +#endif + if (i->p && *i->p) { + ch = *i->p++; + } +#ifndef __U_BOOT__ + } else { + ch = fgetc(i->file); + } + +#endif + debug_printf("b_getch: got a %d\n", ch); + } +#ifndef __U_BOOT__ + if (ch == '\n') i->__promptme=1; +#endif + return ch; +} + +/* All the callers guarantee this routine will never be + * used right after a newline, so prompting is not needed. + */ +static int file_peek(struct in_str *i) +{ +#ifndef __U_BOOT__ + if (i->p && *i->p) { +#endif + return *i->p; +#ifndef __U_BOOT__ + } else { + i->peek_buf[0] = fgetc(i->file); + i->peek_buf[1] = '\0'; + i->p = i->peek_buf; + debug_printf("b_peek: got a %d\n", *i->p); + return *i->p; + } +#endif +} + +#ifndef __U_BOOT__ +static void setup_file_in_str(struct in_str *i, FILE *f) +#else +static void setup_file_in_str(struct in_str *i) +#endif +{ + i->peek = file_peek; + i->get = file_get; + i->__promptme=1; + i->promptmode=1; +#ifndef __U_BOOT__ + i->file = f; +#endif + i->p = NULL; +} + +static void setup_string_in_str(struct in_str *i, const char *s) +{ + i->peek = static_peek; + i->get = static_get; + i->__promptme=1; + i->promptmode=1; + i->p = s; +} + +#ifndef __U_BOOT__ +static void mark_open(int fd) +{ + struct close_me *new = xmalloc(sizeof(struct close_me)); + new->fd = fd; + new->next = close_me_head; + close_me_head = new; +} + +static void mark_closed(int fd) +{ + struct close_me *tmp; + if (close_me_head == NULL || close_me_head->fd != fd) + error_msg_and_die("corrupt close_me"); + tmp = close_me_head; + close_me_head = close_me_head->next; + free(tmp); +} + +static void close_all(void) +{ + struct close_me *c; + for (c=close_me_head; c; c=c->next) { + close(c->fd); + } + close_me_head = NULL; +} + +/* squirrel != NULL means we squirrel away copies of stdin, stdout, + * and stderr if they are redirected. */ +static int setup_redirects(struct child_prog *prog, int squirrel[]) +{ + int openfd, mode; + struct redir_struct *redir; + + for (redir=prog->redirects; redir; redir=redir->next) { + if (redir->dup == -1 && redir->word.gl_pathv == NULL) { + /* something went wrong in the parse. Pretend it didn't happen */ + continue; + } + if (redir->dup == -1) { + mode=redir_table[redir->type].mode; + openfd = open(redir->word.gl_pathv[0], mode, 0666); + if (openfd < 0) { + /* this could get lost if stderr has been redirected, but + bash and ash both lose it as well (though zsh doesn't!) */ + perror_msg("error opening %s", redir->word.gl_pathv[0]); + return 1; + } + } else { + openfd = redir->dup; + } + + if (openfd != redir->fd) { + if (squirrel && redir->fd < 3) { + squirrel[redir->fd] = dup(redir->fd); + } + if (openfd == -3) { + close(openfd); + } else { + dup2(openfd, redir->fd); + if (redir->dup == -1) + close (openfd); + } + } + } + return 0; +} + +static void restore_redirects(int squirrel[]) +{ + int i, fd; + for (i=0; i<3; i++) { + fd = squirrel[i]; + if (fd != -1) { + /* No error checking. I sure wouldn't know what + * to do with an error if I found one! */ + dup2(fd, i); + close(fd); + } + } +} + +/* never returns */ +/* XXX no exit() here. If you don't exec, use _exit instead. + * The at_exit handlers apparently confuse the calling process, + * in particular stdin handling. Not sure why? */ +static void pseudo_exec(struct child_prog *child) +{ + int i, rcode; + char *p; + struct built_in_command *x; + if (child->argv) { + for (i=0; is_assignment(child->argv[i]); i++) { + debug_printf("pid %d environment modification: %s\n",getpid(),child->argv[i]); + p = insert_var_value(child->argv[i]); + putenv(strdup(p)); + if (p != child->argv[i]) free(p); + } + child->argv+=i; /* XXX this hack isn't so horrible, since we are about + to exit, and therefore don't need to keep data + structures consistent for free() use. */ + /* If a variable is assigned in a forest, and nobody listens, + * was it ever really set? + */ + if (child->argv[0] == NULL) { + _exit(EXIT_SUCCESS); + } + + /* + * Check if the command matches any of the builtins. + * Depending on context, this might be redundant. But it's + * easier to waste a few CPU cycles than it is to figure out + * if this is one of those cases. + */ + for (x = bltins; x->cmd; x++) { + if (strcmp(child->argv[0], x->cmd) == 0 ) { + debug_printf("builtin exec %s\n", child->argv[0]); + rcode = x->function(child); + fflush(stdout); + _exit(rcode); + } + } + + /* Check if the command matches any busybox internal commands + * ("applets") here. + * FIXME: This feature is not 100% safe, since + * BusyBox is not fully reentrant, so we have no guarantee the things + * from the .bss are still zeroed, or that things from .data are still + * at their defaults. We could exec ourself from /proc/self/exe, but I + * really dislike relying on /proc for things. We could exec ourself + * from global_argv[0], but if we are in a chroot, we may not be able + * to find ourself... */ +#ifdef CONFIG_FEATURE_SH_STANDALONE_SHELL + { + int argc_l; + char** argv_l=child->argv; + char *name = child->argv[0]; + +#ifdef CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN + /* Following discussions from November 2000 on the busybox mailing + * list, the default configuration, (without + * get_last_path_component()) lets the user force use of an + * external command by specifying the full (with slashes) filename. + * If you enable CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN then applets + * _aways_ override external commands, so if you want to run + * /bin/cat, it will use BusyBox cat even if /bin/cat exists on the + * filesystem and is _not_ busybox. Some systems may want this, + * most do not. */ + name = get_last_path_component(name); +#endif + /* Count argc for use in a second... */ + for(argc_l=0;*argv_l!=NULL; argv_l++, argc_l++); + optind = 1; + debug_printf("running applet %s\n", name); + run_applet_by_name(name, argc_l, child->argv); + } +#endif + debug_printf("exec of %s\n",child->argv[0]); + execvp(child->argv[0],child->argv); + perror_msg("couldn't exec: %s",child->argv[0]); + _exit(1); + } else if (child->group) { + debug_printf("runtime nesting to group\n"); + interactive=0; /* crucial!!!! */ + rcode = run_list_real(child->group); + /* OK to leak memory by not calling free_pipe_list, + * since this process is about to exit */ + _exit(rcode); + } else { + /* Can happen. See what bash does with ">foo" by itself. */ + debug_printf("trying to pseudo_exec null command\n"); + _exit(EXIT_SUCCESS); + } +} + +static void insert_bg_job(struct pipe *pi) +{ + struct pipe *thejob; + + /* Linear search for the ID of the job to use */ + pi->jobid = 1; + for (thejob = job_list; thejob; thejob = thejob->next) + if (thejob->jobid >= pi->jobid) + pi->jobid = thejob->jobid + 1; + + /* add thejob to the list of running jobs */ + if (!job_list) { + thejob = job_list = xmalloc(sizeof(*thejob)); + } else { + for (thejob = job_list; thejob->next; thejob = thejob->next) /* nothing */; + thejob->next = xmalloc(sizeof(*thejob)); + thejob = thejob->next; + } + + /* physically copy the struct job */ + memcpy(thejob, pi, sizeof(struct pipe)); + thejob->next = NULL; + thejob->running_progs = thejob->num_progs; + thejob->stopped_progs = 0; + thejob->text = xmalloc(BUFSIZ); /* cmdedit buffer size */ + + /*if (pi->progs[0] && pi->progs[0].argv && pi->progs[0].argv[0]) */ + { + char *bar=thejob->text; + char **foo=pi->progs[0].argv; + while(foo && *foo) { + bar += sprintf(bar, "%s ", *foo++); + } + } + + /* we don't wait for background thejobs to return -- append it + to the list of backgrounded thejobs and leave it alone */ + printf("[%d] %d\n", thejob->jobid, thejob->progs[0].pid); + last_bg_pid = thejob->progs[0].pid; + last_jobid = thejob->jobid; +} + +/* remove a backgrounded job */ +static void remove_bg_job(struct pipe *pi) +{ + struct pipe *prev_pipe; + + if (pi == job_list) { + job_list = pi->next; + } else { + prev_pipe = job_list; + while (prev_pipe->next != pi) + prev_pipe = prev_pipe->next; + prev_pipe->next = pi->next; + } + if (job_list) + last_jobid = job_list->jobid; + else + last_jobid = 0; + + pi->stopped_progs = 0; + free_pipe(pi, 0); + free(pi); +} + +/* Checks to see if any processes have exited -- if they + have, figure out why and see if a job has completed */ +static int checkjobs(struct pipe* fg_pipe) +{ + int attributes; + int status; + int prognum = 0; + struct pipe *pi; + pid_t childpid; + + attributes = WUNTRACED; + if (fg_pipe==NULL) { + attributes |= WNOHANG; + } + + while ((childpid = waitpid(-1, &status, attributes)) > 0) { + if (fg_pipe) { + int i, rcode = 0; + for (i=0; i < fg_pipe->num_progs; i++) { + if (fg_pipe->progs[i].pid == childpid) { + if (i==fg_pipe->num_progs-1) + rcode=WEXITSTATUS(status); + (fg_pipe->num_progs)--; + return(rcode); + } + } + } + + for (pi = job_list; pi; pi = pi->next) { + prognum = 0; + while (prognum < pi->num_progs && pi->progs[prognum].pid != childpid) { + prognum++; + } + if (prognum < pi->num_progs) + break; + } + + if(pi==NULL) { + debug_printf("checkjobs: pid %d was not in our list!\n", childpid); + continue; + } + + if (WIFEXITED(status) || WIFSIGNALED(status)) { + /* child exited */ + pi->running_progs--; + pi->progs[prognum].pid = 0; + + if (!pi->running_progs) { + printf(JOB_STATUS_FORMAT, pi->jobid, "Done", pi->text); + remove_bg_job(pi); + } + } else { + /* child stopped */ + pi->stopped_progs++; + pi->progs[prognum].is_stopped = 1; + +#if 0 + /* Printing this stuff is a pain, since it tends to + * overwrite the prompt an inconveinient moments. So + * don't do that. */ + if (pi->stopped_progs == pi->num_progs) { + printf("\n"JOB_STATUS_FORMAT, pi->jobid, "Stopped", pi->text); + } +#endif + } + } + + if (childpid == -1 && errno != ECHILD) + perror_msg("waitpid"); + + /* move the shell to the foreground */ + /*if (interactive && tcsetpgrp(shell_terminal, getpgid(0))) */ + /* perror_msg("tcsetpgrp-2"); */ + return -1; +} + +/* Figure out our controlling tty, checking in order stderr, + * stdin, and stdout. If check_pgrp is set, also check that + * we belong to the foreground process group associated with + * that tty. The value of shell_terminal is needed in order to call + * tcsetpgrp(shell_terminal, ...); */ +void controlling_tty(int check_pgrp) +{ + pid_t curpgrp; + + if ((curpgrp = tcgetpgrp(shell_terminal = 2)) < 0 + && (curpgrp = tcgetpgrp(shell_terminal = 0)) < 0 + && (curpgrp = tcgetpgrp(shell_terminal = 1)) < 0) + goto shell_terminal_error; + + if (check_pgrp && curpgrp != getpgid(0)) + goto shell_terminal_error; + + return; + +shell_terminal_error: + shell_terminal = -1; + return; +} +#endif + +/* run_pipe_real() starts all the jobs, but doesn't wait for anything + * to finish. See checkjobs(). + * + * return code is normally -1, when the caller has to wait for children + * to finish to determine the exit status of the pipe. If the pipe + * is a simple builtin command, however, the action is done by the + * time run_pipe_real returns, and the exit code is provided as the + * return value. + * + * The input of the pipe is always stdin, the output is always + * stdout. The outpipe[] mechanism in BusyBox-0.48 lash is bogus, + * because it tries to avoid running the command substitution in + * subshell, when that is in fact necessary. The subshell process + * now has its stdout directed to the input of the appropriate pipe, + * so this routine is noticeably simpler. + */ +static int run_pipe_real(struct pipe *pi) +{ + int i; +#ifndef __U_BOOT__ + int nextin, nextout; + int pipefds[2]; /* pipefds[0] is for reading */ + struct child_prog *child; + struct built_in_command *x; + char *p; +# if __GNUC__ + /* Avoid longjmp clobbering */ + (void) &i; + (void) &nextin; + (void) &nextout; + (void) &child; +# endif +#else + int nextin; + int flag = do_repeat ? CMD_FLAG_REPEAT : 0; + struct child_prog *child; + char *p; +# if __GNUC__ + /* Avoid longjmp clobbering */ + (void) &i; + (void) &nextin; + (void) &child; +# endif +#endif /* __U_BOOT__ */ + + nextin = 0; +#ifndef __U_BOOT__ + pi->pgrp = -1; +#endif + + /* Check if this is a simple builtin (not part of a pipe). + * Builtins within pipes have to fork anyway, and are handled in + * pseudo_exec. "echo foo | read bar" doesn't work on bash, either. + */ + if (pi->num_progs == 1) child = & (pi->progs[0]); +#ifndef __U_BOOT__ + if (pi->num_progs == 1 && child->group && child->subshell == 0) { + int squirrel[] = {-1, -1, -1}; + int rcode; + debug_printf("non-subshell grouping\n"); + setup_redirects(child, squirrel); + /* XXX could we merge code with following builtin case, + * by creating a pseudo builtin that calls run_list_real? */ + rcode = run_list_real(child->group); + restore_redirects(squirrel); +#else + if (pi->num_progs == 1 && child->group) { + int rcode; + debug_printf("non-subshell grouping\n"); + rcode = run_list_real(child->group); +#endif + return rcode; + } else if (pi->num_progs == 1 && pi->progs[0].argv != NULL) { + for (i=0; is_assignment(child->argv[i]); i++) { /* nothing */ } + if (i!=0 && child->argv[i]==NULL) { + /* assignments, but no command: set the local environment */ + for (i=0; child->argv[i]!=NULL; i++) { + + /* Ok, this case is tricky. We have to decide if this is a + * local variable, or an already exported variable. If it is + * already exported, we have to export the new value. If it is + * not exported, we need only set this as a local variable. + * This junk is all to decide whether or not to export this + * variable. */ + int export_me=0; + char *name, *value; + name = xstrdup(child->argv[i]); + debug_printf("Local environment set: %s\n", name); + value = strchr(name, '='); + if (value) + *value=0; +#ifndef __U_BOOT__ + if ( get_local_var(name)) { + export_me=1; + } +#endif + free(name); + p = insert_var_value(child->argv[i]); + set_local_var(p, export_me); + if (p != child->argv[i]) free(p); + } + return EXIT_SUCCESS; /* don't worry about errors in set_local_var() yet */ + } + for (i = 0; is_assignment(child->argv[i]); i++) { + p = insert_var_value(child->argv[i]); +#ifndef __U_BOOT__ + putenv(strdup(p)); +#else + set_local_var(p, 0); +#endif + if (p != child->argv[i]) { + child->sp--; + free(p); + } + } + if (child->sp) { + char * str = NULL; + + str = make_string(child->argv + i, + child->argv_nonnull + i); + parse_string_outer(str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING); + free(str); + return last_return_code; + } +#ifndef __U_BOOT__ + for (x = bltins; x->cmd; x++) { + if (strcmp(child->argv[i], x->cmd) == 0 ) { + int squirrel[] = {-1, -1, -1}; + int rcode; + if (x->function == builtin_exec && child->argv[i+1]==NULL) { + debug_printf("magic exec\n"); + setup_redirects(child,NULL); + return EXIT_SUCCESS; + } + debug_printf("builtin inline %s\n", child->argv[0]); + /* XXX setup_redirects acts on file descriptors, not FILEs. + * This is perfect for work that comes after exec(). + * Is it really safe for inline use? Experimentally, + * things seem to work with glibc. */ + setup_redirects(child, squirrel); + + child->argv += i; /* XXX horrible hack */ + rcode = x->function(child); + /* XXX restore hack so free() can work right */ + child->argv -= i; + restore_redirects(squirrel); + } + return rcode; + } +#else + /* check ";", because ,example , argv consist from + * "help;flinfo" must not execute + */ + if (strchr(child->argv[i], ';')) { + printf("Unknown command '%s' - try 'help' or use " + "'run' command\n", child->argv[i]); + return -1; + } + /* Process the command */ + return cmd_process(flag, child->argc, child->argv, + &flag_repeat, NULL); +#endif + } +#ifndef __U_BOOT__ + + for (i = 0; i < pi->num_progs; i++) { + child = & (pi->progs[i]); + + /* pipes are inserted between pairs of commands */ + if ((i + 1) < pi->num_progs) { + if (pipe(pipefds)<0) perror_msg_and_die("pipe"); + nextout = pipefds[1]; + } else { + nextout=1; + pipefds[0] = -1; + } + + /* XXX test for failed fork()? */ + if (!(child->pid = fork())) { + /* Set the handling for job control signals back to the default. */ + signal(SIGINT, SIG_DFL); + signal(SIGQUIT, SIG_DFL); + signal(SIGTERM, SIG_DFL); + signal(SIGTSTP, SIG_DFL); + signal(SIGTTIN, SIG_DFL); + signal(SIGTTOU, SIG_DFL); + signal(SIGCHLD, SIG_DFL); + + close_all(); + + if (nextin != 0) { + dup2(nextin, 0); + close(nextin); + } + if (nextout != 1) { + dup2(nextout, 1); + close(nextout); + } + if (pipefds[0]!=-1) { + close(pipefds[0]); /* opposite end of our output pipe */ + } + + /* Like bash, explicit redirects override pipes, + * and the pipe fd is available for dup'ing. */ + setup_redirects(child,NULL); + + if (interactive && pi->followup!=PIPE_BG) { + /* If we (the child) win the race, put ourselves in the process + * group whose leader is the first process in this pipe. */ + if (pi->pgrp < 0) { + pi->pgrp = getpid(); + } + if (setpgid(0, pi->pgrp) == 0) { + tcsetpgrp(2, pi->pgrp); + } + } + + pseudo_exec(child); + } + + + /* put our child in the process group whose leader is the + first process in this pipe */ + if (pi->pgrp < 0) { + pi->pgrp = child->pid; + } + /* Don't check for errors. The child may be dead already, + * in which case setpgid returns error code EACCES. */ + setpgid(child->pid, pi->pgrp); + + if (nextin != 0) + close(nextin); + if (nextout != 1) + close(nextout); + + /* If there isn't another process, nextin is garbage + but it doesn't matter */ + nextin = pipefds[0]; + } +#endif + return -1; +} + +static int run_list_real(struct pipe *pi) +{ + char *save_name = NULL; + char **list = NULL; + char **save_list = NULL; + struct pipe *rpipe; + int flag_rep = 0; +#ifndef __U_BOOT__ + int save_num_progs; +#endif + int rcode=0, flag_skip=1; + int flag_restore = 0; + int if_code=0, next_if_code=0; /* need double-buffer to handle elif */ + reserved_style rmode, skip_more_in_this_rmode=RES_XXXX; + /* check syntax for "for" */ + for (rpipe = pi; rpipe; rpipe = rpipe->next) { + if ((rpipe->r_mode == RES_IN || + rpipe->r_mode == RES_FOR) && + (rpipe->next == NULL)) { + syntax(); +#ifdef __U_BOOT__ + flag_repeat = 0; +#endif + return 1; + } + if ((rpipe->r_mode == RES_IN && + (rpipe->next->r_mode == RES_IN && + rpipe->next->progs->argv != NULL))|| + (rpipe->r_mode == RES_FOR && + rpipe->next->r_mode != RES_IN)) { + syntax(); +#ifdef __U_BOOT__ + flag_repeat = 0; +#endif + return 1; + } + } + for (; pi; pi = (flag_restore != 0) ? rpipe : pi->next) { + if (pi->r_mode == RES_WHILE || pi->r_mode == RES_UNTIL || + pi->r_mode == RES_FOR) { +#ifdef __U_BOOT__ + /* check Ctrl-C */ + ctrlc(); + if ((had_ctrlc())) { + return 1; + } +#endif + flag_restore = 0; + if (!rpipe) { + flag_rep = 0; + rpipe = pi; + } + } + rmode = pi->r_mode; + debug_printf("rmode=%d if_code=%d next_if_code=%d skip_more=%d\n", rmode, if_code, next_if_code, skip_more_in_this_rmode); + if (rmode == skip_more_in_this_rmode && flag_skip) { + if (pi->followup == PIPE_SEQ) flag_skip=0; + continue; + } + flag_skip = 1; + skip_more_in_this_rmode = RES_XXXX; + if (rmode == RES_THEN || rmode == RES_ELSE) if_code = next_if_code; + if (rmode == RES_THEN && if_code) continue; + if (rmode == RES_ELSE && !if_code) continue; + if (rmode == RES_ELIF && !if_code) break; + if (rmode == RES_FOR && pi->num_progs) { + if (!list) { + /* if no variable values after "in" we skip "for" */ + if (!pi->next->progs->argv) continue; + /* create list of variable values */ + list = make_list_in(pi->next->progs->argv, + pi->progs->argv[0]); + save_list = list; + save_name = pi->progs->argv[0]; + pi->progs->argv[0] = NULL; + flag_rep = 1; + } + if (!(*list)) { + free(pi->progs->argv[0]); + free(save_list); + list = NULL; + flag_rep = 0; + pi->progs->argv[0] = save_name; +#ifndef __U_BOOT__ + pi->progs->glob_result.gl_pathv[0] = + pi->progs->argv[0]; +#endif + continue; + } else { + /* insert new value from list for variable */ + if (pi->progs->argv[0]) + free(pi->progs->argv[0]); + pi->progs->argv[0] = *list++; +#ifndef __U_BOOT__ + pi->progs->glob_result.gl_pathv[0] = + pi->progs->argv[0]; +#endif + } + } + if (rmode == RES_IN) continue; + if (rmode == RES_DO) { + if (!flag_rep) continue; + } + if (rmode == RES_DONE) { + if (flag_rep) { + flag_restore = 1; + } else { + rpipe = NULL; + } + } + if (pi->num_progs == 0) continue; +#ifndef __U_BOOT__ + save_num_progs = pi->num_progs; /* save number of programs */ +#endif + rcode = run_pipe_real(pi); + debug_printf("run_pipe_real returned %d\n",rcode); +#ifndef __U_BOOT__ + if (rcode!=-1) { + /* We only ran a builtin: rcode was set by the return value + * of run_pipe_real(), and we don't need to wait for anything. */ + } else if (pi->followup==PIPE_BG) { + /* XXX check bash's behavior with nontrivial pipes */ + /* XXX compute jobid */ + /* XXX what does bash do with attempts to background builtins? */ + insert_bg_job(pi); + rcode = EXIT_SUCCESS; + } else { + if (interactive) { + /* move the new process group into the foreground */ + if (tcsetpgrp(shell_terminal, pi->pgrp) && errno != ENOTTY) + perror_msg("tcsetpgrp-3"); + rcode = checkjobs(pi); + /* move the shell to the foreground */ + if (tcsetpgrp(shell_terminal, getpgid(0)) && errno != ENOTTY) + perror_msg("tcsetpgrp-4"); + } else { + rcode = checkjobs(pi); + } + debug_printf("checkjobs returned %d\n",rcode); + } + last_return_code=rcode; +#else + if (rcode < -1) { + last_return_code = -rcode - 2; + return -2; /* exit */ + } + last_return_code=(rcode == 0) ? 0 : 1; +#endif +#ifndef __U_BOOT__ + pi->num_progs = save_num_progs; /* restore number of programs */ +#endif + if ( rmode == RES_IF || rmode == RES_ELIF ) + next_if_code=rcode; /* can be overwritten a number of times */ + if (rmode == RES_WHILE) + flag_rep = !last_return_code; + if (rmode == RES_UNTIL) + flag_rep = last_return_code; + if ( (rcode==EXIT_SUCCESS && pi->followup==PIPE_OR) || + (rcode!=EXIT_SUCCESS && pi->followup==PIPE_AND) ) + skip_more_in_this_rmode=rmode; +#ifndef __U_BOOT__ + checkjobs(NULL); +#endif + } + return rcode; +} + +/* broken, of course, but OK for testing */ +static char *indenter(int i) +{ + static char blanks[]=" "; + return &blanks[sizeof(blanks)-i-1]; +} + +/* return code is the exit status of the pipe */ +static int free_pipe(struct pipe *pi, int indent) +{ + char **p; + struct child_prog *child; +#ifndef __U_BOOT__ + struct redir_struct *r, *rnext; +#endif + int a, i, ret_code=0; + char *ind = indenter(indent); + +#ifndef __U_BOOT__ + if (pi->stopped_progs > 0) + return ret_code; + final_printf("%s run pipe: (pid %d)\n",ind,getpid()); +#endif + for (i=0; inum_progs; i++) { + child = &pi->progs[i]; + final_printf("%s command %d:\n",ind,i); + if (child->argv) { + for (a=0,p=child->argv; *p; a++,p++) { + final_printf("%s argv[%d] = %s\n",ind,a,*p); + } +#ifndef __U_BOOT__ + globfree(&child->glob_result); +#else + for (a = 0; a < child->argc; a++) { + free(child->argv[a]); + } + free(child->argv); + free(child->argv_nonnull); + child->argc = 0; +#endif + child->argv=NULL; + } else if (child->group) { +#ifndef __U_BOOT__ + final_printf("%s begin group (subshell:%d)\n",ind, child->subshell); +#endif + ret_code = free_pipe_list(child->group,indent+3); + final_printf("%s end group\n",ind); + } else { + final_printf("%s (nil)\n",ind); + } +#ifndef __U_BOOT__ + for (r=child->redirects; r; r=rnext) { + final_printf("%s redirect %d%s", ind, r->fd, redir_table[r->type].descrip); + if (r->dup == -1) { + /* guard against the case >$FOO, where foo is unset or blank */ + if (r->word.gl_pathv) { + final_printf(" %s\n", *r->word.gl_pathv); + globfree(&r->word); + } + } else { + final_printf("&%d\n", r->dup); + } + rnext=r->next; + free(r); + } + child->redirects=NULL; +#endif + } + free(pi->progs); /* children are an array, they get freed all at once */ + pi->progs=NULL; + return ret_code; +} + +static int free_pipe_list(struct pipe *head, int indent) +{ + int rcode=0; /* if list has no members */ + struct pipe *pi, *next; + char *ind = indenter(indent); + for (pi=head; pi; pi=next) { + final_printf("%s pipe reserved mode %d\n", ind, pi->r_mode); + rcode = free_pipe(pi, indent); + final_printf("%s pipe followup code %d\n", ind, pi->followup); + next=pi->next; + pi->next=NULL; + free(pi); + } + return rcode; +} + +/* Select which version we will use */ +static int run_list(struct pipe *pi) +{ + int rcode=0; +#ifndef __U_BOOT__ + if (fake_mode==0) { +#endif + rcode = run_list_real(pi); +#ifndef __U_BOOT__ + } +#endif + /* free_pipe_list has the side effect of clearing memory + * In the long run that function can be merged with run_list_real, + * but doing that now would hobble the debugging effort. */ + free_pipe_list(pi,0); + return rcode; +} + +/* The API for glob is arguably broken. This routine pushes a non-matching + * string into the output structure, removing non-backslashed backslashes. + * If someone can prove me wrong, by performing this function within the + * original glob(3) api, feel free to rewrite this routine into oblivion. + * Return code (0 vs. GLOB_NOSPACE) matches glob(3). + * XXX broken if the last character is '\\', check that before calling. + */ +#ifndef __U_BOOT__ +static int globhack(const char *src, int flags, glob_t *pglob) +{ + int cnt=0, pathc; + const char *s; + char *dest; + for (cnt=1, s=src; s && *s; s++) { + if (*s == '\\') s++; + cnt++; + } + dest = malloc(cnt); + if (!dest) return GLOB_NOSPACE; + if (!(flags & GLOB_APPEND)) { + pglob->gl_pathv=NULL; + pglob->gl_pathc=0; + pglob->gl_offs=0; + pglob->gl_offs=0; + } + pathc = ++pglob->gl_pathc; + pglob->gl_pathv = realloc(pglob->gl_pathv, (pathc+1)*sizeof(*pglob->gl_pathv)); + if (pglob->gl_pathv == NULL) return GLOB_NOSPACE; + pglob->gl_pathv[pathc-1]=dest; + pglob->gl_pathv[pathc]=NULL; + for (s=src; s && *s; s++, dest++) { + if (*s == '\\') s++; + *dest = *s; + } + *dest='\0'; + return 0; +} + +/* XXX broken if the last character is '\\', check that before calling */ +static int glob_needed(const char *s) +{ + for (; *s; s++) { + if (*s == '\\') s++; + if (strchr("*[?",*s)) return 1; + } + return 0; +} + +#if 0 +static void globprint(glob_t *pglob) +{ + int i; + debug_printf("glob_t at %p:\n", pglob); + debug_printf(" gl_pathc=%d gl_pathv=%p gl_offs=%d gl_flags=%d\n", + pglob->gl_pathc, pglob->gl_pathv, pglob->gl_offs, pglob->gl_flags); + for (i=0; igl_pathc; i++) + debug_printf("pglob->gl_pathv[%d] = %p = %s\n", i, + pglob->gl_pathv[i], pglob->gl_pathv[i]); +} +#endif + +static int xglob(o_string *dest, int flags, glob_t *pglob) +{ + int gr; + + /* short-circuit for null word */ + /* we can code this better when the debug_printf's are gone */ + if (dest->length == 0) { + if (dest->nonnull) { + /* bash man page calls this an "explicit" null */ + gr = globhack(dest->data, flags, pglob); + debug_printf("globhack returned %d\n",gr); + } else { + return 0; + } + } else if (glob_needed(dest->data)) { + gr = glob(dest->data, flags, NULL, pglob); + debug_printf("glob returned %d\n",gr); + if (gr == GLOB_NOMATCH) { + /* quote removal, or more accurately, backslash removal */ + gr = globhack(dest->data, flags, pglob); + debug_printf("globhack returned %d\n",gr); + } + } else { + gr = globhack(dest->data, flags, pglob); + debug_printf("globhack returned %d\n",gr); + } + if (gr == GLOB_NOSPACE) + error_msg_and_die("out of memory during glob"); + if (gr != 0) { /* GLOB_ABORTED ? */ + error_msg("glob(3) error %d",gr); + } + /* globprint(glob_target); */ + return gr; +} +#endif + +#ifdef __U_BOOT__ +static char *get_dollar_var(char ch); +#endif + +/* This is used to get/check local shell variables */ +char *get_local_var(const char *s) +{ + struct variables *cur; + + if (!s) + return NULL; + +#ifdef __U_BOOT__ + if (*s == '$') + return get_dollar_var(s[1]); +#endif + + for (cur = top_vars; cur; cur=cur->next) + if(strcmp(cur->name, s)==0) + return cur->value; + return NULL; +} + +/* This is used to set local shell variables + flg_export==0 if only local (not exporting) variable + flg_export==1 if "new" exporting environ + flg_export>1 if current startup environ (not call putenv()) */ +int set_local_var(const char *s, int flg_export) +{ + char *name, *value; + int result=0; + struct variables *cur; + +#ifdef __U_BOOT__ + /* might be possible! */ + if (!isalpha(*s)) + return -1; +#endif + + name=strdup(s); + +#ifdef __U_BOOT__ + if (getenv(name) != NULL) { + printf ("ERROR: " + "There is a global environment variable with the same name.\n"); + free(name); + return -1; + } +#endif + /* Assume when we enter this function that we are already in + * NAME=VALUE format. So the first order of business is to + * split 's' on the '=' into 'name' and 'value' */ + value = strchr(name, '='); + if (value == NULL && ++value == NULL) { + free(name); + return -1; + } + *value++ = 0; + + for(cur = top_vars; cur; cur = cur->next) { + if(strcmp(cur->name, name)==0) + break; + } + + if(cur) { + if(strcmp(cur->value, value)==0) { + if(flg_export>0 && cur->flg_export==0) + cur->flg_export=flg_export; + else + result++; + } else { + if(cur->flg_read_only) { + error_msg("%s: readonly variable", name); + result = -1; + } else { + if(flg_export>0 || cur->flg_export>1) + cur->flg_export=1; + free(cur->value); + + cur->value = strdup(value); + } + } + } else { + cur = malloc(sizeof(struct variables)); + if(!cur) { + result = -1; + } else { + cur->name = strdup(name); + if (cur->name == NULL) { + free(cur); + result = -1; + } else { + struct variables *bottom = top_vars; + cur->value = strdup(value); + cur->next = NULL; + cur->flg_export = flg_export; + cur->flg_read_only = 0; + while(bottom->next) bottom=bottom->next; + bottom->next = cur; + } + } + } + +#ifndef __U_BOOT__ + if(result==0 && cur->flg_export==1) { + *(value-1) = '='; + result = putenv(name); + } else { +#endif + free(name); +#ifndef __U_BOOT__ + if(result>0) /* equivalent to previous set */ + result = 0; + } +#endif + return result; +} + +void unset_local_var(const char *name) +{ + struct variables *cur; + + if (name) { + for (cur = top_vars; cur; cur=cur->next) { + if(strcmp(cur->name, name)==0) + break; + } + if (cur != NULL) { + struct variables *next = top_vars; + if(cur->flg_read_only) { + error_msg("%s: readonly variable", name); + return; + } else { +#ifndef __U_BOOT__ + if(cur->flg_export) + unsetenv(cur->name); +#endif + free(cur->name); + free(cur->value); + while (next->next != cur) + next = next->next; + next->next = cur->next; + } + free(cur); + } + } +} + +static int is_assignment(const char *s) +{ + if (s == NULL) + return 0; + + if (!isalpha(*s)) return 0; + ++s; + while(isalnum(*s) || *s=='_') ++s; + return *s=='='; +} + +#ifndef __U_BOOT__ +/* the src parameter allows us to peek forward to a possible &n syntax + * for file descriptor duplication, e.g., "2>&1". + * Return code is 0 normally, 1 if a syntax error is detected in src. + * Resource errors (in xmalloc) cause the process to exit */ +static int setup_redirect(struct p_context *ctx, int fd, redir_type style, + struct in_str *input) +{ + struct child_prog *child=ctx->child; + struct redir_struct *redir = child->redirects; + struct redir_struct *last_redir=NULL; + + /* Create a new redir_struct and drop it onto the end of the linked list */ + while(redir) { + last_redir=redir; + redir=redir->next; + } + redir = xmalloc(sizeof(struct redir_struct)); + redir->next=NULL; + redir->word.gl_pathv=NULL; + if (last_redir) { + last_redir->next=redir; + } else { + child->redirects=redir; + } + + redir->type=style; + redir->fd= (fd==-1) ? redir_table[style].default_fd : fd ; + + debug_printf("Redirect type %d%s\n", redir->fd, redir_table[style].descrip); + + /* Check for a '2>&1' type redirect */ + redir->dup = redirect_dup_num(input); + if (redir->dup == -2) return 1; /* syntax error */ + if (redir->dup != -1) { + /* Erik had a check here that the file descriptor in question + * is legit; I postpone that to "run time" + * A "-" representation of "close me" shows up as a -3 here */ + debug_printf("Duplicating redirect '%d>&%d'\n", redir->fd, redir->dup); + } else { + /* We do _not_ try to open the file that src points to, + * since we need to return and let src be expanded first. + * Set ctx->pending_redirect, so we know what to do at the + * end of the next parsed word. + */ + ctx->pending_redirect = redir; + } + return 0; +} +#endif + +static struct pipe *new_pipe(void) +{ + struct pipe *pi; + pi = xmalloc(sizeof(struct pipe)); + pi->num_progs = 0; + pi->progs = NULL; + pi->next = NULL; + pi->followup = 0; /* invalid */ + pi->r_mode = RES_NONE; + return pi; +} + +static void initialize_context(struct p_context *ctx) +{ + ctx->pipe=NULL; +#ifndef __U_BOOT__ + ctx->pending_redirect=NULL; +#endif + ctx->child=NULL; + ctx->list_head=new_pipe(); + ctx->pipe=ctx->list_head; + ctx->w=RES_NONE; + ctx->stack=NULL; +#ifdef __U_BOOT__ + ctx->old_flag=0; +#endif + done_command(ctx); /* creates the memory for working child */ +} + +/* normal return is 0 + * if a reserved word is found, and processed, return 1 + * should handle if, then, elif, else, fi, for, while, until, do, done. + * case, function, and select are obnoxious, save those for later. + */ +struct reserved_combo { + char *literal; + int code; + long flag; +}; +/* Mostly a list of accepted follow-up reserved words. + * FLAG_END means we are done with the sequence, and are ready + * to turn the compound list into a command. + * FLAG_START means the word must start a new compound list. + */ +static struct reserved_combo reserved_list[] = { + { "if", RES_IF, FLAG_THEN | FLAG_START }, + { "then", RES_THEN, FLAG_ELIF | FLAG_ELSE | FLAG_FI }, + { "elif", RES_ELIF, FLAG_THEN }, + { "else", RES_ELSE, FLAG_FI }, + { "fi", RES_FI, FLAG_END }, + { "for", RES_FOR, FLAG_IN | FLAG_START }, + { "while", RES_WHILE, FLAG_DO | FLAG_START }, + { "until", RES_UNTIL, FLAG_DO | FLAG_START }, + { "in", RES_IN, FLAG_DO }, + { "do", RES_DO, FLAG_DONE }, + { "done", RES_DONE, FLAG_END } +}; +#define NRES (sizeof(reserved_list)/sizeof(struct reserved_combo)) + +static int reserved_word(o_string *dest, struct p_context *ctx) +{ + struct reserved_combo *r; + for (r=reserved_list; + rdata, r->literal) == 0) { + debug_printf("found reserved word %s, code %d\n",r->literal,r->code); + if (r->flag & FLAG_START) { + struct p_context *new = xmalloc(sizeof(struct p_context)); + debug_printf("push stack\n"); + if (ctx->w == RES_IN || ctx->w == RES_FOR) { + syntax(); + free(new); + ctx->w = RES_SNTX; + b_reset(dest); + return 1; + } + *new = *ctx; /* physical copy */ + initialize_context(ctx); + ctx->stack=new; + } else if ( ctx->w == RES_NONE || ! (ctx->old_flag & (1<code))) { + syntax(); + ctx->w = RES_SNTX; + b_reset(dest); + return 1; + } + ctx->w=r->code; + ctx->old_flag = r->flag; + if (ctx->old_flag & FLAG_END) { + struct p_context *old; + debug_printf("pop stack\n"); + done_pipe(ctx,PIPE_SEQ); + old = ctx->stack; + old->child->group = ctx->list_head; +#ifndef __U_BOOT__ + old->child->subshell = 0; +#endif + *ctx = *old; /* physical copy */ + free(old); + } + b_reset (dest); + return 1; + } + } + return 0; +} + +/* normal return is 0. + * Syntax or xglob errors return 1. */ +static int done_word(o_string *dest, struct p_context *ctx) +{ + struct child_prog *child=ctx->child; +#ifndef __U_BOOT__ + glob_t *glob_target; + int gr, flags = 0; +#else + char *str, *s; + int argc, cnt; +#endif + + debug_printf("done_word: %s %p\n", dest->data, child); + if (dest->length == 0 && !dest->nonnull) { + debug_printf(" true null, ignored\n"); + return 0; + } +#ifndef __U_BOOT__ + if (ctx->pending_redirect) { + glob_target = &ctx->pending_redirect->word; + } else { +#endif + if (child->group) { + syntax(); + return 1; /* syntax error, groups and arglists don't mix */ + } + if (!child->argv && (ctx->type & FLAG_PARSE_SEMICOLON)) { + debug_printf("checking %s for reserved-ness\n",dest->data); + if (reserved_word(dest,ctx)) return ctx->w==RES_SNTX; + } +#ifndef __U_BOOT__ + glob_target = &child->glob_result; + if (child->argv) flags |= GLOB_APPEND; +#else + for (cnt = 1, s = dest->data; s && *s; s++) { + if (*s == '\\') s++; + cnt++; + } + str = malloc(cnt); + if (!str) return 1; + if ( child->argv == NULL) { + child->argc=0; + } + argc = ++child->argc; + child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv)); + if (child->argv == NULL) return 1; + child->argv_nonnull = realloc(child->argv_nonnull, + (argc+1)*sizeof(*child->argv_nonnull)); + if (child->argv_nonnull == NULL) + return 1; + child->argv[argc-1]=str; + child->argv_nonnull[argc-1] = dest->nonnull; + child->argv[argc]=NULL; + child->argv_nonnull[argc] = 0; + for (s = dest->data; s && *s; s++,str++) { + if (*s == '\\') s++; + *str = *s; + } + *str = '\0'; +#endif +#ifndef __U_BOOT__ + } + gr = xglob(dest, flags, glob_target); + if (gr != 0) return 1; +#endif + + b_reset(dest); +#ifndef __U_BOOT__ + if (ctx->pending_redirect) { + ctx->pending_redirect=NULL; + if (glob_target->gl_pathc != 1) { + error_msg("ambiguous redirect"); + return 1; + } + } else { + child->argv = glob_target->gl_pathv; + } +#endif + if (ctx->w == RES_FOR) { + done_word(dest,ctx); + done_pipe(ctx,PIPE_SEQ); + } + return 0; +} + +/* The only possible error here is out of memory, in which case + * xmalloc exits. */ +static int done_command(struct p_context *ctx) +{ + /* The child is really already in the pipe structure, so + * advance the pipe counter and make a new, null child. + * Only real trickiness here is that the uncommitted + * child structure, to which ctx->child points, is not + * counted in pi->num_progs. */ + struct pipe *pi=ctx->pipe; + struct child_prog *prog=ctx->child; + + if (prog && prog->group == NULL + && prog->argv == NULL +#ifndef __U_BOOT__ + && prog->redirects == NULL) { +#else + ) { +#endif + debug_printf("done_command: skipping null command\n"); + return 0; + } else if (prog) { + pi->num_progs++; + debug_printf("done_command: num_progs incremented to %d\n",pi->num_progs); + } else { + debug_printf("done_command: initializing\n"); + } + pi->progs = xrealloc(pi->progs, sizeof(*pi->progs) * (pi->num_progs+1)); + + prog = pi->progs + pi->num_progs; +#ifndef __U_BOOT__ + prog->redirects = NULL; +#endif + prog->argv = NULL; + prog->argv_nonnull = NULL; +#ifndef __U_BOOT__ + prog->is_stopped = 0; +#endif + prog->group = NULL; +#ifndef __U_BOOT__ + prog->glob_result.gl_pathv = NULL; + prog->family = pi; +#endif + prog->sp = 0; + ctx->child = prog; + prog->type = ctx->type; + + /* but ctx->pipe and ctx->list_head remain unchanged */ + return 0; +} + +static int done_pipe(struct p_context *ctx, pipe_style type) +{ + struct pipe *new_p; + done_command(ctx); /* implicit closure of previous command */ + debug_printf("done_pipe, type %d\n", type); + ctx->pipe->followup = type; + ctx->pipe->r_mode = ctx->w; + new_p=new_pipe(); + ctx->pipe->next = new_p; + ctx->pipe = new_p; + ctx->child = NULL; + done_command(ctx); /* set up new pipe to accept commands */ + return 0; +} + +#ifndef __U_BOOT__ +/* peek ahead in the in_str to find out if we have a "&n" construct, + * as in "2>&1", that represents duplicating a file descriptor. + * returns either -2 (syntax error), -1 (no &), or the number found. + */ +static int redirect_dup_num(struct in_str *input) +{ + int ch, d=0, ok=0; + ch = b_peek(input); + if (ch != '&') return -1; + + b_getch(input); /* get the & */ + ch=b_peek(input); + if (ch == '-') { + b_getch(input); + return -3; /* "-" represents "close me" */ + } + while (isdigit(ch)) { + d = d*10+(ch-'0'); + ok=1; + b_getch(input); + ch = b_peek(input); + } + if (ok) return d; + + error_msg("ambiguous redirect"); + return -2; +} + +/* If a redirect is immediately preceded by a number, that number is + * supposed to tell which file descriptor to redirect. This routine + * looks for such preceding numbers. In an ideal world this routine + * needs to handle all the following classes of redirects... + * echo 2>foo # redirects fd 2 to file "foo", nothing passed to echo + * echo 49>foo # redirects fd 49 to file "foo", nothing passed to echo + * echo -2>foo # redirects fd 1 to file "foo", "-2" passed to echo + * echo 49x>foo # redirects fd 1 to file "foo", "49x" passed to echo + * A -1 output from this program means no valid number was found, so the + * caller should use the appropriate default for this redirection. + */ +static int redirect_opt_num(o_string *o) +{ + int num; + + if (o->length==0) return -1; + for(num=0; numlength; num++) { + if (!isdigit(*(o->data+num))) { + return -1; + } + } + /* reuse num (and save an int) */ + num=atoi(o->data); + b_reset(o); + return num; +} + +FILE *generate_stream_from_list(struct pipe *head) +{ + FILE *pf; +#if 1 + int pid, channel[2]; + if (pipe(channel)<0) perror_msg_and_die("pipe"); + pid=fork(); + if (pid<0) { + perror_msg_and_die("fork"); + } else if (pid==0) { + close(channel[0]); + if (channel[1] != 1) { + dup2(channel[1],1); + close(channel[1]); + } +#if 0 +#define SURROGATE "surrogate response" + write(1,SURROGATE,sizeof(SURROGATE)); + _exit(run_list(head)); +#else + _exit(run_list_real(head)); /* leaks memory */ +#endif + } + debug_printf("forked child %d\n",pid); + close(channel[1]); + pf = fdopen(channel[0],"r"); + debug_printf("pipe on FILE *%p\n",pf); +#else + free_pipe_list(head,0); + pf=popen("echo surrogate response","r"); + debug_printf("started fake pipe on FILE *%p\n",pf); +#endif + return pf; +} + +/* this version hacked for testing purposes */ +/* return code is exit status of the process that is run. */ +static int process_command_subs(o_string *dest, struct p_context *ctx, struct in_str *input, int subst_end) +{ + int retcode; + o_string result=NULL_O_STRING; + struct p_context inner; + FILE *p; + struct in_str pipe_str; + initialize_context(&inner); + + /* recursion to generate command */ + retcode = parse_stream(&result, &inner, input, subst_end); + if (retcode != 0) return retcode; /* syntax error or EOF */ + done_word(&result, &inner); + done_pipe(&inner, PIPE_SEQ); + b_free(&result); + + p=generate_stream_from_list(inner.list_head); + if (p==NULL) return 1; + mark_open(fileno(p)); + setup_file_in_str(&pipe_str, p); + + /* now send results of command back into original context */ + retcode = parse_stream(dest, ctx, &pipe_str, '\0'); + /* XXX In case of a syntax error, should we try to kill the child? + * That would be tough to do right, so just read until EOF. */ + if (retcode == 1) { + while (b_getch(&pipe_str)!=EOF) { /* discard */ }; + } + + debug_printf("done reading from pipe, pclose()ing\n"); + /* This is the step that wait()s for the child. Should be pretty + * safe, since we just read an EOF from its stdout. We could try + * to better, by using wait(), and keeping track of background jobs + * at the same time. That would be a lot of work, and contrary + * to the KISS philosophy of this program. */ + mark_closed(fileno(p)); + retcode=pclose(p); + free_pipe_list(inner.list_head,0); + debug_printf("pclosed, retcode=%d\n",retcode); + /* XXX this process fails to trim a single trailing newline */ + return retcode; +} + +static int parse_group(o_string *dest, struct p_context *ctx, + struct in_str *input, int ch) +{ + int rcode, endch=0; + struct p_context sub; + struct child_prog *child = ctx->child; + if (child->argv) { + syntax(); + return 1; /* syntax error, groups and arglists don't mix */ + } + initialize_context(&sub); + switch(ch) { + case '(': endch=')'; child->subshell=1; break; + case '{': endch='}'; break; + default: syntax(); /* really logic error */ + } + rcode=parse_stream(dest,&sub,input,endch); + done_word(dest,&sub); /* finish off the final word in the subcontext */ + done_pipe(&sub, PIPE_SEQ); /* and the final command there, too */ + child->group = sub.list_head; + return rcode; + /* child remains "open", available for possible redirects */ +} +#endif + +/* basically useful version until someone wants to get fancier, + * see the bash man page under "Parameter Expansion" */ +static char *lookup_param(char *src) +{ + char *p; + char *sep; + char *default_val = NULL; + int assign = 0; + int expand_empty = 0; + + if (!src) + return NULL; + + sep = strchr(src, ':'); + + if (sep) { + *sep = '\0'; + if (*(sep + 1) == '-') + default_val = sep+2; + if (*(sep + 1) == '=') { + default_val = sep+2; + assign = 1; + } + if (*(sep + 1) == '+') { + default_val = sep+2; + expand_empty = 1; + } + } + + p = getenv(src); + if (!p) + p = get_local_var(src); + + if (!p || strlen(p) == 0) { + p = default_val; + if (assign) { + char *var = malloc(strlen(src)+strlen(default_val)+2); + if (var) { + sprintf(var, "%s=%s", src, default_val); + set_local_var(var, 0); + } + free(var); + } + } else if (expand_empty) { + p += strlen(p); + } + + if (sep) + *sep = ':'; + + return p; +} + +#ifdef __U_BOOT__ +static char *get_dollar_var(char ch) +{ + static char buf[40]; + + buf[0] = '\0'; + switch (ch) { + case '?': + sprintf(buf, "%u", (unsigned int)last_return_code); + break; + default: + return NULL; + } + return buf; +} +#endif + +/* return code: 0 for OK, 1 for syntax error */ +static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input) +{ +#ifndef __U_BOOT__ + int i, advance=0; +#else + int advance=0; +#endif +#ifndef __U_BOOT__ + char sep[]=" "; +#endif + int ch = input->peek(input); /* first character after the $ */ + debug_printf("handle_dollar: ch=%c\n",ch); + if (isalpha(ch)) { + b_addchr(dest, SPECIAL_VAR_SYMBOL); + ctx->child->sp++; + while(ch=b_peek(input),isalnum(ch) || ch=='_') { + b_getch(input); + b_addchr(dest,ch); + } + b_addchr(dest, SPECIAL_VAR_SYMBOL); +#ifndef __U_BOOT__ + } else if (isdigit(ch)) { + i = ch-'0'; /* XXX is $0 special? */ + if (i 0) b_adduint(dest, last_bg_pid); + advance = 1; + break; +#endif + case '?': +#ifndef __U_BOOT__ + b_adduint(dest,last_return_code); +#else + ctx->child->sp++; + b_addchr(dest, SPECIAL_VAR_SYMBOL); + b_addchr(dest, '$'); + b_addchr(dest, '?'); + b_addchr(dest, SPECIAL_VAR_SYMBOL); +#endif + advance = 1; + break; +#ifndef __U_BOOT__ + case '#': + b_adduint(dest,global_argc ? global_argc-1 : 0); + advance = 1; + break; +#endif + case '{': + b_addchr(dest, SPECIAL_VAR_SYMBOL); + ctx->child->sp++; + b_getch(input); + /* XXX maybe someone will try to escape the '}' */ + while(ch=b_getch(input),ch!=EOF && ch!='}') { + b_addchr(dest,ch); + } + if (ch != '}') { + syntax(); + return 1; + } + b_addchr(dest, SPECIAL_VAR_SYMBOL); + break; +#ifndef __U_BOOT__ + case '(': + b_getch(input); + process_command_subs(dest, ctx, input, ')'); + break; + case '*': + sep[0]=ifs[0]; + for (i=1; iquote); + } + /* Eat the character if the flag was set. If the compiler + * is smart enough, we could substitute "b_getch(input);" + * for all the "advance = 1;" above, and also end up with + * a nice size-optimized program. Hah! That'll be the day. + */ + if (advance) b_getch(input); + return 0; +} + +#ifndef __U_BOOT__ +int parse_string(o_string *dest, struct p_context *ctx, const char *src) +{ + struct in_str foo; + setup_string_in_str(&foo, src); + return parse_stream(dest, ctx, &foo, '\0'); +} +#endif + +/* return code is 0 for normal exit, 1 for syntax error */ +static int parse_stream(o_string *dest, struct p_context *ctx, + struct in_str *input, int end_trigger) +{ + unsigned int ch, m; +#ifndef __U_BOOT__ + int redir_fd; + redir_type redir_style; +#endif + int next; + + /* Only double-quote state is handled in the state variable dest->quote. + * A single-quote triggers a bypass of the main loop until its mate is + * found. When recursing, quote state is passed in via dest->quote. */ + + debug_printf("parse_stream, end_trigger=%d\n",end_trigger); + while ((ch=b_getch(input))!=EOF) { + m = map[ch]; +#ifdef __U_BOOT__ + if (input->__promptme == 0) return 1; +#endif + next = (ch == '\n') ? 0 : b_peek(input); + + debug_printf("parse_stream: ch=%c (%d) m=%d quote=%d - %c\n", + ch >= ' ' ? ch : '.', ch, m, + dest->quote, ctx->stack == NULL ? '*' : '.'); + + if (m==0 || ((m==1 || m==2) && dest->quote)) { + b_addqchr(dest, ch, dest->quote); + } else { + if (m==2) { /* unquoted IFS */ + if (done_word(dest, ctx)) { + return 1; + } + /* If we aren't performing a substitution, treat a newline as a + * command separator. */ + if (end_trigger != '\0' && ch=='\n') + done_pipe(ctx,PIPE_SEQ); + } + if (ch == end_trigger && !dest->quote && ctx->w==RES_NONE) { + debug_printf("leaving parse_stream (triggered)\n"); + return 0; + } +#if 0 + if (ch=='\n') { + /* Yahoo! Time to run with it! */ + done_pipe(ctx,PIPE_SEQ); + run_list(ctx->list_head); + initialize_context(ctx); + } +#endif + if (m!=2) switch (ch) { + case '#': + if (dest->length == 0 && !dest->quote) { + while(ch=b_peek(input),ch!=EOF && ch!='\n') { b_getch(input); } + } else { + b_addqchr(dest, ch, dest->quote); + } + break; + case '\\': + if (next == EOF) { + syntax(); + return 1; + } + b_addqchr(dest, '\\', dest->quote); + b_addqchr(dest, b_getch(input), dest->quote); + break; + case '$': + if (handle_dollar(dest, ctx, input)!=0) return 1; + break; + case '\'': + dest->nonnull = 1; + while(ch=b_getch(input),ch!=EOF && ch!='\'') { +#ifdef __U_BOOT__ + if(input->__promptme == 0) return 1; +#endif + b_addchr(dest,ch); + } + if (ch==EOF) { + syntax(); + return 1; + } + break; + case '"': + dest->nonnull = 1; + dest->quote = !dest->quote; + break; +#ifndef __U_BOOT__ + case '`': + process_command_subs(dest, ctx, input, '`'); + break; + case '>': + redir_fd = redirect_opt_num(dest); + done_word(dest, ctx); + redir_style=REDIRECT_OVERWRITE; + if (next == '>') { + redir_style=REDIRECT_APPEND; + b_getch(input); + } else if (next == '(') { + syntax(); /* until we support >(list) Process Substitution */ + return 1; + } + setup_redirect(ctx, redir_fd, redir_style, input); + break; + case '<': + redir_fd = redirect_opt_num(dest); + done_word(dest, ctx); + redir_style=REDIRECT_INPUT; + if (next == '<') { + redir_style=REDIRECT_HEREIS; + b_getch(input); + } else if (next == '>') { + redir_style=REDIRECT_IO; + b_getch(input); + } else if (next == '(') { + syntax(); /* until we support <(list) Process Substitution */ + return 1; + } + setup_redirect(ctx, redir_fd, redir_style, input); + break; +#endif + case ';': + done_word(dest, ctx); + done_pipe(ctx,PIPE_SEQ); + break; + case '&': + done_word(dest, ctx); + if (next=='&') { + b_getch(input); + done_pipe(ctx,PIPE_AND); + } else { +#ifndef __U_BOOT__ + done_pipe(ctx,PIPE_BG); +#else + syntax_err(); + return 1; +#endif + } + break; + case '|': + done_word(dest, ctx); + if (next=='|') { + b_getch(input); + done_pipe(ctx,PIPE_OR); + } else { + /* we could pick up a file descriptor choice here + * with redirect_opt_num(), but bash doesn't do it. + * "echo foo 2| cat" yields "foo 2". */ +#ifndef __U_BOOT__ + done_command(ctx); +#else + syntax_err(); + return 1; +#endif + } + break; +#ifndef __U_BOOT__ + case '(': + case '{': + if (parse_group(dest, ctx, input, ch)!=0) return 1; + break; + case ')': + case '}': + syntax(); /* Proper use of this character caught by end_trigger */ + return 1; + break; +#endif + case SUBSTED_VAR_SYMBOL: + dest->nonnull = 1; + while (ch = b_getch(input), ch != EOF && + ch != SUBSTED_VAR_SYMBOL) { + debug_printf("subst, pass=%d\n", ch); + if (input->__promptme == 0) + return 1; + b_addchr(dest, ch); + } + debug_printf("subst, term=%d\n", ch); + if (ch == EOF) { + syntax(); + return 1; + } + break; + default: + syntax(); /* this is really an internal logic error */ + return 1; + } + } + } + /* complain if quote? No, maybe we just finished a command substitution + * that was quoted. Example: + * $ echo "`cat foo` plus more" + * and we just got the EOF generated by the subshell that ran "cat foo" + * The only real complaint is if we got an EOF when end_trigger != '\0', + * that is, we were really supposed to get end_trigger, and never got + * one before the EOF. Can't use the standard "syntax error" return code, + * so that parse_stream_outer can distinguish the EOF and exit smoothly. */ + debug_printf("leaving parse_stream (EOF)\n"); + if (end_trigger != '\0') return -1; + return 0; +} + +static void mapset(const unsigned char *set, int code) +{ + const unsigned char *s; + for (s=set; *s; s++) map[*s] = code; +} + +static void update_ifs_map(void) +{ + /* char *ifs and char map[256] are both globals. */ + ifs = (uchar *)getenv("IFS"); + if (ifs == NULL) ifs=(uchar *)" \t\n"; + /* Precompute a list of 'flow through' behavior so it can be treated + * quickly up front. Computation is necessary because of IFS. + * Special case handling of IFS == " \t\n" is not implemented. + * The map[] array only really needs two bits each, and on most machines + * that would be faster because of the reduced L1 cache footprint. + */ + memset(map,0,sizeof(map)); /* most characters flow through always */ +#ifndef __U_BOOT__ + mapset((uchar *)"\\$'\"`", 3); /* never flow through */ + mapset((uchar *)"<>;&|(){}#", 1); /* flow through if quoted */ +#else + { + uchar subst[2] = {SUBSTED_VAR_SYMBOL, 0}; + mapset(subst, 3); /* never flow through */ + } + mapset((uchar *)"\\$'\"", 3); /* never flow through */ + mapset((uchar *)";&|#", 1); /* flow through if quoted */ +#endif + mapset(ifs, 2); /* also flow through if quoted */ +} + +/* most recursion does not come through here, the exeception is + * from builtin_source() */ +static int parse_stream_outer(struct in_str *inp, int flag) +{ + + struct p_context ctx; + o_string temp=NULL_O_STRING; + int rcode; +#ifdef __U_BOOT__ + int code = 1; +#endif + do { + ctx.type = flag; + initialize_context(&ctx); + update_ifs_map(); + if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset((uchar *)";$&|", 0); + inp->promptmode=1; + rcode = parse_stream(&temp, &ctx, inp, + flag & FLAG_CONT_ON_NEWLINE ? -1 : '\n'); +#ifdef __U_BOOT__ + if (rcode == 1) flag_repeat = 0; +#endif + if (rcode != 1 && ctx.old_flag != 0) { + syntax(); +#ifdef __U_BOOT__ + flag_repeat = 0; +#endif + } + if (rcode != 1 && ctx.old_flag == 0) { + done_word(&temp, &ctx); + done_pipe(&ctx,PIPE_SEQ); +#ifndef __U_BOOT__ + run_list(ctx.list_head); +#else + code = run_list(ctx.list_head); + if (code == -2) { /* exit */ + b_free(&temp); + code = 0; + /* XXX hackish way to not allow exit from main loop */ + if (inp->peek == file_peek) { + printf("exit not allowed from main input shell.\n"); + continue; + } + break; + } + if (code == -1) + flag_repeat = 0; +#endif + } else { + if (ctx.old_flag != 0) { + free(ctx.stack); + b_reset(&temp); + } +#ifdef __U_BOOT__ + if (inp->__promptme == 0) printf("\n"); + inp->__promptme = 1; +#endif + temp.nonnull = 0; + temp.quote = 0; + inp->p = NULL; + free_pipe_list(ctx.list_head,0); + } + b_free(&temp); + /* loop on syntax errors, return on EOF */ + } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP) && + (inp->peek != static_peek || b_peek(inp))); +#ifndef __U_BOOT__ + return 0; +#else + return (code != 0) ? 1 : 0; +#endif /* __U_BOOT__ */ +} + +#ifndef __U_BOOT__ +static int parse_string_outer(const char *s, int flag) +#else +int parse_string_outer(const char *s, int flag) +#endif /* __U_BOOT__ */ +{ + struct in_str input; +#ifdef __U_BOOT__ + char *p = NULL; + int rcode; + if (!s) + return 1; + if (!*s) + return 0; + if (!(p = strchr(s, '\n')) || *++p) { + p = xmalloc(strlen(s) + 2); + strcpy(p, s); + strcat(p, "\n"); + setup_string_in_str(&input, p); + rcode = parse_stream_outer(&input, flag); + free(p); + return rcode; + } else { +#endif + setup_string_in_str(&input, s); + return parse_stream_outer(&input, flag); +#ifdef __U_BOOT__ + } +#endif +} + +#ifndef __U_BOOT__ +static int parse_file_outer(FILE *f) +#else +int parse_file_outer(void) +#endif +{ + int rcode; + struct in_str input; +#ifndef __U_BOOT__ + setup_file_in_str(&input, f); +#else + setup_file_in_str(&input); +#endif + rcode = parse_stream_outer(&input, FLAG_PARSE_SEMICOLON); + return rcode; +} + +#ifdef __U_BOOT__ +#ifdef CONFIG_NEEDS_MANUAL_RELOC +static void u_boot_hush_reloc(void) +{ + unsigned long addr; + struct reserved_combo *r; + + for (r=reserved_list; rliteral) + gd->reloc_off; + r->literal = (char *)addr; + } +} +#endif + +int u_boot_hush_start(void) +{ + if (top_vars == NULL) { + top_vars = malloc(sizeof(struct variables)); + top_vars->name = "HUSH_VERSION"; + top_vars->value = "0.01"; + top_vars->next = NULL; + top_vars->flg_export = 0; + top_vars->flg_read_only = 1; +#ifdef CONFIG_NEEDS_MANUAL_RELOC + u_boot_hush_reloc(); +#endif + } + return 0; +} + +static void *xmalloc(size_t size) +{ + void *p = NULL; + + if (!(p = malloc(size))) { + printf("ERROR : memory not allocated\n"); + for(;;); + } + return p; +} + +static void *xrealloc(void *ptr, size_t size) +{ + void *p = NULL; + + if (!(p = realloc(ptr, size))) { + printf("ERROR : memory not allocated\n"); + for(;;); + } + return p; +} +#endif /* __U_BOOT__ */ + +#ifndef __U_BOOT__ +/* Make sure we have a controlling tty. If we get started under a job + * aware app (like bash for example), make sure we are now in charge so + * we don't fight over who gets the foreground */ +static void setup_job_control(void) +{ + static pid_t shell_pgrp; + /* Loop until we are in the foreground. */ + while (tcgetpgrp (shell_terminal) != (shell_pgrp = getpgrp ())) + kill (- shell_pgrp, SIGTTIN); + + /* Ignore interactive and job-control signals. */ + signal(SIGINT, SIG_IGN); + signal(SIGQUIT, SIG_IGN); + signal(SIGTERM, SIG_IGN); + signal(SIGTSTP, SIG_IGN); + signal(SIGTTIN, SIG_IGN); + signal(SIGTTOU, SIG_IGN); + signal(SIGCHLD, SIG_IGN); + + /* Put ourselves in our own process group. */ + setsid(); + shell_pgrp = getpid (); + setpgid (shell_pgrp, shell_pgrp); + + /* Grab control of the terminal. */ + tcsetpgrp(shell_terminal, shell_pgrp); +} + +int hush_main(int argc, char * const *argv) +{ + int opt; + FILE *input; + char **e = environ; + + /* XXX what should these be while sourcing /etc/profile? */ + global_argc = argc; + global_argv = argv; + + /* (re?) initialize globals. Sometimes hush_main() ends up calling + * hush_main(), therefore we cannot rely on the BSS to zero out this + * stuff. Reset these to 0 every time. */ + ifs = NULL; + /* map[] is taken care of with call to update_ifs_map() */ + fake_mode = 0; + interactive = 0; + close_me_head = NULL; + last_bg_pid = 0; + job_list = NULL; + last_jobid = 0; + + /* Initialize some more globals to non-zero values */ + set_cwd(); +#ifdef CONFIG_FEATURE_COMMAND_EDITING + cmdedit_set_initial_prompt(); +#else + PS1 = NULL; +#endif + PS2 = "> "; + + /* initialize our shell local variables with the values + * currently living in the environment */ + if (e) { + for (; *e; e++) + set_local_var(*e, 2); /* without call putenv() */ + } + + last_return_code=EXIT_SUCCESS; + + + if (argv[0] && argv[0][0] == '-') { + debug_printf("\nsourcing /etc/profile\n"); + if ((input = fopen("/etc/profile", "r")) != NULL) { + mark_open(fileno(input)); + parse_file_outer(input); + mark_closed(fileno(input)); + fclose(input); + } + } + input=stdin; + + while ((opt = getopt(argc, argv, "c:xif")) > 0) { + switch (opt) { + case 'c': + { + global_argv = argv+optind; + global_argc = argc-optind; + opt = parse_string_outer(optarg, FLAG_PARSE_SEMICOLON); + goto final_return; + } + break; + case 'i': + interactive++; + break; + case 'f': + fake_mode++; + break; + default: +#ifndef BB_VER + fprintf(stderr, "Usage: sh [FILE]...\n" + " or: sh -c command [args]...\n\n"); + exit(EXIT_FAILURE); +#else + show_usage(); +#endif + } + } + /* A shell is interactive if the `-i' flag was given, or if all of + * the following conditions are met: + * no -c command + * no arguments remaining or the -s flag given + * standard input is a terminal + * standard output is a terminal + * Refer to Posix.2, the description of the `sh' utility. */ + if (argv[optind]==NULL && input==stdin && + isatty(fileno(stdin)) && isatty(fileno(stdout))) { + interactive++; + } + + debug_printf("\ninteractive=%d\n", interactive); + if (interactive) { + /* Looks like they want an interactive shell */ +#ifndef CONFIG_FEATURE_SH_EXTRA_QUIET + printf( "\n\n" BB_BANNER " hush - the humble shell v0.01 (testing)\n"); + printf( "Enter 'help' for a list of built-in commands.\n\n"); +#endif + setup_job_control(); + } + + if (argv[optind]==NULL) { + opt=parse_file_outer(stdin); + goto final_return; + } + + debug_printf("\nrunning script '%s'\n", argv[optind]); + global_argv = argv+optind; + global_argc = argc-optind; + input = xfopen(argv[optind], "r"); + opt = parse_file_outer(input); + +#ifdef CONFIG_FEATURE_CLEAN_UP + fclose(input); + if (cwd && cwd != unknown) + free((char*)cwd); + { + struct variables *cur, *tmp; + for(cur = top_vars; cur; cur = tmp) { + tmp = cur->next; + if (!cur->flg_read_only) { + free(cur->name); + free(cur->value); + free(cur); + } + } + } +#endif + +final_return: + return(opt?opt:last_return_code); +} +#endif + +static char *insert_var_value(char *inp) +{ + return insert_var_value_sub(inp, 0); +} + +static char *insert_var_value_sub(char *inp, int tag_subst) +{ + int res_str_len = 0; + int len; + int done = 0; + char *p, *p1, *res_str = NULL; + + while ((p = strchr(inp, SPECIAL_VAR_SYMBOL))) { + /* check the beginning of the string for normal charachters */ + if (p != inp) { + /* copy any charachters to the result string */ + len = p - inp; + res_str = xrealloc(res_str, (res_str_len + len)); + strncpy((res_str + res_str_len), inp, len); + res_str_len += len; + } + inp = ++p; + /* find the ending marker */ + p = strchr(inp, SPECIAL_VAR_SYMBOL); + *p = '\0'; + /* look up the value to substitute */ + if ((p1 = lookup_param(inp))) { + if (tag_subst) + len = res_str_len + strlen(p1) + 2; + else + len = res_str_len + strlen(p1); + res_str = xrealloc(res_str, (1 + len)); + if (tag_subst) { + /* + * copy the variable value to the result + * string + */ + strcpy((res_str + res_str_len + 1), p1); + + /* + * mark the replaced text to be accepted as + * is + */ + res_str[res_str_len] = SUBSTED_VAR_SYMBOL; + res_str[res_str_len + 1 + strlen(p1)] = + SUBSTED_VAR_SYMBOL; + } else + /* + * copy the variable value to the result + * string + */ + strcpy((res_str + res_str_len), p1); + + res_str_len = len; + } + *p = SPECIAL_VAR_SYMBOL; + inp = ++p; + done = 1; + } + if (done) { + res_str = xrealloc(res_str, (1 + res_str_len + strlen(inp))); + strcpy((res_str + res_str_len), inp); + while ((p = strchr(res_str, '\n'))) { + *p = ' '; + } + } + return (res_str == NULL) ? inp : res_str; +} + +static char **make_list_in(char **inp, char *name) +{ + int len, i; + int name_len = strlen(name); + int n = 0; + char **list; + char *p1, *p2, *p3; + + /* create list of variable values */ + list = xmalloc(sizeof(*list)); + for (i = 0; inp[i]; i++) { + p3 = insert_var_value(inp[i]); + p1 = p3; + while (*p1) { + if (*p1 == ' ') { + p1++; + continue; + } + if ((p2 = strchr(p1, ' '))) { + len = p2 - p1; + } else { + len = strlen(p1); + p2 = p1 + len; + } + /* we use n + 2 in realloc for list,because we add + * new element and then we will add NULL element */ + list = xrealloc(list, sizeof(*list) * (n + 2)); + list[n] = xmalloc(2 + name_len + len); + strcpy(list[n], name); + strcat(list[n], "="); + strncat(list[n], p1, len); + list[n++][name_len + len + 1] = '\0'; + p1 = p2; + } + if (p3 != inp[i]) free(p3); + } + list[n] = NULL; + return list; +} + +/* + * Make new string for parser + * inp - array of argument strings to flatten + * nonnull - indicates argument was quoted when originally parsed + */ +static char *make_string(char **inp, int *nonnull) +{ + char *p; + char *str = NULL; + int n; + int len = 2; + char *noeval_str; + int noeval = 0; + + noeval_str = get_local_var("HUSH_NO_EVAL"); + if (noeval_str != NULL && *noeval_str != '0' && *noeval_str != '\0') + noeval = 1; + for (n = 0; inp[n]; n++) { + p = insert_var_value_sub(inp[n], noeval); + str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n]))); + if (n) { + strcat(str, " "); + } else { + *str = '\0'; + } + if (nonnull[n]) + strcat(str, "'"); + strcat(str, p); + if (nonnull[n]) + strcat(str, "'"); + len = strlen(str) + 3; + if (p != inp[n]) free(p); + } + len = strlen(str); + *(str + len) = '\n'; + *(str + len + 1) = '\0'; + return str; +} + +#ifdef __U_BOOT__ +static int do_showvar(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int i, k; + int rcode = 0; + struct variables *cur; + + if (argc == 1) { /* Print all env variables */ + for (cur = top_vars; cur; cur = cur->next) { + printf ("%s=%s\n", cur->name, cur->value); + if (ctrlc ()) { + puts ("\n ** Abort\n"); + return 1; + } + } + return 0; + } + for (i = 1; i < argc; ++i) { /* print single env variables */ + char *name = argv[i]; + + k = -1; + for (cur = top_vars; cur; cur = cur->next) { + if(strcmp (cur->name, name) == 0) { + k = 0; + printf ("%s=%s\n", cur->name, cur->value); + } + if (ctrlc ()) { + puts ("\n ** Abort\n"); + return 1; + } + } + if (k < 0) { + printf ("## Error: \"%s\" not defined\n", name); + rcode ++; + } + } + return rcode; +} + +U_BOOT_CMD( + showvar, CONFIG_SYS_MAXARGS, 1, do_showvar, + "print local hushshell variables", + "\n - print values of all hushshell variables\n" + "showvar name ...\n" + " - print value of hushshell variable 'name'" +); + +#endif +/****************************************************************************/ diff --git a/common/cli_readline.c b/common/cli_readline.c new file mode 100644 index 0000000000..4e821a5cfc --- /dev/null +++ b/common/cli_readline.c @@ -0,0 +1,627 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const char erase_seq[] = "\b \b"; /* erase sequence */ +static const char tab_seq[] = " "; /* used to expand TABs */ + +char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */ + +static char *delete_char (char *buffer, char *p, int *colp, int *np, int plen) +{ + char *s; + + if (*np == 0) + return p; + + if (*(--p) == '\t') { /* will retype the whole line */ + while (*colp > plen) { + puts(erase_seq); + (*colp)--; + } + for (s = buffer; s < p; ++s) { + if (*s == '\t') { + puts(tab_seq + ((*colp) & 07)); + *colp += 8 - ((*colp) & 07); + } else { + ++(*colp); + putc(*s); + } + } + } else { + puts(erase_seq); + (*colp)--; + } + (*np)--; + + return p; +} + +#ifdef CONFIG_CMDLINE_EDITING + +/* + * cmdline-editing related codes from vivi. + * Author: Janghoon Lyu + */ + +#define putnstr(str, n) printf("%.*s", (int)n, str) + +#define CTL_CH(c) ((c) - 'a' + 1) +#define CTL_BACKSPACE ('\b') +#define DEL ((char)255) +#define DEL7 ((char)127) +#define CREAD_HIST_CHAR ('!') + +#define getcmd_putch(ch) putc(ch) +#define getcmd_getch() getc() +#define getcmd_cbeep() getcmd_putch('\a') + +#define HIST_MAX 20 +#define HIST_SIZE CONFIG_SYS_CBSIZE + +static int hist_max; +static int hist_add_idx; +static int hist_cur = -1; +static unsigned hist_num; + +static char *hist_list[HIST_MAX]; +static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */ + +#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1) + +static void hist_init(void) +{ + int i; + + hist_max = 0; + hist_add_idx = 0; + hist_cur = -1; + hist_num = 0; + + for (i = 0; i < HIST_MAX; i++) { + hist_list[i] = hist_lines[i]; + hist_list[i][0] = '\0'; + } +} + +static void cread_add_to_hist(char *line) +{ + strcpy(hist_list[hist_add_idx], line); + + if (++hist_add_idx >= HIST_MAX) + hist_add_idx = 0; + + if (hist_add_idx > hist_max) + hist_max = hist_add_idx; + + hist_num++; +} + +static char *hist_prev(void) +{ + char *ret; + int old_cur; + + if (hist_cur < 0) + return NULL; + + old_cur = hist_cur; + if (--hist_cur < 0) + hist_cur = hist_max; + + if (hist_cur == hist_add_idx) { + hist_cur = old_cur; + ret = NULL; + } else { + ret = hist_list[hist_cur]; + } + + return ret; +} + +static char *hist_next(void) +{ + char *ret; + + if (hist_cur < 0) + return NULL; + + if (hist_cur == hist_add_idx) + return NULL; + + if (++hist_cur > hist_max) + hist_cur = 0; + + if (hist_cur == hist_add_idx) + ret = ""; + else + ret = hist_list[hist_cur]; + + return ret; +} + +#ifndef CONFIG_CMDLINE_EDITING +static void cread_print_hist_list(void) +{ + int i; + unsigned long n; + + n = hist_num - hist_max; + + i = hist_add_idx + 1; + while (1) { + if (i > hist_max) + i = 0; + if (i == hist_add_idx) + break; + printf("%s\n", hist_list[i]); + n++; + i++; + } +} +#endif /* CONFIG_CMDLINE_EDITING */ + +#define BEGINNING_OF_LINE() { \ + while (num) { \ + getcmd_putch(CTL_BACKSPACE); \ + num--; \ + } \ +} + +#define ERASE_TO_EOL() { \ + if (num < eol_num) { \ + printf("%*s", (int)(eol_num - num), ""); \ + do { \ + getcmd_putch(CTL_BACKSPACE); \ + } while (--eol_num > num); \ + } \ +} + +#define REFRESH_TO_EOL() { \ + if (num < eol_num) { \ + wlen = eol_num - num; \ + putnstr(buf + num, wlen); \ + num = eol_num; \ + } \ +} + +static void cread_add_char(char ichar, int insert, unsigned long *num, + unsigned long *eol_num, char *buf, unsigned long len) +{ + unsigned long wlen; + + /* room ??? */ + if (insert || *num == *eol_num) { + if (*eol_num > len - 1) { + getcmd_cbeep(); + return; + } + (*eol_num)++; + } + + if (insert) { + wlen = *eol_num - *num; + if (wlen > 1) + memmove(&buf[*num+1], &buf[*num], wlen-1); + + buf[*num] = ichar; + putnstr(buf + *num, wlen); + (*num)++; + while (--wlen) + getcmd_putch(CTL_BACKSPACE); + } else { + /* echo the character */ + wlen = 1; + buf[*num] = ichar; + putnstr(buf + *num, wlen); + (*num)++; + } +} + +static void cread_add_str(char *str, int strsize, int insert, + unsigned long *num, unsigned long *eol_num, + char *buf, unsigned long len) +{ + while (strsize--) { + cread_add_char(*str, insert, num, eol_num, buf, len); + str++; + } +} + +static int cread_line(const char *const prompt, char *buf, unsigned int *len, + int timeout) +{ + unsigned long num = 0; + unsigned long eol_num = 0; + unsigned long wlen; + char ichar; + int insert = 1; + int esc_len = 0; + char esc_save[8]; + int init_len = strlen(buf); + int first = 1; + + if (init_len) + cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len); + + while (1) { + if (bootretry_tstc_timeout()) + return -2; /* timed out */ + if (first && timeout) { + uint64_t etime = endtick(timeout); + + while (!tstc()) { /* while no incoming data */ + if (get_ticks() >= etime) + return -2; /* timed out */ + WATCHDOG_RESET(); + } + first = 0; + } + +#ifdef CONFIG_SHOW_ACTIVITY + while (!tstc()) { /* while no incoming data */ + show_activity(0); + WATCHDOG_RESET(); + } +#endif + ichar = getcmd_getch(); + + if ((ichar == '\n') || (ichar == '\r')) { + putc('\n'); + break; + } + + /* + * handle standard linux xterm esc sequences for arrow key, etc. + */ + if (esc_len != 0) { + if (esc_len == 1) { + if (ichar == '[') { + esc_save[esc_len] = ichar; + esc_len = 2; + } else { + cread_add_str(esc_save, esc_len, + insert, &num, &eol_num, + buf, *len); + esc_len = 0; + } + continue; + } + + switch (ichar) { + case 'D': /* <- key */ + ichar = CTL_CH('b'); + esc_len = 0; + break; + case 'C': /* -> key */ + ichar = CTL_CH('f'); + esc_len = 0; + break; /* pass off to ^F handler */ + case 'H': /* Home key */ + ichar = CTL_CH('a'); + esc_len = 0; + break; /* pass off to ^A handler */ + case 'A': /* up arrow */ + ichar = CTL_CH('p'); + esc_len = 0; + break; /* pass off to ^P handler */ + case 'B': /* down arrow */ + ichar = CTL_CH('n'); + esc_len = 0; + break; /* pass off to ^N handler */ + default: + esc_save[esc_len++] = ichar; + cread_add_str(esc_save, esc_len, insert, + &num, &eol_num, buf, *len); + esc_len = 0; + continue; + } + } + + switch (ichar) { + case 0x1b: + if (esc_len == 0) { + esc_save[esc_len] = ichar; + esc_len = 1; + } else { + puts("impossible condition #876\n"); + esc_len = 0; + } + break; + + case CTL_CH('a'): + BEGINNING_OF_LINE(); + break; + case CTL_CH('c'): /* ^C - break */ + *buf = '\0'; /* discard input */ + return -1; + case CTL_CH('f'): + if (num < eol_num) { + getcmd_putch(buf[num]); + num++; + } + break; + case CTL_CH('b'): + if (num) { + getcmd_putch(CTL_BACKSPACE); + num--; + } + break; + case CTL_CH('d'): + if (num < eol_num) { + wlen = eol_num - num - 1; + if (wlen) { + memmove(&buf[num], &buf[num+1], wlen); + putnstr(buf + num, wlen); + } + + getcmd_putch(' '); + do { + getcmd_putch(CTL_BACKSPACE); + } while (wlen--); + eol_num--; + } + break; + case CTL_CH('k'): + ERASE_TO_EOL(); + break; + case CTL_CH('e'): + REFRESH_TO_EOL(); + break; + case CTL_CH('o'): + insert = !insert; + break; + case CTL_CH('x'): + case CTL_CH('u'): + BEGINNING_OF_LINE(); + ERASE_TO_EOL(); + break; + case DEL: + case DEL7: + case 8: + if (num) { + wlen = eol_num - num; + num--; + memmove(&buf[num], &buf[num+1], wlen); + getcmd_putch(CTL_BACKSPACE); + putnstr(buf + num, wlen); + getcmd_putch(' '); + do { + getcmd_putch(CTL_BACKSPACE); + } while (wlen--); + eol_num--; + } + break; + case CTL_CH('p'): + case CTL_CH('n'): + { + char *hline; + + esc_len = 0; + + if (ichar == CTL_CH('p')) + hline = hist_prev(); + else + hline = hist_next(); + + if (!hline) { + getcmd_cbeep(); + continue; + } + + /* nuke the current line */ + /* first, go home */ + BEGINNING_OF_LINE(); + + /* erase to end of line */ + ERASE_TO_EOL(); + + /* copy new line into place and display */ + strcpy(buf, hline); + eol_num = strlen(buf); + REFRESH_TO_EOL(); + continue; + } +#ifdef CONFIG_AUTO_COMPLETE + case '\t': { + int num2, col; + + /* do not autocomplete when in the middle */ + if (num < eol_num) { + getcmd_cbeep(); + break; + } + + buf[num] = '\0'; + col = strlen(prompt) + eol_num; + num2 = num; + if (cmd_auto_complete(prompt, buf, &num2, &col)) { + col = num2 - num; + num += col; + eol_num += col; + } + break; + } +#endif + default: + cread_add_char(ichar, insert, &num, &eol_num, buf, + *len); + break; + } + } + *len = eol_num; + buf[eol_num] = '\0'; /* lose the newline */ + + if (buf[0] && buf[0] != CREAD_HIST_CHAR) + cread_add_to_hist(buf); + hist_cur = hist_add_idx; + + return 0; +} + +#endif /* CONFIG_CMDLINE_EDITING */ + +/****************************************************************************/ + +int cli_readline(const char *const prompt) +{ + /* + * If console_buffer isn't 0-length the user will be prompted to modify + * it instead of entering it from scratch as desired. + */ + console_buffer[0] = '\0'; + + return cli_readline_into_buffer(prompt, console_buffer, 0); +} + + +int cli_readline_into_buffer(const char *const prompt, char *buffer, + int timeout) +{ + char *p = buffer; +#ifdef CONFIG_CMDLINE_EDITING + unsigned int len = CONFIG_SYS_CBSIZE; + int rc; + static int initted; + + /* + * History uses a global array which is not + * writable until after relocation to RAM. + * Revert to non-history version if still + * running from flash. + */ + if (gd->flags & GD_FLG_RELOC) { + if (!initted) { + hist_init(); + initted = 1; + } + + if (prompt) + puts(prompt); + + rc = cread_line(prompt, p, &len, timeout); + return rc < 0 ? rc : len; + + } else { +#endif /* CONFIG_CMDLINE_EDITING */ + char *p_buf = p; + int n = 0; /* buffer index */ + int plen = 0; /* prompt length */ + int col; /* output column cnt */ + char c; + + /* print prompt */ + if (prompt) { + plen = strlen(prompt); + puts(prompt); + } + col = plen; + + for (;;) { + if (bootretry_tstc_timeout()) + return -2; /* timed out */ + WATCHDOG_RESET(); /* Trigger watchdog, if needed */ + +#ifdef CONFIG_SHOW_ACTIVITY + while (!tstc()) { + show_activity(0); + WATCHDOG_RESET(); + } +#endif + c = getc(); + + /* + * Special character handling + */ + switch (c) { + case '\r': /* Enter */ + case '\n': + *p = '\0'; + puts("\r\n"); + return p - p_buf; + + case '\0': /* nul */ + continue; + + case 0x03: /* ^C - break */ + p_buf[0] = '\0'; /* discard input */ + return -1; + + case 0x15: /* ^U - erase line */ + while (col > plen) { + puts(erase_seq); + --col; + } + p = p_buf; + n = 0; + continue; + + case 0x17: /* ^W - erase word */ + p = delete_char(p_buf, p, &col, &n, plen); + while ((n > 0) && (*p != ' ')) + p = delete_char(p_buf, p, &col, &n, plen); + continue; + + case 0x08: /* ^H - backspace */ + case 0x7F: /* DEL - backspace */ + p = delete_char(p_buf, p, &col, &n, plen); + continue; + + default: + /* + * Must be a normal character then + */ + if (n < CONFIG_SYS_CBSIZE-2) { + if (c == '\t') { /* expand TABs */ +#ifdef CONFIG_AUTO_COMPLETE + /* + * if auto completion triggered just + * continue + */ + *p = '\0'; + if (cmd_auto_complete(prompt, + console_buffer, + &n, &col)) { + p = p_buf + n; /* reset */ + continue; + } +#endif + puts(tab_seq + (col & 07)); + col += 8 - (col & 07); + } else { + char buf[2]; + + /* + * Echo input using puts() to force an + * LCD flush if we are using an LCD + */ + ++col; + buf[0] = c; + buf[1] = '\0'; + puts(buf); + } + *p++ = c; + ++n; + } else { /* Buffer full */ + putc('\a'); + } + } + } +#ifdef CONFIG_CMDLINE_EDITING + } +#endif +} diff --git a/common/cli_simple.c b/common/cli_simple.c new file mode 100644 index 0000000000..6c65cc686c --- /dev/null +++ b/common/cli_simple.c @@ -0,0 +1,337 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define DEBUG_PARSER 0 /* set to 1 to debug */ + +#define debug_parser(fmt, args...) \ + debug_cond(DEBUG_PARSER, fmt, ##args) + + +int cli_simple_parse_line(char *line, char *argv[]) +{ + int nargs = 0; + + debug_parser("%s: \"%s\"\n", __func__, line); + while (nargs < CONFIG_SYS_MAXARGS) { + /* skip any white space */ + while (isblank(*line)) + ++line; + + if (*line == '\0') { /* end of line, no more args */ + argv[nargs] = NULL; + debug_parser("%s: nargs=%d\n", __func__, nargs); + return nargs; + } + + argv[nargs++] = line; /* begin of argument string */ + + /* find end of string */ + while (*line && !isblank(*line)) + ++line; + + if (*line == '\0') { /* end of line, no more args */ + argv[nargs] = NULL; + debug_parser("parse_line: nargs=%d\n", nargs); + return nargs; + } + + *line++ = '\0'; /* terminate current arg */ + } + + printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS); + + debug_parser("%s: nargs=%d\n", __func__, nargs); + return nargs; +} + +void cli_simple_process_macros(const char *input, char *output) +{ + char c, prev; + const char *varname_start = NULL; + int inputcnt = strlen(input); + int outputcnt = CONFIG_SYS_CBSIZE; + int state = 0; /* 0 = waiting for '$' */ + + /* 1 = waiting for '(' or '{' */ + /* 2 = waiting for ')' or '}' */ + /* 3 = waiting for ''' */ + char *output_start = output; + + debug_parser("[PROCESS_MACROS] INPUT len %zd: \"%s\"\n", strlen(input), + input); + + prev = '\0'; /* previous character */ + + while (inputcnt && outputcnt) { + c = *input++; + inputcnt--; + + if (state != 3) { + /* remove one level of escape characters */ + if ((c == '\\') && (prev != '\\')) { + if (inputcnt-- == 0) + break; + prev = c; + c = *input++; + } + } + + switch (state) { + case 0: /* Waiting for (unescaped) $ */ + if ((c == '\'') && (prev != '\\')) { + state = 3; + break; + } + if ((c == '$') && (prev != '\\')) { + state++; + } else { + *(output++) = c; + outputcnt--; + } + break; + case 1: /* Waiting for ( */ + if (c == '(' || c == '{') { + state++; + varname_start = input; + } else { + state = 0; + *(output++) = '$'; + outputcnt--; + + if (outputcnt) { + *(output++) = c; + outputcnt--; + } + } + break; + case 2: /* Waiting for ) */ + if (c == ')' || c == '}') { + int i; + char envname[CONFIG_SYS_CBSIZE], *envval; + /* Varname # of chars */ + int envcnt = input - varname_start - 1; + + /* Get the varname */ + for (i = 0; i < envcnt; i++) + envname[i] = varname_start[i]; + envname[i] = 0; + + /* Get its value */ + envval = getenv(envname); + + /* Copy into the line if it exists */ + if (envval != NULL) + while ((*envval) && outputcnt) { + *(output++) = *(envval++); + outputcnt--; + } + /* Look for another '$' */ + state = 0; + } + break; + case 3: /* Waiting for ' */ + if ((c == '\'') && (prev != '\\')) { + state = 0; + } else { + *(output++) = c; + outputcnt--; + } + break; + } + prev = c; + } + + if (outputcnt) + *output = 0; + else + *(output - 1) = 0; + + debug_parser("[PROCESS_MACROS] OUTPUT len %zd: \"%s\"\n", + strlen(output_start), output_start); +} + + /* + * WARNING: + * + * We must create a temporary copy of the command since the command we get + * may be the result from getenv(), which returns a pointer directly to + * the environment data, which may change magicly when the command we run + * creates or modifies environment variables (like "bootp" does). + */ +int cli_simple_run_command(const char *cmd, int flag) +{ + char cmdbuf[CONFIG_SYS_CBSIZE]; /* working copy of cmd */ + char *token; /* start of token in cmdbuf */ + char *sep; /* end of token (separator) in cmdbuf */ + char finaltoken[CONFIG_SYS_CBSIZE]; + char *str = cmdbuf; + char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ + int argc, inquotes; + int repeatable = 1; + int rc = 0; + + debug_parser("[RUN_COMMAND] cmd[%p]=\"", cmd); + if (DEBUG_PARSER) { + /* use puts - string may be loooong */ + puts(cmd ? cmd : "NULL"); + puts("\"\n"); + } + clear_ctrlc(); /* forget any previous Control C */ + + if (!cmd || !*cmd) + return -1; /* empty command */ + + if (strlen(cmd) >= CONFIG_SYS_CBSIZE) { + puts("## Command too long!\n"); + return -1; + } + + strcpy(cmdbuf, cmd); + + /* Process separators and check for invalid + * repeatable commands + */ + + debug_parser("[PROCESS_SEPARATORS] %s\n", cmd); + while (*str) { + /* + * Find separator, or string end + * Allow simple escape of ';' by writing "\;" + */ + for (inquotes = 0, sep = str; *sep; sep++) { + if ((*sep == '\'') && + (*(sep - 1) != '\\')) + inquotes = !inquotes; + + if (!inquotes && + (*sep == ';') && /* separator */ + (sep != str) && /* past string start */ + (*(sep - 1) != '\\')) /* and NOT escaped */ + break; + } + + /* + * Limit the token to data between separators + */ + token = str; + if (*sep) { + str = sep + 1; /* start of command for next pass */ + *sep = '\0'; + } else { + str = sep; /* no more commands for next pass */ + } + debug_parser("token: \"%s\"\n", token); + + /* find macros in this token and replace them */ + cli_simple_process_macros(token, finaltoken); + + /* Extract arguments */ + argc = cli_simple_parse_line(finaltoken, argv); + if (argc == 0) { + rc = -1; /* no command at all */ + continue; + } + + if (cmd_process(flag, argc, argv, &repeatable, NULL)) + rc = -1; + + /* Did the user stop this? */ + if (had_ctrlc()) + return -1; /* if stopped then not repeatable */ + } + + return rc ? rc : repeatable; +} + +void cli_simple_loop(void) +{ + static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, }; + + int len; + int flag; + int rc = 1; + + for (;;) { + if (rc >= 0) { + /* Saw enough of a valid command to + * restart the timeout. + */ + bootretry_reset_cmd_timeout(); + } + len = cli_readline(CONFIG_SYS_PROMPT); + + flag = 0; /* assume no special flags for now */ + if (len > 0) + strcpy(lastcommand, console_buffer); + else if (len == 0) + flag |= CMD_FLAG_REPEAT; +#ifdef CONFIG_BOOT_RETRY_TIME + else if (len == -2) { + /* -2 means timed out, retry autoboot + */ + puts("\nTimed out waiting for command\n"); +# ifdef CONFIG_RESET_TO_RETRY + /* Reinit board to run initialization code again */ + do_reset(NULL, 0, 0, NULL); +# else + return; /* retry autoboot */ +# endif + } +#endif + + if (len == -1) + puts("\n"); + else + rc = run_command_repeatable(lastcommand, flag); + + if (rc <= 0) { + /* invalid command or not repeatable, forget it */ + lastcommand[0] = 0; + } + } +} + +int cli_simple_run_command_list(char *cmd, int flag) +{ + char *line, *next; + int rcode = 0; + + /* + * Break into individual lines, and execute each line; terminate on + * error. + */ + next = cmd; + line = cmd; + while (*next) { + if (*next == '\n') { + *next = '\0'; + /* run only non-empty commands */ + if (*line) { + debug("** exec: \"%s\"\n", line); + if (cli_simple_run_command(line, 0) < 0) { + rcode = 1; + break; + } + } + line = next + 1; + } + ++next; + } + if (rcode == 0 && *line) + rcode = (cli_simple_run_command(line, 0) < 0); + + return rcode; +} diff --git a/common/cmd_aes.c b/common/cmd_aes.c new file mode 100644 index 0000000000..76da3efffe --- /dev/null +++ b/common/cmd_aes.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * Command for en/de-crypting block of memory with AES-128-CBC cipher. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * do_aes() - Handle the "aes" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_aes(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + uint32_t key_addr, src_addr, dst_addr, len; + uint8_t *key_ptr, *src_ptr, *dst_ptr; + uint8_t key_exp[AES_EXPAND_KEY_LENGTH]; + uint32_t aes_blocks; + int enc; + + if (argc != 6) + return CMD_RET_USAGE; + + if (!strncmp(argv[1], "enc", 3)) + enc = 1; + else if (!strncmp(argv[1], "dec", 3)) + enc = 0; + else + return CMD_RET_USAGE; + + key_addr = simple_strtoul(argv[2], NULL, 16); + src_addr = simple_strtoul(argv[3], NULL, 16); + dst_addr = simple_strtoul(argv[4], NULL, 16); + len = simple_strtoul(argv[5], NULL, 16); + + key_ptr = (uint8_t *)key_addr; + src_ptr = (uint8_t *)src_addr; + dst_ptr = (uint8_t *)dst_addr; + + /* First we expand the key. */ + aes_expand_key(key_ptr, key_exp); + + /* Calculate the number of AES blocks to encrypt. */ + aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH); + + if (enc) + aes_cbc_encrypt_blocks(key_exp, src_ptr, dst_ptr, aes_blocks); + else + aes_cbc_decrypt_blocks(key_exp, src_ptr, dst_ptr, aes_blocks); + + return 0; +} + +/***************************************************/ +#ifdef CONFIG_SYS_LONGHELP +static char aes_help_text[] = + "enc key src dst len - Encrypt block of data $len bytes long\n" + " at address $src using a key at address\n" + " $key and store the result at address\n" + " $dst. The $len size must be multiple of\n" + " 16 bytes and $key must be 16 bytes long.\n" + "aes dec key src dst len - Decrypt block of data $len bytes long\n" + " at address $src using a key at address\n" + " $key and store the result at address\n" + " $dst. The $len size must be multiple of\n" + " 16 bytes and $key must be 16 bytes long."; +#endif + +U_BOOT_CMD( + aes, 6, 1, do_aes, + "AES 128 CBC encryption", + aes_help_text +); diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index af884b8a6a..e6d8a7ae2c 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -88,11 +88,11 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("sramstart", bd->bi_sramstart); print_num("sramsize", bd->bi_sramsize); #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \ - defined(CONFIG_8260) || defined(CONFIG_E500) + defined(CONFIG_MPC8260) || defined(CONFIG_E500) print_num("immr_base", bd->bi_immr_base); #endif print_num("bootflags", bd->bi_bootflags); -#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || \ +#if defined(CONFIG_405EP) || \ defined(CONFIG_405GP) || \ defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ @@ -106,7 +106,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405) print_mhz("pci_busfreq", bd->bi_pci_busfreq); #endif -#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */ +#else /* ! CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */ #if defined(CONFIG_CPM2) print_mhz("vco", bd->bi_vco); print_mhz("sccfreq", bd->bi_sccfreq); @@ -117,7 +117,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_mhz("cpmfreq", bd->bi_cpmfreq); #endif print_mhz("busfreq", bd->bi_busfreq); -#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */ +#endif /* CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */ #ifdef CONFIG_ENABLE_36BIT_PHYS #ifdef CONFIG_PHYS_64BIT @@ -144,11 +144,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(5); #endif -#ifdef CONFIG_HERMES - print_mhz("ethspeed", bd->bi_ethspeed); -#endif printf("IP addr = %s\n", getenv("ipaddr")); - printf("baudrate = %6u bps\n", bd->bi_baudrate); + printf("baudrate = %6u bps\n", gd->baudrate); print_num("relocaddr", gd->relocaddr); board_detail(); return 0; @@ -176,7 +173,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -198,7 +195,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_CMD_NET) print_eths(); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -231,7 +228,7 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %6u bps\n", bd->bi_baudrate); + printf("baudrate = %6u bps\n", gd->baudrate); return 0; } @@ -277,7 +274,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -304,7 +301,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -324,7 +321,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -344,14 +341,15 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } #elif defined(CONFIG_ARM) -int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { int i; bd_t *bd = gd->bd; @@ -368,7 +366,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_CMD_NET) print_eths(); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) print_num("TLB addr", gd->arch.tlb_addr); #endif @@ -406,7 +404,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -440,7 +438,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); print_mhz("ethspeed", bd->bi_ethspeed); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -490,7 +488,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -512,7 +510,25 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); + + return 0; +} + +#elif defined(CONFIG_ARC) + +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + + print_num("mem start", bd->bi_memstart); + print_lnum("mem size", bd->bi_memsize); + +#if defined(CONFIG_CMD_NET) + print_eth(0); + printf("ip_addr = %s\n", getenv("ipaddr")); +#endif + printf("baudrate = %d bps\n", gd->baudrate); return 0; } diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c index 77b6e3e88e..57a8a3f2fe 100644 --- a/common/cmd_bedbug.c +++ b/common/cmd_bedbug.c @@ -3,6 +3,7 @@ */ #include +#include #include #include #include @@ -19,7 +20,7 @@ extern int run_command __P ((const char *, int)); ulong dis_last_addr = 0; /* Last address disassembled */ ulong dis_last_len = 20; /* Default disassembler length */ CPU_DEBUG_CTX bug_ctx; /* Bedbug context structure */ - + /* ====================================================================== * U-Boot's puts function does not append a newline, so the bedbug stuff @@ -33,7 +34,7 @@ int bedbug_puts (const char *str) printf ("%s\r\n", str); return 0; } /* bedbug_puts */ - + /* ====================================================================== @@ -65,7 +66,7 @@ void bedbug_init (void) return; } /* bedbug_init */ - + /* ====================================================================== @@ -106,7 +107,7 @@ int do_bedbug_dis (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (ds, 3, 1, do_bedbug_dis, "disassemble memory", "ds
[# instructions]"); - + /* ====================================================================== * Entry point from the interpreter to the assembler. Assembles * instructions in consecutive memory locations until a '.' (period) is @@ -134,7 +135,7 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) F_RADHEX); sprintf (prompt, "%08lx: ", mem_addr); - readline (prompt); + cli_readline(prompt); if (console_buffer[0] && strcmp (console_buffer, ".")) { if ((instr = @@ -156,7 +157,7 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (as, 2, 0, do_bedbug_asm, "assemble memory", "as
"); - + /* ====================================================================== * Used to set a break point from the interpreter. Simply calls into the * CPU-specific break point set routine. @@ -177,7 +178,7 @@ U_BOOT_CMD (break, 3, 0, do_bedbug_break, "break
- Break at an address\n" "break off - Disable breakpoint.\n" "break show - List breakpoints."); - + /* ====================================================================== * Called from the debug interrupt routine. Simply calls the CPU-specific * breakpoint handling routine. @@ -192,7 +193,7 @@ void do_bedbug_breakpoint (struct pt_regs *regs) return; } /* do_bedbug_breakpoint */ - + /* ====================================================================== @@ -225,7 +226,7 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) /* A miniature main loop */ while (bug_ctx.stopped) { - len = readline (prompt_str); + len = cli_readline(prompt_str); flag = 0; /* assume no special flags for now */ @@ -237,7 +238,7 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) if (len == -1) printf ("\n"); else - rc = run_command(lastcommand, flag); + rc = run_command_repeatable(lastcommand, flag); if (rc <= 0) { /* invalid command or not repeatable, forget it */ @@ -250,7 +251,7 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) return; } /* bedbug_main_loop */ - + /* ====================================================================== @@ -274,7 +275,7 @@ int do_bedbug_continue (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv U_BOOT_CMD (continue, 1, 0, do_bedbug_continue, "continue from a breakpoint", ""); - + /* ====================================================================== * Interpreter command to continue to the next instruction, stepping into * subroutines. Works by calling the find_next_addr() routine to compute @@ -305,7 +306,7 @@ int do_bedbug_step (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (step, 1, 1, do_bedbug_step, "single step execution.", ""); - + /* ====================================================================== * Interpreter command to continue to the next instruction, stepping over * subroutines. Works by calling the find_next_addr() routine to compute @@ -336,7 +337,7 @@ int do_bedbug_next (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (next, 1, 1, do_bedbug_next, "single step execution, stepping over subroutines.", ""); - + /* ====================================================================== * Interpreter command to print the current stack. This assumes an EABI * architecture, so it starts with GPR R1 and works back up the stack. @@ -381,7 +382,7 @@ int do_bedbug_stack (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (where, 1, 1, do_bedbug_stack, "Print the running stack.", ""); - + /* ====================================================================== * Interpreter command to dump the registers. Calls the CPU-specific * show registers routine. diff --git a/common/cmd_blob.c b/common/cmd_blob.c new file mode 100644 index 0000000000..82ecaf09e5 --- /dev/null +++ b/common/cmd_blob.c @@ -0,0 +1,109 @@ +/* + * + * Command for encapsulating/decapsulating blob of memory. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * blob_decap() - Decapsulate the data as a blob + * @key_mod: - Pointer to key modifier/key + * @src: - Address of data to be decapsulated + * @dst: - Address of data to be decapsulated + * @len: - Size of data to be decapsulated + * + * Returns zero on success,and negative on error. + */ +__weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) +{ + return 0; +} + +/** + * blob_encap() - Encapsulate the data as a blob + * @key_mod: - Pointer to key modifier/key + * @src: - Address of data to be encapsulated + * @dst: - Address of data to be encapsulated + * @len: - Size of data to be encapsulated + * + * Returns zero on success,and negative on error. + */ +__weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) +{ + return 0; +} + +/** + * do_blob() - Handle the "blob" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + uint32_t key_addr, src_addr, dst_addr, len; + uint8_t *km_ptr, *src_ptr, *dst_ptr; + int enc, ret = 0; + + if (argc != 6) + return CMD_RET_USAGE; + + if (!strncmp(argv[1], "enc", 3)) + enc = 1; + else if (!strncmp(argv[1], "dec", 3)) + enc = 0; + else + return CMD_RET_USAGE; + + src_addr = simple_strtoul(argv[2], NULL, 16); + dst_addr = simple_strtoul(argv[3], NULL, 16); + len = simple_strtoul(argv[4], NULL, 16); + key_addr = simple_strtoul(argv[5], NULL, 16); + + km_ptr = (uint8_t *)key_addr; + src_ptr = (uint8_t *)src_addr; + dst_ptr = (uint8_t *)dst_addr; + + if (enc) + ret = blob_encap(km_ptr, src_ptr, dst_ptr, len); + else + ret = blob_decap(km_ptr, src_ptr, dst_ptr, len); + + return ret; +} + +/***************************************************/ +static char blob_help_text[] = + "enc src dst len km - Encapsulate and create blob of data\n" + " $len bytes long at address $src and\n" + " store the result at address $dst.\n" + " $km is the 16 byte key modifier\n" + " is also required for generation/use as\n" + " key for cryptographic operation. Key\n" + " modifier should be 16 byte long.\n" + "blob dec src dst len km - Decapsulate the blob of data at address\n" + " $src and store result of $len byte at\n" + " addr $dst.\n" + " $km is the 16 byte key modifier\n" + " is also required for generation/use as\n" + " key for cryptographic operation. Key\n" + " modifier should be 16 byte long.\n"; + +U_BOOT_CMD( + blob, 6, 1, do_blob, + "Blob encapsulation/decryption", + blob_help_text +); diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index c093fefd4c..cc904c2535 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -121,9 +121,9 @@ static int do_bmp_display(cmd_tbl_t * cmdtp, int flag, int argc, char * const ar break; case 4: addr = simple_strtoul(argv[1], NULL, 16); - x = simple_strtoul(argv[2], NULL, 10); - y = simple_strtoul(argv[3], NULL, 10); - break; + x = simple_strtoul(argv[2], NULL, 10); + y = simple_strtoul(argv[3], NULL, 10); + break; default: return CMD_RET_USAGE; } diff --git a/common/cmd_bootce.c b/common/cmd_bootce.c index c30ed1feea..a95f163d47 100644 --- a/common/cmd_bootce.c +++ b/common/cmd_bootce.c @@ -913,8 +913,6 @@ static inline int ce_init_download_link(ce_net *net, ce_bin *bin, int verbose) return 0; } -#define UINT_MAX ~0UL - static inline int ce_download_file(ce_net *net, ulong timeout) { ulong start = get_timer_masked(); @@ -981,7 +979,7 @@ static int do_ceconnect(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[] timeout = simple_strtoul(argv[i], NULL, 0); if (timeout >= UINT_MAX / CONFIG_SYS_HZ) { - printf("Timeout value %lu out of range (max.: %lu)\n", + printf("Timeout value %lu out of range (max.: %u)\n", timeout, UINT_MAX / CONFIG_SYS_HZ - 1); return CMD_RET_USAGE; } diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 046e22ff48..48199bfff3 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -5,57 +5,26 @@ * SPDX-License-Identifier: GPL-2.0+ */ - /* * Boot support */ #include -#include +#include #include -#include -#include -#include -#include #include +#include +#include #include -#include +#include +#include #include -#include #include - -#if defined(CONFIG_CMD_USB) -#include -#endif - -#ifdef CONFIG_SYS_HUSH_PARSER -#include -#endif - -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#endif - -#ifdef CONFIG_LZMA -#include -#include -#include -#endif /* CONFIG_LZMA */ - -#ifdef CONFIG_LZO -#include -#endif /* CONFIG_LZO */ +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_BOOTM_LEN -#define CONFIG_SYS_BOOTM_LEN 0x800000 /* use 8MByte as default max gunzip size */ -#endif - -#ifdef CONFIG_BZIP2 -extern void bz_internal_error(int); -#endif - #if defined(CONFIG_CMD_IMI) static int image_info(unsigned long addr); #endif @@ -70,436 +39,8 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */ static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif -#include -#include - -#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) -static void fixup_silent_linux(void); -#endif - -static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[], bootm_headers_t *images, - ulong *os_data, ulong *os_len); - -/* - * Continue booting an OS image; caller already has: - * - copied image header to global variable `header' - * - checked header magic number, checksums (both header & image), - * - verified image architecture (PPC) and type (KERNEL or MULTI), - * - loaded (first part of) image to header load address, - * - disabled interrupts. - * - * @flag: Flags indicating what to do (BOOTM_STATE_...) - * @argc: Number of arguments. Note that the arguments are shifted down - * so that 0 is the first argument not processed by U-Boot, and - * argc is adjusted accordingly. This avoids confusion as to how - * many arguments are available for the OS. - * @images: Pointers to os/initrd/fdt - * @return 1 on error. On success the OS boots so this function does - * not return. - */ -typedef int boot_os_fn(int flag, int argc, char * const argv[], - bootm_headers_t *images); - -#ifdef CONFIG_BOOTM_LINUX -extern boot_os_fn do_bootm_linux; -#endif -#ifdef CONFIG_BOOTM_NETBSD -static boot_os_fn do_bootm_netbsd; -#endif -#if defined(CONFIG_LYNXKDI) -static boot_os_fn do_bootm_lynxkdi; -extern void lynxkdi_boot(image_header_t *); -#endif -#ifdef CONFIG_BOOTM_RTEMS -static boot_os_fn do_bootm_rtems; -#endif -#if defined(CONFIG_BOOTM_OSE) -static boot_os_fn do_bootm_ose; -#endif -#if defined(CONFIG_BOOTM_PLAN9) -static boot_os_fn do_bootm_plan9; -#endif -#if defined(CONFIG_CMD_ELF) -static boot_os_fn do_bootm_vxworks; -static boot_os_fn do_bootm_qnxelf; -int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -#endif -#if defined(CONFIG_INTEGRITY) -static boot_os_fn do_bootm_integrity; -#endif - -static boot_os_fn *boot_os[] = { -#ifdef CONFIG_BOOTM_LINUX - [IH_OS_LINUX] = do_bootm_linux, -#endif -#ifdef CONFIG_BOOTM_NETBSD - [IH_OS_NETBSD] = do_bootm_netbsd, -#endif -#ifdef CONFIG_LYNXKDI - [IH_OS_LYNXOS] = do_bootm_lynxkdi, -#endif -#ifdef CONFIG_BOOTM_RTEMS - [IH_OS_RTEMS] = do_bootm_rtems, -#endif -#if defined(CONFIG_BOOTM_OSE) - [IH_OS_OSE] = do_bootm_ose, -#endif -#if defined(CONFIG_BOOTM_PLAN9) - [IH_OS_PLAN9] = do_bootm_plan9, -#endif -#if defined(CONFIG_CMD_ELF) - [IH_OS_VXWORKS] = do_bootm_vxworks, - [IH_OS_QNX] = do_bootm_qnxelf, -#endif -#ifdef CONFIG_INTEGRITY - [IH_OS_INTEGRITY] = do_bootm_integrity, -#endif -}; - bootm_headers_t images; /* pointers to os/initrd/fdt images */ -/* Allow for arch specific config before we boot */ -static void __arch_preboot_os(void) -{ - /* please define platform specific arch_preboot_os() */ -} -void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os"))); - -#define IH_INITRD_ARCH IH_ARCH_DEFAULT - -#ifdef CONFIG_LMB -static void boot_start_lmb(bootm_headers_t *images) -{ - ulong mem_start; - phys_size_t mem_size; - - lmb_init(&images->lmb); - - mem_start = getenv_bootm_low(); - mem_size = getenv_bootm_size(); - - lmb_add(&images->lmb, (phys_addr_t)mem_start, mem_size); - - arch_lmb_reserve(&images->lmb); - board_lmb_reserve(&images->lmb); -} -#else -#define lmb_reserve(lmb, base, size) -static inline void boot_start_lmb(bootm_headers_t *images) { } -#endif - -static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - memset((void *)&images, 0, sizeof(images)); - images.verify = getenv_yesno("verify"); - - boot_start_lmb(&images); - - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_START, "bootm_start"); - images.state = BOOTM_STATE_START; - - return 0; -} - -static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - const void *os_hdr; - - /* get kernel image header, start address and length */ - os_hdr = boot_get_kernel(cmdtp, flag, argc, argv, - &images, &images.os.image_start, &images.os.image_len); - if (images.os.image_len == 0) { - puts("ERROR: can't get kernel image!\n"); - return 1; - } - - /* get image parameters */ - switch (genimg_get_format(os_hdr)) { - case IMAGE_FORMAT_LEGACY: - images.os.type = image_get_type(os_hdr); - images.os.comp = image_get_comp(os_hdr); - images.os.os = image_get_os(os_hdr); - - images.os.end = image_get_image_end(os_hdr); - images.os.load = image_get_load(os_hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - if (fit_image_get_type(images.fit_hdr_os, - images.fit_noffset_os, &images.os.type)) { - puts("Can't get image type!\n"); - bootstage_error(BOOTSTAGE_ID_FIT_TYPE); - return 1; - } - - if (fit_image_get_comp(images.fit_hdr_os, - images.fit_noffset_os, &images.os.comp)) { - puts("Can't get image compression!\n"); - bootstage_error(BOOTSTAGE_ID_FIT_COMPRESSION); - return 1; - } - - if (fit_image_get_os(images.fit_hdr_os, - images.fit_noffset_os, &images.os.os)) { - puts("Can't get image OS!\n"); - bootstage_error(BOOTSTAGE_ID_FIT_OS); - return 1; - } - - images.os.end = fit_get_end(images.fit_hdr_os); - - if (fit_image_get_load(images.fit_hdr_os, images.fit_noffset_os, - &images.os.load)) { - puts("Can't get image load address!\n"); - bootstage_error(BOOTSTAGE_ID_FIT_LOADADDR); - return 1; - } - break; -#endif - default: - puts("ERROR: unknown image format type!\n"); - return 1; - } - - /* find kernel entry point */ - if (images.legacy_hdr_valid) { - images.ep = image_get_ep(&images.legacy_hdr_os_copy); -#if defined(CONFIG_FIT) - } else if (images.fit_uname_os) { - int ret; - - ret = fit_image_get_entry(images.fit_hdr_os, - images.fit_noffset_os, &images.ep); - if (ret) { - puts("Can't get entry point property!\n"); - return 1; - } -#endif - } else { - puts("Could not find kernel entry point!\n"); - return 1; - } - - if (images.os.type == IH_TYPE_KERNEL_NOLOAD) { - images.os.load = images.os.image_start; - images.ep += images.os.load; - } - - images.os.start = (ulong)os_hdr; - - return 0; -} - -static int bootm_find_ramdisk(int flag, int argc, char * const argv[]) -{ - int ret; - - /* find ramdisk */ - ret = boot_get_ramdisk(argc, argv, &images, IH_INITRD_ARCH, - &images.rd_start, &images.rd_end); - if (ret) { - puts("Ramdisk image is corrupt or invalid\n"); - return 1; - } - - return 0; -} - -#if defined(CONFIG_OF_LIBFDT) -static int bootm_find_fdt(int flag, int argc, char * const argv[]) -{ - int ret; - - /* find flattened device tree */ - ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images, - &images.ft_addr, &images.ft_len); - if (ret) { - puts("Could not find a valid device tree\n"); - return 1; - } - - set_working_fdt_addr(images.ft_addr); - - return 0; -} -#endif - -static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - if (((images.os.type == IH_TYPE_KERNEL) || - (images.os.type == IH_TYPE_KERNEL_NOLOAD) || - (images.os.type == IH_TYPE_MULTI)) && - (images.os.os == IH_OS_LINUX)) { - if (bootm_find_ramdisk(flag, argc, argv)) - return 1; - -#if defined(CONFIG_OF_LIBFDT) - if (bootm_find_fdt(flag, argc, argv)) - return 1; -#endif - } - - return 0; -} - -#define BOOTM_ERR_RESET -1 -#define BOOTM_ERR_OVERLAP -2 -#define BOOTM_ERR_UNIMPLEMENTED -3 -static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, - int boot_progress) -{ - image_info_t os = images->os; - uint8_t comp = os.comp; - ulong load = os.load; - ulong blob_start = os.start; - ulong blob_end = os.end; - ulong image_start = os.image_start; - ulong image_len = os.image_len; - __maybe_unused uint unc_len = CONFIG_SYS_BOOTM_LEN; - int no_overlap = 0; - void *load_buf, *image_buf; -#if defined(CONFIG_LZMA) || defined(CONFIG_LZO) - int ret; -#endif /* defined(CONFIG_LZMA) || defined(CONFIG_LZO) */ - - const char *type_name = genimg_get_type_name(os.type); - - load_buf = map_sysmem(load, image_len); - image_buf = map_sysmem(image_start, image_len); - switch (comp) { - case IH_COMP_NONE: - if (load == blob_start || load == image_start) { - printf(" XIP %s ... ", type_name); - no_overlap = 1; - } else { - printf(" Loading %s ... ", type_name); - memmove_wd(load_buf, image_buf, image_len, CHUNKSZ); - } - *load_end = load + image_len; - break; -#ifdef CONFIG_GZIP - case IH_COMP_GZIP: - printf(" Uncompressing %s ... ", type_name); - if (gunzip(load_buf, unc_len, image_buf, &image_len) != 0) { - puts("GUNZIP: uncompress, out-of-mem or overwrite " - "error - must RESET board to recover\n"); - if (boot_progress) - bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); - return BOOTM_ERR_RESET; - } - - *load_end = load + image_len; - break; -#endif /* CONFIG_GZIP */ -#ifdef CONFIG_BZIP2 - case IH_COMP_BZIP2: - printf(" Uncompressing %s ... ", type_name); - /* - * If we've got less than 4 MB of malloc() space, - * use slower decompression algorithm which requires - * at most 2300 KB of memory. - */ - int i = BZ2_bzBuffToBuffDecompress(load_buf, &unc_len, - image_buf, image_len, - CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); - if (i != BZ_OK) { - printf("BUNZIP2: uncompress or overwrite error %d " - "- must RESET board to recover\n", i); - if (boot_progress) - bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); - return BOOTM_ERR_RESET; - } - - *load_end = load + unc_len; - break; -#endif /* CONFIG_BZIP2 */ -#ifdef CONFIG_LZMA - case IH_COMP_LZMA: { - SizeT lzma_len = unc_len; - printf(" Uncompressing %s ... ", type_name); - - ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len, - image_buf, image_len); - unc_len = lzma_len; - if (ret != SZ_OK) { - printf("LZMA: uncompress or overwrite error %d " - "- must RESET board to recover\n", ret); - bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); - return BOOTM_ERR_RESET; - } - *load_end = load + unc_len; - break; - } -#endif /* CONFIG_LZMA */ -#ifdef CONFIG_LZO - case IH_COMP_LZO: - printf(" Uncompressing %s ... ", type_name); - - ret = lzop_decompress(image_buf, image_len, load_buf, - &unc_len); - if (ret != LZO_E_OK) { - printf("LZO: uncompress or overwrite error %d " - "- must RESET board to recover\n", ret); - if (boot_progress) - bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); - return BOOTM_ERR_RESET; - } - - *load_end = load + unc_len; - break; -#endif /* CONFIG_LZO */ - default: - printf("Unimplemented compression type %d\n", comp); - return BOOTM_ERR_UNIMPLEMENTED; - } - - flush_cache(load, (*load_end - load) * sizeof(ulong)); - - puts("OK\n"); - debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end); - bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED); - - if (!no_overlap && (load < blob_end) && (*load_end > blob_start)) { - debug("images.os.start = 0x%lX, images.os.end = 0x%lx\n", - blob_start, blob_end); - debug("images.os.load = 0x%lx, load_end = 0x%lx\n", load, - *load_end); - - /* Check what type of image this is. */ - if (images->legacy_hdr_valid) { - if (image_get_type(&images->legacy_hdr_os_copy) - == IH_TYPE_MULTI) - puts("WARNING: legacy format multi component image overwritten\n"); - return BOOTM_ERR_OVERLAP; - } else { - puts("ERROR: new format image overwritten - must RESET the board to recover\n"); - bootstage_error(BOOTSTAGE_ID_OVERWRITTEN); - return BOOTM_ERR_RESET; - } - } - - return 0; -} - -static int bootm_start_standalone(int argc, char * const argv[]) -{ - char *s; - int (*appl)(int, char * const []); - - /* Don't start if "autostart" is set to "no" */ - if (((s = getenv("autostart")) != NULL) && (strcmp(s, "no") == 0)) { - setenv_hex("filesize", images.os.image_len); - return 0; - } - appl = (int (*)(int, char * const []))(ulong)ntohl(images.ep); - (*appl)(argc, argv); - return 0; -} - /* we overload the cmd field with our state machine info instead of a * function pointer */ static cmd_tbl_t cmd_bootm_sub[] = { @@ -518,211 +59,6 @@ static cmd_tbl_t cmd_bootm_sub[] = { U_BOOT_CMD_MKENT(go, 0, 1, (void *)BOOTM_STATE_OS_GO, "", ""), }; -static int boot_selected_os(int argc, char * const argv[], int state, - bootm_headers_t *images, boot_os_fn *boot_fn) -{ - if (images->os.type == IH_TYPE_STANDALONE) { - /* This may return when 'autostart' is 'no' */ - bootm_start_standalone(argc, argv); - return 0; - } - arch_preboot_os(); - boot_fn(state, argc, argv, images); - if (state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */ - return 0; - bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED); -#ifdef DEBUG - puts("\n## Control returned to monitor - resetting...\n"); -#endif - return BOOTM_ERR_RESET; -} - -/** - * bootm_disable_interrupts() - Disable interrupts in preparation for load/boot - * - * @return interrupt flag (0 if interrupts were disabled, non-zero if they were - * enabled) - */ -static ulong bootm_disable_interrupts(void) -{ - ulong iflag; - - /* - * We have reached the point of no return: we are going to - * overwrite all exception vector code, so we cannot easily - * recover from any failures any more... - */ - iflag = disable_interrupts(); -#ifdef CONFIG_NETCONSOLE - /* Stop the ethernet stack if NetConsole could have left it up */ - eth_halt(); -#endif - -#if defined(CONFIG_CMD_USB) - /* - * turn off USB to prevent the host controller from writing to the - * SDRAM while Linux is booting. This could happen (at least for OHCI - * controller), because the HCCA (Host Controller Communication Area) - * lies within the SDRAM and the host controller writes continously to - * this area (as busmaster!). The HccaFrameNumber is for example - * updated every 1 ms within the HCCA structure in SDRAM! For more - * details see the OpenHCI specification. - */ - usb_stop(); -#endif - return iflag; -} - -/** - * Execute selected states of the bootm command. - * - * Note the arguments to this state must be the first argument, Any 'bootm' - * or sub-command arguments must have already been taken. - * - * Note that if states contains more than one flag it MUST contain - * BOOTM_STATE_START, since this handles and consumes the command line args. - * - * Also note that aside from boot_os_fn functions and bootm_load_os no other - * functions we store the return value of in 'ret' may use a negative return - * value, without special handling. - * - * @param cmdtp Pointer to bootm command table entry - * @param flag Command flags (CMD_FLAG_...) - * @param argc Number of subcommand arguments (0 = no arguments) - * @param argv Arguments - * @param states Mask containing states to run (BOOTM_STATE_...) - * @param images Image header information - * @param boot_progress 1 to show boot progress, 0 to not do this - * @return 0 if ok, something else on error. Some errors will cause this - * function to perform a reboot! If states contains BOOTM_STATE_OS_GO - * then the intent is to boot an OS, so this function will not return - * unless the image type is standalone. - */ -static int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[], int states, bootm_headers_t *images, - int boot_progress) -{ - boot_os_fn *boot_fn; - ulong iflag = 0; - int ret = 0, need_boot_fn; - - images->state |= states; - - /* - * Work through the states and see how far we get. We stop on - * any error. - */ - if (states & BOOTM_STATE_START) - ret = bootm_start(cmdtp, flag, argc, argv); - - if (!ret && (states & BOOTM_STATE_FINDOS)) - ret = bootm_find_os(cmdtp, flag, argc, argv); - - if (!ret && (states & BOOTM_STATE_FINDOTHER)) { - ret = bootm_find_other(cmdtp, flag, argc, argv); - argc = 0; /* consume the args */ - } - - /* Load the OS */ - if (!ret && (states & BOOTM_STATE_LOADOS)) { - ulong load_end; - - iflag = bootm_disable_interrupts(); - ret = bootm_load_os(images, &load_end, 0); - if (ret == 0) - lmb_reserve(&images->lmb, images->os.load, - (load_end - images->os.load)); - else if (ret && ret != BOOTM_ERR_OVERLAP) - goto err; - else if (ret == BOOTM_ERR_OVERLAP) - ret = 0; -#ifdef CONFIG_SILENT_CONSOLE - if (images->os.os == IH_OS_LINUX) - fixup_silent_linux(); -#endif - } - - /* Relocate the ramdisk */ -#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH - if (!ret && (states & BOOTM_STATE_RAMDISK)) { - ulong rd_len = images->rd_end - images->rd_start; - - ret = boot_ramdisk_high(&images->lmb, images->rd_start, - rd_len, &images->initrd_start, &images->initrd_end); - if (!ret) { - setenv_hex("initrd_start", images->initrd_start); - setenv_hex("initrd_end", images->initrd_end); - } - } -#endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB) - if (!ret && (states & BOOTM_STATE_FDT)) { - boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); - ret = boot_relocate_fdt(&images->lmb, &images->ft_addr, - &images->ft_len); - } -#endif - - /* From now on, we need the OS boot function */ - if (ret) - return ret; - boot_fn = boot_os[images->os.os]; - need_boot_fn = states & (BOOTM_STATE_OS_CMDLINE | - BOOTM_STATE_OS_BD_T | BOOTM_STATE_OS_PREP | - BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO); - if (boot_fn == NULL && need_boot_fn) { - if (iflag) - enable_interrupts(); - printf("ERROR: booting os '%s' (%d) is not supported\n", - genimg_get_os_name(images->os.os), images->os.os); - bootstage_error(BOOTSTAGE_ID_CHECK_BOOT_OS); - return 1; - } - - /* Call various other states that are not generally used */ - if (!ret && (states & BOOTM_STATE_OS_CMDLINE)) - ret = boot_fn(BOOTM_STATE_OS_CMDLINE, argc, argv, images); - if (!ret && (states & BOOTM_STATE_OS_BD_T)) - ret = boot_fn(BOOTM_STATE_OS_BD_T, argc, argv, images); - if (!ret && (states & BOOTM_STATE_OS_PREP)) - ret = boot_fn(BOOTM_STATE_OS_PREP, argc, argv, images); - -#ifdef CONFIG_TRACE - /* Pretend to run the OS, then run a user command */ - if (!ret && (states & BOOTM_STATE_OS_FAKE_GO)) { - char *cmd_list = getenv("fakegocmd"); - - ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_FAKE_GO, - images, boot_fn); - if (!ret && cmd_list) - ret = run_command_list(cmd_list, -1, flag); - } -#endif - - /* Check for unsupported subcommand. */ - if (ret) { - puts("subcommand not supported\n"); - return ret; - } - - /* Now run the OS! We hope this doesn't return */ - if (!ret && (states & BOOTM_STATE_OS_GO)) - ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_GO, - images, boot_fn); - - /* Deal with any fallout */ -err: - if (iflag) - enable_interrupts(); - - if (ret == BOOTM_ERR_UNIMPLEMENTED) - bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL); - else if (ret == BOOTM_ERR_RESET) - do_reset(cmdtp, flag, argc, argv); - - return ret; -} - static int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -764,11 +100,6 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (!relocated) { int i; - /* relocate boot function table */ - for (i = 0; i < ARRAY_SIZE(boot_os); i++) - if (boot_os[i] != NULL) - boot_os[i] += gd->reloc_off; - /* relocate names of sub-command table */ for (i = 0; i < ARRAY_SIZE(cmd_bootm_sub); i++) cmd_bootm_sub[i].name += gd->reloc_off; @@ -789,207 +120,35 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * If endp is ':' or '#' assume a FIT identifier so pass * along for normal processing. * - * Right now we assume the first arg should never be '-' - */ - if ((*endp != 0) && (*endp != ':') && (*endp != '#')) - return do_bootm_subcommand(cmdtp, flag, argc, argv); - } - - return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START | - BOOTM_STATE_FINDOS | BOOTM_STATE_FINDOTHER | - BOOTM_STATE_LOADOS | BOOTM_STATE_OS_PREP | - BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO, &images, 1); -} - -int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd) -{ - const char *ep = getenv("autostart"); - - if (ep && !strcmp(ep, "yes")) { - char *local_args[2]; - local_args[0] = (char *)cmd; - local_args[1] = NULL; - printf("Automatic boot of image at addr 0x%08lX ...\n", load_addr); - return do_bootm(cmdtp, 0, 1, local_args); - } - - return 0; -} - -/** - * image_get_kernel - verify legacy format kernel image - * @img_addr: in RAM address of the legacy format image to be verified - * @verify: data CRC verification flag - * - * image_get_kernel() verifies legacy image integrity and returns pointer to - * legacy image header if image verification was completed successfully. - * - * returns: - * pointer to a legacy image header if valid image was found - * otherwise return NULL - */ -static image_header_t *image_get_kernel(ulong img_addr, int verify) -{ - image_header_t *hdr = (image_header_t *)img_addr; - - if (!image_check_magic(hdr)) { - puts("Bad Magic Number\n"); - bootstage_error(BOOTSTAGE_ID_CHECK_MAGIC); - return NULL; - } - bootstage_mark(BOOTSTAGE_ID_CHECK_HEADER); - - if (!image_check_hcrc(hdr)) { - puts("Bad Header Checksum\n"); - bootstage_error(BOOTSTAGE_ID_CHECK_HEADER); - return NULL; - } - - bootstage_mark(BOOTSTAGE_ID_CHECK_CHECKSUM); - image_print_contents(hdr); - - if (verify) { - puts(" Verifying Checksum ... "); - if (!image_check_dcrc(hdr)) { - printf("Bad Data CRC\n"); - bootstage_error(BOOTSTAGE_ID_CHECK_CHECKSUM); - return NULL; - } - puts("OK\n"); - } - bootstage_mark(BOOTSTAGE_ID_CHECK_ARCH); - - if (!image_check_target_arch(hdr)) { - printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr)); - bootstage_error(BOOTSTAGE_ID_CHECK_ARCH); - return NULL; - } - return hdr; -} - -/** - * boot_get_kernel - find kernel image - * @os_data: pointer to a ulong variable, will hold os data start address - * @os_len: pointer to a ulong variable, will hold os data length - * - * boot_get_kernel() tries to find a kernel image, verifies its integrity - * and locates kernel data. - * - * returns: - * pointer to image header if valid image was found, plus kernel start - * address and length, otherwise NULL - */ -static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[], bootm_headers_t *images, ulong *os_data, - ulong *os_len) -{ - image_header_t *hdr; - ulong img_addr; - const void *buf; -#if defined(CONFIG_FIT) - const char *fit_uname_config = NULL; - const char *fit_uname_kernel = NULL; - int os_noffset; -#endif - - /* find out kernel image address */ - if (argc < 1) { - img_addr = load_addr; - debug("* kernel: default image load address = 0x%08lx\n", - load_addr); -#if defined(CONFIG_FIT) - } else if (fit_parse_conf(argv[0], load_addr, &img_addr, - &fit_uname_config)) { - debug("* kernel: config '%s' from image at 0x%08lx\n", - fit_uname_config, img_addr); - } else if (fit_parse_subimage(argv[0], load_addr, &img_addr, - &fit_uname_kernel)) { - debug("* kernel: subimage '%s' from image at 0x%08lx\n", - fit_uname_kernel, img_addr); -#endif - } else { - img_addr = simple_strtoul(argv[0], NULL, 16); - debug("* kernel: cmdline image address = 0x%08lx\n", img_addr); - } - - bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC); - - /* copy from dataflash if needed */ - img_addr = genimg_get_image(img_addr); - - /* check image type, for FIT images get FIT kernel node */ - *os_data = *os_len = 0; - buf = map_sysmem(img_addr, 0); - switch (genimg_get_format(buf)) { - case IMAGE_FORMAT_LEGACY: - printf("## Booting kernel from Legacy Image at %08lx ...\n", - img_addr); - hdr = image_get_kernel(img_addr, images->verify); - if (!hdr) - return NULL; - bootstage_mark(BOOTSTAGE_ID_CHECK_IMAGETYPE); - - /* get os_data and os_len */ - switch (image_get_type(hdr)) { - case IH_TYPE_KERNEL: - case IH_TYPE_KERNEL_NOLOAD: - *os_data = image_get_data(hdr); - *os_len = image_get_data_size(hdr); - break; - case IH_TYPE_MULTI: - image_multi_getimg(hdr, 0, os_data, os_len); - break; - case IH_TYPE_STANDALONE: - *os_data = image_get_data(hdr); - *os_len = image_get_data_size(hdr); - break; - default: - printf("Wrong Image Type for %s command\n", - cmdtp->name); - bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE); - return NULL; - } - - /* - * copy image header to allow for image overwrites during - * kernel decompression. + * Right now we assume the first arg should never be '-' */ - memmove(&images->legacy_hdr_os_copy, hdr, - sizeof(image_header_t)); - - /* save pointer to image header */ - images->legacy_hdr_os = hdr; + if ((*endp != 0) && (*endp != ':') && (*endp != '#')) + return do_bootm_subcommand(cmdtp, flag, argc, argv); + } - images->legacy_hdr_valid = 1; - bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - os_noffset = fit_image_load(images, FIT_KERNEL_PROP, - img_addr, - &fit_uname_kernel, &fit_uname_config, - IH_ARCH_DEFAULT, IH_TYPE_KERNEL, - BOOTSTAGE_ID_FIT_KERNEL_START, - FIT_LOAD_IGNORED, os_data, os_len); - if (os_noffset < 0) - return NULL; - - images->fit_hdr_os = map_sysmem(img_addr, 0); - images->fit_uname_os = fit_uname_kernel; - images->fit_uname_cfg = fit_uname_config; - images->fit_noffset_os = os_noffset; - break; + return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START | + BOOTM_STATE_FINDOS | BOOTM_STATE_FINDOTHER | + BOOTM_STATE_LOADOS | +#if defined(CONFIG_PPC) || defined(CONFIG_MIPS) + BOOTM_STATE_OS_CMDLINE | #endif - default: - printf("Wrong Image Format for %s command\n", cmdtp->name); - bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO); - return NULL; - } + BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO | + BOOTM_STATE_OS_GO, &images, 1); +} + +int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd) +{ + const char *ep = getenv("autostart"); - debug(" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n", - *os_data, *os_len, *os_len); + if (ep && !strcmp(ep, "yes")) { + char *local_args[2]; + local_args[0] = (char *)cmd; + local_args[1] = NULL; + printf("Automatic boot of image at addr 0x%08lX ...\n", load_addr); + return do_bootm(cmdtp, 0, 1, local_args); + } - return buf; + return 0; } #ifdef CONFIG_SYS_LONGHELP @@ -1026,6 +185,9 @@ static char bootm_help_text[] = "\tcmdline - OS specific command line processing/setup\n" "\tbdt - OS specific bd_t processing\n" "\tprep - OS specific prep before relocation or go\n" +#if defined(CONFIG_TRACE) + "\tfake - OS specific fake start without go\n" +#endif "\tgo - start OS"; #endif @@ -1040,11 +202,7 @@ U_BOOT_CMD( #if defined(CONFIG_CMD_BOOTD) int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int rcode = 0; - - if (run_command(getenv("bootcmd"), flag) < 0) - rcode = 1; - return rcode; + return run_command(getenv("bootcmd"), flag); } U_BOOT_CMD( @@ -1092,6 +250,7 @@ static int image_info(ulong addr) printf("\n## Checking Image at %08lx ...\n", addr); switch (genimg_get_format(hdr)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: puts(" Legacy image found\n"); if (!image_check_magic(hdr)) { @@ -1113,6 +272,7 @@ static int image_info(ulong addr) } puts("OK\n"); return 0; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: puts(" FIT image found\n"); @@ -1172,6 +332,7 @@ static int do_imls_nor(void) goto next_sector; switch (genimg_get_format(hdr)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: if (!image_check_hcrc(hdr)) goto next_sector; @@ -1186,6 +347,7 @@ static int do_imls_nor(void) puts("OK\n"); } break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: if (!fit_check_format(hdr)) @@ -1320,12 +482,14 @@ static int do_imls_nand(void) } switch (genimg_get_format(buffer)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: header = (const image_header_t *)buffer; len = image_get_image_size(header); nand_imls_legacyimage(nand, nand_dev, off, len); break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: len = fit_get_size(buffer); @@ -1371,416 +535,168 @@ U_BOOT_CMD( ); #endif -/*******************************************************************/ -/* helper routines */ -/*******************************************************************/ -#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) - -#define CONSOLE_ARG "console=" -#define CONSOLE_ARG_LEN (sizeof(CONSOLE_ARG) - 1) - -static void fixup_silent_linux(void) -{ - char *buf; - const char *env_val; - char *cmdline = getenv("bootargs"); - - /* Only fix cmdline when requested */ - if (!(gd->flags & GD_FLG_SILENT)) - return; - - debug("before silent fix-up: %s\n", cmdline); - if (cmdline && (cmdline[0] != '\0')) { - char *start = strstr(cmdline, CONSOLE_ARG); - - /* Allocate space for maximum possible new command line */ - buf = malloc(strlen(cmdline) + 1 + CONSOLE_ARG_LEN + 1); - if (!buf) { - debug("%s: out of memory\n", __func__); - return; - } - - if (start) { - char *end = strchr(start, ' '); - int num_start_bytes = start - cmdline + CONSOLE_ARG_LEN; - - strncpy(buf, cmdline, num_start_bytes); - if (end) - strcpy(buf + num_start_bytes, end); - else - buf[num_start_bytes] = '\0'; - } else { - sprintf(buf, "%s %s", cmdline, CONSOLE_ARG); - } - env_val = buf; - } else { - buf = NULL; - env_val = CONSOLE_ARG; - } - - setenv("bootargs", env_val); - debug("after silent fix-up: %s\n", env_val); - free(buf); -} -#endif /* CONFIG_SILENT_CONSOLE */ +#ifdef CONFIG_CMD_BOOTZ -#if defined(CONFIG_BOOTM_NETBSD) || defined(CONFIG_BOOTM_PLAN9) -static void copy_args(char *dest, int argc, char * const argv[], char delim) +int __weak bootz_setup(ulong image, ulong *start, ulong *end) { - int i; + /* Please define bootz_setup() for your platform */ - for (i = 0; i < argc; i++) { - if (i > 0) - *dest++ = delim; - strcpy(dest, argv[i]); - dest += strlen(argv[i]); - } + puts("Your platform's zImage format isn't supported yet!\n"); + return -1; } -#endif - -/*******************************************************************/ -/* OS booting routines */ -/*******************************************************************/ -#ifdef CONFIG_BOOTM_NETBSD -static int do_bootm_netbsd(int flag, int argc, char * const argv[], - bootm_headers_t *images) +/* + * zImage booting support + */ +static int bootz_start(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[], bootm_headers_t *images) { - void (*loader)(bd_t *, image_header_t *, char *, char *); - image_header_t *os_hdr, *hdr; - ulong kernel_data, kernel_len; - char *consdev; - char *cmdline; - - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("NetBSD"); - return 1; - } -#endif - hdr = images->legacy_hdr_os; - - /* - * Booting a (NetBSD) kernel image - * - * This process is pretty similar to a standalone application: - * The (first part of an multi-) image must be a stage-2 loader, - * which in turn is responsible for loading & invoking the actual - * kernel. The only differences are the parameters being passed: - * besides the board info strucure, the loader expects a command - * line, the name of the console device, and (optionally) the - * address of the original image header. - */ - os_hdr = NULL; - if (image_check_type(&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) { - image_multi_getimg(hdr, 1, &kernel_data, &kernel_len); - if (kernel_len) - os_hdr = hdr; - } + int ret; + ulong zi_start, zi_end; - consdev = ""; -#if defined(CONFIG_8xx_CONS_SMC1) - consdev = "smc1"; -#elif defined(CONFIG_8xx_CONS_SMC2) - consdev = "smc2"; -#elif defined(CONFIG_8xx_CONS_SCC2) - consdev = "scc2"; -#elif defined(CONFIG_8xx_CONS_SCC3) - consdev = "scc3"; -#endif + ret = do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START, + images, 1); - if (argc > 0) { - ulong len; - int i; - - for (i = 0, len = 0; i < argc; i += 1) - len += strlen(argv[i]) + 1; - cmdline = malloc(len); - copy_args(cmdline, argc, argv, ' '); - } else if ((cmdline = getenv("bootargs")) == NULL) { - cmdline = ""; + /* Setup Linux kernel zImage entry point */ + if (!argc) { + images->ep = load_addr; + debug("* kernel: default image load address = 0x%08lx\n", + load_addr); + } else { + images->ep = simple_strtoul(argv[0], NULL, 16); + debug("* kernel: cmdline image address = 0x%08lx\n", + images->ep); } - loader = (void (*)(bd_t *, image_header_t *, char *, char *))images->ep; - - printf("## Transferring control to NetBSD stage-2 loader " - "(at address %08lx) ...\n", - (ulong)loader); + ret = bootz_setup(images->ep, &zi_start, &zi_end); + if (ret != 0) + return 1; - bootstage_mark(BOOTSTAGE_ID_RUN_OS); + lmb_reserve(&images->lmb, images->ep, zi_end - zi_start); /* - * NetBSD Stage-2 Loader Parameters: - * r3: ptr to board info data - * r4: image address - * r5: console device - * r6: boot args string + * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not + * have a header that provide this informaiton. */ - (*loader)(gd->bd, os_hdr, consdev, cmdline); - - return 1; -} -#endif /* CONFIG_BOOTM_NETBSD*/ - -#ifdef CONFIG_LYNXKDI -static int do_bootm_lynxkdi(int flag, int argc, char * const argv[], - bootm_headers_t *images) -{ - image_header_t *hdr = &images->legacy_hdr_os_copy; - - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) + if (bootm_find_ramdisk_fdt(flag, argc, argv)) return 1; -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("Lynx"); - return 1; - } -#endif - - lynxkdi_boot((image_header_t *)hdr); - - return 1; + return 0; } -#endif /* CONFIG_LYNXKDI */ -#ifdef CONFIG_BOOTM_RTEMS -static int do_bootm_rtems(int flag, int argc, char * const argv[], - bootm_headers_t *images) +int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - void (*entry_point)(bd_t *); + int ret; - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; + /* Consume 'bootz' */ + argc--; argv++; -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("RTEMS"); + if (bootz_start(cmdtp, flag, argc, argv, &images)) return 1; - } -#endif - - entry_point = (void (*)(bd_t *))images->ep; - - printf("## Transferring control to RTEMS (at address %08lx) ...\n", - (ulong)entry_point); - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); /* - * RTEMS Parameters: - * r3: ptr to board info data + * We are doing the BOOTM_STATE_LOADOS state ourselves, so must + * disable interrupts ourselves */ - (*entry_point)(gd->bd); - - return 1; -} -#endif /* CONFIG_BOOTM_RTEMS */ - -#if defined(CONFIG_BOOTM_OSE) -static int do_bootm_ose(int flag, int argc, char * const argv[], - bootm_headers_t *images) -{ - void (*entry_point)(void); - - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("OSE"); - return 1; - } -#endif - - entry_point = (void (*)(void))images->ep; - - printf("## Transferring control to OSE (at address %08lx) ...\n", - (ulong)entry_point); - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); + bootm_disable_interrupts(); - /* - * OSE Parameters: - * None - */ - (*entry_point)(); + images.os.os = IH_OS_LINUX; + ret = do_bootm_states(cmdtp, flag, argc, argv, + BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO | + BOOTM_STATE_OS_GO, + &images, 1); - return 1; + return ret; } -#endif /* CONFIG_BOOTM_OSE */ - -#if defined(CONFIG_BOOTM_PLAN9) -static int do_bootm_plan9(int flag, int argc, char * const argv[], - bootm_headers_t *images) -{ - void (*entry_point)(void); - char *s; - - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("Plan 9"); - return 1; - } +#ifdef CONFIG_SYS_LONGHELP +static char bootz_help_text[] = + "[addr [initrd[:size]] [fdt]]\n" + " - boot Linux zImage stored in memory\n" + "\tThe argument 'initrd' is optional and specifies the address\n" + "\tof the initrd in memory. The optional argument ':size' allows\n" + "\tspecifying the size of RAW initrd.\n" +#if defined(CONFIG_OF_LIBFDT) + "\tWhen booting a Linux kernel which requires a flat device-tree\n" + "\ta third argument is required which is the address of the\n" + "\tdevice-tree blob. To boot that kernel without an initrd image,\n" + "\tuse a '-' for the second argument. If you do not pass a third\n" + "\ta bd_info struct will be passed instead\n" #endif - - /* See README.plan9 */ - s = getenv("confaddr"); - if (s != NULL) { - char *confaddr = (char *)simple_strtoul(s, NULL, 16); - - if (argc > 0) { - copy_args(confaddr, argc, argv, '\n'); - } else { - s = getenv("bootargs"); - if (s != NULL) - strcpy(confaddr, s); - } - } - - entry_point = (void (*)(void))images->ep; - - printf("## Transferring control to Plan 9 (at address %08lx) ...\n", - (ulong)entry_point); - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - - /* - * Plan 9 Parameters: - * None - */ - (*entry_point)(); - - return 1; -} -#endif /* CONFIG_BOOTM_PLAN9 */ - -#if defined(CONFIG_CMD_ELF) -static int do_bootm_vxworks(int flag, int argc, char * const argv[], - bootm_headers_t *images) -{ - char str[80]; - - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("VxWorks"); - return 1; - } + ""; #endif - sprintf(str, "%lx", images->ep); /* write entry-point into string */ - setenv("loadaddr", str); - do_bootvx(NULL, 0, 0, NULL); - - return 1; -} - -static int do_bootm_qnxelf(int flag, int argc, char * const argv[], - bootm_headers_t *images) -{ - char *local_args[2]; - char str[16]; - - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("QNX"); - return 1; - } -#endif +U_BOOT_CMD( + bootz, CONFIG_SYS_MAXARGS, 1, do_bootz, + "boot Linux zImage image from memory", bootz_help_text +); +#endif /* CONFIG_CMD_BOOTZ */ - sprintf(str, "%lx", images->ep); /* write entry-point into string */ - local_args[0] = argv[0]; - local_args[1] = str; /* and provide it via the arguments */ - do_bootelf(NULL, 0, 2, local_args); +#ifdef CONFIG_CMD_BOOTI +/* See Documentation/arm64/booting.txt in the Linux kernel */ +struct Image_header { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset, LE */ + uint64_t image_size; /* Effective Image size, LE */ + uint64_t res1; /* reserved */ + uint64_t res2; /* reserved */ + uint64_t res3; /* reserved */ + uint64_t res4; /* reserved */ + uint32_t magic; /* Magic number */ + uint32_t res5; +}; - return 1; -} -#endif +#define LINUX_ARM64_IMAGE_MAGIC 0x644d5241 -#ifdef CONFIG_INTEGRITY -static int do_bootm_integrity(int flag, int argc, char * const argv[], - bootm_headers_t *images) +static int booti_setup(bootm_headers_t *images) { - void (*entry_point)(void); + struct Image_header *ih; + uint64_t dst; - if (flag & BOOTM_STATE_OS_PREP) - return 0; - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; + ih = (struct Image_header *)map_sysmem(images->ep, 0); -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("INTEGRITY"); + if (ih->magic != le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC)) { + puts("Bad Linux ARM64 Image magic!\n"); return 1; } -#endif - - entry_point = (void (*)(void))images->ep; - - printf("## Transferring control to INTEGRITY (at address %08lx) ...\n", - (ulong)entry_point); - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + if (ih->image_size == 0) { + puts("Image lacks image_size field, assuming 16MiB\n"); + ih->image_size = (16 << 20); + } /* - * INTEGRITY Parameters: - * None + * If we are not at the correct run-time location, set the new + * correct location and then move the image there. */ - (*entry_point)(); - - return 1; -} -#endif + dst = gd->bd->bi_dram[0].start + le32_to_cpu(ih->text_offset); + if (images->ep != dst) { + void *src; -#ifdef CONFIG_CMD_BOOTZ + debug("Moving Image from 0x%lx to 0x%llx\n", images->ep, dst); -int __weak bootz_setup(ulong image, ulong *start, ulong *end) -{ - /* Please define bootz_setup() for your platform */ + src = (void *)images->ep; + images->ep = dst; + memmove((void *)dst, src, le32_to_cpu(ih->image_size)); + } - puts("Your platform's zImage format isn't supported yet!\n"); - return -1; + return 0; } /* - * zImage booting support + * Image booting support */ -static int bootz_start(cmd_tbl_t *cmdtp, int flag, int argc, +static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], bootm_headers_t *images) { int ret; - ulong zi_start, zi_end; + struct Image_header *ih; ret = do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START, images, 1); - /* Setup Linux kernel zImage entry point */ + /* Setup Linux kernel Image entry point */ if (!argc) { images->ep = load_addr; debug("* kernel: default image load address = 0x%08lx\n", @@ -1791,35 +707,32 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag, int argc, images->ep); } - ret = bootz_setup(images->ep, &zi_start, &zi_end); + ret = booti_setup(images); if (ret != 0) return 1; - lmb_reserve(&images->lmb, images->ep, zi_end - zi_start); + ih = (struct Image_header *)map_sysmem(images->ep, 0); + + lmb_reserve(&images->lmb, images->ep, le32_to_cpu(ih->image_size)); /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not * have a header that provide this informaiton. */ - if (bootm_find_ramdisk(flag, argc, argv)) - return 1; - -#if defined(CONFIG_OF_LIBFDT) - if (bootm_find_fdt(flag, argc, argv)) + if (bootm_find_ramdisk_fdt(flag, argc, argv)) return 1; -#endif return 0; } -int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int ret; - /* Consume 'bootz' */ + /* Consume 'booti' */ argc--; argv++; - if (bootz_start(cmdtp, flag, argc, argv, &images)) + if (booti_start(cmdtp, flag, argc, argv, &images)) return 1; /* @@ -1838,24 +751,23 @@ int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #ifdef CONFIG_SYS_LONGHELP -static char bootz_help_text[] = +static char booti_help_text[] = "[addr [initrd[:size]] [fdt]]\n" - " - boot Linux zImage stored in memory\n" + " - boot Linux Image stored in memory\n" "\tThe argument 'initrd' is optional and specifies the address\n" "\tof the initrd in memory. The optional argument ':size' allows\n" "\tspecifying the size of RAW initrd.\n" #if defined(CONFIG_OF_LIBFDT) - "\tWhen booting a Linux kernel which requires a flat device-tree\n" + "\tSince booting a Linux kernelrequires a flat device-tree\n" "\ta third argument is required which is the address of the\n" "\tdevice-tree blob. To boot that kernel without an initrd image,\n" - "\tuse a '-' for the second argument. If you do not pass a third\n" - "\ta bd_info struct will be passed instead\n" + "\tuse a '-' for the second argument.\n" #endif ""; #endif U_BOOT_CMD( - bootz, CONFIG_SYS_MAXARGS, 1, do_bootz, - "boot Linux zImage image from memory", bootz_help_text + booti, CONFIG_SYS_MAXARGS, 1, do_booti, + "boot arm64 Linux Image image from memory", booti_help_text ); -#endif /* CONFIG_CMD_BOOTZ */ +#endif /* CONFIG_CMD_BOOTI */ diff --git a/common/cmd_bootmenu.c b/common/cmd_bootmenu.c index 163d5b2e2b..5879065c2e 100644 --- a/common/cmd_bootmenu.c +++ b/common/cmd_bootmenu.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/common/cmd_cache.c b/common/cmd_cache.c index 602fecaba2..37ab345cb6 100644 --- a/common/cmd_cache.c +++ b/common/cmd_cache.c @@ -20,7 +20,7 @@ void __weak invalidate_icache_all(void) puts("No arch specific invalidate_icache_all available!\n"); } -int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { case 2: /* on / off */ @@ -52,7 +52,7 @@ void __weak flush_dcache_all(void) /* please define arch specific flush_dcache_all */ } -int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { case 2: /* on / off */ diff --git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644 index 0000000000..6d3d46a184 --- /dev/null +++ b/common/cmd_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +int __weak soc_clk_dump(void) +{ + puts("Not implemented\n"); + return 1; +} + +static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + return soc_clk_dump(); +} + +static cmd_tbl_t cmd_clk_sub[] = { + U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), +}; + +static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + /* Strip off leading 'clk' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +#ifdef CONFIG_SYS_LONGHELP +static char clk_help_text[] = + "dump - Print clock frequencies"; +#endif + +U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text); diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c index 896f79f416..4fddd804ab 100644 --- a/common/cmd_dcr.c +++ b/common/cmd_dcr.c @@ -10,6 +10,7 @@ */ #include +#include #include #include @@ -62,7 +63,7 @@ int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) do { value = get_dcr (dcrn); printf ("%04x: %08lx", dcrn, value); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0) { /* * pressed as only input, don't modify current diff --git a/common/cmd_demo.c b/common/cmd_demo.c new file mode 100644 index 0000000000..bcb34d9045 --- /dev/null +++ b/common/cmd_demo.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct udevice *demo_dev; + +static int do_demo_hello(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ch = 0; + + if (argc) + ch = *argv[0]; + + return demo_hello(demo_dev, ch); +} + +static int do_demo_status(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int status; + int ret; + + ret = demo_status(demo_dev, &status); + if (ret) + return ret; + + printf("Status: %d\n", status); + + return 0; +} + +static int do_demo_light(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int light; + int ret; + + if (argc) { + light = simple_strtoul(argv[0], NULL, 16); + ret = demo_set_light(demo_dev, light); + } else { + ret = demo_get_light(demo_dev); + if (ret >= 0) { + printf("Light: %x\n", ret); + ret = 0; + } + } + + return ret; +} + +int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + int i, ret; + + puts("Demo uclass entries:\n"); + + for (i = 0, ret = uclass_first_device(UCLASS_DEMO, &dev); + dev; + ret = uclass_next_device(&dev)) { + printf("entry %d - instance %08x, ops %08x, platdata %08x\n", + i++, map_to_sysmem(dev), + map_to_sysmem(dev->driver->ops), + map_to_sysmem(dev_get_platdata(dev))); + } + + return cmd_process_error(cmdtp, ret); +} + +static cmd_tbl_t demo_commands[] = { + U_BOOT_CMD_MKENT(list, 0, 1, do_demo_list, "", ""), + U_BOOT_CMD_MKENT(hello, 2, 1, do_demo_hello, "", ""), + U_BOOT_CMD_MKENT(light, 2, 1, do_demo_light, "", ""), + U_BOOT_CMD_MKENT(status, 1, 1, do_demo_status, "", ""), +}; + +static int do_demo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *demo_cmd; + int devnum = 0; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + demo_cmd = find_cmd_tbl(argv[1], demo_commands, + ARRAY_SIZE(demo_commands)); + argc -= 2; + argv += 2; + if (!demo_cmd || argc > demo_cmd->maxargs) + return CMD_RET_USAGE; + + if (argc) { + devnum = simple_strtoul(argv[0], NULL, 10); + ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev); + if (ret) + return cmd_process_error(cmdtp, ret); + argc--; + argv++; + } else { + demo_dev = NULL; + if (demo_cmd->cmd != do_demo_list) + return CMD_RET_USAGE; + } + + ret = demo_cmd->cmd(demo_cmd, flag, argc, argv); + + return cmd_process_error(demo_cmd, ret); +} + +U_BOOT_CMD( + demo, 4, 1, do_demo, + "Driver model (dm) demo operations", + "list List available demo devices\n" + "demo hello [] Say hello\n" + "demo light [] Set or get the lights\n" + "demo status Get demo device status\n" + "demo list List available demo devices" +); diff --git a/common/cmd_dfu.c b/common/cmd_dfu.c index 793c422123..e975abebc9 100644 --- a/common/cmd_dfu.c +++ b/common/cmd_dfu.c @@ -9,54 +9,57 @@ */ #include -#include -#include #include -#include #include +#include static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - const char *str_env; - char *s = "dfu"; - int ret, i = 0; - char *env_bkp; + bool dfu_reset = false; - if (argc < 3) + if (argc < 4) return CMD_RET_USAGE; - str_env = getenv("dfu_alt_info"); - if (str_env == NULL) { - printf("%s: \"dfu_alt_info\" env variable not defined!\n", - __func__); - return CMD_RET_FAILURE; - } + char *usb_controller = argv[1]; + char *interface = argv[2]; + char *devstring = argv[3]; + + int ret, i = 0; - env_bkp = strdup(str_env); - ret = dfu_config_entities(env_bkp, argv[1], - (int)simple_strtoul(argv[2], NULL, 10)); + ret = dfu_init_env_entities(interface, devstring); if (ret) - return CMD_RET_FAILURE; + goto done; - if (argc > 3 && strcmp(argv[3], "list") == 0) { + ret = CMD_RET_SUCCESS; + if (argc > 4 && strcmp(argv[4], "list") == 0) { dfu_show_entities(); goto done; } -#ifdef CONFIG_TRATS - board_usb_init(); -#endif - - g_dnl_register(s); + int controller_index = simple_strtoul(usb_controller, NULL, 0); + board_usb_init(controller_index, USB_INIT_DEVICE); + g_dnl_clear_detach(); + g_dnl_register("usb_dnl_dfu"); while (1) { - if (dfu_reset()) + if (g_dnl_detach()) { + /* + * Check if USB bus reset is performed after detach, + * which indicates that -R switch has been passed to + * dfu-util. In this case reboot the device + */ + if (dfu_usb_get_reset()) { + dfu_reset = true; + goto exit; + } + /* * This extra number of usb_gadget_handle_interrupts() * calls is necessary to assure correct transmission * completion with dfu-util */ - if (++i == 10) + if (++i == 10000) goto exit; + } if (ctrlc()) goto exit; @@ -67,18 +70,20 @@ exit: g_dnl_unregister(); done: dfu_free_entities(); - free(env_bkp); - if (dfu_reset()) + if (dfu_reset) run_command("reset", 0); - return CMD_RET_SUCCESS; + g_dnl_clear_detach(); + + return ret; } U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu, "Device Firmware Upgrade", - " [list]\n" - " - device firmware upgrade on a device \n" - " attached to interface \n" - " [list] - list available alt settings" + " [list]\n" + " - device firmware upgrade via \n" + " on device , attached to interface\n" + " \n" + " [list] - list available alt settings\n" ); diff --git a/common/cmd_disk.c b/common/cmd_disk.c index 3e457f672e..8a1fda9f68 100644 --- a/common/cmd_disk.c +++ b/common/cmd_disk.c @@ -17,7 +17,9 @@ int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, ulong addr = CONFIG_SYS_LOAD_ADDR; ulong cnt; disk_partition_t info; +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) image_header_t *hdr; +#endif block_dev_desc_t *dev_desc; #if defined(CONFIG_FIT) @@ -62,6 +64,7 @@ int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, bootstage_mark(BOOTSTAGE_ID_IDE_PART_READ); switch (genimg_get_format((void *) addr)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: hdr = (image_header_t *) addr; @@ -78,6 +81,7 @@ int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, cnt = image_get_image_size(hdr); break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *) addr; diff --git a/common/cmd_dtt.c b/common/cmd_dtt.c index 7257f10fb1..f2e750f2f1 100644 --- a/common/cmd_dtt.c +++ b/common/cmd_dtt.c @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index ef694d8f87..29f0f1f784 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -43,7 +43,7 @@ extern int eeprom_write_enable (unsigned dev_addr, int state); /* ------------------------------------------------------------------------- */ #if defined(CONFIG_CMD_EEPROM) -int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { const char *const fmt = "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... "; @@ -161,7 +161,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) spi_read (addr, alen, buffer, len); #else - if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) + if (i2c_read(addr[0], offset, alen - 1, buffer, len)) rcode = 1; #endif buffer += len; @@ -339,7 +339,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn /* Write is enabled ... now write eeprom value. */ #endif - if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) + if (i2c_write(addr[0], offset, alen - 1, buffer, len)) rcode = 1; #endif @@ -408,7 +408,7 @@ U_BOOT_CMD( "read devaddr addr off cnt\n" "eeprom write devaddr addr off cnt\n" " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'" -); +) #else /* One EEPROM */ U_BOOT_CMD( eeprom, 5, 1, do_eeprom, @@ -416,7 +416,7 @@ U_BOOT_CMD( "read addr off cnt\n" "eeprom write addr off cnt\n" " - read/write `cnt' bytes at EEPROM offset `off'" -); +) #endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */ #endif diff --git a/common/cmd_elf.c b/common/cmd_elf.c index f741f6b83f..58b61c2640 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -28,8 +29,7 @@ static unsigned long load_elf_image_phdr(unsigned long addr); static unsigned long load_elf_image_shdr(unsigned long addr); /* Allow ports to override the default behavior */ -__attribute__((weak)) -unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]), +static unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]), int argc, char * const argv[]) { unsigned long ret; @@ -156,16 +156,16 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * If we don't know where the image is then we're done. */ - if (argc < 1) + if (argc < 2) addr = load_addr; else - addr = simple_strtoul(argv[0], NULL, 16); + addr = simple_strtoul(argv[1], NULL, 16); #if defined(CONFIG_CMD_NET) /* * Check to see if we need to tftp the image ourselves before starting */ - if ((argc == 1) && (strcmp(argv[0], "tftp") == 0)) { + if ((argc == 2) && (strcmp(argv[1], "tftp") == 0)) { if (NetLoop(TFTPGET) <= 0) return 1; printf("Automatic boot of VxWorks image at address 0x%08lx ...\n", @@ -210,9 +210,9 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ bootline = getenv("bootargs"); if (bootline) { - memcpy((void *) bootaddr, bootline, - max(strlen(bootline), 255)); - flush_cache(bootaddr, max(strlen(bootline), 255)); + memcpy((void *)bootaddr, bootline, + max(strlen(bootline), (size_t)255)); + flush_cache(bootaddr, max(strlen(bootline), (size_t)255)); } else { sprintf(build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE); tmp = getenv("bootfile"); @@ -240,9 +240,9 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) CONFIG_SYS_VXWORKS_ADD_PARAMS); #endif - memcpy((void *) bootaddr, build_buf, - max(strlen(build_buf), 255)); - flush_cache(bootaddr, max(strlen(build_buf), 255)); + memcpy((void *)bootaddr, build_buf, + max(strlen(build_buf), (size_t)255)); + flush_cache(bootaddr, max(strlen(build_buf), (size_t)255)); } /* diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c index 173191980e..6657ef5ca4 100644 --- a/common/cmd_ext2.c +++ b/common/cmd_ext2.c @@ -22,7 +22,7 @@ */ #include -int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return do_ls(cmdtp, flag, argc, argv, FS_TYPE_EXT); } @@ -30,9 +30,9 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /****************************************************************************** * Ext2fs boot command intepreter. Derived from diskboot */ -int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16); + return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT); } U_BOOT_CMD( @@ -40,13 +40,12 @@ U_BOOT_CMD( "list files in a directory (default /)", " [directory]\n" " - list files from 'dev' on 'interface' in a 'directory'" -); +) U_BOOT_CMD( ext2load, 6, 0, do_ext2load, "load binary file from a Ext2 filesystem", - " [addr] [filename] [bytes]\n" + " [ [addr [filename [bytes [pos]]]]]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" - " to address 'addr' from ext2 filesystem.\n" - " All numeric parameters are assumed to be hex." -); + " to address 'addr' from ext2 filesystem." +) diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index 4a27cd97c0..19423d1c81 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -42,10 +42,16 @@ #include #endif +int do_ext4_size(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + return do_size(cmdtp, flag, argc, argv, FS_TYPE_EXT); +} + int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16); + return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT); } int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) @@ -55,72 +61,34 @@ int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) #if defined(CONFIG_CMD_EXT4_WRITE) int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) + char *const argv[]) { - const char *filename = "/"; - int dev, part; - unsigned long ram_address; - unsigned long file_size; - disk_partition_t info; - block_dev_desc_t *dev_desc; - - if (argc < 6) - return cmd_usage(cmdtp); - - part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); - if (part < 0) - return 1; - - dev = dev_desc->dev; - - /* get the filename */ - filename = argv[4]; - - /* get the address in hexadecimal format (string to int) */ - ram_address = simple_strtoul(argv[3], NULL, 16); - - /* get the filesize in base 10 format */ - file_size = simple_strtoul(argv[5], NULL, 10); - - /* set the device as block device */ - ext4fs_set_blk_dev(dev_desc, &info); - - /* mount the filesystem */ - if (!ext4fs_mount(info.size)) { - printf("Bad ext4 partition %s %d:%d\n", argv[1], dev, part); - goto fail; - } - - /* start write */ - if (ext4fs_write(filename, (unsigned char *)ram_address, file_size)) { - printf("** Error ext4fs_write() **\n"); - goto fail; - } - ext4fs_close(); - - return 0; - -fail: - ext4fs_close(); - - return 1; + return do_save(cmdtp, flag, argc, argv, FS_TYPE_EXT); } -U_BOOT_CMD(ext4write, 6, 1, do_ext4_write, - "create a file in the root directory", - " [sizebytes]\n" - " - create a file in / directory"); +U_BOOT_CMD(ext4write, 7, 1, do_ext4_write, + "create a file in the root directory", + " \n" + " [sizebytes] [file offset]\n" + " - create a file in / directory"); #endif +U_BOOT_CMD( + ext4size, 4, 0, do_ext4_size, + "determine a file's size", + " \n" + " - Find file 'filename' from 'dev' on 'interface'\n" + " and determine its size." +); + U_BOOT_CMD(ext4ls, 4, 1, do_ext4_ls, "list files in a directory (default /)", " [directory]\n" " - list files from 'dev' on 'interface' in a 'directory'"); -U_BOOT_CMD(ext4load, 6, 0, do_ext4_load, +U_BOOT_CMD(ext4load, 7, 0, do_ext4_load, "load binary file from a Ext4 filesystem", - " [addr] [filename] [bytes]\n" + " [ [addr [filename [bytes [pos]]]]]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" - " to address 'addr' from ext4 filesystem.\n" - " All numeric parameters are assumed to be hex."); + " to address 'addr' from ext4 filesystem"); diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c new file mode 100644 index 0000000000..b72f4f310d --- /dev/null +++ b/common/cmd_fastboot.c @@ -0,0 +1,41 @@ +/* + * Copyright 2008 - 2009 Windriver, + * Author: Tom Rix + * + * (C) Copyright 2014 Linaro, Ltd. + * Rob Herring + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + + g_dnl_clear_detach(); + ret = g_dnl_register("usb_dnl_fastboot"); + if (ret) + return ret; + + while (1) { + if (g_dnl_detach()) + break; + if (ctrlc()) + break; + usb_gadget_handle_interrupts(); + } + + g_dnl_unregister(); + g_dnl_clear_detach(); + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + fastboot, 1, 0, do_fastboot, + "use USB Fastboot protocol", + "\n" + " - run as a fastboot usb device" +); diff --git a/common/cmd_fat.c b/common/cmd_fat.c index f6d7affa0d..c00fb28b62 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -13,20 +13,34 @@ #include #include #include +#include #include #include #include +int do_fat_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return do_size(cmdtp, flag, argc, argv, FS_TYPE_FAT); +} + +U_BOOT_CMD( + fatsize, 4, 0, do_fat_size, + "determine a file's size", + " \n" + " - Find file 'filename' from 'dev' on 'interface'\n" + " and determine its size." +); + int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_load(cmdtp, flag, argc, argv, FS_TYPE_FAT, 16); + return do_load(cmdtp, flag, argc, argv, FS_TYPE_FAT); } U_BOOT_CMD( fatload, 7, 0, do_fat_fsload, "load binary file from a dos filesystem", - " [] [bytes [pos]]\n" + " [ [ [ [bytes [pos]]]]]\n" " - Load binary file 'filename' from 'dev' on 'interface'\n" " to address 'addr' from dos filesystem.\n" " 'pos' gives the file position to start loading from.\n" @@ -35,8 +49,7 @@ U_BOOT_CMD( " the load stops on end of file.\n" " If either 'pos' or 'bytes' are not aligned to\n" " ARCH_DMA_MINALIGN then a misaligned buffer warning will\n" - " be printed and performance will suffer for the load.\n" - " All numeric parameters are assumed to be hex." + " be printed and performance will suffer for the load." ); static int do_fat_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -87,13 +100,15 @@ U_BOOT_CMD( static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - long size; + loff_t size; + int ret; unsigned long addr; unsigned long count; block_dev_desc_t *dev_desc = NULL; disk_partition_t info; int dev = 0; int part = 1; + void *buf; if (argc < 5) return cmd_usage(cmdtp); @@ -112,14 +127,16 @@ static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag, addr = simple_strtoul(argv[3], NULL, 16); count = simple_strtoul(argv[5], NULL, 16); - size = file_fat_write(argv[4], (void *)addr, count); - if (size == -1) { + buf = map_sysmem(addr, count); + ret = file_fat_write(argv[4], buf, 0, count, &size); + unmap_sysmem(buf); + if (ret < 0) { printf("\n** Unable to write \"%s\" from %s %d:%d **\n", argv[4], argv[1], dev, part); return 1; } - printf("%ld bytes written\n", size); + printf("%llu bytes written\n", size); return 0; } diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index 98b3c4c001..5766b5650b 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -627,72 +627,6 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) return true; } -#if defined(CONFIG_CMD_FDOS) - -/* Low level functions for the Floppy-DOS layer */ - -/************************************************************************** -* int fdc_fdos_init -* initialize the FDC layer -* -*/ -int fdc_fdos_init (int drive) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - /* setup FDC and scan for drives */ - if (fdc_setup(drive, pCMD, pFG) == false) { - printf("\n** Error in setup FDC **\n"); - return false; - } - if (fdc_check_drive(pCMD, pFG) == false) { - printf("\n** Error in check_drives **\n"); - return false; - } - if((pCMD->flags&(1<flags&(0x10<drive=drive; - - /* read first block */ - pCMD->blnr=0; - return true; -} -/************************************************************************** -* int fdc_fdos_seek -* parameter is a block number -*/ -int fdc_fdos_seek (int where) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - pCMD -> blnr = where ; - return (fdc_seek (pCMD, pFG)); -} -/************************************************************************** -* int fdc_fdos_read -* the length is in block number -*/ -int fdc_fdos_read (void *buffer, int len) -{ - FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; - FDC_COMMAND_STRUCT *pCMD = &cmd; - - return (fdc_read_data (buffer, len, pCMD, pFG)); -} -#endif - -#if defined(CONFIG_CMD_FDC) /**************************************************************************** * main routine do_fdcboot */ @@ -701,7 +635,9 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; FDC_COMMAND_STRUCT *pCMD = &cmd; unsigned long addr,imsize; +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) image_header_t *hdr; /* used for fdc boot */ +#endif unsigned char boot_drive; int i,nrofblk; #if defined(CONFIG_FIT) @@ -755,12 +691,14 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } switch (genimg_get_format ((void *)addr)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: hdr = (image_header_t *)addr; image_print_contents (hdr); imsize = image_get_image_size (hdr); break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; @@ -812,4 +750,3 @@ U_BOOT_CMD( "boot from floppy device", "loadAddr drive" ); -#endif diff --git a/common/cmd_fdos.c b/common/cmd_fdos.c deleted file mode 100644 index 69303255ff..0000000000 --- a/common/cmd_fdos.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Dos floppy support - */ - -#include -#include -#include -#include - -/*----------------------------------------------------------------------------- - * do_fdosboot -- - *----------------------------------------------------------------------------- - */ -int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *name; - char *ep; - int size; - int drive = CONFIG_SYS_FDC_DRIVE_NUMBER; - - /* pre-set load_addr */ - if ((ep = getenv("loadaddr")) != NULL) { - load_addr = simple_strtoul(ep, NULL, 16); - } - - /* pre-set Boot file name */ - if ((name = getenv("bootfile")) == NULL) { - name = "uImage"; - } - - switch (argc) { - case 1: - break; - case 2: - /* only one arg - accept two forms: - * just load address, or just boot file name. - * The latter form must be written "filename" here. - */ - if (argv[1][0] == '"') { /* just boot filename */ - name = argv [1]; - } else { /* load address */ - load_addr = simple_strtoul(argv[1], NULL, 16); - } - break; - case 3: - load_addr = simple_strtoul(argv[1], NULL, 16); - name = argv [2]; - break; - default: - return CMD_RET_USAGE; - } - - /* Init physical layer */ - if (!fdc_fdos_init (drive)) { - return (-1); - } - - /* Open file */ - if (dos_open (name) < 0) { - printf ("Unable to open %s\n", name); - return 1; - } - if ((size = dos_read (load_addr)) < 0) { - printf ("boot error\n"); - return 1; - } - flush_cache (load_addr, size); - - setenv_hex("filesize", size); - - printf("Floppy DOS load complete: %d bytes loaded to 0x%lx\n", - size, load_addr); - - return bootm_maybe_autostart(cmdtp, argv[0]); -} - -/*----------------------------------------------------------------------------- - * do_fdosls -- - *----------------------------------------------------------------------------- - */ -int do_fdosls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *path = ""; - int drive = CONFIG_SYS_FDC_DRIVE_NUMBER; - - switch (argc) { - case 1: - break; - case 2: - path = argv [1]; - break; - } - - /* Init physical layer */ - if (!fdc_fdos_init (drive)) { - return (-1); - } - /* Open directory */ - if (dos_open (path) < 0) { - printf ("Unable to open %s\n", path); - return 1; - } - return (dos_dir ()); -} - -U_BOOT_CMD( - fdosboot, 3, 0, do_fdosboot, - "boot from a dos floppy file", - "[loadAddr] [filename]" -); - -U_BOOT_CMD( - fdosls, 2, 0, do_fdosls, - "list files in a directory", - "[directory]" -); diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index e17c3f1d51..dc59fab828 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -123,7 +123,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (control) gd->fdt_blob = blob; else - set_working_fdt_addr(blob); + set_working_fdt_addr((void *)blob); if (argc >= 2) { int len; @@ -566,11 +566,30 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #ifdef CONFIG_OF_BOARD_SETUP /* Call the board-specific fixup routine */ - else if (strncmp(argv[1], "boa", 3) == 0) - ft_board_setup(working_fdt, gd->bd); + else if (strncmp(argv[1], "boa", 3) == 0) { + int err = ft_board_setup(working_fdt, gd->bd); + + if (err) { + printf("Failed to update board information in FDT: %s\n", + fdt_strerror(err)); + return CMD_RET_FAILURE; + } + } +#endif +#ifdef CONFIG_OF_SYSTEM_SETUP + /* Call the board-specific fixup routine */ + else if (strncmp(argv[1], "sys", 3) == 0) { + int err = ft_system_setup(working_fdt, gd->bd); + + if (err) { + printf("Failed to add system information to FDT: %s\n", + fdt_strerror(err)); + return CMD_RET_FAILURE; + } + } #endif /* Create a chosen node */ - else if (argv[1][0] == 'c') { + else if (strncmp(argv[1], "cho", 3) == 0) { unsigned long initrd_start = 0, initrd_end = 0; if ((argc != 2) && (argc != 4)) @@ -581,12 +600,47 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) initrd_end = simple_strtoul(argv[3], NULL, 16); } - fdt_chosen(working_fdt, 1); - fdt_initrd(working_fdt, initrd_start, initrd_end, 1); + fdt_chosen(working_fdt); + fdt_initrd(working_fdt, initrd_start, initrd_end); + +#if defined(CONFIG_FIT_SIGNATURE) + } else if (strncmp(argv[1], "che", 3) == 0) { + int cfg_noffset; + int ret; + unsigned long addr; + struct fdt_header *blob; + + if (!working_fdt) + return CMD_RET_FAILURE; + + if (argc > 2) { + addr = simple_strtoul(argv[2], NULL, 16); + blob = map_sysmem(addr, 0); + } else { + blob = (struct fdt_header *)gd->fdt_blob; + } + if (!fdt_valid(&blob)) + return 1; + + gd->fdt_blob = blob; + cfg_noffset = fit_conf_get_node(working_fdt, NULL); + if (!cfg_noffset) { + printf("Could not find configuration node: %s\n", + fdt_strerror(cfg_noffset)); + return CMD_RET_FAILURE; + } + + ret = fit_config_verify(working_fdt, cfg_noffset); + if (ret == 0) + return CMD_RET_SUCCESS; + else + return CMD_RET_FAILURE; +#endif + } /* resize the fdt */ else if (strncmp(argv[1], "re", 2) == 0) { - fdt_resize(working_fdt); + fdt_shrink_to_minimum(working_fdt); } else { /* Unrecognized command */ @@ -972,6 +1026,9 @@ static char fdt_help_text[] = "addr [-c] [] - Set the [control] fdt location to \n" #ifdef CONFIG_OF_BOARD_SETUP "fdt boardsetup - Do board-specific set up\n" +#endif +#ifdef CONFIG_OF_SYSTEM_SETUP + "fdt systemsetup - Do system-specific set up\n" #endif "fdt move - Copy the fdt to and make it active\n" "fdt resize - Resize fdt to size + padding to 4k addr\n" @@ -992,7 +1049,12 @@ static char fdt_help_text[] = "fdt rsvmem delete - Delete a mem reserves\n" "fdt chosen [ ] - Add/update the /chosen branch in the tree\n" " / - initrd start/end addr\n" - "NOTE: Dereference aliases by omitting the leading '/', " +#if defined(CONFIG_FIT_SIGNATURE) + "fdt checksign [] - check FIT signature\n" + " - addr of key blob\n" + " default gd->fdt_blob\n" +#endif + "NOTE: Dereference aliases by omiting the leading '/', " "e.g. fdt print ethernet0."; #endif diff --git a/common/cmd_fitupd.c b/common/cmd_fitupd.c index e811473b47..b0459744d9 100644 --- a/common/cmd_fitupd.c +++ b/common/cmd_fitupd.c @@ -1,12 +1,8 @@ -de - -#if !defined(CONFIG_UPDATE_TFTP) -#error "CONFIG_UPDATE_TFTP required" -#endif - -static int do_fitupd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr = 0Un the root directory of the source tree for details. +/* + * (C) Copyright 2011 + * Andreas Pretzsch, carpe noctem engineering, apr@cn-eng.de + * + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index c4b3c8fc56..7f99aabf8a 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -11,6 +11,7 @@ #include #include #include +#include #include /* Local functions */ @@ -23,6 +24,9 @@ static int fpga_get_op(char *opstr); #define FPGA_LOADB 2 #define FPGA_DUMP 3 #define FPGA_LOADMK 4 +#define FPGA_LOADP 5 +#define FPGA_LOADBP 6 +#define FPGA_LOADFS 7 /* ------------------------------------------------------------------------- */ /* command form: @@ -45,6 +49,10 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) const char *fit_uname = NULL; ulong fit_addr; #endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + fpga_fs_info fpga_fsinfo; + fpga_fsinfo.fstype = FS_TYPE_ANY; +#endif if (devstr) dev = (int) simple_strtoul(devstr, NULL, 16); @@ -52,6 +60,14 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fpga_data = (void *)simple_strtoul(datastr, NULL, 16); switch (argc) { +#if defined(CONFIG_CMD_FPGA_LOADFS) + case 9: + fpga_fsinfo.blocksize = (unsigned int) + simple_strtoul(argv[5], NULL, 16); + fpga_fsinfo.interface = argv[6]; + fpga_fsinfo.dev_part = argv[7]; + fpga_fsinfo.filename = argv[8]; +#endif case 5: /* fpga */ data_size = simple_strtoul(argv[4], NULL, 16); @@ -120,16 +136,27 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) case FPGA_NONE: case FPGA_INFO: break; +#if defined(CONFIG_CMD_FPGA_LOADFS) + case FPGA_LOADFS: + /* Blocksize can be zero */ + if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part || + !fpga_fsinfo.filename) + wrong_parms = 1; +#endif case FPGA_LOAD: + case FPGA_LOADP: case FPGA_LOADB: + case FPGA_LOADBP: case FPGA_DUMP: if (!fpga_data || !data_size) wrong_parms = 1; break; +#if defined(CONFIG_CMD_FPGA_LOADMK) case FPGA_LOADMK: if (!fpga_data) wrong_parms = 1; break; +#endif } if (wrong_parms) { @@ -146,26 +173,69 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) break; case FPGA_LOAD: - rc = fpga_load(dev, fpga_data, data_size); + rc = fpga_load(dev, fpga_data, data_size, BIT_FULL); + break; + +#if defined(CONFIG_CMD_FPGA_LOADP) + case FPGA_LOADP: + rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL); break; +#endif case FPGA_LOADB: - rc = fpga_loadbitstream(dev, fpga_data, data_size); + rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL); break; +#if defined(CONFIG_CMD_FPGA_LOADBP) + case FPGA_LOADBP: + rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL); + break; +#endif + +#if defined(CONFIG_CMD_FPGA_LOADFS) + case FPGA_LOADFS: + rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo); + break; +#endif + +#if defined(CONFIG_CMD_FPGA_LOADMK) case FPGA_LOADMK: switch (genimg_get_format(fpga_data)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: { image_header_t *hdr = (image_header_t *)fpga_data; ulong data; - - data = (ulong)image_get_data(hdr); - data_size = image_get_data_size(hdr); - rc = fpga_load(dev, (void *)data, data_size); + uint8_t comp; + + comp = image_get_comp(hdr); + if (comp == IH_COMP_GZIP) { +#if defined(CONFIG_GZIP) + ulong image_buf = image_get_data(hdr); + data = image_get_load(hdr); + ulong image_size = ~0UL; + + if (gunzip((void *)data, ~0UL, + (void *)image_buf, + &image_size) != 0) { + puts("GUNZIP: error\n"); + return 1; + } + data_size = image_size; +#else + puts("Gunzip image is not supported\n"); + return 1; +#endif + } else { + data = (ulong)image_get_data(hdr); + data_size = image_get_data_size(hdr); + } + rc = fpga_load(dev, (void *)data, data_size, + BIT_FULL); } break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: { @@ -205,7 +275,8 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) return 1; } - rc = fpga_load(dev, fit_data, data_size); + rc = fpga_load(dev, fit_data, data_size, + BIT_FULL); } break; #endif @@ -215,6 +286,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) break; } break; +#endif case FPGA_DUMP: rc = fpga_dump(dev, fpga_data, data_size); @@ -241,8 +313,22 @@ static int fpga_get_op(char *opstr) op = FPGA_LOADB; else if (!strcmp("load", opstr)) op = FPGA_LOAD; +#if defined(CONFIG_CMD_FPGA_LOADP) + else if (!strcmp("loadp", opstr)) + op = FPGA_LOADP; +#endif +#if defined(CONFIG_CMD_FPGA_LOADBP) + else if (!strcmp("loadbp", opstr)) + op = FPGA_LOADBP; +#endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + else if (!strcmp("loadfs", opstr)) + op = FPGA_LOADFS; +#endif +#if defined(CONFIG_CMD_FPGA_LOADMK) else if (!strcmp("loadmk", opstr)) op = FPGA_LOADMK; +#endif else if (!strcmp("dump", opstr)) op = FPGA_DUMP; @@ -252,19 +338,39 @@ static int fpga_get_op(char *opstr) return op; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +U_BOOT_CMD(fpga, 9, 1, do_fpga, +#else U_BOOT_CMD(fpga, 6, 1, do_fpga, +#endif "loadable FPGA image support", "[operation type] [device number] [image address] [image size]\n" "fpga operations:\n" - " dump\t[dev]\t\t\tLoad device to memory buffer\n" + " dump\t[dev] [address] [size]\tLoad device to memory buffer\n" " info\t[dev]\t\t\tlist known device information\n" " load\t[dev] [address] [size]\tLoad device from memory buffer\n" +#if defined(CONFIG_CMD_FPGA_LOADP) + " loadp\t[dev] [address] [size]\t" + "Load device from memory buffer with partial bitstream\n" +#endif " loadb\t[dev] [address] [size]\t" "Load device from bitstream buffer (Xilinx only)\n" +#if defined(CONFIG_CMD_FPGA_LOADBP) + " loadbp\t[dev] [address] [size]\t" + "Load device from bitstream buffer with partial bitstream" + "(Xilinx only)\n" +#endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + "Load device from filesystem (FAT by default) (Xilinx only)\n" + " loadfs [dev] [address] [image size] [blocksize] \n" + " [] \n" +#endif +#if defined(CONFIG_CMD_FPGA_LOADMK) " loadmk [dev] [address]\tLoad device generated with mkimage" #if defined(CONFIG_FIT) "\n" "\tFor loadmk operating on FIT format uImage address must include\n" "\tsubimage unit name in the form of addr:" #endif +#endif ); diff --git a/common/cmd_fpgad.c b/common/cmd_fpgad.c index 1b25ed8747..1f1d00f28a 100644 --- a/common/cmd_fpgad.c +++ b/common/cmd_fpgad.c @@ -31,7 +31,8 @@ int do_fpga_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned int fpga; ulong addr, length; int rc = 0; - u16 linebuf[DISP_LINE_LEN/sizeof(u16)]; + u16 linebuf[DISP_LINE_LEN/sizeof(u16)]; + ulong nbytes; /* * We use the last specified parameters, unless new ones are @@ -63,13 +64,28 @@ int do_fpga_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) length = simple_strtoul(argv[3], NULL, 16); } - /* Print the lines. */ - for (k = 0; k < DISP_LINE_LEN / sizeof(u16); ++k) - fpga_get_reg(fpga, (u16 *)fpga_ptr[fpga] + k, k * sizeof(u16), - &linebuf[k]); - print_buffer(addr, (void *)linebuf, sizeof(u16), - length, DISP_LINE_LEN / sizeof(u16)); - addr += sizeof(u16)*length; + nbytes = length * sizeof(u16); + do { + ulong linebytes = (nbytes > DISP_LINE_LEN) ? + DISP_LINE_LEN : nbytes; + + for (k = 0; k < linebytes / sizeof(u16); ++k) + fpga_get_reg(fpga, + (u16 *)fpga_ptr[fpga] + addr + / sizeof(u16) + k, + addr + k * sizeof(u16), + &linebuf[k]); + print_buffer(addr, (void *)linebuf, sizeof(u16), + linebytes / sizeof(u16), + DISP_LINE_LEN / sizeof(u16)); + + nbytes -= linebytes; + addr += linebytes; + if (ctrlc()) { + rc = 1; + break; + } + } while (nbytes > 0); dp_last_fpga = fpga; dp_last_addr = addr; diff --git a/common/cmd_fs.c b/common/cmd_fs.c index a681d03d1b..e146254f6d 100644 --- a/common/cmd_fs.c +++ b/common/cmd_fs.c @@ -20,9 +20,23 @@ #include #include -int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_size_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY, 0); + return do_size(cmdtp, flag, argc, argv, FS_TYPE_ANY); +} + +U_BOOT_CMD( + size, 4, 0, do_size_wrapper, + "determine a file's size", + " \n" + " - Find file 'filename' from 'dev' on 'interface'\n" + " and determine its size." +); + +static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY); } U_BOOT_CMD( @@ -34,12 +48,28 @@ U_BOOT_CMD( " 'bytes' gives the size to load in bytes.\n" " If 'bytes' is 0 or omitted, the file is read until the end.\n" " 'pos' gives the file byte position to start reading from.\n" - " If 'pos' is 0 or omitted, the file is read from the start.\n" - " All numeric parameters are assumed to be decimal,\n" - " unless specified otherwise using a leading \"0x\"." -); + " If 'pos' is 0 or omitted, the file is read from the start." +) -int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_save_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return do_save(cmdtp, flag, argc, argv, FS_TYPE_ANY); +} + +U_BOOT_CMD( + save, 7, 0, do_save_wrapper, + "save file to a filesystem", + " bytes [pos]\n" + " - Save binary file 'filename' to partition 'part' on device\n" + " type 'interface' instance 'dev' from addr 'addr' in memory.\n" + " 'bytes' gives the size to save in bytes and is mandatory.\n" + " 'pos' gives the file byte position to start writing to.\n" + " If 'pos' is 0 or omitted, the file is written from the start." +) + +static int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { return do_ls(cmdtp, flag, argc, argv, FS_TYPE_ANY); } @@ -50,4 +80,19 @@ U_BOOT_CMD( " [ [directory]]\n" " - List files in directory 'directory' of partition 'part' on\n" " device type 'interface' instance 'dev'." +) + +static int do_fstype_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return do_fs_type(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + fstype, 4, 1, do_fstype_wrapper, + "Look up a filesystem type", + " :\n" + "- print filesystem type\n" + "fstype : \n" + "- set environment variable to filesystem type\n" ); diff --git a/common/cmd_fs_uuid.c b/common/cmd_fs_uuid.c new file mode 100644 index 0000000000..613f3a4f3d --- /dev/null +++ b/common/cmd_fs_uuid.c @@ -0,0 +1,26 @@ +/* + * cmd_fs_uuid.c -- fsuuid command + * + * Copyright (C) 2014, Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static int do_fs_uuid_wrapper(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + return do_fs_uuid(cmdtp, flag, argc, argv, FS_TYPE_ANY); +} + +U_BOOT_CMD( + fsuuid, 4, 1, do_fs_uuid_wrapper, + "Look up a filesystem UUID", + " :\n" + " - print filesystem UUID\n" + "fsuuid : \n" + " - set environment variable to filesystem UUID\n" +); diff --git a/common/cmd_fuse.c b/common/cmd_fuse.c index 0df57dbc80..4d4f77a72d 100644 --- a/common/cmd_fuse.c +++ b/common/cmd_fuse.c @@ -33,15 +33,8 @@ static int confirm_prog(void) "what you are doing!\n" "\nReally perform this fuse programming? \n"); - if (getc() == 'y') { - int c; - - putc('y'); - c = getc(); - putc('\n'); - if (c == '\r') - return 1; - } + if (confirm_yesno()) + return 1; puts("Fuse programming aborted\n"); return 0; @@ -70,13 +63,13 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) printf("Reading bank %u:\n", bank); for (i = 0; i < cnt; i++, word++) { if (!(i % 4)) - printf("\nWord 0x%.8x:", word); + printf("\nWord 0x%08x:", word); ret = fuse_read(bank, word, &val); if (ret) goto err; - printf(" %.8x", val); + printf(" %08x", val); } putc('\n'); } else if (!strcmp(op, "sense")) { @@ -88,13 +81,13 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) printf("Sensing bank %u:\n", bank); for (i = 0; i < cnt; i++, word++) { if (!(i % 4)) - printf("\nWord 0x%.8x:", word); + printf("\nWord 0x%08x:", word); ret = fuse_sense(bank, word, &val); if (ret) goto err; - printf(" %.8x", val); + printf(" %08x", val); } putc('\n'); } else if (!strcmp(op, "prog")) { @@ -105,7 +98,7 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (strtou32(argv[i], 16, &val)) return CMD_RET_USAGE; - printf("Programming bank %u word 0x%.8x to 0x%.8x...\n", + printf("Programming bank %u word 0x%08x to 0x%08x...\n", bank, word, val); if (!confirmed && !confirm_prog()) return CMD_RET_FAILURE; @@ -121,8 +114,8 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (strtou32(argv[i], 16, &val)) return CMD_RET_USAGE; - printf("Overriding bank %u word 0x%.8x with " - "0x%.8x...\n", bank, word, val); + printf("Overriding bank %u word 0x%08x with 0x%08x...\n", + bank, word, val); ret = fuse_override(bank, word, val); if (ret) goto err; @@ -135,7 +128,7 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) err: puts("ERROR\n"); - return ret; + return CMD_RET_FAILURE; } U_BOOT_CMD( diff --git a/common/cmd_gettime.c b/common/cmd_gettime.c index 320ff709fa..c48baad9a1 100644 --- a/common/cmd_gettime.c +++ b/common/cmd_gettime.c @@ -35,6 +35,6 @@ static int do_gettime(cmd_tbl_t *cmdtp, int flag, int argc, U_BOOT_CMD( gettime, 1, 1, do_gettime, - "get timer val elapsed,\n", - "get time elapsed from uboot start\n" + "get timer val elapsed", + "get time elapsed from uboot start" ); diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c index 47eee89221..65d6df451c 100644 --- a/common/cmd_gpio.c +++ b/common/cmd_gpio.c @@ -8,12 +8,14 @@ #include #include - +#include +#include #include -#ifndef name_to_gpio -#define name_to_gpio(name) simple_strtoul(name, NULL, 10) -#endif +__weak int name_to_gpio(const char *name) +{ + return simple_strtoul(name, NULL, 10); +} enum gpio_cmd { GPIO_INPUT, @@ -22,25 +24,137 @@ enum gpio_cmd { GPIO_TOGGLE, }; +#if defined(CONFIG_DM_GPIO) && !defined(gpio_status) + +/* A few flags used by show_gpio() */ +enum { + FLAG_SHOW_ALL = 1 << 0, + FLAG_SHOW_BANK = 1 << 1, + FLAG_SHOW_NEWLINE = 1 << 2, +}; + +static void gpio_get_description(struct udevice *dev, const char *bank_name, + int offset, int *flagsp) +{ + char buf[80]; + int ret; + + ret = gpio_get_function(dev, offset, NULL); + if (ret < 0) + goto err; + if (!(*flagsp & FLAG_SHOW_ALL) && ret == GPIOF_UNUSED) + return; + if ((*flagsp & FLAG_SHOW_BANK) && bank_name) { + if (*flagsp & FLAG_SHOW_NEWLINE) { + putc('\n'); + *flagsp &= ~FLAG_SHOW_NEWLINE; + } + printf("Bank %s:\n", bank_name); + *flagsp &= ~FLAG_SHOW_BANK; + } + + ret = gpio_get_status(dev, offset, buf, sizeof(buf)); + if (ret) + goto err; + + printf("%s\n", buf); + return; +err: + printf("Error %d\n", ret); +} + +static int do_gpio_status(bool all, const char *gpio_name) +{ + struct udevice *dev; + int banklen; + int flags; + int ret; + + flags = 0; + if (gpio_name && !*gpio_name) + gpio_name = NULL; + for (ret = uclass_first_device(UCLASS_GPIO, &dev); + dev; + ret = uclass_next_device(&dev)) { + const char *bank_name; + int num_bits; + + flags |= FLAG_SHOW_BANK; + if (all) + flags |= FLAG_SHOW_ALL; + bank_name = gpio_get_bank_info(dev, &num_bits); + if (!num_bits) { + debug("GPIO device %s has no bits\n", dev->name); + continue; + } + banklen = bank_name ? strlen(bank_name) : 0; + + if (!gpio_name || !bank_name || + !strncmp(gpio_name, bank_name, banklen)) { + const char *p = NULL; + int offset; + + p = gpio_name + banklen; + if (gpio_name && *p) { + offset = simple_strtoul(p, NULL, 10); + gpio_get_description(dev, bank_name, offset, + &flags); + } else { + for (offset = 0; offset < num_bits; offset++) { + gpio_get_description(dev, bank_name, + offset, &flags); + } + } + } + /* Add a newline between bank names */ + if (!(flags & FLAG_SHOW_BANK)) + flags |= FLAG_SHOW_NEWLINE; + } + + return ret; +} +#endif + static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int gpio; + unsigned int gpio; enum gpio_cmd sub_cmd; ulong value; - const char *str_cmd, *str_gpio; + const char *str_cmd, *str_gpio = NULL; + int ret; +#ifdef CONFIG_DM_GPIO + bool all = false; +#endif + if (argc < 2) + show_usage: + return CMD_RET_USAGE; + str_cmd = argv[1]; + argc -= 2; + argv += 2; +#ifdef CONFIG_DM_GPIO + if (argc > 0 && !strcmp(*argv, "-a")) { + all = true; + argc--; + argv++; + } +#endif + if (argc > 0) + str_gpio = *argv; + if (!strcmp(str_cmd, "status")) { + /* Support deprecated gpio_status() */ #ifdef gpio_status - if (argc == 2 && !strcmp(argv[1], "status")) { gpio_status(); return 0; - } +#elif defined(CONFIG_DM_GPIO) + return cmd_process_error(cmdtp, do_gpio_status(all, str_gpio)); +#else + goto show_usage; #endif + } - if (argc != 3) - show_usage: - return CMD_RET_USAGE; - str_cmd = argv[1]; - str_gpio = argv[2]; + if (!str_gpio) + goto show_usage; /* parse the behavior */ switch (*str_cmd) { @@ -51,13 +165,26 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) default: goto show_usage; } +#if defined(CONFIG_DM_GPIO) + /* + * TODO(sjg@chromium.org): For now we must fit into the existing GPIO + * framework, so we look up the name here and convert it to a GPIO number. + * Once all GPIO drivers are converted to driver model, we can change the + * code here to use the GPIO uclass interface instead of the numbered + * GPIO compatibility layer. + */ + ret = gpio_lookup_name(str_gpio, NULL, NULL, &gpio); + if (ret) + return cmd_process_error(cmdtp, ret); +#else /* turn the gpio name into a gpio number */ gpio = name_to_gpio(str_gpio); if (gpio < 0) goto show_usage; - +#endif /* grab the pin before we tweak it */ - if (gpio_request(gpio, "cmd_gpio")) { + ret = gpio_request(gpio, "cmd_gpio"); + if (ret && ret != -EBUSY) { printf("gpio: requesting pin %u failed\n", gpio); return -1; } @@ -78,12 +205,14 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("gpio: pin %s (gpio %i) value is %lu\n", str_gpio, gpio, value); - gpio_free(gpio); + if (ret != -EBUSY) + gpio_free(gpio); return value; } -U_BOOT_CMD(gpio, 3, 0, do_gpio, - "input/set/clear/toggle gpio pins", - " \n" - " - input/set/clear/toggle the specified pin"); +U_BOOT_CMD(gpio, 4, 0, do_gpio, + "query and control gpio pins", + " \n" + " - input/set/clear/toggle the specified pin\n" + "gpio status [-a] [ | ] - show [all/claimed] GPIOs"); diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index d8c6b43158..446da2c970 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -30,30 +29,53 @@ * * @return - zero on successful expand and env is set */ -static char extract_env(const char *str, char **env) +static int extract_env(const char *str, char **env) { + int ret = -1; char *e, *s; +#ifdef CONFIG_RANDOM_UUID + char uuid_str[UUID_STR_LEN + 1]; +#endif if (!str || strlen(str) < 4) return -1; - if ((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')) { - s = strdup(str); - if (s == NULL) - return -1; - memset(s + strlen(s) - 1, '\0', 1); - memmove(s, s + 2, strlen(s) - 1); + if (!((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}'))) + return -1; + + s = strdup(str); + if (s == NULL) + return -1; + + memset(s + strlen(s) - 1, '\0', 1); + memmove(s, s + 2, strlen(s) - 1); + + e = getenv(s); + if (e == NULL) { +#ifdef CONFIG_RANDOM_UUID + debug("%s unset. ", str); + gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_STD); + setenv(s, uuid_str); + e = getenv(s); - free(s); - if (e == NULL) { - printf("Environmental '%s' not set\n", str); - return -1; /* env not set */ + if (e) { + debug("Set to random.\n"); + ret = 0; + } else { + debug("Can't get random UUID.\n"); } - *env = e; - return 0; +#else + debug("%s unset.\n", str); +#endif + } else { + debug("%s get from environment.\n", str); + ret = 0; } - return -1; + *env = e; + free(s); + + return ret; } /** @@ -123,7 +145,7 @@ static int set_gpt_info(block_dev_desc_t *dev_desc, int errno = 0; uint64_t size_ll, start_ll; - debug("%s: MMC lba num: 0x%x %d\n", __func__, + debug("%s: lba num: 0x%x %d\n", __func__, (unsigned int)dev_desc->lba, (unsigned int)dev_desc->lba); if (str_part == NULL) @@ -166,7 +188,7 @@ static int set_gpt_info(block_dev_desc_t *dev_desc, /* allocate memory for partitions */ parts = calloc(sizeof(disk_partition_t), p_count); - /* retrive partions data from string */ + /* retrieve partitions data from string */ for (i = 0; i < p_count; i++) { tok = strsep(&s, ";"); @@ -247,25 +269,18 @@ free_str: return errno; } -static int gpt_mmc_default(int dev, const char *str_part) +static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part) { int ret; char *str_disk_guid; u8 part_count = 0; disk_partition_t *partitions = NULL; - struct mmc *mmc = find_mmc_device(dev); - - if (mmc == NULL) { - printf("%s: mmc dev %d NOT available\n", __func__, dev); - return CMD_RET_FAILURE; - } - if (!str_part) return -1; /* fill partitions */ - ret = set_gpt_info(&mmc->block_dev, str_part, + ret = set_gpt_info(blk_dev_desc, str_part, &str_disk_guid, &partitions, &part_count); if (ret) { if (ret == -1) @@ -278,7 +293,7 @@ static int gpt_mmc_default(int dev, const char *str_part) } /* save partitions layout to disk */ - gpt_restore(&mmc->block_dev, str_disk_guid, partitions, part_count); + gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count); free(str_disk_guid); free(partitions); @@ -299,26 +314,35 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int ret = CMD_RET_SUCCESS; int dev = 0; - char *pstr; + char *ep; + block_dev_desc_t *blk_dev_desc; if (argc < 5) return CMD_RET_USAGE; /* command: 'write' */ if ((strcmp(argv[1], "write") == 0) && (argc == 5)) { - /* device: 'mmc' */ - if (strcmp(argv[2], "mmc") == 0) { - /* check if 'dev' is a number */ - for (pstr = argv[3]; *pstr != '\0'; pstr++) - if (!isdigit(*pstr)) { - printf("'%s' is not a number\n", - argv[3]); - return CMD_RET_USAGE; - } - dev = (int)simple_strtoul(argv[3], NULL, 10); - /* write to mmc */ - if (gpt_mmc_default(dev, argv[4])) - return CMD_RET_FAILURE; + dev = (int)simple_strtoul(argv[3], &ep, 10); + if (!ep || ep[0] != '\0') { + printf("'%s' is not a number\n", argv[3]); + return CMD_RET_USAGE; + } + blk_dev_desc = get_dev(argv[2], dev); + if (!blk_dev_desc) { + printf("%s: %s dev %d NOT available\n", + __func__, argv[2], dev); + return CMD_RET_FAILURE; + } + + puts("Writing GPT: "); + + ret = gpt_default(blk_dev_desc, argv[4]); + if (!ret) { + puts("success!\n"); + return CMD_RET_SUCCESS; + } else { + puts("error!\n"); + return CMD_RET_FAILURE; } } else { return CMD_RET_USAGE; @@ -328,7 +352,7 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt, "GUID Partition Table", - " \n" + " \n" " - GUID partition table restoration\n" " Restore GPT information on a device connected\n" " to interface\n" diff --git a/common/cmd_hash.c b/common/cmd_hash.c index 90facbbe1a..704d21ec6d 100644 --- a/common/cmd_hash.c +++ b/common/cmd_hash.c @@ -18,9 +18,9 @@ static int do_hash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *s; -#ifdef CONFIG_HASH_VERIFY int flags = HASH_FLAG_ENV; +#ifdef CONFIG_HASH_VERIFY if (argc < 4) return CMD_RET_USAGE; if (!strcmp(argv[1], "-v")) { @@ -28,8 +28,6 @@ static int do_hash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) argc--; argv++; } -#else - const int flags = HASH_FLAG_ENV; #endif /* Move forward to 'algorithm' parameter */ argc--; @@ -40,19 +38,19 @@ static int do_hash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #ifdef CONFIG_HASH_VERIFY -U_BOOT_CMD( - hash, 6, 1, do_hash, - "compute hash message digest", - "algorithm address count [[*]sum_dest]\n" - " - compute message digest [save to env var / *address]\n" - "hash -v algorithm address count [*]sum\n" - " - verify hash of memory area with env var / *address" -); +#define HARGS 6 #else +#define HARGS 5 +#endif + U_BOOT_CMD( - hash, 5, 1, do_hash, - "compute message digest", - "algorithm address count [[*]sum_dest]\n" + hash, HARGS, 1, do_hash, + "compute hash message digest", + "algorithm address count [[*]hash_dest]\n" " - compute message digest [save to env var / *address]" -); +#ifdef CONFIG_HASH_VERIFY + "\nhash -v algorithm address count [*]hash\n" + " - verify message digest of memory area to immediate value, \n" + " env var or *address" #endif +); diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 29f5181baf..7c3ad00fdf 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -66,9 +66,13 @@ */ #include +#include +#include #include +#include #include #include +#include #include #include #include @@ -79,12 +83,12 @@ DECLARE_GLOBAL_DATA_PTR; /* Display values from last command. * Memory modify remembered values are different from display memory. */ -static uchar i2c_dp_last_chip; +static uint i2c_dp_last_chip; static uint i2c_dp_last_addr; static uint i2c_dp_last_alen; static uint i2c_dp_last_length = 0x10; -static uchar i2c_mm_last_chip; +static uint i2c_mm_last_chip; static uint i2c_mm_last_addr; static uint i2c_mm_last_alen; @@ -115,6 +119,60 @@ static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; #define DISP_LINE_LEN 16 +/* + * Default for driver model is to use the chip's existing address length. + * For legacy code, this is not stored, so we need to use a suitable + * default. + */ +#ifdef CONFIG_DM_I2C +#define DEFAULT_ADDR_LEN (-1) +#else +#define DEFAULT_ADDR_LEN 1 +#endif + +#ifdef CONFIG_DM_I2C +static struct udevice *i2c_cur_bus; + +static int cmd_i2c_set_bus_num(unsigned int busnum) +{ + struct udevice *bus; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus); + if (ret) { + debug("%s: No bus %d\n", __func__, busnum); + return ret; + } + i2c_cur_bus = bus; + + return 0; +} + +static int i2c_get_cur_bus(struct udevice **busp) +{ + if (!i2c_cur_bus) { + puts("No I2C bus selected\n"); + return -ENODEV; + } + *busp = i2c_cur_bus; + + return 0; +} + +static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp) +{ + struct udevice *bus; + int ret; + + ret = i2c_get_cur_bus(&bus); + if (ret) + return ret; + + return i2c_get_chip(bus, chip_addr, 1, devp); +} + +#endif + /** * i2c_init_board() - Board-specific I2C bus init * @@ -141,7 +199,7 @@ void i2c_init_board(void) * * Returns I2C bus speed in Hz. */ -#if !defined(CONFIG_SYS_I2C) +#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C) /* * TODO: Implement architecture-specific get/set functions * Should go away, if we switched completely to new multibus support @@ -180,12 +238,12 @@ int i2c_set_bus_speed(unsigned int speed) * * Returns the address length. */ -static uint get_alen(char *arg) +static uint get_alen(char *arg, int default_len) { int j; int alen; - alen = 1; + alen = default_len; for (j = 0; j < 8; j++) { if (arg[j] == '.') { alen = arg[j+1] - '0'; @@ -196,6 +254,19 @@ static uint get_alen(char *arg) return alen; } +enum i2c_err_op { + I2C_ERR_READ, + I2C_ERR_WRITE, +}; + +static int i2c_report_err(int ret, enum i2c_err_op op) +{ + printf("Error %s the chip: %d\n", + op == I2C_ERR_READ ? "reading" : "writing", ret); + + return CMD_RET_FAILURE; +} + /** * do_i2c_read() - Handle the "i2c read" command-line command * @cmdtp: Command data struct pointer @@ -211,9 +282,14 @@ static uint get_alen(char *arg) */ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - u_char chip; - uint devaddr, alen, length; + uint chip; + uint devaddr, length; + int alen; u_char *memaddr; + int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif if (argc != 5) return CMD_RET_USAGE; @@ -228,7 +304,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv * 2 bytes long. Some day it might be 3 bytes long :-). */ devaddr = simple_strtoul(argv[2], NULL, 16); - alen = get_alen(argv[2]); + alen = get_alen(argv[2], DEFAULT_ADDR_LEN); if (alen > 3) return CMD_RET_USAGE; @@ -242,18 +318,31 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv */ memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16); - if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) { - puts ("Error reading the chip.\n"); - return 1; - } +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret && alen != -1) + ret = i2c_set_chip_offset_len(dev, alen); + if (!ret) + ret = dm_i2c_read(dev, devaddr, memaddr, length); +#else + ret = i2c_read(chip, devaddr, alen, memaddr, length); +#endif + if (ret) + return i2c_report_err(ret, I2C_ERR_READ); + return 0; } static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - u_char chip; - uint devaddr, alen, length; + uint chip; + uint devaddr, length; + int alen; u_char *memaddr; + int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif if (argc != 5) return cmd_usage(cmdtp); @@ -273,7 +362,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ * 2 bytes long. Some day it might be 3 bytes long :-). */ devaddr = simple_strtoul(argv[3], NULL, 16); - alen = get_alen(argv[3]); + alen = get_alen(argv[3], DEFAULT_ADDR_LEN); if (alen > 3) return cmd_usage(cmdtp); @@ -282,11 +371,22 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ */ length = simple_strtoul(argv[4], NULL, 16); +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret && alen != -1) + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) + return i2c_report_err(ret, I2C_ERR_WRITE); +#endif + while (length-- > 0) { - if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) { - puts("Error writing to the chip.\n"); - return 1; - } +#ifdef CONFIG_DM_I2C + ret = dm_i2c_write(dev, devaddr++, memaddr++, 1); +#else + ret = i2c_write(chip, devaddr++, alen, memaddr++, 1); +#endif + if (ret) + return i2c_report_err(ret, I2C_ERR_WRITE); /* * No write delay with FRAM devices. */ @@ -297,6 +397,38 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ return 0; } +#ifdef CONFIG_DM_I2C +static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + uint flags; + int chip; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + + chip = simple_strtoul(argv[1], NULL, 16); + ret = i2c_get_cur_bus_chip(chip, &dev); + if (ret) + return i2c_report_err(ret, I2C_ERR_READ); + + if (argc > 2) { + flags = simple_strtoul(argv[2], NULL, 16); + ret = i2c_set_chip_flags(dev, flags); + } else { + ret = i2c_get_chip_flags(dev, &flags); + if (!ret) + printf("%x\n", flags); + } + if (ret) + return i2c_report_err(ret, I2C_ERR_READ); + + return 0; +} +#endif + /** * do_i2c_md() - Handle the "i2c md" command-line command * @cmdtp: Command data struct pointer @@ -312,9 +444,14 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ */ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - u_char chip; - uint addr, alen, length; + uint chip; + uint addr, length; + int alen; int j, nbytes, linebytes; + int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif /* We use the last specified parameters, unless new ones are * entered. @@ -342,7 +479,7 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] * 2 bytes long. Some day it might be 3 bytes long :-). */ addr = simple_strtoul(argv[2], NULL, 16); - alen = get_alen(argv[2]); + alen = get_alen(argv[2], DEFAULT_ADDR_LEN); if (alen > 3) return CMD_RET_USAGE; @@ -354,6 +491,14 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] length = simple_strtoul(argv[3], NULL, 16); } +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret && alen != -1) + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) + return i2c_report_err(ret, I2C_ERR_READ); +#endif + /* * Print the lines. * @@ -367,8 +512,13 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; - if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0) - puts ("Error reading the chip.\n"); +#ifdef CONFIG_DM_I2C + ret = dm_i2c_read(dev, addr, linebuf, linebytes); +#else + ret = i2c_read(chip, addr, alen, linebuf, linebytes); +#endif + if (ret) + i2c_report_err(ret, I2C_ERR_READ); else { printf("%04x:", addr); cp = linebuf; @@ -413,11 +563,15 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - uchar chip; + uint chip; ulong addr; - uint alen; + int alen; uchar byte; int count; + int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif if ((argc < 4) || (argc > 5)) return CMD_RET_USAGE; @@ -431,10 +585,17 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); - alen = get_alen(argv[2]); + alen = get_alen(argv[2], DEFAULT_ADDR_LEN); if (alen > 3) return CMD_RET_USAGE; +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret && alen != -1) + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) + return i2c_report_err(ret, I2C_ERR_WRITE); +#endif /* * Value to write is always specified. */ @@ -449,8 +610,13 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] count = 1; while (count-- > 0) { - if (i2c_write(chip, addr++, alen, &byte, 1) != 0) - puts ("Error writing the chip.\n"); +#ifdef CONFIG_DM_I2C + ret = dm_i2c_write(dev, addr++, &byte, 1); +#else + ret = i2c_write(chip, addr++, alen, &byte, 1); +#endif + if (ret) + i2c_report_err(ret, I2C_ERR_WRITE); /* * Wait for the write to complete. The write can take * up to 10mSec (we allow a little more time). @@ -483,13 +649,17 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - uchar chip; + uint chip; ulong addr; - uint alen; + int alen; int count; uchar byte; ulong crc; ulong err; + int ret = 0; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif if (argc < 4) return CMD_RET_USAGE; @@ -503,10 +673,17 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); - alen = get_alen(argv[2]); + alen = get_alen(argv[2], DEFAULT_ADDR_LEN); if (alen > 3) return CMD_RET_USAGE; +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret && alen != -1) + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) + return i2c_report_err(ret, I2C_ERR_READ); +#endif /* * Count is always specified */ @@ -520,13 +697,18 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] crc = 0; err = 0; while (count-- > 0) { - if (i2c_read(chip, addr, alen, &byte, 1) != 0) +#ifdef CONFIG_DM_I2C + ret = dm_i2c_read(dev, addr, &byte, 1); +#else + ret = i2c_read(chip, addr, alen, &byte, 1); +#endif + if (ret) err++; crc = crc32 (crc, &byte, 1); addr++; } if (err > 0) - puts ("Error reading the chip,\n"); + i2c_report_err(ret, I2C_ERR_READ); else printf ("%08lx\n", crc); @@ -552,19 +734,21 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] static int mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) { - uchar chip; + uint chip; ulong addr; - uint alen; + int alen; ulong data; int size = 1; int nbytes; + int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif if (argc != 3) return CMD_RET_USAGE; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* got a good command to get here */ -#endif + bootretry_reset_cmd_timeout(); /* got a good command to get here */ /* * We use the last specified parameters, unless new ones are * entered. @@ -589,19 +773,32 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); - alen = get_alen(argv[2]); + alen = get_alen(argv[2], DEFAULT_ADDR_LEN); if (alen > 3) return CMD_RET_USAGE; } +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret && alen != -1) + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) + return i2c_report_err(ret, I2C_ERR_WRITE); +#endif + /* * Print the address, followed by value. Then accept input for * the next value. A non-converted value exits. */ do { printf("%08lx:", addr); - if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) - puts ("\nError reading the chip,\n"); +#ifdef CONFIG_DM_I2C + ret = dm_i2c_read(dev, addr, (uchar *)&data, size); +#else + ret = i2c_read(chip, addr, alen, (uchar *)&data, size); +#endif + if (ret) + i2c_report_err(ret, I2C_ERR_READ); else { data = cpu_to_be32(data); if (size == 1) @@ -612,7 +809,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg printf(" %08lx", data); } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0) { /* * pressed as only input, don't modify current @@ -621,9 +818,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg if (incrflag) addr += size; nbytes = size; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* good enough to not time out */ -#endif + /* good enough to not time out */ + bootretry_reset_cmd_timeout(); } #ifdef CONFIG_BOOT_RETRY_TIME else if (nbytes == -2) @@ -640,14 +836,19 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg data = be32_to_cpu(data); nbytes = endp - console_buffer; if (nbytes) { -#ifdef CONFIG_BOOT_RETRY_TIME /* * good enough to not time out */ - reset_cmd_timeout(); + bootretry_reset_cmd_timeout(); +#ifdef CONFIG_DM_I2C + ret = dm_i2c_write(dev, addr, (uchar *)&data, + size); +#else + ret = i2c_write(chip, addr, alen, + (uchar *)&data, size); #endif - if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) - puts ("Error writing the chip.\n"); + if (ret) + i2c_report_err(ret, I2C_ERR_WRITE); #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif @@ -688,6 +889,13 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv int k, skip; unsigned int bus = GET_BUS_NUM; #endif /* NOPROBES */ + int ret; +#ifdef CONFIG_DM_I2C + struct udevice *bus, *dev; + + if (i2c_get_cur_bus(&bus)) + return CMD_RET_FAILURE; +#endif if (argc == 2) addr = simple_strtol(argv[1], 0, 16); @@ -708,7 +916,12 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv if (skip) continue; #endif - if (i2c_probe(j) == 0) { +#ifdef CONFIG_DM_I2C + ret = dm_i2c_probe(bus, j, 0, &dev); +#else + ret = i2c_probe(j); +#endif + if (ret == 0) { printf(" %02X", j); found++; } @@ -744,12 +957,16 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv */ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - u_char chip; - ulong alen; + uint chip; + int alen; uint addr; uint length; u_char bytes[16]; int delay; + int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif if (argc < 3) return CMD_RET_USAGE; @@ -763,9 +980,16 @@ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); - alen = get_alen(argv[2]); + alen = get_alen(argv[2], DEFAULT_ADDR_LEN); if (alen > 3) return CMD_RET_USAGE; +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret && alen != -1) + ret = i2c_set_chip_offset_len(dev, alen); + if (ret) + return i2c_report_err(ret, I2C_ERR_WRITE); +#endif /* * Length is the number of objects, not number of bytes. @@ -785,8 +1009,13 @@ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] * Run the loop... */ while (1) { - if (i2c_read(chip, addr, alen, bytes, length) != 0) - puts ("Error reading the chip.\n"); +#ifdef CONFIG_DM_I2C + ret = dm_i2c_read(dev, addr, bytes, length); +#else + ret = i2c_read(chip, addr, alen, bytes, length); +#endif + if (ret) + i2c_report_err(ret, I2C_ERR_READ); udelay(delay); } @@ -856,7 +1085,7 @@ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { enum { unknown, EDO, SDRAM, DDR2 } type; - u_char chip; + uint chip; u_char data[128]; u_char cksum; int j; @@ -1334,8 +1563,12 @@ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_I2C_EDID) int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - u_char chip; + uint chip; struct edid1_info edid; + int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif if (argc < 2) { cmd_usage(cmdtp); @@ -1343,10 +1576,15 @@ int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } chip = simple_strtoul(argv[1], NULL, 16); - if (i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid)) != 0) { - puts("Error reading EDID content.\n"); - return 1; - } +#ifdef CONFIG_DM_I2C + ret = i2c_get_cur_bus_chip(chip, &dev); + if (!ret) + ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid)); +#else + ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid)); +#endif + if (ret) + return i2c_report_err(ret, I2C_ERR_READ); if (edid_check_info(&edid)) { puts("Content isn't valid EDID.\n"); @@ -1369,7 +1607,8 @@ int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) * Returns zero always. */ #if defined(CONFIG_SYS_I2C) -int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { int i; #ifndef CONFIG_SYS_I2C_DIRECT_BUS @@ -1427,23 +1666,41 @@ int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Returns zero on success, CMD_RET_USAGE in case of misuse and negative * on error. */ -#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) -int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \ + defined(CONFIG_DM_I2C) +static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { int ret = 0; - unsigned int bus_no; + int bus_no; - if (argc == 1) + if (argc == 1) { /* querying current setting */ - printf("Current bus is %d\n", i2c_get_bus_num()); - else { +#ifdef CONFIG_DM_I2C + struct udevice *bus; + + if (!i2c_get_cur_bus(&bus)) + bus_no = bus->seq; + else + bus_no = -1; +#else + bus_no = i2c_get_bus_num(); +#endif + printf("Current bus is %d\n", bus_no); + } else { bus_no = simple_strtoul(argv[1], NULL, 10); +#if defined(CONFIG_SYS_I2C) if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", bus_no); return -1; } +#endif printf("Setting bus to %d\n", bus_no); +#ifdef CONFIG_DM_I2C + ret = cmd_i2c_set_bus_num(bus_no); +#else ret = i2c_set_bus_num(bus_no); +#endif if (ret) printf("Failure changing bus number (%d)\n", ret); } @@ -1465,13 +1722,28 @@ static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const { int speed, ret=0; - if (argc == 1) +#ifdef CONFIG_DM_I2C + struct udevice *bus; + + if (i2c_get_cur_bus(&bus)) + return 1; +#endif + if (argc == 1) { +#ifdef CONFIG_DM_I2C + speed = i2c_get_bus_speed(bus); +#else + speed = i2c_get_bus_speed(); +#endif /* querying current speed */ - printf("Current bus speed=%d\n", i2c_get_bus_speed()); - else { + printf("Current bus speed=%d\n", speed); + } else { speed = simple_strtoul(argv[1], NULL, 10); printf("Setting bus speed to %d Hz\n", speed); +#ifdef CONFIG_DM_I2C + ret = i2c_set_bus_speed(bus, speed); +#else ret = i2c_set_bus_speed(speed); +#endif if (ret) printf("Failure changing bus speed (%d)\n", ret); } @@ -1519,7 +1791,16 @@ static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) */ static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { -#if defined(CONFIG_SYS_I2C) +#if defined(CONFIG_DM_I2C) + struct udevice *bus; + + if (i2c_get_cur_bus(&bus)) + return CMD_RET_FAILURE; + if (i2c_deblock(bus)) { + printf("Error: Not supported by the driver\n"); + return CMD_RET_FAILURE; + } +#elif defined(CONFIG_SYS_I2C) i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr); #else i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); @@ -1533,7 +1814,7 @@ static cmd_tbl_t cmd_i2c_sub[] = { #endif U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""), #if defined(CONFIG_SYS_I2C) || \ - defined(CONFIG_I2C_MULTI_BUS) + defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C) U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""), #endif /* CONFIG_I2C_MULTI_BUS */ #if defined(CONFIG_I2C_EDID) @@ -1547,6 +1828,9 @@ static cmd_tbl_t cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""), U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""), U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""), +#ifdef CONFIG_DM_I2C + U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""), +#endif U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""), #if defined(CONFIG_CMD_SDRAM) U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""), @@ -1597,7 +1881,7 @@ static char i2c_help_text[] = #endif "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" #if defined(CONFIG_SYS_I2C) || \ - defined(CONFIG_I2C_MULTI_BUS) + defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C) "i2c dev [dev] - show or set current I2C bus\n" #endif /* CONFIG_I2C_MULTI_BUS */ #if defined(CONFIG_I2C_EDID) @@ -1609,8 +1893,11 @@ static char i2c_help_text[] = "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" "i2c probe [address] - test for and show device(s) on the I2C bus\n" - "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n" + "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n" "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n" +#ifdef CONFIG_DM_I2C + "i2c flags chip [flags] - set or get chip flags\n" +#endif "i2c reset - re-init the I2C Controller\n" #if defined(CONFIG_CMD_SDRAM) "i2c sdram chip - print SDRAM configuration information\n" diff --git a/common/cmd_ide.c b/common/cmd_ide.c index c375ef2093..04a6d9b398 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -253,7 +253,7 @@ int do_diskboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* ------------------------------------------------------------------------- */ -void __ide_led(uchar led, uchar status) +__weak void ide_led(uchar led, uchar status) { #if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */ static uchar led_buffer; /* Buffer for current LED status */ @@ -269,9 +269,6 @@ void __ide_led(uchar led, uchar status) #endif } -void ide_led(uchar led, uchar status) - __attribute__ ((weak, alias("__ide_led"))); - #ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */ # define DEVICE_LED(x) 0 # define LED_IDE1 1 @@ -280,7 +277,7 @@ void ide_led(uchar led, uchar status) /* ------------------------------------------------------------------------- */ -inline void __ide_outb(int dev, int port, unsigned char val) +__weak void ide_outb(int dev, int port, unsigned char val) { debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", dev, port, val, @@ -299,10 +296,7 @@ inline void __ide_outb(int dev, int port, unsigned char val) #endif } -void ide_outb(int dev, int port, unsigned char val) - __attribute__ ((weak, alias("__ide_outb"))); - -inline unsigned char __ide_inb(int dev, int port) +__weak unsigned char ide_inb(int dev, int port) { uchar val; @@ -318,19 +312,6 @@ inline unsigned char __ide_inb(int dev, int port) return val; } -unsigned char ide_inb(int dev, int port) - __attribute__ ((weak, alias("__ide_inb"))); - -#ifdef CONFIG_TUNE_PIO -inline int __ide_set_piomode(int pio_mode) -{ - return 0; -} - -inline int ide_set_piomode(int pio_mode) - __attribute__ ((weak, alias("__ide_set_piomode"))); -#endif - void ide_init(void) { unsigned char c; @@ -471,23 +452,14 @@ block_dev_desc_t *ide_get_dev(int dev) /* ------------------------------------------------------------------------- */ -void ide_input_swap_data(int dev, ulong *sect_buf, int words) - __attribute__ ((weak, alias("__ide_input_swap_data"))); - -void ide_input_data(int dev, ulong *sect_buf, int words) - __attribute__ ((weak, alias("__ide_input_data"))); - -void ide_output_data(int dev, const ulong *sect_buf, int words) - __attribute__ ((weak, alias("__ide_output_data"))); - /* We only need to swap data if we are running on a big endian cpu. */ #if defined(__LITTLE_ENDIAN) -void __ide_input_swap_data(int dev, ulong *sect_buf, int words) +__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words) { ide_input_data(dev, sect_buf, words); } #else -void __ide_input_swap_data(int dev, ulong *sect_buf, int words) +__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words) { volatile ushort *pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); @@ -510,7 +482,7 @@ void __ide_input_swap_data(int dev, ulong *sect_buf, int words) #if defined(CONFIG_IDE_SWAP_IO) -void __ide_output_data(int dev, const ulong *sect_buf, int words) +__weak void ide_output_data(int dev, const ulong *sect_buf, int words) { ushort *dbuf; volatile ushort *pbuf; @@ -525,7 +497,7 @@ void __ide_output_data(int dev, const ulong *sect_buf, int words) } } #else /* ! CONFIG_IDE_SWAP_IO */ -void __ide_output_data(int dev, const ulong *sect_buf, int words) +__weak void ide_output_data(int dev, const ulong *sect_buf, int words) { #if defined(CONFIG_IDE_AHB) ide_write_data(dev, sect_buf, words); @@ -536,7 +508,7 @@ void __ide_output_data(int dev, const ulong *sect_buf, int words) #endif /* CONFIG_IDE_SWAP_IO */ #if defined(CONFIG_IDE_SWAP_IO) -void __ide_input_data(int dev, ulong *sect_buf, int words) +__weak void ide_input_data(int dev, ulong *sect_buf, int words) { ushort *dbuf; volatile ushort *pbuf; @@ -554,7 +526,7 @@ void __ide_input_data(int dev, ulong *sect_buf, int words) } } #else /* ! CONFIG_IDE_SWAP_IO */ -void __ide_input_data(int dev, ulong *sect_buf, int words) +__weak void ide_input_data(int dev, ulong *sect_buf, int words) { #if defined(CONFIG_IDE_AHB) ide_read_data(dev, sect_buf, words); @@ -575,14 +547,6 @@ static void ide_ident(block_dev_desc_t *dev_desc) #ifdef CONFIG_ATAPI int retries = 0; #endif - -#ifdef CONFIG_TUNE_PIO - int pio_mode; -#endif - -#if 0 - int mode, cycle_time; -#endif int device; device = dev_desc->dev; @@ -691,72 +655,6 @@ static void ide_ident(block_dev_desc_t *dev_desc) else dev_desc->removable = 0; -#ifdef CONFIG_TUNE_PIO - /* Mode 0 - 2 only, are directly determined by word 51. */ - pio_mode = iop.tPIO; - if (pio_mode > 2) { - printf("WARNING: Invalid PIO (word 51 = %d).\n", pio_mode); - /* Force it to dead slow, and hope for the best... */ - pio_mode = 0; - } - - /* Any CompactFlash Storage Card that supports PIO mode 3 or above - * shall set bit 1 of word 53 to one and support the fields contained - * in words 64 through 70. - */ - if (iop.field_valid & 0x02) { - /* - * Mode 3 and above are possible. Check in order from slow - * to fast, so we wind up with the highest mode allowed. - */ - if (iop.eide_pio_modes & 0x01) - pio_mode = 3; - if (iop.eide_pio_modes & 0x02) - pio_mode = 4; - if (ata_id_is_cfa((u16 *)&iop)) { - if ((iop.cf_advanced_caps & 0x07) == 0x01) - pio_mode = 5; - if ((iop.cf_advanced_caps & 0x07) == 0x02) - pio_mode = 6; - } - } - - /* System-specific, depends on bus speeds, etc. */ - ide_set_piomode(pio_mode); -#endif /* CONFIG_TUNE_PIO */ - -#if 0 - /* - * Drive PIO mode autoselection - */ - mode = iop.tPIO; - - printf("tPIO = 0x%02x = %d\n", mode, mode); - if (mode > 2) { /* 2 is maximum allowed tPIO value */ - mode = 2; - debug("Override tPIO -> 2\n"); - } - if (iop.field_valid & 2) { /* drive implements ATA2? */ - debug("Drive implements ATA2\n"); - if (iop.capability & 8) { /* drive supports use_iordy? */ - cycle_time = iop.eide_pio_iordy; - } else { - cycle_time = iop.eide_pio; - } - debug("cycle time = %d\n", cycle_time); - mode = 4; - if (cycle_time > 120) - mode = 3; /* 120 ns for PIO mode 4 */ - if (cycle_time > 180) - mode = 2; /* 180 ns for PIO mode 3 */ - if (cycle_time > 240) - mode = 1; /* 240 ns for PIO mode 4 */ - if (cycle_time > 383) - mode = 0; /* 383 ns for PIO mode 4 */ - } - printf("PIO mode to use: PIO %d\n", mode); -#endif /* 0 */ - #ifdef CONFIG_ATAPI if (dev_desc->if_type == IF_TYPE_ATAPI) { atapi_inquiry(dev_desc); @@ -1122,17 +1020,10 @@ int ide_device_present(int dev) * ATAPI Support */ -void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) - __attribute__ ((weak, alias("__ide_input_data_shorts"))); - -void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) - __attribute__ ((weak, alias("__ide_output_data_shorts"))); - - #if defined(CONFIG_IDE_SWAP_IO) /* since ATAPI may use commands with not 4 bytes alligned length * we have our own transfer functions, 2 bytes alligned */ -void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) +__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) { ushort *dbuf; volatile ushort *pbuf; @@ -1149,7 +1040,7 @@ void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) } } -void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) +__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) { ushort *dbuf; volatile ushort *pbuf; @@ -1167,12 +1058,12 @@ void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) } #else /* ! CONFIG_IDE_SWAP_IO */ -void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) +__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) { outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts); } -void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) +__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) { insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts); } diff --git a/common/cmd_immap.c b/common/cmd_immap.c index bdf53a4dbb..1414f9ad55 100644 --- a/common/cmd_immap.c +++ b/common/cmd_immap.c @@ -12,13 +12,13 @@ #include #include -#if defined(CONFIG_8xx) || defined(CONFIG_8260) +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) #if defined(CONFIG_8xx) #include #include #include -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #include #include #include @@ -40,7 +40,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile sysconf8xx_t *sc = &immap->im_siu_conf; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile sysconf8260_t *sc = &immap->im_siu_conf; #endif @@ -50,7 +50,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask); printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec); printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr); -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) printf ("BCR = %08x\n", sc->sc_bcr); printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n", sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl); @@ -72,7 +72,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile memctl8xx_t *memctl = &immap->im_memctl; int nbanks = 8; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile memctl8260_t *memctl = &immap->im_memctl; int nbanks = 12; #endif @@ -92,19 +92,19 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf ("MAR = %08x", memctl->memc_mar); #if defined(CONFIG_8xx) printf (" MCR = %08x\n", memctl->memc_mcr); -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) putc ('\n'); #endif printf ("MAMR = %08x MBMR = %08x", memctl->memc_mamr, memctl->memc_mbmr); #if defined(CONFIG_8xx) printf ("\nMSTAT = %04x\n", memctl->memc_mstat); -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) printf (" MCMR = %08x\n", memctl->memc_mcmr); #endif printf ("MPTPR = %04x MDR = %08x\n", memctl->memc_mptpr, memctl->memc_mdr); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) printf ("PSDMR = %08x LSDMR = %08x\n", memctl->memc_psdmr, memctl->memc_lsdmr); printf ("PURT = %02x PSRT = %02x\n", @@ -123,7 +123,7 @@ do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 int do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -139,7 +139,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile car8xx_t *car = &immap->im_clkrst; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile car8260_t *car = &immap->im_clkrst; #endif @@ -147,7 +147,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf ("SCCR = %08x\n", car->car_sccr); printf ("PLPRCR= %08x\n", car->car_plprcr); printf ("RSR = %08x\n", car->car_rsr); -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) printf ("SCCR = %08x\n", car->car_sccr); printf ("SCMR = %08x\n", car->car_scmr); printf ("RSR = %08x\n", car->car_rsr); @@ -207,7 +207,7 @@ static void binary (char *label, uint value, int nbits) #define PB_NB_ODR 16 #define PC_NBITS 12 #define PD_NBITS 13 -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #define PA_NBITS 32 #define PA_NB_ODR 32 #define PB_NBITS 28 @@ -224,7 +224,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile iop8xx_t *iop = &immap->im_ioport; volatile ushort *l, *r; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile iop8260_t *iop = &immap->im_ioport; volatile uint *l, *r; #endif @@ -240,7 +240,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) l = &iop->iop_padir; R = &immap->im_cpm.cp_pbdir; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) l = &iop->iop_pdira; R = &iop->iop_pdirb; #endif @@ -248,7 +248,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) binary ("PB_DIR", *R++, PB_NBITS); binary ("PA_PAR", *l++, PA_NBITS); binary ("PB_PAR", *R++, PB_NBITS); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) binary ("PA_SOR", *l++, PA_NBITS); binary ("PB_SOR", *R++, PB_NBITS); #endif @@ -266,7 +266,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) l = &iop->iop_pcdir; r = &iop->iop_pddir; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) l = &iop->iop_pdirc; r = &iop->iop_pdird; #endif @@ -278,7 +278,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) binary ("PC_SO ", *l++, PC_NBITS); binary (" ", 0, 0); r++; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) binary ("PC_SOR", *l++, PC_NBITS); binary ("PD_SOR", *r++, PD_NBITS); binary ("PC_ODR", *l++, PC_NBITS); @@ -436,7 +436,7 @@ static void prbrg (int n, uint val) #if defined(CONFIG_8xx) ulong clock = gd->cpu_clk; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) ulong clock = gd->arch.brg_clk; #endif @@ -489,7 +489,7 @@ do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_8xx) volatile cpm8xx_t *cp = &immap->im_cpm; volatile uint *p = &cp->cp_brgc1; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile uint *p = &immap->im_brgc1; #endif int i = 1; @@ -497,7 +497,7 @@ do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) while (i <= 4) prbrg (i++, *p++); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) p = &immap->im_brgc5; while (i <= 8) prbrg (i++, *p++); @@ -514,7 +514,7 @@ do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) volatile i2c8xx_t *i2c = &immap->im_i2c; volatile cpm8xx_t *cp = &immap->im_cpm; volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC]; -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) volatile i2c8260_t *i2c = &immap->im_i2c; volatile iic_t *iip; uint dpaddr; @@ -614,7 +614,7 @@ U_BOOT_CMD( "" ); -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 U_BOOT_CMD( icinfo, 1, 1, do_icinfo, "print Interrupt Controller registers", diff --git a/common/cmd_ini.c b/common/cmd_ini.c index 74481cbf6f..727fd1c664 100644 --- a/common/cmd_ini.c +++ b/common/cmd_ini.c @@ -6,30 +6,7 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com * All rights reserved. * - * The "inih" library is distributed under the following license, which is - * derived from and very similar to the 3-clause BSD license: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Brush Technology nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY BRUSH TECHNOLOGY ''AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BRUSH TECHNOLOGY BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause * * Go to the project home page for more info: * http://code.google.com/p/inih/ diff --git a/common/cmd_io.c b/common/cmd_io.c index eefac36f87..c59148f413 100644 --- a/common/cmd_io.c +++ b/common/cmd_io.c @@ -70,8 +70,8 @@ int do_io_iow(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /**************************************************/ U_BOOT_CMD(iod, 2, 0, do_io_iod, - "IO space display", "[.b, .w, .l] address [# of objects]"); + "IO space display", "[.b, .w, .l] address"); U_BOOT_CMD(iow, 3, 0, do_io_iow, - "IO space modify (auto-incrementing address)", - "[.b, .w, .l] address"); + "IO space modify", + "[.b, .w, .l] address value"); diff --git a/common/cmd_iotrace.c b/common/cmd_iotrace.c new file mode 100644 index 0000000000..f54276d2f5 --- /dev/null +++ b/common/cmd_iotrace.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static void do_print_stats(void) +{ + ulong start, size, offset, count; + + printf("iotrace is %sabled\n", iotrace_get_enabled() ? "en" : "dis"); + iotrace_get_buffer(&start, &size, &offset, &count); + printf("Start: %08lx\n", start); + printf("Size: %08lx\n", size); + printf("Offset: %08lx\n", offset); + printf("Output: %08lx\n", start + offset); + printf("Count: %08lx\n", count); + printf("CRC32: %08lx\n", (ulong)iotrace_get_checksum()); +} + +static int do_set_buffer(int argc, char * const argv[]) +{ + ulong addr = 0, size = 0; + + if (argc == 2) { + addr = simple_strtoul(*argv++, NULL, 16); + size = simple_strtoul(*argv++, NULL, 16); + } else if (argc != 0) { + return CMD_RET_USAGE; + } + + iotrace_set_buffer(addr, size); + + return 0; +} + +int do_iotrace(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *cmd = argc < 2 ? NULL : argv[1]; + + if (!cmd) + return cmd_usage(cmdtp); + switch (*cmd) { + case 'b': + return do_set_buffer(argc - 2, argv + 2); + case 'p': + iotrace_set_enabled(0); + break; + case 'r': + iotrace_set_enabled(1); + break; + case 's': + do_print_stats(); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + iotrace, 4, 1, do_iotrace, + "iotrace utility commands", + "stats - display iotrace stats\n" + "iotrace buffer
- set iotrace buffer\n" + "iotrace pause - pause tracing\n" + "iotrace resume - resume tracing" +); diff --git a/common/cmd_irq.c b/common/cmd_irq.c index a91d0bf1fc..02da450f67 100644 --- a/common/cmd_irq.c +++ b/common/cmd_irq.c @@ -1,7 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/common/cmd_itest.c b/common/cmd_itest.c index 10d53a063b..76af62b46e 100644 --- a/common/cmd_itest.c +++ b/common/cmd_itest.c @@ -2,7 +2,7 @@ * (C) Copyright 2003 * Tait Electronics Limited, Christchurch, New Zealand * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -63,7 +63,7 @@ static long evalexp(char *s, int w) l = simple_strtoul(s, NULL, 16); } - return (l & ((1 << (w * 8)) - 1)); + return l & ((1UL << (w * 8)) - 1); } static char * evalstr(char *s) @@ -71,6 +71,19 @@ static char * evalstr(char *s) /* if the parameter starts with a * then assume a string pointer else its a literal */ if (s[0] == '*') { return (char *)simple_strtoul(&s[1], NULL, 16); + } else if (s[0] == '$') { + int i = 2; + + if (s[1] != '{') + return NULL; + + while (s[i] != '}') { + if (s[i] == 0) + return NULL; + i++; + } + s[i] = 0; + return getenv((const char *)&s[2]); } else { return s; } diff --git a/common/cmd_led.c b/common/cmd_led.c index c48603cada..172bc30bd6 100644 --- a/common/cmd_led.c +++ b/common/cmd_led.c @@ -7,7 +7,7 @@ * (C) Copyright 2008 * Ulf Samuelsson * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/common/cmd_load.c b/common/cmd_load.c index 0ce949683e..d043e6d7bc 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_CMD_LOADB) -static ulong load_serial_ymodem(ulong offset); +static ulong load_serial_ymodem(ulong offset, int mode); #endif #if defined(CONFIG_CMD_LOADS) @@ -222,7 +222,7 @@ static int read_record(char *buf, ulong len) } /* Check for the console hangup (if any different from serial) */ - if (gd->jt[XF_getc] != getc) { + if (gd->jt->getc != getc) { if (ctrlc()) { return (-1); } @@ -462,7 +462,15 @@ static int do_load_serial_bin(cmd_tbl_t *cmdtp, int flag, int argc, offset, load_baudrate); - addr = load_serial_ymodem(offset); + addr = load_serial_ymodem(offset, xyzModem_ymodem); + + } else if (strcmp(argv[0],"loadx")==0) { + printf("## Ready for binary (xmodem) download " + "to 0x%08lX at %d bps...\n", + offset, + load_baudrate); + + addr = load_serial_ymodem(offset, xyzModem_xmodem); } else { @@ -942,7 +950,7 @@ static int getcxmodem(void) { return (getc()); return -1; } -static ulong load_serial_ymodem(ulong offset) +static ulong load_serial_ymodem(ulong offset, int mode) { int size; int err; @@ -953,7 +961,7 @@ static ulong load_serial_ymodem(ulong offset) ulong addr = 0; size = 0; - info.mode = xyzModem_ymodem; + info.mode = mode; res = xyzModem_stream_open(&info, &err); if (!res) { @@ -1055,6 +1063,14 @@ U_BOOT_CMD( " with offset 'off' and baudrate 'baud'" ); +U_BOOT_CMD( + loadx, 3, 0, do_load_serial_bin, + "load binary file over serial line (xmodem mode)", + "[ off ] [ baud ]\n" + " - load binary file over serial line" + " with offset 'off' and baudrate 'baud'" +); + U_BOOT_CMD( loady, 3, 0, do_load_serial_bin, "load binary file over serial line (ymodem mode)", diff --git a/common/cmd_log.c b/common/cmd_log.c index 8164bdf488..873ee40371 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -33,8 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; /* Local prototypes */ -static void logbuff_putc(const char c); -static void logbuff_puts(const char *s); +static void logbuff_putc(struct stdio_dev *dev, const char c); +static void logbuff_puts(struct stdio_dev *dev, const char *s); static int logbuff_printk(const char *line); static char buf[1024]; @@ -52,7 +52,7 @@ static char *lbuf; unsigned long __logbuffer_base(void) { - return CONFIG_SYS_SDRAM_BASE + gd->ram_size - LOGBUFF_LEN; + return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; } unsigned long logbuffer_base(void) __attribute__((weak, alias("__logbuffer_base"))); @@ -143,7 +143,7 @@ int drv_logbuff_init(void) return (rc == 0) ? 1 : rc; } -static void logbuff_putc(const char c) +static void logbuff_putc(struct stdio_dev *dev, const char c) { char buf[2]; buf[0] = c; @@ -151,7 +151,7 @@ static void logbuff_putc(const char c) logbuff_printk(buf); } -static void logbuff_puts(const char *s) +static void logbuff_puts(struct stdio_dev *dev, const char *s) { logbuff_printk (s); } @@ -181,6 +181,7 @@ void logbuff_log(char *msg) */ int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct stdio_dev *sdev = NULL; char *s; unsigned long i, start, size; @@ -188,7 +189,7 @@ int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Log concatenation of all arguments separated by spaces */ for (i = 2; i < argc; i++) { logbuff_printk(argv[i]); - logbuff_putc((i < argc - 1) ? ' ' : '\n'); + logbuff_putc(sdev, (i < argc - 1) ? ' ' : '\n'); } return 0; } diff --git a/common/cmd_lzmadec.c b/common/cmd_lzmadec.c new file mode 100644 index 0000000000..7b0b3fdd90 --- /dev/null +++ b/common/cmd_lzmadec.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2013 Patrice Bouchand + * lzma uncompress command in Uboot + * + * made from existing cmd_unzip.c file of Uboot + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include + +static int do_lzmadec(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long src, dst; + unsigned long src_len = ~0UL, dst_len = ~0UL; + int ret; + + switch (argc) { + case 4: + dst_len = simple_strtoul(argv[3], NULL, 16); + /* fall through */ + case 3: + src = simple_strtoul(argv[1], NULL, 16); + dst = simple_strtoul(argv[2], NULL, 16); + break; + default: + return CMD_RET_USAGE; + } + + ret = lzmaBuffToBuffDecompress(map_sysmem(dst, dst_len), &src_len, + map_sysmem(src, 0), dst_len); + + if (ret != SZ_OK) + return 1; + printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len); + setenv_hex("filesize", src_len); + + return 0; +} + +U_BOOT_CMD( + lzmadec, 4, 1, do_lzmadec, + "lzma uncompress a memory region", + "srcaddr dstaddr [dstsize]" +); diff --git a/common/cmd_md5sum.c b/common/cmd_md5sum.c index ae0f62e260..d22ace5220 100644 --- a/common/cmd_md5sum.c +++ b/common/cmd_md5sum.c @@ -11,6 +11,7 @@ #include #include #include +#include /* * Store the resulting sum to an address or variable @@ -33,7 +34,6 @@ static void store_result(const u8 *sum, const char *dest) sprintf(str_ptr, "%02x", sum[i]); str_ptr += 2; } - str_ptr = '\0'; setenv(dest, str_output); } } @@ -80,6 +80,7 @@ int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int verify = 0; int ac; char * const *av; + void *buf; if (argc < 3) return CMD_RET_USAGE; @@ -97,7 +98,9 @@ int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(*av++, NULL, 16); len = simple_strtoul(*av++, NULL, 16); - md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5); + buf = map_sysmem(addr, len); + md5_wd(buf, len, output, CHUNKSZ_MD5); + unmap_sysmem(buf); if (!verify) { printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1); @@ -136,6 +139,7 @@ static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned long addr, len; unsigned int i; u8 output[16]; + void *buf; if (argc < 3) return CMD_RET_USAGE; @@ -143,7 +147,10 @@ static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(argv[1], NULL, 16); len = simple_strtoul(argv[2], NULL, 16); - md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5); + buf = map_sysmem(addr, len); + md5_wd(buf, len, output, CHUNKSZ_MD5); + unmap_sysmem(buf); + printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1); for (i = 0; i < 16; i++) printf("%02x", output[i]); diff --git a/common/cmd_mdio.c b/common/cmd_mdio.c index 65a1f10a9f..fb13d05075 100644 --- a/common/cmd_mdio.c +++ b/common/cmd_mdio.c @@ -41,9 +41,11 @@ static int extract_range(char *input, int *plo, int *phi) return 0; } -static int mdio_write_ranges(struct mii_dev *bus, int addrlo, +static int mdio_write_ranges(struct phy_device *phydev, struct mii_dev *bus, + int addrlo, int addrhi, int devadlo, int devadhi, - int reglo, int reghi, unsigned short data) + int reglo, int reghi, unsigned short data, + int extended) { int addr, devad, reg; int err = 0; @@ -51,7 +53,12 @@ static int mdio_write_ranges(struct mii_dev *bus, int addrlo, for (addr = addrlo; addr <= addrhi; addr++) { for (devad = devadlo; devad <= devadhi; devad++) { for (reg = reglo; reg <= reghi; reg++) { - err = bus->write(bus, addr, devad, reg, data); + if (!extended) + err = bus->write(bus, addr, devad, + reg, data); + else + err = phydev->drv->writeext(phydev, + addr, devad, reg, data); if (err) goto err_out; @@ -63,9 +70,10 @@ err_out: return err; } -static int mdio_read_ranges(struct mii_dev *bus, int addrlo, +static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus, + int addrlo, int addrhi, int devadlo, int devadhi, - int reglo, int reghi) + int reglo, int reghi, int extended) { int addr, devad, reg; @@ -77,7 +85,12 @@ static int mdio_read_ranges(struct mii_dev *bus, int addrlo, for (reg = reglo; reg <= reghi; reg++) { int val; - val = bus->read(bus, addr, devad, reg); + if (!extended) + val = bus->read(bus, addr, devad, reg); + else + val = phydev->drv->readext(phydev, addr, + devad, reg); + if (val < 0) { printf("Error\n"); @@ -126,9 +139,10 @@ static int extract_reg_range(char *input, int *devadlo, int *devadhi, } static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus, + struct phy_device **phydev, int *addrlo, int *addrhi) { - struct phy_device *phydev; + struct phy_device *dev = *phydev; if ((argc < 1) || (argc > 2)) return -1; @@ -154,11 +168,11 @@ static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus, * device by the given name. If none are found, we call * extract_range() on the string, and see if it's an address range. */ - phydev = mdio_phydev_for_ethname(argv[0]); + dev = mdio_phydev_for_ethname(argv[0]); - if (phydev) { - *addrlo = *addrhi = phydev->addr; - *bus = phydev->bus; + if (dev) { + *addrlo = *addrhi = dev->addr; + *bus = dev->bus; return 0; } @@ -175,6 +189,8 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned short data; int pos = argc - 1; struct mii_dev *bus; + struct phy_device *phydev = NULL; + int extended = 0; if (argc < 2) return CMD_RET_USAGE; @@ -197,6 +213,29 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (flag & CMD_FLAG_REPEAT) op[0] = last_op[0]; + if (strlen(argv[1]) > 1) { + op[1] = argv[1][1]; + if (op[1] == 'x') { + phydev = mdio_phydev_for_ethname(argv[2]); + + if (phydev) { + addrlo = phydev->addr; + addrhi = addrlo; + bus = phydev->bus; + extended = 1; + } else { + return -1; + } + + if (!phydev->drv || + (!phydev->drv->writeext && (op[0] == 'w')) || + (!phydev->drv->readext && (op[0] == 'r'))) { + puts("PHY does not have extended functions\n"); + return -1; + } + } + } + switch (op[0]) { case 'w': if (pos > 1) @@ -210,7 +249,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) default: if (pos > 1) if (extract_phy_range(&(argv[2]), pos - 1, &bus, - &addrlo, &addrhi)) + &phydev, &addrlo, &addrhi)) return -1; break; @@ -227,13 +266,13 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) switch (op[0]) { case 'w': - mdio_write_ranges(bus, addrlo, addrhi, devadlo, devadhi, - reglo, reghi, data); + mdio_write_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi, + reglo, reghi, data, extended); break; case 'r': - mdio_read_ranges(bus, addrlo, addrhi, devadlo, devadhi, - reglo, reghi); + mdio_read_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi, + reglo, reghi, extended); break; } @@ -262,6 +301,10 @@ U_BOOT_CMD( "read PHY's register at .\n" "mdio write [.] - " "write PHY's register at .\n" + "mdio rx [.] - " + "read PHY's extended register at .\n" + "mdio wx [.] - " + "write PHY's extended register at .\n" " may be:\n" " \n" " \n" diff --git a/common/cmd_mem.c b/common/cmd_mem.c index c3aab3d4b5..bcb3ee325a 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -12,11 +12,14 @@ */ #include +#include +#include #include #ifdef CONFIG_HAS_DATAFLASH #include #endif #include +#include #include #include #include @@ -41,7 +44,7 @@ static ulong base_address = 0; /* Memory Display * * Syntax: - * md{.b, .w, .l} {addr} {len} + * md{.b, .w, .l, .q} {addr} {len} */ #define DISP_LINE_LEN 16 static int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -155,7 +158,12 @@ static int do_mem_nm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - ulong addr, writeval, count; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + u64 writeval; +#else + ulong writeval; +#endif + ulong addr, count; int size; void *buf; ulong bytes; @@ -175,7 +183,11 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Get the value to write. */ +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + writeval = simple_strtoull(argv[2], NULL, 16); +#else writeval = simple_strtoul(argv[2], NULL, 16); +#endif /* Count ? */ if (argc == 4) { @@ -188,11 +200,15 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) buf = map_sysmem(addr, bytes); while (count-- > 0) { if (size == 4) - *((ulong *)buf) = (ulong)writeval; + *((u32 *)buf) = (u32)writeval; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + *((u64 *)buf) = (u64)writeval; +#endif else if (size == 2) - *((ushort *)buf) = (ushort)writeval; + *((u16 *)buf) = (u16)writeval; else - *((u_char *)buf) = (u_char)writeval; + *((u8 *)buf) = (u8)writeval; buf += size; } unmap_sysmem(buf); @@ -200,7 +216,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #ifdef CONFIG_MX_CYCLIC -int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_mdc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i; ulong count; @@ -227,7 +243,7 @@ int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int do_mem_mwc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_mwc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i; ulong count; @@ -262,6 +278,11 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int rcode = 0; const char *type; const void *buf1, *buf2, *base; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + u64 word1, word2; +#else + ulong word1, word2; +#endif if (argc != 4) return CMD_RET_USAGE; @@ -270,7 +291,9 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ if ((size = cmd_get_data_size(argv[0], 4)) < 0) return 1; - type = size == 4 ? "word" : size == 2 ? "halfword" : "byte"; + type = size == 8 ? "double word" : + size == 4 ? "word" : + size == 2 ? "halfword" : "byte"; addr1 = simple_strtoul(argv[1], NULL, 16); addr1 += base_address; @@ -298,23 +321,33 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) base = buf1 = map_sysmem(addr1, bytes); buf2 = map_sysmem(addr2, bytes); for (ngood = 0; ngood < count; ++ngood) { - ulong word1, word2; if (size == 4) { - word1 = *(ulong *)buf1; - word2 = *(ulong *)buf2; + word1 = *(u32 *)buf1; + word2 = *(u32 *)buf2; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + } else if (size == 8) { + word1 = *(u64 *)buf1; + word2 = *(u64 *)buf2; +#endif } else if (size == 2) { - word1 = *(ushort *)buf1; - word2 = *(ushort *)buf2; + word1 = *(u16 *)buf1; + word2 = *(u16 *)buf2; } else { - word1 = *(u_char *)buf1; - word2 = *(u_char *)buf2; + word1 = *(u8 *)buf1; + word2 = *(u8 *)buf2; } if (word1 != word2) { ulong offset = buf1 - base; - +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + printf("%s at 0x%p (%#0*"PRIx64") != %s at 0x%p (%#0*" + PRIx64 ")\n", + type, (void *)(addr1 + offset), size, word1, + type, (void *)(addr2 + offset), size, word2); +#else printf("%s at 0x%08lx (%#0*lx) != %s at 0x%08lx (%#0*lx)\n", type, (ulong)(addr1 + offset), size, word1, type, (ulong)(addr2 + offset), size, word2); +#endif rcode = 1; break; } @@ -433,11 +466,15 @@ static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) src = map_sysmem(addr, bytes); while (count-- > 0) { if (size == 4) - *((ulong *)buf) = *((ulong *)src); + *((u32 *)buf) = *((u32 *)src); +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + *((u64 *)buf) = *((u64 *)src); +#endif else if (size == 2) - *((ushort *)buf) = *((ushort *)src); + *((u16 *)buf) = *((u16 *)src); else - *((u_char *)buf) = *((u_char *)src); + *((u8 *)buf) = *((u8 *)src); src += size; buf += size; @@ -445,6 +482,9 @@ static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((count % (64 << 10)) == 0) WATCHDOG_RESET(); } + unmap_sysmem(buf); + unmap_sysmem(src); + return 0; } @@ -467,9 +507,12 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, { ulong addr, length, i, bytes; int size; - volatile uint *longp; - volatile ushort *shortp; - volatile u_char *cp; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + volatile u64 *llp; +#endif + volatile u32 *longp; + volatile u16 *shortp; + volatile u8 *cp; const void *buf; if (argc < 3) @@ -497,24 +540,41 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, * If we have only one object, just run infinite loops. */ if (length == 1) { +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + if (size == 8) { + llp = (u64 *)buf; + for (;;) + i = *llp; + } +#endif if (size == 4) { - longp = (uint *)buf; + longp = (u32 *)buf; for (;;) i = *longp; } if (size == 2) { - shortp = (ushort *)buf; + shortp = (u16 *)buf; for (;;) i = *shortp; } - cp = (u_char *)buf; + cp = (u8 *)buf; for (;;) i = *cp; } +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + if (size == 8) { + for (;;) { + llp = (u64 *)buf; + i = length; + while (i-- > 0) + *llp++; + } + } +#endif if (size == 4) { for (;;) { - longp = (uint *)buf; + longp = (u32 *)buf; i = length; while (i-- > 0) *longp++; @@ -522,14 +582,14 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, } if (size == 2) { for (;;) { - shortp = (ushort *)buf; + shortp = (u16 *)buf; i = length; while (i-- > 0) *shortp++; } } for (;;) { - cp = (u_char *)buf; + cp = (u8 *)buf; i = length; while (i-- > 0) *cp++; @@ -540,13 +600,20 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, } #ifdef CONFIG_LOOPW -int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_loopw(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { - ulong addr, length, i, data, bytes; + ulong addr, length, i, bytes; int size; - volatile uint *longp; - volatile ushort *shortp; - volatile u_char *cp; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + volatile u64 *llp; + u64 data; +#else + ulong data; +#endif + volatile u32 *longp; + volatile u16 *shortp; + volatile u8 *cp; void *buf; if (argc < 4) @@ -568,7 +635,11 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) length = simple_strtoul(argv[2], NULL, 16); /* data to write */ +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + data = simple_strtoull(argv[3], NULL, 16); +#else data = simple_strtoul(argv[3], NULL, 16); +#endif bytes = size * length; buf = map_sysmem(addr, bytes); @@ -577,24 +648,41 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * If we have only one object, just run infinite loops. */ if (length == 1) { +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + if (size == 8) { + llp = (u64 *)buf; + for (;;) + *llp = data; + } +#endif if (size == 4) { - longp = (uint *)buf; + longp = (u32 *)buf; for (;;) *longp = data; - } + } if (size == 2) { - shortp = (ushort *)buf; + shortp = (u16 *)buf; for (;;) *shortp = data; } - cp = (u_char *)buf; + cp = (u8 *)buf; for (;;) *cp = data; } +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + if (size == 8) { + for (;;) { + llp = (u64 *)buf; + i = length; + while (i-- > 0) + *llp++ = data; + } + } +#endif if (size == 4) { for (;;) { - longp = (uint *)buf; + longp = (u32 *)buf; i = length; while (i-- > 0) *longp++ = data; @@ -602,14 +690,14 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (size == 2) { for (;;) { - shortp = (ushort *)buf; + shortp = (u16 *)buf; i = length; while (i-- > 0) *shortp++ = data; } } for (;;) { - cp = (u_char *)buf; + cp = (u8 *)buf; i = length; while (i-- > 0) *cp++ = data; @@ -746,7 +834,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != pattern) { printf("\nFAILURE: Address bit stuck high @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx\n", - start_addr + offset, pattern, temp); + start_addr + offset*sizeof(vu_long), + pattern, temp); errs++; if (ctrlc()) return -1; @@ -767,7 +856,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, printf("\nFAILURE: Address bit stuck low or" " shorted @ 0x%.8lx: expected 0x%.8lx," " actual 0x%.8lx\n", - start_addr + offset, pattern, temp); + start_addr + offset*sizeof(vu_long), + pattern, temp); errs++; if (ctrlc()) return -1; @@ -807,7 +897,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != pattern) { printf("\nFAILURE (read/write) @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx)\n", - start_addr + offset, pattern, temp); + start_addr + offset*sizeof(vu_long), + pattern, temp); errs++; if (ctrlc()) return -1; @@ -827,7 +918,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, if (temp != anti_pattern) { printf("\nFAILURE (read/write): @ 0x%.8lx:" " expected 0x%.8lx, actual 0x%.8lx)\n", - start_addr + offset, anti_pattern, temp); + start_addr + offset*sizeof(vu_long), + anti_pattern, temp); errs++; if (ctrlc()) return -1; @@ -885,7 +977,7 @@ static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr, printf("\nMem error @ 0x%08X: " "found %08lX, expected %08lX\n", - (uint)(uintptr_t)(start_addr + offset), + (uint)(uintptr_t)(start_addr + offset*sizeof(vu_long)), readback, val); errs++; if (ctrlc()) @@ -994,22 +1086,25 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, /* Modify memory. * * Syntax: - * mm{.b, .w, .l} {addr} - * nm{.b, .w, .l} {addr} + * mm{.b, .w, .l, .q} {addr} + * nm{.b, .w, .l, .q} {addr} */ static int mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) { - ulong addr, i; + ulong addr; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + u64 i; +#else + ulong i; +#endif int nbytes, size; void *ptr = NULL; if (argc != 2) return CMD_RET_USAGE; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* got a good command to get here */ -#endif + bootretry_reset_cmd_timeout(); /* got a good command to get here */ /* We use the last specified parameters, unless new ones are * entered. */ @@ -1050,13 +1145,17 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) ptr = map_sysmem(addr, size); printf("%08lx:", addr); if (size == 4) - printf(" %08x", *((uint *)ptr)); + printf(" %08x", *((u32 *)ptr)); +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + printf(" %016" PRIx64, *((u64 *)ptr)); +#endif else if (size == 2) - printf(" %04x", *((ushort *)ptr)); + printf(" %04x", *((u16 *)ptr)); else - printf(" %02x", *((u_char *)ptr)); + printf(" %02x", *((u8 *)ptr)); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { /* pressed as only input, don't modify current * location and move to next. "-" pressed will go back. @@ -1064,9 +1163,8 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) if (incrflag) addr += nbytes ? -size : size; nbytes = 1; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* good enough to not time out */ -#endif + /* good enough to not time out */ + bootretry_reset_cmd_timeout(); } #ifdef CONFIG_BOOT_RETRY_TIME else if (nbytes == -2) { @@ -1075,20 +1173,26 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) #endif else { char *endp; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + i = simple_strtoull(console_buffer, &endp, 16); +#else i = simple_strtoul(console_buffer, &endp, 16); +#endif nbytes = endp - console_buffer; if (nbytes) { -#ifdef CONFIG_BOOT_RETRY_TIME /* good enough to not time out */ - reset_cmd_timeout(); -#endif + bootretry_reset_cmd_timeout(); if (size == 4) - *((uint *)ptr) = i; + *((u32 *)ptr) = i; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + *((u64 *)ptr) = i; +#endif else if (size == 2) - *((ushort *)ptr) = i; + *((u16 *)ptr) = i; else - *((u_char *)ptr) = i; + *((u8 *)ptr) = i; if (incrflag) addr += size; } @@ -1132,39 +1236,63 @@ static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( md, 3, 1, do_mem_md, "memory display", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address [# of objects]" +#else "[.b, .w, .l] address [# of objects]" +#endif ); U_BOOT_CMD( mm, 2, 1, do_mem_mm, "memory modify (auto-incrementing address)", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address" +#else "[.b, .w, .l] address" +#endif ); U_BOOT_CMD( nm, 2, 1, do_mem_nm, "memory modify (constant address)", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address" +#else "[.b, .w, .l] address" +#endif ); U_BOOT_CMD( mw, 4, 1, do_mem_mw, "memory write (fill)", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address value [count]" +#else "[.b, .w, .l] address value [count]" +#endif ); U_BOOT_CMD( cp, 4, 1, do_mem_cp, "memory copy", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] source target count" +#else "[.b, .w, .l] source target count" +#endif ); U_BOOT_CMD( cmp, 4, 1, do_mem_cmp, "memory compare", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] addr1 addr2 count" +#else "[.b, .w, .l] addr1 addr2 count" +#endif ); #ifdef CONFIG_CMD_CRC32 @@ -1216,14 +1344,22 @@ U_BOOT_CMD( U_BOOT_CMD( loop, 3, 1, do_mem_loop, "infinite loop on address range", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address number_of_objects" +#else "[.b, .w, .l] address number_of_objects" +#endif ); #ifdef CONFIG_LOOPW U_BOOT_CMD( loopw, 4, 1, do_mem_loopw, "infinite write loop on address range", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address number_of_objects data_to_write" +#else "[.b, .w, .l] address number_of_objects data_to_write" +#endif ); #endif /* CONFIG_LOOPW */ @@ -1239,13 +1375,21 @@ U_BOOT_CMD( U_BOOT_CMD( mdc, 4, 1, do_mem_mdc, "memory display cyclic", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address count delay(ms)" +#else "[.b, .w, .l] address count delay(ms)" +#endif ); U_BOOT_CMD( mwc, 4, 1, do_mem_mwc, "memory write cyclic", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address value delay(ms)" +#else "[.b, .w, .l] address value delay(ms)" +#endif ); #endif /* CONFIG_MX_CYCLIC */ diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c index d735c9e59b..e8e8e3c0de 100644 --- a/common/cmd_mfsl.c +++ b/common/cmd_mfsl.c @@ -1,7 +1,7 @@ -ve received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * who contributed to this - * project. +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/common/cmd_mii.c b/common/cmd_mii.c index d3dd6b1c9e..7c4a57aa56 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -78,9 +78,9 @@ static const MII_field_desc_t reg_3_desc_tbl[] = { static const MII_field_desc_t reg_4_desc_tbl[] = { { 15, 15, 0x01, "next page able" }, - { 14, 14, 0x01, "reserved" }, + { 14, 14, 0x01, "(reserved)" }, { 13, 13, 0x01, "remote fault" }, - { 12, 12, 0x01, "reserved" }, + { 12, 12, 0x01, "(reserved)" }, { 11, 11, 0x01, "asymmetric pause" }, { 10, 10, 0x01, "pause enable" }, { 9, 9, 0x01, "100BASE-T4 able" }, @@ -160,10 +160,10 @@ static void dump_reg( mask_in_place = pdesc->mask << pdesc->lo; - printf(" (%04hx:%04hx) %u.", - mask_in_place, - regval & mask_in_place, - prd->regno); + printf(" (%04hx:%04x) %u.", + mask_in_place, + regval & mask_in_place, + prd->regno); if (special_field(prd->regno, pdesc, regval)) { } diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index c9c1a19791..f9378de44a 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -11,7 +11,7 @@ static int curr_device = -1; #ifndef CONFIG_GENERIC_MMC -int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_mmc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int dev; @@ -71,15 +71,11 @@ U_BOOT_CMD( ); #else /* !CONFIG_GENERIC_MMC */ -enum mmc_state { - MMC_INVALID, - MMC_READ, - MMC_WRITE, - MMC_ERASE, -}; static void print_mmcinfo(struct mmc *mmc) { - printf("Device: %s\n", mmc->name); + int i; + + printf("Device: %s\n", mmc->cfg->name); printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24); printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff); printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff, @@ -96,7 +92,65 @@ static void print_mmcinfo(struct mmc *mmc) puts("Capacity: "); print_size(mmc->capacity, "\n"); - printf("Bus Width: %d-bit\n", mmc->bus_width); + printf("Bus Width: %d-bit%s\n", mmc->bus_width, + mmc->ddr_mode ? " DDR" : ""); + + puts("Erase Group Size: "); + print_size(((u64)mmc->erase_grp_size) << 9, "\n"); + + if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) { + bool has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0; + bool usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR); + + puts("HC WP Group Size: "); + print_size(((u64)mmc->hc_wp_grp_size) << 9, "\n"); + + puts("User Capacity: "); + print_size(mmc->capacity_user, usr_enh ? " ENH" : ""); + if (mmc->wr_rel_set & EXT_CSD_WR_DATA_REL_USR) + puts(" WRREL\n"); + else + putc('\n'); + if (usr_enh) { + puts("User Enhanced Start: "); + print_size(mmc->enh_user_start, "\n"); + puts("User Enhanced Size: "); + print_size(mmc->enh_user_size, "\n"); + } + puts("Boot Capacity: "); + print_size(mmc->capacity_boot, has_enh ? " ENH\n" : "\n"); + puts("RPMB Capacity: "); + print_size(mmc->capacity_rpmb, has_enh ? " ENH\n" : "\n"); + + for (i = 0; i < ARRAY_SIZE(mmc->capacity_gp); i++) { + bool is_enh = has_enh && + (mmc->part_attr & EXT_CSD_ENH_GP(i)); + if (mmc->capacity_gp[i]) { + printf("GP%i Capacity: ", i+1); + print_size(mmc->capacity_gp[i], + is_enh ? " ENH" : ""); + if (mmc->wr_rel_set & EXT_CSD_WR_DATA_REL_GP(i)) + puts(" WRREL\n"); + else + putc('\n'); + } + } + } +} + +static struct mmc *init_mmc_device(int dev, bool force_init) +{ + struct mmc *mmc; + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return NULL; + } + if (force_init) + mmc->has_init = 0; + if (mmc_init(mmc)) + return NULL; + return mmc; } static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -112,315 +166,817 @@ static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } } - mmc = find_mmc_device(curr_device); + mmc = init_mmc_device(curr_device, false); + if (!mmc) + return CMD_RET_FAILURE; - if (mmc) { - mmc_init(mmc); + print_mmcinfo(mmc); + return CMD_RET_SUCCESS; +} - print_mmcinfo(mmc); - return CMD_RET_SUCCESS; - } else { - printf("no mmc device at slot %x\n", curr_device); +#ifdef CONFIG_SUPPORT_EMMC_RPMB +static int confirm_key_prog(void) +{ + puts("Warning: Programming authentication key can be done only once !\n" + " Use this command only if you are sure of what you are doing,\n" + "Really perform the key programming? "); + if (confirm_yesno()) + return 1; + + puts("Authentication key programming aborted\n"); + return 0; +} + +static int do_mmcrpmb_key(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + void *key_addr; + struct mmc *mmc = find_mmc_device(curr_device); + + if (argc != 2) + return CMD_RET_USAGE; + + key_addr = (void *)simple_strtoul(argv[1], NULL, 16); + if (!confirm_key_prog()) + return CMD_RET_FAILURE; + if (mmc_rpmb_set_key(mmc, key_addr)) { + printf("ERROR - Key already programmed ?\n"); return CMD_RET_FAILURE; } + return CMD_RET_SUCCESS; } -U_BOOT_CMD( - mmcinfo, 1, 0, do_mmcinfo, - "display MMC info", - "- display info of the current MMC device" -); +static int do_mmcrpmb_read(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + u16 blk, cnt; + void *addr; + int n; + void *key_addr = NULL; + struct mmc *mmc = find_mmc_device(curr_device); -#ifdef CONFIG_SUPPORT_EMMC_BOOT -static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) + if (argc < 4) + return CMD_RET_USAGE; + + addr = (void *)simple_strtoul(argv[1], NULL, 16); + blk = simple_strtoul(argv[2], NULL, 16); + cnt = simple_strtoul(argv[3], NULL, 16); + + if (argc == 5) + key_addr = (void *)simple_strtoul(argv[4], NULL, 16); + + printf("\nMMC RPMB read: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); + n = mmc_rpmb_read(mmc, addr, blk, cnt, key_addr); + + printf("%d RPMB blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + if (n != cnt) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; +} + +static int do_mmcrpmb_write(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) { - int err; - err = mmc_boot_part_access(mmc, ack, part_num, access); + u16 blk, cnt; + void *addr; + int n; + void *key_addr; + struct mmc *mmc = find_mmc_device(curr_device); - if ((err == 0) && (access != 0)) { - printf("Notice!\n"); + if (argc != 5) + return CMD_RET_USAGE; - printf("You must close EMMC boot Partition after all images are written\n"); - printf("EMMC boot partition has continuity at image writing time.\n"); - printf("So, do not close the boot partition before all images are written.\n"); - return CMD_RET_SUCCESS; - } else if ((err == 0) && (access == 0)) + addr = (void *)simple_strtoul(argv[1], NULL, 16); + blk = simple_strtoul(argv[2], NULL, 16); + cnt = simple_strtoul(argv[3], NULL, 16); + key_addr = (void *)simple_strtoul(argv[4], NULL, 16); + + printf("\nMMC RPMB write: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); + n = mmc_rpmb_write(mmc, addr, blk, cnt, key_addr); + + printf("%d RPMB blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + if (n != cnt) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; +} + +static int do_mmcrpmb_counter(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + unsigned long counter; + struct mmc *mmc = find_mmc_device(curr_device); + + if (mmc_rpmb_get_counter(mmc, &counter)) + return CMD_RET_FAILURE; + printf("RPMB Write counter= %lx\n", counter); + return CMD_RET_SUCCESS; +} + +static cmd_tbl_t cmd_rpmb[] = { + U_BOOT_CMD_MKENT(key, 2, 0, do_mmcrpmb_key, "", ""), + U_BOOT_CMD_MKENT(read, 5, 1, do_mmcrpmb_read, "", ""), + U_BOOT_CMD_MKENT(write, 5, 0, do_mmcrpmb_write, "", ""), + U_BOOT_CMD_MKENT(counter, 1, 1, do_mmcrpmb_counter, "", ""), +}; + +static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + cmd_tbl_t *cp; + struct mmc *mmc; + char original_part; + int ret; + + cp = find_cmd_tbl(argv[1], cmd_rpmb, ARRAY_SIZE(cmd_rpmb)); + + /* Drop the rpmb subcommand */ + argc--; + argv++; + + if (cp == NULL || argc > cp->maxargs) + return CMD_RET_USAGE; + if (flag == CMD_FLAG_REPEAT && !cp->repeatable) return CMD_RET_SUCCESS; - else if ((err != 0) && (access != 0)) { - printf("EMMC boot partition-%d OPEN Failed.\n", part_num); + + mmc = init_mmc_device(curr_device, false); + if (!mmc) return CMD_RET_FAILURE; - } else { - printf("EMMC boot partition-%d CLOSE Failed.\n", part_num); + + if (!(mmc->version & MMC_VERSION_MMC)) { + printf("It is not a EMMC device\n"); + return CMD_RET_FAILURE; + } + if (mmc->version < MMC_VERSION_4_41) { + printf("RPMB not supported before version 4.41\n"); return CMD_RET_FAILURE; } + /* Switch to the RPMB partition */ + original_part = mmc->part_num; + if (mmc->part_num != MMC_PART_RPMB) { + if (mmc_switch_part(curr_device, MMC_PART_RPMB) != 0) + return CMD_RET_FAILURE; + mmc->part_num = MMC_PART_RPMB; + } + ret = cp->cmd(cmdtp, flag, argc, argv); + + /* Return to original partition */ + if (mmc->part_num != original_part) { + if (mmc_switch_part(curr_device, original_part) != 0) + return CMD_RET_FAILURE; + mmc->part_num = original_part; + } + return ret; } #endif -static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mmc_read(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) { - enum mmc_state state; + struct mmc *mmc; + u32 blk, cnt, n; + void *addr; - if (argc < 2) + if (argc != 4) return CMD_RET_USAGE; - if (curr_device < 0) { - if (get_mmc_num() > 0) - curr_device = 0; - else { - puts("No MMC device available\n"); - return CMD_RET_FAILURE; - } + addr = (void *)simple_strtoul(argv[1], NULL, 16); + blk = simple_strtoul(argv[2], NULL, 16); + cnt = simple_strtoul(argv[3], NULL, 16); + + mmc = init_mmc_device(curr_device, false); + if (!mmc) + return CMD_RET_FAILURE; + + printf("\nMMC read: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); + + n = mmc->block_dev.block_read(curr_device, blk, cnt, addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); /* FIXME */ + printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + + return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} + +static int do_mmc_write(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + u32 blk, cnt, n; + void *addr; + + if (argc != 4) + return CMD_RET_USAGE; + + addr = (void *)simple_strtoul(argv[1], NULL, 16); + blk = simple_strtoul(argv[2], NULL, 16); + cnt = simple_strtoul(argv[3], NULL, 16); + + mmc = init_mmc_device(curr_device, false); + if (!mmc) + return CMD_RET_FAILURE; + + printf("\nMMC write: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); + + if (mmc_getwp(mmc) == 1) { + printf("Error: card is write protected!\n"); + return CMD_RET_FAILURE; } + n = mmc->block_dev.block_write(curr_device, blk, cnt, addr); + printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR"); - if (strcmp(argv[1], "rescan") == 0) { - struct mmc *mmc; + return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} - if (argc != 2) - return CMD_RET_USAGE; +static int do_mmc_erase(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + u32 blk, cnt, n; - mmc = find_mmc_device(curr_device); - if (!mmc) { - printf("no mmc device at slot %x\n", curr_device); - return CMD_RET_FAILURE; - } + if (argc != 3) + return CMD_RET_USAGE; - mmc->has_init = 0; + blk = simple_strtoul(argv[1], NULL, 16); + cnt = simple_strtoul(argv[2], NULL, 16); - if (mmc_init(mmc)) - return CMD_RET_FAILURE; - else - return CMD_RET_SUCCESS; - } else if (strncmp(argv[1], "part", 4) == 0) { - block_dev_desc_t *mmc_dev; - struct mmc *mmc; + mmc = init_mmc_device(curr_device, false); + if (!mmc) + return CMD_RET_FAILURE; - if (argc != 2) - return CMD_RET_USAGE; + printf("\nMMC erase: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); - mmc = find_mmc_device(curr_device); - if (!mmc) { - printf("no mmc device at slot %x\n", curr_device); - return CMD_RET_FAILURE; - } - mmc_init(mmc); - mmc_dev = mmc_get_dev(curr_device); - if (mmc_dev != NULL && - mmc_dev->type != DEV_TYPE_UNKNOWN) { - print_part(mmc_dev); - return CMD_RET_SUCCESS; - } + if (mmc_getwp(mmc) == 1) { + printf("Error: card is write protected!\n"); + return CMD_RET_FAILURE; + } + n = mmc->block_dev.block_erase(curr_device, blk, cnt); + printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR"); - puts("get mmc type error!\n"); + return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} + +static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + + mmc = init_mmc_device(curr_device, true); + if (!mmc) return CMD_RET_FAILURE; - } else if (strcmp(argv[1], "list") == 0) { - if (argc != 2) - return CMD_RET_USAGE; - print_mmc_devices('\n'); + + return CMD_RET_SUCCESS; +} + +static int do_mmc_part(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + block_dev_desc_t *mmc_dev; + struct mmc *mmc; + + mmc = init_mmc_device(curr_device, false); + if (!mmc) + return CMD_RET_FAILURE; + + mmc_dev = mmc_get_dev(curr_device); + if (mmc_dev != NULL && mmc_dev->type != DEV_TYPE_UNKNOWN) { + print_part(mmc_dev); return CMD_RET_SUCCESS; - } else if (strcmp(argv[1], "dev") == 0) { - int dev, part = -1; - struct mmc *mmc; - - if (argc == 2) - dev = curr_device; - else if (argc == 3) - dev = simple_strtoul(argv[2], NULL, 10); - else if (argc == 4) { - dev = (int)simple_strtoul(argv[2], NULL, 10); - part = (int)simple_strtoul(argv[3], NULL, 10); - if (part > PART_ACCESS_MASK) { - printf("#part_num shouldn't be larger" - " than %d\n", PART_ACCESS_MASK); - return CMD_RET_FAILURE; - } - } else - return CMD_RET_USAGE; + } - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); + puts("get mmc type error!\n"); + return CMD_RET_FAILURE; +} + +static int do_mmc_dev(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev, part = 0, ret; + struct mmc *mmc; + + if (argc == 1) { + dev = curr_device; + } else if (argc == 2) { + dev = simple_strtoul(argv[1], NULL, 10); + } else if (argc == 3) { + dev = (int)simple_strtoul(argv[1], NULL, 10); + part = (int)simple_strtoul(argv[2], NULL, 10); + if (part > PART_ACCESS_MASK) { + printf("#part_num shouldn't be larger than %d\n", + PART_ACCESS_MASK); return CMD_RET_FAILURE; } + } else { + return CMD_RET_USAGE; + } - mmc_init(mmc); - if (part != -1) { - int ret; - if (mmc->part_config == MMCPART_NOAVAILABLE) { - printf("Card doesn't support part_switch\n"); - return CMD_RET_FAILURE; - } + mmc = init_mmc_device(dev, true); + if (!mmc) + return CMD_RET_FAILURE; - if (part != mmc->part_num) { - ret = mmc_switch_part(dev, part); - if (!ret) - mmc->part_num = part; + ret = mmc_select_hwpart(dev, part); + printf("switch to partitions #%d, %s\n", + part, (!ret) ? "OK" : "ERROR"); + if (ret) + return 1; - printf("switch to partions #%d, %s\n", - part, (!ret) ? "OK" : "ERROR"); - } - } - curr_device = dev; - if (mmc->part_config == MMCPART_NOAVAILABLE) - printf("mmc%d is current device\n", curr_device); - else - printf("mmc%d(part %d) is current device\n", - curr_device, mmc->part_num); + curr_device = dev; + if (mmc->part_config == MMCPART_NOAVAILABLE) + printf("mmc%d is current device\n", curr_device); + else + printf("mmc%d(part %d) is current device\n", + curr_device, mmc->part_num); - return CMD_RET_SUCCESS; -#ifdef CONFIG_SUPPORT_EMMC_BOOT - } else if ((strcmp(argv[1], "open") == 0) || - (strcmp(argv[1], "close") == 0)) { - int dev; - struct mmc *mmc; - u8 part_num, access = 0; - - if (argc == 4) { - dev = simple_strtoul(argv[2], NULL, 10); - part_num = simple_strtoul(argv[3], NULL, 10); + return CMD_RET_SUCCESS; +} + +static int do_mmc_list(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + print_mmc_devices('\n'); + return CMD_RET_SUCCESS; +} + +static int parse_hwpart_user(struct mmc_hwpart_conf *pconf, + int argc, char * const argv[]) +{ + int i = 0; + + memset(&pconf->user, 0, sizeof(pconf->user)); + + while (i < argc) { + if (!strcmp(argv[i], "enh")) { + if (i + 2 >= argc) + return -1; + pconf->user.enh_start = + simple_strtoul(argv[i+1], NULL, 10); + pconf->user.enh_size = + simple_strtoul(argv[i+2], NULL, 10); + i += 3; + } else if (!strcmp(argv[i], "wrrel")) { + if (i + 1 >= argc) + return -1; + pconf->user.wr_rel_change = 1; + if (!strcmp(argv[i+1], "on")) + pconf->user.wr_rel_set = 1; + else if (!strcmp(argv[i+1], "off")) + pconf->user.wr_rel_set = 0; + else + return -1; + i += 2; } else { - return CMD_RET_USAGE; + break; } + } + return i; +} - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return CMD_RET_FAILURE; +static int parse_hwpart_gp(struct mmc_hwpart_conf *pconf, int pidx, + int argc, char * const argv[]) +{ + int i; + + memset(&pconf->gp_part[pidx], 0, sizeof(pconf->gp_part[pidx])); + + if (1 >= argc) + return -1; + pconf->gp_part[pidx].size = simple_strtoul(argv[0], NULL, 10); + + i = 1; + while (i < argc) { + if (!strcmp(argv[i], "enh")) { + pconf->gp_part[pidx].enhanced = 1; + i += 1; + } else if (!strcmp(argv[i], "wrrel")) { + if (i + 1 >= argc) + return -1; + pconf->gp_part[pidx].wr_rel_change = 1; + if (!strcmp(argv[i+1], "on")) + pconf->gp_part[pidx].wr_rel_set = 1; + else if (!strcmp(argv[i+1], "off")) + pconf->gp_part[pidx].wr_rel_set = 0; + else + return -1; + i += 2; + } else { + break; } + } + return i; +} - if (IS_SD(mmc)) { - printf("SD device cannot be opened/closed\n"); - return CMD_RET_FAILURE; +static int do_mmc_hwpartition(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + struct mmc_hwpart_conf pconf = { }; + enum mmc_hwpart_conf_mode mode = MMC_HWPART_CONF_CHECK; + int i, r, pidx; + + mmc = init_mmc_device(curr_device, false); + if (!mmc) + return CMD_RET_FAILURE; + + if (argc < 1) + return CMD_RET_USAGE; + i = 1; + while (i < argc) { + if (!strcmp(argv[i], "user")) { + i++; + r = parse_hwpart_user(&pconf, argc-i, &argv[i]); + if (r < 0) + return CMD_RET_USAGE; + i += r; + } else if (!strncmp(argv[i], "gp", 2) && + strlen(argv[i]) == 3 && + argv[i][2] >= '1' && argv[i][2] <= '4') { + pidx = argv[i][2] - '1'; + i++; + r = parse_hwpart_gp(&pconf, pidx, argc-i, &argv[i]); + if (r < 0) + return CMD_RET_USAGE; + i += r; + } else if (!strcmp(argv[i], "check")) { + mode = MMC_HWPART_CONF_CHECK; + i++; + } else if (!strcmp(argv[i], "set")) { + mode = MMC_HWPART_CONF_SET; + i++; + } else if (!strcmp(argv[i], "complete")) { + mode = MMC_HWPART_CONF_COMPLETE; + i++; + } else { + return CMD_RET_USAGE; } + } - if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) { - printf("Invalid boot partition number:\n"); - printf("Boot partition number cannot be <= 0\n"); - printf("EMMC44 supports only 2 boot partitions\n"); - return CMD_RET_FAILURE; + puts("Partition configuration:\n"); + if (pconf.user.enh_size) { + puts("\tUser Enhanced Start: "); + print_size(((u64)pconf.user.enh_start) << 9, "\n"); + puts("\tUser Enhanced Size: "); + print_size(((u64)pconf.user.enh_size) << 9, "\n"); + } else { + puts("\tNo enhanced user data area\n"); + } + if (pconf.user.wr_rel_change) + printf("\tUser partition write reliability: %s\n", + pconf.user.wr_rel_set ? "on" : "off"); + for (pidx = 0; pidx < 4; pidx++) { + if (pconf.gp_part[pidx].size) { + printf("\tGP%i Capacity: ", pidx+1); + print_size(((u64)pconf.gp_part[pidx].size) << 9, + pconf.gp_part[pidx].enhanced ? + " ENH\n" : "\n"); + } else { + printf("\tNo GP%i partition\n", pidx+1); } + if (pconf.gp_part[pidx].wr_rel_change) + printf("\tGP%i write reliability: %s\n", pidx+1, + pconf.gp_part[pidx].wr_rel_set ? "on" : "off"); + } - if (strcmp(argv[1], "open") == 0) - access = part_num; /* enable R/W access to boot part*/ - else - access = 0; /* No access to boot partition */ + if (!mmc_hwpart_config(mmc, &pconf, mode)) { + if (mode == MMC_HWPART_CONF_COMPLETE) + puts("Partitioning successful, power-cycle to make effective\n"); + return CMD_RET_SUCCESS; + } else { + puts("Failed!\n"); + return CMD_RET_FAILURE; + } +} - /* acknowledge to be sent during boot operation */ - return boot_part_access(mmc, 1, part_num, access); +#ifdef CONFIG_SUPPORT_EMMC_BOOT +static int do_mmc_bootbus(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev; + struct mmc *mmc; + u8 width, reset, mode; + int ret; + char *end; - } else if (strcmp(argv[1], "bootpart") == 0) { - int dev; + if (argc != 5) + return CMD_RET_USAGE; - if (argc != 5) - return CMD_RET_USAGE; + dev = simple_strtoul(argv[1], &end, 10); + if (dev < 0 || dev >= get_mmc_dev_count() || *end != '\0') { + printf("Invalid mmc device '%s'; should be [0..%u]\n", + argv[1], get_mmc_dev_count() - 1); + return CMD_RET_FAILURE; + } - dev = simple_strtoul(argv[2], NULL, 10); + width = simple_strtoul(argv[2], &end, 10); + if (width > 2 || *end != '\0') { + printf("Invalid boot_bus_width parameter '%s'; expected [0..2]\n", + argv[2]); + return CMD_RET_FAILURE; + } - u32 bootsize = simple_strtoul(argv[3], NULL, 10); - u32 rpmbsize = simple_strtoul(argv[4], NULL, 10); - struct mmc *mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return CMD_RET_FAILURE; - } + reset = simple_strtoul(argv[3], &end, 10); + if (reset > 1 || *end != '\0') { + printf("Invalid reset_boot_bus_width parameter '%s'; expected 0 or 1\n", + argv[3]); + return CMD_RET_FAILURE; + } + mode = simple_strtoul(argv[4], &end, 10); + if (mode > 2 || *end != '\0') { + printf("Invalid boot_mode parameter '%s'; expected [0..2]\n", + argv[4]); + return CMD_RET_FAILURE; + } - if (IS_SD(mmc)) { - printf("It is not a EMMC device\n"); - return CMD_RET_FAILURE; - } + mmc = init_mmc_device(dev, false); + if (!mmc) { + printf("Failed to init MMC device %d\n", dev); + return CMD_RET_FAILURE; + } - if (0 == mmc_boot_partition_size_change(mmc, - bootsize, rpmbsize)) { - printf("EMMC boot partition Size %d MB\n", bootsize); - printf("EMMC RPMB partition Size %d MB\n", rpmbsize); - return CMD_RET_SUCCESS; - } else { - printf("EMMC boot partition Size change Failed.\n"); - return CMD_RET_FAILURE; - } -#endif /* CONFIG_SUPPORT_EMMC_BOOT */ - } - state = MMC_INVALID; - if (argc == 5 && strcmp(argv[1], "read") == 0) - state = MMC_READ; - else if (argc == 5 && strcmp(argv[1], "write") == 0) - state = MMC_WRITE; - else if (argc == 4 && strcmp(argv[1], "erase") == 0) - state = MMC_ERASE; - - if (state != MMC_INVALID) { - struct mmc *mmc = find_mmc_device(curr_device); - int idx = 2; - u32 blk, cnt, n; - void *addr; - - if (state != MMC_ERASE) { - addr = (void *)simple_strtoul(argv[idx], NULL, 16); - ++idx; - } else - addr = NULL; - blk = simple_strtoul(argv[idx], NULL, 16); - cnt = simple_strtoul(argv[idx + 1], NULL, 16); - - if (!mmc) { - printf("no mmc device at slot %x\n", curr_device); - return CMD_RET_FAILURE; - } + if (IS_SD(mmc)) { + puts("BOOT_BUS_WIDTH only exists on eMMC\n"); + return CMD_RET_FAILURE; + } - printf("\nMMC %s: dev # %d, block # %d, count %d ... ", - argv[1], curr_device, blk, cnt); + ret = mmc_set_boot_bus_width(mmc, width, reset, mode); + if (ret) + printf("Setting boot bus width failed: %d\n", ret); + return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} - mmc_init(mmc); +static int do_mmc_boot_resize(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev; + struct mmc *mmc; + u32 bootsize, rpmbsize; + int ret; + char *end; - if ((state == MMC_WRITE || state == MMC_ERASE)) { - if (mmc_getwp(mmc) == 1) { - printf("Error: card is write protected!\n"); - return CMD_RET_FAILURE; - } - } + if (argc != 4) + return CMD_RET_USAGE; - switch (state) { - case MMC_READ: - n = mmc->block_dev.block_read(curr_device, blk, - cnt, addr); - /* flush cache after read */ - flush_cache((ulong)addr, cnt * 512); /* FIXME */ - break; - case MMC_WRITE: - n = mmc->block_dev.block_write(curr_device, blk, - cnt, addr); - break; - case MMC_ERASE: - n = mmc->block_dev.block_erase(curr_device, blk, cnt); - break; - default: - BUG(); - } + dev = simple_strtoul(argv[1], &end, 10); + if (dev < 0 || dev >= get_mmc_dev_count() || *end != '\0') { + printf("Invalid mmc device '%s'; should be [0..%u]\n", + argv[1], get_mmc_dev_count() - 1); + return CMD_RET_FAILURE; + } + + bootsize = simple_strtoul(argv[2], &end, 10); + if (bootsize > 64 || *end != '\0') { + return CMD_RET_FAILURE; + } + + rpmbsize = simple_strtoul(argv[3], &end, 10); + if (rpmbsize > 64 || *end != '\0') { + return CMD_RET_FAILURE; + } + + mmc = init_mmc_device(dev, false); + if (!mmc) + return CMD_RET_FAILURE; + + if (IS_SD(mmc)) { + printf("mmc device %d is not an EMMC device\n", dev); + return CMD_RET_FAILURE; + } + + ret = mmc_boot_partition_size_change(mmc, bootsize, rpmbsize); + if (ret) { + printf("EMMC boot partition size change failed: %d\n", ret); + return CMD_RET_FAILURE; + } + + printf("EMMC boot partition Size %d MB\n", bootsize); + printf("EMMC RPMB partition Size %d MB\n", rpmbsize); + return CMD_RET_SUCCESS; +} + +static int do_mmc_partconf(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev; + struct mmc *mmc; + u8 ack, part_num, access; + char *end; + int ret; + + if (argc != 5) + return CMD_RET_USAGE; + + dev = simple_strtoul(argv[1], &end, 10); + if (dev < 0 || dev >= get_mmc_dev_count() || *end != '\0') { + printf("Invalid mmc device '%s'; should be [0..%u]\n", + argv[1], get_mmc_dev_count() - 1); + return CMD_RET_FAILURE; + } + + ack = simple_strtoul(argv[2], &end, 10); + if (ack < 0 || ack > 1 || *end != '\0') { + printf("Invalid boot_ack value: %s\n", argv[2]); + return CMD_RET_FAILURE; + } - printf("%d blocks %s: %s\n", - n, argv[1], (n == cnt) ? "OK" : "ERROR"); - return (n == cnt) ? 0 : 1; + part_num = simple_strtoul(argv[3], &end, 10); + if (part_num < 0 || (part_num > 4 && part_num != 7) || *end != '\0') { + printf("Invalid part_num: %s\n", argv[3]); + return CMD_RET_FAILURE; } - return CMD_RET_USAGE; + access = simple_strtoul(argv[4], &end, 10); + if (access < 0 || access > 7 || *end != '\0') { + printf("Invalid access value: %s\n", argv[4]); + return CMD_RET_FAILURE; + } + + mmc = init_mmc_device(dev, false); + if (!mmc) + return CMD_RET_FAILURE; + + if (IS_SD(mmc)) { + puts("PARTITION_CONFIG only exists on eMMC\n"); + return CMD_RET_FAILURE; + } + + /* acknowledge to be sent during boot operation */ + ret = mmc_set_part_conf(mmc, ack, part_num, access); + if (ret) + printf("partconf failed: %d\n", ret); + return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +static int do_mmc_rst_func(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev; + struct mmc *mmc; + u8 enable; + char *end; + + /* + * Set the RST_n_ENABLE bit of RST_n_FUNCTION + * The only valid values are 0x0, 0x1 and 0x2 and writing + * a value of 0x1 or 0x2 sets the value permanently. + */ + if (argc != 3) + return CMD_RET_USAGE; + + dev = simple_strtoul(argv[1], &end, 10); + if (dev < 0 || dev >= get_mmc_dev_count() || *end != '\0') { + printf("Invalid mmc device '%s'; should be [0..%u]\n", + argv[1], get_mmc_dev_count() - 1); + return CMD_RET_FAILURE; + } + + enable = simple_strtoul(argv[2], &end, 10); + + if (enable > 2 || enable < 0) { + puts("Invalid RST_n_ENABLE value\n"); + return CMD_RET_USAGE; + } + + mmc = init_mmc_device(dev, false); + if (!mmc) + return CMD_RET_FAILURE; + + if (IS_SD(mmc)) { + puts("RST_n_FUNCTION only exists on eMMC\n"); + return CMD_RET_FAILURE; + } + + return mmc_set_rst_n_function(mmc, enable); +} +#endif + +static int do_mmc_setdsr(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + u32 val; + char *end; + int ret; + + if (argc != 2) + return CMD_RET_USAGE; + val = simple_strtoul(argv[2], &end, 16); + if (val > 0xffff || *end != '\0') { + printf("Invalid DSR value '%s'; expected hex number [0..ffff]\n", + argv[2]); + return CMD_RET_FAILURE; + } + + mmc = find_mmc_device(curr_device); + if (!mmc) { + printf("no mmc device at slot %x\n", curr_device); + return CMD_RET_FAILURE; + } + ret = mmc_set_dsr(mmc, val); + printf("set dsr %s\n", (!ret) ? "OK, force rescan" : "ERROR"); + if (!ret) { + mmc->has_init = 0; + if (mmc_init(mmc)) + return CMD_RET_FAILURE; + else + return CMD_RET_SUCCESS; + } + return ret; +} + +static cmd_tbl_t cmd_mmc[] = { + U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""), + U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""), + U_BOOT_CMD_MKENT(write, 4, 0, do_mmc_write, "", ""), + U_BOOT_CMD_MKENT(erase, 3, 0, do_mmc_erase, "", ""), + U_BOOT_CMD_MKENT(rescan, 1, 1, do_mmc_rescan, "", ""), + U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""), + U_BOOT_CMD_MKENT(dev, 3, 0, do_mmc_dev, "", ""), + U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""), + U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""), +#ifdef CONFIG_SUPPORT_EMMC_BOOT + U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""), + U_BOOT_CMD_MKENT(bootpart-resize, 4, 0, do_mmc_boot_resize, "", ""), + U_BOOT_CMD_MKENT(partconf, 5, 0, do_mmc_partconf, "", ""), + U_BOOT_CMD_MKENT(rst-function, 3, 0, do_mmc_rst_func, "", ""), +#endif +#ifdef CONFIG_SUPPORT_EMMC_RPMB + U_BOOT_CMD_MKENT(rpmb, CONFIG_SYS_MAXARGS, 1, do_mmcrpmb, "", ""), +#endif + U_BOOT_CMD_MKENT(setdsr, 2, 0, do_mmc_setdsr, "", ""), +}; + +static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *cp; + + cp = find_cmd_tbl(argv[1], cmd_mmc, ARRAY_SIZE(cmd_mmc)); + + /* Drop the mmc command */ + argc--; + argv++; + + if (cp == NULL || argc > cp->maxargs) + return CMD_RET_USAGE; + if (flag == CMD_FLAG_REPEAT && !cp->repeatable) + return CMD_RET_SUCCESS; + + if (curr_device < 0) { + if (get_mmc_num() > 0) { + curr_device = 0; + } else { + puts("No MMC device available\n"); + return CMD_RET_FAILURE; + } + } + return cp->cmd(cmdtp, flag, argc, argv); } U_BOOT_CMD( - mmc, 6, 1, do_mmcops, + mmc, 29, 1, do_mmcops, "MMC sub system", - "read addr blk# cnt\n" + "info - display info of the current MMC device\n" + "mmc read addr blk# cnt\n" "mmc write addr blk# cnt\n" "mmc erase blk# cnt\n" "mmc rescan\n" "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device [partition]\n" "mmc list - lists available devices\n" + "mmc hwpartition [args...] - does hardware partitioning\n" + " arguments (sizes in 512-byte blocks):\n" + " [user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes\n" + " [gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition\n" + " [check|set|complete] - mode, complete set partitioning completed\n" + " WARNING: Partitioning is a write-once setting once it is set to complete.\n" + " Power cycling is required to initialize partitions after set to complete.\n" #ifdef CONFIG_SUPPORT_EMMC_BOOT - "mmc open \n" - " - Enable boot_part for booting and enable R/W access of boot_part\n" - "mmc close \n" - " - Enable boot_part for booting and disable access to boot_part\n" - "mmc bootpart \n" - " - change sizes of boot and RPMB partions of specified device\n" + "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" + " - Set the BOOT_BUS_WIDTH field of the specified device\n" + "mmc bootpart-resize \n" + " - Change sizes of boot and RPMB partitions of specified device\n" + "mmc partconf dev boot_ack boot_partition partition_access\n" + " - Change the bits of the PARTITION_CONFIG field of the specified device\n" + "mmc rst-function dev value\n" + " - Change the RST_n_FUNCTION field of the specified device\n" + " WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n" #endif +#ifdef CONFIG_SUPPORT_EMMC_RPMB + "mmc rpmb read addr blk# cnt [address of auth-key] - block size is 256 bytes\n" + "mmc rpmb write addr blk# cnt
- block size is 256 bytes\n" + "mmc rpmb key
- program the RPMB authentication key.\n" + "mmc rpmb counter - read the value of the write counter\n" +#endif + "mmc setdsr - set DSR register value\n" ); + +/* Old command kept for compatibility. Same as 'mmc info' */ +U_BOOT_CMD( + mmcinfo, 1, 0, do_mmcinfo, + "display MMC info", + "- display info of the current MMC device" +); + #endif /* !CONFIG_GENERIC_MMC */ diff --git a/common/cmd_mmc_spi.c b/common/cmd_mmc_spi.c index 98cd788c76..a2138b8650 100644 --- a/common/cmd_mmc_spi.c +++ b/common/cmd_mmc_spi.c @@ -72,7 +72,7 @@ static int do_mmc_spi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Failed to create MMC Device\n"); return 1; } - printf("%s: %d at %u:%u hz %u mode %u\n", mmc->name, mmc->block_dev.dev, + printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name, mmc->block_dev.dev, bus, cs, speed, mode); mmc_init(mmc); return 0; diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c index 8cc5c383b6..3e34558acf 100644 --- a/common/cmd_mtdparts.c +++ b/common/cmd_mtdparts.c @@ -93,13 +93,13 @@ DECLARE_GLOBAL_DATA_PTR; /* special size referring to all the remaining space in a partition */ -#define SIZE_REMAINING 0xFFFFFFFF +#define SIZE_REMAINING (~0llu) /* special offset value, it is used when not provided by user * * this value is used temporarily during parsing, later such offests * are recalculated */ -#define OFFSET_NOT_SPECIFIED 0xFFFFFFFF +#define OFFSET_NOT_SPECIFIED (~0llu) /* minimum partition size */ #define MIN_PART_SIZE 4096 @@ -160,9 +160,9 @@ static int device_del(struct mtd_device *dev); * @param retptr output pointer to next char after parse completes (output) * @return resulting unsigned int */ -static unsigned long memsize_parse (const char *const ptr, const char **retptr) +static u64 memsize_parse (const char *const ptr, const char **retptr) { - unsigned long ret = simple_strtoul(ptr, (char **)retptr, 0); + u64 ret = simple_strtoull(ptr, (char **)retptr, 0); switch (**retptr) { case 'G': @@ -193,20 +193,20 @@ static unsigned long memsize_parse (const char *const ptr, const char **retptr) * @param buf output buffer * @param size size to be converted to string */ -static void memsize_format(char *buf, u32 size) +static void memsize_format(char *buf, u64 size) { #define SIZE_GB ((u32)1024*1024*1024) #define SIZE_MB ((u32)1024*1024) #define SIZE_KB ((u32)1024) if ((size % SIZE_GB) == 0) - sprintf(buf, "%ug", size/SIZE_GB); + sprintf(buf, "%llug", size/SIZE_GB); else if ((size % SIZE_MB) == 0) - sprintf(buf, "%um", size/SIZE_MB); + sprintf(buf, "%llum", size/SIZE_MB); else if (size % SIZE_KB == 0) - sprintf(buf, "%uk", size/SIZE_KB); + sprintf(buf, "%lluk", size/SIZE_KB); else - sprintf(buf, "%u", size); + sprintf(buf, "%llu", size); } /** @@ -292,6 +292,7 @@ static int get_mtd_info(u8 type, u8 num, struct mtd_info **mtd) printf("Device %s not found!\n", mtd_dev); return 1; } + put_mtd_device(*mtd); return 0; } @@ -310,6 +311,7 @@ static int part_validate_eraseblock(struct mtdids *id, struct part_info *part) struct mtd_info *mtd = NULL; int i, j; ulong start; + u64 offset, size; if (get_mtd_info(id->type, id->num, &mtd)) return 1; @@ -321,13 +323,15 @@ static int part_validate_eraseblock(struct mtdids *id, struct part_info *part) * Only one eraseregion (NAND, OneNAND or uniform NOR), * checking for alignment is easy here */ - if ((unsigned long)part->offset % mtd->erasesize) { + offset = part->offset; + if (do_div(offset, mtd->erasesize)) { printf("%s%d: partition (%s) start offset alignment incorrect\n", MTD_DEV_TYPE(id->type), id->num, part->name); return 1; } - if (part->size % mtd->erasesize) { + size = part->size; + if (do_div(size, mtd->erasesize)) { printf("%s%d: partition (%s) size alignment incorrect\n", MTD_DEV_TYPE(id->type), id->num, part->name); return 1; @@ -380,10 +384,9 @@ static int part_validate_eraseblock(struct mtdids *id, struct part_info *part) /** - * Performs sanity check for supplied partition. Offset and size are verified - * to be within valid range. Partition type is checked and either - * parts_validate_nor() or parts_validate_nand() is called with the argument - * of part. + * Performs sanity check for supplied partition. Offset and size are + * verified to be within valid range. Partition type is checked and + * part_validate_eraseblock() is called with the argument of part. * * @param id of the parent device * @param part partition to validate @@ -395,7 +398,7 @@ static int part_validate(struct mtdids *id, struct part_info *part) part->size = id->size - part->offset; if (part->offset > id->size) { - printf("%s: offset %08x beyond flash size %08x\n", + printf("%s: offset %08llx beyond flash size %08llx\n", id->mtd_id, part->offset, id->size); return 1; } @@ -419,7 +422,7 @@ static int part_validate(struct mtdids *id, struct part_info *part) } /** - * Delete selected partition from the partion list of the specified device. + * Delete selected partition from the partition list of the specified device. * * @param dev device to delete partition from * @param part partition to delete @@ -578,8 +581,8 @@ static int part_add(struct mtd_device *dev, struct part_info *part) static int part_parse(const char *const partdef, const char **ret, struct part_info **retpart) { struct part_info *part; - unsigned long size; - unsigned long offset; + u64 size; + u64 offset; const char *name; int name_len; unsigned int mask_flags; @@ -598,7 +601,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i } else { size = memsize_parse(p, &p); if (size < MIN_PART_SIZE) { - printf("partition size too small (%lx)\n", size); + printf("partition size too small (%llx)\n", size); return 1; } } @@ -670,14 +673,14 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i part->auto_name = 0; } else { /* auto generated name in form of size@offset */ - sprintf(part->name, "0x%08lx@0x%08lx", size, offset); + sprintf(part->name, "0x%08llx@0x%08llx", size, offset); part->auto_name = 1; } part->name[name_len - 1] = '\0'; INIT_LIST_HEAD(&part->link); - debug("+ partition: name %-22s size 0x%08x offset 0x%08x mask flags %d\n", + debug("+ partition: name %-22s size 0x%08llx offset 0x%08llx mask flags %d\n", part->name, part->size, part->offset, part->mask_flags); @@ -693,7 +696,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i * @param size a pointer to the size of the mtd device (output) * @return 0 if device is valid, 1 otherwise */ -static int mtd_device_validate(u8 type, u8 num, u32 *size) +static int mtd_device_validate(u8 type, u8 num, u64 *size) { struct mtd_info *mtd = NULL; @@ -826,7 +829,7 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_ LIST_HEAD(tmp_list); struct list_head *entry, *n; u16 num_parts; - u32 offset; + u64 offset; int err = 1; debug("===device_parse===\n"); @@ -858,7 +861,7 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_ debug("dev type = %d (%s), dev num = %d, mtd-id = %s\n", id->type, MTD_DEV_TYPE(id->type), id->num, id->mtd_id); - debug("parsing partitions %.*s\n", (pend ? pend - p : strlen(p)), p); + debug("parsing partitions %.*s\n", (int)(pend ? pend - p : strlen(p)), p); /* parse partitions */ @@ -1003,7 +1006,7 @@ static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_ list_for_each(entry, &mtdids) { id = list_entry(entry, struct mtdids, link); - debug("entry: '%s' (len = %d)\n", + debug("entry: '%s' (len = %zu)\n", id->mtd_id, strlen(id->mtd_id)); if (mtd_id_len != strlen(id->mtd_id)) @@ -1071,7 +1074,8 @@ static int generate_mtdparts(char *buf, u32 buflen) struct part_info *part, *prev_part; char *p = buf; char tmpbuf[32]; - u32 size, offset, len, part_cnt; + u64 size, offset; + u32 len, part_cnt; u32 maxlen = buflen - 1; debug("--- generate_mtdparts ---\n"); @@ -1270,7 +1274,7 @@ static void print_partition_table(void) list_for_each(pentry, &dev->parts) { part = list_entry(pentry, struct part_info, link); - printf("%2d: %-20s0x%08x\t0x%08x\t%d\n", + printf("%2d: %-20s0x%08llx\t0x%08llx\t%d\n", part_num, part->name, part->size, part->offset, part->mask_flags); #endif /* defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES) */ @@ -1297,7 +1301,7 @@ static void list_partitions(void) if (current_mtd_dev) { part = mtd_part_info(current_mtd_dev, current_mtd_partnum); if (part) { - printf("\nactive partition: %s%d,%d - (%s) 0x%08x @ 0x%08x\n", + printf("\nactive partition: %s%d,%d - (%s) 0x%08llx @ 0x%08llx\n", MTD_DEV_TYPE(current_mtd_dev->id->type), current_mtd_dev->id->num, current_mtd_partnum, part->name, part->size, part->offset); @@ -1397,7 +1401,7 @@ static int delete_partition(const char *id) if (find_dev_and_part(id, &dev, &pnum, &part) == 0) { - debug("delete_partition: device = %s%d, partition %d = (%s) 0x%08x@0x%08x\n", + debug("delete_partition: device = %s%d, partition %d = (%s) 0x%08llx@0x%08llx\n", MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum, part->name, part->size, part->offset); @@ -1589,7 +1593,7 @@ static int parse_mtdids(const char *const ids) struct list_head *entry, *n; struct mtdids *id_tmp; u8 type, num; - u32 size; + u64 size; int ret = 1; debug("\n---parse_mtdids---\nmtdids = %s\n\n", ids); @@ -1663,7 +1667,7 @@ static int parse_mtdids(const char *const ids) id->mtd_id[mtd_id_len - 1] = '\0'; INIT_LIST_HEAD(&id->link); - debug("+ id %s%d\t%16d bytes\t%s\n", + debug("+ id %s%d\t%16lld bytes\t%s\n", MTD_DEV_TYPE(id->type), id->num, id->size, id->mtd_id); diff --git a/common/cmd_nand.c b/common/cmd_nand.c index be14b5f6ca..7d477aac56 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -42,6 +42,7 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) int i; u_char *datbuf, *oobbuf, *p; static loff_t last; + int ret = 0; if (repeat) off = last + nand->writesize; @@ -49,11 +50,17 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) last = off; datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize); - oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); - if (!datbuf || !oobbuf) { + if (!datbuf) { puts("No memory for page buffer\n"); return 1; } + + oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); + if (!oobbuf) { + puts("No memory for page buffer\n"); + ret = 1; + goto free_dat; + } off &= ~(nand->writesize - 1); loff_t addr = (loff_t) off; struct mtd_oob_ops ops; @@ -66,23 +73,25 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) i = mtd_read_oob(nand, addr, &ops); if (i < 0) { printf("Error (%d) reading page %08lx\n", i, off); - free(datbuf); - free(oobbuf); - return 1; + ret = 1; + goto free_all; } printf("Page %08lx dump:\n", off); - i = nand->writesize >> 4; - p = datbuf; - while (i--) { - if (!only_oob) + if (!only_oob) { + i = nand->writesize >> 4; + p = datbuf; + + while (i--) { printf("\t%02x %02x %02x %02x %02x %02x %02x %02x" " %02x %02x %02x %02x %02x %02x %02x %02x\n", p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]); - p += 16; + p += 16; + } } + puts("OOB:\n"); i = nand->oobsize >> 3; p = oobbuf; @@ -91,10 +100,13 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); p += 8; } - free(datbuf); + +free_all: free(oobbuf); +free_dat: + free(datbuf); - return 0; + return ret; } /* ------------------------------------------------------------------------- */ @@ -594,22 +606,16 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) opts.spread = spread; if (scrub) { - if (!scrub_yes) - puts(scrub_warn); - - if (scrub_yes) + if (scrub_yes) { opts.scrub = 1; - else if (getc() == 'y') { - puts("y"); - if (getc() == '\r') + } else { + puts(scrub_warn); + if (confirm_yesno()) { opts.scrub = 1; - else { + } else { puts("scrub aborted\n"); return CMD_RET_FAILURE; } - } else { - puts("scrub aborted\n"); - return CMD_RET_FAILURE; } } ret = nand_erase_opts(nand, &opts); @@ -642,8 +648,6 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ printf("\nNAND %s: ", read ? "read" : "write"); - nand = &nand_info[dev]; - s = strchr(cmd, '.'); if (s && !strcmp(s, ".raw")) { @@ -652,6 +656,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (arg_off(argv[3], &dev, &off, &size, &maxsize)) return 1; + nand = &nand_info[dev]; + if (argc > 4 && !str2long(argv[4], &pagecount)) { printf("'%s' is not a number\n", argv[4]); return 1; @@ -674,6 +680,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rwsize = size; } + nand = &nand_info[dev]; + if (!s || !strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")) { if (read) @@ -893,7 +901,9 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, int r; char *s; size_t cnt; +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) image_header_t *hdr; +#endif #if defined(CONFIG_FIT) const void *fit_hdr = NULL; #endif @@ -919,6 +929,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, bootstage_mark(BOOTSTAGE_ID_NAND_HDR_READ); switch (genimg_get_format ((void *)addr)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: hdr = (image_header_t *)addr; @@ -927,6 +938,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, cnt = image_get_image_size (hdr); break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: fit_hdr = (const void *)addr; diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 778dca5af9..855808c3e4 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -7,7 +7,7 @@ * * Copyright 2011 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -25,6 +25,7 @@ */ #include +#include #include #include #include @@ -33,6 +34,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -157,10 +159,8 @@ static int do_env_grep(cmd_tbl_t *cmdtp, int flag, grep_how = H_MATCH_SUBSTR; /* default: substring search */ grep_what = H_MATCH_BOTH; /* default: grep names and values */ - while (argc > 1 && **(argv + 1) == '-') { - char *arg = *++argv; - - --argc; + while (--argc > 0 && **++argv == '-') { + char *arg = *argv; while (*++arg) { switch (*arg) { #ifdef CONFIG_REGEX @@ -409,7 +409,7 @@ int do_env_ask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; /* prompt for input */ - len = readline(message); + len = cli_readline(message); if (size < len) console_buffer[size] = '\0'; @@ -592,7 +592,7 @@ static int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, else buffer[0] = '\0'; - if (readline_into_buffer("edit: ", buffer, 0) < 0) + if (cli_readline_into_buffer("edit: ", buffer, 0) < 0) return 1; return setenv(argv[1], buffer); @@ -848,7 +848,8 @@ static int do_env_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char buf[32]; - char *addr, *cmd, *res; + ulong addr; + char *ptr, *cmd, *res; size_t size = 0; ssize_t len; env_t *envp; @@ -893,10 +894,11 @@ NXTARG: ; if (argc < 1) return CMD_RET_USAGE; - addr = (char *)simple_strtoul(argv[0], NULL, 16); + addr = simple_strtoul(argv[0], NULL, 16); + ptr = map_sysmem(addr, size); if (size) - memset(addr, '\0', size); + memset(ptr, '\0', size); argc--; argv++; @@ -904,7 +906,7 @@ NXTARG: ; if (sep) { /* export as text file */ len = hexport_r(&env_htab, sep, H_MATCH_KEY | H_MATCH_IDENT, - &addr, size, argc, argv); + &ptr, size, argc, argv); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; @@ -915,12 +917,12 @@ NXTARG: ; return 0; } - envp = (env_t *)addr; + envp = (env_t *)ptr; if (chk) /* export as checksum protected block */ res = (char *)envp->data; else /* export as raw binary data */ - res = addr; + res = ptr; len = hexport_r(&env_htab, '\0', H_MATCH_KEY | H_MATCH_IDENT, @@ -948,11 +950,15 @@ sep_err: #ifdef CONFIG_CMD_IMPORTENV /* - * env import [-d] [-t | -b | -c] addr [size] + * env import [-d] [-t [-r] | -b | -c] addr [size] * -d: delete existing environment before importing; * otherwise overwrite / append to existion definitions * -t: assume text format; either "size" must be given or the * text data must be '\0' terminated + * -r: handle CRLF like LF, that means exported variables with + * a content which ends with \r won't get imported. Used + * to import text files created with editors which are using CRLF + * for line endings. Only effective in addition to -t. * -b: assume binary format ('\0' separated, "\0\0" terminated) * -c: assume checksum protected environment format * addr: memory address to read from @@ -962,11 +968,13 @@ sep_err: static int do_env_import(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *cmd, *addr; + ulong addr; + char *cmd, *ptr; char sep = '\n'; int chk = 0; int fmt = 0; int del = 0; + int crlf_is_lf = 0; size_t size; cmd = *argv; @@ -991,6 +999,9 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag, goto sep_err; sep = '\n'; break; + case 'r': /* handle CRLF like LF */ + crlf_is_lf = 1; + break; case 'd': del = 1; break; @@ -1006,12 +1017,19 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag, if (!fmt) printf("## Warning: defaulting to text format\n"); - addr = (char *)simple_strtoul(argv[0], NULL, 16); + if (sep != '\n' && crlf_is_lf ) + crlf_is_lf = 0; + + addr = simple_strtoul(argv[0], NULL, 16); + ptr = map_sysmem(addr, 0); if (argc == 2) { size = simple_strtoul(argv[1], NULL, 16); + } else if (argc == 1 && chk) { + puts("## Error: external checksum format must pass size\n"); + return CMD_RET_FAILURE; } else { - char *s = addr; + char *s = ptr; size = 0; @@ -1031,7 +1049,7 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag, if (chk) { uint32_t crc; - env_t *ep = (env_t *)addr; + env_t *ep = (env_t *)ptr; size -= offsetof(env_t, data); memcpy(&crc, &ep->crc, sizeof(crc)); @@ -1040,11 +1058,11 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag, puts("## Error: bad CRC, import failed\n"); return 1; } - addr = (char *)ep->data; + ptr = (char *)ep->data; } - if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR, - 0, NULL) == 0) { + if (himport_r(&env_htab, ptr, size, sep, del ? 0 : H_NOCLEAR, + crlf_is_lf, 0, NULL) == 0) { error("Environment import failed: errno = %d\n", errno); return 1; } @@ -1059,6 +1077,23 @@ sep_err: } #endif +#if defined(CONFIG_CMD_ENV_EXISTS) +static int do_env_exists(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + ENTRY e, *ep; + + if (argc < 2) + return CMD_RET_USAGE; + + e.key = argv[1]; + e.data = NULL; + hsearch_r(e, FIND, &ep, &env_htab, 0); + + return (ep == NULL) ? 1 : 0; +} +#endif + /* * New command line interface: "env" command with subcommands */ @@ -1094,6 +1129,9 @@ static cmd_tbl_t cmd_env_sub[] = { U_BOOT_CMD_MKENT(save, 1, 0, do_env_save, "", ""), #endif U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""), +#if defined(CONFIG_CMD_ENV_EXISTS) + U_BOOT_CMD_MKENT(exists, 2, 0, do_env_exists, "", ""), +#endif }; #if defined(CONFIG_NEEDS_MANUAL_RELOC) @@ -1136,6 +1174,9 @@ static char env_help_text[] = #if defined(CONFIG_CMD_EDITENV) "env edit name - edit environment variable\n" #endif +#if defined(CONFIG_CMD_ENV_EXISTS) + "env exists name - tests for existence of variable\n" +#endif #if defined(CONFIG_CMD_EXPORTENV) "env export [-t | -b | -c] [-s size] addr [var ...] - export environment\n" #endif @@ -1150,7 +1191,7 @@ static char env_help_text[] = #endif #endif #if defined(CONFIG_CMD_IMPORTENV) - "env import [-d] [-t | -b | -c] addr [size] - import environment\n" + "env import [-d] [-t [-r] | -b | -c] addr [size] - import environment\n" #endif "env print [-a | name ...] - print environment\n" #if defined(CONFIG_CMD_RUN) diff --git a/common/cmd_otp.c b/common/cmd_otp.c index 6f93335517..593bb8c650 100644 --- a/common/cmd_otp.c +++ b/common/cmd_otp.c @@ -18,6 +18,7 @@ #include #include +#include #include static const char *otp_strerror(uint32_t err) @@ -157,21 +158,9 @@ int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) lowup(half + count - 1), page + (half + count - 1) / 2, half + count ); - - i = 0; - while (1) { - if (tstc()) { - const char exp_ans[] = "YES\r"; - char c; - putc(c = getc()); - if (exp_ans[i++] != c) { - printf(" Aborting\n"); - return 1; - } else if (!exp_ans[i]) { - puts("\n"); - break; - } - } + if (!confirm_yesno()) { + printf(" Aborting\n"); + return 1; } } diff --git a/common/cmd_part.c b/common/cmd_part.c index 14248548d9..c99f52735f 100644 --- a/common/cmd_part.c +++ b/common/cmd_part.c @@ -26,7 +26,7 @@ #error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_PART to be enabled #endif -int do_part_uuid(int argc, char * const argv[]) +static int do_part_uuid(int argc, char * const argv[]) { int part; block_dev_desc_t *dev_desc; @@ -49,24 +49,42 @@ int do_part_uuid(int argc, char * const argv[]) return 0; } -int do_part_list(int argc, char * const argv[]) +static int do_part_list(int argc, char * const argv[]) { int ret; block_dev_desc_t *desc; - if (argc != 2) + if (argc < 2 || argc > 3) return CMD_RET_USAGE; ret = get_device(argv[0], argv[1], &desc); if (ret < 0) return 1; + if (argc == 3) { + int p; + char str[512] = { 0, }; + disk_partition_t info; + + for (p = 1; p < 128; p++) { + int r = get_partition_info(desc, p, &info); + + if (r == 0) { + char t[5]; + sprintf(t, "%s%d", str[0] ? " " : "", p); + strcat(str, t); + } + } + setenv(argv[2], str); + return 0; + } + print_part(desc); return 0; } -int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc < 2) return CMD_RET_USAGE; @@ -82,10 +100,12 @@ int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( part, 5, 1, do_part, "disk partition related commands", - "uuid :\n" + "part uuid :\n" " - print partition UUID\n" "part uuid : \n" " - set environment variable to partition UUID\n" "part list \n" - " - print a device's partition table" + " - print a device's partition table\n" + "part list \n" + " - set environment variable to the list of partitions" ); diff --git a/common/cmd_pci.c b/common/cmd_pci.c index d3e7c089b0..e3a77e3582 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -14,6 +14,8 @@ */ #include +#include +#include #include #include #include @@ -40,12 +42,16 @@ void pci_header_show_brief(pci_dev_t dev); */ void pciinfo(int BusNum, int ShortPCIListing) { + struct pci_controller *hose = pci_bus_to_hose(BusNum); int Device; int Function; unsigned char HeaderType; unsigned short VendorID; pci_dev_t dev; + if (!hose) + return; + printf("Scanning PCI devices on bus %d\n", BusNum); if (ShortPCIListing) { @@ -65,6 +71,9 @@ void pciinfo(int BusNum, int ShortPCIListing) dev = PCI_BDF(BusNum, Device, Function); + if (pci_skip_dev(hose, dev)) + continue; + pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) continue; @@ -345,7 +354,7 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag printf(" %02x", val1); } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { /* pressed as only input, don't modify current * location and move to next. "-" pressed will go back. @@ -353,9 +362,8 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag if (incrflag) addr += nbytes ? -size : size; nbytes = 1; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* good enough to not time out */ -#endif + /* good enough to not time out */ + bootretry_reset_cmd_timeout(); } #ifdef CONFIG_BOOT_RETRY_TIME else if (nbytes == -2) { @@ -367,11 +375,9 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag i = simple_strtoul(console_buffer, &endp, 16); nbytes = endp - console_buffer; if (nbytes) { -#ifdef CONFIG_BOOT_RETRY_TIME /* good enough to not time out */ - reset_cmd_timeout(); -#endif + bootretry_reset_cmd_timeout(); pci_cfg_write (bdf, addr, size, i); if (incrflag) addr += size; diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c index ddc24be7d3..682d18f55d 100644 --- a/common/cmd_pcmcia.c +++ b/common/cmd_pcmcia.c @@ -331,11 +331,8 @@ int check_ide_device (int slot) ide_devices_found |= (1 << slot); -#if CONFIG_CPC45 -#else /* set I/O area in config reg -> only valid for ARGOSY D5!!! */ *((uchar *)(addr + config_base)) = 1; -#endif #if 0 printf("\n## Config_base = %04x ###\n", config_base); printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base); diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index a2fb50ab9d..7e32c95df3 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -1,5 +1,6 @@ /* * Copyright 2010-2011 Calxeda, Inc. + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,8 +12,10 @@ #include #include #include +#include #include "menu.h" +#include "cli.h" #define MAX_TFTP_PATH_LEN 127 @@ -25,6 +28,8 @@ const char *pxe_default_paths[] = { NULL }; +static bool is_pxe; + /* * Like getenv, but prints an error if envvar isn't defined in the * environment. It always returns what getenv does, so it can be used in @@ -42,6 +47,7 @@ static char *from_env(const char *envvar) return ret; } +#ifdef CONFIG_CMD_NET /* * Convert an ethaddr from the environment to the format used by pxelinux * filenames based on mac addresses. Convert's ':' to '-', and adds "01-" to @@ -57,7 +63,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len) uchar ethaddr[6]; if (outbuf_len < 21) { - printf("outbuf is too small (%d < 21)\n", outbuf_len); + printf("outbuf is too small (%zd < 21)\n", outbuf_len); return -EINVAL; } @@ -72,6 +78,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len) return 1; } +#endif /* * Returns the directory the file specified in the bootfile env variable is @@ -84,7 +91,8 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path, char *bootfile, *last_slash; size_t path_len = 0; - if (file_path[0] == '/') + /* Only syslinux allows absolute paths */ + if (file_path[0] == '/' && !is_pxe) goto ret; bootfile = from_env("bootfile"); @@ -100,7 +108,7 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path, path_len = (last_slash - bootfile) + 1; if (bootfile_path_size < path_len) { - printf("bootfile_path too small. (%d < %d)\n", + printf("bootfile_path too small. (%zd < %zd)\n", bootfile_path_size, path_len); return -1; @@ -114,44 +122,59 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path, return 1; } -static int (*do_getfile)(const char *file_path, char *file_addr); +static int (*do_getfile)(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr); -static int do_get_tftp(const char *file_path, char *file_addr) +#ifdef CONFIG_CMD_NET +static int do_get_tftp(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) { char *tftp_argv[] = {"tftp", NULL, NULL, NULL}; tftp_argv[1] = file_addr; tftp_argv[2] = (void *)file_path; - if (do_tftpb(NULL, 0, 3, tftp_argv)) + if (do_tftpb(cmdtp, 0, 3, tftp_argv)) return -ENOENT; return 1; } +#endif static char *fs_argv[5]; -static int do_get_ext2(const char *file_path, char *file_addr) +static int do_get_ext2(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) { #ifdef CONFIG_CMD_EXT2 fs_argv[0] = "ext2load"; fs_argv[3] = file_addr; fs_argv[4] = (void *)file_path; - if (!do_ext2load(NULL, 0, 5, fs_argv)) + if (!do_ext2load(cmdtp, 0, 5, fs_argv)) return 1; #endif return -ENOENT; } -static int do_get_fat(const char *file_path, char *file_addr) +static int do_get_fat(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) { #ifdef CONFIG_CMD_FAT fs_argv[0] = "fatload"; fs_argv[3] = file_addr; fs_argv[4] = (void *)file_path; - if (!do_fat_fsload(NULL, 0, 5, fs_argv)) + if (!do_fat_fsload(cmdtp, 0, 5, fs_argv)) + return 1; +#endif + return -ENOENT; +} + +static int do_get_any(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr) +{ +#ifdef CONFIG_CMD_FS_GENERIC + fs_argv[0] = "load"; + fs_argv[3] = file_addr; + fs_argv[4] = (void *)file_path; + + if (!do_load(cmdtp, 0, 5, fs_argv, FS_TYPE_ANY)) return 1; #endif return -ENOENT; @@ -165,7 +188,7 @@ static int do_get_fat(const char *file_path, char *file_addr) * * Returns 1 for success, or < 0 on error. */ -static int get_relfile(const char *file_path, void *file_addr) +static int get_relfile(cmd_tbl_t *cmdtp, const char *file_path, void *file_addr) { size_t path_len; char relfile[MAX_TFTP_PATH_LEN+1]; @@ -194,7 +217,7 @@ static int get_relfile(const char *file_path, void *file_addr) sprintf(addr_buf, "%p", file_addr); - return do_getfile(relfile, addr_buf); + return do_getfile(cmdtp, relfile, addr_buf); } /* @@ -204,13 +227,13 @@ static int get_relfile(const char *file_path, void *file_addr) * * Returns 1 on success, or < 0 for error. */ -static int get_pxe_file(const char *file_path, void *file_addr) +static int get_pxe_file(cmd_tbl_t *cmdtp, const char *file_path, void *file_addr) { unsigned long config_file_size; char *tftp_filesize; int err; - err = get_relfile(file_path, file_addr); + err = get_relfile(cmdtp, file_path, file_addr); if (err < 0) return err; @@ -232,6 +255,8 @@ static int get_pxe_file(const char *file_path, void *file_addr) return 1; } +#ifdef CONFIG_CMD_NET + #define PXELINUX_DIR "pxelinux.cfg/" /* @@ -241,7 +266,7 @@ static int get_pxe_file(const char *file_path, void *file_addr) * * Returns 1 on success or < 0 on error. */ -static int get_pxelinux_path(const char *file, void *pxefile_addr_r) +static int get_pxelinux_path(cmd_tbl_t *cmdtp, const char *file, void *pxefile_addr_r) { size_t base_len = strlen(PXELINUX_DIR); char path[MAX_TFTP_PATH_LEN+1]; @@ -254,7 +279,7 @@ static int get_pxelinux_path(const char *file, void *pxefile_addr_r) sprintf(path, PXELINUX_DIR "%s", file); - return get_pxe_file(path, pxefile_addr_r); + return get_pxe_file(cmdtp, path, pxefile_addr_r); } /* @@ -262,7 +287,7 @@ static int get_pxelinux_path(const char *file, void *pxefile_addr_r) * * Returns 1 on success or < 0 on error. */ -static int pxe_uuid_path(void *pxefile_addr_r) +static int pxe_uuid_path(cmd_tbl_t *cmdtp, void *pxefile_addr_r) { char *uuid_str; @@ -271,7 +296,7 @@ static int pxe_uuid_path(void *pxefile_addr_r) if (!uuid_str) return -ENOENT; - return get_pxelinux_path(uuid_str, pxefile_addr_r); + return get_pxelinux_path(cmdtp, uuid_str, pxefile_addr_r); } /* @@ -280,7 +305,7 @@ static int pxe_uuid_path(void *pxefile_addr_r) * * Returns 1 on success or < 0 on error. */ -static int pxe_mac_path(void *pxefile_addr_r) +static int pxe_mac_path(cmd_tbl_t *cmdtp, void *pxefile_addr_r) { char mac_str[21]; int err; @@ -290,7 +315,7 @@ static int pxe_mac_path(void *pxefile_addr_r) if (err < 0) return err; - return get_pxelinux_path(mac_str, pxefile_addr_r); + return get_pxelinux_path(cmdtp, mac_str, pxefile_addr_r); } /* @@ -300,7 +325,7 @@ static int pxe_mac_path(void *pxefile_addr_r) * * Returns 1 on success or < 0 on error. */ -static int pxe_ipaddr_paths(void *pxefile_addr_r) +static int pxe_ipaddr_paths(cmd_tbl_t *cmdtp, void *pxefile_addr_r) { char ip_addr[9]; int mask_pos, err; @@ -308,7 +333,7 @@ static int pxe_ipaddr_paths(void *pxefile_addr_r) sprintf(ip_addr, "%08X", ntohl(NetOurIP)); for (mask_pos = 7; mask_pos >= 0; mask_pos--) { - err = get_pxelinux_path(ip_addr, pxefile_addr_r); + err = get_pxelinux_path(cmdtp, ip_addr, pxefile_addr_r); if (err > 0) return err; @@ -359,16 +384,16 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Keep trying paths until we successfully get a file we're looking * for. */ - if (pxe_uuid_path((void *)pxefile_addr_r) > 0 || - pxe_mac_path((void *)pxefile_addr_r) > 0 || - pxe_ipaddr_paths((void *)pxefile_addr_r) > 0) { + if (pxe_uuid_path(cmdtp, (void *)pxefile_addr_r) > 0 || + pxe_mac_path(cmdtp, (void *)pxefile_addr_r) > 0 || + pxe_ipaddr_paths(cmdtp, (void *)pxefile_addr_r) > 0) { printf("Config file found\n"); return 0; } while (pxe_default_paths[i]) { - if (get_pxelinux_path(pxe_default_paths[i], + if (get_pxelinux_path(cmdtp, pxe_default_paths[i], (void *)pxefile_addr_r) > 0) { printf("Config file found\n"); return 0; @@ -380,6 +405,7 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } +#endif /* * Wrapper to make it easier to store the file at file_path in the location @@ -388,7 +414,7 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * * Returns 1 on success or < 0 on error. */ -static int get_relfile_envaddr(const char *file_path, const char *envaddr_name) +static int get_relfile_envaddr(cmd_tbl_t *cmdtp, const char *file_path, const char *envaddr_name) { unsigned long file_addr; char *envaddr; @@ -401,7 +427,7 @@ static int get_relfile_envaddr(const char *file_path, const char *envaddr_name) if (strict_strtoul(envaddr, 16, &file_addr) < 0) return -EINVAL; - return get_relfile(file_path, (void *)file_addr); + return get_relfile(cmdtp, file_path, (void *)file_addr); } /* @@ -442,6 +468,7 @@ struct pxe_label { char *append; char *initrd; char *fdt; + char *fdtdir; int ipappend; int attempted; int localboot; @@ -514,6 +541,9 @@ static void label_destroy(struct pxe_label *label) if (label->fdt) free(label->fdt); + if (label->fdtdir) + free(label->fdtdir); + free(label); } @@ -549,8 +579,12 @@ static int label_localboot(struct pxe_label *label) if (!localcmd) return -ENOENT; - if (label->append) - setenv("bootargs", label->append); + if (label->append) { + char bootargs[CONFIG_SYS_CBSIZE]; + + cli_simple_process_macros(label->append, bootargs); + setenv("bootargs", bootargs); + } debug("running: %s\n", localcmd); @@ -572,15 +606,16 @@ static int label_localboot(struct pxe_label *label) * If the label specifies an 'append' line, its contents will overwrite that * of the 'bootargs' environment variable. */ -static int label_boot(struct pxe_label *label) +static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) { char *bootm_argv[] = { "bootm", NULL, NULL, NULL, NULL }; char initrd_str[22]; char mac_str[29] = ""; char ip_str[68] = ""; - char *bootargs; int bootm_argc = 3; int len = 0; + ulong kernel_addr; + void *buf; label_print(label); @@ -599,7 +634,7 @@ static int label_boot(struct pxe_label *label) } if (label->initrd) { - if (get_relfile_envaddr(label->initrd, "ramdisk_addr_r") < 0) { + if (get_relfile_envaddr(cmdtp, label->initrd, "ramdisk_addr_r") < 0) { printf("Skipping %s for failure retrieving initrd\n", label->name); return 1; @@ -613,7 +648,7 @@ static int label_boot(struct pxe_label *label) bootm_argv[2] = "-"; } - if (get_relfile_envaddr(label->kernel, "kernel_addr_r") < 0) { + if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) { printf("Skipping %s for failure retrieving kernel\n", label->name); return 1; @@ -623,35 +658,39 @@ static int label_boot(struct pxe_label *label) sprintf(ip_str, " ip=%s:%s:%s:%s", getenv("ipaddr"), getenv("serverip"), getenv("gatewayip"), getenv("netmask")); - len += strlen(ip_str); } +#ifdef CONFIG_CMD_NET if (label->ipappend & 0x2) { int err; strcpy(mac_str, " BOOTIF="); err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8); if (err < 0) mac_str[0] = '\0'; - len += strlen(mac_str); } +#endif - if (label->append) - len += strlen(label->append); + if ((label->ipappend & 0x3) || label->append) { + char bootargs[CONFIG_SYS_CBSIZE] = ""; + char finalbootargs[CONFIG_SYS_CBSIZE]; - if (len) { - bootargs = malloc(len + 1); - if (!bootargs) + if (strlen(label->append ?: "") + + strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) { + printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n", + strlen(label->append ?: ""), + strlen(ip_str), strlen(mac_str), + sizeof(bootargs)); return 1; - bootargs[0] = '\0'; + } + if (label->append) strcpy(bootargs, label->append); strcat(bootargs, ip_str); strcat(bootargs, mac_str); - setenv("bootargs", bootargs); - printf("append: %s\n", bootargs); - - free(bootargs); + cli_simple_process_macros(bootargs, finalbootargs); + setenv("bootargs", finalbootargs); + printf("append: %s\n", finalbootargs); } bootm_argv[1] = getenv("kernel_addr_r"); @@ -672,23 +711,84 @@ static int label_boot(struct pxe_label *label) bootm_argv[3] = getenv("fdt_addr_r"); /* if fdt label is defined then get fdt from server */ - if (bootm_argv[3] && label->fdt) { - if (get_relfile_envaddr(label->fdt, "fdt_addr_r") < 0) { - printf("Skipping %s for failure retrieving fdt\n", - label->name); - return 1; + if (bootm_argv[3]) { + char *fdtfile = NULL; + char *fdtfilefree = NULL; + + if (label->fdt) { + fdtfile = label->fdt; + } else if (label->fdtdir) { + char *f1, *f2, *f3, *f4, *slash; + + f1 = getenv("fdtfile"); + if (f1) { + f2 = ""; + f3 = ""; + f4 = ""; + } else { + /* + * For complex cases where this code doesn't + * generate the correct filename, the board + * code should set $fdtfile during early boot, + * or the boot scripts should set $fdtfile + * before invoking "pxe" or "sysboot". + */ + f1 = getenv("soc"); + f2 = "-"; + f3 = getenv("board"); + f4 = ".dtb"; + } + + len = strlen(label->fdtdir); + if (!len) + slash = "./"; + else if (label->fdtdir[len - 1] != '/') + slash = "/"; + else + slash = ""; + + len = strlen(label->fdtdir) + strlen(slash) + + strlen(f1) + strlen(f2) + strlen(f3) + + strlen(f4) + 1; + fdtfilefree = malloc(len); + if (!fdtfilefree) { + printf("malloc fail (FDT filename)\n"); + return 1; + } + + snprintf(fdtfilefree, len, "%s%s%s%s%s%s", + label->fdtdir, slash, f1, f2, f3, f4); + fdtfile = fdtfilefree; } - } else + + if (fdtfile) { + int err = get_relfile_envaddr(cmdtp, fdtfile, "fdt_addr_r"); + free(fdtfilefree); + if (err < 0) { + printf("Skipping %s for failure retrieving fdt\n", + label->name); + return 1; + } + } else { + bootm_argv[3] = NULL; + } + } + + if (!bootm_argv[3]) bootm_argv[3] = getenv("fdt_addr"); if (bootm_argv[3]) bootm_argc = 4; - do_bootm(NULL, 0, bootm_argc, bootm_argv); - + kernel_addr = genimg_get_kernel_addr(bootm_argv[1]); + buf = map_sysmem(kernel_addr, 0); + /* Try bootm for legacy and FIT format image */ + if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID) + do_bootm(cmdtp, 0, bootm_argc, bootm_argv); #ifdef CONFIG_CMD_BOOTZ - /* Try booting a zImage if do_bootm returns */ - do_bootz(NULL, 0, bootm_argc, bootm_argv); + /* Try booting a zImage */ + else + do_bootz(cmdtp, 0, bootm_argc, bootm_argv); #endif return 1; } @@ -713,6 +813,7 @@ enum token_type { T_PROMPT, T_INCLUDE, T_FDT, + T_FDTDIR, T_ONTIMEOUT, T_IPAPPEND, T_INVALID @@ -742,7 +843,10 @@ static const struct token keywords[] = { {"append", T_APPEND}, {"initrd", T_INITRD}, {"include", T_INCLUDE}, + {"devicetree", T_FDT}, {"fdt", T_FDT}, + {"devicetreedir", T_FDTDIR}, + {"fdtdir", T_FDTDIR}, {"ontimeout", T_ONTIMEOUT,}, {"ipappend", T_IPAPPEND,}, {NULL, T_INVALID} @@ -950,7 +1054,7 @@ static int parse_integer(char **c, int *dst) return 1; } -static int parse_pxefile_top(char *p, struct pxe_menu *cfg, int nest_level); +static int parse_pxefile_top(cmd_tbl_t *cmdtp, char *p, struct pxe_menu *cfg, int nest_level); /* * Parse an include statement, and retrieve and parse the file it mentions. @@ -960,7 +1064,7 @@ static int parse_pxefile_top(char *p, struct pxe_menu *cfg, int nest_level); * include, nest_level has already been incremented and doesn't need to be * incremented here. */ -static int handle_include(char **c, char *base, +static int handle_include(cmd_tbl_t *cmdtp, char **c, char *base, struct pxe_menu *cfg, int nest_level) { char *include_path; @@ -975,14 +1079,14 @@ static int handle_include(char **c, char *base, return err; } - err = get_pxe_file(include_path, base); + err = get_pxe_file(cmdtp, include_path, base); if (err < 0) { printf("Couldn't retrieve %s\n", include_path); return err; } - return parse_pxefile_top(base, cfg, nest_level); + return parse_pxefile_top(cmdtp, base, cfg, nest_level); } /* @@ -995,7 +1099,7 @@ static int handle_include(char **c, char *base, * nest_level should be 1 when parsing the top level pxe file, 2 when parsing * a file it includes, 3 when parsing a file included by that file, and so on. */ -static int parse_menu(char **c, struct pxe_menu *cfg, char *b, int nest_level) +static int parse_menu(cmd_tbl_t *cmdtp, char **c, struct pxe_menu *cfg, char *b, int nest_level) { struct token t; char *s = *c; @@ -1010,7 +1114,7 @@ static int parse_menu(char **c, struct pxe_menu *cfg, char *b, int nest_level) break; case T_INCLUDE: - err = handle_include(c, b + strlen(b) + 1, cfg, + err = handle_include(cmdtp, c, b + strlen(b) + 1, cfg, nest_level + 1); break; @@ -1131,6 +1235,11 @@ static int parse_label(char **c, struct pxe_menu *cfg) err = parse_sliteral(c, &label->fdt); break; + case T_FDTDIR: + if (!label->fdtdir) + err = parse_sliteral(c, &label->fdtdir); + break; + case T_LOCALBOOT: label->localboot = 1; err = parse_integer(c, &label->localboot_val); @@ -1172,7 +1281,7 @@ static int parse_label(char **c, struct pxe_menu *cfg) * * Returns 1 on success, < 0 on error. */ -static int parse_pxefile_top(char *p, struct pxe_menu *cfg, int nest_level) +static int parse_pxefile_top(cmd_tbl_t *cmdtp, char *p, struct pxe_menu *cfg, int nest_level) { struct token t; char *s, *b, *label_name; @@ -1194,7 +1303,7 @@ static int parse_pxefile_top(char *p, struct pxe_menu *cfg, int nest_level) switch (t.type) { case T_MENU: cfg->prompt = 1; - err = parse_menu(&p, cfg, b, nest_level); + err = parse_menu(cmdtp, &p, cfg, b, nest_level); break; case T_TIMEOUT: @@ -1219,7 +1328,7 @@ static int parse_pxefile_top(char *p, struct pxe_menu *cfg, int nest_level) break; case T_INCLUDE: - err = handle_include(&p, b + ALIGN(strlen(b), 4), cfg, + err = handle_include(cmdtp, &p, b + ALIGN(strlen(b), 4), cfg, nest_level + 1); break; @@ -1276,7 +1385,7 @@ static void destroy_pxe_menu(struct pxe_menu *cfg) * files it includes). The resulting pxe_menu struct can be free()'d by using * the destroy_pxe_menu() function. */ -static struct pxe_menu *parse_pxefile(char *menucfg) +static struct pxe_menu *parse_pxefile(cmd_tbl_t *cmdtp, char *menucfg) { struct pxe_menu *cfg; @@ -1289,7 +1398,7 @@ static struct pxe_menu *parse_pxefile(char *menucfg) INIT_LIST_HEAD(&cfg->labels); - if (parse_pxefile_top(menucfg, cfg, 1) < 0) { + if (parse_pxefile_top(cmdtp, menucfg, cfg, 1) < 0) { destroy_pxe_menu(cfg); return NULL; } @@ -1355,7 +1464,7 @@ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) /* * Try to boot any labels we have yet to attempt to boot. */ -static void boot_unattempted_labels(struct pxe_menu *cfg) +static void boot_unattempted_labels(cmd_tbl_t *cmdtp, struct pxe_menu *cfg) { struct list_head *pos; struct pxe_label *label; @@ -1364,7 +1473,7 @@ static void boot_unattempted_labels(struct pxe_menu *cfg) label = list_entry(pos, struct pxe_label, list); if (!label->attempted) - label_boot(label); + label_boot(cmdtp, label); } } @@ -1380,7 +1489,7 @@ static void boot_unattempted_labels(struct pxe_menu *cfg) * If this function returns, there weren't any labels that successfully * booted, or the user interrupted the menu selection via ctrl+c. */ -static void handle_pxe_menu(struct pxe_menu *cfg) +static void handle_pxe_menu(cmd_tbl_t *cmdtp, struct pxe_menu *cfg) { void *choice; struct menu *m; @@ -1406,16 +1515,17 @@ static void handle_pxe_menu(struct pxe_menu *cfg) */ if (err == 1) { - err = label_boot(choice); + err = label_boot(cmdtp, choice); if (!err) return; } else if (err != -ENOENT) { return; } - boot_unattempted_labels(cfg); + boot_unattempted_labels(cmdtp, cfg); } +#ifdef CONFIG_CMD_NET /* * Boots a system using a pxe file * @@ -1446,17 +1556,19 @@ do_pxe_boot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } - cfg = parse_pxefile((char *)(pxefile_addr_r)); + cfg = parse_pxefile(cmdtp, (char *)(pxefile_addr_r)); if (cfg == NULL) { printf("Error parsing config file\n"); return 1; } - handle_pxe_menu(cfg); + handle_pxe_menu(cmdtp, cfg); destroy_pxe_menu(cfg); + copy_filename(BootFile, "", sizeof(BootFile)); + return 0; } @@ -1465,13 +1577,15 @@ static cmd_tbl_t cmd_pxe_sub[] = { U_BOOT_CMD_MKENT(boot, 2, 1, do_pxe_boot, "", "") }; -int do_pxe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_pxe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cmd_tbl_t *cp; if (argc < 2) return CMD_RET_USAGE; + is_pxe = true; + /* drop initial "pxe" arg */ argc--; argv++; @@ -1490,13 +1604,14 @@ U_BOOT_CMD( "get - try to retrieve a pxe file using tftp\npxe " "boot [pxefile_addr_r] - boot from the pxe file at pxefile_addr_r\n" ); +#endif /* * Boots a system using a local disk syslinux/extlinux file * * Returns 0 on success, 1 on error. */ -int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long pxefile_addr_r; struct pxe_menu *cfg; @@ -1504,6 +1619,8 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *filename; int prompt = 0; + is_pxe = false; + if (strstr(argv[1], "-p")) { prompt = 1; argc--; @@ -1532,6 +1649,8 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) do_getfile = do_get_ext2; else if (strstr(argv[3], "fat")) do_getfile = do_get_fat; + else if (strstr(argv[3], "any")) + do_getfile = do_get_any; else { printf("Invalid filesystem: %s\n", argv[3]); return 1; @@ -1544,12 +1663,12 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } - if (get_pxe_file(filename, (void *)pxefile_addr_r) < 0) { + if (get_pxe_file(cmdtp, filename, (void *)pxefile_addr_r) < 0) { printf("Error reading config file\n"); return 1; } - cfg = parse_pxefile((char *)(pxefile_addr_r)); + cfg = parse_pxefile(cmdtp, (char *)(pxefile_addr_r)); if (cfg == NULL) { printf("Error parsing config file\n"); @@ -1559,7 +1678,7 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (prompt) cfg->prompt = 1; - handle_pxe_menu(cfg); + handle_pxe_menu(cmdtp, cfg); destroy_pxe_menu(cfg); @@ -1569,7 +1688,7 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( sysboot, 7, 1, do_sysboot, "command to get and boot from syslinux files", - "[-p] [addr] [filename]\n" - " - load and parse syslinux menu file 'filename' from ext2 or fat\n" - " filesystem on 'dev' on 'interface' to address 'addr'" + "[-p] [addr] [filename]\n" + " - load and parse syslinux menu file 'filename' from ext2, fat\n" + " or any filesystem on 'dev' on 'interface' to address 'addr'" ); diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c index b9d2449e33..887156486a 100644 --- a/common/cmd_reiser.c +++ b/common/cmd_reiser.c @@ -141,7 +141,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) filelen = reiserfs_open(filename); if (filelen < 0) { - printf("** File not found %s\n", filename); + printf("** File not found %s **\n", filename); return 1; } if ((count < filelen) && (count != 0)) { diff --git a/common/cmd_sandbox.c b/common/cmd_sandbox.c index 75eb23adf2..428696982e 100644 --- a/common/cmd_sandbox.c +++ b/common/cmd_sandbox.c @@ -6,11 +6,14 @@ #include #include +#include +#include +#include static int do_sandbox_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_load(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX, 16); + return do_load(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX); } static int do_sandbox_ls(cmd_tbl_t *cmdtp, int flag, int argc, @@ -22,13 +25,72 @@ static int do_sandbox_ls(cmd_tbl_t *cmdtp, int flag, int argc, static int do_sandbox_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_save(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX, 16); + return do_save(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX); +} + +static int do_sandbox_bind(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc < 2 || argc > 3) + return CMD_RET_USAGE; + char *ep; + char *dev_str = argv[1]; + char *file = argc >= 3 ? argv[2] : NULL; + int dev = simple_strtoul(dev_str, &ep, 16); + if (*ep) { + printf("** Bad device specification %s **\n", dev_str); + return CMD_RET_USAGE; + } + return host_dev_bind(dev, file); +} + +static int do_sandbox_info(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc < 1 || argc > 2) + return CMD_RET_USAGE; + int min_dev = 0; + int max_dev = CONFIG_HOST_MAX_DEVICES - 1; + if (argc >= 2) { + char *ep; + char *dev_str = argv[1]; + int dev = simple_strtoul(dev_str, &ep, 16); + if (*ep) { + printf("** Bad device specification %s **\n", dev_str); + return CMD_RET_USAGE; + } + min_dev = dev; + max_dev = dev; + } + int dev; + printf("%3s %12s %s\n", "dev", "blocks", "path"); + for (dev = min_dev; dev <= max_dev; dev++) { + block_dev_desc_t *blk_dev; + int ret; + + printf("%3d ", dev); + ret = host_get_dev_err(dev, &blk_dev); + if (ret) { + if (ret == -ENOENT) + puts("Not bound to a backing file\n"); + else if (ret == -ENODEV) + puts("Invalid host device number\n"); + + continue; + } + struct host_block_dev *host_dev = blk_dev->priv; + printf("%12lu %s\n", (unsigned long)blk_dev->lba, + host_dev->filename); + } + return 0; } static cmd_tbl_t cmd_sandbox_sub[] = { U_BOOT_CMD_MKENT(load, 7, 0, do_sandbox_load, "", ""), U_BOOT_CMD_MKENT(ls, 3, 0, do_sandbox_ls, "", ""), U_BOOT_CMD_MKENT(save, 6, 0, do_sandbox_save, "", ""), + U_BOOT_CMD_MKENT(bind, 3, 0, do_sandbox_bind, "", ""), + U_BOOT_CMD_MKENT(info, 3, 0, do_sandbox_info, "", ""), }; static int do_sandbox(cmd_tbl_t *cmdtp, int flag, int argc, @@ -52,9 +114,13 @@ static int do_sandbox(cmd_tbl_t *cmdtp, int flag, int argc, U_BOOT_CMD( sb, 8, 1, do_sandbox, "Miscellaneous sandbox commands", - "load host [ ] - " + "load hostfs - [ ] - " "load a file from host\n" - "sb ls host - list files on host\n" - "sb save host [] - " + "sb ls hostfs - - list files on host\n" + "sb save hostfs - [] - " "save a file to host\n" + "sb bind [] - bind \"host\" device to file\n" + "sb info [] - show device binding & info\n" + "sb commands use the \"hostfs\" device. The \"host\" device is used\n" + "with standard IO commands such as fatls or ext2load" ); diff --git a/common/cmd_sata.c b/common/cmd_sata.c index fc92131966..51f67033ae 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -48,6 +48,20 @@ int __sata_initialize(void) } int sata_initialize(void) __attribute__((weak,alias("__sata_initialize"))); +__weak int __sata_stop(void) +{ + int i, err = 0; + + for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) + err |= reset_sata(i); + + if (err) + printf("Could not reset some SATA devices\n"); + + return err; +} +int sata_stop(void) __attribute__((weak, alias("__sata_stop"))); + #ifdef CONFIG_PARTITIONS block_dev_desc_t *sata_get_dev(int dev) { @@ -59,8 +73,15 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int rc = 0; - if (argc == 2 && strcmp(argv[1], "init") == 0) + if (argc == 2 && strcmp(argv[1], "stop") == 0) + return sata_stop(); + + if (argc == 2 && strcmp(argv[1], "init") == 0) { + if (sata_curr_device != -1) + sata_stop(); + return sata_initialize(); + } /* If the user has not yet run `sata init`, do it now */ if (sata_curr_device == -1) @@ -185,6 +206,7 @@ U_BOOT_CMD( sata, 5, 1, do_sata, "SATA sub system", "init - init SATA sub system\n" + "sata stop - disable SATA sub system\n" "sata info - show available SATA devices\n" "sata device [dev] - show or set current device\n" "sata part [dev] - print partition table\n" diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 7b97dc9332..cbc107ea50 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include #include @@ -168,7 +169,9 @@ removable: scsi_curr_dev = -1; printf("Found %d device(s).\n", scsi_max_devs); +#ifndef CONFIG_SPL_BUILD setenv_ulong("scsidevs", scsi_max_devs); +#endif } int scsi_get_disk_count(void) @@ -389,7 +392,7 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, blks=0; } debug("scsi_read_ext: startblk " LBAF - ", blccnt %x buffer %lx\n", + ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr); if (scsi_exec(pccb) != true) { scsi_print_error(pccb); @@ -399,7 +402,7 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, buf_addr+=pccb->datalen; } while(blks!=0); debug("scsi_read_ext: end startblk " LBAF - ", blccnt %x buffer %lx\n", start, smallblks, buf_addr); + ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr); return(blkcnt); } @@ -443,7 +446,7 @@ static ulong scsi_write(int device, lbaint_t blknr, start += blks; blks = 0; } - debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n", + debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n", __func__, start, smallblks, buf_addr); if (scsi_exec(pccb) != true) { scsi_print_error(pccb); @@ -452,7 +455,7 @@ static ulong scsi_write(int device, lbaint_t blknr, } buf_addr += pccb->datalen; } while (blks != 0); - debug("%s: end startblk " LBAF ", blccnt %x buffer %lx\n", + debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n", __func__, start, smallblks, buf_addr); return blkcnt; } diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c index 1fc080b9b5..926339b9f1 100644 --- a/common/cmd_setexpr.c +++ b/common/cmd_setexpr.c @@ -2,7 +2,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. * Copyright 2013 Wolfgang Denk * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 19b0dc9f43..5c788e96bd 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -2,32 +2,22 @@ * Command for accessing SPI flash. * * Copyright (C) 2008 Atmel Corporation - * Licensed under the GPL-2 or later. + * + * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include #include +#include #include #include - -#ifndef CONFIG_SF_DEFAULT_SPEED -# define CONFIG_SF_DEFAULT_SPEED 1000000 -#endif -#ifndef CONFIG_SF_DEFAULT_MODE -# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -#endif -#ifndef CONFIG_SF_DEFAULT_CS -# define CONFIG_SF_DEFAULT_CS 0 -#endif -#ifndef CONFIG_SF_DEFAULT_BUS -# define CONFIG_SF_DEFAULT_BUS 0 -#endif +#include static struct spi_flash *flash; - /* * This function computes the length argument for the erase command. * The length on which the command is to operate can be given in two forms: @@ -80,9 +70,9 @@ static ulong bytes_per_second(unsigned int len, ulong start_ms) { /* less accurate but avoids overflow */ if (len >= ((unsigned int) -1) / 1024) - return len / (max(get_timer(start_ms) / 1024, 1)); + return len / (max(get_timer(start_ms) / 1024, 1UL)); else - return 1024 * len / max(get_timer(start_ms), 1); + return 1024 * len / max(get_timer(start_ms), 1UL); } static int do_spi_flash_probe(int argc, char * const argv[]) @@ -92,7 +82,12 @@ static int do_spi_flash_probe(int argc, char * const argv[]) unsigned int speed = CONFIG_SF_DEFAULT_SPEED; unsigned int mode = CONFIG_SF_DEFAULT_MODE; char *endp; +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new, *bus_dev; + int ret; +#else struct spi_flash *new; +#endif if (argc >= 2) { cs = simple_strtoul(argv[1], &endp, 0); @@ -120,6 +115,23 @@ static int do_spi_flash_probe(int argc, char * const argv[]) return -1; } +#ifdef CONFIG_DM_SPI_FLASH + /* Remove the old device, otherwise probe will just be a nop */ + ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new); + if (!ret) { + device_remove(new); + device_unbind(new); + } + flash = NULL; + ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, &new); + if (ret) { + printf("Failed to initialize SPI flash at %u:%u (error %d)\n", + bus, cs, ret); + return 1; + } + + flash = new->uclass_priv; +#else new = spi_flash_probe(bus, cs, speed, mode); if (!new) { printf("Failed to initialize SPI flash at %u:%u\n", bus, cs); @@ -129,6 +141,7 @@ static int do_spi_flash_probe(int argc, char * const argv[]) if (flash) spi_flash_free(flash); flash = new; +#endif return 0; } @@ -151,19 +164,31 @@ static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset, size_t len, const char *buf, char *cmp_buf, size_t *skipped) { debug("offset=%#x, sector_size=%#x, len=%#zx\n", - offset, flash->sector_size, len); - if (spi_flash_read(flash, offset, len, cmp_buf)) + offset, flash->sector_size, len); + /* Read the entire sector so to allow for rewriting */ + if (spi_flash_read(flash, offset, flash->sector_size, cmp_buf)) return "read"; + /* Compare only what is meaningful (len) */ if (memcmp(cmp_buf, buf, len) == 0) { debug("Skip region %x size %zx: no change\n", - offset, len); + offset, len); *skipped += len; return NULL; } - if (spi_flash_erase(flash, offset, len)) + /* Erase the entire sector */ + if (spi_flash_erase(flash, offset, flash->sector_size)) return "erase"; + /* Write the initial part of the block from the source */ if (spi_flash_write(flash, offset, len, buf)) return "write"; + /* If it's a partial sector, rewrite the existing part */ + if (len != flash->sector_size) { + /* Rewrite the original data to the end of the sector */ + if (spi_flash_write(flash, offset + len, + flash->sector_size - len, &cmp_buf[len])) + return "write"; + } + return NULL; } @@ -197,10 +222,10 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset, ulong last_update = get_timer(0); for (; buf < end && !err_oper; buf += todo, offset += todo) { - todo = min(end - buf, flash->sector_size); + todo = min_t(size_t, end - buf, flash->sector_size); if (get_timer(last_update) > 100) { printf(" \rUpdating, %zu%% %lu B/s", - 100 - (end - buf) / scale, + 100 - (end - buf) / scale, bytes_per_second(buf - start_buf, start_time)); last_update = get_timer(0); @@ -220,9 +245,9 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset, delta = get_timer(start_time); printf("%zu bytes written, %zu bytes skipped", len - skipped, - skipped); + skipped); printf(" in %ld.%lds, speed %ld B/s\n", - delta / 1000, delta % 1000, bytes_per_second(len, start_time)); + delta / 1000, delta % 1000, bytes_per_second(len, start_time)); return 0; } @@ -252,7 +277,7 @@ static int do_spi_flash_read_write(int argc, char * const argv[]) /* Consistency checking */ if (offset + len > flash->size) { printf("ERROR: attempting %s past flash size (%#x)\n", - argv[0], flash->size); + argv[0], flash->size); return 1; } @@ -262,9 +287,9 @@ static int do_spi_flash_read_write(int argc, char * const argv[]) return 1; } - if (strcmp(argv[0], "update") == 0) + if (strcmp(argv[0], "update") == 0) { ret = spi_flash_update(flash, offset, len, buf); - else if (strncmp(argv[0], "read", 4) == 0 || + } else if (strncmp(argv[0], "read", 4) == 0 || strncmp(argv[0], "write", 5) == 0) { int read; @@ -275,7 +300,7 @@ static int do_spi_flash_read_write(int argc, char * const argv[]) ret = spi_flash_write(flash, offset, len, buf); printf("SF: %zu bytes @ %#x %s: %s\n", (size_t)len, (u32)offset, - read ? "Read" : "Written", ret ? "ERROR" : "OK"); + read ? "Read" : "Written", ret ? "ERROR" : "OK"); } unmap_physmem(buf, len); @@ -304,13 +329,13 @@ static int do_spi_flash_erase(int argc, char * const argv[]) /* Consistency checking */ if (offset + len > flash->size) { printf("ERROR: attempting %s past flash size (%#x)\n", - argv[0], flash->size); + argv[0], flash->size); return 1; } ret = spi_flash_erase(flash, offset, len); printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)len, (u32)offset, - ret ? "ERROR" : "OK"); + ret ? "ERROR" : "OK"); return ret == 0 ? 0 : 1; } @@ -345,7 +370,8 @@ static void show_time(struct test_info *test, int stage) int bps; /* Bits per second */ speed = (long long)test->bytes * 1000; - do_div(speed, test->time_ms[stage] * 1024); + if (test->time_ms[stage]) + do_div(speed, test->time_ms[stage] * 1024); bps = speed * 8; printf("%d %s: %d ticks, %d KiB/s %d.%03d Mbps\n", stage, @@ -394,7 +420,8 @@ static int spi_flash_test(struct spi_flash *flash, uint8_t *buf, ulong len, for (i = 0; i < len; i++) { if (vbuf[i] != 0xff) { printf("Check failed at %d\n", i); - print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0); + print_buffer(i, vbuf + i, 1, + min_t(uint, len - i, 0x40), 0); return -1; } } @@ -416,9 +443,11 @@ static int spi_flash_test(struct spi_flash *flash, uint8_t *buf, ulong len, for (i = 0; i < len; i++) { if (buf[i] != vbuf[i]) { printf("Verify failed at %d, good data:\n", i); - print_buffer(i, buf + i, 1, min(len - i, 0x40), 0); + print_buffer(i, buf + i, 1, + min_t(uint, len - i, 0x40), 0); printf("Bad data:\n"); - print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0); + print_buffer(i, vbuf + i, 1, + min_t(uint, len - i, 0x40), 0); return -1; } } @@ -433,11 +462,13 @@ static int do_spi_flash_test(int argc, char * const argv[]) { unsigned long offset; unsigned long len; - uint8_t *buf = (uint8_t *)CONFIG_SYS_TEXT_BASE; + uint8_t *buf, *from; char *endp; uint8_t *vbuf; int ret; + if (argc < 3) + return -1; offset = simple_strtoul(argv[1], &endp, 16); if (*argv[1] == 0 || *endp != 0) return -1; @@ -447,17 +478,18 @@ static int do_spi_flash_test(int argc, char * const argv[]) vbuf = malloc(len); if (!vbuf) { - printf("Cannot allocate memory\n"); + printf("Cannot allocate memory (%lu bytes)\n", len); return 1; } buf = malloc(len); if (!buf) { free(vbuf); - printf("Cannot allocate memory\n"); + printf("Cannot allocate memory (%lu bytes)\n", len); return 1; } - memcpy(buf, (char *)CONFIG_SYS_TEXT_BASE, len); + from = map_sysmem(CONFIG_SYS_TEXT_BASE, 0); + memcpy(buf, from, len); ret = spi_flash_test(flash, buf, len, offset, vbuf); free(vbuf); free(buf); @@ -470,7 +502,8 @@ static int do_spi_flash_test(int argc, char * const argv[]) } #endif /* CONFIG_CMD_SF_TEST */ -static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { const char *cmd; int ret; @@ -526,7 +559,7 @@ U_BOOT_CMD( "SPI flash sub-system", "probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus\n" " and chip select\n" - "sf read addr offset len - read `len' bytes starting at\n" + "sf read addr offset len - read `len' bytes starting at\n" " `offset' to memory at `addr'\n" "sf write addr offset len - write `len' bytes from memory\n" " at `addr' to flash at `offset'\n" diff --git a/common/cmd_sha1sum.c b/common/cmd_sha1sum.c index 644b9a0e66..783ea2e32d 100644 --- a/common/cmd_sha1sum.c +++ b/common/cmd_sha1sum.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/common/cmd_source.c b/common/cmd_source.c index 54ffd16470..6881bc9ddd 100644 --- a/common/cmd_source.c +++ b/common/cmd_source.c @@ -29,7 +29,9 @@ int source (ulong addr, const char *fit_uname) { ulong len; +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) const image_header_t *hdr; +#endif ulong *data; int verify; void *buf; @@ -44,6 +46,7 @@ source (ulong addr, const char *fit_uname) buf = map_sysmem(addr, 0); switch (genimg_get_format(buf)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: hdr = buf; @@ -84,6 +87,7 @@ source (ulong addr, const char *fit_uname) */ while (*data++); break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: if (fit_uname == NULL) { @@ -138,8 +142,7 @@ source (ulong addr, const char *fit_uname) /**************************************************/ #if defined(CONFIG_CMD_SOURCE) -int -do_source (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_source(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr; int rcode; diff --git a/common/cmd_spi.c b/common/cmd_spi.c index 3c8e913be5..64c3ffcf42 100644 --- a/common/cmd_spi.c +++ b/common/cmd_spi.c @@ -11,6 +11,8 @@ #include #include +#include +#include #include /*----------------------------------------------------------------------- @@ -38,6 +40,57 @@ static int bitlen; static uchar dout[MAX_SPI_BYTES]; static uchar din[MAX_SPI_BYTES]; +static int do_spi_xfer(int bus, int cs) +{ + struct spi_slave *slave; + int ret = 0; + +#ifdef CONFIG_DM_SPI + char name[30], *str; + struct udevice *dev; + + snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); + str = strdup(name); + ret = spi_get_bus_and_cs(bus, cs, 1000000, mode, "spi_generic_drv", + str, &dev, &slave); + if (ret) + return ret; +#else + slave = spi_setup_slave(bus, cs, 1000000, mode); + if (!slave) { + printf("Invalid device %d:%d\n", bus, cs); + return -EINVAL; + } +#endif + + ret = spi_claim_bus(slave); + if (ret) + goto done; + ret = spi_xfer(slave, bitlen, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END); +#ifndef CONFIG_DM_SPI + /* We don't get an error code in this case */ + if (ret) + ret = -EIO; +#endif + if (ret) { + printf("Error %d during SPI transaction\n", ret); + } else { + int j; + + for (j = 0; j < ((bitlen + 7) / 8); j++) + printf("%02X", din[j]); + printf("\n"); + } +done: + spi_release_bus(slave); +#ifndef CONFIG_DM_SPI + spi_free_slave(slave); +#endif + + return ret; +} + /* * SPI read/write * @@ -51,11 +104,9 @@ static uchar din[MAX_SPI_BYTES]; int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct spi_slave *slave; char *cp = 0; uchar tmp; int j; - int rcode = 0; /* * We use the last specified parameters, unless new ones are @@ -103,27 +154,10 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } - slave = spi_setup_slave(bus, cs, 1000000, mode); - if (!slave) { - printf("Invalid device %d:%d\n", bus, cs); + if (do_spi_xfer(bus, cs)) return 1; - } - - spi_claim_bus(slave); - if(spi_xfer(slave, bitlen, dout, din, - SPI_XFER_BEGIN | SPI_XFER_END) != 0) { - printf("Error during SPI transaction\n"); - rcode = 1; - } else { - for(j = 0; j < ((bitlen + 7) / 8); j++) { - printf("%02X", din[j]); - } - printf("\n"); - } - spi_release_bus(slave); - spi_free_slave(slave); - return rcode; + return 0; } /***************************************************/ diff --git a/common/cmd_test.c b/common/cmd_test.c index bacc368406..c93fe78231 100644 --- a/common/cmd_test.c +++ b/common/cmd_test.c @@ -16,11 +16,54 @@ #include #include +#include + +#define OP_INVALID 0 +#define OP_NOT 1 +#define OP_OR 2 +#define OP_AND 3 +#define OP_STR_EMPTY 4 +#define OP_STR_NEMPTY 5 +#define OP_STR_EQ 6 +#define OP_STR_NEQ 7 +#define OP_STR_LT 8 +#define OP_STR_GT 9 +#define OP_INT_EQ 10 +#define OP_INT_NEQ 11 +#define OP_INT_LT 12 +#define OP_INT_LE 13 +#define OP_INT_GT 14 +#define OP_INT_GE 15 +#define OP_FILE_EXISTS 16 + +const struct { + int arg; + const char *str; + int op; + int adv; +} op_adv[] = { + {1, "=", OP_STR_EQ, 3}, + {1, "!=", OP_STR_NEQ, 3}, + {1, "<", OP_STR_LT, 3}, + {1, ">", OP_STR_GT, 3}, + {1, "-eq", OP_INT_EQ, 3}, + {1, "-ne", OP_INT_NEQ, 3}, + {1, "-lt", OP_INT_LT, 3}, + {1, "-le", OP_INT_LE, 3}, + {1, "-gt", OP_INT_GT, 3}, + {1, "-ge", OP_INT_GE, 3}, + {0, "!", OP_NOT, 1}, + {0, "-o", OP_OR, 1}, + {0, "-a", OP_AND, 1}, + {0, "-z", OP_STR_EMPTY, 2}, + {0, "-n", OP_STR_NEMPTY, 2}, + {0, "-e", OP_FILE_EXISTS, 4}, +}; static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char * const *ap; - int left, adv, expr, last_expr, neg, last_cmp; + int i, op, left, adv, expr, last_expr, last_unop, last_binop; /* args? */ if (argc < 3) @@ -35,101 +78,112 @@ static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif - last_expr = 0; - left = argc - 1; ap = argv + 1; - if (left > 0 && strcmp(ap[0], "!") == 0) { - neg = 1; - ap++; - left--; - } else - neg = 0; - - expr = -1; - last_cmp = -1; + left = argc - 1; + ap = argv + 1; + expr = 0; + last_unop = OP_INVALID; + last_binop = OP_INVALID; last_expr = -1; while (left > 0) { - - if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0) - adv = 1; - else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0) - adv = 2; - else - adv = 3; - + for (i = 0; i < ARRAY_SIZE(op_adv); i++) { + if (left <= op_adv[i].arg) + continue; + if (!strcmp(ap[op_adv[i].arg], op_adv[i].str)) { + op = op_adv[i].op; + adv = op_adv[i].adv; + break; + } + } + if (i == ARRAY_SIZE(op_adv)) { + expr = 1; + break; + } if (left < adv) { expr = 1; break; } - if (adv == 1) { - if (strcmp(ap[0], "-o") == 0) { - last_expr = expr; - last_cmp = 0; - } else if (strcmp(ap[0], "-a") == 0) { - last_expr = expr; - last_cmp = 1; - } else { - expr = 1; - break; - } + switch (op) { + case OP_STR_EMPTY: + expr = strlen(ap[1]) == 0 ? 1 : 0; + break; + case OP_STR_NEMPTY: + expr = strlen(ap[1]) == 0 ? 0 : 1; + break; + case OP_STR_EQ: + expr = strcmp(ap[0], ap[2]) == 0; + break; + case OP_STR_NEQ: + expr = strcmp(ap[0], ap[2]) != 0; + break; + case OP_STR_LT: + expr = strcmp(ap[0], ap[2]) < 0; + break; + case OP_STR_GT: + expr = strcmp(ap[0], ap[2]) > 0; + break; + case OP_INT_EQ: + expr = simple_strtol(ap[0], NULL, 10) == + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_NEQ: + expr = simple_strtol(ap[0], NULL, 10) != + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_LT: + expr = simple_strtol(ap[0], NULL, 10) < + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_LE: + expr = simple_strtol(ap[0], NULL, 10) <= + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_GT: + expr = simple_strtol(ap[0], NULL, 10) > + simple_strtol(ap[2], NULL, 10); + break; + case OP_INT_GE: + expr = simple_strtol(ap[0], NULL, 10) >= + simple_strtol(ap[2], NULL, 10); + break; + case OP_FILE_EXISTS: + expr = file_exists(ap[1], ap[2], ap[3], FS_TYPE_ANY); + break; } - if (adv == 2) { - if (strcmp(ap[0], "-z") == 0) - expr = strlen(ap[1]) == 0 ? 1 : 0; - else if (strcmp(ap[0], "-n") == 0) - expr = strlen(ap[1]) == 0 ? 0 : 1; - else { - expr = 1; - break; + switch (op) { + case OP_OR: + last_expr = expr; + last_binop = OP_OR; + break; + case OP_AND: + last_expr = expr; + last_binop = OP_AND; + break; + case OP_NOT: + if (last_unop == OP_NOT) + last_unop = OP_INVALID; + else + last_unop = OP_NOT; + break; + default: + if (last_unop == OP_NOT) { + expr = !expr; + last_unop = OP_INVALID; } - if (last_cmp == 0) + if (last_binop == OP_OR) expr = last_expr || expr; - else if (last_cmp == 1) + else if (last_binop == OP_AND) expr = last_expr && expr; - last_cmp = -1; - } - - if (adv == 3) { - if (strcmp(ap[1], "=") == 0) - expr = strcmp(ap[0], ap[2]) == 0; - else if (strcmp(ap[1], "!=") == 0) - expr = strcmp(ap[0], ap[2]) != 0; - else if (strcmp(ap[1], ">") == 0) - expr = strcmp(ap[0], ap[2]) > 0; - else if (strcmp(ap[1], "<") == 0) - expr = strcmp(ap[0], ap[2]) < 0; - else if (strcmp(ap[1], "-eq") == 0) - expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-ne") == 0) - expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-lt") == 0) - expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-le") == 0) - expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-gt") == 0) - expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10); - else if (strcmp(ap[1], "-ge") == 0) - expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10); - else { - expr = 1; - break; - } + last_binop = OP_INVALID; - if (last_cmp == 0) - expr = last_expr || expr; - else if (last_cmp == 1) - expr = last_expr && expr; - last_cmp = -1; + break; } ap += adv; left -= adv; } - if (neg) - expr = !expr; - expr = !expr; debug (": returns %d\n", expr); diff --git a/common/cmd_thordown.c b/common/cmd_thordown.c new file mode 100644 index 0000000000..8ed1dc6f9e --- /dev/null +++ b/common/cmd_thordown.c @@ -0,0 +1,71 @@ +/* + * cmd_thordown.c -- USB TIZEN "THOR" Downloader gadget + * + * Copyright (C) 2013 Lukasz Majewski + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int do_thor_down(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 4) + return CMD_RET_USAGE; + + char *usb_controller = argv[1]; + char *interface = argv[2]; + char *devstring = argv[3]; + + int ret; + + puts("TIZEN \"THOR\" Downloader\n"); + + ret = dfu_init_env_entities(interface, devstring); + if (ret) + goto done; + + int controller_index = simple_strtoul(usb_controller, NULL, 0); + ret = board_usb_init(controller_index, USB_INIT_DEVICE); + if (ret) { + error("USB init failed: %d", ret); + ret = CMD_RET_FAILURE; + goto exit; + } + + g_dnl_register("usb_dnl_thor"); + + ret = thor_init(); + if (ret) { + error("THOR DOWNLOAD failed: %d", ret); + ret = CMD_RET_FAILURE; + goto exit; + } + + ret = thor_handle(); + if (ret) { + error("THOR failed: %d", ret); + ret = CMD_RET_FAILURE; + goto exit; + } + +exit: + g_dnl_unregister(); +done: + dfu_free_entities(); + + return ret; +} + +U_BOOT_CMD(thordown, CONFIG_SYS_MAXARGS, 1, do_thor_down, + "TIZEN \"THOR\" downloader", + " \n" + " - device software upgrade via LTHOR TIZEN dowload\n" + " program via on device ,\n" + " attached to interface \n" +); diff --git a/common/cmd_time.c b/common/cmd_time.c index 5180cb46a8..de57e3b9dd 100644 --- a/common/cmd_time.c +++ b/common/cmd_time.c @@ -21,8 +21,7 @@ static void report_time(ulong cycles) printf("\ntime:"); if (minutes) printf(" %lu minutes,", minutes); - printf(" %lu.%03lu seconds, %lu ticks\n", - seconds, milliseconds, cycles); + printf(" %lu.%03lu seconds\n", seconds, milliseconds); } static int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/common/cmd_tsi148.c b/common/cmd_tsi148.c index 317ba50fd1..dc488b2b3e 100644 --- a/common/cmd_tsi148.c +++ b/common/cmd_tsi148.c @@ -5,7 +5,7 @@ * * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 5ba4feb485..6c8570377e 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -50,33 +51,6 @@ int ubifs_is_mounted(void); void cmd_ubifs_umount(void); #endif -static void ubi_dump_vol_info(const struct ubi_volume *vol) -{ - ubi_msg("volume information dump:"); - ubi_msg("vol_id %d", vol->vol_id); - ubi_msg("reserved_pebs %d", vol->reserved_pebs); - ubi_msg("alignment %d", vol->alignment); - ubi_msg("data_pad %d", vol->data_pad); - ubi_msg("vol_type %d", vol->vol_type); - ubi_msg("name_len %d", vol->name_len); - ubi_msg("usable_leb_size %d", vol->usable_leb_size); - ubi_msg("used_ebs %d", vol->used_ebs); - ubi_msg("used_bytes %lld", vol->used_bytes); - ubi_msg("last_eb_bytes %d", vol->last_eb_bytes); - ubi_msg("corrupted %d", vol->corrupted); - ubi_msg("upd_marker %d", vol->upd_marker); - - if (vol->name_len <= UBI_VOL_NAME_MAX && - strnlen(vol->name, vol->name_len + 1) == vol->name_len) { - ubi_msg("name %s", vol->name); - } else { - ubi_msg("the 1st 5 characters of the name: %c%c%c%c%c", - vol->name[0], vol->name[1], vol->name[2], - vol->name[3], vol->name[4]); - } - printf("\n"); -} - static void display_volume_info(struct ubi_device *ubi) { int i; @@ -123,6 +97,27 @@ static int ubi_info(int layout) return 0; } +static int ubi_check_volumename(const struct ubi_volume *vol, char *name) +{ + return strcmp(vol->name, name); +} + +static int ubi_check(char *name) +{ + int i; + + for (i = 0; i < (ubi->vtbl_slots + 1); i++) { + if (!ubi->volumes[i]) + continue; /* Empty record */ + + if (!ubi_check_volumename(ubi->volumes[i], name)) + return 0; + } + + return -EEXIST; +} + + static int verify_mkvol_req(const struct ubi_device *ubi, const struct ubi_mkvol_req *req) { @@ -167,7 +162,7 @@ bad: return err; } -static int ubi_create_vol(char *volume, int size, int dynamic) +static int ubi_create_vol(char *volume, int64_t size, int dynamic) { struct ubi_mkvol_req req; int err; @@ -191,7 +186,7 @@ static int ubi_create_vol(char *volume, int size, int dynamic) printf("verify_mkvol_req failed %d\n", err); return err; } - printf("Creating %s volume %s of size %d\n", + printf("Creating %s volume %s of size %lld\n", dynamic ? "dynamic" : "static", volume, size); /* Call real ubi create volume */ return ubi_create_volume(ubi, &req); @@ -266,28 +261,15 @@ out_err: return err; } -int ubi_volume_write(char *volume, void *buf, size_t size) +static int ubi_volume_continue_write(char *volume, void *buf, size_t size) { int err = 1; - int rsvd_bytes = 0; struct ubi_volume *vol; vol = ubi_find_volume(volume); if (vol == NULL) return ENODEV; - rsvd_bytes = vol->reserved_pebs * (ubi->leb_size - vol->data_pad); - if (size < 0 || size > rsvd_bytes) { - printf("size > volume size! Aborting!\n"); - return EINVAL; - } - - err = ubi_start_update(ubi, vol, size); - if (err < 0) { - printf("Cannot start volume update\n"); - return -err; - } - err = ubi_more_update_data(ubi, vol, buf, size); if (err < 0) { printf("Couldnt or partially wrote data\n"); @@ -314,6 +296,37 @@ int ubi_volume_write(char *volume, void *buf, size_t size) return 0; } +int ubi_volume_begin_write(char *volume, void *buf, size_t size, + size_t full_size) +{ + int err = 1; + int rsvd_bytes = 0; + struct ubi_volume *vol; + + vol = ubi_find_volume(volume); + if (vol == NULL) + return ENODEV; + + rsvd_bytes = vol->reserved_pebs * (ubi->leb_size - vol->data_pad); + if (size < 0 || size > rsvd_bytes) { + printf("size > volume size! Aborting!\n"); + return EINVAL; + } + + err = ubi_start_update(ubi, vol, full_size); + if (err < 0) { + printf("Cannot start volume update\n"); + return -err; + } + + return ubi_volume_continue_write(volume, buf, size); +} + +int ubi_volume_write(char *volume, void *buf, size_t size) +{ + return ubi_volume_begin_write(volume, buf, size, size); +} + int ubi_volume_read(char *volume, char *buf, size_t size) { int err, lnum, off, len, tbuf_size; @@ -498,7 +511,7 @@ int ubi_part(char *part_name, const char *vid_header_offset) static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - size_t size = 0; + int64_t size = 0; ulong addr = 0; if (argc < 2) @@ -540,6 +553,14 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return ubi_info(layout); } + if (strcmp(argv[1], "check") == 0) { + if (argc > 2) + return ubi_check(argv[2]); + + printf("Error, no volume name passed\n"); + return 1; + } + if (strncmp(argv[1], "create", 6) == 0) { int dynamic = 1; /* default: dynamic volume */ @@ -558,13 +579,13 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } /* E.g., create volume size */ if (argc == 4) { - size = simple_strtoul(argv[3], NULL, 16); + size = simple_strtoull(argv[3], NULL, 16); argc--; } /* Use maximum available size */ if (!size) { - size = ubi->avail_pebs * ubi->leb_size; - printf("No size specified -> Using max size (%u)\n", size); + size = (int64_t)ubi->avail_pebs * ubi->leb_size; + printf("No size specified -> Using max size (%lld)\n", size); } /* E.g., create volume */ if (argc == 3) @@ -588,9 +609,22 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(argv[2], NULL, 16); size = simple_strtoul(argv[4], NULL, 16); - ret = ubi_volume_write(argv[3], (void *)addr, size); + if (strlen(argv[1]) == 10 && + strncmp(argv[1] + 5, ".part", 5) == 0) { + if (argc < 6) { + ret = ubi_volume_continue_write(argv[3], + (void *)addr, size); + } else { + size_t full_size; + full_size = simple_strtoul(argv[5], NULL, 16); + ret = ubi_volume_begin_write(argv[3], + (void *)addr, size, full_size); + } + } else { + ret = ubi_volume_write(argv[3], (void *)addr, size); + } if (!ret) { - printf("%d bytes written to volume %s\n", size, + printf("%lld bytes written to volume %s\n", size, argv[3]); } @@ -613,7 +647,7 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (argc == 3) { - printf("Read %d bytes from volume %s to %lx\n", size, + printf("Read %lld bytes from volume %s to %lx\n", size, argv[3], addr); return ubi_volume_read(argv[3], (char *)addr, size); @@ -632,10 +666,14 @@ U_BOOT_CMD( " header offset)\n" "ubi info [l[ayout]]" " - Display volume and ubi layout information\n" + "ubi check volumename" + " - check if volumename exists\n" "ubi create[vol] volume [size] [type]" " - create volume name with size\n" "ubi write[vol] address volume size" " - Write volume from address with size\n" + "ubi write.part address volume size [fullsize]\n" + " - Write part of a volume from address\n" "ubi read[vol] address volume [size]" " - Read volume to address with size\n" "ubi remove[vol] volume" diff --git a/common/cmd_ubifs.c b/common/cmd_ubifs.c index eba54fd004..8e9a4e5038 100644 --- a/common/cmd_ubifs.c +++ b/common/cmd_ubifs.c @@ -21,16 +21,8 @@ static int ubifs_initialized; static int ubifs_mounted; -extern struct super_block *ubifs_sb; - -/* Prototypes */ -int ubifs_init(void); -int ubifs_mount(char *vol_name); -void ubifs_umount(struct ubifs_info *c); -int ubifs_ls(char *dir_name); -int ubifs_load(char *filename, u32 addr, u32 size); - -int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { char *vol_name; int ret; @@ -46,7 +38,7 @@ int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ubifs_initialized = 1; } - ret = ubifs_mount(vol_name); + ret = uboot_ubifs_mount(vol_name); if (ret) return -1; @@ -74,7 +66,8 @@ void cmd_ubifs_umount(void) ubifs_initialized = 0; } -int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { if (argc != 1) return CMD_RET_USAGE; @@ -89,7 +82,8 @@ int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { char *filename = "/"; int ret; @@ -104,13 +98,16 @@ int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) debug("Using filename %s\n", filename); ret = ubifs_ls(filename); - if (ret) - printf("%s not found!\n", filename); + if (ret) { + printf("** File not found %s **\n", filename); + ret = CMD_RET_FAILURE; + } return ret; } -int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { char *filename; char *endp; @@ -140,8 +137,10 @@ int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) debug("Loading file '%s' to address 0x%08x (size %d)\n", filename, addr, size); ret = ubifs_load(filename, addr, size); - if (ret) - printf("%s not found!\n", filename); + if (ret) { + printf("** File not found %s **\n", filename); + ret = CMD_RET_FAILURE; + } return ret; } diff --git a/common/cmd_universe.c b/common/cmd_universe.c index ad15613845..c9310363f1 100644 --- a/common/cmd_universe.c +++ b/common/cmd_universe.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 2519497dad..27813f0d7a 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -430,6 +430,36 @@ static int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_USB_STORAGE */ +static int do_usb_stop_keyboard(int force) +{ +#ifdef CONFIG_USB_KEYBOARD + if (usb_kbd_deregister(force) != 0) { + printf("USB not stopped: usbkbd still using USB\n"); + return 1; + } +#endif + return 0; +} + +static void do_usb_start(void) +{ + bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start"); + + if (usb_init() < 0) + return; + +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + usb_stor_curr_dev = usb_stor_scan(1); +#endif +#ifdef CONFIG_USB_HOST_ETHER + /* try to recognize ethernet devices immediately */ + usb_ether_curr_dev = usb_host_eth_scan(1); +#endif +#ifdef CONFIG_USB_KEYBOARD + drv_usb_kbd_init(); +#endif +} /****************************************************************************** * usb command intepreter @@ -447,40 +477,27 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc < 2) return CMD_RET_USAGE; - if ((strncmp(argv[1], "reset", 5) == 0) || - (strncmp(argv[1], "start", 5) == 0)) { - bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start"); + if (strncmp(argv[1], "start", 5) == 0) { + if (usb_started) + return 0; /* Already started */ + printf("starting USB...\n"); + do_usb_start(); + return 0; + } + + if (strncmp(argv[1], "reset", 5) == 0) { + printf("resetting USB...\n"); + if (do_usb_stop_keyboard(1) != 0) + return 1; usb_stop(); - printf("(Re)start USB...\n"); - if (usb_init() >= 0) { -#ifdef CONFIG_USB_STORAGE - /* try to recognize storage devices immediately */ - usb_stor_curr_dev = usb_stor_scan(1); -#endif -#ifdef CONFIG_USB_HOST_ETHER - /* try to recognize ethernet devices immediately */ - usb_ether_curr_dev = usb_host_eth_scan(1); -#endif -#ifdef CONFIG_USB_KEYBOARD - drv_usb_kbd_init(); -#endif - } + do_usb_start(); return 0; } if (strncmp(argv[1], "stop", 4) == 0) { -#ifdef CONFIG_USB_KEYBOARD - if (argc == 2) { - if (usb_kbd_deregister() != 0) { - printf("USB not stopped: usbkbd still" - " using USB\n"); - return 1; - } - } else { - /* forced stop, switch console in to serial */ + if (argc != 2) console_assign(stdin, "serial"); - usb_kbd_deregister(); - } -#endif + if (do_usb_stop_keyboard(0) != 0) + return 1; printf("stopping USB..\n"); usb_stop(); return 0; diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c index 33a4715005..2c879ea083 100644 --- a/common/cmd_usb_mass_storage.c +++ b/common/cmd_usb_mass_storage.c @@ -9,65 +9,156 @@ #include #include #include +#include +#include #include +static int ums_read_sector(struct ums *ums_dev, + ulong start, lbaint_t blkcnt, void *buf) +{ + block_dev_desc_t *block_dev = ums_dev->block_dev; + lbaint_t blkstart = start + ums_dev->start_sector; + int dev_num = block_dev->dev; + + return block_dev->block_read(dev_num, blkstart, blkcnt, buf); +} + +static int ums_write_sector(struct ums *ums_dev, + ulong start, lbaint_t blkcnt, const void *buf) +{ + block_dev_desc_t *block_dev = ums_dev->block_dev; + lbaint_t blkstart = start + ums_dev->start_sector; + int dev_num = block_dev->dev; + + return block_dev->block_write(dev_num, blkstart, blkcnt, buf); +} + +static struct ums ums_dev = { + .read_sector = ums_read_sector, + .write_sector = ums_write_sector, + .name = "UMS disk", +}; + +struct ums *ums_init(const char *devtype, const char *devnum) +{ + block_dev_desc_t *block_dev; + int ret; + + ret = get_device(devtype, devnum, &block_dev); + if (ret < 0) + return NULL; + + /* f_mass_storage.c assumes SECTOR_SIZE sectors */ + if (block_dev->blksz != SECTOR_SIZE) + return NULL; + + ums_dev.block_dev = block_dev; + ums_dev.start_sector = 0; + ums_dev.num_sectors = block_dev->lba; + + printf("UMS: disk start sector: %#x, count: %#x\n", + ums_dev.start_sector, ums_dev.num_sectors); + + return &ums_dev; +} + int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *ep; - unsigned int dev_num = 0, offset = 0, part_size = 0; + const char *usb_controller; + const char *devtype; + const char *devnum; + struct ums *ums; + unsigned int controller_index; int rc; + int cable_ready_timeout __maybe_unused; - struct ums_board_info *ums_info; - static char *s = "ums"; + if (argc < 3) + return CMD_RET_USAGE; - if (argc < 2) { - printf("usage: ums - e.g. ums 0\n"); - return 0; + usb_controller = argv[1]; + if (argc >= 4) { + devtype = argv[2]; + devnum = argv[3]; + } else { + devtype = "mmc"; + devnum = argv[2]; } - dev_num = (int)simple_strtoul(argv[1], &ep, 16); + ums = ums_init(devtype, devnum); + if (!ums) + return CMD_RET_FAILURE; - if (dev_num) { - puts("\nSet eMMC device to 0! - e.g. ums 0\n"); - goto fail; + controller_index = (unsigned int)(simple_strtoul( + usb_controller, NULL, 0)); + if (board_usb_init(controller_index, USB_INIT_DEVICE)) { + error("Couldn't init USB controller."); + return CMD_RET_FAILURE; } - board_usb_init(); - ums_info = board_ums_init(dev_num, offset, part_size); - - if (!ums_info) { - printf("MMC: %d -> NOT available\n", dev_num); - goto fail; + rc = fsg_init(ums); + if (rc) { + error("fsg_init failed"); + return CMD_RET_FAILURE; } - rc = fsg_init(ums_info); + + rc = g_dnl_register("usb_dnl_ums"); if (rc) { - printf("cmd ums: fsg_init failed\n"); - goto fail; + error("g_dnl_register failed"); + return CMD_RET_FAILURE; } - g_dnl_register(s); + /* Timeout unit: seconds */ + cable_ready_timeout = UMS_CABLE_READY_TIMEOUT; - while (1) { - /* Handle control-c and timeouts */ - if (ctrlc()) { - printf("The remote end did not respond in time.\n"); - goto exit; + if (!g_dnl_board_usb_cable_connected()) { + /* + * Won't execute if we don't know whether the cable is + * connected. + */ + puts("Please connect USB cable.\n"); + + while (!g_dnl_board_usb_cable_connected()) { + if (ctrlc()) { + puts("\rCTRL+C - Operation aborted.\n"); + goto exit; + } + if (!cable_ready_timeout) { + puts("\rUSB cable not detected.\n" \ + "Command exit.\n"); + goto exit; + } + + printf("\rAuto exit in: %.2d s.", cable_ready_timeout); + mdelay(1000); + cable_ready_timeout--; } + puts("\r\n"); + } + + while (1) { usb_gadget_handle_interrupts(); - /* Check if USB cable has been detached */ - if (fsg_main_thread(NULL) == EIO) + + rc = fsg_main_thread(NULL); + if (rc) { + /* Check I/O error */ + if (rc == -EIO) + printf("\rCheck USB cable connection\n"); + + /* Check CTRL+C */ + if (rc == -EPIPE) + printf("\rCTRL+C - Operation aborted\n"); + goto exit; + } } exit: g_dnl_unregister(); - return 0; - -fail: - return -1; + return CMD_RET_SUCCESS; } -U_BOOT_CMD(ums, CONFIG_SYS_MAXARGS, 1, do_usb_mass_storage, +U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage, "Use the UMS [User Mass Storage]", - "ums - User Mass Storage Gadget" + "ums [] e.g. ums 0 mmc 0\n" + " devtype defaults to mmc" ); diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index b439be3d08..64b9186d73 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -20,6 +20,7 @@ #include #endif #include +#include #ifndef CONFIG_SYS_XIMG_LEN /* use 8MByte as default max gunzip size */ @@ -31,10 +32,13 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { ulong addr = load_addr; ulong dest = 0; - ulong data, len, count; + ulong data, len; int verify; int part = 0; - image_header_t *hdr; +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) + ulong count; + image_header_t *hdr = NULL; +#endif #if defined(CONFIG_FIT) const char *uname = NULL; const void* fit_hdr; @@ -63,6 +67,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } switch (genimg_get_format((void *)addr)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: printf("## Copying part %d from legacy image " @@ -113,6 +118,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) image_multi_getimg(hdr, part, &data, &len); break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: if (uname == NULL) { @@ -210,7 +216,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } break; #endif -#if defined(CONFIG_BZIP2) +#if defined(CONFIG_BZIP2) && defined(CONFIG_IMAGE_FORMAT_LEGACY) case IH_COMP_BZIP2: { int i; @@ -222,7 +228,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) * which requires at most 2300 KB of memory. */ i = BZ2_bzBuffToBuffDecompress( - (char *)ntohl(hdr->ih_load), + map_sysmem(ntohl(hdr->ih_load), 0), &unc_len, (char *)data, len, CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); @@ -241,6 +247,8 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) puts("OK\n"); } + flush_cache(dest, len); + setenv_hex("fileaddr", data); setenv_hex("filesize", len); diff --git a/common/cmd_zfs.c b/common/cmd_zfs.c index 911086809b..0aed29e9b2 100644 --- a/common/cmd_zfs.c +++ b/common/cmd_zfs.c @@ -95,7 +95,7 @@ static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] memset(&zfile, 0, sizeof(zfile)); zfile.device = &vdev; if (zfs_open(&zfile, filename)) { - printf("** File not found %s\n", filename); + printf("** File not found %s **\n", filename); return 1; } diff --git a/common/command.c b/common/command.c index 625571dd4d..4719f4978b 100644 --- a/common/command.c +++ b/common/command.c @@ -18,13 +18,13 @@ * for long help messages */ -int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int - flag, int argc, char * const argv[]) +int _do_help(cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) { int i; int rcode = 0; - if (argc == 1) { /*show list of commands */ + if (argc == 1) { /* show list of commands */ cmd_tbl_t *cmd_array[cmd_items]; int i, j, swaps; @@ -38,8 +38,8 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int for (i = cmd_items - 1; i > 0; --i) { swaps = 0; for (j = 0; j < i; ++j) { - if (strcmp (cmd_array[j]->name, - cmd_array[j + 1]->name) > 0) { + if (strcmp(cmd_array[j]->name, + cmd_array[j + 1]->name) > 0) { cmd_tbl_t *tmp; tmp = cmd_array[j]; cmd_array[j] = cmd_array[j + 1]; @@ -56,7 +56,7 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int const char *usage = cmd_array[i]->usage; /* allow user abort */ - if (ctrlc ()) + if (ctrlc()) return 1; if (usage == NULL) continue; @@ -69,26 +69,23 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int * command help (long version) */ for (i = 1; i < argc; ++i) { - if ((cmdtp = find_cmd_tbl (argv[i], cmd_start, cmd_items )) != NULL) { + cmdtp = find_cmd_tbl(argv[i], cmd_start, cmd_items); + if (cmdtp != NULL) { rcode |= cmd_usage(cmdtp); } else { - printf ("Unknown command '%s' - try 'help'" - " without arguments for list of all" - " known commands\n\n", argv[i] - ); + printf("Unknown command '%s' - try 'help' without arguments for list of all known commands\n\n", + argv[i]); rcode = 1; } } return rcode; } -/*************************************************************************** - * find command table entry for a command - */ -cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len) +/* find command table entry for a command */ +cmd_tbl_t *find_cmd_tbl(const char *cmd, cmd_tbl_t *table, int table_len) { cmd_tbl_t *cmdtp; - cmd_tbl_t *cmdtp_temp = table; /*Init value */ + cmd_tbl_t *cmdtp_temp = table; /* Init value */ const char *p; int len; int n_found = 0; @@ -101,11 +98,9 @@ cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len) */ len = ((p = strchr(cmd, '.')) == NULL) ? strlen (cmd) : (p - cmd); - for (cmdtp = table; - cmdtp != table + table_len; - cmdtp++) { - if (strncmp (cmd, cmdtp->name, len) == 0) { - if (len == strlen (cmdtp->name)) + for (cmdtp = table; cmdtp != table + table_len; cmdtp++) { + if (strncmp(cmd, cmdtp->name, len) == 0) { + if (len == strlen(cmdtp->name)) return cmdtp; /* full match */ cmdtp_temp = cmdtp; /* abbreviated command ? */ @@ -119,7 +114,7 @@ cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len) return NULL; /* not found or ambiguous command */ } -cmd_tbl_t *find_cmd (const char *cmd) +cmd_tbl_t *find_cmd(const char *cmd) { cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd); const int len = ll_entry_count(cmd_tbl_t, cmd); @@ -138,8 +133,8 @@ int cmd_usage(const cmd_tbl_t *cmdtp) return 1; } - puts (cmdtp->help); - putc ('\n'); + puts(cmdtp->help); + putc('\n'); #endif /* CONFIG_SYS_LONGHELP */ return 1; } @@ -184,17 +179,17 @@ static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv /* output full list of commands */ for (; cmdtp != cmdend; cmdtp++) { if (n_found >= maxv - 2) { - cmdv[n_found] = "..."; + cmdv[n_found++] = "..."; break; } - cmdv[n_found] = cmdtp->name; + cmdv[n_found++] = cmdtp->name; } cmdv[n_found] = NULL; return n_found; } /* more than one arg or one but the start of the next */ - if (argc > 1 || (last_char == '\0' || isblank(last_char))) { + if (argc > 1 || last_char == '\0' || isblank(last_char)) { cmdtp = find_cmd(argv[0]); if (cmdtp == NULL || cmdtp->complete == NULL) { cmdv[0] = NULL; @@ -345,7 +340,8 @@ int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp) argc = make_argv(tmp_buf, sizeof(argv)/sizeof(argv[0]), argv); /* do the completion and return the possible completions */ - i = complete_cmdv(argc, argv, last_char, sizeof(cmdv)/sizeof(cmdv[0]), cmdv); + i = complete_cmdv(argc, argv, last_char, + sizeof(cmdv) / sizeof(cmdv[0]), cmdv); /* no match; bell and out */ if (i == 0) { @@ -365,7 +361,7 @@ int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp) len = strlen(s); sep = " "; seplen = 1; - } else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) { /* more */ + } else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) { /* more */ k = strlen(argv[argc - 1]); j -= k; if (j > 0) { @@ -414,13 +410,17 @@ int cmd_get_data_size(char* arg, int default_size) */ int len = strlen(arg); if (len > 2 && arg[len-2] == '.') { - switch(arg[len-1]) { + switch (arg[len-1]) { case 'b': return 1; case 'w': return 2; case 'l': return 4; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + case 'q': + return 8; +#endif case 's': return -2; default: @@ -444,10 +444,10 @@ void fixup_cmdtable(cmd_tbl_t *cmdtp, int size) for (i = 0; i < size; i++) { ulong addr; - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; + addr = (ulong)(cmdtp->cmd) + gd->reloc_off; #if DEBUG_COMMANDS printf("Command \"%s\": 0x%08lx => 0x%08lx\n", - cmdtp->name, (ulong) (cmdtp->cmd), addr); + cmdtp->name, (ulong)(cmdtp->cmd), addr); #endif cmdtp->cmd = (int (*)(struct cmd_tbl_s *, int, int, char * const []))addr; @@ -538,3 +538,13 @@ enum command_ret_t cmd_process(int flag, int argc, char * const argv[], rc = cmd_usage(cmdtp); return rc; } + +int cmd_process_error(cmd_tbl_t *cmdtp, int err) +{ + if (err) { + printf("Command '%s' failed: Error %d\n", cmdtp->name, err); + return 1; + } + + return 0; +} diff --git a/common/console.c b/common/console.c index cc55068c7c..3f25e76fe7 100644 --- a/common/console.c +++ b/common/console.c @@ -7,7 +7,9 @@ #include #include +#include #include +#include #include #include #include @@ -108,7 +110,7 @@ static int console_setfile(int file, struct stdio_dev * dev) case stderr: /* Start new device */ if (dev->start) { - error = dev->start(); + error = dev->start(dev); /* If it's not started dont use it */ if (error < 0) break; @@ -123,13 +125,13 @@ static int console_setfile(int file, struct stdio_dev * dev) */ switch (file) { case stdin: - gd->jt[XF_getc] = dev->getc; - gd->jt[XF_tstc] = dev->tstc; + gd->jt->getc = getc; + gd->jt->tstc = tstc; break; case stdout: - gd->jt[XF_putc] = dev->putc; - gd->jt[XF_puts] = dev->puts; - gd->jt[XF_printf] = printf; + gd->jt->putc = putc; + gd->jt->puts = puts; + gd->jt->printf = printf; break; } break; @@ -158,7 +160,7 @@ static int console_getc(int file) unsigned char ret; /* This is never called with testcdev == NULL */ - ret = tstcdev->getc(); + ret = tstcdev->getc(tstcdev); tstcdev = NULL; return ret; } @@ -172,7 +174,7 @@ static int console_tstc(int file) for (i = 0; i < cd_count[file]; i++) { dev = console_devices[file][i]; if (dev->tstc != NULL) { - ret = dev->tstc(); + ret = dev->tstc(dev); if (ret > 0) { tstcdev = dev; disable_ctrlc(0); @@ -193,10 +195,24 @@ static void console_putc(int file, const char c) for (i = 0; i < cd_count[file]; i++) { dev = console_devices[file][i]; if (dev->putc != NULL) - dev->putc(c); + dev->putc(dev, c); } } +#ifdef CONFIG_PRE_CONSOLE_BUFFER +static void console_putc_noserial(int file, const char c) +{ + int i; + struct stdio_dev *dev; + + for (i = 0; i < cd_count[file]; i++) { + dev = console_devices[file][i]; + if (dev->putc != NULL && strcmp(dev->name, "serial") != 0) + dev->putc(dev, c); + } +} +#endif + static void console_puts(int file, const char *s) { int i; @@ -205,7 +221,7 @@ static void console_puts(int file, const char *s) for (i = 0; i < cd_count[file]; i++) { dev = console_devices[file][i]; if (dev->puts != NULL) - dev->puts(s); + dev->puts(dev, s); } } @@ -221,22 +237,30 @@ static inline void console_doenv(int file, struct stdio_dev *dev) #else static inline int console_getc(int file) { - return stdio_devices[file]->getc(); + return stdio_devices[file]->getc(stdio_devices[file]); } static inline int console_tstc(int file) { - return stdio_devices[file]->tstc(); + return stdio_devices[file]->tstc(stdio_devices[file]); } static inline void console_putc(int file, const char c) { - stdio_devices[file]->putc(c); + stdio_devices[file]->putc(stdio_devices[file], c); +} + +#ifdef CONFIG_PRE_CONSOLE_BUFFER +static inline void console_putc_noserial(int file, const char c) +{ + if (strcmp(stdio_devices[file]->name, "serial") != 0) + stdio_devices[file]->putc(stdio_devices[file], c); } +#endif static inline void console_puts(int file, const char *s) { - stdio_devices[file]->puts(s); + stdio_devices[file]->puts(stdio_devices[file], s); } static inline void console_printdevs(int file) @@ -380,6 +404,9 @@ int tstc(void) return serial_tstc(); } +#define PRE_CONSOLE_FLUSHPOINT1_SERIAL 0 +#define PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL 1 + #ifdef CONFIG_PRE_CONSOLE_BUFFER #define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_PRE_CON_BUF_SZ) @@ -396,7 +423,7 @@ static void pre_console_puts(const char *s) pre_console_putc(*s++); } -static void print_pre_console_buffer(void) +static void print_pre_console_buffer(int flushpoint) { unsigned long i = 0; char *buffer = (char *)CONFIG_PRE_CON_BUF_ADDR; @@ -405,16 +432,30 @@ static void print_pre_console_buffer(void) i = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ; while (i < gd->precon_buf_idx) - putc(buffer[CIRC_BUF_IDX(i++)]); + switch (flushpoint) { + case PRE_CONSOLE_FLUSHPOINT1_SERIAL: + putc(buffer[CIRC_BUF_IDX(i++)]); + break; + case PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL: + console_putc_noserial(stdout, + buffer[CIRC_BUF_IDX(i++)]); + break; + } } #else static inline void pre_console_putc(const char c) {} static inline void pre_console_puts(const char *s) {} -static inline void print_pre_console_buffer(void) {} +static inline void print_pre_console_buffer(int flushpoint) {} #endif void putc(const char c) { +#ifdef CONFIG_SANDBOX + if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) { + os_putc(c); + return; + } +#endif #ifdef CONFIG_SILENT_CONSOLE if (gd->flags & GD_FLG_SILENT) return; @@ -433,12 +474,20 @@ void putc(const char c) fputc(stdout, c); } else { /* Send directly to the handler */ + pre_console_putc(c); serial_putc(c); } } void puts(const char *s) { +#ifdef CONFIG_SANDBOX + if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) { + os_puts(s); + return; + } +#endif + #ifdef CONFIG_SILENT_CONSOLE if (gd->flags & GD_FLG_SILENT) return; @@ -457,6 +506,7 @@ void puts(const char *s) fputs(stdout, s); } else { /* Send directly to the handler */ + pre_console_puts(s); serial_puts(s); } } @@ -467,7 +517,7 @@ int printf(const char *fmt, ...) uint i; char printbuffer[CONFIG_SYS_PBSIZE]; -#ifndef CONFIG_PRE_CONSOLE_BUFFER +#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_PRE_CONSOLE_BUFFER) if (!gd->have_console) return 0; #endif @@ -490,7 +540,7 @@ int vprintf(const char *fmt, va_list args) uint i; char printbuffer[CONFIG_SYS_PBSIZE]; -#ifndef CONFIG_PRE_CONSOLE_BUFFER +#if defined(CONFIG_PRE_CONSOLE_BUFFER) && !defined(CONFIG_SANDBOX) if (!gd->have_console) return 0; #endif @@ -510,6 +560,7 @@ static int ctrlc_disabled = 0; /* see disable_ctrl() */ static int ctrlc_was_pressed = 0; int ctrlc(void) { +#ifndef CONFIG_SANDBOX if (!ctrlc_disabled && gd->have_console) { if (tstc()) { switch (getc()) { @@ -521,9 +572,37 @@ int ctrlc(void) } } } +#endif + + return 0; +} +/* Reads user's confirmation. + Returns 1 if user's input is "y", "Y", "yes" or "YES" +*/ +int confirm_yesno(void) +{ + int i; + char str_input[5]; + + /* Flush input */ + while (tstc()) + getc(); + i = 0; + while (i < sizeof(str_input)) { + str_input[i] = getc(); + putc(str_input[i]); + if (str_input[i] == '\r') + break; + i++; + } + putc('\n'); + if (strncmp(str_input, "y\r", 2) == 0 || + strncmp(str_input, "Y\r", 2) == 0 || + strncmp(str_input, "yes\r", 4) == 0 || + strncmp(str_input, "YES\r", 4) == 0) + return 1; return 0; } - /* pass 1 to disable ctrlc() checking, 0 to enable. * returns previous state */ @@ -578,7 +657,7 @@ inline void dbg(const char *fmt, ...) } #else -inline void dbg(const char *fmt, ...) +static inline void dbg(const char *fmt, ...) { } #endif @@ -635,7 +714,7 @@ int console_init_f(void) gd->flags |= GD_FLG_SILENT; #endif - print_pre_console_buffer(); + print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT1_SERIAL); return 0; } @@ -679,11 +758,11 @@ int console_init_r(void) #endif /* set default handlers at first */ - gd->jt[XF_getc] = serial_getc; - gd->jt[XF_tstc] = serial_tstc; - gd->jt[XF_putc] = serial_putc; - gd->jt[XF_puts] = serial_puts; - gd->jt[XF_printf] = serial_printf; + gd->jt->getc = serial_getc; + gd->jt->tstc = serial_tstc; + gd->jt->putc = serial_putc; + gd->jt->puts = serial_puts; + gd->jt->printf = serial_printf; /* stdin stdout and stderr are in environment */ /* scan for it */ @@ -750,6 +829,7 @@ done: if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL)) return 0; #endif + print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL); return 0; } @@ -825,7 +905,7 @@ int console_init_r(void) if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL)) return 0; #endif - + print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL); return 0; } diff --git a/common/cros_ec.c b/common/cros_ec.c new file mode 100644 index 0000000000..bb299bccff --- /dev/null +++ b/common/cros_ec.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_CROS_EC +struct local_info { + struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ + int cros_ec_err; /* Error for cros_ec, 0 if ok */ +}; + +static struct local_info local; +#endif + +struct cros_ec_dev *board_get_cros_ec_dev(void) +{ +#ifdef CONFIG_DM_CROS_EC + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_CROS_EC, 0, &dev); + if (ret) { + debug("%s: Error %d\n", __func__, ret); + return NULL; + } + return dev->uclass_priv; +#else + return local.cros_ec_dev; +#endif +} + +static int board_init_cros_ec_devices(const void *blob) +{ +#ifndef CONFIG_DM_CROS_EC + local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); + if (local.cros_ec_err) + return -1; /* Will report in board_late_init() */ +#endif + + return 0; +} + +int cros_ec_board_init(void) +{ + return board_init_cros_ec_devices(gd->fdt_blob); +} + +int cros_ec_get_error(void) +{ +#ifdef CONFIG_DM_CROS_EC + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_CROS_EC, 0, &dev); + if (ret && ret != -ENODEV) + return ret; + + return 0; +#else + return local.cros_ec_err; +#endif +} diff --git a/common/ddr_spd.c b/common/ddr_spd.c index 7a388bb9fa..438e71afd2 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -116,3 +116,46 @@ ddr3_spd_check(const ddr3_spd_eeprom_t *spd) return 1; } } + +unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd) +{ + char *p = (char *)spd; + int csum16; + int len; + char crc_lsb; /* byte 126 */ + char crc_msb; /* byte 127 */ + + len = 126; + csum16 = crc16(p, len); + + crc_lsb = (char) (csum16 & 0xff); + crc_msb = (char) (csum16 >> 8); + + if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb) { + printf("SPD checksum unexpected.\n" + "Checksum lsb in SPD = %02X, computed SPD = %02X\n" + "Checksum msb in SPD = %02X, computed SPD = %02X\n", + spd->crc[0], crc_lsb, spd->crc[1], crc_msb); + return 1; + } + + p = (char *)((ulong)spd + 128); + len = 126; + csum16 = crc16(p, len); + + crc_lsb = (char) (csum16 & 0xff); + crc_msb = (char) (csum16 >> 8); + + if (spd->mod_section.uc[126] != crc_lsb || + spd->mod_section.uc[127] != crc_msb) { + printf("SPD checksum unexpected.\n" + "Checksum lsb in SPD = %02X, computed SPD = %02X\n" + "Checksum msb in SPD = %02X, computed SPD = %02X\n", + spd->mod_section.uc[126], + crc_lsb, spd->mod_section.uc[127], + crc_msb); + return 1; + } + + return 0; +} diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 3c70d5dede..6453ee9c25 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1,5 +1,9 @@ #include +#ifdef CONFIG_SANDBOX +#define DEBUG +#endif + #if 0 /* Moved to malloc.h */ /* ---------- To make a malloc.h, start cutting here ------------ */ @@ -220,7 +224,7 @@ */ - + /* Preliminaries */ @@ -930,6 +934,8 @@ struct mallinfo mALLINFo(); #endif /* 0 */ /* Moved to malloc.h */ #include +#include + #ifdef DEBUG #if __STD_C static void malloc_update_mallinfo (void); @@ -1132,7 +1138,7 @@ gAllocatedSize)) #endif - + /* Type declarations @@ -1272,7 +1278,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ serviced via calls to mmap, and then later released via munmap. */ - + /* sizes, alignments */ #define SIZE_SZ (sizeof(INTERNAL_SIZE_T)) @@ -1297,7 +1303,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ #define aligned_OK(m) (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0) - + /* Physical chunk operations @@ -1332,7 +1338,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ #define chunk_at_offset(p, s) ((mchunkptr)(((char*)(p)) + (s))) - + /* Dealing with use bits @@ -1371,7 +1377,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ (((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE)) - + /* Dealing with size fields @@ -1394,7 +1400,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ #define set_foot(p, s) (((mchunkptr)((char*)(p) + (s)))->prev_size = (s)) - + /* @@ -1527,6 +1533,9 @@ void mem_malloc_init(ulong start, ulong size) mem_malloc_end = start + size; mem_malloc_brk = start; + debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start, + mem_malloc_end); + memset((void *)mem_malloc_start, 0, size); malloc_bin_reloc(); @@ -1566,7 +1575,7 @@ void mem_malloc_init(ulong start, ulong size) #define is_small_request(nb) (nb < MAX_SMALLBIN_SIZE - SMALLBIN_WIDTH) - + /* To help compensate for the large number of bins, a one-level index @@ -1590,7 +1599,7 @@ void mem_malloc_init(ulong start, ulong size) #define clear_binblock(ii) (binblocks_w = (mbinptr)(binblocks_r & ~(idx2binblock(ii)))) - + /* Other static bookkeeping data */ @@ -1628,7 +1637,7 @@ static unsigned int max_n_mmaps = 0; static unsigned long max_mmapped_mem = 0; #endif - + /* Debugging support @@ -1769,7 +1778,7 @@ static void do_check_malloced_chunk(p, s) mchunkptr p; INTERNAL_SIZE_T s; #define check_malloced_chunk(P,N) #endif - + /* Macro-based internal utilities @@ -1841,7 +1850,7 @@ static void do_check_malloced_chunk(p, s) mchunkptr p; INTERNAL_SIZE_T s; (last_remainder->fd = last_remainder->bk = last_remainder) - + /* Routines dealing with mmap(). */ @@ -1972,7 +1981,7 @@ static mchunkptr mremap_chunk(p, new_size) mchunkptr p; size_t new_size; #endif /* HAVE_MMAP */ - + /* Extend the top-most chunk by obtaining memory from system. @@ -2089,7 +2098,7 @@ static void malloc_extend_top(nb) INTERNAL_SIZE_T nb; } - + /* Main public routines */ @@ -2174,6 +2183,11 @@ Void_t* mALLOc(bytes) size_t bytes; INTERNAL_SIZE_T nb; +#ifdef CONFIG_SYS_MALLOC_F_LEN + if (gd && !(gd->flags & GD_FLG_FULL_MALLOC_INIT)) + return malloc_simple(bytes); +#endif + /* check if mem_malloc_init() was run */ if ((mem_malloc_start == 0) && (mem_malloc_end == 0)) { /* not initialized yet */ @@ -2396,7 +2410,7 @@ Void_t* mALLOc(bytes) size_t bytes; } - + /* @@ -2437,6 +2451,12 @@ void fREe(mem) Void_t* mem; mchunkptr fwd; /* misc temp for linking */ int islr; /* track whether merging with last_remainder */ +#ifdef CONFIG_SYS_MALLOC_F_LEN + /* free() is a no-op - all the memory will be freed on relocation */ + if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) + return; +#endif + if (mem == NULL) /* free(0) has no effect */ return; @@ -2513,7 +2533,7 @@ void fREe(mem) Void_t* mem; } - + /* @@ -2588,6 +2608,13 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; /* realloc of null is supposed to be same as malloc */ if (oldmem == NULL) return mALLOc(bytes); +#ifdef CONFIG_SYS_MALLOC_F_LEN + if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) { + /* This is harder to support and should not be needed */ + panic("pre-reloc realloc() is not supported"); + } +#endif + newp = oldp = mem2chunk(oldmem); newsize = oldsize = chunksize(oldp); @@ -2750,7 +2777,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; } - + /* @@ -2868,7 +2895,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; } - + /* @@ -2933,6 +2960,12 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; return NULL; else { +#ifdef CONFIG_SYS_MALLOC_F_LEN + if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) { + MALLOC_ZERO(mem, sz); + return mem; + } +#endif p = mem2chunk(mem); /* Two optional cases in which clearing not necessary */ @@ -2975,7 +3008,7 @@ void cfree(mem) Void_t *mem; } #endif - + /* @@ -3056,7 +3089,7 @@ int malloc_trim(pad) size_t pad; } } - + /* malloc_usable_size: @@ -3092,7 +3125,7 @@ size_t malloc_usable_size(mem) Void_t* mem; } - + /* Utility to update current_mallinfo for malloc_stats and mallinfo() */ @@ -3136,7 +3169,7 @@ static void malloc_update_mallinfo() } #endif /* DEBUG */ - + /* @@ -3183,7 +3216,7 @@ struct mallinfo mALLINFo() #endif /* DEBUG */ - + /* mallopt: diff --git a/common/edid.c b/common/edid.c index e66108f24a..df797fcdd5 100644 --- a/common/edid.c +++ b/common/edid.c @@ -12,6 +12,7 @@ #include #include +#include #include #include @@ -29,6 +30,17 @@ int edid_check_info(struct edid1_info *edid_info) return 0; } +int edid_check_checksum(u8 *edid_block) +{ + u8 checksum = 0; + int i; + + for (i = 0; i < 128; i++) + checksum += edid_block[i]; + + return (checksum == 0) ? 0 : -EINVAL; +} + int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, unsigned int *hmax, unsigned int *vmin, unsigned int *vmax) diff --git a/common/env_callback.c b/common/env_callback.c index 34bb58e4a9..d03fa03a43 100644 --- a/common/env_callback.c +++ b/common/env_callback.c @@ -35,6 +35,9 @@ static struct env_clbk_tbl *find_env_callback(const char *name) return NULL; } +static int first_call = 1; +static const char *callback_list; + /* * Look for a possible callback for a newly added variable * This is called specifically when the variable did not exist in the hash @@ -43,11 +46,15 @@ static struct env_clbk_tbl *find_env_callback(const char *name) void env_callback_init(ENTRY *var_entry) { const char *var_name = var_entry->key; - const char *callback_list = getenv(ENV_CALLBACK_VAR); char callback_name[256] = ""; struct env_clbk_tbl *clbkp; int ret = 1; + if (first_call) { + callback_list = getenv(ENV_CALLBACK_VAR); + first_call = 0; + } + /* look in the ".callbacks" var for a reference to this variable */ if (callback_list != NULL) ret = env_attr_lookup(callback_list, var_name, callback_name); diff --git a/common/env_common.c b/common/env_common.c index f387f9ab91..af59c72e1f 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -5,7 +5,7 @@ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH * Andreas Heppel * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -27,12 +27,10 @@ struct hsearch_data env_htab = { .change_ok = env_flags_validate, }; -static uchar __env_get_char_spec(int index) +__weak uchar env_get_char_spec(int index) { return *((uchar *)(gd->env_addr + index)); } -uchar env_get_char_spec(int) - __attribute__((weak, alias("__env_get_char_spec"))); static uchar env_get_char_init(int index) { @@ -120,7 +118,7 @@ void set_default_env(const char *s) } if (himport_r(&env_htab, (char *)default_environment, - sizeof(default_environment), '\0', flags, + sizeof(default_environment), '\0', flags, 0, 0, NULL) == 0) error("Environment import failed: errno = %d\n", errno); @@ -137,10 +135,55 @@ int set_default_vars(int nvars, char * const vars[]) */ return himport_r(&env_htab, (const char *)default_environment, sizeof(default_environment), '\0', - H_NOCLEAR | H_INTERACTIVE, nvars, vars); + H_NOCLEAR | H_INTERACTIVE, 0, nvars, vars); } -#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_ENV_AES +#include +/** + * env_aes_cbc_get_key() - Get AES-128-CBC key for the environment + * + * This function shall return 16-byte array containing AES-128 key used + * to encrypt and decrypt the environment. This function must be overriden + * by the implementer as otherwise the environment encryption will not + * work. + */ +__weak uint8_t *env_aes_cbc_get_key(void) +{ + return NULL; +} + +static int env_aes_cbc_crypt(env_t *env, const int enc) +{ + unsigned char *data = env->data; + uint8_t *key; + uint8_t key_exp[AES_EXPAND_KEY_LENGTH]; + uint32_t aes_blocks; + + key = env_aes_cbc_get_key(); + if (!key) + return -EINVAL; + + /* First we expand the key. */ + aes_expand_key(key, key_exp); + + /* Calculate the number of AES blocks to encrypt. */ + aes_blocks = ENV_SIZE / AES_KEY_LENGTH; + + if (enc) + aes_cbc_encrypt_blocks(key_exp, data, data, aes_blocks); + else + aes_cbc_decrypt_blocks(key_exp, data, data, aes_blocks); + + return 0; +} +#else +static inline int env_aes_cbc_crypt(env_t *env, const int enc) +{ + return 0; +} +#endif + /* * Check if CRC is valid and (if yes) import the environment. * Note that "buf" may or may not be aligned. @@ -148,6 +191,7 @@ int set_default_vars(int nvars, char * const vars[]) int env_import(const char *buf, int check) { env_t *ep = (env_t *)buf; + int ret; if (check) { uint32_t crc; @@ -160,7 +204,15 @@ int env_import(const char *buf, int check) } } - if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0, + /* Decrypt the env if desired. */ + ret = env_aes_cbc_crypt(ep, 0); + if (ret) { + error("Failed to decrypt env!\n"); + set_default_env("!import failed"); + return ret; + } + + if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0, 0, 0, NULL)) { gd->flags |= GD_FLG_ENV_READY; return 1; @@ -172,7 +224,30 @@ int env_import(const char *buf, int check) return 0; } -#endif + +/* Emport the environment and generate CRC for it. */ +int env_export(env_t *env_out) +{ + char *res; + ssize_t len; + int ret; + + res = (char *)env_out->data; + len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + + /* Encrypt the env if desired. */ + ret = env_aes_cbc_crypt(env_out, 1); + if (ret) + return ret; + + env_out->crc = crc32(0, env_out->data, ENV_SIZE); + + return 0; +} void env_relocate(void) { diff --git a/common/env_dataflash.c b/common/env_dataflash.c index 5f21d5c38e..034e323169 100644 --- a/common/env_dataflash.c +++ b/common/env_dataflash.c @@ -29,11 +29,25 @@ uchar env_get_char_spec(int index) void env_relocate_spec(void) { + ulong crc, new = 0; + unsigned off; char buf[CONFIG_ENV_SIZE]; + /* Read old CRC */ + read_dataflash(CONFIG_ENV_ADDR + offsetof(env_t, crc), + sizeof(ulong), (char *)&crc); + + /* Read whole environment */ read_dataflash(CONFIG_ENV_ADDR, CONFIG_ENV_SIZE, buf); - env_import(buf, 1); + /* Calculate the CRC */ + off = offsetof(env_t, data); + new = crc32(new, (unsigned char *)(buf + off), ENV_SIZE); + + if (crc == new) + env_import(buf, 1); + else + set_default_env("!bad CRC"); } #ifdef CONFIG_ENV_OFFSET_REDUND @@ -42,17 +56,12 @@ void env_relocate_spec(void) int saveenv(void) { - env_t env_new; - ssize_t len; - char *res; - - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); + env_t env_new; + int ret; + + ret = env_export(&env_new); + if (ret) + return ret; return write_dataflash(CONFIG_ENV_ADDR, (unsigned long)&env_new, @@ -67,37 +76,9 @@ int saveenv(void) */ int env_init(void) { - ulong crc, len = ENV_SIZE, new = 0; - unsigned off; - uchar buf[64]; - - if (gd->env_valid) - return 0; - - AT91F_DataflashInit(); /* prepare for DATAFLASH read/write */ - - /* read old CRC */ - read_dataflash(CONFIG_ENV_ADDR + offsetof(env_t, crc), - sizeof(ulong), (char *)&crc); - - off = offsetof(env_t, data); - while (len > 0) { - int n = (len > sizeof(buf)) ? sizeof(buf) : len; - - read_dataflash(CONFIG_ENV_ADDR + off, n, (char *)buf); - - new = crc32(new, buf, n); - len -= n; - off += n; - } - - if (crc == new) { - gd->env_addr = offsetof(env_t, data); - gd->env_valid = 1; - } else { - gd->env_addr = (ulong)&default_environment[0]; - gd->env_valid = 0; - } + /* use default */ + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; return 0; } diff --git a/common/env_eeprom.c b/common/env_eeprom.c index 149370f834..905d39ac98 100644 --- a/common/env_eeprom.c +++ b/common/env_eeprom.c @@ -5,7 +5,7 @@ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH * Andreas Heppel * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -24,7 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; env_t *env_ptr; char *env_name_spec = "EEPROM"; -int env_eeprom_bus = -1; static int eeprom_bus_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) @@ -40,8 +39,7 @@ static int eeprom_bus_read(unsigned dev_addr, unsigned offset, rcode = eeprom_read(dev_addr, offset, buffer, cnt); #if defined(CONFIG_I2C_ENV_EEPROM_BUS) - if (old_bus != env_eeprom_bus) - i2c_set_bus_num(old_bus); + i2c_set_bus_num(old_bus); #endif return rcode; @@ -63,6 +61,7 @@ static int eeprom_bus_write(unsigned dev_addr, unsigned offset, #if defined(CONFIG_I2C_ENV_EEPROM_BUS) i2c_set_bus_num(old_bus); #endif + return rcode; } @@ -99,8 +98,6 @@ void env_relocate_spec(void) int saveenv(void) { env_t env_new; - ssize_t len; - char *res; int rc; unsigned int off = CONFIG_ENV_OFFSET; #ifdef CONFIG_ENV_OFFSET_REDUND @@ -110,13 +107,9 @@ int saveenv(void) BUG_ON(env_ptr != NULL); - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); + rc = env_export(&env_new); + if (rc) + return rc; #ifdef CONFIG_ENV_OFFSET_REDUND if (gd->env_valid == 1) { @@ -154,6 +147,7 @@ int saveenv(void) #ifdef CONFIG_ENV_OFFSET_REDUND int env_init(void) { +#ifdef ENV_IS_EMBEDDED ulong len, crc[2], crc_tmp; unsigned int off, off_env[2]; uchar buf[64], flags[2]; @@ -219,12 +213,16 @@ int env_init(void) gd->env_addr = off_env[1] + offsetof(env_t, data); else if (gd->env_valid == 1) gd->env_addr = off_env[0] + offsetof(env_t, data); - +#else + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; +#endif return 0; } #else int env_init(void) { +#ifdef ENV_IS_EMBEDDED ulong crc, len, new; unsigned off; uchar buf[64]; @@ -257,7 +255,10 @@ int env_init(void) gd->env_addr = 0; gd->env_valid = 0; } - +#else + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; +#endif return 0; } #endif diff --git a/common/env_embedded.c b/common/env_embedded.c index 91d8ba308d..56a13cb882 100644 --- a/common/env_embedded.c +++ b/common/env_embedded.c @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASSEMBLY__ @@ -33,7 +33,7 @@ * a seperate section. Note that ENV_CRC is only defined when building * U-Boot itself. */ -#if (defined(CONFIG_SYS_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \ +#if defined(CONFIG_SYS_USE_PPCENV) && \ defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */ /* XXX - This only works with GNU C */ # define __PPCENV__ __attribute__ ((section(".ppcenv"))) diff --git a/common/env_fat.c b/common/env_fat.c index e114921c4a..e4c848935a 100644 --- a/common/env_fat.c +++ b/common/env_fat.c @@ -4,7 +4,7 @@ * Author: * Maximilian Schwerin * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -37,50 +37,31 @@ int env_init(void) int saveenv(void) { env_t env_new; - ssize_t len; - char *res; block_dev_desc_t *dev_desc = NULL; - int dev = FAT_ENV_DEVICE; - int part = FAT_ENV_PART; + disk_partition_t info; + int dev, part; int err; + loff_t size; - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - -#ifdef CONFIG_MMC - if (strcmp(FAT_ENV_INTERFACE, "mmc") == 0) { - struct mmc *mmc = find_mmc_device(dev); - - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return 1; - } + err = env_export(&env_new); + if (err) + return err; - mmc->has_init = 0; - mmc_init(mmc); - } -#endif /* CONFIG_MMC */ - - dev_desc = get_dev(FAT_ENV_INTERFACE, dev); - if (dev_desc == NULL) { - printf("Failed to find %s%d\n", - FAT_ENV_INTERFACE, dev); + part = get_device_and_partition(FAT_ENV_INTERFACE, + FAT_ENV_DEVICE_AND_PART, + &dev_desc, &info, 1); + if (part < 0) return 1; - } - err = fat_register_device(dev_desc, part); - if (err) { - printf("Failed to register %s%d:%d\n", - FAT_ENV_INTERFACE, dev, part); + dev = dev_desc->dev; + if (fat_set_blk_dev(dev_desc, &info) != 0) { + printf("\n** Unable to use %s %d:%d for saveenv **\n", + FAT_ENV_INTERFACE, dev, part); return 1; } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); - err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, sizeof(env_t)); + err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, 0, sizeof(env_t), + &size); if (err == -1) { printf("\n** Unable to write \"%s\" from %s%d:%d **\n", FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part); @@ -94,50 +75,35 @@ int saveenv(void) void env_relocate_spec(void) { - char buf[CONFIG_ENV_SIZE]; + ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); block_dev_desc_t *dev_desc = NULL; - int dev = FAT_ENV_DEVICE; - int part = FAT_ENV_PART; + disk_partition_t info; + int dev, part; int err; -#ifdef CONFIG_MMC - if (strcmp(FAT_ENV_INTERFACE, "mmc") == 0) { - struct mmc *mmc = find_mmc_device(dev); - - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - set_default_env(NULL); - return; - } - - mmc->has_init = 0; - mmc_init(mmc); - } -#endif /* CONFIG_MMC */ - - dev_desc = get_dev(FAT_ENV_INTERFACE, dev); - if (dev_desc == NULL) { - printf("Failed to find %s%d\n", - FAT_ENV_INTERFACE, dev); - set_default_env(NULL); - return; + part = get_device_and_partition(FAT_ENV_INTERFACE, + FAT_ENV_DEVICE_AND_PART, + &dev_desc, &info, 1); + if (part < 0) + goto err_env_relocate; + + dev = dev_desc->dev; + if (fat_set_blk_dev(dev_desc, &info) != 0) { + printf("\n** Unable to use %s %d:%d for loading the env **\n", + FAT_ENV_INTERFACE, dev, part); + goto err_env_relocate; } - err = fat_register_device(dev_desc, part); - if (err) { - printf("Failed to register %s%d:%d\n", - FAT_ENV_INTERFACE, dev, part); - set_default_env(NULL); - return; - } - - err = file_fat_read(FAT_ENV_FILE, (uchar *)&buf, CONFIG_ENV_SIZE); + err = file_fat_read(FAT_ENV_FILE, buf, CONFIG_ENV_SIZE); if (err == -1) { printf("\n** Unable to read \"%s\" from %s%d:%d **\n", FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part); - set_default_env(NULL); - return; + goto err_env_relocate; } env_import(buf, 1); + return; + +err_env_relocate: + set_default_env(NULL); } diff --git a/common/env_flags.c b/common/env_flags.c index e9b72e60a9..985f92e50e 100644 --- a/common/env_flags.c +++ b/common/env_flags.c @@ -395,6 +395,9 @@ static int env_parse_flags_to_bin(const char *flags) return binflags; } +static int first_call = 1; +static const char *flags_list; + /* * Look for possible flags for a newly added variable * This is called specifically when the variable did not exist in the hash @@ -403,10 +406,13 @@ static int env_parse_flags_to_bin(const char *flags) void env_flags_init(ENTRY *var_entry) { const char *var_name = var_entry->key; - const char *flags_list = getenv(ENV_FLAGS_VAR); char flags[ENV_FLAGS_ATTR_MAX_LEN + 1] = ""; int ret = 1; + if (first_call) { + flags_list = getenv(ENV_FLAGS_VAR); + first_call = 0; + } /* look in the ".flags" and static for a reference to this variable */ ret = env_flags_lookup(flags_list, var_name, flags); diff --git a/common/env_flash.c b/common/env_flash.c index d4a0e18c3d..004e8849a7 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -5,7 +5,7 @@ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH * Andreas Heppel - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* #define DEBUG */ @@ -106,8 +106,7 @@ int env_init(void) int saveenv(void) { env_t env_new; - ssize_t len; - char *res, *saved_data = NULL; + char *saved_data = NULL; char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG; int rc = 1; #if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE @@ -125,13 +124,9 @@ int saveenv(void) if (flash_sect_protect(0, (ulong)flash_addr_new, end_addr_new)) goto done; - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - goto done; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); + rc = env_export(&env_new); + if (rc) + return rc; env_new.flags = new_flag; #if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE @@ -229,9 +224,8 @@ int env_init(void) int saveenv(void) { env_t env_new; - ssize_t len; int rc = 1; - char *res, *saved_data = NULL; + char *saved_data = NULL; #if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE ulong up_data = 0; @@ -258,13 +252,9 @@ int saveenv(void) if (flash_sect_protect(0, (long)flash_addr, end_addr)) goto done; - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); + rc = env_export(&env_new); + if (rc) goto done; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); puts("Erasing Flash..."); if (flash_sect_erase((long)flash_addr, end_addr)) diff --git a/common/env_mmc.c b/common/env_mmc.c index 65aafa9cac..14648e37bd 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2008-2011 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* #define DEBUG */ @@ -62,6 +62,34 @@ int env_init(void) return 0; } +#ifdef CONFIG_SYS_MMC_ENV_PART +__weak uint mmc_get_env_part(struct mmc *mmc) +{ + return CONFIG_SYS_MMC_ENV_PART; +} + +static int mmc_set_env_part(struct mmc *mmc) +{ + uint part = mmc_get_env_part(mmc); + int dev = CONFIG_SYS_MMC_ENV_DEV; + int ret = 0; + +#ifdef CONFIG_SPL_BUILD + dev = 0; +#endif + + if (part != mmc->part_num) { + ret = mmc_switch_part(dev, part); + if (ret) + puts("MMC partition switch failed\n"); + } + + return ret; +} +#else +static inline int mmc_set_env_part(struct mmc *mmc) {return 0; }; +#endif + static int init_mmc_for_env(struct mmc *mmc) { if (!mmc) { @@ -74,25 +102,19 @@ static int init_mmc_for_env(struct mmc *mmc) return -1; } -#ifdef CONFIG_SYS_MMC_ENV_PART - if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) { - if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV, - CONFIG_SYS_MMC_ENV_PART)) { - puts("MMC partition switch failed\n"); - return -1; - } - } -#endif - - return 0; + return mmc_set_env_part(mmc); } static void fini_mmc_for_env(struct mmc *mmc) { #ifdef CONFIG_SYS_MMC_ENV_PART - if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) - mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV, - mmc->part_num); + int dev = CONFIG_SYS_MMC_ENV_DEV; + +#ifdef CONFIG_SPL_BUILD + dev = 0; +#endif + if (mmc_get_env_part(mmc) != mmc->part_num) + mmc_switch_part(dev, mmc->part_num); #endif } @@ -118,8 +140,6 @@ static unsigned char env_flags; int saveenv(void) { ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); - ssize_t len; - char *res; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); u32 offset; int ret, copy = 0; @@ -127,15 +147,9 @@ int saveenv(void) if (init_mmc_for_env(mmc)) return 1; - res = (char *)&env_new->data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - ret = 1; + ret = env_export(env_new); + if (ret) goto fini; - } - - env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE); #ifdef CONFIG_ENV_OFFSET_REDUND env_new->flags = ++env_flags; /* increase the serial */ @@ -174,12 +188,16 @@ static inline int read_env(struct mmc *mmc, unsigned long size, unsigned long offset, const void *buffer) { uint blk_start, blk_cnt, n; + int dev = CONFIG_SYS_MMC_ENV_DEV; + +#ifdef CONFIG_SPL_BUILD + dev = 0; +#endif blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; - n = mmc->block_dev.block_read(CONFIG_SYS_MMC_ENV_DEV, blk_start, - blk_cnt, (uchar *)buffer); + n = mmc->block_dev.block_read(dev, blk_start, blk_cnt, (uchar *)buffer); return (n == blk_cnt) ? 0 : -1; } @@ -188,20 +206,22 @@ static inline int read_env(struct mmc *mmc, unsigned long size, void env_relocate_spec(void) { #if !defined(ENV_IS_EMBEDDED) - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + struct mmc *mmc; u32 offset1, offset2; int read1_fail = 0, read2_fail = 0; int crc1_ok = 0, crc2_ok = 0; - env_t *ep, *tmp_env1, *tmp_env2; + env_t *ep; int ret; + int dev = CONFIG_SYS_MMC_ENV_DEV; - tmp_env1 = (env_t *)malloc(CONFIG_ENV_SIZE); - tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE); - if (tmp_env1 == NULL || tmp_env2 == NULL) { - puts("Can't allocate buffers for environment\n"); - ret = 1; - goto err; - } + ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env1, 1); + ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env2, 1); + +#ifdef CONFIG_SPL_BUILD + dev = 0; +#endif + + mmc = find_mmc_device(dev); if (init_mmc_for_env(mmc)) { ret = 1; @@ -266,8 +286,6 @@ err: if (ret) set_default_env(NULL); - free(tmp_env1); - free(tmp_env2); #endif } #else /* ! CONFIG_ENV_OFFSET_REDUND */ @@ -275,9 +293,16 @@ void env_relocate_spec(void) { #if !defined(ENV_IS_EMBEDDED) ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + struct mmc *mmc; u32 offset; int ret; + int dev = CONFIG_SYS_MMC_ENV_DEV; + +#ifdef CONFIG_SPL_BUILD + dev = 0; +#endif + + mmc = find_mmc_device(dev); if (init_mmc_for_env(mmc)) { ret = 1; diff --git a/common/env_nand.c b/common/env_nand.c index 9ae28ecbe7..dc457f959d 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -11,7 +11,7 @@ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH * Andreas Heppel * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -122,7 +122,7 @@ int env_init(void) * The legacy NAND code saved the environment in the first NAND device i.e., * nand_dev_desc + 0. This is also the behaviour using the new NAND code. */ -int writeenv(size_t offset, u_char *buf) +static int writeenv(size_t offset, u_char *buf) { size_t end = offset + CONFIG_ENV_RANGE; size_t amount_saved = 0; @@ -130,7 +130,7 @@ int writeenv(size_t offset, u_char *buf) u_char *char_ptr; blocksize = nand_info[0].erasesize; - len = min(blocksize, CONFIG_ENV_SIZE); + len = min(blocksize, (size_t)CONFIG_ENV_SIZE); while (amount_saved < CONFIG_ENV_SIZE && offset < end) { if (nand_block_isbad(&nand_info[0], offset)) { @@ -150,101 +150,88 @@ int writeenv(size_t offset, u_char *buf) return 0; } -#ifdef CONFIG_ENV_OFFSET_REDUND -static unsigned char env_flags; +struct env_location { + const char *name; + const nand_erase_options_t erase_opts; +}; -int saveenv(void) +static int erase_and_write_env(const struct env_location *location, + u_char *env_new) { - env_t env_new; - ssize_t len; - char *res; - int ret = 0; - nand_erase_options_t nand_erase_options; - - memset(&nand_erase_options, 0, sizeof(nand_erase_options)); - nand_erase_options.length = CONFIG_ENV_RANGE; - - if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) - return 1; - - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); - env_new.flags = ++env_flags; /* increase the serial */ - - if (gd->env_valid == 1) { - puts("Erasing redundant NAND...\n"); - nand_erase_options.offset = CONFIG_ENV_OFFSET_REDUND; - if (nand_erase_opts(&nand_info[0], &nand_erase_options)) - return 1; + int ret = 0; - puts("Writing to redundant NAND... "); - ret = writeenv(CONFIG_ENV_OFFSET_REDUND, (u_char *)&env_new); - } else { - puts("Erasing NAND...\n"); - nand_erase_options.offset = CONFIG_ENV_OFFSET; - if (nand_erase_opts(&nand_info[0], &nand_erase_options)) - return 1; - - puts("Writing to NAND... "); - ret = writeenv(CONFIG_ENV_OFFSET, (u_char *)&env_new); - } - if (ret) { - puts("FAILED!\n"); + printf("Erasing %s...\n", location->name); + if (nand_erase_opts(&nand_info[0], &location->erase_opts)) return 1; - } - - puts("done\n"); - gd->env_valid = gd->env_valid == 2 ? 1 : 2; + printf("Writing to %s... ", location->name); + ret = writeenv(location->erase_opts.offset, env_new); + puts(ret ? "FAILED!\n" : "OK\n"); return ret; } -#else /* ! CONFIG_ENV_OFFSET_REDUND */ + +#ifdef CONFIG_ENV_OFFSET_REDUND +static unsigned char env_flags; +#endif + int saveenv(void) { int ret = 0; ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); - ssize_t len; - char *res; - nand_erase_options_t nand_erase_options; + int env_idx = 0; + static const struct env_location location[] = { + { + .name = "NAND", + .erase_opts = { + .length = CONFIG_ENV_RANGE, + .offset = CONFIG_ENV_OFFSET, + }, + }, +#ifdef CONFIG_ENV_OFFSET_REDUND + { + .name = "redundant NAND", + .erase_opts = { + .length = CONFIG_ENV_RANGE, + .offset = CONFIG_ENV_OFFSET_REDUND, + }, + }, +#endif + }; - memset(&nand_erase_options, 0, sizeof(nand_erase_options)); - nand_erase_options.length = CONFIG_ENV_RANGE; - nand_erase_options.offset = CONFIG_ENV_OFFSET; if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) return 1; - res = (char *)&env_new->data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - env_new->crc = crc32(0, env_new->data, ENV_SIZE); + ret = env_export(env_new); + if (ret) + return ret; - puts("Erasing Nand...\n"); - if (nand_erase_opts(&nand_info[0], &nand_erase_options)) - return 1; +#ifdef CONFIG_ENV_OFFSET_REDUND + env_new->flags = ++env_flags; /* increase the serial */ + env_idx = (gd->env_valid == 1); +#endif - puts("Writing to Nand... "); - if (writeenv(CONFIG_ENV_OFFSET, (u_char *)env_new)) { - puts("FAILED!\n"); - return 1; + ret = erase_and_write_env(&location[env_idx], (u_char *)env_new); +#ifdef CONFIG_ENV_OFFSET_REDUND + if (!ret) { + /* preset other copy for next write */ + gd->env_valid = gd->env_valid == 2 ? 1 : 2; + return ret; } - puts("done\n"); + env_idx = (env_idx + 1) & 1; + ret = erase_and_write_env(&location[env_idx], (u_char *)env_new); + if (!ret) + printf("Warning: primary env write failed," + " redundancy is lost!\n"); +#endif + return ret; } -#endif /* CONFIG_ENV_OFFSET_REDUND */ #endif /* CMD_SAVEENV */ -int readenv(size_t offset, u_char *buf) +static int readenv(size_t offset, u_char *buf) { size_t end = offset + CONFIG_ENV_RANGE; size_t amount_loaded = 0; @@ -255,7 +242,7 @@ int readenv(size_t offset, u_char *buf) if (!blocksize) return 1; - len = min(blocksize, CONFIG_ENV_SIZE); + len = min(blocksize, (size_t)CONFIG_ENV_SIZE); while (amount_loaded < CONFIG_ENV_SIZE && offset < end) { if (nand_block_isbad(&nand_info[0], offset)) { diff --git a/common/env_nowhere.c b/common/env_nowhere.c index c411e8cfe7..bdc1ed5e67 100644 --- a/common/env_nowhere.c +++ b/common/env_nowhere.c @@ -5,7 +5,7 @@ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH * Andreas Heppel - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/common/env_nvram.c b/common/env_nvram.c index 49144220b1..524f07d5f8 100644 --- a/common/env_nvram.c +++ b/common/env_nvram.c @@ -5,7 +5,7 @@ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH * Andreas Heppel - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -69,17 +69,11 @@ void env_relocate_spec(void) int saveenv(void) { env_t env_new; - ssize_t len; - char *res; int rcode = 0; - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); + rcode = env_export(&env_new); + if (rcode) + return rcode; #ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE nvram_write(CONFIG_ENV_ADDR, &env_new, CONFIG_ENV_SIZE); diff --git a/common/env_onenand.c b/common/env_onenand.c index 4b44632180..cc3d670de8 100644 --- a/common/env_onenand.c +++ b/common/env_onenand.c @@ -66,8 +66,7 @@ void env_relocate_spec(void) int saveenv(void) { env_t env_new; - ssize_t len; - char *res; + int ret; struct mtd_info *mtd = &onenand_mtd; #ifdef CONFIG_ENV_ADDR_FLEX struct onenand_chip *this = &onenand_chip; @@ -78,13 +77,9 @@ int saveenv(void) .callback = NULL, }; - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); + ret = env_export(&env_new); + if (ret) + return ret; instr.len = CONFIG_ENV_SIZE; #ifdef CONFIG_ENV_ADDR_FLEX diff --git a/common/env_remote.c b/common/env_remote.c index 1b6609b909..eb977ee1fe 100644 --- a/common/env_remote.c +++ b/common/env_remote.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2011-2012 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* #define DEBUG */ diff --git a/common/env_sf.c b/common/env_sf.c index e3e1897ccb..5e3729c2c2 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -7,11 +7,12 @@ * * (C) Copyright 2008 Atmel Corporation * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#include #include #include #include @@ -47,8 +48,7 @@ static struct spi_flash *env_flash; int saveenv(void) { env_t env_new; - ssize_t len; - char *res, *saved_buffer = NULL, flag = OBSOLETE_FLAG; + char *saved_buffer = NULL, flag = OBSOLETE_FLAG; u32 saved_size, saved_offset, sector = 1; int ret; @@ -62,13 +62,9 @@ int saveenv(void) } } - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); + ret = env_export(&env_new); + if (ret) + return ret; env_new.flags = ACTIVE_FLAG; if (gd->env_valid == 1) { @@ -225,10 +221,9 @@ out: int saveenv(void) { u32 saved_size, saved_offset, sector = 1; - char *res, *saved_buffer = NULL; + char *saved_buffer = NULL; int ret = 1; env_t env_new; - ssize_t len; if (!env_flash) { env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, @@ -260,13 +255,9 @@ int saveenv(void) sector++; } - res = (char *)&env_new.data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); + ret = env_export(&env_new); + if (ret) goto done; - } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); puts("Erasing SPI flash..."); ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET, @@ -299,13 +290,16 @@ int saveenv(void) void env_relocate_spec(void) { - char buf[CONFIG_ENV_SIZE]; int ret; + char *buf = NULL; + buf = (char *)malloc(CONFIG_ENV_SIZE); env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); if (!env_flash) { set_default_env("!spi_flash_probe() failed"); + if (buf) + free(buf); return; } @@ -321,6 +315,8 @@ void env_relocate_spec(void) gd->env_valid = 1; out: spi_flash_free(env_flash); + if (buf) + free(buf); env_flash = NULL; } #endif diff --git a/common/env_ubi.c b/common/env_ubi.c index f24a96c3e9..77bbfa6ef4 100644 --- a/common/env_ubi.c +++ b/common/env_ubi.c @@ -2,7 +2,7 @@ * (c) Copyright 2012 by National Instruments, * Joe Hershberger * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -37,15 +37,11 @@ static unsigned char env_flags; int saveenv(void) { ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); - ssize_t len; - char *res; + int ret; - res = (char *)&env_new->data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } + ret = env_export(env_new); + if (ret) + return ret; if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) { printf("\n** Cannot find mtd partition \"%s\"\n", @@ -53,7 +49,6 @@ int saveenv(void) return 1; } - env_new->crc = crc32(0, env_new->data, ENV_SIZE); env_new->flags = ++env_flags; /* increase the serial */ if (gd->env_valid == 1) { @@ -86,15 +81,11 @@ int saveenv(void) int saveenv(void) { ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); - ssize_t len; - char *res; + int ret; - res = (char *)&env_new->data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } + ret = env_export(env_new); + if (ret) + return ret; if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) { printf("\n** Cannot find mtd partition \"%s\"\n", @@ -102,8 +93,6 @@ int saveenv(void) return 1; } - env_new->crc = crc32(0, env_new->data, ENV_SIZE); - if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME, (void *)env_new, CONFIG_ENV_SIZE)) { printf("\n** Unable to write env to %s:%s **\n", diff --git a/common/exports.c b/common/exports.c index b97ca48307..333107c74c 100644 --- a/common/exports.c +++ b/common/exports.c @@ -1,6 +1,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -13,31 +14,10 @@ unsigned long get_version(void) return XF_VERSION; } -/* Reuse _exports.h with a little trickery to avoid bitrot */ -#define EXPORT_FUNC(sym) gd->jt[XF_##sym] = (void *)sym; - -#if !defined(CONFIG_X86) && !defined(CONFIG_PPC) -# define install_hdlr dummy -# define free_hdlr dummy -#else /* kludge for non-standard function naming */ -# define install_hdlr irq_install_handler -# define free_hdlr irq_free_handler -#endif -#ifndef CONFIG_CMD_I2C -# define i2c_write dummy -# define i2c_read dummy -#endif -#ifndef CONFIG_CMD_SPI -# define spi_init dummy -# define spi_setup_slave dummy -# define spi_free_slave dummy -# define spi_claim_bus dummy -# define spi_release_bus dummy -# define spi_xfer dummy -#endif +#define EXPORT_FUNC(f, a, x, ...) gd->jt->x = f; void jumptable_init(void) { - gd->jt = malloc(XF_MAX * sizeof(void *)); + gd->jt = malloc(sizeof(struct jt_funcs)); #include <_exports.h> } diff --git a/common/fb_mmc.c b/common/fb_mmc.c new file mode 100644 index 0000000000..6ea3938d83 --- /dev/null +++ b/common/fb_mmc.c @@ -0,0 +1,112 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_FASTBOOT_GPT_NAME +#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME +#endif + +/* The 64 defined bytes plus the '\0' */ +#define RESPONSE_LEN (64 + 1) + +static char *response_str; + +void fastboot_fail(const char *s) +{ + strncpy(response_str, "FAIL", 4); + strncat(response_str, s, RESPONSE_LEN - 4 - 1); +} + +void fastboot_okay(const char *s) +{ + strncpy(response_str, "OKAY", 4); + strncat(response_str, s, RESPONSE_LEN - 4 - 1); +} + +static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info, + const char *part_name, void *buffer, + unsigned int download_bytes) +{ + lbaint_t blkcnt; + lbaint_t blks; + + /* determine number of blocks to write */ + blkcnt = ((download_bytes + (info->blksz - 1)) & ~(info->blksz - 1)); + blkcnt = blkcnt / info->blksz; + + if (blkcnt > info->size) { + error("too large for partition: '%s'\n", part_name); + fastboot_fail("too large for partition"); + return; + } + + puts("Flashing Raw Image\n"); + + blks = dev_desc->block_write(dev_desc->dev, info->start, blkcnt, + buffer); + if (blks != blkcnt) { + error("failed writing to device %d\n", dev_desc->dev); + fastboot_fail("failed writing to device"); + return; + } + + printf("........ wrote " LBAFU " bytes to '%s'\n", blkcnt * info->blksz, + part_name); + fastboot_okay(""); +} + +void fb_mmc_flash_write(const char *cmd, void *download_buffer, + unsigned int download_bytes, char *response) +{ + block_dev_desc_t *dev_desc; + disk_partition_t info; + + /* initialize the response buffer */ + response_str = response; + + dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + error("invalid mmc device\n"); + fastboot_fail("invalid mmc device"); + return; + } + + if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) { + printf("%s: updating MBR, Primary and Backup GPT(s)\n", + __func__); + if (is_valid_gpt_buf(dev_desc, download_buffer)) { + printf("%s: invalid GPT - refusing to write to flash\n", + __func__); + fastboot_fail("invalid GPT partition"); + return; + } + if (write_mbr_and_gpt_partitions(dev_desc, download_buffer)) { + printf("%s: writing GPT partitions failed\n", __func__); + fastboot_fail("writing GPT partitions failed"); + return; + } + printf("........ success\n"); + fastboot_okay(""); + return; + } else if (get_partition_info_efi_by_name(dev_desc, cmd, &info)) { + error("cannot find partition: '%s'\n", cmd); + fastboot_fail("cannot find partition"); + return; + } + + if (is_sparse_image(download_buffer)) + write_sparse_image(dev_desc, &info, cmd, download_buffer, + download_bytes); + else + write_raw_image(dev_desc, &info, cmd, download_buffer, + download_bytes); +} diff --git a/common/fdt_support.c b/common/fdt_support.c index ce7527a931..891fcac08e 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -16,10 +17,36 @@ #include #include -/* - * Global data (for the gd->bd) +/** + * fdt_getprop_u32_default_node - Return a node's property or a default + * + * @fdt: ptr to device tree + * @off: offset of node + * @cell: cell offset in property + * @prop: property name + * @dflt: default value if the property isn't found + * + * Convenience function to return a node's property or a default value if + * the property doesn't exist. */ -DECLARE_GLOBAL_DATA_PTR; +u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell, + const char *prop, const u32 dflt) +{ + const fdt32_t *val; + int len; + + val = fdt_getprop(fdt, off, prop, &len); + + /* Check if property exists */ + if (!val) + return dflt; + + /* Check if property is long enough */ + if (len < ((cell + 1) * sizeof(uint32_t))) + return dflt; + + return fdt32_to_cpu(*val); +} /** * fdt_getprop_u32_default - Find a node and return it's property or a default @@ -35,18 +62,13 @@ DECLARE_GLOBAL_DATA_PTR; u32 fdt_getprop_u32_default(const void *fdt, const char *path, const char *prop, const u32 dflt) { - const fdt32_t *val; int off; off = fdt_path_offset(fdt, path); if (off < 0) return dflt; - val = fdt_getprop(fdt, off, prop, NULL); - if (val) - return fdt32_to_cpu(*val); - else - return dflt; + return fdt_getprop_u32_default_node(fdt, off, 0, prop, dflt); } /** @@ -75,9 +97,39 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, return fdt_setprop(fdt, nodeoff, prop, val, len); } -#ifdef CONFIG_OF_STDOUT_VIA_ALIAS +/** + * fdt_find_or_add_subnode() - find or possibly add a subnode of a given node + * + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node with a given name. + * If the subnode does not exist, it will be created. + */ +int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name) +{ + int offset; + + offset = fdt_subnode_offset(fdt, parentoffset, name); -#ifdef CONFIG_CONS_INDEX + if (offset == -FDT_ERR_NOTFOUND) + offset = fdt_add_subnode(fdt, parentoffset, name); + + if (offset < 0) + printf("%s: %s: %s\n", __func__, name, fdt_strerror(offset)); + + return offset; +} + +/* rename to CONFIG_OF_STDOUT_PATH ? */ +#if defined(OF_STDOUT_PATH) +static int fdt_fixup_stdout(void *fdt, int chosenoff) +{ + return fdt_setprop(fdt, chosenoff, "linux,stdout-path", + OF_STDOUT_PATH, strlen(OF_STDOUT_PATH) + 1); +} +#elif defined(CONFIG_OF_STDOUT_VIA_ALIAS) && defined(CONFIG_CONS_INDEX) static void fdt_fill_multisername(char *sername, size_t maxlen) { const char *outname = stdio_devices[stdout]->name; @@ -89,66 +141,75 @@ static void fdt_fill_multisername(char *sername, size_t maxlen) if (strcmp(outname + 1, "serial") > 0) strncpy(sername, outname + 1, maxlen); } -#endif static int fdt_fixup_stdout(void *fdt, int chosenoff) { - int err = 0; -#ifdef CONFIG_CONS_INDEX - int node; + int err; + int aliasoff; char sername[9] = { 0 }; - const char *path; + const void *path; + int len; + char tmp[256]; /* long enough */ fdt_fill_multisername(sername, sizeof(sername) - 1); if (!sername[0]) sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1); - err = node = fdt_path_offset(fdt, "/aliases"); - if (node >= 0) { - int len; - path = fdt_getprop(fdt, node, sername, &len); - if (path) { - char *p = malloc(len); - err = -FDT_ERR_NOSPACE; - if (p) { - memcpy(p, path, len); - err = fdt_setprop(fdt, chosenoff, - "linux,stdout-path", p, len); - free(p); - } - } else { - err = len; - } + aliasoff = fdt_path_offset(fdt, "/aliases"); + if (aliasoff < 0) { + err = aliasoff; + goto error; } -#endif + + path = fdt_getprop(fdt, aliasoff, sername, &len); + if (!path) { + err = len; + goto error; + } + + /* fdt_setprop may break "path" so we copy it to tmp buffer */ + memcpy(tmp, path, len); + + err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", tmp, len); +error: if (err < 0) printf("WARNING: could not set linux,stdout-path %s.\n", - fdt_strerror(err)); + fdt_strerror(err)); return err; } +#else +static int fdt_fixup_stdout(void *fdt, int chosenoff) +{ + return 0; +} #endif -int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force) +static inline int fdt_setprop_uxx(void *fdt, int nodeoffset, const char *name, + uint64_t val, int is_u64) +{ + if (is_u64) + return fdt_setprop_u64(fdt, nodeoffset, name, val); + else + return fdt_setprop_u32(fdt, nodeoffset, name, (uint32_t)val); +} + + +int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end) { int nodeoffset; int err, j, total; - fdt32_t tmp; - const char *path; + int is_u64; uint64_t addr, size; - /* Find the "chosen" node. */ - nodeoffset = fdt_path_offset (fdt, "/chosen"); + /* just return if the size of initrd is zero */ + if (initrd_start == initrd_end) + return 0; - /* If there is no "chosen" node in the blob return */ - if (nodeoffset < 0) { - printf("fdt_initrd: %s\n", fdt_strerror(nodeoffset)); + /* find or create "/chosen" node. */ + nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen"); + if (nodeoffset < 0) return nodeoffset; - } - - /* just return if initrd_start/end aren't valid */ - if ((initrd_start == 0) || (initrd_end == 0)) - return 0; total = fdt_num_mem_rsv(fdt); @@ -170,37 +231,35 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force) return err; } - path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL); - if ((path == NULL) || force) { - tmp = cpu_to_fdt32(initrd_start); - err = fdt_setprop(fdt, nodeoffset, - "linux,initrd-start", &tmp, sizeof(tmp)); - if (err < 0) { - printf("WARNING: " - "could not set linux,initrd-start %s.\n", - fdt_strerror(err)); - return err; - } - tmp = cpu_to_fdt32(initrd_end); - err = fdt_setprop(fdt, nodeoffset, - "linux,initrd-end", &tmp, sizeof(tmp)); - if (err < 0) { - printf("WARNING: could not set linux,initrd-end %s.\n", - fdt_strerror(err)); + is_u64 = (fdt_address_cells(fdt, 0) == 2); - return err; - } + err = fdt_setprop_uxx(fdt, nodeoffset, "linux,initrd-start", + (uint64_t)initrd_start, is_u64); + + if (err < 0) { + printf("WARNING: could not set linux,initrd-start %s.\n", + fdt_strerror(err)); + return err; + } + + err = fdt_setprop_uxx(fdt, nodeoffset, "linux,initrd-end", + (uint64_t)initrd_end, is_u64); + + if (err < 0) { + printf("WARNING: could not set linux,initrd-end %s.\n", + fdt_strerror(err)); + + return err; } return 0; } -int fdt_chosen(void *fdt, int force) +int fdt_chosen(void *fdt) { int nodeoffset; int err; char *str; /* used to set string properties */ - const char *path; err = fdt_check_header(fdt); if (err < 0) { @@ -208,61 +267,23 @@ int fdt_chosen(void *fdt, int force) return err; } - /* - * Find the "chosen" node. - */ - nodeoffset = fdt_path_offset (fdt, "/chosen"); - - /* - * If there is no "chosen" node in the blob, create it. - */ - if (nodeoffset < 0) { - /* - * Create a new node "/chosen" (offset 0 is root level) - */ - nodeoffset = fdt_add_subnode(fdt, 0, "chosen"); - if (nodeoffset < 0) { - printf("WARNING: could not create /chosen %s.\n", - fdt_strerror(nodeoffset)); - return nodeoffset; - } - } + /* find or create "/chosen" node. */ + nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen"); + if (nodeoffset < 0) + return nodeoffset; - /* - * Create /chosen properites that don't exist in the fdt. - * If the property exists, update it only if the "force" parameter - * is true. - */ str = getenv("bootargs"); - if (str != NULL) { - path = fdt_getprop(fdt, nodeoffset, "bootargs", NULL); - if ((path == NULL) || force) { - err = fdt_setprop(fdt, nodeoffset, - "bootargs", str, strlen(str)+1); - if (err < 0) - printf("WARNING: could not set bootargs %s.\n", - fdt_strerror(err)); + if (str) { + err = fdt_setprop(fdt, nodeoffset, "bootargs", str, + strlen(str) + 1); + if (err < 0) { + printf("WARNING: could not set bootargs %s.\n", + fdt_strerror(err)); + return err; } } -#ifdef CONFIG_OF_STDOUT_VIA_ALIAS - path = fdt_getprop(fdt, nodeoffset, "linux,stdout-path", NULL); - if ((path == NULL) || force) - err = fdt_fixup_stdout(fdt, nodeoffset); -#endif - -#ifdef OF_STDOUT_PATH - path = fdt_getprop(fdt, nodeoffset, "linux,stdout-path", NULL); - if ((path == NULL) || force) { - err = fdt_setprop(fdt, nodeoffset, - "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1); - if (err < 0) - printf("WARNING: could not set linux,stdout-path %s.\n", - fdt_strerror(err)); - } -#endif - - return err; + return fdt_fixup_stdout(fdt, nodeoffset); } void do_fixup_by_path(void *fdt, const char *path, const char *prop, @@ -344,31 +365,31 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat, } /* - * Get cells len in bytes - * if #NNNN-cells property is 2 then len is 8 - * otherwise len is 4 + * fdt_pack_reg - pack address and size array into the "reg"-suitable stream */ -static int get_cells_len(void *blob, char *nr_cells_name) +static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size, + int n) { - const fdt32_t *cell; - - cell = fdt_getprop(blob, 0, nr_cells_name, NULL); - if (cell && fdt32_to_cpu(*cell) == 2) - return 8; + int i; + int address_cells = fdt_address_cells(fdt, 0); + int size_cells = fdt_size_cells(fdt, 0); + char *p = buf; - return 4; -} + for (i = 0; i < n; i++) { + if (address_cells == 2) + *(fdt64_t *)p = cpu_to_fdt64(address[i]); + else + *(fdt32_t *)p = cpu_to_fdt32(address[i]); + p += 4 * address_cells; -/* - * Write a 4 or 8 byte big endian cell - */ -static void write_cell(u8 *addr, u64 val, int size) -{ - int shift = (size - 1) * 8; - while (size-- > 0) { - *addr++ = (val >> shift) & 0xff; - shift -= 8; + if (size_cells == 2) + *(fdt64_t *)p = cpu_to_fdt64(size[i]); + else + *(fdt32_t *)p = cpu_to_fdt32(size[i]); + p += 4 * size_cells; } + + return p - (char *)buf; } #ifdef CONFIG_NR_DRAM_BANKS @@ -379,9 +400,8 @@ static void write_cell(u8 *addr, u64 val, int size) int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) { int err, nodeoffset; - int addr_cell_len, size_cell_len, len; + int len; u8 tmp[MEMORY_BANKS_MAX * 16]; /* Up to 64-bit address + 64-bit size */ - int bank; if (banks > MEMORY_BANKS_MAX) { printf("%s: num banks %d exceeds hardcoded limit %d." @@ -396,15 +416,11 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) return err; } - /* update, or add and update /memory node */ - nodeoffset = fdt_path_offset(blob, "/memory"); - if (nodeoffset < 0) { - nodeoffset = fdt_add_subnode(blob, 0, "memory"); - if (nodeoffset < 0) - printf("WARNING: could not create /memory: %s.\n", - fdt_strerror(nodeoffset)); - return nodeoffset; - } + /* find or create "/memory" node. */ + nodeoffset = fdt_find_or_add_subnode(blob, 0, "memory"); + if (nodeoffset < 0) + return nodeoffset; + err = fdt_setprop(blob, nodeoffset, "device_type", "memory", sizeof("memory")); if (err < 0) { @@ -413,16 +429,7 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) return err; } - addr_cell_len = get_cells_len(blob, "#address-cells"); - size_cell_len = get_cells_len(blob, "#size-cells"); - - for (bank = 0, len = 0; bank < banks; bank++) { - write_cell(tmp + len, start[bank], addr_cell_len); - len += addr_cell_len; - - write_cell(tmp + len, size[bank], size_cell_len); - len += size_cell_len; - } + len = fdt_pack_reg(blob, tmp, start, size, banks); err = fdt_setprop(blob, nodeoffset, "reg", tmp, len); if (err < 0) { @@ -450,8 +457,18 @@ void fdt_fixup_ethernet(void *fdt) if (node < 0) return; + if (!getenv("ethaddr")) { + if (getenv("usbethaddr")) { + strcpy(mac, "usbethaddr"); + } else { + debug("No ethernet MAC Address defined\n"); + return; + } + } else { + strcpy(mac, "ethaddr"); + } + i = 0; - strcpy(mac, "ethaddr"); while ((tmp = getenv(mac)) != NULL) { sprintf(enet, "ethernet%d", i); path = fdt_getprop(fdt, node, enet, NULL); @@ -476,7 +493,7 @@ void fdt_fixup_ethernet(void *fdt) } /* Resize the fdt to its actual size + a bit of padding */ -int fdt_resize(void *blob) +int fdt_shrink_to_minimum(void *blob) { int i; uint64_t addr, size; @@ -686,7 +703,7 @@ struct reg_cell { unsigned int r1; }; -int fdt_del_subnodes(const void *blob, int parent_offset) +static int fdt_del_subnodes(const void *blob, int parent_offset) { int off, ndepth; int ret; @@ -694,18 +711,20 @@ int fdt_del_subnodes(const void *blob, int parent_offset) for (ndepth = 0, off = fdt_next_node(blob, parent_offset, &ndepth); (off >= 0) && (ndepth > 0); off = fdt_next_node(blob, off, &ndepth)) { - if (ndepth == 1) { - debug("delete %s: offset: %x\n", - fdt_get_name(blob, off, 0), off); - ret = fdt_del_node((void *)blob, off); - if (ret < 0) { - printf("Can't delete node: %s\n", - fdt_strerror(ret)); - return ret; - } else { - ndepth = 0; - off = parent_offset; - } + if (ndepth != 1) + continue; + if (fdt_getprop(blob, off, "compatible", NULL)) + continue; + debug("delete %s: offset: %x\n", + fdt_get_name(blob, off, 0), off); + ret = fdt_del_node((void *)blob, off); + if (ret < 0) { + printf("Can't delete node: %s\n", + fdt_strerror(ret)); + return ret; + } else { + ndepth = 0; + off = parent_offset; } } return 0; @@ -715,11 +734,14 @@ int fdt_del_partitions(void *blob, int parent_offset) { const void *prop; int ndepth = 0; - int off; + int off = parent_offset; int ret; - off = fdt_next_node(blob, parent_offset, &ndepth); - if (off > 0 && ndepth == 1) { + while ((off = fdt_next_node(blob, off, &ndepth)) > 0) { + if (ndepth != 1) + continue; + if (fdt_getprop(blob, off, "compatible", NULL)) + continue; prop = fdt_getprop(blob, off, "label", NULL); if (prop == NULL) { /* @@ -745,7 +767,7 @@ int fdt_node_set_part_info(void *blob, int parent_offset, struct list_head *pentry; struct part_info *part; struct reg_cell cell; - int off, ndepth = 0; + int off = parent_offset, ndepth = 0; int part_num, ret; char buf[64]; @@ -757,21 +779,25 @@ int fdt_node_set_part_info(void *blob, int parent_offset, * Check if it is nand {}; subnode, adjust * the offset in this case */ - off = fdt_next_node(blob, parent_offset, &ndepth); - if (off > 0 && ndepth == 1) + while ((off = fdt_next_node(blob, off, &ndepth)) > 0) { + if (ndepth != 1) + continue; + if (fdt_getprop(blob, off, "compatible", NULL)) + continue; parent_offset = off; - + break; + } part_num = 0; list_for_each_prev(pentry, &dev->parts) { int newoff; part = list_entry(pentry, struct part_info, link); - debug("%2d: %-20s0x%08x\t0x%08x\t%d\n", + debug("%2d: %-20s0x%08llx\t0x%08llx\t%d\n", part_num, part->name, part->size, part->offset, part->mask_flags); - sprintf(buf, "partition@%x", part->offset); + sprintf(buf, "partition@%llx", part->offset); add_sub: ret = fdt_add_subnode(blob, parent_offset, buf); if (ret == -FDT_ERR_NOSPACE) { @@ -899,17 +925,6 @@ void fdt_del_node_and_alias(void *blob, const char *alias) fdt_delprop(blob, off, alias); } -/* Helper to read a big number; size is in cells (not bytes) */ -static inline u64 of_read_number(const fdt32_t *cell, int size) -{ - u64 r = 0; - while (size--) - r = (r << 32) | fdt32_to_cpu(*(cell++)); - return r; -} - -#define PRu64 "%llx" - /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_BAD_ADDR ((u64)-1) @@ -941,18 +956,13 @@ struct of_bus { }; /* Default translator (generic bus) */ -static void of_bus_default_count_cells(void *blob, int parentoffset, +void of_bus_default_count_cells(void *blob, int parentoffset, int *addrc, int *sizec) { const fdt32_t *prop; - if (addrc) { - prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL); - if (prop) - *addrc = be32_to_cpup(prop); - else - *addrc = 2; - } + if (addrc) + *addrc = fdt_address_cells(blob, parentoffset); if (sizec) { prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL); @@ -972,8 +982,8 @@ static u64 of_bus_default_map(fdt32_t *addr, const fdt32_t *range, s = of_read_number(range + na + pna, ns); da = of_read_number(addr, na); - debug("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n", - cp, s, da); + debug("OF: default map, cp=%" PRIu64 ", s=%" PRIu64 + ", da=%" PRIu64 "\n", cp, s, da); if (da < cp || da >= (cp + s)) return OF_BAD_ADDR; @@ -1051,7 +1061,7 @@ static int of_translate_one(void * blob, int parent, struct of_bus *bus, finish: of_dump_addr("OF: parent translation for:", addr, pna); - debug("OF: with offset: "PRu64"\n", offset); + debug("OF: with offset: %" PRIu64 "\n", offset); /* Translate it into parent bus space */ return pbus->translate(addr, offset, pna); @@ -1177,7 +1187,8 @@ int fdt_node_offset_by_compat_reg(void *blob, const char *compat, */ int fdt_alloc_phandle(void *blob) { - int offset, phandle = 0; + int offset; + uint32_t phandle = 0; for (offset = fdt_next_node(blob, -1, NULL); offset >= 0; offset = fdt_next_node(blob, offset, NULL)) { @@ -1379,9 +1390,9 @@ int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr) dt_addr = fdt_translate_address(fdt, node, reg); if (addr != dt_addr) { - printf("Warning: U-Boot configured device %s at address %llx,\n" - " but the device tree has it address %llx.\n", - alias, addr, dt_addr); + printf("Warning: U-Boot configured device %s at address %" + PRIx64 ",\n but the device tree has it address %" + PRIx64 ".\n", alias, addr, dt_addr); return 0; } @@ -1397,13 +1408,165 @@ u64 fdt_get_base_address(void *fdt, int node) u32 naddr; const fdt32_t *prop; - prop = fdt_getprop(fdt, node, "#address-cells", &size); - if (prop && size == 4) - naddr = be32_to_cpup(prop); - else - naddr = 2; + naddr = fdt_address_cells(fdt, node); prop = fdt_getprop(fdt, node, "ranges", &size); return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0; } + +/* + * Read a property of size . Currently only supports 1 or 2 cells. + */ +static int fdt_read_prop(const fdt32_t *prop, int prop_len, int cell_off, + uint64_t *val, int cells) +{ + const fdt32_t *prop32 = &prop[cell_off]; + const fdt64_t *prop64 = (const fdt64_t *)&prop[cell_off]; + + if ((cell_off + cells) > prop_len) + return -FDT_ERR_NOSPACE; + + switch (cells) { + case 1: + *val = fdt32_to_cpu(*prop32); + break; + case 2: + *val = fdt64_to_cpu(*prop64); + break; + default: + return -FDT_ERR_NOSPACE; + } + + return 0; +} + +/** + * fdt_read_range - Read a node's n'th range property + * + * @fdt: ptr to device tree + * @node: offset of node + * @n: range index + * @child_addr: pointer to storage for the "child address" field + * @addr: pointer to storage for the CPU view translated physical start + * @len: pointer to storage for the range length + * + * Convenience function that reads and interprets a specific range out of + * a number of the "ranges" property array. + */ +int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr, + uint64_t *addr, uint64_t *len) +{ + int pnode = fdt_parent_offset(fdt, node); + const fdt32_t *ranges; + int pacells; + int acells; + int scells; + int ranges_len; + int cell = 0; + int r = 0; + + /* + * The "ranges" property is an array of + * { } + * + * All 3 elements can span a diffent number of cells. Fetch their size. + */ + pacells = fdt_getprop_u32_default_node(fdt, pnode, 0, "#address-cells", 1); + acells = fdt_getprop_u32_default_node(fdt, node, 0, "#address-cells", 1); + scells = fdt_getprop_u32_default_node(fdt, node, 0, "#size-cells", 1); + + /* Now try to get the ranges property */ + ranges = fdt_getprop(fdt, node, "ranges", &ranges_len); + if (!ranges) + return -FDT_ERR_NOTFOUND; + ranges_len /= sizeof(uint32_t); + + /* Jump to the n'th entry */ + cell = n * (pacells + acells + scells); + + /* Read */ + if (child_addr) { + r = fdt_read_prop(ranges, ranges_len, cell, child_addr, + acells); + if (r) + return r; + } + cell += acells; + + /* Read */ + if (addr) + *addr = fdt_translate_address(fdt, node, ranges + cell); + cell += pacells; + + /* Read */ + if (len) { + r = fdt_read_prop(ranges, ranges_len, cell, len, scells); + if (r) + return r; + } + + return 0; +} + +/** + * fdt_setup_simplefb_node - Fill and enable a simplefb node + * + * @fdt: ptr to device tree + * @node: offset of the simplefb node + * @base_address: framebuffer base address + * @width: width in pixels + * @height: height in pixels + * @stride: bytes per line + * @format: pixel format string + * + * Convenience function to fill and enable a simplefb node. + */ +int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, + u32 height, u32 stride, const char *format) +{ + char name[32]; + fdt32_t cells[4]; + int i, addrc, sizec, ret; + + of_bus_default_count_cells(fdt, fdt_parent_offset(fdt, node), + &addrc, &sizec); + i = 0; + if (addrc == 2) + cells[i++] = cpu_to_fdt32(base_address >> 32); + cells[i++] = cpu_to_fdt32(base_address); + if (sizec == 2) + cells[i++] = 0; + cells[i++] = cpu_to_fdt32(height * stride); + + ret = fdt_setprop(fdt, node, "reg", cells, sizeof(cells[0]) * i); + if (ret < 0) + return ret; + + snprintf(name, sizeof(name), "framebuffer@%llx", base_address); + ret = fdt_set_name(fdt, node, name); + if (ret < 0) + return ret; + + ret = fdt_setprop_u32(fdt, node, "width", width); + if (ret < 0) + return ret; + + ret = fdt_setprop_u32(fdt, node, "height", height); + if (ret < 0) + return ret; + + ret = fdt_setprop_u32(fdt, node, "stride", stride); + if (ret < 0) + return ret; + + ret = fdt_setprop_string(fdt, node, "format", format); + if (ret < 0) + return ret; + + ret = fdt_setprop_string(fdt, node, "status", "okay"); + if (ret < 0) + return ret; + + return 0; +} diff --git a/common/flash.c b/common/flash.c index f1440c2c18..fa33f03d2e 100644 --- a/common/flash.c +++ b/common/flash.c @@ -88,7 +88,6 @@ flash_protect (int flag, ulong from, ulong to, flash_info_t *info) flash_info_t * addr2info (ulong addr) { -#ifndef CONFIG_SPD823TS flash_info_t *info; int i; @@ -104,7 +103,6 @@ addr2info (ulong addr) return (info); } } -#endif /* CONFIG_SPD823TS */ return (NULL); } @@ -125,9 +123,6 @@ addr2info (ulong addr) int flash_write (char *src, ulong addr, ulong cnt) { -#ifdef CONFIG_SPD823TS - return (ERR_TIMOUT); /* any other error codes are possible as well */ -#else int i; ulong end = addr + cnt - 1; flash_info_t *info_first = addr2info (addr); @@ -181,7 +176,6 @@ flash_write (char *src, ulong addr, ulong cnt) #endif /* CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE */ return (ERR_OK); -#endif /* CONFIG_SPD823TS */ } /*----------------------------------------------------------------------- diff --git a/common/hash.c b/common/hash.c index 722c40b3f3..d154d029e9 100644 --- a/common/hash.c +++ b/common/hash.c @@ -10,14 +10,106 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef USE_HOSTCC #include #include +#include #include -#include -#include -#include #include #include +#else +#include "mkimage.h" +#include +#include +#endif /* !USE_HOSTCC*/ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SHA1 +static int hash_init_sha1(struct hash_algo *algo, void **ctxp) +{ + sha1_context *ctx = malloc(sizeof(sha1_context)); + sha1_starts(ctx); + *ctxp = ctx; + return 0; +} + +static int hash_update_sha1(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last) +{ + sha1_update((sha1_context *)ctx, buf, size); + return 0; +} + +static int hash_finish_sha1(struct hash_algo *algo, void *ctx, void *dest_buf, + int size) +{ + if (size < algo->digest_size) + return -1; + + sha1_finish((sha1_context *)ctx, dest_buf); + free(ctx); + return 0; +} +#endif + +#ifdef CONFIG_SHA256 +static int hash_init_sha256(struct hash_algo *algo, void **ctxp) +{ + sha256_context *ctx = malloc(sizeof(sha256_context)); + sha256_starts(ctx); + *ctxp = ctx; + return 0; +} + +static int hash_update_sha256(struct hash_algo *algo, void *ctx, + const void *buf, unsigned int size, int is_last) +{ + sha256_update((sha256_context *)ctx, buf, size); + return 0; +} + +static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void + *dest_buf, int size) +{ + if (size < algo->digest_size) + return -1; + + sha256_finish((sha256_context *)ctx, dest_buf); + free(ctx); + return 0; +} +#endif + +static int hash_init_crc32(struct hash_algo *algo, void **ctxp) +{ + uint32_t *ctx = malloc(sizeof(uint32_t)); + *ctx = 0; + *ctxp = ctx; + return 0; +} + +static int hash_update_crc32(struct hash_algo *algo, void *ctx, + const void *buf, unsigned int size, int is_last) +{ + *((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), buf, size); + return 0; +} + +static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf, + int size) +{ + if (size < algo->digest_size) + return -1; + + *((uint32_t *)dest_buf) = *((uint32_t *)ctx); + free(ctx); + return 0; +} /* * These are the hash algorithms we support. Chips which support accelerated @@ -42,19 +134,16 @@ static struct hash_algo hash_algo[] = { CHUNKSZ_SHA256, }, #endif - /* - * This is CONFIG_CMD_SHA1SUM instead of CONFIG_SHA1 since otherwise - * it bloats the code for boards which use SHA1 but not the 'hash' - * or 'sha1sum' commands. - */ -#ifdef CONFIG_CMD_SHA1SUM +#ifdef CONFIG_SHA1 { "sha1", SHA1_SUM_LEN, sha1_csum_wd, CHUNKSZ_SHA1, + hash_init_sha1, + hash_update_sha1, + hash_finish_sha1, }, -#define MULTI_HASH #endif #ifdef CONFIG_SHA256 { @@ -62,17 +151,26 @@ static struct hash_algo hash_algo[] = { SHA256_SUM_LEN, sha256_csum_wd, CHUNKSZ_SHA256, + hash_init_sha256, + hash_update_sha256, + hash_finish_sha256, }, -#define MULTI_HASH #endif { "crc32", 4, crc32_wd_buf, CHUNKSZ_CRC32, + hash_init_crc32, + hash_update_crc32, + hash_finish_crc32, }, }; +#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM) +#define MULTI_HASH +#endif + #if defined(CONFIG_HASH_VERIFY) || defined(CONFIG_CMD_HASH) #define MULTI_HASH #endif @@ -84,6 +182,40 @@ static struct hash_algo hash_algo[] = { #define multi_hash() 0 #endif +int hash_lookup_algo(const char *algo_name, struct hash_algo **algop) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(hash_algo); i++) { + if (!strcmp(algo_name, hash_algo[i].name)) { + *algop = &hash_algo[i]; + return 0; + } + } + + debug("Unknown hash algorithm '%s'\n", algo_name); + return -EPROTONOSUPPORT; +} + +int hash_progressive_lookup_algo(const char *algo_name, + struct hash_algo **algop) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(hash_algo); i++) { + if (!strcmp(algo_name, hash_algo[i].name)) { + if (hash_algo[i].hash_init) { + *algop = &hash_algo[i]; + return 0; + } + } + } + + debug("Unknown hash algorithm '%s'\n", algo_name); + return -EPROTONOSUPPORT; +} + +#ifndef USE_HOSTCC /** * store_result: Store the resulting sum to an address or variable * @@ -95,7 +227,7 @@ static struct hash_algo hash_algo[] = { * @allow_env_vars: non-zero to permit storing the result to an * variable environment */ -static void store_result(struct hash_algo *algo, const u8 *sum, +static void store_result(struct hash_algo *algo, const uint8_t *sum, const char *dest, int allow_env_vars) { unsigned int i; @@ -122,7 +254,7 @@ static void store_result(struct hash_algo *algo, const u8 *sum, sprintf(str_ptr, "%02x", sum[i]); str_ptr += 2; } - str_ptr = '\0'; + *str_ptr = '\0'; setenv(dest, str_output); } else { ulong addr; @@ -151,8 +283,8 @@ static void store_result(struct hash_algo *algo, const u8 *sum, * address, and the * prefix is not expected. * @return 0 if ok, non-zero on error */ -static int parse_verify_sum(struct hash_algo *algo, char *verify_str, u8 *vsum, - int allow_env_vars) +static int parse_verify_sum(struct hash_algo *algo, char *verify_str, + uint8_t *vsum, int allow_env_vars) { int env_var = 0; @@ -164,7 +296,7 @@ static int parse_verify_sum(struct hash_algo *algo, char *verify_str, u8 *vsum, env_var = 1; } - if (env_var) { + if (!env_var) { ulong addr; void *buf; @@ -204,20 +336,7 @@ static int parse_verify_sum(struct hash_algo *algo, char *verify_str, u8 *vsum, return 0; } -static struct hash_algo *find_hash_algo(const char *name) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(hash_algo); i++) { - if (!strcmp(name, hash_algo[i].name)) - return &hash_algo[i]; - } - - return NULL; -} - -static void show_hash(struct hash_algo *algo, ulong addr, ulong len, - u8 *output) +void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output) { int i; @@ -230,12 +349,12 @@ int hash_block(const char *algo_name, const void *data, unsigned int len, uint8_t *output, int *output_size) { struct hash_algo *algo; + int ret; + + ret = hash_lookup_algo(algo_name, &algo); + if (ret) + return ret; - algo = find_hash_algo(algo_name); - if (!algo) { - debug("Unknown hash algorithm '%s'\n", algo_name); - return -EPROTONOSUPPORT; - } if (output_size && *output_size < algo->digest_size) { debug("Output buffer size %d too small (need %d bytes)", *output_size, algo->digest_size); @@ -253,7 +372,7 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, { ulong addr, len; - if (argc < 2) + if ((argc < 2) || ((flags & HASH_FLAG_VERIFY) && (argc < 3))) return CMD_RET_USAGE; addr = simple_strtoul(*argv++, NULL, 16); @@ -261,12 +380,11 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, if (multi_hash()) { struct hash_algo *algo; - u8 output[HASH_MAX_DIGEST_SIZE]; - u8 vsum[HASH_MAX_DIGEST_SIZE]; + uint8_t output[HASH_MAX_DIGEST_SIZE]; + uint8_t vsum[HASH_MAX_DIGEST_SIZE]; void *buf; - algo = find_hash_algo(algo_name); - if (!algo) { + if (hash_lookup_algo(algo_name, &algo)) { printf("Unknown hash algorithm '%s'\n", algo_name); return CMD_RET_USAGE; } @@ -287,8 +405,6 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, #else if (0) { #endif - if (!argc) - return CMD_RET_USAGE; if (parse_verify_sum(algo, *argv, vsum, flags & HASH_FLAG_ENV)) { printf("ERROR: %s does not contain a valid " @@ -298,7 +414,7 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, if (memcmp(output, vsum, algo->digest_size) != 0) { int i; - show_hash(algo, addr, len, output); + hash_show(algo, addr, len, output); printf(" != "); for (i = 0; i < algo->digest_size; i++) printf("%02x", vsum[i]); @@ -306,7 +422,7 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, return 1; } } else { - show_hash(algo, addr, len, output); + hash_show(algo, addr, len, output); printf("\n"); if (argc) { @@ -325,11 +441,12 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, printf("CRC32 for %08lx ... %08lx ==> %08lx\n", addr, addr + len - 1, crc); - if (argc > 3) { - ptr = (ulong *)simple_strtoul(argv[3], NULL, 16); + if (argc >= 3) { + ptr = (ulong *)simple_strtoul(argv[0], NULL, 16); *ptr = crc; } } return 0; } +#endif diff --git a/common/hush.c b/common/hush.c deleted file mode 100644 index 3f3a79c508..0000000000 --- a/common/hush.c +++ /dev/null @@ -1,3668 +0,0 @@ -/* - * sh.c -- a prototype Bourne shell grammar parser - * Intended to follow the original Thompson and Ritchie - * "small and simple is beautiful" philosophy, which - * incidentally is a good match to today's BusyBox. - * - * Copyright (C) 2000,2001 Larry Doolittle - * - * Credits: - * The parser routines proper are all original material, first - * written Dec 2000 and Jan 2001 by Larry Doolittle. - * The execution engine, the builtins, and much of the underlying - * support has been adapted from busybox-0.49pre's lash, - * which is Copyright (C) 2000 by Lineo, Inc., and - * written by Erik Andersen , . - * That, in turn, is based in part on ladsh.c, by Michael K. Johnson and - * Erik W. Troan, which they placed in the public domain. I don't know - * how much of the Johnson/Troan code has survived the repeated rewrites. - * Other credits: - * b_addchr() derived from similar w_addchar function in glibc-2.2 - * setup_redirect(), redirect_opt_num(), and big chunks of main() - * and many builtins derived from contributions by Erik Andersen - * miscellaneous bugfixes from Matt Kraai - * - * There are two big (and related) architecture differences between - * this parser and the lash parser. One is that this version is - * actually designed from the ground up to understand nearly all - * of the Bourne grammar. The second, consequential change is that - * the parser and input reader have been turned inside out. Now, - * the parser is in control, and asks for input as needed. The old - * way had the input reader in control, and it asked for parsing to - * take place as needed. The new way makes it much easier to properly - * handle the recursion implicit in the various substitutions, especially - * across continuation lines. - * - * Bash grammar not implemented: (how many of these were in original sh?) - * $@ (those sure look like weird quoting rules) - * $_ - * ! negation operator for pipes - * &> and >& redirection of stdout+stderr - * Brace Expansion - * Tilde Expansion - * fancy forms of Parameter Expansion - * aliases - * Arithmetic Expansion - * <(list) and >(list) Process Substitution - * reserved words: case, esac, select, function - * Here Documents ( << word ) - * Functions - * Major bugs: - * job handling woefully incomplete and buggy - * reserved word execution woefully incomplete and buggy - * to-do: - * port selected bugfixes from post-0.49 busybox lash - done? - * finish implementing reserved words: for, while, until, do, done - * change { and } from special chars to reserved words - * builtins: break, continue, eval, return, set, trap, ulimit - * test magic exec - * handle children going into background - * clean up recognition of null pipes - * check setting of global_argc and global_argv - * control-C handling, probably with longjmp - * follow IFS rules more precisely, including update semantics - * figure out what to do with backslash-newline - * explain why we use signal instead of sigaction - * propagate syntax errors, die on resource errors? - * continuation lines, both explicit and implicit - done? - * memory leak finding and plugging - done? - * more testing, especially quoting rules and redirection - * document how quoting rules not precisely followed for variable assignments - * maybe change map[] to use 2-bit entries - * (eventually) remove all the printf's - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define __U_BOOT__ -#ifdef __U_BOOT__ -#include /* malloc, free, realloc*/ -#include /* isalpha, isdigit */ -#include /* readline */ -#include -#include /* find_cmd */ -#ifndef CONFIG_SYS_PROMPT_HUSH_PS2 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif -#endif -#ifndef __U_BOOT__ -#include /* isalpha, isdigit */ -#include /* getpid */ -#include /* getenv, atoi */ -#include /* strchr */ -#include /* popen etc. */ -#include /* glob, of course */ -#include /* va_list */ -#include -#include -#include /* should be pretty obvious */ - -#include /* ulimit */ -#include -#include -#include - -/* #include */ - -#if 1 -#include "busybox.h" -#include "cmdedit.h" -#else -#define applet_name "hush" -#include "standalone.h" -#define hush_main main -#undef CONFIG_FEATURE_SH_FANCY_PROMPT -#define BB_BANNER -#endif -#endif -#define SPECIAL_VAR_SYMBOL 03 -#define SUBSTED_VAR_SYMBOL 04 -#ifndef __U_BOOT__ -#define FLAG_EXIT_FROM_LOOP 1 -#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ -#define FLAG_REPARSING (1 << 2) /* >= 2nd pass */ - -#endif - -#ifdef __U_BOOT__ -DECLARE_GLOBAL_DATA_PTR; - -#define EXIT_SUCCESS 0 -#define EOF -1 -#define syntax() syntax_err() -#define xstrdup strdup -#define error_msg printf -#else -typedef enum { - REDIRECT_INPUT = 1, - REDIRECT_OVERWRITE = 2, - REDIRECT_APPEND = 3, - REDIRECT_HEREIS = 4, - REDIRECT_IO = 5 -} redir_type; - -/* The descrip member of this structure is only used to make debugging - * output pretty */ -struct {int mode; int default_fd; char *descrip;} redir_table[] = { - { 0, 0, "()" }, - { O_RDONLY, 0, "<" }, - { O_CREAT|O_TRUNC|O_WRONLY, 1, ">" }, - { O_CREAT|O_APPEND|O_WRONLY, 1, ">>" }, - { O_RDONLY, -1, "<<" }, - { O_RDWR, 1, "<>" } -}; -#endif - -typedef enum { - PIPE_SEQ = 1, - PIPE_AND = 2, - PIPE_OR = 3, - PIPE_BG = 4, -} pipe_style; - -/* might eventually control execution */ -typedef enum { - RES_NONE = 0, - RES_IF = 1, - RES_THEN = 2, - RES_ELIF = 3, - RES_ELSE = 4, - RES_FI = 5, - RES_FOR = 6, - RES_WHILE = 7, - RES_UNTIL = 8, - RES_DO = 9, - RES_DONE = 10, - RES_XXXX = 11, - RES_IN = 12, - RES_SNTX = 13 -} reserved_style; -#define FLAG_END (1<, but protected with __USE_GNU */ -#endif - -/* "globals" within this file */ -static uchar *ifs; -static char map[256]; -#ifndef __U_BOOT__ -static int fake_mode; -static int interactive; -static struct close_me *close_me_head; -static const char *cwd; -static struct pipe *job_list; -static unsigned int last_bg_pid; -static unsigned int last_jobid; -static unsigned int shell_terminal; -static char *PS1; -static char *PS2; -struct variables shell_ver = { "HUSH_VERSION", "0.01", 1, 1, 0 }; -struct variables *top_vars = &shell_ver; -#else -static int flag_repeat = 0; -static int do_repeat = 0; -static struct variables *top_vars = NULL ; -#endif /*__U_BOOT__ */ - -#define B_CHUNK (100) -#define B_NOSPAC 1 - -typedef struct { - char *data; - int length; - int maxlen; - int quote; - int nonnull; -} o_string; -#define NULL_O_STRING {NULL,0,0,0,0} -/* used for initialization: - o_string foo = NULL_O_STRING; */ - -/* I can almost use ordinary FILE *. Is open_memstream() universally - * available? Where is it documented? */ -struct in_str { - const char *p; -#ifndef __U_BOOT__ - char peek_buf[2]; -#endif - int __promptme; - int promptmode; -#ifndef __U_BOOT__ - FILE *file; -#endif - int (*get) (struct in_str *); - int (*peek) (struct in_str *); -}; -#define b_getch(input) ((input)->get(input)) -#define b_peek(input) ((input)->peek(input)) - -#ifndef __U_BOOT__ -#define JOB_STATUS_FORMAT "[%d] %-22s %.40s\n" - -struct built_in_command { - char *cmd; /* name */ - char *descr; /* description */ - int (*function) (struct child_prog *); /* function ptr */ -}; -#endif - -/* define DEBUG_SHELL for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG_SHELL -#endif - -/* This should be in utility.c */ -#ifdef DEBUG_SHELL -#ifndef __U_BOOT__ -static void debug_printf(const char *format, ...) -{ - va_list args; - va_start(args, format); - vfprintf(stderr, format, args); - va_end(args); -} -#else -#define debug_printf(fmt,args...) printf (fmt ,##args) -#endif -#else -static inline void debug_printf(const char *format, ...) { } -#endif -#define final_printf debug_printf - -#ifdef __U_BOOT__ -static void syntax_err(void) { - printf("syntax error\n"); -} -#else -static void __syntax(char *file, int line) { - error_msg("syntax error %s:%d", file, line); -} -#define syntax() __syntax(__FILE__, __LINE__) -#endif - -#ifdef __U_BOOT__ -static void *xmalloc(size_t size); -static void *xrealloc(void *ptr, size_t size); -#else -/* Index of subroutines: */ -/* function prototypes for builtins */ -static int builtin_cd(struct child_prog *child); -static int builtin_env(struct child_prog *child); -static int builtin_eval(struct child_prog *child); -static int builtin_exec(struct child_prog *child); -static int builtin_exit(struct child_prog *child); -static int builtin_export(struct child_prog *child); -static int builtin_fg_bg(struct child_prog *child); -static int builtin_help(struct child_prog *child); -static int builtin_jobs(struct child_prog *child); -static int builtin_pwd(struct child_prog *child); -static int builtin_read(struct child_prog *child); -static int builtin_set(struct child_prog *child); -static int builtin_shift(struct child_prog *child); -static int builtin_source(struct child_prog *child); -static int builtin_umask(struct child_prog *child); -static int builtin_unset(struct child_prog *child); -static int builtin_not_written(struct child_prog *child); -#endif -/* o_string manipulation: */ -static int b_check_space(o_string *o, int len); -static int b_addchr(o_string *o, int ch); -static void b_reset(o_string *o); -static int b_addqchr(o_string *o, int ch, int quote); -#ifndef __U_BOOT__ -static int b_adduint(o_string *o, unsigned int i); -#endif -/* in_str manipulations: */ -static int static_get(struct in_str *i); -static int static_peek(struct in_str *i); -static int file_get(struct in_str *i); -static int file_peek(struct in_str *i); -#ifndef __U_BOOT__ -static void setup_file_in_str(struct in_str *i, FILE *f); -#else -static void setup_file_in_str(struct in_str *i); -#endif -static void setup_string_in_str(struct in_str *i, const char *s); -#ifndef __U_BOOT__ -/* close_me manipulations: */ -static void mark_open(int fd); -static void mark_closed(int fd); -static void close_all(void); -#endif -/* "run" the final data structures: */ -static char *indenter(int i); -static int free_pipe_list(struct pipe *head, int indent); -static int free_pipe(struct pipe *pi, int indent); -/* really run the final data structures: */ -#ifndef __U_BOOT__ -static int setup_redirects(struct child_prog *prog, int squirrel[]); -#endif -static int run_list_real(struct pipe *pi); -#ifndef __U_BOOT__ -static void pseudo_exec(struct child_prog *child) __attribute__ ((noreturn)); -#endif -static int run_pipe_real(struct pipe *pi); -/* extended glob support: */ -#ifndef __U_BOOT__ -static int globhack(const char *src, int flags, glob_t *pglob); -static int glob_needed(const char *s); -static int xglob(o_string *dest, int flags, glob_t *pglob); -#endif -/* variable assignment: */ -static int is_assignment(const char *s); -/* data structure manipulation: */ -#ifndef __U_BOOT__ -static int setup_redirect(struct p_context *ctx, int fd, redir_type style, struct in_str *input); -#endif -static void initialize_context(struct p_context *ctx); -static int done_word(o_string *dest, struct p_context *ctx); -static int done_command(struct p_context *ctx); -static int done_pipe(struct p_context *ctx, pipe_style type); -/* primary string parsing: */ -#ifndef __U_BOOT__ -static int redirect_dup_num(struct in_str *input); -static int redirect_opt_num(o_string *o); -static int process_command_subs(o_string *dest, struct p_context *ctx, struct in_str *input, int subst_end); -static int parse_group(o_string *dest, struct p_context *ctx, struct in_str *input, int ch); -#endif -static char *lookup_param(char *src); -static char *make_string(char **inp); -static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input); -#ifndef __U_BOOT__ -static int parse_string(o_string *dest, struct p_context *ctx, const char *src); -#endif -static int parse_stream(o_string *dest, struct p_context *ctx, struct in_str *input0, int end_trigger); -/* setup: */ -static int parse_stream_outer(struct in_str *inp, int flag); -#ifndef __U_BOOT__ -static int parse_string_outer(const char *s, int flag); -static int parse_file_outer(FILE *f); -#endif -#ifndef __U_BOOT__ -/* job management: */ -static int checkjobs(struct pipe* fg_pipe); -static void insert_bg_job(struct pipe *pi); -static void remove_bg_job(struct pipe *pi); -#endif -/* local variable support */ -static char **make_list_in(char **inp, char *name); -static char *insert_var_value(char *inp); -static char *insert_var_value_sub(char *inp, int tag_subst); - -#ifndef __U_BOOT__ -/* Table of built-in functions. They can be forked or not, depending on - * context: within pipes, they fork. As simple commands, they do not. - * When used in non-forking context, they can change global variables - * in the parent shell process. If forked, of course they can not. - * For example, 'unset foo | whatever' will parse and run, but foo will - * still be set at the end. */ -static struct built_in_command bltins[] = { - {"bg", "Resume a job in the background", builtin_fg_bg}, - {"break", "Exit for, while or until loop", builtin_not_written}, - {"cd", "Change working directory", builtin_cd}, - {"continue", "Continue for, while or until loop", builtin_not_written}, - {"env", "Print all environment variables", builtin_env}, - {"eval", "Construct and run shell command", builtin_eval}, - {"exec", "Exec command, replacing this shell with the exec'd process", - builtin_exec}, - {"exit", "Exit from shell()", builtin_exit}, - {"export", "Set environment variable", builtin_export}, - {"fg", "Bring job into the foreground", builtin_fg_bg}, - {"jobs", "Lists the active jobs", builtin_jobs}, - {"pwd", "Print current directory", builtin_pwd}, - {"read", "Input environment variable", builtin_read}, - {"return", "Return from a function", builtin_not_written}, - {"set", "Set/unset shell local variables", builtin_set}, - {"shift", "Shift positional parameters", builtin_shift}, - {"trap", "Trap signals", builtin_not_written}, - {"ulimit","Controls resource limits", builtin_not_written}, - {"umask","Sets file creation mask", builtin_umask}, - {"unset", "Unset environment variable", builtin_unset}, - {".", "Source-in and run commands in a file", builtin_source}, - {"help", "List shell built-in commands", builtin_help}, - {NULL, NULL, NULL} -}; - -static const char *set_cwd(void) -{ - if(cwd==unknown) - cwd = NULL; /* xgetcwd(arg) called free(arg) */ - cwd = xgetcwd((char *)cwd); - if (!cwd) - cwd = unknown; - return cwd; -} - -/* built-in 'eval' handler */ -static int builtin_eval(struct child_prog *child) -{ - char *str = NULL; - int rcode = EXIT_SUCCESS; - - if (child->argv[1]) { - str = make_string(child->argv + 1); - parse_string_outer(str, FLAG_EXIT_FROM_LOOP | - FLAG_PARSE_SEMICOLON); - free(str); - rcode = last_return_code; - } - return rcode; -} - -/* built-in 'cd ' handler */ -static int builtin_cd(struct child_prog *child) -{ - char *newdir; - if (child->argv[1] == NULL) - newdir = getenv("HOME"); - else - newdir = child->argv[1]; - if (chdir(newdir)) { - printf("cd: %s: %s\n", newdir, strerror(errno)); - return EXIT_FAILURE; - } - set_cwd(); - return EXIT_SUCCESS; -} - -/* built-in 'env' handler */ -static int builtin_env(struct child_prog *dummy) -{ - char **e = environ; - if (e == NULL) return EXIT_FAILURE; - for (; *e; e++) { - puts(*e); - } - return EXIT_SUCCESS; -} - -/* built-in 'exec' handler */ -static int builtin_exec(struct child_prog *child) -{ - if (child->argv[1] == NULL) - return EXIT_SUCCESS; /* Really? */ - child->argv++; - pseudo_exec(child); - /* never returns */ -} - -/* built-in 'exit' handler */ -static int builtin_exit(struct child_prog *child) -{ - if (child->argv[1] == NULL) - exit(last_return_code); - exit (atoi(child->argv[1])); -} - -/* built-in 'export VAR=value' handler */ -static int builtin_export(struct child_prog *child) -{ - int res = 0; - char *name = child->argv[1]; - - if (name == NULL) { - return (builtin_env(child)); - } - - name = strdup(name); - - if(name) { - char *value = strchr(name, '='); - - if (!value) { - char *tmp; - /* They are exporting something without an =VALUE */ - - value = get_local_var(name); - if (value) { - size_t ln = strlen(name); - - tmp = realloc(name, ln+strlen(value)+2); - if(tmp==NULL) - res = -1; - else { - sprintf(tmp+ln, "=%s", value); - name = tmp; - } - } else { - /* bash does not return an error when trying to export - * an undefined variable. Do likewise. */ - res = 1; - } - } - } - if (res<0) - perror_msg("export"); - else if(res==0) - res = set_local_var(name, 1); - else - res = 0; - free(name); - return res; -} - -/* built-in 'fg' and 'bg' handler */ -static int builtin_fg_bg(struct child_prog *child) -{ - int i, jobnum; - struct pipe *pi=NULL; - - if (!interactive) - return EXIT_FAILURE; - /* If they gave us no args, assume they want the last backgrounded task */ - if (!child->argv[1]) { - for (pi = job_list; pi; pi = pi->next) { - if (pi->jobid == last_jobid) { - break; - } - } - if (!pi) { - error_msg("%s: no current job", child->argv[0]); - return EXIT_FAILURE; - } - } else { - if (sscanf(child->argv[1], "%%%d", &jobnum) != 1) { - error_msg("%s: bad argument '%s'", child->argv[0], child->argv[1]); - return EXIT_FAILURE; - } - for (pi = job_list; pi; pi = pi->next) { - if (pi->jobid == jobnum) { - break; - } - } - if (!pi) { - error_msg("%s: %d: no such job", child->argv[0], jobnum); - return EXIT_FAILURE; - } - } - - if (*child->argv[0] == 'f') { - /* Put the job into the foreground. */ - tcsetpgrp(shell_terminal, pi->pgrp); - } - - /* Restart the processes in the job */ - for (i = 0; i < pi->num_progs; i++) - pi->progs[i].is_stopped = 0; - - if ( (i=kill(- pi->pgrp, SIGCONT)) < 0) { - if (i == ESRCH) { - remove_bg_job(pi); - } else { - perror_msg("kill (SIGCONT)"); - } - } - - pi->stopped_progs = 0; - return EXIT_SUCCESS; -} - -/* built-in 'help' handler */ -static int builtin_help(struct child_prog *dummy) -{ - struct built_in_command *x; - - printf("\nBuilt-in commands:\n"); - printf("-------------------\n"); - for (x = bltins; x->cmd; x++) { - if (x->descr==NULL) - continue; - printf("%s\t%s\n", x->cmd, x->descr); - } - printf("\n\n"); - return EXIT_SUCCESS; -} - -/* built-in 'jobs' handler */ -static int builtin_jobs(struct child_prog *child) -{ - struct pipe *job; - char *status_string; - - for (job = job_list; job; job = job->next) { - if (job->running_progs == job->stopped_progs) - status_string = "Stopped"; - else - status_string = "Running"; - - printf(JOB_STATUS_FORMAT, job->jobid, status_string, job->text); - } - return EXIT_SUCCESS; -} - - -/* built-in 'pwd' handler */ -static int builtin_pwd(struct child_prog *dummy) -{ - puts(set_cwd()); - return EXIT_SUCCESS; -} - -/* built-in 'read VAR' handler */ -static int builtin_read(struct child_prog *child) -{ - int res; - - if (child->argv[1]) { - char string[BUFSIZ]; - char *var = 0; - - string[0] = 0; /* In case stdin has only EOF */ - /* read string */ - fgets(string, sizeof(string), stdin); - chomp(string); - var = malloc(strlen(child->argv[1])+strlen(string)+2); - if(var) { - sprintf(var, "%s=%s", child->argv[1], string); - res = set_local_var(var, 0); - } else - res = -1; - if (res) - fprintf(stderr, "read: %m\n"); - free(var); /* So not move up to avoid breaking errno */ - return res; - } else { - do res=getchar(); while(res!='\n' && res!=EOF); - return 0; - } -} - -/* built-in 'set VAR=value' handler */ -static int builtin_set(struct child_prog *child) -{ - char *temp = child->argv[1]; - struct variables *e; - - if (temp == NULL) - for(e = top_vars; e; e=e->next) - printf("%s=%s\n", e->name, e->value); - else - set_local_var(temp, 0); - - return EXIT_SUCCESS; -} - - -/* Built-in 'shift' handler */ -static int builtin_shift(struct child_prog *child) -{ - int n=1; - if (child->argv[1]) { - n=atoi(child->argv[1]); - } - if (n>=0 && nargv[1] == NULL) - return EXIT_FAILURE; - - /* XXX search through $PATH is missing */ - input = fopen(child->argv[1], "r"); - if (!input) { - error_msg("Couldn't open file '%s'", child->argv[1]); - return EXIT_FAILURE; - } - - /* Now run the file */ - /* XXX argv and argc are broken; need to save old global_argv - * (pointer only is OK!) on this stack frame, - * set global_argv=child->argv+1, recurse, and restore. */ - mark_open(fileno(input)); - status = parse_file_outer(input); - mark_closed(fileno(input)); - fclose(input); - return (status); -} - -static int builtin_umask(struct child_prog *child) -{ - mode_t new_umask; - const char *arg = child->argv[1]; - char *end; - if (arg) { - new_umask=strtoul(arg, &end, 8); - if (*end!='\0' || end == arg) { - return EXIT_FAILURE; - } - } else { - printf("%.3o\n", (unsigned int) (new_umask=umask(0))); - } - umask(new_umask); - return EXIT_SUCCESS; -} - -/* built-in 'unset VAR' handler */ -static int builtin_unset(struct child_prog *child) -{ - /* bash returned already true */ - unset_local_var(child->argv[1]); - return EXIT_SUCCESS; -} - -static int builtin_not_written(struct child_prog *child) -{ - printf("builtin_%s not written\n",child->argv[0]); - return EXIT_FAILURE; -} -#endif - -static int b_check_space(o_string *o, int len) -{ - /* It would be easy to drop a more restrictive policy - * in here, such as setting a maximum string length */ - if (o->length + len > o->maxlen) { - char *old_data = o->data; - /* assert (data == NULL || o->maxlen != 0); */ - o->maxlen += max(2*len, B_CHUNK); - o->data = realloc(o->data, 1 + o->maxlen); - if (o->data == NULL) { - free(old_data); - } - } - return o->data == NULL; -} - -static int b_addchr(o_string *o, int ch) -{ - debug_printf("b_addchr: %c %d %p\n", ch, o->length, o); - if (b_check_space(o, 1)) return B_NOSPAC; - o->data[o->length] = ch; - o->length++; - o->data[o->length] = '\0'; - return 0; -} - -static void b_reset(o_string *o) -{ - o->length = 0; - o->nonnull = 0; - if (o->data != NULL) *o->data = '\0'; -} - -static void b_free(o_string *o) -{ - b_reset(o); - free(o->data); - o->data = NULL; - o->maxlen = 0; -} - -/* My analysis of quoting semantics tells me that state information - * is associated with a destination, not a source. - */ -static int b_addqchr(o_string *o, int ch, int quote) -{ - if (quote && strchr("*?[\\",ch)) { - int rc; - rc = b_addchr(o, '\\'); - if (rc) return rc; - } - return b_addchr(o, ch); -} - -#ifndef __U_BOOT__ -static int b_adduint(o_string *o, unsigned int i) -{ - int r; - char *p = simple_itoa(i); - /* no escape checking necessary */ - do r=b_addchr(o, *p++); while (r==0 && *p); - return r; -} -#endif - -static int static_get(struct in_str *i) -{ - int ch = *i->p++; - if (ch=='\0') return EOF; - return ch; -} - -static int static_peek(struct in_str *i) -{ - return *i->p; -} - -#ifndef __U_BOOT__ -static inline void cmdedit_set_initial_prompt(void) -{ -#ifndef CONFIG_FEATURE_SH_FANCY_PROMPT - PS1 = NULL; -#else - PS1 = getenv("PS1"); - if(PS1==0) - PS1 = "\\w \\$ "; -#endif -} - -static inline void setup_prompt_string(int promptmode, char **prompt_str) -{ - debug_printf("setup_prompt_string %d ",promptmode); -#ifndef CONFIG_FEATURE_SH_FANCY_PROMPT - /* Set up the prompt */ - if (promptmode == 1) { - free(PS1); - PS1=xmalloc(strlen(cwd)+4); - sprintf(PS1, "%s %s", cwd, ( geteuid() != 0 ) ? "$ ":"# "); - *prompt_str = PS1; - } else { - *prompt_str = PS2; - } -#else - *prompt_str = (promptmode==1)? PS1 : PS2; -#endif - debug_printf("result %s\n",*prompt_str); -} -#endif - -static void get_user_input(struct in_str *i) -{ -#ifndef __U_BOOT__ - char *prompt_str; - static char the_command[BUFSIZ]; - - setup_prompt_string(i->promptmode, &prompt_str); -#ifdef CONFIG_FEATURE_COMMAND_EDITING - /* - ** enable command line editing only while a command line - ** is actually being read; otherwise, we'll end up bequeathing - ** atexit() handlers and other unwanted stuff to our - ** child processes (rob@sysgo.de) - */ - cmdedit_read_input(prompt_str, the_command); -#else - fputs(prompt_str, stdout); - fflush(stdout); - the_command[0]=fgetc(i->file); - the_command[1]='\0'; -#endif - fflush(stdout); - i->p = the_command; -#else - int n; - static char the_command[CONFIG_SYS_CBSIZE]; - -#ifdef CONFIG_BOOT_RETRY_TIME -# ifndef CONFIG_RESET_TO_RETRY -# error "This currently only works with CONFIG_RESET_TO_RETRY enabled" -# endif - reset_cmd_timeout(); -#endif - i->__promptme = 1; - if (i->promptmode == 1) { - n = readline(CONFIG_SYS_PROMPT); - } else { - n = readline(CONFIG_SYS_PROMPT_HUSH_PS2); - } -#ifdef CONFIG_BOOT_RETRY_TIME - if (n == -2) { - puts("\nTimeout waiting for command\n"); -# ifdef CONFIG_RESET_TO_RETRY - do_reset(NULL, 0, 0, NULL); -# else -# error "This currently only works with CONFIG_RESET_TO_RETRY enabled" -# endif - } -#endif - if (n == -1 ) { - flag_repeat = 0; - i->__promptme = 0; - } - n = strlen(console_buffer); - console_buffer[n] = '\n'; - console_buffer[n+1]= '\0'; - if (had_ctrlc()) flag_repeat = 0; - clear_ctrlc(); - do_repeat = 0; - if (i->promptmode == 1) { - if (console_buffer[0] == '\n'&& flag_repeat == 0) { - strcpy(the_command,console_buffer); - } - else { - if (console_buffer[0] != '\n') { - strcpy(the_command,console_buffer); - flag_repeat = 1; - } - else { - do_repeat = 1; - } - } - i->p = the_command; - } - else { - if (console_buffer[0] != '\n') { - if (strlen(the_command) + strlen(console_buffer) - < CONFIG_SYS_CBSIZE) { - n = strlen(the_command); - the_command[n-1] = ' '; - strcpy(&the_command[n],console_buffer); - } - else { - the_command[0] = '\n'; - the_command[1] = '\0'; - flag_repeat = 0; - } - } - if (i->__promptme == 0) { - the_command[0] = '\n'; - the_command[1] = '\0'; - } - i->p = console_buffer; - } -#endif -} - -/* This is the magic location that prints prompts - * and gets data back from the user */ -static int file_get(struct in_str *i) -{ - int ch; - - ch = 0; - /* If there is data waiting, eat it up */ - if (i->p && *i->p) { - ch = *i->p++; - } else { - /* need to double check i->file because we might be doing something - * more complicated by now, like sourcing or substituting. */ -#ifndef __U_BOOT__ - if (i->__promptme && interactive && i->file == stdin) { - while(! i->p || (interactive && strlen(i->p)==0) ) { -#else - while(! i->p || strlen(i->p)==0 ) { -#endif - get_user_input(i); - } - i->promptmode=2; -#ifndef __U_BOOT__ - i->__promptme = 0; -#endif - if (i->p && *i->p) { - ch = *i->p++; - } -#ifndef __U_BOOT__ - } else { - ch = fgetc(i->file); - } - -#endif - debug_printf("b_getch: got a %d\n", ch); - } -#ifndef __U_BOOT__ - if (ch == '\n') i->__promptme=1; -#endif - return ch; -} - -/* All the callers guarantee this routine will never be - * used right after a newline, so prompting is not needed. - */ -static int file_peek(struct in_str *i) -{ -#ifndef __U_BOOT__ - if (i->p && *i->p) { -#endif - return *i->p; -#ifndef __U_BOOT__ - } else { - i->peek_buf[0] = fgetc(i->file); - i->peek_buf[1] = '\0'; - i->p = i->peek_buf; - debug_printf("b_peek: got a %d\n", *i->p); - return *i->p; - } -#endif -} - -#ifndef __U_BOOT__ -static void setup_file_in_str(struct in_str *i, FILE *f) -#else -static void setup_file_in_str(struct in_str *i) -#endif -{ - i->peek = file_peek; - i->get = file_get; - i->__promptme=1; - i->promptmode=1; -#ifndef __U_BOOT__ - i->file = f; -#endif - i->p = NULL; -} - -static void setup_string_in_str(struct in_str *i, const char *s) -{ - i->peek = static_peek; - i->get = static_get; - i->__promptme=1; - i->promptmode=1; - i->p = s; -} - -#ifndef __U_BOOT__ -static void mark_open(int fd) -{ - struct close_me *new = xmalloc(sizeof(struct close_me)); - new->fd = fd; - new->next = close_me_head; - close_me_head = new; -} - -static void mark_closed(int fd) -{ - struct close_me *tmp; - if (close_me_head == NULL || close_me_head->fd != fd) - error_msg_and_die("corrupt close_me"); - tmp = close_me_head; - close_me_head = close_me_head->next; - free(tmp); -} - -static void close_all(void) -{ - struct close_me *c; - for (c=close_me_head; c; c=c->next) { - close(c->fd); - } - close_me_head = NULL; -} - -/* squirrel != NULL means we squirrel away copies of stdin, stdout, - * and stderr if they are redirected. */ -static int setup_redirects(struct child_prog *prog, int squirrel[]) -{ - int openfd, mode; - struct redir_struct *redir; - - for (redir=prog->redirects; redir; redir=redir->next) { - if (redir->dup == -1 && redir->word.gl_pathv == NULL) { - /* something went wrong in the parse. Pretend it didn't happen */ - continue; - } - if (redir->dup == -1) { - mode=redir_table[redir->type].mode; - openfd = open(redir->word.gl_pathv[0], mode, 0666); - if (openfd < 0) { - /* this could get lost if stderr has been redirected, but - bash and ash both lose it as well (though zsh doesn't!) */ - perror_msg("error opening %s", redir->word.gl_pathv[0]); - return 1; - } - } else { - openfd = redir->dup; - } - - if (openfd != redir->fd) { - if (squirrel && redir->fd < 3) { - squirrel[redir->fd] = dup(redir->fd); - } - if (openfd == -3) { - close(openfd); - } else { - dup2(openfd, redir->fd); - if (redir->dup == -1) - close (openfd); - } - } - } - return 0; -} - -static void restore_redirects(int squirrel[]) -{ - int i, fd; - for (i=0; i<3; i++) { - fd = squirrel[i]; - if (fd != -1) { - /* No error checking. I sure wouldn't know what - * to do with an error if I found one! */ - dup2(fd, i); - close(fd); - } - } -} - -/* never returns */ -/* XXX no exit() here. If you don't exec, use _exit instead. - * The at_exit handlers apparently confuse the calling process, - * in particular stdin handling. Not sure why? */ -static void pseudo_exec(struct child_prog *child) -{ - int i, rcode; - char *p; - struct built_in_command *x; - if (child->argv) { - for (i=0; is_assignment(child->argv[i]); i++) { - debug_printf("pid %d environment modification: %s\n",getpid(),child->argv[i]); - p = insert_var_value(child->argv[i]); - putenv(strdup(p)); - if (p != child->argv[i]) free(p); - } - child->argv+=i; /* XXX this hack isn't so horrible, since we are about - to exit, and therefore don't need to keep data - structures consistent for free() use. */ - /* If a variable is assigned in a forest, and nobody listens, - * was it ever really set? - */ - if (child->argv[0] == NULL) { - _exit(EXIT_SUCCESS); - } - - /* - * Check if the command matches any of the builtins. - * Depending on context, this might be redundant. But it's - * easier to waste a few CPU cycles than it is to figure out - * if this is one of those cases. - */ - for (x = bltins; x->cmd; x++) { - if (strcmp(child->argv[0], x->cmd) == 0 ) { - debug_printf("builtin exec %s\n", child->argv[0]); - rcode = x->function(child); - fflush(stdout); - _exit(rcode); - } - } - - /* Check if the command matches any busybox internal commands - * ("applets") here. - * FIXME: This feature is not 100% safe, since - * BusyBox is not fully reentrant, so we have no guarantee the things - * from the .bss are still zeroed, or that things from .data are still - * at their defaults. We could exec ourself from /proc/self/exe, but I - * really dislike relying on /proc for things. We could exec ourself - * from global_argv[0], but if we are in a chroot, we may not be able - * to find ourself... */ -#ifdef CONFIG_FEATURE_SH_STANDALONE_SHELL - { - int argc_l; - char** argv_l=child->argv; - char *name = child->argv[0]; - -#ifdef CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN - /* Following discussions from November 2000 on the busybox mailing - * list, the default configuration, (without - * get_last_path_component()) lets the user force use of an - * external command by specifying the full (with slashes) filename. - * If you enable CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN then applets - * _aways_ override external commands, so if you want to run - * /bin/cat, it will use BusyBox cat even if /bin/cat exists on the - * filesystem and is _not_ busybox. Some systems may want this, - * most do not. */ - name = get_last_path_component(name); -#endif - /* Count argc for use in a second... */ - for(argc_l=0;*argv_l!=NULL; argv_l++, argc_l++); - optind = 1; - debug_printf("running applet %s\n", name); - run_applet_by_name(name, argc_l, child->argv); - } -#endif - debug_printf("exec of %s\n",child->argv[0]); - execvp(child->argv[0],child->argv); - perror_msg("couldn't exec: %s",child->argv[0]); - _exit(1); - } else if (child->group) { - debug_printf("runtime nesting to group\n"); - interactive=0; /* crucial!!!! */ - rcode = run_list_real(child->group); - /* OK to leak memory by not calling free_pipe_list, - * since this process is about to exit */ - _exit(rcode); - } else { - /* Can happen. See what bash does with ">foo" by itself. */ - debug_printf("trying to pseudo_exec null command\n"); - _exit(EXIT_SUCCESS); - } -} - -static void insert_bg_job(struct pipe *pi) -{ - struct pipe *thejob; - - /* Linear search for the ID of the job to use */ - pi->jobid = 1; - for (thejob = job_list; thejob; thejob = thejob->next) - if (thejob->jobid >= pi->jobid) - pi->jobid = thejob->jobid + 1; - - /* add thejob to the list of running jobs */ - if (!job_list) { - thejob = job_list = xmalloc(sizeof(*thejob)); - } else { - for (thejob = job_list; thejob->next; thejob = thejob->next) /* nothing */; - thejob->next = xmalloc(sizeof(*thejob)); - thejob = thejob->next; - } - - /* physically copy the struct job */ - memcpy(thejob, pi, sizeof(struct pipe)); - thejob->next = NULL; - thejob->running_progs = thejob->num_progs; - thejob->stopped_progs = 0; - thejob->text = xmalloc(BUFSIZ); /* cmdedit buffer size */ - - /*if (pi->progs[0] && pi->progs[0].argv && pi->progs[0].argv[0]) */ - { - char *bar=thejob->text; - char **foo=pi->progs[0].argv; - while(foo && *foo) { - bar += sprintf(bar, "%s ", *foo++); - } - } - - /* we don't wait for background thejobs to return -- append it - to the list of backgrounded thejobs and leave it alone */ - printf("[%d] %d\n", thejob->jobid, thejob->progs[0].pid); - last_bg_pid = thejob->progs[0].pid; - last_jobid = thejob->jobid; -} - -/* remove a backgrounded job */ -static void remove_bg_job(struct pipe *pi) -{ - struct pipe *prev_pipe; - - if (pi == job_list) { - job_list = pi->next; - } else { - prev_pipe = job_list; - while (prev_pipe->next != pi) - prev_pipe = prev_pipe->next; - prev_pipe->next = pi->next; - } - if (job_list) - last_jobid = job_list->jobid; - else - last_jobid = 0; - - pi->stopped_progs = 0; - free_pipe(pi, 0); - free(pi); -} - -/* Checks to see if any processes have exited -- if they - have, figure out why and see if a job has completed */ -static int checkjobs(struct pipe* fg_pipe) -{ - int attributes; - int status; - int prognum = 0; - struct pipe *pi; - pid_t childpid; - - attributes = WUNTRACED; - if (fg_pipe==NULL) { - attributes |= WNOHANG; - } - - while ((childpid = waitpid(-1, &status, attributes)) > 0) { - if (fg_pipe) { - int i, rcode = 0; - for (i=0; i < fg_pipe->num_progs; i++) { - if (fg_pipe->progs[i].pid == childpid) { - if (i==fg_pipe->num_progs-1) - rcode=WEXITSTATUS(status); - (fg_pipe->num_progs)--; - return(rcode); - } - } - } - - for (pi = job_list; pi; pi = pi->next) { - prognum = 0; - while (prognum < pi->num_progs && pi->progs[prognum].pid != childpid) { - prognum++; - } - if (prognum < pi->num_progs) - break; - } - - if(pi==NULL) { - debug_printf("checkjobs: pid %d was not in our list!\n", childpid); - continue; - } - - if (WIFEXITED(status) || WIFSIGNALED(status)) { - /* child exited */ - pi->running_progs--; - pi->progs[prognum].pid = 0; - - if (!pi->running_progs) { - printf(JOB_STATUS_FORMAT, pi->jobid, "Done", pi->text); - remove_bg_job(pi); - } - } else { - /* child stopped */ - pi->stopped_progs++; - pi->progs[prognum].is_stopped = 1; - -#if 0 - /* Printing this stuff is a pain, since it tends to - * overwrite the prompt an inconveinient moments. So - * don't do that. */ - if (pi->stopped_progs == pi->num_progs) { - printf("\n"JOB_STATUS_FORMAT, pi->jobid, "Stopped", pi->text); - } -#endif - } - } - - if (childpid == -1 && errno != ECHILD) - perror_msg("waitpid"); - - /* move the shell to the foreground */ - /*if (interactive && tcsetpgrp(shell_terminal, getpgid(0))) */ - /* perror_msg("tcsetpgrp-2"); */ - return -1; -} - -/* Figure out our controlling tty, checking in order stderr, - * stdin, and stdout. If check_pgrp is set, also check that - * we belong to the foreground process group associated with - * that tty. The value of shell_terminal is needed in order to call - * tcsetpgrp(shell_terminal, ...); */ -void controlling_tty(int check_pgrp) -{ - pid_t curpgrp; - - if ((curpgrp = tcgetpgrp(shell_terminal = 2)) < 0 - && (curpgrp = tcgetpgrp(shell_terminal = 0)) < 0 - && (curpgrp = tcgetpgrp(shell_terminal = 1)) < 0) - goto shell_terminal_error; - - if (check_pgrp && curpgrp != getpgid(0)) - goto shell_terminal_error; - - return; - -shell_terminal_error: - shell_terminal = -1; - return; -} -#endif - -/* run_pipe_real() starts all the jobs, but doesn't wait for anything - * to finish. See checkjobs(). - * - * return code is normally -1, when the caller has to wait for children - * to finish to determine the exit status of the pipe. If the pipe - * is a simple builtin command, however, the action is done by the - * time run_pipe_real returns, and the exit code is provided as the - * return value. - * - * The input of the pipe is always stdin, the output is always - * stdout. The outpipe[] mechanism in BusyBox-0.48 lash is bogus, - * because it tries to avoid running the command substitution in - * subshell, when that is in fact necessary. The subshell process - * now has its stdout directed to the input of the appropriate pipe, - * so this routine is noticeably simpler. - */ -static int run_pipe_real(struct pipe *pi) -{ - int i; -#ifndef __U_BOOT__ - int nextin, nextout; - int pipefds[2]; /* pipefds[0] is for reading */ - struct child_prog *child; - struct built_in_command *x; - char *p; -# if __GNUC__ - /* Avoid longjmp clobbering */ - (void) &i; - (void) &nextin; - (void) &nextout; - (void) &child; -# endif -#else - int nextin; - int flag = do_repeat ? CMD_FLAG_REPEAT : 0; - struct child_prog *child; - char *p; -# if __GNUC__ - /* Avoid longjmp clobbering */ - (void) &i; - (void) &nextin; - (void) &child; -# endif -#endif /* __U_BOOT__ */ - - nextin = 0; -#ifndef __U_BOOT__ - pi->pgrp = -1; -#endif - - /* Check if this is a simple builtin (not part of a pipe). - * Builtins within pipes have to fork anyway, and are handled in - * pseudo_exec. "echo foo | read bar" doesn't work on bash, either. - */ - if (pi->num_progs == 1) child = & (pi->progs[0]); -#ifndef __U_BOOT__ - if (pi->num_progs == 1 && child->group && child->subshell == 0) { - int squirrel[] = {-1, -1, -1}; - int rcode; - debug_printf("non-subshell grouping\n"); - setup_redirects(child, squirrel); - /* XXX could we merge code with following builtin case, - * by creating a pseudo builtin that calls run_list_real? */ - rcode = run_list_real(child->group); - restore_redirects(squirrel); -#else - if (pi->num_progs == 1 && child->group) { - int rcode; - debug_printf("non-subshell grouping\n"); - rcode = run_list_real(child->group); -#endif - return rcode; - } else if (pi->num_progs == 1 && pi->progs[0].argv != NULL) { - for (i=0; is_assignment(child->argv[i]); i++) { /* nothing */ } - if (i!=0 && child->argv[i]==NULL) { - /* assignments, but no command: set the local environment */ - for (i=0; child->argv[i]!=NULL; i++) { - - /* Ok, this case is tricky. We have to decide if this is a - * local variable, or an already exported variable. If it is - * already exported, we have to export the new value. If it is - * not exported, we need only set this as a local variable. - * This junk is all to decide whether or not to export this - * variable. */ - int export_me=0; - char *name, *value; - name = xstrdup(child->argv[i]); - debug_printf("Local environment set: %s\n", name); - value = strchr(name, '='); - if (value) - *value=0; -#ifndef __U_BOOT__ - if ( get_local_var(name)) { - export_me=1; - } -#endif - free(name); - p = insert_var_value(child->argv[i]); - set_local_var(p, export_me); - if (p != child->argv[i]) free(p); - } - return EXIT_SUCCESS; /* don't worry about errors in set_local_var() yet */ - } - for (i = 0; is_assignment(child->argv[i]); i++) { - p = insert_var_value(child->argv[i]); -#ifndef __U_BOOT__ - putenv(strdup(p)); -#else - set_local_var(p, 0); -#endif - if (p != child->argv[i]) { - child->sp--; - free(p); - } - } - if (child->sp) { - char * str = NULL; - - str = make_string((child->argv + i)); - parse_string_outer(str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING); - free(str); - return last_return_code; - } -#ifndef __U_BOOT__ - for (x = bltins; x->cmd; x++) { - if (strcmp(child->argv[i], x->cmd) == 0 ) { - int squirrel[] = {-1, -1, -1}; - int rcode; - if (x->function == builtin_exec && child->argv[i+1]==NULL) { - debug_printf("magic exec\n"); - setup_redirects(child,NULL); - return EXIT_SUCCESS; - } - debug_printf("builtin inline %s\n", child->argv[0]); - /* XXX setup_redirects acts on file descriptors, not FILEs. - * This is perfect for work that comes after exec(). - * Is it really safe for inline use? Experimentally, - * things seem to work with glibc. */ - setup_redirects(child, squirrel); - - child->argv += i; /* XXX horrible hack */ - rcode = x->function(child); - /* XXX restore hack so free() can work right */ - child->argv -= i; - restore_redirects(squirrel); - } - return rcode; - } -#else - /* check ";", because ,example , argv consist from - * "help;flinfo" must not execute - */ - if (strchr(child->argv[i], ';')) { - printf("Unknown command '%s' - try 'help' or use " - "'run' command\n", child->argv[i]); - return -1; - } - /* Process the command */ - return cmd_process(flag, child->argc, child->argv, - &flag_repeat, NULL); -#endif - } -#ifndef __U_BOOT__ - - for (i = 0; i < pi->num_progs; i++) { - child = & (pi->progs[i]); - - /* pipes are inserted between pairs of commands */ - if ((i + 1) < pi->num_progs) { - if (pipe(pipefds)<0) perror_msg_and_die("pipe"); - nextout = pipefds[1]; - } else { - nextout=1; - pipefds[0] = -1; - } - - /* XXX test for failed fork()? */ - if (!(child->pid = fork())) { - /* Set the handling for job control signals back to the default. */ - signal(SIGINT, SIG_DFL); - signal(SIGQUIT, SIG_DFL); - signal(SIGTERM, SIG_DFL); - signal(SIGTSTP, SIG_DFL); - signal(SIGTTIN, SIG_DFL); - signal(SIGTTOU, SIG_DFL); - signal(SIGCHLD, SIG_DFL); - - close_all(); - - if (nextin != 0) { - dup2(nextin, 0); - close(nextin); - } - if (nextout != 1) { - dup2(nextout, 1); - close(nextout); - } - if (pipefds[0]!=-1) { - close(pipefds[0]); /* opposite end of our output pipe */ - } - - /* Like bash, explicit redirects override pipes, - * and the pipe fd is available for dup'ing. */ - setup_redirects(child,NULL); - - if (interactive && pi->followup!=PIPE_BG) { - /* If we (the child) win the race, put ourselves in the process - * group whose leader is the first process in this pipe. */ - if (pi->pgrp < 0) { - pi->pgrp = getpid(); - } - if (setpgid(0, pi->pgrp) == 0) { - tcsetpgrp(2, pi->pgrp); - } - } - - pseudo_exec(child); - } - - - /* put our child in the process group whose leader is the - first process in this pipe */ - if (pi->pgrp < 0) { - pi->pgrp = child->pid; - } - /* Don't check for errors. The child may be dead already, - * in which case setpgid returns error code EACCES. */ - setpgid(child->pid, pi->pgrp); - - if (nextin != 0) - close(nextin); - if (nextout != 1) - close(nextout); - - /* If there isn't another process, nextin is garbage - but it doesn't matter */ - nextin = pipefds[0]; - } -#endif - return -1; -} - -static int run_list_real(struct pipe *pi) -{ - char *save_name = NULL; - char **list = NULL; - char **save_list = NULL; - struct pipe *rpipe; - int flag_rep = 0; -#ifndef __U_BOOT__ - int save_num_progs; -#endif - int rcode=0, flag_skip=1; - int flag_restore = 0; - int if_code=0, next_if_code=0; /* need double-buffer to handle elif */ - reserved_style rmode, skip_more_in_this_rmode=RES_XXXX; - /* check syntax for "for" */ - for (rpipe = pi; rpipe; rpipe = rpipe->next) { - if ((rpipe->r_mode == RES_IN || - rpipe->r_mode == RES_FOR) && - (rpipe->next == NULL)) { - syntax(); -#ifdef __U_BOOT__ - flag_repeat = 0; -#endif - return 1; - } - if ((rpipe->r_mode == RES_IN && - (rpipe->next->r_mode == RES_IN && - rpipe->next->progs->argv != NULL))|| - (rpipe->r_mode == RES_FOR && - rpipe->next->r_mode != RES_IN)) { - syntax(); -#ifdef __U_BOOT__ - flag_repeat = 0; -#endif - return 1; - } - } - for (; pi; pi = (flag_restore != 0) ? rpipe : pi->next) { - if (pi->r_mode == RES_WHILE || pi->r_mode == RES_UNTIL || - pi->r_mode == RES_FOR) { -#ifdef __U_BOOT__ - /* check Ctrl-C */ - ctrlc(); - if ((had_ctrlc())) { - return 1; - } -#endif - flag_restore = 0; - if (!rpipe) { - flag_rep = 0; - rpipe = pi; - } - } - rmode = pi->r_mode; - debug_printf("rmode=%d if_code=%d next_if_code=%d skip_more=%d\n", rmode, if_code, next_if_code, skip_more_in_this_rmode); - if (rmode == skip_more_in_this_rmode && flag_skip) { - if (pi->followup == PIPE_SEQ) flag_skip=0; - continue; - } - flag_skip = 1; - skip_more_in_this_rmode = RES_XXXX; - if (rmode == RES_THEN || rmode == RES_ELSE) if_code = next_if_code; - if (rmode == RES_THEN && if_code) continue; - if (rmode == RES_ELSE && !if_code) continue; - if (rmode == RES_ELIF && !if_code) break; - if (rmode == RES_FOR && pi->num_progs) { - if (!list) { - /* if no variable values after "in" we skip "for" */ - if (!pi->next->progs->argv) continue; - /* create list of variable values */ - list = make_list_in(pi->next->progs->argv, - pi->progs->argv[0]); - save_list = list; - save_name = pi->progs->argv[0]; - pi->progs->argv[0] = NULL; - flag_rep = 1; - } - if (!(*list)) { - free(pi->progs->argv[0]); - free(save_list); - list = NULL; - flag_rep = 0; - pi->progs->argv[0] = save_name; -#ifndef __U_BOOT__ - pi->progs->glob_result.gl_pathv[0] = - pi->progs->argv[0]; -#endif - continue; - } else { - /* insert new value from list for variable */ - if (pi->progs->argv[0]) - free(pi->progs->argv[0]); - pi->progs->argv[0] = *list++; -#ifndef __U_BOOT__ - pi->progs->glob_result.gl_pathv[0] = - pi->progs->argv[0]; -#endif - } - } - if (rmode == RES_IN) continue; - if (rmode == RES_DO) { - if (!flag_rep) continue; - } - if ((rmode == RES_DONE)) { - if (flag_rep) { - flag_restore = 1; - } else { - rpipe = NULL; - } - } - if (pi->num_progs == 0) continue; -#ifndef __U_BOOT__ - save_num_progs = pi->num_progs; /* save number of programs */ -#endif - rcode = run_pipe_real(pi); - debug_printf("run_pipe_real returned %d\n",rcode); -#ifndef __U_BOOT__ - if (rcode!=-1) { - /* We only ran a builtin: rcode was set by the return value - * of run_pipe_real(), and we don't need to wait for anything. */ - } else if (pi->followup==PIPE_BG) { - /* XXX check bash's behavior with nontrivial pipes */ - /* XXX compute jobid */ - /* XXX what does bash do with attempts to background builtins? */ - insert_bg_job(pi); - rcode = EXIT_SUCCESS; - } else { - if (interactive) { - /* move the new process group into the foreground */ - if (tcsetpgrp(shell_terminal, pi->pgrp) && errno != ENOTTY) - perror_msg("tcsetpgrp-3"); - rcode = checkjobs(pi); - /* move the shell to the foreground */ - if (tcsetpgrp(shell_terminal, getpgid(0)) && errno != ENOTTY) - perror_msg("tcsetpgrp-4"); - } else { - rcode = checkjobs(pi); - } - debug_printf("checkjobs returned %d\n",rcode); - } - last_return_code=rcode; -#else - if (rcode < -1) { - last_return_code = -rcode - 2; - return -2; /* exit */ - } - last_return_code=(rcode == 0) ? 0 : 1; -#endif -#ifndef __U_BOOT__ - pi->num_progs = save_num_progs; /* restore number of programs */ -#endif - if ( rmode == RES_IF || rmode == RES_ELIF ) - next_if_code=rcode; /* can be overwritten a number of times */ - if (rmode == RES_WHILE) - flag_rep = !last_return_code; - if (rmode == RES_UNTIL) - flag_rep = last_return_code; - if ( (rcode==EXIT_SUCCESS && pi->followup==PIPE_OR) || - (rcode!=EXIT_SUCCESS && pi->followup==PIPE_AND) ) - skip_more_in_this_rmode=rmode; -#ifndef __U_BOOT__ - checkjobs(NULL); -#endif - } - return rcode; -} - -/* broken, of course, but OK for testing */ -static char *indenter(int i) -{ - static char blanks[]=" "; - return &blanks[sizeof(blanks)-i-1]; -} - -/* return code is the exit status of the pipe */ -static int free_pipe(struct pipe *pi, int indent) -{ - char **p; - struct child_prog *child; -#ifndef __U_BOOT__ - struct redir_struct *r, *rnext; -#endif - int a, i, ret_code=0; - char *ind = indenter(indent); - -#ifndef __U_BOOT__ - if (pi->stopped_progs > 0) - return ret_code; - final_printf("%s run pipe: (pid %d)\n",ind,getpid()); -#endif - for (i=0; inum_progs; i++) { - child = &pi->progs[i]; - final_printf("%s command %d:\n",ind,i); - if (child->argv) { - for (a=0,p=child->argv; *p; a++,p++) { - final_printf("%s argv[%d] = %s\n",ind,a,*p); - } -#ifndef __U_BOOT__ - globfree(&child->glob_result); -#else - for (a = 0; a < child->argc; a++) { - free(child->argv[a]); - } - free(child->argv); - child->argc = 0; -#endif - child->argv=NULL; - } else if (child->group) { -#ifndef __U_BOOT__ - final_printf("%s begin group (subshell:%d)\n",ind, child->subshell); -#endif - ret_code = free_pipe_list(child->group,indent+3); - final_printf("%s end group\n",ind); - } else { - final_printf("%s (nil)\n",ind); - } -#ifndef __U_BOOT__ - for (r=child->redirects; r; r=rnext) { - final_printf("%s redirect %d%s", ind, r->fd, redir_table[r->type].descrip); - if (r->dup == -1) { - /* guard against the case >$FOO, where foo is unset or blank */ - if (r->word.gl_pathv) { - final_printf(" %s\n", *r->word.gl_pathv); - globfree(&r->word); - } - } else { - final_printf("&%d\n", r->dup); - } - rnext=r->next; - free(r); - } - child->redirects=NULL; -#endif - } - free(pi->progs); /* children are an array, they get freed all at once */ - pi->progs=NULL; - return ret_code; -} - -static int free_pipe_list(struct pipe *head, int indent) -{ - int rcode=0; /* if list has no members */ - struct pipe *pi, *next; - char *ind = indenter(indent); - for (pi=head; pi; pi=next) { - final_printf("%s pipe reserved mode %d\n", ind, pi->r_mode); - rcode = free_pipe(pi, indent); - final_printf("%s pipe followup code %d\n", ind, pi->followup); - next=pi->next; - pi->next=NULL; - free(pi); - } - return rcode; -} - -/* Select which version we will use */ -static int run_list(struct pipe *pi) -{ - int rcode=0; -#ifndef __U_BOOT__ - if (fake_mode==0) { -#endif - rcode = run_list_real(pi); -#ifndef __U_BOOT__ - } -#endif - /* free_pipe_list has the side effect of clearing memory - * In the long run that function can be merged with run_list_real, - * but doing that now would hobble the debugging effort. */ - free_pipe_list(pi,0); - return rcode; -} - -/* The API for glob is arguably broken. This routine pushes a non-matching - * string into the output structure, removing non-backslashed backslashes. - * If someone can prove me wrong, by performing this function within the - * original glob(3) api, feel free to rewrite this routine into oblivion. - * Return code (0 vs. GLOB_NOSPACE) matches glob(3). - * XXX broken if the last character is '\\', check that before calling. - */ -#ifndef __U_BOOT__ -static int globhack(const char *src, int flags, glob_t *pglob) -{ - int cnt=0, pathc; - const char *s; - char *dest; - for (cnt=1, s=src; s && *s; s++) { - if (*s == '\\') s++; - cnt++; - } - dest = malloc(cnt); - if (!dest) return GLOB_NOSPACE; - if (!(flags & GLOB_APPEND)) { - pglob->gl_pathv=NULL; - pglob->gl_pathc=0; - pglob->gl_offs=0; - pglob->gl_offs=0; - } - pathc = ++pglob->gl_pathc; - pglob->gl_pathv = realloc(pglob->gl_pathv, (pathc+1)*sizeof(*pglob->gl_pathv)); - if (pglob->gl_pathv == NULL) return GLOB_NOSPACE; - pglob->gl_pathv[pathc-1]=dest; - pglob->gl_pathv[pathc]=NULL; - for (s=src; s && *s; s++, dest++) { - if (*s == '\\') s++; - *dest = *s; - } - *dest='\0'; - return 0; -} - -/* XXX broken if the last character is '\\', check that before calling */ -static int glob_needed(const char *s) -{ - for (; *s; s++) { - if (*s == '\\') s++; - if (strchr("*[?",*s)) return 1; - } - return 0; -} - -#if 0 -static void globprint(glob_t *pglob) -{ - int i; - debug_printf("glob_t at %p:\n", pglob); - debug_printf(" gl_pathc=%d gl_pathv=%p gl_offs=%d gl_flags=%d\n", - pglob->gl_pathc, pglob->gl_pathv, pglob->gl_offs, pglob->gl_flags); - for (i=0; igl_pathc; i++) - debug_printf("pglob->gl_pathv[%d] = %p = %s\n", i, - pglob->gl_pathv[i], pglob->gl_pathv[i]); -} -#endif - -static int xglob(o_string *dest, int flags, glob_t *pglob) -{ - int gr; - - /* short-circuit for null word */ - /* we can code this better when the debug_printf's are gone */ - if (dest->length == 0) { - if (dest->nonnull) { - /* bash man page calls this an "explicit" null */ - gr = globhack(dest->data, flags, pglob); - debug_printf("globhack returned %d\n",gr); - } else { - return 0; - } - } else if (glob_needed(dest->data)) { - gr = glob(dest->data, flags, NULL, pglob); - debug_printf("glob returned %d\n",gr); - if (gr == GLOB_NOMATCH) { - /* quote removal, or more accurately, backslash removal */ - gr = globhack(dest->data, flags, pglob); - debug_printf("globhack returned %d\n",gr); - } - } else { - gr = globhack(dest->data, flags, pglob); - debug_printf("globhack returned %d\n",gr); - } - if (gr == GLOB_NOSPACE) - error_msg_and_die("out of memory during glob"); - if (gr != 0) { /* GLOB_ABORTED ? */ - error_msg("glob(3) error %d",gr); - } - /* globprint(glob_target); */ - return gr; -} -#endif - -#ifdef __U_BOOT__ -static char *get_dollar_var(char ch); -#endif - -/* This is used to get/check local shell variables */ -char *get_local_var(const char *s) -{ - struct variables *cur; - - if (!s) - return NULL; - -#ifdef __U_BOOT__ - if (*s == '$') - return get_dollar_var(s[1]); -#endif - - for (cur = top_vars; cur; cur=cur->next) - if(strcmp(cur->name, s)==0) - return cur->value; - return NULL; -} - -/* This is used to set local shell variables - flg_export==0 if only local (not exporting) variable - flg_export==1 if "new" exporting environ - flg_export>1 if current startup environ (not call putenv()) */ -int set_local_var(const char *s, int flg_export) -{ - char *name, *value; - int result=0; - struct variables *cur; - -#ifdef __U_BOOT__ - /* might be possible! */ - if (!isalpha(*s)) - return -1; -#endif - - name=strdup(s); - -#ifdef __U_BOOT__ - if (getenv(name) != NULL) { - printf ("ERROR: " - "There is a global environment variable with the same name.\n"); - free(name); - return -1; - } -#endif - /* Assume when we enter this function that we are already in - * NAME=VALUE format. So the first order of business is to - * split 's' on the '=' into 'name' and 'value' */ - value = strchr(name, '='); - if (value == NULL && ++value == NULL) { - free(name); - return -1; - } - *value++ = 0; - - for(cur = top_vars; cur; cur = cur->next) { - if(strcmp(cur->name, name)==0) - break; - } - - if(cur) { - if(strcmp(cur->value, value)==0) { - if(flg_export>0 && cur->flg_export==0) - cur->flg_export=flg_export; - else - result++; - } else { - if(cur->flg_read_only) { - error_msg("%s: readonly variable", name); - result = -1; - } else { - if(flg_export>0 || cur->flg_export>1) - cur->flg_export=1; - free(cur->value); - - cur->value = strdup(value); - } - } - } else { - cur = malloc(sizeof(struct variables)); - if(!cur) { - result = -1; - } else { - cur->name = strdup(name); - if (cur->name == NULL) { - free(cur); - result = -1; - } else { - struct variables *bottom = top_vars; - cur->value = strdup(value); - cur->next = NULL; - cur->flg_export = flg_export; - cur->flg_read_only = 0; - while(bottom->next) bottom=bottom->next; - bottom->next = cur; - } - } - } - -#ifndef __U_BOOT__ - if(result==0 && cur->flg_export==1) { - *(value-1) = '='; - result = putenv(name); - } else { -#endif - free(name); -#ifndef __U_BOOT__ - if(result>0) /* equivalent to previous set */ - result = 0; - } -#endif - return result; -} - -void unset_local_var(const char *name) -{ - struct variables *cur; - - if (name) { - for (cur = top_vars; cur; cur=cur->next) { - if(strcmp(cur->name, name)==0) - break; - } - if (cur != NULL) { - struct variables *next = top_vars; - if(cur->flg_read_only) { - error_msg("%s: readonly variable", name); - return; - } else { -#ifndef __U_BOOT__ - if(cur->flg_export) - unsetenv(cur->name); -#endif - free(cur->name); - free(cur->value); - while (next->next != cur) - next = next->next; - next->next = cur->next; - } - free(cur); - } - } -} - -static int is_assignment(const char *s) -{ - if (s == NULL) - return 0; - - if (!isalpha(*s)) return 0; - ++s; - while(isalnum(*s) || *s=='_') ++s; - return *s=='='; -} - -#ifndef __U_BOOT__ -/* the src parameter allows us to peek forward to a possible &n syntax - * for file descriptor duplication, e.g., "2>&1". - * Return code is 0 normally, 1 if a syntax error is detected in src. - * Resource errors (in xmalloc) cause the process to exit */ -static int setup_redirect(struct p_context *ctx, int fd, redir_type style, - struct in_str *input) -{ - struct child_prog *child=ctx->child; - struct redir_struct *redir = child->redirects; - struct redir_struct *last_redir=NULL; - - /* Create a new redir_struct and drop it onto the end of the linked list */ - while(redir) { - last_redir=redir; - redir=redir->next; - } - redir = xmalloc(sizeof(struct redir_struct)); - redir->next=NULL; - redir->word.gl_pathv=NULL; - if (last_redir) { - last_redir->next=redir; - } else { - child->redirects=redir; - } - - redir->type=style; - redir->fd= (fd==-1) ? redir_table[style].default_fd : fd ; - - debug_printf("Redirect type %d%s\n", redir->fd, redir_table[style].descrip); - - /* Check for a '2>&1' type redirect */ - redir->dup = redirect_dup_num(input); - if (redir->dup == -2) return 1; /* syntax error */ - if (redir->dup != -1) { - /* Erik had a check here that the file descriptor in question - * is legit; I postpone that to "run time" - * A "-" representation of "close me" shows up as a -3 here */ - debug_printf("Duplicating redirect '%d>&%d'\n", redir->fd, redir->dup); - } else { - /* We do _not_ try to open the file that src points to, - * since we need to return and let src be expanded first. - * Set ctx->pending_redirect, so we know what to do at the - * end of the next parsed word. - */ - ctx->pending_redirect = redir; - } - return 0; -} -#endif - -static struct pipe *new_pipe(void) -{ - struct pipe *pi; - pi = xmalloc(sizeof(struct pipe)); - pi->num_progs = 0; - pi->progs = NULL; - pi->next = NULL; - pi->followup = 0; /* invalid */ - pi->r_mode = RES_NONE; - return pi; -} - -static void initialize_context(struct p_context *ctx) -{ - ctx->pipe=NULL; -#ifndef __U_BOOT__ - ctx->pending_redirect=NULL; -#endif - ctx->child=NULL; - ctx->list_head=new_pipe(); - ctx->pipe=ctx->list_head; - ctx->w=RES_NONE; - ctx->stack=NULL; -#ifdef __U_BOOT__ - ctx->old_flag=0; -#endif - done_command(ctx); /* creates the memory for working child */ -} - -/* normal return is 0 - * if a reserved word is found, and processed, return 1 - * should handle if, then, elif, else, fi, for, while, until, do, done. - * case, function, and select are obnoxious, save those for later. - */ -struct reserved_combo { - char *literal; - int code; - long flag; -}; -/* Mostly a list of accepted follow-up reserved words. - * FLAG_END means we are done with the sequence, and are ready - * to turn the compound list into a command. - * FLAG_START means the word must start a new compound list. - */ -static struct reserved_combo reserved_list[] = { - { "if", RES_IF, FLAG_THEN | FLAG_START }, - { "then", RES_THEN, FLAG_ELIF | FLAG_ELSE | FLAG_FI }, - { "elif", RES_ELIF, FLAG_THEN }, - { "else", RES_ELSE, FLAG_FI }, - { "fi", RES_FI, FLAG_END }, - { "for", RES_FOR, FLAG_IN | FLAG_START }, - { "while", RES_WHILE, FLAG_DO | FLAG_START }, - { "until", RES_UNTIL, FLAG_DO | FLAG_START }, - { "in", RES_IN, FLAG_DO }, - { "do", RES_DO, FLAG_DONE }, - { "done", RES_DONE, FLAG_END } -}; -#define NRES (sizeof(reserved_list)/sizeof(struct reserved_combo)) - -static int reserved_word(o_string *dest, struct p_context *ctx) -{ - struct reserved_combo *r; - for (r=reserved_list; - rdata, r->literal) == 0) { - debug_printf("found reserved word %s, code %d\n",r->literal,r->code); - if (r->flag & FLAG_START) { - struct p_context *new = xmalloc(sizeof(struct p_context)); - debug_printf("push stack\n"); - if (ctx->w == RES_IN || ctx->w == RES_FOR) { - syntax(); - free(new); - ctx->w = RES_SNTX; - b_reset(dest); - return 1; - } - *new = *ctx; /* physical copy */ - initialize_context(ctx); - ctx->stack=new; - } else if ( ctx->w == RES_NONE || ! (ctx->old_flag & (1<code))) { - syntax(); - ctx->w = RES_SNTX; - b_reset(dest); - return 1; - } - ctx->w=r->code; - ctx->old_flag = r->flag; - if (ctx->old_flag & FLAG_END) { - struct p_context *old; - debug_printf("pop stack\n"); - done_pipe(ctx,PIPE_SEQ); - old = ctx->stack; - old->child->group = ctx->list_head; -#ifndef __U_BOOT__ - old->child->subshell = 0; -#endif - *ctx = *old; /* physical copy */ - free(old); - } - b_reset (dest); - return 1; - } - } - return 0; -} - -/* normal return is 0. - * Syntax or xglob errors return 1. */ -static int done_word(o_string *dest, struct p_context *ctx) -{ - struct child_prog *child=ctx->child; -#ifndef __U_BOOT__ - glob_t *glob_target; - int gr, flags = 0; -#else - char *str, *s; - int argc, cnt; -#endif - - debug_printf("done_word: %s %p\n", dest->data, child); - if (dest->length == 0 && !dest->nonnull) { - debug_printf(" true null, ignored\n"); - return 0; - } -#ifndef __U_BOOT__ - if (ctx->pending_redirect) { - glob_target = &ctx->pending_redirect->word; - } else { -#endif - if (child->group) { - syntax(); - return 1; /* syntax error, groups and arglists don't mix */ - } - if (!child->argv && (ctx->type & FLAG_PARSE_SEMICOLON)) { - debug_printf("checking %s for reserved-ness\n",dest->data); - if (reserved_word(dest,ctx)) return ctx->w==RES_SNTX; - } -#ifndef __U_BOOT__ - glob_target = &child->glob_result; - if (child->argv) flags |= GLOB_APPEND; -#else - for (cnt = 1, s = dest->data; s && *s; s++) { - if (*s == '\\') s++; - cnt++; - } - str = malloc(cnt); - if (!str) return 1; - if ( child->argv == NULL) { - child->argc=0; - } - argc = ++child->argc; - child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv)); - if (child->argv == NULL) return 1; - child->argv[argc-1]=str; - child->argv[argc]=NULL; - for (s = dest->data; s && *s; s++,str++) { - if (*s == '\\') s++; - *str = *s; - } - *str = '\0'; -#endif -#ifndef __U_BOOT__ - } - gr = xglob(dest, flags, glob_target); - if (gr != 0) return 1; -#endif - - b_reset(dest); -#ifndef __U_BOOT__ - if (ctx->pending_redirect) { - ctx->pending_redirect=NULL; - if (glob_target->gl_pathc != 1) { - error_msg("ambiguous redirect"); - return 1; - } - } else { - child->argv = glob_target->gl_pathv; - } -#endif - if (ctx->w == RES_FOR) { - done_word(dest,ctx); - done_pipe(ctx,PIPE_SEQ); - } - return 0; -} - -/* The only possible error here is out of memory, in which case - * xmalloc exits. */ -static int done_command(struct p_context *ctx) -{ - /* The child is really already in the pipe structure, so - * advance the pipe counter and make a new, null child. - * Only real trickiness here is that the uncommitted - * child structure, to which ctx->child points, is not - * counted in pi->num_progs. */ - struct pipe *pi=ctx->pipe; - struct child_prog *prog=ctx->child; - - if (prog && prog->group == NULL - && prog->argv == NULL -#ifndef __U_BOOT__ - && prog->redirects == NULL) { -#else - ) { -#endif - debug_printf("done_command: skipping null command\n"); - return 0; - } else if (prog) { - pi->num_progs++; - debug_printf("done_command: num_progs incremented to %d\n",pi->num_progs); - } else { - debug_printf("done_command: initializing\n"); - } - pi->progs = xrealloc(pi->progs, sizeof(*pi->progs) * (pi->num_progs+1)); - - prog = pi->progs + pi->num_progs; -#ifndef __U_BOOT__ - prog->redirects = NULL; -#endif - prog->argv = NULL; -#ifndef __U_BOOT__ - prog->is_stopped = 0; -#endif - prog->group = NULL; -#ifndef __U_BOOT__ - prog->glob_result.gl_pathv = NULL; - prog->family = pi; -#endif - prog->sp = 0; - ctx->child = prog; - prog->type = ctx->type; - - /* but ctx->pipe and ctx->list_head remain unchanged */ - return 0; -} - -static int done_pipe(struct p_context *ctx, pipe_style type) -{ - struct pipe *new_p; - done_command(ctx); /* implicit closure of previous command */ - debug_printf("done_pipe, type %d\n", type); - ctx->pipe->followup = type; - ctx->pipe->r_mode = ctx->w; - new_p=new_pipe(); - ctx->pipe->next = new_p; - ctx->pipe = new_p; - ctx->child = NULL; - done_command(ctx); /* set up new pipe to accept commands */ - return 0; -} - -#ifndef __U_BOOT__ -/* peek ahead in the in_str to find out if we have a "&n" construct, - * as in "2>&1", that represents duplicating a file descriptor. - * returns either -2 (syntax error), -1 (no &), or the number found. - */ -static int redirect_dup_num(struct in_str *input) -{ - int ch, d=0, ok=0; - ch = b_peek(input); - if (ch != '&') return -1; - - b_getch(input); /* get the & */ - ch=b_peek(input); - if (ch == '-') { - b_getch(input); - return -3; /* "-" represents "close me" */ - } - while (isdigit(ch)) { - d = d*10+(ch-'0'); - ok=1; - b_getch(input); - ch = b_peek(input); - } - if (ok) return d; - - error_msg("ambiguous redirect"); - return -2; -} - -/* If a redirect is immediately preceded by a number, that number is - * supposed to tell which file descriptor to redirect. This routine - * looks for such preceding numbers. In an ideal world this routine - * needs to handle all the following classes of redirects... - * echo 2>foo # redirects fd 2 to file "foo", nothing passed to echo - * echo 49>foo # redirects fd 49 to file "foo", nothing passed to echo - * echo -2>foo # redirects fd 1 to file "foo", "-2" passed to echo - * echo 49x>foo # redirects fd 1 to file "foo", "49x" passed to echo - * A -1 output from this program means no valid number was found, so the - * caller should use the appropriate default for this redirection. - */ -static int redirect_opt_num(o_string *o) -{ - int num; - - if (o->length==0) return -1; - for(num=0; numlength; num++) { - if (!isdigit(*(o->data+num))) { - return -1; - } - } - /* reuse num (and save an int) */ - num=atoi(o->data); - b_reset(o); - return num; -} - -FILE *generate_stream_from_list(struct pipe *head) -{ - FILE *pf; -#if 1 - int pid, channel[2]; - if (pipe(channel)<0) perror_msg_and_die("pipe"); - pid=fork(); - if (pid<0) { - perror_msg_and_die("fork"); - } else if (pid==0) { - close(channel[0]); - if (channel[1] != 1) { - dup2(channel[1],1); - close(channel[1]); - } -#if 0 -#define SURROGATE "surrogate response" - write(1,SURROGATE,sizeof(SURROGATE)); - _exit(run_list(head)); -#else - _exit(run_list_real(head)); /* leaks memory */ -#endif - } - debug_printf("forked child %d\n",pid); - close(channel[1]); - pf = fdopen(channel[0],"r"); - debug_printf("pipe on FILE *%p\n",pf); -#else - free_pipe_list(head,0); - pf=popen("echo surrogate response","r"); - debug_printf("started fake pipe on FILE *%p\n",pf); -#endif - return pf; -} - -/* this version hacked for testing purposes */ -/* return code is exit status of the process that is run. */ -static int process_command_subs(o_string *dest, struct p_context *ctx, struct in_str *input, int subst_end) -{ - int retcode; - o_string result=NULL_O_STRING; - struct p_context inner; - FILE *p; - struct in_str pipe_str; - initialize_context(&inner); - - /* recursion to generate command */ - retcode = parse_stream(&result, &inner, input, subst_end); - if (retcode != 0) return retcode; /* syntax error or EOF */ - done_word(&result, &inner); - done_pipe(&inner, PIPE_SEQ); - b_free(&result); - - p=generate_stream_from_list(inner.list_head); - if (p==NULL) return 1; - mark_open(fileno(p)); - setup_file_in_str(&pipe_str, p); - - /* now send results of command back into original context */ - retcode = parse_stream(dest, ctx, &pipe_str, '\0'); - /* XXX In case of a syntax error, should we try to kill the child? - * That would be tough to do right, so just read until EOF. */ - if (retcode == 1) { - while (b_getch(&pipe_str)!=EOF) { /* discard */ }; - } - - debug_printf("done reading from pipe, pclose()ing\n"); - /* This is the step that wait()s for the child. Should be pretty - * safe, since we just read an EOF from its stdout. We could try - * to better, by using wait(), and keeping track of background jobs - * at the same time. That would be a lot of work, and contrary - * to the KISS philosophy of this program. */ - mark_closed(fileno(p)); - retcode=pclose(p); - free_pipe_list(inner.list_head,0); - debug_printf("pclosed, retcode=%d\n",retcode); - /* XXX this process fails to trim a single trailing newline */ - return retcode; -} - -static int parse_group(o_string *dest, struct p_context *ctx, - struct in_str *input, int ch) -{ - int rcode, endch=0; - struct p_context sub; - struct child_prog *child = ctx->child; - if (child->argv) { - syntax(); - return 1; /* syntax error, groups and arglists don't mix */ - } - initialize_context(&sub); - switch(ch) { - case '(': endch=')'; child->subshell=1; break; - case '{': endch='}'; break; - default: syntax(); /* really logic error */ - } - rcode=parse_stream(dest,&sub,input,endch); - done_word(dest,&sub); /* finish off the final word in the subcontext */ - done_pipe(&sub, PIPE_SEQ); /* and the final command there, too */ - child->group = sub.list_head; - return rcode; - /* child remains "open", available for possible redirects */ -} -#endif - -/* basically useful version until someone wants to get fancier, - * see the bash man page under "Parameter Expansion" */ -static char *lookup_param(char *src) -{ - char *p; - char *sep; - char *default_val = NULL; - int assign = 0; - int expand_empty = 0; - - if (!src) - return NULL; - - sep = strchr(src, ':'); - - if (sep) { - *sep = '\0'; - if (*(sep + 1) == '-') - default_val = sep+2; - if (*(sep + 1) == '=') { - default_val = sep+2; - assign = 1; - } - if (*(sep + 1) == '+') { - default_val = sep+2; - expand_empty = 1; - } - } - - p = getenv(src); - if (!p) - p = get_local_var(src); - - if (!p || strlen(p) == 0) { - p = default_val; - if (assign) { - char *var = malloc(strlen(src)+strlen(default_val)+2); - if (var) { - sprintf(var, "%s=%s", src, default_val); - set_local_var(var, 0); - } - free(var); - } - } else if (expand_empty) { - p += strlen(p); - } - - if (sep) - *sep = ':'; - - return p; -} - -#ifdef __U_BOOT__ -static char *get_dollar_var(char ch) -{ - static char buf[40]; - - buf[0] = '\0'; - switch (ch) { - case '?': - sprintf(buf, "%u", (unsigned int)last_return_code); - break; - default: - return NULL; - } - return buf; -} -#endif - -/* return code: 0 for OK, 1 for syntax error */ -static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input) -{ -#ifndef __U_BOOT__ - int i, advance=0; -#else - int advance=0; -#endif -#ifndef __U_BOOT__ - char sep[]=" "; -#endif - int ch = input->peek(input); /* first character after the $ */ - debug_printf("handle_dollar: ch=%c\n",ch); - if (isalpha(ch)) { - b_addchr(dest, SPECIAL_VAR_SYMBOL); - ctx->child->sp++; - while(ch=b_peek(input),isalnum(ch) || ch=='_') { - b_getch(input); - b_addchr(dest,ch); - } - b_addchr(dest, SPECIAL_VAR_SYMBOL); -#ifndef __U_BOOT__ - } else if (isdigit(ch)) { - i = ch-'0'; /* XXX is $0 special? */ - if (i 0) b_adduint(dest, last_bg_pid); - advance = 1; - break; -#endif - case '?': -#ifndef __U_BOOT__ - b_adduint(dest,last_return_code); -#else - ctx->child->sp++; - b_addchr(dest, SPECIAL_VAR_SYMBOL); - b_addchr(dest, '$'); - b_addchr(dest, '?'); - b_addchr(dest, SPECIAL_VAR_SYMBOL); -#endif - advance = 1; - break; -#ifndef __U_BOOT__ - case '#': - b_adduint(dest,global_argc ? global_argc-1 : 0); - advance = 1; - break; -#endif - case '{': - b_addchr(dest, SPECIAL_VAR_SYMBOL); - ctx->child->sp++; - b_getch(input); - /* XXX maybe someone will try to escape the '}' */ - while(ch=b_getch(input),ch!=EOF && ch!='}') { - b_addchr(dest,ch); - } - if (ch != '}') { - syntax(); - return 1; - } - b_addchr(dest, SPECIAL_VAR_SYMBOL); - break; -#ifndef __U_BOOT__ - case '(': - b_getch(input); - process_command_subs(dest, ctx, input, ')'); - break; - case '*': - sep[0]=ifs[0]; - for (i=1; iquote); - } - /* Eat the character if the flag was set. If the compiler - * is smart enough, we could substitute "b_getch(input);" - * for all the "advance = 1;" above, and also end up with - * a nice size-optimized program. Hah! That'll be the day. - */ - if (advance) b_getch(input); - return 0; -} - -#ifndef __U_BOOT__ -int parse_string(o_string *dest, struct p_context *ctx, const char *src) -{ - struct in_str foo; - setup_string_in_str(&foo, src); - return parse_stream(dest, ctx, &foo, '\0'); -} -#endif - -/* return code is 0 for normal exit, 1 for syntax error */ -static int parse_stream(o_string *dest, struct p_context *ctx, - struct in_str *input, int end_trigger) -{ - unsigned int ch, m; -#ifndef __U_BOOT__ - int redir_fd; - redir_type redir_style; -#endif - int next; - - /* Only double-quote state is handled in the state variable dest->quote. - * A single-quote triggers a bypass of the main loop until its mate is - * found. When recursing, quote state is passed in via dest->quote. */ - - debug_printf("parse_stream, end_trigger=%d\n",end_trigger); - while ((ch=b_getch(input))!=EOF) { - m = map[ch]; -#ifdef __U_BOOT__ - if (input->__promptme == 0) return 1; -#endif - next = (ch == '\n') ? 0 : b_peek(input); - - debug_printf("parse_stream: ch=%c (%d) m=%d quote=%d - %c\n", - ch >= ' ' ? ch : '.', ch, m, - dest->quote, ctx->stack == NULL ? '*' : '.'); - - if (m==0 || ((m==1 || m==2) && dest->quote)) { - b_addqchr(dest, ch, dest->quote); - } else { - if (m==2) { /* unquoted IFS */ - if (done_word(dest, ctx)) { - return 1; - } - /* If we aren't performing a substitution, treat a newline as a - * command separator. */ - if (end_trigger != '\0' && ch=='\n') - done_pipe(ctx,PIPE_SEQ); - } - if (ch == end_trigger && !dest->quote && ctx->w==RES_NONE) { - debug_printf("leaving parse_stream (triggered)\n"); - return 0; - } -#if 0 - if (ch=='\n') { - /* Yahoo! Time to run with it! */ - done_pipe(ctx,PIPE_SEQ); - run_list(ctx->list_head); - initialize_context(ctx); - } -#endif - if (m!=2) switch (ch) { - case '#': - if (dest->length == 0 && !dest->quote) { - while(ch=b_peek(input),ch!=EOF && ch!='\n') { b_getch(input); } - } else { - b_addqchr(dest, ch, dest->quote); - } - break; - case '\\': - if (next == EOF) { - syntax(); - return 1; - } - b_addqchr(dest, '\\', dest->quote); - b_addqchr(dest, b_getch(input), dest->quote); - break; - case '$': - if (handle_dollar(dest, ctx, input)!=0) return 1; - break; - case '\'': - dest->nonnull = 1; - while(ch=b_getch(input),ch!=EOF && ch!='\'') { -#ifdef __U_BOOT__ - if(input->__promptme == 0) return 1; -#endif - b_addchr(dest,ch); - } - if (ch==EOF) { - syntax(); - return 1; - } - break; - case '"': - dest->nonnull = 1; - dest->quote = !dest->quote; - break; -#ifndef __U_BOOT__ - case '`': - process_command_subs(dest, ctx, input, '`'); - break; - case '>': - redir_fd = redirect_opt_num(dest); - done_word(dest, ctx); - redir_style=REDIRECT_OVERWRITE; - if (next == '>') { - redir_style=REDIRECT_APPEND; - b_getch(input); - } else if (next == '(') { - syntax(); /* until we support >(list) Process Substitution */ - return 1; - } - setup_redirect(ctx, redir_fd, redir_style, input); - break; - case '<': - redir_fd = redirect_opt_num(dest); - done_word(dest, ctx); - redir_style=REDIRECT_INPUT; - if (next == '<') { - redir_style=REDIRECT_HEREIS; - b_getch(input); - } else if (next == '>') { - redir_style=REDIRECT_IO; - b_getch(input); - } else if (next == '(') { - syntax(); /* until we support <(list) Process Substitution */ - return 1; - } - setup_redirect(ctx, redir_fd, redir_style, input); - break; -#endif - case ';': - done_word(dest, ctx); - done_pipe(ctx,PIPE_SEQ); - break; - case '&': - done_word(dest, ctx); - if (next=='&') { - b_getch(input); - done_pipe(ctx,PIPE_AND); - } else { -#ifndef __U_BOOT__ - done_pipe(ctx,PIPE_BG); -#else - syntax_err(); - return 1; -#endif - } - break; - case '|': - done_word(dest, ctx); - if (next=='|') { - b_getch(input); - done_pipe(ctx,PIPE_OR); - } else { - /* we could pick up a file descriptor choice here - * with redirect_opt_num(), but bash doesn't do it. - * "echo foo 2| cat" yields "foo 2". */ -#ifndef __U_BOOT__ - done_command(ctx); -#else - syntax_err(); - return 1; -#endif - } - break; -#ifndef __U_BOOT__ - case '(': - case '{': - if (parse_group(dest, ctx, input, ch)!=0) return 1; - break; - case ')': - case '}': - syntax(); /* Proper use of this character caught by end_trigger */ - return 1; - break; -#endif - case SUBSTED_VAR_SYMBOL: - dest->nonnull = 1; - while (ch = b_getch(input), ch != EOF && - ch != SUBSTED_VAR_SYMBOL) { - debug_printf("subst, pass=%d\n", ch); - if (input->__promptme == 0) - return 1; - b_addchr(dest, ch); - } - debug_printf("subst, term=%d\n", ch); - if (ch == EOF) { - syntax(); - return 1; - } - break; - default: - syntax(); /* this is really an internal logic error */ - return 1; - } - } - } - /* complain if quote? No, maybe we just finished a command substitution - * that was quoted. Example: - * $ echo "`cat foo` plus more" - * and we just got the EOF generated by the subshell that ran "cat foo" - * The only real complaint is if we got an EOF when end_trigger != '\0', - * that is, we were really supposed to get end_trigger, and never got - * one before the EOF. Can't use the standard "syntax error" return code, - * so that parse_stream_outer can distinguish the EOF and exit smoothly. */ - debug_printf("leaving parse_stream (EOF)\n"); - if (end_trigger != '\0') return -1; - return 0; -} - -static void mapset(const unsigned char *set, int code) -{ - const unsigned char *s; - for (s=set; *s; s++) map[*s] = code; -} - -static void update_ifs_map(void) -{ - /* char *ifs and char map[256] are both globals. */ - ifs = (uchar *)getenv("IFS"); - if (ifs == NULL) ifs=(uchar *)" \t\n"; - /* Precompute a list of 'flow through' behavior so it can be treated - * quickly up front. Computation is necessary because of IFS. - * Special case handling of IFS == " \t\n" is not implemented. - * The map[] array only really needs two bits each, and on most machines - * that would be faster because of the reduced L1 cache footprint. - */ - memset(map,0,sizeof(map)); /* most characters flow through always */ -#ifndef __U_BOOT__ - mapset((uchar *)"\\$'\"`", 3); /* never flow through */ - mapset((uchar *)"<>;&|(){}#", 1); /* flow through if quoted */ -#else - { - uchar subst[2] = {SUBSTED_VAR_SYMBOL, 0}; - mapset(subst, 3); /* never flow through */ - } - mapset((uchar *)"\\$'\"", 3); /* never flow through */ - mapset((uchar *)";&|#", 1); /* flow through if quoted */ -#endif - mapset(ifs, 2); /* also flow through if quoted */ -} - -/* most recursion does not come through here, the exeception is - * from builtin_source() */ -static int parse_stream_outer(struct in_str *inp, int flag) -{ - - struct p_context ctx; - o_string temp=NULL_O_STRING; - int rcode; -#ifdef __U_BOOT__ - int code = 0; -#endif - do { - ctx.type = flag; - initialize_context(&ctx); - update_ifs_map(); - if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset((uchar *)";$&|", 0); - inp->promptmode=1; - rcode = parse_stream(&temp, &ctx, inp, '\n'); -#ifdef __U_BOOT__ - if (rcode == 1) flag_repeat = 0; -#endif - if (rcode != 1 && ctx.old_flag != 0) { - syntax(); -#ifdef __U_BOOT__ - flag_repeat = 0; -#endif - } - if (rcode != 1 && ctx.old_flag == 0) { - done_word(&temp, &ctx); - done_pipe(&ctx,PIPE_SEQ); -#ifndef __U_BOOT__ - run_list(ctx.list_head); -#else - code = run_list(ctx.list_head); - if (code == -2) { /* exit */ - b_free(&temp); - code = 0; - /* XXX hackish way to not allow exit from main loop */ - if (inp->peek == file_peek) { - printf("exit not allowed from main input shell.\n"); - continue; - } - break; - } - if (code == -1) - flag_repeat = 0; -#endif - } else { - if (ctx.old_flag != 0) { - free(ctx.stack); - b_reset(&temp); - } -#ifdef __U_BOOT__ - if (inp->__promptme == 0) printf("\n"); - inp->__promptme = 1; -#endif - temp.nonnull = 0; - temp.quote = 0; - inp->p = NULL; - free_pipe_list(ctx.list_head,0); - } - b_free(&temp); - } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP)); /* loop on syntax errors, return on EOF */ -#ifndef __U_BOOT__ - return 0; -#else - return (code != 0) ? 1 : 0; -#endif /* __U_BOOT__ */ -} - -#ifndef __U_BOOT__ -static int parse_string_outer(const char *s, int flag) -#else -int parse_string_outer(const char *s, int flag) -#endif /* __U_BOOT__ */ -{ - struct in_str input; -#ifdef __U_BOOT__ - char *p = NULL; - int rcode; - if ( !s || !*s) - return 1; - if (!(p = strchr(s, '\n')) || *++p) { - p = xmalloc(strlen(s) + 2); - strcpy(p, s); - strcat(p, "\n"); - setup_string_in_str(&input, p); - rcode = parse_stream_outer(&input, flag); - free(p); - return rcode; - } else { -#endif - setup_string_in_str(&input, s); - return parse_stream_outer(&input, flag); -#ifdef __U_BOOT__ - } -#endif -} - -#ifndef __U_BOOT__ -static int parse_file_outer(FILE *f) -#else -int parse_file_outer(void) -#endif -{ - int rcode; - struct in_str input; -#ifndef __U_BOOT__ - setup_file_in_str(&input, f); -#else - setup_file_in_str(&input); -#endif - rcode = parse_stream_outer(&input, FLAG_PARSE_SEMICOLON); - return rcode; -} - -#ifdef __U_BOOT__ -#ifdef CONFIG_NEEDS_MANUAL_RELOC -static void u_boot_hush_reloc(void) -{ - unsigned long addr; - struct reserved_combo *r; - - for (r=reserved_list; rliteral) + gd->reloc_off; - r->literal = (char *)addr; - } -} -#endif - -int u_boot_hush_start(void) -{ - if (top_vars == NULL) { - top_vars = malloc(sizeof(struct variables)); - top_vars->name = "HUSH_VERSION"; - top_vars->value = "0.01"; - top_vars->next = NULL; - top_vars->flg_export = 0; - top_vars->flg_read_only = 1; -#ifdef CONFIG_NEEDS_MANUAL_RELOC - u_boot_hush_reloc(); -#endif - } - return 0; -} - -static void *xmalloc(size_t size) -{ - void *p = NULL; - - if (!(p = malloc(size))) { - printf("ERROR : memory not allocated\n"); - for(;;); - } - return p; -} - -static void *xrealloc(void *ptr, size_t size) -{ - void *p = NULL; - - if (!(p = realloc(ptr, size))) { - printf("ERROR : memory not allocated\n"); - for(;;); - } - return p; -} -#endif /* __U_BOOT__ */ - -#ifndef __U_BOOT__ -/* Make sure we have a controlling tty. If we get started under a job - * aware app (like bash for example), make sure we are now in charge so - * we don't fight over who gets the foreground */ -static void setup_job_control(void) -{ - static pid_t shell_pgrp; - /* Loop until we are in the foreground. */ - while (tcgetpgrp (shell_terminal) != (shell_pgrp = getpgrp ())) - kill (- shell_pgrp, SIGTTIN); - - /* Ignore interactive and job-control signals. */ - signal(SIGINT, SIG_IGN); - signal(SIGQUIT, SIG_IGN); - signal(SIGTERM, SIG_IGN); - signal(SIGTSTP, SIG_IGN); - signal(SIGTTIN, SIG_IGN); - signal(SIGTTOU, SIG_IGN); - signal(SIGCHLD, SIG_IGN); - - /* Put ourselves in our own process group. */ - setsid(); - shell_pgrp = getpid (); - setpgid (shell_pgrp, shell_pgrp); - - /* Grab control of the terminal. */ - tcsetpgrp(shell_terminal, shell_pgrp); -} - -int hush_main(int argc, char * const *argv) -{ - int opt; - FILE *input; - char **e = environ; - - /* XXX what should these be while sourcing /etc/profile? */ - global_argc = argc; - global_argv = argv; - - /* (re?) initialize globals. Sometimes hush_main() ends up calling - * hush_main(), therefore we cannot rely on the BSS to zero out this - * stuff. Reset these to 0 every time. */ - ifs = NULL; - /* map[] is taken care of with call to update_ifs_map() */ - fake_mode = 0; - interactive = 0; - close_me_head = NULL; - last_bg_pid = 0; - job_list = NULL; - last_jobid = 0; - - /* Initialize some more globals to non-zero values */ - set_cwd(); -#ifdef CONFIG_FEATURE_COMMAND_EDITING - cmdedit_set_initial_prompt(); -#else - PS1 = NULL; -#endif - PS2 = "> "; - - /* initialize our shell local variables with the values - * currently living in the environment */ - if (e) { - for (; *e; e++) - set_local_var(*e, 2); /* without call putenv() */ - } - - last_return_code=EXIT_SUCCESS; - - - if (argv[0] && argv[0][0] == '-') { - debug_printf("\nsourcing /etc/profile\n"); - if ((input = fopen("/etc/profile", "r")) != NULL) { - mark_open(fileno(input)); - parse_file_outer(input); - mark_closed(fileno(input)); - fclose(input); - } - } - input=stdin; - - while ((opt = getopt(argc, argv, "c:xif")) > 0) { - switch (opt) { - case 'c': - { - global_argv = argv+optind; - global_argc = argc-optind; - opt = parse_string_outer(optarg, FLAG_PARSE_SEMICOLON); - goto final_return; - } - break; - case 'i': - interactive++; - break; - case 'f': - fake_mode++; - break; - default: -#ifndef BB_VER - fprintf(stderr, "Usage: sh [FILE]...\n" - " or: sh -c command [args]...\n\n"); - exit(EXIT_FAILURE); -#else - show_usage(); -#endif - } - } - /* A shell is interactive if the `-i' flag was given, or if all of - * the following conditions are met: - * no -c command - * no arguments remaining or the -s flag given - * standard input is a terminal - * standard output is a terminal - * Refer to Posix.2, the description of the `sh' utility. */ - if (argv[optind]==NULL && input==stdin && - isatty(fileno(stdin)) && isatty(fileno(stdout))) { - interactive++; - } - - debug_printf("\ninteractive=%d\n", interactive); - if (interactive) { - /* Looks like they want an interactive shell */ -#ifndef CONFIG_FEATURE_SH_EXTRA_QUIET - printf( "\n\n" BB_BANNER " hush - the humble shell v0.01 (testing)\n"); - printf( "Enter 'help' for a list of built-in commands.\n\n"); -#endif - setup_job_control(); - } - - if (argv[optind]==NULL) { - opt=parse_file_outer(stdin); - goto final_return; - } - - debug_printf("\nrunning script '%s'\n", argv[optind]); - global_argv = argv+optind; - global_argc = argc-optind; - input = xfopen(argv[optind], "r"); - opt = parse_file_outer(input); - -#ifdef CONFIG_FEATURE_CLEAN_UP - fclose(input); - if (cwd && cwd != unknown) - free((char*)cwd); - { - struct variables *cur, *tmp; - for(cur = top_vars; cur; cur = tmp) { - tmp = cur->next; - if (!cur->flg_read_only) { - free(cur->name); - free(cur->value); - free(cur); - } - } - } -#endif - -final_return: - return(opt?opt:last_return_code); -} -#endif - -static char *insert_var_value(char *inp) -{ - return insert_var_value_sub(inp, 0); -} - -static char *insert_var_value_sub(char *inp, int tag_subst) -{ - int res_str_len = 0; - int len; - int done = 0; - char *p, *p1, *res_str = NULL; - - while ((p = strchr(inp, SPECIAL_VAR_SYMBOL))) { - /* check the beginning of the string for normal charachters */ - if (p != inp) { - /* copy any charachters to the result string */ - len = p - inp; - res_str = xrealloc(res_str, (res_str_len + len)); - strncpy((res_str + res_str_len), inp, len); - res_str_len += len; - } - inp = ++p; - /* find the ending marker */ - p = strchr(inp, SPECIAL_VAR_SYMBOL); - *p = '\0'; - /* look up the value to substitute */ - if ((p1 = lookup_param(inp))) { - if (tag_subst) - len = res_str_len + strlen(p1) + 2; - else - len = res_str_len + strlen(p1); - res_str = xrealloc(res_str, (1 + len)); - if (tag_subst) { - /* - * copy the variable value to the result - * string - */ - strcpy((res_str + res_str_len + 1), p1); - - /* - * mark the replaced text to be accepted as - * is - */ - res_str[res_str_len] = SUBSTED_VAR_SYMBOL; - res_str[res_str_len + 1 + strlen(p1)] = - SUBSTED_VAR_SYMBOL; - } else - /* - * copy the variable value to the result - * string - */ - strcpy((res_str + res_str_len), p1); - - res_str_len = len; - } - *p = SPECIAL_VAR_SYMBOL; - inp = ++p; - done = 1; - } - if (done) { - res_str = xrealloc(res_str, (1 + res_str_len + strlen(inp))); - strcpy((res_str + res_str_len), inp); - while ((p = strchr(res_str, '\n'))) { - *p = ' '; - } - } - return (res_str == NULL) ? inp : res_str; -} - -static char **make_list_in(char **inp, char *name) -{ - int len, i; - int name_len = strlen(name); - int n = 0; - char **list; - char *p1, *p2, *p3; - - /* create list of variable values */ - list = xmalloc(sizeof(*list)); - for (i = 0; inp[i]; i++) { - p3 = insert_var_value(inp[i]); - p1 = p3; - while (*p1) { - if ((*p1 == ' ')) { - p1++; - continue; - } - if ((p2 = strchr(p1, ' '))) { - len = p2 - p1; - } else { - len = strlen(p1); - p2 = p1 + len; - } - /* we use n + 2 in realloc for list,because we add - * new element and then we will add NULL element */ - list = xrealloc(list, sizeof(*list) * (n + 2)); - list[n] = xmalloc(2 + name_len + len); - strcpy(list[n], name); - strcat(list[n], "="); - strncat(list[n], p1, len); - list[n++][name_len + len + 1] = '\0'; - p1 = p2; - } - if (p3 != inp[i]) free(p3); - } - list[n] = NULL; - return list; -} - -/* Make new string for parser */ -static char * make_string(char ** inp) -{ - char *p; - char *str = NULL; - int n; - int len = 2; - char *noeval_str; - int noeval = 0; - - noeval_str = get_local_var("HUSH_NO_EVAL"); - if (noeval_str != NULL && *noeval_str != '0' && *noeval_str != '\0') - noeval = 1; - for (n = 0; inp[n]; n++) { - p = insert_var_value_sub(inp[n], noeval); - str = xrealloc(str, (len + strlen(p))); - if (n) { - strcat(str, " "); - } else { - *str = '\0'; - } - strcat(str, p); - len = strlen(str) + 3; - if (p != inp[n]) free(p); - } - len = strlen(str); - *(str + len) = '\n'; - *(str + len + 1) = '\0'; - return str; -} - -#ifdef __U_BOOT__ -static int do_showvar(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - int i, k; - int rcode = 0; - struct variables *cur; - - if (argc == 1) { /* Print all env variables */ - for (cur = top_vars; cur; cur = cur->next) { - printf ("%s=%s\n", cur->name, cur->value); - if (ctrlc ()) { - puts ("\n ** Abort\n"); - return 1; - } - } - return 0; - } - for (i = 1; i < argc; ++i) { /* print single env variables */ - char *name = argv[i]; - - k = -1; - for (cur = top_vars; cur; cur = cur->next) { - if(strcmp (cur->name, name) == 0) { - k = 0; - printf ("%s=%s\n", cur->name, cur->value); - } - if (ctrlc ()) { - puts ("\n ** Abort\n"); - return 1; - } - } - if (k < 0) { - printf ("## Error: \"%s\" not defined\n", name); - rcode ++; - } - } - return rcode; -} - -U_BOOT_CMD( - showvar, CONFIG_SYS_MAXARGS, 1, do_showvar, - "print local hushshell variables", - "\n - print values of all hushshell variables\n" - "showvar name ...\n" - " - print value of hushshell variable 'name'" -); - -#endif -/****************************************************************************/ diff --git a/common/image-android.c b/common/image-android.c new file mode 100644 index 0000000000..59079fc32b --- /dev/null +++ b/common/image-android.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2011 Sebastian Andrzej Siewior + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; + +/** + * android_image_get_kernel() - processes kernel part of Android boot images + * @hdr: Pointer to image header, which is at the start + * of the image. + * @verify: Checksum verification flag. Currently unimplemented. + * @os_data: Pointer to a ulong variable, will hold os data start + * address. + * @os_len: Pointer to a ulong variable, will hold os data length. + * + * This function returns the os image's start address and length. Also, + * it appends the kernel command line to the bootargs env variable. + * + * Return: Zero, os start address and length on success, + * otherwise on failure. + */ +int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, + ulong *os_data, ulong *os_len) +{ + /* + * Not all Android tools use the id field for signing the image with + * sha1 (or anything) so we don't check it. It is not obvious that the + * string is null terminated so we take care of this. + */ + strncpy(andr_tmp_str, hdr->name, ANDR_BOOT_NAME_SIZE); + andr_tmp_str[ANDR_BOOT_NAME_SIZE] = '\0'; + if (strlen(andr_tmp_str)) + printf("Android's image name: %s\n", andr_tmp_str); + + printf("Kernel load addr 0x%08x size %u KiB\n", + hdr->kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024)); + + int len = 0; + if (*hdr->cmdline) { + printf("Kernel command line: %s\n", hdr->cmdline); + len += strlen(hdr->cmdline); + } + + char *bootargs = getenv("bootargs"); + if (bootargs) + len += strlen(bootargs); + + char *newbootargs = malloc(len + 2); + if (!newbootargs) { + puts("Error: malloc in android_image_get_kernel failed!\n"); + return -ENOMEM; + } + *newbootargs = '\0'; + + if (bootargs) { + strcpy(newbootargs, bootargs); + strcat(newbootargs, " "); + } + if (*hdr->cmdline) + strcat(newbootargs, hdr->cmdline); + + setenv("bootargs", newbootargs); + + if (os_data) { + *os_data = (ulong)hdr; + *os_data += hdr->page_size; + } + if (os_len) + *os_len = hdr->kernel_size; + return 0; +} + +int android_image_check_header(const struct andr_img_hdr *hdr) +{ + return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE); +} + +ulong android_image_get_end(const struct andr_img_hdr *hdr) +{ + ulong end; + /* + * The header takes a full page, the remaining components are aligned + * on page boundary + */ + end = (ulong)hdr; + end += hdr->page_size; + end += ALIGN(hdr->kernel_size, hdr->page_size); + end += ALIGN(hdr->ramdisk_size, hdr->page_size); + end += ALIGN(hdr->second_size, hdr->page_size); + + return end; +} + +ulong android_image_get_kload(const struct andr_img_hdr *hdr) +{ + return hdr->kernel_addr; +} + +int android_image_get_ramdisk(const struct andr_img_hdr *hdr, + ulong *rd_data, ulong *rd_len) +{ + if (!hdr->ramdisk_size) + return -1; + + printf("RAM disk load addr 0x%08x size %u KiB\n", + hdr->ramdisk_addr, DIV_ROUND_UP(hdr->ramdisk_size, 1024)); + + *rd_data = (unsigned long)hdr; + *rd_data += hdr->page_size; + *rd_data += ALIGN(hdr->kernel_size, hdr->page_size); + + *rd_len = hdr->ramdisk_size; + return 0; +} diff --git a/common/image-fdt.c b/common/image-fdt.c index 2e22cca54e..e3f06cdd1a 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -29,6 +29,7 @@ static void fdt_error(const char *msg) puts(" - must RESET the board to recover.\n"); } +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) static const image_header_t *image_get_fdt(ulong fdt_addr) { const image_header_t *fdt_hdr = map_sysmem(fdt_addr, 0); @@ -55,12 +56,13 @@ static const image_header_t *image_get_fdt(ulong fdt_addr) fdt_error("uImage is compressed"); return NULL; } - if (fdt_check_header((char *)image_get_data(fdt_hdr)) != 0) { + if (fdt_check_header((void *)image_get_data(fdt_hdr)) != 0) { fdt_error("uImage data is not a fdt"); return NULL; } return fdt_hdr; } +#endif /** * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable @@ -220,11 +222,13 @@ error: int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, bootm_headers_t *images, char **of_flat_tree, ulong *of_size) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) const image_header_t *fdt_hdr; + ulong load, load_end; + ulong image_start, image_data, image_end; +#endif ulong fdt_addr; char *fdt_blob = NULL; - ulong image_start, image_data, image_end; - ulong load, load_end; void *buf; #if defined(CONFIG_FIT) const char *fit_uname_config = images->fit_uname_cfg; @@ -233,6 +237,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, int fdt_noffset; #endif const char *select = NULL; + int ok_no_fdt = 0; *of_flat_tree = NULL; *of_size = 0; @@ -298,13 +303,14 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, */ buf = map_sysmem(fdt_addr, 0); switch (genimg_get_format(buf)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: /* verify fdt_addr points to a valid image header */ printf("## Flattened Device Tree from Legacy Image at %08lx\n", fdt_addr); fdt_hdr = image_get_fdt(fdt_addr); if (!fdt_hdr) - goto error; + goto no_fdt; /* * move image data to the load address, @@ -337,6 +343,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, fdt_addr = load; break; +#endif case IMAGE_FORMAT_FIT: /* * This case will catch both: new uImage format @@ -349,7 +356,6 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, ulong load, len; fdt_noffset = fit_image_load(images, - FIT_FDT_PROP, fdt_addr, &fit_uname_fdt, &fit_uname_config, arch, IH_TYPE_FLATDT, @@ -374,7 +380,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, break; default: puts("ERROR: Did not find a cmdline Flattened Device Tree\n"); - goto error; + goto no_fdt; } printf(" Booting using the fdt blob at %#08lx\n", fdt_addr); @@ -408,11 +414,11 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, } } else { debug("## No Flattened Device Tree\n"); - return 0; + goto no_fdt; } } else { debug("## No Flattened Device Tree\n"); - return 0; + goto no_fdt; } *of_flat_tree = fdt_blob; @@ -422,9 +428,15 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, return 0; +no_fdt: + ok_no_fdt = 1; error: *of_flat_tree = NULL; *of_size = 0; + if (!select && ok_no_fdt) { + debug("Continuing to boot without FDT\n"); + return 0; + } return 1; } @@ -445,7 +457,7 @@ __weak int ft_verify_fdt(void *fdt) return 1; } -__weak int arch_fixup_memory_node(void *blob) +__weak int arch_fixup_fdt(void *blob) { return 0; } @@ -455,25 +467,41 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, { ulong *initrd_start = &images->initrd_start; ulong *initrd_end = &images->initrd_end; - int ret; + int ret = -EPERM; + int fdt_ret; - if (fdt_chosen(blob, 1) < 0) { - puts("ERROR: /chosen node create failed"); - puts(" - must RESET the board to recover.\n"); - return -1; + if (fdt_chosen(blob) < 0) { + printf("ERROR: /chosen node create failed\n"); + goto err; + } + if (arch_fixup_fdt(blob) < 0) { + printf("ERROR: arch-specific fdt fixup failed\n"); + goto err; + } + if (IMAGE_OF_BOARD_SETUP) { + fdt_ret = ft_board_setup(blob, gd->bd); + if (fdt_ret) { + printf("ERROR: board-specific fdt fixup failed: %s\n", + fdt_strerror(fdt_ret)); + goto err; + } + } + if (IMAGE_OF_SYSTEM_SETUP) { + if (ft_system_setup(blob, gd->bd)) { + printf("ERROR: system-specific fdt fixup failed: %s\n", + fdt_strerror(fdt_ret)); + goto err; + } } - arch_fixup_memory_node(blob); - if (IMAAGE_OF_BOARD_SETUP) - ft_board_setup(blob, gd->bd); fdt_fixup_ethernet(blob); /* Delete the old LMB reservation */ lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob, (phys_size_t)fdt_totalsize(blob)); - ret = fdt_resize(blob); + ret = fdt_shrink_to_minimum(blob); if (ret < 0) - return ret; + goto err; of_size = ret; if (*initrd_start && *initrd_end) { @@ -483,9 +511,18 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, /* Create a new LMB reservation */ lmb_reserve(lmb, (ulong)blob, of_size); - fdt_initrd(blob, *initrd_start, *initrd_end, 1); + fdt_initrd(blob, *initrd_start, *initrd_end); if (!ft_verify_fdt(blob)) - return -1; + goto err; + +#if defined(CONFIG_SOC_KEYSTONE) + if (IMAGE_OF_BOARD_SETUP) + ft_board_setup_ex(blob, gd->bd); +#endif return 0; +err: + printf(" - must RESET the board to recover.\n\n"); + + return ret; } diff --git a/common/image-fit.c b/common/image-fit.c index 683c1a511d..b47d11024f 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -21,9 +21,10 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ #include -#include #include #include +#include +#include /*****************************************************************************/ /* New uImage format routines */ @@ -58,7 +59,7 @@ static int fit_parse_spec(const char *spec, char sepc, ulong addr_curr, * @conf_name double pointer to a char, will hold pointer to a configuration * unit name * - * fit_parse_conf() expects configuration spec in the for of []#, + * fit_parse_conf() expects configuration spec in the form of []#, * where is a FIT image address that contains configuration * with a unit name. * @@ -84,7 +85,7 @@ int fit_parse_conf(const char *spec, ulong addr_curr, * subimage * @image_name: double pointer to a char, will hold pointer to a subimage name * - * fit_parse_subimage() expects subimage spec in the for of + * fit_parse_subimage() expects subimage spec in the form of * []:, where is a FIT image address that contains * subimage with a unit name. * @@ -111,6 +112,33 @@ static void fit_get_debug(const void *fit, int noffset, fdt_strerror(err)); } +/** + * fit_get_subimage_count - get component (sub-image) count + * @fit: pointer to the FIT format image header + * @images_noffset: offset of images node + * + * returns: + * number of image components + */ +int fit_get_subimage_count(const void *fit, int images_noffset) +{ + int noffset; + int ndepth; + int count = 0; + + /* Process its subnodes, print out component images details */ + for (ndepth = 0, count = 0, + noffset = fdt_next_node(fit, images_noffset, &ndepth); + (noffset >= 0) && (ndepth > 0); + noffset = fdt_next_node(fit, noffset, &ndepth)) { + if (ndepth == 1) { + count++; + } + } + + return count; +} + #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT) /** * fit_print_contents - prints out the contents of the FIT format image @@ -343,6 +371,17 @@ void fit_image_print(const void *fit, int image_noffset, const char *p) else printf("%s\n", desc); + if (IMAGE_ENABLE_TIMESTAMP) { + time_t timestamp; + + ret = fit_get_timestamp(fit, 0, ×tamp); + printf("%s Created: ", p); + if (ret) + printf("unavailable\n"); + else + genimg_print_time(timestamp); + } + fit_image_get_type(fit, image_noffset, &type); printf("%s Type: %s\n", p, genimg_get_type_name(type)); @@ -411,7 +450,8 @@ void fit_image_print(const void *fit, int image_noffset, const char *p) } } } -#endif + +#endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT) */ /** * fit_get_desc - get node description property @@ -821,7 +861,7 @@ static int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore) * * returns: * 0, on success - * -1, on property read failure + * -ENOSPC if no space in device tree, -1 for other error */ int fit_set_timestamp(void *fit, int noffset, time_t timestamp) { @@ -835,7 +875,7 @@ int fit_set_timestamp(void *fit, int noffset, time_t timestamp) printf("Can't set '%s' property for '%s' node (%s)\n", FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL), fdt_strerror(ret)); - return -1; + return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -1; } return 0; @@ -871,6 +911,10 @@ int calculate_hash(const void *data, int data_len, const char *algo, sha1_csum_wd((unsigned char *)data, data_len, (unsigned char *)value, CHUNKSZ_SHA1); *value_len = 20; + } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) { + sha256_csum_wd((unsigned char *)data, data_len, + (unsigned char *)value, CHUNKSZ_SHA256); + *value_len = SHA256_SUM_LEN; } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) { md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5); *value_len = 16; @@ -1098,7 +1142,8 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch) if (fit_image_get_arch(fit, noffset, &image_arch)) return 0; - return (arch == image_arch); + return (arch == image_arch) || + (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64); } /** @@ -1320,7 +1365,7 @@ int fit_conf_find_compat(const void *fit, const void *fdt) * * When NULL is provided in second argument fit_conf_get_node() will search * for a default configuration node instead. Default configuration node unit - * name is retrived from FIT_DEFAULT_PROP property of the '/configurations' + * name is retrieved from FIT_DEFAULT_PROP property of the '/configurations' * node. * * returns: @@ -1418,7 +1463,7 @@ void fit_conf_print(const void *fit, int noffset, const char *p) printf("%s FDT: %s\n", p, uname); } -int fit_image_select(const void *fit, int rd_noffset, int verify) +static int fit_image_select(const void *fit, int rd_noffset, int verify) { fit_image_print(fit, rd_noffset, " "); @@ -1461,7 +1506,34 @@ int fit_get_node_from_config(bootm_headers_t *images, const char *prop_name, return noffset; } -int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, +/** + * fit_get_image_type_property() - get property name for IH_TYPE_... + * + * @return the properly name where we expect to find the image in the + * config node + */ +static const char *fit_get_image_type_property(int type) +{ + /* + * This is sort-of available in the uimage_type[] table in image.c + * but we don't have access to the sohrt name, and "fdt" is different + * anyway. So let's just keep it here. + */ + switch (type) { + case IH_TYPE_FLATDT: + return FIT_FDT_PROP; + case IH_TYPE_KERNEL: + return FIT_KERNEL_PROP; + case IH_TYPE_RAMDISK: + return FIT_RAMDISK_PROP; + case IH_TYPE_X86_SETUP: + return FIT_SETUP_PROP; + } + + return "unknown"; +} + +int fit_image_load(bootm_headers_t *images, ulong addr, const char **fit_unamep, const char **fit_uname_configp, int arch, int image_type, int bootstage_id, enum fit_load_op load_op, ulong *datap, ulong *lenp) @@ -1474,11 +1546,14 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, size_t size; int type_ok, os_ok; ulong load, data, len; + uint8_t os; + const char *prop_name; int ret; fit = map_sysmem(addr, 0); fit_uname = fit_unamep ? *fit_unamep : NULL; fit_uname_config = fit_uname_configp ? *fit_uname_configp : NULL; + prop_name = fit_get_image_type_property(image_type); printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr); bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT); @@ -1489,7 +1564,7 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, } bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT_OK); if (fit_uname) { - /* get ramdisk component image node offset */ + /* get FIT component image node offset */ bootstage_mark(bootstage_id + BOOTSTAGE_SUB_UNIT_NAME); noffset = fit_image_get_node(fit, fit_uname); } else { @@ -1518,7 +1593,7 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, images->fit_uname_cfg = fit_uname_config; if (IMAGE_ENABLE_VERIFY && images->verify) { puts(" Verifying Hash Integrity ... "); - if (!fit_config_verify(fit, cfg_noffset)) { + if (fit_config_verify(fit, cfg_noffset)) { puts("Bad Data Hash\n"); bootstage_error(bootstage_id + BOOTSTAGE_SUB_HASH); @@ -1548,12 +1623,13 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, } bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH); +#if !defined(USE_HOSTCC) && !defined(CONFIG_SANDBOX) if (!fit_image_check_target_arch(fit, noffset)) { puts("Unsupported Architecture\n"); bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH); return -ENOEXEC; } - +#endif if (image_type == IH_TYPE_FLATDT && !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) { puts("FDT image is compressed"); @@ -1565,10 +1641,15 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, (image_type == IH_TYPE_KERNEL && fit_image_check_type(fit, noffset, IH_TYPE_KERNEL_NOLOAD)); + os_ok = image_type == IH_TYPE_FLATDT || - fit_image_check_os(fit, noffset, IH_OS_LINUX); + fit_image_check_os(fit, noffset, IH_OS_LINUX) || + fit_image_check_os(fit, noffset, IH_OS_OPENRTOS); if (!type_ok || !os_ok) { - printf("No Linux %s %s Image\n", genimg_get_arch_name(arch), + fit_image_get_os(fit, noffset, &os); + printf("No %s %s %s Image\n", + genimg_get_os_name(os), + genimg_get_arch_name(arch), genimg_get_type_name(image_type)); bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL); return -EIO; @@ -1585,7 +1666,7 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, len = (ulong)size; /* verify that image data is a proper FDT blob */ - if (image_type == IH_TYPE_FLATDT && fdt_check_header((char *)buf)) { + if (image_type == IH_TYPE_FLATDT && fdt_check_header(buf)) { puts("Subimage data is not a FDT"); return -ENOEXEC; } @@ -1594,7 +1675,7 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, /* * Work-around for eldk-4.2 which gives this warning if we try to - * case in the unmap_sysmem() call: + * cast in the unmap_sysmem() call: * warning: initialization discards qualifiers from pointer target type */ { @@ -1612,7 +1693,7 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, bootstage_error(bootstage_id + BOOTSTAGE_SUB_LOAD); return -EBADF; } - } else { + } else if (load_op != FIT_LOAD_OPTIONAL_NON_ZERO || load) { ulong image_start, image_end; ulong load_end; void *dst; @@ -1649,3 +1730,23 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, return noffset; } + +int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch, + ulong *setup_start, ulong *setup_len) +{ + int noffset; + ulong addr; + ulong len; + int ret; + + addr = map_to_sysmem(images->fit_hdr_os); + noffset = fit_get_node_from_config(images, FIT_SETUP_PROP, addr); + if (noffset < 0) + return noffset; + + ret = fit_image_load(images, addr, NULL, NULL, arch, + IH_TYPE_X86_SETUP, BOOTSTAGE_ID_FIT_SETUP_START, + FIT_LOAD_REQUIRED, setup_start, &len); + + return ret; +} diff --git a/common/image-sig.c b/common/image-sig.c index 973b06d505..2c9f0cdf7a 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -13,17 +13,80 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ #include -#include +#include +#include #define IMAGE_MAX_HASHED_NODES 100 +#ifdef USE_HOSTCC +void *host_blob; +void image_set_host_blob(void *blob) +{ + host_blob = blob; +} +void *image_get_host_blob(void) +{ + return host_blob; +} +#endif + +struct checksum_algo checksum_algos[] = { + { + "sha1", + SHA1_SUM_LEN, + RSA2048_BYTES, +#if IMAGE_ENABLE_SIGN + EVP_sha1, +#endif + hash_calculate, + padding_sha1_rsa2048, + }, + { + "sha256", + SHA256_SUM_LEN, + RSA2048_BYTES, +#if IMAGE_ENABLE_SIGN + EVP_sha256, +#endif + hash_calculate, + padding_sha256_rsa2048, + }, + { + "sha256", + SHA256_SUM_LEN, + RSA4096_BYTES, +#if IMAGE_ENABLE_SIGN + EVP_sha256, +#endif + hash_calculate, + padding_sha256_rsa4096, + } + +}; + struct image_sig_algo image_sig_algos[] = { { "sha1,rsa2048", rsa_sign, rsa_add_verify_data, rsa_verify, + &checksum_algos[0], + }, + { + "sha256,rsa2048", + rsa_sign, + rsa_add_verify_data, + rsa_verify, + &checksum_algos[1], + }, + { + "sha256,rsa4096", + rsa_sign, + rsa_add_verify_data, + rsa_verify, + &checksum_algos[2], } + }; struct image_sig_algo *image_get_sig_algo(const char *name) @@ -404,6 +467,6 @@ int fit_config_verify_required_sigs(const void *fit, int conf_noffset, int fit_config_verify(const void *fit, int conf_noffset) { - return !fit_config_verify_required_sigs(fit, conf_noffset, - gd_fdt_blob()); + return fit_config_verify_required_sigs(fit, conf_noffset, + gd_fdt_blob()); } diff --git a/common/image.c b/common/image.c index 56a5a626e6..a911aa9b4d 100644 --- a/common/image.c +++ b/common/image.c @@ -34,7 +34,7 @@ #endif #include -#include +#include #include #include @@ -44,8 +44,10 @@ extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, int verify); +#endif #else #include "mkimage.h" #include @@ -81,6 +83,9 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_NDS32, "nds32", "NDS32", }, { IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",}, { IH_ARCH_SANDBOX, "sandbox", "Sandbox", }, + { IH_ARCH_ARM64, "arm64", "AArch64", }, + { IH_ARCH_ARC, "arc", "ARC", }, + { IH_ARCH_X86_64, "x86_64", "AMD x86_64", }, { -1, "", "", }, }; @@ -95,9 +100,9 @@ static const table_entry_t uimage_os[] = { { IH_OS_PLAN9, "plan9", "Plan 9", }, { IH_OS_RTEMS, "rtems", "RTEMS", }, { IH_OS_U_BOOT, "u-boot", "U-Boot", }, + { IH_OS_VXWORKS, "vxworks", "VxWorks", }, #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC) { IH_OS_QNX, "qnx", "QNX", }, - { IH_OS_VXWORKS, "vxworks", "VxWorks", }, #endif #if defined(CONFIG_INTEGRITY) || defined(USE_HOSTCC) { IH_OS_INTEGRITY,"integrity", "INTEGRITY", }, @@ -115,6 +120,10 @@ static const table_entry_t uimage_os[] = { { IH_OS_SOLARIS, "solaris", "Solaris", }, { IH_OS_SVR4, "svr4", "SVR4", }, #endif +#if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC) + { IH_OS_OPENRTOS, "openrtos", "OpenRTOS", }, +#endif + { -1, "", "", }, }; @@ -123,6 +132,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image", }, { IH_TYPE_FIRMWARE, "firmware", "Firmware", }, { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, + { IH_TYPE_GPIMAGE, "gpimage", "TI Keystone SPL Image",}, { IH_TYPE_KERNEL, "kernel", "Kernel Image", }, { IH_TYPE_KERNEL_NOLOAD, "kernel_noload", "Kernel Image (no loading done)", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, @@ -133,8 +143,12 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, + { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",}, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, + { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, + { IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",}, + { IH_TYPE_X86_SETUP, "x86_setup", "x86 setup.bin", }, { -1, "", "", }, }; @@ -325,6 +339,7 @@ void image_print_contents(const void *ptr) #ifndef USE_HOSTCC +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) /** * image_get_ramdisk - get and verify ramdisk image * @rd_addr: ramdisk image start address @@ -386,6 +401,7 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, return rd_hdr; } +#endif #endif /* !USE_HOSTCC */ /*****************************************************************************/ @@ -473,12 +489,22 @@ void memmove_wd(void *to, void *from, size_t len, ulong chunksz) return; #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + if (to > from) { + from += len; + to += len; + } while (len > 0) { size_t tail = (len > chunksz) ? chunksz : len; WATCHDOG_RESET(); + if (to > from) { + to -= tail; + from -= tail; + } memmove(to, from, tail); - to += tail; - from += tail; + if (to < from) { + to += tail; + from += tail; + } len -= tail; } #else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ @@ -633,6 +659,64 @@ int genimg_get_comp_id(const char *name) } #ifndef USE_HOSTCC +/** + * genimg_get_kernel_addr_fit - get the real kernel address and return 2 + * FIT strings + * @img_addr: a string might contain real image address + * @fit_uname_config: double pointer to a char, will hold pointer to a + * configuration unit name + * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage + * name + * + * genimg_get_kernel_addr_fit get the real kernel start address from a string + * which is normally the first argv of bootm/bootz + * + * returns: + * kernel start address + */ +ulong genimg_get_kernel_addr_fit(char * const img_addr, + const char **fit_uname_config, + const char **fit_uname_kernel) +{ + ulong kernel_addr; + + /* find out kernel image address */ + if (!img_addr) { + kernel_addr = load_addr; + debug("* kernel: default image load address = 0x%08lx\n", + load_addr); +#if defined(CONFIG_FIT) + } else if (fit_parse_conf(img_addr, load_addr, &kernel_addr, + fit_uname_config)) { + debug("* kernel: config '%s' from image at 0x%08lx\n", + *fit_uname_config, kernel_addr); + } else if (fit_parse_subimage(img_addr, load_addr, &kernel_addr, + fit_uname_kernel)) { + debug("* kernel: subimage '%s' from image at 0x%08lx\n", + *fit_uname_kernel, kernel_addr); +#endif + } else { + kernel_addr = simple_strtoul(img_addr, NULL, 16); + debug("* kernel: cmdline image address = 0x%08lx\n", + kernel_addr); + } + + return kernel_addr; +} + +/** + * genimg_get_kernel_addr() is the simple version of + * genimg_get_kernel_addr_fit(). It ignores those return FIT strings + */ +ulong genimg_get_kernel_addr(char * const img_addr) +{ + const char *fit_uname_config = NULL; + const char *fit_uname_kernel = NULL; + + return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config, + &fit_uname_kernel); +} + /** * genimg_get_format - get image format type * @img_addr: image start address @@ -649,31 +733,30 @@ int genimg_get_comp_id(const char *name) */ int genimg_get_format(const void *img_addr) { - ulong format = IMAGE_FORMAT_INVALID; +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) const image_header_t *hdr; -#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT) - char *fit_hdr; -#endif hdr = (const image_header_t *)img_addr; if (image_check_magic(hdr)) - format = IMAGE_FORMAT_LEGACY; + return IMAGE_FORMAT_LEGACY; +#endif #if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT) - else { - fit_hdr = (char *)img_addr; - if (fdt_check_header(fit_hdr) == 0) - format = IMAGE_FORMAT_FIT; - } + if (fdt_check_header(img_addr) == 0) + return IMAGE_FORMAT_FIT; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + if (android_image_check_header(img_addr) == 0) + return IMAGE_FORMAT_ANDROID; #endif - return format; + return IMAGE_FORMAT_INVALID; } /** * genimg_get_image - get image from special storage (if necessary) * @img_addr: image start address * - * genimg_get_image() checks if provided image start adddress is located + * genimg_get_image() checks if provided image start address is located * in a dataflash storage. If so, image is moved to a system RAM memory. * * returns: @@ -708,12 +791,14 @@ ulong genimg_get_image(ulong img_addr) /* get data size */ switch (genimg_get_format(buf)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: d_size = image_get_data_size(buf); debug(" Legacy format image found at 0x%08lx, " "size 0x%08lx\n", ram_addr, d_size); break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: d_size = fit_get_size(buf) - h_size; @@ -789,7 +874,9 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, { ulong rd_addr, rd_load; ulong rd_data, rd_len; +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) const image_header_t *rd_hdr; +#endif void *buf; #ifdef CONFIG_SUPPORT_RAW_INITRD char *end; @@ -872,6 +959,7 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, */ buf = map_sysmem(rd_addr, 0); switch (genimg_get_format(buf)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) case IMAGE_FORMAT_LEGACY: printf("## Loading init Ramdisk from Legacy " "Image at %08lx ...\n", rd_addr); @@ -887,14 +975,16 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, rd_len = image_get_data_size(rd_hdr); rd_load = image_get_load(rd_hdr); break; +#endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: - rd_noffset = fit_image_load(images, FIT_RAMDISK_PROP, + rd_noffset = fit_image_load(images, rd_addr, &fit_uname_ramdisk, &fit_uname_config, arch, IH_TYPE_RAMDISK, BOOTSTAGE_ID_FIT_RD_START, - FIT_LOAD_IGNORED, &rd_data, &rd_len); + FIT_LOAD_OPTIONAL_NON_ZERO, + &rd_data, &rd_len); if (rd_noffset < 0) return 1; @@ -933,7 +1023,16 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, (ulong)images->legacy_hdr_os); image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len); - } else { + } +#ifdef CONFIG_ANDROID_BOOT_IMAGE + else if ((genimg_get_format((void *)images->os.start) + == IMAGE_FORMAT_ANDROID) && + (!android_image_get_ramdisk((void *)images->os.start, + &rd_data, &rd_len))) { + /* empty */ + } +#endif + else { /* * no initrd image */ @@ -964,7 +1063,7 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, * @initrd_end: pointer to a ulong variable, will hold final init ramdisk * end address (after possible relocation) * - * boot_ramdisk_high() takes a relocation hint from "initrd_high" environement + * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment * variable and if requested ramdisk data is moved to a specified location. * * Initrd_start and initrd_end are set to final (after relocation) ramdisk @@ -1054,6 +1153,16 @@ error: } #endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */ +int boot_get_setup(bootm_headers_t *images, uint8_t arch, + ulong *setup_start, ulong *setup_len) +{ +#if defined(CONFIG_FIT) + return boot_get_setup_fit(images, arch, setup_start, setup_len); +#else + return -ENOENT; +#endif +} + #ifdef CONFIG_SYS_BOOT_GET_CMDLINE /** * boot_get_cmdline - allocate and initialize kernel cmdline diff --git a/common/iomux.c b/common/iomux.c index cf4da45707..62bdec61aa 100644 --- a/common/iomux.c +++ b/common/iomux.c @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/common/iotrace.c b/common/iotrace.c new file mode 100644 index 0000000000..ced426ea5c --- /dev/null +++ b/common/iotrace.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2014 Google, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define IOTRACE_IMPL + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Support up to the machine word length for now */ +typedef ulong iovalue_t; + +enum iotrace_flags { + IOT_8 = 0, + IOT_16, + IOT_32, + + IOT_READ = 0 << 3, + IOT_WRITE = 1 << 3, +}; + +/** + * struct iotrace_record - Holds a single I/O trace record + * + * @flags: I/O access type + * @addr: Address of access + * @value: Value written or read + */ +struct iotrace_record { + enum iotrace_flags flags; + phys_addr_t addr; + iovalue_t value; +}; + +/** + * struct iotrace - current trace status and checksum + * + * @start: Start address of iotrace buffer + * @size: Size of iotrace buffer in bytes + * @offset: Current write offset into iotrace buffer + * @crc32: Current value of CRC chceksum of trace records + * @enabled: true if enabled, false if disabled + */ +static struct iotrace { + ulong start; + ulong size; + ulong offset; + u32 crc32; + bool enabled; +} iotrace; + +static void add_record(int flags, const void *ptr, ulong value) +{ + struct iotrace_record srec, *rec = &srec; + + /* + * We don't support iotrace before relocation. Since the trace buffer + * is set up by a command, it can't be enabled at present. To change + * this we would need to set the iotrace buffer at build-time. See + * lib/trace.c for how this might be done if you are interested. + */ + if (!(gd->flags & GD_FLG_RELOC) || !iotrace.enabled) + return; + + /* Store it if there is room */ + if (iotrace.offset + sizeof(*rec) < iotrace.size) { + rec = (struct iotrace_record *)map_sysmem( + iotrace.start + iotrace.offset, + sizeof(value)); + } + + rec->flags = flags; + rec->addr = map_to_sysmem(ptr); + rec->value = value; + + /* Update our checksum */ + iotrace.crc32 = crc32(iotrace.crc32, (unsigned char *)rec, + sizeof(*rec)); + + iotrace.offset += sizeof(struct iotrace_record); +} + +u32 iotrace_readl(const void *ptr) +{ + u32 v; + + v = readl(ptr); + add_record(IOT_32 | IOT_READ, ptr, v); + + return v; +} + +void iotrace_writel(ulong value, const void *ptr) +{ + add_record(IOT_32 | IOT_WRITE, ptr, value); + writel(value, ptr); +} + +u16 iotrace_readw(const void *ptr) +{ + u32 v; + + v = readw(ptr); + add_record(IOT_16 | IOT_READ, ptr, v); + + return v; +} + +void iotrace_writew(ulong value, const void *ptr) +{ + add_record(IOT_16 | IOT_WRITE, ptr, value); + writew(value, ptr); +} + +u8 iotrace_readb(const void *ptr) +{ + u32 v; + + v = readb(ptr); + add_record(IOT_8 | IOT_READ, ptr, v); + + return v; +} + +void iotrace_writeb(ulong value, const void *ptr) +{ + add_record(IOT_8 | IOT_WRITE, ptr, value); + writeb(value, ptr); +} + +void iotrace_reset_checksum(void) +{ + iotrace.crc32 = 0; +} + +u32 iotrace_get_checksum(void) +{ + return iotrace.crc32; +} + +void iotrace_set_enabled(int enable) +{ + iotrace.enabled = enable; +} + +int iotrace_get_enabled(void) +{ + return iotrace.enabled; +} + +void iotrace_set_buffer(ulong start, ulong size) +{ + iotrace.start = start; + iotrace.size = size; + iotrace.offset = 0; + iotrace.crc32 = 0; +} + +void iotrace_get_buffer(ulong *start, ulong *size, ulong *offset, ulong *count) +{ + *start = iotrace.start; + *size = iotrace.size; + *offset = iotrace.offset; + *count = iotrace.offset / sizeof(struct iotrace_record); +} diff --git a/common/kgdb.c b/common/kgdb.c index 8a621ad1fc..d357463695 100644 --- a/common/kgdb.c +++ b/common/kgdb.c @@ -103,7 +103,7 @@ static char remcomOutBuffer[BUFMAX]; static char remcomRegBuffer[BUFMAX]; static int initialized = 0; -static int kgdb_active = 0, first_entry = 1; +static int kgdb_active; static struct pt_regs entry_regs; static long error_jmp_buf[BUFMAX/2]; static int longjmp_on_fault = 0; @@ -348,16 +348,7 @@ handle_exception (struct pt_regs *regs) kgdb_enter(regs, &kd); - if (first_entry) { - /* - * the first time we enter kgdb, we save the processor - * state so that we can return to the monitor if the - * remote end quits gdb (or at least, tells us to quit - * with the 'k' packet) - */ - entry_regs = *regs; - first_entry = 0; - } + entry_regs = *regs; ptr = remcomOutBuffer; @@ -459,7 +450,6 @@ handle_exception (struct pt_regs *regs) case 'k': /* kill the program, actually return to monitor */ kd.extype = KGDBEXIT_KILL; *regs = entry_regs; - first_entry = 1; goto doexit; case 'C': /* CSS continue with signal SS */ diff --git a/common/lcd.c b/common/lcd.c index 36a41056f6..41af1b199b 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -4,7 +4,7 @@ * (C) Copyright 2001-2002 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************/ @@ -26,12 +26,14 @@ #endif #include #include - +#include #include +#include +#include +#include #if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ defined(CONFIG_CPU_MONAHANS) -#define CONFIG_CPU_PXA #include #endif @@ -51,7 +53,6 @@ /* ** FONT DATA */ /************************************************************************/ #include /* Get font data, width and height */ -#include /************************************************************************/ /* ** LOGO DATA */ @@ -64,54 +65,25 @@ # endif #endif -#ifndef CONFIG_LCD_ALIGNMENT -#define CONFIG_LCD_ALIGNMENT PAGE_SIZE -#endif - -/* By default we scroll by a single line */ -#ifndef CONFIG_CONSOLE_SCROLL_LINES -#define CONFIG_CONSOLE_SCROLL_LINES 1 +#ifdef CONFIG_SANDBOX +#include #endif -/************************************************************************/ -/* ** CONSOLE DEFINITIONS & FUNCTIONS */ -/************************************************************************/ -#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) -# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \ - / VIDEO_FONT_HEIGHT) -#else -# define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT) +#ifndef CONFIG_LCD_ALIGNMENT +#define CONFIG_LCD_ALIGNMENT PAGE_SIZE #endif -#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) -#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) -#define CONSOLE_ROW_FIRST lcd_console_address -#define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) -#define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ - - CONSOLE_ROW_SIZE) -#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) -#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) - -#if LCD_BPP == LCD_MONOCHROME -# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ - (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) -#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR24) -# define COLOR_MASK(c) (c) -#else +#if (LCD_BPP != LCD_COLOR8) && (LCD_BPP != LCD_COLOR16) && \ + (LCD_BPP != LCD_COLOR32) # error Unsupported LCD BPP. #endif DECLARE_GLOBAL_DATA_PTR; -static void lcd_drawchars(ushort x, ushort y, uchar *str, int count); -static inline void lcd_puts_xy(ushort x, ushort y, uchar *s); -static inline void lcd_putc_xy(ushort x, ushort y, uchar c); - static int lcd_init(void *lcdbase); static void *lcd_logo(void); -static int lcd_getbgcolor(void); static void lcd_setfgcolor(int color); static void lcd_setbgcolor(int color); @@ -121,10 +93,6 @@ int lcd_line_length; char lcd_is_enabled = 0; -static short console_col; -static short console_row; - -static void *lcd_console_address; static void *lcd_base; /* Start of framebuffer memory */ static char lcd_flush_dcache; /* 1 to flush dcache after each lcd update */ @@ -145,6 +113,13 @@ void lcd_sync(void) if (lcd_flush_dcache) flush_dcache_range((u32)lcd_base, (u32)(lcd_base + lcd_get_size(&line_length))); +#elif defined(CONFIG_SANDBOX) && defined(CONFIG_VIDEO_SANDBOX_SDL) + static ulong last_sync; + + if (get_timer(last_sync) > 10) { + sandbox_sdl_sync(lcd_base); + last_sync = get_timer(0); + } #endif } @@ -155,192 +130,14 @@ void lcd_set_flush_dcache(int flush) /*----------------------------------------------------------------------*/ -static void console_scrollup(void) +static void lcd_stub_putc(struct stdio_dev *dev, const char c) { - const int rows = CONFIG_CONSOLE_SCROLL_LINES; - - /* Copy up rows ignoring those that will be overwritten */ - memcpy(CONSOLE_ROW_FIRST, - lcd_console_address + CONSOLE_ROW_SIZE * rows, - CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows); - - /* Clear the last rows */ - memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows, - COLOR_MASK(lcd_color_bg), - CONSOLE_ROW_SIZE * rows); - - lcd_sync(); - console_row -= rows; + lcd_putc(c); } -/*----------------------------------------------------------------------*/ - -static inline void console_back(void) +static void lcd_stub_puts(struct stdio_dev *dev, const char *s) { - if (--console_col < 0) { - console_col = CONSOLE_COLS-1 ; - if (--console_row < 0) - console_row = 0; - } - - lcd_putc_xy(console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, ' '); -} - -/*----------------------------------------------------------------------*/ - -static inline void console_newline(void) -{ - console_col = 0; - - /* Check if we need to scroll the terminal */ - if (++console_row >= CONSOLE_ROWS) - console_scrollup(); - else - lcd_sync(); -} - -/*----------------------------------------------------------------------*/ - -void lcd_putc(const char c) -{ - if (!lcd_is_enabled) { - serial_putc(c); - - return; - } - - switch (c) { - case '\r': - console_col = 0; - - return; - case '\n': - console_newline(); - - return; - case '\t': /* Tab (8 chars alignment) */ - console_col += 8; - console_col &= ~7; - - if (console_col >= CONSOLE_COLS) - console_newline(); - - return; - case '\b': - console_back(); - - return; - default: - lcd_putc_xy(console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, c); - if (++console_col >= CONSOLE_COLS) - console_newline(); - } -} - -/*----------------------------------------------------------------------*/ - -void lcd_puts(const char *s) -{ - if (!lcd_is_enabled) { - serial_puts(s); - - return; - } - - while (*s) - lcd_putc(*s++); - - lcd_sync(); -} - -/*----------------------------------------------------------------------*/ - -void lcd_printf(const char *fmt, ...) -{ - va_list args; - char buf[CONFIG_SYS_PBSIZE]; - - va_start(args, fmt); - vsprintf(buf, fmt, args); - va_end(args); - - lcd_puts(buf); -} - -/************************************************************************/ -/* ** Low-Level Graphics Routines */ -/************************************************************************/ - -static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) -{ - void *dest; - ushort row; - -#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) - y += BMP_LOGO_HEIGHT; -#endif - -#if LCD_BPP == LCD_MONOCHROME - ushort off = x * (1 << LCD_BPP) % 8; -#endif - - dest = lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8; - - for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { - uchar *s = str; - int i; -#if LCD_BPP == LCD_COLOR24 - ulong *d = dest; -#elif LCD_BPP == LCD_COLOR16 - ushort *d = dest; -#else - uchar *d = dest; -#endif - -#if LCD_BPP == LCD_MONOCHROME - uchar rest = *d & -(1 << (8 - off)); - uchar sym; -#endif - for (i = 0; i < count; ++i) { - uchar c, bits; - - c = *s++; - bits = video_fontdata[c * VIDEO_FONT_HEIGHT + row]; - -#if LCD_BPP == LCD_MONOCHROME - sym = (COLOR_MASK(lcd_color_fg) & bits) | - (COLOR_MASK(lcd_color_bg) & ~bits); - - *d++ = rest | (sym >> off); - rest = sym << (8-off); -#else - for (c = 0; c < 8; ++c) { - *d++ = (bits & 0x80) ? - lcd_color_fg : lcd_color_bg; - bits <<= 1; - } -#endif - } -#if LCD_BPP == LCD_MONOCHROME - *d = rest | (*d & ((1 << (8 - off)) - 1)); -#endif - } -} - -/*----------------------------------------------------------------------*/ - -static inline void lcd_puts_xy(ushort x, ushort y, uchar *s) -{ - lcd_drawchars(x, y, s, strlen((char *)s)); -} - -/*----------------------------------------------------------------------*/ - -static inline void lcd_putc_xy(ushort x, ushort y, uchar c) -{ - lcd_drawchars(x, y, &c, 1); + lcd_puts(s); } /************************************************************************/ @@ -360,7 +157,7 @@ static int test_colors[N_BLK_HOR * N_BLK_VERT] = { typedef uchar pix_t; #elif LCD_BPP == LCD_COLOR16 typedef ushort pix_t; -#elif LCD_BPP == LCD_COLOR24 +#elif LCD_BPP == LCD_COLOR32 typedef ulong pix_t; #else #error Unsupported pixelformat @@ -393,8 +190,13 @@ static void test_pattern(void) /************************************************************************/ /* ** GENERIC Initialization Routines */ /************************************************************************/ - -int lcd_get_size(int *line_length) +/* + * With most lcd drivers the line length is set up + * by calculating it from panel_info parameters. Some + * drivers need to calculate the line length differently, + * so make the function weak to allow overriding it. + */ +__weak int lcd_get_size(int *line_length) { *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; return *line_length * panel_info.vl_row; @@ -405,7 +207,7 @@ int drv_lcd_init(void) struct stdio_dev lcddev; int rc; - lcd_base = (void *)gd->fb_base; + lcd_base = map_sysmem(gd->fb_base, 0); lcd_init(lcd_base); /* LCD initialization */ @@ -415,8 +217,8 @@ int drv_lcd_init(void) strcpy(lcddev.name, "lcd"); lcddev.ext = 0; /* No extensions */ lcddev.flags = DEV_FLAGS_OUTPUT; /* Output only */ - lcddev.putc = lcd_putc; /* 'putc' function */ - lcddev.puts = lcd_puts; /* 'puts' function */ + lcddev.putc = lcd_stub_putc; /* 'putc' function */ + lcddev.puts = lcd_stub_puts; /* 'puts' function */ rc = stdio_register(&lcddev); @@ -426,11 +228,9 @@ int drv_lcd_init(void) /*----------------------------------------------------------------------*/ void lcd_clear(void) { -#if LCD_BPP == LCD_MONOCHROME - /* Setting the palette */ - lcd_initcolregs(); - -#elif LCD_BPP == LCD_COLOR8 + short console_rows, console_cols; + int bg_color; +#if LCD_BPP == LCD_COLOR8 /* Setting the palette */ lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0); lcd_setcolreg(CONSOLE_COLOR_RED, 0xFF, 0, 0); @@ -446,25 +246,40 @@ void lcd_clear(void) #ifndef CONFIG_SYS_WHITE_ON_BLACK lcd_setfgcolor(CONSOLE_COLOR_BLACK); lcd_setbgcolor(CONSOLE_COLOR_WHITE); + bg_color = CONSOLE_COLOR_WHITE; #else lcd_setfgcolor(CONSOLE_COLOR_WHITE); lcd_setbgcolor(CONSOLE_COLOR_BLACK); + bg_color = CONSOLE_COLOR_BLACK; #endif /* CONFIG_SYS_WHITE_ON_BLACK */ #ifdef LCD_TEST_PATTERN test_pattern(); #else /* set framebuffer to background color */ - memset((char *)lcd_base, - COLOR_MASK(lcd_getbgcolor()), - lcd_line_length * panel_info.vl_row); +#if (LCD_BPP != LCD_COLOR32) + memset((char *)lcd_base, bg_color, lcd_line_length * panel_info.vl_row); +#else + u32 *ppix = lcd_base; + u32 i; + for (i = 0; + i < (lcd_line_length * panel_info.vl_row)/NBYTES(panel_info.vl_bpix); + i++) { + *ppix++ = bg_color; + } +#endif #endif /* Paint the logo and retrieve LCD base address */ debug("[LCD] Drawing the logo @ %p...\n", lcd_base); - lcd_console_address = lcd_logo(); - - console_col = 0; - console_row = 0; +#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) + console_rows = (panel_info.vl_row - BMP_LOGO_HEIGHT); + console_rows /= VIDEO_FONT_HEIGHT; +#else + console_rows = panel_info.vl_row / VIDEO_FONT_HEIGHT; +#endif + console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH; + lcd_init_console(lcd_base, console_rows, console_cols); + lcd_init_console(lcd_logo(), console_rows, console_cols); lcd_sync(); } @@ -493,28 +308,27 @@ static int lcd_init(void *lcdbase) lcd_ctrl_init(lcdbase); /* - * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi_b) ignores + * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi) ignores * the 'lcdbase' argument and uses custom lcd base address * by setting up gd->fb_base. Check for this condition and fixup * 'lcd_base' address. */ - if ((unsigned long)lcdbase != gd->fb_base) - lcd_base = (void *)gd->fb_base; + if (map_to_sysmem(lcdbase) != gd->fb_base) + lcd_base = map_sysmem(gd->fb_base, 0); debug("[LCD] Using LCD frambuffer at %p\n", lcd_base); lcd_get_size(&lcd_line_length); - lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; lcd_is_enabled = 1; lcd_clear(); lcd_enable(); /* Initialize the console */ - console_col = 0; + lcd_set_col(0); #ifdef CONFIG_LCD_INFO_BELOW_LOGO - console_row = 7 + BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT; + lcd_set_row(7 + BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT); #else - console_row = 1; /* leave 1 blank line below logo */ + lcd_set_row(1); /* leave 1 blank line below logo */ #endif return 0; @@ -561,23 +375,19 @@ static void lcd_setfgcolor(int color) lcd_color_fg = color; } -/*----------------------------------------------------------------------*/ - -static void lcd_setbgcolor(int color) +int lcd_getfgcolor(void) { - lcd_color_bg = color; + return lcd_color_fg; } /*----------------------------------------------------------------------*/ -int lcd_getfgcolor(void) +static void lcd_setbgcolor(int color) { - return lcd_color_fg; + lcd_color_bg = color; } -/*----------------------------------------------------------------------*/ - -static inline int lcd_getbgcolor(void) +int lcd_getbgcolor(void) { return lcd_color_bg; } @@ -663,11 +473,7 @@ void bitmap_plot(int x, int y) *(cmap + BMP_LOGO_OFFSET) = lut_entry; cmap++; #else /* !CONFIG_ATMEL_LCD */ -#ifdef CONFIG_SYS_INVERT_COLORS - *cmap++ = 0xffff - colreg; -#else *cmap++ = colreg; -#endif #endif /* CONFIG_ATMEL_LCD */ } @@ -739,7 +545,7 @@ static void splash_align_axis(int *axis, unsigned long panel_size, else return; - *axis = max(0, axis_alignment); + *axis = max(0, (int)axis_alignment); } #endif @@ -796,9 +602,9 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb, int x, y; int decode = 1; - width = le32_to_cpu(bmp->header.width); - height = le32_to_cpu(bmp->header.height); - bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset); + width = get_unaligned_le32(&bmp->header.width); + height = get_unaligned_le32(&bmp->header.height); + bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset); x = 0; y = height - 1; @@ -874,7 +680,7 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb, } #endif -#if defined(CONFIG_MPC823) || defined(CONFIG_MCC200) +#if defined(CONFIG_MPC823) #define FB_PUT_BYTE(fb, from) *(fb)++ = (255 - *(from)++) #else #define FB_PUT_BYTE(fb, from) *(fb)++ = *(from)++ @@ -905,13 +711,11 @@ static inline bmp_color_table_entry_t *get_color_table(bmp_image_t *bmp) int lcd_display_bitmap(ulong bmp_image, int x, int y) { -#if !defined(CONFIG_MCC200) ushort *cmap = NULL; -#endif ushort *cmap_base = NULL; ushort i, j; uchar *fb; - bmp_image_t *bmp=(bmp_image_t *)bmp_image; + bmp_image_t *bmp = (bmp_image_t *)map_sysmem(bmp_image, 0); uchar *bmap; ushort padded_width; unsigned long width, height; @@ -927,10 +731,11 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) return 1; } - width = le32_to_cpu(bmp->header.width); - height = le32_to_cpu(bmp->header.height); - bmp_bpix = le16_to_cpu(bmp->header.bit_count); - colors = 1ULL << bmp_bpix; + width = get_unaligned_le32(&bmp->header.width); + height = get_unaligned_le32(&bmp->header.height); + bmp_bpix = get_unaligned_le16(&bmp->header.bit_count); + + colors = 1 << bmp_bpix; bpix = NBITS(panel_info.vl_bpix); @@ -941,12 +746,15 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) return 1; } - /* We support displaying 8bpp BMPs on 16bpp or 32bpp LCDs */ - if (bpix != bmp_bpix && (bmp_bpix != 8 || (bpix != 16 && bpix != 32))) { + /* + * We support displaying 8bpp BMPs on 16bpp LCDs + * and displaying 24bpp BMPs on 32bpp LCDs + * */ + if (bpix != bmp_bpix && + !(bmp_bpix == 8 && bpix == 16) && + !(bmp_bpix == 24 && bpix == 32)) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", - bpix, - le16_to_cpu(bmp->header.bit_count)); - + bpix, get_unaligned_le16(&bmp->header.bit_count)); return 1; } @@ -954,8 +762,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) width, height, colors); cte = get_color_table(bmp); -#if !defined(CONFIG_MCC200) - /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ if (bmp_bpix == 8) { cmap = configuration_get_cmap(); cmap_base = cmap; @@ -967,11 +773,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) ( ((cte[i].red) << 8) & 0xf800) | ( ((cte[i].green) << 3) & 0x07e0) | ( ((cte[i].blue) >> 3) & 0x001f) ; -#ifdef CONFIG_SYS_INVERT_COLORS - *cmap = 0xffff - colreg; -#else *cmap = colreg; -#endif #if defined(CONFIG_MPC823) cmap--; #else @@ -982,25 +784,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) #endif } } -#endif - - /* - * BMP format for Monochrome assumes that the state of a - * pixel is described on a per Bit basis, not per Byte. - * So, in case of Monochrome BMP we should align widths - * on a byte boundary and convert them from Bit to Byte - * units. - * Probably, PXA250 and MPC823 process 1bpp BMP images in - * their own ways, so make the converting to be MCC200 - * specific. - */ -#if defined(CONFIG_MCC200) - if (bpix == 1) { - width = ALIGN(width, 8) >> 3; - x = ALIGN(x, 8) >> 3; - pwidth= ALIGN(pwidth, 8) >> 3; - } -#endif padded_width = ALIGN(width, 4); @@ -1008,7 +791,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) splash_align_axis(&x, pwidth, width); splash_align_axis(&y, panel_info.vl_row, height); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ - bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset); + bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset); if ((x + width) > pwidth) width = pwidth - x; @@ -1022,9 +805,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) switch (bmp_bpix) { case 1: /* pass through */ - case 8: + case 8: { #ifdef CONFIG_LCD_BMP_RLE8 - if (le32_to_cpu(bmp->header.compression) == BMP_BI_RLE8) { + u32 compression = get_unaligned_le32(&bmp->header.compression); + if (compression == BMP_BI_RLE8) { if (bpix != 16) { /* TODO implement render code for bpix != 16 */ printf("Error: only support 16 bpix"); @@ -1062,7 +846,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } } break; - + } #if defined(CONFIG_BMP_16BPP) case 16: for (i = 0; i < height; ++i) { @@ -1075,6 +859,20 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } break; #endif /* CONFIG_BMP_16BPP */ +#if defined(CONFIG_BMP_24BMP) + case 24: + for (i = 0; i < height; ++i) { + for (j = 0; j < width; j++) { + *(fb++) = *(bmap++); + *(fb++) = *(bmap++); + *(fb++) = *(bmap++); + *(fb++) = 0; + } + fb -= lcd_line_length + width * (bpix / 8); + } + break; +#endif /* CONFIG_BMP_24BPP */ +#if defined(CONFIG_BMP_32BPP) case 32: for (i = 0; i < height; ++i) { WATCHDOG_RESET(); @@ -1089,6 +887,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) fb -= lcd_line_length + width * (bpix / 8); } break; +#endif /* CONFIG_BMP_32BPP */ }; return 0; @@ -1125,8 +924,8 @@ static void *lcd_logo(void) bitmap_plot(0, 0); #ifdef CONFIG_LCD_INFO - console_col = LCD_INFO_X / VIDEO_FONT_WIDTH; - console_row = LCD_INFO_Y / VIDEO_FONT_HEIGHT; + lcd_set_col(LCD_INFO_X / VIDEO_FONT_WIDTH); + lcd_set_row(LCD_INFO_Y / VIDEO_FONT_HEIGHT); lcd_show_board_info(); #endif /* CONFIG_LCD_INFO */ @@ -1161,12 +960,6 @@ static int on_splashimage(const char *name, const char *value, enum env_op op, U_BOOT_ENV_CALLBACK(splashimage, on_splashimage); #endif -void lcd_position_cursor(unsigned col, unsigned row) -{ - console_col = min(col, CONSOLE_COLS - 1); - console_row = min(row, CONSOLE_ROWS - 1); -} - int lcd_get_pixel_width(void) { return panel_info.vl_col; @@ -1177,64 +970,16 @@ int lcd_get_pixel_height(void) return panel_info.vl_row; } -int lcd_get_screen_rows(void) -{ - return CONSOLE_ROWS; -} - -int lcd_get_screen_columns(void) -{ - return CONSOLE_COLS; -} - #if defined(CONFIG_LCD_DT_SIMPLEFB) static int lcd_dt_simplefb_configure_node(void *blob, int off) { - u32 stride; - fdt32_t cells[2]; - int ret; - static const char format[] = #if LCD_BPP == LCD_COLOR16 - "r5g6b5"; + return fdt_setup_simplefb_node(blob, off, gd->fb_base, + panel_info.vl_col, panel_info.vl_row, + panel_info.vl_col * 2, "r5g6b5"); #else - ""; + return -1; #endif - - if (!format[0]) - return -1; - - stride = panel_info.vl_col * 2; - - cells[0] = cpu_to_fdt32(gd->fb_base); - cells[1] = cpu_to_fdt32(stride * panel_info.vl_row); - ret = fdt_setprop(blob, off, "reg", cells, sizeof(cells[0]) * 2); - if (ret < 0) - return -1; - - cells[0] = cpu_to_fdt32(panel_info.vl_col); - ret = fdt_setprop(blob, off, "width", cells, sizeof(cells[0])); - if (ret < 0) - return -1; - - cells[0] = cpu_to_fdt32(panel_info.vl_row); - ret = fdt_setprop(blob, off, "height", cells, sizeof(cells[0])); - if (ret < 0) - return -1; - - cells[0] = cpu_to_fdt32(stride); - ret = fdt_setprop(blob, off, "stride", cells, sizeof(cells[0])); - if (ret < 0) - return -1; - - ret = fdt_setprop(blob, off, "format", format, strlen(format) + 1); - if (ret < 0) - return -1; - - ret = fdt_delprop(blob, off, "status"); - if (ret < 0) - return -1; - - return 0; } int lcd_dt_simplefb_add_node(void *blob) diff --git a/common/lcd_console.c b/common/lcd_console.c new file mode 100644 index 0000000000..74c388a0ca --- /dev/null +++ b/common/lcd_console.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2001-2014 + * DENX Software Engineering -- wd@denx.de + * Compulab Ltd - http://compulab.co.il/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include /* Get font data, width and height */ + +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) +#define CONSOLE_ROW_FIRST lcd_console_address +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * console_rows) + +static short console_curr_col; +static short console_curr_row; +static short console_cols; +static short console_rows; +static void *lcd_console_address; + +void lcd_init_console(void *address, int rows, int cols) +{ + console_curr_col = 0; + console_curr_row = 0; + console_cols = cols; + console_rows = rows; + lcd_console_address = address; +} + +void lcd_set_col(short col) +{ + console_curr_col = col; +} + +void lcd_set_row(short row) +{ + console_curr_row = row; +} + +void lcd_position_cursor(unsigned col, unsigned row) +{ + console_curr_col = min_t(short, col, console_cols - 1); + console_curr_row = min_t(short, row, console_rows - 1); +} + +int lcd_get_screen_rows(void) +{ + return console_rows; +} + +int lcd_get_screen_columns(void) +{ + return console_cols; +} + +static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) +{ + uchar *dest; + ushort row; + int fg_color, bg_color; + + dest = (uchar *)(lcd_console_address + + y * lcd_line_length + x * NBITS(LCD_BPP) / 8); + + for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { + uchar *s = str; + int i; +#if LCD_BPP == LCD_COLOR16 + ushort *d = (ushort *)dest; +#elif LCD_BPP == LCD_COLOR32 + u32 *d = (u32 *)dest; +#else + uchar *d = dest; +#endif + + fg_color = lcd_getfgcolor(); + bg_color = lcd_getbgcolor(); + for (i = 0; i < count; ++i) { + uchar c, bits; + + c = *s++; + bits = video_fontdata[c * VIDEO_FONT_HEIGHT + row]; + + for (c = 0; c < 8; ++c) { + *d++ = (bits & 0x80) ? fg_color : bg_color; + bits <<= 1; + } + } + } +} + +static inline void lcd_putc_xy(ushort x, ushort y, uchar c) +{ + lcd_drawchars(x, y, &c, 1); +} + +static void console_scrollup(void) +{ + const int rows = CONFIG_CONSOLE_SCROLL_LINES; + int bg_color = lcd_getbgcolor(); + + /* Copy up rows ignoring those that will be overwritten */ + memcpy(CONSOLE_ROW_FIRST, + lcd_console_address + CONSOLE_ROW_SIZE * rows, + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows); + + /* Clear the last rows */ +#if (LCD_BPP != LCD_COLOR32) + memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows, + bg_color, CONSOLE_ROW_SIZE * rows); +#else + u32 *ppix = lcd_console_address + + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows; + u32 i; + for (i = 0; + i < (CONSOLE_ROW_SIZE * rows) / NBYTES(panel_info.vl_bpix); + i++) { + *ppix++ = bg_color; + } +#endif + lcd_sync(); + console_curr_row -= rows; +} + +static inline void console_back(void) +{ + if (--console_curr_col < 0) { + console_curr_col = console_cols - 1; + if (--console_curr_row < 0) + console_curr_row = 0; + } + + lcd_putc_xy(console_curr_col * VIDEO_FONT_WIDTH, + console_curr_row * VIDEO_FONT_HEIGHT, ' '); +} + +static inline void console_newline(void) +{ + console_curr_col = 0; + + /* Check if we need to scroll the terminal */ + if (++console_curr_row >= console_rows) + console_scrollup(); + else + lcd_sync(); +} + +void lcd_putc(const char c) +{ + if (!lcd_is_enabled) { + serial_putc(c); + + return; + } + + switch (c) { + case '\r': + console_curr_col = 0; + + return; + case '\n': + console_newline(); + + return; + case '\t': /* Tab (8 chars alignment) */ + console_curr_col += 8; + console_curr_col &= ~7; + + if (console_curr_col >= console_cols) + console_newline(); + + return; + case '\b': + console_back(); + + return; + default: + lcd_putc_xy(console_curr_col * VIDEO_FONT_WIDTH, + console_curr_row * VIDEO_FONT_HEIGHT, c); + if (++console_curr_col >= console_cols) + console_newline(); + } +} + +void lcd_puts(const char *s) +{ + if (!lcd_is_enabled) { + serial_puts(s); + + return; + } + + while (*s) + lcd_putc(*s++); + + lcd_sync(); +} + +void lcd_printf(const char *fmt, ...) +{ + va_list args; + char buf[CONFIG_SYS_PBSIZE]; + + va_start(args, fmt); + vsprintf(buf, fmt, args); + va_end(args); + + lcd_puts(buf); +} diff --git a/common/main.c b/common/main.c index dd2b095e6b..2979fbed63 100644 --- a/common/main.c +++ b/common/main.c @@ -2,457 +2,41 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Add to readline cmdline-editing by - * (C) Copyright 2005 - * JinHua Luo, GuangDong Linux Center, - * * SPDX-License-Identifier: GPL-2.0+ */ /* #define DEBUG */ #include -#include -#include -#include -#include -#include -#include +#include +#include #include -#include -#include DECLARE_GLOBAL_DATA_PTR; /* * Board-specific Platform code can reimplement show_boot_progress () if needed */ -void inline __show_boot_progress (int val) {} -void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); - -#define MAX_DELAY_STOP_STR 32 - -#define DEBUG_PARSER 0 /* set to 1 to debug */ - -#define debug_parser(fmt, args...) \ - debug_cond(DEBUG_PARSER, fmt, ##args) - -#ifndef DEBUG_BOOTKEYS -#define DEBUG_BOOTKEYS 0 -#endif -#define debug_bootkeys(fmt, args...) \ - debug_cond(DEBUG_BOOTKEYS, fmt, ##args) - -char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */ - -static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); -static const char erase_seq[] = "\b \b"; /* erase sequence */ -static const char tab_seq[] = " "; /* used to expand TABs */ - -#ifdef CONFIG_BOOT_RETRY_TIME -static uint64_t endtime = 0; /* must be set, default is instant timeout */ -static int retry_time = -1; /* -1 so can call readline before main_loop */ -#endif - -#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk()) - -#ifndef CONFIG_BOOT_RETRY_MIN -#define CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME -#endif - -#ifdef CONFIG_MODEM_SUPPORT -int do_mdm_init = 0; -extern void mdm_init(void); /* defined in board.c */ -#endif +__weak void show_boot_progress(int val) {} -/*************************************************************************** - * Watch for 'delay' seconds for autoboot stop or autoboot delay string. - * returns: 0 - no key string, allow autoboot 1 - got key string, abort - */ -#if defined(CONFIG_BOOTDELAY) -# if defined(CONFIG_AUTOBOOT_KEYED) -static int abortboot_keyed(int bootdelay) +static void modem_init(void) { - int abort = 0; - uint64_t etime = endtick(bootdelay); - struct { - char* str; - u_int len; - int retry; - } - delaykey [] = { - { str: getenv ("bootdelaykey"), retry: 1 }, - { str: getenv ("bootdelaykey2"), retry: 1 }, - { str: getenv ("bootstopkey"), retry: 0 }, - { str: getenv ("bootstopkey2"), retry: 0 }, - }; - - char presskey [MAX_DELAY_STOP_STR]; - u_int presskey_len = 0; - u_int presskey_max = 0; - u_int i; - -#ifndef CONFIG_ZERO_BOOTDELAY_CHECK - if (bootdelay == 0) - return 0; -#endif - -# ifdef CONFIG_AUTOBOOT_PROMPT - printf(CONFIG_AUTOBOOT_PROMPT); -# endif - -# ifdef CONFIG_AUTOBOOT_DELAY_STR - if (delaykey[0].str == NULL) - delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR; -# endif -# ifdef CONFIG_AUTOBOOT_DELAY_STR2 - if (delaykey[1].str == NULL) - delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2; -# endif -# ifdef CONFIG_AUTOBOOT_STOP_STR - if (delaykey[2].str == NULL) - delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR; -# endif -# ifdef CONFIG_AUTOBOOT_STOP_STR2 - if (delaykey[3].str == NULL) - delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2; -# endif - - for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) { - delaykey[i].len = delaykey[i].str == NULL ? - 0 : strlen (delaykey[i].str); - delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ? - MAX_DELAY_STOP_STR : delaykey[i].len; - - presskey_max = presskey_max > delaykey[i].len ? - presskey_max : delaykey[i].len; - - debug_bootkeys("%s key:<%s>\n", - delaykey[i].retry ? "delay" : "stop", - delaykey[i].str ? delaykey[i].str : "NULL"); - } - - /* In order to keep up with incoming data, check timeout only - * when catch up. - */ - do { - if (tstc()) { - if (presskey_len < presskey_max) { - presskey [presskey_len ++] = getc(); - } - else { - for (i = 0; i < presskey_max - 1; i ++) - presskey [i] = presskey [i + 1]; - - presskey [i] = getc(); - } - } - - for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) { - if (delaykey[i].len > 0 && - presskey_len >= delaykey[i].len && - memcmp (presskey + presskey_len - delaykey[i].len, - delaykey[i].str, - delaykey[i].len) == 0) { - debug_bootkeys("got %skey\n", - delaykey[i].retry ? "delay" : - "stop"); - -# ifdef CONFIG_BOOT_RETRY_TIME - /* don't retry auto boot */ - if (! delaykey[i].retry) - retry_time = -1; -# endif - abort = 1; - } - } - } while (!abort && get_ticks() <= etime); - - if (!abort) - debug_bootkeys("key timeout\n"); - -#ifdef CONFIG_SILENT_CONSOLE - if (abort) - gd->flags &= ~GD_FLG_SILENT; -#endif - - return abort; -} - -# else /* !defined(CONFIG_AUTOBOOT_KEYED) */ - -#ifdef CONFIG_MENUKEY -static int menukey = 0; -#endif - -static int abortboot_normal(int bootdelay) -{ - int abort = 0; - unsigned long ts; - -#ifdef CONFIG_MENUPROMPT - printf(CONFIG_MENUPROMPT); -#else - if (bootdelay >= 0) - printf("Hit any key to stop autoboot: %2d ", bootdelay); -#endif - -#if defined CONFIG_ZERO_BOOTDELAY_CHECK - /* - * Check if key already pressed - * Don't check if bootdelay < 0 - */ - if (bootdelay >= 0) { - if (tstc()) { /* we got a key press */ - (void) getc(); /* consume input */ - puts ("\b\b\b 0"); - abort = 1; /* don't auto boot */ - } - } -#endif - - while ((bootdelay > 0) && (!abort)) { - --bootdelay; - /* delay 1000 ms */ - ts = get_timer(0); - do { - if (tstc()) { /* we got a key press */ - abort = 1; /* don't auto boot */ - bootdelay = 0; /* no more delay */ -# ifdef CONFIG_MENUKEY - menukey = getc(); -# else - (void) getc(); /* consume input */ -# endif - break; - } - udelay(10000); - } while (!abort && get_timer(ts) < 1000); - - printf("\b\b\b%2d ", bootdelay); - } - - putc('\n'); - -#ifdef CONFIG_SILENT_CONSOLE - if (abort) - gd->flags &= ~GD_FLG_SILENT; -#endif - - return abort; -} -# endif /* CONFIG_AUTOBOOT_KEYED */ - -static int abortboot(int bootdelay) -{ -#ifdef CONFIG_AUTOBOOT_KEYED - return abortboot_keyed(bootdelay); -#else - return abortboot_normal(bootdelay); -#endif -} -#endif /* CONFIG_BOOTDELAY */ - -/* - * Runs the given boot command securely. Specifically: - * - Doesn't run the command with the shell (run_command or parse_string_outer), - * since that's a lot of code surface that an attacker might exploit. - * Because of this, we don't do any argument parsing--the secure boot command - * has to be a full-fledged u-boot command. - * - Doesn't check for keypresses before booting, since that could be a - * security hole; also disables Ctrl-C. - * - Doesn't allow the command to return. - * - * Upon any failures, this function will drop into an infinite loop after - * printing the error message to console. - */ - -#if defined(CONFIG_BOOTDELAY) && defined(CONFIG_OF_CONTROL) -static void secure_boot_cmd(char *cmd) -{ - cmd_tbl_t *cmdtp; - int rc; - - if (!cmd) { - printf("## Error: Secure boot command not specified\n"); - goto err; - } - - /* Disable Ctrl-C just in case some command is used that checks it. */ - disable_ctrlc(1); - - /* Find the command directly. */ - cmdtp = find_cmd(cmd); - if (!cmdtp) { - printf("## Error: \"%s\" not defined\n", cmd); - goto err; - } - - /* Run the command, forcing no flags and faking argc and argv. */ - rc = (cmdtp->cmd)(cmdtp, 0, 1, &cmd); - - /* Shouldn't ever return from boot command. */ - printf("## Error: \"%s\" returned (code %d)\n", cmd, rc); - -err: - /* - * Not a whole lot to do here. Rebooting won't help much, since we'll - * just end up right back here. Just loop. - */ - hang(); -} - -static void process_fdt_options(const void *blob) -{ - ulong addr; - - /* Add an env variable to point to a kernel payload, if available */ - addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0); - if (addr) - setenv_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); - - /* Add an env variable to point to a root disk, if available */ - addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0); - if (addr) - setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); -} -#endif /* CONFIG_OF_CONTROL */ - -#ifdef CONFIG_BOOTDELAY -static void process_boot_delay(void) -{ -#ifdef CONFIG_OF_CONTROL - char *env; -#endif - char *s; - int bootdelay; -#ifdef CONFIG_BOOTCOUNT_LIMIT - unsigned long bootcount = 0; - unsigned long bootlimit = 0; -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - bootcount = bootcount_load(); - bootcount++; - bootcount_store (bootcount); - setenv_ulong("bootcount", bootcount); - bootlimit = getenv_ulong("bootlimit", 10, 0); -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - - s = getenv ("bootdelay"); - bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; - -#ifdef CONFIG_OF_CONTROL - bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", - bootdelay); -#endif - - debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay); - -#if defined(CONFIG_MENU_SHOW) - bootdelay = menu_show(bootdelay); -#endif -# ifdef CONFIG_BOOT_RETRY_TIME - init_cmd_timeout (); -# endif /* CONFIG_BOOT_RETRY_TIME */ - -#ifdef CONFIG_POST - if (gd->flags & GD_FLG_POSTFAIL) { - s = getenv("failbootcmd"); - } - else -#endif /* CONFIG_POST */ -#ifdef CONFIG_BOOTCOUNT_LIMIT - if (bootlimit && (bootcount > bootlimit)) { - printf ("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n", - (unsigned)bootlimit); - s = getenv ("altbootcmd"); - } - else -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - s = getenv ("bootcmd"); -#ifdef CONFIG_OF_CONTROL - /* Allow the fdt to override the boot command */ - env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd"); - if (env) - s = env; - - process_fdt_options(gd->fdt_blob); - - /* - * If the bootsecure option was chosen, use secure_boot_cmd(). - * Always use 'env' in this case, since bootsecure requres that the - * bootcmd was specified in the FDT too. - */ - if (fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0)) - secure_boot_cmd(env); - -#endif /* CONFIG_OF_CONTROL */ - - debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : ""); - - if (bootdelay != -1 && s && !abortboot(bootdelay)) { -#ifdef CONFIG_AUTOBOOT_KEYED - int prev = disable_ctrlc(1); /* disable Control C checking */ -#endif - - run_command_list(s, -1, 0); - -#ifdef CONFIG_AUTOBOOT_KEYED - disable_ctrlc(prev); /* restore Control C checking */ -#endif - } +#ifdef CONFIG_MODEM_SUPPORT + debug("DEBUG: main_loop: gd->do_mdm_init=%lu\n", gd->do_mdm_init); + if (gd->do_mdm_init) { + char *str = getenv("mdm_cmd"); -#ifdef CONFIG_MENUKEY - if (menukey == CONFIG_MENUKEY) { - s = getenv("menucmd"); - if (s) - run_command_list(s, -1, 0); + setenv("preboot", str); /* set or delete definition */ + mdm_init(); /* wait for modem connection */ } -#endif /* CONFIG_MENUKEY */ +#endif /* CONFIG_MODEM_SUPPORT */ } -#endif /* CONFIG_BOOTDELAY */ -void main_loop(void) +static void run_preboot_environment_command(void) { -#ifndef CONFIG_SYS_HUSH_PARSER - static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, }; - int len; - int rc = 1; - int flag; -#endif #ifdef CONFIG_PREBOOT char *p; -#endif - bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); - -#ifdef CONFIG_MODEM_SUPPORT - debug("DEBUG: main_loop: do_mdm_init=%d\n", do_mdm_init); - if (do_mdm_init) { - char *str = strdup(getenv("mdm_cmd")); - setenv("preboot", str); /* set or delete definition */ - if (str != NULL) - free(str); - mdm_init(); /* wait for modem connection */ - } -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CONFIG_VERSION_VARIABLE - { - setenv("ver", version_string); /* set version variable */ - } -#endif /* CONFIG_VERSION_VARIABLE */ - -#ifdef CONFIG_SYS_HUSH_PARSER - u_boot_hush_start(); -#endif - -#if defined(CONFIG_HUSH_INIT_VAR) - hush_init_var(); -#endif - -#ifdef CONFIG_PREBOOT p = getenv("preboot"); if (p != NULL) { # ifdef CONFIG_AUTOBOOT_KEYED @@ -466,1094 +50,39 @@ void main_loop(void) # endif } #endif /* CONFIG_PREBOOT */ - -#if defined(CONFIG_UPDATE_TFTP) - update_tftp(0UL); -#endif /* CONFIG_UPDATE_TFTP */ - -#ifdef CONFIG_BOOTDELAY - process_boot_delay(); -#endif - /* - * Main Loop for Monitor Command Processing - */ -#ifdef CONFIG_SYS_HUSH_PARSER - parse_file_outer(); - /* This point is never reached */ - for (;;); -#else - for (;;) { -#ifdef CONFIG_BOOT_RETRY_TIME - if (rc >= 0) { - /* Saw enough of a valid command to - * restart the timeout. - */ - reset_cmd_timeout(); - } -#endif - len = readline (CONFIG_SYS_PROMPT); - - flag = 0; /* assume no special flags for now */ - if (len > 0) - strcpy (lastcommand, console_buffer); - else if (len == 0) - flag |= CMD_FLAG_REPEAT; -#ifdef CONFIG_BOOT_RETRY_TIME - else if (len == -2) { - /* -2 means timed out, retry autoboot - */ - puts ("\nTimed out waiting for command\n"); -# ifdef CONFIG_RESET_TO_RETRY - /* Reinit board to run initialization code again */ - do_reset (NULL, 0, 0, NULL); -# else - return; /* retry autoboot */ -# endif - } -#endif - - if (len == -1) - puts ("\n"); - else - rc = run_command(lastcommand, flag); - - if (rc || len < 0) { - /* invalid command or not repeatable, forget it */ - lastcommand[0] = '\0'; - } - } -#endif /*CONFIG_SYS_HUSH_PARSER*/ -} - -#ifdef CONFIG_BOOT_RETRY_TIME -/*************************************************************************** - * initialize command line timeout - */ -void init_cmd_timeout(void) -{ - char *s = getenv ("bootretry"); - - if (s != NULL) - retry_time = (int)simple_strtol(s, NULL, 10); - else - retry_time = CONFIG_BOOT_RETRY_TIME; - - if (retry_time >= 0 && retry_time < CONFIG_BOOT_RETRY_MIN) - retry_time = CONFIG_BOOT_RETRY_MIN; -} - -/*************************************************************************** - * reset command line timeout to retry_time seconds - */ -void reset_cmd_timeout(void) -{ - endtime = endtick(retry_time); -} -#endif - -#ifdef CONFIG_CMDLINE_EDITING - -/* - * cmdline-editing related codes from vivi. - * Author: Janghoon Lyu - */ - -#define putnstr(str,n) do { \ - printf ("%.*s", (int)n, str); \ - } while (0) - -#define CTL_CH(c) ((c) - 'a' + 1) -#define CTL_BACKSPACE ('\b') -#define DEL ((char)255) -#define DEL7 ((char)127) -#define CREAD_HIST_CHAR ('!') - -#define getcmd_putch(ch) putc(ch) -#define getcmd_getch() getc() -#define getcmd_cbeep() getcmd_putch('\a') - -#define HIST_MAX 20 -#define HIST_SIZE CONFIG_SYS_CBSIZE - -static int hist_max; -static int hist_add_idx; -static int hist_cur = -1; -static unsigned hist_num; - -static char *hist_list[HIST_MAX]; -static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */ - -#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1) - -static void hist_init(void) -{ - int i; - - hist_max = 0; - hist_add_idx = 0; - hist_cur = -1; - hist_num = 0; - - for (i = 0; i < HIST_MAX; i++) { - hist_list[i] = hist_lines[i]; - hist_list[i][0] = '\0'; - } -} - -static void cread_add_to_hist(char *line) -{ - strcpy(hist_list[hist_add_idx], line); - - if (++hist_add_idx >= HIST_MAX) - hist_add_idx = 0; - - if (hist_add_idx > hist_max) - hist_max = hist_add_idx; - - hist_num++; } -static char* hist_prev(void) -{ - char *ret; - int old_cur; - - if (hist_cur < 0) - return NULL; - - old_cur = hist_cur; - if (--hist_cur < 0) - hist_cur = hist_max; - - if (hist_cur == hist_add_idx) { - hist_cur = old_cur; - ret = NULL; - } else - ret = hist_list[hist_cur]; - - return (ret); -} - -static char* hist_next(void) -{ - char *ret; - - if (hist_cur < 0) - return NULL; - - if (hist_cur == hist_add_idx) - return NULL; - - if (++hist_cur > hist_max) - hist_cur = 0; - - if (hist_cur == hist_add_idx) { - ret = ""; - } else - ret = hist_list[hist_cur]; - - return (ret); -} - -#ifndef CONFIG_CMDLINE_EDITING -static void cread_print_hist_list(void) -{ - int i; - unsigned long n; - - n = hist_num - hist_max; - - i = hist_add_idx + 1; - while (1) { - if (i > hist_max) - i = 0; - if (i == hist_add_idx) - break; - printf("%s\n", hist_list[i]); - n++; - i++; - } -} -#endif /* CONFIG_CMDLINE_EDITING */ - -#define BEGINNING_OF_LINE() { \ - while (num) { \ - getcmd_putch(CTL_BACKSPACE); \ - num--; \ - } \ -} - -#define ERASE_TO_EOL() { \ - if (num < eol_num) { \ - printf("%*s", (int)(eol_num - num), ""); \ - do { \ - getcmd_putch(CTL_BACKSPACE); \ - } while (--eol_num > num); \ - } \ -} - -#define REFRESH_TO_EOL() { \ - if (num < eol_num) { \ - wlen = eol_num - num; \ - putnstr(buf + num, wlen); \ - num = eol_num; \ - } \ -} - -static void cread_add_char(char ichar, int insert, unsigned long *num, - unsigned long *eol_num, char *buf, unsigned long len) -{ - unsigned long wlen; - - /* room ??? */ - if (insert || *num == *eol_num) { - if (*eol_num > len - 1) { - getcmd_cbeep(); - return; - } - (*eol_num)++; - } - - if (insert) { - wlen = *eol_num - *num; - if (wlen > 1) { - memmove(&buf[*num+1], &buf[*num], wlen-1); - } - - buf[*num] = ichar; - putnstr(buf + *num, wlen); - (*num)++; - while (--wlen) { - getcmd_putch(CTL_BACKSPACE); - } - } else { - /* echo the character */ - wlen = 1; - buf[*num] = ichar; - putnstr(buf + *num, wlen); - (*num)++; - } -} - -static void cread_add_str(char *str, int strsize, int insert, unsigned long *num, - unsigned long *eol_num, char *buf, unsigned long len) -{ - while (strsize--) { - cread_add_char(*str, insert, num, eol_num, buf, len); - str++; - } -} - -static int cread_line(const char *const prompt, char *buf, unsigned int *len, - int timeout) -{ - unsigned long num = 0; - unsigned long eol_num = 0; - unsigned long wlen; - char ichar; - int insert = 1; - int esc_len = 0; - char esc_save[8]; - int init_len = strlen(buf); - int first = 1; - - if (init_len) - cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len); - - while (1) { -#ifdef CONFIG_BOOT_RETRY_TIME - while (!tstc()) { /* while no incoming data */ - if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ - WATCHDOG_RESET(); - } -#endif - if (first && timeout) { - uint64_t etime = endtick(timeout); - - while (!tstc()) { /* while no incoming data */ - if (get_ticks() >= etime) - return -2; /* timed out */ - WATCHDOG_RESET(); - } - first = 0; - } - - ichar = getcmd_getch(); - - if ((ichar == '\n') || (ichar == '\r')) { - putc('\n'); - break; - } - - /* - * handle standard linux xterm esc sequences for arrow key, etc. - */ - if (esc_len != 0) { - if (esc_len == 1) { - if (ichar == '[') { - esc_save[esc_len] = ichar; - esc_len = 2; - } else { - cread_add_str(esc_save, esc_len, insert, - &num, &eol_num, buf, *len); - esc_len = 0; - } - continue; - } - - switch (ichar) { - - case 'D': /* <- key */ - ichar = CTL_CH('b'); - esc_len = 0; - break; - case 'C': /* -> key */ - ichar = CTL_CH('f'); - esc_len = 0; - break; /* pass off to ^F handler */ - case 'H': /* Home key */ - ichar = CTL_CH('a'); - esc_len = 0; - break; /* pass off to ^A handler */ - case 'A': /* up arrow */ - ichar = CTL_CH('p'); - esc_len = 0; - break; /* pass off to ^P handler */ - case 'B': /* down arrow */ - ichar = CTL_CH('n'); - esc_len = 0; - break; /* pass off to ^N handler */ - default: - esc_save[esc_len++] = ichar; - cread_add_str(esc_save, esc_len, insert, - &num, &eol_num, buf, *len); - esc_len = 0; - continue; - } - } - - switch (ichar) { - case 0x1b: - if (esc_len == 0) { - esc_save[esc_len] = ichar; - esc_len = 1; - } else { - puts("impossible condition #876\n"); - esc_len = 0; - } - break; - - case CTL_CH('a'): - BEGINNING_OF_LINE(); - break; - case CTL_CH('c'): /* ^C - break */ - *buf = '\0'; /* discard input */ - return (-1); - case CTL_CH('f'): - if (num < eol_num) { - getcmd_putch(buf[num]); - num++; - } - break; - case CTL_CH('b'): - if (num) { - getcmd_putch(CTL_BACKSPACE); - num--; - } - break; - case CTL_CH('d'): - if (num < eol_num) { - wlen = eol_num - num - 1; - if (wlen) { - memmove(&buf[num], &buf[num+1], wlen); - putnstr(buf + num, wlen); - } - - getcmd_putch(' '); - do { - getcmd_putch(CTL_BACKSPACE); - } while (wlen--); - eol_num--; - } - break; - case CTL_CH('k'): - ERASE_TO_EOL(); - break; - case CTL_CH('e'): - REFRESH_TO_EOL(); - break; - case CTL_CH('o'): - insert = !insert; - break; - case CTL_CH('x'): - case CTL_CH('u'): - BEGINNING_OF_LINE(); - ERASE_TO_EOL(); - break; - case DEL: - case DEL7: - case 8: - if (num) { - wlen = eol_num - num; - num--; - memmove(&buf[num], &buf[num+1], wlen); - getcmd_putch(CTL_BACKSPACE); - putnstr(buf + num, wlen); - getcmd_putch(' '); - do { - getcmd_putch(CTL_BACKSPACE); - } while (wlen--); - eol_num--; - } - break; - case CTL_CH('p'): - case CTL_CH('n'): - { - char * hline; - - esc_len = 0; - - if (ichar == CTL_CH('p')) - hline = hist_prev(); - else - hline = hist_next(); - - if (!hline) { - getcmd_cbeep(); - continue; - } - - /* nuke the current line */ - /* first, go home */ - BEGINNING_OF_LINE(); - - /* erase to end of line */ - ERASE_TO_EOL(); - - /* copy new line into place and display */ - strcpy(buf, hline); - eol_num = strlen(buf); - REFRESH_TO_EOL(); - continue; - } -#ifdef CONFIG_AUTO_COMPLETE - case '\t': { - int num2, col; - - /* do not autocomplete when in the middle */ - if (num < eol_num) { - getcmd_cbeep(); - break; - } - - buf[num] = '\0'; - col = strlen(prompt) + eol_num; - num2 = num; - if (cmd_auto_complete(prompt, buf, &num2, &col)) { - col = num2 - num; - num += col; - eol_num += col; - } - break; - } -#endif - default: - cread_add_char(ichar, insert, &num, &eol_num, buf, *len); - break; - } - } - *len = eol_num; - buf[eol_num] = '\0'; /* lose the newline */ - - if (buf[0] && buf[0] != CREAD_HIST_CHAR) - cread_add_to_hist(buf); - hist_cur = hist_add_idx; - - return 0; -} - -#endif /* CONFIG_CMDLINE_EDITING */ - -/****************************************************************************/ - -/* - * Prompt for input and read a line. - * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0, - * time out when time goes past endtime (timebase time in ticks). - * Return: number of read characters - * -1 if break - * -2 if timed out - */ -int readline (const char *const prompt) -{ - /* - * If console_buffer isn't 0-length the user will be prompted to modify - * it instead of entering it from scratch as desired. - */ - console_buffer[0] = '\0'; - - return readline_into_buffer(prompt, console_buffer, 0); -} - - -int readline_into_buffer(const char *const prompt, char *buffer, int timeout) -{ - char *p = buffer; -#ifdef CONFIG_CMDLINE_EDITING - unsigned int len = CONFIG_SYS_CBSIZE; - int rc; - static int initted = 0; - - /* - * History uses a global array which is not - * writable until after relocation to RAM. - * Revert to non-history version if still - * running from flash. - */ - if (gd->flags & GD_FLG_RELOC) { - if (!initted) { - hist_init(); - initted = 1; - } - - if (prompt) - puts (prompt); - -#ifdef CONFIG_SHOW_ACTIVITY - while (!tstc()) { - extern void show_activity(int arg); - show_activity(0); - WATCHDOG_RESET(); - } -#endif - rc = cread_line(prompt, p, &len, timeout); - return rc < 0 ? rc : len; - - } else { -#endif /* CONFIG_CMDLINE_EDITING */ - char * p_buf = p; - int n = 0; /* buffer index */ - int plen = 0; /* prompt length */ - int col; /* output column cnt */ - char c; - - /* print prompt */ - if (prompt) { - plen = strlen (prompt); - puts (prompt); - } - col = plen; - - for (;;) { -#ifdef CONFIG_BOOT_RETRY_TIME - while (!tstc()) { /* while no incoming data */ - if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ - WATCHDOG_RESET(); - } -#endif - WATCHDOG_RESET(); /* Trigger watchdog, if needed */ - -#ifdef CONFIG_SHOW_ACTIVITY - while (!tstc()) { - show_activity(0); - WATCHDOG_RESET(); - } -#endif - c = getc(); - - /* - * Special character handling - */ - switch (c) { - case '\r': /* Enter */ - case '\n': - *p = '\0'; - puts ("\r\n"); - return p - p_buf; - - case '\0': /* nul */ - continue; - - case 0x03: /* ^C - break */ - p_buf[0] = '\0'; /* discard input */ - return -1; - - case 0x15: /* ^U - erase line */ - while (col > plen) { - puts (erase_seq); - --col; - } - p = p_buf; - n = 0; - continue; - - case 0x17: /* ^W - erase word */ - p=delete_char(p_buf, p, &col, &n, plen); - while ((n > 0) && (*p != ' ')) { - p=delete_char(p_buf, p, &col, &n, plen); - } - continue; - - case 0x08: /* ^H - backspace */ - case 0x7F: /* DEL - backspace */ - p=delete_char(p_buf, p, &col, &n, plen); - continue; - - default: - /* - * Must be a normal character then - */ - if (n < CONFIG_SYS_CBSIZE-2) { - if (c == '\t') { /* expand TABs */ -#ifdef CONFIG_AUTO_COMPLETE - /* if auto completion triggered just continue */ - *p = '\0'; - if (cmd_auto_complete(prompt, console_buffer, &n, &col)) { - p = p_buf + n; /* reset */ - continue; - } -#endif - puts (tab_seq+(col&07)); - col += 8 - (col&07); - } else { - char buf[2]; - - /* - * Echo input using puts() to force an - * LCD flush if we are using an LCD - */ - ++col; - buf[0] = c; - buf[1] = '\0'; - puts(buf); - } - *p++ = c; - ++n; - } else { /* Buffer full */ - putc ('\a'); - } - } - } -#ifdef CONFIG_CMDLINE_EDITING - } -#endif -} - -/****************************************************************************/ - -static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) -{ - char *s; - - if (*np == 0) { - return (p); - } - - if (*(--p) == '\t') { /* will retype the whole line */ - while (*colp > plen) { - puts (erase_seq); - (*colp)--; - } - for (s=buffer; s= CONFIG_SYS_CBSIZE) { - puts ("## Command too long!\n"); - return -1; - } - - strcpy (cmdbuf, cmd); - - /* Process separators and check for invalid - * repeatable commands - */ - - debug_parser("[PROCESS_SEPARATORS] %s\n", cmd); - while (*str) { - - /* - * Find separator, or string end - * Allow simple escape of ';' by writing "\;" - */ - for (inquotes = 0, sep = str; *sep; sep++) { - if ((*sep=='\'') && - (*(sep-1) != '\\')) - inquotes=!inquotes; - - if (!inquotes && - (*sep == ';') && /* separator */ - ( sep != str) && /* past string start */ - (*(sep-1) != '\\')) /* and NOT escaped */ - break; - } - - /* - * Limit the token to data between separators - */ - token = str; - if (*sep) { - str = sep + 1; /* start of command for next pass */ - *sep = '\0'; - } - else - str = sep; /* no more commands for next pass */ - debug_parser("token: \"%s\"\n", token); - - /* find macros in this token and replace them */ - process_macros (token, finaltoken); - - /* Extract arguments */ - if ((argc = parse_line (finaltoken, argv)) == 0) { - rc = -1; /* no command at all */ - continue; - } - - if (cmd_process(flag, argc, argv, &repeatable, NULL) != CMD_RET_SUCCESS) - rc = -1; - - /* Did the user stop this? */ - if (had_ctrlc ()) - return -1; /* if stopped then not repeatable */ - } - - return rc ? rc : repeatable; -} -#endif - -/* - * Run a command using the selected parser. - * - * @param cmd Command to run - * @param flag Execution flags (CMD_FLAG_...) - * @return 0 on success, or != 0 on error. - */ -int run_command(const char *cmd, int flag) -{ -#ifndef CONFIG_SYS_HUSH_PARSER - /* - * builtin_run_command can return 0 or 1 for success, so clean up - * its result. - */ - if ((builtin_run_command(cmd, flag) & ~1) != 0) - return CMD_RET_FAILURE; - - return CMD_RET_SUCCESS; -#else - return parse_string_outer(cmd, - FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP); -#endif -} - -#ifndef CONFIG_SYS_HUSH_PARSER -/** - * Execute a list of command separated by ; or \n using the built-in parser. - * - * This function cannot take a const char * for the command, since if it - * finds newlines in the string, it replaces them with \0. - * - * @param cmd String containing list of commands - * @param flag Execution flags (CMD_FLAG_...) - * @return 0 on success, or != 0 on error. - */ -static int builtin_run_command_list(char *cmd, int flag) +/* We come here after U-Boot is initialised and ready to process commands */ +void main_loop(void) { - char *line, *next; - int rcode = 0; + const char *s; - /* - * Break into individual lines, and execute each line; terminate on - * error. - */ - line = next = cmd; - while (*next) { - if (*next == '\n') { - *next = '\0'; - /* run only non-empty commands */ - if (*line) { - debug("** exec: \"%s\"\n", line); - if (builtin_run_command(line, 0) < 0) { - rcode = 1; - break; - } - } - line = next + 1; - } - ++next; - } - if (rcode == 0 && *line) - rcode = (builtin_run_command(line, 0) >= 0); + bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); - return rcode; -} +#ifndef CONFIG_SYS_GENERIC_BOARD + puts("Warning: Your board does not use generic board. Please read\n"); + puts("doc/README.generic-board and take action. Boards not\n"); + puts("upgraded by the late 2014 may break or be removed.\n"); #endif -int run_command_list(const char *cmd, int len, int flag) -{ - int need_buff = 1; - char *buff = (char *)cmd; /* cast away const */ - int rcode = 0; - - if (len == -1) { - len = strlen(cmd); -#ifdef CONFIG_SYS_HUSH_PARSER - /* hush will never change our string */ - need_buff = 0; -#else - /* the built-in parser will change our string if it sees \n */ - need_buff = strchr(cmd, '\n') != NULL; -#endif - } - if (need_buff) { - buff = malloc(len + 1); - if (!buff) - return 1; - memcpy(buff, cmd, len); - buff[len] = '\0'; - } -#ifdef CONFIG_SYS_HUSH_PARSER - rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON); -#else - /* - * This function will overwrite any \n it sees with a \0, which - * is why it can't work with a const char *. Here we are making - * using of internal knowledge of this function, to avoid always - * doing a malloc() which is actually required only in a case that - * is pretty rare. - */ - rcode = builtin_run_command_list(buff, flag); - if (need_buff) - free(buff); -#endif - - return rcode; -} + modem_init(); +#ifdef CONFIG_VERSION_VARIABLE + setenv("ver", version_string); /* set version variable */ +#endif /* CONFIG_VERSION_VARIABLE */ -/****************************************************************************/ + cli_init(); -#if defined(CONFIG_CMD_RUN) -int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - int i; + run_preboot_environment_command(); - if (argc < 2) - return CMD_RET_USAGE; +#if defined(CONFIG_UPDATE_TFTP) + update_tftp(0UL); +#endif /* CONFIG_UPDATE_TFTP */ - for (i=1; i +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void *malloc_simple(size_t bytes) +{ + ulong new_ptr; + void *ptr; + + new_ptr = gd->malloc_ptr + bytes; + if (new_ptr > gd->malloc_limit) + panic("Out of pre-reloc memory"); + ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes); + gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr)); + return ptr; +} + +#ifdef CONFIG_SYS_MALLOC_SIMPLE +void *calloc(size_t nmemb, size_t elem_size) +{ + size_t size = nmemb * elem_size; + void *ptr; + + ptr = malloc(size); + memset(ptr, '\0', size); + + return ptr; +} +#endif diff --git a/common/memsize.c b/common/memsize.c index 73b92c8a00..0fb9ba57b6 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -5,7 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include + +DECLARE_GLOBAL_DATA_PTR; + #ifdef __PPC__ /* * At least on G2 PowerPC cores, sequential accesses to non-existent @@ -30,43 +33,46 @@ long get_ram_size(long *base, long maxsize) long size; int i = 0; - for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { + for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ - sync (); + sync(); save[i++] = *addr; - sync (); + sync(); *addr = ~cnt; } addr = base; - sync (); + sync(); save[i] = *addr; - sync (); + sync(); *addr = 0; - sync (); + sync(); if ((val = *addr) != 0) { - /* Restore the original data before leaving the function. - */ - sync (); + /* Restore the original data before leaving the function. */ + sync(); *addr = save[i]; for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { addr = base + cnt; - sync (); + sync(); *addr = save[--i]; } return (0); } - for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { + for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { addr = base + cnt; /* pointer arith! */ val = *addr; *addr = save[--i]; if (val != ~cnt) { - size = cnt * sizeof (long); - /* Restore the original data before leaving the function. + size = cnt * sizeof(long); + /* + * Restore the original data + * before leaving the function. */ - for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) { + for (cnt <<= 1; + cnt < maxsize / sizeof(long); + cnt <<= 1) { addr = base + cnt; *addr = save[--i]; } @@ -76,3 +82,14 @@ long get_ram_size(long *base, long maxsize) return (maxsize); } + +phys_size_t __weak get_effective_memsize(void) +{ +#ifndef CONFIG_VERY_BIG_RAM + return gd->ram_size; +#else + /* limit stack to what we can reasonable map */ + return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : gd->ram_size); +#endif +} diff --git a/common/menu.c b/common/menu.c index ba393adc32..e81c074f36 100644 --- a/common/menu.c +++ b/common/menu.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -104,12 +105,9 @@ static inline void *menu_item_destroy(struct menu *m, return NULL; } -void __menu_display_statusline(struct menu *m) +__weak void menu_display_statusline(struct menu *m) { - return; } -void menu_display_statusline(struct menu *m) - __attribute__ ((weak, alias("__menu_display_statusline"))); /* * Display a menu so the user can make a choice of an item. First display its @@ -196,8 +194,9 @@ static inline int menu_interactive_choice(struct menu *m, void **choice) menu_display(m); if (!m->item_choice) { - readret = readline_into_buffer("Enter choice: ", cbuf, - m->timeout / 10); + readret = cli_readline_into_buffer("Enter choice: ", + cbuf, + m->timeout / 10); if (readret >= 0) { choice_item = menu_item_by_key(m, cbuf); diff --git a/common/modem.c b/common/modem.c index be54b10110..96b10648d8 100644 --- a/common/modem.c +++ b/common/modem.c @@ -19,7 +19,7 @@ static inline void mdm_readline(char *buf, int bufsiz) for(;;) { c = serial_getc(); - /* dbg("(%c)", c); */ + debug("(%c)", c); switch(c) { case '\r': @@ -40,7 +40,6 @@ static inline void mdm_readline(char *buf, int bufsiz) } } -extern void dbg(const char *fmt, ...); int mdm_init (void) { char env_str[16]; @@ -66,15 +65,15 @@ int mdm_init (void) serial_puts("\n"); for(;;) { mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini%d: [%s]", i, console_buffer); + debug("ini%d: [%s]", i, console_buffer); if ((strcmp(console_buffer, "OK") == 0) || (strcmp(console_buffer, "ERROR") == 0)) { - dbg("ini%d: cmd done", i); + debug("ini%d: cmd done", i); break; } else /* in case we are originating call ... */ if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini%d: connect", i); + debug("ini%d: connect", i); return 0; } } @@ -90,9 +89,9 @@ int mdm_init (void) for(;i > 1;) { /* if 'i' > 1 - wait for connection message from modem */ mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini_f: [%s]", console_buffer); + debug("ini_f: [%s]", console_buffer); if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini_f: connected"); + debug("ini_f: connected"); return 0; } } diff --git a/common/spl/Makefile b/common/spl/Makefile index e8144f7040..10a4589969 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -8,34 +8,16 @@ # Based on common/Makefile. # -include $(TOPDIR)/config.mk - -LIB = $(obj)libspl.o - ifdef CONFIG_SPL_BUILD -COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o -COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o -COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o -COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o -COBJS-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o -COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o -COBJS-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o +obj-$(CONFIG_SPL_FRAMEWORK) += spl.o +obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o +obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o +obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o +obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o +obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o +obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o +obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o +obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o +obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o +obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o endif - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/common/spl/spl.c b/common/spl/spl.c index e9e3c7449f..526bd1a754 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -7,6 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -23,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #endif #ifndef CONFIG_SYS_MONITOR_LEN +/* Unknown U-Boot size, let's assume it will not be more than 200 KB */ #define CONFIG_SYS_MONITOR_LEN (200 * 1024) #endif @@ -61,6 +64,15 @@ __weak void spl_board_prepare_for_linux(void) /* Nothing to do! */ } +void spl_set_header_raw_uboot(void) +{ + spl_image.size = CONFIG_SYS_MONITOR_LEN; + spl_image.entry_point = CONFIG_SYS_UBOOT_START; + spl_image.load_addr = CONFIG_SYS_TEXT_BASE; + spl_image.os = IH_OS_U_BOOT; + spl_image.name = "U-Boot"; +} + void spl_parse_image_header(const struct image_header *header) { u32 header_size = sizeof(struct image_header); @@ -85,18 +97,14 @@ void spl_parse_image_header(const struct image_header *header) } spl_image.os = image_get_os(header); spl_image.name = image_get_name(header); - debug("spl: payload image: %s load addr: 0x%x size: %d\n", - spl_image.name, spl_image.load_addr, spl_image.size); + debug("spl: payload image: %.*s load addr: 0x%x size: %d\n", + (int)sizeof(spl_image.name), spl_image.name, + spl_image.load_addr, spl_image.size); } else { /* Signature not found - assume u-boot.bin */ debug("mkimage signature not found - ih_magic = %x\n", header->ih_magic); - /* Let's assume U-Boot will not be more than 200 KB */ - spl_image.size = CONFIG_SYS_MONITOR_LEN; - spl_image.entry_point = CONFIG_SYS_UBOOT_START; - spl_image.load_addr = CONFIG_SYS_TEXT_BASE; - spl_image.os = IH_OS_U_BOOT; - spl_image.name = "U-Boot"; + spl_set_header_raw_uboot(); } } @@ -133,9 +141,16 @@ void board_init_r(gd_t *dummy1, ulong dummy2) u32 boot_device; debug(">>spl:board_init_r()\n"); -#ifdef CONFIG_SYS_SPL_MALLOC_START +#if defined(CONFIG_SYS_SPL_MALLOC_START) mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; +#elif defined(CONFIG_SYS_MALLOC_F_LEN) + gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN; + gd->malloc_ptr = 0; +#endif +#ifdef CONFIG_SPL_DM + dm_init_and_scan(true); #endif #ifndef CONFIG_PPC @@ -204,9 +219,21 @@ void board_init_r(gd_t *dummy1, ulong dummy2) case BOOT_DEVICE_USBETH: spl_net_load_image("usb_ether"); break; +#endif +#ifdef CONFIG_SPL_USB_SUPPORT + case BOOT_DEVICE_USB: + spl_usb_load_image(); + break; +#endif +#ifdef CONFIG_SPL_SATA_SUPPORT + case BOOT_DEVICE_SATA: + spl_sata_load_image(); + break; #endif default: - printf("SPL: Unsupported Boot Device\n"); +#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + puts("SPL: Unsupported Boot Device!\n"); +#endif hang(); } @@ -223,6 +250,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) default: debug("Unsupported OS image.. Jumping nevertheless..\n"); } +#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE) + debug("SPL malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr, + gd->malloc_ptr / 1024); +#endif + jump_to_image_no_args(&spl_image); } diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c new file mode 100644 index 0000000000..9d37fd3521 --- /dev/null +++ b/common/spl/spl_ext.c @@ -0,0 +1,139 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_EXT_SUPPORT +int spl_load_image_ext(block_dev_desc_t *block_dev, + int partition, + const char *filename) +{ + s32 err; + struct image_header *header; + loff_t filelen, actlen; + disk_partition_t part_info = {}; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + if (get_partition_info(block_dev, + partition, &part_info)) { + printf("spl: no partition table found\n"); + return -1; + } + + ext4fs_set_blk_dev(block_dev, &part_info); + + err = ext4fs_mount(0); + if (!err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: ext4fs mount err - %d\n", __func__, err); +#endif + goto end; + } + + err = ext4fs_open(filename, &filelen); + if (err < 0) { + puts("spl: ext4fs_open failed\n"); + goto end; + } + err = ext4fs_read((char *)header, sizeof(struct image_header), &actlen); + if (err < 0) { + puts("spl: ext4fs_read failed\n"); + goto end; + } + + spl_parse_image_header(header); + + err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen); + +end: +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + if (err < 0) + printf("%s: error reading image %s, err - %d\n", + __func__, filename, err); +#endif + + return err < 0; +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition) +{ + int err; + __maybe_unused loff_t filelen, actlen; + disk_partition_t part_info = {}; + __maybe_unused char *file; + + if (get_partition_info(block_dev, + partition, &part_info)) { + printf("spl: no partition table found\n"); + return -1; + } + + ext4fs_set_blk_dev(block_dev, &part_info); + + err = ext4fs_mount(0); + if (!err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: ext4fs mount err - %d\n", __func__, err); +#endif + return -1; + } + +#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT) + file = getenv("falcon_args_file"); + if (file) { + err = ext4fs_open(file, &filelen); + if (err < 0) { + puts("spl: ext4fs_open failed\n"); + goto defaults; + } + err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen); + if (err < 0) { + printf("spl: error reading image %s, err - %d, falling back to default\n", + file, err); + goto defaults; + } + file = getenv("falcon_image_file"); + if (file) { + err = spl_load_image_ext(block_dev, partition, file); + if (err != 0) { + puts("spl: falling back to default\n"); + goto defaults; + } + + return 0; + } else { + puts("spl: falcon_image_file not set in environment, falling back to default\n"); + } + } else { + puts("spl: falcon_args_file not set in environment, falling back to default\n"); + } + +defaults: +#endif + + err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME, &filelen); + if (err < 0) + puts("spl: ext4fs_open failed\n"); + + err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen); + if (err < 0) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: error reading image %s, err - %d\n", + __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err); +#endif + return -1; + } + + return spl_load_image_ext(block_dev, partition, + CONFIG_SPL_FS_LOAD_KERNEL_NAME); +} +#endif +#endif diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c new file mode 100644 index 0000000000..350f7d9fd6 --- /dev/null +++ b/common/spl/spl_fat.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, + * + * Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + * + * FAT Image Functions copied from spl_mmc.c + */ + +#include +#include +#include +#include +#include + +static int fat_registered; + +#ifdef CONFIG_SPL_FAT_SUPPORT +static int spl_register_fat_device(block_dev_desc_t *block_dev, int partition) +{ + int err = 0; + + if (fat_registered) + return err; + + err = fat_register_device(block_dev, partition); + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: fat register err - %d\n", __func__, err); +#endif + return err; + } + + fat_registered = 1; + + return err; +} + +int spl_load_image_fat(block_dev_desc_t *block_dev, + int partition, + const char *filename) +{ + int err; + struct image_header *header; + + err = spl_register_fat_device(block_dev, partition); + if (err) + goto end; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + err = file_fat_read(filename, header, sizeof(struct image_header)); + if (err <= 0) + goto end; + + spl_parse_image_header(header); + + err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0); + +end: +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + if (err <= 0) + printf("%s: error reading image %s, err - %d\n", + __func__, filename, err); +#endif + + return (err <= 0); +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition) +{ + int err; + __maybe_unused char *file; + + err = spl_register_fat_device(block_dev, partition); + if (err) + return err; + +#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT) + file = getenv("falcon_args_file"); + if (file) { + err = file_fat_read(file, (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0); + if (err <= 0) { + printf("spl: error reading image %s, err - %d, falling back to default\n", + file, err); + goto defaults; + } + file = getenv("falcon_image_file"); + if (file) { + err = spl_load_image_fat(block_dev, partition, file); + if (err != 0) { + puts("spl: falling back to default\n"); + goto defaults; + } + + return 0; + } else + puts("spl: falcon_image_file not set in environment, falling back to default\n"); + } else + puts("spl: falcon_args_file not set in environment, falling back to default\n"); + +defaults: +#endif + + err = file_fat_read(CONFIG_SPL_FS_LOAD_ARGS_NAME, + (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0); + if (err <= 0) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: error reading image %s, err - %d\n", + __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err); +#endif + return -1; + } + + return spl_load_image_fat(block_dev, partition, + CONFIG_SPL_FS_LOAD_KERNEL_NAME); +} +#endif +#endif diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index e369ce3975..c2e596be69 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -9,14 +9,13 @@ #include #include #include -#include #include -#include #include +#include DECLARE_GLOBAL_DATA_PTR; -static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector) +static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) { unsigned long err; u32 image_size_sectors; @@ -30,6 +29,9 @@ static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector) if (err == 0) goto end; + if (image_get_magic(header) != IH_MAGIC) + return -1; + spl_parse_image_header(header); /* convert size to sectors - round up */ @@ -41,71 +43,48 @@ static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector) (void *)spl_image.load_addr); end: +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT if (err == 0) printf("spl: mmc blk read err - %lu\n", err); +#endif return (err == 0); } -#ifdef CONFIG_SPL_OS_BOOT -static int mmc_load_image_raw_os(struct mmc *mmc) +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION +static int mmc_load_image_raw_partition(struct mmc *mmc, int partition) { - if (!mmc->block_dev.block_read(0, - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS, - (void *)CONFIG_SYS_SPL_ARGS_ADDR)) { - printf("mmc args blk read error\n"); + disk_partition_t info; + + if (get_partition_info(&mmc->block_dev, partition, &info)) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("spl: partition error\n"); +#endif return -1; } - return mmc_load_image_raw(mmc, CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR); + return mmc_load_image_raw_sector(mmc, info.start); } #endif -#ifdef CONFIG_SPL_FAT_SUPPORT -static int mmc_load_image_fat(struct mmc *mmc, const char *filename) -{ - int err; - struct image_header *header; - - header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - - sizeof(struct image_header)); - - err = file_fat_read(filename, header, sizeof(struct image_header)); - if (err <= 0) - goto end; - - spl_parse_image_header(header); - - err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0); - -end: - if (err <= 0) - printf("spl: error reading image %s, err - %d\n", - filename, err); - - return (err <= 0); -} - #ifdef CONFIG_SPL_OS_BOOT -static int mmc_load_image_fat_os(struct mmc *mmc) +static int mmc_load_image_raw_os(struct mmc *mmc) { - int err; - - err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME, - (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0); - if (err <= 0) { - printf("spl: error reading image %s, err - %d\n", - CONFIG_SPL_FAT_LOAD_ARGS_NAME, err); + if (!mmc->block_dev.block_read(0, + CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, + CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS, + (void *)CONFIG_SYS_SPL_ARGS_ADDR)) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("mmc args blk read error\n"); +#endif return -1; } - return mmc_load_image_fat(mmc, CONFIG_SPL_FAT_LOAD_KERNEL_NAME); + return mmc_load_image_raw_sector(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR); } #endif -#endif - void spl_mmc_load_image(void) { struct mmc *mmc; @@ -116,13 +95,17 @@ void spl_mmc_load_image(void) /* We register only one device. So, the dev id is always 0 */ mmc = find_mmc_device(0); if (!mmc) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("spl: mmc device not found!!\n"); +#endif hang(); } err = mmc_init(mmc); if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT printf("spl: mmc init failed: err - %d\n", err); +#endif hang(); } @@ -132,27 +115,81 @@ void spl_mmc_load_image(void) #ifdef CONFIG_SPL_OS_BOOT if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) #endif - err = mmc_load_image_raw(mmc, - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION + err = mmc_load_image_raw_partition(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION); +#else + err = mmc_load_image_raw_sector(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); +#endif +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) + } + if (err || boot_mode == MMCSD_MODE_FS) { + debug("boot mode - FS\n"); #ifdef CONFIG_SPL_FAT_SUPPORT - } else if (boot_mode == MMCSD_MODE_FAT) { - debug("boot mode - FAT\n"); - - err = fat_register_device(&mmc->block_dev, - CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION); - if (err) { - printf("spl: fat register err - %d\n", err); +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION)) +#endif + err = spl_load_image_fat(&mmc->block_dev, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + if(err) +#endif /* CONFIG_SPL_FAT_SUPPORT */ + { +#ifdef CONFIG_SPL_EXT_SUPPORT +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION)) +#endif + err = spl_load_image_ext(&mmc->block_dev, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); +#endif /* CONFIG_SPL_EXT_SUPPORT */ + } +#endif /* defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) */ +#ifdef CONFIG_SUPPORT_EMMC_BOOT + } else if (boot_mode == MMCSD_MODE_EMMCBOOT) { + /* + * We need to check what the partition is configured to. + * 1 and 2 match up to boot0 / boot1 and 7 is user data + * which is the first physical partition (0). + */ + int part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + + if (part == 7) + part = 0; + + if (mmc_switch_part(0, part)) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + puts("MMC partition switch failed\n"); +#endif hang(); } - #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || mmc_load_image_fat_os(mmc)) + if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) #endif - err = mmc_load_image_fat(mmc, CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); + err = mmc_load_image_raw_sector(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #endif - } else { - puts("spl: wrong MMC boot mode\n"); - hang(); + } + + switch(boot_mode){ + case MMCSD_MODE_RAW: +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) + case MMCSD_MODE_FS: +#endif +#ifdef CONFIG_SUPPORT_EMMC_BOOT + case MMCSD_MODE_EMMCBOOT: +#endif + /* Boot mode is ok. Nothing to do. */ + break; + case MMCSD_MODE_UNDEFINED: + default: +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + puts("spl: wrong MMC boot mode\n"); +#endif + hang(); } if (err) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index da14d1faaf..f58c21a7d6 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -10,6 +10,24 @@ #include #include +#if defined(CONFIG_SPL_NAND_RAW_ONLY) +int spl_nand_load_image(void) +{ + int ret; + + nand_init(); + + ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (void *)CONFIG_SYS_NAND_U_BOOT_DST); + nand_deselect(); + if (ret) + return ret; + + spl_set_header_raw_uboot(); + return 0; +} +#else int spl_nand_load_image(void) { int ret; @@ -45,7 +63,7 @@ int spl_nand_load_image(void) /* load linux */ nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + sizeof(*header), (void *)header); spl_parse_image_header(header); if (header->ih_os == IH_OS_LINUX) { /* happy - was a linux */ @@ -63,13 +81,13 @@ int spl_nand_load_image(void) #endif #ifdef CONFIG_NAND_ENV_DST nand_spl_load_image(CONFIG_ENV_OFFSET, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + sizeof(*header), (void *)header); spl_parse_image_header(header); nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size, (void *)spl_image.load_addr); #ifdef CONFIG_ENV_OFFSET_REDUND nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + sizeof(*header), (void *)header); spl_parse_image_header(header); nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size, (void *)spl_image.load_addr); @@ -86,3 +104,4 @@ int spl_nand_load_image(void) nand_deselect(); return ret; } +#endif diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index b444a3ea2b..2c0e8e00dd 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -15,37 +15,51 @@ void spl_nor_load_image(void) */ spl_image.flags |= SPL_COPY_PAYLOAD_ONLY; - if (spl_start_uboot()) { - /* - * Load real U-Boot from its location in NOR flash to its - * defined location in SDRAM - */ - spl_parse_image_header( - (const struct image_header *)CONFIG_SYS_UBOOT_BASE); +#ifdef CONFIG_SPL_OS_BOOT + if (!spl_start_uboot()) { + struct image_header *header; - memcpy((void *)spl_image.load_addr, - (void *)(CONFIG_SYS_UBOOT_BASE + - sizeof(struct image_header)), - spl_image.size); - } else { /* * Load Linux from its location in NOR flash to its defined * location in SDRAM */ - spl_parse_image_header( - (const struct image_header *)CONFIG_SYS_OS_BASE); + header = (const struct image_header *)CONFIG_SYS_OS_BASE; - memcpy((void *)spl_image.load_addr, - (void *)(CONFIG_SYS_OS_BASE + - sizeof(struct image_header)), - spl_image.size); + if (image_get_os(header) == IH_OS_LINUX) { + /* happy - was a Linux */ - /* - * Copy DT blob (fdt) to SDRAM. Passing pointer to flash - * doesn't work (16 KiB should be enough for DT) - */ - memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR, - (void *)(CONFIG_SYS_FDT_BASE), - (16 << 10)); + spl_parse_image_header(header); + + memcpy((void *)spl_image.load_addr, + (void *)(CONFIG_SYS_OS_BASE + + sizeof(struct image_header)), + spl_image.size); + + /* + * Copy DT blob (fdt) to SDRAM. Passing pointer to + * flash doesn't work (16 KiB should be enough for DT) + */ + memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR, + (void *)(CONFIG_SYS_FDT_BASE), + (16 << 10)); + + return; + } else { + puts("The Expected Linux image was not found.\n" + "Please check your NOR configuration.\n" + "Trying to start u-boot now...\n"); + } } +#endif + + /* + * Load real U-Boot from its location in NOR flash to its + * defined location in SDRAM + */ + spl_parse_image_header( + (const struct image_header *)CONFIG_SYS_UBOOT_BASE); + + memcpy((void *)spl_image.load_addr, + (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)), + spl_image.size); } diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c new file mode 100644 index 0000000000..d9eb2d6687 --- /dev/null +++ b/common/spl/spl_sata.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013 + * Texas Instruments, + * + * Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived work from spl_usb.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_sata_load_image(void) +{ + int err; + block_dev_desc_t *stor_dev; + + err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE); + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("spl: sata init failed: err - %d\n", err); +#endif + hang(); + } else { + /* try to recognize storage devices immediately */ + scsi_scan(0); + stor_dev = scsi_get_dev(0); + } + +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spl_load_image_fat_os(stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION)) +#endif + err = spl_load_image_fat(stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + if (err) { + puts("Error loading sata device\n"); + hang(); + } +} diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c new file mode 100644 index 0000000000..c81672b798 --- /dev/null +++ b/common/spl/spl_usb.c @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, + * + * Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived work from spl_mmc.c + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB_STORAGE +static int usb_stor_curr_dev = -1; /* current device */ +#endif + +void spl_usb_load_image(void) +{ + int err; + block_dev_desc_t *stor_dev; + + usb_stop(); + err = usb_init(); + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("%s: usb init failed: err - %d\n", __func__, err); +#endif + hang(); + } + +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + usb_stor_curr_dev = usb_stor_scan(1); + stor_dev = usb_stor_get_dev(usb_stor_curr_dev); +#endif + + debug("boot mode - FAT\n"); + +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spl_load_image_fat_os(stor_dev, + CONFIG_SYS_USB_FAT_BOOT_PARTITION)) +#endif + err = spl_load_image_fat(stor_dev, + CONFIG_SYS_USB_FAT_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + + if (err) { + puts("Error loading USB device\n"); + hang(); + } +} diff --git a/common/splash.c b/common/splash.c index 18885f1bfe..144fb10ddd 100644 --- a/common/splash.c +++ b/common/splash.c @@ -23,15 +23,11 @@ #include #include -int __splash_screen_prepare(void) +__weak int splash_screen_prepare(void) { return 0; } -int splash_screen_prepare(void) - __attribute__ ((weak, alias("__splash_screen_prepare"))); - - #ifdef CONFIG_SPLASH_SCREEN_ALIGN void splash_get_pos(int *x, int *y) { diff --git a/common/stdio.c b/common/stdio.c index 721e9a1444..adbfc890dd 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -33,25 +34,48 @@ char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" }; #define CONFIG_SYS_DEVICE_NULLDEV 1 #endif +#ifdef CONFIG_SYS_STDIO_DEREGISTER +#define CONFIG_SYS_DEVICE_NULLDEV 1 +#endif #ifdef CONFIG_SYS_DEVICE_NULLDEV -void nulldev_putc(const char c) +static void nulldev_putc(struct stdio_dev *dev, const char c) { /* nulldev is empty! */ } -void nulldev_puts(const char *s) +static void nulldev_puts(struct stdio_dev *dev, const char *s) { /* nulldev is empty! */ } -int nulldev_input(void) +static int nulldev_input(struct stdio_dev *dev) { /* nulldev is empty! */ return 0; } #endif +static void stdio_serial_putc(struct stdio_dev *dev, const char c) +{ + serial_putc(c); +} + +static void stdio_serial_puts(struct stdio_dev *dev, const char *s) +{ + serial_puts(s); +} + +static int stdio_serial_getc(struct stdio_dev *dev) +{ + return serial_getc(); +} + +static int stdio_serial_tstc(struct stdio_dev *dev) +{ + return serial_tstc(); +} + /************************************************************************** * SYSTEM DRIVERS ************************************************************************** @@ -65,10 +89,10 @@ static void drv_system_init (void) strcpy (dev.name, "serial"); dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - dev.putc = serial_putc; - dev.puts = serial_puts; - dev.getc = serial_getc; - dev.tstc = serial_tstc; + dev.putc = stdio_serial_putc; + dev.puts = stdio_serial_puts; + dev.getc = stdio_serial_getc; + dev.tstc = stdio_serial_tstc; stdio_register (&dev); #ifdef CONFIG_SYS_DEVICE_NULLDEV @@ -128,35 +152,42 @@ struct stdio_dev* stdio_clone(struct stdio_dev *dev) return _dev; } -int stdio_register (struct stdio_dev * dev) +int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp) { struct stdio_dev *_dev; _dev = stdio_clone(dev); if(!_dev) - return -1; + return -ENODEV; list_add_tail(&(_dev->list), &(devs.list)); + if (devp) + *devp = _dev; + return 0; } +int stdio_register(struct stdio_dev *dev) +{ + return stdio_register_dev(dev, NULL); +} + /* deregister the device "devname". * returns 0 if success, -1 if device is assigned and 1 if devname not found */ #ifdef CONFIG_SYS_STDIO_DEREGISTER -int stdio_deregister(const char *devname) +int stdio_deregister_dev(struct stdio_dev *dev, int force) { int l; struct list_head *pos; - struct stdio_dev *dev; char temp_names[3][16]; - dev = stdio_get_by_name(devname); - - if(!dev) /* device not found */ - return -1; /* get stdio devices (ListRemoveItem changes the dev list) */ for (l=0 ; l< MAX_FILES; l++) { if (stdio_devices[l] == dev) { + if (force) { + strcpy(temp_names[l], "nulldev"); + continue; + } /* Device is assigned -> report error */ return -1; } @@ -166,6 +197,7 @@ int stdio_deregister(const char *devname) } list_del(&(dev->list)); + free(dev); /* reassign Device list */ list_for_each(pos, &(devs.list)) { @@ -177,9 +209,21 @@ int stdio_deregister(const char *devname) } return 0; } + +int stdio_deregister(const char *devname, int force) +{ + struct stdio_dev *dev; + + dev = stdio_get_by_name(devname); + + if (!dev) /* device not found */ + return -ENODEV; + + return stdio_deregister_dev(dev, force); +} #endif /* CONFIG_SYS_STDIO_DEREGISTER */ -int stdio_init (void) +int stdio_init_tables(void) { #if defined(CONFIG_NEEDS_MANUAL_RELOC) /* already relocated for current ARM implementation */ @@ -196,9 +240,11 @@ int stdio_init (void) /* Initialize the list */ INIT_LIST_HEAD(&(devs.list)); -#ifdef CONFIG_ARM_DCC - drv_arm_dcc_init (); -#endif + return 0; +} + +int stdio_add_devices(void) +{ #ifdef CONFIG_SYS_I2C i2c_init_all(); #else @@ -232,5 +278,14 @@ int stdio_init (void) #ifdef CONFIG_CBMEM_CONSOLE cbmemc_init(); #endif - return (0); + + return 0; +} + +int stdio_init(void) +{ + stdio_init_tables(); + stdio_add_devices(); + + return 0; } diff --git a/common/usb.c b/common/usb.c index f740e5ec21..32e15cd8dd 100644 --- a/common/usb.c +++ b/common/usb.c @@ -33,7 +33,7 @@ #include #include #include - +#include #include #ifdef CONFIG_4xx #include @@ -59,6 +59,8 @@ int usb_init(void) void *ctrl; struct usb_device *dev; int i, start_index = 0; + int controllers_initialized = 0; + int ret; dev_index = 0; asynch_allowed = 1; @@ -74,7 +76,14 @@ int usb_init(void) for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { /* init low_level USB */ printf("USB%d: ", i); - if (usb_lowlevel_init(i, &ctrl)) { + ret = usb_lowlevel_init(i, USB_INIT_HOST, &ctrl); + if (ret == -ENODEV) { /* No such device. */ + puts("Port not available.\n"); + controllers_initialized++; + continue; + } + + if (ret) { /* Other error. */ puts("lowlevel init failed\n"); continue; } @@ -82,6 +91,7 @@ int usb_init(void) * lowlevel init is OK, now scan the bus for devices * i.e. search HUBs and configure them */ + controllers_initialized++; start_index = dev_index; printf("scanning bus %d for devices... ", i); dev = usb_alloc_new_device(ctrl); @@ -103,12 +113,10 @@ int usb_init(void) debug("scan end\n"); /* if we were not able to find at least one working bus, bail out */ - if (!usb_started) { + if (controllers_initialized == 0) puts("USB error: all controllers failed lowlevel init\n"); - return -1; - } - return 0; + return usb_started ? 0 : -1; } /****************************************************************************** @@ -323,6 +331,7 @@ static int usb_set_maxpacket(struct usb_device *dev) /******************************************************************************* * Parse the config, located in buffer, and fills the dev->config structure. * Note that all little/big endian swapping are done automatically. + * (wTotalLength has already been swapped and sanitized when it was read.) */ static int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) @@ -343,24 +352,43 @@ static int usb_parse_config(struct usb_device *dev, head->bDescriptorType); return -1; } - memcpy(&dev->config, buffer, buffer[0]); - le16_to_cpus(&(dev->config.desc.wTotalLength)); + if (head->bLength != USB_DT_CONFIG_SIZE) { + printf("ERROR: Invalid USB CFG length (%d)\n", head->bLength); + return -1; + } + memcpy(&dev->config, head, USB_DT_CONFIG_SIZE); dev->config.no_of_if = 0; index = dev->config.desc.bLength; /* Ok the first entry must be a configuration entry, * now process the others */ head = (struct usb_descriptor_header *) &buffer[index]; - while (index + 1 < dev->config.desc.wTotalLength) { + while (index + 1 < dev->config.desc.wTotalLength && head->bLength) { switch (head->bDescriptorType) { case USB_DT_INTERFACE: + if (head->bLength != USB_DT_INTERFACE_SIZE) { + printf("ERROR: Invalid USB IF length (%d)\n", + head->bLength); + break; + } + if (index + USB_DT_INTERFACE_SIZE > + dev->config.desc.wTotalLength) { + puts("USB IF descriptor overflowed buffer!\n"); + break; + } if (((struct usb_interface_descriptor *) \ - &buffer[index])->bInterfaceNumber != curr_if_num) { + head)->bInterfaceNumber != curr_if_num) { /* this is a new interface, copy new desc */ ifno = dev->config.no_of_if; + if (ifno >= USB_MAXINTERFACES) { + puts("Too many USB interfaces!\n"); + /* try to go on with what we have */ + return 1; + } if_desc = &dev->config.if_desc[ifno]; dev->config.no_of_if++; - memcpy(if_desc, &buffer[index], buffer[index]); + memcpy(if_desc, head, + USB_DT_INTERFACE_SIZE); if_desc->no_of_ep = 0; if_desc->num_altsetting = 1; curr_if_num = @@ -374,12 +402,31 @@ static int usb_parse_config(struct usb_device *dev, } break; case USB_DT_ENDPOINT: + if (head->bLength != USB_DT_ENDPOINT_SIZE) { + printf("ERROR: Invalid USB EP length (%d)\n", + head->bLength); + break; + } + if (index + USB_DT_ENDPOINT_SIZE > + dev->config.desc.wTotalLength) { + puts("USB EP descriptor overflowed buffer!\n"); + break; + } + if (ifno < 0) { + puts("Endpoint descriptor out of order!\n"); + break; + } epno = dev->config.if_desc[ifno].no_of_ep; if_desc = &dev->config.if_desc[ifno]; + if (epno > USB_MAXENDPOINTS) { + printf("Interface %d has too many endpoints!\n", + if_desc->desc.bInterfaceNumber); + return 1; + } /* found an endpoint */ if_desc->no_of_ep++; - memcpy(&if_desc->ep_desc[epno], - &buffer[index], buffer[index]); + memcpy(&if_desc->ep_desc[epno], head, + USB_DT_ENDPOINT_SIZE); ep_wMaxPacketSize = get_unaligned(&dev->config.\ if_desc[ifno].\ ep_desc[epno].\ @@ -392,9 +439,23 @@ static int usb_parse_config(struct usb_device *dev, debug("if %d, ep %d\n", ifno, epno); break; case USB_DT_SS_ENDPOINT_COMP: + if (head->bLength != USB_DT_SS_EP_COMP_SIZE) { + printf("ERROR: Invalid USB EPC length (%d)\n", + head->bLength); + break; + } + if (index + USB_DT_SS_EP_COMP_SIZE > + dev->config.desc.wTotalLength) { + puts("USB EPC descriptor overflowed buffer!\n"); + break; + } + if (ifno < 0 || epno < 0) { + puts("EPC descriptor out of order!\n"); + break; + } if_desc = &dev->config.if_desc[ifno]; - memcpy(&if_desc->ss_ep_comp_desc[epno], - &buffer[index], buffer[index]); + memcpy(&if_desc->ss_ep_comp_desc[epno], head, + USB_DT_SS_EP_COMP_SIZE); break; default: if (head->bLength == 0) @@ -473,7 +534,7 @@ int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer, int cfgno) { int result; - unsigned int tmp; + unsigned int length; struct usb_config_descriptor *config; config = (struct usb_config_descriptor *)&buffer[0]; @@ -487,16 +548,18 @@ int usb_get_configuration_no(struct usb_device *dev, "(expected %i, got %i)\n", 9, result); return -1; } - tmp = le16_to_cpu(config->wTotalLength); + length = le16_to_cpu(config->wTotalLength); - if (tmp > USB_BUFSIZ) { - printf("usb_get_configuration_no: failed to get " \ - "descriptor - too long: %d\n", tmp); + if (length > USB_BUFSIZ) { + printf("%s: failed to get descriptor - too long: %d\n", + __func__, length); return -1; } - result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp); - debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, tmp); + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, length); + debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, length); + config->wTotalLength = length; /* validated, with CPU byte order */ + return result; } @@ -799,6 +862,16 @@ void usb_free_device(void) usb_dev[dev_index].devnum = -1; } +/* + * XHCI issues Enable Slot command and thereafter + * allocates device contexts. Provide a weak alias + * function for the purpose, so that XHCI overrides it + * and EHCI/OHCI just work out of the box. + */ +__weak int usb_alloc_device(struct usb_device *udev) +{ + return 0; +} /* * By the time we get here, the device has gotten a new device ID * and is in the default state. We need to identify the thing and @@ -812,6 +885,17 @@ int usb_new_device(struct usb_device *dev) int tmp; ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ); + /* + * Allocate usb 3.0 device context. + * USB 3.0 (xHCI) protocol tries to allocate device slot + * and related data structures first. This call does that. + * Refer to sec 4.3.2 in xHCI spec rev1.0 + */ + if (usb_alloc_device(dev)) { + printf("Cannot allocate device context to get SLOT_ID\n"); + return -1; + } + /* We still haven't set the Address yet */ addr = dev->devnum; dev->devnum = 0; @@ -842,8 +926,7 @@ int usb_new_device(struct usb_device *dev) * http://sourceforge.net/mailarchive/forum.php? * thread_id=5729457&forum_id=5398 */ - struct usb_device_descriptor *desc; - int port = -1; + __maybe_unused struct usb_device_descriptor *desc; struct usb_device *parent = dev->parent; unsigned short portstatus; @@ -859,6 +942,13 @@ int usb_new_device(struct usb_device *dev) dev->epmaxpacketin[0] = 64; dev->epmaxpacketout[0] = 64; + /* + * XHCI needs to issue a Address device command to setup + * proper device context structures, before it can interact + * with the device. So a get_descriptor will fail before any + * of that is done for XHCI unlike EHCI. + */ +#ifndef CONFIG_USB_XHCI err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64); if (err < 0) { debug("usb_new_device: usb_get_descriptor() failed\n"); @@ -871,28 +961,17 @@ int usb_new_device(struct usb_device *dev) * to differentiate between HUB and DEVICE. */ dev->descriptor.bDeviceClass = desc->bDeviceClass; +#endif - /* find the port number we're at */ if (parent) { - int j; - - for (j = 0; j < parent->maxchild; j++) { - if (parent->children[j] == dev) { - port = j; - break; - } - } - if (port < 0) { - printf("usb_new_device:cannot locate device's port.\n"); - return 1; - } - /* reset the port for the second time */ - err = hub_port_reset(dev->parent, port, &portstatus); + err = hub_port_reset(dev->parent, dev->portnr - 1, &portstatus); if (err < 0) { - printf("\n Couldn't reset port %i\n", port); + printf("\n Couldn't reset port %i\n", dev->portnr); return 1; } + } else { + usb_reset_root_port(); } #endif @@ -982,4 +1061,9 @@ int usb_new_device(struct usb_device *dev) return 0; } +__weak +int board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} /* EOF */ diff --git a/common/usb_hub.c b/common/usb_hub.c index a11b401e62..66b4a725d1 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -35,15 +35,15 @@ #include #endif -#ifndef CONFIG_USB_HUB_MIN_POWER_ON_DELAY -#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 100 -#endif - #define USB_BUFSIZ 512 static struct usb_hub_device hub_dev[USB_MAX_HUB]; static int usb_hub_index; +__weak void usb_hub_reset_devices(int port) +{ + return; +} static int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size) { @@ -86,56 +86,20 @@ static void usb_hub_power_on(struct usb_hub_device *hub) int i; struct usb_device *dev; unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2; - ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); - unsigned short portstatus; - int ret; dev = hub->pusb_dev; - /* - * Enable power to the ports: - * Here we Power-cycle the ports: aka, - * turning them off and turning on again. - */ debug("enabling power on all ports\n"); - for (i = 0; i < dev->maxchild; i++) { - usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); - debug("port %d returns %lX\n", i + 1, dev->status); - } - - /* Wait at least 2*bPwrOn2PwrGood for PP to change */ - mdelay(pgood_delay); - - for (i = 0; i < dev->maxchild; i++) { - ret = usb_get_port_status(dev, i + 1, portsts); - if (ret < 0) { - debug("port %d: get_port_status failed\n", i + 1); - continue; - } - - /* - * Check to confirm the state of Port Power: - * xHCI says "After modifying PP, s/w shall read - * PP and confirm that it has reached the desired state - * before modifying it again, undefined behavior may occur - * if this procedure is not followed". - * EHCI doesn't say anything like this, but no harm in keeping - * this. - */ - portstatus = le16_to_cpu(portsts->wPortStatus); - if (portstatus & (USB_PORT_STAT_POWER << 1)) { - debug("port %d: Port power change failed\n", i + 1); - continue; - } - } - for (i = 0; i < dev->maxchild; i++) { usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); debug("port %d returns %lX\n", i + 1, dev->status); } - /* Wait for power to become stable */ - mdelay(max(pgood_delay, CONFIG_USB_HUB_MIN_POWER_ON_DELAY)); + /* + * Wait for power to become stable, + * plus spec-defined max time for device to connect + */ + mdelay(pgood_delay + 1000); } void usb_hub_reset(void) @@ -206,9 +170,22 @@ int hub_port_reset(struct usb_device *dev, int port, (portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0, (portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0); - if ((portchange & USB_PORT_STAT_C_CONNECTION) || - !(portstatus & USB_PORT_STAT_CONNECTION)) - return -1; + /* + * Perhaps we should check for the following here: + * - C_CONNECTION hasn't been set. + * - CONNECTION is still set. + * + * Doing so would ensure that the device is still connected + * to the bus, and hasn't been unplugged or replaced while the + * USB bus reset was going on. + * + * However, if we do that, then (at least) a San Disk Ultra + * USB 3.0 16GB device fails to reset on (at least) an NVIDIA + * Tegra Jetson TK1 board. For some reason, the device appears + * to briefly drop off the bus when this second bus reset is + * executed, yet if we retry this loop, it'll eventually come + * back after another reset or two. + */ if (portstatus & USB_PORT_STAT_ENABLE) break; @@ -302,7 +279,7 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port) static int usb_hub_configure(struct usb_device *dev) { - int i; + int i, length; ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, USB_BUFSIZ); unsigned char *bitmap; short hubCharacteristics; @@ -323,20 +300,15 @@ static int usb_hub_configure(struct usb_device *dev) } descriptor = (struct usb_hub_descriptor *)buffer; - /* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */ - i = descriptor->bLength; - if (i > USB_BUFSIZ) { - debug("usb_hub_configure: failed to get hub " \ - "descriptor - too long: %d\n", descriptor->bLength); - return -1; - } + length = min_t(int, descriptor->bLength, + sizeof(struct usb_hub_descriptor)); - if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) { + if (usb_get_hub_descriptor(dev, buffer, length) < 0) { debug("usb_hub_configure: failed to get hub " \ "descriptor 2nd giving up %lX\n", dev->status); return -1; } - memcpy((unsigned char *)&hub->desc, buffer, descriptor->bLength); + memcpy((unsigned char *)&hub->desc, buffer, length); /* adjust 16bit values */ put_unaligned(le16_to_cpu(get_unaligned( &descriptor->wHubCharacteristics)), @@ -426,6 +398,14 @@ static int usb_hub_configure(struct usb_device *dev) "" : "no "); usb_hub_power_on(hub); + /* + * Reset any devices that may be in a bad state when applying + * the power. This is a __weak function. Resetting of the devices + * should occur in the board file of the device. + */ + for (i = 0; i < dev->maxchild; i++) + usb_hub_reset_devices(i + 1); + for (i = 0; i < dev->maxchild; i++) { ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); unsigned short portstatus, portchange; diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 2ca3767ecf..ecc3085cc0 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -8,6 +8,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -91,7 +92,18 @@ static const unsigned char usb_kbd_arrow[] = { #define USB_KBD_LEDMASK \ (USB_KBD_NUMLOCK | USB_KBD_CAPSLOCK | USB_KBD_SCROLLLOCK) +/* + * USB Keyboard reports are 8 bytes in boot protocol. + * Appendix B of HID Device Class Definition 1.11 + */ +#define USB_KBD_BOOT_REPORT_SIZE 8 + struct usb_kbd_pdata { + unsigned long intpipe; + int intpktsize; + int intinterval; + struct int_queue *intq; + uint32_t repeat_delay; uint32_t usb_in_pointer; @@ -99,35 +111,15 @@ struct usb_kbd_pdata { uint8_t usb_kbd_buffer[USB_KBD_BUFFER_LEN]; uint8_t *new; - uint8_t old[8]; + uint8_t old[USB_KBD_BOOT_REPORT_SIZE]; uint8_t flags; }; -/* Generic keyboard event polling. */ -void usb_kbd_generic_poll(void) -{ - struct stdio_dev *dev; - struct usb_device *usb_kbd_dev; - struct usb_kbd_pdata *data; - struct usb_interface *iface; - struct usb_endpoint_descriptor *ep; - int pipe; - int maxp; - - /* Get the pointer to USB Keyboard device pointer */ - dev = stdio_get_by_name(DEVNAME); - usb_kbd_dev = (struct usb_device *)dev->priv; - data = usb_kbd_dev->privptr; - iface = &usb_kbd_dev->config.if_desc[0]; - ep = &iface->ep_desc[0]; - pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress); +extern int __maybe_unused net_busy_flag; - /* Submit a interrupt transfer request */ - maxp = usb_maxpacket(usb_kbd_dev, pipe); - usb_submit_int_msg(usb_kbd_dev, pipe, data->new, - maxp > 8 ? 8 : maxp, ep->bInterval); -} +/* The period of time between two calls of usb_kbd_testc(). */ +static unsigned long __maybe_unused kbd_testc_tms; /* Puts character in the queue and sets up the in and out pointer. */ static void usb_kbd_put_queue(struct usb_kbd_pdata *data, char c) @@ -158,11 +150,12 @@ static void usb_kbd_setled(struct usb_device *dev) { struct usb_interface *iface = &dev->config.if_desc[0]; struct usb_kbd_pdata *data = dev->privptr; - uint32_t leds = data->flags & USB_KBD_LEDMASK; + ALLOC_ALIGN_BUFFER(uint32_t, leds, 1, USB_DMA_MINALIGN); + *leds = data->flags & USB_KBD_LEDMASK; usb_control_msg(dev, usb_sndctrlpipe(dev, 0), USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE, - 0x200, iface->desc.bInterfaceNumber, (void *)&leds, 1, 0); + 0x200, iface->desc.bInterfaceNumber, leds, 1, 0); } #define CAPITAL_MASK 0x20 @@ -261,8 +254,11 @@ static uint32_t usb_kbd_service_key(struct usb_device *dev, int i, int up) old = data->old; } - if ((old[i] > 3) && (memscan(new + 2, old[i], 6) == new + 8)) + if ((old[i] > 3) && + (memscan(new + 2, old[i], USB_KBD_BOOT_REPORT_SIZE - 2) == + new + USB_KBD_BOOT_REPORT_SIZE)) { res |= usb_kbd_translate(data, old[i], data->new[0], up); + } return res; } @@ -280,7 +276,7 @@ static int usb_kbd_irq_worker(struct usb_device *dev) else if ((data->new[0] == LEFT_CNTR) || (data->new[0] == RIGHT_CNTR)) data->flags |= USB_KBD_CTRL; - for (i = 2; i < 8; i++) { + for (i = 2; i < USB_KBD_BOOT_REPORT_SIZE; i++) { res |= usb_kbd_service_key(dev, i, 0); res |= usb_kbd_service_key(dev, i, 1); } @@ -292,7 +288,7 @@ static int usb_kbd_irq_worker(struct usb_device *dev) if (res == 1) usb_kbd_setled(dev); - memcpy(data->old, data->new, 8); + memcpy(data->old, data->new, USB_KBD_BOOT_REPORT_SIZE); return 1; } @@ -300,7 +296,8 @@ static int usb_kbd_irq_worker(struct usb_device *dev) /* Keyboard interrupt handler */ static int usb_kbd_irq(struct usb_device *dev) { - if ((dev->irq_status != 0) || (dev->irq_act_len != 8)) { + if ((dev->irq_status != 0) || + (dev->irq_act_len != USB_KBD_BOOT_REPORT_SIZE)) { debug("USB KBD: Error %lX, len %d\n", dev->irq_status, dev->irq_act_len); return 1; @@ -313,22 +310,11 @@ static int usb_kbd_irq(struct usb_device *dev) static inline void usb_kbd_poll_for_event(struct usb_device *dev) { #if defined(CONFIG_SYS_USB_EVENT_POLL) - struct usb_interface *iface; - struct usb_endpoint_descriptor *ep; - struct usb_kbd_pdata *data; - int pipe; - int maxp; - - /* Get the pointer to USB Keyboard device pointer */ - data = dev->privptr; - iface = &dev->config.if_desc[0]; - ep = &iface->ep_desc[0]; - pipe = usb_rcvintpipe(dev, ep->bEndpointAddress); + struct usb_kbd_pdata *data = dev->privptr; /* Submit a interrupt transfer request */ - maxp = usb_maxpacket(dev, pipe); - usb_submit_int_msg(dev, pipe, &data->new[0], - maxp > 8 ? 8 : maxp, ep->bInterval); + usb_submit_int_msg(dev, data->intpipe, &data->new[0], data->intpktsize, + data->intinterval); usb_kbd_irq_worker(dev); #elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) @@ -336,19 +322,39 @@ static inline void usb_kbd_poll_for_event(struct usb_device *dev) struct usb_kbd_pdata *data = dev->privptr; iface = &dev->config.if_desc[0]; usb_get_report(dev, iface->desc.bInterfaceNumber, - 1, 0, data->new, sizeof(data->new)); - if (memcmp(data->old, data->new, sizeof(data->new))) + 1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE); + if (memcmp(data->old, data->new, USB_KBD_BOOT_REPORT_SIZE)) + usb_kbd_irq_worker(dev); +#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE) + struct usb_kbd_pdata *data = dev->privptr; + if (poll_int_queue(dev, data->intq)) { usb_kbd_irq_worker(dev); + /* We've consumed all queued int packets, create new */ + destroy_int_queue(dev, data->intq); + data->intq = create_int_queue(dev, data->intpipe, 1, + USB_KBD_BOOT_REPORT_SIZE, data->new, + data->intinterval); + } #endif } /* test if a character is in the queue */ -static int usb_kbd_testc(void) +static int usb_kbd_testc(struct stdio_dev *sdev) { struct stdio_dev *dev; struct usb_device *usb_kbd_dev; struct usb_kbd_pdata *data; +#ifdef CONFIG_CMD_NET + /* + * If net_busy_flag is 1, NET transfer is running, + * then we check key-pressed every second (first check may be + * less than 1 second) to improve TFTP booting performance. + */ + if (net_busy_flag && (get_timer(kbd_testc_tms) < CONFIG_SYS_HZ)) + return 0; + kbd_testc_tms = get_timer(0); +#endif dev = stdio_get_by_name(DEVNAME); usb_kbd_dev = (struct usb_device *)dev->priv; data = usb_kbd_dev->privptr; @@ -359,7 +365,7 @@ static int usb_kbd_testc(void) } /* gets the character from the queue */ -static int usb_kbd_getc(void) +static int usb_kbd_getc(struct stdio_dev *sdev) { struct stdio_dev *dev; struct usb_device *usb_kbd_dev; @@ -386,7 +392,6 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) struct usb_interface *iface; struct usb_endpoint_descriptor *ep; struct usb_kbd_pdata *data; - int pipe, maxp; if (dev->descriptor.bNumConfigurations != 1) return 0; @@ -426,7 +431,8 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) memset(data, 0, sizeof(struct usb_kbd_pdata)); /* allocate input buffer aligned and sized to USB DMA alignment */ - data->new = memalign(USB_DMA_MINALIGN, roundup(8, USB_DMA_MINALIGN)); + data->new = memalign(USB_DMA_MINALIGN, + roundup(USB_KBD_BOOT_REPORT_SIZE, USB_DMA_MINALIGN)); /* Insert private data into USB device structure */ dev->privptr = data; @@ -434,8 +440,10 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) /* Set IRQ handler */ dev->irq_handle = usb_kbd_irq; - pipe = usb_rcvintpipe(dev, ep->bEndpointAddress); - maxp = usb_maxpacket(dev, pipe); + data->intpipe = usb_rcvintpipe(dev, ep->bEndpointAddress); + data->intpktsize = min(usb_maxpacket(dev, data->intpipe), + USB_KBD_BOOT_REPORT_SIZE); + data->intinterval = ep->bInterval; /* We found a USB Keyboard, install it. */ usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0); @@ -444,8 +452,15 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0); debug("USB KBD: enable interrupt pipe...\n"); - if (usb_submit_int_msg(dev, pipe, data->new, maxp > 8 ? 8 : maxp, - ep->bInterval) < 0) { +#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE + data->intq = create_int_queue(dev, data->intpipe, 1, + USB_KBD_BOOT_REPORT_SIZE, data->new, + data->intinterval); + if (!data->intq) { +#else + if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize, + data->intinterval) < 0) { +#endif printf("Failed to get keyboard state from device %04x:%04x\n", dev->descriptor.idVendor, dev->descriptor.idProduct); /* Abort, we don't want to use that non-functional keyboard. */ @@ -459,7 +474,7 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) /* Search for keyboard and register it if found. */ int drv_usb_kbd_init(void) { - struct stdio_dev usb_kbd_dev, *old_dev; + struct stdio_dev usb_kbd_dev; struct usb_device *dev; char *stdinname = getenv("stdin"); int error, i; @@ -478,23 +493,11 @@ int drv_usb_kbd_init(void) if (usb_kbd_probe(dev, 0) != 1) continue; - /* We found a keyboard, check if it is already registered. */ - debug("USB KBD: found set up device.\n"); - old_dev = stdio_get_by_name(DEVNAME); - if (old_dev) { - /* Already registered, just return ok. */ - debug("USB KBD: is already registered.\n"); - usb_kbd_deregister(); - return 1; - } - /* Register the keyboard */ debug("USB KBD: register.\n"); memset(&usb_kbd_dev, 0, sizeof(struct stdio_dev)); strcpy(usb_kbd_dev.name, DEVNAME); usb_kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - usb_kbd_dev.putc = NULL; - usb_kbd_dev.puts = NULL; usb_kbd_dev.getc = usb_kbd_getc; usb_kbd_dev.tstc = usb_kbd_testc; usb_kbd_dev.priv = (void *)dev; @@ -528,10 +531,31 @@ int drv_usb_kbd_init(void) } /* Deregister the keyboard. */ -int usb_kbd_deregister(void) +int usb_kbd_deregister(int force) { #ifdef CONFIG_SYS_STDIO_DEREGISTER - return stdio_deregister(DEVNAME); + struct stdio_dev *dev; + struct usb_device *usb_kbd_dev; + struct usb_kbd_pdata *data; + + dev = stdio_get_by_name(DEVNAME); + if (dev) { + usb_kbd_dev = (struct usb_device *)dev->priv; + data = usb_kbd_dev->privptr; + if (stdio_deregister_dev(dev, force) != 0) + return 1; +#ifdef CONFIG_CONSOLE_MUX + if (iomux_doenv(stdin, getenv("stdin")) != 0) + return 1; +#endif +#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE + destroy_int_queue(usb_kbd_dev, data->intq); +#endif + free(data->new); + free(data); + } + + return 0; #else return 1; #endif diff --git a/common/usb_storage.c b/common/usb_storage.c index 6ac358d5e2..1411737bed 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -33,6 +33,7 @@ #include #include +#include #include #include @@ -1071,7 +1072,7 @@ unsigned long usb_stor_read(int device, lbaint_t blknr, blks = blkcnt; debug("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF - " buffer %lx\n", device, start, blks, buf_addr); + " buffer %" PRIxPTR "\n", device, start, blks, buf_addr); do { /* XXX need some comment here */ @@ -1101,7 +1102,7 @@ retry_it: ss->flags &= ~USB_READY; debug("usb_read: end startblk " LBAF - ", blccnt %x buffer %lx\n", + ", blccnt %x buffer %" PRIxPTR "\n", start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ @@ -1145,7 +1146,7 @@ unsigned long usb_stor_write(int device, lbaint_t blknr, blks = blkcnt; debug("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF - " buffer %lx\n", device, start, blks, buf_addr); + " buffer %" PRIxPTR "\n", device, start, blks, buf_addr); do { /* If write fails retry for max retry count else @@ -1176,8 +1177,8 @@ retry_it: } while (blks != 0); ss->flags &= ~USB_READY; - debug("usb_write: end startblk " LBAF ", blccnt %x buffer %lx\n", - start, smallblks, buf_addr); + debug("usb_write: end startblk " LBAF ", blccnt %x buffer %" + PRIxPTR "\n", start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ if (blkcnt >= USB_MAX_XFER_BLK) @@ -1350,8 +1351,11 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, perq = usb_stor_buf[0]; modi = usb_stor_buf[1]; - if ((perq & 0x1f) == 0x1f) { - /* skip unknown devices */ + /* + * Skip unknown devices (0x1f) and enclosure service devices (0x0d), + * they would not respond to test_unit_ready . + */ + if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) { return 0; } if ((modi&0x80) == 0x80) { diff --git a/common/xyzModem.c b/common/xyzModem.c index 82039df1f3..8e35e99a0d 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -760,7 +760,8 @@ xyzModem_stream_terminate (bool abort, int (*getc) (void)) * If we don't eat it now, RedBoot will think the user typed it. */ ZM_DEBUG (zm_dprintf ("Trailing gunk:\n")); - while ((c = (*getc) ()) > -1); + while ((c = (*getc) ()) > -1) + ; ZM_DEBUG (zm_dprintf ("\n")); /* * Make a small delay to give terminal programs like minicom diff --git a/config.mk b/config.mk index 4c4551828f..64c2951ac1 100644 --- a/config.mk +++ b/config.mk @@ -6,365 +6,77 @@ # ######################################################################### -# Set shell to bash if possible, otherwise fall back to sh -SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ - else if [ -x /bin/bash ]; then echo /bin/bash; \ - else echo sh; fi; fi) - -export SHELL - -ifeq ($(CURDIR),$(SRCTREE)) -dir := -else -dir := $(subst $(SRCTREE)/,,$(CURDIR)) -endif - -ifneq ($(OBJTREE),$(SRCTREE)) -# Create object files for SPL in a separate directory -ifeq ($(CONFIG_SPL_BUILD),y) -obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) -else -obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) -endif -src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) - -$(shell mkdir -p $(obj)) -else -# Create object files for SPL in a separate directory -ifeq ($(CONFIG_SPL_BUILD),y) -obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) - -$(shell mkdir -p $(obj)) -else -obj := -endif -src := -endif - -# clean the slate ... -PLATFORM_RELFLAGS = -PLATFORM_CPPFLAGS = -PLATFORM_LDFLAGS = - -######################################################################### - -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \ - $(HOSTCPPFLAGS) -HOSTSTRIP = strip - -# -# Mac OS X / Darwin's C preprocessor is Apple specific. It -# generates numerous errors and warnings. We want to bypass it -# and use GNU C's cpp. To do this we pass the -traditional-cpp -# option to the compiler. Note that the -traditional-cpp flag -# DOES NOT have the same semantics as GNU C's flag, all it does -# is invoke the GNU preprocessor in stock ANSI/ISO C fashion. +# This file is included from ./Makefile and spl/Makefile. +# Clean the state to avoid the same flags added twice. # -# Apple's linker is similar, thanks to the new 2 stage linking -# multiple symbol definitions are treated as errors, hence the -# -multiply_defined suppress option to turn off this error. -# - -ifeq ($(HOSTOS),darwin) -# get major and minor product version (e.g. '10' and '6' for Snow Leopard) -DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.') -DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.') - -os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \ - $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) - -# Snow Leopards build environment has no longer restrictions as described above -HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc") -HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") -HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") -else -HOSTCC = gcc -endif - -ifeq ($(HOSTOS),cygwin) -HOSTCFLAGS += -ansi -endif - -# We build some files with extra pedantic flags to try to minimize things -# that won't build on some weird host compiler -- though there are lots of -# exceptions for files that aren't complaint. - -HOSTCFLAGS_NOPED = $(filter-out -pedantic,$(HOSTCFLAGS)) -HOSTCFLAGS += -pedantic - +# (Tegra needs different flags for SPL. +# That's the reason why this file must be included from spl/Makefile too. +# If we did not have Tegra SoCs, build system would be much simpler...) +PLATFORM_RELFLAGS := +PLATFORM_CPPFLAGS := +PLATFORM_LDFLAGS := +LDFLAGS := +LDFLAGS_FINAL := +OBJCOPYFLAGS := +# clear VENDOR for tcsh +VENDOR := ######################################################################### -# -# Option checker, gcc version (courtesy linux kernel) to ensure -# only supported compiler options are used -# -CC_OPTIONS_CACHE_FILE := $(OBJTREE)/include/generated/cc_options.mk -CC_TEST_OFILE := $(OBJTREE)/include/generated/cc_test_file.o - --include $(CC_OPTIONS_CACHE_FILE) -cc-option-sys = $(shell mkdir -p $(dir $(CC_TEST_OFILE)); \ - if $(CC) $(CFLAGS) $(1) -S -xc /dev/null -o $(CC_TEST_OFILE) \ - > /dev/null 2>&1; then \ - echo 'CC_OPTIONS += $(strip $1)' >> $(CC_OPTIONS_CACHE_FILE); \ - echo "$(1)"; fi) - -ifeq ($(CONFIG_CC_OPT_CACHE_DISABLE),y) -cc-option = $(strip $(if $(call cc-option-sys,$1),$1,$2)) -else -cc-option = $(strip $(if $(findstring $1,$(CC_OPTIONS)),$1,\ - $(if $(call cc-option-sys,$1),$1,$2))) +ARCH := $(CONFIG_SYS_ARCH:"%"=%) +CPU := $(CONFIG_SYS_CPU:"%"=%) +BOARD := $(CONFIG_SYS_BOARD:"%"=%) +ifneq ($(CONFIG_SYS_VENDOR),) +VENDOR := $(CONFIG_SYS_VENDOR:"%"=%) +endif +ifneq ($(CONFIG_SYS_SOC),) +SOC := $(CONFIG_SYS_SOC:"%"=%) endif - -# cc-version -# Usage gcc-ver := $(call cc-version) -cc-version = $(shell $(SHELL) $(SRCTREE)/tools/gcc-version.sh $(CC)) -binutils-version = $(shell $(SHELL) $(SRCTREE)/tools/binutils-version.sh $(AS)) -dtc-version = $(shell $(SHELL) $(SRCTREE)/tools/dtc-version.sh $(DTC)) - -# -# Include the make variables (CC, etc...) -# -AS = $(CROSS_COMPILE)as - -# Always use GNU ld -LD = $(shell if $(CROSS_COMPILE)ld.bfd -v > /dev/null 2>&1; \ - then echo "$(CROSS_COMPILE)ld.bfd"; else echo "$(CROSS_COMPILE)ld"; fi;) - -CC = $(CROSS_COMPILE)gcc -CPP = $(CC) -E -AR = $(CROSS_COMPILE)ar -NM = $(CROSS_COMPILE)nm -LDR = $(CROSS_COMPILE)ldr -STRIP = $(CROSS_COMPILE)strip -OBJCOPY = $(CROSS_COMPILE)objcopy -OBJDUMP = $(CROSS_COMPILE)objdump -RANLIB = $(CROSS_COMPILE)RANLIB -DTC = dtc -CHECK = sparse - -######################################################################### - -# Load generated board configuration -sinclude $(OBJTREE)/include/autoconf.mk -sinclude $(OBJTREE)/include/config.mk # Some architecture config.mk files need to know what CPUDIR is set to, # so calculate CPUDIR before including ARCH/SOC/CPU config.mk files. # Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains # CPU-specific code. -CPUDIR=arch/$(ARCH)/cpu/$(CPU) -ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR))) -CPUDIR=arch/$(ARCH)/cpu -endif +CPUDIR=arch/$(ARCH)/cpu$(if $(CPU),/$(CPU),) -sinclude $(TOPDIR)/arch/$(ARCH)/config.mk # include architecture dependend rules -sinclude $(TOPDIR)/$(CPUDIR)/config.mk # include CPU specific rules +sinclude $(srctree)/arch/$(ARCH)/config.mk # include architecture dependend rules +sinclude $(srctree)/$(CPUDIR)/config.mk # include CPU specific rules ifdef SOC -sinclude $(TOPDIR)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules +sinclude $(srctree)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules endif +ifneq ($(BOARD),) ifdef VENDOR BOARDDIR = $(VENDOR)/$(BOARD) else BOARDDIR = $(BOARD) endif -ifdef BOARD -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules -endif - -######################################################################### - -# We don't actually use $(ARFLAGS) anywhere anymore, so catch people -# who are porting old code to latest mainline but not updating $(AR). -ARFLAGS = $(error update your Makefile to use cmd_link_o_target and not AR) -RELFLAGS= $(PLATFORM_RELFLAGS) -DBGFLAGS= -g # -DDEBUG -OPTFLAGS= -Os #-fomit-frame-pointer - -OBJCFLAGS += --gap-fill=0xff - -gccincdir := $(shell $(CC) -print-file-name=include) - -CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ - -D__KERNEL__ - -# Enable garbage collection of un-used sections for SPL -ifeq ($(CONFIG_SPL_BUILD),y) -CPPFLAGS += -ffunction-sections -fdata-sections -LDFLAGS_FINAL += --gc-sections endif - -# TODO(sjg@chromium.org): Is this correct on Mac OS? -ifdef CONFIG_FIT_SIGNATURE -HOSTLIBS += -lssl -lcrypto - -# This affects include/image.h, but including the board config file -# is tricky, so manually define this options here. -HOSTCFLAGS += -DCONFIG_FIT_SIGNATURE -endif - -ifneq ($(CONFIG_SYS_TEXT_BASE),) -CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -endif - -ifneq ($(CONFIG_SPL_TEXT_BASE),) -CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE) -endif - -ifneq ($(CONFIG_SPL_PAD_TO),) -CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO) -endif - -ifneq ($(CONFIG_UBOOT_PAD_TO),) -CPPFLAGS += -DCONFIG_UBOOT_PAD_TO=$(CONFIG_UBOOT_PAD_TO) -endif - -ifeq ($(CONFIG_SPL_BUILD),y) -CPPFLAGS += -DCONFIG_SPL_BUILD -endif - -# Does this architecture support generic board init? -ifeq ($(__HAVE_ARCH_GENERIC_BOARD),) -ifneq ($(CONFIG_SYS_GENERIC_BOARD),) -CHECK_GENERIC_BOARD = $(error Your architecture does not support generic board. \ -Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file) -endif -endif - -ifneq ($(RESET_VECTOR_ADDRESS),) -CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS) -endif - -ifneq ($(OBJTREE),$(SRCTREE)) -CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include -endif - -CPPFLAGS += -I$(TOPDIR)/include -CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ - -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) - -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes - -ifdef BUILD_TAG -CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' -endif - -CFLAGS_SSP := $(call cc-option,-fno-stack-protector) - -# Some toolchains enable security related warning flags by default, -# but they don't make much sense in the u-boot world, so disable them. -CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \ - $(call cc-option,-Wno-format-security) - -CFLAGS := $(CFLAGS_SSP) $(CFLAGS_WARN) $(CPPFLAGS) -Wall -Wstrict-prototypes -ifdef BUILD_TAG - CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' +ifdef BOARD +sinclude $(srctree)/board/$(BOARDDIR)/config.mk # include board specific rules endif -# Report stack usage if supported -CFLAGS_STACK := $(call cc-option,-fstack-usage) -CFLAGS += $(CFLAGS_STACK) - -BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%)) - -ifeq ($(findstring examples/,$(BCURDIR)),) -ifeq ($(CONFIG_SPL_BUILD),) ifdef FTRACE -CFLAGS += -finstrument-functions -DFTRACE -endif -endif -endif - -# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g -# option to the assembler. -AFLAGS_DEBUG := - -# turn jbsr into jsr for m68k -ifeq ($(ARCH),m68k) -ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4) -AFLAGS_DEBUG := -Wa,-gstabs,-S -endif -endif - -AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) - -LDFLAGS += $(PLATFORM_LDFLAGS) -LDFLAGS_FINAL += -Bstatic - -LDFLAGS_u-boot += -T $(obj)u-boot.lds $(LDFLAGS_FINAL) -ifneq ($(CONFIG_SYS_TEXT_BASE),) -LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) -endif - -LDFLAGS_u-boot-spl += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL) -ifneq ($(CONFIG_SPL_TEXT_BASE),) -LDFLAGS_u-boot-spl += -Ttext $(CONFIG_SPL_TEXT_BASE) +PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE endif -# Linus' kernel sanity checking tool -CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ - -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF) - -# Location of a usable BFD library, where we define "usable" as -# "built for ${HOST}, supports ${TARGET}". Sensible values are -# - When cross-compiling: the root of the cross-environment -# - Linux/ppc (native): /usr -# - NetBSD/ppc (native): you lose ... (must extract these from the -# binutils build directory, plus the native and U-Boot include -# files don't like each other) -# -# So far, this is used only by tools/gdb/Makefile. - -ifeq ($(HOSTOS),darwin) -BFD_ROOT_DIR = /usr/local/tools -else -ifeq ($(HOSTARCH),$(ARCH)) -# native -BFD_ROOT_DIR = /usr -else -#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 -#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 -BFD_ROOT_DIR = /opt/powerpc -endif +# Allow use of stdint.h if available +ifneq ($(USE_STDINT),) +PLATFORM_CPPFLAGS += -DCONFIG_USE_STDINT endif ######################################################################### -export HOSTCC HOSTCFLAGS HOSTLDFLAGS PEDCFLAGS HOSTSTRIP CROSS_COMPILE \ - AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP MAKE -export CONFIG_SYS_TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS - -######################################################################### - -# Allow boards to use custom optimize flags on a per dir/file basis -ALL_AFLAGS = $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) -ALL_CFLAGS = $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) -EXTRA_CPPFLAGS = $(CPPFLAGS_$(BCURDIR)/$(@F)) $(CPPFLAGS_$(BCURDIR)) -ALL_CFLAGS += $(EXTRA_CPPFLAGS) +RELFLAGS := $(PLATFORM_RELFLAGS) -# The _DEP version uses the $< file target (for dependency generation) -# See rules.mk -EXTRA_CPPFLAGS_DEP = $(CPPFLAGS_$(BCURDIR)/$(addsuffix .o,$(basename $<))) \ - $(CPPFLAGS_$(BCURDIR)) -$(obj)%.s: %.S - $(CPP) $(ALL_AFLAGS) -o $@ $< -$(obj)%.o: %.S - $(CC) $(ALL_AFLAGS) -o $@ $< -c -$(obj)%.o: %.c -ifneq ($(CHECKSRC),0) - $(CHECK) $(CHECKFLAGS) $(ALL_CFLAGS) $< -endif - $(CC) $(ALL_CFLAGS) -o $@ $< -c -$(obj)%.i: %.c - $(CPP) $(ALL_CFLAGS) -o $@ $< -c -$(obj)%.s: %.c - $(CC) $(ALL_CFLAGS) -o $@ $< -c -S +OBJCOPYFLAGS += --gap-fill=0xff -######################################################################### +PLATFORM_CPPFLAGS += $(RELFLAGS) +PLATFORM_CPPFLAGS += -pipe -# If the list of objects to link is empty, just create an empty built-in.o -cmd_link_o_target = $(if $(strip $1),\ - $(LD) $(LDFLAGS) -r -o $@ $1,\ - rm -f $@; $(AR) rcs $@ ) +LDFLAGS += $(PLATFORM_LDFLAGS) +LDFLAGS_FINAL += -Bstatic -######################################################################### +export PLATFORM_CPPFLAGS +export RELFLAGS +export LDFLAGS_FINAL +export CONFIG_STANDALONE_LOAD_ADDR diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig new file mode 100644 index 0000000000..8fa1a330cd --- /dev/null +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-olinuxino-lime.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=480 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig new file mode 100644 index 0000000000..b5f0a0f782 --- /dev/null +++ b/configs/A10s-OLinuXino-M_defconfig @@ -0,0 +1,13 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI" +CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb" +CONFIG_MMC_SUNXI_SLOT_EXTRA=1 +CONFIG_USB1_VBUS_PIN="PB10" ++S:CONFIG_MMC0_CD_PIN="PG1" ++S:CONFIG_MMC1_CD_PIN="PG13" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig new file mode 100644 index 0000000000..a04f2b3362 --- /dev/null +++ b/configs/A13-OLinuXinoM_defconfig @@ -0,0 +1,18 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI" +CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb" +CONFIG_USB1_VBUS_PIN="PG11" +CONFIG_VIDEO_HDMI=n +CONFIG_VIDEO_VGA_VIA_LCD=y +CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y +# For use with the Olimex 7" LCD module, adjust timings for other displays +# Set video-mode=sunxi:800x600-24@60,monitor=lcd in the env. to enable +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="PB10" +CONFIG_VIDEO_LCD_BL_PWM="PB2" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig new file mode 100644 index 0000000000..806d5b7bd5 --- /dev/null +++ b/configs/A13-OLinuXino_defconfig @@ -0,0 +1,18 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI" +CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb" +CONFIG_USB1_VBUS_PIN="PG11" +CONFIG_VIDEO_HDMI=n +CONFIG_VIDEO_VGA_VIA_LCD=y +CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y +# For use with the Olimex 7" LCD module, adjust timings for other displays +# Set video-mode=sunxi:800x600-24@60,monitor=lcd in the env. to enable +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="AXP0-0" +CONFIG_VIDEO_LCD_BL_PWM="PB2" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig new file mode 100644 index 0000000000..ff94e77200 --- /dev/null +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-olinuxino-lime2.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=480 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig new file mode 100644 index 0000000000..5442f645f8 --- /dev/null +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-olinuxino-lime.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=480 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig new file mode 100644 index 0000000000..97a21ee534 --- /dev/null +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -0,0 +1,13 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb" +CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +CONFIG_VIDEO_VGA=y ++S:CONFIG_MMC0_CD_PIN="PH1" ++S:CONFIG_MMC3_CD_PIN="PH11" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=384 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig new file mode 100644 index 0000000000..03ec3dbdc4 --- /dev/null +++ b/configs/Auxtek-T004_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" +CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb" +CONFIG_USB1_VBUS_PIN="PG13" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig new file mode 100644 index 0000000000..5367e9bc62 --- /dev/null +++ b/configs/B4420QDS_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_B4860QDS=y diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig new file mode 100644 index 0000000000..d62a0688ca --- /dev/null +++ b/configs/B4420QDS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_B4860QDS=y diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig new file mode 100644 index 0000000000..dc77f70233 --- /dev/null +++ b/configs/B4420QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_B4860QDS=y diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig new file mode 100644 index 0000000000..05cf734101 --- /dev/null +++ b/configs/B4860QDS_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_B4860QDS=y diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..f73a2ae1b4 --- /dev/null +++ b/configs/B4860QDS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_B4860QDS=y diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig new file mode 100644 index 0000000000..235d3eaa58 --- /dev/null +++ b/configs/B4860QDS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_B4860QDS=y diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..dda19442a6 --- /dev/null +++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_B4860QDS=y diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig new file mode 100644 index 0000000000..15b3dfb057 --- /dev/null +++ b/configs/B4860QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_B4860QDS=y diff --git a/configs/BC3450_defconfig b/configs/BC3450_defconfig new file mode 100644 index 0000000000..ecb46e92f7 --- /dev/null +++ b/configs/BC3450_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_BC3450=y diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig new file mode 100644 index 0000000000..1adc2b8d11 --- /dev/null +++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_BSC9131RDB=y diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig new file mode 100644 index 0000000000..502fa31475 --- /dev/null +++ b/configs/BSC9131RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_BSC9131RDB=y diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig new file mode 100644 index 0000000000..895ae12d3b --- /dev/null +++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9131RDB=y diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig new file mode 100644 index 0000000000..89619762c0 --- /dev/null +++ b/configs/BSC9131RDB_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9131RDB=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig new file mode 100644 index 0000000000..8aef0d6bf3 --- /dev/null +++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig new file mode 100644 index 0000000000..3c3b46e4df --- /dev/null +++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig new file mode 100644 index 0000000000..ac31fad0d2 --- /dev/null +++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig new file mode 100644 index 0000000000..d2e7391003 --- /dev/null +++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig new file mode 100644 index 0000000000..b26f6e0cbc --- /dev/null +++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig new file mode 100644 index 0000000000..7eaa32db95 --- /dev/null +++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig new file mode 100644 index 0000000000..13d7794cb2 --- /dev/null +++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig new file mode 100644 index 0000000000..7e205c58a6 --- /dev/null +++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig new file mode 100644 index 0000000000..8e5585a762 --- /dev/null +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig new file mode 100644 index 0000000000..6a7920f6f0 --- /dev/null +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig new file mode 100644 index 0000000000..920cf6ccb6 --- /dev/null +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig new file mode 100644 index 0000000000..95a35f2c8c --- /dev/null +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig new file mode 100644 index 0000000000..c55b5a7836 --- /dev/null +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig new file mode 100644 index 0000000000..85e47011ed --- /dev/null +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig new file mode 100644 index 0000000000..7eb3727219 --- /dev/null +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig new file mode 100644 index 0000000000..b8e4e7d103 --- /dev/null +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_BSC9132QDS=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig new file mode 100644 index 0000000000..5aba938276 --- /dev/null +++ b/configs/Bananapi_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-bananapi.dtb" +CONFIG_GMAC_TX_DELAY=3 ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig new file mode 100644 index 0000000000..e501b5c95c --- /dev/null +++ b/configs/Bananapro_defconfig @@ -0,0 +1,12 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-bananapro.dtb" +CONFIG_USB1_VBUS_PIN="PH0" +CONFIG_USB2_VBUS_PIN="PH1" +CONFIG_GMAC_TX_DELAY=3 ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig new file mode 100644 index 0000000000..c9325795b5 --- /dev/null +++ b/configs/C29XPCIE_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_C29XPCIE=y diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig new file mode 100644 index 0000000000..86751cf8ac --- /dev/null +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_C29XPCIE=y diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig new file mode 100644 index 0000000000..d1a42b27eb --- /dev/null +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_C29XPCIE=y diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig new file mode 100644 index 0000000000..2185d9d88d --- /dev/null +++ b/configs/C29XPCIE_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_C29XPCIE=y diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig new file mode 100644 index 0000000000..2ee3305f83 --- /dev/null +++ b/configs/C29XPCIE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_C29XPCIE=y diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig new file mode 100644 index 0000000000..23631e92ab --- /dev/null +++ b/configs/CPCI2DP_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_CPCI2DP=y diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig new file mode 100644 index 0000000000..5d30b79c0b --- /dev/null +++ b/configs/CPCI4052_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_CPCI4052=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig new file mode 100644 index 0000000000..4040beea69 --- /dev/null +++ b/configs/CSQ_CS908_defconfig @@ -0,0 +1,15 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" +CONFIG_FDTFILE="sun6i-a31s-cs908.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=123 +# Ethernet phy power ++S:CONFIG_AXP221_DLDO1_VOLT=3300 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# No Vbus gpio for either usb ++S:CONFIG_USB1_VBUS_PIN="" ++S:CONFIG_USB2_VBUS_PIN="" diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig new file mode 100644 index 0000000000..680b6317df --- /dev/null +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -0,0 +1,19 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" +CONFIG_FDTFILE="sun4i-a10-chuwi-v7-cw0825.dtb" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN="PB9" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="PH8" +CONFIG_VIDEO_LCD_BL_EN="PH7" +CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_VIDEO_LCD_SPI_CS="PA0" +CONFIG_VIDEO_LCD_SPI_SCLK="PA1" +CONFIG_VIDEO_LCD_SPI_MOSI="PA2" +CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig new file mode 100644 index 0000000000..33edcc4205 --- /dev/null +++ b/configs/Colombus_defconfig @@ -0,0 +1,12 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" +CONFIG_FDTFILE="sun6i-a31-colombus.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_DRAM_CLK=240 ++S:CONFIG_DRAM_ZQ=251 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# No Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN="" diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig new file mode 100644 index 0000000000..7704a0ef81 --- /dev/null +++ b/configs/Cubieboard2_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=480 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig new file mode 100644 index 0000000000..4efc6e147e --- /dev/null +++ b/configs/Cubieboard_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-cubieboard.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=480 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig new file mode 100644 index 0000000000..b64f84f2b8 --- /dev/null +++ b/configs/Cubietruck_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb" +CONFIG_VIDEO_VGA=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig new file mode 100644 index 0000000000..027546391f --- /dev/null +++ b/configs/Hummingbird_A31_defconfig @@ -0,0 +1,16 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)" +CONFIG_FDTFILE="sun6i-a31-hummingbird.dtb" +CONFIG_VIDEO_VGA_VIA_LCD=y +CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_DRAM_CLK=312 ++S:CONFIG_DRAM_ZQ=251 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN="PH24" +# No Vbus gpio for usb2 ++S:CONFIG_USB2_VBUS_PIN="" diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig new file mode 100644 index 0000000000..204640ee24 --- /dev/null +++ b/configs/Hyundai_A7HD_defconfig @@ -0,0 +1,23 @@ +# The Hyundai A7HD is a 7" 16:9 A10 powered tablet featuring 1G RAM, 8G +# nand, 1024x600 IPS screen, a mini hdmi port, mini usb receptacle and a +# headphones port for details see: http://linux-sunxi.org/Hyundai_A7HD +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" +CONFIG_FDTFILE="sun4i-a10-hyundai-a7hd.dtb" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN="PB09" +CONFIG_USB1_VBUS_PIN="" +CONFIG_USB2_VBUS_PIN="PH6" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=1 +CONFIG_VIDEO_LCD_POWER="PH2" +CONFIG_VIDEO_LCD_BL_EN="PH9" +CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n +CONFIG_VIDEO_LCD_PANEL_LVDS=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=360 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Inet_86VS_defconfig b/configs/Inet_86VS_defconfig new file mode 100644 index 0000000000..ce9985affe --- /dev/null +++ b/configs/Inet_86VS_defconfig @@ -0,0 +1,15 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" +CONFIG_FDTFILE="sun5i-a13-inet-86vs.dtb" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN="PG12" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="AXP0-0" +CONFIG_VIDEO_LCD_BL_EN="AXP0-1" +CONFIG_VIDEO_LCD_BL_PWM="PB2" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig new file mode 100644 index 0000000000..192a461f55 --- /dev/null +++ b/configs/Ippo_q8h_v1_2_defconfig @@ -0,0 +1,20 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" +CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v1.2.dtb" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN="axp_drivebus" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER="PH7" +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN8I=y ++S:CONFIG_DRAM_CLK=432 +# zq = 0xf74a ++S:CONFIG_DRAM_ZQ=63306 +# Wifi power ++S:CONFIG_AXP221_DLDO1_VOLT=3300 +# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP ++S:CONFIG_AXP221_ALDO1_VOLT=3000 diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig new file mode 100644 index 0000000000..4786202e16 --- /dev/null +++ b/configs/Ippo_q8h_v5_defconfig @@ -0,0 +1,20 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" +CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN="axp_drivebus" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER="PH7" +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN8I=y ++S:CONFIG_DRAM_CLK=480 +# zq = 0xf777 ++S:CONFIG_DRAM_ZQ=63351 +# Wifi power ++S:CONFIG_AXP221_DLDO1_VOLT=3300 +# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP ++S:CONFIG_AXP221_ALDO1_VOLT=3000 diff --git a/configs/JSE_defconfig b/configs/JSE_defconfig new file mode 100644 index 0000000000..14c9c2feea --- /dev/null +++ b/configs/JSE_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_JSE=y diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig new file mode 100644 index 0000000000..4baba14bf0 --- /dev/null +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -0,0 +1,11 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-pcduino3-nano.dtb" +CONFIG_GMAC_TX_DELAY=3 +CONFIG_USB1_VBUS_PIN="PH11" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=122 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig new file mode 100644 index 0000000000..45d88f3015 --- /dev/null +++ b/configs/Linksprite_pcDuino3_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=480 ++S:CONFIG_DRAM_ZQ=122 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig new file mode 100644 index 0000000000..3b6dfa6fa6 --- /dev/null +++ b/configs/Linksprite_pcDuino3_fdt_defconfig @@ -0,0 +1,13 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb" +CONFIG_DM=y +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=480 ++S:CONFIG_DRAM_ZQ=122 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig new file mode 100644 index 0000000000..1ba37bb3fb --- /dev/null +++ b/configs/Linksprite_pcDuino_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-pcduino.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig new file mode 100644 index 0000000000..c7276834a4 --- /dev/null +++ b/configs/M5208EVBE_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_M5208EVBE=y diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig new file mode 100644 index 0000000000..bcf2359b75 --- /dev/null +++ b/configs/M52277EVB_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000" +CONFIG_M68K=y +CONFIG_TARGET_M52277EVB=y diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig new file mode 100644 index 0000000000..0e49bc34f7 --- /dev/null +++ b/configs/M52277EVB_stmicro_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000" +CONFIG_M68K=y +CONFIG_TARGET_M52277EVB=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig new file mode 100644 index 0000000000..e6facec4e1 --- /dev/null +++ b/configs/M5235EVB_Flash32_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000" +CONFIG_M68K=y +CONFIG_TARGET_M5235EVB=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig new file mode 100644 index 0000000000..04b11ecbf1 --- /dev/null +++ b/configs/M5235EVB_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFE00000" +CONFIG_M68K=y +CONFIG_TARGET_M5235EVB=y diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig new file mode 100644 index 0000000000..fb292744e0 --- /dev/null +++ b/configs/M5249EVB_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_M5249EVB=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig new file mode 100644 index 0000000000..68cad2f284 --- /dev/null +++ b/configs/M5253DEMO_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_M5253DEMO=y diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig new file mode 100644 index 0000000000..5c562fe64e --- /dev/null +++ b/configs/M5253EVBE_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_M5253EVBE=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig new file mode 100644 index 0000000000..fdb872a566 --- /dev/null +++ b/configs/M5272C3_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_M5272C3=y diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig new file mode 100644 index 0000000000..1e33649639 --- /dev/null +++ b/configs/M5275EVB_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_M5275EVB=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig new file mode 100644 index 0000000000..66d742f539 --- /dev/null +++ b/configs/M5282EVB_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_M5282EVB=y diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig new file mode 100644 index 0000000000..d83e638c8c --- /dev/null +++ b/configs/M53017EVB_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_M53017EVB=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig new file mode 100644 index 0000000000..048d3a9ca9 --- /dev/null +++ b/configs/M5329AFEE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0" +CONFIG_M68K=y +CONFIG_TARGET_M5329EVB=y diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig new file mode 100644 index 0000000000..01e3d6a167 --- /dev/null +++ b/configs/M5329BFEE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" +CONFIG_M68K=y +CONFIG_TARGET_M5329EVB=y diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig new file mode 100644 index 0000000000..51a7b81d28 --- /dev/null +++ b/configs/M5373EVB_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" +CONFIG_M68K=y +CONFIG_TARGET_M5373EVB=y diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig new file mode 100644 index 0000000000..8f18bbea96 --- /dev/null +++ b/configs/M54418TWR_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" +CONFIG_M68K=y +CONFIG_TARGET_M54418TWR=y diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig new file mode 100644 index 0000000000..4b1c6c9e61 --- /dev/null +++ b/configs/M54418TWR_nand_mii_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000" +CONFIG_M68K=y +CONFIG_TARGET_M54418TWR=y diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig new file mode 100644 index 0000000000..72cc83c66f --- /dev/null +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" +CONFIG_M68K=y +CONFIG_TARGET_M54418TWR=y diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig new file mode 100644 index 0000000000..0bc929f8e5 --- /dev/null +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" +CONFIG_M68K=y +CONFIG_TARGET_M54418TWR=y diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig new file mode 100644 index 0000000000..93fe401252 --- /dev/null +++ b/configs/M54418TWR_serial_mii_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000" +CONFIG_M68K=y +CONFIG_TARGET_M54418TWR=y diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig new file mode 100644 index 0000000000..8f18bbea96 --- /dev/null +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" +CONFIG_M68K=y +CONFIG_TARGET_M54418TWR=y diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig new file mode 100644 index 0000000000..af02731bfe --- /dev/null +++ b/configs/M54451EVB_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000" +CONFIG_M68K=y +CONFIG_TARGET_M54451EVB=y diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig new file mode 100644 index 0000000000..4a3c87f57a --- /dev/null +++ b/configs/M54451EVB_stmicro_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000" +CONFIG_M68K=y +CONFIG_TARGET_M54451EVB=y diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig new file mode 100644 index 0000000000..b05a12e95d --- /dev/null +++ b/configs/M54455EVB_a66_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666" +CONFIG_M68K=y +CONFIG_TARGET_M54455EVB=y diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig new file mode 100644 index 0000000000..ffd34070cc --- /dev/null +++ b/configs/M54455EVB_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333" +CONFIG_M68K=y +CONFIG_TARGET_M54455EVB=y diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig new file mode 100644 index 0000000000..90cf787447 --- /dev/null +++ b/configs/M54455EVB_i66_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666" +CONFIG_M68K=y +CONFIG_TARGET_M54455EVB=y diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig new file mode 100644 index 0000000000..a3d69db995 --- /dev/null +++ b/configs/M54455EVB_intel_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333" +CONFIG_M68K=y +CONFIG_TARGET_M54455EVB=y diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig new file mode 100644 index 0000000000..cf33d0f0cc --- /dev/null +++ b/configs/M54455EVB_stm33_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333" +CONFIG_M68K=y +CONFIG_TARGET_M54455EVB=y diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig new file mode 100644 index 0000000000..28fd0ecc8c --- /dev/null +++ b/configs/M5475AFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64" +CONFIG_M68K=y +CONFIG_TARGET_M5475EVB=y diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig new file mode 100644 index 0000000000..329f3e3076 --- /dev/null +++ b/configs/M5475BFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" +CONFIG_M68K=y +CONFIG_TARGET_M5475EVB=y diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig new file mode 100644 index 0000000000..8dd75dbac6 --- /dev/null +++ b/configs/M5475CFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" +CONFIG_M68K=y +CONFIG_TARGET_M5475EVB=y diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig new file mode 100644 index 0000000000..a6288da897 --- /dev/null +++ b/configs/M5475DFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" +CONFIG_M68K=y +CONFIG_TARGET_M5475EVB=y diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig new file mode 100644 index 0000000000..19640a2e90 --- /dev/null +++ b/configs/M5475EFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" +CONFIG_M68K=y +CONFIG_TARGET_M5475EVB=y diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig new file mode 100644 index 0000000000..0201d38824 --- /dev/null +++ b/configs/M5475FFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" +CONFIG_M68K=y +CONFIG_TARGET_M5475EVB=y diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig new file mode 100644 index 0000000000..b8768684d6 --- /dev/null +++ b/configs/M5475GFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64" +CONFIG_M68K=y +CONFIG_TARGET_M5475EVB=y diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig new file mode 100644 index 0000000000..612218da38 --- /dev/null +++ b/configs/M5485AFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64" +CONFIG_M68K=y +CONFIG_TARGET_M5485EVB=y diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig new file mode 100644 index 0000000000..697feb050a --- /dev/null +++ b/configs/M5485BFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" +CONFIG_M68K=y +CONFIG_TARGET_M5485EVB=y diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig new file mode 100644 index 0000000000..46c0d08faa --- /dev/null +++ b/configs/M5485CFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" +CONFIG_M68K=y +CONFIG_TARGET_M5485EVB=y diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig new file mode 100644 index 0000000000..ad6248d73f --- /dev/null +++ b/configs/M5485DFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" +CONFIG_M68K=y +CONFIG_TARGET_M5485EVB=y diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig new file mode 100644 index 0000000000..5f27496896 --- /dev/null +++ b/configs/M5485EFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" +CONFIG_M68K=y +CONFIG_TARGET_M5485EVB=y diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig new file mode 100644 index 0000000000..b1da7438c7 --- /dev/null +++ b/configs/M5485FFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" +CONFIG_M68K=y +CONFIG_TARGET_M5485EVB=y diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig new file mode 100644 index 0000000000..578d24a9bb --- /dev/null +++ b/configs/M5485GFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64" +CONFIG_M68K=y +CONFIG_TARGET_M5485EVB=y diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig new file mode 100644 index 0000000000..c632055ed5 --- /dev/null +++ b/configs/M5485HFE_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO" +CONFIG_M68K=y +CONFIG_TARGET_M5485EVB=y diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig new file mode 100644 index 0000000000..304d890793 --- /dev/null +++ b/configs/MIP405T_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MIP405T" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_MIP405=y diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig new file mode 100644 index 0000000000..57004e8554 --- /dev/null +++ b/configs/MIP405_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_MIP405=y diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig new file mode 100644 index 0000000000..64717ecfa8 --- /dev/null +++ b/configs/MPC8308RDB_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8308RDB=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig new file mode 100644 index 0000000000..ca6c304525 --- /dev/null +++ b/configs/MPC8313ERDB_33_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8313ERDB=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig new file mode 100644 index 0000000000..974bdf90ae --- /dev/null +++ b/configs/MPC8313ERDB_66_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8313ERDB=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig new file mode 100644 index 0000000000..3a55931b01 --- /dev/null +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC83xx=y ++S:CONFIG_TARGET_MPC8313ERDB=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig new file mode 100644 index 0000000000..180316ba20 --- /dev/null +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC83xx=y ++S:CONFIG_TARGET_MPC8313ERDB=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig new file mode 100644 index 0000000000..ebebbedf0c --- /dev/null +++ b/configs/MPC8315ERDB_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8315ERDB=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig new file mode 100644 index 0000000000..7c03842bfa --- /dev/null +++ b/configs/MPC8323ERDB_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8323ERDB=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig new file mode 100644 index 0000000000..e1ba08deae --- /dev/null +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC832XEMDS=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig new file mode 100644 index 0000000000..55df0f6088 --- /dev/null +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC832XEMDS=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig new file mode 100644 index 0000000000..1ceee68ee2 --- /dev/null +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC832XEMDS=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig new file mode 100644 index 0000000000..ef67be5644 --- /dev/null +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC832XEMDS=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig new file mode 100644 index 0000000000..0398472534 --- /dev/null +++ b/configs/MPC832XEMDS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC832XEMDS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig new file mode 100644 index 0000000000..f6af218288 --- /dev/null +++ b/configs/MPC8349EMDS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349EMDS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig new file mode 100644 index 0000000000..f853309b87 --- /dev/null +++ b/configs/MPC8349ITXGP_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349ITX=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig new file mode 100644 index 0000000000..5321801a17 --- /dev/null +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349ITX=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig new file mode 100644 index 0000000000..83f25ae53d --- /dev/null +++ b/configs/MPC8349ITX_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349ITX=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig new file mode 100644 index 0000000000..d3be43ac9e --- /dev/null +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC837XEMDS=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig new file mode 100644 index 0000000000..d3b7c1d05c --- /dev/null +++ b/configs/MPC837XEMDS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC837XEMDS=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig new file mode 100644 index 0000000000..bb4411adea --- /dev/null +++ b/configs/MPC837XERDB_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC837XERDB=y diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig new file mode 100644 index 0000000000..45dc91aa5f --- /dev/null +++ b/configs/MPC8536DS_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8536DS=y diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig new file mode 100644 index 0000000000..4a9f0cd6bd --- /dev/null +++ b/configs/MPC8536DS_SDCARD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8536DS=y diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig new file mode 100644 index 0000000000..2d357e8d5a --- /dev/null +++ b/configs/MPC8536DS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8536DS=y diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig new file mode 100644 index 0000000000..62edc91747 --- /dev/null +++ b/configs/MPC8536DS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8536DS=y diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig new file mode 100644 index 0000000000..41af34927d --- /dev/null +++ b/configs/MPC8540ADS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8540ADS=y diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig new file mode 100644 index 0000000000..bc9c24630a --- /dev/null +++ b/configs/MPC8541CDS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8541CDS=y diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig new file mode 100644 index 0000000000..502fbfc588 --- /dev/null +++ b/configs/MPC8541CDS_legacy_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8541CDS=y diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig new file mode 100644 index 0000000000..faeaa948f4 --- /dev/null +++ b/configs/MPC8544DS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8544DS=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig new file mode 100644 index 0000000000..438ea85b94 --- /dev/null +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8548CDS=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig new file mode 100644 index 0000000000..ba52e9441a --- /dev/null +++ b/configs/MPC8548CDS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8548CDS=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig new file mode 100644 index 0000000000..e027b2f620 --- /dev/null +++ b/configs/MPC8548CDS_legacy_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8548CDS=y diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig new file mode 100644 index 0000000000..3bdbb0c2d1 --- /dev/null +++ b/configs/MPC8555CDS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8555CDS=y diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig new file mode 100644 index 0000000000..3040905dd0 --- /dev/null +++ b/configs/MPC8555CDS_legacy_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8555CDS=y diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig new file mode 100644 index 0000000000..aa84d28a66 --- /dev/null +++ b/configs/MPC8560ADS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8560ADS=y diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig new file mode 100644 index 0000000000..ac0ec8c501 --- /dev/null +++ b/configs/MPC8568MDS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8568MDS=y diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig new file mode 100644 index 0000000000..57301805bb --- /dev/null +++ b/configs/MPC8569MDS_ATM_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="ATM" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8569MDS=y diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig new file mode 100644 index 0000000000..81fb82a542 --- /dev/null +++ b/configs/MPC8569MDS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8569MDS=y diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig new file mode 100644 index 0000000000..9a26a59990 --- /dev/null +++ b/configs/MPC8572DS_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8572DS=y diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig new file mode 100644 index 0000000000..dde9eb2846 --- /dev/null +++ b/configs/MPC8572DS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_MPC8572DS=y diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig new file mode 100644 index 0000000000..f4e89515f7 --- /dev/null +++ b/configs/MPC8610HPCD_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC86xx=y +CONFIG_TARGET_MPC8610HPCD=y diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig new file mode 100644 index 0000000000..525fa06135 --- /dev/null +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT" +CONFIG_PPC=y +CONFIG_MPC86xx=y +CONFIG_TARGET_MPC8641HPCN=y diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig new file mode 100644 index 0000000000..6c117d5bb0 --- /dev/null +++ b/configs/MPC8641HPCN_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC86xx=y +CONFIG_TARGET_MPC8641HPCN=y diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig new file mode 100644 index 0000000000..c6fb7e65d0 --- /dev/null +++ b/configs/MSI_Primo73_defconfig @@ -0,0 +1,23 @@ +# The MSI Primo73 is an A20 based tablet, with 1G RAM, 16G NAND, +# 1024x600 TN LCD display, mono speaker, 0.3 MP front camera, 2.0 MP +# rear camera, 3000 mAh battery, gt911 touchscreen, mma8452 accelerometer +# and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons +# (both volume buttons are also connected to the UBOOT_SEL pin). The +# external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB +# OTG and 3.5mm headphone jack. More details are available at +# http://linux-sunxi.org/MSI_Primo73 +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" +CONFIG_FDTFILE="sun7i-a20-primo73.dtb" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER="PH8" +CONFIG_VIDEO_LCD_BL_EN="PH7" +CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_USB_KEYBOARD=n ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=384 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig new file mode 100644 index 0000000000..6657ad66c9 --- /dev/null +++ b/configs/MSI_Primo81_defconfig @@ -0,0 +1,30 @@ +# The MSI Primo81 is an A31s based tablet, with 1G RAM, 16G NAND, +# 1024x768 IPS LCD display, mono speaker, 0.3 MP front camera, 2.0 MP +# rear camera, 3500 mAh battery, gt911 touchscreen, mma8452 accelerometer +# and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons +# (both volume buttons are also connected to the UBOOT_SEL pin). The +# external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB +# OTG and 3.5mm headphone jack. More details are available at +# http://linux-sunxi.org/MSI_Primo81 + +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="" +CONFIG_FDTFILE="sun6i-a31s-primo81.dtb" +CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0" +CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y +CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27 +CONFIG_VIDEO_LCD_SSD2828_RESET="PA26" +CONFIG_VIDEO_LCD_SPI_CS="PH9" +CONFIG_VIDEO_LCD_SPI_SCLK="PH10" +CONFIG_VIDEO_LCD_SPI_MOSI="PH11" +CONFIG_VIDEO_LCD_SPI_MISO="PH12" +CONFIG_VIDEO_LCD_BL_EN="PA25" +CONFIG_VIDEO_LCD_BL_PWM="PH13" +CONFIG_USB_KEYBOARD=n ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_DRAM_CLK=360 ++S:CONFIG_DRAM_ZQ=122 +# Wifi power ++S:CONFIG_AXP221_DLDO1_VOLT=3300 diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig new file mode 100644 index 0000000000..653cb01b93 --- /dev/null +++ b/configs/Marsboard_A10_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-marsboard.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=360 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig new file mode 100644 index 0000000000..1a0a025bd9 --- /dev/null +++ b/configs/Mele_A1000_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-a1000.dtb" +CONFIG_VIDEO_VGA=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=360 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig new file mode 100644 index 0000000000..723a72a2ef --- /dev/null +++ b/configs/Mele_M3_defconfig @@ -0,0 +1,12 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-m3.dtb" +CONFIG_VIDEO_VGA=y ++S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++S:CONFIG_MMC0_CD_PIN="PH1" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=384 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig new file mode 100644 index 0000000000..2e1f80d509 --- /dev/null +++ b/configs/Mele_M5_defconfig @@ -0,0 +1,13 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,USB_EHCI,STATUSLED=234" +CONFIG_FDTFILE="sun7i-a20-m5.dtb" +CONFIG_VIDEO_HDMI=y ++S:CONFIG_MMC0_CD_PIN="PH1" ++S:CONFIG_USB1_VBUS_PIN="PH6" ++S:CONFIG_USB2_VBUS_PIN="PH3" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=122 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig new file mode 100644 index 0000000000..eaf9a7e349 --- /dev/null +++ b/configs/Mele_M9_defconfig @@ -0,0 +1,20 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" +CONFIG_FDTFILE="sun6i-a31-m9.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_DRAM_CLK=312 ++S:CONFIG_DRAM_ZQ=120 +# The Mele M9 uses 3.3V for general IO ++S:CONFIG_AXP221_DCDC1_VOLT=3300 +# Ethernet phy power ++S:CONFIG_AXP221_DLDO1_VOLT=3300 +# USB hub power ++S:CONFIG_AXP221_DLDO4_VOLT=3300 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN="PC27" +# No Vbus gpio for usb2 ++S:CONFIG_USB2_VBUS_PIN="" diff --git a/configs/MigoR_defconfig b/configs/MigoR_defconfig new file mode 100644 index 0000000000..dd79ff5414 --- /dev/null +++ b/configs/MigoR_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_MIGOR=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig new file mode 100644 index 0000000000..6aea77716d --- /dev/null +++ b/configs/Mini-X_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=360 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig new file mode 100644 index 0000000000..8eccf2679d --- /dev/null +++ b/configs/MiniFAP_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MINIFAP" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig new file mode 100644 index 0000000000..c63b5da484 --- /dev/null +++ b/configs/O2D300_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2D300=y diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig new file mode 100644 index 0000000000..49e60abcfe --- /dev/null +++ b/configs/O2DNT2_RAMBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2DNT2=y diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig new file mode 100644 index 0000000000..9df3b88895 --- /dev/null +++ b/configs/O2DNT2_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2DNT2=y diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig new file mode 100644 index 0000000000..f2d3663e39 --- /dev/null +++ b/configs/O2D_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2D=y diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig new file mode 100644 index 0000000000..84db574e95 --- /dev/null +++ b/configs/O2I_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2I=y diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig new file mode 100644 index 0000000000..12428debf1 --- /dev/null +++ b/configs/O2MNT_O2M110_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\"" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2MNT=y diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig new file mode 100644 index 0000000000..a56329a6f1 --- /dev/null +++ b/configs/O2MNT_O2M112_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\"" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2MNT=y diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig new file mode 100644 index 0000000000..03f54cace5 --- /dev/null +++ b/configs/O2MNT_O2M113_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\"" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2MNT=y diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig new file mode 100644 index 0000000000..23c4dc3c05 --- /dev/null +++ b/configs/O2MNT_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O2MNT=y diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig new file mode 100644 index 0000000000..1f28a43667 --- /dev/null +++ b/configs/O3DNT_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_O3DNT=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig new file mode 100644 index 0000000000..c441d9fc36 --- /dev/null +++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig new file mode 100644 index 0000000000..b13024d0f8 --- /dev/null +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig new file mode 100644 index 0000000000..197141a4c8 --- /dev/null +++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig new file mode 100644 index 0000000000..8739428441 --- /dev/null +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..944d52fd7b --- /dev/null +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig new file mode 100644 index 0000000000..2dae76c7b1 --- /dev/null +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig new file mode 100644 index 0000000000..7cb82ef137 --- /dev/null +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig new file mode 100644 index 0000000000..c3c30fa45a --- /dev/null +++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig new file mode 100644 index 0000000000..fdf0777511 --- /dev/null +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig new file mode 100644 index 0000000000..9769a2f25c --- /dev/null +++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig new file mode 100644 index 0000000000..8935503b39 --- /dev/null +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig new file mode 100644 index 0000000000..8d6ab188a7 --- /dev/null +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig new file mode 100644 index 0000000000..76499d911e --- /dev/null +++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig new file mode 100644 index 0000000000..869b1a460e --- /dev/null +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig new file mode 100644 index 0000000000..be6fe06bfb --- /dev/null +++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig new file mode 100644 index 0000000000..dd5277d8fd --- /dev/null +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig new file mode 100644 index 0000000000..90e278d3e8 --- /dev/null +++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig new file mode 100644 index 0000000000..ac2321809c --- /dev/null +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..f1900fece9 --- /dev/null +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig new file mode 100644 index 0000000000..e2a379d13e --- /dev/null +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig new file mode 100644 index 0000000000..1b24dba2cc --- /dev/null +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig new file mode 100644 index 0000000000..de34914eff --- /dev/null +++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig new file mode 100644 index 0000000000..012516496f --- /dev/null +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig new file mode 100644 index 0000000000..78221afbc0 --- /dev/null +++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig new file mode 100644 index 0000000000..a2386c7900 --- /dev/null +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig new file mode 100644 index 0000000000..dcb0847a01 --- /dev/null +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig new file mode 100644 index 0000000000..1cba9200e8 --- /dev/null +++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig new file mode 100644 index 0000000000..23dc027a83 --- /dev/null +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1010RDB=y diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..e2b625ea15 --- /dev/null +++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig new file mode 100644 index 0000000000..503ee0c6ea --- /dev/null +++ b/configs/P1020MBG-PC_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig new file mode 100644 index 0000000000..d34d3c873b --- /dev/null +++ b/configs/P1020MBG-PC_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig new file mode 100644 index 0000000000..cee84efe4f --- /dev/null +++ b/configs/P1020MBG-PC_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1020MBG" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig new file mode 100644 index 0000000000..c01de3a54a --- /dev/null +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..81593e1cd5 --- /dev/null +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig new file mode 100644 index 0000000000..93c0c71ca6 --- /dev/null +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig new file mode 100644 index 0000000000..2120a09787 --- /dev/null +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig new file mode 100644 index 0000000000..521398dec7 --- /dev/null +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig new file mode 100644 index 0000000000..4e3ed602d1 --- /dev/null +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig new file mode 100644 index 0000000000..d4642c4403 --- /dev/null +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig new file mode 100644 index 0000000000..a19a59ff37 --- /dev/null +++ b/configs/P1020RDB-PC_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig new file mode 100644 index 0000000000..199b3f202e --- /dev/null +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig new file mode 100644 index 0000000000..a5edd3bb83 --- /dev/null +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig new file mode 100644 index 0000000000..789b1bd5f6 --- /dev/null +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig new file mode 100644 index 0000000000..61f7a022e8 --- /dev/null +++ b/configs/P1020RDB-PD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..7f393f4e33 --- /dev/null +++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig new file mode 100644 index 0000000000..6892cc2aae --- /dev/null +++ b/configs/P1020UTM-PC_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig new file mode 100644 index 0000000000..3757de38bb --- /dev/null +++ b/configs/P1020UTM-PC_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig new file mode 100644 index 0000000000..4c28014f7d --- /dev/null +++ b/configs/P1020UTM-PC_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1020UTM" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig new file mode 100644 index 0000000000..285a0c4af0 --- /dev/null +++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..0f9b175842 --- /dev/null +++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig new file mode 100644 index 0000000000..e2345dd4b9 --- /dev/null +++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig new file mode 100644 index 0000000000..eae7d2da76 --- /dev/null +++ b/configs/P1021RDB-PC_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig new file mode 100644 index 0000000000..da4b17db12 --- /dev/null +++ b/configs/P1021RDB-PC_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig new file mode 100644 index 0000000000..ec729d8de0 --- /dev/null +++ b/configs/P1021RDB-PC_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig new file mode 100644 index 0000000000..98a3e23923 --- /dev/null +++ b/configs/P1021RDB-PC_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig new file mode 100644 index 0000000000..7557da2b0c --- /dev/null +++ b/configs/P1021RDB-PC_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig new file mode 100644 index 0000000000..d482617490 --- /dev/null +++ b/configs/P1022DS_36BIT_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1022DS=y diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..3f2a46c90f --- /dev/null +++ b/configs/P1022DS_36BIT_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1022DS=y diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig new file mode 100644 index 0000000000..47a39eec3f --- /dev/null +++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1022DS=y diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig new file mode 100644 index 0000000000..f2ff2d030b --- /dev/null +++ b/configs/P1022DS_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1022DS=y diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig new file mode 100644 index 0000000000..071280b0a3 --- /dev/null +++ b/configs/P1022DS_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1022DS=y diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig new file mode 100644 index 0000000000..47f21eab2e --- /dev/null +++ b/configs/P1022DS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1022DS=y diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig new file mode 100644 index 0000000000..a866f2467b --- /dev/null +++ b/configs/P1022DS_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1022DS=y diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig new file mode 100644 index 0000000000..d2953a4e99 --- /dev/null +++ b/configs/P1022DS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1022DS=y diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig new file mode 100644 index 0000000000..fc15e4bc4c --- /dev/null +++ b/configs/P1023RDB_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1023RDB=y diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig new file mode 100644 index 0000000000..687277feec --- /dev/null +++ b/configs/P1024RDB_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig new file mode 100644 index 0000000000..be4201462e --- /dev/null +++ b/configs/P1024RDB_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig new file mode 100644 index 0000000000..88504bf4b8 --- /dev/null +++ b/configs/P1024RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig new file mode 100644 index 0000000000..5def94279f --- /dev/null +++ b/configs/P1024RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig new file mode 100644 index 0000000000..89e88f217f --- /dev/null +++ b/configs/P1024RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig new file mode 100644 index 0000000000..6903fec05d --- /dev/null +++ b/configs/P1025RDB_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig new file mode 100644 index 0000000000..f07388a536 --- /dev/null +++ b/configs/P1025RDB_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig new file mode 100644 index 0000000000..1791ec420f --- /dev/null +++ b/configs/P1025RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig new file mode 100644 index 0000000000..774bbfe225 --- /dev/null +++ b/configs/P1025RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig new file mode 100644 index 0000000000..589e1740a0 --- /dev/null +++ b/configs/P1025RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig new file mode 100644 index 0000000000..cdfe13db1c --- /dev/null +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..a98ce43297 --- /dev/null +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig new file mode 100644 index 0000000000..14e53ba014 --- /dev/null +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig new file mode 100644 index 0000000000..8f0c994bdb --- /dev/null +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig new file mode 100644 index 0000000000..10b208a48b --- /dev/null +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" ++ST:CONFIG_PPC=y ++ST:CONFIG_MPC85xx=y ++ST:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig new file mode 100644 index 0000000000..6cb0e6e350 --- /dev/null +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig new file mode 100644 index 0000000000..769eb37ebb --- /dev/null +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig new file mode 100644 index 0000000000..3e46572009 --- /dev/null +++ b/configs/P2020RDB-PC_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_P2_RDB_PC=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig new file mode 100644 index 0000000000..4a4e076db7 --- /dev/null +++ b/configs/P2041RDB_NAND_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2041RDB=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig new file mode 100644 index 0000000000..af06581683 --- /dev/null +++ b/configs/P2041RDB_SDCARD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2041RDB=y diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..c49dcbfbd0 --- /dev/null +++ b/configs/P2041RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2041RDB=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig new file mode 100644 index 0000000000..ecba89af66 --- /dev/null +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2041RDB=y diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..53bd27137e --- /dev/null +++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2041RDB=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig new file mode 100644 index 0000000000..802b38d6df --- /dev/null +++ b/configs/P2041RDB_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2041RDB=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig new file mode 100644 index 0000000000..59340486b7 --- /dev/null +++ b/configs/P3041DS_NAND_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig new file mode 100644 index 0000000000..dacadaaf26 --- /dev/null +++ b/configs/P3041DS_SDCARD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..9850956b84 --- /dev/null +++ b/configs/P3041DS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig new file mode 100644 index 0000000000..0a71926093 --- /dev/null +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..5c14324c01 --- /dev/null +++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig new file mode 100644 index 0000000000..327765005e --- /dev/null +++ b/configs/P3041DS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig new file mode 100644 index 0000000000..99fbbf2722 --- /dev/null +++ b/configs/P4080DS_SDCARD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P4080DS=y diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..bae1da21c0 --- /dev/null +++ b/configs/P4080DS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P4080DS=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig new file mode 100644 index 0000000000..855319dfc3 --- /dev/null +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P4080DS=y diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..6240d730ee --- /dev/null +++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P4080DS=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig new file mode 100644 index 0000000000..9b5fc89ed2 --- /dev/null +++ b/configs/P4080DS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P4080DS=y diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig new file mode 100644 index 0000000000..6fe8446ee4 --- /dev/null +++ b/configs/P5020DS_NAND_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig new file mode 100644 index 0000000000..e19aa6efb9 --- /dev/null +++ b/configs/P5020DS_SDCARD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..30871d9887 --- /dev/null +++ b/configs/P5020DS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig new file mode 100644 index 0000000000..dbcc05661a --- /dev/null +++ b/configs/P5020DS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..dc191f7fd8 --- /dev/null +++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig new file mode 100644 index 0000000000..d1c5c722c0 --- /dev/null +++ b/configs/P5020DS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig new file mode 100644 index 0000000000..de3cd0664b --- /dev/null +++ b/configs/P5040DS_NAND_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig new file mode 100644 index 0000000000..f0ef285b1d --- /dev/null +++ b/configs/P5040DS_SDCARD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..8e21ca5895 --- /dev/null +++ b/configs/P5040DS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig new file mode 100644 index 0000000000..a2922f5a14 --- /dev/null +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig new file mode 100644 index 0000000000..38f3d589cd --- /dev/null +++ b/configs/P5040DS_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig new file mode 100644 index 0000000000..14ca871b44 --- /dev/null +++ b/configs/PATI_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_5xx=y +CONFIG_TARGET_PATI=y diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig new file mode 100644 index 0000000000..38b3acbb1f --- /dev/null +++ b/configs/PIP405_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_PIP405=y diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig new file mode 100644 index 0000000000..15477c481e --- /dev/null +++ b/configs/PLU405_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_PLU405=y diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig new file mode 100644 index 0000000000..78c5d393cd --- /dev/null +++ b/configs/PMC405DE_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_PMC405DE=y diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig new file mode 100644 index 0000000000..27869ac07b --- /dev/null +++ b/configs/PMC440_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_PMC440=y diff --git a/configs/T1024QDS_D4_SECURE_BOOT_defconfig b/configs/T1024QDS_D4_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..d86ae05603 --- /dev/null +++ b/configs/T1024QDS_D4_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig new file mode 100644 index 0000000000..acbbe43ac9 --- /dev/null +++ b/configs/T1024QDS_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig new file mode 100644 index 0000000000..82c6e194f5 --- /dev/null +++ b/configs/T1024QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..b932619689 --- /dev/null +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig new file mode 100644 index 0000000000..52aeac79b0 --- /dev/null +++ b/configs/T1024QDS_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig new file mode 100644 index 0000000000..94a76ba95a --- /dev/null +++ b/configs/T1024QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig new file mode 100644 index 0000000000..73d14ab6b2 --- /dev/null +++ b/configs/T1024RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig new file mode 100644 index 0000000000..3599f1dae9 --- /dev/null +++ b/configs/T1024RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..83772600a1 --- /dev/null +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig new file mode 100644 index 0000000000..c8ea98544a --- /dev/null +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig new file mode 100644 index 0000000000..e19e404bd1 --- /dev/null +++ b/configs/T1024RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1040QDS_D4_defconfig b/configs/T1040QDS_D4_defconfig new file mode 100644 index 0000000000..0684cb072e --- /dev/null +++ b/configs/T1040QDS_D4_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T1040QDS=y diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..f3f61ebcb6 --- /dev/null +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T1040QDS=y diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig new file mode 100644 index 0000000000..b8e1a3deef --- /dev/null +++ b/configs/T1040QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T1040QDS=y diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig new file mode 100644 index 0000000000..5fe34d8a3f --- /dev/null +++ b/configs/T1040RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig new file mode 100644 index 0000000000..08c3730718 --- /dev/null +++ b/configs/T1040RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..0b5ddaf46b --- /dev/null +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig new file mode 100644 index 0000000000..1a6170391c --- /dev/null +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig new file mode 100644 index 0000000000..072eab06b0 --- /dev/null +++ b/configs/T1040RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig new file mode 100644 index 0000000000..d1a1665b7c --- /dev/null +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig new file mode 100644 index 0000000000..2bf123dd30 --- /dev/null +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig new file mode 100644 index 0000000000..30d6d2dc88 --- /dev/null +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig new file mode 100644 index 0000000000..f8f63346db --- /dev/null +++ b/configs/T1042RDB_PI_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..c8dd5c2049 --- /dev/null +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig new file mode 100644 index 0000000000..85eceb9120 --- /dev/null +++ b/configs/T1042RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig new file mode 100644 index 0000000000..b75195a314 --- /dev/null +++ b/configs/T2080QDS_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig new file mode 100644 index 0000000000..6ed65dd53c --- /dev/null +++ b/configs/T2080QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..4f7d709fbe --- /dev/null +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig new file mode 100644 index 0000000000..a3b58d3bce --- /dev/null +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..105548697b --- /dev/null +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig new file mode 100644 index 0000000000..180d155e21 --- /dev/null +++ b/configs/T2080QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig new file mode 100644 index 0000000000..7c48f8f8ac --- /dev/null +++ b/configs/T2080RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XRDB=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig new file mode 100644 index 0000000000..31ca9a7387 --- /dev/null +++ b/configs/T2080RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XRDB=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..cee5370286 --- /dev/null +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T208XRDB=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig new file mode 100644 index 0000000000..bdddeae291 --- /dev/null +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XRDB=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..9bdf533b36 --- /dev/null +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T208XRDB=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig new file mode 100644 index 0000000000..f6ade166ef --- /dev/null +++ b/configs/T2080RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T208XRDB=y diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig new file mode 100644 index 0000000000..d3558c5668 --- /dev/null +++ b/configs/T2081QDS_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig new file mode 100644 index 0000000000..fc13d2caa5 --- /dev/null +++ b/configs/T2081QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig new file mode 100644 index 0000000000..e5ea3dce1b --- /dev/null +++ b/configs/T2081QDS_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..407af9212a --- /dev/null +++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T208XQDS=y diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig new file mode 100644 index 0000000000..93480a680e --- /dev/null +++ b/configs/T2081QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T208XQDS=y diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig new file mode 100644 index 0000000000..0a18424157 --- /dev/null +++ b/configs/T4160QDS_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig new file mode 100644 index 0000000000..de1b2c4669 --- /dev/null +++ b/configs/T4160QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..9fc209f8b8 --- /dev/null +++ b/configs/T4160QDS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4160QDS_SPIFLASH_defconfig b/configs/T4160QDS_SPIFLASH_defconfig new file mode 100644 index 0000000000..6146b00fd1 --- /dev/null +++ b/configs/T4160QDS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig new file mode 100644 index 0000000000..749f445708 --- /dev/null +++ b/configs/T4160QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig new file mode 100644 index 0000000000..34bd914779 --- /dev/null +++ b/configs/T4160RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240RDB=y diff --git a/configs/T4240EMU_defconfig b/configs/T4240EMU_defconfig new file mode 100644 index 0000000000..e95151b231 --- /dev/null +++ b/configs/T4240EMU_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240EMU=y diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig new file mode 100644 index 0000000000..65978ebe89 --- /dev/null +++ b/configs/T4240QDS_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig new file mode 100644 index 0000000000..4db1b80a68 --- /dev/null +++ b/configs/T4240QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..9cc7775168 --- /dev/null +++ b/configs/T4240QDS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4240QDS_SPIFLASH_defconfig b/configs/T4240QDS_SPIFLASH_defconfig new file mode 100644 index 0000000000..14dc48a0b8 --- /dev/null +++ b/configs/T4240QDS_SPIFLASH_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig new file mode 100644 index 0000000000..7c106552af --- /dev/null +++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig new file mode 100644 index 0000000000..80889e0b22 --- /dev/null +++ b/configs/T4240QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240QDS=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig new file mode 100644 index 0000000000..37b1b555d1 --- /dev/null +++ b/configs/T4240RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T4240RDB=y diff --git a/configs/TB5200_B_defconfig b/configs/TB5200_B_defconfig new file mode 100644 index 0000000000..00d06c9217 --- /dev/null +++ b/configs/TB5200_B_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TB5200=y diff --git a/configs/TB5200_defconfig b/configs/TB5200_defconfig new file mode 100644 index 0000000000..13d8e2dc7c --- /dev/null +++ b/configs/TB5200_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TB5200=y diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig new file mode 100644 index 0000000000..f54377e3e5 --- /dev/null +++ b/configs/TQM5200S_HIGHBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig new file mode 100644 index 0000000000..5d976ce1e1 --- /dev/null +++ b/configs/TQM5200S_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig new file mode 100644 index 0000000000..61c120a95a --- /dev/null +++ b/configs/TQM5200_B_HIGHBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig new file mode 100644 index 0000000000..ddc5d2cedf --- /dev/null +++ b/configs/TQM5200_B_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig new file mode 100644 index 0000000000..9c198c68ef --- /dev/null +++ b/configs/TQM5200_STK100_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig new file mode 100644 index 0000000000..1fe9682278 --- /dev/null +++ b/configs/TQM5200_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig new file mode 100644 index 0000000000..cacd3e25db --- /dev/null +++ b/configs/TQM823L_LCD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20" +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM823L=y diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig new file mode 100644 index 0000000000..5678bf2d8d --- /dev/null +++ b/configs/TQM823L_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM823L=y diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig new file mode 100644 index 0000000000..974bc912c0 --- /dev/null +++ b/configs/TQM823M_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM823M=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig new file mode 100644 index 0000000000..2cf89b4732 --- /dev/null +++ b/configs/TQM834x_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_TQM834X=y diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig new file mode 100644 index 0000000000..f3d5f4d48d --- /dev/null +++ b/configs/TQM850L_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM850L=y diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig new file mode 100644 index 0000000000..6052ada603 --- /dev/null +++ b/configs/TQM850M_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM850M=y diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig new file mode 100644 index 0000000000..b7d5891179 --- /dev/null +++ b/configs/TQM855L_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM855L=y diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig new file mode 100644 index 0000000000..367a70972f --- /dev/null +++ b/configs/TQM855M_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM855M=y diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig new file mode 100644 index 0000000000..0a215a7e25 --- /dev/null +++ b/configs/TQM860L_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM860L=y diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig new file mode 100644 index 0000000000..5c9a4f19c0 --- /dev/null +++ b/configs/TQM860M_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM860M=y diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig new file mode 100644 index 0000000000..24a290e549 --- /dev/null +++ b/configs/TQM862L_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM862L=y diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig new file mode 100644 index 0000000000..ca8dba180f --- /dev/null +++ b/configs/TQM862M_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM862M=y diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig new file mode 100644 index 0000000000..bcf039a661 --- /dev/null +++ b/configs/TQM866M_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM866M=y diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig new file mode 100644 index 0000000000..6a0268aa4f --- /dev/null +++ b/configs/TQM885D_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM885D=y diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig new file mode 100644 index 0000000000..be99da306d --- /dev/null +++ b/configs/TTTech_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01" +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM823L=y diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig new file mode 100644 index 0000000000..95d758eda7 --- /dev/null +++ b/configs/TWR-P1025_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P1_TWR=y diff --git a/configs/TZX-Q8-713B7_defconfig b/configs/TZX-Q8-713B7_defconfig new file mode 100644 index 0000000000..7b7b9ddf8e --- /dev/null +++ b/configs/TZX-Q8-713B7_defconfig @@ -0,0 +1,15 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" +CONFIG_FDTFILE="sun5i-a13-tzx-q8-713b7.dtb" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN="PG12" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="AXP0-0" +CONFIG_VIDEO_LCD_BL_EN="AXP0-1" +CONFIG_VIDEO_LCD_BL_PWM="PB2" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig new file mode 100644 index 0000000000..6aa8de0b50 --- /dev/null +++ b/configs/VCMA9_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_VCMA9=y diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig new file mode 100644 index 0000000000..b65515f2d3 --- /dev/null +++ b/configs/VOM405_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_VOM405=y diff --git a/configs/W7OLMC_defconfig b/configs/W7OLMC_defconfig new file mode 100644 index 0000000000..573427b9f5 --- /dev/null +++ b/configs/W7OLMC_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_W7OLMC=y diff --git a/configs/W7OLMG_defconfig b/configs/W7OLMG_defconfig new file mode 100644 index 0000000000..74101244c9 --- /dev/null +++ b/configs/W7OLMG_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_W7OLMG=y diff --git a/configs/a320evb_defconfig b/configs/a320evb_defconfig new file mode 100644 index 0000000000..5ebf5e6a71 --- /dev/null +++ b/configs/a320evb_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_A320EVB=y diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig new file mode 100644 index 0000000000..16218c0519 --- /dev/null +++ b/configs/a3m071_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_PPC=y ++S:CONFIG_MPC5xxx=y ++S:CONFIG_TARGET_A3M071=y diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig new file mode 100644 index 0000000000..ddc8d3f76e --- /dev/null +++ b/configs/a4m072_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_A4M072=y diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig new file mode 100644 index 0000000000..15f04f9540 --- /dev/null +++ b/configs/a4m2k_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="A4M2K" ++S:CONFIG_PPC=y ++S:CONFIG_MPC5xxx=y ++S:CONFIG_TARGET_A3M071=y diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig new file mode 100644 index 0000000000..37966320b4 --- /dev/null +++ b/configs/ac14xx_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC512X=y +CONFIG_TARGET_AC14XX=y diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig new file mode 100644 index 0000000000..26221ce4e0 --- /dev/null +++ b/configs/acadia_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_ACADIA=y diff --git a/configs/adp-ag101_defconfig b/configs/adp-ag101_defconfig new file mode 100644 index 0000000000..289115409f --- /dev/null +++ b/configs/adp-ag101_defconfig @@ -0,0 +1,2 @@ +CONFIG_NDS32=y +CONFIG_TARGET_ADP_AG101=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig new file mode 100644 index 0000000000..0a7a64cc16 --- /dev/null +++ b/configs/adp-ag101p_defconfig @@ -0,0 +1,2 @@ +CONFIG_NDS32=y +CONFIG_TARGET_ADP_AG101P=y diff --git a/configs/adp-ag102_defconfig b/configs/adp-ag102_defconfig new file mode 100644 index 0000000000..03f2241c56 --- /dev/null +++ b/configs/adp-ag102_defconfig @@ -0,0 +1,2 @@ +CONFIG_NDS32=y +CONFIG_TARGET_ADP_AG102=y diff --git a/configs/aev_defconfig b/configs/aev_defconfig new file mode 100644 index 0000000000..b2a9589b49 --- /dev/null +++ b/configs/aev_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_AEV=y diff --git a/configs/afeb9260_defconfig b/configs/afeb9260_defconfig new file mode 100644 index 0000000000..2616d2d027 --- /dev/null +++ b/configs/afeb9260_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_AFEB9260=y diff --git a/configs/alpr_defconfig b/configs/alpr_defconfig new file mode 100644 index 0000000000..9f613c84e9 --- /dev/null +++ b/configs/alpr_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_ALPR=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig new file mode 100644 index 0000000000..d722306d4d --- /dev/null +++ b/configs/alt_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_ALT=y diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig new file mode 100644 index 0000000000..b631c410dc --- /dev/null +++ b/configs/am335x_boneblack_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig new file mode 100644 index 0000000000..51bf370364 --- /dev/null +++ b/configs/am335x_boneblack_vboot_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_AM335X_EVM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig new file mode 100644 index 0000000000..2e5aeaa4dd --- /dev/null +++ b/configs/am335x_evm_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_CONS_INDEX=1 ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig new file mode 100644 index 0000000000..be901633ac --- /dev/null +++ b/configs/am335x_evm_nor_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_CONS_INDEX=1 ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_AM335X_EVM=y +CONFIG_NOR=y diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig new file mode 100644 index 0000000000..47ff6cdb16 --- /dev/null +++ b/configs/am335x_evm_norboot_defconfig @@ -0,0 +1,5 @@ +CONFIG_CONS_INDEX=1 +CONFIG_ARM=y +CONFIG_TARGET_AM335X_EVM=y +CONFIG_NOR=y +CONFIG_NOR_BOOT=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig new file mode 100644 index 0000000000..a6188ea726 --- /dev/null +++ b/configs/am335x_evm_spiboot_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT" +CONFIG_CONS_INDEX=1 ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig new file mode 100644 index 0000000000..352c1fb596 --- /dev/null +++ b/configs/am335x_evm_usbspl_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT" +CONFIG_CONS_INDEX=1 ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig new file mode 100644 index 0000000000..23f0a32d63 --- /dev/null +++ b/configs/am335x_igep0033_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_AM335X_IGEP0033=y diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig new file mode 100644 index 0000000000..cf9d8c7120 --- /dev/null +++ b/configs/am3517_crane_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_AM3517_CRANE=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig new file mode 100644 index 0000000000..2336f1ed82 --- /dev/null +++ b/configs/am3517_evm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_AM3517_EVM=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig new file mode 100644 index 0000000000..369f2a4c77 --- /dev/null +++ b/configs/am43xx_evm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_AM43XX_EVM=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig new file mode 100644 index 0000000000..281a21535b --- /dev/null +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_AM43XX_EVM=y diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig new file mode 100644 index 0000000000..ae2039cca5 --- /dev/null +++ b/configs/ap325rxa_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_AP325RXA=y diff --git a/configs/ap_sh4a_4a_defconfig b/configs/ap_sh4a_4a_defconfig new file mode 100644 index 0000000000..f76329b0b0 --- /dev/null +++ b/configs/ap_sh4a_4a_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_AP_SH4A_4A=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig new file mode 100644 index 0000000000..fc5e1e4d38 --- /dev/null +++ b/configs/apalis_t30_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA30=y ++S:CONFIG_TARGET_APALIS_T30=y +CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis" diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig new file mode 100644 index 0000000000..67effa1642 --- /dev/null +++ b/configs/apf27_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_APF27=y diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig new file mode 100644 index 0000000000..a47d6301c2 --- /dev/null +++ b/configs/apx4devkit_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_APX4DEVKIT=y diff --git a/configs/arcangel4-be_defconfig b/configs/arcangel4-be_defconfig new file mode 100644 index 0000000000..0c3ab4e4fc --- /dev/null +++ b/configs/arcangel4-be_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARC=y +CONFIG_TARGET_ARCANGEL4_BE=y +CONFIG_SYS_CLK_FREQ=70000000 diff --git a/configs/arcangel4_defconfig b/configs/arcangel4_defconfig new file mode 100644 index 0000000000..a63ef21de8 --- /dev/null +++ b/configs/arcangel4_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARC=y +CONFIG_TARGET_ARCANGEL4=y +CONFIG_SYS_CLK_FREQ=70000000 diff --git a/configs/arches_defconfig b/configs/arches_defconfig new file mode 100644 index 0000000000..18d0a140da --- /dev/null +++ b/configs/arches_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="ARCHES" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_CANYONLANDS=y diff --git a/configs/aria_defconfig b/configs/aria_defconfig new file mode 100644 index 0000000000..f7ebfa674c --- /dev/null +++ b/configs/aria_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC512X=y +CONFIG_TARGET_ARIA=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig new file mode 100644 index 0000000000..6541865b7c --- /dev/null +++ b/configs/aristainetos_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL" +CONFIG_ARM=y +CONFIG_TARGET_ARISTAINETOS=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig new file mode 100644 index 0000000000..22dc1f8a41 --- /dev/null +++ b/configs/armadillo-800eva_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_ARMADILLO_800EVA=y diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig new file mode 100644 index 0000000000..fc30508170 --- /dev/null +++ b/configs/arndale_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_ARNDALE=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale" diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig new file mode 100644 index 0000000000..0b341d6432 --- /dev/null +++ b/configs/aspenite_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_ASPENITE=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig new file mode 100644 index 0000000000..6807aee99b --- /dev/null +++ b/configs/astro_mcf5373l_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_ASTRO_MCF5373L=y diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig new file mode 100644 index 0000000000..95b5c2797b --- /dev/null +++ b/configs/at91rm9200ek_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_AT91RM9200EK=y diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig new file mode 100644 index 0000000000..5039ebc9b9 --- /dev/null +++ b/configs/at91rm9200ek_ram_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" +CONFIG_ARM=y +CONFIG_TARGET_AT91RM9200EK=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig new file mode 100644 index 0000000000..7f929c8376 --- /dev/null +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig new file mode 100644 index 0000000000..e2c32bf7c7 --- /dev/null +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig new file mode 100644 index 0000000000..1168cace31 --- /dev/null +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig new file mode 100644 index 0000000000..486eeb295f --- /dev/null +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9261EK=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig new file mode 100644 index 0000000000..5f42a90ca5 --- /dev/null +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9261EK=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig new file mode 100644 index 0000000000..4d7aa9064e --- /dev/null +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9261EK=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig new file mode 100644 index 0000000000..4dce54e5c6 --- /dev/null +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9263EK=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig new file mode 100644 index 0000000000..4dce54e5c6 --- /dev/null +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9263EK=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig new file mode 100644 index 0000000000..6f60daa9c7 --- /dev/null +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9263EK=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig new file mode 100644 index 0000000000..944c14dde0 --- /dev/null +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9263EK=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig new file mode 100644 index 0000000000..b54ef7f0ba --- /dev/null +++ b/configs/at91sam9263ek_norflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9263EK=y diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig new file mode 100644 index 0000000000..132102db3c --- /dev/null +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9261EK=y diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig new file mode 100644 index 0000000000..3dd3f9a817 --- /dev/null +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9261EK=y diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig new file mode 100644 index 0000000000..a2bd6df384 --- /dev/null +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9261EK=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig new file mode 100644 index 0000000000..1a4c505849 --- /dev/null +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig new file mode 100644 index 0000000000..cf35782ebb --- /dev/null +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig new file mode 100644 index 0000000000..1377ad91f4 --- /dev/null +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9g20ek_mmc_defconfig b/configs/at91sam9g20ek_mmc_defconfig new file mode 100644 index 0000000000..8cca2e575e --- /dev/null +++ b/configs/at91sam9g20ek_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_MMC" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig new file mode 100644 index 0000000000..cfe91273c6 --- /dev/null +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig new file mode 100644 index 0000000000..1681bc8b71 --- /dev/null +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9M10G45EK=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig new file mode 100644 index 0000000000..61ae56e452 --- /dev/null +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9M10G45EK=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig new file mode 100644 index 0000000000..71d16588f3 --- /dev/null +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9N12EK=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig new file mode 100644 index 0000000000..6f677b1744 --- /dev/null +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9N12EK=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig new file mode 100644 index 0000000000..7e898f0c43 --- /dev/null +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9N12EK=y diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig new file mode 100644 index 0000000000..90516e0c45 --- /dev/null +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9RLEK=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig new file mode 100644 index 0000000000..0e2edfd0e0 --- /dev/null +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9RLEK=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig new file mode 100644 index 0000000000..d00eed5876 --- /dev/null +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9X5EK=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig new file mode 100644 index 0000000000..64f7af9bab --- /dev/null +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9X5EK=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig new file mode 100644 index 0000000000..47cd1e013b --- /dev/null +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9X5EK=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig new file mode 100644 index 0000000000..1b7391e096 --- /dev/null +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9X5EK=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig new file mode 100644 index 0000000000..ccbccd43c8 --- /dev/null +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig new file mode 100644 index 0000000000..e8f4cc32c9 --- /dev/null +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig new file mode 100644 index 0000000000..49c5d78778 --- /dev/null +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_AT91SAM9260EK=y diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig new file mode 100644 index 0000000000..cd79990eac --- /dev/null +++ b/configs/atngw100_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_ATNGW100=y diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig new file mode 100644 index 0000000000..88b1de2a48 --- /dev/null +++ b/configs/atngw100mkii_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_ATNGW100MKII=y diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig new file mode 100644 index 0000000000..d6e9a77e96 --- /dev/null +++ b/configs/atstk1002_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_ATSTK1002=y diff --git a/configs/atstk1003_defconfig b/configs/atstk1003_defconfig new file mode 100644 index 0000000000..b704532dbf --- /dev/null +++ b/configs/atstk1003_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_ATSTK1003=y diff --git a/configs/atstk1004_defconfig b/configs/atstk1004_defconfig new file mode 100644 index 0000000000..76502549c1 --- /dev/null +++ b/configs/atstk1004_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_ATSTK1004=y diff --git a/configs/atstk1006_defconfig b/configs/atstk1006_defconfig new file mode 100644 index 0000000000..54beb0b894 --- /dev/null +++ b/configs/atstk1006_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_ATSTK1006=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig new file mode 100644 index 0000000000..076ad0fe8d --- /dev/null +++ b/configs/axm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TAURUS=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig new file mode 100644 index 0000000000..5c0ca11fa5 --- /dev/null +++ b/configs/axs101_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARC=y +CONFIG_TARGET_AXS101=y +CONFIG_SYS_CLK_FREQ=750000000 \ No newline at end of file diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig new file mode 100644 index 0000000000..400906d377 --- /dev/null +++ b/configs/ba10_tv_box_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb" +CONFIG_USB2_VBUS_PIN="PH12" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=384 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/balloon3_defconfig b/configs/balloon3_defconfig new file mode 100644 index 0000000000..a1f4adbb1b --- /dev/null +++ b/configs/balloon3_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_BALLOON3=y diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig new file mode 100644 index 0000000000..1d66807df8 --- /dev/null +++ b/configs/bamboo_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_BAMBOO=y diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig new file mode 100644 index 0000000000..f8c9f0352a --- /dev/null +++ b/configs/bcm11130_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0" +CONFIG_ARM=y +CONFIG_TARGET_BCM28155_AP=y diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig new file mode 100644 index 0000000000..39cb709ff4 --- /dev/null +++ b/configs/bcm11130_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_ARM=y +CONFIG_TARGET_BCM28155_AP=y diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig new file mode 100644 index 0000000000..0a1c592472 --- /dev/null +++ b/configs/bcm28155_ap_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_BCM28155_AP=y diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig new file mode 100644 index 0000000000..94b791c150 --- /dev/null +++ b/configs/bcm28155_w1d_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC" +CONFIG_ARM=y +CONFIG_TARGET_BCM28155_AP=y diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig new file mode 100644 index 0000000000..6f5c154c44 --- /dev/null +++ b/configs/bcm911360_entphn-ns_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig new file mode 100644 index 0000000000..37b584642f --- /dev/null +++ b/configs/bcm911360_entphn_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig new file mode 100644 index 0000000000..527e4072c9 --- /dev/null +++ b/configs/bcm911360k_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig new file mode 100644 index 0000000000..0e3aaa779c --- /dev/null +++ b/configs/bcm958300k-ns_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig new file mode 100644 index 0000000000..527e4072c9 --- /dev/null +++ b/configs/bcm958300k_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig new file mode 100644 index 0000000000..527e4072c9 --- /dev/null +++ b/configs/bcm958305k_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig new file mode 100644 index 0000000000..7c86300968 --- /dev/null +++ b/configs/bcm958622hr_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000" +CONFIG_ARM=y +CONFIG_TARGET_BCMNSP=y diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig new file mode 100644 index 0000000000..26b145d30a --- /dev/null +++ b/configs/bct-brettl2_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BCT_BRETTL2=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig new file mode 100644 index 0000000000..872ab63bdd --- /dev/null +++ b/configs/beagle_x15_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_BEAGLE_X15=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig new file mode 100644 index 0000000000..ab615a83d7 --- /dev/null +++ b/configs/beaver_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA30=y ++S:CONFIG_TARGET_BEAVER=y +CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver" diff --git a/configs/bf506f-ezkit_defconfig b/configs/bf506f-ezkit_defconfig new file mode 100644 index 0000000000..f164e06b54 --- /dev/null +++ b/configs/bf506f-ezkit_defconfig @@ -0,0 +1,5 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF506F_EZKIT=y +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig new file mode 100644 index 0000000000..fb35ad023d --- /dev/null +++ b/configs/bf518f-ezbrd_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF518F_EZBRD=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf525-ucr2_defconfig b/configs/bf525-ucr2_defconfig new file mode 100644 index 0000000000..692e006fc5 --- /dev/null +++ b/configs/bf525-ucr2_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF525_UCR2=y diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig new file mode 100644 index 0000000000..da06d3ad6e --- /dev/null +++ b/configs/bf526-ezbrd_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF526_EZBRD=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig new file mode 100644 index 0000000000..47f53c9d81 --- /dev/null +++ b/configs/bf527-ad7160-eval_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF527_AD7160_EVAL=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig new file mode 100644 index 0000000000..e250e10354 --- /dev/null +++ b/configs/bf527-ezkit-v2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1" +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF527_EZKIT=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig new file mode 100644 index 0000000000..69f6ef781b --- /dev/null +++ b/configs/bf527-ezkit_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF527_EZKIT=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig new file mode 100644 index 0000000000..57f47e9fc8 --- /dev/null +++ b/configs/bf527-sdp_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF527_SDP=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig new file mode 100644 index 0000000000..57f8da1475 --- /dev/null +++ b/configs/bf533-ezkit_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF533_EZKIT=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig new file mode 100644 index 0000000000..1bcf3d319a --- /dev/null +++ b/configs/bf533-stamp_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF533_STAMP=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig new file mode 100644 index 0000000000..e76118fbd3 --- /dev/null +++ b/configs/bf537-minotaur_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF537_MINOTAUR=y diff --git a/configs/bf537-pnav_defconfig b/configs/bf537-pnav_defconfig new file mode 100644 index 0000000000..ba5eaaa392 --- /dev/null +++ b/configs/bf537-pnav_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF537_PNAV=y diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig new file mode 100644 index 0000000000..61ac0e7d0e --- /dev/null +++ b/configs/bf537-srv1_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF537_SRV1=y diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig new file mode 100644 index 0000000000..9b9a92f13f --- /dev/null +++ b/configs/bf537-stamp_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF537_STAMP=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig new file mode 100644 index 0000000000..1892151db0 --- /dev/null +++ b/configs/bf538f-ezkit_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF538F_EZKIT=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig new file mode 100644 index 0000000000..52369849aa --- /dev/null +++ b/configs/bf548-ezkit_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF548_EZKIT=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig new file mode 100644 index 0000000000..098f31fb55 --- /dev/null +++ b/configs/bf561-acvilon_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF561_ACVILON=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig new file mode 100644 index 0000000000..5665288316 --- /dev/null +++ b/configs/bf561-ezkit_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF561_EZKIT=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig new file mode 100644 index 0000000000..2bfb6a54bc --- /dev/null +++ b/configs/bf609-ezkit_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BF609_EZKIT=y diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig new file mode 100644 index 0000000000..b8c8352f38 --- /dev/null +++ b/configs/bg0900_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_BG0900=y diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig new file mode 100644 index 0000000000..d531ffcd09 --- /dev/null +++ b/configs/blackstamp_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BLACKSTAMP=y diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig new file mode 100644 index 0000000000..1ec2fa9ec8 --- /dev/null +++ b/configs/blackvme_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BLACKVME=y diff --git a/configs/br4_defconfig b/configs/br4_defconfig new file mode 100644 index 0000000000..5655d54b04 --- /dev/null +++ b/configs/br4_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_BR4=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig new file mode 100644 index 0000000000..65ea4d1f7c --- /dev/null +++ b/configs/bubinga_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_BUBINGA=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig new file mode 100644 index 0000000000..6e4a389a93 --- /dev/null +++ b/configs/caddy2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="CADDY2" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_VME8349=y diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig new file mode 100644 index 0000000000..02d391203b --- /dev/null +++ b/configs/calimain_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_CALIMAIN=y diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig new file mode 100644 index 0000000000..d3de17b944 --- /dev/null +++ b/configs/cam5200_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig new file mode 100644 index 0000000000..a375e1313b --- /dev/null +++ b/configs/cam5200_niosflash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/cam_enc_4xx_defconfig b/configs/cam_enc_4xx_defconfig new file mode 100644 index 0000000000..dfdda82f0a --- /dev/null +++ b/configs/cam_enc_4xx_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_DAVINCI=y ++S:CONFIG_TARGET_CAM_ENC_4XX=y diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig new file mode 100644 index 0000000000..86ffbd2aa5 --- /dev/null +++ b/configs/canmb_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_CANMB=y diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig new file mode 100644 index 0000000000..09b9ab9330 --- /dev/null +++ b/configs/canyonlands_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="CANYONLANDS" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_CANYONLANDS=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig new file mode 100644 index 0000000000..4466e98ac8 --- /dev/null +++ b/configs/cardhu_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA30=y ++S:CONFIG_TARGET_CARDHU=y +CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu" diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig new file mode 100644 index 0000000000..4eba4bea6d --- /dev/null +++ b/configs/cgtqmx6qeval_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" +CONFIG_ARM=y +CONFIG_TARGET_CGTQMX6EVAL=y diff --git a/configs/charon_defconfig b/configs/charon_defconfig new file mode 100644 index 0000000000..1dd3f5d58b --- /dev/null +++ b/configs/charon_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_CHARON=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig new file mode 100644 index 0000000000..2f0c714e59 --- /dev/null +++ b/configs/chromebook_link_defconfig @@ -0,0 +1,11 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CHROMEBOOK_LINK=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" +CONFIG_HAVE_MRC=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/configs/cm-bf527_defconfig b/configs/cm-bf527_defconfig new file mode 100644 index 0000000000..a6830b54fd --- /dev/null +++ b/configs/cm-bf527_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_CM_BF527=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig new file mode 100644 index 0000000000..b9508ae297 --- /dev/null +++ b/configs/cm-bf533_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_CM_BF533=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/cm-bf537e_defconfig b/configs/cm-bf537e_defconfig new file mode 100644 index 0000000000..a44eab7f0d --- /dev/null +++ b/configs/cm-bf537e_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_CM_BF537E=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/cm-bf537u_defconfig b/configs/cm-bf537u_defconfig new file mode 100644 index 0000000000..29c33b9514 --- /dev/null +++ b/configs/cm-bf537u_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_CM_BF537U=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig new file mode 100644 index 0000000000..525f2e7f37 --- /dev/null +++ b/configs/cm-bf548_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_CM_BF548=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig new file mode 100644 index 0000000000..062bfeb6dc --- /dev/null +++ b/configs/cm-bf561_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_CM_BF561=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/cm4008_defconfig b/configs/cm4008_defconfig new file mode 100644 index 0000000000..487589d4a3 --- /dev/null +++ b/configs/cm4008_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_CM4008=y diff --git a/configs/cm41xx_defconfig b/configs/cm41xx_defconfig new file mode 100644 index 0000000000..15e9362397 --- /dev/null +++ b/configs/cm41xx_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_CM41XX=y diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig new file mode 100644 index 0000000000..8f5dd3c3e7 --- /dev/null +++ b/configs/cm5200_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_CM5200=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig new file mode 100644 index 0000000000..3c0d64fecb --- /dev/null +++ b/configs/cm_fx6_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_CM_FX6=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig new file mode 100644 index 0000000000..5ff4f9c4a5 --- /dev/null +++ b/configs/cm_t335_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_CM_T335=y diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig new file mode 100644 index 0000000000..4000d2c75d --- /dev/null +++ b/configs/cm_t3517_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=n ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_CM_T3517=y diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig new file mode 100644 index 0000000000..2bb616fb90 --- /dev/null +++ b/configs/cm_t35_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_CM_T35=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig new file mode 100644 index 0000000000..32efaa233a --- /dev/null +++ b/configs/cm_t54_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_CM_T54=y diff --git a/configs/cmi_mpc5xx_defconfig b/configs/cmi_mpc5xx_defconfig new file mode 100644 index 0000000000..5c855b137b --- /dev/null +++ b/configs/cmi_mpc5xx_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_5xx=y +CONFIG_TARGET_CMI_MPC5XX=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig new file mode 100644 index 0000000000..dc1552d2c1 --- /dev/null +++ b/configs/cobra5272_defconfig @@ -0,0 +1,2 @@ +CONFIG_M68K=y +CONFIG_TARGET_COBRA5272=y diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig new file mode 100644 index 0000000000..c8faf0b309 --- /dev/null +++ b/configs/colibri_pxa270_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_PXA270=y diff --git a/configs/colibri_t20_iris_defconfig b/configs/colibri_t20_iris_defconfig new file mode 100644 index 0000000000..b76f78bba5 --- /dev/null +++ b/configs/colibri_t20_iris_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_COLIBRI_T20_IRIS=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris" diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig new file mode 100644 index 0000000000..b955303070 --- /dev/null +++ b/configs/colibri_t30_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA30=y ++S:CONFIG_TARGET_COLIBRI_T30=y +CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri" diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig new file mode 100644 index 0000000000..661e85cadd --- /dev/null +++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_CONTROLCENTERD=y diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig new file mode 100644 index 0000000000..76ab9d36c3 --- /dev/null +++ b/configs/controlcenterd_36BIT_SDCARD_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_CONTROLCENTERD=y diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig new file mode 100644 index 0000000000..c8695abfec --- /dev/null +++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig @@ -0,0 +1,5 @@ +CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_CONTROLCENTERD=y +# CONFIG_CMD_BOOTM is not set diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig new file mode 100644 index 0000000000..730b96e551 --- /dev/null +++ b/configs/controlcenterd_TRAILBLAZER_defconfig @@ -0,0 +1,5 @@ +CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_CONTROLCENTERD=y +# CONFIG_CMD_BOOTM is not set diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig new file mode 100644 index 0000000000..3cc034a98b --- /dev/null +++ b/configs/coreboot-x86_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000" +CONFIG_X86=y +CONFIG_TARGET_COREBOOT=y +CONFIG_OF_CONTROL=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig new file mode 100644 index 0000000000..5d60847523 --- /dev/null +++ b/configs/corvus_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_CORVUS=y diff --git a/configs/cpu9260_128M_defconfig b/configs/cpu9260_128M_defconfig new file mode 100644 index 0000000000..86fc6bd7c5 --- /dev/null +++ b/configs/cpu9260_128M_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M" +CONFIG_ARM=y +CONFIG_TARGET_CPU9260=y diff --git a/configs/cpu9260_defconfig b/configs/cpu9260_defconfig new file mode 100644 index 0000000000..10299e3bde --- /dev/null +++ b/configs/cpu9260_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CPU9260" +CONFIG_ARM=y +CONFIG_TARGET_CPU9260=y diff --git a/configs/cpu9260_nand_128M_defconfig b/configs/cpu9260_nand_128M_defconfig new file mode 100644 index 0000000000..e582a15ce4 --- /dev/null +++ b/configs/cpu9260_nand_128M_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M,NANDBOOT" +CONFIG_ARM=y +CONFIG_TARGET_CPU9260=y diff --git a/configs/cpu9260_nand_defconfig b/configs/cpu9260_nand_defconfig new file mode 100644 index 0000000000..40988cdf2a --- /dev/null +++ b/configs/cpu9260_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CPU9260,NANDBOOT" +CONFIG_ARM=y +CONFIG_TARGET_CPU9260=y diff --git a/configs/cpu9G20_128M_defconfig b/configs/cpu9G20_128M_defconfig new file mode 100644 index 0000000000..4c28d252f9 --- /dev/null +++ b/configs/cpu9G20_128M_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M" +CONFIG_ARM=y +CONFIG_TARGET_CPU9260=y diff --git a/configs/cpu9G20_defconfig b/configs/cpu9G20_defconfig new file mode 100644 index 0000000000..468b2c8c9b --- /dev/null +++ b/configs/cpu9G20_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CPU9G20" +CONFIG_ARM=y +CONFIG_TARGET_CPU9260=y diff --git a/configs/cpu9G20_nand_128M_defconfig b/configs/cpu9G20_nand_128M_defconfig new file mode 100644 index 0000000000..a74df9d124 --- /dev/null +++ b/configs/cpu9G20_nand_128M_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M,NANDBOOT" +CONFIG_ARM=y +CONFIG_TARGET_CPU9260=y diff --git a/configs/cpu9G20_nand_defconfig b/configs/cpu9G20_nand_defconfig new file mode 100644 index 0000000000..11cc276838 --- /dev/null +++ b/configs/cpu9G20_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,NANDBOOT" +CONFIG_ARM=y +CONFIG_TARGET_CPU9260=y diff --git a/configs/cpuat91_defconfig b/configs/cpuat91_defconfig new file mode 100644 index 0000000000..d25bd3ae78 --- /dev/null +++ b/configs/cpuat91_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_CPUAT91=y diff --git a/configs/cpuat91_ram_defconfig b/configs/cpuat91_ram_defconfig new file mode 100644 index 0000000000..f5b722dd4c --- /dev/null +++ b/configs/cpuat91_ram_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" +CONFIG_ARM=y +CONFIG_TARGET_CPUAT91=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig new file mode 100644 index 0000000000..ce905539f9 --- /dev/null +++ b/configs/crownbay_defconfig @@ -0,0 +1,6 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CROWNBAY=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="crownbay" diff --git a/configs/csb272_defconfig b/configs/csb272_defconfig new file mode 100644 index 0000000000..8ccd6452d6 --- /dev/null +++ b/configs/csb272_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_CSB272=y diff --git a/configs/csb472_defconfig b/configs/csb472_defconfig new file mode 100644 index 0000000000..81a0cf1298 --- /dev/null +++ b/configs/csb472_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_CSB472=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig new file mode 100644 index 0000000000..c459f4de23 --- /dev/null +++ b/configs/d2net_v2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NET2BIG_V2=y diff --git a/configs/da830evm_defconfig b/configs/da830evm_defconfig new file mode 100644 index 0000000000..d27cdb083d --- /dev/null +++ b/configs/da830evm_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DA830EVM=y diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig new file mode 100644 index 0000000000..a79a0a8c42 --- /dev/null +++ b/configs/da850_am18xxevm_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_DAVINCI=y ++S:CONFIG_TARGET_DA850EVM=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig new file mode 100644 index 0000000000..afdce5ed25 --- /dev/null +++ b/configs/da850evm_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_DAVINCI=y ++S:CONFIG_TARGET_DA850EVM=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig new file mode 100644 index 0000000000..25c303c847 --- /dev/null +++ b/configs/da850evm_direct_nor_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT" +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DA850EVM=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig new file mode 100644 index 0000000000..f704c75afa --- /dev/null +++ b/configs/dalmore_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA114=y ++S:CONFIG_TARGET_DALMORE=y +CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore" diff --git a/configs/davinci_dm355evm_defconfig b/configs/davinci_dm355evm_defconfig new file mode 100644 index 0000000000..d3a03b216c --- /dev/null +++ b/configs/davinci_dm355evm_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_DM355EVM=y diff --git a/configs/davinci_dm355leopard_defconfig b/configs/davinci_dm355leopard_defconfig new file mode 100644 index 0000000000..875c0b5e5d --- /dev/null +++ b/configs/davinci_dm355leopard_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_DM355LEOPARD=y diff --git a/configs/davinci_dm365evm_defconfig b/configs/davinci_dm365evm_defconfig new file mode 100644 index 0000000000..f841fd941d --- /dev/null +++ b/configs/davinci_dm365evm_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_DM365EVM=y diff --git a/configs/davinci_dm6467Tevm_defconfig b/configs/davinci_dm6467Tevm_defconfig new file mode 100644 index 0000000000..4523d4a0d0 --- /dev/null +++ b/configs/davinci_dm6467Tevm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000" +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_DM6467EVM=y diff --git a/configs/davinci_dm6467evm_defconfig b/configs/davinci_dm6467evm_defconfig new file mode 100644 index 0000000000..5208257029 --- /dev/null +++ b/configs/davinci_dm6467evm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000" +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_DM6467EVM=y diff --git a/configs/davinci_dvevm_defconfig b/configs/davinci_dvevm_defconfig new file mode 100644 index 0000000000..74e55b97d1 --- /dev/null +++ b/configs/davinci_dvevm_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_DVEVM=y diff --git a/configs/davinci_schmoogie_defconfig b/configs/davinci_schmoogie_defconfig new file mode 100644 index 0000000000..64ed2c1fef --- /dev/null +++ b/configs/davinci_schmoogie_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_SCHMOOGIE=y diff --git a/configs/davinci_sffsdr_defconfig b/configs/davinci_sffsdr_defconfig new file mode 100644 index 0000000000..9eb0f07b46 --- /dev/null +++ b/configs/davinci_sffsdr_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_SFFSDR=y diff --git a/configs/davinci_sonata_defconfig b/configs/davinci_sonata_defconfig new file mode 100644 index 0000000000..d8f0f7724a --- /dev/null +++ b/configs/davinci_sonata_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_DAVINCI_SONATA=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig new file mode 100644 index 0000000000..7aa216c47d --- /dev/null +++ b/configs/db-mv784mp-gp_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_DB_MV784MP_GP=y diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig new file mode 100644 index 0000000000..aa4d338d43 --- /dev/null +++ b/configs/dbau1000_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="DBAU1000" +CONFIG_MIPS=y +CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_BIG_ENDIAN=y diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig new file mode 100644 index 0000000000..aac9f032b0 --- /dev/null +++ b/configs/dbau1100_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_DBAU1100=y diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig new file mode 100644 index 0000000000..d96de13ff9 --- /dev/null +++ b/configs/dbau1500_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_DBAU1500=y diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig new file mode 100644 index 0000000000..a2dfe18c78 --- /dev/null +++ b/configs/dbau1550_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_DBAU1550=y diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig new file mode 100644 index 0000000000..767326f6d4 --- /dev/null +++ b/configs/dbau1550_el_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_DBAU1550=y diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig new file mode 100644 index 0000000000..7f82d7df8b --- /dev/null +++ b/configs/devconcenter_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_INTIP=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig new file mode 100644 index 0000000000..ba990bc67b --- /dev/null +++ b/configs/devkit3250_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_DEVKIT3250=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig new file mode 100644 index 0000000000..578ae74bba --- /dev/null +++ b/configs/devkit8000_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_DEVKIT8000=y diff --git a/configs/dig297_defconfig b/configs/dig297_defconfig new file mode 100644 index 0000000000..95bc353926 --- /dev/null +++ b/configs/dig297_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_OMAP34XX=y +CONFIG_TARGET_DIG297=y diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig new file mode 100644 index 0000000000..a1e765bfd3 --- /dev/null +++ b/configs/digsy_mtc_RAMBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_DIGSY_MTC=y diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig new file mode 100644 index 0000000000..666c5c8971 --- /dev/null +++ b/configs/digsy_mtc_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_DIGSY_MTC=y diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig new file mode 100644 index 0000000000..d356174af5 --- /dev/null +++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_DIGSY_MTC=y diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig new file mode 100644 index 0000000000..f66f86f856 --- /dev/null +++ b/configs/digsy_mtc_rev5_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_DIGSY_MTC=y diff --git a/configs/dkb_defconfig b/configs/dkb_defconfig new file mode 100644 index 0000000000..0be9578f4f --- /dev/null +++ b/configs/dkb_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_DKB=y diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig new file mode 100644 index 0000000000..1d2a5718b0 --- /dev/null +++ b/configs/dlvision-10g_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_DLVISION_10G=y diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig new file mode 100644 index 0000000000..c0317dcf09 --- /dev/null +++ b/configs/dlvision_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_DLVISION=y diff --git a/configs/dnp5370_defconfig b/configs/dnp5370_defconfig new file mode 100644 index 0000000000..0c00087631 --- /dev/null +++ b/configs/dnp5370_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_DNP5370=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig new file mode 100644 index 0000000000..cc4a03b117 --- /dev/null +++ b/configs/dns325_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_DNS325=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig new file mode 100644 index 0000000000..b773cdeff4 --- /dev/null +++ b/configs/dockstar_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_DOCKSTAR=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig new file mode 100644 index 0000000000..297c6b5879 --- /dev/null +++ b/configs/dra7xx_evm_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_DRA7XX_EVM=y diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig new file mode 100644 index 0000000000..92417f267b --- /dev/null +++ b/configs/dra7xx_evm_qspiboot_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_DRA7XX_EVM=y diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig new file mode 100644 index 0000000000..3551317a14 --- /dev/null +++ b/configs/dra7xx_evm_uart3_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPL_YMODEM_SUPPORT" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_DRA7XX_EVM=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig new file mode 100644 index 0000000000..18def0b503 --- /dev/null +++ b/configs/draco_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_DRACO=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig new file mode 100644 index 0000000000..45113c881f --- /dev/null +++ b/configs/dreamplug_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_DREAMPLUG=y diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig new file mode 100644 index 0000000000..85918458e4 --- /dev/null +++ b/configs/duovero_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP44XX=y ++S:CONFIG_TARGET_DUOVERO=y diff --git a/configs/dxr2_defconfig b/configs/dxr2_defconfig new file mode 100644 index 0000000000..15f11810f2 --- /dev/null +++ b/configs/dxr2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_DXR2=y diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig new file mode 100644 index 0000000000..93676cd3f9 --- /dev/null +++ b/configs/ea20_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_EA20=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig new file mode 100644 index 0000000000..f69aa539e2 --- /dev/null +++ b/configs/eb_cpu5282_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400" +CONFIG_M68K=y +CONFIG_TARGET_EB_CPU5282=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig new file mode 100644 index 0000000000..b590f25bb1 --- /dev/null +++ b/configs/eb_cpu5282_internal_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418" +CONFIG_M68K=y +CONFIG_TARGET_EB_CPU5282=y diff --git a/configs/eb_cpux9k2_defconfig b/configs/eb_cpux9k2_defconfig new file mode 100644 index 0000000000..5f0ab44f45 --- /dev/null +++ b/configs/eb_cpux9k2_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_EB_CPUX9K2=y diff --git a/configs/eb_cpux9k2_ram_defconfig b/configs/eb_cpux9k2_ram_defconfig new file mode 100644 index 0000000000..c6e8b71773 --- /dev/null +++ b/configs/eb_cpux9k2_ram_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" +CONFIG_ARM=y +CONFIG_TARGET_EB_CPUX9K2=y diff --git a/configs/ebony_defconfig b/configs/ebony_defconfig new file mode 100644 index 0000000000..db93555b9e --- /dev/null +++ b/configs/ebony_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_EBONY=y diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig new file mode 100644 index 0000000000..e45bdadf3f --- /dev/null +++ b/configs/eco5pk_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_ECO5PK=y diff --git a/configs/ecovec_defconfig b/configs/ecovec_defconfig new file mode 100644 index 0000000000..57771e4123 --- /dev/null +++ b/configs/ecovec_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_ECOVEC=y diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig new file mode 100644 index 0000000000..e92daf633b --- /dev/null +++ b/configs/edb9315a_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a" +CONFIG_ARM=y +CONFIG_TARGET_EDB93XX=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig new file mode 100644 index 0000000000..3b1a6c193a --- /dev/null +++ b/configs/edminiv2_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ORION5X=y +CONFIG_TARGET_EDMINIV2=y diff --git a/configs/enbw_cmc_defconfig b/configs/enbw_cmc_defconfig new file mode 100644 index 0000000000..92c49268de --- /dev/null +++ b/configs/enbw_cmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_DAVINCI=y +CONFIG_TARGET_ENBW_CMC=y diff --git a/configs/espt_defconfig b/configs/espt_defconfig new file mode 100644 index 0000000000..a50781d04e --- /dev/null +++ b/configs/espt_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_ESPT=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig new file mode 100644 index 0000000000..5be495cfa3 --- /dev/null +++ b/configs/ethernut5_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE" +CONFIG_ARM=y +CONFIG_TARGET_ETHERNUT5=y diff --git a/configs/favr-32-ezkit_defconfig b/configs/favr-32-ezkit_defconfig new file mode 100644 index 0000000000..941e02840e --- /dev/null +++ b/configs/favr-32-ezkit_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_FAVR_32_EZKIT=y diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig new file mode 100644 index 0000000000..ac112cdd7a --- /dev/null +++ b/configs/flea3_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_FLEA3=y diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig new file mode 100644 index 0000000000..6492b4b02e --- /dev/null +++ b/configs/fo300_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="FO300" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_TQM5200=y diff --git a/configs/fx12mm_defconfig b/configs/fx12mm_defconfig new file mode 100644 index 0000000000..9900a54869 --- /dev/null +++ b/configs/fx12mm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_FX12MM=y diff --git a/configs/fx12mm_flash_defconfig b/configs/fx12mm_flash_defconfig new file mode 100644 index 0000000000..5a0587ffec --- /dev/null +++ b/configs/fx12mm_flash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_FX12MM=y diff --git a/configs/galaxy5200_LOWBOOT_defconfig b/configs/galaxy5200_LOWBOOT_defconfig new file mode 100644 index 0000000000..4f193f5930 --- /dev/null +++ b/configs/galaxy5200_LOWBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="galaxy5200_LOWBOOT" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_GALAXY5200=y diff --git a/configs/galaxy5200_defconfig b/configs/galaxy5200_defconfig new file mode 100644 index 0000000000..0fdf643987 --- /dev/null +++ b/configs/galaxy5200_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="galaxy5200" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_GALAXY5200=y diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig new file mode 100644 index 0000000000..1097b9c157 --- /dev/null +++ b/configs/gdppc440etx_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_GDPPC440ETX=y diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig new file mode 100644 index 0000000000..2a66bfb08c --- /dev/null +++ b/configs/glacier_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="GLACIER" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_CANYONLANDS=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig new file mode 100644 index 0000000000..276489bbae --- /dev/null +++ b/configs/goflexhome_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_GOFLEXHOME=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig new file mode 100644 index 0000000000..54a56f5e71 --- /dev/null +++ b/configs/gose_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_GOSE=y diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig new file mode 100644 index 0000000000..ec8f45c1a1 --- /dev/null +++ b/configs/gplugd_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_GPLUGD=y diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig new file mode 100644 index 0000000000..b59d07772f --- /dev/null +++ b/configs/gr_cpci_ax2000_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SPARC=y +CONFIG_TARGET_GR_CPCI_AX2000=y diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig new file mode 100644 index 0000000000..2c69efa605 --- /dev/null +++ b/configs/gr_ep2s60_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SPARC=y +CONFIG_TARGET_GR_EP2S60=y diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig new file mode 100644 index 0000000000..fecdd2507c --- /dev/null +++ b/configs/gr_xc3s_1500_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SPARC=y +CONFIG_TARGET_GR_XC3S_1500=y diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig new file mode 100644 index 0000000000..72013e7417 --- /dev/null +++ b/configs/grasshopper_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_GRASSHOPPER=y diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig new file mode 100644 index 0000000000..e3ffd69f19 --- /dev/null +++ b/configs/grsim_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SPARC=y +CONFIG_TARGET_GRSIM=y diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig new file mode 100644 index 0000000000..6090e34e67 --- /dev/null +++ b/configs/grsim_leon2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SPARC=y +CONFIG_TARGET_GRSIM_LEON2=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig new file mode 100644 index 0000000000..912a0896a4 --- /dev/null +++ b/configs/guruplug_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_GURUPLUG=y diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig new file mode 100644 index 0000000000..4cddbdd655 --- /dev/null +++ b/configs/gwventana_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_GW_VENTANA=y diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig new file mode 100644 index 0000000000..7040c090bf --- /dev/null +++ b/configs/h2200_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_H2200=y diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig new file mode 100644 index 0000000000..7e6311676f --- /dev/null +++ b/configs/haleakala_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_KILAUEA=y diff --git a/configs/hammerhead_defconfig b/configs/hammerhead_defconfig new file mode 100644 index 0000000000..0d69cc6a27 --- /dev/null +++ b/configs/hammerhead_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_HAMMERHEAD=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig new file mode 100644 index 0000000000..d99b42955a --- /dev/null +++ b/configs/harmony_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_HARMONY=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony" diff --git a/configs/hawkboard_defconfig b/configs/hawkboard_defconfig new file mode 100644 index 0000000000..4084f9c019 --- /dev/null +++ b/configs/hawkboard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_DAVINCI=y ++S:CONFIG_TARGET_HAWKBOARD=y diff --git a/configs/hawkboard_uart_defconfig b/configs/hawkboard_uart_defconfig new file mode 100644 index 0000000000..d7eeae7a29 --- /dev/null +++ b/configs/hawkboard_uart_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="UART_U_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_DAVINCI=y ++S:CONFIG_TARGET_HAWKBOARD=y diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig new file mode 100644 index 0000000000..88efbdfc10 --- /dev/null +++ b/configs/highbank_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_ARCH_HIGHBANK=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig new file mode 100644 index 0000000000..69c65baae5 --- /dev/null +++ b/configs/hrcon_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_HRCON=y diff --git a/configs/hummingboard_solo_defconfig b/configs/hummingboard_solo_defconfig new file mode 100644 index 0000000000..600fa00c90 --- /dev/null +++ b/configs/hummingboard_solo_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512" +CONFIG_ARM=y +CONFIG_TARGET_HUMMINGBOARD=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig new file mode 100644 index 0000000000..41192fc73f --- /dev/null +++ b/configs/i12-tvbox_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=384 ++S:CONFIG_DRAM_ZQ=127 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig new file mode 100644 index 0000000000..b6780c54da --- /dev/null +++ b/configs/ib62x0_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_IB62X0=y diff --git a/configs/ibf-dsp561_defconfig b/configs/ibf-dsp561_defconfig new file mode 100644 index 0000000000..41a5c6592f --- /dev/null +++ b/configs/ibf-dsp561_defconfig @@ -0,0 +1,2 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_IBF_DSP561=y diff --git a/configs/icon_defconfig b/configs/icon_defconfig new file mode 100644 index 0000000000..771a093250 --- /dev/null +++ b/configs/icon_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_ICON=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig new file mode 100644 index 0000000000..7ff8d673d8 --- /dev/null +++ b/configs/iconnect_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_ICONNECT=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig new file mode 100644 index 0000000000..0950ec8b77 --- /dev/null +++ b/configs/ids8313_defconfig @@ -0,0 +1,7 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_TARGET_IDS8313=y +CONFIG_DM=y diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig new file mode 100644 index 0000000000..dd56ea18c3 --- /dev/null +++ b/configs/igep0020_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_IGEP00X0=y diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig new file mode 100644 index 0000000000..da54da02ab --- /dev/null +++ b/configs/igep0020_nand_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_IGEP00X0=y diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig new file mode 100644 index 0000000000..1025feddba --- /dev/null +++ b/configs/igep0030_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_IGEP00X0=y diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig new file mode 100644 index 0000000000..b3b3366c9b --- /dev/null +++ b/configs/igep0030_nand_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_IGEP00X0=y diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig new file mode 100644 index 0000000000..faa04f7ecd --- /dev/null +++ b/configs/igep0032_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_IGEP00X0=y diff --git a/configs/ima3-mx53_defconfig b/configs/ima3-mx53_defconfig new file mode 100644 index 0000000000..c7a9f681b6 --- /dev/null +++ b/configs/ima3-mx53_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg" +CONFIG_ARM=y +CONFIG_TARGET_IMA3_MX53=y diff --git a/configs/imx27lite_defconfig b/configs/imx27lite_defconfig new file mode 100644 index 0000000000..03803c67a1 --- /dev/null +++ b/configs/imx27lite_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_IMX27LITE=y diff --git a/configs/imx31_litekit_defconfig b/configs/imx31_litekit_defconfig new file mode 100644 index 0000000000..cd41c0e4ec --- /dev/null +++ b/configs/imx31_litekit_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_IMX31_LITEKIT=y diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig new file mode 100644 index 0000000000..563de57dc0 --- /dev/null +++ b/configs/imx31_phycore_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_IMX31_PHYCORE=y diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig new file mode 100644 index 0000000000..9531952004 --- /dev/null +++ b/configs/imx31_phycore_eet_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET" +CONFIG_ARM=y +CONFIG_TARGET_IMX31_PHYCORE=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig new file mode 100644 index 0000000000..1123b524d4 --- /dev/null +++ b/configs/inetspace_v2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig new file mode 100644 index 0000000000..6581b0a4af --- /dev/null +++ b/configs/inka4x0_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_INKA4X0=y diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig new file mode 100644 index 0000000000..0bb7b085ce --- /dev/null +++ b/configs/integratorap_cm720t_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CM720T" +CONFIG_ARM=y +CONFIG_TARGET_INTEGRATORAP_CM720T=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig new file mode 100644 index 0000000000..fb925d50b1 --- /dev/null +++ b/configs/integratorap_cm920t_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CM920T" +CONFIG_ARM=y +CONFIG_TARGET_INTEGRATORAP_CM920T=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig new file mode 100644 index 0000000000..308a1e6162 --- /dev/null +++ b/configs/integratorap_cm926ejs_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CM926EJ_S" +CONFIG_ARM=y +CONFIG_TARGET_INTEGRATORAP_CM926EJS=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig new file mode 100644 index 0000000000..d1b9db5d6a --- /dev/null +++ b/configs/integratorap_cm946es_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CM946ES" +CONFIG_ARM=y +CONFIG_TARGET_INTEGRATORAP_CM946ES=y diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig new file mode 100644 index 0000000000..3feb6563f6 --- /dev/null +++ b/configs/integratorcp_cm1136_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CM1136" +CONFIG_ARM=y +CONFIG_TARGET_INTEGRATORCP_CM1136=y diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig new file mode 100644 index 0000000000..f304bbe8eb --- /dev/null +++ b/configs/integratorcp_cm920t_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CM920T" +CONFIG_ARM=y +CONFIG_TARGET_INTEGRATORCP_CM920T=y diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig new file mode 100644 index 0000000000..a8d762b004 --- /dev/null +++ b/configs/integratorcp_cm926ejs_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CM924EJ_S" +CONFIG_ARM=y +CONFIG_TARGET_INTEGRATORCP_CM926EJS=y diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig new file mode 100644 index 0000000000..2e67dbc70a --- /dev/null +++ b/configs/integratorcp_cm946es_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="CM946ES" +CONFIG_ARM=y +CONFIG_TARGET_INTEGRATORCP_CM946ES=y diff --git a/configs/intip_defconfig b/configs/intip_defconfig new file mode 100644 index 0000000000..d6af774363 --- /dev/null +++ b/configs/intip_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="INTIB" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_INTIP=y diff --git a/configs/io64_defconfig b/configs/io64_defconfig new file mode 100644 index 0000000000..1111e54e9d --- /dev/null +++ b/configs/io64_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_IO64=y diff --git a/configs/io_defconfig b/configs/io_defconfig new file mode 100644 index 0000000000..959af75a1e --- /dev/null +++ b/configs/io_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_IO=y diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig new file mode 100644 index 0000000000..6dc88874fa --- /dev/null +++ b/configs/iocon_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_IOCON=y diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig new file mode 100644 index 0000000000..ba737aedfb --- /dev/null +++ b/configs/ip04_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_IP04=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig new file mode 100644 index 0000000000..4fefcbee76 --- /dev/null +++ b/configs/ipam390_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_DAVINCI=y ++S:CONFIG_TARGET_IPAM390=y diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig new file mode 100644 index 0000000000..83cf557934 --- /dev/null +++ b/configs/ipek01_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_IPEK01=y diff --git a/configs/jadecpu_defconfig b/configs/jadecpu_defconfig new file mode 100644 index 0000000000..4348e0e5df --- /dev/null +++ b/configs/jadecpu_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_JADECPU=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig new file mode 100644 index 0000000000..ef1d41c20b --- /dev/null +++ b/configs/jetson-tk1_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA124=y ++S:CONFIG_TARGET_JETSON_TK1=y +CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1" diff --git a/configs/jornada_defconfig b/configs/jornada_defconfig new file mode 100644 index 0000000000..ad1c3382b7 --- /dev/null +++ b/configs/jornada_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_JORNADA=y diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig new file mode 100644 index 0000000000..dac4f1a038 --- /dev/null +++ b/configs/jupiter_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_JUPITER=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig new file mode 100644 index 0000000000..9e702198be --- /dev/null +++ b/configs/k2e_evm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_KEYSTONE=y ++S:CONFIG_TARGET_K2E_EVM=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig new file mode 100644 index 0000000000..e04e3151b6 --- /dev/null +++ b/configs/k2hk_evm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_KEYSTONE=y ++S:CONFIG_TARGET_K2HK_EVM=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig new file mode 100644 index 0000000000..45399cea6b --- /dev/null +++ b/configs/k2l_evm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_KEYSTONE=y ++S:CONFIG_TARGET_K2L_EVM=y diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig new file mode 100644 index 0000000000..849231492b --- /dev/null +++ b/configs/katmai_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_KATMAI=y diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig new file mode 100644 index 0000000000..28021d99c3 --- /dev/null +++ b/configs/kilauea_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KILAUEA" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_KILAUEA=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig new file mode 100644 index 0000000000..6a263a6ad4 --- /dev/null +++ b/configs/km_kirkwood_128m16_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig new file mode 100644 index 0000000000..aff76e50a5 --- /dev/null +++ b/configs/km_kirkwood_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig new file mode 100644 index 0000000000..13c70a796c --- /dev/null +++ b/configs/km_kirkwood_pci_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig new file mode 100644 index 0000000000..22a005cca0 --- /dev/null +++ b/configs/kmcoge4_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_KMP204X=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig new file mode 100644 index 0000000000..80c1f75a6c --- /dev/null +++ b/configs/kmcoge5ne_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_KM8360=y diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig new file mode 100644 index 0000000000..78057e495a --- /dev/null +++ b/configs/kmcoge5un_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig new file mode 100644 index 0000000000..f87e347dd6 --- /dev/null +++ b/configs/kmeter1_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KMETER1" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_KM8360=y diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig new file mode 100644 index 0000000000..82c1924b40 --- /dev/null +++ b/configs/kmlion1_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KMLION1" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_KMP204X=y diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig new file mode 100644 index 0000000000..d125c52d40 --- /dev/null +++ b/configs/kmnusa_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig new file mode 100644 index 0000000000..8195184ee8 --- /dev/null +++ b/configs/kmopti2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_TUXX1=y diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig new file mode 100644 index 0000000000..d40dfd938f --- /dev/null +++ b/configs/kmsugp1_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig new file mode 100644 index 0000000000..99a9a9b14b --- /dev/null +++ b/configs/kmsupx5_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_TUXX1=y diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig new file mode 100644 index 0000000000..40d09935ac --- /dev/null +++ b/configs/kmsuv31_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig new file mode 100644 index 0000000000..dd9c2f2562 --- /dev/null +++ b/configs/kmvect1_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_SUVD3=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig new file mode 100644 index 0000000000..35f605cb74 --- /dev/null +++ b/configs/koelsch_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_KOELSCH=y diff --git a/configs/korat_defconfig b/configs/korat_defconfig new file mode 100644 index 0000000000..d363aab770 --- /dev/null +++ b/configs/korat_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_KORAT=y diff --git a/configs/korat_perm_defconfig b/configs/korat_perm_defconfig new file mode 100644 index 0000000000..8c6b4c4c35 --- /dev/null +++ b/configs/korat_perm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KORAT_PERMANENT" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_KORAT=y diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig new file mode 100644 index 0000000000..106a24f199 --- /dev/null +++ b/configs/kwb_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_KWB=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig new file mode 100644 index 0000000000..20656dd61d --- /dev/null +++ b/configs/kzm9g_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_KZM9G=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig new file mode 100644 index 0000000000..8b4aeea9a8 --- /dev/null +++ b/configs/lager_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_LAGER=y diff --git a/configs/lcd4_lwmon5_defconfig b/configs/lcd4_lwmon5_defconfig new file mode 100644 index 0000000000..1541733528 --- /dev/null +++ b/configs/lcd4_lwmon5_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5" ++S:CONFIG_PPC=y ++S:CONFIG_4xx=y ++S:CONFIG_TARGET_LWMON5=y diff --git a/configs/lp8x4x_defconfig b/configs/lp8x4x_defconfig new file mode 100644 index 0000000000..2fc2cbcc35 --- /dev/null +++ b/configs/lp8x4x_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_LP8X4X=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig new file mode 100644 index 0000000000..3c574810ef --- /dev/null +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig new file mode 100644 index 0000000000..dad5274ae8 --- /dev/null +++ b/configs/ls1021aqds_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..2b47995510 --- /dev/null +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig new file mode 100644 index 0000000000..9e42d61095 --- /dev/null +++ b/configs/ls1021aqds_nor_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig new file mode 100644 index 0000000000..29335ee10c --- /dev/null +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="LPUART" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig new file mode 100644 index 0000000000..05ec8e6502 --- /dev/null +++ b/configs/ls1021aqds_qspi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig new file mode 100644 index 0000000000..e03c3b467d --- /dev/null +++ b/configs/ls1021aqds_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..eeeb0d5907 --- /dev/null +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_LS1021ATWR=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig new file mode 100644 index 0000000000..5f465d3100 --- /dev/null +++ b/configs/ls1021atwr_nor_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021ATWR=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig new file mode 100644 index 0000000000..bdab6d9985 --- /dev/null +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="LPUART" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig new file mode 100644 index 0000000000..611f6e846a --- /dev/null +++ b/configs/ls1021atwr_qspi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig new file mode 100644 index 0000000000..0eb556ad4c --- /dev/null +++ b/configs/ls1021atwr_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/configs/ls2085a_emu_D4_defconfig b/configs/ls2085a_emu_D4_defconfig new file mode 100644 index 0000000000..0bc36ed0b0 --- /dev/null +++ b/configs/ls2085a_emu_D4_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS2085A_EMU=y diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2085a_emu_defconfig new file mode 100644 index 0000000000..a2efec3ccf --- /dev/null +++ b/configs/ls2085a_emu_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="EMU" +CONFIG_ARM=y +CONFIG_TARGET_LS2085A_EMU=y diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig new file mode 100644 index 0000000000..7563a7546e --- /dev/null +++ b/configs/ls2085a_simu_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SIMU" +CONFIG_ARM=y +CONFIG_TARGET_LS2085A_SIMU=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig new file mode 100644 index 0000000000..8c02fb3e4f --- /dev/null +++ b/configs/lschlv2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_LSXL=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig new file mode 100644 index 0000000000..86845d1904 --- /dev/null +++ b/configs/lsxhl_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="LSXHL" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_LSXL=y diff --git a/configs/luan_defconfig b/configs/luan_defconfig new file mode 100644 index 0000000000..d42b4a902f --- /dev/null +++ b/configs/luan_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_LUAN=y diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig new file mode 100644 index 0000000000..1ae21099e4 --- /dev/null +++ b/configs/lwmon5_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_LWMON5=y diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig new file mode 100644 index 0000000000..e7af81714c --- /dev/null +++ b/configs/m28evk_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_M28EVK=y diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig new file mode 100644 index 0000000000..65a647044a --- /dev/null +++ b/configs/m53evk_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_M53EVK=y diff --git a/configs/magnesium_defconfig b/configs/magnesium_defconfig new file mode 100644 index 0000000000..d45cfd73bc --- /dev/null +++ b/configs/magnesium_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_MAGNESIUM=y diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig new file mode 100644 index 0000000000..ed9b82d503 --- /dev/null +++ b/configs/makalu_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_MAKALU=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig new file mode 100644 index 0000000000..5a178a76b3 --- /dev/null +++ b/configs/malta_defconfig @@ -0,0 +1,3 @@ +CONFIG_MIPS=y +CONFIG_TARGET_MALTA=y +CONFIG_SYS_BIG_ENDIAN=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig new file mode 100644 index 0000000000..011525fc2b --- /dev/null +++ b/configs/maltael_defconfig @@ -0,0 +1,3 @@ +CONFIG_MIPS=y +CONFIG_TARGET_MALTA=y +CONFIG_SYS_LITTLE_ENDIAN=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig new file mode 100644 index 0000000000..d5c9f08f3e --- /dev/null +++ b/configs/marsboard_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH" +CONFIG_ARM=y +CONFIG_TARGET_EMBESTMX6BOARDS=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig new file mode 100644 index 0000000000..4bcffd8c2d --- /dev/null +++ b/configs/maxbcm_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_MAXBCM=y diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig new file mode 100644 index 0000000000..c2031f85b7 --- /dev/null +++ b/configs/mcx_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_MCX=y diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig new file mode 100644 index 0000000000..3b0a0a081e --- /dev/null +++ b/configs/mecp5123_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC512X=y +CONFIG_TARGET_MECP5123=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig new file mode 100644 index 0000000000..35963e9302 --- /dev/null +++ b/configs/medcom-wide_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_MEDCOM_WIDE=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide" diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig new file mode 100644 index 0000000000..fa737ef206 --- /dev/null +++ b/configs/meesc_dataflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_ARM=y +CONFIG_TARGET_MEESC=y diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig new file mode 100644 index 0000000000..f58efbbe6c --- /dev/null +++ b/configs/meesc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_MEESC=y diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig new file mode 100644 index 0000000000..e2eb06fe23 --- /dev/null +++ b/configs/mgcoge3ne_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE" +CONFIG_PPC=y +CONFIG_MPC8260=y +CONFIG_TARGET_KM82XX=y diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig new file mode 100644 index 0000000000..da991aad6a --- /dev/null +++ b/configs/mgcoge3un_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig new file mode 100644 index 0000000000..d2d4673ec6 --- /dev/null +++ b/configs/mgcoge_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MGCOGE" +CONFIG_PPC=y +CONFIG_MPC8260=y +CONFIG_TARGET_KM82XX=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig new file mode 100644 index 0000000000..5cfd596761 --- /dev/null +++ b/configs/microblaze-generic_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y ++S:CONFIG_MICROBLAZE=y ++S:CONFIG_TARGET_MICROBLAZE_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" diff --git a/configs/mimc200_defconfig b/configs/mimc200_defconfig new file mode 100644 index 0000000000..f6edbc768e --- /dev/null +++ b/configs/mimc200_defconfig @@ -0,0 +1,2 @@ +CONFIG_AVR32=y +CONFIG_TARGET_MIMC200=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig new file mode 100644 index 0000000000..cafcbaa62e --- /dev/null +++ b/configs/mk802_a10s_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" +CONFIG_FDTFILE="sun5i-a10s-mk802.dtb" +CONFIG_USB1_VBUS_PIN="PB10" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig new file mode 100644 index 0000000000..d6b51a5269 --- /dev/null +++ b/configs/mk802_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-mk802.dtb" +CONFIG_USB2_VBUS_PIN="PH12" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=360 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig new file mode 100644 index 0000000000..500f4df4b9 --- /dev/null +++ b/configs/mk802ii_defconfig @@ -0,0 +1,9 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" +CONFIG_FDTFILE="sun4i-a10-mk802ii.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=360 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=0 diff --git a/configs/ml507_defconfig b/configs/ml507_defconfig new file mode 100644 index 0000000000..009972a1e1 --- /dev/null +++ b/configs/ml507_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_ML507=y diff --git a/configs/ml507_flash_defconfig b/configs/ml507_flash_defconfig new file mode 100644 index 0000000000..a9658b608d --- /dev/null +++ b/configs/ml507_flash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_ML507=y diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig new file mode 100644 index 0000000000..535cb84ad2 --- /dev/null +++ b/configs/motionpro_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_MOTIONPRO=y diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig new file mode 100644 index 0000000000..4d76470cdd --- /dev/null +++ b/configs/mpc5121ads_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC512X=y +CONFIG_TARGET_MPC5121ADS=y diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig new file mode 100644 index 0000000000..9a89611b79 --- /dev/null +++ b/configs/mpc5121ads_rev2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2" +CONFIG_PPC=y +CONFIG_MPC512X=y +CONFIG_TARGET_MPC5121ADS=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig new file mode 100644 index 0000000000..2b8fc4e354 --- /dev/null +++ b/configs/mpc8308_p1m_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8308_P1M=y diff --git a/configs/mpr2_defconfig b/configs/mpr2_defconfig new file mode 100644 index 0000000000..c8be9872f4 --- /dev/null +++ b/configs/mpr2_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_MPR2=y diff --git a/configs/ms7720se_defconfig b/configs/ms7720se_defconfig new file mode 100644 index 0000000000..0e3f834442 --- /dev/null +++ b/configs/ms7720se_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_MS7720SE=y diff --git a/configs/ms7722se_defconfig b/configs/ms7722se_defconfig new file mode 100644 index 0000000000..4acb50914d --- /dev/null +++ b/configs/ms7722se_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_MS7722SE=y diff --git a/configs/ms7750se_defconfig b/configs/ms7750se_defconfig new file mode 100644 index 0000000000..c23e4c9ef1 --- /dev/null +++ b/configs/ms7750se_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_MS7750SE=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig new file mode 100644 index 0000000000..a0678bb823 --- /dev/null +++ b/configs/mt_ventoux_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_MT_VENTOUX=y diff --git a/configs/munices_defconfig b/configs/munices_defconfig new file mode 100644 index 0000000000..cc9f75e859 --- /dev/null +++ b/configs/munices_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_MUNICES=y diff --git a/configs/mv88f6281gtw_ge_defconfig b/configs/mv88f6281gtw_ge_defconfig new file mode 100644 index 0000000000..0650032f20 --- /dev/null +++ b/configs/mv88f6281gtw_ge_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_MV88F6281GTW_GE=y diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig new file mode 100644 index 0000000000..03d5066255 --- /dev/null +++ b/configs/mx23_olinuxino_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX23_OLINUXINO=y diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig new file mode 100644 index 0000000000..963cec365c --- /dev/null +++ b/configs/mx23evk_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX23EVK=y diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig new file mode 100644 index 0000000000..f676da6930 --- /dev/null +++ b/configs/mx25pdk_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg" +CONFIG_ARM=y +CONFIG_TARGET_MX25PDK=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig new file mode 100644 index 0000000000..7986880173 --- /dev/null +++ b/configs/mx28evk_auart_console_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX28EVK=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig new file mode 100644 index 0000000000..e006209d7a --- /dev/null +++ b/configs/mx28evk_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX28EVK=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig new file mode 100644 index 0000000000..ab42316b36 --- /dev/null +++ b/configs/mx28evk_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX28EVK=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig new file mode 100644 index 0000000000..df992fac31 --- /dev/null +++ b/configs/mx28evk_spi_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX28EVK=y diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig new file mode 100644 index 0000000000..5105a9a1c8 --- /dev/null +++ b/configs/mx31ads_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_MX31ADS=y diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig new file mode 100644 index 0000000000..26cd87e384 --- /dev/null +++ b/configs/mx31pdk_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX31PDK=y diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig new file mode 100644 index 0000000000..3d79fe1cdf --- /dev/null +++ b/configs/mx35pdk_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_MX35PDK=y diff --git a/configs/mx51_efikamx_defconfig b/configs/mx51_efikamx_defconfig new file mode 100644 index 0000000000..a804b5ae73 --- /dev/null +++ b/configs/mx51_efikamx_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg" +CONFIG_ARM=y +CONFIG_TARGET_MX51_EFIKAMX=y diff --git a/configs/mx51_efikasb_defconfig b/configs/mx51_efikasb_defconfig new file mode 100644 index 0000000000..b07762f394 --- /dev/null +++ b/configs/mx51_efikasb_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg" +CONFIG_ARM=y +CONFIG_TARGET_MX51_EFIKAMX=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig new file mode 100644 index 0000000000..890aa76c09 --- /dev/null +++ b/configs/mx51evk_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg" +CONFIG_ARM=y +CONFIG_TARGET_MX51EVK=y diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig new file mode 100644 index 0000000000..e5cb89591e --- /dev/null +++ b/configs/mx53ard_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg" +CONFIG_ARM=y +CONFIG_TARGET_MX53ARD=y diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig new file mode 100644 index 0000000000..570241f1ce --- /dev/null +++ b/configs/mx53evk_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg" +CONFIG_ARM=y +CONFIG_TARGET_MX53EVK=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig new file mode 100644 index 0000000000..92a67fb73d --- /dev/null +++ b/configs/mx53loco_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" +CONFIG_ARM=y +CONFIG_TARGET_MX53LOCO=y diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig new file mode 100644 index 0000000000..97cb931e7b --- /dev/null +++ b/configs/mx53smd_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg" +CONFIG_ARM=y +CONFIG_TARGET_MX53SMD=y diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig new file mode 100644 index 0000000000..de0193f4cc --- /dev/null +++ b/configs/mx6dlarm2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048" +CONFIG_ARM=y +CONFIG_TARGET_MX6QARM2=y diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig new file mode 100644 index 0000000000..cc432cfb54 --- /dev/null +++ b/configs/mx6dlarm2_lpddr2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512" +CONFIG_ARM=y +CONFIG_TARGET_MX6QARM2=y diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig new file mode 100644 index 0000000000..b649935912 --- /dev/null +++ b/configs/mx6dlsabreauto_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL" +CONFIG_ARM=y +CONFIG_TARGET_MX6QSABREAUTO=y diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig new file mode 100644 index 0000000000..7f6cdff384 --- /dev/null +++ b/configs/mx6dlsabresd_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" +CONFIG_ARM=y +CONFIG_TARGET_MX6SABRESD=y diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig new file mode 100644 index 0000000000..3fe3559a17 --- /dev/null +++ b/configs/mx6qarm2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048" +CONFIG_ARM=y +CONFIG_TARGET_MX6QARM2=y diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig new file mode 100644 index 0000000000..491e22a057 --- /dev/null +++ b/configs/mx6qarm2_lpddr2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512" +CONFIG_ARM=y +CONFIG_TARGET_MX6QARM2=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig new file mode 100644 index 0000000000..7d86700b30 --- /dev/null +++ b/configs/mx6qsabreauto_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q" +CONFIG_ARM=y +CONFIG_TARGET_MX6QSABREAUTO=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig new file mode 100644 index 0000000000..dfa9c2e4db --- /dev/null +++ b/configs/mx6qsabrelite_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE" +CONFIG_ARM=y +CONFIG_TARGET_NITROGEN6X=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig new file mode 100644 index 0000000000..67c1b77e05 --- /dev/null +++ b/configs/mx6qsabresd_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" +CONFIG_ARM=y +CONFIG_TARGET_MX6SABRESD=y diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig new file mode 100644 index 0000000000..12e784435c --- /dev/null +++ b/configs/mx6sabresd_spl_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX6SABRESD=y + diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig new file mode 100644 index 0000000000..fb8c4decfd --- /dev/null +++ b/configs/mx6slevk_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" +CONFIG_ARM=y +CONFIG_TARGET_MX6SLEVK=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig new file mode 100644 index 0000000000..93efe73014 --- /dev/null +++ b/configs/mx6slevk_spinor_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR" +CONFIG_ARM=y +CONFIG_TARGET_MX6SLEVK=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig new file mode 100644 index 0000000000..f23d48f361 --- /dev/null +++ b/configs/mx6sxsabresd_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX" +CONFIG_ARM=y +CONFIG_TARGET_MX6SXSABRESD=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig new file mode 100644 index 0000000000..5a79c51ef3 --- /dev/null +++ b/configs/nas220_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NAS220=y diff --git a/configs/neo_defconfig b/configs/neo_defconfig new file mode 100644 index 0000000000..2a19247731 --- /dev/null +++ b/configs/neo_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_NEO=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig new file mode 100644 index 0000000000..7422fbedcf --- /dev/null +++ b/configs/net2big_v2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NET2BIG_V2=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig new file mode 100644 index 0000000000..6a3a32f8aa --- /dev/null +++ b/configs/netspace_lite_v2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig new file mode 100644 index 0000000000..903d6c9847 --- /dev/null +++ b/configs/netspace_max_v2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig new file mode 100644 index 0000000000..774faa74bc --- /dev/null +++ b/configs/netspace_mini_v2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig new file mode 100644 index 0000000000..776fc04916 --- /dev/null +++ b/configs/netspace_v2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/nhk8815_defconfig b/configs/nhk8815_defconfig new file mode 100644 index 0000000000..f661226897 --- /dev/null +++ b/configs/nhk8815_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_NOMADIK=y +CONFIG_NOMADIK_NHK8815=y diff --git a/configs/nhk8815_onenand_defconfig b/configs/nhk8815_onenand_defconfig new file mode 100644 index 0000000000..dd8048df74 --- /dev/null +++ b/configs/nhk8815_onenand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND" +CONFIG_ARM=y +CONFIG_ARCH_NOMADIK=y +CONFIG_NOMADIK_NHK8815=y diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig new file mode 100644 index 0000000000..f6da884541 --- /dev/null +++ b/configs/nios2-generic_defconfig @@ -0,0 +1,2 @@ +CONFIG_NIOS2=y +CONFIG_TARGET_NIOS2_GENERIC=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig new file mode 100644 index 0000000000..ce9343a03c --- /dev/null +++ b/configs/nitrogen6dl2g_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048" +CONFIG_ARM=y +CONFIG_TARGET_NITROGEN6X=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig new file mode 100644 index 0000000000..15dd549c0d --- /dev/null +++ b/configs/nitrogen6dl_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" +CONFIG_ARM=y +CONFIG_TARGET_NITROGEN6X=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig new file mode 100644 index 0000000000..12d951604b --- /dev/null +++ b/configs/nitrogen6q2g_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" +CONFIG_ARM=y +CONFIG_TARGET_NITROGEN6X=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig new file mode 100644 index 0000000000..b282dc3310 --- /dev/null +++ b/configs/nitrogen6q_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024" +CONFIG_ARM=y +CONFIG_TARGET_NITROGEN6X=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig new file mode 100644 index 0000000000..d1a4f156ec --- /dev/null +++ b/configs/nitrogen6s1g_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024" +CONFIG_ARM=y +CONFIG_TARGET_NITROGEN6X=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig new file mode 100644 index 0000000000..73a206f02f --- /dev/null +++ b/configs/nitrogen6s_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" +CONFIG_ARM=y +CONFIG_TARGET_NITROGEN6X=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig new file mode 100644 index 0000000000..e03f586880 --- /dev/null +++ b/configs/nokia_rx51_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_OMAP34XX=y +CONFIG_TARGET_NOKIA_RX51=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig new file mode 100644 index 0000000000..b8fd97fd3f --- /dev/null +++ b/configs/novena_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_KOSAGI_NOVENA=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig new file mode 100644 index 0000000000..ec79b5b5f0 --- /dev/null +++ b/configs/nyan-big_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA124=y ++S:CONFIG_TARGET_NYAN_BIG=y +CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" diff --git a/configs/ocotea_defconfig b/configs/ocotea_defconfig new file mode 100644 index 0000000000..34518cd457 --- /dev/null +++ b/configs/ocotea_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_OCOTEA=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000000..74aa0cf672 --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig new file mode 100644 index 0000000000..a8428373ac --- /dev/null +++ b/configs/odroid_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig new file mode 100644 index 0000000000..a3e4c2c6d6 --- /dev/null +++ b/configs/omap3_beagle_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="NAND" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_BEAGLE=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig new file mode 100644 index 0000000000..c749aa74b7 --- /dev/null +++ b/configs/omap3_evm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_EVM=y diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig new file mode 100644 index 0000000000..e89bb82ac9 --- /dev/null +++ b/configs/omap3_evm_quick_mmc_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig new file mode 100644 index 0000000000..e70fddd794 --- /dev/null +++ b/configs/omap3_evm_quick_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig new file mode 100644 index 0000000000..50bffa90a2 --- /dev/null +++ b/configs/omap3_ha_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_TAO3530=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig new file mode 100644 index 0000000000..5f2c063b6e --- /dev/null +++ b/configs/omap3_logic_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_OMAP34XX=y +CONFIG_TARGET_OMAP3_LOGIC=y diff --git a/configs/omap3_mvblx_defconfig b/configs/omap3_mvblx_defconfig new file mode 100644 index 0000000000..fb6edc252a --- /dev/null +++ b/configs/omap3_mvblx_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_OMAP34XX=y +CONFIG_TARGET_OMAP3_MVBLX=y diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig new file mode 100644 index 0000000000..7e0d334289 --- /dev/null +++ b/configs/omap3_overo_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_OVERO=y diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig new file mode 100644 index 0000000000..bf285378a3 --- /dev/null +++ b/configs/omap3_pandora_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_OMAP34XX=y +CONFIG_TARGET_OMAP3_PANDORA=y diff --git a/configs/omap3_sdp3430_defconfig b/configs/omap3_sdp3430_defconfig new file mode 100644 index 0000000000..1172c2adc5 --- /dev/null +++ b/configs/omap3_sdp3430_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_OMAP34XX=y +CONFIG_TARGET_OMAP3_SDP3430=y diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig new file mode 100644 index 0000000000..e2d0a8c5b9 --- /dev/null +++ b/configs/omap3_zoom1_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_OMAP34XX=y +CONFIG_TARGET_OMAP3_ZOOM1=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig new file mode 100644 index 0000000000..6afac386c2 --- /dev/null +++ b/configs/omap4_panda_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP44XX=y ++S:CONFIG_TARGET_OMAP4_PANDA=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig new file mode 100644 index 0000000000..c771e76026 --- /dev/null +++ b/configs/omap4_sdp4430_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP44XX=y ++S:CONFIG_TARGET_OMAP4_SDP4430=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig new file mode 100644 index 0000000000..86d5c1662e --- /dev/null +++ b/configs/omap5_uevm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_OMAP5_UEVM=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig new file mode 100644 index 0000000000..7b3ea99a21 --- /dev/null +++ b/configs/openrd_base_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig new file mode 100644 index 0000000000..d34793dd8a --- /dev/null +++ b/configs/openrd_client_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig new file mode 100644 index 0000000000..4e10d4d1d6 --- /dev/null +++ b/configs/openrd_ultimate_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y diff --git a/configs/openrisc-generic_defconfig b/configs/openrisc-generic_defconfig new file mode 100644 index 0000000000..e422974f40 --- /dev/null +++ b/configs/openrisc-generic_defconfig @@ -0,0 +1,2 @@ +CONFIG_OPENRISC=y +CONFIG_TARGET_OPENRISC_GENERIC=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig new file mode 100644 index 0000000000..2a7f83bf89 --- /dev/null +++ b/configs/origen_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_ORIGEN=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen" diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig new file mode 100644 index 0000000000..c516038697 --- /dev/null +++ b/configs/ot1200_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q" +CONFIG_ARM=y +CONFIG_TARGET_OT1200=y diff --git a/configs/otc570_dataflash_defconfig b/configs/otc570_dataflash_defconfig new file mode 100644 index 0000000000..992d6b649c --- /dev/null +++ b/configs/otc570_dataflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_ARM=y +CONFIG_TARGET_OTC570=y diff --git a/configs/otc570_defconfig b/configs/otc570_defconfig new file mode 100644 index 0000000000..65295cb734 --- /dev/null +++ b/configs/otc570_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_OTC570=y diff --git a/configs/p3p440_defconfig b/configs/p3p440_defconfig new file mode 100644 index 0000000000..0511b14bc7 --- /dev/null +++ b/configs/p3p440_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_P3P440=y diff --git a/configs/palmld_defconfig b/configs/palmld_defconfig new file mode 100644 index 0000000000..599acc357f --- /dev/null +++ b/configs/palmld_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_PALMLD=y diff --git a/configs/palmtc_defconfig b/configs/palmtc_defconfig new file mode 100644 index 0000000000..91cb76d9e4 --- /dev/null +++ b/configs/palmtc_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_PALMTC=y diff --git a/configs/palmtreo680_defconfig b/configs/palmtreo680_defconfig new file mode 100644 index 0000000000..84c4c16179 --- /dev/null +++ b/configs/palmtreo680_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PALMTREO680=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig new file mode 100644 index 0000000000..d2d36a5848 --- /dev/null +++ b/configs/paz00_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_PAZ00=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00" diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig new file mode 100644 index 0000000000..72c22a0876 --- /dev/null +++ b/configs/pb1000_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PB1000" +CONFIG_MIPS=y +CONFIG_TARGET_PB1X00=y +CONFIG_SYS_LITTLE_ENDIAN=y diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig new file mode 100644 index 0000000000..72ecf8f54e --- /dev/null +++ b/configs/pcm030_LOWBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000" +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_PCM030=y diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig new file mode 100644 index 0000000000..3283517ae8 --- /dev/null +++ b/configs/pcm030_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_PCM030=y diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig new file mode 100644 index 0000000000..8b27682997 --- /dev/null +++ b/configs/pcm051_rev1_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="REV1" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PCM051=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig new file mode 100644 index 0000000000..27ad6ff26b --- /dev/null +++ b/configs/pcm051_rev3_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="REV3" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PCM051=y diff --git a/configs/pcs440ep_defconfig b/configs/pcs440ep_defconfig new file mode 100644 index 0000000000..299bf8afa7 --- /dev/null +++ b/configs/pcs440ep_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_PCS440EP=y diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig new file mode 100644 index 0000000000..4e3d704f81 --- /dev/null +++ b/configs/pdm360ng_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC512X=y +CONFIG_TARGET_PDM360NG=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig new file mode 100644 index 0000000000..8ada0dbe40 --- /dev/null +++ b/configs/peach-pi_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_PEACH_PI=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig new file mode 100644 index 0000000000..b944b3bb50 --- /dev/null +++ b/configs/peach-pit_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_PEACH_PIT=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit" diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig new file mode 100644 index 0000000000..1b9aa68260 --- /dev/null +++ b/configs/pengwyn_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PENGWYN=y diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig new file mode 100644 index 0000000000..22c7bb4a60 --- /dev/null +++ b/configs/pepper_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PEPPER=y diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig new file mode 100644 index 0000000000..86b4b15724 --- /dev/null +++ b/configs/ph1_ld4_defconfig @@ -0,0 +1,42 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_UNIPHIER=y ++S:CONFIG_MACH_PH1_LD4=y ++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y +CONFIG_CMD_BOOTD=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_NET=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" +CONFIG_DM=y +CONFIG_NAND_DENALI=y +CONFIG_SYS_NAND_DENALI_64BIT=y +CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 +CONFIG_DM_SERIAL=y +CONFIG_UNIPHIER_SERIAL=y +CONFIG_DM_I2C=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig new file mode 100644 index 0000000000..242bcf9263 --- /dev/null +++ b/configs/ph1_pro4_defconfig @@ -0,0 +1,42 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_UNIPHIER=y ++S:CONFIG_MACH_PH1_PRO4=y ++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y +CONFIG_CMD_BOOTD=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_NET=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" +CONFIG_DM=y +CONFIG_NAND_DENALI=y +CONFIG_SYS_NAND_DENALI_64BIT=y +CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 +CONFIG_DM_SERIAL=y +CONFIG_UNIPHIER_SERIAL=y +CONFIG_DM_I2C=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig new file mode 100644 index 0000000000..8e95f17e6d --- /dev/null +++ b/configs/ph1_sld8_defconfig @@ -0,0 +1,42 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_UNIPHIER=y ++S:CONFIG_MACH_PH1_SLD8=y ++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y +CONFIG_CMD_BOOTD=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_NET=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" +CONFIG_DM=y +CONFIG_NAND_DENALI=y +CONFIG_SYS_NAND_DENALI_64BIT=y +CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 +CONFIG_DM_SERIAL=y +CONFIG_UNIPHIER_SERIAL=y +CONFIG_DM_I2C=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig new file mode 100644 index 0000000000..d2743b8ef6 --- /dev/null +++ b/configs/plutux_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_PLUTUX=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux" diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig new file mode 100644 index 0000000000..b8a02483c1 --- /dev/null +++ b/configs/pm9261_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261" +CONFIG_ARM=y +CONFIG_TARGET_PM9261=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig new file mode 100644 index 0000000000..3a5029a665 --- /dev/null +++ b/configs/pm9263_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263" +CONFIG_ARM=y +CONFIG_TARGET_PM9263=y diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig new file mode 100644 index 0000000000..89297e0dbe --- /dev/null +++ b/configs/pm9g45_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" +CONFIG_ARM=y +CONFIG_TARGET_PM9G45=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig new file mode 100644 index 0000000000..97effefa31 --- /dev/null +++ b/configs/pogo_e02_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_POGO_E02=y diff --git a/configs/polaris_defconfig b/configs/polaris_defconfig new file mode 100644 index 0000000000..f510a53e44 --- /dev/null +++ b/configs/polaris_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="POLARIS" +CONFIG_ARM=y +CONFIG_TARGET_TRIZEPSIV=y diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig new file mode 100644 index 0000000000..1895c80bb4 --- /dev/null +++ b/configs/portl2_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2" +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/portuxg20_defconfig b/configs/portuxg20_defconfig new file mode 100644 index 0000000000..b1634e9a68 --- /dev/null +++ b/configs/portuxg20_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,PORTUXG20" +CONFIG_ARM=y +CONFIG_TARGET_STAMP9G20=y diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig new file mode 100644 index 0000000000..793a4e8376 --- /dev/null +++ b/configs/pr1_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_PR1=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/pxa255_idp_defconfig b/configs/pxa255_idp_defconfig new file mode 100644 index 0000000000..251d6c4278 --- /dev/null +++ b/configs/pxa255_idp_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_PXA255_IDP=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig new file mode 100644 index 0000000000..e0d9031561 --- /dev/null +++ b/configs/pxm2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PXM2=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig new file mode 100644 index 0000000000..2b8f707d5f --- /dev/null +++ b/configs/qemu-ppce500_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_QEMU_PPCE500=y diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig new file mode 100644 index 0000000000..3608bbe552 --- /dev/null +++ b/configs/qemu_mips64_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_QEMU_MIPS=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_CPU_MIPS64_R1=y diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig new file mode 100644 index 0000000000..a9ebd7b5ff --- /dev/null +++ b/configs/qemu_mips64el_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_QEMU_MIPS=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS64_R1=y diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig new file mode 100644 index 0000000000..f58dd2200a --- /dev/null +++ b/configs/qemu_mips_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_QEMU_MIPS=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig new file mode 100644 index 0000000000..84a45116fa --- /dev/null +++ b/configs/qemu_mipsel_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_QEMU_MIPS=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y diff --git a/configs/qong_defconfig b/configs/qong_defconfig new file mode 100644 index 0000000000..fddd836318 --- /dev/null +++ b/configs/qong_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_QONG=y diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig new file mode 100644 index 0000000000..2b2d2cd6a2 --- /dev/null +++ b/configs/r0p7734_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_R0P7734=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig new file mode 100644 index 0000000000..87de323247 --- /dev/null +++ b/configs/r2dplus_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_R2DPLUS=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig new file mode 100644 index 0000000000..e99e57d505 --- /dev/null +++ b/configs/r7-tv-dongle_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" +CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb" +CONFIG_USB1_VBUS_PIN="PG13" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_DRAM_CLK=384 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig new file mode 100644 index 0000000000..7e201f5b77 --- /dev/null +++ b/configs/r7780mp_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_R7780MP=y diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig new file mode 100644 index 0000000000..666cb18550 --- /dev/null +++ b/configs/rainier_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAINIER" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_SEQUOIA=y diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig new file mode 100644 index 0000000000..2ecb1cfba8 --- /dev/null +++ b/configs/rainier_ramboot_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_SEQUOIA=y diff --git a/configs/rd6281a_defconfig b/configs/rd6281a_defconfig new file mode 100644 index 0000000000..ed083bf069 --- /dev/null +++ b/configs/rd6281a_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_RD6281A=y diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig new file mode 100644 index 0000000000..ad87d0eb4a --- /dev/null +++ b/configs/redwood_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_REDWOOD=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig new file mode 100644 index 0000000000..5296bde84a --- /dev/null +++ b/configs/riotboard_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC" +CONFIG_ARM=y +CONFIG_TARGET_EMBESTMX6BOARDS=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig new file mode 100644 index 0000000000..9379cf00d4 --- /dev/null +++ b/configs/rpi_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_RPI=y diff --git a/configs/rsk7203_defconfig b/configs/rsk7203_defconfig new file mode 100644 index 0000000000..44c0bc85ed --- /dev/null +++ b/configs/rsk7203_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_RSK7203=y diff --git a/configs/rsk7264_defconfig b/configs/rsk7264_defconfig new file mode 100644 index 0000000000..aedc333dc4 --- /dev/null +++ b/configs/rsk7264_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_RSK7264=y diff --git a/configs/rsk7269_defconfig b/configs/rsk7269_defconfig new file mode 100644 index 0000000000..25fdf80a7f --- /dev/null +++ b/configs/rsk7269_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_RSK7269=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig new file mode 100644 index 0000000000..0568655e1e --- /dev/null +++ b/configs/rut_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_RUT=y diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig new file mode 100644 index 0000000000..618e590802 --- /dev/null +++ b/configs/s5p_goni_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_S5PC1XX=y +CONFIG_TARGET_S5P_GONI=y +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig new file mode 100644 index 0000000000..cdce39f892 --- /dev/null +++ b/configs/s5pc210_universal_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_S5PC210_UNIVERSAL=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210" diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig new file mode 100644 index 0000000000..a7d791f85c --- /dev/null +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D3_XPLAINED=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig new file mode 100644 index 0000000000..b97286081e --- /dev/null +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D3_XPLAINED=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig new file mode 100644 index 0000000000..3f8d997af5 --- /dev/null +++ b/configs/sama5d3xek_mmc_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D3XEK=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig new file mode 100644 index 0000000000..7a924172fe --- /dev/null +++ b/configs/sama5d3xek_nandflash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D3XEK=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig new file mode 100644 index 0000000000..c83a7ab1fb --- /dev/null +++ b/configs/sama5d3xek_spiflash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D3XEK=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig new file mode 100644 index 0000000000..3720f3cfb4 --- /dev/null +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4_XPLAINED=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig new file mode 100644 index 0000000000..5e13da7908 --- /dev/null +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4_XPLAINED=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig new file mode 100644 index 0000000000..3a4607c676 --- /dev/null +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4_XPLAINED=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig new file mode 100644 index 0000000000..16a5ed7ef5 --- /dev/null +++ b/configs/sama5d4ek_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4EK=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig new file mode 100644 index 0000000000..8b7fbc33f4 --- /dev/null +++ b/configs/sama5d4ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4EK=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig new file mode 100644 index 0000000000..63e9b6c0c6 --- /dev/null +++ b/configs/sama5d4ek_spiflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4EK=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig new file mode 100644 index 0000000000..660063ebf3 --- /dev/null +++ b/configs/sandbox_defconfig @@ -0,0 +1,7 @@ +CONFIG_OF_CONTROL=y +CONFIG_OF_HOSTFILE=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y +CONFIG_DEFAULT_DEVICE_TREE="sandbox" diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig new file mode 100644 index 0000000000..b6b0fc7478 --- /dev/null +++ b/configs/sansa_fuze_plus_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SANSA_FUZE_PLUS=y diff --git a/configs/sbc35_a9g20_eeprom_defconfig b/configs/sbc35_a9g20_eeprom_defconfig new file mode 100644 index 0000000000..aa9cd3e4a0 --- /dev/null +++ b/configs/sbc35_a9g20_eeprom_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_EEPROM" +CONFIG_ARM=y +CONFIG_TARGET_SBC35_A9G20=y diff --git a/configs/sbc35_a9g20_nandflash_defconfig b/configs/sbc35_a9g20_nandflash_defconfig new file mode 100644 index 0000000000..fba9f311c6 --- /dev/null +++ b/configs/sbc35_a9g20_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_SBC35_A9G20=y diff --git a/configs/sbc405_defconfig b/configs/sbc405_defconfig new file mode 100644 index 0000000000..b34cbb7871 --- /dev/null +++ b/configs/sbc405_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_SBC405=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig new file mode 100644 index 0000000000..f7aaa7d776 --- /dev/null +++ b/configs/sbc8349_PCI_33_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_SBC8349=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig new file mode 100644 index 0000000000..2e1171f06d --- /dev/null +++ b/configs/sbc8349_PCI_66_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_SBC8349=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig new file mode 100644 index 0000000000..f1808e831a --- /dev/null +++ b/configs/sbc8349_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_SBC8349=y diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig new file mode 100644 index 0000000000..ae4f63f4d0 --- /dev/null +++ b/configs/sbc8548_PCI_33_PCIE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_SBC8548=y diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig new file mode 100644 index 0000000000..b79b99329c --- /dev/null +++ b/configs/sbc8548_PCI_33_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,33" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_SBC8548=y diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig new file mode 100644 index 0000000000..661fd0ff69 --- /dev/null +++ b/configs/sbc8548_PCI_66_PCIE_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_SBC8548=y diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig new file mode 100644 index 0000000000..8cc95e5727 --- /dev/null +++ b/configs/sbc8548_PCI_66_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PCI,66" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_SBC8548=y diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig new file mode 100644 index 0000000000..b74f7bc0f7 --- /dev/null +++ b/configs/sbc8548_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_SBC8548=y diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig new file mode 100644 index 0000000000..6b89473b6a --- /dev/null +++ b/configs/sbc8641d_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC86xx=y +CONFIG_TARGET_SBC8641D=y diff --git a/configs/sc3_defconfig b/configs/sc3_defconfig new file mode 100644 index 0000000000..e77b04cf2b --- /dev/null +++ b/configs/sc3_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_SC3=y diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig new file mode 100644 index 0000000000..75e0fc8248 --- /dev/null +++ b/configs/sc_sps_1_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SC_SPS_1=y diff --git a/configs/scb9328_defconfig b/configs/scb9328_defconfig new file mode 100644 index 0000000000..048caeb9f5 --- /dev/null +++ b/configs/scb9328_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_SCB9328=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig new file mode 100644 index 0000000000..ddf2cd6995 --- /dev/null +++ b/configs/seaboard_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_SEABOARD=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard" diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig new file mode 100644 index 0000000000..678c2bb5d1 --- /dev/null +++ b/configs/sequoia_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_SEQUOIA=y diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig new file mode 100644 index 0000000000..0d0c6c1302 --- /dev/null +++ b/configs/sequoia_ramboot_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_SEQUOIA=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig new file mode 100644 index 0000000000..1f7c6d0284 --- /dev/null +++ b/configs/sh7752evb_defconfig @@ -0,0 +1,3 @@ +CONFIG_SH=y +CONFIG_SH_32BIT=y +CONFIG_TARGET_SH7752EVB=y diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig new file mode 100644 index 0000000000..35809e9530 --- /dev/null +++ b/configs/sh7753evb_defconfig @@ -0,0 +1,3 @@ +CONFIG_SH=y +CONFIG_SH_32BIT=y +CONFIG_TARGET_SH7753EVB=y diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig new file mode 100644 index 0000000000..ffcf961bb5 --- /dev/null +++ b/configs/sh7757lcr_defconfig @@ -0,0 +1,3 @@ +CONFIG_SH=y +CONFIG_SH_32BIT=y +CONFIG_TARGET_SH7757LCR=y diff --git a/configs/sh7763rdp_defconfig b/configs/sh7763rdp_defconfig new file mode 100644 index 0000000000..8857e8a714 --- /dev/null +++ b/configs/sh7763rdp_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_SH7763RDP=y diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig new file mode 100644 index 0000000000..31b84ff352 --- /dev/null +++ b/configs/sh7785lcr_32bit_defconfig @@ -0,0 +1,3 @@ +CONFIG_SH=y +CONFIG_SH_32BIT=y +CONFIG_TARGET_SH7785LCR=y diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig new file mode 100644 index 0000000000..31d2c38fd1 --- /dev/null +++ b/configs/sh7785lcr_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_SH7785LCR=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig new file mode 100644 index 0000000000..d22b00674f --- /dev/null +++ b/configs/sheevaplug_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_SHEEVAPLUG=y diff --git a/configs/shmin_defconfig b/configs/shmin_defconfig new file mode 100644 index 0000000000..74c35505e7 --- /dev/null +++ b/configs/shmin_defconfig @@ -0,0 +1,2 @@ +CONFIG_SH=y +CONFIG_TARGET_SHMIN=y diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig new file mode 100644 index 0000000000..fec4ba6839 --- /dev/null +++ b/configs/smdk2410_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_SMDK2410=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig new file mode 100644 index 0000000000..9b76d0d124 --- /dev/null +++ b/configs/smdk5250_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_SMDK5250=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250" diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig new file mode 100644 index 0000000000..8cf673d093 --- /dev/null +++ b/configs/smdk5420_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_SMDK5420=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420" diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig new file mode 100644 index 0000000000..041030f942 --- /dev/null +++ b/configs/smdkc100_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_TARGET_SMDKC100=y +CONFIG_ARCH_S5PC1XX=y +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig new file mode 100644 index 0000000000..0d1a24f99f --- /dev/null +++ b/configs/smdkv310_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_SMDKV310=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig new file mode 100644 index 0000000000..7055e2a13b --- /dev/null +++ b/configs/snapper9260_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" +CONFIG_ARM=y +CONFIG_TARGET_SNAPPER9260=y diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig new file mode 100644 index 0000000000..2faae15930 --- /dev/null +++ b/configs/snapper9g20_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" +CONFIG_ARM=y +CONFIG_TARGET_SNAPPER9260=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig new file mode 100644 index 0000000000..14ed793f6d --- /dev/null +++ b/configs/snow_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_SNOW=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow" diff --git a/configs/snowball_defconfig b/configs/snowball_defconfig new file mode 100644 index 0000000000..19100c2526 --- /dev/null +++ b/configs/snowball_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_SNOWBALL=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig new file mode 100644 index 0000000000..4b2ede490b --- /dev/null +++ b/configs/socfpga_cyclone5_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig new file mode 100644 index 0000000000..0f3896d5f0 --- /dev/null +++ b/configs/socfpga_socrates_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig new file mode 100644 index 0000000000..d7ed82b879 --- /dev/null +++ b/configs/socrates_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_SOCRATES=y diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig new file mode 100644 index 0000000000..25a08df34e --- /dev/null +++ b/configs/spear300_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear300" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR300=y diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig new file mode 100644 index 0000000000..a4b70e8090 --- /dev/null +++ b/configs/spear300_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear300,nand" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR300=y diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig new file mode 100644 index 0000000000..d750cf49d7 --- /dev/null +++ b/configs/spear300_usbtty_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR300=y diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig new file mode 100644 index 0000000000..8bafdb5396 --- /dev/null +++ b/configs/spear300_usbtty_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty,nand" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR300=y diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig new file mode 100644 index 0000000000..8a9ec859a0 --- /dev/null +++ b/configs/spear310_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear310" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR310=y diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig new file mode 100644 index 0000000000..1439ac53d2 --- /dev/null +++ b/configs/spear310_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear310,nand" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR310=y diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig new file mode 100644 index 0000000000..19604b3fed --- /dev/null +++ b/configs/spear310_pnor_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear310,FLASH_PNOR" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR310=y diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig new file mode 100644 index 0000000000..6342a56512 --- /dev/null +++ b/configs/spear310_usbtty_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR310=y diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig new file mode 100644 index 0000000000..5b9f1f6d70 --- /dev/null +++ b/configs/spear310_usbtty_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,nand" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR310=y diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig new file mode 100644 index 0000000000..0567936ac6 --- /dev/null +++ b/configs/spear310_usbtty_pnor_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,FLASH_PNOR" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR310=y diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig new file mode 100644 index 0000000000..3d91bb186e --- /dev/null +++ b/configs/spear320_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear320" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR320=y diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig new file mode 100644 index 0000000000..fd0f908d3a --- /dev/null +++ b/configs/spear320_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear320,nand" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR320=y diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig new file mode 100644 index 0000000000..6cce316460 --- /dev/null +++ b/configs/spear320_pnor_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear320,FLASH_PNOR" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR320=y diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig new file mode 100644 index 0000000000..7ad3d8413e --- /dev/null +++ b/configs/spear320_usbtty_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR320=y diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig new file mode 100644 index 0000000000..a5ad90bb05 --- /dev/null +++ b/configs/spear320_usbtty_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,nand" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR320=y diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig new file mode 100644 index 0000000000..6b110ef97a --- /dev/null +++ b/configs/spear320_usbtty_pnor_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,FLASH_PNOR" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR320=y diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig new file mode 100644 index 0000000000..f1cb0aa17a --- /dev/null +++ b/configs/spear600_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear600" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR600=y diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig new file mode 100644 index 0000000000..172c187f07 --- /dev/null +++ b/configs/spear600_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear600,nand" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR600=y diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig new file mode 100644 index 0000000000..cf8b0ec847 --- /dev/null +++ b/configs/spear600_usbtty_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR600=y diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig new file mode 100644 index 0000000000..8bd2f0776f --- /dev/null +++ b/configs/spear600_usbtty_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty,nand" +CONFIG_ARM=y +CONFIG_TARGET_SPEAR600=y diff --git a/configs/stamp9g20_defconfig b/configs/stamp9g20_defconfig new file mode 100644 index 0000000000..8c0f874c88 --- /dev/null +++ b/configs/stamp9g20_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" +CONFIG_ARM=y +CONFIG_TARGET_STAMP9G20=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig new file mode 100644 index 0000000000..a05e9917b6 --- /dev/null +++ b/configs/stv0991_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="stv0991" +CONFIG_ARM=y +CONFIG_TARGET_STV0991=y diff --git a/configs/stxgp3_defconfig b/configs/stxgp3_defconfig new file mode 100644 index 0000000000..b7537df98d --- /dev/null +++ b/configs/stxgp3_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_STXGP3=y diff --git a/configs/stxssa_4M_defconfig b/configs/stxssa_4M_defconfig new file mode 100644 index 0000000000..1ffe9f9c54 --- /dev/null +++ b/configs/stxssa_4M_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="STXSSA_4M" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_STXSSA=y diff --git a/configs/stxssa_defconfig b/configs/stxssa_defconfig new file mode 100644 index 0000000000..f1701f24bd --- /dev/null +++ b/configs/stxssa_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_STXSSA=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig new file mode 100644 index 0000000000..a85db2a235 --- /dev/null +++ b/configs/sunxi_Gemei_G9_defconfig @@ -0,0 +1,20 @@ +# Gemei G9 is an A10 based tablet, with 1G RAM, 16G NAND, +# 1024x768 IPS LCD display, stereo speakers, 1.3MP front camera and 5 MP +# rear camera, 8000mAh battery, GT901 2+1 touchscreen, Bosch BMA250 +# accelerometer and RTL8188CUS USB wifi. It also has MicroSD slot, MiniHDMI, +# 1 x MicroUSB OTG port and 1 x MicroUSB host port and 3.5mm headphone jack. +# More details are available at: http://linux-sunxi.org/Gemei_G9 +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" +CONFIG_FDTFILE="sun4i-gemei-g9.dtb" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_PANEL_LVDS=y +CONFIG_VIDEO_LCD_POWER="PH8" +CONFIG_VIDEO_LCD_BL_EN="PH7" +CONFIG_VIDEO_LCD_BL_PWM="PB2" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN4I=y ++S:CONFIG_DRAM_CLK=432 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig new file mode 100644 index 0000000000..0407c87115 --- /dev/null +++ b/configs/suvd3_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SUVD3" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_SUVD3=y diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig new file mode 100644 index 0000000000..844e67fe3a --- /dev/null +++ b/configs/sycamore_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_WALNUT=y diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig new file mode 100644 index 0000000000..c61508af34 --- /dev/null +++ b/configs/t3corp_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_T3CORP=y diff --git a/configs/taihu_defconfig b/configs/taihu_defconfig new file mode 100644 index 0000000000..ac83725130 --- /dev/null +++ b/configs/taihu_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_TAIHU=y diff --git a/configs/taishan_defconfig b/configs/taishan_defconfig new file mode 100644 index 0000000000..e956c6f856 --- /dev/null +++ b/configs/taishan_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_TAISHAN=y diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig new file mode 100644 index 0000000000..a5113890ef --- /dev/null +++ b/configs/tao3530_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_TAO3530=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig new file mode 100644 index 0000000000..438e25d84f --- /dev/null +++ b/configs/taurus_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TAURUS=y diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig new file mode 100644 index 0000000000..d2de03b649 --- /dev/null +++ b/configs/tb100_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARC=y +CONFIG_TARGET_TB100=y +CONFIG_SYS_CLK_FREQ=500000000 \ No newline at end of file diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig new file mode 100644 index 0000000000..602d691d77 --- /dev/null +++ b/configs/tbs2910_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q" +CONFIG_ARM=y +CONFIG_TARGET_TBS2910=y diff --git a/configs/tcm-bf518_defconfig b/configs/tcm-bf518_defconfig new file mode 100644 index 0000000000..0c9ae4d57e --- /dev/null +++ b/configs/tcm-bf518_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_TCM_BF518=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/tcm-bf537_defconfig b/configs/tcm-bf537_defconfig new file mode 100644 index 0000000000..6d604b6c9e --- /dev/null +++ b/configs/tcm-bf537_defconfig @@ -0,0 +1,3 @@ +CONFIG_BLACKFIN=y +CONFIG_TARGET_TCM_BF537=y +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig new file mode 100644 index 0000000000..fabd34a3f3 --- /dev/null +++ b/configs/tec-ng_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA30=y ++S:CONFIG_TARGET_TEC_NG=y +CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng" diff --git a/configs/tec_defconfig b/configs/tec_defconfig new file mode 100644 index 0000000000..d3cafa7e4b --- /dev/null +++ b/configs/tec_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_TEC=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec" diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig new file mode 100644 index 0000000000..0170655122 --- /dev/null +++ b/configs/ti814x_evm_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TI814X_EVM=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig new file mode 100644 index 0000000000..abb6c5e0bc --- /dev/null +++ b/configs/ti816x_evm_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TI816X_EVM=y diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig new file mode 100644 index 0000000000..96f7f79c44 --- /dev/null +++ b/configs/titanium_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg" +CONFIG_ARM=y +CONFIG_TARGET_TITANIUM=y diff --git a/configs/tk71_defconfig b/configs/tk71_defconfig new file mode 100644 index 0000000000..411e3c1f97 --- /dev/null +++ b/configs/tk71_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_TK71=y diff --git a/configs/tnetv107x_evm_defconfig b/configs/tnetv107x_evm_defconfig new file mode 100644 index 0000000000..b0915d2026 --- /dev/null +++ b/configs/tnetv107x_evm_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_TNETV107X_EVM=y diff --git a/configs/tny_a9260_eeprom_defconfig b/configs/tny_a9260_eeprom_defconfig new file mode 100644 index 0000000000..a662669d96 --- /dev/null +++ b/configs/tny_a9260_eeprom_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_EEPROM" +CONFIG_ARM=y +CONFIG_TARGET_TNY_A9260=y diff --git a/configs/tny_a9260_nandflash_defconfig b/configs/tny_a9260_nandflash_defconfig new file mode 100644 index 0000000000..41fd9c1192 --- /dev/null +++ b/configs/tny_a9260_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_TNY_A9260=y diff --git a/configs/tny_a9g20_eeprom_defconfig b/configs/tny_a9g20_eeprom_defconfig new file mode 100644 index 0000000000..a2eb60ef71 --- /dev/null +++ b/configs/tny_a9g20_eeprom_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_EEPROM" +CONFIG_ARM=y +CONFIG_TARGET_TNY_A9260=y diff --git a/configs/tny_a9g20_nandflash_defconfig b/configs/tny_a9g20_nandflash_defconfig new file mode 100644 index 0000000000..60ebfa2512 --- /dev/null +++ b/configs/tny_a9g20_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_TNY_A9260=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig new file mode 100644 index 0000000000..4ee9238969 --- /dev/null +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_MMC_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_TQMA6=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig new file mode 100644 index 0000000000..86d4ca33ff --- /dev/null +++ b/configs/tqma6q_mba6_spi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_SPI_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_TQMA6=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig new file mode 100644 index 0000000000..5efce6ab4d --- /dev/null +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_MMC_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_TQMA6=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig new file mode 100644 index 0000000000..e8b3afdbbc --- /dev/null +++ b/configs/tqma6s_mba6_spi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_SPI_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_TQMA6=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig new file mode 100644 index 0000000000..1b98b739da --- /dev/null +++ b/configs/trats2_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_TRATS2=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2" diff --git a/configs/trats_defconfig b/configs/trats_defconfig new file mode 100644 index 0000000000..901a014734 --- /dev/null +++ b/configs/trats_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_TRATS=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats" diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig new file mode 100644 index 0000000000..7ea5e02f5e --- /dev/null +++ b/configs/tricorder_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_TRICORDER=y diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig new file mode 100644 index 0000000000..f6e1c464aa --- /dev/null +++ b/configs/tricorder_flash_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_TRICORDER=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig new file mode 100644 index 0000000000..0b2a6d0292 --- /dev/null +++ b/configs/trimslice_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_TRIMSLICE=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice" diff --git a/configs/trizepsiv_defconfig b/configs/trizepsiv_defconfig new file mode 100644 index 0000000000..444d3bbe95 --- /dev/null +++ b/configs/trizepsiv_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_TRIZEPSIV=y diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig new file mode 100644 index 0000000000..6eda869fbe --- /dev/null +++ b/configs/tseries_mmc_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TSERIES=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig new file mode 100644 index 0000000000..bd06d83efd --- /dev/null +++ b/configs/tseries_nand_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TSERIES=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig new file mode 100644 index 0000000000..32ccc4e007 --- /dev/null +++ b/configs/tseries_spi_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TSERIES=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/tt01_defconfig b/configs/tt01_defconfig new file mode 100644 index 0000000000..a0e6664522 --- /dev/null +++ b/configs/tt01_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_TT01=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig new file mode 100644 index 0000000000..c1c9c43cdb --- /dev/null +++ b/configs/tuge1_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="TUGE1" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_TUXX1=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig new file mode 100644 index 0000000000..ecea63f5f9 --- /dev/null +++ b/configs/tuxx1_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="TUXX1" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_TUXX1=y diff --git a/configs/twister_defconfig b/configs/twister_defconfig new file mode 100644 index 0000000000..902373601a --- /dev/null +++ b/configs/twister_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_TWISTER=y diff --git a/configs/tx25_defconfig b/configs/tx25_defconfig new file mode 100644 index 0000000000..0cbc4ee37b --- /dev/null +++ b/configs/tx25_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX25=y diff --git a/configs/tx28-40x1_defconfig b/configs/tx28-40x1_defconfig new file mode 100644 index 0000000000..c24af64f73 --- /dev/null +++ b/configs/tx28-40x1_defconfig @@ -0,0 +1,38 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX28=y ++S:CONFIG_TARGET_TX28_40X1=y ++S:CONFIG_TX28_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_ENV_IS_IN_NAND=y +S:CONFIG_ENV_IS_NOWHERE=y +CONFIG_FEC_MXC=y +CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MXS_MMC=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_MXS=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx28-40x1_noenv_defconfig b/configs/tx28-40x1_noenv_defconfig new file mode 100644 index 0000000000..84b0454292 --- /dev/null +++ b/configs/tx28-40x1_noenv_defconfig @@ -0,0 +1,36 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX28=y ++S:CONFIG_TARGET_TX28_40X1=y ++S:CONFIG_TX28_UBOOT_NOENV=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_FEC_MXC=y +CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MXS_MMC=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_MXS=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx28-40x2_defconfig b/configs/tx28-40x2_defconfig new file mode 100644 index 0000000000..f84c66ec62 --- /dev/null +++ b/configs/tx28-40x2_defconfig @@ -0,0 +1,38 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX28=y ++S:CONFIG_TARGET_TX28_40X1=y ++S:CONFIG_TX28_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_ENV_IS_IN_NAND=y +S:CONFIG_ENV_IS_NOWHERE=y +CONFIG_FEC_MXC=y +CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MXS_MMC=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_MXS=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx28-40x2_noenv_defconfig b/configs/tx28-40x2_noenv_defconfig new file mode 100644 index 0000000000..942c540f9f --- /dev/null +++ b/configs/tx28-40x2_noenv_defconfig @@ -0,0 +1,36 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX28=y ++S:CONFIG_TARGET_TX28_40X1=y ++S:CONFIG_TX28_UBOOT_NOENV=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_FEC_MXC=y +CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MXS_MMC=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_MXS=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx28-40x3_defconfig b/configs/tx28-40x3_defconfig new file mode 100644 index 0000000000..311022df08 --- /dev/null +++ b/configs/tx28-40x3_defconfig @@ -0,0 +1,38 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX28=y ++S:CONFIG_TARGET_TX28_40X1=y ++S:CONFIG_TX28_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_ENV_IS_IN_NAND=y +S:CONFIG_ENV_IS_NOWHERE=y +CONFIG_FEC_MXC=y +CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MXS_MMC=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_MXS=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx28-40x3_noenv_defconfig b/configs/tx28-40x3_noenv_defconfig new file mode 100644 index 0000000000..28fa3a2aa1 --- /dev/null +++ b/configs/tx28-40x3_noenv_defconfig @@ -0,0 +1,36 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX28=y ++S:CONFIG_TARGET_TX28_40X1=y ++S:CONFIG_TX28_UBOOT_NOENV=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_FEC_MXC=y +CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MXS_MMC=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_MXS=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx28-41x0_defconfig b/configs/tx28-41x0_defconfig new file mode 100644 index 0000000000..c5861bc097 --- /dev/null +++ b/configs/tx28-41x0_defconfig @@ -0,0 +1,38 @@ +CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX28=y ++S:CONFIG_TARGET_TX28_41X0=y ++S:CONFIG_TX28_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_ENV_IS_IN_NAND=y +S:CONFIG_ENV_IS_NOWHERE=y +CONFIG_FEC_MXC=y +CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MXS_MMC=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_MXS=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx28-41x0_noenv_defconfig b/configs/tx28-41x0_noenv_defconfig new file mode 100644 index 0000000000..a707d599a4 --- /dev/null +++ b/configs/tx28-41x0_noenv_defconfig @@ -0,0 +1,36 @@ +CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX28=y ++S:CONFIG_TARGET_TX28_41X0=y ++S:CONFIG_TX28_UBOOT_NOENV=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_FEC_MXC=y +CONFIG_GET_FEC_MAC_ADDR_FROM_IIM=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MXS_MMC=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_MXS=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx48_defconfig b/configs/tx48_defconfig new file mode 100644 index 0000000000..9105d2a36a --- /dev/null +++ b/configs/tx48_defconfig @@ -0,0 +1,33 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_MPU_CLK=720,SYS_DDR_CLK=400" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TX48=y ++S:CONFIG_TX48_UBOOT=y +CONFIG_BOOTP_DNS=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_CMD_BOOTCE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PING=y +CONFIG_CMD_ROMUPDATE=y +CONFIG_CMD_TIME=y ++S:CONFIG_DOS_PARTITION=y +CONFIG_DM=y +CONFIG_ENV_IS_IN_NAND=y +S:CONFIG_ENV_IS_NOWHERE=y +CONFIG_LCD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y ++S:CONFIG_NAND=y ++S:CONFIG_NAND_OMAP_GPMC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx51-8xx0_defconfig b/configs/tx51-8xx0_defconfig new file mode 100644 index 0000000000..a29602ba80 --- /dev/null +++ b/configs/tx51-8xx0_defconfig @@ -0,0 +1,20 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800" +CONFIG_ARM=y +CONFIG_TARGET_TX51=y +CONFIG_TARGET_TX51_8XX0=y +CONFIG_TX51_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx51-8xx0_noenv_defconfig b/configs/tx51-8xx0_noenv_defconfig new file mode 100644 index 0000000000..7b6ff0d040 --- /dev/null +++ b/configs/tx51-8xx0_noenv_defconfig @@ -0,0 +1,20 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800" +CONFIG_ARM=y +CONFIG_TARGET_TX51=y +CONFIG_TARGET_TX51_8XX0=y +CONFIG_TX51_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_NOWHERE=y diff --git a/configs/tx51-8xx1_2_defconfig b/configs/tx51-8xx1_2_defconfig new file mode 100644 index 0000000000..97ba9786ce --- /dev/null +++ b/configs/tx51-8xx1_2_defconfig @@ -0,0 +1,20 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800" +CONFIG_ARM=y +CONFIG_TARGET_TX51=y +CONFIG_TARGET_TX51_8XX1_2=y +CONFIG_TX51_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx51-8xx1_2_noenv_defconfig b/configs/tx51-8xx1_2_noenv_defconfig new file mode 100644 index 0000000000..0af017c883 --- /dev/null +++ b/configs/tx51-8xx1_2_noenv_defconfig @@ -0,0 +1,20 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800" +CONFIG_ARM=y +CONFIG_TARGET_TX51=y +CONFIG_TARGET_TX51_8XX1_2=y +CONFIG_TX51_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_NOWHERE=y diff --git a/configs/tx53-1232_defconfig b/configs/tx53-1232_defconfig new file mode 100644 index 0000000000..0fcb12c450 --- /dev/null +++ b/configs/tx53-1232_defconfig @@ -0,0 +1,22 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_2G" +CONFIG_ARM=y +CONFIG_TARGET_TX53=y +CONFIG_TARGET_TX53_1232=y +CONFIG_TX53_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx53-1232_sec_defconfig b/configs/tx53-1232_sec_defconfig new file mode 100644 index 0000000000..6fe8485392 --- /dev/null +++ b/configs/tx53-1232_sec_defconfig @@ -0,0 +1,22 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_SIZE=SZ_2G" +CONFIG_ARM=y +CONFIG_TARGET_TX53=y +CONFIG_TARGET_TX53_1232=y +CONFIG_TX53_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx53-x030_defconfig b/configs/tx53-x030_defconfig new file mode 100644 index 0000000000..25dcf97d92 --- /dev/null +++ b/configs/tx53-x030_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_TARGET_TX53=y +CONFIG_TARGET_TX53_X030=y +CONFIG_TX53_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx53-x030_sec_defconfig b/configs/tx53-x030_sec_defconfig new file mode 100644 index 0000000000..f39b3e5398 --- /dev/null +++ b/configs/tx53-x030_sec_defconfig @@ -0,0 +1,22 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_TX53=y +CONFIG_TARGET_TX53_X030=y +CONFIG_TX53_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx53-x130_defconfig b/configs/tx53-x130_defconfig new file mode 100644 index 0000000000..9e8eb1a40b --- /dev/null +++ b/configs/tx53-x130_defconfig @@ -0,0 +1,22 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_TARGET_TX53=y +CONFIG_TARGET_TX53_X130=y +CONFIG_TX53_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx53-x130_sec_defconfig b/configs/tx53-x130_sec_defconfig new file mode 100644 index 0000000000..e7af1aa837 --- /dev/null +++ b/configs/tx53-x130_sec_defconfig @@ -0,0 +1,22 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF,SECURE_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_TX53=y +CONFIG_TARGET_TX53_X130=y +CONFIG_TX53_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx53-x131_defconfig b/configs/tx53-x131_defconfig new file mode 100644 index 0000000000..b74eb354fd --- /dev/null +++ b/configs/tx53-x131_defconfig @@ -0,0 +1,22 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_TARGET_TX53=y +CONFIG_TARGET_TX53_X131=y +CONFIG_TX53_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx53-x131_sec_defconfig b/configs/tx53-x131_sec_defconfig new file mode 100644 index 0000000000..41adf69023 --- /dev/null +++ b/configs/tx53-x131_sec_defconfig @@ -0,0 +1,22 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF,SECURE_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_TX53=y +CONFIG_TARGET_TX53_X131=y +CONFIG_TX53_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/tx6q-1020_defconfig b/configs/tx6q-1020_defconfig new file mode 100644 index 0000000000..b03729a19c --- /dev/null +++ b/configs/tx6q-1020_defconfig @@ -0,0 +1,28 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2" +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_1020=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-1020_mfg_defconfig b/configs/tx6q-1020_mfg_defconfig new file mode 100644 index 0000000000..d354c782d0 --- /dev/null +++ b/configs/tx6q-1020_mfg_defconfig @@ -0,0 +1,27 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2" +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_1020=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-1020_noenv_defconfig b/configs/tx6q-1020_noenv_defconfig new file mode 100644 index 0000000000..f8d3f4d81e --- /dev/null +++ b/configs/tx6q-1020_noenv_defconfig @@ -0,0 +1,27 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2" +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_1020=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-1020_sec_defconfig b/configs/tx6q-1020_sec_defconfig new file mode 100644 index 0000000000..66dc59b180 --- /dev/null +++ b/configs/tx6q-1020_sec_defconfig @@ -0,0 +1,28 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2,SECURE_BOOT" +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_1020=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-10x0_defconfig b/configs/tx6q-10x0_defconfig new file mode 100644 index 0000000000..91960a8fb9 --- /dev/null +++ b/configs/tx6q-10x0_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_10X0=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-10x0_mfg_defconfig b/configs/tx6q-10x0_mfg_defconfig new file mode 100644 index 0000000000..20e3d1a255 --- /dev/null +++ b/configs/tx6q-10x0_mfg_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_10X0=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-10x0_noenv_defconfig b/configs/tx6q-10x0_noenv_defconfig new file mode 100644 index 0000000000..b896343293 --- /dev/null +++ b/configs/tx6q-10x0_noenv_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_10X0=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-10x0_sec_defconfig b/configs/tx6q-10x0_sec_defconfig new file mode 100644 index 0000000000..f3b4fd9b7f --- /dev/null +++ b/configs/tx6q-10x0_sec_defconfig @@ -0,0 +1,26 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_10X0=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y diff --git a/configs/tx6q-11x0_defconfig b/configs/tx6q-11x0_defconfig new file mode 100644 index 0000000000..adb4622370 --- /dev/null +++ b/configs/tx6q-11x0_defconfig @@ -0,0 +1,30 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_11X0=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-11x0_mfg_defconfig b/configs/tx6q-11x0_mfg_defconfig new file mode 100644 index 0000000000..91e13853db --- /dev/null +++ b/configs/tx6q-11x0_mfg_defconfig @@ -0,0 +1,29 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_11X0=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6q-11x0_noenv_defconfig b/configs/tx6q-11x0_noenv_defconfig new file mode 100644 index 0000000000..6068f63e9a --- /dev/null +++ b/configs/tx6q-11x0_noenv_defconfig @@ -0,0 +1,29 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6Q=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6Q_11X0=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6s-8034_defconfig b/configs/tx6s-8034_defconfig new file mode 100644 index 0000000000..8e65cbf0d0 --- /dev/null +++ b/configs/tx6s-8034_defconfig @@ -0,0 +1,30 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16" +CONFIG_ARM=y +CONFIG_SOC_MX6S=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6S_8034=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6s-8034_mfg_defconfig b/configs/tx6s-8034_mfg_defconfig new file mode 100644 index 0000000000..cca3102919 --- /dev/null +++ b/configs/tx6s-8034_mfg_defconfig @@ -0,0 +1,29 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16" +CONFIG_ARM=y +CONFIG_SOC_MX6S=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6S_8034=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6s-8034_noenv_defconfig b/configs/tx6s-8034_noenv_defconfig new file mode 100644 index 0000000000..f5078658cf --- /dev/null +++ b/configs/tx6s-8034_noenv_defconfig @@ -0,0 +1,29 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16" +CONFIG_ARM=y +CONFIG_SOC_MX6S=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6S_8034=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6s-8034_sec_defconfig b/configs/tx6s-8034_sec_defconfig new file mode 100644 index 0000000000..3462556905 --- /dev/null +++ b/configs/tx6s-8034_sec_defconfig @@ -0,0 +1,30 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16,SECURE_BOOT" +CONFIG_ARM=y +CONFIG_SOC_MX6S=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6S_8034=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6s-8035_defconfig b/configs/tx6s-8035_defconfig new file mode 100644 index 0000000000..874704a249 --- /dev/null +++ b/configs/tx6s-8035_defconfig @@ -0,0 +1,28 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32" +CONFIG_ARM=y +CONFIG_SOC_MX6S=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6S_8035=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6s-8035_mfg_defconfig b/configs/tx6s-8035_mfg_defconfig new file mode 100644 index 0000000000..158c9b9156 --- /dev/null +++ b/configs/tx6s-8035_mfg_defconfig @@ -0,0 +1,26 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32" +CONFIG_ARM=y +CONFIG_SOC_MX6S=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6S_8035=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6s-8035_noenv_defconfig b/configs/tx6s-8035_noenv_defconfig new file mode 100644 index 0000000000..f704e1772d --- /dev/null +++ b/configs/tx6s-8035_noenv_defconfig @@ -0,0 +1,27 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32" +CONFIG_ARM=y +CONFIG_SOC_MX6S=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6S_8035=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8011_defconfig b/configs/tx6u-8011_defconfig new file mode 100644 index 0000000000..c055fb15d2 --- /dev/null +++ b/configs/tx6u-8011_defconfig @@ -0,0 +1,30 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8011=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8011_mfg_defconfig b/configs/tx6u-8011_mfg_defconfig new file mode 100644 index 0000000000..5e1b5cf478 --- /dev/null +++ b/configs/tx6u-8011_mfg_defconfig @@ -0,0 +1,28 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8011=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8011_noenv_defconfig b/configs/tx6u-8011_noenv_defconfig new file mode 100644 index 0000000000..c1cc683e2d --- /dev/null +++ b/configs/tx6u-8011_noenv_defconfig @@ -0,0 +1,29 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8011=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8012_defconfig b/configs/tx6u-8012_defconfig new file mode 100644 index 0000000000..86e8ce8424 --- /dev/null +++ b/configs/tx6u-8012_defconfig @@ -0,0 +1,30 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8012=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8012_mfg_defconfig b/configs/tx6u-8012_mfg_defconfig new file mode 100644 index 0000000000..722b295b3e --- /dev/null +++ b/configs/tx6u-8012_mfg_defconfig @@ -0,0 +1,28 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8012=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8012_noenv_defconfig b/configs/tx6u-8012_noenv_defconfig new file mode 100644 index 0000000000..e2c4819005 --- /dev/null +++ b/configs/tx6u-8012_noenv_defconfig @@ -0,0 +1,29 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8012=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8012_sec_defconfig b/configs/tx6u-8012_sec_defconfig new file mode 100644 index 0000000000..4d7e3bcf3e --- /dev/null +++ b/configs/tx6u-8012_sec_defconfig @@ -0,0 +1,26 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048,SECURE_BOOT" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8012=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y diff --git a/configs/tx6u-8033_defconfig b/configs/tx6u-8033_defconfig new file mode 100644 index 0000000000..6e37e6b16e --- /dev/null +++ b/configs/tx6u-8033_defconfig @@ -0,0 +1,28 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8033=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8033_mfg_defconfig b/configs/tx6u-8033_mfg_defconfig new file mode 100644 index 0000000000..4597a1d7d5 --- /dev/null +++ b/configs/tx6u-8033_mfg_defconfig @@ -0,0 +1,27 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8033=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8033_noenv_defconfig b/configs/tx6u-8033_noenv_defconfig new file mode 100644 index 0000000000..eeb1615aec --- /dev/null +++ b/configs/tx6u-8033_noenv_defconfig @@ -0,0 +1,27 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8033=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8033_sec_defconfig b/configs/tx6u-8033_sec_defconfig new file mode 100644 index 0000000000..566a1551bb --- /dev/null +++ b/configs/tx6u-8033_sec_defconfig @@ -0,0 +1,26 @@ +CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_8033=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y diff --git a/configs/tx6u-80x0_defconfig b/configs/tx6u-80x0_defconfig new file mode 100644 index 0000000000..dd728acd74 --- /dev/null +++ b/configs/tx6u-80x0_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_80X0=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-80x0_mfg_defconfig b/configs/tx6u-80x0_mfg_defconfig new file mode 100644 index 0000000000..939016e68d --- /dev/null +++ b/configs/tx6u-80x0_mfg_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_80X0=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-80x0_noenv_defconfig b/configs/tx6u-80x0_noenv_defconfig new file mode 100644 index 0000000000..39654718f0 --- /dev/null +++ b/configs/tx6u-80x0_noenv_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_80X0=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-80x0_sec_defconfig b/configs/tx6u-80x0_sec_defconfig new file mode 100644 index 0000000000..f1fc096022 --- /dev/null +++ b/configs/tx6u-80x0_sec_defconfig @@ -0,0 +1,26 @@ +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_80X0=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y diff --git a/configs/tx6u-8111_defconfig b/configs/tx6u-8111_defconfig new file mode 100644 index 0000000000..0c61bc5524 --- /dev/null +++ b/configs/tx6u-8111_defconfig @@ -0,0 +1,30 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_81X0=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8111_mfg_defconfig b/configs/tx6u-8111_mfg_defconfig new file mode 100644 index 0000000000..91770aa821 --- /dev/null +++ b/configs/tx6u-8111_mfg_defconfig @@ -0,0 +1,28 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_81X0=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-8111_noenv_defconfig b/configs/tx6u-8111_noenv_defconfig new file mode 100644 index 0000000000..9dd4b893a6 --- /dev/null +++ b/configs/tx6u-8111_noenv_defconfig @@ -0,0 +1,29 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_81X0=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-81x0_defconfig b/configs/tx6u-81x0_defconfig new file mode 100644 index 0000000000..88b267c4f5 --- /dev/null +++ b/configs/tx6u-81x0_defconfig @@ -0,0 +1,30 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_81X0=y +CONFIG_TX6_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-81x0_mfg_defconfig b/configs/tx6u-81x0_mfg_defconfig new file mode 100644 index 0000000000..b9b4bdedd6 --- /dev/null +++ b/configs/tx6u-81x0_mfg_defconfig @@ -0,0 +1,28 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_81X0=y +CONFIG_TX6_UBOOT_MFG=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/tx6u-81x0_noenv_defconfig b/configs/tx6u-81x0_noenv_defconfig new file mode 100644 index 0000000000..616429a3c7 --- /dev/null +++ b/configs/tx6u-81x0_noenv_defconfig @@ -0,0 +1,29 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF" +CONFIG_ARM=y +CONFIG_SOC_MX6DL=y +CONFIG_TARGET_TX6=y +CONFIG_TARGET_TX6U_81X0=y +CONFIG_TX6_UBOOT_NOENV=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_USDHC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DOS_PARTITION=y +CONFIG_FEC_MXC_PHYADDR=0 +CONFIG_MXC_OCOTP=y +CONFIG_CMD_FUSE=y +CONFIG_PHY_SMSC=y diff --git a/configs/txa5-5010_defconfig b/configs/txa5-5010_defconfig new file mode 100644 index 0000000000..78bec57fdd --- /dev/null +++ b/configs/txa5-5010_defconfig @@ -0,0 +1,18 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_TXA5=y +CONFIG_TARGET_TXA5_5010=y +CONFIG_TXA5_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +#CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/txa5-5011_defconfig b/configs/txa5-5011_defconfig new file mode 100644 index 0000000000..a184de8eb9 --- /dev/null +++ b/configs/txa5-5011_defconfig @@ -0,0 +1,18 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" +CONFIG_ARM=y +CONFIG_TARGET_TXA5=y +CONFIG_TARGET_TXA5_5011=y +CONFIG_TXA5_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +#CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/u8500_href_defconfig b/configs/u8500_href_defconfig new file mode 100644 index 0000000000..fef179f411 --- /dev/null +++ b/configs/u8500_href_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_U8500_HREF=y diff --git a/configs/udoo_quad_defconfig b/configs/udoo_quad_defconfig new file mode 100644 index 0000000000..860a310113 --- /dev/null +++ b/configs/udoo_quad_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024" +CONFIG_ARM=y +CONFIG_TARGET_UDOO=y diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig new file mode 100644 index 0000000000..8c0ac11ed9 --- /dev/null +++ b/configs/usb_a9263_dataflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" +CONFIG_ARM=y +CONFIG_TARGET_USB_A9263=y diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig new file mode 100644 index 0000000000..811354c3d1 --- /dev/null +++ b/configs/v38b_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC5xxx=y +CONFIG_TARGET_V38B=y diff --git a/configs/v5fx30teval_defconfig b/configs/v5fx30teval_defconfig new file mode 100644 index 0000000000..bb58153c1f --- /dev/null +++ b/configs/v5fx30teval_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_V5FX30TEVAL=y diff --git a/configs/v5fx30teval_flash_defconfig b/configs/v5fx30teval_flash_defconfig new file mode 100644 index 0000000000..1c6ec89cd6 --- /dev/null +++ b/configs/v5fx30teval_flash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_V5FX30TEVAL=y diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig new file mode 100644 index 0000000000..32e9e8cc6d --- /dev/null +++ b/configs/vct_platinum_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUM=y diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig new file mode 100644 index 0000000000..4346518a18 --- /dev/null +++ b/configs/vct_platinum_onenand_defconfig @@ -0,0 +1,5 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUM=y +CONFIG_VCT_ONENAND=y diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig new file mode 100644 index 0000000000..fd52282966 --- /dev/null +++ b/configs/vct_platinum_onenand_small_defconfig @@ -0,0 +1,7 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUM=y +CONFIG_VCT_ONENAND=y +CONFIG_VCT_SMALL_IMAGE=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig new file mode 100644 index 0000000000..58f956d7db --- /dev/null +++ b/configs/vct_platinum_small_defconfig @@ -0,0 +1,6 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUM=y +CONFIG_VCT_SMALL_IMAGE=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig new file mode 100644 index 0000000000..732565cb96 --- /dev/null +++ b/configs/vct_platinumavc_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUMAVC=y diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig new file mode 100644 index 0000000000..670e7f92da --- /dev/null +++ b/configs/vct_platinumavc_onenand_defconfig @@ -0,0 +1,5 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUMAVC=y +CONFIG_VCT_ONENAND=y diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig new file mode 100644 index 0000000000..31a4948e70 --- /dev/null +++ b/configs/vct_platinumavc_onenand_small_defconfig @@ -0,0 +1,7 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUMAVC=y +CONFIG_VCT_ONENAND=y +CONFIG_VCT_SMALL_IMAGE=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig new file mode 100644 index 0000000000..ce00a6c0f1 --- /dev/null +++ b/configs/vct_platinumavc_small_defconfig @@ -0,0 +1,6 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUMAVC=y +CONFIG_VCT_SMALL_IMAGE=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig new file mode 100644 index 0000000000..a19e65d7e6 --- /dev/null +++ b/configs/vct_premium_defconfig @@ -0,0 +1,4 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PREMIUM=y diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig new file mode 100644 index 0000000000..092d0f79d3 --- /dev/null +++ b/configs/vct_premium_onenand_defconfig @@ -0,0 +1,5 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PREMIUM=y +CONFIG_VCT_ONENAND=y diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig new file mode 100644 index 0000000000..eabfb88e0c --- /dev/null +++ b/configs/vct_premium_onenand_small_defconfig @@ -0,0 +1,7 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PREMIUM=y +CONFIG_VCT_ONENAND=y +CONFIG_VCT_SMALL_IMAGE=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig new file mode 100644 index 0000000000..1ce0efd273 --- /dev/null +++ b/configs/vct_premium_small_defconfig @@ -0,0 +1,6 @@ +CONFIG_MIPS=y +CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PREMIUM=y +CONFIG_VCT_SMALL_IMAGE=y +# CONFIG_CMD_CRC32 is not set diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig new file mode 100644 index 0000000000..462c4827cd --- /dev/null +++ b/configs/ve8313_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_VE8313=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig new file mode 100644 index 0000000000..c12dae933f --- /dev/null +++ b/configs/venice2_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA124=y ++S:CONFIG_TARGET_VENICE2=y +CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2" diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig new file mode 100644 index 0000000000..f62ab6b17a --- /dev/null +++ b/configs/ventana_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_VENTANA=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana" diff --git a/configs/versatileab_defconfig b/configs/versatileab_defconfig new file mode 100644 index 0000000000..94680fef21 --- /dev/null +++ b/configs/versatileab_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB" +CONFIG_ARM=y +CONFIG_ARCH_VERSATILE=y diff --git a/configs/versatilepb_defconfig b/configs/versatilepb_defconfig new file mode 100644 index 0000000000..2c59e5c510 --- /dev/null +++ b/configs/versatilepb_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB" +CONFIG_ARM=y +CONFIG_ARCH_VERSATILE=y diff --git a/configs/versatileqemu_defconfig b/configs/versatileqemu_defconfig new file mode 100644 index 0000000000..fb0485d985 --- /dev/null +++ b/configs/versatileqemu_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB" +CONFIG_ARM=y +CONFIG_ARCH_VERSATILE=y diff --git a/configs/vexpress_aemv8a_defconfig b/configs/vexpress_aemv8a_defconfig new file mode 100644 index 0000000000..9f4b876556 --- /dev/null +++ b/configs/vexpress_aemv8a_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_TARGET_VEXPRESS64_AEMV8A=y +CONFIG_DEFAULT_DEVICE_TREE="vexpress64" diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig new file mode 100644 index 0000000000..d28a4286e5 --- /dev/null +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -0,0 +1,5 @@ +# ARM Ltd. Juno Board Reference Design +CONFIG_ARM=y +CONFIG_TARGET_VEXPRESS64_JUNO=y +CONFIG_DEFAULT_DEVICE_TREE="vexpress64" +CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig new file mode 100644 index 0000000000..26cf7db47f --- /dev/null +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -0,0 +1,4 @@ +# Semihosted FVP fast model +CONFIG_ARM=y +CONFIG_TARGET_VEXPRESS64_BASE_FVP=y +CONFIG_DEFAULT_DEVICE_TREE="vexpress64" diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig new file mode 100644 index 0000000000..ee5b351b86 --- /dev/null +++ b/configs/vexpress_ca15_tc2_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_VEXPRESS_CA15_TC2=y diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig new file mode 100644 index 0000000000..fafed03ad1 --- /dev/null +++ b/configs/vexpress_ca5x2_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_VEXPRESS_CA5X2=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig new file mode 100644 index 0000000000..1ff2ebfa62 --- /dev/null +++ b/configs/vexpress_ca9x4_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_VEXPRESS_CA9X4=y diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig new file mode 100644 index 0000000000..7de374a406 --- /dev/null +++ b/configs/vf610twr_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC" +CONFIG_ARM=y +CONFIG_TARGET_VF610TWR=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig new file mode 100644 index 0000000000..e78db26ff6 --- /dev/null +++ b/configs/vf610twr_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_ARM=y +CONFIG_TARGET_VF610TWR=y diff --git a/configs/vision2_defconfig b/configs/vision2_defconfig new file mode 100644 index 0000000000..430dbc0235 --- /dev/null +++ b/configs/vision2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg" +CONFIG_ARM=y +CONFIG_TARGET_VISION2=y diff --git a/configs/vl_ma2sc_defconfig b/configs/vl_ma2sc_defconfig new file mode 100644 index 0000000000..39cd7258e5 --- /dev/null +++ b/configs/vl_ma2sc_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_VL_MA2SC=y diff --git a/configs/vl_ma2sc_ram_defconfig b/configs/vl_ma2sc_ram_defconfig new file mode 100644 index 0000000000..70a07abe65 --- /dev/null +++ b/configs/vl_ma2sc_ram_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMLOAD" +CONFIG_ARM=y +CONFIG_TARGET_VL_MA2SC=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig new file mode 100644 index 0000000000..8df2cfd742 --- /dev/null +++ b/configs/vme8349_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_VME8349=y diff --git a/configs/vpac270_nor_128_defconfig b/configs/vpac270_nor_128_defconfig new file mode 100644 index 0000000000..74609ab097 --- /dev/null +++ b/configs/vpac270_nor_128_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M" +CONFIG_ARM=y +CONFIG_TARGET_VPAC270=y diff --git a/configs/vpac270_nor_256_defconfig b/configs/vpac270_nor_256_defconfig new file mode 100644 index 0000000000..d6163ef74f --- /dev/null +++ b/configs/vpac270_nor_256_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M" +CONFIG_ARM=y +CONFIG_TARGET_VPAC270=y diff --git a/configs/vpac270_ond_256_defconfig b/configs/vpac270_ond_256_defconfig new file mode 100644 index 0000000000..2a536a564c --- /dev/null +++ b/configs/vpac270_ond_256_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_VPAC270=y diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig new file mode 100644 index 0000000000..844e67fe3a --- /dev/null +++ b/configs/walnut_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_WALNUT=y diff --git a/configs/wandboard_dl_defconfig b/configs/wandboard_dl_defconfig new file mode 100644 index 0000000000..5a1f7f54dc --- /dev/null +++ b/configs/wandboard_dl_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" +CONFIG_ARM=y +CONFIG_TARGET_WANDBOARD=y diff --git a/configs/wandboard_quad_defconfig b/configs/wandboard_quad_defconfig new file mode 100644 index 0000000000..d940848cca --- /dev/null +++ b/configs/wandboard_quad_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" +CONFIG_ARM=y +CONFIG_TARGET_WANDBOARD=y diff --git a/configs/wandboard_solo_defconfig b/configs/wandboard_solo_defconfig new file mode 100644 index 0000000000..66aa5d395b --- /dev/null +++ b/configs/wandboard_solo_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" +CONFIG_ARM=y +CONFIG_TARGET_WANDBOARD=y diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig new file mode 100644 index 0000000000..9553eb8664 --- /dev/null +++ b/configs/whistler_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA20=y ++S:CONFIG_TARGET_WHISTLER=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler" diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig new file mode 100644 index 0000000000..580e5ce61f --- /dev/null +++ b/configs/wireless_space_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_WIRELESS_SPACE=y diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig new file mode 100644 index 0000000000..9f96bd9a09 --- /dev/null +++ b/configs/woodburn_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_WOODBURN=y diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig new file mode 100644 index 0000000000..d3dcb3c3c1 --- /dev/null +++ b/configs/woodburn_sd_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_WOODBURN_SD=y diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig new file mode 100644 index 0000000000..2ccddc1bbc --- /dev/null +++ b/configs/wtk_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U" +CONFIG_PPC=y +CONFIG_8xx=y +CONFIG_TARGET_TQM823L=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig new file mode 100644 index 0000000000..cb66890498 --- /dev/null +++ b/configs/x600_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_X600=y diff --git a/configs/xaeniax_defconfig b/configs/xaeniax_defconfig new file mode 100644 index 0000000000..52e301ca33 --- /dev/null +++ b/configs/xaeniax_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_XAENIAX=y diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig new file mode 100644 index 0000000000..737db40959 --- /dev/null +++ b/configs/xfi3_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_XFI3=y diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig new file mode 100644 index 0000000000..691412cb6e --- /dev/null +++ b/configs/xilinx-ppc405-generic_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_XILINX_PPC405_GENERIC=y diff --git a/configs/xilinx-ppc405-generic_flash_defconfig b/configs/xilinx-ppc405-generic_flash_defconfig new file mode 100644 index 0000000000..317b63d4a7 --- /dev/null +++ b/configs/xilinx-ppc405-generic_flash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_XILINX_PPC405_GENERIC=y diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig new file mode 100644 index 0000000000..31ce75b872 --- /dev/null +++ b/configs/xilinx-ppc440-generic_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_XILINX_PPC440_GENERIC=y diff --git a/configs/xilinx-ppc440-generic_flash_defconfig b/configs/xilinx-ppc440-generic_flash_defconfig new file mode 100644 index 0000000000..635926ffba --- /dev/null +++ b/configs/xilinx-ppc440-generic_flash_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_XILINX_PPC440_GENERIC=y diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig new file mode 100644 index 0000000000..635da2658c --- /dev/null +++ b/configs/xpedite1000_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_XPEDITE1000=y diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig new file mode 100644 index 0000000000..b8513c1a1c --- /dev/null +++ b/configs/xpedite517x_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC86xx=y +CONFIG_TARGET_XPEDITE517X=y diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig new file mode 100644 index 0000000000..d5f526d54e --- /dev/null +++ b/configs/xpedite520x_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_XPEDITE520X=y diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig new file mode 100644 index 0000000000..8001dd13a9 --- /dev/null +++ b/configs/xpedite537x_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_XPEDITE537X=y diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig new file mode 100644 index 0000000000..dc33ca9a4f --- /dev/null +++ b/configs/xpedite550x_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_XPEDITE550X=y diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig new file mode 100644 index 0000000000..843095be16 --- /dev/null +++ b/configs/yellowstone_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_YOSEMITE=y diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig new file mode 100644 index 0000000000..d5eea68c04 --- /dev/null +++ b/configs/yosemite_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_YOSEMITE=y diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig new file mode 100644 index 0000000000..6c8e20a36e --- /dev/null +++ b/configs/yucca_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_YUCCA=y diff --git a/configs/zeus_defconfig b/configs/zeus_defconfig new file mode 100644 index 0000000000..546f10ae8b --- /dev/null +++ b/configs/zeus_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_ZEUS=y diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig new file mode 100644 index 0000000000..8d921a0bfe --- /dev/null +++ b/configs/zipitz2_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_ZIPITZ2=y diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig new file mode 100644 index 0000000000..80a66d03fd --- /dev/null +++ b/configs/zmx25_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_ZMX25=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig new file mode 100644 index 0000000000..8b985fe5a4 --- /dev/null +++ b/configs/zynq_microzed_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ZYNQ=y ++S:CONFIG_TARGET_ZYNQ_MICROZED=y +CONFIG_OF_CONTROL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig new file mode 100644 index 0000000000..cceb32199d --- /dev/null +++ b/configs/zynq_zc70x_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ZYNQ=y ++S:CONFIG_TARGET_ZYNQ_ZC70X=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig new file mode 100644 index 0000000000..2935c0dff7 --- /dev/null +++ b/configs/zynq_zc770_xm010_defconfig @@ -0,0 +1,11 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" ++S:CONFIG_ARM=y ++S:CONFIG_ZYNQ=y ++S:CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig new file mode 100644 index 0000000000..0401739652 --- /dev/null +++ b/configs/zynq_zc770_xm012_defconfig @@ -0,0 +1,11 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" ++S:CONFIG_ARM=y ++S:CONFIG_ZYNQ=y ++S:CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig new file mode 100644 index 0000000000..a95970a917 --- /dev/null +++ b/configs/zynq_zc770_xm013_defconfig @@ -0,0 +1,11 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" ++S:CONFIG_ARM=y ++S:CONFIG_ZYNQ=y ++S:CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig new file mode 100644 index 0000000000..0fbc41ab8a --- /dev/null +++ b/configs/zynq_zed_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ZYNQ=y ++S:CONFIG_TARGET_ZYNQ_ZED=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig new file mode 100644 index 0000000000..4e66760750 --- /dev/null +++ b/configs/zynq_zybo_defconfig @@ -0,0 +1,10 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ZYNQ=y ++S:CONFIG_TARGET_ZYNQ_ZYBO=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_DM=y diff --git a/disk/Kconfig b/disk/Kconfig new file mode 100644 index 0000000000..95fb843f89 --- /dev/null +++ b/disk/Kconfig @@ -0,0 +1,10 @@ +config PARTITIONS + bool + +config DOS_PARTITION + bool "Support DOS partitions" + select PARTITIONS + +config MAC_PARTITION + bool "Support MAC partitions" + select PARTITIONS diff --git a/disk/Makefile b/disk/Makefile index 2b04e03dec..6970cecc71 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -5,33 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -#CFLAGS += -DET_DEBUG -DDEBUG - -LIB = $(obj)libdisk.o - -COBJS-$(CONFIG_PARTITIONS) += part.o -COBJS-$(CONFIG_MAC_PARTITION) += part_mac.o -COBJS-$(CONFIG_DOS_PARTITION) += part_dos.o -COBJS-$(CONFIG_ISO_PARTITION) += part_iso.o -COBJS-$(CONFIG_AMIGA_PARTITION) += part_amiga.o -COBJS-$(CONFIG_EFI_PARTITION) += part_efi.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +#ccflags-y += -DET_DEBUG -DDEBUG + +obj-$(CONFIG_PARTITIONS) += part.o +obj-$(CONFIG_MAC_PARTITION) += part_mac.o +obj-$(CONFIG_DOS_PARTITION) += part_dos.o +obj-$(CONFIG_ISO_PARTITION) += part_iso.o +obj-$(CONFIG_AMIGA_PARTITION) += part_amiga.o +obj-$(CONFIG_EFI_PARTITION) += part_efi.o diff --git a/disk/part.c b/disk/part.c index 6827744df3..18fcc7b156 100644 --- a/disk/part.c +++ b/disk/part.c @@ -22,6 +22,7 @@ struct block_drvr { char *name; block_dev_desc_t* (*get_dev)(int dev); + int (*select_hwpart)(int dev_num, int hwpart); }; static const struct block_drvr block_drvr[] = { @@ -41,10 +42,17 @@ static const struct block_drvr block_drvr[] = { { .name = "usb", .get_dev = usb_stor_get_dev, }, #endif #if defined(CONFIG_MMC) - { .name = "mmc", .get_dev = mmc_get_dev, }, + { + .name = "mmc", + .get_dev = mmc_get_dev, + .select_hwpart = mmc_select_hwpart, + }, #endif #if defined(CONFIG_SYSTEMACE) { .name = "ace", .get_dev = systemace_get_dev, }, +#endif +#if defined(CONFIG_SANDBOX) + { .name = "host", .get_dev = host_get_dev, }, #endif { }, }; @@ -52,11 +60,13 @@ static const struct block_drvr block_drvr[] = { DECLARE_GLOBAL_DATA_PTR; #ifdef HAVE_BLOCK_DEVICE -block_dev_desc_t *get_dev(const char *ifname, int dev) +static block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart) { const struct block_drvr *drvr = block_drvr; block_dev_desc_t* (*reloc_get_dev)(int dev); + int (*select_hwpart)(int dev_num, int hwpart); char *name; + int ret; if (!ifname) return NULL; @@ -68,17 +78,41 @@ block_dev_desc_t *get_dev(const char *ifname, int dev) while (drvr->name) { name = drvr->name; reloc_get_dev = drvr->get_dev; + select_hwpart = drvr->select_hwpart; #ifdef CONFIG_NEEDS_MANUAL_RELOC name += gd->reloc_off; reloc_get_dev += gd->reloc_off; -#endif - if (strncmp(ifname, name, strlen(name)) == 0) - return reloc_get_dev(dev); + if (select_hwpart) + select_hwpart += gd->reloc_off; +#endif + if (strncmp(ifname, name, strlen(name)) == 0) { + block_dev_desc_t *dev_desc = reloc_get_dev(dev); + if (!dev_desc) + return NULL; + if (hwpart == 0 && !select_hwpart) + return dev_desc; + if (!select_hwpart) + return NULL; + ret = select_hwpart(dev_desc->dev, hwpart); + if (ret < 0) + return NULL; + return dev_desc; + } drvr++; } return NULL; } + +block_dev_desc_t *get_dev(const char *ifname, int dev) +{ + return get_dev_hwpart(ifname, dev, 0); +} #else +block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart) +{ + return NULL; +} + block_dev_desc_t *get_dev(const char *ifname, int dev) { return NULL; @@ -102,7 +136,7 @@ typedef lbaint_t lba512_t; * Overflowless variant of (block_count * mul_by / div_by) * when div_by > mul_by */ -static lba512_t lba512_muldiv (lba512_t block_count, lba512_t mul_by, lba512_t div_by) +static lba512_t lba512_muldiv(lba512_t block_count, lba512_t mul_by, lba512_t div_by) { lba512_t bc_quot, bc_rem; @@ -184,7 +218,8 @@ void dev_print (block_dev_desc_t *dev_desc) lba512 = (lba * (dev_desc->blksz/512)); /* round to 1 digit */ - mb = lba512_muldiv(lba512, 10, 2048); /* 2048 = (1024 * 1024) / 512 MB */ + /* 2048 = (1024 * 1024) / 512 MB */ + mb = lba512_muldiv(lba512, 10, 2048); mb_quot = mb / 10; mb_rem = mb - (10 * mb_quot); @@ -217,7 +252,7 @@ void dev_print (block_dev_desc_t *dev_desc) #ifdef HAVE_BLOCK_DEVICE -void init_part (block_dev_desc_t * dev_desc) +void init_part(block_dev_desc_t *dev_desc) { #ifdef CONFIG_ISO_PARTITION if (test_part_iso(dev_desc) == 0) { @@ -264,7 +299,7 @@ void init_part (block_dev_desc_t * dev_desc) defined(CONFIG_AMIGA_PARTITION) || \ defined(CONFIG_EFI_PARTITION) -static void print_part_header (const char *type, block_dev_desc_t * dev_desc) +static void print_part_header(const char *type, block_dev_desc_t *dev_desc) { puts ("\nPartition Map for "); switch (dev_desc->if_type) { @@ -289,6 +324,9 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc) case IF_TYPE_MMC: puts ("MMC"); break; + case IF_TYPE_HOST: + puts("HOST"); + break; default: puts ("UNKNOWN"); break; @@ -299,7 +337,7 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc) #endif /* any CONFIG_..._PARTITION */ -void print_part (block_dev_desc_t * dev_desc) +void print_part(block_dev_desc_t * dev_desc) { switch (dev_desc->part_type) { @@ -347,8 +385,8 @@ void print_part (block_dev_desc_t * dev_desc) #endif /* HAVE_BLOCK_DEVICE */ -int get_partition_info(block_dev_desc_t *dev_desc, int part - , disk_partition_t *info) +int get_partition_info(block_dev_desc_t *dev_desc, int part, + disk_partition_t *info) { #ifdef HAVE_BLOCK_DEVICE @@ -410,25 +448,52 @@ int get_partition_info(block_dev_desc_t *dev_desc, int part return -1; } -int get_device(const char *ifname, const char *dev_str, +int get_device(const char *ifname, const char *dev_hwpart_str, block_dev_desc_t **dev_desc) { char *ep; - int dev; + char *dup_str = NULL; + const char *dev_str, *hwpart_str; + int dev, hwpart; + + hwpart_str = strchr(dev_hwpart_str, '.'); + if (hwpart_str) { + dup_str = strdup(dev_hwpart_str); + dup_str[hwpart_str - dev_hwpart_str] = 0; + dev_str = dup_str; + hwpart_str++; + } else { + dev_str = dev_hwpart_str; + hwpart = 0; + } dev = simple_strtoul(dev_str, &ep, 16); if (*ep) { printf("** Bad device specification %s %s **\n", ifname, dev_str); - return -1; + dev = -1; + goto cleanup; + } + + if (hwpart_str) { + hwpart = simple_strtoul(hwpart_str, &ep, 16); + if (*ep) { + printf("** Bad HW partition specification %s %s **\n", + ifname, hwpart_str); + dev = -1; + goto cleanup; + } } - *dev_desc = get_dev(ifname, dev); + *dev_desc = get_dev_hwpart(ifname, dev, hwpart); if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) { - printf("** Bad device %s %s **\n", ifname, dev_str); - return -1; + printf("** Bad device %s %s **\n", ifname, dev_hwpart_str); + dev = -1; + goto cleanup; } +cleanup: + free(dup_str); return dev; } @@ -450,12 +515,14 @@ int get_device_and_partition(const char *ifname, const char *dev_part_str, disk_partition_t tmpinfo; /* - * For now, we have a special case for sandbox, since there is no - * real block device support. + * Special-case a pseudo block device "hostfs", to allow access to the + * host's own filesystem. */ - if (0 == strcmp(ifname, "host")) { + if (0 == strcmp(ifname, "hostfs")) { *dev_desc = NULL; - info->start = info->size = info->blksz = 0; + info->start = 0; + info->size = 0; + info->blksz = 0; info->bootable = 0; strcpy((char *)info->type, BOOT_PART_TYPE); strcpy((char *)info->name, "Sandbox host"); diff --git a/disk/part_amiga.h b/disk/part_amiga.h index 524da10fd0..0f04e97e2c 100644 --- a/disk/part_amiga.h +++ b/disk/part_amiga.h @@ -3,7 +3,7 @@ * Hans-Joerg Frieden, Hyperion Entertainment * Hans-JoergF@hyperion-entertainment.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _DISK_PART_AMIGA_H diff --git a/disk/part_dos.c b/disk/part_dos.c index 05c3933c32..cf1a36ebb8 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -21,6 +21,8 @@ #ifdef HAVE_BLOCK_DEVICE +#define DOS_PART_DEFAULT_SECTOR 512 + /* Convert char[4] in little endian format to the host format integer */ static inline int le32_to_int(unsigned char *le32) @@ -168,6 +170,7 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); dos_partition_t *pt; int i; + int dos_type; if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) { printf ("** Can't read partition table on %d:%d **\n", @@ -198,9 +201,10 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part (pt->sys_ind != 0) && (part_num == which_part) && (is_extended(pt->sys_ind) == 0)) { - info->blksz = 512; - info->start = ext_part_sector + le32_to_int (pt->start4); - info->size = le32_to_int (pt->size4); + info->blksz = DOS_PART_DEFAULT_SECTOR; + info->start = (lbaint_t)(ext_part_sector + + le32_to_int(pt->start4)); + info->size = (lbaint_t)le32_to_int(pt->size4); switch(dev_desc->if_type) { case IF_TYPE_IDE: case IF_TYPE_SATA: @@ -252,6 +256,22 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part part_num, which_part, info, disksig); } } + + /* Check for DOS PBR if no partition is found */ + dos_type = test_block_type(buffer); + + if (dos_type == DOS_PBR) { + info->start = 0; + info->size = dev_desc->lba; + info->blksz = DOS_PART_DEFAULT_SECTOR; + info->bootable = 0; + sprintf ((char *)info->type, "U-Boot"); +#ifdef CONFIG_PARTITION_UUIDS + info->uuid[0] = 0; +#endif + return 0; + } + return -1; } diff --git a/disk/part_dos.h b/disk/part_dos.h index e0608e0925..0321d922b7 100644 --- a/disk/part_dos.h +++ b/disk/part_dos.h @@ -2,7 +2,7 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _DISK_PART_DOS_H diff --git a/disk/part_efi.c b/disk/part_efi.c index 09c2e1b671..5856f93211 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -6,18 +6,15 @@ */ /* - * Problems with CONFIG_SYS_64BIT_LBA: - * - * struct disk_partition.start in include/part.h is sized as ulong. - * When CONFIG_SYS_64BIT_LBA is activated, lbaint_t changes from ulong to uint64_t. - * For now, it is cast back to ulong at assignment. - * - * This limits the maximum size of addressable storage to < 2 Terra Bytes + * NOTE: + * when CONFIG_SYS_64BIT_LBA is not defined, lbaint_t is 32 bits; this + * limits the maximum size of addressable storage to < 2 Terra Bytes */ #include #include #include #include +#include #include #include #include @@ -43,8 +40,8 @@ static inline u32 efi_crc32(const void *buf, u32 len) static int pmbr_part_valid(struct partition *part); static int is_pmbr_valid(legacy_mbr * mbr); -static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba, - gpt_header * pgpt_head, gpt_entry ** pgpt_pte); +static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba, + gpt_header *pgpt_head, gpt_entry **pgpt_pte); static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, gpt_header * pgpt_head); static int is_pte_valid(gpt_entry * pte); @@ -63,26 +60,6 @@ static char *print_efiname(gpt_entry *pte) return name; } -static void uuid_string(unsigned char *uuid, char *str) -{ - static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, - 12, 13, 14, 15}; - int i; - - for (i = 0; i < 16; i++) { - sprintf(str, "%02x", uuid[le[i]]); - str += 2; - switch (i) { - case 3: - case 5: - case 7: - case 9: - *str++ = '-'; - break; - } - } -} - static efi_guid_t system_guid = PARTITION_SYSTEM_GUID; static inline int is_bootable(gpt_entry *p) @@ -92,6 +69,107 @@ static inline int is_bootable(gpt_entry *p) sizeof(efi_guid_t)); } +static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba, + lbaint_t lastlba) +{ + uint32_t crc32_backup = 0; + uint32_t calc_crc32; + + /* Check the GPT header signature */ + if (le64_to_cpu(gpt_h->signature) != GPT_HEADER_SIGNATURE) { + printf("%s signature is wrong: 0x%llX != 0x%llX\n", + "GUID Partition Table Header", + le64_to_cpu(gpt_h->signature), + GPT_HEADER_SIGNATURE); + return -1; + } + + /* Check the GUID Partition Table CRC */ + memcpy(&crc32_backup, &gpt_h->header_crc32, sizeof(crc32_backup)); + memset(&gpt_h->header_crc32, 0, sizeof(gpt_h->header_crc32)); + + calc_crc32 = efi_crc32((const unsigned char *)gpt_h, + le32_to_cpu(gpt_h->header_size)); + + memcpy(&gpt_h->header_crc32, &crc32_backup, sizeof(crc32_backup)); + + if (calc_crc32 != le32_to_cpu(crc32_backup)) { + printf("%s CRC is wrong: 0x%x != 0x%x\n", + "GUID Partition Table Header", + le32_to_cpu(crc32_backup), calc_crc32); + return -1; + } + + /* + * Check that the my_lba entry points to the LBA that contains the GPT + */ + if (le64_to_cpu(gpt_h->my_lba) != lba) { + printf("GPT: my_lba incorrect: %llX != " LBAF "\n", + le64_to_cpu(gpt_h->my_lba), + lba); + return -1; + } + + /* + * Check that the first_usable_lba and that the last_usable_lba are + * within the disk. + */ + if (le64_to_cpu(gpt_h->first_usable_lba) > lastlba) { + printf("GPT: first_usable_lba incorrect: %llX > " LBAF "\n", + le64_to_cpu(gpt_h->first_usable_lba), lastlba); + return -1; + } + if (le64_to_cpu(gpt_h->last_usable_lba) > lastlba) { + printf("GPT: last_usable_lba incorrect: %llX > " LBAF "\n", + le64_to_cpu(gpt_h->last_usable_lba), lastlba); + return -1; + } + + debug("GPT: first_usable_lba: %llX last_usable_lba: %llX last lba: " + LBAF "\n", le64_to_cpu(gpt_h->first_usable_lba), + le64_to_cpu(gpt_h->last_usable_lba), lastlba); + + return 0; +} + +static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e) +{ + uint32_t calc_crc32; + + /* Check the GUID Partition Table Entry Array CRC */ + calc_crc32 = efi_crc32((const unsigned char *)gpt_e, + le32_to_cpu(gpt_h->num_partition_entries) * + le32_to_cpu(gpt_h->sizeof_partition_entry)); + + if (calc_crc32 != le32_to_cpu(gpt_h->partition_entry_array_crc32)) { + printf("%s: 0x%x != 0x%x\n", + "GUID Partition Table Entry Array CRC is wrong", + le32_to_cpu(gpt_h->partition_entry_array_crc32), + calc_crc32); + return -1; + } + + return 0; +} + +static void prepare_backup_gpt_header(gpt_header *gpt_h) +{ + uint32_t calc_crc32; + uint64_t val; + + /* recalculate the values for the Backup GPT Header */ + val = le64_to_cpu(gpt_h->my_lba); + gpt_h->my_lba = gpt_h->alternate_lba; + gpt_h->alternate_lba = cpu_to_le64(val); + gpt_h->partition_entry_lba = + cpu_to_le64(le64_to_cpu(gpt_h->last_usable_lba) + 1); + gpt_h->header_crc32 = 0; + + calc_crc32 = efi_crc32((const unsigned char *)gpt_h, + le32_to_cpu(gpt_h->header_size)); + gpt_h->header_crc32 = cpu_to_le32(calc_crc32); +} + #ifdef CONFIG_EFI_PARTITION /* * Public Functions (include/part.h) @@ -103,6 +181,7 @@ void print_part_efi(block_dev_desc_t * dev_desc) gpt_entry *gpt_pte = NULL; int i = 0; char uuid[37]; + unsigned char *uuid_bin; if (!dev_desc) { printf("%s: Invalid Argument(s)\n", __func__); @@ -112,15 +191,23 @@ void print_part_efi(block_dev_desc_t * dev_desc) if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head, &gpt_pte) != 1) { printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - return; + if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), + gpt_head, &gpt_pte) != 1) { + printf("%s: *** ERROR: Invalid Backup GPT ***\n", + __func__); + return; + } else { + printf("%s: *** Using Backup GPT ***\n", + __func__); + } } debug("%s: gpt-entry at %p\n", __func__, gpt_pte); printf("Part\tStart LBA\tEnd LBA\t\tName\n"); printf("\tAttributes\n"); - printf("\tType UUID\n"); - printf("\tPartition UUID\n"); + printf("\tType GUID\n"); + printf("\tPartition GUID\n"); for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) { /* Stop at the first non valid PTE */ @@ -132,10 +219,12 @@ void print_part_efi(block_dev_desc_t * dev_desc) le64_to_cpu(gpt_pte[i].ending_lba), print_efiname(&gpt_pte[i])); printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw); - uuid_string(gpt_pte[i].partition_type_guid.b, uuid); + uuid_bin = (unsigned char *)gpt_pte[i].partition_type_guid.b; + uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); printf("\ttype:\t%s\n", uuid); - uuid_string(gpt_pte[i].unique_partition_guid.b, uuid); - printf("\tuuid:\t%s\n", uuid); + uuid_bin = (unsigned char *)gpt_pte[i].unique_partition_guid.b; + uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); + printf("\tguid:\t%s\n", uuid); } /* Remember to free pte */ @@ -159,20 +248,29 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head, &gpt_pte) != 1) { printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - return -1; + if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), + gpt_head, &gpt_pte) != 1) { + printf("%s: *** ERROR: Invalid Backup GPT ***\n", + __func__); + return -1; + } else { + printf("%s: *** Using Backup GPT ***\n", + __func__); + } } if (part > le32_to_cpu(gpt_head->num_partition_entries) || !is_pte_valid(&gpt_pte[part - 1])) { - printf("%s: *** ERROR: Invalid partition number %d ***\n", + debug("%s: *** ERROR: Invalid partition number %d ***\n", __func__, part); + free(gpt_pte); return -1; } - /* The ulong casting limits the maximum disk size to 2 TB */ - info->start = (u64)le64_to_cpu(gpt_pte[part - 1].starting_lba); + /* The 'lbaint_t' casting may limit the maximum disk size to 2 TB */ + info->start = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].starting_lba); /* The ending LBA is inclusive, to calculate size, add 1 to it */ - info->size = ((u64)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1) + info->size = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1 - info->start; info->blksz = dev_desc->blksz; @@ -181,10 +279,11 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, sprintf((char *)info->type, "U-Boot"); info->bootable = is_bootable(&gpt_pte[part - 1]); #ifdef CONFIG_PARTITION_UUIDS - uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid); + uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid, + UUID_STR_FORMAT_GUID); #endif - debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__, + debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__, info->start, info->size, info->name); /* Remember to free pte */ @@ -192,6 +291,25 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, return 0; } +int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc, + const char *name, disk_partition_t *info) +{ + int ret; + int i; + for (i = 1; i < GPT_ENTRY_NUMBERS; i++) { + ret = get_partition_info_efi(dev_desc, i, info); + if (ret != 0) { + /* no more entries in table */ + return -1; + } + if (strcmp(name, (const char *)info->name) == 0) { + /* matched */ + return 0; + } + } + return -2; +} + int test_part_efi(block_dev_desc_t * dev_desc) { ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz); @@ -212,10 +330,10 @@ int test_part_efi(block_dev_desc_t * dev_desc) */ static int set_protective_mbr(block_dev_desc_t *dev_desc) { - legacy_mbr *p_mbr; - /* Setup the Protective MBR */ - p_mbr = calloc(1, sizeof(p_mbr)); + ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, p_mbr, 1); + memset(p_mbr, 0, sizeof(*p_mbr)); + if (p_mbr == NULL) { printf("%s: calloc failed!\n", __func__); return -1; @@ -224,71 +342,15 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc) p_mbr->signature = MSDOS_MBR_SIGNATURE; p_mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT; p_mbr->partition_record[0].start_sect = 1; - p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba; + p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1; /* Write MBR sector to the MMC device */ if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) { printf("** Can't write to device %d **\n", dev_desc->dev); - free(p_mbr); - return -1; - } - - free(p_mbr); - return 0; -} - -/** - * string_uuid(); Convert UUID stored as string to bytes - * - * @param uuid - UUID represented as string - * @param dst - GUID buffer - * - * @return return 0 on successful conversion - */ -static int string_uuid(char *uuid, u8 *dst) -{ - efi_guid_t guid; - u16 b, c, d; - u64 e; - u32 a; - u8 *p; - u8 i; - - const u8 uuid_str_len = 36; - - /* The UUID is written in text: */ - /* 1 9 14 19 24 */ - /* xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx */ - - debug("%s: uuid: %s\n", __func__, uuid); - - if (strlen(uuid) != uuid_str_len) return -1; - - for (i = 0; i < uuid_str_len; i++) { - if ((i == 8) || (i == 13) || (i == 18) || (i == 23)) { - if (uuid[i] != '-') - return -1; - } else { - if (!isxdigit(uuid[i])) - return -1; - } } - a = (u32)simple_strtoul(uuid, NULL, 16); - b = (u16)simple_strtoul(uuid + 9, NULL, 16); - c = (u16)simple_strtoul(uuid + 14, NULL, 16); - d = (u16)simple_strtoul(uuid + 19, NULL, 16); - e = (u64)simple_strtoull(uuid + 24, NULL, 16); - - p = (u8 *) &e; - guid = EFI_GUID(a, b, c, d >> 8, d & 0xFF, - *(p + 5), *(p + 4), *(p + 3), - *(p + 2), *(p + 1) , *p); - - memcpy(dst, guid.b, sizeof(efi_guid_t)); - return 0; } @@ -298,7 +360,6 @@ int write_gpt_table(block_dev_desc_t *dev_desc, const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries * sizeof(gpt_entry)), dev_desc); u32 calc_crc32; - u64 val; debug("max lba: %x\n", (u32) dev_desc->lba); /* Setup the Protective MBR */ @@ -323,23 +384,17 @@ int write_gpt_table(block_dev_desc_t *dev_desc, != pte_blk_cnt) goto err; - /* recalculate the values for the Second GPT Header */ - val = le64_to_cpu(gpt_h->my_lba); - gpt_h->my_lba = gpt_h->alternate_lba; - gpt_h->alternate_lba = cpu_to_le64(val); - gpt_h->header_crc32 = 0; - - calc_crc32 = efi_crc32((const unsigned char *)gpt_h, - le32_to_cpu(gpt_h->header_size)); - gpt_h->header_crc32 = cpu_to_le32(calc_crc32); + prepare_backup_gpt_header(gpt_h); if (dev_desc->block_write(dev_desc->dev, - le32_to_cpu(gpt_h->last_usable_lba + 1), + (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba) + + 1, pte_blk_cnt, gpt_e) != pte_blk_cnt) goto err; if (dev_desc->block_write(dev_desc->dev, - le32_to_cpu(gpt_h->my_lba), 1, gpt_h) != 1) + (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1, + gpt_h) != 1) goto err; debug("GPT successfully written to block device!\n"); @@ -353,12 +408,15 @@ int write_gpt_table(block_dev_desc_t *dev_desc, int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, disk_partition_t *partitions, int parts) { - u32 offset = (u32)le32_to_cpu(gpt_h->first_usable_lba); - ulong start; + lbaint_t offset = (lbaint_t)le64_to_cpu(gpt_h->first_usable_lba); + lbaint_t start; + lbaint_t last_usable_lba = (lbaint_t) + le64_to_cpu(gpt_h->last_usable_lba); int i, k; size_t efiname_len, dosname_len; #ifdef CONFIG_PARTITION_UUIDS char *str_uuid; + unsigned char *bin_uuid; #endif for (i = 0; i < parts; i++) { @@ -375,8 +433,8 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, gpt_e[i].starting_lba = cpu_to_le64(offset); offset += partitions[i].size; } - if (offset >= gpt_h->last_usable_lba) { - printf("Partitions layout exceeds disk size\n"); + if (offset >= last_usable_lba) { + printf("Partitions layout exceds disk size\n"); return -1; } /* partition ending lba */ @@ -392,7 +450,9 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, #ifdef CONFIG_PARTITION_UUIDS str_uuid = partitions[i].uuid; - if (string_uuid(str_uuid, gpt_e[i].unique_partition_guid.b)) { + bin_uuid = gpt_e[i].unique_partition_guid.b; + + if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_STD)) { printf("Partition no. %d: invalid guid: %s\n", i, str_uuid); return -1; @@ -415,7 +475,8 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, gpt_e[i].partition_name[k] = (efi_char16_t)(partitions[i].name[k]); - debug("%s: name: %s offset[%d]: 0x%x size[%d]: 0x" LBAF "\n", + debug("%s: name: %s offset[%d]: 0x" LBAF + " size[%d]: 0x" LBAF "\n", __func__, partitions[i].name, i, offset, i, partitions[i].size); } @@ -439,7 +500,7 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h, gpt_h->header_crc32 = 0; gpt_h->partition_entry_array_crc32 = 0; - if (string_uuid(str_guid, gpt_h->disk_guid.b)) + if (uuid_str_to_bin(str_guid, gpt_h->disk_guid.b, UUID_STR_FORMAT_GUID)) return -1; return 0; @@ -486,6 +547,97 @@ err: free(gpt_h); return ret; } + +int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf) +{ + gpt_header *gpt_h; + gpt_entry *gpt_e; + + /* determine start of GPT Header in the buffer */ + gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA * + dev_desc->blksz); + if (validate_gpt_header(gpt_h, GPT_PRIMARY_PARTITION_TABLE_LBA, + dev_desc->lba)) + return -1; + + /* determine start of GPT Entries in the buffer */ + gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) * + dev_desc->blksz); + if (validate_gpt_entries(gpt_h, gpt_e)) + return -1; + + return 0; +} + +int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf) +{ + gpt_header *gpt_h; + gpt_entry *gpt_e; + int gpt_e_blk_cnt; + lbaint_t lba; + int cnt; + + if (is_valid_gpt_buf(dev_desc, buf)) + return -1; + + /* determine start of GPT Header in the buffer */ + gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA * + dev_desc->blksz); + + /* determine start of GPT Entries in the buffer */ + gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) * + dev_desc->blksz); + gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) * + le32_to_cpu(gpt_h->sizeof_partition_entry)), + dev_desc); + + /* write MBR */ + lba = 0; /* MBR is always at 0 */ + cnt = 1; /* MBR (1 block) */ + if (dev_desc->block_write(dev_desc->dev, lba, cnt, buf) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "MBR", cnt, lba); + return 1; + } + + /* write Primary GPT */ + lba = GPT_PRIMARY_PARTITION_TABLE_LBA; + cnt = 1; /* GPT Header (1 block) */ + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Primary GPT Header", cnt, lba); + return 1; + } + + lba = le64_to_cpu(gpt_h->partition_entry_lba); + cnt = gpt_e_blk_cnt; + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Primary GPT Entries", cnt, lba); + return 1; + } + + prepare_backup_gpt_header(gpt_h); + + /* write Backup GPT */ + lba = le64_to_cpu(gpt_h->partition_entry_lba); + cnt = gpt_e_blk_cnt; + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Backup GPT Entries", cnt, lba); + return 1; + } + + lba = le64_to_cpu(gpt_h->my_lba); + cnt = 1; /* GPT Header (1 block) */ + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Backup GPT Header", cnt, lba); + return 1; + } + + return 0; +} #endif /* @@ -539,73 +691,23 @@ static int is_pmbr_valid(legacy_mbr * mbr) * Description: returns 1 if valid, 0 on error. * If valid, returns pointers to PTEs. */ -static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba, - gpt_header * pgpt_head, gpt_entry ** pgpt_pte) +static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba, + gpt_header *pgpt_head, gpt_entry **pgpt_pte) { - u32 crc32_backup = 0; - u32 calc_crc32; - unsigned long long lastlba; - if (!dev_desc || !pgpt_head) { printf("%s: Invalid Argument(s)\n", __func__); return 0; } /* Read GPT Header from device */ - if (dev_desc->block_read(dev_desc->dev, lba, 1, pgpt_head) != 1) { + if (dev_desc->block_read(dev_desc->dev, (lbaint_t)lba, 1, pgpt_head) + != 1) { printf("*** ERROR: Can't read GPT header ***\n"); return 0; } - /* Check the GPT header signature */ - if (le64_to_cpu(pgpt_head->signature) != GPT_HEADER_SIGNATURE) { - printf("GUID Partition Table Header signature is wrong:" - "0x%llX != 0x%llX\n", - le64_to_cpu(pgpt_head->signature), - GPT_HEADER_SIGNATURE); - return 0; - } - - /* Check the GUID Partition Table CRC */ - memcpy(&crc32_backup, &pgpt_head->header_crc32, sizeof(crc32_backup)); - memset(&pgpt_head->header_crc32, 0, sizeof(pgpt_head->header_crc32)); - - calc_crc32 = efi_crc32((const unsigned char *)pgpt_head, - le32_to_cpu(pgpt_head->header_size)); - - memcpy(&pgpt_head->header_crc32, &crc32_backup, sizeof(crc32_backup)); - - if (calc_crc32 != le32_to_cpu(crc32_backup)) { - printf("GUID Partition Table Header CRC is wrong:" - "0x%x != 0x%x\n", - le32_to_cpu(crc32_backup), calc_crc32); + if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba)) return 0; - } - - /* Check that the my_lba entry points to the LBA that contains the GPT */ - if (le64_to_cpu(pgpt_head->my_lba) != lba) { - printf("GPT: my_lba incorrect: %llX != %llX\n", - le64_to_cpu(pgpt_head->my_lba), - lba); - return 0; - } - - /* Check the first_usable_lba and last_usable_lba are within the disk. */ - lastlba = (unsigned long long)dev_desc->lba; - if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) { - printf("GPT: first_usable_lba incorrect: %llX > %llX\n", - le64_to_cpu(pgpt_head->first_usable_lba), lastlba); - return 0; - } - if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) { - printf("GPT: last_usable_lba incorrect: %llX > %llX\n", - (u64) le64_to_cpu(pgpt_head->last_usable_lba), lastlba); - return 0; - } - - debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %llX\n", - le64_to_cpu(pgpt_head->first_usable_lba), - le64_to_cpu(pgpt_head->last_usable_lba), lastlba); /* Read and allocate Partition Table Entries */ *pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head); @@ -614,17 +716,7 @@ static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba, return 0; } - /* Check the GUID Partition Table Entry Array CRC */ - calc_crc32 = efi_crc32((const unsigned char *)*pgpt_pte, - le32_to_cpu(pgpt_head->num_partition_entries) * - le32_to_cpu(pgpt_head->sizeof_partition_entry)); - - if (calc_crc32 != le32_to_cpu(pgpt_head->partition_entry_array_crc32)) { - printf("GUID Partition Table Entry Array CRC is wrong:" - "0x%x != 0x%x\n", - le32_to_cpu(pgpt_head->partition_entry_array_crc32), - calc_crc32); - + if (validate_gpt_entries(pgpt_head, *pgpt_pte)) { free(*pgpt_pte); return 0; } @@ -676,7 +768,7 @@ static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, /* Read GPT Entries from device */ blk_cnt = BLOCK_CNT(count, dev_desc); if (dev_desc->block_read (dev_desc->dev, - le64_to_cpu(pgpt_head->partition_entry_lba), + (lbaint_t)le64_to_cpu(pgpt_head->partition_entry_lba), (lbaint_t) (blk_cnt), pte) != blk_cnt) { diff --git a/disk/part_iso.c b/disk/part_iso.c index 80c1d95d59..2547c703db 100644 --- a/disk/part_iso.c +++ b/disk/part_iso.c @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/disk/part_iso.h b/disk/part_iso.h index e5a3e0220f..dace0f87dc 100644 --- a/disk/part_iso.h +++ b/disk/part_iso.h @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PART_CD_H #define _PART_CD_H diff --git a/doc/DocBook/.gitignore b/doc/DocBook/.gitignore index 90c1b112a1..7ebd5465d9 100644 --- a/doc/DocBook/.gitignore +++ b/doc/DocBook/.gitignore @@ -1,4 +1,3 @@ -*/ *.xml *.ps *.pdf @@ -11,5 +10,6 @@ *.out *.png *.gif +*.svg media-indices.tmpl media-entities.tmpl diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile index 521e8bc0e9..593237f04a 100644 --- a/doc/DocBook/Makefile +++ b/doc/DocBook/Makefile @@ -1,14 +1,12 @@ ### # This makefile is used to generate the kernel documentation, # primarily based on in-line comments in various source files. -# See doc/kernel-doc-nano-HOWTO.txt for instruction in how +# See Documentation/kernel-doc-nano-HOWTO.txt for instruction in how # to document the SRC - and how to read it. # To add a new book the only step required is to add the book to the # list of DOCBOOKS. -include $(TOPDIR)/config.mk - -DOCBOOKS := fs.xml linker_lists.xml stdio.xml +DOCBOOKS := linker_lists.xml stdio.xml ### # The build process is as follows (targets): @@ -26,9 +24,10 @@ PS_METHOD = $(prefer-db2x) ### # The targets that may be used. -PHONY += $(obj).depend xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs +PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs -BOOKS := $(addprefix $(OBJTREE)/doc/DocBook/,$(DOCBOOKS)) +targets += $(DOCBOOKS) +BOOKS := $(addprefix $(obj)/,$(DOCBOOKS)) xmldocs: $(BOOKS) sgmldocs: xmldocs @@ -46,17 +45,18 @@ htmldocs: $(HTML) MAN := $(patsubst %.xml, %.9, $(BOOKS)) mandocs: $(MAN) + $(if $(wildcard $(obj)/man/*.9),gzip -f $(obj)/man/*.9) installmandocs: mandocs mkdir -p /usr/local/man/man9/ - install doc/DocBook/man/*.9.gz /usr/local/man/man9/ + install $(obj)/man/*.9.gz /usr/local/man/man9/ ### #External programs used -KERNELDOC = $(SRCTREE)/tools/kernel-doc/kernel-doc -DOCPROC = $(OBJTREE)/tools/kernel-doc/docproc +KERNELDOC = $(srctree)/scripts/kernel-doc +DOCPROC = $(objtree)/scripts/docproc -XMLTOFLAGS = -m $(SRCTREE)/doc/DocBook/stylesheet.xsl +XMLTOFLAGS = -m $(srctree)/$(src)/stylesheet.xsl XMLTOFLAGS += --skip-validation ### @@ -66,27 +66,23 @@ XMLTOFLAGS += --skip-validation # appropriate parameters. # The following rules are used to generate the .xml documentation # required to generate the final targets. (ps, pdf, html). -%.xml: %.tmpl - $(DOCPROC) doc $< >$@ - -ifeq ($@, "cleandocs") -sinclude $(obj).depend -$(obj).depend: $(patsubst %.xml, %.tmpl, $(DOCBOOKS)) - rm -f $(obj).depend ; \ - touch $(obj).depend ; \ - for file in $^ ; do \ - xmlfile=`echo "$${file}" | \ - sed "s/tmpl$$/xml/"` ; \ - echo -n "$${xmlfile}: ">> $(obj).depend ; \ - $(DOCPROC) depend $$file >> $(obj).depend ; \ - echo -e "\n\t$(DOCPROC) doc $< >$${xmlfile} " >> \ - $(obj).depend ; \ - done -endif - -### -# Changes in kernel-doc force a rebuild of all documentation -$(BOOKS): $(KERNELDOC) +quiet_cmd_docproc = DOCPROC $@ + cmd_docproc = SRCTREE=$(srctree)/ $(DOCPROC) doc $< >$@ +define rule_docproc + set -e; \ + $(if $($(quiet)cmd_$(1)),echo ' $($(quiet)cmd_$(1))';) \ + $(cmd_$(1)); \ + ( \ + echo 'cmd_$@ := $(cmd_$(1))'; \ + echo $@: `SRCTREE=$(srctree) $(DOCPROC) depend $<`; \ + ) > $(dir $@).$(notdir $@).cmd +endef + +%.xml: %.tmpl $(KERNELDOC) $(DOCPROC) FORCE + $(call if_changed_rule,docproc) + +# Tell kbuild to always build the programs +always := $(hostprogs-y) notfoundtemplate = echo "*** You have to install docbook-utils or xmlto ***"; \ exit 1 @@ -113,46 +109,43 @@ endif quiet_cmd_db2ps = PS $@ cmd_db2ps = $(subst TYPE,ps, $($(PS_METHOD)template)) %.ps : %.xml - $(call cmd_db2ps) + $(call cmd,db2ps) quiet_cmd_db2pdf = PDF $@ cmd_db2pdf = $(subst TYPE,pdf, $($(PDF_METHOD)template)) %.pdf : %.xml - $(call cmd_db2pdf) + $(call cmd,db2pdf) index = index.html -main_idx = $(index) +main_idx = $(obj)/$(index) build_main_index = rm -rf $(main_idx); \ echo '

U-Boot Bootloader HTML Documentation

' >> $(main_idx) && \ - echo '

U-Boot Version: $(U_BOOT_VERSION)

' >> $(main_idx) && \ + echo '

U-Boot Version: $(UBOOTVERSION)

' >> $(main_idx) && \ cat $(HTML) >> $(main_idx) -# To work around bug [1] in docbook-xsl-stylesheets 1.76.1 , generate only html -# docs instead of xhtml with xmlto. -# [1] http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=654338 quiet_cmd_db2html = HTML $@ cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \ echo ' \ - $(patsubst %.html,%,$(notdir $@))

' > $@ + $(patsubst %.html,%,$(notdir $@))

' > $@ %.html: %.xml @(which xmlto > /dev/null 2>&1) || \ (echo "*** You need to install xmlto ***"; \ exit 1) @rm -rf $@ $(patsubst %.html,%,$@) - $(call cmd_db2html) + $(call cmd,db2html) @if [ ! -z "$(PNG-$(basename $(notdir $@)))" ]; then \ cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi quiet_cmd_db2man = MAN $@ - cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi + cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; fi %.9 : %.xml @(which xmlto > /dev/null 2>&1) || \ (echo "*** You need to install xmlto ***"; \ exit 1) - $(Q)mkdir -p $(obj)man - $(call cmd_db2man) + $(Q)mkdir -p $(obj)/man + $(call cmd,db2man) @touch $@ ### @@ -164,7 +157,7 @@ quiet_cmd_fig2eps = FIG2EPS $@ @(which fig2dev > /dev/null 2>&1) || \ (echo "*** You need to install transfig ***"; \ exit 1) - $(call cmd_fig2eps) + $(call cmd,fig2eps) quiet_cmd_fig2png = FIG2PNG $@ cmd_fig2png = fig2dev -Lpng $< $@ @@ -173,7 +166,7 @@ quiet_cmd_fig2png = FIG2PNG $@ @(which fig2dev > /dev/null 2>&1) || \ (echo "*** You need to install transfig ***"; \ exit 1) - $(call cmd_fig2png) + $(call cmd,fig2png) ### # Rule to convert a .c file to inline XML documentation @@ -219,9 +212,8 @@ clean-files := $(DOCBOOKS) \ clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man cleandocs: - @rm -f $(obj).depend - @$(Q)rm -f $(call objectify, $(clean-files)) - @$(Q)rm -rf $(call objectify, $(clean-dirs)) + $(Q)rm -f $(call objectify, $(clean-files)) + $(Q)rm -rf $(call objectify, $(clean-dirs)) # Declare the contents of the .PHONY variable as phony. We keep that # information in a variable se we can use it in if_changed and friends. diff --git a/doc/DocBook/stylesheet.xsl b/doc/DocBook/stylesheet.xsl index 8adce568b6..85b2527519 100644 --- a/doc/DocBook/stylesheet.xsl +++ b/doc/DocBook/stylesheet.xsl @@ -7,5 +7,4 @@ 2 1 -../docbook.css diff --git a/doc/README.ARC b/doc/README.ARC new file mode 100644 index 0000000000..5f414fb2fa --- /dev/null +++ b/doc/README.ARC @@ -0,0 +1,27 @@ +Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs +that SoC designers can optimize for a wide range of uses, from deeply embedded +to high-performance host applications. + +More information on ARC cores avaialble here: +http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx + +Designers can differentiate their products by using patented configuration +technology to tailor each ARC processor instance to meet specific performance, +power and area requirements. + +The DesignWare ARC processors are also extendable, allowing designers to add +their own custom instructions that dramatically increase performance. + +Synopsys' ARC processors have been used by over 170 customers worldwide who +collectively ship more than 1 billion ARC-based chips annually. + +All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent +performance and code density for embedded and host SoC applications. + +The RISC microprocessors are synthesizable and can be implemented in any foundry +or process, and are supported by a complete suite of development tools. + +The ARC GNU toolchain with support for all ARC Processors can be downloaded +from here (available pre-built toolchains as well): + +https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases diff --git a/doc/README.ARM-SoC b/doc/README.ARM-SoC deleted file mode 100644 index d6bd624886..0000000000 --- a/doc/README.ARM-SoC +++ /dev/null @@ -1,31 +0,0 @@ -[By Steven Scholz , 16 Aug 2004] - -Since the cpu/ directory gets clobbered with peripheral driver code I -started cleaning up arch/arm/cpu/arm920t. - -I introduced the concept of Soc (system on a chip) into the ./cpu -directory. That means that code that is cpu (i.e. core) specific -resides in - - $(CPUDIR)/ - -and code that is specific to some SoC (i.e. vendor specific -peripherals around the core) is moved into - - $(CPUDIR)/$(SOC)/ - -Thus a library/archive "$(CPUDIR)/$(SOC)/lib$(SOC).a" will be build -and linked. Examples will be - - arch/arm/cpu/arm920t/imx/ - arch/arm/cpu/arm920t/s3c24x0 - -One can select an SoC by passing the name of it to ./mkconfig just -like - - @./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0 - -If there's no VENDOR field (like "mpl" in the above line) one has to -pass NULL instead: - - @./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx diff --git a/doc/README.JFFS2_NAND b/doc/README.JFFS2_NAND index 5018ae8342..09788d5348 100644 --- a/doc/README.JFFS2_NAND +++ b/doc/README.JFFS2_NAND @@ -1,6 +1,6 @@ JFFS2 NAND support: -To ebable, use the following #define in the board configuration file: +To enable, use the following #define in the board configuration file: #define CONFIG_JFFS2_NAND 1 diff --git a/doc/README.SPL b/doc/README.SPL index ac9a2137c8..3ba313caa8 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -13,34 +13,29 @@ can be reused. No code duplication or symlinking is necessary anymore. How it works ------------ -There is a new directory TOPDIR/spl which contains only a Makefile. -The object files are built separately for SPL and placed in this directory. +The object files for SPL are built separately and placed in the "spl" directory. The final binaries which are generated are u-boot-spl, u-boot-spl.bin and u-boot-spl.map. -During the SPL build a variable named CONFIG_SPL_BUILD is exported -in the make environment and also appended to CPPFLAGS with -DCONFIG_SPL_BUILD. +A config option named CONFIG_SPL_BUILD is enabled by Kconfig for SPL. Source files can therefore be compiled for SPL with different settings. -ARM-based boards have previously used the option CONFIG_PRELOADER for it. For example: ifeq ($(CONFIG_SPL_BUILD),y) -COBJS-y += board_spl.o +obj-y += board_spl.o else -COBJS-y += board.o +obj-y += board.o endif -COBJS-$(CONFIG_SPL_BUILD) += foo.o +obj-$(CONFIG_SPL_BUILD) += foo.o #ifdef CONFIG_SPL_BUILD foo(); #endif -The building of SPL images can be with: - -#define CONFIG_SPL +The building of SPL images can be enabled by CONFIG_SPL option in Kconfig. Because SPL images normally have a different text base, one has to be configured by defining CONFIG_SPL_TEXT_BASE. The linker script has to be @@ -59,26 +54,17 @@ CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o) CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o) CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o) CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o) +CONFIG_SPL_EXT_SUPPORT CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o) CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o) +CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc) CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o) CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o) CONFIG_SPL_RAM_DEVICE (common/spl/spl.c) - - -Normally CPU is assumed to be the same between the SPL and normal -u-boot build. However it is possible to specify a different CPU for -the SPL build for cases where the SPL is expected to run on a -different CPU model from the main u-boot. This is done by specifying -an SPL CPU in boards.cfg as follows: - - normal_cpu:spl_cpu - -This case CPU will be set to "normal_cpu" during the main u-boot -build and "spl_cpu" during the SPL build. +CONFIG_SPL_WATCHDOG_SUPPORT (drivers/watchdog/libwatchdog.o) Debugging diff --git a/doc/README.TPL b/doc/README.TPL new file mode 100644 index 0000000000..980debe777 --- /dev/null +++ b/doc/README.TPL @@ -0,0 +1,45 @@ +Generic TPL framework +===================== + +Overview +-------- + +TPL---Third Program Loader. + +Due to the SPL on some boards(powerpc mpc85xx) has a size limit and cannot +be compatible with all the external device(e.g. DDR). So add a tertiary +program loader (TPL) to enable a loader stub loaded by the code from the +SPL. It loads the final uboot image into DDR, then jump to it to begin +execution. Now, only the powerpc mpc85xx has this requirement and will +implemente it. + +Keep consistent with SPL, with this framework almost all source files for a +board can be reused. No code duplication or symlinking is necessary anymore. + +How it works +------------ + +There has been a directory $(srctree)/spl which contains only a Makefile. The +Makefile is shared by SPL and TPL. + +The object files are built separately for SPL/TPL and placed in the +directory spl/tpl. The final binaries which are generated are +u-boot-{spl|tpl}, u-boot-{spl|tpl}.bin and u-boot-{spl|tpl}.map. + +During the TPL build a variable named CONFIG_TPL_BUILD is exported in the +make environment and also appended to CPPFLAGS with -DCONFIG_TPL_BUILD. + +The SPL options are shared by SPL and TPL, the board config file should +determine which SPL options to choose based on whether CONFIG_TPL_BUILD +is set. Source files can be compiled for TPL with options choosed in the +board config file. + +For example: + +spl/Makefile: +LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o + +CONFIG_SPL_LIBCOMMON_SUPPORT is defined in board config file: +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#endif diff --git a/doc/README.android-fastboot b/doc/README.android-fastboot new file mode 100644 index 0000000000..167760968f --- /dev/null +++ b/doc/README.android-fastboot @@ -0,0 +1,96 @@ +Android Fastboot +~~~~~~~~~~~~~~~~ + +Overview +======== +The protocol that is used over USB is described in +README.android-fastboot-protocol in same directory. + +The current implementation does not yet support the erase command or the +"oem format" command, and there is minimal support for the flash command; +it only supports eMMC devices. + +Client installation +=================== +The counterpart to this gadget is the fastboot client which can +be found in Android's platform/system/core repository in the fastboot +folder. It runs on Windows, Linux and even OSX. Linux user are lucky since +they only need libusb. +Windows users need to bring some time until they have Android SDK (currently +http://dl.google.com/android/installer_r12-windows.exe) installed. You +need to install ADB package which contains the required glue libraries for +accessing USB. Also you need "Google USB driver package" and "SDK platform +tools". Once installed the usb driver is placed in your SDK folder under +extras\google\usb_driver. The android_winusb.inf needs a line like + + %SingleBootLoaderInterface% = USB_Install, USB\VID_0451&PID_D022 + +either in the [Google.NTx86] section for 32bit Windows or [Google.NTamd64] +for 64bit Windows. VID and PID should match whatever the fastboot is +advertising. + +Board specific +============== +The fastboot gadget relies on the USB download gadget, so the following +options must be configured: + +CONFIG_USBDOWNLOAD_GADGET +CONFIG_G_DNL_VENDOR_NUM +CONFIG_G_DNL_PRODUCT_NUM +CONFIG_G_DNL_MANUFACTURER + +NOTE: The CONFIG_G_DNL_VENDOR_NUM must be one of the numbers supported by +the fastboot client. The list of vendor IDs supported can be found in the +fastboot client source code (fastboot.c) mentioned above. + +The fastboot function is enabled by defining CONFIG_CMD_FASTBOOT and +CONFIG_ANDROID_BOOT_IMAGE. + +The fastboot protocol requires a large memory buffer for downloads. This +buffer should be as large as possible for a platform. The location of the +buffer and size are set with CONFIG_USB_FASTBOOT_BUF_ADDR and +CONFIG_USB_FASTBOOT_BUF_SIZE. + +In Action +========= +Enter into fastboot by executing the fastboot command in u-boot and you +should see: +|GADGET DRIVER: usb_dnl_fastboot + +On the client side you can fetch the bootloader version for instance: +|>fastboot getvar bootloader-version +|bootloader-version: U-Boot 2014.04-00005-gd24cabc +|finished. total time: 0.000s + +or initiate a reboot: +|>fastboot reboot + +and once the client comes back, the board should reset. + +You can also specify a kernel image to boot. You have to either specify +the an image in Android format _or_ pass a binary kernel and let the +fastboot client wrap the Android suite around it. On OMAP for instance you +take zImage kernel and pass it to the fastboot client: + +|>fastboot -b 0x80000000 -c "console=ttyO2 earlyprintk root=/dev/ram0 +| mem=128M" boot zImage +|creating boot image... +|creating boot image - 1847296 bytes +|downloading 'boot.img'... +|OKAY [ 2.766s] +|booting... +|OKAY [ -0.000s] +|finished. total time: 2.766s + +and on the gadget side you should see: +|Starting download of 1847296 bytes +|........................................................ +|downloading of 1847296 bytes finished +|Booting kernel.. +|## Booting Android Image at 0x81000000 ... +|Kernel load addr 0x80008000 size 1801 KiB +|Kernel command line: console=ttyO2 earlyprintk root=/dev/ram0 mem=128M +| Loading Kernel Image ... OK +|OK +| +|Starting kernel ... diff --git a/doc/README.android-fastboot-protocol b/doc/README.android-fastboot-protocol new file mode 100644 index 0000000000..e9e7166a26 --- /dev/null +++ b/doc/README.android-fastboot-protocol @@ -0,0 +1,170 @@ +FastBoot Version 0.4 +---------------------- + +The fastboot protocol is a mechanism for communicating with bootloaders +over USB. It is designed to be very straightforward to implement, to +allow it to be used across a wide range of devices and from hosts running +Linux, Windows, or OSX. + + +Basic Requirements +------------------ + +* Two bulk endpoints (in, out) are required +* Max packet size must be 64 bytes for full-speed and 512 bytes for + high-speed USB +* The protocol is entirely host-driven and synchronous (unlike the + multi-channel, bi-directional, asynchronous ADB protocol) + + +Transport and Framing +--------------------- + +1. Host sends a command, which is an ascii string in a single + packet no greater than 64 bytes. + +2. Client response with a single packet no greater than 64 bytes. + The first four bytes of the response are "OKAY", "FAIL", "DATA", + or "INFO". Additional bytes may contain an (ascii) informative + message. + + a. INFO -> the remaining 60 bytes are an informative message + (providing progress or diagnostic messages). They should + be displayed and then step #2 repeats + + b. FAIL -> the requested command failed. The remaining 60 bytes + of the response (if present) provide a textual failure message + to present to the user. Stop. + + c. OKAY -> the requested command completed successfully. Go to #5 + + d. DATA -> the requested command is ready for the data phase. + A DATA response packet will be 12 bytes long, in the form of + DATA00000000 where the 8 digit hexidecimal number represents + the total data size to transfer. + +3. Data phase. Depending on the command, the host or client will + send the indicated amount of data. Short packets are always + acceptable and zero-length packets are ignored. This phase continues + until the client has sent or received the number of bytes indicated + in the "DATA" response above. + +4. Client responds with a single packet no greater than 64 bytes. + The first four bytes of the response are "OKAY", "FAIL", or "INFO". + Similar to #2: + + a. INFO -> display the remaining 60 bytes and return to #4 + + b. FAIL -> display the remaining 60 bytes (if present) as a failure + reason and consider the command failed. Stop. + + c. OKAY -> success. Go to #5 + +5. Success. Stop. + + +Example Session +--------------- + +Host: "getvar:version" request version variable + +Client: "OKAY0.4" return version "0.4" + +Host: "getvar:nonexistant" request some undefined variable + +Client: "OKAY" return value "" + +Host: "download:00001234" request to send 0x1234 bytes of data + +Client: "DATA00001234" ready to accept data + +Host: < 0x1234 bytes > send data + +Client: "OKAY" success + +Host: "flash:bootloader" request to flash the data to the bootloader + +Client: "INFOerasing flash" indicate status / progress + "INFOwriting flash" + "OKAY" indicate success + +Host: "powerdown" send a command + +Client: "FAILunknown command" indicate failure + + +Command Reference +----------------- + +* Command parameters are indicated by printf-style escape sequences. + +* Commands are ascii strings and sent without the quotes (which are + for illustration only here) and without a trailing 0 byte. + +* Commands that begin with a lowercase letter are reserved for this + specification. OEM-specific commands should not begin with a + lowercase letter, to prevent incompatibilities with future specs. + + "getvar:%s" Read a config/version variable from the bootloader. + The variable contents will be returned after the + OKAY response. + + "download:%08x" Write data to memory which will be later used + by "boot", "ramdisk", "flash", etc. The client + will reply with "DATA%08x" if it has enough + space in RAM or "FAIL" if not. The size of + the download is remembered. + + "verify:%08x" Send a digital signature to verify the downloaded + data. Required if the bootloader is "secure" + otherwise "flash" and "boot" will be ignored. + + "flash:%s" Write the previously downloaded image to the + named partition (if possible). + + "erase:%s" Erase the indicated partition (clear to 0xFFs) + + "boot" The previously downloaded data is a boot.img + and should be booted according to the normal + procedure for a boot.img + + "continue" Continue booting as normal (if possible) + + "reboot" Reboot the device. + + "reboot-bootloader" Reboot back into the bootloader. + Useful for upgrade processes that require upgrading + the bootloader and then upgrading other partitions + using the new bootloader. + + "powerdown" Power off the device. + + + +Client Variables +---------------- + +The "getvar:%s" command is used to read client variables which +represent various information about the device and the software +on it. + +The various currently defined names are: + + version Version of FastBoot protocol supported. + It should be "0.3" for this document. + + version-bootloader Version string for the Bootloader. + + version-baseband Version string of the Baseband Software + + product Name of the product + + serialno Product serial number + + secure If the value is "yes", this is a secure + bootloader requiring a signature before + it will install or boot images. + +Names starting with a lowercase character are reserved by this +specification. OEM-specific names should not start with lowercase +characters. diff --git a/doc/README.arm-caches b/doc/README.arm-caches index f6a52e3e38..dbb6190b95 100644 --- a/doc/README.arm-caches +++ b/doc/README.arm-caches @@ -47,7 +47,7 @@ Cleanup Before Linux: - cleanup_before_linux() should flush the D-cache, invalidate I-cache, and disable MMU and caches. - The following sequence is advisable while disabling d-cache: - 1. disable_dcache() - flushes and disables d-cache + 1. dcache_disable() - flushes and disables d-cache 2. invalidate_dcache_all() - invalid any entry that came to the cache in the short period after the cache was flushed but before the cache got disabled. diff --git a/doc/README.arm-unaligned-accesses b/doc/README.arm-unaligned-accesses deleted file mode 100644 index c37d135852..0000000000 --- a/doc/README.arm-unaligned-accesses +++ /dev/null @@ -1,122 +0,0 @@ -If you are reading this because of a data abort: the following MIGHT -be relevant to your abort, if it was caused by an alignment violation. -In order to determine this, use the PC from the abort dump along with -an objdump -s -S of the u-boot ELF binary to locate the function where -the abort happened; then compare this function with the examples below. -If they match, then you've been hit with a compiler generated unaligned -access, and you should rewrite your code or add -mno-unaligned-access -to the command line of the offending file. - -Note that the PC shown in the abort message is relocated. In order to -be able to match it to an address in the ELF binary dump, you will need -to know the relocation offset. If your target defines CONFIG_CMD_BDI -and if you can get to the prompt and enter commands before the abort -happens, then command "bdinfo" will give you the offset. Otherwise you -will need to try a build with DEBUG set, which will display the offset, -or use a debugger and set a breakpoint at relocate_code() to see the -offset (passed as an argument). - -* - -Since U-Boot runs on a variety of hardware, some only able to perform -unaligned accesses with a strong penalty, some unable to perform them -at all, the policy regarding unaligned accesses is to not perform any, -unless absolutely necessary because of hardware or standards. - -Also, on hardware which permits it, the core is configured to throw -data abort exceptions on unaligned accesses in order to catch these -unallowed accesses as early as possible. - -Until version 4.7, the gcc default for performing unaligned accesses -(-mno-unaligned-access) is to emulate unaligned accesses using aligned -loads and stores plus shifts and masks. Emulated unaligned accesses -will not be caught by hardware. These accesses may be costly and may -be actually unnecessary. In order to catch these accesses and remove -or optimize them, option -munaligned-access is explicitly set for all -versions of gcc which support it. - -From gcc 4.7 onward starting at armv7 architectures, the default for -performing unaligned accesses is to use unaligned native loads and -stores (-munaligned-access), because the cost of unaligned accesses -has dropped on armv7 and beyond. This should not affect U-Boot's -policy of controlling unaligned accesses, however the compiler may -generate uncontrolled unaligned accesses on its own in at least one -known case: when declaring a local initialized char array, e.g. - -function foo() -{ - char buffer[] = "initial value"; -/* or */ - char buffer[] = { 'i', 'n', 'i', 't', 0 }; - ... -} - -Under -munaligned-accesses with optimizations on, this declaration -causes the compiler to generate native loads from the literal string -and native stores to the buffer, and the literal string alignment -cannot be controlled. If it is misaligned, then the core will throw -a data abort exception. - -Quite probably the same might happen for 16-bit array initializations -where the constant is aligned on a boundary which is a multiple of 2 -but not of 4: - -function foo() -{ - u16 buffer[] = { 1, 2, 3 }; - ... -} - -The long term solution to this issue is to add an option to gcc to -allow controlling the general alignment of data, including constant -initialization values. - -However this will only apply to the version of gcc which will have such -an option. For other versions, there are four workarounds: - -a) Enforce as a rule that array initializations as described above - are forbidden. This is generally not acceptable as they are valid, - and usual, C constructs. The only case where they could be rejected - is when they actually equate to a const char* declaration, i.e. the - array is initialized and never modified in the function's scope. - -b) Drop the requirement on unaligned accesses at least for ARMv7, - i.e. do not throw a data abort exception upon unaligned accesses. - But that will allow adding badly aligned code to U-Boot, only for - it to fail when re-used with a stricter target, possibly once the - bad code is already in mainline. - -c) Relax the -munaligned-access rule globally. This will prevent native - unaligned accesses of course, but that will also hide any bug caused - by a bad unaligned access, making it much harder to diagnose it. It - is actually what already happens when building ARM targets with a - pre-4.7 gcc, and it may actually already hide some bugs yet unseen - until the target gets compiled with -munaligned-access. - -d) Relax the -munaligned-access rule only for for files susceptible to - the local initialized array issue and for armv7 architectures and - beyond. This minimizes the quantity of code which can hide unwanted - misaligned accesses. - -The option retained is d). - -Considering that actual occurrences of the issue are rare (as of this -writing, 5 files out of 7840 in U-Boot, or .3%, contain an initialized -local char array which cannot actually be replaced with a const char*), -contributors should not be required to systematically try and detect -the issue in their patches. - -Detecting files susceptible to the issue can be automated through a -filter installed as a hook in .git which recognizes local char array -initializations. Automation should err on the false positive side, for -instance flagging non-local arrays as if they were local if they cannot -be told apart. - -In any case, detection shall not prevent committing the patch, but -shall pre-populate the commit message with a note to the effect that -this patch contains an initialized local char or 16-bit array and thus -should be protected from the gcc 4.7 issue. - -Upon a positive detection, either $(PLATFORM_NO_UNALIGNED) should be -added to CFLAGS for the affected file(s), or if the array is a pseudo -const char*, it should be replaced by an actual one. diff --git a/doc/README.arm64 b/doc/README.arm64 new file mode 100644 index 0000000000..75586dbaa7 --- /dev/null +++ b/doc/README.arm64 @@ -0,0 +1,46 @@ +U-boot for arm64 + +Summary +======= +No hardware platform of arm64 is available now. The u-boot is +simulated on Foundation Model and Fast Model for ARMv8. + +Notes +===== + +1. Currenly, u-boot run at the highest exception level processor + supported and jump to EL2 or optionally EL1 before enter OS. + +2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc + use rela relocation format, a tool(tools/relocate-rela) by Scott Wood + is used to encode the initial addend of rela to u-boot.bin. After running, + the u-boot will be relocated to destination again. + +3. Fdt should be placed at a 2-megabyte boundary and within the first 512 + megabytes from the start of the kernel image. So, fdt_high should be + defined specially. + Please reference linux/Documentation/arm64/booting.txt for detail. + +4. Spin-table is used to wake up secondary processors. One location + (or per processor location) is defined to hold the kernel entry point + for secondary processors. It must be ensured that the location is + accessible and zero immediately after secondary processor + enter slave_cpu branch execution in start.S. The location address + is encoded in cpu node of DTS. Linux kernel store the entry point + of secondary processors to it and send event to wakeup secondary + processors. + Please reference linux/Documentation/arm64/booting.txt for detail. + +5. Generic board is supported. + +6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and + aarch32 specific codes. + +Contributor +=========== + Tom Rini + Scott Wood + York Sun + Simon Glass + Sharma Bhupesh + Rob Herring diff --git a/doc/README.at91-soc b/doc/README.at91-soc index bed035c88d..ab3f713422 100644 --- a/doc/README.at91-soc +++ b/doc/README.at91-soc @@ -39,3 +39,10 @@ The method for updating 3. add new structures for SoC access 4. Convert arch, driver and boards file to new SoC 5. remove legacy code, if all boards and drives are ready + +2013-10-30 Andreas Bießmann : + +The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but +remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The +AT91 spi driver has also some CONFIG_ATMEL_LEGACY stuff left, so another point +to fix until this README can be removed. diff --git a/doc/README.atmel_pmecc b/doc/README.atmel_pmecc index b483744ea5..cc0f73db8f 100644 --- a/doc/README.atmel_pmecc +++ b/doc/README.atmel_pmecc @@ -19,17 +19,6 @@ To use PMECC in this driver, the user needs to set: It can be 2, 4, 8, 12 or 24. 2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE. It only can be 512 or 1024. - 3. The PMECC index lookup table's offsets in ROM code: CONFIG_PMECC_INDEX_TABLE_OFFSET. - In the chip datasheet section "Boot Stragegies", you can find - two Galois Field Table in the ROM code. One table is for 512-bytes - sector. Another is for 1024-byte sector. Each Galois Field includes - two sub-table: indext table & alpha table. - In the beginning of each Galois Field Table is the index table, - Alpha table is in the following. - So the index table's offset is same as the Galois Field Table. - - Please set CONFIG_PMECC_INDEX_TABLE_OFFSET correctly according the - Galois Field Table's offset base on the sector size you used. Take AT91SAM9X5EK as an example, the board definition file likes: @@ -38,7 +27,24 @@ Take AT91SAM9X5EK as an example, the board definition file likes: #define CONFIG_ATMEL_NAND_HW_PMECC 1 #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 -NOTE: If you use 1024 as the sector size, then need set 0x10000 as the - CONFIG_PMECC_INDEX_TABLE_OFFSET +How to enable PMECC header for direct programmable boot.bin +----------------------------------------------------------- +2014-05-19 Andreas Bießmann + +The usual way to program SPL into NAND flash is to use the SAM-BA Atmel tool. +This however is often not usable when doing field updates. To be able to +program a SPL binary into NAND flash we need to add the PMECC header to the +binary before. Chapter '12.4.4.1 NAND Flash Boot: NAND Flash Detection' in +sama5d3 SoC spec (as of 03. April 2014) defines how this PMECC header has to +look like. In order to do so we have a new image type added to mkimage to +generate this PMECC header and integrated this into the build process of SPL. + +To enable the generation of atmel PMECC header for SPL one need to define +CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER. The required parameters are taken from +board configuration and compiled into the host tools atmel_pmecc_params. This +tool will be called in build process to parametrize mkimage for atmelimage +type. The mkimage tool has intentionally _not_ compiled in those parameters. + +The mkimage image type atmelimage also set the 6'th interrupt vector to the +correct value. This feature can also be used to setup a boot.bin for MMC boot. diff --git a/doc/README.autoboot b/doc/README.autoboot index e4fabc90ce..14e3660dd8 100644 --- a/doc/README.autoboot +++ b/doc/README.autoboot @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Dave Ellis, SIXNET, dge@sixnetio.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ Using autoboot configuration options @@ -74,6 +74,7 @@ What they do "bootretry" is >= 0. CONFIG_AUTOBOOT_KEYED + CONFIG_AUTOBOOT_KEYED_CTRLC CONFIG_AUTOBOOT_PROMPT CONFIG_AUTOBOOT_DELAY_STR CONFIG_AUTOBOOT_STOP_STR @@ -135,6 +136,13 @@ What they do environment variable you can specify a second, alternate string (which allows you to have two "password" strings). + The CONFIG_AUTOBOOT_KEYED_CTRLC #define allows for the boot + sequence to be interrupted by ctrl-c, in addition to the + "bootdelaykey" and "bootstopkey". Setting this variable + provides an escape sequence from the limited "password" + strings. + + CONFIG_ZERO_BOOTDELAY_CHECK If this option is defined, you can stop the autoboot process diff --git a/doc/README.b4860qds b/doc/README.b4860qds index bd10a6df04..eada0c7dd8 100644 --- a/doc/README.b4860qds +++ b/doc/README.b4860qds @@ -5,7 +5,7 @@ The B4860QDS is a Freescale reference board that hosts the B4860 SoC (and varian B4860 Overview ------------- The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on -StarCore and Power Architecture® cores. It targets the broadband wireless +StarCore and Power Architecture® cores. It targets the broadband wireless infrastructure and builds upon the proven success of the existing multicore DSPs and Power CPUs. It is designed to bolster the rapidly changing and expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS. @@ -99,11 +99,11 @@ B4420 Personality B4420 Personality -------------------- B4420 is a reduced personality of B4860 with less core/clusters(both SC3900 and e6500), less DDR -controllers, less serdes lanes, less SGMII interfaces and reduced target frequencies. +controllers, less serdes lanes, less SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- - + B4420 has: 1. Less e6500 cores: 1 cluster with 2 e6500 cores 2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. @@ -130,7 +130,7 @@ Note: Boot location: NOR flash. SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz -a) NAND boot +a) NAND boot SW1 [1.1] = 0 SW2 [1.1] = 1 SW3 [1:4] = 0001 @@ -155,7 +155,7 @@ Note: Boot location: NOR flash. SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz -a) NAND boot +a) NAND boot SW1 [1.1] = 0 SW2 [1.1] = 1 SW3 [1:4] = 0001 @@ -227,17 +227,17 @@ Start Address End Address Description Size NOR Flash memory Map on B4860 and B4420QDS ------------------------------------------ Start End Definition Size -0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB -0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB -0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB -0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB -0xEDF80000 0xEDFFFFFF u-boot (alternate bank) 512KB -0xEDF60000 0xEDF7FFFF u-boot env (alternate bank) 128KB -0xEDF40000 0xEDF5FFFF FMAN ucode (alternate bank) 128KB -0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB +0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB +0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB +0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB +0xED300000 0xEDEFFFFF rootfs (current bank) 12MB 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB 0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB 0xEC000000 0xEC01FFFF RCW (current bank) 128KB @@ -246,7 +246,7 @@ Various Software configurations/environment variables/commands -------------------------------------------------------------- The below commands apply to both B4860QDS and B4420QDS. -1. U-boot environment variable hwconfig +1. U-boot environment variable hwconfig The default hwconfig is: hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: dr_mode=host,phy_type=ulpi @@ -258,7 +258,7 @@ The below commands apply to both B4860QDS and B4420QDS. 3. Switching to alternate bank Commands for switching to alternate bank. - 1. To change from vbank0 to vbank2 + 1. To change from vbank0 to vbank2 => qixis_reset altbank (it will boot using vbank2) 2.To change from vbank2 to vbank0 @@ -269,7 +269,7 @@ The below commands apply to both B4860QDS and B4420QDS. 1)Boot from vbank0 2)Flash vbank2 with b4420 rcw and u-boot 3)Give following commands to uboot prompt - => mw.b ffdf0040 0x30; + => mw.b ffdf0040 0x30; => mw.b ffdf0010 0x00; => mw.b ffdf0062 0x02; => mw.b ffdf0050 0x02; @@ -283,32 +283,32 @@ The below commands apply to both B4860QDS and B4420QDS. To change from NOR to NAND boot give following command on uboot prompt => mw.b ffdf0040 0x30 - => mw.b ffdf0010 0x00 + => mw.b ffdf0010 0x00 => mw.b 0xffdf0050 0x08 => mw.b 0xffdf0060 0x82 => mw.b ffdf0061 0x00 - => mw.b ffdf0010 0x30 + => mw.b ffdf0010 0x30 => reset To change from NAND to NOR boot give following command on uboot prompt: => mw.b ffdf0040 0x30 - => mw.b ffdf0010 0x00 + => mw.b ffdf0010 0x00 => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2) => mw.b 0xffdf0060 0x12 => mw.b ffdf0061 0x01 - => mw.b ffdf0010 0x30 + => mw.b ffdf0010 0x30 => reset Note: Power off cycle will lead to default switch settings. Note: 0xffdf0000 is the address of the QIXIS FPGA. -6. Ethernet interfaces for B4860QDS +6. Ethernet interfaces for B4860QDS Serdes protocosl tested: 0x2a, 0x8d (serdes1, serdes2) [DEFAULT] 0x2a, 0xb2 (serdes1, serdes2) When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G - SGMII on SGMII riser card. + SGMII on SGMII riser card. Under U-boot these network interfaces are recognized as: FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6. @@ -318,7 +318,7 @@ The below commands apply to both B4860QDS and B4420QDS. . eth4 -> fm1-gb4 . eth5 -> fm1-gb5 -7. RCW and Ethernet interfaces for B4420QDS +7. RCW and Ethernet interfaces for B4420QDS Serdes protocosl tested: 0x18, 0x9e (serdes1, serdes2) @@ -328,3 +328,39 @@ The below commands apply to both B4860QDS and B4420QDS. On Linux the interfaces are renamed as: . eth2 -> fm1-gb2 . eth3 -> fm1-gb3 + +NAND boot with 2 Stage boot loader +---------------------------------- +PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +u-boot(768 KB) from flash to DDR. +Finally SPL transer control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + + Run time view of SPL framework during boot :- + ----------------------------------------------- + Area | Address | +----------------------------------------------- + Secure boot | 0xFFFC0000 (32KB) | + headers | | + ----------------------------------------------- + GD, BD | 0xFFFC8000 (4KB) | + ----------------------------------------------- + ENV | 0xFFFC9000 (8KB) | + ----------------------------------------------- + HEAP | 0xFFFCB000 (30KB) | + ----------------------------------------------- + STACK | 0xFFFD8000 (22KB) | + ----------------------------------------------- + U-boot SPL | 0xFFFD8000 (160KB) | + ----------------------------------------------- + +NAND Flash memory Map on B4860 and B4420QDS +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x140000 0x15FFFF u-boot env 128KB +0x1A0000 0x1BFFFF FMAN Ucode 128KB diff --git a/doc/README.cfi b/doc/README.cfi index d087ff0d63..81e7cf1d7e 100644 --- a/doc/README.cfi +++ b/doc/README.cfi @@ -27,3 +27,16 @@ void flash_cmd_reset(flash_info_t *info) see also: http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html + + +Config Option + + CONFIG_SYS_MAX_FLASH_SECT: Number of sectors available on Flash device + + CONFIG_SYS_FLASH_CFI_WIDTH: Data-width of the flash device + + CONFIG_CMD_FLASH: Enables Flash command library + + CONFIG_FLASH_CFI_DRIVER: Enables CFI Flash driver + + CONFIG_FLASH_CFI_MTD: Enables MTD frame work for NOR Flash devices diff --git a/doc/README.clang b/doc/README.clang new file mode 100644 index 0000000000..fe36909449 --- /dev/null +++ b/doc/README.clang @@ -0,0 +1,56 @@ +The biggest problem when trying to compile U-boot with clang is that +almost all archs rely on storing gd in a global register and clang user +manual states: "clang does not support global register variables; this +is unlikely to be implemented soon because it requires additional LLVM +backend support." + +Since version 3.4 the ARM backend can be instructed to leave r9 alone. +Global registers themselves are not supported so some inline assembly is +used to get its value. This does lead to larger code then strictly +necessary, but at least works. + +NOTE: target compilation only work for _some_ ARM boards at the moment. +Also Aarch64 is not supported: Most notably boards which aren't using +the generic board will fail to compile, but since those are expected +to be converted this will solve itself. Boards which reassign gd in c +will also fail to compile, but there is in no strict reason to do so +in the ARM world, since crt0.S takes care of this. These assignments +can be avoided by changing the init calls but this is not in mainline yet. + +NOTE: without the -mllvm -arm-use-movt=0 flags u-boot will compile +fine, but llvm might hardcode addresses in movw / movt pairs, which +cannot be relocated and u-boot will fail at runtime. + +Debian (based) +-------------- +Binary packages can be installed as usual, e.g.: +sudo apt-get install clang + +To compile U-Boot with clang on linux without IAS use e.g.: +export TRIPLET=arm-linux-gnueabi && export CROSS_COMPILE="$TRIPLET-" +make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_defconfig +make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" all V=1 -j8 + +FreeBSD 11 (Current): +-------------------- +Since llvm 3.4 is currently in the base system, the integrated as is +incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils +is used instead. It needs a symlinks to be picked up correctly though: + +ln -s /usr/local/bin/arm-gnueabi-freebsd-as /usr/bin/arm-freebsd-eabi-as + +# The following commands compile U-Boot using the clang xdev toolchain. +# NOTE: CROSS_COMPILE and target differ on purpose! +export CROSS_COMPILE=arm-gnueabi-freebsd- +gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_defconfig +gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8 + +Given that u-boot will default to gcc, above commands can be +simplified with a simple wrapper script, listed below. + +/usr/local/bin/arm-gnueabi-freebsd-gcc +--- +#!/bin/sh + +exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0 "$@" + diff --git a/doc/README.commands b/doc/README.commands index 9eb367104f..afd5577b0a 100644 --- a/doc/README.commands +++ b/doc/README.commands @@ -28,7 +28,7 @@ these symbols when linking full U-Boot even though they are not referenced in the source code as such. If a new board is defined do not forget to define the command section -by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these +by writing in u-boot.lds ($(srctree)/board/boardname/u-boot.lds) these 3 lines: .u_boot_list : { diff --git a/doc/README.console b/doc/README.console index c9ef59e9a5..aadf596a8a 100644 --- a/doc/README.console +++ b/doc/README.console @@ -25,7 +25,7 @@ stdout or stderr) to any device you see in that list simply by assigning its name to the corresponding environment variable. For example: - setenv stdin wl_kbd <- To use the wireless keyboard + setenv stdin serial <- To use the serial input setenv stdout video <- To use the video console Do a simple "saveenv" to save the console settings in the environment @@ -99,4 +99,3 @@ The driver has been tested with the following configurations (see CREDITS for other contact informations): - MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it -- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it diff --git a/doc/README.designware_eth b/doc/README.designware_eth deleted file mode 100644 index 25ec6bd969..0000000000 --- a/doc/README.designware_eth +++ /dev/null @@ -1,25 +0,0 @@ -This driver supports Designware Ethernet Controller provided by Synopsis. - -The driver is enabled by CONFIG_DESIGNWARE_ETH. - -The driver has been developed and tested on SPEAr platforms. By default, the -MDIO interface works at 100/Full. #defining the below options in board -configuration file changes this behavior. - -Call an subroutine from respective board/.../board.c -designware_initialize(u32 id, ulong base_addr, u32 phy_addr); - -The various options suported by the driver are -1. CONFIG_DW_ALTDESCRIPTOR - Define this to use the Alternate/Enhanced Descriptor configurations. -1. CONFIG_DW_AUTONEG - Define this to autonegotiate with the host before proceeding with mac - level configuration. This obviates the definitions of CONFIG_DW_SPEED10M - and CONFIG_DW_DUPLEXHALF. -2. CONFIG_DW_SPEED10M - Define this to change the default behavior from 100Mbps to 10Mbps. -3. CONFIG_DW_DUPLEXHALF - Define this to change the default behavior from Full Duplex to Half. -4. CONFIG_DW_SEARCH_PHY - Define this to search the phy address. This would overwrite the value - passed as 3rd arg from designware_initialize routine. diff --git a/doc/README.distro b/doc/README.distro new file mode 100644 index 0000000000..dd0f1c7b6a --- /dev/null +++ b/doc/README.distro @@ -0,0 +1,341 @@ +/* + * (C) Copyright 2014 Red Hat Inc. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Generic Distro Configuration Concept +==================================== + +Linux distributions are faced with supporting a variety of boot mechanisms, +environments or bootloaders (PC BIOS, EFI, U-Boot, Barebox, ...). This makes +life complicated. Worse, bootloaders such as U-Boot have a configurable set +of features, and each board chooses to enable a different set of features. +Hence, distros typically need to have board-specific knowledge in order to +set up a bootable system. + +This document defines a common set of U-Boot features that are required for +a distro to support the board in a generic fashion. Any board wishing to +allow distros to install and boot in an out-of-the-box fashion should enable +all these features. Linux distros can then create a single set of boot +support/install logic that targets these features. This will allow distros +to install on many boards without the need for board-specific logic. + +In fact, some of these features can be implemented by any bootloader, thus +decoupling distro install/boot logic from any knowledge of the bootloader. + +This model assumes that boards will load boot configuration files from a +regular storage mechanism (eMMC, SD card, USB Disk, SATA disk, etc.) with +a standard partitioning scheme (MBR, GPT). Boards that cannnot support this +storage model are outside the scope of this document, and may still need +board-specific installer/boot-configuration support in a distro. + +To some extent, this model assumes that a board has a separate boot flash +that contains U-Boot, and that the user has somehow installed U-Boot to this +flash before running the distro installer. Even on boards that do not conform +to this aspect of the model, the extent of the board-specific support in the +distro installer logic would be to install a board-specific U-Boot package to +the boot partition partition during installation. This distro-supplied U-Boot +can still implement the same features as on any other board, and hence the +distro's boot configuration file generation logic can still be board-agnostic. + +Locating Bootable Disks +----------------------- + +Typical desktop/server PCs search all (or a user-defined subset of) attached +storage devices for a bootable partition, then load the bootloader or boot +configuration files from there. A U-Boot board port that enables the features +mentioned in this document will search for boot configuration files in the +same way. + +Thus, distros do not need to manipulate any kind of bootloader-specific +configuration data to indicate which storage device the system should boot +from. + +Distros simply need to install the boot configuration files (see next +section) in an ext2/3/4 or FAT partition, mark the partition bootable (via +the MBR bootable flag, or GPT legacy_bios_bootable attribute), and U-Boot (or +any other bootloader) will find those boot files and execute them. This is +conceptually identical to creating a grub2 configuration file on a desktop +PC. + +Note that in the absense of any partition that is explicitly marked bootable, +U-Boot falls back to searching the first valid partition of a disk for boot +configuration files. Other bootloaders are recommended to do the same, since +I believe that partition table bootable flags aren't so commonly used outside +the realm of x86 PCs. + +U-Boot can also search for boot configuration files from a TFTP server. + +Boot Configuration Files +------------------------ + +The standard format for boot configuration files is that of extlinux.conf, as +handled by U-Boot's "syslinux" (disk) or "pxe boot" (network). This is roughly +as specified at: + +http://www.freedesktop.org/wiki/Specifications/BootLoaderSpec/ + +... with the exceptions that the BootLoaderSpec document: + +* Prescribes a separate configuration per boot menu option, whereas U-Boot + lumps all options into a single extlinux.conf file. Hence, U-Boot searches + for /extlinux/extlinux.conf then /boot/extlinux/extlinux.conf on disk, or + pxelinux.cfg/default over the network. + +* Does not document the fdtdir option, which automatically selects the DTB to + pass to the kernel. + +One example extlinux.conf generated by the Fedora installer is: + +------------------------------------------------------------ +# extlinux.conf generated by anaconda + +ui menu.c32 + +menu autoboot Welcome to Fedora. Automatic boot in # second{,s}. Press a key for options. +menu title Fedora Boot Options. +menu hidden + +timeout 50 +#totaltimeout 9000 + +default Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae) 22 (Rawhide) + +label Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl) 22 (Rawhide) + kernel /boot/vmlinuz-3.17.0-0.rc4.git2.1.fc22.armv7hl + append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8 LANG=en_US.UTF-8 drm.debug=0xf + fdtdir /boot/dtb-3.17.0-0.rc4.git2.1.fc22.armv7hl + initrd /boot/initramfs-3.17.0-0.rc4.git2.1.fc22.armv7hl.img + +label Fedora (3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae) 22 (Rawhide) + kernel /boot/vmlinuz-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae + append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8 LANG=en_US.UTF-8 drm.debug=0xf + fdtdir /boot/dtb-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae + initrd /boot/initramfs-3.17.0-0.rc4.git2.1.fc22.armv7hl+lpae.img + +label Fedora-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc (0-rescue-8f6ba7b039524e0eb957d2c9203f04bc) + kernel /boot/vmlinuz-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc + initrd /boot/initramfs-0-rescue-8f6ba7b039524e0eb957d2c9203f04bc.img + append ro root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450 console=ttyS0,115200n8 + fdtdir /boot/dtb-3.16.0-0.rc6.git1.1.fc22.armv7hl+lpae +------------------------------------------------------------ + +Another hand-crafted network boot configuration file is: + +------------------------------------------------------------ +TIMEOUT 100 + +MENU TITLE TFTP boot options + +LABEL jetson-tk1-emmc + MENU LABEL ../zImage root on Jetson TK1 eMMC + LINUX ../zImage + FDTDIR ../ + APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=80a5a8e9-c744-491a-93c1-4f4194fd690b + +LABEL venice2-emmc + MENU LABEL ../zImage root on Venice2 eMMC + LINUX ../zImage + FDTDIR ../ + APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=5f71e06f-be08-48ed-b1ef-ee4800cc860f + +LABEL sdcard + MENU LABEL ../zImage, root on 2GB sdcard + LINUX ../zImage + FDTDIR ../ + APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=b2f82cda-2535-4779-b467-094a210fbae7 + +LABEL fedora-installer-fk + MENU LABEL Fedora installer w/ Fedora kernel + LINUX fedora-installer/vmlinuz + INITRD fedora-installer/initrd.img.orig + FDTDIR fedora-installer/dtb + APPEND loglevel=8 ip=dhcp inst.repo=http://10.0.0.2/mirrors/fedora/linux/development/rawhide/armhfp/os/ rd.shell cma=64M +------------------------------------------------------------ + +U-Boot Implementation +===================== + +Enabling the distro options +--------------------------- + +In your board configuration file, include the following: + +------------------------------------------------------------ +#ifndef CONFIG_SPL_BUILD +#include +#include +#endif +------------------------------------------------------------ + +The first of those headers primarily enables a core set of U-Boot features, +such as support for MBR and GPT partitions, ext* and FAT filesystems, booting +raw zImage and initrd (rather than FIT- or uImage-wrapped files), etc. Network +boot support is also enabled here, which is useful in order to boot distro +installers given that distros do not commonly distribute bootable install +media for non-PC targets at present. + +Finally, a few options that are mostly relevant only when using U-Boot- +specific boot.scr scripts are enabled. This enables distros to generate a +U-Boot-specific boot.scr script rather than extlinux.conf as the boot +configuration file. While doing so is fully supported, and + exposes enough parameterization to boot.scr to +allow for board-agnostic boot.scr content, this document recommends that +distros generate extlinux.conf rather than boot.scr. extlinux.conf is intended +to work across multiple bootloaders, whereas boot.scr will only work with +U-Boot. TODO: document the contract between U-Boot and boot.scr re: which +environment variables a generic boot.scr may rely upon. + +The second of those headers sets up the default environment so that $bootcmd +is defined in a way that searches attached disks for boot configuration files, +and executes them if found. + +Required Environment Variables +------------------------------ + +The U-Boot "syslinux" and "pxe boot" commands require a number of environment +variables be set. Default values for these variables are often hard-coded into +CONFIG_EXTRA_ENV_SETTINGS in the board's U-Boot configuration file, so that +the user doesn't have to configure them. + +fdt_addr: + + Mandatory for any system that provides the DTB in HW (e.g. ROM) and wishes + to pass that DTB to Linux, rather than loading a DTB from the boot + filesystem. Prohibited for any other system. + + If specified a DTB to boot the system must be available at the given + address. + +fdt_addr_r: + + Mandatory. The location in RAM where the DTB will be loaded or copied to when + processing the fdtdir/devicetreedir or fdt/devicetree options in + extlinux.conf. + + This is mandatory even when fdt_addr is provided, since extlinux.conf must + always be able to provide a DTB which overrides any copy provided by the HW. + + A size of 1MB for the FDT/DTB seems reasonable. + +ramdisk_addr_r: + + Mandatory. The location in RAM where the initial ramdisk will be loaded to + when processing the initrd option in extlinux.conf. + + It is recommended that this location be highest in RAM out of fdt_addr_, + kernel_addr_r, and ramdisk_addr_r, so that the RAM disk can vary in size + and use any available RAM. + +kernel_addr_r: + + Mandatory. The location in RAM where the kernel will be loaded to when + processing the kernel option in the extlinux.conf. + + The kernel should be located within the first 128M of RAM in order for the + kernel CONFIG_AUTO_ZRELADDR option to work, which is likely enabled on any + distro kernel. Since the kernel will decompress itself to 0x8000 after the + start of RAM, kernel_addr_rshould not overlap that area, or the kernel will + have to copy itself somewhere else first before decompression. + + A size of 16MB for the kernel is likely adequate. + +pxe_addr_r: + + Mandatory. The location in RAM where extlinux.conf will be loaded to prior + to processing. + + A size of 1MB for extlinux.conf is more than adequate. + +scriptaddr: + + Mandatory, if the boot script is boot.scr rather than extlinux.conf. The + location in RAM where boot.scr will be loaded to prior to execution. + + A size of 1MB for extlinux.conf is more than adequate. + +For suggestions on memory locations for ARM systems, you must follow the +guidelines specified in Documentation/arm/Booting in the Linux kernel tree. + +For a commented example of setting these values, please see the definition of +MEM_LAYOUT_ENV_SETTINGS in include/configs/tegra124-common.h. + +Boot Target Configuration +------------------------- + + defines $bootcmd and many helper command variables +that automatically search attached disks for boot configuration files and +execute them. Boards must provide configure so that +it supports the correct set of possible boot device types. To provide this +configuration, simply define macro BOOT_TARGET_DEVICES prior to including +. For example: + +------------------------------------------------------------ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#include +#endif +------------------------------------------------------------ + +Each entry in the macro defines a single boot device (e.g. a specific eMMC +device or SD card) or type of boot device (e.g. USB disk). The parameters to +the func macro (passed in by the internal implementation of the header) are: + +- Upper-case disk type (MMC, SATA, SCSI, IDE, USB, DHCP, PXE). +- Lower-case disk type (same options as above). +- ID of the specific disk (MMC only) or ignored for other types. + +User Configuration +================== + +Once the user has installed U-Boot, it is expected that the environment will +be reset to the default values in order to enable $bootcmd and friends, as set +up by . After this, various environment variables may +be altered to influence the boot process: + +boot_targets: + + The list of boot locations searched. + + Example: mmc0, mmc1, usb, pxe + + Entries may be removed or re-ordered in this list to affect the boot order. + +boot_prefixes: + + For disk-based booting, the list of directories within a partition that are + searched for boot configuration files (extlinux.conf, boot.scr). + + Example: / /boot/ + + Entries may be removed or re-ordered in this list to affect the set of + directories which are searched. + +boot_scripts: + + The name of U-Boot style boot.scr files that $bootcmd searches for. + + Example: boot.scr.uimg boot.scr + + (Typically we expect extlinux.conf to be used, but execution of boot.scr is + maintained for backwards-compatibility.) + + Entries may be removed or re-ordered in this list to affect the set of + filenames which are supported. + +scan_dev_for_extlinux: + + If you want to disable extlinux.conf on all disks, set the value to something + innocuous, e.g. setenv scan_dev_for_extlinux true. + +scan_dev_for_scripts: + + If you want to disable boot.scr on all disks, set the value to something + innocuous, e.g. setenv scan_dev_for_scripts true. diff --git a/doc/README.ext4 b/doc/README.ext4 index b7d0ad3930..9a2de5088b 100644 --- a/doc/README.ext4 +++ b/doc/README.ext4 @@ -28,30 +28,30 @@ Steps to test: 1. After applying the patch, ext4 specific commands can be seen in the boot loader prompt using - UBOOT #help + UBOOT #help - ext4load- load binary file from a Ext4 file system - ext4ls - list files in a directory (default /) - ext4write- create a file in ext4 formatted partition + ext4load- load binary file from a Ext4 file system + ext4ls - list files in a directory (default /) + ext4write- create a file in ext4 formatted partition 2. To list the files in ext4 formatted partition, execute - ext4ls [directory] - For example: - UBOOT #ext4ls mmc 0:5 /usr/lib + ext4ls [directory] + For example: + UBOOT #ext4ls mmc 0:5 /usr/lib 3. To read and load a file from an ext4 formatted partition to RAM, execute - ext4load [addr] [filename] [bytes] - For example: - UBOOT #ext4load mmc 2:2 0x30007fc0 uImage + ext4load [addr] [filename] [bytes] + For example: + UBOOT #ext4load mmc 2:2 0x30007fc0 uImage 4. To write a file to a ext4 formatted partition. - a) First load a file to RAM at a particular address for example 0x30007fc0. - Now execute ext4write command - ext4write [filename] [Address] [sizebytes] - For example: - UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120 - (here 6183120 is the size of the file to be written) - Note: Absolute path is required for the file to be written + a) First load a file to RAM at a particular address for example 0x30007fc0. + Now execute ext4write command + ext4write [filename] [Address] [sizebytes] + For example: + UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120 + (here 6183120 is the size of the file to be written) + Note: Absolute path is required for the file to be written References : -- ext4 implementation in Linux Kernel diff --git a/doc/README.falcon b/doc/README.falcon index 93e855d20e..e9f8a7583c 100644 --- a/doc/README.falcon +++ b/doc/README.falcon @@ -31,9 +31,10 @@ informed to load it before running the kernel. To boot the kernel, these steps under a Falcon-aware U-Boot are required: 1. Boot the board into U-Boot. -Use the "spl export" command to generate the kernel parameters area or the DT. -U-Boot runs as when it boots the kernel, but stops before passing the control -to the kernel. +After loading the desired legacy-format kernel image into memory (and DT as +well, if used), use the "spl export" command to generate the kernel parameters +area or the DT. U-Boot runs as when it boots the kernel, but stops before +passing the control to the kernel. 2. Save the prepared snapshot into persistent media. The address where to save it must be configured into board configuration @@ -41,6 +42,8 @@ file (CONFIG_CMD_SPL_NAND_OFS for NAND). 3. Boot the board into Falcon Mode. SPL will load the kernel and copy the parameters which are saved in the persistent area to the required address. +If a valid uImage is not found at the defined location, U-Boot will be +booted instead. It is required to implement a custom mechanism to select if SPL loads U-Boot or another image. @@ -78,6 +81,19 @@ spl_start_uboot() : required Returns "0" if SPL should start the kernel, "1" if U-Boot must be started. +Environment variables +--------------------- + +A board may chose to look at the environment for decisions about falcon +mode. In this case the following variables may be supported: + +boot_os : Set to yes/Yes/true/True/1 to enable booting to OS, + any other value to fall back to U-Boot (including + unset) +falcon_args_file : Filename to load as the 'args' portion of falcon mode + rather than the hard-coded value. +falcon_image_file : Filename to load as the OS image portion of falcon + mode rather than the hard-coded value. Using spl command ----------------- diff --git a/doc/README.fdt-control b/doc/README.fdt-control index 86bae6816d..d8fe4a826f 100644 --- a/doc/README.fdt-control +++ b/doc/README.fdt-control @@ -66,11 +66,11 @@ Tools To use this feature you will need to get the device tree compiler here: - git://jdl.com/software/dtc.git + git://git.kernel.org/pub/scm/utils/dtc/dtc.git For example: - $ git clone git://jdl.com/software/dtc.git + $ git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git $ cd dtc $ make $ sudo make install @@ -122,7 +122,8 @@ This should include your CPU or SOC's device tree file, placed in arch//dts, and then make any adjustments required. If CONFIG_OF_EMBED is defined, then it will be picked up and built into -the U-Boot image (including u-boot.bin). +the U-Boot image (including u-boot.bin). This is suitable for debugging +and development only and is not recommended for production devices. If CONFIG_OF_SEPARATE is defined, then it will be built and placed in a u-boot.dtb file alongside u-boot.bin. A common approach is then to @@ -130,7 +131,10 @@ join the two: cat u-boot.bin u-boot.dtb >image.bin -and then flash image.bin onto your board. +and then flash image.bin onto your board. Note that U-Boot creates +u-boot-dtb.bin which does the above step for you also. If you are using +CONFIG_SPL_FRAMEWORK, then u-boot.img will be built to include the device +tree binary. If CONFIG_OF_HOSTFILE is defined, then it will be read from a file on startup. This is only useful for sandbox. Use the -d flag to U-Boot to @@ -138,6 +142,14 @@ specify the file to read. You cannot use more than one of these options at the same time. +To use a device tree file that you have compiled yourself, pass +EXT_DTB= to 'make', as in: + + make EXT_DTB=boot/am335x-boneblack-pubkey.dtb + +Then U-Boot will copy that file to u-boot.dtb, put it in the .img file +if used, and u-boot-dtb.bin. + If you wish to put the fdt at a different address in memory, you can define the "fdtcontroladdr" environment variable. This is the hex address of the fdt binary blob, and will override either of the options. diff --git a/doc/README.fsl-dpaa b/doc/README.fsl-dpaa new file mode 100644 index 0000000000..0d8d4f6efc --- /dev/null +++ b/doc/README.fsl-dpaa @@ -0,0 +1,10 @@ +This file documents Freescale DPAA-specific options. + +FMan (Frame Manager) + - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION + on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: + 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 + on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: + 10GEC1->MAC1, 10GEC2->MAC2 + so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on + which 10GEC enumeration is consistent with MAC enumeration. diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc new file mode 100644 index 0000000000..b70f271d1a --- /dev/null +++ b/doc/README.fsl-esdhc @@ -0,0 +1,5 @@ +CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. +CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. + +Accessing ESDHC registers can be determined by ESDHC IP's endian +mode or processor's endian mode. diff --git a/doc/README.generic-board b/doc/README.generic-board new file mode 100644 index 0000000000..37c1b03ced --- /dev/null +++ b/doc/README.generic-board @@ -0,0 +1,190 @@ +# +# (C) Copyright 2014 Google, Inc +# Simon Glass +# +# SPDX-License-Identifier: GPL-2.0+ +# + +DEPRECATION NOTICE FOR arch//lib/board.c + +For board maintainers: Please submit patches for boards you maintain before +July 2014, to make them use generic board. + +For architecture maintainers: Please submit patches to remove your +architecture-specific board.c file before October 2014. + + +Background +---------- + +U-Boot has traditionally had a board.c file for each architecture. This has +introduced quite a lot of duplication, with each architecture tending to do +initialisation slightly differently. To address this, a new 'generic board +init' feature was introduced a year ago in March 2013 (further motivation is +provided in the cover letter below). + + +What has changed? +----------------- + +The main change is that the arch//lib/board.c file is being removed in +favour of common/board_f.c (for pre-relocation init) and common/board_r.c +(for post-relocation init). + +Related to this, the global_data and bd_t structures now have a core set of +fields which are common to all architectures. Architecture-specific fields +have been moved to separate structures. + + +Supported Arcthitectures +------------------------ + +If you are unlucky then your architecture may not support generic board. +The following architectures are supported now: + + arc + arm + mips + powerpc + sandbox + x86 + +If your architecture is not supported, you need to adjust your +arch//config.mk file to include: + + __HAVE_ARCH_GENERIC_BOARD := y + +and test it with a suitable board, as follows. + + +Adding Support for your Board +----------------------------- + +To enable generic board for your board, define CONFIG_SYS_GENERIC_BOARD in +your board config header file. + +Test that U-Boot still functions correctly on your board, and fix any +problems you find. Don't be surprised if there are no problems - generic +board has had a reasonable amount of testing with common boards. + + +DeadLine +-------- + +Please don't take this the wrong way - there is no intent to make your life +miserable, and we have the greatest respect and admiration for U-Boot users. +However, with any migration there has to be a period where the old way is +deprecated and removed. Every patch to the deprecated code introduces a +potential breakage in the new unused code. Therefore: + +Boards or architectures not converted over to general board by the +end of 2014 may be forcibly changed over (potentially causing run-time +breakage) or removed. + + + +Further Background +------------------ + +The full text of the original generic board series is reproduced below. + +--8<------------- + +This series creates a generic board.c implementation which contains +the essential functions of the major arch/xxx/lib/board.c files. + +What is the motivation for this change? + +1. There is a lot of repeated code in the board.c files. Any change to +things like setting up the baud rate requires a change in 10 separate +places. + +2. Since there are 10 separate files, adding a new feature which requires +initialisation is painful since it must be independently added in 10 +places. + +3. As time goes by the architectures naturely diverge since there is limited +pressure to compare features or even CONFIG options against simiilar things +in other board.c files. + +4. New architectures must implement all the features all over again, and +sometimes in subtley different ways. This places an unfair burden on getting +a new architecture fully functional and running with U-Boot. + +5. While it is a bit of a tricky change, I believe it is worthwhile and +achievable. There is no requirement that all code be common, only that +the code that is common should be located in common/board.c rather than +arch/xxx/lib/board.c. + +All the functions of board_init_f() and board_init_r() are broken into +separate function calls so that they can easily be included or excluded +for a particular architecture. It also makes it easier to adopt Graeme's +initcall proposal when it is ready. + +http://lists.denx.de/pipermail/u-boot/2012-January/114499.html + +This series removes the dependency on generic relocation. So relocation +happens as one big chunk and is still completely arch-specific. See the +relocation series for a proposed solution to this for ARM: + +http://lists.denx.de/pipermail/u-boot/2011-December/112928.html + +or Graeme's recent x86 series v2: + +http://lists.denx.de/pipermail/u-boot/2012-January/114467.html + +Instead of moving over a whole architecture, this series takes the approach +of simply enabling generic board support for an architecture. It is then up +to each board to opt in by defining CONFIG_SYS_GENERIC_BOARD in the board +config file. If this is not done, then the code will be generated as +before. This allows both sets of code to co-exist until we are comfortable +with the generic approach, and enough boards run. + +ARM is a relatively large board.c file and one which I can test, therefore +I think it is a good target for this series. On the other hand, x86 is +relatively small and simple, but different enough that it introduces a +few issues to be solved. So I have chosen both ARM and x86 for this series. +After a suggestion from Wolfgang I have added PPC also. This is the +largest and most feature-full board, so hopefully we have all bases +covered in this RFC. + +A generic global_data structure is also required. This might upset a few +people. Here is my basic reasoning: most fields are the same, all +architectures include and need it, most global_data.h files already have +#ifdefs to select fields for a particular SOC, so it is hard to +see why architecures are different in this area. We can perhaps add a +way to put architecture-specific fields into a separate header file, but +for now I have judged that to be counter-productive. + +Similarly we need a generic bd_info structure, since generic code will +be accessing it. I have done this in the same way as global_data and the +same comments apply. + +There was dicussion on the list about passing gd_t around as a parameter +to pre-relocation init functions. I think this makes sense, but it can +be done as a separate change, and this series does not require it. + +While this series needs to stand on its own (as with the link script +cleanup series and the generic relocation series) the goal is the +unification of the board init code. So I hope we can address issues with +this in mind, rather than focusing too narrowly on particular ARM, x86 or +PPC issues. + +I have run-tested ARM on Tegra Seaboard only. To try it out, define +CONFIG_SYS_GENERIC_BOARD in your board file and rebuild. Most likely on +x86 and PPC at least it will hang, but if you are lucky it will print +something first :-) + +I have run this though MAKEALL with CONFIG_SYS_GENERIC_BOARD on for all +ARM, PPC and x86 boards. There are a few failures due to errors in +the board config, which I have sent patches for. The main issue is +just the difference between __bss_end and __bss_end__. + +Note: the first group of commits are required for this series to build, +but could be separated out if required. I have included them here for +convenience. + +------------->8-- + +Simon Glass, sjg@chromium.org +March 2014 diff --git a/doc/README.gpt b/doc/README.gpt index 81dfe584c5..ec0156d8aa 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -6,7 +6,6 @@ # # SPDX-License-Identifier: GPL-2.0+ - Glossary: ======== - UUID -(Universally Unique Identifier) @@ -22,7 +21,6 @@ Introduction: This document describes the GPT partition table format and usage of the gpt command in u-boot. - UUID introduction: ==================== @@ -68,17 +66,16 @@ GPT brief explanation: |Partition n | | | ---------------------------------------------------------- - LBA -34 |Entry 1|Entry 2| Entry 3| Entry 4| Secondary - -------------------------------------------------- (bkp) - LBA -33 |Entries 5 - 128 | GPT + LBA -34 |Entry 1|Entry 2| Entry 3| Entry 4| Backup + -------------------------------------------------- GPT + LBA -33 |Entries 5 - 128 | | | | | LBA -2 | | -------------------------------------------------- - LBA -1 |Secondary GPT Header | + LBA -1 |Backup GPT Header | ---------------------------------------------------------- - For a legacy reasons, GPT's LBA 0 sector has a MBR structure. It is called "protective MBR". Its first partition entry ID has 0xEE value, and disk software, which is not @@ -89,7 +86,7 @@ It is possible to define 128 linearly placed partition entries. "LBA -1" means the last addressable block (in the mmc subsystem: "dev_desc->lba - 1") -Primary/Secondary GPT header: +Primary/Backup GPT header: ---------------------------- Offset Size Description @@ -114,12 +111,11 @@ Offset Size Description TOTAL: 512 B - IMPORTANT: GPT headers and partition entries are protected by CRC32 (the POSIX CRC32). -Primary GPT header and Secondary GPT header have swapped values of "Current LBA" +Primary GPT header and Backup GPT header have swapped values of "Current LBA" and "Backup LBA" and therefore different CRC32 check-sum. CRC32 for GPT headers (field "CRC of header") are calculated up till @@ -129,16 +125,15 @@ CRC32 for partition entries (field "CRC32 of partition array") is calculated for the whole array entry ( Number_of_partition_entries * sizeof(partition_entry_size (usually 128))) -Observe, how Secondary GPT is placed in the memory. It is NOT a mirror reflect +Observe, how Backup GPT is placed in the memory. It is NOT a mirror reflect of the Primary. - Partition Entry Format: ---------------------- Offset Size Description - 0 16 B Partition type GUID - 16 16 B Unique partition GUID + 0 16 B Partition type GUID (Big Endian) + 16 16 B Unique partition GUID in (Big Endian) 32 8 B First LBA (Little Endian) 40 8 B Last LBA (inclusive) 48 8 B Attribute flags [+] @@ -150,7 +145,6 @@ of the Primary. Bit 62 - Hidden Bit 63 - Not mount - Creating GPT partitions in U-Boot: ============== @@ -166,20 +160,31 @@ To restore GUID partition table one needs to: Fields 'name', 'size' and 'uuid' are mandatory for every partition. The field 'start' is optional. + option: CONFIG_RANDOM_UUID + If any partition "UUID" no exists then it is randomly generated. + 2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT' 2. From u-boot prompt type: gpt write mmc 0 $partitions - Useful info: ============ -Two programs, namely: 'fdisk' and 'parted' are recommended to work with GPT -recovery. Parted is able to handle GUID partitions. Unfortunately the 'fdisk' -hasn't got such ability. +Two programs, namely: 'gdisk' and 'parted' are recommended to work with GPT +recovery. Both are able to handle GUID partitions. Please, pay attention at -l switch for parted. "uuid" program is recommended to generate UUID string. Moreover it can decode (-d switch) passed in UUID string. It can be used to generate partitions UUID passed to u-boot environment variables. +If optional CONFIG_RANDOM_UUID is defined then for any partition which environment +uuid is unset, uuid is randomly generated and stored in correspond environment +variable. + +note: +Each string block of UUID generated by program "uuid" is in big endian and it is +also stored in big endian in disk GPT. +Partitions layout can be printed by typing "mmc part". Note that each partition +GUID has different byte order than UUID generated before, this is because first +three blocks of GUID string are in Little Endian. diff --git a/doc/README.hwconfig b/doc/README.hwconfig index cf549651c7..b6ddb438cf 100644 --- a/doc/README.hwconfig +++ b/doc/README.hwconfig @@ -18,7 +18,7 @@ Current implementation details/limitations: U-Boot. But I haven't bothered yet. 2. Since we don't implement a hwconfig command, i.e. we're working - with the environement directly, there is no way to tell that + with the environment directly, there is no way to tell that toggling a particular option will need a reboot to take effect. So, for now it's advised to always reboot the target after modifying the hwconfig variable. diff --git a/doc/README.imx6 b/doc/README.imx6 index 513a06ee86..437af2fd9a 100644 --- a/doc/README.imx6 +++ b/doc/README.imx6 @@ -8,3 +8,79 @@ SoC. 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the 16 msbs in word 3. + +Example: + +For reading the MAC address fuses on a MX6Q: + +- The MAC address is stored in two fuse addresses (the fuse addresses are +described in the Fusemap Descriptions table from the mx6q Reference Manual): + +0x620[31:0] - MAC_ADDR[31:0] +0x630[15:0] - MAC_ADDR[47:32] + +In order to use the fuse API, we need to pass the bank and word values, which +are calculated as below: + +Fuse address for the lower MAC address: 0x620 +Base address for the fuses: 0x400 + +(0x620 - 0x400)/0x10 = 0x22 = 34 decimal + +As the fuses are arranged in banks of 8 words: + +34 / 8 = 4 and the remainder is 2, so in this case: + +bank = 4 +word = 2 + +And the U-boot command would be: + +=> fuse read 4 2 +Reading bank 4: + +Word 0x00000002: 9f027772 + +Doing the same for the upper MAC address: + +Fuse address for the upper MAC address: 0x630 +Base address for the fuses: 0x400 + +(0x630 - 0x400)/0x10 = 0x23 = 35 decimal + +As the fuses are arranged in banks of 8 words: + +35 / 8 = 4 and the remainder is 3, so in this case: + +bank = 4 +word = 3 + +And the U-boot command would be: + +=> fuse read 4 3 +Reading bank 4: + +Word 0x00000003: 00000004 + +,which matches the ethaddr value: +=> echo ${ethaddr} +00:04:9f:02:77:72 + +Some other useful hints: + +- The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference +Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register +Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual, +Rev. 1, 04/2013" document. For example, for the MAC fuses we have: + +Address: +21B_C620 Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0) + +21B_C630 Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1) + +- The command '=> fuse read 4 2 2' reads the whole MAC addresses at once: + +=> fuse read 4 2 2 +Reading bank 4: + +Word 0x00000002: 9f027772 00000004 diff --git a/doc/README.imximage b/doc/README.imximage index 802eb90f1d..27d3354569 100644 --- a/doc/README.imximage +++ b/doc/README.imximage @@ -15,9 +15,6 @@ Booting from NOR flash does not require to use this image type. For more details refer Chapter 2 - System Boot and section 2.14 (flash header description) of the processor's manual. -This implementation does not use at the moment the secure boot feature -of the processor. The image is generated disabling all security fields. - Command syntax: -------------- ./tools/mkimage -l @@ -86,6 +83,33 @@ Configuration command line syntax: Example: BOOT_FROM spi + CSF value + + Total size of CSF (Command Sequence File) + used for Secure Boot/ High Assurance Boot + (HAB). + + Using this command will populate the IVT + (Initial Vector Table) CSF pointer and adjust + the length fields only. The CSF itself needs + to be generated with Freescale tools and + 'manually' appended to the u-boot.imx file. + + The CSF is then simply concatenated + to the u-boot image, making a signed bootloader, + that the processor can verify + if the fuses for the keys are burned. + + Further infos how to configure the SOC to verify + the bootloader can be found in the "High + Assurance Boot Version Application Programming + Interface Reference Manual" as part of the + Freescale Code Signing Tool, available on the + manufacturer's website. + + Example: + CSF 0x2000 + DATA type address value type: word=4, halfword=2, byte=1 @@ -96,7 +120,7 @@ Configuration command line syntax: DATA 4 0x73FA88a0 0x200 The processor support up to 60 register programming commands for IMXIMAGE_VERSION 1 -and 121 register programming commands for IMXIMAGE_VERSION 2. +and 220 register programming commands for IMXIMAGE_VERSION 2. An error is generated if more commands are found in the configuration file. 3. All commands are optional to program. diff --git a/doc/README.kconfig b/doc/README.kconfig new file mode 100644 index 0000000000..69dc45970b --- /dev/null +++ b/doc/README.kconfig @@ -0,0 +1,226 @@ +Kconfig in U-Boot +================= + +This document describes the configuration infrastructure of U-Boot. + +The conventional configuration was replaced by Kconfig at v2014.10-rc1 release. + + +Language Specification +---------------------- + +Kconfig originates in Linux Kernel. +See the file "Documentation/kbuild/kconfig*.txt" in your Linux Kernel +source directory for a basic specification of Kconfig. + + +Difference from Linux's Kconfig +------------------------------- + +The biggest difference between Linux Kernel and U-Boot in terms of the +configuration is that U-Boot has to configure multiple boot images per board: +Normal, SPL, TPL. +Kconfig functions need to be expanded for U-Boot to handle multiple images. +The files scripts/kconfig/* were imported from Linux Kernel and adjusted +for that purpose. + +See below for how each configuration target works in U-Boot: + +- config, nconfig, menuconfig, xconfig, gconfig + + These targets are used to configure Normal and create (or modify) the + .config file. For SPL configuration, the configutation targets are prefixed + with "spl/", for example "make spl/config", "make spl/menuconfig", etc. + Those targets create or modify the spl/.config file. Likewise, run + "make tpl/config", "make tpl/menuconfig", etc. for TPL. + +- silentoldconfig + + This target updates .config, include/generated/autoconf.h and + include/configs/*. In U-Boot, the same thing is done for SPL, TPL, + if supported by the target board. Depending on whether CONFIG_SPL and + CONFIG_TPL are defined, "make silentoldconfig" iterates three times at most + changing the work directory. + + To sum up, "make silentoldconfig" possibly updates: + - .config, include/generated/autoconf.h, include/config/* + - spl/.config, spl/include/generated/autoconf.h, spl/include/config/* + (in case CONFIG_SPL=y) + - tpl/.config, tpl/include/generated/autoconf.h, tpl/include/config/* + (in case CONFIG_TPL=y) + +- defconfig, _defconfig + + The target "_defconfig" is used to create the .config based on the + file configs/_defconfig. The "defconfig" target is the same + except it checks for a file specified with KBUILD_DEFCONFIG environment. + + Note: + The defconfig files are placed under the "configs" directory, + not "arch/$(ARCH)/configs". This is because "ARCH" is not necessarily + given from the command line for the U-Boot configuration and build. + + The defconfig file format in U-Boot has the special syntax; each line has + ":" prefix to show which image(s) the line is valid for. + For example, + + CONFIG_FOO=100 + S:CONFIG_FOO=200 + T:CONFIG_FOO=300 + ST:CONFIG_BAR=y + +S:CONFIG_BAZ=y + +T:CONFIG_QUX=y + +ST:CONFIG_QUUX=y + + Here, the ":" prefix is one of: + None - the line is valid only for Normal image + S: - the line is valid only for SPL image + T: - the line is valid only for TPL image + ST: - the line is valid for SPL and TPL images + +S: - the line is valid for Normal and SPL images + +T: - the line is valid for Normal and TPL images + +ST: - the line is valid for Normal, SPL and TPL images + + So, if neither CONFIG_SPL nor CONFIG_TPL is defined, the defconfig file + has no ":" part and therefore has the same form as in Linux. + From the example defconfig shown above, three separete configuration sets + are generated and used for creating .config, spl/.config and tpl/.config. + + - Input for the default configuration of Normal + CONFIG_FOO=100 + CONFIG_BAZ=y + CONFIG_QUX=y + CONFIG_QUUX=y + + - Input for the default configuration of SPL + CONFIG_FOO=200 + CONFIG_BAR=y + CONFIG_BAZ=y + CONFIG_QUUX=y + + - Input for the default configuration of TPL + CONFIG_FOO=300 + CONFIG_BAR=y + CONFIG_QUX=y + CONFIG_QUUX=y + +- savedefconfig + + This is the reverse operation of "make defconfig". If neither CONFIG_SPL + nor CONFIG_TPL is defined in the .config file, it works like "savedefconfig" + in Linux Kernel: creates the minimal set of config based on the .config + and saves it into the "defconfig" file. If CONFIG_SPL (and CONFIG_TPL) is + defined, the common lines among .config, spl/.config (and tpl/.config) are + coalesced together with "" prefix for each line as shown above. + This file can be used as an input of "defconfig" target. + +- _config + + This does not exist in Linux's Kconfig. + Prior to Kconfig, in U-Boot, "make _config" was used for the + configuration. It is still supported for backward compatibility and + its behavior is the same as "make _defconfig". + + +Migration steps to Kconfig +-------------------------- + +Prior to Kconfig, the C preprocessor based board configuration had been used +in U-Boot. + +Although Kconfig was introduced and some configs have been moved to Kconfig, +many of configs are still defined in C header files. It will take a very +long term to move all of them to Kconfig. In the interim, the two different +configuration infrastructures should coexist. +The configuration files are generated by both Kconfig and the old preprocessor +based configuration as follows: + +Configuration files for use in C sources + - include/generated/autoconf.h (generated by Kconfig for Normal) + - spl/include/generated/autoconf.h (generated by Kconfig for SPL) + - tpl/include/generated/autoconf.h (generated by Kconfig for TPL) + - include/configs/.h (exists for all boards) + +Configuration file for use in makefiles + - include/config/auto.conf (generated by Kconfig for Normal) + - spl/include/config/auto.conf (generated by Kconfig for SPL) + - tpl/include/config/auto.conf (generated by Kconfig for TPL) + - include/autoconf.mk (generated by the old config for Normal) + - spl/include/autoconfig.mk (generated by the old config for SPL) + - tpl/include/autoconfig.mk (generated by the old config for TPL) + +When adding a new CONFIG macro, it is highly recommended to add it to Kconfig +rather than to a header file. + + +Conversion from boards.cfg to Kconfig +------------------------------------- + +Prior to Kconfig, boards.cfg was a primary database that contained Arch, CPU, +SoC, etc. of all the supported boards. It was deleted when switching to +Kconfig. Each field of boards.cfg was converted as follows: + + Status -> "S:" entry of MAINTAINERS + Arch -> CONFIG_SYS_ARCH defined by Kconfig + CPU -> CONFIG_SYS_CPU defined by Kconfig + SoC -> CONFIG_SYS_SOC defined by Kconfig + Vendor -> CONFIG_SYS_VENDOR defined by Kconfig + Board -> CONFIG_SYS_BOARD defined by Kconfig + Target -> File name of defconfig (configs/_defconfig) + Options -> CONFIG_SYS_EXTRA_OPTIONS defined by Kconfig + Maintainers -> "M:" entry of MAINTAINERS + + +Tips to add/remove boards +------------------------- + +When adding a new board, the following steps are generally needed: + + [1] Add a header file include/configs/.h + [2] Make sure to define necessary CONFIG_SYS_* in Kconfig: + Define CONFIG_SYS_CPU="cpu" to compile arch//cpu/ + Define CONFIG_SYS_SOC="soc" to compile arch//cpu// + Define CONFIG_SYS_VENDOR="vendor" to compile board//common/* + and board///* + Define CONFIG_SYS_BOARD="board" to compile board//* + (or board///* if CONFIG_SYS_VENDOR is defined) + Define CONFIG_SYS_CONFIG_NAME="target" to include + include/configs/.h + [3] Add a new entry to the board select menu in Kconfig. + The board select menu is located in arch//Kconfig or + arch//*/Kconfig. + [4] Add a MAINTAINERS file + It is generally placed at board//MAINTAINERS or + board///MAINTAINERS + [5] Add configs/_defconfig + +When removing an obsolete board, the following steps are generally needed: + + [1] Remove configs/_defconfig + [2] Remove include/configs/.h if it is not used by any other boards + [3] Remove board///* or board//* if it is not used + by any other boards + [4] Update MAINTAINERS if necessary + [5] Remove the unused entry from the board select menu in Kconfig + [6] Add an entry to doc/README.scrapyard + + +TODO +---- + +- The option field of boards.cfg, which was used for the pre-Kconfig + configuration, moved to CONFIG_SYS_EXTRA_OPTIONS verbatim now. + Board maintainers are expected to implement proper Kconfig options + and switch over to them. Eventually CONFIG_SYS_EXTRA_OPTIONS will go away. + CONFIG_SYS_EXTRA_OPTIONS should not be used for new boards. + +- In the pre-Kconfig, a single board had multiple entries in the boards.cfg + file with differences in the option fields. The correspoing defconfig files + were auto-generated when switching to Kconfig. Now we have too many + defconfig files compared with the number of the supported boards. It is + recommended to have only one defconfig per board and allow users to select + the config options. + +- Move the config macros in header files to Kconfig. When we move at least + macros used in makefiles, we can drop include/autoconfig.mk, which makes + the build scripts much simpler. diff --git a/doc/README.kwbimage b/doc/README.kwbimage index e91c387b51..762b2e3acb 100644 --- a/doc/README.kwbimage +++ b/doc/README.kwbimage @@ -30,19 +30,19 @@ kwbimage support available with mkimage utility will generate kirkwood boot image that can be flashed on the board NAND/SPI flash. The make target which uses mkimage to produce such an image is "u-boot.kwb". For example: - export BUILD_DIR=/tmp/build + export KBUILD_OUTPUT=/tmp/build make distclean make yourboard_config - make $BUILD_DIR/u-boot.kwb + make u-boot.kwb Board specific configuration file specifications: ------------------------------------------------ 1. This file must present in the $(BOARDDIR). The default name is kwbimage.cfg. The name can be set as part of the full path - to the file using CONFIG_SYS_KWD_CONFIG (probably in - include/configs/.h). The path should look like: - $(SRCTREE)/$(CONFIG_BOARDDIR)/.cfg + to the file using CONFIG_SYS_KWD_CONFIG (probably in + include/configs/.h). The path should look like: + $(CONFIG_BOARDDIR)/.cfg 2. This file can have empty lines and lines starting with "#" as first character to put comments 3. This file can have configuration command lines as mentioned below, diff --git a/doc/README.malta b/doc/README.malta new file mode 100644 index 0000000000..c8db8a0c39 --- /dev/null +++ b/doc/README.malta @@ -0,0 +1,16 @@ +MIPS Malta board + +How to flash using a MIPS Navigator Probe: + + - Ensure that your Malta has jumper JP1 fitted. Without this jumper you will + be unable to flash your Malta using a Navigator Probe. + + - Connect Navigator Console to your probe and Malta as usual. + + - Within Navigator Console run the following commands: + + source /path/to/u-boot/board/imgtec/malta/flash-malta-boot.tcl + reset + flash-boot /path/to/u-boot/u-boot.bin + + - You should now be able to reboot your Malta to a U-boot shell. diff --git a/doc/README.mini2440 b/doc/README.mini2440 deleted file mode 100644 index 311ca52862..0000000000 --- a/doc/README.mini2440 +++ /dev/null @@ -1,28 +0,0 @@ -U-Boot for FriendlyARM Mini2440 (s3c2440) - -This file contains information for the port of U-Boot to FriendlyARM -mini2440 - -All information about the board can be found on : -http://www.friendlyarm.net/products/mini2440 - -To build u-boot : ./MAKEALL mini2440 - -Overview : --------- -FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440 -ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9 -systems. It's a low cost board. - -Boot Methods : ------------- -Mini2440 can boot from NOR or NAND. - -Build : ------ -./MAKEALL mini2440 - -or - -make mini2440_config -make diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot new file mode 100644 index 0000000000..d5043ccb66 --- /dev/null +++ b/doc/README.mpc85xx-sd-spi-boot @@ -0,0 +1,81 @@ +---------------------------------------- +Booting from On-Chip ROM (eSDHC or eSPI) +---------------------------------------- + +boot_format is a tool to write SD bootable images to a filesystem and build +SD/SPI images to a binary file for writing later. + +When booting from an SD card/MMC, boot_format puts the configuration file and +the RAM-based U-Boot image on the card. +When booting from an EEPROM, boot_format generates a binary image that is used +to boot from this EEPROM. + +Where to get boot_format: +======================== + +you can browse it online at: +http://git.freescale.com/git/cgit.cgi/ppc/sdk/boot-format.git/ + +Building +======== + +Run the following to build this project + + $ make + +Execution +========= + +boot_format runs under a regular Linux machine and requires a super user mode +to run. Execute boot_format as follows. + +For building SD images by writing directly to a file system on SD media: + + $ boot_format $config u-boot.bin -sd $device + +Where $config is the included config.dat file for your platform and $device +is the target block device for the SD media on your computer. + +For build binary images directly a local file: + + $ boot_format $config u-boot.bin -spi $file + +Where $file is the target file. Also keep in mind the u-boot.bin file needs +to be the u-boot built for your particular platform and target media. + +Example: To generate a u-boot.bin for a P1022DS booting from SD, run the +following in the u-boot repository: + + $ make P1022DS_SDCARD + +Configuration Files +=================== + +Below are the configuration files to be used with a particular platform. Keep +in mind that some of these config files are tied to the platforms DDR speed. +Please see the SoC reference manual for more documentation. + +P1022DS config_sram_p1022ds.dat +P2020DS config_sram_p2020ds.dat +P2010DS config_sram_p2020ds.dat +P1020RDB config_ddr2_1g_p1020rdb_533M.dat +P1020RDB config_ddr2_1g_p1020rdb_667M.dat +P2020RDB config_ddr2_1g_p2020rdb_800M.dat +P2020RDB config_ddr2_1g_p2020rdb_667M.dat +P2020RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat +P2010RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat +P1020RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1011RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1010RDB config_ddr3_1gb_p1010rdb_800M.dat +P1014RDB config_ddr3_1gb_p1014rdb_800M.dat +P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1012RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1022DS config_ddr3_2gb_p1022ds.dat +P1013DS config_ddr3_2gb_p1022ds.dat +P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat +P1013RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat +P1025RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat +P1016RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat +P1020UTM config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +P1020MBG config_ddr3_1gb_p1_p2_rdb_pc_800M.dat +MPC8536DS config_ddr2_512m_mpc8536ds_667M.dat diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab new file mode 100644 index 0000000000..43e64a2797 --- /dev/null +++ b/doc/README.mxc_hab @@ -0,0 +1,48 @@ +High Assurance Boot (HAB) for i.MX6 CPUs + +To authenticate U-Boot only by the CPU there is no code required in +U-Boot itself. However, the U-Boot image to be programmed into the +boot media needs to be properly constructed, i.e. it must contain a +proper Command Sequence File (CSF). + +The Initial Vector Table contains a pointer to the CSF. Please see +doc/README.imximage for how to prepare u-boot.imx. + +The CSF itself is being generated by Freescale HAB tools. + +mkimage will output additional information about "HAB Blocks" +which can be used in the Freescale tooling to authenticate U-Boot +(entries in the CSF file). + +Image Type: Freescale IMX Boot Image +Image Ver: 2 (i.MX53/6 compatible) +Data Size: 327680 Bytes = 320.00 kB = 0.31 MB +Load Address: 177ff420 +Entry Point: 17800000 +HAB Blocks: 177ff400 00000000 0004dc00 + ^^^^^^^^ ^^^^^^^^ ^^^^^^^^ + | | | + | | -------- (1) + | | + | ------------------- (2) + | + --------------------------- (3) + +(1) Size of area in file u-boot.imx to sign + This area should include the IVT, the Boot Data the DCD + and U-Boot itself. +(2) Start of area in u-boot.imx to sign +(3) Start of area in RAM to authenticate + +CONFIG_SECURE_BOOT currently enables only an additional command +'hab_status' in U-Boot to retrieve the HAB status and events. This +can be useful while developing and testing HAB. + +Commands to generate a signed U-Boot using Freescale HAB tools: +cst --o U-Boot_CSF.bin < U-Boot.CSF +objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0x00 \ + U-Boot_CSF.bin U-Boot_CSF_pad.bin +cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx + +NOTE: U-Boot_CSF.bin needs to be padded to the value specified in +the imximage.cfg file. diff --git a/doc/README.mxs b/doc/README.mxs index 5d9e72f958..ed2e568856 100644 --- a/doc/README.mxs +++ b/doc/README.mxs @@ -23,13 +23,30 @@ Contents 2) Compiling U-Boot for a MXS based board 3) Installation of U-Boot for a MXS based board to SD card 4) Installation of U-Boot into NAND flash on a MX28 based board +5) Installation of U-boot into SPI NOR flash on a MX28 based board 1) Prerequisites ---------------- -To make a MXS based board bootable, some tools are necessary. The first one is -the "elftosb" tool distributed by Freescale Semiconductor. The other one is the -"mxsboot" tool found in U-Boot source tree. +To make a MXS based board bootable, some tools are necessary. The only +mandatory tool is the "mxsboot" tool found in U-Boot source tree. The +tool is built automatically when compiling U-Boot for i.MX23 or i.MX28. + +The production of BootStream image is handled via "mkimage", which is +also part of the U-Boot source tree. The "mkimage" requires OpenSSL +development libraries to be installed. In case of Debian and derivates, +this is installed by running: + + $ sudo apt-get install libssl-dev + +NOTE: The "elftosb" tool distributed by Freescale Semiconductor is no + longer necessary for general use of U-Boot on i.MX23 and i.MX28. + The mkimage supports generation of BootStream images encrypted + with a zero key, which is the vast majority of use-cases. In + case you do need to produce image encrypted with non-zero key + or other special features, please use the "elftosb" tool, + otherwise continue to section 2). The installation procedure of + the "elftosb" is outlined below: Firstly, obtain the elftosb archive from the following location: @@ -107,6 +124,18 @@ The code produces "u-boot.sb" file. This file needs to be augmented with a proper header to allow successful boot from SD or NAND. Adding the header is discussed in the following chapters. +NOTE: The process that produces u-boot.sb uses the mkimage to generate the + BootStream. The BootStream is encrypted with zero key. In case you need + some special features of the BootStream and plan on using the "elftosb" + tool instead, the invocation to produce a compatible BootStream with the + one produced by mkimage is outlined below. For further details, refer to + the documentation bundled with the "elftosb" package. + + $ elftosb -zf imx23 -c arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd \ + -o u-boot.sb + $ elftosb -zf imx28 -c arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd \ + -o u-boot.sb + 3) Installation of U-Boot for a MXS based board to SD card ---------------------------------------------------------- @@ -234,3 +263,28 @@ There are two possibilities when preparing an image writable to NAND flash. In case the user needs to boot a firmware image bigger than 1Mb, the user has to adjust the "update_nand_firmware_maxsz" variable for the update scripts to work properly. + +5) Installation of U-Boot into SPI NOR flash on a MX28 based board +------------------------------------------------------------------ + +The u-boot.sb file can be directly written to SPI NOR from U-boot prompt. + +Load u-boot.sb into RAM, this can be done in several ways and one way is to use +tftp: + => tftp u-boot.sb 0x42000000 + +Probe the SPI NOR flash: + => sf probe + +(SPI NOR should be succesfully detected in this step) + +Erase the blocks where U-boot binary will be written to: + => sf erase 0x0 0x80000 + +Write u-boot.sb to SPI NOR: + => sf write 0x42000000 0 0x80000 + +Power off the board and set the boot mode DIP switches to boot from the SPI NOR +according to MX28 manual section 12.2.1 (Table 12-2) + +Last step is to power up the board and U-boot should start from SPI NOR. diff --git a/doc/README.mxsimage b/doc/README.mxsimage new file mode 100644 index 0000000000..c3975ee5e6 --- /dev/null +++ b/doc/README.mxsimage @@ -0,0 +1,170 @@ +Freescale i.MX233/i.MX28 SB image generator via mkimage +======================================================= + +This tool allows user to produce SB BootStream encrypted with a zero key. +Such a BootStream is then bootable on i.MX23/i.MX28. + +Usage -- producing image: +========================= +The mxsimage tool is targeted to be a simple replacement for the elftosb2 . +To generate an image, write an image configuration file and run: + + mkimage -A arm -O u-boot -T mxsimage -n \ + + +The output bootstream file is usually using the .sb file extension. Note +that the example configuration files for producing bootable BootStream with +the U-Boot bootloader can be found under arch/arm/boot/cpu/arm926ejs/mxs/ +directory. See the following files: + + mxsimage.mx23.cfg -- This is an example configuration for i.MX23 + mxsimage.mx28.cfg -- This is an example configuration for i.MX28 + +Each configuration file uses very simple instruction semantics and a few +additional rules have to be followed so that a useful image can be produced. +These semantics and rules will be outlined now. + +- Each line of the configuration file contains exactly one instruction. +- Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 . +- The configuration file is a concatenation of blocks called "sections" and + optionally "DCD blocks" (see below), and optional flags lines. + - Each "section" is started by the "SECTION" instruction. + - The "SECTION" instruction has the following semantics: + + SECTION u32_section_number [BOOTABLE] + - u32_section_number :: User-selected ID of the section + - BOOTABLE :: Sets the section as bootable + + - A bootable section is one from which the BootROM starts executing + subsequent instructions or code. Exactly one section must be selected + as bootable, usually the one containing the instructions and data to + load the bootloader. + + - A "SECTION" must be immediatelly followed by a "TAG" instruction. + - The "TAG" instruction has the following semantics: + + TAG [LAST] + - LAST :: Flag denoting the last section in the file + + - After a "TAG" unstruction, any of the following instructions may follow + in any order and any quantity: + + NOOP + - This instruction does nothing + + LOAD u32_address string_filename + - Instructs the BootROM to load file pointed by "string_filename" onto + address "u32_address". + + LOAD IVT u32_address u32_IVT_entry_point + - Crafts and loads IVT onto address "u32_address" with the entry point + of u32_IVT_entry_point. + - i.MX28-specific instruction! + + LOAD DCD u32_address u32_DCD_block_ID + - Loads the DCD block with ID "u32_DCD_block_ID" onto address + "u32_address" and executes the contents of this DCD block + - i.MX28-specific instruction! + + FILL u32_address u32_pattern u32_length + - Starts to write memory from addres "u32_address" with a pattern + specified by "u32_pattern". Writes exactly "u32_length" bytes of the + pattern. + + JUMP [HAB] u32_address [u32_r0_arg] + - Jumps onto memory address specified by "u32_address" by setting this + address in PT. The BootROM will pass the "u32_r0_arg" value in ARM + register "r0" to the executed code if this option is specified. + Otherwise, ARM register "r0" will default to value 0x00000000. The + optional "HAB" flag is i.MX28-specific flag turning on the HAB boot. + + CALL [HAB] u32_address [u32_r0_arg] + - See JUMP instruction above, as the operation is exactly the same with + one difference. The CALL instruction does allow returning into the + BootROM from the executed code. U-Boot makes use of this in it's SPL + code. + + MODE string_mode + - Restart the CPU and start booting from device specified by the + "string_mode" argument. The "string_mode" differs for each CPU + and can be: + i.MX23, string_mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH + JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1 + i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH + JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1 + + - An optional "DCD" blocks can be added at the begining of the configuration + file. Note that the DCD is only supported on i.MX28. + - The DCD blocks must be inserted before the first "section" in the + configuration file. + - The DCD block has the following semantics: + + DCD u32_DCD_block_ID + - u32_DCD_block_ID :: The ID number of the DCD block, must match + the ID number used by "LOAD DCD" instruction. + + - The DCD block must be followed by one of the following instructions. All + of the instructions operate either on 1, 2 or 4 bytes. This is selected by + the 'n' suffix of the instruction: + + WRITE.n u32_address u32_value + - Write the "u32_value" to the "u32_address" address. + + ORR.n u32_address u32_value + - Read the "u32_address", perform a bitwise-OR with the "u32_value" and + write the result back to "u32_address". + + ANDC.n u32_address u32_value + - Read the "u32_address", perform a bitwise-AND with the complement of + "u32_value" and write the result back to "u32_address". + + EQZ.n u32_address u32_count + - Read the "u32_address" at most "u32_count" times and test if the value + read is zero. If it is, break the loop earlier. + + NEZ.n u32_address u32_count + - Read the "u32_address" at most "u32_count" times and test if the value + read is non-zero. If it is, break the loop earlier. + + EQ.n u32_address u32_mask + - Read the "u32_address" in a loop and test if the result masked with + "u32_mask" equals the "u32_mask". If the values are equal, break the + reading loop. + + NEQ.n u32_address u32_mask + - Read the "u32_address" in a loop and test if the result masked with + "u32_mask" does not equal the "u32_mask". If the values are not equal, + break the reading loop. + + NOOP + - This instruction does nothing. + + - An optional flags lines can be one of the following: + + DISPLAYPROGRESS + - Enable boot progress output form the BootROM. + +- If the boot progress output from the BootROM is enabled, the BootROM will + produce a letter on the Debug UART for each instruction it started processing. + Here is a mapping between the above instructions and the BootROM output: + + H -- SB Image header loaded + T -- TAG instruction + N -- NOOP instruction + L -- LOAD instruction + F -- FILL instruction + J -- JUMP instruction + C -- CALL instruction + M -- MODE instruction + +Usage -- verifying image: +========================= + +The mxsimage can also verify and dump contents of an image. Use the following +syntax to verify and dump contents of an image: + + mkimage -l + +This will output all the information from the SB image header and all the +instructions contained in the SB image. It will also check if the various +checksums in the SB image are correct. diff --git a/doc/README.nand b/doc/README.nand index 913e9b50b8..dee0e00a61 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -89,6 +89,10 @@ Commands: Configuration Options: + CONFIG_SYS_NAND_U_BOOT_OFFS + NAND Offset from where SPL will read u-boot image. This is the starting + address of u-boot MTD partition in NAND. + CONFIG_CMD_NAND Enables NAND support and commmands. @@ -104,6 +108,16 @@ Configuration Options: CONFIG_SYS_MAX_NAND_DEVICE The maximum number of NAND devices you want to support. + CONFIG_SYS_NAND_MAX_ECCPOS + If specified, overrides the maximum number of ECC bytes + supported. Useful for reducing image size, especially with SPL. + This must be at least 48 if nand_base.c is used. + + CONFIG_SYS_NAND_MAX_OOBFREE + If specified, overrides the maximum number of free OOB regions + supported. Useful for reducing image size, especially with SPL. + This must be at least 2 if nand_base.c is used. + CONFIG_SYS_NAND_MAX_CHIPS The maximum number of NAND chips per device to be supported. @@ -169,6 +183,132 @@ Configuration Options: Please convert your driver even if you don't need the extra flexibility, so that one day we can eliminate the old mechanism. + + CONFIG_SYS_NAND_ONFI_DETECTION + Enables detection of ONFI compliant devices during probe. + And fetching device parameters flashed on device, by parsing + ONFI parameter page. + + CONFIG_BCH + Enables software based BCH ECC algorithm present in lib/bch.c + This is used by SoC platforms which do not have built-in ELM + hardware engine required for BCH ECC correction. + + CONFIG_SYS_NAND_BUSWIDTH_16BIT + Indicates that NAND device has 16-bit wide data-bus. In absence of this + config, bus-width of NAND device is assumed to be either 8-bit and later + determined by reading ONFI params. + Above config is useful when NAND device's bus-width information cannot + be determined from on-chip ONFI params, like in following scenarios: + - SPL boot does not support reading of ONFI parameters. This is done to + keep SPL code foot-print small. + - In current U-Boot flow using nand_init(), driver initialization + happens in board_nand_init() which is called before any device probe + (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are + not available while configuring controller. So a static CONFIG_NAND_xx + is needed to know the device's bus-width in advance. + Some drivers using above config are: + drivers/mtd/nand/mxc_nand.c + drivers/mtd/nand/ndfc.c + drivers/mtd/nand/omap_gpmc.c + + +Platform specific options +========================= + CONFIG_NAND_OMAP_GPMC + Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. + GPMC controller is used for parallel NAND flash devices, and can + do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 + and BCH16 ECC algorithms. + + CONFIG_NAND_OMAP_ELM + Enables omap_elm.c driver for OMAPx and AMxxxx platforms. + ELM controller is used for ECC error detection (not ECC calculation) + of BCH4, BCH8 and BCH16 ECC algorithms. + Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, + thus such SoC platforms need to depend on software library for ECC error + detection. However ECC calculation on such plaforms would still be + done by GPMC controller. + + CONFIG_SPL_NAND_AM33XX_BCH + Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based + hardware ECC correction. This is useful for platforms which have ELM + hardware engine and use NAND boot mode. + Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, + so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling + SPL-NAND driver with software ECC correction support. + + CONFIG_NAND_OMAP_ECCSCHEME + On OMAP platforms, this CONFIG specifies NAND ECC scheme. + It can take following values: + OMAP_ECC_HAM1_CODE_SW + 1-bit Hamming code using software lib. + (for legacy devices only) + OMAP_ECC_HAM1_CODE_HW + 1-bit Hamming code using GPMC hardware. + (for legacy devices only) + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW + 4-bit BCH code (unsupported) + OMAP_ECC_BCH4_CODE_HW + 4-bit BCH code (unsupported) + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + 8-bit BCH code with + - ecc calculation using GPMC hardware engine, + - error detection using software library. + - requires CONFIG_BCH to enable software BCH library + (For legacy device which do not have ELM h/w engine) + OMAP_ECC_BCH8_CODE_HW + 8-bit BCH code with + - ecc calculation using GPMC hardware engine, + - error detection using ELM hardware engine. + OMAP_ECC_BCH16_CODE_HW + 16-bit BCH code with + - ecc calculation using GPMC hardware engine, + - error detection using ELM hardware engine. + + How to select ECC scheme on OMAP and AMxx platforms ? + ----------------------------------------------------- + Though higher ECC schemes have more capability to detect and correct + bit-flips, but still selection of ECC scheme is dependent on following + - hardware engines present in SoC. + Some legacy OMAP SoC do not have ELM h/w engine thus such + SoC cannot support BCHx_HW ECC schemes. + - size of OOB/Spare region + With higher ECC schemes, more OOB/Spare area is required to + store ECC. So choice of ECC scheme is limited by NAND oobsize. + + In general following expression can help: + NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES + where + NAND_OOBSIZE = number of bytes available in + OOB/spare area per NAND page. + NAND_PAGESIZE = bytes in main-area of NAND page. + ECC_BYTES = number of ECC bytes generated to + protect 512 bytes of data, which is: + 3 for HAM1_xx ecc schemes + 7 for BCH4_xx ecc schemes + 14 for BCH8_xx ecc schemes + 26 for BCH16_xx ecc schemes + + example to check for BCH16 on 2K page NAND + NAND_PAGESIZE = 2048 + NAND_OOBSIZE = 64 + 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE + Thus BCH16 cannot be supported on 2K page NAND. + + However, for 4K pagesize NAND + NAND_PAGESIZE = 4096 + NAND_OOBSIZE = 64 + ECC_BYTES = 26 + 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE + Thus BCH16 can be supported on 4K page NAND. + + + CONFIG_NAND_OMAP_GPMC_PREFETCH + On OMAP platforms that use the GPMC controller + (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that + uses the prefetch mode to speed up read operations. + NOTE: ===== diff --git a/doc/README.nokia_rx51 b/doc/README.nokia_rx51 index a8fdfcd372..586ed7c1cc 100644 --- a/doc/README.nokia_rx51 +++ b/doc/README.nokia_rx51 @@ -62,7 +62,7 @@ Available additional commands/variables: * run trymmcscriptboot - Try to load and boot script ${mmcscriptfile} * run trymmckernboot - Try to load and boot kernel image ${mmckernfile} * run trymmckerninitrdboot - Try to load and boot kernel image ${mmckernfile} - with initrd image ${mmcinitrdfile} + with initrd image ${mmcinitrdfile} Additional variables for loading files from mmc: diff --git a/doc/README.odroid b/doc/README.odroid new file mode 100644 index 0000000000..8a004ca6ba --- /dev/null +++ b/doc/README.odroid @@ -0,0 +1,327 @@ + U-boot for Odroid X2/U3/XU3 +======================== + +1. Summary +========== +This is a quick instruction for setup Odroid boards. +Board config: odroid_config for X2/U3 +Board config: odroid-xu3_config for XU3 + +2. Supported devices +==================== +This U-BOOT config can be used on three boards: +- Odroid U3 +- Odroid X2 +with CPU Exynos 4412 rev 2.0 and 2GB of RAM +- Odroid XU3 +with CPU Exynos5422 and 2GB of RAM + +3. Boot sequence +================ +iROM->BL1->(BL2 + TrustZone)->U-BOOT + +This version of U-BOOT doesn't implement SPL. So, BL1, BL2, and TrustZone +binaries are needed to boot up. + +<< X2/U3 >> +It can be found in "boot.tar.gz" from here: +http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&value=boot.tar.gz +or here: +http://odroid.in/guides/ubuntu-lfs/boot.tar.gz + +<< XU3 >> +It can be downloaded from: +https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel + + +4. Boot media layout +==================== +The table below shows SD/eMMC cards layout for U-boot. +The block offset is starting from 0 and the block size is 512B. + ------------------------------------- +| Binary | Block offset| part type | +| name | SD | eMMC |(eMMC only)| + ------------------------------------- +| Bl1 | 1 | 0 | 1 (boot) | +| Bl2 | 31 | 30 | 1 (boot) | +| U-boot | 63 | 62 | 1 (boot) | +| Tzsw | 2111 | 2110 | 1 (boot) | +| Uboot Env | 2560 | 2560 | 0 (user) | + ------------------------------------- + +5. Prepare the SD boot card - with SD card reader +================================================= +To prepare bootable media you need boot binaries provided by hardkernel. +From the downloaded files, You can find: +- bl1.bin +- tzsw.bin +- bl2.bin +- sd_fusing.sh +- u-boot.bin +(The file names can be slightly different, but you can distinguish what they are +without problem) + +This is all you need to boot this board. But if you want to use your custom +u-boot then you need to change u-boot.bin with your own u-boot binary* +and run the script "sd_fusing.sh" - this script is valid only for SD card. + +*note: +The proper binary file of current U-boot is u-boot-dtb.bin. + +quick steps for Linux: +- Download all files from the link at point 3 and extract it if needed. +- put any SD card into the SD reader +- check the device with "dmesg" +- run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition) +Check if Hardkernel U-boot is booting, and next do the same with your U-boot. + +6. Prepare the eMMC boot card + with a eMMC card reader (boot from eMMC card slot) +===================================================== +To boot the device from the eMMC slot you should use a special card reader +which supports eMMC partition switch. All of the boot binaries are stored +on the eMMC boot partition which is normally hidden. + +The "sd_fusing.sh" script can be used after updating offsets of binaries +according to the table from point 4. Be sure that you are working on the right +eMMC partition - its size is usually very small, about 1-4 MiB. + +7. Prepare the eMMC boot card + with a SD card reader (boot from SD card slot) +================================================= +If you have an eMMC->microSD adapter you can prepare the card as in point 5. +But then the device can boot only from the SD card slot. + +8. Prepare the boot media using Hardkernel U-boot +================================================= +You can update the U-boot to the custom one if you have a working bootloader +delivered with the board on the eMMC/SD card. Then follow the steps: +- install the android fastboot tool +- connect a micro usb cable to the board +- on the U-boot prompt, run command: fastboot (as a root) +- on the host, run command: "fastboot flash bootloader u-boot-dtb.bin" +- the custom U-boot should start after the board resets. + +9. Partition layout +==================== +Default U-boot environment is setup for fixed partition layout. + +Partition table: MSDOS. Disk layout and files as listed in the table below. + ----- ------ ------ ------ -------- --------------------------------- +| Num | Name | FS | Size | Offset | Reguired files | +| | | Type | MiB | MiB | | + ----- ------ ------ ------ -------- --------------------------------- +| 1 | BOOT | fat | 100 | 2 | kernel, fdt** | +| 2 | ROOT | ext4 | - | | any Linux system | + ----- ------ ------ ------ -------- --------------------------------- + +**note: +Supported fdt files are: +- exynos4412-odroidx2.dtb +- exynos4412-odroidu3.dtb +- exynos5422-odroidxu3.dtb + +Supported kernel files are: +- Image.itb +- zImage +- uImage + +The default environmental variable "dfu_alt_info" is set* for above layout. +Each partition size is just an example, dfu_alt_info tries init two partitions. +The size of each is not important. + +*note: +$dfu_alt_info is set on a boot time and it is concatenated using two variables: +- $dfu_alt_boot(set dynamically) +- $dfu_alt_system(from current env). + +To add any changes to dfu_alt_info - please modify $dfu_alt_system only. +Changes are visible after board reset. + +10. The environment and booting the kernel +========================================== +There are three macros defined in config for various boot options: +Two for both, kernel with device tree support and also without it: +- boot_uimg - load uImage +- boot_zimg - load zImage +If proper fdt file exists then it will be automatically loaded, +so for old kernel types, please remove fdt file from boot partition. + +The third boot option for multi image support (more info: doc/uImage.FIT/) +- boot_fit - for binary file: "Image.itb" + +Default boot command: "autoboot" +And the boot sequence is: +- boot_fit - if "Image.itb" exists +- boot_zimg - if "zImage" exists +- boot_uimg - if "uImage" exists + +11. USB host support +==================== +NOTE: This section is only for Odroid X2/U3. + +The ethernet can be accessed after starting the USB subsystem in U-Boot. +The adapter does not come with a preconfigured MAC address, and hence it needs +to be set before starting USB. +setenv usbethaddr 02:DE:AD:BE:EF:FF + +Note that in this example a locally managed MAC address is chosen. Care should +be taken to make these MAC addresses unique within the same subnet. + +Start the USB subsystem: +Odroid # setenv usbethaddr 02:DE:AD:BE:EF:FF +Odroid # usb start +(Re)start USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 4 USB Device(s) found + scanning usb for storage devices... 1 Storage Device(s) found + scanning usb for ethernet devices... 1 Ethernet Device(s) found +Odroid # + +Automatic IP assignment: +------------------------ +If the ethernet is connected to a DHCP server (router maybe with DHCP enabled), +then the below will automatically assign an ip address through DHCP. +setenv autoload no +dhcp + +Odroid # setenv autoload no +Odroid # dhcp +Waiting for Ethernet connection... done. +BOOTP broadcast 1 +DHCP client bound to address 192.168.1.10 (524 ms) +Odroid # + +Note that this automatically sets the many IP address related variables in +U-Boot that is obtained from the DHCP server. + +Odroid # printenv ipaddr netmask gatewayip dnsip +ipaddr=192.168.1.10 +netmask=255.255.255.0 +gatewayip=192.168.1.1 +dnsip=192.168.1.1 + +Ping example: +The ping command can be used a test to check connectivity. In this example, +192.168.1.27 is a pingable server in the network. +Odroid # ping 192.168.1.27 +Waiting for Ethernet connection... done. +Using sms0 device +host 192.168.1.27 is alive +Odroid # + +Static IP assignment: +--------------------- +In the case where there are no DHCP servers in the network, or you want to +set the IP address statically, it can be done by: +Odroid # setenv ipaddr 192.168.1.10 +Odroid # ping 192.168.1.27 +Waiting for Ethernet connection... done. +Using sms0 device +host 192.168.1.27 is alive + +TFTP booting: +------------- +Say there exists a tftp server in the network with address 192.168.1.27 and +it serves a kernel image (zImage.3.17) and a DTB blob (exynos4412-odroidu3.dtb) +that needs to be loaded and booted. It can be accomplished as below: +(Assumes that you have setenv usbethaddr, and have not set autoload to no) + +Odroid # setenv serverip 192.168.1.27 +Odroid # tftpboot 0x40080000 zImage.3.17 +Waiting for Ethernet connection... done. +Using sms0 device +TFTP from server 192.168.1.27; our IP address is 192.168.1.10 +Filename 'zImage.3.17'. +Load address: 0x40080000 +Loading: ################################################################# + ################################################################# + ################################################################# + ####################### + 52.7 KiB/s +done +Bytes transferred = 3194200 (30bd58 hex) +Odroid # tftpboot 0x42000000 exynos4412-odroidu3.dtb +Waiting for Ethernet connection... done. +Using sms0 device +TFTP from server 192.168.1.27; our IP address is 192.168.1.10 +Filename 'exynos4412-odroidu3.dtb'. +Load address: 0x42000000 +Loading: #### + 40 KiB/s +done +Bytes transferred = 46935 (b757 hex) +Odroid # printenv bootargs +bootargs=Please use defined boot +Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/mmcblk0p2 rootwait +Odroid # bootz 40080000 - 42000000 +Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ] +## Flattened Device Tree blob at 42000000 + Booting using the fdt blob at 0x42000000 + Loading Device Tree to 4fff1000, end 4ffff756 ... OK + +Starting kernel ... + +[ 0.000000] Booting Linux on physical CPU 0xa00 +... etc ... + +In the above example you can substitute 'dhcp' for 'tftpboot' as well. + +USB Storage booting: +-------------------- +Similarly we can use the USB storage to load the kernel image/initrd/fdt etc +and boot. For this example, there is a USB drive plugged in. It has a FAT +1st partition and an EXT 2nd partition. Using the generic FS (ls/load) makes +it even easier to work with FAT/EXT file systems. +For this example the second EXT partition is used for booting and as rootfs. +The boot files - kernel and the dtb are present in the /boot directory of the +second partition. + +Odroid # usb start +(Re)start USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 4 USB Device(s) found + scanning usb for storage devices... 1 Storage Device(s) found + scanning usb for ethernet devices... +Error: sms0 address not set. <----- Note the error as usbethaddr +Warning: failed to set MAC address <----- is not set. +1 Ethernet Device(s) found +Odroid # usb part 0 + +Partition Map for USB device 0 -- Partition Type: DOS + +Part Start Sector Num Sectors UUID Type + 1 3072 263168 000c4046-01 06 + 2 266240 13457408 000c4046-02 83 + +Odroid # ls usb 0:2 /boot +

4096 . + 4096 .. + 353 boot.scr + 281 boot.txt + 101420 config-3.8.13.23 + 2127254 initrd.img-3.8.13.23 + 2194825 uInitrd + 2194825 uInitrd-3.8.13.23 + 2453112 zImage + 101448 config-3.8.13.26 + 2127670 uInitrd-3.8.13.26 + 2127606 initrd.img-3.8.13.26 + 3194200 zImage.3.17 <--- Kernel + 46935 exynos4412-odroidu3.dtb <--- DTB +Odroid # load usb 0:2 40080000 /boot/zImage.3.17 +3194200 bytes read in 471 ms (6.5 MiB/s) +Odroid # load usb 0:2 42000000 /boot/exynos4412-odroidu3.dtb +46935 bytes read in 233 ms (196.3 KiB/s) +Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/sda2 rootwait +Odroid # bootz 40080000 - 42000000 +Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ] +## Flattened Device Tree blob at 42000000 + Booting using the fdt blob at 0x42000000 + Loading Device Tree to 4fff1000, end 4ffff756 ... OK + +Starting kernel ... + +[ 0.000000] Booting Linux on physical CPU 0xa00 + +Please refer to README.usb for additional information. diff --git a/doc/README.omap3 b/doc/README.omap3 index 1fbe79db37..a62c357405 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -161,8 +161,7 @@ BCH8 To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH -to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted -syndrom generation to your board config. +and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW. The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8 implementation for OMAP3 works for you so the u-boot version should also. When you require the SPL to read with BCH8 there are two more configs to diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb deleted file mode 100644 index dee63d713a..0000000000 --- a/doc/README.p1010rdb +++ /dev/null @@ -1,199 +0,0 @@ -Overview -========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB board features are as follows: -Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5" 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port: via an ULPI PHY to micro-AB connector - - x1 USB2.0 poort via an internal PHY to micro-AB connector - - FlexCAN ports: - - x2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - J45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM - interface. SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to - POTS -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash -Note: 1 stands for 'on', 0 stands for 'off' - - -Setting of hwconfig -=================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn u-boot to NOR flash -================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -============================ -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef80000 +$filesize - => erase eef80000 +$filesize - => cp.b $loadaddr eef80000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn u-boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - - -Build and burn u-boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -Please contact your local field applications engineer or sales representative -to obtain related documents, such as P1010-RDB User Guide for details. diff --git a/doc/README.pblimage b/doc/README.pblimage index 2b9bb5c5f5..7fdd26b71b 100644 --- a/doc/README.pblimage +++ b/doc/README.pblimage @@ -14,20 +14,17 @@ Building PBL Boot Image and boot steps 1. Building PBL Boot Image. The default Image is u-boot.pbl. - For eSPI boot(available on P3041/P4080/P5020): + For eSPI boot(available on P2041/P3041/P4080/P5020/P5040/T4240): To build the eSPI boot image: - make _SPIFLASH_config - make u-boot.pbl + make _SPIFLASH - For SD boot(available on P3041/P4080/P5020): + For SD boot(available on P2041/P3041/P4080/P5020/P5040/T4240): To build the SD boot image: - make _SDCARD_config - make u-boot.pbl + make _SDCARD - For Nand boot(available on P3041/P5020): + For Nand boot(available on P2041/P3041/P5020/P5040): To build the NAND boot image: - make _NAND_config - make u-boot.pbl + make _NAND 2. pblimage support available with mkimage utility will generate Freescale PBL diff --git a/doc/README.power-framework b/doc/README.power-framework new file mode 100644 index 0000000000..1f6fd43203 --- /dev/null +++ b/doc/README.power-framework @@ -0,0 +1,166 @@ +# +# (C) Copyright 2014 Samsung Electronics +# Lukasz Majewski +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Introduction +------------ + +This document describes the second version of the u-boot's PMIC (Power +Management IC) framework. As a reference boards please consider Samsungs' Trats +and Trats2. + +Background +---------- + +Boards supported by u-boot are getting increasingly complex. Developers and +designers strive to cut down power consumption. Hence several different types of +devices are now available on the board - namely power managers (PMIC), fuel +gauges (FG), micro USB interface controllers (MUIC), batteries, multi-function +devices (MFD). + +Explanation of key design decisions +----------------------------------- + +One package can integrate PMIC and MUIC with different addresses on the I2C bus. +The same device - e.g. MAX8997 uses two different I2C busses and addresses. + +Power devices use not only I2C for communication, but SPI as well. Additionally +different ICs use different endianess. For this reason struct pmic holds +information about I2C/SPI transmission, which is used with generic +pmic_req_write() function. + +The "flat" hierarchy for power devices works well when each device performs only +one operation - e.g. PMIC enables LDO. + +The problem emerges when we have a device (battery) which conceptually shall be +the master and uses methods exported by other devices. We need to control MUIC +to start charging the battery, use PMIC to reduce board's overall power +consumption (by disabling not needed LDOs, BUCKs) and get current state of +energy on the battery from FG. +Up till now u-boot doesn't support device model, so a simple one had to be +added. + +The directory hierarchy has following structure: +./include/power/_.h +e.g. ./include/power/max8997_pmic.h + +./drivers/power/pmic/power_{core files}.c +e.g. ./drivers/power/pmic/power_core.c + +./drivers/power/pmic//_.c +e.g. ./drivers/power/pmic/pmic_max8997.c +e.g. ./drivers/power/battery/trats/bat_trats.c +e.g. ./drivers/power/fuel_gauge/fg_max17042.c + +The framework classifies devices by their function - separate directories should +be maintained for different classes of devices. + +Current design +-------------- + +Everything is a power device described by struct pmic. Even battery is +considered as a valid power device. This helps for better management of those +devices. + +- Block diagram of the hierarchy: + ----------------- + --------| BAT |------------ + | | | | + | ----------------- | + | | | + \|/ \|/ \|/ + ----------- ----------------- --------- + |FG | |MUIC | |CHRG | + | | | | | | + ----------- ----------------- --------- + + +1. When hierarchy is not needed (no complex battery charge): + +Definition of the struct pmic is only required with proper name and parameters +for communication. This is enough to use the "pmic" command in the u-boot +prompt to change values of device's register (enable/disable LDO, BUCK). + +The PG, MUIC and CHRG above are regarded to be in the same level in the +hierarchy. + +2. Complex battery charging. + +To charge a battery, information from several "abstract" power devices is +needed (defined at ./include/power/pmic.h): +- FG device (struct power_fg): + -- *fg_battery_check - check if battery is not above its limits + -- *fg_battery_update - update the pmic framework with current + battery state(voltage and current capacity) + +- Charger device (struct power_chrq): + -- *chrg_type - type/capacity of the charger (including information + about USB cable disconnection) + -- *chrg_bat_present - detection if battery to be charged is + present + -- *chrg_state - status of the charger - if it is enabled or + disabled + +- Battery device (struct power_battery): + -- *battery_init - assign proper callbacks to be used by top + hierarchy battery device + -- *battery_charge - called from "pmic" command, responsible + for performing the charging + +Now two batteries are supported; trats and trats2 [*]. Those differ in the way +how they handle the exact charging. Trats uses polling (MAX8997) and trats2 +relies on the PMIC/MUIC HW completely (MAX77693). + +__Example for trats (this can be very different for other board):__ + -- *fg_battery_check -> FG device (fg_max17042.c) + -- *fg_battery_update -> FG device (fg_max17042.c) + -- *chrg_type -> MUIC device (muic_max8997.c) + -- *chrg_bat_present -> PMIC device (pmic_max8997.c) + -- *chrg_state -> PMIC device (pmic_max8997.c) + -- *battery_init -> BAT device (bat_trats.c) + -- *battery_charge -> BAT device (bat_trats.c) + +Also the struct pmic holds method (*low_power_mode) for reducing board's +power consumption when one calls "pmic BAT_TRATS bat charge" command. + +How to add a new power device +----------------------------- + +1. Simple device should be added with creation of file +_.c, _.h according to the +proposed and described above scheme. + +Then "pmic" command supports reading/writing/dump of device's internal +registers. + +2. Charging battery with hierarchy +Define devices as listed at 1. + +Define battery file (bat_.c). Please also note that one might need a +corresponding battery model description for FG. + +For points 1 and 2 use a generic function power_init_board() to initialise the +power framework on your board. + +For reference, please look into the trats/trats2 boards. + +TO DO list (for PMICv3) - up till v2014.04 +------------------------------------------ + +1. Description of the devices related to power via device tree is not available. +This is the main problem when a developer tries to build a multi-boot u-boot +binary. The best would be to parse the DTS from Linux kernel. + +2. To support many instances of the same IC, like two MAX8997, one needs to +copy the corresponding pmic_max8997.c file with changed name to "MAX8997_PMICX", +where X is the device number. This problem will be addressed when extended +pmic_core.c will support storing available devices in a list. + +3. Definition of batteries [*] (for trats/trats2) should be excluded from the +code responsible for charging them and since it in fact describes the charging +profile it should be put to a separate file. + +4. Adjust the framework to work with the device model. diff --git a/doc/README.qemu-mips b/doc/README.qemu-mips index 1fdfbab677..a192752f4d 100644 --- a/doc/README.qemu-mips +++ b/doc/README.qemu-mips @@ -15,7 +15,6 @@ recent qemu versions. When using emulated flash, launch with -pflash and erase mips_bios.bin. - Notes for the Qemu MIPS port ---------------------------- diff --git a/doc/README.ramboot-ppc85xx b/doc/README.ramboot-ppc85xx index 8ed45fb46d..5cc546a36f 100644 --- a/doc/README.ramboot-ppc85xx +++ b/doc/README.ramboot-ppc85xx @@ -23,11 +23,11 @@ methods could be handy. the board.And then execute the bootloader from DDR. Some usecases where this may be used: - While developing some new feature of u-boot, for example USB driver or - SPI driver. - Suppose the board already has a working bootloader on it. And you would - prefer to keep it intact, at the same time want to test your bootloader. - In this case you can get your test bootloader binary into DDR via tftp - for example. Then execute the test bootloader. + SPI driver. + Suppose the board already has a working bootloader on it. And you would + prefer to keep it intact, at the same time want to test your bootloader. + In this case you can get your test bootloader binary into DDR via tftp + for example. Then execute the test bootloader. - Suppose a platform already has a propreitery bootloader which does not support for example AMP boot. In this case also RAM boot loader can be utilized. diff --git a/doc/README.rmobile b/doc/README.rmobile index 7ec63f13ce..4fbbcb3ef7 100644 --- a/doc/README.rmobile +++ b/doc/README.rmobile @@ -2,13 +2,15 @@ Summary ======= This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1] -family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9. +and R-Car[2]family of SoCs. Renesas's RMOBILE/R-Car SoC family contains an ARM +Cortex-A9. Currently the following boards are supported: -* KMC KZM-A9-GT [2] - -* Atmark-Techno Armadillo-800-EVA [3] +* KMC KZM-A9-GT [3] +* Atmark-Techno Armadillo-800-EVA [4] +* Renesas Electronics Lager +* Renesas Electronics Koelsch Toolchain ========= @@ -17,7 +19,7 @@ ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a). But currently we compile with -march=armv5 to allow more compilers to work. (For U-Boot code this has no performance impact.) Because there was no compiler which is supporting armv7a not much before. -Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a +Currently, ELDK[5], Linaro[6], CodeSourcey[7] and Emdebian[8] supports -march=armv7a and you can get. Build @@ -25,13 +27,26 @@ Build * KZM-A9-GT -make kzm9g_config -make + make kzm9g_config + make * Armadillo-800-EVA -make armadillo-800eva_config -make + make armadillo-800eva_config + make + + Note: Armadillo-800-EVA's U-Boot supports booting from SDcard only. + Please see "B.2 Appendix B Boot Specifications" in hardware manual. + +* Lager + + make lager_config + make + +* Koelsch + + make koelsch_config + make Links ===== @@ -40,26 +55,30 @@ Links http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp -[2] KZM-A9-GT +[2] Renesas R-Car: + +http://am.renesas.com/products/soc/assp/automotive/index.jsp + +[3] KZM-A9-GT http://www.kmckk.co.jp/kzma9-gt/index.html -[3] Armadillo-800-EVA +[4] Armadillo-800-EVA http://armadillo.atmark-techno.com/armadillo-800-EVA -[4] ELDK +[5] ELDK http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6. -[5] Linaro +[6] Linaro http://www.linaro.org/downloads/ -[6] CodeSourcey +[7] CodeSourcey http://www.mentor.com/embedded-software/codesourcery -[7] Emdebian +[8] Emdebian http://www.emdebian.org/crosstools.html diff --git a/doc/README.scrapyard b/doc/README.scrapyard index a0f1fa30f8..952ab871c2 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -5,34 +5,216 @@ by unnoticed, but often build errors will result. If nobody cares any more to resolve such problems, then the code is really dead and will be removed from the U-Boot source tree. The remainders rest in piece in the imperishable depths of the git history. This document tries to -maintain a list of such former fellows, so archeologists can check -easily if here is something they might want to dig for... +maintain a list of such former fellows, so archaeologists can check +easily if there is something they might want to dig for... +The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -Alaska8220 powerpc mpc8220 - - -Yukon8220 powerpc mpc8220 - - -sorcery powerpc mpc8220 - - -smdk6400 arm arm1176 52587f1 2013-04-12 Zhong Hongbo -ns9750dev arm arm926ejs 4cfc611 2013-02-28 Markus Pietrek +icecube_5200 powerpc mpc5xxx - - Wolfgang Denk +Lite5200 powerpc mpc5xxx - - +cpci5200 powerpc mpc5xxx - - Reinhard Arlt +mecp5200 powerpc mpc5xxx - - Reinhard Arlt +pf5200 powerpc mpc5xxx - - Reinhard Arlt +PM520 powerpc mpc5xxx - - Josef Wagner +Total5200 powerpc mpc5xxx - - +CATcenter powerpc ppc4xx - - +PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson +P2020DS powerpc mpc85xx - - +P2020COME powerpc mpc85xx - - Ira W. Snyder +P2020RDB powerpc mpc85xx - - Poonam Aggrwal +P2010RDB powerpc mpc85xx - - +P1020RDB powerpc mpc85xx - - +P1011RDB powerpc mpc85xx - - +MPC8360EMDS powerpc mpc83xx - - Dave Liu +MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov +P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk +ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu +ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16 +ELPPC powerpc 74xx_7xx d928664f 2015-01-16 +mpc7448hpc2 powerpc 74xx_7xx d928664f 2015-01-16 Roy Zang +CPCI405 ppc4xx 405gp 5f1459dc 2015-01-13 Matthias Fuchs +CPCI405DT ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs +CPCI405AB ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs +G2000 ppc4xx 405ep 5f8f6294 2015-01-13 Matthias Fuchs +WUH405 ppc4xx 405ep fc88a5bf 2015-01-13 Matthias Fuchs +VOH405 ppc4xx 405ep 807db88b 2015-01-13 Matthias Fuchs +PMC405 ppc4xx 405gp d5263304 2015-01-13 Matthias Fuchs +PCI405 ppc4xx 405gp dbe7bb0d 2015-01-13 Matthias Fuchs +OCRTC ppc4xx 405gpr cc6e715f 2015-01-13 Matthias Fuchs +HUB405 ppc4xx 405ep e434d5d7 2015-01-13 Matthias Fuchs +HH405 ppc4xx 405ep 843125da 2015-01-13 Matthias Fuchs +DU440 ppc4xx 440epx 7ac9d47a 2015-01-13 Matthias Fuchs +DU405 ppc4xx 405gpr bc114076 2015-01-13 Matthias Fuchs +DP405 ppc4xx 405ep 9a4018e0 2015-01-13 Matthias Fuchs +CPCIISER4 ppc4xx 405gp 37057260 2015-01-13 Matthias Fuchs +CMS700 ppc4xx 405ep 2404124c 2015-01-13 Matthias Fuchs +ASH405 ppc4xx 405ep b5e7c84f 2015-01-13 Matthias Fuchs +AR405 ppc4xx 405gpr 61b57c4a 2015-01-13 Matthias Fuchs +APC405 ppc4xx 405gpr 2b8a04e5 2015-01-13 Matthias Fuchs +TASREG m68k mcf52x2 cbdc662a 2015-01-13 Matthias Fuchs +A3000 powerpc mpc824x d622ac39 2015-01-05 +CPC45 powerpc mpc824x d622ac39 2015-01-05 Josef Wagner +CU824 powerpc mpc824x d622ac39 2015-01-05 Wolfgang Denk +eXalion powerpc mpc824x d622ac39 2015-01-05 Torsten Demke +MVBLUE powerpc mpc824x d622ac39 2015-01-05 +MUSENKI powerpc mpc824x d622ac39 2015-01-05 Jim Thompson +Sandpoint8240 powerpc mpc824x d622ac39 2015-01-05 Wolfgang Denk +Sandpoint8245 powerpc mpc824x d622ac39 2015-01-05 Jim Thompson +utx8245 powerpc mpc824x d622ac39 2015-01-05 Greg Allen +atc powerpc mpc8260 9067b300 2015-01-05 Wolfgang Denk +CPU86 powerpc mpc8260 f7e1af86 2015-01-05 Wolfgang Denk +CPU87 powerpc mpc8260 f7e1af86 2015-01-05 +ep82xxm powerpc mpc8260 e2b19629 2015-01-05 +gw8260 powerpc mpc8260 8eecbaf3 2015-01-05 Oliver Brown +IPHASE4539 powerpc mpc8260 87882f57 2015-01-05 Wolfgang Grandegger +muas3001 powerpc mpc8260 d2fd1d66 2015-01-05 Heiko Schocher +PM825 powerpc mpc8260 dc0b2fb4 2015-01-05 Wolfgang Denk +PM826 powerpc mpc8260 dc0b2fb4 2015-01-05 Wolfgang Denk +PM828 powerpc mpc8260 dc0b2fb4 2015-01-05 +MPC8266ADS powerpc mpc8260 b3a2bbe1 2015-01-05 Rune Torgersen +VoVPN-GW powerpc mpc8260 cc90905f 2015-01-05 +ep8260 powerpc mpc8260 4ad015ba 2015-01-05 Frank Panno +ppmc8260 powerpc mpc8260 793116d2 2015-01-05 Brad Kemp +sacsng powerpc mpc8260 b35c0ad6 2015-01-05 Jerry Van Baren +cogent_mpc8260 powerpc mpc8260 d19f6a60 2015-01-05 Murray Jensen +cogent_8xx powerpc mpc8xx d19f6a60 2015-01-05 Murray Jensen +ESTEEM192E powerpc mpc8xx af0e3514 2015-01-05 Conn Clark +IP860 powerpc mpc8xx 5ec71100 2015-01-05 Wolfgang Denk +IVML24 powerpc mpc8xx ca620cd1 2015-01-05 Wolfgang Denk +IVMS8 powerpc mpc8xx ca620cd1 2015-01-05 Wolfgang Denk +lwmon powerpc mpc8xx acc2372d 2015-01-05 Wolfgang Denk +NETVIA powerpc mpc8xx f017cd7f 2015-01-05 Pantelis Antoniou +R360MPI powerpc mpc8xx 79cbecb8 2015-01-05 Wolfgang Denk +RRvision powerpc mpc8xx 8737fc75 2015-01-05 Wolfgang Denk +SPD823TS powerpc mpc8xx 72ba368f 2015-01-05 Wolfgang Denk +KUP4K powerpc mpc8xx 4317d070 2015-01-05 Klaus Heydeck +KUP4X powerpc mpc8xx 4317d070 2015-01-05 Klaus Heydeck +ELPT860 powerpc mpc8xx 3c5b20f1 2015-01-05 The LEOX team +hmi1001 powerpc mpc5xxx ceaf499b 2015-01-05 +mucmc52 powerpc mpc5xxx ceaf499b 2015-01-05 Heiko Schocher +uc101 powerpc mpc5xxx ceaf499b 2015-01-05 Heiko Schocher +uc100 powerpc mpc8xx ceaf499b 2015-01-05 Stefan Roese +FPS850L powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk +FPS860L powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk +NSCU powerpc mpc8xx 5d2a5ef7 2015-01-05 +SM850 powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk +TK885D powerpc mpc8xx 5d2a5ef7 2015-01-05 +virtlab2 powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk +hermes powerpc mpc8xx 36da51e 2014-12-08 Wolfgang Denk +PRS200 powerpc mpc5200 ecfdcee 2014-11-12 +MCC200 powerpc mpc5200 ecfdcee 2014-11-12 +TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer +TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer +TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer +TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk +TQM8260 powerpc mpc8260 ccc1950 2014-10-27 Wolfgang Denk +IDS8247 powerpc mpc8260 6afb357 2014-10-27 Heiko Schocher +HWW1U1A powerpc mpc85xx 4109cb0 2014-10-27 Kyle Moffett +hymod powerpc mpc8260 5038d7f 2014-10-27 Murray Jensen +MHPC powerpc mpc8xx 1655f9f 2014-10-27 Frank Gottschling +ICU862 powerpc mpc8xx 4af5f0f 2014-10-27 Wolfgang Denk +CPCI750 powerpc 74xx_7xx 03b0040 2014-10-27 Reinhard Arlt +DB64360 powerpc 74xx_7xx 03b0040 2014-10-27 +DB64460 powerpc 74xx_7xx 03b0040 2014-10-27 +p3m750 powerpc 74xx_7xx 03b0040 2014-10-27 Stefan Roese +p3m7448 powerpc 74xx_7xx 03b0040 2014-10-27 Stefan Roese +MVBC_P powerpc mpc5xxx af55e35 2014-10-10 Andre Schwarz +MVSMR powerpc mpc5xxx af55e35 2014-10-10 Andre Schwarz +MERGERBOX powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz +MVBLM7 powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz +bluestone powerpc ppc4xx 9ed3246 2014-10-10 Tirumala Marri +CRAYL1 powerpc ppc4xx 1521cdc 2014-10-10 David Updegraff +KAREF powerpc ppc4xx dc9617e 2014-10-10 Travis Sawyer +METROBOX powerpc ppc4xx dc9617e 2014-10-10 Travis Sawyer +PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt +PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt +flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári Davíðsson +gen860t powerpc mpc8xx 6bde1ec1 2014-08-22 Keith Outwater +sixnet powerpc mpc8xx 4723ce49 2014-08-22 Dave Ellis +svm_sc8xx powerpc mpc8xx d1a4aafd 2014-08-22 John Zhan +stxxtc powerpc mpc8xx 0ace4d9d 2014-08-22 Dan Malek +omap5912osk arm arm926ejs 62d636aa 2014-08-22 Rishi Bhattacharya +p1023rds powerpc mpc85xx d0bc5140 2014-07-22 Roy Zang +spc1920 powerpc mpc8xx 98ad54be 2014-07-07 +v37 powerpc mpc8xx b8c1438a 2014-07-07 +fads powerpc mpc8xx 03f9d7d1 2014-07-07 +netphone powerpc mpc8xx c51c1c9a 2014-07-07 +netta2 powerpc mpc8xx c51c1c9a 2014-07-07 +netta powerpc mpc8xx c51c1c9a 2014-07-07 +rbc823 powerpc mpc8xx c750b9c0 2014-07-07 +quantum powerpc mpc8xx 0657e46e 2014-07-07 +RPXlite_dw powerpc mpc8xx 0657e46e 2014-07-07 +qs850 powerpc mpc8xx dab0f762 2014-07-07 +qs860t powerpc mpc8xx dab0f762 2014-07-07 +simpc8313 powerpc mpc83xx 7445207f 2014-06-05 Ron Madrid +hidden_dragon powerpc mpc824x 3fe1a854 2014-05-30 Yusdi Santoso +debris powerpc mpc824x 7edb1f7b 2014-05-30 Sangmoon Kim +kvme080 powerpc mpc824x 2868f862 2014-05-30 Sangmoon Kim +ep8248 powerpc mpc8260 49ad566d 2014-05-30 Yuli Barcohen +ispan powerpc mpc8260 80bae39a 2014-05-30 Yuli Barcohen +rattler powerpc mpc8260 d0664db4 2014-05-30 Yuli Barcohen +zpc1900 powerpc mpc8260 6f80bb48 2014-05-30 Yuli Barcohen +mpc8260ads powerpc mpc8260 facb6725 2014-05-30 Yuli Barcohen +adder powerpc mpc8xx 373a9788 2014-05-30 Yuli Barcohen +quad100hd powerpc ppc405ep 3569571d 2014-05-30 Gary Jennejohn +incaip mips mips32 538cf92c 2014-04-20 Wolfgang Denk +lubbock arm pxa 36bf57b 2014-04-18 Kyle Harris +EVB64260 powerpc mpc824x bb3aef9 2014-04-18 +MOUSSE powerpc mpc824x 03f2ecc 2014-04-18 +rsdproto powerpc mpc8260 8b043e6 2014-04-18 +RPXsuper powerpc mpc8260 0ebf5f5 2014-04-18 +RPXClassic powerpc mpc8xx 4fb3925 2014-04-18 +RPXlite powerpc mpc8xx 4fb3925 2014-04-18 +FADS powerpc mpc8xx aa6e1e4 2014-04-18 +genietv powerpc mpc8xx b8a49bd 2014-04-18 +mbx8xx powerpc mpc8xx d6b11fd 2014-04-18 +nx823 powerpc mpc8xx a146e8b 2014-04-18 +idmr m68k mcf52x2 ba650e9b 2014-01-28 +M5271EVB m68k mcf52x2 ba650e9b 2014-01-28 +dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen +actux4 arm ixp 6ff7aafa 2014-01-28 Michael Schwingen +actux3 arm ixp 38da33f3 2014-01-28 Michael Schwingen +actux2 arm ixp 13e0ee7f 2014-01-28 Michael Schwingen +actux1 arm ixp 373ee048 2014-01-28 Michael Schwingen +mx1ads arm arm920t e570aca9 2014-01-13 +mini2440 arm arm920t af5b9b1f 2014-01-13 Gabriel Huau +omap730p2 arm arm926ejs 79c5c08d 2013-11-11 +pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger +pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese +scpu arm ixp 304db0b 2013-09-24 Stefan Roese +omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta +CANBT powerpc 405CR fb8f4fd 2013-08-07 Matthias Fuchs +omap2420h4 arm omap24xx 7f5eef9 2013-06-04 Richard Woodruff +Alaska8220 powerpc mpc8220 d6ed322 2013-05-11 +Yukon8220 powerpc mpc8220 d6ed322 2013-05-11 +sorcery powerpc mpc8220 d6ed322 2013-05-11 +smdk6400 arm arm1176 52587f1 2013-04-12 Zhong Hongbo +ns9750dev arm arm926ejs 4cfc611 2013-02-28 Markus Pietrek +eNET x86 x86 7e8c53d 2013-02-14 Graeme Russ +PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk +PCIPPC6 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk AMX860 powerpc mpc860 1b0757e 2012-10-28 Wolfgang Denk c2mon powerpc mpc855 1b0757e 2012-10-28 Wolfgang Denk +EP88x powerpc mpc885 1b0757e 2012-10-28 ETX094 powerpc mpc850 1b0757e 2012-10-28 Wolfgang Denk IAD210 powerpc mpc860 1b0757e 2012-10-28 - LANTEC powerpc mpc850 1b0757e 2012-10-28 Wolfgang Denk SCM powerpc mpc8260 1b0757e 2012-10-28 Wolfgang Grandegger SX1 arm arm925t 53c4154 2012-10-26 TQM85xx powerpc MPC85xx d923a5d 2012-10-04 Stefan Roese +ADCIOP powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuchs +DASA_SIM powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuchs apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park tb0229 mips mips32 3f3110d 2011-12-12 rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk OXC powerpc MPC8240 309a292 2011-12-07 BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling -xm250 arm pxa c746cdd 2011-25-11 -pleb2 arm pxa b185a1c 2011-25-11 -cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris -cerf250 arm pxa a3f1241 2011-25-11 Prakash Kumar +xm250 arm pxa c477d72 2011-11-25 +pleb2 arm pxa d299173 2011-11-25 +cradle arm pxa 00c4aca 2011-11-25 Kyle Harris +cerf250 arm pxa f13eba6 2011-11-25 Prakash Kumar mpq101 powerpc mpc85xx e877fab 2011-10-23 Alex Dubov ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese ixdp425 arm ixp 0ca8eb7 2011-09-22 Kyle Harris @@ -71,13 +253,13 @@ B2 arm s3c44b0 5dcf536 2011-07-16 Andrea Scian armadillo arm arm720t be28857 2011-07-16 Rowel Atienza assabet arm sa1100 c91e90d 2011-07-16 George G. Davis trab arm S3C2400 566e5cf 2011-05-01 Gary Jennejohn -xsengine ARM PXA2xx 4262a7c 2010-10-20 -wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli -delta ARM PXA2xx 75e2035 2010-10-20 mp2usb ARM AT91RM2900 ee986e2 2011-01-25 Eric Bénard barco powerpc MPC8245 afaa27b 2010-11-23 Marc Leeman ERIC powerpc 405GP d9ba451 2010-11-21 Swen Anderson VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent +xsengine ARM PXA2xx 4262a7c 2010-10-20 +wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli +delta ARM PXA2xx 75e2035 2010-10-20 NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl @@ -94,6 +276,3 @@ MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwar adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi R5200 ColdFire - 48ead7a 2008-03-31 Zachary P. Landau CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs -PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk -PCIPPC6 powerpc MPC740/MPC750 - - Wolfgang Denk -omap2420h4 arm omap24xx - 2013-06-04 Richard Woodruff diff --git a/doc/README.semihosting b/doc/README.semihosting new file mode 100644 index 0000000000..7248560780 --- /dev/null +++ b/doc/README.semihosting @@ -0,0 +1,54 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Semihosting is ARM's way of having a real or virtual target communicate +with a host or host debugger for basic operations such as file I/O, +console I/O, etc. Please see +http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjjgij.html for more information. + +For developing on armv8 virtual fastmodel platforms, semihosting is a +valuable tool since it allows access to image/configuration files before +eMMC or other NV media are available. + +There are two main ARM virtual Fixed Virtual Platform (FVP) models, +Versatile Express (VE) FVP and BASE FVP (See +http://www.arm.com/products/tools/models/fast-models/foundation-model.php) +The initial vexpress64 u-boot board created here runs on the VE virtual +platform using the license-free Foundation_v8 simulator. Fortunately, +the Foundation_v8 simulator also supports the BASE_FVP model which +companies can purchase licenses for and contain much more functionality. +So we can, in u-boot, run either model by either using the VE FVP (default), +or turning on CONFIG_BASE_FVP for the more full featured model. + +Rather than create a new armv8 board similar to armltd/vexpress64, add +semihosting calls to the existing one, enabled with CONFIG_SEMIHOSTING +and CONFIG_BASE_FVP both set. Also reuse the existing board config file +vexpress_aemv8a.h but differentiate the two models by the presence or +absence of CONFIG_BASE_FVP. This change is tested and works on both the +Foundation and Base fastmodel simulators. + +The level of semihosting support is minimal, restricted to just what it +takes to load images to memory. If more semihosting functionality is +required, such as file seek, outputting strings, reading characters, etc, +then it can be easily added later. + +We require that the board include file define these env variables: +- kernel_name e.g. "uImage" +- kernel_addr_r e.g. "0x80000000" +- initrd_name e.g. "ramdisk.img" +- initrd_addr_r e.g. "0x88000000" +- fdt_name e.g. "devtree.dtb" +- fdt_addr_r e.g. "0x83000000" + +Optionally, "fdt_high" and "initrd_high" can be specified as per +their rules for allowing or preventing copying of these images. + +For the "fdt chosen" startup macro, this code will then define: +- initrd_end (based on retrieving initrd_addr_r plus actual initrd_size) + +We will then load the kernel, initrd, and fdt into the specified +locations in memory in a similar way that the ATF fastmodel code +uses semihosting calls to load other boot stages and u-boot itself. diff --git a/doc/README.sh7753evb b/doc/README.sh7753evb new file mode 100644 index 0000000000..5fe178c53f --- /dev/null +++ b/doc/README.sh7753evb @@ -0,0 +1,67 @@ +======================================== +Renesas SH7753 EVB board +======================================== + +This board specification: +========================= + +The SH7753 EVB (board config name:sh7753evb) has the following device: + + - SH7753 (SH-4A) + - DDR3-SDRAM 512MB + - SPI ROM 8MB + - Gigabit Ethernet controllers + - eMMC 4GB + + +Configuration for This board: +============================= + +You can select the configuration as follows: + + - make sh7753evb_config + + +This board specific command: +============================ + +This board has the following its specific command: + + - write_mac + + +1. write_mac + +You can write MAC address to SPI ROM. + + Usage 1) Write MAC address + + write_mac [GETHERC ch0] [GETHERC ch1] + + For example) + => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f + *) We have to input the command as a single line + (without carriage return) + *) We have to reset after input the command. + + Usage 2) Show current data + + write_mac + + For example) + => write_mac + GETHERC ch0 = 74:90:50:00:33:9e + GETHERC ch1 = 74:90:50:00:33:9f + + +Update SPI ROM: +============================ + +1. Copy u-boot image to RAM area. +2. Probe SPI device. + => sf probe 0 + SF: Detected MX25L6405D with page size 64KiB, total 8 MiB +3. Erase SPI ROM. + => sf erase 0 80000 +4. Write u-boot image to SPI ROM. + => sf write 0x48000000 0 80000 diff --git a/doc/README.socfpga b/doc/README.socfpga new file mode 100644 index 0000000000..cfcbbfe379 --- /dev/null +++ b/doc/README.socfpga @@ -0,0 +1,53 @@ + +-------------------------------------------- +SOCFPGA Documentation for U-Boot and SPL +-------------------------------------------- + +This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore +based SOCFPGA. To know more about the hardware itself, please refer to +www.altera.com. + + +-------------------------------------------- +socfpga_dw_mmc +-------------------------------------------- +Here are macro and detailed configuration required to enable DesignWare SDMMC +controller support within SOCFPGA + +#define CONFIG_MMC +-> To enable the SD MMC framework support + +#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) +-> The base address of CSR register for DesignWare SDMMC controller + +#define CONFIG_GENERIC_MMC +-> Enable the generic MMC driver + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM + +#define CONFIG_DWMMC +-> Enable the common DesignWare SDMMC controller framework + +#define CONFIG_SOCFPGA_DWMMC +-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +-> The FIFO depth for SOCFPGA DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to +the card to meet hold time requirements. SD clock is running at 50MHz and +drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time +is 135 / 360 * 20ns = 7.5ns. + +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +-> Phase-shifted clock of sdmmc_clk used to sample the command and data from +the card + +#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 +-> Bus width of data line which either 1, 4 or 8 and based on board routing. + +#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 +-> The clock rate to controller. Do note the controller have a wrapper which +divide the clock from PLL by 4. diff --git a/doc/README.standalone b/doc/README.standalone index 2be5f27696..659a12f6cb 100644 --- a/doc/README.standalone +++ b/doc/README.standalone @@ -5,23 +5,23 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: table is allocated and initialized in the jumptable_init() routine (common/exports.c). Other routines may also modify the jump table, however. The jump table can be accessed as the 'jt' field of the - 'global_data' structure. The slot numbers for the jump table are + 'global_data' structure. The struct members for the jump table are defined in the header. E.g., to substitute the malloc() and free() functions that will be available to standalone applications, one should do the following: DECLARE_GLOBAL_DATA_PTR; - gd->jt[XF_malloc] = my_malloc; - gd->jt[XF_free] = my_free; + gd->jt->malloc = my_malloc; + gd->jt->free = my_free; - Note that the pointers to the functions all have 'void *' type and - thus the compiler cannot perform type checks on these assignments. + Note that the pointers to the functions are real function pointers + so the compiler can perform type checks on these assignments. 2. The pointer to the jump table is passed to the application in a machine-dependent way. PowerPC, ARM, MIPS, Blackfin and Nios II architectures use a dedicated register to hold the pointer to the - 'global_data' structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, + 'global_data' structure: r2 on PowerPC, r9 on ARM, k0 on MIPS, P3 on Blackfin and gp on Nios II. The x86 architecture does not use such a register; instead, the pointer to the 'global_data' structure is passed as 'argv[-1]' pointer. @@ -65,27 +65,46 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: => tftp 0x40000 hello_world.bin => go 0x40004 -5. To export some additional function foobar(), the following steps +5. To export some additional function long foobar(int i,char c), the following steps should be undertaken: - Append the following line at the end of the include/_exports.h file: - EXPORT_FUNC(foobar) + EXPORT_FUNC(foobar, long, foobar, int, char) + + Parameters to EXPORT_FUNC: + - the first parameter is the function that is exported (default implementation) + - the second parameter is the return value type + - the third parameter is the name of the member in struct jt_funcs + this is also the name that the standalone application will used. + the rest of the parameters are the function arguments - Add the prototype for this function to the include/exports.h file: - void foobar(void); + long foobar(int i, char c); + + Initialization with the default implementation is done in jumptable_init() + + You can override the default implementation using: - - Add the initialization of the jump table slot wherever - appropriate (most likely, to the jumptable_init() function): + gd->jt->foobar = another_foobar; - gd->jt[XF_foobar] = foobar; + The signature of another_foobar must then match the declaration of foobar. - Increase the XF_VERSION value by one in the include/exports.h file + - If you want to export a function which depends on a CONFIG_XXX + use 2 lines like this: + #ifdef CONFIG_FOOBAR + EXPORT_FUNC(foobar, long, foobar, int, char) + #else + EXPORT_FUNC(dummy, void, foobar, void) + #endif + + 6. The code for exporting the U-Boot functions to applications is mostly machine-independent. The only places written in assembly language are stub functions that perform the jump through the jump diff --git a/doc/README.t1040-l2switch b/doc/README.t1040-l2switch new file mode 100644 index 0000000000..14dbf31bf2 --- /dev/null +++ b/doc/README.t1040-l2switch @@ -0,0 +1,48 @@ +This file contains information for VSC9953, a Vitesse L2 Switch IP +which is integrated in the T1040/T1020 Freescale SoCs. + +About Device: +============= +VSC9953 is an 8-port Gigabit Ethernet switch supports the following features: + - 8192 MAC addresses + - Static Address provisioning + - Dynamic learning of MAC addresses and aging + - 4096 VLANs + - Independent and shared VLAN learning (IVL, SVL) + - Policing with storm control and MC/BC protection + - IPv4 and IPv6 multicast + - Jumbo frames (9.6 KB) + - Access Control List + - VLAN editing, translation and remarking + - RMON counters per port + +Switch interfaces: + - 8 Gigabit switch ports (ports 0 to 7) are external and are connected to external PHYs + - 2 switch ports (ports 8 and 9) of 2.5 G are connected (fixed links) + to FMan ports (FM1@DTSEC1 and FM1@DTSEC2) + +Commands Overview: +============= +Commands supported + - enable/disable a port + - check a port's link speed, duplexity and status. + +Commands syntax + ethsw port enable|disable - enable/disable an l2 switch port + ethsw port show - show an l2 switch port's configuration + + port_nr=0..9; use "all" for all ports + +=> ethsw port all show + Port Status Link Speed Duplex + 0 enabled down 10 half + 1 enabled down 10 half + 2 enabled down 10 half + 3 enabled up 1000 full + 4 disabled down - half + 5 disabled down - half + 6 disabled down - half + 7 disabled down - half + 8 enabled up 2500 full + 9 enabled up 2500 full +=> diff --git a/doc/README.t4240qds b/doc/README.t4240qds deleted file mode 100644 index a9841fb5f7..0000000000 --- a/doc/README.t4240qds +++ /dev/null @@ -1,122 +0,0 @@ -Overview --------- -The T4240QDS is a high-performance computing evaluation, development and test -platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is -optimized to support the high-bandwidth DDR3 memory ports, as well as the -highly-configurable SerDes ports. The system is lead-free and RoHS-compliant. - -Board Features - SERDES Connections - 32 lanes grouped into four 8-lane banks - Two “front side” banks dedicated to Ethernet - - High-speed crosspoint switch fabric on selected lanes - - Two PCI Express slots with side-band connector supporting - - SGMII - - XAUI - - HiGig - - I-pass connectors allow board-to-board and loopback support - Two “back side” banks dedicated to other protocols - - High-speed crosspoint switch fabric on all lanes - - Four PCI Express slots with side-band connector supporting - - PCI Express 3.0 - - SATA 2.0 - - SRIO 2.0 - - Supports 4X Aurora debug with two connectors - DDR Controllers - Three independant 64-bit DDR3 controllers - Supports rates of 1866 up to 2133 MHz data-rate - Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller - DDR power supplies 1.5V to all devices with automatic tracking of VTT. - Power software-switchable to 1.35V if software detects all DDR3LP devices. - MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and - 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time - increases by 1 clock. - - IFC/Local Bus - NAND flash: 8-bit, async or sync, up to 2GB. - NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - - NOR devices support 16 virtual banks - GASIC: Minimal target within Qixis FPGA - PromJET rapid memory download support - Address demultiplexing handled within FPGA. - - Flexible demux allows 8 or 16 bit evaluation. - IFC Debug/Development card - - Support for 32-bit devices - Ethernet - Support two on-board RGMII 10/100/1G ethernet ports. - SGMII and XAUI support via SERDES block (see above). - 1588 support via Symmetricom board. - QIXIS System Logic FPGA - Manages system power and reset sequencing - Manages DUT, board, clock, etc. configuration for dynamic shmoo - Collects V-I-T data in background for code/power profiling. - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) - General fault monitoring and logging - Runs from ATX “hot” power rails allowing operation while system is off. - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz. - - Software selectable in 1MHz increments from 1-200MHz. - SERDES clocks - - Provides clocks to all SerDes blocks and slots - - 100, 125 and 156.25 MHz - Power Supplies - Dedicated regulators for VDD - - Adjustable from (0.7V to 1.3V at 80A - - Regulators can be controlled by VID and/or software - Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A - - VTT/MVREF automatically track operating voltage - Dedicated regulators/filters for AVDD supplies - Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc. - USB - Supports two USB 2.0 ports with integrated PHYs - - One type A, one type micro-AB with 1.0A power per port. - Other IO - eSDHC/MMC - - SDHC card slot - eSPI port - - High-speed serial flash - Two Serial port - Four I2C ports - -Memory map ----------- -The addresses in brackets are physical addresses. - -0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) -0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory -0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers) -0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan -0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan -0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO -0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash -0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR -0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS -0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores - -The physical address of the last (boot page translation) varies with the actual DDR size. - -Voltage ID and VDD override --------------------- -T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage -accordingly. The voltage can also be override by command vdd_override. The -syntax is - -vdd_override , eg. 1050 is for 1.050v. - -Upon success, the actual voltage will be read back. The value is checked -for safety and any invalid value will not adjust the voltage. - -Another way to override VDD is to use environmental variable, in case of using -command is too late for some debugging. The syntax is - -setenv t4240qds_vdd_mv -saveenv -reset - -The override voltage takes effect when booting. - -Note: voltage adjustment needs to be done step by step. Changing voltage too -rapidly may cause current surge. The voltage stepping is done by software. -Users can set the final voltage directly. diff --git a/doc/README.trace b/doc/README.trace index 8106290ed9..f0c9699773 100644 --- a/doc/README.trace +++ b/doc/README.trace @@ -63,20 +63,20 @@ In: serial Out: serial Err: serial =>trace stats - 671,406 function sites - 69,712 function calls - 0 untracked function calls - 73,373 traced function calls - 16 maximum observed call depth - 15 call depth limit - 66,491 calls not traced due to depth + 671,406 function sites + 69,712 function calls + 0 untracked function calls + 73,373 traced function calls + 16 maximum observed call depth + 15 call depth limit + 66,491 calls not traced due to depth =>trace stats - 671,406 function sites + 671,406 function sites 1,279,450 function calls - 0 untracked function calls - 950,490 traced function calls (333217 dropped due to overflow) - 16 maximum observed call depth - 15 call depth limit + 0 untracked function calls + 950,490 traced function calls (333217 dropped due to overflow) + 16 maximum observed call depth + 15 call depth limit 1,275,767 calls not traced due to depth =>trace calls 0 e00000 Call list dumped to 00000000, size 0xae0a40 diff --git a/doc/README.ubi b/doc/README.ubi index 3cf4ef232d..9efab6cdc9 100644 --- a/doc/README.ubi +++ b/doc/README.ubi @@ -14,6 +14,8 @@ ubi part [part] [offset] ubi info [l[ayout]] - Display volume and ubi layout information ubi create[vol] volume [size] [type] - create volume name with size ubi write[vol] address volume size - Write volume from address with size +ubi write.part address volume size [fullsize] + - Write part of a volume from address ubi read[vol] address volume [size] - Read volume to address with size ubi remove[vol] volume - Remove volume [Legends] @@ -77,6 +79,7 @@ ubi createvol Create UBI volume on UBI device ubi removevol Remove UBI volume from UBI device ubi read Read data from UBI volume to memory ubi write Write data from memory to UBI volume +ubi write.part Write data from memory to UBI volume, in parts Here a few examples on the usage: @@ -185,8 +188,8 @@ ubifsls [directory] For example: => ubifsls - 17442 Thu Jan 01 02:57:38 1970 imx28-evk.dtb - 2998146 Thu Jan 01 02:57:43 1970 zImage + 17442 Thu Jan 01 02:57:38 1970 imx28-evk.dtb + 2998146 Thu Jan 01 02:57:43 1970 zImage And the ubifsload command allows you to load a file from a UBI diff --git a/doc/README.unaligned-memory-access.txt b/doc/README.unaligned-memory-access.txt new file mode 100644 index 0000000000..70a85f9cfe --- /dev/null +++ b/doc/README.unaligned-memory-access.txt @@ -0,0 +1,240 @@ +Editors note: This document is _heavily_ cribbed from the Linux Kernel, with +really only the section about "Alignment vs. Networking" removed. + +UNALIGNED MEMORY ACCESSES +========================= + +Linux runs on a wide variety of architectures which have varying behaviour +when it comes to memory access. This document presents some details about +unaligned accesses, why you need to write code that doesn't cause them, +and how to write such code! + + +The definition of an unaligned access +===================================== + +Unaligned memory accesses occur when you try to read N bytes of data starting +from an address that is not evenly divisible by N (i.e. addr % N != 0). +For example, reading 4 bytes of data from address 0x10004 is fine, but +reading 4 bytes of data from address 0x10005 would be an unaligned memory +access. + +The above may seem a little vague, as memory access can happen in different +ways. The context here is at the machine code level: certain instructions read +or write a number of bytes to or from memory (e.g. movb, movw, movl in x86 +assembly). As will become clear, it is relatively easy to spot C statements +which will compile to multiple-byte memory access instructions, namely when +dealing with types such as u16, u32 and u64. + + +Natural alignment +================= + +The rule mentioned above forms what we refer to as natural alignment: +When accessing N bytes of memory, the base memory address must be evenly +divisible by N, i.e. addr % N == 0. + +When writing code, assume the target architecture has natural alignment +requirements. + +In reality, only a few architectures require natural alignment on all sizes +of memory access. However, we must consider ALL supported architectures; +writing code that satisfies natural alignment requirements is the easiest way +to achieve full portability. + + +Why unaligned access is bad +=========================== + +The effects of performing an unaligned memory access vary from architecture +to architecture. It would be easy to write a whole document on the differences +here; a summary of the common scenarios is presented below: + + - Some architectures are able to perform unaligned memory accesses + transparently, but there is usually a significant performance cost. + - Some architectures raise processor exceptions when unaligned accesses + happen. The exception handler is able to correct the unaligned access, + at significant cost to performance. + - Some architectures raise processor exceptions when unaligned accesses + happen, but the exceptions do not contain enough information for the + unaligned access to be corrected. + - Some architectures are not capable of unaligned memory access, but will + silently perform a different memory access to the one that was requested, + resulting in a subtle code bug that is hard to detect! + +It should be obvious from the above that if your code causes unaligned +memory accesses to happen, your code will not work correctly on certain +platforms and will cause performance problems on others. + + +Code that does not cause unaligned access +========================================= + +At first, the concepts above may seem a little hard to relate to actual +coding practice. After all, you don't have a great deal of control over +memory addresses of certain variables, etc. + +Fortunately things are not too complex, as in most cases, the compiler +ensures that things will work for you. For example, take the following +structure: + + struct foo { + u16 field1; + u32 field2; + u8 field3; + }; + +Let us assume that an instance of the above structure resides in memory +starting at address 0x10000. With a basic level of understanding, it would +not be unreasonable to expect that accessing field2 would cause an unaligned +access. You'd be expecting field2 to be located at offset 2 bytes into the +structure, i.e. address 0x10002, but that address is not evenly divisible +by 4 (remember, we're reading a 4 byte value here). + +Fortunately, the compiler understands the alignment constraints, so in the +above case it would insert 2 bytes of padding in between field1 and field2. +Therefore, for standard structure types you can always rely on the compiler +to pad structures so that accesses to fields are suitably aligned (assuming +you do not cast the field to a type of different length). + +Similarly, you can also rely on the compiler to align variables and function +parameters to a naturally aligned scheme, based on the size of the type of +the variable. + +At this point, it should be clear that accessing a single byte (u8 or char) +will never cause an unaligned access, because all memory addresses are evenly +divisible by one. + +On a related topic, with the above considerations in mind you may observe +that you could reorder the fields in the structure in order to place fields +where padding would otherwise be inserted, and hence reduce the overall +resident memory size of structure instances. The optimal layout of the +above example is: + + struct foo { + u32 field2; + u16 field1; + u8 field3; + }; + +For a natural alignment scheme, the compiler would only have to add a single +byte of padding at the end of the structure. This padding is added in order +to satisfy alignment constraints for arrays of these structures. + +Another point worth mentioning is the use of __attribute__((packed)) on a +structure type. This GCC-specific attribute tells the compiler never to +insert any padding within structures, useful when you want to use a C struct +to represent some data that comes in a fixed arrangement 'off the wire'. + +You might be inclined to believe that usage of this attribute can easily +lead to unaligned accesses when accessing fields that do not satisfy +architectural alignment requirements. However, again, the compiler is aware +of the alignment constraints and will generate extra instructions to perform +the memory access in a way that does not cause unaligned access. Of course, +the extra instructions obviously cause a loss in performance compared to the +non-packed case, so the packed attribute should only be used when avoiding +structure padding is of importance. + + +Code that causes unaligned access +================================= + +With the above in mind, let's move onto a real life example of a function +that can cause an unaligned memory access. The following function taken +from the Linux Kernel's include/linux/etherdevice.h is an optimized routine +to compare two ethernet MAC addresses for equality. + +bool ether_addr_equal(const u8 *addr1, const u8 *addr2) +{ +#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + u32 fold = ((*(const u32 *)addr1) ^ (*(const u32 *)addr2)) | + ((*(const u16 *)(addr1 + 4)) ^ (*(const u16 *)(addr2 + 4))); + + return fold == 0; +#else + const u16 *a = (const u16 *)addr1; + const u16 *b = (const u16 *)addr2; + return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0; +#endif +} + +In the above function, when the hardware has efficient unaligned access +capability, there is no issue with this code. But when the hardware isn't +able to access memory on arbitrary boundaries, the reference to a[0] causes +2 bytes (16 bits) to be read from memory starting at address addr1. + +Think about what would happen if addr1 was an odd address such as 0x10003. +(Hint: it'd be an unaligned access.) + +Despite the potential unaligned access problems with the above function, it +is included in the kernel anyway but is understood to only work normally on +16-bit-aligned addresses. It is up to the caller to ensure this alignment or +not use this function at all. This alignment-unsafe function is still useful +as it is a decent optimization for the cases when you can ensure alignment, +which is true almost all of the time in ethernet networking context. + + +Here is another example of some code that could cause unaligned accesses: + void myfunc(u8 *data, u32 value) + { + [...] + *((u32 *) data) = cpu_to_le32(value); + [...] + } + +This code will cause unaligned accesses every time the data parameter points +to an address that is not evenly divisible by 4. + +In summary, the 2 main scenarios where you may run into unaligned access +problems involve: + 1. Casting variables to types of different lengths + 2. Pointer arithmetic followed by access to at least 2 bytes of data + + +Avoiding unaligned accesses +=========================== + +The easiest way to avoid unaligned access is to use the get_unaligned() and +put_unaligned() macros provided by the header file. + +Going back to an earlier example of code that potentially causes unaligned +access: + + void myfunc(u8 *data, u32 value) + { + [...] + *((u32 *) data) = cpu_to_le32(value); + [...] + } + +To avoid the unaligned memory access, you would rewrite it as follows: + + void myfunc(u8 *data, u32 value) + { + [...] + value = cpu_to_le32(value); + put_unaligned(value, (u32 *) data); + [...] + } + +The get_unaligned() macro works similarly. Assuming 'data' is a pointer to +memory and you wish to avoid unaligned access, its usage is as follows: + + u32 value = get_unaligned((u32 *) data); + +These macros work for memory accesses of any length (not just 32 bits as +in the examples above). Be aware that when compared to standard access of +aligned memory, using these macros to access unaligned memory can be costly in +terms of performance. + +If use of such macros is not convenient, another option is to use memcpy(), +where the source or destination (or both) are of type u8* or unsigned char*. +Due to the byte-wise nature of this operation, unaligned accesses are avoided. + +-- +In the Linux Kernel, +Authors: Daniel Drake , + Johannes Berg +With help from: Alan Cox, Avuton Olrich, Heikki Orsila, Jan Engelhardt, +Kyle McMartin, Kyle Moffett, Randy Dunlap, Robert Hancock, Uli Kunitz, +Vadim Lobanov diff --git a/doc/README.usb b/doc/README.usb index 65fb2886d9..bc768a3854 100644 --- a/doc/README.usb +++ b/doc/README.usb @@ -127,8 +127,14 @@ To enable USB Host Ethernet in U-Boot, your platform must of course support USB with CONFIG_CMD_USB enabled and working. You will need to add some config settings to your board header file: +#define CONFIG_CMD_USB /* the 'usb' interactive command */ #define CONFIG_USB_HOST_ETHER /* Enable USB Ethernet adapters */ -#define CONFIG_USB_ETHER_ASIX /* Asix, or whatever driver(s) you want */ + +and one or more of the following for individual adapter hardware: + +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX As with built-in networking, you will also want to enable some network commands, for example: @@ -148,7 +154,10 @@ settings should start you off: You can also set the default IP address of your board and the server as well as the default file to load when a 'bootp' command is issued. -All of these can be obtained from the bootp server if not set. +However note that encoding these individual network settings into a +common exectuable is discouraged, as it leads to potential conflicts, +and all the parameters can either get stored in the board's external +environment, or get obtained from the bootp server if not set. #define CONFIG_IPADDR 10.0.0.2 (replace with your value) #define CONFIG_SERVERIP 10.0.0.1 (replace with your value) diff --git a/doc/README.video b/doc/README.video index f09d5f9f6b..d0a3ad6e8d 100644 --- a/doc/README.video +++ b/doc/README.video @@ -5,17 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -U-Boot MPC8xx video controller driver -====================================== - -The driver has been tested with the following configurations: - -- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it -- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it - - "video-mode" environment variable -=============================== +================================= The 'video-mode' environment variable can be used to enable and configure some video drivers. The format matches the video= command-line option used @@ -30,4 +21,50 @@ for Linux: The frequency (in Hz) to use. A comma-separated list of device-specific options + +U-Boot MPC8xx video controller driver +===================================== + +The driver has been tested with the following configurations: + +- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it + Example: video-mode=fslfb:1280x1024-32@60,monitor=dvi + + +U-boot sunxi video controller driver +==================================== + +U-boot supports hdmi and lcd output on Allwinner sunxi SoCs, lcd output +requires the CONFIG_VIDEO_LCD_MODE Kconfig value to be set. + +The sunxi u-boot driver supports the following video-mode options: + +- monitor=[none|dvi|hdmi|lcd] - Select the video output to use + none: Disable video output. + dvi/hdmi: Selects output over the hdmi connector with dvi resp. hdmi output + format, if edid is used the format is automatically selected. + lcd: Selects video output to a LCD screen. + vga: Selects bideo output over the VGA connector. + Defaults to monitor=dvi. + +- hpd=[0|1] - Enable use of the hdmi HotPlug Detect feature + 0: Disabled. Configure dvi/hdmi output even if no cable is detected + 1: Enabled. Fallback to the lcd / vga / none in that order (if available) + Defaults to hpd=1. + +- hpd_delay= - How long to wait for the hdmi HPD signal in milliseconds + When the monitor and the board power up at the same time, it may take some + time for the monitor to assert the HPD signal. This configures how long to + wait for the HPD signal before assuming no cable is connected. + Defaults to hpd_delay=500. + +- edid=[0|1] - Enable use of DDC + EDID to get monitor info + 0: Disabled. + 1: Enabled. If valid EDID info was read from the monitor the EDID info will + overrides the xres, yres and refresh from the video-mode env. variable. + Defaults to edid=1. + +For example to always use the hdmi connector, even if no cable is inserted, +using edid info when available and otherwise initalizing it at 1024x768@60Hz, +use: "setenv video-mode sunxi:1024x768-24@60,monitor=dvi,hpd=0,edid=1". diff --git a/doc/README.vxworks b/doc/README.vxworks new file mode 100644 index 0000000000..4cb302e7f4 --- /dev/null +++ b/doc/README.vxworks @@ -0,0 +1,19 @@ +From VxWorks 6.9+ (not include 6.9), VxWorks starts adopting device tree as its hardware +decription mechansim (for PowerPC and ARM), thus requiring boot interface changes. +This section will describe the new interface. + +For PowerPC, the calling convention of the new VxWorks entry point conforms to the ePAPR standard, +which is shown below (see ePAPR for more details): + + void (*kernel_entry)(fdt_addr, + 0, 0, EPAPR_MAGIC, boot_IMA, 0, 0) + +For ARM, the calling convention is show below: + + void (*kernel_entry)(void *fdt_addr) + +When booting new VxWorks kernel (uImage format), the parameters passed to bootm is like below: + + bootm - + +The do_bootvx command still works as it was for older VxWorks kernels. diff --git a/doc/README.x86 b/doc/README.x86 new file mode 100644 index 0000000000..7df8cc516a --- /dev/null +++ b/doc/README.x86 @@ -0,0 +1,177 @@ +# +# Copyright (C) 2014, Simon Glass +# Copyright (C) 2014, Bin Meng +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +============= + +This document describes the information about U-Boot running on x86 targets, +including supported boards, build instructions, todo list, etc. + +Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only Link +(Chromebook Pixel) has been tested, but it should work with minimal adjustments +on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Link and Intel Crown Bay board +support running U-Boot 'bare metal'. + +As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux +kernel as part of a FIT image. It also supports a compressed zImage. + +Build Instructions +------------------ +Building U-Boot as a coreboot payload is just like building U-Boot for targets +on other architectures, like below: + +$ make coreboot-x86_defconfig +$ make all + +Note this default configuration will build a U-Boot payload for the Link board. +To build a coreboot payload against another board, you can change the build +configuration during the 'make menuconfig' process. + +x86 architecture ---> + ... + (chromebook_link) Board configuration file + (chromebook_link) Board Device Tree Source (dts) file + (0x19200000) Board specific Cache-As-RAM (CAR) address + (0x4000) Board specific Cache-As-RAM (CAR) size + +Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' +to point to a new board. You can also change the Cache-As-RAM (CAR) related +settings here if the default values do not fit your new board. + +Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a +little bit tricky, as generally it requires several binary blobs which are not +shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is +not turned on by default in the U-Boot source tree. Firstly, you need turn it +on by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Link-specific instructions: + +First, you need the following binary blobs: + +* descriptor.bin - Intel flash descriptor +* me.bin - Intel Management Engine +* mrc.bin - Memory Reference Code, which sets up SDRAM +* video ROM - sets up the display + +You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin. +As for the video ROM, you can get it here [2]. +Make sure all these binary blobs are put in the board directory. + +Now you can build U-Boot and obtain u-boot.rom: + +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide, including initialization of the CPU, +memory controller, chipset and certain bus interfaces. + +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Rename the first one to fsp.bin and second one to cmc.bin and put them in the +board directory. + +Now you can build U-Boot and obtain u-boot.rom + +$ make crownbay_defconfig +$ make all + +Test with coreboot +------------------ +For testing U-Boot as the coreboot payload, there are things that need be paid +attention to. coreboot supports loading an ELF executable and a 32-bit plain +binary, as well as other supported payloads. With the default configuration, +U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the +generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool +provided by coreboot) manually as coreboot's 'make menuconfig' does not provide +this capability yet. The command is as follows: + +# in the coreboot root directory +$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ + -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 + +Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the +symbol address of _start (in arch/x86/cpu/start.S). + +If you want to use ELF as the coreboot payload, change U-Boot configuration to +use CONFIG_OF_EMBED. + +CPU Microcode +------------- +Modern CPU usually requires a special bit stream called microcode [5] to be +loaded on the processor after power up in order to function properly. U-Boot +has already integrated these as hex dumps in the source tree. + +Driver Model +------------ +x86 has been converted to use driver model for serial and GPIO. + +Device Tree +----------- +x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to +be turned on. Not every device on the board is configured via device tree, but +more and more devices will be added as time goes by. Check out the directory +arch/x86/dts/ for these device tree source files. + +Useful Commands +--------------- + +In keeping with the U-Boot philosophy of providing functions to check and +adjust internal settings, there are several x86-specific commands that may be +useful: + +hob - Display information about Firmware Support Package (FSP) Hand-off + Block. This is only available on platforms which use FSP, mostly + Atom. +iod - Display I/O memory +iow - Write I/O memory +mtrr - List and set the Memory Type Range Registers (MTRR). These are used to + tell the CPU whether memory is cacheable and if so the cache write + mode to use. U-Boot sets up some reasonable values but you can + adjust then with this command. + +TODO List +--------- +- Audio +- Chrome OS verified boot +- SMI and ACPI support, to provide platform info and facilities to Linux + +References +---------- +[1] http://www.coreboot.org +[2] http://www.coreboot.org/~stepan/pci8086,0166.rom +[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +[4] http://www.intel.com/fsp +[5] http://en.wikipedia.org/wiki/Microcode diff --git a/doc/README.zfs b/doc/README.zfs index f5998f2f88..7f237c4076 100644 --- a/doc/README.zfs +++ b/doc/README.zfs @@ -7,20 +7,20 @@ Steps to test: 1. After applying the patch, zfs specific commands can be seen in the boot loader prompt using - UBOOT #help + UBOOT #help - zfsload- load binary file from a ZFS file system - zfsls - list files in a directory (default /) + zfsload- load binary file from a ZFS file system + zfsls - list files in a directory (default /) 2. To list the files in zfs pool, device or partition, execute - zfsls [POOL/@/dir/file] - For example: - UBOOT #zfsls mmc 0:5 /rpool/@/usr/bin/ + zfsls [POOL/@/dir/file] + For example: + UBOOT #zfsls mmc 0:5 /rpool/@/usr/bin/ 3. To read and load a file from an ZFS formatted partition to RAM, execute - zfsload [addr] [filename] [bytes] - For example: - UBOOT #zfsload mmc 2:2 0x30007fc0 /rpool/@/boot/uImage + zfsload [addr] [filename] [bytes] + For example: + UBOOT #zfsload mmc 2:2 0x30007fc0 /rpool/@/boot/uImage References : -- ZFS GRUB sources from Solaris GRUB-0.97 diff --git a/doc/README.zynq b/doc/README.zynq new file mode 100644 index 0000000000..043c970140 --- /dev/null +++ b/doc/README.zynq @@ -0,0 +1,94 @@ +# +# Xilinx ZYNQ U-Boot +# +# (C) Copyright 2013 Xilinx, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +1. About this + +This document describes the information about Xilinx Zynq U-Boot - +like supported boards, ML status and TODO list. + +2. Zynq boards + +Xilinx Zynq-7000 All Programmable SoCs enable extensive system level +differentiation, integration, and flexibility through hardware, software, +and I/O programmability. + +* zc70x + - zc702 (single qspi, gem0, mmc) [1] + - zc706 (dual parallel qspi, gem0, mmc) [2] +* zed (single qspi, gem0, mmc) [3] +* microzed (single qspi, gem0, mmc) [4] +* zc770 + - zc770-xm010 (single qspi, gem0, mmc) + - zc770-xm011 (8 or 16 bit nand) + - zc770-xm012 (nor) + - zc770-xm013 (dual parallel qspi, gem1) + +3. Building + + # Configure for zc70x board + $ make zynq_zc70x_config + Configuring for zynq_zc70x board... + + # Building default dts for zc702 board + $ make + + # Building specified dts for zc706 board + $ make DEVICE_TREE=zynq-zc706 + +4. Bootmode + +Zynq has a facility to read the bootmode from the slcr bootmode register +once user is setting through jumpers on the board - see page no:1546 on [5] + +All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins +on [5]. + +board_late_init() will read the bootmode values using slcr bootmode register +at runtime and assign the modeboot variable to specific bootmode string which +is intern used in autoboot. + +SLCR bootmode register Bit[3:0] values +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + +"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" +bootmode strings at runtime. + +5. Mainline status + +- Added basic board configurations support. +- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq +- Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013 +- Added zynq drivers: + serial - drivers/serial/serial_zynq.c + net - drivers/net/zynq_gem.c + mmc - drivers/mmc/zynq_sdhci.c + mmc - drivers/mmc/zynq_sdhci.c + spi- drivers/spi/zynq_spi.c + i2c - drivers/i2c/zynq_i2c.c +- Done proper cleanups on board configurations +- Added basic FDT support for zynq boards +- d-cache support for zynq_gem.c + +6. TODO + +- Add zynq boards support - zc770_xm011 +- Add zynq qspi controller driver +- Add zynq nand controller driver +- Add FDT support on individual drivers + +[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm +[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm +[3] http://zedboard.org/product/zedboard +[4] http://zedboard.org/product/microzed +[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf + +-- +Jagannadha Sutradharudu Teki +Sun Dec 15 14:52:41 IST 2013 diff --git a/doc/SPI/README.altera_spi b/doc/SPI/README.altera_spi new file mode 100644 index 0000000000..b07449f80d --- /dev/null +++ b/doc/SPI/README.altera_spi @@ -0,0 +1,6 @@ +SoCFPGA EPCS/EPCQx1 mini howto: +- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild +- The controller base address is the "Base" in QSys + 0x400 +- Set MSEL[4:0]=10010 (AS Standard) +- Load the bitstream into FPGA, enable bridges +- Only then will the driver work diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash new file mode 100644 index 0000000000..6c88d65dd4 --- /dev/null +++ b/doc/SPI/README.dual-flash @@ -0,0 +1,92 @@ +SPI/QSPI Dual flash connection modes: +===================================== + +This describes how SPI/QSPI flash memories are connected to a given +controller in a single chip select line. + +Current spi_flash framework supports, single flash memory connected +to a given controller with single chip select line, but there are some +hw logics(ex: xilinx zynq qspi) that describes two/dual memories are +connected with a single chip select line from a controller. + +"dual_flash" from include/spi.h describes these types of connection mode + +Possible connections: +-------------------- +SF_SINGLE_FLASH: + - single spi flash memory connected with single chip select line. + + +------------+ CS +---------------+ + | |----------------------->| | + | Controller | I0[3:0] | Flash memory | + | SPI/QSPI |<======================>| (SPI/QSPI) | + | | CLK | | + | |----------------------->| | + +------------+ +---------------+ + +SF_DUAL_STACKED_FLASH: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating stacked fasion with shared buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | | +=========>| memory | + | | | CLK | (SPI/QSPI) | + | | | +---->| | + | Controller | CS | | +---------------+ + | SPI/QSPI |------------|----|---->| | + | | I0[3:0] | | | Lower Flash | + | |<===========+====|====>| memory | + | | CLK | | (SPI/QSPI) | + | |-----------------+---->| | + +------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG + Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory + Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory + - Operation: + accessing memories serially like one after another. + by default, if U_PAGE is unset lower memory should accessible, + once user wants to access upper memory need to set U_PAGE. + +SPI_FLASH_CONN_DUALPARALLEL: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating parallel with separate buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +-------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + | Controller | CS +---------------+ + | SPI/QSPI |---------------------->| | + | | I0[3:0] | Lower Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + +-------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register. + - Operation: + Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory + and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory. + +Note: Technically there is only one CS line from the controller, but +zynq qspi controller has an internal hw logic to enable additional CS +when controller is configured for dual memories. + +[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf + +-- +Jagannadha Sutradharudu Teki +05-01-2014. diff --git a/doc/SPI/README.ftssp010_spi_test b/doc/SPI/README.ftssp010_spi_test new file mode 100644 index 0000000000..1d86f3623f --- /dev/null +++ b/doc/SPI/README.ftssp010_spi_test @@ -0,0 +1,41 @@ +SPI Flash test on Faraday A369 EVB: +================================== + +U-Boot 2014.01-rc2-g3444b6f (Dec 20 2013 - 10:58:40) + +CPU: FA626TE 528 MHz +AHB: 132 MHz +APB: 66 MHz +I2C: ready +DRAM: 256 MiB +MMU: on +NAND: 512 MiB +MMC: ftsdc010: 0 +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: FTGMAC100#0 +Hit any key to stop autoboot: 0 +=> sf probe 0:0 +SF: Detected MX25L1605D with page size 256 Bytes, erase size 64 KiB, total 2 MiB +=> sf read 0x10800000 0 0x400 +SF: 1024 bytes @ 0x0 Read: OK +=> md 0x10800000 +10800000: ea000013 e59ff014 e59ff014 e59ff014 ................ +10800010: e59ff014 e59ff014 e59ff014 e59ff014 ................ +10800020: 1ff7b0c0 1ff7b120 1ff7b180 1ff7b1e0 .... ........... +10800030: 1ff7b240 1ff7b2a0 1ff7b300 deadbeef @............... +10800040: 10800000 0002c1f0 0007409c 00032048 .........@..H .. +10800050: 1fd6af40 e10f0000 e3c0001f e38000d3 @............... +10800060: e129f000 eb000001 eb000223 e12fff1e ..).....#...../. +10800070: e3a00000 ee070f1e ee080f17 ee070f15 ................ +10800080: ee070f9a ee110f10 e3c00c03 e3c00087 ................ +10800090: e3c00a02 e3800002 e3800a01 ee010f10 ................ +108000a0: e1a0c00e eb007a68 e1a0e00c e1a0f00e ....hz.......... +108000b0: e1a00000 e1a00000 e1a00000 e1a00000 ................ +108000c0: e51fd078 e58de000 e14fe000 e58de004 x.........O..... +108000d0: e3a0d013 e169f00d e1a0e00f e1b0f00e ......i......... +108000e0: e24dd048 e88d1fff e51f20a0 e892000c H.M...... ...... +108000f0: e28d0048 e28d5034 e1a0100e e885000f H...4P.......... diff --git a/doc/SPI/README.sandbox-spi b/doc/SPI/README.sandbox-spi new file mode 100644 index 0000000000..bb73eaf288 --- /dev/null +++ b/doc/SPI/README.sandbox-spi @@ -0,0 +1,64 @@ +Sandbox SPI/SPI Flash Implementation +==================================== + +U-Boot supports SPI and SPI flash emuation in sandbox. This must be enabled +using the --spi_sf paramter when starting U-Boot. + +For example: + +$ make O=sandbox sandbox_config +$ make O=sandbox +$ ./sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin + +The four parameters to spi_sf are: + + SPI bus number (typically 0) + SPI chip select number (typically 0) + SPI chip to emulate + File containing emulated data + +Supported chips are W25Q16 (2MB), W25Q32 (4MB) and W25Q128 (16MB). Once +U-Boot it started you can use 'sf' commands as normal. For example: + +$ ./b/sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin \ + -c "sf probe; sf test 0 100000; sf read 0 1000 1000; \ + sf erase 1000 1000; sf write 0 1000 1000" + + +U-Boot 2013.10-00237-gd4e0fdb (Nov 07 2013 - 20:08:15) + +DRAM: 128 MiB +Using default environment + +In: serial +Out: serial +Err: serial +SF: Detected W25Q128BV with page size 256 Bytes, erase size 4 KiB, total 16 MiB +SPI flash test: +0 erase: 1 ticks, 1024000 KiB/s 8192.000 Mbps +1 check: 2 ticks, 512000 KiB/s 4096.000 Mbps +2 write: 6 ticks, 170666 KiB/s 1365.328 Mbps +3 read: 0 ticks, 1048576000 KiB/s -201326.-592 Mbps +Test passed +0 erase: 1 ticks, 1024000 KiB/s 8192.000 Mbps +1 check: 2 ticks, 512000 KiB/s 4096.000 Mbps +2 write: 6 ticks, 170666 KiB/s 1365.328 Mbps +3 read: 0 ticks, 1048576000 KiB/s -201326.-592 Mbps +SF: 4096 bytes @ 0x1000 Read: OK +SF: 4096 bytes @ 0x1000 Erased: OK +SF: 4096 bytes @ 0x1000 Written: OK + + +Since the SPI bus is fully implemented as well as the SPI flash connected to +it, you can also use low-level SPI commands to access the flash. For example +this reads the device ID from the emulated chip: + +=> sspi 0 32 9f +FFEF4018 + + +Simon Glass +sjg@chromium.org +7/11/2013 +Note that the sandbox SPI implementation was written by Mike Frysinger +. diff --git a/doc/SPI/README.sh_qspi_test b/doc/SPI/README.sh_qspi_test new file mode 100644 index 0000000000..8a33fec32f --- /dev/null +++ b/doc/SPI/README.sh_qspi_test @@ -0,0 +1,38 @@ +------------------------------------------------- + Simple steps used to test the SH-QSPI at U-Boot +------------------------------------------------- + +#0, Currently, SH-QSPI is used by lager board (Renesas ARM SoC R8A7790) + and koelsch board (Renesas ARM SoC R8A7791). These boot from SPI ROM + basically. Thus, U-Boot start, SH-QSPI will is operating normally. + +#1, build U-Boot and load u-boot.bin + + => tftpboot 40000000 u-boot.bin + sh_eth Waiting for PHY auto negotiation to complete.. done + sh_eth: 100Base/Half + Using sh_eth device + TFTP from server 192.168.169.1; our IP address is 192.168.169.79 + Filename 'u-boot.bin'. + Load address: 0x40000000 + Loading: ############ + 2.5 MiB/s + done + Bytes transferred = 175364 (2ad04 hex) + +#2, Commands to erase/write u-boot to flash device + + Note: This method is description of the lager board. If you want to use the + other boards, please change the value according to each environment. + + => sf probe 0 + SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 64 KiB, total 64 MiB + => sf erase 80000 40000 + SF: 262144 bytes @ 0x80000 Erased: OK + => sf write 40000000 80000 175364 + SF: 1528676 bytes @ 0x80000 Written: OK + => + +#3, Push reset button. + + If you're written correctly and driver works properly, U-Boot starts. diff --git a/doc/SPI/README.ti_qspi_am43x_test b/doc/SPI/README.ti_qspi_am43x_test new file mode 100644 index 0000000000..8fbf10b57a --- /dev/null +++ b/doc/SPI/README.ti_qspi_am43x_test @@ -0,0 +1,76 @@ +Testing details- +---------------- + +This doc simply illustrated the testing details of qspi flash +driver with Macronix M25L51235 flash device. + +The test includes +- probing the flash device +- erasing the flash device +- Writing to flash +- Reading the contents of the flash. + +Test Log +-------- + +Hit any key to stop autoboot: 0 +U-Boot# sf probe 0 +SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 +U-Boot# sf erase 0 0x80000 +SF: 524288 bytes @ 0x0 Erased: OK +U-Boot# mw 81000000 0xdededede 0x40000 +U-Boot# sf write 81000000 0 0x40000 +SF: 262144 bytes @ 0x0 Written: OK +U-Boot# sf read 82000000 0 0x40000 +SF: 262144 bytes @ 0x0 Read: OK +U-Boot# md 0x82000000 +82000000: dededede dededede dededede dededede ................ +82000010: dededede dededede dededede dededede ................ +82000020: dededede dededede dededede dededede ................ +82000030: dededede dededede dededede dededede ................ +82000040: dededede dededede dededede dededede ................ +82000050: dededede dededede dededede dededede ................ +82000060: dededede dededede dededede dededede ................ +82000070: dededede dededede dededede dededede ................ +82000080: dededede dededede dededede dededede ................ +82000090: dededede dededede dededede dededede ................ +820000a0: dededede dededede dededede dededede ................ +820000b0: dededede dededede dededede dededede ................ +820000c0: dededede dededede dededede dededede ................ +820000d0: dededede dededede dededede dededede ................ +820000e0: dededede dededede dededede dededede ................ +820000f0: dededede dededede dededede dededede ................ +U-Boot# md 0x82010000 +82010000: dededede dededede dededede dededede ................ +82010010: dededede dededede dededede dededede ................ +82010020: dededede dededede dededede dededede ................ +82010030: dededede dededede dededede dededede ................ +82010040: dededede dededede dededede dededede ................ +82010050: dededede dededede dededede dededede ................ +82010060: dededede dededede dededede dededede ................ +82010070: dededede dededede dededede dededede ................ +82010080: dededede dededede dededede dededede ................ +82010090: dededede dededede dededede dededede ................ +820100a0: dededede dededede dededede dededede ................ +820100b0: dededede dededede dededede dededede ................ +820100c0: dededede dededede dededede dededede ................ +820100d0: dededede dededede dededede dededede ................ +820100e0: dededede dededede dededede dededede ................ +820100f0: dededede dededede dededede dededede ................ +U-Boot# md 0x82030000 +82030000: dededede dededede dededede dededede ................ +82030010: dededede dededede dededede dededede ................ +82030020: dededede dededede dededede dededede ................ +82030030: dededede dededede dededede dededede ................ +82030040: dededede dededede dededede dededede ................ +82030050: dededede dededede dededede dededede ................ +82030060: dededede dededede dededede dededede ................ +82030070: dededede dededede dededede dededede ................ +82030080: dededede dededede dededede dededede ................ +82030090: dededede dededede dededede dededede ................ +820300a0: dededede dededede dededede dededede ................ +820300b0: dededede dededede dededede dededede ................ +820300c0: dededede dededede dededede dededede ................ +820300d0: dededede dededede dededede dededede ................ +820300e0: dededede dededede dededede dededede ................ +820300f0: dededede dededede dededede dededede ................ diff --git a/doc/SPI/README.ti_qspi_dra_test b/doc/SPI/README.ti_qspi_dra_test new file mode 100644 index 0000000000..fe37857236 --- /dev/null +++ b/doc/SPI/README.ti_qspi_dra_test @@ -0,0 +1,48 @@ +------------------------------------------------- + Simple steps used to test the QSPI at U-Boot +------------------------------------------------- + +For #1, build the patched U-Boot and load MLO/u-boot.img + +---------------------------------- +Boot from another medium like MMC +---------------------------------- + +U-Boot# mmc dev 0 +mmc0 is current device +U-Boot# fatload mmc 0 0x82000000 MLO +reading MLO +55872 bytes read in 8 ms (6.7 MiB/s) +U-Boot# fatload mmc 0 0x83000000 u-boot.img +reading u-boot.img +248600 bytes read in 19 ms (12.5 MiB/s) + +-------------------------------------------------- +Commands to erase/write u-boot/mlo to flash device +-------------------------------------------------- +U-Boot# sf probe 0 +SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c000000 +SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR +U-Boot# sf erase 0 0x10000 +SF: 65536 bytes @ 0x0 Erased: OK +U-Boot# sf erase 0x20000 0x10000 +SF: 65536 bytes @ 0x20000 Erased: OK +U-Boot# sf erase 0x30000 0x10000 +SF: 65536 bytes @ 0x30000 Erased: OK +U-Boot# sf erase 0x40000 0x10000 +SF: 65536 bytes @ 0x40000 Erased: OK +U-Boot# sf erase 0x50000 0x10000 +SF: 65536 bytes @ 0x50000 Erased: OK +U-Boot# sf erase 0x60000 0x10000 +SF: 65536 bytes @ 0x60000 Erased: OK +U-Boot# sf write 82000000 0 0x10000 +SF: 65536 bytes @ 0x0 Written: OK +U-Boot# sf write 83000000 0x20000 0x60000 +SF: 393216 bytes @ 0x20000 Written: OK + +For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power +on. ROM should find the GP header at offset 0 and load/execute SPL. SPL +then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to +find a U-Boot image header at offset 0x20000 (set in the config file) +and proceeds to load that image using the U-Boot image payload offset/size +from the header. It will then start U-Boot. diff --git a/doc/SPI/README.ti_qspi_flash b/doc/SPI/README.ti_qspi_flash new file mode 100644 index 0000000000..1b86d01a0e --- /dev/null +++ b/doc/SPI/README.ti_qspi_flash @@ -0,0 +1,47 @@ +QSPI U-boot support +------------------ + +Host processor is connected to serial flash device via qpsi +interface. QSPI is a kind of spi module that allows single, +dual and quad read access to external spi devices. The module +has a memory mapped interface which provide direct interface +for accessing data form external spi devices. + +The one QSPI in the device is primarily intended for fast booting +from Quad SPI flash devices. + +Usecase +------- + +MLO/u-boot.img will be flashed from SD/MMC to the flash device +using serial flash erase and write commands. Then, switch settings +will be changed to qspi boot. Then, the ROM code will read MLO +from the predefined location in the flash, where it was flashed and +execute it after storing it in SDRAM. Then, the MLO will read +u-boot.img from flash and execute it from SDRAM. + +SPI mode +------- +SPI mode uses mtd spi framework for transfer and reception of data. +Can be used in: +1. Normal mode: use single pin for transfers +2. Dual Mode: use two pins for transfers. +3. Quad mode: use four pin for transfer + +Memory mapped read mode +----------------------- +In this, SPI controller is configured using configuration port and then +controler is switched to memory mapped port for data read. + +Driver +------ +drivers/qspi/ti_qspi.c + - Newly created file which is responsible for configuring the + qspi controller and also for providing the low level api which + is responsible for transferring the datas from host controller + to flash device and vice versa. + +Testing +------- +A seperated file named README.dra_qspi_test has been created which gives all the +details about the commands required to test qspi at u-boot level. diff --git a/doc/SPI/status.txt b/doc/SPI/status.txt new file mode 100644 index 0000000000..13889f5455 --- /dev/null +++ b/doc/SPI/status.txt @@ -0,0 +1,32 @@ +Status on SPI subsystem: +======================= + +SPI COMMAND (common/cmd_sf, cmd_spi): +- + +SPI FLASH (drivers/mtd/spi): +- sf_probe.c: SPI flash probing code. +- sf_ops.c: SPI flash operations code. +- sf.c: SPI flash interface, which interacts controller driver. +- Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing) +- Added memory_mapped support for read operations. +- Common probe support for all supported flash vendors except, ramtron. +- Extended read commands support(dual read, dual IO read) +- Quad Page Program support. +- Quad Read support(quad fast read, quad IO read) +- Dual flash connection topology support(accessing two spi flash memories with single cs) +- Banking support on dual flash connection topology. + +SPI DRIVERS (drivers/spi): +- + +TODO: +- Runtime detection of spi_flash params, SFDP(if possible) +- Add support for multibus build/accessing. +- Need proper cleanups on spi_flash and drivers. + +-- +Jagannadha Sutradharudu Teki +18-09-2013. +07-10-2013. +08-01-2014. diff --git a/doc/device-tree-bindings/ata/intel-sata.txt b/doc/device-tree-bindings/ata/intel-sata.txt new file mode 100644 index 0000000000..5e4da832a3 --- /dev/null +++ b/doc/device-tree-bindings/ata/intel-sata.txt @@ -0,0 +1,26 @@ +Intel Pantherpoint SATA Device Binding +====================================== + +The device tree node which describes the operation of the Intel Pantherpoint +SATA device is as follows: + +Required properties : +- compatible = "intel,pantherpoint-ahci" +- intel,sata-mode : string, one of: + "ahci" : Use AHCI mode (default) + "combined" : Use combined IDE + legacy mode + "plain-ide" : Use plain IDE mode +- intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port, + bit 1=enable second port, etc. +- intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register +- intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register + +Example +------- + +sata { + compatible = "intel,pantherpoint-ahci"; + intel,sata-mode = "ahci"; + intel,sata-port-map = <1>; + intel,sata-port0-gen3-tx = <0x00880a7f>; +}; diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt b/doc/device-tree-bindings/exynos/dwmmc.txt index 566da3b636..694d195916 100644 --- a/doc/device-tree-bindings/exynos/dwmmc.txt +++ b/doc/device-tree-bindings/exynos/dwmmc.txt @@ -1,18 +1,18 @@ -* Exynos 5250 DWC_mobile_storage +* Exynos DWC_mobile_storage -The Exynos 5250 provides DWC_mobile_storage interface which supports +The Exynos provides DWC_mobile_storage interface which supports . Embedded Multimedia Cards (EMMC-version 4.5) . Secure Digital memory (SD mem-version 2.0) . Secure Digital I/O (SDIO-version 3.0) . Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1) -The Exynos 5250 DWC_mobile_storage provides four channels. +The Exynos DWC_mobile_storage provides four channels. SOC specific and Board specific properties are channel specific. Required SoC Specific Properties: - compatible: should be - - samsung,exynos5250-dwmmc: for exynos5250 platforms + - samsung,exynos-dwmmc: for exynos platforms - reg: physical base address of the controller and length of memory mapped region. diff --git a/doc/device-tree-bindings/gpio/gpio-samsung.txt b/doc/device-tree-bindings/gpio/gpio-samsung.txt new file mode 100644 index 0000000000..5375625e8c --- /dev/null +++ b/doc/device-tree-bindings/gpio/gpio-samsung.txt @@ -0,0 +1,41 @@ +Samsung Exynos4 GPIO Controller + +Required properties: +- compatible: Compatible property value should be "samsung,exynos4-gpio>". + +- reg: Physical base address of the controller and length of memory mapped + region. + +- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes + should be the following with values derived from the SoC user manual. + <[phandle of the gpio controller node] + [pin number within the gpio controller] + [mux function] + [flags and pull up/down] + [drive strength]> + + Values for gpio specifier: + - Pin number: is a value between 0 to 7. + - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled. + 1 - Pull Down Enabled. + 3 - Pull Up Enabled. + Bit 16 (0x00010000) - Input is active low. + - Drive Strength: 0 - 1x, + 1 - 3x, + 2 - 2x, + 3 - 4x + +- gpio-controller: Specifies that the node is a gpio controller. +- #address-cells: should be 1. +- #size-cells: should be 1. + +Example: + + gpa0: gpio-controller@11400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "samsung,exynos4-gpio"; + reg = <0x11400000 0x20>; + #gpio-cells = <4>; + gpio-controller; + }; diff --git a/doc/device-tree-bindings/gpio/gpio.txt b/doc/device-tree-bindings/gpio/gpio.txt new file mode 100644 index 0000000000..b9bd1d64cf --- /dev/null +++ b/doc/device-tree-bindings/gpio/gpio.txt @@ -0,0 +1,211 @@ +Specifying GPIO information for devices +============================================ + +1) gpios property +----------------- + +Nodes that makes use of GPIOs should specify them using one or more +properties, each containing a 'gpio-list': + + gpio-list ::= [gpio-list] + single-gpio ::= + gpio-phandle : phandle to gpio controller node + gpio-specifier : Array of #gpio-cells specifying specific gpio + (controller specific) + +GPIO properties should be named "[-]gpios", with being the purpose +of this GPIO for the device. While a non-existent is considered valid +for compatibility reasons (resolving to the "gpios" property), it is not allowed +for new bindings. + +GPIO properties can contain one or more GPIO phandles, but only in exceptional +cases should they contain more than one. If your device uses several GPIOs with +distinct functions, reference each of them under its own property, giving it a +meaningful name. The only case where an array of GPIOs is accepted is when +several GPIOs serve the same function (e.g. a parallel data line). + +The exact purpose of each gpios property must be documented in the device tree +binding of the device. + +The following example could be used to describe GPIO pins used as device enable +and bit-banged data signals: + + gpio1: gpio1 { + gpio-controller + #gpio-cells = <2>; + }; + gpio2: gpio2 { + gpio-controller + #gpio-cells = <1>; + }; + [...] + + enable-gpios = <&gpio2 2>; + data-gpios = <&gpio1 12 0>, + <&gpio1 13 0>, + <&gpio1 14 0>, + <&gpio1 15 0>; + +Note that gpio-specifier length is controller dependent. In the +above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 +only uses one. + +gpio-specifier may encode: bank, pin position inside the bank, +whether pin is open-drain and whether pin is logically inverted. +Exact meaning of each specifier cell is controller specific, and must +be documented in the device tree binding for the device. Use the macros +defined in include/dt-bindings/gpio/gpio.h whenever possible: + +Example of a node using GPIOs: + + node { + enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>; + }; + +GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes +GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. + +1.1) GPIO specifier best practices +---------------------------------- + +A gpio-specifier should contain a flag indicating the GPIO polarity; active- +high or active-low. If it does, the follow best practices should be followed: + +The gpio-specifier's polarity flag should represent the physical level at the +GPIO controller that achieves (or represents, for inputs) a logically asserted +value at the device. The exact definition of logically asserted should be +defined by the binding for the device. If the board inverts the signal between +the GPIO controller and the device, then the gpio-specifier will represent the +opposite physical level than the signal at the device's pin. + +When the device's signal polarity is configurable, the binding for the +device must either: + +a) Define a single static polarity for the signal, with the expectation that +any software using that binding would statically program the device to use +that signal polarity. + +The static choice of polarity may be either: + +a1) (Preferred) Dictated by a binding-specific DT property. + +or: + +a2) Defined statically by the DT binding itself. + +In particular, the polarity cannot be derived from the gpio-specifier, since +that would prevent the DT from separately representing the two orthogonal +concepts of configurable signal polarity in the device, and possible board- +level signal inversion. + +or: + +b) Pick a single option for device signal polarity, and document this choice +in the binding. The gpio-specifier should represent the polarity of the signal +(at the GPIO controller) assuming that the device is configured for this +particular signal polarity choice. If software chooses to program the device +to generate or receive a signal of the opposite polarity, software will be +responsible for correctly interpreting (inverting) the GPIO signal at the GPIO +controller. + +2) gpio-controller nodes +------------------------ + +Every GPIO controller node must contain both an empty "gpio-controller" +property, and a #gpio-cells integer property, which indicates the number of +cells in a gpio-specifier. + +Example of two SOC GPIO banks defined as gpio-controller nodes: + + qe_pio_a: gpio-controller@1400 { + compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; + reg = <0x1400 0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + qe_pio_e: gpio-controller@1460 { + compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; + reg = <0x1460 0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + +2.1) gpio- and pin-controller interaction +----------------------------------------- + +Some or all of the GPIOs provided by a GPIO controller may be routed to pins +on the package via a pin controller. This allows muxing those pins between +GPIO and other functions. + +It is useful to represent which GPIOs correspond to which pins on which pin +controllers. The gpio-ranges property described below represents this, and +contains information structures as follows: + + gpio-range-list ::= [gpio-range-list] + single-gpio-range ::= | + numeric-gpio-range ::= + + named-gpio-range ::= '<0 0>' + gpio-phandle : phandle to pin controller node. + gpio-base : Base GPIO ID in the GPIO controller + pinctrl-base : Base pinctrl pin ID in the pin controller + count : The number of GPIOs/pins in this range + +The "pin controller node" mentioned above must conform to the bindings +described in ../pinctrl/pinctrl-bindings.txt. + +In case named gpio ranges are used (ranges with both and + set to 0), the property gpio-ranges-group-names contains one string +for every single-gpio-range in gpio-ranges: + gpiorange-names-list ::= [gpiorange-names-list] + gpiorange-name : Name of the pingroup associated to the GPIO range in + the respective pin controller. + +Elements of gpiorange-names-list corresponding to numeric ranges contain +the empty string. Elements of gpiorange-names-list corresponding to named +ranges contain the name of a pin group defined in the respective pin +controller. The number of pins/GPIOs in the range is the number of pins in +that pin group. + +Previous versions of this binding required all pin controller nodes that +were referenced by any gpio-ranges property to contain a property named +#gpio-range-cells with value <3>. This requirement is now deprecated. +However, that property may still exist in older device trees for +compatibility reasons, and would still be required even in new device +trees that need to be compatible with older software. + +Example 1: + + qe_pio_e: gpio-controller@1460 { + #gpio-cells = <2>; + compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; + reg = <0x1460 0x18>; + gpio-controller; + gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; + }; + +Here, a single GPIO controller has GPIOs 0..9 routed to pin controller +pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's +pins 50..59. + +Example 2: + + gpio_pio_i: gpio-controller@14B0 { + #gpio-cells = <2>; + compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; + reg = <0x1480 0x18>; + gpio-controller; + gpio-ranges = <&pinctrl1 0 20 10>, + <&pinctrl2 10 0 0>, + <&pinctrl1 15 0 10>, + <&pinctrl2 25 0 0>; + gpio-ranges-group-names = "", + "foo", + "", + "bar"; + }; + +Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO +ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2 +are named "foo" and "bar". diff --git a/doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt b/doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt new file mode 100644 index 0000000000..023c9526e5 --- /dev/null +++ b/doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt @@ -0,0 +1,40 @@ +NVIDIA Tegra GPIO controller + +Required properties: +- compatible : "nvidia,tegra-gpio" +- reg : Physical base address and length of the controller's registers. +- interrupts : The interrupt outputs from the controller. For Tegra20, + there should be 7 interrupts specified, and for Tegra30, there should + be 8 interrupts specified. +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters: + - bit 0 specifies polarity (0 for normal, 1 for inverted) +- gpio-controller : Marks the device node as a GPIO controller. +- #interrupt-cells : Should be 2. + The first cell is the GPIO number. + The second cell is used to specify flags: + bits[3:0] trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + Valid combinations are 1, 2, 3, 4, 8. +- interrupt-controller : Marks the device node as an interrupt controller. + +Example: + +gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 >; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; +}; diff --git a/doc/device-tree-bindings/i2c/i2c.txt b/doc/device-tree-bindings/i2c/i2c.txt new file mode 100644 index 0000000000..ea918dd61d --- /dev/null +++ b/doc/device-tree-bindings/i2c/i2c.txt @@ -0,0 +1,28 @@ +U-Boot I2C +---------- + +U-Boot's I2C model has the concept of an offset within a chip (I2C target +device). The offset can be up to 4 bytes long, but is normally 1 byte, +meaning that offsets from 0 to 255 are supported by the chip. This often +corresponds to register numbers. + +Apart from the controller-specific I2C bindings, U-Boot supports a special +property which allows the chip offset length to be selected. + +Optional properties: +- u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the + default value of 1 is used. + + +Example +------- + +i2c4: i2c@12ca0000 { + cros-ec@1e { + reg = <0x1e>; + compatible = "google,cros-ec"; + i2c-max-frequency = <100000>; + u-boot,i2c-offset-len = <0>; + ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/doc/device-tree-bindings/input/cros-ec-keyb.txt b/doc/device-tree-bindings/input/cros-ec-keyb.txt index 3118276078..0f6355ce39 100644 --- a/doc/device-tree-bindings/input/cros-ec-keyb.txt +++ b/doc/device-tree-bindings/input/cros-ec-keyb.txt @@ -1,45 +1,38 @@ -CROS_EC Keyboard +ChromeOS EC Keyboard -The CROS_EC (Matrix Keyboard Protocol) allows communcation with a secondary -micro used for keyboard, and possible other features. +Google's ChromeOS EC Keyboard is a simple matrix keyboard implemented on +a separate EC (Embedded Controller) device. It provides a message for reading +key scans from the EC. These are then converted into keycodes for processing +by the kernel. -The CROS_EC keyboard uses this protocol to receive key scans and produce input -in U-Boot. +This binding is based on matrix-keymap.txt and extends/modifies it as follows: -Required properties : -- compatible : "google,cros-ec-keyb" -- google,key-rows : Number of key rows -- google,key-columns : Number of key columns +Required properties: +- compatible: "google,cros-ec-keyb" -Optional properties, in addition to those specified by the shared -matrix-keyboard bindings: +Optional properties: +- google,needs-ghost-filter: True to enable a ghost filter for the matrix +keyboard. This is recommended if the EC does not have its own logic or +hardware for this. -- linux,fn-keymap: a second keymap, same specification as the - matrix-keyboard-controller spec but to be used when the KEY_FN modifier - key is pressed. -- google,repeat-delay-ms : delay in milliseconds before repeat starts -- google,repeat-rate-ms : delay between each subsequent key press -- google,ghost-filter : enable ghost filtering for this device -Example, taken from daisy: +Example: cros-ec-keyb { compatible = "google,cros-ec-keyb"; - google,key-rows = <8>; - google,key-columns = <13>; - google,ghost-filter; - google,repeat-delay-ms = <240>; - google,repeat-rate-ms = <30>; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; /* - * Keymap entries take the form of 0xRRCCKKKK where - * RR=Row CC=Column KKKK=Key Code - * The values below are for a US keyboard layout and - * are taken from the Linux driver. Note that the - * 102ND key is not used for US keyboards. - */ + * Keymap entries take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * The values below are for a US keyboard layout and + * are taken from the Linux driver. Note that the + * 102ND key is not used for US keyboards. + */ linux,keymap = < /* CAPSLCK F1 B F10 */ - 0x0001003a 0x0002003c 0x00030030 0x00040044 + 0x0001003a 0x0002003b 0x00030030 0x00040044 /* N = R_ALT ESC */ 0x00060031 0x0008000d 0x000a0064 0x01010001 /* F4 G F7 H */ diff --git a/doc/device-tree-bindings/misc/intel-lpc.txt b/doc/device-tree-bindings/misc/intel-lpc.txt new file mode 100644 index 0000000000..ba6ca9dbc7 --- /dev/null +++ b/doc/device-tree-bindings/misc/intel-lpc.txt @@ -0,0 +1,64 @@ +Intel LPC Device Binding +======================== + +The device tree node which describes the operation of the Intel Low Pin +Count device is as follows: + +Required properties : +- compatible = "intel,lpc" +- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the + ALT_GP_SMI_EN register +- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four + cell pairs can be provided - the first of each pair is the base address and + the second is the size. These are written into the GENx_DEC registers of + the LPC device +- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid + values are: + 0 No effect (default) + 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + 2 SCI (if corresponding GPIO_EN bit is also set) +- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H, + one cell for each. + 0x00 - 0000 = Reserved + 0x01 - 0001 = Reserved + 0x02 - 0010 = Reserved + 0x03 - 0011 = IRQ3 + 0x04 - 0100 = IRQ4 + 0x05 - 0101 = IRQ5 + 0x06 - 0110 = IRQ6 + 0x07 - 0111 = IRQ7 + 0x08 - 1000 = Reserved + 0x09 - 1001 = IRQ9 + 0x0A - 1010 = IRQ10 + 0x0B - 1011 = IRQ11 + 0x0C - 1100 = IRQ12 + 0x0D - 1101 = Reserved + 0x0E - 1110 = IRQ14 + 0x0F - 1111 = IRQ15 + PIRQ[n]_ROUT[7] - PIRQ Routing Control + 0x80 - The PIRQ is not routed. + + +Example +------- + +lpc { + compatible = "intel,lpc"; + #address-cells = <1>; + #size-cells = <1>; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; + + intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b + 0x80 0x80 0x80 0x80>; + /* + * GPI routing + * 0 No effect (default) + * 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is + * also set) + * 2 SCI (if corresponding GPIO_EN bit is also set) + */ + intel,gpi-routing = <0 0 0 0 0 0 0 2 + 1 0 0 0 0 0 0 0>; + /* Enable EC SMI source */ + intel,alt-gp-smi-enable = <0x0100>; +}; diff --git a/doc/device-tree-bindings/mtd/spi/spi-flash.txt b/doc/device-tree-bindings/mtd/spi/spi-flash.txt new file mode 100644 index 0000000000..85522d8011 --- /dev/null +++ b/doc/device-tree-bindings/mtd/spi/spi-flash.txt @@ -0,0 +1,25 @@ +* MTD SPI driver for serial flash chips + +Required properties: +- #address-cells, #size-cells : Must be present if the device has sub-nodes + representing partitions. +- compatible : Should be the manufacturer and the name of the chip. Bear in + mind that the DT binding is not U-Boot-only, but in case of + U-Boot, see spi_flash_params_table table in + drivers/mtd/spi/sf_params.c for the list of supported chips. +- reg : Chip-Select number +- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at + +Optional properties: + - memory-map : Address and size of the flash, if memory mapped. This may + apply to Intel chipsets, which tend to memory-map flash. + +Example: + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + reg = <0>; + spi-max-frequency = <40000000>; + }; diff --git a/doc/device-tree-bindings/power/tps65090.txt b/doc/device-tree-bindings/power/tps65090.txt new file mode 100644 index 0000000000..8e5e0d3910 --- /dev/null +++ b/doc/device-tree-bindings/power/tps65090.txt @@ -0,0 +1,17 @@ +TPS65090 Frontend PMU with Switchmode Charger + +Required Properties: +-compatible: "ti,tps65090-charger" + +Optional Properties: +-ti,enable-low-current-chrg: Enables charging when a low current is detected + while the default logic is to stop charging. + +This node is a subnode of the tps65090 PMIC. + +Example: + + tps65090-charger { + compatible = "ti,tps65090-charger"; + ti,enable-low-current-chrg; + }; diff --git a/doc/device-tree-bindings/regulator/tps65090.txt b/doc/device-tree-bindings/regulator/tps65090.txt new file mode 100644 index 0000000000..313a60ba61 --- /dev/null +++ b/doc/device-tree-bindings/regulator/tps65090.txt @@ -0,0 +1,122 @@ +TPS65090 regulators + +Required properties: +- compatible: "ti,tps65090" +- reg: I2C slave address +- interrupts: the interrupt outputs of the controller +- regulators: A node that houses a sub-node for each regulator within the + device. Each sub-node is identified using the node's name, with valid + values listed below. The content of each sub-node is defined by the + standard binding for regulators; see regulator.txt. + dcdc[1-3], fet[1-7] and ldo[1-2] respectively. +- vsys[1-3]-supply: The input supply for DCDC[1-3] respectively. +- infet[1-7]-supply: The input supply for FET[1-7] respectively. +- vsys-l[1-2]-supply: The input supply for LDO[1-2] respectively. + +Optional properties: +- ti,enable-ext-control: This is applicable for DCDC1, DCDC2 and DCDC3. + If DCDCs are externally controlled then this property should be there. +- "dcdc-ext-control-gpios: This is applicable for DCDC1, DCDC2 and DCDC3. + If DCDCs are externally controlled and if it is from GPIO then GPIO + number should be provided. If it is externally controlled and no GPIO + entry then driver will just configure this rails as external control + and will not provide any enable/disable APIs. + +Each regulator is defined using the standard binding for regulators. + +Example: + + tps65090@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + interrupts = <0 88 0x4>; + + vsys1-supply = <&some_reg>; + vsys2-supply = <&some_reg>; + vsys3-supply = <&some_reg>; + infet1-supply = <&some_reg>; + infet2-supply = <&some_reg>; + infet3-supply = <&some_reg>; + infet4-supply = <&some_reg>; + infet5-supply = <&some_reg>; + infet6-supply = <&some_reg>; + infet7-supply = <&some_reg>; + vsys_l1-supply = <&some_reg>; + vsys_l2-supply = <&some_reg>; + + regulators { + dcdc1 { + regulator-name = "dcdc1"; + regulator-boot-on; + regulator-always-on; + ti,enable-ext-control; + dcdc-ext-control-gpios = <&gpio 10 0>; + }; + + dcdc2 { + regulator-name = "dcdc2"; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3 { + regulator-name = "dcdc3"; + regulator-boot-on; + regulator-always-on; + }; + + fet1 { + regulator-name = "fet1"; + regulator-boot-on; + regulator-always-on; + }; + + fet2 { + regulator-name = "fet2"; + regulator-boot-on; + regulator-always-on; + }; + + fet3 { + regulator-name = "fet3"; + regulator-boot-on; + regulator-always-on; + }; + + fet4 { + regulator-name = "fet4"; + regulator-boot-on; + regulator-always-on; + }; + + fet5 { + regulator-name = "fet5"; + regulator-boot-on; + regulator-always-on; + }; + + fet6 { + regulator-name = "fet6"; + regulator-boot-on; + regulator-always-on; + }; + + fet7 { + regulator-name = "fet7"; + regulator-boot-on; + regulator-always-on; + }; + + ldo1 { + regulator-name = "ldo1"; + regulator-boot-on; + regulator-always-on; + }; + + ldo2 { + regulator-name = "ldo2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; diff --git a/doc/device-tree-bindings/serial/ns16550.txt b/doc/device-tree-bindings/serial/ns16550.txt new file mode 100644 index 0000000000..ef0b9aee6d --- /dev/null +++ b/doc/device-tree-bindings/serial/ns16550.txt @@ -0,0 +1,10 @@ +NS16550 UART + +This UART driver supports many chip variants and is used in mamy SoCs. + +Required properties: +- compatible: "ns16550" or "nvidia,tegra20-uart" +- reg: start address and size of registers +- reg-shift: shift value indicating register size: 0=byte, 1=16bit,2=32bit etc. +- clock-frequency: input clock frequency for the UART (used to calculate the + baud rate divisor) diff --git a/doc/device-tree-bindings/serial/sandbox-serial.txt b/doc/device-tree-bindings/serial/sandbox-serial.txt new file mode 100644 index 0000000000..f429c90421 --- /dev/null +++ b/doc/device-tree-bindings/serial/sandbox-serial.txt @@ -0,0 +1,13 @@ +Sandbox serial + +The sandbox serial device is an emulated device which displays its output +on the host machine's console, and accepts input from its keyboard. + +Required properties: + compatible: "sandbox,serial" + +Optional properties: + sandbox,text-colour: If present, this is the colour of the console text. + Supported values are: + "black", "red", "green", "yellow", "blue", "megenta", "cyan", + "white" diff --git a/doc/device-tree-bindings/spi/soft-spi.txt b/doc/device-tree-bindings/spi/soft-spi.txt new file mode 100644 index 0000000000..d09c1a5076 --- /dev/null +++ b/doc/device-tree-bindings/spi/soft-spi.txt @@ -0,0 +1,34 @@ +Soft SPI + +The soft SPI bus implementation allows the use of GPIO pins to simulate a +SPI bus. No SPI host is required for this to work. The down-side is that the +performance will typically be much lower than a real SPI bus. + +The soft SPI node requires the following properties: + +compatible: "u-boot,soft-spi" +soft_spi_cs: GPIO number to use for SPI chip select (output) +soft_spi_sclk: GPIO number to use for SPI clock (output) +soft_spi_mosi: GPIO number to use for SPI MOSI line (output) +soft_spi_miso GPIO number to use for SPI MISO line (input) +spi-delay-us: Number of microseconds of delay between each CS transition + +The GPIOs should be specified as required by the GPIO controller referenced. +The first cell holds the phandle of the controller and the second cell +typically holds the GPIO number. + + +Example: + + soft-spi { + compatible = "u-boot,soft-spi"; + cs-gpio = <&gpio 235 0>; /* Y43 */ + sclk-gpio = <&gpio 225 0>; /* Y31 */ + mosi-gpio = <&gpio 227 0>; /* Y33 */ + miso-gpio = <&gpio 224 0>; /* Y30 */ + spi-delay-us = <1>; + #address-cells = <1>; + #size-cells = <0>; + cs@0 { + }; + }; diff --git a/doc/device-tree-bindings/spi/spi-bus.txt b/doc/device-tree-bindings/spi/spi-bus.txt new file mode 100644 index 0000000000..5c8720a820 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-bus.txt @@ -0,0 +1,94 @@ +SPI (Serial Peripheral Interface) busses + +SPI busses can be described with a node for the SPI master device +and a set of child nodes for each SPI slave on the bus. For this +discussion, it is assumed that the system's SPI controller is in +SPI master mode. This binding does not describe SPI controllers +in slave mode. + +The SPI master node requires the following properties: +- #address-cells - number of cells required to define a chip select + address on the SPI bus. +- #size-cells - should be zero. +- compatible - name of SPI bus controller following generic names + recommended practice. +- cs-gpios - (optional) gpios chip select. +No other properties are required in the SPI bus node. It is assumed +that a driver for an SPI bus device will understand that it is an SPI bus. +However, the binding does not attempt to define the specific method for +assigning chip select numbers. Since SPI chip select configuration is +flexible and non-standardized, it is left out of this binding with the +assumption that board specific platform code will be used to manage +chip selects. Individual drivers can define additional properties to +support describing the chip select layout. + +Optional property: +- num-cs : total number of chipselects + +If cs-gpios is used the number of chip select will automatically increased +with max(cs-gpios > hw cs) + +So if for example the controller has 2 CS lines, and the cs-gpios +property looks like this: + +cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; + +Then it should be configured so that num_chipselect = 4 with the +following mapping: + +cs0 : &gpio1 0 0 +cs1 : native +cs2 : &gpio1 1 0 +cs3 : &gpio1 2 0 + +SPI slave nodes must be children of the SPI master node and can +contain the following properties. +- reg - (required) chip select address of device. +- compatible - (required) name of SPI device following generic names + recommended practice +- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz +- spi-cpol - (optional) Empty property indicating device requires + inverse clock polarity (CPOL) mode +- spi-cpha - (optional) Empty property indicating device requires + shifted clock phase (CPHA) mode +- spi-cs-high - (optional) Empty property indicating device requires + chip select active high +- spi-3wire - (optional) Empty property indicating device requires + 3-wire mode. +- spi-tx-bus-width - (optional) The bus width(number of data wires) that + used for MOSI. Defaults to 1 if not present. +- spi-rx-bus-width - (optional) The bus width(number of data wires) that + used for MISO. Defaults to 1 if not present. +- spi-half-duplex - (optional) Indicates that the SPI bus should wait for + a header byte before reading data from the slave. + +Some SPI controllers and devices support Dual and Quad SPI transfer mode. +It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD). +Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is +only 1(SINGLE), 2(DUAL) and 4(QUAD). +Dual/Quad mode is not allowed when 3-wire mode is used. + +If a gpio chipselect is used for the SPI slave the gpio number will be passed +via the cs_gpio + +SPI example for an MPC5200 SPI bus: + spi@f00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; + reg = <0xf00 0x20>; + interrupts = <2 13 0 2 14 0>; + interrupt-parent = <&mpc5200_pic>; + + ethernet-switch@0 { + compatible = "micrel,ks8995m"; + spi-max-frequency = <1000000>; + reg = <0>; + }; + + codec@1 { + compatible = "ti,tlv320aic26"; + spi-max-frequency = <100000>; + reg = <1>; + }; + }; diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index bb7441cbbe..dc4e44fbc5 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -55,6 +55,12 @@ Board(panel specific): samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL) samsung,sclk-div: parent_clock/source_clock ratio samsung,dual-lcd-enabled: 1 if you support two LCD, else 0 + samsung,disable-sysmmu: Define this if you want to disable FIMD sysmmu. + (needed for Exynos5420 and newer versions) + Add the required FIMD sysmmu nodes to be + disabled with compatible string + "samsung,sysmmu-v3.3", with a "reg" property + holding the register address of FIMD sysmmu. Example: SOC specific part: diff --git a/doc/device-tree-bindings/video/exynos_mipi_dsi.txt b/doc/device-tree-bindings/video/exynos_mipi_dsi.txt new file mode 100644 index 0000000000..4938ea01ec --- /dev/null +++ b/doc/device-tree-bindings/video/exynos_mipi_dsi.txt @@ -0,0 +1,82 @@ +Exynos MIPI-DSIM Controller +========================= + +Required properties: +SOC specific: + compatible: should be "samsung,exynos-mipi-dsi" + reg: Base address of MIPI-DSIM IP. + +Board specific: + samsung,dsim-config-e-interface: interface to be used (RGB interface + for main display or CPU interface for main or sub display). + samsung,dsim-config-e-virtual-ch: virtual channel number that main + or sub display uses. + samsung,dsim-config-e-pixel-format: pixel stream format for main + or sub display. + samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode. + in Non-burst mode, RGB data area is filled with RGB data and + NULL packets, according to input bandwidth of RGB interface. + samsung,dsim-config-e-no-data-lane: data lane count used by Master. + samsung,dsim-config-e-byte-clk: select byte clock source. + It must be DSIM_PLL_OUT_DIV8. + DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported. + samsung,dsim-config-hfp: HFP disable mode. + If set, DSI master ignores HFP area in VIDEO mode. + In command mode, this variable is ignored. + samsung,dsim-config-p: P value for PMS setting. + samsung,dsim-config-m: M value for PMS setting. + samsung,dsim-config-s: S value for PMS setting. + samsung,dsim-config-pll-stable-time: the PLL Timer for stability + of the ganerated clock. + samsung,dsim-config-esc-clk: escape clock frequency for getting + the escape clock prescaler value. + samsung,dsim-config-stop-holding-cnt: the interval value between + transmitting read packet (or write "set_tear_on" command) + and BTA request. After transmitting read packet or write + "set_tear_on" command, BTA requests to D-PHY automatically. + This counter value specifies the interval between them. + samsung,dsim-config-bta-timeout: the timer for BTA. This register + specifies time out from BTA request to change the direction + with respect to Tx escape clock. + samsung,dsim-config-rx-timeout: the timer for LP Rx mode timeout. + this register specifies time out on how long RxValid deasserts, + after RxLpdt asserts with respect to Tx escape clock. + - RxValid specifies Rx data valid indicator. + - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode + - RxValid and RxLpdt specifies signal from D-PHY. + samsung,dsim-device-name: name of the device. + samsung,dsim-device-id: unique device id. + samsung,dsim-device-bus_id: bus id for identifing connected bus + and this bus id should be same as id of mipi_dsim_device. + +Optional properties: + samsung,dsim-device-reverse-panel: reverse panel. + +Example: + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; diff --git a/doc/device-tree-bindings/video/intel-gma.txt b/doc/device-tree-bindings/video/intel-gma.txt new file mode 100644 index 0000000000..914be4fedd --- /dev/null +++ b/doc/device-tree-bindings/video/intel-gma.txt @@ -0,0 +1,40 @@ +Intel GMA Bindings +================== + +This is the Intel Graphics Media Accelerator. This binding supports selection +of display parameters only. + + +Required properties: + - compatible : "intel,gma"; + +Optional properties: + - intel,dp-hotplug : values for digital port hotplug, one cell per value for + ports B, C and D + - intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D + - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms) + + The following delays are in units of 0.1ms: + - intel,panel-power-up-delay : T1+T2 time sequence + - intel,panel-power-down-delay : T3 time sequence + - intel,panel-power-backlight-on-delay : T5 time sequence + - intel,panel-power-backlight-off-delay : Tx time sequence + + - intel,cpu-backlight : Value for CPU Backlight PWM + - intel,pch-backlight : Value for PCH Backlight PWM + +Example +------- + +gma { + compatible = "intel,gma"; + intel,dp_hotplug = <0 0 0x06>; + intel,panel-port-select = <1>; + intel,panel-power-cycle-delay = <6>; + intel,panel-power-up-delay = <2000>; + intel,panel-power-down-delay = <500>; + intel,panel-power-backlight-on-delay = <2000>; + intel,panel-power-backlight-off-delay = <2000>; + intel,cpu-backlight = <0x00000200>; + intel,pch-backlight = <0x04000000>; +}; diff --git a/doc/device-tree-bindings/video/sandbox-fb.txt b/doc/device-tree-bindings/video/sandbox-fb.txt new file mode 100644 index 0000000000..eb91b30e3f --- /dev/null +++ b/doc/device-tree-bindings/video/sandbox-fb.txt @@ -0,0 +1,13 @@ +Sandbox LCD +=========== + +This uses the displaymode.txt binding except that only xres and yres are +required properties. + +Example: + + lcd { + compatible = "sandbox,lcd-sdl"; + xres = <800>; + yres = <600>; + }; diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt new file mode 100644 index 0000000000..f83264d615 --- /dev/null +++ b/doc/driver-model/README.txt @@ -0,0 +1,799 @@ +Driver Model +============ + +This README contains high-level information about driver model, a unified +way of declaring and accessing drivers in U-Boot. The original work was done +by: + + Marek Vasut + Pavel Herrmann + Viktor Křivák + Tomas Hlavacek + +This has been both simplified and extended into the current implementation +by: + + Simon Glass + + +Terminology +----------- + +Uclass - a group of devices which operate in the same way. A uclass provides + a way of accessing individual devices within the group, but always + using the same interface. For example a GPIO uclass provides + operations for get/set value. An I2C uclass may have 10 I2C ports, + 4 with one driver, and 6 with another. + +Driver - some code which talks to a peripheral and presents a higher-level + interface to it. + +Device - an instance of a driver, tied to a particular port or peripheral. + + +How to try it +------------- + +Build U-Boot sandbox and run it: + + make sandbox_defconfig + make + ./u-boot -d u-boot.dtb + + (type 'reset' to exit U-Boot) + + +There is a uclass called 'demo'. This uclass handles +saying hello, and reporting its status. There are two drivers in this +uclass: + + - simple: Just prints a message for hello, doesn't implement status + - shape: Prints shapes and reports number of characters printed as status + +The demo class is pretty simple, but not trivial. The intention is that it +can be used for testing, so it will implement all driver model features and +provide good code coverage of them. It does have multiple drivers, it +handles parameter data and platdata (data which tells the driver how +to operate on a particular platform) and it uses private driver data. + +To try it, see the example session below: + +=>demo hello 1 +Hello '@' from 07981110: red 4 +=>demo status 2 +Status: 0 +=>demo hello 2 +g +r@ +e@@ +e@@@ +n@@@@ +g@@@@@ +=>demo status 2 +Status: 21 +=>demo hello 4 ^ + y^^^ + e^^^^^ +l^^^^^^^ +l^^^^^^^ + o^^^^^ + w^^^ +=>demo status 4 +Status: 36 +=> + + +Running the tests +----------------- + +The intent with driver model is that the core portion has 100% test coverage +in sandbox, and every uclass has its own test. As a move towards this, tests +are provided in test/dm. To run them, try: + + ./test/dm/test-dm.sh + +You should see something like this: + + <...U-Boot banner...> + Running 29 driver model tests + Test: dm_test_autobind + Test: dm_test_autoprobe + Test: dm_test_bus_children + Device 'd-test': seq 3 is in use by 'b-test' + Device 'c-test@0': seq 0 is in use by 'a-test' + Device 'c-test@1': seq 1 is in use by 'd-test' + Test: dm_test_bus_children_funcs + Test: dm_test_bus_children_iterators + Test: dm_test_bus_parent_data + Test: dm_test_bus_parent_ops + Test: dm_test_children + Test: dm_test_fdt + Device 'd-test': seq 3 is in use by 'b-test' + Test: dm_test_fdt_offset + Test: dm_test_fdt_pre_reloc + Test: dm_test_fdt_uclass_seq + Device 'd-test': seq 3 is in use by 'b-test' + Device 'a-test': seq 0 is in use by 'd-test' + Test: dm_test_gpio + extra-gpios: get_value: error: gpio b5 not reserved + Test: dm_test_gpio_anon + Test: dm_test_gpio_copy + Test: dm_test_gpio_leak + extra-gpios: get_value: error: gpio b5 not reserved + Test: dm_test_gpio_requestf + Test: dm_test_leak + Test: dm_test_lifecycle + Test: dm_test_operations + Test: dm_test_ordering + Test: dm_test_platdata + Test: dm_test_pre_reloc + Test: dm_test_remove + Test: dm_test_spi_find + Invalid chip select 0:0 (err=-19) + SF: Failed to get idcodes + Device 'name-emul': seq 0 is in use by 'name-emul' + SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB + Test: dm_test_spi_flash + 2097152 bytes written in 0 ms + SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB + SPI flash test: + 0 erase: 0 ticks, 65536000 KiB/s 524288.000 Mbps + 1 check: 0 ticks, 65536000 KiB/s 524288.000 Mbps + 2 write: 0 ticks, 65536000 KiB/s 524288.000 Mbps + 3 read: 0 ticks, 65536000 KiB/s 524288.000 Mbps + Test passed + 0 erase: 0 ticks, 65536000 KiB/s 524288.000 Mbps + 1 check: 0 ticks, 65536000 KiB/s 524288.000 Mbps + 2 write: 0 ticks, 65536000 KiB/s 524288.000 Mbps + 3 read: 0 ticks, 65536000 KiB/s 524288.000 Mbps + Test: dm_test_spi_xfer + SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB + Test: dm_test_uclass + Test: dm_test_uclass_before_ready + Failures: 0 + + +What is going on? +----------------- + +Let's start at the top. The demo command is in common/cmd_demo.c. It does +the usual command processing and then: + + struct udevice *demo_dev; + + ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev); + +UCLASS_DEMO means the class of devices which implement 'demo'. Other +classes might be MMC, or GPIO, hashing or serial. The idea is that the +devices in the class all share a particular way of working. The class +presents a unified view of all these devices to U-Boot. + +This function looks up a device for the demo uclass. Given a device +number we can find the device because all devices have registered with +the UCLASS_DEMO uclass. + +The device is automatically activated ready for use by uclass_get_device(). + +Now that we have the device we can do things like: + + return demo_hello(demo_dev, ch); + +This function is in the demo uclass. It takes care of calling the 'hello' +method of the relevant driver. Bearing in mind that there are two drivers, +this particular device may use one or other of them. + +The code for demo_hello() is in drivers/demo/demo-uclass.c: + +int demo_hello(struct udevice *dev, int ch) +{ + const struct demo_ops *ops = device_get_ops(dev); + + if (!ops->hello) + return -ENOSYS; + + return ops->hello(dev, ch); +} + +As you can see it just calls the relevant driver method. One of these is +in drivers/demo/demo-simple.c: + +static int simple_hello(struct udevice *dev, int ch) +{ + const struct dm_demo_pdata *pdata = dev_get_platdata(dev); + + printf("Hello from %08x: %s %d\n", map_to_sysmem(dev), + pdata->colour, pdata->sides); + + return 0; +} + + +So that is a trip from top (command execution) to bottom (driver action) +but it leaves a lot of topics to address. + + +Declaring Drivers +----------------- + +A driver declaration looks something like this (see +drivers/demo/demo-shape.c): + +static const struct demo_ops shape_ops = { + .hello = shape_hello, + .status = shape_status, +}; + +U_BOOT_DRIVER(demo_shape_drv) = { + .name = "demo_shape_drv", + .id = UCLASS_DEMO, + .ops = &shape_ops, + .priv_data_size = sizeof(struct shape_data), +}; + + +This driver has two methods (hello and status) and requires a bit of +private data (accessible through dev_get_priv(dev) once the driver has +been probed). It is a member of UCLASS_DEMO so will register itself +there. + +In U_BOOT_DRIVER it is also possible to specify special methods for bind +and unbind, and these are called at appropriate times. For many drivers +it is hoped that only 'probe' and 'remove' will be needed. + +The U_BOOT_DRIVER macro creates a data structure accessible from C, +so driver model can find the drivers that are available. + +The methods a device can provide are documented in the device.h header. +Briefly, they are: + + bind - make the driver model aware of a device (bind it to its driver) + unbind - make the driver model forget the device + ofdata_to_platdata - convert device tree data to platdata - see later + probe - make a device ready for use + remove - remove a device so it cannot be used until probed again + +The sequence to get a device to work is bind, ofdata_to_platdata (if using +device tree) and probe. + + +Platform Data +------------- + +Platform data is like Linux platform data, if you are familiar with that. +It provides the board-specific information to start up a device. + +Why is this information not just stored in the device driver itself? The +idea is that the device driver is generic, and can in principle operate on +any board that has that type of device. For example, with modern +highly-complex SoCs it is common for the IP to come from an IP vendor, and +therefore (for example) the MMC controller may be the same on chips from +different vendors. It makes no sense to write independent drivers for the +MMC controller on each vendor's SoC, when they are all almost the same. +Similarly, we may have 6 UARTs in an SoC, all of which are mostly the same, +but lie at different addresses in the address space. + +Using the UART example, we have a single driver and it is instantiated 6 +times by supplying 6 lots of platform data. Each lot of platform data +gives the driver name and a pointer to a structure containing information +about this instance - e.g. the address of the register space. It may be that +one of the UARTS supports RS-485 operation - this can be added as a flag in +the platform data, which is set for this one port and clear for the rest. + +Think of your driver as a generic piece of code which knows how to talk to +a device, but needs to know where it is, any variant/option information and +so on. Platform data provides this link between the generic piece of code +and the specific way it is bound on a particular board. + +Examples of platform data include: + + - The base address of the IP block's register space + - Configuration options, like: + - the SPI polarity and maximum speed for a SPI controller + - the I2C speed to use for an I2C device + - the number of GPIOs available in a GPIO device + +Where does the platform data come from? It is either held in a structure +which is compiled into U-Boot, or it can be parsed from the Device Tree +(see 'Device Tree' below). + +For an example of how it can be compiled in, see demo-pdata.c which +sets up a table of driver names and their associated platform data. +The data can be interpreted by the drivers however they like - it is +basically a communication scheme between the board-specific code and +the generic drivers, which are intended to work on any board. + +Drivers can access their data via dev->info->platdata. Here is +the declaration for the platform data, which would normally appear +in the board file. + + static const struct dm_demo_cdata red_square = { + .colour = "red", + .sides = 4. + }; + static const struct driver_info info[] = { + { + .name = "demo_shape_drv", + .platdata = &red_square, + }, + }; + + demo1 = driver_bind(root, &info[0]); + + +Device Tree +----------- + +While platdata is useful, a more flexible way of providing device data is +by using device tree. With device tree we replace the above code with the +following device tree fragment: + + red-square { + compatible = "demo-shape"; + colour = "red"; + sides = <4>; + }; + +This means that instead of having lots of U_BOOT_DEVICE() declarations in +the board file, we put these in the device tree. This approach allows a lot +more generality, since the same board file can support many types of boards +(e,g. with the same SoC) just by using different device trees. An added +benefit is that the Linux device tree can be used, thus further simplifying +the task of board-bring up either for U-Boot or Linux devs (whoever gets to +the board first!). + +The easiest way to make this work it to add a few members to the driver: + + .platdata_auto_alloc_size = sizeof(struct dm_test_pdata), + .ofdata_to_platdata = testfdt_ofdata_to_platdata, + +The 'auto_alloc' feature allowed space for the platdata to be allocated +and zeroed before the driver's ofdata_to_platdata() method is called. The +ofdata_to_platdata() method, which the driver write supplies, should parse +the device tree node for this device and place it in dev->platdata. Thus +when the probe method is called later (to set up the device ready for use) +the platform data will be present. + +Note that both methods are optional. If you provide an ofdata_to_platdata +method then it will be called first (during activation). If you provide a +probe method it will be called next. See Driver Lifecycle below for more +details. + +If you don't want to have the platdata automatically allocated then you +can leave out platdata_auto_alloc_size. In this case you can use malloc +in your ofdata_to_platdata (or probe) method to allocate the required memory, +and you should free it in the remove method. + +The driver model tree is intended to mirror that of the device tree. The +root driver is at device tree offset 0 (the root node, '/'), and its +children are the children of the root node. + + +Declaring Uclasses +------------------ + +The demo uclass is declared like this: + +U_BOOT_CLASS(demo) = { + .id = UCLASS_DEMO, +}; + +It is also possible to specify special methods for probe, etc. The uclass +numbering comes from include/dm/uclass.h. To add a new uclass, add to the +end of the enum there, then declare your uclass as above. + + +Device Sequence Numbers +----------------------- + +U-Boot numbers devices from 0 in many situations, such as in the command +line for I2C and SPI buses, and the device names for serial ports (serial0, +serial1, ...). Driver model supports this numbering and permits devices +to be locating by their 'sequence'. This numbering uniquely identifies a +device in its uclass, so no two devices within a particular uclass can have +the same sequence number. + +Sequence numbers start from 0 but gaps are permitted. For example, a board +may have I2C buses 1, 4, 5 but no 0, 2 or 3. The choice of how devices are +numbered is up to a particular board, and may be set by the SoC in some +cases. While it might be tempting to automatically renumber the devices +where there are gaps in the sequence, this can lead to confusion and is +not the way that U-Boot works. + +Each device can request a sequence number. If none is required then the +device will be automatically allocated the next available sequence number. + +To specify the sequence number in the device tree an alias is typically +used. Make sure that the uclass has the DM_UC_FLAG_SEQ_ALIAS flag set. + +aliases { + serial2 = "/serial@22230000"; +}; + +This indicates that in the uclass called "serial", the named node +("/serial@22230000") will be given sequence number 2. Any command or driver +which requests serial device 2 will obtain this device. + +More commonly you can use node references, which expand to the full path: + +aliases { + serial2 = &serial_2; +}; +... +serial_2: serial@22230000 { +... +}; + +The alias resolves to the same string in this case, but this version is +easier to read. + +Device sequence numbers are resolved when a device is probed. Before then +the sequence number is only a request which may or may not be honoured, +depending on what other devices have been probed. However the numbering is +entirely under the control of the board author so a conflict is generally +an error. + + +Bus Drivers +----------- + +A common use of driver model is to implement a bus, a device which provides +access to other devices. Example of buses include SPI and I2C. Typically +the bus provides some sort of transport or translation that makes it +possible to talk to the devices on the bus. + +Driver model provides some useful features to help with implementing buses. +Firstly, a bus can request that its children store some 'parent data' which +can be used to keep track of child state. Secondly, the bus can define +methods which are called when a child is probed or removed. This is similar +to the methods the uclass driver provides. Thirdly, per-child platform data +can be provided to specify things like the child's address on the bus. This +persists across child probe()/remove() cycles. + +For consistency and ease of implementation, the bus uclass can specify the +per-child platform data, so that it can be the same for all children of buses +in that uclass. There are also uclass methods which can be called when +children are bound and probed. + +Here an explanation of how a bus fits with a uclass may be useful. Consider +a USB bus with several devices attached to it, each from a different (made +up) uclass: + + xhci_usb (UCLASS_USB) + eth (UCLASS_ETHERNET) + camera (UCLASS_CAMERA) + flash (UCLASS_FLASH_STORAGE) + +Each of the devices is connected to a different address on the USB bus. +The bus device wants to store this address and some other information such +as the bus speed for each device. + +To achieve this, the bus device can use dev->parent_platdata in each of its +three children. This can be auto-allocated if the bus driver (or bus uclass) +has a non-zero value for per_child_platdata_auto_alloc_size. If not, then +the bus device or uclass can allocate the space itself before the child +device is probed. + +Also the bus driver can define the child_pre_probe() and child_post_remove() +methods to allow it to do some processing before the child is activated or +after it is deactivated. + +Similarly the bus uclass can define the child_post_bind() method to obtain +the per-child platform data from the device tree and set it up for the child. +The bus uclass can also provide a child_pre_probe() method. Very often it is +the bus uclass that controls these features, since it avoids each driver +having to do the same processing. Of course the driver can still tweak and +override these activities. + +Note that the information that controls this behaviour is in the bus's +driver, not the child's. In fact it is possible that child has no knowledge +that it is connected to a bus. The same child device may even be used on two +different bus types. As an example. the 'flash' device shown above may also +be connected on a SATA bus or standalone with no bus: + + xhci_usb (UCLASS_USB) + flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by USB bus + + sata (UCLASS_SATA) + flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by SATA bus + + flash (UCLASS_FLASH_STORAGE) - no parent data/methods (not on a bus) + +Above you can see that the driver for xhci_usb/sata controls the child's +bus methods. In the third example the device is not on a bus, and therefore +will not have these methods at all. Consider the case where the flash +device defines child methods. These would be used for *its* children, and +would be quite separate from the methods defined by the driver for the bus +that the flash device is connetced to. The act of attaching a device to a +parent device which is a bus, causes the device to start behaving like a +bus device, regardless of its own views on the matter. + +The uclass for the device can also contain data private to that uclass. +But note that each device on the bus may be a memeber of a different +uclass, and this data has nothing to do with the child data for each child +on the bus. It is the bus' uclass that controls the child with respect to +the bus. + + +Driver Lifecycle +---------------- + +Here are the stages that a device goes through in driver model. Note that all +methods mentioned here are optional - e.g. if there is no probe() method for +a device then it will not be called. A simple device may have very few +methods actually defined. + +1. Bind stage + +A device and its driver are bound using one of these two methods: + + - Scan the U_BOOT_DEVICE() definitions. U-Boot It looks up the +name specified by each, to find the appropriate driver. It then calls +device_bind() to create a new device and bind' it to its driver. This will +call the device's bind() method. + + - Scan through the device tree definitions. U-Boot looks at top-level +nodes in the the device tree. It looks at the compatible string in each node +and uses the of_match part of the U_BOOT_DRIVER() structure to find the +right driver for each node. It then calls device_bind() to bind the +newly-created device to its driver (thereby creating a device structure). +This will also call the device's bind() method. + +At this point all the devices are known, and bound to their drivers. There +is a 'struct udevice' allocated for all devices. However, nothing has been +activated (except for the root device). Each bound device that was created +from a U_BOOT_DEVICE() declaration will hold the platdata pointer specified +in that declaration. For a bound device created from the device tree, +platdata will be NULL, but of_offset will be the offset of the device tree +node that caused the device to be created. The uclass is set correctly for +the device. + +The device's bind() method is permitted to perform simple actions, but +should not scan the device tree node, not initialise hardware, nor set up +structures or allocate memory. All of these tasks should be left for +the probe() method. + +Note that compared to Linux, U-Boot's driver model has a separate step of +probe/remove which is independent of bind/unbind. This is partly because in +U-Boot it may be expensive to probe devices and we don't want to do it until +they are needed, or perhaps until after relocation. + +2. Activation/probe + +When a device needs to be used, U-Boot activates it, by following these +steps (see device_probe()): + + a. If priv_auto_alloc_size is non-zero, then the device-private space + is allocated for the device and zeroed. It will be accessible as + dev->priv. The driver can put anything it likes in there, but should use + it for run-time information, not platform data (which should be static + and known before the device is probed). + + b. If platdata_auto_alloc_size is non-zero, then the platform data space + is allocated. This is only useful for device tree operation, since + otherwise you would have to specific the platform data in the + U_BOOT_DEVICE() declaration. The space is allocated for the device and + zeroed. It will be accessible as dev->platdata. + + c. If the device's uclass specifies a non-zero per_device_auto_alloc_size, + then this space is allocated and zeroed also. It is allocated for and + stored in the device, but it is uclass data. owned by the uclass driver. + It is possible for the device to access it. + + d. If the device's immediate parent specifies a per_child_auto_alloc_size + then this space is allocated. This is intended for use by the parent + device to keep track of things related to the child. For example a USB + flash stick attached to a USB host controller would likely use this + space. The controller can hold information about the USB state of each + of its children. + + e. All parent devices are probed. It is not possible to activate a device + unless its predecessors (all the way up to the root device) are activated. + This means (for example) that an I2C driver will require that its bus + be activated. + + f. The device's sequence number is assigned, either the requested one + (assuming no conflicts) or the next available one if there is a conflict + or nothing particular is requested. + + g. If the driver provides an ofdata_to_platdata() method, then this is + called to convert the device tree data into platform data. This should + do various calls like fdtdec_get_int(gd->fdt_blob, dev->of_offset, ...) + to access the node and store the resulting information into dev->platdata. + After this point, the device works the same way whether it was bound + using a device tree node or U_BOOT_DEVICE() structure. In either case, + the platform data is now stored in the platdata structure. Typically you + will use the platdata_auto_alloc_size feature to specify the size of the + platform data structure, and U-Boot will automatically allocate and zero + it for you before entry to ofdata_to_platdata(). But if not, you can + allocate it yourself in ofdata_to_platdata(). Note that it is preferable + to do all the device tree decoding in ofdata_to_platdata() rather than + in probe(). (Apart from the ugliness of mixing configuration and run-time + data, one day it is possible that U-Boot will cache platformat data for + devices which are regularly de/activated). + + h. The device's probe() method is called. This should do anything that + is required by the device to get it going. This could include checking + that the hardware is actually present, setting up clocks for the + hardware and setting up hardware registers to initial values. The code + in probe() can access: + + - platform data in dev->platdata (for configuration) + - private data in dev->priv (for run-time state) + - uclass data in dev->uclass_priv (for things the uclass stores + about this device) + + Note: If you don't use priv_auto_alloc_size then you will need to + allocate the priv space here yourself. The same applies also to + platdata_auto_alloc_size. Remember to free them in the remove() method. + + i. The device is marked 'activated' + + j. The uclass's post_probe() method is called, if one exists. This may + cause the uclass to do some housekeeping to record the device as + activated and 'known' by the uclass. + +3. Running stage + +The device is now activated and can be used. From now until it is removed +all of the above structures are accessible. The device appears in the +uclass's list of devices (so if the device is in UCLASS_GPIO it will appear +as a device in the GPIO uclass). This is the 'running' state of the device. + +4. Removal stage + +When the device is no-longer required, you can call device_remove() to +remove it. This performs the probe steps in reverse: + + a. The uclass's pre_remove() method is called, if one exists. This may + cause the uclass to do some housekeeping to record the device as + deactivated and no-longer 'known' by the uclass. + + b. All the device's children are removed. It is not permitted to have + an active child device with a non-active parent. This means that + device_remove() is called for all the children recursively at this point. + + c. The device's remove() method is called. At this stage nothing has been + deallocated so platform data, private data and the uclass data will all + still be present. This is where the hardware can be shut down. It is + intended that the device be completely inactive at this point, For U-Boot + to be sure that no hardware is running, it should be enough to remove + all devices. + + d. The device memory is freed (platform data, private data, uclass data, + parent data). + + Note: Because the platform data for a U_BOOT_DEVICE() is defined with a + static pointer, it is not de-allocated during the remove() method. For + a device instantiated using the device tree data, the platform data will + be dynamically allocated, and thus needs to be deallocated during the + remove() method, either: + + 1. if the platdata_auto_alloc_size is non-zero, the deallocation + happens automatically within the driver model core; or + + 2. when platdata_auto_alloc_size is 0, both the allocation (in probe() + or preferably ofdata_to_platdata()) and the deallocation in remove() + are the responsibility of the driver author. + + e. The device sequence number is set to -1, meaning that it no longer + has an allocated sequence. If the device is later reactivated and that + sequence number is still free, it may well receive the name sequence + number again. But from this point, the sequence number previously used + by this device will no longer exist (think of SPI bus 2 being removed + and bus 2 is no longer available for use). + + f. The device is marked inactive. Note that it is still bound, so the + device structure itself is not freed at this point. Should the device be + activated again, then the cycle starts again at step 2 above. + +5. Unbind stage + +The device is unbound. This is the step that actually destroys the device. +If a parent has children these will be destroyed first. After this point +the device does not exist and its memory has be deallocated. + + +Data Structures +--------------- + +Driver model uses a doubly-linked list as the basic data structure. Some +nodes have several lists running through them. Creating a more efficient +data structure might be worthwhile in some rare cases, once we understand +what the bottlenecks are. + + +Changes since v1 +---------------- + +For the record, this implementation uses a very similar approach to the +original patches, but makes at least the following changes: + +- Tried to aggressively remove boilerplate, so that for most drivers there +is little or no 'driver model' code to write. +- Moved some data from code into data structure - e.g. store a pointer to +the driver operations structure in the driver, rather than passing it +to the driver bind function. +- Rename some structures to make them more similar to Linux (struct udevice +instead of struct instance, struct platdata, etc.) +- Change the name 'core' to 'uclass', meaning U-Boot class. It seems that +this concept relates to a class of drivers (or a subsystem). We shouldn't +use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems +better than 'core'. +- Remove 'struct driver_instance' and just use a single 'struct udevice'. +This removes a level of indirection that doesn't seem necessary. +- Built in device tree support, to avoid the need for platdata +- Removed the concept of driver relocation, and just make it possible for +the new driver (created after relocation) to access the old driver data. +I feel that relocation is a very special case and will only apply to a few +drivers, many of which can/will just re-init anyway. So the overhead of +dealing with this might not be worth it. +- Implemented a GPIO system, trying to keep it simple + + +Pre-Relocation Support +---------------------- + +For pre-relocation we simply call the driver model init function. Only +drivers marked with DM_FLAG_PRE_RELOC or the device tree +'u-boot,dm-pre-reloc' flag are initialised prior to relocation. This helps +to reduce the driver model overhead. + +Then post relocation we throw that away and re-init driver model again. +For drivers which require some sort of continuity between pre- and +post-relocation devices, we can provide access to the pre-relocation +device pointers, but this is not currently implemented (the root device +pointer is saved but not made available through the driver model API). + + +SPL Support +----------- + +Driver model can operate in SPL. Its efficient implementation and small code +size provide for a small overhead which is acceptable for all but the most +constrained systems. + +To enable driver model in SPL, define CONFIG_SPL_DM. You might want to +consider the following option also. See the main README for more details. + + - CONFIG_SYS_MALLOC_SIMPLE + - CONFIG_DM_WARN + - CONFIG_DM_DEVICE_REMOVE + - CONFIG_DM_STDIO + + +Enabling Driver Model +--------------------- + +Driver model is being brought into U-Boot gradually. As each subsystems gets +support, a uclass is created and a CONFIG to enable use of driver model for +that subsystem. + +For example CONFIG_DM_SERIAL enables driver model for serial. With that +defined, the old serial support is not enabled, and your serial driver must +conform to driver model. With that undefined, the old serial support is +enabled and driver model is not available for serial. This means that when +you convert a driver, you must either convert all its boards, or provide for +the driver to be compiled both with and without driver model (generally this +is not very hard). + +See the main README for full details of the available driver model CONFIG +options. + + +Things to punt for later +------------------------ + +Uclasses are statically numbered at compile time. It would be possible to +change this to dynamic numbering, but then we would require some sort of +lookup service, perhaps searching by name. This is slightly less efficient +so has been left out for now. One small advantage of dynamic numbering might +be fewer merge conflicts in uclass-id.h. + + +Simon Glass +sjg@chromium.org +April 2013 +Updated 7-May-13 +Updated 14-Jun-13 +Updated 18-Oct-13 +Updated 5-Nov-13 diff --git a/doc/driver-model/UDM-block.txt b/doc/driver-model/UDM-block.txt deleted file mode 100644 index b42ec69c94..0000000000 --- a/doc/driver-model/UDM-block.txt +++ /dev/null @@ -1,279 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Block device subsystem analysis -=============================== - -Pavel Herrmann -2012-03-08 - -I) Overview ------------ - - U-Boot currently implements several distinct APIs for block devices - some - drivers use the SATA API, some drivers use the IDE API, sym53c8xx and - AHCI use the SCSI API, mg_disk has a separate API, and systemace also has a - separate API. There are also MMC and USB APIs used outside of drivers/block, - those will be detailed in their specific documents. - - Block devices are described by block_dev_desc structure, that holds, among - other things, the read/write/erase callbacks. Block device structures are - stored in any way depending on the API, but can be accessed by - - block_dev_desc_t * $api_get_dev(int dev) - - function, as seen in disk/part.c. - - 1) SATA interface - ----------------- - - The SATA interface drivers implement the following functions: - - int init_sata(int dev) - int scan_sata(int dev) - ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer) - ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer) - - Block devices are kept in sata_dev_desc[], which is prefilled with values - common to all SATA devices in cmd_sata.c, and then modified in init_sata - function in the drivers. Callbacks of the block device use SATA API - directly. The sata_get_dev function is defined in cmd_sata.c. - - 2) SCSI interface - ----------------- - - The SCSI interface drivers implement the following functions: - - void scsi_print_error(ccb *pccb) - int scsi_exec(ccb *pccb) - void scsi_bus_reset(void) - void scsi_low_level_init(int busdevfunc) - - The SCSI API works through the scsi_exec function, the actual operation - requested is found in the ccb structure. - - Block devices are kept in scsi_dev_desc[], which lives only in cmd_scsi.c. - Callbacks of the block device use functions from cmd_scsi.c, which in turn - call scsi_exec of the controller. The scsi_get_dev function is also defined - in cmd_scsi.c. - - 3) mg_disk interface - -------------------- - - The mg_disk interface drivers implement the following functions: - - struct mg_drv_data* mg_get_drv_data (void) - uint mg_disk_init (void) - uint mg_disk_read (u32 addr, u8 *buff, u32 len) - uint mg_disk_write(u32 addr, u8 *buff, u32 len) - uint mg_disk_write_sects(void *buff, u32 sect_num, u32 sect_cnt) - uint mg_disk_read_sects(void *buff, u32 sect_num, u32 sect_cnt) - - The mg_get_drv_data function is to be overridden per-board, but there are no - board in-tree that do this. - - Only one driver for this API exists, and it only supports one block device. - Callbacks for this device are implemented in mg_disk.c and call the mg_disk - API. The mg_disk_get_dev function is defined in mg_disk.c and ignores the - device number, always returning the same device. - - 4) systemace interface - ---------------------- - - The systemace interface does not define any driver API, and has no command - itself. The single defined function is systemace_get_devs() from - systemace.c, which returns a single static structure for the only supported - block device. Callbacks for this device are also implemented in systemace.c. - - 5) IDE interface - ---------------- - - The IDE interface drivers implement the following functions, but only if - CONFIG_IDE_AHB is set: - - uchar ide_read_register(int dev, unsigned int port); - void ide_write_register(int dev, unsigned int port, unsigned char val); - void ide_read_data(int dev, ulong *sect_buf, int words); - void ide_write_data(int dev, const ulong *sect_buf, int words); - - The first two functions are called from ide_inb()/ide_outb(), and will - default to direct memory access if CONFIG_IDE_AHB is not set, or - ide_inb()/ide_outb() functions will get overridden by the board altogether. - - The second two functions are called from input_data()/output_data() - functions, and also default to direct memory access, but cannot be - overridden by the board. - - One function shared by IDE drivers (but not defined in ide.h) is - int ide_preinit(void) - This function gets called from ide_init in cmd_ide.c if CONFIG_IDE_PREINIT - is defined, and will do the driver-specific initialization of the device. - - Block devices are kept in ide_dev_desc[], which is filled in cmd_ide.c. - Callbacks of the block device are defined in cmd_ide.c, and use the - ide_inb()/ide_outb()/input_data()/output_data() functions mentioned above. - The ide_get_dev function is defined in cmd_ide.c. - -II) Approach ------------- - - A new block controller core and an associated API will be created to mimic the - current SATA API, its drivers will have the following ops: - - struct block_ctrl_ops { - int scan(instance *i); - int reset(instance *i, int port); - lbaint_t read(instance *i, int port, lbaint_t start, lbatin_t length, - void *buffer); - lbaint_t write(instance *i, int port, lbaint_t start, lbatin_t length, - void*buffer); - } - - The current sata_init() function will be changed into the driver probe() - function. The read() and write() functions should never be called directly, - instead they should be called by block device driver for disks. - - Other block APIs would either be transformed into this API, or be kept as - legacy for old drivers, or be dropped altogether. - - Legacy driver APIs will each have its own driver core that will contain the - shared logic, which is currently located mostly in cmd_* files. Callbacks for - block device drivers will then probably be implemented as a part of the core - logic, and will use the driver ops (which will copy current state of - respective APIs) to do the work. - - All drivers will be cleaned up, most ifdefs should be converted into - platform_data, to enable support for multiple devices with different settings. - - A new block device core will also be created, and will keep track of all - block devices on all interfaces. - - Current block_dev_desc structure will be changed to fit the driver model, all - identification and configuration will be placed in private data, and - a single accessor and modifier will be defined, to accommodate the need for - different sets of options for different interfaces, while keeping the - structure small. The new block device drivers will have the following ops - structure (lbaint_t is either 32bit or 64bit unsigned, depending on - CONFIG_LBA48): - - struct blockdev_ops { - lbaint_t (*block_read)(struct instance *i, lbaint_t start, lbaint_t blkcnt, - void *buffer); - lbaint_t (*block_write)(struct instance *i, lbaint_t start, lbaint_t blkcnt, - void *buffer); - lbaint_t (*block_erase)(struct instance *i, lbaint_t start, lbaint_t blkcnt - ); - int (*get_option)(struct instance *i, enum blockdev_option_code op, - struct option *res); - int (*set_option)(struct instance *i, enum blockdev_option_code op, - struct option *val); - } - - struct option { - uint32_t flags - union data { - uint64_t data_u; - char* data_s; - void* data_p; - } - } - - enum blockdev_option_code { - BLKD_OPT_IFTYPE=0, - BLKD_OPT_TYPE, - BLKD_OPT_BLOCKSIZE, - BLKD_OPT_BLOCKCOUNT, - BLKD_OPT_REMOVABLE, - BLKD_OPT_LBA48, - BLKD_OPT_VENDOR, - BLKD_OPT_PRODICT, - BLKD_OPT_REVISION, - BLKD_OPT_SCSILUN, - BLKD_OPT_SCSITARGET, - BLKD_OPT_OFFSET - } - - Flags in option above will contain the type of returned data (which should be - checked against what is expected, even though the option requested should - specify it), and a flag to indicate whether the returned pointer needs to be - free()'d. - - The block device core will contain the logic now located in disk/part.c and - related files, and will be used to forward requests to block devices. The API - for the block device core will copy the ops of a block device (with a string - identifier instead of instance pointer). This means that partitions will also - be handled by the block device core, and exported as block devices, making - them transparent to the rest of the code. - - Sadly, this will change how file systems can access the devices, and thus will - affect a lot of places. However, these changes should be localized and easy to - implement. - - AHCI driver will be rewritten to fit the new unified block controller API, - making SCSI API easy to merge with sym53c8xx, or remove it once the device - driver has died. - - Optionally, IDE core may be changed into one driver with unified block - controller API, as most of it is already in one place and device drivers are - just sets of hooks. Additionally, mg_disk driver is unused and may be removed - in near future. - - - -III) Analysis of in-tree drivers --------------------------------- - - 1) ahci.c - --------- - SCSI API, will be rewritten for a different API. - - 2) ata_piix.c - ------------- - SATA API, easy to port. - - 3) fsl_sata.c - ------------- - SATA API, few CONFIG macros, easy to port. - - 4) ftide020.c - ------------- - IDE API, defines CONFIG_IDE_AHB and ide_preinit hook functions. - - 5) mg_disk.c - ------------ - Single driver with mg_disk API, not much to change, easy to port. - - 6) mvsata_ide.c - --------------- - IDE API, only defines ide_preinit hook function. - - 7) mxc_ata.c - ------------ - IDE API, only defines ide_preinit hook function. - - 8) pata_bfin.c - -------------- - SATA API, easy to port. - - 9) sata_dwc.c - ------------- - SATA API, easy to port. - - 10) sata_sil3114.c - ------------------ - SATA API, easy to port. - - 11) sata_sil.c - -------------- - SATA API, easy to port. - - 12) sil680.c - ------------ - IDE API, only defines ide_preinit hook function. - - 13) sym53c8xx.c - --------------- - SCSI API, may be merged with code from cmd_scsi. - - 14) systemace.c - --------------- - Single driver with systemace API, not much to change, easy to port. diff --git a/doc/driver-model/UDM-cores.txt b/doc/driver-model/UDM-cores.txt deleted file mode 100644 index 4e1318871a..0000000000 --- a/doc/driver-model/UDM-cores.txt +++ /dev/null @@ -1,126 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Driver cores API document -========================= - -Pavel Herrmann - -1) Overview ------------ - Driver cores will be used as a wrapper for devices of the same type, and as - an abstraction for device driver APIs. For each driver API (which roughly - correspond to device types), there will be one driver core. Each driver core - will implement three APIs - a driver API (which will be the same as API of - drivers the core wraps around), a core API (which will be implemented by all - cores) and a command API (core-specific API which will be exposed to - commands). - - A) Command API - The command API will provide access to shared functionality for a specific - device, which is currently located mostly in commands. Commands will be - rewritten to be more lightweight by using this API. As this API will be - different for each core, it is out of scope of this document. - - B) Driver API - The driver API will act as a wrapper around actual device drivers, - providing a single entrypoint for device access. All functions in this API - have an instance* argument (probably called "this" or "i"), which will be - examined by the core, and a correct function for the specified driver will - get called. - - If the core gets called with a group instance pointer (as discussed in - design), it will automatically select the instance that is associated - with this core, and use it as target of the call. if the group contains - multiple instances of a single type, the caller must explicitly use an - accessor to select the correct instance. - - This accessor will look like: - struct instance *get_instance_from_group(struct instance *group, int i) - - When called with a non-group instance, it will simply return the instance. - - C) Core API - The core API will be implemented by all cores, and will provide - functionality for getting driver instances from non-driver code. This API - will consist of following functions: - - int get_count(struct instance *core); - struct instance* get_instance(struct instance *core, int index); - int init(struct instance *core); - int bind(struct instance *core, struct instance *dev, void *ops, - void *hint); - int unbind(struct instance *core, instance *dev); - int replace(struct instance *core, struct_instance *new_dev, - struct instance *old_dev); - int destroy(struct instance *core); - int reloc(struct instance *new_core, struct instance *old_core); - - The 'hint' parameter of bind() serves for additional data a driver can - pass to the core, to help it create the correct internal state for this - instance. the replace() function will get called during instance - relocation, and will replace the old instance with the new one, keeping - the internal state untouched. - - -2) Lifetime of a driver core ----------------------------- - Driver cores will be initialized at runtime, to limit memory footprint in - early-init stage, when we have to fit into ~1KB of memory. All active cores - will be stored in a tree structure (referenced as "Core tree") in global data, - which provides good tradeoff between size and access time. - Every core will have a number constant associated with it, which will be used - to find the instance in Core tree, and to refer to the core in all calls - working with the Core tree. - The Core Tree should be implemented using B-tree (or a similar structure) - to guarantee acceptable time overhead in all cases. - - Code for working with the core (i2c in this example) follows: - - core_init(CORE_I2C); - This will check whether we already have a i2c core, and if not it creates - a new instance and adds it into the Core tree. This will not be exported, - all code should depend on get_core_instance to init the core when - necessary. - - get_core_instance(CORE_I2C); - This is an accessor into the Core tree, which will return the instance - of i2c core, creating it if necessary - - core_bind(CORE_I2C, instance, driver_ops); - This will get called in bind() function of a driver, and will add the - instance into cores internal list of devices. If the core is not found, it - will get created. - - driver_activate(instance *inst); - This call will recursively activate all devices necessary for using the - specified device. the code could be simplified as: - { - if (is_activated(inst)) - return; - driver_activate(inst->bus); - get_driver(inst)->probe(inst); - } - - The case with multiple parents will need to be handled here as well. - get_driver is an accessor to available drivers, which will get struct - driver based on a name in the instance. - - i2c_write(instance *inst, ...); - An actual call to some method of the driver. This code will look like: - { - driver_activate(inst); - struct instance *core = get_core_instance(CORE_I2C); - device_ops = get_ops(inst); - device_ops->write(...); - } - - get_ops will not be an exported function, it will be internal and specific - to the core, as it needs to know how are the ops stored, and what type - they are. - - Please note that above examples represent the algorithm, not the actual code, - as they are missing checks for validity of return values. - - core_init() function will get called the first time the core is requested, - either by core_link() or core_get_instance(). This way, the cores will get - created only when they are necessary, which will reduce our memory footprint. diff --git a/doc/driver-model/UDM-design.txt b/doc/driver-model/UDM-design.txt deleted file mode 100644 index 185f477b06..0000000000 --- a/doc/driver-model/UDM-design.txt +++ /dev/null @@ -1,315 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Design document -=============== -Marek Vasut -Pavel Herrmann -2012-05-17 - -I) The modular concept ----------------------- - -The driver core design is done with modularity in mind. The long-term plan is to -extend this modularity to allow loading not only drivers, but various other -objects into U-Boot at runtime -- like commands, support for other boards etc. - -II) Driver core initialization stages -------------------------------------- - -The drivers have to be initialized in two stages, since the U-Boot bootloader -runs in two stages itself. The first stage is the one which is executed before -the bootloader itself is relocated. The second stage then happens after -relocation. - - 1) First stage - -------------- - - The first stage runs after the bootloader did very basic hardware init. This - means the stack pointer was configured, caches disabled and that's about it. - The problem with this part is the memory management isn't running at all. To - make things even worse, at this point, the RAM is still likely uninitialized - and therefore unavailable. - - 2) Second stage - --------------- - - At this stage, the bootloader has initialized RAM and is running from it's - final location. Dynamic memory allocations are working at this point. Most of - the driver initialization is executed here. - -III) The drivers ----------------- - - 1) The structure of a driver - ---------------------------- - - The driver will contain a structure located in a separate section, which - will allow linker to create a list of compiled-in drivers at compile time. - Let's call this list "driver_list". - - struct driver __attribute__((section(driver_list))) { - /* The name of the driver */ - char name[STATIC_CONFIG_DRIVER_NAME_LENGTH]; - - /* - * This function should connect this driver with cores it depends on and - * with other drivers, likely bus drivers - */ - int (*bind)(struct instance *i); - - /* This function actually initializes the hardware. */ - int (*probe)(struct instance *i); - - /* - * The function of the driver called when U-Boot finished relocation. - * This is particularly important to eg. move pointers to DMA buffers - * and such from the location before relocation to their final location. - */ - int (*reloc)(struct instance *i); - - /* - * This is called when the driver is shuting down, to deinitialize the - * hardware. - */ - int (*remove)(struct instance *i); - - /* This is called to remove the driver from the driver tree */ - int (*unbind)(struct instance *i); - - /* This is a list of cores this driver depends on */ - struct driver *cores[]; - }; - - The cores[] array in here is very important. It allows u-boot to figure out, - in compile-time, which possible cores can be activated at runtime. Therefore - if there are cores that won't be ever activated, GCC LTO might remove them - from the final binary. Actually, this information might be used to drive build - of the cores. - - FIXME: Should *cores[] be really struct driver, pointing to drivers that - represent the cores? Shouldn't it be core instance pointer? - - 2) Instantiation of a driver - ---------------------------- - - The driver is instantiated by calling: - - driver_bind(struct instance *bus, const struct driver_info *di) - - The "struct instance *bus" is a pointer to a bus with which this driver should - be registered with. The "root" bus pointer is supplied to the board init - functions. - - FIXME: We need some functions that will return list of busses of certain type - registered with the system so the user can find proper instance even if - he has no bus pointer (this will come handy if the user isn't - registering the driver from board init function, but somewhere else). - - The "const struct driver_info *di" pointer points to a structure defining the - driver to be registered. The structure is defined as follows: - - struct driver_info { - char name[STATIC_CONFIG_DRIVER_NAME_LENGTH]; - void *platform_data; - } - - The instantiation of a driver by calling driver_bind() creates an instance - of the driver by allocating "struct driver_instance". Note that only struct - instance is passed to the driver. The wrapping struct driver_instance is there - for purposes of the driver core: - - struct driver_instance { - uint32_t flags; - struct instance i; - }; - - struct instance { - /* Pointer to a driver information passed by driver_register() */ - const struct driver_info *info; - /* Pointer to a bus this driver is bound with */ - struct instance *bus; - /* Pointer to this driver's own private data */ - void *private_data; - /* Pointer to the first block of successor nodes (optional) */ - struct successor_block *succ; - } - - The instantiation of a driver does not mean the hardware is initialized. The - driver_bind() call only creates the instance of the driver, fills in the "bus" - pointer and calls the drivers' .bind() function. The .bind() function of the - driver should hook the driver with the remaining cores and/or drivers it - depends on. - - It's important to note here, that in case the driver instance has multiple - parents, such parent can be connected with this instance by calling: - - driver_link(struct instance *parent, struct instance *dev); - - This will connect the other parent driver with the newly instantiated driver. - Note that this must be called after driver_bind() and before driver_acticate() - (driver_activate() will be explained below). To allow struct instance to have - multiple parent pointer, the struct instance *bus will utilize it's last bit - to indicate if this is a pointer to struct instance or to an array if - instances, struct successor block. The approach is similar as the approach to - *succ in struct instance, described in the following paragraph. - - The last pointer of the struct instance, the pointer to successor nodes, is - used only in case of a bus driver. Otherwise the pointer contains NULL value. - The last bit of this field indicates if this is a bus having a single child - node (so the last bit is 0) or if this bus has multiple child nodes (the last - bit is 1). In the former case, the driver core should clear the last bit and - this pointer points directly to the child node. In the later case of a bus - driver, the pointer points to an instance of structure: - - struct successor_block { - /* Array of pointers to instances of devices attached to this bus */ - struct instance *dev[BLOCKING_FACTOR]; - /* Pointer to next block of successors */ - struct successor_block *next; - } - - Some of the *dev[] array members might be NULL in case there are no more - devices attached. The *next is NULL in case the list of attached devices - doesn't continue anymore. The BLOCKING_FACTOR is used to allocate multiple - slots for successor devices at once to avoid fragmentation of memory. - - 3) The bind() function of a driver - ---------------------------------- - - The bind function of a driver connects the driver with various cores the - driver provides functions for. The driver model related part will look like - the following example for a bus driver: - - int driver_bind(struct instance *in) - { - ... - core_bind(&core_i2c_static_instance, in, i2c_bus_funcs); - ... - } - - FIXME: What if we need to run-time determine, depending on some hardware - register, what kind of i2c_bus_funcs to pass? - - This makes the i2c core aware of a new bus. The i2c_bus_funcs is a constant - structure of functions any i2c bus driver must provide to work. This will - allow the i2c command operate with the bus. The core_i2c_static_instance is - the pointer to the instance of a core this driver provides function to. - - FIXME: Maybe replace "core-i2c" with CORE_I2C global pointer to an instance of - the core? - - 4) The instantiation of a core driver - ------------------------------------- - - The core driver is special in the way that it's single-instance driver. It is - always present in the system, though it might not be activated. The fact that - it's single instance allows it to be instantiated at compile time. - - Therefore, all possible structures of this driver can be in read-only memory, - especially struct driver and struct driver_instance. But the successor list, - which needs special treatment. - - To solve the problem with a successor list and the core driver flags, a new - entry in struct gd (global data) will be introduced. This entry will point to - runtime allocated array of struct driver_instance. It will be possible to - allocate the exact amount of struct driver_instance necessary, as the number - of cores that might be activated will be known at compile time. The cores will - then behave like any usual driver. - - Pointers to the struct instance of cores can be computed at compile time, - therefore allowing the resulting u-boot binary to save some overhead. - - 5) The probe() function of a driver - ----------------------------------- - - The probe function of a driver allocates necessary resources and does required - initialization of the hardware itself. This is usually called only when the - driver is needed, as a part of the defered probe mechanism. - - The driver core should implement a function called - - int driver_activate(struct instance *in); - - which should call the .probe() function of the driver and then configure the - state of the driver instance to "ACTIVATED". This state of a driver instance - should be stored in a wrap-around structure for the structure instance, the - struct driver_instance. - - 6) The command side interface to a driver - ----------------------------------------- - - The U-Boot command shall communicate only with the specific driver core. The - driver core in turn exports necessary API towards the command. - - 7) Demonstration imaginary board - -------------------------------- - - Consider the following computer: - - * - | - +-- System power management logic - | - +-- CPU clock controlling logc - | - +-- NAND controller - | | - | +-- NAND flash chip - | - +-- 128MB of DDR DRAM - | - +-- I2C bus #0 - | | - | +-- RTC - | | - | +-- EEPROM #0 - | | - | +-- EEPROM #1 - | - +-- USB host-only IP core - | | - | +-- USB storage device - | - +-- USB OTG-capable IP core - | | - | +-- connection to the host PC - | - +-- GPIO - | | - | +-- User LED #0 - | | - | +-- User LED #1 - | - +-- UART0 - | - +-- UART1 - | - +-- Ethernet controller #0 - | - +-- Ethernet controller #1 - | - +-- Audio codec - | - +-- PCI bridge - | | - | +-- Ethernet controller #2 - | | - | +-- SPI host card - | | | - | | +-- Audio amplifier (must be operational before codec) - | | - | +-- GPIO host card - | | - | +-- User LED #2 - | - +-- LCD controller - | - +-- PWM controller (must be enabled after LCD controller) - | - +-- SPI host controller - | | - | +-- SD/MMC connected via SPI - | | - | +-- SPI flash - | - +-- CPLD/FPGA with stored configuration of the board diff --git a/doc/driver-model/UDM-fpga.txt b/doc/driver-model/UDM-fpga.txt deleted file mode 100644 index 4f9df940ed..0000000000 --- a/doc/driver-model/UDM-fpga.txt +++ /dev/null @@ -1,115 +0,0 @@ -The U-Boot Driver Model Project -=============================== -I/O system analysis -=================== -Marek Vasut -2012-02-21 - -I) Overview ------------ - -The current FPGA implementation is handled by command "fpga". This command in -turn calls the following functions: - -fpga_info() -fpga_load() -fpga_dump() - -These functions are implemented by what appears to be FPGA multiplexer, located -in drivers/fpga/fpga.c . This code determines which device to operate with -depending on the device ID. - -The fpga_info() function is multiplexer of the functions providing information -about the particular FPGA device. These functions are implemented in the drivers -for the particular FPGA device: - -xilinx_info() -altera_info() -lattice_info() - -Similar approach is used for fpga_load(), which multiplexes "xilinx_load()", -"altera_load()" and "lattice_load()" and is used to load firmware into the FPGA -device. - -The fpga_dump() function, which prints the contents of the FPGA device, is no -different either, by multiplexing "xilinx_dump()", "altera_dump()" and -"lattice_dump()" functions. - -Finally, each new FPGA device is registered by calling "fpga_add()" function. -This function takes two arguments, the second one being particularly important, -because it's basically what will become platform_data. Currently, it's data that -are passed to the driver from the board/platform code. - -II) Approach ------------- - -The path to conversion of the FPGA subsystem will be very straightforward, since -the FPGA subsystem is already quite dynamic. Multiple things will need to be -modified though. - -First is the registration of the new FPGA device towards the FPGA core. This -will be achieved by calling: - - fpga_device_register(struct instance *i, const struct fpga_ops *ops); - -The particularly interesting part is the struct fpga_ops, which contains -operations supported by the FPGA device. These are basically the already used -calls in the current implementation: - -struct fpga_ops { - int info(struct instance *i); - int load(struct instance *i, const char *buf, size_t size); - int dump(struct instance *i, const char *buf, size_t size); -} - -The other piece that'll have to be modified is how the devices are tracked. -It'll be necessary to introduce a linked list of devices within the FPGA core -instead of tracking them by ID number. - -Next, the "Xilinx_desc", "Lattice_desc" and "Altera_desc" structures will have -to be moved to driver's private_data. Finally, structures passed from the board -and/or platform files, like "Xilinx_Virtex2_Slave_SelectMap_fns" would be passed -via platform_data to the driver. - -III) Analysis of in-tree drivers --------------------------------- - - 1) Altera driver - ---------------- - The driver is realized using the following files: - - drivers/fpga/altera.c - drivers/fpga/ACEX1K.c - drivers/fpga/cyclon2.c - drivers/fpga/stratixII.c - - All of the sub-drivers implement basically the same info-load-dump interface - and there's no expected problem during the conversion. The driver itself will - be realised by altera.c and all the sub-drivers will be linked in. The - distinction will be done by passing different platform data. - - 2) Lattice driver - ----------------- - The driver is realized using the following files: - - drivers/fpga/lattice.c - drivers/fpga/ivm_core.c - - This driver also implements the standard interface, but to realise the - operations with the FPGA device, uses functions from "ivm_core.c" file. This - file implements the main communications logic and has to be linked in together - with "lattice.c". No problem converting is expected here. - - 3) Xilinx driver - ---------------- - The driver is realized using the following files: - - drivers/fpga/xilinx.c - drivers/fpga/spartan2.c - drivers/fpga/spartan3.c - drivers/fpga/virtex2.c - - This set of sub-drivers is special by defining a big set of macros in - "include/spartan3.h" and similar files. These macros would need to be either - rewritten or replaced. Otherwise, there are no problems expected during the - conversion process. diff --git a/doc/driver-model/UDM-gpio.txt b/doc/driver-model/UDM-gpio.txt deleted file mode 100644 index 8ff0a965c7..0000000000 --- a/doc/driver-model/UDM-gpio.txt +++ /dev/null @@ -1,106 +0,0 @@ -The U-Boot Driver Model Project -=============================== -GPIO analysis -============= -Viktor Krivak -2012-02-24 - -I) Overview ------------ - - At this moment U-Boot provides standard API that consists of 7 functions. - - int gpio_request(unsigned gpio, const char *label) - int gpio_free(unsigned gpio) - int gpio_direction_input(unsigned gpio) - int gpio_direction_output(unsigned gpio, int value) - int gpio_get_value(unsigned gpio) - void gpio_set_value(unsigned gpio, int value) - - Methods "gpio_request()" and "gpio_free()" are used for claiming and releasing - GPIOs. First one should check if the desired pin exists and if the pin wasn't - requested already elsewhere. The method also has a label argument that can be - used for debug purposes. The label argument should be copied into the internal - memory, but only if the DEBUG macro is set. The "gpio_free()" is the exact - opposite. It releases the particular pin. Other methods are used for setting - input or output direction and obtaining or setting values of the pins. - -II) Approach ------------- - - 1) Request and free GPIO - ------------------------ - - The "gpio_request()" implementation is basically the same for all boards. - The function checks if the particular GPIO is correct and checks if the - GPIO pin is still free. If the conditions are met, the method marks the - GPIO claimed in it's internal structure. If macro DEBUG is defined, the - function also copies the label argument to the structure. If the pin is - already locked, the function returns -1 and if DEBUG is defined, certain - debug output is generated, including the contents of the label argument. - The "gpio_free()" function releases the lock and eventually deallocates - data used by the copied label argument. - - 2) Internal data - ---------------- - - Internal data are driver specific. They have to contain some mechanism to - realise the locking though. This can be done for example using a bit field. - - 3) Operations provided by the driver - ------------------------------------ - - The driver operations basically meet API that is already defined and used. - Except for "gpio_request()" and "gpio_free()", all methods can be converted in - a simple manner. The driver provides the following structure: - - struct gpio_driver_ops { - int (*gpio_request)(struct instance *i, unsigned gpio, - const char *label); - int (*gpio_free)(struct instance *i, unsigned gpio); - int (*gpio_direction_input)(struct instance *i, unsigned gpio); - int (*gpio_direction_output)(struct instance *i, unsigned gpio, - int value); - int (*gpio_get_value)(struct instance *i, unsigned gpio); - void (*gpio_set_value)(struct instance *i, unsigned gpio, int value); - } - -III) Analysis of in-tree drivers --------------------------------- - - 1) altera_pio.c - --------------- - Meets standard API. Implements gpio_request() properly. Simple conversion - possible. - - 2) at91_gpio.c - -------------- - Don't meet standard API. Need some other methods to implement. - - 3) da8xx_gpio.c - --------------- - Meets standard API. Implements gpio_request() properly. Simple conversion - possible. - - 4) kw_gpio.c - ------------ - Doesn't meet standard API. Needs some other methods to implement and move some - methods to another file. - - 5) mpc83xx_gpio.c - ----------------- - Meets standard API. Doesn't implement gpio_request() properly (only checks - if the pin is valid). Simple conversion possible. - - 6) mvgpio.c - ----------- - Meets standard API. Doesn't implement gpio_request() properly (only checks - if the pin is valid). Simple conversion possible. - - 7) mvgpio.h - ----------- - Wrong placement. Will be moved to another location. - - 8) mvmfp.c - ---------- - Wrong placement. Will be moved to another location. diff --git a/doc/driver-model/UDM-hwmon.txt b/doc/driver-model/UDM-hwmon.txt deleted file mode 100644 index cc5d529c3b..0000000000 --- a/doc/driver-model/UDM-hwmon.txt +++ /dev/null @@ -1,118 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Hwmon device subsystem analysis -=============================== - -Tomas Hlavacek -2012-03-02 - -I) Overview ------------ - -U-Boot currently implements one API for HW monitoring devices. The -interface is defined in include/dtt.h and comprises of functions: - - void dtt_init(void); - int dtt_init_one(int); - int dtt_read(int sensor, int reg); - int dtt_write(int sensor, int reg, int val); - int dtt_get_temp(int sensor); - -The functions are implemented by a proper device driver in drivers/hwmon -directory and the driver to be compiled in is selected in a Makefile. -Drivers are mutually exclusive. - -Drivers depends on I2O code and naturally on board specific data. There are -few ad-hoc constants put in dtt.h file and driver headers and code. This -has to be consolidated into board specific data or driver headers if those -constants makes sense globally. - - -II) Approach ------------- - - 1) New API - ---------- - In the UDM each hwmon driver would register itself by a function - - int hwmon_device_register(struct instance *i, - struct hwmon_device_ops *o); - - The structure being defined as follows: - - struct hwmon_device_ops { - int (*read)(struct instance *i, int sensor, int reg); - int (*write)(struct instance *i, int sensor, int reg, - int val); - int (*get_temp)(struct instance *i, int sensor); - }; - - - 2) Conversion thougths - ---------------------- - U-Boot hwmon drivers exports virtually the same functions (with exceptions) - and we are considering low number of drivers and code anyway. The interface - is already similar and unified by the interface defined in dtt.h. - Current initialization functions dtt_init() and dtt_init_one() will be - converted into probe() and hwmon_device_register(), so the funcionality will - be kept in more proper places. Besides implementing core registration and - initialization we need to do code cleanup, especially separate - driver-specific and HW specific constants. - - 3) Special consideration due to early initialization - ---------------------------------------------------- - The dtt_init() function call is used during early initialization in - board/gdsys/405ex/io64.c for starting up fans. The dtt code is perfectly - usable in the early stage because it uses only local variables and no heap - memory is required at this level. However the underlying code of I2C has to - keep the same properties with regard to possibility of running in early - initialization stage. - -III) Analysis of in-tree drivers --------------------------------- - - 1) drivers/hwmon/lm81.c - ----------------------- - The driver is standard dtt. Simple conversion is possible. - - - 2) drivers/hwmon/ds1722.c - ------------------------- - The driver is not standard dtt, but interface is similar to dtt. - The interface has to be changed in order to comply to above mentioned - specification. - - - 3) drivers/hwmon/ds1775.c - ------------------------- - The driver is standard dtt. Simple conversion is possible. - - - 4) drivers/hwmon/lm73.c - ----------------------- - The driver is standard dtt. Simple conversion is possible. - - - 5) drivers/hwmon/lm63.c - ----------------------- - The driver is standard dtt. Simple conversion is possible. - - - 6) drivers/hwmon/adt7460.c - -------------------------- - The driver is standard dtt. Simple conversion is possible. - - - 7) drivers/hwmon/lm75.c - ----------------------- - The driver is standard dtt. Simple conversion is possible. - - - 8) drivers/hwmon/ds1621.c - ------------------------- - The driver is standard dtt. Simple conversion is possible. - - - 9) drivers/hwmon/adm1021.c - -------------------------- - The driver is standard dtt. Simple conversion is possible. diff --git a/doc/driver-model/UDM-keyboard.txt b/doc/driver-model/UDM-keyboard.txt deleted file mode 100644 index ef3761dc24..0000000000 --- a/doc/driver-model/UDM-keyboard.txt +++ /dev/null @@ -1,47 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Keyboard input analysis -======================= -Marek Vasut -2012-02-20 - -I) Overview ------------ - -The keyboard drivers are most often registered with STDIO subsystem. There are -components of the keyboard drivers though, which operate in severe ad-hoc -manner, often being related to interrupt-driven keypress reception. This -components will require the most sanitization of all parts of keyboard input -subsystem. - -Otherwise, the keyboard is no different from other standard input but with the -necessity to decode scancodes. These are decoded using tables provided by -keyboard drivers. These tables are often driver specific. - -II) Approach ------------- - -The most problematic part is the interrupt driven keypress reception. For this, -the buffers that are currently shared throughout the whole U-Boot would need to -be converted into driver's private data. - -III) Analysis of in-tree drivers --------------------------------- - - 1) board/mpl/common/kbd.c - ------------------------- - This driver is a classic STDIO driver, no problem with conversion is expected. - Only necessary change will be to move this driver to a proper location. - - 2) board/rbc823/kbd.c - --------------------- - This driver is a classic STDIO driver, no problem with conversion is expected. - Only necessary change will be to move this driver to a proper location. - - 3) drivers/input/keyboard.c - --------------------------- - This driver is special in many ways. Firstly because this is a universal stub - driver for converting scancodes from i8042 and the likes. Secondly because the - buffer is filled by various other ad-hoc implementations of keyboard input by - using this buffer as an extern. This will need to be fixed by allowing drivers - to pass certain routines to this driver via platform data. diff --git a/doc/driver-model/UDM-mmc.txt b/doc/driver-model/UDM-mmc.txt deleted file mode 100644 index bed430643b..0000000000 --- a/doc/driver-model/UDM-mmc.txt +++ /dev/null @@ -1,319 +0,0 @@ -The U-Boot Driver Model Project -=============================== -MMC system analysis -=================== -Marek Vasut -2012-02-25 - -I) Overview ------------ - -The MMC subsystem is already quite dynamic in it's nature. It's only necessary -to flip the subsystem to properly defined API. - -The probing process of MMC drivers start by calling "mmc_initialize()", -implemented by MMC framework, from the architecture initialization file. The -"mmc_initialize()" function in turn calls "board_mmc_init()" function and if -this doesn't succeed, "cpu_mmc_init()" function is called. It is important to -note that both of the "*_mmc_init()" functions have weak aliases to functions -which automatically fail. - -Both of the "*_mmc_init()" functions though serve only one purpose. To call -driver specific probe function, which in turn actually registers the driver with -MMC subsystem. Each of the driver specific probe functions is currently done in -very ad-hoc manner. - -The registration with the MMC subsystem is done by calling "mmc_register()", -whose argument is a runtime configured structure of information about the MMC -driver. Currently, the information structure is intermixed with driver's internal -data. The description of the structure follows: - -struct mmc { - /* - * API: Allows this driver to be a member of the linked list of all MMC drivers - * registered with MMC subsystem - */ - struct list_head link; - - /* DRIVER: Name of the registered driver */ - char name[32]; - - /* DRIVER: Driver's private data */ - void *priv; - - /* DRIVER: Voltages the host bus can provide */ - uint voltages; - - /* API: Version of the card */ - uint version; - - /* API: Test if the driver was already initialized */ - uint has_init; - - /* DRIVER: Minimum frequency the host bus can provide */ - uint f_min; - - /* DRIVER: Maximum frequency the host bus can provide */ - uint f_max; - - /* API: Is the card SDHC */ - int high_capacity; - - /* API: Actual width of the bus used by the current card */ - uint bus_width; - - /* - * DRIVER: Clock frequency to be configured on the host bus, this is read-only - * for the driver. - */ - uint clock; - - /* API: Capabilities of the card */ - uint card_caps; - - /* DRIVER: MMC bus capabilities */ - uint host_caps; - - /* API: Configuration and ID data retrieved from the card */ - uint ocr; - uint scr[2]; - uint csd[4]; - uint cid[4]; - ushort rca; - - /* API: Partition configuration */ - char part_config; - - /* API: Number of partitions */ - char part_num; - - /* API: Transmission speed */ - uint tran_speed; - - /* API: Read block length */ - uint read_bl_len; - - /* API: Write block length */ - uint write_bl_len; - - /* API: Erase group size */ - uint erase_grp_size; - - /* API: Capacity of the card */ - u64 capacity; - - /* API: Descriptor of this block device */ - block_dev_desc_t block_dev; - - /* DRIVER: Function used to submit command to the card */ - int (*send_cmd)(struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data); - - /* DRIVER: Function used to configure the host */ - void (*set_ios)(struct mmc *mmc); - - /* DRIVER: Function used to initialize the host */ - int (*init)(struct mmc *mmc); - - /* DRIVER: Function used to report the status of Card Detect pin */ - int (*getcd)(struct mmc *mmc); - - /* - * DRIVER: Maximum amount of blocks sent during multiblock xfer, - * set to 0 to autodetect. - */ - uint b_max; -}; - -The API above is the new API used by most of the drivers. There're still drivers -in the tree that use old, legacy API though. - -2) Approach ------------ - -To convert the MMC subsystem to a proper driver model, the "struct mmc" -structure will have to be properly split in the first place. The result will -consist of multiple parts, first will be the structure defining operations -provided by the MMC driver: - -struct mmc_driver_ops { - /* Function used to submit command to the card */ - int (*send_cmd)(struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data); - /* DRIVER: Function used to configure the host */ - void (*set_ios)(struct mmc *mmc); - /* Function used to initialize the host */ - int (*init)(struct mmc *mmc); - /* Function used to report the status of Card Detect pin */ - int (*getcd)(struct mmc *mmc); -} - -The second part will define the parameters of the MMC driver: - -struct mmc_driver_params { - /* Voltages the host bus can provide */ - uint32_t voltages; - /* Minimum frequency the host bus can provide */ - uint32_t f_min; - /* Maximum frequency the host bus can provide */ - uint32_t f_max; - /* MMC bus capabilities */ - uint32_t host_caps; - /* - * Maximum amount of blocks sent during multiblock xfer, - * set to 0 to autodetect. - */ - uint32_t b_max; -} - -And finally, the internal per-card data of the MMC subsystem core: - -struct mmc_card_props { - /* Version of the card */ - uint32_t version; - /* Test if the driver was already initializes */ - bool has_init; - /* Is the card SDHC */ - bool high_capacity; - /* Actual width of the bus used by the current card */ - uint8_t bus_width; - /* Capabilities of the card */ - uint32_t card_caps; - /* Configuration and ID data retrieved from the card */ - uint32_t ocr; - uint32_t scr[2]; - uint32_t csd[4]; - uint32_t cid[4]; - uint16_t rca; - /* Partition configuration */ - uint8_t part_config; - /* Number of partitions */ - uint8_t part_num; - /* Transmission speed */ - uint32_t tran_speed; - /* Read block length */ - uint32_t read_bl_len; - /* Write block length */ - uint32_t write_bl_len; - /* Erase group size */ - uint32_t erase_grp_size; - /* Capacity of the card */ - uint64_t capacity; - /* Descriptor of this block device */ - block_dev_desc_t block_dev; -} - -The probe() function will then register the MMC driver by calling: - - mmc_device_register(struct instance *i, struct mmc_driver_ops *o, - struct mmc_driver_params *p); - -The struct mmc_driver_params will have to be dynamic in some cases, but the -driver shouldn't modify it's contents elsewhere than in probe() call. - -Next, since the MMC drivers will now be consistently registered into the driver -tree from board file, the functions "board_mmc_init()" and "cpu_mmc_init()" will -disappear altogether. - -As for the legacy drivers, these will either be converted or removed altogether. - -III) Analysis of in-tree drivers --------------------------------- - - 1) arm_pl180_mmci.c - ------------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 2) atmel_mci.c - -------------- - This driver uses the legacy API and should be removed unless converted. It is - probably possbible to replace this driver with gen_atmel_mci.c . No conversion - will be done on this driver. - - 3) bfin_sdh.c - ------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 4) davinci_mmc.c - ---------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 5) fsl_esdhc.c - -------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple, unless some problem appears due to the FDT - component of the driver. - - 6) ftsdc010_esdhc.c - ------------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 7) gen_atmel_mci.c - ------------------ - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 8) mmc_spi.c - ------------ - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 9) mv_sdhci.c - ------------- - This is a component of the SDHCI support, allowing it to run on Marvell - Kirkwood chip. It is probable the SDHCI support will have to be modified to - allow calling functions from this file based on information passed via - platform_data. - - 10) mxcmmc.c - ------------ - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 11) mxsmmc.c - ------------ - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 12) omap_hsmmc.c - ---------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 13) pxa_mmc.c - ------------- - This driver uses the legacy API and is written in a severely ad-hoc manner. - This driver will be removed in favor of pxa_mmc_gen.c, which is proved to work - better and is already well tested. No conversion will be done on this driver - anymore. - - 14) pxa_mmc_gen.c - ----------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 15) s5p_mmc.c - ------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 16) sdhci.c - ----------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple, though it'd be necessary to modify this driver - to also support the Kirkwood series and probably also Tegra series of CPUs. - See the respective parts of this section for details. - - 17) sh_mmcif.c - -------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. - - 18) tegra2_mmc.c - ---------------- - Follows the new API and also has a good encapsulation of the whole driver. The - conversion here will be simple. diff --git a/doc/driver-model/UDM-net.txt b/doc/driver-model/UDM-net.txt deleted file mode 100644 index e2ea8f5a60..0000000000 --- a/doc/driver-model/UDM-net.txt +++ /dev/null @@ -1,434 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Net system analysis -=================== -Marek Vasut -2012-03-03 - -I) Overview ------------ - -The networking subsystem already supports multiple devices. Therefore the -conversion shall not be very hard. - -The network subsystem is operated from net/eth.c, which tracks all registered -ethernet interfaces and calls their particular functions registered via -eth_register(). - -The eth_register() is called from the network driver initialization function, -which in turn is called most often either from "board_net_init()" or -"cpu_net_init()". This function has one important argument, which is the -"struct eth_device", defined at include/net.h: - -struct eth_device { - /* DRIVER: Name of the device */ - char name[NAMESIZE]; - /* DRIVER: MAC address */ - unsigned char enetaddr[6]; - /* DRIVER: Register base address */ - int iobase; - /* CORE: state of the device */ - int state; - - /* DRIVER: Device initialization function */ - int (*init) (struct eth_device*, bd_t*); - /* DRIVER: Function for sending packets */ - int (*send) (struct eth_device*, volatile void* packet, int length); - /* DRIVER: Function for receiving packets */ - int (*recv) (struct eth_device*); - /* DRIVER: Function to cease operation of the device */ - void (*halt) (struct eth_device*); - /* DRIVER: Function to send multicast packet (OPTIONAL) */ - int (*mcast) (struct eth_device*, u32 ip, u8 set); - /* DRIVER: Function to change ethernet MAC address */ - int (*write_hwaddr) (struct eth_device*); - /* CORE: Next device in the linked list of devices managed by net core */ - struct eth_device *next; - /* CORE: Device index */ - int index; - /* DRIVER: Driver's private data */ - void *priv; -}; - -This structure defines the particular driver, though also contains elements that -should not be exposed to the driver, like core state. - -Small, but important part of the networking subsystem is the PHY management -layer, whose drivers are contained in drivers/net/phy. These drivers register in -a very similar manner to network drivers, by calling "phy_register()" with the -argument of "struct phy_driver": - -struct phy_driver { - /* DRIVER: Name of the PHY driver */ - char *name; - /* DRIVER: UID of the PHY driver */ - unsigned int uid; - /* DRIVER: Mask for UID of the PHY driver */ - unsigned int mask; - /* DRIVER: MMDS of the PHY driver */ - unsigned int mmds; - /* DRIVER: Features the PHY driver supports */ - u32 features; - /* DRIVER: Initialize the PHY hardware */ - int (*probe)(struct phy_device *phydev); - /* DRIVER: Reconfigure the PHY hardware */ - int (*config)(struct phy_device *phydev); - /* DRIVER: Turn on the PHY hardware, allow it to send/receive */ - int (*startup)(struct phy_device *phydev); - /* DRIVER: Turn off the PHY hardware */ - int (*shutdown)(struct phy_device *phydev); - /* CORE: Allows this driver to be part of list of drivers */ - struct list_head list; -}; - -II) Approach ------------- - -To convert the elements of network subsystem to proper driver model method, the -"struct eth_device" will have to be split into multiple components. The first -will be a structure defining the driver operations: - -struct eth_driver_ops { - int (*init)(struct instance*, bd_t*); - int (*send)(struct instance*, void *packet, int length); - int (*recv)(struct instance*); - void (*halt)(struct instance*); - int (*mcast)(struct instance*, u32 ip, u8 set); - int (*write_hwaddr)(struct instance*); -}; - -Next, there'll be platform data which will be per-driver and will replace the -"priv" part of "struct eth_device". Last part will be the per-device core state. - -With regards to the PHY part of the API, the "struct phy_driver" is almost ready -to be used with the new driver model approach. The only change will be the -replacement of per-driver initialization functions and removal of -"phy_register()" function in favor or driver model approach. - -III) Analysis of in-tree drivers --------------------------------- - - 1) drivers/net/4xx_enet.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 2) drivers/net/altera_tse.c - --------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 3) drivers/net/armada100_fec.c - ------------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 4) drivers/net/at91_emac.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 5) drivers/net/ax88180.c - ------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 6) drivers/net/ax88796.c - ------------------------ - - This file contains a components of the NE2000 driver, implementing only - different parts on the NE2000 clone AX88796. This being no standalone driver, - no conversion will be done here. - - 7) drivers/net/bfin_mac.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 8) drivers/net/calxedaxgmac.c - ----------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 9) drivers/net/cs8900.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 10) drivers/net/davinci_emac.c - ------------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 11) drivers/net/dc2114x.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 12) drivers/net/designware.c - ---------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 13) drivers/net/dm9000x.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 14) drivers/net/dnet.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 15) drivers/net/e1000.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 16) drivers/net/e1000_spi.c - --------------------------- - - Driver for the SPI bus integrated on the Intel E1000. This is not part of the - network stack. - - 17) drivers/net/eepro100.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 18) drivers/net/enc28j60.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 19) drivers/net/ep93xx_eth.c - ---------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 20) drivers/net/ethoc.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 21) drivers/net/fec_mxc.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 22) drivers/net/fsl_mcdmafec.c - ------------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 23) drivers/net/fsl_mdio.c - -------------------------- - - This file contains driver for FSL MDIO interface, which is not part of the - networking stack. - - 24) drivers/net/ftgmac100.c - --------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 25) drivers/net/ftmac100.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 26) drivers/net/greth.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 27) drivers/net/inca-ip_sw.c - ---------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 28) drivers/net/ks8695eth.c - --------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 29) drivers/net/lan91c96.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 30) drivers/net/macb.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 31) drivers/net/mcffec.c - ------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 32) drivers/net/mcfmii.c - ------------------------ - - This file contains MII interface driver for MCF FEC. - - 33) drivers/net/mpc512x_fec.c - ----------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 34) drivers/net/mpc5xxx_fec.c - ----------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 35) drivers/net/mvgbe.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 36) drivers/net/natsemi.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 37) drivers/net/ne2000_base.c - ----------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. This driver contains the core - implementation of NE2000, which needs a few external functions, implemented by - AX88796, NE2000 etc. - - 38) drivers/net/ne2000.c - ------------------------ - - This file implements external functions necessary for native NE2000 compatible - networking card to work. - - 39) drivers/net/netarm_eth.c - ---------------------------- - - This driver uses the old, legacy, network API and will either have to be - converted or removed. - - 40) drivers/net/netconsole.c - ---------------------------- - - This is actually an STDIO driver. - - 41) drivers/net/ns8382x.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 42) drivers/net/pcnet.c - ----------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 43) drivers/net/plb2800_eth.c - ----------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 44) drivers/net/rtl8139.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 45) drivers/net/rtl8169.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 46) drivers/net/sh_eth.c - ------------------------ - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 47) drivers/net/smc91111.c - -------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 48) drivers/net/smc911x.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 49) drivers/net/tsec.c - ---------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 50) drivers/net/tsi108_eth.c - ---------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 51) drivers/net/uli526x.c - ------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 52) drivers/net/vsc7385.c - ------------------------- - - This is a driver that only uploads firmware to a switch. This is not subject - of conversion. - - 53) drivers/net/xilinx_axi_emac.c - --------------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. - - 54) drivers/net/xilinx_emaclite.c - --------------------------------- - - This driver uses the standard new networking API, therefore there should be no - obstacles throughout the conversion process. diff --git a/doc/driver-model/UDM-pci.txt b/doc/driver-model/UDM-pci.txt deleted file mode 100644 index 6a592b3368..0000000000 --- a/doc/driver-model/UDM-pci.txt +++ /dev/null @@ -1,257 +0,0 @@ -The U-Boot Driver Model Project -=============================== -PCI subsystem analysis -====================== - -Pavel Herrmann -2012-03-17 - -I) Overview ------------ - - U-Boot already supports multiple PCI busses, stored in a linked-list of - pci_controller structures. This structure contains generic driver data, bus - interface operations and private data for the driver. - - Bus interface operations for PCI are (names are self-explanatory): - - read_byte() - read_word() - read_dword() - write_byte() - write_word() - write_dword() - - Each driver has to implement dword operations, and either implement word and - byte operations, or use shared $operation_config_$type_via_dword (eg. - read_config_byte_via_dword and similar) function. These functions are used - for config space I/O (read_config_dword and similar functions of the PCI - subsystem), which is used to configure the connected devices for standard MMIO - operations. All data transfers by respective device drivers are then done by - MMIO - - Each driver also defines a separate init function, which has unique symbol - name, and thus more drivers can be compiled in without colliding. This init - function is typically called from pci_init_board(), different for each - particular board. - - Some boards also define a function called fixup_irq, which gets called after - scanning the PCI bus for devices, and should dismiss any interrupts. - - Several drivers are also located in arch/ and should be moved to drivers/pci. - -II) Approach ------------- - - The pci_controller structure needs to be broken down to fit the new driver - model. Due to a large number of members, this will be done through three - distinct accessors, one for memory regions, one for config table and one for - everything else. That will make the pci_ops structure look like this: - - struct pci_ops { - int (*read_byte)(struct instance *bus, pci_dev_t *dev, int addr, - u8 *buf); - int (*read_word)(struct instance *bus, pci_dev_t *dev, int addr, - u16 *buf); - int (*read_dword)(struct instance *bus, pci_dev_t *dev, int addr, - u32 *buf); - int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr, - u8 val); - int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr, - u8 val); - int (*write_dword)(struct instance *bus, pci_dev_t *dev, int addr, - u32 val); - void (*fixup_irq)(struct instance *bus, pci_dev_t *dev); - struct pci_region* (*get_region)(struct instance *, uint num); - struct pci_config_table* (*get_cfg_table)(struct instance *bus); - uint (*get_option)(struct instance * bus, enum pci_option_code op); - } - - enum pci_option_code { - PCI_OPT_BUS_NUMBER=0, - PCI_OPT_REGION_COUNT, - PCI_OPT_INDIRECT_TYPE, - PCI_OPT_AUTO_MEM, - PCI_OPT_AUTO_IO, - PCI_OPT_AUTO_PREFETCH, - PCI_OPT_AUTO_FB, - PCI_OPT_CURRENT_BUS, - PCI_OPT_CFG_ADDR, - } - - The return value for get_option will be an unsigned integer value for any - option code. If the option currently is a pointer to pci_region, it will - return an index for get_region function. Special case has to be made for - PCI_OPT_CFG_ADDR, which should be interpreted as a pointer, but it is only - used for equality in find_hose_by_cfg_addr, and thus can be returned as an - uint. Other function using cfg_addr value are read/write functions for - specific drivers (especially ops for indirect bridges), and thus have access - to private_data of the driver instance. - - The config table accessor will return a pointer to a NULL-terminated array of - pci_config_table, which is supplied by the board in platform_data, or NULL if - the board didn't specify one. This table is used to override PnP - auto-initialization, or to specific initialization functions for non-PNP - devices. - - Transparent PCI-PCI bridges will get their own driver, and will forward all - operations to operations of their parent bus. This however makes it - impossible to use instances to identify devices, as not all devices will be - directly visible to the respective bus driver. - - Init functions of controller drivers will be moved to their respective - probe() functions, in accordance to the driver model. - - The PCI core will handle all mapping functions currently found in pci.c, as - well as proxy functions for read/write operations of the drivers. The PCI - core will also handle bus scanning and device configuration. - - The PnP helper functions currently in pci_auto.c will also be a part of PCI - core, but they will be exposed only to PCI controller drivers, not to other - device drivers. - - The PCI API for device drivers will remain largely unchanged, most drivers - will require no changes at all, and all modifications will be limited to - changing the pci_controlle into instance*. - -III) Analysis of in-tree drivers --------------------------------- - - A) drivers in drivers/pci/ - -------------------------- - - 1) pci_indirect.c - ----------------- - Shared driver for indirect PCI bridges, several CONFIG macros - will - require significant cleanup. - - 2) pci_ixp.c - ------------ - Standard driver, specifies all read/write functions separately. - - 3) pci_sh4.c - ------------ - Shared init function for SH4 drivers, uses dword for read/write ops. - - 4) pci_sh7751.c - --------------- - Standard driver, uses SH4 shared init. - - 5) pci_sh7780.c - --------------- - Standard driver, uses SH4 shared init. - - 6) tsi108_pci.c - --------------- - Standard driver, uses dword for read/write ops. - - 7) fsl_pci_init.c - ----------------- - Driver for PCI and PCI-e, uses indirect functions. - - 8) pci_ftpci100.c - ----------------- - Standard driver, uses indirect functions, has separate scan/setup - functions. - - B) driver in arch/ - ------------------ - - 1) x86/lib/pci_type1.c - ---------------------- - Standard driver, specifies all read/write functions separately. - - 2) m68k/cpu/mcf5445x/pci.c - -------------------------- - Standard driver, specifies all read/write functions separately. - - 3) m68k/cpu/mcf547x_8x/pci.c - ---------------------------- - Standard driver, specifies all read/write functions separately. - - 4) powerpc/cpu/mpc824x/pci.c - ---------------------------- - Standard driver, uses indirect functions, does not setup HW. - - 5) powerpc/cpu/mpc8260/pci.c - ---------------------------- - Standard driver, uses indirect functions. - - 6) powerpc/cpu/ppc4xx/4xx_pci.c - ------------------------------- - Standard driver, uses indirect functions. - - 7) powerpc/cpu/ppc4xx/4xx_pcie.c - -------------------------------- - PCI-e driver, specifies all read/write functions separately. - - 8) powerpc/cpu/mpc83xx/pci.c - ---------------------------- - Standard driver, uses indirect functions. - - 9) powerpc/cpu/mpc83xx/pcie.c - ----------------------------- - PCI-e driver, specifies all read/write functions separately. - - 10) powerpc/cpu/mpc5xxx/pci_mpc5200.c - ------------------------------------- - Standard driver, uses dword for read/write ops. - - 11) powerpc/cpu/mpc512x/pci.c - ----------------------------- - Standard driver, uses indirect functions. - - 12) powerpc/cpu/mpc85xx/pci.c - ----------------------------- - Standard driver, uses indirect functions, has two busses. - - C) drivers in board/ - -------------------- - - 1) eltec/elppc/pci.c - -------------------- - Standard driver, uses indirect functions. - - 2) amirix/ap1000/pci.c - ---------------------- - Standard driver, specifies all read/write functions separately. - - 3) prodrive/p3mx/pci.c - ---------------------- - Standard driver, uses dword for read/write ops, has two busses. - - 4) esd/cpci750/pci.c - -------------------- - Standard driver, uses dword for read/write ops, has two busses. - - 5) esd/common/pci.c - ------------------- - Standard driver, uses dword for read/write ops. - - 6) dave/common/pci.c - -------------------- - Standard driver, uses dword for read/write ops. - - 7) ppmc7xx/pci.c - ---------------- - Standard driver, uses indirect functions. - - 9) Marvell/db64360/pci.c - ------------------------ - Standard driver, uses dword for read/write ops, has two busses. - - 10) Marvell/db64460/pci.c - ------------------------- - Standard driver, uses dword for read/write ops, has two busses. - - 11) evb64260/pci.c - ------------------ - Standard driver, uses dword for read/write ops, has two busses. - - 12) armltd/integrator/pci.c - --------------------------- - Standard driver, specifies all read/write functions separately. - - All drivers will be moved to drivers/pci. Several drivers seem - similar/identical, especially those located under board, and may be merged - into one. diff --git a/doc/driver-model/UDM-pcmcia.txt b/doc/driver-model/UDM-pcmcia.txt deleted file mode 100644 index fc31461ca7..0000000000 --- a/doc/driver-model/UDM-pcmcia.txt +++ /dev/null @@ -1,78 +0,0 @@ -The U-Boot Driver Model Project -=============================== -PCMCIA analysis -=============== -Viktor Krivak -2012-03-17 - -I) Overview ------------ - - U-boot implements only 2 methods to interoperate with pcmcia. One to turn - device on and other to turn device off. Names of these methods are usually - pcmcia_on() and pcmcia_off() without any parameters. Some files in driver - directory implements only internal API. These methods aren't used outside - driver directory and they are not converted to new driver model. - -II) Approach ------------ - - 1) New API - ---------- - - Current API is preserved and all internal methods are hiden. - - struct ops { - void (*pcmcia_on)(struct instance *i); - void (*pcmcia_off)(struct instance *i); - } - - 2) Conversion - ------------- - - In header file pcmcia.h are some other variables which are used for - additional configuration. But all have to be moved to platform data or to - specific driver implementation. - - 3) Platform data - ---------------- - - Many boards have custom implementation of internal API. Pointers to these - methods are stored in platform_data. But the most implementations for Intel - 82365 and compatible PC Card controllers and Yenta-compatible - PCI-to-CardBus controllers implement whole API per board. In these cases - pcmcia_on() and pcmcia_off() behave only as wrappers and call specific - board methods. - -III) Analysis of in-tree drivers --------------------------------- - - 1) i82365.c - ----------- - Driver methods have different name i82365_init() and i82365_exit but - all functionality is the same. Board files board/atc/ti113x.c and - board/cpc45/pd67290.c use their own implementation of these method. - In this case all methods in driver behave only as wrappers. - - 2) marubun_pcmcia.c - ------------------- - Meets standard API behaviour. Simple conversion. - - 3) mpc8xx_pcmcia.c - ------------------ - Meets standard API behaviour. Simple conversion. - - 4) rpx_pcmcia.c - --------------- - Implements only internal API used in other drivers. Non of methods - implemented here are used outside driver model. - - 5) ti_pci1410a.c - ---------------- - Has different API but methods in this file are never called. Probably - dead code. - - 6)tqm8xx_pcmcia.c - ----------------- - Implements only internal API used in other drivers. Non of methods - implemented here are used outside driver model. diff --git a/doc/driver-model/UDM-power.txt b/doc/driver-model/UDM-power.txt deleted file mode 100644 index 9ac1a5fbb5..0000000000 --- a/doc/driver-model/UDM-power.txt +++ /dev/null @@ -1,88 +0,0 @@ -The U-Boot Driver Model Project -=============================== -POWER analysis -============== -Viktor Krivak -2012-03-09 - -I) Overview ------------ - - 1) Actual state - --------------- - - At this moment power doesn't contain API. There are many methods for - initialization of some board specific functions but only few does what is - expected. Basically only one file contains something meaningful for this - driver. - - 2) Current implementation - ------------------------- - - In file twl6030.c are methods twl6030_stop_usb_charging() and - twl6030_start_usb_charging() for start and stop charging from USB. There are - also methods to get information about battery state and initialization of - battery charging. Only these methods are used in converted API. - - -II) Approach ------------- - - 1) New API - ---------- - - New API implements only functions specific for managing power. All board - specific init methods are moved to other files. Name of methods are - self-explanatory. - - struct ops { - void (*start_usb_charging)(struct instance *i); - void (*stop_usb_charging)(struct instance *i); - int (*get_battery_current)(struct instance *i); - int (*get_battery_voltage)(struct instance *i); - void (*init_battery_charging)(struct instance *i); - } - - 2) Conversions of other methods - ------------------------------- - - Methods that can't be converted to new API are moved to board file or to - special file for board hacks. - -III) Analysis of in-tree drivers --------------------------------- - - 1) ftpmu010.c - ------------- - All methods of this file are moved to another location. - void ftpmu010_32768osc_enable(void): Move to boards hacks - void ftpmu010_mfpsr_select_dev(unsigned int dev): Move to board file - arch/nds32/lib/board.c - void ftpmu010_mfpsr_diselect_dev(unsigned int dev): Dead code - void ftpmu010_dlldis_disable(void): Dead code - void ftpmu010_sdram_clk_disable(unsigned int cr0): Move to board file - arch/nds32/lib/board.c - void ftpmu010_sdramhtc_set(unsigned int val): Move to board file - arch/nds32/lib/board.c - - 2) twl4030.c - ------------ - All methods of this file are moved to another location. - void twl4030_power_reset_init(void): Move to board hacks - void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, u8 dev_grp, - u8 dev_grp_sel): Move to board hacks - void twl4030_power_init(void): Move to board hacks - void twl4030_power_mmc_init(void): Move to board hacks - - 3) twl6030.c - ------------ - Some methods are converted to new API and rest are moved to another location. - void twl6030_stop_usb_charging(void): Convert to new API - void twl6030_start_usb_charging(void): Convert to new API - int twl6030_get_battery_current(void): Convert to new API - int twl6030_get_battery_voltage(void): Convert to new API - void twl6030_init_battery_charging(void): Convert to new API - void twl6030_power_mmc_init(): Move to board file - drivers/mmc/omap_hsmmc.c - void twl6030_usb_device_settings(): Move to board file - drivers/usb/musb/omap3.c diff --git a/doc/driver-model/UDM-rtc.txt b/doc/driver-model/UDM-rtc.txt deleted file mode 100644 index 5d9fb333ba..0000000000 --- a/doc/driver-model/UDM-rtc.txt +++ /dev/null @@ -1,258 +0,0 @@ -============================= -RTC device subsystem analysis -============================= - -Tomas Hlavacek -2012-03-10 - -I) Overview ------------ - -U-Boot currently implements one common API for RTC devices. The interface -is defined in include/rtc.h and comprises of functions and structures: - - struct rtc_time { - int tm_sec; - int tm_min; - int tm_hour; - int tm_mday; - int tm_mon; - int tm_year; - int tm_wday; - int tm_yday; - int tm_isdst; - }; - - int rtc_get (struct rtc_time *); - int rtc_set (struct rtc_time *); - void rtc_reset (void); - -The functions are implemented by a proper device driver in drivers/rtc -directory and the driver to be compiled in is selected in a Makefile. -Drivers are mutually exclusive. - -Drivers depends on date code in drivers/rtc/date.c and naturally on board -specific data. - -II) Approach ------------- - - 1) New API - ---------- - In the UDM each rtc driver would register itself by a function - - int rtc_device_register(struct instance *i, - struct rtc_device_ops *o); - - The structure being defined as follows: - - struct rtc_device_ops { - int (*get_time)(struct instance *i, struct rtc_time *t); - int (*set_time)(struct instance *i, struct rtc_time *t); - int (*reset)(struct instance *i); - }; - - - 2) Conversion thougths - ---------------------- - U-Boot RTC drivers exports the same functions and therefore the conversion - of the drivers is straight-forward. There is no initialization needed. - - -III) Analysis of in-tree drivers --------------------------------- - - 1) drivers/rtc/rv3029.c - ----------------------- - The driver is standard rtc. Simple conversion is possible. - - - 2) drivers/rtc/s3c24x0_rtc.c - ---------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 3) drivers/rtc/pt7c4338.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 4) drivers/rtc/mvrtc.c - ---------------------- - The driver is standard rtc. Simple conversion is possible. - - - 5) drivers/rtc/ftrtc010.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 6) drivers/rtc/mpc5xxx.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 7) drivers/rtc/ds164x.c - ----------------------- - The driver is standard rtc. Simple conversion is possible. - - - 8) drivers/rtc/rs5c372.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 9) drivers/rtc/m41t94.c - ----------------------- - The driver is standard rtc. Simple conversion is possible. - - - 10) drivers/rtc/mc13xxx-rtc.c - ----------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 11) drivers/rtc/mcfrtc.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 12) drivers/rtc/davinci.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 13) drivers/rtc/rx8025.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 14) drivers/rtc/bfin_rtc.c - -------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 15) drivers/rtc/m41t62.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 16) drivers/rtc/ds1306.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 17) drivers/rtc/mpc8xx.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 18) drivers/rtc/ds3231.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 19) drivers/rtc/ds12887.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 20) drivers/rtc/ds1302.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 21) drivers/rtc/ds1374.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 22) drivers/rtc/ds174x.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 23) drivers/rtc/m41t60.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 24) drivers/rtc/m48t35ax.c - -------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 25) drivers/rtc/pl031.c - ----------------------- - The driver is standard rtc. Simple conversion is possible. - - - 26) drivers/rtc/x1205.c - ----------------------- - The driver is standard rtc. Simple conversion is possible. - - - 27) drivers/rtc/m41t11.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 28) drivers/rtc/pcf8563.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 29) drivers/rtc/mk48t59.c - ------------------------- - Macros needs cleanup. Besides that the driver is standard rtc. - Simple conversion is possible. - - - 30) drivers/rtc/mxsrtc.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 31) drivers/rtc/ds1307.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 32) drivers/rtc/ds1556.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 33) drivers/rtc/rtc4543.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 34) drivers/rtc/s3c44b0_rtc.c - ----------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 35) drivers/rtc/ds1337.c - ------------------------ - The driver is standard rtc. Simple conversion is possible. - - - 36) drivers/rtc/isl1208.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 37) drivers/rtc/max6900.c - ------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 38) drivers/rtc/mc146818.c - -------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 39) drivers/rtc/at91sam9_rtt.c - ------------------------------ - The driver is standard rtc. Simple conversion is possible. diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt deleted file mode 100644 index 1011c32d18..0000000000 --- a/doc/driver-model/UDM-serial.txt +++ /dev/null @@ -1,179 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Serial I/O analysis -=================== -Marek Vasut -2012-02-20 - -I) Overview ------------ - -The serial port support currently requires the driver to export the following -functions: - - serial_putc() ...... Output a character - serial_puts() ...... Output string, often done using serial_putc() - serial_tstc() ...... Test if incoming character is in a buffer - serial_getc() ...... Retrieve incoming character - serial_setbrg() .... Configure port options - serial_init() ...... Initialize the hardware - -The simpliest implementation, supporting only one port, simply defines these six -functions and calls them. Such calls are scattered all around U-Boot, especiall -serial_putc(), serial_puts(), serial_tstc() and serial_getc(). The serial_init() -and serial_setbrg() are often called from platform-dependent places. - -It's important to consider current implementation of CONFIG_SERIAL_MULTI though. -This resides in common/serial.c and behaves as a multiplexer for serial ports. -This, by calling serial_assign(), allows user to switch I/O from one serial port -to another. Though the environmental variables "stdin", "stdout", "stderr" -remain set to "serial". - -These variables are managed by the IOMUX. This resides in common/iomux.c and -manages all console input/output from U-Boot. For serial port, only one IOMUX is -always registered, called "serial" and the switching of different serial ports -is done by code in common/serial.c. - -On a final note, it's important to mention function default_serial_console(), -which is platform specific and reports the default serial console for the -platform, unless proper environment variable overrides this. - -II) Approach ------------- - -Drivers not using CONFIG_SERIAL_MULTI already will have to be converted to -similar approach. The probe() function of a driver will call a function -registering the driver with a STDIO subsystem core, stdio_device_register(). - -The serial_init() function will now be replaced by probe() function of the -driver, the rest of the components of the driver will be converted to standard -STDIO driver calls. See [ UDM-stdio.txt ] for details. - -The serial_setbrg() function depends on global data pointer. This is wrong, -since there is likely to be user willing to configure different baudrate on two -different serial ports. The function will be replaced with STDIO's "conf()" -call, with STDIO_CONFIG_SERIAL_BAUDRATE argument. - -III) Analysis of in-tree drivers --------------------------------- - - 1) altera_jtag_uart.c - --------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 2) altera_uart.c - ---------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 3) arm_dcc.c - ------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible, unless used - with CONFIG_ARM_DCC_MULTI. Then it registers another separate IOMUX. - - 4) atmel_usart.c - ---------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 5) mcfuart.c - ------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 6) ns16550.c - ------------ - This driver seems complicated and certain consideration will need to be made - during conversion. This driver is implemented in very universal manner, - therefore it'll be necessary to properly design it's platform_data. - - 7) ns9750_serial.c - ------------------ - Unmaintained port. Code got removed. - - 8) opencores_yanu.c - ------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 9) s3c4510b_uart.c - ------------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 10) sandbox.c - ------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 11) serial.c - ------------ - This is a complementary part of NS16550 UART driver, see above. - - 12) serial_clps7111.c - --------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 13) serial_imx.c - ---------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver - might be removed in favor of serial_mxc.c . - - 14) serial_ixp.c - ---------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 15) serial_ks8695.c - ------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 16) serial_max3100.c - -------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 17) serial_mxc.c - ---------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 18) serial_netarm.c - ------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 19) serial_pl01x.c - ------------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this - driver in fact contains two drivers in total. - - 20) serial_pxa.c - ---------------- - This driver is a bit complicated, but due to clean support for - CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the - conversion process. - - 21) serial_s3c24x0.c - -------------------- - This driver, being quite ad-hoc might need some work to bring back to shape. - - 22) serial_s3c44b0.c - -------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 23) serial_s5p.c - ---------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 24) serial_sa1100.c - ------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 25) serial_sh.c - --------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 26) serial_xuartlite.c - ---------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 27) usbtty.c - ------------ - This driver seems very complicated and entangled with USB framework. The - conversion might be complicated here. - - 28) arch/powerpc/cpu/mpc512x/serial.c - ------------------------------------- - This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to - proper place. diff --git a/doc/driver-model/UDM-spi.txt b/doc/driver-model/UDM-spi.txt deleted file mode 100644 index 7442a32bd0..0000000000 --- a/doc/driver-model/UDM-spi.txt +++ /dev/null @@ -1,200 +0,0 @@ -The U-Boot Driver Model Project -=============================== -SPI analysis -============ -Viktor Krivak -2012-03-03 - -I) Overview ------------ - - 1) The SPI driver - ----------------- - - At this moment U-Boot provides standard API that consist of 7 functions: - - void spi_init(void); - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); - void spi_free_slave(struct spi_slave *slave); - int spi_claim_bus(struct spi_slave *slave); - void spi_release_bus(struct spi_slave *slave); - int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags); - int spi_cs_is_valid(unsigned int bus, unsigned int cs); - void spi_cs_activate(struct spi_slave *slave); - void spi_cs_deactivate(struct spi_slave *slave); - void spi_set_speed(struct spi_slave *slave, uint hz); - - Method spi_init() is usually empty. All necessary configuration are sets by - spi_setup_slave(). But this configuration is usually stored only in memory. - No real hardware sets are made. All hardware settings are provided by method - spi_claim_bus(). This method claims the bus and it can't be claimed again - until it's release. That's mean all calls of method spi_claim_bus() will - fail. But lots of cpu implementation don't meet this behaviour. - Method spi_release_bus() does exact opposite. It release bus directly by - some hardware sets. spi_free_slave() only free memory allocated by - spi_setup_slave(). Method spi_xfer() do actually read and write operation - throw specified bus and cs. Other methods are self explanatory. - - 2) Current limitations - ---------------------- - - Theoretically at this moment api allows use more then one bus per device at - the time. But in real this can be achieved only when all buses have their - own base addresses in memory. - - -II) Approach ------------- - - 1) Claiming bus - --------------- - - The current api cannot be used because struct spi_slave have to be in - private data. In that case user are prohibited to use different bus on one - device at same time. But when base memory address for bus are different. - It's possible make more instance of this driver. Otherwise it can't can be - done because of hardware limitation. - - 2) API change - ------------- - - Method spi_init() is moved to probe. Methods spi_setup_slave() and - spi_claim_bus() are joined to one method. This method checks if desired bus - exists and is available then configure necessary hardware and claims bus. - Method spi_release_bus() and spi_free_slave() are also joined to meet this - new approach. Other function remain same. Only struct spi_slave was change - to instance. - - struct ops { - int (*spi_request_bus)(struct instance *i, unsigned int bus, - unsigned int cs, unsigned int max_hz, - unsigned int mode); - void (*spi_release_bus)(struct instance *i); - int (*spi_xfer) (struct instance *i, unsigned int bitlen, - const void *dout, void *din, unsigned long flags); - int (*spi_cs_is_valid)(struct instance *i, unsigned int bus, - unsigned int cs); - void (*spi_cs_activate)(struct instance *i); - void (*spi_cs_deactivate)(struct instance *i); - void (*spi_set_speed)(struct instance *i, uint hz); - } - - 3) Legacy API - ------------- - - To easy conversion of the whole driver. Original and new api can exist next - to each other. New API is designed to be only a wrapper that extracts - necessary information from private_data and use old api. When driver can - use more than one bus at the time. New API require multiple instance. One - for each bus. In this case spi_slave have to be copied in each instance. - - 4) Conversion TIME-LINE - ----------------------- - - To prevent build corruption api conversion have to be processed in several - independent steps. In first step all old API methods are renamed. After that - new API and core function are implemented. Next step is conversion of all - board init methods to set platform data. After all these steps it is possible - to start conversion of all remaining calls. This procedure guarantees that - build procedure and binaries are never broken. - -III) Analysis of in-tree drivers --------------------------------- - - 1) altera_spi.c - --------------- - All methods have designated structure. Simple conversion possible. - - 2) andes_spi.c - -------------- - All methods have designated structure. Simple conversion possible. - - 3) andes_spi.h - -------------- - Support file for andes_spi.c. No conversion is needed. - - 4) armada100_spi.c - ------------------ - All methods have designated structure. Simple conversion possible. - - 5) atmel_dataflash_spi.c - ------------------------ - Wrong placement. Will be moved to another location. - - 6) atmel_spi.c - -------------- - Supports more than one bus. Need some minor change. - - 7) atmel_spi.h - -------------- - Support file for andes_spi.c. No conversion is needed. - - 8) bfin_spi.c - ------------- - Supports more than one bus. Need some minor change. - - 9) cf_spi.c - ----------- - Cooperate with some cpu specific methods from other files. Hard conversion. - - 10) davinci_spi.c - ----------------- - All methods have designated structure. Simple conversion possible. - - 11) davinci_spi.h - ----------------- - Support file for davinci_spi.h. No conversion is needed. - - 12) fsl_espi.c - -------------- - All methods have designated structure. Simple conversion possible. - - 13) kirkwood_spi.c - ------------------ - All methods have designated structure. Simple conversion possible. - - 14) mpc8xxx_spi.c - ----------------- - All methods have designated structure. Simple conversion possible. - - 15) mpc52xx_spi.c - ----------------- - All methods have designated structure. Simple conversion possible. - - 16) mxc_spi.c - ------------- - All methods have designated structure. Simple conversion possible. - - 17) mxs_spi.c - ------------- - All methods have designated structure. Simple conversion possible. - - 18) oc_tiny_spi.c - ----------------- - Supports more than one bus. Need some minor change. - - 19) omap3_spi.c - --------------- - Supports more than one bus. Need some minor change. - - 20) omap3_spi.h - --------------- - Support file for omap3_spi.c. No conversion is needed. - - 21) sh_spi.c - ------------ - All methods have designated structure. Simple conversion possible. - - 22) sh_spi.h - ------------ - Support file for sh_spi.h. No conversion is needed. - - 23) soft_spi.c - -------------- - Use many board specific method linked from other files. Need careful debugging. - - 24) tegra2_spi.c - ---------------- - Some hardware specific problem when releasing bus. diff --git a/doc/driver-model/UDM-stdio.txt b/doc/driver-model/UDM-stdio.txt deleted file mode 100644 index a6c484f37c..0000000000 --- a/doc/driver-model/UDM-stdio.txt +++ /dev/null @@ -1,191 +0,0 @@ -The U-Boot Driver Model Project -=============================== -I/O system analysis -=================== -Marek Vasut -2012-02-20 - -I) Overview ------------ - -The console input and output is currently done using the STDIO subsystem in -U-Boot. The design of this subsystem is already flexible enough to be easily -converted to new driver model approach. Minor changes will need to be done -though. - -Each device that wants to register with STDIO subsystem has to define struct -stdio_dev, defined in include/stdio_dev.h and containing the following fields: - -struct stdio_dev { - int flags; /* Device flags: input/output/system */ - int ext; /* Supported extensions */ - char name[16]; /* Device name */ - -/* GENERAL functions */ - - int (*start) (void); /* To start the device */ - int (*stop) (void); /* To stop the device */ - -/* OUTPUT functions */ - - void (*putc) (const char c); /* To put a char */ - void (*puts) (const char *s); /* To put a string (accelerator) */ - -/* INPUT functions */ - - int (*tstc) (void); /* To test if a char is ready... */ - int (*getc) (void); /* To get that char */ - -/* Other functions */ - - void *priv; /* Private extensions */ - struct list_head list; -}; - -Currently used flags are DEV_FLAGS_INPUT, DEV_FLAGS_OUTPUT and DEV_FLAGS_SYSTEM, -extensions being only one, the DEV_EXT_VIDEO. - -The private extensions are now used as a per-device carrier of private data and -finally list allows this structure to be a member of linked list of STDIO -devices. - -The STDIN, STDOUT and STDERR routing is handled by environment variables -"stdin", "stdout" and "stderr". By configuring the variable to the name of a -driver, functions of such driver are called to execute that particular -operation. - -II) Approach ------------- - - 1) Similarity of serial, video and keyboard drivers - --------------------------------------------------- - - All of these drivers can be unified under the STDIO subsystem if modified - slightly. The serial drivers basically define both input and output functions - and need function to configure baudrate. The keyboard drivers provide only - input. On the other hand, video drivers provide output, but need to be - configured in certain way. This configuration might be dynamic, therefore the - STDIO has to be modified to provide such flexibility. - - 2) Unification of serial, video and keyboard drivers - ---------------------------------------------------- - - Every STDIO device would register a structure containing operation it supports - with the STDIO core by calling: - - int stdio_device_register(struct instance *i, struct stdio_device_ops *o); - - The structure being defined as follows: - - struct stdio_device_ops { - void (*putc)(struct instance *i, const char c); - void (*puts)(struct instance *i, const char *s); /* OPTIONAL */ - - int (*tstc)(struct instance *i); - int (*getc)(struct instance *i); - - int (*init)(struct instance *i); - int (*exit)(struct instance *i); - int (*conf)(struct instance *i, enum stdio_config c, const void *data); - }; - - The "putc()" function will emit a character, the "puts()" function will emit a - string. If both of these are set to NULL, the device is considered STDIN only, - aka input only device. - - The "getc()" retrieves a character from a STDIN device, while "tstc()" tests - if there is a character in the buffer of STDIN device. In case these two are - set to NULL, this device is STDOUT / STDERR device. - - Setting all "putc()", "puts()", "getc()" and "tstc()" calls to NULL isn't an - error condition, though such device does nothing. By instroducing tests for - these functions being NULL, the "flags" and "ext" fields from original struct - stdio_dev can be eliminated. - - The "init()" and "exit()" calls are replacement for "start()" and "exit()" - calls in the old approach. The "priv" part of the old struct stdio_dev will be - replaced by common private data in the driver model and the struct list_head - list will be eliminated by introducing common STDIO core, that tracks all the - STDIO devices. - - Lastly, the "conf()" call will allow the user to configure various options of - the driver. The enum stdio_config contains all possible configuration options - available to the STDIO devices, const void *data being the argument to be - configured. Currently, the enum stdio_config will contain at least the - following options: - - enum stdio_config { - STDIO_CONFIG_SERIAL_BAUDRATE, - }; - - 3) Transformation of stdio routing - ---------------------------------- - - By allowing multiple instances of drivers, the environment variables "stdin", - "stdout" and "stderr" can no longer be set to the name of the driver. - Therefore the STDIO core, tracking all of the STDIO devices in the system will - need to have a small amount of internal data for each device: - - struct stdio_device_node { - struct instance *i; - struct stdio_device_ops *ops; - uint8_t id; - uint8_t flags; - struct list_head list; - } - - The "id" is the order of the instance of the same driver. The "flags" variable - allows multiple drivers to be used at the same time and even for different - purpose. The following flags will be defined: - - STDIO_FLG_STDIN ..... This device will be used as an input device. All input - from all devices with this flag set will be received - and passed to the upper layers. - STDIO_FLG_STDOUT .... This device will be used as an output device. All - output sent to stdout will be routed to all devices - with this flag set. - STDIO_FLG_STDERR .... This device will be used as an standard error output - device. All output sent to stderr will be routed to - all devices with this flag set. - - The "list" member of this structure allows to have a linked list of all - registered STDIO devices. - -III) Analysis of in-tree drivers --------------------------------- - -For in-depth analysis of serial port drivers, refer to [ UDM-serial.txt ]. -For in-depth analysis of keyboard drivers, refer to [ UDM-keyboard.txt ]. -For in-depth analysis of video drivers, refer to [ UDM-video.txt ]. - - 1) arch/blackfin/cpu/jtag-console.c - ----------------------------------- - This driver is a classic STDIO driver, no problem with conversion is expected. - - 2) board/mpl/pati/pati.c - ------------------------ - This driver registers with the STDIO framework, though it uses a lot of ad-hoc - stuff which will need to be sorted out. - - 3) board/netphone/phone_console.c - --------------------------------- - This driver is a classic STDIO driver, no problem with conversion is expected. - - 4) drivers/net/netconsole.c - --------------------------- - This driver is a classic STDIO driver, no problem with conversion is expected. - -IV) Other involved files (To be removed) ----------------------------------------- - -common/cmd_console.c -common/cmd_log.c -common/cmd_terminal.c -common/console.c -common/fdt_support.c -common/iomux.c -common/lcd.c -common/serial.c -common/stdio.c -common/usb_kbd.c -doc/README.iomux diff --git a/doc/driver-model/UDM-tpm.txt b/doc/driver-model/UDM-tpm.txt deleted file mode 100644 index 91a953a72e..0000000000 --- a/doc/driver-model/UDM-tpm.txt +++ /dev/null @@ -1,48 +0,0 @@ -The U-Boot Driver Model Project -=============================== -TPM system analysis -=================== -Marek Vasut -2012-02-23 - -I) Overview ------------ - -There is currently only one TPM chip driver available and therefore the API -controlling it is very much based on this. The API is very simple: - - int tis_open(void); - int tis_close(void); - int tis_sendrecv(const u8 *sendbuf, size_t send_size, - u8 *recvbuf, size_t *recv_len); - -The command operating the TPM chip only provides operations to send and receive -bytes from the chip. - -II) Approach ------------- - -The API can't be generalised too much considering there's only one TPM chip -supported. But it's a good idea to split the tis_sendrecv() function in two -functions. Therefore the new API will use register the TPM chip by calling: - - tpm_device_register(struct instance *i, const struct tpm_ops *ops); - -And the struct tpm_ops will contain the following members: - - struct tpm_ops { - int (*tpm_open)(struct instance *i); - int (*tpm_close)(struct instance *i); - int (*tpm_send)(const uint8_t *buf, const size_t size); - int (*tpm_recv)(uint8_t *buf, size_t *size); - }; - -The behaviour of "tpm_open()" and "tpm_close()" will basically copy the -behaviour of "tis_open()" and "tis_close()". The "tpm_send()" will be based on -the "tis_senddata()" and "tis_recv()" will be based on "tis_readresponse()". - -III) Analysis of in-tree drivers --------------------------------- - -There is only one in-tree driver present, the "drivers/tpm/generic_lpc_tpm.c", -which will be simply converted as outlined in previous chapter. diff --git a/doc/driver-model/UDM-twserial.txt b/doc/driver-model/UDM-twserial.txt deleted file mode 100644 index 289416acde..0000000000 --- a/doc/driver-model/UDM-twserial.txt +++ /dev/null @@ -1,47 +0,0 @@ -================================== -TWserial device subsystem analysis -================================== - -Tomas Hlavacek -2012-03-21 - -I) Overview ------------ - -U-Boot currently implements one common API for TWSerial devices. The interface -is defined in include/tws.h and comprises of functions: - - int tws_read(uchar *buffer, int len); - int tws_write(uchar *buffer, int len); - -The functions are implemented by a proper device driver in drivers/twserial -directory and the driver to be compiled in is selected in a Makefile. There is -only one driver present now. - -The driver depends on ad-hoc code in board specific data, namely functions: - - void tws_ce(unsigned bit); - void tws_wr(unsigned bit); - void tws_clk(unsigned bit); - void tws_data(unsigned bit); - unsigned tws_data_read(void); - void tws_data_config_output(unsigned output); - -implemented in include/configs/inka4x0.h . - -II) Approach ------------- - - U-Boot TWserial drivers exports two simple functions and therefore the conversion - of the driver and creating a core for it is not needed. It should be consolidated - with include/configs/inka4x0.h and taken to the misc/ dir. - - -III) Analysis of in-tree drivers --------------------------------- - - 1) drivers/twserial/soft_tws.c - ------------------------------ - The driver is the only TWserial driver. The ad-hoc part in - include/configs/inka4x0.h and the core soft_tws driver should be consolidated - to one compact driver and moved to misc/ . diff --git a/doc/driver-model/UDM-usb.txt b/doc/driver-model/UDM-usb.txt deleted file mode 100644 index 5ce85b5d60..0000000000 --- a/doc/driver-model/UDM-usb.txt +++ /dev/null @@ -1,94 +0,0 @@ -The U-Boot Driver Model Project -=============================== -USB analysis -============ -Marek Vasut -2012-02-16 - -I) Overview ------------ - - 1) The USB Host driver - ---------------------- - There are basically four or five USB host drivers. All such drivers currently - provide at least the following fuctions: - - usb_lowlevel_init() ... Do the initialization of the USB controller hardware - usb_lowlevel_stop() ... Do the shutdown of the USB controller hardware - - usb_event_poll() ...... Poll interrupt from USB device, often used by KBD - - submit_control_msg() .. Submit message via Control endpoint - submit_int_msg() ...... Submit message via Interrupt endpoint - submit_bulk_msg() ..... Submit message via Bulk endpoint - - - This allows for the host driver to be easily abstracted. - - 2) The USB hierarchy - -------------------- - - In the current implementation, the USB Host driver provides operations to - communicate via the USB bus. This is realised by providing access to a USB - root port to which an USB root hub is attached. The USB bus is scanned and for - each newly found device, a struct usb_device is allocated. See common/usb.c - and include/usb.h for details. - -II) Approach ------------- - - 1) The USB Host driver - ---------------------- - - Converting the host driver will follow the classic driver model consideration. - Though, the host driver will have to call a function that registers a root - port with the USB core in it's probe() function, let's call this function - - usb_register_root_port(&ops); - - This will allow the USB core to track all available root ports. The ops - parameter will contain structure describing operations supported by the root - port: - - struct usb_port_ops { - void (*usb_event_poll)(); - int (*submit_control_msg)(); - int (*submit_int_msg)(); - int (*submit_bulk_msg)(); - } - - 2) The USB hierarchy and hub drivers - ------------------------------------ - - Converting the USB heirarchy should be fairy simple, considering the already - dynamic nature of the implementation. The current usb_hub_device structure - will have to be converted to a struct instance. Every such instance will - contain components of struct usb_device and struct usb_hub_device in it's - private data, providing only accessors in order to properly encapsulate the - driver. - - By registering the root port, the USB framework will instantiate a USB hub - driver, which is always present, the root hub. The root hub and any subsequent - hub instance is represented by struct instance and it's private data contain - amongst others common bits from struct usb_device. - - Note the USB hub driver is partly defying the usual method of registering a - set of callbacks to a particular core driver. Instead, a static set of - functions is defined and the USB hub instance is passed to those. This creates - certain restrictions as of how the USB hub driver looks, but considering the - specification for USB hub is given and a different type of USB hub won't ever - exist, this approach is ok: - - - Report how many ports does this hub have: - uint get_nr_ports(struct instance *hub); - - Get pointer to device connected to a port: - struct instance *(*get_child)(struct instance *hub, int port); - - Instantiate and configure device on port: - struct instance *(*enum_dev_on_port)(struct instance *hub, int port); - - 3) USB device drivers - --------------------- - - The USB device driver, in turn, will have to register various ops structures - with certain cores. For example, USB disc driver will have to register it's - ops with core handling USB discs etc. diff --git a/doc/driver-model/UDM-video.txt b/doc/driver-model/UDM-video.txt deleted file mode 100644 index 342aeee485..0000000000 --- a/doc/driver-model/UDM-video.txt +++ /dev/null @@ -1,74 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Video output analysis -===================== -Marek Vasut -2012-02-20 - -I) Overview ------------ - -The video drivers are most often registered with video subsystem. This subsystem -often expects to be allowed access to framebuffer of certain parameters. This -subsystem also provides calls for STDIO subsystem to allow it to output -characters on the screen. For this part, see [ UDM-stdio.txt ]. - -Therefore the API has two parts, the video driver part and the part where the -video driver core registers with STDIO API. - -The video driver part will follow the current cfb_console approach, though -allowing it to be more dynamic. - -II) Approach ------------- - -Registering the video driver into the video driver core is done by calling the -following function from the driver probe() function: - - video_device_register(struct instance *i, GraphicDevice *gd); - -Because the video driver core is in charge or rendering characters as well as -bitmaps on the screen, it will in turn call stdio_device_register(i, so), where -"i" is the same instance as the video driver's one. But "so" will be special -static struct stdio_device_ops handling the character output. - - -III) Analysis of in-tree drivers --------------------------------- - - 1) arch/powerpc/cpu/mpc8xx/video.c - ---------------------------------- - This driver copies the cfb_console [ see drivers/video/cfb_console.c ] - approach and acts only as a STDIO device. Therefore there are currently two - possible approaches, first being the conversion of this driver to usual STDIO - device and second, long-term one, being conversion of this driver to video - driver that provides console. - - 2) arch/x86/lib/video.c - ----------------------- - This driver registers two separate STDIO devices and should be therefore - converted as such. - - 3) board/bf527-ezkit/video.c - ---------------------------- - This driver seems bogus as it behaves as STDIO device, but provides no input - or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use - or present otherwise than as a dead code/define. - - 4) board/bf533-stamp/video.c - ---------------------------- - This driver seems bogus as it behaves as STDIO device, but provides no input - or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use - or present otherwise than as a dead code/define. - - 5) board/bf548-ezkit/video.c - ---------------------------- - This driver seems bogus as it behaves as STDIO device, but provides no input - or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use - or present otherwise than as a dead code/define. - - 6) board/cm-bf548/video.c - ---------------------------- - This driver seems bogus as it behaves as STDIO device, but provides no input - or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use - or present otherwise than as a dead code/define. diff --git a/doc/driver-model/UDM-watchdog.txt b/doc/driver-model/UDM-watchdog.txt deleted file mode 100644 index 7db328639f..0000000000 --- a/doc/driver-model/UDM-watchdog.txt +++ /dev/null @@ -1,329 +0,0 @@ -The U-Boot Driver Model Project -=============================== -Watchdog device subsystem analysis -================================== - -Tomas Hlavacek -2012-03-09 - -I) Overview ------------ - -U-Boot currently implements an API for HW watchdog devices as explicit drivers -in drivers/watchdog directory. There are also drivers for both hardware and -software watchdog on particular CPUs implemented in arch/*/cpu/*/cpu.c. There -are macros in include/watchdog.h that selects between SW and HW watchdog and -assembly SW implementation. - -The current common interface comprises of one set out of these two possible -variants: - - 1) - void watchdog_reset(void); - int watchdog_disable(void); - int watchdog_init(void); - - 2) - void hw_watchdog_reset(void); - void hw_watchdog_init(void); - -The watchdog implementations are also spread through board/*/*.c that in -some cases. The API and semantics is in most cases same as the above -mentioned common functions. - - -II) Approach ------------- - - 1) New API - ---------- - - In the UDM each watchdog driver would register itself by a function - - int watchdog_device_register(struct instance *i, - const struct watchdog_device_ops *o); - - The structure being defined as follows: - - struct watchdog_device_ops { - int (*disable)(struct instance *i); - void (*reset)(struct instance *i); - }; - - The watchdog_init() function will be dissolved into probe() function. - - 2) Conversion thougths - ---------------------- - - Conversion of watchdog implementations to a new API could be divided - to three subsections: a) HW implementations, which are mostly compliant - to the above mentioned API; b) SW implementations, which are compliant - to the above mentioned API and c) SW implementations that are not compliant - to the API and has to be rectified or partially rewritten. - -III) Analysis of in-tree drivers --------------------------------- - - 1) drivers/watchdog/at91sam9_wdt.c - ---------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 2) drivers/watchdog/ftwdt010_wdt.c - ---------------------------------- - The driver is ad-hoc HW watchdog. Conversion has to take into account - driver parts spread in include/faraday/*. Restructuring the driver and - code cleanup has to be considered. - - - 3) arch/arm/cpu/arm1136/mx31/timer.c - ------------------------------------ - The driver is semi-standard ad-hoc HW watchdog. Conversion has to take - into account driver parts spread in the timer.c file. - - - 4) arch/arm/cpu/arm926ejs/davinci/timer.c - ----------------------------------------- - The driver is ad-hoc semi-standard HW watchdog. Conversion has to take - into account driver parts spread in the timer.c file. - - - 5) arch/arm/cpu/armv7/omap-common/hwinit-common.c - ------------------------------------------------- - The driver is non-standard ad-hoc HW watchdog. Conversion is possible - but functions has to be renamed and constants moved to another places. - - - 6) arch/arm/cpu/armv7/omap3/board.c - ----------------------------------- - The driver is non-standard ad-hoc HW watchdog. Conversion is possible - but functions has to be renamed and constants moved to another places. - - - 7) arch/blackfin/cpu/watchdog.c - ------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 8) arch/m68k/cpu/mcf523x/cpu.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - 9) arch/m68k/cpu/mcf52x2/cpu.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - 10) arch/m68k/cpu/mcf532x/cpu.c - ------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 11) arch/m68k/cpu/mcf547x_8x/cpu.c - ---------------------------------- - The driver is standard HW watchdog (there is slight naming convention - violation that has to be rectified). Simple conversion is possible. - - - 12) arch/powerpc/cpu/74xx_7xx/cpu.c - ----------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 13) arch/powerpc/cpu/mpc512x/cpu.c - ---------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 14) arch/powerpc/cpu/mpc5xx/cpu.c - --------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 15) arch/powerpc/cpu/mpc5xxx/cpu.c - ---------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 16) arch/powerpc/cpu/mpc8260/cpu.c - ---------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 17) arch/powerpc/cpu/mpc83xx/cpu.c - ---------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 18) arch/powerpc/cpu/mpc85xx/cpu.c - ---------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 19) arch/powerpc/cpu/mpc86xx/cpu.c - ---------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 20) arch/powerpc/cpu/mpc8xx/cpu.c - - The driver is standard HW watchdog. Simple conversion is possible. - - - 21) arch/powerpc/cpu/ppc4xx/cpu.c - --------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 22) arch/sh/cpu/sh2/watchdog.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - 23) arch/sh/cpu/sh3/watchdog.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - 24) arch/sh/cpu/sh4/watchdog.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - 25) board/amcc/luan/luan.c - -------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 26) board/amcc/yosemite/yosemite.c - ---------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 27) board/apollon/apollon.c - --------------------------- - The driver is standard HW watchdog however the watchdog_init() - function is called in early initialization. Simple conversion is possible. - - - 28) board/bmw/m48t59y.c - ----------------------- - Special watchdog driver. Dead code. To be removed. - - - 29) board/davedenx/qong/qong.c - ------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - 30) board/dvlhost/watchdog.c - ---------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 31) board/eNET/eNET.c - --------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 32) board/eltec/elppc/elppc.c - ----------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 33) board/enbw/enbw_cmc/enbw_cmc.c - ---------------------------------- - Only function proxy call. Code cleanup needed. - - - 34) board/freescale/mx31pdk/mx31pdk.c - ------------------------------------- - Only function proxy call. Code cleanup needed. - - - 35) board/gth2/gth2.c - --------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 36) board/lwmon5/lwmon5.c - ------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 37) board/manroland/mucmc52/mucmc52.c - ------------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 38) board/manroland/uc101/uc101.c - --------------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 39) board/mousse/m48t59y.c - -------------------------- - Special watchdog driver. Dead code. To be removed. - - - 40) board/mvblue/mvblue.c - ------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 41) board/netphone/netphone.c - ----------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 42) board/netta/netta.c - ----------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 43) board/netta2/netta2.c - ------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 44) board/omicron/calimain/calimain.c - ------------------------------------- - Only function proxy call. Code cleanup needed. - - - 46) board/pcs440ep/pcs440ep.c - ----------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 47) board/stx/stxxtc/stxxtc.c - ----------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 48) board/ti/omap2420h4/omap2420h4.c - ------------------------------------ - The driver is standard HW watchdog. Simple conversion is possible. - - - 49) board/ttcontrol/vision2/vision2.c - ------------------------------------- - The driver is standard HW watchdog but namespace is polluted by - non-standard macros. Simple conversion is possible, code cleanup - needed. - - - 50) board/v38b/v38b.c - --------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 51) board/ve8313/ve8313.c - ------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - - 52) board/w7o/watchdog.c - ------------------------ - The driver is standard HW watchdog. Simple conversion is possible. diff --git a/doc/driver-model/spi-howto.txt b/doc/driver-model/spi-howto.txt new file mode 100644 index 0000000000..5bc29ad65c --- /dev/null +++ b/doc/driver-model/spi-howto.txt @@ -0,0 +1,628 @@ +How to port a SPI driver to driver model +======================================== + +Here is a rough step-by-step guide. It is based around converting the +exynos SPI driver to driver model (DM) and the example code is based +around U-Boot v2014.10-rc2 (commit be9f643). This has been updated for +v2015.04. + +It is quite long since it includes actual code examples. + +Before driver model, SPI drivers have their own private structure which +contains 'struct spi_slave'. With driver model, 'struct spi_slave' still +exists, but now it is 'per-child data' for the SPI bus. Each child of the +SPI bus is a SPI slave. The information that was stored in the +driver-specific slave structure can now be port in private data for the +SPI bus. + +For example, struct tegra_spi_slave looks like this: + +struct tegra_spi_slave { + struct spi_slave slave; + struct tegra_spi_ctrl *ctrl; +}; + +In this case 'slave' will be in per-child data, and 'ctrl' will be in the +SPI's buses private data. + + +0. How long does this take? + +You should be able to complete this within 2 hours, including testing but +excluding preparing the patches. The API is basically the same as before +with only minor changes: + +- methods to set speed and mode are separated out +- cs_info is used to get information on a chip select + + +1. Enable driver mode for SPI and SPI flash + +Add these to your board config: + +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH + + +2. Add the skeleton + +Put this code at the bottom of your existing driver file: + +struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + return NULL; +} + +struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, + int spi_node) +{ + return NULL; +} + +static int exynos_spi_ofdata_to_platdata(struct udevice *dev) +{ + return -ENODEV; +} + +static int exynos_spi_probe(struct udevice *dev) +{ + return -ENODEV; +} + +static int exynos_spi_remove(struct udevice *dev) +{ + return -ENODEV; +} + +static int exynos_spi_claim_bus(struct udevice *dev) +{ + + return -ENODEV; +} + +static int exynos_spi_release_bus(struct udevice *dev) +{ + + return -ENODEV; +} + +static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + + return -ENODEV; +} + +static int exynos_spi_set_speed(struct udevice *dev, uint speed) +{ + return -ENODEV; +} + +static int exynos_spi_set_mode(struct udevice *dev, uint mode) +{ + return -ENODEV; +} + +static int exynos_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + return -ENODEV; +} + +static const struct dm_spi_ops exynos_spi_ops = { + .claim_bus = exynos_spi_claim_bus, + .release_bus = exynos_spi_release_bus, + .xfer = exynos_spi_xfer, + .set_speed = exynos_spi_set_speed, + .set_mode = exynos_spi_set_mode, + .cs_info = exynos_cs_info, +}; + +static const struct udevice_id exynos_spi_ids[] = { + { .compatible = "samsung,exynos-spi" }, + { } +}; + +U_BOOT_DRIVER(exynos_spi) = { + .name = "exynos_spi", + .id = UCLASS_SPI, + .of_match = exynos_spi_ids, + .ops = &exynos_spi_ops, + .ofdata_to_platdata = exynos_spi_ofdata_to_platdata, + .probe = exynos_spi_probe, + .remove = exynos_spi_remove, +}; + + +3. Replace 'exynos' in the above code with your driver name + + +4. #ifdef out all of the code in your driver except for the above + +This will allow you to get it building, which means you can work +incrementally. Since all the methods return an error initially, there is +less chance that you will accidentally leave something in. + +Also, even though your conversion is basically a rewrite, it might help +reviewers if you leave functions in the same place in the file, +particularly for large drivers. + + +5. Add some includes + +Add these includes to your driver: + +#include +#include + + +6. Build + +At this point you should be able to build U-Boot for your board with the +empty SPI driver. You still have empty methods in your driver, but we will +write these one by one. + +If you have spi_init() functions or the like that are called from your +board then the build will fail. Remove these calls and make a note of the +init that needs to be done. + + +7. Set up your platform data structure + +This will hold the information your driver to operate, like its hardware +address or maximum frequency. + +You may already have a struct like this, or you may need to create one +from some of the #defines or global variables in the driver. + +Note that this information is not the run-time information. It should not +include state that changes. It should be fixed throughout the live of +U-Boot. Run-time information comes later. + +Here is what was in the exynos spi driver: + +struct spi_bus { + enum periph_id periph_id; + s32 frequency; /* Default clock frequency, -1 for none */ + struct exynos_spi *regs; + int inited; /* 1 if this bus is ready for use */ + int node; + uint deactivate_delay_us; /* Delay to wait after deactivate */ +}; + +Of these, inited is handled by DM and node is the device tree node, which +DM tells you. The name is not quite right. So in this case we would use: + +struct exynos_spi_platdata { + enum periph_id periph_id; + s32 frequency; /* Default clock frequency, -1 for none */ + struct exynos_spi *regs; + uint deactivate_delay_us; /* Delay to wait after deactivate */ +}; + + +8a. Write ofdata_to_platdata() [for device tree only] + +This method will convert information in the device tree node into a C +structure in your driver (called platform data). If you are not using +device tree, go to 8b. + +DM will automatically allocate the struct for us when we are using device +tree, but we need to tell it the size: + +U_BOOT_DRIVER(spi_exynos) = { +... + .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata), + + +Here is a sample function. It gets a pointer to the platform data and +fills in the fields from device tree. + +static int exynos_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct exynos_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg"); + plat->periph_id = pinmux_decode_periph_id(blob, node); + + if (plat->periph_id == PERIPH_ID_NONE) { + debug("%s: Invalid peripheral ID %d\n", __func__, + plat->periph_id); + return -FDT_ERR_NOTFOUND; + } + + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->regs, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); + + return 0; +} + + +8b. Add the platform data [non-device-tree only] + +Specify this data in a U_BOOT_DEVICE() declaration in your board file: + +struct exynos_spi_platdata platdata_spi0 = { + .periph_id = ... + .frequency = ... + .regs = ... + .deactivate_delay_us = ... +}; + +U_BOOT_DEVICE(board_spi0) = { + .name = "exynos_spi", + .platdata = &platdata_spi0, +}; + +You will unfortunately need to put the struct definition into a header file +in this case so that your board file can use it. + + +9. Add the device private data + +Most devices have some private data which they use to keep track of things +while active. This is the run-time information and needs to be stored in +a structure. There is probably a structure in the driver that includes a +'struct spi_slave', so you can use that. + +struct exynos_spi_slave { + struct spi_slave slave; + struct exynos_spi *regs; + unsigned int freq; /* Default frequency */ + unsigned int mode; + enum periph_id periph_id; /* Peripheral ID for this device */ + unsigned int fifo_size; + int skip_preamble; + struct spi_bus *bus; /* Pointer to our SPI bus info */ + ulong last_transaction_us; /* Time of last transaction end */ +}; + + +We should rename this to make its purpose more obvious, and get rid of +the slave structure, so we have: + +struct exynos_spi_priv { + struct exynos_spi *regs; + unsigned int freq; /* Default frequency */ + unsigned int mode; + enum periph_id periph_id; /* Peripheral ID for this device */ + unsigned int fifo_size; + int skip_preamble; + ulong last_transaction_us; /* Time of last transaction end */ +}; + + +DM can auto-allocate this also: + +U_BOOT_DRIVER(spi_exynos) = { +... + .priv_auto_alloc_size = sizeof(struct exynos_spi_priv), + + +Note that this is created before the probe method is called, and destroyed +after the remove method is called. It will be zeroed when the probe +method is called. + + +10. Add the probe() and remove() methods + +Note: It's a good idea to build repeatedly as you are working, to avoid a +huge amount of work getting things compiling at the end. + +The probe method is supposed to set up the hardware. U-Boot used to use +spi_setup_slave() to do this. So take a look at this function and see +what you can copy out to set things up. + + +static int exynos_spi_probe(struct udevice *bus) +{ + struct exynos_spi_platdata *plat = dev_get_platdata(bus); + struct exynos_spi_priv *priv = dev_get_priv(bus); + + priv->regs = plat->regs; + if (plat->periph_id == PERIPH_ID_SPI1 || + plat->periph_id == PERIPH_ID_SPI2) + priv->fifo_size = 64; + else + priv->fifo_size = 256; + + priv->skip_preamble = 0; + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; + + return 0; +} + +This implementation doesn't actually touch the hardware, which is somewhat +unusual for a driver. In this case we will do that when the device is +claimed by something that wants to use the SPI bus. + +For remove we could shut down the clocks, but in this case there is +nothing to do. DM frees any memory that it allocated, so we can just +remove exynos_spi_remove() and its reference in U_BOOT_DRIVER. + + +11. Implement set_speed() + +This should set up clocks so that the SPI bus is running at the right +speed. With the old API spi_claim_bus() would normally do this and several +of the following functions, so let's look at that function: + +int spi_claim_bus(struct spi_slave *slave) +{ + struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); + struct exynos_spi *regs = spi_slave->regs; + u32 reg = 0; + int ret; + + ret = set_spi_clk(spi_slave->periph_id, + spi_slave->freq); + if (ret < 0) { + debug("%s: Failed to setup spi clock\n", __func__); + return ret; + } + + exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE); + + spi_flush_fifo(slave); + + reg = readl(®s->ch_cfg); + reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L); + + if (spi_slave->mode & SPI_CPHA) + reg |= SPI_CH_CPHA_B; + + if (spi_slave->mode & SPI_CPOL) + reg |= SPI_CH_CPOL_L; + + writel(reg, ®s->ch_cfg); + writel(SPI_FB_DELAY_180, ®s->fb_clk); + + return 0; +} + + +It sets up the speed, mode, pinmux, feedback delay and clears the FIFOs. +With DM these will happen in separate methods. + + +Here is an example for the speed part: + +static int exynos_spi_set_speed(struct udevice *bus, uint speed) +{ + struct exynos_spi_platdata *plat = bus->platdata; + struct exynos_spi_priv *priv = dev_get_priv(bus); + int ret; + + if (speed > plat->frequency) + speed = plat->frequency; + ret = set_spi_clk(priv->periph_id, speed); + if (ret) + return ret; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} + + +12. Implement set_mode() + +This should adjust the SPI mode (polarity, etc.). Again this code probably +comes from the old spi_claim_bus(). Here is an example: + + +static int exynos_spi_set_mode(struct udevice *bus, uint mode) +{ + struct exynos_spi_priv *priv = dev_get_priv(bus); + uint32_t reg; + + reg = readl(&priv->regs->ch_cfg); + reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L); + + if (mode & SPI_CPHA) + reg |= SPI_CH_CPHA_B; + + if (mode & SPI_CPOL) + reg |= SPI_CH_CPOL_L; + + writel(reg, &priv->regs->ch_cfg); + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + + +13. Implement claim_bus() + +This is where a client wants to make use of the bus, so claims it first. +At this point we need to make sure everything is set up ready for data +transfer. Note that this function is wholly internal to the driver - at +present the SPI uclass never calls it. + +Here again we look at the old claim function and see some code that is +needed. It is anything unrelated to speed and mode: + +static int exynos_spi_claim_bus(struct udevice *bus) +{ + struct exynos_spi_priv *priv = dev_get_priv(bus); + + exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE); + spi_flush_fifo(priv->regs); + + writel(SPI_FB_DELAY_180, &priv->regs->fb_clk); + + return 0; +} + +The spi_flush_fifo() function is in the removed part of the code, so we +need to expose it again (perhaps with an #endif before it and '#if 0' +after it). It only needs access to priv->regs which is why we have +passed that in: + +/** + * Flush spi tx, rx fifos and reset the SPI controller + * + * @param regs Pointer to SPI registers + */ +static void spi_flush_fifo(struct exynos_spi *regs) +{ + clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); +} + + +14. Implement release_bus() + +This releases the bus - in our example the old code in spi_release_bus() +is a call to spi_flush_fifo, so we add: + +static int exynos_spi_release_bus(struct udevice *bus) +{ + struct exynos_spi_priv *priv = dev_get_priv(bus); + + spi_flush_fifo(priv->regs); + + return 0; +} + + +15. Implement xfer() + +This is the final method that we need to create, and it is where all the +work happens. The method parameters are the same as the old spi_xfer() with +the addition of a 'struct udevice' so conversion is pretty easy. Start +by copying the contents of spi_xfer() to your new xfer() method and proceed +from there. + +If (flags & SPI_XFER_BEGIN) is non-zero then xfer() normally calls an +activate function, something like this: + +void spi_cs_activate(struct spi_slave *slave) +{ + struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); + + /* If it's too soon to do another transaction, wait */ + if (spi_slave->bus->deactivate_delay_us && + spi_slave->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - spi_slave->last_transaction_us; + if (delay_us < spi_slave->bus->deactivate_delay_us) + udelay(spi_slave->bus->deactivate_delay_us - delay_us); + } + + clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); + debug("Activate CS, bus %d\n", spi_slave->slave.bus); + spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE; +} + +The new version looks like this: + +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct exynos_spi_platdata *pdata = dev_get_platdata(bus); + struct exynos_spi_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } + + clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT); + debug("Activate CS, bus '%s'\n", bus->name); + priv->skip_preamble = priv->mode & SPI_PREAMBLE; +} + +All we have really done here is change the pointers and print the device name +instead of the bus number. Other local static functions can be treated in +the same way. + + +16. Set up the per-child data and child pre-probe function + +To minimise the pain and complexity of the SPI subsystem while the driver +model change-over is in place, struct spi_slave is used to reference a +SPI bus slave, even though that slave is actually a struct udevice. In fact +struct spi_slave is the device's child data. We need to make sure this space +is available. It is possible to allocate more space that struct spi_slave +needs, but this is the minimum. + +U_BOOT_DRIVER(exynos_spi) = { +... + .per_child_auto_alloc_size = sizeof(struct spi_slave), +} + + +17. Optional: Set up cs_info() if you want it + +Sometimes it is useful to know whether a SPI chip select is valid, but this +is not obvious from outside the driver. In this case you can provide a +method for cs_info() to deal with this. If you don't provide it, then the +device tree will be used to determine what chip selects are valid. + +Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid. +If you don't provide the cs_info() method, -ENODEV is assumed for all +chip selects that do not appear in the device tree. + + +18. Test it + +Now that you have the code written and it compiles, try testing it using +the 'sf test' command. You may need to enable CONFIG_CMD_SF_TEST for your +board. + + +19. Prepare patches and send them to the mailing lists + +You can use 'tools/patman/patman' to prepare, check and send patches for +your work. See the README for details. + +20. A little note about SPI uclass features: + +The SPI uclass keeps some information about each device 'dev' on the bus: + + struct dm_spi_slave_platdata - this is device_get_parent_platdata(dev) + This is where the chip select number is stored, along with + the default bus speed and mode. It is automatically read + from the device tree in spi_child_post_bind(). It must not + be changed at run-time after being set up because platform + data is supposed to be immutable at run-time. + struct spi_slave - this is device_get_parentdata(dev) + Already mentioned above. It holds run-time information about + the device. + +There are also some SPI uclass methods that get called behind the scenes: + + spi_post_bind() - called when a new bus is bound + This scans the device tree for devices on the bus, and binds + each one. This in turn causes spi_child_post_bind() to be + called for each, which reads the device tree information + into the parent (per-child) platform data. + spi_child_post_bind() - called when a new child is bound + As mentioned above this reads the device tree information + into the per-child platform data + spi_child_pre_probe() - called before a new child is probed + This sets up the mode and speed in struct spi_slave by + copying it from the parent's platform data for this child. + It also sets the 'dev' pointer, needed to permit passing + 'struct spi_slave' around the place without needing a + separate 'struct udevice' pointer. + +The above housekeeping makes it easier to write your SPI driver. diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index 1c79c14a3b..4ed30df707 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -19,22 +19,6 @@ Who: Tom Rini --------------------------- -What: Remove CONFIG_SYS_ENABLE_PADS_ALL and CONFIG_SYS_CLOCKS_ENABLE_ALL -When: Release v2013.07 - -Why: When set these options enable "all" of the pads and clocks found - on OMAP4/5 platforms, so that the Linux Kernel does not have to. - It has been agreed that this goes against the U-Boot design - philosophy and since f3f98bb0 we have not enabled more than is - used in U-Boot. The kernel has been updating drivers to enable - rather than assume pads/clocks have been enabled already. Our - expectation is that by v2013.07 a suitable kernel shall exist that - does not need these options set for a reasonable I/O set to function. - -Who: Tom Rini and Sricharan R - ---------------------------- - What: Users of the legacy miiphy_* code When: undetermined @@ -42,7 +26,7 @@ Why: We now have a PHY library, which allows everyone to share PHY drivers. All new drivers should use this infrastructure, and all old drivers should get converted to use it. -Who: Andy Fleming and driver maintainers +Who: Andy Fleming and driver maintainers --------------------------- diff --git a/doc/git-mailrc b/doc/git-mailrc index e3a47c46f3..8ba599cd9d 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -12,19 +12,30 @@ alias u-boot uboot # things simple and easy to look up/coordinate. alias aaribaud Albert Aribaud alias abiessmann Andreas Bießmann -alias afleming Andy Fleming +alias afleming Andy Fleming alias ag Anatolij Gustschin +alias alisonwang Alison Wang +alias angelo_ts Angelo Dureghello +alias danielschwierzeck Daniel Schwierzeck alias galak Kumar Gala alias gruss Graeme Russ alias hs Heiko Schocher +alias ijc Ian Campbell alias iwamatsu Nobuhiro Iwamatsu +alias jagan Jagannadha Sutradharudu Teki alias jasonjin Jason Jin alias jhersh Joe Hershberger +alias jwrdegoede Hans de Goede alias kimphill Kim Phillips +alias luka Luka Perkov +alias lukma Lukasz Majewski alias macpaul Macpaul Lin -alias marex Marek Vasut +alias marex Marek Vasut +alias masahiro Masahiro Yamada alias monstr Michal Simek +alias panto Pantelis Antoniou alias prafulla Prafulla Wadaskar +alias bobenstein Przemyslaw Marczak alias prom Minkyu Kang alias rbohmer Remy Bohmer alias reinhardm Reinhard Meyer @@ -46,29 +57,32 @@ alias arm uboot, aaribaud alias at91 uboot, abiessmann alias davinci ti alias imx uboot, sbabic -alias kirkwood uboot, prafulla +alias kirkwood uboot, prafulla, luka alias omap ti alias pxa uboot, marex alias rmobile uboot, iwamatsu alias s3c samsung alias s5pc samsung alias samsung uboot, prom +alias sunxi uboot, ijc, jwrdegoede alias tegra uboot, sjg, Tom Warren , Stephen Warren alias tegra2 tegra alias ti uboot, trini +alias uniphier uboot, masahiro +alias zynq uboot, monstr alias avr32 uboot, abiessmann alias bfin uboot, vapier, sonic alias blackfin bfin -alias m68k uboot, jasonjin +alias m68k uboot, alisonwang, angelo_ts alias coldfire m68k alias microblaze uboot, monstr alias mb microblaze -alias mips uboot, Shinya Kuribayashi +alias mips uboot, danielschwierzeck alias nds32 uboot, macpaul @@ -84,8 +98,6 @@ alias mpc83xx uboot, kimphill alias mpc85xx uboot, afleming, galak alias mpc86xx uboot, afleming, galak alias ppc4xx uboot, stroese -alias ppc7xx uboot, wd -alias ppc74xx uboot, wd alias sandbox sjg alias sb sandbox @@ -98,12 +110,20 @@ alias sh superh alias x86 uboot, sjg, gruss # Subsystem aliases +alias dm uboot, sjg alias cfi uboot, stroese +alias dfu uboot, lukma alias kerneldoc uboot, marex -alias fdt uboot, Jerry Van Baren +alias fdt uboot, sjg alias i2c uboot, hs -alias mmc uboot, afleming +alias kconfig uboot, masahiro +alias mmc uboot, panto alias nand uboot, scottwood alias net uboot, jhersh +alias spi uboot, jagan +alias ubi uboot, hs alias usb uboot, marex alias video uboot, ag +alias patman uboot, sjg +alias buildman uboot, sjg +alias pmic uboot, bobenstein diff --git a/doc/mkimage.1 b/doc/mkimage.1 index 14374da88a..b48f70bb3c 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -115,7 +115,7 @@ FIT image. .TP .BI "\-F" Indicates that an existing FIT image should be modified. No dtc -compilation is performed and the -f flag should not be given. +compilation is performed and the \-f flag should not be given. This can be used to sign images with additional keys after initial image creation. @@ -163,7 +163,8 @@ Create FIT image with compressed kernel and sign it with keys in the skipping those for which keys cannot be found. Also add a comment. .nf .B mkimage -f kernel.its -k /public/signing-keys -K u-boot.dtb \\\\ --c "Kernel 3.8 image for production devices" kernel.itb +.br +.B -c "Kernel 3.8 image for production devices" kernel.itb .fi .P @@ -173,7 +174,8 @@ with keys that are available in the new directory. Images that request signing with unavailable keys are skipped. .nf .B mkimage -F -k /secret/signing-keys -K u-boot.dtb \\\\ --c "Kernel 3.8 image for production devices" kernel.itb +.br +.B -c "Kernel 3.8 image for production devices" kernel.itb .fi .SH HOMEPAGE diff --git a/doc/uImage.FIT/beaglebone_vboot.txt b/doc/uImage.FIT/beaglebone_vboot.txt new file mode 100644 index 0000000000..b4ab28542e --- /dev/null +++ b/doc/uImage.FIT/beaglebone_vboot.txt @@ -0,0 +1,608 @@ +Verified Boot on the Beaglebone Black +===================================== + +Introduction +------------ + +Before reading this, please read verified-boot.txt and signature.txt. These +instructions are for mainline U-Boot from v2014.07 onwards. + +There is quite a bit of documentation in this directory describing how +verified boot works in U-Boot. There is also a test which runs through the +entire process of signing an image and running U-Boot (sandbox) to check it. +However, it might be useful to also have an example on a real board. + +Beaglebone Black is a fairly common board so seems to be a reasonable choice +for an example of how to enable verified boot using U-Boot. + +First a note that may to help avoid confusion. U-Boot and Linux both use +device tree. They may use the same device tree source, but it is seldom useful +for them to use the exact same binary from the same place. More typically, +U-Boot has its device tree packaged wtih it, and the kernel's device tree is +packaged with the kernel. In particular this is important with verified boot, +since U-Boot's device tree must be immutable. If it can be changed then the +public keys can be changed and verified boot is useless. An attacker can +simply generate a new key and put his public key into U-Boot so that +everything verifies. On the other hand the kernel's device tree typically +changes when the kernel changes, so it is useful to package an updated device +tree with the kernel binary. U-Boot supports the latter with its flexible FIT +format (Flat Image Tree). + + +Overview +-------- + +The steps are roughly as follows: + +1. Build U-Boot for the board, with the verified boot options enabled. + +2. Obtain a suitable Linux kernel + +3. Create a Image Tree Source file (ITS) file describing how you want the +kernel to be packaged, compressed and signed. + +4. Create a key pair + +5. Sign the kernel + +6. Put the public key into U-Boot's image + +7. Put U-Boot and the kernel onto the board + +8. Try it + + +Step 1: Build U-Boot +-------------------- + +a. Set up the environment variable to point to your toolchain. You will need +this for U-Boot and also for the kernel if you build it. For example if you +installed a Linaro version manually it might be something like: + + export CROSS_COMPILE=/opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux/bin/arm-linux-gnueabihf- + +or if you just installed gcc-arm-linux-gnueabi then it might be + + export CROSS_COMPILE=arm-linux-gnueabi- + +b. Configure and build U-Boot with verified boot enabled: + + export ARCH=arm + export UBOOT=/path/to/u-boot + cd $UBOOT + # You can add -j10 if you have 10 CPUs to make it faster + make O=b/am335x_boneblack_vboot am335x_boneblack_vboot_config all + export UOUT=$UBOOT/b/am335x_boneblack_vboot + +c. You will now have a U-Boot image: + + file b/am335x_boneblack_vboot/u-boot-dtb.img +b/am335x_boneblack_vboot/u-boot-dtb.img: u-boot legacy uImage, U-Boot 2014.07-rc2-00065-g2f69f8, Firmware/ARM, Firmware Image (Not compressed), 395375 bytes, Sat May 31 16:19:04 2014, Load Address: 0x80800000, Entry Point: 0x00000000, Header CRC: 0x0ABD6ACA, Data CRC: 0x36DEF7E4 + + +Step 2: Build Linux +-------------------- + +a. Find the kernel image ('Image') and device tree (.dtb) file you plan to +use. In our case it is am335x-boneblack.dtb and it is built with the kernel. +At the time of writing an SD Boot image can be obtained from here: + + http://www.elinux.org/Beagleboard:Updating_The_Software#Image_For_Booting_From_microSD + +You can write this to an SD card and then mount it to extract the kernel and +device tree files. + +You can also build a kernel. Instructions for this are are here: + + http://elinux.org/Building_BBB_Kernel + +or you can use your favourite search engine. Following these instructions +produces a kernel Image and device tree files. For the record the steps were: + + export KERNEL=/path/to/kernel + cd $KERNEL + git clone git://github.com/beagleboard/kernel.git . + git checkout v3.14 + ./patch.sh + cp configs/beaglebone kernel/arch/arm/configs/beaglebone_defconfig + cd kernel + make beaglebone_defconfig + make uImage dtbs # -j10 if you have 10 CPUs + export OKERNEL=$KERNEL/kernel/arch/arm/boot + +c. You now have the 'Image' and 'am335x-boneblack.dtb' files needed to boot. + + +Step 3: Create the ITS +---------------------- + +Set up a directory for your work. + + export WORK=/path/to/dir + cd $WORK + +Put this into a file in that directory called sign.its: + +/dts-v1/; + +/ { + description = "Beaglebone black"; + #address-cells = <1>; + + images { + kernel@1 { + data = /incbin/("Image.lzo"); + type = "kernel"; + arch = "arm"; + os = "linux"; + compression = "lzo"; + load = <0x80008000>; + entry = <0x80008000>; + hash@1 { + algo = "sha1"; + }; + }; + fdt@1 { + description = "beaglebone-black"; + data = /incbin/("am335x-boneblack.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash@1 { + algo = "sha1"; + }; + }; + }; + configurations { + default = "conf@1"; + conf@1 { + kernel = "kernel@1"; + fdt = "fdt@1"; + signature@1 { + algo = "sha1,rsa2048"; + key-name-hint = "dev"; + sign-images = "fdt", "kernel"; + }; + }; + }; +}; + + +The explanation for this is all in the documentation you have already read. +But briefly it packages a kernel and device tree, and provides a single +configuration to be signed with a key named 'dev'. The kernel is compressed +with LZO to make it smaller. + + +Step 4: Create a key pair +------------------------- + +See signature.txt for details on this step. + + cd $WORK + mkdir keys + openssl genrsa -F4 -out keys/dev.key 2048 + openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt + +Note: keys/dev.key contains your private key and is very secret. If anyone +gets access to that file they can sign kernels with it. Keep it secure. + + +Step 5: Sign the kernel +----------------------- + +We need to use mkimage (which was built when you built U-Boot) to package the +Linux kernel into a FIT (Flat Image Tree, a flexible file format that U-Boot +can load) using the ITS file you just created. + +At the same time we must put the public key into U-Boot device tree, with the +'required' property, which tells U-Boot that this key must be verified for the +image to be valid. You will make this key available to U-Boot for booting in +step 6. + + ln -s $OKERNEL/dts/am335x-boneblack.dtb + ln -s $OKERNEL/Image + ln -s $UOUT/u-boot-dtb.img + cp $UOUT/arch/arm/dts/am335x-boneblack.dtb am335x-boneblack-pubkey.dtb + lzop Image + $UOUT/tools/mkimage -f sign.its -K am335x-boneblack-pubkey.dtb -k keys -r image.fit + +You should see something like this: + +FIT description: Beaglebone black +Created: Sun Jun 1 12:50:30 2014 + Image 0 (kernel@1) + Description: unavailable + Created: Sun Jun 1 12:50:30 2014 + Type: Kernel Image + Compression: lzo compressed + Data Size: 7790938 Bytes = 7608.34 kB = 7.43 MB + Architecture: ARM + OS: Linux + Load Address: 0x80008000 + Entry Point: 0x80008000 + Hash algo: sha1 + Hash value: c94364646427e10f423837e559898ef02c97b988 + Image 1 (fdt@1) + Description: beaglebone-black + Created: Sun Jun 1 12:50:30 2014 + Type: Flat Device Tree + Compression: uncompressed + Data Size: 31547 Bytes = 30.81 kB = 0.03 MB + Architecture: ARM + Hash algo: sha1 + Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Default Configuration: 'conf@1' + Configuration 0 (conf@1) + Description: unavailable + Kernel: kernel@1 + FDT: fdt@1 + + +Now am335x-boneblack-pubkey.dtb contains the public key and image.fit contains +the signed kernel. Jump to step 6 if you like, or continue reading to increase +your understanding. + +You can also run fit_check_sign to check it: + + $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb + +which results in: + +Verifying Hash Integrity ... sha1,rsa2048:dev+ +## Loading kernel from FIT Image at 7fc6ee469000 ... + Using 'conf@1' configuration + Verifying Hash Integrity ... +sha1,rsa2048:dev+ +OK + + Trying 'kernel@1' kernel subimage + Description: unavailable + Created: Sun Jun 1 12:50:30 2014 + Type: Kernel Image + Compression: lzo compressed + Data Size: 7790938 Bytes = 7608.34 kB = 7.43 MB + Architecture: ARM + OS: Linux + Load Address: 0x80008000 + Entry Point: 0x80008000 + Hash algo: sha1 + Hash value: c94364646427e10f423837e559898ef02c97b988 + Verifying Hash Integrity ... +sha1+ +OK + +Unimplemented compression type 4 +## Loading fdt from FIT Image at 7fc6ee469000 ... + Using 'conf@1' configuration + Trying 'fdt@1' fdt subimage + Description: beaglebone-black + Created: Sun Jun 1 12:50:30 2014 + Type: Flat Device Tree + Compression: uncompressed + Data Size: 31547 Bytes = 30.81 kB = 0.03 MB + Architecture: ARM + Hash algo: sha1 + Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Verifying Hash Integrity ... +sha1+ +OK + + Loading Flat Device Tree ... OK + +## Loading ramdisk from FIT Image at 7fc6ee469000 ... + Using 'conf@1' configuration +Could not find subimage node + +Signature check OK + + +At the top, you see "sha1,rsa2048:dev+". This means that it checked an RSA key +of size 2048 bits using SHA1 as the hash algorithm. The key name checked was +'dev' and the '+' means that it verified. If it showed '-' that would be bad. + +Once the configuration is verified it is then possible to rely on the hashes +in each image referenced by that configuration. So fit_check_sign goes on to +load each of the images. We have a kernel and an FDT but no ramkdisk. In each +case fit_check_sign checks the hash and prints sha1+ meaning that the SHA1 +hash verified. This means that none of the images has been tampered with. + +There is a test in test/vboot which uses U-Boot's sandbox build to verify that +the above flow works. + +But it is fun to do this by hand, so you can load image.fit into a hex editor +like ghex, and change a byte in the kernel: + + $UOUT/tools/fit_info -f image.fit -n /images/kernel@1 -p data +NAME: kernel@1 +LEN: 7790938 +OFF: 168 + +This tells us that the kernel starts at byte offset 168 (decimal) in image.fit +and extends for about 7MB. Try changing a byte at 0x2000 (say) and run +fit_check_sign again. You should see something like: + +Verifying Hash Integrity ... sha1,rsa2048:dev+ +## Loading kernel from FIT Image at 7f5a39571000 ... + Using 'conf@1' configuration + Verifying Hash Integrity ... +sha1,rsa2048:dev+ +OK + + Trying 'kernel@1' kernel subimage + Description: unavailable + Created: Sun Jun 1 13:09:21 2014 + Type: Kernel Image + Compression: lzo compressed + Data Size: 7790938 Bytes = 7608.34 kB = 7.43 MB + Architecture: ARM + OS: Linux + Load Address: 0x80008000 + Entry Point: 0x80008000 + Hash algo: sha1 + Hash value: c94364646427e10f423837e559898ef02c97b988 + Verifying Hash Integrity ... +sha1 error +Bad hash value for 'hash@1' hash node in 'kernel@1' image node +Bad Data Hash + +## Loading fdt from FIT Image at 7f5a39571000 ... + Using 'conf@1' configuration + Trying 'fdt@1' fdt subimage + Description: beaglebone-black + Created: Sun Jun 1 13:09:21 2014 + Type: Flat Device Tree + Compression: uncompressed + Data Size: 31547 Bytes = 30.81 kB = 0.03 MB + Architecture: ARM + Hash algo: sha1 + Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Verifying Hash Integrity ... +sha1+ +OK + + Loading Flat Device Tree ... OK + +## Loading ramdisk from FIT Image at 7f5a39571000 ... + Using 'conf@1' configuration +Could not find subimage node + +Signature check Bad (error 1) + + +It has detected the change in the kernel. + +You can also be sneaky and try to switch images, using the libfdt utilities +that come with dtc (package name is device-tree-compiler but you will need a +recent version like 1.4: + + dtc -v +Version: DTC 1.4.0 + +First we can check which nodes are actually hashed by the configuration: + + fdtget -l image.fit / +images +configurations + + fdtget -l image.fit /configurations +conf@1 +fdtget -l image.fit /configurations/conf@1 +signature@1 + + fdtget -p image.fit /configurations/conf@1/signature@1 +hashed-strings +hashed-nodes +timestamp +signer-version +signer-name +value +algo +key-name-hint +sign-images + + fdtget image.fit /configurations/conf@1/signature@1 hashed-nodes +/ /configurations/conf@1 /images/fdt@1 /images/fdt@1/hash@1 /images/kernel@1 /images/kernel@1/hash@1 + +This gives us a bit of a look into the signature that mkimage added. Note you +can also use fdtdump to list the entire device tree. + +Say we want to change the kernel that this configuration uses +(/images/kernel@1). We could just put a new kernel in the image, but we will +need to change the hash to match. Let's simulate that by changing a byte of +the hash: + + fdtget -tx image.fit /images/kernel@1/hash@1 value +c9436464 6427e10f 423837e5 59898ef0 2c97b988 + fdtput -tx image.fit /images/kernel@1/hash@1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981 + +Now check it again: + + $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb +Verifying Hash Integrity ... sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 +rsa_verify_with_keynode: RSA failed to verify: -13 +- +Failed to verify required signature 'key-dev' +Signature check Bad (error 1) + +This time we don't even get as far as checking the images, since the +configuration signature doesn't match. We can't change any hashes without the +signature check noticing. The configuration is essentially locked. U-Boot has +a public key for which it requires a match, and will not permit the use of any +configuration that does not match that public key. The only way the +configuration will match is if it was signed by the matching private key. + +It would also be possible to add a new signature node that does match your new +configuration. But that won't work since you are not allowed to change the +configuration in any way. Try it with a fresh (valid) image if you like by +running the mkimage link again. Then: + + fdtput -p image.fit /configurations/conf@1/signature@2 value fred + $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb +Verifying Hash Integrity ... - +sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 +rsa_verify_with_keynode: RSA failed to verify: -13 +- +Failed to verify required signature 'key-dev' +Signature check Bad (error 1) + + +Of course it would be possible to add an entirely new configuration and boot +with that, but it still needs to be signed, so it won't help. + + +6. Put the public key into U-Boot's image +----------------------------------------- + +Having confirmed that the signature is doing its job, let's try it out in +U-Boot on the board. U-Boot needs access to the public key corresponding to +the private key that you signed with so that it can verify any kernels that +you sign. + + cd $UBOOT + make O=b/am335x_boneblack_vboot EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb + +Here we are overrriding the normal device tree file with our one, which +contains the public key. + +Now you have a special U-Boot image with the public key. It can verify can +kernel that you sign with the private key as in step 5. + +If you like you can take a look at the public key information that mkimage +added to U-Boot's device tree: + + fdtget -p am335x-boneblack-pubkey.dtb /signature/key-dev +required +algo +rsa,r-squared +rsa,modulus +rsa,n0-inverse +rsa,num-bits +key-name-hint + +This has information about the key and some pre-processed values which U-Boot +can use to verify against it. These values are obtained from the public key +certificate by mkimage, but require quite a bit of code to generate. To save +code space in U-Boot, the information is extracted and written in raw form for +U-Boot to easily use. The same mechanism is used in Google's Chrome OS. + +Notice the 'required' property. This marks the key as required - U-Boot will +not boot any image that does not verify against this key. + + +7. Put U-Boot and the kernel onto the board +------------------------------------------- + +The method here varies depending on how you are booting. For this example we +are booting from an micro-SD card with two partitions, one for U-Boot and one +for Linux. Put it into your machine and write U-Boot and the kernel to it. +Here the card is /dev/sde: + + cd $WORK + export UDEV=/dev/sde1 # Change thes two lines to the correct device + export KDEV=/dev/sde2 + sudo mount $UDEV /mnt/tmp && sudo cp $UOUT/u-boot-dtb.img /mnt/tmp/u-boot.img && sleep 1 && sudo umount $UDEV + sudo mount $KDEV /mnt/tmp && sudo cp $WORK/image.fit /mnt/tmp/boot/image.fit && sleep 1 && sudo umount $KDEV + + +8. Try it +--------- + +Boot the board using the commands below: + + setenv bootargs console=ttyO0,115200n8 quiet root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait + ext2load mmc 0:2 82000000 /boot/image.fit + bootm 82000000 + +You should then see something like this: + +U-Boot# setenv bootargs console=ttyO0,115200n8 quiet root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait +U-Boot# ext2load mmc 0:2 82000000 /boot/image.fit +7824930 bytes read in 589 ms (12.7 MiB/s) +U-Boot# bootm 82000000 +## Loading kernel from FIT Image at 82000000 ... + Using 'conf@1' configuration + Verifying Hash Integrity ... sha1,rsa2048:dev+ OK + Trying 'kernel@1' kernel subimage + Description: unavailable + Created: 2014-06-01 19:32:54 UTC + Type: Kernel Image + Compression: lzo compressed + Data Start: 0x820000a8 + Data Size: 7790938 Bytes = 7.4 MiB + Architecture: ARM + OS: Linux + Load Address: 0x80008000 + Entry Point: 0x80008000 + Hash algo: sha1 + Hash value: c94364646427e10f423837e559898ef02c97b988 + Verifying Hash Integrity ... sha1+ OK +## Loading fdt from FIT Image at 82000000 ... + Using 'conf@1' configuration + Trying 'fdt@1' fdt subimage + Description: beaglebone-black + Created: 2014-06-01 19:32:54 UTC + Type: Flat Device Tree + Compression: uncompressed + Data Start: 0x8276e2ec + Data Size: 31547 Bytes = 30.8 KiB + Architecture: ARM + Hash algo: sha1 + Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Verifying Hash Integrity ... sha1+ OK + Booting using the fdt blob at 0x8276e2ec + Uncompressing Kernel Image ... OK + Loading Device Tree to 8fff5000, end 8ffffb3a ... OK + +Starting kernel ... + +[ 0.582377] omap_init_mbox: hwmod doesn't have valid attrs +[ 2.589651] musb-hdrc musb-hdrc.0.auto: Failed to request rx1. +[ 2.595830] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed with status -517 +[ 2.606470] musb-hdrc musb-hdrc.1.auto: Failed to request rx1. +[ 2.612723] musb-hdrc musb-hdrc.1.auto: musb_init_controller failed with status -517 +[ 2.940808] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) +[ 7.248889] libphy: PHY 4a101000.mdio:01 not found +[ 7.253995] net eth0: phy 4a101000.mdio:01 not found on slave 1 +systemd-fsck[83]: Angstrom: clean, 50607/218160 files, 306348/872448 blocks + +.---O---. +| | .-. o o +| | |-----.-----.-----.| | .----..-----.-----. +| | | __ | ---'| '--.| .-'| | | +| | | | | |--- || --'| | | ' | | | | +'---'---'--'--'--. |-----''----''--' '-----'-'-'-' + -' | + '---' + +The Angstrom Distribution beaglebone ttyO0 + +Angstrom v2012.12 - Kernel 3.14.1+ + +beaglebone login: + +At this point your kernel has been verified and you can be sure that it is one +that you signed. As an exercise, try changing image.fit as in step 5 and see +what happens. + + +Further Improvements +-------------------- + +Several of the steps here can be easily automated. In particular it would be +capital if signing and packaging a kernel were easy, perhaps a simple make +target in the kernel. + +Some mention of how to use multiple .dtb files in a FIT might be useful. + +U-Boot's verified boot mechanism has not had a robust and independent security +review. Such a review should look at the implementation and its resistance to +attacks. + +Perhaps the verified boot feature could could be integrated into the Amstrom +distribution. + + +Simon Glass +sjg@chromium.org +2-June-14 diff --git a/doc/uImage.FIT/command_syntax_extensions.txt b/doc/uImage.FIT/command_syntax_extensions.txt index 002818c226..6c99b1c159 100644 --- a/doc/uImage.FIT/command_syntax_extensions.txt +++ b/doc/uImage.FIT/command_syntax_extensions.txt @@ -170,7 +170,7 @@ bootm 200000 In case of the new uImage argument syntax, the address portion of any argument can be omitted. If is omitted, then it is assumed that image at - should be used. Similarly, when is omitted, is is assumed that + should be used. Similarly, when is omitted, it is assumed that image at should be used. If is omitted, it is assumed that the current image address is to be used. For example, consider the following commands: diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt index 59e21e91e3..14e316f72c 100644 --- a/doc/uImage.FIT/howto.txt +++ b/doc/uImage.FIT/howto.txt @@ -16,12 +16,15 @@ create an uImage in the new format: mkimage and dtc, although only one (mkimage) is invoked directly. dtc is called from within mkimage and operates behind the scenes, but needs to be present in the $PATH nevertheless. It is important that the dtc used has support for binary includes -- refer to -www.jdl.com for its latest version. mkimage (together with dtc) takes as input + + git://git.kernel.org/pub/scm/utils/dtc/dtc.git + +for its latest version. mkimage (together with dtc) takes as input an image source file, which describes the contents of the image and defines its various properties used during booting. By convention, image source file has the ".its" extension, also, the details of its format are given in -doc/source_file_format.txt. The actual data that is to be included in the -uImage (kernel, ramdisk, etc.) is specified in the image source file in the +doc/uImage.FIT/source_file_format.txt. The actual data that is to be included in +the uImage (kernel, ramdisk, etc.) is specified in the image source file in the form of paths to appropriate data files. The outcome of the image creation process is a binary file (by convention with the ".itb" extension) that contains all the referenced data (kernel, ramdisk, etc.) and other information @@ -39,7 +42,7 @@ Here's a graphical overview of the image creation and booting process: image source file mkimage + dtc transfer to target + ---------------> image file --------------------> bootm -image data files(s) +image data file(s) Example 1 -- old-style (non-FDT) kernel booting diff --git a/doc/uImage.FIT/kernel.its b/doc/uImage.FIT/kernel.its index ef3ab8f726..539cdbfafe 100644 --- a/doc/uImage.FIT/kernel.its +++ b/doc/uImage.FIT/kernel.its @@ -35,3 +35,53 @@ }; }; }; + + + +For x86 a setup node is also required: see x86-fit-boot.txt. + +/dts-v1/; + +/ { + description = "Simple image with single Linux kernel on x86"; + #address-cells = <1>; + + images { + kernel@1 { + description = "Vanilla Linux kernel"; + data = /incbin/("./image.bin.lzo"); + type = "kernel"; + arch = "x86"; + os = "linux"; + compression = "lzo"; + load = <0x01000000>; + entry = <0x00000000>; + hash@2 { + algo = "sha1"; + }; + }; + + setup@1 { + description = "Linux setup.bin"; + data = /incbin/("./setup.bin"); + type = "x86_setup"; + arch = "x86"; + os = "linux"; + compression = "none"; + load = <0x00090000>; + entry = <0x00090000>; + hash@2 { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config@1"; + config@1 { + description = "Boot Linux kernel"; + kernel = "kernel@1"; + setup = "setup@1"; + }; + }; +}; diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index bc9f3fa6e1..b2f89fcc65 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -66,7 +66,8 @@ Creating an RSA key and certificate ----------------------------------- To create a new public key, size 2048 bits: -$ openssl genrsa -F4 -out keys/dev.key 2048 +$ openssl genpkey -algorithm RSA -out keys/dev.key \ + -pkeyopt rsa_keygen_bits:2048 -pkeyopt rsa_keygen_pubexp:65537 To create a certificate for this: @@ -159,6 +160,7 @@ For RSA the following are mandatory: - rsa,num-bits: Number of key bits (e.g. 2048) - rsa,modulus: Modulus (N) as a big-endian multi-word integer +- rsa,exponent: Public exponent (E) as a 64 bit unsigned integer - rsa,r-squared: (2^num-bits)^2 as a big-endian multi-word integer - rsa,n0-inverse: -1 / modulus[0] mod 2^32 @@ -328,6 +330,9 @@ be enabled: CONFIG_FIT_SIGNATURE - enable signing and verfication in FITs CONFIG_RSA - enable RSA algorithm for signing +WARNING: When relying on signed FIT images with required signature check +the legacy image format is default disabled by not defining +CONFIG_IMAGE_FORMAT_LEGACY Testing ------- @@ -346,7 +351,9 @@ Simple Verified Boot Test Please see doc/uImage.FIT/verified-boot.txt for more information +/home/hs/ids/u-boot/sandbox/tools/mkimage -D -I dts -O dtb -p 2000 Build keys +do sha1 test Build FIT with signed images Test Verified Boot Run: unsigned signatures:: OK Sign images @@ -355,6 +362,25 @@ Build FIT with signed configuration Test Verified Boot Run: unsigned config: OK Sign images Test Verified Boot Run: signed config: OK +check signed config on the host +Signature check OK +OK +Test Verified Boot Run: signed config: OK +Test Verified Boot Run: signed config with bad hash: OK +do sha256 test +Build FIT with signed images +Test Verified Boot Run: unsigned signatures:: OK +Sign images +Test Verified Boot Run: signed images: OK +Build FIT with signed configuration +Test Verified Boot Run: unsigned config: OK +Sign images +Test Verified Boot Run: signed config: OK +check signed config on the host +Signature check OK +OK +Test Verified Boot Run: signed config: OK +Test Verified Boot Run: signed config with bad hash: OK Test passed diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 6d2070758d..427ea498b4 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -55,14 +55,14 @@ FIT is formally a flattened device tree (in the libfdt meaning), which conforms to bindings defined in this document. .its - image tree source -.itb - image tree blob +.fit - flattened image tree blob c) Image building procedure The following picture shows how the new uImage is prepared. Input consists of image source file (.its) and a set of data files. Image is created with the help of standard U-boot mkimage tool which in turn uses dtc (device tree -compiler) to produce image tree blob (.itb). Resulting .itb file is is the +compiler) to produce image tree blob (.itb). Resulting .itb file is the actual binary of a new uImage. @@ -101,15 +101,15 @@ Root node of the uImage Tree should have the following layout: | o images | | - | o img@1 {...} - | o img@2 {...} + | o image@1 {...} + | o image@2 {...} | ... | o configurations - |- default = "cfg@1" + |- default = "conf@1" | - o cfg@1 {...} - o cfg@2 {...} + o conf@1 {...} + o conf@2 {...} ... @@ -159,21 +159,22 @@ the '/images' node should have the following layout: - description : Textual description of the component sub-image - type : Name of component sub-image type, supported types are: "standalone", "kernel", "ramdisk", "firmware", "script", "filesystem", - "fdt". + "flat_dt" and others (see uimage_type in common/image.c). - data : Path to the external file which contains this node's binary data. - compression : Compression used by included data. Supported compressions are "gzip" and "bzip2". If no compression is used compression property should be set to "none". Conditionally mandatory property: - - os : OS name, mandatory for type="kernel", valid OS names are: "openbsd", - "netbsd", "freebsd", "4_4bsd", "linux", "svr4", "esix", "solaris", "irix", - "sco", "dell", "ncr", "lynxos", "vxworks", "psos", "qnx", "u_boot", - "rtems", "unity", "integrity". + - os : OS name, mandatory for types "kernel" and "ramdisk". Valid OS names + are: "openbsd", "netbsd", "freebsd", "4_4bsd", "linux", "svr4", "esix", + "solaris", "irix", "sco", "dell", "ncr", "lynxos", "vxworks", "psos", "qnx", + "u_boot", "rtems", "unity", "integrity". - arch : Architecture name, mandatory for types: "standalone", "kernel", "firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha", "arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc", - "sparc64", "m68k", "microblaze", "nios2", "blackfin", "avr32", "st200". + "sparc64", "m68k", "microblaze", "nios2", "blackfin", "avr32", "st200", + "sandbox". - entry : entry point address, address size is determined by '#address-cells' property of the root node. Mandatory for for types: "standalone" and "kernel". @@ -246,6 +247,8 @@ o config@1 node of a "ramdisk" type). - fdt : Unit name of the corresponding fdt blob (component image node of a "fdt type"). + - setup : Unit name of the corresponding setup binary (used for booting + an x86 kernel). This contains the setup.bin file built by the kernel. The FDT blob is required to properly boot FDT based kernel, so the minimal configuration for 2.6 FDT kernel is (kernel, fdt) pair. diff --git a/doc/uImage.FIT/verified-boot.txt b/doc/uImage.FIT/verified-boot.txt index 3c83fbc2c1..e639e7ae71 100644 --- a/doc/uImage.FIT/verified-boot.txt +++ b/doc/uImage.FIT/verified-boot.txt @@ -64,7 +64,7 @@ software from updatable memory. It is critical that the public key be secure and cannot be tampered with. It can be stored in read-only memory, or perhaps protected by other on-chip -crypto provided by some modern SOCs. If the public key can ben changed, then +crypto provided by some modern SOCs. If the public key can be changed, then the verification is worthless. @@ -87,7 +87,7 @@ affect the whole change. Flattened Image Tree (FIT) -------------------------- -The FIT format is alreay widely used in U-Boot. It is a flattened device +The FIT format is already widely used in U-Boot. It is a flattened device tree (FDT) in a particular format, with images contained within. FITs include hashes to verify images, so it is relatively straightforward to add signatures as well. diff --git a/doc/uImage.FIT/x86-fit-boot.txt b/doc/uImage.FIT/x86-fit-boot.txt new file mode 100644 index 0000000000..61c10ff7c2 --- /dev/null +++ b/doc/uImage.FIT/x86-fit-boot.txt @@ -0,0 +1,276 @@ +Booting Linux on x86 with FIT +============================= + +Background +---------- + +(corrections to the text below are welcome) + +Generally Linux x86 uses its own very complex booting method. There is a setup +binary which contains all sorts of parameters and a compressed self-extracting +binary for the kernel itself, often with a small built-in serial driver to +display decompression progress. + +The x86 CPU has various processor modes. I am no expert on these, but my +understanding is that an x86 CPU (even a really new one) starts up in a 16-bit +'real' mode where only 1MB of memory is visible, moves to 32-bit 'protected' +mode where 4GB is visible (or more with special memory access techniques) and +then to 64-bit 'long' mode if 64-bit execution is required. + +Partly the self-extracting nature of Linux was introduced to cope with boot +loaders that were barely capable of loading anything. Even changing to 32-bit +mode was something of a challenge, so putting this logic in the kernel seemed +to make sense. + +Bit by bit more and more logic has been added to this post-boot pre-Linux +wrapper: + +- Changing to 32-bit mode +- Decompression +- Serial output (with drivers for various chips) +- Load address randomisation +- Elf loader complete with relocation (for the above) +- Random number generator via 3 methods (again for the above) +- Some sort of EFI mini-loader (1000+ glorious lines of code) +- Locating and tacking on a device tree and ramdisk + +To my mind, if you sit back and look at things from first principles, this +doesn't make a huge amount of sense. Any boot loader worth its salts already +has most of the above features and more besides. The boot loader already knows +the layout of memory, has a serial driver, can decompress things, includes an +ELF loader and supports device tree and ramdisks. The decision to duplicate +all these features in a Linux wrapper caters for the lowest common +denominator: a boot loader which consists of a BIOS call to load something off +disk, followed by a jmp instruction. + +(Aside: On ARM systems, we worry that the boot loader won't know where to load +the kernel. It might be easier to just provide that information in the image, +or in the boot loader rather than adding a self-relocator to put it in the +right place. Or just use ELF? + +As a result, the x86 kernel boot process is needlessly complex. The file +format is also complex, and obfuscates the contents to a degree that it is +quite a challenge to extract anything from it. This bzImage format has become +so prevalent that is actually isn't possible to produce the 'raw' kernel build +outputs with the standard Makefile (as it is on ARM for example, at least at +the time of writing). + +This document describes an alternative boot process which uses simple raw +images which are loaded into the right place by the boot loader and then +executed. + + +Build the kernel +---------------- + +Note: these instructions assume a 32-bit kernel. U-Boot does not currently +support booting a 64-bit kernel as it has no way of going into 64-bit mode on +x86. + +You can build the kernel as normal with 'make'. This will create a file called +'vmlinux'. This is a standard ELF file and you can look at it if you like: + +$ objdump -h vmlinux + +vmlinux: file format elf32-i386 + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00416850 81000000 01000000 00001000 2**5 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 .notes 00000024 81416850 01416850 00417850 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 __ex_table 00000c50 81416880 01416880 00417880 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 3 .rodata 00154b9e 81418000 01418000 00419000 2**5 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 4 __bug_table 0000597c 8156cba0 0156cba0 0056dba0 2**0 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 5 .pci_fixup 00001b80 8157251c 0157251c 0057351c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 6 .tracedata 00000024 8157409c 0157409c 0057509c 2**0 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 7 __ksymtab 00007ec0 815740c0 015740c0 005750c0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 8 __ksymtab_gpl 00004a28 8157bf80 0157bf80 0057cf80 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 9 __ksymtab_strings 0001d6fc 815809a8 015809a8 005819a8 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 10 __init_rodata 00001c3c 8159e0a4 0159e0a4 0059f0a4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 11 __param 00000ff0 8159fce0 0159fce0 005a0ce0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 12 __modver 00000330 815a0cd0 015a0cd0 005a1cd0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 13 .data 00063000 815a1000 015a1000 005a2000 2**12 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 14 .init.text 0002f104 81604000 01604000 00605000 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 15 .init.data 00040cdc 81634000 01634000 00635000 2**12 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 16 .x86_cpu_dev.init 0000001c 81674cdc 01674cdc 00675cdc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 17 .altinstructions 0000267c 81674cf8 01674cf8 00675cf8 2**0 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 18 .altinstr_replacement 00000942 81677374 01677374 00678374 2**0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 19 .iommu_table 00000014 81677cb8 01677cb8 00678cb8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 20 .apicdrivers 00000004 81677cd0 01677cd0 00678cd0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 21 .exit.text 00001a80 81677cd8 01677cd8 00678cd8 2**0 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 22 .data..percpu 00007880 8167a000 0167a000 0067b000 2**12 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 23 .smp_locks 00003000 81682000 01682000 00683000 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA + 24 .bss 000a1000 81685000 01685000 00686000 2**12 + ALLOC + 25 .brk 00424000 81726000 01726000 00686000 2**0 + ALLOC + 26 .comment 00000049 00000000 00000000 00686000 2**0 + CONTENTS, READONLY + 27 .GCC.command.line 0003e055 00000000 00000000 00686049 2**0 + CONTENTS, READONLY + 28 .debug_aranges 0000f4c8 00000000 00000000 006c40a0 2**3 + CONTENTS, RELOC, READONLY, DEBUGGING + 29 .debug_info 0440b0df 00000000 00000000 006d3568 2**0 + CONTENTS, RELOC, READONLY, DEBUGGING + 30 .debug_abbrev 0022a83b 00000000 00000000 04ade647 2**0 + CONTENTS, READONLY, DEBUGGING + 31 .debug_line 004ead0d 00000000 00000000 04d08e82 2**0 + CONTENTS, RELOC, READONLY, DEBUGGING + 32 .debug_frame 0010a960 00000000 00000000 051f3b90 2**2 + CONTENTS, RELOC, READONLY, DEBUGGING + 33 .debug_str 001b442d 00000000 00000000 052fe4f0 2**0 + CONTENTS, READONLY, DEBUGGING + 34 .debug_loc 007c7fa9 00000000 00000000 054b291d 2**0 + CONTENTS, RELOC, READONLY, DEBUGGING + 35 .debug_ranges 00098828 00000000 00000000 05c7a8c8 2**3 + CONTENTS, RELOC, READONLY, DEBUGGING + +There is also the setup binary mentioned earlier. This is at +arch/x86/boot/setup.bin and is about 12KB in size. It includes the command +line and various settings need by the kernel. Arguably the boot loader should +provide all of this also, but setting it up is some complex that the kernel +helps by providing a head start. + +As you can see the code loads to address 0x01000000 and everything else +follows after that. We could load this image using the 'bootelf' command but +we would still need to provide the setup binary. This is not supported by +U-Boot although I suppose you could mostly script it. This would permit the +use of a relocatable kernel. + +All we need to boot is the vmlinux file and the setup.bin file. + + +Create a FIT +------------ + +To create a FIT you will need a source file describing what should go in the +FIT. See kernel.its for an example for x86. Put this into a file called +image.its. + +Note that setup is loaded to the special address of 0x90000 (a special address +you just have to know) and the kernel is loaded to 0x01000000 (the address you +saw above). This means that you will need to load your FIT to a different +address so that U-Boot doesn't overwrite it when decompressing. Something like +0x02000000 will do so you can set CONFIG_SYS_LOAD_ADDR to that. + +In that example the kernel is compressed with lzo. Also we need to provide a +flat binary, not an ELF. So the steps needed to set things are are: + + # Create a flat binary + objcopy -O binary vmlinux vmlinux.bin + + # Compress it into LZO format + lzop vmlinux.bin + + # Build a FIT image + mkimage -f image.its image.fit + +(be careful to run the mkimage from your U-Boot tools directory since it +will have x86_setup support.) + +You can take a look at the resulting fit file if you like: + +$ dumpimage -l image.fit +FIT description: Simple image with single Linux kernel on x86 +Created: Tue Oct 7 10:57:24 2014 + Image 0 (kernel@1) + Description: Vanilla Linux kernel + Created: Tue Oct 7 10:57:24 2014 + Type: Kernel Image + Compression: lzo compressed + Data Size: 4591767 Bytes = 4484.15 kB = 4.38 MB + Architecture: Intel x86 + OS: Linux + Load Address: 0x01000000 + Entry Point: 0x00000000 + Hash algo: sha1 + Hash value: 446b5163ebfe0fb6ee20cbb7a8501b263cd92392 + Image 1 (setup@1) + Description: Linux setup.bin + Created: Tue Oct 7 10:57:24 2014 + Type: x86 setup.bin + Compression: uncompressed + Data Size: 12912 Bytes = 12.61 kB = 0.01 MB + Hash algo: sha1 + Hash value: a1f2099cf47ff9816236cd534c77af86e713faad + Default Configuration: 'config@1' + Configuration 0 (config@1) + Description: Boot Linux kernel + Kernel: kernel@1 + + +Booting the FIT +--------------- + +To make it boot you need to load it and then use 'bootm' to boot it. A +suitable script to do this from a network server is: + + bootp + tftp image.fit + bootm + +This will load the image from the network and boot it. The command line (from +the 'bootargs' environment variable) will be passed to the kernel. + +If you want a ramdisk you can add it as normal with FIT. If you want a device +tree then x86 doesn't normally use those - it has ACPI instead. + + +Why Bother? +----------- + +1. It demystifies the process of booting an x86 kernel +2. It allows use of the standard U-Boot boot file format +3. It allows U-Boot to perform decompression - problems will provide an error +message and you are still in the boot loader. It is possible to investigate. +4. It avoids all the pre-loader code in the kernel which is quite complex to +follow +5. You can use verified/secure boot and other features which haven't yet been +added to the pre-Linux +6. It makes x86 more like other architectures in the way it boots a kernel. +You can potentially use the same file format for the kernel, and the same +procedure for building and packaging it. + + +References +---------- + +In the Linux kernel, Documentation/x86/boot.txt defines the boot protocol for +the kernel including the setup.bin format. This is handled in U-Boot in +arch/x86/lib/zimage.c and arch/x86/lib/bootm.c. + +The procedure for entering 64-bit mode on x86 seems to be described here: + + http://wiki.osdev.org/64-bit_Higher_Half_Kernel_with_GRUB_2 + +Various files in the same directory as this file describe the FIT format. + + +-- +Simon Glass +sjg@chromium.org +7-Oct-2014 diff --git a/drivers/Kconfig b/drivers/Kconfig new file mode 100644 index 0000000000..128736dae3 --- /dev/null +++ b/drivers/Kconfig @@ -0,0 +1,51 @@ +menu "Device Drivers" + +source "drivers/core/Kconfig" + +source "drivers/pci/Kconfig" + +source "drivers/pcmcia/Kconfig" + +source "drivers/mtd/Kconfig" + +source "drivers/block/Kconfig" + +source "drivers/misc/Kconfig" + +source "drivers/net/Kconfig" + +source "drivers/input/Kconfig" + +source "drivers/serial/Kconfig" + +source "drivers/tpm/Kconfig" + +source "drivers/i2c/Kconfig" + +source "drivers/spi/Kconfig" + +source "drivers/gpio/Kconfig" + +source "drivers/power/Kconfig" + +source "drivers/hwmon/Kconfig" + +source "drivers/watchdog/Kconfig" + +source "drivers/video/Kconfig" + +source "drivers/sound/Kconfig" + +source "drivers/usb/Kconfig" + +source "drivers/dfu/Kconfig" + +source "drivers/mmc/Kconfig" + +source "drivers/rtc/Kconfig" + +source "drivers/dma/Kconfig" + +source "drivers/crypto/Kconfig" + +endmenu diff --git a/drivers/Makefile b/drivers/Makefile new file mode 100644 index 0000000000..5ef58c051e --- /dev/null +++ b/drivers/Makefile @@ -0,0 +1,25 @@ +obj-$(CONFIG_DM) += core/ +obj-$(CONFIG_DM_DEMO) += demo/ +obj-$(CONFIG_BIOSEMU) += bios_emulator/ +obj-y += block/ +obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ +obj-y += crypto/ +obj-$(CONFIG_FPGA) += fpga/ +obj-y += hwmon/ +obj-y += misc/ +obj-y += pcmcia/ +obj-y += dfu/ +obj-y += rtc/ +obj-y += sound/ +obj-y += tpm/ +obj-y += twserial/ +obj-y += video/ +obj-y += watchdog/ +obj-$(CONFIG_QE) += qe/ +obj-$(CONFIG_U_QE) += qe/ +obj-y += memory/ +obj-y += pwm/ +obj-y += input/ +# SOC specific infrastructure drivers. +obj-y += soc/ +obj-y += thermal/ diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index d94a144292..2ba43ac731 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -1,12 +1,6 @@ -include $(TOPDIR)/config.mk - -LIB := $(obj)libatibiosemu.o - X86DIR = x86emu -$(shell mkdir -p $(obj)$(X86DIR)) - -COBJS-$(CONFIG_BIOSEMU) = atibios.o biosemu.o besys.o bios.o \ +obj-y = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/decode.o \ $(X86DIR)/ops2.o \ $(X86DIR)/ops.o \ @@ -14,26 +8,5 @@ COBJS-$(CONFIG_BIOSEMU) = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ - -D__PPC__ -D__BIG_ENDIAN__ - -CFLAGS += $(EXTRA_CFLAGS) -HOSTCFLAGS += $(EXTRA_CFLAGS) -CPPFLAGS += $(EXTRA_CFLAGS) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \ + $(if $(CONFIG_PPC),-D__PPC__ -D__BIG_ENDIAN__) diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 3b2ed6e109..7ea5fa6224 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -46,8 +46,11 @@ * BIOS in u-boot. ****************************************************************************/ #include -#include "biosemui.h" +#include +#include #include +#include +#include "biosemui.h" /* Length of the BIOS image */ #define MAX_BIOSLEN (128 * 1024L) @@ -59,17 +62,172 @@ static u32 saveBaseAddress14; static u32 saveBaseAddress18; static u32 saveBaseAddress20; +/* Addres im memory of VBE region */ +const int vbe_offset = 0x2000; + +static const void *bios_ptr(const void *buf, BE_VGAInfo *vga_info, + u32 x86_dword_ptr) +{ + u32 seg_ofs, flat; + + seg_ofs = le32_to_cpu(x86_dword_ptr); + flat = ((seg_ofs & 0xffff0000) >> 12) | (seg_ofs & 0xffff); + if (flat >= 0xc0000) + return vga_info->BIOSImage + flat - 0xc0000; + else + return buf + (flat - vbe_offset); +} + +static int atibios_debug_mode(BE_VGAInfo *vga_info, RMREGS *regs, + int vesa_mode, struct vbe_mode_info *mode_info) +{ + void *buffer = (void *)(M.mem_base + vbe_offset); + u16 buffer_seg = (((unsigned long)vbe_offset) >> 4) & 0xff00; + u16 buffer_adr = ((unsigned long)vbe_offset) & 0xffff; + struct vesa_mode_info *vm; + struct vbe_info *info; + const u16 *modes_bios, *ptr; + u16 *modes; + int size; + + debug("VBE: Getting information\n"); + regs->e.eax = VESA_GET_INFO; + regs->e.esi = buffer_seg; + regs->e.edi = buffer_adr; + info = buffer; + memset(info, '\0', sizeof(*info)); + strcpy(info->signature, "VBE2"); + BE_int86(0x10, regs, regs); + if (regs->e.eax != 0x4f) { + debug("VESA_GET_INFO: error %x\n", regs->e.eax); + return -ENOSYS; + } + debug("version %x\n", le16_to_cpu(info->version)); + debug("oem '%s'\n", (char *)bios_ptr(buffer, vga_info, + info->oem_string_ptr)); + debug("vendor '%s'\n", (char *)bios_ptr(buffer, vga_info, + info->vendor_name_ptr)); + debug("product '%s'\n", (char *)bios_ptr(buffer, vga_info, + info->product_name_ptr)); + debug("rev '%s'\n", (char *)bios_ptr(buffer, vga_info, + info->product_rev_ptr)); + modes_bios = bios_ptr(buffer, vga_info, info->modes_ptr); + debug("Modes: "); + for (ptr = modes_bios; *ptr != 0xffff; ptr++) + debug("%x ", le16_to_cpu(*ptr)); + debug("\nmemory %dMB\n", le16_to_cpu(info->total_memory) >> 4); + size = (ptr - modes_bios) * sizeof(u16) + 2; + modes = malloc(size); + if (!modes) + return -ENOMEM; + memcpy(modes, modes_bios, size); + + regs->e.eax = VESA_GET_CUR_MODE; + BE_int86(0x10, regs, regs); + if (regs->e.eax != 0x4f) { + debug("VESA_GET_CUR_MODE: error %x\n", regs->e.eax); + return -ENOSYS; + } + debug("Current mode %x\n", regs->e.ebx); + + for (ptr = modes; *ptr != 0xffff; ptr++) { + int mode = le16_to_cpu(*ptr); + bool linear_ok; + int attr; + + break; + debug("Mode %x: ", mode); + memset(buffer, '\0', sizeof(struct vbe_mode_info)); + regs->e.eax = VESA_GET_MODE_INFO; + regs->e.ebx = 0; + regs->e.ecx = mode; + regs->e.edx = 0; + regs->e.esi = buffer_seg; + regs->e.edi = buffer_adr; + BE_int86(0x10, regs, regs); + if (regs->e.eax != 0x4f) { + debug("VESA_GET_MODE_INFO: error %x\n", regs->e.eax); + continue; + } + memcpy(mode_info->mode_info_block, buffer, + sizeof(struct vesa_mode_info)); + mode_info->valid = true; + vm = &mode_info->vesa; + attr = le16_to_cpu(vm->mode_attributes); + linear_ok = attr & 0x80; + debug("res %d x %d, %d bpp, mm %d, (Linear %s, attr %02x)\n", + le16_to_cpu(vm->x_resolution), + le16_to_cpu(vm->y_resolution), + vm->bits_per_pixel, vm->memory_model, + linear_ok ? "OK" : "not available", + attr); + debug("\tRGB pos=%d,%d,%d, size=%d,%d,%d\n", + vm->red_mask_pos, vm->green_mask_pos, vm->blue_mask_pos, + vm->red_mask_size, vm->green_mask_size, + vm->blue_mask_size); + } + + return 0; +} + +static int atibios_set_vesa_mode(RMREGS *regs, int vesa_mode, + struct vbe_mode_info *mode_info) +{ + void *buffer = (void *)(M.mem_base + vbe_offset); + u16 buffer_seg = (((unsigned long)vbe_offset) >> 4) & 0xff00; + u16 buffer_adr = ((unsigned long)vbe_offset) & 0xffff; + struct vesa_mode_info *vm; + + debug("VBE: Setting VESA mode %#04x\n", vesa_mode); + regs->e.eax = VESA_SET_MODE; + regs->e.ebx = vesa_mode; + /* request linear framebuffer mode and don't clear display */ + regs->e.ebx |= (1 << 14) | (1 << 15); + BE_int86(0x10, regs, regs); + if (regs->e.eax != 0x4f) { + debug("VESA_SET_MODE: error %x\n", regs->e.eax); + return -ENOSYS; + } + + memset(buffer, '\0', sizeof(struct vbe_mode_info)); + debug("VBE: Geting info for VESA mode %#04x\n", vesa_mode); + regs->e.eax = VESA_GET_MODE_INFO; + regs->e.ecx = vesa_mode; + regs->e.esi = buffer_seg; + regs->e.edi = buffer_adr; + BE_int86(0x10, regs, regs); + if (regs->e.eax != 0x4f) { + debug("VESA_GET_MODE_INFO: error %x\n", regs->e.eax); + return -ENOSYS; + } + + memcpy(mode_info->mode_info_block, buffer, + sizeof(struct vesa_mode_info)); + mode_info->valid = true; + mode_info->video_mode = vesa_mode; + vm = &mode_info->vesa; + vm->x_resolution = le16_to_cpu(vm->x_resolution); + vm->y_resolution = le16_to_cpu(vm->y_resolution); + vm->bytes_per_scanline = le16_to_cpu(vm->bytes_per_scanline); + vm->phys_base_ptr = le32_to_cpu(vm->phys_base_ptr); + vm->mode_attributes = le16_to_cpu(vm->mode_attributes); + debug("VBE: Init complete\n"); + + return 0; +} + /**************************************************************************** PARAMETERS: pcidev - PCI device info for the video card on the bus to boot -VGAInfo - BIOS emulator VGA info structure +vga_info - BIOS emulator VGA info structure REMARKS: This function executes the BIOS POST code on the controller. We assume that at this stage the controller has its I/O and memory space enabled and that all other controllers are in a disabled state. ****************************************************************************/ -static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) +static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info, + int vesa_mode, struct vbe_mode_info *mode_info) { RMREGS regs; RMSREGS sregs; @@ -84,13 +242,19 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev); /*Setup the X86 emulator for the VGA BIOS*/ - BE_setVGA(VGAInfo); + BE_setVGA(vga_info); /*Execute the BIOS POST code*/ BE_callRealMode(0xC000, 0x0003, ®s, &sregs); /*Cleanup and exit*/ - BE_getVGA(VGAInfo); + BE_getVGA(vga_info); + + /* Useful for debugging */ + if (0) + atibios_debug_mode(vga_info, ®s, vesa_mode, mode_info); + if (vesa_mode != -1) + atibios_set_vesa_mode(®s, vesa_mode, mode_info); } /**************************************************************************** @@ -244,60 +408,61 @@ REMARKS: Loads and POST's the display controllers BIOS, directly from the BIOS image we can extract over the PCI bus. ****************************************************************************/ -static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) +static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int vesa_mode, + struct vbe_mode_info *mode_info) { - u32 BIOSImageLen; - uchar *mappedBIOS; - uchar *copyOfBIOS; - - /*Allocate memory to store copy of BIOS from display controller*/ - if ((mappedBIOS = PCI_mapBIOSImage(pcidev)) == NULL) { - printf("videoboot: Video ROM failed to map!\n"); - return false; - } + u32 bios_image_len; + uchar *mapped_bios; + uchar *copy_of_bios; + + if (bios_rom) { + copy_of_bios = bios_rom; + bios_image_len = bios_len; + } else { + /* + * Allocate memory to store copy of BIOS from display + * controller + */ + mapped_bios = PCI_mapBIOSImage(pcidev); + if (mapped_bios == NULL) { + printf("videoboot: Video ROM failed to map!\n"); + return false; + } - BIOSImageLen = mappedBIOS[2] * 512; + bios_image_len = mapped_bios[2] * 512; - if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) { - printf("videoboot: Out of memory!\n"); - return false; + copy_of_bios = malloc(bios_image_len); + if (copy_of_bios == NULL) { + printf("videoboot: Out of memory!\n"); + return false; + } + memcpy(copy_of_bios, mapped_bios, bios_image_len); + PCI_unmapBIOSImage(pcidev, mapped_bios); } - memcpy(copyOfBIOS, mappedBIOS, BIOSImageLen); - PCI_unmapBIOSImage(pcidev, mappedBIOS); - - /*Save information in VGAInfo structure*/ - VGAInfo->function = PCI_FUNC(pcidev); - VGAInfo->device = PCI_DEV(pcidev); - VGAInfo->bus = PCI_BUS(pcidev); - VGAInfo->pcidev = pcidev; - VGAInfo->BIOSImage = copyOfBIOS; - VGAInfo->BIOSImageLen = BIOSImageLen; + /*Save information in vga_info structure*/ + vga_info->function = PCI_FUNC(pcidev); + vga_info->device = PCI_DEV(pcidev); + vga_info->bus = PCI_BUS(pcidev); + vga_info->pcidev = pcidev; + vga_info->BIOSImage = copy_of_bios; + vga_info->BIOSImageLen = bios_image_len; /*Now execute the BIOS POST for the device*/ - if (copyOfBIOS[0] != 0x55 || copyOfBIOS[1] != 0xAA) { + if (copy_of_bios[0] != 0x55 || copy_of_bios[1] != 0xAA) { printf("videoboot: Video ROM image is invalid!\n"); return false; } - PCI_doBIOSPOST(pcidev, VGAInfo); + PCI_doBIOSPOST(pcidev, vga_info, vesa_mode, mode_info); /*Reset the size of the BIOS image to the final size*/ - VGAInfo->BIOSImageLen = copyOfBIOS[2] * 512; + vga_info->BIOSImageLen = copy_of_bios[2] * 512; return true; } -/**************************************************************************** -PARAMETERS: -pcidev - PCI device info for the video card on the bus to boot -pVGAInfo - Place to return VGA info structure is requested -cleanUp - true to clean up on exit, false to leave emulator active - -REMARKS: -Boots the PCI/AGP video card on the bus using the Video ROM BIOS image -and the X86 BIOS emulator module. -****************************************************************************/ -int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp) +int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop) { BE_VGAInfo *VGAInfo; @@ -307,28 +472,70 @@ int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp) /*Initialise the x86 BIOS emulator*/ if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) { printf("videoboot: Out of memory!\n"); - return false; + return -ENOMEM; } memset(VGAInfo, 0, sizeof(*VGAInfo)); BE_init(0, 65536, VGAInfo, 0); + *vga_infop = VGAInfo; - /*Post all the display controller BIOS'es*/ - if (!PCI_postController(pcidev, VGAInfo)) - return false; + return 0; +} + +void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)) +{ + X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func); +} - /*Cleanup and exit the emulator if requested. If the BIOS emulator - is needed after booting the card, we will not call BE_exit and - leave it enabled for further use (ie: VESA driver etc). +int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info) +{ + /*Post all the display controller BIOS'es*/ + if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info, + vesa_mode, mode_info)) + return -EINVAL; + + /* + * Cleanup and exit the emulator if requested. If the BIOS emulator + * is needed after booting the card, we will not call BE_exit and + * leave it enabled for further use (ie: VESA driver etc). */ - if (cleanUp) { + if (clean_up) { BE_exit(); - if (VGAInfo->BIOSImage) - free(VGAInfo->BIOSImage); - free(VGAInfo); - VGAInfo = NULL; + if (vga_info->BIOSImage) + free(vga_info->BIOSImage); + free(vga_info); + vga_info = NULL; } - /*Return VGA info pointer if the caller requested it*/ + + return 0; +} + +/**************************************************************************** +PARAMETERS: +pcidev - PCI device info for the video card on the bus to boot +pVGAInfo - Place to return VGA info structure is requested +cleanUp - true to clean up on exit, false to leave emulator active + +REMARKS: +Boots the PCI/AGP video card on the bus using the Video ROM BIOS image +and the X86 BIOS emulator module. +****************************************************************************/ +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up) +{ + BE_VGAInfo *VGAInfo; + int ret; + + ret = biosemu_setup(pcidev, &VGAInfo); + if (ret) + return false; + ret = biosemu_run(pcidev, NULL, 0, VGAInfo, clean_up, -1, NULL); + if (ret) + return false; + + /* Return VGA info pointer if the caller requested it*/ if (pVGAInfo) *pVGAInfo = VGAInfo; + return true; } diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index ad88a53f0c..02c4286a85 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -48,18 +48,26 @@ ****************************************************************************/ #define __io -#include #include +#include #include "biosemui.h" /*------------------------- Global Variables ------------------------------*/ -#ifndef __i386__ +#ifndef CONFIG_X86EMU_RAW_IO static char *BE_biosDate = "08/14/99"; static u8 BE_model = 0xFC; static u8 BE_submodel = 0x00; #endif +#undef DEBUG_IO_ACCESS + +#ifdef DEBUG_IO_ACCESS +#define debug_io(fmt, ...) printf(fmt, ##__VA_ARGS__) +#else +#define debug_io(x, b...) +#endif + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** @@ -80,38 +88,40 @@ static u8 *BE_memaddr(u32 addr) if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { return (u8*)(_BE_env.biosmem_base + addr - 0xC0000); } else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) { - DB(printf("BE_memaddr: address %#lx may be invalid!\n", addr);) - return M.mem_base; + DB(printf("BE_memaddr: address %#lx may be invalid!\n", + (ulong)addr);) + return (u8 *)M.mem_base; } else if (addr >= 0xA0000 && addr <= 0xBFFFF) { return (u8*)(_BE_env.busmem_base + addr - 0xA0000); } -#ifdef __i386__ +#ifdef CONFIG_X86EMU_RAW_IO else if (addr >= 0xD0000 && addr <= 0xFFFFF) { /* We map the real System BIOS directly on real PC's */ - DB(printf("BE_memaddr: System BIOS address %#lx\n", addr);) - return _BE_env.busmem_base + addr - 0xA0000; + DB(printf("BE_memaddr: System BIOS address %#lx\n", + (ulong)addr);) + return (u8 *)_BE_env.busmem_base + addr - 0xA0000; } #else else if (addr >= 0xFFFF5 && addr < 0xFFFFE) { /* Return a faked BIOS date string for non-x86 machines */ - DB(printf("BE_memaddr - Returning BIOS date\n");) + debug_io("BE_memaddr - Returning BIOS date\n"); return (u8 *)(BE_biosDate + addr - 0xFFFF5); } else if (addr == 0xFFFFE) { /* Return system model identifier for non-x86 machines */ - DB(printf("BE_memaddr - Returning model\n");) + debug_io("BE_memaddr - Returning model\n"); return &BE_model; } else if (addr == 0xFFFFF) { /* Return system submodel identifier for non-x86 machines */ - DB(printf("BE_memaddr - Returning submodel\n");) + debug_io("BE_memaddr - Returning submodel\n"); return &BE_submodel; } #endif else if (addr > M.mem_size - 1) { HALT_SYS(); - return M.mem_base; + return (u8 *)M.mem_base; } - return M.mem_base + addr; + return (u8 *)(M.mem_base + addr); } /**************************************************************************** @@ -230,7 +240,7 @@ void X86API BE_wrl(u32 addr, u32 val) } } -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) /* For Non-Intel machines we may need to emulate some I/O port accesses that * the BIOS may try to access, such as the PCI config registers. @@ -258,6 +268,7 @@ static u8 VGA_inpb (const int port) { u8 val = 0xff; + debug_io("vga_inb.%04X -> ", (u16) port); switch (port) { case 0x3C0: /* 3C0 has funky characteristics because it can act as either @@ -560,7 +571,7 @@ u8 X86API BE_inb(X86EMU_pioAddr port) { u8 val = 0; -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) if (IS_VGA_PORT(port)){ /*seems reading port 0x3c3 return the high 16 bit of io port*/ if(port == 0x3c3) @@ -581,7 +592,12 @@ u8 X86API BE_inb(X86EMU_pioAddr port) val = LOG_inpb(port); } else #endif + { + debug_io("inb.%04X -> ", (u16) port); val = LOG_inpb(port); + debug_io("%02X\n", val); + } + return val; } @@ -601,7 +617,7 @@ u16 X86API BE_inw(X86EMU_pioAddr port) { u16 val = 0; -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) if (IS_PCI_PORT(port)) val = PCI_inp(port, REG_READ_WORD); else if (port < 0x100) { @@ -609,7 +625,12 @@ u16 X86API BE_inw(X86EMU_pioAddr port) val = LOG_inpw(port); } else #endif + { + debug_io("inw.%04X -> ", (u16) port); val = LOG_inpw(port); + debug_io("%04X\n", val); + } + return val; } @@ -629,14 +650,19 @@ u32 X86API BE_inl(X86EMU_pioAddr port) { u32 val = 0; -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) if (IS_PCI_PORT(port)) val = PCI_inp(port, REG_READ_DWORD); else if (port < 0x100) { val = LOG_inpd(port); } else #endif + { + debug_io("inl.%04X -> ", (u16) port); val = LOG_inpd(port); + debug_io("%08X\n", val); + } + return val; } @@ -652,7 +678,7 @@ through to the real hardware if we don't need to special case it. ****************************************************************************/ void X86API BE_outb(X86EMU_pioAddr port, u8 val) { -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) if (IS_VGA_PORT(port)) VGA_outpb(port, val); else if (IS_TIMER_PORT(port)) @@ -668,7 +694,11 @@ void X86API BE_outb(X86EMU_pioAddr port, u8 val) LOG_outpb(port, val); } else #endif + { + debug_io("outb.%04X <- %02X", (u16) port, val); LOG_outpb(port, val); + debug_io("\n"); + } } /**************************************************************************** @@ -683,19 +713,23 @@ through to the real hardware if we don't need to special case it. ****************************************************************************/ void X86API BE_outw(X86EMU_pioAddr port, u16 val) { -#if defined(DEBUG) || !defined(__i386__) - if (IS_VGA_PORT(port)) { - VGA_outpb(port, val); - VGA_outpb(port + 1, val >> 8); - } else if (IS_PCI_PORT(port)) - PCI_outp(port, val, REG_WRITE_WORD); - else if (port < 0x100) { - DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16) port, - val);) - LOG_outpw(port, val); - } else +#if !defined(CONFIG_X86EMU_RAW_IO) + if (IS_VGA_PORT(port)) { + VGA_outpb(port, val); + VGA_outpb(port + 1, val >> 8); + } else if (IS_PCI_PORT(port)) { + PCI_outp(port, val, REG_WRITE_WORD); + } else if (port < 0x100) { + DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16)port, + val);) + LOG_outpw(port, val); + } else #endif - LOG_outpw(port, val); + { + debug_io("outw.%04X <- %04X", (u16) port, val); + LOG_outpw(port, val); + debug_io("\n"); + } } /**************************************************************************** @@ -710,13 +744,17 @@ through to the real hardware if we don't need to special case it. ****************************************************************************/ void X86API BE_outl(X86EMU_pioAddr port, u32 val) { -#if defined(DEBUG) || !defined(__i386__) - if (IS_PCI_PORT(port)) +#if !defined(CONFIG_X86EMU_RAW_IO) + if (IS_PCI_PORT(port)) { PCI_outp(port, val, REG_WRITE_DWORD); - else if (port < 0x100) { + } else if (port < 0x100) { DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);) LOG_outpd(port, val); } else #endif + { + debug_io("outl.%04X <- %08X", (u16) port, val); LOG_outpd(port, val); + debug_io("\n"); + } } diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index bcc192fb2e..dd4c0a4f32 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -42,8 +42,8 @@ ****************************************************************************/ #define __io -#include #include +#include #include "biosemui.h" /*----------------------------- Implementation ----------------------------*/ @@ -84,14 +84,14 @@ static void X86API int42(int intno) PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8) ~ 0x02); return; } -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG else { printf("int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n", M.x86.R_AL); } #endif } -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG else { printf("int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n", M.x86.R_AH, M.x86.R_AL, M.x86.R_BL); diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h index 8c1f111fc8..7853015c1e 100644 --- a/drivers/bios_emulator/biosemui.h +++ b/drivers/bios_emulator/biosemui.h @@ -48,7 +48,7 @@ #include /*---------------------- Macros and type definitions ----------------------*/ -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG #define DB(x) x #else #define DB(x) do{}while(0); diff --git a/drivers/bios_emulator/include/biosemu.h b/drivers/bios_emulator/include/biosemu.h index e92e96e82b..124d79d80e 100644 --- a/drivers/bios_emulator/include/biosemu.h +++ b/drivers/bios_emulator/include/biosemu.h @@ -43,6 +43,8 @@ #ifndef __BIOSEMU_H #define __BIOSEMU_H +#include + #ifdef __KERNEL__ #include "x86emu.h" #else @@ -55,57 +57,6 @@ #pragma pack(1) -#ifndef __KERNEL__ -/**************************************************************************** -REMARKS: -Data structure used to describe the details specific to a particular VGA -controller. This information is used to allow the VGA controller to be -swapped on the fly within the BIOS emulator. - -HEADER: -biosemu.h - -MEMBERS: -pciInfo - PCI device information block for the controller -BIOSImage - Pointer to a read/write copy of the BIOS image -BIOSImageLen - Length of the BIOS image -LowMem - Copy of key low memory areas -****************************************************************************/ -typedef struct { - PCIDeviceInfo *pciInfo; - void *BIOSImage; - ulong BIOSImageLen; - uchar LowMem[1536]; -} BE_VGAInfo; -#else -/**************************************************************************** -REMARKS: -Data structure used to describe the details for the BIOS emulator system -environment as used by the X86 emulator library. - -HEADER: -biosemu.h - -MEMBERS: -vgaInfo - VGA BIOS information structure -biosmem_base - Base of the BIOS image -biosmem_limit - Limit of the BIOS image -busmem_base - Base of the VGA bus memory -****************************************************************************/ -typedef struct { - int function; - int device; - int bus; - u32 VendorID; - u32 DeviceID; - pci_dev_t pcidev; - void *BIOSImage; - u32 BIOSImageLen; - u8 LowMem[1536]; -} BE_VGAInfo; - -#endif /* __KERNEL__ */ - #define CRT_C 24 /* 24 CRT Controller Registers */ #define ATT_C 21 /* 21 Attribute Controller Registers */ #define GRA_C 9 /* 9 Graphics Controller Registers */ diff --git a/drivers/bios_emulator/include/x86emu.h b/drivers/bios_emulator/include/x86emu.h index a70a76874b..b28cdc6b8c 100644 --- a/drivers/bios_emulator/include/x86emu.h +++ b/drivers/bios_emulator/include/x86emu.h @@ -53,9 +53,9 @@ typedef u16 X86EMU_pioAddr; /*---------------------- Macros and type definitions ----------------------*/ -#if defined (CONFIG_ARM) +#if defined(CONFIG_ARM) #define GAS_LINE_COMMENT "@" -#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC) +#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_X86) #define GAS_LINE_COMMENT "#" #elif defined (CONFIG_SH) #define GAS_LINE_COMMENT "!" @@ -153,6 +153,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs); void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs); void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); + void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func); void X86EMU_prepareForInt(int num); /* decode.c */ @@ -160,7 +161,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ void X86EMU_exec(void); void X86EMU_halt_sys(void); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG #define HALT_SYS() \ printf("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ X86EMU_halt_sys() diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h index 268c9d391e..4962a2acaf 100644 --- a/drivers/bios_emulator/include/x86emu/debug.h +++ b/drivers/bios_emulator/include/x86emu/debug.h @@ -48,7 +48,7 @@ #define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ #define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */ -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) # define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) # define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) @@ -60,7 +60,7 @@ # define CHECK_DATA_ACCESS() #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) # define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) # define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) @@ -99,7 +99,11 @@ # define DEBUG_DECODE_NOPRINT() 0 #endif -#ifdef DEBUG +# define ERR_PRINTF(x) printf(x) +# define ERR_PRINTF2(x, y) printf(x, y) + +#ifdef CONFIG_X86EMU_DEBUG + # define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ x86emu_decode_printf(x) @@ -129,7 +133,7 @@ # define SAVE_IP_CS(x,y) #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG #define TRACE_REGS() \ if (DEBUG_DISASSEMBLE()) { \ x86emu_just_disassemble(); \ @@ -140,7 +144,7 @@ # define TRACE_REGS() #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() #else # define SINGLE_STEP() @@ -150,7 +154,7 @@ TRACE_REGS(); \ SINGLE_STEP() -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define START_OF_INSTR() # define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); # define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); @@ -160,7 +164,7 @@ # define END_OF_INSTR_NO_TRACE() #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define CALL_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ x86emu_dump_regs(); \ @@ -176,7 +180,7 @@ # define RETURN_TRACE(n,u,v) #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG #define DB(x) x #else #define DB(x) diff --git a/drivers/bios_emulator/include/x86emu/prim_asm.h b/drivers/bios_emulator/include/x86emu/prim_asm.h deleted file mode 100644 index 4cb4cab5d5..0000000000 --- a/drivers/bios_emulator/include/x86emu/prim_asm.h +++ /dev/null @@ -1,970 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: Watcom C++ 10.6 or later -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Inline assembler versions of the primitive operand -* functions for faster performance. At the moment this is -* x86 inline assembler, but these functions could be replaced -* with native inline assembler for each supported processor -* platform. -* -****************************************************************************/ - -#ifndef __X86EMU_PRIM_ASM_H -#define __X86EMU_PRIM_ASM_H - -#ifdef __WATCOMC__ - -#ifndef VALIDATE -#define __HAVE_INLINE_ASSEMBLER__ -#endif - -u32 get_flags_asm(void); -#pragma aux get_flags_asm = \ - "pushf" \ - "pop eax" \ - value [eax] \ - modify exact [eax]; - -u16 aaa_word_asm(u32 * flags, u16 d); -#pragma aux aaa_word_asm = \ - "push [edi]" \ - "popf" \ - "aaa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aas_word_asm(u32 * flags, u16 d); -#pragma aux aas_word_asm = \ - "push [edi]" \ - "popf" \ - "aas" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aad_word_asm(u32 * flags, u16 d); -#pragma aux aad_word_asm = \ - "push [edi]" \ - "popf" \ - "aad" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aam_word_asm(u32 * flags, u8 d); -#pragma aux aam_word_asm = \ - "push [edi]" \ - "popf" \ - "aam" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [ax] \ - modify exact [ax]; - -u8 adc_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux adc_byte_asm = \ - "push [edi]" \ - "popf" \ - "adc al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 adc_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux adc_word_asm = \ - "push [edi]" \ - "popf" \ - "adc ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 adc_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux adc_long_asm = \ - "push [edi]" \ - "popf" \ - "adc eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 add_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux add_byte_asm = \ - "push [edi]" \ - "popf" \ - "add al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 add_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux add_word_asm = \ - "push [edi]" \ - "popf" \ - "add ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 add_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux add_long_asm = \ - "push [edi]" \ - "popf" \ - "add eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 and_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux and_byte_asm = \ - "push [edi]" \ - "popf" \ - "and al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 and_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux and_word_asm = \ - "push [edi]" \ - "popf" \ - "and ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 and_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux and_long_asm = \ - "push [edi]" \ - "popf" \ - "and eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 cmp_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux cmp_byte_asm = \ - "push [edi]" \ - "popf" \ - "cmp al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 cmp_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux cmp_word_asm = \ - "push [edi]" \ - "popf" \ - "cmp ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 cmp_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux cmp_long_asm = \ - "push [edi]" \ - "popf" \ - "cmp eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 daa_byte_asm(u32 * flags, u8 d); -#pragma aux daa_byte_asm = \ - "push [edi]" \ - "popf" \ - "daa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u8 das_byte_asm(u32 * flags, u8 d); -#pragma aux das_byte_asm = \ - "push [edi]" \ - "popf" \ - "das" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u8 dec_byte_asm(u32 * flags, u8 d); -#pragma aux dec_byte_asm = \ - "push [edi]" \ - "popf" \ - "dec al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 dec_word_asm(u32 * flags, u16 d); -#pragma aux dec_word_asm = \ - "push [edi]" \ - "popf" \ - "dec ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 dec_long_asm(u32 * flags, u32 d); -#pragma aux dec_long_asm = \ - "push [edi]" \ - "popf" \ - "dec eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 inc_byte_asm(u32 * flags, u8 d); -#pragma aux inc_byte_asm = \ - "push [edi]" \ - "popf" \ - "inc al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 inc_word_asm(u32 * flags, u16 d); -#pragma aux inc_word_asm = \ - "push [edi]" \ - "popf" \ - "inc ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 inc_long_asm(u32 * flags, u32 d); -#pragma aux inc_long_asm = \ - "push [edi]" \ - "popf" \ - "inc eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 or_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux or_byte_asm = \ - "push [edi]" \ - "popf" \ - "or al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 or_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux or_word_asm = \ - "push [edi]" \ - "popf" \ - "or ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 or_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux or_long_asm = \ - "push [edi]" \ - "popf" \ - "or eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 neg_byte_asm(u32 * flags, u8 d); -#pragma aux neg_byte_asm = \ - "push [edi]" \ - "popf" \ - "neg al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 neg_word_asm(u32 * flags, u16 d); -#pragma aux neg_word_asm = \ - "push [edi]" \ - "popf" \ - "neg ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 neg_long_asm(u32 * flags, u32 d); -#pragma aux neg_long_asm = \ - "push [edi]" \ - "popf" \ - "neg eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 not_byte_asm(u32 * flags, u8 d); -#pragma aux not_byte_asm = \ - "push [edi]" \ - "popf" \ - "not al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 not_word_asm(u32 * flags, u16 d); -#pragma aux not_word_asm = \ - "push [edi]" \ - "popf" \ - "not ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 not_long_asm(u32 * flags, u32 d); -#pragma aux not_long_asm = \ - "push [edi]" \ - "popf" \ - "not eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 rcl_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rcl_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rcl_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rcl_word_asm = \ - "push [edi]" \ - "popf" \ - "rcl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rcl_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rcl_long_asm = \ - "push [edi]" \ - "popf" \ - "rcl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 rcr_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rcr_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rcr_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rcr_word_asm = \ - "push [edi]" \ - "popf" \ - "rcr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rcr_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rcr_long_asm = \ - "push [edi]" \ - "popf" \ - "rcr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 rol_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rol_byte_asm = \ - "push [edi]" \ - "popf" \ - "rol al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rol_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rol_word_asm = \ - "push [edi]" \ - "popf" \ - "rol ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rol_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rol_long_asm = \ - "push [edi]" \ - "popf" \ - "rol eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 ror_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux ror_byte_asm = \ - "push [edi]" \ - "popf" \ - "ror al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 ror_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux ror_word_asm = \ - "push [edi]" \ - "popf" \ - "ror ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 ror_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux ror_long_asm = \ - "push [edi]" \ - "popf" \ - "ror eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 shl_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux shl_byte_asm = \ - "push [edi]" \ - "popf" \ - "shl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 shl_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux shl_word_asm = \ - "push [edi]" \ - "popf" \ - "shl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 shl_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux shl_long_asm = \ - "push [edi]" \ - "popf" \ - "shl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 shr_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux shr_byte_asm = \ - "push [edi]" \ - "popf" \ - "shr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 shr_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux shr_word_asm = \ - "push [edi]" \ - "popf" \ - "shr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 shr_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux shr_long_asm = \ - "push [edi]" \ - "popf" \ - "shr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 sar_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sar_byte_asm = \ - "push [edi]" \ - "popf" \ - "sar al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 sar_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux sar_word_asm = \ - "push [edi]" \ - "popf" \ - "sar ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 sar_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux sar_long_asm = \ - "push [edi]" \ - "popf" \ - "sar eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u16 shld_word_asm(u32 * flags, u16 d, u16 fill, u8 s); -#pragma aux shld_word_asm = \ - "push [edi]" \ - "popf" \ - "shld ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ - modify exact [ax dx cl]; - -u32 shld_long_asm(u32 * flags, u32 d, u32 fill, u8 s); -#pragma aux shld_long_asm = \ - "push [edi]" \ - "popf" \ - "shld eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ - modify exact [eax edx cl]; - -u16 shrd_word_asm(u32 * flags, u16 d, u16 fill, u8 s); -#pragma aux shrd_word_asm = \ - "push [edi]" \ - "popf" \ - "shrd ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ - modify exact [ax dx cl]; - -u32 shrd_long_asm(u32 * flags, u32 d, u32 fill, u8 s); -#pragma aux shrd_long_asm = \ - "push [edi]" \ - "popf" \ - "shrd eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ - modify exact [eax edx cl]; - -u8 sbb_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sbb_byte_asm = \ - "push [edi]" \ - "popf" \ - "sbb al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 sbb_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux sbb_word_asm = \ - "push [edi]" \ - "popf" \ - "sbb ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 sbb_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux sbb_long_asm = \ - "push [edi]" \ - "popf" \ - "sbb eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 sub_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sub_byte_asm = \ - "push [edi]" \ - "popf" \ - "sub al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 sub_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux sub_word_asm = \ - "push [edi]" \ - "popf" \ - "sub ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 sub_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux sub_long_asm = \ - "push [edi]" \ - "popf" \ - "sub eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -void test_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux test_byte_asm = \ - "push [edi]" \ - "popf" \ - "test al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - modify exact [al bl]; - -void test_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux test_word_asm = \ - "push [edi]" \ - "popf" \ - "test ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - modify exact [ax bx]; - -void test_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux test_long_asm = \ - "push [edi]" \ - "popf" \ - "test eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - modify exact [eax ebx]; - -u8 xor_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux xor_byte_asm = \ - "push [edi]" \ - "popf" \ - "xor al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 xor_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux xor_word_asm = \ - "push [edi]" \ - "popf" \ - "xor ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 xor_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux xor_long_asm = \ - "push [edi]" \ - "popf" \ - "xor eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -void imul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s); -#pragma aux imul_byte_asm = \ - "push [edi]" \ - "popf" \ - "imul bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ - modify exact [esi ax bl]; - -void imul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s); -#pragma aux imul_word_asm = \ - "push [edi]" \ - "popf" \ - "imul bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [bx]\ - modify exact [esi edi ax bx dx]; - -void imul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s); -#pragma aux imul_long_asm = \ - "push [edi]" \ - "popf" \ - "imul ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [ebx] \ - modify exact [esi edi eax ebx edx]; - -void mul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s); -#pragma aux mul_byte_asm = \ - "push [edi]" \ - "popf" \ - "mul bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ - modify exact [esi ax bl]; - -void mul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s); -#pragma aux mul_word_asm = \ - "push [edi]" \ - "popf" \ - "mul bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [bx]\ - modify exact [esi edi ax bx dx]; - -void mul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s); -#pragma aux mul_long_asm = \ - "push [edi]" \ - "popf" \ - "mul ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [ebx] \ - modify exact [esi edi eax ebx edx]; - -void idiv_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s); -#pragma aux idiv_byte_asm = \ - "push [edi]" \ - "popf" \ - "idiv bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],al" \ - "mov [ecx],ah" \ - parm [edi] [esi] [ecx] [ax] [bl]\ - modify exact [esi edi ax bl]; - -void idiv_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s); -#pragma aux idiv_word_asm = \ - "push [edi]" \ - "popf" \ - "idiv bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [dx] [bx]\ - modify exact [esi edi ax dx bx]; - -void idiv_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s); -#pragma aux idiv_long_asm = \ - "push [edi]" \ - "popf" \ - "idiv ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ - modify exact [esi edi eax edx ebx]; - -void div_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s); -#pragma aux div_byte_asm = \ - "push [edi]" \ - "popf" \ - "div bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],al" \ - "mov [ecx],ah" \ - parm [edi] [esi] [ecx] [ax] [bl]\ - modify exact [esi edi ax bl]; - -void div_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s); -#pragma aux div_word_asm = \ - "push [edi]" \ - "popf" \ - "div bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [dx] [bx]\ - modify exact [esi edi ax dx bx]; - -void div_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s); -#pragma aux div_long_asm = \ - "push [edi]" \ - "popf" \ - "div ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ - modify exact [esi edi eax edx ebx]; - -#endif - -#endif /* __X86EMU_PRIM_ASM_H */ diff --git a/drivers/bios_emulator/include/x86emu/regs.h b/drivers/bios_emulator/include/x86emu/regs.h index a7fedd2f6c..29341297d9 100644 --- a/drivers/bios_emulator/include/x86emu/regs.h +++ b/drivers/bios_emulator/include/x86emu/regs.h @@ -282,7 +282,7 @@ typedef struct { u8 intno; volatile int intr; /* mask of pending interrupts */ int debug; -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG int check; u16 saved_ip; u16 saved_cs; diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 2fa8050f6a..27e90e441a 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -44,7 +44,7 @@ /*----------------------------- Implementation ----------------------------*/ -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG static void print_encoded_bytes(u16 s, u16 o); static void print_decoded_instruction(void); @@ -211,9 +211,7 @@ void X86EMU_dump_memory(u16 seg, u16 off, u32 amt) u32 start = off & 0xfffffff0; u32 end = (off + 16) & 0xfffffff0; u32 i; - u32 current; - current = start; while (end <= off + amt) { printk("%04x:%04x ", seg, start); for (i = start; i < off; i++) @@ -229,7 +227,7 @@ void X86EMU_dump_memory(u16 seg, u16 off, u32 amt) void x86emu_single_step(void) { char s[1024]; - int ps[10]; + int ps[10]; int ntok; int cmd; int done; @@ -238,8 +236,6 @@ void x86emu_single_step(void) static int breakpoint; static int noDecode = 1; - char *p; - if (DEBUG_BREAK()) { if (M.x86.saved_ip != breakpoint) { return; @@ -255,6 +251,8 @@ void x86emu_single_step(void) offset = M.x86.saved_ip; while (!done) { printk("-"); + ps[1] = 0; /* Avoid dodgy compiler warnings */ + ps[2] = 0; cmd = x86emu_parse_line(s, ps, &ntok); switch (cmd) { case 'u': diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index a782b817b7..da44c3d8d9 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -303,7 +303,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u8 fetch_data_byte( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -322,7 +322,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u16 fetch_data_word( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -341,7 +341,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u32 fetch_data_long( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -362,7 +362,7 @@ u8 fetch_data_byte_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -383,7 +383,7 @@ u16 fetch_data_word_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -404,7 +404,7 @@ u32 fetch_data_long_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -426,7 +426,7 @@ void store_data_byte( uint offset, u8 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -448,7 +448,7 @@ void store_data_word( uint offset, u16 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -470,7 +470,7 @@ void store_data_long( uint offset, u32 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -493,7 +493,7 @@ void store_data_byte_abs( uint offset, u8 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -516,7 +516,7 @@ void store_data_word_abs( uint offset, u16 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -539,7 +539,7 @@ void store_data_long_abs( uint offset, u32 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index f8e093d751..5752fee1cd 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -79,7 +79,7 @@ /* constant arrays to do several instructions in just one function */ -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG static char *x86emu_GenOpName[8] = { "ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"}; #endif @@ -160,7 +160,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) = sar_long, }; -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG static char *opF6_names[8] = { "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" }; @@ -179,7 +179,7 @@ void x86emuOp_illegal_op( { START_OF_INSTR(); if (M.x86.R_SP != 0) { - DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + DB(printf("ILLEGAL X86 OPCODE\n")); TRACE_REGS(); DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", M.x86.R_CS, M.x86.R_IP-1,op1)); @@ -1281,7 +1281,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1359,7 +1359,7 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1475,7 +1475,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1551,7 +1551,7 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -2148,7 +2148,7 @@ void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("POP\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); HALT_SYS(); } if (mod < 3) { @@ -3083,7 +3083,7 @@ void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3158,7 +3158,7 @@ void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3347,7 +3347,7 @@ void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + ERR_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); HALT_SYS(); } if (mod < 3) { @@ -3381,7 +3381,7 @@ void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); HALT_SYS(); } if (mod < 3) { @@ -3630,7 +3630,7 @@ void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3701,7 +3701,7 @@ void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3803,7 +3803,7 @@ void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3876,7 +3876,7 @@ void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3968,7 +3968,7 @@ void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("AAM\n"); a = fetch_byte_imm(); /* this is a stupid encoding. */ if (a != 10) { - DECODE_PRINTF("ERROR DECODING AAM\n"); + ERR_PRINTF("ERROR DECODING AAM\n"); TRACE_REGS(); HALT_SYS(); } @@ -4443,7 +4443,7 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) test_byte(destval, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: @@ -4490,7 +4490,7 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) test_byte(*destreg, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: @@ -4559,7 +4559,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) test_long(destval, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); HALT_SYS(); break; case 2: @@ -4611,7 +4611,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) test_word(destval, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); HALT_SYS(); break; case 2: @@ -4666,7 +4666,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) test_long(*destreg, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: @@ -4715,7 +4715,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) test_word(*destreg, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: @@ -4859,7 +4859,7 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4879,7 +4879,7 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) case 5: case 6: case 7: - DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + ERR_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x\n", mod); HALT_SYS(); break; } @@ -4923,7 +4923,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4961,7 +4961,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("PUSH\t"); break; case 7: - DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + ERR_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); HALT_SYS(); break; } @@ -5092,7 +5092,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) M.x86.R_IP = *destreg; break; case 3: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + ERR_PRINTF("OPERATION UNDEFINED 0XFF\n"); TRACE_AND_STEP(); HALT_SYS(); break; @@ -5104,7 +5104,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) M.x86.R_IP = (u16) (*destreg); break; case 5: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + ERR_PRINTF("OPERATION UNDEFINED 0XFF\n"); TRACE_AND_STEP(); HALT_SYS(); break; diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 59dbb422dd..be4ef36443 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -58,7 +58,7 @@ void x86emuOp2_illegal_op( u8 op2) { START_OF_INSTR(); - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", M.x86.R_CS, M.x86.R_IP-2,op2); @@ -1089,7 +1089,7 @@ void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTC\t"); break; default: - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index 21f9730bec..0ba9c0c105 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -273,6 +273,11 @@ void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs) sys_outl = funcs->outl; } +void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func) +{ + _X86EMU_intrTab[intnum] = func; +} + /**************************************************************************** PARAMETERS: funcs - New interrupt vector table to make active diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 2016e98440..8697da4262 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -5,40 +5,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libblock.o - -COBJS-$(CONFIG_SCSI_AHCI) += ahci.o -COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o -COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o -COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o -COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o -COBJS-$(CONFIG_LIBATA) += libata.o -COBJS-$(CONFIG_MVSATA_IDE) += mvsata_ide.o -COBJS-$(CONFIG_MX51_PATA) += mxc_ata.o -COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o -COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o -COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o -COBJS-$(CONFIG_SATA_SIL) += sata_sil.o -COBJS-$(CONFIG_IDE_SIL680) += sil680.o -COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o -COBJS-$(CONFIG_SYSTEMACE) += systemace.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_SCSI_AHCI) += ahci.o +obj-$(CONFIG_ATA_PIIX) += ata_piix.o +obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o +obj-$(CONFIG_FSL_SATA) += fsl_sata.o +obj-$(CONFIG_IDE_FTIDE020) += ftide020.o +obj-$(CONFIG_LIBATA) += libata.o +obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o +obj-$(CONFIG_MX51_PATA) += mxc_ata.o +obj-$(CONFIG_PATA_BFIN) += pata_bfin.o +obj-$(CONFIG_SATA_DWC) += sata_dwc.o +obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o +obj-$(CONFIG_SATA_SIL) += sata_sil.o +obj-$(CONFIG_IDE_SIL680) += sil680.o +obj-$(CONFIG_SANDBOX) += sandbox.o +obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o +obj-$(CONFIG_SYSTEMACE) += systemace.o diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index e455ba5fb6..c908fab450 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -16,14 +16,14 @@ #include #include #include -#include +#include #include #include static int ata_io_flush(u8 port); struct ahci_probe_ent *probe_ent = NULL; -hd_driveid_t *ataid[AHCI_MAX_PORTS]; +u16 *ataid[AHCI_MAX_PORTS]; #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) @@ -38,10 +38,10 @@ hd_driveid_t *ataid[AHCI_MAX_PORTS]; #endif /* Maximum timeouts for each event */ -#define WAIT_MS_SPINUP 10000 +#define WAIT_MS_SPINUP 20000 #define WAIT_MS_DATAIO 5000 #define WAIT_MS_FLUSH 5000 -#define WAIT_MS_LINKUP 4 +#define WAIT_MS_LINKUP 200 static inline u32 ahci_port_base(u32 base, u32 port) { @@ -107,6 +107,62 @@ static int waiting_for_cmd_completed(volatile u8 *offset, return (i < timeout_msec) ? 0 : -1; } +int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) +{ + u32 tmp; + int j = 0; + u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; + + /* + * Bring up SATA link. + * SATA link bringup time is usually less than 1 ms; only very + * rarely has it taken between 1-2 ms. Never seen it above 2 ms. + */ + while (j < WAIT_MS_LINKUP) { + tmp = readl(port_mmio + PORT_SCR_STAT); + tmp &= PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_PHYRDY) + return 0; + udelay(1000); + j++; + } + return 1; +} + +#ifdef CONFIG_SUNXI_AHCI +/* The sunxi AHCI controller requires this undocumented setup */ +static void sunxi_dma_init(volatile u8 *port_mmio) +{ + clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); +} +#endif + +int ahci_reset(u32 base) +{ + int i = 1000; + u32 host_ctl_reg = base + HOST_CTL; + u32 tmp = readl(host_ctl_reg); /* global controller reset */ + + if ((tmp & HOST_RESET) == 0) + writel_with_flush(tmp | HOST_RESET, host_ctl_reg); + + /* + * reset must complete within 1 second, or + * the hardware should be considered fried. + */ + do { + udelay(1000); + tmp = readl(host_ctl_reg); + i--; + } while ((i > 0) && (tmp & HOST_RESET)); + + if (i == 0) { + printf("controller reset failed (0x%x)\n", tmp); + return -1; + } + + return 0; +} static int ahci_host_init(struct ahci_probe_ent *probe_ent) { @@ -117,8 +173,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) #endif volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; u32 tmp, cap_save, cmd; - int i, j; + int i, j, ret; volatile u8 *port_mmio; + u32 port_map; debug("ahci_host_init: start\n"); @@ -126,23 +183,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) cap_save &= ((1 << 28) | (1 << 17)); cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ - /* global controller reset */ - tmp = readl(mmio + HOST_CTL); - if ((tmp & HOST_RESET) == 0) - writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); - - /* reset must complete within 1 second, or - * the hardware should be considered fried. - */ - i = 1000; - do { - udelay(1000); - tmp = readl(mmio + HOST_CTL); - if (!i--) { - debug("controller reset failed (0x%x)\n", tmp); - return -1; - } - } while (tmp & HOST_RESET); + ret = ahci_reset(probe_ent->mmio_base); + if (ret) + return ret; writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); writel(cap_save, mmio + HOST_CAP); @@ -160,6 +203,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) #endif probe_ent->cap = readl(mmio + HOST_CAP); probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + port_map = probe_ent->port_map; probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; debug("cap 0x%x port_map 0x%x n_ports %d\n", @@ -169,6 +213,8 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; for (i = 0; i < probe_ent->n_ports; i++) { + if (!(port_map & (1 << i))) + continue; probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); port_mmio = (u8 *) probe_ent->port[i].port_mmio; ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); @@ -188,27 +234,20 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) msleep(500); } +#ifdef CONFIG_SUNXI_AHCI + sunxi_dma_init(port_mmio); +#endif + /* Add the spinup command to whatever mode bits may * already be on in the command register. */ cmd = readl(port_mmio + PORT_CMD); - cmd |= PORT_CMD_FIS_RX; cmd |= PORT_CMD_SPIN_UP; writel_with_flush(cmd, port_mmio + PORT_CMD); - /* Bring up SATA link. - * SATA link bringup time is usually less than 1 ms; only very - * rarely has it taken between 1-2 ms. Never seen it above 2 ms. - */ - j = 0; - while (j < WAIT_MS_LINKUP) { - tmp = readl(port_mmio + PORT_SCR_STAT); - if ((tmp & 0xf) == 0x3) - break; - udelay(1000); - j++; - } - if (j == WAIT_MS_LINKUP) { + /* Bring up SATA link. */ + ret = ahci_link_up(probe_ent, i); + if (ret) { printf("SATA link %d timeout.\n", i); continue; } else { @@ -225,11 +264,23 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) j = 0; while (j < WAIT_MS_SPINUP) { tmp = readl(port_mmio + PORT_TFDATA); - if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ))) + if (!(tmp & (ATA_BUSY | ATA_DRQ))) break; udelay(1000); + tmp = readl(port_mmio + PORT_SCR_STAT); + tmp &= PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_PHYRDY) + break; j++; } + + tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; + if (tmp == PORT_SCR_STAT_DET_COMINIT) { + debug("SATA link %d down (COMINIT received), retrying...\n", i); + i--; + continue; + } + printf("Target spinup took %d ms.\n", j); if (j == WAIT_MS_SPINUP) debug("timeout.\n"); @@ -254,7 +305,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) /* register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); debug("SATA port %d status: 0x%x\n", i, tmp); - if ((tmp & 0xf) == 0x03) + if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) probe_ent->link_port_map |= (0x01 << i); } @@ -351,9 +402,12 @@ static int ahci_init_one(pci_dev_t pdev) u16 vendor; int rc; - memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); - probe_ent = malloc(sizeof(struct ahci_probe_ent)); + if (!probe_ent) { + printf("%s: No memory for probe_ent\n", __func__); + return -ENOMEM; + } + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->dev = pdev; @@ -442,7 +496,7 @@ static void ahci_set_feature(u8 port) memset(fis, 0, sizeof(fis)); fis[0] = 0x27; fis[1] = 1 << 7; - fis[2] = ATA_CMD_SETF; + fis[2] = ATA_CMD_SET_FEATURES; fis[3] = SETFEATURES_XFER; fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; @@ -459,6 +513,20 @@ static void ahci_set_feature(u8 port) } #endif +static int wait_spinup(volatile u8 *port_mmio) +{ + ulong start; + u32 tf_data; + + start = get_timer(0); + do { + tf_data = readl(port_mmio + PORT_TFDATA); + if (!(tf_data & ATA_BUSY)) + return 0; + } while (get_timer(start) < WAIT_MS_SPINUP); + + return -ETIMEDOUT; +} static int ahci_port_start(u8 port) { @@ -478,7 +546,7 @@ static int ahci_port_start(u8 port) mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); if (!mem) { free(pp); - printf("No mem for table!\n"); + printf("%s: No mem for table!\n", __func__); return -ENOMEM; } @@ -515,13 +583,21 @@ static int ahci_port_start(u8 port) writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); +#ifdef CONFIG_SUNXI_AHCI + sunxi_dma_init(port_mmio); +#endif + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | PORT_CMD_START, port_mmio + PORT_CMD); debug("Exit start port %d\n", port); - return 0; + /* + * Make sure interface is not busy based on error and status + * information from task file data register before proceeding + */ + return wait_spinup(port_mmio); } @@ -580,33 +656,12 @@ static char *ata_id_strcpy(u16 *target, u16 *src, int len) return (char *)target; } - -static void dump_ataid(hd_driveid_t *ataid) -{ - debug("(49)ataid->capability = 0x%x\n", ataid->capability); - debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); - debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); - debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); - debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); - debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); - debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); - debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); - debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); - debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); - debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); - debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); - debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); - debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); - debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); -} - - /* * SCSI INQUIRY command operation. */ static int ata_scsiop_inquiry(ccb *pccb) { - u8 hdr[] = { + static const u8 hdr[] = { 0, 0, 0x5, /* claim SPC-3 version compatibility */ @@ -614,7 +669,8 @@ static int ata_scsiop_inquiry(ccb *pccb) 95 - 4, }; u8 fis[20]; - u8 *tmpid; + u16 *idbuf; + ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); u8 port; /* Clean ccb data buffer */ @@ -629,28 +685,37 @@ static int ata_scsiop_inquiry(ccb *pccb) /* Construct the FIS */ fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_IDENT; /* Command byte. */ + fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ /* Read id from sata */ port = pccb->target; - if (!(tmpid = malloc(sizeof(hd_driveid_t)))) - return -ENOMEM; - if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid, - sizeof(hd_driveid_t), 0)) { + if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, + ATA_ID_WORDS * 2, 0)) { debug("scsi_ahci: SCSI inquiry command failure.\n"); return -EIO; } - if (ataid[port]) - free(ataid[port]); - ataid[port] = (hd_driveid_t *) tmpid; + if (!ataid[port]) { + ataid[port] = malloc(ATA_ID_WORDS * 2); + if (!ataid[port]) { + printf("%s: No memory for ataid[port]\n", __func__); + return -ENOMEM; + } + } + + idbuf = ataid[port]; + + memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); + ata_swap_buf_le16(idbuf, ATA_ID_WORDS); memcpy(&pccb->pdata[8], "ATA ", 8); - ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); - ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); + ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); - dump_ataid(ataid[port]); +#ifdef DEBUG + ata_dump_id(idbuf); +#endif return 0; } @@ -696,9 +761,9 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) u16 now_blocks; /* number of blocks per iteration */ u32 transfer_size; /* number of bytes per iteration */ - now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); + now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks); - transfer_size = ATA_BLOCKSIZE * now_blocks; + transfer_size = ATA_SECT_SIZE * now_blocks; if (transfer_size > user_buffer_size) { printf("scsi_ahci: Error: buffer too small.\n"); return -EIO; @@ -753,6 +818,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) static int ata_scsiop_read_capacity10(ccb *pccb) { u32 cap; + u64 cap64; u32 block_size; if (!ataid[pccb->target]) { @@ -762,18 +828,11 @@ static int ata_scsiop_read_capacity10(ccb *pccb) return -EPERM; } - cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); - if (cap == 0xfffffff) { - unsigned short *cap48 = ataid[pccb->target]->lba48_capacity; - if (cap48[2] || cap48[3]) { - cap = 0xffffffff; - } else { - cap = (le16_to_cpu(cap48[1]) << 16) | - (le16_to_cpu(cap48[0])); - } - } + cap64 = ata_id_n_sectors(ataid[pccb->target]); + if (cap64 > 0x100000000ULL) + cap64 = 0xffffffff; - cap = cpu_to_be32(cap); + cap = cpu_to_be32(cap64); memcpy(pccb->pdata, &cap, sizeof(cap)); block_size = cpu_to_be32((u32)512); @@ -798,12 +857,7 @@ static int ata_scsiop_read_capacity16(ccb *pccb) return -EPERM; } - cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); - if (cap == 0xfffffff) { - memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap)); - cap = le64_to_cpu(cap); - } - + cap = ata_id_n_sectors(ataid[pccb->target]); cap = cpu_to_be64(cap); memcpy(pccb->pdata, &cap, sizeof(cap)); @@ -890,9 +944,12 @@ int ahci_init(u32 base) int i, rc = 0; u32 linkmap; - memset(ataid, 0, sizeof(ataid)); - probe_ent = malloc(sizeof(struct ahci_probe_ent)); + if (!probe_ent) { + printf("%s: No memory for probe_ent\n", __func__); + return -ENOMEM; + } + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->host_flags = ATA_FLAG_SATA @@ -928,6 +985,11 @@ int ahci_init(u32 base) err_out: return rc; } + +void __weak scsi_init(void) +{ +} + #endif /* @@ -966,12 +1028,11 @@ static int ata_io_flush(u8 port) } -void scsi_bus_reset(void) +__weak void scsi_bus_reset(void) { /*Not implement*/ } - void scsi_print_error(ccb * pccb) { /*The ahci error info can be read in the ahci driver*/ diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c index 5cf91ade8d..30426842cc 100644 --- a/drivers/block/ata_piix.c +++ b/drivers/block/ata_piix.c @@ -192,6 +192,11 @@ int init_sata(int dev) return 0; } +int reset_sata(int dev) +{ + return 0; +} + static inline u8 sata_inb(unsigned long ioaddr) { return inb(ioaddr); diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index 3569214297..30cc4e8cb9 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "dwc_ahsata.h" struct sata_port_regs { @@ -558,6 +559,10 @@ int init_sata(int dev) u32 linkmap; struct ahci_probe_ent *probe_ent = NULL; +#if defined(CONFIG_SOC_MX6) + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + return 1; +#endif if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { printf("The sata index %d is out of ranges\n\r", dev); return -1; @@ -587,6 +592,29 @@ int init_sata(int dev) return 0; } +int reset_sata(int dev) +{ + struct ahci_probe_ent *probe_ent; + struct sata_host_regs *host_mmio; + + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { + printf("The sata index %d is out of ranges\n\r", dev); + return -1; + } + + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + if (NULL == probe_ent) + /* not initialized, so nothing to reset */ + return 0; + + host_mmio = (struct sata_host_regs *)probe_ent->mmio_base; + setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); + while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) + udelay(100); + + return 0; +} + static void dwc_ahsata_print_info(int dev) { block_dev_desc_t *pdev = &(sata_dev_desc[dev]); @@ -859,6 +887,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, return blkcnt; } +int sata_port_status(int dev, int port) +{ + struct sata_port_regs *port_mmio; + struct ahci_probe_ent *probe_ent = NULL; + + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) + return -EINVAL; + + if (sata_dev_desc[dev].priv == NULL) + return -ENODEV; + + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio; + + return readl(&(port_mmio->ssts)) & SATA_PORT_SSTS_DET_MASK; +} + /* * SATA interface between low level driver and command layer */ diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index ebd626178d..71d7cec7bd 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -255,6 +255,11 @@ int init_sata(int dev) return 0; } +int reset_sata(int dev) +{ + return 0; +} + static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg) { printf("\n\rSATA: %08x\n\r", (u32)reg); diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 574bc40b10..e54d564bf7 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -12,7 +12,7 @@ #if defined(CONFIG_ORION5X) #include #elif defined(CONFIG_KIRKWOOD) -#include +#include #endif /* SATA port registers */ diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c index 27ecaf4f9e..c2673bd05d 100644 --- a/drivers/block/pata_bfin.c +++ b/drivers/block/pata_bfin.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1008,6 +1009,11 @@ int init_sata(int dev) return res; } +int reset_sata(int dev) +{ + return 0; +} + /* Read up to 255 sectors * * Returns sectors read diff --git a/drivers/block/pata_bfin.h b/drivers/block/pata_bfin.h index 2093cf06b4..b678f60b2d 100644 --- a/drivers/block/pata_bfin.h +++ b/drivers/block/pata_bfin.h @@ -43,7 +43,6 @@ struct ata_port { #define DRV_NAME "pata-bfin" #define DRV_VERSION "0.9" -#define __iomem #define ATA_REG_CTRL 0x0E #define ATA_REG_ALTSTATUS ATA_REG_CTRL diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c new file mode 100644 index 0000000000..73f4c4a9e9 --- /dev/null +++ b/drivers/block/sandbox.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2013 Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct host_block_dev host_devices[CONFIG_HOST_MAX_DEVICES]; + +static struct host_block_dev *find_host_device(int dev) +{ + if (dev >= 0 && dev < CONFIG_HOST_MAX_DEVICES) + return &host_devices[dev]; + + return NULL; +} + +static unsigned long host_block_read(int dev, unsigned long start, + lbaint_t blkcnt, void *buffer) +{ + struct host_block_dev *host_dev = find_host_device(dev); + + if (!host_dev) + return -1; + if (os_lseek(host_dev->fd, + start * host_dev->blk_dev.blksz, + OS_SEEK_SET) == -1) { + printf("ERROR: Invalid position\n"); + return -1; + } + ssize_t len = os_read(host_dev->fd, buffer, + blkcnt * host_dev->blk_dev.blksz); + if (len >= 0) + return len / host_dev->blk_dev.blksz; + return -1; +} + +static unsigned long host_block_write(int dev, unsigned long start, + lbaint_t blkcnt, const void *buffer) +{ + struct host_block_dev *host_dev = find_host_device(dev); + if (os_lseek(host_dev->fd, + start * host_dev->blk_dev.blksz, + OS_SEEK_SET) == -1) { + printf("ERROR: Invalid position\n"); + return -1; + } + ssize_t len = os_write(host_dev->fd, buffer, blkcnt * + host_dev->blk_dev.blksz); + if (len >= 0) + return len / host_dev->blk_dev.blksz; + return -1; +} + +int host_dev_bind(int dev, char *filename) +{ + struct host_block_dev *host_dev = find_host_device(dev); + + if (!host_dev) + return -1; + if (host_dev->blk_dev.priv) { + os_close(host_dev->fd); + host_dev->blk_dev.priv = NULL; + } + if (host_dev->filename) + free(host_dev->filename); + if (filename && *filename) { + host_dev->filename = strdup(filename); + } else { + host_dev->filename = NULL; + return 0; + } + + host_dev->fd = os_open(host_dev->filename, OS_O_RDWR); + if (host_dev->fd == -1) { + printf("Failed to access host backing file '%s'\n", + host_dev->filename); + return 1; + } + + block_dev_desc_t *blk_dev = &host_dev->blk_dev; + blk_dev->if_type = IF_TYPE_HOST; + blk_dev->priv = host_dev; + blk_dev->blksz = 512; + blk_dev->lba = os_lseek(host_dev->fd, 0, OS_SEEK_END) / blk_dev->blksz; + blk_dev->block_read = host_block_read; + blk_dev->block_write = host_block_write; + blk_dev->dev = dev; + blk_dev->part_type = PART_TYPE_UNKNOWN; + init_part(blk_dev); + + return 0; +} + +int host_get_dev_err(int dev, block_dev_desc_t **blk_devp) +{ + struct host_block_dev *host_dev = find_host_device(dev); + + if (!host_dev) + return -ENODEV; + + if (!host_dev->blk_dev.priv) + return -ENOENT; + + *blk_devp = &host_dev->blk_dev; + return 0; +} + +block_dev_desc_t *host_get_dev(int dev) +{ + block_dev_desc_t *blk_dev; + + if (host_get_dev_err(dev, &blk_dev)) + return NULL; + + return blk_dev; +} diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c index efca5eaba4..9e8b067cdc 100644 --- a/drivers/block/sata_dwc.c +++ b/drivers/block/sata_dwc.c @@ -423,6 +423,11 @@ int init_sata(int dev) return rc; } +int reset_sata(int dev) +{ + return 0; +} + static u8 ata_check_altstatus(struct ata_port *ap) { u8 val = 0; diff --git a/drivers/block/sata_sil.c b/drivers/block/sata_sil.c index 1f510cd265..daff7d4ab5 100644 --- a/drivers/block/sata_sil.c +++ b/drivers/block/sata_sil.c @@ -519,7 +519,7 @@ int init_sata(int dev) u16 word; if (init_done == 1 && dev < sata_info.maxport) - return 1; + return 0; init_done = 1; @@ -571,6 +571,11 @@ int init_sata(int dev) return 0; } +int reset_sata(int dev) +{ + return 0; +} + /* * SATA interface between low level driver and command layer */ diff --git a/drivers/block/sata_sil3114.c b/drivers/block/sata_sil3114.c index 3aa6fc9839..61ffb66a77 100644 --- a/drivers/block/sata_sil3114.c +++ b/drivers/block/sata_sil3114.c @@ -702,6 +702,11 @@ int init_sata (int dev) return res; } +int reset_sata(int dev) +{ + return 0; +} + /* Check if device is connected to port */ int sata_bus_probe (int portno) { diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c index c538e370e1..6f1ac85723 100644 --- a/drivers/block/sym53c8xx.c +++ b/drivers/block/sym53c8xx.c @@ -248,7 +248,7 @@ void scsi_print_error (ccb * pccb) /****************************************************************************** * sets-up the SCSI controller - * the base memory address is retrived via the pci_read_config_dword + * the base memory address is retrieved via the pci_read_config_dword */ void scsi_low_level_init(int busdevfunc) { diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index 2b517b6dfb..6f1c419c7a 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -2,28 +2,11 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libbootcount.o - -COBJS-y += bootcount.o -COBJS-$(CONFIG_AT91SAM9XE) += bootcount_at91.o -COBJS-$(CONFIG_BLACKFIN) += bootcount_blackfin.o -COBJS-$(CONFIG_SOC_DA8XX) += bootcount_davinci.o -COBJS-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################## +obj-y += bootcount.o +obj-$(CONFIG_AT91SAM9XE) += bootcount_at91.o +obj-$(CONFIG_BLACKFIN) += bootcount_blackfin.o +obj-$(CONFIG_SOC_DA8XX) += bootcount_davinci.o +obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o +obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o +obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o +obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index 3ad441393e..e0343f71d7 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -36,7 +36,7 @@ #endif /* defined(CONFIG_MPC8260) */ #if defined(CONFIG_QE) -#include +#include #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ QE_MURAM_SIZE - 2 * sizeof(u32)) diff --git a/drivers/bootcount/bootcount_davinci.c b/drivers/bootcount/bootcount_davinci.c index efa4d42cbf..fa87b5e7b9 100644 --- a/drivers/bootcount/bootcount_davinci.c +++ b/drivers/bootcount/bootcount_davinci.c @@ -2,12 +2,15 @@ * (C) Copyright 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * + * A bootcount driver for the RTC IP block found on many TI platforms. + * This requires the RTC clocks, etc, to be enabled prior to use and + * not all boards with this IP block on it will have the RTC in use. + * * SPDX-License-Identifier: GPL-2.0+ */ #include -#include -#include +#include void bootcount_store(ulong a) { @@ -21,17 +24,19 @@ void bootcount_store(ulong a) */ writel(RTC_KICK0R_WE, ®->kick0r); writel(RTC_KICK1R_WE, ®->kick1r); - raw_bootcount_store(®->scratch0, a); - raw_bootcount_store(®->scratch1, BOOTCOUNT_MAGIC); + raw_bootcount_store(®->scratch2, + (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff)); } ulong bootcount_load(void) { + unsigned long val; struct davinci_rtc *reg = (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; - if (raw_bootcount_load(®->scratch1) != BOOTCOUNT_MAGIC) + val = raw_bootcount_load(®->scratch2); + if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) return 0; else - return raw_bootcount_load(®->scratch0); + return val & 0x0000ffff; } diff --git a/drivers/bootcount/bootcount_env.c b/drivers/bootcount/bootcount_env.c new file mode 100644 index 0000000000..2d6e8db126 --- /dev/null +++ b/drivers/bootcount/bootcount_env.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +void bootcount_store(ulong a) +{ + int upgrade_available = getenv_ulong("upgrade_available", 10, 0); + + if (upgrade_available) { + setenv_ulong("bootcount", a); + saveenv(); + } +} + +ulong bootcount_load(void) +{ + int upgrade_available = getenv_ulong("upgrade_available", 10, 0); + ulong val = 0; + + if (upgrade_available) + val = getenv_ulong("bootcount", 10, 0); + + return val; +} diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c new file mode 100644 index 0000000000..e27b168c55 --- /dev/null +++ b/drivers/bootcount/bootcount_i2c.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define BC_MAGIC 0xbc + +void bootcount_store(ulong a) +{ + unsigned char buf[3]; + int ret; + + buf[0] = BC_MAGIC; + buf[1] = (a & 0xff); + ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + CONFIG_BOOTCOUNT_ALEN, buf, 2); + if (ret != 0) + puts("Error writing bootcount\n"); +} + +ulong bootcount_load(void) +{ + unsigned char buf[3]; + int ret; + + ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + CONFIG_BOOTCOUNT_ALEN, buf, 2); + if (ret != 0) { + puts("Error loading bootcount\n"); + return 0; + } + if (buf[0] == BC_MAGIC) + return buf[1]; + + bootcount_store(0); + + return 0; +} diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig new file mode 100644 index 0000000000..d2799dc861 --- /dev/null +++ b/drivers/core/Kconfig @@ -0,0 +1,6 @@ +config DM + bool "Enable Driver Model" + depends on !SPL_BUILD + help + This config option enables Driver Model. + To use legacy drivers, say N. diff --git a/drivers/core/Makefile b/drivers/core/Makefile new file mode 100644 index 0000000000..f14695b2d6 --- /dev/null +++ b/drivers/core/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (c) 2013 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DM) += device.o lists.o root.o uclass.o util.o +obj-$(CONFIG_OF_CONTROL) += simple-bus.o +obj-$(CONFIG_DM_DEVICE_REMOVE) += device-remove.o diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c new file mode 100644 index 0000000000..3a5f48df7a --- /dev/null +++ b/drivers/core/device-remove.c @@ -0,0 +1,195 @@ +/* + * Device manager + * + * Copyright (c) 2014 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * device_chld_unbind() - Unbind all device's children from the device + * + * On error, the function continues to unbind all children, and reports the + * first error. + * + * @dev: The device that is to be stripped of its children + * @return 0 on success, -ve on error + */ +static int device_chld_unbind(struct udevice *dev) +{ + struct udevice *pos, *n; + int ret, saved_ret = 0; + + assert(dev); + + list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { + ret = device_unbind(pos); + if (ret && !saved_ret) + saved_ret = ret; + } + + return saved_ret; +} + +/** + * device_chld_remove() - Stop all device's children + * @dev: The device whose children are to be removed + * @return 0 on success, -ve on error + */ +static int device_chld_remove(struct udevice *dev) +{ + struct udevice *pos, *n; + int ret; + + assert(dev); + + list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { + ret = device_remove(pos); + if (ret) + return ret; + } + + return 0; +} + +int device_unbind(struct udevice *dev) +{ + struct driver *drv; + int ret; + + if (!dev) + return -EINVAL; + + if (dev->flags & DM_FLAG_ACTIVATED) + return -EINVAL; + + drv = dev->driver; + assert(drv); + + if (drv->unbind) { + ret = drv->unbind(dev); + if (ret) + return ret; + } + + ret = device_chld_unbind(dev); + if (ret) + return ret; + + if (dev->flags & DM_FLAG_ALLOC_PDATA) { + free(dev->platdata); + dev->platdata = NULL; + } + if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) { + free(dev->parent_platdata); + dev->parent_platdata = NULL; + } + ret = uclass_unbind_device(dev); + if (ret) + return ret; + + if (dev->parent) + list_del(&dev->sibling_node); + free(dev); + + return 0; +} + +/** + * device_free() - Free memory buffers allocated by a device + * @dev: Device that is to be started + */ +void device_free(struct udevice *dev) +{ + int size; + + if (dev->driver->priv_auto_alloc_size) { + free(dev->priv); + dev->priv = NULL; + } + size = dev->uclass->uc_drv->per_device_auto_alloc_size; + if (size) { + free(dev->uclass_priv); + dev->uclass_priv = NULL; + } + if (dev->parent) { + size = dev->parent->driver->per_child_auto_alloc_size; + if (!size) { + size = dev->parent->uclass->uc_drv-> + per_child_auto_alloc_size; + } + if (size) { + free(dev->parent_priv); + dev->parent_priv = NULL; + } + } +} + +int device_remove(struct udevice *dev) +{ + struct driver *drv; + int ret; + + if (!dev) + return -EINVAL; + + if (!(dev->flags & DM_FLAG_ACTIVATED)) + return 0; + + drv = dev->driver; + assert(drv); + + ret = uclass_pre_remove_device(dev); + if (ret) + return ret; + + ret = device_chld_remove(dev); + if (ret) + goto err; + + if (drv->remove) { + ret = drv->remove(dev); + if (ret) + goto err_remove; + } + + if (dev->parent && dev->parent->driver->child_post_remove) { + ret = dev->parent->driver->child_post_remove(dev); + if (ret) { + dm_warn("%s: Device '%s' failed child_post_remove()", + __func__, dev->name); + } + } + + device_free(dev); + + dev->seq = -1; + dev->flags &= ~DM_FLAG_ACTIVATED; + + return ret; + +err_remove: + /* We can't put the children back */ + dm_warn("%s: Device '%s' failed to remove, but children are gone\n", + __func__, dev->name); +err: + ret = uclass_post_probe_device(dev); + if (ret) { + dm_warn("%s: Device '%s' failed to post_probe on error path\n", + __func__, dev->name); + } + + return ret; +} diff --git a/drivers/core/device.c b/drivers/core/device.c new file mode 100644 index 0000000000..b73d3b8961 --- /dev/null +++ b/drivers/core/device.c @@ -0,0 +1,451 @@ +/* + * Device manager + * + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int device_bind(struct udevice *parent, struct driver *drv, const char *name, + void *platdata, int of_offset, struct udevice **devp) +{ + struct udevice *dev; + struct uclass *uc; + int ret = 0; + + *devp = NULL; + if (!name) + return -EINVAL; + + ret = uclass_get(drv->id, &uc); + if (ret) + return ret; + + dev = calloc(1, sizeof(struct udevice)); + if (!dev) + return -ENOMEM; + + INIT_LIST_HEAD(&dev->sibling_node); + INIT_LIST_HEAD(&dev->child_head); + INIT_LIST_HEAD(&dev->uclass_node); + dev->platdata = platdata; + dev->name = name; + dev->of_offset = of_offset; + dev->parent = parent; + dev->driver = drv; + dev->uclass = uc; + + dev->seq = -1; + dev->req_seq = -1; +#ifdef CONFIG_OF_CONTROL + /* + * Some devices, such as a SPI bus, I2C bus and serial ports are + * numbered using aliases. + * + * This is just a 'requested' sequence, and will be + * resolved (and ->seq updated) when the device is probed. + */ + if (uc->uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS) { + if (uc->uc_drv->name && of_offset != -1) { + fdtdec_get_alias_seq(gd->fdt_blob, uc->uc_drv->name, + of_offset, &dev->req_seq); + } + } +#endif + if (!dev->platdata && drv->platdata_auto_alloc_size) { + dev->flags |= DM_FLAG_ALLOC_PDATA; + dev->platdata = calloc(1, drv->platdata_auto_alloc_size); + if (!dev->platdata) { + ret = -ENOMEM; + goto fail_alloc1; + } + } + if (parent) { + int size = parent->driver->per_child_platdata_auto_alloc_size; + + if (!size) { + size = parent->uclass->uc_drv-> + per_child_platdata_auto_alloc_size; + } + if (size) { + dev->flags |= DM_FLAG_ALLOC_PARENT_PDATA; + dev->parent_platdata = calloc(1, size); + if (!dev->parent_platdata) { + ret = -ENOMEM; + goto fail_alloc2; + } + } + } + + /* put dev into parent's successor list */ + if (parent) + list_add_tail(&dev->sibling_node, &parent->child_head); + + ret = uclass_bind_device(dev); + if (ret) + goto fail_uclass_bind; + + /* if we fail to bind we remove device from successors and free it */ + if (drv->bind) { + ret = drv->bind(dev); + if (ret) + goto fail_bind; + } + if (parent && parent->driver->child_post_bind) { + ret = parent->driver->child_post_bind(dev); + if (ret) + goto fail_child_post_bind; + } + + if (parent) + dm_dbg("Bound device %s to %s\n", dev->name, parent->name); + *devp = dev; + + return 0; + +fail_child_post_bind: + if (drv->unbind && drv->unbind(dev)) { + dm_warn("unbind() method failed on dev '%s' on error path\n", + dev->name); + } + +fail_bind: + if (uclass_unbind_device(dev)) { + dm_warn("Failed to unbind dev '%s' on error path\n", + dev->name); + } +fail_uclass_bind: + list_del(&dev->sibling_node); + if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) { + free(dev->parent_platdata); + dev->parent_platdata = NULL; + } +fail_alloc2: + if (dev->flags & DM_FLAG_ALLOC_PDATA) { + free(dev->platdata); + dev->platdata = NULL; + } +fail_alloc1: + free(dev); + + return ret; +} + +int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, + const struct driver_info *info, struct udevice **devp) +{ + struct driver *drv; + + drv = lists_driver_lookup_name(info->name); + if (!drv) + return -ENOENT; + if (pre_reloc_only && !(drv->flags & DM_FLAG_PRE_RELOC)) + return -EPERM; + + return device_bind(parent, drv, info->name, (void *)info->platdata, + -1, devp); +} + +int device_probe_child(struct udevice *dev, void *parent_priv) +{ + struct driver *drv; + int size = 0; + int ret; + int seq; + + if (!dev) + return -EINVAL; + + if (dev->flags & DM_FLAG_ACTIVATED) + return 0; + + drv = dev->driver; + assert(drv); + + /* Allocate private data if requested */ + if (drv->priv_auto_alloc_size) { + dev->priv = calloc(1, drv->priv_auto_alloc_size); + if (!dev->priv) { + ret = -ENOMEM; + goto fail; + } + } + /* Allocate private data if requested */ + size = dev->uclass->uc_drv->per_device_auto_alloc_size; + if (size) { + dev->uclass_priv = calloc(1, size); + if (!dev->uclass_priv) { + ret = -ENOMEM; + goto fail; + } + } + + /* Ensure all parents are probed */ + if (dev->parent) { + size = dev->parent->driver->per_child_auto_alloc_size; + if (!size) { + size = dev->parent->uclass->uc_drv-> + per_child_auto_alloc_size; + } + if (size) { + dev->parent_priv = calloc(1, size); + if (!dev->parent_priv) { + ret = -ENOMEM; + goto fail; + } + if (parent_priv) + memcpy(dev->parent_priv, parent_priv, size); + } + + ret = device_probe(dev->parent); + if (ret) + goto fail; + } + + seq = uclass_resolve_seq(dev); + if (seq < 0) { + ret = seq; + goto fail; + } + dev->seq = seq; + + ret = uclass_pre_probe_child(dev); + if (ret) + goto fail; + + if (dev->parent && dev->parent->driver->child_pre_probe) { + ret = dev->parent->driver->child_pre_probe(dev); + if (ret) + goto fail; + } + + if (drv->ofdata_to_platdata && dev->of_offset >= 0) { + ret = drv->ofdata_to_platdata(dev); + if (ret) + goto fail; + } + + if (drv->probe) { + ret = drv->probe(dev); + if (ret) + goto fail; + } + + dev->flags |= DM_FLAG_ACTIVATED; + + ret = uclass_post_probe_device(dev); + if (ret) { + dev->flags &= ~DM_FLAG_ACTIVATED; + goto fail_uclass; + } + + return 0; +fail_uclass: + if (device_remove(dev)) { + dm_warn("%s: Device '%s' failed to remove on error path\n", + __func__, dev->name); + } +fail: + dev->seq = -1; + device_free(dev); + + return ret; +} + +int device_probe(struct udevice *dev) +{ + return device_probe_child(dev, NULL); +} + +void *dev_get_platdata(struct udevice *dev) +{ + if (!dev) { + dm_warn("%s: null device\n", __func__); + return NULL; + } + + return dev->platdata; +} + +void *dev_get_parent_platdata(struct udevice *dev) +{ + if (!dev) { + dm_warn("%s: null device", __func__); + return NULL; + } + + return dev->parent_platdata; +} + +void *dev_get_priv(struct udevice *dev) +{ + if (!dev) { + dm_warn("%s: null device\n", __func__); + return NULL; + } + + return dev->priv; +} + +void *dev_get_parentdata(struct udevice *dev) +{ + if (!dev) { + dm_warn("%s: null device\n", __func__); + return NULL; + } + + return dev->parent_priv; +} + +static int device_get_device_tail(struct udevice *dev, int ret, + struct udevice **devp) +{ + if (ret) + return ret; + + ret = device_probe(dev); + if (ret) + return ret; + + *devp = dev; + + return 0; +} + +int device_get_child(struct udevice *parent, int index, struct udevice **devp) +{ + struct udevice *dev; + + list_for_each_entry(dev, &parent->child_head, sibling_node) { + if (!index--) + return device_get_device_tail(dev, 0, devp); + } + + return -ENODEV; +} + +int device_find_child_by_seq(struct udevice *parent, int seq_or_req_seq, + bool find_req_seq, struct udevice **devp) +{ + struct udevice *dev; + + *devp = NULL; + if (seq_or_req_seq == -1) + return -ENODEV; + + list_for_each_entry(dev, &parent->child_head, sibling_node) { + if ((find_req_seq ? dev->req_seq : dev->seq) == + seq_or_req_seq) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + +int device_get_child_by_seq(struct udevice *parent, int seq, + struct udevice **devp) +{ + struct udevice *dev; + int ret; + + *devp = NULL; + ret = device_find_child_by_seq(parent, seq, false, &dev); + if (ret == -ENODEV) { + /* + * We didn't find it in probed devices. See if there is one + * that will request this seq if probed. + */ + ret = device_find_child_by_seq(parent, seq, true, &dev); + } + return device_get_device_tail(dev, ret, devp); +} + +int device_find_child_by_of_offset(struct udevice *parent, int of_offset, + struct udevice **devp) +{ + struct udevice *dev; + + *devp = NULL; + + list_for_each_entry(dev, &parent->child_head, sibling_node) { + if (dev->of_offset == of_offset) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + +int device_get_child_by_of_offset(struct udevice *parent, int seq, + struct udevice **devp) +{ + struct udevice *dev; + int ret; + + *devp = NULL; + ret = device_find_child_by_of_offset(parent, seq, &dev); + return device_get_device_tail(dev, ret, devp); +} + +int device_find_first_child(struct udevice *parent, struct udevice **devp) +{ + if (list_empty(&parent->child_head)) { + *devp = NULL; + } else { + *devp = list_first_entry(&parent->child_head, struct udevice, + sibling_node); + } + + return 0; +} + +int device_find_next_child(struct udevice **devp) +{ + struct udevice *dev = *devp; + struct udevice *parent = dev->parent; + + if (list_is_last(&dev->sibling_node, &parent->child_head)) { + *devp = NULL; + } else { + *devp = list_entry(dev->sibling_node.next, struct udevice, + sibling_node); + } + + return 0; +} + +struct udevice *dev_get_parent(struct udevice *child) +{ + return child->parent; +} + +ulong dev_get_of_data(struct udevice *dev) +{ + return dev->of_id->data; +} + +enum uclass_id device_get_uclass_id(struct udevice *dev) +{ + return dev->uclass->uc_drv->id; +} diff --git a/drivers/core/lists.c b/drivers/core/lists.c new file mode 100644 index 0000000000..ff115c4723 --- /dev/null +++ b/drivers/core/lists.c @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct driver *lists_driver_lookup_name(const char *name) +{ + struct driver *drv = + ll_entry_start(struct driver, driver); + const int n_ents = ll_entry_count(struct driver, driver); + struct driver *entry; + + for (entry = drv; entry != drv + n_ents; entry++) { + if (!strcmp(name, entry->name)) + return entry; + } + + /* Not found */ + return NULL; +} + +struct uclass_driver *lists_uclass_lookup(enum uclass_id id) +{ + struct uclass_driver *uclass = + ll_entry_start(struct uclass_driver, uclass); + const int n_ents = ll_entry_count(struct uclass_driver, uclass); + struct uclass_driver *entry; + + for (entry = uclass; entry != uclass + n_ents; entry++) { + if (entry->id == id) + return entry; + } + + return NULL; +} + +int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only) +{ + struct driver_info *info = + ll_entry_start(struct driver_info, driver_info); + const int n_ents = ll_entry_count(struct driver_info, driver_info); + struct driver_info *entry; + struct udevice *dev; + int result = 0; + int ret; + + for (entry = info; entry != info + n_ents; entry++) { + ret = device_bind_by_name(parent, pre_reloc_only, entry, &dev); + if (ret && ret != -EPERM) { + dm_warn("No match for driver '%s'\n", entry->name); + if (!result || ret != -ENOENT) + result = ret; + } + } + + return result; +} + +int device_bind_driver(struct udevice *parent, const char *drv_name, + const char *dev_name, struct udevice **devp) +{ + struct driver *drv; + int ret; + + drv = lists_driver_lookup_name(drv_name); + if (!drv) { + printf("Cannot find driver '%s'\n", drv_name); + return -ENOENT; + } + ret = device_bind(parent, drv, dev_name, NULL, -1, devp); + if (ret) { + printf("Cannot create device named '%s' (err=%d)\n", + dev_name, ret); + return ret; + } + + return 0; +} + +#ifdef CONFIG_OF_CONTROL +/** + * driver_check_compatible() - Check if a driver is compatible with this node + * + * @param blob: Device tree pointer + * @param offset: Offset of node in device tree + * @param of_match: List of compatible strings to match + * @param of_idp: Returns the match that was found + * @return 0 if there is a match, -ENOENT if no match, -ENODEV if the node + * does not have a compatible string, other error <0 if there is a device + * tree error + */ +static int driver_check_compatible(const void *blob, int offset, + const struct udevice_id *of_match, + const struct udevice_id **of_idp) +{ + int ret; + + *of_idp = NULL; + if (!of_match) + return -ENOENT; + + while (of_match->compatible) { + ret = fdt_node_check_compatible(blob, offset, + of_match->compatible); + if (!ret) { + *of_idp = of_match; + return 0; + } else if (ret == -FDT_ERR_NOTFOUND) { + return -ENODEV; + } else if (ret < 0) { + return -EINVAL; + } + of_match++; + } + + return -ENOENT; +} + +int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, + struct udevice **devp) +{ + struct driver *driver = ll_entry_start(struct driver, driver); + const int n_ents = ll_entry_count(struct driver, driver); + const struct udevice_id *id; + struct driver *entry; + struct udevice *dev; + bool found = false; + const char *name; + int result = 0; + int ret = 0; + + dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL)); + if (devp) + *devp = NULL; + for (entry = driver; entry != driver + n_ents; entry++) { + ret = driver_check_compatible(blob, offset, entry->of_match, + &id); + name = fdt_get_name(blob, offset, NULL); + if (ret == -ENOENT) { + continue; + } else if (ret == -ENODEV) { + dm_dbg("Device '%s' has no compatible string\n", name); + break; + } else if (ret) { + dm_warn("Device tree error at offset %d\n", offset); + result = ret; + break; + } + + dm_dbg(" - found match at '%s'\n", entry->name); + ret = device_bind(parent, entry, name, NULL, offset, &dev); + if (ret) { + dm_warn("Error binding driver '%s'\n", entry->name); + return ret; + } else { + dev->of_id = id; + found = true; + if (devp) + *devp = dev; + } + break; + } + + if (!found && !result && ret != -ENODEV) { + dm_dbg("No match for node '%s'\n", + fdt_get_name(blob, offset, NULL)); + } + + return result; +} +#endif diff --git a/drivers/core/root.c b/drivers/core/root.c new file mode 100644 index 0000000000..73e3c7228e --- /dev/null +++ b/drivers/core/root.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct driver_info root_info = { + .name = "root_driver", +}; + +struct udevice *dm_root(void) +{ + if (!gd->dm_root) { + dm_warn("Virtual root driver does not exist!\n"); + return NULL; + } + + return gd->dm_root; +} + +int dm_init(void) +{ + int ret; + + if (gd->dm_root) { + dm_warn("Virtual root driver already exists!\n"); + return -EINVAL; + } + INIT_LIST_HEAD(&DM_UCLASS_ROOT_NON_CONST); + + ret = device_bind_by_name(NULL, false, &root_info, &DM_ROOT_NON_CONST); + if (ret) + return ret; +#ifdef CONFIG_OF_CONTROL + DM_ROOT_NON_CONST->of_offset = 0; +#endif + ret = device_probe(DM_ROOT_NON_CONST); + if (ret) + return ret; + + return 0; +} + +int dm_uninit(void) +{ + device_remove(dm_root()); + device_unbind(dm_root()); + + return 0; +} + +int dm_scan_platdata(bool pre_reloc_only) +{ + int ret; + + ret = lists_bind_drivers(DM_ROOT_NON_CONST, pre_reloc_only); + if (ret == -ENOENT) { + dm_warn("Some drivers were not found\n"); + ret = 0; + } + + return ret; +} + +#ifdef CONFIG_OF_CONTROL +int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset, + bool pre_reloc_only) +{ + int ret = 0, err; + + for (offset = fdt_first_subnode(blob, offset); + offset > 0; + offset = fdt_next_subnode(blob, offset)) { + if (pre_reloc_only && + !fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL)) + continue; + if (!fdtdec_get_is_enabled(blob, offset)) { + dm_dbg(" - ignoring disabled device\n"); + continue; + } + err = lists_bind_fdt(parent, blob, offset, NULL); + if (err && !ret) + ret = err; + } + + if (ret) + dm_warn("Some drivers failed to bind\n"); + + return ret; +} + +int dm_scan_fdt(const void *blob, bool pre_reloc_only) +{ + return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only); +} +#endif + +__weak int dm_scan_other(bool pre_reloc_only) +{ + return 0; +} + +int dm_init_and_scan(bool pre_reloc_only) +{ + int ret; + + ret = dm_init(); + if (ret) { + debug("dm_init() failed: %d\n", ret); + return ret; + } + ret = dm_scan_platdata(pre_reloc_only); + if (ret) { + debug("dm_scan_platdata() failed: %d\n", ret); + return ret; + } +#ifdef CONFIG_OF_CONTROL + ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only); + if (ret) { + debug("dm_scan_fdt() failed: %d\n", ret); + return ret; + } +#endif + ret = dm_scan_other(pre_reloc_only); + if (ret) + return ret; + + return 0; +} + +/* This is the root driver - all drivers are children of this */ +U_BOOT_DRIVER(root_driver) = { + .name = "root_driver", + .id = UCLASS_ROOT, +}; + +/* This is the root uclass */ +UCLASS_DRIVER(root) = { + .name = "root", + .id = UCLASS_ROOT, +}; diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c new file mode 100644 index 0000000000..3ea4d8230b --- /dev/null +++ b/drivers/core/simple-bus.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int simple_bus_post_bind(struct udevice *dev) +{ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + +UCLASS_DRIVER(simple_bus) = { + .id = UCLASS_SIMPLE_BUS, + .name = "simple_bus", + .post_bind = simple_bus_post_bind, +}; + +static const struct udevice_id generic_simple_bus_ids[] = { + { .compatible = "simple-bus" }, + { } +}; + +U_BOOT_DRIVER(simple_bus_drv) = { + .name = "generic_simple_bus", + .id = UCLASS_SIMPLE_BUS, + .of_match = generic_simple_bus_ids, +}; diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c new file mode 100644 index 0000000000..289a5d2d53 --- /dev/null +++ b/drivers/core/uclass.c @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct uclass *uclass_find(enum uclass_id key) +{ + struct uclass *uc; + + if (!gd->dm_root) + return NULL; + /* + * TODO(sjg@chromium.org): Optimise this, perhaps moving the found + * node to the start of the list, or creating a linear array mapping + * id to node. + */ + list_for_each_entry(uc, &gd->uclass_root, sibling_node) { + if (uc->uc_drv->id == key) + return uc; + } + + return NULL; +} + +/** + * uclass_add() - Create new uclass in list + * @id: Id number to create + * @ucp: Returns pointer to uclass, or NULL on error + * @return 0 on success, -ve on error + * + * The new uclass is added to the list. There must be only one uclass for + * each id. + */ +static int uclass_add(enum uclass_id id, struct uclass **ucp) +{ + struct uclass_driver *uc_drv; + struct uclass *uc; + int ret; + + *ucp = NULL; + uc_drv = lists_uclass_lookup(id); + if (!uc_drv) { + dm_warn("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n", + id); + return -ENOENT; + } + uc = calloc(1, sizeof(*uc)); + if (!uc) + return -ENOMEM; + if (uc_drv->priv_auto_alloc_size) { + uc->priv = calloc(1, uc_drv->priv_auto_alloc_size); + if (!uc->priv) { + ret = -ENOMEM; + goto fail_mem; + } + } + uc->uc_drv = uc_drv; + INIT_LIST_HEAD(&uc->sibling_node); + INIT_LIST_HEAD(&uc->dev_head); + list_add(&uc->sibling_node, &DM_UCLASS_ROOT_NON_CONST); + + if (uc_drv->init) { + ret = uc_drv->init(uc); + if (ret) + goto fail; + } + + *ucp = uc; + + return 0; +fail: + if (uc_drv->priv_auto_alloc_size) { + free(uc->priv); + uc->priv = NULL; + } + list_del(&uc->sibling_node); +fail_mem: + free(uc); + + return ret; +} + +int uclass_destroy(struct uclass *uc) +{ + struct uclass_driver *uc_drv; + struct udevice *dev, *tmp; + int ret; + + list_for_each_entry_safe(dev, tmp, &uc->dev_head, uclass_node) { + ret = device_remove(dev); + if (ret) + return ret; + ret = device_unbind(dev); + if (ret) + return ret; + } + + uc_drv = uc->uc_drv; + if (uc_drv->destroy) + uc_drv->destroy(uc); + list_del(&uc->sibling_node); + if (uc_drv->priv_auto_alloc_size) + free(uc->priv); + free(uc); + + return 0; +} + +int uclass_get(enum uclass_id id, struct uclass **ucp) +{ + struct uclass *uc; + + *ucp = NULL; + uc = uclass_find(id); + if (!uc) + return uclass_add(id, ucp); + *ucp = uc; + + return 0; +} + +int uclass_find_device(enum uclass_id id, int index, struct udevice **devp) +{ + struct uclass *uc; + struct udevice *dev; + int ret; + + *devp = NULL; + ret = uclass_get(id, &uc); + if (ret) + return ret; + + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + if (!index--) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + +int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq, + bool find_req_seq, struct udevice **devp) +{ + struct uclass *uc; + struct udevice *dev; + int ret; + + *devp = NULL; + debug("%s: %d %d\n", __func__, find_req_seq, seq_or_req_seq); + if (seq_or_req_seq == -1) + return -ENODEV; + ret = uclass_get(id, &uc); + if (ret) + return ret; + + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + debug(" - %d %d\n", dev->req_seq, dev->seq); + if ((find_req_seq ? dev->req_seq : dev->seq) == + seq_or_req_seq) { + *devp = dev; + debug(" - found\n"); + return 0; + } + } + debug(" - not found\n"); + + return -ENODEV; +} + +static int uclass_find_device_by_of_offset(enum uclass_id id, int node, + struct udevice **devp) +{ + struct uclass *uc; + struct udevice *dev; + int ret; + + *devp = NULL; + if (node < 0) + return -ENODEV; + ret = uclass_get(id, &uc); + if (ret) + return ret; + + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + if (dev->of_offset == node) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + +/** + * uclass_get_device_tail() - handle the end of a get_device call + * + * This handles returning an error or probing a device as needed. + * + * @dev: Device that needs to be probed + * @ret: Error to return. If non-zero then the device is not probed + * @devp: Returns the value of 'dev' if there is no error + * @return ret, if non-zero, else the result of the device_probe() call + */ +static int uclass_get_device_tail(struct udevice *dev, int ret, + struct udevice **devp) +{ + if (ret) + return ret; + + ret = device_probe(dev); + if (ret) + return ret; + + *devp = dev; + + return 0; +} + +int uclass_get_device(enum uclass_id id, int index, struct udevice **devp) +{ + struct udevice *dev; + int ret; + + *devp = NULL; + ret = uclass_find_device(id, index, &dev); + return uclass_get_device_tail(dev, ret, devp); +} + +int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp) +{ + struct udevice *dev; + int ret; + + *devp = NULL; + ret = uclass_find_device_by_seq(id, seq, false, &dev); + if (ret == -ENODEV) { + /* + * We didn't find it in probed devices. See if there is one + * that will request this seq if probed. + */ + ret = uclass_find_device_by_seq(id, seq, true, &dev); + } + return uclass_get_device_tail(dev, ret, devp); +} + +int uclass_get_device_by_of_offset(enum uclass_id id, int node, + struct udevice **devp) +{ + struct udevice *dev; + int ret; + + *devp = NULL; + ret = uclass_find_device_by_of_offset(id, node, &dev); + return uclass_get_device_tail(dev, ret, devp); +} + +int uclass_first_device(enum uclass_id id, struct udevice **devp) +{ + struct uclass *uc; + struct udevice *dev; + int ret; + + *devp = NULL; + ret = uclass_get(id, &uc); + if (ret) + return ret; + if (list_empty(&uc->dev_head)) + return 0; + + dev = list_first_entry(&uc->dev_head, struct udevice, uclass_node); + ret = device_probe(dev); + if (ret) + return ret; + *devp = dev; + + return 0; +} + +int uclass_next_device(struct udevice **devp) +{ + struct udevice *dev = *devp; + int ret; + + *devp = NULL; + if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) + return 0; + + dev = list_entry(dev->uclass_node.next, struct udevice, + uclass_node); + ret = device_probe(dev); + if (ret) + return ret; + *devp = dev; + + return 0; +} + +int uclass_bind_device(struct udevice *dev) +{ + struct uclass *uc; + int ret; + + uc = dev->uclass; + list_add_tail(&dev->uclass_node, &uc->dev_head); + + if (dev->parent) { + struct uclass_driver *uc_drv = dev->parent->uclass->uc_drv; + + if (uc_drv->child_post_bind) { + ret = uc_drv->child_post_bind(dev); + if (ret) + goto err; + } + } + if (uc->uc_drv->post_bind) { + ret = uc->uc_drv->post_bind(dev); + if (ret) + goto err; + } + + return 0; +err: + /* There is no need to undo the parent's post_bind call */ + list_del(&dev->uclass_node); + + return ret; +} + +int uclass_unbind_device(struct udevice *dev) +{ + struct uclass *uc; + int ret; + + uc = dev->uclass; + if (uc->uc_drv->pre_unbind) { + ret = uc->uc_drv->pre_unbind(dev); + if (ret) + return ret; + } + + list_del(&dev->uclass_node); + return 0; +} + +int uclass_resolve_seq(struct udevice *dev) +{ + struct udevice *dup; + int seq; + int ret; + + assert(dev->seq == -1); + ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, dev->req_seq, + false, &dup); + if (!ret) { + dm_warn("Device '%s': seq %d is in use by '%s'\n", + dev->name, dev->req_seq, dup->name); + } else if (ret == -ENODEV) { + /* Our requested sequence number is available */ + if (dev->req_seq != -1) + return dev->req_seq; + } else { + return ret; + } + + for (seq = 0; seq < DM_MAX_SEQ; seq++) { + ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, seq, + false, &dup); + if (ret == -ENODEV) + break; + if (ret) + return ret; + } + return seq; +} + +int uclass_pre_probe_child(struct udevice *dev) +{ + struct uclass_driver *uc_drv; + + if (!dev->parent) + return 0; + uc_drv = dev->parent->uclass->uc_drv; + if (uc_drv->child_pre_probe) + return uc_drv->child_pre_probe(dev); + + return 0; +} + +int uclass_post_probe_device(struct udevice *dev) +{ + struct uclass_driver *uc_drv = dev->uclass->uc_drv; + + if (uc_drv->post_probe) + return uc_drv->post_probe(dev); + + return 0; +} + +int uclass_pre_remove_device(struct udevice *dev) +{ + struct uclass_driver *uc_drv; + struct uclass *uc; + int ret; + + uc = dev->uclass; + uc_drv = uc->uc_drv; + if (uc->uc_drv->pre_remove) { + ret = uc->uc_drv->pre_remove(dev); + if (ret) + return ret; + } + if (uc_drv->per_device_auto_alloc_size) { + free(dev->uclass_priv); + dev->uclass_priv = NULL; + } + dev->seq = -1; + + return 0; +} diff --git a/drivers/core/util.c b/drivers/core/util.c new file mode 100644 index 0000000000..e01dd06d28 --- /dev/null +++ b/drivers/core/util.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +void dm_warn(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + vprintf(fmt, args); + va_end(args); +} + +void dm_dbg(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + vprintf(fmt, args); + va_end(args); +} + +int list_count_items(struct list_head *head) +{ + struct list_head *node; + int count = 0; + + list_for_each(node, head) + count++; + + return count; +} diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig new file mode 100644 index 0000000000..bd26a2bcfa --- /dev/null +++ b/drivers/crypto/Kconfig @@ -0,0 +1 @@ +source drivers/crypto/fsl/Kconfig diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 02c53bffd1..fb8c10b38c 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -5,27 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libcrypto.o - -COBJS-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################## +obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o +obj-y += rsa_mod_exp/ +obj-y += fsl/ diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c index acbafde97c..efef491123 100644 --- a/drivers/crypto/ace_sha.c +++ b/drivers/crypto/ace_sha.c @@ -5,11 +5,13 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include -#include -#include -#include #include "ace_sha.h" +#ifdef CONFIG_SHA_HW_ACCEL +#include +#include +#include + /* SHA1 value for the message of zero length */ static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = { 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D, @@ -111,3 +113,72 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1)) debug("ACE was not setup properly or it is faulty\n"); } +#endif /* CONFIG_SHA_HW_ACCEL */ + +#ifdef CONFIG_LIB_HW_RAND +static unsigned int seed_done; + +void srand(unsigned int seed) +{ + struct exynos_ace_sfr *reg = + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); + int i, status; + + /* Seed data */ + for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++) + writel(seed << i, ®->hash_seed[i]); + + /* Wait for seed setup done */ + while (1) { + status = readl(®->hash_status); + if ((status & ACE_HASH_SEEDSETTING_MASK) || + (status & ACE_HASH_PRNGERROR_MASK)) + break; + } + + seed_done = 1; +} + +unsigned int rand(void) +{ + struct exynos_ace_sfr *reg = + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); + int i, status; + unsigned int seed = (unsigned int)&status; + unsigned int ret = 0; + + if (!seed_done) + srand(seed); + + /* Start PRNG */ + writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, ®->hash_control); + + /* Wait for PRNG done */ + while (1) { + status = readl(®->hash_status); + if (status & ACE_HASH_PRNGDONE_MASK) + break; + if (status & ACE_HASH_PRNGERROR_MASK) { + seed_done = 0; + return 0; + } + } + + /* Clear Done IRQ */ + writel(ACE_HASH_PRNGDONE_MASK, ®->hash_status); + + /* Read a PRNG result */ + for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++) + ret += readl(®->hash_prng[i]); + + seed_done = 0; + return ret; +} + +unsigned int rand_r(unsigned int *seedp) +{ + srand(*seedp); + + return rand(); +} +#endif /* CONFIG_LIB_HW_RAND */ diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h index a426d52372..f1097f72dc 100644 --- a/drivers/crypto/ace_sha.h +++ b/drivers/crypto/ace_sha.h @@ -72,9 +72,10 @@ struct exynos_ace_sfr { unsigned char res12[0x30]; unsigned int hash_result[8]; unsigned char res13[0x20]; - unsigned int hash_seed[8]; - unsigned int hash_prng[8]; - unsigned char res14[0x180]; + unsigned int hash_seed[5]; + unsigned char res14[12]; + unsigned int hash_prng[5]; + unsigned char res15[0x18c]; unsigned int pka_sfr[5]; /* base + 0x700 */ }; @@ -291,6 +292,7 @@ struct exynos_ace_sfr { #define ACE_HASH_PRNGERROR_MASK (1 << 7) #define ACE_HASH_PRNGERROR_OFF (0 << 7) #define ACE_HASH_PRNGERROR_ON (1 << 7) +#define ACE_HASH_PRNG_REG_NUM 5 #define ACE_SHA_TYPE_SHA1 1 #define ACE_SHA_TYPE_SHA256 2 diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig new file mode 100644 index 0000000000..86b2f2f7ac --- /dev/null +++ b/drivers/crypto/fsl/Kconfig @@ -0,0 +1,6 @@ +config FSL_CAAM + bool "Freescale Crypto Driver Support" + help + Enables the Freescale's Cryptographic Accelerator and Assurance + Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses + Job Ring as interface to communicate with CAAM. diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile new file mode 100644 index 0000000000..c0cf64229e --- /dev/null +++ b/drivers/crypto/fsl/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# Version 2 as published by the Free Software Foundation. +# + +obj-y += sec.o +obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o +obj-$(CONFIG_CMD_BLOB) += fsl_blob.o +obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h new file mode 100644 index 0000000000..504f2b07d0 --- /dev/null +++ b/drivers/crypto/fsl/desc.h @@ -0,0 +1,651 @@ +/* + * CAAM descriptor composition header + * Definitions to support CAAM descriptor instruction generation + * + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Based on desc.h file in linux drivers/crypto/caam + */ + +#ifndef DESC_H +#define DESC_H + +/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */ +#define MAX_CAAM_DESCSIZE 64 + +/* Block size of any entity covered/uncovered with a KEK/TKEK */ +#define KEK_BLOCKSIZE 16 +/* + * Supported descriptor command types as they show up + * inside a descriptor command word. + */ +#define CMD_SHIFT 27 +#define CMD_MASK 0xf8000000 + +#define CMD_KEY (0x00 << CMD_SHIFT) +#define CMD_SEQ_KEY (0x01 << CMD_SHIFT) +#define CMD_LOAD (0x02 << CMD_SHIFT) +#define CMD_SEQ_LOAD (0x03 << CMD_SHIFT) +#define CMD_FIFO_LOAD (0x04 << CMD_SHIFT) +#define CMD_SEQ_FIFO_LOAD (0x05 << CMD_SHIFT) +#define CMD_STORE (0x0a << CMD_SHIFT) +#define CMD_SEQ_STORE (0x0b << CMD_SHIFT) +#define CMD_FIFO_STORE (0x0c << CMD_SHIFT) +#define CMD_SEQ_FIFO_STORE (0x0d << CMD_SHIFT) +#define CMD_MOVE_LEN (0x0e << CMD_SHIFT) +#define CMD_MOVE (0x0f << CMD_SHIFT) +#define CMD_OPERATION (0x10 << CMD_SHIFT) +#define CMD_SIGNATURE (0x12 << CMD_SHIFT) +#define CMD_JUMP (0x14 << CMD_SHIFT) +#define CMD_MATH (0x15 << CMD_SHIFT) +#define CMD_DESC_HDR (0x16 << CMD_SHIFT) +#define CMD_SHARED_DESC_HDR (0x17 << CMD_SHIFT) +#define CMD_SEQ_IN_PTR (0x1e << CMD_SHIFT) +#define CMD_SEQ_OUT_PTR (0x1f << CMD_SHIFT) + +/* General-purpose class selector for all commands */ +#define CLASS_SHIFT 25 +#define CLASS_MASK (0x03 << CLASS_SHIFT) + +#define CLASS_NONE (0x00 << CLASS_SHIFT) +#define CLASS_1 (0x01 << CLASS_SHIFT) +#define CLASS_2 (0x02 << CLASS_SHIFT) +#define CLASS_BOTH (0x03 << CLASS_SHIFT) + +/* + * Descriptor header command constructs + * Covers shared, job, and trusted descriptor headers + */ + +/* + * Do Not Run - marks a descriptor inexecutable if there was + * a preceding error somewhere + */ +#define HDR_DNR 0x01000000 + +/* + * ONE - should always be set. Combination of ONE (always + * set) and ZRO (always clear) forms an endianness sanity check + */ +#define HDR_ONE 0x00800000 +#define HDR_ZRO 0x00008000 + +/* Start Index or SharedDesc Length */ +#define HDR_START_IDX_MASK 0x3f +#define HDR_START_IDX_SHIFT 16 + +/* If shared descriptor header, 6-bit length */ +#define HDR_DESCLEN_SHR_MASK 0x3f + +/* If non-shared header, 7-bit length */ +#define HDR_DESCLEN_MASK 0x7f + +/* This is a TrustedDesc (if not SharedDesc) */ +#define HDR_TRUSTED 0x00004000 + +/* Make into TrustedDesc (if not SharedDesc) */ +#define HDR_MAKE_TRUSTED 0x00002000 + +/* Save context if self-shared (if SharedDesc) */ +#define HDR_SAVECTX 0x00001000 + +/* Next item points to SharedDesc */ +#define HDR_SHARED 0x00001000 + +/* + * Reverse Execution Order - execute JobDesc first, then + * execute SharedDesc (normally SharedDesc goes first). + */ +#define HDR_REVERSE 0x00000800 + +/* Propogate DNR property to SharedDesc */ +#define HDR_PROP_DNR 0x00000800 + +/* JobDesc/SharedDesc share property */ +#define HDR_SD_SHARE_MASK 0x03 +#define HDR_SD_SHARE_SHIFT 8 +#define HDR_JD_SHARE_MASK 0x07 +#define HDR_JD_SHARE_SHIFT 8 + +#define HDR_SHARE_NEVER (0x00 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_WAIT (0x01 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_SERIAL (0x02 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_ALWAYS (0x03 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_DEFER (0x04 << HDR_SD_SHARE_SHIFT) + +/* JobDesc/SharedDesc descriptor length */ +#define HDR_JD_LENGTH_MASK 0x7f +#define HDR_SD_LENGTH_MASK 0x3f + +/* + * KEY/SEQ_KEY Command Constructs + */ + +/* Key Destination Class: 01 = Class 1, 02 - Class 2 */ +#define KEY_DEST_CLASS_SHIFT 25 /* use CLASS_1 or CLASS_2 */ +#define KEY_DEST_CLASS_MASK (0x03 << KEY_DEST_CLASS_SHIFT) + +/* Scatter-Gather Table/Variable Length Field */ +#define KEY_SGF 0x01000000 +#define KEY_VLF 0x01000000 + +/* Immediate - Key follows command in the descriptor */ +#define KEY_IMM 0x00800000 + +/* + * Encrypted - Key is encrypted either with the KEK, or + * with the TDKEK if TK is set + */ +#define KEY_ENC 0x00400000 + +/* + * No Write Back - Do not allow key to be FIFO STOREd + */ +#define KEY_NWB 0x00200000 + +/* + * Enhanced Encryption of Key + */ +#define KEY_EKT 0x00100000 + +/* + * Encrypted with Trusted Key + */ +#define KEY_TK 0x00008000 + +/* + * KDEST - Key Destination: 0 - class key register, + * 1 - PKHA 'e', 2 - AFHA Sbox, 3 - MDHA split-key + */ +#define KEY_DEST_SHIFT 16 +#define KEY_DEST_MASK (0x03 << KEY_DEST_SHIFT) + +#define KEY_DEST_CLASS_REG (0x00 << KEY_DEST_SHIFT) +#define KEY_DEST_PKHA_E (0x01 << KEY_DEST_SHIFT) +#define KEY_DEST_AFHA_SBOX (0x02 << KEY_DEST_SHIFT) +#define KEY_DEST_MDHA_SPLIT (0x03 << KEY_DEST_SHIFT) + +/* Length in bytes */ +#define KEY_LENGTH_MASK 0x000003ff + +/* + * LOAD/SEQ_LOAD/STORE/SEQ_STORE Command Constructs + */ + +/* + * Load/Store Destination: 0 = class independent CCB, + * 1 = class 1 CCB, 2 = class 2 CCB, 3 = DECO + */ +#define LDST_CLASS_SHIFT 25 +#define LDST_CLASS_MASK (0x03 << LDST_CLASS_SHIFT) +#define LDST_CLASS_IND_CCB (0x00 << LDST_CLASS_SHIFT) +#define LDST_CLASS_1_CCB (0x01 << LDST_CLASS_SHIFT) +#define LDST_CLASS_2_CCB (0x02 << LDST_CLASS_SHIFT) +#define LDST_CLASS_DECO (0x03 << LDST_CLASS_SHIFT) + +/* Scatter-Gather Table/Variable Length Field */ +#define LDST_SGF 0x01000000 +#define LDST_VLF LDST_SGF + +/* Immediate - Key follows this command in descriptor */ +#define LDST_IMM_MASK 1 +#define LDST_IMM_SHIFT 23 +#define LDST_IMM (LDST_IMM_MASK << LDST_IMM_SHIFT) + +/* SRC/DST - Destination for LOAD, Source for STORE */ +#define LDST_SRCDST_SHIFT 16 +#define LDST_SRCDST_MASK (0x7f << LDST_SRCDST_SHIFT) + +#define LDST_SRCDST_BYTE_CONTEXT (0x20 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_KEY (0x40 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_INFIFO (0x7c << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_OUTFIFO (0x7e << LDST_SRCDST_SHIFT) + +#define LDST_SRCDST_WORD_MODE_REG (0x00 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_KEYSZ_REG (0x01 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DATASZ_REG (0x02 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_ICVSZ_REG (0x03 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CHACTRL (0x06 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECOCTRL (0x06 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_IRQCTRL (0x07 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_PCLOVRD (0x07 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLRW (0x08 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH0 (0x08 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_STAT (0x09 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH1 (0x09 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH2 (0x0a << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_AAD_SZ (0x0b << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH3 (0x0b << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLASS1_ICV_SZ (0x0c << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_ALTDS_CLASS1 (0x0f << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_A_SZ (0x10 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_B_SZ (0x11 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_N_SZ (0x12 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_E_SZ (0x13 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLASS_CTX (0x20 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF (0x40 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_JOB (0x41 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_SHARED (0x42 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_JOB_WE (0x45 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_SHARED_WE (0x46 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_INFO_FIFO (0x7a << LDST_SRCDST_SHIFT) + +/* Offset in source/destination */ +#define LDST_OFFSET_SHIFT 8 +#define LDST_OFFSET_MASK (0xff << LDST_OFFSET_SHIFT) + +/* LDOFF definitions used when DST = LDST_SRCDST_WORD_DECOCTRL */ +/* These could also be shifted by LDST_OFFSET_SHIFT - this reads better */ +#define LDOFF_CHG_SHARE_SHIFT 0 +#define LDOFF_CHG_SHARE_MASK (0x3 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_NEVER (0x1 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_OK_PROP (0x2 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_OK_NO_PROP (0x3 << LDOFF_CHG_SHARE_SHIFT) + +#define LDOFF_ENABLE_AUTO_NFIFO (1 << 2) +#define LDOFF_DISABLE_AUTO_NFIFO (1 << 3) + +#define LDOFF_CHG_NONSEQLIODN_SHIFT 4 +#define LDOFF_CHG_NONSEQLIODN_MASK (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_SEQ (0x1 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_NON_SEQ (0x2 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_TRUSTED (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT) + +#define LDOFF_CHG_SEQLIODN_SHIFT 6 +#define LDOFF_CHG_SEQLIODN_MASK (0x3 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_SEQ (0x1 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_NON_SEQ (0x2 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_TRUSTED (0x3 << LDOFF_CHG_SEQLIODN_SHIFT) + +/* Data length in bytes */ +#define LDST_LEN_SHIFT 0 +#define LDST_LEN_MASK (0xff << LDST_LEN_SHIFT) + +/* Special Length definitions when dst=deco-ctrl */ +#define LDLEN_ENABLE_OSL_COUNT (1 << 7) +#define LDLEN_RST_CHA_OFIFO_PTR (1 << 6) +#define LDLEN_RST_OFIFO (1 << 5) +#define LDLEN_SET_OFIFO_OFF_VALID (1 << 4) +#define LDLEN_SET_OFIFO_OFF_RSVD (1 << 3) +#define LDLEN_SET_OFIFO_OFFSET_SHIFT 0 +#define LDLEN_SET_OFIFO_OFFSET_MASK (3 << LDLEN_SET_OFIFO_OFFSET_SHIFT) + +/* + * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE + * Command Constructs + */ + +/* + * Load Destination: 0 = skip (SEQ_FIFO_LOAD only), + * 1 = Load for Class1, 2 = Load for Class2, 3 = Load both + * Store Source: 0 = normal, 1 = Class1key, 2 = Class2key + */ +#define FIFOLD_CLASS_SHIFT 25 +#define FIFOLD_CLASS_MASK (0x03 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_SKIP (0x00 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_CLASS1 (0x01 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_CLASS2 (0x02 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_BOTH (0x03 << FIFOLD_CLASS_SHIFT) + +#define FIFOST_CLASS_SHIFT 25 +#define FIFOST_CLASS_MASK (0x03 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_NORMAL (0x00 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_CLASS1KEY (0x01 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_CLASS2KEY (0x02 << FIFOST_CLASS_SHIFT) + +/* + * Scatter-Gather Table/Variable Length Field + * If set for FIFO_LOAD, refers to a SG table. Within + * SEQ_FIFO_LOAD, is variable input sequence + */ +#define FIFOLDST_SGF_SHIFT 24 +#define FIFOLDST_SGF_MASK (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_VLF_MASK (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_SGF (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_VLF (1 << FIFOLDST_SGF_SHIFT) + +/* Immediate - Data follows command in descriptor */ +#define FIFOLD_IMM_SHIFT 23 +#define FIFOLD_IMM_MASK (1 << FIFOLD_IMM_SHIFT) +#define FIFOLD_IMM (1 << FIFOLD_IMM_SHIFT) + +/* Continue - Not the last FIFO store to come */ +#define FIFOST_CONT_SHIFT 23 +#define FIFOST_CONT_MASK (1 << FIFOST_CONT_SHIFT) + +/* + * Extended Length - use 32-bit extended length that + * follows the pointer field. Illegal with IMM set + */ +#define FIFOLDST_EXT_SHIFT 22 +#define FIFOLDST_EXT_MASK (1 << FIFOLDST_EXT_SHIFT) +#define FIFOLDST_EXT (1 << FIFOLDST_EXT_SHIFT) + +/* Input data type.*/ +#define FIFOLD_TYPE_SHIFT 16 +#define FIFOLD_CONT_TYPE_SHIFT 19 /* shift past last-flush bits */ +#define FIFOLD_TYPE_MASK (0x3f << FIFOLD_TYPE_SHIFT) + +/* PK types */ +#define FIFOLD_TYPE_PK (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_MASK (0x30 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_TYPEMASK (0x0f << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A0 (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A1 (0x01 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A2 (0x02 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A3 (0x03 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B0 (0x04 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B1 (0x05 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B2 (0x06 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B3 (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_N (0x08 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A (0x0c << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B (0x0d << FIFOLD_TYPE_SHIFT) + +/* Other types. Need to OR in last/flush bits as desired */ +#define FIFOLD_TYPE_MSG_MASK (0x38 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_MSG (0x10 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_MSG1OUT2 (0x18 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_IV (0x20 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_BITDATA (0x28 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_AAD (0x30 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_ICV (0x38 << FIFOLD_TYPE_SHIFT) + +/* Last/Flush bits for use with "other" types above */ +#define FIFOLD_TYPE_ACT_MASK (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_NOACTION (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_FLUSH1 (0x01 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST1 (0x02 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2FLUSH (0x03 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2 (0x04 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2FLUSH1 (0x05 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LASTBOTH (0x06 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LASTBOTHFL (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_NOINFOFIFO (0x0F << FIFOLD_TYPE_SHIFT) + +#define FIFOLDST_LEN_MASK 0xffff +#define FIFOLDST_EXT_LEN_MASK 0xffffffff + +/* Output data types */ +#define FIFOST_TYPE_SHIFT 16 +#define FIFOST_TYPE_MASK (0x3f << FIFOST_TYPE_SHIFT) + +#define FIFOST_TYPE_PKHA_A0 (0x00 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A1 (0x01 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A2 (0x02 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A3 (0x03 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B0 (0x04 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B1 (0x05 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B2 (0x06 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B3 (0x07 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_JKEK (0x10 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_E_TKEK (0x23 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_KEK (0x24 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_TKEK (0x25 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SPLIT_KEK (0x26 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SPLIT_TKEK (0x27 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_OUTFIFO_KEK (0x28 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_OUTFIFO_TKEK (0x29 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_MESSAGE_DATA (0x30 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_RNGSTORE (0x34 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_RNGFIFO (0x35 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SKIP (0x3f << FIFOST_TYPE_SHIFT) + +/* + * OPERATION Command Constructs + */ + +/* Operation type selectors - OP TYPE */ +#define OP_TYPE_SHIFT 24 +#define OP_TYPE_MASK (0x07 << OP_TYPE_SHIFT) + +#define OP_TYPE_UNI_PROTOCOL (0x00 << OP_TYPE_SHIFT) +#define OP_TYPE_PK (0x01 << OP_TYPE_SHIFT) +#define OP_TYPE_CLASS1_ALG (0x02 << OP_TYPE_SHIFT) +#define OP_TYPE_CLASS2_ALG (0x04 << OP_TYPE_SHIFT) +#define OP_TYPE_DECAP_PROTOCOL (0x06 << OP_TYPE_SHIFT) +#define OP_TYPE_ENCAP_PROTOCOL (0x07 << OP_TYPE_SHIFT) + +/* ProtocolID selectors - PROTID */ +#define OP_PCLID_SHIFT 16 +#define OP_PCLID_MASK (0xff << 16) + +/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */ +#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT) +#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT) +#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT) + +/* For non-protocol/alg-only op commands */ +#define OP_ALG_TYPE_SHIFT 24 +#define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) +#define OP_ALG_TYPE_CLASS1 2 +#define OP_ALG_TYPE_CLASS2 4 + +#define OP_ALG_ALGSEL_SHIFT 16 +#define OP_ALG_ALGSEL_MASK (0xff << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SUBMASK (0x0f << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_AES (0x10 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_DES (0x20 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_3DES (0x21 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_ARC4 (0x30 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_MD5 (0x40 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA1 (0x41 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA224 (0x42 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA256 (0x43 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA384 (0x44 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA512 (0x45 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_RNG (0x50 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW (0x60 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW_F8 (0x60 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_KASUMI (0x70 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_CRC (0x90 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW_F9 (0xA0 << OP_ALG_ALGSEL_SHIFT) + +#define OP_ALG_AAI_SHIFT 4 +#define OP_ALG_AAI_MASK (0x1ff << OP_ALG_AAI_SHIFT) + +/* randomizer AAI set */ +#define OP_ALG_AAI_RNG (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG_NZB (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG_OBP (0x20 << OP_ALG_AAI_SHIFT) + +/* RNG4 AAI set */ +#define OP_ALG_AAI_RNG4_SH_0 (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_SH_1 (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_PS (0x40 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_AI (0x80 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_SK (0x100 << OP_ALG_AAI_SHIFT) + +/* hmac/smac AAI set */ +#define OP_ALG_AAI_HASH (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_HMAC (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_SMAC (0x02 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_HMAC_PRECOMP (0x04 << OP_ALG_AAI_SHIFT) + +#define OP_ALG_AS_SHIFT 2 +#define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_UPDATE (0 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_INIT (1 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_FINALIZE (2 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_INITFINAL (3 << OP_ALG_AS_SHIFT) + +#define OP_ALG_ICV_SHIFT 1 +#define OP_ALG_ICV_MASK (1 << OP_ALG_ICV_SHIFT) +#define OP_ALG_ICV_OFF (0 << OP_ALG_ICV_SHIFT) +#define OP_ALG_ICV_ON (1 << OP_ALG_ICV_SHIFT) + +#define OP_ALG_DIR_SHIFT 0 +#define OP_ALG_DIR_MASK 1 +#define OP_ALG_DECRYPT 0 +#define OP_ALG_ENCRYPT 1 + +/* PKHA algorithm type set */ +#define OP_ALG_PK 0x00800000 +#define OP_ALG_PK_FUN_MASK 0x3f /* clrmem, modmath, or cpymem */ + +/* PKHA mode modular-arithmetic functions */ +#define OP_ALG_PKMODE_MOD_EXPO 0x006 + +/* + * SEQ_IN_PTR Command Constructs + */ + +/* Release Buffers */ +#define SQIN_RBS 0x04000000 + +/* Sequence pointer is really a descriptor */ +#define SQIN_INL 0x02000000 + +/* Sequence pointer is a scatter-gather table */ +#define SQIN_SGF 0x01000000 + +/* Appends to a previous pointer */ +#define SQIN_PRE 0x00800000 + +/* Use extended length following pointer */ +#define SQIN_EXT 0x00400000 + +/* Restore sequence with pointer/length */ +#define SQIN_RTO 0x00200000 + +/* Replace job descriptor */ +#define SQIN_RJD 0x00100000 + +#define SQIN_LEN_SHIFT 0 +#define SQIN_LEN_MASK (0xffff << SQIN_LEN_SHIFT) + +/* + * SEQ_OUT_PTR Command Constructs + */ + +/* Sequence pointer is a scatter-gather table */ +#define SQOUT_SGF 0x01000000 + +/* Appends to a previous pointer */ +#define SQOUT_PRE SQIN_PRE + +/* Restore sequence with pointer/length */ +#define SQOUT_RTO SQIN_RTO + +/* Use extended length following pointer */ +#define SQOUT_EXT 0x00400000 + +#define SQOUT_LEN_SHIFT 0 +#define SQOUT_LEN_MASK (0xffff << SQOUT_LEN_SHIFT) + +/* + * MOVE Command Constructs + */ + +#define MOVE_AUX_SHIFT 25 +#define MOVE_AUX_MASK (3 << MOVE_AUX_SHIFT) +#define MOVE_AUX_MS (2 << MOVE_AUX_SHIFT) +#define MOVE_AUX_LS (1 << MOVE_AUX_SHIFT) + +#define MOVE_WAITCOMP_SHIFT 24 +#define MOVE_WAITCOMP_MASK (1 << MOVE_WAITCOMP_SHIFT) +#define MOVE_WAITCOMP (1 << MOVE_WAITCOMP_SHIFT) + +#define MOVE_SRC_SHIFT 20 +#define MOVE_SRC_MASK (0x0f << MOVE_SRC_SHIFT) +#define MOVE_SRC_CLASS1CTX (0x00 << MOVE_SRC_SHIFT) +#define MOVE_SRC_CLASS2CTX (0x01 << MOVE_SRC_SHIFT) +#define MOVE_SRC_OUTFIFO (0x02 << MOVE_SRC_SHIFT) +#define MOVE_SRC_DESCBUF (0x03 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH0 (0x04 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH1 (0x05 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH2 (0x06 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH3 (0x07 << MOVE_SRC_SHIFT) +#define MOVE_SRC_INFIFO (0x08 << MOVE_SRC_SHIFT) +#define MOVE_SRC_INFIFO_CL (0x09 << MOVE_SRC_SHIFT) + +#define MOVE_DEST_SHIFT 16 +#define MOVE_DEST_MASK (0x0f << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1CTX (0x00 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2CTX (0x01 << MOVE_DEST_SHIFT) +#define MOVE_DEST_OUTFIFO (0x02 << MOVE_DEST_SHIFT) +#define MOVE_DEST_DESCBUF (0x03 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH0 (0x04 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH1 (0x05 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH2 (0x06 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH3 (0x07 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1INFIFO (0x08 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2INFIFO (0x09 << MOVE_DEST_SHIFT) +#define MOVE_DEST_INFIFO_NOINFO (0x0a << MOVE_DEST_SHIFT) +#define MOVE_DEST_PK_A (0x0c << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1KEY (0x0d << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2KEY (0x0e << MOVE_DEST_SHIFT) + +#define MOVE_OFFSET_SHIFT 8 +#define MOVE_OFFSET_MASK (0xff << MOVE_OFFSET_SHIFT) + +#define MOVE_LEN_SHIFT 0 +#define MOVE_LEN_MASK (0xff << MOVE_LEN_SHIFT) + +#define MOVELEN_MRSEL_SHIFT 0 +#define MOVELEN_MRSEL_MASK (0x3 << MOVE_LEN_SHIFT) + +/* + * JUMP Command Constructs + */ + +#define JUMP_CLASS_SHIFT 25 +#define JUMP_CLASS_MASK (3 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_NONE 0 +#define JUMP_CLASS_CLASS1 (1 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_CLASS2 (2 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_BOTH (3 << JUMP_CLASS_SHIFT) + +#define JUMP_JSL_SHIFT 24 +#define JUMP_JSL_MASK (1 << JUMP_JSL_SHIFT) +#define JUMP_JSL (1 << JUMP_JSL_SHIFT) + +#define JUMP_TYPE_SHIFT 22 +#define JUMP_TYPE_MASK (0x03 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_LOCAL (0x00 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_NONLOCAL (0x01 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_HALT (0x02 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_HALT_USER (0x03 << JUMP_TYPE_SHIFT) + +#define JUMP_TEST_SHIFT 16 +#define JUMP_TEST_MASK (0x03 << JUMP_TEST_SHIFT) +#define JUMP_TEST_ALL (0x00 << JUMP_TEST_SHIFT) +#define JUMP_TEST_INVALL (0x01 << JUMP_TEST_SHIFT) +#define JUMP_TEST_ANY (0x02 << JUMP_TEST_SHIFT) +#define JUMP_TEST_INVANY (0x03 << JUMP_TEST_SHIFT) + +/* Condition codes. JSL bit is factored in */ +#define JUMP_COND_SHIFT 8 +#define JUMP_COND_MASK (0x100ff << JUMP_COND_SHIFT) +#define JUMP_COND_PK_0 (0x80 << JUMP_COND_SHIFT) +#define JUMP_COND_PK_GCD_1 (0x40 << JUMP_COND_SHIFT) +#define JUMP_COND_PK_PRIME (0x20 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_N (0x08 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_Z (0x04 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_C (0x02 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_NV (0x01 << JUMP_COND_SHIFT) + +#define JUMP_COND_JRP ((0x80 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_SHRD ((0x40 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_SELF ((0x20 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_CALM ((0x10 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NIP ((0x08 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NIFP ((0x04 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NOP ((0x02 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NCP ((0x01 << JUMP_COND_SHIFT) | JUMP_JSL) + +#define JUMP_OFFSET_SHIFT 0 +#define JUMP_OFFSET_MASK (0xff << JUMP_OFFSET_SHIFT) + +#define OP_ALG_RNG4_SHIFT 4 +#define OP_ALG_RNG4_MAS (0x1f3 << OP_ALG_RNG4_SHIFT) +#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT) + +#endif /* DESC_H */ diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h new file mode 100644 index 0000000000..f9cae9144a --- /dev/null +++ b/drivers/crypto/fsl/desc_constr.h @@ -0,0 +1,280 @@ +/* + * caam descriptor construction helper functions + * + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Based on desc_constr.h file in linux drivers/crypto/caam + */ + +#include +#include "desc.h" + +#define IMMEDIATE (1 << 23) +#define CAAM_CMD_SZ sizeof(u32) +#define CAAM_PTR_SZ sizeof(dma_addr_t) +#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) +#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) + +#ifdef DEBUG +#define PRINT_POS do { printf("%02d: %s\n", desc_len(desc),\ + &__func__[sizeof("append")]); \ + } while (0) +#else +#define PRINT_POS +#endif + +#define SET_OK_NO_PROP_ERRORS (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_CHG_SHARE_OK_NO_PROP << \ + LDST_OFFSET_SHIFT)) +#define DISABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_DISABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) +#define ENABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) + +static inline int desc_len(u32 *desc) +{ + return *desc & HDR_DESCLEN_MASK; +} + +static inline int desc_bytes(void *desc) +{ + return desc_len(desc) * CAAM_CMD_SZ; +} + +static inline u32 *desc_end(u32 *desc) +{ + return desc + desc_len(desc); +} + +static inline void init_desc(u32 *desc, u32 options) +{ + *desc = (options | HDR_ONE) + 1; +} + +static inline void init_job_desc(u32 *desc, u32 options) +{ + init_desc(desc, CMD_DESC_HDR | options); +} + +static inline void append_ptr(u32 *desc, dma_addr_t ptr) +{ + dma_addr_t *offset = (dma_addr_t *)desc_end(desc); + + *offset = ptr; + + (*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ; +} + +static inline void append_data(u32 *desc, void *data, int len) +{ + u32 *offset = desc_end(desc); + + if (len) /* avoid sparse warning: memcpy with byte count of 0 */ + memcpy(offset, data, len); + + (*desc) += (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ; +} + +static inline void append_cmd(u32 *desc, u32 command) +{ + u32 *cmd = desc_end(desc); + + *cmd = command; + + (*desc)++; +} + +#define append_u32 append_cmd + +static inline void append_u64(u32 *desc, u64 data) +{ + u32 *offset = desc_end(desc); + + *offset = upper_32_bits(data); + *(++offset) = lower_32_bits(data); + + (*desc) += 2; +} + +/* Write command without affecting header, and return pointer to next word */ +static inline u32 *write_cmd(u32 *desc, u32 command) +{ + *desc = command; + + return desc + 1; +} + +static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, + u32 command) +{ + append_cmd(desc, command | len); + append_ptr(desc, ptr); +} + +/* Write length after pointer, rather than inside command */ +static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr, + unsigned int len, u32 command) +{ + append_cmd(desc, command); + if (!(command & (SQIN_RTO | SQIN_PRE))) + append_ptr(desc, ptr); + append_cmd(desc, len); +} + +static inline void append_cmd_data(u32 *desc, void *data, int len, + u32 command) +{ + append_cmd(desc, command | IMMEDIATE | len); + append_data(desc, data, len); +} + +#define APPEND_CMD_RET(cmd, op) \ +static inline u32 *append_##cmd(u32 *desc, u32 options) \ +{ \ + u32 *cmd = desc_end(desc); \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | options); \ + return cmd; \ +} +APPEND_CMD_RET(jump, JUMP) +APPEND_CMD_RET(move, MOVE) + +static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd) +{ + *jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc)); +} + +static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd) +{ + *move_cmd &= ~MOVE_OFFSET_MASK; + *move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) & + MOVE_OFFSET_MASK); +} + +#define APPEND_CMD(cmd, op) \ +static inline void append_##cmd(u32 *desc, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | options); \ +} +APPEND_CMD(operation, OPERATION) + +#define APPEND_CMD_LEN(cmd, op) \ +static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | len | options); \ +} +APPEND_CMD_LEN(seq_store, SEQ_STORE) +APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) +APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) + +#define APPEND_CMD_PTR(cmd, op) \ +static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \ + u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_ptr(desc, ptr, len, CMD_##op | options); \ +} +APPEND_CMD_PTR(key, KEY) +APPEND_CMD_PTR(load, LOAD) +APPEND_CMD_PTR(fifo_load, FIFO_LOAD) +APPEND_CMD_PTR(fifo_store, FIFO_STORE) + +static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, + u32 options) +{ + u32 cmd_src; + + cmd_src = options & LDST_SRCDST_MASK; + + append_cmd(desc, CMD_STORE | options | len); + + /* The following options do not require pointer */ + if (!(cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED || + cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB || + cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB_WE || + cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED_WE)) + append_ptr(desc, ptr); +} + +#define APPEND_SEQ_PTR_INTLEN(cmd, op) \ +static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \ + unsigned int len, \ + u32 options) \ +{ \ + PRINT_POS; \ + if (options & (SQIN_RTO | SQIN_PRE)) \ + append_cmd(desc, CMD_SEQ_##op##_PTR | len | options); \ + else \ + append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \ +} +APPEND_SEQ_PTR_INTLEN(in, IN) +APPEND_SEQ_PTR_INTLEN(out, OUT) + +#define APPEND_CMD_PTR_TO_IMM(cmd, op) \ +static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_data(desc, data, len, CMD_##op | options); \ +} +APPEND_CMD_PTR_TO_IMM(load, LOAD); +APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD); + +#define APPEND_CMD_PTR_EXTLEN(cmd, op) \ +static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_ptr_extlen(desc, ptr, len, CMD_##op | SQIN_EXT | options); \ +} +APPEND_CMD_PTR_EXTLEN(seq_in_ptr, SEQ_IN_PTR) +APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) + +/* + * Determine whether to store length internally or externally depending on + * the size of its type + */ +#define APPEND_CMD_PTR_LEN(cmd, op, type) \ +static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \ + type len, u32 options) \ +{ \ + PRINT_POS; \ + if (sizeof(type) > sizeof(u16)) \ + append_##cmd##_extlen(desc, ptr, len, options); \ + else \ + append_##cmd##_intlen(desc, ptr, len, options); \ +} +APPEND_CMD_PTR_LEN(seq_in_ptr, SEQ_IN_PTR, u32) +APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32) + +/* + * 2nd variant for commands whose specified immediate length differs + * from length of immediate data provided, e.g., split keys + */ +#define APPEND_CMD_PTR_TO_IMM2(cmd, op) \ +static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ + unsigned int data_len, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | IMMEDIATE | len | options); \ + append_data(desc, data, data_len); \ +} +APPEND_CMD_PTR_TO_IMM2(key, KEY); + +#define APPEND_CMD_RAW_IMM(cmd, op, type) \ +static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \ + u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | IMMEDIATE | options | sizeof(type)); \ + append_cmd(desc, immediate); \ +} +APPEND_CMD_RAW_IMM(load, LOAD, u32); diff --git a/drivers/crypto/fsl/error.c b/drivers/crypto/fsl/error.c new file mode 100644 index 0000000000..28cdcdd4cc --- /dev/null +++ b/drivers/crypto/fsl/error.c @@ -0,0 +1,258 @@ +/* + * CAAM Error Reporting + * + * Copyright 2009-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived from error.c file in linux drivers/crypto/caam + */ + +#include +#include +#include "desc.h" +#include "jr.h" + +#define CAAM_ERROR_STR_MAX 302 + +#define JRSTA_SSRC_SHIFT 28 +#define JRSTA_CCBERR_CHAID_MASK 0x00f0 +#define JRSTA_CCBERR_CHAID_SHIFT 4 +#define JRSTA_CCBERR_ERRID_MASK 0x000 +#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) + +#define JRSTA_DECOERR_JUMP 0x08000000 +#define JRSTA_DECOERR_INDEX_SHIFT 8 +#define JRSTA_DECOERR_INDEX_MASK 0xff00 +#define JRSTA_DECOERR_ERROR_MASK 0x00ff + + +static const struct { + u8 value; + const char *error_text; +} desc_error_list[] = { + { 0x00, "No error." }, + { 0x01, "SGT Length Error. The descriptor is trying to read" \ + " more data than is contained in the SGT table." }, + { 0x02, "SGT Null Entry Error." }, + { 0x03, "Job Ring Control Error. Bad value in Job Ring Control reg." }, + { 0x04, "Invalid Descriptor Command." }, + { 0x05, "Reserved." }, + { 0x06, "Invalid KEY Command" }, + { 0x07, "Invalid LOAD Command" }, + { 0x08, "Invalid STORE Command" }, + { 0x09, "Invalid OPERATION Command" }, + { 0x0A, "Invalid FIFO LOAD Command" }, + { 0x0B, "Invalid FIFO STORE Command" }, + { 0x0C, "Invalid MOVE/MOVE_LEN Command" }, + { 0x0D, "Invalid JUMP Command" }, + { 0x0E, "Invalid MATH Command" }, + { 0x0F, "Invalid SIGNATURE Command" }, + { 0x10, "Invalid Sequence Command" }, + { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."}, + { 0x12, "Shared Descriptor Header Error" }, + { 0x13, "Header Error. Invalid length or parity, or other problems." }, + { 0x14, "Burster Error. Burster has gotten to an illegal state" }, + { 0x15, "Context Register Length Error" }, + { 0x16, "DMA Error" }, + { 0x17, "Reserved." }, + { 0x1A, "Job failed due to JR reset" }, + { 0x1B, "Job failed due to Fail Mode" }, + { 0x1C, "DECO Watchdog timer timeout error" }, + { 0x1D, "DECO tried to copy a key from another DECO but" \ + " the other DECO's Key Registers were locked" }, + { 0x1E, "DECO attempted to copy data from a DECO" \ + "that had an unmasked Descriptor error" }, + { 0x1F, "LIODN error" }, + { 0x20, "DECO has completed a reset initiated via the DRR register" }, + { 0x21, "Nonce error" }, + { 0x22, "Meta data is too large (> 511 bytes) for TLS decap" }, + { 0x23, "Read Input Frame error" }, + { 0x24, "JDKEK, TDKEK or TDSK not loaded error" }, + { 0x80, "DNR (do not run) error" }, + { 0x81, "undefined protocol command" }, + { 0x82, "invalid setting in PDB" }, + { 0x83, "Anti-replay LATE error" }, + { 0x84, "Anti-replay REPLAY error" }, + { 0x85, "Sequence number overflow" }, + { 0x86, "Sigver invalid signature" }, + { 0x87, "DSA Sign Illegal test descriptor" }, + { 0x88, "Protocol Format Error" }, + { 0x89, "Protocol Size Error" }, + { 0xC1, "Blob Command error: Undefined mode" }, + { 0xC2, "Blob Command error: Secure Memory Blob mode error" }, + { 0xC4, "Blob Command error: Black Blob key or input size error" }, + { 0xC5, "Blob Command error: Invalid key destination" }, + { 0xC8, "Blob Command error: Trusted/Secure mode error" }, + { 0xF0, "IPsec TTL or hop limit field is 0, or was decremented to 0" }, + { 0xF1, "3GPP HFN matches or exceeds the Threshold" }, +}; + +static const char * const cha_id_list[] = { + "", + "AES", + "DES", + "ARC4", + "MDHA", + "RNG", + "SNOW f8", + "Kasumi f8/9", + "PKHA", + "CRCA", + "SNOW f9", + "ZUCE", + "ZUCA", +}; + +static const char * const err_id_list[] = { + "No error.", + "Mode error.", + "Data size error.", + "Key size error.", + "PKHA A memory size error.", + "PKHA B memory size error.", + "Data arrived out of sequence error.", + "PKHA divide-by-zero error.", + "PKHA modulus even error.", + "DES key parity error.", + "ICV check failed.", + "Hardware error.", + "Unsupported CCM AAD size.", + "Class 1 CHA is not reset", + "Invalid CHA combination was selected", + "Invalid CHA selected.", +}; + +static const char * const rng_err_id_list[] = { + "", + "", + "", + "Instantiate", + "Not instantiated", + "Test instantiate", + "Prediction resistance", + "Prediction resistance and test request", + "Uninstantiate", + "Secure key generation", +}; + +static void report_ccb_status(const u32 status, + const char *error) +{ + u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >> + JRSTA_CCBERR_CHAID_SHIFT; + u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; + u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> + JRSTA_DECOERR_INDEX_SHIFT; + char *idx_str; + const char *cha_str = "unidentified cha_id value 0x"; + char cha_err_code[3] = { 0 }; + const char *err_str = "unidentified err_id value 0x"; + char err_err_code[3] = { 0 }; + + if (status & JRSTA_DECOERR_JUMP) + idx_str = "jump tgt desc idx"; + else + idx_str = "desc idx"; + + if (cha_id < ARRAY_SIZE(cha_id_list)) + cha_str = cha_id_list[cha_id]; + else + snprintf(cha_err_code, sizeof(cha_err_code), "%02x", cha_id); + + if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG && + err_id < ARRAY_SIZE(rng_err_id_list) && + strlen(rng_err_id_list[err_id])) { + /* RNG-only error */ + err_str = rng_err_id_list[err_id]; + } else if (err_id < ARRAY_SIZE(err_id_list)) { + err_str = err_id_list[err_id]; + } else { + snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id); + } + + debug("%08x: %s: %s %d: %s%s: %s%s\n", + status, error, idx_str, idx, + cha_str, cha_err_code, + err_str, err_err_code); +} + +static void report_jump_status(const u32 status, + const char *error) +{ + debug("%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +static void report_deco_status(const u32 status, + const char *error) +{ + u8 err_id = status & JRSTA_DECOERR_ERROR_MASK; + u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> + JRSTA_DECOERR_INDEX_SHIFT; + char *idx_str; + const char *err_str = "unidentified error value 0x"; + char err_err_code[3] = { 0 }; + int i; + + if (status & JRSTA_DECOERR_JUMP) + idx_str = "jump tgt desc idx"; + else + idx_str = "desc idx"; + + for (i = 0; i < ARRAY_SIZE(desc_error_list); i++) + if (desc_error_list[i].value == err_id) + break; + + if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text) + err_str = desc_error_list[i].error_text; + else + snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id); + + debug("%08x: %s: %s %d: %s%s\n", + status, error, idx_str, idx, err_str, err_err_code); +} + +static void report_jr_status(const u32 status, + const char *error) +{ + debug("%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +static void report_cond_code_status(const u32 status, + const char *error) +{ + debug("%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +void caam_jr_strstatus(u32 status) +{ + static const struct stat_src { + void (*report_ssed)(const u32 status, + const char *error); + const char *error; + } status_src[] = { + { NULL, "No error" }, + { NULL, NULL }, + { report_ccb_status, "CCB" }, + { report_jump_status, "Jump" }, + { report_deco_status, "DECO" }, + { NULL, NULL }, + { report_jr_status, "Job Ring" }, + { report_cond_code_status, "Condition Code" }, + }; + u32 ssrc = status >> JRSTA_SSRC_SHIFT; + const char *error = status_src[ssrc].error; + + /* + * If there is no further error handling function, just + * print the error code, error string and exit. Otherwise + * call the handler function. + */ + if (!status_src[ssrc].report_ssed) + debug("%08x: %s:\n", status, status_src[ssrc].error); + else + status_src[ssrc].report_ssed(status, error); +} diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c new file mode 100644 index 0000000000..bc0107521c --- /dev/null +++ b/drivers/crypto/fsl/fsl_blob.c @@ -0,0 +1,61 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include "jobdesc.h" +#include "desc.h" +#include "jr.h" + +int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) +{ + int ret, i = 0; + u32 *desc; + + printf("\nDecapsulating data to form blob\n"); + desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + if (!desc) { + debug("Not enough memory for descriptor allocation\n"); + return -1; + } + + inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len); + + for (i = 0; i < 14; i++) + printf("%x\n", *(desc + i)); + ret = run_descriptor_jr(desc); + + if (ret) + printf("Error in Decapsulation %d\n", ret); + + free(desc); + return ret; +} + +int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) +{ + int ret, i = 0; + u32 *desc; + + printf("\nEncapsulating data to form blob\n"); + desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + if (!desc) { + debug("Not enough memory for descriptor allocation\n"); + return -1; + } + + inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len); + for (i = 0; i < 14; i++) + printf("%x\n", *(desc + i)); + ret = run_descriptor_jr(desc); + + if (ret) + printf("Error in Encapsulation %d\n", ret); + + free(desc); + return ret; +} diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c new file mode 100644 index 0000000000..d77f2573d0 --- /dev/null +++ b/drivers/crypto/fsl/fsl_hash.c @@ -0,0 +1,77 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include "jobdesc.h" +#include "desc.h" +#include "jr.h" + +#define CRYPTO_MAX_ALG_NAME 80 +#define SHA1_DIGEST_SIZE 20 +#define SHA256_DIGEST_SIZE 32 + +struct caam_hash_template { + char name[CRYPTO_MAX_ALG_NAME]; + unsigned int digestsize; + u32 alg_type; +}; + +enum caam_hash_algos { + SHA1 = 0, + SHA256 +}; + +static struct caam_hash_template driver_hash[] = { + { + .name = "sha1", + .digestsize = SHA1_DIGEST_SIZE, + .alg_type = OP_ALG_ALGSEL_SHA1, + }, + { + .name = "sha256", + .digestsize = SHA256_DIGEST_SIZE, + .alg_type = OP_ALG_ALGSEL_SHA256, + }, +}; + +int caam_hash(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, enum caam_hash_algos algo) +{ + int ret = 0; + uint32_t *desc; + + desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + if (!desc) { + debug("Not enough memory for descriptor allocation\n"); + return -1; + } + + inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout, + driver_hash[algo].alg_type, + driver_hash[algo].digestsize, + 0); + + ret = run_descriptor_jr(desc); + + free(desc); + return ret; +} + +void hw_sha256(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + if (caam_hash(pbuf, buf_len, pout, SHA256)) + printf("CAAM was not setup properly or it is faulty\n"); +} + +void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + if (caam_hash(pbuf, buf_len, pout, SHA1)) + printf("CAAM was not setup properly or it is faulty\n"); +} diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c new file mode 100644 index 0000000000..cf1c4c1d45 --- /dev/null +++ b/drivers/crypto/fsl/fsl_rsa.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + * Author: Ruchika Gupta + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "jobdesc.h" +#include "desc.h" +#include "jr.h" +#include "rsa_caam.h" +#include + +int fsl_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, + struct key_prop *prop, uint8_t *out) +{ + uint32_t keylen; + struct pk_in_params pkin; + uint32_t desc[MAX_CAAM_DESCSIZE]; + int ret; + + /* Length in bytes */ + keylen = prop->num_bits / 8; + + pkin.a = sig; + pkin.a_siz = sig_len; + pkin.n = prop->modulus; + pkin.n_siz = keylen; + pkin.e = prop->public_exponent; + pkin.e_siz = prop->exp_len; + + inline_cnstr_jobdesc_pkha_rsaexp(desc, &pkin, out, sig_len); + + ret = run_descriptor_jr(desc); + if (ret) { + debug("%s: RSA failed to verify: %d\n", __func__, ret); + return -EFAULT; + } + + return 0; +} + +static const struct mod_exp_ops fsl_mod_exp_ops = { + .mod_exp = fsl_mod_exp, +}; + +U_BOOT_DRIVER(fsl_rsa_mod_exp) = { + .name = "fsl_rsa_mod_exp", + .id = UCLASS_MOD_EXP, + .ops = &fsl_mod_exp_ops, +}; + +U_BOOT_DEVICE(fsl_rsa) = { + .name = "fsl_rsa_mod_exp", +}; diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c new file mode 100644 index 0000000000..cc0dcede7b --- /dev/null +++ b/drivers/crypto/fsl/jobdesc.c @@ -0,0 +1,153 @@ +/* + * SEC Descriptor Construction Library + * Basic job descriptor construction + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include "desc_constr.h" +#include "jobdesc.h" +#include "rsa_caam.h" + +#define KEY_BLOB_SIZE 32 +#define MAC_SIZE 16 + +void inline_cnstr_jobdesc_hash(uint32_t *desc, + const uint8_t *msg, uint32_t msgsz, uint8_t *digest, + u32 alg_type, uint32_t alg_size, int sg_tbl) +{ + /* SHA 256 , output is of length 32 words */ + uint32_t storelen = alg_size; + u32 options; + dma_addr_t dma_addr_in, dma_addr_out; + + dma_addr_in = virt_to_phys((void *)msg); + dma_addr_out = virt_to_phys((void *)digest); + + init_job_desc(desc, 0); + append_operation(desc, OP_TYPE_CLASS2_ALG | + OP_ALG_AAI_HASH | OP_ALG_AS_INITFINAL | + OP_ALG_ENCRYPT | OP_ALG_ICV_OFF | alg_type); + + options = LDST_CLASS_2_CCB | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2; + if (sg_tbl) + options |= FIFOLDST_SGF; + if (msgsz > 0xffff) { + options |= FIFOLDST_EXT; + append_fifo_load(desc, dma_addr_in, 0, options); + append_cmd(desc, msgsz); + } else { + append_fifo_load(desc, dma_addr_in, msgsz, options); + } + + append_store(desc, dma_addr_out, storelen, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT); +} + +void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, + uint8_t *plain_txt, uint8_t *enc_blob, + uint32_t in_sz) +{ + dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + uint32_t key_sz = KEY_IDNFR_SZ_BYTES; + /* output blob will have 32 bytes key blob in beginning and + * 16 byte HMAC identifier at end of data blob */ + uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE; + + dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr); + dma_addr_in = virt_to_phys((void *)plain_txt); + dma_addr_out = virt_to_phys((void *)enc_blob); + + init_job_desc(desc, 0); + + append_key(desc, dma_addr_key_idnfr, key_sz, CLASS_2); + + append_seq_in_ptr(desc, dma_addr_in, in_sz, 0); + + append_seq_out_ptr(desc, dma_addr_out, out_sz, 0); + + append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB); +} + +void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, + uint8_t *enc_blob, uint8_t *plain_txt, + uint32_t out_sz) +{ + dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + uint32_t key_sz = KEY_IDNFR_SZ_BYTES; + uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE; + + dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr); + dma_addr_in = virt_to_phys((void *)enc_blob); + dma_addr_out = virt_to_phys((void *)plain_txt); + + init_job_desc(desc, 0); + + append_key(desc, dma_addr_key_idnfr, key_sz, CLASS_2); + + append_seq_in_ptr(desc, dma_addr_in, in_sz, 0); + + append_seq_out_ptr(desc, dma_addr_out, out_sz, 0); + + append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); +} + +/* + * Descriptor to instantiate RNG State Handle 0 in normal mode and + * load the JDKEK, TDKEK and TDSK registers + */ +void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc) +{ + u32 *jump_cmd; + + init_job_desc(desc, 0); + + /* INIT RNG in non-test mode */ + append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + OP_ALG_AS_INIT); + + /* wait for done */ + jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); + set_jump_tgt_here(desc, jump_cmd); + + /* + * load 1 to clear written reg: + * resets the done interrrupt and returns the RNG to idle. + */ + append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); + + /* generate secure keys (non-test) */ + append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + OP_ALG_RNG4_SK); +} + +/* Change key size to bytes form bits in calling function*/ +void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, + struct pk_in_params *pkin, uint8_t *out, + uint32_t out_siz) +{ + dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; + + dma_addr_e = virt_to_phys((void *)pkin->e); + dma_addr_a = virt_to_phys((void *)pkin->a); + dma_addr_n = virt_to_phys((void *)pkin->n); + dma_addr_out = virt_to_phys((void *)out); + + init_job_desc(desc, 0); + append_key(desc, dma_addr_e, pkin->e_siz, KEY_DEST_PKHA_E | CLASS_1); + + append_fifo_load(desc, dma_addr_a, + pkin->a_siz, LDST_CLASS_1_CCB | FIFOLD_TYPE_PK_A); + + append_fifo_load(desc, dma_addr_n, + pkin->n_siz, LDST_CLASS_1_CCB | FIFOLD_TYPE_PK_N); + + append_operation(desc, OP_TYPE_PK | OP_ALG_PK | OP_ALG_PKMODE_MOD_EXPO); + + append_fifo_store(desc, dma_addr_out, out_siz, + LDST_CLASS_1_CCB | FIFOST_TYPE_PKHA_B); +} diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h new file mode 100644 index 0000000000..84b3edd6e2 --- /dev/null +++ b/drivers/crypto/fsl/jobdesc.h @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __JOBDESC_H +#define __JOBDESC_H + +#include +#include +#include "rsa_caam.h" + +#define KEY_IDNFR_SZ_BYTES 16 + +void inline_cnstr_jobdesc_hash(uint32_t *desc, + const uint8_t *msg, uint32_t msgsz, uint8_t *digest, + u32 alg_type, uint32_t alg_size, int sg_tbl); + +void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, + uint8_t *plain_txt, uint8_t *enc_blob, + uint32_t in_sz); + +void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, + uint8_t *enc_blob, uint8_t *plain_txt, + uint32_t out_sz); + +void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc); + +void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, + struct pk_in_params *pkin, uint8_t *out, + uint32_t out_siz); +#endif diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c new file mode 100644 index 0000000000..f9d4938834 --- /dev/null +++ b/drivers/crypto/fsl/jr.c @@ -0,0 +1,462 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Based on CAAM driver in drivers/crypto/caam in Linux + */ + +#include +#include +#include "fsl_sec.h" +#include "jr.h" +#include "jobdesc.h" + +#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) +#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) + +struct jobring jr; + +static inline void start_jr0(void) +{ + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + u32 ctpr_ms = sec_in32(&sec->ctpr_ms); + u32 scfgr = sec_in32(&sec->scfgr); + + if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) { + /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or + * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1 + */ + if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) || + (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) && + (scfgr & SEC_SCFGR_VIRT_EN))) + sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); + } else { + /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ + if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) + sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); + } +} + +static inline void jr_reset_liodn(void) +{ + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + sec_out32(&sec->jrliodnr[0].ls, 0); +} + +static inline void jr_disable_irq(void) +{ + struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + uint32_t jrcfg = sec_in32(®s->jrcfg1); + + jrcfg = jrcfg | JR_INTMASK; + + sec_out32(®s->jrcfg1, jrcfg); +} + +static void jr_initregs(void) +{ + struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring); + phys_addr_t op_base = virt_to_phys((void *)jr.output_ring); + +#ifdef CONFIG_PHYS_64BIT + sec_out32(®s->irba_h, ip_base >> 32); +#else + sec_out32(®s->irba_h, 0x0); +#endif + sec_out32(®s->irba_l, (uint32_t)ip_base); +#ifdef CONFIG_PHYS_64BIT + sec_out32(®s->orba_h, op_base >> 32); +#else + sec_out32(®s->orba_h, 0x0); +#endif + sec_out32(®s->orba_l, (uint32_t)op_base); + sec_out32(®s->ors, JR_SIZE); + sec_out32(®s->irs, JR_SIZE); + + if (!jr.irq) + jr_disable_irq(); +} + +static int jr_init(void) +{ + memset(&jr, 0, sizeof(struct jobring)); + + jr.jq_id = DEFAULT_JR_ID; + jr.irq = DEFAULT_IRQ; + +#ifdef CONFIG_FSL_CORENET + jr.liodn = DEFAULT_JR_LIODN; +#endif + jr.size = JR_SIZE; + jr.input_ring = (dma_addr_t *)malloc(JR_SIZE * sizeof(dma_addr_t)); + if (!jr.input_ring) + return -1; + jr.output_ring = + (struct op_ring *)malloc(JR_SIZE * sizeof(struct op_ring)); + if (!jr.output_ring) + return -1; + + memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); + memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring)); + + start_jr0(); + + jr_initregs(); + + return 0; +} + +static int jr_sw_cleanup(void) +{ + jr.head = 0; + jr.tail = 0; + jr.read_idx = 0; + jr.write_idx = 0; + memset(jr.info, 0, sizeof(jr.info)); + memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t)); + memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring)); + + return 0; +} + +static int jr_hw_reset(void) +{ + struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + uint32_t timeout = 100000; + uint32_t jrint, jrcr; + + sec_out32(®s->jrcr, JRCR_RESET); + do { + jrint = sec_in32(®s->jrint); + } while (((jrint & JRINT_ERR_HALT_MASK) == + JRINT_ERR_HALT_INPROGRESS) && --timeout); + + jrint = sec_in32(®s->jrint); + if (((jrint & JRINT_ERR_HALT_MASK) != + JRINT_ERR_HALT_INPROGRESS) && timeout == 0) + return -1; + + timeout = 100000; + sec_out32(®s->jrcr, JRCR_RESET); + do { + jrcr = sec_in32(®s->jrcr); + } while ((jrcr & JRCR_RESET) && --timeout); + + if (timeout == 0) + return -1; + + return 0; +} + +/* -1 --- error, can't enqueue -- no space available */ +static int jr_enqueue(uint32_t *desc_addr, + void (*callback)(uint32_t desc, uint32_t status, void *arg), + void *arg) +{ + struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + int head = jr.head; + dma_addr_t desc_phys_addr = virt_to_phys(desc_addr); + + if (sec_in32(®s->irsa) == 0 || + CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0) + return -1; + + jr.input_ring[head] = desc_phys_addr; + jr.info[head].desc_phys_addr = desc_phys_addr; + jr.info[head].desc_addr = (uint32_t)desc_addr; + jr.info[head].callback = (void *)callback; + jr.info[head].arg = arg; + jr.info[head].op_done = 0; + + jr.head = (head + 1) & (jr.size - 1); + + sec_out32(®s->irja, 1); + + return 0; +} + +static int jr_dequeue(void) +{ + struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; + int head = jr.head; + int tail = jr.tail; + int idx, i, found; + void (*callback)(uint32_t desc, uint32_t status, void *arg); + void *arg = NULL; + + while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { + found = 0; + + dma_addr_t op_desc = jr.output_ring[jr.tail].desc; + uint32_t status = jr.output_ring[jr.tail].status; + uint32_t desc_virt; + + for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) { + idx = (tail + i) & (jr.size - 1); + if (op_desc == jr.info[idx].desc_phys_addr) { + desc_virt = jr.info[idx].desc_addr; + found = 1; + break; + } + } + + /* Error condition if match not found */ + if (!found) + return -1; + + jr.info[idx].op_done = 1; + callback = (void *)jr.info[idx].callback; + arg = jr.info[idx].arg; + + /* When the job on tail idx gets done, increment + * tail till the point where job completed out of oredr has + * been taken into account + */ + if (idx == tail) + do { + tail = (tail + 1) & (jr.size - 1); + } while (jr.info[tail].op_done); + + jr.tail = tail; + jr.read_idx = (jr.read_idx + 1) & (jr.size - 1); + + sec_out32(®s->orjr, 1); + jr.info[idx].op_done = 0; + + callback(desc_virt, status, arg); + } + + return 0; +} + +static void desc_done(uint32_t desc, uint32_t status, void *arg) +{ + struct result *x = arg; + x->status = status; + caam_jr_strstatus(status); + x->done = 1; +} + +int run_descriptor_jr(uint32_t *desc) +{ + unsigned long long timeval = get_ticks(); + unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); + struct result op; + int ret = 0; + + memset(&op, 0, sizeof(op)); + + ret = jr_enqueue(desc, desc_done, &op); + if (ret) { + debug("Error in SEC enq\n"); + ret = JQ_ENQ_ERR; + goto out; + } + + timeval = get_ticks(); + timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); + while (op.done != 1) { + ret = jr_dequeue(); + if (ret) { + debug("Error in SEC deq\n"); + ret = JQ_DEQ_ERR; + goto out; + } + + if ((get_ticks() - timeval) > timeout) { + debug("SEC Dequeue timed out\n"); + ret = JQ_DEQ_TO_ERR; + goto out; + } + } + + if (!op.status) { + debug("Error %x\n", op.status); + ret = op.status; + } +out: + return ret; +} + +int jr_reset(void) +{ + if (jr_hw_reset() < 0) + return -1; + + /* Clean up the jobring structure maintained by software */ + jr_sw_cleanup(); + + return 0; +} + +int sec_reset(void) +{ + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + uint32_t mcfgr = sec_in32(&sec->mcfgr); + uint32_t timeout = 100000; + + mcfgr |= MCFGR_SWRST; + sec_out32(&sec->mcfgr, mcfgr); + + mcfgr |= MCFGR_DMA_RST; + sec_out32(&sec->mcfgr, mcfgr); + do { + mcfgr = sec_in32(&sec->mcfgr); + } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout); + + if (timeout == 0) + return -1; + + timeout = 100000; + do { + mcfgr = sec_in32(&sec->mcfgr); + } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout); + + if (timeout == 0) + return -1; + + return 0; +} + +static int instantiate_rng(void) +{ + struct result op; + u32 *desc; + u32 rdsta_val; + int ret = 0; + ccsr_sec_t __iomem *sec = + (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + struct rng4tst __iomem *rng = + (struct rng4tst __iomem *)&sec->rng; + + memset(&op, 0, sizeof(struct result)); + + desc = malloc(sizeof(int) * 6); + if (!desc) { + printf("cannot allocate RNG init descriptor memory\n"); + return -1; + } + + inline_cnstr_jobdesc_rng_instantiation(desc); + ret = run_descriptor_jr(desc); + + if (ret) + printf("RNG: Instantiation failed with error %x\n", ret); + + rdsta_val = sec_in32(&rng->rdsta); + if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED)) + return -1; + + return ret; +} + +static u8 get_rng_vid(void) +{ + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + u32 cha_vid = sec_in32(&sec->chavid_ls); + + return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT; +} + +/* + * By default, the TRNG runs for 200 clocks per sample; + * 1200 clocks per sample generates better entropy. + */ +static void kick_trng(int ent_delay) +{ + ccsr_sec_t __iomem *sec = + (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + struct rng4tst __iomem *rng = + (struct rng4tst __iomem *)&sec->rng; + u32 val; + + /* put RNG4 into program mode */ + sec_setbits32(&rng->rtmctl, RTMCTL_PRGM); + /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the + * length (in system clocks) of each Entropy sample taken + * */ + val = sec_in32(&rng->rtsdctl); + val = (val & ~RTSDCTL_ENT_DLY_MASK) | + (ent_delay << RTSDCTL_ENT_DLY_SHIFT); + sec_out32(&rng->rtsdctl, val); + /* min. freq. count, equal to 1/4 of the entropy sample length */ + sec_out32(&rng->rtfreqmin, ent_delay >> 2); + /* max. freq. count, equal to 8 times the entropy sample length */ + sec_out32(&rng->rtfreqmax, ent_delay << 3); + /* put RNG4 into run mode */ + sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); +} + +static int rng_init(void) +{ + int ret, ent_delay = RTSDCTL_ENT_DLY_MIN; + ccsr_sec_t __iomem *sec = + (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + struct rng4tst __iomem *rng = + (struct rng4tst __iomem *)&sec->rng; + + u32 rdsta = sec_in32(&rng->rdsta); + + /* Check if RNG state 0 handler is already instantiated */ + if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) + return 0; + + do { + /* + * If either of the SH's were instantiated by somebody else + * then it is assumed that the entropy + * parameters are properly set and thus the function + * setting these (kick_trng(...)) is skipped. + * Also, if a handle was instantiated, do not change + * the TRNG parameters. + */ + kick_trng(ent_delay); + ent_delay += 400; + /* + * if instantiate_rng(...) fails, the loop will rerun + * and the kick_trng(...) function will modfiy the + * upper and lower limits of the entropy sampling + * interval, leading to a sucessful initialization of + * the RNG. + */ + ret = instantiate_rng(); + } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); + if (ret) { + printf("RNG: Failed to instantiate RNG\n"); + return ret; + } + + /* Enable RDB bit so that RNG works faster */ + sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE); + + return ret; +} + +int sec_init(void) +{ + int ret = 0; + +#ifdef CONFIG_PHYS_64BIT + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + uint32_t mcr = sec_in32(&sec->mcfgr); + + sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT); +#endif + ret = jr_init(); + if (ret < 0) { + printf("SEC initialization failed\n"); + return -1; + } + + if (get_rng_vid() >= 4) { + if (rng_init() < 0) { + printf("RNG instantiation failed\n"); + return -1; + } + printf("SEC: RNG instantiated\n"); + } + + return ret; +} diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h new file mode 100644 index 0000000000..cce2c589ce --- /dev/null +++ b/drivers/crypto/fsl/jr.h @@ -0,0 +1,97 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __JR_H +#define __JR_H + +#include + +#define JR_SIZE 4 +/* Timeout currently defined as 90 sec */ +#define CONFIG_SEC_DEQ_TIMEOUT 90000000U + +#define DEFAULT_JR_ID 0 +#define DEFAULT_JR_LIODN 0 +#define DEFAULT_IRQ 0 /* Interrupts not to be configured */ + +#define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */ +#define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */ +#define MCFGR_PS_SHIFT 16 +#define JR_INTMASK 0x00000001 +#define JRCR_RESET 0x01 +#define JRINT_ERR_HALT_INPROGRESS 0x4 +#define JRINT_ERR_HALT_MASK 0xc +#define JRNSLIODN_SHIFT 16 +#define JRNSLIODN_MASK 0x0fff0000 +#define JRSLIODN_SHIFT 0 +#define JRSLIODN_MASK 0x00000fff + +#define JQ_DEQ_ERR -1 +#define JQ_DEQ_TO_ERR -2 +#define JQ_ENQ_ERR -3 + +struct op_ring { + dma_addr_t desc; + uint32_t status; +} __packed; + +struct jr_info { + void (*callback)(dma_addr_t desc, uint32_t status, void *arg); + dma_addr_t desc_phys_addr; + uint32_t desc_addr; + uint32_t desc_len; + uint32_t op_done; + void *arg; +}; + +struct jobring { + int jq_id; + int irq; + int liodn; + /* Head is the index where software would enq the descriptor in + * the i/p ring + */ + int head; + /* Tail index would be used by s/w ehile enqueuing to determine if + * there is any space left in the s/w maintained i/p rings + */ + /* Also in case of deq tail will be incremented only in case of + * in-order job completion + */ + int tail; + /* Read index of the output ring. It may not match with tail in case + * of out of order completetion + */ + int read_idx; + /* Write index to input ring. Would be always equal to head */ + int write_idx; + /* Size of the rings. */ + int size; + /* The ip and output rings have to be accessed by SEC. So the + * pointers will ahve to point to the housekeeping region provided + * by SEC + */ + /*Circular Ring of i/p descriptors */ + dma_addr_t *input_ring; + /* Circular Ring of o/p descriptors */ + /* Circula Ring containing info regarding descriptors in i/p + * and o/p ring + */ + /* This ring can be on the stack */ + struct jr_info info[JR_SIZE]; + struct op_ring *output_ring; +}; + +struct result { + int done; + uint32_t status; +}; + +void caam_jr_strstatus(u32 status); +int run_descriptor_jr(uint32_t *desc); + +#endif diff --git a/drivers/crypto/fsl/rsa_caam.h b/drivers/crypto/fsl/rsa_caam.h new file mode 100644 index 0000000000..4ff87efc5b --- /dev/null +++ b/drivers/crypto/fsl/rsa_caam.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RSA_CAAM_H +#define __RSA_CAAM_H + +#include + +/** + * struct pk_in_params - holder for input to PKHA block in CAAM + * These parameters are required to perform Modular Exponentiation + * using PKHA Block in CAAM + */ +struct pk_in_params { + const uint8_t *e; /* public exponent as byte array */ + uint32_t e_siz; /* size of e[] in number of bytes */ + const uint8_t *n; /* modulus as byte array */ + uint32_t n_siz; /* size of n[] in number of bytes */ + const uint8_t *a; /* Signature as byte array */ + uint32_t a_siz; /* size of a[] in number of bytes */ + uint8_t *b; /* Result exp. modulus in number of bytes */ + uint32_t b_siz; /* size of b[] in number of bytes */ +}; + +#endif diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c new file mode 100644 index 0000000000..443ee964fe --- /dev/null +++ b/drivers/crypto/fsl/sec.c @@ -0,0 +1,184 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#if CONFIG_SYS_FSL_SEC_COMPAT == 2 || CONFIG_SYS_FSL_SEC_COMPAT >= 4 +#include +#endif + +/* + * update crypto node properties to a specified revision of the SEC + * called with sec_rev == 0 if not on an E processor + */ +#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */ +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + static const struct sec_rev_prop { + u32 sec_rev; + u32 num_channels; + u32 channel_fifo_len; + u32 exec_units_mask; + u32 descriptor_types_mask; + } sec_rev_prop_list[] = { + { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ + { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ + { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ + { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ + { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ + { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ + { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ + }; + static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * + sizeof("fsl,secX.Y")]; + int crypto_node, sec_idx, err; + char *p; + u32 val; + + /* locate crypto node based on lowest common compatible */ + crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); + if (crypto_node == -FDT_ERR_NOTFOUND) + return; + + /* delete it if not on an E-processor */ + if (crypto_node > 0 && !sec_rev) { + fdt_del_node(blob, crypto_node); + return; + } + + /* else we got called for possible uprev */ + for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) + if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) + break; + + if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { + puts("warning: unknown SEC revision number\n"); + return; + } + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); + err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); + err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", + &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); + err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); + err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = 0; + while (sec_idx >= 0) { + p = compat_strlist + val; + val += sprintf(p, "fsl,sec%d.%d", + (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, + sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; + sec_idx--; + } + err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, + val); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); +} +#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ +static u8 caam_get_era(void) +{ + static const struct { + u16 ip_id; + u8 maj_rev; + u8 era; + } caam_eras[] = { + {0x0A10, 1, 1}, + {0x0A10, 2, 2}, + {0x0A12, 1, 3}, + {0x0A14, 1, 3}, + {0x0A14, 2, 4}, + {0x0A16, 1, 4}, + {0x0A10, 3, 4}, + {0x0A11, 1, 4}, + {0x0A18, 1, 4}, + {0x0A11, 2, 5}, + {0x0A12, 2, 5}, + {0x0A13, 1, 5}, + {0x0A1C, 1, 5} + }; + + ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + u32 secvid_ms = sec_in32(&sec->secvid_ms); + u32 ccbvid = sec_in32(&sec->ccbvid); + u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> + SEC_SECVID_MS_IPID_SHIFT; + u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >> + SEC_SECVID_MS_MAJ_REV_SHIFT; + u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT; + + int i; + + if (era) /* This is '0' prior to CAAM ERA-6 */ + return era; + + for (i = 0; i < ARRAY_SIZE(caam_eras); i++) + if (caam_eras[i].ip_id == ip_id && + caam_eras[i].maj_rev == maj_rev) + return caam_eras[i].era; + + return 0; +} + +static void fdt_fixup_crypto_era(void *blob, u32 era) +{ + int err; + int crypto_node; + + crypto_node = fdt_path_offset(blob, "crypto"); + if (crypto_node < 0) { + printf("WARNING: Missing crypto node\n"); + return; + } + + err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era, + sizeof(era)); + if (err < 0) { + printf("ERROR: could not set fsl,sec-era property: %s\n", + fdt_strerror(err)); + } +} + +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + u8 era; + + if (!sec_rev) { + fdt_del_node_and_alias(blob, "crypto"); + return; + } + + /* Add SEC ERA information in compatible */ + era = caam_get_era(); + if (era) { + fdt_fixup_crypto_era(blob, era); + } else { + printf("WARNING: Unable to get ERA for CAAM rev: %d\n", + sec_rev); + } +} +#endif diff --git a/drivers/crypto/rsa_mod_exp/Kconfig b/drivers/crypto/rsa_mod_exp/Kconfig new file mode 100644 index 0000000000..6dcb39a8d3 --- /dev/null +++ b/drivers/crypto/rsa_mod_exp/Kconfig @@ -0,0 +1,5 @@ +config DM_MOD_EXP + bool "Enable Driver Model for RSA Modular Exponentiation" + depends on DM + help + If you want to use driver model for RSA Modular Exponentiation, say Y. diff --git a/drivers/crypto/rsa_mod_exp/Makefile b/drivers/crypto/rsa_mod_exp/Makefile new file mode 100644 index 0000000000..915b751dbe --- /dev/null +++ b/drivers/crypto/rsa_mod_exp/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_RSA) += mod_exp_uclass.o mod_exp_sw.o diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c new file mode 100644 index 0000000000..dc6c064b4e --- /dev/null +++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + * Author: Ruchika Gupta + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int mod_exp_sw(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, + struct key_prop *prop, uint8_t *out) +{ + int ret = 0; + + ret = rsa_mod_exp_sw(sig, sig_len, prop, out); + if (ret) { + debug("%s: RSA failed to verify: %d\n", __func__, ret); + return ret; + } + + return 0; +} + +static const struct mod_exp_ops mod_exp_ops_sw = { + .mod_exp = mod_exp_sw, +}; + +U_BOOT_DRIVER(mod_exp_sw) = { + .name = "mod_exp_sw", + .id = UCLASS_MOD_EXP, + .ops = &mod_exp_ops_sw, +}; + +U_BOOT_DEVICE(mod_exp_sw) = { + .name = "mod_exp_sw", +}; diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c new file mode 100644 index 0000000000..266f09484f --- /dev/null +++ b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc + * Author: Ruchika Gupta + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, + struct key_prop *node, uint8_t *out) +{ + const struct mod_exp_ops *ops = device_get_ops(dev); + + if (!ops->mod_exp) + return -ENOSYS; + + return ops->mod_exp(dev, sig, sig_len, node, out); +} + +UCLASS_DRIVER(mod_exp) = { + .id = UCLASS_MOD_EXP, + .name = "rsa_mod_exp", +}; diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile new file mode 100644 index 0000000000..df66c07230 --- /dev/null +++ b/drivers/ddr/fsl/Makefile @@ -0,0 +1,37 @@ +# +# Copyright 2008-2014 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# Version 2 as published by the Free Software Foundation. +# + +obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o + +ifdef CONFIG_DDR_SPD +SPD := y +endif +ifdef CONFIG_SPD_EEPROM +SPD := y +endif +ifdef SPD +obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o +endif + +obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o +obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o +obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o +obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o +obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o +obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o +obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c new file mode 100644 index 0000000000..c139da6da9 --- /dev/null +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -0,0 +1,247 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived from mpc85xx_ddr_gen3.c, removed all workarounds + */ + +#include +#include +#include +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + + +/* + * regs has the to-be-set values for DDR controller registers + * ctrl_num is the DDR controller number + * step: 0 goes through the initialization in one pass + * 1 sets registers and returns before enabling controller + * 2 resumes from step 1 and continues to initialize + * Dividing the initialization to two steps to deassert DDR reset signal + * to comply with JEDEC specs for RDIMMs. + */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i, bus_width; + struct ccsr_ddr __iomem *ddr; + u32 temp_sdram_cfg; + u32 total_gb_size_per_controller; + int timeout; + + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); + return; + } + + if (step == 2) + goto step2; + + if (regs->ddr_eor) + ddr_out32(&ddr->eor, regs->ddr_eor); + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs0_config, regs->cs[i].config); + ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); + + } else if (i == 1) { + ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs1_config, regs->cs[i].config); + ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); + + } else if (i == 2) { + ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs2_config, regs->cs[i].config); + ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); + + } else if (i == 3) { + ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs3_config, regs->cs[i].config); + ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); + } + } + + ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); + ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); + ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); + ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); + ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); + ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); + ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); + ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); + ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); + ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); +#ifndef CONFIG_SYS_FSL_DDR_EMU + /* + * Skip these two registers if running on emulator + * because emulator doesn't have skew between bytes. + */ + + if (regs->ddr_wrlvl_cntl_2) + ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + if (regs->ddr_wrlvl_cntl_3) + ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); +#endif + + ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + ddr_out32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + ddr_out32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } + ddr_out32(&ddr->err_disable, regs->err_disable); + ddr_out32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) { + if (regs->debug[i]) { + debug("Write to debug_%d as %08x\n", i + 1, + regs->debug[i]); + ddr_out32(&ddr->debug[i], regs->debug[i]); + } + } + + /* + * For RDIMMs, JEDEC spec requires clocks to be stable before reset is + * deasserted. Clocks start when any chip select is enabled and clock + * control register is set. Because all DDR components are connected to + * one reset signal, this needs to be done in two steps. Step 1 is to + * get the clocks started. Step 2 resumes after reset signal is + * deasserted. + */ + if (step == 1) { + udelay(200); + return; + } + +step2: + /* Set, but do not enable the memory */ + temp_sdram_cfg = regs->ddr_sdram_cfg; + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); + + /* + * 500 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. + */ + udelay(500); + asm volatile("dsb sy;isb"); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + /* do board specific memory setup */ + board_mem_sleep_setup(); + + temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + /* Let the controller go */ + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + asm volatile("dsb sy;isb"); + + total_gb_size_per_controller = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (!(regs->cs[i].config & 0x80000000)) + continue; + total_gb_size_per_controller += 1 << ( + ((regs->cs[i].config >> 14) & 0x3) + 2 + + ((regs->cs[i].config >> 8) & 0x7) + 12 + + ((regs->cs[i].config >> 0) & 0x7) + 8 + + 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - + 26); /* minus 26 (count of 64M) */ + } + if (regs->cs[0].config & 0x20000000) { + /* 2-way interleaving */ + total_gb_size_per_controller <<= 1; + } + /* + * total memory / bus width = transactions needed + * transactions needed / data rate = seconds + * to add plenty of buffer, double the time + * For example, 2GB on 666MT/s 64-bit bus takes about 402ms + * Let's wait for 800ms + */ + bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) + >> SDRAM_CFG_DBW_SHIFT); + timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / + (get_ddr_freq(0) >> 20)) << 1; + total_gb_size_per_controller >>= 4; /* shift down to gb size */ + debug("total %d GB\n", total_gb_size_per_controller); + debug("Need to wait up to %d * 10ms\n", timeout); + + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ + while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif +} diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c new file mode 100644 index 0000000000..03d7ff17dd --- /dev/null +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -0,0 +1,2383 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Based on code from spd_sdram.c + * Author: James Yang [at freescale.com] + */ + +#include +#include + +#include +#include +#include + +unsigned int picos_to_mclk(unsigned int picos); + +/* + * Determine Rtt value. + * + * This should likely be either board or controller specific. + * + * Rtt(nominal) - DDR2: + * 0 = Rtt disabled + * 1 = 75 ohm + * 2 = 150 ohm + * 3 = 50 ohm + * Rtt(nominal) - DDR3: + * 0 = Rtt disabled + * 1 = 60 ohm + * 2 = 120 ohm + * 3 = 40 ohm + * 4 = 20 ohm + * 5 = 30 ohm + * + * FIXME: Apparently 8641 needs a value of 2 + * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 + * + * FIXME: There was some effort down this line earlier: + * + * unsigned int i; + * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { + * if (popts->dimmslot[i].num_valid_cs + * && (popts->cs_local_opts[2*i].odt_rd_cfg + * || popts->cs_local_opts[2*i].odt_wr_cfg)) { + * rtt = 2; + * break; + * } + * } + */ +static inline int fsl_ddr_get_rtt(void) +{ + int rtt; + +#if defined(CONFIG_SYS_FSL_DDR1) + rtt = 0; +#elif defined(CONFIG_SYS_FSL_DDR2) + rtt = 3; +#else + rtt = 0; +#endif + + return rtt; +} + +#ifdef CONFIG_SYS_FSL_DDR4 +/* + * compute CAS write latency according to DDR4 spec + * CWL = 9 for <= 1600MT/s + * 10 for <= 1866MT/s + * 11 for <= 2133MT/s + * 12 for <= 2400MT/s + * 14 for <= 2667MT/s + * 16 for <= 2933MT/s + * 18 for higher + */ +static inline unsigned int compute_cas_write_latency(void) +{ + unsigned int cwl; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + if (mclk_ps >= 1250) + cwl = 9; + else if (mclk_ps >= 1070) + cwl = 10; + else if (mclk_ps >= 935) + cwl = 11; + else if (mclk_ps >= 833) + cwl = 12; + else if (mclk_ps >= 750) + cwl = 14; + else if (mclk_ps >= 681) + cwl = 16; + else + cwl = 18; + + return cwl; +} +#else +/* + * compute the CAS write latency according to DDR3 spec + * CWL = 5 if tCK >= 2.5ns + * 6 if 2.5ns > tCK >= 1.875ns + * 7 if 1.875ns > tCK >= 1.5ns + * 8 if 1.5ns > tCK >= 1.25ns + * 9 if 1.25ns > tCK >= 1.07ns + * 10 if 1.07ns > tCK >= 0.935ns + * 11 if 0.935ns > tCK >= 0.833ns + * 12 if 0.833ns > tCK >= 0.75ns + */ +static inline unsigned int compute_cas_write_latency(void) +{ + unsigned int cwl; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + + if (mclk_ps >= 2500) + cwl = 5; + else if (mclk_ps >= 1875) + cwl = 6; + else if (mclk_ps >= 1500) + cwl = 7; + else if (mclk_ps >= 1250) + cwl = 8; + else if (mclk_ps >= 1070) + cwl = 9; + else if (mclk_ps >= 935) + cwl = 10; + else if (mclk_ps >= 833) + cwl = 11; + else if (mclk_ps >= 750) + cwl = 12; + else { + cwl = 12; + printf("Warning: CWL is out of range\n"); + } + return cwl; +} +#endif + +/* Chip Select Configuration (CSn_CONFIG) */ +static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const dimm_params_t *dimm_params) +{ + unsigned int cs_n_en = 0; /* Chip Select enable */ + unsigned int intlv_en = 0; /* Memory controller interleave enable */ + unsigned int intlv_ctl = 0; /* Interleaving control */ + unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ + unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ + unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ + unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ + unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ + unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ + int go_config = 0; +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */ +#else + unsigned int n_banks_per_sdram_device; +#endif + + /* Compute CS_CONFIG only for existing ranks of each DIMM. */ + switch (i) { + case 0: + if (dimm_params[dimm_number].n_ranks > 0) { + go_config = 1; + /* These fields only available in CS0_CONFIG */ + if (!popts->memctl_interleaving) + break; + switch (popts->memctl_interleaving_mode) { + case FSL_DDR_256B_INTERLEAVING: + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + intlv_en = popts->memctl_interleaving; + intlv_ctl = popts->memctl_interleaving_mode; + break; + default: + break; + } + } + break; + case 1: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ + (dimm_number == 1 && dimm_params[1].n_ranks > 0)) + go_config = 1; + break; + case 2: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ + (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) + go_config = 1; + break; + case 3: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ + (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ + (dimm_number == 3 && dimm_params[3].n_ranks > 0)) + go_config = 1; + break; + default: + break; + } + if (go_config) { + cs_n_en = 1; + ap_n_en = popts->cs_local_opts[i].auto_precharge; + odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; + odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; +#ifdef CONFIG_SYS_FSL_DDR4 + ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits; + bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits; +#else + n_banks_per_sdram_device + = dimm_params[dimm_number].n_banks_per_sdram_device; + ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; +#endif + row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; + col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; + } + ddr->cs[i].config = (0 + | ((cs_n_en & 0x1) << 31) + | ((intlv_en & 0x3) << 29) + | ((intlv_ctl & 0xf) << 24) + | ((ap_n_en & 0x1) << 23) + + /* XXX: some implementation only have 1 bit starting at left */ + | ((odt_rd_cfg & 0x7) << 20) + + /* XXX: Some implementation only have 1 bit starting at left */ + | ((odt_wr_cfg & 0x7) << 16) + + | ((ba_bits_cs_n & 0x3) << 14) + | ((row_bits_cs_n & 0x7) << 8) +#ifdef CONFIG_SYS_FSL_DDR4 + | ((bg_bits_cs_n & 0x3) << 4) +#endif + | ((col_bits_cs_n & 0x7) << 0) + ); + debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); +} + +/* Chip Select Configuration 2 (CSn_CONFIG_2) */ +/* FIXME: 8572 */ +static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int pasr_cfg = 0; /* Partial array self refresh config */ + + ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); + debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); +} + +/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ + +#if !defined(CONFIG_SYS_FSL_DDR1) +/* + * Check DIMM configuration, return 2 if quad-rank or two dual-rank + * Return 1 if other two slots configuration. Return 0 if single slot. + */ +static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) +{ +#if CONFIG_DIMM_SLOTS_PER_CTLR == 1 + if (dimm_params[0].n_ranks == 4) + return 2; +#endif + +#if CONFIG_DIMM_SLOTS_PER_CTLR == 2 + if ((dimm_params[0].n_ranks == 2) && + (dimm_params[1].n_ranks == 2)) + return 2; + +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (dimm_params[0].n_ranks == 4) + return 2; +#endif + + if ((dimm_params[0].n_ranks != 0) && + (dimm_params[2].n_ranks != 0)) + return 1; +#endif + return 0; +} + +/* + * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) + * + * Avoid writing for DDR I. The new PQ38 DDR controller + * dreams up non-zero default values to be backwards compatible. + */ +static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const dimm_params_t *dimm_params) +{ + unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ + unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ + /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ + unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ + unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ + + /* Active powerdown exit timing (tXARD and tXARDS). */ + unsigned char act_pd_exit_mclk; + /* Precharge powerdown exit timing (tXP). */ + unsigned char pre_pd_exit_mclk; + /* ODT powerdown exit timing (tAXPD). */ + unsigned char taxpd_mclk = 0; + /* Mode register set cycle time (tMRD). */ + unsigned char tmrd_mclk; +#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) + const unsigned int mclk_ps = get_memory_clk_period_ps(); +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 + /* tXP=max(4nCK, 6ns) */ + int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ + trwt_mclk = 2; + twrt_mclk = 1; + act_pd_exit_mclk = picos_to_mclk(txp); + pre_pd_exit_mclk = act_pd_exit_mclk; + /* + * MRS_CYC = max(tMRD, tMOD) + * tMRD = 8nCK, tMOD = max(24nCK, 15ns) + */ + tmrd_mclk = max(24U, picos_to_mclk(15000)); +#elif defined(CONFIG_SYS_FSL_DDR3) + unsigned int data_rate = get_ddr_freq(0); + int txp; + unsigned int ip_rev; + int odt_overlap; + /* + * (tXARD and tXARDS). Empirical? + * The DDR3 spec has not tXARD, + * we use the tXP instead of it. + * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066 + * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133 + * spec has not the tAXPD, we use + * tAXPD=1, need design to confirm. + */ + txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); + + ip_rev = fsl_ddr_get_version(); + if (ip_rev >= 0x40700) { + /* + * MRS_CYC = max(tMRD, tMOD) + * tMRD = 4nCK (8nCK for RDIMM) + * tMOD = max(12nCK, 15ns) + */ + tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000)); + } else { + /* + * MRS_CYC = tMRD + * tMRD = 4nCK (8nCK for RDIMM) + */ + if (popts->registered_dimm_en) + tmrd_mclk = 8; + else + tmrd_mclk = 4; + } + + /* set the turnaround time */ + + /* + * for single quad-rank DIMM and two-slot DIMMs + * to avoid ODT overlap + */ + odt_overlap = avoid_odt_overlap(dimm_params); + switch (odt_overlap) { + case 2: + twwt_mclk = 2; + trrt_mclk = 1; + break; + case 1: + twwt_mclk = 1; + trrt_mclk = 0; + break; + default: + break; + } + + /* for faster clock, need more time for data setup */ + trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; + + if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) + twrt_mclk = 1; + + if (popts->dynamic_power == 0) { /* powerdown is not used */ + act_pd_exit_mclk = 1; + pre_pd_exit_mclk = 1; + taxpd_mclk = 1; + } else { + /* act_pd_exit_mclk = tXARD, see above */ + act_pd_exit_mclk = picos_to_mclk(txp); + /* Mode register MR0[A12] is '1' - fast exit */ + pre_pd_exit_mclk = act_pd_exit_mclk; + taxpd_mclk = 1; + } +#else /* CONFIG_SYS_FSL_DDR2 */ + /* + * (tXARD and tXARDS). Empirical? + * tXARD = 2 for DDR2 + * tXP=2 + * tAXPD=8 + */ + act_pd_exit_mclk = 2; + pre_pd_exit_mclk = 2; + taxpd_mclk = 8; + tmrd_mclk = 2; +#endif + + if (popts->trwt_override) + trwt_mclk = popts->trwt; + + ddr->timing_cfg_0 = (0 + | ((trwt_mclk & 0x3) << 30) /* RWT */ + | ((twrt_mclk & 0x3) << 28) /* WRT */ + | ((trrt_mclk & 0x3) << 26) /* RRT */ + | ((twwt_mclk & 0x3) << 24) /* WWT */ + | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */ + | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ + | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ + | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */ + ); + debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); +} +#endif /* !defined(CONFIG_SYS_FSL_DDR1) */ + +/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ +static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) +{ + /* Extended precharge to activate interval (tRP) */ + unsigned int ext_pretoact = 0; + /* Extended Activate to precharge interval (tRAS) */ + unsigned int ext_acttopre = 0; + /* Extended activate to read/write interval (tRCD) */ + unsigned int ext_acttorw = 0; + /* Extended refresh recovery time (tRFC) */ + unsigned int ext_refrec; + /* Extended MCAS latency from READ cmd */ + unsigned int ext_caslat = 0; + /* Extended additive latency */ + unsigned int ext_add_lat = 0; + /* Extended last data to precharge interval (tWR) */ + unsigned int ext_wrrec = 0; + /* Control Adjust */ + unsigned int cntl_adj = 0; + + ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4; + ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; + ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; + ext_caslat = (2 * cas_latency - 1) >> 4; + ext_add_lat = additive_latency >> 4; +#ifdef CONFIG_SYS_FSL_DDR4 + ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4; +#else + ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; + /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ +#endif + ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + + (popts->otf_burst_chop_en ? 2 : 0)) >> 4; + + ddr->timing_cfg_3 = (0 + | ((ext_pretoact & 0x1) << 28) + | ((ext_acttopre & 0x3) << 24) + | ((ext_acttorw & 0x1) << 22) + | ((ext_refrec & 0x1F) << 16) + | ((ext_caslat & 0x3) << 12) + | ((ext_add_lat & 0x1) << 10) + | ((ext_wrrec & 0x1) << 8) + | ((cntl_adj & 0x7) << 0) + ); + debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); +} + +/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ +static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) +{ + /* Precharge-to-activate interval (tRP) */ + unsigned char pretoact_mclk; + /* Activate to precharge interval (tRAS) */ + unsigned char acttopre_mclk; + /* Activate to read/write interval (tRCD) */ + unsigned char acttorw_mclk; + /* CASLAT */ + unsigned char caslat_ctrl; + /* Refresh recovery time (tRFC) ; trfc_low */ + unsigned char refrec_ctrl; + /* Last data to precharge minimum interval (tWR) */ + unsigned char wrrec_mclk; + /* Activate-to-activate interval (tRRD) */ + unsigned char acttoact_mclk; + /* Last write data pair to read command issue interval (tWTR) */ + unsigned char wrtord_mclk; +#ifdef CONFIG_SYS_FSL_DDR4 + /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */ + static const u8 wrrec_table[] = { + 10, 10, 10, 10, 10, + 10, 10, 10, 10, 10, + 12, 12, 14, 14, 16, + 16, 18, 18, 20, 20, + 24, 24, 24, 24}; +#else + /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ + static const u8 wrrec_table[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; +#endif + + pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); + acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); + acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps); + + /* + * Translate CAS Latency to a DDR controller field value: + * + * CAS Lat DDR I DDR II Ctrl + * Clocks SPD Bit SPD Bit Value + * ------- ------- ------- ----- + * 1.0 0 0001 + * 1.5 1 0010 + * 2.0 2 2 0011 + * 2.5 3 0100 + * 3.0 4 3 0101 + * 3.5 5 0110 + * 4.0 4 0111 + * 4.5 1000 + * 5.0 5 1001 + */ +#if defined(CONFIG_SYS_FSL_DDR1) + caslat_ctrl = (cas_latency + 1) & 0x07; +#elif defined(CONFIG_SYS_FSL_DDR2) + caslat_ctrl = 2 * cas_latency - 1; +#else + /* + * if the CAS latency more than 8 cycle, + * we need set extend bit for it at + * TIMING_CFG_3[EXT_CASLAT] + */ + if (fsl_ddr_get_version() <= 0x40400) + caslat_ctrl = 2 * cas_latency - 1; + else + caslat_ctrl = (cas_latency - 1) << 1; +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 + refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8; + wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); + acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U); + wrtord_mclk = max(2U, picos_to_mclk(2500)); + if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) + printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); + else + wrrec_mclk = wrrec_table[wrrec_mclk - 1]; +#else + refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; + wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); + acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); + wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); + if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) + printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); + else + wrrec_mclk = wrrec_table[wrrec_mclk - 1]; +#endif + if (popts->otf_burst_chop_en) + wrrec_mclk += 2; + + /* + * JEDEC has min requirement for tRRD + */ +#if defined(CONFIG_SYS_FSL_DDR3) + if (acttoact_mclk < 4) + acttoact_mclk = 4; +#endif + /* + * JEDEC has some min requirements for tWTR + */ +#if defined(CONFIG_SYS_FSL_DDR2) + if (wrtord_mclk < 2) + wrtord_mclk = 2; +#elif defined(CONFIG_SYS_FSL_DDR3) + if (wrtord_mclk < 4) + wrtord_mclk = 4; +#endif + if (popts->otf_burst_chop_en) + wrtord_mclk += 2; + + ddr->timing_cfg_1 = (0 + | ((pretoact_mclk & 0x0F) << 28) + | ((acttopre_mclk & 0x0F) << 24) + | ((acttorw_mclk & 0xF) << 20) + | ((caslat_ctrl & 0xF) << 16) + | ((refrec_ctrl & 0xF) << 12) + | ((wrrec_mclk & 0x0F) << 8) + | ((acttoact_mclk & 0x0F) << 4) + | ((wrtord_mclk & 0x0F) << 0) + ); + debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); +} + +/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ +static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) +{ + /* Additive latency */ + unsigned char add_lat_mclk; + /* CAS-to-preamble override */ + unsigned short cpo; + /* Write latency */ + unsigned char wr_lat; + /* Read to precharge (tRTP) */ + unsigned char rd_to_pre; + /* Write command to write data strobe timing adjustment */ + unsigned char wr_data_delay; + /* Minimum CKE pulse width (tCKE) */ + unsigned char cke_pls; + /* Window for four activates (tFAW) */ + unsigned short four_act; +#ifdef CONFIG_SYS_FSL_DDR3 + const unsigned int mclk_ps = get_memory_clk_period_ps(); +#endif + + /* FIXME add check that this must be less than acttorw_mclk */ + add_lat_mclk = additive_latency; + cpo = popts->cpo_override; + +#if defined(CONFIG_SYS_FSL_DDR1) + /* + * This is a lie. It should really be 1, but if it is + * set to 1, bits overlap into the old controller's + * otherwise unused ACSM field. If we leave it 0, then + * the HW will magically treat it as 1 for DDR 1. Oh Yea. + */ + wr_lat = 0; +#elif defined(CONFIG_SYS_FSL_DDR2) + wr_lat = cas_latency - 1; +#else + wr_lat = compute_cas_write_latency(); +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 + rd_to_pre = picos_to_mclk(7500); +#else + rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); +#endif + /* + * JEDEC has some min requirements for tRTP + */ +#if defined(CONFIG_SYS_FSL_DDR2) + if (rd_to_pre < 2) + rd_to_pre = 2; +#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + if (rd_to_pre < 4) + rd_to_pre = 4; +#endif + if (popts->otf_burst_chop_en) + rd_to_pre += 2; /* according to UM */ + + wr_data_delay = popts->write_data_delay; +#ifdef CONFIG_SYS_FSL_DDR4 + cpo = 0; + cke_pls = max(3U, picos_to_mclk(5000)); +#elif defined(CONFIG_SYS_FSL_DDR3) + /* + * cke pulse = max(3nCK, 7.5ns) for DDR3-800 + * max(3nCK, 5.625ns) for DDR3-1066, 1333 + * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 + */ + cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 : + (mclk_ps > 1245 ? 5625 : 5000))); +#else + cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; +#endif + four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); + + ddr->timing_cfg_2 = (0 + | ((add_lat_mclk & 0xf) << 28) + | ((cpo & 0x1f) << 23) + | ((wr_lat & 0xf) << 19) + | ((wr_lat & 0x10) << 14) + | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) + | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) + | ((cke_pls & 0x7) << 6) + | ((four_act & 0x3f) << 0) + ); + debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); +} + +/* DDR SDRAM Register Control Word */ +static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) +{ + if (common_dimm->all_dimms_registered && + !common_dimm->all_dimms_unbuffered) { + if (popts->rcw_override) { + ddr->ddr_sdram_rcw_1 = popts->rcw_1; + ddr->ddr_sdram_rcw_2 = popts->rcw_2; + } else { + ddr->ddr_sdram_rcw_1 = + common_dimm->rcw[0] << 28 | \ + common_dimm->rcw[1] << 24 | \ + common_dimm->rcw[2] << 20 | \ + common_dimm->rcw[3] << 16 | \ + common_dimm->rcw[4] << 12 | \ + common_dimm->rcw[5] << 8 | \ + common_dimm->rcw[6] << 4 | \ + common_dimm->rcw[7]; + ddr->ddr_sdram_rcw_2 = + common_dimm->rcw[8] << 28 | \ + common_dimm->rcw[9] << 24 | \ + common_dimm->rcw[10] << 20 | \ + common_dimm->rcw[11] << 16 | \ + common_dimm->rcw[12] << 12 | \ + common_dimm->rcw[13] << 8 | \ + common_dimm->rcw[14] << 4 | \ + common_dimm->rcw[15]; + } + debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); + debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); + } +} + +/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ +static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) +{ + unsigned int mem_en; /* DDR SDRAM interface logic enable */ + unsigned int sren; /* Self refresh enable (during sleep) */ + unsigned int ecc_en; /* ECC enable. */ + unsigned int rd_en; /* Registered DIMM enable */ + unsigned int sdram_type; /* Type of SDRAM */ + unsigned int dyn_pwr; /* Dynamic power management mode */ + unsigned int dbw; /* DRAM dta bus width */ + unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ + unsigned int ncap = 0; /* Non-concurrent auto-precharge */ + unsigned int threet_en; /* Enable 3T timing */ + unsigned int twot_en; /* Enable 2T timing */ + unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ + unsigned int x32_en = 0; /* x32 enable */ + unsigned int pchb8 = 0; /* precharge bit 8 enable */ + unsigned int hse; /* Global half strength override */ + unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */ + unsigned int mem_halt = 0; /* memory controller halt */ + unsigned int bi = 0; /* Bypass initialization */ + + mem_en = 1; + sren = popts->self_refresh_in_sleep; + if (common_dimm->all_dimms_ecc_capable) { + /* Allow setting of ECC only if all DIMMs are ECC. */ + ecc_en = popts->ecc_mode; + } else { + ecc_en = 0; + } + + if (common_dimm->all_dimms_registered && + !common_dimm->all_dimms_unbuffered) { + rd_en = 1; + twot_en = 0; + } else { + rd_en = 0; + twot_en = popts->twot_en; + } + + sdram_type = CONFIG_FSL_SDRAM_TYPE; + + dyn_pwr = popts->dynamic_power; + dbw = popts->data_bus_width; + /* 8-beat burst enable DDR-III case + * we must clear it when use the on-the-fly mode, + * must set it when use the 32-bits bus mode. + */ + if ((sdram_type == SDRAM_TYPE_DDR3) || + (sdram_type == SDRAM_TYPE_DDR4)) { + if (popts->burst_length == DDR_BL8) + eight_be = 1; + if (popts->burst_length == DDR_OTF) + eight_be = 0; + if (dbw == 0x1) + eight_be = 1; + } + + threet_en = popts->threet_en; + ba_intlv_ctl = popts->ba_intlv_ctl; + hse = popts->half_strength_driver_enable; + + /* set when ddr bus width < 64 */ + acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0; + + ddr->ddr_sdram_cfg = (0 + | ((mem_en & 0x1) << 31) + | ((sren & 0x1) << 30) + | ((ecc_en & 0x1) << 29) + | ((rd_en & 0x1) << 28) + | ((sdram_type & 0x7) << 24) + | ((dyn_pwr & 0x1) << 21) + | ((dbw & 0x3) << 19) + | ((eight_be & 0x1) << 18) + | ((ncap & 0x1) << 17) + | ((threet_en & 0x1) << 16) + | ((twot_en & 0x1) << 15) + | ((ba_intlv_ctl & 0x7F) << 8) + | ((x32_en & 0x1) << 5) + | ((pchb8 & 0x1) << 4) + | ((hse & 0x1) << 3) + | ((acc_ecc_en & 0x1) << 2) + | ((mem_halt & 0x1) << 1) + | ((bi & 0x1) << 0) + ); + debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); +} + +/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ +static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const unsigned int unq_mrs_en) +{ + unsigned int frc_sr = 0; /* Force self refresh */ + unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ + unsigned int odt_cfg = 0; /* ODT configuration */ + unsigned int num_pr; /* Number of posted refreshes */ + unsigned int slow = 0; /* DDR will be run less than 1250 */ + unsigned int x4_en = 0; /* x4 DRAM enable */ + unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ + unsigned int ap_en; /* Address Parity Enable */ + unsigned int d_init; /* DRAM data initialization */ + unsigned int rcw_en = 0; /* Register Control Word Enable */ + unsigned int md_en = 0; /* Mirrored DIMM Enable */ + unsigned int qd_en = 0; /* quad-rank DIMM Enable */ + int i; +#ifndef CONFIG_SYS_FSL_DDR4 + unsigned int dll_rst_dis = 1; /* DLL reset disable */ + unsigned int dqs_cfg; /* DQS configuration */ + + dqs_cfg = popts->dqs_config; +#endif + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->cs_local_opts[i].odt_rd_cfg + || popts->cs_local_opts[i].odt_wr_cfg) { + odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; + break; + } + } + + num_pr = 1; /* Make this configurable */ + + /* + * 8572 manual says + * {TIMING_CFG_1[PRETOACT] + * + [DDR_SDRAM_CFG_2[NUM_PR] + * * ({EXT_REFREC || REFREC} + 8 + 2)]} + * << DDR_SDRAM_INTERVAL[REFINT] + */ +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + obc_cfg = popts->otf_burst_chop_en; +#else + obc_cfg = 0; +#endif + +#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) + slow = get_ddr_freq(0) < 1249000000; +#endif + + if (popts->registered_dimm_en) { + rcw_en = 1; + ap_en = popts->ap_en; + } else { + ap_en = 0; + } + + x4_en = popts->x4_en ? 1 : 0; + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Use the DDR controller to auto initialize memory. */ + d_init = popts->ecc_init_using_memctl; + ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); +#else + /* Memory will be initialized via DMA, or not at all. */ + d_init = 0; +#endif + +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + md_en = popts->mirrored_dimm; +#endif + qd_en = popts->quad_rank_present ? 1 : 0; + ddr->ddr_sdram_cfg_2 = (0 + | ((frc_sr & 0x1) << 31) + | ((sr_ie & 0x1) << 30) +#ifndef CONFIG_SYS_FSL_DDR4 + | ((dll_rst_dis & 0x1) << 29) + | ((dqs_cfg & 0x3) << 26) +#endif + | ((odt_cfg & 0x3) << 21) + | ((num_pr & 0xf) << 12) + | ((slow & 1) << 11) + | (x4_en << 10) + | (qd_en << 9) + | (unq_mrs_en << 8) + | ((obc_cfg & 0x1) << 6) + | ((ap_en & 0x1) << 5) + | ((d_init & 0x1) << 4) + | ((rcw_en & 0x1) << 2) + | ((md_en & 0x1) << 0) + ); + debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); +} + +#ifdef CONFIG_SYS_FSL_DDR4 +/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ + unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ + int i; + unsigned int wr_crc = 0; /* Disable */ + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ + unsigned int srt = 0; /* self-refresh temerature, normal range */ + unsigned int cwl = compute_cas_write_latency() - 9; + unsigned int mpr = 0; /* serial */ + unsigned int wc_lat; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; + + if (common_dimm->extended_op_srt) + srt = common_dimm->extended_op_srt; + + esdmode2 = (0 + | ((wr_crc & 0x1) << 12) + | ((rtt_wr & 0x3) << 9) + | ((srt & 0x3) << 6) + | ((cwl & 0x7) << 3)); + + if (mclk_ps >= 1250) + wc_lat = 0; + else if (mclk_ps >= 833) + wc_lat = 1; + else + wc_lat = 2; + + esdmode3 = (0 + | ((mpr & 0x3) << 11) + | ((wc_lat & 0x3) << 9)); + + ddr->ddr_sdram_mode_2 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; + + esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ + esdmode2 |= (rtt_wr & 0x3) << 9; + switch (i) { + case 1: + ddr->ddr_sdram_mode_4 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_6 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_8 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", + ddr->ddr_sdram_mode_4); + debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", + ddr->ddr_sdram_mode_6); + debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", + ddr->ddr_sdram_mode_8); + } +} +#elif defined(CONFIG_SYS_FSL_DDR3) +/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ + unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ + int i; + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ + unsigned int srt = 0; /* self-refresh temerature, normal range */ + unsigned int asr = 0; /* auto self-refresh disable */ + unsigned int cwl = compute_cas_write_latency() - 5; + unsigned int pasr = 0; /* partial array self refresh disable */ + + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; + + if (common_dimm->extended_op_srt) + srt = common_dimm->extended_op_srt; + + esdmode2 = (0 + | ((rtt_wr & 0x3) << 9) + | ((srt & 0x1) << 7) + | ((asr & 0x1) << 6) + | ((cwl & 0x7) << 3) + | ((pasr & 0x7) << 0)); + ddr->ddr_sdram_mode_2 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; + + esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ + esdmode2 |= (rtt_wr & 0x3) << 9; + switch (i) { + case 1: + ddr->ddr_sdram_mode_4 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_6 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_8 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", + ddr->ddr_sdram_mode_4); + debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", + ddr->ddr_sdram_mode_6); + debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", + ddr->ddr_sdram_mode_8); + } +} + +#else /* for DDR2 and DDR1 */ +/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ + unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ + + ddr->ddr_sdram_mode_2 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); +} +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 +/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */ +static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + int i; + unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ + unsigned short esdmode5; /* Extended SDRAM mode 5 */ + + esdmode5 = 0x00000400; /* Data mask enabled */ + + ddr->ddr_sdram_mode_9 = (0 + | ((esdmode4 & 0xffff) << 16) + | ((esdmode5 & 0xffff) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9); + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + switch (i) { + case 1: + ddr->ddr_sdram_mode_11 = (0 + | ((esdmode4 & 0xFFFF) << 16) + | ((esdmode5 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_13 = (0 + | ((esdmode4 & 0xFFFF) << 16) + | ((esdmode5 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_15 = (0 + | ((esdmode4 & 0xFFFF) << 16) + | ((esdmode5 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n", + ddr->ddr_sdram_mode_11); + debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n", + ddr->ddr_sdram_mode_13); + debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n", + ddr->ddr_sdram_mode_15); + } +} + +/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */ +static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + int i; + unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ + unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ + unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps); + + esdmode6 = ((tccdl_min - 4) & 0x7) << 10; + + ddr->ddr_sdram_mode_10 = (0 + | ((esdmode6 & 0xffff) << 16) + | ((esdmode7 & 0xffff) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10); + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + switch (i) { + case 1: + ddr->ddr_sdram_mode_12 = (0 + | ((esdmode6 & 0xFFFF) << 16) + | ((esdmode7 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_14 = (0 + | ((esdmode6 & 0xFFFF) << 16) + | ((esdmode7 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_16 = (0 + | ((esdmode6 & 0xFFFF) << 16) + | ((esdmode7 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n", + ddr->ddr_sdram_mode_12); + debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n", + ddr->ddr_sdram_mode_14); + debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n", + ddr->ddr_sdram_mode_16); + } +} + +#endif + +/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ +static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) +{ + unsigned int refint; /* Refresh interval */ + unsigned int bstopre; /* Precharge interval */ + + refint = picos_to_mclk(common_dimm->refresh_rate_ps); + + bstopre = popts->bstopre; + + /* refint field used 0x3FFF in earlier controllers */ + ddr->ddr_sdram_interval = (0 + | ((refint & 0xFFFF) << 16) + | ((bstopre & 0x3FFF) << 0) + ); + debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); +} + +#ifdef CONFIG_SYS_FSL_DDR4 +/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ +static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency, + const unsigned int unq_mrs_en) +{ + int i; + unsigned short esdmode; /* Extended SDRAM mode */ + unsigned short sdmode; /* SDRAM mode */ + + /* Mode Register - MR1 */ + unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ + unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ + unsigned int rtt; + unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ + unsigned int al = 0; /* Posted CAS# additive latency (AL) */ + unsigned int dic = 0; /* Output driver impedance, 40ohm */ + unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal), + 0=Disable (Test/Debug) */ + + /* Mode Register - MR0 */ + unsigned int wr = 0; /* Write Recovery */ + unsigned int dll_rst; /* DLL Reset */ + unsigned int mode; /* Normal=0 or Test=1 */ + unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ + /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ + unsigned int bt; + unsigned int bl; /* BL: Burst Length */ + + unsigned int wr_mclk; + /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */ + static const u8 wr_table[] = { + 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6}; + /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */ + static const u8 cas_latency_table[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, + 9, 9, 10, 10, 11, 11}; + + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[0].odt_rtt_norm; + + if (additive_latency == (cas_latency - 1)) + al = 1; + if (additive_latency == (cas_latency - 2)) + al = 2; + + if (popts->quad_rank_present) + dic = 1; /* output driver impedance 240/7 ohm */ + + /* + * The esdmode value will also be used for writing + * MR1 during write leveling for DDR3, although the + * bits specifically related to the write leveling + * scheme will be handled automatically by the DDR + * controller. so we set the wrlvl_en = 0 here. + */ + esdmode = (0 + | ((qoff & 0x1) << 12) + | ((tdqs_en & 0x1) << 11) + | ((rtt & 0x7) << 8) + | ((wrlvl_en & 0x1) << 7) + | ((al & 0x3) << 3) + | ((dic & 0x3) << 1) /* DIC field is split */ + | ((dll_en & 0x1) << 0) + ); + + /* + * DLL control for precharge PD + * 0=slow exit DLL off (tXPDLL) + * 1=fast exit DLL on (tXP) + */ + + wr_mclk = picos_to_mclk(common_dimm->twr_ps); + if (wr_mclk <= 24) { + wr = wr_table[wr_mclk - 10]; + } else { + printf("Error: unsupported write recovery for mode register wr_mclk = %d\n", + wr_mclk); + } + + dll_rst = 0; /* dll no reset */ + mode = 0; /* normal mode */ + + /* look up table to get the cas latency bits */ + if (cas_latency >= 9 && cas_latency <= 24) + caslat = cas_latency_table[cas_latency - 9]; + else + printf("Error: unsupported cas latency for mode register\n"); + + bt = 0; /* Nibble sequential */ + + switch (popts->burst_length) { + case DDR_BL8: + bl = 0; + break; + case DDR_OTF: + bl = 1; + break; + case DDR_BC4: + bl = 2; + break; + default: + printf("Error: invalid burst length of %u specified. ", + popts->burst_length); + puts("Defaulting to on-the-fly BC4 or BL8 beats.\n"); + bl = 1; + break; + } + + sdmode = (0 + | ((wr & 0x7) << 9) + | ((dll_rst & 0x1) << 8) + | ((mode & 0x1) << 7) + | (((caslat >> 1) & 0x7) << 4) + | ((bt & 0x1) << 3) + | ((caslat & 1) << 2) + | ((bl & 0x3) << 0) + ); + + ddr->ddr_sdram_mode = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[i].odt_rtt_norm; + + esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */ + esdmode |= (rtt & 0x7) << 8; + switch (i) { + case 1: + ddr->ddr_sdram_mode_3 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_5 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_7 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", + ddr->ddr_sdram_mode_3); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + } +} + +#elif defined(CONFIG_SYS_FSL_DDR3) +/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ +static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency, + const unsigned int unq_mrs_en) +{ + int i; + unsigned short esdmode; /* Extended SDRAM mode */ + unsigned short sdmode; /* SDRAM mode */ + + /* Mode Register - MR1 */ + unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ + unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ + unsigned int rtt; + unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ + unsigned int al = 0; /* Posted CAS# additive latency (AL) */ + unsigned int dic = 0; /* Output driver impedance, 40ohm */ + unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), + 1=Disable (Test/Debug) */ + + /* Mode Register - MR0 */ + unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ + unsigned int wr = 0; /* Write Recovery */ + unsigned int dll_rst; /* DLL Reset */ + unsigned int mode; /* Normal=0 or Test=1 */ + unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ + /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ + unsigned int bt; + unsigned int bl; /* BL: Burst Length */ + + unsigned int wr_mclk; + /* + * DDR_SDRAM_MODE doesn't support 9,11,13,15 + * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 + * for this table + */ + static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; + + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[0].odt_rtt_norm; + + if (additive_latency == (cas_latency - 1)) + al = 1; + if (additive_latency == (cas_latency - 2)) + al = 2; + + if (popts->quad_rank_present) + dic = 1; /* output driver impedance 240/7 ohm */ + + /* + * The esdmode value will also be used for writing + * MR1 during write leveling for DDR3, although the + * bits specifically related to the write leveling + * scheme will be handled automatically by the DDR + * controller. so we set the wrlvl_en = 0 here. + */ + esdmode = (0 + | ((qoff & 0x1) << 12) + | ((tdqs_en & 0x1) << 11) + | ((rtt & 0x4) << 7) /* rtt field is split */ + | ((wrlvl_en & 0x1) << 7) + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((dic & 0x2) << 4) /* DIC field is split */ + | ((al & 0x3) << 3) + | ((rtt & 0x1) << 2) /* rtt field is split */ + | ((dic & 0x1) << 1) /* DIC field is split */ + | ((dll_en & 0x1) << 0) + ); + + /* + * DLL control for precharge PD + * 0=slow exit DLL off (tXPDLL) + * 1=fast exit DLL on (tXP) + */ + dll_on = 1; + + wr_mclk = picos_to_mclk(common_dimm->twr_ps); + if (wr_mclk <= 16) { + wr = wr_table[wr_mclk - 5]; + } else { + printf("Error: unsupported write recovery for mode register " + "wr_mclk = %d\n", wr_mclk); + } + + dll_rst = 0; /* dll no reset */ + mode = 0; /* normal mode */ + + /* look up table to get the cas latency bits */ + if (cas_latency >= 5 && cas_latency <= 16) { + unsigned char cas_latency_table[] = { + 0x2, /* 5 clocks */ + 0x4, /* 6 clocks */ + 0x6, /* 7 clocks */ + 0x8, /* 8 clocks */ + 0xa, /* 9 clocks */ + 0xc, /* 10 clocks */ + 0xe, /* 11 clocks */ + 0x1, /* 12 clocks */ + 0x3, /* 13 clocks */ + 0x5, /* 14 clocks */ + 0x7, /* 15 clocks */ + 0x9, /* 16 clocks */ + }; + caslat = cas_latency_table[cas_latency - 5]; + } else { + printf("Error: unsupported cas latency for mode register\n"); + } + + bt = 0; /* Nibble sequential */ + + switch (popts->burst_length) { + case DDR_BL8: + bl = 0; + break; + case DDR_OTF: + bl = 1; + break; + case DDR_BC4: + bl = 2; + break; + default: + printf("Error: invalid burst length of %u specified. " + " Defaulting to on-the-fly BC4 or BL8 beats.\n", + popts->burst_length); + bl = 1; + break; + } + + sdmode = (0 + | ((dll_on & 0x1) << 12) + | ((wr & 0x7) << 9) + | ((dll_rst & 0x1) << 8) + | ((mode & 0x1) << 7) + | (((caslat >> 1) & 0x7) << 4) + | ((bt & 0x1) << 3) + | ((caslat & 1) << 2) + | ((bl & 0x3) << 0) + ); + + ddr->ddr_sdram_mode = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[i].odt_rtt_norm; + + esdmode &= 0xFDBB; /* clear bit 9,6,2 */ + esdmode |= (0 + | ((rtt & 0x4) << 7) /* rtt field is split */ + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((rtt & 0x1) << 2) /* rtt field is split */ + ); + switch (i) { + case 1: + ddr->ddr_sdram_mode_3 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_5 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_7 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", + ddr->ddr_sdram_mode_3); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + } +} + +#else /* !CONFIG_SYS_FSL_DDR3 */ + +/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ +static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode; /* Extended SDRAM mode */ + unsigned short sdmode; /* SDRAM mode */ + + /* + * FIXME: This ought to be pre-calculated in a + * technology-specific routine, + * e.g. compute_DDR2_mode_register(), and then the + * sdmode and esdmode passed in as part of common_dimm. + */ + + /* Extended Mode Register */ + unsigned int mrs = 0; /* Mode Register Set */ + unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ + unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ + unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ + unsigned int ocd = 0; /* 0x0=OCD not supported, + 0x7=OCD default state */ + unsigned int rtt; + unsigned int al; /* Posted CAS# additive latency (AL) */ + unsigned int ods = 0; /* Output Drive Strength: + 0 = Full strength (18ohm) + 1 = Reduced strength (4ohm) */ + unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), + 1=Disable (Test/Debug) */ + + /* Mode Register (MR) */ + unsigned int mr; /* Mode Register Definition */ + unsigned int pd; /* Power-Down Mode */ + unsigned int wr; /* Write Recovery */ + unsigned int dll_res; /* DLL Reset */ + unsigned int mode; /* Normal=0 or Test=1 */ + unsigned int caslat = 0;/* CAS# latency */ + /* BT: Burst Type (0=Sequential, 1=Interleaved) */ + unsigned int bt; + unsigned int bl; /* BL: Burst Length */ + + dqs_en = !popts->dqs_config; + rtt = fsl_ddr_get_rtt(); + + al = additive_latency; + + esdmode = (0 + | ((mrs & 0x3) << 14) + | ((outputs & 0x1) << 12) + | ((rdqs_en & 0x1) << 11) + | ((dqs_en & 0x1) << 10) + | ((ocd & 0x7) << 7) + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((al & 0x7) << 3) + | ((rtt & 0x1) << 2) /* rtt field is split */ + | ((ods & 0x1) << 1) + | ((dll_en & 0x1) << 0) + ); + + mr = 0; /* FIXME: CHECKME */ + + /* + * 0 = Fast Exit (Normal) + * 1 = Slow Exit (Low Power) + */ + pd = 0; + +#if defined(CONFIG_SYS_FSL_DDR1) + wr = 0; /* Historical */ +#elif defined(CONFIG_SYS_FSL_DDR2) + wr = picos_to_mclk(common_dimm->twr_ps); +#endif + dll_res = 0; + mode = 0; + +#if defined(CONFIG_SYS_FSL_DDR1) + if (1 <= cas_latency && cas_latency <= 4) { + unsigned char mode_caslat_table[4] = { + 0x5, /* 1.5 clocks */ + 0x2, /* 2.0 clocks */ + 0x6, /* 2.5 clocks */ + 0x3 /* 3.0 clocks */ + }; + caslat = mode_caslat_table[cas_latency - 1]; + } else { + printf("Warning: unknown cas_latency %d\n", cas_latency); + } +#elif defined(CONFIG_SYS_FSL_DDR2) + caslat = cas_latency; +#endif + bt = 0; + + switch (popts->burst_length) { + case DDR_BL4: + bl = 2; + break; + case DDR_BL8: + bl = 3; + break; + default: + printf("Error: invalid burst length of %u specified. " + " Defaulting to 4 beats.\n", + popts->burst_length); + bl = 2; + break; + } + + sdmode = (0 + | ((mr & 0x3) << 14) + | ((pd & 0x1) << 12) + | ((wr & 0x7) << 9) + | ((dll_res & 0x1) << 8) + | ((mode & 0x1) << 7) + | ((caslat & 0x7) << 4) + | ((bt & 0x1) << 3) + | ((bl & 0x7) << 0) + ); + + ddr->ddr_sdram_mode = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); +} +#endif + +/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ +static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int init_value; /* Initialization value */ + +#ifdef CONFIG_MEM_INIT_VALUE + init_value = CONFIG_MEM_INIT_VALUE; +#else + init_value = 0xDEADBEEF; +#endif + ddr->ddr_data_init = init_value; +} + +/* + * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) + * The old controller on the 8540/60 doesn't have this register. + * Hope it's OK to set it (to 0) anyway. + */ +static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + unsigned int clk_adjust; /* Clock adjust */ + + clk_adjust = popts->clk_adjust; + ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; + debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); +} + +/* DDR Initialization Address (DDR_INIT_ADDR) */ +static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int init_addr = 0; /* Initialization address */ + + ddr->ddr_init_addr = init_addr; +} + +/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ +static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int uia = 0; /* Use initialization address */ + unsigned int init_ext_addr = 0; /* Initialization address */ + + ddr->ddr_init_ext_addr = (0 + | ((uia & 0x1) << 31) + | (init_ext_addr & 0xF) + ); +} + +/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ +static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ + unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ + unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ + unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ + unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ + +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + if (popts->burst_length == DDR_BL8) { + /* We set BL/2 for fixed BL8 */ + rrt = 0; /* BL/2 clocks */ + wwt = 0; /* BL/2 clocks */ + } else { + /* We need to set BL/2 + 2 to BC4 and OTF */ + rrt = 2; /* BL/2 + 2 clocks */ + wwt = 2; /* BL/2 + 2 clocks */ + } +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 + dll_lock = 2; /* tDLLK = 1024 clocks */ +#elif defined(CONFIG_SYS_FSL_DDR3) + dll_lock = 1; /* tDLLK = 512 clocks from spec */ +#endif + ddr->timing_cfg_4 = (0 + | ((rwt & 0xf) << 28) + | ((wrt & 0xf) << 24) + | ((rrt & 0xf) << 20) + | ((wwt & 0xf) << 16) + | (dll_lock & 0x3) + ); + debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); +} + +/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ +static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) +{ + unsigned int rodt_on = 0; /* Read to ODT on */ + unsigned int rodt_off = 0; /* Read to ODT off */ + unsigned int wodt_on = 0; /* Write to ODT on */ + unsigned int wodt_off = 0; /* Write to ODT off */ + +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + + ((ddr->timing_cfg_2 & 0x00040000) >> 14); + /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ + if (cas_latency >= wr_lat) + rodt_on = cas_latency - wr_lat + 1; + rodt_off = 4; /* 4 clocks */ + wodt_on = 1; /* 1 clocks */ + wodt_off = 4; /* 4 clocks */ +#endif + + ddr->timing_cfg_5 = (0 + | ((rodt_on & 0x1f) << 24) + | ((rodt_off & 0x7) << 20) + | ((wodt_on & 0x1f) << 12) + | ((wodt_off & 0x7) << 8) + ); + debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); +} + +#ifdef CONFIG_SYS_FSL_DDR4 +static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int hs_caslat = 0; + unsigned int hs_wrlat = 0; + unsigned int hs_wrrec = 0; + unsigned int hs_clkadj = 0; + unsigned int hs_wrlvl_start = 0; + + ddr->timing_cfg_6 = (0 + | ((hs_caslat & 0x1f) << 24) + | ((hs_wrlat & 0x1f) << 19) + | ((hs_wrrec & 0x1f) << 12) + | ((hs_clkadj & 0x1f) << 6) + | ((hs_wrlvl_start & 0x1f) << 0) + ); + debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); +} + +static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm) +{ + unsigned int txpr, tcksre, tcksrx; + unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; + + txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000)); + tcksre = max(5U, picos_to_mclk(10000)); + tcksrx = max(5U, picos_to_mclk(10000)); + par_lat = 0; + cs_to_cmd = 0; + + if (txpr <= 200) + cke_rst = 0; + else if (txpr <= 256) + cke_rst = 1; + else if (txpr <= 512) + cke_rst = 2; + else + cke_rst = 3; + + if (tcksre <= 19) + cksre = tcksre - 5; + else + cksre = 15; + + if (tcksrx <= 19) + cksrx = tcksrx - 5; + else + cksrx = 15; + + ddr->timing_cfg_7 = (0 + | ((cke_rst & 0x3) << 28) + | ((cksre & 0xf) << 24) + | ((cksrx & 0xf) << 20) + | ((par_lat & 0xf) << 16) + | ((cs_to_cmd & 0xf) << 4) + ); + debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); +} + +static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) +{ + unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg; + unsigned int acttoact_bg, wrtord_bg, pre_all_rec; + unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps); + unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + + ((ddr->timing_cfg_2 & 0x00040000) >> 14); + + rwt_bg = cas_latency + 2 + 4 - wr_lat; + if (rwt_bg < tccdl) + rwt_bg = tccdl - rwt_bg; + else + rwt_bg = 0; + + wrt_bg = wr_lat + 4 + 1 - cas_latency; + if (wrt_bg < tccdl) + wrt_bg = tccdl - wrt_bg; + else + wrt_bg = 0; + + if (popts->burst_length == DDR_BL8) { + rrt_bg = tccdl - 4; + wwt_bg = tccdl - 4; + } else { + rrt_bg = tccdl - 2; + wwt_bg = tccdl - 4; + } + + acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); + wrtord_bg = max(4U, picos_to_mclk(7500)); + if (popts->otf_burst_chop_en) + wrtord_bg += 2; + + pre_all_rec = 0; + + ddr->timing_cfg_8 = (0 + | ((rwt_bg & 0xf) << 28) + | ((wrt_bg & 0xf) << 24) + | ((rrt_bg & 0xf) << 20) + | ((wwt_bg & 0xf) << 16) + | ((acttoact_bg & 0xf) << 12) + | ((wrtord_bg & 0xf) << 8) + | ((pre_all_rec & 0x1f) << 0) + ); + + debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); +} + +static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr) +{ + ddr->timing_cfg_9 = 0; + debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); +} + +/* This function needs to be called after set_ddr_sdram_cfg() is called */ +static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, + const dimm_params_t *dimm_params) +{ + unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; + + ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) | + ((dimm_params->dq_mapping[1] & 0x3F) << 20) | + ((dimm_params->dq_mapping[2] & 0x3F) << 14) | + ((dimm_params->dq_mapping[3] & 0x3F) << 8) | + ((dimm_params->dq_mapping[4] & 0x3F) << 2); + + ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) | + ((dimm_params->dq_mapping[6] & 0x3F) << 20) | + ((dimm_params->dq_mapping[7] & 0x3F) << 14) | + ((dimm_params->dq_mapping[10] & 0x3F) << 8) | + ((dimm_params->dq_mapping[11] & 0x3F) << 2); + + ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) | + ((dimm_params->dq_mapping[13] & 0x3F) << 20) | + ((dimm_params->dq_mapping[14] & 0x3F) << 14) | + ((dimm_params->dq_mapping[15] & 0x3F) << 8) | + ((dimm_params->dq_mapping[16] & 0x3F) << 2); + + /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */ + ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) | + ((dimm_params->dq_mapping[8] & 0x3F) << 20) | + (acc_ecc_en ? 0 : + (dimm_params->dq_mapping[9] & 0x3F) << 14) | + dimm_params->dq_mapping_ors; + + debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); + debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); + debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); + debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); +} +static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + int rd_pre; + + rd_pre = popts->quad_rank_present ? 1 : 0; + + ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; + + debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); +} +#endif /* CONFIG_SYS_FSL_DDR4 */ + +/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ +static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) +{ + unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ + /* Normal Operation Full Calibration Time (tZQoper) */ + unsigned int zqoper = 0; + /* Normal Operation Short Calibration Time (tZQCS) */ + unsigned int zqcs = 0; +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int zqcs_init; +#endif + + if (zq_en) { +#ifdef CONFIG_SYS_FSL_DDR4 + zqinit = 10; /* 1024 clocks */ + zqoper = 9; /* 512 clocks */ + zqcs = 7; /* 128 clocks */ + zqcs_init = 5; /* 1024 refresh sequences */ +#else + zqinit = 9; /* 512 clocks */ + zqoper = 8; /* 256 clocks */ + zqcs = 6; /* 64 clocks */ +#endif + } + + ddr->ddr_zq_cntl = (0 + | ((zq_en & 0x1) << 31) + | ((zqinit & 0xF) << 24) + | ((zqoper & 0xF) << 16) + | ((zqcs & 0xF) << 8) +#ifdef CONFIG_SYS_FSL_DDR4 + | ((zqcs_init & 0xF) << 0) +#endif + ); + debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); +} + +/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ +static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, + const memctl_options_t *popts) +{ + /* + * First DQS pulse rising edge after margining mode + * is programmed (tWL_MRD) + */ + unsigned int wrlvl_mrd = 0; + /* ODT delay after margining mode is programmed (tWL_ODTEN) */ + unsigned int wrlvl_odten = 0; + /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ + unsigned int wrlvl_dqsen = 0; + /* WRLVL_SMPL: Write leveling sample time */ + unsigned int wrlvl_smpl = 0; + /* WRLVL_WLR: Write leveling repeition time */ + unsigned int wrlvl_wlr = 0; + /* WRLVL_START: Write leveling start time */ + unsigned int wrlvl_start = 0; + + /* suggest enable write leveling for DDR3 due to fly-by topology */ + if (wrlvl_en) { + /* tWL_MRD min = 40 nCK, we set it 64 */ + wrlvl_mrd = 0x6; + /* tWL_ODTEN 128 */ + wrlvl_odten = 0x7; + /* tWL_DQSEN min = 25 nCK, we set it 32 */ + wrlvl_dqsen = 0x5; + /* + * Write leveling sample time at least need 6 clocks + * higher than tWLO to allow enough time for progagation + * delay and sampling the prime data bits. + */ + wrlvl_smpl = 0xf; + /* + * Write leveling repetition time + * at least tWLO + 6 clocks clocks + * we set it 64 + */ + wrlvl_wlr = 0x6; + /* + * Write leveling start time + * The value use for the DQS_ADJUST for the first sample + * when write leveling is enabled. It probably needs to be + * overriden per platform. + */ + wrlvl_start = 0x8; + /* + * Override the write leveling sample and start time + * according to specific board + */ + if (popts->wrlvl_override) { + wrlvl_smpl = popts->wrlvl_sample; + wrlvl_start = popts->wrlvl_start; + } + } + + ddr->ddr_wrlvl_cntl = (0 + | ((wrlvl_en & 0x1) << 31) + | ((wrlvl_mrd & 0x7) << 24) + | ((wrlvl_odten & 0x7) << 20) + | ((wrlvl_dqsen & 0x7) << 16) + | ((wrlvl_smpl & 0xf) << 12) + | ((wrlvl_wlr & 0x7) << 8) + | ((wrlvl_start & 0x1F) << 0) + ); + debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); + ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; + debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); + ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; + debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); + +} + +/* DDR Self Refresh Counter (DDR_SR_CNTR) */ +static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) +{ + /* Self Refresh Idle Threshold */ + ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; +} + +static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + if (popts->addr_hash) { + ddr->ddr_eor = 0x40000000; /* address hash enable */ + puts("Address hashing enabled.\n"); + } +} + +static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + ddr->ddr_cdr1 = popts->ddr_cdr1; + debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); +} + +static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + ddr->ddr_cdr2 = popts->ddr_cdr2; + debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); +} + +unsigned int +check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int res = 0; + + /* + * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are + * not set at the same time. + */ + if (ddr->ddr_sdram_cfg & 0x10000000 + && ddr->ddr_sdram_cfg & 0x00008000) { + printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " + " should not be set at the same time.\n"); + res++; + } + + return res; +} + +unsigned int +compute_fsl_memctl_config_regs(const memctl_options_t *popts, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm, + const dimm_params_t *dimm_params, + unsigned int dbw_cap_adj, + unsigned int size_only) +{ + unsigned int i; + unsigned int cas_latency; + unsigned int additive_latency; + unsigned int sr_it; + unsigned int zq_en; + unsigned int wrlvl_en; + unsigned int ip_rev = 0; + unsigned int unq_mrs_en = 0; + int cs_en = 1; + + memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); + + if (common_dimm == NULL) { + printf("Error: subset DIMM params struct null pointer\n"); + return 1; + } + + /* + * Process overrides first. + * + * FIXME: somehow add dereated caslat to this + */ + cas_latency = (popts->cas_latency_override) + ? popts->cas_latency_override_value + : common_dimm->lowest_common_spd_caslat; + + additive_latency = (popts->additive_latency_override) + ? popts->additive_latency_override_value + : common_dimm->additive_latency; + + sr_it = (popts->auto_self_refresh_en) + ? popts->sr_it + : 0; + /* ZQ calibration */ + zq_en = (popts->zq_en) ? 1 : 0; + /* write leveling */ + wrlvl_en = (popts->wrlvl_en) ? 1 : 0; + + /* Chip Select Memory Bounds (CSn_BNDS) */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + unsigned long long ea, sa; + unsigned int cs_per_dimm + = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; + unsigned int dimm_number + = i / cs_per_dimm; + unsigned long long rank_density + = dimm_params[dimm_number].rank_density >> dbw_cap_adj; + + if (dimm_params[dimm_number].n_ranks == 0) { + debug("Skipping setup of CS%u " + "because n_ranks on DIMM %u is 0\n", i, dimm_number); + continue; + } + if (popts->memctl_interleaving) { + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + break; + case FSL_DDR_CS0_CS1: + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + if (i > 1) + cs_en = 0; + break; + case FSL_DDR_CS2_CS3: + default: + if (i > 0) + cs_en = 0; + break; + } + sa = common_dimm->base_address; + ea = sa + common_dimm->total_mem - 1; + } else if (!popts->memctl_interleaving) { + /* + * If memory interleaving between controllers is NOT + * enabled, the starting address for each memory + * controller is distinct. However, because rank + * interleaving is enabled, the starting and ending + * addresses of the total memory on that memory + * controller needs to be programmed into its + * respective CS0_BNDS. + */ + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + sa = common_dimm->base_address; + ea = sa + common_dimm->total_mem - 1; + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + if ((i >= 2) && (dimm_number == 0)) { + sa = dimm_params[dimm_number].base_address + + 2 * rank_density; + ea = sa + 2 * rank_density - 1; + } else { + sa = dimm_params[dimm_number].base_address; + ea = sa + 2 * rank_density - 1; + } + break; + case FSL_DDR_CS0_CS1: + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa = dimm_params[dimm_number].base_address; + ea = sa + rank_density - 1; + if (i != 1) + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; + } else { + sa = 0; + ea = 0; + } + if (i == 0) + ea += rank_density; + break; + case FSL_DDR_CS2_CS3: + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa = dimm_params[dimm_number].base_address; + ea = sa + rank_density - 1; + if (i != 3) + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; + } else { + sa = 0; + ea = 0; + } + if (i == 2) + ea += (rank_density >> dbw_cap_adj); + break; + default: /* No bank(chip-select) interleaving */ + sa = dimm_params[dimm_number].base_address; + ea = sa + rank_density - 1; + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; + } else { + sa = 0; + ea = 0; + } + break; + } + } + + sa >>= 24; + ea >>= 24; + + if (cs_en) { + ddr->cs[i].bnds = (0 + | ((sa & 0xffff) << 16) /* starting address */ + | ((ea & 0xffff) << 0) /* ending address */ + ); + } else { + /* setting bnds to 0xffffffff for inactive CS */ + ddr->cs[i].bnds = 0xffffffff; + } + + debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); + set_csn_config(dimm_number, i, ddr, popts, dimm_params); + set_csn_config_2(i, ddr); + } + + /* + * In the case we only need to compute the ddr sdram size, we only need + * to set csn registers, so return from here. + */ + if (size_only) + return 0; + + set_ddr_eor(ddr, popts); + +#if !defined(CONFIG_SYS_FSL_DDR1) + set_timing_cfg_0(ddr, popts, dimm_params); +#endif + + set_timing_cfg_3(ddr, popts, common_dimm, cas_latency, + additive_latency); + set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_2(ddr, popts, common_dimm, + cas_latency, additive_latency); + + set_ddr_cdr1(ddr, popts); + set_ddr_cdr2(ddr, popts); + set_ddr_sdram_cfg(ddr, popts, common_dimm); + ip_rev = fsl_ddr_get_version(); + if (ip_rev > 0x40400) + unq_mrs_en = 1; + + if ((ip_rev > 0x40700) && (popts->cswl_override != 0)) + ddr->debug[18] = popts->cswl_override; + + set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); + set_ddr_sdram_mode(ddr, popts, common_dimm, + cas_latency, additive_latency, unq_mrs_en); + set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); +#ifdef CONFIG_SYS_FSL_DDR4 + set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); + set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en); +#endif + set_ddr_sdram_interval(ddr, popts, common_dimm); + set_ddr_data_init(ddr); + set_ddr_sdram_clk_cntl(ddr, popts); + set_ddr_init_addr(ddr); + set_ddr_init_ext_addr(ddr); + set_timing_cfg_4(ddr, popts); + set_timing_cfg_5(ddr, cas_latency); +#ifdef CONFIG_SYS_FSL_DDR4 + set_ddr_sdram_cfg_3(ddr, popts); + set_timing_cfg_6(ddr); + set_timing_cfg_7(ddr, common_dimm); + set_timing_cfg_8(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_9(ddr); + set_ddr_dq_mapping(ddr, dimm_params); +#endif + + set_ddr_zq_cntl(ddr, zq_en); + set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); + + set_ddr_sr_cntr(ddr, sr_it); + + set_ddr_sdram_rcw(ddr, popts, common_dimm); + +#ifdef CONFIG_SYS_FSL_DDR_EMU + /* disble DDR training for emulator */ + ddr->debug[2] = 0x00000400; + ddr->debug[4] = 0xff800000; +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004508 + if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) + ddr->debug[2] |= 0x00000200; /* set bit 22 */ +#endif + + return check_fsl_memctl_config_regs(ddr); +} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c similarity index 88% rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c rename to drivers/ddr/fsl/ddr1_dimm_params.c index 376be2fb37..7df27b90b7 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c +++ b/drivers/ddr/fsl/ddr1_dimm_params.c @@ -7,9 +7,9 @@ */ #include -#include +#include -#include "ddr.h" +#include /* * Calculate the Density of each Physical Rank. @@ -287,57 +287,57 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, * The SPD clk_cycle field (tCKmin) is measured in tenths of * nanoseconds and represented as BCD. */ - pdimm->tCKmin_X_ps + pdimm->tckmin_x_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tCKmin_X_minus_1_ps + pdimm->tckmin_x_minus_1_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tCKmin_X_minus_2_ps + pdimm->tckmin_x_minus_2_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - pdimm->tCKmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); + pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); /* * Compute CAS latencies defined by SPD - * The SPD caslat_X should have at least 1 and at most 3 bits set. + * The SPD caslat_x should have at least 1 and at most 3 bits set. * * If cas_lat after masking is 0, the __ilog2 function returns * 255 into the variable. This behavior is abused once. */ - pdimm->caslat_X = __ilog2(spd->cas_lat); - pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_X)); - pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_X) - & ~(1 << pdimm->caslat_X_minus_1)); + pdimm->caslat_x = __ilog2(spd->cas_lat); + pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x)); + pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x) + & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps()); /* Compute timing parameters */ - pdimm->tRCD_ps = spd->trcd * 250; - pdimm->tRP_ps = spd->trp * 250; - pdimm->tRAS_ps = spd->tras * 1000; + pdimm->trcd_ps = spd->trcd * 250; + pdimm->trp_ps = spd->trp * 250; + pdimm->tras_ps = spd->tras * 1000; - pdimm->tWR_ps = mclk_to_picos(3); - pdimm->tWTR_ps = mclk_to_picos(1); - pdimm->tRFC_ps = compute_trfc_ps_from_spd(0, spd->trfc); + pdimm->twr_ps = mclk_to_picos(3); + pdimm->twtr_ps = mclk_to_picos(1); + pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); - pdimm->tRRD_ps = spd->trrd * 250; - pdimm->tRC_ps = compute_trc_ps_from_spd(0, spd->trc); + pdimm->trrd_ps = spd->trrd * 250; + pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc); pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tDS_ps + pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); + pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); + pdimm->tds_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tDH_ps + pdimm->tdh_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - pdimm->tRTP_ps = mclk_to_picos(2); /* By the book. */ - pdimm->tDQSQ_max_ps = spd->tdqsq * 10; - pdimm->tQHS_ps = spd->tqhs * 10; + pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */ + pdimm->tdqsq_max_ps = spd->tdqsq * 10; + pdimm->tqhs_ps = spd->tqhs * 10; return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c similarity index 88% rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c rename to drivers/ddr/fsl/ddr2_dimm_params.c index f637f3d045..d865df78a8 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -7,9 +7,9 @@ */ #include -#include +#include -#include "ddr.h" +#include /* * Calculate the Density of each Physical Rank. * Returned size is in bytes. @@ -286,57 +286,57 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, * The SPD clk_cycle field (tCKmin) is measured in tenths of * nanoseconds and represented as BCD. */ - pdimm->tCKmin_X_ps + pdimm->tckmin_x_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tCKmin_X_minus_1_ps + pdimm->tckmin_x_minus_1_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tCKmin_X_minus_2_ps + pdimm->tckmin_x_minus_2_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); + pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); /* * Compute CAS latencies defined by SPD - * The SPD caslat_X should have at least 1 and at most 3 bits set. + * The SPD caslat_x should have at least 1 and at most 3 bits set. * * If cas_lat after masking is 0, the __ilog2 function returns * 255 into the variable. This behavior is abused once. */ - pdimm->caslat_X = __ilog2(spd->cas_lat); - pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_X)); - pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_X) - & ~(1 << pdimm->caslat_X_minus_1)); + pdimm->caslat_x = __ilog2(spd->cas_lat); + pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x)); + pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x) + & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps()); /* Compute timing parameters */ - pdimm->tRCD_ps = spd->trcd * 250; - pdimm->tRP_ps = spd->trp * 250; - pdimm->tRAS_ps = spd->tras * 1000; + pdimm->trcd_ps = spd->trcd * 250; + pdimm->trp_ps = spd->trp * 250; + pdimm->tras_ps = spd->tras * 1000; - pdimm->tWR_ps = spd->twr * 250; - pdimm->tWTR_ps = spd->twtr * 250; - pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); + pdimm->twr_ps = spd->twr * 250; + pdimm->twtr_ps = spd->twtr * 250; + pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); - pdimm->tRRD_ps = spd->trrd * 250; - pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); + pdimm->trrd_ps = spd->trrd * 250; + pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tDS_ps + pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); + pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); + pdimm->tds_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tDH_ps + pdimm->tdh_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - pdimm->tRTP_ps = spd->trtp * 250; - pdimm->tDQSQ_max_ps = spd->tdqsq * 10; - pdimm->tQHS_ps = spd->tqhs * 10; + pdimm->trtp_ps = spd->trtp * 250; + pdimm->tdqsq_max_ps = spd->tdqsq * 10; + pdimm->tqhs_ps = spd->tqhs * 10; return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c similarity index 84% rename from arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c rename to drivers/ddr/fsl/ddr3_dimm_params.c index 3e7c269e40..a4b8c101f5 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -12,9 +12,9 @@ */ #include -#include +#include -#include "ddr.h" +#include /* * Calculate the Density of each Physical Rank. @@ -129,6 +129,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->ec_sdram_width = 0; pdimm->data_width = pdimm->primary_sdram_width + pdimm->ec_sdram_width; + pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); /* These are the types defined by the JEDEC DDR3 SPD spec */ pdimm->mirrored_dimm = 0; @@ -209,12 +210,12 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * sdram minimum cycle time * we assume the MTB is 0.125ns * eg: - * tCK_min=15 MTB (1.875ns) ->DDR3-1066 + * tck_min=15 MTB (1.875ns) ->DDR3-1066 * =12 MTB (1.5ns) ->DDR3-1333 * =10 MTB (1.25ns) ->DDR3-1600 */ - pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps + - (spd->fine_tCK_min * ftb_10th_ps) / 10; + pdimm->tckmin_x_ps = spd->tck_min * mtb_ps + + (spd->fine_tck_min * ftb_10th_ps) / 10; /* * CAS latency supported @@ -222,55 +223,55 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * bit5 - CL5 * bit18 - CL18 */ - pdimm->caslat_X = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; + pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; /* * min CAS latency time - * eg: tAA_min = + * eg: taa_min = * DDR3-800D 100 MTB (12.5ns) * DDR3-1066F 105 MTB (13.125ns) * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25ns) */ - pdimm->tAA_ps = spd->tAA_min * mtb_ps + - (spd->fine_tAA_min * ftb_10th_ps) / 10; + pdimm->taa_ps = spd->taa_min * mtb_ps + + (spd->fine_taa_min * ftb_10th_ps) / 10; /* * min write recovery time * eg: - * tWR_min = 120 MTB (15ns) -> all speed grades. + * twr_min = 120 MTB (15ns) -> all speed grades. */ - pdimm->tWR_ps = spd->tWR_min * mtb_ps; + pdimm->twr_ps = spd->twr_min * mtb_ps; /* * min RAS to CAS delay time - * eg: tRCD_min = + * eg: trcd_min = * DDR3-800 100 MTB (12.5ns) * DDR3-1066F 105 MTB (13.125ns) * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25) */ - pdimm->tRCD_ps = spd->tRCD_min * mtb_ps + - (spd->fine_tRCD_min * ftb_10th_ps) / 10; + pdimm->trcd_ps = spd->trcd_min * mtb_ps + + (spd->fine_trcd_min * ftb_10th_ps) / 10; /* * min row active to row active delay time - * eg: tRRD_min = + * eg: trrd_min = * DDR3-800(1KB page) 80 MTB (10ns) * DDR3-1333(1KB page) 48 MTB (6ns) */ - pdimm->tRRD_ps = spd->tRRD_min * mtb_ps; + pdimm->trrd_ps = spd->trrd_min * mtb_ps; /* * min row precharge delay time - * eg: tRP_min = + * eg: trp_min = * DDR3-800D 100 MTB (12.5ns) * DDR3-1066F 105 MTB (13.125ns) * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25ns) */ - pdimm->tRP_ps = spd->tRP_min * mtb_ps + - (spd->fine_tRP_min * ftb_10th_ps) / 10; + pdimm->trp_ps = spd->trp_min * mtb_ps + + (spd->fine_trp_min * ftb_10th_ps) / 10; /* min active to precharge delay time * eg: tRAS_min = @@ -279,7 +280,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * DDR3-1333H 288 MTB (36ns) * DDR3-1600H 280 MTB (35ns) */ - pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb) + pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb) * mtb_ps; /* * min active to actice/refresh delay time @@ -289,8 +290,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * DDR3-1333H 396 MTB (49.5ns) * DDR3-1600H 370 MTB (46.25ns) */ - pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb) - * mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10; + pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb) + * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10; /* * min refresh recovery delay time * eg: tRFC_min = @@ -298,21 +299,21 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * 1Gb 880 MTB (110ns) * 2Gb 1280 MTB (160ns) */ - pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb) + pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb) * mtb_ps; /* * min internal write to read command delay time - * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins. + * eg: twtr_min = 40 MTB (7.5ns) - all speed bins. * tWRT is at least 4 mclk independent of operating freq. */ - pdimm->tWTR_ps = spd->tWTR_min * mtb_ps; + pdimm->twtr_ps = spd->twtr_min * mtb_ps; /* * min internal read to precharge command delay time - * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins. + * eg: trtp_min = 40 MTB (7.5ns) - all speed bins. * tRTP is at least 4 mclk independent of operating freq. */ - pdimm->tRTP_ps = spd->tRTP_min * mtb_ps; + pdimm->trtp_ps = spd->trtp_min * mtb_ps; /* * Average periodic refresh interval @@ -320,16 +321,20 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * = 3.9 us at ext temperature range */ pdimm->refresh_rate_ps = 7800000; + if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { + pdimm->refresh_rate_ps = 3900000; + pdimm->extended_op_srt = 1; + } /* * min four active window delay time - * eg: tFAW_min = + * eg: tfaw_min = * DDR3-800(1KB page) 320 MTB (40ns) * DDR3-1066(1KB page) 300 MTB (37.5ns) * DDR3-1333(1KB page) 240 MTB (30ns) * DDR3-1600(1KB page) 240 MTB (30ns) */ - pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min) + pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) * mtb_ps; return 0; diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c new file mode 100644 index 0000000000..aaddc8fa08 --- /dev/null +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -0,0 +1,322 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * calculate the organization and timing parameter + * from ddr3 spd, please refer to the spec + * JEDEC standard No.21-C 4_01_02_12R23A.pdf + * + * + */ + +#include +#include + +#include + +/* + * Calculate the Density of each Physical Rank. + * Returned size is in bytes. + * + * Total DIMM size = + * sdram capacity(bit) / 8 * primary bus width / sdram width + * * Logical Ranks per DIMM + * + * where: sdram capacity = spd byte4[3:0] + * primary bus width = spd byte13[2:0] + * sdram width = spd byte12[2:0] + * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP + * spd byte12{5:3] * spd byte6[6:4] for 3DS + * + * To simplify each rank size = total DIMM size / Number of Package Ranks + * where Number of Package Ranks = spd byte12[5:3] + * + * SPD byte4 - sdram density and banks + * bit[3:0] size(bit) size(byte) + * 0000 256Mb 32MB + * 0001 512Mb 64MB + * 0010 1Gb 128MB + * 0011 2Gb 256MB + * 0100 4Gb 512MB + * 0101 8Gb 1GB + * 0110 16Gb 2GB + * 0111 32Gb 4GB + * + * SPD byte13 - module memory bus width + * bit[2:0] primary bus width + * 000 8bits + * 001 16bits + * 010 32bits + * 011 64bits + * + * SPD byte12 - module organization + * bit[2:0] sdram device width + * 000 4bits + * 001 8bits + * 010 16bits + * 011 32bits + * + * SPD byte12 - module organization + * bit[5:3] number of package ranks per DIMM + * 000 1 + * 001 2 + * 010 3 + * 011 4 + * + * SPD byte6 - SDRAM package type + * bit[6:4] Die count + * 000 1 + * 001 2 + * 010 3 + * 011 4 + * 100 5 + * 101 6 + * 110 7 + * 111 8 + * + * SPD byte6 - SRAM package type + * bit[1:0] Signal loading + * 00 Not specified + * 01 Multi load stack + * 10 Sigle load stack (3DS) + * 11 Reserved + */ +static unsigned long long +compute_ranksize(const struct ddr4_spd_eeprom_s *spd) +{ + unsigned long long bsize; + + int nbit_sdram_cap_bsize = 0; + int nbit_primary_bus_width = 0; + int nbit_sdram_width = 0; + int die_count = 0; + bool package_3ds; + + if ((spd->density_banks & 0xf) <= 7) + nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; + if ((spd->bus_width & 0x7) < 4) + nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; + if ((spd->organization & 0x7) < 4) + nbit_sdram_width = (spd->organization & 0x7) + 2; + package_3ds = (spd->package_type & 0x3) == 0x2; + if (package_3ds) + die_count = (spd->package_type >> 4) & 0x7; + + bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + + nbit_primary_bus_width - nbit_sdram_width + + die_count); + + debug("DDR: DDR III rank density = 0x%16llx\n", bsize); + + return bsize; +} + +#define spd_to_ps(mtb, ftb) \ + (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10) +/* + * ddr_compute_dimm_parameters for DDR4 SPD + * + * Compute DIMM parameters based upon the SPD information in spd. + * Writes the results to the dimm_params_t structure pointed by pdimm. + * + */ +unsigned int +ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + unsigned int retval; + int i; + const u8 udimm_rc_e_dq[18] = { + 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15, + 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36 + }; + int spd_error = 0; + u8 *ptr; + + if (spd->mem_type) { + if (spd->mem_type != SPD_MEMTYPE_DDR4) { + printf("DIMM %u: is not a DDR4 SPD.\n", dimm_number); + return 1; + } + } else { + memset(pdimm, 0, sizeof(dimm_params_t)); + return 1; + } + + retval = ddr4_spd_check(spd); + if (retval) { + printf("DIMM %u: failed checksum\n", dimm_number); + return 2; + } + + /* + * The part name in ASCII in the SPD EEPROM is not null terminated. + * Guarantee null termination here by presetting all bytes to 0 + * and copying the part name in ASCII from the SPD onto it + */ + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + if ((spd->info_size_crc & 0xF) > 2) + memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); + + /* DIMM organization parameters */ + pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; + pdimm->rank_density = compute_ranksize(spd); + pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; + pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); + if ((spd->bus_width >> 3) & 0x3) + pdimm->ec_sdram_width = 8; + else + pdimm->ec_sdram_width = 0; + pdimm->data_width = pdimm->primary_sdram_width + + pdimm->ec_sdram_width; + pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); + + /* These are the types defined by the JEDEC SPD spec */ + pdimm->mirrored_dimm = 0; + pdimm->registered_dimm = 0; + switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) { + case DDR4_SPD_MODULETYPE_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; + break; + + case DDR4_SPD_MODULETYPE_UDIMM: + case DDR4_SPD_MODULETYPE_SO_DIMM: + /* Unbuffered DIMMs */ + if (spd->mod_section.unbuffered.addr_mapping & 0x1) + pdimm->mirrored_dimm = 1; + if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 && + (spd->mod_section.unbuffered.ref_raw_card == 0x04)) { + /* Fix SPD error found on DIMMs with raw card E0 */ + for (i = 0; i < 18; i++) { + if (spd->mapping[i] == udimm_rc_e_dq[i]) + continue; + spd_error = 1; + debug("SPD byte %d: 0x%x, should be 0x%x\n", + 60 + i, spd->mapping[i], + udimm_rc_e_dq[i]); + ptr = (u8 *)&spd->mapping[i]; + *ptr = udimm_rc_e_dq[i]; + } + if (spd_error) + puts("SPD DQ mapping error fixed\n"); + } + break; + + default: + printf("unknown module_type 0x%02X\n", spd->module_type); + return 1; + } + + /* SDRAM device parameters */ + pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; + pdimm->n_col_addr = (spd->addressing & 0x7) + 9; + pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3; + pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3; + + /* + * The SPD spec has not the ECC bit, + * We consider the DIMM as ECC capability + * when the extension bus exist + */ + if (pdimm->ec_sdram_width) + pdimm->edc_config = 0x02; + else + pdimm->edc_config = 0x00; + + /* + * The SPD spec has not the burst length byte + * but DDR4 spec has nature BL8 and BC4, + * BL8 -bit3, BC4 -bit2 + */ + pdimm->burst_lengths_bitmask = 0x0c; + pdimm->row_density = __ilog2(pdimm->rank_density); + + /* MTB - medium timebase + * The MTB in the SPD spec is 125ps, + * + * FTB - fine timebase + * use 1/10th of ps as our unit to avoid floating point + * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps + */ + if ((spd->timebases & 0xf) == 0x0) { + pdimm->mtb_ps = 125; + pdimm->ftb_10th_ps = 10; + + } else { + printf("Unknown Timebases\n"); + } + + /* sdram minimum cycle time */ + pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min); + + /* sdram max cycle time */ + pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max); + + /* + * CAS latency supported + * bit0 - CL7 + * bit4 - CL11 + * bit8 - CL15 + * bit12- CL19 + * bit16- CL23 + */ + pdimm->caslat_x = (spd->caslat_b1 << 7) | + (spd->caslat_b2 << 15) | + (spd->caslat_b3 << 23); + + BUG_ON(spd->caslat_b4 != 0); + + /* + * min CAS latency time + */ + pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min); + + /* + * min RAS to CAS delay time + */ + pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min); + + /* + * Min Row Precharge Delay Time + */ + pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min); + + /* min active to precharge delay time */ + pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) + + spd->tras_min_lsb) * pdimm->mtb_ps; + + /* min active to actice/refresh delay time */ + pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) + + spd->trc_min_lsb), spd->fine_trc_min); + /* Min Refresh Recovery Delay Time */ + pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) * + pdimm->mtb_ps; + pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) * + pdimm->mtb_ps; + pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) * + pdimm->mtb_ps; + /* min four active window delay time */ + pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) * + pdimm->mtb_ps; + + /* min row active to row active delay time, different bank group */ + pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min); + /* min row active to row active delay time, same bank group */ + pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min); + /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */ + pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min); + + /* + * Average periodic refresh interval + * tREFI = 7.8 us at normal temperature range + */ + pdimm->refresh_rate_ps = 7800000; + + for (i = 0; i < 18; i++) + pdimm->dq_mapping[i] = spd->mapping[i]; + + pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0; + + return 0; +} diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c new file mode 100644 index 0000000000..4eef047343 --- /dev/null +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -0,0 +1,278 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +/* + * regs has the to-be-set values for DDR controller registers + * ctrl_num is the DDR controller number + * step: 0 goes through the initialization in one pass + * 1 sets registers and returns before enabling controller + * 2 resumes from step 1 and continues to initialize + * Dividing the initialization to two steps to deassert DDR reset signal + * to comply with JEDEC specs for RDIMMs. + */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i, bus_width; + struct ccsr_ddr __iomem *ddr; + u32 temp_sdram_cfg; + u32 total_gb_size_per_controller; + int timeout; + + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); + return; + } + + if (step == 2) + goto step2; + + if (regs->ddr_eor) + ddr_out32(&ddr->eor, regs->ddr_eor); + + ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs0_config, regs->cs[i].config); + ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); + + } else if (i == 1) { + ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs1_config, regs->cs[i].config); + ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); + + } else if (i == 2) { + ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs2_config, regs->cs[i].config); + ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); + + } else if (i == 3) { + ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs3_config, regs->cs[i].config); + ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); + } + } + + ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); + ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); + ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); + ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); + ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); + ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); + ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); + ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); + ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); + ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); + ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + ddr_out32(&ddr->dq_map_0, regs->dq_map_0); + ddr_out32(&ddr->dq_map_1, regs->dq_map_1); + ddr_out32(&ddr->dq_map_2, regs->dq_map_2); + ddr_out32(&ddr->dq_map_3, regs->dq_map_3); + ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); + ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); + ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); + ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); + ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); + ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); + ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); + ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); + ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); + ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); + ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); + ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); + ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); +#ifndef CONFIG_SYS_FSL_DDR_EMU + /* + * Skip these two registers if running on emulator + * because emulator doesn't have skew between bytes. + */ + + if (regs->ddr_wrlvl_cntl_2) + ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + if (regs->ddr_wrlvl_cntl_3) + ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); +#endif + + ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); + ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); + ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); + ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); + ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + ddr_out32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + ddr_out32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } + ddr_out32(&ddr->err_disable, regs->err_disable); + ddr_out32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) { + if (regs->debug[i]) { + debug("Write to debug_%d as %08x\n", + i+1, regs->debug[i]); + ddr_out32(&ddr->debug[i], regs->debug[i]); + } + } +#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 + /* Erratum applies when accumulated ECC is used, or DBI is enabled */ +#define IS_ACC_ECC_EN(v) ((v) & 0x4) +#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) + if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || + IS_DBI(regs->ddr_sdram_cfg_3)) + ddr_setbits32(ddr->debug[28], 0x9 << 20); +#endif + + /* + * For RDIMMs, JEDEC spec requires clocks to be stable before reset is + * deasserted. Clocks start when any chip select is enabled and clock + * control register is set. Because all DDR components are connected to + * one reset signal, this needs to be done in two steps. Step 1 is to + * get the clocks started. Step 2 resumes after reset signal is + * deasserted. + */ + if (step == 1) { + udelay(200); + return; + } + +step2: + /* Set, but do not enable the memory */ + temp_sdram_cfg = regs->ddr_sdram_cfg; + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); + + /* + * 500 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. + */ + udelay(500); + mb(); + isb(); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + /* do board specific memory setup */ + board_mem_sleep_setup(); + + temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + /* Let the controller go */ + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + mb(); + isb(); + + total_gb_size_per_controller = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (!(regs->cs[i].config & 0x80000000)) + continue; + total_gb_size_per_controller += 1 << ( + ((regs->cs[i].config >> 14) & 0x3) + 2 + + ((regs->cs[i].config >> 8) & 0x7) + 12 + + ((regs->cs[i].config >> 4) & 0x3) + 0 + + ((regs->cs[i].config >> 0) & 0x7) + 8 + + 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - + 26); /* minus 26 (count of 64M) */ + } + if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ + total_gb_size_per_controller *= 3; + else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ + total_gb_size_per_controller <<= 1; + /* + * total memory / bus width = transactions needed + * transactions needed / data rate = seconds + * to add plenty of buffer, double the time + * For example, 2GB on 666MT/s 64-bit bus takes about 402ms + * Let's wait for 800ms + */ + bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) + >> SDRAM_CFG_DBW_SHIFT); + timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / + (get_ddr_freq(0) >> 20)) << 2; + total_gb_size_per_controller >>= 4; /* shift down to gb size */ + debug("total %d GB\n", total_gb_size_per_controller); + debug("Need to wait up to %d * 10ms\n", timeout); + + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ + while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif +} diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c new file mode 100644 index 0000000000..32ba6d820b --- /dev/null +++ b/drivers/ddr/fsl/interactive.c @@ -0,0 +1,2242 @@ +/* + * Copyright 2010-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Based on code from spd_sdram.c + * Author: James Yang [at freescale.com] + * York Sun [at freescale.com] + */ + +#include +#include +#include +#include +#include + +#include +#include + +/* Option parameter Structures */ +struct options_string { + const char *option_name; + size_t offset; + unsigned int size; + const char printhex; +}; + +static unsigned int picos_to_mhz(unsigned int picos) +{ + return 1000000 / picos; +} + +static void print_option_table(const struct options_string *table, + int table_size, + const void *base) +{ + unsigned int i; + unsigned int *ptr; + unsigned long long *ptr_l; + + for (i = 0; i < table_size; i++) { + switch (table[i].size) { + case 4: + ptr = (unsigned int *) (base + table[i].offset); + if (table[i].printhex) { + printf("%s = 0x%08X\n", + table[i].option_name, *ptr); + } else { + printf("%s = %u\n", + table[i].option_name, *ptr); + } + break; + case 8: + ptr_l = (unsigned long long *) (base + table[i].offset); + printf("%s = %llu\n", + table[i].option_name, *ptr_l); + break; + default: + printf("Unrecognized size!\n"); + break; + } + } +} + +static int handle_option_table(const struct options_string *table, + int table_size, + void *base, + const char *opt, + const char *val) +{ + unsigned int i; + unsigned int value, *ptr; + unsigned long long value_l, *ptr_l; + + for (i = 0; i < table_size; i++) { + if (strcmp(table[i].option_name, opt) != 0) + continue; + switch (table[i].size) { + case 4: + value = simple_strtoul(val, NULL, 0); + ptr = base + table[i].offset; + *ptr = value; + break; + case 8: + value_l = simple_strtoull(val, NULL, 0); + ptr_l = base + table[i].offset; + *ptr_l = value_l; + break; + default: + printf("Unrecognized size!\n"); + break; + } + return 1; + } + + return 0; +} + +static void fsl_ddr_generic_edit(void *pdata, + void *pend, + unsigned int element_size, + unsigned int element_num, + unsigned int value) +{ + char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */ + + pcdata += element_num * element_size; + if ((pcdata + element_size) > (char *) pend) { + printf("trying to write past end of data\n"); + return; + } + + switch (element_size) { + case 1: + __raw_writeb(value, pcdata); + break; + case 2: + __raw_writew(value, pcdata); + break; + case 4: + __raw_writel(value, pcdata); + break; + default: + printf("unexpected element size %u\n", element_size); + break; + } +} + +static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + unsigned int dimm_num, + unsigned int element_num, + unsigned int value) +{ + generic_spd_eeprom_t *pspd; + + pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); + fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value); +} + +#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \ + sizeof((common_timing_params_t *)0)->x, 0} + +static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + const char *optname_str, + const char *value_str) +{ + common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; + + static const struct options_string options[] = { + COMMON_TIMING(tckmin_x_ps), + COMMON_TIMING(tckmax_ps), + COMMON_TIMING(taamin_ps), + COMMON_TIMING(trcd_ps), + COMMON_TIMING(trp_ps), + COMMON_TIMING(tras_ps), + +#ifdef CONFIG_SYS_FSL_DDR4 + COMMON_TIMING(trfc1_ps), + COMMON_TIMING(trfc2_ps), + COMMON_TIMING(trfc4_ps), + COMMON_TIMING(trrds_ps), + COMMON_TIMING(trrdl_ps), + COMMON_TIMING(tccdl_ps), +#else + COMMON_TIMING(twtr_ps), + COMMON_TIMING(trfc_ps), + COMMON_TIMING(trrd_ps), + COMMON_TIMING(trtp_ps), +#endif + COMMON_TIMING(twr_ps), + COMMON_TIMING(trc_ps), + COMMON_TIMING(refresh_rate_ps), + COMMON_TIMING(extended_op_srt), +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + COMMON_TIMING(tis_ps), + COMMON_TIMING(tih_ps), + COMMON_TIMING(tds_ps), + COMMON_TIMING(tdh_ps), + COMMON_TIMING(tdqsq_max_ps), + COMMON_TIMING(tqhs_ps), +#endif + COMMON_TIMING(ndimms_present), + COMMON_TIMING(lowest_common_spd_caslat), + COMMON_TIMING(highest_common_derated_caslat), + COMMON_TIMING(additive_latency), + COMMON_TIMING(all_dimms_burst_lengths_bitmask), + COMMON_TIMING(all_dimms_registered), + COMMON_TIMING(all_dimms_unbuffered), + COMMON_TIMING(all_dimms_ecc_capable), + COMMON_TIMING(total_mem), + COMMON_TIMING(base_address), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, optname_str, value_str)) + return; + + printf("Error: couldn't find option string %s\n", optname_str); +} + +#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \ + sizeof((dimm_params_t *)0)->x, 0} + +static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + unsigned int dimm_num, + const char *optname_str, + const char *value_str) +{ + dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); + + static const struct options_string options[] = { + DIMM_PARM(n_ranks), + DIMM_PARM(data_width), + DIMM_PARM(primary_sdram_width), + DIMM_PARM(ec_sdram_width), + DIMM_PARM(registered_dimm), + DIMM_PARM(device_width), + + DIMM_PARM(n_row_addr), + DIMM_PARM(n_col_addr), + DIMM_PARM(edc_config), +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM(bank_addr_bits), + DIMM_PARM(bank_group_bits), +#else + DIMM_PARM(n_banks_per_sdram_device), +#endif + DIMM_PARM(burst_lengths_bitmask), + DIMM_PARM(row_density), + + DIMM_PARM(tckmin_x_ps), + DIMM_PARM(tckmin_x_minus_1_ps), + DIMM_PARM(tckmin_x_minus_2_ps), + DIMM_PARM(tckmax_ps), + + DIMM_PARM(caslat_x), + DIMM_PARM(caslat_x_minus_1), + DIMM_PARM(caslat_x_minus_2), + + DIMM_PARM(caslat_lowest_derated), + + DIMM_PARM(trcd_ps), + DIMM_PARM(trp_ps), + DIMM_PARM(tras_ps), +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM(trfc1_ps), + DIMM_PARM(trfc2_ps), + DIMM_PARM(trfc4_ps), + DIMM_PARM(trrds_ps), + DIMM_PARM(trrdl_ps), + DIMM_PARM(tccdl_ps), +#else + DIMM_PARM(twr_ps), + DIMM_PARM(twtr_ps), + DIMM_PARM(trfc_ps), + DIMM_PARM(trrd_ps), + DIMM_PARM(trtp_ps), +#endif + DIMM_PARM(trc_ps), + DIMM_PARM(refresh_rate_ps), + DIMM_PARM(extended_op_srt), + +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + DIMM_PARM(tis_ps), + DIMM_PARM(tih_ps), + DIMM_PARM(tds_ps), + DIMM_PARM(tdh_ps), + DIMM_PARM(tdqsq_max_ps), + DIMM_PARM(tqhs_ps), +#endif + + DIMM_PARM(rank_density), + DIMM_PARM(capacity), + DIMM_PARM(base_address), + }; + + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, optname_str, value_str)) + return; + + printf("couldn't find option string %s\n", optname_str); +} + +static void print_dimm_parameters(const dimm_params_t *pdimm) +{ + static const struct options_string options[] = { + DIMM_PARM(n_ranks), + DIMM_PARM(data_width), + DIMM_PARM(primary_sdram_width), + DIMM_PARM(ec_sdram_width), + DIMM_PARM(registered_dimm), + DIMM_PARM(device_width), + + DIMM_PARM(n_row_addr), + DIMM_PARM(n_col_addr), + DIMM_PARM(edc_config), +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM(bank_addr_bits), + DIMM_PARM(bank_group_bits), +#else + DIMM_PARM(n_banks_per_sdram_device), +#endif + + DIMM_PARM(tckmin_x_ps), + DIMM_PARM(tckmin_x_minus_1_ps), + DIMM_PARM(tckmin_x_minus_2_ps), + DIMM_PARM(tckmax_ps), + + DIMM_PARM(caslat_x), + DIMM_PARM(taa_ps), + DIMM_PARM(caslat_x_minus_1), + DIMM_PARM(caslat_x_minus_2), + DIMM_PARM(caslat_lowest_derated), + + DIMM_PARM(trcd_ps), + DIMM_PARM(trp_ps), + DIMM_PARM(tras_ps), +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM(trfc1_ps), + DIMM_PARM(trfc2_ps), + DIMM_PARM(trfc4_ps), + DIMM_PARM(trrds_ps), + DIMM_PARM(trrdl_ps), + DIMM_PARM(tccdl_ps), +#else + DIMM_PARM(twr_ps), + DIMM_PARM(twtr_ps), + DIMM_PARM(trfc_ps), + DIMM_PARM(trrd_ps), + DIMM_PARM(trtp_ps), +#endif + DIMM_PARM(trc_ps), + DIMM_PARM(refresh_rate_ps), + +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + DIMM_PARM(tis_ps), + DIMM_PARM(tih_ps), + DIMM_PARM(tds_ps), + DIMM_PARM(tdh_ps), + DIMM_PARM(tdqsq_max_ps), + DIMM_PARM(tqhs_ps), +#endif + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (pdimm->n_ranks == 0) { + printf("DIMM not present\n"); + return; + } + printf("DIMM organization parameters:\n"); + printf("module part name = %s\n", pdimm->mpart); + printf("rank_density = %llu bytes (%llu megabytes)\n", + pdimm->rank_density, pdimm->rank_density / 0x100000); + printf("capacity = %llu bytes (%llu megabytes)\n", + pdimm->capacity, pdimm->capacity / 0x100000); + printf("burst_lengths_bitmask = %02X\n", + pdimm->burst_lengths_bitmask); + printf("base_addresss = %llu (%08llX %08llX)\n", + pdimm->base_address, + (pdimm->base_address >> 32), + pdimm->base_address & 0xFFFFFFFF); + print_option_table(options, n_opts, pdimm); +} + +static void print_lowest_common_dimm_parameters( + const common_timing_params_t *plcd_dimm_params) +{ + static const struct options_string options[] = { + COMMON_TIMING(taamin_ps), + COMMON_TIMING(trcd_ps), + COMMON_TIMING(trp_ps), + COMMON_TIMING(tras_ps), +#ifdef CONFIG_SYS_FSL_DDR4 + COMMON_TIMING(trfc1_ps), + COMMON_TIMING(trfc2_ps), + COMMON_TIMING(trfc4_ps), + COMMON_TIMING(trrds_ps), + COMMON_TIMING(trrdl_ps), + COMMON_TIMING(tccdl_ps), +#else + COMMON_TIMING(twtr_ps), + COMMON_TIMING(trfc_ps), + COMMON_TIMING(trrd_ps), + COMMON_TIMING(trtp_ps), +#endif + COMMON_TIMING(twr_ps), + COMMON_TIMING(trc_ps), + COMMON_TIMING(refresh_rate_ps), + COMMON_TIMING(extended_op_srt), +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + COMMON_TIMING(tis_ps), + COMMON_TIMING(tih_ps), + COMMON_TIMING(tds_ps), + COMMON_TIMING(tdh_ps), + COMMON_TIMING(tdqsq_max_ps), + COMMON_TIMING(tqhs_ps), +#endif + COMMON_TIMING(lowest_common_spd_caslat), + COMMON_TIMING(highest_common_derated_caslat), + COMMON_TIMING(additive_latency), + COMMON_TIMING(ndimms_present), + COMMON_TIMING(all_dimms_registered), + COMMON_TIMING(all_dimms_unbuffered), + COMMON_TIMING(all_dimms_ecc_capable), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + /* Clock frequencies */ + printf("tckmin_x_ps = %u (%u MHz)\n", + plcd_dimm_params->tckmin_x_ps, + picos_to_mhz(plcd_dimm_params->tckmin_x_ps)); + printf("tckmax_ps = %u (%u MHz)\n", + plcd_dimm_params->tckmax_ps, + picos_to_mhz(plcd_dimm_params->tckmax_ps)); + printf("all_dimms_burst_lengths_bitmask = %02X\n", + plcd_dimm_params->all_dimms_burst_lengths_bitmask); + + print_option_table(options, n_opts, plcd_dimm_params); + + printf("total_mem = %llu (%llu megabytes)\n", + plcd_dimm_params->total_mem, + plcd_dimm_params->total_mem / 0x100000); + printf("base_address = %llu (%llu megabytes)\n", + plcd_dimm_params->base_address, + plcd_dimm_params->base_address / 0x100000); +} + +#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \ + sizeof((memctl_options_t *)0)->x, 0} +#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \ + offsetof(memctl_options_t, cs_local_opts[x].y), \ + sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0} + +static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, + unsigned int ctl_num, + const char *optname_str, + const char *value_str) +{ + memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]); + /* + * This array all on the stack and *computed* each time this + * function is rung. + */ + static const struct options_string options[] = { + CTRL_OPTIONS_CS(0, odt_rd_cfg), + CTRL_OPTIONS_CS(0, odt_wr_cfg), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rd_cfg), + CTRL_OPTIONS_CS(1, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rd_cfg), + CTRL_OPTIONS_CS(2, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(3, odt_rd_cfg), + CTRL_OPTIONS_CS(3, odt_wr_cfg), +#endif +#if defined(CONFIG_SYS_FSL_DDR3) + CTRL_OPTIONS_CS(0, odt_rtt_norm), + CTRL_OPTIONS_CS(0, odt_rtt_wr), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rtt_norm), + CTRL_OPTIONS_CS(1, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rtt_norm), + CTRL_OPTIONS_CS(2, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(3, odt_rtt_norm), + CTRL_OPTIONS_CS(3, odt_rtt_wr), +#endif +#endif + CTRL_OPTIONS(memctl_interleaving), + CTRL_OPTIONS(memctl_interleaving_mode), + CTRL_OPTIONS(ba_intlv_ctl), + CTRL_OPTIONS(ecc_mode), + CTRL_OPTIONS(ecc_init_using_memctl), + CTRL_OPTIONS(dqs_config), + CTRL_OPTIONS(self_refresh_in_sleep), + CTRL_OPTIONS(dynamic_power), + CTRL_OPTIONS(data_bus_width), + CTRL_OPTIONS(burst_length), + CTRL_OPTIONS(cas_latency_override), + CTRL_OPTIONS(cas_latency_override_value), + CTRL_OPTIONS(use_derated_caslat), + CTRL_OPTIONS(additive_latency_override), + CTRL_OPTIONS(additive_latency_override_value), + CTRL_OPTIONS(clk_adjust), + CTRL_OPTIONS(cpo_override), + CTRL_OPTIONS(write_data_delay), + CTRL_OPTIONS(half_strength_driver_enable), + + /* + * These can probably be changed to 2T_EN and 3T_EN + * (using a leading numerical character) without problem + */ + CTRL_OPTIONS(twot_en), + CTRL_OPTIONS(threet_en), + CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(x4_en), + CTRL_OPTIONS(bstopre), + CTRL_OPTIONS(wrlvl_override), + CTRL_OPTIONS(wrlvl_sample), + CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS(cswl_override), + CTRL_OPTIONS(rcw_override), + CTRL_OPTIONS(rcw_1), + CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS(ddr_cdr1), + CTRL_OPTIONS(ddr_cdr2), + CTRL_OPTIONS(tfaw_window_four_activates_ps), + CTRL_OPTIONS(trwt_override), + CTRL_OPTIONS(trwt), + CTRL_OPTIONS(rtt_override), + CTRL_OPTIONS(rtt_override_value), + CTRL_OPTIONS(rtt_wr_override_value), + }; + + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, + optname_str, value_str)) + return; + + printf("couldn't find option string %s\n", optname_str); +} + +#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \ + sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1} +#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \ + offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \ + sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1} + +static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int i; + static const struct options_string options[] = { + CFG_REGS_CS(0, bnds), + CFG_REGS_CS(0, config), + CFG_REGS_CS(0, config_2), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CFG_REGS_CS(1, bnds), + CFG_REGS_CS(1, config), + CFG_REGS_CS(1, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(2, bnds), + CFG_REGS_CS(2, config), + CFG_REGS_CS(2, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(3, bnds), + CFG_REGS_CS(3, config), + CFG_REGS_CS(3, config_2), +#endif + CFG_REGS(timing_cfg_3), + CFG_REGS(timing_cfg_0), + CFG_REGS(timing_cfg_1), + CFG_REGS(timing_cfg_2), + CFG_REGS(ddr_sdram_cfg), + CFG_REGS(ddr_sdram_cfg_2), + CFG_REGS(ddr_sdram_cfg_3), + CFG_REGS(ddr_sdram_mode), + CFG_REGS(ddr_sdram_mode_2), + CFG_REGS(ddr_sdram_mode_3), + CFG_REGS(ddr_sdram_mode_4), + CFG_REGS(ddr_sdram_mode_5), + CFG_REGS(ddr_sdram_mode_6), + CFG_REGS(ddr_sdram_mode_7), + CFG_REGS(ddr_sdram_mode_8), +#ifdef CONFIG_SYS_FSL_DDR4 + CFG_REGS(ddr_sdram_mode_9), + CFG_REGS(ddr_sdram_mode_10), + CFG_REGS(ddr_sdram_mode_11), + CFG_REGS(ddr_sdram_mode_12), + CFG_REGS(ddr_sdram_mode_13), + CFG_REGS(ddr_sdram_mode_14), + CFG_REGS(ddr_sdram_mode_15), + CFG_REGS(ddr_sdram_mode_16), +#endif + CFG_REGS(ddr_sdram_interval), + CFG_REGS(ddr_data_init), + CFG_REGS(ddr_sdram_clk_cntl), + CFG_REGS(ddr_init_addr), + CFG_REGS(ddr_init_ext_addr), + CFG_REGS(timing_cfg_4), + CFG_REGS(timing_cfg_5), +#ifdef CONFIG_SYS_FSL_DDR4 + CFG_REGS(timing_cfg_6), + CFG_REGS(timing_cfg_7), + CFG_REGS(timing_cfg_8), + CFG_REGS(timing_cfg_9), +#endif + CFG_REGS(ddr_zq_cntl), + CFG_REGS(ddr_wrlvl_cntl), + CFG_REGS(ddr_wrlvl_cntl_2), + CFG_REGS(ddr_wrlvl_cntl_3), + CFG_REGS(ddr_sr_cntr), + CFG_REGS(ddr_sdram_rcw_1), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_cdr1), + CFG_REGS(ddr_cdr2), + CFG_REGS(dq_map_0), + CFG_REGS(dq_map_1), + CFG_REGS(dq_map_2), + CFG_REGS(dq_map_3), + CFG_REGS(err_disable), + CFG_REGS(err_int_en), + CFG_REGS(ddr_eor), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + print_option_table(options, n_opts, ddr); + + for (i = 0; i < 32; i++) + printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); +} + +static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + const char *regname, + const char *value_str) +{ + unsigned int i; + fsl_ddr_cfg_regs_t *ddr; + char buf[20]; + static const struct options_string options[] = { + CFG_REGS_CS(0, bnds), + CFG_REGS_CS(0, config), + CFG_REGS_CS(0, config_2), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CFG_REGS_CS(1, bnds), + CFG_REGS_CS(1, config), + CFG_REGS_CS(1, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(2, bnds), + CFG_REGS_CS(2, config), + CFG_REGS_CS(2, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CFG_REGS_CS(3, bnds), + CFG_REGS_CS(3, config), + CFG_REGS_CS(3, config_2), +#endif + CFG_REGS(timing_cfg_3), + CFG_REGS(timing_cfg_0), + CFG_REGS(timing_cfg_1), + CFG_REGS(timing_cfg_2), + CFG_REGS(ddr_sdram_cfg), + CFG_REGS(ddr_sdram_cfg_2), + CFG_REGS(ddr_sdram_cfg_3), + CFG_REGS(ddr_sdram_mode), + CFG_REGS(ddr_sdram_mode_2), + CFG_REGS(ddr_sdram_mode_3), + CFG_REGS(ddr_sdram_mode_4), + CFG_REGS(ddr_sdram_mode_5), + CFG_REGS(ddr_sdram_mode_6), + CFG_REGS(ddr_sdram_mode_7), + CFG_REGS(ddr_sdram_mode_8), +#ifdef CONFIG_SYS_FSL_DDR4 + CFG_REGS(ddr_sdram_mode_9), + CFG_REGS(ddr_sdram_mode_10), + CFG_REGS(ddr_sdram_mode_11), + CFG_REGS(ddr_sdram_mode_12), + CFG_REGS(ddr_sdram_mode_13), + CFG_REGS(ddr_sdram_mode_14), + CFG_REGS(ddr_sdram_mode_15), + CFG_REGS(ddr_sdram_mode_16), +#endif + CFG_REGS(ddr_sdram_interval), + CFG_REGS(ddr_data_init), + CFG_REGS(ddr_sdram_clk_cntl), + CFG_REGS(ddr_init_addr), + CFG_REGS(ddr_init_ext_addr), + CFG_REGS(timing_cfg_4), + CFG_REGS(timing_cfg_5), +#ifdef CONFIG_SYS_FSL_DDR4 + CFG_REGS(timing_cfg_6), + CFG_REGS(timing_cfg_7), + CFG_REGS(timing_cfg_8), + CFG_REGS(timing_cfg_9), +#endif + CFG_REGS(ddr_zq_cntl), + CFG_REGS(ddr_wrlvl_cntl), + CFG_REGS(ddr_wrlvl_cntl_2), + CFG_REGS(ddr_wrlvl_cntl_3), + CFG_REGS(ddr_sr_cntr), + CFG_REGS(ddr_sdram_rcw_1), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_cdr1), + CFG_REGS(ddr_cdr2), + CFG_REGS(dq_map_0), + CFG_REGS(dq_map_1), + CFG_REGS(dq_map_2), + CFG_REGS(dq_map_3), + CFG_REGS(err_disable), + CFG_REGS(err_int_en), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_eor), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + debug("fsl_ddr_regs_edit: ctrl_num = %u, " + "regname = %s, value = %s\n", + ctrl_num, regname, value_str); + if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS) + return; + + ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); + + if (handle_option_table(options, n_opts, ddr, regname, value_str)) + return; + + for (i = 0; i < 32; i++) { + unsigned int value = simple_strtoul(value_str, NULL, 0); + sprintf(buf, "debug_%u", i + 1); + if (strcmp(buf, regname) == 0) { + ddr->debug[i] = value; + return; + } + } + printf("Error: couldn't find register string %s\n", regname); +} + +#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \ + sizeof((memctl_options_t *)0)->x, 1} + +static void print_memctl_options(const memctl_options_t *popts) +{ + static const struct options_string options[] = { + CTRL_OPTIONS_CS(0, odt_rd_cfg), + CTRL_OPTIONS_CS(0, odt_wr_cfg), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rd_cfg), + CTRL_OPTIONS_CS(1, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rd_cfg), + CTRL_OPTIONS_CS(2, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CTRL_OPTIONS_CS(3, odt_rd_cfg), + CTRL_OPTIONS_CS(3, odt_wr_cfg), +#endif +#if defined(CONFIG_SYS_FSL_DDR3) + CTRL_OPTIONS_CS(0, odt_rtt_norm), + CTRL_OPTIONS_CS(0, odt_rtt_wr), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rtt_norm), + CTRL_OPTIONS_CS(1, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rtt_norm), + CTRL_OPTIONS_CS(2, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CTRL_OPTIONS_CS(3, odt_rtt_norm), + CTRL_OPTIONS_CS(3, odt_rtt_wr), +#endif +#endif + CTRL_OPTIONS(memctl_interleaving), + CTRL_OPTIONS(memctl_interleaving_mode), + CTRL_OPTIONS_HEX(ba_intlv_ctl), + CTRL_OPTIONS(ecc_mode), + CTRL_OPTIONS(ecc_init_using_memctl), + CTRL_OPTIONS(dqs_config), + CTRL_OPTIONS(self_refresh_in_sleep), + CTRL_OPTIONS(dynamic_power), + CTRL_OPTIONS(data_bus_width), + CTRL_OPTIONS(burst_length), + CTRL_OPTIONS(cas_latency_override), + CTRL_OPTIONS(cas_latency_override_value), + CTRL_OPTIONS(use_derated_caslat), + CTRL_OPTIONS(additive_latency_override), + CTRL_OPTIONS(additive_latency_override_value), + CTRL_OPTIONS(clk_adjust), + CTRL_OPTIONS(cpo_override), + CTRL_OPTIONS(write_data_delay), + CTRL_OPTIONS(half_strength_driver_enable), + /* + * These can probably be changed to 2T_EN and 3T_EN + * (using a leading numerical character) without problem + */ + CTRL_OPTIONS(twot_en), + CTRL_OPTIONS(threet_en), + CTRL_OPTIONS(registered_dimm_en), + CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(x4_en), + CTRL_OPTIONS(bstopre), + CTRL_OPTIONS(wrlvl_override), + CTRL_OPTIONS(wrlvl_sample), + CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS_HEX(cswl_override), + CTRL_OPTIONS(rcw_override), + CTRL_OPTIONS(rcw_1), + CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS_HEX(ddr_cdr1), + CTRL_OPTIONS_HEX(ddr_cdr2), + CTRL_OPTIONS(tfaw_window_four_activates_ps), + CTRL_OPTIONS(trwt_override), + CTRL_OPTIONS(trwt), + CTRL_OPTIONS(rtt_override), + CTRL_OPTIONS(rtt_override_value), + CTRL_OPTIONS(rtt_wr_override_value), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + print_option_table(options, n_opts, popts); +} + +#ifdef CONFIG_SYS_FSL_DDR1 +void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd) +{ + unsigned int i; + + printf("%-3d : %02x %s\n", 0, spd->info_size, + " spd->info_size, * 0 # bytes written into serial memory *"); + printf("%-3d : %02x %s\n", 1, spd->chip_size, + " spd->chip_size, * 1 Total # bytes of SPD memory device *"); + printf("%-3d : %02x %s\n", 2, spd->mem_type, + " spd->mem_type, * 2 Fundamental memory type *"); + printf("%-3d : %02x %s\n", 3, spd->nrow_addr, + " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); + printf("%-3d : %02x %s\n", 4, spd->ncol_addr, + " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); + printf("%-3d : %02x %s\n", 5, spd->nrows, + " spd->nrows * 5 # of DIMM Banks *"); + printf("%-3d : %02x %s\n", 6, spd->dataw_lsb, + " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); + printf("%-3d : %02x %s\n", 7, spd->dataw_msb, + " spd->dataw_msb, * 7 Data Width msb of this assembly *"); + printf("%-3d : %02x %s\n", 8, spd->voltage, + " spd->voltage, * 8 Voltage intf std of this assembly *"); + printf("%-3d : %02x %s\n", 9, spd->clk_cycle, + " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); + printf("%-3d : %02x %s\n", 10, spd->clk_access, + " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); + printf("%-3d : %02x %s\n", 11, spd->config, + " spd->config, * 11 DIMM Configuration type *"); + printf("%-3d : %02x %s\n", 12, spd->refresh, + " spd->refresh, * 12 Refresh Rate/Type *"); + printf("%-3d : %02x %s\n", 13, spd->primw, + " spd->primw, * 13 Primary SDRAM Width *"); + printf("%-3d : %02x %s\n", 14, spd->ecw, + " spd->ecw, * 14 Error Checking SDRAM width *"); + printf("%-3d : %02x %s\n", 15, spd->min_delay, + " spd->min_delay, * 15 Back to Back Random Access *"); + printf("%-3d : %02x %s\n", 16, spd->burstl, + " spd->burstl, * 16 Burst Lengths Supported *"); + printf("%-3d : %02x %s\n", 17, spd->nbanks, + " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); + printf("%-3d : %02x %s\n", 18, spd->cas_lat, + " spd->cas_lat, * 18 CAS# Latencies Supported *"); + printf("%-3d : %02x %s\n", 19, spd->cs_lat, + " spd->cs_lat, * 19 Chip Select Latency *"); + printf("%-3d : %02x %s\n", 20, spd->write_lat, + " spd->write_lat, * 20 Write Latency/Recovery *"); + printf("%-3d : %02x %s\n", 21, spd->mod_attr, + " spd->mod_attr, * 21 SDRAM Module Attributes *"); + printf("%-3d : %02x %s\n", 22, spd->dev_attr, + " spd->dev_attr, * 22 SDRAM Device Attributes *"); + printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, + " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); + printf("%-3d : %02x %s\n", 24, spd->clk_access2, + " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); + printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, + " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); + printf("%-3d : %02x %s\n", 26, spd->clk_access3, + " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); + printf("%-3d : %02x %s\n", 27, spd->trp, + " spd->trp, * 27 Min Row Precharge Time (tRP)*"); + printf("%-3d : %02x %s\n", 28, spd->trrd, + " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); + printf("%-3d : %02x %s\n", 29, spd->trcd, + " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); + printf("%-3d : %02x %s\n", 30, spd->tras, + " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); + printf("%-3d : %02x %s\n", 31, spd->bank_dens, + " spd->bank_dens, * 31 Density of each bank on module *"); + printf("%-3d : %02x %s\n", 32, spd->ca_setup, + " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); + printf("%-3d : %02x %s\n", 33, spd->ca_hold, + " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); + printf("%-3d : %02x %s\n", 34, spd->data_setup, + " spd->data_setup, * 34 Data signal input setup time *"); + printf("%-3d : %02x %s\n", 35, spd->data_hold, + " spd->data_hold, * 35 Data signal input hold time *"); + printf("%-3d : %02x %s\n", 36, spd->res_36_40[0], + " spd->res_36_40[0], * 36 Reserved / tWR *"); + printf("%-3d : %02x %s\n", 37, spd->res_36_40[1], + " spd->res_36_40[1], * 37 Reserved / tWTR *"); + printf("%-3d : %02x %s\n", 38, spd->res_36_40[2], + " spd->res_36_40[2], * 38 Reserved / tRTP *"); + printf("%-3d : %02x %s\n", 39, spd->res_36_40[3], + " spd->res_36_40[3], * 39 Reserved / mem_probe *"); + printf("%-3d : %02x %s\n", 40, spd->res_36_40[4], + " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); + printf("%-3d : %02x %s\n", 41, spd->trc, + " spd->trc, * 41 Min Active to Auto refresh time tRC *"); + printf("%-3d : %02x %s\n", 42, spd->trfc, + " spd->trfc, * 42 Min Auto to Active period tRFC *"); + printf("%-3d : %02x %s\n", 43, spd->tckmax, + " spd->tckmax, * 43 Max device cycle time tCKmax *"); + printf("%-3d : %02x %s\n", 44, spd->tdqsq, + " spd->tdqsq, * 44 Max DQS to DQ skew *"); + printf("%-3d : %02x %s\n", 45, spd->tqhs, + " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); + printf("%-3d : %02x %s\n", 46, spd->res_46, + " spd->res_46, * 46 Reserved/ PLL Relock time *"); + printf("%-3d : %02x %s\n", 47, spd->dimm_height, + " spd->dimm_height * 47 SDRAM DIMM Height *"); + + printf("%-3d-%3d: ", 48, 61); + + for (i = 0; i < 14; i++) + printf("%02x", spd->res_48_61[i]); + + printf(" * 48-61 IDD in SPD and Reserved space *\n"); + + printf("%-3d : %02x %s\n", 62, spd->spd_rev, + " spd->spd_rev, * 62 SPD Data Revision Code *"); + printf("%-3d : %02x %s\n", 63, spd->cksum, + " spd->cksum, * 63 Checksum for bytes 0-62 *"); + printf("%-3d-%3d: ", 64, 71); + + for (i = 0; i < 8; i++) + printf("%02x", spd->mid[i]); + + printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); + printf("%-3d : %02x %s\n", 72, spd->mloc, + " spd->mloc, * 72 Manufacturing Location *"); + + printf("%-3d-%3d: >>", 73, 90); + + for (i = 0; i < 18; i++) + printf("%c", spd->mpart[i]); + + printf("<<* 73 Manufacturer's Part Number *\n"); + + printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], + "* 91 Revision Code *"); + printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], + "* 93 Manufacturing Date *"); + printf("%-3d-%3d: ", 95, 98); + + for (i = 0; i < 4; i++) + printf("%02x", spd->sernum[i]); + + printf("* 95 Assembly Serial Number *\n"); + + printf("%-3d-%3d: ", 99, 127); + + for (i = 0; i < 27; i++) + printf("%02x", spd->mspec[i]); + + printf("* 99 Manufacturer Specific Data *\n"); +} +#endif + +#ifdef CONFIG_SYS_FSL_DDR2 +void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) +{ + unsigned int i; + + printf("%-3d : %02x %s\n", 0, spd->info_size, + " spd->info_size, * 0 # bytes written into serial memory *"); + printf("%-3d : %02x %s\n", 1, spd->chip_size, + " spd->chip_size, * 1 Total # bytes of SPD memory device *"); + printf("%-3d : %02x %s\n", 2, spd->mem_type, + " spd->mem_type, * 2 Fundamental memory type *"); + printf("%-3d : %02x %s\n", 3, spd->nrow_addr, + " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); + printf("%-3d : %02x %s\n", 4, spd->ncol_addr, + " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); + printf("%-3d : %02x %s\n", 5, spd->mod_ranks, + " spd->mod_ranks * 5 # of Module Rows on this assembly *"); + printf("%-3d : %02x %s\n", 6, spd->dataw, + " spd->dataw, * 6 Data Width of this assembly *"); + printf("%-3d : %02x %s\n", 7, spd->res_7, + " spd->res_7, * 7 Reserved *"); + printf("%-3d : %02x %s\n", 8, spd->voltage, + " spd->voltage, * 8 Voltage intf std of this assembly *"); + printf("%-3d : %02x %s\n", 9, spd->clk_cycle, + " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); + printf("%-3d : %02x %s\n", 10, spd->clk_access, + " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); + printf("%-3d : %02x %s\n", 11, spd->config, + " spd->config, * 11 DIMM Configuration type *"); + printf("%-3d : %02x %s\n", 12, spd->refresh, + " spd->refresh, * 12 Refresh Rate/Type *"); + printf("%-3d : %02x %s\n", 13, spd->primw, + " spd->primw, * 13 Primary SDRAM Width *"); + printf("%-3d : %02x %s\n", 14, spd->ecw, + " spd->ecw, * 14 Error Checking SDRAM width *"); + printf("%-3d : %02x %s\n", 15, spd->res_15, + " spd->res_15, * 15 Reserved *"); + printf("%-3d : %02x %s\n", 16, spd->burstl, + " spd->burstl, * 16 Burst Lengths Supported *"); + printf("%-3d : %02x %s\n", 17, spd->nbanks, + " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); + printf("%-3d : %02x %s\n", 18, spd->cas_lat, + " spd->cas_lat, * 18 CAS# Latencies Supported *"); + printf("%-3d : %02x %s\n", 19, spd->mech_char, + " spd->mech_char, * 19 Mechanical Characteristics *"); + printf("%-3d : %02x %s\n", 20, spd->dimm_type, + " spd->dimm_type, * 20 DIMM type *"); + printf("%-3d : %02x %s\n", 21, spd->mod_attr, + " spd->mod_attr, * 21 SDRAM Module Attributes *"); + printf("%-3d : %02x %s\n", 22, spd->dev_attr, + " spd->dev_attr, * 22 SDRAM Device Attributes *"); + printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, + " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); + printf("%-3d : %02x %s\n", 24, spd->clk_access2, + " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); + printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, + " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); + printf("%-3d : %02x %s\n", 26, spd->clk_access3, + " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); + printf("%-3d : %02x %s\n", 27, spd->trp, + " spd->trp, * 27 Min Row Precharge Time (tRP)*"); + printf("%-3d : %02x %s\n", 28, spd->trrd, + " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); + printf("%-3d : %02x %s\n", 29, spd->trcd, + " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); + printf("%-3d : %02x %s\n", 30, spd->tras, + " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); + printf("%-3d : %02x %s\n", 31, spd->rank_dens, + " spd->rank_dens, * 31 Density of each rank on module *"); + printf("%-3d : %02x %s\n", 32, spd->ca_setup, + " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); + printf("%-3d : %02x %s\n", 33, spd->ca_hold, + " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); + printf("%-3d : %02x %s\n", 34, spd->data_setup, + " spd->data_setup, * 34 Data signal input setup time *"); + printf("%-3d : %02x %s\n", 35, spd->data_hold, + " spd->data_hold, * 35 Data signal input hold time *"); + printf("%-3d : %02x %s\n", 36, spd->twr, + " spd->twr, * 36 Write Recovery time tWR *"); + printf("%-3d : %02x %s\n", 37, spd->twtr, + " spd->twtr, * 37 Int write to read delay tWTR *"); + printf("%-3d : %02x %s\n", 38, spd->trtp, + " spd->trtp, * 38 Int read to precharge delay tRTP *"); + printf("%-3d : %02x %s\n", 39, spd->mem_probe, + " spd->mem_probe, * 39 Mem analysis probe characteristics *"); + printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext, + " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); + printf("%-3d : %02x %s\n", 41, spd->trc, + " spd->trc, * 41 Min Active to Auto refresh time tRC *"); + printf("%-3d : %02x %s\n", 42, spd->trfc, + " spd->trfc, * 42 Min Auto to Active period tRFC *"); + printf("%-3d : %02x %s\n", 43, spd->tckmax, + " spd->tckmax, * 43 Max device cycle time tCKmax *"); + printf("%-3d : %02x %s\n", 44, spd->tdqsq, + " spd->tdqsq, * 44 Max DQS to DQ skew *"); + printf("%-3d : %02x %s\n", 45, spd->tqhs, + " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); + printf("%-3d : %02x %s\n", 46, spd->pll_relock, + " spd->pll_relock, * 46 PLL Relock time *"); + printf("%-3d : %02x %s\n", 47, spd->t_casemax, + " spd->t_casemax, * 47 t_casemax *"); + printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram, + " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package " + "from Top (Case) to Ambient (Psi T-A DRAM) *"); + printf("%-3d : %02x %s\n", 49, spd->dt0_mode, + " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " + "Ambient due to Activate-Precharge/Mode Bits " + "(DT0/Mode Bits) *)"); + printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q, + " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from " + "Ambient due to Precharge/Quiet Standby " + "(DT2N/DT2Q) *"); + printf("%-3d : %02x %s\n", 51, spd->dt2p, + " spd->dt2p, * 51 DRAM Case Temperature Rise from " + "Ambient due to Precharge Power-Down (DT2P) *"); + printf("%-3d : %02x %s\n", 52, spd->dt3n, + " spd->dt3n, * 52 DRAM Case Temperature Rise from " + "Ambient due to Active Standby (DT3N) *"); + printf("%-3d : %02x %s\n", 53, spd->dt3pfast, + " spd->dt3pfast, * 53 DRAM Case Temperature Rise from " + "Ambient due to Active Power-Down with Fast PDN Exit " + "(DT3Pfast) *"); + printf("%-3d : %02x %s\n", 54, spd->dt3pslow, + " spd->dt3pslow, * 54 DRAM Case Temperature Rise from " + "Ambient due to Active Power-Down with Slow PDN Exit " + "(DT3Pslow) *"); + printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w, + " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from " + "Ambient due to Page Open Burst Read/DT4R4W Mode Bit " + "(DT4R/DT4R4W Mode Bit) *"); + printf("%-3d : %02x %s\n", 56, spd->dt5b, + " spd->dt5b, * 56 DRAM Case Temperature Rise from " + "Ambient due to Burst Refresh (DT5B) *"); + printf("%-3d : %02x %s\n", 57, spd->dt7, + " spd->dt7, * 57 DRAM Case Temperature Rise from " + "Ambient due to Bank Interleave Reads with " + "Auto-Precharge (DT7) *"); + printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll, + " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form" + " Top (Case) to Ambient (Psi T-A PLL) *"); + printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg, + " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package" + " from Top (Case) to Ambient (Psi T-A Register) *"); + printf("%-3d : %02x %s\n", 60, spd->dtpllactive, + " spd->dtpllactive, * 60 PLL Case Temperature Rise from " + "Ambient due to PLL Active (DT PLL Active) *"); + printf("%-3d : %02x %s\n", 61, spd->dtregact, + " spd->dtregact, " + "* 61 Register Case Temperature Rise from Ambient due to " + "Register Active/Mode Bit (DT Register Active/Mode Bit) *"); + printf("%-3d : %02x %s\n", 62, spd->spd_rev, + " spd->spd_rev, * 62 SPD Data Revision Code *"); + printf("%-3d : %02x %s\n", 63, spd->cksum, + " spd->cksum, * 63 Checksum for bytes 0-62 *"); + + printf("%-3d-%3d: ", 64, 71); + + for (i = 0; i < 8; i++) + printf("%02x", spd->mid[i]); + + printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); + + printf("%-3d : %02x %s\n", 72, spd->mloc, + " spd->mloc, * 72 Manufacturing Location *"); + + printf("%-3d-%3d: >>", 73, 90); + for (i = 0; i < 18; i++) + printf("%c", spd->mpart[i]); + + + printf("<<* 73 Manufacturer's Part Number *\n"); + + printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], + "* 91 Revision Code *"); + printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], + "* 93 Manufacturing Date *"); + printf("%-3d-%3d: ", 95, 98); + + for (i = 0; i < 4; i++) + printf("%02x", spd->sernum[i]); + + printf("* 95 Assembly Serial Number *\n"); + + printf("%-3d-%3d: ", 99, 127); + for (i = 0; i < 27; i++) + printf("%02x", spd->mspec[i]); + + + printf("* 99 Manufacturer Specific Data *\n"); +} +#endif + +#ifdef CONFIG_SYS_FSL_DDR3 +void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) +{ + unsigned int i; + + /* General Section: Bytes 0-59 */ + +#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); +#define PRINT_NNXXS(n0, n1, x0, x1, s) \ + printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); + + PRINT_NXS(0, spd->info_size_crc, + "info_size_crc bytes written into serial memory, " + "CRC coverage"); + PRINT_NXS(1, spd->spd_rev, + "spd_rev SPD Revision"); + PRINT_NXS(2, spd->mem_type, + "mem_type Key Byte / DRAM Device Type"); + PRINT_NXS(3, spd->module_type, + "module_type Key Byte / Module Type"); + PRINT_NXS(4, spd->density_banks, + "density_banks SDRAM Density and Banks"); + PRINT_NXS(5, spd->addressing, + "addressing SDRAM Addressing"); + PRINT_NXS(6, spd->module_vdd, + "module_vdd Module Nominal Voltage, VDD"); + PRINT_NXS(7, spd->organization, + "organization Module Organization"); + PRINT_NXS(8, spd->bus_width, + "bus_width Module Memory Bus Width"); + PRINT_NXS(9, spd->ftb_div, + "ftb_div Fine Timebase (FTB) Dividend / Divisor"); + PRINT_NXS(10, spd->mtb_dividend, + "mtb_dividend Medium Timebase (MTB) Dividend"); + PRINT_NXS(11, spd->mtb_divisor, + "mtb_divisor Medium Timebase (MTB) Divisor"); + PRINT_NXS(12, spd->tck_min, + "tck_min SDRAM Minimum Cycle Time"); + PRINT_NXS(13, spd->res_13, + "res_13 Reserved"); + PRINT_NXS(14, spd->caslat_lsb, + "caslat_lsb CAS Latencies Supported, LSB"); + PRINT_NXS(15, spd->caslat_msb, + "caslat_msb CAS Latencies Supported, MSB"); + PRINT_NXS(16, spd->taa_min, + "taa_min Min CAS Latency Time"); + PRINT_NXS(17, spd->twr_min, + "twr_min Min Write REcovery Time"); + PRINT_NXS(18, spd->trcd_min, + "trcd_min Min RAS# to CAS# Delay Time"); + PRINT_NXS(19, spd->trrd_min, + "trrd_min Min Row Active to Row Active Delay Time"); + PRINT_NXS(20, spd->trp_min, + "trp_min Min Row Precharge Delay Time"); + PRINT_NXS(21, spd->tras_trc_ext, + "tras_trc_ext Upper Nibbles for tRAS and tRC"); + PRINT_NXS(22, spd->tras_min_lsb, + "tras_min_lsb Min Active to Precharge Delay Time, LSB"); + PRINT_NXS(23, spd->trc_min_lsb, + "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB"); + PRINT_NXS(24, spd->trfc_min_lsb, + "trfc_min_lsb Min Refresh Recovery Delay Time LSB"); + PRINT_NXS(25, spd->trfc_min_msb, + "trfc_min_msb Min Refresh Recovery Delay Time MSB"); + PRINT_NXS(26, spd->twtr_min, + "twtr_min Min Internal Write to Read Command Delay Time"); + PRINT_NXS(27, spd->trtp_min, + "trtp_min " + "Min Internal Read to Precharge Command Delay Time"); + PRINT_NXS(28, spd->tfaw_msb, + "tfaw_msb Upper Nibble for tFAW"); + PRINT_NXS(29, spd->tfaw_min, + "tfaw_min Min Four Activate Window Delay Time"); + PRINT_NXS(30, spd->opt_features, + "opt_features SDRAM Optional Features"); + PRINT_NXS(31, spd->therm_ref_opt, + "therm_ref_opt SDRAM Thermal and Refresh Opts"); + PRINT_NXS(32, spd->therm_sensor, + "therm_sensor SDRAM Thermal Sensor"); + PRINT_NXS(33, spd->device_type, + "device_type SDRAM Device Type"); + PRINT_NXS(34, spd->fine_tck_min, + "fine_tck_min Fine offset for tCKmin"); + PRINT_NXS(35, spd->fine_taa_min, + "fine_taa_min Fine offset for tAAmin"); + PRINT_NXS(36, spd->fine_trcd_min, + "fine_trcd_min Fine offset for tRCDmin"); + PRINT_NXS(37, spd->fine_trp_min, + "fine_trp_min Fine offset for tRPmin"); + PRINT_NXS(38, spd->fine_trc_min, + "fine_trc_min Fine offset for tRCmin"); + + printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ + + for (i = 39; i <= 59; i++) + printf("%02x ", spd->res_39_59[i - 39]); + + puts("\n"); + + switch (spd->module_type) { + case 0x02: /* UDIMM */ + case 0x03: /* SO-DIMM */ + case 0x04: /* Micro-DIMM */ + case 0x06: /* Mini-UDIMM */ + PRINT_NXS(60, spd->mod_section.unbuffered.mod_height, + "mod_height (Unbuffered) Module Nominal Height"); + PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness, + "mod_thickness (Unbuffered) Module Maximum Thickness"); + PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card, + "ref_raw_card (Unbuffered) Reference Raw Card Used"); + PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping, + "addr_mapping (Unbuffered) Address mapping from " + "Edge Connector to DRAM"); + break; + case 0x01: /* RDIMM */ + case 0x05: /* Mini-RDIMM */ + PRINT_NXS(60, spd->mod_section.registered.mod_height, + "mod_height (Registered) Module Nominal Height"); + PRINT_NXS(61, spd->mod_section.registered.mod_thickness, + "mod_thickness (Registered) Module Maximum Thickness"); + PRINT_NXS(62, spd->mod_section.registered.ref_raw_card, + "ref_raw_card (Registered) Reference Raw Card Used"); + PRINT_NXS(63, spd->mod_section.registered.modu_attr, + "modu_attr (Registered) DIMM Module Attributes"); + PRINT_NXS(64, spd->mod_section.registered.thermal, + "thermal (Registered) Thermal Heat " + "Spreader Solution"); + PRINT_NXS(65, spd->mod_section.registered.reg_id_lo, + "reg_id_lo (Registered) Register Manufacturer ID " + "Code, LSB"); + PRINT_NXS(66, spd->mod_section.registered.reg_id_hi, + "reg_id_hi (Registered) Register Manufacturer ID " + "Code, MSB"); + PRINT_NXS(67, spd->mod_section.registered.reg_rev, + "reg_rev (Registered) Register " + "Revision Number"); + PRINT_NXS(68, spd->mod_section.registered.reg_type, + "reg_type (Registered) Register Type"); + for (i = 69; i <= 76; i++) { + printf("%-3d : %02x rcw[%d]\n", i, + spd->mod_section.registered.rcw[i-69], i-69); + } + break; + default: + /* Module-specific Section, Unsupported Module Type */ + printf("%-3d-%3d: ", 60, 116); + + for (i = 60; i <= 116; i++) + printf("%02x", spd->mod_section.uc[i - 60]); + + break; + } + + /* Unique Module ID: Bytes 117-125 */ + PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); + PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); + PRINT_NXS(119, spd->mloc, "Mfg Location"); + PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date"); + + printf("%-3d-%3d: ", 122, 125); + + for (i = 122; i <= 125; i++) + printf("%02x ", spd->sernum[i - 122]); + printf(" Module Serial Number\n"); + + /* CRC: Bytes 126-127 */ + PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); + + /* Other Manufacturer Fields and User Space: Bytes 128-255 */ + printf("%-3d-%3d: ", 128, 145); + for (i = 128; i <= 145; i++) + printf("%02x ", spd->mpart[i - 128]); + printf(" Mfg's Module Part Number\n"); + + PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1], + "Module Revision code"); + + PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); + PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); + + printf("%-3d-%3d: ", 150, 175); + for (i = 150; i <= 175; i++) + printf("%02x ", spd->msd[i - 150]); + printf(" Mfg's Specific Data\n"); + + printf("%-3d-%3d: ", 176, 255); + for (i = 176; i <= 255; i++) + printf("%02x", spd->cust[i - 176]); + printf(" Mfg's Specific Data\n"); + +} +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 +void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd) +{ + unsigned int i; + + /* General Section: Bytes 0-127 */ + +#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); +#define PRINT_NNXXS(n0, n1, x0, x1, s) \ + printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); + + PRINT_NXS(0, spd->info_size_crc, + "info_size_crc bytes written into serial memory, CRC coverage"); + PRINT_NXS(1, spd->spd_rev, + "spd_rev SPD Revision"); + PRINT_NXS(2, spd->mem_type, + "mem_type Key Byte / DRAM Device Type"); + PRINT_NXS(3, spd->module_type, + "module_type Key Byte / Module Type"); + PRINT_NXS(4, spd->density_banks, + "density_banks SDRAM Density and Banks"); + PRINT_NXS(5, spd->addressing, + "addressing SDRAM Addressing"); + PRINT_NXS(6, spd->package_type, + "package_type Package type"); + PRINT_NXS(7, spd->opt_feature, + "opt_feature Optional features"); + PRINT_NXS(8, spd->thermal_ref, + "thermal_ref Thermal and Refresh options"); + PRINT_NXS(9, spd->oth_opt_features, + "oth_opt_features Other SDRAM optional features"); + PRINT_NXS(10, spd->res_10, + "res_10 Reserved"); + PRINT_NXS(11, spd->module_vdd, + "module_vdd Module Nominal Voltage, VDD"); + PRINT_NXS(12, spd->organization, + "organization Module Organization"); + PRINT_NXS(13, spd->bus_width, + "bus_width Module Memory Bus Width"); + PRINT_NXS(14, spd->therm_sensor, + "therm_sensor Module Thermal Sensor"); + PRINT_NXS(15, spd->ext_type, + "ext_type Extended module type"); + PRINT_NXS(16, spd->res_16, + "res_16 Reserved"); + PRINT_NXS(17, spd->timebases, + "timebases MTb and FTB"); + PRINT_NXS(18, spd->tck_min, + "tck_min tCKAVGmin"); + PRINT_NXS(19, spd->tck_max, + "tck_max TCKAVGmax"); + PRINT_NXS(20, spd->caslat_b1, + "caslat_b1 CAS latencies, 1st byte"); + PRINT_NXS(21, spd->caslat_b2, + "caslat_b2 CAS latencies, 2nd byte"); + PRINT_NXS(22, spd->caslat_b3, + "caslat_b3 CAS latencies, 3rd byte "); + PRINT_NXS(23, spd->caslat_b4, + "caslat_b4 CAS latencies, 4th byte"); + PRINT_NXS(24, spd->taa_min, + "taa_min Min CAS Latency Time"); + PRINT_NXS(25, spd->trcd_min, + "trcd_min Min RAS# to CAS# Delay Time"); + PRINT_NXS(26, spd->trp_min, + "trp_min Min Row Precharge Delay Time"); + PRINT_NXS(27, spd->tras_trc_ext, + "tras_trc_ext Upper Nibbles for tRAS and tRC"); + PRINT_NXS(28, spd->tras_min_lsb, + "tras_min_lsb tRASmin, lsb"); + PRINT_NXS(29, spd->trc_min_lsb, + "trc_min_lsb tRCmin, lsb"); + PRINT_NXS(30, spd->trfc1_min_lsb, + "trfc1_min_lsb Min Refresh Recovery Delay Time, LSB"); + PRINT_NXS(31, spd->trfc1_min_msb, + "trfc1_min_msb Min Refresh Recovery Delay Time, MSB "); + PRINT_NXS(32, spd->trfc2_min_lsb, + "trfc2_min_lsb Min Refresh Recovery Delay Time, LSB"); + PRINT_NXS(33, spd->trfc2_min_msb, + "trfc2_min_msb Min Refresh Recovery Delay Time, MSB"); + PRINT_NXS(34, spd->trfc4_min_lsb, + "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB"); + PRINT_NXS(35, spd->trfc4_min_msb, + "trfc4_min_msb Min Refresh Recovery Delay Time, MSB"); + PRINT_NXS(36, spd->tfaw_msb, + "tfaw_msb Upper Nibble for tFAW"); + PRINT_NXS(37, spd->tfaw_min, + "tfaw_min tFAW, lsb"); + PRINT_NXS(38, spd->trrds_min, + "trrds_min tRRD_Smin, MTB"); + PRINT_NXS(39, spd->trrdl_min, + "trrdl_min tRRD_Lmin, MTB"); + PRINT_NXS(40, spd->tccdl_min, + "tccdl_min tCCS_Lmin, MTB"); + + printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */ + for (i = 41; i <= 59; i++) + printf("%02x ", spd->res_41[i - 41]); + + puts("\n"); + printf("%-3d-%3d: ", 60, 77); + for (i = 60; i <= 77; i++) + printf("%02x ", spd->mapping[i - 60]); + puts(" mapping[] Connector to SDRAM bit map\n"); + + PRINT_NXS(117, spd->fine_tccdl_min, + "fine_tccdl_min Fine offset for tCCD_Lmin"); + PRINT_NXS(118, spd->fine_trrdl_min, + "fine_trrdl_min Fine offset for tRRD_Lmin"); + PRINT_NXS(119, spd->fine_trrds_min, + "fine_trrds_min Fine offset for tRRD_Smin"); + PRINT_NXS(120, spd->fine_trc_min, + "fine_trc_min Fine offset for tRCmin"); + PRINT_NXS(121, spd->fine_trp_min, + "fine_trp_min Fine offset for tRPmin"); + PRINT_NXS(122, spd->fine_trcd_min, + "fine_trcd_min Fine offset for tRCDmin"); + PRINT_NXS(123, spd->fine_taa_min, + "fine_taa_min Fine offset for tAAmin"); + PRINT_NXS(124, spd->fine_tck_max, + "fine_tck_max Fine offset for tCKAVGmax"); + PRINT_NXS(125, spd->fine_tck_min, + "fine_tck_min Fine offset for tCKAVGmin"); + + /* CRC: Bytes 126-127 */ + PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); + + switch (spd->module_type) { + case 0x02: /* UDIMM */ + case 0x03: /* SO-DIMM */ + PRINT_NXS(128, spd->mod_section.unbuffered.mod_height, + "mod_height (Unbuffered) Module Nominal Height"); + PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness, + "mod_thickness (Unbuffered) Module Maximum Thickness"); + PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card, + "ref_raw_card (Unbuffered) Reference Raw Card Used"); + PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping, + "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM"); + PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0], + spd->mod_section.unbuffered.crc[1], " Module CRC"); + break; + case 0x01: /* RDIMM */ + PRINT_NXS(128, spd->mod_section.registered.mod_height, + "mod_height (Registered) Module Nominal Height"); + PRINT_NXS(129, spd->mod_section.registered.mod_thickness, + "mod_thickness (Registered) Module Maximum Thickness"); + PRINT_NXS(130, spd->mod_section.registered.ref_raw_card, + "ref_raw_card (Registered) Reference Raw Card Used"); + PRINT_NXS(131, spd->mod_section.registered.modu_attr, + "modu_attr (Registered) DIMM Module Attributes"); + PRINT_NXS(132, spd->mod_section.registered.thermal, + "thermal (Registered) Thermal Heat Spreader Solution"); + PRINT_NXS(133, spd->mod_section.registered.reg_id_lo, + "reg_id_lo (Registered) Register Manufacturer ID Code, LSB"); + PRINT_NXS(134, spd->mod_section.registered.reg_id_hi, + "reg_id_hi (Registered) Register Manufacturer ID Code, MSB"); + PRINT_NXS(135, spd->mod_section.registered.reg_rev, + "reg_rev (Registered) Register Revision Number"); + PRINT_NXS(136, spd->mod_section.registered.reg_map, + "reg_map (Registered) Address mapping"); + PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0], + spd->mod_section.registered.crc[1], " Module CRC"); + break; + case 0x04: /* LRDIMM */ + PRINT_NXS(128, spd->mod_section.loadreduced.mod_height, + "mod_height (Loadreduced) Module Nominal Height"); + PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness, + "mod_thickness (Loadreduced) Module Maximum Thickness"); + PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card, + "ref_raw_card (Loadreduced) Reference Raw Card Used"); + PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr, + "modu_attr (Loadreduced) DIMM Module Attributes"); + PRINT_NXS(132, spd->mod_section.loadreduced.thermal, + "thermal (Loadreduced) Thermal Heat Spreader Solution"); + PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo, + "reg_id_lo (Loadreduced) Register Manufacturer ID Code, LSB"); + PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi, + "reg_id_hi (Loadreduced) Register Manufacturer ID Code, MSB"); + PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev, + "reg_rev (Loadreduced) Register Revision Number"); + PRINT_NXS(136, spd->mod_section.loadreduced.reg_map, + "reg_map (Loadreduced) Address mapping"); + PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv, + "reg_drv (Loadreduced) Reg output drive strength"); + PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck, + "reg_drv_ck (Loadreduced) Reg output drive strength for CK"); + PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev, + "data_buf_rev (Loadreduced) Data Buffer Revision Numbe"); + PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0, + "vrefqe_r0 (Loadreduced) DRAM VrefDQ for Package Rank 0"); + PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1, + "vrefqe_r1 (Loadreduced) DRAM VrefDQ for Package Rank 1"); + PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2, + "vrefqe_r2 (Loadreduced) DRAM VrefDQ for Package Rank 2"); + PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3, + "vrefqe_r3 (Loadreduced) DRAM VrefDQ for Package Rank 3"); + PRINT_NXS(144, spd->mod_section.loadreduced.data_intf, + "data_intf (Loadreduced) Data Buffer VrefDQ for DRAM Interface"); + PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866, + "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); + PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400, + "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); + PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200, + "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); + PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv, + "dram_drv (Loadreduced) DRAM Drive Strength"); + PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866, + "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); + PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400, + "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); + PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200, + "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); + PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866, + "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)"); + PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400, + "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)"); + PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200, + "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)"); + PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0], + spd->mod_section.loadreduced.crc[1], + " Module CRC"); + break; + default: + /* Module-specific Section, Unsupported Module Type */ + printf("%-3d-%3d: ", 128, 255); + + for (i = 128; i <= 255; i++) + printf("%02x", spd->mod_section.uc[i - 128]); + + break; + } + + /* Unique Module ID: Bytes 320-383 */ + PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); + PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); + PRINT_NXS(322, spd->mloc, "Mfg Location"); + PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date"); + + printf("%-3d-%3d: ", 325, 328); + + for (i = 325; i <= 328; i++) + printf("%02x ", spd->sernum[i - 325]); + printf(" Module Serial Number\n"); + + printf("%-3d-%3d: ", 329, 348); + for (i = 329; i <= 348; i++) + printf("%02x ", spd->mpart[i - 329]); + printf(" Mfg's Module Part Number\n"); + + PRINT_NXS(349, spd->mrev, "Module Revision code"); + PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); + PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); + PRINT_NXS(352, spd->stepping, "DRAM stepping"); + + printf("%-3d-%3d: ", 353, 381); + for (i = 353; i <= 381; i++) + printf("%02x ", spd->msd[i - 353]); + printf(" Mfg's Specific Data\n"); +} +#endif + +static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) +{ +#if defined(CONFIG_SYS_FSL_DDR1) + ddr1_spd_dump(spd); +#elif defined(CONFIG_SYS_FSL_DDR2) + ddr2_spd_dump(spd); +#elif defined(CONFIG_SYS_FSL_DDR3) + ddr3_spd_dump(spd); +#elif defined(CONFIG_SYS_FSL_DDR4) + ddr4_spd_dump(spd); +#endif +} + +static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo, + unsigned int ctrl_mask, + unsigned int dimm_mask, + unsigned int do_mask) +{ + unsigned int i, j, retval; + + /* STEP 1: DIMM SPD data */ + if (do_mask & STEP_GET_SPD) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + if (!(dimm_mask & (1 << j))) + continue; + + printf("SPD info: Controller=%u " + "DIMM=%u\n", i, j); + generic_spd_dump( + &(pinfo->spd_installed_dimms[i][j])); + printf("\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 2: DIMM Parameters */ + if (do_mask & STEP_COMPUTE_DIMM_PARMS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + if (!(dimm_mask & (1 << j))) + continue; + printf("DIMM parameters: Controller=%u " + "DIMM=%u\n", i, j); + print_dimm_parameters( + &(pinfo->dimm_params[i][j])); + printf("\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 3: Common Parameters */ + if (do_mask & STEP_COMPUTE_COMMON_PARMS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("\"lowest common\" DIMM parameters: " + "Controller=%u\n", i); + print_lowest_common_dimm_parameters( + &pinfo->common_timing_params[i]); + printf("\n"); + } + printf("\n"); + } + + /* STEP 4: User Configuration Options */ + if (do_mask & STEP_GATHER_OPTS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("User Config Options: Controller=%u\n", i); + print_memctl_options(&pinfo->memctl_opts[i]); + printf("\n"); + } + printf("\n"); + } + + /* STEP 5: Address assignment */ + if (do_mask & STEP_ASSIGN_ADDRESSES) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + printf("Address Assignment: Controller=%u " + "DIMM=%u\n", i, j); + printf("Don't have this functionality yet\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 6: computed controller register values */ + if (do_mask & STEP_COMPUTE_REGS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("Computed Register Values: Controller=%u\n", i); + print_fsl_memctl_config_regs( + &pinfo->fsl_ddr_config_reg[i]); + retval = check_fsl_memctl_config_regs( + &pinfo->fsl_ddr_config_reg[i]); + if (retval) { + printf("check_fsl_memctl_config_regs " + "result = %u\n", retval); + } + printf("\n"); + } + printf("\n"); + } +} + +struct data_strings { + const char *data_name; + unsigned int step_mask; + unsigned int dimm_number_required; +}; + +#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm} + +static unsigned int fsl_ddr_parse_interactive_cmd( + char **argv, + int argc, + unsigned int *pstep_mask, + unsigned int *pctlr_mask, + unsigned int *pdimm_mask, + unsigned int *pdimm_number_required + ) { + + static const struct data_strings options[] = { + DATA_OPTIONS(spd, STEP_GET_SPD, 1), + DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1), + DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0), + DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0), + DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0), + DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + unsigned int i, j; + unsigned int error = 0; + + for (i = 1; i < argc; i++) { + unsigned int matched = 0; + + for (j = 0; j < n_opts; j++) { + if (strcmp(options[j].data_name, argv[i]) != 0) + continue; + *pstep_mask |= options[j].step_mask; + *pdimm_number_required = + options[j].dimm_number_required; + matched = 1; + break; + } + + if (matched) + continue; + + if (argv[i][0] == 'c') { + char c = argv[i][1]; + if (isdigit(c)) + *pctlr_mask |= 1 << (c - '0'); + continue; + } + + if (argv[i][0] == 'd') { + char c = argv[i][1]; + if (isdigit(c)) + *pdimm_mask |= 1 << (c - '0'); + continue; + } + + printf("unknown arg %s\n", argv[i]); + *pstep_mask = 0; + error = 1; + break; + } + + return error; +} + +int fsl_ddr_interactive_env_var_exists(void) +{ + char buffer[CONFIG_SYS_CBSIZE]; + + if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0) + return 1; + + return 0; +} + +unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set) +{ + unsigned long long ddrsize; + const char *prompt = "FSL DDR>"; + char buffer[CONFIG_SYS_CBSIZE]; + char buffer2[CONFIG_SYS_CBSIZE]; + char *p = NULL; + char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ + int argc; + unsigned int next_step = STEP_GET_SPD; + const char *usage = { + "commands:\n" + "print print SPD and intermediate computed data\n" + "reset reboot machine\n" + "recompute reload SPD and options to default and recompute regs\n" + "edit modify spd, parameter, or option\n" + "compute recompute registers from current next_step to end\n" + "copy copy parameters\n" + "next_step shows current next_step\n" + "help this message\n" + "go program the memory controller and continue with u-boot\n" + }; + + if (var_is_set) { + if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) { + p = buffer2; + } else { + var_is_set = 0; + } + } + + /* + * The strategy for next_step is that it points to the next + * step in the computation process that needs to be done. + */ + while (1) { + if (var_is_set) { + char *pend = strchr(p, ';'); + if (pend) { + /* found command separator, copy sub-command */ + *pend = '\0'; + strcpy(buffer, p); + p = pend + 1; + } else { + /* separator not found, copy whole string */ + strcpy(buffer, p); + p = NULL; + var_is_set = 0; + } + } else { + /* + * No need to worry for buffer overflow here in + * this function; cli_readline() maxes out at + * CFG_CBSIZE + */ + cli_readline_into_buffer(prompt, buffer, 0); + } + argc = cli_simple_parse_line(buffer, argv); + if (argc == 0) + continue; + + + if (strcmp(argv[0], "help") == 0) { + puts(usage); + continue; + } + + if (strcmp(argv[0], "next_step") == 0) { + printf("next_step = 0x%02X (%s)\n", + next_step, + step_to_string(next_step)); + continue; + } + + if (strcmp(argv[0], "copy") == 0) { + unsigned int error = 0; + unsigned int step_mask = 0; + unsigned int src_ctlr_mask = 0; + unsigned int src_dimm_mask = 0; + unsigned int dimm_number_required = 0; + unsigned int src_ctlr_num = 0; + unsigned int src_dimm_num = 0; + unsigned int dst_ctlr_num = -1; + unsigned int dst_dimm_num = -1; + unsigned int i, num_dest_parms; + + if (argc == 1) { + printf("copy \n"); + continue; + } + + error = fsl_ddr_parse_interactive_cmd( + argv, argc, + &step_mask, + &src_ctlr_mask, + &src_dimm_mask, + &dimm_number_required + ); + + /* XXX: only dimm_number_required and step_mask will + be used by this function. Parse the controller and + DIMM number separately because it is easier. */ + + if (error) + continue; + + /* parse source destination controller / DIMM */ + + num_dest_parms = dimm_number_required ? 2 : 1; + + for (i = 0; i < argc; i++) { + if (argv[i][0] == 'c') { + char c = argv[i][1]; + if (isdigit(c)) { + src_ctlr_num = (c - '0'); + break; + } + } + } + + for (i = 0; i < argc; i++) { + if (argv[i][0] == 'd') { + char c = argv[i][1]; + if (isdigit(c)) { + src_dimm_num = (c - '0'); + break; + } + } + } + + /* parse destination controller / DIMM */ + + for (i = argc - 1; i >= argc - num_dest_parms; i--) { + if (argv[i][0] == 'c') { + char c = argv[i][1]; + if (isdigit(c)) { + dst_ctlr_num = (c - '0'); + break; + } + } + } + + for (i = argc - 1; i >= argc - num_dest_parms; i--) { + if (argv[i][0] == 'd') { + char c = argv[i][1]; + if (isdigit(c)) { + dst_dimm_num = (c - '0'); + break; + } + } + } + + /* TODO: validate inputs */ + + debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n", + src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask); + + + switch (step_mask) { + + case STEP_GET_SPD: + memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]), + &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]), + sizeof(pinfo->spd_installed_dimms[0][0])); + break; + + case STEP_COMPUTE_DIMM_PARMS: + memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]), + &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]), + sizeof(pinfo->dimm_params[0][0])); + break; + + case STEP_COMPUTE_COMMON_PARMS: + memcpy(&(pinfo->common_timing_params[dst_ctlr_num]), + &(pinfo->common_timing_params[src_ctlr_num]), + sizeof(pinfo->common_timing_params[0])); + break; + + case STEP_GATHER_OPTS: + memcpy(&(pinfo->memctl_opts[dst_ctlr_num]), + &(pinfo->memctl_opts[src_ctlr_num]), + sizeof(pinfo->memctl_opts[0])); + break; + + /* someday be able to have addresses to copy addresses... */ + + case STEP_COMPUTE_REGS: + memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]), + &(pinfo->fsl_ddr_config_reg[src_ctlr_num]), + sizeof(pinfo->memctl_opts[0])); + break; + + default: + printf("unexpected step_mask value\n"); + } + + continue; + + } + + if (strcmp(argv[0], "edit") == 0) { + unsigned int error = 0; + unsigned int step_mask = 0; + unsigned int ctlr_mask = 0; + unsigned int dimm_mask = 0; + char *p_element = NULL; + char *p_value = NULL; + unsigned int dimm_number_required = 0; + unsigned int ctrl_num; + unsigned int dimm_num; + + if (argc == 1) { + /* Only the element and value must be last */ + printf("edit " + " \n"); + printf("for spd, specify byte number for " + "element\n"); + continue; + } + + error = fsl_ddr_parse_interactive_cmd( + argv, argc - 2, + &step_mask, + &ctlr_mask, + &dimm_mask, + &dimm_number_required + ); + + if (error) + continue; + + + /* Check arguments */ + + /* ERROR: If no steps were found */ + if (step_mask == 0) { + printf("Error: No valid steps were specified " + "in argument.\n"); + continue; + } + + /* ERROR: If multiple steps were found */ + if (step_mask & (step_mask - 1)) { + printf("Error: Multiple steps specified in " + "argument.\n"); + continue; + } + + /* ERROR: Controller not specified */ + if (ctlr_mask == 0) { + printf("Error: controller number not " + "specified or no element and " + "value specified\n"); + continue; + } + + if (ctlr_mask & (ctlr_mask - 1)) { + printf("Error: multiple controllers " + "specified, %X\n", ctlr_mask); + continue; + } + + /* ERROR: DIMM number not specified */ + if (dimm_number_required && dimm_mask == 0) { + printf("Error: DIMM number number not " + "specified or no element and " + "value specified\n"); + continue; + } + + if (dimm_mask & (dimm_mask - 1)) { + printf("Error: multipled DIMMs specified\n"); + continue; + } + + p_element = argv[argc - 2]; + p_value = argv[argc - 1]; + + ctrl_num = __ilog2(ctlr_mask); + dimm_num = __ilog2(dimm_mask); + + switch (step_mask) { + case STEP_GET_SPD: + { + unsigned int element_num; + unsigned int value; + + element_num = simple_strtoul(p_element, + NULL, 0); + value = simple_strtoul(p_value, + NULL, 0); + fsl_ddr_spd_edit(pinfo, + ctrl_num, + dimm_num, + element_num, + value); + next_step = STEP_COMPUTE_DIMM_PARMS; + } + break; + + case STEP_COMPUTE_DIMM_PARMS: + fsl_ddr_dimm_parameters_edit( + pinfo, ctrl_num, dimm_num, + p_element, p_value); + next_step = STEP_COMPUTE_COMMON_PARMS; + break; + + case STEP_COMPUTE_COMMON_PARMS: + lowest_common_dimm_parameters_edit(pinfo, + ctrl_num, p_element, p_value); + next_step = STEP_GATHER_OPTS; + break; + + case STEP_GATHER_OPTS: + fsl_ddr_options_edit(pinfo, ctrl_num, + p_element, p_value); + next_step = STEP_ASSIGN_ADDRESSES; + break; + + case STEP_ASSIGN_ADDRESSES: + printf("editing of address assignment " + "not yet implemented\n"); + break; + + case STEP_COMPUTE_REGS: + { + fsl_ddr_regs_edit(pinfo, + ctrl_num, + p_element, + p_value); + next_step = STEP_PROGRAM_REGS; + } + break; + + default: + printf("programming error\n"); + while (1) + ; + break; + } + continue; + } + + if (strcmp(argv[0], "reset") == 0) { + /* + * Reboot machine. + * Args don't seem to matter because this + * doesn't return + */ + do_reset(NULL, 0, 0, NULL); + printf("Reset didn't work\n"); + } + + if (strcmp(argv[0], "recompute") == 0) { + /* + * Recalculate everything, starting with + * loading SPD EEPROM from DIMMs + */ + next_step = STEP_GET_SPD; + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + continue; + } + + if (strcmp(argv[0], "compute") == 0) { + /* + * Compute rest of steps starting at + * the current next_step/ + */ + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + continue; + } + + if (strcmp(argv[0], "print") == 0) { + unsigned int error = 0; + unsigned int step_mask = 0; + unsigned int ctlr_mask = 0; + unsigned int dimm_mask = 0; + unsigned int dimm_number_required = 0; + + if (argc == 1) { + printf("print [c] [d] [spd] [dimmparms] " + "[commonparms] [opts] [addresses] [regs]\n"); + continue; + } + + error = fsl_ddr_parse_interactive_cmd( + argv, argc, + &step_mask, + &ctlr_mask, + &dimm_mask, + &dimm_number_required + ); + + if (error) + continue; + + /* If no particular controller was found, print all */ + if (ctlr_mask == 0) + ctlr_mask = 0xFF; + + /* If no particular dimm was found, print all dimms. */ + if (dimm_mask == 0) + dimm_mask = 0xFF; + + /* If no steps were found, print all steps. */ + if (step_mask == 0) + step_mask = STEP_ALL; + + fsl_ddr_printinfo(pinfo, ctlr_mask, + dimm_mask, step_mask); + continue; + } + + if (strcmp(argv[0], "go") == 0) { + if (next_step) + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + break; + } + + printf("unknown command %s\n", argv[0]); + } + + debug("end of memory = %llu\n", (u64)ddrsize); + + return ddrsize; +} diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c new file mode 100644 index 0000000000..73db444615 --- /dev/null +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -0,0 +1,577 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) +static unsigned int +compute_cas_latency(const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms) +{ + unsigned int i; + unsigned int common_caslat; + unsigned int caslat_actual; + unsigned int retry = 16; + unsigned int tmp; + const unsigned int mclk_ps = get_memory_clk_period_ps(); +#ifdef CONFIG_SYS_FSL_DDR3 + const unsigned int taamax = 20000; +#else + const unsigned int taamax = 18000; +#endif + + /* compute the common CAS latency supported between slots */ + tmp = dimm_params[0].caslat_x; + for (i = 1; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) + tmp &= dimm_params[i].caslat_x; + } + common_caslat = tmp; + + /* validate if the memory clk is in the range of dimms */ + if (mclk_ps < outpdimm->tckmin_x_ps) { + printf("DDR clock (MCLK cycle %u ps) is faster than " + "the slowest DIMM(s) (tCKmin %u ps) can support.\n", + mclk_ps, outpdimm->tckmin_x_ps); + } +#ifdef CONFIG_SYS_FSL_DDR4 + if (mclk_ps > outpdimm->tckmax_ps) { + printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n", + mclk_ps, outpdimm->tckmax_ps); + } +#endif + /* determine the acutal cas latency */ + caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps; + /* check if the dimms support the CAS latency */ + while (!(common_caslat & (1 << caslat_actual)) && retry > 0) { + caslat_actual++; + retry--; + } + /* once the caculation of caslat_actual is completed + * we must verify that this CAS latency value does not + * exceed tAAmax, which is 20 ns for all DDR3 speed grades, + * 18ns for all DDR4 speed grades. + */ + if (caslat_actual * mclk_ps > taamax) { + printf("The choosen cas latency %d is too large\n", + caslat_actual); + } + outpdimm->lowest_common_spd_caslat = caslat_actual; + debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual); + + return 0; +} +#else /* for DDR1 and DDR2 */ +static unsigned int +compute_cas_latency(const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms) +{ + int i; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + unsigned int lowest_good_caslat; + unsigned int not_ok; + unsigned int temp1, temp2; + + debug("using mclk_ps = %u\n", mclk_ps); + if (mclk_ps > outpdimm->tckmax_ps) { + printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n", + mclk_ps, outpdimm->tckmax_ps); + } + + /* + * Compute a CAS latency suitable for all DIMMs + * + * Strategy for SPD-defined latencies: compute only + * CAS latency defined by all DIMMs. + */ + + /* + * Step 1: find CAS latency common to all DIMMs using bitwise + * operation. + */ + temp1 = 0xFF; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) { + temp2 = 0; + temp2 |= 1 << dimm_params[i].caslat_x; + temp2 |= 1 << dimm_params[i].caslat_x_minus_1; + temp2 |= 1 << dimm_params[i].caslat_x_minus_2; + /* + * If there was no entry for X-2 (X-1) in + * the SPD, then caslat_x_minus_2 + * (caslat_x_minus_1) contains either 255 or + * 0xFFFFFFFF because that's what the glorious + * __ilog2 function returns for an input of 0. + * On 32-bit PowerPC, left shift counts with bit + * 26 set (that the value of 255 or 0xFFFFFFFF + * will have), cause the destination register to + * be 0. That is why this works. + */ + temp1 &= temp2; + } + } + + /* + * Step 2: check each common CAS latency against tCK of each + * DIMM's SPD. + */ + lowest_good_caslat = 0; + temp2 = 0; + while (temp1) { + not_ok = 0; + temp2 = __ilog2(temp1); + debug("checking common caslat = %u\n", temp2); + + /* Check if this CAS latency will work on all DIMMs at tCK. */ + for (i = 0; i < number_of_dimms; i++) { + if (!dimm_params[i].n_ranks) + continue; + + if (dimm_params[i].caslat_x == temp2) { + if (mclk_ps >= dimm_params[i].tckmin_x_ps) { + debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n", + temp2, i, mclk_ps, + dimm_params[i].tckmin_x_ps); + continue; + } else { + not_ok++; + } + } + + if (dimm_params[i].caslat_x_minus_1 == temp2) { + unsigned int tckmin_x_minus_1_ps + = dimm_params[i].tckmin_x_minus_1_ps; + if (mclk_ps >= tckmin_x_minus_1_ps) { + debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n", + temp2, i, mclk_ps, + tckmin_x_minus_1_ps); + continue; + } else { + not_ok++; + } + } + + if (dimm_params[i].caslat_x_minus_2 == temp2) { + unsigned int tckmin_x_minus_2_ps + = dimm_params[i].tckmin_x_minus_2_ps; + if (mclk_ps >= tckmin_x_minus_2_ps) { + debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n", + temp2, i, mclk_ps, + tckmin_x_minus_2_ps); + continue; + } else { + not_ok++; + } + } + } + + if (!not_ok) + lowest_good_caslat = temp2; + + temp1 &= ~(1 << temp2); + } + + debug("lowest common SPD-defined CAS latency = %u\n", + lowest_good_caslat); + outpdimm->lowest_common_spd_caslat = lowest_good_caslat; + + + /* + * Compute a common 'de-rated' CAS latency. + * + * The strategy here is to find the *highest* dereated cas latency + * with the assumption that all of the DIMMs will support a dereated + * CAS latency higher than or equal to their lowest dereated value. + */ + temp1 = 0; + for (i = 0; i < number_of_dimms; i++) + temp1 = max(temp1, dimm_params[i].caslat_lowest_derated); + + outpdimm->highest_common_derated_caslat = temp1; + debug("highest common dereated CAS latency = %u\n", temp1); + + return 0; +} +#endif + +/* + * compute_lowest_common_dimm_parameters() + * + * Determine the worst-case DIMM timing parameters from the set of DIMMs + * whose parameters have been computed into the array pointed to + * by dimm_params. + */ +unsigned int +compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + const unsigned int number_of_dimms) +{ + unsigned int i, j; + + unsigned int tckmin_x_ps = 0; + unsigned int tckmax_ps = 0xFFFFFFFF; + unsigned int trcd_ps = 0; + unsigned int trp_ps = 0; + unsigned int tras_ps = 0; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + unsigned int taamin_ps = 0; +#endif +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int twr_ps = 15000; + unsigned int trfc1_ps = 0; + unsigned int trfc2_ps = 0; + unsigned int trfc4_ps = 0; + unsigned int trrds_ps = 0; + unsigned int trrdl_ps = 0; + unsigned int tccdl_ps = 0; +#else + unsigned int twr_ps = 0; + unsigned int twtr_ps = 0; + unsigned int trfc_ps = 0; + unsigned int trrd_ps = 0; + unsigned int trtp_ps = 0; +#endif + unsigned int trc_ps = 0; + unsigned int refresh_rate_ps = 0; + unsigned int extended_op_srt = 1; +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + unsigned int tis_ps = 0; + unsigned int tih_ps = 0; + unsigned int tds_ps = 0; + unsigned int tdh_ps = 0; + unsigned int tdqsq_max_ps = 0; + unsigned int tqhs_ps = 0; +#endif + unsigned int temp1, temp2; + unsigned int additive_latency = 0; + + temp1 = 0; + for (i = 0; i < number_of_dimms; i++) { + /* + * If there are no ranks on this DIMM, + * it probably doesn't exist, so skip it. + */ + if (dimm_params[i].n_ranks == 0) { + temp1++; + continue; + } + if (dimm_params[i].n_ranks == 4 && i != 0) { + printf("Found Quad-rank DIMM in wrong bank, ignored." + " Software may not run as expected.\n"); + temp1++; + continue; + } + + /* + * check if quad-rank DIMM is plugged if + * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined + * Only the board with proper design is capable + */ +#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (dimm_params[i].n_ranks == 4 && \ + CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) { + printf("Found Quad-rank DIMM, not able to support."); + temp1++; + continue; + } +#endif + /* + * Find minimum tckmax_ps to find fastest slow speed, + * i.e., this is the slowest the whole system can go. + */ + tckmax_ps = min(tckmax_ps, + (unsigned int)dimm_params[i].tckmax_ps); +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + taamin_ps = max(taamin_ps, + (unsigned int)dimm_params[i].taa_ps); +#endif + tckmin_x_ps = max(tckmin_x_ps, + (unsigned int)dimm_params[i].tckmin_x_ps); + trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps); + trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps); + tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps); +#ifdef CONFIG_SYS_FSL_DDR4 + trfc1_ps = max(trfc1_ps, + (unsigned int)dimm_params[i].trfc1_ps); + trfc2_ps = max(trfc2_ps, + (unsigned int)dimm_params[i].trfc2_ps); + trfc4_ps = max(trfc4_ps, + (unsigned int)dimm_params[i].trfc4_ps); + trrds_ps = max(trrds_ps, + (unsigned int)dimm_params[i].trrds_ps); + trrdl_ps = max(trrdl_ps, + (unsigned int)dimm_params[i].trrdl_ps); + tccdl_ps = max(tccdl_ps, + (unsigned int)dimm_params[i].tccdl_ps); +#else + twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps); + twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps); + trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps); + trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps); + trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps); +#endif + trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps); +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps); + tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps); + tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps); + tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps); + tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps); + /* + * Find maximum tdqsq_max_ps to find slowest. + * + * FIXME: is finding the slowest value the correct + * strategy for this parameter? + */ + tdqsq_max_ps = max(tdqsq_max_ps, + (unsigned int)dimm_params[i].tdqsq_max_ps); +#endif + refresh_rate_ps = max(refresh_rate_ps, + (unsigned int)dimm_params[i].refresh_rate_ps); + /* extended_op_srt is either 0 or 1, 0 having priority */ + extended_op_srt = min(extended_op_srt, + (unsigned int)dimm_params[i].extended_op_srt); + } + + outpdimm->ndimms_present = number_of_dimms - temp1; + + if (temp1 == number_of_dimms) { + debug("no dimms this memory controller\n"); + return 0; + } + + outpdimm->tckmin_x_ps = tckmin_x_ps; + outpdimm->tckmax_ps = tckmax_ps; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + outpdimm->taamin_ps = taamin_ps; +#endif + outpdimm->trcd_ps = trcd_ps; + outpdimm->trp_ps = trp_ps; + outpdimm->tras_ps = tras_ps; +#ifdef CONFIG_SYS_FSL_DDR4 + outpdimm->trfc1_ps = trfc1_ps; + outpdimm->trfc2_ps = trfc2_ps; + outpdimm->trfc4_ps = trfc4_ps; + outpdimm->trrds_ps = trrds_ps; + outpdimm->trrdl_ps = trrdl_ps; + outpdimm->tccdl_ps = tccdl_ps; +#else + outpdimm->twtr_ps = twtr_ps; + outpdimm->trfc_ps = trfc_ps; + outpdimm->trrd_ps = trrd_ps; + outpdimm->trtp_ps = trtp_ps; +#endif + outpdimm->twr_ps = twr_ps; + outpdimm->trc_ps = trc_ps; + outpdimm->refresh_rate_ps = refresh_rate_ps; + outpdimm->extended_op_srt = extended_op_srt; +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + outpdimm->tis_ps = tis_ps; + outpdimm->tih_ps = tih_ps; + outpdimm->tds_ps = tds_ps; + outpdimm->tdh_ps = tdh_ps; + outpdimm->tdqsq_max_ps = tdqsq_max_ps; + outpdimm->tqhs_ps = tqhs_ps; +#endif + + /* Determine common burst length for all DIMMs. */ + temp1 = 0xff; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) { + temp1 &= dimm_params[i].burst_lengths_bitmask; + } + } + outpdimm->all_dimms_burst_lengths_bitmask = temp1; + + /* Determine if all DIMMs registered buffered. */ + temp1 = temp2 = 0; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) { + if (dimm_params[i].registered_dimm) { + temp1 = 1; +#ifndef CONFIG_SPL_BUILD + printf("Detected RDIMM %s\n", + dimm_params[i].mpart); +#endif + } else { + temp2 = 1; +#ifndef CONFIG_SPL_BUILD + printf("Detected UDIMM %s\n", + dimm_params[i].mpart); +#endif + } + } + } + + outpdimm->all_dimms_registered = 0; + outpdimm->all_dimms_unbuffered = 0; + if (temp1 && !temp2) { + outpdimm->all_dimms_registered = 1; + } else if (!temp1 && temp2) { + outpdimm->all_dimms_unbuffered = 1; + } else { + printf("ERROR: Mix of registered buffered and unbuffered " + "DIMMs detected!\n"); + } + + temp1 = 0; + if (outpdimm->all_dimms_registered) + for (j = 0; j < 16; j++) { + outpdimm->rcw[j] = dimm_params[0].rcw[j]; + for (i = 1; i < number_of_dimms; i++) { + if (!dimm_params[i].n_ranks) + continue; + if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { + temp1 = 1; + break; + } + } + } + + if (temp1 != 0) + printf("ERROR: Mix different RDIMM detected!\n"); + + /* calculate cas latency for all DDR types */ + if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms)) + return 1; + + /* Determine if all DIMMs ECC capable. */ + temp1 = 1; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks && + !(dimm_params[i].edc_config & EDC_ECC)) { + temp1 = 0; + break; + } + } + if (temp1) { + debug("all DIMMs ECC capable\n"); + } else { + debug("Warning: not all DIMMs ECC capable, cant enable ECC\n"); + } + outpdimm->all_dimms_ecc_capable = temp1; + + /* + * Compute additive latency. + * + * For DDR1, additive latency should be 0. + * + * For DDR2, with ODT enabled, use "a value" less than ACTTORW, + * which comes from Trcd, and also note that: + * add_lat + caslat must be >= 4 + * + * For DDR3, we use the AL=0 + * + * When to use additive latency for DDR2: + * + * I. Because you are using CL=3 and need to do ODT on writes and + * want functionality. + * 1. Are you going to use ODT? (Does your board not have + * additional termination circuitry for DQ, DQS, DQS_, + * DM, RDQS, RDQS_ for x4/x8 configs?) + * 2. If so, is your lowest supported CL going to be 3? + * 3. If so, then you must set AL=1 because + * + * WL >= 3 for ODT on writes + * RL = AL + CL + * WL = RL - 1 + * -> + * WL = AL + CL - 1 + * AL + CL - 1 >= 3 + * AL + CL >= 4 + * QED + * + * RL >= 3 for ODT on reads + * RL = AL + CL + * + * Since CL aren't usually less than 2, AL=0 is a minimum, + * so the WL-derived AL should be the -- FIXME? + * + * II. Because you are using auto-precharge globally and want to + * use additive latency (posted CAS) to get more bandwidth. + * 1. Are you going to use auto-precharge mode globally? + * + * Use addtivie latency and compute AL to be 1 cycle less than + * tRCD, i.e. the READ or WRITE command is in the cycle + * immediately following the ACTIVATE command.. + * + * III. Because you feel like it or want to do some sort of + * degraded-performance experiment. + * 1. Do you just want to use additive latency because you feel + * like it? + * + * Validation: AL is less than tRCD, and within the other + * read-to-precharge constraints. + */ + + additive_latency = 0; + +#if defined(CONFIG_SYS_FSL_DDR2) + if ((outpdimm->lowest_common_spd_caslat < 4) && + (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) { + additive_latency = picos_to_mclk(trcd_ps) - + outpdimm->lowest_common_spd_caslat; + if (mclk_to_picos(additive_latency) > trcd_ps) { + additive_latency = picos_to_mclk(trcd_ps); + debug("setting additive_latency to %u because it was " + " greater than tRCD_ps\n", additive_latency); + } + } +#endif + + /* + * Validate additive latency + * + * AL <= tRCD(min) + */ + if (mclk_to_picos(additive_latency) > trcd_ps) { + printf("Error: invalid additive latency exceeds tRCD(min).\n"); + return 1; + } + + /* + * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled + * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled + * ADD_LAT (the register) must be set to a value less + * than ACTTORW if WL = 1, then AL must be set to 1 + * RD_TO_PRE (the register) must be set to a minimum + * tRTP + AL if AL is nonzero + */ + + /* + * Additive latency will be applied only if the memctl option to + * use it. + */ + outpdimm->additive_latency = additive_latency; + + debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps); + debug("trcd_ps = %u\n", outpdimm->trcd_ps); + debug("trp_ps = %u\n", outpdimm->trp_ps); + debug("tras_ps = %u\n", outpdimm->tras_ps); +#ifdef CONFIG_SYS_FSL_DDR4 + debug("trfc1_ps = %u\n", trfc1_ps); + debug("trfc2_ps = %u\n", trfc2_ps); + debug("trfc4_ps = %u\n", trfc4_ps); + debug("trrds_ps = %u\n", trrds_ps); + debug("trrdl_ps = %u\n", trrdl_ps); + debug("tccdl_ps = %u\n", tccdl_ps); +#else + debug("twtr_ps = %u\n", outpdimm->twtr_ps); + debug("trfc_ps = %u\n", outpdimm->trfc_ps); + debug("trrd_ps = %u\n", outpdimm->trrd_ps); +#endif + debug("twr_ps = %u\n", outpdimm->twr_ps); + debug("trc_ps = %u\n", outpdimm->trc_ps); + + return 0; +} diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c new file mode 100644 index 0000000000..6f291ebc03 --- /dev/null +++ b/drivers/ddr/fsl/main.c @@ -0,0 +1,851 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +/* + * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Based on code from spd_sdram.c + * Author: James Yang [at freescale.com] + */ + +#include +#include +#include +#include + +/* + * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view + * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * all Power SoCs. But it could be different for ARM SoCs. For example, + * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of + * 0x00_8000_0000 ~ 0x00_ffff_ffff + * 0x80_8000_0000 ~ 0xff_ffff_ffff + */ +#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#endif + +#ifdef CONFIG_PPC +#include + +void fsl_ddr_set_lawbar( + const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); +#endif + +void fsl_ddr_set_intl3r(const unsigned int granule_size); +#if defined(SPD_EEPROM_ADDRESS) || \ + defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ + defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) +#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS, +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ + [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ + [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ + [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ +}; + +#endif + +#define SPD_SPA0_ADDRESS 0x36 +#define SPD_SPA1_ADDRESS 0x37 + +static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret; +#ifdef CONFIG_SYS_FSL_DDR4 + uint8_t dummy = 0; +#endif + + i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); + +#ifdef CONFIG_SYS_FSL_DDR4 + /* + * DDR4 SPD has 384 to 512 bytes + * To access the lower 256 bytes, we need to set EE page address to 0 + * To access the upper 256 bytes, we need to set EE page address to 1 + * See Jedec standar No. 21-C for detail + */ + i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1); + ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256); + if (!ret) { + i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1); + ret = i2c_read(i2c_address, 0, 1, + (uchar *)((ulong)spd + 256), + min(256, + (int)sizeof(generic_spd_eeprom_t) - 256)); + } +#else + ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); +#endif + + if (ret) { + if (i2c_address == +#ifdef SPD_EEPROM_ADDRESS + SPD_EEPROM_ADDRESS +#elif defined(SPD_EEPROM_ADDRESS1) + SPD_EEPROM_ADDRESS1 +#endif + ) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + } else { + debug("DDR: failed to read SPD from address %u\n", + i2c_address); + } + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +__attribute__((weak, alias("__get_spd"))) +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); + +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) +{ + unsigned int i; + unsigned int i2c_address = 0; + + if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < dimm_slots_per_ctrl; i++) { + i2c_address = spd_i2c_addr[ctrl_num][i]; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} +#else +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) +{ +} +#endif /* SPD_EEPROM_ADDRESSx */ + +/* + * ASSUMPTIONS: + * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller + * - Same memory data bus width on all controllers + * + * NOTES: + * + * The memory controller and associated documentation use confusing + * terminology when referring to the orgranization of DRAM. + * + * Here is a terminology translation table: + * + * memory controller/documention |industry |this code |signals + * -------------------------------|-----------|-----------|----------------- + * physical bank/bank |rank |rank |chip select (CS) + * logical bank/sub-bank |bank |bank |bank address (BA) + * page/row |row |page |row address + * ??? |column |column |column address + * + * The naming confusion is further exacerbated by the descriptions of the + * memory controller interleaving feature, where accesses are interleaved + * _BETWEEN_ two seperate memory controllers. This is configured only in + * CS0_CONFIG[INTLV_CTL] of each memory controller. + * + * memory controller documentation | number of chip selects + * | per memory controller supported + * --------------------------------|----------------------------------------- + * cache line interleaving | 1 (CS0 only) + * page interleaving | 1 (CS0 only) + * bank interleaving | 1 (CS0 only) + * superbank interleraving | depends on bank (chip select) + * | interleraving [rank interleaving] + * | mode used on every memory controller + * + * Even further confusing is the existence of the interleaving feature + * _WITHIN_ each memory controller. The feature is referred to in + * documentation as chip select interleaving or bank interleaving, + * although it is configured in the DDR_SDRAM_CFG field. + * + * Name of field | documentation name | this code + * -----------------------------|-----------------------|------------------ + * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving + * | interleaving + */ + +const char *step_string_tbl[] = { + "STEP_GET_SPD", + "STEP_COMPUTE_DIMM_PARMS", + "STEP_COMPUTE_COMMON_PARMS", + "STEP_GATHER_OPTS", + "STEP_ASSIGN_ADDRESSES", + "STEP_COMPUTE_REGS", + "STEP_PROGRAM_REGS", + "STEP_ALL" +}; + +const char * step_to_string(unsigned int step) { + + unsigned int s = __ilog2(step); + + if ((1 << s) != step) + return step_string_tbl[7]; + + if (s >= ARRAY_SIZE(step_string_tbl)) { + printf("Error for the step in %s\n", __func__); + s = 0; + } + + return step_string_tbl[s]; +} + +static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]) +{ + unsigned int i, j; + unsigned long long total_mem, current_mem_base, total_ctlr_mem; + unsigned long long rank_density, ctlr_density = 0; + unsigned int first_ctrl = pinfo->first_ctrl; + unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; + + /* + * If a reduced data width is requested, but the SPD + * specifies a physically wider device, adjust the + * computed dimm capacities accordingly before + * assigning addresses. + */ + for (i = first_ctrl; i <= last_ctrl; i++) { + unsigned int found = 0; + + switch (pinfo->memctl_opts[i].data_bus_width) { + case 2: + /* 16-bit */ + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned int dw; + if (!pinfo->dimm_params[i][j].n_ranks) + continue; + dw = pinfo->dimm_params[i][j].primary_sdram_width; + if ((dw == 72 || dw == 64)) { + dbw_cap_adj[i] = 2; + break; + } else if ((dw == 40 || dw == 32)) { + dbw_cap_adj[i] = 1; + break; + } + } + break; + + case 1: + /* 32-bit */ + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned int dw; + dw = pinfo->dimm_params[i][j].data_width; + if (pinfo->dimm_params[i][j].n_ranks + && (dw == 72 || dw == 64)) { + /* + * FIXME: can't really do it + * like this because this just + * further reduces the memory + */ + found = 1; + break; + } + } + if (found) { + dbw_cap_adj[i] = 1; + } + break; + + case 0: + /* 64-bit */ + break; + + default: + printf("unexpected data bus width " + "specified controller %u\n", i); + return 1; + } + debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); + } + + current_mem_base = pinfo->mem_base; + total_mem = 0; + if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) { + rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >> + dbw_cap_adj[first_ctrl]; + switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl & + FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + ctlr_density = 4 * rank_density; + break; + case FSL_DDR_CS0_CS1: + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + ctlr_density = 2 * rank_density; + break; + case FSL_DDR_CS2_CS3: + default: + ctlr_density = rank_density; + break; + } + debug("rank density is 0x%llx, ctlr density is 0x%llx\n", + rank_density, ctlr_density); + for (i = first_ctrl; i <= last_ctrl; i++) { + if (pinfo->memctl_opts[i].memctl_interleaving) { + switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_256B_INTERLEAVING: + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + total_ctlr_mem = 2 * ctlr_density; + break; + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + total_ctlr_mem = 3 * ctlr_density; + break; + case FSL_DDR_4WAY_1KB_INTERLEAVING: + case FSL_DDR_4WAY_4KB_INTERLEAVING: + case FSL_DDR_4WAY_8KB_INTERLEAVING: + total_ctlr_mem = 4 * ctlr_density; + break; + default: + panic("Unknown interleaving mode"); + } + pinfo->common_timing_params[i].base_address = + current_mem_base; + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem = current_mem_base + total_ctlr_mem; + debug("ctrl %d base 0x%llx\n", i, current_mem_base); + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + } else { + /* when 3rd controller not interleaved */ + current_mem_base = total_mem; + total_ctlr_mem = 0; + pinfo->common_timing_params[i].base_address = + current_mem_base; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned long long cap = + pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; + pinfo->dimm_params[i][j].base_address = + current_mem_base; + debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); + current_mem_base += cap; + total_ctlr_mem += cap; + } + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem += total_ctlr_mem; + } + } + } else { + /* + * Simple linear assignment if memory + * controllers are not interleaved. + */ + for (i = first_ctrl; i <= last_ctrl; i++) { + total_ctlr_mem = 0; + pinfo->common_timing_params[i].base_address = + current_mem_base; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + /* Compute DIMM base addresses. */ + unsigned long long cap = + pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; + pinfo->dimm_params[i][j].base_address = + current_mem_base; + debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); + current_mem_base += cap; + total_ctlr_mem += cap; + } + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem += total_ctlr_mem; + } + } + debug("Total mem by %s is 0x%llx\n", __func__, total_mem); + + return total_mem; +} + +/* Use weak function to allow board file to override the address assignment */ +__attribute__((weak, alias("__step_assign_addresses"))) +unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]); + +unsigned long long +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only) +{ + unsigned int i, j; + unsigned long long total_mem = 0; + int assert_reset = 0; + unsigned int first_ctrl = pinfo->first_ctrl; + unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; + __maybe_unused int retval; + __maybe_unused bool goodspd = false; + __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl; + + fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; + common_timing_params_t *timing_params = pinfo->common_timing_params; + if (pinfo->board_need_mem_reset) + assert_reset = pinfo->board_need_mem_reset(); + + /* data bus width capacity adjust shift amount */ + unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; + + for (i = first_ctrl; i <= last_ctrl; i++) + dbw_capacity_adjust[i] = 0; + + debug("starting at step %u (%s)\n", + start_step, step_to_string(start_step)); + + switch (start_step) { + case STEP_GET_SPD: +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) + /* STEP 1: Gather all DIMM SPD data */ + for (i = first_ctrl; i <= last_ctrl; i++) { + fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i, + dimm_slots_per_ctrl); + } + + case STEP_COMPUTE_DIMM_PARMS: + /* STEP 2: Compute DIMM parameters from SPD data */ + + for (i = first_ctrl; i <= last_ctrl; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + generic_spd_eeprom_t *spd = + &(pinfo->spd_installed_dimms[i][j]); + dimm_params_t *pdimm = + &(pinfo->dimm_params[i][j]); + retval = compute_dimm_parameters(spd, pdimm, i); +#ifdef CONFIG_SYS_DDR_RAW_TIMING + if (!i && !j && retval) { + printf("SPD error on controller %d! " + "Trying fallback to raw timing " + "calculation\n", i); + retval = fsl_ddr_get_dimm_params(pdimm, + i, j); + } +#else + if (retval == 2) { + printf("Error: compute_dimm_parameters" + " non-zero returned FATAL value " + "for memctl=%u dimm=%u\n", i, j); + return 0; + } +#endif + if (retval) { + debug("Warning: compute_dimm_parameters" + " non-zero return value for memctl=%u " + "dimm=%u\n", i, j); + } else { + goodspd = true; + } + } + } + if (!goodspd) { + /* + * No valid SPD found + * Throw an error if this is for main memory, i.e. + * first_ctrl == 0. Otherwise, siliently return 0 + * as the memory size. + */ + if (first_ctrl == 0) + printf("Error: No valid SPD detected.\n"); + + return 0; + } +#elif defined(CONFIG_SYS_DDR_RAW_TIMING) + case STEP_COMPUTE_DIMM_PARMS: + for (i = first_ctrl; i <= last_ctrl; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + dimm_params_t *pdimm = + &(pinfo->dimm_params[i][j]); + fsl_ddr_get_dimm_params(pdimm, i, j); + } + } + debug("Filling dimm parameters from board specific file\n"); +#endif + case STEP_COMPUTE_COMMON_PARMS: + /* + * STEP 3: Compute a common set of timing parameters + * suitable for all of the DIMMs on each memory controller + */ + for (i = first_ctrl; i <= last_ctrl; i++) { + debug("Computing lowest common DIMM" + " parameters for memctl=%u\n", i); + compute_lowest_common_dimm_parameters( + pinfo->dimm_params[i], + &timing_params[i], + CONFIG_DIMM_SLOTS_PER_CTLR); + } + + case STEP_GATHER_OPTS: + /* STEP 4: Gather configuration requirements from user */ + for (i = first_ctrl; i <= last_ctrl; i++) { + debug("Reloading memory controller " + "configuration options for memctl=%u\n", i); + /* + * This "reloads" the memory controller options + * to defaults. If the user "edits" an option, + * next_step points to the step after this, + * which is currently STEP_ASSIGN_ADDRESSES. + */ + populate_memctl_options( + timing_params[i].all_dimms_registered, + &pinfo->memctl_opts[i], + pinfo->dimm_params[i], i); + /* + * For RDIMMs, JEDEC spec requires clocks to be stable + * before reset signal is deasserted. For the boards + * using fixed parameters, this function should be + * be called from board init file. + */ + if (timing_params[i].all_dimms_registered) + assert_reset = 1; + } + if (assert_reset && !size_only) { + if (pinfo->board_mem_reset) { + debug("Asserting mem reset\n"); + pinfo->board_mem_reset(); + } else { + debug("Asserting mem reset missing\n"); + } + } + + case STEP_ASSIGN_ADDRESSES: + /* STEP 5: Assign addresses to chip selects */ + check_interleaving_options(pinfo); + total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); + debug("Total mem %llu assigned\n", total_mem); + + case STEP_COMPUTE_REGS: + /* STEP 6: compute controller register values */ + debug("FSL Memory ctrl register computation\n"); + for (i = first_ctrl; i <= last_ctrl; i++) { + if (timing_params[i].ndimms_present == 0) { + memset(&ddr_reg[i], 0, + sizeof(fsl_ddr_cfg_regs_t)); + continue; + } + + compute_fsl_memctl_config_regs( + &pinfo->memctl_opts[i], + &ddr_reg[i], &timing_params[i], + pinfo->dimm_params[i], + dbw_capacity_adjust[i], + size_only); + } + + default: + break; + } + + { + /* + * Compute the amount of memory available just by + * looking for the highest valid CSn_BNDS value. + * This allows us to also experiment with using + * only CS0 when using dual-rank DIMMs. + */ + unsigned int max_end = 0; + + for (i = first_ctrl; i <= last_ctrl; i++) { + for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { + fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; + if (reg->cs[j].config & 0x80000000) { + unsigned int end; + /* + * 0xfffffff is a special value we put + * for unused bnds + */ + if (reg->cs[j].bnds == 0xffffffff) + continue; + end = reg->cs[j].bnds & 0xffff; + if (end > max_end) { + max_end = end; + } + } + } + } + + total_mem = 1 + (((unsigned long long)max_end << 24ULL) | + 0xFFFFFFULL) - pinfo->mem_base; + } + + return total_mem; +} + +phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) +{ + unsigned int i, first_ctrl, last_ctrl; +#ifdef CONFIG_PPC + unsigned int law_memctl = LAW_TRGT_IF_DDR_1; +#endif + unsigned long long total_memory; + int deassert_reset = 0; + + first_ctrl = pinfo->first_ctrl; + last_ctrl = first_ctrl + pinfo->num_ctrls - 1; + + /* Compute it once normally. */ +#ifdef CONFIG_FSL_DDR_INTERACTIVE + if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ + total_memory = fsl_ddr_interactive(pinfo, 0); + } else if (fsl_ddr_interactive_env_var_exists()) { + total_memory = fsl_ddr_interactive(pinfo, 1); + } else +#endif + total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0); + + /* setup 3-way interleaving before enabling DDRC */ + switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) { + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + fsl_ddr_set_intl3r( + pinfo->memctl_opts[first_ctrl]. + memctl_interleaving_mode); + break; + default: + break; + } + + /* + * Program configuration registers. + * JEDEC specs requires clocks to be stable before deasserting reset + * for RDIMMs. Clocks start after chip select is enabled and clock + * control register is set. During step 1, all controllers have their + * registers set but not enabled. Step 2 proceeds after deasserting + * reset through board FPGA or GPIO. + * For non-registered DIMMs, initialization can go through but it is + * also OK to follow the same flow. + */ + if (pinfo->board_need_mem_reset) + deassert_reset = pinfo->board_need_mem_reset(); + for (i = first_ctrl; i <= last_ctrl; i++) { + if (pinfo->common_timing_params[i].all_dimms_registered) + deassert_reset = 1; + } + for (i = first_ctrl; i <= last_ctrl; i++) { + debug("Programming controller %u\n", i); + if (pinfo->common_timing_params[i].ndimms_present == 0) { + debug("No dimms present on controller %u; " + "skipping programming\n", i); + continue; + } + /* + * The following call with step = 1 returns before enabling + * the controller. It has to finish with step = 2 later. + */ + fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i, + deassert_reset ? 1 : 0); + } + if (deassert_reset) { + /* Use board FPGA or GPIO to deassert reset signal */ + if (pinfo->board_mem_de_reset) { + debug("Deasserting mem reset\n"); + pinfo->board_mem_de_reset(); + } else { + debug("Deasserting mem reset missing\n"); + } + for (i = first_ctrl; i <= last_ctrl; i++) { + /* Call with step = 2 to continue initialization */ + fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), + i, 2); + } + } + +#ifdef CONFIG_PPC + /* program LAWs */ + for (i = first_ctrl; i <= last_ctrl; i++) { + if (pinfo->memctl_opts[i].memctl_interleaving) { + switch (pinfo->memctl_opts[i]. + memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + if (i % 2) + break; + if (i == 0) { + law_memctl = LAW_TRGT_IF_DDR_INTRLV; + fsl_ddr_set_lawbar( + &pinfo->common_timing_params[i], + law_memctl, i); + } +#if CONFIG_NUM_DDR_CONTROLLERS > 3 + else if (i == 2) { + law_memctl = LAW_TRGT_IF_DDR_INTLV_34; + fsl_ddr_set_lawbar( + &pinfo->common_timing_params[i], + law_memctl, i); + } +#endif + break; + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + law_memctl = LAW_TRGT_IF_DDR_INTLV_123; + if (i == 0) { + fsl_ddr_set_lawbar( + &pinfo->common_timing_params[i], + law_memctl, i); + } + break; + case FSL_DDR_4WAY_1KB_INTERLEAVING: + case FSL_DDR_4WAY_4KB_INTERLEAVING: + case FSL_DDR_4WAY_8KB_INTERLEAVING: + law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; + if (i == 0) + fsl_ddr_set_lawbar( + &pinfo->common_timing_params[i], + law_memctl, i); + /* place holder for future 4-way interleaving */ + break; + default: + break; + } + } else { + switch (i) { + case 0: + law_memctl = LAW_TRGT_IF_DDR_1; + break; + case 1: + law_memctl = LAW_TRGT_IF_DDR_2; + break; + case 2: + law_memctl = LAW_TRGT_IF_DDR_3; + break; + case 3: + law_memctl = LAW_TRGT_IF_DDR_4; + break; + default: + break; + } + fsl_ddr_set_lawbar(&pinfo->common_timing_params[i], + law_memctl, i); + } + } +#endif + + debug("total_memory by %s = %llu\n", __func__, total_memory); + +#if !defined(CONFIG_PHYS_64BIT) + /* Check for 4G or more. Bad. */ + if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) { + puts("Detected "); + print_size(total_memory, " of memory\n"); + printf(" This U-Boot only supports < 4G of DDR\n"); + printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); + printf(" "); /* re-align to match init_func_ram print */ + total_memory = CONFIG_MAX_MEM_MAPPED; + } +#endif + + return total_memory; +} + +/* + * fsl_ddr_sdram(void) -- this is the main function to be + * called by initdram() in the board file. + * + * It returns amount of memory configured in bytes. + */ +phys_size_t fsl_ddr_sdram(void) +{ + fsl_ddr_info_t info; + + /* Reset info structure. */ + memset(&info, 0, sizeof(fsl_ddr_info_t)); + info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; + info.first_ctrl = 0; + info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; + info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; + info.board_need_mem_reset = board_need_mem_reset; + info.board_mem_reset = board_assert_mem_reset; + info.board_mem_de_reset = board_deassert_mem_reset; + + return __fsl_ddr_sdram(&info); +} + +#ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS +phys_size_t fsl_other_ddr_sdram(unsigned long long base, + unsigned int first_ctrl, + unsigned int num_ctrls, + unsigned int dimm_slots_per_ctrl, + int (*board_need_reset)(void), + void (*board_reset)(void), + void (*board_de_reset)(void)) +{ + fsl_ddr_info_t info; + + /* Reset info structure. */ + memset(&info, 0, sizeof(fsl_ddr_info_t)); + info.mem_base = base; + info.first_ctrl = first_ctrl; + info.num_ctrls = num_ctrls; + info.dimm_slots_per_ctrl = dimm_slots_per_ctrl; + info.board_need_mem_reset = board_need_reset; + info.board_mem_reset = board_reset; + info.board_mem_de_reset = board_de_reset; + + return __fsl_ddr_sdram(&info); +} +#endif + +/* + * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the + * size of the total memory without setting ddr control registers. + */ +phys_size_t +fsl_ddr_sdram_size(void) +{ + fsl_ddr_info_t info; + unsigned long long total_memory = 0; + + memset(&info, 0 , sizeof(fsl_ddr_info_t)); + info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; + info.first_ctrl = 0; + info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; + info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; + info.board_need_mem_reset = NULL; + + /* Compute it once normally. */ + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); + + return total_memory; +} diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c new file mode 100644 index 0000000000..8dd4a9136c --- /dev/null +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -0,0 +1,91 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + + if (ctrl_num != 0) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + } + } + + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541) + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); +#endif + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + asm volatile("sync;isync"); + + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + + asm("sync;isync;msync"); + udelay(500); +} + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +/* + * Initialize all of memory for ECC, then enable errors. + */ + +void +ddr_enable_ecc(unsigned int dram_size) +{ + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + + dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); + + /* + * Enable errors for ECC. + */ + debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); + ddr->err_disable = 0x00000000; + asm("sync;isync;msync"); + debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); +} + +#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c new file mode 100644 index 0000000000..988b4a4941 --- /dev/null +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -0,0 +1,96 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + +#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint svr; +#endif + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + /* + * Set the DDR IO receiver to an acceptable bias point. + * Fixed in Rev 2.1. + */ + svr = get_svr(); + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) { + if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == + SDRAM_CFG_SDRAM_TYPE_DDR2) + out_be32(&gur->ddrioovcr, 0x90000000); + else + out_be32(&gur->ddrioovcr, 0xA8000000); + } +#endif + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + } + } + + out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); + out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + out_be32(&ddr->sdram_data_init, regs->ddr_data_init); + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + asm volatile("sync;isync"); + + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ + while (in_be32(&ddr->sdram_cfg_2) & 0x10) { + udelay(10000); /* throttle polling rate */ + } +} diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c new file mode 100644 index 0000000000..8f4d01ad85 --- /dev/null +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -0,0 +1,556 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +/* + * regs has the to-be-set values for DDR controller registers + * ctrl_num is the DDR controller number + * step: 0 goes through the initialization in one pass + * 1 sets registers and returns before enabling controller + * 2 resumes from step 1 and continues to initialize + * Dividing the initialization to two steps to deassert DDR reset signal + * to comply with JEDEC specs for RDIMMs. + */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i, bus_width; + struct ccsr_ddr __iomem *ddr; + u32 temp_sdram_cfg; + u32 total_gb_size_per_controller; + int timeout; +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + int timeout_save; + volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; + unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; + int csn = -1; +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + u32 save1, save2; +#endif + + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + if (step == 2) + goto step2; + + if (regs->ddr_eor) + out_be32(&ddr->eor, regs->ddr_eor); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + debug("Workaround for ERRATUM_DDR111_DDR134\n"); + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; + cs_ea = regs->cs[i].bnds & 0xfff; + if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { + csn = i; + csn_bnds_backup = regs->cs[i].bnds; + csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; + if (cs_ea > 0xeff) + *csn_bnds_t = regs->cs[i].bnds + 0x01000000; + else + *csn_bnds_t = regs->cs[i].bnds + 0x01000100; + debug("Found cs%d_bns (0x%08x) covering 0xff000000, " + "change it to 0x%x\n", + csn, csn_bnds_backup, regs->cs[i].bnds); + break; + } + } +#endif + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); + } + } + + out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); + out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + out_be32(&ddr->sdram_data_init, regs->ddr_data_init); + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); + out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); +#ifndef CONFIG_SYS_FSL_DDR_EMU + /* + * Skip these two registers if running on emulator + * because emulator doesn't have skew between bytes. + */ + + if (regs->ddr_wrlvl_cntl_2) + out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + if (regs->ddr_wrlvl_cntl_3) + out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); +#endif + + out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + out_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + out_be32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } + out_be32(&ddr->err_disable, regs->err_disable); + out_be32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) { + if (regs->debug[i]) { + debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); + out_be32(&ddr->debug[i], regs->debug[i]); + } + } +#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 + out_be32(&ddr->debug[28], 0x30003000); +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ + + /* + * For RDIMMs, JEDEC spec requires clocks to be stable before reset is + * deasserted. Clocks start when any chip select is enabled and clock + * control register is set. Because all DDR components are connected to + * one reset signal, this needs to be done in two steps. Step 1 is to + * get the clocks started. Step 2 resumes after reset signal is + * deasserted. + */ + if (step == 1) { + udelay(200); + return; + } + +step2: + /* Set, but do not enable the memory */ + temp_sdram_cfg = regs->ddr_sdram_cfg; + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + debug("Workaround for ERRATUM_DDR_A003\n"); + if (regs->ddr_sdram_rcw_2 & 0x00f00000) { + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); + out_be32(&ddr->debug[2], 0x00000400); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); + out_be32(&ddr->mtcr, 0); + save1 = in_be32(&ddr->debug[12]); + save2 = in_be32(&ddr->debug[21]); + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); + + asm volatile("sync;isync"); + while (!(in_be32(&ddr->debug[1]) & 0x2)) + ; + + switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { + case 0x00000000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); +#endif + break; + case 0x00100000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x0a)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x0a)); +#endif + break; + case 0x00200000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x12)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x12)); +#endif + break; + case 0x00300000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x1a)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x1a)); +#endif + break; + default: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); +#endif + printf("Unsupported RC10\n"); + break; + } + + while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) + ; + udelay(6); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->debug[2], 0x0); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->debug[12], save1); + out_be32(&ddr->debug[21], save2); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + + } +#endif + /* + * For 8572 DDR1 erratum - DDR controller may enter illegal state + * when operatiing in 32-bit bus mode with 4-beat bursts, + * This erratum does not affect DDR3 mode, only for DDR2 mode. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 + debug("Workaround for ERRATUM_DDR_115\n"); + if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) + && in_be32(&ddr->sdram_cfg) & 0x80000) { + /* set DEBUG_1[31] */ + setbits_be32(&ddr->debug[0], 1); + } +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + debug("Workaround for ERRATUM_DDR111_DDR134\n"); + /* + * This is the combined workaround for DDR111 and DDR134 + * following the published errata for MPC8572 + */ + + /* 1. Set EEBACR[3] */ + setbits_be32(&ecm->eebacr, 0x10000000); + debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); + + /* 2. Set DINIT in SDRAM_CFG_2*/ + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); + debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", + in_be32(&ddr->sdram_cfg_2)); + + /* 3. Set DEBUG_3[21] */ + setbits_be32(&ddr->debug[2], 0x400); + debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); + +#endif /* part 1 of the workaound */ + + /* + * 500 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. + */ + udelay(500); + asm volatile("sync;isync"); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); + /* do board specific memory setup */ + board_mem_sleep_setup(); + temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + asm volatile("sync;isync"); + + total_gb_size_per_controller = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (!(regs->cs[i].config & 0x80000000)) + continue; + total_gb_size_per_controller += 1 << ( + ((regs->cs[i].config >> 14) & 0x3) + 2 + + ((regs->cs[i].config >> 8) & 0x7) + 12 + + ((regs->cs[i].config >> 0) & 0x7) + 8 + + 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - + 26); /* minus 26 (count of 64M) */ + } + if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ + total_gb_size_per_controller *= 3; + else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ + total_gb_size_per_controller <<= 1; + /* + * total memory / bus width = transactions needed + * transactions needed / data rate = seconds + * to add plenty of buffer, double the time + * For example, 2GB on 666MT/s 64-bit bus takes about 402ms + * Let's wait for 800ms + */ + bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) + >> SDRAM_CFG_DBW_SHIFT); + timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / + (get_ddr_freq(0) >> 20)) << 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + timeout_save = timeout; +#endif + total_gb_size_per_controller >>= 4; /* shift down to gb size */ + debug("total %d GB\n", total_gb_size_per_controller); + debug("Need to wait up to %d * 10ms\n", timeout); + + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ + while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); + +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + /* continue this workaround */ + + /* 4. Clear DEBUG3[21] */ + clrbits_be32(&ddr->debug[2], 0x400); + debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); + + /* DDR134 workaround starts */ + /* A: Clear sdram_cfg_2[odt_cfg] */ + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); + debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", + in_be32(&ddr->sdram_cfg_2)); + + /* B: Set DEBUG1[15] */ + setbits_be32(&ddr->debug[0], 0x10000); + debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); + + /* C: Set timing_cfg_2[cpo] to 0b11111 */ + setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); + debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", + in_be32(&ddr->timing_cfg_2)); + + /* D: Set D6 to 0x9f9f9f9f */ + out_be32(&ddr->debug[5], 0x9f9f9f9f); + debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); + + /* E: Set D7 to 0x9f9f9f9f */ + out_be32(&ddr->debug[6], 0x9f9f9f9f); + debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); + + /* F: Set D2[20] */ + setbits_be32(&ddr->debug[1], 0x800); + debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); + + /* G: Poll on D2[20] until cleared */ + while (in_be32(&ddr->debug[1]) & 0x800) + udelay(10000); /* throttle polling rate */ + + /* H: Clear D1[15] */ + clrbits_be32(&ddr->debug[0], 0x10000); + debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); + + /* I: Set sdram_cfg_2[odt_cfg] */ + setbits_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); + debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); + + /* Continuing with the DDR111 workaround */ + /* 5. Set D2[21] */ + setbits_be32(&ddr->debug[1], 0x400); + debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); + + /* 6. Poll D2[21] until its cleared */ + while (in_be32(&ddr->debug[1]) & 0x400) + udelay(10000); /* throttle polling rate */ + + /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ + debug("Wait for %d * 10ms\n", timeout_save); + udelay(timeout_save * 10000); + + /* 8. Set sdram_cfg_2[dinit] if options requires */ + setbits_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); + debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); + + /* 9. Poll until dinit is cleared */ + timeout = timeout_save; + debug("Need to wait up to %d * 10ms\n", timeout); + while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); + + /* 10. Clear EEBACR[3] */ + clrbits_be32(&ecm->eebacr, 10000000); + debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); + + if (csn != -1) { + csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds; + *csn_bnds_t = csn_bnds_backup; + debug("Change cs%d_bnds back to 0x%08x\n", + csn, regs->cs[csn].bnds); + setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ + switch (csn) { + case 0: + out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); + break; + case 1: + out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); + break; + case 2: + out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); + break; + case 3: + out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); + break; + } + clrbits_be32(&ddr->sdram_cfg, 0x2); + } +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) + /* exit self-refresh */ + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); +#endif +} diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c new file mode 100644 index 0000000000..4551ed87db --- /dev/null +++ b/drivers/ddr/fsl/mpc86xx_ddr.c @@ -0,0 +1,85 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i; + struct ccsr_ddr __iomem *ddr; + + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; + default: + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + } + } + + out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); + out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + out_be32(&ddr->sdram_data_init, regs->ddr_data_init); + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + + debug("before go\n"); + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + asm volatile("sync;isync"); + + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + + /* + * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done + */ + while (in_be32(&ddr->sdram_cfg_2) & 0x10) { + udelay(10000); /* throttle polling rate */ + } +} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/drivers/ddr/fsl/options.c similarity index 85% rename from arch/powerpc/cpu/mpc8xxx/ddr/options.c rename to drivers/ddr/fsl/options.c index 26369e0996..6d098d1fa2 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/drivers/ddr/fsl/options.c @@ -1,14 +1,14 @@ /* - * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include #include -#include +#include -#include "ddr.h" +#include /* * Use our own stack based buffer before relocation to allow accessing longer @@ -29,7 +29,7 @@ struct dynamic_odt { unsigned int odt_rtt_wr; }; -#ifdef CONFIG_FSL_DDR3 +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) static const struct dynamic_odt single_Q[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, @@ -259,7 +259,7 @@ static const struct dynamic_odt odt_unknown[4] = { DDR3_RTT_OFF } }; -#else /* CONFIG_FSL_DDR3 */ +#else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */ static const struct dynamic_odt single_Q[4] = { {0, 0, 0, 0}, {0, 0, 0, 0}, @@ -499,7 +499,7 @@ static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm) return 0; } -unsigned int populate_memctl_options(int all_DIMMs_registered, +unsigned int populate_memctl_options(int all_dimms_registered, memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) @@ -507,7 +507,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int i; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) +#if defined(CONFIG_SYS_FSL_DDR3) || \ + defined(CONFIG_SYS_FSL_DDR2) || \ + defined(CONFIG_SYS_FSL_DDR4) const struct dynamic_odt *pdodt = odt_unknown; #endif ulong ddr_freq; @@ -519,73 +521,76 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) +#if defined(CONFIG_SYS_FSL_DDR3) || \ + defined(CONFIG_SYS_FSL_DDR2) || \ + defined(CONFIG_SYS_FSL_DDR4) /* Chip select options. */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - switch (pdimm[0].n_ranks) { - case 1: - pdodt = single_S; - break; +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + switch (pdimm[0].n_ranks) { + case 1: + pdodt = single_S; + break; + case 2: + pdodt = single_D; + break; + case 4: + pdodt = single_Q; + break; + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + switch (pdimm[0].n_ranks) { +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + case 4: + pdodt = single_Q; + if (pdimm[1].n_ranks) + printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n"); + break; +#endif + case 2: + switch (pdimm[1].n_ranks) { case 2: - pdodt = single_D; + pdodt = dual_DD; break; - case 4: - pdodt = single_Q; + case 1: + pdodt = dual_DS; break; - } - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - switch (pdimm[0].n_ranks) { -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - case 4: - pdodt = single_Q; - if (pdimm[1].n_ranks) - printf("Error: Quad- and Dual-rank DIMMs " - "cannot be used together\n"); + case 0: + pdodt = dual_D0; break; -#endif + } + break; + case 1: + switch (pdimm[1].n_ranks) { case 2: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_DD; - break; - case 1: - pdodt = dual_DS; - break; - case 0: - pdodt = dual_D0; - break; - } + pdodt = dual_SD; break; case 1: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_SD; - break; - case 1: - pdodt = dual_SS; - break; - case 0: - pdodt = dual_S0; - break; - } + pdodt = dual_SS; break; case 0: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_0D; - break; - case 1: - pdodt = dual_0S; - break; - } + pdodt = dual_S0; break; } + break; + case 0: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_0D; + break; + case 1: + pdodt = dual_0S; + break; + } + break; } -#endif +#endif /* CONFIG_DIMM_SLOTS_PER_CTLR */ +#endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */ /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) +#if defined(CONFIG_SYS_FSL_DDR3) || \ + defined(CONFIG_SYS_FSL_DDR2) || \ + defined(CONFIG_SYS_FSL_DDR4) popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; @@ -635,30 +640,30 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->ba_intlv_ctl = 0; /* Memory Organization Parameters */ - popts->registered_dimm_en = all_DIMMs_registered; + popts->registered_dimm_en = all_dimms_registered; /* Operational Mode Paramters */ /* Pick ECC modes */ - popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */ + popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */ #ifdef CONFIG_DDR_ECC if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) - popts->ECC_mode = 1; + popts->ecc_mode = 1; } else - popts->ECC_mode = 1; + popts->ecc_mode = 1; #endif - popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ + popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ /* * Choose DQS config * 0 for DDR1 * 1 for DDR2 */ -#if defined(CONFIG_FSL_DDR1) - popts->DQS_config = 0; -#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) - popts->DQS_config = 1; +#if defined(CONFIG_SYS_FSL_DDR1) + popts->dqs_config = 0; +#elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) + popts->dqs_config = 1; #endif /* Choose self-refresh during sleep. */ @@ -672,7 +677,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * presuming all dimms are similar * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ -#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2) +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) if (pdimm[0].n_ranks != 0) { if ((pdimm[0].data_width >= 64) && \ (pdimm[0].data_width <= 72)) @@ -700,18 +705,20 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } #endif + popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; + /* Choose burst length. */ -#if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) #if defined(CONFIG_E500MC) - popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ + popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ #else if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { /* 32-bit or 16-bit bus */ - popts->OTF_burst_chop_en = 0; + popts->otf_burst_chop_en = 0; popts->burst_length = DDR_BL8; } else { - popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ + popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */ popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ } #endif @@ -720,7 +727,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, #endif /* Choose ddr controller address mirror mode */ -#if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) popts->mirrored_dimm = pdimm[0].mirrored_dimm; #endif @@ -754,8 +761,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * - number of components, number of active ranks * - how much time you want to spend playing around */ - popts->twoT_en = 0; - popts->threeT_en = 0; + popts->twot_en = 0; + popts->threet_en = 0; /* for RDIMM, address parity enable */ popts->ap_en = 1; @@ -764,18 +771,12 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * BSTTOPRE precharge interval * * Set this to 0 for global auto precharge - * - * FIXME: Should this be configured in picoseconds? - * Why it should be in ps: better understanding of this - * relative to actual DRAM timing parameters such as tRAS. - * e.g. tRAS(min) = 40 ns + * The value of 0x100 has been used for DDR1, DDR2, DDR3. + * It is not wrong. Any value should be OK. The performance depends on + * applications. There is no one good value for all. */ popts->bstopre = 0x100; - /* Minimum CKE pulse width -- tCKE(MIN) */ - popts->tCKE_clock_pulse_width_ps - = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR); - /* * Window for four activates -- tFAW * @@ -783,22 +784,22 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * FIXME: varies depending upon number of column addresses or data * FIXME: width, was considering looking at pdimm->primary_sdram_width */ -#if defined(CONFIG_FSL_DDR1) - popts->tFAW_window_four_activates_ps = mclk_to_picos(1); +#if defined(CONFIG_SYS_FSL_DDR1) + popts->tfaw_window_four_activates_ps = mclk_to_picos(1); -#elif defined(CONFIG_FSL_DDR2) +#elif defined(CONFIG_SYS_FSL_DDR2) /* * x4/x8; some datasheets have 35000 * x16 wide columns only? Use 50000? */ - popts->tFAW_window_four_activates_ps = 37500; + popts->tfaw_window_four_activates_ps = 37500; -#elif defined(CONFIG_FSL_DDR3) - popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps; +#else + popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; #endif popts->zq_en = 0; popts->wrlvl_en = 0; -#if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) /* * due to ddr3 dimm is fly-by topology * we suggest to enable write leveling to @@ -816,21 +817,32 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * If memory controller interleaving is enabled, then the data * bus widths must be programmed identically for all memory controllers. * - * XXX: Attempt to set all controllers to the same chip select + * Attempt to set all controllers to the same chip select * interleaving mode. It will do a best effort to get the * requested ranks interleaved together such that the result * should be a subset of the requested configuration. + * + * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving + * with 256 Byte is enabled. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) +#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B + ; +#else goto done; - +#endif if (pdimm[0].n_ranks == 0) { printf("There is no rank on CS0 for controller %d.\n", ctrl_num); popts->memctl_interleaving = 0; goto done; } popts->memctl_interleaving = 1; +#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B + popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; + popts->memctl_interleaving = 1; + debug("256 Byte interleaving\n"); +#else /* * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero @@ -912,8 +924,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->memctl_interleaving = 0; printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); } +#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */ done: -#endif +#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { /* test null first. if CONFIG_HWCONFIG is not defined, @@ -1048,18 +1061,21 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) unsigned int check_intlv, check_n_row_addr, check_n_col_addr; unsigned long long check_rank_density; struct dimm_params_s *dimm; + int first_ctrl = pinfo->first_ctrl; + int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; + /* * Check if all controllers are configured for memory * controller interleaving. Identical dimms are recommended. At least * the size, row and col address should be checked. */ j = 0; - check_n_ranks = pinfo->dimm_params[0][0].n_ranks; - check_rank_density = pinfo->dimm_params[0][0].rank_density; - check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr; - check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr; - check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks; + check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density; + check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr; + check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr; + check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode; + for (i = first_ctrl; i <= last_ctrl; i++) { dimm = &pinfo->dimm_params[i][0]; if (!pinfo->memctl_opts[i].memctl_interleaving) { continue; @@ -1077,20 +1093,22 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) } if (intlv_invalid) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + for (i = first_ctrl; i <= last_ctrl; i++) pinfo->memctl_opts[i].memctl_interleaving = 0; printf("Not all DIMMs are identical. " "Memory controller interleaving disabled.\n"); } else { switch (check_intlv) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: case FSL_DDR_SUPERBANK_INTERLEAVING: - if (3 == CONFIG_NUM_DDR_CONTROLLERS) +#if (3 == CONFIG_NUM_DDR_CONTROLLERS) k = 2; - else +#else k = CONFIG_NUM_DDR_CONTROLLERS; +#endif break; case FSL_DDR_3WAY_1KB_INTERLEAVING: case FSL_DDR_3WAY_4KB_INTERLEAVING: @@ -1104,10 +1122,10 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) } debug("%d of %d controllers are interleaving.\n", j, k); if (j && (j != k)) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + for (i = first_ctrl; i <= last_ctrl; i++) pinfo->memctl_opts[i].memctl_interleaving = 0; - printf("Not all controllers have compatible " - "interleaving mode. All disabled.\n"); + if ((last_ctrl - first_ctrl) > 1) + puts("Not all controllers have compatible interleaving mode. All disabled.\n"); } } debug("Checking interleaving options completed\n"); diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c new file mode 100644 index 0000000000..58b519b403 --- /dev/null +++ b/drivers/ddr/fsl/util.c @@ -0,0 +1,310 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#ifdef CONFIG_PPC +#include +#endif +#include + +#include +#include +#include + +/* To avoid 64-bit full-divides, we factor this here */ +#define ULL_2E12 2000000000000ULL +#define UL_5POW12 244140625UL +#define UL_2POW13 (1UL << 13) + +#define ULL_8FS 0xFFFFFFFFULL + +u32 fsl_ddr_get_version(void) +{ + struct ccsr_ddr __iomem *ddr; + u32 ver_major_minor_errata; + + ddr = (void *)_DDR_ADDR; + ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; + + return ver_major_minor_errata; +} + +/* + * Round up mclk_ps to nearest 1 ps in memory controller code + * if the error is 0.5ps or more. + * + * If an imprecise data rate is too high due to rounding error + * propagation, compute a suitably rounded mclk_ps to compute + * a working memory controller configuration. + */ +unsigned int get_memory_clk_period_ps(void) +{ + unsigned int data_rate = get_ddr_freq(0); + unsigned int result; + + /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ + unsigned long long rem, mclk_ps = ULL_2E12; + + /* Now perform the big divide, the result fits in 32-bits */ + rem = do_div(mclk_ps, data_rate); + result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; + + return result; +} + +/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ +unsigned int picos_to_mclk(unsigned int picos) +{ + unsigned long long clks, clks_rem; + unsigned long data_rate = get_ddr_freq(0); + + /* Short circuit for zero picos */ + if (!picos) + return 0; + + /* First multiply the time by the data rate (32x32 => 64) */ + clks = picos * (unsigned long long)data_rate; + /* + * Now divide by 5^12 and track the 32-bit remainder, then divide + * by 2*(2^12) using shifts (and updating the remainder). + */ + clks_rem = do_div(clks, UL_5POW12); + clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; + clks >>= 13; + + /* If we had a remainder greater than the 1ps error, then round up */ + if (clks_rem > data_rate) + clks++; + + /* Clamp to the maximum representable value */ + if (clks > ULL_8FS) + clks = ULL_8FS; + return (unsigned int) clks; +} + +unsigned int mclk_to_picos(unsigned int mclk) +{ + return get_memory_clk_period_ps() * mclk; +} + +#ifdef CONFIG_PPC +void +__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, + unsigned int law_memctl, + unsigned int ctrl_num) +{ + unsigned long long base = memctl_common_params->base_address; + unsigned long long size = memctl_common_params->total_mem; + + /* + * If no DIMMs on this controller, do not proceed any further. + */ + if (!memctl_common_params->ndimms_present) { + return; + } + +#if !defined(CONFIG_PHYS_64BIT) + if (base >= CONFIG_MAX_MEM_MAPPED) + return; + if ((base + size) >= CONFIG_MAX_MEM_MAPPED) + size = CONFIG_MAX_MEM_MAPPED - base; +#endif + if (set_ddr_laws(base, size, law_memctl) < 0) { + printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, + law_memctl); + return ; + } + debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", + base, size, law_memctl); +} + +__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void +fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); +#endif + +void fsl_ddr_set_intl3r(const unsigned int granule_size) +{ +#ifdef CONFIG_E6500 + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); + *mcintl3r = 0x80000000 | (granule_size & 0x1f); + debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); +#endif +} + +u32 fsl_ddr_get_intl3r(void) +{ + u32 val = 0; +#ifdef CONFIG_E6500 + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); + val = *mcintl3r; +#endif + return val; +} + +void print_ddr_info(unsigned int start_ctrl) +{ + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + +#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + uint32_t cs0_config = ddr_in32(&ddr->cs0_config); +#endif + uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); + int cas_lat; + +#if CONFIG_NUM_DDR_CONTROLLERS >= 2 + if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || + (start_ctrl == 1)) { + ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; + sdram_cfg = ddr_in32(&ddr->sdram_cfg); + } +#endif +#if CONFIG_NUM_DDR_CONTROLLERS >= 3 + if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || + (start_ctrl == 2)) { + ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; + sdram_cfg = ddr_in32(&ddr->sdram_cfg); + } +#endif + + if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { + puts(" (DDR not enabled)\n"); + return; + } + + puts(" (DDR"); + switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> + SDRAM_CFG_SDRAM_TYPE_SHIFT) { + case SDRAM_TYPE_DDR1: + puts("1"); + break; + case SDRAM_TYPE_DDR2: + puts("2"); + break; + case SDRAM_TYPE_DDR3: + puts("3"); + break; + case SDRAM_TYPE_DDR4: + puts("4"); + break; + default: + puts("?"); + break; + } + + if (sdram_cfg & SDRAM_CFG_32_BE) + puts(", 32-bit"); + else if (sdram_cfg & SDRAM_CFG_16_BE) + puts(", 16-bit"); + else + puts(", 64-bit"); + + /* Calculate CAS latency based on timing cfg values */ + cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); + if (fsl_ddr_get_version() <= 0x40400) + cas_lat += 1; + else + cas_lat += 2; + cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; + printf(", CL=%d", cas_lat >> 1); + if (cas_lat & 0x1) + puts(".5"); + + if (sdram_cfg & SDRAM_CFG_ECC_EN) + puts(", ECC on)"); + else + puts(", ECC off)"); + +#if (CONFIG_NUM_DDR_CONTROLLERS == 3) +#ifdef CONFIG_E6500 + if (*mcintl3r & 0x80000000) { + puts("\n"); + puts(" DDR Controller Interleaving Mode: "); + switch (*mcintl3r & 0x1f) { + case FSL_DDR_3WAY_1KB_INTERLEAVING: + puts("3-way 1KB"); + break; + case FSL_DDR_3WAY_4KB_INTERLEAVING: + puts("3-way 4KB"); + break; + case FSL_DDR_3WAY_8KB_INTERLEAVING: + puts("3-way 8KB"); + break; + default: + puts("3-way UNKNOWN"); + break; + } + } +#endif +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + if ((cs0_config & 0x20000000) && (start_ctrl == 0)) { + puts("\n"); + puts(" DDR Controller Interleaving Mode: "); + + switch ((cs0_config >> 24) & 0xf) { + case FSL_DDR_256B_INTERLEAVING: + puts("256B"); + break; + case FSL_DDR_CACHE_LINE_INTERLEAVING: + puts("cache line"); + break; + case FSL_DDR_PAGE_INTERLEAVING: + puts("page"); + break; + case FSL_DDR_BANK_INTERLEAVING: + puts("bank"); + break; + case FSL_DDR_SUPERBANK_INTERLEAVING: + puts("super-bank"); + break; + default: + puts("invalid"); + break; + } + } +#endif + + if ((sdram_cfg >> 8) & 0x7f) { + puts("\n"); + puts(" DDR Chip-Select Interleaving Mode: "); + switch(sdram_cfg >> 8 & 0x7f) { + case FSL_DDR_CS0_CS1_CS2_CS3: + puts("CS0+CS1+CS2+CS3"); + break; + case FSL_DDR_CS0_CS1: + puts("CS0+CS1"); + break; + case FSL_DDR_CS2_CS3: + puts("CS2+CS3"); + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + puts("CS0+CS1 and CS2+CS3"); + break; + default: + puts("invalid"); + break; + } + } +} + +void __weak detail_board_ddr_info(void) +{ + print_ddr_info(0); +} + +void board_add_ram_info(int use_default) +{ + detail_board_ddr_info(); +} diff --git a/drivers/demo/Makefile b/drivers/demo/Makefile new file mode 100644 index 0000000000..171ddf3678 --- /dev/null +++ b/drivers/demo/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (c) 2013 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += demo-uclass.o demo-pdata.o +obj-$(CONFIG_DM_DEMO_SIMPLE) += demo-simple.o +obj-$(CONFIG_DM_DEMO_SHAPE) += demo-shape.o diff --git a/drivers/demo/demo-pdata.c b/drivers/demo/demo-pdata.c new file mode 100644 index 0000000000..e92841db69 --- /dev/null +++ b/drivers/demo/demo-pdata.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static const struct dm_demo_pdata red_square = { + .colour = "red", + .sides = 4. +}; +static const struct dm_demo_pdata green_triangle = { + .colour = "green", + .sides = 3. +}; +static const struct dm_demo_pdata yellow_hexagon = { + .colour = "yellow", + .sides = 6. +}; + +U_BOOT_DEVICE(demo0) = { + .name = "demo_shape_drv", + .platdata = &red_square, +}; + +U_BOOT_DEVICE(demo1) = { + .name = "demo_simple_drv", + .platdata = &red_square, +}; + +U_BOOT_DEVICE(demo2) = { + .name = "demo_shape_drv", + .platdata = &green_triangle, +}; + +U_BOOT_DEVICE(demo3) = { + .name = "demo_simple_drv", + .platdata = &yellow_hexagon, +}; + +U_BOOT_DEVICE(demo4) = { + .name = "demo_shape_drv", + .platdata = &yellow_hexagon, +}; diff --git a/drivers/demo/demo-shape.c b/drivers/demo/demo-shape.c new file mode 100644 index 0000000000..d908736cff --- /dev/null +++ b/drivers/demo/demo-shape.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Shape size */ +#define WIDTH 8 +#define HEIGHT 6 + +struct shape_data { + int num_chars; /* Number of non-space characters output so far */ + struct gpio_desc gpio_desc[8]; + int gpio_count; +}; + +/* Crazy little function to draw shapes on the console */ +static int shape_hello(struct udevice *dev, int ch) +{ + const struct dm_demo_pdata *pdata = dev_get_platdata(dev); + struct shape_data *data = dev_get_priv(dev); + static const struct shape { + int start; + int end; + int dstart; + int dend; + } shapes[3] = { + { 0, 1, 0, 1 }, + { 0, WIDTH, 0, 0 }, + { HEIGHT / 2 - 1, WIDTH - HEIGHT / 2 + 1, -1, 1}, + }; + struct shape shape; + unsigned int index; + int line, pos, inside; + const char *colour = pdata->colour; + int first = 0; + + if (!ch) + ch = pdata->default_char; + if (!ch) + ch = '@'; + + index = (pdata->sides / 2) - 1; + if (index >= ARRAY_SIZE(shapes)) + return -EIO; + shape = shapes[index]; + + for (line = 0; line < HEIGHT; line++) { + first = 1; + for (pos = 0; pos < WIDTH; pos++) { + inside = pos >= shape.start && pos < shape.end; + if (inside) { + putc(first ? *colour++ : ch); + data->num_chars++; + first = 0; + if (!*colour) + colour = pdata->colour; + } else { + putc(' '); + } + } + putc('\n'); + shape.start += shape.dstart; + shape.end += shape.dend; + if (shape.start < 0) { + shape.dstart = -shape.dstart; + shape.dend = -shape.dend; + shape.start += shape.dstart; + shape.end += shape.dend; + } + } + + return 0; +} + +static int shape_status(struct udevice *dev, int *status) +{ + struct shape_data *data = dev_get_priv(dev); + + *status = data->num_chars; + return 0; +} + +static int set_light(struct udevice *dev, int light) +{ + struct shape_data *priv = dev_get_priv(dev); + struct gpio_desc *desc; + int ret; + int i; + + desc = priv->gpio_desc; + for (i = 0; i < priv->gpio_count; i++, desc++) { + uint mask = 1 << i; + + ret = dm_gpio_set_value(desc, light & mask); + if (ret < 0) + return ret; + } + + return 0; +} + +static int get_light(struct udevice *dev) +{ + struct shape_data *priv = dev_get_priv(dev); + struct gpio_desc *desc; + uint value = 0; + int ret; + int i; + + desc = priv->gpio_desc; + for (i = 0; i < priv->gpio_count; i++, desc++) { + uint mask = 1 << i; + + ret = dm_gpio_get_value(desc); + if (ret < 0) + return ret; + if (ret) + value |= mask; + } + + return value; +} + +static const struct demo_ops shape_ops = { + .hello = shape_hello, + .status = shape_status, + .get_light = get_light, + .set_light = set_light, +}; + +static int shape_ofdata_to_platdata(struct udevice *dev) +{ + struct dm_demo_pdata *pdata = dev_get_platdata(dev); + int ret; + + /* Parse the data that is common with all demo devices */ + ret = demo_parse_dt(dev); + if (ret) + return ret; + + /* Parse the data that only we need */ + pdata->default_char = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "character", '@'); + + return 0; +} + +static int dm_shape_probe(struct udevice *dev) +{ + struct shape_data *priv = dev_get_priv(dev); + int ret; + + ret = gpio_request_list_by_name(dev, "light-gpios", priv->gpio_desc, + ARRAY_SIZE(priv->gpio_desc), + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret < 0) + return ret; + priv->gpio_count = ret; + debug("%s: %d GPIOs\n", __func__, priv->gpio_count); + + return 0; +} + +static int dm_shape_remove(struct udevice *dev) +{ + struct shape_data *priv = dev_get_priv(dev); + + return gpio_free_list(dev, priv->gpio_desc, priv->gpio_count); +} + +static const struct udevice_id demo_shape_id[] = { + { "demo-shape", 0 }, + { }, +}; + +U_BOOT_DRIVER(demo_shape_drv) = { + .name = "demo_shape_drv", + .of_match = demo_shape_id, + .id = UCLASS_DEMO, + .ofdata_to_platdata = shape_ofdata_to_platdata, + .ops = &shape_ops, + .probe = dm_shape_probe, + .remove = dm_shape_remove, + .priv_auto_alloc_size = sizeof(struct shape_data), + .platdata_auto_alloc_size = sizeof(struct dm_demo_pdata), +}; diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c new file mode 100644 index 0000000000..2bcb7dfb47 --- /dev/null +++ b/drivers/demo/demo-simple.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static int simple_hello(struct udevice *dev, int ch) +{ + const struct dm_demo_pdata *pdata = dev_get_platdata(dev); + + printf("Hello from %08x: %s %d\n", map_to_sysmem(dev), pdata->colour, + pdata->sides); + + return 0; +} + +static const struct demo_ops simple_ops = { + .hello = simple_hello, +}; + +static int demo_shape_ofdata_to_platdata(struct udevice *dev) +{ + /* Parse the data that is common with all demo devices */ + return demo_parse_dt(dev); +} + +static const struct udevice_id demo_shape_id[] = { + { "demo-simple", 0 }, + { }, +}; + +U_BOOT_DRIVER(demo_simple_drv) = { + .name = "demo_simple_drv", + .of_match = demo_shape_id, + .id = UCLASS_DEMO, + .ofdata_to_platdata = demo_shape_ofdata_to_platdata, + .ops = &simple_ops, + .platdata_auto_alloc_size = sizeof(struct dm_demo_pdata), +}; diff --git a/drivers/demo/demo-uclass.c b/drivers/demo/demo-uclass.c new file mode 100644 index 0000000000..725f06898f --- /dev/null +++ b/drivers/demo/demo-uclass.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +UCLASS_DRIVER(demo) = { + .name = "demo", + .id = UCLASS_DEMO, +}; + +int demo_hello(struct udevice *dev, int ch) +{ + const struct demo_ops *ops = device_get_ops(dev); + + if (!ops->hello) + return -ENOSYS; + + return ops->hello(dev, ch); +} + +int demo_status(struct udevice *dev, int *status) +{ + const struct demo_ops *ops = device_get_ops(dev); + + if (!ops->status) + return -ENOSYS; + + return ops->status(dev, status); +} + +int demo_get_light(struct udevice *dev) +{ + const struct demo_ops *ops = device_get_ops(dev); + + if (!ops->get_light) + return -ENOSYS; + + return ops->get_light(dev); +} + +int demo_set_light(struct udevice *dev, int light) +{ + const struct demo_ops *ops = device_get_ops(dev); + + if (!ops->set_light) + return -ENOSYS; + + return ops->set_light(dev, light); +} + +int demo_parse_dt(struct udevice *dev) +{ + struct dm_demo_pdata *pdata = dev_get_platdata(dev); + int dn = dev->of_offset; + + pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0); + pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL); + if (!pdata->sides || !pdata->colour) { + debug("%s: Invalid device tree data\n", __func__); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile index fca370ae04..5cc535efdd 100644 --- a/drivers/dfu/Makefile +++ b/drivers/dfu/Makefile @@ -5,25 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libdfu.o - -COBJS-$(CONFIG_DFU_FUNCTION) += dfu.o -COBJS-$(CONFIG_DFU_MMC) += dfu_mmc.o -COBJS-$(CONFIG_DFU_NAND) += dfu_nand.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_DFU_FUNCTION) += dfu.o +obj-$(CONFIG_DFU_MMC) += dfu_mmc.o +obj-$(CONFIG_DFU_NAND) += dfu_nand.o +obj-$(CONFIG_DFU_RAM) += dfu_ram.o +obj-$(CONFIG_DFU_SF) += dfu_sf.o diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index d73d510391..ad0a7e7c25 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -13,21 +13,29 @@ #include #include #include +#include #include #include -static bool dfu_reset_request; static LIST_HEAD(dfu_list); static int dfu_alt_num; +static int alt_num_cnt; +static struct hash_algo *dfu_hash_algo; -bool dfu_reset(void) -{ - return dfu_reset_request; -} - -void dfu_trigger_reset() +/* + * The purpose of the dfu_usb_get_reset() function is to + * provide information if after USB_DETACH request + * being sent the dfu-util performed reset of USB + * bus. + * + * Described behaviour is the only way to distinct if + * user has typed -e (detach) or -R (reset) when invoking + * dfu-util command. + * + */ +__weak bool dfu_usb_get_reset(void) { - dfu_reset_request = true; + return true; } static int dfu_find_alt_num(const char *s) @@ -41,17 +49,45 @@ static int dfu_find_alt_num(const char *s) return ++i; } +int dfu_init_env_entities(char *interface, char *devstr) +{ + const char *str_env; + char *env_bkp; + int ret; + + str_env = getenv("dfu_alt_info"); + if (!str_env) { + error("\"dfu_alt_info\" env variable not defined!\n"); + return -EINVAL; + } + + env_bkp = strdup(str_env); + ret = dfu_config_entities(env_bkp, interface, devstr); + if (ret) { + error("DFU entities configuration failed!\n"); + return ret; + } + + free(env_bkp); + return 0; +} + static unsigned char *dfu_buf; static unsigned long dfu_buf_size = CONFIG_SYS_DFU_DATA_BUF_SIZE; -static unsigned char *dfu_free_buf(void) +unsigned char *dfu_free_buf(void) { free(dfu_buf); dfu_buf = NULL; return dfu_buf; } -static unsigned char *dfu_get_buf(void) +unsigned long dfu_get_buf_size(void) +{ + return dfu_buf_size; +} + +unsigned char *dfu_get_buf(struct dfu_entity *dfu) { char *s; @@ -59,8 +95,14 @@ static unsigned char *dfu_get_buf(void) return dfu_buf; s = getenv("dfu_bufsiz"); - dfu_buf_size = s ? (unsigned long)simple_strtol(s, NULL, 16) : - CONFIG_SYS_DFU_DATA_BUF_SIZE; + if (s) + dfu_buf_size = (unsigned long)simple_strtol(s, NULL, 0); + + if (!s || !dfu_buf_size) + dfu_buf_size = CONFIG_SYS_DFU_DATA_BUF_SIZE; + + if (dfu->max_buf_size && dfu_buf_size > dfu->max_buf_size) + dfu_buf_size = dfu->max_buf_size; dfu_buf = memalign(CONFIG_SYS_CACHELINE_SIZE, dfu_buf_size); if (dfu_buf == NULL) @@ -70,6 +112,23 @@ static unsigned char *dfu_get_buf(void) return dfu_buf; } +static char *dfu_get_hash_algo(void) +{ + char *s; + + s = getenv("dfu_hash_algo"); + if (!s) + return NULL; + + if (!strcmp(s, "crc32")) { + debug("%s: DFU hash method: %s\n", __func__, s); + return s; + } + + error("DFU hash method: %s not supported!\n", s); + return NULL; +} + static int dfu_write_buffer_drain(struct dfu_entity *dfu) { long w_size; @@ -80,8 +139,9 @@ static int dfu_write_buffer_drain(struct dfu_entity *dfu) if (w_size == 0) return 0; - /* update CRC32 */ - dfu->crc = crc32(dfu->crc, dfu->i_buf_start, w_size); + if (dfu_hash_algo) + dfu_hash_algo->hash_update(dfu_hash_algo, &dfu->crc, + dfu->i_buf_start, w_size, 0); ret = dfu->write_medium(dfu, dfu->offset, dfu->i_buf_start, &w_size); if (ret) @@ -98,10 +158,42 @@ static int dfu_write_buffer_drain(struct dfu_entity *dfu) return ret; } -int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) +void dfu_write_transaction_cleanup(struct dfu_entity *dfu) +{ + /* clear everything */ + dfu_free_buf(); + dfu->crc = 0; + dfu->offset = 0; + dfu->i_blk_seq_num = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf; + dfu->i_buf = dfu->i_buf_start; + dfu->inited = 0; +} + +int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { int ret = 0; - int tret; + + ret = dfu_write_buffer_drain(dfu); + if (ret) + return ret; + + if (dfu->flush_medium) + ret = dfu->flush_medium(dfu); + + if (dfu_hash_algo) + printf("\nDFU complete %s: 0x%08x\n", dfu_hash_algo->name, + dfu->crc); + + dfu_write_transaction_cleanup(dfu); + + return ret; +} + +int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) +{ + int ret; debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x offset: 0x%llx bufoffset: 0x%x\n", __func__, dfu->name, buf, size, blk_seq_num, dfu->offset, @@ -113,10 +205,10 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) dfu->offset = 0; dfu->bad_skip = 0; dfu->i_blk_seq_num = 0; - dfu->i_buf_start = dfu_get_buf(); + dfu->i_buf_start = dfu_get_buf(dfu); if (dfu->i_buf_start == NULL) return -ENOMEM; - dfu->i_buf_end = dfu_get_buf() + dfu_buf_size; + dfu->i_buf_end = dfu_get_buf(dfu) + dfu_buf_size; dfu->i_buf = dfu->i_buf_start; dfu->inited = 1; @@ -125,6 +217,7 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) if (dfu->i_blk_seq_num != blk_seq_num) { printf("%s: Wrong sequence number! [%d] [%d]\n", __func__, dfu->i_blk_seq_num, blk_seq_num); + dfu_write_transaction_cleanup(dfu); return -1; } @@ -146,15 +239,18 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) /* flush buffer if overflow */ if ((dfu->i_buf + size) > dfu->i_buf_end) { - tret = dfu_write_buffer_drain(dfu); - if (ret == 0) - ret = tret; + ret = dfu_write_buffer_drain(dfu); + if (ret) { + dfu_write_transaction_cleanup(dfu); + return ret; + } } /* we should be in buffer now (if not then size too large) */ if ((dfu->i_buf + size) > dfu->i_buf_end) { - printf("%s: Wrong size! [%d] [%d] - %d\n", - __func__, dfu->i_blk_seq_num, blk_seq_num, size); + error("Buffer overflow! (0x%p + 0x%x > 0x%p)\n", dfu->i_buf, + size, dfu->i_buf_end); + dfu_write_transaction_cleanup(dfu); return -1; } @@ -163,32 +259,14 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) /* if end or if buffer full flush */ if (size == 0 || (dfu->i_buf + size) > dfu->i_buf_end) { - tret = dfu_write_buffer_drain(dfu); - if (ret == 0) - ret = tret; - } - - /* end? */ - if (size == 0) { - /* Now try and flush to the medium if needed. */ - if (dfu->flush_medium) - ret = dfu->flush_medium(dfu); - printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc); - - /* clear everything */ - dfu_free_buf(); - dfu->crc = 0; - dfu->offset = 0; - dfu->i_blk_seq_num = 0; - dfu->i_buf_start = dfu_buf; - dfu->i_buf_end = dfu_buf; - dfu->i_buf = dfu->i_buf_start; - - dfu->inited = 0; - + ret = dfu_write_buffer_drain(dfu); + if (ret) { + dfu_write_transaction_cleanup(dfu); + return ret; + } } - return ret = 0 ? size : ret; + return 0; } static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size) @@ -199,11 +277,15 @@ static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size) readn = 0; while (size > 0) { /* get chunk that can be read */ - chunk = min(size, dfu->b_left); + chunk = min((long)size, dfu->b_left); /* consume */ if (chunk > 0) { memcpy(buf, dfu->i_buf, chunk); - dfu->crc = crc32(dfu->crc, buf, chunk); + if (dfu_hash_algo) + dfu_hash_algo->hash_update(dfu_hash_algo, + &dfu->crc, buf, + chunk, 0); + dfu->i_buf += chunk; dfu->b_left -= chunk; size -= chunk; @@ -247,14 +329,23 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) __func__, dfu->name, buf, size, blk_seq_num, dfu->i_buf); if (!dfu->inited) { - dfu->i_buf_start = dfu_get_buf(); + dfu->i_buf_start = dfu_get_buf(dfu); if (dfu->i_buf_start == NULL) return -ENOMEM; - ret = dfu->read_medium(dfu, 0, dfu->i_buf_start, &dfu->r_left); - if (ret != 0) { - debug("%s: failed to get r_left\n", __func__); - return ret; + dfu->r_left = dfu->get_medium_size(dfu); + if (dfu->r_left < 0) + return dfu->r_left; + switch (dfu->layout) { + case DFU_RAW_ADDR: + case DFU_RAM_ADDR: + break; + default: + if (dfu->r_left > dfu_buf_size) { + printf("%s: File too big for buffer\n", + __func__); + return -EOVERFLOW; + } } debug("%s: %s %ld [B]\n", __func__, dfu->name, dfu->r_left); @@ -262,7 +353,7 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) dfu->i_blk_seq_num = 0; dfu->crc = 0; dfu->offset = 0; - dfu->i_buf_end = dfu_get_buf() + dfu_buf_size; + dfu->i_buf_end = dfu_get_buf(dfu) + dfu_buf_size; dfu->i_buf = dfu->i_buf_start; dfu->b_left = 0; @@ -286,7 +377,9 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) } if (ret < size) { - debug("%s: %s CRC32: 0x%x\n", __func__, dfu->name, dfu->crc); + if (dfu_hash_algo) + debug("%s: %s %s: 0x%x\n", __func__, dfu->name, + dfu_hash_algo->name, dfu->crc); puts("\nUPLOAD ... done\nCtrl+C to exit ...\n"); dfu_free_buf(); @@ -307,23 +400,30 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) } static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt, - char *interface, int num) + char *interface, char *devstr) { char *st; - debug("%s: %s interface: %s num: %d\n", __func__, s, interface, num); + debug("%s: %s interface: %s dev: %s\n", __func__, s, interface, devstr); st = strsep(&s, " "); strcpy(dfu->name, st); - dfu->dev_num = num; dfu->alt = alt; + dfu->max_buf_size = 0; + dfu->free_entity = NULL; /* Specific for mmc device */ if (strcmp(interface, "mmc") == 0) { - if (dfu_fill_entity_mmc(dfu, s)) + if (dfu_fill_entity_mmc(dfu, devstr, s)) return -1; } else if (strcmp(interface, "nand") == 0) { - if (dfu_fill_entity_nand(dfu, s)) + if (dfu_fill_entity_nand(dfu, devstr, s)) + return -1; + } else if (strcmp(interface, "ram") == 0) { + if (dfu_fill_entity_ram(dfu, devstr, s)) + return -1; + } else if (strcmp(interface, "sf") == 0) { + if (dfu_fill_entity_sf(dfu, devstr, s)) return -1; } else { printf("%s: Device %s not (yet) supported!\n", @@ -340,14 +440,18 @@ void dfu_free_entities(void) list_for_each_entry_safe_reverse(dfu, p, &dfu_list, list) { list_del(&dfu->list); + if (dfu->free_entity) + dfu->free_entity(dfu); t = dfu; } if (t) free(t); INIT_LIST_HEAD(&dfu_list); + + alt_num_cnt = 0; } -int dfu_config_entities(char *env, char *interface, int num) +int dfu_config_entities(char *env, char *interface, char *devstr) { struct dfu_entity *dfu; int i, ret; @@ -356,17 +460,27 @@ int dfu_config_entities(char *env, char *interface, int num) dfu_alt_num = dfu_find_alt_num(env); debug("%s: dfu_alt_num=%d\n", __func__, dfu_alt_num); + dfu_hash_algo = NULL; + s = dfu_get_hash_algo(); + if (s) { + ret = hash_lookup_algo(s, &dfu_hash_algo); + if (ret) + error("Hash algorithm %s not supported\n", s); + } + dfu = calloc(sizeof(*dfu), dfu_alt_num); if (!dfu) return -1; for (i = 0; i < dfu_alt_num; i++) { s = strsep(&env, ";"); - ret = dfu_fill_entity(&dfu[i], s, i, interface, num); + ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface, + devstr); if (ret) return -1; list_add_tail(&dfu[i].list, &dfu_list); + alt_num_cnt++; } return 0; @@ -374,14 +488,14 @@ int dfu_config_entities(char *env, char *interface, int num) const char *dfu_get_dev_type(enum dfu_device_type t) { - const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND" }; + const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM" }; return dev_t[t]; } const char *dfu_get_layout(enum dfu_layout l) { const char *dfu_layout[] = {NULL, "RAW_ADDR", "FAT", "EXT2", - "EXT3", "EXT4" }; + "EXT3", "EXT4", "RAM_ADDR" }; return dfu_layout[l]; } @@ -414,3 +528,40 @@ struct dfu_entity *dfu_get_entity(int alt) return NULL; } + +int dfu_get_alt(char *name) +{ + struct dfu_entity *dfu; + char *str; + + list_for_each_entry(dfu, &dfu_list, list) { + if (dfu->name[0] != '/') { + if (!strncmp(dfu->name, name, strlen(dfu->name))) + return dfu->alt; + } else { + /* + * One must also consider absolute path + * (/boot/bin/uImage) available at dfu->name when + * compared "plain" file name (uImage) + * + * It is the case for e.g. thor gadget where lthor SW + * sends only the file name, so only the very last part + * of path must be checked for equality + */ + + str = strstr(dfu->name, name); + if (!str) + continue; + + /* + * Check if matching substring is the last element of + * dfu->name (uImage) + */ + if (strlen(dfu->name) == + ((str - dfu->name) + strlen(name))) + return dfu->alt; + } + } + + return -ENODEV; +} diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 0871a770b7..62d72fe4c6 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -12,21 +12,43 @@ #include #include #include - -enum dfu_mmc_op { - DFU_OP_READ = 1, - DFU_OP_WRITE, -}; +#include +#include +#include static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE]; static long dfu_file_buf_len; -static int mmc_block_op(enum dfu_mmc_op op, struct dfu_entity *dfu, +static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part) +{ + int ret; + + if (part == mmc->part_num) + return 0; + + ret = mmc_switch_part(dfu->data.mmc.dev_num, part); + if (ret) { + error("Cannot switch to partition %d\n", part); + return ret; + } + mmc->part_num = part; + + return 0; +} + +static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) { - char cmd_buf[DFU_CMD_BUF_SIZE]; - u32 blk_start, blk_count; + struct mmc *mmc; + u32 blk_start, blk_count, n = 0; + int ret, part_num_bkp = 0; + + mmc = find_mmc_device(dfu->data.mmc.dev_num); + if (!mmc) { + error("Device MMC %d - not found!", dfu->data.mmc.dev_num); + return -ENODEV; + } /* * We must ensure that we work in lba_blk_size chunks, so ALIGN @@ -43,12 +65,43 @@ static int mmc_block_op(enum dfu_mmc_op op, struct dfu_entity *dfu, return -EINVAL; } - sprintf(cmd_buf, "mmc %s %p %x %x", - op == DFU_OP_READ ? "read" : "write", - buf, blk_start, blk_count); + if (dfu->data.mmc.hw_partition >= 0) { + part_num_bkp = mmc->part_num; + ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition); + if (ret) + return ret; + } - debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); - return run_command(cmd_buf, 0); + debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__, + op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", + dfu->data.mmc.dev_num, blk_start, blk_count, buf); + switch (op) { + case DFU_OP_READ: + n = mmc->block_dev.block_read(dfu->data.mmc.dev_num, blk_start, + blk_count, buf); + break; + case DFU_OP_WRITE: + n = mmc->block_dev.block_write(dfu->data.mmc.dev_num, blk_start, + blk_count, buf); + break; + default: + error("Operation not supported\n"); + } + + if (n != blk_count) { + error("MMC operation failed"); + if (dfu->data.mmc.hw_partition >= 0) + mmc_access_part(dfu, mmc, part_num_bkp); + return -EIO; + } + + if (dfu->data.mmc.hw_partition >= 0) { + ret = mmc_access_part(dfu, mmc, part_num_bkp); + if (ret) + return ret; + } + + return 0; } static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) @@ -65,29 +118,20 @@ static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) return 0; } -static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, +static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, void *buf, long *len) { + const char *fsname, *opname; char cmd_buf[DFU_CMD_BUF_SIZE]; char *str_env; int ret; switch (dfu->layout) { case DFU_FS_FAT: - sprintf(cmd_buf, "fat%s mmc %d:%d 0x%x %s", - op == DFU_OP_READ ? "load" : "write", - dfu->data.mmc.dev, dfu->data.mmc.part, - (unsigned int) buf, dfu->name); - if (op == DFU_OP_WRITE) - sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len); + fsname = "fat"; break; case DFU_FS_EXT4: - sprintf(cmd_buf, "ext4%s mmc %d:%d 0x%x /%s", - op == DFU_OP_READ ? "load" : "write", - dfu->data.mmc.dev, dfu->data.mmc.part, - (unsigned int) buf, dfu->name); - if (op == DFU_OP_WRITE) - sprintf(cmd_buf + strlen(cmd_buf), " %ld", *len); + fsname = "ext4"; break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -95,6 +139,31 @@ static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, return -1; } + switch (op) { + case DFU_OP_READ: + opname = "load"; + break; + case DFU_OP_WRITE: + opname = "write"; + break; + case DFU_OP_SIZE: + opname = "size"; + break; + default: + return -1; + } + + sprintf(cmd_buf, "%s%s mmc %d:%d", fsname, opname, + dfu->data.mmc.dev, dfu->data.mmc.part); + + if (op != DFU_OP_SIZE) + sprintf(cmd_buf + strlen(cmd_buf), " 0x%x", (unsigned int)buf); + + sprintf(cmd_buf + strlen(cmd_buf), " %s", dfu->name); + + if (op == DFU_OP_WRITE) + sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len); + debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); ret = run_command(cmd_buf, 0); @@ -103,7 +172,7 @@ static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, return ret; } - if (dfu->layout != DFU_RAW_ADDR && op == DFU_OP_READ) { + if (op != DFU_OP_WRITE) { str_env = getenv("filesize"); if (str_env == NULL) { puts("dfu: Wrong file size!\n"); @@ -152,6 +221,27 @@ int dfu_flush_medium_mmc(struct dfu_entity *dfu) return ret; } +long dfu_get_medium_size_mmc(struct dfu_entity *dfu) +{ + int ret; + long len; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + return dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size; + case DFU_FS_FAT: + case DFU_FS_EXT4: + ret = mmc_file_op(DFU_OP_SIZE, dfu, NULL, &len); + if (ret < 0) + return ret; + return len; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + return -1; + } +} + int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, long *len) { @@ -173,66 +263,112 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, return ret; } -int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) +/* + * @param s Parameter string containing space-separated arguments: + * 1st: + * raw (raw read/write) + * fat (files) + * ext4 (^) + * part (partition image) + * 2nd and 3rd: + * lba_start and lba_size, for raw write + * mmc_dev and mmc_part, for filesystems and part + * 4th (optional): + * mmcpart (access to HW eMMC partitions) + */ +int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s) { - int dev, part; - struct mmc *mmc; - block_dev_desc_t *blk_dev; - disk_partition_t partinfo; - char *st; + const char *entity_type; + size_t second_arg; + size_t third_arg; - dfu->dev_type = DFU_DEV_MMC; - st = strsep(&s, " "); - if (!strcmp(st, "mmc")) { - dfu->layout = DFU_RAW_ADDR; - dfu->data.mmc.lba_start = simple_strtoul(s, &s, 16); - dfu->data.mmc.lba_size = simple_strtoul(++s, &s, 16); - dfu->data.mmc.lba_blk_size = get_mmc_blk_size(dfu->dev_num); - } else if (!strcmp(st, "fat")) { - dfu->layout = DFU_FS_FAT; - } else if (!strcmp(st, "ext4")) { - dfu->layout = DFU_FS_EXT4; - } else if (!strcmp(st, "part")) { + struct mmc *mmc; - dfu->layout = DFU_RAW_ADDR; + const char *argv[3]; + const char **parg = argv; - dev = simple_strtoul(s, &s, 10); - s++; - part = simple_strtoul(s, &s, 10); + dfu->data.mmc.dev_num = simple_strtoul(devstr, NULL, 10); - mmc = find_mmc_device(dev); - if (mmc == NULL || mmc_init(mmc)) { - printf("%s: could not find mmc device #%d!\n", - __func__, dev); + for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) { + *parg = strsep(&s, " "); + if (*parg == NULL) { + error("Invalid number of arguments.\n"); return -ENODEV; } + } - blk_dev = &mmc->block_dev; - if (get_partition_info(blk_dev, part, &partinfo) != 0) { - printf("%s: could not find partition #%d on mmc device #%d!\n", - __func__, part, dev); + entity_type = argv[0]; + /* + * Base 0 means we'll accept (prefixed with 0x or 0) base 16, 8, + * with default 10. + */ + second_arg = simple_strtoul(argv[1], NULL, 0); + third_arg = simple_strtoul(argv[2], NULL, 0); + + mmc = find_mmc_device(dfu->data.mmc.dev_num); + if (mmc == NULL) { + error("Couldn't find MMC device no. %d.\n", + dfu->data.mmc.dev_num); + return -ENODEV; + } + + if (mmc_init(mmc)) { + error("Couldn't init MMC device.\n"); + return -ENODEV; + } + + dfu->data.mmc.hw_partition = -EINVAL; + if (!strcmp(entity_type, "raw")) { + dfu->layout = DFU_RAW_ADDR; + dfu->data.mmc.lba_start = second_arg; + dfu->data.mmc.lba_size = third_arg; + dfu->data.mmc.lba_blk_size = mmc->read_bl_len; + + /* + * Check for an extra entry at dfu_alt_info env variable + * specifying the mmc HW defined partition number + */ + if (s) + if (!strcmp(strsep(&s, " "), "mmcpart")) + dfu->data.mmc.hw_partition = + simple_strtoul(s, NULL, 0); + + } else if (!strcmp(entity_type, "part")) { + disk_partition_t partinfo; + block_dev_desc_t *blk_dev = &mmc->block_dev; + int mmcdev = second_arg; + int mmcpart = third_arg; + + if (get_partition_info(blk_dev, mmcpart, &partinfo) != 0) { + error("Couldn't find part #%d on mmc device #%d\n", + mmcpart, mmcdev); return -ENODEV; } - dfu->data.mmc.lba_start = partinfo.start; - dfu->data.mmc.lba_size = partinfo.size; - dfu->data.mmc.lba_blk_size = partinfo.blksz; - + dfu->layout = DFU_RAW_ADDR; + dfu->data.mmc.lba_start = partinfo.start; + dfu->data.mmc.lba_size = partinfo.size; + dfu->data.mmc.lba_blk_size = partinfo.blksz; + } else if (!strcmp(entity_type, "fat")) { + dfu->layout = DFU_FS_FAT; + } else if (!strcmp(entity_type, "ext4")) { + dfu->layout = DFU_FS_EXT4; } else { - printf("%s: Memory layout (%s) not supported!\n", __func__, st); + error("Memory layout (%s) not supported!\n", entity_type); return -ENODEV; } - if (dfu->layout == DFU_FS_EXT4 || dfu->layout == DFU_FS_FAT) { - dfu->data.mmc.dev = simple_strtoul(s, &s, 10); - dfu->data.mmc.part = simple_strtoul(++s, &s, 10); + /* if it's NOT a raw write */ + if (strcmp(entity_type, "raw")) { + dfu->data.mmc.dev = second_arg; + dfu->data.mmc.part = third_arg; } + dfu->dev_type = DFU_DEV_MMC; + dfu->get_medium_size = dfu_get_medium_size_mmc; dfu->read_medium = dfu_read_medium_mmc; dfu->write_medium = dfu_write_medium_mmc; dfu->flush_medium = dfu_flush_medium_mmc; - - /* initial state */ dfu->inited = 0; return 0; diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 2a01cc11b8..f9ee18999a 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -19,12 +19,7 @@ #include #include -enum dfu_nand_op { - DFU_OP_READ = 1, - DFU_OP_WRITE, -}; - -static int nand_block_op(enum dfu_nand_op op, struct dfu_entity *dfu, +static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) { loff_t start, lim; @@ -119,6 +114,11 @@ static int dfu_write_medium_nand(struct dfu_entity *dfu, return ret; } +long dfu_get_medium_size_nand(struct dfu_entity *dfu) +{ + return dfu->data.nand.size; +} + static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf, long *len) { @@ -136,11 +136,55 @@ static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf, return ret; } -int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) +static int dfu_flush_medium_nand(struct dfu_entity *dfu) +{ + int ret = 0; + + /* in case of ubi partition, erase rest of the partition */ + if (dfu->data.nand.ubi) { + nand_info_t *nand; + nand_erase_options_t opts; + + if (nand_curr_device < 0 || + nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || + !nand_info[nand_curr_device].name) { + printf("%s: invalid nand device\n", __func__); + return -1; + } + + nand = &nand_info[nand_curr_device]; + + memset(&opts, 0, sizeof(opts)); + opts.offset = dfu->data.nand.start + dfu->offset + + dfu->bad_skip; + opts.length = dfu->data.nand.start + + dfu->data.nand.size - opts.offset; + ret = nand_erase_opts(nand, &opts); + if (ret != 0) + printf("Failure erase: %d\n", ret); + } + + return ret; +} + +unsigned int dfu_polltimeout_nand(struct dfu_entity *dfu) +{ + /* + * Currently, Poll Timeout != 0 is only needed on nand + * ubi partition, as the not used sectors need an erase + */ + if (dfu->data.nand.ubi) + return DFU_MANIFEST_POLL_TIMEOUT; + + return DFU_DEFAULT_POLL_TIMEOUT; +} + +int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s) { char *st; int ret, dev, part; + dfu->data.nand.ubi = 0; dfu->dev_type = DFU_DEV_NAND; st = strsep(&s, " "); if (!strcmp(st, "raw")) { @@ -148,7 +192,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) dfu->data.nand.start = simple_strtoul(s, &s, 16); s++; dfu->data.nand.size = simple_strtoul(s, &s, 16); - } else if (!strcmp(st, "part")) { + } else if ((!strcmp(st, "part")) || (!strcmp(st, "partubi"))) { char mtd_id[32]; struct mtd_device *mtd_dev; u8 part_num; @@ -173,14 +217,18 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) dfu->data.nand.start = pi->offset; dfu->data.nand.size = pi->size; - + if (!strcmp(st, "partubi")) + dfu->data.nand.ubi = 1; } else { printf("%s: Memory layout (%s) not supported!\n", __func__, st); return -1; } + dfu->get_medium_size = dfu_get_medium_size_nand; dfu->read_medium = dfu_read_medium_nand; dfu->write_medium = dfu_write_medium_nand; + dfu->flush_medium = dfu_flush_medium_nand; + dfu->poll_timeout = dfu_polltimeout_nand; /* initial state */ dfu->inited = 0; diff --git a/drivers/dfu/dfu_ram.c b/drivers/dfu/dfu_ram.c new file mode 100644 index 0000000000..e094a946f6 --- /dev/null +++ b/drivers/dfu/dfu_ram.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2013 + * Afzal Mohammed + * + * Reference: dfu_mmc.c + * Copyright (C) 2012 Samsung Electronics + * author: Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static int dfu_transfer_medium_ram(enum dfu_op op, struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + if (dfu->layout != DFU_RAM_ADDR) { + error("unsupported layout: %s\n", dfu_get_layout(dfu->layout)); + return -EINVAL; + } + + if (offset > dfu->data.ram.size) { + error("request exceeds allowed area\n"); + return -EINVAL; + } + + if (op == DFU_OP_WRITE) + memcpy(dfu->data.ram.start + offset, buf, *len); + else + memcpy(buf, dfu->data.ram.start + offset, *len); + + return 0; +} + +static int dfu_write_medium_ram(struct dfu_entity *dfu, u64 offset, + void *buf, long *len) +{ + return dfu_transfer_medium_ram(DFU_OP_WRITE, dfu, offset, buf, len); +} + +long dfu_get_medium_size_ram(struct dfu_entity *dfu) +{ + return dfu->data.ram.size; +} + +static int dfu_read_medium_ram(struct dfu_entity *dfu, u64 offset, + void *buf, long *len) +{ + return dfu_transfer_medium_ram(DFU_OP_READ, dfu, offset, buf, len); +} + +int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s) +{ + char *st; + + dfu->dev_type = DFU_DEV_RAM; + st = strsep(&s, " "); + if (strcmp(st, "ram")) { + error("unsupported device: %s\n", st); + return -ENODEV; + } + + dfu->layout = DFU_RAM_ADDR; + dfu->data.ram.start = (void *)simple_strtoul(s, &s, 16); + s++; + dfu->data.ram.size = simple_strtoul(s, &s, 16); + + dfu->write_medium = dfu_write_medium_ram; + dfu->get_medium_size = dfu_get_medium_size_ram; + dfu->read_medium = dfu_read_medium_ram; + + dfu->inited = 0; + + return 0; +} diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c new file mode 100644 index 0000000000..c3d3c3bcd8 --- /dev/null +++ b/drivers/dfu/dfu_sf.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static long dfu_get_medium_size_sf(struct dfu_entity *dfu) +{ + return dfu->data.sf.size; +} + +static int dfu_read_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf, + long *len) +{ + return spi_flash_read(dfu->data.sf.dev, offset, *len, buf); +} + +static int dfu_write_medium_sf(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + int ret; + + ret = spi_flash_erase(dfu->data.sf.dev, offset, *len); + if (ret) + return ret; + + ret = spi_flash_write(dfu->data.sf.dev, offset, *len, buf); + if (ret) + return ret; + + return 0; +} + +static int dfu_flush_medium_sf(struct dfu_entity *dfu) +{ + return 0; +} + +static unsigned int dfu_polltimeout_sf(struct dfu_entity *dfu) +{ + return DFU_DEFAULT_POLL_TIMEOUT; +} + +static void dfu_free_entity_sf(struct dfu_entity *dfu) +{ + spi_flash_free(dfu->data.sf.dev); +} + +static struct spi_flash *parse_dev(char *devstr) +{ + unsigned int bus; + unsigned int cs; + unsigned int speed = CONFIG_SF_DEFAULT_SPEED; + unsigned int mode = CONFIG_SF_DEFAULT_MODE; + char *s, *endp; + struct spi_flash *dev; + + s = strsep(&devstr, ":"); + if (!s || !*s || (bus = simple_strtoul(s, &endp, 0), *endp)) { + printf("Invalid SPI bus %s\n", s); + return NULL; + } + + s = strsep(&devstr, ":"); + if (!s || !*s || (cs = simple_strtoul(s, &endp, 0), *endp)) { + printf("Invalid SPI chip-select %s\n", s); + return NULL; + } + + s = strsep(&devstr, ":"); + if (s && *s) { + speed = simple_strtoul(s, &endp, 0); + if (*endp || !speed) { + printf("Invalid SPI speed %s\n", s); + return NULL; + } + } + + s = strsep(&devstr, ":"); + if (s && *s) { + mode = simple_strtoul(s, &endp, 0); + if (*endp || mode > 3) { + printf("Invalid SPI mode %s\n", s); + return NULL; + } + } + + dev = spi_flash_probe(bus, cs, speed, mode); + if (!dev) { + printf("Failed to create SPI flash at %d:%d:%d:%d\n", + bus, cs, speed, mode); + return NULL; + } + + return dev; +} + +int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s) +{ + char *st; + + dfu->data.sf.dev = parse_dev(devstr); + if (!dfu->data.sf.dev) + return -ENODEV; + + dfu->dev_type = DFU_DEV_SF; + dfu->max_buf_size = dfu->data.sf.dev->sector_size; + + st = strsep(&s, " "); + if (!strcmp(st, "raw")) { + dfu->layout = DFU_RAW_ADDR; + dfu->data.sf.start = simple_strtoul(s, &s, 16); + s++; + dfu->data.sf.size = simple_strtoul(s, &s, 16); + } else { + printf("%s: Memory layout (%s) not supported!\n", __func__, st); + spi_flash_free(dfu->data.sf.dev); + return -1; + } + + dfu->get_medium_size = dfu_get_medium_size_sf; + dfu->read_medium = dfu_read_medium_sf; + dfu->write_medium = dfu_write_medium_sf; + dfu->flush_medium = dfu_flush_medium_sf; + dfu->poll_timeout = dfu_polltimeout_sf; + dfu->free_entity = dfu_free_entity_sf; + + /* initial state */ + dfu->inited = 0; + + return 0; +} diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig new file mode 100644 index 0000000000..a6da34198c --- /dev/null +++ b/drivers/dma/Kconfig @@ -0,0 +1,14 @@ +config APBH_DMA + bool "Freescale MXS and i.MX6 APBH DMA support" + default y + depends on SOC_MX28 || SOC_MX6 + +config APBH_DMA_BURST + bool "Enable DMA burst mode" + default y + depends on APBH_DMA + +config APBH_DMA_BURST8 + bool "Use 8-beat DMA bursts" + default y + depends on APBH_DMA_BURST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index a6132e22e7..4c8fcc2575 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -5,29 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libdma.o - -COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o -COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o -COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o -COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o +obj-$(CONFIG_APBH_DMA) += apbh_dma.o +obj-$(CONFIG_FSL_DMA) += fsl_dma.o +obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o +obj-$(CONFIG_TI_EDMA3) += ti-edma3.o diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index eab87bc9f4..4c5732e76e 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -210,10 +210,10 @@ static int mxs_dma_disable(int channel) static int mxs_dma_reset(int channel) { int ret; -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) uint32_t *setreg = &apbh_regs->hw_apbh_ctrl0_set; uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET; -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) +#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6)) uint32_t *setreg = &apbh_regs->hw_apbh_channel_ctrl_set; uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; #endif @@ -584,6 +584,28 @@ int mxs_dma_go(int chan) return ret; } +/* + * Execute a continuously running circular DMA descriptor. + * NOTE: This is not intended for general use, but rather + * for the LCD driver in Smart-LCD mode. It allows + * continuous triggering of the RUN bit there. + */ +void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc) +{ + struct mxs_apbh_regs *apbh_regs = + (struct mxs_apbh_regs *)MXS_APBH_BASE; + + mxs_dma_flush_desc(pdesc); + + mxs_dma_enable_irq(chan, 1); + + writel(mxs_dma_cmd_address(pdesc), + &apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar); + writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema); + writel(1 << (chan + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET), + &apbh_regs->hw_apbh_ctrl0_clr); +} + /* * Initialize the DMA hardware */ diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 45e49c7faf..7ef7f12b0a 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -96,7 +96,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { uint xfer_size; while (count) { - xfer_size = MIN(FSL_DMA_MAX_SIZE, count); + xfer_size = min(FSL_DMA_MAX_SIZE, count); out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF)); out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF)); diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c new file mode 100644 index 0000000000..dfca75abdc --- /dev/null +++ b/drivers/dma/keystone_nav.c @@ -0,0 +1,320 @@ +/* + * Multicore Navigator driver for TI Keystone 2 devices. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +struct qm_config qm_memmap = { + .stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE, + .queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE, + .mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS, + .i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE, + .proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE, + .status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE, + .mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE, + .intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE, + .desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE, + .region_num = CONFIG_KSNAV_QM_REGION_NUM, + .pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE, + .pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE, + .pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE, + .qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM, +}; + +/* + * We are going to use only one type of descriptors - host packet + * descriptors. We staticaly allocate memory for them here + */ +struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc)); + +static struct qm_config *qm_cfg; + +inline int num_of_desc_to_reg(int num_descr) +{ + int j, num; + + for (j = 0, num = 32; j < 15; j++, num *= 2) { + if (num_descr <= num) + return j; + } + + return 15; +} + +int _qm_init(struct qm_config *cfg) +{ + u32 j; + + qm_cfg = cfg; + + qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram; + qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8; + qm_cfg->mngr_cfg->link_ram_base1 = 0; + qm_cfg->mngr_cfg->link_ram_size1 = 0; + qm_cfg->mngr_cfg->link_ram_base2 = 0; + + qm_cfg->desc_mem[0].base_addr = (u32)desc_pool; + qm_cfg->desc_mem[0].start_idx = 0; + qm_cfg->desc_mem[0].desc_reg_size = + (((sizeof(struct qm_host_desc) >> 4) - 1) << 16) | + num_of_desc_to_reg(HDESC_NUM); + + memset(desc_pool, 0, sizeof(desc_pool)); + for (j = 0; j < HDESC_NUM; j++) + qm_push(&desc_pool[j], qm_cfg->qpool_num); + + return QM_OK; +} + +int qm_init(void) +{ + return _qm_init(&qm_memmap); +} + +void qm_close(void) +{ + u32 j; + + queue_close(qm_cfg->qpool_num); + + qm_cfg->mngr_cfg->link_ram_base0 = 0; + qm_cfg->mngr_cfg->link_ram_size0 = 0; + qm_cfg->mngr_cfg->link_ram_base1 = 0; + qm_cfg->mngr_cfg->link_ram_size1 = 0; + qm_cfg->mngr_cfg->link_ram_base2 = 0; + + for (j = 0; j < qm_cfg->region_num; j++) { + qm_cfg->desc_mem[j].base_addr = 0; + qm_cfg->desc_mem[j].start_idx = 0; + qm_cfg->desc_mem[j].desc_reg_size = 0; + } + + qm_cfg = NULL; +} + +void qm_push(struct qm_host_desc *hd, u32 qnum) +{ + u32 regd; + + cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4); + regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1); + writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh); +} + +void qm_buff_push(struct qm_host_desc *hd, u32 qnum, + void *buff_ptr, u32 buff_len) +{ + hd->orig_buff_len = buff_len; + hd->buff_len = buff_len; + hd->orig_buff_ptr = (u32)buff_ptr; + hd->buff_ptr = (u32)buff_ptr; + qm_push(hd, qnum); +} + +struct qm_host_desc *qm_pop(u32 qnum) +{ + u32 uhd; + + uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf; + if (uhd) + cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4); + + return (struct qm_host_desc *)uhd; +} + +struct qm_host_desc *qm_pop_from_free_pool(void) +{ + return qm_pop(qm_cfg->qpool_num); +} + +void queue_close(u32 qnum) +{ + struct qm_host_desc *hd; + + while ((hd = qm_pop(qnum))) + ; +} + +/** + * DMA API + */ + +static int ksnav_rx_disable(struct pktdma_cfg *pktdma) +{ + u32 j, v, k; + + for (j = 0; j < pktdma->rx_ch_num; j++) { + v = readl(&pktdma->rx_ch[j].cfg_a); + if (!(v & CPDMA_CHAN_A_ENABLE)) + continue; + + writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->rx_ch[j].cfg_a); + for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) { + udelay(100); + v = readl(&pktdma->rx_ch[j].cfg_a); + if (!(v & CPDMA_CHAN_A_ENABLE)) + continue; + } + /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */ + } + + /* Clear all of the flow registers */ + for (j = 0; j < pktdma->rx_flow_num; j++) { + writel(0, &pktdma->rx_flows[j].control); + writel(0, &pktdma->rx_flows[j].tags); + writel(0, &pktdma->rx_flows[j].tag_sel); + writel(0, &pktdma->rx_flows[j].fdq_sel[0]); + writel(0, &pktdma->rx_flows[j].fdq_sel[1]); + writel(0, &pktdma->rx_flows[j].thresh[0]); + writel(0, &pktdma->rx_flows[j].thresh[1]); + writel(0, &pktdma->rx_flows[j].thresh[2]); + } + + return QM_OK; +} + +static int ksnav_tx_disable(struct pktdma_cfg *pktdma) +{ + u32 j, v, k; + + for (j = 0; j < pktdma->tx_ch_num; j++) { + v = readl(&pktdma->tx_ch[j].cfg_a); + if (!(v & CPDMA_CHAN_A_ENABLE)) + continue; + + writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->tx_ch[j].cfg_a); + for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) { + udelay(100); + v = readl(&pktdma->tx_ch[j].cfg_a); + if (!(v & CPDMA_CHAN_A_ENABLE)) + continue; + } + /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */ + } + + return QM_OK; +} + +int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers) +{ + u32 j, v; + struct qm_host_desc *hd; + u8 *rx_ptr; + + if (pktdma == NULL || rx_buffers == NULL || + rx_buffers->buff_ptr == NULL || qm_cfg == NULL) + return QM_ERR; + + pktdma->rx_flow = rx_buffers->rx_flow; + + /* init rx queue */ + rx_ptr = rx_buffers->buff_ptr; + + for (j = 0; j < rx_buffers->num_buffs; j++) { + hd = qm_pop(qm_cfg->qpool_num); + if (hd == NULL) + return QM_ERR; + + qm_buff_push(hd, pktdma->rx_free_q, + rx_ptr, rx_buffers->buff_len); + + rx_ptr += rx_buffers->buff_len; + } + + ksnav_rx_disable(pktdma); + + /* configure rx channels */ + v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, pktdma->rx_rcv_q); + writel(v, &pktdma->rx_flows[pktdma->rx_flow].control); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].tags); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].tag_sel); + + v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, pktdma->rx_free_q, 0, + pktdma->rx_free_q); + + writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[0]); + writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[1]); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[0]); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[1]); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[2]); + + for (j = 0; j < pktdma->rx_ch_num; j++) + writel(CPDMA_CHAN_A_ENABLE, &pktdma->rx_ch[j].cfg_a); + + /* configure tx channels */ + /* Disable loopback in the tx direction */ + writel(0, &pktdma->global->emulation_control); + + /* Set QM base address, only for K2x devices */ + writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]); + + /* Enable all channels. The current state isn't important */ + for (j = 0; j < pktdma->tx_ch_num; j++) { + writel(0, &pktdma->tx_ch[j].cfg_b); + writel(CPDMA_CHAN_A_ENABLE, &pktdma->tx_ch[j].cfg_a); + } + + return QM_OK; +} + +int ksnav_close(struct pktdma_cfg *pktdma) +{ + if (!pktdma) + return QM_ERR; + + ksnav_tx_disable(pktdma); + ksnav_rx_disable(pktdma); + + queue_close(pktdma->rx_free_q); + queue_close(pktdma->rx_rcv_q); + queue_close(pktdma->tx_snd_q); + + return QM_OK; +} + +int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2) +{ + struct qm_host_desc *hd; + + hd = qm_pop(qm_cfg->qpool_num); + if (hd == NULL) + return QM_ERR; + + hd->desc_info = num_bytes; + hd->swinfo[2] = swinfo2; + hd->packet_info = qm_cfg->qpool_num; + + qm_buff_push(hd, pktdma->tx_snd_q, pkt, num_bytes); + + return QM_OK; +} + +void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes) +{ + struct qm_host_desc *hd; + + hd = qm_pop(pktdma->rx_rcv_q); + if (!hd) + return NULL; + + *pkt = (u32 *)hd->buff_ptr; + *num_bytes = hd->desc_info & 0x3fffff; + + return hd; +} + +void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd) +{ + struct qm_host_desc *_hd = (struct qm_host_desc *)hd; + + _hd->buff_len = _hd->orig_buff_len; + _hd->buff_ptr = _hd->orig_buff_ptr; + + qm_push(_hd, pktdma->rx_free_q); +} diff --git a/drivers/dma/keystone_nav_cfg.c b/drivers/dma/keystone_nav_cfg.c new file mode 100644 index 0000000000..bdd30a0262 --- /dev/null +++ b/drivers/dma/keystone_nav_cfg.c @@ -0,0 +1,27 @@ +/* + * Multicore Navigator driver for TI Keystone 2 devices. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifdef CONFIG_KSNAV_PKTDMA_NETCP +/* NETCP Pktdma */ +struct pktdma_cfg netcp_pktdma = { + .global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE, + .tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE, + .tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM, + .rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE, + .rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM, + .tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE, + .rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE, + .rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM, + .rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE, + .rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE, + .tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE, +}; +#endif diff --git a/drivers/dma/omap3_dma.c b/drivers/dma/omap3_dma.c deleted file mode 100644 index 3320b3d08d..0000000000 --- a/drivers/dma/omap3_dma.c +++ /dev/null @@ -1,167 +0,0 @@ -/* Copyright (C) 2011 - * Corscience GmbH & Co. KG - Simon Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* This is a basic implementation of the SDMA/DMA4 controller of OMAP3 - * Tested on Silicon Revision major:0x4 minor:0x0 - */ - -#include -#include -#include -#include -#include -#include - -static struct dma4 *dma4_cfg = (struct dma4 *)OMAP34XX_DMA4_BASE; -uint32_t dma_active; /* if a transfer is started the respective - bit is set for the logical channel */ - -/* Check if we have the given channel - * PARAMETERS: - * chan: Channel number - * - * RETURN of non-zero means error */ -static inline int check_channel(uint32_t chan) -{ - if (chan < CHAN_NR_MIN || chan > CHAN_NR_MAX) - return -EINVAL; - return 0; -} - -static inline void reset_irq(uint32_t chan) -{ - /* reset IRQ reason */ - writel(0x1DFE, &dma4_cfg->chan[chan].csr); - /* reset IRQ */ - writel((1 << chan), &dma4_cfg->irqstatus_l[0]); - dma_active &= ~(1 << chan); -} - -/* Set Source, Destination and Size of DMA transfer for the - * specified channel. - * PARAMETERS: - * chan: channel to use - * src: source of the transfer - * dst: destination of the transfer - * sze: Size of the transfer - * - * RETURN of non-zero means error */ -int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, - uint32_t sze) -{ - if (check_channel(chan)) - return -EINVAL; - /* CDSA0 */ - writel((uint32_t)src, &dma4_cfg->chan[chan].cssa); - writel((uint32_t)dst, &dma4_cfg->chan[chan].cdsa); - writel(sze, &dma4_cfg->chan[chan].cen); -return 0; -} - -/* Start the DMA transfer */ -int omap3_dma_start_transfer(uint32_t chan) -{ - uint32_t val; - - if (check_channel(chan)) - return -EINVAL; - - val = readl(&dma4_cfg->chan[chan].ccr); - /* Test for channel already in use */ - if (val & CCR_ENABLE_ENABLE) - return -EBUSY; - - writel((val | CCR_ENABLE_ENABLE), &dma4_cfg->chan[chan].ccr); - dma_active |= (1 << chan); - debug("started transfer...\n"); - return 0; -} - -/* Busy-waiting for a DMA transfer - * This has to be called before another transfer is started - * PARAMETER - * chan: Channel to wait for - * - * RETURN of non-zero means error*/ -int omap3_dma_wait_for_transfer(uint32_t chan) -{ - uint32_t val; - - if (!(dma_active & (1 << chan))) { - val = readl(&dma4_cfg->irqstatus_l[0]); - if (!(val & chan)) { - debug("dma: The channel you are trying to wait for " - "was never activated - ERROR\n"); - return -1; /* channel was never active */ - } - } - - /* all irqs on line 0 */ - while (!(readl(&dma4_cfg->irqstatus_l[0]) & (1 << chan))) - asm("nop"); - - val = readl(&dma4_cfg->chan[chan].csr); - if ((val & CSR_TRANS_ERR) | (val & CSR_SUPERVISOR_ERR) | - (val & CSR_MISALIGNED_ADRS_ERR)) { - debug("err code: %X\n", val); - debug("dma: transfer error detected\n"); - reset_irq(chan); - return -1; - } - reset_irq(chan); - return 0; -} - -/* Get the revision of the DMA module - * PARAMETER - * minor: Address of minor revision to write - * major: Address of major revision to write - * - * RETURN of non-zero means error - */ -int omap3_dma_get_revision(uint32_t *minor, uint32_t *major) -{ - uint32_t val; - - /* debug information */ - val = readl(&dma4_cfg->revision); - *major = (val & 0x000000F0) >> 4; - *minor = (val & 0x0000000F); - debug("DMA Silicon revision (maj/min): 0x%X/0x%X\n", *major, *minor); - return 0; -} - -/* Initial config of omap dma - */ -void omap3_dma_init(void) -{ - dma_active = 0; - /* All interrupts on channel 0 */ - writel(0xFFFFFFFF, &dma4_cfg->irqenable_l[0]); -} - -/* set channel config to config - * - * RETURN of non-zero means error */ -int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config) -{ - if (check_channel(chan)) - return -EINVAL; - - dma4_cfg->chan[chan] = *config; - return 0; -} - -/* get channel config to config - * - * RETURN of non-zero means error */ -int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config) -{ - if (check_channel(chan)) - return -EINVAL; - *config = dma4_cfg->chan[chan]; - return 0; -} diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c new file mode 100644 index 0000000000..8184ded9fa --- /dev/null +++ b/drivers/dma/ti-edma3.c @@ -0,0 +1,384 @@ +/* + * Enhanced Direct Memory Access (EDMA3) Controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * Author: Ivan Khoronzhuk + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5)) +#define EDMA3_SL_MAX_NUM 512 +#define EDMA3_SLOPT_FIFO_WIDTH_MASK (0x7 << 8) + +#define EDMA3_QCHMAP(ch) 0x0200 + ((ch) << 2) +#define EDMA3_CHMAP_PARSET_MASK 0x1ff +#define EDMA3_CHMAP_PARSET_SHIFT 0x5 +#define EDMA3_CHMAP_TRIGWORD_SHIFT 0x2 + +#define EDMA3_QEMCR 0x314 +#define EDMA3_IPR 0x1068 +#define EDMA3_IPRH 0x106c +#define EDMA3_ICR 0x1070 +#define EDMA3_ICRH 0x1074 +#define EDMA3_QEECR 0x1088 +#define EDMA3_QEESR 0x108c +#define EDMA3_QSECR 0x1094 + +/** + * qedma3_start - start qdma on a channel + * @base: base address of edma + * @cfg: pinter to struct edma3_channel_config where you can set + * the slot number to associate with, the chnum, which corresponds + * your quick channel number 0-7, complete code - transfer complete code + * and trigger slot word - which has to correspond to the word number in + * edma3_slot_layout struct for generating event. + * + */ +void qedma3_start(u32 base, struct edma3_channel_config *cfg) +{ + u32 qchmap; + + /* Clear the pending int bit */ + if (cfg->complete_code < 32) + __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); + else + __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH); + + /* Map parameter set and trigger word 7 to quick channel */ + qchmap = ((EDMA3_CHMAP_PARSET_MASK & cfg->slot) + << EDMA3_CHMAP_PARSET_SHIFT) | + (cfg->trigger_slot_word << EDMA3_CHMAP_TRIGWORD_SHIFT); + + __raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum)); + + /* Clear missed event if set*/ + __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR); + __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR); + + /* Enable qdma channel event */ + __raw_writel(1 << cfg->chnum, base + EDMA3_QEESR); +} + +/** + * edma3_set_dest - set initial DMA destination address in parameter RAM slot + * @base: base address of edma + * @slot: parameter RAM slot being configured + * @dst: physical address of destination (memory, controller FIFO, etc) + * @addressMode: INCR, except in very rare cases + * @width: ignored unless @addressMode is FIFO, else specifies the + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * + * Note that the destination address is modified during the DMA transfer + * according to edma3_set_dest_index(). + */ +void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode, + enum edma3_fifo_width width) +{ + u32 opt; + struct edma3_slot_layout *rg; + + rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot)); + + opt = __raw_readl(&rg->opt); + if (mode == FIFO) + opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) | + (EDMA3_SLOPT_DST_ADDR_CONST_MODE | + EDMA3_SLOPT_FIFO_WIDTH_SET(width)); + else + opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE; + + __raw_writel(opt, &rg->opt); + __raw_writel(dst, &rg->dst); +} + +/** + * edma3_set_dest_index - configure DMA destination address indexing + * @base: base address of edma + * @slot: parameter RAM slot being configured + * @bidx: byte offset between destination arrays in a frame + * @cidx: byte offset between destination frames in a block + * + * Offsets are specified to support either contiguous or discontiguous + * memory transfers, or repeated access to a hardware register, as needed. + * When accessing hardware registers, both offsets are normally zero. + */ +void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx) +{ + u32 src_dst_bidx; + u32 src_dst_cidx; + struct edma3_slot_layout *rg; + + rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot)); + + src_dst_bidx = __raw_readl(&rg->src_dst_bidx); + src_dst_cidx = __raw_readl(&rg->src_dst_cidx); + + __raw_writel((src_dst_bidx & 0x0000ffff) | (bidx << 16), + &rg->src_dst_bidx); + __raw_writel((src_dst_cidx & 0x0000ffff) | (cidx << 16), + &rg->src_dst_cidx); +} + +/** + * edma3_set_dest_addr - set destination address for slot only + */ +void edma3_set_dest_addr(u32 base, int slot, u32 dst) +{ + struct edma3_slot_layout *rg; + + rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot)); + __raw_writel(dst, &rg->dst); +} + +/** + * edma3_set_src - set initial DMA source address in parameter RAM slot + * @base: base address of edma + * @slot: parameter RAM slot being configured + * @src_port: physical address of source (memory, controller FIFO, etc) + * @mode: INCR, except in very rare cases + * @width: ignored unless @addressMode is FIFO, else specifies the + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * + * Note that the source address is modified during the DMA transfer + * according to edma3_set_src_index(). + */ +void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode, + enum edma3_fifo_width width) +{ + u32 opt; + struct edma3_slot_layout *rg; + + rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot)); + + opt = __raw_readl(&rg->opt); + if (mode == FIFO) + opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) | + (EDMA3_SLOPT_DST_ADDR_CONST_MODE | + EDMA3_SLOPT_FIFO_WIDTH_SET(width)); + else + opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE; + + __raw_writel(opt, &rg->opt); + __raw_writel(src, &rg->src); +} + +/** + * edma3_set_src_index - configure DMA source address indexing + * @base: base address of edma + * @slot: parameter RAM slot being configured + * @bidx: byte offset between source arrays in a frame + * @cidx: byte offset between source frames in a block + * + * Offsets are specified to support either contiguous or discontiguous + * memory transfers, or repeated access to a hardware register, as needed. + * When accessing hardware registers, both offsets are normally zero. + */ +void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx) +{ + u32 src_dst_bidx; + u32 src_dst_cidx; + struct edma3_slot_layout *rg; + + rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot)); + + src_dst_bidx = __raw_readl(&rg->src_dst_bidx); + src_dst_cidx = __raw_readl(&rg->src_dst_cidx); + + __raw_writel((src_dst_bidx & 0xffff0000) | bidx, + &rg->src_dst_bidx); + __raw_writel((src_dst_cidx & 0xffff0000) | cidx, + &rg->src_dst_cidx); +} + +/** + * edma3_set_src_addr - set source address for slot only + */ +void edma3_set_src_addr(u32 base, int slot, u32 src) +{ + struct edma3_slot_layout *rg; + + rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot)); + __raw_writel(src, &rg->src); +} + +/** + * edma3_set_transfer_params - configure DMA transfer parameters + * @base: base address of edma + * @slot: parameter RAM slot being configured + * @acnt: how many bytes per array (at least one) + * @bcnt: how many arrays per frame (at least one) + * @ccnt: how many frames per block (at least one) + * @bcnt_rld: used only for A-Synchronized transfers; this specifies + * the value to reload into bcnt when it decrements to zero + * @sync_mode: ASYNC or ABSYNC + * + * See the EDMA3 documentation to understand how to configure and link + * transfers using the fields in PaRAM slots. If you are not doing it + * all at once with edma3_write_slot(), you will use this routine + * plus two calls each for source and destination, setting the initial + * address and saying how to index that address. + * + * An example of an A-Synchronized transfer is a serial link using a + * single word shift register. In that case, @acnt would be equal to + * that word size; the serial controller issues a DMA synchronization + * event to transfer each word, and memory access by the DMA transfer + * controller will be word-at-a-time. + * + * An example of an AB-Synchronized transfer is a device using a FIFO. + * In that case, @acnt equals the FIFO width and @bcnt equals its depth. + * The controller with the FIFO issues DMA synchronization events when + * the FIFO threshold is reached, and the DMA transfer controller will + * transfer one frame to (or from) the FIFO. It will probably use + * efficient burst modes to access memory. + */ +void edma3_set_transfer_params(u32 base, int slot, int acnt, + int bcnt, int ccnt, u16 bcnt_rld, + enum edma3_sync_dimension sync_mode) +{ + u32 opt; + u32 link_bcntrld; + struct edma3_slot_layout *rg; + + rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot)); + + link_bcntrld = __raw_readl(&rg->link_bcntrld); + + __raw_writel((bcnt_rld << 16) | (0x0000ffff & link_bcntrld), + &rg->link_bcntrld); + + opt = __raw_readl(&rg->opt); + if (sync_mode == ASYNC) + __raw_writel(opt & ~EDMA3_SLOPT_AB_SYNC, &rg->opt); + else + __raw_writel(opt | EDMA3_SLOPT_AB_SYNC, &rg->opt); + + /* Set the acount, bcount, ccount registers */ + __raw_writel((bcnt << 16) | (acnt & 0xffff), &rg->a_b_cnt); + __raw_writel(0xffff & ccnt, &rg->ccnt); +} + +/** + * edma3_write_slot - write parameter RAM data for slot + * @base: base address of edma + * @slot: number of parameter RAM slot being modified + * @param: data to be written into parameter RAM slot + * + * Use this to assign all parameters of a transfer at once. This + * allows more efficient setup of transfers than issuing multiple + * calls to set up those parameters in small pieces, and provides + * complete control over all transfer options. + */ +void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param) +{ + int i; + u32 *p = (u32 *)param; + u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot)); + + for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4) + __raw_writel(*p++, addr++); +} + +/** + * edma3_read_slot - read parameter RAM data from slot + * @base: base address of edma + * @slot: number of parameter RAM slot being copied + * @param: where to store copy of parameter RAM data + * + * Use this to read data from a parameter RAM slot, perhaps to + * save them as a template for later reuse. + */ +void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param) +{ + int i; + u32 *p = (u32 *)param; + u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot)); + + for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4) + *p++ = __raw_readl(addr++); +} + +void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg) +{ + struct edma3_slot_layout *rg; + + rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot)); + + __raw_writel(cfg->opt, &rg->opt); + __raw_writel(cfg->src, &rg->src); + __raw_writel((cfg->bcnt << 16) | (cfg->acnt & 0xffff), &rg->a_b_cnt); + __raw_writel(cfg->dst, &rg->dst); + __raw_writel((cfg->dst_bidx << 16) | + (cfg->src_bidx & 0xffff), &rg->src_dst_bidx); + __raw_writel((cfg->bcntrld << 16) | + (cfg->link & 0xffff), &rg->link_bcntrld); + __raw_writel((cfg->dst_cidx << 16) | + (cfg->src_cidx & 0xffff), &rg->src_dst_cidx); + __raw_writel(0xffff & cfg->ccnt, &rg->ccnt); +} + +/** + * edma3_check_for_transfer - check if transfer coplete by checking + * interrupt pending bit. Clear interrupt pending bit if complete. + * @base: base address of edma + * @cfg: pinter to struct edma3_channel_config which was passed + * to qedma3_start when you started qdma channel + * + * Return 0 if complete, 1 if not. + */ +int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg) +{ + u32 inum; + u32 ipr_base; + u32 icr_base; + + if (cfg->complete_code < 32) { + ipr_base = base + EDMA3_IPR; + icr_base = base + EDMA3_ICR; + inum = 1 << cfg->complete_code; + } else { + ipr_base = base + EDMA3_IPRH; + icr_base = base + EDMA3_ICRH; + inum = 1 << (cfg->complete_code - 32); + } + + /* check complete interrupt */ + if (!(__raw_readl(ipr_base) & inum)) + return 1; + + /* clean up the pending int bit */ + __raw_writel(inum, icr_base); + + return 0; +} + +/** + * qedma3_stop - stops dma on the channel passed + * @base: base address of edma + * @cfg: pinter to struct edma3_channel_config which was passed + * to qedma3_start when you started qdma channel + */ +void qedma3_stop(u32 base, struct edma3_channel_config *cfg) +{ + /* Disable qdma channel event */ + __raw_writel(1 << cfg->chnum, base + EDMA3_QEECR); + + /* clean up the interrupt indication */ + if (cfg->complete_code < 32) + __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); + else + __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH); + + /* Clear missed event if set*/ + __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR); + __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR); + + /* Clear the channel map */ + __raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum)); +} diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index a1a0602ab2..6aa24d4359 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -5,40 +5,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libfpga.o - -ifdef CONFIG_FPGA -COBJS-y += fpga.o -COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o -COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o -COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o -COBJS-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o -COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o -COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o +obj-y += fpga.o +obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o +obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o +obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o +obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o +obj-$(CONFIG_FPGA_XILINX) += xilinx.o +obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o ifdef CONFIG_FPGA_ALTERA -COBJS-y += altera.o -COBJS-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o -COBJS-$(CONFIG_FPGA_CYCLON2) += cyclon2.o -COBJS-$(CONFIG_FPGA_STRATIX_II) += stratixII.o -endif +obj-y += altera.o +obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o +obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o +obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o +obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o endif - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index af189f4ef4..a5bfe5dce1 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,216 +12,162 @@ * Altera FPGA support */ #include +#include #include #include -/* Define FPGA_DEBUG to get debug printf's */ -/* #define FPGA_DEBUG */ +/* Define FPGA_DEBUG to 1 to get debug printf's */ +#define FPGA_DEBUG 0 -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* Local Static Functions */ -static int altera_validate (Altera_desc * desc, const char *fn); - -/* ------------------------------------------------------------------------- */ -int altera_load(Altera_desc *desc, const void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (!altera_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else { - switch (desc->family) { - case Altera_ACEX1K: - case Altera_CYC2: +static const struct altera_fpga { + enum altera_family family; + const char *name; + int (*load)(Altera_desc *, const void *, size_t); + int (*dump)(Altera_desc *, const void *, size_t); + int (*info)(Altera_desc *); +} altera_fpga[] = { #if defined(CONFIG_FPGA_ACEX1K) - PRINTF ("%s: Launching the ACEX1K Loader...\n", - __FUNCTION__); - ret_val = ACEX1K_load (desc, buf, bsize); + { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, + { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, #elif defined(CONFIG_FPGA_CYCLON2) - PRINTF ("%s: Launching the CYCLONE II Loader...\n", - __FUNCTION__); - ret_val = CYC2_load (desc, buf, bsize); -#else - printf ("%s: No support for ACEX1K devices.\n", - __FUNCTION__); + { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, + { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, #endif - break; - #if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - PRINTF ("%s: Launching the Stratix II Loader...\n", - __FUNCTION__); - ret_val = StratixII_load (desc, buf, bsize); - break; + { Altera_StratixII, "StratixII", StratixII_load, + StratixII_dump, StratixII_info }, +#endif +#if defined(CONFIG_FPGA_SOCFPGA) + { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, #endif - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } +}; + +static int altera_validate(Altera_desc *desc, const char *fn) +{ + if (!desc) { + printf("%s: NULL descriptor!\n", fn); + return -EINVAL; + } + + if ((desc->family < min_altera_type) || + (desc->family > max_altera_type)) { + printf("%s: Invalid family type, %d\n", fn, desc->family); + return -EINVAL; + } + + if ((desc->iface < min_altera_iface_type) || + (desc->iface > max_altera_iface_type)) { + printf("%s: Invalid Interface type, %d\n", fn, desc->iface); + return -EINVAL; } - return ret_val; + if (!desc->size) { + printf("%s: NULL part size\n", fn); + return -EINVAL; + } + + return 0; } -int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) +static const struct altera_fpga * +altera_desc_to_fpga(Altera_desc *desc, const char *fn) { - int ret_val = FPGA_FAIL; /* assume a failure */ + int i; - if (!altera_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else { - switch (desc->family) { - case Altera_ACEX1K: -#if defined(CONFIG_FPGA_ACEX) - PRINTF ("%s: Launching the ACEX1K Reader...\n", - __FUNCTION__); - ret_val = ACEX1K_dump (desc, buf, bsize); -#else - printf ("%s: No support for ACEX1K devices.\n", - __FUNCTION__); -#endif - break; + if (altera_validate(desc, fn)) { + printf("%s: Invalid device descriptor\n", fn); + return NULL; + } -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - PRINTF ("%s: Launching the Stratix II Reader...\n", - __FUNCTION__); - ret_val = StratixII_dump (desc, buf, bsize); + for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) { + if (desc->family == altera_fpga[i].family) break; -#endif - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } } - return ret_val; + if (i == ARRAY_SIZE(altera_fpga)) { + printf("%s: Unsupported family type, %d\n", fn, desc->family); + return NULL; + } + + return &altera_fpga[i]; } -int altera_info( Altera_desc *desc ) +int altera_load(Altera_desc *desc, const void *buf, size_t bsize) { - int ret_val = FPGA_FAIL; + const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); - if (altera_validate (desc, (char *)__FUNCTION__)) { - printf ("Family: \t"); - switch (desc->family) { - case Altera_ACEX1K: - printf ("ACEX1K\n"); - break; - case Altera_CYC2: - printf ("CYCLON II\n"); - break; - case Altera_StratixII: - printf ("Stratix II\n"); - break; - /* Add new family types here */ - default: - printf ("Unknown family type, %d\n", desc->family); - } - - printf ("Interface type:\t"); - switch (desc->iface) { - case passive_serial: - printf ("Passive Serial (PS)\n"); - break; - case passive_parallel_synchronous: - printf ("Passive Parallel Synchronous (PPS)\n"); - break; - case passive_parallel_asynchronous: - printf ("Passive Parallel Asynchronous (PPA)\n"); - break; - case passive_serial_asynchronous: - printf ("Passive Serial Asynchronous (PSA)\n"); - break; - case altera_jtag_mode: /* Not used */ - printf ("JTAG Mode\n"); - break; - case fast_passive_parallel: - printf ("Fast Passive Parallel (FPP)\n"); - break; - case fast_passive_parallel_security: - printf - ("Fast Passive Parallel with Security (FPPS) \n"); - break; - /* Add new interface types here */ - default: - printf ("Unsupported interface type, %d\n", desc->iface); - } - - printf ("Device Size: \t%d bytes\n" - "Cookie: \t0x%x (%d)\n", - desc->size, desc->cookie, desc->cookie); - - if (desc->iface_fns) { - printf ("Device Function Table @ 0x%p\n", desc->iface_fns); - switch (desc->family) { - case Altera_ACEX1K: - case Altera_CYC2: -#if defined(CONFIG_FPGA_ACEX1K) - ACEX1K_info (desc); -#elif defined(CONFIG_FPGA_CYCLON2) - CYC2_info (desc); -#else - /* just in case */ - printf ("%s: No support for ACEX1K devices.\n", - __FUNCTION__); -#endif - break; -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - StratixII_info (desc); - break; -#endif - /* Add new family types here */ - default: - /* we don't need a message here - we give one up above */ - break; - } - } else { - printf ("No Device Function Table.\n"); - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } + if (!fpga) + return FPGA_FAIL; - return ret_val; + debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n", + __func__, fpga->name); + if (fpga->load) + return fpga->load(desc, buf, bsize); + return 0; } -/* ------------------------------------------------------------------------- */ +int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) +{ + const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); + + if (!fpga) + return FPGA_FAIL; -static int altera_validate (Altera_desc * desc, const char *fn) + debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n", + __func__, fpga->name); + if (fpga->dump) + return fpga->dump(desc, buf, bsize); + return 0; +} + +int altera_info(Altera_desc *desc) { - int ret_val = false; - - if (desc) { - if ((desc->family > min_altera_type) && - (desc->family < max_altera_type)) { - if ((desc->iface > min_altera_iface_type) && - (desc->iface < max_altera_iface_type)) { - if (desc->size) { - ret_val = true; - } else { - printf ("%s: NULL part size\n", fn); - } - } else { - printf ("%s: Invalid Interface type, %d\n", - fn, desc->iface); - } - } else { - printf ("%s: Invalid family type, %d\n", fn, desc->family); - } + const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); + + if (!fpga) + return FPGA_FAIL; + + printf("Family: \t%s\n", fpga->name); + + printf("Interface type:\t"); + switch (desc->iface) { + case passive_serial: + printf("Passive Serial (PS)\n"); + break; + case passive_parallel_synchronous: + printf("Passive Parallel Synchronous (PPS)\n"); + break; + case passive_parallel_asynchronous: + printf("Passive Parallel Asynchronous (PPA)\n"); + break; + case passive_serial_asynchronous: + printf("Passive Serial Asynchronous (PSA)\n"); + break; + case altera_jtag_mode: /* Not used */ + printf("JTAG Mode\n"); + break; + case fast_passive_parallel: + printf("Fast Passive Parallel (FPP)\n"); + break; + case fast_passive_parallel_security: + printf("Fast Passive Parallel with Security (FPPS)\n"); + break; + /* Add new interface types here */ + default: + printf("Unsupported interface type, %d\n", desc->iface); + } + + printf("Device Size: \t%zd bytes\n" + "Cookie: \t0x%x (%d)\n", + desc->size, desc->cookie, desc->cookie); + + if (desc->iface_fns) { + printf("Device Function Table @ 0x%p\n", desc->iface_fns); + if (fpga->info) + fpga->info(desc); } else { - printf ("%s: NULL descriptor!\n", fn); + printf("No Device Function Table.\n"); } - return ret_val; + return FPGA_SUCCESS; } - -/* ------------------------------------------------------------------------- */ diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index b940d9b316..d94eb5cc25 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -38,7 +38,7 @@ static void fpga_no_sup(char *fn, char *msg) /* fpga_get_desc * map a device number to a descriptor */ -static const fpga_desc *const fpga_get_desc(int devnum) +const fpga_desc *const fpga_get_desc(int devnum) { fpga_desc *desc = (fpga_desc *)NULL; @@ -173,16 +173,45 @@ int fpga_add(fpga_type devtype, void *desc) /* * Convert bitstream data and load into the fpga */ -int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { printf("Bitstream support not implemented for this FPGA device\n"); return FPGA_FAIL; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo) +{ + int ret_val = FPGA_FAIL; /* assume failure */ + const fpga_desc *desc = fpga_validate(devnum, buf, size, + (char *)__func__); + + if (desc) { + switch (desc->devtype) { + case fpga_xilinx: +#if defined(CONFIG_FPGA_XILINX) + ret_val = xilinx_loadfs(desc->devdesc, buf, size, + fpga_fsinfo); +#else + fpga_no_sup((char *)__func__, "Xilinx devices"); +#endif + break; + default: + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); + } + } + + return ret_val; +} +#endif + /* * Generic multiplexing code */ -int fpga_load(int devnum, const void *buf, size_t bsize) +int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype) { int ret_val = FPGA_FAIL; /* assume failure */ const fpga_desc *desc = fpga_validate(devnum, buf, bsize, @@ -192,7 +221,8 @@ int fpga_load(int devnum, const void *buf, size_t bsize) switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_load(desc->devdesc, buf, bsize); + ret_val = xilinx_load(desc->devdesc, buf, bsize, + bstype); #else fpga_no_sup((char *)__func__, "Xilinx devices"); #endif diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c new file mode 100644 index 0000000000..63b3566e3e --- /dev/null +++ b/drivers/fpga/socfpga.c @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Timeout count */ +#define FPGA_TIMEOUT_CNT 0x1000000 + +static struct socfpga_fpga_manager *fpgamgr_regs = + (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* Set CD ratio */ +static void fpgamgr_set_cd_ratio(unsigned long ratio) +{ + clrsetbits_le32(&fpgamgr_regs->ctrl, + 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB, + (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); +} + +static int fpgamgr_dclkcnt_set(unsigned long cnt) +{ + unsigned long i; + + /* Clear any existing done status */ + if (readl(&fpgamgr_regs->dclkstat)) + writel(0x1, &fpgamgr_regs->dclkstat); + + /* Write the dclkcnt */ + writel(cnt, &fpgamgr_regs->dclkcnt); + + /* Wait till the dclkcnt done */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (!readl(&fpgamgr_regs->dclkstat)) + continue; + + writel(0x1, &fpgamgr_regs->dclkstat); + return 0; + } + + return -ETIMEDOUT; +} + +/* Start the FPGA programming by initialize the FPGA Manager */ +static int fpgamgr_program_init(void) +{ + unsigned long msel, i; + + /* Get the MSEL value */ + msel = readl(&fpgamgr_regs->stat); + msel &= FPGAMGRREGS_STAT_MSEL_MASK; + msel >>= FPGAMGRREGS_STAT_MSEL_LSB; + + /* + * Set the cfg width + * If MSEL[3] = 1, cfg width = 32 bit + */ + if (msel & 0x8) { + setbits_le32(&fpgamgr_regs->ctrl, + FPGAMGRREGS_CTRL_CFGWDTH_MASK); + + /* To determine the CD ratio */ + /* MSEL[1:0] = 0, CD Ratio = 1 */ + if ((msel & 0x3) == 0x0) + fpgamgr_set_cd_ratio(CDRATIO_x1); + /* MSEL[1:0] = 1, CD Ratio = 4 */ + else if ((msel & 0x3) == 0x1) + fpgamgr_set_cd_ratio(CDRATIO_x4); + /* MSEL[1:0] = 2, CD Ratio = 8 */ + else if ((msel & 0x3) == 0x2) + fpgamgr_set_cd_ratio(CDRATIO_x8); + + } else { /* MSEL[3] = 0 */ + clrbits_le32(&fpgamgr_regs->ctrl, + FPGAMGRREGS_CTRL_CFGWDTH_MASK); + + /* To determine the CD ratio */ + /* MSEL[1:0] = 0, CD Ratio = 1 */ + if ((msel & 0x3) == 0x0) + fpgamgr_set_cd_ratio(CDRATIO_x1); + /* MSEL[1:0] = 1, CD Ratio = 2 */ + else if ((msel & 0x3) == 0x1) + fpgamgr_set_cd_ratio(CDRATIO_x2); + /* MSEL[1:0] = 2, CD Ratio = 4 */ + else if ((msel & 0x3) == 0x2) + fpgamgr_set_cd_ratio(CDRATIO_x4); + } + + /* To enable FPGA Manager configuration */ + clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); + + /* To enable FPGA Manager drive over configuration line */ + setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); + + /* Put FPGA into reset phase */ + setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); + + /* (1) wait until FPGA enter reset phase */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE) + break; + } + + /* If not in reset state, return error */ + if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) { + puts("FPGA: Could not reset\n"); + return -1; + } + + /* Release FPGA from reset phase */ + clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); + + /* (2) wait until FPGA enter configuration phase */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE) + break; + } + + /* If not in configuration state, return error */ + if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) { + puts("FPGA: Could not configure\n"); + return -2; + } + + /* Clear all interrupts in CB Monitor */ + writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi); + + /* Enable AXI configuration */ + setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); + + return 0; +} + +/* Write the RBF data to FPGA Manager */ +static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) +{ + uint32_t src = (uint32_t)rbf_data; + uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS; + + /* Number of loops for 32-byte long copying. */ + uint32_t loops32 = rbf_size / 32; + /* Number of loops for 4-byte long copying + trailing bytes */ + uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); + + asm volatile( + "1: ldmia %0!, {r0-r7}\n" + " stmia %1!, {r0-r7}\n" + " sub %1, #32\n" + " subs %2, #1\n" + " bne 1b\n" + "2: ldr %2, [%0], #4\n" + " str %2, [%1]\n" + " subs %3, #1\n" + " bne 2b\n" + : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); +} + +/* Ensure the FPGA entering config done */ +static int fpgamgr_program_poll_cd(void) +{ + const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | + FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; + unsigned long reg, i; + + /* (3) wait until full config done */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + reg = readl(&fpgamgr_regs->gpio_ext_porta); + + /* Config error */ + if (!(reg & mask)) { + printf("FPGA: Configuration error.\n"); + return -3; + } + + /* Config done without error */ + if (reg & mask) + break; + } + + /* Timeout happened, return error */ + if (i == FPGA_TIMEOUT_CNT) { + printf("FPGA: Timeout waiting for program.\n"); + return -4; + } + + /* Disable AXI configuration */ + clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); + + return 0; +} + +/* Ensure the FPGA entering init phase */ +static int fpgamgr_program_poll_initphase(void) +{ + unsigned long i; + + /* Additional clocks for the CB to enter initialization phase */ + if (fpgamgr_dclkcnt_set(0x4)) + return -5; + + /* (4) wait until FPGA enter init phase or user mode */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) + break; + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) + break; + } + + /* If not in configuration state, return error */ + if (i == FPGA_TIMEOUT_CNT) + return -6; + + return 0; +} + +/* Ensure the FPGA entering user mode */ +static int fpgamgr_program_poll_usermode(void) +{ + unsigned long i; + + /* Additional clocks for the CB to exit initialization phase */ + if (fpgamgr_dclkcnt_set(0x5000)) + return -7; + + /* (5) wait until FPGA enter user mode */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) + break; + } + /* If not in configuration state, return error */ + if (i == FPGA_TIMEOUT_CNT) + return -8; + + /* To release FPGA Manager drive over configuration line */ + clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); + + return 0; +} + +/* + * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. + * Return 0 for sucess, non-zero for error. + */ +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + unsigned long status; + + if ((uint32_t)rbf_data & 0x3) { + puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); + return -EINVAL; + } + + /* Prior programming the FPGA, all bridges need to be shut off */ + + /* Disable all signals from hps peripheral controller to fpga */ + writel(0, &sysmgr_regs->fpgaintfgrp_module); + + /* Disable all signals from FPGA to HPS SDRAM */ +#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 + writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); + + /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ + socfpga_bridges_reset(1); + + /* Unmap the bridges from NIC-301 */ + writel(0x1, SOCFPGA_L3REGS_ADDRESS); + + /* Initialize the FPGA Manager */ + status = fpgamgr_program_init(); + if (status) + return status; + + /* Write the RBF data to FPGA Manager */ + fpgamgr_program_write(rbf_data, rbf_size); + + /* Ensure the FPGA entering config done */ + status = fpgamgr_program_poll_cd(); + if (status) + return status; + + /* Ensure the FPGA entering init phase */ + status = fpgamgr_program_poll_initphase(); + if (status) + return status; + + /* Ensure the FPGA entering user mode */ + return fpgamgr_program_poll_usermode(); +} diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 6eab1b51e5..859fb3c778 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -31,29 +31,30 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_sp_info(xilinx_desc *desc ); */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_ss_info(xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan2_ss_load (desc, buf, bsize); + ret_val = spartan2_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan2_sp_load (desc, buf, bsize); + ret_val = spartan2_sp_load(desc, buf, bsize); break; default: @@ -64,19 +65,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan2_ss_dump (desc, buf, bsize); + ret_val = spartan2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan2_sp_dump (desc, buf, bsize); + ret_val = spartan2_sp_dump(desc, buf, bsize); break; default: @@ -87,7 +88,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_info( Xilinx_desc *desc ) +static int spartan2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -96,10 +97,10 @@ int Spartan2_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -248,10 +249,10 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -296,10 +297,10 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -439,7 +440,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ @@ -447,3 +448,9 @@ static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan2_op = { + .load = spartan2_load, + .dump = spartan2_dump, + .info = spartan2_info, +}; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 3edc5c2c66..b0213e6999 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -35,29 +35,30 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_sp_info(xilinx_desc *desc ); */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_ss_info(Xilinx_desc *desc); */ +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_ss_info(xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan3_ss_load (desc, buf, bsize); + ret_val = spartan3_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan3_sp_load (desc, buf, bsize); + ret_val = spartan3_sp_load(desc, buf, bsize); break; default: @@ -68,19 +69,19 @@ int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan3_ss_dump (desc, buf, bsize); + ret_val = spartan3_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan3_sp_dump (desc, buf, bsize); + ret_val = spartan3_sp_dump(desc, buf, bsize); break; default: @@ -91,7 +92,7 @@ int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_info( Xilinx_desc *desc ) +static int spartan3_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -100,10 +101,10 @@ int Spartan3_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -254,10 +255,10 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -302,10 +303,10 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -457,7 +458,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ @@ -465,3 +466,9 @@ static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan3_op = { + .load = spartan3_load, + .dump = spartan3_dump, + .info = spartan3_info, +}; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index b5a895d41a..0d2d9a4693 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -84,25 +84,26 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Virtex2_ss_load (desc, buf, bsize); + ret_val = virtex2_ss_load(desc, buf, bsize); break; case slave_selectmap: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Virtex2_ssm_load (desc, buf, bsize); + ret_val = virtex2_ssm_load(desc, buf, bsize); break; default: @@ -112,19 +113,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Virtex2_ss_dump (desc, buf, bsize); + ret_val = virtex2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Virtex2_ssm_dump (desc, buf, bsize); + ret_val = virtex2_ssm_dump(desc, buf, bsize); break; default: @@ -134,7 +135,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_info (Xilinx_desc * desc) +static int virtex2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,10 +154,10 @@ int Virtex2_info (Xilinx_desc * desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", __FUNCTION__, __LINE__, fn); @@ -352,10 +353,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -404,16 +405,22 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; } /* vim: set ts=4 tw=78: */ + +struct xilinx_fpga_op virtex2_op = { + .load = virtex2_load, + .dump = virtex2_dump, + .info = virtex2_info, +}; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 2e0db535d4..c765a74a25 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -19,23 +19,13 @@ #include #include -#if 0 -#define FPGA_DEBUG -#endif - -/* Define FPGA_DEBUG to get debug printf's */ -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - /* Local Static Functions */ -static int xilinx_validate (Xilinx_desc * desc, char *fn); +static int xilinx_validate(xilinx_desc *desc, char *fn); /* ------------------------------------------------------------------------- */ -int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { unsigned int length; unsigned int swapsize; @@ -43,7 +33,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) unsigned char *dataptr; unsigned int i; const fpga_desc *desc; - Xilinx_desc *xdesc; + xilinx_desc *xdesc; dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ @@ -94,7 +84,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) return FPGA_FAIL; } } else { - printf("%s: Please fill correct device ID to Xilinx_desc\n", + printf("%s: Please fill correct device ID to xilinx_desc\n", __func__); } printf(" part number = \"%s\"\n", buffer); @@ -138,137 +128,72 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) dataptr += 4; printf(" bytes in bitstream = %d\n", swapsize); - return fpga_load(devnum, dataptr, swapsize); + return fpga_load(devnum, dataptr, swapsize, bstype); } -int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { - int ret_val = FPGA_FAIL; /* assume a failure */ - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Loader...\n", - __FUNCTION__); - ret_val = Spartan2_load (desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Loader...\n", - __FUNCTION__); - ret_val = Spartan3_load (desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Loader...\n", - __FUNCTION__); - ret_val = Virtex2_load (desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Loader...\n", - __func__); - ret_val = zynq_load(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; + return FPGA_FAIL; + } - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + if (!desc->operations || !desc->operations->load) { + printf("%s: Missing load operation\n", __func__); + return FPGA_FAIL; + } - return ret_val; + return desc->operations->load(desc, buf, bsize, bstype); } -int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +#if defined(CONFIG_CMD_FPGA_LOADFS) +int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo) { - int ret_val = FPGA_FAIL; /* assume a failure */ + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); + return FPGA_FAIL; + } + + if (!desc->operations || !desc->operations->loadfs) { + printf("%s: Missing loadfs operation\n", __func__); + return FPGA_FAIL; + } + return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); +} +#endif + +int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) +{ if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Reader...\n", - __FUNCTION__); - ret_val = Spartan2_dump (desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Reader...\n", - __FUNCTION__); - ret_val = Spartan3_dump (desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Virtex2: -#if defined( CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Reader...\n", - __FUNCTION__); - ret_val = Virtex2_dump (desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Reader...\n", - __func__); - ret_val = zynq_dump(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; + return FPGA_FAIL; + } - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + if (!desc->operations || !desc->operations->dump) { + printf("%s: Missing dump operation\n", __func__); + return FPGA_FAIL; + } - return ret_val; + return desc->operations->dump(desc, buf, bsize); } -int xilinx_info (Xilinx_desc * desc) +int xilinx_info(xilinx_desc *desc) { int ret_val = FPGA_FAIL; if (xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("Family: \t"); switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: printf ("Spartan-II\n"); break; - case Xilinx_Spartan3: + case xilinx_spartan3: printf ("Spartan-III\n"); break; - case Xilinx_Virtex2: + case xilinx_virtex2: printf ("Virtex-II\n"); break; case xilinx_zynq: @@ -307,58 +232,20 @@ int xilinx_info (Xilinx_desc * desc) printf ("Unsupported interface type, %d\n", desc->iface); } - printf ("Device Size: \t%d bytes\n" - "Cookie: \t0x%x (%d)\n", - desc->size, desc->cookie, desc->cookie); + printf("Device Size: \t%zd bytes\n" + "Cookie: \t0x%x (%d)\n", + desc->size, desc->cookie, desc->cookie); if (desc->name) printf("Device name: \t%s\n", desc->name); - if (desc->iface_fns) { + if (desc->iface_fns) printf ("Device Function Table @ 0x%p\n", desc->iface_fns); - switch (desc->family) { - case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - Spartan2_info (desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - Spartan3_info (desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - Virtex2_info (desc); -#else - /* just in case */ - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - zynq_info(desc); -#else - /* just in case */ - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - /* Add new family types here */ - default: - /* we don't need a message here - we give one up above */ - ; - } - } else + else printf ("No Device Function Table.\n"); + if (desc->operations && desc->operations->info) + desc->operations->info(desc); + ret_val = FPGA_SUCCESS; } else { printf ("%s: Invalid device descriptor\n", __FUNCTION__); @@ -369,7 +256,7 @@ int xilinx_info (Xilinx_desc * desc) /* ------------------------------------------------------------------------- */ -static int xilinx_validate (Xilinx_desc * desc, char *fn) +static int xilinx_validate(xilinx_desc *desc, char *fn) { int ret_val = false; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 8cc16fd2c2..6a74f89610 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -4,12 +4,14 @@ * (C) Copyright 2012 * Joe Hershberger * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include #include +#include #include #include @@ -23,6 +25,7 @@ #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 #define DEVCFG_STATUS_PCFG_INIT 0x00000010 +#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 @@ -31,10 +34,10 @@ #endif #ifndef CONFIG_SYS_FPGA_PROG_TIME -#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */ +#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -int zynq_info(Xilinx_desc *desc) +static int zynq_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -145,62 +148,62 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } /* Loop can be huge - support CTRL + C */ if (ctrlc()) - return 0; + return NULL; } - return 0; + return NULL; } - -int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) { - unsigned long ts; /* Timestamp */ - u32 partialbit = 0; - u32 i, control, isr_status, status, swap, diff; - u32 *buf_start; + unsigned long ts; + u32 isr_status; - /* Detect if we are going working with partial or full bitstream */ - if (bsize != desc->size) { - printf("%s: Working with partial bitstream\n", __func__); - partialbit = 1; - } - - buf_start = check_data((u8 *)buf, bsize, &swap); - if (!buf_start) - return FPGA_FAIL; + /* Set up the transfer */ + writel((u32)srcbuf, &devcfg_base->dma_src_addr); + writel(dstbuf, &devcfg_base->dma_dst_addr); + writel(srclen, &devcfg_base->dma_src_len); + writel(dstlen, &devcfg_base->dma_dst_len); - /* Check if data is postpone from start */ - diff = (u32)buf_start - (u32)buf; - if (diff) { - printf("%s: Bitstream is not validated yet (diff %x)\n", - __func__, diff); - return FPGA_FAIL; - } + isr_status = readl(&devcfg_base->int_sts); - if ((u32)buf_start & 0x3) { - u32 *new_buf = (u32 *)((u32)buf & ~0x3); + /* Polling the PCAP_INIT status for Set */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { + if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { + debug("%s: Error: isr = 0x%08X\n", __func__, + isr_status); + debug("%s: Write count = 0x%08X\n", __func__, + readl(&devcfg_base->write_count)); + debug("%s: Read count = 0x%08X\n", __func__, + readl(&devcfg_base->read_count)); - printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, - (u32)buf_start, (u32)new_buf, swap); + return FPGA_FAIL; + } + if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { + printf("%s: Timeout wait for DMA to complete\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } - for (i = 0; i < (bsize/4); i++) - new_buf[i] = load_word(&buf_start[i], swap); + debug("%s: DMA transfer is done\n", __func__); - swap = SWAP_DONE; - buf = new_buf; - } else if (swap != SWAP_DONE) { - /* For bitstream which are aligned */ - u32 *new_buf = (u32 *)buf; + /* Clear out the DMA status */ + writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); - printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, - swap); + return FPGA_SUCCESS; +} - for (i = 0; i < (bsize/4); i++) - new_buf[i] = load_word(&buf_start[i], swap); +static int zynq_dma_xfer_init(bitstream_type bstype) +{ + u32 status, control, isr_status; + unsigned long ts; - swap = SWAP_DONE; - } + /* Clear loopback bit */ + clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); - if (!partialbit) { + if (bstype != BIT_PARTIAL) { zynq_slcr_devcfg_disable(); /* Setting PCFG_PROG_B signal to high */ @@ -277,39 +280,185 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); } + return FPGA_SUCCESS; +} + +static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) +{ + u32 *new_buf; + u32 i; + + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + + /* + * This might be dangerous but permits to flash if + * ARCH_DMA_MINALIGN is greater than header size + */ + if (new_buf > buf) { + debug("%s: Aligned buffer is after buffer start\n", + __func__); + new_buf -= ARCH_DMA_MINALIGN; + } + printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, + (u32)buf, (u32)new_buf, swap); + + for (i = 0; i < (len/4); i++) + new_buf[i] = load_word(&buf[i], swap); + + buf = new_buf; + } else if (swap != SWAP_DONE) { + /* For bitstream which are aligned */ + u32 *new_buf = (u32 *)buf; + + printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, + swap); + + for (i = 0; i < (len/4); i++) + new_buf[i] = load_word(&buf[i], swap); + } + + return buf; +} + +static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, + size_t bsize, u32 blocksize, u32 *swap, + bitstream_type *bstype) +{ + u32 *buf_start; + u32 diff; + + buf_start = check_data((u8 *)buf, blocksize, swap); + + if (!buf_start) + return FPGA_FAIL; + + /* Check if data is postpone from start */ + diff = (u32)buf_start - (u32)buf; + if (diff) { + printf("%s: Bitstream is not validated yet (diff %x)\n", + __func__, diff); + return FPGA_FAIL; + } + + if ((u32)buf < SZ_1M) { + printf("%s: Bitstream has to be placed up to 1MB (%x)\n", + __func__, (u32)buf); + return FPGA_FAIL; + } + + if (zynq_dma_xfer_init(*bstype)) + return FPGA_FAIL; + + return 0; +} + +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) +{ + unsigned long ts; /* Timestamp */ + u32 isr_status, swap; + + /* + * send bsize inplace of blocksize as it was not a bitstream + * in chunks + */ + if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, + &bstype)) + return FPGA_FAIL; + + buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); + debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); - /* Set up the transfer */ - writel((u32)buf | 1, &devcfg_base->dma_src_addr); - writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); - writel(bsize >> 2, &devcfg_base->dma_src_len); - writel(0, &devcfg_base->dma_dst_len); + /* flush(clean & invalidate) d-cache range buf */ + flush_dcache_range((u32)buf, (u32)buf + + roundup(bsize, ARCH_DMA_MINALIGN)); - isr_status = readl(&devcfg_base->int_sts); + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; - /* Polling the PCAP_INIT status for Set */ + isr_status = readl(&devcfg_base->int_sts); + /* Check FPGA configuration completion */ ts = get_timer(0); - while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { - if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { - debug("%s: Error: isr = 0x%08X\n", __func__, - isr_status); - debug("%s: Write count = 0x%08X\n", __func__, - readl(&devcfg_base->write_count)); - debug("%s: Read count = 0x%08X\n", __func__, - readl(&devcfg_base->read_count)); - - return FPGA_FAIL; - } - if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { - printf("%s: Timeout wait for DMA to complete\n", + while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; } isr_status = readl(&devcfg_base->int_sts); } - debug("%s: DMA transfer is done\n", __func__); + debug("%s: FPGA config done\n", __func__); + + if (bstype != BIT_PARTIAL) + zynq_slcr_devcfg_enable(); + + return FPGA_SUCCESS; +} + +#if defined(CONFIG_CMD_FPGA_LOADFS) +static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fsinfo) +{ + unsigned long ts; /* Timestamp */ + u32 isr_status, swap; + u32 partialbit = 0; + loff_t blocksize, actread; + loff_t pos = 0; + int fstype; + char *interface, *dev_part, *filename; + + blocksize = fsinfo->blocksize; + interface = fsinfo->interface; + dev_part = fsinfo->dev_part; + filename = fsinfo->filename; + fstype = fsinfo->fstype; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0) + return FPGA_FAIL; + + if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap, + &partialbit)) + return FPGA_FAIL; + + dcache_disable(); + + do { + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2, + 0xffffffff, 0)) + return FPGA_FAIL; + + bsize -= blocksize; + pos += blocksize; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (bsize > blocksize) { + if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0) + return FPGA_FAIL; + } else { + if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0) + return FPGA_FAIL; + } + } while (bsize > blocksize); + + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; + + dcache_enable(); + + isr_status = readl(&devcfg_base->int_sts); /* Check FPGA configuration completion */ ts = get_timer(0); @@ -324,16 +473,23 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: FPGA config done\n", __func__); - /* Clear out the DMA status */ - writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); - if (!partialbit) zynq_slcr_devcfg_enable(); return FPGA_SUCCESS; } +#endif -int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; } + +struct xilinx_fpga_op zynq_op = { + .load = zynq_load, +#if defined(CONFIG_CMD_FPGA_LOADFS) + .loadfs = zynq_loadfs, +#endif + .dump = zynq_dump, + .info = zynq_info, +}; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig new file mode 100644 index 0000000000..d21302f8da --- /dev/null +++ b/drivers/gpio/Kconfig @@ -0,0 +1,6 @@ +config DM_GPIO + bool "Enable Driver Model for GPIO drivers" + depends on DM + help + If you want to use driver model for GPIO drivers, say Y. + To use legacy GPIO drivers, say N. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index be64df2253..e035a74333 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -5,53 +5,36 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libgpio.o - -COBJS-y += gpiolib.o - -COBJS-$(CONFIG_AM33XX_GPIO) += am33xx_gpio.o -COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o -COBJS-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o -COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o -COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o -COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o -COBJS-$(CONFIG_MXS_GPIO) += mxs_gpio.o -COBJS-$(CONFIG_PCA953X) += pca953x.o -COBJS-$(CONFIG_PCA9698) += pca9698.o -COBJS-$(CONFIG_S5P) += s5p_gpio.o -COBJS-$(CONFIG_SANDBOX_GPIO) += sandbox.o -COBJS-$(CONFIG_SPEAR_GPIO) += spear_gpio.o -COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o -COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o -COBJS-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o -COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o -COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o -COBJS-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o -COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o -COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o -COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o -COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o -COBJS-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o -COBJS-$(CONFIG_ADI_GPIO2) += adi_gpio2.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################## +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_DM_GPIO) += gpio-uclass.o +endif + +obj-$(CONFIG_AM33XX_GPIO) += am33xx_gpio.o +obj-$(CONFIG_AT91_GPIO) += at91_gpio.o +obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o +obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +obj-$(CONFIG_KONA_GPIO) += kona_gpio.o +obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o +obj-$(CONFIG_MARVELL_MFP) += mvmfp.o +obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o +obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o +obj-$(CONFIG_PCA953X) += pca953x.o +obj-$(CONFIG_PCA9698) += pca9698.o +obj-$(CONFIG_S5P) += s5p_gpio.o +obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o +obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o +obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o +obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o +obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o +obj-$(CONFIG_ALTERA_PIO) += altera_pio.o +obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o +obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o +obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o +obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o +obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o +obj-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o +obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o +obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o +obj-$(CONFIG_TCA642X) += tca642x.o +oby-$(CONFIG_SX151X) += sx151x.o +obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o diff --git a/drivers/gpio/adi_gpio2.c b/drivers/gpio/adi_gpio2.c index 051073cee3..88cd65b87f 100644 --- a/drivers/gpio/adi_gpio2.c +++ b/drivers/gpio/adi_gpio2.c @@ -10,22 +10,6 @@ #include #include #include -#include - -static struct gpio_port_t * const gpio_array[] = { - (struct gpio_port_t *)PORTA_FER, - (struct gpio_port_t *)PORTB_FER, - (struct gpio_port_t *)PORTC_FER, - (struct gpio_port_t *)PORTD_FER, - (struct gpio_port_t *)PORTE_FER, - (struct gpio_port_t *)PORTF_FER, - (struct gpio_port_t *)PORTG_FER, -#if defined(CONFIG_BF54x) - (struct gpio_port_t *)PORTH_FER, - (struct gpio_port_t *)PORTI_FER, - (struct gpio_port_t *)PORTJ_FER, -#endif -}; #define RESOURCE_LABEL_SIZE 16 @@ -98,7 +82,6 @@ static void port_setup(unsigned gpio, unsigned short usage) else gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio); #endif - SSYNC(); } inline void portmux_setup(unsigned short per) diff --git a/drivers/gpio/am33xx_gpio.c b/drivers/gpio/am33xx_gpio.c index de0bc475ca..4893d25440 100644 --- a/drivers/gpio/am33xx_gpio.c +++ b/drivers/gpio/am33xx_gpio.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 23229148d9..6129c020ea 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -1,5 +1,5 @@ /* - * Memory Setup stuff - taken from blob memsetup.S + * Copyright (C) 2013 Bo Shen * * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) * @@ -8,36 +8,60 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/* - * WARNING: - * - * As the code is right now, it expects all PIO ports A,B,C,... - * to be evenly spaced in the memory map: - * ATMEL_BASE_PIOA + port * sizeof at91pio_t - * This might not necessaryly be true in future Atmel SoCs. - * This code should be fixed to use a pointer array to the ports. - */ - #include #include +#include #include -#include +#include +#include #include #include +#define GPIO_PER_BANK 32 + +static struct at91_port *at91_pio_get_port(unsigned port) +{ + switch (port) { + case AT91_PIO_PORTA: + return (struct at91_port *)ATMEL_BASE_PIOA; + case AT91_PIO_PORTB: + return (struct at91_port *)ATMEL_BASE_PIOB; + case AT91_PIO_PORTC: + return (struct at91_port *)ATMEL_BASE_PIOC; +#if (ATMEL_PIO_PORTS > 3) + case AT91_PIO_PORTD: + return (struct at91_port *)ATMEL_BASE_PIOD; +#if (ATMEL_PIO_PORTS > 4) + case AT91_PIO_PORTE: + return (struct at91_port *)ATMEL_BASE_PIOE; +#endif +#endif + default: + printf("Error: at91_gpio: Fail to get PIO base!\n"); + return NULL; + } +} + +static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset, + int use_pullup) +{ + u32 mask; + + mask = 1 << offset; + if (use_pullup) + writel(mask, &at91_port->puer); + else + writel(mask, &at91_port->pudr); + writel(mask, &at91_port->per); +} + int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_pullup(at91_port, pin, use_pullup); - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { - mask = 1 << pin; - if (use_pullup) - writel(1 << pin, &pio->port[port].puer); - else - writel(1 << pin, &pio->port[port].pudr); - writel(mask, &pio->port[port].per); - } return 0; } @@ -46,15 +70,16 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) */ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; - writel(mask, &pio->port[port].idr); + writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); - writel(mask, &pio->port[port].per); + writel(mask, &at91_port->per); } + return 0; } @@ -63,23 +88,24 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; - writel(mask, &pio->port[port].idr); + writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); #if defined(CPU_HAS_PIO3) - writel(readl(&pio->port[port].abcdsr1) & ~mask, - &pio->port[port].abcdsr1); - writel(readl(&pio->port[port].abcdsr2) & ~mask, - &pio->port[port].abcdsr2); + writel(readl(&at91_port->abcdsr1) & ~mask, + &at91_port->abcdsr1); + writel(readl(&at91_port->abcdsr2) & ~mask, + &at91_port->abcdsr2); #else - writel(mask, &pio->port[port].asr); + writel(mask, &at91_port->asr); #endif - writel(mask, &pio->port[port].pdr); + writel(mask, &at91_port->pdr); } + return 0; } @@ -88,23 +114,24 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; - writel(mask, &pio->port[port].idr); + writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); #if defined(CPU_HAS_PIO3) - writel(readl(&pio->port[port].abcdsr1) | mask, - &pio->port[port].abcdsr1); - writel(readl(&pio->port[port].abcdsr2) & ~mask, - &pio->port[port].abcdsr2); + writel(readl(&at91_port->abcdsr1) | mask, + &at91_port->abcdsr1); + writel(readl(&at91_port->abcdsr2) & ~mask, + &at91_port->abcdsr2); #else - writel(mask, &pio->port[port].bsr); + writel(mask, &at91_port->bsr); #endif - writel(mask, &pio->port[port].pdr); + writel(mask, &at91_port->pdr); } + return 0; } @@ -114,19 +141,20 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; - writel(mask, &pio->port[port].idr); + writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); - writel(readl(&pio->port[port].abcdsr1) & ~mask, - &pio->port[port].abcdsr1); - writel(readl(&pio->port[port].abcdsr2) | mask, - &pio->port[port].abcdsr2); - writel(mask, &pio->port[port].pdr); + writel(readl(&at91_port->abcdsr1) & ~mask, + &at91_port->abcdsr1); + writel(readl(&at91_port->abcdsr2) | mask, + &at91_port->abcdsr2); + writel(mask, &at91_port->pdr); } + return 0; } @@ -135,62 +163,88 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; - writel(mask, &pio->port[port].idr); + writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); - writel(readl(&pio->port[port].abcdsr1) | mask, - &pio->port[port].abcdsr1); - writel(readl(&pio->port[port].abcdsr2) | mask, - &pio->port[port].abcdsr2); - writel(mask, &pio->port[port].pdr); + writel(readl(&at91_port->abcdsr1) | mask, + &at91_port->abcdsr1); + writel(readl(&at91_port->abcdsr2) | mask, + &at91_port->abcdsr2); + writel(mask, &at91_port->pdr); } + return 0; } #endif +#ifdef CONFIG_DM_GPIO +static bool at91_get_port_output(struct at91_port *at91_port, int offset) +{ + u32 mask, val; + + mask = 1 << offset; + val = readl(&at91_port->osr); + return val & mask; +} +#endif + +static void at91_set_port_input(struct at91_port *at91_port, int offset, + int use_pullup) +{ + u32 mask; + + mask = 1 << offset; + writel(mask, &at91_port->idr); + at91_set_port_pullup(at91_port, offset, use_pullup); + writel(mask, &at91_port->odr); + writel(mask, &at91_port->per); +} + /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. */ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_input(at91_port, pin, use_pullup); - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { - mask = 1 << pin; - writel(mask, &pio->port[port].idr); - at91_set_pio_pullup(port, pin, use_pullup); - writel(mask, &pio->port[port].odr); - writel(mask, &pio->port[port].per); - } return 0; } +static void at91_set_port_output(struct at91_port *at91_port, int offset, + int value) +{ + u32 mask; + + mask = 1 << offset; + writel(mask, &at91_port->idr); + writel(mask, &at91_port->pudr); + if (value) + writel(mask, &at91_port->sodr); + else + writel(mask, &at91_port->codr); + writel(mask, &at91_port->oer); + writel(mask, &at91_port->per); +} + /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), * and configure it for an output. */ int at91_set_pio_output(unsigned port, u32 pin, int value) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_output(at91_port, pin, value); - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { - mask = 1 << pin; - writel(mask, &pio->port[port].idr); - writel(mask, &pio->port[port].pudr); - if (value) - writel(mask, &pio->port[port].sodr); - else - writel(mask, &pio->port[port].codr); - writel(mask, &pio->port[port].oer); - writel(mask, &pio->port[port].per); - } return 0; } @@ -199,20 +253,21 @@ int at91_set_pio_output(unsigned port, u32 pin, int value) */ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; if (is_on) { #if defined(CPU_HAS_PIO3) - writel(mask, &pio->port[port].ifscdr); + writel(mask, &at91_port->ifscdr); #endif - writel(mask, &pio->port[port].ifer); + writel(mask, &at91_port->ifer); } else { - writel(mask, &pio->port[port].ifdr); + writel(mask, &at91_port->ifdr); } } + return 0; } @@ -222,19 +277,20 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) */ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; if (is_on) { - writel(mask, &pio->port[port].ifscer); - writel(div & PIO_SCDR_DIV, &pio->port[port].scdr); - writel(mask, &pio->port[port].ifer); + writel(mask, &at91_port->ifscer); + writel(div & PIO_SCDR_DIV, &at91_port->scdr); + writel(mask, &at91_port->ifer); } else { - writel(mask, &pio->port[port].ifdr); + writel(mask, &at91_port->ifdr); } } + return 0; } @@ -244,17 +300,18 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) */ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; - writel(mask, &pio->port[port].pudr); + writel(mask, &at91_port->pudr); if (is_on) - writel(mask, &pio->port[port].ppder); + writel(mask, &at91_port->ppder); else - writel(mask, &pio->port[port].ppddr); + writel(mask, &at91_port->ppddr); } + return 0; } @@ -263,14 +320,15 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) */ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; - writel(readl(&pio->port[port].schmitt) | mask, - &pio->port[port].schmitt); + writel(readl(&at91_port->schmitt) | mask, + &at91_port->schmitt); } + return 0; } #endif @@ -281,49 +339,192 @@ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) */ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; if (is_on) - writel(mask, &pio->port[port].mder); + writel(mask, &at91_port->mder); else - writel(mask, &pio->port[port].mddr); + writel(mask, &at91_port->mddr); } + return 0; } +static void at91_set_port_value(struct at91_port *at91_port, int offset, + int value) +{ + u32 mask; + + mask = 1 << offset; + if (value) + writel(mask, &at91_port->sodr); + else + writel(mask, &at91_port->codr); +} + /* * assuming the pin is muxed as a gpio output, set its value. */ int at91_set_pio_value(unsigned port, unsigned pin, int value) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); + + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_value(at91_port, pin, value); - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { - mask = 1 << pin; - if (value) - writel(mask, &pio->port[port].sodr); - else - writel(mask, &pio->port[port].codr); - } return 0; } +static int at91_get_port_value(struct at91_port *at91_port, int offset) +{ + u32 pdsr = 0, mask; + + mask = 1 << offset; + pdsr = readl(&at91_port->pdsr) & mask; + + return pdsr != 0; +} /* * read the pin's value (works even if it's not muxed as a gpio). */ int at91_get_pio_value(unsigned port, unsigned pin) { - u32 pdsr = 0; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; - u32 mask; + struct at91_port *at91_port = at91_pio_get_port(port); - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { - mask = 1 << pin; - pdsr = readl(&pio->port[port].pdsr) & mask; - } - return pdsr != 0; + if (at91_port && (pin < GPIO_PER_BANK)) + return at91_get_port_value(at91_port, pin); + + return 0; +} + +#ifndef CONFIG_DM_GPIO +/* Common GPIO API */ + +int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + at91_set_pio_input(at91_gpio_to_port(gpio), + at91_gpio_to_pin(gpio), 0); + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + at91_set_pio_output(at91_gpio_to_port(gpio), + at91_gpio_to_pin(gpio), value); + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + return at91_get_pio_value(at91_gpio_to_port(gpio), + at91_gpio_to_pin(gpio)); +} + +int gpio_set_value(unsigned gpio, int value) +{ + at91_set_pio_value(at91_gpio_to_port(gpio), + at91_gpio_to_pin(gpio), value); + + return 0; +} +#endif + +#ifdef CONFIG_DM_GPIO + +struct at91_port_priv { + struct at91_port *regs; +}; + +/* set GPIO pin 'gpio' as an input */ +static int at91_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + at91_set_port_input(port->regs, offset, 0); + + return 0; +} + +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +static int at91_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + at91_set_port_output(port->regs, offset, value); + + return 0; +} + +/* read GPIO IN value of pin 'gpio' */ +static int at91_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + return at91_get_port_value(port->regs, offset); +} + +/* write GPIO OUT value to pin 'gpio' */ +static int at91_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + at91_set_port_value(port->regs, offset, value); + + return 0; +} + +static int at91_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + /* GPIOF_FUNC is not implemented yet */ + if (at91_get_port_output(port->regs, offset)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops gpio_at91_ops = { + .direction_input = at91_gpio_direction_input, + .direction_output = at91_gpio_direction_output, + .get_value = at91_gpio_get_value, + .set_value = at91_gpio_set_value, + .get_function = at91_gpio_get_function, +}; + +static int at91_gpio_probe(struct udevice *dev) +{ + struct at91_port_priv *port = dev_get_priv(dev); + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + uc_priv->bank_name = plat->bank_name; + uc_priv->gpio_count = GPIO_PER_BANK; + port->regs = (struct at91_port *)plat->base_addr; + + return 0; } + +U_BOOT_DRIVER(gpio_at91) = { + .name = "gpio_at91", + .id = UCLASS_GPIO, + .ops = &gpio_at91_ops, + .probe = at91_gpio_probe, + .priv_auto_alloc_size = sizeof(struct at91_port_priv), +}; +#endif diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c index 97b5137114..0244c01882 100644 --- a/drivers/gpio/bcm2835_gpio.c +++ b/drivers/gpio/bcm2835_gpio.c @@ -6,73 +6,118 @@ */ #include +#include +#include #include #include -inline int gpio_is_valid(unsigned gpio) -{ - return (gpio < BCM2835_GPIO_COUNT); -} - -int gpio_request(unsigned gpio, const char *label) -{ - return !gpio_is_valid(gpio); -} +struct bcm2835_gpios { + struct bcm2835_gpio_regs *reg; +}; -int gpio_free(unsigned gpio) +static int bcm2835_gpio_direction_input(struct udevice *dev, unsigned gpio) { - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - struct bcm2835_gpio_regs *reg = - (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE; + struct bcm2835_gpios *gpios = dev_get_priv(dev); unsigned val; - val = readl(®->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); + val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio)); val |= (BCM2835_GPIO_INPUT << BCM2835_GPIO_FSEL_SHIFT(gpio)); - writel(val, ®->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); + writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); return 0; } -int gpio_direction_output(unsigned gpio, int value) +static int bcm2835_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) { - struct bcm2835_gpio_regs *reg = - (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE; + struct bcm2835_gpios *gpios = dev_get_priv(dev); unsigned val; gpio_set_value(gpio, value); - val = readl(®->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); + val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio)); val |= (BCM2835_GPIO_OUTPUT << BCM2835_GPIO_FSEL_SHIFT(gpio)); - writel(val, ®->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); + writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); return 0; } -int gpio_get_value(unsigned gpio) +static bool bcm2835_gpio_is_output(const struct bcm2835_gpios *gpios, int gpio) +{ + u32 val; + + val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]); + val &= BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio); + return val ? true : false; +} + +static int bcm2835_get_value(const struct bcm2835_gpios *gpios, unsigned gpio) { - struct bcm2835_gpio_regs *reg = - (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE; unsigned val; - val = readl(®->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]); + val = readl(&gpios->reg->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]); return (val >> BCM2835_GPIO_COMMON_SHIFT(gpio)) & 0x1; } -int gpio_set_value(unsigned gpio, int value) +static int bcm2835_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + const struct bcm2835_gpios *gpios = dev_get_priv(dev); + + return bcm2835_get_value(gpios, gpio); +} + +static int bcm2835_gpio_set_value(struct udevice *dev, unsigned gpio, + int value) { - struct bcm2835_gpio_regs *reg = - (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE; - u32 *output_reg = value ? reg->gpset : reg->gpclr; + struct bcm2835_gpios *gpios = dev_get_priv(dev); + u32 *output_reg = value ? gpios->reg->gpset : gpios->reg->gpclr; writel(1 << BCM2835_GPIO_COMMON_SHIFT(gpio), &output_reg[BCM2835_GPIO_COMMON_BANK(gpio)]); return 0; } + +static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct bcm2835_gpios *gpios = dev_get_priv(dev); + + /* GPIOF_FUNC is not implemented yet */ + if (bcm2835_gpio_is_output(gpios, offset)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + + +static const struct dm_gpio_ops gpio_bcm2835_ops = { + .direction_input = bcm2835_gpio_direction_input, + .direction_output = bcm2835_gpio_direction_output, + .get_value = bcm2835_gpio_get_value, + .set_value = bcm2835_gpio_set_value, + .get_function = bcm2835_gpio_get_function, +}; + +static int bcm2835_gpio_probe(struct udevice *dev) +{ + struct bcm2835_gpios *gpios = dev_get_priv(dev); + struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + uc_priv->bank_name = "GPIO"; + uc_priv->gpio_count = BCM2835_GPIO_COUNT; + gpios->reg = (struct bcm2835_gpio_regs *)plat->base; + + return 0; +} + +U_BOOT_DRIVER(gpio_bcm2835) = { + .name = "gpio_bcm2835", + .id = UCLASS_GPIO, + .ops = &gpio_bcm2835_ops, + .probe = bcm2835_gpio_probe, + .priv_auto_alloc_size = sizeof(struct bcm2835_gpios), +}; diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c new file mode 100644 index 0000000000..a69bbd2002 --- /dev/null +++ b/drivers/gpio/gpio-uclass.c @@ -0,0 +1,723 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * gpio_to_device() - Convert global GPIO number to device, number + * + * Convert the GPIO number to an entry in the list of GPIOs + * or GPIO blocks registered with the GPIO controller. Returns + * entry on success, NULL on error. + * + * @gpio: The numeric representation of the GPIO + * @desc: Returns description (desc->flags will always be 0) + * @return 0 if found, -ENOENT if not found + */ +static int gpio_to_device(unsigned int gpio, struct gpio_desc *desc) +{ + struct gpio_dev_priv *uc_priv; + struct udevice *dev; + int ret; + + for (ret = uclass_first_device(UCLASS_GPIO, &dev); + dev; + ret = uclass_next_device(&dev)) { + uc_priv = dev->uclass_priv; + if (gpio >= uc_priv->gpio_base && + gpio < uc_priv->gpio_base + uc_priv->gpio_count) { + desc->dev = dev; + desc->offset = gpio - uc_priv->gpio_base; + desc->flags = 0; + return 0; + } + } + + /* No such GPIO */ + return ret ? ret : -ENOENT; +} + +int gpio_lookup_name(const char *name, struct udevice **devp, + unsigned int *offsetp, unsigned int *gpiop) +{ + struct gpio_dev_priv *uc_priv = NULL; + struct udevice *dev; + ulong offset; + int numeric; + int ret; + + if (devp) + *devp = NULL; + numeric = isdigit(*name) ? simple_strtoul(name, NULL, 10) : -1; + for (ret = uclass_first_device(UCLASS_GPIO, &dev); + dev; + ret = uclass_next_device(&dev)) { + int len; + + uc_priv = dev->uclass_priv; + if (numeric != -1) { + offset = numeric - uc_priv->gpio_base; + /* Allow GPIOs to be numbered from 0 */ + if (offset >= 0 && offset < uc_priv->gpio_count) + break; + } + + len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0; + + if (!strncasecmp(name, uc_priv->bank_name, len)) { + if (!strict_strtoul(name + len, 10, &offset)) + break; + } + } + + if (!dev) + return ret ? ret : -EINVAL; + + if (devp) + *devp = dev; + if (offsetp) + *offsetp = offset; + if (gpiop) + *gpiop = uc_priv->gpio_base + offset; + + return 0; +} + +static int gpio_find_and_xlate(struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + struct dm_gpio_ops *ops = gpio_get_ops(desc->dev); + + /* Use the first argument as the offset by default */ + if (args->args_count > 0) + desc->offset = args->args[0]; + else + desc->offset = -1; + desc->flags = 0; + + return ops->xlate ? ops->xlate(desc->dev, desc, args) : 0; +} + +static int dm_gpio_request(struct gpio_desc *desc, const char *label) +{ + struct udevice *dev = desc->dev; + struct gpio_dev_priv *uc_priv; + char *str; + int ret; + + uc_priv = dev->uclass_priv; + if (uc_priv->name[desc->offset]) + return -EBUSY; + str = strdup(label); + if (!str) + return -ENOMEM; + if (gpio_get_ops(dev)->request) { + ret = gpio_get_ops(dev)->request(dev, desc->offset, label); + if (ret) { + free(str); + return ret; + } + } + uc_priv->name[desc->offset] = str; + + return 0; +} + +static int dm_gpio_requestf(struct gpio_desc *desc, const char *fmt, ...) +{ + va_list args; + char buf[40]; + + va_start(args, fmt); + vscnprintf(buf, sizeof(buf), fmt, args); + va_end(args); + return dm_gpio_request(desc, buf); +} + +/** + * gpio_request() - [COMPAT] Request GPIO + * gpio: GPIO number + * label: Name for the requested GPIO + * + * The label is copied and allocated so the caller does not need to keep + * the pointer around. + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_request(unsigned gpio, const char *label) +{ + struct gpio_desc desc; + int ret; + + ret = gpio_to_device(gpio, &desc); + if (ret) + return ret; + + return dm_gpio_request(&desc, label); +} + +/** + * gpio_requestf() - [COMPAT] Request GPIO + * @gpio: GPIO number + * @fmt: Format string for the requested GPIO + * @...: Arguments for the printf() format string + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_requestf(unsigned gpio, const char *fmt, ...) +{ + va_list args; + char buf[40]; + + va_start(args, fmt); + vscnprintf(buf, sizeof(buf), fmt, args); + va_end(args); + return gpio_request(gpio, buf); +} + +int _dm_gpio_free(struct udevice *dev, uint offset) +{ + struct gpio_dev_priv *uc_priv; + int ret; + + uc_priv = dev->uclass_priv; + if (!uc_priv->name[offset]) + return -ENXIO; + if (gpio_get_ops(dev)->free) { + ret = gpio_get_ops(dev)->free(dev, offset); + if (ret) + return ret; + } + + free(uc_priv->name[offset]); + uc_priv->name[offset] = NULL; + + return 0; +} + +/** + * gpio_free() - [COMPAT] Relinquish GPIO + * gpio: GPIO number + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_free(unsigned gpio) +{ + struct gpio_desc desc; + int ret; + + ret = gpio_to_device(gpio, &desc); + if (ret) + return ret; + + return _dm_gpio_free(desc.dev, desc.offset); +} + +static int check_reserved(struct gpio_desc *desc, const char *func) +{ + struct gpio_dev_priv *uc_priv = desc->dev->uclass_priv; + + if (!uc_priv->name[desc->offset]) { + printf("%s: %s: error: gpio %s%d not reserved\n", + desc->dev->name, func, + uc_priv->bank_name ? uc_priv->bank_name : "", + desc->offset); + return -EBUSY; + } + + return 0; +} + +/** + * gpio_direction_input() - [COMPAT] Set GPIO direction to input + * gpio: GPIO number + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_direction_input(unsigned gpio) +{ + struct gpio_desc desc; + int ret; + + ret = gpio_to_device(gpio, &desc); + if (ret) + return ret; + ret = check_reserved(&desc, "dir_input"); + if (ret) + return ret; + + return gpio_get_ops(desc.dev)->direction_input(desc.dev, desc.offset); +} + +/** + * gpio_direction_output() - [COMPAT] Set GPIO direction to output and set value + * gpio: GPIO number + * value: Logical value to be set on the GPIO pin + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_direction_output(unsigned gpio, int value) +{ + struct gpio_desc desc; + int ret; + + ret = gpio_to_device(gpio, &desc); + if (ret) + return ret; + ret = check_reserved(&desc, "dir_output"); + if (ret) + return ret; + + return gpio_get_ops(desc.dev)->direction_output(desc.dev, + desc.offset, value); +} + +int dm_gpio_get_value(struct gpio_desc *desc) +{ + int value; + int ret; + + ret = check_reserved(desc, "get_value"); + if (ret) + return ret; + + value = gpio_get_ops(desc->dev)->get_value(desc->dev, desc->offset); + + return desc->flags & GPIOD_ACTIVE_LOW ? !value : value; +} + +int dm_gpio_set_value(struct gpio_desc *desc, int value) +{ + int ret; + + ret = check_reserved(desc, "set_value"); + if (ret) + return ret; + + if (desc->flags & GPIOD_ACTIVE_LOW) + value = !value; + gpio_get_ops(desc->dev)->set_value(desc->dev, desc->offset, value); + return 0; +} + +int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags) +{ + struct udevice *dev = desc->dev; + struct dm_gpio_ops *ops = gpio_get_ops(dev); + int ret; + + ret = check_reserved(desc, "set_dir"); + if (ret) + return ret; + + if (flags & GPIOD_IS_OUT) { + int value = flags & GPIOD_IS_OUT_ACTIVE ? 1 : 0; + + if (flags & GPIOD_ACTIVE_LOW) + value = !value; + ret = ops->direction_output(dev, desc->offset, value); + } else if (flags & GPIOD_IS_IN) { + ret = ops->direction_input(dev, desc->offset); + } + if (ret) + return ret; + /* + * Update desc->flags here, so that GPIO_ACTIVE_LOW is honoured in + * futures + */ + desc->flags = flags; + + return 0; +} + +int dm_gpio_set_dir(struct gpio_desc *desc) +{ + return dm_gpio_set_dir_flags(desc, desc->flags); +} + +/** + * gpio_get_value() - [COMPAT] Sample GPIO pin and return it's value + * gpio: GPIO number + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns the value of the GPIO pin, or negative value + * on error. + */ +int gpio_get_value(unsigned gpio) +{ + int ret; + + struct gpio_desc desc; + + ret = gpio_to_device(gpio, &desc); + if (ret) + return ret; + return dm_gpio_get_value(&desc); +} + +/** + * gpio_set_value() - [COMPAT] Configure logical value on GPIO pin + * gpio: GPIO number + * value: Logical value to be set on the GPIO pin. + * + * This function implements the API that's compatible with current + * GPIO API used in U-Boot. The request is forwarded to particular + * GPIO driver. Returns 0 on success, negative value on error. + */ +int gpio_set_value(unsigned gpio, int value) +{ + struct gpio_desc desc; + int ret; + + ret = gpio_to_device(gpio, &desc); + if (ret) + return ret; + return dm_gpio_set_value(&desc, value); +} + +const char *gpio_get_bank_info(struct udevice *dev, int *bit_count) +{ + struct gpio_dev_priv *priv; + + /* Must be called on an active device */ + priv = dev->uclass_priv; + assert(priv); + + *bit_count = priv->gpio_count; + return priv->bank_name; +} + +static const char * const gpio_function[GPIOF_COUNT] = { + "input", + "output", + "unused", + "unknown", + "func", +}; + +int get_function(struct udevice *dev, int offset, bool skip_unused, + const char **namep) +{ + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct dm_gpio_ops *ops = gpio_get_ops(dev); + + BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function)); + if (!device_active(dev)) + return -ENODEV; + if (offset < 0 || offset >= uc_priv->gpio_count) + return -EINVAL; + if (namep) + *namep = uc_priv->name[offset]; + if (skip_unused && !uc_priv->name[offset]) + return GPIOF_UNUSED; + if (ops->get_function) { + int ret; + + ret = ops->get_function(dev, offset); + if (ret < 0) + return ret; + if (ret >= ARRAY_SIZE(gpio_function)) + return -ENODATA; + return ret; + } + + return GPIOF_UNKNOWN; +} + +int gpio_get_function(struct udevice *dev, int offset, const char **namep) +{ + return get_function(dev, offset, true, namep); +} + +int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep) +{ + return get_function(dev, offset, false, namep); +} + +int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize) +{ + struct dm_gpio_ops *ops = gpio_get_ops(dev); + struct gpio_dev_priv *priv; + char *str = buf; + int func; + int ret; + int len; + + BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function)); + + *buf = 0; + priv = dev->uclass_priv; + ret = gpio_get_raw_function(dev, offset, NULL); + if (ret < 0) + return ret; + func = ret; + len = snprintf(str, buffsize, "%s%d: %s", + priv->bank_name ? priv->bank_name : "", + offset, gpio_function[func]); + if (func == GPIOF_INPUT || func == GPIOF_OUTPUT || + func == GPIOF_UNUSED) { + const char *label; + bool used; + + ret = ops->get_value(dev, offset); + if (ret < 0) + return ret; + used = gpio_get_function(dev, offset, &label) != GPIOF_UNUSED; + snprintf(str + len, buffsize - len, ": %d [%c]%s%s", + ret, + used ? 'x' : ' ', + used ? " " : "", + label ? label : ""); + } + + return 0; +} + +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned gpio_get_values_as_int(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + if (gpio_get_value(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} + +static int _gpio_request_by_name_nodev(const void *blob, int node, + const char *list_name, int index, + struct gpio_desc *desc, int flags, + bool add_index) +{ + struct fdtdec_phandle_args args; + int ret; + + desc->dev = NULL; + desc->offset = 0; + ret = fdtdec_parse_phandle_with_args(blob, node, list_name, + "#gpio-cells", 0, index, &args); + if (ret) { + debug("%s: fdtdec_parse_phandle_with_args failed\n", __func__); + goto err; + } + + ret = uclass_get_device_by_of_offset(UCLASS_GPIO, args.node, + &desc->dev); + if (ret) { + debug("%s: uclass_get_device_by_of_offset failed\n", __func__); + goto err; + } + ret = gpio_find_and_xlate(desc, &args); + if (ret) { + debug("%s: gpio_find_and_xlate failed\n", __func__); + goto err; + } + ret = dm_gpio_requestf(desc, add_index ? "%s.%s%d" : "%s.%s", + fdt_get_name(blob, node, NULL), + list_name, index); + if (ret) { + debug("%s: dm_gpio_requestf failed\n", __func__); + goto err; + } + ret = dm_gpio_set_dir_flags(desc, flags | desc->flags); + if (ret) { + debug("%s: dm_gpio_set_dir failed\n", __func__); + goto err; + } + + return 0; +err: + debug("%s: Node '%s', property '%s', failed to request GPIO index %d: %d\n", + __func__, fdt_get_name(blob, node, NULL), list_name, index, ret); + return ret; +} + +int gpio_request_by_name_nodev(const void *blob, int node, + const char *list_name, int index, + struct gpio_desc *desc, int flags) +{ + return _gpio_request_by_name_nodev(blob, node, list_name, index, desc, + flags, index > 0); +} + +int gpio_request_by_name(struct udevice *dev, const char *list_name, int index, + struct gpio_desc *desc, int flags) +{ + /* + * This isn't ideal since we don't use dev->name in the debug() + * calls in gpio_request_by_name(), but we can do this until + * gpio_request_by_name_nodev() can be dropped. + */ + return gpio_request_by_name_nodev(gd->fdt_blob, dev->of_offset, + list_name, index, desc, flags); +} + +int gpio_request_list_by_name_nodev(const void *blob, int node, + const char *list_name, + struct gpio_desc *desc, int max_count, + int flags) +{ + int count; + int ret; + + for (count = 0; ; count++) { + if (count >= max_count) { + ret = -ENOSPC; + goto err; + } + ret = _gpio_request_by_name_nodev(blob, node, list_name, count, + &desc[count], flags, true); + if (ret == -ENOENT) + break; + else if (ret) + goto err; + } + + /* We ran out of GPIOs in the list */ + return count; + +err: + gpio_free_list_nodev(desc, count - 1); + + return ret; +} + +int gpio_request_list_by_name(struct udevice *dev, const char *list_name, + struct gpio_desc *desc, int max_count, + int flags) +{ + /* + * This isn't ideal since we don't use dev->name in the debug() + * calls in gpio_request_by_name(), but we can do this until + * gpio_request_list_by_name_nodev() can be dropped. + */ + return gpio_request_list_by_name_nodev(gd->fdt_blob, dev->of_offset, + list_name, desc, max_count, + flags); +} + +int gpio_get_list_count(struct udevice *dev, const char *list_name) +{ + int ret; + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset, + list_name, "#gpio-cells", 0, -1, + NULL); + if (ret) { + debug("%s: Node '%s', property '%s', GPIO count failed: %d\n", + __func__, dev->name, list_name, ret); + } + + return ret; +} + +int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc) +{ + /* For now, we don't do any checking of dev */ + return _dm_gpio_free(desc->dev, desc->offset); +} + +int gpio_free_list(struct udevice *dev, struct gpio_desc *desc, int count) +{ + int i; + + /* For now, we don't do any checking of dev */ + for (i = 0; i < count; i++) + dm_gpio_free(dev, &desc[i]); + + return 0; +} + +int gpio_free_list_nodev(struct gpio_desc *desc, int count) +{ + return gpio_free_list(NULL, desc, count); +} + +/* We need to renumber the GPIOs when any driver is probed/removed */ +static int gpio_renumber(struct udevice *removed_dev) +{ + struct gpio_dev_priv *uc_priv; + struct udevice *dev; + struct uclass *uc; + unsigned base; + int ret; + + ret = uclass_get(UCLASS_GPIO, &uc); + if (ret) + return ret; + + /* Ensure that we have a base for each bank */ + base = 0; + uclass_foreach_dev(dev, uc) { + if (device_active(dev) && dev != removed_dev) { + uc_priv = dev->uclass_priv; + uc_priv->gpio_base = base; + base += uc_priv->gpio_count; + } + } + + return 0; +} + +static int gpio_post_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + uc_priv->name = calloc(uc_priv->gpio_count, sizeof(char *)); + if (!uc_priv->name) + return -ENOMEM; + + return gpio_renumber(NULL); +} + +static int gpio_pre_remove(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + int i; + + for (i = 0; i < uc_priv->gpio_count; i++) { + if (uc_priv->name[i]) + free(uc_priv->name[i]); + } + free(uc_priv->name); + + return gpio_renumber(dev); +} + +UCLASS_DRIVER(gpio) = { + .id = UCLASS_GPIO, + .name = "gpio", + .post_probe = gpio_post_probe, + .pre_remove = gpio_pre_remove, + .per_device_auto_alloc_size = sizeof(struct gpio_dev_priv), +}; diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c deleted file mode 100644 index ef314eefe9..0000000000 --- a/drivers/gpio/gpiolib.c +++ /dev/null @@ -1,55 +0,0 @@ -#include -#include - -int gpio_request_one(unsigned int gpio, enum gpio_flags flags, - const char *label) -{ - int ret; - - ret = gpio_request(gpio, label); - if (ret) - return ret; - - if (flags == GPIOF_INPUT) - gpio_direction_input(gpio); - else if (flags == GPIOF_OUTPUT_INIT_LOW) - gpio_direction_output(gpio, 0); - else if (flags == GPIOF_OUTPUT_INIT_HIGH) - gpio_direction_output(gpio, 1); - - return ret; -} - -int gpio_request_array(const struct gpio *gpios, int count) -{ - int ret; - int i; - - for (i = 0; i < count; i++) { - ret = gpio_request_one(gpios[i].gpio, gpios[i].flags, - gpios[i].label); - if (ret) { - printf("Failed to request GPIO%d (%u of %u): %d\n", - gpios[i].gpio, i, count, ret); - goto error; - } - } - return 0; - -error: - while (--i >= 0) - gpio_free(gpios[i].gpio); - - return ret; -} - -int gpio_free_array(const struct gpio *gpios, int count) -{ - int ret = 0; - int i; - - for (i = 0; i < count; i++) - ret |= gpio_free(gpios[i].gpio); - - return ret; -} diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 7d9fac7233..7720cc3dad 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -27,88 +27,50 @@ */ #include +#include +#include +#include #include #include #include +#include -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 +#define GPIO_PER_BANK 32 -#define NUM_BANKS 3 - -/* Within the I/O space, where are the registers to control the GPIOs? */ -static struct { - u8 use_sel; - u8 io_sel; - u8 lvl; -} gpio_bank[NUM_BANKS] = { - { 0x00, 0x04, 0x0c }, /* Bank 0 */ - { 0x30, 0x34, 0x38 }, /* Bank 1 */ - { 0x40, 0x44, 0x48 } /* Bank 2 */ +struct ich6_bank_priv { + /* These are I/O addresses */ + uint16_t use_sel; + uint16_t io_sel; + uint16_t lvl; }; -static pci_dev_t dev; /* handle for 0:1f:0 */ -static u32 gpiobase; /* offset into I/O space */ -static int found_it_once; /* valid GPIO device? */ -static u32 lock[NUM_BANKS]; /* "lock" for access to pins */ - -static int bad_arg(int num, int *bank, int *bitnum) -{ - int i = num / 32; - int j = num % 32; - - if (num < 0 || i > NUM_BANKS) { - debug("%s: bogus gpio num: %d\n", __func__, num); - return -1; - } - *bank = i; - *bitnum = j; - return 0; -} - -static int mark_gpio(int bank, int bitnum) +/* TODO: Move this to device tree, or platform data */ +void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) { - if (lock[bank] & (1UL << bitnum)) { - debug("%s: %d.%d already marked\n", __func__, bank, bitnum); - return -1; - } - lock[bank] |= (1 << bitnum); - return 0; + gd->arch.gpio_map = map; } -static void clear_gpio(int bank, int bitnum) -{ - lock[bank] &= ~(1 << bitnum); -} - -static int notmine(int num, int *bank, int *bitnum) -{ - if (bad_arg(num, bank, bitnum)) - return -1; - return !(lock[*bank] & (1UL << *bitnum)); -} - -static int gpio_init(void) +static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) { + struct ich6_bank_platdata *plat = dev_get_platdata(dev); + pci_dev_t pci_dev; /* handle for 0:1f:0 */ u8 tmpbyte; u16 tmpword; u32 tmplong; - - /* Have we already done this? */ - if (found_it_once) - return 0; + u16 gpiobase; + int offset; /* Where should it be? */ - dev = PCI_BDF(0, 0x1f, 0); + pci_dev = PCI_BDF(0, 0x1f, 0); /* Is the device present? */ - pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID); if (tmpword != PCI_VENDOR_ID_INTEL) { debug("%s: wrong VendorID\n", __func__); - return -1; + return -ENODEV; } - pci_read_config_word(dev, PCI_DEVICE_ID, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID); debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); /* * We'd like to validate the Device ID too, but pretty much any @@ -118,49 +80,53 @@ static int gpio_init(void) */ /* I/O should already be enabled (it's a RO bit). */ - pci_read_config_word(dev, PCI_COMMAND, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_COMMAND); if (!(tmpword & PCI_COMMAND_IO)) { debug("%s: device IO not enabled\n", __func__); - return -1; + return -ENODEV; } /* Header Type must be normal (bits 6-0 only; see spec.) */ - pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE); if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { debug("%s: invalid Header type\n", __func__); - return -1; + return -ENODEV; } /* Base Class must be a bridge device */ - pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE); if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { debug("%s: invalid class\n", __func__); - return -1; + return -ENODEV; } /* Sub Class must be ISA */ - pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { debug("%s: invalid subclass\n", __func__); - return -1; + return -ENODEV; } /* Programming Interface must be 0x00 (no others exist) */ - pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG); if (tmpbyte != 0x00) { debug("%s: invalid interface type\n", __func__); - return -1; + return -ENODEV; } /* * GPIOBASE moved to its current offset with ICH6, but prior to * that it was unused (or undocumented). Check that it looks - * okay: not all ones or zeros, and mapped to I/O space (bit 0). + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. */ - pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong); - if (tmplong == 0x00000000 || tmplong == 0xffffffff || - !(tmplong & 0x00000001)) { + tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); + if (tmplong == 0x00000000 || tmplong == 0xffffffff) { debug("%s: unexpected GPIOBASE value\n", __func__); - return -1; + return -ENODEV; } /* @@ -169,106 +135,146 @@ static int gpio_init(void) * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ - gpiobase = tmplong & 0xfffffffe; + gpiobase = tmplong & 0xfffe; + offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); + if (offset == -1) { + debug("%s: Invalid register offset %d\n", __func__, offset); + return -EINVAL; + } + plat->base_addr = gpiobase + offset; + plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, + "bank-name", NULL); - /* Finally. These are the droids we're looking for. */ - found_it_once = 1; return 0; } -int gpio_request(unsigned num, const char *label /* UNUSED */) +static int ich6_gpio_probe(struct udevice *dev) { - u32 tmplong; - int i = 0, j = 0; + struct ich6_bank_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct ich6_bank_priv *bank = dev_get_priv(dev); + + if (gd->arch.gpio_map) { + setup_pch_gpios(plat->base_addr, gd->arch.gpio_map); + gd->arch.gpio_map = NULL; + } - /* Is the hardware ready? */ - if (gpio_init()) - return -1; + uc_priv->gpio_count = GPIO_PER_BANK; + uc_priv->bank_name = plat->bank_name; + bank->use_sel = plat->base_addr; + bank->io_sel = plat->base_addr + 4; + bank->lvl = plat->base_addr + 8; + + return 0; +} - if (bad_arg(num, &i, &j)) - return -1; +static int ich6_gpio_request(struct udevice *dev, unsigned offset, + const char *label) +{ + struct ich6_bank_priv *bank = dev_get_priv(dev); + u32 tmplong; /* * Make sure that the GPIO pin we want isn't already in use for some * built-in hardware function. We have to check this for every * requested pin. */ - tmplong = inl(gpiobase + gpio_bank[i].use_sel); - if (!(tmplong & (1UL << j))) { + tmplong = inl(bank->use_sel); + if (!(tmplong & (1UL << offset))) { debug("%s: gpio %d is reserved for internal use\n", __func__, - num); - return -1; + offset); + return -EPERM; } - return mark_gpio(i, j); -} - -int gpio_free(unsigned num) -{ - int i = 0, j = 0; - - if (notmine(num, &i, &j)) - return -1; - - clear_gpio(i, j); return 0; } -int gpio_direction_input(unsigned num) +static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) { + struct ich6_bank_priv *bank = dev_get_priv(dev); u32 tmplong; - int i = 0, j = 0; - - if (notmine(num, &i, &j)) - return -1; - tmplong = inl(gpiobase + gpio_bank[i].io_sel); - tmplong |= (1UL << j); - outl(gpiobase + gpio_bank[i].io_sel, tmplong); + tmplong = inl(bank->io_sel); + tmplong |= (1UL << offset); + outl(bank->io_sel, tmplong); return 0; } -int gpio_direction_output(unsigned num, int value) +static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) { + struct ich6_bank_priv *bank = dev_get_priv(dev); u32 tmplong; - int i = 0, j = 0; - if (notmine(num, &i, &j)) - return -1; + gpio_set_value(offset, value); - tmplong = inl(gpiobase + gpio_bank[i].io_sel); - tmplong &= ~(1UL << j); - outl(gpiobase + gpio_bank[i].io_sel, tmplong); + tmplong = inl(bank->io_sel); + tmplong &= ~(1UL << offset); + outl(bank->io_sel, tmplong); return 0; } -int gpio_get_value(unsigned num) +static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) + { + struct ich6_bank_priv *bank = dev_get_priv(dev); u32 tmplong; - int i = 0, j = 0; int r; - if (notmine(num, &i, &j)) - return -1; - - tmplong = inl(gpiobase + gpio_bank[i].lvl); - r = (tmplong & (1UL << j)) ? 1 : 0; + tmplong = inl(bank->lvl); + r = (tmplong & (1UL << offset)) ? 1 : 0; return r; } -int gpio_set_value(unsigned num, int value) +static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, + int value) { + struct ich6_bank_priv *bank = dev_get_priv(dev); u32 tmplong; - int i = 0, j = 0; - - if (notmine(num, &i, &j)) - return -1; - tmplong = inl(gpiobase + gpio_bank[i].lvl); + tmplong = inl(bank->lvl); if (value) - tmplong |= (1UL << j); + tmplong |= (1UL << offset); else - tmplong &= ~(1UL << j); - outl(gpiobase + gpio_bank[i].lvl, tmplong); + tmplong &= ~(1UL << offset); + outl(bank->lvl, tmplong); return 0; } + +static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct ich6_bank_priv *bank = dev_get_priv(dev); + u32 mask = 1UL << offset; + + if (!(inl(bank->use_sel) & mask)) + return GPIOF_FUNC; + if (inl(bank->io_sel) & mask) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops gpio_ich6_ops = { + .request = ich6_gpio_request, + .direction_input = ich6_gpio_direction_input, + .direction_output = ich6_gpio_direction_output, + .get_value = ich6_gpio_get_value, + .set_value = ich6_gpio_set_value, + .get_function = ich6_gpio_get_function, +}; + +static const struct udevice_id intel_ich6_gpio_ids[] = { + { .compatible = "intel,ich6-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_ich6) = { + .name = "gpio_ich6", + .id = UCLASS_GPIO, + .of_match = intel_ich6_gpio_ids, + .ops = &gpio_ich6_ops, + .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata, + .probe = ich6_gpio_probe, + .priv_auto_alloc_size = sizeof(struct ich6_bank_priv), + .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata), +}; diff --git a/drivers/gpio/kona_gpio.c b/drivers/gpio/kona_gpio.c new file mode 100644 index 0000000000..65117438c5 --- /dev/null +++ b/drivers/gpio/kona_gpio.c @@ -0,0 +1,141 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define GPIO_BASE (void *)GPIO2_BASE_ADDR + +#define GPIO_PASSWD 0x00a5a501 +#define GPIO_PER_BANK 32 +#define GPIO_MAX_BANK_NUM 8 + +#define GPIO_BANK(gpio) ((gpio) >> 5) +#define GPIO_BITMASK(gpio) \ + (1UL << ((gpio) & (GPIO_PER_BANK - 1))) + +#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) +#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) +#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) +#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) +#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) +#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) +#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) +#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) +#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) + +#define GPIO_GPPWR_OFFSET 0x00000520 + +#define GPIO_GPCTR0_DBR_SHIFT 5 +#define GPIO_GPCTR0_DBR_MASK 0x000001e0 + +#define GPIO_GPCTR0_ITR_SHIFT 3 +#define GPIO_GPCTR0_ITR_MASK 0x00000018 +#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 +#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 +#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 + +#define GPIO_GPCTR0_IOTR_MASK 0x00000001 +#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 +#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 + +int gpio_request(unsigned gpio, const char *label) +{ + unsigned int value, off; + + writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); + off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); + value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio); + writel(value, GPIO_BASE + off); + + return 0; +} + +int gpio_free(unsigned gpio) +{ + unsigned int value, off; + + writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); + off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); + value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio); + writel(value, GPIO_BASE + off); + + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + u32 val; + + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= ~GPIO_GPCTR0_IOTR_MASK; + val |= GPIO_GPCTR0_IOTR_CMD_INPUT; + writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); + + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= ~GPIO_GPCTR0_IOTR_MASK; + val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; + writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); + off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); + + val = readl(GPIO_BASE + off); + val |= bitmask; + writel(val, GPIO_BASE + off); + + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + /* determine the GPIO pin direction */ + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= GPIO_GPCTR0_IOTR_MASK; + + /* read the GPIO bank status */ + off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? + GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); + val = readl(GPIO_BASE + off); + + /* return the specified bit status */ + return !!(val & bitmask); +} + +void gpio_set_value(unsigned gpio, int value) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + /* determine the GPIO pin direction */ + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= GPIO_GPCTR0_IOTR_MASK; + + /* this function only applies to output pin */ + if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) { + printf("%s: Cannot set an input pin %d\n", __func__, gpio); + return; + } + + off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); + + val = readl(GPIO_BASE + off); + val |= bitmask; + writel(val, GPIO_BASE + off); +} diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c index 0af75a84ea..43b27e3fea 100644 --- a/drivers/gpio/kw_gpio.c +++ b/drivers/gpio/kw_gpio.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)]; @@ -36,7 +36,7 @@ void __set_direction(unsigned pin, int input) u = readl(GPIO_IO_CONF(pin)); } -void __set_level(unsigned pin, int high) +static void __set_level(unsigned pin, int high) { u32 u; @@ -48,7 +48,7 @@ void __set_level(unsigned pin, int high) writel(u, GPIO_OUT(pin)); } -void __set_blinking(unsigned pin, int blink) +static void __set_blinking(unsigned pin, int blink) { u32 u; diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 65dc50df39..125f24c609 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -8,16 +8,29 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include +#include #include #include #include -#include enum mxc_gpio_direction { MXC_GPIO_DIRECTION_IN, MXC_GPIO_DIRECTION_OUT, }; +#define GPIO_PER_BANK 32 + +struct mxc_gpio_plat { + struct gpio_regs *regs; +}; + +struct mxc_bank_info { + struct gpio_regs *regs; +}; + +#ifndef CONFIG_DM_GPIO #define GPIO_TO_PORT(n) ((n) / 32) /* GPIO port description */ @@ -25,15 +38,15 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ - defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \ + defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) [3] = GPIO4_BASE_ADDR, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) [4] = GPIO5_BASE_ADDR, [5] = GPIO6_BASE_ADDR, #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) [6] = GPIO7_BASE_ADDR, #endif }; @@ -152,3 +165,176 @@ int gpio_direction_output(unsigned gpio, int value) return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT); } +#endif + +#ifdef CONFIG_DM_GPIO +static int mxc_gpio_is_output(struct gpio_regs *regs, int offset) +{ + u32 val; + + val = readl(®s->gpio_dir); + + return val & (1 << offset) ? 1 : 0; +} + +static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset, + enum mxc_gpio_direction direction) +{ + u32 l; + + l = readl(®s->gpio_dir); + + switch (direction) { + case MXC_GPIO_DIRECTION_OUT: + l |= 1 << offset; + break; + case MXC_GPIO_DIRECTION_IN: + l &= ~(1 << offset); + } + writel(l, ®s->gpio_dir); +} + +static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset, + int value) +{ + u32 l; + + l = readl(®s->gpio_dr); + if (value) + l |= 1 << offset; + else + l &= ~(1 << offset); + writel(l, ®s->gpio_dr); +} + +static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset) +{ + return (readl(®s->gpio_psr) >> offset) & 0x01; +} + +/* set GPIO pin 'gpio' as an input */ +static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct mxc_bank_info *bank = dev_get_priv(dev); + + /* Configure GPIO direction as input. */ + mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN); + + return 0; +} + +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct mxc_bank_info *bank = dev_get_priv(dev); + + /* Configure GPIO output value. */ + mxc_gpio_bank_set_value(bank->regs, offset, value); + + /* Configure GPIO direction as output. */ + mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT); + + return 0; +} + +/* read GPIO IN value of pin 'gpio' */ +static int mxc_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct mxc_bank_info *bank = dev_get_priv(dev); + + return mxc_gpio_bank_get_value(bank->regs, offset); +} + +/* write GPIO OUT value to pin 'gpio' */ +static int mxc_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct mxc_bank_info *bank = dev_get_priv(dev); + + mxc_gpio_bank_set_value(bank->regs, offset, value); + + return 0; +} + +static int mxc_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct mxc_bank_info *bank = dev_get_priv(dev); + + /* GPIOF_FUNC is not implemented yet */ + if (mxc_gpio_is_output(bank->regs, offset)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops gpio_mxc_ops = { + .direction_input = mxc_gpio_direction_input, + .direction_output = mxc_gpio_direction_output, + .get_value = mxc_gpio_get_value, + .set_value = mxc_gpio_set_value, + .get_function = mxc_gpio_get_function, +}; + +static const struct mxc_gpio_plat mxc_plat[] = { + { (struct gpio_regs *)GPIO1_BASE_ADDR }, + { (struct gpio_regs *)GPIO2_BASE_ADDR }, + { (struct gpio_regs *)GPIO3_BASE_ADDR }, +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \ + defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) + { (struct gpio_regs *)GPIO4_BASE_ADDR }, +#endif +#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) + { (struct gpio_regs *)GPIO5_BASE_ADDR }, + { (struct gpio_regs *)GPIO6_BASE_ADDR }, +#endif +#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) + { (struct gpio_regs *)GPIO7_BASE_ADDR }, +#endif +}; + +static int mxc_gpio_probe(struct udevice *dev) +{ + struct mxc_bank_info *bank = dev_get_priv(dev); + struct mxc_gpio_plat *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + int banknum; + char name[18], *str; + + banknum = plat - mxc_plat; + sprintf(name, "GPIO%d_", banknum + 1); + str = strdup(name); + if (!str) + return -ENOMEM; + uc_priv->bank_name = str; + uc_priv->gpio_count = GPIO_PER_BANK; + bank->regs = plat->regs; + + return 0; +} + +U_BOOT_DRIVER(gpio_mxc) = { + .name = "gpio_mxc", + .id = UCLASS_GPIO, + .ops = &gpio_mxc_ops, + .probe = mxc_gpio_probe, + .priv_auto_alloc_size = sizeof(struct mxc_bank_info), +}; + +U_BOOT_DEVICES(mxc_gpios) = { + { "gpio_mxc", &mxc_plat[0] }, + { "gpio_mxc", &mxc_plat[1] }, + { "gpio_mxc", &mxc_plat[2] }, +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \ + defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) + { "gpio_mxc", &mxc_plat[3] }, +#endif +#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) + { "gpio_mxc", &mxc_plat[4] }, + { "gpio_mxc", &mxc_plat[5] }, +#endif +#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6) + { "gpio_mxc", &mxc_plat[6] }, +#endif +}; +#endif diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index d9a7a3aaf6..82ae23d315 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -11,10 +11,11 @@ #include #include #include +#include #include #include -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) #define PINCTRL_BANKS 3 #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10)) #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10)) @@ -22,7 +23,7 @@ #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10)) #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10)) #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10)) -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) #define PINCTRL_BANKS 5 #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10)) #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10)) @@ -31,7 +32,7 @@ #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10)) #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10)) #else -#error "Please select CONFIG_MX23 or CONFIG_MX28" +#error "Please select CONFIG_SOC_MX23 or CONFIG_SOC_MX28" #endif #define GPIO_INT_FALL_EDGE 0x0 @@ -63,7 +64,7 @@ int gpio_get_value(unsigned gpio) return (readl(®->reg) >> PAD_PIN(gpio)) & 1; } -void gpio_set_value(unsigned gpio, int value) +int gpio_set_value(unsigned gpio, int value) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOUT(bank); @@ -74,6 +75,8 @@ void gpio_set_value(unsigned gpio, int value) writel(1 << PAD_PIN(gpio), ®->reg_set); else writel(1 << PAD_PIN(gpio), ®->reg_clr); + + return 0; } int gpio_direction_input(unsigned gpio) @@ -95,10 +98,10 @@ int gpio_direction_output(unsigned gpio, int value) struct mxs_register_32 *reg = (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); - writel(1 << PAD_PIN(gpio), ®->reg_set); - gpio_set_value(gpio, value); + writel(1 << PAD_PIN(gpio), ®->reg_set); + return 0; } diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index f16e9ae4d2..f3a7ccb51e 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -2,20 +2,7 @@ * Copyright (c) 2009 Wind River Systems, Inc. * Tom Rix * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * This work is derived from the linux 2.6.27 kernel source * To fetch, use the kernel repository @@ -30,12 +17,9 @@ * * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include +#include #include #include #include @@ -43,10 +27,17 @@ #define OMAP_GPIO_DIR_OUT 0 #define OMAP_GPIO_DIR_IN 1 -static inline const struct gpio_bank *get_gpio_bank(int gpio) -{ - return &omap_gpio_bank[gpio >> 5]; -} +#ifdef CONFIG_DM_GPIO + +#define GPIO_PER_BANK 32 + +struct gpio_bank { + /* TODO(sjg@chromium.org): Can we use a struct here? */ + void *base; /* address of registers in physical memory */ + enum gpio_method method; +}; + +#endif static inline int get_gpio_index(int gpio) { @@ -58,15 +49,6 @@ int gpio_is_valid(int gpio) return (gpio >= 0) && (gpio < OMAP_MAX_GPIO); } -static int check_gpio(int gpio) -{ - if (!gpio_is_valid(gpio)) { - printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); - return -1; - } - return 0; -} - static void _set_gpio_direction(const struct gpio_bank *bank, int gpio, int is_input) { @@ -135,6 +117,48 @@ static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio, __raw_writel(l, reg); } +static int _get_gpio_value(const struct gpio_bank *bank, int gpio) +{ + void *reg = bank->base; + int input; + + switch (bank->method) { + case METHOD_GPIO_24XX: + input = _get_gpio_direction(bank, gpio); + switch (input) { + case OMAP_GPIO_DIR_IN: + reg += OMAP_GPIO_DATAIN; + break; + case OMAP_GPIO_DIR_OUT: + reg += OMAP_GPIO_DATAOUT; + break; + default: + return -1; + } + break; + default: + return -1; + } + + return (__raw_readl(reg) & (1 << gpio)) != 0; +} + +#ifndef CONFIG_DM_GPIO + +static inline const struct gpio_bank *get_gpio_bank(int gpio) +{ + return &omap_gpio_bank[gpio >> 5]; +} + +static int check_gpio(int gpio) +{ + if (!gpio_is_valid(gpio)) { + printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); + return -1; + } + return 0; +} + /** * Set value of the specified gpio */ @@ -156,32 +180,12 @@ int gpio_set_value(unsigned gpio, int value) int gpio_get_value(unsigned gpio) { const struct gpio_bank *bank; - void *reg; - int input; if (check_gpio(gpio) < 0) return -1; bank = get_gpio_bank(gpio); - reg = bank->base; - switch (bank->method) { - case METHOD_GPIO_24XX: - input = _get_gpio_direction(bank, get_gpio_index(gpio)); - switch (input) { - case OMAP_GPIO_DIR_IN: - reg += OMAP_GPIO_DATAIN; - break; - case OMAP_GPIO_DIR_OUT: - reg += OMAP_GPIO_DATAOUT; - break; - default: - return -1; - } - break; - default: - return -1; - } - return (__raw_readl(reg) - & (1 << get_gpio_index(gpio))) != 0; + + return _get_gpio_value(bank, get_gpio_index(gpio)); } /** @@ -237,3 +241,95 @@ int gpio_free(unsigned gpio) { return 0; } + +#else /* new driver model interface CONFIG_DM_GPIO */ + +/* set GPIO pin 'gpio' as an input */ +static int omap_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + /* Configure GPIO direction as input. */ + _set_gpio_direction(bank, offset, 1); + + return 0; +} + +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +static int omap_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + _set_gpio_dataout(bank, offset, value); + _set_gpio_direction(bank, offset, 0); + + return 0; +} + +/* read GPIO IN value of pin 'gpio' */ +static int omap_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + return _get_gpio_value(bank, offset); +} + +/* write GPIO OUT value to pin 'gpio' */ +static int omap_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + _set_gpio_dataout(bank, offset, value); + + return 0; +} + +static int omap_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + /* GPIOF_FUNC is not implemented yet */ + if (_get_gpio_direction(bank->base, offset) == OMAP_GPIO_DIR_OUT) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops gpio_omap_ops = { + .direction_input = omap_gpio_direction_input, + .direction_output = omap_gpio_direction_output, + .get_value = omap_gpio_get_value, + .set_value = omap_gpio_set_value, + .get_function = omap_gpio_get_function, +}; + +static int omap_gpio_probe(struct udevice *dev) +{ + struct gpio_bank *bank = dev_get_priv(dev); + struct omap_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + char name[18], *str; + + sprintf(name, "GPIO%d_", plat->bank_index); + str = strdup(name); + if (!str) + return -ENOMEM; + uc_priv->bank_name = str; + uc_priv->gpio_count = GPIO_PER_BANK; + bank->base = (void *)plat->base; + bank->method = plat->method; + + return 0; +} + +U_BOOT_DRIVER(gpio_omap) = { + .name = "gpio_omap", + .id = UCLASS_GPIO, + .ops = &gpio_omap_ops, + .probe = omap_gpio_probe, + .priv_auto_alloc_size = sizeof(struct gpio_bank), +}; + +#endif /* CONFIG_DM_GPIO */ diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index be13745921..7371cd4a87 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -47,9 +47,6 @@ struct pca953x_chip_ngpio { static struct pca953x_chip_ngpio pca953x_chip_ngpios[] = CONFIG_SYS_I2C_PCA953X_WIDTH; -#define NUM_CHIP_GPIOS (sizeof(pca953x_chip_ngpios) / \ - sizeof(struct pca953x_chip_ngpio)) - /* * Determine the number of GPIO pins supported. If we don't know we assume * 8 pins. @@ -58,7 +55,7 @@ static int pca953x_ngpio(uint8_t chip) { int i; - for (i = 0; i < NUM_CHIP_GPIOS; i++) + for (i = 0; i < ARRAY_SIZE(pca953x_chip_ngpios); i++) if (pca953x_chip_ngpios[i].chip == chip) return pca953x_chip_ngpios[i].ngpio; diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 7eeb96d19f..0a245ba18a 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -6,24 +6,73 @@ */ #include +#include +#include +#include +#include #include #include +#include +#include -#define CON_MASK(x) (0xf << ((x) << 2)) -#define CON_SFR(x, v) ((v) << ((x) << 2)) +DECLARE_GLOBAL_DATA_PTR; -#define DAT_MASK(x) (0x1 << (x)) -#define DAT_SET(x) (0x1 << (x)) +#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK) -#define PULL_MASK(x) (0x3 << ((x) << 1)) -#define PULL_MODE(x, v) ((v) << ((x) << 1)) +#define CON_MASK(val) (0xf << ((val) << 2)) +#define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2)) +#define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2)) -#define DRV_MASK(x) (0x3 << ((x) << 1)) -#define DRV_SET(x, m) ((m) << ((x) << 1)) -#define RATE_MASK(x) (0x1 << (x + 16)) -#define RATE_SET(x) (0x1 << (x + 16)) +#define DAT_MASK(gpio) (0x1 << (gpio)) +#define DAT_SET(gpio) (0x1 << (gpio)) -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) +#define PULL_MASK(gpio) (0x3 << ((gpio) << 1)) +#define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1)) + +#define DRV_MASK(gpio) (0x3 << ((gpio) << 1)) +#define DRV_SET(gpio, mode) ((mode) << ((gpio) << 1)) +#define RATE_MASK(gpio) (0x1 << (gpio + 16)) +#define RATE_SET(gpio) (0x1 << (gpio + 16)) + +/* Platform data for each bank */ +struct exynos_gpio_platdata { + struct s5p_gpio_bank *bank; + const char *bank_name; /* Name of port, e.g. 'gpa0" */ +}; + +/* Information about each bank at run-time */ +struct exynos_bank_info { + struct s5p_gpio_bank *bank; +}; + +static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio) +{ + const struct gpio_info *data; + unsigned int upto; + int i, count; + + data = get_gpio_data(); + count = get_bank_num(); + upto = 0; + + for (i = 0; i < count; i++) { + debug("i=%d, upto=%d\n", i, upto); + if (gpio < data->max_gpio) { + struct s5p_gpio_bank *bank; + bank = (struct s5p_gpio_bank *)data->reg_addr; + bank += (gpio - upto) / GPIO_PER_BANK; + debug("gpio=%d, bank=%p\n", gpio, bank); + return bank; + } + + upto = data->max_gpio; + data++; + } + + return NULL; +} + +static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) { unsigned int value; @@ -33,18 +82,7 @@ void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) writel(value, &bank->con); } -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) -{ - s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); - s5p_gpio_set_value(bank, gpio, en); -} - -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) -{ - s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT); -} - -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) +static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) { unsigned int value; @@ -55,15 +93,35 @@ void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) writel(value, &bank->dat); } -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) +#ifdef CONFIG_SPL_BUILD +/* Common GPIO API - SPL does not support driver model yet */ +int gpio_set_value(unsigned gpio, int value) +{ + s5p_gpio_set_value(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), value); + + return 0; +} +#else +static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio) +{ + unsigned int value; + + value = readl(&bank->con); + value &= CON_MASK(gpio); + return CON_SFR_UNSHIFT(value, gpio); +} + +static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) { unsigned int value; value = readl(&bank->dat); return !!(value & DAT_MASK(gpio)); } +#endif /* CONFIG_SPL_BUILD */ -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -71,8 +129,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~PULL_MASK(gpio); switch (mode) { - case GPIO_PULL_DOWN: - case GPIO_PULL_UP: + case S5P_GPIO_PULL_DOWN: + case S5P_GPIO_PULL_UP: value |= PULL_MODE(gpio, mode); break; default: @@ -82,7 +140,7 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->pull); } -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -90,10 +148,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~DRV_MASK(gpio); switch (mode) { - case GPIO_DRV_1X: - case GPIO_DRV_2X: - case GPIO_DRV_3X: - case GPIO_DRV_4X: + case S5P_GPIO_DRV_1X: + case S5P_GPIO_DRV_2X: + case S5P_GPIO_DRV_3X: + case S5P_GPIO_DRV_4X: value |= DRV_SET(gpio, mode); break; default: @@ -103,7 +161,7 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -111,8 +169,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~RATE_MASK(gpio); switch (mode) { - case GPIO_DRV_FAST: - case GPIO_DRV_SLOW: + case S5P_GPIO_DRV_FAST: + case S5P_GPIO_DRV_SLOW: value |= RATE_SET(gpio); break; default: @@ -122,57 +180,202 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) +int s5p_gpio_get_pin(unsigned gpio) +{ + return S5P_GPIO_GET_PIN(gpio); +} + +/* Driver model interface */ +#ifndef CONFIG_SPL_BUILD +/* set GPIO pin 'gpio' as an input */ +static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset) { - int bank; - unsigned g = gpio - s5p_gpio_part_max(gpio); + struct exynos_bank_info *state = dev_get_priv(dev); + + /* Configure GPIO direction as input. */ + s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT); - bank = g / GPIO_PER_BANK; - bank *= sizeof(struct s5p_gpio_bank); - return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank); + return 0; } -int s5p_gpio_get_pin(unsigned gpio) +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) { - return gpio % GPIO_PER_BANK; + struct exynos_bank_info *state = dev_get_priv(dev); + + /* Configure GPIO output value. */ + s5p_gpio_set_value(state->bank, offset, value); + + /* Configure GPIO direction as output. */ + s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT); + + return 0; } -/* Common GPIO API */ +/* read GPIO IN value of pin 'gpio' */ +static int exynos_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct exynos_bank_info *state = dev_get_priv(dev); -int gpio_request(unsigned gpio, const char *label) + return s5p_gpio_get_value(state->bank, offset); +} + +/* write GPIO OUT value to pin 'gpio' */ +static int exynos_gpio_set_value(struct udevice *dev, unsigned offset, + int value) { + struct exynos_bank_info *state = dev_get_priv(dev); + + s5p_gpio_set_value(state->bank, offset, value); + return 0; } +#endif /* nCONFIG_SPL_BUILD */ -int gpio_free(unsigned gpio) +/* + * There is no common GPIO API for pull, drv, pin, rate (yet). These + * functions are kept here to preserve function ordering for review. + */ +void gpio_set_pull(int gpio, int mode) { - return 0; + s5p_gpio_set_pull(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); } -int gpio_direction_input(unsigned gpio) +void gpio_set_drv(int gpio, int mode) { - s5p_gpio_direction_input(s5p_gpio_get_bank(gpio), - s5p_gpio_get_pin(gpio)); - return 0; + s5p_gpio_set_drv(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} + +void gpio_cfg_pin(int gpio, int cfg) +{ + s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), cfg); +} + +void gpio_set_rate(int gpio, int mode) +{ + s5p_gpio_set_rate(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} + +#ifndef CONFIG_SPL_BUILD +static int exynos_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct exynos_bank_info *state = dev_get_priv(dev); + int cfg; + + cfg = s5p_gpio_get_cfg_pin(state->bank, offset); + if (cfg == S5P_GPIO_OUTPUT) + return GPIOF_OUTPUT; + else if (cfg == S5P_GPIO_INPUT) + return GPIOF_INPUT; + else + return GPIOF_FUNC; } -int gpio_direction_output(unsigned gpio, int value) +static int exynos_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) { - s5p_gpio_direction_output(s5p_gpio_get_bank(gpio), - s5p_gpio_get_pin(gpio), value); + desc->offset = args->args[0]; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + return 0; } -int gpio_get_value(unsigned gpio) +static const struct dm_gpio_ops gpio_exynos_ops = { + .direction_input = exynos_gpio_direction_input, + .direction_output = exynos_gpio_direction_output, + .get_value = exynos_gpio_get_value, + .set_value = exynos_gpio_set_value, + .get_function = exynos_gpio_get_function, + .xlate = exynos_gpio_xlate, +}; + +static int gpio_exynos_probe(struct udevice *dev) { - return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio), - s5p_gpio_get_pin(gpio)); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct exynos_bank_info *priv = dev->priv; + struct exynos_gpio_platdata *plat = dev->platdata; + + /* Only child devices have ports */ + if (!plat) + return 0; + + priv->bank = plat->bank; + + uc_priv->gpio_count = GPIO_PER_BANK; + uc_priv->bank_name = plat->bank_name; + + return 0; } -int gpio_set_value(unsigned gpio, int value) +/** + * We have a top-level GPIO device with no actual GPIOs. It has a child + * device for each Exynos GPIO bank. + */ +static int gpio_exynos_bind(struct udevice *parent) { - s5p_gpio_set_value(s5p_gpio_get_bank(gpio), - s5p_gpio_get_pin(gpio), value); + struct exynos_gpio_platdata *plat = parent->platdata; + struct s5p_gpio_bank *bank, *base; + const void *blob = gd->fdt_blob; + int node; + + /* If this is a child device, there is nothing to do here */ + if (plat) + return 0; + + base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob, + parent->of_offset, "reg"); + for (node = fdt_first_subnode(blob, parent->of_offset), bank = base; + node > 0; + node = fdt_next_subnode(blob, node), bank++) { + struct exynos_gpio_platdata *plat; + struct udevice *dev; + fdt_addr_t reg; + int ret; + + if (!fdtdec_get_bool(blob, node, "gpio-controller")) + continue; + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + reg = fdtdec_get_addr(blob, node, "reg"); + if (reg != FDT_ADDR_T_NONE) + bank = (struct s5p_gpio_bank *)((ulong)base + reg); + plat->bank = bank; + plat->bank_name = fdt_get_name(blob, node, NULL); + debug("dev at %p: %s\n", bank, plat->bank_name); + + ret = device_bind(parent, parent->driver, + plat->bank_name, plat, -1, &dev); + if (ret) + return ret; + dev->of_offset = node; + } return 0; } + +static const struct udevice_id exynos_gpio_ids[] = { + { .compatible = "samsung,s5pc100-pinctrl" }, + { .compatible = "samsung,s5pc110-pinctrl" }, + { .compatible = "samsung,exynos4210-pinctrl" }, + { .compatible = "samsung,exynos4x12-pinctrl" }, + { .compatible = "samsung,exynos5250-pinctrl" }, + { .compatible = "samsung,exynos5420-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(gpio_exynos) = { + .name = "gpio_exynos", + .id = UCLASS_GPIO, + .of_match = exynos_gpio_ids, + .bind = gpio_exynos_bind, + .probe = gpio_exynos_probe, + .priv_auto_alloc_size = sizeof(struct exynos_bank_info), + .ops = &gpio_exynos_ops, +}; +#endif diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index 3c6cfec179..d564c252c7 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -4,46 +4,47 @@ */ #include +#include +#include +#include #include +#include + +DECLARE_GLOBAL_DATA_PTR; /* Flags for each GPIO */ #define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */ #define GPIOF_HIGH (1 << 1) /* Currently set high */ -#define GPIOF_RESERVED (1 << 2) /* Is in use / requested */ struct gpio_state { const char *label; /* label given by requester */ u8 flags; /* flags (GPIOF_...) */ }; -/* - * State of GPIOs - * TODO: Put this into sandbox state - */ -static struct gpio_state state[CONFIG_SANDBOX_GPIO_COUNT]; - /* Access routines for GPIO state */ -static u8 *get_gpio_flags(unsigned gp) +static u8 *get_gpio_flags(struct udevice *dev, unsigned offset) { - /* assert()'s could be disabled, so make sure we handle that */ - assert(gp < ARRAY_SIZE(state)); - if (gp >= ARRAY_SIZE(state)) { + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct gpio_state *state = dev_get_priv(dev); + + if (offset >= uc_priv->gpio_count) { static u8 invalid_flags; - printf("sandbox_gpio: error: invalid gpio %u\n", gp); + printf("sandbox_gpio: error: invalid gpio %u\n", offset); return &invalid_flags; } - return &state[gp].flags; + return &state[offset].flags; } -static int get_gpio_flag(unsigned gp, int flag) +static int get_gpio_flag(struct udevice *dev, unsigned offset, int flag) { - return (*get_gpio_flags(gp) & flag) != 0; + return (*get_gpio_flags(dev, offset) & flag) != 0; } -static int set_gpio_flag(unsigned gp, int flag, int value) +static int set_gpio_flag(struct udevice *dev, unsigned offset, int flag, + int value) { - u8 *gpio = get_gpio_flags(gp); + u8 *gpio = get_gpio_flags(dev, offset); if (value) *gpio |= flag; @@ -53,141 +54,154 @@ static int set_gpio_flag(unsigned gp, int flag, int value) return 0; } -static int check_reserved(unsigned gpio, const char *func) -{ - if (!get_gpio_flag(gpio, GPIOF_RESERVED)) { - printf("sandbox_gpio: %s: error: gpio %u not reserved\n", - func, gpio); - return -1; - } - - return 0; -} - /* * Back-channel sandbox-internal-only access to GPIO state */ -int sandbox_gpio_get_value(unsigned gp) +int sandbox_gpio_get_value(struct udevice *dev, unsigned offset) { - if (get_gpio_flag(gp, GPIOF_OUTPUT)) - debug("sandbox_gpio: get_value on output gpio %u\n", gp); - return get_gpio_flag(gp, GPIOF_HIGH); + if (get_gpio_flag(dev, offset, GPIOF_OUTPUT)) + debug("sandbox_gpio: get_value on output gpio %u\n", offset); + return get_gpio_flag(dev, offset, GPIOF_HIGH); } -int sandbox_gpio_set_value(unsigned gp, int value) +int sandbox_gpio_set_value(struct udevice *dev, unsigned offset, int value) { - return set_gpio_flag(gp, GPIOF_HIGH, value); + return set_gpio_flag(dev, offset, GPIOF_HIGH, value); } -int sandbox_gpio_get_direction(unsigned gp) +int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset) { - return get_gpio_flag(gp, GPIOF_OUTPUT); + return get_gpio_flag(dev, offset, GPIOF_OUTPUT); } -int sandbox_gpio_set_direction(unsigned gp, int output) +int sandbox_gpio_set_direction(struct udevice *dev, unsigned offset, int output) { - return set_gpio_flag(gp, GPIOF_OUTPUT, output); + return set_gpio_flag(dev, offset, GPIOF_OUTPUT, output); } /* * These functions implement the public interface within U-Boot */ -/* set GPIO port 'gp' as an input */ -int gpio_direction_input(unsigned gp) +/* set GPIO port 'offset' as an input */ +static int sb_gpio_direction_input(struct udevice *dev, unsigned offset) { - debug("%s: gp:%u\n", __func__, gp); - - if (check_reserved(gp, __func__)) - return -1; + debug("%s: offset:%u\n", __func__, offset); - return sandbox_gpio_set_direction(gp, 0); + return sandbox_gpio_set_direction(dev, offset, 0); } -/* set GPIO port 'gp' as an output, with polarity 'value' */ -int gpio_direction_output(unsigned gp, int value) +/* set GPIO port 'offset' as an output, with polarity 'value' */ +static int sb_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) { - debug("%s: gp:%u, value = %d\n", __func__, gp, value); + debug("%s: offset:%u, value = %d\n", __func__, offset, value); - if (check_reserved(gp, __func__)) - return -1; - - return sandbox_gpio_set_direction(gp, 1) | - sandbox_gpio_set_value(gp, value); + return sandbox_gpio_set_direction(dev, offset, 1) | + sandbox_gpio_set_value(dev, offset, value); } -/* read GPIO IN value of port 'gp' */ -int gpio_get_value(unsigned gp) +/* read GPIO IN value of port 'offset' */ +static int sb_gpio_get_value(struct udevice *dev, unsigned offset) { - debug("%s: gp:%u\n", __func__, gp); + debug("%s: offset:%u\n", __func__, offset); - if (check_reserved(gp, __func__)) - return -1; - - return sandbox_gpio_get_value(gp); + return sandbox_gpio_get_value(dev, offset); } -/* write GPIO OUT value to port 'gp' */ -int gpio_set_value(unsigned gp, int value) +/* write GPIO OUT value to port 'offset' */ +static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value) { - debug("%s: gp:%u, value = %d\n", __func__, gp, value); - - if (check_reserved(gp, __func__)) - return -1; + debug("%s: offset:%u, value = %d\n", __func__, offset, value); - if (!sandbox_gpio_get_direction(gp)) { - printf("sandbox_gpio: error: set_value on input gpio %u\n", gp); + if (!sandbox_gpio_get_direction(dev, offset)) { + printf("sandbox_gpio: error: set_value on input gpio %u\n", + offset); return -1; } - return sandbox_gpio_set_value(gp, value); + return sandbox_gpio_set_value(dev, offset, value); } -int gpio_request(unsigned gp, const char *label) +static int sb_gpio_get_function(struct udevice *dev, unsigned offset) { - debug("%s: gp:%u, label:%s\n", __func__, gp, label); - - if (gp >= ARRAY_SIZE(state)) { - printf("sandbox_gpio: error: invalid gpio %u\n", gp); - return -1; - } + if (get_gpio_flag(dev, offset, GPIOF_OUTPUT)) + return GPIOF_OUTPUT; + return GPIOF_INPUT; +} - if (get_gpio_flag(gp, GPIOF_RESERVED)) { - printf("sandbox_gpio: error: gpio %u already reserved\n", gp); - return -1; - } +static int sb_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + desc->offset = args->args[0]; + if (args->args_count < 2) + return 0; + if (args->args[1] & GPIO_ACTIVE_LOW) + desc->flags |= GPIOD_ACTIVE_LOW; + if (args->args[1] & 2) + desc->flags |= GPIOD_IS_IN; + if (args->args[1] & 4) + desc->flags |= GPIOD_IS_OUT; + if (args->args[1] & 8) + desc->flags |= GPIOD_IS_OUT_ACTIVE; - state[gp].label = label; - return set_gpio_flag(gp, GPIOF_RESERVED, 1); + return 0; } -int gpio_free(unsigned gp) +static const struct dm_gpio_ops gpio_sandbox_ops = { + .direction_input = sb_gpio_direction_input, + .direction_output = sb_gpio_direction_output, + .get_value = sb_gpio_get_value, + .set_value = sb_gpio_set_value, + .get_function = sb_gpio_get_function, + .xlate = sb_gpio_xlate, +}; + +static int sandbox_gpio_ofdata_to_platdata(struct udevice *dev) { - debug("%s: gp:%u\n", __func__, gp); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; - if (check_reserved(gp, __func__)) - return -1; + uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "num-gpios", 0); + uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, + "gpio-bank-name", NULL); - state[gp].label = NULL; - return set_gpio_flag(gp, GPIOF_RESERVED, 0); + return 0; } -/* Display GPIO information */ -void gpio_info(void) +static int gpio_sandbox_probe(struct udevice *dev) { - unsigned gpio; + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + if (dev->of_offset == -1) { + /* Tell the uclass how many GPIOs we have */ + uc_priv->gpio_count = CONFIG_SANDBOX_GPIO_COUNT; + } + + dev->priv = calloc(sizeof(struct gpio_state), uc_priv->gpio_count); - puts("Sandbox GPIOs\n"); + return 0; +} - for (gpio = 0; gpio < ARRAY_SIZE(state); ++gpio) { - const char *label = state[gpio].label; +static int gpio_sandbox_remove(struct udevice *dev) +{ + free(dev->priv); - printf("%4d: %s: %d [%c] %s\n", - gpio, - sandbox_gpio_get_direction(gpio) ? "out" : " in", - sandbox_gpio_get_value(gpio), - get_gpio_flag(gpio, GPIOF_RESERVED) ? 'x' : ' ', - label ? label : ""); - } + return 0; } + +static const struct udevice_id sandbox_gpio_ids[] = { + { .compatible = "sandbox,gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_sandbox) = { + .name = "gpio_sandbox", + .id = UCLASS_GPIO, + .of_match = sandbox_gpio_ids, + .ofdata_to_platdata = sandbox_gpio_ofdata_to_platdata, + .probe = gpio_sandbox_probe, + .remove = gpio_sandbox_remove, + .ops = &gpio_sandbox_ops, +}; diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c index 367b670166..6fb4117dbe 100644 --- a/drivers/gpio/spear_gpio.c +++ b/drivers/gpio/spear_gpio.c @@ -36,7 +36,10 @@ int gpio_set_value(unsigned gpio, int value) { struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; - writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]); + if (value) + writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]); + else + writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]); return 0; } diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c new file mode 100644 index 0000000000..62960929ad --- /dev/null +++ b/drivers/gpio/sunxi_gpio.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c: + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_AXP209_POWER +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR + +struct sunxi_gpio_platdata { + struct sunxi_gpio *regs; + const char *bank_name; /* Name of bank, e.g. "B" */ + int gpio_count; +}; + +#ifndef CONFIG_DM_GPIO +static int sunxi_gpio_output(u32 pin, u32 val) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + dat = readl(&pio->dat); + if (val) + dat |= 0x1 << num; + else + dat &= ~(0x1 << num); + + writel(dat, &pio->dat); + + return 0; +} + +static int sunxi_gpio_input(u32 pin) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + dat = readl(&pio->dat); + dat >>= num; + + return dat & 0x1; +} + +int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ +#ifdef AXP_GPIO + if (gpio >= SUNXI_GPIO_AXP0_START) + return axp_gpio_direction_input(gpio - SUNXI_GPIO_AXP0_START); +#endif + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT); + + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ +#ifdef AXP_GPIO + if (gpio >= SUNXI_GPIO_AXP0_START) + return axp_gpio_direction_output(gpio - SUNXI_GPIO_AXP0_START, + value); +#endif + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT); + + return sunxi_gpio_output(gpio, value); +} + +int gpio_get_value(unsigned gpio) +{ +#ifdef AXP_GPIO + if (gpio >= SUNXI_GPIO_AXP0_START) + return axp_gpio_get_value(gpio - SUNXI_GPIO_AXP0_START); +#endif + return sunxi_gpio_input(gpio); +} + +int gpio_set_value(unsigned gpio, int value) +{ +#ifdef AXP_GPIO + if (gpio >= SUNXI_GPIO_AXP0_START) + return axp_gpio_set_value(gpio - SUNXI_GPIO_AXP0_START, value); +#endif + return sunxi_gpio_output(gpio, value); +} + +int sunxi_name_to_gpio(const char *name) +{ + int group = 0; + int groupsize = 9 * 32; + long pin; + char *eptr; + +#ifdef AXP_GPIO + if (strncasecmp(name, "AXP0-", 5) == 0) { + name += 5; + pin = simple_strtol(name, &eptr, 10); + if (!*name || *eptr) + return -1; + return SUNXI_GPIO_AXP0_START + pin; + } +#endif + if (*name == 'P' || *name == 'p') + name++; + if (*name >= 'A') { + group = *name - (*name > 'a' ? 'a' : 'A'); + groupsize = 32; + name++; + } + + pin = simple_strtol(name, &eptr, 10); + if (!*name || *eptr) + return -1; + if (pin < 0 || pin > groupsize || group >= 9) + return -1; + return group * 32 + pin; +} +#endif + +#ifdef CONFIG_DM_GPIO +static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); + + sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT); + + return 0; +} + +static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); + u32 num = GPIO_NUM(offset); + + sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); + clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0); + + return 0; +} + +static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); + u32 num = GPIO_NUM(offset); + unsigned dat; + + dat = readl(&plat->regs->dat); + dat >>= num; + + return dat & 0x1; +} + +static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); + u32 num = GPIO_NUM(offset); + + clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0); + return 0; +} + +static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); + int func; + + func = sunxi_gpio_get_cfgbank(plat->regs, offset); + if (func == SUNXI_GPIO_OUTPUT) + return GPIOF_OUTPUT; + else if (func == SUNXI_GPIO_INPUT) + return GPIOF_INPUT; + else + return GPIOF_FUNC; +} + +static const struct dm_gpio_ops gpio_sunxi_ops = { + .direction_input = sunxi_gpio_direction_input, + .direction_output = sunxi_gpio_direction_output, + .get_value = sunxi_gpio_get_value, + .set_value = sunxi_gpio_set_value, + .get_function = sunxi_gpio_get_function, +}; + +/** + * Returns the name of a GPIO bank + * + * GPIO banks are named A, B, C, ... + * + * @bank: Bank number (0, 1..n-1) + * @return allocated string containing the name + */ +static char *gpio_bank_name(int bank) +{ + char *name; + + name = malloc(2); + if (name) { + name[0] = 'A' + bank; + name[1] = '\0'; + } + + return name; +} + +static int gpio_sunxi_probe(struct udevice *dev) +{ + struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + /* Tell the uclass how many GPIOs we have */ + if (plat) { + uc_priv->gpio_count = plat->gpio_count; + uc_priv->bank_name = plat->bank_name; + } + + return 0; +} +/** + * We have a top-level GPIO device with no actual GPIOs. It has a child + * device for each Sunxi bank. + */ +static int gpio_sunxi_bind(struct udevice *parent) +{ + struct sunxi_gpio_platdata *plat = parent->platdata; + struct sunxi_gpio_reg *ctlr; + int bank; + int ret; + + /* If this is a child device, there is nothing to do here */ + if (plat) + return 0; + + ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob, + parent->of_offset, "reg"); + for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) { + struct sunxi_gpio_platdata *plat; + struct udevice *dev; + + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + plat->regs = &ctlr->gpio_bank[bank]; + plat->bank_name = gpio_bank_name(bank); + plat->gpio_count = SUNXI_GPIOS_PER_BANK; + + ret = device_bind(parent, parent->driver, + plat->bank_name, plat, -1, &dev); + if (ret) + return ret; + dev->of_offset = parent->of_offset; + } + + return 0; +} + +static const struct udevice_id sunxi_gpio_ids[] = { + { .compatible = "allwinner,sun7i-a20-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(gpio_sunxi) = { + .name = "gpio_sunxi", + .id = UCLASS_GPIO, + .ops = &gpio_sunxi_ops, + .of_match = sunxi_gpio_ids, + .bind = gpio_sunxi_bind, + .probe = gpio_sunxi_probe, +}; +#endif diff --git a/drivers/gpio/sx151x.c b/drivers/gpio/sx151x.c new file mode 100644 index 0000000000..167cf40c71 --- /dev/null +++ b/drivers/gpio/sx151x.c @@ -0,0 +1,242 @@ +/* + * (C) Copyright 2013 + * Viktar Palstsiuk, Promwad, viktar.palstsiuk@promwad.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Driver for Semtech SX151x SPI GPIO Expanders + */ + +#include +#include +#include + +#ifndef CONFIG_SX151X_SPI_BUS +#define CONFIG_SX151X_SPI_BUS 0 +#endif + +/* + * The SX151x registers + */ + +#ifdef CONFIG_SX151X_GPIO_COUNT_8 +/* 8bit: SX1511 */ +#define SX151X_REG_DIR 0x07 +#define SX151X_REG_DATA 0x08 +#else +/* 16bit: SX1512 */ +#define SX151X_REG_DIR 0x0F +#define SX151X_REG_DATA 0x11 +#endif +#define SX151X_REG_RESET 0x7D + +static int sx151x_spi_write(int chip, unsigned char reg, unsigned char val) +{ + struct spi_slave *slave; + unsigned char buf[2]; + int ret; + + slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000, + SPI_MODE_0); + if (!slave) + return 0; + + spi_claim_bus(slave); + + buf[0] = reg; + buf[1] = val; + + ret = spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + if (ret < 0) + printf("spi%d.%d write fail: can't write %02x to %02x: %d\n", + CONFIG_SX151X_SPI_BUS, chip, val, reg, ret); + else + printf("spi%d.%d write 0x%02x to register 0x%02x\n", + CONFIG_SX151X_SPI_BUS, chip, val, reg); + spi_release_bus(slave); + spi_free_slave(slave); + + return ret; +} + +static int sx151x_spi_read(int chip, unsigned char reg) +{ + struct spi_slave *slave; + int ret; + + slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000, + SPI_MODE_0); + if (!slave) + return 0; + + spi_claim_bus(slave); + + ret = spi_w8r8(slave, reg | 0x80); + if (ret < 0) + printf("spi%d.%d read fail: can't read %02x: %d\n", + CONFIG_SX151X_SPI_BUS, chip, reg, ret); + else + printf("spi%d.%d read register 0x%02x: 0x%02x\n", + CONFIG_SX151X_SPI_BUS, chip, reg, ret); + + spi_release_bus(slave); + spi_free_slave(slave); + + return ret; +} + +static inline void sx151x_find_cfg(int gpio, unsigned char *reg, unsigned char *mask) +{ + *reg -= gpio / 8; + *mask = 1 << (gpio % 8); +} + +static int sx151x_write_cfg(int chip, unsigned char gpio, unsigned char reg, int val) +{ + unsigned char mask; + unsigned char data; + int ret; + + sx151x_find_cfg(gpio, ®, &mask); + ret = sx151x_spi_read(chip, reg); + if (ret < 0) + return ret; + else + data = ret; + data &= ~mask; + data |= (val << (gpio % 8)) & mask; + return sx151x_spi_write(chip, reg, data); +} + +int sx151x_get_value(int chip, int gpio) +{ + unsigned char reg = SX151X_REG_DATA; + unsigned char mask; + int ret; + + sx151x_find_cfg(gpio, ®, &mask); + ret = sx151x_spi_read(chip, reg); + if (ret >= 0) + ret = (ret & mask) != 0 ? 1 : 0; + + return ret; +} + +int sx151x_set_value(int chip, int gpio, int val) +{ + return sx151x_write_cfg(chip, gpio, SX151X_REG_DATA, (val ? 1 : 0)); +} + +int sx151x_direction_input(int chip, int gpio) +{ + return sx151x_write_cfg(chip, gpio, SX151X_REG_DIR, 1); +} + +int sx151x_direction_output(int chip, int gpio) +{ + return sx151x_write_cfg(chip, gpio, SX151X_REG_DIR, 0); +} + +int sx151x_reset(int chip) +{ + int err; + + err = sx151x_spi_write(chip, SX151X_REG_RESET, 0x12); + if (err < 0) + return err; + + err = sx151x_spi_write(chip, SX151X_REG_RESET, 0x34); + return err; +} + +#ifdef CONFIG_CMD_SX151X + +int do_sx151x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret = CMD_RET_USAGE, chip = 0, gpio = 0, val = 0; + + if (argc < 3) + return CMD_RET_USAGE; + + /* arg2 used as chip number */ + chip = simple_strtoul(argv[2], NULL, 10); + + if (strcmp(argv[1], "reset") == 0) { + ret = sx151x_reset(chip); + if (!ret) { + printf("Device at spi%d.%d was reset\n", + CONFIG_SX151X_SPI_BUS, chip); + } + return ret; + } + + if (argc < 4) + return CMD_RET_USAGE; + + /* arg3 used as gpio number */ + gpio = simple_strtoul(argv[3], NULL, 10); + + if (strcmp(argv[1], "get") == 0) { + ret = sx151x_get_value(chip, gpio); + if (ret < 0) + printf("Failed to get value at spi%d.%d gpio %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio); + else { + printf("Value at spi%d.%d gpio %d is %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio, ret); + ret = 0; + } + return ret; + } + + if (argc < 5) + return CMD_RET_USAGE; + + /* arg4 used as value or direction */ + val = simple_strtoul(argv[4], NULL, 10); + + if (strcmp(argv[1], "set") == 0) { + ret = sx151x_set_value(chip, gpio, val); + if (ret < 0) + printf("Failed to set value at spi%d.%d gpio %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio); + else + printf("New value at spi%d.%d gpio %d is %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio, val); + return ret; + } else if (strcmp(argv[1], "dir") == 0) { + if (val == 0) + ret = sx151x_direction_output(chip, gpio); + else + ret = sx151x_direction_input(chip, gpio); + + if (ret < 0) + printf("Failed to set direction of spi%d.%d gpio %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio); + else + printf("New direction of spi%d.%d gpio %d is %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio, val); + return ret; + } + + printf("Please see usage\n"); + + return ret; +} + +U_BOOT_CMD( + sx151x, 5, 1, do_sx151x, + "sx151x gpio access", + "dir chip gpio 0|1\n" + " - set gpio direction (0 for output, 1 for input)\n" + "sx151x get chip gpio\n" + " - get gpio value\n" + "sx151x set chip gpio 0|1\n" + " - set gpio value\n" + "sx151x reset chip\n" + " - reset chip" +); + +#endif /* CONFIG_CMD_SX151X */ diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c new file mode 100644 index 0000000000..6386835d5d --- /dev/null +++ b/drivers/gpio/tca642x.c @@ -0,0 +1,333 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * Author: Dan Murphy + * + * Derived work from the pca953x.c driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* tca642x register address definitions */ +struct tca642x_bank_info tca642x_regs[] = { + { .input_reg = 0x00, + .output_reg = 0x04, + .polarity_reg = 0x08, + .configuration_reg = 0x0c }, + { .input_reg = 0x01, + .output_reg = 0x05, + .polarity_reg = 0x09, + .configuration_reg = 0x0d }, + { .input_reg = 0x02, + .output_reg = 0x06, + .polarity_reg = 0x0a, + .configuration_reg = 0x0e }, +}; + +/* + * Modify masked bits in register + */ +static int tca642x_reg_write(uchar chip, uint8_t addr, + uint8_t reg_bit, uint8_t data) +{ + uint8_t valw; + int org_bus_num; + int ret; + + org_bus_num = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + + if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) { + printf("Could not read before writing\n"); + ret = -1; + goto error; + } + valw &= ~reg_bit; + valw |= data; + + ret = i2c_write(chip, addr, 1, (u8 *)&valw, 1); + +error: + i2c_set_bus_num(org_bus_num); + return ret; +} + +static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data) +{ + uint8_t valw; + int org_bus_num; + int ret = 0; + + org_bus_num = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) { + ret = -1; + goto error; + } + + *data = valw; + +error: + i2c_set_bus_num(org_bus_num); + return ret; +} + +/* + * Set output value of IO pins in 'reg_bit' to corresponding value in 'data' + * 0 = low, 1 = high + */ +int tca642x_set_val(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data) +{ + uint8_t out_reg = tca642x_regs[gpio_bank].output_reg; + + return tca642x_reg_write(chip, out_reg, reg_bit, data); +} + +/* + * Set read polarity of IO pins in 'reg_bit' to corresponding value in 'data' + * 0 = read pin value, 1 = read inverted pin value + */ +int tca642x_set_pol(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data) +{ + uint8_t pol_reg = tca642x_regs[gpio_bank].polarity_reg; + + return tca642x_reg_write(chip, pol_reg, reg_bit, data); +} + +/* + * Set direction of IO pins in 'reg_bit' to corresponding value in 'data' + * 0 = output, 1 = input + */ +int tca642x_set_dir(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data) +{ + uint8_t config_reg = tca642x_regs[gpio_bank].configuration_reg; + + return tca642x_reg_write(chip, config_reg, reg_bit, data); +} + +/* + * Read current logic level of all IO pins + */ +int tca642x_get_val(uchar chip, uint8_t gpio_bank) +{ + uint8_t val; + uint8_t in_reg = tca642x_regs[gpio_bank].input_reg; + + if (tca642x_reg_read(chip, in_reg, &val) < 0) + return -1; + + return (int)val; +} + +/* + * Set the inital register states for the tca642x gpio expander + */ +int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]) +{ + int i, ret; + uint8_t config_reg; + uint8_t polarity_reg; + uint8_t output_reg; + + for (i = 0; i < 3; i++) { + config_reg = tca642x_regs[i].configuration_reg; + ret = tca642x_reg_write(chip, config_reg, 0xff, + init_data[i].configuration_reg); + polarity_reg = tca642x_regs[i].polarity_reg; + ret = tca642x_reg_write(chip, polarity_reg, 0xff, + init_data[i].polarity_reg); + output_reg = tca642x_regs[i].output_reg; + ret = tca642x_reg_write(chip, output_reg, 0xff, + init_data[i].output_reg); + } + + return ret; +} + +#ifdef CONFIG_CMD_TCA642X +/* + * Display tca642x information + */ +static int tca642x_info(uchar chip) +{ + int i, j; + uint8_t data; + + printf("tca642x@ 0x%x (%d pins):\n", chip, 24); + for (i = 0; i < 3; i++) { + printf("Bank %i\n", i); + if (tca642x_reg_read(chip, + tca642x_regs[i].configuration_reg, + &data) < 0) + return -1; + printf("\tConfiguration: "); + for (j = 7; j >= 0; j--) + printf("%c", data & (1 << j) ? 'i' : 'o'); + printf("\n"); + + if (tca642x_reg_read(chip, + tca642x_regs[i].polarity_reg, &data) < 0) + return -1; + printf("\tPolarity: "); + for (j = 7; j >= 0; j--) + printf("%c", data & (1 << j) ? '1' : '0'); + printf("\n"); + + if (tca642x_reg_read(chip, + tca642x_regs[i].input_reg, &data) < 0) + return -1; + printf("\tInput value: "); + for (j = 7; j >= 0; j--) + printf("%c", data & (1 << j) ? '1' : '0'); + printf("\n"); + + if (tca642x_reg_read(chip, + tca642x_regs[i].output_reg, &data) < 0) + return -1; + printf("\tOutput value: "); + for (j = 7; j >= 0; j--) + printf("%c", data & (1 << j) ? '1' : '0'); + printf("\n"); + } + + return 0; +} + +cmd_tbl_t cmd_tca642x[] = { + U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""), + U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""), + U_BOOT_CMD_MKENT(input, 3, 0, (void *)TCA642X_CMD_INPUT, "", ""), + U_BOOT_CMD_MKENT(invert, 4, 0, (void *)TCA642X_CMD_INVERT, "", ""), + U_BOOT_CMD_MKENT(info, 2, 0, (void *)TCA642X_CMD_INFO, "", ""), +}; + +int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR; + int ret = CMD_RET_USAGE, val; + uint8_t gpio_bank = 0; + uint8_t bank_shift; + ulong ul_arg2 = 0; + ulong ul_arg3 = 0; + cmd_tbl_t *c; + + c = find_cmd_tbl(argv[1], cmd_tca642x, ARRAY_SIZE(cmd_tca642x)); + + /* All commands but "device" require 'maxargs' arguments */ + if (!c || + !((argc == (c->maxargs)) || + (((int)c->cmd == TCA642X_CMD_DEVICE) && + (argc == (c->maxargs - 1))))) { + return CMD_RET_USAGE; + } + + /* arg2 used as chip number or pin number */ + if (argc > 2) + ul_arg2 = simple_strtoul(argv[2], NULL, 10); + + /* arg3 used as pin or invert value */ + if (argc > 3) { + ul_arg3 = simple_strtoul(argv[3], NULL, 10) & 0x1; + if (ul_arg2 <= 7) { + gpio_bank = 0; + } else if ((ul_arg2 >= 10) && (ul_arg2 <= 17)) { + gpio_bank = 1; + } else if ((ul_arg2 >= 20) && (ul_arg2 <= 27)) { + gpio_bank = 2; + } else { + printf("Requested pin is not available\n"); + ret = CMD_RET_FAILURE; + goto error; + } + } + + switch ((int)c->cmd) { + case TCA642X_CMD_INFO: + ret = tca642x_info(chip); + if (ret) + ret = CMD_RET_FAILURE; + break; + + case TCA642X_CMD_DEVICE: + if (argc == 3) + chip = (uint8_t)ul_arg2; + printf("Current device address: 0x%x\n", chip); + ret = CMD_RET_SUCCESS; + break; + + case TCA642X_CMD_INPUT: + bank_shift = ul_arg2 - (gpio_bank * 10); + ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift), + TCA642X_DIR_IN << bank_shift); + val = (tca642x_get_val(chip, gpio_bank) & + (1 << bank_shift)) != 0; + + if (ret) + ret = CMD_RET_FAILURE; + else + printf("chip 0x%02x, pin 0x%lx = %d\n", chip, + ul_arg2, val); + break; + + case TCA642X_CMD_OUTPUT: + bank_shift = ul_arg2 - (gpio_bank * 10); + ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift), + (TCA642X_DIR_OUT << bank_shift)); + if (!ret) + ret = tca642x_set_val(chip, + gpio_bank, (1 << bank_shift), + (ul_arg3 << bank_shift)); + if (ret) + ret = CMD_RET_FAILURE; + break; + + case TCA642X_CMD_INVERT: + bank_shift = ul_arg2 - (gpio_bank * 10); + ret = tca642x_set_pol(chip, gpio_bank, (1 << bank_shift), + (ul_arg3 << bank_shift)); + if (ret) + ret = CMD_RET_FAILURE; + break; + } +error: + if (ret == CMD_RET_FAILURE) + eprintf("Error talking to chip at 0x%x\n", chip); + + return ret; +} + +U_BOOT_CMD( + tca642x, 5, 1, do_tca642x, + "tca642x gpio access", + "device [dev]\n" + " - show or set current device address\n" + "tca642x info\n" + " - display info for current chip\n" + "tca642x output pin 0|1\n" + " - set pin as output and drive low or high\n" + "tca642x invert pin 0|1\n" + " - disable/enable polarity inversion for reads\n" + "tca642x input pin\n" + " - set pin as input and read value" +); + +#endif /* CONFIG_CMD_TCA642X */ diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 82b30d5ab6..43928b8812 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -12,10 +12,18 @@ */ #include +#include +#include +#include +#include #include #include #include #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; enum { TEGRA_CMD_INFO, @@ -24,14 +32,17 @@ enum { TEGRA_CMD_INPUT, }; -static struct gpio_names { - char name[GPIO_NAME_SIZE]; -} gpio_names[MAX_NUM_GPIOS]; +struct tegra_gpio_platdata { + struct gpio_ctlr_bank *bank; + const char *port_name; /* Name of port, e.g. "B" */ + int base_gpio; /* Port number for this port (0, 1,.., n-1) */ +}; -static char *get_name(int i) -{ - return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN"; -} +/* Information about each port at run-time */ +struct tegra_port_info { + struct gpio_ctlr_bank *bank; + int base_gpio; /* Port number for this port (0, 1,.., n-1) */ +}; /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ static int get_config(unsigned gpio) @@ -121,69 +132,53 @@ static void set_level(unsigned gpio, int high) writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); } -/* - * Generic_GPIO primitives. - */ - -int gpio_request(unsigned gpio, const char *label) +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +int tegra_spl_gpio_direction_output(int gpio, int value) { - if (gpio >= MAX_NUM_GPIOS) - return -1; - - if (label != NULL) { - strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE); - gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0'; - } - /* Configure as a GPIO */ set_config(gpio, 1); - return 0; -} + /* Configure GPIO output value. */ + set_level(gpio, value); -int gpio_free(unsigned gpio) -{ - if (gpio >= MAX_NUM_GPIOS) - return -1; + /* Configure GPIO direction as output. */ + set_direction(gpio, 1); - gpio_names[gpio].name[0] = '\0'; - /* Do not configure as input or change pin mux here */ return 0; } -/* read GPIO OUT value of pin 'gpio' */ -static int gpio_get_output_value(unsigned gpio) -{ - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; - int val; +/* + * Generic_GPIO primitives. + */ - debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); +static int tegra_gpio_request(struct udevice *dev, unsigned offset, + const char *label) +{ + struct tegra_port_info *state = dev_get_priv(dev); - val = readl(&bank->gpio_out[GPIO_PORT(gpio)]); + /* Configure as a GPIO */ + set_config(state->base_gpio + offset, 1); - return (val >> GPIO_BIT(gpio)) & 1; + return 0; } /* set GPIO pin 'gpio' as an input */ -int gpio_direction_input(unsigned gpio) +static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) { - debug("gpio_direction_input: pin = %d (port %d:bit %d)\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); + struct tegra_port_info *state = dev_get_priv(dev); /* Configure GPIO direction as input. */ - set_direction(gpio, 0); + set_direction(state->base_gpio + offset, 0); return 0; } /* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int gpio_direction_output(unsigned gpio, int value) +static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) { - debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), - value ? "HIGH" : "LOW"); + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; /* Configure GPIO output value. */ set_level(gpio, value); @@ -195,25 +190,28 @@ int gpio_direction_output(unsigned gpio, int value) } /* read GPIO IN value of pin 'gpio' */ -int gpio_get_value(unsigned gpio) +static int tegra_gpio_get_value(struct udevice *dev, unsigned offset) { - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; int val; - debug("gpio_get_value: pin = %d (port %d:bit %d)\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); + debug("%s: pin = %d (port %d:bit %d)\n", __func__, + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - val = readl(&bank->gpio_in[GPIO_PORT(gpio)]); + val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); return (val >> GPIO_BIT(gpio)) & 1; } /* write GPIO OUT value to pin 'gpio' */ -int gpio_set_value(unsigned gpio, int value) +static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value) { + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; + debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); /* Configure GPIO output value. */ set_level(gpio, value); @@ -221,26 +219,173 @@ int gpio_set_value(unsigned gpio, int value) return 0; } -/* - * Display Tegra GPIO information +void gpio_config_table(const struct tegra_gpio_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) { + switch (config[i].init) { + case TEGRA_GPIO_INIT_IN: + gpio_direction_input(config[i].gpio); + break; + case TEGRA_GPIO_INIT_OUT0: + gpio_direction_output(config[i].gpio, 0); + break; + case TEGRA_GPIO_INIT_OUT1: + gpio_direction_output(config[i].gpio, 1); + break; + } + set_config(config[i].gpio, 1); + } +} + +static int tegra_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; + + if (!get_config(gpio)) + return GPIOF_FUNC; + else if (get_direction(gpio)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + int gpio, port, ret; + + gpio = args->args[0]; + port = gpio / TEGRA_GPIOS_PER_PORT; + ret = device_get_child(dev, port, &desc->dev); + if (ret) + return ret; + desc->offset = gpio % TEGRA_GPIOS_PER_PORT; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + +static const struct dm_gpio_ops gpio_tegra_ops = { + .request = tegra_gpio_request, + .direction_input = tegra_gpio_direction_input, + .direction_output = tegra_gpio_direction_output, + .get_value = tegra_gpio_get_value, + .set_value = tegra_gpio_set_value, + .get_function = tegra_gpio_get_function, + .xlate = tegra_gpio_xlate, +}; + +/** + * Returns the name of a GPIO port + * + * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ... + * + * @base_port: Base port number (0, 1..n-1) + * @return allocated string containing the name */ -void gpio_info(void) +static char *gpio_port_name(int base_port) { - unsigned c; - int type; + char *name, *s; + + name = malloc(3); + if (name) { + s = name; + *s++ = 'A' + (base_port % 26); + if (base_port >= 26) + *s++ = *name; + *s = '\0'; + } - for (c = 0; c < MAX_NUM_GPIOS; c++) { - type = get_config(c); /* GPIO, not SFPIO */ - if (type) { - printf("GPIO_%d:\t%s is an %s, ", c, - get_name(c), - get_direction(c) ? "OUTPUT" : "INPUT"); - if (get_direction(c)) - printf("value = %d", gpio_get_output_value(c)); - else - printf("value = %d", gpio_get_value(c)); - printf("\n"); - } else - continue; + return name; +} + +static const struct udevice_id tegra_gpio_ids[] = { + { .compatible = "nvidia,tegra30-gpio" }, + { .compatible = "nvidia,tegra20-gpio" }, + { } +}; + +static int gpio_tegra_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct tegra_port_info *priv = dev->priv; + struct tegra_gpio_platdata *plat = dev->platdata; + + /* Only child devices have ports */ + if (!plat) + return 0; + + priv->bank = plat->bank; + priv->base_gpio = plat->base_gpio; + + uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT; + uc_priv->bank_name = plat->port_name; + + return 0; +} + +/** + * We have a top-level GPIO device with no actual GPIOs. It has a child + * device for each Tegra port. + */ +static int gpio_tegra_bind(struct udevice *parent) +{ + struct tegra_gpio_platdata *plat = parent->platdata; + struct gpio_ctlr *ctlr; + int bank_count; + int bank; + int ret; + int len; + + /* If this is a child device, there is nothing to do here */ + if (plat) + return 0; + + /* + * This driver does not make use of interrupts, other than to figure + * out the number of GPIO banks + */ + if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len)) + return -EINVAL; + bank_count = len / 3 / sizeof(u32); + ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob, + parent->of_offset, "reg"); + for (bank = 0; bank < bank_count; bank++) { + int port; + + for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) { + struct tegra_gpio_platdata *plat; + struct udevice *dev; + int base_port; + + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + plat->bank = &ctlr->gpio_bank[bank]; + base_port = bank * TEGRA_PORTS_PER_BANK + port; + plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; + plat->port_name = gpio_port_name(base_port); + + ret = device_bind(parent, parent->driver, + plat->port_name, plat, -1, &dev); + if (ret) + return ret; + dev->of_offset = parent->of_offset; + } } + + return 0; } + +U_BOOT_DRIVER(gpio_tegra) = { + .name = "gpio_tegra", + .id = UCLASS_GPIO, + .of_match = tegra_gpio_ids, + .bind = gpio_tegra_bind, + .probe = gpio_tegra_probe, + .priv_auto_alloc_size = sizeof(struct tegra_port_info), + .ops = &gpio_tegra_ops, +}; diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 6e203a34a2..25b8e8a2d7 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -8,36 +8,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -#CFLAGS += -DDEBUG - -LIB = $(obj)libhwmon.o - -COBJS-$(CONFIG_DTT_ADM1021) += adm1021.o -COBJS-$(CONFIG_DTT_ADT7460) += adt7460.o -COBJS-$(CONFIG_DTT_DS1621) += ds1621.o -COBJS-$(CONFIG_DTT_DS1722) += ds1722.o -COBJS-$(CONFIG_DTT_DS1775) += ds1775.o -COBJS-$(CONFIG_DTT_LM63) += lm63.o -COBJS-$(CONFIG_DTT_LM73) += lm73.o -COBJS-$(CONFIG_DTT_LM75) += lm75.o -COBJS-$(CONFIG_DTT_LM81) += lm81.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +#ccflags-y += -DDEBUG + +obj-$(CONFIG_DTT_ADM1021) += adm1021.o +obj-$(CONFIG_DTT_ADT7460) += adt7460.o +obj-$(CONFIG_DTT_DS1621) += ds1621.o +obj-$(CONFIG_DTT_DS1722) += ds1722.o +obj-$(CONFIG_DTT_DS1775) += ds1775.o +obj-$(CONFIG_DTT_LM63) += lm63.o +obj-$(CONFIG_DTT_LM73) += lm73.o +obj-$(CONFIG_DTT_LM75) += lm75.o +obj-$(CONFIG_DTT_LM81) += lm81.o diff --git a/drivers/hwmon/ds1722.c b/drivers/hwmon/ds1722.c index a46cd4dfb5..c46958846c 100644 --- a/drivers/hwmon/ds1722.c +++ b/drivers/hwmon/ds1722.c @@ -1,4 +1,3 @@ - #include #include #include diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig new file mode 100644 index 0000000000..c3e8d226ac --- /dev/null +++ b/drivers/i2c/Kconfig @@ -0,0 +1,36 @@ +config DM_I2C + bool "Enable Driver Model for I2C drivers" + depends on DM + help + If you want to use driver model for I2C drivers, say Y. + To use legacy I2C drivers, say N. + +config SYS_I2C_UNIPHIER + bool "UniPhier I2C driver" + depends on ARCH_UNIPHIER && DM_I2C + default y + help + Support for Panasonic UniPhier I2C controller driver. This I2C + controller is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. + +config SYS_I2C_UNIPHIER_F + bool "UniPhier FIFO-builtin I2C driver" + depends on ARCH_UNIPHIER && DM_I2C + default y + help + Support for Panasonic UniPhier FIFO-builtin I2C controller driver. + This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. +menuconfig SYS_I2C + bool "I2C device support" + +if SYS_I2C + +config HARD_I2C + bool + +config SYS_I2C_MXC + bool "Freescale i.MX I2C controller" + select HARD_I2C + select I2C_QUIRK_REG if FSL_LSCH3 || SOC_LS102XA + +endif diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 37ccbd1423..774bc94a4a 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -4,50 +4,34 @@ # # SPDX-License-Identifier: GPL-2.0+ # - -include $(TOPDIR)/config.mk - -LIB := $(obj)libi2c.o - -COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o -COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o -COBJS-$(CONFIG_DW_I2C) += designware_i2c.o -COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o -COBJS-$(CONFIG_I2C_MV) += mv_i2c.o -COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o -COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o -COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o -COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o -COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o -COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o -COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o -COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o -COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o -COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o -COBJS-$(CONFIG_SH_I2C) += sh_i2c.o -COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o -COBJS-$(CONFIG_SYS_I2C) += i2c_core.o -COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o -COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o -COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o -COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o -COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o -COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_DM_I2C) += i2c-uclass.o +obj-$(CONFIG_DM_I2C_COMPAT) += i2c-uclass-compat.o + +obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o +obj-$(CONFIG_I2C_MV) += mv_i2c.o +obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o +obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o +obj-$(CONFIG_U8500_I2C) += u8500_i2c.o +obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o +obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o +obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o +obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o +obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o +obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o +obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o +obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o +obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o +obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o +obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o +obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o +obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o +obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o +obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o +obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o +obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o +obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o +obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o +obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o +obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o +obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c new file mode 100644 index 0000000000..20495b1d7f --- /dev/null +++ b/drivers/i2c/adi_i2c.c @@ -0,0 +1,305 @@ +/* + * i2c.c - driver for ADI TWI/I2C + * + * Copyright (c) 2006-2014 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include + +#include +#include +#include + +static struct twi_regs *i2c_get_base(struct i2c_adapter *adap); + +/* Every register is 32bit aligned, but only 16bits in size */ +#define ureg(name) u16 name; u16 __pad_##name; +struct twi_regs { + ureg(clkdiv); + ureg(control); + ureg(slave_ctl); + ureg(slave_stat); + ureg(slave_addr); + ureg(master_ctl); + ureg(master_stat); + ureg(master_addr); + ureg(int_stat); + ureg(int_mask); + ureg(fifo_ctl); + ureg(fifo_stat); + char __pad[0x50]; + ureg(xmt_data8); + ureg(xmt_data16); + ureg(rcv_data8); + ureg(rcv_data16); +}; +#undef ureg + +#ifdef TWI_CLKDIV +#define TWI0_CLKDIV TWI_CLKDIV +# ifdef CONFIG_SYS_MAX_I2C_BUS +# undef CONFIG_SYS_MAX_I2C_BUS +# endif +#define CONFIG_SYS_MAX_I2C_BUS 1 +#endif + +/* + * The way speed is changed into duty often results in integer truncation + * with 50% duty, so we'll force rounding up to the next duty by adding 1 + * to the max. In practice this will get us a speed of something like + * 385 KHz. The other limit is easy to handle as it is only 8 bits. + */ +#define I2C_SPEED_MAX 400000 +#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) +#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) +#define I2C_DUTY_MIN 0xff /* 8 bit limited */ +#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) +/* Note: duty is inverse of speed, so the comparisons below are correct */ +#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN +# error "The I2C hardware can only operate 20KHz - 400KHz" +#endif + +/* All transfers are described by this data structure */ +struct i2c_msg { + u8 flags; +#define I2C_M_COMBO 0x4 +#define I2C_M_STOP 0x2 +#define I2C_M_READ 0x1 + int len; /* msg length */ + u8 *buf; /* pointer to msg data */ + int alen; /* addr length */ + u8 *abuf; /* addr buffer */ +}; + +/* Allow msec timeout per ~byte transfer */ +#define I2C_TIMEOUT 10 + +/** + * wait_for_completion - manage the actual i2c transfer + * @msg: the i2c msg + */ +static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg) +{ + u16 int_stat, ctl; + ulong timebase = get_timer(0); + + do { + int_stat = readw(&twi->int_stat); + + if (int_stat & XMTSERV) { + writew(XMTSERV, &twi->int_stat); + if (msg->alen) { + writew(*(msg->abuf++), &twi->xmt_data8); + --msg->alen; + } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { + writew(*(msg->buf++), &twi->xmt_data8); + --msg->len; + } else { + ctl = readw(&twi->master_ctl); + if (msg->flags & I2C_M_COMBO) + writew(ctl | RSTART | MDIR, + &twi->master_ctl); + else + writew(ctl | STOP, &twi->master_ctl); + } + } + if (int_stat & RCVSERV) { + writew(RCVSERV, &twi->int_stat); + if (msg->len) { + *(msg->buf++) = readw(&twi->rcv_data8); + --msg->len; + } else if (msg->flags & I2C_M_STOP) { + ctl = readw(&twi->master_ctl); + writew(ctl | STOP, &twi->master_ctl); + } + } + if (int_stat & MERR) { + writew(MERR, &twi->int_stat); + return msg->len; + } + if (int_stat & MCOMP) { + writew(MCOMP, &twi->int_stat); + if (msg->flags & I2C_M_COMBO && msg->len) { + ctl = readw(&twi->master_ctl); + ctl = (ctl & ~RSTART) | + (min(msg->len, 0xff) << 6) | MEN | MDIR; + writew(ctl, &twi->master_ctl); + } else + break; + } + + /* If we were able to do something, reset timeout */ + if (int_stat) + timebase = get_timer(0); + + } while (get_timer(timebase) < I2C_TIMEOUT); + + return msg->len; +} + +static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr, + int alen, uint8_t *buffer, int len, uint8_t flags) +{ + struct twi_regs *twi = i2c_get_base(adap); + int ret; + u16 ctl; + uchar addr_buffer[] = { + (addr >> 0), + (addr >> 8), + (addr >> 16), + }; + struct i2c_msg msg = { + .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), + .buf = buffer, + .len = len, + .abuf = addr_buffer, + .alen = alen, + }; + + /* wait for things to settle */ + while (readw(&twi->master_stat) & BUSBUSY) + if (ctrlc()) + return 1; + + /* Set Transmit device address */ + writew(chip, &twi->master_addr); + + /* Clear the FIFO before starting things */ + writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl); + writew(0, &twi->fifo_ctl); + + /* prime the pump */ + if (msg.alen) { + len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; + writew(*(msg.abuf++), &twi->xmt_data8); + --msg.alen; + } else if (!(msg.flags & I2C_M_READ) && msg.len) { + writew(*(msg.buf++), &twi->xmt_data8); + --msg.len; + } + + /* clear int stat */ + writew(-1, &twi->master_stat); + writew(-1, &twi->int_stat); + writew(0, &twi->int_mask); + + /* Master enable */ + ctl = readw(&twi->master_ctl); + ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN | + ((msg.flags & I2C_M_READ) ? MDIR : 0); + writew(ctl, &twi->master_ctl); + + /* process the rest */ + ret = wait_for_completion(twi, &msg); + + if (ret) { + ctl = readw(&twi->master_ctl) & ~MEN; + writew(ctl, &twi->master_ctl); + ctl = readw(&twi->control) & ~TWI_ENA; + writew(ctl, &twi->control); + ctl = readw(&twi->control) | TWI_ENA; + writew(ctl, &twi->control); + } + + return ret; +} + +static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct twi_regs *twi = i2c_get_base(adap); + u16 clkdiv = I2C_SPEED_TO_DUTY(speed); + + /* Set TWI interface clock */ + if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) + return -1; + clkdiv = (clkdiv << 8) | (clkdiv & 0xff); + writew(clkdiv, &twi->clkdiv); + + /* Don't turn it on */ + writew(speed > 100000 ? FAST : 0, &twi->master_ctl); + + return 0; +} + +static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +{ + struct twi_regs *twi = i2c_get_base(adap); + u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; + + /* Set TWI internal clock as 10MHz */ + writew(prescale, &twi->control); + + /* Set TWI interface clock as specified */ + i2c_set_bus_speed(speed); + + /* Enable it */ + writew(TWI_ENA | prescale, &twi->control); +} + +static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, int len) +{ + return i2c_transfer(adap, chip, addr, alen, buffer, + len, alen ? I2C_M_COMBO : I2C_M_READ); +} + +static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, int len) +{ + return i2c_transfer(adap, chip, addr, alen, buffer, len, 0); +} + +static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip) +{ + u8 byte; + return adi_i2c_read(adap, chip, 0, 0, &byte, 1); +} + +static struct twi_regs *i2c_get_base(struct i2c_adapter *adap) +{ + switch (adap->hwadapnr) { +#if CONFIG_SYS_MAX_I2C_BUS > 2 + case 2: + return (struct twi_regs *)TWI2_CLKDIV; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 1 + case 1: + return (struct twi_regs *)TWI1_CLKDIV; +#endif + case 0: + return (struct twi_regs *)TWI0_CLKDIV; + + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + } + + return NULL; +} + +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe, + adi_i2c_read, adi_i2c_write, + adi_i2c_setspeed, + CONFIG_SYS_I2C_SPEED, + 0, + 0) + +#if CONFIG_SYS_MAX_I2C_BUS > 1 +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe, + adi_i2c_read, adi_i2c_write, + adi_i2c_setspeed, + CONFIG_SYS_I2C_SPEED, + 0, + 1) +#endif + +#if CONFIG_SYS_MAX_I2C_BUS > 2 +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe, + adi_i2c_read, adi_i2c_write, + adi_i2c_setspeed, + CONFIG_SYS_I2C_SPEED, + 0, + 2) +#endif diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c deleted file mode 100644 index b3a04d3207..0000000000 --- a/drivers/i2c/bfin-twi_i2c.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * i2c.c - driver for Blackfin on-chip TWI/I2C - * - * Copyright (c) 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#include -#include - -/* Every register is 32bit aligned, but only 16bits in size */ -#define ureg(name) u16 name; u16 __pad_##name; -struct twi_regs { - ureg(clkdiv); - ureg(control); - ureg(slave_ctl); - ureg(slave_stat); - ureg(slave_addr); - ureg(master_ctl); - ureg(master_stat); - ureg(master_addr); - ureg(int_stat); - ureg(int_mask); - ureg(fifo_ctl); - ureg(fifo_stat); - char __pad[0x50]; - ureg(xmt_data8); - ureg(xmt_data16); - ureg(rcv_data8); - ureg(rcv_data16); -}; -#undef ureg - -/* U-Boot I2C framework allows only one active device at a time. */ -#ifdef TWI_CLKDIV -#define TWI0_CLKDIV TWI_CLKDIV -#endif -static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV; - -#ifdef DEBUG -# define dmemset(s, c, n) memset(s, c, n) -#else -# define dmemset(s, c, n) -#endif -#define debugi(fmt, args...) \ - debug( \ - "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \ - twi->master_stat, twi->fifo_stat, twi->int_stat, \ - __func__, __LINE__, ## args) - -#ifdef CONFIG_TWICLK_KHZ -# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED -#endif - -/* - * The way speed is changed into duty often results in integer truncation - * with 50% duty, so we'll force rounding up to the next duty by adding 1 - * to the max. In practice this will get us a speed of something like - * 385 KHz. The other limit is easy to handle as it is only 8 bits. - */ -#define I2C_SPEED_MAX 400000 -#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) -#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) -#define I2C_DUTY_MIN 0xff /* 8 bit limited */ -#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) -/* Note: duty is inverse of speed, so the comparisons below are correct */ -#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN -# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" -#endif - -/* All transfers are described by this data structure */ -struct i2c_msg { - u8 flags; -#define I2C_M_COMBO 0x4 -#define I2C_M_STOP 0x2 -#define I2C_M_READ 0x1 - int len; /* msg length */ - u8 *buf; /* pointer to msg data */ - int alen; /* addr length */ - u8 *abuf; /* addr buffer */ -}; - -/* Allow msec timeout per ~byte transfer */ -#define I2C_TIMEOUT 10 - -/** - * wait_for_completion - manage the actual i2c transfer - * @msg: the i2c msg - */ -static int wait_for_completion(struct i2c_msg *msg) -{ - uint16_t int_stat; - ulong timebase = get_timer(0); - - do { - int_stat = twi->int_stat; - - if (int_stat & XMTSERV) { - debugi("processing XMTSERV"); - twi->int_stat = XMTSERV; - SSYNC(); - if (msg->alen) { - twi->xmt_data8 = *(msg->abuf++); - --msg->alen; - } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - twi->xmt_data8 = *(msg->buf++); - --msg->len; - } else { - twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP; - SSYNC(); - } - } - if (int_stat & RCVSERV) { - debugi("processing RCVSERV"); - twi->int_stat = RCVSERV; - SSYNC(); - if (msg->len) { - *(msg->buf++) = twi->rcv_data8; - --msg->len; - } else if (msg->flags & I2C_M_STOP) { - twi->master_ctl |= STOP; - SSYNC(); - } - } - if (int_stat & MERR) { - debugi("processing MERR"); - twi->int_stat = MERR; - SSYNC(); - return msg->len; - } - if (int_stat & MCOMP) { - debugi("processing MCOMP"); - twi->int_stat = MCOMP; - SSYNC(); - if (msg->flags & I2C_M_COMBO && msg->len) { - twi->master_ctl = (twi->master_ctl & ~RSTART) | - (min(msg->len, 0xff) << 6) | MEN | MDIR; - SSYNC(); - } else - break; - } - - /* If we were able to do something, reset timeout */ - if (int_stat) - timebase = get_timer(0); - - } while (get_timer(timebase) < I2C_TIMEOUT); - - return msg->len; -} - -/** - * i2c_transfer - setup an i2c transfer - * @return: 0 if things worked, non-0 if things failed - * - * Here we just get the i2c stuff all prepped and ready, and then tail off - * into wait_for_completion() for all the bits to go. - */ -static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags) -{ - uchar addr_buffer[] = { - (addr >> 0), - (addr >> 8), - (addr >> 16), - }; - struct i2c_msg msg = { - .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), - .buf = buffer, - .len = len, - .abuf = addr_buffer, - .alen = alen, - }; - int ret; - - dmemset(buffer, 0xff, len); - debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ", - chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr")); - - /* wait for things to settle */ - while (twi->master_stat & BUSBUSY) - if (ctrlc()) - return 1; - - /* Set Transmit device address */ - twi->master_addr = chip; - - /* Clear the FIFO before starting things */ - twi->fifo_ctl = XMTFLUSH | RCVFLUSH; - SSYNC(); - twi->fifo_ctl = 0; - SSYNC(); - - /* prime the pump */ - if (msg.alen) { - len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; - debugi("first byte=0x%02x", *msg.abuf); - twi->xmt_data8 = *(msg.abuf++); - --msg.alen; - } else if (!(msg.flags & I2C_M_READ) && msg.len) { - debugi("first byte=0x%02x", *msg.buf); - twi->xmt_data8 = *(msg.buf++); - --msg.len; - } - - /* clear int stat */ - twi->master_stat = -1; - twi->int_stat = -1; - twi->int_mask = 0; - SSYNC(); - - /* Master enable */ - twi->master_ctl = - (twi->master_ctl & FAST) | - (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0); - SSYNC(); - debugi("CTL=0x%04x", twi->master_ctl); - - /* process the rest */ - ret = wait_for_completion(&msg); - debugi("ret=%d", ret); - - if (ret) { - twi->master_ctl &= ~MEN; - twi->control &= ~TWI_ENA; - SSYNC(); - twi->control |= TWI_ENA; - SSYNC(); - } - - return ret; -} - -/** - * i2c_set_bus_speed - set i2c bus speed - * @speed: bus speed (in HZ) - */ -int i2c_set_bus_speed(unsigned int speed) -{ - u16 clkdiv = I2C_SPEED_TO_DUTY(speed); - - /* Set TWI interface clock */ - if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) - return -1; - twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff); - - /* Don't turn it on */ - twi->master_ctl = (speed > 100000 ? FAST : 0); - - return 0; -} - -/** - * i2c_get_bus_speed - get i2c bus speed - * @speed: bus speed (in HZ) - */ -unsigned int i2c_get_bus_speed(void) -{ - /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ - return 5000000 / (twi->clkdiv & 0xff); -} - -/** - * i2c_init - initialize the i2c bus - * @speed: bus speed (in HZ) - * @slaveaddr: address of device in slave mode (0 - not slave) - * - * Slave mode isn't actually implemented. It'll stay that way until - * we get a real request for it. - */ -void i2c_init(int speed, int slaveaddr) -{ - uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F; - - /* Set TWI internal clock as 10MHz */ - twi->control = prescale; - - /* Set TWI interface clock as specified */ - i2c_set_bus_speed(speed); - - /* Enable it */ - twi->control = TWI_ENA | prescale; - SSYNC(); - - debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv); - -#if CONFIG_SYS_I2C_SLAVE -# error I2C slave support not tested/supported - /* If they want us as a slave, do it */ - if (slaveaddr) { - twi->slave_addr = slaveaddr; - twi->slave_ctl = SEN; - } -#endif -} - -/** - * i2c_probe - test if a chip exists at a given i2c address - * @chip: i2c chip addr to search for - * @return: 0 if found, non-0 if not found - */ -int i2c_probe(uchar chip) -{ - u8 byte; - return i2c_read(chip, 0, 0, &byte, 1); -} - -/** - * i2c_read - read data from an i2c device - * @chip: i2c chip addr - * @addr: memory (register) address in the chip - * @alen: byte size of address - * @buffer: buffer to store data read from chip - * @len: how many bytes to read - * @return: 0 on success, non-0 on failure - */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ)); -} - -/** - * i2c_write - write data to an i2c device - * @chip: i2c chip addr - * @addr: memory (register) address in the chip - * @alen: byte size of address - * @buffer: buffer holding data to write to chip - * @len: how many bytes to write - * @return: 0 on success, non-0 on failure - */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - return i2c_transfer(chip, addr, alen, buffer, len, 0); -} - -/** - * i2c_set_bus_num - change active I2C bus - * @bus: bus index, zero based - * @returns: 0 on success, non-0 on failure - */ -int i2c_set_bus_num(unsigned int bus) -{ - switch (bus) { -#if CONFIG_SYS_MAX_I2C_BUS > 0 - case 0: twi = (void *)TWI0_CLKDIV; return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case 1: twi = (void *)TWI1_CLKDIV; return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case 2: twi = (void *)TWI2_CLKDIV; return 0; -#endif - default: return -1; - } -} - -/** - * i2c_get_bus_num - returns index of active I2C bus - */ -unsigned int i2c_get_bus_num(void) -{ - switch ((unsigned long)twi) { -#if CONFIG_SYS_MAX_I2C_BUS > 0 - case TWI0_CLKDIV: return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case TWI1_CLKDIV: return 1; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case TWI2_CLKDIV: return 2; -#endif - default: return -1; - } -} diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index e56fe75b15..9ca99c4abd 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -1,8 +1,9 @@ /* * TI DaVinci (TMS320DM644x) I2C driver. * - * Copyright (C) 2007 Sergey Kubushyn - * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * (C) Copyright 2007 Sergey Kubushyn * -------------------------------------------------------- * * SPDX-License-Identifier: GPL-2.0+ @@ -12,305 +13,372 @@ #include #include #include +#include +#include "davinci_i2c.h" #define CHECK_NACK() \ do {\ if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ - REG(I2C_CON) = 0;\ - return(1);\ - }\ + REG(&(i2c_base->i2c_con)) = 0;\ + return 1;\ + } \ } while (0) +static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap); -static int wait_for_bus(void) +static int wait_for_bus(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int stat, timeout; - REG(I2C_STAT) = 0xffff; + REG(&(i2c_base->i2c_stat)) = 0xffff; for (timeout = 0; timeout < 10; timeout++) { - if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { - REG(I2C_STAT) = 0xffff; - return(0); + stat = REG(&(i2c_base->i2c_stat)); + if (!((stat) & I2C_STAT_BB)) { + REG(&(i2c_base->i2c_stat)) = 0xffff; + return 0; } - REG(I2C_STAT) = stat; + REG(&(i2c_base->i2c_stat)) = stat; udelay(50000); } - REG(I2C_STAT) = 0xffff; - return(1); + REG(&(i2c_base->i2c_stat)) = 0xffff; + return 1; } -static int poll_i2c_irq(int mask) +static int poll_i2c_irq(struct i2c_adapter *adap, int mask) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int stat, timeout; for (timeout = 0; timeout < 10; timeout++) { udelay(1000); - stat = REG(I2C_STAT); - if (stat & mask) { - return(stat); - } + stat = REG(&(i2c_base->i2c_stat)); + if (stat & mask) + return stat; } - REG(I2C_STAT) = 0xffff; - return(stat | I2C_TIMEOUT); + REG(&(i2c_base->i2c_stat)) = 0xffff; + return stat | I2C_TIMEOUT; } - -void flush_rx(void) +static void flush_rx(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = davinci_get_base(adap); + while (1) { - if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) + if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY)) break; - REG(I2C_DRR); - REG(I2C_STAT) = I2C_STAT_RRDY; + REG(&(i2c_base->i2c_drr)); + REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY; udelay(1000); } } +static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t div, psc; + + psc = 2; + /* SCLL + SCLH */ + div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; + REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */ + REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */ + REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); + + adap->speed = speed; + return 0; +} -void i2c_init(int speed, int slaveadd) +static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { - u_int32_t div, psc; + struct i2c_regs *i2c_base = davinci_get_base(adap); - if (REG(I2C_CON) & I2C_CON_EN) { - REG(I2C_CON) = 0; - udelay (50000); + if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) { + REG(&(i2c_base->i2c_con)) = 0; + udelay(50000); } - psc = 2; - div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ - REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ - REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ - REG(I2C_SCLH) = div - REG(I2C_SCLL); + davinci_i2c_setspeed(adap, speed); - REG(I2C_OA) = slaveadd; - REG(I2C_CNT) = 0; + REG(&(i2c_base->i2c_oa)) = slaveadd; + REG(&(i2c_base->i2c_cnt)) = 0; /* Interrupts must be enabled or I2C module won't work */ - REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | + REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; /* Now enable I2C controller (get it out of reset) */ - REG(I2C_CON) = I2C_CON_EN; + REG(&(i2c_base->i2c_con)) = I2C_CON_EN; udelay(1000); } -int i2c_set_bus_speed(unsigned int speed) -{ - i2c_init(speed, CONFIG_SYS_I2C_SLAVE); - return 0; -} - -int i2c_probe(u_int8_t chip) +static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int rc = 1; - if (chip == REG(I2C_OA)) { - return(rc); - } + if (chip == REG(&(i2c_base->i2c_oa))) + return rc; - REG(I2C_CON) = 0; - if (wait_for_bus()) {return(1);} + REG(&(i2c_base->i2c_con)) = 0; + if (wait_for_bus(adap)) + return 1; /* try to read one byte from current (or only) address */ - REG(I2C_CNT) = 1; - REG(I2C_SA) = chip; - REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); - udelay (50000); + REG(&(i2c_base->i2c_cnt)) = 1; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_STP); + udelay(50000); - if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { + if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) { rc = 0; - flush_rx(); - REG(I2C_STAT) = 0xffff; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; } else { - REG(I2C_STAT) = 0xffff; - REG(I2C_CON) |= I2C_CON_STP; + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_con)) |= I2C_CON_STP; udelay(20000); - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - return(rc); + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + return rc; } - -int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint32_t addr, int alen, uint8_t *buf, int len) { - u_int32_t tmp; + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t tmp; int i; if ((alen < 0) || (alen > 2)) { - printf("%s(): bogus address length %x\n", __FUNCTION__, alen); - return(1); + printf("%s(): bogus address length %x\n", __func__, alen); + return 1; } - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; if (alen != 0) { /* Start address phase */ tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; - REG(I2C_CNT) = alen; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + REG(&(i2c_base->i2c_cnt)) = alen; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); CHECK_NACK(); switch (alen) { - case 2: - /* Send address MSByte */ - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = (addr >> 8) & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); - - CHECK_NACK(); - /* No break, fall through */ - case 1: - /* Send address LSByte */ - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = addr & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); - - CHECK_NACK(); - - if (!(tmp & I2C_STAT_ARDY)) { - REG(I2C_CON) = 0; - return(1); - } + case 2: + /* Send address MSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + /* No break, fall through */ + case 1: + /* Send address LSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = addr & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | + I2C_STAT_NACK | I2C_STAT_ARDY); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_ARDY)) { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } } } /* Address phase is over, now read 'len' bytes and stop */ tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; - REG(I2C_CNT) = len & 0xffff; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + REG(&(i2c_base->i2c_cnt)) = len & 0xffff; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; for (i = 0; i < len; i++) { - tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); + tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK | + I2C_STAT_ROVR); CHECK_NACK(); if (tmp & I2C_STAT_RRDY) { - buf[i] = REG(I2C_DRR); + buf[i] = REG(&(i2c_base->i2c_drr)); } else { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } } - tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK); CHECK_NACK(); if (!(tmp & I2C_STAT_SCD)) { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - REG(I2C_CON) = 0; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + REG(&(i2c_base->i2c_con)) = 0; - return(0); + return 0; } - -int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip, + uint32_t addr, int alen, uint8_t *buf, int len) { - u_int32_t tmp; + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t tmp; int i; if ((alen < 0) || (alen > 2)) { - printf("%s(): bogus address length %x\n", __FUNCTION__, alen); - return(1); + printf("%s(): bogus address length %x\n", __func__, alen); + return 1; } if (len < 0) { - printf("%s(): bogus length %x\n", __FUNCTION__, len); - return(1); + printf("%s(): bogus length %x\n", __func__, len); + return 1; } - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; /* Start address phase */ - tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; - REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_TRX | I2C_CON_STP; + REG(&(i2c_base->i2c_cnt)) = (alen == 0) ? + len & 0xffff : (len & 0xffff) + alen; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; switch (alen) { - case 2: - /* Send address MSByte */ - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + case 2: + /* Send address MSByte */ + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); - CHECK_NACK(); + CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = (addr >> 8) & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - /* No break, fall through */ - case 1: - /* Send address LSByte */ - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + /* No break, fall through */ + case 1: + /* Send address LSByte */ + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); - CHECK_NACK(); + CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = addr & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = addr & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } } for (i = 0; i < len; i++) { - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = buf[i]; - } else { - return(1); - } + if (tmp & I2C_STAT_XRDY) + REG(&(i2c_base->i2c_dxr)) = buf[i]; + else + return 1; } - tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK); CHECK_NACK(); if (!(tmp & I2C_STAT_SCD)) { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - REG(I2C_CON) = 0; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + REG(&(i2c_base->i2c_con)) = 0; + + return 0; +} + +static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap) +{ + switch (adap->hwadapnr) { +#if I2C_BUS_MAX >= 3 + case 2: + return (struct i2c_regs *)I2C2_BASE; +#endif +#if I2C_BUS_MAX >= 2 + case 1: + return (struct i2c_regs *)I2C1_BASE; +#endif + case 0: + return (struct i2c_regs *)I2C_BASE; + + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + } - return(0); + return NULL; } + +U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED, + CONFIG_SYS_DAVINCI_I2C_SLAVE, + 0) + +#if I2C_BUS_MAX >= 2 +U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED1, + CONFIG_SYS_DAVINCI_I2C_SLAVE1, + 1) +#endif + +#if I2C_BUS_MAX >= 3 +U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED2, + CONFIG_SYS_DAVINCI_I2C_SLAVE2, + 2) +#endif diff --git a/drivers/i2c/davinci_i2c.h b/drivers/i2c/davinci_i2c.h new file mode 100644 index 0000000000..20d43424b9 --- /dev/null +++ b/drivers/i2c/davinci_i2c.h @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2004-2014 + * Texas Instruments, + * + * Some changes copyright (C) 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _DAVINCI_I2C_H_ +#define _DAVINCI_I2C_H_ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +struct i2c_regs { + u32 i2c_oa; + u32 i2c_ie; + u32 i2c_stat; + u32 i2c_scll; + u32 i2c_sclh; + u32 i2c_cnt; + u32 i2c_drr; + u32 i2c_sa; + u32 i2c_dxr; + u32 i2c_con; + u32 i2c_iv; + u32 res_2c; + u32 i2c_psc; +}; + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ +#define I2C_INTCODE_SCD 6 /* Stop condition detect */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 5) /* I2C module enable */ +#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ +#define I2C_CON_FREE (1 << 14) /* Free run on emulation */ + +#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ + +#endif diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index c2f06627d3..e768cdedb0 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -6,17 +6,33 @@ */ #include +#include #include -#include #include "designware_i2c.h" -#ifdef CONFIG_I2C_MULTI_BUS -static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX]; -static unsigned int current_bus = 0; +static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) +{ + switch (adap->hwadapnr) { +#if CONFIG_SYS_I2C_BUS_MAX >= 4 + case 3: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3; +#endif +#if CONFIG_SYS_I2C_BUS_MAX >= 3 + case 2: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2; +#endif +#if CONFIG_SYS_I2C_BUS_MAX >= 2 + case 1: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1; #endif + case 0: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE; + default: + printf("Wrong I2C-adapter number %d\n", adap->hwadapnr); + } -static struct i2c_regs *i2c_regs_p = - (struct i2c_regs *)CONFIG_SYS_I2C_BASE; + return NULL; +} /* * set_speed - Set the i2c speed mode (standard, high, fast) @@ -24,51 +40,52 @@ static struct i2c_regs *i2c_regs_p = * * Set the i2c speed mode (standard, high, fast) */ -static void set_speed(int i2c_spd) +static void set_speed(struct i2c_adapter *adap, int i2c_spd) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int cntl; unsigned int hcnt, lcnt; unsigned int enbl; /* to set speed cltr must be disabled */ - enbl = readl(&i2c_regs_p->ic_enable); + enbl = readl(&i2c_base->ic_enable); enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); + writel(enbl, &i2c_base->ic_enable); - cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK)); + cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); switch (i2c_spd) { case IC_SPEED_MODE_MAX: cntl |= IC_CON_SPD_HS; hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; - writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt); + writel(hcnt, &i2c_base->ic_hs_scl_hcnt); lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; - writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt); + writel(lcnt, &i2c_base->ic_hs_scl_lcnt); break; case IC_SPEED_MODE_STANDARD: cntl |= IC_CON_SPD_SS; hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; - writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt); + writel(hcnt, &i2c_base->ic_ss_scl_hcnt); lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; - writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt); + writel(lcnt, &i2c_base->ic_ss_scl_lcnt); break; case IC_SPEED_MODE_FAST: default: cntl |= IC_CON_SPD_FS; hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; - writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt); + writel(hcnt, &i2c_base->ic_fs_scl_hcnt); lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; - writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt); + writel(lcnt, &i2c_base->ic_fs_scl_lcnt); break; } - writel(cntl, &i2c_regs_p->ic_con); + writel(cntl, &i2c_base->ic_con); /* Enable back i2c now speed set */ enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); + writel(enbl, &i2c_base->ic_enable); } /* @@ -77,35 +94,20 @@ static void set_speed(int i2c_spd) * * Set the i2c speed. */ -int i2c_set_bus_speed(int speed) +static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) { + int i2c_spd; + if (speed >= I2C_MAX_SPEED) - set_speed(IC_SPEED_MODE_MAX); + i2c_spd = IC_SPEED_MODE_MAX; else if (speed >= I2C_FAST_SPEED) - set_speed(IC_SPEED_MODE_FAST); + i2c_spd = IC_SPEED_MODE_FAST; else - set_speed(IC_SPEED_MODE_STANDARD); + i2c_spd = IC_SPEED_MODE_STANDARD; - return 0; -} - -/* - * i2c_get_bus_speed - Gets the i2c speed - * - * Gets the i2c speed. - */ -int i2c_get_bus_speed(void) -{ - u32 cntl; - - cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK); - - if (cntl == IC_CON_SPD_HS) - return I2C_MAX_SPEED; - else if (cntl == IC_CON_SPD_FS) - return I2C_FAST_SPEED; - else if (cntl == IC_CON_SPD_SS) - return I2C_STANDARD_SPEED; + set_speed(adap, i2c_spd); + adap->speed = speed; return 0; } @@ -113,34 +115,32 @@ int i2c_get_bus_speed(void) /* * i2c_init - Init function * @speed: required i2c speed - * @slaveadd: slave address for the device + * @slaveaddr: slave address for the device * * Initialization function. */ -void i2c_init(int speed, int slaveadd) +static void dw_i2c_init(struct i2c_adapter *adap, int speed, + int slaveaddr) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int enbl; /* Disable i2c */ - enbl = readl(&i2c_regs_p->ic_enable); + enbl = readl(&i2c_base->ic_enable); enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); + writel(enbl, &i2c_base->ic_enable); - writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con); - writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl); - writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl); - i2c_set_bus_speed(speed); - writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask); - writel(slaveadd, &i2c_regs_p->ic_sar); + writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); + writel(IC_RX_TL, &i2c_base->ic_rx_tl); + writel(IC_TX_TL, &i2c_base->ic_tx_tl); + dw_i2c_set_bus_speed(adap, speed); + writel(IC_STOP_DET, &i2c_base->ic_intr_mask); + writel(slaveaddr, &i2c_base->ic_sar); /* Enable i2c */ - enbl = readl(&i2c_regs_p->ic_enable); + enbl = readl(&i2c_base->ic_enable); enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_regs_p->ic_enable); - -#ifdef CONFIG_I2C_MULTI_BUS - bus_initialized[current_bus] = 1; -#endif + writel(enbl, &i2c_base->ic_enable); } /* @@ -149,9 +149,22 @@ void i2c_init(int speed, int slaveadd) * * Sets the target slave address. */ -static void i2c_setaddress(unsigned int i2c_addr) +static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr) { - writel(i2c_addr, &i2c_regs_p->ic_tar); + struct i2c_regs *i2c_base = i2c_get_base(adap); + unsigned int enbl; + + /* Disable i2c */ + enbl = readl(&i2c_base->ic_enable); + enbl &= ~IC_ENABLE_0B; + writel(enbl, &i2c_base->ic_enable); + + writel(i2c_addr, &i2c_base->ic_tar); + + /* Enable i2c */ + enbl = readl(&i2c_base->ic_enable); + enbl |= IC_ENABLE_0B; + writel(enbl, &i2c_base->ic_enable); } /* @@ -159,10 +172,12 @@ static void i2c_setaddress(unsigned int i2c_addr) * * Flushes the i2c RX FIFO */ -static void i2c_flush_rxfifo(void) +static void i2c_flush_rxfifo(struct i2c_adapter *adap) { - while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) - readl(&i2c_regs_p->ic_cmd_data); + struct i2c_regs *i2c_base = i2c_get_base(adap); + + while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) + readl(&i2c_base->ic_cmd_data); } /* @@ -170,12 +185,13 @@ static void i2c_flush_rxfifo(void) * * Waits for bus busy */ -static int i2c_wait_for_bb(void) +static int i2c_wait_for_bb(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned long start_time_bb = get_timer(0); - while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) || - !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) { + while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) || + !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) { /* Evaluate timeout */ if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) @@ -185,60 +201,44 @@ static int i2c_wait_for_bb(void) return 0; } -/* check parameters for i2c_read and i2c_write */ -static int check_params(uint addr, int alen, uchar *buffer, int len) +static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr, + int alen) { - if (buffer == NULL) { - printf("Buffer is invalid\n"); - return 1; - } + struct i2c_regs *i2c_base = i2c_get_base(adap); - if (alen > 1) { - printf("addr len %d not supported\n", alen); + if (i2c_wait_for_bb(adap)) return 1; - } - if (addr + len > 256) { - printf("address out of range\n"); - return 1; + i2c_setaddress(adap, chip); + while (alen) { + alen--; + /* high byte address going out first */ + writel((addr >> (alen * 8)) & 0xff, + &i2c_base->ic_cmd_data); } - return 0; } -static int i2c_xfer_init(uchar chip, uint addr) -{ - if (i2c_wait_for_bb()) - return 1; - - i2c_setaddress(chip); - writel(addr, &i2c_regs_p->ic_cmd_data); - - return 0; -} - -static int i2c_xfer_finish(void) +static int i2c_xfer_finish(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = i2c_get_base(adap); ulong start_stop_det = get_timer(0); while (1) { - if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) { - readl(&i2c_regs_p->ic_clr_stop_det); + if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) { + readl(&i2c_base->ic_clr_stop_det); break; } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { break; } } - if (i2c_wait_for_bb()) { + if (i2c_wait_for_bb(adap)) { printf("Timed out waiting for bus\n"); return 1; } - i2c_flush_rxfifo(); - - /* Wait for read/write operation to complete on actual memory */ - udelay(10000); + i2c_flush_rxfifo(adap); return 0; } @@ -253,25 +253,43 @@ static int i2c_xfer_finish(void) * * Read from i2c memory. */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *buffer, int len) { + struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned long start_time_rx; - if (check_params(addr, alen, buffer, len)) - return 1; +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); - if (i2c_xfer_init(chip, addr)) + debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, + addr); +#endif + + if (i2c_xfer_init(adap, dev, addr, alen)) return 1; start_time_rx = get_timer(0); while (len) { if (len == 1) - writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data); + writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); else - writel(IC_CMD, &i2c_regs_p->ic_cmd_data); + writel(IC_CMD, &i2c_base->ic_cmd_data); - if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) { - *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data); + if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) { + *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data); len--; start_time_rx = get_timer(0); @@ -280,7 +298,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } } - return i2c_xfer_finish(); + return i2c_xfer_finish(adap); } /* @@ -293,24 +311,44 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * * Write to i2c memory. */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *buffer, int len) { + struct i2c_regs *i2c_base = i2c_get_base(adap); int nb = len; unsigned long start_time_tx; - if (check_params(addr, alen, buffer, len)) - return 1; +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); - if (i2c_xfer_init(chip, addr)) + debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, + addr); +#endif + + if (i2c_xfer_init(adap, dev, addr, alen)) return 1; start_time_tx = get_timer(0); while (len) { - if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) { - if (--len == 0) - writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data); - else - writel(*buffer, &i2c_regs_p->ic_cmd_data); + if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) { + if (--len == 0) { + writel(*buffer | IC_STOP, + &i2c_base->ic_cmd_data); + } else { + writel(*buffer, &i2c_base->ic_cmd_data); + } buffer++; start_time_tx = get_timer(0); @@ -320,13 +358,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } } - return i2c_xfer_finish(); + return i2c_xfer_finish(adap); } /* * i2c_probe - Probe the i2c chip */ -int i2c_probe(uchar chip) +static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev) { u32 tmp; int ret; @@ -334,80 +372,31 @@ int i2c_probe(uchar chip) /* * Try to read the first location of the chip. */ - ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1); if (ret) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + dw_i2c_init(adap, adap->speed, adap->slaveaddr); return ret; } -#ifdef CONFIG_I2C_MULTI_BUS -int i2c_set_bus_num(unsigned int bus) -{ - switch (bus) { - case 0: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE; - break; -#ifdef CONFIG_SYS_I2C_BASE1 - case 1: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE2 - case 2: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE3 - case 3: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE4 - case 4: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE5 - case 5: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE6 - case 6: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE7 - case 7: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE8 - case 8: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8; - break; -#endif -#ifdef CONFIG_SYS_I2C_BASE9 - case 9: - i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9; - break; -#endif - default: - printf("Bad bus: %d\n", bus); - return -1; - } +U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read, + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) - current_bus = bus; - - if (!bus_initialized[current_bus]) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#if CONFIG_SYS_I2C_BUS_MAX >= 2 +U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read, + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1) +#endif - return 0; -} +#if CONFIG_SYS_I2C_BUS_MAX >= 3 +U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read, + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2) +#endif -int i2c_get_bus_num(void) -{ - return current_bus; -} +#if CONFIG_SYS_I2C_BUS_MAX >= 4 +U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) #endif diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 38455e1c66..ff7f25a0ef 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -38,7 +38,7 @@ * generic value. */ #ifndef CONFIG_I2C_TIMEOUT -#define CONFIG_I2C_TIMEOUT 10000 +#define CONFIG_I2C_TIMEOUT 100000 #endif #define I2C_READ_BIT 1 @@ -46,10 +46,16 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct fsl_i2c *i2c_dev[2] = { +static const struct fsl_i2c *i2c_dev[4] = { (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET), #ifdef CONFIG_SYS_FSL_I2C2_OFFSET - (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET) + (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET), +#endif +#ifdef CONFIG_SYS_FSL_I2C3_OFFSET + (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET), +#endif +#ifdef CONFIG_SYS_FSL_I2C4_OFFSET + (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET) #endif }; @@ -121,7 +127,7 @@ static const struct { static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, unsigned int i2c_clk, unsigned int speed) { - unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); + unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX); /* * We want to choose an FDR/DFSR that generates an I2C bus speed that @@ -206,9 +212,58 @@ static unsigned int get_i2c_clock(int bus) return gd->arch.i2c1_clk; /* I2C1 clock */ } +static int fsl_i2c_fixup(const struct fsl_i2c *dev) +{ + const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); + unsigned long long timeval = 0; + int ret = -1; + unsigned int flags = 0; + +#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 + unsigned int svr = get_svr(); + if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || + (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) + flags = I2C_CR_BIT6; +#endif + + writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr); + + timeval = get_ticks(); + while (!(readb(&dev->sr) & I2C_SR_MBB)) { + if ((get_ticks() - timeval) > timeout) + goto err; + } + + if (readb(&dev->sr) & I2C_SR_MAL) { + /* SDA is stuck low */ + writeb(0, &dev->cr); + udelay(100); + writeb(I2C_CR_MSTA | flags, &dev->cr); + writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr); + } + + readb(&dev->dr); + + timeval = get_ticks(); + while (!(readb(&dev->sr) & I2C_SR_MIF)) { + if ((get_ticks() - timeval) > timeout) + goto err; + } + ret = 0; + +err: + writeb(I2C_CR_MEN | flags, &dev->cr); + writeb(0, &dev->sr); + udelay(100); + + return ret; +} + static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { const struct fsl_i2c *dev; + const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); + unsigned long long timeval; #ifdef CONFIG_SYS_I2C_INIT_BOARD /* Call board specific i2c bus reset routine before accessing the @@ -226,6 +281,18 @@ static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ + timeval = get_ticks(); + while (readb(&dev->sr) & I2C_SR_MBB) { + if ((get_ticks() - timeval) < timeout) + continue; + + if (fsl_i2c_fixup(dev)) + debug("i2c_init: BUS#%d failed to init\n", + adap->hwadapnr); + + break; + } + #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT /* Call board specific i2c bus reset routine AFTER the bus has been * initialized. Use either this callpoint or i2c_init_board; @@ -362,18 +429,45 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data, struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; int i = -1; /* signal error */ u8 *a = (u8*)&addr; + int len = alen * -1; if (i2c_wait4bus(adap) < 0) return -1; - if ((!length || alen > 0) - && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 - && __i2c_write(adap, &a[4 - alen], alen) == alen) - i = 0; /* No error so far */ + /* To handle the need of I2C devices that require to write few bytes + * (more than 4 bytes of address as in the case of else part) + * of data before reading, Negative equivalent of length(bytes to write) + * is passed, but used the +ve part of len for writing data + */ + if (alen < 0) { + /* Generate a START and send the Address and + * the Tx Bytes to the slave. + * "START: Address: Write bytes data[len]" + * IF part supports writing any number of bytes in contrast + * to the else part, which supports writing address offset + * of upto 4 bytes only. + * bytes that need to be written are passed in + * "data", which will eventually keep the data READ, + * after writing the len bytes out of it + */ + if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0) + i = __i2c_write(adap, data, len); + + if (i != len) + return -1; - if (length && - i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0) - i = __i2c_read(adap, data, length); + if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0) + i = __i2c_read(adap, data, length); + } else { + if ((!length || alen > 0) && + i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 && + __i2c_write(adap, &a[4 - alen], alen) == alen) + i = 0; /* No error so far */ + + if (length && + i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0) + i = __i2c_read(adap, data, length); + } writeb(I2C_CR_MEN, &device->cr); @@ -394,8 +488,10 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen, int i = -1; /* signal error */ u8 *a = (u8*)&addr; - if (i2c_wait4bus(adap) >= 0 && - i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 && + if (i2c_wait4bus(adap) < 0) + return -1; + + if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 && __i2c_write(adap, &a[4 - alen], alen) == alen) { i = __i2c_write(adap, data, length); } @@ -449,3 +545,15 @@ U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE, 1) #endif +#ifdef CONFIG_SYS_FSL_I2C3_OFFSET +U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, + fsl_i2c_write, fsl_i2c_set_bus_speed, + CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE, + 2) +#endif +#ifdef CONFIG_SYS_FSL_I2C4_OFFSET +U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, + fsl_i2c_write, fsl_i2c_set_bus_speed, + CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE, + 3) +#endif diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c index ddeb941faf..68d9a42912 100644 --- a/drivers/i2c/fti2c010.c +++ b/drivers/i2c/fti2c010.c @@ -13,67 +13,78 @@ #include "fti2c010.h" -#ifndef CONFIG_HARD_I2C -#error "fti2c010: CONFIG_HARD_I2C is not defined" +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 5000 #endif -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0 #endif -#ifndef CONFIG_FTI2C010_FREQ -#define CONFIG_FTI2C010_FREQ clk_get_rate("I2C") +#ifndef CONFIG_FTI2C010_CLOCK +#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C") #endif -/* command timeout */ -#define CFG_CMD_TIMEOUT 10 /* ms */ +#ifndef CONFIG_FTI2C010_TIMEOUT +#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */ +#endif -/* 7-bit chip address + 1-bit read/write */ -#define I2C_RD(chip) ((((chip) << 1) & 0xff) | 1) -#define I2C_WR(chip) (((chip) << 1) & 0xff) +/* 7-bit dev address + 1-bit read/write */ +#define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1) +#define I2C_WR(dev) (((dev) << 1) & 0xfe) struct fti2c010_chip { - void __iomem *regs; - uint bus; - uint speed; + struct fti2c010_regs *regs; }; static struct fti2c010_chip chip_list[] = { { - .bus = 0, - .regs = (void __iomem *)CONFIG_FTI2C010_BASE, + .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE, }, -#ifdef CONFIG_I2C_MULTI_BUS -# ifdef CONFIG_FTI2C010_BASE1 +#ifdef CONFIG_FTI2C010_BASE1 { - .bus = 1, - .regs = (void __iomem *)CONFIG_FTI2C010_BASE1, + .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1, }, -# endif -# ifdef CONFIG_FTI2C010_BASE2 +#endif +#ifdef CONFIG_FTI2C010_BASE2 { - .bus = 2, - .regs = (void __iomem *)CONFIG_FTI2C010_BASE2, + .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2, }, -# endif -# ifdef CONFIG_FTI2C010_BASE3 +#endif +#ifdef CONFIG_FTI2C010_BASE3 { - .bus = 3, - .regs = (void __iomem *)CONFIG_FTI2C010_BASE3, + .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3, }, -# endif -#endif /* #ifdef CONFIG_I2C_MULTI_BUS */ +#endif }; -static struct fti2c010_chip *curr = chip_list; +static int fti2c010_reset(struct fti2c010_chip *chip) +{ + ulong ts; + int ret = -1; + struct fti2c010_regs *regs = chip->regs; + + writel(CR_I2CRST, ®s->cr); + for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) { + if (!(readl(®s->cr) & CR_I2CRST)) { + ret = 0; + break; + } + } -static int fti2c010_wait(uint32_t mask) + if (ret) + printf("fti2c010: reset timeout\n"); + + return ret; +} + +static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask) { int ret = -1; uint32_t stat, ts; - struct fti2c010_regs *regs = curr->regs; + struct fti2c010_regs *regs = chip->regs; - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { + for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) { stat = readl(®s->sr); if ((stat & mask) == mask) { ret = 0; @@ -84,88 +95,124 @@ static int fti2c010_wait(uint32_t mask) return ret; } -/* - * u-boot I2C API - */ +static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip, + unsigned int speed) +{ + struct fti2c010_regs *regs = chip->regs; + unsigned int clk = CONFIG_FTI2C010_CLOCK; + unsigned int gsr = 0; + unsigned int tsr = 32; + unsigned int div, rate; + + for (div = 0; div < 0x3ffff; ++div) { + /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */ + rate = clk / (2 * (div + 2) + gsr); + if (rate <= speed) + break; + } + + writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr); + writel(CDR_DIV(div), ®s->cdr); + + return rate; +} /* * Initialization, must be called once on start up, may be called * repeatedly to change the speed and slave addresses. */ -void i2c_init(int speed, int slaveaddr) +static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr) { - if (speed || !curr->speed) - i2c_set_bus_speed(speed); + struct fti2c010_chip *chip = chip_list + adap->hwadapnr; - /* if slave mode disabled */ - if (!slaveaddr) + if (adap->init_done) return; - /* - * TODO: - * Implement slave mode, but is it really necessary? - */ +#ifdef CONFIG_SYS_I2C_INIT_BOARD + /* Call board specific i2c bus reset routine before accessing the + * environment, which might be in a chip on that bus. For details + * about this problem see doc/I2C_Edge_Conditions. + */ + i2c_init_board(); +#endif + + /* master init */ + + fti2c010_reset(chip); + + set_i2c_bus_speed(chip, speed); + + /* slave init, don't care */ + +#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT + /* Call board specific i2c bus reset routine AFTER the bus has been + * initialized. Use either this callpoint or i2c_init_board; + * which is called before fti2c010_init operations. + * For details about this problem see doc/I2C_Edge_Conditions. + */ + i2c_board_late_init(); +#endif } /* * Probe the given I2C chip address. Returns 0 if a chip responded, * not 0 on failure. */ -int i2c_probe(uchar chip) +static int fti2c010_probe(struct i2c_adapter *adap, u8 dev) { + struct fti2c010_chip *chip = chip_list + adap->hwadapnr; + struct fti2c010_regs *regs = chip->regs; int ret; - struct fti2c010_regs *regs = curr->regs; - - i2c_init(0, 0); /* 1. Select slave device (7bits Address + 1bit R/W) */ - writel(I2C_WR(chip), ®s->dr); + writel(I2C_WR(dev), ®s->dr); writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); - ret = fti2c010_wait(SR_DT); + ret = fti2c010_wait(chip, SR_DT); if (ret) return ret; /* 2. Select device register */ writel(0, ®s->dr); writel(CR_ENABLE | CR_TBEN, ®s->cr); - ret = fti2c010_wait(SR_DT); + ret = fti2c010_wait(chip, SR_DT); return ret; } -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +static void to_i2c_addr(u8 *buf, uint32_t addr, int alen) { - int ret, pos; - uchar paddr[4]; - struct fti2c010_regs *regs = curr->regs; + int i, shift; - i2c_init(0, 0); + if (!buf || alen <= 0) + return; + + /* MSB first */ + i = 0; + shift = (alen - 1) * 8; + while (alen-- > 0) { + buf[i] = (u8)(addr >> shift); + shift -= 8; + } +} - paddr[0] = (addr >> 0) & 0xFF; - paddr[1] = (addr >> 8) & 0xFF; - paddr[2] = (addr >> 16) & 0xFF; - paddr[3] = (addr >> 24) & 0xFF; +static int fti2c010_read(struct i2c_adapter *adap, + u8 dev, uint addr, int alen, uchar *buf, int len) +{ + struct fti2c010_chip *chip = chip_list + adap->hwadapnr; + struct fti2c010_regs *regs = chip->regs; + int ret, pos; + uchar paddr[4] = { 0 }; + + to_i2c_addr(paddr, addr, alen); /* * Phase A. Set register address */ /* A.1 Select slave device (7bits Address + 1bit R/W) */ - writel(I2C_WR(chip), ®s->dr); + writel(I2C_WR(dev), ®s->dr); writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); - ret = fti2c010_wait(SR_DT); + ret = fti2c010_wait(chip, SR_DT); if (ret) return ret; @@ -175,7 +222,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) writel(paddr[pos], ®s->dr); writel(ctrl, ®s->cr); - ret = fti2c010_wait(SR_DT); + ret = fti2c010_wait(chip, SR_DT); if (ret) return ret; } @@ -185,9 +232,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) */ /* B.1 Select slave device (7bits Address + 1bit R/W) */ - writel(I2C_RD(chip), ®s->dr); + writel(I2C_RD(dev), ®s->dr); writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); - ret = fti2c010_wait(SR_DT); + ret = fti2c010_wait(chip, SR_DT); if (ret) return ret; @@ -201,7 +248,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) stat |= SR_ACK; } writel(ctrl, ®s->cr); - ret = fti2c010_wait(stat); + ret = fti2c010_wait(chip, stat); if (ret) break; buf[pos] = (uchar)(readl(®s->dr) & 0xFF); @@ -210,39 +257,24 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) return ret; } -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +static int fti2c010_write(struct i2c_adapter *adap, + u8 dev, uint addr, int alen, u8 *buf, int len) { + struct fti2c010_chip *chip = chip_list + adap->hwadapnr; + struct fti2c010_regs *regs = chip->regs; int ret, pos; - uchar paddr[4]; - struct fti2c010_regs *regs = curr->regs; + uchar paddr[4] = { 0 }; - i2c_init(0, 0); - - paddr[0] = (addr >> 0) & 0xFF; - paddr[1] = (addr >> 8) & 0xFF; - paddr[2] = (addr >> 16) & 0xFF; - paddr[3] = (addr >> 24) & 0xFF; + to_i2c_addr(paddr, addr, alen); /* * Phase A. Set register address * * A.1 Select slave device (7bits Address + 1bit R/W) */ - writel(I2C_WR(chip), ®s->dr); + writel(I2C_WR(dev), ®s->dr); writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); - ret = fti2c010_wait(SR_DT); + ret = fti2c010_wait(chip, SR_DT); if (ret) return ret; @@ -252,7 +284,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) writel(paddr[pos], ®s->dr); writel(ctrl, ®s->cr); - ret = fti2c010_wait(SR_DT); + ret = fti2c010_wait(chip, SR_DT); if (ret) return ret; } @@ -267,7 +299,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) ctrl |= CR_STOP; writel(buf[pos], ®s->dr); writel(ctrl, ®s->cr); - ret = fti2c010_wait(SR_DT); + ret = fti2c010_wait(chip, SR_DT); if (ret) break; } @@ -275,94 +307,40 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) return ret; } -/* - * Functions for setting the current I2C bus and its speed - */ -#ifdef CONFIG_I2C_MULTI_BUS - -/* - * i2c_set_bus_num: - * - * Change the active I2C bus. Subsequent read/write calls will - * go to this one. - * - * bus - bus index, zero based - * - * Returns: 0 on success, not 0 on failure - */ -int i2c_set_bus_num(uint bus) -{ - if (bus >= ARRAY_SIZE(chip_list)) - return -1; - curr = chip_list + bus; - i2c_init(0, 0); - return 0; -} - -/* - * i2c_get_bus_num: - * - * Returns index of currently active I2C bus. Zero-based. - */ - -uint i2c_get_bus_num(void) -{ - return curr->bus; -} - -#endif /* #ifdef CONFIG_I2C_MULTI_BUS */ - -/* - * i2c_set_bus_speed: - * - * Change the speed of the active I2C bus - * - * speed - bus speed in Hz - * - * Returns: 0 on success, not 0 on failure - */ -int i2c_set_bus_speed(uint speed) +static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) { - struct fti2c010_regs *regs = curr->regs; - uint clk = CONFIG_FTI2C010_FREQ; - uint gsr = 0, tsr = 32; - uint spd, div; - - if (!speed) - speed = CONFIG_SYS_I2C_SPEED; - - for (div = 0; div < 0x3ffff; ++div) { - /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */ - spd = clk / (2 * (div + 2) + gsr); - if (spd <= speed) - break; - } - - if (curr->speed == spd) - return 0; - - writel(CR_I2CRST, ®s->cr); - mdelay(100); - if (readl(®s->cr) & CR_I2CRST) { - printf("fti2c010: reset timeout\n"); - return -1; - } + struct fti2c010_chip *chip = chip_list + adap->hwadapnr; + int ret; - curr->speed = spd; + fti2c010_reset(chip); + ret = set_i2c_bus_speed(chip, speed); - writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr); - writel(CDR_DIV(div), ®s->cdr); - - return 0; + return ret; } /* - * i2c_get_bus_speed: - * - * Returns speed of currently active I2C bus in Hz + * Register i2c adapters */ - -uint i2c_get_bus_speed(void) -{ - return curr->speed; -} +U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read, + fti2c010_write, fti2c010_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + 0) +#ifdef CONFIG_FTI2C010_BASE1 +U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read, + fti2c010_write, fti2c010_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + 1) +#endif +#ifdef CONFIG_FTI2C010_BASE2 +U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read, + fti2c010_write, fti2c010_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + 2) +#endif +#ifdef CONFIG_FTI2C010_BASE3 +U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read, + fti2c010_write, fti2c010_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + 3) +#endif diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c new file mode 100644 index 0000000000..aa89f95953 --- /dev/null +++ b/drivers/i2c/i2c-emul-uclass.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +UCLASS_DRIVER(i2c_emul) = { + .id = UCLASS_I2C_EMUL, + .name = "i2c_emul", +}; diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c new file mode 100644 index 0000000000..223f238f4b --- /dev/null +++ b/drivers/i2c/i2c-uclass-compat.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static int cur_busnum; + +static int i2c_compat_get_device(uint chip_addr, int alen, + struct udevice **devp) +{ + struct dm_i2c_chip *chip; + int ret; + + ret = i2c_get_chip_for_busnum(cur_busnum, chip_addr, alen, devp); + if (ret) + return ret; + chip = dev_get_parent_platdata(*devp); + if (chip->offset_len != alen) { + printf("I2C chip %x: requested alen %d does not match chip offset_len %d\n", + chip_addr, alen, chip->offset_len); + return -EADDRNOTAVAIL; + } + + return 0; +} + +int i2c_probe(uint8_t chip_addr) +{ + struct udevice *bus, *dev; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, cur_busnum, &bus); + if (ret) { + debug("Cannot find I2C bus %d: err=%d\n", cur_busnum, ret); + return ret; + } + + if (!bus) + return -ENOENT; + + return dm_i2c_probe(bus, chip_addr, 0, &dev); +} + +int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, + int len) +{ + struct udevice *dev; + int ret; + + ret = i2c_compat_get_device(chip_addr, alen, &dev); + if (ret) + return ret; + + return dm_i2c_read(dev, addr, buffer, len); +} + +int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, + int len) +{ + struct udevice *dev; + int ret; + + ret = i2c_compat_get_device(chip_addr, alen, &dev); + if (ret) + return ret; + + return dm_i2c_write(dev, addr, buffer, len); +} + +int i2c_get_bus_num_fdt(int node) +{ + struct udevice *bus; + int ret; + + ret = uclass_get_device_by_of_offset(UCLASS_I2C, node, &bus); + if (ret) + return ret; + + return bus->seq; +} + +unsigned int i2c_get_bus_num(void) +{ + return cur_busnum; +} + +int i2c_set_bus_num(unsigned int bus) +{ + cur_busnum = bus; + + return 0; +} + +void i2c_init(int speed, int slaveaddr) +{ + /* Nothing to do here - the init happens through driver model */ +} + +void board_i2c_init(const void *blob) +{ + /* Nothing to do here - the init happens through driver model */ +} diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c new file mode 100644 index 0000000000..eafa457845 --- /dev/null +++ b/drivers/i2c/i2c-uclass.c @@ -0,0 +1,481 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define I2C_MAX_OFFSET_LEN 4 + +/** + * i2c_setup_offset() - Set up a new message with a chip offset + * + * @chip: Chip to use + * @offset: Byte offset within chip + * @offset_buf: Place to put byte offset + * @msg: Message buffer + * @return 0 if OK, -EADDRNOTAVAIL if the offset length is 0. In that case the + * message is still set up but will not contain an offset. + */ +static int i2c_setup_offset(struct dm_i2c_chip *chip, uint offset, + uint8_t offset_buf[], struct i2c_msg *msg) +{ + int offset_len; + + msg->addr = chip->chip_addr; + msg->flags = chip->flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0; + msg->len = chip->offset_len; + msg->buf = offset_buf; + if (!chip->offset_len) + return -EADDRNOTAVAIL; + assert(chip->offset_len <= I2C_MAX_OFFSET_LEN); + offset_len = chip->offset_len; + while (offset_len--) + *offset_buf++ = offset >> (8 * offset_len); + + return 0; +} + +static int i2c_read_bytewise(struct udevice *dev, uint offset, + uint8_t *buffer, int len) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + struct udevice *bus = dev_get_parent(dev); + struct dm_i2c_ops *ops = i2c_get_ops(bus); + struct i2c_msg msg[2], *ptr; + uint8_t offset_buf[I2C_MAX_OFFSET_LEN]; + int ret; + int i; + + for (i = 0; i < len; i++) { + if (i2c_setup_offset(chip, offset + i, offset_buf, msg)) + return -EINVAL; + ptr = msg + 1; + ptr->addr = chip->chip_addr; + ptr->flags = msg->flags | I2C_M_RD; + ptr->len = 1; + ptr->buf = &buffer[i]; + ptr++; + + ret = ops->xfer(bus, msg, ptr - msg); + if (ret) + return ret; + } + + return 0; +} + +static int i2c_write_bytewise(struct udevice *dev, uint offset, + const uint8_t *buffer, int len) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + struct udevice *bus = dev_get_parent(dev); + struct dm_i2c_ops *ops = i2c_get_ops(bus); + struct i2c_msg msg[1]; + uint8_t buf[I2C_MAX_OFFSET_LEN + 1]; + int ret; + int i; + + for (i = 0; i < len; i++) { + if (i2c_setup_offset(chip, offset + i, buf, msg)) + return -EINVAL; + buf[msg->len++] = buffer[i]; + + ret = ops->xfer(bus, msg, 1); + if (ret) + return ret; + } + + return 0; +} + +int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + struct udevice *bus = dev_get_parent(dev); + struct dm_i2c_ops *ops = i2c_get_ops(bus); + struct i2c_msg msg[2], *ptr; + uint8_t offset_buf[I2C_MAX_OFFSET_LEN]; + int msg_count; + + if (!ops->xfer) + return -ENOSYS; + if (chip->flags & DM_I2C_CHIP_RD_ADDRESS) + return i2c_read_bytewise(dev, offset, buffer, len); + ptr = msg; + if (!i2c_setup_offset(chip, offset, offset_buf, ptr)) + ptr++; + + if (len) { + ptr->addr = chip->chip_addr; + ptr->flags = chip->flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0; + ptr->flags |= I2C_M_RD; + ptr->len = len; + ptr->buf = buffer; + ptr++; + } + msg_count = ptr - msg; + + return ops->xfer(bus, msg, msg_count); +} + +int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, + int len) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + struct udevice *bus = dev_get_parent(dev); + struct dm_i2c_ops *ops = i2c_get_ops(bus); + struct i2c_msg msg[1]; + + if (!ops->xfer) + return -ENOSYS; + + if (chip->flags & DM_I2C_CHIP_WR_ADDRESS) + return i2c_write_bytewise(dev, offset, buffer, len); + /* + * The simple approach would be to send two messages here: one to + * set the offset and one to write the bytes. However some drivers + * will not be expecting this, and some chips won't like how the + * driver presents this on the I2C bus. + * + * The API does not support separate offset and data. We could extend + * it with a flag indicating that there is data in the next message + * that needs to be processed in the same transaction. We could + * instead add an additional buffer to each message. For now, handle + * this in the uclass since it isn't clear what the impact on drivers + * would be with this extra complication. Unfortunately this means + * copying the message. + * + * Use the stack for small messages, malloc() for larger ones. We + * need to allow space for the offset (up to 4 bytes) and the message + * itself. + */ + if (len < 64) { + uint8_t buf[I2C_MAX_OFFSET_LEN + len]; + + i2c_setup_offset(chip, offset, buf, msg); + msg->len += len; + memcpy(buf + chip->offset_len, buffer, len); + + return ops->xfer(bus, msg, 1); + } else { + uint8_t *buf; + int ret; + + buf = malloc(I2C_MAX_OFFSET_LEN + len); + if (!buf) + return -ENOMEM; + i2c_setup_offset(chip, offset, buf, msg); + msg->len += len; + memcpy(buf + chip->offset_len, buffer, len); + + ret = ops->xfer(bus, msg, 1); + free(buf); + return ret; + } +} + +/** + * i2c_probe_chip() - probe for a chip on a bus + * + * @bus: Bus to probe + * @chip_addr: Chip address to probe + * @flags: Flags for the chip + * @return 0 if found, -ENOSYS if the driver is invalid, -EREMOTEIO if the chip + * does not respond to probe + */ +static int i2c_probe_chip(struct udevice *bus, uint chip_addr, + enum dm_i2c_chip_flags chip_flags) +{ + struct dm_i2c_ops *ops = i2c_get_ops(bus); + struct i2c_msg msg[1]; + int ret; + + if (ops->probe_chip) { + ret = ops->probe_chip(bus, chip_addr, chip_flags); + if (!ret || ret != -ENOSYS) + return ret; + } + + if (!ops->xfer) + return -ENOSYS; + + /* Probe with a zero-length message */ + msg->addr = chip_addr; + msg->flags = chip_flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0; + msg->len = 0; + msg->buf = NULL; + + return ops->xfer(bus, msg, 1); +} + +static int i2c_bind_driver(struct udevice *bus, uint chip_addr, uint offset_len, + struct udevice **devp) +{ + struct dm_i2c_chip *chip; + char name[30], *str; + struct udevice *dev; + int ret; + + snprintf(name, sizeof(name), "generic_%x", chip_addr); + str = strdup(name); + ret = device_bind_driver(bus, "i2c_generic_chip_drv", str, &dev); + debug("%s: device_bind_driver: ret=%d\n", __func__, ret); + if (ret) + goto err_bind; + + /* Tell the device what we know about it */ + chip = dev_get_parent_platdata(dev); + chip->chip_addr = chip_addr; + chip->offset_len = offset_len; + ret = device_probe(dev); + debug("%s: device_probe: ret=%d\n", __func__, ret); + if (ret) + goto err_probe; + + *devp = dev; + return 0; + +err_probe: + /* + * If the device failed to probe, unbind it. There is nothing there + * on the bus so we don't want to leave it lying around + */ + device_unbind(dev); +err_bind: + free(str); + return ret; +} + +int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, + struct udevice **devp) +{ + struct udevice *dev; + + debug("%s: Searching bus '%s' for address %02x: ", __func__, + bus->name, chip_addr); + for (device_find_first_child(bus, &dev); dev; + device_find_next_child(&dev)) { + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + int ret; + + if (chip->chip_addr == chip_addr) { + ret = device_probe(dev); + debug("found, ret=%d\n", ret); + if (ret) + return ret; + *devp = dev; + return 0; + } + } + debug("not found\n"); + return i2c_bind_driver(bus, chip_addr, offset_len, devp); +} + +int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, + struct udevice **devp) +{ + struct udevice *bus; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus); + if (ret) { + debug("Cannot find I2C bus %d\n", busnum); + return ret; + } + ret = i2c_get_chip(bus, chip_addr, offset_len, devp); + if (ret) { + debug("Cannot find I2C chip %02x on bus %d\n", chip_addr, + busnum); + return ret; + } + + return 0; +} + +int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, + struct udevice **devp) +{ + int ret; + + *devp = NULL; + + /* First probe that chip */ + ret = i2c_probe_chip(bus, chip_addr, chip_flags); + debug("%s: bus='%s', address %02x, ret=%d\n", __func__, bus->name, + chip_addr, ret); + if (ret) + return ret; + + /* The chip was found, see if we have a driver, and probe it */ + ret = i2c_get_chip(bus, chip_addr, 1, devp); + debug("%s: i2c_get_chip: ret=%d\n", __func__, ret); + + return ret; +} + +int i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct dm_i2c_ops *ops = i2c_get_ops(bus); + struct dm_i2c_bus *i2c = bus->uclass_priv; + int ret; + + /* + * If we have a method, call it. If not then the driver probably wants + * to deal with speed changes on the next transfer. It can easily read + * the current speed from this uclass + */ + if (ops->set_bus_speed) { + ret = ops->set_bus_speed(bus, speed); + if (ret) + return ret; + } + i2c->speed_hz = speed; + + return 0; +} + +/* + * i2c_get_bus_speed: + * + * Returns speed of selected I2C bus in Hz + */ +int i2c_get_bus_speed(struct udevice *bus) +{ + struct dm_i2c_ops *ops = i2c_get_ops(bus); + struct dm_i2c_bus *i2c = bus->uclass_priv; + + if (!ops->get_bus_speed) + return i2c->speed_hz; + + return ops->get_bus_speed(bus); +} + +int i2c_set_chip_flags(struct udevice *dev, uint flags) +{ + struct udevice *bus = dev->parent; + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + struct dm_i2c_ops *ops = i2c_get_ops(bus); + int ret; + + if (ops->set_flags) { + ret = ops->set_flags(dev, flags); + if (ret) + return ret; + } + chip->flags = flags; + + return 0; +} + +int i2c_get_chip_flags(struct udevice *dev, uint *flagsp) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + + *flagsp = chip->flags; + + return 0; +} + +int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + + if (offset_len > I2C_MAX_OFFSET_LEN) + return -EINVAL; + chip->offset_len = offset_len; + + return 0; +} + +int i2c_deblock(struct udevice *bus) +{ + struct dm_i2c_ops *ops = i2c_get_ops(bus); + + /* + * We could implement a software deblocking here if we could get + * access to the GPIOs used by I2C, and switch them to GPIO mode + * and then back to I2C. This is somewhat beyond our powers in + * driver model at present, so for now just fail. + * + * See https://patchwork.ozlabs.org/patch/399040/ + */ + if (!ops->deblock) + return -ENOSYS; + + return ops->deblock(bus); +} + +int i2c_chip_ofdata_to_platdata(const void *blob, int node, + struct dm_i2c_chip *chip) +{ + chip->offset_len = fdtdec_get_int(gd->fdt_blob, node, + "u-boot,i2c-offset-len", 1); + chip->flags = 0; + chip->chip_addr = fdtdec_get_int(gd->fdt_blob, node, "reg", -1); + if (chip->chip_addr == -1) { + debug("%s: I2C Node '%s' has no 'reg' property\n", __func__, + fdt_get_name(blob, node, NULL)); + return -EINVAL; + } + + return 0; +} + +static int i2c_post_probe(struct udevice *dev) +{ + struct dm_i2c_bus *i2c = dev->uclass_priv; + + i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 100000); + + return i2c_set_bus_speed(dev, i2c->speed_hz); +} + +static int i2c_post_bind(struct udevice *dev) +{ + /* Scan the bus for devices */ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + +static int i2c_child_post_bind(struct udevice *dev) +{ + struct dm_i2c_chip *plat = dev_get_parent_platdata(dev); + + if (dev->of_offset == -1) + return 0; + + return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat); +} + +UCLASS_DRIVER(i2c) = { + .id = UCLASS_I2C, + .name = "i2c", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .post_bind = i2c_post_bind, + .post_probe = i2c_post_probe, + .per_device_auto_alloc_size = sizeof(struct dm_i2c_bus), + .per_child_platdata_auto_alloc_size = sizeof(struct dm_i2c_chip), + .child_post_bind = i2c_child_post_bind, +}; + +UCLASS_DRIVER(i2c_generic) = { + .id = UCLASS_I2C_GENERIC, + .name = "i2c_generic", +}; + +U_BOOT_DRIVER(i2c_generic_chip_drv) = { + .name = "i2c_generic_chip_drv", + .id = UCLASS_I2C_GENERIC, +}; diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c new file mode 100644 index 0000000000..6707edd9ef --- /dev/null +++ b/drivers/i2c/i2c-uniphier-f.c @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct uniphier_fi2c_regs { + u32 cr; /* control register */ +#define I2C_CR_MST (1 << 3) /* master mode */ +#define I2C_CR_STA (1 << 2) /* start condition */ +#define I2C_CR_STO (1 << 1) /* stop condition */ +#define I2C_CR_NACK (1 << 0) /* not ACK */ + u32 dttx; /* send FIFO (write-only) */ +#define dtrx dttx /* receive FIFO (read-only) */ +#define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */ +#define I2C_DTTX_RD (1 << 0) /* read */ + u32 __reserved; /* no register at offset 0x08 */ + u32 slad; /* slave address */ + u32 cyc; /* clock cycle control */ + u32 lctl; /* clock low period control */ + u32 ssut; /* restart/stop setup time control */ + u32 dsut; /* data setup time control */ + u32 intr; /* interrupt status */ + u32 ie; /* interrupt enable */ + u32 ic; /* interrupt clear */ +#define I2C_INT_TE (1 << 9) /* TX FIFO empty */ +#define I2C_INT_RB (1 << 4) /* received specified bytes */ +#define I2C_INT_NA (1 << 2) /* no answer */ +#define I2C_INT_AL (1 << 1) /* arbitration lost */ + u32 sr; /* status register */ +#define I2C_SR_DB (1 << 12) /* device busy */ +#define I2C_SR_BB (1 << 8) /* bus busy */ +#define I2C_SR_RFF (1 << 3) /* Rx FIFO full */ +#define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */ +#define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */ +#define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */ + u32 __reserved2; /* no register at offset 0x30 */ + u32 rst; /* reset control */ +#define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */ +#define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */ +#define I2C_RST_RST (1 << 0) /* forcible bus reset */ + u32 bm; /* bus monitor */ + u32 noise; /* noise filter control */ + u32 tbc; /* Tx byte count setting */ + u32 rbc; /* Rx byte count setting */ + u32 tbcm; /* Tx byte count monitor */ + u32 rbcm; /* Rx byte count monitor */ + u32 brst; /* bus reset */ +#define I2C_BRST_FOEN (1 << 1) /* normal operation */ +#define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */ +}; + +#define FIOCLK 50000000 + +struct uniphier_fi2c_dev { + struct uniphier_fi2c_regs __iomem *regs; /* register base */ + unsigned long fioclk; /* internal operation clock */ + unsigned long timeout; /* time out (us) */ +}; + +static int poll_status(u32 __iomem *reg, u32 flag) +{ + int wait = 1000000; /* 1 sec is long enough */ + + while (readl(reg) & flag) { + if (wait-- < 0) + return -EREMOTEIO; + udelay(1); + } + + return 0; +} + +static int reset_bus(struct uniphier_fi2c_regs __iomem *regs) +{ + int ret; + + /* bus forcible reset */ + writel(I2C_RST_RST, ®s->rst); + ret = poll_status(®s->rst, I2C_RST_RST); + if (ret < 0) + debug("error: fail to reset I2C controller\n"); + + return ret; +} + +static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs) +{ + int ret; + + ret = poll_status(®s->sr, I2C_SR_DB); + if (ret < 0) { + debug("error: device busy too long. reset...\n"); + ret = reset_bus(regs); + } + + return ret; +} + +static int uniphier_fi2c_probe(struct udevice *dev) +{ + fdt_addr_t addr; + fdt_size_t size; + struct uniphier_fi2c_dev *priv = dev_get_priv(dev); + int ret; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", + &size); + + priv->regs = map_sysmem(addr, size); + + if (!priv->regs) + return -ENOMEM; + + priv->fioclk = FIOCLK; + + /* bus forcible reset */ + ret = reset_bus(priv->regs); + if (ret < 0) + return ret; + + writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst); + + return 0; +} + +static int uniphier_fi2c_remove(struct udevice *dev) +{ + struct uniphier_fi2c_dev *priv = dev_get_priv(dev); + + unmap_sysmem(priv->regs); + + return 0; +} + +static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags, + bool *stop) +{ + u32 irq; + unsigned long wait = dev->timeout; + int ret = -EREMOTEIO; + + do { + udelay(1); + irq = readl(&dev->regs->intr); + } while (!(irq & flags) && wait--); + + if (wait < 0) { + debug("error: time out\n"); + return ret; + } + + if (irq & I2C_INT_AL) { + debug("error: arbitration lost\n"); + *stop = false; + return ret; + } + + if (irq & I2C_INT_NA) { + debug("error: no answer\n"); + return ret; + } + + return 0; +} + +static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret) +{ + int ret; + + debug("stop condition\n"); + writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr); + + ret = poll_status(&dev->regs->sr, I2C_SR_DB); + if (ret < 0) + debug("error: device busy after operation\n"); + + return old_ret ? old_ret : ret; +} + +static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr, + uint len, const u8 *buf, bool *stop) +{ + int ret; + const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL; + struct uniphier_fi2c_regs __iomem *regs = dev->regs; + + debug("%s: addr = %x, len = %d\n", __func__, addr, len); + + writel(I2C_DTTX_CMD | addr << 1, ®s->dttx); + + writel(irq_flags, ®s->ie); + writel(irq_flags, ®s->ic); + + debug("start condition\n"); + writel(I2C_CR_MST | I2C_CR_STA, ®s->cr); + + ret = wait_for_irq(dev, irq_flags, stop); + if (ret < 0) + goto error; + + while (len--) { + debug("sending %x\n", *buf); + writel(*buf++, ®s->dttx); + + writel(irq_flags, ®s->ic); + + ret = wait_for_irq(dev, irq_flags, stop); + if (ret < 0) + goto error; + } + +error: + writel(irq_flags, ®s->ic); + + if (*stop) + ret = issue_stop(dev, ret); + + return ret; +} + +static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr, + uint len, u8 *buf, bool *stop) +{ + int ret = 0; + const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL; + struct uniphier_fi2c_regs __iomem *regs = dev->regs; + + debug("%s: addr = %x, len = %d\n", __func__, addr, len); + + /* + * In case 'len == 0', only the slave address should be sent + * for probing, which is covered by the transmit function. + */ + if (len == 0) + return uniphier_fi2c_transmit(dev, addr, len, buf, stop); + + writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, ®s->dttx); + + writel(0, ®s->rbc); + writel(irq_flags, ®s->ie); + writel(irq_flags, ®s->ic); + + debug("start condition\n"); + writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0), + ®s->cr); + + while (len--) { + ret = wait_for_irq(dev, irq_flags, stop); + if (ret < 0) + goto error; + + *buf++ = readl(®s->dtrx); + debug("received %x\n", *(buf - 1)); + + if (len == 1) + writel(I2C_CR_MST | I2C_CR_NACK, ®s->cr); + + writel(irq_flags, ®s->ic); + } + +error: + writel(irq_flags, ®s->ic); + + if (*stop) + ret = issue_stop(dev, ret); + + return ret; +} + +static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + int ret; + struct uniphier_fi2c_dev *dev = dev_get_priv(bus); + bool stop; + + ret = check_device_busy(dev->regs); + if (ret < 0) + return ret; + + for (; nmsgs > 0; nmsgs--, msg++) { + /* If next message is read, skip the stop condition */ + stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true; + + if (msg->flags & I2C_M_RD) + ret = uniphier_fi2c_receive(dev, msg->addr, msg->len, + msg->buf, &stop); + else + ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len, + msg->buf, &stop); + + if (ret < 0) + break; + } + + return ret; +} + +static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + int ret; + unsigned int clk_count; + struct uniphier_fi2c_dev *dev = dev_get_priv(bus); + struct uniphier_fi2c_regs __iomem *regs = dev->regs; + + /* max supported frequency is 400 kHz */ + if (speed > 400000) + return -EINVAL; + + ret = check_device_busy(dev->regs); + if (ret < 0) + return ret; + + /* make sure the bus is idle when changing the frequency */ + writel(I2C_BRST_RSCLO, ®s->brst); + + clk_count = dev->fioclk / speed; + + writel(clk_count, ®s->cyc); + writel(clk_count / 2, ®s->lctl); + writel(clk_count / 2, ®s->ssut); + writel(clk_count / 16, ®s->dsut); + + writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, ®s->brst); + + /* + * Theoretically, each byte can be transferred in + * 1000000 * 9 / speed usec. + * This time out value is long enough. + */ + dev->timeout = 100000000L / speed; + + return 0; +} + +static const struct dm_i2c_ops uniphier_fi2c_ops = { + .xfer = uniphier_fi2c_xfer, + .set_bus_speed = uniphier_fi2c_set_bus_speed, +}; + +static const struct udevice_id uniphier_fi2c_of_match[] = { + { .compatible = "panasonic,uniphier-fi2c" }, + {}, +}; + +U_BOOT_DRIVER(uniphier_fi2c) = { + .name = "uniphier-fi2c", + .id = UCLASS_I2C, + .of_match = uniphier_fi2c_of_match, + .probe = uniphier_fi2c_probe, + .remove = uniphier_fi2c_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev), + .ops = &uniphier_fi2c_ops, +}; diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c new file mode 100644 index 0000000000..64a9ed81d2 --- /dev/null +++ b/drivers/i2c/i2c-uniphier.c @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct uniphier_i2c_regs { + u32 dtrm; /* data transmission */ +#define I2C_DTRM_STA (1 << 10) +#define I2C_DTRM_STO (1 << 9) +#define I2C_DTRM_NACK (1 << 8) +#define I2C_DTRM_RD (1 << 0) + u32 drec; /* data reception */ +#define I2C_DREC_STS (1 << 12) +#define I2C_DREC_LRB (1 << 11) +#define I2C_DREC_LAB (1 << 9) + u32 myad; /* slave address */ + u32 clk; /* clock frequency control */ + u32 brst; /* bus reset */ +#define I2C_BRST_FOEN (1 << 1) +#define I2C_BRST_BRST (1 << 0) + u32 hold; /* hold time control */ + u32 bsts; /* bus status monitor */ + u32 noise; /* noise filter control */ + u32 setup; /* setup time control */ +}; + +#define IOBUS_FREQ 100000000 + +struct uniphier_i2c_dev { + struct uniphier_i2c_regs __iomem *regs; /* register base */ + unsigned long input_clk; /* master clock (Hz) */ + unsigned long wait_us; /* wait for every byte transfer (us) */ +}; + +static int uniphier_i2c_probe(struct udevice *dev) +{ + fdt_addr_t addr; + fdt_size_t size; + struct uniphier_i2c_dev *priv = dev_get_priv(dev); + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); + + priv->regs = map_sysmem(addr, size); + + if (!priv->regs) + return -ENOMEM; + + priv->input_clk = IOBUS_FREQ; + + /* deassert reset */ + writel(0x3, &priv->regs->brst); + + return 0; +} + +static int uniphier_i2c_remove(struct udevice *dev) +{ + struct uniphier_i2c_dev *priv = dev_get_priv(dev); + + unmap_sysmem(priv->regs); + + return 0; +} + +static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm) +{ + writel(dtrm, &dev->regs->dtrm); + + /* + * This controller only provides interruption to inform the completion + * of each byte transfer. (No status register to poll it.) + * Unfortunately, U-Boot does not have a good support of interrupt. + * Wait for a while. + */ + udelay(dev->wait_us); + + return readl(&dev->regs->drec); +} + +static int send_byte(struct uniphier_i2c_dev *dev, u32 dtrm, bool *stop) +{ + int ret = 0; + u32 drec; + + drec = send_and_recv_byte(dev, dtrm); + + if (drec & I2C_DREC_LAB) { + debug("uniphier_i2c: bus arbitration failed\n"); + *stop = false; + ret = -EREMOTEIO; + } + if (drec & I2C_DREC_LRB) { + debug("uniphier_i2c: slave did not return ACK\n"); + ret = -EREMOTEIO; + } + return ret; +} + +static int uniphier_i2c_transmit(struct uniphier_i2c_dev *dev, uint addr, + uint len, const u8 *buf, bool *stop) +{ + int ret; + + debug("%s: addr = %x, len = %d\n", __func__, addr, len); + + ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop); + if (ret < 0) + goto fail; + + while (len--) { + ret = send_byte(dev, I2C_DTRM_NACK | *buf++, stop); + if (ret < 0) + goto fail; + } + +fail: + if (*stop) + writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm); + + return ret; +} + +static int uniphier_i2c_receive(struct uniphier_i2c_dev *dev, uint addr, + uint len, u8 *buf, bool *stop) +{ + int ret; + + debug("%s: addr = %x, len = %d\n", __func__, addr, len); + + ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | + I2C_DTRM_RD | addr << 1, stop); + if (ret < 0) + goto fail; + + while (len--) + *buf++ = send_and_recv_byte(dev, len ? 0 : I2C_DTRM_NACK); + +fail: + if (*stop) + writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm); + + return ret; +} + +static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + int ret = 0; + struct uniphier_i2c_dev *dev = dev_get_priv(bus); + bool stop; + + for (; nmsgs > 0; nmsgs--, msg++) { + /* If next message is read, skip the stop condition */ + stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true; + + if (msg->flags & I2C_M_RD) + ret = uniphier_i2c_receive(dev, msg->addr, msg->len, + msg->buf, &stop); + else + ret = uniphier_i2c_transmit(dev, msg->addr, msg->len, + msg->buf, &stop); + + if (ret < 0) + break; + } + + return ret; +} + +static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct uniphier_i2c_dev *priv = dev_get_priv(bus); + + /* max supported frequency is 400 kHz */ + if (speed > 400000) + return -EINVAL; + + /* bus reset: make sure the bus is idle when change the frequency */ + writel(0x1, &priv->regs->brst); + + writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed), + &priv->regs->clk); + + writel(0x3, &priv->regs->brst); + + /* + * Theoretically, each byte can be transferred in + * 1000000 * 9 / speed usec. For safety, wait more than double. + */ + priv->wait_us = 20000000 / speed; + + return 0; +} + + +static const struct dm_i2c_ops uniphier_i2c_ops = { + .xfer = uniphier_i2c_xfer, + .set_bus_speed = uniphier_i2c_set_bus_speed, +}; + +static const struct udevice_id uniphier_i2c_of_match[] = { + { .compatible = "panasonic,uniphier-i2c" }, + {}, +}; + +U_BOOT_DRIVER(uniphier_i2c) = { + .name = "uniphier-i2c", + .id = UCLASS_I2C, + .of_match = uniphier_i2c_of_match, + .probe = uniphier_i2c_probe, + .remove = uniphier_i2c_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev), + .ops = &uniphier_i2c_ops, +}; diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index d1072e819b..41cc3b8fa4 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -53,32 +53,26 @@ void i2c_reloc_fixup(void) return; for (i = 0; i < max; i++) { - /* adapter itself */ - addr = (unsigned long)i2c_adap_p; - addr += gd->reloc_off; - i2c_adap_p = (struct i2c_adapter *)addr; /* i2c_init() */ addr = (unsigned long)i2c_adap_p->init; addr += gd->reloc_off; - i2c_adap_p->init = (void (*)(int, int))addr; + i2c_adap_p->init = (void *)addr; /* i2c_probe() */ addr = (unsigned long)i2c_adap_p->probe; addr += gd->reloc_off; - i2c_adap_p->probe = (int (*)(uint8_t))addr; + i2c_adap_p->probe = (void *)addr; /* i2c_read() */ addr = (unsigned long)i2c_adap_p->read; addr += gd->reloc_off; - i2c_adap_p->read = (int (*)(uint8_t, uint, int, uint8_t *, - int))addr; + i2c_adap_p->read = (void *)addr; /* i2c_write() */ addr = (unsigned long)i2c_adap_p->write; addr += gd->reloc_off; - i2c_adap_p->write = (int (*)(uint8_t, uint, int, uint8_t *, - int))addr; + i2c_adap_p->write = (void *)addr; /* i2c_set_bus_speed() */ addr = (unsigned long)i2c_adap_p->set_bus_speed; addr += gd->reloc_off; - i2c_adap_p->set_bus_speed = (uint (*)(uint))addr; + i2c_adap_p->set_bus_speed = (void *)addr; /* name */ addr = (unsigned long)i2c_adap_p->name; addr += gd->reloc_off; @@ -138,6 +132,11 @@ static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip, return -1; buf = (uint8_t)((channel & 0x07) | (1 << 3)); break; + case I2C_MUX_PCA9548_ID: + if (channel > 7) + return -1; + buf = (uint8_t)(0x01 << channel); + break; default: printf("%s: wrong mux id: %d\n", __func__, mux_id); return -1; @@ -175,11 +174,11 @@ static int i2c_mux_set_all(void) return 0; } -static int i2c_mux_disconnet_all(void) +static int i2c_mux_disconnect_all(void) { struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS]; int i; - uint8_t buf; + uint8_t buf = 0; if (I2C_ADAP->init_done == 0) return 0; @@ -198,7 +197,7 @@ static int i2c_mux_disconnet_all(void) ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1); if (ret != 0) { - printf("i2c: mux diconnect error\n"); + printf("i2c: mux disconnect error\n"); return ret; } } while (i > 0); @@ -230,11 +229,9 @@ static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr) } /* implement possible board specific board init */ -static void __def_i2c_init_board(void) +__weak void i2c_init_board(void) { } -void i2c_init_board(void) - __attribute__((weak, alias("__def_i2c_init_board"))); /* * i2c_init_all(): @@ -278,23 +275,25 @@ unsigned int i2c_get_bus_num(void) */ int i2c_set_bus_num(unsigned int bus) { - int max = ll_entry_count(struct i2c_adapter, i2c); + int max; + + if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0)) + return 0; - if (I2C_ADAPTER(bus) >= max) { - printf("Error, wrong i2c adapter %d max %d possible\n", - I2C_ADAPTER(bus), max); - return -2; - } #ifndef CONFIG_SYS_I2C_DIRECT_BUS if (bus >= CONFIG_SYS_NUM_I2C_BUSES) return -1; #endif - if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0)) - return 0; + max = ll_entry_count(struct i2c_adapter, i2c); + if (I2C_ADAPTER(bus) >= max) { + printf("Error, wrong i2c adapter %d max %d possible\n", + I2C_ADAPTER(bus), max); + return -2; + } #ifndef CONFIG_SYS_I2C_DIRECT_BUS - i2c_mux_disconnet_all(); + i2c_mux_disconnect_all(); #endif gd->cur_i2c_bus = bus; @@ -348,7 +347,7 @@ unsigned int i2c_set_bus_speed(unsigned int speed) return 0; ret = I2C_ADAP->set_bus_speed(I2C_ADAP, speed); if (gd->flags & GD_FLG_RELOC) - I2C_ADAP->speed = ret; + I2C_ADAP->speed = (ret == 0) ? speed : 0; return ret; } @@ -394,9 +393,7 @@ void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val) i2c_write(addr, reg, 1, &val, 1); } -void __i2c_init(int speed, int slaveaddr) +__weak void i2c_init(int speed, int slaveaddr) { i2c_init_bus(i2c_get_bus_num(), speed, slaveaddr); } -void i2c_init(int speed, int slaveaddr) - __attribute__((weak, alias("__i2c_init"))); diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c new file mode 100644 index 0000000000..19fbe596f4 --- /dev/null +++ b/drivers/i2c/ihs_i2c.c @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2013 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + I2CINT_ERROR_EV = 1 << 13, + I2CINT_TRANSMIT_EV = 1 << 14, + I2CINT_RECEIVE_EV = 1 << 15, +}; + +enum { + I2CMB_WRITE = 1 << 10, + I2CMB_2BYTE = 1 << 11, + I2CMB_HOLD_BUS = 1 << 13, + I2CMB_NATIVE = 2 << 14, +}; + +static int wait_for_int(bool read) +{ + u16 val; + unsigned int ctr = 0; + + FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + while (!(val & (I2CINT_ERROR_EV + | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { + udelay(10); + if (ctr++ > 5000) { + return 1; + } + FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + } + + return (val & I2CINT_ERROR_EV) ? 1 : 0; +} + +static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, + bool is_last) +{ + u16 val; + + FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV + | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); + FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + + if (!read && len) { + val = buffer[0]; + + if (len > 1) + val |= buffer[1] << 8; + FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val); + } + + FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox, + I2CMB_NATIVE + | (read ? 0 : I2CMB_WRITE) + | (chip << 1) + | ((len > 1) ? I2CMB_2BYTE : 0) + | (is_last ? 0 : I2CMB_HOLD_BUS)); + + if (wait_for_int(read)) + return 1; + + if (read) { + FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val); + buffer[0] = val & 0xff; + if (len > 1) + buffer[1] = val >> 8; + } + + return 0; +} + +static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus) +{ + int shift = (alen-1) * 8; + + while (alen) { + int transfer = min(alen, 2); + uchar buf[2]; + bool is_last = alen <= transfer; + + buf[0] = addr >> shift; + if (alen > 1) + buf[1] = addr >> (shift - 8); + + if (ihs_i2c_transfer(chip, buf, transfer, false, + hold_bus ? false : is_last)) + return 1; + + shift -= 16; + alen -= transfer; + } + + return 0; +} + +static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len, bool read) +{ + if (len <= 0) + return 1; + + if (ihs_i2c_address(chip, addr, alen, !read)) + return 1; + + while (len) { + int transfer = min(len, 2); + + if (ihs_i2c_transfer(chip, buffer, transfer, read, + len <= transfer)) + return 1; + + buffer += transfer; + addr += transfer; + len -= transfer; + } + + return 0; +} + + +static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +{ +#ifdef CONFIG_SYS_I2C_INIT_BOARD + /* + * Call board specific i2c bus reset routine before accessing the + * environment, which might be in a chip on that bus. For details + * about this problem see doc/I2C_Edge_Conditions. + */ + i2c_init_board(); +#endif +} + +static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + uchar buffer[2]; + + if (ihs_i2c_transfer(chip, buffer, 0, true, true)) + return 1; + + return 0; +} + +static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true); +} + +static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false); +} + +static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + if (speed != adap->speed) + return 1; + return speed; +} + +/* + * Register IHS i2c adapters + */ +#ifdef CONFIG_SYS_I2C_IHS_CH0 +U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_0, + CONFIG_SYS_I2C_IHS_SLAVE_0, 0) +#endif +#ifdef CONFIG_SYS_I2C_IHS_CH1 +U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_1, + CONFIG_SYS_I2C_IHS_SLAVE_1, 1) +#endif +#ifdef CONFIG_SYS_I2C_IHS_CH2 +U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_2, + CONFIG_SYS_I2C_IHS_SLAVE_2, 2) +#endif +#ifdef CONFIG_SYS_I2C_IHS_CH3 +U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_3, + CONFIG_SYS_I2C_IHS_SLAVE_3, 3) +#endif diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c new file mode 100644 index 0000000000..5eab338cfc --- /dev/null +++ b/drivers/i2c/kona_i2c.c @@ -0,0 +1,730 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware register offsets and field defintions */ +#define CS_OFFSET 0x00000020 +#define CS_ACK_SHIFT 3 +#define CS_ACK_MASK 0x00000008 +#define CS_ACK_CMD_GEN_START 0x00000000 +#define CS_ACK_CMD_GEN_RESTART 0x00000001 +#define CS_CMD_SHIFT 1 +#define CS_CMD_CMD_NO_ACTION 0x00000000 +#define CS_CMD_CMD_START_RESTART 0x00000001 +#define CS_CMD_CMD_STOP 0x00000002 +#define CS_EN_SHIFT 0 +#define CS_EN_CMD_ENABLE_BSC 0x00000001 + +#define TIM_OFFSET 0x00000024 +#define TIM_PRESCALE_SHIFT 6 +#define TIM_P_SHIFT 3 +#define TIM_NO_DIV_SHIFT 2 +#define TIM_DIV_SHIFT 0 + +#define DAT_OFFSET 0x00000028 + +#define TOUT_OFFSET 0x0000002c + +#define TXFCR_OFFSET 0x0000003c +#define TXFCR_FIFO_FLUSH_MASK 0x00000080 +#define TXFCR_FIFO_EN_MASK 0x00000040 + +#define IER_OFFSET 0x00000044 +#define IER_READ_COMPLETE_INT_MASK 0x00000010 +#define IER_I2C_INT_EN_MASK 0x00000008 +#define IER_FIFO_INT_EN_MASK 0x00000002 +#define IER_NOACK_EN_MASK 0x00000001 + +#define ISR_OFFSET 0x00000048 +#define ISR_RESERVED_MASK 0xffffff60 +#define ISR_CMDBUSY_MASK 0x00000080 +#define ISR_READ_COMPLETE_MASK 0x00000010 +#define ISR_SES_DONE_MASK 0x00000008 +#define ISR_ERR_MASK 0x00000004 +#define ISR_TXFIFOEMPTY_MASK 0x00000002 +#define ISR_NOACK_MASK 0x00000001 + +#define CLKEN_OFFSET 0x0000004c +#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 +#define CLKEN_M_SHIFT 4 +#define CLKEN_N_SHIFT 1 +#define CLKEN_CLKEN_MASK 0x00000001 + +#define FIFO_STATUS_OFFSET 0x00000054 +#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 +#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 + +#define HSTIM_OFFSET 0x00000058 +#define HSTIM_HS_MODE_MASK 0x00008000 +#define HSTIM_HS_HOLD_SHIFT 10 +#define HSTIM_HS_HIGH_PHASE_SHIFT 5 +#define HSTIM_HS_SETUP_SHIFT 0 + +#define PADCTL_OFFSET 0x0000005c +#define PADCTL_PAD_OUT_EN_MASK 0x00000004 + +#define RXFCR_OFFSET 0x00000068 +#define RXFCR_NACK_EN_SHIFT 7 +#define RXFCR_READ_COUNT_SHIFT 0 +#define RXFIFORDOUT_OFFSET 0x0000006c + +/* Locally used constants */ +#define MAX_RX_FIFO_SIZE 64U /* bytes */ +#define MAX_TX_FIFO_SIZE 64U /* bytes */ + +#define I2C_TIMEOUT 100000 /* usecs */ + +#define WAIT_INT_CHK 100 /* usecs */ +#if I2C_TIMEOUT % WAIT_INT_CHK +#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK +#endif + +/* Operations that can be commanded to the controller */ +enum bcm_kona_cmd_t { + BCM_CMD_NOACTION = 0, + BCM_CMD_START, + BCM_CMD_RESTART, + BCM_CMD_STOP, +}; + +enum bus_speed_index { + BCM_SPD_100K = 0, + BCM_SPD_400K, + BCM_SPD_1MHZ, +}; + +/* Internal divider settings for standard mode, fast mode and fast mode plus */ +struct bus_speed_cfg { + uint8_t time_m; /* Number of cycles for setup time */ + uint8_t time_n; /* Number of cycles for hold time */ + uint8_t prescale; /* Prescale divider */ + uint8_t time_p; /* Timing coefficient */ + uint8_t no_div; /* Disable clock divider */ + uint8_t time_div; /* Post-prescale divider */ +}; + +static const struct bus_speed_cfg std_cfg_table[] = { + [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, + [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, + [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, +}; + +struct bcm_kona_i2c_dev { + void *base; + uint speed; + const struct bus_speed_cfg *std_cfg; +}; + +/* Keep these two defines in sync */ +#define DEF_SPD 100000 +#define DEF_SPD_ENUM BCM_SPD_100K + +#define DEF_DEVICE(num) \ +{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]} + +static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = { +#ifdef CONFIG_SYS_I2C_BASE0 + DEF_DEVICE(0), +#endif +#ifdef CONFIG_SYS_I2C_BASE1 + DEF_DEVICE(1), +#endif +#ifdef CONFIG_SYS_I2C_BASE2 + DEF_DEVICE(2), +#endif +#ifdef CONFIG_SYS_I2C_BASE3 + DEF_DEVICE(3), +#endif +#ifdef CONFIG_SYS_I2C_BASE4 + DEF_DEVICE(4), +#endif +#ifdef CONFIG_SYS_I2C_BASE5 + DEF_DEVICE(5), +#endif +}; + +#define I2C_M_TEN 0x0010 /* ten bit address */ +#define I2C_M_RD 0x0001 /* read data */ +#define I2C_M_NOSTART 0x4000 /* no restart between msgs */ + +struct i2c_msg { + uint16_t addr; + uint16_t flags; + uint16_t len; + uint8_t *buf; +}; + +static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, + enum bcm_kona_cmd_t cmd) +{ + debug("%s, %d\n", __func__, cmd); + + switch (cmd) { + case BCM_CMD_NOACTION: + writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_START: + writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | + (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_RESTART: + writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | + (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_STOP: + writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + default: + printf("Unknown command %d\n", cmd); + } +} + +static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +/* Wait until at least one of the mask bit(s) are set */ +static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev, + unsigned long time_left, + uint32_t mask) +{ + uint32_t status; + + while (time_left) { + status = readl(dev->base + ISR_OFFSET); + + if ((status & ~ISR_RESERVED_MASK) == 0) { + debug("Bogus I2C interrupt 0x%x\n", status); + continue; + } + + /* Must flush the TX FIFO when NAK detected */ + if (status & ISR_NOACK_MASK) + writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, + dev->base + TXFCR_OFFSET); + + writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); + + if (status & mask) { + /* We are done since one of the mask bits are set */ + return time_left; + } + udelay(WAIT_INT_CHK); + time_left -= WAIT_INT_CHK; + } + return 0; +} + +/* Send command to I2C bus */ +static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, + enum bcm_kona_cmd_t cmd) +{ + int rc = 0; + unsigned long time_left = I2C_TIMEOUT; + + /* Send the command */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); + + /* Wait for transaction to finish or timeout */ + time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); + + if (!time_left) { + printf("controller timed out\n"); + rc = -ETIMEDOUT; + } + + /* Clear command */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); + + return rc; +} + +/* Read a single RX FIFO worth of data from the i2c bus */ +static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, + uint8_t *buf, unsigned int len, + unsigned int last_byte_nak) +{ + unsigned long time_left = I2C_TIMEOUT; + + /* Start the RX FIFO */ + writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | + (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET); + + /* Wait for FIFO read to complete */ + time_left = + wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK); + + if (!time_left) { + printf("RX FIFO time out\n"); + return -EREMOTEIO; + } + + /* Read data from FIFO */ + for (; len > 0; len--, buf++) + *buf = readl(dev->base + RXFIFORDOUT_OFFSET); + + return 0; +} + +/* Read any amount of data using the RX FIFO from the i2c bus */ +static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; + unsigned int last_byte_nak = 0; + unsigned int bytes_read = 0; + int rc; + + uint8_t *tmp_buf = msg->buf; + + while (bytes_read < msg->len) { + if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { + last_byte_nak = 1; /* NAK last byte of transfer */ + bytes_to_read = msg->len - bytes_read; + } + + rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, + last_byte_nak); + if (rc < 0) + return -EREMOTEIO; + + bytes_read += bytes_to_read; + tmp_buf += bytes_to_read; + } + + return 0; +} + +/* Write a single byte of data to the i2c bus */ +static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, + unsigned int nak_expected) +{ + unsigned long time_left = I2C_TIMEOUT; + unsigned int nak_received; + + /* Clear pending session done interrupt */ + writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); + + /* Send one byte of data */ + writel(data, dev->base + DAT_OFFSET); + + time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); + + if (!time_left) { + debug("controller timed out\n"); + return -ETIMEDOUT; + } + + nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; + + if (nak_received ^ nak_expected) { + debug("unexpected NAK/ACK\n"); + return -EREMOTEIO; + } + + return 0; +} + +/* Write a single TX FIFO worth of data to the i2c bus */ +static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, + uint8_t *buf, unsigned int len) +{ + int k; + unsigned long time_left = I2C_TIMEOUT; + unsigned int fifo_status; + + /* Write data into FIFO */ + for (k = 0; k < len; k++) + writel(buf[k], (dev->base + DAT_OFFSET)); + + /* Wait for FIFO to empty */ + do { + time_left = + wait_for_int_timeout(dev, time_left, + (IER_FIFO_INT_EN_MASK | + IER_NOACK_EN_MASK)); + fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); + } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); + + /* Check if there was a NAK */ + if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { + printf("unexpected NAK\n"); + return -EREMOTEIO; + } + + /* Check if a timeout occured */ + if (!time_left) { + printf("completion timed out\n"); + return -EREMOTEIO; + } + + return 0; +} + +/* Write any amount of data using TX FIFO to the i2c bus */ +static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; + unsigned int bytes_written = 0; + int rc; + + uint8_t *tmp_buf = msg->buf; + + while (bytes_written < msg->len) { + if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) + bytes_to_write = msg->len - bytes_written; + + rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, + bytes_to_write); + if (rc < 0) + return -EREMOTEIO; + + bytes_written += bytes_to_write; + tmp_buf += bytes_to_write; + } + + return 0; +} + +/* Send i2c address */ +static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned char addr; + + if (msg->flags & I2C_M_TEN) { + /* First byte is 11110XX0 where XX is upper 2 bits */ + addr = 0xf0 | ((msg->addr & 0x300) >> 7); + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + + /* Second byte is the remaining 8 bits */ + addr = msg->addr & 0xff; + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + + if (msg->flags & I2C_M_RD) { + /* For read, send restart command */ + if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) + return -EREMOTEIO; + + /* Then re-send the first byte with the read bit set */ + addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01; + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + } + } else { + addr = msg->addr << 1; + + if (msg->flags & I2C_M_RD) + addr |= 1; + + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + } + + return 0; +} + +static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, + dev->base + HSTIM_OFFSET); + + writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | + (dev->std_cfg->time_p << TIM_P_SHIFT) | + (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | + (dev->std_cfg->time_div << TIM_DIV_SHIFT), + dev->base + TIM_OFFSET); + + writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | + (dev->std_cfg->time_n << CLKEN_N_SHIFT) | + CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET); +} + +/* Master transfer function */ +static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev, + struct i2c_msg msgs[], int num) +{ + struct i2c_msg *pmsg; + int rc = 0; + int i; + + /* Enable pad output */ + writel(0, dev->base + PADCTL_OFFSET); + + /* Enable internal clocks */ + bcm_kona_i2c_enable_clock(dev); + + /* Send start command */ + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); + if (rc < 0) { + printf("Start command failed rc = %d\n", rc); + goto xfer_disable_pad; + } + + /* Loop through all messages */ + for (i = 0; i < num; i++) { + pmsg = &msgs[i]; + + /* Send restart for subsequent messages */ + if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); + if (rc < 0) { + printf("restart cmd failed rc = %d\n", rc); + goto xfer_send_stop; + } + } + + /* Send slave address */ + if (!(pmsg->flags & I2C_M_NOSTART)) { + rc = bcm_kona_i2c_do_addr(dev, pmsg); + if (rc < 0) { + debug("NAK from addr %2.2x msg#%d rc = %d\n", + pmsg->addr, i, rc); + goto xfer_send_stop; + } + } + + /* Perform data transfer */ + if (pmsg->flags & I2C_M_RD) { + rc = bcm_kona_i2c_read_fifo(dev, pmsg); + if (rc < 0) { + printf("read failure\n"); + goto xfer_send_stop; + } + } else { + rc = bcm_kona_i2c_write_fifo(dev, pmsg); + if (rc < 0) { + printf("write failure"); + goto xfer_send_stop; + } + } + } + + rc = num; + +xfer_send_stop: + /* Send a STOP command */ + bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); + +xfer_disable_pad: + /* Disable pad output */ + writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); + + /* Stop internal clock */ + bcm_kona_i2c_disable_clock(dev); + + return rc; +} + +static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev, + uint speed) +{ + switch (speed) { + case 100000: + dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; + break; + case 400000: + dev->std_cfg = &std_cfg_table[BCM_SPD_400K]; + break; + case 1000000: + dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ]; + break; + default: + printf("%d hz bus speed not supported\n", speed); + return -EINVAL; + } + dev->speed = speed; + return 0; +} + +static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev) +{ + /* Parse bus speed */ + bcm_kona_i2c_assign_bus_speed(dev, dev->speed); + + /* Enable internal clocks */ + bcm_kona_i2c_enable_clock(dev); + + /* Configure internal dividers */ + bcm_kona_i2c_config_timing(dev); + + /* Disable timeout */ + writel(0, dev->base + TOUT_OFFSET); + + /* Enable autosense */ + bcm_kona_i2c_enable_autosense(dev); + + /* Enable TX FIFO */ + writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, + dev->base + TXFCR_OFFSET); + + /* Mask all interrupts */ + writel(0, dev->base + IER_OFFSET); + + /* Clear all pending interrupts */ + writel(ISR_CMDBUSY_MASK | + ISR_READ_COMPLETE_MASK | + ISR_SES_DONE_MASK | + ISR_ERR_MASK | + ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET); + + /* Enable the controller but leave it idle */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); + + /* Disable pad output */ + writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); +} + +/* + * uboot layer + */ +struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap) +{ + return &g_i2c_devs[adap->hwadapnr]; +} + +static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +{ + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + if (clk_bsc_enable(dev->base)) + return; + + bcm_kona_i2c_init(dev); +} + +static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + /* msg[0] writes the addr, msg[1] reads the data */ + struct i2c_msg msg[2]; + unsigned char msgbuf0[64]; + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + msg[0].addr = chip; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */ + + msg[1].addr = chip; + msg[1].flags = I2C_M_RD; + /* msg[1].buf dest ptr increments each read */ + + msgbuf0[0] = (unsigned char)addr; + msg[1].buf = buffer; + msg[1].len = len; + if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) { + /* Sending 2 i2c messages */ + kona_i2c_init(adap, adap->speed, adap->slaveaddr); + debug("I2C read: I/O error\n"); + return -EIO; + } + return 0; +} + +static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + struct i2c_msg msg[1]; + unsigned char msgbuf0[64]; + unsigned int i; + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + msg[0].addr = chip; + msg[0].flags = 0; + msg[0].len = 2; /* addr byte plus data */ + msg[0].buf = msgbuf0; + + for (i = 0; i < len; i++) { + msgbuf0[0] = addr++; + msgbuf0[1] = buffer[i]; + if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) { + kona_i2c_init(adap, adap->speed, adap->slaveaddr); + debug("I2C write: I/O error\n"); + return -EIO; + } + } + return 0; +} + +static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + uchar tmp; + + /* + * read addr 0x0 of the given chip. + */ + return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1); +} + +static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) +{ + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + return bcm_kona_i2c_assign_bus_speed(dev, speed); +} + +/* + * Register kona i2c adapters. Keep the order below so + * that the bus number matches the adapter number. + */ +#define DEF_ADAPTER(num) \ +U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \ + kona_i2c_read, kona_i2c_write, \ + kona_i2c_set_bus_speed, DEF_SPD, 0x00, num) + +#ifdef CONFIG_SYS_I2C_BASE0 + DEF_ADAPTER(0) +#endif +#ifdef CONFIG_SYS_I2C_BASE1 + DEF_ADAPTER(1) +#endif +#ifdef CONFIG_SYS_I2C_BASE2 + DEF_ADAPTER(2) +#endif +#ifdef CONFIG_SYS_I2C_BASE3 + DEF_ADAPTER(3) +#endif +#ifdef CONFIG_SYS_I2C_BASE4 + DEF_ADAPTER(4) +#endif +#ifdef CONFIG_SYS_I2C_BASE5 + DEF_ADAPTER(5) +#endif diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 90c8387918..9b2ca1e81b 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -20,8 +20,10 @@ #if defined(CONFIG_ORION5X) #include -#elif defined(CONFIG_KIRKWOOD) -#include +#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP)) +#include +#elif defined(CONFIG_SUNXI) +#include #else #error Driver mvtwsi not supported by SoC or board #endif @@ -30,6 +32,20 @@ * TWSI register structure */ +#ifdef CONFIG_SUNXI + +struct mvtwsi_registers { + u32 slave_address; + u32 xtnd_slave_addr; + u32 data; + u32 control; + u32 status; + u32 baudrate; + u32 soft_reset; +}; + +#else + struct mvtwsi_registers { u32 slave_address; u32 data; @@ -43,6 +59,8 @@ struct mvtwsi_registers { u32 soft_reset; }; +#endif + /* * Control register fields */ @@ -216,29 +234,14 @@ static int twsi_stop(int status) */ #define TWSI_FREQUENCY(m, n) \ - ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n)))) - -/* - * These are required to be reprogrammed before enabling the controller - * because a reset loses them. - * Default values come from the spec, but a twsi_reset will change them. - * twsi_slave_address left uninitialized lest checkpatch.pl complains. - */ - -/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */ -static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */ -/* Default frequency corresponding to default m=4, n=4 */ -static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4); -/* Default slave address is 0 (so is an uninitialized static) */ -static u8 twsi_slave_address; + (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n))) /* * Reset controller. - * Called at end of i2c_init unsuccessful i2c transactions. * Controller reset also resets the baud rate and slave address, so - * re-establish them. + * they must be re-established afterwards. */ -static void twsi_reset(void) +static void twsi_reset(struct i2c_adapter *adap) { /* ensure controller will be enabled by any twsi*() function */ twsi_control_flags = MVTWSI_CONTROL_TWSIEN; @@ -246,23 +249,17 @@ static void twsi_reset(void) writel(0, &twsi->soft_reset); /* wait 2 ms -- this is what the Marvell LSP does */ udelay(20000); - /* set baud rate */ - writel(twsi_baud_rate, &twsi->baudrate); - /* set slave address even though we don't use it */ - writel(twsi_slave_address, &twsi->slave_address); - writel(0, &twsi->xtnd_slave_addr); - /* assert STOP but don't care for the result */ - (void) twsi_stop(0); } /* * I2C init called by cmd_i2c when doing 'i2c reset'. * Sets baud to the highest possible value not exceeding requested one. */ -void i2c_init(int requested_speed, int slaveadd) +static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int requested_speed) { - int tmp_speed, highest_speed, n, m; - int baud = 0x44; /* baudrate at controller reset */ + unsigned int tmp_speed, highest_speed, n, m; + unsigned int baud = 0x44; /* baudrate at controller reset */ /* use actual speed to collect progressively higher values */ highest_speed = 0; @@ -277,12 +274,21 @@ void i2c_init(int requested_speed, int slaveadd) } } } - /* save baud rate and slave for later calls to twsi_reset */ - twsi_baud_rate = baud; - twsi_actual_speed = highest_speed; - twsi_slave_address = slaveadd; + writel(baud, &twsi->baudrate); + return 0; +} + +static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ /* reset controller */ - twsi_reset(); + twsi_reset(adap); + /* set speed */ + twsi_i2c_set_bus_speed(adap, speed); + /* set slave address even though we don't use it */ + writel(slaveadd, &twsi->slave_address); + writel(0, &twsi->xtnd_slave_addr); + /* assert STOP but don't care for the result */ + (void) twsi_stop(0); } /* @@ -312,7 +318,7 @@ static int i2c_begin(int expected_start_status, u8 addr) * I2C probe called by cmd_i2c when doing 'i2c probe'. * Begin read, nak data byte, end. */ -int i2c_probe(uchar chip) +static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) { u8 dummy_byte; int status; @@ -338,12 +344,13 @@ int i2c_probe(uchar chip) * cmd_eeprom, so we have to choose here, and for the moment that'll be * a repeated start without a preceding stop. */ -int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *data, int length) { int status; /* begin i2c write to send the address bytes */ - status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); + status = i2c_begin(MVTWSI_STATUS_START, (chip << 1)); /* send addr bytes */ while ((status == 0) && alen--) status = twsi_send(addr >> (8*alen), @@ -351,7 +358,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) /* begin i2c read to receive eeprom data bytes */ if (status == 0) status = i2c_begin( - MVTWSI_STATUS_REPEATED_START, (dev << 1) | 1); + MVTWSI_STATUS_REPEATED_START, (chip << 1) | 1); /* prepare ACK if at least one byte must be received */ if (length > 0) twsi_control_flags |= MVTWSI_CONTROL_ACK; @@ -373,12 +380,13 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c * Begin write, send address byte(s), send data bytes, end. */ -int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *data, int length) { int status; /* begin i2c write to send the eeprom adress bytes then data bytes */ - status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); + status = i2c_begin(MVTWSI_STATUS_START, (chip << 1)); /* send addr bytes */ while ((status == 0) && alen--) status = twsi_send(addr >> (8*alen), @@ -392,21 +400,7 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) return status; } -/* - * Bus set routine: we only support bus 0. - */ -int i2c_set_bus_num(unsigned int bus) -{ - if (bus > 0) { - return -1; - } - return 0; -} - -/* - * Bus get routine: hard-return bus 0. - */ -unsigned int i2c_get_bus_num(void) -{ - return 0; -} +U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, + twsi_i2c_read, twsi_i2c_write, + twsi_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 06ba4e39f1..da55c6b9b7 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -22,6 +22,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #ifdef I2C_QUIRK_REG struct mxc_i2c_regs { uint8_t iadr; @@ -102,6 +104,28 @@ static u16 i2c_clk_div[50][2] = { }; #endif + +#ifndef CONFIG_SYS_MXC_I2C1_SPEED +#define CONFIG_SYS_MXC_I2C1_SPEED 100000 +#endif +#ifndef CONFIG_SYS_MXC_I2C2_SPEED +#define CONFIG_SYS_MXC_I2C2_SPEED 100000 +#endif +#ifndef CONFIG_SYS_MXC_I2C3_SPEED +#define CONFIG_SYS_MXC_I2C3_SPEED 100000 +#endif + +#ifndef CONFIG_SYS_MXC_I2C1_SLAVE +#define CONFIG_SYS_MXC_I2C1_SLAVE 0 +#endif +#ifndef CONFIG_SYS_MXC_I2C2_SLAVE +#define CONFIG_SYS_MXC_I2C2_SLAVE 0 +#endif +#ifndef CONFIG_SYS_MXC_I2C3_SLAVE +#define CONFIG_SYS_MXC_I2C3_SLAVE 0 +#endif + + /* * Calculate and set proper clock divider */ @@ -111,7 +135,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate) unsigned int div; u8 clk_div; -#if defined(CONFIG_MX31) +#if defined(CONFIG_SOC_MX31) struct clock_control_regs *sc_regs = (struct clock_control_regs *)CCM_BASE; @@ -153,21 +177,6 @@ static int bus_i2c_set_bus_speed(void *base, int speed) return 0; } -/* - * Get I2C Speed - */ -static unsigned int bus_i2c_get_bus_speed(void *base) -{ - struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; - u8 clk_idx = readb(&i2c_regs->ifdr); - u8 clk_div; - - for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++) - ; - - return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0]; -} - #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) @@ -393,6 +402,32 @@ int bus_i2c_write(void *base, uchar chip, uint addr, int alen, return ret; } +static void * const i2c_bases[] = { +#if defined(CONFIG_SOC_MX25) + (void *)IMX_I2C_BASE, + (void *)IMX_I2C2_BASE, + (void *)IMX_I2C3_BASE +#elif defined(CONFIG_SOC_MX27) + (void *)IMX_I2C1_BASE, + (void *)IMX_I2C2_BASE +#elif defined(CONFIG_SOC_MX31) || defined(CONFIG_SOC_MX35) || \ + defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || \ + defined(CONFIG_SOC_MX6) || defined(CONFIG_SOC_LS102XA) + (void *)I2C1_BASE_ADDR, + (void *)I2C2_BASE_ADDR, + (void *)I2C3_BASE_ADDR +#elif defined(CONFIG_SOC_VF610) + (void *)I2C0_BASE_ADDR +#elif defined(CONFIG_FSL_LSCH3) + (void *)I2C1_BASE_ADDR, + (void *)I2C2_BASE_ADDR, + (void *)I2C3_BASE_ADDR, + (void *)I2C4_BASE_ADDR +#else +#error "architecture not supported" +#endif +}; + struct i2c_parms { void *base; void *idle_bus_data; @@ -401,36 +436,20 @@ struct i2c_parms { struct sram_data { unsigned curr_i2c_bus; - struct i2c_parms i2c_data[3]; + struct i2c_parms i2c_data[ARRAY_SIZE(i2c_bases)]; }; -/* - * For SPL boot some boards need i2c before SDRAM is initialized so force - * variables to live in SRAM - */ -static struct sram_data __attribute__((section(".data"))) srdata; - -void *get_base(void) +void *i2c_get_base(struct i2c_adapter *adap) { -#ifdef CONFIG_SYS_I2C_BASE -#ifdef CONFIG_I2C_MULTI_BUS - void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base; - if (ret) - return ret; -#endif - return (void *)CONFIG_SYS_I2C_BASE; -#elif defined(CONFIG_I2C_MULTI_BUS) - return srdata.i2c_data[srdata.curr_i2c_bus].base; -#else - return srdata.i2c_data[0].base; -#endif + return i2c_bases[adap->hwadapnr]; } static struct i2c_parms *i2c_get_parms(void *base) { + struct sram_data *srdata = (void *)gd->srdata; int i = 0; - struct i2c_parms *p = srdata.i2c_data; - while (i < ARRAY_SIZE(srdata.i2c_data)) { + struct i2c_parms *p = srdata->i2c_data; + while (i < ARRAY_SIZE(srdata->i2c_data)) { if (p->base == base) return p; p++; @@ -448,46 +467,34 @@ static int i2c_idle_bus(void *base) return 0; } -#ifdef CONFIG_I2C_MULTI_BUS -unsigned int i2c_get_bus_num(void) +static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, + int len) { - return srdata.curr_i2c_bus; + return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); } -int i2c_set_bus_num(unsigned bus_idx) +static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, + int len) { - if (bus_idx >= ARRAY_SIZE(srdata.i2c_data)) - return -1; - if (!srdata.i2c_data[bus_idx].base) - return -1; - srdata.curr_i2c_bus = bus_idx; - return 0; -} -#endif - -int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - return bus_i2c_read(get_base(), chip, addr, alen, buf, len); -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - return bus_i2c_write(get_base(), chip, addr, alen, buf, len); + return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); } /* * Test if a chip at a given address responds (probe the chip) */ -int i2c_probe(uchar chip) +static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) { - return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0); + return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); } void bus_i2c_init(void *base, int speed, int unused, int (*idle_bus_fn)(void *p), void *idle_bus_data) { + struct sram_data *srdata = (void *)gd->srdata; int i = 0; - struct i2c_parms *p = srdata.i2c_data; + struct i2c_parms *p = srdata->i2c_data; if (!base) return; for (;;) { @@ -501,7 +508,7 @@ void bus_i2c_init(void *base, int speed, int unused, } p++; i++; - if (i >= ARRAY_SIZE(srdata.i2c_data)) + if (i >= ARRAY_SIZE(srdata->i2c_data)) return; } bus_i2c_set_bus_speed(base, speed); @@ -510,23 +517,38 @@ void bus_i2c_init(void *base, int speed, int unused, /* * Init I2C Bus */ -void i2c_init(int speed, int unused) +static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { - bus_i2c_init(get_base(), speed, unused, NULL, NULL); + bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL); } /* * Set I2C Speed */ -int i2c_set_bus_speed(unsigned int speed) +static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) { - return bus_i2c_set_bus_speed(get_base(), speed); + return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); } /* - * Get I2C Speed + * Register mxc i2c adapters */ -unsigned int i2c_get_bus_speed(void) -{ - return bus_i2c_get_bus_speed(get_base()); -} +U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C1_SPEED, + CONFIG_SYS_MXC_I2C1_SLAVE, 0) +U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C2_SPEED, + CONFIG_SYS_MXC_I2C2_SLAVE, 1) +#if defined(CONFIG_SOC_MX31) || defined(CONFIG_SOC_MX35) ||\ + defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) ||\ + defined(CONFIG_SOC_MX6) || defined(CONFIG_SOC_LS102XA) +U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C3_SPEED, + CONFIG_SYS_MXC_I2C3_SLAVE, 2) +#endif diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c index 46106b7712..87e05c7125 100644 --- a/drivers/i2c/mxs_i2c.c +++ b/drivers/i2c/mxs_i2c.c @@ -24,11 +24,74 @@ #define MXS_I2C_MAX_TIMEOUT 1000000 -static void mxs_i2c_reset(void) +static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap) { - struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; + if (adap->hwadapnr == 0) + return (struct mxs_i2c_regs *)MXS_I2C0_BASE; + else + return (struct mxs_i2c_regs *)MXS_I2C1_BASE; +} + +static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap) +{ + struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); + uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); + uint32_t timing0; + + timing0 = readl(&i2c_regs->hw_i2c_timing0); + /* + * This is a reverse version of the algorithm presented in + * i2c_set_bus_speed(). Please refer there for details. + */ + return clk / ((((timing0 >> 16) - 3) * 2) + 38); +} + +static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) +{ + struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); + /* + * The timing derivation algorithm. There is no documentation for this + * algorithm available, it was derived by using the scope and fiddling + * with constants until the result observed on the scope was good enough + * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be + * possible to assume the algorithm works for other frequencies as well. + * + * Note it was necessary to cap the frequency on both ends as it's not + * possible to configure completely arbitrary frequency for the I2C bus + * clock. + */ + uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); + uint32_t base = ((clk / speed) - 38) / 2; + uint16_t high_count = base + 3; + uint16_t low_count = base - 3; + uint16_t rcv_count = (high_count * 3) / 4; + uint16_t xmit_count = low_count / 4; + + if (speed > 540000) { + printf("MXS I2C: Speed too high (%d Hz)\n", speed); + return -EINVAL; + } + + if (speed < 12000) { + printf("MXS I2C: Speed too low (%d Hz)\n", speed); + return -EINVAL; + } + + writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0); + writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1); + + writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) | + (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET), + &i2c_regs->hw_i2c_timing2); + + return 0; +} + +static void mxs_i2c_reset(struct i2c_adapter *adap) +{ + struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); int ret; - int speed = i2c_get_bus_speed(); + int speed = mxs_i2c_get_bus_speed(adap); ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg); if (ret) { @@ -43,12 +106,12 @@ static void mxs_i2c_reset(void) writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set); - i2c_set_bus_speed(speed); + mxs_i2c_set_bus_speed(adap, speed); } -static void mxs_i2c_setup_read(uint8_t chip, int len) +static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len) { - struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; + struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START | I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | @@ -64,16 +127,17 @@ static void mxs_i2c_setup_read(uint8_t chip, int len) writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); } -static void mxs_i2c_write(uchar chip, uint addr, int alen, - uchar *buf, int blen, int stop) +static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buf, int blen, int stop) { - struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; - uint32_t data; + struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); + uint32_t data, tmp; int i, remain, off; + int timeout = MXS_I2C_MAX_TIMEOUT; if ((alen > 4) || (alen == 0)) { debug("MXS I2C: Invalid address length\n"); - return; + return -EINVAL; } if (stop) @@ -106,11 +170,24 @@ static void mxs_i2c_write(uchar chip, uint addr, int alen, writel(data >> remain, &i2c_regs->hw_i2c_data); writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); + + while (--timeout) { + tmp = readl(&i2c_regs->hw_i2c_queuestat); + if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY) + break; + } + + if (!timeout) { + debug("MXS I2C: Failed transmitting data!\n"); + return -EINVAL; + } + + return 0; } -static int mxs_i2c_wait_for_ack(void) +static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap) { - struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; + struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); uint32_t tmp; int timeout = MXS_I2C_MAX_TIMEOUT; @@ -142,26 +219,34 @@ static int mxs_i2c_wait_for_ack(void) return 0; err: - mxs_i2c_reset(); + mxs_i2c_reset(adap); return 1; } -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, + int len) { - struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; + struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); uint32_t tmp = 0; + int timeout = MXS_I2C_MAX_TIMEOUT; int ret; int i; - mxs_i2c_write(chip, addr, alen, NULL, 0, 0); - ret = mxs_i2c_wait_for_ack(); + ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0); if (ret) { debug("MXS I2C: Failed writing address\n"); return ret; } - mxs_i2c_setup_read(chip, len); - ret = mxs_i2c_wait_for_ack(); + ret = mxs_i2c_wait_for_ack(adap); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + + mxs_i2c_setup_read(adap, chip, len); + ret = mxs_i2c_wait_for_ack(adap); if (ret) { debug("MXS I2C: Failed reading address\n"); return ret; @@ -169,9 +254,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) for (i = 0; i < len; i++) { if (!(i & 3)) { - while (readl(&i2c_regs->hw_i2c_queuestat) & - I2C_QUEUESTAT_RD_QUEUE_EMPTY) - ; + while (--timeout) { + tmp = readl(&i2c_regs->hw_i2c_queuestat); + if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY)) + break; + } + + if (!timeout) { + debug("MXS I2C: Failed receiving data!\n"); + return -ETIMEDOUT; + } + tmp = readl(&i2c_regs->hw_i2c_queuedata); } buffer[i] = tmp & 0xff; @@ -181,85 +274,47 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) return 0; } -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, + int len) { int ret; - mxs_i2c_write(chip, addr, alen, buffer, len, 1); - ret = mxs_i2c_wait_for_ack(); + ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + + ret = mxs_i2c_wait_for_ack(adap); if (ret) debug("MXS I2C: Failed writing address\n"); return ret; } -int i2c_probe(uchar chip) +static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip) { int ret; - mxs_i2c_write(chip, 0, 1, NULL, 0, 1); - ret = mxs_i2c_wait_for_ack(); - mxs_i2c_reset(); + ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1); + if (!ret) + ret = mxs_i2c_wait_for_ack(adap); + mxs_i2c_reset(adap); return ret; } -int i2c_set_bus_speed(unsigned int speed) +static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { - struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; - /* - * The timing derivation algorithm. There is no documentation for this - * algorithm available, it was derived by using the scope and fiddling - * with constants until the result observed on the scope was good enough - * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be - * possible to assume the algorithm works for other frequencies as well. - * - * Note it was necessary to cap the frequency on both ends as it's not - * possible to configure completely arbitrary frequency for the I2C bus - * clock. - */ - uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); - uint32_t base = ((clk / speed) - 38) / 2; - uint16_t high_count = base + 3; - uint16_t low_count = base - 3; - uint16_t rcv_count = (high_count * 3) / 4; - uint16_t xmit_count = low_count / 4; - - if (speed > 540000) { - printf("MXS I2C: Speed too high (%d Hz)\n", speed); - return -EINVAL; - } - - if (speed < 12000) { - printf("MXS I2C: Speed too low (%d Hz)\n", speed); - return -EINVAL; - } - - writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0); - writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1); - - writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) | - (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET), - &i2c_regs->hw_i2c_timing2); - - return 0; -} - -unsigned int i2c_get_bus_speed(void) -{ - struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; - uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); - uint32_t timing0; - - timing0 = readl(&i2c_regs->hw_i2c_timing0); - /* - * This is a reverse version of the algorithm presented in - * i2c_set_bus_speed(). Please refer there for details. - */ - return clk / ((((timing0 >> 16) - 3) * 2) + 38); -} - -void i2c_init(int speed, int slaveadd) -{ - mxs_i2c_reset(); - i2c_set_bus_speed(speed); + mxs_i2c_reset(adap); + mxs_i2c_set_bus_speed(adap, speed); return; } + +U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe, + mxs_i2c_if_read, mxs_i2c_if_write, + mxs_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED, 0, 0) +U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe, + mxs_i2c_if_read, mxs_i2c_if_write, + mxs_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED, 0, 1) diff --git a/drivers/i2c/omap1510_i2c.c b/drivers/i2c/omap1510_i2c.c deleted file mode 100644 index f91ee8884a..0000000000 --- a/drivers/i2c/omap1510_i2c.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Basic I2C functions - * - * Copyright (c) 2003 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Author: Jian Zhang jzhang@ti.com, Texas Instruments - * - * Copyright (c) 2003 Wolfgang Denk, wd@denx.de - * Rewritten to fit into the current U-Boot framework - * - */ - -#include - -static void wait_for_bb (void); -static u16 wait_for_pin (void); - -void i2c_init (int speed, int slaveadd) -{ - u16 scl; - - if (inw (I2C_CON) & I2C_CON_EN) { - outw (0, I2C_CON); - udelay (5000); - } - - /* 12MHz I2C module clock */ - outw (0, I2C_PSC); - outw (I2C_CON_EN, I2C_CON); - outw (0, I2C_SYSTEST); - /* have to enable intrrupts or OMAP i2c module doesn't work */ - outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); - scl = (12000000 / 2) / speed - 6; - outw (scl, I2C_SCLL); - outw (scl, I2C_SCLH); - /* own address */ - outw (slaveadd, I2C_OA); - outw (0, I2C_CNT); - udelay (1000); -} - -static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) -{ - int i2c_error = 0; - u16 status; - - /* wait until bus not busy */ - wait_for_bb (); - - /* one byte only */ - outw (1, I2C_CNT); - /* set slave address */ - outw (devaddr, I2C_SA); - /* no stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); - - status = wait_for_pin (); - - if (status & I2C_STAT_XRDY) { - /* Important: have to use byte access */ - *(volatile u8 *) (I2C_DATA) = regoffset; - udelay (20000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { - i2c_error = 1; - } - } else { - i2c_error = 1; - } - - if (!i2c_error) { - /* free bus, otherwise we can't use a combined transction */ - outw (0, I2C_CON); - while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (10000); - /* Have to clear pending interrupt to clear I2C_STAT */ - inw (I2C_IV); - } - - wait_for_bb (); - /* set slave address */ - outw (devaddr, I2C_SA); - /* read one byte from slave */ - outw (1, I2C_CNT); - /* need stop bit here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); - - status = wait_for_pin (); - if (status & I2C_STAT_RRDY) { - *value = inw (I2C_DATA); - udelay (20000); - } else { - i2c_error = 1; - } - - if (!i2c_error) { - outw (I2C_CON_EN, I2C_CON); - while (inw (I2C_STAT) - || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (10000); - inw (I2C_IV); - } - } - } - - return i2c_error; -} - -static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) -{ - int i2c_error = 0; - u16 status; - - /* wait until bus not busy */ - wait_for_bb (); - - /* two bytes */ - outw (2, I2C_CNT); - /* set slave address */ - outw (devaddr, I2C_SA); - /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); - - /* wait until state change */ - status = wait_for_pin (); - - if (status & I2C_STAT_XRDY) { - /* send out two bytes */ - outw ((value << 8) + regoffset, I2C_DATA); - /* must have enough delay to allow BB bit to go low */ - udelay (30000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { - i2c_error = 1; - } - } else { - i2c_error = 1; - } - - if (!i2c_error) { - outw (I2C_CON_EN, I2C_CON); - while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (1000); - /* have to read to clear intrrupt */ - inw (I2C_IV); - } - } - - return i2c_error; -} - -int i2c_probe (uchar chip) -{ - int res = 1; - - if (chip == inw (I2C_OA)) { - return res; - } - - /* wait until bus not busy */ - wait_for_bb (); - - /* try to read one byte */ - outw (1, I2C_CNT); - /* set slave address */ - outw (chip, I2C_SA); - /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); - /* enough delay for the NACK bit set */ - udelay (2000); - if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { - res = 0; - } else { - outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); - udelay (20); - wait_for_bb (); - } - - return res; -} - -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - int i; - - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf ("I2C read: address out of range\n"); - return 1; - } - - for (i = 0; i < len; i++) { - if (i2c_read_byte (chip, addr + i, &buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; - } - } - - return 0; -} - -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - int i; - - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf ("I2C read: address out of range\n"); - return 1; - } - - for (i = 0; i < len; i++) { - if (i2c_write_byte (chip, addr + i, buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; - } - } - - return 0; -} - -static void wait_for_bb (void) -{ - int timeout = 10; - - while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - inw (I2C_IV); - udelay (1000); - } - - if (timeout <= 0) { - printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - inw (I2C_STAT)); - } -} - -static u16 wait_for_pin (void) -{ - u16 status, iv; - int timeout = 10; - - do { - udelay (1000); - status = inw (I2C_STAT); - iv = inw (I2C_IV); - } while (!iv && - !(status & - (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | - I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | - I2C_STAT_AL)) && timeout--); - - if (timeout <= 0) { - printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - inw (I2C_STAT)); - } - - return status; -} diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index ef38d71725..0f1e35c460 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -32,9 +32,14 @@ * - Status functions now read irqstatus_raw as per TRM guidelines * (except for OMAP243X and OMAP34XX). * - Driver now supports up to I2C5 (OMAP5). + * + * Copyright (c) 2014 Hannes Petermaier , B&R + * - Added support for set_speed + * */ #include +#include #include #include @@ -48,55 +53,70 @@ DECLARE_GLOBAL_DATA_PTR; /* Absolutely safe for status update at 100 kHz I2C: */ #define I2C_WAIT 200 -static int wait_for_bb(void); -static u16 wait_for_event(void); -static void flush_fifo(void); +static int wait_for_bb(struct i2c_adapter *adap); +static struct i2c *omap24_get_base(struct i2c_adapter *adap); +static u16 wait_for_event(struct i2c_adapter *adap); +static void flush_fifo(struct i2c_adapter *adap); +static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) +{ + unsigned int sampleclk, prescaler; + int fsscll, fssclh; -/* - * For SPL boot some boards need i2c before SDRAM is initialised so force - * variables to live in SRAM - */ -static struct i2c __attribute__((section (".data"))) *i2c_base = - (struct i2c *)I2C_DEFAULT_BASE; -static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = - { [0 ... (I2C_BUS_MAX-1)] = 0 }; -static unsigned int __attribute__((section (".data"))) current_bus = 0; + speed <<= 1; + prescaler = 0; + /* + * some divisors may cause a precission loss, but shouldn't + * be a big thing, because i2c_clk is then allready very slow. + */ + while (prescaler <= 0xFF) { + sampleclk = I2C_IP_CLK / (prescaler+1); -void i2c_init(int speed, int slaveadd) -{ - int psc, fsscll, fssclh; - int hsscll = 0, hssclh = 0; - u32 scll, sclh; - int timeout = I2C_TIMEOUT; + fsscll = sampleclk / speed; + fssclh = fsscll; + fsscll -= I2C_FASTSPEED_SCLL_TRIM; + fssclh -= I2C_FASTSPEED_SCLH_TRIM; - /* Only handle standard, fast and high speeds */ - if ((speed != OMAP_I2C_STANDARD) && - (speed != OMAP_I2C_FAST_MODE) && - (speed != OMAP_I2C_HIGH_SPEED)) { - printf("Error : I2C unsupported speed %d\n", speed); - return; - } + if (((fsscll > 0) && (fssclh > 0)) && + ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) && + (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) { + if (pscl) + *pscl = fsscll; + if (psch) + *psch = fssclh; - psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; - psc -= 1; - if (psc < I2C_PSC_MIN) { - printf("Error : I2C unsupported prescalar %d\n", psc); - return; + return prescaler; + } + prescaler++; } + return -1; +} +static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int psc, fsscll = 0, fssclh = 0; + int hsscll = 0, hssclh = 0; + u32 scll = 0, sclh = 0; - if (speed == OMAP_I2C_HIGH_SPEED) { + if (speed >= OMAP_I2C_HIGH_SPEED) { /* High speed */ + psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; + psc -= 1; + if (psc < I2C_PSC_MIN) { + printf("Error : I2C unsupported prescaler %d\n", psc); + return -1; + } /* For first phase of HS mode */ - fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / - (2 * OMAP_I2C_FAST_MODE); + fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); + + fssclh = fsscll; fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing first phase clock\n"); - return; + return -1; } /* For second phase of HS mode */ @@ -107,7 +127,7 @@ void i2c_init(int speed, int slaveadd) if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing second phase clock\n"); - return; + return -1; } scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; @@ -115,20 +135,78 @@ void i2c_init(int speed, int slaveadd) } else { /* Standard and fast speed */ - fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); - - fsscll -= I2C_FASTSPEED_SCLL_TRIM; - fssclh -= I2C_FASTSPEED_SCLH_TRIM; - if (((fsscll < 0) || (fssclh < 0)) || - ((fsscll > 255) || (fssclh > 255))) { + psc = omap24_i2c_findpsc(&scll, &sclh, speed); + if (0 > psc) { puts("Error : I2C initializing clock\n"); - return; + return -1; } + } + + adap->speed = speed; + adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ + writew(0, &i2c_base->con); + writew(psc, &i2c_base->psc); + writew(scll, &i2c_base->scll); + writew(sclh, &i2c_base->sclh); + writew(I2C_CON_EN, &i2c_base->con); + writew(0xFFFF, &i2c_base->stat); /* clear all pending status */ + + return 0; +} - scll = (unsigned int)fsscll; - sclh = (unsigned int)fssclh; +static void omap24_i2c_deblock(struct i2c_adapter *adap) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int i; + u16 systest; + u16 orgsystest; + + /* set test mode ST_EN = 1 */ + orgsystest = readw(&i2c_base->systest); + systest = orgsystest; + /* enable testmode */ + systest |= I2C_SYSTEST_ST_EN; + writew(systest, &i2c_base->systest); + systest &= ~I2C_SYSTEST_TMODE_MASK; + systest |= 3 << I2C_SYSTEST_TMODE_SHIFT; + writew(systest, &i2c_base->systest); + + /* set SCL, SDA = 1 */ + systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; + writew(systest, &i2c_base->systest); + udelay(10); + + /* toggle scl 9 clocks */ + for (i = 0; i < 9; i++) { + /* SCL = 0 */ + systest &= ~I2C_SYSTEST_SCL_O; + writew(systest, &i2c_base->systest); + udelay(10); + /* SCL = 1 */ + systest |= I2C_SYSTEST_SCL_O; + writew(systest, &i2c_base->systest); + udelay(10); } + /* send stop */ + systest &= ~I2C_SYSTEST_SDA_O; + writew(systest, &i2c_base->systest); + udelay(10); + systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; + writew(systest, &i2c_base->systest); + udelay(10); + + /* restore original mode */ + writew(orgsystest, &i2c_base->systest); +} + +static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int timeout = I2C_TIMEOUT; + int deblock = 1; + +retry: if (readw(&i2c_base->con) & I2C_CON_EN) { writew(0, &i2c_base->con); udelay(50000); @@ -146,14 +224,14 @@ void i2c_init(int speed, int slaveadd) udelay(1000); } - writew(0, &i2c_base->con); - writew(psc, &i2c_base->psc); - writew(scll, &i2c_base->scll); - writew(sclh, &i2c_base->sclh); + if (0 != omap24_i2c_setspeed(adap, speed)) { + printf("ERROR: failed to setup I2C bus-speed!\n"); + return; + } /* own address */ writew(slaveadd, &i2c_base->oa); - writew(I2C_CON_EN, &i2c_base->con); + #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* * Have to enable interrupts for OMAP2/3, these IPs don't have @@ -163,18 +241,25 @@ void i2c_init(int speed, int slaveadd) I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); #endif udelay(1000); - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); - writew(0, &i2c_base->cnt); - if (gd->flags & GD_FLG_RELOC) - bus_initialized[current_bus] = 1; + /* Handle possible failed I2C state */ + if (wait_for_bb(adap)) + if (deblock == 1) { + omap24_i2c_deblock(adap); + deblock = 0; + goto retry; + } } -static void flush_fifo(void) -{ u16 stat; +static void flush_fifo(struct i2c_adapter *adap) +{ + struct i2c *i2c_base = omap24_get_base(adap); + u16 stat; - /* note: if you try and read data when its not there or ready + /* + * note: if you try and read data when its not there or ready * you get a bus error */ while (1) { @@ -192,8 +277,9 @@ static void flush_fifo(void) * i2c_probe: Use write access. Allows to identify addresses that are * write-only (like the config register of dual-port EEPROMs) */ -int i2c_probe(uchar chip) +static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) { + struct i2c *i2c_base = omap24_get_base(adap); u16 status; int res = 1; /* default = fail */ @@ -201,18 +287,16 @@ int i2c_probe(uchar chip) return res; /* Wait until bus is free */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return res; /* No data transfer, slave addr only */ - writew(0, &i2c_base->cnt); - /* Set slave address */ writew(chip, &i2c_base->sa); /* Stop bit needed here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); - status = wait_for_event(); + status = wait_for_event(adap); if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { /* @@ -223,15 +307,15 @@ int i2c_probe(uchar chip) */ if (status == I2C_STAT_XRDY) printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto pr_exit; } /* Check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) { - res = 0; /* Device found */ - udelay(I2C_WAIT); /* Required by AM335X in SPL */ + res = 0; /* Device found */ + udelay(adap->waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ udelay(1000); @@ -239,9 +323,8 @@ int i2c_probe(uchar chip) I2C_CON_STP, &i2c_base->con); /* STP */ } pr_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); - writew(0, &i2c_base->cnt); return res; } @@ -258,8 +341,10 @@ pr_exit: * or that do not need a register address at all (such as some clock * distributors). */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) { + struct i2c *i2c_base = omap24_get_base(adap); int i2c_error = 0; u16 status; @@ -287,7 +372,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Wait until bus not busy */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return 1; /* Zero, one or two bytes reg address (offset) */ @@ -308,15 +393,15 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) #endif /* Send register offset */ while (1) { - status = wait_for_event(); + status = wait_for_event(adap); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto rd_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", status); @@ -348,7 +433,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) /* Receive data */ while (1) { - status = wait_for_event(); + status = wait_for_event(adap); /* * Try to identify bus that is not padconf'd for I2C. This * state could be left over from previous transactions if @@ -357,10 +442,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto rd_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; goto rd_exit; } @@ -375,18 +460,20 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } rd_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); - writew(0, &i2c_base->cnt); return i2c_error; } /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) { + struct i2c *i2c_base = omap24_get_base(adap); int i; u16 status; int i2c_error = 0; + int timeout = I2C_TIMEOUT; if (alen < 0) { puts("I2C write: addr len < 0\n"); @@ -415,7 +502,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Wait until bus not busy */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return 1; /* Start address phase - will write regoffset + len bytes data */ @@ -428,15 +515,15 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) while (alen) { /* Must write reg offset (one or two bytes) */ - status = wait_for_event(); + status = wait_for_event(adap); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto wr_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", status); @@ -455,8 +542,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Address phase is over, now write data */ for (i = 0; i < len; i++) { - status = wait_for_event(); - if (status == 0 || status & I2C_STAT_NACK) { + status = wait_for_event(adap); + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", status); @@ -472,11 +559,19 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) goto wr_exit; } } + /* + * poll ARDY bit for making sure that last byte really has been + * transferred on the bus. + */ + do { + status = wait_for_event(adap); + } while (!(status & I2C_STAT_ARDY) && timeout--); + if (timeout <= 0) + printf("i2c_write: timed out writig last byte!\n"); wr_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); - writew(0, &i2c_base->cnt); return i2c_error; } @@ -484,8 +579,9 @@ wr_exit: * Wait for the bus to be free by checking the Bus Busy (BB) * bit to become clear */ -static int wait_for_bb(void) +static int wait_for_bb(struct i2c_adapter *adap) { + struct i2c *i2c_base = omap24_get_base(adap); int timeout = I2C_TIMEOUT; u16 stat; @@ -498,7 +594,7 @@ static int wait_for_bb(void) I2C_STAT_BB) && timeout--) { #endif writew(stat, &i2c_base->stat); - udelay(I2C_WAIT); + udelay(adap->waitdelay); } if (timeout <= 0) { @@ -514,13 +610,14 @@ static int wait_for_bb(void) * Wait for the I2C controller to complete current action * and update status */ -static u16 wait_for_event(void) +static u16 wait_for_event(struct i2c_adapter *adap) { + struct i2c *i2c_base = omap24_get_base(adap); u16 status; int timeout = I2C_TIMEOUT; do { - udelay(I2C_WAIT); + udelay(adap->waitdelay); #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) status = readw(&i2c_base->stat); #else @@ -540,7 +637,7 @@ static u16 wait_for_event(void) * not been configured for I2C, and/or pull-ups are missing. */ printf("Check if pads/pull-ups of bus %d are properly configured\n", - current_bus); + adap->hwadapnr); writew(0xFFFF, &i2c_base->stat); status = 0; } @@ -548,48 +645,93 @@ static u16 wait_for_event(void) return status; } -int i2c_set_bus_num(unsigned int bus) +static struct i2c *omap24_get_base(struct i2c_adapter *adap) { - if (bus >= I2C_BUS_MAX) { - printf("Bad bus: %x\n", bus); - return -1; - } - - switch (bus) { - default: - bus = 0; /* Fall through */ + switch (adap->hwadapnr) { case 0: - i2c_base = (struct i2c *)I2C_BASE1; + return (struct i2c *)I2C_BASE1; break; case 1: - i2c_base = (struct i2c *)I2C_BASE2; + return (struct i2c *)I2C_BASE2; break; #if (I2C_BUS_MAX > 2) case 2: - i2c_base = (struct i2c *)I2C_BASE3; + return (struct i2c *)I2C_BASE3; break; #if (I2C_BUS_MAX > 3) case 3: - i2c_base = (struct i2c *)I2C_BASE4; + return (struct i2c *)I2C_BASE4; break; #if (I2C_BUS_MAX > 4) case 4: - i2c_base = (struct i2c *)I2C_BASE5; + return (struct i2c *)I2C_BASE5; break; #endif #endif #endif + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + break; } + return NULL; +} - current_bus = bus; +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) +#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) +#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif - if (!bus_initialized[current_bus]) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, + CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE, + 0) +U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, + CONFIG_SYS_OMAP24_I2C_SPEED1, + CONFIG_SYS_OMAP24_I2C_SLAVE1, + 1) +#if (I2C_BUS_MAX > 2) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) +#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) +#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif - return 0; -} +U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED2, + CONFIG_SYS_OMAP24_I2C_SLAVE2, + 2) +#if (I2C_BUS_MAX > 3) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) +#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) +#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif -int i2c_get_bus_num(void) -{ - return (int) current_bus; -} +U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED3, + CONFIG_SYS_OMAP24_I2C_SLAVE3, + 3) +#if (I2C_BUS_MAX > 4) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) +#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) +#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif + +U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED4, + CONFIG_SYS_OMAP24_I2C_SLAVE4, + 4) +#endif +#endif +#endif diff --git a/drivers/i2c/ppc4xx_i2c.c b/drivers/i2c/ppc4xx_i2c.c index e7a15ba644..df8888550b 100644 --- a/drivers/i2c/ppc4xx_i2c.c +++ b/drivers/i2c/ppc4xx_i2c.c @@ -158,8 +158,7 @@ static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) * * Typical case is a Write of an addr followd by a Read. The * IBM FAQ does not cover this. On the last byte of the write - * we don't set the creg CHT bit, and on the first bytes of the - * read we set the RPST bit. + * we don't set the creg CHT bit but the RPST bit. * * It does not support address only transfers, there must be * a data part. If you want to write the address yourself, put @@ -247,6 +246,10 @@ static int _i2c_transfer(struct i2c_adapter *adap, if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) creg |= IIC_CNTL_CHT; + /* last part of address, prepare for repeated start on read */ + if (cmd_type && (ptr == addr) && ((tran + bc) == cnt)) + creg |= IIC_CNTL_RPST; + if (reading) { creg |= IIC_CNTL_READ; } else { @@ -286,6 +289,27 @@ static int _i2c_transfer(struct i2c_adapter *adap, /* Transfer aborted? */ if (status & IIC_EXTSTS_XFRA) result = IIC_NOK_XFRA; + /* Is bus free? + * If error happened during combined xfer + * IIC interface is usually stuck in some strange + * state without a valid stop condition. + * Brute, but working: generate stop, then soft reset. + */ + if ((status & IIC_EXTSTS_BCS_MASK) + != IIC_EXTSTS_BCS_FREE){ + u8 mdcntl = in_8(&i2c->mdcntl); + + /* Generate valid stop condition */ + out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); + out_8(&i2c->directcntl, IIC_DIRCNTL_SCC); + udelay(10); + out_8(&i2c->directcntl, + IIC_DIRCNTL_SCC | IIC_DIRCNTL_SDAC); + out_8(&i2c->xtcntlss, 0); + + ppc4xx_i2c_init(adap, (mdcntl & IIC_MDCNTL_FSM) + ? 400000 : 100000, 0); + } } else if ( status & IIC_STS_PT) { result = IIC_NOK_TOUT; } @@ -314,8 +338,6 @@ static int _i2c_transfer(struct i2c_adapter *adap, cnt = data_len; tran = 0; reading = cmd_type; - if (reading) - creg = IIC_CNTL_RPST; } } return result; diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c new file mode 100644 index 0000000000..90ad116a98 --- /dev/null +++ b/drivers/i2c/rcar_i2c.c @@ -0,0 +1,290 @@ +/* + * drivers/i2c/rcar_i2c.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct rcar_i2c { + u32 icscr; + u32 icmcr; + u32 icssr; + u32 icmsr; + u32 icsier; + u32 icmier; + u32 icccr; + u32 icsar; + u32 icmar; + u32 icrxdtxd; + u32 icccr2; + u32 icmpr; + u32 ichpr; + u32 iclpr; +}; + +#define MCR_MDBS 0x80 /* non-fifo mode switch */ +#define MCR_FSCL 0x40 /* override SCL pin */ +#define MCR_FSDA 0x20 /* override SDA pin */ +#define MCR_OBPC 0x10 /* override pins */ +#define MCR_MIE 0x08 /* master if enable */ +#define MCR_TSBE 0x04 +#define MCR_FSB 0x02 /* force stop bit */ +#define MCR_ESG 0x01 /* en startbit gen. */ + +#define MSR_MASK 0x7f +#define MSR_MNR 0x40 /* nack received */ +#define MSR_MAL 0x20 /* arbitration lost */ +#define MSR_MST 0x10 /* sent a stop */ +#define MSR_MDE 0x08 +#define MSR_MDT 0x04 +#define MSR_MDR 0x02 +#define MSR_MAT 0x01 /* slave addr xfer done */ + +static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = { + (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE, + (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE, + (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE, + (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE, +}; + +static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr) +{ + /* set slave address */ + writel(chip << 1, &dev->icmar); + /* set register address */ + writel(addr, &dev->icrxdtxd); + /* clear status */ + writel(0, &dev->icmsr); + /* start master send */ + writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); + + while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE)) + != (MSR_MAT | MSR_MDE)) + udelay(10); + + /* clear ESG */ + writel(MCR_MDBS | MCR_MIE, &dev->icmcr); + /* start SCLclk */ + writel(~(MSR_MAT | MSR_MDE), &dev->icmsr); + + while (!(readl(&dev->icmsr) & MSR_MDE)) + udelay(10); +} + +static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev) +{ + while (!(readl(&dev->icmsr) & MSR_MST)) + udelay(10); + + writel(0, &dev->icmcr); +} + +static int +rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size) +{ + rcar_i2c_raw_rw_common(dev, chip, addr); + + /* set send date */ + writel(*val, &dev->icrxdtxd); + /* start SCLclk */ + writel(~MSR_MDE, &dev->icmsr); + + while (!(readl(&dev->icmsr) & MSR_MDE)) + udelay(10); + + /* set stop condition */ + writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); + /* start SCLclk */ + writel(~MSR_MDE, &dev->icmsr); + + rcar_i2c_raw_rw_finish(dev); + + return 0; +} + +static u8 +rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) +{ + u8 ret; + + rcar_i2c_raw_rw_common(dev, chip, addr); + + /* set slave address, receive */ + writel((chip << 1) | 1, &dev->icmar); + /* start master receive */ + writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); + /* clear status */ + writel(0, &dev->icmsr); + + while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR)) + != (MSR_MAT | MSR_MDR)) + udelay(10); + + /* clear ESG */ + writel(MCR_MDBS | MCR_MIE, &dev->icmcr); + /* prepare stop condition */ + writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); + /* start SCLclk */ + writel(~(MSR_MAT | MSR_MDR), &dev->icmsr); + + while (!(readl(&dev->icmsr) & MSR_MDR)) + udelay(10); + + /* get receive data */ + ret = (u8)readl(&dev->icrxdtxd); + /* start SCLclk */ + writel(~MSR_MDR, &dev->icmsr); + + rcar_i2c_raw_rw_finish(dev); + + return ret; +} + +/* + * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck]) + * iicck : I2C internal clock < 20 MHz + * ticf : I2C SCL falling time: 35 ns + * tr : I2C SCL rising time: 200 ns + * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5 + * F[n] : n rounded up to an integer + */ +static u32 rcar_clock_gen(int i2c_no, u32 bus_speed) +{ + u32 iicck, f, scl, scgd; + u32 intd = 5; + + int bit = 0, cdf_width = 3; + for (bit = 0; bit < (1 << cdf_width); bit++) { + iicck = CONFIG_HP_CLK_FREQ / (1 + bit); + if (iicck < 20000000) + break; + } + + if (bit > (1 << cdf_width)) { + puts("rcar-i2c: Can not get CDF\n"); + return 0; + } + + if (i2c_no == 0) + intd = 50; + + f = (35 + 200 + intd) * (iicck / 1000000000); + + for (scgd = 0; scgd < 0x40; scgd++) { + scl = iicck / (20 + (scgd * 8) + f); + if (scl <= bus_speed) + break; + } + + if (scgd > 0x40) { + puts("rcar-i2c: Can not get SDGB\n"); + return 0; + } + + debug("%s: scl: %d\n", __func__, scl); + debug("%s: bit %x\n", __func__, bit); + debug("%s: scgd %x\n", __func__, scgd); + debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit)); + + return scgd << (cdf_width) | bit; +} + +static void +rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ + struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; + u32 icccr = 0; + + /* No i2c support prior to relocation */ + if (!(gd->flags & GD_FLG_RELOC)) + return; + + /* + * reset slave mode. + * slave mode is not used on this driver + */ + writel(0, &dev->icsier); + writel(0, &dev->icsar); + writel(0, &dev->icscr); + writel(0, &dev->icssr); + + /* reset master mode */ + writel(0, &dev->icmier); + writel(0, &dev->icmcr); + writel(0, &dev->icmsr); + writel(0, &dev->icmar); + + icccr = rcar_clock_gen(adap->hwadapnr, adap->speed); + if (icccr == 0) + puts("I2C: Init failed\n"); + else + writel(icccr, &dev->icccr); +} + +static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, u8 *data, int len) +{ + struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; + int i; + + for (i = 0; i < len; i++) + data[i] = rcar_i2c_raw_read(dev, chip, addr + i); + + return 0; +} + +static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, + int alen, u8 *data, int len) +{ + struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; + return rcar_i2c_raw_write(dev, chip, addr, data, len); +} + +static int +rcar_i2c_probe(struct i2c_adapter *adap, u8 dev) +{ + return rcar_i2c_read(adap, dev, 0, 0, NULL, 0); +} + +static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; + u32 icccr; + int ret = 0; + + rcar_i2c_raw_rw_finish(dev); + + icccr = rcar_clock_gen(adap->hwadapnr, speed); + if (icccr == 0) { + puts("I2C: Init failed\n"); + ret = -1; + } else { + writel(icccr, &dev->icccr); + } + return ret; +} + +/* + * Register RCAR i2c adapters + */ +U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, + rcar_i2c_write, rcar_i2c_set_bus_speed, + CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0) +U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, + rcar_i2c_write, rcar_i2c_set_bus_speed, + CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1) +U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, + rcar_i2c_write, rcar_i2c_set_bus_speed, + CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2) +U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, + rcar_i2c_write, rcar_i2c_set_bus_speed, + CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3) diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index cd09c788be..0dd1abcf80 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -9,8 +9,9 @@ * as they seem to have the same I2C controller inside. * The different address mapping is handled by the s3c24xx.h files below. */ - #include +#include +#include #include #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) #include @@ -23,8 +24,6 @@ #include #include "s3c24x0_i2c.h" -#ifdef CONFIG_HARD_I2C - #define I2C_WRITE 0 #define I2C_READ 1 @@ -34,6 +33,76 @@ #define I2C_NOK_LA 3 /* Lost arbitration */ #define I2C_NOK_TOUT 4 /* time out */ +/* HSI2C specific register description */ + +/* I2C_CTL Register bits */ +#define HSI2C_FUNC_MODE_I2C (1u << 0) +#define HSI2C_MASTER (1u << 3) +#define HSI2C_RXCHON (1u << 6) /* Write/Send */ +#define HSI2C_TXCHON (1u << 7) /* Read/Receive */ +#define HSI2C_SW_RST (1u << 31) + +/* I2C_FIFO_CTL Register bits */ +#define HSI2C_RXFIFO_EN (1u << 0) +#define HSI2C_TXFIFO_EN (1u << 1) +#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) +#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) + +/* I2C_TRAILING_CTL Register bits */ +#define HSI2C_TRAILING_COUNT (0xff) + +/* I2C_INT_EN Register bits */ +#define HSI2C_TX_UNDERRUN_EN (1u << 2) +#define HSI2C_TX_OVERRUN_EN (1u << 3) +#define HSI2C_RX_UNDERRUN_EN (1u << 4) +#define HSI2C_RX_OVERRUN_EN (1u << 5) +#define HSI2C_INT_TRAILING_EN (1u << 6) +#define HSI2C_INT_I2C_EN (1u << 9) + +#define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ + HSI2C_TX_OVERRUN_EN |\ + HSI2C_RX_UNDERRUN_EN |\ + HSI2C_RX_OVERRUN_EN |\ + HSI2C_INT_TRAILING_EN) + +/* I2C_CONF Register bits */ +#define HSI2C_AUTO_MODE (1u << 31) +#define HSI2C_10BIT_ADDR_MODE (1u << 30) +#define HSI2C_HS_MODE (1u << 29) + +/* I2C_AUTO_CONF Register bits */ +#define HSI2C_READ_WRITE (1u << 16) +#define HSI2C_STOP_AFTER_TRANS (1u << 17) +#define HSI2C_MASTER_RUN (1u << 31) + +/* I2C_TIMEOUT Register bits */ +#define HSI2C_TIMEOUT_EN (1u << 31) + +/* I2C_TRANS_STATUS register bits */ +#define HSI2C_MASTER_BUSY (1u << 17) +#define HSI2C_SLAVE_BUSY (1u << 16) +#define HSI2C_TIMEOUT_AUTO (1u << 4) +#define HSI2C_NO_DEV (1u << 3) +#define HSI2C_NO_DEV_ACK (1u << 2) +#define HSI2C_TRANS_ABORT (1u << 1) +#define HSI2C_TRANS_SUCCESS (1u << 0) +#define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ + HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ + HSI2C_TRANS_ABORT) +#define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) + + +/* I2C_FIFO_STAT Register bits */ +#define HSI2C_RX_FIFO_EMPTY (1u << 24) +#define HSI2C_RX_FIFO_FULL (1u << 23) +#define HSI2C_TX_FIFO_EMPTY (1u << 8) +#define HSI2C_TX_FIFO_FULL (1u << 7) +#define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) +#define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) + +#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) + +/* S3C I2C Controller bits */ #define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ @@ -43,20 +112,54 @@ #define I2C_START_STOP 0x20 /* START / STOP */ #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ -#define I2C_TIMEOUT 1 /* 1 second */ +#define I2C_TIMEOUT_MS 1000 /* 1 second */ + +#define HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */ +/* To support VCMA9 boards and other who dont define max_i2c_num */ +#ifndef CONFIG_MAX_I2C_NUM +#define CONFIG_MAX_I2C_NUM 1 +#endif + +DECLARE_GLOBAL_DATA_PTR; + /* * For SPL boot some boards need i2c before SDRAM is initialised so force * variables to live in SRAM */ -static unsigned int g_current_bus __attribute__((section(".data"))); -#ifdef CONFIG_OF_CONTROL -static int i2c_busses __attribute__((section(".data"))); +#ifdef CONFIG_SYS_I2C static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM] __attribute__((section(".data"))); #endif +enum exynos_i2c_type { + EXYNOS_I2C_STD, + EXYNOS_I2C_HS, +}; + +#ifdef CONFIG_SYS_I2C +/** + * Get a pointer to the given bus index + * + * @bus_idx: Bus index to look up + * @return pointer to bus, or NULL if invalid or not available + */ +static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx) +{ + if (bus_idx < ARRAY_SIZE(i2c_bus)) { + struct s3c24x0_i2c_bus *bus; + + bus = &i2c_bus[bus_idx]; + if (bus->active) + return bus; + } + + debug("Undefined bus: %d\n", bus_idx); + return NULL; +} +#endif + #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) static int GetI2CSDA(void) { @@ -84,22 +187,75 @@ static void SetI2CSCL(int x) } #endif +/* + * Wait til the byte transfer is completed. + * + * @param i2c- pointer to the appropriate i2c register bank. + * @return I2C_OK, if transmission was ACKED + * I2C_NACK, if transmission was NACKED + * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS + */ + static int WaitForXfer(struct s3c24x0_i2c *i2c) { - int i; + ulong start_time = get_timer(0); - i = I2C_TIMEOUT * 10000; - while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { - udelay(100); - i--; - } + do { + if (readl(&i2c->iiccon) & I2CCON_IRPND) + return (readl(&i2c->iicstat) & I2CSTAT_NACK) ? + I2C_NACK : I2C_OK; + } while (get_timer(start_time) < I2C_TIMEOUT_MS); - return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; + return I2C_NOK_TOUT; } -static int IsACK(struct s3c24x0_i2c *i2c) +/* + * Wait for transfer completion. + * + * This function reads the interrupt status register waiting for the INT_I2C + * bit to be set, which indicates copletion of a transaction. + * + * @param i2c: pointer to the appropriate register bank + * + * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case + * the status bits do not get set in time, or an approrpiate error + * value in case of transfer errors. + */ +static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) { - return !(readl(&i2c->iicstat) & I2CSTAT_NACK); + int i = HSI2C_TIMEOUT_US; + + while (i-- > 0) { + u32 int_status = readl(&i2c->usi_int_stat); + + if (int_status & HSI2C_INT_I2C_EN) { + u32 trans_status = readl(&i2c->usi_trans_status); + + /* Deassert pending interrupt. */ + writel(int_status, &i2c->usi_int_stat); + + if (trans_status & HSI2C_NO_DEV_ACK) { + debug("%s: no ACK from device\n", __func__); + return I2C_NACK; + } + if (trans_status & HSI2C_NO_DEV) { + debug("%s: no device\n", __func__); + return I2C_NOK; + } + if (trans_status & HSI2C_TRANS_ABORT) { + debug("%s: arbitration lost\n", __func__); + return I2C_NOK_LA; + } + if (trans_status & HSI2C_TIMEOUT_AUTO) { + debug("%s: device timed out\n", __func__); + return I2C_NOK_TOUT; + } + return I2C_OK; + } + udelay(1); + } + debug("%s: transaction timeout!\n", __func__); + return I2C_NOK_TOUT; } static void ReadWriteByte(struct s3c24x0_i2c *i2c) @@ -107,22 +263,24 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c) writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } -static struct s3c24x0_i2c *get_base_i2c(void) +#ifdef CONFIG_SYS_I2C +static struct s3c24x0_i2c *get_base_i2c(int bus) { #ifdef CONFIG_EXYNOS4 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() + (EXYNOS4_I2C_SPACING - * g_current_bus)); + * bus)); return i2c; #elif defined CONFIG_EXYNOS5 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() + (EXYNOS5_I2C_SPACING - * g_current_bus)); + * bus)); return i2c; #else return s3c24x0_get_base_i2c(); #endif } +#endif static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) { @@ -151,53 +309,139 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } -/* - * MULTI BUS I2C support - */ - -#ifdef CONFIG_I2C_MULTI_BUS -int i2c_set_bus_num(unsigned int bus) +static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) { - struct s3c24x0_i2c *i2c; + struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; + ulong clkin; + unsigned int op_clk = i2c_bus->clock_frequency; + unsigned int i = 0, utemp0 = 0, utemp1 = 0; + unsigned int t_ftl_cycle; - if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) { - debug("Bad bus: %d\n", bus); - return -1; +#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) + clkin = get_i2c_clk(); +#else + clkin = get_PCLK(); +#endif + /* FPCLK / FI2C = + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE + * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + * uTemp1 = (TSCLK_L + TSCLK_H + 2) + * uTemp2 = TSCLK_L + TSCLK_H + */ + t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; + utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; + + /* CLK_DIV max is 256 */ + for (i = 0; i < 256; i++) { + utemp1 = utemp0 / (i + 1); + if ((utemp1 < 512) && (utemp1 > 4)) { + i2c_bus->clk_cycle = utemp1 - 2; + i2c_bus->clk_div = i; + return 0; + } } + return -EINVAL; +} - g_current_bus = bus; - i2c = get_base_i2c(); - i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - return 0; +static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) +{ + struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; + unsigned int t_sr_release; + unsigned int n_clkdiv; + unsigned int t_start_su, t_start_hd; + unsigned int t_stop_su; + unsigned int t_data_su, t_data_hd; + unsigned int t_scl_l, t_scl_h; + u32 i2c_timing_s1; + u32 i2c_timing_s2; + u32 i2c_timing_s3; + u32 i2c_timing_sla; + + n_clkdiv = i2c_bus->clk_div; + t_scl_l = i2c_bus->clk_cycle / 2; + t_scl_h = i2c_bus->clk_cycle / 2; + t_start_su = t_scl_l; + t_start_hd = t_scl_l; + t_stop_su = t_scl_l; + t_data_su = t_scl_l / 2; + t_data_hd = t_scl_l / 2; + t_sr_release = i2c_bus->clk_cycle; + + i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; + i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; + i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; + i2c_timing_sla = t_data_hd << 0; + + writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); + + /* Clear to enable Timeout */ + clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); + + /* set AUTO mode */ + writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); + + /* Enable completion conditions' reporting. */ + writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); + + /* Enable FIFOs */ + writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); + + /* Currently operating in Fast speed mode. */ + writel(i2c_timing_s1, &hsregs->usi_timing_fs1); + writel(i2c_timing_s2, &hsregs->usi_timing_fs2); + writel(i2c_timing_s3, &hsregs->usi_timing_fs3); + writel(i2c_timing_sla, &hsregs->usi_timing_sla); } -unsigned int i2c_get_bus_num(void) +/* SW reset for the high speed bus */ +static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) { - return g_current_bus; + struct exynos5_hsi2c *i2c = i2c_bus->hsregs; + u32 i2c_ctl; + + /* Set and clear the bit for reset */ + i2c_ctl = readl(&i2c->usi_ctl); + i2c_ctl |= HSI2C_SW_RST; + writel(i2c_ctl, &i2c->usi_ctl); + + i2c_ctl = readl(&i2c->usi_ctl); + i2c_ctl &= ~HSI2C_SW_RST; + writel(i2c_ctl, &i2c->usi_ctl); + + /* Initialize the configure registers */ + hsi2c_ch_init(i2c_bus); } -#endif -void i2c_init(int speed, int slaveadd) +#ifdef CONFIG_SYS_I2C +static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { struct s3c24x0_i2c *i2c; + struct s3c24x0_i2c_bus *bus; #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #endif - int i; + ulong start_time = get_timer(0); - /* By default i2c channel 0 is the current bus */ - g_current_bus = 0; - i2c = get_base_i2c(); + i2c = get_base_i2c(adap->hwadapnr); + bus = &i2c_bus[adap->hwadapnr]; + if (!bus) + return; - /* wait for some time to give previous transfer a chance to finish */ - i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { - udelay(1000); - i--; + /* + * In case the previous transfer is still going, wait to give it a + * chance to finish. + */ + while (readl(&i2c->iicstat) & I2CSTAT_BSY) { + if (get_timer(start_time) > I2C_TIMEOUT_MS) { + printf("%s: I2C bus busy for %p\n", __func__, + &i2c->iicstat); + return; + } } #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) + int i; + if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { #ifdef CONFIG_S3C2410 ulong old_gpecon = readl(&gpio->gpecon); @@ -242,7 +486,263 @@ void i2c_init(int speed, int slaveadd) #endif } #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */ + i2c_ch_init(i2c, speed, slaveadd); + + bus->active = true; + bus->regs = i2c; +} +#endif /* CONFIG_SYS_I2C */ + +/* + * Poll the appropriate bit of the fifo status register until the interface is + * ready to process the next byte or timeout expires. + * + * In addition to the FIFO status register this function also polls the + * interrupt status register to be able to detect unexpected transaction + * completion. + * + * When FIFO is ready to process the next byte, this function returns I2C_OK. + * If in course of polling the INT_I2C assertion is detected, the function + * returns I2C_NOK. If timeout happens before any of the above conditions is + * met - the function returns I2C_NOK_TOUT; + + * @param i2c: pointer to the appropriate i2c register bank. + * @param rx_transfer: set to True if the receive transaction is in progress. + * @return: as described above. + */ +static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) +{ + u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; + int i = HSI2C_TIMEOUT_US; + + while (readl(&i2c->usi_fifo_stat) & fifo_bit) { + if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { + /* + * There is a chance that assertion of + * HSI2C_INT_I2C_EN and deassertion of + * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's + * give FIFO status priority and check it one more + * time before reporting interrupt. The interrupt will + * be reported next time this function is called. + */ + if (rx_transfer && + !(readl(&i2c->usi_fifo_stat) & fifo_bit)) + break; + return I2C_NOK; + } + if (!i--) { + debug("%s: FIFO polling timeout!\n", __func__); + return I2C_NOK_TOUT; + } + udelay(1); + } + return I2C_OK; +} + +/* + * Preapre hsi2c transaction, either read or write. + * + * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of + * the 5420 UM. + * + * @param i2c: pointer to the appropriate i2c register bank. + * @param chip: slave address on the i2c bus (with read/write bit exlcuded) + * @param len: number of bytes expected to be sent or received + * @param rx_transfer: set to true for receive transactions + * @param: issue_stop: set to true if i2c stop condition should be generated + * after this transaction. + * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, + * I2C_OK otherwise. + */ +static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, + u8 chip, + u16 len, + bool rx_transfer, + bool issue_stop) +{ + u32 conf; + + conf = len | HSI2C_MASTER_RUN; + + if (issue_stop) + conf |= HSI2C_STOP_AFTER_TRANS; + + /* Clear to enable Timeout */ + writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); + + /* Set slave address */ + writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); + + if (rx_transfer) { + /* i2c master, read transaction */ + writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); + + /* read up to len bytes, stop after transaction is finished */ + writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); + } else { + /* i2c master, write transaction */ + writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); + + /* write up to len bytes, stop after transaction is finished */ + writel(conf, &i2c->usi_auto_conf); + } + + /* Reset all pending interrupt status bits we care about, if any */ + writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); + + return I2C_OK; +} + +/* + * Wait while i2c bus is settling down (mostly stop gets completed). + */ +static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) +{ + int i = HSI2C_TIMEOUT_US; + + while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { + if (!i--) { + debug("%s: bus busy\n", __func__); + return I2C_NOK_TOUT; + } + udelay(1); + } + return I2C_OK; +} + +static int hsi2c_write(struct exynos5_hsi2c *i2c, + unsigned char chip, + unsigned char addr[], + unsigned char alen, + unsigned char data[], + unsigned short len, + bool issue_stop) +{ + int i, rv = 0; + + if (!(len + alen)) { + /* Writes of zero length not supported in auto mode. */ + debug("%s: zero length writes not supported\n", __func__); + return I2C_NOK; + } + + rv = hsi2c_prepare_transaction + (i2c, chip, len + alen, false, issue_stop); + if (rv != I2C_OK) + return rv; + + /* Move address, if any, and the data, if any, into the FIFO. */ + for (i = 0; i < alen; i++) { + rv = hsi2c_poll_fifo(i2c, false); + if (rv != I2C_OK) { + debug("%s: address write failed\n", __func__); + goto write_error; + } + writel(addr[i], &i2c->usi_txdata); + } + + for (i = 0; i < len; i++) { + rv = hsi2c_poll_fifo(i2c, false); + if (rv != I2C_OK) { + debug("%s: data write failed\n", __func__); + goto write_error; + } + writel(data[i], &i2c->usi_txdata); + } + + rv = hsi2c_wait_for_trx(i2c); + + write_error: + if (issue_stop) { + int tmp_ret = hsi2c_wait_while_busy(i2c); + if (rv == I2C_OK) + rv = tmp_ret; + } + + writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ + return rv; +} + +static int hsi2c_read(struct exynos5_hsi2c *i2c, + unsigned char chip, + unsigned char addr[], + unsigned char alen, + unsigned char data[], + unsigned short len) +{ + int i, rv, tmp_ret; + bool drop_data = false; + + if (!len) { + /* Reads of zero length not supported in auto mode. */ + debug("%s: zero length read adjusted\n", __func__); + drop_data = true; + len = 1; + } + + if (alen) { + /* Internal register adress needs to be written first. */ + rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); + if (rv != I2C_OK) + return rv; + } + + rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); + + if (rv != I2C_OK) + return rv; + + for (i = 0; i < len; i++) { + rv = hsi2c_poll_fifo(i2c, true); + if (rv != I2C_OK) + goto read_err; + if (drop_data) + continue; + data[i] = readl(&i2c->usi_rxdata); + } + + rv = hsi2c_wait_for_trx(i2c); + + read_err: + tmp_ret = hsi2c_wait_while_busy(i2c); + if (rv == I2C_OK) + rv = tmp_ret; + + writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ + return rv; +} + +#ifdef CONFIG_SYS_I2C +static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +#else +static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) +#endif +{ + struct s3c24x0_i2c_bus *i2c_bus; + +#ifdef CONFIG_SYS_I2C + i2c_bus = get_bus(adap->hwadapnr); + if (!i2c_bus) + return -EFAULT; +#else + i2c_bus = dev_get_priv(dev); +#endif + i2c_bus->clock_frequency = speed; + + if (i2c_bus->is_highspeed) { + if (hsi2c_get_clk_details(i2c_bus)) + return -EFAULT; + hsi2c_ch_init(i2c_bus); + } else { + i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency, + CONFIG_SYS_I2C_S3C24X0_SLAVE); + } + + return 0; } /* @@ -260,7 +760,8 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, unsigned char data[], unsigned short data_len) { - int i, result; + int i = 0, result; + ulong start_time = get_timer(0); if (data == 0 || data_len == 0) { /*Don't support data transfer of no length or to address 0 */ @@ -268,128 +769,78 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, return I2C_NOK; } - /* Check I2C bus idle */ - i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { - udelay(1000); - i--; + while (readl(&i2c->iicstat) & I2CSTAT_BSY) { + if (get_timer(start_time) > I2C_TIMEOUT_MS) + return I2C_NOK_TOUT; } - if (readl(&i2c->iicstat) & I2CSTAT_BSY) - return I2C_NOK_TOUT; - writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); - result = I2C_OK; - switch (cmd_type) { - case I2C_WRITE: - if (addr && addr_len) { - writel(chip, &i2c->iicds); - /* send START */ - writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); - i = 0; - while ((i < addr_len) && (result == I2C_OK)) { - result = WaitForXfer(i2c); - writel(addr[i], &i2c->iicds); - ReadWriteByte(i2c); - i++; - } - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - result = WaitForXfer(i2c); - writel(data[i], &i2c->iicds); - ReadWriteByte(i2c); - i++; - } - } else { - writel(chip, &i2c->iicds); - /* send START */ - writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - result = WaitForXfer(i2c); - writel(data[i], &i2c->iicds); - ReadWriteByte(i2c); - i++; - } + /* Get the slave chip address going */ + writel(chip, &i2c->iicds); + if ((cmd_type == I2C_WRITE) || (addr && addr_len)) + writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); + else + writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); + + /* Wait for chip address to transmit. */ + result = WaitForXfer(i2c); + if (result != I2C_OK) + goto bailout; + + /* If register address needs to be transmitted - do it now. */ + if (addr && addr_len) { + while ((i < addr_len) && (result == I2C_OK)) { + writel(addr[i++], &i2c->iicds); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); } + i = 0; + if (result != I2C_OK) + goto bailout; + } - if (result == I2C_OK) + switch (cmd_type) { + case I2C_WRITE: + while ((i < data_len) && (result == I2C_OK)) { + writel(data[i++], &i2c->iicds); + ReadWriteByte(i2c); result = WaitForXfer(i2c); - - /* send STOP */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); - ReadWriteByte(i2c); + } break; case I2C_READ: if (addr && addr_len) { + /* + * Register address has been sent, now send slave chip + * address again to start the actual read transaction. + */ writel(chip, &i2c->iicds); - /* send START */ - writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); - result = WaitForXfer(i2c); - if (IsACK(i2c)) { - i = 0; - while ((i < addr_len) && (result == I2C_OK)) { - writel(addr[i], &i2c->iicds); - ReadWriteByte(i2c); - result = WaitForXfer(i2c); - i++; - } - - writel(chip, &i2c->iicds); - /* resend START */ - writel(I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP, &i2c->iicstat); - ReadWriteByte(i2c); - result = WaitForXfer(i2c); - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - /* disable ACK for final READ */ - if (i == data_len - 1) - writel(readl(&i2c->iiccon) - & ~I2CCON_ACKGEN, - &i2c->iiccon); - ReadWriteByte(i2c); - result = WaitForXfer(i2c); - data[i] = readl(&i2c->iicds); - i++; - } - } else { - result = I2C_NACK; - } - } else { - writel(chip, &i2c->iicds); - /* send START */ + /* Generate a re-START. */ writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, &i2c->iicstat); + ReadWriteByte(i2c); result = WaitForXfer(i2c); - if (IsACK(i2c)) { - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - /* disable ACK for final READ */ - if (i == data_len - 1) - writel(readl(&i2c->iiccon) & - ~I2CCON_ACKGEN, - &i2c->iiccon); - ReadWriteByte(i2c); - result = WaitForXfer(i2c); - data[i] = readl(&i2c->iicds); - i++; - } - } else { - result = I2C_NACK; - } + if (result != I2C_OK) + goto bailout; } - /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); - ReadWriteByte(i2c); + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) + writel(readl(&i2c->iiccon) + & ~I2CCON_ACKGEN, + &i2c->iiccon); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); + data[i++] = readl(&i2c->iicds); + } + if (result == I2C_NACK) + result = I2C_OK; /* Normal terminated read. */ break; default: @@ -398,15 +849,31 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, break; } +bailout: + /* Send STOP. */ + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); + ReadWriteByte(i2c); + return result; } -int i2c_probe(uchar chip) +#ifdef CONFIG_SYS_I2C +static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip) +#else +static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) +#endif { - struct s3c24x0_i2c *i2c; + struct s3c24x0_i2c_bus *i2c_bus; uchar buf[1]; + int ret; - i2c = get_base_i2c(); +#ifdef CONFIG_SYS_I2C + i2c_bus = get_bus(adap->hwadapnr); + if (!i2c_bus) + return -EFAULT; +#else + i2c_bus = dev_get_priv(dev); +#endif buf[0] = 0; /* @@ -414,18 +881,32 @@ int i2c_probe(uchar chip) * address was ed (i.e. there was a chip at that address which * drove the data line low). */ - return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; + if (i2c_bus->is_highspeed) { + ret = hsi2c_read(i2c_bus->hsregs, + chip, 0, 0, buf, 1); + } else { + ret = i2c_transfer(i2c_bus->regs, + I2C_READ, chip << 1, 0, 0, buf, 1); + } + + return ret != I2C_OK; } -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +#ifdef CONFIG_SYS_I2C +static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) { - struct s3c24x0_i2c *i2c; + struct s3c24x0_i2c_bus *i2c_bus; uchar xaddr[4]; int ret; + i2c_bus = get_bus(adap->hwadapnr); + if (!i2c_bus) + return -EFAULT; + if (alen > 4) { debug("I2C read: addr len %d not supported\n", alen); - return 1; + return -EADDRNOTAVAIL; } if (alen > 0) { @@ -451,24 +932,36 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif - i2c = get_base_i2c(); - ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen, - buffer, len); - if (ret != 0) { - debug("I2c read: failed %d\n", ret); - return 1; + if (i2c_bus->is_highspeed) + ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen], + alen, buffer, len); + else + ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, + &xaddr[4 - alen], alen, buffer, len); + + if (ret) { + if (i2c_bus->is_highspeed) + exynos5_i2c_reset(i2c_bus); + debug("I2c read failed %d\n", ret); + return -EIO; } return 0; } -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) { - struct s3c24x0_i2c *i2c; + struct s3c24x0_i2c_bus *i2c_bus; uchar xaddr[4]; + int ret; + + i2c_bus = get_bus(adap->hwadapnr); + if (!i2c_bus) + return -EFAULT; if (alen > 4) { debug("I2C write: addr len %d not supported\n", alen); - return 1; + return -EINVAL; } if (alen > 0) { @@ -493,82 +986,415 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif - i2c = get_base_i2c(); - return (i2c_transfer - (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, - len) != 0); + if (i2c_bus->is_highspeed) + ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen], + alen, buffer, len, true); + else + ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1, + &xaddr[4 - alen], alen, buffer, len); + + if (ret != 0) { + if (i2c_bus->is_highspeed) + exynos5_i2c_reset(i2c_bus); + return 1; + } else { + return 0; + } } #ifdef CONFIG_OF_CONTROL -void board_i2c_init(const void *blob) +static void process_nodes(const void *blob, int node_list[], int count, + int is_highspeed) { - int i; - int node_list[CONFIG_MAX_I2C_NUM]; - int count; - - count = fdtdec_find_aliases_for_id(blob, "i2c", - COMPAT_SAMSUNG_S3C2440_I2C, node_list, - CONFIG_MAX_I2C_NUM); + struct s3c24x0_i2c_bus *bus; + int i, flags; for (i = 0; i < count; i++) { - struct s3c24x0_i2c_bus *bus; int node = node_list[i]; if (node <= 0) continue; + bus = &i2c_bus[i]; - bus->regs = (struct s3c24x0_i2c *) - fdtdec_get_addr(blob, node, "reg"); + bus->active = true; + bus->is_highspeed = is_highspeed; + + if (is_highspeed) { + flags = PINMUX_FLAG_HS_MODE; + bus->hsregs = (struct exynos5_hsi2c *) + fdtdec_get_addr(blob, node, "reg"); + } else { + flags = 0; + bus->regs = (struct s3c24x0_i2c *) + fdtdec_get_addr(blob, node, "reg"); + } + bus->id = pinmux_decode_periph_id(blob, node); + bus->clock_frequency = fdtdec_get_int(blob, node, + "clock-frequency", + CONFIG_SYS_I2C_S3C24X0_SPEED); bus->node = node; - bus->bus_num = i2c_busses++; - exynos_pinmux_config(bus->id, 0); + bus->bus_num = i; + exynos_pinmux_config(PERIPH_ID_I2C0 + bus->id, flags); + + /* Mark position as used */ + node_list[i] = -1; } } -static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx) +void board_i2c_init(const void *blob) { - if (bus_idx < i2c_busses) - return &i2c_bus[bus_idx]; + int node_list[CONFIG_MAX_I2C_NUM]; + int count; - debug("Undefined bus: %d\n", bus_idx); - return NULL; + /* First get the normal i2c ports */ + count = fdtdec_find_aliases_for_id(blob, "i2c", + COMPAT_SAMSUNG_S3C2440_I2C, node_list, + CONFIG_MAX_I2C_NUM); + process_nodes(blob, node_list, count, 0); + + /* Now look for high speed i2c ports */ + count = fdtdec_find_aliases_for_id(blob, "i2c", + COMPAT_SAMSUNG_EXYNOS5_I2C, node_list, + CONFIG_MAX_I2C_NUM); + process_nodes(blob, node_list, count, 1); } int i2c_get_bus_num_fdt(int node) { int i; - for (i = 0; i < i2c_busses; i++) { + for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) { if (node == i2c_bus[i].node) return i; } debug("%s: Can't find any matched I2C bus\n", __func__); - return -1; + return -EINVAL; } int i2c_reset_port_fdt(const void *blob, int node) { - struct s3c24x0_i2c_bus *i2c; + struct s3c24x0_i2c_bus *i2c_bus; int bus; bus = i2c_get_bus_num_fdt(node); if (bus < 0) { debug("could not get bus for node %d\n", node); - return -1; + return bus; } - i2c = get_bus(bus); - if (!i2c) { - debug("get_bus() failed for node node %d\n", node); - return -1; + i2c_bus = get_bus(bus); + if (!i2c_bus) { + debug("get_bus() failed for node %d\n", node); + return -EFAULT; } - i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (i2c_bus->is_highspeed) { + if (hsi2c_get_clk_details(i2c_bus)) + return -EINVAL; + hsi2c_ch_init(i2c_bus); + } else { + i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency, + CONFIG_SYS_I2C_S3C24X0_SLAVE); + } return 0; } +#endif /* CONFIG_OF_CONTROL */ + +#ifdef CONFIG_EXYNOS5 +static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +{ + /* This will override the speed selected in the fdt for that port */ + debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); + if (i2c_set_bus_speed(speed)) + error("i2c_init: failed to init bus for speed = %d", speed); +} +#endif /* CONFIG_EXYNOS5 */ + +/* + * Register s3c24x0 i2c adapters + */ +#if defined(CONFIG_EXYNOS5420) +U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 0) +U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 1) +U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 2) +U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 3) +U_BOOT_I2C_ADAP_COMPLETE(i2c04, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 4) +U_BOOT_I2C_ADAP_COMPLETE(i2c05, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 5) +U_BOOT_I2C_ADAP_COMPLETE(i2c06, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 6) +U_BOOT_I2C_ADAP_COMPLETE(i2c07, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 7) +U_BOOT_I2C_ADAP_COMPLETE(i2c08, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 8) +U_BOOT_I2C_ADAP_COMPLETE(i2c09, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 9) +U_BOOT_I2C_ADAP_COMPLETE(i2c10, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 10) +#elif defined(CONFIG_EXYNOS5250) +U_BOOT_I2C_ADAP_COMPLETE(i2c00, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 0) +U_BOOT_I2C_ADAP_COMPLETE(i2c01, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 1) +U_BOOT_I2C_ADAP_COMPLETE(i2c02, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 2) +U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 3) +U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 4) +U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 5) +U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 6) +U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 7) +U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 8) +U_BOOT_I2C_ADAP_COMPLETE(i2c09, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 9) +U_BOOT_I2C_ADAP_COMPLETE(s3c10, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 10) +#elif defined(CONFIG_EXYNOS4) +U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 0) +U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 1) +U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 2) +U_BOOT_I2C_ADAP_COMPLETE(i2c03, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 3) +U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 4) +U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 5) +U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 6) +U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 7) +U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 8) +#else +U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe, + s3c24x0_i2c_read, s3c24x0_i2c_write, + s3c24x0_i2c_set_bus_speed, + CONFIG_SYS_I2C_S3C24X0_SPEED, + CONFIG_SYS_I2C_S3C24X0_SLAVE, 0) #endif +#endif /* CONFIG_SYS_I2C */ + +#ifdef CONFIG_DM_I2C +static int i2c_write_data(struct s3c24x0_i2c_bus *i2c_bus, uchar chip, + uchar *buffer, int len, bool end_with_repeated_start) +{ + int ret; + + if (i2c_bus->is_highspeed) { + ret = hsi2c_write(i2c_bus->hsregs, chip, 0, 0, + buffer, len, true); + if (ret) + exynos5_i2c_reset(i2c_bus); + } else { + ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, + chip << 1, 0, 0, buffer, len); + } + + return ret != I2C_OK; +} + +static int i2c_read_data(struct s3c24x0_i2c_bus *i2c_bus, uchar chip, + uchar *buffer, int len) +{ + int ret; + + if (i2c_bus->is_highspeed) { + ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buffer, len); + if (ret) + exynos5_i2c_reset(i2c_bus); + } else { + ret = i2c_transfer(i2c_bus->regs, I2C_READ, + chip << 1, 0, 0, buffer, len); + } + + return ret != I2C_OK; +} + +static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); + int ret; + + for (; nmsgs > 0; nmsgs--, msg++) { + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); + + if (msg->flags & I2C_M_RD) { + ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, + msg->len); + } else { + ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, + msg->len, next_is_read); + } + if (ret) + return -EREMOTEIO; + } + + return 0; +} + +static int s3c_i2c_ofdata_to_platdata(struct udevice *dev) +{ + const void *blob = gd->fdt_blob; + struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); + int node, flags; + + i2c_bus->is_highspeed = dev->of_id->data; + node = dev->of_offset; + + if (i2c_bus->is_highspeed) { + flags = PINMUX_FLAG_HS_MODE; + i2c_bus->hsregs = (struct exynos5_hsi2c *) + fdtdec_get_addr(blob, node, "reg"); + } else { + flags = 0; + i2c_bus->regs = (struct s3c24x0_i2c *) + fdtdec_get_addr(blob, node, "reg"); + } + + i2c_bus->id = pinmux_decode_periph_id(blob, node); + + i2c_bus->clock_frequency = fdtdec_get_int(blob, node, + "clock-frequency", + CONFIG_SYS_I2C_S3C24X0_SPEED); + i2c_bus->node = node; + i2c_bus->bus_num = dev->seq; + + exynos_pinmux_config(i2c_bus->id, flags); + + i2c_bus->active = true; + + return 0; +} -#endif /* CONFIG_HARD_I2C */ +static const struct dm_i2c_ops s3c_i2c_ops = { + .xfer = s3c24x0_i2c_xfer, + .probe_chip = s3c24x0_i2c_probe, + .set_bus_speed = s3c24x0_i2c_set_bus_speed, +}; + +static const struct udevice_id s3c_i2c_ids[] = { + { .compatible = "samsung,s3c2440-i2c", .data = EXYNOS_I2C_STD }, + { .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS }, + { } +}; + +U_BOOT_DRIVER(i2c_s3c) = { + .name = "i2c_s3c", + .id = UCLASS_I2C, + .of_match = s3c_i2c_ids, + .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), + .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), + .ops = &s3c_i2c_ops, +}; +#endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index b4a337a57b..1ae73d2777 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -15,10 +15,48 @@ struct s3c24x0_i2c { u32 iiclc; }; +struct exynos5_hsi2c { + u32 usi_ctl; + u32 usi_fifo_ctl; + u32 usi_trailing_ctl; + u32 usi_clk_ctl; + u32 usi_clk_slot; + u32 spi_ctl; + u32 uart_ctl; + u32 res1; + u32 usi_int_en; + u32 usi_int_stat; + u32 usi_modem_stat; + u32 usi_error_stat; + u32 usi_fifo_stat; + u32 usi_txdata; + u32 usi_rxdata; + u32 res2; + u32 usi_conf; + u32 usi_auto_conf; + u32 usi_timeout; + u32 usi_manual_cmd; + u32 usi_trans_status; + u32 usi_timing_hs1; + u32 usi_timing_hs2; + u32 usi_timing_hs3; + u32 usi_timing_fs1; + u32 usi_timing_fs2; + u32 usi_timing_fs3; + u32 usi_timing_sla; + u32 i2c_addr; +}; + struct s3c24x0_i2c_bus { + bool active; /* port is active and available */ int node; /* device tree node */ int bus_num; /* i2c bus number */ struct s3c24x0_i2c *regs; + struct exynos5_hsi2c *hsregs; + int is_highspeed; /* High speed type, rather than I2C */ + unsigned clock_frequency; int id; + unsigned clk_cycle; + unsigned clk_div; }; #endif /* _S3C24X0_I2C_H */ diff --git a/drivers/i2c/s3c44b0_i2c.c b/drivers/i2c/s3c44b0_i2c.c deleted file mode 100644 index 8445e01caf..0000000000 --- a/drivers/i2c/s3c44b0_i2c.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr) -{ - /* - setting up I2C support - */ - unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; - - save_F = PCONF; - save_PF = PUPF; - - rPCONF = ((save_F & ~(0xF))| 0xa); - rPUPF = (save_PF | 0x3); - PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ - PUPF = rPUPF; /* Disable pull-up */ - - /* Configuring pin for WC pin of EEprom */ - rPCONA = PCONA; - rPCONA &= ~(1<<9); - PCONA = rPCONA; - - rPDATA = PDATA; - rPDATA &= ~(1<<9); - PDATA = rPDATA; - - /* - Enable ACK, IICCLK=MCLK/16, enable interrupt - 75MHz/16/(12+1) = 390625 Hz - */ - rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); - IICCON = rIICCON; - - IICADD = slaveaddr; -} - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(uchar chip) -{ - /* - not implemented - */ - - printf("i2c_probe chip %d\n", (int) chip); - return -1; -} - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -#define S3C44B0X_rIIC_INTPEND (1<<4) -#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) -#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) -#define S3C44B0_IIC_TIMEOUT 100 - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - - int k, j, temp; - u32 rIICSTAT; - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - for(k=0; k +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct dm_sandbox_i2c_emul_priv { + struct udevice *emul; +}; + +static int get_emul(struct udevice *dev, struct udevice **devp, + struct dm_i2c_ops **opsp) +{ + struct dm_i2c_chip *plat; + int ret; + + *devp = NULL; + *opsp = NULL; + plat = dev_get_parent_platdata(dev); + if (!plat->emul) { + ret = dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, + false); + if (ret) + return ret; + + ret = device_get_child(dev, 0, &plat->emul); + if (ret) + return ret; + } + *devp = plat->emul; + *opsp = i2c_get_ops(plat->emul); + + return 0; +} + +static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + struct dm_i2c_bus *i2c = bus->uclass_priv; + struct dm_i2c_ops *ops; + struct udevice *emul, *dev; + bool is_read; + int ret; + + /* Special test code to return success but with no emulation */ + if (msg->addr == SANDBOX_I2C_TEST_ADDR) + return 0; + + ret = i2c_get_chip(bus, msg->addr, 1, &dev); + if (ret) + return ret; + + ret = get_emul(dev, &emul, &ops); + if (ret) + return ret; + + /* + * For testing, don't allow writing above 100KHz for writes and + * 400KHz for reads + */ + is_read = nmsgs > 1; + if (i2c->speed_hz > (is_read ? 400000 : 100000)) + return -EINVAL; + return ops->xfer(emul, msg, nmsgs); +} + +static const struct dm_i2c_ops sandbox_i2c_ops = { + .xfer = sandbox_i2c_xfer, +}; + +static const struct udevice_id sandbox_i2c_ids[] = { + { .compatible = "sandbox,i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_sandbox) = { + .name = "i2c_sandbox", + .id = UCLASS_I2C, + .of_match = sandbox_i2c_ids, + .ops = &sandbox_i2c_ops, +}; diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 58f8bf1bd5..e7e96921d2 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -1,13 +1,16 @@ /* - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Nobuhiro Iwamatsu + * Copyright (C) 2011, 2013 Renesas Solutions Corp. + * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu * * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include +DECLARE_GLOBAL_DATA_PTR; + /* Every register is 32bit aligned, but only 8bits in size */ #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; struct sh_i2c { @@ -20,8 +23,6 @@ struct sh_i2c { }; #undef ureg -static struct sh_i2c *base; - /* ICCR */ #define SH_I2C_ICCR_ICE (1 << 7) #define SH_I2C_ICCR_RACK (1 << 6) @@ -41,209 +42,171 @@ static struct sh_i2c *base; #define SH_I2C_ICIC_ICCHB8 (1 << 6) #endif +static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = { + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0, +#ifdef CONFIG_SYS_I2C_SH_BASE1 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE2 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE3 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE4 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4, +#endif +}; + static u16 iccl, icch; #define IRQ_WAIT 1000 -static void irq_dte(struct sh_i2c *base) +static void sh_irq_dte(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (SH_IC_DTE & readb(&base->icsr)) + for (i = 0; i < IRQ_WAIT; i++) { + if (SH_IC_DTE & readb(&dev->icsr)) break; udelay(10); } } -static int irq_dte_with_tack(struct sh_i2c *base) +static int sh_irq_dte_with_tack(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (SH_IC_DTE & readb(&base->icsr)) + for (i = 0; i < IRQ_WAIT; i++) { + if (SH_IC_DTE & readb(&dev->icsr)) break; - if (SH_IC_TACK & readb(&base->icsr)) + if (SH_IC_TACK & readb(&dev->icsr)) return -1; udelay(10); } return 0; } -static void irq_busy(struct sh_i2c *base) +static void sh_irq_busy(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (!(SH_IC_BUSY & readb(&base->icsr))) + for (i = 0; i < IRQ_WAIT; i++) { + if (!(SH_IC_BUSY & readb(&dev->icsr))) break; udelay(10); } } -static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) +static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop) { u8 icic = SH_IC_TACK; - clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); - setbits_8(&base->iccr, SH_I2C_ICCR_ICE); + debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n", + __func__, chip, addr, iccl, icch); + clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); + setbits_8(&dev->iccr, SH_I2C_ICCR_ICE); - writeb(iccl & 0xff, &base->iccl); - writeb(icch & 0xff, &base->icch); + writeb(iccl & 0xff, &dev->iccl); + writeb(icch & 0xff, &dev->icch); #ifdef CONFIG_SH_I2C_8BIT if (iccl > 0xff) icic |= SH_I2C_ICIC_ICCLB8; if (icch > 0xff) icic |= SH_I2C_ICIC_ICCHB8; #endif - writeb(icic, &base->icic); + writeb(icic, &dev->icic); - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); - irq_dte(base); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); + sh_irq_dte(dev); - clrbits_8(&base->icsr, SH_IC_TACK); - writeb(id << 1, &base->icdr); - if (irq_dte_with_tack(base) != 0) + clrbits_8(&dev->icsr, SH_IC_TACK); + writeb(chip << 1, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) return -1; - writeb(reg, &base->icdr); + writeb(addr, &dev->icdr); if (stop) - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr); - if (irq_dte_with_tack(base) != 0) + if (sh_irq_dte_with_tack(dev) != 0) return -1; return 0; } -static void i2c_finish(struct sh_i2c *base) +static void sh_i2c_finish(struct sh_i2c *dev) { - writeb(0, &base->icsr); - clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); + writeb(0, &dev->icsr); + clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); } -static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) +static int +sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val) { int ret = -1; - if (i2c_set_addr(base, id, reg, 0) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) goto exit0; udelay(10); - writeb(val, &base->icdr); - if (irq_dte_with_tack(base) != 0) + writeb(val, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); - if (irq_dte_with_tack(base) != 0) + writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - irq_busy(base); + sh_irq_busy(dev); ret = 0; + exit0: - i2c_finish(base); + sh_i2c_finish(dev); return ret; } -static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) +static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr) { int ret = -1; #if defined(CONFIG_SH73A0) - if (i2c_set_addr(base, id, reg, 0) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) goto exit0; #else - if (i2c_set_addr(base, id, reg, 1) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 1) != 0) goto exit0; udelay(100); #endif - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); - irq_dte(base); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); + sh_irq_dte(dev); - writeb(id << 1 | 0x01, &base->icdr); - if (irq_dte_with_tack(base) != 0) + writeb(chip << 1 | 0x01, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); - if (irq_dte_with_tack(base) != 0) + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - ret = readb(&base->icdr) & 0xff; + ret = readb(&dev->icdr) & 0xff; + + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr); + readb(&dev->icdr); /* Dummy read */ + sh_irq_busy(dev); - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); - readb(&base->icdr); /* Dummy read */ - irq_busy(base); exit0: - i2c_finish(base); + sh_i2c_finish(dev); return ret; } -#ifdef CONFIG_I2C_MULTI_BUS -static unsigned int current_bus; - -/** - * i2c_set_bus_num - change active I2C bus - * @bus: bus index, zero based - * @returns: 0 on success, non-0 on failure - */ -int i2c_set_bus_num(unsigned int bus) -{ - if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { - printf("Bad bus: %d\n", bus); - return -1; - } - - switch (bus) { - case 0: - base = (void *)CONFIG_SH_I2C_BASE0; - break; - case 1: - base = (void *)CONFIG_SH_I2C_BASE1; - break; -#ifdef CONFIG_SH_I2C_BASE2 - case 2: - base = (void *)CONFIG_SH_I2C_BASE2; - break; -#endif -#ifdef CONFIG_SH_I2C_BASE3 - case 3: - base = (void *)CONFIG_SH_I2C_BASE3; - break; -#endif -#ifdef CONFIG_SH_I2C_BASE4 - case 4: - base = (void *)CONFIG_SH_I2C_BASE4; - break; -#endif - default: - return -1; - } - current_bus = bus; - - return 0; -} - -/** - * i2c_get_bus_num - returns index of active I2C bus - */ -unsigned int i2c_get_bus_num(void) -{ - return current_bus; -} -#endif - -#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ - ((clk / rate) * (t_low / t_low + t_high)) -#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ - ((clk / rate) * (t_high / t_low + t_high)) - -void i2c_init(int speed, int slaveaddr) +static void +sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { int num, denom, tmp; -#ifdef CONFIG_I2C_MULTI_BUS - current_bus = 0; -#endif - base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; + /* No i2c support prior to relocation */ + if (!(gd->flags & GD_FLG_RELOC)) + return; /* * Calculate the value for iccl. From the data sheet: @@ -266,67 +229,80 @@ void i2c_init(int speed, int slaveaddr) icch = (u16)((num/denom) + 1); else icch = (u16)(num/denom); + + debug("clock: %d, speed %d, iccl: %x, icch: %x\n", + CONFIG_SH_I2C_CLOCK, speed, iccl, icch); } -/* - * i2c_read: - Read multiple bytes from an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be read - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to write the data - * @len: how much byte do we want to read - * @return: 0 in case of success - */ -int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) +static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, u8 *data, int len) { - int ret; - int i = 0; - for (i = 0 ; i < len ; i++) { - ret = i2c_raw_read(base, chip, addr + i); + int ret, i; + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + + for (i = 0; i < len; i++) { + ret = sh_i2c_raw_read(dev, chip, addr + i); if (ret < 0) return -1; - buffer[i] = ret & 0xff; + + data[i] = ret & 0xff; + debug("%s: data[%d]: %02x\n", __func__, i, data[i]); } + return 0; } -/* - * i2c_write: - Write multiple bytes to an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be written - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to find the data to be written - * @len: how much byte do we want to read - * @return: 0 in case of success - */ -int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) +static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, + int alen, u8 *data, int len) { - int i = 0; - for (i = 0; i < len ; i++) - if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0) + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + int i; + + for (i = 0; i < len; i++) { + debug("%s: data[%d]: %02x\n", __func__, i, data[i]); + if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0) return -1; + } return 0; } -/* - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ -int i2c_probe(u8 chip) +static int +sh_i2c_probe(struct i2c_adapter *adap, u8 dev) { - int ret; + u8 dummy[1]; - ret = i2c_set_addr(base, chip, 0, 1); - i2c_finish(base); - return ret; + return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy); +} + +static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + + sh_i2c_finish(dev); + sh_i2c_init(adap, speed, 0); + + return 0; } + +/* + * Register RCAR i2c adapters + */ +U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0) +#ifdef CONFIG_SYS_I2C_SH_BASE1 +U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE2 +U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE3 +U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE4 +U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4) +#endif diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 396fea89af..db9b4026b3 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -25,13 +25,10 @@ #include #include #include -#ifdef CONFIG_AT91_LEGACY +#ifdef CONFIG_ATMEL_LEGACY #include #endif #endif -#ifdef CONFIG_IXP425 /* only valid for IXP425 */ -#include -#endif #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866) #include #endif diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 9ac3969a07..f4142870b3 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -7,6 +7,8 @@ */ #include +#include +#include #include #include #include @@ -19,6 +21,12 @@ DECLARE_GLOBAL_DATA_PTR; +enum i2c_type { + TYPE_114, + TYPE_STD, + TYPE_DVC, +}; + /* Information about i2c controller */ struct i2c_bus { int id; @@ -27,20 +35,17 @@ struct i2c_bus { int pinmux_config; struct i2c_control *control; struct i2c_ctlr *regs; - int is_dvc; /* DVC type, rather than I2C */ - int is_scs; /* single clock source (T114+) */ + enum i2c_type type; int inited; /* bus is inited */ }; -static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS]; - static void set_packet_mode(struct i2c_bus *i2c_bus) { u32 config; config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; - if (i2c_bus->is_dvc) { + if (i2c_bus->type == TYPE_DVC) { struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; writel(config, &dvc->cnfg); @@ -65,6 +70,9 @@ static void i2c_reset_controller(struct i2c_bus *i2c_bus) static void i2c_init_controller(struct i2c_bus *i2c_bus) { + if (!i2c_bus->speed) + return; + debug("%s: speed=%d\n", __func__, i2c_bus->speed); /* * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 * here, in section 23.3.1, but in fact we seem to need a factor of @@ -73,7 +81,7 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, i2c_bus->speed * 2 * 8); - if (i2c_bus->is_scs) { + if (i2c_bus->type == TYPE_114) { /* * T114 I2C went to a single clock source for standard/fast and * HS clock speeds. The new clock rate setting calculation is: @@ -98,7 +106,7 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) i2c_reset_controller(i2c_bus); /* Configure I2C controller. */ - if (i2c_bus->is_dvc) { /* only for DVC I2C */ + if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */ struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); @@ -110,7 +118,8 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) static void send_packet_headers( struct i2c_bus *i2c_bus, struct i2c_trans_info *trans, - u32 packet_id) + u32 packet_id, + bool end_with_repeated_start) { u32 data; @@ -132,6 +141,8 @@ static void send_packet_headers( /* Enable Read if it is not a write transaction */ if (!(trans->flags & I2C_IS_WRITE)) data |= PKT_HDR3_READ_MODE_MASK; + if (end_with_repeated_start) + data |= PKT_HDR3_REPEAT_START_MASK; /* Write I2C specific header */ writel(data, &i2c_bus->control->tx_fifo); @@ -209,7 +220,8 @@ static int send_recv_packets(struct i2c_bus *i2c_bus, int_status = readl(&control->int_status); writel(int_status, &control->int_status); - send_packet_headers(i2c_bus, trans, 1); + send_packet_headers(i2c_bus, trans, 1, + trans->flags & I2C_USE_REPEATED_START); words = DIV_ROUND_UP(trans->num_bytes, 4); last_bytes = trans->num_bytes & 3; @@ -220,14 +232,16 @@ static int send_recv_packets(struct i2c_bus *i2c_bus, if (is_write) { /* deal with word alignment */ - if ((unsigned)dptr & 3) { + if ((words == 1) && last_bytes) { + local = 0; + memcpy(&local, dptr, last_bytes); + } else if ((unsigned)dptr & 3) { memcpy(&local, dptr, sizeof(u32)); - writel(local, &control->tx_fifo); - debug("pkt data sent (0x%x)\n", local); } else { - writel(*wptr, &control->tx_fifo); - debug("pkt data sent (0x%x)\n", *wptr); + local = *wptr; } + writel(local, &control->tx_fifo); + debug("pkt data sent (0x%x)\n", local); if (!wait_for_tx_fifo_empty(control)) { error = -1; goto exit; @@ -266,8 +280,8 @@ exit: return error; } -static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data, - u32 len) +static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, + u32 len, bool end_with_repeated_start) { int error; struct i2c_trans_info trans_info; @@ -275,17 +289,19 @@ static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data, trans_info.address = addr; trans_info.buf = data; trans_info.flags = I2C_IS_WRITE; + if (end_with_repeated_start) + trans_info.flags |= I2C_USE_REPEATED_START; trans_info.num_bytes = len; trans_info.is_10bit_address = 0; - error = send_recv_packets(bus, &trans_info); + error = send_recv_packets(i2c_bus, &trans_info); if (error) debug("tegra_i2c_write_data: Error (%d) !!!\n", error); return error; } -static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data, +static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, u32 len) { int error; @@ -297,52 +313,32 @@ static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data, trans_info.num_bytes = len; trans_info.is_10bit_address = 0; - error = send_recv_packets(bus, &trans_info); + error = send_recv_packets(i2c_bus, &trans_info); if (error) debug("tegra_i2c_read_data: Error (%d) !!!\n", error); return error; } -#ifndef CONFIG_OF_CONTROL -#error "Please enable device tree support to use this driver" -#endif - -/** - * Check that a bus number is valid and return a pointer to it - * - * @param bus_num Bus number to check / return - * @return pointer to bus, if valid, else NULL - */ -static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap) +static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) { - struct i2c_bus *bus; + struct i2c_bus *i2c_bus = dev_get_priv(dev); - bus = &i2c_controllers[adap->hwadapnr]; - if (!bus->inited) { - debug("%s: Bus %u not available\n", __func__, adap->hwadapnr); - return NULL; - } - - return bus; -} - -static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) -{ - struct i2c_bus *bus; - - bus = tegra_i2c_get_bus(adap); - if (!bus) - return 0; - bus->speed = speed; - i2c_init_controller(bus); + i2c_bus->speed = speed; + i2c_init_controller(i2c_bus); return 0; } -static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) +static int tegra_i2c_probe(struct udevice *dev) { + struct i2c_bus *i2c_bus = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + bool is_dvc; + + i2c_bus->id = dev->seq; + i2c_bus->type = dev_get_of_data(dev); i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg"); /* @@ -350,7 +346,6 @@ static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) * far no one needs anything other than the default. */ i2c_bus->pinmux_config = FUNCMUX_DEFAULT; - i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0); i2c_bus->periph_id = clock_decode_periph_id(blob, node); /* @@ -363,103 +358,26 @@ static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; */ if (i2c_bus->periph_id == -1) - return -FDT_ERR_NOTFOUND; - - return 0; -} - -/* - * Process a list of nodes, adding them to our list of I2C ports. - * - * @param blob fdt blob - * @param node_list list of nodes to process (any <=0 are ignored) - * @param count number of nodes to process - * @param is_dvc 1 if these are DVC ports, 0 if standard I2C - * @param is_scs 1 if this HW uses a single clock source (T114+) - * @return 0 if ok, -1 on error - */ -static int process_nodes(const void *blob, int node_list[], int count, - int is_dvc, int is_scs) -{ - struct i2c_bus *i2c_bus; - int i; - - /* build the i2c_controllers[] for each controller */ - for (i = 0; i < count; i++) { - int node = node_list[i]; - - if (node <= 0) - continue; - - i2c_bus = &i2c_controllers[i]; - i2c_bus->id = i; - - if (i2c_get_config(blob, node, i2c_bus)) { - printf("i2c_init_board: failed to decode bus %d\n", i); - return -1; - } - - i2c_bus->is_scs = is_scs; + return -EINVAL; - i2c_bus->is_dvc = is_dvc; - if (is_dvc) { - i2c_bus->control = - &((struct dvc_ctlr *)i2c_bus->regs)->control; - } else { - i2c_bus->control = &i2c_bus->regs->control; - } - debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", - is_dvc ? "dvc" : "i2c", i, i2c_bus->regs, - i2c_bus->periph_id, i2c_bus->speed); - i2c_init_controller(i2c_bus); - debug("ok\n"); - i2c_bus->inited = 1; - - /* Mark position as used */ - node_list[i] = -1; + is_dvc = dev_get_of_data(dev) == TYPE_DVC; + if (is_dvc) { + i2c_bus->control = + &((struct dvc_ctlr *)i2c_bus->regs)->control; + } else { + i2c_bus->control = &i2c_bus->regs->control; } + i2c_init_controller(i2c_bus); + debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", + is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, + i2c_bus->periph_id, i2c_bus->speed); return 0; } -/* Sadly there is no error return from this function */ -void i2c_init_board(void) -{ - int node_list[TEGRA_I2C_NUM_CONTROLLERS]; - const void *blob = gd->fdt_blob; - int count; - - /* First check for newer (T114+) I2C ports */ - count = fdtdec_find_aliases_for_id(blob, "i2c", - COMPAT_NVIDIA_TEGRA114_I2C, node_list, - TEGRA_I2C_NUM_CONTROLLERS); - if (process_nodes(blob, node_list, count, 0, 1)) - return; - - /* Now get the older (T20/T30) normal I2C ports */ - count = fdtdec_find_aliases_for_id(blob, "i2c", - COMPAT_NVIDIA_TEGRA20_I2C, node_list, - TEGRA_I2C_NUM_CONTROLLERS); - if (process_nodes(blob, node_list, count, 0, 0)) - return; - - /* Now look for dvc ports */ - count = fdtdec_add_aliases_for_id(blob, "i2c", - COMPAT_NVIDIA_TEGRA20_DVC, node_list, - TEGRA_I2C_NUM_CONTROLLERS); - if (process_nodes(blob, node_list, count, 1, 0)) - return; -} - -static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - /* This will override the speed selected in the fdt for that port */ - debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); - i2c_set_bus_speed(speed); -} - /* i2c write version without the register address */ -int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) +static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, + int len, bool end_with_repeated_start) { int rc; @@ -471,7 +389,8 @@ int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) debug("\n"); /* Shift 7-bit address over for lower-level i2c functions */ - rc = tegra_i2c_write_data(bus, chip << 1, buffer, len); + rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len, + end_with_repeated_start); if (rc) debug("i2c_write_data(): rc=%d\n", rc); @@ -479,13 +398,14 @@ int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) } /* i2c read version without the register address */ -int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) +static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, + int len) { int rc; debug("inside i2c_read_data():\n"); /* Shift 7-bit address over for lower-level i2c functions */ - rc = tegra_i2c_read_data(bus, chip << 1, buffer, len); + rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len); if (rc) { debug("i2c_read_data(): rc=%d\n", rc); return rc; @@ -501,127 +421,81 @@ int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) } /* Probe to see if a chip is present. */ -static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip) +static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) { - struct i2c_bus *bus; + struct i2c_bus *i2c_bus = dev_get_priv(bus); int rc; - uchar reg; - - debug("i2c_probe: addr=0x%x\n", chip); - bus = tegra_i2c_get_bus(adap); - if (!bus) - return 1; - reg = 0; - rc = i2c_write_data(bus, chip, ®, 1); - if (rc) { - debug("Error probing 0x%x.\n", chip); - return 1; - } - return 0; -} + u8 reg; -static int i2c_addr_ok(const uint addr, const int alen) -{ - /* We support 7 or 10 bit addresses, so one or two bytes each */ - return alen == 1 || alen == 2; + /* Shift 7-bit address over for lower-level i2c functions */ + rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg), + false); + + return rc; } -/* Read bytes */ -static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) +static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) { - struct i2c_bus *bus; - uint offset; - int i; - - debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n", - chip, addr, len); - bus = tegra_i2c_get_bus(adap); - if (!bus) - return 1; - if (!i2c_addr_ok(addr, alen)) { - debug("i2c_read: Bad address %x.%d.\n", addr, alen); - return 1; - } - for (offset = 0; offset < len; offset++) { - if (alen) { - uchar data[alen]; - for (i = 0; i < alen; i++) { - data[alen - i - 1] = - (addr + offset) >> (8 * i); - } - if (i2c_write_data(bus, chip, data, alen)) { - debug("i2c_read: error sending (0x%x)\n", - addr); - return 1; - } + struct i2c_bus *i2c_bus = dev_get_priv(bus); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); + + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) { + ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, + msg->len); + } else { + ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, + msg->len, next_is_read); } - if (i2c_read_data(bus, chip, buffer + offset, 1)) { - debug("i2c_read: error reading (0x%x)\n", addr); - return 1; + if (ret) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; } } return 0; } -/* Write bytes */ -static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) +int tegra_i2c_get_dvc_bus(struct udevice **busp) { - struct i2c_bus *bus; - uint offset; - int i; - - debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n", - chip, addr, len); - bus = tegra_i2c_get_bus(adap); - if (!bus) - return 1; - if (!i2c_addr_ok(addr, alen)) { - debug("i2c_write: Bad address %x.%d.\n", addr, alen); - return 1; - } - for (offset = 0; offset < len; offset++) { - uchar data[alen + 1]; - for (i = 0; i < alen; i++) - data[alen - i - 1] = (addr + offset) >> (8 * i); - data[alen] = buffer[offset]; - if (i2c_write_data(bus, chip, data, alen + 1)) { - debug("i2c_write: error sending (0x%x)\n", addr); - return 1; + struct udevice *bus; + + for (uclass_first_device(UCLASS_I2C, &bus); + bus; + uclass_next_device(&bus)) { + if (dev_get_of_data(bus) == TYPE_DVC) { + *busp = bus; + return 0; } } - return 0; + return -ENODEV; } -int tegra_i2c_get_dvc_bus_num(void) -{ - int i; - - for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) { - struct i2c_bus *bus = &i2c_controllers[i]; - - if (bus->inited && bus->is_dvc) - return i; - } +static const struct dm_i2c_ops tegra_i2c_ops = { + .xfer = tegra_i2c_xfer, + .probe_chip = tegra_i2c_probe_chip, + .set_bus_speed = tegra_i2c_set_bus_speed, +}; - return -1; -} +static const struct udevice_id tegra_i2c_ids[] = { + { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 }, + { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD }, + { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC }, + { } +}; -/* - * Register soft i2c adapters - */ -U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe, - tegra_i2c_read, tegra_i2c_write, - tegra_i2c_set_bus_speed, 100000, 0, 0) -U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe, - tegra_i2c_read, tegra_i2c_write, - tegra_i2c_set_bus_speed, 100000, 0, 1) -U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe, - tegra_i2c_read, tegra_i2c_write, - tegra_i2c_set_bus_speed, 100000, 0, 2) -U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe, - tegra_i2c_read, tegra_i2c_write, - tegra_i2c_set_bus_speed, 100000, 0, 3) +U_BOOT_DRIVER(i2c_tegra) = { + .name = "i2c_tegra", + .id = UCLASS_I2C, + .of_match = tegra_i2c_ids, + .probe = tegra_i2c_probe, + .priv_auto_alloc_size = sizeof(struct i2c_bus), + .ops = &tegra_i2c_ops, +}; diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index ce2d23f725..b3264af452 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -64,18 +64,21 @@ struct zynq_i2c_registers { #define ZYNQ_I2C_FIFO_DEPTH 16 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */ -#if defined(CONFIG_ZYNQ_I2C0) -# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0 -#else -# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1 -#endif - -static struct zynq_i2c_registers *zynq_i2c = - (struct zynq_i2c_registers *)ZYNQ_I2C_BASE; +static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap) +{ + return adap->hwadapnr ? + /* Zynq PS I2C1 */ + (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 : + /* Zynq PS I2C0 */ + (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0; +} /* I2C init called by cmd_i2c when doing 'i2c reset'. */ -void i2c_init(int requested_speed, int slaveadd) +static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, + int slaveadd) { + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); + /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control); @@ -86,7 +89,7 @@ void i2c_init(int requested_speed, int slaveadd) } #ifdef DEBUG -static void zynq_i2c_debug_status(void) +static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c) { int int_status; int status; @@ -128,7 +131,7 @@ static void zynq_i2c_debug_status(void) #endif /* Wait for an interrupt */ -static u32 zynq_i2c_wait(u32 mask) +static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) { int timeout, int_status; @@ -139,7 +142,7 @@ static u32 zynq_i2c_wait(u32 mask) break; } #ifdef DEBUG - zynq_i2c_debug_status(); + zynq_i2c_debug_status(zynq_i2c); #endif /* Clear interrupt status flags */ writel(int_status & mask, &zynq_i2c->interrupt_status); @@ -151,8 +154,10 @@ static u32 zynq_i2c_wait(u32 mask) * I2C probe called by cmd_i2c when doing 'i2c probe'. * Begin read, nak data byte, end. */ -int i2c_probe(u8 dev) +static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) { + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); + /* Attempt to read a byte */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | ZYNQ_I2C_CONTROL_RW); @@ -161,7 +166,7 @@ int i2c_probe(u8 dev) writel(dev, &zynq_i2c->address); writel(1, &zynq_i2c->transfer_size); - return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | + return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | ZYNQ_I2C_INTERRUPT_NACK) & ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; } @@ -170,11 +175,13 @@ int i2c_probe(u8 dev) * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c * Begin write, send address byte(s), begin read, receive data bytes, end. */ -int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) { u32 status; u32 i = 0; u8 *cur_data = data; + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); /* Check the hardware can handle the requested bytes */ if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX)) @@ -187,20 +194,22 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) * Temporarily disable restart (by clearing hold) * It doesn't seem to work. */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW | - ZYNQ_I2C_CONTROL_HOLD); + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); writel(0xFF, &zynq_i2c->interrupt_status); - while (alen--) - writel(addr >> (8*alen), &zynq_i2c->data); - writel(dev, &zynq_i2c->address); + if (alen) { + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); + writel(dev, &zynq_i2c->address); + while (alen--) + writel(addr >> (8 * alen), &zynq_i2c->data); - /* Wait for the address to be sent */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; + /* Wait for the address to be sent */ + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { + /* Release the bus */ + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + debug("Device acked address\n"); } - debug("Device acked address\n"); setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | ZYNQ_I2C_CONTROL_RW); @@ -210,7 +219,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) /* Wait for data */ do { - status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | + status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | ZYNQ_I2C_INTERRUPT_DATA); if (!status) { /* Release the bus */ @@ -226,7 +235,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); #ifdef DEBUG - zynq_i2c_debug_status(); + zynq_i2c_debug_status(zynq_i2c); #endif return 0; } @@ -235,30 +244,34 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c * Begin write, send address byte(s), send data bytes, end. */ -int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) { u8 *cur_data = data; + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); /* Write the register address */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | ZYNQ_I2C_CONTROL_HOLD); clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); writel(0xFF, &zynq_i2c->interrupt_status); - while (alen--) - writel(addr >> (8*alen), &zynq_i2c->data); - /* Start the tranfer */ writel(dev, &zynq_i2c->address); - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; + if (alen) { + while (alen--) + writel(addr >> (8 * alen), &zynq_i2c->data); + /* Start the tranfer */ + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { + /* Release the bus */ + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + debug("Device acked address\n"); } - debug("Device acked address\n"); while (length--) { writel(*(cur_data++), &zynq_i2c->data); if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) { - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); @@ -270,21 +283,25 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) /* All done... release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); /* Wait for the address and data to be sent */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) return -ETIMEDOUT; return 0; } -int i2c_set_bus_num(unsigned int bus) +static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) { - /* Only support bus 0 */ - if (bus > 0) - return -1; - return 0; -} + if (speed != 1000000) + return -EINVAL; -unsigned int i2c_get_bus_num(void) -{ - /* Only support bus 0 */ return 0; } + +U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, + zynq_i2c_write, zynq_i2c_set_bus_speed, + CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, + 0) +U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, + zynq_i2c_write, zynq_i2c_set_bus_speed, + CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, + 1) diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 788540342d..a8e9be2f7f 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -5,34 +5,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libinput.o - -COBJS-$(CONFIG_I8042_KBD) += i8042.o -COBJS-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o -COBJS-$(CONFIG_CROS_EC_KEYB) += cros_ec_keyb.o +obj-$(CONFIG_I8042_KBD) += i8042.o +obj-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o +obj-$(CONFIG_CROS_EC_KEYB) += cros_ec_keyb.o ifdef CONFIG_PS2KBD -COBJS-y += keyboard.o pc_keyb.o -COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o +obj-y += keyboard.o pc_keyb.o +obj-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o endif -COBJS-y += input.o -COBJS-$(CONFIG_OF_CONTROL) += key_matrix.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += input.o +obj-$(CONFIG_OF_CONTROL) += key_matrix.o diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c index e8dac237a9..49ee7b2c9b 100644 --- a/drivers/input/cros_ec_keyb.c +++ b/drivers/input/cros_ec_keyb.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -17,6 +18,8 @@ DECLARE_GLOBAL_DATA_PTR; enum { KBC_MAX_KEYS = 8, /* Maximum keys held down at once */ + KBC_REPEAT_RATE_MS = 30, + KBC_REPEAT_DELAY_MS = 240, }; static struct keyb { @@ -25,8 +28,6 @@ static struct keyb { struct key_matrix matrix; /* The key matrix layer */ int key_rows; /* Number of keyboard rows */ int key_cols; /* Number of keyboard columns */ - unsigned int repeat_delay_ms; /* Time before autorepeat starts */ - unsigned int repeat_rate_ms; /* Autorepeat rate in ms */ int ghost_filter; /* 1 to enable ghost filter, else 0 */ int inited; /* 1 if keyboard is ready */ } config; @@ -39,20 +40,34 @@ static struct keyb { * @param config Keyboard config * @param keys List of keys that we have detected * @param max_count Maximum number of keys to return - * @return number of pressed keys, 0 for none + * @param samep Set to true if this scan repeats the last, else false + * @return number of pressed keys, 0 for none, -EIO on error */ static int check_for_keys(struct keyb *config, - struct key_matrix_key *keys, int max_count) + struct key_matrix_key *keys, int max_count, + bool *samep) { struct key_matrix_key *key; + static struct mbkp_keyscan last_scan; + static bool last_scan_valid; struct mbkp_keyscan scan; unsigned int row, col, bit, data; int num_keys; if (cros_ec_scan_keyboard(config->dev, &scan)) { debug("%s: keyboard scan failed\n", __func__); - return -1; + return -EIO; } + *samep = last_scan_valid && !memcmp(&last_scan, &scan, sizeof(scan)); + + /* + * This is a bit odd. The EC has no way to tell us that it has run + * out of key scans. It just returns the same scan over and over + * again. So the only way to detect that we have run out is to detect + * that this scan is the same as the last. + */ + last_scan_valid = true; + memcpy(&last_scan, &scan, sizeof(last_scan)); for (col = num_keys = bit = 0; col < config->matrix.num_cols; col++) { @@ -78,7 +93,7 @@ static int check_for_keys(struct keyb *config, * * @return 0 if no keys available, 1 if keys are available */ -static int kbd_tstc(void) +static int kbd_tstc(struct stdio_dev *dev) { /* Just get input to do this for us */ return config.inited ? input_tstc(&config.input) : 0; @@ -89,7 +104,7 @@ static int kbd_tstc(void) * * @return ASCII key code, or 0 if no key, or -1 if error */ -static int kbd_getc(void) +static int kbd_getc(struct stdio_dev *dev) { /* Just get input to do this for us */ return config.inited ? input_getc(&config.input) : 0; @@ -112,6 +127,7 @@ int cros_ec_kbc_check(struct input_config *input) int keycodes[KBC_MAX_KEYS]; int num_keys, num_keycodes; int irq_pending, sent; + bool same = false; /* * Loop until the EC has no more keyscan records, or we have @@ -125,7 +141,10 @@ int cros_ec_kbc_check(struct input_config *input) do { irq_pending = cros_ec_interrupt_pending(config.dev); if (irq_pending) { - num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS); + num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS, + &same); + if (num_keys < 0) + return 0; last_num_keys = num_keys; memcpy(last_keys, keys, sizeof(keys)); } else { @@ -142,6 +161,13 @@ int cros_ec_kbc_check(struct input_config *input) num_keycodes = key_matrix_decode(&config.matrix, keys, num_keys, keycodes, KBC_MAX_KEYS); sent = input_send_keycodes(input, keycodes, num_keycodes); + + /* + * For those ECs without an interrupt, stop scanning when we + * see that the scan is the same as last time. + */ + if ((irq_pending < 0) && same) + break; } while (irq_pending && !sent); return 1; @@ -162,8 +188,8 @@ static int cros_ec_keyb_decode_fdt(const void *blob, int node, * Get keyboard rows and columns - at present we are limited to * 8 columns by the protocol (one byte per row scan) */ - config->key_rows = fdtdec_get_int(blob, node, "google,key-rows", 0); - config->key_cols = fdtdec_get_int(blob, node, "google,key-columns", 0); + config->key_rows = fdtdec_get_int(blob, node, "keypad,num-rows", 0); + config->key_cols = fdtdec_get_int(blob, node, "keypad,num-columns", 0); if (!config->key_rows || !config->key_cols || config->key_rows * config->key_cols / 8 > CROS_EC_KEYSCAN_COLS) { @@ -171,10 +197,6 @@ static int cros_ec_keyb_decode_fdt(const void *blob, int node, config->key_rows, config->key_cols); return -1; } - config->repeat_delay_ms = fdtdec_get_int(blob, node, - "google,repeat-delay-ms", 0); - config->repeat_rate_ms = fdtdec_get_int(blob, node, - "google,repeat-rate-ms", 0); config->ghost_filter = fdtdec_get_bool(blob, node, "google,ghost-filter"); return 0; @@ -188,7 +210,7 @@ static int cros_ec_keyb_decode_fdt(const void *blob, int node, * * @return 0 if ok, -1 on error */ -static int cros_ec_init_keyboard(void) +static int cros_ec_init_keyboard(struct stdio_dev *dev) { const void *blob = gd->fdt_blob; int node; @@ -206,8 +228,8 @@ static int cros_ec_init_keyboard(void) } if (cros_ec_keyb_decode_fdt(blob, node, &config)) return -1; - input_set_delays(&config.input, config.repeat_delay_ms, - config.repeat_rate_ms); + input_set_delays(&config.input, KBC_REPEAT_DELAY_MS, + KBC_REPEAT_RATE_MS); if (key_matrix_init(&config.matrix, config.key_rows, config.key_cols, config.ghost_filter)) { debug("%s: cannot init key matrix\n", __func__); diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 8a1e22e8df..ca1604c540 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -2,7 +2,7 @@ * (C) Copyright 2002 ELTEC Elektronik AG * Frank Gottschling * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* i8042.c - Intel 8042 keyboard driver routines */ @@ -398,7 +398,7 @@ int i8042_kbd_init(void) * i8042_tstc - test if keyboard input is available * option: cursor blinking if called in a loop */ -int i8042_tstc(void) +int i8042_tstc(struct stdio_dev *dev) { unsigned char scan_code = 0; @@ -432,7 +432,7 @@ int i8042_tstc(void) * i8042_getc - wait till keyboard input is available * option: turn on/off cursor while waiting */ -int i8042_getc(void) +int i8042_getc(struct stdio_dev *dev) { int ret_chr; unsigned char scan_code; diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c index 614592ef3c..be0f3330db 100644 --- a/drivers/input/keyboard.c +++ b/drivers/input/keyboard.c @@ -70,7 +70,7 @@ static void kbd_put_queue(char data) } /* test if a character is in the queue */ -static int kbd_testc(void) +static int kbd_testc(struct stdio_dev *dev) { #if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) /* no ISR is used, so received chars must be polled */ @@ -83,7 +83,7 @@ static int kbd_testc(void) } /* gets the character from the queue */ -static int kbd_getc(void) +static int kbd_getc(struct stdio_dev *dev) { char c; while(in_pointer==out_pointer) { @@ -275,8 +275,6 @@ int kbd_init (void) memset (&kbddev, 0, sizeof(kbddev)); strcpy(kbddev.name, DEVNAME); kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbddev.putc = NULL ; - kbddev.puts = NULL ; kbddev.getc = kbd_getc ; kbddev.tstc = kbd_testc ; diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index f137f930a9..0ef94f7a00 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -181,7 +181,7 @@ static void kbd_wait_for_fifo_init(struct keyb *config) * @param input Input configuration * @return 1, to indicate that we have something to look at */ -int tegra_kbc_check(struct input_config *input) +static int tegra_kbc_check(struct input_config *input) { kbd_wait_for_fifo_init(&config); check_for_keys(&config); @@ -194,7 +194,7 @@ int tegra_kbc_check(struct input_config *input) * * @return 0 if no keys available, 1 if keys are available */ -static int kbd_tstc(void) +static int kbd_tstc(struct stdio_dev *dev) { /* Just get input to do this for us */ return input_tstc(&config.input); @@ -207,7 +207,7 @@ static int kbd_tstc(void) * * @return ASCII key code, or 0 if no key, or -1 if error */ -static int kbd_getc(void) +static int kbd_getc(struct stdio_dev *dev) { /* Just get input to do this for us */ return input_getc(&config.input); @@ -289,7 +289,7 @@ static void tegra_kbc_open(void) * * @return 0 if ok, -ve on error */ -static int init_tegra_keyboard(void) +static int init_tegra_keyboard(struct stdio_dev *dev) { /* check if already created */ if (config.created) diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile new file mode 100644 index 0000000000..9bfb9c785d --- /dev/null +++ b/drivers/memory/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c new file mode 100644 index 0000000000..f821daea4e --- /dev/null +++ b/drivers/memory/ti-aemif.c @@ -0,0 +1,80 @@ +/* + * Keystone2: Asynchronous EMIF Configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4) +#define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60) +#define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c) +#define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \ + + (cs * 4)) + +#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) +#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) +#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) +#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) +#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) +#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) +#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) +#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) +#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) +#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) + +#define set_config_field(reg, field, val) \ + do { \ + if (val != -1) { \ + reg &= ~AEMIF_CFG_##field(0xffffffff); \ + reg |= AEMIF_CFG_##field(val); \ + } \ + } while (0) + +static void aemif_configure(int cs, struct aemif_config *cfg) +{ + unsigned long tmp; + + if (cfg->mode == AEMIF_MODE_NAND) { + tmp = __raw_readl(AEMIF_NAND_CONTROL); + tmp |= (1 << cs); + __raw_writel(tmp, AEMIF_NAND_CONTROL); + + } else if (cfg->mode == AEMIF_MODE_ONENAND) { + tmp = __raw_readl(AEMIF_ONENAND_CONTROL); + tmp |= (1 << cs); + __raw_writel(tmp, AEMIF_ONENAND_CONTROL); + } + + tmp = __raw_readl(AEMIF_CONFIG(cs)); + + set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); + set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); + set_config_field(tmp, WR_SETUP, cfg->wr_setup); + set_config_field(tmp, WR_STROBE, cfg->wr_strobe); + set_config_field(tmp, WR_HOLD, cfg->wr_hold); + set_config_field(tmp, RD_SETUP, cfg->rd_setup); + set_config_field(tmp, RD_STROBE, cfg->rd_strobe); + set_config_field(tmp, RD_HOLD, cfg->rd_hold); + set_config_field(tmp, TURN_AROUND, cfg->turn_around); + set_config_field(tmp, WIDTH, cfg->width); + + __raw_writel(tmp, AEMIF_CONFIG(cs)); +} + +void aemif_init(int num_cs, struct aemif_config *config) +{ + int cs; + + if (num_cs > AEMIF_NUM_CS) { + num_cs = AEMIF_NUM_CS; + printf("AEMIF: csnum has to be <= 5"); + } + + for (cs = 0; cs < num_cs; cs++) + aemif_configure(cs, config + cs); +} diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig new file mode 100644 index 0000000000..ce90a2cb49 --- /dev/null +++ b/drivers/misc/Kconfig @@ -0,0 +1,7 @@ +config MXC_OCOTP + bool "Freescale OCOTP support" + depends on SOC_MX5 || SOC_MX6 + +config MXS_OCOTP + bool "Freescale OCOTP support" + depends on SOC_MXS diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 08828ee31c..a34972df4e 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -5,40 +5,26 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libmisc.o - -COBJS-$(CONFIG_ALI152X) += ali512x.o -COBJS-$(CONFIG_DS4510) += ds4510.o -COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o -COBJS-$(CONFIG_CROS_EC) += cros_ec.o -COBJS-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o -COBJS-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o -COBJS-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o -COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o -COBJS-$(CONFIG_GPIO_LED) += gpio_led.o -COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o -COBJS-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o -COBJS-$(CONFIG_NS87308) += ns87308.o -COBJS-$(CONFIG_PDSP188x) += pdsp188x.o -COBJS-$(CONFIG_STATUS_LED) += status_led.o -COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_ALI152X) += ali512x.o +obj-$(CONFIG_DS4510) += ds4510.o +obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o +obj-$(CONFIG_CROS_EC) += cros_ec.o +obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o +obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o +obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o +obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_FSL_IIM) += fsl_iim.o +obj-$(CONFIG_GPIO_LED) += gpio_led.o +obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o +obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o +obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o +obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o +obj-$(CONFIG_NS87308) += ns87308.o +obj-$(CONFIG_PDSP188x) += pdsp188x.o +ifdef CONFIG_DM_I2C +obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o +endif +obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_STATUS_LED) += status_led.o +obj-$(CONFIG_TWL4030_LED) += twl4030_led.o +obj-$(CONFIG_FSL_IFC) += fsl_ifc.o diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c index 80a84fdf8f..5f85ccf21e 100644 --- a/drivers/misc/cbmem_console.c +++ b/drivers/misc/cbmem_console.c @@ -31,7 +31,7 @@ struct cbmem_console { static struct cbmem_console *cbmem_console_p; -void cbmemc_putc(char data) +void cbmemc_putc(struct stdio_dev *dev, char data) { int cursor; @@ -40,12 +40,12 @@ void cbmemc_putc(char data) cbmem_console_p->buffer_body[cursor] = data; } -void cbmemc_puts(const char *str) +void cbmemc_puts(struct stdio_dev *dev, const char *str) { char c; while ((c = *str++) != 0) - cbmemc_putc(c); + cbmemc_putc(dev, c); } int cbmemc_init(void) diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 301e8ebbf5..5846e76c49 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -7,21 +7,26 @@ */ /* - * The Matrix Keyboard Protocol driver handles talking to the keyboard - * controller chip. Mostly this is for keyboard functions, but some other - * things have slipped in, so we provide generic services to talk to the - * KBC. + * This is the interface to the Chrome OS EC. It provides keyboard functions, + * power control and battery management. Quite a few other functions are + * provided to enable the EC software to be updated, talk to the EC's I2C bus + * and store a small amount of data in a memory which persists while the EC + * is not reset. */ #include #include +#include #include #include #include #include #include +#include #include #include +#include +#include #ifdef DEBUG_TRACE #define debug_trace(fmt, b...) debug(fmt, #b) @@ -36,7 +41,9 @@ enum { CROS_EC_CMD_HASH_TIMEOUT_MS = 2000, }; +#ifndef CONFIG_DM_CROS_EC static struct cros_ec_dev static_dev, *last_dev; +#endif DECLARE_GLOBAL_DATA_PTR; @@ -73,12 +80,203 @@ int cros_ec_calc_checksum(const uint8_t *data, int size) return csum & 0xff; } +/** + * Create a request packet for protocol version 3. + * + * The packet is stored in the device's internal output buffer. + * + * @param dev CROS-EC device + * @param cmd Command to send (EC_CMD_...) + * @param cmd_version Version of command to send (EC_VER_...) + * @param dout Output data (may be NULL If dout_len=0) + * @param dout_len Size of output data in bytes + * @return packet size in bytes, or <0 if error. + */ +static int create_proto3_request(struct cros_ec_dev *dev, + int cmd, int cmd_version, + const void *dout, int dout_len) +{ + struct ec_host_request *rq = (struct ec_host_request *)dev->dout; + int out_bytes = dout_len + sizeof(*rq); + + /* Fail if output size is too big */ + if (out_bytes > (int)sizeof(dev->dout)) { + debug("%s: Cannot send %d bytes\n", __func__, dout_len); + return -EC_RES_REQUEST_TRUNCATED; + } + + /* Fill in request packet */ + rq->struct_version = EC_HOST_REQUEST_VERSION; + rq->checksum = 0; + rq->command = cmd; + rq->command_version = cmd_version; + rq->reserved = 0; + rq->data_len = dout_len; + + /* Copy data after header */ + memcpy(rq + 1, dout, dout_len); + + /* Write checksum field so the entire packet sums to 0 */ + rq->checksum = (uint8_t)(-cros_ec_calc_checksum(dev->dout, out_bytes)); + + cros_ec_dump_data("out", cmd, dev->dout, out_bytes); + + /* Return size of request packet */ + return out_bytes; +} + +/** + * Prepare the device to receive a protocol version 3 response. + * + * @param dev CROS-EC device + * @param din_len Maximum size of response in bytes + * @return maximum expected number of bytes in response, or <0 if error. + */ +static int prepare_proto3_response_buffer(struct cros_ec_dev *dev, int din_len) +{ + int in_bytes = din_len + sizeof(struct ec_host_response); + + /* Fail if input size is too big */ + if (in_bytes > (int)sizeof(dev->din)) { + debug("%s: Cannot receive %d bytes\n", __func__, din_len); + return -EC_RES_RESPONSE_TOO_BIG; + } + + /* Return expected size of response packet */ + return in_bytes; +} + +/** + * Handle a protocol version 3 response packet. + * + * The packet must already be stored in the device's internal input buffer. + * + * @param dev CROS-EC device + * @param dinp Returns pointer to response data + * @param din_len Maximum size of response in bytes + * @return number of bytes of response data, or <0 if error. Note that error + * codes can be from errno.h or -ve EC_RES_INVALID_CHECKSUM values (and they + * overlap!) + */ +static int handle_proto3_response(struct cros_ec_dev *dev, + uint8_t **dinp, int din_len) +{ + struct ec_host_response *rs = (struct ec_host_response *)dev->din; + int in_bytes; + int csum; + + cros_ec_dump_data("in-header", -1, dev->din, sizeof(*rs)); + + /* Check input data */ + if (rs->struct_version != EC_HOST_RESPONSE_VERSION) { + debug("%s: EC response version mismatch\n", __func__); + return -EC_RES_INVALID_RESPONSE; + } + + if (rs->reserved) { + debug("%s: EC response reserved != 0\n", __func__); + return -EC_RES_INVALID_RESPONSE; + } + + if (rs->data_len > din_len) { + debug("%s: EC returned too much data\n", __func__); + return -EC_RES_RESPONSE_TOO_BIG; + } + + cros_ec_dump_data("in-data", -1, dev->din + sizeof(*rs), rs->data_len); + + /* Update in_bytes to actual data size */ + in_bytes = sizeof(*rs) + rs->data_len; + + /* Verify checksum */ + csum = cros_ec_calc_checksum(dev->din, in_bytes); + if (csum) { + debug("%s: EC response checksum invalid: 0x%02x\n", __func__, + csum); + return -EC_RES_INVALID_CHECKSUM; + } + + /* Return error result, if any */ + if (rs->result) + return -(int)rs->result; + + /* If we're still here, set response data pointer and return length */ + *dinp = (uint8_t *)(rs + 1); + + return rs->data_len; +} + +static int send_command_proto3(struct cros_ec_dev *dev, + int cmd, int cmd_version, + const void *dout, int dout_len, + uint8_t **dinp, int din_len) +{ +#ifdef CONFIG_DM_CROS_EC + struct dm_cros_ec_ops *ops; +#endif + int out_bytes, in_bytes; + int rv; + + /* Create request packet */ + out_bytes = create_proto3_request(dev, cmd, cmd_version, + dout, dout_len); + if (out_bytes < 0) + return out_bytes; + + /* Prepare response buffer */ + in_bytes = prepare_proto3_response_buffer(dev, din_len); + if (in_bytes < 0) + return in_bytes; + +#ifdef CONFIG_DM_CROS_EC + ops = dm_cros_ec_get_ops(dev->dev); + rv = ops->packet ? ops->packet(dev->dev, out_bytes, in_bytes) : -ENOSYS; +#else + switch (dev->interface) { +#ifdef CONFIG_CROS_EC_SPI + case CROS_EC_IF_SPI: + rv = cros_ec_spi_packet(dev, out_bytes, in_bytes); + break; +#endif +#ifdef CONFIG_CROS_EC_SANDBOX + case CROS_EC_IF_SANDBOX: + rv = cros_ec_sandbox_packet(dev, out_bytes, in_bytes); + break; +#endif + case CROS_EC_IF_NONE: + /* TODO: support protocol 3 for LPC, I2C; for now fall through */ + default: + debug("%s: Unsupported interface\n", __func__); + rv = -1; + } +#endif + if (rv < 0) + return rv; + + /* Process the response */ + return handle_proto3_response(dev, dinp, din_len); +} + static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - int ret; +#ifdef CONFIG_DM_CROS_EC + struct dm_cros_ec_ops *ops; +#endif + int ret = -1; + + /* Handle protocol version 3 support */ + if (dev->protocol_version == 3) { + return send_command_proto3(dev, cmd, cmd_version, + dout, dout_len, dinp, din_len); + } +#ifdef CONFIG_DM_CROS_EC + ops = dm_cros_ec_get_ops(dev->dev); + ret = ops->command(dev->dev, cmd, cmd_version, + (const uint8_t *)dout, dout_len, dinp, din_len); +#else switch (dev->interface) { #ifdef CONFIG_CROS_EC_SPI case CROS_EC_IF_SPI: @@ -105,6 +303,7 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, default: ret = -1; } +#endif return ret; } @@ -123,25 +322,21 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, * If not NULL, it will be updated to point to the data * and will always be double word aligned (64-bits) * @param din_len Maximum size of response in bytes - * @return number of bytes in response, or -1 on error + * @return number of bytes in response, or -ve on error */ static int ec_command_inptr(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - uint8_t *din; + uint8_t *din = NULL; int len; - if (cmd_version != 0 && !dev->cmd_version_is_supported) { - debug("%s: Command version >0 unsupported\n", __func__); - return -1; - } len = send_command(dev, cmd, cmd_version, dout, dout_len, &din, din_len); /* If the command doesn't complete, wait a while */ if (len == -EC_RES_IN_PROGRESS) { - struct ec_response_get_comms_status *resp; + struct ec_response_get_comms_status *resp = NULL; ulong start; /* Wait for command to complete */ @@ -169,7 +364,8 @@ static int ec_command_inptr(struct cros_ec_dev *dev, uint8_t cmd, NULL, 0, &din, din_len); } - debug("%s: len=%d, dinp=%p, *dinp=%p\n", __func__, len, dinp, *dinp); + debug("%s: len=%d, dinp=%p, *dinp=%p\n", __func__, len, dinp, + dinp ? *dinp : NULL); if (dinp) { /* If we have any data to return, it must be 64bit-aligned */ assert(len <= 0 || !((uintptr_t)din & 7)); @@ -193,7 +389,7 @@ static int ec_command_inptr(struct cros_ec_dev *dev, uint8_t cmd, * It not NULL, it is a place for ec_command() to copy the * data to. * @param din_len Maximum size of response in bytes - * @return number of bytes in response, or -1 on error + * @return number of bytes in response, or -ve on error */ static int ec_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const void *dout, int dout_len, @@ -220,8 +416,8 @@ static int ec_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, int cros_ec_scan_keyboard(struct cros_ec_dev *dev, struct mbkp_keyscan *scan) { - if (ec_command(dev, EC_CMD_CROS_EC_STATE, 0, NULL, 0, scan, - sizeof(scan->data)) < sizeof(scan->data)) + if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan, + sizeof(scan->data)) != sizeof(scan->data)) return -1; return 0; @@ -232,10 +428,10 @@ int cros_ec_read_id(struct cros_ec_dev *dev, char *id, int maxlen) struct ec_response_get_version *r; if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0, - (uint8_t **)&r, sizeof(*r)) < sizeof(*r)) + (uint8_t **)&r, sizeof(*r)) != sizeof(*r)) return -1; - if (maxlen > sizeof(r->version_string_ro)) + if (maxlen > (int)sizeof(r->version_string_ro)) maxlen = sizeof(r->version_string_ro); switch (r->current_image) { @@ -258,7 +454,7 @@ int cros_ec_read_version(struct cros_ec_dev *dev, { if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0, (uint8_t **)versionp, sizeof(**versionp)) - < sizeof(**versionp)) + != sizeof(**versionp)) return -1; return 0; @@ -267,7 +463,7 @@ int cros_ec_read_version(struct cros_ec_dev *dev, int cros_ec_read_build_info(struct cros_ec_dev *dev, char **strp) { if (ec_command_inptr(dev, EC_CMD_GET_BUILD_INFO, 0, NULL, 0, - (uint8_t **)strp, EC_HOST_PARAM_SIZE) < 0) + (uint8_t **)strp, EC_PROTO2_MAX_PARAM_SIZE) < 0) return -1; return 0; @@ -279,7 +475,7 @@ int cros_ec_read_current_image(struct cros_ec_dev *dev, struct ec_response_get_version *r; if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0, - (uint8_t **)&r, sizeof(*r)) < sizeof(*r)) + (uint8_t **)&r, sizeof(*r)) != sizeof(*r)) return -1; *image = r->current_image; @@ -336,7 +532,7 @@ int cros_ec_read_hash(struct cros_ec_dev *dev, debug("%s: No valid hash (status=%d size=%d). Compute one...\n", __func__, hash->status, hash->size); - p.cmd = EC_VBOOT_HASH_RECALC; + p.cmd = EC_VBOOT_HASH_START; p.hash_type = EC_VBOOT_HASH_TYPE_SHA256; p.nonce_size = 0; p.offset = EC_VBOOT_HASH_OFFSET_RW; @@ -412,16 +608,16 @@ int cros_ec_reboot(struct cros_ec_dev *dev, enum ec_reboot_cmd cmd, int cros_ec_interrupt_pending(struct cros_ec_dev *dev) { /* no interrupt support : always poll */ - if (!fdt_gpio_isvalid(&dev->ec_int)) - return 1; + if (!dm_gpio_is_valid(&dev->ec_int)) + return -ENOENT; - return !gpio_get_value(dev->ec_int.gpio); + return dm_gpio_get_value(&dev->ec_int); } -int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_cros_ec_info *info) +int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_mkbp_info *info) { - if (ec_command(dev, EC_CMD_CROS_EC_INFO, 0, NULL, 0, info, - sizeof(*info)) < sizeof(*info)) + if (ec_command(dev, EC_CMD_MKBP_INFO, 0, NULL, 0, info, + sizeof(*info)) != sizeof(*info)) return -1; return 0; @@ -436,7 +632,7 @@ int cros_ec_get_host_events(struct cros_ec_dev *dev, uint32_t *events_ptr) * used by ACPI/SMI. */ if (ec_command_inptr(dev, EC_CMD_HOST_EVENT_GET_B, 0, NULL, 0, - (uint8_t **)&resp, sizeof(*resp)) < sizeof(*resp)) + (uint8_t **)&resp, sizeof(*resp)) < (int)sizeof(*resp)) return -1; if (resp->mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID)) @@ -474,7 +670,7 @@ int cros_ec_flash_protect(struct cros_ec_dev *dev, if (ec_command(dev, EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT, ¶ms, sizeof(params), - resp, sizeof(*resp)) < sizeof(*resp)) + resp, sizeof(*resp)) != sizeof(*resp)) return -1; return 0; @@ -504,23 +700,31 @@ static int cros_ec_check_version(struct cros_ec_dev *dev) * * So for now, just read all the data anyway. */ - dev->cmd_version_is_supported = 1; + + /* Try sending a version 3 packet */ + dev->protocol_version = 3; + req.in_data = 0; + if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req), + (uint8_t **)&resp, sizeof(*resp)) > 0) { + return 0; + } + + /* Try sending a version 2 packet */ + dev->protocol_version = 2; if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req), (uint8_t **)&resp, sizeof(*resp)) > 0) { - /* It appears to understand new version commands */ - dev->cmd_version_is_supported = 1; - } else { - dev->cmd_version_is_supported = 0; - if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, - sizeof(req), (uint8_t **)&resp, - sizeof(*resp)) < 0) { - debug("%s: Failed both old and new command style\n", - __func__); - return -1; - } + return 0; } - return 0; + /* + * Fail if we're still here, since the EC doesn't understand any + * protcol version we speak. Version 1 interface without command + * version is no longer supported, and we don't know about any new + * protocol versions. + */ + dev->protocol_version = 0; + printf("%s: ERROR: old EC interface not supported\n", __func__); + return -1; } int cros_ec_test(struct cros_ec_dev *dev) @@ -599,8 +803,8 @@ static int cros_ec_flash_write_block(struct cros_ec_dev *dev, p.offset = offset; p.size = size; - assert(data && p.size <= sizeof(p.data)); - memcpy(p.data, data, p.size); + assert(data && p.size <= EC_FLASH_WRITE_VER0_SIZE); + memcpy(&p + 1, data, p.size); return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0, &p, sizeof(p), NULL, 0) >= 0 ? 0 : -1; @@ -611,8 +815,7 @@ static int cros_ec_flash_write_block(struct cros_ec_dev *dev, */ static int cros_ec_flash_write_burst_size(struct cros_ec_dev *dev) { - struct ec_params_flash_write p; - return sizeof(p.data); + return EC_FLASH_WRITE_VER0_SIZE; } /** @@ -718,7 +921,7 @@ int cros_ec_flash_update_rw(struct cros_ec_dev *dev, if (cros_ec_flash_offset(dev, EC_FLASH_REGION_RW, &rw_offset, &rw_size)) return -1; - if (image_size > rw_size) + if (image_size > (int)rw_size) return -1; /* Invalidate the existing hash, just in case the AP reboots @@ -804,7 +1007,7 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state) if (ec_command_inptr(dev, EC_CMD_LDO_GET, 0, ¶ms, sizeof(params), - (uint8_t **)&resp, sizeof(*resp)) < sizeof(*resp)) + (uint8_t **)&resp, sizeof(*resp)) != sizeof(*resp)) return -1; *state = resp->state; @@ -812,8 +1015,10 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state) return 0; } +#ifndef CONFIG_DM_CROS_EC /** - * Decode MBKP details from the device tree and allocate a suitable device. + * Decode EC interface details from the device tree and allocate a suitable + * device. * * @param blob Device tree blob * @param node Node to decode from @@ -858,24 +1063,74 @@ static int cros_ec_decode_fdt(const void *blob, int node, case COMPAT_INTEL_LPC: dev->interface = CROS_EC_IF_LPC; break; +#endif +#ifdef CONFIG_CROS_EC_SANDBOX + case COMPAT_SANDBOX_HOST_EMULATION: + dev->interface = CROS_EC_IF_SANDBOX; + break; #endif default: debug("%s: Unknown compat id %d\n", __func__, compat); return -1; } - fdtdec_decode_gpio(blob, node, "ec-interrupt", &dev->ec_int); + gpio_request_by_name_nodev(blob, node, "ec-interrupt", 0, &dev->ec_int, + GPIOD_IS_IN); dev->optimise_flash_write = fdtdec_get_bool(blob, node, "optimise-flash-write"); *devp = dev; return 0; } +#endif -int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp) +#ifdef CONFIG_DM_CROS_EC +int cros_ec_register(struct udevice *dev) { + struct cros_ec_dev *cdev = dev->uclass_priv; + const void *blob = gd->fdt_blob; + int node = dev->of_offset; char id[MSG_BYTES]; + + cdev->dev = dev; + gpio_request_by_name(dev, "ec-interrupt", 0, &cdev->ec_int, + GPIOD_IS_IN); + cdev->optimise_flash_write = fdtdec_get_bool(blob, node, + "optimise-flash-write"); + + if (cros_ec_check_version(cdev)) { + debug("%s: Could not detect CROS-EC version\n", __func__); + return -CROS_EC_ERR_CHECK_VERSION; + } + + if (cros_ec_read_id(cdev, id, sizeof(id))) { + debug("%s: Could not read KBC ID\n", __func__); + return -CROS_EC_ERR_READ_ID; + } + + /* Remember this device for use by the cros_ec command */ + debug("Google Chrome EC CROS-EC driver ready, id '%s'\n", id); + + return 0; +} +#else +int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp) +{ struct cros_ec_dev *dev; + char id[MSG_BYTES]; +#ifdef CONFIG_DM_CROS_EC + struct udevice *udev; + int ret; + + ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev); + if (!ret) + device_remove(udev); + ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev); + if (ret) + return ret; + dev = udev->uclass_priv; + return 0; +#else int node = 0; *cros_ecp = NULL; @@ -913,16 +1168,18 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp) if (cros_ec_lpc_init(dev, blob)) return -CROS_EC_ERR_DEV_INIT; break; +#endif +#ifdef CONFIG_CROS_EC_SANDBOX + case CROS_EC_IF_SANDBOX: + if (cros_ec_sandbox_init(dev, blob)) + return -CROS_EC_ERR_DEV_INIT; + break; #endif case CROS_EC_IF_NONE: default: return 0; } - - /* we will poll the EC interrupt line */ - fdtdec_setup_gpio(&dev->ec_int); - if (fdt_gpio_isvalid(&dev->ec_int)) - gpio_direction_input(dev->ec_int.gpio); +#endif if (cros_ec_check_version(dev)) { debug("%s: Could not detect CROS-EC version\n", __func__); @@ -935,13 +1192,16 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp) } /* Remember this device for use by the cros_ec command */ - last_dev = *cros_ecp = dev; + *cros_ecp = dev; +#ifndef CONFIG_DM_CROS_EC + last_dev = dev; +#endif debug("Google Chrome EC CROS-EC driver ready, id '%s'\n", id); return 0; } +#endif -#ifdef CONFIG_CMD_CROS_EC int cros_ec_decode_region(int argc, char * const argv[]) { if (argc > 0) { @@ -958,6 +1218,134 @@ int cros_ec_decode_region(int argc, char * const argv[]) return -1; } +int cros_ec_decode_ec_flash(const void *blob, int node, + struct fdt_cros_ec *config) +{ + int flash_node; + + flash_node = fdt_subnode_offset(blob, node, "flash"); + if (flash_node < 0) { + debug("Failed to find flash node\n"); + return -1; + } + + if (fdtdec_read_fmap_entry(blob, flash_node, "flash", + &config->flash)) { + debug("Failed to decode flash node in chrome-ec'\n"); + return -1; + } + + config->flash_erase_value = fdtdec_get_int(blob, flash_node, + "erase-value", -1); + for (node = fdt_first_subnode(blob, flash_node); node >= 0; + node = fdt_next_subnode(blob, node)) { + const char *name = fdt_get_name(blob, node, NULL); + enum ec_flash_region region; + + if (0 == strcmp(name, "ro")) { + region = EC_FLASH_REGION_RO; + } else if (0 == strcmp(name, "rw")) { + region = EC_FLASH_REGION_RW; + } else if (0 == strcmp(name, "wp-ro")) { + region = EC_FLASH_REGION_WP_RO; + } else { + debug("Unknown EC flash region name '%s'\n", name); + return -1; + } + + if (fdtdec_read_fmap_entry(blob, node, "reg", + &config->region[region])) { + debug("Failed to decode flash region in chrome-ec'\n"); + return -1; + } + } + + return 0; +} + +int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr, + int alen, uchar *buffer, int len, int is_read) +{ + union { + struct ec_params_i2c_passthru p; + uint8_t outbuf[EC_PROTO2_MAX_PARAM_SIZE]; + } params; + union { + struct ec_response_i2c_passthru r; + uint8_t inbuf[EC_PROTO2_MAX_PARAM_SIZE]; + } response; + struct ec_params_i2c_passthru *p = ¶ms.p; + struct ec_response_i2c_passthru *r = &response.r; + struct ec_params_i2c_passthru_msg *msg = p->msg; + uint8_t *pdata; + int read_len, write_len; + int size; + int rv; + + p->port = 0; + + if (alen != 1) { + printf("Unsupported address length %d\n", alen); + return -1; + } + if (is_read) { + read_len = len; + write_len = alen; + p->num_msgs = 2; + } else { + read_len = 0; + write_len = alen + len; + p->num_msgs = 1; + } + + size = sizeof(*p) + p->num_msgs * sizeof(*msg); + if (size + write_len > sizeof(params)) { + puts("Params too large for buffer\n"); + return -1; + } + if (sizeof(*r) + read_len > sizeof(response)) { + puts("Read length too big for buffer\n"); + return -1; + } + + /* Create a message to write the register address and optional data */ + pdata = (uint8_t *)p + size; + msg->addr_flags = chip; + msg->len = write_len; + pdata[0] = addr; + if (!is_read) + memcpy(pdata + 1, buffer, len); + msg++; + + if (read_len) { + msg->addr_flags = chip | EC_I2C_FLAG_READ; + msg->len = read_len; + } + + rv = ec_command(dev, EC_CMD_I2C_PASSTHRU, 0, p, size + write_len, + r, sizeof(*r) + read_len); + if (rv < 0) + return rv; + + /* Parse response */ + if (r->i2c_status & EC_I2C_STATUS_ERROR) { + printf("Transfer failed with status=0x%x\n", r->i2c_status); + return -1; + } + + if (rv < sizeof(*r) + read_len) { + puts("Truncated read response\n"); + return -1; + } + + if (read_len) + memcpy(buffer, r->data, read_len); + + return 0; +} + +#ifdef CONFIG_CMD_CROS_EC + /** * Perform a flash read or write command * @@ -1011,9 +1399,193 @@ static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc, return 0; } +/** + * get_alen() - Small parser helper function to get address length + * + * Returns the address length. + */ +static uint get_alen(char *arg) +{ + int j; + int alen; + + alen = 1; + for (j = 0; j < 8; j++) { + if (arg[j] == '.') { + alen = arg[j+1] - '0'; + break; + } else if (arg[j] == '\0') { + break; + } + } + return alen; +} + +#define DISP_LINE_LEN 16 + +/* + * TODO(sjg@chromium.org): This code copied almost verbatim from cmd_i2c.c + * so we can remove it later. + */ +static int cros_ec_i2c_md(struct cros_ec_dev *dev, int flag, int argc, + char * const argv[]) +{ + u_char chip; + uint addr, alen, length = 0x10; + int j, nbytes, linebytes; + + if (argc < 2) + return CMD_RET_USAGE; + + if (1 || (flag & CMD_FLAG_REPEAT) == 0) { + /* + * New command specified. + */ + + /* + * I2C chip address + */ + chip = simple_strtoul(argv[0], NULL, 16); + + /* + * I2C data address within the chip. This can be 1 or + * 2 bytes long. Some day it might be 3 bytes long :-). + */ + addr = simple_strtoul(argv[1], NULL, 16); + alen = get_alen(argv[1]); + if (alen > 3) + return CMD_RET_USAGE; + + /* + * If another parameter, it is the length to display. + * Length is the number of objects, not number of bytes. + */ + if (argc > 2) + length = simple_strtoul(argv[2], NULL, 16); + } + + /* + * Print the lines. + * + * We buffer all read data, so we can make sure data is read only + * once. + */ + nbytes = length; + do { + unsigned char linebuf[DISP_LINE_LEN]; + unsigned char *cp; + + linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; + + if (cros_ec_i2c_xfer(dev, chip, addr, alen, linebuf, linebytes, + 1)) + puts("Error reading the chip.\n"); + else { + printf("%04x:", addr); + cp = linebuf; + for (j = 0; j < linebytes; j++) { + printf(" %02x", *cp++); + addr++; + } + puts(" "); + cp = linebuf; + for (j = 0; j < linebytes; j++) { + if ((*cp < 0x20) || (*cp > 0x7e)) + puts("."); + else + printf("%c", *cp); + cp++; + } + putc('\n'); + } + nbytes -= linebytes; + } while (nbytes > 0); + + return 0; +} + +static int cros_ec_i2c_mw(struct cros_ec_dev *dev, int flag, int argc, + char * const argv[]) +{ + uchar chip; + ulong addr; + uint alen; + uchar byte; + int count; + + if ((argc < 3) || (argc > 4)) + return CMD_RET_USAGE; + + /* + * Chip is always specified. + */ + chip = simple_strtoul(argv[0], NULL, 16); + + /* + * Address is always specified. + */ + addr = simple_strtoul(argv[1], NULL, 16); + alen = get_alen(argv[1]); + if (alen > 3) + return CMD_RET_USAGE; + + /* + * Value to write is always specified. + */ + byte = simple_strtoul(argv[2], NULL, 16); + + /* + * Optional count + */ + if (argc == 4) + count = simple_strtoul(argv[3], NULL, 16); + else + count = 1; + + while (count-- > 0) { + if (cros_ec_i2c_xfer(dev, chip, addr++, alen, &byte, 1, 0)) + puts("Error writing the chip.\n"); + /* + * Wait for the write to complete. The write can take + * up to 10mSec (we allow a little more time). + */ +/* + * No write delay with FRAM devices. + */ +#if !defined(CONFIG_SYS_I2C_FRAM) + udelay(11000); +#endif + } + + return 0; +} + +/* Temporary code until we have driver model and can use the i2c command */ +static int cros_ec_i2c_passthrough(struct cros_ec_dev *dev, int flag, + int argc, char * const argv[]) +{ + const char *cmd; + + if (argc < 1) + return CMD_RET_USAGE; + cmd = *argv++; + argc--; + if (0 == strcmp("md", cmd)) + cros_ec_i2c_md(dev, flag, argc, argv); + else if (0 == strcmp("mw", cmd)) + cros_ec_i2c_mw(dev, flag, argc, argv); + else + return CMD_RET_USAGE; + + return 0; +} + static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct cros_ec_dev *dev = last_dev; + struct cros_ec_dev *dev; +#ifdef CONFIG_DM_CROS_EC + struct udevice *udev; +#endif const char *cmd; int ret = 0; @@ -1022,19 +1594,31 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) cmd = argv[1]; if (0 == strcmp("init", cmd)) { +#ifndef CONFIG_DM_CROS_EC ret = cros_ec_init(gd->fdt_blob, &dev); if (ret) { printf("Could not init cros_ec device (err %d)\n", ret); return 1; } +#endif return 0; } +#ifdef CONFIG_DM_CROS_EC + ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev); + if (ret) { + printf("Cannot get cros-ec device (err=%d)\n", ret); + return 1; + } + dev = udev->uclass_priv; +#else /* Just use the last allocated device; there should be only one */ if (!last_dev) { printf("No CROS-EC device available\n"); return 1; } + dev = last_dev; +#endif if (0 == strcmp("id", cmd)) { char id[MSG_BYTES]; @@ -1044,7 +1628,7 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } printf("%s\n", id); } else if (0 == strcmp("info", cmd)) { - struct ec_response_cros_ec_info info; + struct ec_response_mkbp_info info; if (cros_ec_info(dev, &info)) { debug("%s: Could not read KBC info\n", __func__); @@ -1213,10 +1797,10 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (!ret) { /* Print versions */ printf("RO version: %1.*s\n", - sizeof(p->version_string_ro), + (int)sizeof(p->version_string_ro), p->version_string_ro); printf("RW version: %1.*s\n", - sizeof(p->version_string_rw), + (int)sizeof(p->version_string_rw), p->version_string_rw); printf("Firmware copy: %s\n", (p->current_image < @@ -1254,6 +1838,8 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) debug("%s: Could not access LDO%d\n", __func__, index); return ret; } + } else if (0 == strcmp("i2c", cmd)) { + ret = cros_ec_i2c_passthrough(dev, flag, argc - 2, argv + 2); } else { return CMD_RET_USAGE; } @@ -1267,7 +1853,7 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - crosec, 5, 1, do_cros_ec, + crosec, 6, 1, do_cros_ec, "CROS-EC utility command", "init Re-init CROS-EC (done on startup automatically)\n" "crosec id Read CROS-EC ID\n" @@ -1284,6 +1870,16 @@ U_BOOT_CMD( "crosec vbnvcontext [hexstring] Read [write] VbNvContext from EC\n" "crosec ldo [] Switch/Read LDO state\n" "crosec test run tests on cros_ec\n" - "crosec version Read CROS-EC version" + "crosec version Read CROS-EC version\n" + "crosec i2c md chip address[.0, .1, .2] [# of objects] - read from I2C passthru\n" + "crosec i2c mw chip address[.0, .1, .2] value [count] - write to I2C passthru (fill)" ); #endif + +#ifdef CONFIG_DM_CROS_EC +UCLASS_DRIVER(cros_ec) = { + .id = UCLASS_CROS_EC, + .name = "cros_ec", + .per_device_auto_alloc_size = sizeof(struct cros_ec_dev), +}; +#endif diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c index 0fbab991b5..f9bc9750d4 100644 --- a/drivers/misc/cros_ec_i2c.c +++ b/drivers/misc/cros_ec_i2c.c @@ -14,6 +14,7 @@ */ #include +#include #include #include @@ -23,11 +24,11 @@ #define debug_trace(fmt, b...) #endif -int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len) +static int cros_ec_i2c_command(struct udevice *udev, uint8_t cmd, + int cmd_version, const uint8_t *dout, + int dout_len, uint8_t **dinp, int din_len) { - int old_bus = 0; + struct cros_ec_dev *dev = udev->uclass_priv; /* version8, cmd8, arglen8, out8[dout_len], csum8 */ int out_bytes = dout_len + 4; /* response8, arglen8, in8[din_len], checksum8 */ @@ -35,9 +36,7 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, uint8_t *ptr; /* Receive input data, so that args will be dword aligned */ uint8_t *in_ptr; - int ret; - - old_bus = i2c_get_bus_num(); + int len, csum, ret; /* * Sanity-check I/O sizes given transaction overhead in internal @@ -67,80 +66,62 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, * will be dword aligned. */ in_ptr = dev->din + sizeof(int64_t); - if (!dev->cmd_version_is_supported) { - /* Send an old-style command */ - *ptr++ = cmd; - out_bytes = dout_len + 1; - in_bytes = din_len + 2; - in_ptr--; /* Expect just a status byte */ - } else { - *ptr++ = EC_CMD_VERSION0 + cmd_version; - *ptr++ = cmd; - *ptr++ = dout_len; - in_ptr -= 2; /* Expect status, length bytes */ + + if (dev->protocol_version != 2) { + /* Something we don't support */ + debug("%s: Protocol version %d unsupported\n", + __func__, dev->protocol_version); + return -1; } + + *ptr++ = EC_CMD_VERSION0 + cmd_version; + *ptr++ = cmd; + *ptr++ = dout_len; + in_ptr -= 2; /* Expect status, length bytes */ + memcpy(ptr, dout, dout_len); ptr += dout_len; - if (dev->cmd_version_is_supported) - *ptr++ = (uint8_t) - cros_ec_calc_checksum(dev->dout, dout_len + 3); - - /* Set to the proper i2c bus */ - if (i2c_set_bus_num(dev->bus_num)) { - debug("%s: Cannot change to I2C bus %d\n", __func__, - dev->bus_num); - return -1; - } + *ptr++ = (uint8_t) + cros_ec_calc_checksum(dev->dout, dout_len + 3); /* Send output data */ cros_ec_dump_data("out", -1, dev->dout, out_bytes); - ret = i2c_write(dev->addr, 0, 0, dev->dout, out_bytes); + ret = dm_i2c_write(udev, 0, dev->dout, out_bytes); if (ret) { - debug("%s: Cannot complete I2C write to 0x%x\n", - __func__, dev->addr); + debug("%s: Cannot complete I2C write to %s\n", __func__, + udev->name); ret = -1; } if (!ret) { - ret = i2c_read(dev->addr, 0, 0, in_ptr, in_bytes); + ret = dm_i2c_read(udev, 0, in_ptr, in_bytes); if (ret) { - debug("%s: Cannot complete I2C read from 0x%x\n", - __func__, dev->addr); + debug("%s: Cannot complete I2C read from %s\n", + __func__, udev->name); ret = -1; } } - /* Return to original bus number */ - i2c_set_bus_num(old_bus); - if (ret) - return ret; - if (*in_ptr != EC_RES_SUCCESS) { debug("%s: Received bad result code %d\n", __func__, *in_ptr); return -(int)*in_ptr; } - if (dev->cmd_version_is_supported) { - int len, csum; - - len = in_ptr[1]; - if (len + 3 > sizeof(dev->din)) { - debug("%s: Received length %#02x too large\n", - __func__, len); - return -1; - } - csum = cros_ec_calc_checksum(in_ptr, 2 + len); - if (csum != in_ptr[2 + len]) { - debug("%s: Invalid checksum rx %#02x, calced %#02x\n", - __func__, in_ptr[2 + din_len], csum); - return -1; - } - din_len = min(din_len, len); - cros_ec_dump_data("in", -1, in_ptr, din_len + 3); - } else { - cros_ec_dump_data("in (old)", -1, in_ptr, in_bytes); + len = in_ptr[1]; + if (len + 3 > sizeof(dev->din)) { + debug("%s: Received length %#02x too large\n", + __func__, len); + return -1; } + csum = cros_ec_calc_checksum(in_ptr, 2 + len); + if (csum != in_ptr[2 + len]) { + debug("%s: Invalid checksum rx %#02x, calced %#02x\n", + __func__, in_ptr[2 + din_len], csum); + return -1; + } + din_len = min(din_len, len); + cros_ec_dump_data("in", -1, in_ptr, din_len + 3); /* Return pointer to dword-aligned input data, if any */ *dinp = dev->din + sizeof(int64_t); @@ -148,37 +129,24 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, return din_len; } -int cros_ec_i2c_decode_fdt(struct cros_ec_dev *dev, const void *blob) +static int cros_ec_probe(struct udevice *dev) { - /* Decode interface-specific FDT params */ - dev->max_frequency = fdtdec_get_int(blob, dev->node, - "i2c-max-frequency", 100000); - dev->bus_num = i2c_get_bus_num_fdt(dev->parent_node); - if (dev->bus_num == -1) { - debug("%s: Failed to read bus number\n", __func__); - return -1; - } - dev->addr = fdtdec_get_int(blob, dev->node, "reg", -1); - if (dev->addr == -1) { - debug("%s: Failed to read device address\n", __func__); - return -1; - } - - return 0; + return cros_ec_register(dev); } -/** - * Initialize I2C protocol. - * - * @param dev CROS_EC device - * @param blob Device tree blob - * @return 0 if ok, -1 on error - */ -int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob) -{ - i2c_init(dev->max_frequency, dev->addr); - - dev->cmd_version_is_supported = 0; - - return 0; -} +static struct dm_cros_ec_ops cros_ec_ops = { + .command = cros_ec_i2c_command, +}; + +static const struct udevice_id cros_ec_ids[] = { + { .compatible = "google,cros-ec" }, + { } +}; + +U_BOOT_DRIVER(cros_ec_i2c) = { + .name = "cros_ec", + .id = UCLASS_CROS_EC, + .of_match = cros_ec_ids, + .probe = cros_ec_probe, + .ops = &cros_ec_ops, +}; diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c index 725747693d..07624a136f 100644 --- a/drivers/misc/cros_ec_lpc.c +++ b/drivers/misc/cros_ec_lpc.c @@ -40,71 +40,6 @@ static int wait_for_sync(struct cros_ec_dev *dev) return 0; } -/** - * Send a command to a LPC CROS_EC device and return the reply. - * - * The device's internal input/output buffers are used. - * - * @param dev CROS_EC device - * @param cmd Command to send (EC_CMD_...) - * @param cmd_version Version of command to send (EC_VER_...) - * @param dout Output data (may be NULL If dout_len=0) - * @param dout_len Size of output data in bytes - * @param dinp Place to put pointer to response data - * @param din_len Maximum size of response in bytes - * @return number of bytes in response, or -1 on error - */ -static int old_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len) -{ - int ret, i; - - if (dout_len > EC_OLD_PARAM_SIZE) { - debug("%s: Cannot send %d bytes\n", __func__, dout_len); - return -1; - } - - if (din_len > EC_OLD_PARAM_SIZE) { - debug("%s: Cannot receive %d bytes\n", __func__, din_len); - return -1; - } - - if (wait_for_sync(dev)) { - debug("%s: Timeout waiting ready\n", __func__); - return -1; - } - - debug_trace("cmd: %02x, ", cmd); - for (i = 0; i < dout_len; i++) { - debug_trace("%02x ", dout[i]); - outb(dout[i], EC_LPC_ADDR_OLD_PARAM + i); - } - outb(cmd, EC_LPC_ADDR_HOST_CMD); - debug_trace("\n"); - - if (wait_for_sync(dev)) { - debug("%s: Timeout waiting ready\n", __func__); - return -1; - } - - ret = inb(EC_LPC_ADDR_HOST_DATA); - if (ret) { - debug("%s: CROS_EC result code %d\n", __func__, ret); - return -ret; - } - - debug_trace("resp: %02x, ", ret); - for (i = 0; i < din_len; i++) { - dev->din[i] = inb(EC_LPC_ADDR_OLD_PARAM + i); - debug_trace("%02x ", dev->din[i]); - } - debug_trace("\n"); - *dinp = dev->din; - - return din_len; -} - int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const uint8_t *dout, int dout_len, uint8_t **dinp, int din_len) @@ -119,12 +54,7 @@ int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, int csum; int i; - /* Fall back to old-style command interface if args aren't supported */ - if (!dev->cmd_version_is_supported) - return old_lpc_command(dev, cmd, dout, dout_len, dinp, - din_len); - - if (dout_len > EC_HOST_PARAM_SIZE) { + if (dout_len > EC_PROTO2_MAX_PARAM_SIZE) { debug("%s: Cannot send %d bytes\n", __func__, dout_len); return -1; } @@ -229,7 +159,7 @@ int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob) byte = 0xff; byte &= inb(EC_LPC_ADDR_HOST_CMD); byte &= inb(EC_LPC_ADDR_HOST_DATA); - for (i = 0; i < EC_HOST_PARAM_SIZE && (byte == 0xff); i++) + for (i = 0; i < EC_PROTO2_MAX_PARAM_SIZE && (byte == 0xff); i++) byte &= inb(EC_LPC_ADDR_HOST_PARAM + i); if (byte == 0xff) { debug("%s: CROS_EC device not found on LPC bus\n", @@ -256,13 +186,9 @@ int cros_ec_lpc_check_version(struct cros_ec_dev *dev) (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS) & EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED)) { - dev->cmd_version_is_supported = 1; - } else { - /* We are going to use the old IO ports */ - dev->cmd_version_is_supported = 0; + return 0; } - debug("lpc: version %s\n", dev->cmd_version_is_supported ? - "new" : "old"); - return 0; + printf("%s: ERROR: old EC interface not supported\n", __func__); + return -1; } diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c new file mode 100644 index 0000000000..99cc5297cf --- /dev/null +++ b/drivers/misc/cros_ec_sandbox.c @@ -0,0 +1,644 @@ +/* + * Chromium OS cros_ec driver - sandbox emulation + * + * Copyright (c) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Ultimately it shold be possible to connect an Chrome OS EC emulation + * to U-Boot and remove all of this code. But this provides a test + * environment for bringing up chromeos_sandbox and demonstrating its + * utility. + * + * This emulation includes the following: + * + * 1. Emulation of the keyboard, by converting keypresses received from SDL + * into key scan data, passed back from the EC as key scan messages. The + * key layout is read from the device tree. + * + * 2. Emulation of vboot context - so this can be read/written as required. + * + * 3. Save/restore of EC state, so that the vboot context, flash memory + * contents and current image can be preserved across boots. This is important + * since the EC is supposed to continue running even if the AP resets. + * + * 4. Some event support, in particular allowing Escape to be pressed on boot + * to enter recovery mode. The EC passes this to U-Boot through the normal + * event message. + * + * 5. Flash read/write/erase support, so that software sync works. The + * protect messages are supported but no protection is implemented. + * + * 6. Hashing of the EC image, again to support software sync. + * + * Other features can be added, although a better path is probably to link + * the EC image in with U-Boot (Vic has demonstrated a prototype for this). + */ + +DECLARE_GLOBAL_DATA_PTR; + +#define KEYBOARD_ROWS 8 +#define KEYBOARD_COLS 13 + +/* A single entry of the key matrix */ +struct ec_keymatrix_entry { + int row; /* key matrix row */ + int col; /* key matrix column */ + int keycode; /* corresponding linux key code */ +}; + +/** + * struct ec_state - Information about the EC state + * + * @vbnv_context: Vboot context data stored by EC + * @ec_config: FDT config information about the EC (e.g. flashmap) + * @flash_data: Contents of flash memory + * @flash_data_len: Size of flash memory + * @current_image: Current image the EC is running + * @matrix_count: Number of keys to decode in matrix + * @matrix: Information about keyboard matrix + * @keyscan: Current keyscan information (bit set for each row/column pressed) + * @recovery_req: Keyboard recovery requested + */ +struct ec_state { + uint8_t vbnv_context[EC_VBNV_BLOCK_SIZE]; + struct fdt_cros_ec ec_config; + uint8_t *flash_data; + int flash_data_len; + enum ec_current_image current_image; + int matrix_count; + struct ec_keymatrix_entry *matrix; /* the key matrix info */ + uint8_t keyscan[KEYBOARD_COLS]; + bool recovery_req; +} s_state, *g_state; + +/** + * cros_ec_read_state() - read the sandbox EC state from the state file + * + * If data is available, then blob and node will provide access to it. If + * not this function sets up an empty EC. + * + * @param blob: Pointer to device tree blob, or NULL if no data to read + * @param node: Node offset to read from + */ +static int cros_ec_read_state(const void *blob, int node) +{ + struct ec_state *ec = &s_state; + const char *prop; + int len; + + /* Set everything to defaults */ + ec->current_image = EC_IMAGE_RO; + if (!blob) + return 0; + + /* Read the data if available */ + ec->current_image = fdtdec_get_int(blob, node, "current-image", + EC_IMAGE_RO); + prop = fdt_getprop(blob, node, "vbnv-context", &len); + if (prop && len == sizeof(ec->vbnv_context)) + memcpy(ec->vbnv_context, prop, len); + + prop = fdt_getprop(blob, node, "flash-data", &len); + if (prop) { + ec->flash_data_len = len; + ec->flash_data = os_malloc(len); + if (!ec->flash_data) + return -ENOMEM; + memcpy(ec->flash_data, prop, len); + debug("%s: Loaded EC flash data size %#x\n", __func__, len); + } + + return 0; +} + +/** + * cros_ec_write_state() - Write out our state to the state file + * + * The caller will ensure that there is a node ready for the state. The node + * may already contain the old state, in which case it is overridden. + * + * @param blob: Device tree blob holding state + * @param node: Node to write our state into + */ +static int cros_ec_write_state(void *blob, int node) +{ + struct ec_state *ec = g_state; + + /* We are guaranteed enough space to write basic properties */ + fdt_setprop_u32(blob, node, "current-image", ec->current_image); + fdt_setprop(blob, node, "vbnv-context", ec->vbnv_context, + sizeof(ec->vbnv_context)); + return state_setprop(node, "flash-data", ec->flash_data, + ec->ec_config.flash.length); +} + +SANDBOX_STATE_IO(cros_ec, "google,cros-ec", cros_ec_read_state, + cros_ec_write_state); + +/** + * Return the number of bytes used in the specified image. + * + * This is the actual size of code+data in the image, as opposed to the + * amount of space reserved in flash for that image. This code is similar to + * that used by the real EC code base. + * + * @param ec Current emulated EC state + * @param entry Flash map entry containing the image to check + * @return actual image size in bytes, 0 if the image contains no content or + * error. + */ +static int get_image_used(struct ec_state *ec, struct fmap_entry *entry) +{ + int size; + + /* + * Scan backwards looking for 0xea byte, which is by definition the + * last byte of the image. See ec.lds.S for how this is inserted at + * the end of the image. + */ + for (size = entry->length - 1; + size > 0 && ec->flash_data[entry->offset + size] != 0xea; + size--) + ; + + return size ? size + 1 : 0; /* 0xea byte IS part of the image */ +} + +/** + * Read the key matrix from the device tree + * + * Keymap entries in the fdt take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * + * @param ec Current emulated EC state + * @param blob Device tree blob containing keyscan information + * @param node Keyboard node of device tree containing keyscan information + * @return 0 if ok, -1 on error + */ +static int keyscan_read_fdt_matrix(struct ec_state *ec, const void *blob, + int node) +{ + const u32 *cell; + int upto; + int len; + + cell = fdt_getprop(blob, node, "linux,keymap", &len); + ec->matrix_count = len / 4; + ec->matrix = calloc(ec->matrix_count, sizeof(*ec->matrix)); + if (!ec->matrix) { + debug("%s: Out of memory for key matrix\n", __func__); + return -1; + } + + /* Now read the data */ + for (upto = 0; upto < ec->matrix_count; upto++) { + struct ec_keymatrix_entry *matrix = &ec->matrix[upto]; + u32 word; + + word = fdt32_to_cpu(*cell++); + matrix->row = word >> 24; + matrix->col = (word >> 16) & 0xff; + matrix->keycode = word & 0xffff; + + /* Hard-code some sanity limits for now */ + if (matrix->row >= KEYBOARD_ROWS || + matrix->col >= KEYBOARD_COLS) { + debug("%s: Matrix pos out of range (%d,%d)\n", + __func__, matrix->row, matrix->col); + return -1; + } + } + + if (upto != ec->matrix_count) { + debug("%s: Read mismatch from key matrix\n", __func__); + return -1; + } + + return 0; +} + +/** + * Return the next keyscan message contents + * + * @param ec Current emulated EC state + * @param scan Place to put keyscan bytes for the keyscan message (must hold + * enough space for a full keyscan) + * @return number of bytes of valid scan data + */ +static int cros_ec_keyscan(struct ec_state *ec, uint8_t *scan) +{ + const struct ec_keymatrix_entry *matrix; + int bytes = KEYBOARD_COLS; + int key[8]; /* allow up to 8 keys to be pressed at once */ + int count; + int i; + + memset(ec->keyscan, '\0', bytes); + count = sandbox_sdl_scan_keys(key, ARRAY_SIZE(key)); + + /* Look up keycode in matrix */ + for (i = 0, matrix = ec->matrix; i < ec->matrix_count; i++, matrix++) { + bool found; + int j; + + for (found = false, j = 0; j < count; j++) { + if (matrix->keycode == key[j]) + found = true; + } + + if (found) { + debug("%d: %d,%d\n", matrix->keycode, matrix->row, + matrix->col); + ec->keyscan[matrix->col] |= 1 << matrix->row; + } + } + + memcpy(scan, ec->keyscan, bytes); + return bytes; +} + +/** + * Process an emulated EC command + * + * @param ec Current emulated EC state + * @param req_hdr Pointer to request header + * @param req_data Pointer to body of request + * @param resp_hdr Pointer to place to put response header + * @param resp_data Pointer to place to put response data, if any + * @return length of response data, or 0 for no response data, or -1 on error + */ +static int process_cmd(struct ec_state *ec, + struct ec_host_request *req_hdr, const void *req_data, + struct ec_host_response *resp_hdr, void *resp_data) +{ + int len; + + /* TODO(sjg@chromium.org): Check checksums */ + debug("EC command %#0x\n", req_hdr->command); + + switch (req_hdr->command) { + case EC_CMD_HELLO: { + const struct ec_params_hello *req = req_data; + struct ec_response_hello *resp = resp_data; + + resp->out_data = req->in_data + 0x01020304; + len = sizeof(*resp); + break; + } + case EC_CMD_GET_VERSION: { + struct ec_response_get_version *resp = resp_data; + + strcpy(resp->version_string_ro, "sandbox_ro"); + strcpy(resp->version_string_rw, "sandbox_rw"); + resp->current_image = ec->current_image; + debug("Current image %d\n", resp->current_image); + len = sizeof(*resp); + break; + } + case EC_CMD_VBNV_CONTEXT: { + const struct ec_params_vbnvcontext *req = req_data; + struct ec_response_vbnvcontext *resp = resp_data; + + switch (req->op) { + case EC_VBNV_CONTEXT_OP_READ: + memcpy(resp->block, ec->vbnv_context, + sizeof(resp->block)); + len = sizeof(*resp); + break; + case EC_VBNV_CONTEXT_OP_WRITE: + memcpy(ec->vbnv_context, resp->block, + sizeof(resp->block)); + len = 0; + break; + default: + printf(" ** Unknown vbnv_context command %#02x\n", + req->op); + return -1; + } + break; + } + case EC_CMD_REBOOT_EC: { + const struct ec_params_reboot_ec *req = req_data; + + printf("Request reboot type %d\n", req->cmd); + switch (req->cmd) { + case EC_REBOOT_DISABLE_JUMP: + len = 0; + break; + case EC_REBOOT_JUMP_RW: + ec->current_image = EC_IMAGE_RW; + len = 0; + break; + default: + puts(" ** Unknown type"); + return -1; + } + break; + } + case EC_CMD_HOST_EVENT_GET_B: { + struct ec_response_host_event_mask *resp = resp_data; + + resp->mask = 0; + if (ec->recovery_req) { + resp->mask |= EC_HOST_EVENT_MASK( + EC_HOST_EVENT_KEYBOARD_RECOVERY); + } + + len = sizeof(*resp); + break; + } + case EC_CMD_VBOOT_HASH: { + const struct ec_params_vboot_hash *req = req_data; + struct ec_response_vboot_hash *resp = resp_data; + struct fmap_entry *entry; + int ret, size; + + entry = &ec->ec_config.region[EC_FLASH_REGION_RW]; + + switch (req->cmd) { + case EC_VBOOT_HASH_RECALC: + case EC_VBOOT_HASH_GET: + size = SHA256_SUM_LEN; + len = get_image_used(ec, entry); + ret = hash_block("sha256", + ec->flash_data + entry->offset, + len, resp->hash_digest, &size); + if (ret) { + printf(" ** hash_block() failed\n"); + return -1; + } + resp->status = EC_VBOOT_HASH_STATUS_DONE; + resp->hash_type = EC_VBOOT_HASH_TYPE_SHA256; + resp->digest_size = size; + resp->reserved0 = 0; + resp->offset = entry->offset; + resp->size = len; + len = sizeof(*resp); + break; + default: + printf(" ** EC_CMD_VBOOT_HASH: Unknown command %d\n", + req->cmd); + return -1; + } + break; + } + case EC_CMD_FLASH_PROTECT: { + const struct ec_params_flash_protect *req = req_data; + struct ec_response_flash_protect *resp = resp_data; + uint32_t expect = EC_FLASH_PROTECT_ALL_NOW | + EC_FLASH_PROTECT_ALL_AT_BOOT; + + printf("mask=%#x, flags=%#x\n", req->mask, req->flags); + if (req->flags == expect || req->flags == 0) { + resp->flags = req->flags ? EC_FLASH_PROTECT_ALL_NOW : + 0; + resp->valid_flags = EC_FLASH_PROTECT_ALL_NOW; + resp->writable_flags = 0; + len = sizeof(*resp); + } else { + puts(" ** unexpected flash protect request\n"); + return -1; + } + break; + } + case EC_CMD_FLASH_REGION_INFO: { + const struct ec_params_flash_region_info *req = req_data; + struct ec_response_flash_region_info *resp = resp_data; + struct fmap_entry *entry; + + switch (req->region) { + case EC_FLASH_REGION_RO: + case EC_FLASH_REGION_RW: + case EC_FLASH_REGION_WP_RO: + entry = &ec->ec_config.region[req->region]; + resp->offset = entry->offset; + resp->size = entry->length; + len = sizeof(*resp); + printf("EC flash region %d: offset=%#x, size=%#x\n", + req->region, resp->offset, resp->size); + break; + default: + printf("** Unknown flash region %d\n", req->region); + return -1; + } + break; + } + case EC_CMD_FLASH_ERASE: { + const struct ec_params_flash_erase *req = req_data; + + memset(ec->flash_data + req->offset, + ec->ec_config.flash_erase_value, + req->size); + len = 0; + break; + } + case EC_CMD_FLASH_WRITE: { + const struct ec_params_flash_write *req = req_data; + + memcpy(ec->flash_data + req->offset, req + 1, req->size); + len = 0; + break; + } + case EC_CMD_MKBP_STATE: + len = cros_ec_keyscan(ec, resp_data); + break; + default: + printf(" ** Unknown EC command %#02x\n", req_hdr->command); + return -1; + } + + return len; +} + +#ifdef CONFIG_DM_CROS_EC +int cros_ec_sandbox_packet(struct udevice *udev, int out_bytes, int in_bytes) +{ + struct cros_ec_dev *dev = udev->uclass_priv; + struct ec_state *ec = dev_get_priv(dev->dev); +#else +int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, + int in_bytes) +{ + struct ec_state *ec = &s_state; +#endif + struct ec_host_request *req_hdr = (struct ec_host_request *)dev->dout; + const void *req_data = req_hdr + 1; + struct ec_host_response *resp_hdr = (struct ec_host_response *)dev->din; + void *resp_data = resp_hdr + 1; + int len; + + len = process_cmd(ec, req_hdr, req_data, resp_hdr, resp_data); + if (len < 0) + return len; + + resp_hdr->struct_version = 3; + resp_hdr->result = EC_RES_SUCCESS; + resp_hdr->data_len = len; + resp_hdr->reserved = 0; + len += sizeof(*resp_hdr); + resp_hdr->checksum = 0; + resp_hdr->checksum = (uint8_t) + -cros_ec_calc_checksum((const uint8_t *)resp_hdr, len); + + return in_bytes; +} + +int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob) +{ + return 0; +} + +void cros_ec_check_keyboard(struct cros_ec_dev *dev) +{ +#ifdef CONFIG_DM_CROS_EC + struct ec_state *ec = dev_get_priv(dev->dev); +#else + struct ec_state *ec = &s_state; +#endif + ulong start; + + printf("Press keys for EC to detect on reset (ESC=recovery)..."); + start = get_timer(0); + while (get_timer(start) < 1000) + ; + putc('\n'); + if (!sandbox_sdl_key_pressed(KEY_ESC)) { + ec->recovery_req = true; + printf(" - EC requests recovery\n"); + } +} + +#ifdef CONFIG_DM_CROS_EC +int cros_ec_probe(struct udevice *dev) +{ + struct ec_state *ec = dev->priv; + struct cros_ec_dev *cdev = dev->uclass_priv; + const void *blob = gd->fdt_blob; + int node; + int err; + + memcpy(ec, &s_state, sizeof(*ec)); + err = cros_ec_decode_ec_flash(blob, dev->of_offset, &ec->ec_config); + if (err) + return err; + + node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB); + if (node < 0) { + debug("%s: No cros_ec keyboard found\n", __func__); + } else if (keyscan_read_fdt_matrix(ec, blob, node)) { + debug("%s: Could not read key matrix\n", __func__); + return -1; + } + + /* If we loaded EC data, check that the length matches */ + if (ec->flash_data && + ec->flash_data_len != ec->ec_config.flash.length) { + printf("EC data length is %x, expected %x, discarding data\n", + ec->flash_data_len, ec->ec_config.flash.length); + os_free(ec->flash_data); + ec->flash_data = NULL; + } + + /* Otherwise allocate the memory */ + if (!ec->flash_data) { + ec->flash_data_len = ec->ec_config.flash.length; + ec->flash_data = os_malloc(ec->flash_data_len); + if (!ec->flash_data) + return -ENOMEM; + } + + cdev->dev = dev; + g_state = ec; + return cros_ec_register(dev); +} + +#else + +/** + * Initialize sandbox EC emulation. + * + * @param dev CROS_EC device + * @param blob Device tree blob + * @return 0 if ok, -1 on error + */ +int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob) +{ + struct ec_state *ec = &s_state; + int node; + int err; + + node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC); + if (node < 0) { + debug("Failed to find chrome-ec node'\n"); + return -1; + } + + err = cros_ec_decode_ec_flash(blob, node, &ec->ec_config); + if (err) + return err; + + node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB); + if (node < 0) { + debug("%s: No cros_ec keyboard found\n", __func__); + } else if (keyscan_read_fdt_matrix(ec, blob, node)) { + debug("%s: Could not read key matrix\n", __func__); + return -1; + } + + /* If we loaded EC data, check that the length matches */ + if (ec->flash_data && + ec->flash_data_len != ec->ec_config.flash.length) { + printf("EC data length is %x, expected %x, discarding data\n", + ec->flash_data_len, ec->ec_config.flash.length); + os_free(ec->flash_data); + ec->flash_data = NULL; + } + + /* Otherwise allocate the memory */ + if (!ec->flash_data) { + ec->flash_data_len = ec->ec_config.flash.length; + ec->flash_data = os_malloc(ec->flash_data_len); + if (!ec->flash_data) + return -ENOMEM; + } + + return 0; +} +#endif + +#ifdef CONFIG_DM_CROS_EC +struct dm_cros_ec_ops cros_ec_ops = { + .packet = cros_ec_sandbox_packet, +}; + +static const struct udevice_id cros_ec_ids[] = { + { .compatible = "google,cros-ec" }, + { } +}; + +U_BOOT_DRIVER(cros_ec_sandbox) = { + .name = "cros_ec", + .id = UCLASS_CROS_EC, + .of_match = cros_ec_ids, + .probe = cros_ec_probe, + .priv_auto_alloc_size = sizeof(struct ec_state), + .ops = &cros_ec_ops, +}; +#endif diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index 202acf258b..9359c56e87 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -15,8 +15,38 @@ #include #include +#include +#include #include +DECLARE_GLOBAL_DATA_PTR; + +int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes) +{ + struct cros_ec_dev *dev = udev->uclass_priv; + struct spi_slave *slave = dev_get_parentdata(dev->dev); + int rv; + + /* Do the transfer */ + if (spi_claim_bus(slave)) { + debug("%s: Cannot claim SPI bus\n", __func__); + return -1; + } + + rv = spi_xfer(slave, max(out_bytes, in_bytes) * 8, + dev->dout, dev->din, + SPI_XFER_BEGIN | SPI_XFER_END); + + spi_release_bus(slave); + + if (rv) { + debug("%s: Cannot complete SPI transfer\n", __func__); + return -1; + } + + return in_bytes; +} + /** * Send a command to a LPC CROS_EC device and return the reply. * @@ -32,16 +62,24 @@ * @param din_len Maximum size of response in bytes * @return number of bytes in response, or -1 on error */ -int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, +int cros_ec_spi_command(struct udevice *udev, uint8_t cmd, int cmd_version, const uint8_t *dout, int dout_len, uint8_t **dinp, int din_len) { + struct cros_ec_dev *dev = udev->uclass_priv; + struct spi_slave *slave = dev_get_parentdata(dev->dev); int in_bytes = din_len + 4; /* status, length, checksum, trailer */ uint8_t *out; uint8_t *p; int csum, len; int rv; + if (dev->protocol_version != 2) { + debug("%s: Unsupported EC protcol version %d\n", + __func__, dev->protocol_version); + return -1; + } + /* * Sanity-check input size to make sure it plus transaction overhead * fits in the internal device buffer. @@ -62,13 +100,13 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, */ memset(dev->din, '\0', in_bytes); - if (spi_claim_bus(dev->spi)) { + if (spi_claim_bus(slave)) { debug("%s: Cannot claim SPI bus\n", __func__); return -1; } out = dev->dout; - out[0] = cmd_version; + out[0] = EC_CMD_VERSION0 + cmd_version; out[1] = cmd; out[2] = (uint8_t)dout_len; memcpy(out + 3, dout, dout_len); @@ -83,17 +121,17 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, p = dev->din + sizeof(int64_t) - 2; len = dout_len + 4; cros_ec_dump_data("out", cmd, out, len); - rv = spi_xfer(dev->spi, max(len, in_bytes) * 8, out, p, + rv = spi_xfer(slave, max(len, in_bytes) * 8, out, p, SPI_XFER_BEGIN | SPI_XFER_END); - spi_release_bus(dev->spi); + spi_release_bus(slave); if (rv) { debug("%s: Cannot complete SPI transfer\n", __func__); return -1; } - len = min(p[1], din_len); + len = min((int)p[1], din_len); cros_ec_dump_data("in", -1, p, len + 3); /* Response code is first byte of message */ @@ -116,31 +154,25 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, return len; } -int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob) +static int cros_ec_probe(struct udevice *dev) { - /* Decode interface-specific FDT params */ - dev->max_frequency = fdtdec_get_int(blob, dev->node, - "spi-max-frequency", 500000); - dev->cs = fdtdec_get_int(blob, dev->node, "reg", 0); - - return 0; + return cros_ec_register(dev); } -/** - * Initialize SPI protocol. - * - * @param dev CROS_EC device - * @param blob Device tree blob - * @return 0 if ok, -1 on error - */ -int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob) -{ - dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, - dev->cs, dev->max_frequency, 0); - if (!dev->spi) { - debug("%s: Could not setup SPI slave\n", __func__); - return -1; - } - - return 0; -} +static struct dm_cros_ec_ops cros_ec_ops = { + .packet = cros_ec_spi_packet, + .command = cros_ec_spi_command, +}; + +static const struct udevice_id cros_ec_ids[] = { + { .compatible = "google,cros-ec" }, + { } +}; + +U_BOOT_DRIVER(cros_ec_spi) = { + .name = "cros_ec", + .id = UCLASS_CROS_EC, + .of_match = cros_ec_ids, + .probe = cros_ec_probe, + .ops = &cros_ec_ops, +}; diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/drivers/misc/fsl_ifc.c similarity index 85% rename from arch/powerpc/cpu/mpc8xxx/fsl_ifc.c rename to drivers/misc/fsl_ifc.c index 2d0fb433bc..3902e9ff53 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -6,7 +6,7 @@ */ #include -#include +#include void print_ifc_regs(void) { @@ -33,6 +33,9 @@ void init_early_memctl_regs(void) #ifndef CONFIG_A003399_NOR_WORKAROUND #ifdef CONFIG_SYS_CSPR0_EXT set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); +#endif +#ifdef CONFIG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); #endif set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); @@ -43,6 +46,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR1_EXT set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); #endif +#ifdef CONFIG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); @@ -57,6 +63,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR2_EXT set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); #endif +#ifdef CONFIG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#endif #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); @@ -71,6 +80,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR3_EXT set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); #endif +#ifdef CONFIG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#endif #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); @@ -85,6 +97,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR4_EXT set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); #endif +#ifdef CONFIG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#endif #if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); @@ -99,6 +114,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR5_EXT set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); #endif +#ifdef CONFIG_SYS_CSOR5_EXT + set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); +#endif #if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); @@ -113,6 +131,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR6_EXT set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); #endif +#ifdef CONFIG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#endif #if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); @@ -127,6 +148,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR7_EXT set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); #endif +#ifdef CONFIG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#endif #if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); @@ -138,3 +162,10 @@ void init_early_memctl_regs(void) set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); #endif } + +void init_final_memctl_regs(void) +{ +#ifdef CONFIG_SYS_CSPR0_FINAL + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); +#endif +} diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c index 588bfda09f..008919f99b 100644 --- a/drivers/misc/fsl_iim.c +++ b/drivers/misc/fsl_iim.c @@ -16,6 +16,9 @@ #ifndef CONFIG_MPC512X #include #endif +#if defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) +#include +#endif /* FSL IIM-specific constants */ #define STAT_BUSY 0x80 @@ -93,6 +96,10 @@ struct fsl_iim { } bank[8]; }; +#if !defined(CONFIG_SOC_MX51) && !defined(CONFIG_SOC_MX53) +#define enable_efuse_prog_supply(enable) +#endif + static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert, const char *caller) { @@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val) if (ret) return ret; + enable_efuse_prog_supply(1); for (bit = 0; val; bit++, val >>= 1) if (val & 0x01) { ret = prog_bit(regs, bank, word, bit); - if (ret) + if (ret) { + enable_efuse_prog_supply(0); return ret; + } } + enable_efuse_prog_supply(0); return 0; } diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c index 3fedddc8b5..3e95727d79 100644 --- a/drivers/misc/gpio_led.c +++ b/drivers/misc/gpio_led.c @@ -9,15 +9,42 @@ #include #include +#ifndef CONFIG_GPIO_LED_INVERTED_TABLE +#define CONFIG_GPIO_LED_INVERTED_TABLE {} +#endif + +static led_id_t gpio_led_inv[] = CONFIG_GPIO_LED_INVERTED_TABLE; + +static int gpio_led_gpio_value(led_id_t mask, int state) +{ + int i, gpio_value = (state == STATUS_LED_ON); + + for (i = 0; i < ARRAY_SIZE(gpio_led_inv); i++) { + if (gpio_led_inv[i] == mask) + gpio_value = !gpio_value; + } + + return gpio_value; +} + void __led_init(led_id_t mask, int state) { - gpio_request(mask, "gpio_led"); - gpio_direction_output(mask, state == STATUS_LED_ON); + int gpio_value; + + if (gpio_request(mask, "gpio_led") != 0) { + printf("%s: failed requesting GPIO%lu!\n", __func__, mask); + return; + } + + gpio_value = gpio_led_gpio_value(mask, state); + gpio_direction_output(mask, gpio_value); } void __led_set(led_id_t mask, int state) { - gpio_set_value(mask, state == STATUS_LED_ON); + int gpio_value = gpio_led_gpio_value(mask, state); + + gpio_set_value(mask, gpio_value); } void __led_toggle(led_id_t mask) diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c new file mode 100644 index 0000000000..814134a2cb --- /dev/null +++ b/drivers/misc/i2c_eeprom.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, + int size) +{ + return -ENODEV; +} + +static int i2c_eeprom_write(struct udevice *dev, int offset, + const uint8_t *buf, int size) +{ + return -ENODEV; +} + +struct i2c_eeprom_ops i2c_eeprom_std_ops = { + .read = i2c_eeprom_read, + .write = i2c_eeprom_write, +}; + +int i2c_eeprom_std_probe(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id i2c_eeprom_std_ids[] = { + { .compatible = "i2c-eeprom" }, + { } +}; + +U_BOOT_DRIVER(i2c_eeprom_std) = { + .name = "i2c_eeprom", + .id = UCLASS_I2C_EEPROM, + .of_match = i2c_eeprom_std_ids, + .probe = i2c_eeprom_std_probe, + .priv_auto_alloc_size = sizeof(struct i2c_eeprom), + .ops = &i2c_eeprom_std_ops, +}; + +UCLASS_DRIVER(i2c_eeprom) = { + .id = UCLASS_I2C_EEPROM, + .name = "i2c_eeprom", +}; diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c new file mode 100644 index 0000000000..7343445d42 --- /dev/null +++ b/drivers/misc/i2c_eeprom_emul.c @@ -0,0 +1,168 @@ +/* + * Simulate an I2C eeprom + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#ifdef DEBUG +#define debug_buffer print_buffer +#else +#define debug_buffer(x, ...) +#endif + +DECLARE_GLOBAL_DATA_PTR; + +struct sandbox_i2c_flash_plat_data { + enum sandbox_i2c_eeprom_test_mode test_mode; + const char *filename; + int offset_len; /* Length of an offset in bytes */ + int size; /* Size of data buffer */ +}; + +struct sandbox_i2c_flash { + uint8_t *data; +}; + +void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev, + enum sandbox_i2c_eeprom_test_mode mode) +{ + struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev); + + plat->test_mode = mode; +} + +void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len) +{ + struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev); + + plat->offset_len = offset_len; +} + +static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg, + int nmsgs) +{ + struct sandbox_i2c_flash *priv = dev_get_priv(emul); + uint offset = 0; + + debug("\n%s\n", __func__); + debug_buffer(0, priv->data, 1, 16, 0); + for (; nmsgs > 0; nmsgs--, msg++) { + struct sandbox_i2c_flash_plat_data *plat = + dev_get_platdata(emul); + int len; + u8 *ptr; + + if (!plat->size) + return -ENODEV; + if (msg->addr + msg->len > plat->size) { + debug("%s: Address %x, len %x is outside range 0..%x\n", + __func__, msg->addr, msg->len, plat->size); + return -EINVAL; + } + len = msg->len; + debug(" %s: msg->len=%d", + msg->flags & I2C_M_RD ? "read" : "write", + msg->len); + if (msg->flags & I2C_M_RD) { + if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE) + len = 1; + debug(", offset %x, len %x: ", offset, len); + memcpy(msg->buf, priv->data + offset, len); + memset(msg->buf + len, '\xff', msg->len - len); + debug_buffer(0, msg->buf, 1, msg->len, 0); + } else if (len >= plat->offset_len) { + int i; + + ptr = msg->buf; + for (i = 0; i < plat->offset_len; i++, len--) + offset = (offset << 8) | *ptr++; + debug(", set offset %x: ", offset); + debug_buffer(0, msg->buf, 1, msg->len, 0); + if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE) + len = min(len, 1); + + /* For testing, map offsets into our limited buffer */ + for (i = 24; i > 0; i -= 8) { + if (offset > (1 << i)) { + offset = (offset >> i) | + (offset & ((1 << i) - 1)); + offset += i; + } + } + memcpy(priv->data + offset, ptr, len); + } + } + debug_buffer(0, priv->data, 1, 16, 0); + + return 0; +} + +struct dm_i2c_ops sandbox_i2c_emul_ops = { + .xfer = sandbox_i2c_eeprom_xfer, +}; + +static int sandbox_i2c_eeprom_ofdata_to_platdata(struct udevice *dev) +{ + struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev); + + plat->size = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "sandbox,size", 32); + plat->filename = fdt_getprop(gd->fdt_blob, dev->of_offset, + "sandbox,filename", NULL); + if (!plat->filename) { + debug("%s: No filename for device '%s'\n", __func__, + dev->name); + return -EINVAL; + } + plat->test_mode = SIE_TEST_MODE_NONE; + plat->offset_len = 1; + + return 0; +} + +static int sandbox_i2c_eeprom_probe(struct udevice *dev) +{ + struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev); + struct sandbox_i2c_flash *priv = dev_get_priv(dev); + + priv->data = calloc(1, plat->size); + if (!priv->data) + return -ENOMEM; + + return 0; +} + +static int sandbox_i2c_eeprom_remove(struct udevice *dev) +{ + struct sandbox_i2c_flash *priv = dev_get_priv(dev); + + free(priv->data); + + return 0; +} + +static const struct udevice_id sandbox_i2c_ids[] = { + { .compatible = "sandbox,i2c-eeprom" }, + { } +}; + +U_BOOT_DRIVER(sandbox_i2c_emul) = { + .name = "sandbox_i2c_eeprom_emul", + .id = UCLASS_I2C_EMUL, + .of_match = sandbox_i2c_ids, + .ofdata_to_platdata = sandbox_i2c_eeprom_ofdata_to_platdata, + .probe = sandbox_i2c_eeprom_probe, + .remove = sandbox_i2c_eeprom_remove, + .priv_auto_alloc_size = sizeof(struct sandbox_i2c_flash), + .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_flash_plat_data), + .ops = &sandbox_i2c_emul_ops, +}; diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 3de1245699..5fb86ca6b2 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -60,7 +60,7 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; if (bank >= ARRAY_SIZE((*regs)->bank) || - word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || + word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) || !assert) { printf("mxc_ocotp %s(): Invalid argument\n", caller); return -EINVAL; @@ -81,8 +81,6 @@ static int finish_access(struct ocotp_regs *regs, const char *caller) err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); clear_error(regs); - enable_ocotp_clk(0); - if (err) { printf("mxc_ocotp %s(): Access protect error\n", caller); return -EIO; @@ -122,8 +120,8 @@ static void set_timing(struct ocotp_regs *regs) relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, 1000000000) + 2 * (relax + 1) - 1; - strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) + - 2 * (relax + 1) - 1; + strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US, + 1000000) + 2 * (relax + 1) - 1; timing = BF(strobe_read, TIMING_STROBE_READ) | BF(relax, TIMING_RELAX) | diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c new file mode 100644 index 0000000000..6f0a1d3e6d --- /dev/null +++ b/drivers/misc/mxs_ocotp.c @@ -0,0 +1,317 @@ +/* + * Freescale i.MX28 OCOTP Driver + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block + * used in i.MX6 . While these blocks are very similar at the first + * glance, by digging deeper, one will notice differences (like the + * tight dependence on MXS power block, some completely new registers + * etc.) which would make common driver an ifdef nightmare :-( + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MXS_OCOTP_TIMEOUT 100000 + +static struct mxs_ocotp_regs *ocotp_regs = + (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; +static struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; +static struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + +static int mxs_ocotp_wait_busy_clear(void) +{ + uint32_t reg; + int timeout = MXS_OCOTP_TIMEOUT; + + while (--timeout) { + reg = readl(&ocotp_regs->hw_ocotp_ctrl); + if (!(reg & OCOTP_CTRL_BUSY)) + break; + udelay(10); + } + + if (!timeout) + return -EINVAL; + + /* Wait a little as per FSL datasheet's 'write postamble' section. */ + udelay(10); + + return 0; +} + +static void mxs_ocotp_clear_error(void) +{ + writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr); +} + +static int mxs_ocotp_read_bank_open(bool open) +{ + int ret = 0; + + if (open) { + writel(OCOTP_CTRL_RD_BANK_OPEN, + &ocotp_regs->hw_ocotp_ctrl_set); + + /* + * Wait before polling the BUSY bit, since the BUSY bit might + * be asserted only after a few HCLK cycles and if we were to + * poll immediatelly, we could miss the busy bit. + */ + udelay(10); + ret = mxs_ocotp_wait_busy_clear(); + } else { + writel(OCOTP_CTRL_RD_BANK_OPEN, + &ocotp_regs->hw_ocotp_ctrl_clr); + } + + return ret; +} + +static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val) +{ + uint32_t scale_val; + + if (enter) { + /* + * Enter the fuse programming VDDIO voltage setup. We start + * scaling the voltage from it's current value down to 2.8V + * which is the one and only correct voltage for programming + * the OCOTP fuses (according to datasheet). + */ + scale_val = readl(&power_regs->hw_power_vddioctrl); + scale_val &= POWER_VDDIOCTRL_TRG_MASK; + + /* Return the original voltage. */ + *val = scale_val; + + /* + * Start scaling VDDIO down to 0x2, which is 2.8V . Actually, + * the value 0x0 should be 2.8V, but that's not the case on + * most designs due to load etc., so we play safe. Undervolt + * can actually cause incorrect programming of the fuses and + * or reboots of the board. + */ + while (scale_val > 2) { + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, --scale_val); + udelay(500); + } + } else { + /* Start scaling VDDIO up to original value . */ + for (scale_val = 2; scale_val <= *val; scale_val++) { + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, scale_val); + udelay(500); + } + } + + mdelay(10); +} + +static int mxs_ocotp_wait_hclk_ready(void) +{ + uint32_t reg, timeout = MXS_OCOTP_TIMEOUT; + + while (--timeout) { + reg = readl(&clkctrl_regs->hw_clkctrl_hbus); + if (!(reg & CLKCTRL_HBUS_ASM_BUSY)) + break; + } + + if (!timeout) + return -EINVAL; + + return 0; +} + +static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val) +{ + uint32_t scale_val; + int ret; + + ret = mxs_ocotp_wait_hclk_ready(); + if (ret) + return ret; + + /* Set CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); + + if (enter) { + /* Return the original HCLK clock speed. */ + *val = readl(&clkctrl_regs->hw_clkctrl_hbus); + *val &= CLKCTRL_HBUS_DIV_MASK; + + /* Scale the HCLK to 454/19 = 23.9 MHz . */ + scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET; + scale_val &= CLKCTRL_HBUS_DIV_MASK; + } else { + /* Scale the HCLK back to original frequency. */ + scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET; + scale_val &= CLKCTRL_HBUS_DIV_MASK; + } + + writel(CLKCTRL_HBUS_DIV_MASK, + &clkctrl_regs->hw_clkctrl_hbus_set); + writel(scale_val, + &clkctrl_regs->hw_clkctrl_hbus_clr); + + mdelay(10); + + ret = mxs_ocotp_wait_hclk_ready(); + if (ret) + return ret; + + /* Disable CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_clr); + + mdelay(10); + + return 0; +} + +static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask) +{ + uint32_t hclk_val, vddio_val; + int ret; + + mxs_ocotp_clear_error(); + + /* Make sure the banks are closed for reading. */ + ret = mxs_ocotp_read_bank_open(0); + if (ret) { + puts("Failed closing banks for reading!\n"); + return ret; + } + + ret = mxs_ocotp_scale_hclk(1, &hclk_val); + if (ret) { + puts("Failed scaling down the HCLK!\n"); + return ret; + } + mxs_ocotp_scale_vddio(1, &vddio_val); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + goto fail; + } + + /* Program the fuse address */ + writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl); + + /* Program the data. */ + writel(mask, &ocotp_regs->hw_ocotp_data); + + udelay(10); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + goto fail; + } + + /* Check for errors */ + if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) { + puts("Failed writing fuses!\n"); + ret = -EPERM; + goto fail; + } + +fail: + mxs_ocotp_scale_vddio(0, &vddio_val); + if (mxs_ocotp_scale_hclk(0, &hclk_val)) + puts("Failed scaling up the HCLK!\n"); + + return ret; +} + +static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val) +{ + int ret; + + /* Register offset from CUST0 */ + reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + return ret; + } + + mxs_ocotp_clear_error(); + + ret = mxs_ocotp_read_bank_open(1); + if (ret) { + puts("Failed opening banks for reading!\n"); + return ret; + } + + *val = readl(reg); + + ret = mxs_ocotp_read_bank_open(0); + if (ret) { + puts("Failed closing banks for reading!\n"); + return ret; + } + + return ret; +} + +static int mxs_ocotp_valid(u32 bank, u32 word) +{ + if (bank > 4) + return -EINVAL; + if (word > 7) + return -EINVAL; + return 0; +} + +/* + * The 'fuse' command API + */ +int fuse_read(u32 bank, u32 word, u32 *val) +{ + int ret; + + ret = mxs_ocotp_valid(bank, word); + if (ret) + return ret; + + return mxs_ocotp_read_fuse((bank << 3) | word, val); +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + int ret; + + ret = mxs_ocotp_valid(bank, word); + if (ret) + return ret; + + return mxs_ocotp_write_fuse((bank << 3) | word, val); +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + /* We do not support sensing :-( */ + return -EINVAL; +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + /* We do not support overriding :-( */ + return -EINVAL; +} diff --git a/drivers/misc/smsc_lpc47m.c b/drivers/misc/smsc_lpc47m.c new file mode 100644 index 0000000000..d51f8e3024 --- /dev/null +++ b/drivers/misc/smsc_lpc47m.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static void pnp_enter_conf_state(u16 dev) +{ + u16 port = dev >> 8; + + outb(0x55, port); +} + +static void pnp_exit_conf_state(u16 dev) +{ + u16 port = dev >> 8; + + outb(0xaa, port); +} + +void lpc47m_enable_serial(u16 dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/drivers/misc/status_led.c b/drivers/misc/status_led.c index 6b71ad4f25..ed9adb21d6 100644 --- a/drivers/misc/status_led.c +++ b/drivers/misc/status_led.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig new file mode 100644 index 0000000000..b3d0000454 --- /dev/null +++ b/drivers/mmc/Kconfig @@ -0,0 +1,34 @@ +menu "MMC Host controller Support" + +config MMC + bool + +config GENERIC_MMC + bool + select MMC + +config SH_SDHI + bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" + depends on RMOBILE + help + Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform + +config FSL_ESDHC + bool "Freescale ESDHC controller" + select GENERIC_MMC + +config FSL_USDHC + bool "Support USDHC" + depends on SOC_MX6 + depends on FSL_ESDHC + +config MXS_MMC + bool "i.MXS MMC/SDHC controller" + depends on SOC_MXS || SOC_MX6 + select GENERIC_MMC + +config SUPPORT_EMMC_BOOT + bool "Support boot from eMMC" + depends on MMC + +endmenu diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 49e5cb9c2a..4ba5878936 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -5,48 +5,40 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o +obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o +obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o +obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o +obj-$(CONFIG_DWMMC) += dw_mmc.o +obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o +obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o +obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o +obj-$(CONFIG_GENERIC_MMC) += mmc.o +obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o +obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o +obj-$(CONFIG_MMC_SPI) += mmc_spi.o +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o +obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o +obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o +obj-$(CONFIG_MXC_MMC) += mxcmmc.o +obj-$(CONFIG_MXS_MMC) += mxsmmc.o +obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o +obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o +obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o +obj-$(CONFIG_S3C_SDI) += s3c_sdi.o +obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o +obj-$(CONFIG_SDHCI) += sdhci.o +obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o +obj-$(CONFIG_SH_SDHI) += sh_sdhi.o +obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o +obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o +obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o +obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o +else +obj-$(CONFIG_GENERIC_MMC) += mmc_write.o +endif -LIB := $(obj)libmmc.o - - -COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o -COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o -COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o -COBJS-$(CONFIG_FTSDC010) += ftsdc010_mci.o -COBJS-$(CONFIG_GENERIC_MMC) += mmc.o -COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o -COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o -COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o -COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o -COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o -COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o -COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o -COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o -COBJS-$(CONFIG_SDHCI) += sdhci.o -COBJS-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o -COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o -COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o -COBJS-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o -COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o -COBJS-$(CONFIG_DWMMC) += dw_mmc.o -COBJS-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o -COBJS-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index 5a55fe73b7..5ef7ff7ff2 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -287,9 +287,9 @@ static void host_set_ios(struct mmc *dev) u32 clkdiv = 0; u32 tmp_clock; - if (dev->clock >= dev->f_max) { + if (dev->clock >= dev->cfg->f_max) { clkdiv = 0; - dev->clock = dev->f_max; + dev->clock = dev->cfg->f_max; } else { clkdiv = (host->clock_in / dev->clock) - 2; } @@ -335,6 +335,12 @@ static void host_set_ios(struct mmc *dev) udelay(CLK_CHANGE_DELAY); } +static const struct mmc_ops arm_pl180_mmci_ops = { + .send_cmd = host_request, + .set_ios = host_set_ios, + .init = mmc_host_reset, +}; + /* * mmc_host_init - initialize the mmc controller. * Set initial clock and power for mmc slot. @@ -342,16 +348,9 @@ static void host_set_ios(struct mmc *dev) */ int arm_pl180_mmci_init(struct pl180_mmc_host *host) { - struct mmc *dev; + struct mmc *mmc; u32 sdi_u32; - dev = malloc(sizeof(struct mmc)); - if (!dev) - return -ENOMEM; - - memset(dev, 0, sizeof(struct mmc)); - dev->priv = host; - writel(host->pwr_init, &host->base->power); writel(host->clkdiv_init, &host->base->clock); udelay(CLK_CHANGE_DELAY); @@ -359,19 +358,24 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host) /* Disable mmc interrupts */ sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK; writel(sdi_u32, &host->base->mask0); - strncpy(dev->name, host->name, sizeof(dev->name)); - dev->send_cmd = host_request; - dev->set_ios = host_set_ios; - dev->init = mmc_host_reset; - dev->getcd = NULL; - dev->getwp = NULL; - dev->host_caps = host->caps; - dev->voltages = host->voltages; - dev->f_min = host->clock_min; - dev->f_max = host->clock_max; - dev->b_max = host->b_max; - mmc_register(dev); - debug("registered mmc interface number is:%d\n", dev->block_dev.dev); + + host->cfg.name = host->name; + host->cfg.ops = &arm_pl180_mmci_ops; + /* TODO remove the duplicates */ + host->cfg.host_caps = host->caps; + host->cfg.voltages = host->voltages; + host->cfg.f_min = host->clock_min; + host->cfg.f_max = host->clock_max; + if (host->b_max != 0) + host->cfg.b_max = host->b_max; + else + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create(&host->cfg, host); + if (mmc == NULL) + return -1; + + debug("registered mmc interface number is:%d\n", mmc->block_dev.dev); return 0; } diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h index 72344498d6..f23bd391ee 100644 --- a/drivers/mmc/arm_pl180_mmci.h +++ b/drivers/mmc/arm_pl180_mmci.h @@ -13,6 +13,9 @@ #ifndef __ARM_PL180_MMCI_H__ #define __ARM_PL180_MMCI_H__ +/* need definition of struct mmc_config */ +#include + #define COMMAND_REG_DELAY 300 #define DATA_REG_DELAY 1000 #define CLK_CHANGE_DELAY 2000 @@ -184,6 +187,7 @@ struct pl180_mmc_host { unsigned int clkdiv_init; unsigned int pwr_init; int version2; + struct mmc_config cfg; }; int arm_pl180_mmci_init(struct pl180_mmc_host *); diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 54cfabfb91..92f7d8942f 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -40,6 +40,7 @@ #include #include #include +#include /* 400KHz is max freq for card ID etc. Use that as min */ #define MIN_FREQ 400000 @@ -179,7 +180,7 @@ int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq) host->name = "bcm2835_sdhci"; host->ioaddr = (void *)regbase; host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | - SDHCI_QUIRK_WAIT_SEND_CMD; + SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; host->ops = &bcm2835_ops; diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 26311741f5..9bdfbbca01 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -137,9 +138,9 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) if (data->flags & MMC_DATA_WRITE) return UNUSABLE_ERR; #ifndef RSI_BLKSZ - data_ctl |= ((ffs(data_size) - 1) << 4); + data_ctl |= ((ffs(data->blocksize) - 1) << 4); #else - bfin_write_SDH_BLK_SIZE(data_size); + bfin_write_SDH_BLK_SIZE(data->blocksize); #endif data_ctl |= DTX_DIR; bfin_write_SDH_DATA_CTL(data_ctl); @@ -188,7 +189,8 @@ static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, do { udelay(1); status = bfin_read_SDH_STATUS(); - } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN))); + } while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | + RX_OVERRUN))); if (status & DAT_TIME_OUT) { bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT); @@ -273,30 +275,30 @@ static int bfin_sdh_init(struct mmc *mmc) return 0; } +static const struct mmc_ops bfin_mmc_ops = { + .send_cmd = bfin_sdh_request, + .set_ios = bfin_sdh_set_ios, + .init = bfin_sdh_init, +}; + +static struct mmc_config bfin_mmc_cfg = { + .name = "Blackfin SDH", + .ops = &bfin_mmc_ops, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; int bfin_mmc_init(bd_t *bis) { - struct mmc *mmc = NULL; - - mmc = malloc(sizeof(struct mmc)); - - if (!mmc) - return -ENOMEM; - sprintf(mmc->name, "Blackfin SDH"); - mmc->send_cmd = bfin_sdh_request; - mmc->set_ios = bfin_sdh_set_ios; - mmc->init = bfin_sdh_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_4BIT; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = get_sclk(); - mmc->f_min = mmc->f_max >> 9; + struct mmc *mmc; - mmc->b_max = 0; + bfin_mmc_cfg.f_max = get_sclk(); + bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9; - mmc_register(mmc); + mmc = mmc_create(&bfin_mmc_cfg, NULL); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index b380961188..aae00e9dab 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -30,10 +30,10 @@ static void dmmc_set_clock(struct mmc *mmc, uint clock) struct davinci_mmc_regs *regs = host->reg_base; uint clkrt, sysclk2, act_clock; - if (clock < mmc->f_min) - clock = mmc->f_min; - if (clock > mmc->f_max) - clock = mmc->f_max; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; + if (clock > mmc->cfg->f_max) + clock = mmc->cfg->f_max; set_val(®s->mmcclk, 0); sysclk2 = host->input_clk; @@ -363,32 +363,27 @@ static void dmmc_set_ios(struct mmc *mmc) dmmc_set_clock(mmc, mmc->clock); } +static const struct mmc_ops dmmc_ops = { + .send_cmd = dmmc_send_cmd, + .set_ios = dmmc_set_ios, + .init = dmmc_init, +}; + /* Called from board_mmc_init during startup. Can be called multiple times * depending on the number of slots available on board and controller */ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) { - struct mmc *mmc; - - mmc = malloc(sizeof(struct mmc)); - memset(mmc, 0, sizeof(struct mmc)); - - sprintf(mmc->name, "davinci"); - mmc->priv = host; - mmc->send_cmd = dmmc_send_cmd; - mmc->set_ios = dmmc_set_ios; - mmc->init = dmmc_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - - mmc->f_min = 200000; - mmc->f_max = 25000000; - mmc->voltages = host->voltages; - mmc->host_caps = host->host_caps; + host->cfg.name = "davinci"; + host->cfg.ops = &dmmc_ops; + host->cfg.f_min = 200000; + host->cfg.f_max = 25000000; + host->cfg.voltages = host->voltages; + host->cfg.host_caps = host->host_caps; - mmc->b_max = DAVINCI_MAX_BLOCKS; + host->cfg.b_max = DAVINCI_MAX_BLOCKS; - mmc_register(mmc); + mmc_create(&host->cfg, host); return 0; } diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index a82ee17a25..b18c75dee2 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -41,12 +42,13 @@ static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, } static void dwmci_prepare_data(struct dwmci_host *host, - struct mmc_data *data) + struct mmc_data *data, + struct dwmci_idmac *cur_idmac, + void *bounce_buffer) { unsigned long ctrl; unsigned int i = 0, flags, cnt, blk_cnt; - ulong data_start, data_end, start_addr; - ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data->blocks); + ulong data_start, data_end; blk_cnt = data->blocks; @@ -56,11 +58,6 @@ static void dwmci_prepare_data(struct dwmci_host *host, data_start = (ulong)cur_idmac; dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); - if (data->flags == MMC_DATA_READ) - start_addr = (unsigned int)data->dest; - else - start_addr = (unsigned int)data->src; - do { flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; @@ -71,9 +68,9 @@ static void dwmci_prepare_data(struct dwmci_host *host, cnt = data->blocksize * 8; dwmci_set_idma_desc(cur_idmac, flags, cnt, - start_addr + (i * PAGE_SIZE)); + (u32)bounce_buffer + (i * PAGE_SIZE)); - if(blk_cnt < 8) + if (blk_cnt <= 8) break; blk_cnt -= 8; cur_idmac++; @@ -110,24 +107,38 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host, static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + struct dwmci_host *host = mmc->priv; + ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, + data ? DIV_ROUND_UP(data->blocks, 8) : 0); int flags = 0, i; unsigned int timeout = 100000; u32 retry = 10000; u32 mask, ctrl; ulong start = get_timer(0); + struct bounce_buffer bbstate; while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { if (get_timer(start) > timeout) { - printf("Timeout on data busy\n"); + printf("%s: Timeout on data busy\n", __func__); return TIMEOUT; } } dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); - if (data) - dwmci_prepare_data(host, data); + if (data) { + if (data->flags == MMC_DATA_READ) { + bounce_buffer_start(&bbstate, (void*)data->dest, + data->blocksize * + data->blocks, GEN_BB_WRITE); + } else { + bounce_buffer_start(&bbstate, (void*)data->src, + data->blocksize * + data->blocks, GEN_BB_READ); + } + dwmci_prepare_data(host, data, cur_idmac, + bbstate.bounce_buffer); + } dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); @@ -166,14 +177,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } } - if (i == retry) + if (i == retry) { + printf("%s: Timeout.\n", __func__); return TIMEOUT; + } if (mask & DWMCI_INTMSK_RTO) { - debug("Response Timeout..\n"); + /* + * Timeout here is not necessarily fatal. (e)MMC cards + * will splat here when they receive CMD55 as they do + * not support this command and that is exactly the way + * to tell them apart from SD cards. Thus, this output + * below shall be debug(). eMMC cards also do not favor + * CMD8, please keep that in mind. + */ + debug("%s: Response Timeout.\n", __func__); return TIMEOUT; } else if (mask & DWMCI_INTMSK_RE) { - debug("Response Error..\n"); + printf("%s: Response Error.\n", __func__); return -1; } @@ -193,7 +214,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, do { mask = dwmci_readl(host, DWMCI_RINTSTS); if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { - debug("DATA ERROR!\n"); + printf("%s: DATA ERROR!\n", __func__); return -1; } } while (!(mask & DWMCI_INTMSK_DTO)); @@ -203,6 +224,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl &= ~(DWMCI_DMA_EN); dwmci_writel(host, DWMCI_CTRL, ctrl); + + bounce_buffer_stop(&bbstate); } udelay(100); @@ -219,20 +242,23 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) if ((freq == host->clock) || (freq == 0)) return 0; /* - * If host->mmc_clk didn't define, + * If host->get_mmc_clk isn't defined, * then assume that host->bus_hz is source clock value. - * host->bus_hz should be set from user. + * host->bus_hz should be set by user. */ - if (host->mmc_clk) - sclk = host->mmc_clk(host->dev_index); + if (host->get_mmc_clk) + sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { - printf("Didn't get source clock value..\n"); + printf("%s: Didn't get source clock value.\n", __func__); return -EINVAL; } - div = DIV_ROUND_UP(sclk, 2 * freq); + if (sclk == freq) + div = 0; /* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); @@ -244,7 +270,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + printf("%s: Timeout!\n", __func__); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -259,7 +285,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + printf("%s: Timeout!\n", __func__); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -272,9 +298,9 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) static void dwmci_set_ios(struct mmc *mmc) { struct dwmci_host *host = (struct dwmci_host *)mmc->priv; - u32 ctype; + u32 ctype, regs; - debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); + debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); dwmci_setup_bus(host, mmc->clock); switch (mmc->bus_width) { @@ -291,24 +317,34 @@ static void dwmci_set_ios(struct mmc *mmc) dwmci_writel(host, DWMCI_CTYPE, ctype); + regs = dwmci_readl(host, DWMCI_UHS_REG); + if (mmc->ddr_mode) + regs |= DWMCI_DDR_MODE; + else + regs &= DWMCI_DDR_MODE; + + dwmci_writel(host, DWMCI_UHS_REG, regs); + if (host->clksel) host->clksel(host); } static int dwmci_init(struct mmc *mmc) { - struct dwmci_host *host = (struct dwmci_host *)mmc->priv; - u32 fifo_size; + struct dwmci_host *host = mmc->priv; + + if (host->board_init) + host->board_init(host); dwmci_writel(host, DWMCI_PWREN, 1); if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { - debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); + printf("%s[%d] Fail-reset!!\n", __func__, __LINE__); return -1; } /* Enumerate at 400KHz */ - dwmci_setup_bus(host, mmc->f_min); + dwmci_setup_bus(host, mmc->cfg->f_min); dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); dwmci_writel(host, DWMCI_INTMASK, 0); @@ -318,13 +354,9 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_IDINTEN, 0); dwmci_writel(host, DWMCI_BMOD, 1); - if (!host->fifoth_val) { - fifo_size = dwmci_readl(host, DWMCI_FIFOTH); - fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; - host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | - TX_WMARK(fifo_size / 2); + if (host->fifoth_val) { + dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); } - dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); @@ -332,41 +364,37 @@ static int dwmci_init(struct mmc *mmc) return 0; } +static const struct mmc_ops dwmci_ops = { + .send_cmd = dwmci_send_cmd, + .set_ios = dwmci_set_ios, + .init = dwmci_init, +}; + int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) { - struct mmc *mmc; - int err = 0; + host->cfg.name = host->name; + host->cfg.ops = &dwmci_ops; + host->cfg.f_min = min_clk; + host->cfg.f_max = max_clk; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) { - printf("mmc malloc fail!\n"); - return -1; - } + host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->priv = host; - host->mmc = mmc; - - sprintf(mmc->name, "%s", host->name); - mmc->send_cmd = dwmci_send_cmd; - mmc->set_ios = dwmci_set_ios; - mmc->init = dwmci_init; - mmc->f_min = min_clk; - mmc->f_max = max_clk; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - - mmc->host_caps = host->caps; + host->cfg.host_caps = host->caps; if (host->buswidth == 8) { - mmc->host_caps |= MMC_MODE_8BIT; - mmc->host_caps &= ~MMC_MODE_4BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps &= ~MMC_MODE_4BIT; } else { - mmc->host_caps |= MMC_MODE_4BIT; - mmc->host_caps &= ~MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_4BIT; + host->cfg.host_caps &= ~MMC_MODE_8BIT; } - mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; + host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; - err = mmc_register(mmc); + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - return err; + host->mmc = mmc_create(&host->cfg, host); + if (host->mmc == NULL) + return -1; + + return 0; } diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 4ef9fec0e4..dfa209bded 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #define DWMMC_MAX_CH_NUM 4 #define DWMMC_MAX_FREQ 52000000 @@ -29,123 +31,212 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); } -unsigned int exynos_dwmci_get_clk(int dev_index) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) { - return get_mmc_clk(dev_index); + unsigned long sclk; + int8_t clk_div; + + /* + * Since SDCLKIN is divided inside controller by the DIVRATIO + * value set in the CLKSEL register, we need to use the same output + * clock value to calculate the CLKDIV value. + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) + */ + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; + sclk = get_mmc_clk(host->dev_index); + + /* + * Assume to know divider value. + * When clock unit is broken, need to set "host->div" + */ + return sclk / clk_div / (host->div + 1); } -/* - * This function adds the mmc channel to be registered with mmc core. - * index - mmc channel number. - * regbase - register base address of mmc channel specified in 'index'. - * bus_width - operating bus width of mmc channel specified in 'index'. - * clksel - value to be written into CLKSEL register in case of FDT. - * NULL in case od non-FDT. - */ -int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) +static void exynos_dwmci_board_init(struct dwmci_host *host) +{ + if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { + dwmci_writel(host, EMMCP_MPSBEGIN0, 0); + dwmci_writel(host, EMMCP_SEND0, 0); + dwmci_writel(host, EMMCP_CTRL0, + MPSCTRL_SECURE_READ_BIT | + MPSCTRL_SECURE_WRITE_BIT | + MPSCTRL_NON_SECURE_READ_BIT | + MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); + } +} + +static int exynos_dwmci_core_init(struct dwmci_host *host, int index) { - struct dwmci_host *host = NULL; unsigned int div; unsigned long freq, sclk; - host = malloc(sizeof(struct dwmci_host)); - if (!host) { - printf("dwmci_host malloc fail!\n"); - return 1; - } + + if (host->bus_hz) + freq = host->bus_hz; + else + freq = DWMMC_MAX_FREQ; + /* request mmc clock vlaue of 52MHz. */ - freq = 52000000; sclk = get_mmc_clk(index); div = DIV_ROUND_UP(sclk, freq); /* set the clock divisor for mmc */ set_mmc_clk(index, div); host->name = "EXYNOS DWMMC"; - host->ioaddr = (void *)regbase; - host->buswidth = bus_width; +#ifdef CONFIG_EXYNOS5420 + host->quirks = DWMCI_QUIRK_DISABLE_SMU; +#endif + host->board_init = exynos_dwmci_board_init; - if (clksel) { - host->clksel_val = clksel; - } else { - if (0 == index) + if (!host->clksel_val) { + if (index == 0) host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; - if (2 == index) + else if (index == 2) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } + host->caps = MMC_MODE_DDR_52MHz; host->clksel = exynos_dwmci_clksel; host->dev_index = index; - host->mmc_clk = exynos_dwmci_get_clk; + host->get_mmc_clk = exynos_dwmci_get_clk; /* Add the mmc channel to be registered with mmc core */ if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { - debug("dwmmc%d registration failed\n", index); + printf("DWMMC%d registration failed\n", index); return -1; } return 0; } +/* + * This function adds the mmc channel to be registered with mmc core. + * index - mmc channel number. + * regbase - register base address of mmc channel specified in 'index'. + * bus_width - operating bus width of mmc channel specified in 'index'. + * clksel - value to be written into CLKSEL register in case of FDT. + * NULL in case od non-FDT. + */ +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + error("dwmci_host malloc fail!\n"); + return -ENOMEM; + } + + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + + if (clksel) + host->clksel_val = clksel; + + return exynos_dwmci_core_init(host, index); +} + #ifdef CONFIG_OF_CONTROL -int exynos_dwmmc_init(const void *blob) +static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; + +static int do_dwmci_init(struct dwmci_host *host) { - int index, bus_width; - int node_list[DWMMC_MAX_CH_NUM]; - int err = 0, dev_id, flag, count, i; - u32 clksel_val, base, timing[3]; + int index, flag, err; - count = fdtdec_find_aliases_for_id(blob, "mmc", - COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list, - DWMMC_MAX_CH_NUM); + index = host->dev_index; - for (i = 0; i < count; i++) { - int node = node_list[i]; + flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + err = exynos_pinmux_config(host->dev_id, flag); + if (err) { + printf("DWMMC%d not configure\n", index); + return err; + } - if (node <= 0) - continue; + return exynos_dwmci_core_init(host, index); +} - /* Extract device id for each mmc channel */ - dev_id = pinmux_decode_periph_id(blob, node); +static int exynos_dwmci_get_config(const void *blob, int node, + struct dwmci_host *host) +{ + int err = 0; + u32 base, clksel_val, timing[3]; - /* Get the bus width from the device node */ - bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); - if (bus_width <= 0) { - debug("DWMMC: Can't get bus-width\n"); - return -1; - } - if (8 == bus_width) - flag = PINMUX_FLAG_8BIT_MODE; - else - flag = PINMUX_FLAG_NONE; + /* Extract device id for each mmc channel */ + host->dev_id = pinmux_decode_periph_id(blob, node); - /* config pinmux for each mmc channel */ - err = exynos_pinmux_config(dev_id, flag); - if (err) { - debug("DWMMC not configured\n"); - return err; - } + host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); + if (host->dev_index == host->dev_id) + host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; - index = dev_id - PERIPH_ID_SDMMC0; - /* Get the base address from the device node */ - base = fdtdec_get_addr(blob, node, "reg"); - if (!base) { - debug("DWMMC: Can't get base address\n"); - return -1; - } - /* Extract the timing info from the node */ - err = fdtdec_get_int_array(blob, node, "samsung,timing", - timing, 3); + /* Get the bus width from the device node */ + host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (host->buswidth <= 0) { + printf("DWMMC%d: Can't get bus-width\n", host->dev_index); + return -EINVAL; + } + + /* Set the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + printf("DWMMC%d: Can't get base address\n", host->dev_index); + return -EINVAL; + } + host->ioaddr = (void *)base; + + /* Extract the timing info from the node */ + err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); + if (err) { + printf("DWMMC%d: Can't get sdr-timings for devider\n", + host->dev_index); + return -EINVAL; + } + + clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(timing[2])); + if (clksel_val) + host->clksel_val = clksel_val; + + host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); + host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); + host->div = fdtdec_get_int(blob, node, "div", 0); + + return 0; +} + +static int exynos_dwmci_process_node(const void *blob, + int node_list[], int count) +{ + struct dwmci_host *host; + int i, node, err; + + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) + continue; + host = &dwmci_host[i]; + err = exynos_dwmci_get_config(blob, node, host); if (err) { - debug("Can't get sdr-timings for divider\n"); - return -1; + printf("%s: failed to decode dev %d\n", __func__, i); + return err; } - clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | - DWMCI_SET_DRV_CLK(timing[1]) | - DWMCI_SET_DIV_RATIO(timing[2])); - /* Initialise each mmc channel */ - err = exynos_dwmci_add_port(index, base, bus_width, clksel_val); - if (err) - debug("dwmmc Channel-%d init failed\n", index); + do_dwmci_init(host); } return 0; } + +int exynos_dwmmc_init(const void *blob) +{ + int compat_id; + int node_list[DWMMC_MAX_CH_NUM]; + int err = 0, count; + + compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + compat_id, node_list, DWMMC_MAX_CH_NUM); + err = exynos_dwmci_process_node(blob, node_list, count); + + return err; +} #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 36ec912869..4b11e9da29 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -23,32 +23,51 @@ DECLARE_GLOBAL_DATA_PTR; +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ + IRQSTATEN_CINT | \ + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ + IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ + IRQSTATEN_DINT) + struct fsl_esdhc { - uint dsaddr; - uint blkattr; - uint cmdarg; - uint xfertyp; - uint cmdrsp0; - uint cmdrsp1; - uint cmdrsp2; - uint cmdrsp3; - uint datport; - uint prsstat; - uint proctl; - uint sysctl; - uint irqstat; - uint irqstaten; - uint irqsigen; - uint autoc12err; - uint hostcapblt; - uint wml; - uint mixctrl; - char reserved1[4]; - uint fevt; - char reserved2[168]; - uint hostver; - char reserved3[780]; - uint scr; + uint dsaddr; /* SDMA system address register */ + uint blkattr; /* Block attributes register */ + uint cmdarg; /* Command argument register */ + uint xfertyp; /* Transfer type register */ + uint cmdrsp0; /* Command response 0 register */ + uint cmdrsp1; /* Command response 1 register */ + uint cmdrsp2; /* Command response 2 register */ + uint cmdrsp3; /* Command response 3 register */ + uint datport; /* Buffer data port register */ + uint prsstat; /* Present state register */ + uint proctl; /* Protocol control register */ + uint sysctl; /* System Control Register */ + uint irqstat; /* Interrupt status register */ + uint irqstaten; /* Interrupt status enable register */ + uint irqsigen; /* Interrupt signal enable register */ + uint autoc12err; /* Auto CMD error status register */ + uint hostcapblt; /* Host controller capabilities register */ + uint wml; /* Watermark level register */ + uint mixctrl; /* For USDHC */ + char reserved1[4]; /* reserved */ + uint fevt; /* Force event register */ + uint admaes; /* ADMA error status register */ + uint adsaddr; /* ADMA system address register */ + char reserved2[160]; /* reserved */ + uint hostver; /* Host controller version register */ + char reserved3[4]; /* reserved */ + uint dmaerraddr; /* DMA error address register */ + char reserved4[4]; /* reserved */ + uint dmaerrattr; /* DMA error attribute register */ + char reserved5[4]; /* reserved */ + uint hostcapblt2; /* Host controller capabilities register 2 */ + char reserved6[8]; /* reserved */ + uint tcr; /* Tuning control register */ + char reserved7[28]; /* reserved */ + uint sddirctl; /* SD direction control register */ + char reserved8[712]; /* reserved */ + uint scr; /* eSDHC control register */ }; /* Return the XFERTYP flags for a given command and data packet */ @@ -84,7 +103,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) +#if defined(CONFIG_SOC_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_SOC_LS102XA) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif @@ -174,7 +193,6 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) int timeout; struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = cfg->esdhc_base; -#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO uint wml_value; wml_value = data->blocksize / 4; @@ -184,8 +202,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value = WML_RD_WML_MAX_VAL; esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_write32(®s->dsaddr, (u32)data->dest); +#endif } else { +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO + flush_dcache_range((ulong)data->src, + (ulong)data->src+data->blocks + *data->blocksize); +#endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { @@ -197,19 +222,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) (unsigned long)data->src + data->blocks * data->blocksize); esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, wml_value << 16); +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_write32(®s->dsaddr, (u32)data->src); +#endif } -#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ - if (!(data->flags & MMC_DATA_READ)) { - if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { - printf("The SD card is locked. Can not write to a locked card.\n"); - return UNUSABLE_ERR; - } - esdhc_write32(®s->dsaddr, (u32)data->src); - } else { - esdhc_write32(®s->dsaddr, (u32)data->dest); - } -#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ esdhc_write32(®s->blkattr, (data->blocks << 16) | data->blocksize); @@ -219,16 +235,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) * 2)Timeout period should be minimum 0.250sec as per SD Card spec * So, Number of SD Clock cycles for 0.25sec should be minimum * (SD Clock/sec * 0.25 sec) SD Clock cycles - * = (mmc->tran_speed * 1/4) SD Clock cycles + * = (mmc->clock * 1/4) SD Clock cycles * As 1) >= 2) - * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 + * => (2^(timeout+13)) >= mmc->clock * 1/4 * Taking log2 both the sides - * => timeout + 13 >= log2(mmc->tran_speed/4) + * => timeout + 13 >= log2(mmc->clock/4) * Rounding up to next power of 2 - * => timeout + 13 = log2(mmc->tran_speed/4) + 1 - * => timeout + 13 = fls(mmc->tran_speed/4) + * => timeout + 13 = log2(mmc->clock/4) + 1 + * => timeout + 13 = fls(mmc->clock/4) */ - timeout = fls(mmc->tran_speed / 4); + timeout = fls(mmc->clock/4); timeout -= 13; if (timeout > 14) @@ -240,22 +256,26 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) if ((timeout == 4) || (timeout == 8) || (timeout == 12)) timeout++; #endif + +#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE + timeout = 0xE; +#endif esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); return 0; } -static inline void check_and_invalidate_dcache_range(struct mmc_cmd *cmd, - struct mmc_data *data) -{ - unsigned long start = (unsigned long)data->dest; - size_t start_ofs = start & (ARCH_DMA_MINALIGN - 1); - unsigned long size = data->blocks * data->blocksize; - unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); - - start -= start_ofs; +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO +static void check_and_invalidate_dcache_range + (struct mmc_cmd *cmd, + struct mmc_data *data) { + unsigned start = (unsigned)data->dest ; + unsigned size = roundup(ARCH_DMA_MINALIGN, + data->blocks*data->blocksize); + unsigned end = start+size ; invalidate_dcache_range(start, end); } +#endif /* * Sends a command out on the bus. Takes the mmc pointer, @@ -264,6 +284,7 @@ static inline void check_and_invalidate_dcache_range(struct mmc_cmd *cmd, static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { + int err = 0; uint xfertyp; uint irqstat; struct fsl_esdhc_cfg *cfg = mmc->priv; @@ -303,8 +324,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Set up for a data transfer if we have one */ if (data) { - int err; - err = esdhc_setup_data(mmc, data); if (err) return err; @@ -343,33 +362,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) irqstat = esdhc_read32(®s->irqstat); - /* Reset CMD and DATA portions on error */ - if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { - esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | - SYSCTL_RSTC); - start = get_timer_masked(); - while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) { - if (get_timer(start) > CONFIG_SYS_HZ) - return TIMEOUT; - } - - if (data) { - esdhc_write32(®s->sysctl, - esdhc_read32(®s->sysctl) | - SYSCTL_RSTD); - start = get_timer_masked(); - while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) { - if (get_timer(start) > CONFIG_SYS_HZ) - return TIMEOUT; - } - } + if (irqstat & CMD_ERR) { + err = COMM_ERR; + goto out; } - if (irqstat & CMD_ERR) - return COMM_ERR; - - if (irqstat & IRQSTAT_CTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_CTOE) { + err = TIMEOUT; + goto out; + } /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { @@ -384,7 +385,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (timeout <= 0) { printf("Timeout waiting for DAT0 to go high!\n"); - return TIMEOUT; + err = TIMEOUT; + goto out; } } @@ -408,42 +410,45 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_pio_read_write(mmc, data); #else - unsigned long start = get_timer_masked(); - unsigned long data_timeout = data->blocks * - data->blocksize * 100 / mmc->bus_width / - (mmc->tran_speed / CONFIG_SYS_HZ) + CONFIG_SYS_HZ; - do { irqstat = esdhc_read32(®s->irqstat); if (irqstat & IRQSTAT_DTOE) { - printf("MMC/SD data %s timeout\n", - data->flags & MMC_DATA_READ ? - "read" : "write"); - return TIMEOUT; + err = TIMEOUT; + goto out; } if (irqstat & DATA_ERR) { - printf("MMC/SD data error\n"); - return COMM_ERR; - } - - if (get_timer(start) > data_timeout) { - printf("MMC/SD timeout waiting for %s xfer completion\n", - data->flags & MMC_DATA_READ ? - "read" : "write"); - return TIMEOUT; + err = COMM_ERR; + goto out; } - } while (!(irqstat & IRQSTAT_TC) && - (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); + } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); - check_and_invalidate_dcache_range(cmd, data); + if (data->flags & MMC_DATA_READ) + check_and_invalidate_dcache_range(cmd, data); #endif } +out: + /* Reset CMD and DATA portions on error */ + if (err) { + esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | + SYSCTL_RSTC); + while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) + ; + + if (data) { + esdhc_write32(®s->sysctl, + esdhc_read32(®s->sysctl) | + SYSCTL_RSTD); + while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) + ; + } + } + esdhc_write32(®s->irqstat, irqstat); - return 0; + return err; } static void set_sysctl(struct mmc *mmc, uint clock) @@ -454,8 +459,8 @@ static void set_sysctl(struct mmc *mmc, uint clock) int sdhc_clk = cfg->sdhc_clk; uint clk; - if (clock < mmc->f_min) - clock = mmc->f_min; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; if (sdhc_clk / 16 > clock) { for (pre_div = 2; pre_div < 256; pre_div *= 2) @@ -543,6 +548,10 @@ static int esdhc_getcd(struct mmc *mmc) struct fsl_esdhc *regs = cfg->esdhc_base; int timeout = 1000; +#ifdef CONFIG_ESDHC_DETECT_QUIRK + if (CONFIG_ESDHC_DETECT_QUIRK) + return 1; +#endif while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000); @@ -563,6 +572,13 @@ static void esdhc_reset(struct fsl_esdhc *regs) printf("MMC/SD: Reset never completed.\n"); } +static const struct mmc_ops esdhc_ops = { + .send_cmd = esdhc_send_cmd, + .set_ios = esdhc_set_ios, + .init = esdhc_init, + .getcd = esdhc_getcd, +}; + int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) { struct fsl_esdhc *regs; @@ -572,12 +588,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (!cfg) return -EINVAL; - mmc = kzalloc(sizeof(struct mmc), GFP_KERNEL); - if (!mmc) - return -ENOMEM; - - sprintf(mmc->name, "FSL_SDHC"); - regs = cfg->esdhc_base; + regs = (struct fsl_esdhc *)cfg->esdhc_base; /* First reset the eSDHC controller */ esdhc_reset(regs); @@ -585,20 +596,22 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); - mmc->priv = cfg; - mmc->send_cmd = esdhc_send_cmd; - mmc->set_ios = esdhc_set_ios; - mmc->init = esdhc_init; - mmc->getcd = esdhc_getcd; - mmc->getwp = NULL; + writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); + memset(&cfg->cfg, 0, sizeof(cfg->cfg)); voltage_caps = 0; - caps = regs->hostcapblt; + caps = esdhc_read32(®s->hostcapblt); #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); #endif + +/* T4240 host controller capabilities register should have VS33 bit */ +#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 + caps = caps | ESDHC_HOSTCAPBLT_VS33; +#endif + if (caps & ESDHC_HOSTCAPBLT_VS18) voltage_caps |= MMC_VDD_165_195; if (caps & ESDHC_HOSTCAPBLT_VS30) @@ -606,33 +619,43 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (caps & ESDHC_HOSTCAPBLT_VS33) voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->cfg.name = "FSL_SDHC"; + cfg->cfg.ops = &esdhc_ops; #ifdef CONFIG_SYS_SD_VOLTAGE - mmc->voltages = CONFIG_SYS_SD_VOLTAGE; + cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; #else - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; #endif - if ((mmc->voltages & voltage_caps) == 0) { + if ((cfg->cfg.voltages & voltage_caps) == 0) { printf("voltage not supported by controller\n"); return -EINVAL; } - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; + cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; if (cfg->max_bus_width > 0) { if (cfg->max_bus_width < 8) - mmc->host_caps &= ~MMC_MODE_8BIT; + cfg->cfg.host_caps &= ~MMC_MODE_8BIT; if (cfg->max_bus_width < 4) - mmc->host_caps &= ~MMC_MODE_4BIT; + cfg->cfg.host_caps &= ~MMC_MODE_4BIT; } if (caps & ESDHC_HOSTCAPBLT_HSS) - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + +#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK + if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) + cfg->cfg.host_caps &= ~MMC_MODE_8BIT; +#endif + + cfg->cfg.f_min = 400000; + cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); - mmc->f_min = 400000; - mmc->f_max = MIN(cfg->sdhc_clk, 52000000); + cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc->b_max = 0; - mmc_register(mmc); + mmc = mmc_create(&cfg->cfg, cfg); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c new file mode 100644 index 0000000000..b1cb4b3534 --- /dev/null +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -0,0 +1,150 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * The environment variables are written to just after the u-boot image + * on SDCard, so we must read the MBR to get the start address and code + * length of the u-boot image, then calculate the address of the env. + */ +#define ESDHC_BOOT_IMAGE_SIZE 0x48 +#define ESDHC_BOOT_IMAGE_ADDR 0x50 +#define MBRDBR_BOOT_SIG_55 0x1fe +#define MBRDBR_BOOT_SIG_AA 0x1ff +#define CONFIG_CFG_DATA_SECTOR 0 + + +void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst) +{ + uint blk_start, blk_cnt, err; + + struct mmc *mmc = find_mmc_device(0); + if (!mmc) { + puts("spl: mmc device not found!!\n"); + hang(); + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return; + } + + blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + + err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst); + if (err != blk_cnt) { + puts("spl: mmc read failed!!\n"); + hang(); + } +} + +/* + * The main entry for mmc booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from mmc into SDRAM and starts it from there. + */ + +void __noreturn mmc_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + uint blk_start, blk_cnt, err; +#ifndef CONFIG_FSL_CORENET + uchar *tmp_buf; + u32 blklen; + uchar val; + uint i, byte_num; +#endif + u32 offset, code_len; + struct mmc *mmc; + + mmc = find_mmc_device(0); + if (!mmc) { + puts("spl: mmc device not found!!\n"); + hang(); + } + +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_MMC_U_BOOT_OFFS; + code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; +#else + blklen = mmc->read_bl_len; + tmp_buf = malloc(blklen); + if (!tmp_buf) { + puts("spl: malloc memory failed!!\n"); + hang(); + } + memset(tmp_buf, 0, blklen); + + /* + * Read source addr from sd card + */ + err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); + if (err != 1) { + puts("spl: mmc read failed!!\n"); + free(tmp_buf); + hang(); + } + + val = *(tmp_buf + MBRDBR_BOOT_SIG_55); + if (0x55 != val) { + puts("spl: mmc signature is not valid!!\n"); + free(tmp_buf); + hang(); + } + val = *(tmp_buf + MBRDBR_BOOT_SIG_AA); + if (0xAA != val) { + puts("spl: mmc signature is not valid!!\n"); + free(tmp_buf); + hang(); + } + + byte_num = 4; + offset = 0; + for (i = 0; i < byte_num; i++) { + val = *(tmp_buf + ESDHC_BOOT_IMAGE_ADDR + i); + offset = (offset << 8) + val; + } + offset += CONFIG_SYS_MMC_U_BOOT_OFFS; + /* Get the code size from offset 0x48 */ + byte_num = 4; + code_len = 0; + for (i = 0; i < byte_num; i++) { + val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i); + code_len = (code_len << 8) + val; + } + code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS; + /* + * Load U-Boot image from mmc into RAM + */ +#endif + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; + err = mmc->block_dev.block_read(0, blk_start, blk_cnt, + (uchar *)CONFIG_SYS_MMC_U_BOOT_DST); + if (err != blk_cnt) { + puts("spl: mmc read failed!!\n"); +#ifndef CONFIG_FSL_CORENET + free(tmp_buf); +#endif + hang(); + } + + /* + * Clean d-cache and invalidate i-cache, to + * make sure that no stale data is executed. + */ + flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE); + + /* + * Jump to U-Boot image + */ + uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START; + (*uboot)(); +} diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 7600d5ce55..a620678e5f 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -27,6 +27,7 @@ struct ftsdc010_chip { uint32_t sclk; /* FTSDC010 source clock in Hz */ uint32_t fifo; /* fifo depth in bytes */ uint32_t acmd; + struct mmc_config cfg; /* mmc configuration */ }; static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) @@ -123,14 +124,6 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) } } -static inline int ftsdc010_is_ro(struct mmc *mmc) -{ - struct ftsdc010_chip *chip = mmc->priv; - const uint8_t *csd = (const uint8_t *)mmc->csd; - - return chip->wprot || (csd[1] & 0x30); -} - static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) { int ret = TIMEOUT; @@ -316,6 +309,12 @@ static int ftsdc010_init(struct mmc *mmc) return 0; } +static const struct mmc_ops ftsdc010_ops = { + .send_cmd = ftsdc010_request, + .set_ios = ftsdc010_set_ios, + .init = ftsdc010_init, +}; + int ftsdc010_mmc_init(int devid) { struct mmc *mmc; @@ -331,50 +330,44 @@ int ftsdc010_mmc_init(int devid) regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20)); #endif - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - return -ENOMEM; - memset(mmc, 0, sizeof(struct mmc)); - chip = malloc(sizeof(struct ftsdc010_chip)); - if (!chip) { - free(mmc); + if (!chip) return -ENOMEM; - } memset(chip, 0, sizeof(struct ftsdc010_chip)); chip->regs = regs; - mmc->priv = chip; - - sprintf(mmc->name, "ftsdc010"); - mmc->send_cmd = ftsdc010_request; - mmc->set_ios = ftsdc010_set_ios; - mmc->init = ftsdc010_init; +#ifdef CONFIG_SYS_CLK_FREQ + chip->sclk = CONFIG_SYS_CLK_FREQ; +#else + chip->sclk = clk_get_rate("SDC"); +#endif - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; + chip->cfg.name = "ftsdc010"; + chip->cfg.ops = &ftsdc010_ops; + chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) { case FTSDC010_BWR_CAPS_4BIT: - mmc->host_caps |= MMC_MODE_4BIT; + chip->cfg.host_caps |= MMC_MODE_4BIT; break; case FTSDC010_BWR_CAPS_8BIT: - mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; + chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; break; default: break; } -#ifdef CONFIG_SYS_CLK_FREQ - chip->sclk = CONFIG_SYS_CLK_FREQ; -#else - chip->sclk = clk_get_rate("SDC"); -#endif + chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + chip->cfg.f_max = chip->sclk / 2; + chip->cfg.f_min = chip->sclk / 0x100; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = chip->sclk / 2; - mmc->f_min = chip->sclk / 0x100; - mmc->block_dev.part_type = PART_TYPE_DOS; + chip->cfg.part_type = PART_TYPE_DOS; + chip->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc_register(mmc); + mmc = mmc_create(&chip->cfg, chip); + if (mmc == NULL) { + free(chip); + return -ENOMEM; + } return 0; } diff --git a/drivers/mmc/ftsdc021_sdhci.c b/drivers/mmc/ftsdc021_sdhci.c new file mode 100644 index 0000000000..1f6cdba173 --- /dev/null +++ b/drivers/mmc/ftsdc021_sdhci.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2013 Faraday Technology + * Kuo-Jung Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#ifndef CONFIG_FTSDC021_CLOCK +#define CONFIG_FTSDC021_CLOCK clk_get_rate("MMC") +#endif + +int ftsdc021_sdhci_init(u32 regbase) +{ + struct sdhci_host *host = NULL; + uint32_t freq = CONFIG_FTSDC021_CLOCK; + + host = calloc(1, sizeof(struct sdhci_host)); + if (!host) { + puts("sdh_host malloc fail!\n"); + return 1; + } + + host->name = "FTSDC021"; + host->ioaddr = (void __iomem *)regbase; + host->quirks = 0; + add_sdhci(host, freq, 0); + + return 0; +} diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index c11dcd0f97..45bcffb6b2 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -55,33 +55,64 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) /* Setup for MCI Clock and Block Size */ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; u32 bus_hz = get_mci_clk_rate(); u32 clkdiv = 255; + unsigned int version = atmel_mci_get_version(mci); + u32 clkodd = 0; + u32 mr; debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n", bus_hz, hz, blklen); if (hz > 0) { - /* find lowest clkdiv yielding a rate <= than requested */ - for (clkdiv=0; clkdiv<255; clkdiv++) { - if ((bus_hz / (clkdiv+1) / 2) <= hz) - break; + if (version >= 0x500) { + clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2; + if (clkdiv > 511) + clkdiv = 511; + + clkodd = clkdiv & 1; + clkdiv >>= 1; + + printf("mci: setting clock %u Hz, block size %u\n", + bus_hz / (clkdiv * 2 + clkodd + 2), blklen); + } else { + /* find clkdiv yielding a rate <= than requested */ + for (clkdiv = 0; clkdiv < 255; clkdiv++) { + if ((bus_hz / (clkdiv + 1) / 2) <= hz) + break; + } + printf("mci: setting clock %u Hz, block size %u\n", + (bus_hz / (clkdiv + 1)) / 2, blklen); + } } - printf("mci: setting clock %u Hz, block size %u\n", - (bus_hz / (clkdiv+1)) / 2, blklen); blklen &= 0xfffc; - /* On some platforms RDPROOF and WRPROOF are ignored */ - writel((MMCI_BF(CLKDIV, clkdiv) - | MMCI_BF(BLKLEN, blklen) - | MMCI_BIT(RDPROOF) - | MMCI_BIT(WRPROOF)), &mci->mr); + + mr = MMCI_BF(CLKDIV, clkdiv); + + /* MCI IP version >= 0x200 has R/WPROOF */ + if (version >= 0x200) + mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF); + /* - * On some new platforms BLKLEN in mci->mr is ignored. - * Should use the BLKLEN in the block register. + * MCI IP version >= 0x500 use bit 16 as clkodd. + * MCI IP version < 0x500 use upper 16 bits for blklen. */ - writel(MMCI_BF(BLKLEN, blklen), &mci->blkr); + if (version >= 0x500) + mr |= MMCI_BF(CLKODD, clkodd); + else + mr |= MMCI_BF(BLKLEN, blklen); + + writel(mr, &mci->mr); + + /* MCI IP version >= 0x200 has blkr */ + if (version >= 0x200) + writel(MMCI_BF(BLKLEN, blklen), &mci->blkr); + + if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS) + writel(MMCI_BIT(HSMODE), &mci->cfg); + initialized = 1; } @@ -165,7 +196,7 @@ io_fail: static int mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; u32 cmdr; u32 error_flags = 0; u32 status; @@ -243,9 +274,10 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #ifdef DEBUG if (data->flags & MMC_DATA_READ) { + u32 cnt = word_count * 4; printf("Read Data:\n"); - print_buffer(0, data->dest, 1, - word_count*4, 0); + print_buffer(0, data->dest + cnt * block_count, + 1, cnt, 0); } #endif #ifdef DEBUG @@ -289,7 +321,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Entered into mmc structure during driver init */ static void mci_set_ios(struct mmc *mmc) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; int bus_width = mmc->bus_width; unsigned int version = atmel_mci_get_version(mci); int busw; @@ -325,7 +357,7 @@ static void mci_set_ios(struct mmc *mmc) /* Entered into mmc structure during driver init */ static int mci_init(struct mmc *mmc) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; /* Initialize controller */ writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ @@ -344,6 +376,12 @@ static int mci_init(struct mmc *mmc) return 0; } +static const struct mmc_ops atmel_mci_ops = { + .send_cmd = mci_send_cmd, + .set_ios = mci_set_ios, + .init = mci_init, +}; + /* * This is the only exported function * @@ -351,40 +389,47 @@ static int mci_init(struct mmc *mmc) */ int atmel_mci_init(void *regs) { - struct mmc *mmc = malloc(sizeof(struct mmc)); + struct mmc *mmc; + struct mmc_config *cfg; struct atmel_mci *mci; unsigned int version; - if (!mmc) + cfg = malloc(sizeof(*cfg)); + if (cfg == NULL) return -1; + memset(cfg, 0, sizeof(*cfg)); + + mci = (struct atmel_mci *)regs; - strcpy(mmc->name, "mci"); - mmc->priv = regs; - mmc->send_cmd = mci_send_cmd; - mmc->set_ios = mci_set_ios; - mmc->init = mci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; + cfg->name = "mci"; + cfg->ops = &atmel_mci_ops; /* need to be able to pass these in on a board by board basis */ - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mci = (struct atmel_mci *)mmc->priv; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; version = atmel_mci_get_version(mci); - if ((version & 0xf00) >= 0x300) - mmc->host_caps = MMC_MODE_8BIT; + if ((version & 0xf00) >= 0x300) { + cfg->host_caps = MMC_MODE_8BIT; + cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; + } - mmc->host_caps |= MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_4BIT; /* * min and max frequencies determined by * max and min of clock divider */ - mmc->f_min = get_mci_clk_rate() / (2*256); - mmc->f_max = get_mci_clk_rate() / (2*1); + cfg->f_min = get_mci_clk_rate() / (2*256); + cfg->f_max = get_mci_clk_rate() / (2*1); + + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc->b_max = 0; + mmc = mmc_create(cfg, regs); - mmc_register(mmc); + if (mmc == NULL) { + free(cfg); + return -1; + } + /* NOTE: possibly leaking the cfg structure */ return 0; } diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c new file mode 100644 index 0000000000..f804f4c0db --- /dev/null +++ b/drivers/mmc/kona_sdhci.c @@ -0,0 +1,138 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define SDHCI_CORECTRL_OFFSET 0x00008000 +#define SDHCI_CORECTRL_EN 0x01 +#define SDHCI_CORECTRL_RESET 0x02 + +#define SDHCI_CORESTAT_OFFSET 0x00008004 +#define SDHCI_CORESTAT_CD_SW 0x01 + +#define SDHCI_COREIMR_OFFSET 0x00008008 +#define SDHCI_COREIMR_IP 0x01 + +static int init_kona_mmc_core(struct sdhci_host *host) +{ + unsigned int mask; + unsigned int timeout; + + if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) { + printf("%s: sd host controller reset error\n", __func__); + return 1; + } + + /* For kona a hardware reset before anything else. */ + mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; + sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); + + /* Wait max 100 ms */ + timeout = 1000; + do { + if (timeout == 0) { + printf("%s: reset timeout error\n", __func__); + return 1; + } + timeout--; + udelay(100); + } while (0 == + (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) & + SDHCI_CORECTRL_RESET)); + + /* Clear the reset bit. */ + mask = mask & ~SDHCI_CORECTRL_RESET; + sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); + + /* Enable AHB clock */ + mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET); + sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET); + + /* Enable interrupts */ + sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET); + + /* Make sure Card is detected in controller */ + mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET); + sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET); + + /* Wait max 100 ms */ + timeout = 1000; + while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { + if (timeout == 0) { + printf("%s: CARD DETECT timeout error\n", __func__); + return 1; + } + timeout--; + udelay(100); + } + return 0; +} + +int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks) +{ + int ret = 0; + u32 max_clk; + void *reg_base; + struct sdhci_host *host = NULL; + + host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + if (!host) { + printf("%s: sdhci host malloc fail!\n", __func__); + return -ENOMEM; + } + switch (dev_index) { + case 0: + reg_base = (void *)CONFIG_SYS_SDIO_BASE0; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, + &max_clk); + break; + case 1: + reg_base = (void *)CONFIG_SYS_SDIO_BASE1; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, + &max_clk); + break; + case 2: + reg_base = (void *)CONFIG_SYS_SDIO_BASE2; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, + &max_clk); + break; + case 3: + reg_base = (void *)CONFIG_SYS_SDIO_BASE3; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, + &max_clk); + break; + default: + printf("%s: sdio dev index %d not supported\n", + __func__, dev_index); + ret = -EINVAL; + } + if (ret) { + free(host); + return ret; + } + + host->name = "kona-sdhci"; + host->ioaddr = reg_base; + host->quirks = quirks; + host->host_caps = MMC_MODE_HC; + + if (init_kona_mmc_core(host)) { + free(host); + return -EINVAL; + } + + if (quirks & SDHCI_QUIRK_REG32_RW) + host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; + else + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + + add_sdhci(host, max_clk, min_clk); + return ret; +} diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index cc998b2039..c0bab82714 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -10,21 +10,19 @@ #include #include #include +#include #include #include #include #include #include - -/* Set block count limit because of 16 bit register limit on some hardware*/ -#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 -#endif +#include "mmc_private.h" static struct list_head mmc_devices; static int cur_dev_num = -1; +static int mmc_dev_count; -int __weak board_mmc_getwp(struct mmc *mmc) +__weak int board_mmc_getwp(struct mmc *mmc) { return -1; } @@ -36,8 +34,8 @@ int mmc_getwp(struct mmc *mmc) wp = board_mmc_getwp(mmc); if (wp < 0) { - if (mmc->getwp) - wp = mmc->getwp(mmc); + if (mmc->cfg->ops->getwp) + wp = mmc->cfg->ops->getwp(mmc); else wp = 0; } @@ -45,28 +43,22 @@ int mmc_getwp(struct mmc *mmc) return wp; } -int __board_mmc_getcd(struct mmc *mmc) { +__weak int board_mmc_getcd(struct mmc *mmc) +{ return -1; } -int board_mmc_getcd(struct mmc *mmc)__attribute__((weak, - alias("__board_mmc_getcd"))); - -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) +int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct mmc_data backup; int ret; - memset(&backup, 0, sizeof(backup)); - #ifdef CONFIG_MMC_TRACE int i; u8 *ptr; printf("CMD_SEND:%d\n", cmd->cmdidx); printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); - ret = mmc->send_cmd(mmc, cmd, data); + ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); switch (cmd->resp_type) { case MMC_RSP_NONE: printf("\t\tMMC_RSP_NONE\n"); @@ -109,12 +101,12 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, break; } #else - ret = mmc->send_cmd(mmc, cmd, data); + ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); #endif return ret; } -static int mmc_send_status(struct mmc *mmc, int timeout) +int mmc_send_status(struct mmc *mmc, int timeout) { struct mmc_cmd cmd; int err, retries = 5; @@ -135,8 +127,10 @@ static int mmc_send_status(struct mmc *mmc, int timeout) MMC_STATE_PRG) break; else if (cmd.response[0] & MMC_STATUS_MASK) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("Status Error: 0x%08X\n", cmd.response[0]); +#endif return COMM_ERR; } } else if (--retries < 0) @@ -151,17 +145,24 @@ static int mmc_send_status(struct mmc *mmc, int timeout) printf("CURR STATE:%d\n", status); #endif if (timeout <= 0) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("Timeout waiting card ready\n"); +#endif return TIMEOUT; } + if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) + return SWITCH_ERR; return 0; } -static int mmc_set_blocklen(struct mmc *mmc, int len) +int mmc_set_blocklen(struct mmc *mmc, int len) { struct mmc_cmd cmd; + if (mmc->ddr_mode) + return 0; + cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; cmd.resp_type = MMC_RSP_R1; cmd.cmdarg = len; @@ -181,179 +182,13 @@ struct mmc *find_mmc_device(int dev_num) return m; } +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC Device %d not found\n", dev_num); +#endif return NULL; } -static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt) -{ - struct mmc_cmd cmd; - ulong end; - int err, start_cmd, end_cmd; - - if (mmc->high_capacity) - end = start + blkcnt - 1; - else { - end = (start + blkcnt - 1) * mmc->write_bl_len; - start *= mmc->write_bl_len; - } - - if (IS_SD(mmc)) { - start_cmd = SD_CMD_ERASE_WR_BLK_START; - end_cmd = SD_CMD_ERASE_WR_BLK_END; - } else { - start_cmd = MMC_CMD_ERASE_GROUP_START; - end_cmd = MMC_CMD_ERASE_GROUP_END; - } - - cmd.cmdidx = start_cmd; - cmd.cmdarg = start; - cmd.resp_type = MMC_RSP_R1; - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) - goto err_out; - - cmd.cmdidx = end_cmd; - cmd.cmdarg = end; - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) - goto err_out; - - cmd.cmdidx = MMC_CMD_ERASE; - cmd.cmdarg = SECURE_ERASE; - cmd.resp_type = MMC_RSP_R1b; - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) - goto err_out; - - return 0; - -err_out: - puts("mmc erase failed\n"); - return err; -} - -static unsigned long -mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt) -{ - int err = 0; - struct mmc *mmc = find_mmc_device(dev_num); - lbaint_t blk = 0, blk_r = 0; - int timeout = 1000; - - if (!mmc) - return -1; - - if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size)) - printf("\n\nCaution! Your devices Erase group is 0x%x\n" - "The erase range would be change to " - "0x" LBAF "~0x" LBAF "\n\n", - mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1), - ((start + blkcnt + mmc->erase_grp_size) - & ~(mmc->erase_grp_size - 1)) - 1); - - while (blk < blkcnt) { - blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ? - mmc->erase_grp_size : (blkcnt - blk); - err = mmc_erase_t(mmc, start + blk, blk_r); - if (err) - break; - - blk += blk_r; - - /* Waiting for the ready status */ - if (mmc_send_status(mmc, timeout)) - return 0; - } - - return blk; -} - -static ulong -mmc_write_blocks(struct mmc *mmc, lbaint_t start, lbaint_t blkcnt, const void*src) -{ - struct mmc_cmd cmd; - struct mmc_data data; - int timeout = 1000; - - if ((start + blkcnt) > mmc->block_dev.lba) { - printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", - start + blkcnt, mmc->block_dev.lba); - return 0; - } - - if (blkcnt == 0) - return 0; - else if (blkcnt == 1) - cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK; - else - cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; - - if (mmc->high_capacity) - cmd.cmdarg = start; - else - cmd.cmdarg = start * mmc->write_bl_len; - - cmd.resp_type = MMC_RSP_R1; - - data.src = src; - data.blocks = blkcnt; - data.blocksize = mmc->write_bl_len; - data.flags = MMC_DATA_WRITE; - - if (mmc_send_cmd(mmc, &cmd, &data)) { - printf("mmc write failed\n"); - return 0; - } - - /* SPI multiblock writes terminate using a special - * token, not a STOP_TRANSMISSION request. - */ - if (!mmc_host_is_spi(mmc) && blkcnt > 1) { - cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; - cmd.cmdarg = 0; - cmd.resp_type = MMC_RSP_R1b; - if (mmc_send_cmd(mmc, &cmd, NULL)) { - printf("mmc fail to send stop cmd\n"); - return 0; - } - } - - /* Waiting for the ready status */ - if (mmc_send_status(mmc, timeout)) - return 0; - - return blkcnt; -} - -static ulong -mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void*src) -{ - lbaint_t cur, blocks_todo = blkcnt; - - struct mmc *mmc = find_mmc_device(dev_num); - if (!mmc) - return 0; - - if (mmc_set_blocklen(mmc, mmc->write_bl_len)) - return 0; - - do { - cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo; - if(mmc_write_blocks(mmc, start, cur, src) != cur) - return 0; - blocks_todo -= cur; - start += cur; - src += cur * mmc->write_bl_len; - } while (blocks_todo > 0); - - return blkcnt; -} - static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, lbaint_t blkcnt) { @@ -385,7 +220,9 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, cmd.cmdarg = 0; cmd.resp_type = MMC_RSP_R1b; if (mmc_send_cmd(mmc, &cmd, NULL)) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("mmc fail to send stop cmd\n"); +#endif return 0; } } @@ -405,8 +242,10 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) return 0; if ((start + blkcnt) > mmc->block_dev.lba) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", start + blkcnt, mmc->block_dev.lba); +#endif return 0; } @@ -414,7 +253,8 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) return 0; do { - cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo; + cur = (blocks_todo > mmc->cfg->b_max) ? + mmc->cfg->b_max : blocks_todo; if(mmc_read_blocks(mmc, dst, start, cur) != cur) return 0; blocks_todo -= cur; @@ -473,7 +313,7 @@ static int sd_send_op_cond(struct mmc *mmc) * specified. */ cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : - (mmc->voltages & 0xff8000); + (mmc->cfg->voltages & 0xff8000); if (mmc->version == SD_VERSION_2) cmd.cmdarg |= OCR_HCS; @@ -521,11 +361,11 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd, cmd->cmdarg = 0; if (use_arg && !mmc_host_is_spi(mmc)) { cmd->cmdarg = - (mmc->voltages & + (mmc->cfg->voltages & (mmc->op_cond_response & OCR_VOLTAGE_MASK)) | (mmc->op_cond_response & OCR_ACCESS_MODE); - if (mmc->host_caps & MMC_MODE_HC) + if (mmc->cfg->host_caps & MMC_MODE_HC) cmd->cmdarg |= OCR_HCS; } err = mmc_send_cmd(mmc, cmd, NULL); @@ -535,7 +375,7 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd, return 0; } -int mmc_send_op_cond(struct mmc *mmc) +static int mmc_send_op_cond(struct mmc *mmc) { struct mmc_cmd cmd; int err, i; @@ -557,7 +397,7 @@ int mmc_send_op_cond(struct mmc *mmc) return IN_PROGRESS; } -int mmc_complete_op_cond(struct mmc *mmc) +static int mmc_complete_op_cond(struct mmc *mmc) { struct mmc_cmd cmd; int timeout = 1000; @@ -594,7 +434,7 @@ int mmc_complete_op_cond(struct mmc *mmc) mmc->ocr = cmd.response[0]; mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); - mmc->rca = 0; + mmc->rca = 1; return 0; } @@ -659,6 +499,8 @@ static int mmc_change_freq(struct mmc *mmc) if (mmc->version < MMC_VERSION_4) return 0; + mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; + err = mmc_send_ext_csd(mmc, ext_csd); if (err) @@ -669,7 +511,7 @@ static int mmc_change_freq(struct mmc *mmc) err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); if (err) - return err; + return err == SWITCH_ERR ? 0 : err; /* Now check to see that it worked */ err = mmc_send_ext_csd(mmc, ext_csd); @@ -682,10 +524,13 @@ static int mmc_change_freq(struct mmc *mmc) return 0; /* High Speed is set, there are two types: 52MHz and 26MHz */ - if (cardtype & MMC_HS_52MHZ) + if (cardtype & EXT_CSD_CARD_TYPE_52) { + if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) + mmc->card_caps |= MMC_MODE_DDR_52MHz; mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - else + } else { mmc->card_caps |= MMC_MODE_HS; + } return 0; } @@ -718,6 +563,32 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num) return 0; } +int mmc_select_hwpart(int dev_num, int hwpart) +{ + struct mmc *mmc = find_mmc_device(dev_num); + int ret; + + if (!mmc) + return -ENODEV; + + if (mmc->part_num == hwpart) + return 0; + + if (mmc->part_config == MMCPART_NOAVAILABLE) { + printf("Card doesn't support part_switch\n"); + return -EMEDIUMTYPE; + } + + ret = mmc_switch_part(dev_num, hwpart); + if (ret) + return ret; + + mmc->part_num = hwpart; + + return 0; +} + + int mmc_switch_part(int dev_num, unsigned int part_num) { struct mmc *mmc = find_mmc_device(dev_num); @@ -729,10 +600,209 @@ int mmc_switch_part(int dev_num, unsigned int part_num) ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, (mmc->part_config & ~PART_ACCESS_MASK) | (part_num & PART_ACCESS_MASK)); - if (ret) - return ret; - return mmc_set_capacity(mmc, part_num); + /* + * Set the capacity if the switch succeeded or was intended + * to return to representing the raw device. + */ + if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) + ret = mmc_set_capacity(mmc, part_num); + + return ret; +} + +int mmc_hwpart_config(struct mmc *mmc, + const struct mmc_hwpart_conf *conf, + enum mmc_hwpart_conf_mode mode) +{ + u8 part_attrs = 0; + u32 enh_size_mult; + u32 enh_start_addr; + u32 gp_size_mult[4]; + u32 max_enh_size_mult; + u32 tot_enh_size_mult = 0; + u8 wr_rel_set; + int i, pidx, err; + ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); + + if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) + return -EINVAL; + + if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { + printf("eMMC >= 4.4 required for enhanced user data area\n"); + return -EMEDIUMTYPE; + } + + if (!(mmc->part_support & PART_SUPPORT)) { + printf("Card does not support partitioning\n"); + return -EMEDIUMTYPE; + } + + if (!mmc->hc_wp_grp_size) { + printf("Card does not define HC WP group size\n"); + return -EMEDIUMTYPE; + } + + /* check partition alignment and total enhanced size */ + if (conf->user.enh_size) { + if (conf->user.enh_size % mmc->hc_wp_grp_size || + conf->user.enh_start % mmc->hc_wp_grp_size) { + printf("User data enhanced area not HC WP group " + "size aligned\n"); + return -EINVAL; + } + part_attrs |= EXT_CSD_ENH_USR; + enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; + if (mmc->high_capacity) { + enh_start_addr = conf->user.enh_start; + } else { + enh_start_addr = (conf->user.enh_start << 9); + } + } else { + enh_size_mult = 0; + enh_start_addr = 0; + } + tot_enh_size_mult += enh_size_mult; + + for (pidx = 0; pidx < 4; pidx++) { + if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { + printf("GP%i partition not HC WP group size " + "aligned\n", pidx+1); + return -EINVAL; + } + gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; + if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { + part_attrs |= EXT_CSD_ENH_GP(pidx); + tot_enh_size_mult += gp_size_mult[pidx]; + } + } + + if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { + printf("Card does not support enhanced attribute\n"); + return -EMEDIUMTYPE; + } + + err = mmc_send_ext_csd(mmc, ext_csd); + if (err) + return err; + + max_enh_size_mult = + (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + + (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + + ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; + if (tot_enh_size_mult > max_enh_size_mult) { + printf("Total enhanced size exceeds maximum (%u > %u)\n", + tot_enh_size_mult, max_enh_size_mult); + return -EMEDIUMTYPE; + } + + /* The default value of EXT_CSD_WR_REL_SET is device + * dependent, the values can only be changed if the + * EXT_CSD_HS_CTRL_REL bit is set. The values can be + * changed only once and before partitioning is completed. */ + wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; + if (conf->user.wr_rel_change) { + if (conf->user.wr_rel_set) + wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; + else + wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; + } + for (pidx = 0; pidx < 4; pidx++) { + if (conf->gp_part[pidx].wr_rel_change) { + if (conf->gp_part[pidx].wr_rel_set) + wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); + else + wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); + } + } + + if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && + !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { + puts("Card does not support host controlled partition write " + "reliability settings\n"); + return -EMEDIUMTYPE; + } + + if (ext_csd[EXT_CSD_PARTITION_SETTING] & + EXT_CSD_PARTITION_SETTING_COMPLETED) { + printf("Card already partitioned\n"); + return -EPERM; + } + + if (mode == MMC_HWPART_CONF_CHECK) + return 0; + + /* Partitioning requires high-capacity size definitions */ + if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_ERASE_GROUP_DEF, 1); + + if (err) + return err; + + ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; + + /* update erase group size to be high-capacity */ + mmc->erase_grp_size = + ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; + + } + + /* all OK, write the configuration */ + for (i = 0; i < 4; i++) { + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_ENH_START_ADDR+i, + (enh_start_addr >> (i*8)) & 0xFF); + if (err) + return err; + } + for (i = 0; i < 3; i++) { + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_ENH_SIZE_MULT+i, + (enh_size_mult >> (i*8)) & 0xFF); + if (err) + return err; + } + for (pidx = 0; pidx < 4; pidx++) { + for (i = 0; i < 3; i++) { + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_GP_SIZE_MULT+pidx*3+i, + (gp_size_mult[pidx] >> (i*8)) & 0xFF); + if (err) + return err; + } + } + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); + if (err) + return err; + + if (mode == MMC_HWPART_CONF_SET) + return 0; + + /* The WR_REL_SET is a write-once register but shall be + * written before setting PART_SETTING_COMPLETED. As it is + * write-once we can only write it when completing the + * partitioning. */ + if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_WR_REL_SET, wr_rel_set); + if (err) + return err; + } + + /* Setting PART_SETTING_COMPLETED confirms the partition + * configuration but it only becomes effective after power + * cycle, so we do not adjust the partition related settings + * in the mmc struct. */ + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_PARTITION_SETTING, + EXT_CSD_PARTITION_SETTING_COMPLETED); + if (err) + return err; + + return 0; } int mmc_getcd(struct mmc *mmc) @@ -742,8 +812,8 @@ int mmc_getcd(struct mmc *mmc) cd = board_mmc_getcd(mmc); if (cd < 0) { - if (mmc->getcd) - cd = mmc->getcd(mmc); + if (mmc->cfg->ops->getcd) + cd = mmc->cfg->ops->getcd(mmc); else cd = 1; } @@ -867,8 +937,8 @@ retry_scr: * This can avoid furthur problem when the card runs in different * mode between the host. */ - if (!((mmc->host_caps & MMC_MODE_HS_52MHz) && - (mmc->host_caps & MMC_MODE_HS))) + if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && + (mmc->cfg->host_caps & MMC_MODE_HS))) return 0; err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); @@ -915,16 +985,17 @@ static const int multipliers[] = { static void mmc_set_ios(struct mmc *mmc) { - mmc->set_ios(mmc); + if (mmc->cfg->ops->set_ios) + mmc->cfg->ops->set_ios(mmc); } void mmc_set_clock(struct mmc *mmc, uint clock) { - if (clock > mmc->f_max) - clock = mmc->f_max; + if (clock > mmc->cfg->f_max) + clock = mmc->cfg->f_max; - if (clock < mmc->f_min) - clock = mmc->f_min; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; mmc->clock = clock; @@ -947,6 +1018,8 @@ static int mmc_startup(struct mmc *mmc) ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); int timeout = 1000; + bool has_parts = false; + bool part_completed; #ifdef CONFIG_MMC_SPI_CRC_ON if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ @@ -1041,6 +1114,7 @@ static int mmc_startup(struct mmc *mmc) mmc->tran_speed = freq * mult; + mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); if (IS_SD(mmc)) @@ -1071,6 +1145,14 @@ static int mmc_startup(struct mmc *mmc) if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) mmc->write_bl_len = MMC_MAX_BLOCK_LEN; + if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { + cmd.cmdidx = MMC_CMD_SET_DSR; + cmd.cmdarg = (mmc->dsr & 0xffff) << 16; + cmd.resp_type = MMC_RSP_NONE; + if (mmc_send_cmd(mmc, &cmd, NULL)) + printf("MMC: SET_DSR failed\n"); + } + /* Select the card, and put it into Transfer Mode */ if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ cmd.cmdidx = MMC_CMD_SELECT_CARD; @@ -1090,7 +1172,9 @@ static int mmc_startup(struct mmc *mmc) if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { /* check ext_csd version and capacity */ err = mmc_send_ext_csd(mmc, ext_csd); - if (!err && (ext_csd[EXT_CSD_REV] >= 2)) { + if (err) + return err; + if (ext_csd[EXT_CSD_REV] >= 2) { /* * According to the JEDEC Standard, the value of * ext_csd's capacity is valid if the value is more @@ -1121,29 +1205,27 @@ static int mmc_startup(struct mmc *mmc) case 6: mmc->version = MMC_VERSION_4_5; break; + case 7: + mmc->version = MMC_VERSION_5_0; + break; } - /* - * Check whether GROUP_DEF is set, if yes, read out - * group size from ext_csd directly, or calculate - * the group size from the csd value. - */ - if (ext_csd[EXT_CSD_ERASE_GROUP_DEF]) { - mmc->erase_grp_size = - ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * - MMC_MAX_BLOCK_LEN * 1024; - } else { - int erase_gsz, erase_gmul; - erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; - erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; - mmc->erase_grp_size = (erase_gsz + 1) - * (erase_gmul + 1); - } + /* The partition data may be non-zero but it is only + * effective if PARTITION_SETTING_COMPLETED is set in + * EXT_CSD, so ignore any data if this bit is not set, + * except for enabling the high-capacity group size + * definition (see below). */ + part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & + EXT_CSD_PARTITION_SETTING_COMPLETED); /* store the partition info of emmc */ + mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || ext_csd[EXT_CSD_BOOT_MULT]) mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; + if (part_completed && + (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) + mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; @@ -1151,12 +1233,87 @@ static int mmc_startup(struct mmc *mmc) for (i = 0; i < 4; i++) { int idx = EXT_CSD_GP_SIZE_MULT + i * 3; - mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) + + uint mult = (ext_csd[idx + 2] << 16) + (ext_csd[idx + 1] << 8) + ext_csd[idx]; + if (mult) + has_parts = true; + if (!part_completed) + continue; + mmc->capacity_gp[i] = mult; mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; + mmc->capacity_gp[i] <<= 19; + } + + if (part_completed) { + mmc->enh_user_size = + (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + + (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + + ext_csd[EXT_CSD_ENH_SIZE_MULT]; + mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; + mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; + mmc->enh_user_size <<= 19; + mmc->enh_user_start = + (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + + (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + + (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + + ext_csd[EXT_CSD_ENH_START_ADDR]; + if (mmc->high_capacity) + mmc->enh_user_start <<= 9; + } + + /* + * Host needs to enable ERASE_GRP_DEF bit if device is + * partitioned. This bit will be lost every time after a reset + * or power off. This will affect erase size. + */ + if (part_completed) + has_parts = true; + if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && + (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) + has_parts = true; + if (has_parts) { + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_ERASE_GROUP_DEF, 1); + + if (err) + return err; + else + ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; + } + + if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { + /* Read out group size from ext_csd */ + mmc->erase_grp_size = + ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; + /* + * if high capacity and partition setting completed + * SEC_COUNT is valid even if it is smaller than 2 GiB + * JEDEC Standard JESD84-B45, 6.2.4 + */ + if (mmc->high_capacity && part_completed) { + capacity = (ext_csd[EXT_CSD_SEC_CNT]) | + (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | + (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | + (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); + capacity *= MMC_MAX_BLOCK_LEN; + mmc->capacity_user = capacity; + } + } else { + /* Calculate the group size from the csd value. */ + int erase_gsz, erase_gmul; + erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; + erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; + mmc->erase_grp_size = (erase_gsz + 1) + * (erase_gmul + 1); } + + mmc->hc_wp_grp_size = 1024 + * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] + * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; + + mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; } err = mmc_set_capacity(mmc, mmc->part_num); @@ -1172,7 +1329,7 @@ static int mmc_startup(struct mmc *mmc) return err; /* Restrict card's capabilities by what the host can do */ - mmc->card_caps &= mmc->host_caps; + mmc->card_caps &= mmc->cfg->host_caps; if (IS_SD(mmc)) { if (mmc->card_caps & MMC_MODE_4BIT) { @@ -1198,11 +1355,14 @@ static int mmc_startup(struct mmc *mmc) mmc->tran_speed = 50000000; else mmc->tran_speed = 25000000; - } else { + } else if (mmc->version >= MMC_VERSION_4) { + /* Only version 4 of MMC supports wider bus widths */ int idx; /* An array of possible bus widths in order of preference */ static unsigned ext_csd_bits[] = { + EXT_CSD_DDR_BUS_WIDTH_8, + EXT_CSD_DDR_BUS_WIDTH_4, EXT_CSD_BUS_WIDTH_8, EXT_CSD_BUS_WIDTH_4, EXT_CSD_BUS_WIDTH_1, @@ -1210,24 +1370,40 @@ static int mmc_startup(struct mmc *mmc) /* An array to map CSD bus widths to host cap bits */ static unsigned ext_to_hostcaps[] = { + [EXT_CSD_DDR_BUS_WIDTH_4] = + MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, + [EXT_CSD_DDR_BUS_WIDTH_8] = + MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, }; /* An array to map chosen bus width to an integer */ static unsigned widths[] = { - 8, 4, 1, + 8, 4, 8, 4, 1, }; for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { unsigned int extw = ext_csd_bits[idx]; + unsigned int caps = ext_to_hostcaps[extw]; /* - * Check to make sure the controller supports - * this bus width, if it's more than 1 + * If the bus width is still not changed, + * don't try to set the default again. + * Otherwise, recover from switch attempts + * by switching to 1-bit bus width. */ - if (extw != EXT_CSD_BUS_WIDTH_1 && - !(mmc->host_caps & ext_to_hostcaps[extw])) + if (extw == EXT_CSD_BUS_WIDTH_1 && + mmc->bus_width == 1) { + err = 0; + break; + } + + /* + * Check to make sure the card and controller support + * these capabilities + */ + if ((mmc->card_caps & caps) != caps) continue; err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, @@ -1236,25 +1412,33 @@ static int mmc_startup(struct mmc *mmc) if (err) continue; + mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; mmc_set_bus_width(mmc, widths[idx]); err = mmc_send_ext_csd(mmc, test_csd); - if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \ - == test_csd[EXT_CSD_PARTITIONING_SUPPORT] - && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \ - == test_csd[EXT_CSD_ERASE_GROUP_DEF] \ - && ext_csd[EXT_CSD_REV] \ - == test_csd[EXT_CSD_REV] - && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \ - == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] - && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \ - &test_csd[EXT_CSD_SEC_CNT], 4) == 0) { - - mmc->card_caps |= ext_to_hostcaps[extw]; + + if (err) + continue; + + /* Only compare read only fields */ + if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] + == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && + ext_csd[EXT_CSD_HC_WP_GRP_SIZE] + == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && + ext_csd[EXT_CSD_REV] + == test_csd[EXT_CSD_REV] && + ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] + == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && + memcmp(&ext_csd[EXT_CSD_SEC_CNT], + &test_csd[EXT_CSD_SEC_CNT], 4) == 0) break; - } + else + err = SWITCH_ERR; } + if (err) + return err; + if (mmc->card_caps & MMC_MODE_HS) { if (mmc->card_caps & MMC_MODE_HS_52MHz) mmc->tran_speed = 52000000; @@ -1265,12 +1449,19 @@ static int mmc_startup(struct mmc *mmc) mmc_set_clock(mmc, mmc->tran_speed); + /* Fix the block length for DDR mode */ + if (mmc->ddr_mode) { + mmc->read_bl_len = MMC_MAX_BLOCK_LEN; + mmc->write_bl_len = MMC_MAX_BLOCK_LEN; + } + /* fill in device description */ mmc->block_dev.lun = 0; mmc->block_dev.type = 0; mmc->block_dev.blksz = mmc->read_bl_len; mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), (mmc->cid[3] >> 16) & 0xffff); @@ -1280,6 +1471,11 @@ static int mmc_startup(struct mmc *mmc) (mmc->cid[2] >> 24) & 0xff); sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, (mmc->cid[2] >> 16) & 0xf); +#else + mmc->block_dev.vendor[0] = 0; + mmc->block_dev.product[0] = 0; + mmc->block_dev.revision[0] = 0; +#endif #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) init_part(&mmc->block_dev); #endif @@ -1294,7 +1490,7 @@ static int mmc_send_if_cond(struct mmc *mmc) cmd.cmdidx = SD_CMD_SEND_IF_COND; /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ - cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa; + cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; cmd.resp_type = MMC_RSP_R7; err = mmc_send_cmd(mmc, &cmd, NULL); @@ -1310,8 +1506,36 @@ static int mmc_send_if_cond(struct mmc *mmc) return 0; } -int mmc_register(struct mmc *mmc) +/* not used any more */ +int __deprecated mmc_register(struct mmc *mmc) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + printf("%s is deprecated! use mmc_create() instead.\n", __func__); +#endif + return -1; +} + +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) +{ + struct mmc *mmc; + + /* quick validation */ + if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || + cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) + return NULL; + + mmc = calloc(1, sizeof(*mmc)); + if (mmc == NULL) + return NULL; + + mmc->cfg = cfg; + mmc->priv = priv; + + /* the following chunk was mmc_register() */ + + /* Setup dsr related values */ + mmc->dsr_imp = 0; + mmc->dsr = 0xffffffff; /* Setup the universal parts of the block interface just once */ mmc->block_dev.if_type = IF_TYPE_MMC; mmc->block_dev.dev = cur_dev_num++; @@ -1319,14 +1543,22 @@ int mmc_register(struct mmc *mmc) mmc->block_dev.block_read = mmc_bread; mmc->block_dev.block_write = mmc_bwrite; mmc->block_dev.block_erase = mmc_berase; - if (!mmc->b_max) - mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - INIT_LIST_HEAD (&mmc->link); + /* setup initial part type */ + mmc->block_dev.part_type = mmc->cfg->part_type; - list_add_tail (&mmc->link, &mmc_devices); + INIT_LIST_HEAD(&mmc->link); - return 0; + list_add_tail(&mmc->link, &mmc_devices); + mmc_dev_count++; + + return mmc; +} + +void mmc_destroy(struct mmc *mmc) +{ + /* only freeing memory for now */ + free(mmc); } #ifdef CONFIG_PARTITIONS @@ -1340,24 +1572,36 @@ block_dev_desc_t *mmc_get_dev(int dev) } #endif +/* board-specific MMC power initializations. */ +__weak void board_mmc_power_init(void) +{ +} + int mmc_start_init(struct mmc *mmc) { int err; - if (mmc_getcd(mmc) == 0) { + /* we pretend there's no card when init is NULL */ + if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { mmc->has_init = 0; +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC: no card present\n"); +#endif return NO_CARD_ERR; } if (mmc->has_init) return 0; - err = mmc->init(mmc); + board_mmc_power_init(); + + /* made sure it's not NULL earlier */ + err = mmc->cfg->ops->init(mmc); if (err) return err; + mmc->ddr_mode = 0; mmc_set_bus_width(mmc, 1); mmc_set_clock(mmc, 1); @@ -1381,7 +1625,9 @@ int mmc_start_init(struct mmc *mmc) err = mmc_send_op_cond(mmc); if (err && err != IN_PROGRESS) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("Card did not respond to voltage select!\n"); +#endif return UNUSABLE_ERR; } } @@ -1412,10 +1658,13 @@ static int mmc_complete_init(struct mmc *mmc) int mmc_init(struct mmc *mmc) { int err = IN_PROGRESS; - unsigned start = get_timer(0); + unsigned start; if (mmc->has_init) return 0; + + start = get_timer(0); + if (!mmc->init_in_progress) err = mmc_start_init(mmc); @@ -1425,17 +1674,25 @@ int mmc_init(struct mmc *mmc) return err; } -/* - * CPU and board-specific MMC initializations. Aliased function - * signals caller to move on - */ -static int __def_mmc_init(bd_t *bis) +int mmc_set_dsr(struct mmc *mmc, u16 val) +{ + mmc->dsr = val; + return 0; +} + +/* CPU-specific MMC initializations */ +__weak int cpu_mmc_init(bd_t *bis) { return -1; } -int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init"))); -int board_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init"))); +/* board-specific MMC initializations. */ +__weak int board_mmc_init(bd_t *bis) +{ + return -1; +} + +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) void print_mmc_devices(char separator) { @@ -1445,20 +1702,32 @@ void print_mmc_devices(char separator) list_for_each(entry, &mmc_devices) { m = list_entry(entry, struct mmc, link); - printf("%s: %d", m->name, m->block_dev.dev); + printf("%s: %d", m->cfg->name, m->block_dev.dev); - if (entry->next != &mmc_devices) - printf("%c ", separator); + if (entry->next != &mmc_devices) { + printf("%c", separator); + if (separator != '\n') + puts (" "); + } } printf("\n"); } +#else +void print_mmc_devices(char separator) { } +#endif + int get_mmc_num(void) { return cur_dev_num; } +int get_mmc_dev_count(void) +{ + return mmc_dev_count; +} + void mmc_set_preinit(struct mmc *mmc, int preinit) { mmc->preinit = preinit; @@ -1486,7 +1755,9 @@ int mmc_initialize(bd_t *bis) if (board_mmc_init(bis) < 0) cpu_mmc_init(bis); +#ifndef CONFIG_SPL_BUILD print_mmc_devices(','); +#endif do_preinit(); return 0; @@ -1561,67 +1832,69 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, } /* - * This function shall form and send the commands to open / close the - * boot partition specified by user. - * - * Input Parameters: - * ack: 0x0 - No boot acknowledge sent (default) - * 0x1 - Boot acknowledge sent during boot operation - * part_num: User selects boot data that will be sent to master - * 0x0 - Device not boot enabled (default) - * 0x1 - Boot partition 1 enabled for boot - * 0x2 - Boot partition 2 enabled for boot - * access: User selects partitions to access - * 0x0 : No access to boot partition (default) - * 0x1 : R/W boot partition 1 - * 0x2 : R/W boot partition 2 - * 0x3 : R/W Replay Protected Memory Block (RPMB) + * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH + * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH + * and BOOT_MODE. * * Returns 0 on success. */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) { int err; - struct mmc_cmd cmd; - /* Boot ack enable, boot partition enable , boot partition access */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, + EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | + EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | + EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_PART_CONF << 16) | - ((EXT_CSD_BOOT_ACK(ack) | - EXT_CSD_BOOT_PART_NUM(part_num) | - EXT_CSD_PARTITION_ACCESS(access)) << 8); + if (err) + return err; + return 0; +} - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - if (access) { - debug("mmc boot partition#%d open fail:Error1 = %d\n", - part_num, err); - } else { - debug("mmc boot partition#%d close fail:Error = %d\n", - part_num, err); - } +/* + * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) + * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and + * PARTITION_ACCESS. + * + * Returns 0 on success. + */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +{ + int err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, + EXT_CSD_BOOT_ACK(ack) | + EXT_CSD_BOOT_PART_NUM(part_num) | + EXT_CSD_PARTITION_ACCESS(access)); + + if (err) return err; - } + return 0; +} - if (access) { - /* 4bit transfer mode at booting time. */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; +/* + * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value + * for enable. Note that this is a write-once field for non-zero values. + * + * Returns 0 on success. + */ +int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) +{ + int ret; + ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_BOOT_BUS_WIDTH << 16) | - ((1 << 0) << 8); + ret = mmc_send_ext_csd(mmc, ext_csd); + if (ret) + return ret; - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc boot partition#%d open fail:Error2 = %d\n", - part_num, err); - return err; - } + if (ext_csd[EXT_CSD_RST_N_FUNCTION] != 0 && + ext_csd[EXT_CSD_RST_N_FUNCTION] != enable) { + printf("RST_N_FUNCTION is already set to %u; cannot change to %u\n", + ext_csd[EXT_CSD_RST_N_FUNCTION], enable); + return -EINVAL; } - return 0; + return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, + enable); } #endif diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h new file mode 100644 index 0000000000..16dcf9ff61 --- /dev/null +++ b/drivers/mmc/mmc_private.h @@ -0,0 +1,45 @@ +/* + * Copyright 2008,2010 Freescale Semiconductor, Inc + * Andy Fleming + * + * Based (loosely) on the Linux code + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MMC_PRIVATE_H_ +#define _MMC_PRIVATE_H_ + +#include + +extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data); +extern int mmc_send_status(struct mmc *mmc, int timeout); +extern int mmc_set_blocklen(struct mmc *mmc, int len); + +#ifndef CONFIG_SPL_BUILD + +extern unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt); + +extern ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, + const void *src); + +#else /* CONFIG_SPL_BUILD */ + +/* SPL will never write or erase, declare dummies to reduce code size. */ + +static inline unsigned long mmc_berase(int dev_num, lbaint_t start, + lbaint_t blkcnt) +{ + return 0; +} + +static inline ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, + const void *src) +{ + return 0; +} + +#endif /* CONFIG_SPL_BUILD */ + +#endif /* _MMC_PRIVATE_H_ */ diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index fe6a5a166d..5b5b33a4b2 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -92,7 +92,7 @@ static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf, spi_xfer(spi, 2 * 8, NULL, &crc, 0); #ifdef CONFIG_MMC_SPI_CRC_ON if (swab16(cyg_crc16(buf, bsize)) != crc) { - debug("%s: CRC error\n", mmc->name); + debug("%s: CRC error\n", mmc->cfg->name); r1 = R1_SPI_COM_CRC; break; } @@ -238,6 +238,7 @@ done: static void mmc_spi_set_ios(struct mmc *mmc) { struct spi_slave *spi = mmc->priv; + debug("%s: clock %u\n", __func__, mmc->clock); if (mmc->clock) spi_set_speed(spi, mmc->clock); @@ -246,7 +247,6 @@ static void mmc_spi_set_ios(struct mmc *mmc) static int mmc_spi_init_p(struct mmc *mmc) { struct spi_slave *spi = mmc->priv; - mmc->clock = 0; spi_set_speed(spi, MMC_SPI_MIN_CLOCK); spi_claim_bus(spi); /* cs deactivated for 100+ clock */ @@ -255,33 +255,37 @@ static int mmc_spi_init_p(struct mmc *mmc) return 0; } +static const struct mmc_ops mmc_spi_ops = { + .send_cmd = mmc_spi_request, + .set_ios = mmc_spi_set_ios, + .init = mmc_spi_init_p, +}; + +static struct mmc_config mmc_spi_cfg = { + .name = "MMC_SPI", + .ops = &mmc_spi_ops, + .host_caps = MMC_MODE_SPI, + .voltages = MMC_SPI_VOLTAGE, + .f_min = MMC_SPI_MIN_CLOCK, + .part_type = PART_TYPE_DOS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode) { struct mmc *mmc; + struct spi_slave *spi; - mmc = malloc(sizeof(*mmc)); - if (!mmc) - return NULL; - memset(mmc, 0, sizeof(*mmc)); - mmc->priv = spi_setup_slave(bus, cs, speed, mode); - if (!mmc->priv) { - free(mmc); + spi = spi_setup_slave(bus, cs, speed, mode); + if (spi == NULL) return NULL; - } - sprintf(mmc->name, "MMC_SPI"); - mmc->send_cmd = mmc_spi_request; - mmc->set_ios = mmc_spi_set_ios; - mmc->init = mmc_spi_init_p; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_SPI; - - mmc->voltages = MMC_SPI_VOLTAGE; - mmc->f_max = speed; - mmc->f_min = MMC_SPI_MIN_CLOCK; - mmc->block_dev.part_type = PART_TYPE_DOS; - mmc_register(mmc); + mmc_spi_cfg.f_max = speed; + mmc = mmc_create(&mmc_spi_cfg, spi); + if (mmc == NULL) { + spi_free_slave(spi); + return NULL; + } return mmc; } diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c new file mode 100644 index 0000000000..3db9669c82 --- /dev/null +++ b/drivers/mmc/mmc_write.c @@ -0,0 +1,180 @@ +/* + * Copyright 2008, Freescale Semiconductor, Inc + * Andy Fleming + * + * Based vaguely on the Linux code + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "mmc_private.h" + +static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt) +{ + struct mmc_cmd cmd; + ulong end; + int err, start_cmd, end_cmd; + + if (mmc->high_capacity) { + end = start + blkcnt - 1; + } else { + end = (start + blkcnt - 1) * mmc->write_bl_len; + start *= mmc->write_bl_len; + } + + if (IS_SD(mmc)) { + start_cmd = SD_CMD_ERASE_WR_BLK_START; + end_cmd = SD_CMD_ERASE_WR_BLK_END; + } else { + start_cmd = MMC_CMD_ERASE_GROUP_START; + end_cmd = MMC_CMD_ERASE_GROUP_END; + } + + cmd.cmdidx = start_cmd; + cmd.cmdarg = start; + cmd.resp_type = MMC_RSP_R1; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) + goto err_out; + + cmd.cmdidx = end_cmd; + cmd.cmdarg = end; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) + goto err_out; + + cmd.cmdidx = MMC_CMD_ERASE; + cmd.cmdarg = SECURE_ERASE; + cmd.resp_type = MMC_RSP_R1b; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) + goto err_out; + + return 0; + +err_out: + puts("mmc erase failed\n"); + return err; +} + +unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt) +{ + int err = 0; + struct mmc *mmc = find_mmc_device(dev_num); + lbaint_t blk = 0, blk_r = 0; + int timeout = 1000; + + if (!mmc) + return -1; + + if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size)) + printf("\n\nCaution! Your devices Erase group is 0x%x\n" + "The erase range would be change to " + "0x" LBAF "~0x" LBAF "\n\n", + mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1), + ((start + blkcnt + mmc->erase_grp_size) + & ~(mmc->erase_grp_size - 1)) - 1); + + while (blk < blkcnt) { + blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ? + mmc->erase_grp_size : (blkcnt - blk); + err = mmc_erase_t(mmc, start + blk, blk_r); + if (err) + break; + + blk += blk_r; + + /* Waiting for the ready status */ + if (mmc_send_status(mmc, timeout)) + return 0; + } + + return blk; +} + +static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, + lbaint_t blkcnt, const void *src) +{ + struct mmc_cmd cmd; + struct mmc_data data; + int timeout = 1000; + + if ((start + blkcnt) > mmc->block_dev.lba) { + printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", + start + blkcnt, mmc->block_dev.lba); + return 0; + } + + if (blkcnt == 0) + return 0; + else if (blkcnt == 1) + cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK; + else + cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; + + if (mmc->high_capacity) + cmd.cmdarg = start; + else + cmd.cmdarg = start * mmc->write_bl_len; + + cmd.resp_type = MMC_RSP_R1; + + data.src = src; + data.blocks = blkcnt; + data.blocksize = mmc->write_bl_len; + data.flags = MMC_DATA_WRITE; + + if (mmc_send_cmd(mmc, &cmd, &data)) { + printf("mmc write failed\n"); + return 0; + } + + /* SPI multiblock writes terminate using a special + * token, not a STOP_TRANSMISSION request. + */ + if (!mmc_host_is_spi(mmc) && blkcnt > 1) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + if (mmc_send_cmd(mmc, &cmd, NULL)) { + printf("mmc fail to send stop cmd\n"); + return 0; + } + } + + /* Waiting for the ready status */ + if (mmc_send_status(mmc, timeout)) + return 0; + + return blkcnt; +} + +ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src) +{ + lbaint_t cur, blocks_todo = blkcnt; + + struct mmc *mmc = find_mmc_device(dev_num); + if (!mmc) + return 0; + + if (mmc_set_blocklen(mmc, mmc->write_bl_len)) + return 0; + + do { + cur = (blocks_todo > mmc->cfg->b_max) ? + mmc->cfg->b_max : blocks_todo; + if (mmc_write_blocks(mmc, start, cur, src) != cur) + return 0; + blocks_todo -= cur; + start += cur; + src += cur * mmc->write_bl_len; + } while (blocks_todo > 0); + + return blkcnt; +} diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c new file mode 100644 index 0000000000..8ca09042d8 --- /dev/null +++ b/drivers/mmc/mvebu_mmc.c @@ -0,0 +1,438 @@ +/* + * Marvell MMC/SD/SDIO driver + * + * (C) Copyright 2012-2014 + * Marvell Semiconductor + * Written-by: Maen Suleiman, Gerald Kerma + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DRIVER_NAME "MVEBU_MMC" + +#define MVEBU_TARGET_DRAM 0 + +#define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */ + +static void mvebu_mmc_write(u32 offs, u32 val) +{ + writel(val, CONFIG_SYS_MMC_BASE + (offs)); +} + +static u32 mvebu_mmc_read(u32 offs) +{ + return readl(CONFIG_SYS_MMC_BASE + (offs)); +} + +static int mvebu_mmc_setup_data(struct mmc_data *data) +{ + u32 ctrl_reg; + + debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME, + (data->flags & MMC_DATA_READ) ? "read" : "write", + data->blocks, data->blocksize); + + /* default to maximum timeout */ + ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL); + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); + mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg); + + if (data->flags & MMC_DATA_READ) { + mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff); + mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16); + } else { + mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff); + mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16); + } + + mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks); + mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize); + + return 0; +} + +static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + ulong start; + ushort waittype = 0; + ushort resptype = 0; + ushort xfertype = 0; + ushort resp_indx = 0; + + debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", + DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg); + + debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME, + cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE)); + + /* + * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE + * register is sometimes not set before a while when some + * "unusual" data block sizes are used (such as with the SWITCH + * command), even despite the fact that the XFER_DONE interrupt + * was raised. And if another data transfer starts before + * this bit comes to good sense (which eventually happens by + * itself) then the new transfer simply fails with a timeout. + */ + if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) { + ushort hw_state, count = 0; + + start = get_timer(0); + do { + hw_state = mvebu_mmc_read(SDIO_HW_STATE); + if ((get_timer(0) - start) > TIMEOUT_DELAY) { + printf("%s : FIFO_EMPTY bit missing\n", + DRIVER_NAME); + break; + } + count++; + } while (!(hw_state & CMD_FIFO_EMPTY)); + debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n", + DRIVER_NAME, hw_state, count, (get_timer(0) - (start))); + } + + /* Clear status */ + mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK); + mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); + + resptype = SDIO_CMD_INDEX(cmd->cmdidx); + + /* Analyzing resptype/xfertype/waittype for the command */ + if (cmd->resp_type & MMC_RSP_BUSY) + resptype |= SDIO_CMD_RSP_48BUSY; + else if (cmd->resp_type & MMC_RSP_136) + resptype |= SDIO_CMD_RSP_136; + else if (cmd->resp_type & MMC_RSP_PRESENT) + resptype |= SDIO_CMD_RSP_48; + else + resptype |= SDIO_CMD_RSP_NONE; + + if (cmd->resp_type & MMC_RSP_CRC) + resptype |= SDIO_CMD_CHECK_CMDCRC; + + if (cmd->resp_type & MMC_RSP_OPCODE) + resptype |= SDIO_CMD_INDX_CHECK; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + resptype |= SDIO_UNEXPECTED_RESP; + waittype |= SDIO_NOR_UNEXP_RSP; + } + + if (data) { + int err = mvebu_mmc_setup_data(data); + + if (err) { + debug("%s: command DATA error :%x\n", + DRIVER_NAME, err); + return err; + } + + resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16; + xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN; + if (data->flags & MMC_DATA_READ) { + xfertype |= SDIO_XFER_MODE_TO_HOST; + waittype = SDIO_NOR_DMA_INI; + } else { + waittype |= SDIO_NOR_XFER_DONE; + } + } else { + waittype |= SDIO_NOR_CMD_DONE; + } + + /* Setting cmd arguments */ + mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff); + mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16); + + /* Setting Xfer mode */ + mvebu_mmc_write(SDIO_XFER_MODE, xfertype); + + /* Sending command */ + mvebu_mmc_write(SDIO_CMD, resptype); + + start = get_timer(0); + + while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) { + if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) { + debug("%s: error! cmdidx : %d, err reg: %04x\n", + DRIVER_NAME, cmd->cmdidx, + mvebu_mmc_read(SDIO_ERR_INTR_STATUS)); + if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) & + (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) { + debug("%s: command READ timed out\n", + DRIVER_NAME); + return TIMEOUT; + } + debug("%s: command READ error\n", DRIVER_NAME); + return COMM_ERR; + } + + if ((get_timer(0) - start) > TIMEOUT_DELAY) { + debug("%s: command timed out\n", DRIVER_NAME); + return TIMEOUT; + } + } + + /* Handling response */ + if (cmd->resp_type & MMC_RSP_136) { + uint response[8]; + + for (resp_indx = 0; resp_indx < 8; resp_indx++) + response[resp_indx] + = mvebu_mmc_read(SDIO_RSP(resp_indx)); + + cmd->response[0] = ((response[0] & 0x03ff) << 22) | + ((response[1] & 0xffff) << 6) | + ((response[2] & 0xfc00) >> 10); + cmd->response[1] = ((response[2] & 0x03ff) << 22) | + ((response[3] & 0xffff) << 6) | + ((response[4] & 0xfc00) >> 10); + cmd->response[2] = ((response[4] & 0x03ff) << 22) | + ((response[5] & 0xffff) << 6) | + ((response[6] & 0xfc00) >> 10); + cmd->response[3] = ((response[6] & 0x03ff) << 22) | + ((response[7] & 0x3fff) << 8); + } else if (cmd->resp_type & MMC_RSP_PRESENT) { + uint response[3]; + + for (resp_indx = 0; resp_indx < 3; resp_indx++) + response[resp_indx] + = mvebu_mmc_read(SDIO_RSP(resp_indx)); + + cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) | + ((response[1] & 0xffff) << (14 - 8)) | + ((response[0] & 0x03ff) << (30 - 8)); + cmd->response[1] = ((response[0] & 0xfc00) >> 10); + cmd->response[2] = 0; + cmd->response[3] = 0; + } else { + cmd->response[0] = 0; + cmd->response[1] = 0; + cmd->response[2] = 0; + cmd->response[3] = 0; + } + + debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type); + debug("[0x%x] ", cmd->response[0]); + debug("[0x%x] ", cmd->response[1]); + debug("[0x%x] ", cmd->response[2]); + debug("[0x%x] ", cmd->response[3]); + debug("\n"); + + if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) & + (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) + return TIMEOUT; + + return 0; +} + +static void mvebu_mmc_power_up(void) +{ + debug("%s: power up\n", DRIVER_NAME); + + /* disable interrupts */ + mvebu_mmc_write(SDIO_NOR_INTR_EN, 0); + mvebu_mmc_write(SDIO_ERR_INTR_EN, 0); + + /* SW reset */ + mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); + + mvebu_mmc_write(SDIO_XFER_MODE, 0); + + /* enable status */ + mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); + mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); + + /* enable interrupts status */ + mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK); + mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); +} + +static void mvebu_mmc_set_clk(unsigned int clock) +{ + unsigned int m; + + if (clock == 0) { + debug("%s: clock off\n", DRIVER_NAME); + mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK); + mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX); + } else { + m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1; + if (m > MVEBU_MMC_BASE_DIV_MAX) + m = MVEBU_MMC_BASE_DIV_MAX; + mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX); + debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m); + } +} + +static void mvebu_mmc_set_bus(unsigned int bus) +{ + u32 ctrl_reg = 0; + + ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL); + ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; + + switch (bus) { + case 4: + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; + break; + case 1: + default: + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT; + } + + /* default transfer mode */ + ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN; + ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST; + + /* default to maximum timeout */ + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); + ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN; + + ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN; + + ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY; + + debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg, + (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ? + "push-pull" : "open-drain", + (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ? + "4bit-width" : "1bit-width", + (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ? + "high-speed" : ""); + + mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg); +} + +static void mvebu_mmc_set_ios(struct mmc *mmc) +{ + debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME, + mmc->bus_width, mmc->clock); + mvebu_mmc_set_bus(mmc->bus_width); + mvebu_mmc_set_clk(mmc->clock); +} + +/* + * Set window register. + */ +static void mvebu_window_setup(void) +{ + int i; + + for (i = 0; i < 4; i++) { + mvebu_mmc_write(WINDOW_CTRL(i), 0); + mvebu_mmc_write(WINDOW_BASE(i), 0); + } + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + u32 size, base, attrib; + + /* Enable DRAM bank */ + switch (i) { + case 0: + attrib = KWCPU_ATTR_DRAM_CS0; + break; + case 1: + attrib = KWCPU_ATTR_DRAM_CS1; + break; + case 2: + attrib = KWCPU_ATTR_DRAM_CS2; + break; + case 3: + attrib = KWCPU_ATTR_DRAM_CS3; + break; + default: + /* invalide bank, disable access */ + attrib = 0; + break; + } + + size = gd->bd->bi_dram[i].size; + base = gd->bd->bi_dram[i].start; + if (size && attrib) { + mvebu_mmc_write(WINDOW_CTRL(i), + MVCPU_WIN_CTRL_DATA(size, + MVEBU_TARGET_DRAM, + attrib, + MVCPU_WIN_ENABLE)); + } else { + mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE); + } + mvebu_mmc_write(WINDOW_BASE(i), base); + } +} + +static int mvebu_mmc_initialize(struct mmc *mmc) +{ + debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME); + + /* + * Setting host parameters + * Initial Host Ctrl : Timeout : max , Normal Speed mode, + * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line + */ + mvebu_mmc_write(SDIO_HOST_CTRL, + SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) | + SDIO_HOST_CTRL_DATA_WIDTH_4_BITS | + SDIO_HOST_CTRL_BIG_ENDIAN | + SDIO_HOST_CTRL_PUSH_PULL_EN | + SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY); + + mvebu_mmc_write(SDIO_CLK_CTRL, 0); + + /* enable status */ + mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); + mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); + + /* disable interrupts */ + mvebu_mmc_write(SDIO_NOR_INTR_EN, 0); + mvebu_mmc_write(SDIO_ERR_INTR_EN, 0); + + mvebu_window_setup(); + + /* SW reset */ + mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); + + return 0; +} + +static const struct mmc_ops mvebu_mmc_ops = { + .send_cmd = mvebu_mmc_send_cmd, + .set_ios = mvebu_mmc_set_ios, + .init = mvebu_mmc_initialize, +}; + +static struct mmc_config mvebu_mmc_cfg = { + .name = DRIVER_NAME, + .ops = &mvebu_mmc_ops, + .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX, + .f_max = MVEBU_MMC_CLOCKRATE_MAX, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC | + MMC_MODE_HS_52MHz, + .part_type = PART_TYPE_DOS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + +int mvebu_mmc_init(bd_t *bis) +{ + struct mmc *mmc; + + mvebu_mmc_power_up(); + + mmc = mmc_create(&mvebu_mmc_cfg, bis); + if (mmc == NULL) + return -1; + + return 0; +} diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index 4f99617b9a..561b204598 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -122,6 +122,8 @@ struct mxcmci_host { }; static struct mxcmci_host mxcmci_host; + +/* maintainer note: do we really want to have a global host pointer? */ static struct mxcmci_host *host = &mxcmci_host; static inline int mxcmci_use_dma(struct mxcmci_host *host) @@ -485,35 +487,30 @@ static int mxcmci_init(struct mmc *mmc) return 0; } -static int mxcmci_initialize(bd_t *bis) -{ - struct mmc *mmc = NULL; - - mmc = malloc(sizeof(struct mmc)); - - if (!mmc) - return -ENOMEM; +static const struct mmc_ops mxcmci_ops = { + .send_cmd = mxcmci_request, + .set_ios = mxcmci_set_ios, + .init = mxcmci_init, +}; - sprintf(mmc->name, "MXC MCI"); - mmc->send_cmd = mxcmci_request; - mmc->set_ios = mxcmci_set_ios; - mmc->init = mxcmci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_4BIT; +static struct mmc_config mxcmci_cfg = { + .name = "MXC MCI", + .ops = &mxcmci_ops, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; +static int mxcmci_initialize(bd_t *bis) +{ host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE; - mmc->priv = host; - host->mmc = mmc; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - - mmc->f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7; - mmc->f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1; - mmc->b_max = 0; + mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7; + mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1; - mmc_register(mmc); + host->mmc = mmc_create(&mxcmci_cfg, host); + if (host->mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 7c59a6f367..d9d855b875 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -35,6 +35,7 @@ struct mxsmmc_priv { int (*mmc_is_wp)(int); int (*mmc_cd)(int); struct mxs_dma_desc *desc; + struct mmc_config cfg; /* mmc configuration */ }; #define MXSMMC_MAX_TIMEOUT 10000 @@ -140,7 +141,7 @@ static int mxsmmc_send_cmd_dma(struct mmc *mmc, struct mxsmmc_priv *priv, static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; uint32_t reg; int timeout; @@ -211,7 +212,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) ctrl0 |= SSP_CTRL0_DATA_XFER; reg = data->blocksize * data->blocks; -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK; clrsetbits_le32(&ssp_regs->hw_ssp_cmd0, @@ -219,7 +220,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) | ((ffs(data->blocksize) - 1) << SSP_CMD0_BLOCK_SIZE_OFFSET)); -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) writel(reg, &ssp_regs->hw_ssp_xfer_size); reg = ((data->blocks - 1) << @@ -307,7 +308,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) static void mxsmmc_set_ios(struct mmc *mmc) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; /* Set the clock speed */ @@ -336,7 +337,7 @@ static void mxsmmc_set_ios(struct mmc *mmc) static int mxsmmc_init(struct mmc *mmc) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; /* Reset SSP */ @@ -365,54 +366,49 @@ static int mxsmmc_init(struct mmc *mmc) return 0; } +static const struct mmc_ops mxsmmc_ops = { + .send_cmd = mxsmmc_send_cmd, + .set_ios = mxsmmc_set_ios, + .init = mxsmmc_init, +}; + int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) { - struct mmc *mmc = NULL; - struct mxsmmc_priv *priv = NULL; + struct mmc *mmc; + struct mxsmmc_priv *priv; int ret; const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id); if (!mxs_ssp_bus_id_valid(id)) return -ENODEV; - mmc = calloc(sizeof(struct mmc), 1); - if (!mmc) - return -ENOMEM; - priv = calloc(sizeof(struct mxsmmc_priv), 1); - if (!priv) { - free(mmc); + if (!priv) return -ENOMEM; - } priv->desc = mxs_dma_desc_alloc(); if (!priv->desc) { - free(priv); - free(mmc); - return -ENOMEM; + ret = -ENOMEM; + goto free_priv; } ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id); if (ret) - return ret; + goto free_priv; priv->mmc_is_wp = wp; priv->mmc_cd = cd; priv->id = id; priv->regs = mxs_ssp_regs_by_bus(id); - sprintf(mmc->name, "MXS MMC"); - mmc->send_cmd = mxsmmc_send_cmd; - mmc->set_ios = mxsmmc_set_ios; - mmc->init = mxsmmc_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->priv = priv; + priv->cfg.name = "MXS MMC"; + priv->cfg.ops = &mxsmmc_ops; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | - MMC_MODE_HS_52MHz | MMC_MODE_HS; + priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | + MMC_MODE_HS_52MHz | MMC_MODE_HS | + MMC_MODE_HC; /* * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz @@ -420,10 +416,20 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) * CLOCK_DIVIDE has to be an even value from 2 to 254, and * CLOCK_RATE could be any integer from 0 to 255. */ - mmc->f_min = 400000; - mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; - mmc->b_max = 0x20; - - mmc_register(mmc); + priv->cfg.f_min = 400000; + priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; + priv->cfg.b_max = 0x20; + + mmc = mmc_create(&priv->cfg, priv); + if (mmc == NULL) { + ret = -ENOMEM; + goto free_dma; + } return 0; + +free_dma: + mxs_dma_desc_free(priv->desc); +free_priv: + free(priv); + return ret; } diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 20893217df..813b90946c 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -35,14 +36,25 @@ #include #include +/* simplify defines to OMAP_HSMMC_USE_GPIO */ +#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) +#define OMAP_HSMMC_USE_GPIO +#else +#undef OMAP_HSMMC_USE_GPIO +#endif + /* common definitions for all OMAPs */ #define SYSCTL_SRC (1 << 25) #define SYSCTL_SRD (1 << 26) struct omap_hsmmc_data { struct hsmmc *base_addr; + struct mmc_config cfg; +#ifdef OMAP_HSMMC_USE_GPIO int cd_gpio; int wp_gpio; +#endif }; /* If we fail after 1 second wait, something is really bad */ @@ -51,44 +63,26 @@ struct omap_hsmmc_data { static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); -static struct mmc hsmmc_dev[3]; -static struct omap_hsmmc_data hsmmc_dev_data[3]; -#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) +#ifdef OMAP_HSMMC_USE_GPIO static int omap_mmc_setup_gpio_in(int gpio, const char *label) { - if (!gpio_is_valid(gpio)) - return -1; + int ret; - if (gpio_request(gpio, label) < 0) +#ifndef CONFIG_DM_GPIO + if (!gpio_is_valid(gpio)) return -1; +#endif + ret = gpio_request(gpio, label); + if (ret) + return ret; - if (gpio_direction_input(gpio) < 0) - return -1; + ret = gpio_direction_input(gpio); + if (ret) + return ret; return gpio; } - -static int omap_mmc_getcd(struct mmc *mmc) -{ - int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio; - return gpio_get_value(cd_gpio); -} - -static int omap_mmc_getwp(struct mmc *mmc) -{ - int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio; - return gpio_get_value(wp_gpio); -} -#else -static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) -{ - return -1; -} - -#define omap_mmc_getcd NULL -#define omap_mmc_getwp NULL #endif #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) @@ -140,13 +134,12 @@ static void mmc_board_init(struct mmc *mmc) pbias_lite = readl(&t2_base->pbias_lite); pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); - writel(pbias_lite, &t2_base->pbias_lite); +#ifdef CONFIG_TARGET_OMAP3_CAIRO + /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ + pbias_lite &= ~PBIASLITEVMODE0; #endif -#if defined(CONFIG_TWL4030_POWER) - twl4030_power_mmc_init(); - mdelay(100); /* ramp-up delay from Linux code */ -#endif -#if defined(CONFIG_OMAP34XX) + writel(pbias_lite, &t2_base->pbias_lite); + writel(pbias_lite | PBIASLITEPWRDNZ1 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, &t2_base->pbias_lite); @@ -158,7 +151,7 @@ static void mmc_board_init(struct mmc *mmc) &t2_base->devconf1); /* Change from default of 52MHz to 26MHz if necessary */ - if (!(mmc->host_caps & MMC_MODE_HS_52MHz)) + if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz)) writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, &t2_base->ctl_prog_io1); @@ -214,7 +207,8 @@ void mmc_init_stream(struct hsmmc *mmc_base) writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); } -static int mmc_init_setup(struct mmc *mmc) + +static int omap_hsmmc_init_setup(struct mmc *mmc) { struct omap_hsmmc_data *priv_data = mmc->priv; struct hsmmc *mmc_base = priv_data->base_addr; @@ -295,6 +289,30 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) mmc_reg_out(&mmc_base->sysctl, bit, bit); + /* + * CMD(DAT) lines reset procedures are slightly different + * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). + * According to OMAP3 TRM: + * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it + * returns to 0x0. + * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset + * procedure steps must be as follows: + * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in + * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). + * 2. Poll the SRC(SRD) bit until it is set to 0x1. + * 3. Wait until the SRC (SRD) bit returns to 0x0 + * (reset procedure is completed). + */ +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ + defined(CONFIG_AM33XX) + if (!(readl(&mmc_base->sysctl) & bit)) { + start = get_timer(0); + while (!(readl(&mmc_base->sysctl) & bit)) { + if (get_timer(0) - start > MAX_RETRY_MS) + return; + } + } +#endif start = get_timer(0); while ((readl(&mmc_base->sysctl) & bit) != 0) { if (get_timer(0) - start > MAX_RETRY_MS) @@ -306,7 +324,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) } } -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, +static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct omap_hsmmc_data *priv_data = mmc->priv; @@ -386,6 +404,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } writel(cmd->cmdarg, &mmc_base->arg); + udelay(20); /* To fix "No status update" error on eMMC */ writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); start = get_timer(0); @@ -492,7 +511,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int count; /* - * Start Polled Read + * Start Polled Write */ count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; count /= 4; @@ -540,7 +559,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, return 0; } -static void mmc_set_ios(struct mmc *mmc) +static void omap_hsmmc_set_ios(struct mmc *mmc) { struct omap_hsmmc_data *priv_data = mmc->priv; struct hsmmc *mmc_base = priv_data->base_addr; @@ -596,12 +615,61 @@ static void mmc_set_ios(struct mmc *mmc) writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); } +#ifdef OMAP_HSMMC_USE_GPIO +static int omap_hsmmc_getcd(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv_data = mmc->priv; + int cd_gpio; + + /* if no CD return as 1 */ + cd_gpio = priv_data->cd_gpio; + if (cd_gpio < 0) + return 1; + + /* NOTE: assumes card detect signal is active-low */ + return !gpio_get_value(cd_gpio); +} + +static int omap_hsmmc_getwp(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv_data = mmc->priv; + int wp_gpio; + + /* if no WP return as 0 */ + wp_gpio = priv_data->wp_gpio; + if (wp_gpio < 0) + return 0; + + /* NOTE: assumes write protect signal is active-high */ + return gpio_get_value(wp_gpio); +} +#endif + +static const struct mmc_ops omap_hsmmc_ops = { + .send_cmd = omap_hsmmc_send_cmd, + .set_ios = omap_hsmmc_set_ios, + .init = omap_hsmmc_init_setup, +#ifdef OMAP_HSMMC_USE_GPIO + .getcd = omap_hsmmc_getcd, + .getwp = omap_hsmmc_getwp, +#endif +}; + int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio) { + int ret; struct mmc *mmc; struct omap_hsmmc_data *priv_data; - unsigned long base_addr; + struct mmc_config *cfg; + uint host_caps_val; + + priv_data = calloc(sizeof(*priv_data), 1); + if (priv_data == NULL) + return -ENOMEM; + + host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | + MMC_MODE_HC; switch (dev_index) { case 0: @@ -609,66 +677,75 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, break; #ifdef OMAP_HSMMC2_BASE case 1: - base_addr = OMAP_HSMMC2_BASE; + priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; +#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ + defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \ + defined(CONFIG_HSMMC2_8BIT) + /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ + host_caps_val |= MMC_MODE_8BIT; +#endif break; #endif #ifdef OMAP_HSMMC3_BASE case 2: - base_addr = OMAP_HSMMC3_BASE; + priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; +#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT) + /* Enable 8-bit interface for eMMC on DRA7XX */ + host_caps_val |= MMC_MODE_8BIT; +#endif break; #endif default: printf("Invalid MMC device index: %d\n", dev_index); - return 1; + ret = 1; + goto out; } - - mmc = &hsmmc_dev[dev_index]; - priv_data = &hsmmc_dev_data[dev_index]; - priv_data->base_addr = (void *)base_addr; - - sprintf(mmc->name, "OMAP SD/MMC"); - mmc->send_cmd = mmc_send_cmd; - mmc->set_ios = mmc_set_ios; - mmc->init = mmc_init_setup; - mmc->priv = priv_data; - +#ifdef OMAP_HSMMC_USE_GPIO + /* on error gpio values are set to -1, which is what we want */ priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); - if (priv_data->cd_gpio != -1) - mmc->getcd = omap_mmc_getcd; - priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); - if (priv_data->wp_gpio != -1) - mmc->getwp = omap_mmc_getwp; +#endif + + cfg = &priv_data->cfg; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | - MMC_MODE_HC) & ~host_caps_mask; + cfg->name = "OMAP SD/MMC"; + cfg->ops = &omap_hsmmc_ops; - mmc->f_min = 400000; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->host_caps = host_caps_val & ~host_caps_mask; + + cfg->f_min = 400000; if (f_max != 0) - mmc->f_max = f_max; + cfg->f_max = f_max; else { - if (mmc->host_caps & MMC_MODE_HS) { - if (mmc->host_caps & MMC_MODE_HS_52MHz) - mmc->f_max = 52000000; + if (cfg->host_caps & MMC_MODE_HS) { + if (cfg->host_caps & MMC_MODE_HS_52MHz) + cfg->f_max = 52000000; else - mmc->f_max = 26000000; + cfg->f_max = 26000000; } else - mmc->f_max = 20000000; + cfg->f_max = 20000000; } - mmc->b_max = 0; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; #if defined(CONFIG_OMAP34XX) /* * Silicon revs 2.1 and older do not support multiblock transfers. */ if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) - mmc->b_max = 1; + cfg->b_max = 1; #endif - - mmc_register(mmc); + mmc = mmc_create(cfg, priv_data); + if (mmc == NULL) { + ret = -ENOMEM; + goto out; + } return 0; + +out: + free(priv_data); + return ret; } diff --git a/drivers/mmc/pxa_mmc.h b/drivers/mmc/pxa_mmc.h deleted file mode 100644 index 6fa42686e6..0000000000 --- a/drivers/mmc/pxa_mmc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * linux/drivers/mmc/mmc_pxa.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_PXA_P_H__ -#define __MMC_PXA_P_H__ - -/* PXA-250 MMC controller registers */ - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (0x0001UL) -#define MMC_STRPCL_START_CLK (0x0002UL) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (0x0001UL << 13) -#define MMC_STAT_PRG_DONE (0x0001UL << 12) -#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) -#define MMC_STAT_CLK_EN (0x0001UL << 8) -#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) -#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) -#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) -#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) -#define MMC_STAT_READ_TIME_OUT (0x0001UL) - -#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ - |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ - |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ (0x0000UL) -#define MMC_CLKRT_10MHZ (0x0001UL) -#define MMC_CLKRT_5MHZ (0x0002UL) -#define MMC_CLKRT_2_5MHZ (0x0003UL) -#define MMC_CLKRT_1_25MHZ (0x0004UL) -#define MMC_CLKRT_0_625MHZ (0x0005UL) -#define MMC_CLKRT_0_3125MHZ (0x0006UL) - -/* MMC_SPI */ -#define MMC_SPI_DISABLE (0x00UL) -#define MMC_SPI_EN (0x01UL) -#define MMC_SPI_CS_EN (0x01UL << 2) -#define MMC_SPI_CS_ADDRESS (0x01UL << 3) -#define MMC_SPI_CRC_ON (0x01UL << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (0x0001UL << 8) -#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) -#define MMC_CMDAT_INIT (0x0001UL << 6) -#define MMC_CMDAT_BUSY (0x0001UL << 5) -#define MMC_CMDAT_BCR (0x0003UL << 5) -#define MMC_CMDAT_STREAM (0x0001UL << 4) -#define MMC_CMDAT_BLOCK (0x0000UL << 4) -#define MMC_CMDAT_WRITE (0x0001UL << 3) -#define MMC_CMDAT_READ (0x0000UL << 3) -#define MMC_CMDAT_DATA_EN (0x0001UL << 2) -#define MMC_CMDAT_R0 (0) -#define MMC_CMDAT_R1 (0x0001UL) -#define MMC_CMDAT_R2 (0x0002UL) -#define MMC_CMDAT_R3 (0x0003UL) - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) -#define MMC_PRTBUF_BUF_FULL (0x00UL ) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_MASK_STOP_CMD (0x01UL << 3) -#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) -#define MMC_I_MASK_PRG_DONE (0x01UL << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) -#define MMC_I_MASK_ALL (0x07fUL) - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_REG_STOP_CMD (0x01UL << 3) -#define MMC_I_REG_END_CMD_RES (0x01UL << 2) -#define MMC_I_REG_PRG_DONE (0x01UL << 1) -#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) -#define MMC_I_REG_ALL (0x007fUL) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ -#define CMD(x) (x) - -#define MMC_DEFAULT_RCA 1 - -#define MMC_BLOCK_SIZE 512 -#define MMC_MAX_BLOCK_SIZE 512 - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -#endif /* __MMC_PXA_P_H__ */ diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 29f3eaf30b..25ab0b1fc8 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -52,7 +52,7 @@ struct pxa_mmc_priv { /* Wait for bit to be set */ static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; unsigned int timeout = PXA_MMC_TIMEOUT; @@ -71,7 +71,7 @@ static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) static int pxa_mmc_stop_clock(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; unsigned int timeout = PXA_MMC_TIMEOUT; @@ -100,7 +100,7 @@ static int pxa_mmc_stop_clock(struct mmc *mmc) static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, uint32_t cmdat) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; int ret; @@ -143,7 +143,7 @@ static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t a, b, c; int i; @@ -185,7 +185,7 @@ static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t len; uint32_t *buf = (uint32_t *)data->dest; @@ -197,7 +197,7 @@ static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) while (len) { /* The controller has data ready */ if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) { - size = min(len, PXAMMC_FIFO_SIZE); + size = min(len, (uint32_t)PXAMMC_FIFO_SIZE); len -= size; size /= 4; @@ -221,7 +221,7 @@ static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t len; uint32_t *buf = (uint32_t *)data->src; @@ -233,14 +233,14 @@ static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) while (len) { /* The controller is ready to receive data */ if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) { - size = min(len, PXAMMC_FIFO_SIZE); + size = min(len, (uint32_t)PXAMMC_FIFO_SIZE); len -= size; size /= 4; while (size--) writel(*buf++, ®s->txfifo); - if (min(len, PXAMMC_FIFO_SIZE) < 32) + if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32) writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf); } @@ -264,7 +264,7 @@ static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t cmdat = 0; int ret; @@ -317,7 +317,7 @@ static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, static void pxa_mmc_set_ios(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t tmp; uint32_t pxa_mmc_clock; @@ -335,7 +335,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc) /* Set clock to the card the usual way. */ pxa_mmc_clock = 0; - tmp = mmc->f_max / mmc->clock; + tmp = mmc->cfg->f_max / mmc->clock; tmp += tmp % 2; while (tmp > 1) { @@ -348,7 +348,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc) static int pxa_mmc_init(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; /* Make sure the clock are stopped */ @@ -366,6 +366,22 @@ static int pxa_mmc_init(struct mmc *mmc) return 0; } +static const struct mmc_ops pxa_mmc_ops = { + .send_cmd = pxa_mmc_request, + .set_ios = pxa_mmc_set_ios, + .init = pxa_mmc_init, +}; + +static struct mmc_config pxa_mmc_cfg = { + .name = "PXA MMC", + .ops = &pxa_mmc_ops, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .f_max = PXAMMC_MAX_SPEED, + .f_min = PXAMMC_MIN_SPEED, + .host_caps = PXAMMC_HOST_CAPS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + int pxa_mmc_register(int card_index) { struct mmc *mmc; @@ -373,13 +389,11 @@ int pxa_mmc_register(int card_index) uint32_t reg; int ret = -ENOMEM; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - goto err0; - priv = malloc(sizeof(struct pxa_mmc_priv)); if (!priv) - goto err1; + goto err0; + + memset(priv, 0, sizeof(*priv)); switch (card_index) { case 0: @@ -389,26 +403,12 @@ int pxa_mmc_register(int card_index) priv->regs = (struct pxa_mmc_regs *)MMC1_BASE; break; default: + ret = -EINVAL; printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n", card_index); - goto err2; + goto err1; } - mmc->priv = priv; - - sprintf(mmc->name, "PXA MMC"); - mmc->send_cmd = pxa_mmc_request; - mmc->set_ios = pxa_mmc_set_ios; - mmc->init = pxa_mmc_init; - mmc->getcd = NULL; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = PXAMMC_MAX_SPEED; - mmc->f_min = PXAMMC_MIN_SPEED; - mmc->host_caps = PXAMMC_HOST_CAPS; - - mmc->b_max = 0; - #ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ reg = readl(CKEN); reg |= CKEN12_MMC; @@ -419,14 +419,14 @@ int pxa_mmc_register(int card_index) writel(reg, CKENA); #endif - mmc_register(mmc); + mmc = mmc_create(&pxa_mmc_cfg, priv); + if (mmc == NULL) + goto err1; return 0; -err2: - free(priv); err1: - free(mmc); + free(priv); err0: return ret; } diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c new file mode 100644 index 0000000000..9d0b8bc0c8 --- /dev/null +++ b/drivers/mmc/rpmb.c @@ -0,0 +1,323 @@ +/* + * Copyright 2014, Staubli Faverges + * Pierre Aubert + * + * eMMC- Replay Protected Memory Block + * According to JEDEC Standard No. 84-A441 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "mmc_private.h" + +/* Request codes */ +#define RPMB_REQ_KEY 1 +#define RPMB_REQ_WCOUNTER 2 +#define RPMB_REQ_WRITE_DATA 3 +#define RPMB_REQ_READ_DATA 4 +#define RPMB_REQ_STATUS 5 + +/* Response code */ +#define RPMB_RESP_KEY 0x0100 +#define RPMB_RESP_WCOUNTER 0x0200 +#define RPMB_RESP_WRITE_DATA 0x0300 +#define RPMB_RESP_READ_DATA 0x0400 + +/* Error codes */ +#define RPMB_OK 0 +#define RPMB_ERR_GENERAL 1 +#define RPMB_ERR_AUTH 2 +#define RPMB_ERR_COUNTER 3 +#define RPMB_ERR_ADDRESS 4 +#define RPMB_ERR_WRITE 5 +#define RPMB_ERR_READ 6 +#define RPMB_ERR_KEY 7 +#define RPMB_ERR_CNT_EXPIRED 0x80 +#define RPMB_ERR_MSK 0x7 + +/* Sizes of RPMB data frame */ +#define RPMB_SZ_STUFF 196 +#define RPMB_SZ_MAC 32 +#define RPMB_SZ_DATA 256 +#define RPMB_SZ_NONCE 16 + +#define SHA256_BLOCK_SIZE 64 + +/* Error messages */ +static const char * const rpmb_err_msg[] = { + "", + "General failure", + "Authentication failure", + "Counter failure", + "Address failure", + "Write failure", + "Read failure", + "Authentication key not yet programmed", +}; + + +/* Structure of RPMB data frame. */ +struct s_rpmb { + unsigned char stuff[RPMB_SZ_STUFF]; + unsigned char mac[RPMB_SZ_MAC]; + unsigned char data[RPMB_SZ_DATA]; + unsigned char nonce[RPMB_SZ_NONCE]; + unsigned long write_counter; + unsigned short address; + unsigned short block_count; + unsigned short result; + unsigned short request; +}; + +static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount, + bool is_rel_write) +{ + struct mmc_cmd cmd = {0}; + + cmd.cmdidx = MMC_CMD_SET_BLOCK_COUNT; + cmd.cmdarg = blockcount & 0x0000FFFF; + if (is_rel_write) + cmd.cmdarg |= 1 << 31; + cmd.resp_type = MMC_RSP_R1; + + return mmc_send_cmd(mmc, &cmd, NULL); +} +static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, + unsigned int count, bool is_rel_write) +{ + struct mmc_cmd cmd = {0}; + struct mmc_data data; + int ret; + + ret = mmc_set_blockcount(mmc, count, is_rel_write); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_set_blockcount-> %d\n", __func__, ret); +#endif + return 1; + } + + cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + + data.src = (const char *)s; + data.blocks = 1; + data.blocksize = MMC_MAX_BLOCK_LEN; + data.flags = MMC_DATA_WRITE; + + ret = mmc_send_cmd(mmc, &cmd, &data); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_send_cmd-> %d\n", __func__, ret); +#endif + return 1; + } + return 0; +} +static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, + unsigned short expected) +{ + struct mmc_cmd cmd = {0}; + struct mmc_data data; + int ret; + + ret = mmc_set_blockcount(mmc, 1, false); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_set_blockcount-> %d\n", __func__, ret); +#endif + return -1; + } + cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1; + + data.dest = (char *)s; + data.blocks = 1; + data.blocksize = MMC_MAX_BLOCK_LEN; + data.flags = MMC_DATA_READ; + + ret = mmc_send_cmd(mmc, &cmd, &data); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_send_cmd-> %d\n", __func__, ret); +#endif + return -1; + } + /* Check the response and the status */ + if (be16_to_cpu(s->request) != expected) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:response= %x\n", __func__, + be16_to_cpu(s->request)); +#endif + return -1; + } + ret = be16_to_cpu(s->result); + if (ret) { + printf("%s %s\n", rpmb_err_msg[ret & RPMB_ERR_MSK], + (ret & RPMB_ERR_CNT_EXPIRED) ? + "Write counter has expired" : ""); + } + + /* Return the status of the command */ + return ret; +} +static int mmc_rpmb_status(struct mmc *mmc, unsigned short expected) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_STATUS); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + return -1; + + /* Read the result */ + return mmc_rpmb_response(mmc, rpmb_frame, expected); +} +static void rpmb_hmac(unsigned char *key, unsigned char *buff, int len, + unsigned char *output) +{ + sha256_context ctx; + int i; + unsigned char k_ipad[SHA256_BLOCK_SIZE]; + unsigned char k_opad[SHA256_BLOCK_SIZE]; + + sha256_starts(&ctx); + + /* According to RFC 4634, the HMAC transform looks like: + SHA(K XOR opad, SHA(K XOR ipad, text)) + + where K is an n byte key. + ipad is the byte 0x36 repeated blocksize times + opad is the byte 0x5c repeated blocksize times + and text is the data being protected. + */ + + for (i = 0; i < RPMB_SZ_MAC; i++) { + k_ipad[i] = key[i] ^ 0x36; + k_opad[i] = key[i] ^ 0x5c; + } + /* remaining pad bytes are '\0' XOR'd with ipad and opad values */ + for ( ; i < SHA256_BLOCK_SIZE; i++) { + k_ipad[i] = 0x36; + k_opad[i] = 0x5c; + } + sha256_update(&ctx, k_ipad, SHA256_BLOCK_SIZE); + sha256_update(&ctx, buff, len); + sha256_finish(&ctx, output); + + /* Init context for second pass */ + sha256_starts(&ctx); + + /* start with outer pad */ + sha256_update(&ctx, k_opad, SHA256_BLOCK_SIZE); + + /* then results of 1st hash */ + sha256_update(&ctx, output, RPMB_SZ_MAC); + + /* finish up 2nd pass */ + sha256_finish(&ctx, output); +} +int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *pcounter) +{ + int ret; + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_WCOUNTER); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + return -1; + + /* Read the result */ + ret = mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_WCOUNTER); + if (ret) + return ret; + + *pcounter = be32_to_cpu(rpmb_frame->write_counter); + return 0; +} +int mmc_rpmb_set_key(struct mmc *mmc, void *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_KEY); + memcpy(rpmb_frame->mac, key, RPMB_SZ_MAC); + + if (mmc_rpmb_request(mmc, rpmb_frame, 1, true)) + return -1; + + /* read the operation status */ + return mmc_rpmb_status(mmc, RPMB_RESP_KEY); +} +int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + int i; + + for (i = 0; i < cnt; i++) { + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->address = cpu_to_be16(blk + i); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_READ_DATA); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + break; + + /* Read the result */ + if (mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_READ_DATA)) + break; + + /* Check the HMAC if key is provided */ + if (key) { + unsigned char ret_hmac[RPMB_SZ_MAC]; + + rpmb_hmac(key, rpmb_frame->data, 284, ret_hmac); + if (memcmp(ret_hmac, rpmb_frame->mac, RPMB_SZ_MAC)) { + printf("MAC error on block #%d\n", i); + break; + } + } + /* Copy data */ + memcpy(addr + i * RPMB_SZ_DATA, rpmb_frame->data, RPMB_SZ_DATA); + } + return i; +} +int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + unsigned long wcount; + int i; + + for (i = 0; i < cnt; i++) { + if (mmc_rpmb_get_counter(mmc, &wcount)) { + printf("Cannot read RPMB write counter\n"); + break; + } + + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + memcpy(rpmb_frame->data, addr + i * RPMB_SZ_DATA, RPMB_SZ_DATA); + rpmb_frame->address = cpu_to_be16(blk + i); + rpmb_frame->block_count = cpu_to_be16(1); + rpmb_frame->write_counter = cpu_to_be32(wcount); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_WRITE_DATA); + /* Computes HMAC */ + rpmb_hmac(key, rpmb_frame->data, 284, rpmb_frame->mac); + + if (mmc_rpmb_request(mmc, rpmb_frame, 1, true)) + break; + + /* Get status */ + if (mmc_rpmb_status(mmc, RPMB_RESP_WRITE_DATA)) + break; + } + return i; +} diff --git a/drivers/mmc/s3c_sdi.c b/drivers/mmc/s3c_sdi.c new file mode 100644 index 0000000000..1b5b70512d --- /dev/null +++ b/drivers/mmc/s3c_sdi.c @@ -0,0 +1,321 @@ +/* + * S3C24xx SD/MMC driver + * + * Based on OpenMoko S3C24xx driver by Harald Welte + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define S3C2440_SDICON_SDRESET (1 << 8) +#define S3C2410_SDICON_FIFORESET (1 << 1) +#define S3C2410_SDICON_CLOCKTYPE (1 << 0) + +#define S3C2410_SDICMDCON_LONGRSP (1 << 10) +#define S3C2410_SDICMDCON_WAITRSP (1 << 9) +#define S3C2410_SDICMDCON_CMDSTART (1 << 8) +#define S3C2410_SDICMDCON_SENDERHOST (1 << 6) +#define S3C2410_SDICMDCON_INDEX 0x3f + +#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12) +#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11) +#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10) +#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9) + +#define S3C2440_SDIDCON_DS_WORD (2 << 22) +#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20) +#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19) +#define S3C2410_SDIDCON_BLOCKMODE (1 << 17) +#define S3C2410_SDIDCON_WIDEBUS (1 << 16) +#define S3C2440_SDIDCON_DATSTART (1 << 14) +#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12) +#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12) +#define S3C2410_SDIDCON_BLKNUM 0x7ff + +#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8) +#define S3C2410_SDIDSTA_CRCFAIL (1 << 7) +#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6) +#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5) +#define S3C2410_SDIDSTA_XFERFINISH (1 << 4) + +#define S3C2410_SDIFSTA_TFHALF (1 << 11) +#define S3C2410_SDIFSTA_COUNTMASK 0x7f + +/* + * WARNING: We only support one SD IP block. + * NOTE: It's not likely there will ever exist an S3C24xx with two, + * at least not in this universe all right. + */ +static int wide_bus; + +static int +s3cmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi(); + uint32_t sdiccon, sdicsta, sdidcon, sdidsta, sdidat, sdifsta; + uint32_t sdicsta_wait_bit = S3C2410_SDICMDSTAT_CMDSENT; + unsigned int timeout = 100000; + int ret = 0, xfer_len, data_offset = 0; + const uint32_t sdidsta_err_mask = S3C2410_SDIDSTA_FIFOFAIL | + S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL | + S3C2410_SDIDSTA_DATATIMEOUT; + + + writel(0xffffffff, &sdi_regs->sdicsta); + writel(0xffffffff, &sdi_regs->sdidsta); + writel(0xffffffff, &sdi_regs->sdifsta); + + /* Set up data transfer (if applicable). */ + if (data) { + writel(data->blocksize, &sdi_regs->sdibsize); + + sdidcon = data->blocks & S3C2410_SDIDCON_BLKNUM; + sdidcon |= S3C2410_SDIDCON_BLOCKMODE; +#if defined(CONFIG_S3C2440) + sdidcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART; +#endif + if (wide_bus) + sdidcon |= S3C2410_SDIDCON_WIDEBUS; + + if (data->flags & MMC_DATA_READ) { + sdidcon |= S3C2410_SDIDCON_RXAFTERCMD; + sdidcon |= S3C2410_SDIDCON_XFER_RXSTART; + } else { + sdidcon |= S3C2410_SDIDCON_TXAFTERRESP; + sdidcon |= S3C2410_SDIDCON_XFER_TXSTART; + } + + writel(sdidcon, &sdi_regs->sdidcon); + } + + /* Write CMD arg. */ + writel(cmd->cmdarg, &sdi_regs->sdicarg); + + /* Write CMD index. */ + sdiccon = cmd->cmdidx & S3C2410_SDICMDCON_INDEX; + sdiccon |= S3C2410_SDICMDCON_SENDERHOST; + sdiccon |= S3C2410_SDICMDCON_CMDSTART; + + /* Command with short response. */ + if (cmd->resp_type & MMC_RSP_PRESENT) { + sdiccon |= S3C2410_SDICMDCON_WAITRSP; + sdicsta_wait_bit = S3C2410_SDICMDSTAT_RSPFIN; + } + + /* Command with long response. */ + if (cmd->resp_type & MMC_RSP_136) + sdiccon |= S3C2410_SDICMDCON_LONGRSP; + + /* Start the command. */ + writel(sdiccon, &sdi_regs->sdiccon); + + /* Wait for the command to complete or for response. */ + for (timeout = 100000; timeout; timeout--) { + sdicsta = readl(&sdi_regs->sdicsta); + if (sdicsta & sdicsta_wait_bit) + break; + + if (sdicsta & S3C2410_SDICMDSTAT_CMDTIMEOUT) + timeout = 1; + } + + /* Clean the status bits. */ + setbits_le32(&sdi_regs->sdicsta, 0xf << 9); + + if (!timeout) { + puts("S3C SDI: Command timed out!\n"); + ret = TIMEOUT; + goto error; + } + + /* Read out the response. */ + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = readl(&sdi_regs->sdirsp0); + cmd->response[1] = readl(&sdi_regs->sdirsp1); + cmd->response[2] = readl(&sdi_regs->sdirsp2); + cmd->response[3] = readl(&sdi_regs->sdirsp3); + } else { + cmd->response[0] = readl(&sdi_regs->sdirsp0); + } + + /* If there are no data, we're done. */ + if (!data) + return 0; + + xfer_len = data->blocksize * data->blocks; + + while (xfer_len > 0) { + sdidsta = readl(&sdi_regs->sdidsta); + sdifsta = readl(&sdi_regs->sdifsta); + + if (sdidsta & sdidsta_err_mask) { + printf("S3C SDI: Data error (sdta=0x%08x)\n", sdidsta); + ret = -EIO; + goto error; + } + + if (data->flags & MMC_DATA_READ) { + if ((sdifsta & S3C2410_SDIFSTA_COUNTMASK) < 4) + continue; + sdidat = readl(&sdi_regs->sdidat); + put_unaligned_le32(sdidat, data->dest + data_offset); + } else { /* Write */ + /* TX FIFO half full. */ + if (!(sdifsta & S3C2410_SDIFSTA_TFHALF)) + continue; + + /* TX FIFO is below 32b full, write. */ + sdidat = get_unaligned_le32(data->src + data_offset); + writel(sdidat, &sdi_regs->sdidat); + } + data_offset += 4; + xfer_len -= 4; + } + + /* Wait for the command to complete or for response. */ + for (timeout = 100000; timeout; timeout--) { + sdidsta = readl(&sdi_regs->sdidsta); + if (sdidsta & S3C2410_SDIDSTA_XFERFINISH) + break; + + if (sdidsta & S3C2410_SDIDSTA_DATATIMEOUT) + timeout = 1; + } + + /* Clear status bits. */ + writel(0x6f8, &sdi_regs->sdidsta); + + if (!timeout) { + puts("S3C SDI: Command timed out!\n"); + ret = TIMEOUT; + goto error; + } + + writel(0, &sdi_regs->sdidcon); + + return 0; +error: + return ret; +} + +static void s3cmmc_set_ios(struct mmc *mmc) +{ + struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi(); + uint32_t divider = 0; + + wide_bus = (mmc->bus_width == 4); + + if (!mmc->clock) + return; + + divider = DIV_ROUND_UP(get_PCLK(), mmc->clock); + if (divider) + divider--; + + writel(divider, &sdi_regs->sdipre); + mdelay(125); +} + +static int s3cmmc_init(struct mmc *mmc) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi(); + + /* Start the clock. */ + setbits_le32(&clk_power->clkcon, 1 << 9); + +#if defined(CONFIG_S3C2440) + writel(S3C2440_SDICON_SDRESET, &sdi_regs->sdicon); + mdelay(10); + writel(0x7fffff, &sdi_regs->sdidtimer); +#else + writel(0xffff, &sdi_regs->sdidtimer); +#endif + writel(MMC_MAX_BLOCK_LEN, &sdi_regs->sdibsize); + writel(0x0, &sdi_regs->sdiimsk); + + writel(S3C2410_SDICON_FIFORESET | S3C2410_SDICON_CLOCKTYPE, + &sdi_regs->sdicon); + + mdelay(125); + + return 0; +} + +struct s3cmmc_priv { + struct mmc_config cfg; + int (*getcd)(struct mmc *); + int (*getwp)(struct mmc *); +}; + +static int s3cmmc_getcd(struct mmc *mmc) +{ + struct s3cmmc_priv *priv = mmc->priv; + if (priv->getcd) + return priv->getcd(mmc); + else + return 0; +} + +static int s3cmmc_getwp(struct mmc *mmc) +{ + struct s3cmmc_priv *priv = mmc->priv; + if (priv->getwp) + return priv->getwp(mmc); + else + return 0; +} + +static const struct mmc_ops s3cmmc_ops = { + .send_cmd = s3cmmc_send_cmd, + .set_ios = s3cmmc_set_ios, + .init = s3cmmc_init, + .getcd = s3cmmc_getcd, + .getwp = s3cmmc_getwp, +}; + +int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *), + int (*getwp)(struct mmc *)) +{ + struct s3cmmc_priv *priv; + struct mmc *mmc; + struct mmc_config *cfg; + + priv = calloc(1, sizeof(*priv)); + if (!priv) + return -ENOMEM; + cfg = &priv->cfg; + + cfg->name = "S3C MMC"; + cfg->ops = &s3cmmc_ops; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS; + cfg->f_min = 400000; + cfg->f_max = get_PCLK() / 2; + cfg->b_max = 0x80; + +#if defined(CONFIG_S3C2410) + /* + * S3C2410 has some bug that prevents reliable + * operation at higher speed + */ + cfg->f_max /= 2; +#endif + + mmc = mmc_create(cfg, priv); + if (!mmc) { + free(priv); + return -ENOMEM; + } + + return 0; +} diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 7f89403b43..3899372e0e 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -8,8 +8,13 @@ #include #include #include +#include +#include +#include #include #include +#include +#include static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) @@ -58,29 +63,146 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) sdhci_writel(host, ctrl, SDHCI_CONTROL2); } -int s5p_sdhci_init(u32 regbase, int index, int bus_width) +static int s5p_sdhci_core_init(struct sdhci_host *host) { - struct sdhci_host *host = NULL; - host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); - if (!host) { - printf("sdhci__host malloc fail!\n"); - return 1; - } - host->name = S5P_NAME; - host->ioaddr = (void *)regbase; host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | - SDHCI_QUIRK_WAIT_SEND_CMD; + SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->set_control_reg = &s5p_sdhci_set_control_reg; host->set_clock = set_mmc_clk; - host->index = index; host->host_caps = MMC_MODE_HC; + if (host->bus_width == 8) + host->host_caps |= MMC_MODE_8BIT; return add_sdhci(host, 52000000, 400000); } + +int s5p_sdhci_init(u32 regbase, int index, int bus_width) +{ + struct sdhci_host *host = malloc(sizeof(struct sdhci_host)); + if (!host) { + printf("sdhci__host malloc fail!\n"); + return 1; + } + host->ioaddr = (void *)regbase; + host->index = index; + host->bus_width = bus_width; + + return s5p_sdhci_core_init(host); +} + +#ifdef CONFIG_OF_CONTROL +struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; + +static int do_sdhci_init(struct sdhci_host *host) +{ + int dev_id, flag; + int err = 0; + + flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + dev_id = host->index + PERIPH_ID_SDMMC0; + + if (dm_gpio_is_valid(&host->pwr_gpio)) { + dm_gpio_set_value(&host->pwr_gpio, 1); + err = exynos_pinmux_config(dev_id, flag); + if (err) { + debug("MMC not configured\n"); + return err; + } + } + + if (dm_gpio_is_valid(&host->cd_gpio)) { + if (dm_gpio_get_value(&host->cd_gpio)) + return -ENODEV; + + err = exynos_pinmux_config(dev_id, flag); + if (err) { + printf("external SD not configured\n"); + return err; + } + } + + return s5p_sdhci_core_init(host); +} + +static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) +{ + int bus_width, dev_id; + unsigned int base; + + /* Get device id */ + dev_id = pinmux_decode_periph_id(blob, node); + if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) { + debug("MMC: Can't get device id\n"); + return -1; + } + host->index = dev_id - PERIPH_ID_SDMMC0; + + /* Get bus width */ + bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (bus_width <= 0) { + debug("MMC: Can't get bus-width\n"); + return -1; + } + host->bus_width = bus_width; + + /* Get the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("MMC: Can't get base address\n"); + return -1; + } + host->ioaddr = (void *)base; + + gpio_request_by_name_nodev(blob, node, "pwr-gpios", 0, &host->pwr_gpio, + GPIOD_IS_OUT); + gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio, + GPIOD_IS_IN); + + return 0; +} + +static int process_nodes(const void *blob, int node_list[], int count) +{ + struct sdhci_host *host; + int i, node; + + debug("%s: count = %d\n", __func__, count); + + /* build sdhci_host[] for each controller */ + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) + continue; + + host = &sdhci_host[i]; + + if (sdhci_get_config(blob, node, host)) { + printf("%s: failed to decode dev %d\n", __func__, i); + return -1; + } + do_sdhci_init(host); + } + return 0; +} + +int exynos_mmc_init(const void *blob) +{ + int count; + int node_list[SDHCI_MAX_HOSTS]; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + COMPAT_SAMSUNG_EXYNOS_MMC, node_list, + SDHCI_MAX_HOSTS); + + process_nodes(blob, node_list, count); + + return 1; +} +#endif diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 42619916e5..de88e19609 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -24,7 +24,8 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { if (timeout == 0) { - printf("Reset 0x%x never completed.\n", (int)mask); + printf("%s: Reset 0x%x never completed.\n", + __func__, (int)mask); return; } timeout--; @@ -68,10 +69,9 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, unsigned int stat, rdy, mask, timeout, block = 0; #ifdef CONFIG_MMC_SDMA unsigned char ctrl; - ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL); + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); ctrl &= ~SDHCI_CTRL_DMA_MASK; - ctrl |= SDHCI_CTRL_SDMA; - sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL); + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); #endif timeout = 1000000; @@ -80,7 +80,8 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) { - printf("Error detected in status(0x%X)!\n", stat); + printf("%s: Error detected in status(0x%X)!\n", + __func__, stat); return -1; } if (stat & rdy) { @@ -103,26 +104,40 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, if (timeout-- > 0) udelay(10); else { - printf("Transfer data timeout\n"); + printf("%s: Transfer data timeout\n", __func__); return -1; } } while (!(stat & SDHCI_INT_DATA_END)); return 0; } -int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, +/* + * No command will be sent by driver if card is busy, so driver must wait + * for card ready state. + * Every time when card is busy after timeout then (last) timeout value will be + * increased twice but only if it doesn't exceed global defined maximum. + * Each function call will use last timeout value. Max timeout can be redefined + * in board config file. + */ +#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT +#define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 +#endif +#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 + +static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; unsigned int stat = 0; int ret = 0; int trans_bytes = 0, is_aligned = 1; u32 mask, flags, mode; - unsigned int timeout, start_addr = 0; + unsigned int time = 0, start_addr = 0; unsigned int retry = 10000; + int mmc_dev = mmc->block_dev.dev; - /* Wait max 10 ms */ - timeout = 10; + /* Timeout unit - ms */ + static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; @@ -133,11 +148,18 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, mask &= ~SDHCI_DATA_INHIBIT; while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { - if (timeout == 0) { - printf("Controller never released inhibit bit(s).\n"); - return COMM_ERR; + if (time >= cmd_timeout) { + printf("%s: MMC: %d busy ", __func__, mmc_dev); + if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) { + cmd_timeout += cmd_timeout; + printf("timeout increasing to: %u ms.\n", + cmd_timeout); + } else { + puts("timeout.\n"); + return COMM_ERR; + } } - timeout--; + time++; udelay(1000); } @@ -159,7 +181,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (data) flags |= SDHCI_CMD_DATA; - /*Set Transfer mode regarding to data flag*/ + /* Set Transfer mode regarding to data flag */ if (data != 0) { sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); mode = SDHCI_TRNS_BLK_CNT_EN; @@ -210,7 +232,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) return 0; else { - printf("Timeout for status update!\n"); + printf("%s: Timeout for status update!\n", __func__); return TIMEOUT; } } @@ -246,7 +268,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; unsigned int div, clk, timeout; sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); @@ -254,20 +276,20 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (clock == 0) return 0; - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) { + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { /* Version 3.00 divisors must be a multiple of 2. */ - if (mmc->f_max <= clock) + if (mmc->cfg->f_max <= clock) div = 1; else { for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { - if ((mmc->f_max / div) <= clock) + if ((mmc->cfg->f_max / div) <= clock) break; } } } else { /* Version 2.00 divisors must be a power of 2. */ for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { - if ((mmc->f_max / div) <= clock) + if ((mmc->cfg->f_max / div) <= clock) break; } } @@ -287,7 +309,8 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & SDHCI_CLOCK_INT_STABLE)) { if (timeout == 0) { - printf("Internal clock never stabilised.\n"); + printf("%s: Internal clock never stabilised.\n", + __func__); return -1; } timeout--; @@ -332,10 +355,10 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); } -void sdhci_set_ios(struct mmc *mmc) +static void sdhci_set_ios(struct mmc *mmc) { u32 ctrl; - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; if (host->set_control_reg) host->set_control_reg(host); @@ -347,10 +370,11 @@ void sdhci_set_ios(struct mmc *mmc) ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); if (mmc->bus_width == 8) { ctrl &= ~SDHCI_CTRL_4BITBUS; - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || + (host->quirks & SDHCI_QUIRK_USE_WIDE8)) ctrl |= SDHCI_CTRL_8BITBUS; } else { - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ctrl &= ~SDHCI_CTRL_8BITBUS; if (mmc->bus_width == 4) ctrl |= SDHCI_CTRL_4BITBUS; @@ -369,19 +393,20 @@ void sdhci_set_ios(struct mmc *mmc) sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); } -int sdhci_init(struct mmc *mmc) +static int sdhci_init(struct mmc *mmc) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { aligned_buffer = memalign(8, 512*1024); if (!aligned_buffer) { - printf("Aligned buffer alloc failed!!!"); + printf("%s: Aligned buffer alloc failed!!!\n", + __func__); return -1; } } - sdhci_set_power(host, fls(mmc->voltages) - 1); + sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); if (host->quirks & SDHCI_QUIRK_NO_CD) { unsigned int status; @@ -397,88 +422,92 @@ int sdhci_init(struct mmc *mmc) } /* Enable only interrupts served by the SD controller */ - sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK - , SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, + SDHCI_INT_ENABLE); /* Mask all sdhci interrupt sources */ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); return 0; } + +static const struct mmc_ops sdhci_ops = { + .send_cmd = sdhci_send_command, + .set_ios = sdhci_set_ios, + .init = sdhci_init, +}; + int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) { - struct mmc *mmc; unsigned int caps; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) { - printf("mmc malloc fail!\n"); - return -1; - } - - mmc->priv = host; - host->mmc = mmc; - - sprintf(mmc->name, "%s", host->name); - mmc->send_cmd = sdhci_send_command; - mmc->set_ios = sdhci_set_ios; - mmc->init = sdhci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; + host->cfg.name = host->name; + host->cfg.ops = &sdhci_ops; caps = sdhci_readl(host, SDHCI_CAPABILITIES); #ifdef CONFIG_MMC_SDMA if (!(caps & SDHCI_CAN_DO_SDMA)) { - printf("Your controller don't support sdma!!\n"); + printf("%s: Your controller doesn't support SDMA!!\n", + __func__); return -1; } #endif if (max_clk) - mmc->f_max = max_clk; + host->cfg.f_max = max_clk; else { - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) - mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) + host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; else - mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK) + host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; - mmc->f_max *= 1000000; + host->cfg.f_max *= 1000000; } - if (mmc->f_max == 0) { - printf("Hardware doesn't specify base clock frequency\n"); + if (host->cfg.f_max == 0) { + printf("%s: Hardware doesn't specify base clock frequency\n", + __func__); return -1; } if (min_clk) - mmc->f_min = min_clk; + host->cfg.f_min = min_clk; else { - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) - mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) + host->cfg.f_min = host->cfg.f_max / + SDHCI_MAX_DIV_SPEC_300; else - mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; + host->cfg.f_min = host->cfg.f_max / + SDHCI_MAX_DIV_SPEC_200; } - mmc->voltages = 0; + host->cfg.voltages = 0; if (caps & SDHCI_CAN_VDD_330) - mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; + host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; if (caps & SDHCI_CAN_VDD_300) - mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; if (caps & SDHCI_CAN_VDD_180) - mmc->voltages |= MMC_VDD_165_195; + host->cfg.voltages |= MMC_VDD_165_195; if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) - mmc->voltages |= host->voltages; + host->cfg.voltages |= host->voltages; - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) { + host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { if (caps & SDHCI_CAN_DO_8BIT) - mmc->host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; } if (host->host_caps) - mmc->host_caps |= host->host_caps; + host->cfg.host_caps |= host->host_caps; + + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; sdhci_reset(host, SDHCI_RESET_ALL); - mmc_register(mmc); + + host->mmc = mmc_create(&host->cfg, host); + if (host->mmc == NULL) { + printf("%s: mmc create fail!\n", __func__); + return -1; + } return 0; } diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 011d4f3e63..76ba93b81d 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -20,11 +20,6 @@ #define DRIVER_NAME "sh_mmcif" -static void *mmc_priv(struct mmc *mmc) -{ - return (void *)mmc->priv; -} - static int sh_mmcif_intr(void *dev_id) { struct sh_mmcif_host *host = dev_id; @@ -108,20 +103,18 @@ static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host) static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) { - int i; - sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); if (!clk) return; - if (clk == CLKDEV_EMMC_DATA) { + + if (clk == CLKDEV_EMMC_DATA) sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); - } else { - for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++) - ; - sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl); - } + else + sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk, + clk) - 1) - 1) << 16, + &host->regs->ce_clk_ctrl); sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); } @@ -522,7 +515,7 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; int ret; WATCHDOG_RESET(); @@ -550,7 +543,7 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, static void sh_mmcif_set_ios(struct mmc *mmc) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; if (mmc->clock) sh_mmcif_clock_control(host, mmc->clock); @@ -567,44 +560,49 @@ static void sh_mmcif_set_ios(struct mmc *mmc) static int sh_mmcif_init(struct mmc *mmc) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; sh_mmcif_sync_reset(host); sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); return 0; } +static const struct mmc_ops sh_mmcif_ops = { + .send_cmd = sh_mmcif_request, + .set_ios = sh_mmcif_set_ios, + .init = sh_mmcif_init, +}; + +static struct mmc_config sh_mmcif_cfg = { + .name = DRIVER_NAME, + .ops = &sh_mmcif_ops, + .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | + MMC_MODE_8BIT | MMC_MODE_HC, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + int mmcif_mmc_init(void) { - int ret = 0; struct mmc *mmc; struct sh_mmcif_host *host = NULL; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - ret = -ENOMEM; - memset(mmc, 0, sizeof(*mmc)); host = malloc(sizeof(struct sh_mmcif_host)); if (!host) - ret = -ENOMEM; + return -ENOMEM; memset(host, 0, sizeof(*host)); - mmc->f_min = CLKDEV_MMC_INIT; - mmc->f_max = CLKDEV_EMMC_DATA; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | - MMC_MODE_8BIT | MMC_MODE_HC; - memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME)); - mmc->send_cmd = sh_mmcif_request; - mmc->set_ios = sh_mmcif_set_ios; - mmc->init = sh_mmcif_init; - mmc->getcd = NULL; - mmc->getwp = NULL; host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; host->clk = CONFIG_SH_MMCIF_CLK; - mmc->priv = host; - mmc_register(mmc); + sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk); + sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk); - return ret; + mmc = mmc_create(&sh_mmcif_cfg, host); + if (mmc == NULL) { + free(host); + return -ENOMEM; + } + + return 0; } diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h index bd6fbf7c62..4b6752f7f9 100644 --- a/drivers/mmc/sh_mmcif.h +++ b/drivers/mmc/sh_mmcif.h @@ -199,7 +199,13 @@ struct sh_mmcif_regs { #define SOFT_RST_OFF (0 << 31) #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ -#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */ +#ifdef CONFIG_RMOBILE +#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9)) +#define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1)) +#else +#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8)) +#define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA +#endif #define MMC_BUS_WIDTH_1 0 #define MMC_BUS_WIDTH_4 2 diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c new file mode 100644 index 0000000000..cc62c89a25 --- /dev/null +++ b/drivers/mmc/sh_sdhi.c @@ -0,0 +1,695 @@ +/* + * drivers/mmc/sh_sdhi.c + * + * SD/MMC driver for Renesas rmobile ARM SoCs. + * + * Copyright (C) 2011,2013-2014 Renesas Electronics Corporation + * Copyright (C) 2014 Nobuhiro Iwamatsu + * Copyright (C) 2008-2009 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "sh-sdhi" + +struct sh_sdhi_host { + unsigned long addr; + int ch; + int bus_shift; + unsigned long quirks; + unsigned char wait_int; + unsigned char sd_error; + unsigned char detect_waiting; +}; +static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val) +{ + writew(val, host->addr + (reg << host->bus_shift)); +} + +static inline u16 sh_sdhi_readw(struct sh_sdhi_host *host, int reg) +{ + return readw(host->addr + (reg << host->bus_shift)); +} + +static void *mmc_priv(struct mmc *mmc) +{ + return (void *)mmc->priv; +} + +static void sh_sdhi_detect(struct sh_sdhi_host *host) +{ + sh_sdhi_writew(host, SDHI_OPTION, + OPT_BUS_WIDTH_1 | sh_sdhi_readw(host, SDHI_OPTION)); + + host->detect_waiting = 0; +} + +static int sh_sdhi_intr(void *dev_id) +{ + struct sh_sdhi_host *host = dev_id; + int state1 = 0, state2 = 0; + + state1 = sh_sdhi_readw(host, SDHI_INFO1); + state2 = sh_sdhi_readw(host, SDHI_INFO2); + + debug("%s: state1 = %x, state2 = %x\n", __func__, state1, state2); + + /* CARD Insert */ + if (state1 & INFO1_CARD_IN) { + sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_IN); + if (!host->detect_waiting) { + host->detect_waiting = 1; + sh_sdhi_detect(host); + } + sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END | + INFO1M_ACCESS_END | INFO1M_CARD_IN | + INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); + return -EAGAIN; + } + /* CARD Removal */ + if (state1 & INFO1_CARD_RE) { + sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_RE); + if (!host->detect_waiting) { + host->detect_waiting = 1; + sh_sdhi_detect(host); + } + sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END | + INFO1M_ACCESS_END | INFO1M_CARD_RE | + INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); + sh_sdhi_writew(host, SDHI_SDIO_INFO1_MASK, SDIO_INFO1M_ON); + sh_sdhi_writew(host, SDHI_SDIO_MODE, SDIO_MODE_OFF); + return -EAGAIN; + } + + if (state2 & INFO2_ALL_ERR) { + sh_sdhi_writew(host, SDHI_INFO2, + (unsigned short)~(INFO2_ALL_ERR)); + sh_sdhi_writew(host, SDHI_INFO2_MASK, + INFO2M_ALL_ERR | + sh_sdhi_readw(host, SDHI_INFO2_MASK)); + host->sd_error = 1; + host->wait_int = 1; + return 0; + } + /* Respons End */ + if (state1 & INFO1_RESP_END) { + sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END); + sh_sdhi_writew(host, SDHI_INFO1_MASK, + INFO1M_RESP_END | + sh_sdhi_readw(host, SDHI_INFO1_MASK)); + host->wait_int = 1; + return 0; + } + /* SD_BUF Read Enable */ + if (state2 & INFO2_BRE_ENABLE) { + sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BRE_ENABLE); + sh_sdhi_writew(host, SDHI_INFO2_MASK, + INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ | + sh_sdhi_readw(host, SDHI_INFO2_MASK)); + host->wait_int = 1; + return 0; + } + /* SD_BUF Write Enable */ + if (state2 & INFO2_BWE_ENABLE) { + sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BWE_ENABLE); + sh_sdhi_writew(host, SDHI_INFO2_MASK, + INFO2_BWE_ENABLE | INFO2M_BUF_ILL_WRITE | + sh_sdhi_readw(host, SDHI_INFO2_MASK)); + host->wait_int = 1; + return 0; + } + /* Access End */ + if (state1 & INFO1_ACCESS_END) { + sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_ACCESS_END); + sh_sdhi_writew(host, SDHI_INFO1_MASK, + INFO1_ACCESS_END | + sh_sdhi_readw(host, SDHI_INFO1_MASK)); + host->wait_int = 1; + return 0; + } + return -EAGAIN; +} + +static int sh_sdhi_wait_interrupt_flag(struct sh_sdhi_host *host) +{ + int timeout = 10000000; + + while (1) { + timeout--; + if (timeout < 0) { + debug(DRIVER_NAME": %s timeout\n", __func__); + return 0; + } + + if (!sh_sdhi_intr(host)) + break; + + udelay(1); /* 1 usec */ + } + + return 1; /* Return value: NOT 0 = complete waiting */ +} + +static int sh_sdhi_clock_control(struct sh_sdhi_host *host, unsigned long clk) +{ + u32 clkdiv, i, timeout; + + if (sh_sdhi_readw(host, SDHI_INFO2) & (1 << 14)) { + printf(DRIVER_NAME": Busy state ! Cannot change the clock\n"); + return -EBUSY; + } + + sh_sdhi_writew(host, SDHI_CLK_CTRL, + ~CLK_ENABLE & sh_sdhi_readw(host, SDHI_CLK_CTRL)); + + if (clk == 0) + return -EIO; + + clkdiv = 0x80; + i = CONFIG_SH_SDHI_FREQ >> (0x8 + 1); + for (; clkdiv && clk >= (i << 1); (clkdiv >>= 1)) + i <<= 1; + + sh_sdhi_writew(host, SDHI_CLK_CTRL, clkdiv); + + timeout = 100000; + /* Waiting for SD Bus busy to be cleared */ + while (timeout--) { + if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000)) + break; + } + + if (timeout) + sh_sdhi_writew(host, SDHI_CLK_CTRL, + CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL)); + else + return -EBUSY; + + return 0; +} + +static int sh_sdhi_sync_reset(struct sh_sdhi_host *host) +{ + u32 timeout; + sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_ON); + sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_OFF); + sh_sdhi_writew(host, SDHI_CLK_CTRL, + CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL)); + + timeout = 100000; + while (timeout--) { + if (!(sh_sdhi_readw(host, SDHI_INFO2) & INFO2_CBUSY)) + break; + udelay(100); + } + + if (!timeout) + return -EBUSY; + + if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF) + sh_sdhi_writew(host, SDHI_HOST_MODE, 1); + + return 0; +} + +static int sh_sdhi_error_manage(struct sh_sdhi_host *host) +{ + unsigned short e_state1, e_state2; + int ret; + + host->sd_error = 0; + host->wait_int = 0; + + e_state1 = sh_sdhi_readw(host, SDHI_ERR_STS1); + e_state2 = sh_sdhi_readw(host, SDHI_ERR_STS2); + if (e_state2 & ERR_STS2_SYS_ERROR) { + if (e_state2 & ERR_STS2_RES_STOP_TIMEOUT) + ret = TIMEOUT; + else + ret = -EILSEQ; + debug("%s: ERR_STS2 = %04x\n", + DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS2)); + sh_sdhi_sync_reset(host); + + sh_sdhi_writew(host, SDHI_INFO1_MASK, + INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); + return ret; + } + if (e_state1 & ERR_STS1_CRC_ERROR || e_state1 & ERR_STS1_CMD_ERROR) + ret = -EILSEQ; + else + ret = TIMEOUT; + + debug("%s: ERR_STS1 = %04x\n", + DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS1)); + sh_sdhi_sync_reset(host); + sh_sdhi_writew(host, SDHI_INFO1_MASK, + INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); + return ret; +} + +static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data) +{ + long time; + unsigned short blocksize, i; + unsigned short *p = (unsigned short *)data->dest; + + if ((unsigned long)p & 0x00000001) { + debug(DRIVER_NAME": %s: The data pointer is unaligned.", + __func__); + return -EIO; + } + + host->wait_int = 0; + sh_sdhi_writew(host, SDHI_INFO2_MASK, + ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) & + sh_sdhi_readw(host, SDHI_INFO2_MASK)); + sh_sdhi_writew(host, SDHI_INFO1_MASK, + ~INFO1M_ACCESS_END & + sh_sdhi_readw(host, SDHI_INFO1_MASK)); + time = sh_sdhi_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_sdhi_error_manage(host); + + host->wait_int = 0; + blocksize = sh_sdhi_readw(host, SDHI_SIZE); + for (i = 0; i < blocksize / 2; i++) + *p++ = sh_sdhi_readw(host, SDHI_BUF0); + + time = sh_sdhi_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_sdhi_error_manage(host); + + host->wait_int = 0; + return 0; +} + +static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data) +{ + long time; + unsigned short blocksize, i, sec; + unsigned short *p = (unsigned short *)data->dest; + + if ((unsigned long)p & 0x00000001) { + debug(DRIVER_NAME": %s: The data pointer is unaligned.", + __func__); + return -EIO; + } + + debug("%s: blocks = %d, blocksize = %d\n", + __func__, data->blocks, data->blocksize); + + host->wait_int = 0; + for (sec = 0; sec < data->blocks; sec++) { + sh_sdhi_writew(host, SDHI_INFO2_MASK, + ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) & + sh_sdhi_readw(host, SDHI_INFO2_MASK)); + + time = sh_sdhi_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_sdhi_error_manage(host); + + host->wait_int = 0; + blocksize = sh_sdhi_readw(host, SDHI_SIZE); + for (i = 0; i < blocksize / 2; i++) + *p++ = sh_sdhi_readw(host, SDHI_BUF0); + } + + return 0; +} + +static int sh_sdhi_single_write(struct sh_sdhi_host *host, + struct mmc_data *data) +{ + long time; + unsigned short blocksize, i; + const unsigned short *p = (const unsigned short *)data->src; + + if ((unsigned long)p & 0x00000001) { + debug(DRIVER_NAME": %s: The data pointer is unaligned.", + __func__); + return -EIO; + } + + debug("%s: blocks = %d, blocksize = %d\n", + __func__, data->blocks, data->blocksize); + + host->wait_int = 0; + sh_sdhi_writew(host, SDHI_INFO2_MASK, + ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) & + sh_sdhi_readw(host, SDHI_INFO2_MASK)); + sh_sdhi_writew(host, SDHI_INFO1_MASK, + ~INFO1M_ACCESS_END & + sh_sdhi_readw(host, SDHI_INFO1_MASK)); + + time = sh_sdhi_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_sdhi_error_manage(host); + + host->wait_int = 0; + blocksize = sh_sdhi_readw(host, SDHI_SIZE); + for (i = 0; i < blocksize / 2; i++) + sh_sdhi_writew(host, SDHI_BUF0, *p++); + + time = sh_sdhi_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_sdhi_error_manage(host); + + host->wait_int = 0; + return 0; +} + +static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data) +{ + long time; + unsigned short i, sec, blocksize; + const unsigned short *p = (const unsigned short *)data->src; + + debug("%s: blocks = %d, blocksize = %d\n", + __func__, data->blocks, data->blocksize); + + host->wait_int = 0; + for (sec = 0; sec < data->blocks; sec++) { + sh_sdhi_writew(host, SDHI_INFO2_MASK, + ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) & + sh_sdhi_readw(host, SDHI_INFO2_MASK)); + + time = sh_sdhi_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_sdhi_error_manage(host); + + host->wait_int = 0; + blocksize = sh_sdhi_readw(host, SDHI_SIZE); + for (i = 0; i < blocksize / 2; i++) + sh_sdhi_writew(host, SDHI_BUF0, *p++); + } + + return 0; +} + +static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd) +{ + unsigned short i, j, cnt = 1; + unsigned short resp[8]; + unsigned long *p1, *p2; + + if (cmd->resp_type & MMC_RSP_136) { + cnt = 4; + resp[0] = sh_sdhi_readw(host, SDHI_RSP00); + resp[1] = sh_sdhi_readw(host, SDHI_RSP01); + resp[2] = sh_sdhi_readw(host, SDHI_RSP02); + resp[3] = sh_sdhi_readw(host, SDHI_RSP03); + resp[4] = sh_sdhi_readw(host, SDHI_RSP04); + resp[5] = sh_sdhi_readw(host, SDHI_RSP05); + resp[6] = sh_sdhi_readw(host, SDHI_RSP06); + resp[7] = sh_sdhi_readw(host, SDHI_RSP07); + + /* SDHI REGISTER SPECIFICATION */ + for (i = 7, j = 6; i > 0; i--) { + resp[i] = (resp[i] << 8) & 0xff00; + resp[i] |= (resp[j--] >> 8) & 0x00ff; + } + resp[0] = (resp[0] << 8) & 0xff00; + + /* SDHI REGISTER SPECIFICATION */ + p1 = ((unsigned long *)resp) + 3; + + } else { + resp[0] = sh_sdhi_readw(host, SDHI_RSP00); + resp[1] = sh_sdhi_readw(host, SDHI_RSP01); + + p1 = ((unsigned long *)resp); + } + + p2 = (unsigned long *)cmd->response; +#if defined(__BIG_ENDIAN_BITFIELD) + for (i = 0; i < cnt; i++) { + *p2++ = ((*p1 >> 16) & 0x0000ffff) | + ((*p1 << 16) & 0xffff0000); + p1--; + } +#else + for (i = 0; i < cnt; i++) + *p2++ = *p1--; +#endif /* __BIG_ENDIAN_BITFIELD */ +} + +static unsigned short sh_sdhi_set_cmd(struct sh_sdhi_host *host, + struct mmc_data *data, unsigned short opc) +{ + switch (opc) { + case SD_CMD_APP_SEND_OP_COND: + case SD_CMD_APP_SEND_SCR: + opc |= SDHI_APP; + break; + case SD_CMD_APP_SET_BUS_WIDTH: + /* SD_APP_SET_BUS_WIDTH*/ + if (!data) + opc |= SDHI_APP; + else /* SD_SWITCH */ + opc = SDHI_SD_SWITCH; + break; + default: + break; + } + return opc; +} + +static unsigned short sh_sdhi_data_trans(struct sh_sdhi_host *host, + struct mmc_data *data, unsigned short opc) +{ + unsigned short ret; + + switch (opc) { + case MMC_CMD_READ_MULTIPLE_BLOCK: + ret = sh_sdhi_multi_read(host, data); + break; + case MMC_CMD_WRITE_MULTIPLE_BLOCK: + ret = sh_sdhi_multi_write(host, data); + break; + case MMC_CMD_WRITE_SINGLE_BLOCK: + ret = sh_sdhi_single_write(host, data); + break; + case MMC_CMD_READ_SINGLE_BLOCK: + case SDHI_SD_APP_SEND_SCR: + case SDHI_SD_SWITCH: /* SD_SWITCH */ + ret = sh_sdhi_single_read(host, data); + break; + default: + printf(DRIVER_NAME": SD: NOT SUPPORT CMD = d'%04d\n", opc); + ret = -EINVAL; + break; + } + return ret; +} + +static int sh_sdhi_start_cmd(struct sh_sdhi_host *host, + struct mmc_data *data, struct mmc_cmd *cmd) +{ + long time; + unsigned short opc = cmd->cmdidx; + int ret = 0; + unsigned long timeout; + + debug("opc = %d, arg = %x, resp_type = %x\n", + opc, cmd->cmdarg, cmd->resp_type); + + if (opc == MMC_CMD_STOP_TRANSMISSION) { + /* SDHI sends the STOP command automatically by STOP reg */ + sh_sdhi_writew(host, SDHI_INFO1_MASK, ~INFO1M_ACCESS_END & + sh_sdhi_readw(host, SDHI_INFO1_MASK)); + + time = sh_sdhi_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_sdhi_error_manage(host); + + sh_sdhi_get_response(host, cmd); + return 0; + } + + if (data) { + if ((opc == MMC_CMD_READ_MULTIPLE_BLOCK) || + opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { + sh_sdhi_writew(host, SDHI_STOP, STOP_SEC_ENABLE); + sh_sdhi_writew(host, SDHI_SECCNT, data->blocks); + } + sh_sdhi_writew(host, SDHI_SIZE, data->blocksize); + } + opc = sh_sdhi_set_cmd(host, data, opc); + + /* + * U-boot cannot use interrupt. + * So this flag may not be clear by timing + */ + sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END); + + sh_sdhi_writew(host, SDHI_INFO1_MASK, + INFO1M_RESP_END | sh_sdhi_readw(host, SDHI_INFO1_MASK)); + sh_sdhi_writew(host, SDHI_ARG0, + (unsigned short)(cmd->cmdarg & ARG0_MASK)); + sh_sdhi_writew(host, SDHI_ARG1, + (unsigned short)((cmd->cmdarg >> 16) & ARG1_MASK)); + + timeout = 100000; + /* Waiting for SD Bus busy to be cleared */ + while (timeout--) { + if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000)) + break; + } + + sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(opc & CMD_MASK)); + + host->wait_int = 0; + sh_sdhi_writew(host, SDHI_INFO1_MASK, + ~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK)); + sh_sdhi_writew(host, SDHI_INFO2_MASK, + ~(INFO2M_CMD_ERROR | INFO2M_CRC_ERROR | + INFO2M_END_ERROR | INFO2M_TIMEOUT | + INFO2M_RESP_TIMEOUT | INFO2M_ILA) & + sh_sdhi_readw(host, SDHI_INFO2_MASK)); + + time = sh_sdhi_wait_interrupt_flag(host); + if (!time) + return sh_sdhi_error_manage(host); + + if (host->sd_error) { + switch (cmd->cmdidx) { + case MMC_CMD_ALL_SEND_CID: + case MMC_CMD_SELECT_CARD: + case SD_CMD_SEND_IF_COND: + case MMC_CMD_APP_CMD: + ret = TIMEOUT; + break; + default: + debug(DRIVER_NAME": Cmd(d'%d) err\n", opc); + debug(DRIVER_NAME": cmdidx = %d\n", cmd->cmdidx); + ret = sh_sdhi_error_manage(host); + break; + } + host->sd_error = 0; + host->wait_int = 0; + return ret; + } + if (sh_sdhi_readw(host, SDHI_INFO1) & INFO1_RESP_END) + return -EINVAL; + + if (host->wait_int) { + sh_sdhi_get_response(host, cmd); + host->wait_int = 0; + } + if (data) + ret = sh_sdhi_data_trans(host, data, opc); + + debug("ret = %d, resp = %08x, %08x, %08x, %08x\n", + ret, cmd->response[0], cmd->response[1], + cmd->response[2], cmd->response[3]); + return ret; +} + +static int sh_sdhi_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_sdhi_host *host = mmc_priv(mmc); + int ret; + + host->sd_error = 0; + + ret = sh_sdhi_start_cmd(host, data, cmd); + + return ret; +} + +static void sh_sdhi_set_ios(struct mmc *mmc) +{ + int ret; + struct sh_sdhi_host *host = mmc_priv(mmc); + + ret = sh_sdhi_clock_control(host, mmc->clock); + if (ret) + return; + + if (mmc->bus_width == 4) + sh_sdhi_writew(host, SDHI_OPTION, ~OPT_BUS_WIDTH_1 & + sh_sdhi_readw(host, SDHI_OPTION)); + else + sh_sdhi_writew(host, SDHI_OPTION, OPT_BUS_WIDTH_1 | + sh_sdhi_readw(host, SDHI_OPTION)); + + debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); +} + +static int sh_sdhi_initialize(struct mmc *mmc) +{ + struct sh_sdhi_host *host = mmc_priv(mmc); + int ret = sh_sdhi_sync_reset(host); + + sh_sdhi_writew(host, SDHI_PORTSEL, USE_1PORT); + +#if defined(__BIG_ENDIAN_BITFIELD) + sh_sdhi_writew(host, SDHI_EXT_SWAP, SET_SWAP); +#endif + + sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END | + INFO1M_ACCESS_END | INFO1M_CARD_RE | + INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); + + return ret; +} + +static const struct mmc_ops sh_sdhi_ops = { + .send_cmd = sh_sdhi_send_cmd, + .set_ios = sh_sdhi_set_ios, + .init = sh_sdhi_initialize, +}; + +static struct mmc_config sh_sdhi_cfg = { + .name = DRIVER_NAME, + .ops = &sh_sdhi_ops, + .f_min = CLKDEV_INIT, + .f_max = CLKDEV_HS_DATA, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .host_caps = MMC_MODE_4BIT | MMC_MODE_HS, + .part_type = PART_TYPE_DOS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + +int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) +{ + int ret = 0; + struct mmc *mmc; + struct sh_sdhi_host *host = NULL; + + if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL) + return -ENODEV; + + host = malloc(sizeof(struct sh_sdhi_host)); + if (!host) + return -ENOMEM; + + mmc = mmc_create(&sh_sdhi_cfg, host); + if (!mmc) { + ret = -1; + goto error; + } + + host->ch = ch; + host->addr = addr; + host->quirks = quirks; + + if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF) + host->bus_shift = 1; + + return ret; +error: + if (host) + free(host); + return ret; +} diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c new file mode 100644 index 0000000000..eb69aed9df --- /dev/null +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct socfpga_clock_manager *clock_manager_base = + (void *)SOCFPGA_CLKMGR_ADDRESS; +static const struct socfpga_system_manager *system_manager_base = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +static void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + unsigned int drvsel; + unsigned int smplsel; + + /* Disable SDMMC clock. */ + clrbits_le32(&clock_manager_base->per_pll.en, + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + + /* Configures drv_sel and smpl_sel */ + drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; + smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; + + debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); + writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), + &system_manager_base->sdmmcgrp_ctrl); + + debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, + readl(&system_manager_base->sdmmcgrp_ctrl)); + + /* Enable SDMMC clock */ + setbits_le32(&clock_manager_base->per_pll.en, + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); +} + +int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) +{ + struct dwmci_host *host; + unsigned long clk = cm_get_mmc_controller_clk_hz(); + + if (clk == 0) { + printf("%s: MMC clock is zero!", __func__); + return -EINVAL; + } + + /* calloc for zero init */ + host = calloc(1, sizeof(struct dwmci_host)); + if (!host) { + printf("%s: calloc() failed!\n", __func__); + return -ENOMEM; + } + + host->name = "SOCFPGA DWMMC"; + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->clksel = socfpga_dwmci_clksel; + host->dev_index = index; + /* fixed clock divide by 4 which due to the SDMMC wrapper */ + host->bus_hz = clk; + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) | + TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2); + + return add_dwmci(host, host->bus_hz, 400000); +} + diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c new file mode 100644 index 0000000000..ebfec7cf07 --- /dev/null +++ b/drivers/mmc/sunxi_mmc.c @@ -0,0 +1,468 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Aaron + * + * MMC driver for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct sunxi_mmc_host { + unsigned mmc_no; + uint32_t *mclkreg; + unsigned fatal_err; + struct sunxi_mmc *reg; + struct mmc_config cfg; +}; + +/* support 4 mmc hosts */ +struct sunxi_mmc_host mmc_host[4]; + +static int sunxi_mmc_getcd_gpio(int sdc_no) +{ + switch (sdc_no) { + case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN); + case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN); + case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN); + case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN); + } + return -1; +} + +static int mmc_resource_init(int sdc_no) +{ + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int cd_pin, ret = 0; + + debug("init mmc %d resource\n", sdc_no); + + switch (sdc_no) { + case 0: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; + mmchost->mclkreg = &ccm->sd0_clk_cfg; + break; + case 1: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; + mmchost->mclkreg = &ccm->sd1_clk_cfg; + break; + case 2: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; + mmchost->mclkreg = &ccm->sd2_clk_cfg; + break; + case 3: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; + mmchost->mclkreg = &ccm->sd3_clk_cfg; + break; + default: + printf("Wrong mmc number %d\n", sdc_no); + return -1; + } + mmchost->mmc_no = sdc_no; + + cd_pin = sunxi_mmc_getcd_gpio(sdc_no); + if (cd_pin != -1) { + ret = gpio_request(cd_pin, "mmc_cd"); + if (!ret) + ret = gpio_direction_input(cd_pin); + } + + return ret; +} + +static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) +{ + unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; + + if (hz <= 24000000) { + pll = CCM_MMC_CTRL_OSCM24; + pll_hz = 24000000; + } else { +#ifdef CONFIG_MACH_SUN9I + pll = CCM_MMC_CTRL_PLL_PERIPH0; + pll_hz = clock_get_pll4_periph0(); +#else + pll = CCM_MMC_CTRL_PLL6; + pll_hz = clock_get_pll6(); +#endif + } + + div = pll_hz / hz; + if (pll_hz % hz) + div++; + + n = 0; + while (div > 16) { + n++; + div = (div + 1) / 2; + } + + if (n > 3) { + printf("mmc %u error cannot set clock to %u\n", + mmchost->mmc_no, hz); + return -1; + } + + /* determine delays */ + if (hz <= 400000) { + oclk_dly = 0; + sclk_dly = 7; + } else if (hz <= 25000000) { + oclk_dly = 0; + sclk_dly = 5; + } else if (hz <= 50000000) { + oclk_dly = 3; + sclk_dly = 5; + } else { + /* hz > 50000000 */ + oclk_dly = 2; + sclk_dly = 4; + } + + writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | + CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | + CCM_MMC_CTRL_M(div), mmchost->mclkreg); + + debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", + mmchost->mmc_no, hz, pll_hz, 1u << n, div, + pll_hz / (1u << n) / div); + + return 0; +} + +static int mmc_clk_io_on(int sdc_no) +{ + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d clock and io\n", sdc_no); + + /* config ahb clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); + +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ + defined(CONFIG_MACH_SUN9I) + /* unassert reset */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); +#endif +#if defined(CONFIG_MACH_SUN9I) + /* sun9i has a mmc-common module, also set the gate and reset there */ + writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET, + SUNXI_MMC_COMMON_BASE + 4 * sdc_no); +#endif + + return mmc_set_mod_clk(mmchost, 24000000); +} + +static int mmc_update_clk(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int cmd; + unsigned timeout_msecs = 2000; + + cmd = SUNXI_MMC_CMD_START | + SUNXI_MMC_CMD_UPCLK_ONLY | + SUNXI_MMC_CMD_WAIT_PRE_OVER; + writel(cmd, &mmchost->reg->cmd); + while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) { + if (!timeout_msecs--) + return -1; + udelay(1000); + } + + /* clock update sets various irq status bits, clear these */ + writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); + + return 0; +} + +static int mmc_config_clock(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned rval = readl(&mmchost->reg->clkcr); + + /* Disable Clock */ + rval &= ~SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + + /* Set mod_clk to new rate */ + if (mmc_set_mod_clk(mmchost, mmc->clock)) + return -1; + + /* Clear internal divider */ + rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; + writel(rval, &mmchost->reg->clkcr); + + /* Re-enable Clock */ + rval |= SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + + return 0; +} + +static void sunxi_mmc_set_ios(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + + debug("set ios: bus_width: %x, clock: %d\n", + mmc->bus_width, mmc->clock); + + /* Change clock first */ + if (mmc->clock && mmc_config_clock(mmc) != 0) { + mmchost->fatal_err = 1; + return; + } + + /* Change bus width */ + if (mmc->bus_width == 8) + writel(0x2, &mmchost->reg->width); + else if (mmc->bus_width == 4) + writel(0x1, &mmchost->reg->width); + else + writel(0x0, &mmchost->reg->width); +} + +static int sunxi_mmc_core_init(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + + /* Reset controller */ + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + udelay(1000); + + return 0; +} + +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + const int reading = !!(data->flags & MMC_DATA_READ); + const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : + SUNXI_MMC_STATUS_FIFO_FULL; + unsigned i; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned timeout_msecs = 2000; + unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); + + /* Always read / write data through the CPU */ + setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); + + for (i = 0; i < (byte_cnt >> 2); i++) { + while (readl(&mmchost->reg->status) & status_bit) { + if (!timeout_msecs--) + return -1; + udelay(1000); + } + + if (reading) + buff[i] = readl(&mmchost->reg->fifo); + else + writel(buff[i], &mmchost->reg->fifo); + } + + return 0; +} + +static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, + unsigned int done_bit, const char *what) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int status; + + do { + status = readl(&mmchost->reg->rint); + if (!timeout_msecs-- || + (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { + debug("%s timeout %x\n", what, + status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); + return TIMEOUT; + } + udelay(1000); + } while (!(status & done_bit)); + + return 0; +} + +static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int cmdval = SUNXI_MMC_CMD_START; + unsigned int timeout_msecs; + int error = 0; + unsigned int status = 0; + unsigned int bytecnt = 0; + + if (mmchost->fatal_err) + return -1; + if (cmd->resp_type & MMC_RSP_BUSY) + debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); + if (cmd->cmdidx == 12) + return 0; + + if (!cmd->cmdidx) + cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; + if (cmd->resp_type & MMC_RSP_PRESENT) + cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; + if (cmd->resp_type & MMC_RSP_136) + cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; + if (cmd->resp_type & MMC_RSP_CRC) + cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; + + if (data) { + if ((u32) data->dest & 0x3) { + error = -1; + goto out; + } + + cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; + if (data->flags & MMC_DATA_WRITE) + cmdval |= SUNXI_MMC_CMD_WRITE; + if (data->blocks > 1) + cmdval |= SUNXI_MMC_CMD_AUTO_STOP; + writel(data->blocksize, &mmchost->reg->blksz); + writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); + } + + debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); + writel(cmd->cmdarg, &mmchost->reg->arg); + + if (!data) + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + + /* + * transfer data and check status + * STATREG[2] : FIFO empty + * STATREG[3] : FIFO full + */ + if (data) { + int ret = 0; + + bytecnt = data->blocksize * data->blocks; + debug("trans data %d bytes\n", bytecnt); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + ret = mmc_trans_data_by_cpu(mmc, data); + if (ret) { + error = readl(&mmchost->reg->rint) & \ + SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; + error = TIMEOUT; + goto out; + } + } + + error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); + if (error) + goto out; + + if (data) { + timeout_msecs = 120; + debug("cacl timeout %x msec\n", timeout_msecs); + error = mmc_rint_wait(mmc, timeout_msecs, + data->blocks > 1 ? + SUNXI_MMC_RINT_AUTO_COMMAND_DONE : + SUNXI_MMC_RINT_DATA_OVER, + "data"); + if (error) + goto out; + } + + if (cmd->resp_type & MMC_RSP_BUSY) { + timeout_msecs = 2000; + do { + status = readl(&mmchost->reg->status); + if (!timeout_msecs--) { + debug("busy timeout\n"); + error = TIMEOUT; + goto out; + } + udelay(1000); + } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); + } + + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = readl(&mmchost->reg->resp3); + cmd->response[1] = readl(&mmchost->reg->resp2); + cmd->response[2] = readl(&mmchost->reg->resp1); + cmd->response[3] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", + cmd->response[3], cmd->response[2], + cmd->response[1], cmd->response[0]); + } else { + cmd->response[0] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x\n", cmd->response[0]); + } +out: + if (error < 0) { + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + mmc_update_clk(mmc); + } + writel(0xffffffff, &mmchost->reg->rint); + writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, + &mmchost->reg->gctrl); + + return error; +} + +static int sunxi_mmc_getcd(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + int cd_pin; + + cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no); + if (cd_pin == -1) + return 1; + + return !gpio_get_value(cd_pin); +} + +static const struct mmc_ops sunxi_mmc_ops = { + .send_cmd = sunxi_mmc_send_cmd, + .set_ios = sunxi_mmc_set_ios, + .init = sunxi_mmc_core_init, + .getcd = sunxi_mmc_getcd, +}; + +struct mmc *sunxi_mmc_init(int sdc_no) +{ + struct mmc_config *cfg = &mmc_host[sdc_no].cfg; + + memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); + + cfg->name = "SUNXI SD/MMC"; + cfg->ops = &sunxi_mmc_ops; + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->host_caps = MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I) + cfg->host_caps |= MMC_MODE_HC; +#endif + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + cfg->f_min = 400000; + cfg->f_max = 52000000; + + if (mmc_resource_init(sdc_no) != 0) + return NULL; + + mmc_clk_io_on(sdc_no); + + return mmc_create(cfg, &mmc_host[sdc_no]); +} diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index e1817e24f6..2cd8cf10ae 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -13,13 +13,13 @@ #include #include #include +#include #include #include DECLARE_GLOBAL_DATA_PTR; -struct mmc mmc_dev[MAX_HOSTS]; -struct mmc_host mmc_host[MAX_HOSTS]; +struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE]; #ifndef CONFIG_OF_CONTROL #error "Please enable device tree support to use this driver" @@ -145,7 +145,7 @@ static int mmc_wait_inhibit(struct mmc_host *host, static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data, struct bounce_buffer *bbstate) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; int flags, i; int result; unsigned int mask = 0; @@ -293,7 +293,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, /* Transfer Complete */ debug("r/w is done\n"); break; - } else if (get_timer(start) > 2000UL) { + } else if (get_timer(start) > 8000UL) { writel(mask, &host->reg->norintsts); printf("%s: MMC Timeout\n" " Interrupt status 0x%08x\n" @@ -314,7 +314,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, return 0; } -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, +static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { void *buf; @@ -396,7 +396,7 @@ out: host->clock = clock; } -static void mmc_set_ios(struct mmc *mmc) +static void tegra_mmc_set_ios(struct mmc *mmc) { struct mmc_host *host = mmc->priv; unsigned char ctrl; @@ -456,7 +456,7 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc) } /* Set SD bus voltage & enable bus power */ - mmc_set_power(host, fls(mmc->voltages) - 1); + mmc_set_power(host, fls(mmc->cfg->voltages) - 1); debug("%s: power control = %02X, host control = %02X\n", __func__, readb(&host->reg->pwrcon), readb(&host->reg->hostctl)); @@ -464,9 +464,9 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc) pad_init_mmc(host); } -static int mmc_core_init(struct mmc *mmc) +static int tegra_mmc_core_init(struct mmc *mmc) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; unsigned int mask; debug(" mmc_core_init called\n"); @@ -509,22 +509,28 @@ static int mmc_core_init(struct mmc *mmc) return 0; } -int tegra_mmc_getcd(struct mmc *mmc) +static int tegra_mmc_getcd(struct mmc *mmc) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; debug("tegra_mmc_getcd called\n"); - if (fdt_gpio_isvalid(&host->cd_gpio)) - return fdtdec_get_gpio(&host->cd_gpio); + if (dm_gpio_is_valid(&host->cd_gpio)) + return dm_gpio_get_value(&host->cd_gpio); return 1; } +static const struct mmc_ops tegra_mmc_ops = { + .send_cmd = tegra_mmc_send_cmd, + .set_ios = tegra_mmc_set_ios, + .init = tegra_mmc_core_init, + .getcd = tegra_mmc_getcd, +}; + static int do_mmc_init(int dev_index) { struct mmc_host *host; - char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */ struct mmc *mmc; /* DT should have been read & host config filled in */ @@ -532,45 +538,28 @@ static int do_mmc_init(int dev_index) if (!host->enabled) return -1; - debug(" do_mmc_init: index %d, bus width %d " - "pwr_gpio %d cd_gpio %d\n", - dev_index, host->width, - host->pwr_gpio.gpio, host->cd_gpio.gpio); + debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n", + dev_index, host->width, gpio_get_number(&host->pwr_gpio), + gpio_get_number(&host->cd_gpio)); host->clock = 0; clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); - if (fdt_gpio_isvalid(&host->pwr_gpio)) { - sprintf(gpusage, "SD/MMC%d PWR", dev_index); - gpio_request(host->pwr_gpio.gpio, gpusage); - gpio_direction_output(host->pwr_gpio.gpio, 1); - debug(" Power GPIO name = %s\n", host->pwr_gpio.name); - } - - if (fdt_gpio_isvalid(&host->cd_gpio)) { - sprintf(gpusage, "SD/MMC%d CD", dev_index); - gpio_request(host->cd_gpio.gpio, gpusage); - gpio_direction_input(host->cd_gpio.gpio); - debug(" CD GPIO name = %s\n", host->cd_gpio.name); - } + if (dm_gpio_is_valid(&host->pwr_gpio)) + dm_gpio_set_value(&host->pwr_gpio, 1); - mmc = &mmc_dev[dev_index]; + memset(&host->cfg, 0, sizeof(host->cfg)); - sprintf(mmc->name, "Tegra SD/MMC"); - mmc->priv = host; - mmc->send_cmd = mmc_send_cmd; - mmc->set_ios = mmc_set_ios; - mmc->init = mmc_core_init; - mmc->getcd = tegra_mmc_getcd; - mmc->getwp = NULL; + host->cfg.name = "Tegra SD/MMC"; + host->cfg.ops = &tegra_mmc_ops; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->host_caps = 0; + host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + host->cfg.host_caps = 0; if (host->width == 8) - mmc->host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; if (host->width >= 4) - mmc->host_caps |= MMC_MODE_4BIT; - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; + host->cfg.host_caps |= MMC_MODE_4BIT; + host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; /* * min freq is for card identification, and is the highest @@ -578,10 +567,14 @@ static int do_mmc_init(int dev_index) * max freq is highest HS eMMC clock as per the SD/MMC spec * (actually 52MHz) */ - mmc->f_min = 375000; - mmc->f_max = 48000000; + host->cfg.f_min = 375000; + host->cfg.f_max = 48000000; - mmc_register(mmc); + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create(&host->cfg, host); + if (mmc == NULL) + return -1; return 0; } @@ -620,9 +613,12 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host) debug("%s: no sdmmc width found\n", __func__); /* These GPIOs are optional */ - fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio); - fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio); - fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio); + gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio, + GPIOD_IS_IN); + gpio_request_by_name_nodev(blob, node, "wp-gpios", 0, &host->wp_gpio, + GPIOD_IS_IN); + gpio_request_by_name_nodev(blob, node, "power-gpios", 0, + &host->pwr_gpio, GPIOD_IS_OUT); debug("%s: found controller at %p, width = %d, periph_id = %d\n", __func__, host->reg, host->width, host->mmc_id); @@ -664,13 +660,24 @@ static int process_nodes(const void *blob, int node_list[], int count) void tegra_mmc_init(void) { - int node_list[MAX_HOSTS], count; + int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count; const void *blob = gd->fdt_blob; debug("%s entry\n", __func__); + /* See if any Tegra124 MMC controllers are present */ + count = fdtdec_find_aliases_for_id(blob, "sdhci", + COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, + CONFIG_SYS_MMC_MAX_DEVICE); + debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); + if (process_nodes(blob, node_list, count)) { + printf("%s: Error processing T30 mmc node(s)!\n", __func__); + return; + } + /* See if any Tegra30 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", - COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS); + COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, + CONFIG_SYS_MMC_MAX_DEVICE); debug("%s: count of T30 sdhci nodes is %d\n", __func__, count); if (process_nodes(blob, node_list, count)) { printf("%s: Error processing T30 mmc node(s)!\n", __func__); @@ -679,7 +686,8 @@ void tegra_mmc_init(void) /* Now look for any Tegra20 MMC controllers */ count = fdtdec_find_aliases_for_id(blob, "sdhci", - COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS); + COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, + CONFIG_SYS_MMC_MAX_DEVICE); debug("%s: count of T20 sdhci nodes is %d\n", __func__, count); if (process_nodes(blob, node_list, count)) { printf("%s: Error processing T20 mmc node(s)!\n", __func__); diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 610bef5cba..7887f11c64 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -7,11 +7,13 @@ */ #include +#include +#include #include #include #include -int zynq_sdhci_init(u32 regbase) +int zynq_sdhci_init(phys_addr_t regbase) { struct sdhci_host *host = NULL; @@ -23,7 +25,8 @@ int zynq_sdhci_init(u32 regbase) host->name = "zynq_sdhci"; host->ioaddr = (void *)regbase; - host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD; + host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD | + SDHCI_QUIRK_BROKEN_R1B; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->host_caps = MMC_MODE_HC; @@ -31,3 +34,30 @@ int zynq_sdhci_init(u32 regbase) add_sdhci(host, 52000000, 52000000 >> 9); return 0; } + +#ifdef CONFIG_OF_CONTROL +int zynq_sdhci_of_init(const void *blob) +{ + int offset = 0; + u32 ret = 0; + phys_addr_t reg; + + debug("ZYNQ SDHCI: Initialization\n"); + + do { + offset = fdt_node_offset_by_compatible(blob, offset, + "arasan,sdhci-8.9a"); + if (offset != -1) { + reg = fdtdec_get_addr(blob, offset, "reg"); + if (reg != FDT_ADDR_T_NONE) { + ret |= zynq_sdhci_init(reg); + } else { + debug("ZYNQ SDHCI: Can't get base address\n"); + return -1; + } + } + } while (offset != -1); + + return ret; +} +#endif diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig new file mode 100644 index 0000000000..5b56f11e93 --- /dev/null +++ b/drivers/mtd/Kconfig @@ -0,0 +1,21 @@ +menuconfig NOR_FLASH + bool "NOR flash support" + +if NOR_FLASH + +config CONFIG_FLASH_CFI_DRIVER + bool "CFI flash driver" + +endif + +config SYS_NO_FLASH + bool + default y + depends on !NOR_FLASH + +config MTD_PARTITIONS + bool "Support MTD partition tables" + depends on MTD_DEVICE + default y + +source "drivers/mtd/nand/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index d2c3bdab96..5467a951bb 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -5,38 +5,16 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libmtd.o - ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND))) -COBJS-y += mtdcore.o +obj-y += mtdcore.o endif -COBJS-$(CONFIG_MTD_PARTITIONS) += mtdpart.o -COBJS-$(CONFIG_MTD_CONCAT) += mtdconcat.o -COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o -COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o -COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o -COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o -COBJS-$(CONFIG_FTSMC020) += ftsmc020.o -COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o -COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o -COBJS-$(CONFIG_ST_SMI) += st_smi.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o +obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o +obj-$(CONFIG_HAS_DATAFLASH) += at45.o +obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o +obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o +obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o +obj-$(CONFIG_FTSMC020) += ftsmc020.o +obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o +obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o +obj-$(CONFIG_ST_SMI) += st_smi.o diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index a389cd101c..50983b837b 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -63,6 +63,12 @@ flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #endif +#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define __maybe_weak __weak +#else +#define __maybe_weak static +#endif + /* * 0xffff is an undefined value for the configuration register. When * this value is returned, the configuration register shall not be @@ -81,14 +87,12 @@ static u16 cfi_flash_config_reg(int i) int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; #endif -static phys_addr_t __cfi_flash_bank_addr(int i) +__weak phys_addr_t cfi_flash_bank_addr(int i) { return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; } -phys_addr_t cfi_flash_bank_addr(int i) - __attribute__((weak, alias("__cfi_flash_bank_addr"))); -static unsigned long __cfi_flash_bank_size(int i) +__weak unsigned long cfi_flash_bank_size(int i) { #ifdef CONFIG_SYS_FLASH_BANKS_SIZES return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; @@ -96,71 +100,49 @@ static unsigned long __cfi_flash_bank_size(int i) return 0; #endif } -unsigned long cfi_flash_bank_size(int i) - __attribute__((weak, alias("__cfi_flash_bank_size"))); -static void __flash_write8(u8 value, void *addr) +__maybe_weak void flash_write8(u8 value, void *addr) { __raw_writeb(value, addr); } -static void __flash_write16(u16 value, void *addr) +__maybe_weak void flash_write16(u16 value, void *addr) { __raw_writew(value, addr); } -static void __flash_write32(u32 value, void *addr) +__maybe_weak void flash_write32(u32 value, void *addr) { __raw_writel(value, addr); } -static void __flash_write64(u64 value, void *addr) +__maybe_weak void flash_write64(u64 value, void *addr) { /* No architectures currently implement __raw_writeq() */ *(volatile u64 *)addr = value; } -static u8 __flash_read8(void *addr) +__maybe_weak u8 flash_read8(void *addr) { return __raw_readb(addr); } -static u16 __flash_read16(void *addr) +__maybe_weak u16 flash_read16(void *addr) { return __raw_readw(addr); } -static u32 __flash_read32(void *addr) +__maybe_weak u32 flash_read32(void *addr) { return __raw_readl(addr); } -static u64 __flash_read64(void *addr) +__maybe_weak u64 flash_read64(void *addr) { /* No architectures currently implement __raw_readq() */ return *(volatile u64 *)addr; } -#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8"))); -void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16"))); -void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32"))); -void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64"))); -u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8"))); -u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16"))); -u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32"))); -u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); -#else -#define flash_write8 __flash_write8 -#define flash_write16 __flash_write16 -#define flash_write32 __flash_write32 -#define flash_write64 __flash_write64 -#define flash_read8 __flash_read8 -#define flash_read16 __flash_read16 -#define flash_read32 __flash_read32 -#define flash_read64 __flash_read64 -#endif - /*----------------------------------------------------------------------- */ #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) @@ -593,7 +575,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: - if ((retcode != ERR_OK) + if ((retcode == ERR_OK) && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { retcode = ERR_INVAL; printf ("Flash %s error at address %lx\n", prompt, @@ -2360,7 +2342,7 @@ unsigned long flash_init (void) #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ } #ifdef CONFIG_SYS_FLASH_PROTECTION - else if ((s != NULL) && (strcmp(s, "yes") == 0)) { + else if (strcmp(s, "yes") == 0) { /* * Only the U-Boot image and it's environment * is protected, all other sectors are diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index ac805ff1e9..709a48642d 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -226,6 +226,7 @@ int cfi_mtd_init(void) mtd->flags = MTD_CAP_NORFLASH; mtd->size = fi->size; mtd->writesize = 1; + mtd->writebufsize = mtd->writesize; mtd->_erase = cfi_mtd_erase; mtd->_read = cfi_mtd_read; diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index 593b9b8433..ce9af8f254 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -332,6 +332,57 @@ static const struct amd_flash_info jedec_table[] = { ERASEINFO(0x10000, 15), } }, + { + .mfr_id = (u16)AMD_MANUFACT, + .dev_id = AM29LV800BT, + .name = "AMD AM29LV800BT", + .uaddr = { + [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ + }, + .DevSize = SIZE_1MiB, + .CmdSet = CFI_CMDSET_AMD_LEGACY, + .NumEraseRegions= 4, + .regions = { + ERASEINFO(0x10000, 15), + ERASEINFO(0x08000, 1), + ERASEINFO(0x02000, 2), + ERASEINFO(0x04000, 1), + } + }, + { + .mfr_id = (u16)MX_MANUFACT, + .dev_id = AM29LV800BT, + .name = "MXIC MX29LV800BT", + .uaddr = { + [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ + }, + .DevSize = SIZE_1MiB, + .CmdSet = CFI_CMDSET_AMD_LEGACY, + .NumEraseRegions= 4, + .regions = { + ERASEINFO(0x10000, 15), + ERASEINFO(0x08000, 1), + ERASEINFO(0x02000, 2), + ERASEINFO(0x04000, 1), + } + }, + { + .mfr_id = (u16)EON_ALT_MANU, + .dev_id = AM29LV800BT, + .name = "EON EN29LV800BT", + .uaddr = { + [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ + }, + .DevSize = SIZE_1MiB, + .CmdSet = CFI_CMDSET_AMD_LEGACY, + .NumEraseRegions= 4, + .regions = { + ERASEINFO(0x10000, 15), + ERASEINFO(0x08000, 1), + ERASEINFO(0x02000, 2), + ERASEINFO(0x04000, 1), + } + }, { .mfr_id = (u16)STM_MANUFACT, .dev_id = STM29F400BB, diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c index 31e4289b16..3e36918f1c 100644 --- a/drivers/mtd/mtdconcat.c +++ b/drivers/mtd/mtdconcat.c @@ -1,16 +1,31 @@ /* * MTD device concatenation layer * - * (C) 2002 Robert Kaiser + * Copyright © 2002 Robert Kaiser + * Copyright © 2002-2010 David Woodhouse * * NAND support by Christian Gan * - * This code is GPL + * SPDX-License-Identifier: GPL-2.0+ + * */ -#include +#ifndef __UBOOT__ +#include +#include +#include +#include +#include +#include +#include +#else +#include #include +#endif + +#include #include + #include /* @@ -51,7 +66,9 @@ concat_read(struct mtd_info *mtd, loff_t from, size_t len, int ret = 0, err; int i; +#ifdef __UBOOT__ *retlen = 0; +#endif for (i = 0; i < concat->num_subdev; i++) { struct mtd_info *subdev = concat->subdev[i]; @@ -105,7 +122,9 @@ concat_write(struct mtd_info *mtd, loff_t to, size_t len, int err = -EINVAL; int i; +#ifdef __UBOOT__ *retlen = 0; +#endif for (i = 0; i < concat->num_subdev; i++) { struct mtd_info *subdev = concat->subdev[i]; @@ -137,6 +156,83 @@ concat_write(struct mtd_info *mtd, loff_t to, size_t len, return err; } +#ifndef __UBOOT__ +static int +concat_writev(struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t * retlen) +{ + struct mtd_concat *concat = CONCAT(mtd); + struct kvec *vecs_copy; + unsigned long entry_low, entry_high; + size_t total_len = 0; + int i; + int err = -EINVAL; + + /* Calculate total length of data */ + for (i = 0; i < count; i++) + total_len += vecs[i].iov_len; + + /* Check alignment */ + if (mtd->writesize > 1) { + uint64_t __to = to; + if (do_div(__to, mtd->writesize) || (total_len % mtd->writesize)) + return -EINVAL; + } + + /* make a copy of vecs */ + vecs_copy = kmemdup(vecs, sizeof(struct kvec) * count, GFP_KERNEL); + if (!vecs_copy) + return -ENOMEM; + + entry_low = 0; + for (i = 0; i < concat->num_subdev; i++) { + struct mtd_info *subdev = concat->subdev[i]; + size_t size, wsize, retsize, old_iov_len; + + if (to >= subdev->size) { + to -= subdev->size; + continue; + } + + size = min_t(uint64_t, total_len, subdev->size - to); + wsize = size; /* store for future use */ + + entry_high = entry_low; + while (entry_high < count) { + if (size <= vecs_copy[entry_high].iov_len) + break; + size -= vecs_copy[entry_high++].iov_len; + } + + old_iov_len = vecs_copy[entry_high].iov_len; + vecs_copy[entry_high].iov_len = size; + + err = mtd_writev(subdev, &vecs_copy[entry_low], + entry_high - entry_low + 1, to, &retsize); + + vecs_copy[entry_high].iov_len = old_iov_len - size; + vecs_copy[entry_high].iov_base += size; + + entry_low = entry_high; + + if (err) + break; + + *retlen += retsize; + total_len -= wsize; + + if (total_len == 0) + break; + + err = -EINVAL; + to = 0; + } + + kfree(vecs_copy); + return err; +} +#endif + static int concat_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { @@ -204,7 +300,7 @@ concat_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) if (!(mtd->flags & MTD_WRITEABLE)) return -EROFS; - ops->retlen = 0; + ops->retlen = ops->oobretlen = 0; for (i = 0; i < concat->num_subdev; i++) { struct mtd_info *subdev = concat->subdev[i]; @@ -219,7 +315,7 @@ concat_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) devops.len = subdev->size - to; err = mtd_write_oob(subdev, to, &devops); - ops->retlen += devops.retlen; + ops->retlen += devops.oobretlen; if (err) return err; @@ -243,6 +339,9 @@ concat_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) static void concat_erase_callback(struct erase_info *instr) { /* Nothing to do here in U-Boot */ +#ifndef __UBOOT__ + wake_up((wait_queue_head_t *) instr->priv); +#endif } static int concat_dev_erase(struct mtd_info *mtd, struct erase_info *erase) @@ -316,7 +415,7 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr) * to-be-erased area begins. Verify that the starting * offset is aligned to this region's erase size: */ - if (instr->addr & (erase_regions[i].erasesize - 1)) + if (i < 0 || instr->addr & (erase_regions[i].erasesize - 1)) return -EINVAL; /* @@ -329,8 +428,8 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr) /* * check if the ending offset is aligned to this region's erase size */ - if ((instr->addr + instr->len) & (erase_regions[i].erasesize - - 1)) + if (i < 0 || ((instr->addr + instr->len) & + (erase_regions[i].erasesize - 1))) return -EINVAL; } @@ -422,7 +521,6 @@ static int concat_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) size = len; err = mtd_lock(subdev, ofs, size); - if (err) break; @@ -457,7 +555,6 @@ static int concat_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) size = len; err = mtd_unlock(subdev, ofs, size); - if (err) break; @@ -483,6 +580,32 @@ static void concat_sync(struct mtd_info *mtd) } } +#ifndef __UBOOT__ +static int concat_suspend(struct mtd_info *mtd) +{ + struct mtd_concat *concat = CONCAT(mtd); + int i, rc = 0; + + for (i = 0; i < concat->num_subdev; i++) { + struct mtd_info *subdev = concat->subdev[i]; + if ((rc = mtd_suspend(subdev)) < 0) + return rc; + } + return rc; +} + +static void concat_resume(struct mtd_info *mtd) +{ + struct mtd_concat *concat = CONCAT(mtd); + int i; + + for (i = 0; i < concat->num_subdev; i++) { + struct mtd_info *subdev = concat->subdev[i]; + mtd_resume(subdev); + } +} +#endif + static int concat_block_isbad(struct mtd_info *mtd, loff_t ofs) { struct mtd_concat *concat = CONCAT(mtd); @@ -511,9 +634,6 @@ static int concat_block_markbad(struct mtd_info *mtd, loff_t ofs) struct mtd_concat *concat = CONCAT(mtd); int i, err = -EINVAL; - if (!mtd_can_have_bb(concat->subdev[0])) - return 0; - for (i = 0; i < concat->num_subdev; i++) { struct mtd_info *subdev = concat->subdev[i]; @@ -531,6 +651,32 @@ static int concat_block_markbad(struct mtd_info *mtd, loff_t ofs) return err; } +/* + * try to support NOMMU mmaps on concatenated devices + * - we don't support subdev spanning as we can't guarantee it'll work + */ +static unsigned long concat_get_unmapped_area(struct mtd_info *mtd, + unsigned long len, + unsigned long offset, + unsigned long flags) +{ + struct mtd_concat *concat = CONCAT(mtd); + int i; + + for (i = 0; i < concat->num_subdev; i++) { + struct mtd_info *subdev = concat->subdev[i]; + + if (offset >= subdev->size) { + offset -= subdev->size; + continue; + } + + return mtd_get_unmapped_area(subdev, len, offset, flags); + } + + return (unsigned long) -ENOSYS; +} + /* * This function constructs a virtual MTD device by concatenating * num_devs MTD devices. A pointer to the new device object is @@ -539,17 +685,22 @@ static int concat_block_markbad(struct mtd_info *mtd, loff_t ofs) */ struct mtd_info *mtd_concat_create(struct mtd_info *subdev[], /* subdevices to concatenate */ int num_devs, /* number of subdevices */ +#ifndef __UBOOT__ const char *name) +#else + char *name) +#endif { /* name for the new device */ int i; size_t size; struct mtd_concat *concat; uint32_t max_erasesize, curr_erasesize; int num_erase_region; + int max_writebufsize = 0; debug("Concatenating MTD devices:\n"); for (i = 0; i < num_devs; i++) - debug("(%d): \"%s\"\n", i, subdev[i]->name); + printk(KERN_NOTICE "(%d): \"%s\"\n", i, subdev[i]->name); debug("into device \"%s\"\n", name); /* allocate the device structure */ @@ -565,16 +716,26 @@ struct mtd_info *mtd_concat_create(struct mtd_info *subdev[], /* subdevices to c /* * Set up the new "super" device's MTD object structure, check for - * incompatibilites between the subdevices. + * incompatibilities between the subdevices. */ concat->mtd.type = subdev[0]->type; concat->mtd.flags = subdev[0]->flags; concat->mtd.size = subdev[0]->size; concat->mtd.erasesize = subdev[0]->erasesize; concat->mtd.writesize = subdev[0]->writesize; + + for (i = 0; i < num_devs; i++) + if (max_writebufsize < subdev[i]->writebufsize) + max_writebufsize = subdev[i]->writebufsize; + concat->mtd.writebufsize = max_writebufsize; + concat->mtd.subpage_sft = subdev[0]->subpage_sft; concat->mtd.oobsize = subdev[0]->oobsize; concat->mtd.oobavail = subdev[0]->oobavail; +#ifndef __UBOOT__ + if (subdev[0]->_writev) + concat->mtd._writev = concat_writev; +#endif if (subdev[0]->_read_oob) concat->mtd._read_oob = concat_read_oob; if (subdev[0]->_write_oob) @@ -586,6 +747,10 @@ struct mtd_info *mtd_concat_create(struct mtd_info *subdev[], /* subdevices to c concat->mtd.ecc_stats.badblocks = subdev[0]->ecc_stats.badblocks; +#ifndef __UBOOT__ + concat->mtd.backing_dev_info = subdev[0]->backing_dev_info; +#endif + concat->subdev[0] = subdev[0]; for (i = 1; i < num_devs; i++) { @@ -613,6 +778,16 @@ struct mtd_info *mtd_concat_create(struct mtd_info *subdev[], /* subdevices to c subdev[i]->flags & MTD_WRITEABLE; } +#ifndef __UBOOT__ + /* only permit direct mapping if the BDIs are all the same + * - copy-mapping is still permitted + */ + if (concat->mtd.backing_dev_info != + subdev[i]->backing_dev_info) + concat->mtd.backing_dev_info = + &default_backing_dev_info; +#endif + concat->mtd.size += subdev[i]->size; concat->mtd.ecc_stats.badblocks += subdev[i]->ecc_stats.badblocks; @@ -641,6 +816,11 @@ struct mtd_info *mtd_concat_create(struct mtd_info *subdev[], /* subdevices to c concat->mtd._sync = concat_sync; concat->mtd._lock = concat_lock; concat->mtd._unlock = concat_unlock; +#ifndef __UBOOT__ + concat->mtd._suspend = concat_suspend; + concat->mtd._resume = concat_resume; +#endif + concat->mtd._get_unmapped_area = concat_get_unmapped_area; /* * Combine the erase block size info of the subdevices: @@ -771,3 +951,22 @@ struct mtd_info *mtd_concat_create(struct mtd_info *subdev[], /* subdevices to c return &concat->mtd; } + +/* + * This function destroys an MTD object obtained from concat_mtd_devs() + */ + +void mtd_concat_destroy(struct mtd_info *mtd) +{ + struct mtd_concat *concat = CONCAT(mtd); + if (concat->mtd.numeraseregions) + kfree(concat->mtd.eraseregions); + kfree(concat); +} + +EXPORT_SYMBOL(mtd_concat_create); +EXPORT_SYMBOL(mtd_concat_destroy); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Robert Kaiser "); +MODULE_DESCRIPTION("Generic support for concatenating of MTD devices"); diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 49c08145a7..cb27ff22be 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -2,130 +2,768 @@ * Core registration and callback routines for MTD * drivers and users. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright © 1999-2010 David Woodhouse + * Copyright © 2006 Red Hat UK Limited + * + * SPDX-License-Identifier: GPL-2.0+ + * */ -#include +#ifndef __UBOOT__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#else #include +#include #include +#endif + +#include +#include + +#include "mtdcore.h" + +#ifndef __UBOOT__ +/* + * backing device capabilities for non-mappable devices (such as NAND flash) + * - permits private mappings, copies are taken of the data + */ +static struct backing_dev_info mtd_bdi_unmappable = { + .capabilities = BDI_CAP_MAP_COPY, +}; + +/* + * backing device capabilities for R/O mappable devices (such as ROM) + * - permits private mappings, copies are taken of the data + * - permits non-writable shared mappings + */ +static struct backing_dev_info mtd_bdi_ro_mappable = { + .capabilities = (BDI_CAP_MAP_COPY | BDI_CAP_MAP_DIRECT | + BDI_CAP_EXEC_MAP | BDI_CAP_READ_MAP), +}; + +/* + * backing device capabilities for writable mappable devices (such as RAM) + * - permits private mappings, copies are taken of the data + * - permits non-writable shared mappings + */ +static struct backing_dev_info mtd_bdi_rw_mappable = { + .capabilities = (BDI_CAP_MAP_COPY | BDI_CAP_MAP_DIRECT | + BDI_CAP_EXEC_MAP | BDI_CAP_READ_MAP | + BDI_CAP_WRITE_MAP), +}; + +static int mtd_cls_suspend(struct device *dev, pm_message_t state); +static int mtd_cls_resume(struct device *dev); +static struct class mtd_class = { + .name = "mtd", + .owner = THIS_MODULE, + .suspend = mtd_cls_suspend, + .resume = mtd_cls_resume, +}; +#else struct mtd_info *mtd_table[MAX_MTD_DEVICES]; +#define MAX_IDR_ID 64 + +struct idr_layer { + int used; + void *ptr; +}; + +struct idr { + struct idr_layer id[MAX_IDR_ID]; +}; + +#define DEFINE_IDR(name) struct idr name; + +void idr_remove(struct idr *idp, int id) +{ + if (idp->id[id].used) + idp->id[id].used = 0; + + return; +} +void *idr_find(struct idr *idp, int id) +{ + if (idp->id[id].used) + return idp->id[id].ptr; + + return NULL; +} + +void *idr_get_next(struct idr *idp, int *next) +{ + void *ret; + int id = *next; + + ret = idr_find(idp, id); + if (ret) { + id ++; + if (!idp->id[id].used) + id = 0; + *next = id; + } else { + *next = 0; + } + + return ret; +} + +int idr_alloc(struct idr *idp, void *ptr, int start, int end, gfp_t gfp_mask) +{ + struct idr_layer *idl; + int i = 0; + + while (i < MAX_IDR_ID) { + idl = &idp->id[i]; + if (idl->used == 0) { + idl->used = 1; + idl->ptr = ptr; + return i; + } + i++; + } + return -ENOSPC; +} +#endif + +static DEFINE_IDR(mtd_idr); + +/* These are exported solely for the purpose of mtd_blkdevs.c. You + should not use them for _anything_ else */ +DEFINE_MUTEX(mtd_table_mutex); +EXPORT_SYMBOL_GPL(mtd_table_mutex); + +struct mtd_info *__mtd_next_device(int i) +{ + return idr_get_next(&mtd_idr, &i); +} +EXPORT_SYMBOL_GPL(__mtd_next_device); + +#ifndef __UBOOT__ +static LIST_HEAD(mtd_notifiers); + + +#define MTD_DEVT(index) MKDEV(MTD_CHAR_MAJOR, (index)*2) + +/* REVISIT once MTD uses the driver model better, whoever allocates + * the mtd_info will probably want to use the release() hook... + */ +static void mtd_release(struct device *dev) +{ + struct mtd_info __maybe_unused *mtd = dev_get_drvdata(dev); + dev_t index = MTD_DEVT(mtd->index); + + /* remove /dev/mtdXro node if needed */ + if (index) + device_destroy(&mtd_class, index + 1); +} + +static int mtd_cls_suspend(struct device *dev, pm_message_t state) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return mtd ? mtd_suspend(mtd) : 0; +} + +static int mtd_cls_resume(struct device *dev) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + if (mtd) + mtd_resume(mtd); + return 0; +} + +static ssize_t mtd_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + char *type; + + switch (mtd->type) { + case MTD_ABSENT: + type = "absent"; + break; + case MTD_RAM: + type = "ram"; + break; + case MTD_ROM: + type = "rom"; + break; + case MTD_NORFLASH: + type = "nor"; + break; + case MTD_NANDFLASH: + type = "nand"; + break; + case MTD_DATAFLASH: + type = "dataflash"; + break; + case MTD_UBIVOLUME: + type = "ubi"; + break; + case MTD_MLCNANDFLASH: + type = "mlc-nand"; + break; + default: + type = "unknown"; + } + + return snprintf(buf, PAGE_SIZE, "%s\n", type); +} +static DEVICE_ATTR(type, S_IRUGO, mtd_type_show, NULL); + +static ssize_t mtd_flags_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)mtd->flags); + +} +static DEVICE_ATTR(flags, S_IRUGO, mtd_flags_show, NULL); + +static ssize_t mtd_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%llu\n", + (unsigned long long)mtd->size); + +} +static DEVICE_ATTR(size, S_IRUGO, mtd_size_show, NULL); + +static ssize_t mtd_erasesize_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->erasesize); + +} +static DEVICE_ATTR(erasesize, S_IRUGO, mtd_erasesize_show, NULL); + +static ssize_t mtd_writesize_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->writesize); + +} +static DEVICE_ATTR(writesize, S_IRUGO, mtd_writesize_show, NULL); + +static ssize_t mtd_subpagesize_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + unsigned int subpagesize = mtd->writesize >> mtd->subpage_sft; + + return snprintf(buf, PAGE_SIZE, "%u\n", subpagesize); + +} +static DEVICE_ATTR(subpagesize, S_IRUGO, mtd_subpagesize_show, NULL); + +static ssize_t mtd_oobsize_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->oobsize); + +} +static DEVICE_ATTR(oobsize, S_IRUGO, mtd_oobsize_show, NULL); + +static ssize_t mtd_numeraseregions_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%u\n", mtd->numeraseregions); + +} +static DEVICE_ATTR(numeraseregions, S_IRUGO, mtd_numeraseregions_show, + NULL); + +static ssize_t mtd_name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", mtd->name); + +} +static DEVICE_ATTR(name, S_IRUGO, mtd_name_show, NULL); + +static ssize_t mtd_ecc_strength_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_strength); +} +static DEVICE_ATTR(ecc_strength, S_IRUGO, mtd_ecc_strength_show, NULL); + +static ssize_t mtd_bitflip_threshold_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%u\n", mtd->bitflip_threshold); +} + +static ssize_t mtd_bitflip_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + unsigned int bitflip_threshold; + int retval; + + retval = kstrtouint(buf, 0, &bitflip_threshold); + if (retval) + return retval; + + mtd->bitflip_threshold = bitflip_threshold; + return count; +} +static DEVICE_ATTR(bitflip_threshold, S_IRUGO | S_IWUSR, + mtd_bitflip_threshold_show, + mtd_bitflip_threshold_store); + +static ssize_t mtd_ecc_step_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_step_size); + +} +static DEVICE_ATTR(ecc_step_size, S_IRUGO, mtd_ecc_step_size_show, NULL); + +static struct attribute *mtd_attrs[] = { + &dev_attr_type.attr, + &dev_attr_flags.attr, + &dev_attr_size.attr, + &dev_attr_erasesize.attr, + &dev_attr_writesize.attr, + &dev_attr_subpagesize.attr, + &dev_attr_oobsize.attr, + &dev_attr_numeraseregions.attr, + &dev_attr_name.attr, + &dev_attr_ecc_strength.attr, + &dev_attr_ecc_step_size.attr, + &dev_attr_bitflip_threshold.attr, + NULL, +}; +ATTRIBUTE_GROUPS(mtd); + +static struct device_type mtd_devtype = { + .name = "mtd", + .groups = mtd_groups, + .release = mtd_release, +}; +#endif + +/** + * add_mtd_device - register an MTD device + * @mtd: pointer to new MTD device info structure + * + * Add a device to the list of MTD devices present in the system, and + * notify each currently active MTD 'user' of its arrival. Returns + * zero on success or 1 on failure, which currently will only happen + * if there is insufficient memory or a sysfs error. + */ + int add_mtd_device(struct mtd_info *mtd) { - int i; +#ifndef __UBOOT__ + struct mtd_notifier *not; +#endif + int i, error; + +#ifndef __UBOOT__ + if (!mtd->backing_dev_info) { + switch (mtd->type) { + case MTD_RAM: + mtd->backing_dev_info = &mtd_bdi_rw_mappable; + break; + case MTD_ROM: + mtd->backing_dev_info = &mtd_bdi_ro_mappable; + break; + default: + mtd->backing_dev_info = &mtd_bdi_unmappable; + break; + } + } +#endif BUG_ON(mtd->writesize == 0); + mutex_lock(&mtd_table_mutex); - for (i = 0; i < MAX_MTD_DEVICES; i++) - if (!mtd_table[i]) { - mtd_table[i] = mtd; - mtd->index = i; - mtd->usecount = 0; + i = idr_alloc(&mtd_idr, mtd, 0, 0, GFP_KERNEL); + if (i < 0) + goto fail_locked; - /* default value if not set by driver */ - if (mtd->bitflip_threshold == 0) - mtd->bitflip_threshold = mtd->ecc_strength; + mtd->index = i; + mtd->usecount = 0; + /* default value if not set by driver */ + if (mtd->bitflip_threshold == 0) + mtd->bitflip_threshold = mtd->ecc_strength; - /* No need to get a refcount on the module containing - the notifier, since we hold the mtd_table_mutex */ + if (is_power_of_2(mtd->erasesize)) + mtd->erasesize_shift = ffs(mtd->erasesize) - 1; + else + mtd->erasesize_shift = 0; - /* We _know_ we aren't being removed, because - our caller is still holding us here. So none - of this try_ nonsense, and no bitching about it - either. :) */ - return 0; - } + if (is_power_of_2(mtd->writesize)) + mtd->writesize_shift = ffs(mtd->writesize) - 1; + else + mtd->writesize_shift = 0; + + mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1; + mtd->writesize_mask = (1 << mtd->writesize_shift) - 1; + + /* Some chips always power up locked. Unlock them now */ + if ((mtd->flags & MTD_WRITEABLE) && (mtd->flags & MTD_POWERUP_LOCK)) { + error = mtd_unlock(mtd, 0, mtd->size); + if (error && error != -EOPNOTSUPP) + printk(KERN_WARNING + "%s: unlock failed, writes may not work\n", + mtd->name); + } + +#ifndef __UBOOT__ + /* Caller should have set dev.parent to match the + * physical device. + */ + mtd->dev.type = &mtd_devtype; + mtd->dev.class = &mtd_class; + mtd->dev.devt = MTD_DEVT(i); + dev_set_name(&mtd->dev, "mtd%d", i); + dev_set_drvdata(&mtd->dev, mtd); + if (device_register(&mtd->dev) != 0) + goto fail_added; + + if (MTD_DEVT(i)) + device_create(&mtd_class, mtd->dev.parent, + MTD_DEVT(i) + 1, + NULL, "mtd%dro", i); + pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name); + /* No need to get a refcount on the module containing + the notifier, since we hold the mtd_table_mutex */ + list_for_each_entry(not, &mtd_notifiers, list) + not->add(mtd); +#else + pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name); +#endif + + mutex_unlock(&mtd_table_mutex); + /* We _know_ we aren't being removed, because + our caller is still holding us here. So none + of this try_ nonsense, and no bitching about it + either. :) */ + __module_get(THIS_MODULE); + return 0; + +#ifndef __UBOOT__ +fail_added: + idr_remove(&mtd_idr, i); +#endif +fail_locked: + mutex_unlock(&mtd_table_mutex); return 1; } /** - * del_mtd_device - unregister an MTD device - * @mtd: pointer to MTD device info structure + * del_mtd_device - unregister an MTD device + * @mtd: pointer to MTD device info structure * - * Remove a device from the list of MTD devices present in the system, - * and notify each currently active MTD 'user' of its departure. - * Returns zero on success or 1 on failure, which currently will happen - * if the requested device does not appear to be present in the list. + * Remove a device from the list of MTD devices present in the system, + * and notify each currently active MTD 'user' of its departure. + * Returns zero on success or 1 on failure, which currently will happen + * if the requested device does not appear to be present in the list. */ + int del_mtd_device(struct mtd_info *mtd) { int ret; +#ifndef __UBOOT__ + struct mtd_notifier *not; +#endif - if (mtd_table[mtd->index] != mtd) { + mutex_lock(&mtd_table_mutex); + + if (idr_find(&mtd_idr, mtd->index) != mtd) { ret = -ENODEV; - } else if (mtd->usecount) { - printk(KERN_NOTICE "Removing MTD device #%d (%s)" - " with use count %d\n", - mtd->index, mtd->name, mtd->usecount); + goto out_error; + } + +#ifndef __UBOOT__ + /* No need to get a refcount on the module containing + the notifier, since we hold the mtd_table_mutex */ + list_for_each_entry(not, &mtd_notifiers, list) + not->remove(mtd); +#endif + + if (mtd->usecount) { + printk(KERN_NOTICE "Removing MTD device #%d (%s) with use count %d\n", + mtd->index, mtd->name, mtd->usecount); ret = -EBUSY; } else { - /* No need to get a refcount on the module containing - * the notifier, since we hold the mtd_table_mutex */ - mtd_table[mtd->index] = NULL; +#ifndef __UBOOT__ + device_unregister(&mtd->dev); +#endif + + idr_remove(&mtd_idr, mtd->index); + module_put(THIS_MODULE); ret = 0; } +out_error: + mutex_unlock(&mtd_table_mutex); return ret; } +#ifndef __UBOOT__ +/** + * mtd_device_parse_register - parse partitions and register an MTD device. + * + * @mtd: the MTD device to register + * @types: the list of MTD partition probes to try, see + * 'parse_mtd_partitions()' for more information + * @parser_data: MTD partition parser-specific data + * @parts: fallback partition information to register, if parsing fails; + * only valid if %nr_parts > %0 + * @nr_parts: the number of partitions in parts, if zero then the full + * MTD device is registered if no partition info is found + * + * This function aggregates MTD partitions parsing (done by + * 'parse_mtd_partitions()') and MTD device and partitions registering. It + * basically follows the most common pattern found in many MTD drivers: + * + * * It first tries to probe partitions on MTD device @mtd using parsers + * specified in @types (if @types is %NULL, then the default list of parsers + * is used, see 'parse_mtd_partitions()' for more information). If none are + * found this functions tries to fallback to information specified in + * @parts/@nr_parts. + * * If any partitioning info was found, this function registers the found + * partitions. + * * If no partitions were found this function just registers the MTD device + * @mtd and exits. + * + * Returns zero in case of success and a negative error code in case of failure. + */ +int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types, + struct mtd_part_parser_data *parser_data, + const struct mtd_partition *parts, + int nr_parts) +{ + int err; + struct mtd_partition *real_parts; + + err = parse_mtd_partitions(mtd, types, &real_parts, parser_data); + if (err <= 0 && nr_parts && parts) { + real_parts = kmemdup(parts, sizeof(*parts) * nr_parts, + GFP_KERNEL); + if (!real_parts) + err = -ENOMEM; + else + err = nr_parts; + } + + if (err > 0) { + err = add_mtd_partitions(mtd, real_parts, err); + kfree(real_parts); + } else if (err == 0) { + err = add_mtd_device(mtd); + if (err == 1) + err = -ENODEV; + } + + return err; +} +EXPORT_SYMBOL_GPL(mtd_device_parse_register); + +/** + * mtd_device_unregister - unregister an existing MTD device. + * + * @master: the MTD device to unregister. This will unregister both the master + * and any partitions if registered. + */ +int mtd_device_unregister(struct mtd_info *master) +{ + int err; + + err = del_mtd_partitions(master); + if (err) + return err; + + if (!device_is_registered(&master->dev)) + return 0; + + return del_mtd_device(master); +} +EXPORT_SYMBOL_GPL(mtd_device_unregister); + +/** + * register_mtd_user - register a 'user' of MTD devices. + * @new: pointer to notifier info structure + * + * Registers a pair of callbacks function to be called upon addition + * or removal of MTD devices. Causes the 'add' callback to be immediately + * invoked for each MTD device currently present in the system. + */ +void register_mtd_user (struct mtd_notifier *new) +{ + struct mtd_info *mtd; + + mutex_lock(&mtd_table_mutex); + + list_add(&new->list, &mtd_notifiers); + + __module_get(THIS_MODULE); + + mtd_for_each_device(mtd) + new->add(mtd); + + mutex_unlock(&mtd_table_mutex); +} +EXPORT_SYMBOL_GPL(register_mtd_user); + +/** + * unregister_mtd_user - unregister a 'user' of MTD devices. + * @old: pointer to notifier info structure + * + * Removes a callback function pair from the list of 'users' to be + * notified upon addition or removal of MTD devices. Causes the + * 'remove' callback to be immediately invoked for each MTD device + * currently present in the system. + */ +int unregister_mtd_user (struct mtd_notifier *old) +{ + struct mtd_info *mtd; + + mutex_lock(&mtd_table_mutex); + + module_put(THIS_MODULE); + + mtd_for_each_device(mtd) + old->remove(mtd); + + list_del(&old->list); + mutex_unlock(&mtd_table_mutex); + return 0; +} +EXPORT_SYMBOL_GPL(unregister_mtd_user); +#endif + /** * get_mtd_device - obtain a validated handle for an MTD device * @mtd: last known address of the required MTD device * @num: internal device number of the required MTD device * * Given a number and NULL address, return the num'th entry in the device - * table, if any. Given an address and num == -1, search the device table - * for a device with that address and return if it's still present. Given - * both, return the num'th driver only if its address matches. Return - * error code if not. + * table, if any. Given an address and num == -1, search the device table + * for a device with that address and return if it's still present. Given + * both, return the num'th driver only if its address matches. Return + * error code if not. */ struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num) { - struct mtd_info *ret = NULL; - int i, err = -ENODEV; + struct mtd_info *ret = NULL, *other; + int err = -ENODEV; + + mutex_lock(&mtd_table_mutex); if (num == -1) { - for (i = 0; i < MAX_MTD_DEVICES; i++) - if (mtd_table[i] == mtd) - ret = mtd_table[i]; - } else if (num < MAX_MTD_DEVICES) { - ret = mtd_table[num]; + mtd_for_each_device(other) { + if (other == mtd) { + ret = mtd; + break; + } + } + } else if (num >= 0) { + ret = idr_find(&mtd_idr, num); if (mtd && mtd != ret) ret = NULL; } - if (!ret) - goto out_unlock; + if (!ret) { + ret = ERR_PTR(err); + goto out; + } - ret->usecount++; + err = __get_mtd_device(ret); + if (err) + ret = ERR_PTR(err); +out: + mutex_unlock(&mtd_table_mutex); return ret; +} +EXPORT_SYMBOL_GPL(get_mtd_device); -out_unlock: - return ERR_PTR(err); + +int __get_mtd_device(struct mtd_info *mtd) +{ + int err; + + if (!try_module_get(mtd->owner)) + return -ENODEV; + + if (mtd->_get_device) { + err = mtd->_get_device(mtd); + + if (err) { + module_put(mtd->owner); + return err; + } + } + mtd->usecount++; + return 0; } +EXPORT_SYMBOL_GPL(__get_mtd_device); /** - * get_mtd_device_nm - obtain a validated handle for an MTD device by - * device name - * @name: MTD device name to open + * get_mtd_device_nm - obtain a validated handle for an MTD device by + * device name + * @name: MTD device name to open * - * This function returns MTD device description structure in case of - * success and an error code in case of failure. + * This function returns MTD device description structure in case of + * success and an error code in case of failure. */ struct mtd_info *get_mtd_device_nm(const char *name) { - int i, err = -ENODEV; - struct mtd_info *mtd = NULL; + int err = -ENODEV; + struct mtd_info *mtd = NULL, *other; + + mutex_lock(&mtd_table_mutex); - for (i = 0; i < MAX_MTD_DEVICES; i++) { - if (mtd_table[i] && !strcmp(name, mtd_table[i]->name)) { - mtd = mtd_table[i]; + mtd_for_each_device(other) { + if (!strcmp(name, other->name)) { + mtd = other; break; } } @@ -133,20 +771,18 @@ struct mtd_info *get_mtd_device_nm(const char *name) if (!mtd) goto out_unlock; - mtd->usecount++; + err = __get_mtd_device(mtd); + if (err) + goto out_unlock; + + mutex_unlock(&mtd_table_mutex); return mtd; out_unlock: + mutex_unlock(&mtd_table_mutex); return ERR_PTR(err); } - -void put_mtd_device(struct mtd_info *mtd) -{ - int c; - - c = --mtd->usecount; - BUG_ON(c < 0); -} +EXPORT_SYMBOL_GPL(get_mtd_device_nm); #if defined(CONFIG_CMD_MTDPARTS_SPREAD) /** @@ -167,7 +803,7 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, *truncated = 0; *len_incl_bad = 0; - if (!mtd->block_isbad) { + if (!mtd->_block_isbad) { *len_incl_bad = length; return; } @@ -183,7 +819,7 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, block_len = mtd->erasesize - (offset & (mtd->erasesize - 1)); - if (!mtd->block_isbad(mtd, offset & ~(mtd->erasesize - 1))) + if (!mtd->_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) len_excl_bad += block_len; *len_incl_bad += block_len; @@ -192,7 +828,28 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, } #endif /* defined(CONFIG_CMD_MTDPARTS_SPREAD) */ - /* +void put_mtd_device(struct mtd_info *mtd) +{ + mutex_lock(&mtd_table_mutex); + __put_mtd_device(mtd); + mutex_unlock(&mtd_table_mutex); + +} +EXPORT_SYMBOL_GPL(put_mtd_device); + +void __put_mtd_device(struct mtd_info *mtd) +{ + --mtd->usecount; + BUG_ON(mtd->usecount < 0); + + if (mtd->_put_device) + mtd->_put_device(mtd); + + module_put(mtd->owner); +} +EXPORT_SYMBOL_GPL(__put_mtd_device); + +/* * Erase is an asynchronous operation. Device drivers are supposed * to call instr->callback() whenever the operation completes, even * if it completes with a failure. @@ -213,16 +870,82 @@ int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) } return mtd->_erase(mtd, instr); } +EXPORT_SYMBOL_GPL(mtd_erase); + +#ifndef __UBOOT__ +/* + * This stuff for eXecute-In-Place. phys is optional and may be set to NULL. + */ +int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, + void **virt, resource_size_t *phys) +{ + *retlen = 0; + *virt = NULL; + if (phys) + *phys = 0; + if (!mtd->_point) + return -EOPNOTSUPP; + if (from < 0 || from > mtd->size || len > mtd->size - from) + return -EINVAL; + if (!len) + return 0; + return mtd->_point(mtd, from, len, retlen, virt, phys); +} +EXPORT_SYMBOL_GPL(mtd_point); + +/* We probably shouldn't allow XIP if the unpoint isn't a NULL */ +int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len) +{ + if (!mtd->_point) + return -EOPNOTSUPP; + if (from < 0 || from > mtd->size || len > mtd->size - from) + return -EINVAL; + if (!len) + return 0; + return mtd->_unpoint(mtd, from, len); +} +EXPORT_SYMBOL_GPL(mtd_unpoint); +#endif + +/* + * Allow NOMMU mmap() to directly map the device (if not NULL) + * - return the address to which the offset maps + * - return -ENOSYS to indicate refusal to do the mapping + */ +unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len, + unsigned long offset, unsigned long flags) +{ + if (!mtd->_get_unmapped_area) + return -EOPNOTSUPP; + if (offset > mtd->size || len > mtd->size - offset) + return -EINVAL; + return mtd->_get_unmapped_area(mtd, len, offset, flags); +} +EXPORT_SYMBOL_GPL(mtd_get_unmapped_area); int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { + int ret_code; + *retlen = 0; if (from < 0 || from > mtd->size || len > mtd->size - from) return -EINVAL; if (!len) return 0; - return mtd->_read(mtd, from, len, retlen, buf); + + /* + * In the absence of an error, drivers return a non-negative integer + * representing the maximum number of bitflips that were corrected on + * any one ecc region (if applicable; zero otherwise). + */ + ret_code = mtd->_read(mtd, from, len, retlen, buf); + if (unlikely(ret_code < 0)) + return ret_code; + if (mtd->ecc_strength == 0) + return 0; /* device lacks ecc */ + return ret_code >= mtd->bitflip_threshold ? -EUCLEAN : 0; } +EXPORT_SYMBOL_GPL(mtd_read); int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) @@ -236,6 +959,7 @@ int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, return 0; return mtd->_write(mtd, to, len, retlen, buf); } +EXPORT_SYMBOL_GPL(mtd_write); /* * In blackbox flight recorder like scenarios we want to make successful writes @@ -258,29 +982,44 @@ int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, return 0; return mtd->_panic_write(mtd, to, len, retlen, buf); } +EXPORT_SYMBOL_GPL(mtd_panic_write); int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { + int ret_code; ops->retlen = ops->oobretlen = 0; if (!mtd->_read_oob) return -EOPNOTSUPP; - return mtd->_read_oob(mtd, from, ops); + /* + * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics + * similar to mtd->_read(), returning a non-negative integer + * representing max bitflips. In other cases, mtd->_read_oob() may + * return -EUCLEAN. In all cases, perform similar logic to mtd_read(). + */ + ret_code = mtd->_read_oob(mtd, from, ops); + if (unlikely(ret_code < 0)) + return ret_code; + if (mtd->ecc_strength == 0) + return 0; /* device lacks ecc */ + return ret_code >= mtd->bitflip_threshold ? -EUCLEAN : 0; } +EXPORT_SYMBOL_GPL(mtd_read_oob); /* * Method to access the protection register area, present in some flash * devices. The user data is one time programmable but the factory data is read * only. */ -int mtd_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf, - size_t len) +int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, + struct otp_info *buf) { if (!mtd->_get_fact_prot_info) return -EOPNOTSUPP; if (!len) return 0; - return mtd->_get_fact_prot_info(mtd, buf, len); + return mtd->_get_fact_prot_info(mtd, len, retlen, buf); } +EXPORT_SYMBOL_GPL(mtd_get_fact_prot_info); int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) @@ -292,16 +1031,18 @@ int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, return 0; return mtd->_read_fact_prot_reg(mtd, from, len, retlen, buf); } +EXPORT_SYMBOL_GPL(mtd_read_fact_prot_reg); -int mtd_get_user_prot_info(struct mtd_info *mtd, struct otp_info *buf, - size_t len) +int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, + struct otp_info *buf) { if (!mtd->_get_user_prot_info) return -EOPNOTSUPP; if (!len) return 0; - return mtd->_get_user_prot_info(mtd, buf, len); + return mtd->_get_user_prot_info(mtd, len, retlen, buf); } +EXPORT_SYMBOL_GPL(mtd_get_user_prot_info); int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) @@ -313,17 +1054,29 @@ int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, return 0; return mtd->_read_user_prot_reg(mtd, from, len, retlen, buf); } +EXPORT_SYMBOL_GPL(mtd_read_user_prot_reg); int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, u_char *buf) { + int ret; + *retlen = 0; if (!mtd->_write_user_prot_reg) return -EOPNOTSUPP; if (!len) return 0; - return mtd->_write_user_prot_reg(mtd, to, len, retlen, buf); + ret = mtd->_write_user_prot_reg(mtd, to, len, retlen, buf); + if (ret) + return ret; + + /* + * If no data could be written at all, we are out of memory and + * must return -ENOSPC. + */ + return (*retlen) ? 0 : -ENOSPC; } +EXPORT_SYMBOL_GPL(mtd_write_user_prot_reg); int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len) { @@ -333,6 +1086,7 @@ int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len) return 0; return mtd->_lock_user_prot_reg(mtd, from, len); } +EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg); /* Chip-supported device locking */ int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) @@ -345,6 +1099,7 @@ int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) return 0; return mtd->_lock(mtd, ofs, len); } +EXPORT_SYMBOL_GPL(mtd_lock); int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) { @@ -356,6 +1111,19 @@ int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) return 0; return mtd->_unlock(mtd, ofs, len); } +EXPORT_SYMBOL_GPL(mtd_unlock); + +int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) +{ + if (!mtd->_is_locked) + return -EOPNOTSUPP; + if (ofs < 0 || ofs > mtd->size || len > mtd->size - ofs) + return -EINVAL; + if (!len) + return 0; + return mtd->_is_locked(mtd, ofs, len); +} +EXPORT_SYMBOL_GPL(mtd_is_locked); int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs) { @@ -365,6 +1133,7 @@ int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs) return -EINVAL; return mtd->_block_isbad(mtd, ofs); } +EXPORT_SYMBOL_GPL(mtd_block_isbad); int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs) { @@ -376,4 +1145,225 @@ int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs) return -EROFS; return mtd->_block_markbad(mtd, ofs); } +EXPORT_SYMBOL_GPL(mtd_block_markbad); + +#ifndef __UBOOT__ +/* + * default_mtd_writev - the default writev method + * @mtd: mtd device description object pointer + * @vecs: the vectors to write + * @count: count of vectors in @vecs + * @to: the MTD device offset to write to + * @retlen: on exit contains the count of bytes written to the MTD device. + * + * This function returns zero in case of success and a negative error code in + * case of failure. + */ +static int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t *retlen) +{ + unsigned long i; + size_t totlen = 0, thislen; + int ret = 0; + + for (i = 0; i < count; i++) { + if (!vecs[i].iov_len) + continue; + ret = mtd_write(mtd, to, vecs[i].iov_len, &thislen, + vecs[i].iov_base); + totlen += thislen; + if (ret || thislen != vecs[i].iov_len) + break; + to += vecs[i].iov_len; + } + *retlen = totlen; + return ret; +} + +/* + * mtd_writev - the vector-based MTD write method + * @mtd: mtd device description object pointer + * @vecs: the vectors to write + * @count: count of vectors in @vecs + * @to: the MTD device offset to write to + * @retlen: on exit contains the count of bytes written to the MTD device. + * + * This function returns zero in case of success and a negative error code in + * case of failure. + */ +int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t *retlen) +{ + *retlen = 0; + if (!(mtd->flags & MTD_WRITEABLE)) + return -EROFS; + if (!mtd->_writev) + return default_mtd_writev(mtd, vecs, count, to, retlen); + return mtd->_writev(mtd, vecs, count, to, retlen); +} +EXPORT_SYMBOL_GPL(mtd_writev); + +/** + * mtd_kmalloc_up_to - allocate a contiguous buffer up to the specified size + * @mtd: mtd device description object pointer + * @size: a pointer to the ideal or maximum size of the allocation, points + * to the actual allocation size on success. + * + * This routine attempts to allocate a contiguous kernel buffer up to + * the specified size, backing off the size of the request exponentially + * until the request succeeds or until the allocation size falls below + * the system page size. This attempts to make sure it does not adversely + * impact system performance, so when allocating more than one page, we + * ask the memory allocator to avoid re-trying, swapping, writing back + * or performing I/O. + * + * Note, this function also makes sure that the allocated buffer is aligned to + * the MTD device's min. I/O unit, i.e. the "mtd->writesize" value. + * + * This is called, for example by mtd_{read,write} and jffs2_scan_medium, + * to handle smaller (i.e. degraded) buffer allocations under low- or + * fragmented-memory situations where such reduced allocations, from a + * requested ideal, are allowed. + * + * Returns a pointer to the allocated buffer on success; otherwise, NULL. + */ +void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size) +{ + gfp_t flags = __GFP_NOWARN | __GFP_WAIT | + __GFP_NORETRY | __GFP_NO_KSWAPD; + size_t min_alloc = max_t(size_t, mtd->writesize, PAGE_SIZE); + void *kbuf; + + *size = min_t(size_t, *size, KMALLOC_MAX_SIZE); + + while (*size > min_alloc) { + kbuf = kmalloc(*size, flags); + if (kbuf) + return kbuf; + + *size >>= 1; + *size = ALIGN(*size, mtd->writesize); + } + + /* + * For the last resort allocation allow 'kmalloc()' to do all sorts of + * things (write-back, dropping caches, etc) by using GFP_KERNEL. + */ + return kmalloc(*size, GFP_KERNEL); +} +EXPORT_SYMBOL_GPL(mtd_kmalloc_up_to); +#endif + +#ifdef CONFIG_PROC_FS + +/*====================================================================*/ +/* Support for /proc/mtd */ + +static int mtd_proc_show(struct seq_file *m, void *v) +{ + struct mtd_info *mtd; + + seq_puts(m, "dev: size erasesize name\n"); + mutex_lock(&mtd_table_mutex); + mtd_for_each_device(mtd) { + seq_printf(m, "mtd%d: %8.8llx %8.8x \"%s\"\n", + mtd->index, (unsigned long long)mtd->size, + mtd->erasesize, mtd->name); + } + mutex_unlock(&mtd_table_mutex); + return 0; +} + +static int mtd_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, mtd_proc_show, NULL); +} + +static const struct file_operations mtd_proc_ops = { + .open = mtd_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +#endif /* CONFIG_PROC_FS */ + +/*====================================================================*/ +/* Init code */ + +#ifndef __UBOOT__ +static int __init mtd_bdi_init(struct backing_dev_info *bdi, const char *name) +{ + int ret; + + ret = bdi_init(bdi); + if (!ret) + ret = bdi_register(bdi, NULL, "%s", name); + + if (ret) + bdi_destroy(bdi); + + return ret; +} + +static struct proc_dir_entry *proc_mtd; + +static int __init init_mtd(void) +{ + int ret; + + ret = class_register(&mtd_class); + if (ret) + goto err_reg; + + ret = mtd_bdi_init(&mtd_bdi_unmappable, "mtd-unmap"); + if (ret) + goto err_bdi1; + + ret = mtd_bdi_init(&mtd_bdi_ro_mappable, "mtd-romap"); + if (ret) + goto err_bdi2; + + ret = mtd_bdi_init(&mtd_bdi_rw_mappable, "mtd-rwmap"); + if (ret) + goto err_bdi3; + + proc_mtd = proc_create("mtd", 0, NULL, &mtd_proc_ops); + + ret = init_mtdchar(); + if (ret) + goto out_procfs; + + return 0; + +out_procfs: + if (proc_mtd) + remove_proc_entry("mtd", NULL); +err_bdi3: + bdi_destroy(&mtd_bdi_ro_mappable); +err_bdi2: + bdi_destroy(&mtd_bdi_unmappable); +err_bdi1: + class_unregister(&mtd_class); +err_reg: + pr_err("Error registering mtd class or bdi: %d\n", ret); + return ret; +} + +static void __exit cleanup_mtd(void) +{ + cleanup_mtdchar(); + if (proc_mtd) + remove_proc_entry("mtd", NULL); + class_unregister(&mtd_class); + bdi_destroy(&mtd_bdi_unmappable); + bdi_destroy(&mtd_bdi_ro_mappable); + bdi_destroy(&mtd_bdi_rw_mappable); +} + +module_init(init_mtd); +module_exit(cleanup_mtd); +#endif +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("David Woodhouse "); +MODULE_DESCRIPTION("Core MTD registration and access routines"); diff --git a/drivers/mtd/mtdcore.h b/drivers/mtd/mtdcore.h new file mode 100644 index 0000000000..7b0353399a --- /dev/null +++ b/drivers/mtd/mtdcore.h @@ -0,0 +1,23 @@ +/* + * These are exported solely for the purpose of mtd_blkdevs.c and mtdchar.c. + * You should not use them for _anything_ else. + */ + +extern struct mutex mtd_table_mutex; + +struct mtd_info *__mtd_next_device(int i); +int add_mtd_device(struct mtd_info *mtd); +int del_mtd_device(struct mtd_info *mtd); +int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); +int del_mtd_partitions(struct mtd_info *); +int parse_mtd_partitions(struct mtd_info *master, const char * const *types, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data); + +int __init init_mtdchar(void); +void __exit cleanup_mtdchar(void); + +#define mtd_for_each_device(mtd) \ + for ((mtd) = __mtd_next_device(0); \ + (mtd) != NULL; \ + (mtd) = __mtd_next_device(mtd->index + 1)) diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 9dfe7bbc9a..cfbaa3d9a0 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -1,35 +1,49 @@ /* * Simple MTD partitioning layer * - * (C) 2000 Nicolas Pitre + * Copyright © 2000 Nicolas Pitre + * Copyright © 2002 Thomas Gleixner + * Copyright © 2000-2010 David Woodhouse * - * This code is GPL + * SPDX-License-Identifier: GPL-2.0+ * - * 02-21-2002 Thomas Gleixner - * added support for read_oob, write_oob */ +#ifndef __UBOOT__ +#include +#include +#include +#include +#include +#include +#endif + #include #include #include +#include +#include -#include -#include #include #include -#include +#include + +#include "mtdcore.h" /* Our partition linked list */ -struct list_head mtd_partitions; +static LIST_HEAD(mtd_partitions); +#ifndef __UBOOT__ +static DEFINE_MUTEX(mtd_partitions_mutex); +#else +DEFINE_MUTEX(mtd_partitions_mutex); +#endif /* Our partition node structure */ struct mtd_part { struct mtd_info mtd; struct mtd_info *master; uint64_t offset; - int index; struct list_head list; - int registered; }; /* @@ -39,6 +53,30 @@ struct mtd_part { #define PART(x) ((struct mtd_part *)(x)) +#ifdef __UBOOT__ +/* from mm/util.c */ + +/** + * kstrdup - allocate space for and copy an existing string + * @s: the string to duplicate + * @gfp: the GFP mask used in the kmalloc() call when allocating memory + */ +char *kstrdup(const char *s, gfp_t gfp) +{ + size_t len; + char *buf; + + if (!s) + return NULL; + + len = strlen(s) + 1; + buf = kmalloc(len, gfp); + if (buf) + memcpy(buf, s, len); + return buf; +} +#endif + /* * MTD methods which simply translate the effective address and pass through * to the _real_ device. @@ -52,16 +90,47 @@ static int part_read(struct mtd_info *mtd, loff_t from, size_t len, int res; stats = part->master->ecc_stats; - res = mtd_read(part->master, from + part->offset, len, retlen, buf); - if (unlikely(res)) { - if (mtd_is_bitflip(res)) - mtd->ecc_stats.corrected += part->master->ecc_stats.corrected - stats.corrected; - if (mtd_is_eccerr(res)) - mtd->ecc_stats.failed += part->master->ecc_stats.failed - stats.failed; - } + res = part->master->_read(part->master, from + part->offset, len, + retlen, buf); + if (unlikely(mtd_is_eccerr(res))) + mtd->ecc_stats.failed += + part->master->ecc_stats.failed - stats.failed; + else + mtd->ecc_stats.corrected += + part->master->ecc_stats.corrected - stats.corrected; return res; } +#ifndef __UBOOT__ +static int part_point(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, void **virt, resource_size_t *phys) +{ + struct mtd_part *part = PART(mtd); + + return part->master->_point(part->master, from + part->offset, len, + retlen, virt, phys); +} + +static int part_unpoint(struct mtd_info *mtd, loff_t from, size_t len) +{ + struct mtd_part *part = PART(mtd); + + return part->master->_unpoint(part->master, from + part->offset, len); +} +#endif + +static unsigned long part_get_unmapped_area(struct mtd_info *mtd, + unsigned long len, + unsigned long offset, + unsigned long flags) +{ + struct mtd_part *part = PART(mtd); + + offset += part->offset; + return part->master->_get_unmapped_area(part->master, len, offset, + flags); +} + static int part_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { @@ -72,8 +141,25 @@ static int part_read_oob(struct mtd_info *mtd, loff_t from, return -EINVAL; if (ops->datbuf && from + ops->len > mtd->size) return -EINVAL; - res = mtd_read_oob(part->master, from + part->offset, ops); + /* + * If OOB is also requested, make sure that we do not read past the end + * of this partition. + */ + if (ops->oobbuf) { + size_t len, pages; + + if (ops->mode == MTD_OPS_AUTO_OOB) + len = mtd->oobavail; + else + len = mtd->oobsize; + pages = mtd_div_by_ws(mtd->size, mtd); + pages -= mtd_div_by_ws(from, mtd); + if (ops->ooboffs + ops->ooblen > pages * len) + return -EINVAL; + } + + res = part->master->_read_oob(part->master, from + part->offset, ops); if (unlikely(res)) { if (mtd_is_bitflip(res)) mtd->ecc_stats.corrected++; @@ -87,35 +173,48 @@ static int part_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct mtd_part *part = PART(mtd); - return mtd_read_user_prot_reg(part->master, from, len, retlen, buf); + return part->master->_read_user_prot_reg(part->master, from, len, + retlen, buf); } -static int part_get_user_prot_info(struct mtd_info *mtd, - struct otp_info *buf, size_t len) +static int part_get_user_prot_info(struct mtd_info *mtd, size_t len, + size_t *retlen, struct otp_info *buf) { struct mtd_part *part = PART(mtd); - return mtd_get_user_prot_info(part->master, buf, len); + return part->master->_get_user_prot_info(part->master, len, retlen, + buf); } static int part_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct mtd_part *part = PART(mtd); - return mtd_read_fact_prot_reg(part->master, from, len, retlen, buf); + return part->master->_read_fact_prot_reg(part->master, from, len, + retlen, buf); } -static int part_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf, - size_t len) +static int part_get_fact_prot_info(struct mtd_info *mtd, size_t len, + size_t *retlen, struct otp_info *buf) { struct mtd_part *part = PART(mtd); - return mtd_get_fact_prot_info(part->master, buf, len); + return part->master->_get_fact_prot_info(part->master, len, retlen, + buf); } static int part_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) { struct mtd_part *part = PART(mtd); - return mtd_write(part->master, to + part->offset, len, retlen, buf); + return part->master->_write(part->master, to + part->offset, len, + retlen, buf); +} + +static int part_panic_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + struct mtd_part *part = PART(mtd); + return part->master->_panic_write(part->master, to + part->offset, len, + retlen, buf); } static int part_write_oob(struct mtd_info *mtd, loff_t to, @@ -127,30 +226,41 @@ static int part_write_oob(struct mtd_info *mtd, loff_t to, return -EINVAL; if (ops->datbuf && to + ops->len > mtd->size) return -EINVAL; - return mtd_write_oob(part->master, to + part->offset, ops); + return part->master->_write_oob(part->master, to + part->offset, ops); } static int part_write_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct mtd_part *part = PART(mtd); - return mtd_write_user_prot_reg(part->master, from, len, retlen, buf); + return part->master->_write_user_prot_reg(part->master, from, len, + retlen, buf); } static int part_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len) { struct mtd_part *part = PART(mtd); - return mtd_lock_user_prot_reg(part->master, from, len); + return part->master->_lock_user_prot_reg(part->master, from, len); } +#ifndef __UBOOT__ +static int part_writev(struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t *retlen) +{ + struct mtd_part *part = PART(mtd); + return part->master->_writev(part->master, vecs, count, + to + part->offset, retlen); +} +#endif + static int part_erase(struct mtd_info *mtd, struct erase_info *instr) { struct mtd_part *part = PART(mtd); int ret; instr->addr += part->offset; - ret = mtd_erase(part->master, instr); + ret = part->master->_erase(part->master, instr); if (ret) { if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) instr->fail_addr -= part->offset; @@ -171,30 +281,51 @@ void mtd_erase_callback(struct erase_info *instr) if (instr->callback) instr->callback(instr); } +EXPORT_SYMBOL_GPL(mtd_erase_callback); static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) { struct mtd_part *part = PART(mtd); - return mtd_lock(part->master, ofs + part->offset, len); + return part->master->_lock(part->master, ofs + part->offset, len); } static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) { struct mtd_part *part = PART(mtd); - return mtd_unlock(part->master, ofs + part->offset, len); + return part->master->_unlock(part->master, ofs + part->offset, len); +} + +static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) +{ + struct mtd_part *part = PART(mtd); + return part->master->_is_locked(part->master, ofs + part->offset, len); } static void part_sync(struct mtd_info *mtd) { struct mtd_part *part = PART(mtd); - mtd_sync(part->master); + part->master->_sync(part->master); } +#ifndef __UBOOT__ +static int part_suspend(struct mtd_info *mtd) +{ + struct mtd_part *part = PART(mtd); + return part->master->_suspend(part->master); +} + +static void part_resume(struct mtd_info *mtd) +{ + struct mtd_part *part = PART(mtd); + part->master->_resume(part->master); +} +#endif + static int part_block_isbad(struct mtd_info *mtd, loff_t ofs) { struct mtd_part *part = PART(mtd); ofs += part->offset; - return mtd_block_isbad(part->master, ofs); + return part->master->_block_isbad(part->master, ofs); } static int part_block_markbad(struct mtd_info *mtd, loff_t ofs) @@ -203,12 +334,18 @@ static int part_block_markbad(struct mtd_info *mtd, loff_t ofs) int res; ofs += part->offset; - res = mtd_block_markbad(part->master, ofs); + res = part->master->_block_markbad(part->master, ofs); if (!res) mtd->ecc_stats.badblocks++; return res; } +static inline void free_partition(struct mtd_part *p) +{ + kfree(p->mtd.name); + kfree(p); +} + /* * This function unregisters and destroy all slave MTD objects which are * attached to the given master MTD object. @@ -217,49 +354,78 @@ static int part_block_markbad(struct mtd_info *mtd, loff_t ofs) int del_mtd_partitions(struct mtd_info *master) { struct mtd_part *slave, *next; + int ret, err = 0; + mutex_lock(&mtd_partitions_mutex); list_for_each_entry_safe(slave, next, &mtd_partitions, list) if (slave->master == master) { + ret = del_mtd_device(&slave->mtd); + if (ret < 0) { + err = ret; + continue; + } list_del(&slave->list); - if (slave->registered) - del_mtd_device(&slave->mtd); - kfree(slave); + free_partition(slave); } + mutex_unlock(&mtd_partitions_mutex); - return 0; + return err; } -static struct mtd_part *add_one_partition(struct mtd_info *master, - const struct mtd_partition *part, int partno, - uint64_t cur_offset) +static struct mtd_part *allocate_partition(struct mtd_info *master, + const struct mtd_partition *part, int partno, + uint64_t cur_offset) { struct mtd_part *slave; + char *name; /* allocate the partition structure */ slave = kzalloc(sizeof(*slave), GFP_KERNEL); - if (!slave) { + name = kstrdup(part->name, GFP_KERNEL); + if (!name || !slave) { printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n", - master->name); - del_mtd_partitions(master); - return NULL; + master->name); + kfree(name); + kfree(slave); + return ERR_PTR(-ENOMEM); } - list_add(&slave->list, &mtd_partitions); /* set up the MTD object for this partition */ slave->mtd.type = master->type; slave->mtd.flags = master->flags & ~part->mask_flags; slave->mtd.size = part->size; slave->mtd.writesize = master->writesize; + slave->mtd.writebufsize = master->writebufsize; slave->mtd.oobsize = master->oobsize; slave->mtd.oobavail = master->oobavail; slave->mtd.subpage_sft = master->subpage_sft; - slave->mtd.name = part->name; + slave->mtd.name = name; slave->mtd.owner = master->owner; +#ifndef __UBOOT__ + slave->mtd.backing_dev_info = master->backing_dev_info; + + /* NOTE: we don't arrange MTDs as a tree; it'd be error-prone + * to have the same data be in two different partitions. + */ + slave->mtd.dev.parent = master->dev.parent; +#endif slave->mtd._read = part_read; slave->mtd._write = part_write; + if (master->_panic_write) + slave->mtd._panic_write = part_panic_write; + +#ifndef __UBOOT__ + if (master->_point && master->_unpoint) { + slave->mtd._point = part_point; + slave->mtd._unpoint = part_unpoint; + } +#endif + + if (master->_get_unmapped_area) + slave->mtd._get_unmapped_area = part_get_unmapped_area; if (master->_read_oob) slave->mtd._read_oob = part_read_oob; if (master->_write_oob) @@ -278,10 +444,21 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, slave->mtd._get_fact_prot_info = part_get_fact_prot_info; if (master->_sync) slave->mtd._sync = part_sync; +#ifndef __UBOOT__ + if (!partno && !master->dev.class && master->_suspend && + master->_resume) { + slave->mtd._suspend = part_suspend; + slave->mtd._resume = part_resume; + } + if (master->_writev) + slave->mtd._writev = part_writev; +#endif if (master->_lock) slave->mtd._lock = part_lock; if (master->_unlock) slave->mtd._unlock = part_unlock; + if (master->_is_locked) + slave->mtd._is_locked = part_is_locked; if (master->_block_isbad) slave->mtd._block_isbad = part_block_isbad; if (master->_block_markbad) @@ -289,7 +466,6 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, slave->mtd._erase = part_erase; slave->master = master; slave->offset = part->offset; - slave->index = partno; if (slave->offset == MTDPART_OFS_APPEND) slave->offset = cur_offset; @@ -298,18 +474,29 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, if (mtd_mod_by_eb(cur_offset, master) != 0) { /* Round up to next erasesize */ slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize; - debug("Moving partition %d: 0x%012llx -> 0x%012llx\n", - partno, (unsigned long long)cur_offset, - (unsigned long long)slave->offset); + debug("Moving partition %d: " + "0x%012llx -> 0x%012llx\n", partno, + (unsigned long long)cur_offset, (unsigned long long)slave->offset); + } + } + if (slave->offset == MTDPART_OFS_RETAIN) { + slave->offset = cur_offset; + if (master->size - slave->offset >= slave->mtd.size) { + slave->mtd.size = master->size - slave->offset + - slave->mtd.size; + } else { + debug("mtd partition \"%s\" doesn't have enough space: %#llx < %#llx, disabled\n", + part->name, master->size - slave->offset, + slave->mtd.size); + /* register to preserve ordering */ + goto out_register; } } if (slave->mtd.size == MTDPART_SIZ_FULL) slave->mtd.size = master->size - slave->offset; - debug("0x%012llx-0x%012llx : \"%s\"\n", - (unsigned long long)slave->offset, - (unsigned long long)(slave->offset + slave->mtd.size), - slave->mtd.name); + debug("0x%012llx-0x%012llx : \"%s\"\n", (unsigned long long)slave->offset, + (unsigned long long)(slave->offset + slave->mtd.size), slave->mtd.name); /* let's do some sanity checks */ if (slave->offset >= master->size) { @@ -336,7 +523,8 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, for (i = 0; i < max && regions[i].offset <= slave->offset; i++) ; /* The loop searched for the region _behind_ the first one */ - i--; + if (i > 0) + i--; /* Pick biggest erasesize */ for (; i < max && regions[i].offset < end; i++) { @@ -367,6 +555,10 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, } slave->mtd.ecclayout = master->ecclayout; + slave->mtd.ecc_step_size = master->ecc_step_size; + slave->mtd.ecc_strength = master->ecc_strength; + slave->mtd.bitflip_threshold = master->bitflip_threshold; + if (master->_block_isbad) { uint64_t offs = 0; @@ -378,18 +570,91 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, } out_register: - if (part->mtdp) { - /* store the object pointer (caller may or may not register it*/ - *part->mtdp = &slave->mtd; - slave->registered = 0; - } else { - /* register our partition */ - add_mtd_device(&slave->mtd); - slave->registered = 1; - } return slave; } +#ifndef __UBOOT__ +int mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length) +{ + struct mtd_partition part; + struct mtd_part *p, *new; + uint64_t start, end; + int ret = 0; + + /* the direct offset is expected */ + if (offset == MTDPART_OFS_APPEND || + offset == MTDPART_OFS_NXTBLK) + return -EINVAL; + + if (length == MTDPART_SIZ_FULL) + length = master->size - offset; + + if (length <= 0) + return -EINVAL; + + part.name = name; + part.size = length; + part.offset = offset; + part.mask_flags = 0; + part.ecclayout = NULL; + + new = allocate_partition(master, &part, -1, offset); + if (IS_ERR(new)) + return PTR_ERR(new); + + start = offset; + end = offset + length; + + mutex_lock(&mtd_partitions_mutex); + list_for_each_entry(p, &mtd_partitions, list) + if (p->master == master) { + if ((start >= p->offset) && + (start < (p->offset + p->mtd.size))) + goto err_inv; + + if ((end >= p->offset) && + (end < (p->offset + p->mtd.size))) + goto err_inv; + } + + list_add(&new->list, &mtd_partitions); + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&new->mtd); + + return ret; +err_inv: + mutex_unlock(&mtd_partitions_mutex); + free_partition(new); + return -EINVAL; +} +EXPORT_SYMBOL_GPL(mtd_add_partition); + +int mtd_del_partition(struct mtd_info *master, int partno) +{ + struct mtd_part *slave, *next; + int ret = -EINVAL; + + mutex_lock(&mtd_partitions_mutex); + list_for_each_entry_safe(slave, next, &mtd_partitions, list) + if ((slave->master == master) && + (slave->mtd.index == partno)) { + ret = del_mtd_device(&slave->mtd); + if (ret < 0) + break; + + list_del(&slave->list); + free_partition(slave); + break; + } + mutex_unlock(&mtd_partitions_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(mtd_del_partition); +#endif + /* * This function, given a master MTD object and a partition table, creates * and registers slave MTD objects which are bound to the master according to @@ -407,6 +672,7 @@ int add_mtd_partitions(struct mtd_info *master, uint64_t cur_offset = 0; int i; +#ifdef __UBOOT__ /* * Need to init the list here, since LIST_INIT() does not * work on platforms where relocation has problems (like MIPS @@ -414,15 +680,147 @@ int add_mtd_partitions(struct mtd_info *master, */ if (mtd_partitions.next == NULL) INIT_LIST_HEAD(&mtd_partitions); +#endif debug("Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); for (i = 0; i < nbparts; i++) { - slave = add_one_partition(master, parts + i, i, cur_offset); - if (!slave) - return -ENOMEM; + slave = allocate_partition(master, parts + i, i, cur_offset); + if (IS_ERR(slave)) + return PTR_ERR(slave); + + mutex_lock(&mtd_partitions_mutex); + list_add(&slave->list, &mtd_partitions); + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&slave->mtd); + cur_offset = slave->offset + slave->mtd.size; } return 0; } + +#ifndef __UBOOT__ +static DEFINE_SPINLOCK(part_parser_lock); +static LIST_HEAD(part_parsers); + +static struct mtd_part_parser *get_partition_parser(const char *name) +{ + struct mtd_part_parser *p, *ret = NULL; + + spin_lock(&part_parser_lock); + + list_for_each_entry(p, &part_parsers, list) + if (!strcmp(p->name, name) && try_module_get(p->owner)) { + ret = p; + break; + } + + spin_unlock(&part_parser_lock); + + return ret; +} + +#define put_partition_parser(p) do { module_put((p)->owner); } while (0) + +void register_mtd_parser(struct mtd_part_parser *p) +{ + spin_lock(&part_parser_lock); + list_add(&p->list, &part_parsers); + spin_unlock(&part_parser_lock); +} +EXPORT_SYMBOL_GPL(register_mtd_parser); + +void deregister_mtd_parser(struct mtd_part_parser *p) +{ + spin_lock(&part_parser_lock); + list_del(&p->list); + spin_unlock(&part_parser_lock); +} +EXPORT_SYMBOL_GPL(deregister_mtd_parser); + +/* + * Do not forget to update 'parse_mtd_partitions()' kerneldoc comment if you + * are changing this array! + */ +static const char * const default_mtd_part_types[] = { + "cmdlinepart", + "ofpart", + NULL +}; + +/** + * parse_mtd_partitions - parse MTD partitions + * @master: the master partition (describes whole MTD device) + * @types: names of partition parsers to try or %NULL + * @pparts: array of partitions found is returned here + * @data: MTD partition parser-specific data + * + * This function tries to find partition on MTD device @master. It uses MTD + * partition parsers, specified in @types. However, if @types is %NULL, then + * the default list of parsers is used. The default list contains only the + * "cmdlinepart" and "ofpart" parsers ATM. + * Note: If there are more then one parser in @types, the kernel only takes the + * partitions parsed out by the first parser. + * + * This function may return: + * o a negative error code in case of failure + * o zero if no partitions were found + * o a positive number of found partitions, in which case on exit @pparts will + * point to an array containing this number of &struct mtd_info objects. + */ +int parse_mtd_partitions(struct mtd_info *master, const char *const *types, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct mtd_part_parser *parser; + int ret = 0; + + if (!types) + types = default_mtd_part_types; + + for ( ; ret <= 0 && *types; types++) { + parser = get_partition_parser(*types); + if (!parser && !request_module("%s", *types)) + parser = get_partition_parser(*types); + if (!parser) + continue; + ret = (*parser->parse_fn)(master, pparts, data); + put_partition_parser(parser); + if (ret > 0) { + printk(KERN_NOTICE "%d %s partitions found on MTD device %s\n", + ret, parser->name, master->name); + break; + } + } + return ret; +} +#endif + +int mtd_is_partition(const struct mtd_info *mtd) +{ + struct mtd_part *part; + int ispart = 0; + + mutex_lock(&mtd_partitions_mutex); + list_for_each_entry(part, &mtd_partitions, list) + if (&part->mtd == mtd) { + ispart = 1; + break; + } + mutex_unlock(&mtd_partitions_mutex); + + return ispart; +} +EXPORT_SYMBOL_GPL(mtd_is_partition); + +/* Returns the size of the entire flash chip */ +uint64_t mtd_get_device_size(const struct mtd_info *mtd) +{ + if (!mtd_is_partition(mtd)) + return mtd->size; + + return PART(mtd)->master->size; +} +EXPORT_SYMBOL_GPL(mtd_get_device_size); diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig new file mode 100644 index 0000000000..3a5ffc1c22 --- /dev/null +++ b/drivers/mtd/nand/Kconfig @@ -0,0 +1,77 @@ +menuconfig NAND + bool "NAND Device Support" + +if NAND + +config SYS_NAND_USE_FLASH_BBT + bool "Use a flash based bad block table" + +config SYS_NAND_SELF_INIT + bool + help + This option, if enabled, provides more flexible and linux-like + NAND initialization process. + +if !SPL_BUILD + +config NAND_DENALI + bool "Support Denali NAND controller" + select SYS_NAND_SELF_INIT + help + Enable support for the Denali NAND controller. + +config SYS_NAND_DENALI_64BIT + bool "Use 64-bit variant of Denali NAND controller" + depends on NAND_DENALI + help + The Denali NAND controller IP has some variations in terms of + the bus interface. The DMA setup sequence is completely differenct + between 32bit / 64bit AXI bus variants. + + If your Denali NAND controller is the 64-bit variant, say Y. + Otherwise (32 bit), say N. + +config NAND_DENALI_SPARE_AREA_SKIP_BYTES + int "Number of bytes skipped in OOB area" + depends on NAND_DENALI + range 0 63 + help + This option specifies the number of bytes to skip from the beginning + of OOB area before last ECC sector data starts. This is potentially + used to preserve the bad block marker in the OOB area. + +endif + +if SPL_BUILD + +config SPL_NAND_DENALI + bool "Support Denali NAND controller for SPL" + help + This is a small implementation of the Denali NAND controller + for use on SPL. + +endif + +config NAND_ATMEL + bool "AT91 NAND flash controller" + select SYS_NAND_SELF_INIT + +config NAND_MXC + bool "Support Freescale i.MX NAND controller" + select SYS_NAND_SELF_INIT + help + Enable support for the Freescale NAND controller found on + i.MX processors. + +config NAND_MXS + bool "Support Freescale GPMI NAND controller" + help + Enable support for the Freescale GPMI NAND controller found + on i.MX28 and i.MX6 processors. + +config NAND_MXS_NO_BBM_SWAP + bool "disable bad block mark swapping" + depends on NAND_MXS && SOC_MX6 + select SYS_NAND_USE_FLASH_BBT + +endif diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index e27e0b7050..1f02bfc35f 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -5,88 +5,72 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libnand.o - -ifdef CONFIG_CMD_NAND - ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_NAND_DRIVERS NORMAL_DRIVERS=y endif -COBJS-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o -COBJS-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o -COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o -COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o -COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o +obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o +obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o +obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o +obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o +obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o +obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o +obj-$(CONFIG_SPL_NAND_INIT) += nand.o +ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) +obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o +endif else # not spl NORMAL_DRIVERS=y -COBJS-y += nand.o -COBJS-y += nand_bbt.o -COBJS-y += nand_ids.o -COBJS-y += nand_util.o -COBJS-y += nand_ecc.o -COBJS-y += nand_base.o +obj-y += nand.o +obj-y += nand_bbt.o +obj-y += nand_ids.o +obj-y += nand_util.o +obj-y += nand_ecc.o +obj-y += nand_base.o endif # not spl ifdef NORMAL_DRIVERS -COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o - -COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o -COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o -COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o -COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o -COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o -COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o -COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o -COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o -COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o -COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o -COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o -COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o -COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o -COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o -COBJS-$(CONFIG_NAND_NDFC) += ndfc.o -COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o -COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o -COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o -COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o -COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o -COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o -COBJS-$(CONFIG_NAND_DOCG4) += docg4.o +obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o + +obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o +obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o +obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o +obj-$(CONFIG_NAND_DENALI) += denali.o +obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o +obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o +obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o +obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o +obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o +obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o +obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o +obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o +obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o +obj-$(CONFIG_NAND_MXC) += mxc_nand.o +obj-$(CONFIG_NAND_MXS) += mxs_nand.o +obj-$(CONFIG_NAND_NDFC) += ndfc.o +obj-$(CONFIG_NAND_NOMADIK) += nomadik.o +obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o +obj-$(CONFIG_NAND_SPEAR) += spr_nand.o +obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o +obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o +obj-$(CONFIG_NAND_PLAT) += nand_plat.o +obj-$(CONFIG_NAND_DOCG4) += docg4.o else # minimal SPL drivers -COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o -COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o -COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o +obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o +obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o +obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o +obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o endif # drivers -endif # nand - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index c84851bab5..bf8b2ee16a 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -16,7 +16,7 @@ #include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; -static nand_info_t mtd; +nand_info_t nand_info[1]; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ @@ -30,12 +30,12 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(&nand_info[0])) ; /* Emulate NAND_CMD_READOOB */ @@ -45,50 +45,54 @@ static int nand_command(int block, int page, uint32_t offs, } /* Begin command latch cycle */ - hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); if (cmd == NAND_CMD_RESET) { - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - while (!this->dev_ready(&mtd)) + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + while (!this->dev_ready(&nand_info[0])) ; return 0; } /* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; /* Set ALE and clear CLE to start address cycle */ /* Column address */ - hwctrl(&mtd, offs & 0xff, + hwctrl(&nand_info[0], offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ - hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ + hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ /* Row address */ - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ - hwctrl(&mtd, ((page_addr >> 8) & 0xff), + if (cmd != NAND_CMD_RNDOUT) { + hwctrl(&nand_info[0], (page_addr & 0xff), + NAND_CTRL_ALE); /* A[19:12] */ + hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); /* A[27:20] */ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE - /* One more address cycle for devices > 128MiB */ - hwctrl(&mtd, (page_addr >> 16) & 0x0f, + /* One more address cycle for devices > 128MiB */ + hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); /* A[31:28] */ #endif - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + } + + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); if (cmd == NAND_CMD_READ0) { /* Latch in address */ - hwctrl(&mtd, NAND_CMD_READSTART, + hwctrl(&nand_info[0], NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(&nand_info[0])) ; } else if (cmd == NAND_CMD_RNDOUT) { - hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | + hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); } return 0; @@ -96,7 +100,7 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_is_bad_block(int block) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); @@ -117,7 +121,7 @@ static int nand_is_bad_block(int block) static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -133,15 +137,15 @@ static int nand_read_page(int block, int page, void *dst) nand_command(block, page, 0, NAND_CMD_READ0); for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(&mtd, NAND_ECC_READ); + this->ecc.hwctl(&nand_info[0], NAND_ECC_READ); nand_command(block, page, data_pos, NAND_CMD_RNDOUT); - this->read_buf(&mtd, p, eccsize); + this->read_buf(&nand_info[0], p, eccsize); nand_command(block, page, oob_pos, NAND_CMD_RNDOUT); - this->read_buf(&mtd, oob, eccbytes); - this->ecc.calculate(&mtd, p, &ecc_calc[i]); + this->read_buf(&nand_info[0], oob, eccbytes); + this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]); data_pos += eccsize; oob_pos += eccbytes; @@ -160,7 +164,7 @@ static int nand_read_page(int block, int page, void *dst) * from correct_data(). We just hope that all possible errors * are corrected by this routine. */ - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]); } return 0; @@ -206,13 +210,13 @@ void nand_init(void) /* * Init board specific nand support */ - mtd.priv = &nand_chip; + nand_info[0].priv = &nand_chip; nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, 0); + nand_chip.select_chip(&nand_info[0], 0); /* NAND chip may require reset after power-on */ nand_command(0, 0, 0, NAND_CMD_RESET); @@ -222,5 +226,5 @@ void nand_init(void) void nand_deselect(void) { if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, -1); + nand_chip.select_chip(&nand_info[0], -1); } diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index f844990e38..620b6e8ff9 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -12,12 +12,13 @@ */ #include -#include +#include #include -#include +#include #include #include +#include #ifdef CONFIG_ATMEL_NAND_HWECC @@ -31,6 +32,10 @@ #ifdef CONFIG_ATMEL_NAND_HW_PMECC +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SYS_NAND_ONFI_DETECTION +#endif + struct atmel_nand_host { struct pmecc_regs __iomem *pmecc; struct pmecc_errloc_regs __iomem *pmerrloc; @@ -50,13 +55,13 @@ struct atmel_nand_host { void __iomem *pmecc_index_of; /* data for pmecc computation */ - int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)]; - int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1]; - int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1]; - int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */ - int pmecc_mu[CONFIG_PMECC_CAP + 1]; - int pmecc_dmu[CONFIG_PMECC_CAP + 1]; - int pmecc_delta[CONFIG_PMECC_CAP + 1]; + int16_t *pmecc_smu; + int16_t *pmecc_partial_syn; + int16_t *pmecc_si; + int16_t *pmecc_lmu; /* polynomal order */ + int *pmecc_mu; + int *pmecc_dmu; + int *pmecc_delta; }; static struct atmel_nand_host pmecc_host; @@ -109,6 +114,48 @@ static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host) table_size * sizeof(int16_t); } +static void pmecc_data_free(struct atmel_nand_host *host) +{ + free(host->pmecc_partial_syn); + free(host->pmecc_si); + free(host->pmecc_lmu); + free(host->pmecc_smu); + free(host->pmecc_mu); + free(host->pmecc_dmu); + free(host->pmecc_delta); +} + +static int pmecc_data_alloc(struct atmel_nand_host *host) +{ + const int cap = host->pmecc_corr_cap; + int size; + + size = (2 * cap + 1) * sizeof(int16_t); + host->pmecc_partial_syn = malloc(size); + host->pmecc_si = malloc(size); + host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t)); + host->pmecc_smu = malloc((cap + 2) * size); + + size = (cap + 1) * sizeof(int); + host->pmecc_mu = malloc(size); + host->pmecc_dmu = malloc(size); + host->pmecc_delta = malloc(size); + + if (host->pmecc_partial_syn && + host->pmecc_si && + host->pmecc_lmu && + host->pmecc_smu && + host->pmecc_mu && + host->pmecc_dmu && + host->pmecc_delta) + return 0; + + /* error happened */ + pmecc_data_free(host); + return -ENOMEM; + +} + static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector) { struct nand_chip *nand_chip = mtd->priv; @@ -118,7 +165,7 @@ static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector) /* Fill odd syndromes */ for (i = 0; i < host->pmecc_corr_cap; i++) { - value = readl(&host->pmecc->rem_port[sector].rem[i / 2]); + value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]); if (i & 1) value >>= 16; value &= 0xffff; @@ -346,10 +393,11 @@ static int pmecc_err_location(struct mtd_info *mtd) int16_t *smu = host->pmecc_smu; int timeout = PMECC_MAX_TIMEOUT_US; - writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis); + pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE); for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) { - writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]); + pmecc_writel(host->pmerrloc, sigma[i], + smu[(cap + 1) * num + i]); err_nbr++; } @@ -357,23 +405,23 @@ static int pmecc_err_location(struct mtd_info *mtd) if (sector_size == 1024) val |= PMERRLOC_ELCFG_SECTOR_1024; - writel(val, &host->pmerrloc->elcfg); - writel(sector_size * 8 + host->pmecc_degree * cap, - &host->pmerrloc->elen); + pmecc_writel(host->pmerrloc, elcfg, val); + pmecc_writel(host->pmerrloc, elen, + sector_size * 8 + host->pmecc_degree * cap); while (--timeout) { - if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE) + if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE) break; WATCHDOG_RESET(); udelay(1); } if (!timeout) { - printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n"); + dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n"); return -1; } - roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK) + roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK) >> 8; /* Number of roots == degree of smu hence <= cap */ if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1) @@ -397,7 +445,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, sector_size = host->pmecc_sector_size; while (err_nbr) { - tmp = readl(&host->pmerrloc->el[i]) - 1; + tmp = pmecc_readl(host->pmerrloc, el[i]) - 1; byte_pos = tmp / 8; bit_pos = tmp % 8; @@ -409,7 +457,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, *(buf + byte_pos) ^= (1 << bit_pos); pos = sector_num * host->pmecc_sector_size + byte_pos; - printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", + dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", pos, bit_pos, err_byte, *(buf + byte_pos)); } else { /* Bit flip in OOB area */ @@ -419,7 +467,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, ecc[tmp] ^= (1 << bit_pos); pos = tmp + nand_chip->ecc.layout->eccpos[0]; - printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", + dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", pos, bit_pos, err_byte, ecc[tmp]); } @@ -457,7 +505,7 @@ normal_check: err_nbr = pmecc_err_location(mtd); if (err_nbr == -1) { - printk(KERN_ERR "PMECC: Too many errors\n"); + dev_err(host->dev, "PMECC: Too many errors\n"); mtd->ecc_stats.failed++; return -EIO; } else { @@ -501,7 +549,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, } if (!timeout) { - printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n"); + dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n"); return -1; } @@ -541,7 +589,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, } if (!timeout) { - printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n"); + dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n"); goto out; } @@ -551,7 +599,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, pos = i * host->pmecc_bytes_per_sector + j; chip->oob_poi[eccpos[pos]] = - readb(&host->pmecc->ecc_port[i].ecc[j]); + pmecc_readb(host->pmecc, ecc_port[i].ecc[j]); } } chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); @@ -622,6 +670,155 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd) pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE); } +#ifdef CONFIG_SYS_NAND_ONFI_DETECTION +/* + * get_onfi_ecc_param - Get ECC requirement from ONFI parameters + * @ecc_bits: store the ONFI ECC correct bits capbility + * @sector_size: in how many bytes that ONFI require to correct @ecc_bits + * + * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits, + * @sector_size are initialize to 0. + * Return 0 if success to get the ECC requirement. + */ +static int get_onfi_ecc_param(struct nand_chip *chip, + int *ecc_bits, int *sector_size) +{ + *ecc_bits = *sector_size = 0; + + if (chip->onfi_params.ecc_bits == 0xff) + /* TODO: the sector_size and ecc_bits need to be find in + * extended ecc parameter, currently we don't support it. + */ + return -1; + + *ecc_bits = chip->onfi_params.ecc_bits; + + /* The default sector size (ecc codeword size) is 512 */ + *sector_size = 512; + + return 0; +} + +/* + * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If + * pmecc_corr_cap or pmecc_sector_size is 0, then set it as + * ONFI ECC parameters. + * @host: point to an atmel_nand_host structure. + * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits. + * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size. + * @chip: point to an nand_chip structure. + * @cap: store the ONFI ECC correct bits capbility + * @sector_size: in how many bytes that ONFI require to correct @ecc_bits + * + * Return 0 if success. otherwise return the error code. + */ +static int pmecc_choose_ecc(struct atmel_nand_host *host, + struct nand_chip *chip, + int *cap, int *sector_size) +{ + /* Get ECC requirement from ONFI parameters */ + *cap = *sector_size = 0; + if (chip->onfi_version) { + if (!get_onfi_ecc_param(chip, cap, sector_size)) { + MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n", + *cap, *sector_size); + } else { + dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n"); + } + } else { + dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes"); + } + if (*cap == 0 && *sector_size == 0) { + /* Non-ONFI compliant or use extended ONFI parameters */ + *cap = 2; + *sector_size = 512; + } + + /* If head file doesn't specify then use the one in ONFI parameters */ + if (host->pmecc_corr_cap == 0) { + /* use the most fitable ecc bits (the near bigger one ) */ + if (*cap <= 2) + host->pmecc_corr_cap = 2; + else if (*cap <= 4) + host->pmecc_corr_cap = 4; + else if (*cap <= 8) + host->pmecc_corr_cap = 8; + else if (*cap <= 12) + host->pmecc_corr_cap = 12; + else if (*cap <= 24) + host->pmecc_corr_cap = 24; + else + return -EINVAL; + } + if (host->pmecc_sector_size == 0) { + /* use the most fitable sector size (the near smaller one ) */ + if (*sector_size >= 1024) + host->pmecc_sector_size = 1024; + else if (*sector_size >= 512) + host->pmecc_sector_size = 512; + else + return -EINVAL; + } + return 0; +} +#endif + +#if defined(NO_GALOIS_TABLE_IN_ROM) +static uint16_t *pmecc_galois_table; +static inline int deg(unsigned int poly) +{ + /* polynomial degree is the most-significant bit index */ + return fls(poly) - 1; +} + +static int build_gf_tables(int mm, unsigned int poly, + int16_t *index_of, int16_t *alpha_to) +{ + unsigned int i, x = 1; + const unsigned int k = 1 << deg(poly); + unsigned int nn = (1 << mm) - 1; + + /* primitive polynomial must be of degree m */ + if (k != (1u << mm)) + return -EINVAL; + + for (i = 0; i < nn; i++) { + alpha_to[i] = x; + index_of[x] = i; + if (i && (x == 1)) + /* polynomial is not primitive (a^i=1 with 0ecc.correct = NULL; nand->ecc.hwctl = NULL; - cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP; - sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE; - host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET; +#ifdef CONFIG_SYS_NAND_ONFI_DETECTION + host->pmecc_corr_cap = host->pmecc_sector_size = 0; + +#ifdef CONFIG_PMECC_CAP + host->pmecc_corr_cap = CONFIG_PMECC_CAP; +#endif +#ifdef CONFIG_PMECC_SECTOR_SIZE + host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE; +#endif + /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or + * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size + * from ONFI. + */ + if (pmecc_choose_ecc(host, nand, &cap, §or_size)) { + dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!", + cap, sector_size); + return -EINVAL; + } + + if (cap > host->pmecc_corr_cap) + dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n", + host->pmecc_corr_cap, cap); + if (sector_size < host->pmecc_sector_size) + dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n", + host->pmecc_sector_size, sector_size); +#else /* CONFIG_SYS_NAND_ONFI_DETECTION */ + host->pmecc_corr_cap = CONFIG_PMECC_CAP; + host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE; +#endif + + cap = host->pmecc_corr_cap; + sector_size = host->pmecc_sector_size; + + /* TODO: need check whether cap & sector_size is validate */ +#if defined(NO_GALOIS_TABLE_IN_ROM) + /* + * As pmecc_rom_base is the begin of the gallois field table, So the + * index offset just set as 0. + */ + host->pmecc_index_table_offset = 0; +#else + if (host->pmecc_sector_size == 512) + host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512; + else + host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024; +#endif MTDDEBUG(MTD_DEBUG_LEVEL1, "Initialize PMECC params, cap: %d, sector: %d\n", @@ -646,7 +886,17 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC; host->pmerrloc = (struct pmecc_errloc_regs __iomem *) ATMEL_BASE_PMERRLOC; +#if defined(NO_GALOIS_TABLE_IN_ROM) + pmecc_galois_table = create_lookup_table(host->pmecc_sector_size); + if (!pmecc_galois_table) { + dev_err(host->dev, "out of memory\n"); + return -ENOMEM; + } + + host->pmecc_rom_base = (void __iomem *)pmecc_galois_table; +#else host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM; +#endif /* ECC is calculated for the whole page (1 step) */ nand->ecc.size = mtd->writesize; @@ -655,7 +905,9 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, switch (mtd->writesize) { case 2048: case 4096: - host->pmecc_degree = PMECC_GF_DIMENSION_13; + case 8192: + host->pmecc_degree = (sector_size == 512) ? + PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14; host->pmecc_cw_len = (1 << host->pmecc_degree) - 1; host->pmecc_sector_number = mtd->writesize / sector_size; host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes( @@ -667,8 +919,15 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, nand->ecc.steps = 1; nand->ecc.bytes = host->pmecc_bytes_per_sector * host->pmecc_sector_number; + + if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) { + dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n", + MTD_MAX_ECCPOS_ENTRIES_LARGE); + return -EINVAL; + } + if (nand->ecc.bytes > mtd->oobsize - 2) { - printk(KERN_ERR "No room for ECC bytes\n"); + dev_err(host->dev, "No room for ECC bytes\n"); return -EINVAL; } pmecc_config_ecc_layout(&atmel_pmecc_oobinfo, @@ -679,7 +938,7 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, case 512: case 1024: /* TODO */ - printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n"); + dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n"); default: /* page size not handled by HW ECC */ /* switching back to soft ECC */ @@ -691,6 +950,13 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, return 0; } + /* Allocate data for PMECC computation */ + if (pmecc_data_alloc(host)) { + dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n"); + return -ENOMEM; + } + + nand->options |= NAND_NO_SUBPAGE_WRITE; nand->ecc.read_page = atmel_nand_pmecc_read_page; nand->ecc.write_page = atmel_nand_pmecc_write_page; nand->ecc.strength = cap; @@ -856,7 +1122,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, /* it doesn't seems to be a freshly * erased block. * We can't correct so many errors */ - printk(KERN_WARNING "atmel_nand : multiple errors detected." + dev_warn(host->dev, "atmel_nand : multiple errors detected." " Unable to correct.\n"); return -EIO; } @@ -866,12 +1132,12 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, /* there's nothing much to do here. * the bit error is on the ECC itself. */ - printk(KERN_WARNING "atmel_nand : one bit error on ECC code." + dev_warn(host->dev, "atmel_nand : one bit error on ECC code." " Nothing to correct\n"); return 0; } - printk(KERN_WARNING "atmel_nand : one bit error on data." + dev_warn(host->dev, "atmel_nand : one bit error on data." " (word offset in the page :" " 0x%x bit offset : 0x%x)\n", ecc_word, ecc_bit); @@ -883,7 +1149,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, /* 8 bits words */ dat[ecc_word] ^= (1 << ecc_bit); } - printk(KERN_WARNING "atmel_nand : error corrected\n"); + dev_warn(host->dev, "atmel_nand : error corrected\n"); return 1; } @@ -967,8 +1233,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE; #ifdef CONFIG_SYS_NAND_ENABLE_PIN - at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN, - !(ctrl & NAND_NCE)); + gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE)); #endif this->IO_ADDR_W = (void *) IO_ADDR_W; } @@ -980,10 +1245,246 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, #ifdef CONFIG_SYS_NAND_READY_PIN static int at91_nand_ready(struct mtd_info *mtd) { - return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN); + return gpio_get_value(CONFIG_SYS_NAND_READY_PIN); } #endif +#ifdef CONFIG_SPL_BUILD +/* The following code is for SPL */ +static nand_info_t mtd; +static struct nand_chip nand_chip; + +static int nand_command(int block, int page, uint32_t offs, u8 cmd) +{ + struct nand_chip *this = mtd.priv; + int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + void (*hwctrl)(struct mtd_info *mtd, int cmd, + unsigned int ctrl) = this->cmd_ctrl; + + while (!this->dev_ready(&mtd)) + ; + + if (cmd == NAND_CMD_READOOB) { + offs += CONFIG_SYS_NAND_PAGE_SIZE; + cmd = NAND_CMD_READ0; + } + + hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) + offs >>= 1; + + hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); + hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); + hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); + hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE + hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); +#endif + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + while (!this->dev_ready(&mtd)) + ; + + return 0; +} + +static int nand_is_bad_block(int block) +{ + struct nand_chip *this = mtd.priv; + + nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); + + if (this->options & NAND_BUSWIDTH_16) { + if (readw(this->IO_ADDR_R) != 0xffff) + return 1; + } else { + if (readb(this->IO_ADDR_R) != 0xff) + return 1; + } + + return 0; +} + +#ifdef CONFIG_SPL_NAND_ECC +static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + +static int nand_read_page(int block, int page, void *dst) +{ + struct nand_chip *this = mtd.priv; + u_char ecc_calc[ECCTOTAL]; + u_char ecc_code[ECCTOTAL]; + u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; + int eccsize = CONFIG_SYS_NAND_ECCSIZE; + int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsteps = ECCSTEPS; + int i; + uint8_t *p = dst; + nand_command(block, page, 0, NAND_CMD_READ0); + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + if (this->ecc.mode != NAND_ECC_SOFT) + this->ecc.hwctl(&mtd, NAND_ECC_READ); + this->read_buf(&mtd, p, eccsize); + this->ecc.calculate(&mtd, p, &ecc_calc[i]); + } + this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); + + for (i = 0; i < ECCTOTAL; i++) + ecc_code[i] = oob_data[nand_ecc_pos[i]]; + + eccsteps = ECCSTEPS; + p = dst; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + + return 0; +} + +int spl_nand_erase_one(int block, int page) +{ + struct nand_chip *this = mtd.priv; + void (*hwctrl)(struct mtd_info *mtd, int cmd, + unsigned int ctrl) = this->cmd_ctrl; + int page_addr; + + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, 0); + + page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + /* Row address */ + hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE); + hwctrl(&mtd, ((page_addr >> 8) & 0xff), + NAND_CTRL_ALE | NAND_CTRL_CHANGE); +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE + /* One more address cycle for devices > 128MiB */ + hwctrl(&mtd, (page_addr >> 16) & 0x0f, + NAND_CTRL_ALE | NAND_CTRL_CHANGE); +#endif + + hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + udelay(2000); + + while (!this->dev_ready(&mtd)) + ; + + nand_deselect(); + + return 0; +} +#else +static int nand_read_page(int block, int page, void *dst) +{ + struct nand_chip *this = mtd.priv; + + nand_command(block, page, 0, NAND_CMD_READ0); + atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page); + + return 0; +} +#endif /* CONFIG_SPL_NAND_ECC */ + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + unsigned int block, lastblock; + unsigned int page; + + block = offs / CONFIG_SYS_NAND_BLOCK_SIZE; + lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; + page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE; + + while (block <= lastblock) { + if (!nand_is_bad_block(block)) { + while (page < CONFIG_SYS_NAND_PAGE_COUNT) { + nand_read_page(block, page, dst); + dst += CONFIG_SYS_NAND_PAGE_SIZE; + page++; + } + + page = 0; + } else { + lastblock++; + } + + block++; + } + + return 0; +} + +int at91_nand_wait_ready(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + udelay(this->chip_delay); + + return 1; +} + +int board_nand_init(struct nand_chip *nand) +{ + int ret = 0; + + nand->ecc.mode = NAND_ECC_SOFT; +#ifdef CONFIG_SYS_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; + nand->read_buf = nand_read_buf16; +#else + nand->read_buf = nand_read_buf; +#endif + nand->cmd_ctrl = at91_nand_hwcontrol; +#ifdef CONFIG_SYS_NAND_READY_PIN + nand->dev_ready = at91_nand_ready; +#else + nand->dev_ready = at91_nand_wait_ready; +#endif + nand->chip_delay = 20; + +#ifdef CONFIG_ATMEL_NAND_HWECC +#ifdef CONFIG_ATMEL_NAND_HW_PMECC + ret = atmel_pmecc_nand_init_params(nand, &mtd); +#endif +#endif + + return ret; +} + +void nand_init(void) +{ + mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE; + mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE; + mtd.priv = &nand_chip; + nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + board_nand_init(&nand_chip); + +#ifdef CONFIG_SPL_NAND_ECC + if (nand_chip.ecc.mode == NAND_ECC_SOFT) { + nand_chip.ecc.calculate = nand_calculate_ecc; + nand_chip.ecc.correct = nand_correct_data; + } +#endif + + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, 0); +} + +void nand_deselect(void) +{ + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, -1); +} + +#else + #ifndef CONFIG_SYS_NAND_BASE_LIST #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #endif @@ -999,7 +1500,11 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; +#ifdef CONFIG_NAND_ECC_BCH + nand->ecc.mode = NAND_ECC_SOFT_BCH; +#else nand->ecc.mode = NAND_ECC_SOFT; +#endif #ifdef CONFIG_SYS_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif @@ -1007,7 +1512,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) #ifdef CONFIG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #endif - nand->chip_delay = 20; + nand->chip_delay = 75; ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); if (ret) @@ -1035,6 +1540,7 @@ void board_nand_init(void) int i; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) if (atmel_nand_chip_init(i, base_addr[i])) - printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip", + dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip", i); } +#endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h index 55d7711c8b..eac860d13c 100644 --- a/drivers/mtd/nand/atmel_nand_ecc.h +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -34,6 +34,9 @@ #define pmecc_readl(addr, reg) \ readl(&addr->reg) +#define pmecc_readb(addr, reg) \ + readb(&addr->reg) + #define pmecc_writel(addr, reg, value) \ writel((value), &addr->reg) @@ -138,6 +141,10 @@ struct pmecc_errloc_regs { #define PMECC_GF_DIMENSION_13 13 #define PMECC_GF_DIMENSION_14 14 +/* Primitive Polynomial used by PMECC */ +#define PMECC_GF_13_PRIMITIVE_POLY 0x201b +#define PMECC_GF_14_PRIMITIVE_POLY 0x4443 + #define PMECC_INDEX_TABLE_SIZE_512 0x2000 #define PMECC_INDEX_TABLE_SIZE_1024 0x4000 diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d8bb5d3519..41689b5165 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -32,8 +32,7 @@ #include #include #include -#include -#include +#include /* Definitions for 4-bit hardware ECC */ #define NAND_TIMEOUT 10240 @@ -266,6 +265,17 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { #if defined(CONFIG_SYS_NAND_PAGE_2K) .eccbytes = 40, +#ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + {2, 4}, {16, 6}, {32, 6}, {48, 6}, + }, +#else .eccpos = { 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, @@ -276,6 +286,7 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { .oobfree = { {.offset = 2, .length = 22, }, }, +#endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */ #elif defined(CONFIG_SYS_NAND_PAGE_4K) .eccbytes = 80, .eccpos = { @@ -294,6 +305,190 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { #endif }; +#if defined CONFIG_KEYSTONE_RBL_NAND +static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = { +#if defined(CONFIG_SYS_NAND_PAGE_2K) + .eccbytes = 40, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + {.offset = 2, .length = 4, }, + {.offset = 16, .length = 6, }, + {.offset = 32, .length = 6, }, + {.offset = 48, .length = 6, }, + }, +#elif defined(CONFIG_SYS_NAND_PAGE_4K) + .eccbytes = 80, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, + 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, + 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, + 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, + }, + .oobfree = { + {.offset = 2, .length = 4, }, + {.offset = 16, .length = 6, }, + {.offset = 32, .length = 6, }, + {.offset = 48, .length = 6, }, + {.offset = 64, .length = 6, }, + {.offset = 80, .length = 6, }, + {.offset = 96, .length = 6, }, + {.offset = 112, .length = 6, }, + }, +#endif +}; + +#ifdef CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11 +#elif defined(CONFIG_SYS_NAND_PAGE_4K) +#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12 +#endif + +/** + * nand_davinci_write_page - write one page + * @mtd: MTD device structure + * @chip: NAND chip descriptor + * @buf: the data to write + * @oob_required: must write chip->oob_poi to OOB + * @page: page number to write + * @cached: cached programming + * @raw: use _raw version of write_page + */ +static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, + uint32_t offset, int data_len, + const uint8_t *buf, int oob_required, + int page, int cached, int raw) +{ + int status; + int ret = 0; + struct nand_ecclayout *saved_ecc_layout; + + /* save current ECC layout and assign Keystone RBL ECC layout */ + if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + saved_ecc_layout = chip->ecc.layout; + chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; + mtd->oobavail = chip->ecc.layout->oobavail; + } + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + + if (unlikely(raw)) + status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); + else + status = chip->ecc.write_page(mtd, chip, buf, oob_required); + + if (status < 0) { + ret = status; + goto err; + } + + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + + /* + * See if operation failed and additional status checks are + * available. + */ + if ((status & NAND_STATUS_FAIL) && (chip->errstat)) + status = chip->errstat(mtd, chip, FL_WRITING, status, page); + + if (status & NAND_STATUS_FAIL) { + ret = -EIO; + goto err; + } + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* Send command to read back the data */ + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + if (chip->verify_buf(mtd, buf, mtd->writesize)) { + ret = -EIO; + goto err; + } + + /* Make sure the next page prog is preceded by a status read */ + chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); +#endif +err: + /* restore ECC layout */ + if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = saved_ecc_layout; + mtd->oobavail = saved_ecc_layout->oobavail; + } + + return ret; +} + +/** + * nand_davinci_read_page_hwecc - hardware ECC based page read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @oob_required: caller requires OOB data read to chip->oob_poi + * @page: page number to read + * + * Not for syndrome calculating ECC controllers which need a special oob layout. + */ +static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint32_t *eccpos; + uint8_t *p = buf; + uint8_t *ecc_code = chip->buffers->ecccode; + uint8_t *ecc_calc = chip->buffers->ecccalc; + struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout; + + /* save current ECC layout and assign Keystone RBL ECC layout */ + if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; + mtd->oobavail = chip->ecc.layout->oobavail; + } + + eccpos = chip->ecc.layout->eccpos; + + /* Read the OOB area first */ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + + /* restore ECC layout */ + if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = saved_ecc_layout; + mtd->oobavail = saved_ecc_layout->oobavail; + } + + return 0; +} +#endif /* CONFIG_KEYSTONE_RBL_NAND */ + static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) { u32 val; @@ -593,10 +788,26 @@ static void nand_flash_init(void) void davinci_nand_init(struct nand_chip *nand) { +#if defined CONFIG_KEYSTONE_RBL_NAND + int i; + struct nand_ecclayout *layout; + + layout = &nand_keystone_rbl_4bit_layout_oobfirst; + layout->oobavail = 0; + for (i = 0; layout->oobfree[i].length && + i < ARRAY_SIZE(layout->oobfree); i++) + layout->oobavail += layout->oobfree[i].length; + + nand->write_page = nand_davinci_write_page; + nand->ecc.read_page = nand_davinci_read_page_hwecc; +#endif nand->chip_delay = 0; #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand->bbt_options |= NAND_BBT_USE_FLASH; #endif +#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE + nand->options |= NAND_NO_SUBPAGE_WRITE; +#endif #ifdef CONFIG_SYS_NAND_HW_ECC nand->ecc.mode = NAND_ECC_HW; nand->ecc.size = 512; diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c new file mode 100644 index 0000000000..9e0429aa19 --- /dev/null +++ b/drivers/mtd/nand/denali.c @@ -0,0 +1,1271 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2013-2014, Altera Corporation + * Copyright (C) 2009-2010, Intel Corporation and its suppliers. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include "denali.h" + +#define NAND_DEFAULT_TIMINGS -1 + +static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; + +/* We define a macro here that combines all interrupts this driver uses into + * a single constant value, for convenience. */ +#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ + INTR_STATUS__ECC_TRANSACTION_DONE | \ + INTR_STATUS__ECC_ERR | \ + INTR_STATUS__PROGRAM_FAIL | \ + INTR_STATUS__LOAD_COMP | \ + INTR_STATUS__PROGRAM_COMP | \ + INTR_STATUS__TIME_OUT | \ + INTR_STATUS__ERASE_FAIL | \ + INTR_STATUS__RST_COMP | \ + INTR_STATUS__ERASE_COMP | \ + INTR_STATUS__ECC_UNCOR_ERR | \ + INTR_STATUS__INT_ACT | \ + INTR_STATUS__LOCKED_BLK) + +/* indicates whether or not the internal value for the flash bank is + * valid or not */ +#define CHIP_SELECT_INVALID -1 + +#define SUPPORT_8BITECC 1 + +/* + * this macro allows us to convert from an MTD structure to our own + * device context (denali) structure. + */ +#define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand) + +/* These constants are defined by the driver to enable common driver + * configuration options. */ +#define SPARE_ACCESS 0x41 +#define MAIN_ACCESS 0x42 +#define MAIN_SPARE_ACCESS 0x43 + +#define DENALI_UNLOCK_START 0x10 +#define DENALI_UNLOCK_END 0x11 +#define DENALI_LOCK 0x21 +#define DENALI_LOCK_TIGHT 0x31 +#define DENALI_BUFFER_LOAD 0x60 +#define DENALI_BUFFER_WRITE 0x62 + +#define DENALI_READ 0 +#define DENALI_WRITE 0x100 + +/* types of device accesses. We can issue commands and get status */ +#define COMMAND_CYCLE 0 +#define ADDR_CYCLE 1 +#define STATUS_CYCLE 2 + +/* this is a helper macro that allows us to + * format the bank into the proper bits for the controller */ +#define BANK(x) ((x) << 24) + +/* Interrupts are cleared by writing a 1 to the appropriate status bit */ +static inline void clear_interrupt(struct denali_nand_info *denali, + uint32_t irq_mask) +{ + uint32_t intr_status_reg; + + intr_status_reg = INTR_STATUS(denali->flash_bank); + + writel(irq_mask, denali->flash_reg + intr_status_reg); +} + +static uint32_t read_interrupt_status(struct denali_nand_info *denali) +{ + uint32_t intr_status_reg; + + intr_status_reg = INTR_STATUS(denali->flash_bank); + + return readl(denali->flash_reg + intr_status_reg); +} + +static void clear_interrupts(struct denali_nand_info *denali) +{ + uint32_t status; + + status = read_interrupt_status(denali); + clear_interrupt(denali, status); + + denali->irq_status = 0; +} + +static void denali_irq_enable(struct denali_nand_info *denali, + uint32_t int_mask) +{ + int i; + + for (i = 0; i < denali->max_banks; ++i) + writel(int_mask, denali->flash_reg + INTR_EN(i)); +} + +static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) +{ + unsigned long timeout = 1000000; + uint32_t intr_status; + + do { + intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL; + if (intr_status & irq_mask) { + denali->irq_status &= ~irq_mask; + /* our interrupt was detected */ + break; + } + udelay(1); + timeout--; + } while (timeout != 0); + + if (timeout == 0) { + /* timeout */ + printf("Denali timeout with interrupt status %08x\n", + read_interrupt_status(denali)); + intr_status = 0; + } + return intr_status; +} + +/* + * Certain operations for the denali NAND controller use an indexed mode to + * read/write data. The operation is performed by writing the address value + * of the command to the device memory followed by the data. This function + * abstracts this common operation. +*/ +static void index_addr(struct denali_nand_info *denali, + uint32_t address, uint32_t data) +{ + writel(address, denali->flash_mem + INDEX_CTRL_REG); + writel(data, denali->flash_mem + INDEX_DATA_REG); +} + +/* Perform an indexed read of the device */ +static void index_addr_read_data(struct denali_nand_info *denali, + uint32_t address, uint32_t *pdata) +{ + writel(address, denali->flash_mem + INDEX_CTRL_REG); + *pdata = readl(denali->flash_mem + INDEX_DATA_REG); +} + +/* We need to buffer some data for some of the NAND core routines. + * The operations manage buffering that data. */ +static void reset_buf(struct denali_nand_info *denali) +{ + denali->buf.head = 0; + denali->buf.tail = 0; +} + +static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) +{ + denali->buf.buf[denali->buf.tail++] = byte; +} + +/* resets a specific device connected to the core */ +static void reset_bank(struct denali_nand_info *denali) +{ + uint32_t irq_status; + uint32_t irq_mask = INTR_STATUS__RST_COMP | + INTR_STATUS__TIME_OUT; + + clear_interrupts(denali); + + writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); + + irq_status = wait_for_irq(denali, irq_mask); + if (irq_status & INTR_STATUS__TIME_OUT) + debug("reset bank failed.\n"); +} + +/* Reset the flash controller */ +static uint32_t denali_nand_reset(struct denali_nand_info *denali) +{ + uint32_t i; + + for (i = 0; i < denali->max_banks; i++) + writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, + denali->flash_reg + INTR_STATUS(i)); + + for (i = 0; i < denali->max_banks; i++) { + writel(1 << i, denali->flash_reg + DEVICE_RESET); + while (!(readl(denali->flash_reg + INTR_STATUS(i)) & + (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) + if (readl(denali->flash_reg + INTR_STATUS(i)) & + INTR_STATUS__TIME_OUT) + debug("NAND Reset operation timed out on bank" + " %d\n", i); + } + + for (i = 0; i < denali->max_banks; i++) + writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, + denali->flash_reg + INTR_STATUS(i)); + + return 0; +} + +/* + * this routine calculates the ONFI timing values for a given mode and + * programs the clocking register accordingly. The mode is determined by + * the get_onfi_nand_para routine. + */ +static void nand_onfi_timing_set(struct denali_nand_info *denali, + uint16_t mode) +{ + uint32_t trea[6] = {40, 30, 25, 20, 20, 16}; + uint32_t trp[6] = {50, 25, 17, 15, 12, 10}; + uint32_t treh[6] = {30, 15, 15, 10, 10, 7}; + uint32_t trc[6] = {100, 50, 35, 30, 25, 20}; + uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15}; + uint32_t trloh[6] = {0, 0, 0, 0, 5, 5}; + uint32_t tcea[6] = {100, 45, 30, 25, 25, 25}; + uint32_t tadl[6] = {200, 100, 100, 100, 70, 70}; + uint32_t trhw[6] = {200, 100, 100, 100, 100, 100}; + uint32_t trhz[6] = {200, 100, 100, 100, 100, 100}; + uint32_t twhr[6] = {120, 80, 80, 60, 60, 60}; + uint32_t tcs[6] = {70, 35, 25, 25, 20, 15}; + + uint32_t tclsrising = 1; + uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid; + uint32_t dv_window = 0; + uint32_t en_lo, en_hi; + uint32_t acc_clks; + uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; + + en_lo = DIV_ROUND_UP(trp[mode], CLK_X); + en_hi = DIV_ROUND_UP(treh[mode], CLK_X); + if ((en_hi * CLK_X) < (treh[mode] + 2)) + en_hi++; + + if ((en_lo + en_hi) * CLK_X < trc[mode]) + en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X), + CLK_X); + + if ((en_lo + en_hi) < CLK_MULTI) + en_lo += CLK_MULTI - en_lo - en_hi; + + while (dv_window < 8) { + data_invalid_rhoh = en_lo * CLK_X + trhoh[mode]; + + data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode]; + + data_invalid = + data_invalid_rhoh < + data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh; + + dv_window = data_invalid - trea[mode]; + + if (dv_window < 8) + en_lo++; + } + + acc_clks = DIV_ROUND_UP(trea[mode], CLK_X); + + while (((acc_clks * CLK_X) - trea[mode]) < 3) + acc_clks++; + + if ((data_invalid - acc_clks * CLK_X) < 2) + debug("%s, Line %d: Warning!\n", __FILE__, __LINE__); + + addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X); + re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X); + re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X); + we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X); + cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X); + if (!tclsrising) + cs_cnt = DIV_ROUND_UP(tcs[mode], CLK_X); + if (cs_cnt == 0) + cs_cnt = 1; + + if (tcea[mode]) { + while (((cs_cnt * CLK_X) + trea[mode]) < tcea[mode]) + cs_cnt++; + } + + /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ + if ((readl(denali->flash_reg + MANUFACTURER_ID) == 0) && + (readl(denali->flash_reg + DEVICE_ID) == 0x88)) + acc_clks = 6; + + writel(acc_clks, denali->flash_reg + ACC_CLKS); + writel(re_2_we, denali->flash_reg + RE_2_WE); + writel(re_2_re, denali->flash_reg + RE_2_RE); + writel(we_2_re, denali->flash_reg + WE_2_RE); + writel(addr_2_data, denali->flash_reg + ADDR_2_DATA); + writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); + writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); + writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT); +} + +/* queries the NAND device to see what ONFI modes it supports. */ +static uint32_t get_onfi_nand_para(struct denali_nand_info *denali) +{ + int i; + /* + * we needn't to do a reset here because driver has already + * reset all the banks before + */ + if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) & + ONFI_TIMING_MODE__VALUE)) + return -EIO; + + for (i = 5; i > 0; i--) { + if (readl(denali->flash_reg + ONFI_TIMING_MODE) & + (0x01 << i)) + break; + } + + nand_onfi_timing_set(denali, i); + + /* By now, all the ONFI devices we know support the page cache */ + /* rw feature. So here we enable the pipeline_rw_ahead feature */ + return 0; +} + +static void get_samsung_nand_para(struct denali_nand_info *denali, + uint8_t device_id) +{ + if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ + /* Set timing register values according to datasheet */ + writel(5, denali->flash_reg + ACC_CLKS); + writel(20, denali->flash_reg + RE_2_WE); + writel(12, denali->flash_reg + WE_2_RE); + writel(14, denali->flash_reg + ADDR_2_DATA); + writel(3, denali->flash_reg + RDWR_EN_LO_CNT); + writel(2, denali->flash_reg + RDWR_EN_HI_CNT); + writel(2, denali->flash_reg + CS_SETUP_CNT); + } +} + +static void get_toshiba_nand_para(struct denali_nand_info *denali) +{ + uint32_t tmp; + + /* Workaround to fix a controller bug which reports a wrong */ + /* spare area size for some kind of Toshiba NAND device */ + if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && + (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { + writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); + tmp = readl(denali->flash_reg + DEVICES_CONNECTED) * + readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); + writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); + } +} + +static void get_hynix_nand_para(struct denali_nand_info *denali, + uint8_t device_id) +{ + uint32_t main_size, spare_size; + + switch (device_id) { + case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ + case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ + writel(128, denali->flash_reg + PAGES_PER_BLOCK); + writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); + writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); + main_size = 4096 * + readl(denali->flash_reg + DEVICES_CONNECTED); + spare_size = 224 * + readl(denali->flash_reg + DEVICES_CONNECTED); + writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); + writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); + writel(0, denali->flash_reg + DEVICE_WIDTH); + break; + default: + debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x)." + "Will use default parameter values instead.\n", + device_id); + } +} + +/* + * determines how many NAND chips are connected to the controller. Note for + * Intel CE4100 devices we don't support more than one device. + */ +static void find_valid_banks(struct denali_nand_info *denali) +{ + uint32_t id[denali->max_banks]; + int i; + + denali->total_used_banks = 1; + for (i = 0; i < denali->max_banks; i++) { + index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); + index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); + index_addr_read_data(denali, + (uint32_t)(MODE_11 | (i << 24) | 2), + &id[i]); + + if (i == 0) { + if (!(id[i] & 0x0ff)) + break; + } else { + if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) + denali->total_used_banks++; + else + break; + } + } +} + +/* + * Use the configuration feature register to determine the maximum number of + * banks that the hardware supports. + */ +static void detect_max_banks(struct denali_nand_info *denali) +{ + uint32_t features = readl(denali->flash_reg + FEATURES); + denali->max_banks = 2 << (features & FEATURES__N_BANKS); +} + +static void detect_partition_feature(struct denali_nand_info *denali) +{ + /* + * For MRST platform, denali->fwblks represent the + * number of blocks firmware is taken, + * FW is in protect partition and MTD driver has no + * permission to access it. So let driver know how many + * blocks it can't touch. + */ + if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { + if ((readl(denali->flash_reg + PERM_SRC_ID(1)) & + PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { + denali->fwblks = + ((readl(denali->flash_reg + MIN_MAX_BANK(1)) & + MIN_MAX_BANK__MIN_VALUE) * + denali->blksperchip) + + + (readl(denali->flash_reg + MIN_BLK_ADDR(1)) & + MIN_BLK_ADDR__VALUE); + } else { + denali->fwblks = SPECTRA_START_BLOCK; + } + } else { + denali->fwblks = SPECTRA_START_BLOCK; + } +} + +static uint32_t denali_nand_timing_set(struct denali_nand_info *denali) +{ + uint32_t id_bytes[5], addr; + uint8_t i, maf_id, device_id; + + /* Use read id method to get device ID and other + * params. For some NAND chips, controller can't + * report the correct device ID by reading from + * DEVICE_ID register + * */ + addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); + index_addr(denali, (uint32_t)addr | 0, 0x90); + index_addr(denali, (uint32_t)addr | 1, 0); + for (i = 0; i < 5; i++) + index_addr_read_data(denali, addr | 2, &id_bytes[i]); + maf_id = id_bytes[0]; + device_id = id_bytes[1]; + + if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & + ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ + if (get_onfi_nand_para(denali)) + return -EIO; + } else if (maf_id == 0xEC) { /* Samsung NAND */ + get_samsung_nand_para(denali, device_id); + } else if (maf_id == 0x98) { /* Toshiba NAND */ + get_toshiba_nand_para(denali); + } else if (maf_id == 0xAD) { /* Hynix NAND */ + get_hynix_nand_para(denali, device_id); + } + + find_valid_banks(denali); + + detect_partition_feature(denali); + + /* If the user specified to override the default timings + * with a specific ONFI mode, we apply those changes here. + */ + if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) + nand_onfi_timing_set(denali, onfi_timing_mode); + + return 0; +} + +/* validation function to verify that the controlling software is making + * a valid request + */ +static inline bool is_flash_bank_valid(int flash_bank) +{ + return flash_bank >= 0 && flash_bank < 4; +} + +static void denali_irq_init(struct denali_nand_info *denali) +{ + uint32_t int_mask = 0; + int i; + + /* Disable global interrupts */ + writel(0, denali->flash_reg + GLOBAL_INT_ENABLE); + + int_mask = DENALI_IRQ_ALL; + + /* Clear all status bits */ + for (i = 0; i < denali->max_banks; ++i) + writel(0xFFFF, denali->flash_reg + INTR_STATUS(i)); + + denali_irq_enable(denali, int_mask); +} + +/* This helper function setups the registers for ECC and whether or not + * the spare area will be transferred. */ +static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, + bool transfer_spare) +{ + int ecc_en_flag = 0, transfer_spare_flag = 0; + + /* set ECC, transfer spare bits if needed */ + ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; + transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; + + /* Enable spare area/ECC per user's request. */ + writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE); + /* applicable for MAP01 only */ + writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); +} + +/* sends a pipeline command operation to the controller. See the Denali NAND + * controller's user guide for more information (section 4.2.3.6). + */ +static int denali_send_pipeline_cmd(struct denali_nand_info *denali, + bool ecc_en, bool transfer_spare, + int access_type, int op) +{ + uint32_t addr, cmd, irq_status; + static uint32_t page_count = 1; + + setup_ecc_for_xfer(denali, ecc_en, transfer_spare); + + /* clear interrupts */ + clear_interrupts(denali); + + addr = BANK(denali->flash_bank) | denali->page; + + /* setup the acccess type */ + cmd = MODE_10 | addr; + index_addr(denali, cmd, access_type); + + /* setup the pipeline command */ + index_addr(denali, cmd, 0x2000 | op | page_count); + + cmd = MODE_01 | addr; + writel(cmd, denali->flash_mem + INDEX_CTRL_REG); + + if (op == DENALI_READ) { + /* wait for command to be accepted */ + irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP); + + if (irq_status == 0) + return -EIO; + } + + return 0; +} + +/* helper function that simply writes a buffer to the flash */ +static int write_data_to_flash_mem(struct denali_nand_info *denali, + const uint8_t *buf, int len) +{ + uint32_t i = 0, *buf32; + + /* verify that the len is a multiple of 4. see comment in + * read_data_from_flash_mem() */ + BUG_ON((len % 4) != 0); + + /* write the data to the flash memory */ + buf32 = (uint32_t *)buf; + for (i = 0; i < len / 4; i++) + writel(*buf32++, denali->flash_mem + INDEX_DATA_REG); + return i * 4; /* intent is to return the number of bytes read */ +} + +/* helper function that simply reads a buffer from the flash */ +static int read_data_from_flash_mem(struct denali_nand_info *denali, + uint8_t *buf, int len) +{ + uint32_t i, *buf32; + + /* + * we assume that len will be a multiple of 4, if not + * it would be nice to know about it ASAP rather than + * have random failures... + * This assumption is based on the fact that this + * function is designed to be used to read flash pages, + * which are typically multiples of 4... + */ + + BUG_ON((len % 4) != 0); + + /* transfer the data from the flash */ + buf32 = (uint32_t *)buf; + for (i = 0; i < len / 4; i++) + *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG); + + return i * 4; /* intent is to return the number of bytes read */ +} + +static void denali_mode_main_access(struct denali_nand_info *denali) +{ + uint32_t addr, cmd; + + addr = BANK(denali->flash_bank) | denali->page; + cmd = MODE_10 | addr; + index_addr(denali, cmd, MAIN_ACCESS); +} + +static void denali_mode_main_spare_access(struct denali_nand_info *denali) +{ + uint32_t addr, cmd; + + addr = BANK(denali->flash_bank) | denali->page; + cmd = MODE_10 | addr; + index_addr(denali, cmd, MAIN_SPARE_ACCESS); +} + +/* writes OOB data to the device */ +static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t irq_status; + uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | + INTR_STATUS__PROGRAM_FAIL; + int status = 0; + + denali->page = page; + + if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, + DENALI_WRITE) == 0) { + write_data_to_flash_mem(denali, buf, mtd->oobsize); + + /* wait for operation to complete */ + irq_status = wait_for_irq(denali, irq_mask); + + if (irq_status == 0) { + dev_err(denali->dev, "OOB write failed\n"); + status = -EIO; + } + } else { + printf("unable to send pipeline command\n"); + status = -EIO; + } + return status; +} + +/* reads OOB data from the device */ +static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t irq_mask = INTR_STATUS__LOAD_COMP, + irq_status = 0, addr = 0x0, cmd = 0x0; + + denali->page = page; + + if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, + DENALI_READ) == 0) { + read_data_from_flash_mem(denali, buf, mtd->oobsize); + + /* wait for command to be accepted + * can always use status0 bit as the mask is identical for each + * bank. */ + irq_status = wait_for_irq(denali, irq_mask); + + if (irq_status == 0) + printf("page on OOB timeout %d\n", denali->page); + + /* We set the device back to MAIN_ACCESS here as I observed + * instability with the controller if you do a block erase + * and the last transaction was a SPARE_ACCESS. Block erase + * is reliable (according to the MTD test infrastructure) + * if you are in MAIN_ACCESS. + */ + addr = BANK(denali->flash_bank) | denali->page; + cmd = MODE_10 | addr; + index_addr(denali, cmd, MAIN_ACCESS); + } +} + +/* this function examines buffers to see if they contain data that + * indicate that the buffer is part of an erased region of flash. + */ +static bool is_erased(uint8_t *buf, int len) +{ + int i = 0; + for (i = 0; i < len; i++) + if (buf[i] != 0xFF) + return false; + return true; +} + +/* programs the controller to either enable/disable DMA transfers */ +static void denali_enable_dma(struct denali_nand_info *denali, bool en) +{ + uint32_t reg_val = 0x0; + + if (en) + reg_val = DMA_ENABLE__FLAG; + + writel(reg_val, denali->flash_reg + DMA_ENABLE); + readl(denali->flash_reg + DMA_ENABLE); +} + +/* setups the HW to perform the data DMA */ +static void denali_setup_dma(struct denali_nand_info *denali, int op) +{ + uint32_t mode; + const int page_count = 1; + uint32_t addr = (uint32_t)denali->buf.dma_buf; + + flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf)); + +/* For Denali controller that is 64 bit bus IP core */ +#ifdef CONFIG_SYS_NAND_DENALI_64BIT + mode = MODE_10 | BANK(denali->flash_bank) | denali->page; + + /* DMA is a three step process */ + + /* 1. setup transfer type, interrupt when complete, + burst len = 64 bytes, the number of pages */ + index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); + + /* 2. set memory low address bits 31:0 */ + index_addr(denali, mode, addr); + + /* 3. set memory high address bits 64:32 */ + index_addr(denali, mode, 0); +#else + mode = MODE_10 | BANK(denali->flash_bank); + + /* DMA is a four step process */ + + /* 1. setup transfer type and # of pages */ + index_addr(denali, mode | denali->page, 0x2000 | op | page_count); + + /* 2. set memory high address bits 23:8 */ + index_addr(denali, mode | ((uint32_t)(addr >> 16) << 8), 0x2200); + + /* 3. set memory low address bits 23:8 */ + index_addr(denali, mode | ((uint32_t)addr << 8), 0x2300); + + /* 4. interrupt when complete, burst len = 64 bytes*/ + index_addr(denali, mode | 0x14000, 0x2400); +#endif +} + +/* Common DMA function */ +static uint32_t denali_dma_configuration(struct denali_nand_info *denali, + uint32_t ops, bool raw_xfer, + uint32_t irq_mask, int oob_required) +{ + uint32_t irq_status = 0; + /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */ + setup_ecc_for_xfer(denali, !raw_xfer, oob_required); + + /* clear any previous interrupt flags */ + clear_interrupts(denali); + + /* enable the DMA */ + denali_enable_dma(denali, true); + + /* setup the DMA */ + denali_setup_dma(denali, ops); + + /* wait for operation to complete */ + irq_status = wait_for_irq(denali, irq_mask); + + /* if ECC fault happen, seems we need delay before turning off DMA. + * If not, the controller will go into non responsive condition */ + if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) + udelay(100); + + /* disable the DMA */ + denali_enable_dma(denali, false); + + return irq_status; +} + +static int write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, bool raw_xfer, int oob_required) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + uint32_t irq_status = 0; + uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; + + denali->status = 0; + + /* copy buffer into DMA buffer */ + memcpy(denali->buf.dma_buf, buf, mtd->writesize); + + /* need extra memcpy for raw transfer */ + if (raw_xfer) + memcpy(denali->buf.dma_buf + mtd->writesize, + chip->oob_poi, mtd->oobsize); + + /* setting up DMA */ + irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer, + irq_mask, oob_required); + + /* if timeout happen, error out */ + if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) { + debug("DMA timeout for denali write_page\n"); + denali->status = NAND_STATUS_FAIL; + return -EIO; + } + + if (irq_status & INTR_STATUS__LOCKED_BLK) { + debug("Failed as write to locked block\n"); + denali->status = NAND_STATUS_FAIL; + return -EIO; + } + return 0; +} + +/* NAND core entry points */ + +/* + * this is the callback that the NAND core calls to write a page. Since + * writing a page with ECC or without is similar, all the work is done + * by write_page above. + */ +static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + /* + * for regular page writes, we let HW handle all the ECC + * data written to the device. + */ + if (oob_required) + /* switch to main + spare access */ + denali_mode_main_spare_access(denali); + else + /* switch to main access only */ + denali_mode_main_access(denali); + + return write_page(mtd, chip, buf, false, oob_required); +} + +/* + * This is the callback that the NAND core calls to write a page without ECC. + * raw access is similar to ECC page writes, so all the work is done in the + * write_page() function above. + */ +static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + /* + * for raw page writes, we want to disable ECC and simply write + * whatever data is in the buffer. + */ + + if (oob_required) + /* switch to main + spare access */ + denali_mode_main_spare_access(denali); + else + /* switch to main access only */ + denali_mode_main_access(denali); + + return write_page(mtd, chip, buf, true, oob_required); +} + +static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + return write_oob_data(mtd, chip->oob_poi, page); +} + +/* raw include ECC value and all the spare area */ +static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP; + + if (denali->page != page) { + debug("Missing NAND_CMD_READ0 command\n"); + return -EIO; + } + + if (oob_required) + /* switch to main + spare access */ + denali_mode_main_spare_access(denali); + else + /* switch to main access only */ + denali_mode_main_access(denali); + + /* setting up the DMA where ecc_enable is false */ + irq_status = denali_dma_configuration(denali, DENALI_READ, true, + irq_mask, oob_required); + + /* if timeout happen, error out */ + if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) { + debug("DMA timeout for denali_read_page_raw\n"); + return -EIO; + } + + /* splitting the content to destination buffer holder */ + memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize), + mtd->oobsize); + memcpy(buf, denali->buf.dma_buf, mtd->writesize); + + return 0; +} + +static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP; + + if (denali->page != page) { + debug("Missing NAND_CMD_READ0 command\n"); + return -EIO; + } + + if (oob_required) + /* switch to main + spare access */ + denali_mode_main_spare_access(denali); + else + /* switch to main access only */ + denali_mode_main_access(denali); + + /* setting up the DMA where ecc_enable is true */ + irq_status = denali_dma_configuration(denali, DENALI_READ, false, + irq_mask, oob_required); + + memcpy(buf, denali->buf.dma_buf, mtd->writesize); + + /* check whether any ECC error */ + if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) { + /* is the ECC cause by erase page, check using read_page_raw */ + debug(" Uncorrected ECC detected\n"); + denali_read_page_raw(mtd, chip, buf, oob_required, + denali->page); + + if (is_erased(buf, mtd->writesize) == true && + is_erased(chip->oob_poi, mtd->oobsize) == true) { + debug(" ECC error cause by erased block\n"); + /* false alarm, return the 0xFF */ + } else { + return -EIO; + } + } + memcpy(buf, denali->buf.dma_buf, mtd->writesize); + return 0; +} + +static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + read_oob_data(mtd, chip->oob_poi, page); + + return 0; +} + +static uint8_t denali_read_byte(struct mtd_info *mtd) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t addr, result; + + addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); + index_addr_read_data(denali, addr | 2, &result); + return (uint8_t)result & 0xFF; +} + +static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t i, addr, result; + + /* delay for tR (data transfer from Flash array to data register) */ + udelay(25); + + /* ensure device completed else additional delay and polling */ + wait_for_irq(denali, INTR_STATUS__INT_ACT); + + addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); + for (i = 0; i < len; i++) { + index_addr_read_data(denali, (uint32_t)addr | 2, &result); + write_byte_to_buf(denali, result); + } + memcpy(buf, denali->buf.buf, len); +} + +static void denali_select_chip(struct mtd_info *mtd, int chip) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + denali->flash_bank = chip; +} + +static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + int status = denali->status; + denali->status = 0; + + return status; +} + +static void denali_erase(struct mtd_info *mtd, int page) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t cmd, irq_status; + + /* clear interrupts */ + clear_interrupts(denali); + + /* setup page read request for access type */ + cmd = MODE_10 | BANK(denali->flash_bank) | page; + index_addr(denali, cmd, 0x1); + + /* wait for erase to complete or failure to occur */ + irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | + INTR_STATUS__ERASE_FAIL); + + if (irq_status & INTR_STATUS__ERASE_FAIL || + irq_status & INTR_STATUS__LOCKED_BLK) + denali->status = NAND_STATUS_FAIL; + else + denali->status = 0; +} + +static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, + int page) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t addr; + + switch (cmd) { + case NAND_CMD_PAGEPROG: + break; + case NAND_CMD_STATUS: + addr = MODE_11 | BANK(denali->flash_bank); + index_addr(denali, addr | 0, cmd); + break; + case NAND_CMD_READID: + case NAND_CMD_PARAM: + reset_buf(denali); + /* sometimes ManufactureId read from register is not right + * e.g. some of Micron MT29F32G08QAA MLC NAND chips + * So here we send READID cmd to NAND insteand + * */ + addr = MODE_11 | BANK(denali->flash_bank); + index_addr(denali, addr | 0, cmd); + index_addr(denali, addr | 1, col & 0xFF); + if (cmd == NAND_CMD_PARAM) + udelay(50); + break; + case NAND_CMD_RNDOUT: + addr = MODE_11 | BANK(denali->flash_bank); + index_addr(denali, addr | 0, cmd); + index_addr(denali, addr | 1, col & 0xFF); + index_addr(denali, addr | 1, col >> 8); + index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART); + break; + case NAND_CMD_READ0: + case NAND_CMD_SEQIN: + denali->page = page; + break; + case NAND_CMD_RESET: + reset_bank(denali); + break; + case NAND_CMD_READOOB: + /* TODO: Read OOB data */ + break; + case NAND_CMD_ERASE1: + /* + * supporting block erase only, not multiblock erase as + * it will cross plane and software need complex calculation + * to identify the block count for the cross plane + */ + denali_erase(mtd, page); + break; + case NAND_CMD_ERASE2: + /* nothing to do here as it was done during NAND_CMD_ERASE1 */ + break; + case NAND_CMD_UNLOCK1: + addr = MODE_10 | BANK(denali->flash_bank) | page; + index_addr(denali, addr | 0, DENALI_UNLOCK_START); + break; + case NAND_CMD_UNLOCK2: + addr = MODE_10 | BANK(denali->flash_bank) | page; + index_addr(denali, addr | 0, DENALI_UNLOCK_END); + break; + case NAND_CMD_LOCK: + addr = MODE_10 | BANK(denali->flash_bank); + index_addr(denali, addr | 0, DENALI_LOCK); + break; + default: + printf(": unsupported command received 0x%x\n", cmd); + break; + } +} +/* end NAND core entry points */ + +/* Initialization code to bring the device up to a known good state */ +static void denali_hw_init(struct denali_nand_info *denali) +{ + /* + * tell driver how many bit controller will skip before writing + * ECC code in OOB. This is normally used for bad block marker + */ + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, + denali->flash_reg + SPARE_AREA_SKIP_BYTES); + detect_max_banks(denali); + denali_nand_reset(denali); + writel(0x0F, denali->flash_reg + RB_PIN_ENABLED); + writel(CHIP_EN_DONT_CARE__FLAG, + denali->flash_reg + CHIP_ENABLE_DONT_CARE); + writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER); + + /* Should set value for these registers when init */ + writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); + writel(1, denali->flash_reg + ECC_ENABLE); + denali_nand_timing_set(denali); + denali_irq_init(denali); +} + +static struct nand_ecclayout nand_oob; + +static int denali_init(struct denali_nand_info *denali) +{ + int ret; + + denali_hw_init(denali); + + denali->mtd->name = "denali-nand"; + denali->mtd->owner = THIS_MODULE; + denali->mtd->priv = &denali->nand; + + /* register the driver with the NAND core subsystem */ + denali->nand.select_chip = denali_select_chip; + denali->nand.cmdfunc = denali_cmdfunc; + denali->nand.read_byte = denali_read_byte; + denali->nand.read_buf = denali_read_buf; + denali->nand.waitfunc = denali_waitfunc; + + /* + * scan for NAND devices attached to the controller + * this is the first stage in a two step process to register + * with the nand subsystem + */ + if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) { + ret = -ENXIO; + goto fail; + } + +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + /* check whether flash got BBT table (located at end of flash). As we + * use NAND_BBT_NO_OOB, the BBT page will start with + * bbt_pattern. We will have mirror pattern too */ + denali->nand.bbt_options |= NAND_BBT_USE_FLASH; + /* + * We are using main + spare with ECC support. As BBT need ECC support, + * we need to ensure BBT code don't write to OOB for the BBT pattern. + * All BBT info will be stored into data area with ECC support. + */ + denali->nand.bbt_options |= NAND_BBT_NO_OOB; +#endif + + denali->nand.ecc.mode = NAND_ECC_HW; + denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE; + + /* + * Tell driver the ecc strength. This register may be already set + * correctly. So we read this value out. + */ + denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION); + switch (denali->nand.ecc.size) { + case 512: + denali->nand.ecc.bytes = + (denali->nand.ecc.strength * 13 + 15) / 16 * 2; + break; + case 1024: + denali->nand.ecc.bytes = + (denali->nand.ecc.strength * 14 + 15) / 16 * 2; + break; + default: + pr_err("Unsupported ECC size\n"); + ret = -EINVAL; + goto fail; + } + nand_oob.eccbytes = denali->nand.ecc.bytes; + denali->nand.ecc.layout = &nand_oob; + + writel(denali->mtd->erasesize / denali->mtd->writesize, + denali->flash_reg + PAGES_PER_BLOCK); + writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0, + denali->flash_reg + DEVICE_WIDTH); + writel(denali->mtd->writesize, + denali->flash_reg + DEVICE_MAIN_AREA_SIZE); + writel(denali->mtd->oobsize, + denali->flash_reg + DEVICE_SPARE_AREA_SIZE); + if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0) + writel(1, denali->flash_reg + DEVICES_CONNECTED); + + /* override the default operations */ + denali->nand.ecc.read_page = denali_read_page; + denali->nand.ecc.read_page_raw = denali_read_page_raw; + denali->nand.ecc.write_page = denali_write_page; + denali->nand.ecc.write_page_raw = denali_write_page_raw; + denali->nand.ecc.read_oob = denali_read_oob; + denali->nand.ecc.write_oob = denali_write_oob; + + if (nand_scan_tail(denali->mtd)) { + ret = -ENXIO; + goto fail; + } + + ret = nand_register(0); + +fail: + return ret; +} + +static int __board_nand_init(void) +{ + struct denali_nand_info *denali; + + denali = kzalloc(sizeof(*denali), GFP_KERNEL); + if (!denali) + return -ENOMEM; + + /* + * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible + * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c + * still provides a "struct mtd_info nand_info" instance. + */ + denali->mtd = &nand_info[0]; + + /* + * In the future, these base addresses should be taken from + * Device Tree or platform data. + */ + denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; + + return denali_init(denali); +} + +void board_nand_init(void) +{ + if (__board_nand_init() < 0) + pr_warn("Failed to initialize Denali NAND controller.\n"); +} diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h new file mode 100644 index 0000000000..a258df00fd --- /dev/null +++ b/drivers/mtd/nand/denali.h @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2013-2014 Altera Corporation + * Copyright (C) 2009-2010, Intel Corporation and its suppliers. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define DEVICE_RESET 0x0 +#define DEVICE_RESET__BANK0 0x0001 +#define DEVICE_RESET__BANK1 0x0002 +#define DEVICE_RESET__BANK2 0x0004 +#define DEVICE_RESET__BANK3 0x0008 + +#define TRANSFER_SPARE_REG 0x10 +#define TRANSFER_SPARE_REG__FLAG 0x0001 + +#define LOAD_WAIT_CNT 0x20 +#define LOAD_WAIT_CNT__VALUE 0xffff + +#define PROGRAM_WAIT_CNT 0x30 +#define PROGRAM_WAIT_CNT__VALUE 0xffff + +#define ERASE_WAIT_CNT 0x40 +#define ERASE_WAIT_CNT__VALUE 0xffff + +#define INT_MON_CYCCNT 0x50 +#define INT_MON_CYCCNT__VALUE 0xffff + +#define RB_PIN_ENABLED 0x60 +#define RB_PIN_ENABLED__BANK0 0x0001 +#define RB_PIN_ENABLED__BANK1 0x0002 +#define RB_PIN_ENABLED__BANK2 0x0004 +#define RB_PIN_ENABLED__BANK3 0x0008 + +#define MULTIPLANE_OPERATION 0x70 +#define MULTIPLANE_OPERATION__FLAG 0x0001 + +#define MULTIPLANE_READ_ENABLE 0x80 +#define MULTIPLANE_READ_ENABLE__FLAG 0x0001 + +#define COPYBACK_DISABLE 0x90 +#define COPYBACK_DISABLE__FLAG 0x0001 + +#define CACHE_WRITE_ENABLE 0xa0 +#define CACHE_WRITE_ENABLE__FLAG 0x0001 + +#define CACHE_READ_ENABLE 0xb0 +#define CACHE_READ_ENABLE__FLAG 0x0001 + +#define PREFETCH_MODE 0xc0 +#define PREFETCH_MODE__PREFETCH_EN 0x0001 +#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0 + +#define CHIP_ENABLE_DONT_CARE 0xd0 +#define CHIP_EN_DONT_CARE__FLAG 0x01 + +#define ECC_ENABLE 0xe0 +#define ECC_ENABLE__FLAG 0x0001 + +#define GLOBAL_INT_ENABLE 0xf0 +#define GLOBAL_INT_EN_FLAG 0x01 + +#define WE_2_RE 0x100 +#define WE_2_RE__VALUE 0x003f + +#define ADDR_2_DATA 0x110 +#define ADDR_2_DATA__VALUE 0x003f + +#define RE_2_WE 0x120 +#define RE_2_WE__VALUE 0x003f + +#define ACC_CLKS 0x130 +#define ACC_CLKS__VALUE 0x000f + +#define NUMBER_OF_PLANES 0x140 +#define NUMBER_OF_PLANES__VALUE 0x0007 + +#define PAGES_PER_BLOCK 0x150 +#define PAGES_PER_BLOCK__VALUE 0xffff + +#define DEVICE_WIDTH 0x160 +#define DEVICE_WIDTH__VALUE 0x0003 + +#define DEVICE_MAIN_AREA_SIZE 0x170 +#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff + +#define DEVICE_SPARE_AREA_SIZE 0x180 +#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff + +#define TWO_ROW_ADDR_CYCLES 0x190 +#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001 + +#define MULTIPLANE_ADDR_RESTRICT 0x1a0 +#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001 + +#define ECC_CORRECTION 0x1b0 +#define ECC_CORRECTION__VALUE 0x001f + +#define READ_MODE 0x1c0 +#define READ_MODE__VALUE 0x000f + +#define WRITE_MODE 0x1d0 +#define WRITE_MODE__VALUE 0x000f + +#define COPYBACK_MODE 0x1e0 +#define COPYBACK_MODE__VALUE 0x000f + +#define RDWR_EN_LO_CNT 0x1f0 +#define RDWR_EN_LO_CNT__VALUE 0x001f + +#define RDWR_EN_HI_CNT 0x200 +#define RDWR_EN_HI_CNT__VALUE 0x001f + +#define MAX_RD_DELAY 0x210 +#define MAX_RD_DELAY__VALUE 0x000f + +#define CS_SETUP_CNT 0x220 +#define CS_SETUP_CNT__VALUE 0x001f + +#define SPARE_AREA_SKIP_BYTES 0x230 +#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f + +#define SPARE_AREA_MARKER 0x240 +#define SPARE_AREA_MARKER__VALUE 0xffff + +#define DEVICES_CONNECTED 0x250 +#define DEVICES_CONNECTED__VALUE 0x0007 + +#define DIE_MASK 0x260 +#define DIE_MASK__VALUE 0x00ff + +#define FIRST_BLOCK_OF_NEXT_PLANE 0x270 +#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff + +#define WRITE_PROTECT 0x280 +#define WRITE_PROTECT__FLAG 0x0001 + +#define RE_2_RE 0x290 +#define RE_2_RE__VALUE 0x003f + +#define MANUFACTURER_ID 0x300 +#define MANUFACTURER_ID__VALUE 0x00ff + +#define DEVICE_ID 0x310 +#define DEVICE_ID__VALUE 0x00ff + +#define DEVICE_PARAM_0 0x320 +#define DEVICE_PARAM_0__VALUE 0x00ff + +#define DEVICE_PARAM_1 0x330 +#define DEVICE_PARAM_1__VALUE 0x00ff + +#define DEVICE_PARAM_2 0x340 +#define DEVICE_PARAM_2__VALUE 0x00ff + +#define LOGICAL_PAGE_DATA_SIZE 0x350 +#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff + +#define LOGICAL_PAGE_SPARE_SIZE 0x360 +#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff + +#define REVISION 0x370 +#define REVISION__VALUE 0xffff + +#define ONFI_DEVICE_FEATURES 0x380 +#define ONFI_DEVICE_FEATURES__VALUE 0x003f + +#define ONFI_OPTIONAL_COMMANDS 0x390 +#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f + +#define ONFI_TIMING_MODE 0x3a0 +#define ONFI_TIMING_MODE__VALUE 0x003f + +#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 +#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f + +#define ONFI_DEVICE_NO_OF_LUNS 0x3c0 +#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff +#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100 + +#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 +#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff + +#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 +#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff + +#define FEATURES 0x3f0 +#define FEATURES__N_BANKS 0x0003 +#define FEATURES__ECC_MAX_ERR 0x003c +#define FEATURES__DMA 0x0040 +#define FEATURES__CMD_DMA 0x0080 +#define FEATURES__PARTITION 0x0100 +#define FEATURES__XDMA_SIDEBAND 0x0200 +#define FEATURES__GPREG 0x0400 +#define FEATURES__INDEX_ADDR 0x0800 + +#define TRANSFER_MODE 0x400 +#define TRANSFER_MODE__VALUE 0x0003 + +#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) +#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) + +/* + * Some versions of the IP have the ECC fixup handled in hardware. In this + * configuration we only get interrupted when the error is uncorrectable. + * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the + * old IP. + */ +#define INTR_STATUS__ECC_UNCOR_ERR 0x0001 +#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001 +#define INTR_STATUS__ECC_ERR 0x0002 +#define INTR_STATUS__DMA_CMD_COMP 0x0004 +#define INTR_STATUS__TIME_OUT 0x0008 +#define INTR_STATUS__PROGRAM_FAIL 0x0010 +#define INTR_STATUS__ERASE_FAIL 0x0020 +#define INTR_STATUS__LOAD_COMP 0x0040 +#define INTR_STATUS__PROGRAM_COMP 0x0080 +#define INTR_STATUS__ERASE_COMP 0x0100 +#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200 +#define INTR_STATUS__LOCKED_BLK 0x0400 +#define INTR_STATUS__UNSUP_CMD 0x0800 +#define INTR_STATUS__INT_ACT 0x1000 +#define INTR_STATUS__RST_COMP 0x2000 +#define INTR_STATUS__PIPE_CMD_ERR 0x4000 +#define INTR_STATUS__PAGE_XFER_INC 0x8000 + +#define INTR_EN__ECC_TRANSACTION_DONE 0x0001 +#define INTR_EN__ECC_ERR 0x0002 +#define INTR_EN__DMA_CMD_COMP 0x0004 +#define INTR_EN__TIME_OUT 0x0008 +#define INTR_EN__PROGRAM_FAIL 0x0010 +#define INTR_EN__ERASE_FAIL 0x0020 +#define INTR_EN__LOAD_COMP 0x0040 +#define INTR_EN__PROGRAM_COMP 0x0080 +#define INTR_EN__ERASE_COMP 0x0100 +#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200 +#define INTR_EN__LOCKED_BLK 0x0400 +#define INTR_EN__UNSUP_CMD 0x0800 +#define INTR_EN__INT_ACT 0x1000 +#define INTR_EN__RST_COMP 0x2000 +#define INTR_EN__PIPE_CMD_ERR 0x4000 +#define INTR_EN__PAGE_XFER_INC 0x8000 + +#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50)) +#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) +#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50)) + +#define DATA_INTR 0x550 +#define DATA_INTR__WRITE_SPACE_AV 0x0001 +#define DATA_INTR__READ_DATA_AV 0x0002 + +#define DATA_INTR_EN 0x560 +#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 +#define DATA_INTR_EN__READ_DATA_AV 0x0002 + +#define GPREG_0 0x570 +#define GPREG_0__VALUE 0xffff + +#define GPREG_1 0x580 +#define GPREG_1__VALUE 0xffff + +#define GPREG_2 0x590 +#define GPREG_2__VALUE 0xffff + +#define GPREG_3 0x5a0 +#define GPREG_3__VALUE 0xffff + +#define ECC_THRESHOLD 0x600 +#define ECC_THRESHOLD__VALUE 0x03ff + +#define ECC_ERROR_BLOCK_ADDRESS 0x610 +#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff + +#define ECC_ERROR_PAGE_ADDRESS 0x620 +#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff +#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000 + +#define ECC_ERROR_ADDRESS 0x630 +#define ECC_ERROR_ADDRESS__OFFSET 0x0fff +#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000 + +#define ERR_CORRECTION_INFO 0x640 +#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff +#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00 +#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 +#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 + +#define DMA_ENABLE 0x700 +#define DMA_ENABLE__FLAG 0x0001 + +#define IGNORE_ECC_DONE 0x710 +#define IGNORE_ECC_DONE__FLAG 0x0001 + +#define DMA_INTR 0x720 +#define DMA_INTR__TARGET_ERROR 0x0001 +#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 +#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 +#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 +#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 +#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 + +#define DMA_INTR_EN 0x730 +#define DMA_INTR_EN__TARGET_ERROR 0x0001 +#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 +#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 +#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 +#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 +#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 + +#define TARGET_ERR_ADDR_LO 0x740 +#define TARGET_ERR_ADDR_LO__VALUE 0xffff + +#define TARGET_ERR_ADDR_HI 0x750 +#define TARGET_ERR_ADDR_HI__VALUE 0xffff + +#define CHNL_ACTIVE 0x760 +#define CHNL_ACTIVE__CHANNEL0 0x0001 +#define CHNL_ACTIVE__CHANNEL1 0x0002 +#define CHNL_ACTIVE__CHANNEL2 0x0004 +#define CHNL_ACTIVE__CHANNEL3 0x0008 + +#define ACTIVE_SRC_ID 0x800 +#define ACTIVE_SRC_ID__VALUE 0x00ff + +#define PTN_INTR 0x810 +#define PTN_INTR__CONFIG_ERROR 0x0001 +#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 +#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 +#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 +#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 +#define PTN_INTR__REG_ACCESS_ERROR 0x0020 + +#define PTN_INTR_EN 0x820 +#define PTN_INTR_EN__CONFIG_ERROR 0x0001 +#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 +#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 +#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 +#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 +#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 + +#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40)) +#define PERM_SRC_ID__SRCID 0x00ff +#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800 +#define PERM_SRC_ID__WRITE_ACTIVE 0x2000 +#define PERM_SRC_ID__READ_ACTIVE 0x4000 +#define PERM_SRC_ID__PARTITION_VALID 0x8000 + +#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40)) +#define MIN_BLK_ADDR__VALUE 0xffff + +#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40)) +#define MAX_BLK_ADDR__VALUE 0xffff + +#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40)) +#define MIN_MAX_BANK__MIN_VALUE 0x0003 +#define MIN_MAX_BANK__MAX_VALUE 0x000c + +/* lld.h */ +#define GOOD_BLOCK 0 +#define DEFECTIVE_BLOCK 1 +#define READ_ERROR 2 + +#define CLK_X 5 +#define CLK_MULTI 4 + +/* spectraswconfig.h */ +#define CMD_DMA 0 + +#define SPECTRA_PARTITION_ID 0 +/**** Block Table and Reserved Block Parameters *****/ +#define SPECTRA_START_BLOCK 3 +#define NUM_FREE_BLOCKS_GATE 30 + +/* KBV - Updated to LNW scratch register address */ +#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR +#define SCRATCH_REG_SIZE 64 + +#define GLOB_HWCTL_DEFAULT_BLKS 2048 + +#define CUSTOM_CONF_PARAMS 0 + +#ifndef _LLD_NAND_ +#define _LLD_NAND_ + +#define INDEX_CTRL_REG 0x0 +#define INDEX_DATA_REG 0x10 + +#define MODE_00 0x00000000 +#define MODE_01 0x04000000 +#define MODE_10 0x08000000 +#define MODE_11 0x0C000000 + + +#define DATA_TRANSFER_MODE 0 +#define PROTECTION_PER_BLOCK 1 +#define LOAD_WAIT_COUNT 2 +#define PROGRAM_WAIT_COUNT 3 +#define ERASE_WAIT_COUNT 4 +#define INT_MONITOR_CYCLE_COUNT 5 +#define READ_BUSY_PIN_ENABLED 6 +#define MULTIPLANE_OPERATION_SUPPORT 7 +#define PRE_FETCH_MODE 8 +#define CE_DONT_CARE_SUPPORT 9 +#define COPYBACK_SUPPORT 10 +#define CACHE_WRITE_SUPPORT 11 +#define CACHE_READ_SUPPORT 12 +#define NUM_PAGES_IN_BLOCK 13 +#define ECC_ENABLE_SELECT 14 +#define WRITE_ENABLE_2_READ_ENABLE 15 +#define ADDRESS_2_DATA 16 +#define READ_ENABLE_2_WRITE_ENABLE 17 +#define TWO_ROW_ADDRESS_CYCLES 18 +#define MULTIPLANE_ADDRESS_RESTRICT 19 +#define ACC_CLOCKS 20 +#define READ_WRITE_ENABLE_LOW_COUNT 21 +#define READ_WRITE_ENABLE_HIGH_COUNT 22 + +#define ECC_SECTOR_SIZE 512 + +#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) + +struct nand_buf { + int head; + int tail; + /* seprating dma_buf as buf can be used for status read purpose */ + uint8_t dma_buf[DENALI_BUF_SIZE] __aligned(64); + uint8_t buf[DENALI_BUF_SIZE]; +}; + +#define INTEL_CE4100 1 +#define INTEL_MRST 2 +#define DT 3 + +struct denali_nand_info { + struct mtd_info *mtd; + struct nand_chip nand; + int flash_bank; /* currently selected chip */ + int status; + int platform; + struct nand_buf buf; + struct device *dev; + int total_used_banks; + uint32_t block; /* stored for future use */ + uint32_t page; + void __iomem *flash_reg; /* Mapped io reg base address */ + void __iomem *flash_mem; /* Mapped io reg base address */ + + /* elements used by ISR */ + /*struct completion complete;*/ + + uint32_t irq_status; + int irq_debug_array[32]; + int idx; + int irq; + + uint32_t devnum; /* represent how many nands connected */ + uint32_t fwblks; /* represent how many blocks FW used */ + uint32_t totalblks; + uint32_t blksperchip; + uint32_t bbtskipbytes; + uint32_t max_banks; +}; + +#endif /*_LLD_NAND_*/ diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c new file mode 100644 index 0000000000..e98f537c2c --- /dev/null +++ b/drivers/mtd/nand/denali_spl.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "denali.h" + +#define SPARE_ACCESS 0x41 +#define MAIN_ACCESS 0x42 +#define PIPELINE_ACCESS 0x2000 + +#define BANK(x) ((x) << 24) + +static void __iomem *denali_flash_mem = + (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; +static void __iomem *denali_flash_reg = + (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + +static const int flash_bank; +static uint8_t page_buffer[NAND_MAX_PAGESIZE]; +static int page_size, oob_size, pages_per_block; + +static void index_addr(uint32_t address, uint32_t data) +{ + writel(address, denali_flash_mem + INDEX_CTRL_REG); + writel(data, denali_flash_mem + INDEX_DATA_REG); +} + +static int wait_for_irq(uint32_t irq_mask) +{ + unsigned long timeout = 1000000; + uint32_t intr_status; + + do { + intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank)); + + if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) { + debug("Uncorrected ECC detected\n"); + return -EIO; + } + + if (intr_status & irq_mask) + break; + + udelay(1); + timeout--; + } while (timeout); + + if (!timeout) { + debug("Timeout with interrupt status %08x\n", intr_status); + return -EIO; + } + + return 0; +} + +static void read_data_from_flash_mem(uint8_t *buf, int len) +{ + int i; + uint32_t *buf32; + + /* transfer the data from the flash */ + buf32 = (uint32_t *)buf; + + /* + * Let's take care of unaligned access although it rarely happens. + * Avoid put_unaligned() for the normal use cases since it leads to + * a bit performance regression. + */ + if ((unsigned long)buf32 % 4) { + for (i = 0; i < len / 4; i++) + put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG), + buf32++); + } else { + for (i = 0; i < len / 4; i++) + *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG); + } + + if (len % 4) { + u32 tmp; + + tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG)); + buf = (uint8_t *)buf32; + for (i = 0; i < len % 4; i++) { + *buf++ = tmp; + tmp >>= 8; + } + } +} + +int denali_send_pipeline_cmd(int page, int ecc_en, int access_type) +{ + uint32_t addr, cmd; + static uint32_t page_count = 1; + + writel(ecc_en, denali_flash_reg + ECC_ENABLE); + + /* clear all bits of intr_status. */ + writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank)); + + addr = BANK(flash_bank) | page; + + /* setup the acccess type */ + cmd = MODE_10 | addr; + index_addr(cmd, access_type); + + /* setup the pipeline command */ + index_addr(cmd, PIPELINE_ACCESS | page_count); + + cmd = MODE_01 | addr; + writel(cmd, denali_flash_mem + INDEX_CTRL_REG); + + return wait_for_irq(INTR_STATUS__LOAD_COMP); +} + +static int nand_read_oob(void *buf, int page) +{ + int ret; + + ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS); + if (ret < 0) + return ret; + + read_data_from_flash_mem(buf, oob_size); + + return 0; +} + +static int nand_read_page(void *buf, int page) +{ + int ret; + + ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS); + if (ret < 0) + return ret; + + read_data_from_flash_mem(buf, page_size); + + return 0; +} + +static int nand_block_isbad(int block) +{ + int ret; + + ret = nand_read_oob(page_buffer, block * pages_per_block); + if (ret < 0) + return ret; + + return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff; +} + +/* nand_init() - initialize data to make nand usable by SPL */ +void nand_init(void) +{ + /* access to main area */ + writel(0, denali_flash_reg + TRANSFER_SPARE_REG); + + /* + * These registers are expected to be already set by the hardware + * or earlier boot code. So we read these values out. + */ + page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); + oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); + pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + int block, page, column, readlen; + int ret; + int force_bad_block_check = 1; + + page = offs / page_size; + column = offs % page_size; + + block = page / pages_per_block; + page = page % pages_per_block; + + while (size) { + if (force_bad_block_check || page == 0) { + ret = nand_block_isbad(block); + if (ret < 0) + return ret; + + if (ret) { + block++; + continue; + } + } + + force_bad_block_check = 0; + + if (unlikely(column || size < page_size)) { + /* Partial page read */ + ret = nand_read_page(page_buffer, + block * pages_per_block + page); + if (ret < 0) + return ret; + + readlen = min(page_size - column, (int)size); + memcpy(dst, page_buffer, readlen); + + column = 0; + } else { + ret = nand_read_page(dst, + block * pages_per_block + page); + if (ret < 0) + return ret; + + readlen = page_size; + } + + size -= readlen; + dst += readlen; + page++; + if (page == pages_per_block) { + block++; + page = 0; + } + } + + return 0; +} + +void nand_deselect(void) {} diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c deleted file mode 100644 index 4cd741ebbb..0000000000 --- a/drivers/mtd/nand/diskonchip.c +++ /dev/null @@ -1,1780 +0,0 @@ -/* - * drivers/mtd/nand/diskonchip.c - * - * (C) 2003 Red Hat, Inc. - * (C) 2004 Dan Brown - * (C) 2004 Kalev Lember - * - * Author: David Woodhouse - * Additional Diskonchip 2000 and Millennium support by Dan Brown - * Diskonchip Millennium Plus support by Kalev Lember - * - * Error correction code lifted from the old docecc code - * Author: Fabrice Bellard (fabrice.bellard@netgem.com) - * Copyright (C) 2000 Netgem S.A. - * converted to the generic Reed-Solomon library by Thomas Gleixner - * - * Interface to generic NAND code for M-Systems DiskOnChip devices - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* Where to look for the devices? */ -#ifndef CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS -#define CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS 0 -#endif - -static unsigned long __initdata doc_locations[] = { -#if defined (__alpha__) || defined(__i386__) || defined(__x86_64__) -#ifdef CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH - 0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000, - 0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000, - 0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000, - 0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000, - 0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000, -#else /* CONFIG_MTD_DOCPROBE_HIGH */ - 0xc8000, 0xca000, 0xcc000, 0xce000, - 0xd0000, 0xd2000, 0xd4000, 0xd6000, - 0xd8000, 0xda000, 0xdc000, 0xde000, - 0xe0000, 0xe2000, 0xe4000, 0xe6000, - 0xe8000, 0xea000, 0xec000, 0xee000, -#endif /* CONFIG_MTD_DOCPROBE_HIGH */ -#else -#warning Unknown architecture for DiskOnChip. No default probe locations defined -#endif - 0xffffffff }; - -static struct mtd_info *doclist = NULL; - -struct doc_priv { - void __iomem *virtadr; - unsigned long physadr; - u_char ChipID; - u_char CDSNControl; - int chips_per_floor; /* The number of chips detected on each floor */ - int curfloor; - int curchip; - int mh0_page; - int mh1_page; - struct mtd_info *nextdoc; -}; - -/* This is the syndrome computed by the HW ecc generator upon reading an empty - page, one with all 0xff for data and stored ecc code. */ -static u_char empty_read_syndrome[6] = { 0x26, 0xff, 0x6d, 0x47, 0x73, 0x7a }; - -/* This is the ecc value computed by the HW ecc generator upon writing an empty - page, one with all 0xff for data. */ -static u_char empty_write_ecc[6] = { 0x4b, 0x00, 0xe2, 0x0e, 0x93, 0xf7 }; - -#define INFTL_BBT_RESERVED_BLOCKS 4 - -#define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DOC_ChipID_DocMilPlus32) -#define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil) -#define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k) - -static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int bitmask); -static void doc200x_select_chip(struct mtd_info *mtd, int chip); - -static int debug = 0; -module_param(debug, int, 0); - -static int try_dword = 1; -module_param(try_dword, int, 0); - -static int no_ecc_failures = 0; -module_param(no_ecc_failures, int, 0); - -static int no_autopart = 0; -module_param(no_autopart, int, 0); - -static int show_firmware_partition = 0; -module_param(show_firmware_partition, int, 0); - -#ifdef CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE -static int inftl_bbt_write = 1; -#else -static int inftl_bbt_write = 0; -#endif -module_param(inftl_bbt_write, int, 0); - -static unsigned long doc_config_location = CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS; -module_param(doc_config_location, ulong, 0); -MODULE_PARM_DESC(doc_config_location, "Physical memory address at which to probe for DiskOnChip"); - -/* Sector size for HW ECC */ -#define SECTOR_SIZE 512 -/* The sector bytes are packed into NB_DATA 10 bit words */ -#define NB_DATA (((SECTOR_SIZE + 1) * 8 + 6) / 10) -/* Number of roots */ -#define NROOTS 4 -/* First consective root */ -#define FCR 510 -/* Number of symbols */ -#define NN 1023 - -/* the Reed Solomon control structure */ -static struct rs_control *rs_decoder; - -/* - * The HW decoder in the DoC ASIC's provides us a error syndrome, - * which we must convert to a standard syndrome usable by the generic - * Reed-Solomon library code. - * - * Fabrice Bellard figured this out in the old docecc code. I added - * some comments, improved a minor bit and converted it to make use - * of the generic Reed-Solomon libary. tglx - */ -static int doc_ecc_decode(struct rs_control *rs, uint8_t *data, uint8_t *ecc) -{ - int i, j, nerr, errpos[8]; - uint8_t parity; - uint16_t ds[4], s[5], tmp, errval[8], syn[4]; - - /* Convert the ecc bytes into words */ - ds[0] = ((ecc[4] & 0xff) >> 0) | ((ecc[5] & 0x03) << 8); - ds[1] = ((ecc[5] & 0xfc) >> 2) | ((ecc[2] & 0x0f) << 6); - ds[2] = ((ecc[2] & 0xf0) >> 4) | ((ecc[3] & 0x3f) << 4); - ds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2); - parity = ecc[1]; - - /* Initialize the syndrome buffer */ - for (i = 0; i < NROOTS; i++) - s[i] = ds[0]; - /* - * Evaluate - * s[i] = ds[3]x^3 + ds[2]x^2 + ds[1]x^1 + ds[0] - * where x = alpha^(FCR + i) - */ - for (j = 1; j < NROOTS; j++) { - if (ds[j] == 0) - continue; - tmp = rs->index_of[ds[j]]; - for (i = 0; i < NROOTS; i++) - s[i] ^= rs->alpha_to[rs_modnn(rs, tmp + (FCR + i) * j)]; - } - - /* Calc s[i] = s[i] / alpha^(v + i) */ - for (i = 0; i < NROOTS; i++) { - if (syn[i]) - syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i)); - } - /* Call the decoder library */ - nerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval); - - /* Incorrectable errors ? */ - if (nerr < 0) - return nerr; - - /* - * Correct the errors. The bitpositions are a bit of magic, - * but they are given by the design of the de/encoder circuit - * in the DoC ASIC's. - */ - for (i = 0; i < nerr; i++) { - int index, bitpos, pos = 1015 - errpos[i]; - uint8_t val; - if (pos >= NB_DATA && pos < 1019) - continue; - if (pos < NB_DATA) { - /* extract bit position (MSB first) */ - pos = 10 * (NB_DATA - 1 - pos) - 6; - /* now correct the following 10 bits. At most two bytes - can be modified since pos is even */ - index = (pos >> 3) ^ 1; - bitpos = pos & 7; - if ((index >= 0 && index < SECTOR_SIZE) || index == (SECTOR_SIZE + 1)) { - val = (uint8_t) (errval[i] >> (2 + bitpos)); - parity ^= val; - if (index < SECTOR_SIZE) - data[index] ^= val; - } - index = ((pos >> 3) + 1) ^ 1; - bitpos = (bitpos + 10) & 7; - if (bitpos == 0) - bitpos = 8; - if ((index >= 0 && index < SECTOR_SIZE) || index == (SECTOR_SIZE + 1)) { - val = (uint8_t) (errval[i] << (8 - bitpos)); - parity ^= val; - if (index < SECTOR_SIZE) - data[index] ^= val; - } - } - } - /* If the parity is wrong, no rescue possible */ - return parity ? -EBADMSG : nerr; -} - -static void DoC_Delay(struct doc_priv *doc, unsigned short cycles) -{ - volatile char dummy; - int i; - - for (i = 0; i < cycles; i++) { - if (DoC_is_Millennium(doc)) - dummy = ReadDOC(doc->virtadr, NOP); - else if (DoC_is_MillenniumPlus(doc)) - dummy = ReadDOC(doc->virtadr, Mplus_NOP); - else - dummy = ReadDOC(doc->virtadr, DOCStatus); - } - -} - -#define CDSN_CTRL_FR_B_MASK (CDSN_CTRL_FR_B0 | CDSN_CTRL_FR_B1) - -/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */ -static int _DoC_WaitReady(struct doc_priv *doc) -{ - void __iomem *docptr = doc->virtadr; - unsigned long timeo = jiffies + (HZ * 10); - - if (debug) - printk("_DoC_WaitReady...\n"); - /* Out-of-line routine to wait for chip response */ - if (DoC_is_MillenniumPlus(doc)) { - while ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { - if (time_after(jiffies, timeo)) { - printk("_DoC_WaitReady timed out.\n"); - return -EIO; - } - udelay(1); - cond_resched(); - } - } else { - while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { - if (time_after(jiffies, timeo)) { - printk("_DoC_WaitReady timed out.\n"); - return -EIO; - } - udelay(1); - cond_resched(); - } - } - - return 0; -} - -static inline int DoC_WaitReady(struct doc_priv *doc) -{ - void __iomem *docptr = doc->virtadr; - int ret = 0; - - if (DoC_is_MillenniumPlus(doc)) { - DoC_Delay(doc, 4); - - if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) - /* Call the out-of-line routine to wait */ - ret = _DoC_WaitReady(doc); - } else { - DoC_Delay(doc, 4); - - if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) - /* Call the out-of-line routine to wait */ - ret = _DoC_WaitReady(doc); - DoC_Delay(doc, 2); - } - - if (debug) - printk("DoC_WaitReady OK\n"); - return ret; -} - -static void doc2000_write_byte(struct mtd_info *mtd, u_char datum) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - if (debug) - printk("write_byte %02x\n", datum); - WriteDOC(datum, docptr, CDSNSlowIO); - WriteDOC(datum, docptr, 2k_CDSN_IO); -} - -static u_char doc2000_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - u_char ret; - - ReadDOC(docptr, CDSNSlowIO); - DoC_Delay(doc, 2); - ret = ReadDOC(docptr, 2k_CDSN_IO); - if (debug) - printk("read_byte returns %02x\n", ret); - return ret; -} - -static void doc2000_writebuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - if (debug) - printk("writebuf of %d bytes: ", len); - for (i = 0; i < len; i++) { - WriteDOC_(buf[i], docptr, DoC_2k_CDSN_IO + i); - if (debug && i < 16) - printk("%02x ", buf[i]); - } - if (debug) - printk("\n"); -} - -static void doc2000_readbuf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("readbuf of %d bytes: ", len); - - for (i = 0; i < len; i++) { - buf[i] = ReadDOC(docptr, 2k_CDSN_IO + i); - } -} - -static void doc2000_readbuf_dword(struct mtd_info *mtd, - u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("readbuf_dword of %d bytes: ", len); - - if (unlikely((((unsigned long)buf) | len) & 3)) { - for (i = 0; i < len; i++) { - *(uint8_t *) (&buf[i]) = ReadDOC(docptr, 2k_CDSN_IO + i); - } - } else { - for (i = 0; i < len; i += 4) { - *(uint32_t*) (&buf[i]) = readl(docptr + DoC_2k_CDSN_IO + i); - } - } -} - -static int doc2000_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - for (i = 0; i < len; i++) - if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO)) - return -EFAULT; - return 0; -} - -static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - uint16_t ret; - - doc200x_select_chip(mtd, nr); - doc200x_hwcontrol(mtd, NAND_CMD_READID, - NAND_CTRL_CLE | NAND_CTRL_CHANGE); - doc200x_hwcontrol(mtd, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE); - doc200x_hwcontrol(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - - /* We cant' use dev_ready here, but at least we wait for the - * command to complete - */ - udelay(50); - - ret = this->read_byte(mtd) << 8; - ret |= this->read_byte(mtd); - - if (doc->ChipID == DOC_ChipID_Doc2k && try_dword && !nr) { - /* First chip probe. See if we get same results by 32-bit access */ - union { - uint32_t dword; - uint8_t byte[4]; - } ident; - void __iomem *docptr = doc->virtadr; - - doc200x_hwcontrol(mtd, NAND_CMD_READID, - NAND_CTRL_CLE | NAND_CTRL_CHANGE); - doc200x_hwcontrol(mtd, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE); - doc200x_hwcontrol(mtd, NAND_CMD_NONE, - NAND_NCE | NAND_CTRL_CHANGE); - - udelay(50); - - ident.dword = readl(docptr + DoC_2k_CDSN_IO); - if (((ident.byte[0] << 8) | ident.byte[1]) == ret) { - printk(KERN_INFO "DiskOnChip 2000 responds to DWORD access\n"); - this->read_buf = &doc2000_readbuf_dword; - } - } - - return ret; -} - -static void __init doc2000_count_chips(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - uint16_t mfrid; - int i; - - /* Max 4 chips per floor on DiskOnChip 2000 */ - doc->chips_per_floor = 4; - - /* Find out what the first chip is */ - mfrid = doc200x_ident_chip(mtd, 0); - - /* Find how many chips in each floor. */ - for (i = 1; i < 4; i++) { - if (doc200x_ident_chip(mtd, i) != mfrid) - break; - } - doc->chips_per_floor = i; - printk(KERN_DEBUG "Detected %d chips per floor.\n", i); -} - -static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this) -{ - struct doc_priv *doc = this->priv; - - int status; - - DoC_WaitReady(doc); - this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); - DoC_WaitReady(doc); - status = (int)this->read_byte(mtd); - - return status; -} - -static void doc2001_write_byte(struct mtd_info *mtd, u_char datum) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - WriteDOC(datum, docptr, CDSNSlowIO); - WriteDOC(datum, docptr, Mil_CDSN_IO); - WriteDOC(datum, docptr, WritePipeTerm); -} - -static u_char doc2001_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - /*ReadDOC(docptr, CDSNSlowIO); */ - /* 11.4.5 -- delay twice to allow extended length cycle */ - DoC_Delay(doc, 2); - ReadDOC(docptr, ReadPipeInit); - /*return ReadDOC(docptr, Mil_CDSN_IO); */ - return ReadDOC(docptr, LastDataRead); -} - -static void doc2001_writebuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - for (i = 0; i < len; i++) - WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); - /* Terminate write pipeline */ - WriteDOC(0x00, docptr, WritePipeTerm); -} - -static void doc2001_readbuf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - /* Start read pipeline */ - ReadDOC(docptr, ReadPipeInit); - - for (i = 0; i < len - 1; i++) - buf[i] = ReadDOC(docptr, Mil_CDSN_IO + (i & 0xff)); - - /* Terminate read pipeline */ - buf[i] = ReadDOC(docptr, LastDataRead); -} - -static int doc2001_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - /* Start read pipeline */ - ReadDOC(docptr, ReadPipeInit); - - for (i = 0; i < len - 1; i++) - if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { - ReadDOC(docptr, LastDataRead); - return i; - } - if (buf[i] != ReadDOC(docptr, LastDataRead)) - return i; - return 0; -} - -static u_char doc2001plus_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - u_char ret; - - ReadDOC(docptr, Mplus_ReadPipeInit); - ReadDOC(docptr, Mplus_ReadPipeInit); - ret = ReadDOC(docptr, Mplus_LastDataRead); - if (debug) - printk("read_byte returns %02x\n", ret); - return ret; -} - -static void doc2001plus_writebuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("writebuf of %d bytes: ", len); - for (i = 0; i < len; i++) { - WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); - if (debug && i < 16) - printk("%02x ", buf[i]); - } - if (debug) - printk("\n"); -} - -static void doc2001plus_readbuf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("readbuf of %d bytes: ", len); - - /* Start read pipeline */ - ReadDOC(docptr, Mplus_ReadPipeInit); - ReadDOC(docptr, Mplus_ReadPipeInit); - - for (i = 0; i < len - 2; i++) { - buf[i] = ReadDOC(docptr, Mil_CDSN_IO); - if (debug && i < 16) - printk("%02x ", buf[i]); - } - - /* Terminate read pipeline */ - buf[len - 2] = ReadDOC(docptr, Mplus_LastDataRead); - if (debug && i < 16) - printk("%02x ", buf[len - 2]); - buf[len - 1] = ReadDOC(docptr, Mplus_LastDataRead); - if (debug && i < 16) - printk("%02x ", buf[len - 1]); - if (debug) - printk("\n"); -} - -static int doc2001plus_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("verifybuf of %d bytes: ", len); - - /* Start read pipeline */ - ReadDOC(docptr, Mplus_ReadPipeInit); - ReadDOC(docptr, Mplus_ReadPipeInit); - - for (i = 0; i < len - 2; i++) - if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { - ReadDOC(docptr, Mplus_LastDataRead); - ReadDOC(docptr, Mplus_LastDataRead); - return i; - } - if (buf[len - 2] != ReadDOC(docptr, Mplus_LastDataRead)) - return len - 2; - if (buf[len - 1] != ReadDOC(docptr, Mplus_LastDataRead)) - return len - 1; - return 0; -} - -static void doc2001plus_select_chip(struct mtd_info *mtd, int chip) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int floor = 0; - - if (debug) - printk("select chip (%d)\n", chip); - - if (chip == -1) { - /* Disable flash internally */ - WriteDOC(0, docptr, Mplus_FlashSelect); - return; - } - - floor = chip / doc->chips_per_floor; - chip -= (floor * doc->chips_per_floor); - - /* Assert ChipEnable and deassert WriteProtect */ - WriteDOC((DOC_FLASH_CE), docptr, Mplus_FlashSelect); - this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); - - doc->curchip = chip; - doc->curfloor = floor; -} - -static void doc200x_select_chip(struct mtd_info *mtd, int chip) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int floor = 0; - - if (debug) - printk("select chip (%d)\n", chip); - - if (chip == -1) - return; - - floor = chip / doc->chips_per_floor; - chip -= (floor * doc->chips_per_floor); - - /* 11.4.4 -- deassert CE before changing chip */ - doc200x_hwcontrol(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); - - WriteDOC(floor, docptr, FloorSelect); - WriteDOC(chip, docptr, CDSNDeviceSelect); - - doc200x_hwcontrol(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - - doc->curchip = chip; - doc->curfloor = floor; -} - -#define CDSN_CTRL_MSK (CDSN_CTRL_CE | CDSN_CTRL_CLE | CDSN_CTRL_ALE) - -static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - if (ctrl & NAND_CTRL_CHANGE) { - doc->CDSNControl &= ~CDSN_CTRL_MSK; - doc->CDSNControl |= ctrl & CDSN_CTRL_MSK; - if (debug) - printk("hwcontrol(%d): %02x\n", cmd, doc->CDSNControl); - WriteDOC(doc->CDSNControl, docptr, CDSNControl); - /* 11.4.3 -- 4 NOPs after CSDNControl write */ - DoC_Delay(doc, 4); - } - if (cmd != NAND_CMD_NONE) { - if (DoC_is_2000(doc)) - doc2000_write_byte(mtd, cmd); - else - doc2001_write_byte(mtd, cmd); - } -} - -static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - /* - * Must terminate write pipeline before sending any commands - * to the device. - */ - if (command == NAND_CMD_PAGEPROG) { - WriteDOC(0x00, docptr, Mplus_WritePipeTerm); - WriteDOC(0x00, docptr, Mplus_WritePipeTerm); - } - - /* - * Write out the command to the device. - */ - if (command == NAND_CMD_SEQIN) { - int readcmd; - - if (column >= mtd->writesize) { - /* OOB area */ - column -= mtd->writesize; - readcmd = NAND_CMD_READOOB; - } else if (column < 256) { - /* First 256 bytes --> READ0 */ - readcmd = NAND_CMD_READ0; - } else { - column -= 256; - readcmd = NAND_CMD_READ1; - } - WriteDOC(readcmd, docptr, Mplus_FlashCmd); - } - WriteDOC(command, docptr, Mplus_FlashCmd); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - - if (column != -1 || page_addr != -1) { - /* Serially input address */ - if (column != -1) { - /* Adjust columns for 16 bit buswidth */ - if (this->options & NAND_BUSWIDTH_16) - column >>= 1; - WriteDOC(column, docptr, Mplus_FlashAddress); - } - if (page_addr != -1) { - WriteDOC((unsigned char)(page_addr & 0xff), docptr, Mplus_FlashAddress); - WriteDOC((unsigned char)((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress); - /* One more address cycle for higher density devices */ - if (this->chipsize & 0x0c000000) { - WriteDOC((unsigned char)((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress); - printk("high density\n"); - } - } - WriteDOC(0, docptr, Mplus_WritePipeTerm); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - /* deassert ALE */ - if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || - command == NAND_CMD_READOOB || command == NAND_CMD_READID) - WriteDOC(0, docptr, Mplus_FlashControl); - } - - /* - * program and erase have their own busy handlers - * status and sequential in needs no delay - */ - switch (command) { - - case NAND_CMD_PAGEPROG: - case NAND_CMD_ERASE1: - case NAND_CMD_ERASE2: - case NAND_CMD_SEQIN: - case NAND_CMD_STATUS: - return; - - case NAND_CMD_RESET: - if (this->dev_ready) - break; - udelay(this->chip_delay); - WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - while (!(this->read_byte(mtd) & 0x40)) ; - return; - - /* This applies to read commands */ - default: - /* - * If we don't have access to the busy pin, we apply the given - * command delay - */ - if (!this->dev_ready) { - udelay(this->chip_delay); - return; - } - } - - /* Apply this short delay always to ensure that we do wait tWB in - * any case on any machine. */ - ndelay(100); - /* wait until command is processed */ - while (!this->dev_ready(mtd)) ; -} - -static int doc200x_dev_ready(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - if (DoC_is_MillenniumPlus(doc)) { - /* 11.4.2 -- must NOP four times before checking FR/B# */ - DoC_Delay(doc, 4); - if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { - if (debug) - printk("not ready\n"); - return 0; - } - if (debug) - printk("was ready\n"); - return 1; - } else { - /* 11.4.2 -- must NOP four times before checking FR/B# */ - DoC_Delay(doc, 4); - if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { - if (debug) - printk("not ready\n"); - return 0; - } - /* 11.4.2 -- Must NOP twice if it's ready */ - DoC_Delay(doc, 2); - if (debug) - printk("was ready\n"); - return 1; - } -} - -static int doc200x_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) -{ - /* This is our last resort if we couldn't find or create a BBT. Just - pretend all blocks are good. */ - return 0; -} - -static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - /* Prime the ECC engine */ - switch (mode) { - case NAND_ECC_READ: - WriteDOC(DOC_ECC_RESET, docptr, ECCConf); - WriteDOC(DOC_ECC_EN, docptr, ECCConf); - break; - case NAND_ECC_WRITE: - WriteDOC(DOC_ECC_RESET, docptr, ECCConf); - WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf); - break; - } -} - -static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - /* Prime the ECC engine */ - switch (mode) { - case NAND_ECC_READ: - WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); - WriteDOC(DOC_ECC_EN, docptr, Mplus_ECCConf); - break; - case NAND_ECC_WRITE: - WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); - WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, Mplus_ECCConf); - break; - } -} - -/* This code is only called on write */ -static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat, unsigned char *ecc_code) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - int emptymatch = 1; - - /* flush the pipeline */ - if (DoC_is_2000(doc)) { - WriteDOC(doc->CDSNControl & ~CDSN_CTRL_FLASH_IO, docptr, CDSNControl); - WriteDOC(0, docptr, 2k_CDSN_IO); - WriteDOC(0, docptr, 2k_CDSN_IO); - WriteDOC(0, docptr, 2k_CDSN_IO); - WriteDOC(doc->CDSNControl, docptr, CDSNControl); - } else if (DoC_is_MillenniumPlus(doc)) { - WriteDOC(0, docptr, Mplus_NOP); - WriteDOC(0, docptr, Mplus_NOP); - WriteDOC(0, docptr, Mplus_NOP); - } else { - WriteDOC(0, docptr, NOP); - WriteDOC(0, docptr, NOP); - WriteDOC(0, docptr, NOP); - } - - for (i = 0; i < 6; i++) { - if (DoC_is_MillenniumPlus(doc)) - ecc_code[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); - else - ecc_code[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); - if (ecc_code[i] != empty_write_ecc[i]) - emptymatch = 0; - } - if (DoC_is_MillenniumPlus(doc)) - WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); - else - WriteDOC(DOC_ECC_DIS, docptr, ECCConf); -#if 0 - /* If emptymatch=1, we might have an all-0xff data buffer. Check. */ - if (emptymatch) { - /* Note: this somewhat expensive test should not be triggered - often. It could be optimized away by examining the data in - the writebuf routine, and remembering the result. */ - for (i = 0; i < 512; i++) { - if (dat[i] == 0xff) - continue; - emptymatch = 0; - break; - } - } - /* If emptymatch still =1, we do have an all-0xff data buffer. - Return all-0xff ecc value instead of the computed one, so - it'll look just like a freshly-erased page. */ - if (emptymatch) - memset(ecc_code, 0xff, 6); -#endif - return 0; -} - -static int doc200x_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *isnull) -{ - int i, ret = 0; - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - uint8_t calc_ecc[6]; - volatile u_char dummy; - int emptymatch = 1; - - /* flush the pipeline */ - if (DoC_is_2000(doc)) { - dummy = ReadDOC(docptr, 2k_ECCStatus); - dummy = ReadDOC(docptr, 2k_ECCStatus); - dummy = ReadDOC(docptr, 2k_ECCStatus); - } else if (DoC_is_MillenniumPlus(doc)) { - dummy = ReadDOC(docptr, Mplus_ECCConf); - dummy = ReadDOC(docptr, Mplus_ECCConf); - dummy = ReadDOC(docptr, Mplus_ECCConf); - } else { - dummy = ReadDOC(docptr, ECCConf); - dummy = ReadDOC(docptr, ECCConf); - dummy = ReadDOC(docptr, ECCConf); - } - - /* Error occured ? */ - if (dummy & 0x80) { - for (i = 0; i < 6; i++) { - if (DoC_is_MillenniumPlus(doc)) - calc_ecc[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); - else - calc_ecc[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); - if (calc_ecc[i] != empty_read_syndrome[i]) - emptymatch = 0; - } - /* If emptymatch=1, the read syndrome is consistent with an - all-0xff data and stored ecc block. Check the stored ecc. */ - if (emptymatch) { - for (i = 0; i < 6; i++) { - if (read_ecc[i] == 0xff) - continue; - emptymatch = 0; - break; - } - } - /* If emptymatch still =1, check the data block. */ - if (emptymatch) { - /* Note: this somewhat expensive test should not be triggered - often. It could be optimized away by examining the data in - the readbuf routine, and remembering the result. */ - for (i = 0; i < 512; i++) { - if (dat[i] == 0xff) - continue; - emptymatch = 0; - break; - } - } - /* If emptymatch still =1, this is almost certainly a freshly- - erased block, in which case the ECC will not come out right. - We'll suppress the error and tell the caller everything's - OK. Because it is. */ - if (!emptymatch) - ret = doc_ecc_decode(rs_decoder, dat, calc_ecc); - if (ret > 0) - printk(KERN_ERR "doc200x_correct_data corrected %d errors\n", ret); - } - if (DoC_is_MillenniumPlus(doc)) - WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); - else - WriteDOC(DOC_ECC_DIS, docptr, ECCConf); - if (no_ecc_failures && mtd_is_eccerr(ret)) { - printk(KERN_ERR "suppressing ECC failure\n"); - ret = 0; - } - return ret; -} - -/*u_char mydatabuf[528]; */ - -/* The strange out-of-order .oobfree list below is a (possibly unneeded) - * attempt to retain compatibility. It used to read: - * .oobfree = { {8, 8} } - * Since that leaves two bytes unusable, it was changed. But the following - * scheme might affect existing jffs2 installs by moving the cleanmarker: - * .oobfree = { {6, 10} } - * jffs2 seems to handle the above gracefully, but the current scheme seems - * safer. The only problem with it is that any code that parses oobfree must - * be able to handle out-of-order segments. - */ -static struct nand_ecclayout doc200x_oobinfo = { - .eccbytes = 6, - .eccpos = {0, 1, 2, 3, 4, 5}, - .oobfree = {{8, 8}, {6, 2}} -}; - -/* Find the (I)NFTL Media Header, and optionally also the mirror media header. - On sucessful return, buf will contain a copy of the media header for - further processing. id is the string to scan for, and will presumably be - either "ANAND" or "BNAND". If findmirror=1, also look for the mirror media - header. The page #s of the found media headers are placed in mh0_page and - mh1_page in the DOC private structure. */ -static int __init find_media_headers(struct mtd_info *mtd, u_char *buf, const char *id, int findmirror) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - unsigned offs; - int ret; - size_t retlen; - - for (offs = 0; offs < mtd->size; offs += mtd->erasesize) { - ret = mtd_read(mtd, offs, mtd->writesize, &retlen, buf); - if (retlen != mtd->writesize) - continue; - if (ret) { - printk(KERN_WARNING "ECC error scanning DOC at 0x%x\n", offs); - } - if (memcmp(buf, id, 6)) - continue; - printk(KERN_INFO "Found DiskOnChip %s Media Header at 0x%x\n", id, offs); - if (doc->mh0_page == -1) { - doc->mh0_page = offs >> this->page_shift; - if (!findmirror) - return 1; - continue; - } - doc->mh1_page = offs >> this->page_shift; - return 2; - } - if (doc->mh0_page == -1) { - printk(KERN_WARNING "DiskOnChip %s Media Header not found.\n", id); - return 0; - } - /* Only one mediaheader was found. We want buf to contain a - mediaheader on return, so we'll have to re-read the one we found. */ - offs = doc->mh0_page << this->page_shift; - ret = mtd_read(mtd, offs, mtd->writesize, &retlen, buf); - if (retlen != mtd->writesize) { - /* Insanity. Give up. */ - printk(KERN_ERR "Read DiskOnChip Media Header once, but can't reread it???\n"); - return 0; - } - return 1; -} - -static inline int __init nftl_partscan(struct mtd_info *mtd, struct mtd_partition *parts) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - int ret = 0; - u_char *buf; - struct NFTLMediaHeader *mh; - const unsigned psize = 1 << this->page_shift; - int numparts = 0; - unsigned blocks, maxblocks; - int offs, numheaders; - - buf = kmalloc(mtd->writesize, GFP_KERNEL); - if (!buf) { - printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); - return 0; - } - if (!(numheaders = find_media_headers(mtd, buf, "ANAND", 1))) - goto out; - mh = (struct NFTLMediaHeader *)buf; - - le16_to_cpus(&mh->NumEraseUnits); - le16_to_cpus(&mh->FirstPhysicalEUN); - le32_to_cpus(&mh->FormattedSize); - - printk(KERN_INFO " DataOrgID = %s\n" - " NumEraseUnits = %d\n" - " FirstPhysicalEUN = %d\n" - " FormattedSize = %d\n" - " UnitSizeFactor = %d\n", - mh->DataOrgID, mh->NumEraseUnits, - mh->FirstPhysicalEUN, mh->FormattedSize, - mh->UnitSizeFactor); - - blocks = mtd->size >> this->phys_erase_shift; - maxblocks = min(32768U, mtd->erasesize - psize); - - if (mh->UnitSizeFactor == 0x00) { - /* Auto-determine UnitSizeFactor. The constraints are: - - There can be at most 32768 virtual blocks. - - There can be at most (virtual block size - page size) - virtual blocks (because MediaHeader+BBT must fit in 1). - */ - mh->UnitSizeFactor = 0xff; - while (blocks > maxblocks) { - blocks >>= 1; - maxblocks = min(32768U, (maxblocks << 1) + psize); - mh->UnitSizeFactor--; - } - printk(KERN_WARNING "UnitSizeFactor=0x00 detected. Correct value is assumed to be 0x%02x.\n", mh->UnitSizeFactor); - } - - /* NOTE: The lines below modify internal variables of the NAND and MTD - layers; variables with have already been configured by nand_scan. - Unfortunately, we didn't know before this point what these values - should be. Thus, this code is somewhat dependant on the exact - implementation of the NAND layer. */ - if (mh->UnitSizeFactor != 0xff) { - this->bbt_erase_shift += (0xff - mh->UnitSizeFactor); - mtd->erasesize <<= (0xff - mh->UnitSizeFactor); - printk(KERN_INFO "Setting virtual erase size to %d\n", mtd->erasesize); - blocks = mtd->size >> this->bbt_erase_shift; - maxblocks = min(32768U, mtd->erasesize - psize); - } - - if (blocks > maxblocks) { - printk(KERN_ERR "UnitSizeFactor of 0x%02x is inconsistent with device size. Aborting.\n", mh->UnitSizeFactor); - goto out; - } - - /* Skip past the media headers. */ - offs = max(doc->mh0_page, doc->mh1_page); - offs <<= this->page_shift; - offs += mtd->erasesize; - - if (show_firmware_partition == 1) { - parts[0].name = " DiskOnChip Firmware / Media Header partition"; - parts[0].offset = 0; - parts[0].size = offs; - numparts = 1; - } - - parts[numparts].name = " DiskOnChip BDTL partition"; - parts[numparts].offset = offs; - parts[numparts].size = (mh->NumEraseUnits - numheaders) << this->bbt_erase_shift; - - offs += parts[numparts].size; - numparts++; - - if (offs < mtd->size) { - parts[numparts].name = " DiskOnChip Remainder partition"; - parts[numparts].offset = offs; - parts[numparts].size = mtd->size - offs; - numparts++; - } - - ret = numparts; - out: - kfree(buf); - return ret; -} - -/* This is a stripped-down copy of the code in inftlmount.c */ -static inline int __init inftl_partscan(struct mtd_info *mtd, struct mtd_partition *parts) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - int ret = 0; - u_char *buf; - struct INFTLMediaHeader *mh; - struct INFTLPartition *ip; - int numparts = 0; - int blocks; - int vshift, lastvunit = 0; - int i; - int end = mtd->size; - - if (inftl_bbt_write) - end -= (INFTL_BBT_RESERVED_BLOCKS << this->phys_erase_shift); - - buf = kmalloc(mtd->writesize, GFP_KERNEL); - if (!buf) { - printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); - return 0; - } - - if (!find_media_headers(mtd, buf, "BNAND", 0)) - goto out; - doc->mh1_page = doc->mh0_page + (4096 >> this->page_shift); - mh = (struct INFTLMediaHeader *)buf; - - le32_to_cpus(&mh->NoOfBootImageBlocks); - le32_to_cpus(&mh->NoOfBinaryPartitions); - le32_to_cpus(&mh->NoOfBDTLPartitions); - le32_to_cpus(&mh->BlockMultiplierBits); - le32_to_cpus(&mh->FormatFlags); - le32_to_cpus(&mh->PercentUsed); - - printk(KERN_INFO " bootRecordID = %s\n" - " NoOfBootImageBlocks = %d\n" - " NoOfBinaryPartitions = %d\n" - " NoOfBDTLPartitions = %d\n" - " BlockMultiplerBits = %d\n" - " FormatFlgs = %d\n" - " OsakVersion = %d.%d.%d.%d\n" - " PercentUsed = %d\n", - mh->bootRecordID, mh->NoOfBootImageBlocks, - mh->NoOfBinaryPartitions, - mh->NoOfBDTLPartitions, - mh->BlockMultiplierBits, mh->FormatFlags, - ((unsigned char *) &mh->OsakVersion)[0] & 0xf, - ((unsigned char *) &mh->OsakVersion)[1] & 0xf, - ((unsigned char *) &mh->OsakVersion)[2] & 0xf, - ((unsigned char *) &mh->OsakVersion)[3] & 0xf, - mh->PercentUsed); - - vshift = this->phys_erase_shift + mh->BlockMultiplierBits; - - blocks = mtd->size >> vshift; - if (blocks > 32768) { - printk(KERN_ERR "BlockMultiplierBits=%d is inconsistent with device size. Aborting.\n", mh->BlockMultiplierBits); - goto out; - } - - blocks = doc->chips_per_floor << (this->chip_shift - this->phys_erase_shift); - if (inftl_bbt_write && (blocks > mtd->erasesize)) { - printk(KERN_ERR "Writeable BBTs spanning more than one erase block are not yet supported. FIX ME!\n"); - goto out; - } - - /* Scan the partitions */ - for (i = 0; (i < 4); i++) { - ip = &(mh->Partitions[i]); - le32_to_cpus(&ip->virtualUnits); - le32_to_cpus(&ip->firstUnit); - le32_to_cpus(&ip->lastUnit); - le32_to_cpus(&ip->flags); - le32_to_cpus(&ip->spareUnits); - le32_to_cpus(&ip->Reserved0); - - printk(KERN_INFO " PARTITION[%d] ->\n" - " virtualUnits = %d\n" - " firstUnit = %d\n" - " lastUnit = %d\n" - " flags = 0x%x\n" - " spareUnits = %d\n", - i, ip->virtualUnits, ip->firstUnit, - ip->lastUnit, ip->flags, - ip->spareUnits); - - if ((show_firmware_partition == 1) && - (i == 0) && (ip->firstUnit > 0)) { - parts[0].name = " DiskOnChip IPL / Media Header partition"; - parts[0].offset = 0; - parts[0].size = mtd->erasesize * ip->firstUnit; - numparts = 1; - } - - if (ip->flags & INFTL_BINARY) - parts[numparts].name = " DiskOnChip BDK partition"; - else - parts[numparts].name = " DiskOnChip BDTL partition"; - parts[numparts].offset = ip->firstUnit << vshift; - parts[numparts].size = (1 + ip->lastUnit - ip->firstUnit) << vshift; - numparts++; - if (ip->lastUnit > lastvunit) - lastvunit = ip->lastUnit; - if (ip->flags & INFTL_LAST) - break; - } - lastvunit++; - if ((lastvunit << vshift) < end) { - parts[numparts].name = " DiskOnChip Remainder partition"; - parts[numparts].offset = lastvunit << vshift; - parts[numparts].size = end - parts[numparts].offset; - numparts++; - } - ret = numparts; - out: - kfree(buf); - return ret; -} - -static int __init nftl_scan_bbt(struct mtd_info *mtd) -{ - int ret, numparts; - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - struct mtd_partition parts[2]; - - memset((char *)parts, 0, sizeof(parts)); - /* On NFTL, we have to find the media headers before we can read the - BBTs, since they're stored in the media header eraseblocks. */ - numparts = nftl_partscan(mtd, parts); - if (!numparts) - return -EIO; - this->bbt_td->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | - NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | - NAND_BBT_VERSION; - this->bbt_td->veroffs = 7; - this->bbt_td->pages[0] = doc->mh0_page + 1; - if (doc->mh1_page != -1) { - this->bbt_md->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | - NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | - NAND_BBT_VERSION; - this->bbt_md->veroffs = 7; - this->bbt_md->pages[0] = doc->mh1_page + 1; - } else { - this->bbt_md = NULL; - } - - /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. - At least as nand_bbt.c is currently written. */ - if ((ret = nand_scan_bbt(mtd, NULL))) - return ret; - add_mtd_device(mtd); -#ifdef CONFIG_MTD_PARTITIONS - if (!no_autopart) - add_mtd_partitions(mtd, parts, numparts); -#endif - return 0; -} - -static int __init inftl_scan_bbt(struct mtd_info *mtd) -{ - int ret, numparts; - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - struct mtd_partition parts[5]; - - if (this->numchips > doc->chips_per_floor) { - printk(KERN_ERR "Multi-floor INFTL devices not yet supported.\n"); - return -EIO; - } - - if (DoC_is_MillenniumPlus(doc)) { - this->bbt_td->options = NAND_BBT_2BIT | NAND_BBT_ABSPAGE; - if (inftl_bbt_write) - this->bbt_td->options |= NAND_BBT_WRITE; - this->bbt_td->pages[0] = 2; - this->bbt_md = NULL; - } else { - this->bbt_td->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | NAND_BBT_VERSION; - if (inftl_bbt_write) - this->bbt_td->options |= NAND_BBT_WRITE; - this->bbt_td->offs = 8; - this->bbt_td->len = 8; - this->bbt_td->veroffs = 7; - this->bbt_td->maxblocks = INFTL_BBT_RESERVED_BLOCKS; - this->bbt_td->reserved_block_code = 0x01; - this->bbt_td->pattern = "MSYS_BBT"; - - this->bbt_md->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | NAND_BBT_VERSION; - if (inftl_bbt_write) - this->bbt_md->options |= NAND_BBT_WRITE; - this->bbt_md->offs = 8; - this->bbt_md->len = 8; - this->bbt_md->veroffs = 7; - this->bbt_md->maxblocks = INFTL_BBT_RESERVED_BLOCKS; - this->bbt_md->reserved_block_code = 0x01; - this->bbt_md->pattern = "TBB_SYSM"; - } - - /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. - At least as nand_bbt.c is currently written. */ - if ((ret = nand_scan_bbt(mtd, NULL))) - return ret; - memset((char *)parts, 0, sizeof(parts)); - numparts = inftl_partscan(mtd, parts); - /* At least for now, require the INFTL Media Header. We could probably - do without it for non-INFTL use, since all it gives us is - autopartitioning, but I want to give it more thought. */ - if (!numparts) - return -EIO; - add_mtd_device(mtd); -#ifdef CONFIG_MTD_PARTITIONS - if (!no_autopart) - add_mtd_partitions(mtd, parts, numparts); -#endif - return 0; -} - -static inline int __init doc2000_init(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - - this->read_byte = doc2000_read_byte; - this->write_buf = doc2000_writebuf; - this->read_buf = doc2000_readbuf; - this->verify_buf = doc2000_verifybuf; - this->scan_bbt = nftl_scan_bbt; - - doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO; - doc2000_count_chips(mtd); - mtd->name = "DiskOnChip 2000 (NFTL Model)"; - return (4 * doc->chips_per_floor); -} - -static inline int __init doc2001_init(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - - this->read_byte = doc2001_read_byte; - this->write_buf = doc2001_writebuf; - this->read_buf = doc2001_readbuf; - this->verify_buf = doc2001_verifybuf; - - ReadDOC(doc->virtadr, ChipID); - ReadDOC(doc->virtadr, ChipID); - ReadDOC(doc->virtadr, ChipID); - if (ReadDOC(doc->virtadr, ChipID) != DOC_ChipID_DocMil) { - /* It's not a Millennium; it's one of the newer - DiskOnChip 2000 units with a similar ASIC. - Treat it like a Millennium, except that it - can have multiple chips. */ - doc2000_count_chips(mtd); - mtd->name = "DiskOnChip 2000 (INFTL Model)"; - this->scan_bbt = inftl_scan_bbt; - return (4 * doc->chips_per_floor); - } else { - /* Bog-standard Millennium */ - doc->chips_per_floor = 1; - mtd->name = "DiskOnChip Millennium"; - this->scan_bbt = nftl_scan_bbt; - return 1; - } -} - -static inline int __init doc2001plus_init(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - - this->read_byte = doc2001plus_read_byte; - this->write_buf = doc2001plus_writebuf; - this->read_buf = doc2001plus_readbuf; - this->verify_buf = doc2001plus_verifybuf; - this->scan_bbt = inftl_scan_bbt; - this->cmd_ctrl = NULL; - this->select_chip = doc2001plus_select_chip; - this->cmdfunc = doc2001plus_command; - this->ecc.hwctl = doc2001plus_enable_hwecc; - - doc->chips_per_floor = 1; - mtd->name = "DiskOnChip Millennium Plus"; - - return 1; -} - -static int __init doc_probe(unsigned long physadr) -{ - unsigned char ChipID; - struct mtd_info *mtd; - struct nand_chip *nand; - struct doc_priv *doc; - void __iomem *virtadr; - unsigned char save_control; - unsigned char tmp, tmpb, tmpc; - int reg, len, numchips; - int ret = 0; - - virtadr = ioremap(physadr, DOC_IOREMAP_LEN); - if (!virtadr) { - printk(KERN_ERR "Diskonchip ioremap failed: 0x%x bytes at 0x%lx\n", DOC_IOREMAP_LEN, physadr); - return -EIO; - } - - /* It's not possible to cleanly detect the DiskOnChip - the - * bootup procedure will put the device into reset mode, and - * it's not possible to talk to it without actually writing - * to the DOCControl register. So we store the current contents - * of the DOCControl register's location, in case we later decide - * that it's not a DiskOnChip, and want to put it back how we - * found it. - */ - save_control = ReadDOC(virtadr, DOCControl); - - /* Reset the DiskOnChip ASIC */ - WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, virtadr, DOCControl); - WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, virtadr, DOCControl); - - /* Enable the DiskOnChip ASIC */ - WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, virtadr, DOCControl); - WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, virtadr, DOCControl); - - ChipID = ReadDOC(virtadr, ChipID); - - switch (ChipID) { - case DOC_ChipID_Doc2k: - reg = DoC_2k_ECCStatus; - break; - case DOC_ChipID_DocMil: - reg = DoC_ECCConf; - break; - case DOC_ChipID_DocMilPlus16: - case DOC_ChipID_DocMilPlus32: - case 0: - /* Possible Millennium Plus, need to do more checks */ - /* Possibly release from power down mode */ - for (tmp = 0; (tmp < 4); tmp++) - ReadDOC(virtadr, Mplus_Power); - - /* Reset the Millennium Plus ASIC */ - tmp = DOC_MODE_RESET | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | DOC_MODE_BDECT; - WriteDOC(tmp, virtadr, Mplus_DOCControl); - WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); - - mdelay(1); - /* Enable the Millennium Plus ASIC */ - tmp = DOC_MODE_NORMAL | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | DOC_MODE_BDECT; - WriteDOC(tmp, virtadr, Mplus_DOCControl); - WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); - mdelay(1); - - ChipID = ReadDOC(virtadr, ChipID); - - switch (ChipID) { - case DOC_ChipID_DocMilPlus16: - reg = DoC_Mplus_Toggle; - break; - case DOC_ChipID_DocMilPlus32: - printk(KERN_ERR "DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n"); - default: - ret = -ENODEV; - goto notfound; - } - break; - - default: - ret = -ENODEV; - goto notfound; - } - /* Check the TOGGLE bit in the ECC register */ - tmp = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; - tmpb = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; - tmpc = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; - if ((tmp == tmpb) || (tmp != tmpc)) { - printk(KERN_WARNING "Possible DiskOnChip at 0x%lx failed TOGGLE test, dropping.\n", physadr); - ret = -ENODEV; - goto notfound; - } - - for (mtd = doclist; mtd; mtd = doc->nextdoc) { - unsigned char oldval; - unsigned char newval; - nand = mtd->priv; - doc = nand->priv; - /* Use the alias resolution register to determine if this is - in fact the same DOC aliased to a new address. If writes - to one chip's alias resolution register change the value on - the other chip, they're the same chip. */ - if (ChipID == DOC_ChipID_DocMilPlus16) { - oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); - newval = ReadDOC(virtadr, Mplus_AliasResolution); - } else { - oldval = ReadDOC(doc->virtadr, AliasResolution); - newval = ReadDOC(virtadr, AliasResolution); - } - if (oldval != newval) - continue; - if (ChipID == DOC_ChipID_DocMilPlus16) { - WriteDOC(~newval, virtadr, Mplus_AliasResolution); - oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); - WriteDOC(newval, virtadr, Mplus_AliasResolution); /* restore it */ - } else { - WriteDOC(~newval, virtadr, AliasResolution); - oldval = ReadDOC(doc->virtadr, AliasResolution); - WriteDOC(newval, virtadr, AliasResolution); /* restore it */ - } - newval = ~newval; - if (oldval == newval) { - printk(KERN_DEBUG "Found alias of DOC at 0x%lx to 0x%lx\n", doc->physadr, physadr); - goto notfound; - } - } - - printk(KERN_NOTICE "DiskOnChip found at 0x%lx\n", physadr); - - len = sizeof(struct mtd_info) + - sizeof(struct nand_chip) + sizeof(struct doc_priv) + (2 * sizeof(struct nand_bbt_descr)); - mtd = kzalloc(len, GFP_KERNEL); - if (!mtd) { - printk(KERN_ERR "DiskOnChip kmalloc (%d bytes) failed!\n", len); - ret = -ENOMEM; - goto fail; - } - - nand = (struct nand_chip *) (mtd + 1); - doc = (struct doc_priv *) (nand + 1); - nand->bbt_td = (struct nand_bbt_descr *) (doc + 1); - nand->bbt_md = nand->bbt_td + 1; - - mtd->priv = nand; - mtd->owner = THIS_MODULE; - - nand->priv = doc; - nand->select_chip = doc200x_select_chip; - nand->cmd_ctrl = doc200x_hwcontrol; - nand->dev_ready = doc200x_dev_ready; - nand->waitfunc = doc200x_wait; - nand->block_bad = doc200x_block_bad; - nand->ecc.hwctl = doc200x_enable_hwecc; - nand->ecc.calculate = doc200x_calculate_ecc; - nand->ecc.correct = doc200x_correct_data; - - nand->ecc.layout = &doc200x_oobinfo; - nand->ecc.mode = NAND_ECC_HW_SYNDROME; - nand->ecc.size = 512; - nand->ecc.bytes = 6; - nand->ecc.strength = 2; - nand->bbt_options = NAND_BBT_USE_FLASH; - - doc->physadr = physadr; - doc->virtadr = virtadr; - doc->ChipID = ChipID; - doc->curfloor = -1; - doc->curchip = -1; - doc->mh0_page = -1; - doc->mh1_page = -1; - doc->nextdoc = doclist; - - if (ChipID == DOC_ChipID_Doc2k) - numchips = doc2000_init(mtd); - else if (ChipID == DOC_ChipID_DocMilPlus16) - numchips = doc2001plus_init(mtd); - else - numchips = doc2001_init(mtd); - - if ((ret = nand_scan(mtd, numchips))) { - /* DBB note: i believe nand_release is necessary here, as - buffers may have been allocated in nand_base. Check with - Thomas. FIX ME! */ - /* nand_release will call del_mtd_device, but we haven't yet - added it. This is handled without incident by - del_mtd_device, as far as I can tell. */ - nand_release(mtd); - kfree(mtd); - goto fail; - } - - /* Success! */ - doclist = mtd; - return 0; - - notfound: - /* Put back the contents of the DOCControl register, in case it's not - actually a DiskOnChip. */ - WriteDOC(save_control, virtadr, DOCControl); - fail: - iounmap(virtadr); - return ret; -} - -static void release_nanddoc(void) -{ - struct mtd_info *mtd, *nextmtd; - struct nand_chip *nand; - struct doc_priv *doc; - - for (mtd = doclist; mtd; mtd = nextmtd) { - nand = mtd->priv; - doc = nand->priv; - - nextmtd = doc->nextdoc; - nand_release(mtd); - iounmap(doc->virtadr); - kfree(mtd); - } -} - -static int __init init_nanddoc(void) -{ - int i, ret = 0; - - /* We could create the decoder on demand, if memory is a concern. - * This way we have it handy, if an error happens - * - * Symbolsize is 10 (bits) - * Primitve polynomial is x^10+x^3+1 - * first consecutive root is 510 - * primitve element to generate roots = 1 - * generator polinomial degree = 4 - */ - rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS); - if (!rs_decoder) { - printk(KERN_ERR "DiskOnChip: Could not create a RS decoder\n"); - return -ENOMEM; - } - - if (doc_config_location) { - printk(KERN_INFO "Using configured DiskOnChip probe address 0x%lx\n", doc_config_location); - ret = doc_probe(doc_config_location); - if (ret < 0) - goto outerr; - } else { - for (i = 0; (doc_locations[i] != 0xffffffff); i++) { - doc_probe(doc_locations[i]); - } - } - /* No banner message any more. Print a message if no DiskOnChip - found, so the user knows we at least tried. */ - if (!doclist) { - printk(KERN_INFO "No valid DiskOnChip devices found\n"); - ret = -ENODEV; - goto outerr; - } - return 0; - outerr: - free_rs(rs_decoder); - return ret; -} - -static void __exit cleanup_nanddoc(void) -{ - /* Cleanup the nand/DoC resources */ - release_nanddoc(); - - /* Free the reed solomon resources */ - if (rs_decoder) { - free_rs(rs_decoder); - } -} - -module_init(init_nanddoc); -module_exit(cleanup_nanddoc); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("David Woodhouse "); -MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n"); diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 795209788b..3372b64212 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -37,7 +37,6 @@ #define MAX_BANKS 8 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ -#define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */ #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) @@ -199,7 +198,8 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) struct fsl_elbc_mtd *priv = chip->priv; struct fsl_elbc_ctrl *ctrl = priv->ctrl; fsl_lbc_t *lbc = ctrl->regs; - long long end_tick; + u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; + u32 time_start; u32 ltesr; /* Setup the FMR[OP] to execute without write protection */ @@ -218,10 +218,10 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) out_be32(&lbc->lsor, priv->bank); /* wait for FCM complete flag or timeout */ - end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks(); + time_start = get_timer(0); ltesr = 0; - while (end_tick > get_ticks()) { + while (get_timer(time_start) < timeo) { ltesr = in_be32(&lbc->ltesr); if (ltesr & LTESR_CC) break; @@ -561,6 +561,7 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) len, avail); } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) /* * Verify buffer against the FCM Controller Data Buffer */ @@ -593,6 +594,7 @@ static int fsl_elbc_verify_buf(struct mtd_info *mtd, ctrl->index += len; return i == len && ctrl->status == LTESR_CC ? 0 : -EIO; } +#endif /* This function is called after Program and Erase Operations to * check for success or failure. @@ -725,7 +727,9 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) nand->read_byte = fsl_elbc_read_byte; nand->write_buf = fsl_elbc_write_buf; nand->read_buf = fsl_elbc_read_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) nand->verify_buf = fsl_elbc_verify_buf; +#endif nand->select_chip = fsl_elbc_select_chip; nand->cmdfunc = fsl_elbc_cmdfunc; nand->waitfunc = fsl_elbc_wait; @@ -759,8 +763,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) nand->ecc.steps = 1; nand->ecc.strength = 1; } else { - /* otherwise fall back to default software ECC */ + /* otherwise fall back to software ECC */ +#if defined(CONFIG_NAND_ECC_BCH) + nand->ecc.mode = NAND_ECC_SOFT_BCH; +#else nand->ecc.mode = NAND_ECC_SOFT; +#endif } ret = nand_scan_ident(mtd, 1, NULL); diff --git a/drivers/mtd/nand/fsl_elbc_spl.c b/drivers/mtd/nand/fsl_elbc_spl.c index 7e5599ac63..29521359a5 100644 --- a/drivers/mtd/nand/fsl_elbc_spl.c +++ b/drivers/mtd/nand/fsl_elbc_spl.c @@ -34,7 +34,11 @@ static void nand_wait(void) } } +#ifdef CONFIG_TPL_BUILD +int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) +#else static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) +#endif { fsl_lbc_t *regs = LBC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; @@ -55,20 +59,20 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) if (large) { fmr |= FMR_ECCM; out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | - (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); + (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); out_be32(®s->fir, - (FIR_OP_CW0 << FIR_OP0_SHIFT) | - (FIR_OP_CA << FIR_OP1_SHIFT) | - (FIR_OP_PA << FIR_OP2_SHIFT) | - (FIR_OP_CW1 << FIR_OP3_SHIFT) | - (FIR_OP_RBW << FIR_OP4_SHIFT)); + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT)); } else { out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); out_be32(®s->fir, - (FIR_OP_CW0 << FIR_OP0_SHIFT) | - (FIR_OP_CA << FIR_OP1_SHIFT) | - (FIR_OP_PA << FIR_OP2_SHIFT) | - (FIR_OP_RBW << FIR_OP3_SHIFT)); + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT)); } out_be32(®s->fbcr, 0); @@ -113,6 +117,15 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) return 0; } +/* + * Defines a static function nand_load_image() here, because non-static makes + * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes) + */ +#ifndef CONFIG_TPL_BUILD +#define nand_spl_load_image(offs, uboot_size, vdst) \ + nand_load_image(offs, uboot_size, vdst) +#endif + /* * The main entry for NAND booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image @@ -124,17 +137,17 @@ void nand_boot(void) /* * Load U-Boot image from NAND into RAM */ - nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (void *)CONFIG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST - nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (void *)CONFIG_NAND_ENV_DST); + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (void *)CONFIG_NAND_ENV_DST); #ifdef CONFIG_ENV_OFFSET_REDUND - nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, - (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); #endif #endif diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 98a09c0641..b283eaea34 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -17,14 +17,15 @@ #include #include -#include +#include -#define FSL_IFC_V1_1_0 0x01010000 -#define MAX_BANKS 4 +#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#endif + +#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ -#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC - NAND Machine */ struct fsl_ifc_ctrl; @@ -125,6 +126,69 @@ static struct nand_ecclayout oob_4096_ecc8 = { .oobfree = { {2, 6}, {136, 82} }, }; +/* 8192-byte page size with 4-bit ECC */ +static struct nand_ecclayout oob_8192_ecc4 = { + .eccbytes = 128, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + }, + .oobfree = { {2, 6}, {136, 208} }, +}; + +/* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */ +static struct nand_ecclayout oob_8192_ecc8 = { + .eccbytes = 256, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, + 152, 153, 154, 155, 156, 157, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, + 168, 169, 170, 171, 172, 173, 174, 175, + 176, 177, 178, 179, 180, 181, 182, 183, + 184, 185, 186, 187, 188, 189, 190, 191, + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215, + 216, 217, 218, 219, 220, 221, 222, 223, + 224, 225, 226, 227, 228, 229, 230, 231, + 232, 233, 234, 235, 236, 237, 238, 239, + 240, 241, 242, 243, 244, 245, 246, 247, + 248, 249, 250, 251, 252, 253, 254, 255, + 256, 257, 258, 259, 260, 261, 262, 263, + }, + .oobfree = { {2, 6}, {264, 80} }, +}; /* * Generic flash bbt descriptors @@ -167,8 +231,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) ctrl->page = page_addr; /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, page_addr); - out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); + ifc_out32(&ifc->ifc_nand.row0, page_addr); + ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); buf_num = page_addr & priv->bufnum_mask; @@ -226,28 +290,29 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) struct fsl_ifc_mtd *priv = chip->priv; struct fsl_ifc_ctrl *ctrl = priv->ctrl; struct fsl_ifc *ifc = ctrl->regs; - long long end_tick; - u32 eccstat[4]; + u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; + u32 time_start; + u32 eccstat[4] = {0}; int i; /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read/write seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ - end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); + time_start = get_timer(0); - while (end_tick > get_ticks()) { - ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + while (get_timer(time_start) < timeo) { + ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER) printf("%s: Flash Time Out Error\n", __func__); @@ -261,7 +326,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int sector_end = sector + chip->ecc.steps - 1; for (i = sector / 4; i <= sector_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = sector; i <= sector_end; i++) { errors = check_read_ecc(mtd, ctrl, eccstat, i); @@ -301,30 +366,30 @@ static void fsl_ifc_do_read(struct nand_chip *chip, /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ if (mtd->writesize > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); if (oob) - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); else - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } } @@ -345,7 +410,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, switch (command) { /* READ0 read the entire buffer to use hardware ECC. */ case NAND_CMD_READ0: { - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); set_addr(mtd, 0, page_addr, 0); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -361,7 +426,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* READOOB reads only the OOB because no ECC is performed. */ case NAND_CMD_READOOB: - out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); set_addr(mtd, column, page_addr, 1); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -378,19 +443,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, if (command == NAND_CMD_PARAM) timing = IFC_FIR_OP_RBCD; - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (timing << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - command << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, column); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (timing << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + command << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, column); /* * although currently it's 8 bytes for READID, we always read * the maximum 256 bytes(for PARAM) */ - out_be32(&ifc->ifc_nand.nand_fbcr, 256); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 256); ctrl->read_bytes = 256; set_addr(mtd, 0, 0, 0); @@ -405,16 +470,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* ERASE2 uses the block and page address from ERASE1 */ case NAND_CMD_ERASE2: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); ctrl->read_bytes = 0; fsl_ifc_run_command(mtd); return; @@ -428,29 +493,41 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, if (mtd->writesize > 512) { nand_fcr0 = (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT); - - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0); + (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | + (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); + + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_WBCD << + IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_RDSTAT << + IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); } else { nand_fcr0 = ((NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT) | (NAND_CMD_SEQIN << - IFC_NAND_FCR0_CMD2_SHIFT)); - - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT)); + IFC_NAND_FCR0_CMD2_SHIFT) | + (NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD3_SHIFT)); + + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_RDSTAT << + IFC_NAND_FIR1_OP7_SHIFT) | + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); if (column >= mtd->writesize) nand_fcr0 |= @@ -465,7 +542,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, column -= mtd->writesize; ctrl->oob = 1; } - out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); + ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); set_addr(mtd, column, page_addr, ctrl->oob); return; } @@ -473,21 +550,21 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ case NAND_CMD_PAGEPROG: if (ctrl->oob) - out_be32(&ifc->ifc_nand.nand_fbcr, - ctrl->index - ctrl->column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, + ctrl->index - ctrl->column); else - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); fsl_ifc_run_command(mtd); return; case NAND_CMD_STATUS: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -498,10 +575,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, return; case NAND_CMD_RESET: - out_be32(&ifc->ifc_nand.nand_fir0, - IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); fsl_ifc_run_command(mtd); return; @@ -573,8 +650,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) * next byte. */ if (ctrl->index < ctrl->read_bytes) { - data = in_be16((uint16_t *)&ctrl-> - addr[ctrl->index]); + data = ifc_in16((uint16_t *)&ctrl-> + addr[ctrl->index]); ctrl->index += 2; return (uint8_t)data; } @@ -606,6 +683,7 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) __func__, len, avail); } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) /* * Verify buffer against the IFC Controller Data Buffer */ @@ -638,6 +716,7 @@ static int fsl_ifc_verify_buf(struct mtd_info *mtd, ctrl->index += len; return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO; } +#endif /* This function is called after Program and Erase Operations to * check for success or failure. @@ -653,12 +732,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) return NAND_STATUS_FAIL; /* Use READ_STATUS command, but wait for the device to be ready */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << - IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -667,7 +746,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) return NAND_STATUS_FAIL; - nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); + nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); /* Chip sometimes reporting write protect even when it's not */ nand_fsr = nand_fsr | NAND_STATUS_WP; @@ -710,76 +789,101 @@ static void fsl_ifc_ctrl_init(void) ifc_ctrl->regs = IFC_BASE_ADDR; /* clear event registers */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); - out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); /* Enable error and event for any detected errors */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, - IFC_NAND_EVTER_EN_OPC_EN | - IFC_NAND_EVTER_EN_PGRDCMPL_EN | - IFC_NAND_EVTER_EN_FTOER_EN | - IFC_NAND_EVTER_EN_WPER_EN); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, + IFC_NAND_EVTER_EN_OPC_EN | + IFC_NAND_EVTER_EN_PGRDCMPL_EN | + IFC_NAND_EVTER_EN_FTOER_EN | + IFC_NAND_EVTER_EN_WPER_EN); - out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); } static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) { } -static void fsl_ifc_sram_init(void) +static int fsl_ifc_sram_init(uint32_t ver) { struct fsl_ifc *ifc = ifc_ctrl->regs; uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0; - long long end_tick; + uint32_t ncfgr = 0; + u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; + u32 time_start; + + if (ver > FSL_IFC_V1_1_0) { + ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr); + ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN); + + /* wait for SRAM_INIT bit to be clear or timeout */ + time_start = get_timer(0); + while (get_timer(time_start) < timeo) { + ifc_ctrl->status = + ifc_in32(&ifc->ifc_nand.nand_evter_stat); + + if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN)) + return 0; + } + printf("fsl-ifc: Failed to Initialise SRAM\n"); + return 1; + } cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; /* Save CSOR and CSOR_ext */ - csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor); - csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor); + csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); /* chage PageSize 8K and SpareSize 1K*/ csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); /* READID */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, 0x0); - out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0); /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, 0x0); - out_be32(&ifc->ifc_nand.col0, 0x0); + ifc_out32(&ifc->ifc_nand.row0, 0x0); + ifc_out32(&ifc->ifc_nand.col0, 0x0); /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); - /* wait for NAND Machine complete flag or timeout */ - end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); + time_start = get_timer(0); - while (end_tick > get_ticks()) { - ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + while (get_timer(time_start) < timeo) { + ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); + if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) { + printf("fsl-ifc: Failed to Initialise SRAM\n"); + return 1; + } + + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); /* Restore CSOR and CSOR_ext */ - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); + + return 0; } static int fsl_ifc_chip_init(int devnum, u8 *addr) @@ -789,7 +893,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) struct fsl_ifc_mtd *priv; struct nand_ecclayout *layout; uint32_t cspr = 0, csor = 0, ver = 0; - int ret; + int ret = 0; if (!ifc_ctrl) { fsl_ifc_ctrl_init(); @@ -809,8 +913,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { phys_addr_t phys_addr = virt_to_phys(addr); - cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); - csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); + cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) { @@ -836,7 +940,9 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) nand->write_buf = fsl_ifc_write_buf; nand->read_buf = fsl_ifc_read_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) nand->verify_buf = fsl_ifc_verify_buf; +#endif nand->select_chip = fsl_ifc_select_chip; nand->cmdfunc = fsl_ifc_cmdfunc; nand->waitfunc = fsl_ifc_wait; @@ -902,6 +1008,21 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) priv->bufnum_mask = 1; break; + case CSOR_NAND_PGS_8K: + if ((csor & CSOR_NAND_ECC_MODE_MASK) == + CSOR_NAND_ECC_MODE_4) { + layout = &oob_8192_ecc4; + nand->ecc.strength = 4; + } else { + layout = &oob_8192_ecc8; + nand->ecc.strength = 8; + nand->ecc.bytes = 16; + } + + priv->bufnum_mask = 0; + break; + + default: printf("ifc nand: bad csor %#x: bad page size\n", csor); return -ENODEV; @@ -915,9 +1036,14 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) nand->ecc.mode = NAND_ECC_SOFT; } - ver = in_be32(&ifc_ctrl->regs->ifc_rev); - if (ver == FSL_IFC_V1_1_0) - fsl_ifc_sram_init(); + ver = ifc_in32(&ifc_ctrl->regs->ifc_rev); + if (ver >= FSL_IFC_V1_1_0) + ret = fsl_ifc_sram_init(ver); + if (ret) + return ret; + + if (ver >= FSL_IFC_V2_0_0) + priv->bufnum_mask = (priv->bufnum_mask * 2) + 1; ret = nand_scan_ident(mtd, 1, NULL); if (ret) diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d4622653fa..fb827c5e74 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include static inline int is_blank(uchar *addr, int page_size) @@ -60,7 +60,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) bufnum_end = bufnum + bufperpage - 1; do { - status = in_be32(&ifc->ifc_nand.nand_evter_stat); + status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); } while (!(status & IFC_NAND_EVTER_STAT_OPC)); if (status & IFC_NAND_EVTER_STAT_FTOER) { @@ -70,14 +70,14 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) } for (i = bufnum / 4; i <= bufnum_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = bufnum; i <= bufnum_end; i++) { if (check_read_ecc(buf, eccstat, i, page_size)) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, status); } static inline int bad_block(uchar *marker, int port_size) @@ -88,7 +88,7 @@ static inline int bad_block(uchar *marker, int port_size) return __raw_readw((u16 *)marker) != 0xffff; } -static void nand_load(unsigned int offs, int uboot_size, uchar *dst) +int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) { struct fsl_ifc *ifc = IFC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; @@ -97,7 +97,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) int pages_per_blk; int blk_size; int bad_marker = 0; - int bufnum_mask, bufnum; + int bufnum_mask, bufnum, ver = 0; int csor, cspr; int pos = 0; @@ -105,6 +105,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) int sram_addr; int pg_no; + uchar *dst = vdst; /* Get NAND Flash configuration */ csor = CONFIG_SYS_NAND_CSOR; @@ -112,10 +113,13 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; - if (csor & CSOR_NAND_PGS_4K) { + if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) { + page_size = 8192; + bufnum_mask = 0x0; + } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) { page_size = 4096; bufnum_mask = 0x1; - } else if (csor & CSOR_NAND_PGS_2K) { + } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) { page_size = 2048; bufnum_mask = 0x3; } else { @@ -126,44 +130,48 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) bad_marker = 5; } + ver = ifc_in32(&ifc->ifc_rev); + if (ver >= FSL_IFC_V2_0_0) + bufnum_mask = (bufnum_mask * 2) + 1; + pages_per_blk = 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT); blk_size = pages_per_blk * page_size; /* Open Full SRAM mapping for spare are access */ - out_be32(&ifc->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc->ifc_nand.ncfgr, 0x0); /* Clear Boot events */ - out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); /* Program FIR/FCR for Large/Small page */ if (page_size > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } /* Program FBCR = 0 for full page read */ - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); /* Read and copy u-boot on SDRAM from NAND device, In parallel * check for Bad block if found skip it and read continue to @@ -176,11 +184,11 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) bufnum = pg_no & bufnum_mask; sram_addr = bufnum * page_size * 2; - out_be32(&ifc->ifc_nand.row0, pg_no); - out_be32(&ifc->ifc_nand.col0, 0); + ifc_out32(&ifc->ifc_nand.row0, pg_no); + ifc_out32(&ifc->ifc_nand.col0, 0); /* start read */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for read to complete */ nand_wait(&buf[sram_addr], bufnum, page_size); @@ -205,6 +213,8 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) offs += page_size; } while ((offs & (blk_size - 1)) && (pos < uboot_size)); } + + return 0; } /* @@ -218,16 +228,17 @@ void nand_boot(void) /* * Load U-Boot image from NAND into RAM */ - nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST - nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST); + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST); #ifdef CONFIG_ENV_OFFSET_REDUND - nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); #endif #endif /* @@ -243,3 +254,13 @@ void nand_boot(void) uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } + +#ifndef CONFIG_SPL_NAND_INIT +void nand_init(void) +{ +} + +void nand_deselect(void) +{ +} +#endif diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index a0fe1e09ec..65ce98ad5e 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -112,10 +112,10 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar); /* - * Some boards/chips needs this. At least the MPC8360E-RDK - * needs it. Probably weird chip, because I don't see any - * need for this on MPC8555E + Samsung K9F1G08U0A. Usually - * here are 0-2 unexpected busy states per block read. + * Some boards/chips needs this. At least the MPC8360E-RDK + * needs it. Probably weird chip, because I don't see any + * need for this on MPC8555E + Samsung K9F1G08U0A. Usually + * here are 0-2 unexpected busy states per block read. */ if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) fun_wait(fun); @@ -153,6 +153,7 @@ static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) buf[i] = in_8(chip->IO_ADDR_R); } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) static int upm_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; @@ -165,6 +166,7 @@ static int upm_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) return 0; } +#endif static int nand_dev_ready(struct mtd_info *mtd) { @@ -191,7 +193,9 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) chip->read_byte = upm_nand_read_byte; chip->read_buf = upm_nand_read_buf; chip->write_buf = upm_nand_write_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) chip->verify_buf = upm_nand_verify_buf; +#endif if (fun->dev_ready) chip->dev_ready = nand_dev_ready; diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index 72687a1da3..4fc34d6b9f 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include /* NAND Flash Soc registers */ @@ -58,6 +58,9 @@ void kw_nand_select_chip(struct mtd_info *mtd, int chip) int board_nand_init(struct nand_chip *nand) { nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; +#if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE) + nand->options |= NAND_NO_SUBPAGE_WRITE; +#endif #if defined(CONFIG_NAND_ECC_BCH) nand->ecc.mode = NAND_ECC_SOFT_BCH; #else diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index d0f3a35329..7233bfc127 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -459,6 +459,7 @@ static void mpc5121_nfc_write_buf(struct mtd_info *mtd, mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1); } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) /* Compare buffer with NAND flash */ static int mpc5121_nfc_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) @@ -479,6 +480,7 @@ static int mpc5121_nfc_verify_buf(struct mtd_info *mtd, return 0; } +#endif /* Read byte from NFC buffers */ static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd) @@ -607,7 +609,9 @@ int board_nand_init(struct nand_chip *chip) chip->read_word = mpc5121_nfc_read_word; chip->read_buf = mpc5121_nfc_read_buf; chip->write_buf = mpc5121_nfc_write_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) chip->verify_buf = mpc5121_nfc_verify_buf; +#endif chip->select_chip = mpc5121_nfc_select_chip; chip->bbt_options = NAND_BBT_USE_FLASH; chip->ecc.mode = NAND_ECC_SOFT; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index f4528f20bd..a232e71ed9 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -3,21 +3,7 @@ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de * Copyright 2009 Ilya Yanok, * - * Copyright 2012 Lothar Waßmann - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -25,15 +11,15 @@ #include #include #include -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \ - defined(CONFIG_MX51) || defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX35) || \ + defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) #include #endif static struct mxc_nand_host mxc_host; static struct mxc_nand_host *host = &mxc_host; -#ifdef CONFIG_MX27 +#ifdef CONFIG_SOC_MX27 static int is_16bit_nand(void) { struct system_control_regs *sc_regs = @@ -44,7 +30,7 @@ static int is_16bit_nand(void) else return 0; } -#elif defined(CONFIG_MX31) +#elif defined(CONFIG_SOC_MX31) static int is_16bit_nand(void) { struct clock_control_regs *sc_regs = @@ -55,7 +41,7 @@ static int is_16bit_nand(void) else return 0; } -#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) +#elif defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX35) static int is_16bit_nand(void) { struct ccm_regs *ccm = @@ -66,7 +52,7 @@ static int is_16bit_nand(void) else return 0; } -#elif defined(CONFIG_MX51) +#elif defined(CONFIG_SOC_MX51) static int is_16bit_nand(void) { struct src *src = (struct src *)SRC_BASE_ADDR; @@ -76,7 +62,7 @@ static int is_16bit_nand(void) else return 0; } -#elif defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX53) /* BOOT_CFG[1..3][0..7] */ #define SRC_BOOT_CFG(m, n) (1 << ((m) * 8 + (n))) static int is_16bit_nand(void) @@ -104,19 +90,19 @@ static int is_16bit_nand(void) #error CONFIG_MXC_NAND_REGS_BASE not defined #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX31) +#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX31) #define nfc_is_v1() 1 #define nfc_is_v21() 0 #define nfc_is_v3_2() 0 #define nfc_is_v3() nfc_is_v3_2() #define NFC_VERSION "V1" -#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) +#elif defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX35) #define nfc_is_v1() 0 #define nfc_is_v21() 1 #define nfc_is_v3_2() 0 #define nfc_is_v3() nfc_is_v3_2() #define NFC_VERSION "V2" -#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) #define nfc_is_v1() 0 #define nfc_is_v21() 0 #define nfc_is_v3_2() 1 @@ -677,6 +663,7 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) host->buf_start += n; } +#if defined(__UBOOT__) && defined(CONFIG_MTD_NAND_VERIFY_WRITE) /* Used by the upper layer to verify the data in NAND Flash * with the data in the buf. */ static int mxc_nand_verify_buf(struct mtd_info *mtd, @@ -684,6 +671,7 @@ static int mxc_nand_verify_buf(struct mtd_info *mtd, { return -EFAULT; } +#endif /* This function is used by upper layer for select and * deselect of the NAND chip */ @@ -883,7 +871,7 @@ static void preset_v3(struct mtd_info *mtd) } if (mtd->writesize) { -#if defined CONFIG_MX53 +#if defined CONFIG_SOC_MX53 config2 |= MX53_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6); #else config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6); @@ -1053,8 +1041,9 @@ static void mxc_nand_chip_init(int devno) this->read_word = mxc_nand_read_word; this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; +#if defined(__UBOOT__) && defined(CONFIG_MTD_NAND_VERIFY_WRITE) this->verify_buf = mxc_nand_verify_buf; - +#endif host->base = (void __iomem *)CONFIG_MXC_NAND_REGS_BASE; if (!host->base) { return; diff --git a/drivers/mtd/nand/mxc_nand.h b/drivers/mtd/nand/mxc_nand.h index a02d6e0a5a..40b689d8c6 100644 --- a/drivers/mtd/nand/mxc_nand.h +++ b/drivers/mtd/nand/mxc_nand.h @@ -25,17 +25,17 @@ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. * Also some of registers are moved and/or changed meaning as seen below. */ -#if defined(CONFIG_MX27) || defined(CONFIG_MX31) +#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX31) #define MXC_NFC_V1 #define is_mxc_nfc_1() 1 #define is_mxc_nfc_21() 0 #define is_mxc_nfc_32() 0 -#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) +#elif defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX35) #define MXC_NFC_V2_1 #define is_mxc_nfc_1() 0 #define is_mxc_nfc_21() 1 #define is_mxc_nfc_32() 0 -#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) +#elif defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) #define MXC_NFC_V3 #define MXC_NFC_V3_2 #define is_mxc_nfc_1() 0 diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index bf368f8a08..08847fd8e2 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -31,7 +31,7 @@ #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 -#if defined(CONFIG_MX6) +#if defined(CONFIG_SOC_MX6) #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #else #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 @@ -275,8 +275,13 @@ static int mxs_nand_gpmi_init(void) static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, uint32_t page_oob_size) { - if (page_data_size == 2048) - return 8; + if (page_data_size == 2048) { + if (page_oob_size == 64) + return 8; + + if (page_oob_size == 112) + return 14; + } if (page_data_size == 4096) { if (page_oob_size == 128) @@ -284,6 +289,9 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, if (page_oob_size == 218) return 16; + + if (page_oob_size == 224) + return 16; } return 0; @@ -581,7 +589,7 @@ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) length; mxs_dma_desc_append(channel, d); -#ifndef CONFIG_MX6Q +#ifndef CONFIG_SOC_MX6Q /* * A DMA descriptor that waits for the command to end and the chip to * become ready. @@ -1296,12 +1304,11 @@ int board_nand_init(struct nand_chip *nand) struct mxs_nand_info *nand_info; int err; - nand_info = malloc(sizeof(struct mxs_nand_info)); + nand_info = calloc(1, sizeof(struct mxs_nand_info)); if (!nand_info) { printf("MXS NAND: Failed to allocate private data\n"); return -ENOMEM; } - memset(nand_info, 0, sizeof(struct mxs_nand_info)); err = mxs_nand_alloc_buffers(nand_info); if (err) diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c new file mode 100644 index 0000000000..0e7c364a22 --- /dev/null +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +static nand_info_t mtd; +static struct nand_chip nand_chip; + +static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + register struct nand_chip *chip = mtd->priv; + u32 timeo, time_start; + + /* write out the command to the device */ + chip->cmd_ctrl(mtd, command, NAND_CLE); + + /* Serially input address */ + if (column != -1) { + chip->cmd_ctrl(mtd, column, NAND_ALE); + chip->cmd_ctrl(mtd, column >> 8, NAND_ALE); + } + if (page_addr != -1) { + chip->cmd_ctrl(mtd, page_addr, NAND_ALE); + chip->cmd_ctrl(mtd, page_addr >> 8, NAND_ALE); + /* One more address cycle for devices > 128MiB */ + if (chip->chipsize > (128 << 20)) + chip->cmd_ctrl(mtd, page_addr >> 16, NAND_ALE); + } + chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); + + if (command == NAND_CMD_READ0) { + chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE); + chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); + } + + /* wait for nand ready */ + ndelay(100); + timeo = (CONFIG_SYS_HZ * 20) / 1000; + time_start = get_timer(0); + while (get_timer(time_start) < timeo) { + if (chip->dev_ready(mtd)) + break; + } +} + +static int mxs_flash_ident(struct mtd_info *mtd) +{ + register struct nand_chip *chip = mtd->priv; + int i; + u8 mfg_id, dev_id; + u8 id_data[8]; + struct nand_onfi_params *p = &chip->onfi_params; + + /* Reset the chip */ + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Send the command for reading device ID */ + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + mfg_id = chip->read_byte(mtd); + dev_id = chip->read_byte(mtd); + + /* Try again to make sure */ + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + for (i = 0; i < 8; i++) + id_data[i] = chip->read_byte(mtd); + if (id_data[0] != mfg_id || id_data[1] != dev_id) { + printf("second ID read did not match"); + return -1; + } + debug("0x%02x:0x%02x ", mfg_id, dev_id); + + /* read ONFI */ + chip->onfi_version = 0; + chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); + if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || + chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') { + return -2; + } + + /* we have ONFI, probe it */ + chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); + chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); + mtd->name = p->model; + mtd->writesize = le32_to_cpu(p->byte_per_page); + mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; + mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); + chip->chipsize = le32_to_cpu(p->blocks_per_lun); + chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; + /* Calculate the address shift from the page size */ + chip->page_shift = ffs(mtd->writesize) - 1; + chip->phys_erase_shift = ffs(mtd->erasesize) - 1; + /* Convert chipsize to number of pages per chip -1 */ + chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; + chip->badblockbits = 8; + + debug("erasesize=%d (>>%d)\n", mtd->erasesize, chip->phys_erase_shift); + debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift); + debug("oobsize=%d\n", mtd->oobsize); + debug("chipsize=%lld\n", chip->chipsize); + + return 0; +} + +static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page) +{ + register struct nand_chip *chip = mtd->priv; + int ret; + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); + ret = nand_chip.ecc.read_page(mtd, chip, buf, 1, page); + if (ret < 0) { + printf("read_page failed %d\n", ret); + return -1; + } + return 0; +} + +static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt) +{ + register struct nand_chip *chip = mtd->priv; + unsigned int block = offs >> chip->phys_erase_shift; + unsigned int page = offs >> chip->page_shift; + + debug("%s offs=0x%08x block:%d page:%d\n", __func__, (int)offs, block, + page); + chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); + memset(chip->oob_poi, 0, mtd->oobsize); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + return chip->oob_poi[0] != 0xff; +} + +/* setup mtd and nand structs and init mxs_nand driver */ +static int mxs_nand_init(void) +{ + /* return if already initalized */ + if (nand_chip.numchips) + return 0; + + /* init mxs nand driver */ + board_nand_init(&nand_chip); + mtd.priv = &nand_chip; + /* set mtd functions */ + nand_chip.cmdfunc = mxs_nand_command; + nand_chip.numchips = 1; + + /* identify flash device */ + puts("NAND : "); + if (mxs_flash_ident(&mtd)) { + printf("Failed to identify\n"); + return -1; + } + + /* allocate and initialize buffers */ + nand_chip.buffers = memalign(ARCH_DMA_MINALIGN, + sizeof(*nand_chip.buffers)); + nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize; + /* setup flash layout (does not scan as we override that) */ + mtd.size = nand_chip.chipsize; + nand_chip.scan_bbt(&mtd); + + printf("%llu MiB\n", (mtd.size / (1024 * 1024))); + return 0; +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) +{ + struct nand_chip *chip; + unsigned int page; + unsigned int nand_page_per_block; + unsigned int sz = 0; + + if (mxs_nand_init()) + return -ENODEV; + chip = mtd.priv; + page = offs >> chip->page_shift; + nand_page_per_block = mtd.erasesize / mtd.writesize; + + debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page); + + size = roundup(size, mtd.writesize); + while (sz < size) { + if (mxs_read_page_ecc(&mtd, buf, page) < 0) + return -1; + sz += mtd.writesize; + offs += mtd.writesize; + page++; + buf += mtd.writesize; + + /* + * Check if we have crossed a block boundary, and if so + * check for bad block. + */ + if (!(page % nand_page_per_block)) { + /* + * Yes, new block. See if this block is good. If not, + * loop until we find a good block. + */ + while (is_badblock(&mtd, offs, 1)) { + page = page + nand_page_per_block; + /* Check i we've reached the end of flash. */ + if (page >= mtd.size >> chip->page_shift) + return -ENOMEM; + } + } + } + + return 0; +} + +int nand_default_bbt(struct mtd_info *mtd) +{ + return 0; +} + +void nand_init(void) +{ +} + +void nand_deselect(void) +{ +} + diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index a2587b6d25..5aaea904c2 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -4,7 +4,6 @@ * Overview: * This is the generic MTD driver for NAND flash devices. It should be * capable of working with almost all NAND chips currently available. - * Basic support for AG-AND chips is provided. * * Additional technical information is available on * http://www.linux-mtd.infradead.org/doc/nand.html @@ -22,8 +21,6 @@ * Enable cached programming for 2k page size chips * Check, if mtd->ecctype should be set to MTD_ECC_HW * if we have HW ECC support. - * The AG-AND chips have nice features for speed improvement, - * which are not supported yet. Read / program 4 pages in one go. * BBT table is not serialized, has to be fixed * * This program is free software; you can redistribute it and/or modify @@ -32,10 +29,28 @@ * */ -#include - -#define ENOTSUPP 524 /* Operation is not supported */ +#ifndef __UBOOT__ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#else +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -44,11 +59,9 @@ #include #include #include - #ifdef CONFIG_MTD_PARTITIONS #include #endif - #include #include @@ -63,6 +76,9 @@ #define CONFIG_SYS_NAND_RESET_CNT 200000 #endif +static bool is_module_text_address(unsigned long addr) {return 0;} +#endif + /* Define default oob placement schemes for large and small page devices */ static struct nand_ecclayout nand_oob_8 = { .eccbytes = 3, @@ -107,13 +123,16 @@ static struct nand_ecclayout nand_oob_128 = { .length = 78} } }; -static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, - int new_state); +static int nand_get_device(struct mtd_info *mtd, int new_state); static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops); -static int nand_wait(struct mtd_info *mtd, struct nand_chip *this); +/* + * For devices which display every fart in the system on a separate LED. Is + * compiled away when LED support is disabled. + */ +DEFINE_LED_TRIGGER(nand_led_trigger); static int check_offs_len(struct mtd_info *mtd, loff_t ofs, uint64_t len) @@ -122,15 +141,14 @@ static int check_offs_len(struct mtd_info *mtd, int ret = 0; /* Start address must align on block boundary */ - if (ofs & ((1 << chip->phys_erase_shift) - 1)) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__); + if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { + pr_debug("%s: unaligned address\n", __func__); ret = -EINVAL; } /* Length must align on block boundary */ - if (len & ((1 << chip->phys_erase_shift) - 1)) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n", - __func__); + if (len & ((1ULL << chip->phys_erase_shift) - 1)) { + pr_debug("%s: length not block aligned\n", __func__); ret = -EINVAL; } @@ -141,30 +159,43 @@ static int check_offs_len(struct mtd_info *mtd, * nand_release_device - [GENERIC] release chip * @mtd: MTD device structure * - * Deselect, release chip lock and wake up anyone waiting on the device. + * Release chip lock and wake up anyone waiting on the device. */ static void nand_release_device(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; +#ifndef __UBOOT__ + /* Release the controller and the chip */ + spin_lock(&chip->controller->lock); + chip->controller->active = NULL; + chip->state = FL_READY; + wake_up(&chip->controller->wq); + spin_unlock(&chip->controller->lock); +#else /* De-select the NAND device */ chip->select_chip(mtd, -1); +#endif } /** * nand_read_byte - [DEFAULT] read one byte from the chip * @mtd: MTD device structure * - * Default read function for 8bit buswidth. + * Default read function for 8bit buswidth */ +#ifndef __UBOOT__ +static uint8_t nand_read_byte(struct mtd_info *mtd) +#else uint8_t nand_read_byte(struct mtd_info *mtd) +#endif { struct nand_chip *chip = mtd->priv; return readb(chip->IO_ADDR_R); } /** - * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip + * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip * @mtd: MTD device structure * @@ -212,6 +243,86 @@ static void nand_select_chip(struct mtd_info *mtd, int chipnr) } } +/** + * nand_write_byte - [DEFAULT] write single byte to chip + * @mtd: MTD device structure + * @byte: value to write + * + * Default function to write a byte to I/O[7:0] + */ +static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) +{ + struct nand_chip *chip = mtd->priv; + + chip->write_buf(mtd, &byte, 1); +} + +/** + * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 + * @mtd: MTD device structure + * @byte: value to write + * + * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. + */ +static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) +{ + struct nand_chip *chip = mtd->priv; + uint16_t word = byte; + + /* + * It's not entirely clear what should happen to I/O[15:8] when writing + * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: + * + * When the host supports a 16-bit bus width, only data is + * transferred at the 16-bit width. All address and command line + * transfers shall use only the lower 8-bits of the data bus. During + * command transfers, the host may place any value on the upper + * 8-bits of the data bus. During address transfers, the host shall + * set the upper 8-bits of the data bus to 00h. + * + * One user of the write_byte callback is nand_onfi_set_features. The + * four parameters are specified to be written to I/O[7:0], but this is + * neither an address nor a command transfer. Let's assume a 0 on the + * upper I/O lines is OK. + */ + chip->write_buf(mtd, (uint8_t *)&word, 2); +} + +#if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN) +static void iowrite8_rep(void *addr, const uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + writeb(buf[i], addr); +} +static void ioread8_rep(void *addr, uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + buf[i] = readb(addr); +} + +static void ioread16_rep(void *addr, void *buf, int len) +{ + int i; + u16 *p = (u16 *) buf; + + for (i = 0; i < len; i++) + p[i] = readw(addr); +} + +static void iowrite16_rep(void *addr, void *buf, int len) +{ + int i; + u16 *p = (u16 *) buf; + + for (i = 0; i < len; i++) + writew(p[i], addr); +} +#endif + /** * nand_write_buf - [DEFAULT] write buffer to chip * @mtd: MTD device structure @@ -220,13 +331,15 @@ static void nand_select_chip(struct mtd_info *mtd, int chipnr) * * Default write function for 8bit buswidth. */ +#ifndef __UBOOT__ +static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +#else void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +#endif { - int i; struct nand_chip *chip = mtd->priv; - for (i = 0; i < len; i++) - writeb(buf[i], chip->IO_ADDR_W); + iowrite8_rep(chip->IO_ADDR_W, buf, len); } /** @@ -237,15 +350,19 @@ void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) * * Default read function for 8bit buswidth. */ +#ifndef __UBOOT__ +static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +#else void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +#endif { - int i; struct nand_chip *chip = mtd->priv; - for (i = 0; i < len; i++) - buf[i] = readb(chip->IO_ADDR_R); + ioread8_rep(chip->IO_ADDR_R, buf, len); } +#ifdef __UBOOT__ +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) /** * nand_verify_buf - [DEFAULT] Verify chip data against buffer * @mtd: MTD device structure @@ -266,14 +383,14 @@ static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) } /** - * nand_write_buf16 - [DEFAULT] write buffer to chip + * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer * @mtd: MTD device structure - * @buf: data buffer - * @len: number of bytes to write + * @buf: buffer containing the data to compare + * @len: number of bytes to compare * - * Default write function for 16bit buswidth. + * Default verify function for 16bit buswidth. */ -void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) +static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) { int i; struct nand_chip *chip = mtd->priv; @@ -281,49 +398,52 @@ void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) len >>= 1; for (i = 0; i < len; i++) - writew(p[i], chip->IO_ADDR_W); + if (p[i] != readw(chip->IO_ADDR_R)) + return -EFAULT; + return 0; } +#endif +#endif /** - * nand_read_buf16 - [DEFAULT] read chip data into buffer + * nand_write_buf16 - [DEFAULT] write buffer to chip * @mtd: MTD device structure - * @buf: buffer to store date - * @len: number of bytes to read + * @buf: data buffer + * @len: number of bytes to write * - * Default read function for 16bit buswidth. + * Default write function for 16bit buswidth. */ -void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) +#ifndef __UBOOT__ +static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) +#else +void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) +#endif { - int i; struct nand_chip *chip = mtd->priv; u16 *p = (u16 *) buf; - len >>= 1; - for (i = 0; i < len; i++) - p[i] = readw(chip->IO_ADDR_R); + iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); } /** - * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer + * nand_read_buf16 - [DEFAULT] read chip data into buffer * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare + * @buf: buffer to store date + * @len: number of bytes to read * - * Default verify function for 16bit buswidth. + * Default read function for 16bit buswidth. */ -static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) +#ifndef __UBOOT__ +static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) +#else +void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) +#endif { - int i; struct nand_chip *chip = mtd->priv; u16 *p = (u16 *) buf; - len >>= 1; - - for (i = 0; i < len; i++) - if (p[i] != readw(chip->IO_ADDR_R)) - return -EFAULT; - return 0; + ioread16_rep(chip->IO_ADDR_R, p, len >> 1); } /** @@ -348,7 +468,7 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) if (getchip) { chipnr = (int)(ofs >> chip->chip_shift); - nand_get_device(chip, mtd, FL_READING); + nand_get_device(mtd, FL_READING); /* Select the NAND device */ chip->select_chip(mtd, chipnr); @@ -378,87 +498,97 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) i++; } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); - if (getchip) + if (getchip) { + chip->select_chip(mtd, -1); nand_release_device(mtd); + } return res; } /** - * nand_default_block_markbad - [DEFAULT] mark a block bad + * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker * @mtd: MTD device structure * @ofs: offset from device start * * This is the default implementation, which can be overridden by a hardware - * specific driver. We try operations in the following order, according to our - * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH): + * specific driver. It provides the details for writing a bad block marker to a + * block. + */ +static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + struct nand_chip *chip = mtd->priv; + struct mtd_oob_ops ops; + uint8_t buf[2] = { 0, 0 }; + int ret = 0, res, i = 0; + + ops.datbuf = NULL; + ops.oobbuf = buf; + ops.ooboffs = chip->badblockpos; + if (chip->options & NAND_BUSWIDTH_16) { + ops.ooboffs &= ~0x01; + ops.len = ops.ooblen = 2; + } else { + ops.len = ops.ooblen = 1; + } + ops.mode = MTD_OPS_PLACE_OOB; + + /* Write to first/last page(s) if necessary */ + if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) + ofs += mtd->erasesize - mtd->writesize; + do { + res = nand_do_write_oob(mtd, ofs, &ops); + if (!ret) + ret = res; + + i++; + ofs += mtd->writesize; + } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); + + return ret; +} + +/** + * nand_block_markbad_lowlevel - mark a block bad + * @mtd: MTD device structure + * @ofs: offset from device start + * + * This function performs the generic NAND bad block marking steps (i.e., bad + * block table(s) and/or marker(s)). We only allow the hardware driver to + * specify how to write bad block markers to OOB (chip->block_markbad). + * + * We try operations in the following order: * (1) erase the affected block, to allow OOB marker to be written cleanly - * (2) update in-memory BBT - * (3) write bad block marker to OOB area of affected block - * (4) update flash-based BBT - * Note that we retain the first error encountered in (3) or (4), finish the + * (2) write bad block marker to OOB area of affected block (unless flag + * NAND_BBT_NO_OOB_BBM is present) + * (3) update the BBT + * Note that we retain the first error encountered in (2) or (3), finish the * procedures, and dump the error in the end. */ -static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) +static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd->priv; - uint8_t buf[2] = { 0, 0 }; - int block, res, ret = 0, i = 0; - int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM); + int res, ret = 0; - if (write_oob) { + if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { struct erase_info einfo; /* Attempt erase before marking OOB */ memset(&einfo, 0, sizeof(einfo)); einfo.mtd = mtd; einfo.addr = ofs; - einfo.len = 1 << chip->phys_erase_shift; + einfo.len = 1ULL << chip->phys_erase_shift; nand_erase_nand(mtd, &einfo, 0); - } - - /* Get block number */ - block = (int)(ofs >> chip->bbt_erase_shift); - /* Mark block bad in memory-based BBT */ - if (chip->bbt) - chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); - - /* Write bad block marker to OOB */ - if (write_oob) { - struct mtd_oob_ops ops; - loff_t wr_ofs = ofs; - - nand_get_device(chip, mtd, FL_WRITING); - - ops.datbuf = NULL; - ops.oobbuf = buf; - ops.ooboffs = chip->badblockpos; - if (chip->options & NAND_BUSWIDTH_16) { - ops.ooboffs &= ~0x01; - ops.len = ops.ooblen = 2; - } else { - ops.len = ops.ooblen = 1; - } - ops.mode = MTD_OPS_PLACE_OOB; - - /* Write to first/last page(s) if necessary */ - if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) - wr_ofs += mtd->erasesize - mtd->writesize; - do { - res = nand_do_write_oob(mtd, wr_ofs, &ops); - if (!ret) - ret = res; - - i++; - wr_ofs += mtd->writesize; - } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); + /* Write bad block marker to OOB */ + nand_get_device(mtd, FL_WRITING); + ret = chip->block_markbad(mtd, ofs); nand_release_device(mtd); } - /* Update flash-based bad block table */ - if (chip->bbt_options & NAND_BBT_USE_FLASH) { - res = nand_update_bbt(mtd, ofs); + /* Mark block bad in BBT */ + if (chip->bbt) { + res = nand_markbad_bbt(mtd, ofs); if (!ret) ret = res; } @@ -504,7 +634,8 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, { struct nand_chip *chip = mtd->priv; - if (!(chip->options & NAND_BBT_SCANNED)) { + if (!(chip->options & NAND_SKIP_BBTSCAN) && + !(chip->options & NAND_BBT_SCANNED)) { chip->options |= NAND_BBT_SCANNED; chip->scan_bbt(mtd); } @@ -516,22 +647,63 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, return nand_isbad_bbt(mtd, ofs, allowbbt); } +#ifndef __UBOOT__ +/** + * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. + * @mtd: MTD device structure + * @timeo: Timeout + * + * Helper function for nand_wait_ready used when needing to wait in interrupt + * context. + */ +static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) +{ + struct nand_chip *chip = mtd->priv; + int i; + + /* Wait for the device to get ready */ + for (i = 0; i < timeo; i++) { + if (chip->dev_ready(mtd)) + break; + touch_softlockup_watchdog(); + mdelay(1); + } +} +#endif + /* Wait for the ready pin, after a command. The timeout is caught later. */ void nand_wait_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; +#ifndef __UBOOT__ + unsigned long timeo = jiffies + msecs_to_jiffies(20); + + /* 400ms timeout */ + if (in_interrupt() || oops_in_progress) + return panic_nand_wait_ready(mtd, 400); + + led_trigger_event(nand_led_trigger, LED_FULL); + /* Wait until command is processed or timeout occurs */ + do { + if (chip->dev_ready(mtd)) + break; + touch_softlockup_watchdog(); + } while (time_before(jiffies, timeo)); + led_trigger_event(nand_led_trigger, LED_OFF); +#else u32 timeo = (CONFIG_SYS_HZ * 20) / 1000; u32 time_start; time_start = get_timer(0); - /* Wait until command is processed or timeout occurs */ while (get_timer(time_start) < timeo) { if (chip->dev_ready) if (chip->dev_ready(mtd)) break; } +#endif } +EXPORT_SYMBOL_GPL(nand_wait_ready); /** * nand_command - [DEFAULT] Send command to NAND device @@ -541,7 +713,7 @@ void nand_wait_ready(struct mtd_info *mtd) * @page_addr: the page address for this command, -1 if none * * Send command to NAND device. This function is used for small page devices - * (256/512 Bytes per page). + * (512 Bytes per page). */ static void nand_command(struct mtd_info *mtd, unsigned int command, int column, int page_addr) @@ -575,7 +747,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16) + if (chip->options & NAND_BUSWIDTH_16 && + !nand_opcode_8bits(command)) column >>= 1; chip->cmd_ctrl(mtd, column, ctrl); ctrl &= ~NAND_CTRL_CHANGE; @@ -659,8 +832,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, } /* Command latch cycle */ - chip->cmd_ctrl(mtd, command & 0xff, - NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); + chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); if (column != -1 || page_addr != -1) { int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; @@ -668,7 +840,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16) + if (chip->options & NAND_BUSWIDTH_16 && + !nand_opcode_8bits(command)) column >>= 1; chip->cmd_ctrl(mtd, column, ctrl); ctrl &= ~NAND_CTRL_CHANGE; @@ -699,16 +872,6 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, case NAND_CMD_SEQIN: case NAND_CMD_RNDIN: case NAND_CMD_STATUS: - case NAND_CMD_DEPLETE1: - return; - - case NAND_CMD_STATUS_ERROR: - case NAND_CMD_STATUS_ERROR0: - case NAND_CMD_STATUS_ERROR1: - case NAND_CMD_STATUS_ERROR2: - case NAND_CMD_STATUS_ERROR3: - /* Read error status commands require only a short delay */ - udelay(chip->chip_delay); return; case NAND_CMD_RESET: @@ -759,18 +922,91 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, } /** - * nand_get_device - [GENERIC] Get chip for selected access + * panic_nand_get_device - [GENERIC] Get chip for selected access * @chip: the nand chip descriptor * @mtd: MTD device structure * @new_state: the state which is requested * + * Used when in panic, no locks are taken. + */ +static void panic_nand_get_device(struct nand_chip *chip, + struct mtd_info *mtd, int new_state) +{ + /* Hardware controller shared among independent devices */ + chip->controller->active = chip; + chip->state = new_state; +} + +/** + * nand_get_device - [GENERIC] Get chip for selected access + * @mtd: MTD device structure + * @new_state: the state which is requested + * * Get the device and lock it for exclusive access */ static int -nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) +nand_get_device(struct mtd_info *mtd, int new_state) { + struct nand_chip *chip = mtd->priv; +#ifndef __UBOOT__ + spinlock_t *lock = &chip->controller->lock; + wait_queue_head_t *wq = &chip->controller->wq; + DECLARE_WAITQUEUE(wait, current); +retry: + spin_lock(lock); + + /* Hardware controller shared among independent devices */ + if (!chip->controller->active) + chip->controller->active = chip; + + if (chip->controller->active == chip && chip->state == FL_READY) { + chip->state = new_state; + spin_unlock(lock); + return 0; + } + if (new_state == FL_PM_SUSPENDED) { + if (chip->controller->active->state == FL_PM_SUSPENDED) { + chip->state = FL_PM_SUSPENDED; + spin_unlock(lock); + return 0; + } + } + set_current_state(TASK_UNINTERRUPTIBLE); + add_wait_queue(wq, &wait); + spin_unlock(lock); + schedule(); + remove_wait_queue(wq, &wait); + goto retry; +#else chip->state = new_state; return 0; +#endif +} + +/** + * panic_nand_wait - [GENERIC] wait until the command is done + * @mtd: MTD device structure + * @chip: NAND chip structure + * @timeo: timeout + * + * Wait for command done. This is a helper function for nand_wait used when + * we are in interrupt context. May happen when in panic and trying to write + * an oops through mtdoops. + */ +static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, + unsigned long timeo) +{ + int i; + for (i = 0; i < timeo; i++) { + if (chip->dev_ready) { + if (chip->dev_ready(mtd)) + break; + } else { + if (chip->read_byte(mtd) & NAND_STATUS_READY) + break; + } + mdelay(1); + } } /** @@ -784,28 +1020,42 @@ nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) */ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) { - unsigned long timeo; - int state = chip->state; - u32 time_start; - if (state == FL_ERASING) - timeo = (CONFIG_SYS_HZ * 400) / 1000; - else - timeo = (CONFIG_SYS_HZ * 20) / 1000; + int status, state = chip->state; + unsigned long timeo = (state == FL_ERASING ? 400 : 20); - if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) - chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); - else - chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + led_trigger_event(nand_led_trigger, LED_FULL); - time_start = get_timer(0); + /* + * Apply this short delay always to ensure that we do wait tWB in any + * case on any machine. + */ + ndelay(100); - while (1) { - if (get_timer(time_start) > timeo) { - printf("Timeout!"); - return 0x01; - } + chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); +#ifndef __UBOOT__ + if (in_interrupt() || oops_in_progress) + panic_nand_wait(mtd, chip, timeo); + else { + timeo = jiffies + msecs_to_jiffies(timeo); + while (time_before(jiffies, timeo)) { + if (chip->dev_ready) { + if (chip->dev_ready(mtd)) + break; + } else { + if (chip->read_byte(mtd) & NAND_STATUS_READY) + break; + } + cond_resched(); + } + } +#else + u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; + u32 time_start; + + time_start = get_timer(0); + while (get_timer(time_start) < timer) { if (chip->dev_ready) { if (chip->dev_ready(mtd)) break; @@ -814,15 +1064,171 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) break; } } -#ifdef PPCHAMELON_NAND_TIMER_HACK - time_start = get_timer(0); - while (get_timer(time_start) < 10) - ; -#endif /* PPCHAMELON_NAND_TIMER_HACK */ +#endif + led_trigger_event(nand_led_trigger, LED_OFF); - return (int)chip->read_byte(mtd); + status = (int)chip->read_byte(mtd); + /* This can happen if in case of timeout or buggy dev_ready */ + WARN_ON(!(status & NAND_STATUS_READY)); + return status; } +#ifndef __UBOOT__ +/** + * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks + * @mtd: mtd info + * @ofs: offset to start unlock from + * @len: length to unlock + * @invert: when = 0, unlock the range of blocks within the lower and + * upper boundary address + * when = 1, unlock the range of blocks outside the boundaries + * of the lower and upper boundary address + * + * Returs unlock status. + */ +static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, + uint64_t len, int invert) +{ + int ret = 0; + int status, page; + struct nand_chip *chip = mtd->priv; + + /* Submit address of first page to unlock */ + page = ofs >> chip->page_shift; + chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); + + /* Submit address of last page to unlock */ + page = (ofs + len) >> chip->page_shift; + chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, + (page | invert) & chip->pagemask); + + /* Call wait ready function */ + status = chip->waitfunc(mtd, chip); + /* See if device thinks it succeeded */ + if (status & NAND_STATUS_FAIL) { + pr_debug("%s: error status = 0x%08x\n", + __func__, status); + ret = -EIO; + } + + return ret; +} + +/** + * nand_unlock - [REPLACEABLE] unlocks specified locked blocks + * @mtd: mtd info + * @ofs: offset to start unlock from + * @len: length to unlock + * + * Returns unlock status. + */ +int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +{ + int ret = 0; + int chipnr; + struct nand_chip *chip = mtd->priv; + + pr_debug("%s: start = 0x%012llx, len = %llu\n", + __func__, (unsigned long long)ofs, len); + + if (check_offs_len(mtd, ofs, len)) + ret = -EINVAL; + + /* Align to last block address if size addresses end of the device */ + if (ofs + len == mtd->size) + len -= mtd->erasesize; + + nand_get_device(mtd, FL_UNLOCKING); + + /* Shift to get chip number */ + chipnr = ofs >> chip->chip_shift; + + chip->select_chip(mtd, chipnr); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) { + pr_debug("%s: device is write protected!\n", + __func__); + ret = -EIO; + goto out; + } + + ret = __nand_unlock(mtd, ofs, len, 0); + +out: + chip->select_chip(mtd, -1); + nand_release_device(mtd); + + return ret; +} +EXPORT_SYMBOL(nand_unlock); + +/** + * nand_lock - [REPLACEABLE] locks all blocks present in the device + * @mtd: mtd info + * @ofs: offset to start unlock from + * @len: length to unlock + * + * This feature is not supported in many NAND parts. 'Micron' NAND parts do + * have this feature, but it allows only to lock all blocks, not for specified + * range for block. Implementing 'lock' feature by making use of 'unlock', for + * now. + * + * Returns lock status. + */ +int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +{ + int ret = 0; + int chipnr, status, page; + struct nand_chip *chip = mtd->priv; + + pr_debug("%s: start = 0x%012llx, len = %llu\n", + __func__, (unsigned long long)ofs, len); + + if (check_offs_len(mtd, ofs, len)) + ret = -EINVAL; + + nand_get_device(mtd, FL_LOCKING); + + /* Shift to get chip number */ + chipnr = ofs >> chip->chip_shift; + + chip->select_chip(mtd, chipnr); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) { + pr_debug("%s: device is write protected!\n", + __func__); + status = MTD_ERASE_FAILED; + ret = -EIO; + goto out; + } + + /* Submit address of first page to lock */ + page = ofs >> chip->page_shift; + chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); + + /* Call wait ready function */ + status = chip->waitfunc(mtd, chip); + /* See if device thinks it succeeded */ + if (status & NAND_STATUS_FAIL) { + pr_debug("%s: error status = 0x%08x\n", + __func__, status); + ret = -EIO; + goto out; + } + + ret = __nand_unlock(mtd, ofs, len, 0x1); + +out: + chip->select_chip(mtd, -1); + nand_release_device(mtd); + + return ret; +} +EXPORT_SYMBOL(nand_lock); +#endif + /** * nand_read_page_raw - [INTERN] read raw page data without ecc * @mtd: mtd info structure @@ -904,6 +1310,7 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *ecc_calc = chip->buffers->ecccalc; uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; + unsigned int max_bitflips = 0; chip->ecc.read_page_raw(mtd, chip, buf, 1, page); @@ -920,24 +1327,28 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, int stat; stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); - if (stat < 0) + if (stat < 0) { mtd->ecc_stats.failed++; - else + } else { mtd->ecc_stats.corrected += stat; + max_bitflips = max_t(unsigned int, max_bitflips, stat); + } } - return 0; + return max_bitflips; } /** - * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function + * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function * @mtd: mtd info structure * @chip: nand chip info structure * @data_offs: offset of requested data within the page * @readlen: data length * @bufpoi: buffer to store read data + * @page: page number to read */ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, - uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) + uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, + int page) { int start_step, end_step, num_steps; uint32_t *eccpos = chip->ecc.layout->eccpos; @@ -945,12 +1356,14 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, int data_col_addr, i, gaps = 0; int datafrag_len, eccfrag_len, aligned_len, aligned_pos; int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; - int index = 0; + int index; + unsigned int max_bitflips = 0; /* Column address within the page aligned to ECC size (256bytes) */ start_step = data_offs / chip->ecc.size; end_step = (data_offs + readlen - 1) / chip->ecc.size; num_steps = end_step - start_step + 1; + index = start_step * chip->ecc.bytes; /* Data size aligned to ECC ecc.size */ datafrag_len = num_steps * chip->ecc.size; @@ -987,8 +1400,6 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, * Send the command to read the particular ECC bytes take care * about buswidth alignment in read_buf. */ - index = start_step * chip->ecc.bytes; - aligned_pos = eccpos[index] & ~(busw - 1); aligned_len = eccfrag_len; if (eccpos[index] & (busw - 1)) @@ -1010,12 +1421,14 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); - if (stat < 0) + if (stat < 0) { mtd->ecc_stats.failed++; - else + } else { mtd->ecc_stats.corrected += stat; + max_bitflips = max_t(unsigned int, max_bitflips, stat); + } } - return 0; + return max_bitflips; } /** @@ -1038,6 +1451,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *ecc_calc = chip->buffers->ecccalc; uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; + unsigned int max_bitflips = 0; for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { chip->ecc.hwctl(mtd, NAND_ECC_READ); @@ -1056,12 +1470,14 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, int stat; stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); - if (stat < 0) + if (stat < 0) { mtd->ecc_stats.failed++; - else + } else { mtd->ecc_stats.corrected += stat; + max_bitflips = max_t(unsigned int, max_bitflips, stat); + } } - return 0; + return max_bitflips; } /** @@ -1088,6 +1504,7 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; uint8_t *ecc_calc = chip->buffers->ecccalc; + unsigned int max_bitflips = 0; /* Read the OOB area first */ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); @@ -1105,12 +1522,14 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, chip->ecc.calculate(mtd, p, &ecc_calc[i]); stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); - if (stat < 0) + if (stat < 0) { mtd->ecc_stats.failed++; - else + } else { mtd->ecc_stats.corrected += stat; + max_bitflips = max_t(unsigned int, max_bitflips, stat); + } } - return 0; + return max_bitflips; } /** @@ -1132,6 +1551,7 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int eccsteps = chip->ecc.steps; uint8_t *p = buf; uint8_t *oob = chip->oob_poi; + unsigned int max_bitflips = 0; for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { int stat; @@ -1148,10 +1568,12 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, chip->read_buf(mtd, oob, eccbytes); stat = chip->ecc.correct(mtd, p, oob, NULL); - if (stat < 0) + if (stat < 0) { mtd->ecc_stats.failed++; - else + } else { mtd->ecc_stats.corrected += stat; + max_bitflips = max_t(unsigned int, max_bitflips, stat); + } oob += eccbytes; @@ -1166,7 +1588,7 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, if (i) chip->read_buf(mtd, oob, i); - return 0; + return max_bitflips; } /** @@ -1217,6 +1639,30 @@ static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, return NULL; } +/** + * nand_setup_read_retry - [INTERN] Set the READ RETRY mode + * @mtd: MTD device structure + * @retry_mode: the retry mode to use + * + * Some vendors supply a special command to shift the Vt threshold, to be used + * when there are too many bitflips in a page (i.e., ECC error). After setting + * a new threshold, the host should retry reading the page. + */ +static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) +{ + struct nand_chip *chip = mtd->priv; + + pr_debug("setting READ RETRY mode %d\n", retry_mode); + + if (retry_mode >= chip->read_retries) + return -EINVAL; + + if (!chip->setup_read_retry) + return -EOPNOTSUPP; + + return chip->setup_read_retry(mtd, retry_mode); +} + /** * nand_do_read_ops - [INTERN] Read data with ECC * @mtd: MTD device structure @@ -1230,7 +1676,6 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, { int chipnr, page, realpage, col, bytes, aligned, oob_required; struct nand_chip *chip = mtd->priv; - struct mtd_ecc_stats stats; int ret = 0; uint32_t readlen = ops->len; uint32_t oobreadlen = ops->ooblen; @@ -1238,8 +1683,9 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, mtd->oobavail : mtd->oobsize; uint8_t *bufpoi, *oob, *buf; - - stats = mtd->ecc_stats; + unsigned int max_bitflips = 0; + int retry_mode = 0; + bool ecc_fail = false; chipnr = (int)(from >> chip->chip_shift); chip->select_chip(mtd, chipnr); @@ -1254,8 +1700,9 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, oob_required = oob ? 1 : 0; while (1) { - WATCHDOG_RESET(); + unsigned int ecc_failures = mtd->ecc_stats.failed; + WATCHDOG_RESET(); bytes = min(mtd->writesize - col, readlen); aligned = (bytes == mtd->writesize); @@ -1263,17 +1710,22 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, if (realpage != chip->pagebuf || oob) { bufpoi = aligned ? buf : chip->buffers->databuf; +read_retry: chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); - /* Now read the page into the buffer */ + /* + * Now read the page into the buffer. Absent an error, + * the read methods return max bitflips per ecc step. + */ if (unlikely(ops->mode == MTD_OPS_RAW)) ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, oob_required, page); else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && - !oob) + !oob) ret = chip->ecc.read_subpage(mtd, chip, - col, bytes, bufpoi); + col, bytes, bufpoi, + page); else ret = chip->ecc.read_page(mtd, chip, bufpoi, oob_required, page); @@ -1284,20 +1736,22 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, break; } + max_bitflips = max_t(unsigned int, max_bitflips, ret); + /* Transfer not aligned data */ if (!aligned) { if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && - !(mtd->ecc_stats.failed - stats.failed) && - (ops->mode != MTD_OPS_RAW)) + !(mtd->ecc_stats.failed - ecc_failures) && + (ops->mode != MTD_OPS_RAW)) { chip->pagebuf = realpage; - else + chip->pagebuf_bitflips = ret; + } else { /* Invalidate page cache */ chip->pagebuf = -1; + } memcpy(buf, chip->buffers->databuf + col, bytes); } - buf += bytes; - if (unlikely(oob)) { int toread = min(oobreadlen, max_oobsize); @@ -1307,13 +1761,50 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, oobreadlen -= toread; } } + + if (chip->options & NAND_NEED_READRDY) { + /* Apply delay or wait for ready/busy pin */ + if (!chip->dev_ready) + udelay(chip->chip_delay); + else + nand_wait_ready(mtd); + } + + if (mtd->ecc_stats.failed - ecc_failures) { + if (retry_mode + 1 < chip->read_retries) { + retry_mode++; + ret = nand_setup_read_retry(mtd, + retry_mode); + if (ret < 0) + break; + + /* Reset failures; retry */ + mtd->ecc_stats.failed = ecc_failures; + goto read_retry; + } else { + /* No more retry modes; real failure */ + ecc_fail = true; + } + } + + buf += bytes; } else { memcpy(buf, chip->buffers->databuf + col, bytes); buf += bytes; + max_bitflips = max_t(unsigned int, max_bitflips, + chip->pagebuf_bitflips); } readlen -= bytes; + /* Reset to retry mode 0 */ + if (retry_mode) { + ret = nand_setup_read_retry(mtd, 0); + if (ret < 0) + break; + retry_mode = 0; + } + if (!readlen) break; @@ -1330,18 +1821,19 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, chip->select_chip(mtd, chipnr); } } + chip->select_chip(mtd, -1); ops->retlen = ops->len - (size_t) readlen; if (oob) ops->oobretlen = ops->ooblen - oobreadlen; - if (ret) + if (ret < 0) return ret; - if (mtd->ecc_stats.failed - stats.failed) + if (ecc_fail) return -EBADMSG; - return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; + return max_bitflips; } /** @@ -1357,11 +1849,10 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, uint8_t *buf) { - struct nand_chip *chip = mtd->priv; struct mtd_oob_ops ops; int ret; - nand_get_device(chip, mtd, FL_READING); + nand_get_device(mtd, FL_READING); ops.len = len; ops.datbuf = buf; ops.oobbuf = NULL; @@ -1525,7 +2016,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, uint8_t *buf = ops->oobbuf; int ret = 0; - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n", + pr_debug("%s: from = 0x%08Lx, len = %i\n", __func__, (unsigned long long)from, readlen); stats = mtd->ecc_stats; @@ -1536,8 +2027,8 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, len = mtd->oobsize; if (unlikely(ops->ooboffs >= len)) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read " - "outside oob\n", __func__); + pr_debug("%s: attempt to start read outside oob\n", + __func__); return -EINVAL; } @@ -1545,8 +2036,8 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, if (unlikely(from >= mtd->size || ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - (from >> chip->page_shift)) * len)) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end " - "of device\n", __func__); + pr_debug("%s: attempt to read beyond end of device\n", + __func__); return -EINVAL; } @@ -1559,6 +2050,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, while (1) { WATCHDOG_RESET(); + if (ops->mode == MTD_OPS_RAW) ret = chip->ecc.read_oob_raw(mtd, chip, page); else @@ -1570,6 +2062,14 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, len = min(len, readlen); buf = nand_transfer_oob(chip, buf, ops, len); + if (chip->options & NAND_NEED_READRDY) { + /* Apply delay or wait for ready/busy pin */ + if (!chip->dev_ready) + udelay(chip->chip_delay); + else + nand_wait_ready(mtd); + } + readlen -= len; if (!readlen) break; @@ -1585,6 +2085,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, chip->select_chip(mtd, chipnr); } } + chip->select_chip(mtd, -1); ops->oobretlen = ops->ooblen - readlen; @@ -1608,19 +2109,18 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, static int nand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { - struct nand_chip *chip = mtd->priv; int ret = -ENOTSUPP; ops->retlen = 0; /* Do not allow reads past end of device */ if (ops->datbuf && (from + ops->len) > mtd->size) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read " - "beyond end of device\n", __func__); + pr_debug("%s: attempt to read beyond end of device\n", + __func__); return -EINVAL; } - nand_get_device(chip, mtd, FL_READING); + nand_get_device(mtd, FL_READING); switch (ops->mode) { case MTD_OPS_PLACE_OOB: @@ -1689,7 +2189,7 @@ static int nand_write_page_raw_syndrome(struct mtd_info *mtd, oob += chip->ecc.prepad; } - chip->read_buf(mtd, oob, eccbytes); + chip->write_buf(mtd, oob, eccbytes); oob += eccbytes; if (chip->ecc.postpad) { @@ -1762,6 +2262,68 @@ static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, return 0; } + +/** + * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write + * @mtd: mtd info structure + * @chip: nand chip info structure + * @offset: column address of subpage within the page + * @data_len: data length + * @buf: data buffer + * @oob_required: must write chip->oob_poi to OOB + */ +static int nand_write_subpage_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, uint32_t offset, + uint32_t data_len, const uint8_t *buf, + int oob_required) +{ + uint8_t *oob_buf = chip->oob_poi; + uint8_t *ecc_calc = chip->buffers->ecccalc; + int ecc_size = chip->ecc.size; + int ecc_bytes = chip->ecc.bytes; + int ecc_steps = chip->ecc.steps; + uint32_t *eccpos = chip->ecc.layout->eccpos; + uint32_t start_step = offset / ecc_size; + uint32_t end_step = (offset + data_len - 1) / ecc_size; + int oob_bytes = mtd->oobsize / ecc_steps; + int step, i; + + for (step = 0; step < ecc_steps; step++) { + /* configure controller for WRITE access */ + chip->ecc.hwctl(mtd, NAND_ECC_WRITE); + + /* write data (untouched subpages already masked by 0xFF) */ + chip->write_buf(mtd, buf, ecc_size); + + /* mask ECC of un-touched subpages by padding 0xFF */ + if ((step < start_step) || (step > end_step)) + memset(ecc_calc, 0xff, ecc_bytes); + else + chip->ecc.calculate(mtd, buf, ecc_calc); + + /* mask OOB of un-touched subpages by padding 0xFF */ + /* if oob_required, preserve OOB metadata of written subpage */ + if (!oob_required || (step < start_step) || (step > end_step)) + memset(oob_buf, 0xff, oob_bytes); + + buf += ecc_size; + ecc_calc += ecc_bytes; + oob_buf += oob_bytes; + } + + /* copy calculated ECC for whole page to chip->buffer->oob */ + /* this include masked-value(0xFF) for unwritten subpages */ + ecc_calc = chip->buffers->ecccalc; + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ecc_calc[i]; + + /* write OOB buffer to NAND device */ + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; +} + + /** * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write * @mtd: mtd info structure @@ -1814,6 +2376,8 @@ static int nand_write_page_syndrome(struct mtd_info *mtd, * nand_write_page - [REPLACEABLE] write one page * @mtd: MTD device structure * @chip: NAND chip descriptor + * @offset: address offset within the page + * @data_len: length of actual data to be written * @buf: the data to write * @oob_required: must write chip->oob_poi to OOB * @page: page number to write @@ -1821,15 +2385,25 @@ static int nand_write_page_syndrome(struct mtd_info *mtd, * @raw: use _raw version of write_page */ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required, int page, - int cached, int raw) + uint32_t offset, int data_len, const uint8_t *buf, + int oob_required, int page, int cached, int raw) { - int status; + int status, subpage; + + if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && + chip->ecc.write_subpage) + subpage = offset || (data_len < mtd->writesize); + else + subpage = 0; chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); if (unlikely(raw)) - status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); + status = chip->ecc.write_page_raw(mtd, chip, buf, + oob_required); + else if (subpage) + status = chip->ecc.write_subpage(mtd, chip, offset, data_len, + buf, oob_required); else status = chip->ecc.write_page(mtd, chip, buf, oob_required); @@ -1842,7 +2416,7 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, */ cached = 0; - if (!cached || !(chip->options & NAND_CACHEPRG)) { + if (!cached || !NAND_HAS_CACHEPROG(chip)) { chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); status = chip->waitfunc(mtd, chip); @@ -1861,7 +2435,9 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, status = chip->waitfunc(mtd, chip); } -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + +#ifdef __UBOOT__ +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) /* Send command to read back the data */ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); @@ -1871,6 +2447,8 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, /* Make sure the next page prog is preceded by a status read */ chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); #endif +#endif + return 0; } @@ -1930,6 +2508,8 @@ static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, return NULL; } +#define NOTALIGNED(x) (((x) & (chip->subpagesize - 1)) != 0) + /** * nand_do_write_ops - [INTERN] NAND write with ECC * @mtd: MTD device structure @@ -1951,26 +2531,34 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, uint8_t *oob = ops->oobbuf; uint8_t *buf = ops->datbuf; - int ret, subpage; + int ret; int oob_required = oob ? 1 : 0; ops->retlen = 0; if (!writelen) return 0; - column = to & (mtd->writesize - 1); - subpage = column || (writelen & (mtd->writesize - 1)); - - if (subpage && oob) +#ifndef __UBOOT__ + /* Reject writes, which are not page aligned */ + if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { +#else + /* Reject writes, which are not page aligned */ + if (NOTALIGNED(to)) { +#endif + pr_notice("%s: attempt to write non page aligned data\n", + __func__); return -EINVAL; + } + + column = to & (mtd->writesize - 1); chipnr = (int)(to >> chip->chip_shift); chip->select_chip(mtd, chipnr); /* Check, if it is write protected */ if (nand_check_wp(mtd)) { - printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n"); - return -EIO; + ret = -EIO; + goto err_out; } realpage = (int)(to >> chip->page_shift); @@ -1983,18 +2571,19 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, chip->pagebuf = -1; /* Don't allow multipage oob writes with offset */ - if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) - return -EINVAL; + if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { + ret = -EINVAL; + goto err_out; + } while (1) { - WATCHDOG_RESET(); - int bytes = mtd->writesize; int cached = writelen > bytes && page != blockmask; uint8_t *wbuf = buf; + WATCHDOG_RESET(); /* Partial page write? */ - if (unlikely(column || writelen < mtd->writesize)) { + if (unlikely(column || writelen < (mtd->writesize - 1))) { cached = 0; bytes = min_t(int, bytes - column, (int) writelen); chip->pagebuf = -1; @@ -2011,9 +2600,9 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, /* We still need to erase leftover OOB data */ memset(chip->oob_poi, 0xff, mtd->oobsize); } - - ret = chip->write_page(mtd, chip, wbuf, oob_required, page, - cached, (ops->mode == MTD_OPS_RAW)); + ret = chip->write_page(mtd, chip, column, bytes, wbuf, + oob_required, page, cached, + (ops->mode == MTD_OPS_RAW)); if (ret) break; @@ -2037,6 +2626,44 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, ops->retlen = ops->len - writelen; if (unlikely(oob)) ops->oobretlen = ops->ooblen; + +err_out: + chip->select_chip(mtd, -1); + return ret; +} + +/** + * panic_nand_write - [MTD Interface] NAND write with ECC + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * + * NAND write with ECC. Used when performing writes in interrupt context, this + * may for example be called by mtdoops when writing an oops while in panic. + */ +static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const uint8_t *buf) +{ + struct nand_chip *chip = mtd->priv; + struct mtd_oob_ops ops; + int ret; + + /* Wait for the device to get ready */ + panic_nand_wait(mtd, chip, 400); + + /* Grab the device */ + panic_nand_get_device(chip, mtd, FL_WRITING); + + ops.len = len; + ops.datbuf = (uint8_t *)buf; + ops.oobbuf = NULL; + ops.mode = MTD_OPS_PLACE_OOB; + + ret = nand_do_write_ops(mtd, to, &ops); + + *retlen = ops.retlen; return ret; } @@ -2053,11 +2680,10 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const uint8_t *buf) { - struct nand_chip *chip = mtd->priv; struct mtd_oob_ops ops; int ret; - nand_get_device(chip, mtd, FL_WRITING); + nand_get_device(mtd, FL_WRITING); ops.len = len; ops.datbuf = (uint8_t *)buf; ops.oobbuf = NULL; @@ -2082,7 +2708,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, int chipnr, page, status, len; struct nand_chip *chip = mtd->priv; - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n", + pr_debug("%s: to = 0x%08x, len = %i\n", __func__, (unsigned int)to, (int)ops->ooblen); if (ops->mode == MTD_OPS_AUTO_OOB) @@ -2092,14 +2718,14 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, /* Do not allow write past end of page */ if ((ops->ooboffs + ops->ooblen) > len) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write " - "past end of page\n", __func__); + pr_debug("%s: attempt to write past end of page\n", + __func__); return -EINVAL; } if (unlikely(ops->ooboffs >= len)) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start " - "write outside oob\n", __func__); + pr_debug("%s: attempt to start write outside oob\n", + __func__); return -EINVAL; } @@ -2108,8 +2734,8 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, ops->ooboffs + ops->ooblen > ((mtd->size >> chip->page_shift) - (to >> chip->page_shift)) * len)) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " - "end of device\n", __func__); + pr_debug("%s: attempt to write beyond end of device\n", + __func__); return -EINVAL; } @@ -2128,8 +2754,10 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); /* Check, if it is write protected */ - if (nand_check_wp(mtd)) + if (nand_check_wp(mtd)) { + chip->select_chip(mtd, -1); return -EROFS; + } /* Invalidate the page cache, if we write to the cached page */ if (page == chip->pagebuf) @@ -2142,6 +2770,8 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, else status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); + chip->select_chip(mtd, -1); + if (status) return status; @@ -2159,19 +2789,18 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, static int nand_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) { - struct nand_chip *chip = mtd->priv; int ret = -ENOTSUPP; ops->retlen = 0; /* Do not allow writes past end of device */ if (ops->datbuf && (to + ops->len) > mtd->size) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " - "end of device\n", __func__); + pr_debug("%s: attempt to write beyond end of device\n", + __func__); return -EINVAL; } - nand_get_device(chip, mtd, FL_WRITING); + nand_get_device(mtd, FL_WRITING); switch (ops->mode) { case MTD_OPS_PLACE_OOB: @@ -2208,24 +2837,6 @@ static void single_erase_cmd(struct mtd_info *mtd, int page) chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); } -/** - * multi_erase_cmd - [GENERIC] AND specific block erase command function - * @mtd: MTD device structure - * @page: the page address of the block which will be erased - * - * AND multi block erase command function. Erase 4 consecutive blocks. - */ -static void multi_erase_cmd(struct mtd_info *mtd, int page) -{ - struct nand_chip *chip = mtd->priv; - /* Send commands to erase a block */ - chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); - chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); - chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); - chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); - chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); -} - /** * nand_erase - [MTD Interface] erase block(s) * @mtd: MTD device structure @@ -2238,7 +2849,6 @@ static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) return nand_erase_nand(mtd, instr, 0); } -#define BBT_PAGE_MASK 0xffffff3f /** * nand_erase_nand - [INTERN] erase block(s) * @mtd: MTD device structure @@ -2252,19 +2862,17 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, { int page, status, pages_per_block, ret, chipnr; struct nand_chip *chip = mtd->priv; - loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0}; - unsigned int bbt_masked_page = 0xffffffff; loff_t len; - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", - __func__, (unsigned long long)instr->addr, - (unsigned long long)instr->len); + pr_debug("%s: start = 0x%012llx, len = %llu\n", + __func__, (unsigned long long)instr->addr, + (unsigned long long)instr->len); if (check_offs_len(mtd, instr->addr, instr->len)) return -EINVAL; /* Grab the lock and see if the device is available */ - nand_get_device(chip, mtd, FL_ERASING); + nand_get_device(mtd, FL_ERASING); /* Shift to get first page */ page = (int)(instr->addr >> chip->page_shift); @@ -2278,21 +2886,12 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, /* Check, if it is write protected */ if (nand_check_wp(mtd)) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", - __func__); + pr_debug("%s: device is write protected!\n", + __func__); instr->state = MTD_ERASE_FAILED; goto erase_exit; } - /* - * If BBT requires refresh, set the BBT page mask to see if the BBT - * should be rewritten. Otherwise the mask is set to 0xffffffff which - * can not be matched. This is also done when the bbt is actually - * erased to avoid recursive updates. - */ - if (chip->options & BBT_AUTO_REFRESH && !allowbbt) - bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; - /* Loop through the pages */ len = instr->len; @@ -2300,11 +2899,12 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, while (len) { WATCHDOG_RESET(); + /* Check if we have a bad block, we do not erase bad blocks! */ if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) << chip->page_shift, 0, allowbbt)) { pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", - __func__, page); + __func__, page); instr->state = MTD_ERASE_FAILED; goto erase_exit; } @@ -2331,25 +2931,16 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, /* See if block erase succeeded */ if (status & NAND_STATUS_FAIL) { - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, " - "page 0x%08x\n", __func__, page); + pr_debug("%s: failed erase, page 0x%08x\n", + __func__, page); instr->state = MTD_ERASE_FAILED; instr->fail_addr = ((loff_t)page << chip->page_shift); goto erase_exit; } - /* - * If BBT requires refresh, set the BBT rewrite flag to the - * page being erased. - */ - if (bbt_masked_page != 0xffffffff && - (page & BBT_PAGE_MASK) == bbt_masked_page) - rewrite_bbt[chipnr] = - ((loff_t)page << chip->page_shift); - /* Increment page address and decrement length */ - len -= (1 << chip->phys_erase_shift); + len -= (1ULL << chip->phys_erase_shift); page += pages_per_block; /* Check, if we cross a chip boundary */ @@ -2357,15 +2948,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, chipnr++; chip->select_chip(mtd, -1); chip->select_chip(mtd, chipnr); - - /* - * If BBT requires refresh and BBT-PERCHIP, set the BBT - * page mask to see if this BBT should be rewritten. - */ - if (bbt_masked_page != 0xffffffff && - (chip->bbt_td->options & NAND_BBT_PERCHIP)) - bbt_masked_page = chip->bbt_td->pages[chipnr] & - BBT_PAGE_MASK; } } instr->state = MTD_ERASE_DONE; @@ -2375,29 +2957,13 @@ erase_exit: ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; /* Deselect and wake up anyone waiting on the device */ + chip->select_chip(mtd, -1); nand_release_device(mtd); /* Do call back function */ if (!ret) mtd_erase_callback(instr); - /* - * If BBT requires refresh and erase was successful, rewrite any - * selected bad block tables. - */ - if (bbt_masked_page == 0xffffffff || ret) - return ret; - - for (chipnr = 0; chipnr < chip->numchips; chipnr++) { - if (!rewrite_bbt[chipnr]) - continue; - /* Update the BBT for chip */ - MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt " - "(%d:0x%0llx 0x%0x)\n", __func__, chipnr, - rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]); - nand_update_bbt(mtd, rewrite_bbt[chipnr]); - } - /* Return more or less happy */ return ret; } @@ -2410,12 +2976,10 @@ erase_exit: */ static void nand_sync(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - - MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__); + pr_debug("%s: called\n", __func__); /* Grab the lock and see if the device is available */ - nand_get_device(chip, mtd, FL_SYNCING); + nand_get_device(mtd, FL_SYNCING); /* Release it and go back */ nand_release_device(mtd); } @@ -2437,7 +3001,6 @@ static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) */ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) { - struct nand_chip *chip = mtd->priv; int ret; ret = nand_block_isbad(mtd, ofs); @@ -2448,10 +3011,10 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) return ret; } - return chip->block_markbad(mtd, ofs); + return nand_block_markbad_lowlevel(mtd, ofs); } - /** +/** * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand * @mtd: MTD device structure * @chip: nand chip info structure @@ -2462,12 +3025,19 @@ static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, int addr, uint8_t *subfeature_param) { int status; + int i; - if (!chip->onfi_version) +#ifdef CONFIG_SYS_NAND_ONFI_DETECTION + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) return -EINVAL; +#endif chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); - chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); + for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) + chip->write_byte(mtd, subfeature_param[i]); + status = chip->waitfunc(mtd, chip); if (status & NAND_STATUS_FAIL) return -EIO; @@ -2484,17 +3054,50 @@ static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, int addr, uint8_t *subfeature_param) { - if (!chip->onfi_version) + int i; + +#ifdef CONFIG_SYS_NAND_ONFI_DETECTION + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) return -EINVAL; +#endif /* clear the sub feature parameters */ memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); - chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); + for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) + *subfeature_param++ = chip->read_byte(mtd); return 0; } +#ifndef __UBOOT__ +/** + * nand_suspend - [MTD Interface] Suspend the NAND flash + * @mtd: MTD device structure + */ +static int nand_suspend(struct mtd_info *mtd) +{ + return nand_get_device(mtd, FL_PM_SUSPENDED); +} + +/** + * nand_resume - [MTD Interface] Resume the NAND flash + * @mtd: MTD device structure + */ +static void nand_resume(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (chip->state == FL_PM_SUSPENDED) + nand_release_device(mtd); + else + pr_err("%s called for a chip which is not in suspended state\n", + __func__); +} +#endif + /* Set default functions */ static void nand_set_defaults(struct nand_chip *chip, int busw) { @@ -2512,7 +3115,15 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) if (!chip->select_chip) chip->select_chip = nand_select_chip; - if (!chip->read_byte) + + /* set for ONFI nand */ + if (!chip->onfi_set_features) + chip->onfi_set_features = nand_onfi_set_features; + if (!chip->onfi_get_features) + chip->onfi_get_features = nand_onfi_get_features; + + /* If called twice, pointers that depend on busw may need to be reset */ + if (!chip->read_byte || chip->read_byte == nand_read_byte) chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; if (!chip->read_word) chip->read_word = nand_read_word; @@ -2520,21 +3131,35 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->block_bad = nand_block_bad; if (!chip->block_markbad) chip->block_markbad = nand_default_block_markbad; - if (!chip->write_buf) + if (!chip->write_buf || chip->write_buf == nand_write_buf) chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; - if (!chip->read_buf) + if (!chip->write_byte || chip->write_byte == nand_write_byte) + chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; + if (!chip->read_buf || chip->read_buf == nand_read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; - if (!chip->verify_buf) - chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; - if (!chip->controller) +#ifdef __UBOOT__ +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) + if (!chip->verify_buf) + chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; +#endif +#endif + + if (!chip->controller) { chip->controller = &chip->hwcontrol; + spin_lock_init(&chip->controller->lock); + init_waitqueue_head(&chip->controller->wq); + } + } -#ifdef CONFIG_SYS_NAND_ONFI_DETECTION /* Sanitize ONFI strings so we can safely print them */ +#ifndef __UBOOT__ +static void sanitize_string(uint8_t *s, size_t len) +#else static void sanitize_string(char *s, size_t len) +#endif { ssize_t i; @@ -2563,6 +3188,106 @@ static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) return crc; } +#ifdef CONFIG_SYS_NAND_ONFI_DETECTION +/* Parse the Extended Parameter Page. */ +static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, + struct nand_chip *chip, struct nand_onfi_params *p) +{ + struct onfi_ext_param_page *ep; + struct onfi_ext_section *s; + struct onfi_ext_ecc_info *ecc; + uint8_t *cursor; + int ret = -EINVAL; + int len; + int i; + + len = le16_to_cpu(p->ext_param_page_length) * 16; + ep = kmalloc(len, GFP_KERNEL); + if (!ep) + return -ENOMEM; + + /* Send our own NAND_CMD_PARAM. */ + chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); + + /* Use the Change Read Column command to skip the ONFI param pages. */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, + sizeof(*p) * p->num_of_param_pages , -1); + + /* Read out the Extended Parameter Page. */ + chip->read_buf(mtd, (uint8_t *)ep, len); + if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) + != le16_to_cpu(ep->crc))) { + pr_debug("fail in the CRC.\n"); + goto ext_out; + } + + /* + * Check the signature. + * Do not strictly follow the ONFI spec, maybe changed in future. + */ +#ifndef __UBOOT__ + if (strncmp(ep->sig, "EPPS", 4)) { +#else + if (strncmp((char *)ep->sig, "EPPS", 4)) { +#endif + pr_debug("The signature is invalid.\n"); + goto ext_out; + } + + /* find the ECC section. */ + cursor = (uint8_t *)(ep + 1); + for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { + s = ep->sections + i; + if (s->type == ONFI_SECTION_TYPE_2) + break; + cursor += s->length * 16; + } + if (i == ONFI_EXT_SECTION_MAX) { + pr_debug("We can not find the ECC section.\n"); + goto ext_out; + } + + /* get the info we want. */ + ecc = (struct onfi_ext_ecc_info *)cursor; + + if (!ecc->codeword_size) { + pr_debug("Invalid codeword size\n"); + goto ext_out; + } + + chip->ecc_strength_ds = ecc->ecc_bits; + chip->ecc_step_ds = 1 << ecc->codeword_size; + ret = 0; + +ext_out: + kfree(ep); + return ret; +} + +static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) +{ + struct nand_chip *chip = mtd->priv; + uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; + + return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, + feature); +} + +/* + * Configure chip properties from Micron vendor-specific ONFI table + */ +static void nand_onfi_detect_micron(struct nand_chip *chip, + struct nand_onfi_params *p) +{ + struct nand_onfi_vendor_micron *micron = (void *)p->vendor; + + if (le16_to_cpu(p->vendor_revision) < 1) + return; + + chip->read_retries = micron->read_retry_options; + chip->setup_read_retry = nand_setup_read_retry_micron; +} + /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ @@ -2570,7 +3295,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, int *busw) { struct nand_onfi_params *p = &chip->onfi_params; - int i; + int i, j; int val; /* Try ONFI for unknown chip or LP */ @@ -2581,16 +3306,18 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); for (i = 0; i < 3; i++) { - chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); + for (j = 0; j < sizeof(*p); j++) + ((uint8_t *)p)[j] = chip->read_byte(mtd); if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == le16_to_cpu(p->crc)) { - pr_info("ONFI param page %d valid\n", i); break; } } - if (i == 3) + if (i == 3) { + pr_err("Could not find valid ONFI parameter page; aborting\n"); return 0; + } /* Check version */ val = le16_to_cpu(p->revision); @@ -2604,11 +3331,9 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, chip->onfi_version = 20; else if (val & (1 << 1)) chip->onfi_version = 10; - else - chip->onfi_version = 0; if (!chip->onfi_version) { - pr_info("%s: unsupported ONFI version: %d\n", __func__, val); + pr_info("unsupported ONFI version: %d\n", val); return 0; } @@ -2616,27 +3341,145 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, sanitize_string(p->model, sizeof(p->model)); if (!mtd->name) mtd->name = p->model; + mtd->writesize = le32_to_cpu(p->byte_per_page); - mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; + + /* + * pages_per_block and blocks_per_lun may not be a power-of-2 size + * (don't ask me who thought of this...). MTD assumes that these + * dimensions will be power-of-2, so just truncate the remaining area. + */ + mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); + mtd->erasesize *= mtd->writesize; + mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); - chip->chipsize = le32_to_cpu(p->blocks_per_lun); + + /* See erasesize comment */ + chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; - *busw = 0; - if (le16_to_cpu(p->features) & 1) + chip->bits_per_cell = p->bits_per_cell; + + if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) *busw = NAND_BUSWIDTH_16; + else + *busw = 0; + + if (p->ecc_bits != 0xff) { + chip->ecc_strength_ds = p->ecc_bits; + chip->ecc_step_ds = 512; + } else if (chip->onfi_version >= 21 && + (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { + + /* + * The nand_flash_detect_ext_param_page() uses the + * Change Read Column command which maybe not supported + * by the chip->cmdfunc. So try to update the chip->cmdfunc + * now. We do not replace user supplied command function. + */ + if (mtd->writesize > 512 && chip->cmdfunc == nand_command) + chip->cmdfunc = nand_command_lp; + + /* The Extended Parameter Page is supported since ONFI 2.1. */ + if (nand_flash_detect_ext_param_page(mtd, chip, p)) + pr_warn("Failed to detect ONFI extended param page\n"); + } else { + pr_warn("Could not retrieve ONFI ECC requirements\n"); + } + + if (p->jedec_id == NAND_MFR_MICRON) + nand_onfi_detect_micron(chip, p); - pr_info("ONFI flash detected\n"); return 1; } #else -static inline int nand_flash_detect_onfi(struct mtd_info *mtd, - struct nand_chip *chip, +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, int *busw) { return 0; } #endif +/* + * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. + */ +static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, + int *busw) +{ + struct nand_jedec_params *p = &chip->jedec_params; + struct jedec_ecc_info *ecc; + int val; + int i, j; + + /* Try JEDEC for unknown chip or LP */ + chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); + if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || + chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || + chip->read_byte(mtd) != 'C') + return 0; + + chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); + for (i = 0; i < 3; i++) { + for (j = 0; j < sizeof(*p); j++) + ((uint8_t *)p)[j] = chip->read_byte(mtd); + + if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == + le16_to_cpu(p->crc)) + break; + } + + if (i == 3) { + pr_err("Could not find valid JEDEC parameter page; aborting\n"); + return 0; + } + + /* Check version */ + val = le16_to_cpu(p->revision); + if (val & (1 << 2)) + chip->jedec_version = 10; + else if (val & (1 << 1)) + chip->jedec_version = 1; /* vendor specific version */ + + if (!chip->jedec_version) { + pr_info("unsupported JEDEC version: %d\n", val); + return 0; + } + + sanitize_string(p->manufacturer, sizeof(p->manufacturer)); + sanitize_string(p->model, sizeof(p->model)); + if (!mtd->name) + mtd->name = p->model; + + mtd->writesize = le32_to_cpu(p->byte_per_page); + + /* Please reference to the comment for nand_flash_detect_onfi. */ + mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); + mtd->erasesize *= mtd->writesize; + + mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); + + /* Please reference to the comment for nand_flash_detect_onfi. */ + chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); + chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; + chip->bits_per_cell = p->bits_per_cell; + + if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) + *busw = NAND_BUSWIDTH_16; + else + *busw = 0; + + /* ECC info */ + ecc = &p->ecc_info[0]; + + if (ecc->codeword_size >= 9) { + chip->ecc_strength_ds = ecc->ecc_bits; + chip->ecc_step_ds = 1 << ecc->codeword_size; + } else { + pr_warn("Invalid codeword size\n"); + } + + return 1; +} + /* * nand_id_has_period - Check if an ID string has a given wraparound period * @id_data: the ID string @@ -2645,7 +3488,7 @@ static inline int nand_flash_detect_onfi(struct mtd_info *mtd, * * Check if an ID string is repeated within a given sequence of bytes at * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a - * period of 2). This is a helper function for nand_id_len(). Returns non-zero + * period of 3). This is a helper function for nand_id_len(). Returns non-zero * if the repetition has a period of @period; otherwise, returns zero. */ static int nand_id_has_period(u8 *id_data, int arrlen, int period) @@ -2696,6 +3539,16 @@ static int nand_id_len(u8 *id_data, int arrlen) return arrlen; } +/* Extract the bits of per cell from the 3rd byte of the extended ID */ +static int nand_get_bits_per_cell(u8 cellinfo) +{ + int bits; + + bits = cellinfo & NAND_CI_CELLTYPE_MSK; + bits >>= NAND_CI_CELLTYPE_SHIFT; + return bits + 1; +} + /* * Many new NAND share similar device ID codes, which represent the size of the * chip. The rest of the parameters must be decoded according to generic or @@ -2706,7 +3559,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ - chip->cellinfo = id_data[2]; + chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); /* The 4th id byte is the important one */ extid = id_data[3]; @@ -2722,8 +3575,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * ID to decide what to do. */ if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && - (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && - id_data[5] != 0x00) { + !nand_is_slc(chip) && id_data[5] != 0x00) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; @@ -2745,9 +3597,12 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->oobsize = 512; break; case 6: - default: /* Other cases are "reserved" (unknown) */ mtd->oobsize = 640; break; + case 7: + default: /* Other cases are "reserved" (unknown) */ + mtd->oobsize = 1024; + break; } extid >>= 2; /* Calc blocksize */ @@ -2755,7 +3610,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, (((extid >> 1) & 0x04) | (extid & 0x03)); *busw = 0; } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && - (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { + !nand_is_slc(chip)) { unsigned int tmp; /* Calc pagesize */ @@ -2808,16 +3663,32 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, extid >>= 2; /* Get buswidth information */ *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + + /* + * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per + * 512B page. For Toshiba SLC, we decode the 5th/6th byte as + * follows: + * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, + * 110b -> 24nm + * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC + */ + if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && + nand_is_slc(chip) && + (id_data[5] & 0x7) == 0x6 /* 24nm */ && + !(id_data[4] & 0x80) /* !BENAND */) { + mtd->oobsize = 32 * mtd->writesize >> 9; + } + } } - /* +/* * Old devices have chip data hardcoded in the device ID table. nand_decode_id * decodes a matching ID table entry and assigns the MTD size parameters for * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - const struct nand_flash_dev *type, u8 id_data[8], + struct nand_flash_dev *type, u8 id_data[8], int *busw) { int maf_id = id_data[0]; @@ -2827,6 +3698,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->oobsize = mtd->writesize / 32; *busw = type->options & NAND_BUSWIDTH_16; + /* All legacy ID NAND are small-page, SLC */ + chip->bits_per_cell = 1; + /* * Check for Spansion/AMD ID + repeating 5th, 6th byte since * some Spansion chips have erasesize that conflicts with size @@ -2841,7 +3715,7 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, } } - /* +/* * Set the bad block marker/indicator (BBM/BBI) patterns according to some * heuristic patterns using various detected parameters (e.g., manufacturer, * page size, cell-type information). @@ -2863,11 +3737,11 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && + if (!nand_is_slc(chip) && (maf_id == NAND_MFR_SAMSUNG || maf_id == NAND_MFR_HYNIX)) chip->bbt_options |= NAND_BBT_SCANLASTPAGE; - else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && + else if ((nand_is_slc(chip) && (maf_id == NAND_MFR_SAMSUNG || maf_id == NAND_MFR_HYNIX || maf_id == NAND_MFR_TOSHIBA || @@ -2878,16 +3752,48 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } +static inline bool is_full_id_nand(struct nand_flash_dev *type) +{ + return type->id_len; +} + +static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, + struct nand_flash_dev *type, u8 *id_data, int *busw) +{ +#ifndef __UBOOT__ + if (!strncmp(type->id, id_data, type->id_len)) { +#else + if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { +#endif + mtd->writesize = type->pagesize; + mtd->erasesize = type->erasesize; + mtd->oobsize = type->oobsize; + + chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->chipsize = (uint64_t)type->chipsize << 20; + chip->options |= type->options; + chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); + chip->ecc_step_ds = NAND_ECC_STEP(type); + + *busw = type->options & NAND_BUSWIDTH_16; + + if (!mtd->name) + mtd->name = type->name; + + return true; + } + return false; +} + /* * Get the flash and manufacturer id and lookup if the type is supported. */ -static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, +static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, struct nand_chip *chip, - int busw, int *maf_id, int *dev_id, - const struct nand_flash_dev *type) + struct nand_flash_dev *type) { - const char *name; + int busw; int i, maf_idx; u8 id_data[8]; @@ -2921,8 +3827,7 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, id_data[i] = chip->read_byte(mtd); if (id_data[0] != *maf_id || id_data[1] != *dev_id) { - pr_info("%s: second ID read did not match " - "%02x,%02x against %02x,%02x\n", __func__, + pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", *maf_id, *dev_id, id_data[0], id_data[1]); return ERR_PTR(-ENODEV); } @@ -2930,15 +3835,24 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type) type = nand_flash_ids; - for (; type->name != NULL; type++) - if (*dev_id == type->id) - break; + for (; type->name != NULL; type++) { + if (is_full_id_nand(type)) { + if (find_full_id_nand(mtd, chip, type, id_data, &busw)) + goto ident_done; + } else if (*dev_id == type->dev_id) { + break; + } + } chip->onfi_version = 0; if (!type->name || !type->pagesize) { /* Check is chip is ONFI compliant */ if (nand_flash_detect_onfi(mtd, chip, &busw)) goto ident_done; + + /* Check if the chip is JEDEC compliant */ + if (nand_flash_detect_jedec(mtd, chip, &busw)) + goto ident_done; } if (!type->name) @@ -2958,7 +3872,7 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, } else { nand_decode_id(mtd, chip, type, id_data, &busw); } - /* Get chip options, preserve non chip based options */ + /* Get chip options */ chip->options |= type->options; /* @@ -2975,15 +3889,19 @@ ident_done: break; } - /* - * Check, if buswidth is correct. Hardware drivers should set - * chip correct! - */ - if (busw != (chip->options & NAND_BUSWIDTH_16)) { - pr_info("NAND device: Manufacturer ID:" - " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, - *dev_id, nand_manuf_ids[maf_idx].name, mtd->name); - pr_warn("NAND bus width %d instead %d bit\n", + if (chip->options & NAND_BUSWIDTH_AUTO) { + WARN_ON(chip->options & NAND_BUSWIDTH_16); + chip->options |= busw; + nand_set_defaults(chip, busw); + } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { + /* + * Check, if buswidth is correct. Hardware drivers should set + * chip correct! + */ + pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", + *maf_id, *dev_id); + pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); + pr_warn("bus width %d instead %d bit\n", (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, busw ? 16 : 8); return ERR_PTR(-EINVAL); @@ -3006,28 +3924,40 @@ ident_done: } chip->badblockbits = 8; - - /* Check for AND chips with 4 page planes */ - if (chip->options & NAND_4PAGE_ARRAY) - chip->erase_cmd = multi_erase_cmd; - else - chip->erase_cmd = single_erase_cmd; + chip->erase_cmd = single_erase_cmd; /* Do not replace user supplied command function! */ if (mtd->writesize > 512 && chip->cmdfunc == nand_command) chip->cmdfunc = nand_command_lp; - name = type->name; + pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", + *maf_id, *dev_id); + #ifdef CONFIG_SYS_NAND_ONFI_DETECTION if (chip->onfi_version) - name = chip->onfi_params.model; + pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + chip->onfi_params.model); + else if (chip->jedec_version) + pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + chip->jedec_params.model); + else + pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + type->name); +#else + if (chip->jedec_version) + pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + chip->jedec_params.model); + else + pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + type->name); + + pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + type->name); #endif - pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s)," - " page size: %d, OOB size: %d\n", - *maf_id, *dev_id, nand_manuf_ids[maf_idx].name, - name, - mtd->writesize, mtd->oobsize); + pr_info("%dMiB, %s, page size: %d, OOB size: %d\n", + (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", + mtd->writesize, mtd->oobsize); return type; } @@ -3043,29 +3973,28 @@ ident_done: * The mtd->owner field must be set to the module of the caller. */ int nand_scan_ident(struct mtd_info *mtd, int maxchips, - const struct nand_flash_dev *table) + struct nand_flash_dev *table) { - int i, busw, nand_maf_id, nand_dev_id; + int i, nand_maf_id, nand_dev_id; struct nand_chip *chip = mtd->priv; - const struct nand_flash_dev *type; + struct nand_flash_dev *type; - /* Get buswidth to select the correct functions */ - busw = chip->options & NAND_BUSWIDTH_16; /* Set the default functions */ - nand_set_defaults(chip, busw); + nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); /* Read the flash type */ - type = nand_get_flash_type(mtd, chip, busw, - &nand_maf_id, &nand_dev_id, table); + type = nand_get_flash_type(mtd, chip, &nand_maf_id, + &nand_dev_id, table); if (IS_ERR(type)) { -#ifndef CONFIG_SYS_NAND_QUIET_TEST - pr_warn("No NAND device found\n"); -#endif + if (!(chip->options & NAND_SCAN_SILENT_NODEV)) + pr_warn("No NAND device found\n"); chip->select_chip(mtd, -1); return PTR_ERR(type); } + chip->select_chip(mtd, -1); + /* Check for a chip array */ for (i = 1; i < maxchips; i++) { chip->select_chip(mtd, i); @@ -3075,12 +4004,16 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); /* Read manufacturer and device IDs */ if (nand_maf_id != chip->read_byte(mtd) || - nand_dev_id != chip->read_byte(mtd)) + nand_dev_id != chip->read_byte(mtd)) { + chip->select_chip(mtd, -1); break; + } + chip->select_chip(mtd, -1); } + #ifdef DEBUG if (i > 1) - pr_info("%d NAND chips detected\n", i); + pr_info("%d chips detected\n", i); #endif /* Store the number of chips and calc total size for mtd */ @@ -3089,6 +4022,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, return 0; } +EXPORT_SYMBOL(nand_scan_ident); /** @@ -3103,16 +4037,31 @@ int nand_scan_tail(struct mtd_info *mtd) { int i; struct nand_chip *chip = mtd->priv; + struct nand_ecc_ctrl *ecc = &chip->ecc; + struct nand_buffers *nbuf; /* New bad blocks should be marked in OOB, flash-based BBT, or both */ BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && !(chip->bbt_options & NAND_BBT_USE_FLASH)); - if (!(chip->options & NAND_OWN_BUFFERS)) - chip->buffers = memalign(ARCH_DMA_MINALIGN, - sizeof(*chip->buffers)); - if (!chip->buffers) - return chip->options & NAND_OWN_BUFFERS ? -EINVAL : -ENOMEM; + if (!(chip->options & NAND_OWN_BUFFERS)) { +#ifndef __UBOOT__ + nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize + + mtd->oobsize * 3, GFP_KERNEL); + if (!nbuf) + return -ENOMEM; + nbuf->ecccalc = (uint8_t *)(nbuf + 1); + nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; + nbuf->databuf = nbuf->ecccode + mtd->oobsize; +#else + nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL); +#endif + + chip->buffers = nbuf; + } else { + if (!chip->buffers) + return -ENOMEM; + } /* Set the internal oob buffer location, just after the page data */ chip->oob_poi = chip->buffers->databuf + mtd->writesize; @@ -3120,94 +4069,91 @@ int nand_scan_tail(struct mtd_info *mtd) /* * If no default placement scheme is given, select an appropriate one. */ - if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) { + if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { switch (mtd->oobsize) { case 8: - chip->ecc.layout = &nand_oob_8; + ecc->layout = &nand_oob_8; break; case 16: - chip->ecc.layout = &nand_oob_16; + ecc->layout = &nand_oob_16; break; case 64: - chip->ecc.layout = &nand_oob_64; + ecc->layout = &nand_oob_64; break; case 128: - chip->ecc.layout = &nand_oob_128; + ecc->layout = &nand_oob_128; break; default: pr_warn("No oob scheme defined for oobsize %d\n", mtd->oobsize); + BUG(); } } if (!chip->write_page) chip->write_page = nand_write_page; - /* set for ONFI nand */ - if (!chip->onfi_set_features) - chip->onfi_set_features = nand_onfi_set_features; - if (!chip->onfi_get_features) - chip->onfi_get_features = nand_onfi_get_features; - /* * Check ECC mode, default to software if 3byte/512byte hardware ECC is * selected and we have 256 byte pagesize fallback to software ECC */ - switch (chip->ecc.mode) { + switch (ecc->mode) { case NAND_ECC_HW_OOB_FIRST: /* Similar to NAND_ECC_HW, but a separate read_page handle */ - if (!chip->ecc.calculate || !chip->ecc.correct || - !chip->ecc.hwctl) { + if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { pr_warn("No ECC functions supplied; " "hardware ECC not possible\n"); BUG(); } - if (!chip->ecc.read_page) - chip->ecc.read_page = nand_read_page_hwecc_oob_first; + if (!ecc->read_page) + ecc->read_page = nand_read_page_hwecc_oob_first; case NAND_ECC_HW: /* Use standard hwecc read page function? */ - if (!chip->ecc.read_page) - chip->ecc.read_page = nand_read_page_hwecc; - if (!chip->ecc.write_page) - chip->ecc.write_page = nand_write_page_hwecc; - if (!chip->ecc.read_page_raw) - chip->ecc.read_page_raw = nand_read_page_raw; - if (!chip->ecc.write_page_raw) - chip->ecc.write_page_raw = nand_write_page_raw; - if (!chip->ecc.read_oob) - chip->ecc.read_oob = nand_read_oob_std; - if (!chip->ecc.write_oob) - chip->ecc.write_oob = nand_write_oob_std; + if (!ecc->read_page) + ecc->read_page = nand_read_page_hwecc; + if (!ecc->write_page) + ecc->write_page = nand_write_page_hwecc; + if (!ecc->read_page_raw) + ecc->read_page_raw = nand_read_page_raw; + if (!ecc->write_page_raw) + ecc->write_page_raw = nand_write_page_raw; + if (!ecc->read_oob) + ecc->read_oob = nand_read_oob_std; + if (!ecc->write_oob) + ecc->write_oob = nand_write_oob_std; + if (!ecc->read_subpage) + ecc->read_subpage = nand_read_subpage; + if (!ecc->write_subpage) + ecc->write_subpage = nand_write_subpage_hwecc; case NAND_ECC_HW_SYNDROME: - if ((!chip->ecc.calculate || !chip->ecc.correct || - !chip->ecc.hwctl) && - (!chip->ecc.read_page || - chip->ecc.read_page == nand_read_page_hwecc || - !chip->ecc.write_page || - chip->ecc.write_page == nand_write_page_hwecc)) { + if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && + (!ecc->read_page || + ecc->read_page == nand_read_page_hwecc || + !ecc->write_page || + ecc->write_page == nand_write_page_hwecc)) { pr_warn("No ECC functions supplied; " "hardware ECC not possible\n"); BUG(); } /* Use standard syndrome read/write page function? */ - if (!chip->ecc.read_page) - chip->ecc.read_page = nand_read_page_syndrome; - if (!chip->ecc.write_page) - chip->ecc.write_page = nand_write_page_syndrome; - if (!chip->ecc.read_page_raw) - chip->ecc.read_page_raw = nand_read_page_raw_syndrome; - if (!chip->ecc.write_page_raw) - chip->ecc.write_page_raw = nand_write_page_raw_syndrome; - if (!chip->ecc.read_oob) - chip->ecc.read_oob = nand_read_oob_syndrome; - if (!chip->ecc.write_oob) - chip->ecc.write_oob = nand_write_oob_syndrome; - - if (mtd->writesize >= chip->ecc.size) { - if (!chip->ecc.strength) { + if (!ecc->read_page) + ecc->read_page = nand_read_page_syndrome; + if (!ecc->write_page) + ecc->write_page = nand_write_page_syndrome; + if (!ecc->read_page_raw) + ecc->read_page_raw = nand_read_page_raw_syndrome; + if (!ecc->write_page_raw) + ecc->write_page_raw = nand_write_page_raw_syndrome; + if (!ecc->read_oob) + ecc->read_oob = nand_read_oob_syndrome; + if (!ecc->write_oob) + ecc->write_oob = nand_write_oob_syndrome; + + if (mtd->writesize >= ecc->size) { + if (!ecc->strength) { pr_warn("Driver must set ecc.strength when using hardware ECC\n"); BUG(); } @@ -3215,111 +4161,109 @@ int nand_scan_tail(struct mtd_info *mtd) } pr_warn("%d byte HW ECC not possible on " "%d byte page size, fallback to SW ECC\n", - chip->ecc.size, mtd->writesize); - chip->ecc.mode = NAND_ECC_SOFT; + ecc->size, mtd->writesize); + ecc->mode = NAND_ECC_SOFT; case NAND_ECC_SOFT: - chip->ecc.calculate = nand_calculate_ecc; - chip->ecc.correct = nand_correct_data; - chip->ecc.read_page = nand_read_page_swecc; - chip->ecc.read_subpage = nand_read_subpage; - chip->ecc.write_page = nand_write_page_swecc; - chip->ecc.read_page_raw = nand_read_page_raw; - chip->ecc.write_page_raw = nand_write_page_raw; - chip->ecc.read_oob = nand_read_oob_std; - chip->ecc.write_oob = nand_write_oob_std; - if (!chip->ecc.size) - chip->ecc.size = 256; - chip->ecc.bytes = 3; - chip->ecc.strength = 1; + ecc->calculate = nand_calculate_ecc; + ecc->correct = nand_correct_data; + ecc->read_page = nand_read_page_swecc; + ecc->read_subpage = nand_read_subpage; + ecc->write_page = nand_write_page_swecc; + ecc->read_page_raw = nand_read_page_raw; + ecc->write_page_raw = nand_write_page_raw; + ecc->read_oob = nand_read_oob_std; + ecc->write_oob = nand_write_oob_std; + if (!ecc->size) + ecc->size = 256; + ecc->bytes = 3; + ecc->strength = 1; break; case NAND_ECC_SOFT_BCH: if (!mtd_nand_has_bch()) { - pr_warn("CONFIG_MTD_ECC_BCH not enabled\n"); - return -EINVAL; + pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); + BUG(); } - chip->ecc.calculate = nand_bch_calculate_ecc; - chip->ecc.correct = nand_bch_correct_data; - chip->ecc.read_page = nand_read_page_swecc; - chip->ecc.read_subpage = nand_read_subpage; - chip->ecc.write_page = nand_write_page_swecc; - chip->ecc.read_page_raw = nand_read_page_raw; - chip->ecc.write_page_raw = nand_write_page_raw; - chip->ecc.read_oob = nand_read_oob_std; - chip->ecc.write_oob = nand_write_oob_std; + ecc->calculate = nand_bch_calculate_ecc; + ecc->correct = nand_bch_correct_data; + ecc->read_page = nand_read_page_swecc; + ecc->read_subpage = nand_read_subpage; + ecc->write_page = nand_write_page_swecc; + ecc->read_page_raw = nand_read_page_raw; + ecc->write_page_raw = nand_write_page_raw; + ecc->read_oob = nand_read_oob_std; + ecc->write_oob = nand_write_oob_std; /* * Board driver should supply ecc.size and ecc.bytes values to * select how many bits are correctable; see nand_bch_init() * for details. Otherwise, default to 4 bits for large page * devices. */ - if (!chip->ecc.size && (mtd->oobsize >= 64)) { - chip->ecc.size = 512; - chip->ecc.bytes = 7; + if (!ecc->size && (mtd->oobsize >= 64)) { + ecc->size = 512; + ecc->bytes = 7; } - chip->ecc.priv = nand_bch_init(mtd, - chip->ecc.size, - chip->ecc.bytes, - &chip->ecc.layout); - if (!chip->ecc.priv) + ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, + &ecc->layout); + if (!ecc->priv) { pr_warn("BCH ECC initialization failed!\n"); - chip->ecc.strength = - chip->ecc.bytes * 8 / fls(8 * chip->ecc.size); + BUG(); + } + ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size); break; case NAND_ECC_NONE: pr_warn("NAND_ECC_NONE selected by board driver. " - "This is not recommended !!\n"); - chip->ecc.read_page = nand_read_page_raw; - chip->ecc.write_page = nand_write_page_raw; - chip->ecc.read_oob = nand_read_oob_std; - chip->ecc.read_page_raw = nand_read_page_raw; - chip->ecc.write_page_raw = nand_write_page_raw; - chip->ecc.write_oob = nand_write_oob_std; - chip->ecc.size = mtd->writesize; - chip->ecc.bytes = 0; + "This is not recommended!\n"); + ecc->read_page = nand_read_page_raw; + ecc->write_page = nand_write_page_raw; + ecc->read_oob = nand_read_oob_std; + ecc->read_page_raw = nand_read_page_raw; + ecc->write_page_raw = nand_write_page_raw; + ecc->write_oob = nand_write_oob_std; + ecc->size = mtd->writesize; + ecc->bytes = 0; + ecc->strength = 0; break; default: - pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode); + pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); BUG(); } /* For many systems, the standard OOB write also works for raw */ - if (!chip->ecc.read_oob_raw) - chip->ecc.read_oob_raw = chip->ecc.read_oob; - if (!chip->ecc.write_oob_raw) - chip->ecc.write_oob_raw = chip->ecc.write_oob; + if (!ecc->read_oob_raw) + ecc->read_oob_raw = ecc->read_oob; + if (!ecc->write_oob_raw) + ecc->write_oob_raw = ecc->write_oob; /* * The number of bytes available for a client to place data into * the out of band area. */ - chip->ecc.layout->oobavail = 0; - for (i = 0; chip->ecc.layout->oobfree[i].length - && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) - chip->ecc.layout->oobavail += - chip->ecc.layout->oobfree[i].length; - mtd->oobavail = chip->ecc.layout->oobavail; + ecc->layout->oobavail = 0; + for (i = 0; ecc->layout->oobfree[i].length + && i < ARRAY_SIZE(ecc->layout->oobfree); i++) + ecc->layout->oobavail += ecc->layout->oobfree[i].length; + mtd->oobavail = ecc->layout->oobavail; /* * Set the number of read / write steps for one page depending on ECC * mode. */ - chip->ecc.steps = mtd->writesize / chip->ecc.size; - if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { + ecc->steps = mtd->writesize / ecc->size; + if (ecc->steps * ecc->size != mtd->writesize) { pr_warn("Invalid ECC parameters\n"); pr_warn("steps=%d size=%d writesize=%d\n", chip->ecc.steps, chip->ecc.size, mtd->writesize); BUG(); } - chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; + ecc->total = ecc->steps * ecc->bytes; /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ - if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && - !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { - switch (chip->ecc.steps) { + if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { + switch (ecc->steps) { case 2: mtd->subpage_sft = 1; break; @@ -3335,36 +4279,42 @@ int nand_scan_tail(struct mtd_info *mtd) /* Initialize state */ chip->state = FL_READY; - /* De-select the device */ - chip->select_chip(mtd, -1); - /* Invalidate the pagebuffer reference */ chip->pagebuf = -1; /* Large page NAND with SOFT_ECC should support subpage reads */ - if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) + if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) chip->options |= NAND_SUBPAGE_READ; /* Fill in remaining MTD driver data */ - mtd->type = MTD_NANDFLASH; + mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : MTD_CAP_NANDFLASH; mtd->_erase = nand_erase; +#ifndef __UBOOT__ mtd->_point = NULL; mtd->_unpoint = NULL; +#endif mtd->_read = nand_read; mtd->_write = nand_write; + mtd->_panic_write = panic_nand_write; mtd->_read_oob = nand_read_oob; mtd->_write_oob = nand_write_oob; mtd->_sync = nand_sync; mtd->_lock = NULL; mtd->_unlock = NULL; +#ifndef __UBOOT__ + mtd->_suspend = nand_suspend; + mtd->_resume = nand_resume; +#endif mtd->_block_isbad = nand_block_isbad; mtd->_block_markbad = nand_block_markbad; + mtd->writebufsize = mtd->writesize; /* propagate ecc info to mtd_info */ - mtd->ecclayout = chip->ecc.layout; - mtd->ecc_strength = chip->ecc.strength; + mtd->ecclayout = ecc->layout; + mtd->ecc_strength = ecc->strength; + mtd->ecc_step_size = ecc->size; /* * Initialize bitflip_threshold to its default prior scan_bbt() call. * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be @@ -3373,12 +4323,21 @@ int nand_scan_tail(struct mtd_info *mtd) if (!mtd->bitflip_threshold) mtd->bitflip_threshold = mtd->ecc_strength; - /* Check, if we should skip the bad block table scan */ - if (chip->options & NAND_SKIP_BBTSCAN) - chip->options |= NAND_BBT_SCANNED; - return 0; } +EXPORT_SYMBOL(nand_scan_tail); + +/* + * is_module_text_address() isn't exported, and it's mostly a pointless + * test if this is a module _anyway_ -- they'd have to try _really_ hard + * to call us from in-kernel code if the core NAND support is modular. + */ +#ifdef MODULE +#define caller_is_module() (1) +#else +#define caller_is_module() \ + is_module_text_address((unsigned long)__builtin_return_address(0)) +#endif /** * nand_scan - [NAND Interface] Scan for the NAND device @@ -3394,12 +4353,20 @@ int nand_scan(struct mtd_info *mtd, int maxchips) { int ret; + /* Many callers got this wrong, so check for it for a while... */ + if (!mtd->owner && caller_is_module()) { + pr_crit("%s called with NULL mtd->owner!\n", __func__); + BUG(); + } + ret = nand_scan_ident(mtd, maxchips, NULL); if (!ret) ret = nand_scan_tail(mtd); return ret; } +EXPORT_SYMBOL(nand_scan); +#ifndef __UBOOT__ /** * nand_release - [NAND Interface] Free resources held by the NAND device * @mtd: MTD device structure @@ -3411,10 +4378,7 @@ void nand_release(struct mtd_info *mtd) if (chip->ecc.mode == NAND_ECC_SOFT_BCH) nand_bch_free((struct nand_bch_control *)chip->ecc.priv); -#ifdef CONFIG_MTD_PARTITIONS - /* Deregister partitions */ - del_mtd_partitions(mtd); -#endif + mtd_device_unregister(mtd); /* Free bad block table memory */ kfree(chip->bbt); @@ -3426,3 +4390,24 @@ void nand_release(struct mtd_info *mtd) & NAND_BBT_DYNAMICSTRUCT) kfree(chip->badblock_pattern); } +EXPORT_SYMBOL_GPL(nand_release); + +static int __init nand_base_init(void) +{ + led_trigger_register_simple("nand-disk", &nand_led_trigger); + return 0; +} + +static void __exit nand_base_exit(void) +{ + led_trigger_unregister_simple(nand_led_trigger); +} +#endif + +module_init(nand_base_init); +module_exit(nand_base_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Steven J. Hill "); +MODULE_AUTHOR("Thomas Gleixner "); +MODULE_DESCRIPTION("Generic NAND flash driver code"); diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 8ef58451d5..cf4a82d93a 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -59,17 +59,54 @@ * */ -#include -#include -#include +#ifndef __UBOOT__ +#include +#include #include #include #include #include #include +#include +#include +#include #include +#else +#include +#include +#include + + #include + #include + #include + #include + #include + #include +#endif + +#define BBT_BLOCK_GOOD 0x00 +#define BBT_BLOCK_WORN 0x01 +#define BBT_BLOCK_RESERVED 0x02 +#define BBT_BLOCK_FACTORY_BAD 0x03 -#include +#define BBT_ENTRY_MASK 0x03 +#define BBT_ENTRY_SHIFT 2 + +static int nand_update_bbt(struct mtd_info *mtd, loff_t offs); + +static inline uint8_t bbt_get_entry(struct nand_chip *chip, int block) +{ + uint8_t entry = chip->bbt[block >> BBT_ENTRY_SHIFT]; + entry >>= (block & BBT_ENTRY_MASK) * 2; + return entry & BBT_ENTRY_MASK; +} + +static inline void bbt_mark_entry(struct nand_chip *chip, int block, + uint8_t mark) +{ + uint8_t msk = (mark & BBT_ENTRY_MASK) << ((block & BBT_ENTRY_MASK) * 2); + chip->bbt[block >> BBT_ENTRY_SHIFT] |= msk; +} static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) { @@ -86,33 +123,17 @@ static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) * @td: search pattern descriptor * * Check for a pattern at the given place. Used to search bad block tables and - * good / bad block identifiers. If the SCAN_EMPTY option is set then check, if - * all bytes except the pattern area contain 0xff. + * good / bad block identifiers. */ static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td) { - int end = 0; - uint8_t *p = buf; - if (td->options & NAND_BBT_NO_OOB) return check_pattern_no_oob(buf, td); - end = paglen + td->offs; - if (td->options & NAND_BBT_SCANEMPTY) - if (memchr_inv(p, 0xff, end)) - return -1; - p += end; - /* Compare the pattern */ - if (memcmp(p, td->pattern, td->len)) + if (memcmp(buf + paglen + td->offs, td->pattern, td->len)) return -1; - if (td->options & NAND_BBT_SCANEMPTY) { - p += td->len; - end += td->len; - if (memchr_inv(p, 0xff, len - end)) - return -1; - } return 0; } @@ -159,7 +180,7 @@ static u32 add_marker_len(struct nand_bbt_descr *td) * @page: the starting page * @num: the number of bbt descriptors to read * @td: the bbt describtion table - * @offs: offset in the memory table + * @offs: block number offset in the table * * Read the bad block table starting from page. */ @@ -209,25 +230,33 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, /* Analyse data */ for (i = 0; i < len; i++) { uint8_t dat = buf[i]; - for (j = 0; j < 8; j += bits, act += 2) { + for (j = 0; j < 8; j += bits, act++) { uint8_t tmp = (dat >> j) & msk; if (tmp == msk) continue; if (reserved_block_code && (tmp == reserved_block_code)) { pr_info("nand_read_bbt: reserved block at 0x%012llx\n", - (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift); - this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); + (loff_t)(offs + act) << + this->bbt_erase_shift); + bbt_mark_entry(this, offs + act, + BBT_BLOCK_RESERVED); mtd->ecc_stats.bbtblocks++; continue; } - pr_info("nand_read_bbt: Bad block at 0x%012llx\n", - (loff_t)((offs << 2) + (act >> 1)) - << this->bbt_erase_shift); + /* + * Leave it for now, if it's matured we can + * move this message to pr_debug. + */ + pr_info("nand_read_bbt: bad block at 0x%012llx\n", + (loff_t)(offs + act) << + this->bbt_erase_shift); /* Factory marked bad or worn out? */ if (tmp == 0) - this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); + bbt_mark_entry(this, offs + act, + BBT_BLOCK_FACTORY_BAD); else - this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06); + bbt_mark_entry(this, offs + act, + BBT_BLOCK_WORN); mtd->ecc_stats.badblocks++; } } @@ -262,7 +291,7 @@ static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc td, offs); if (res) return res; - offs += this->chipsize >> (this->bbt_erase_shift + 2); + offs += this->chipsize >> this->bbt_erase_shift; } } else { res = read_bbt(mtd, buf, td->pages[0], @@ -396,25 +425,6 @@ static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, } } -/* Scan a given block full */ -static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd, - loff_t offs, uint8_t *buf, size_t readlen, - int scanlen, int numpages) -{ - int ret, j; - - ret = scan_read_oob(mtd, buf, offs, readlen); - /* Ignore ECC errors when checking for BBM */ - if (ret && !mtd_is_bitflip_or_eccerr(ret)) - return ret; - - for (j = 0; j < numpages; j++, buf += scanlen) { - if (check_pattern(buf, scanlen, mtd->writesize, bd)) - return 1; - } - return 0; -} - /* Scan a given block partially */ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd, loff_t offs, uint8_t *buf, int numpages) @@ -461,36 +471,19 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip) { struct nand_chip *this = mtd->priv; - int i, numblocks, numpages, scanlen; + int i, numblocks, numpages; int startblock; loff_t from; - size_t readlen; pr_info("Scanning device for bad blocks\n"); - if (bd->options & NAND_BBT_SCANALLPAGES) - numpages = 1 << (this->bbt_erase_shift - this->page_shift); - else if (bd->options & NAND_BBT_SCAN2NDPAGE) + if (bd->options & NAND_BBT_SCAN2NDPAGE) numpages = 2; else numpages = 1; - if (!(bd->options & NAND_BBT_SCANEMPTY)) { - /* We need only read few bytes from the OOB area */ - scanlen = 0; - readlen = bd->len; - } else { - /* Full page content should be read */ - scanlen = mtd->writesize + mtd->oobsize; - readlen = numpages * mtd->writesize; - } - if (chip == -1) { - /* - * Note that numblocks is 2 * (real numblocks) here, see i+=2 - * below as it makes shifting and masking less painful - */ - numblocks = mtd->size >> (this->bbt_erase_shift - 1); + numblocks = mtd->size >> this->bbt_erase_shift; startblock = 0; from = 0; } else { @@ -499,37 +492,31 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, chip + 1, this->numchips); return -EINVAL; } - numblocks = this->chipsize >> (this->bbt_erase_shift - 1); + numblocks = this->chipsize >> this->bbt_erase_shift; startblock = chip * numblocks; numblocks += startblock; - from = (loff_t)startblock << (this->bbt_erase_shift - 1); + from = (loff_t)startblock << this->bbt_erase_shift; } if (this->bbt_options & NAND_BBT_SCANLASTPAGE) from += mtd->erasesize - (mtd->writesize * numpages); - for (i = startblock; i < numblocks;) { + for (i = startblock; i < numblocks; i++) { int ret; BUG_ON(bd->options & NAND_BBT_NO_OOB); - if (bd->options & NAND_BBT_SCANALLPAGES) - ret = scan_block_full(mtd, bd, from, buf, readlen, - scanlen, numpages); - else - ret = scan_block_fast(mtd, bd, from, buf, numpages); - + ret = scan_block_fast(mtd, bd, from, buf, numpages); if (ret < 0) return ret; if (ret) { - this->bbt[i >> 3] |= 0x03 << (i & 0x6); + bbt_mark_entry(this, i, BBT_BLOCK_FACTORY_BAD); pr_warn("Bad eraseblock %d at 0x%012llx\n", - i >> 1, (unsigned long long)from); + i, (unsigned long long)from); mtd->ecc_stats.badblocks++; } - i += 2; from += (1 << this->bbt_erase_shift); } return 0; @@ -554,7 +541,11 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr { struct nand_chip *this = mtd->priv; int i, chips; +#ifndef __UBOOT__ + int bits, startblock, block, dir; +#else int startblock, block, dir; +#endif int scanlen = mtd->writesize + mtd->oobsize; int bbtblocks; int blocktopage = this->bbt_erase_shift - this->page_shift; @@ -578,6 +569,11 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr bbtblocks = mtd->size >> this->bbt_erase_shift; } +#ifndef __UBOOT__ + /* Number of bits for each erase block in the bbt */ + bits = td->options & NAND_BBT_NRBITS_MSK; +#endif + for (i = 0; i < chips; i++) { /* Reset version information */ td->version[i] = 0; @@ -606,8 +602,8 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr if (td->pages[i] == -1) pr_warn("Bad block table not found for chip %d\n", i); else - pr_info("Bad block table found at page %d, version 0x%02X\n", td->pages[i], - td->version[i]); + pr_info("Bad block table found at page %d, version " + "0x%02X\n", td->pages[i], td->version[i]); } return 0; } @@ -649,9 +645,9 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, { struct nand_chip *this = mtd->priv; struct erase_info einfo; - int i, j, res, chip = 0; + int i, res, chip = 0; int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; - int nrchips, bbtoffs, pageoffs, ooboffs; + int nrchips, pageoffs, ooboffs; uint8_t msk[4]; uint8_t rcode = td->reserved_block_code; size_t retlen, len = 0; @@ -707,10 +703,9 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, for (i = 0; i < td->maxblocks; i++) { int block = startblock + dir * i; /* Check, if the block is bad */ - switch ((this->bbt[block >> 2] >> - (2 * (block & 0x03))) & 0x03) { - case 0x01: - case 0x03: + switch (bbt_get_entry(this, block)) { + case BBT_BLOCK_WORN: + case BBT_BLOCK_FACTORY_BAD: continue; } page = block << @@ -742,8 +737,6 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, default: return -EINVAL; } - bbtoffs = chip * (numblocks >> 2); - to = ((loff_t)page) << this->page_shift; /* Must we save the block contents? */ @@ -808,16 +801,12 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, buf[ooboffs + td->veroffs] = td->version[chip]; /* Walk through the memory table */ - for (i = 0; i < numblocks;) { + for (i = 0; i < numblocks; i++) { uint8_t dat; - dat = this->bbt[bbtoffs + (i >> 2)]; - for (j = 0; j < 4; j++, i++) { - int sftcnt = (i << (3 - sft)) & sftmsk; - /* Do not store the reserved bbt blocks! */ - buf[offs + (i >> sft)] &= - ~(msk[dat & 0x03] << sftcnt); - dat >>= 2; - } + int sftcnt = (i << (3 - sft)) & sftmsk; + dat = bbt_get_entry(this, chip * numblocks + i); + /* Do not store the reserved bbt blocks! */ + buf[offs + (i >> sft)] &= ~(msk[dat] << sftcnt); } memset(&einfo, 0, sizeof(einfo)); @@ -859,7 +848,6 @@ static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *b { struct nand_chip *this = mtd->priv; - bd->options &= ~NAND_BBT_SCANEMPTY; return create_bbt(mtd, this->buffers->databuf, bd, -1); } @@ -1003,7 +991,7 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) { struct nand_chip *this = mtd->priv; int i, j, chips, block, nrblocks, update; - uint8_t oldval, newval; + uint8_t oldval; /* Do we have a bbt per chip? */ if (td->options & NAND_BBT_PERCHIP) { @@ -1020,12 +1008,12 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) if (td->pages[i] == -1) continue; block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift); - block <<= 1; - oldval = this->bbt[(block >> 3)]; - newval = oldval | (0x2 << (block & 0x06)); - this->bbt[(block >> 3)] = newval; - if ((oldval != newval) && td->reserved_block_code) - nand_update_bbt(mtd, (loff_t)block << (this->bbt_erase_shift - 1)); + oldval = bbt_get_entry(this, block); + bbt_mark_entry(this, block, BBT_BLOCK_RESERVED); + if ((oldval != BBT_BLOCK_RESERVED) && + td->reserved_block_code) + nand_update_bbt(mtd, (loff_t)block << + this->bbt_erase_shift); continue; } update = 0; @@ -1033,14 +1021,12 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) block = ((i + 1) * nrblocks) - td->maxblocks; else block = i * nrblocks; - block <<= 1; for (j = 0; j < td->maxblocks; j++) { - oldval = this->bbt[(block >> 3)]; - newval = oldval | (0x2 << (block & 0x06)); - this->bbt[(block >> 3)] = newval; - if (oldval != newval) + oldval = bbt_get_entry(this, block); + bbt_mark_entry(this, block, BBT_BLOCK_RESERVED); + if (oldval != BBT_BLOCK_RESERVED) update = 1; - block += 2; + block++; } /* * If we want reserved blocks to be recorded to flash, and some @@ -1048,7 +1034,8 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) * bbts. This should only happen once. */ if (update && td->reserved_block_code) - nand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1)); + nand_update_bbt(mtd, (loff_t)(block - 1) << + this->bbt_erase_shift); } } @@ -1174,13 +1161,13 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) } /** - * nand_update_bbt - [NAND Interface] update bad block table(s) + * nand_update_bbt - update bad block table(s) * @mtd: MTD device structure * @offs: the offset of the newly marked block * * The function updates the bad block table(s). */ -int nand_update_bbt(struct mtd_info *mtd, loff_t offs) +static int nand_update_bbt(struct mtd_info *mtd, loff_t offs) { struct nand_chip *this = mtd->priv; int len, res = 0; @@ -1234,15 +1221,6 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs) */ static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; -static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 }; - -static struct nand_bbt_descr agand_flashbased = { - .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, - .offs = 0x20, - .len = 6, - .pattern = scan_agand_pattern -}; - /* Generic flash bbt descriptors */ static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; @@ -1327,22 +1305,6 @@ int nand_default_bbt(struct mtd_info *mtd) { struct nand_chip *this = mtd->priv; - /* - * Default for AG-AND. We must use a flash based bad block table as the - * devices have factory marked _good_ blocks. Erasing those blocks - * leads to loss of the good / bad information, so we _must_ store this - * information in a good / bad table during startup. - */ - if (this->options & NAND_IS_AND) { - /* Use the default pattern descriptors */ - if (!this->bbt_td) { - this->bbt_td = &bbt_main_descr; - this->bbt_md = &bbt_mirror_descr; - } - this->bbt_options |= NAND_BBT_USE_FLASH; - return nand_scan_bbt(mtd, &agand_flashbased); - } - /* Is a flash based bad block table requested? */ if (this->bbt_options & NAND_BBT_USE_FLASH) { /* Use the default pattern descriptors */ @@ -1375,23 +1337,46 @@ int nand_default_bbt(struct mtd_info *mtd) int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) { struct nand_chip *this = mtd->priv; - int block; - uint8_t res; + int block, res; - /* Get block number * 2 */ - block = (int)(offs >> (this->bbt_erase_shift - 1)); - res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; + block = (int)(offs >> this->bbt_erase_shift); + res = bbt_get_entry(this, block); - MTDDEBUG(MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n", - (unsigned int)offs, block >> 1, res); + pr_debug("nand_isbad_bbt(): bbt info for offs 0x%08x: " + "(block %d) 0x%02x\n", + (unsigned int)offs, block, res); - switch ((int)res) { - case 0x00: + switch (res) { + case BBT_BLOCK_GOOD: return 0; - case 0x01: + case BBT_BLOCK_WORN: return 1; - case 0x02: + case BBT_BLOCK_RESERVED: return allowbbt ? 0 : 1; } return 1; } + +/** + * nand_markbad_bbt - [NAND Interface] Mark a block bad in the BBT + * @mtd: MTD device structure + * @offs: offset of the bad block + */ +int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs) +{ + struct nand_chip *this = mtd->priv; + int block, ret = 0; + + block = (int)(offs >> this->bbt_erase_shift); + + /* Mark bad block in memory */ + bbt_mark_entry(this, block, BBT_BLOCK_WORN); + + /* Update flash-based bad block table */ + if (this->bbt_options & NAND_BBT_USE_FLASH) + ret = nand_update_bbt(mtd, offs); + + return ret; +} + +EXPORT_SYMBOL(nand_scan_bbt); diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index f856778b5e..9ed05778d3 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -8,165 +8,174 @@ * published by the Free Software Foundation. * */ - +#ifndef __UBOOT__ +#include +#include +#else #include #include -/* -* Chip ID list -* -* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size, -* options -* -* Pagesize; 0, 256, 512 -* 0 get this information from the extended chip ID -+ 256 256 Byte page size -* 512 512 Byte page size -*/ -const struct nand_flash_dev nand_flash_ids[] = { - -#ifdef CONFIG_MTD_NAND_MUSEUM_IDS - {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, - {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, - {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, - {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, - {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, - {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, - {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0}, - {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0}, - {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0}, - {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0}, - - {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0}, - {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0}, - {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16}, - {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16}, #endif +#include - {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0}, - {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0}, - {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16}, - {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16}, - - {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0}, - {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0}, - {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16}, - {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16}, - - {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0}, - {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0}, - {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16}, - {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16}, +#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS +#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) - {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0}, - {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0}, - {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0}, - {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16}, - {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16}, - {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16}, - {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16}, +#define SP_OPTIONS NAND_NEED_READRDY +#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16) - {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, +/* + * The chip ID list: + * name, device ID, page size, chip size in MiB, eraseblock size, options + * + * If page size and eraseblock size are 0, the sizes are taken from the + * extended chip ID. + */ +struct nand_flash_dev nand_flash_ids[] = { +#ifdef CONFIG_MTD_NAND_MUSEUM_IDS + LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), + + LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS), +#endif + /* + * Some incompatible NAND chips share device ID's and so must be + * listed by full ID. We list them first so that we can easily identify + * the most specific match. + */ + {"TC58NVG2S0F 4G 3.3V 8-bit", + { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} }, + SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) }, + {"TC58NVG3S0F 8G 3.3V 8-bit", + { .id = {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} }, + SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) }, + {"TC58NVG5D2 32G 3.3V 8-bit", + { .id = {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0x09, 0x00} }, + SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, + {"TC58NVG6D2 64G 3.3V 8-bit", + { .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} }, + SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, + {"SDTNRGAMA 64G 3.3V 8-bit", + { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, + SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, + + LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS), + + LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16), + LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16), + + LEGACY_ID_NAND("NAND 32MiB 1,8V 8-bit", 0x35, 32, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 32MiB 3,3V 8-bit", 0x75, 32, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 32MiB 1,8V 16-bit", 0x45, 32, SZ_16K, SP_OPTIONS16), + LEGACY_ID_NAND("NAND 32MiB 3,3V 16-bit", 0x55, 32, SZ_16K, SP_OPTIONS16), + + LEGACY_ID_NAND("NAND 64MiB 1,8V 8-bit", 0x36, 64, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 64MiB 3,3V 8-bit", 0x76, 64, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 64MiB 1,8V 16-bit", 0x46, 64, SZ_16K, SP_OPTIONS16), + LEGACY_ID_NAND("NAND 64MiB 3,3V 16-bit", 0x56, 64, SZ_16K, SP_OPTIONS16), + + LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x78, 128, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x39, 128, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 128MiB 3,3V 8-bit", 0x79, 128, SZ_16K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x72, 128, SZ_16K, SP_OPTIONS16), + LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x49, 128, SZ_16K, SP_OPTIONS16), + LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x74, 128, SZ_16K, SP_OPTIONS16), + LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x59, 128, SZ_16K, SP_OPTIONS16), + + LEGACY_ID_NAND("NAND 256MiB 3,3V 8-bit", 0x71, 256, SZ_16K, SP_OPTIONS), /* - * These are the new chips with large page size. The pagesize and the - * erasesize is determined from the extended id bytes + * These are the new chips with large page size. Their page size and + * eraseblock size are determined from the extended ID bytes. */ -#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS -#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) /* 512 Megabit */ - {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS}, - {"NAND 64MiB 1,8V 8-bit", 0xA0, 0, 64, 0, LP_OPTIONS}, - {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS}, - {"NAND 64MiB 3,3V 8-bit", 0xD0, 0, 64, 0, LP_OPTIONS}, - {"NAND 64MiB 3,3V 8-bit", 0xF0, 0, 64, 0, LP_OPTIONS}, - {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16}, - {"NAND 64MiB 1,8V 16-bit", 0xB0, 0, 64, 0, LP_OPTIONS16}, - {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16}, - {"NAND 64MiB 3,3V 16-bit", 0xC0, 0, 64, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 64MiB 1,8V 8-bit", 0xA2, 64, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 64MiB 1,8V 8-bit", 0xA0, 64, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xF2, 64, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xD0, 64, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 64MiB 3,3V 8-bit", 0xF0, 64, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 64MiB 1,8V 16-bit", 0xB2, 64, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 64MiB 1,8V 16-bit", 0xB0, 64, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 64MiB 3,3V 16-bit", 0xC2, 64, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 64MiB 3,3V 16-bit", 0xC0, 64, LP_OPTIONS16), /* 1 Gigabit */ - {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS}, - {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS}, - {"NAND 128MiB 3,3V 8-bit", 0xD1, 0, 128, 0, LP_OPTIONS}, - {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16}, - {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16}, - {"NAND 128MiB 1,8V 16-bit", 0xAD, 0, 128, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 128MiB 1,8V 8-bit", 0xA1, 128, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 128MiB 3,3V 8-bit", 0xF1, 128, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 128MiB 3,3V 8-bit", 0xD1, 128, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 128MiB 1,8V 16-bit", 0xB1, 128, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 128MiB 3,3V 16-bit", 0xC1, 128, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 128MiB 1,8V 16-bit", 0xAD, 128, LP_OPTIONS16), /* 2 Gigabit */ - {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS}, - {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS}, - {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16}, - {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 256MiB 1,8V 8-bit", 0xAA, 256, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 256MiB 3,3V 8-bit", 0xDA, 256, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 256MiB 1,8V 16-bit", 0xBA, 256, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 256MiB 3,3V 16-bit", 0xCA, 256, LP_OPTIONS16), /* 4 Gigabit */ - {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS}, - {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS}, - {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16}, - {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 512MiB 1,8V 8-bit", 0xAC, 512, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 512MiB 3,3V 8-bit", 0xDC, 512, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 512MiB 1,8V 16-bit", 0xBC, 512, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 512MiB 3,3V 16-bit", 0xCC, 512, LP_OPTIONS16), /* 8 Gigabit */ - {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS}, - {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS}, - {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16}, - {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 1GiB 1,8V 8-bit", 0xA3, 1024, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 1GiB 3,3V 8-bit", 0xD3, 1024, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 1GiB 1,8V 16-bit", 0xB3, 1024, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 1GiB 3,3V 16-bit", 0xC3, 1024, LP_OPTIONS16), /* 16 Gigabit */ - {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS}, - {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS}, - {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, - {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 2GiB 1,8V 8-bit", 0xA5, 2048, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 2GiB 3,3V 8-bit", 0xD5, 2048, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 2GiB 1,8V 16-bit", 0xB5, 2048, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 2GiB 3,3V 16-bit", 0xC5, 2048, LP_OPTIONS16), /* 32 Gigabit */ - {"NAND 4GiB 1,8V 8-bit", 0xA7, 0, 4096, 0, LP_OPTIONS}, - {"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 4096, 0, LP_OPTIONS}, - {"NAND 4GiB 1,8V 16-bit", 0xB7, 0, 4096, 0, LP_OPTIONS16}, - {"NAND 4GiB 3,3V 16-bit", 0xC7, 0, 4096, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 4GiB 1,8V 8-bit", 0xA7, 4096, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 4GiB 3,3V 8-bit", 0xD7, 4096, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 4GiB 1,8V 16-bit", 0xB7, 4096, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 4GiB 3,3V 16-bit", 0xC7, 4096, LP_OPTIONS16), /* 64 Gigabit */ - {"NAND 8GiB 1,8V 8-bit", 0xAE, 0, 8192, 0, LP_OPTIONS}, - {"NAND 8GiB 3,3V 8-bit", 0xDE, 0, 8192, 0, LP_OPTIONS}, - {"NAND 8GiB 1,8V 16-bit", 0xBE, 0, 8192, 0, LP_OPTIONS16}, - {"NAND 8GiB 3,3V 16-bit", 0xCE, 0, 8192, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 8GiB 1,8V 8-bit", 0xAE, 8192, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 8GiB 3,3V 8-bit", 0xDE, 8192, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 8GiB 1,8V 16-bit", 0xBE, 8192, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 8GiB 3,3V 16-bit", 0xCE, 8192, LP_OPTIONS16), /* 128 Gigabit */ - {"NAND 16GiB 1,8V 8-bit", 0x1A, 0, 16384, 0, LP_OPTIONS}, - {"NAND 16GiB 3,3V 8-bit", 0x3A, 0, 16384, 0, LP_OPTIONS}, - {"NAND 16GiB 1,8V 16-bit", 0x2A, 0, 16384, 0, LP_OPTIONS16}, - {"NAND 16GiB 3,3V 16-bit", 0x4A, 0, 16384, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 16GiB 1,8V 8-bit", 0x1A, 16384, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 16GiB 3,3V 8-bit", 0x3A, 16384, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 16GiB 1,8V 16-bit", 0x2A, 16384, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 16GiB 3,3V 16-bit", 0x4A, 16384, LP_OPTIONS16), /* 256 Gigabit */ - {"NAND 32GiB 1,8V 8-bit", 0x1C, 0, 32768, 0, LP_OPTIONS}, - {"NAND 32GiB 3,3V 8-bit", 0x3C, 0, 32768, 0, LP_OPTIONS}, - {"NAND 32GiB 1,8V 16-bit", 0x2C, 0, 32768, 0, LP_OPTIONS16}, - {"NAND 32GiB 3,3V 16-bit", 0x4C, 0, 32768, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 32GiB 1,8V 8-bit", 0x1C, 32768, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 32GiB 3,3V 8-bit", 0x3C, 32768, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 32GiB 1,8V 16-bit", 0x2C, 32768, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 32GiB 3,3V 16-bit", 0x4C, 32768, LP_OPTIONS16), /* 512 Gigabit */ - {"NAND 64GiB 1,8V 8-bit", 0x1E, 0, 65536, 0, LP_OPTIONS}, - {"NAND 64GiB 3,3V 8-bit", 0x3E, 0, 65536, 0, LP_OPTIONS}, - {"NAND 64GiB 1,8V 16-bit", 0x2E, 0, 65536, 0, LP_OPTIONS16}, - {"NAND 64GiB 3,3V 16-bit", 0x4E, 0, 65536, 0, LP_OPTIONS16}, + EXTENDED_ID_NAND("NAND 64GiB 1,8V 8-bit", 0x1E, 65536, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 64GiB 3,3V 8-bit", 0x3E, 65536, LP_OPTIONS), + EXTENDED_ID_NAND("NAND 64GiB 1,8V 16-bit", 0x2E, 65536, LP_OPTIONS16), + EXTENDED_ID_NAND("NAND 64GiB 3,3V 16-bit", 0x4E, 65536, LP_OPTIONS16), - /* - * Renesas AND 1 Gigabit. Those chips do not support extended id and - * have a strange page/block layout ! The chosen minimum erasesize is - * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page - * planes 1 block = 2 pages, but due to plane arrangement the blocks - * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would - * increase the eraseblock size so we chose a combined one which can be - * erased in one go There are more speed improvements for reads and - * writes possible, but not implemented now - */ - {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, - NAND_IS_AND | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH}, - - {NULL,} + {NULL} }; -/* -* Manufacturer ID list -*/ -const struct nand_manufacturers nand_manuf_ids[] = { +/* Manufacturer IDs */ +struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_TOSHIBA, "Toshiba"}, {NAND_MFR_SAMSUNG, "Samsung"}, {NAND_MFR_FUJITSU, "Fujitsu"}, @@ -178,6 +187,14 @@ const struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, + {NAND_MFR_SANDISK, "SanDisk"}, + {NAND_MFR_INTEL, "Intel"}, {0x0, "Unknown"} }; +EXPORT_SYMBOL(nand_manuf_ids); +EXPORT_SYMBOL(nand_flash_ids); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Thomas Gleixner "); +MODULE_DESCRIPTION("Nand device & manufacturer IDs"); diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index 664dfc5dd9..24cbac80a2 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -78,7 +78,7 @@ static int nand_command(int block, int page, uint32_t offs, } /* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; /* Begin command latch cycle */ diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 1e0210a9a4..afdd160d81 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -14,7 +14,9 @@ * Copyright (C) 2008 Nokia Corporation: drop_ffs() function by * Artem Bityutskiy from mtd-utils * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright 2010 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0 */ #include @@ -51,7 +53,6 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) struct jffs2_unknown_node cleanmarker; erase_info_t erase; unsigned long erase_length, erased_length; /* in blocks */ - int bbtest = 1; int result; int percent_complete = -1; const char *mtd_device = meminfo->name; @@ -90,6 +91,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) kfree(chip->bbt); } chip->bbt = NULL; + chip->options &= ~NAND_BBT_SCANNED; } for (erased_length = 0; @@ -102,7 +104,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) puts("Size of erase exceeds limit\n"); return -EFBIG; } - if (!opts->scrub && bbtest) { + if (!opts->scrub) { int ret = mtd_block_isbad(meminfo, erase.addr); if (ret > 0) { if (!opts->quiet) @@ -143,8 +145,8 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) ops.mode = MTD_OPS_AUTO_OOB; result = mtd_write_oob(meminfo, - erase.addr, - &ops); + erase.addr, + &ops); if (result != 0) { printf("\n%s: MTD writeoob failure: %d\n", mtd_device, result); @@ -178,14 +180,14 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) if (!opts->quiet) printf("\n"); - if (opts->scrub) - chip->scan_bbt(meminfo); - return 0; } #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK +#define NAND_CMD_LOCK_TIGHT 0x2c +#define NAND_CMD_LOCK_STATUS 0x7a + /****************************************************************************** * Support for locking / unlocking operations of some NAND devices *****************************************************************************/ @@ -314,7 +316,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, int page; struct nand_chip *chip = mtd->priv; - debug("nand_unlock%s: start: %08llx, length: %d!\n", + debug("nand_unlock%s: start: %08llx, length: %zd!\n", allexcept ? " (allexcept)" : "", start, length); /* select the NAND device */ diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 34688e9bef..265959502d 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -104,7 +104,6 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) *p++ = in_be32((u32 *)(base + NDFC_DATA)); } -#ifndef CONFIG_NAND_SPL /* * Don't use these speedup functions in NAND boot image, since the image * has to fit into 4kByte. @@ -119,6 +118,7 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len out_be32((u32 *)(base + NDFC_DATA), *p++); } +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; @@ -131,6 +131,7 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len return 0; } +#endif /* * Read a byte from the NDFC. @@ -148,8 +149,6 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd) } -#endif /* #ifndef CONFIG_NAND_SPL */ - void board_nand_select_device(struct nand_chip *nand, int chip) { /* @@ -207,21 +206,13 @@ int board_nand_init(struct nand_chip *nand) nand->options |= NAND_BUSWIDTH_16; #endif -#ifndef CONFIG_NAND_SPL nand->write_buf = ndfc_write_buf; +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) nand->verify_buf = ndfc_verify_buf; +#endif nand->read_byte = ndfc_read_byte; chip++; -#else - /* - * Setup EBC (CS0 only right now) - */ - mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG); - - mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); - mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); -#endif return 0; } diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c new file mode 100644 index 0000000000..d963e6c07c --- /dev/null +++ b/drivers/mtd/nand/omap_elm.c @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, + * Mansoor Ahamed + * + * BCH Error Location Module (ELM) support. + * + * NOTE: + * 1. Supports only continuous mode. Dont see need for page mode in uboot + * 2. Supports only syndrome polynomial 0. i.e. poly local variable is + * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial + * sets in uboot + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define DRIVER_NAME "omap-elm" +#define ELM_DEFAULT_POLY (0) + +struct elm *elm_cfg; + +/** + * elm_load_syndromes - Load BCH syndromes based on bch_type selection + * @syndrome: BCH syndrome + * @bch_type: BCH4/BCH8/BCH16 + * @poly: Syndrome Polynomial set to use + */ +static void elm_load_syndromes(u8 *syndrome, enum bch_level bch_type, u8 poly) +{ + u32 *ptr; + u32 val; + + /* reg 0 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0]; + val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) | + (syndrome[3] << 24); + writel(val, ptr); + /* reg 1 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1]; + val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) | + (syndrome[7] << 24); + writel(val, ptr); + + if (bch_type == BCH_8_BIT || bch_type == BCH_16_BIT) { + /* reg 2 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; + val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | + (syndrome[11] << 24); + writel(val, ptr); + /* reg 3 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3]; + val = syndrome[12] | (syndrome[13] << 8) | + (syndrome[14] << 16) | (syndrome[15] << 24); + writel(val, ptr); + } + + if (bch_type == BCH_16_BIT) { + /* reg 4 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; + val = syndrome[16] | (syndrome[17] << 8) | + (syndrome[18] << 16) | (syndrome[19] << 24); + writel(val, ptr); + + /* reg 5 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5]; + val = syndrome[20] | (syndrome[21] << 8) | + (syndrome[22] << 16) | (syndrome[23] << 24); + writel(val, ptr); + + /* reg 6 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]; + val = syndrome[24] | (syndrome[25] << 8) | + (syndrome[26] << 16) | (syndrome[27] << 24); + writel(val, ptr); + } +} + +/** + * elm_check_errors - Check for BCH errors and return error locations + * @syndrome: BCH syndrome + * @bch_type: BCH4/BCH8/BCH16 + * @error_count: Returns number of errrors in the syndrome + * @error_locations: Returns error locations (in decimal) in this array + * + * Check the provided syndrome for BCH errors and return error count + * and locations in the array passed. Returns -1 if error is not correctable, + * else returns 0 + */ +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, + u32 *error_locations) +{ + u8 poly = ELM_DEFAULT_POLY; + s8 i; + u32 location_status; + + elm_load_syndromes(syndrome, bch_type, poly); + + /* start processing */ + writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) + | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID), + &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); + + /* wait for processing to complete */ + while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1) + ; + /* clear status */ + writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)), + &elm_cfg->irqstatus); + + /* check if correctable */ + location_status = readl(&elm_cfg->error_location[poly].location_status); + if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) { + printf("%s: uncorrectable ECC errors\n", DRIVER_NAME); + return -EBADMSG; + } + + /* get error count */ + *error_count = readl(&elm_cfg->error_location[poly].location_status) & + ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; + + for (i = 0; i < *error_count; i++) { + error_locations[i] = + readl(&elm_cfg->error_location[poly].error_location_x[i]); + } + + return 0; +} + + +/** + * elm_config - Configure ELM module + * @level: 4 / 8 / 16 bit BCH + * + * Configure ELM module based on BCH level. + * Set mode as continuous mode. + * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used. + * Also, the mode is set only for syndrome 0 + */ +int elm_config(enum bch_level level) +{ + u32 val; + u8 poly = ELM_DEFAULT_POLY; + u32 buffer_size = 0x7FF; + + /* config size and level */ + val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK; + val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) & + ELM_LOCATION_CONFIG_ECC_SIZE_MASK); + writel(val, &elm_cfg->location_config); + + /* config continous mode */ + /* enable interrupt generation for syndrome polynomial set */ + writel((readl(&elm_cfg->irqenable) | (0x1 << poly)), + &elm_cfg->irqenable); + /* set continuous mode for the syndrome polynomial set */ + writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)), + &elm_cfg->page_ctrl); + + return 0; +} + +/** + * elm_reset - Do a soft reset of ELM + * + * Perform a soft reset of ELM and return after reset is done. + */ +void elm_reset(void) +{ + /* initiate reset */ + writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET), + &elm_cfg->sysconfig); + + /* wait for reset complete and normal operation */ + while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) != + ELM_SYSSTATUS_RESETDONE) + ; +} + +/** + * elm_init - Initialize ELM module + * + * Initialize ELM support. Currently it does only base address init + * and ELM reset. + */ +void elm_init(void) +{ + elm_cfg = (struct elm *)ELM_BASE; + elm_reset(); +} diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 5af213c758..9c56bd3a55 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -9,21 +9,38 @@ #include #include #include -#include -#include +#include #include #include #include #include -#ifdef CONFIG_AM33XX -#include +#include + +#define BADBLOCK_MARKER_LENGTH 2 +#define SECTOR_BYTES 512 +#define ECCCLEAR (0x1 << 8) +#define ECCRESULTREG1 (0x1 << 0) +/* 4 bit padding to make byte aligned, 56 = 52 + 4 */ +#define BCH4_BIT_PAD 4 + +#ifdef CONFIG_BCH +static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, + 0x97, 0x79, 0xe5, 0x24, 0xb5}; #endif +static uint8_t cs_next; +static __maybe_unused struct nand_ecclayout omap_ecclayout; -static uint8_t cs; -static __maybe_unused struct nand_ecclayout hw_nand_oob = - GPMC_NAND_HW_ECC_LAYOUT; -static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob = - GPMC_NAND_HW_BCH8_ECC_LAYOUT; +/* + * Driver configurations + */ +struct omap_nand_info { + struct bch_control *control; + enum omap_ecc ecc_scheme; + int cs; +}; + +/* We are wasting a bit of memory but al least we are safe */ +static struct omap_nand_info omap_nand_info[GPMC_MAX_CS]; static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE; @@ -217,6 +234,8 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, uint32_t ctrl) { register struct nand_chip *this = mtd->priv; + struct omap_nand_info *info = this->priv; + int cs = info->cs; /* * Point the IO_ADDR to DATA and ADDRESS registers instead @@ -238,29 +257,11 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, writeb(cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SPL_BUILD /* Check wait pin as dev ready indicator */ -int omap_spl_dev_ready(struct mtd_info *mtd) +static int omap_dev_ready(struct mtd_info *mtd) { return readl(&gpmc_cfg->status) & (1 << 8); } -#endif - -/* - * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in - * GPMC controller - * @mtd: MTD device structure - * - */ -static void __maybe_unused omap_hwecc_init(struct nand_chip *chip) -{ - /* - * Init ECC Control Register - * Clear all ECC | Enable Reg1 - */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config); -} /* * gen_true_ecc - This function will generate true ECC value, which @@ -342,8 +343,86 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, } /* - * omap_calculate_ecc - Generate non-inverted ECC bytes. - * + * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +__maybe_unused +static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) +{ + struct nand_chip *nand = mtd->priv; + struct omap_nand_info *info = nand->priv; + unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; + unsigned int ecc_algo = 0; + unsigned int bch_type = 0; + unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00; + u32 ecc_size_config_val = 0; + u32 ecc_config_val = 0; + int cs = info->cs; + + /* configure GPMC for specific ecc-scheme */ + switch (info->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_SW: + return; + case OMAP_ECC_HAM1_CODE_HW: + ecc_algo = 0x0; + bch_type = 0x0; + bch_wrapmode = 0x00; + eccsize0 = 0xFF; + eccsize1 = 0xFF; + break; + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: + case OMAP_ECC_BCH8_CODE_HW: + ecc_algo = 0x1; + bch_type = 0x1; + if (mode == NAND_ECC_WRITE) { + bch_wrapmode = 0x01; + eccsize0 = 0; /* extra bits in nibbles per sector */ + eccsize1 = 28; /* OOB bits in nibbles per sector */ + } else { + bch_wrapmode = 0x01; + eccsize0 = 26; /* ECC bits in nibbles per sector */ + eccsize1 = 2; /* non-ECC bits in nibbles per sector */ + } + break; + case OMAP_ECC_BCH16_CODE_HW: + ecc_algo = 0x1; + bch_type = 0x2; + if (mode == NAND_ECC_WRITE) { + bch_wrapmode = 0x01; + eccsize0 = 0; /* extra bits in nibbles per sector */ + eccsize1 = 52; /* OOB bits in nibbles per sector */ + } else { + bch_wrapmode = 0x01; + eccsize0 = 52; /* ECC bits in nibbles per sector */ + eccsize1 = 0; /* non-ECC bits in nibbles per sector */ + } + break; + default: + return; + } + /* Clear ecc and enable bits */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + /* Configure ecc size for BCH */ + ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12); + writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config); + + /* Configure device details for BCH engine */ + ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */ + (bch_type << 12) | /* BCH4/BCH8/BCH16 */ + (bch_wrapmode << 8) | /* wrap mode */ + (dev_width << 7) | /* bus width */ + (0x0 << 4) | /* number of sectors */ + (cs << 1) | /* ECC CS */ + (0x1)); /* enable ECC */ + writel(ecc_config_val, &gpmc_cfg->ecc_config); +} + +/* + * omap_calculate_ecc - Read ECC result + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer * Using noninverted ECC can be considered ugly since writing a blank * page ie. padding will clear the ECC bytes. This is no problem as * long nobody is trying to write data on the seemingly unused page. @@ -352,428 +431,309 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC * is used, the result of read will be 0x0 while the ECC offsets of the * spare area will be 0xFF which will result in an ECC mismatch. - * @mtd: MTD structure - * @dat: unused - * @ecc_code: ecc_code buffer - */ -static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd, - const uint8_t *dat, uint8_t *ecc_code) -{ - u_int32_t val; - - /* Start Reading from HW ECC1_Result = 0x200 */ - val = readl(&gpmc_cfg->ecc1_result); - - ecc_code[0] = val & 0xFF; - ecc_code[1] = (val >> 16) & 0xFF; - ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - writel(0x000, &gpmc_cfg->ecc_config); - - return 0; -} - -/* - * omap_enable_ecc - This function enables the hardware ecc functionality - * @mtd: MTD device structure - * @mode: Read/Write mode */ -static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) +static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) { struct nand_chip *chip = mtd->priv; - uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; - - switch (mode) { - case NAND_ECC_READ: - case NAND_ECC_WRITE: - /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - - /* - * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes - * tell all regs to generate size0 sized regs - * we just have a single ECC engine for all CS - */ - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, - &gpmc_cfg->ecc_size_config); - val = (dev_width << 7) | (cs << 1) | (1 << 0); - writel(val, &gpmc_cfg->ecc_config); + struct omap_nand_info *info = chip->priv; + uint32_t *ptr, val = 0; + int8_t i = 0, j; + + switch (info->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_HW: + val = readl(&gpmc_cfg->ecc1_result); + ecc_code[0] = val & 0xFF; + ecc_code[1] = (val >> 16) & 0xFF; + ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); break; - default: - printf("Error: Unrecognized Mode[%d]!\n", mode); - } -} - -/* - * Generic BCH interface - */ -struct nand_bch_priv { - uint8_t mode; - uint8_t type; - uint8_t nibbles; - struct bch_control *control; -}; - -/* bch types */ -#define ECC_BCH4 0 -#define ECC_BCH8 1 -#define ECC_BCH16 2 - -/* GPMC ecc engine settings */ -#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ -#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ - -/* BCH nibbles for diff bch levels */ -#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1) -#define ECC_BCH4_NIBBLES 13 -#define ECC_BCH8_NIBBLES 26 -#define ECC_BCH16_NIBBLES 52 - -/* - * This can be a single instance cause all current users have only one NAND - * with nearly the same setup (BCH8, some with ELM and others with sw BCH - * library). - * When some users with other BCH strength will exists this have to change! - */ -static __maybe_unused struct nand_bch_priv bch_priv = { - .mode = NAND_ECC_HW_BCH, - .type = ECC_BCH8, - .nibbles = ECC_BCH8_NIBBLES, - .control = NULL, -}; - -/* - * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in - * GPMC controller - * @mtd: MTD device structure - * @mode: Read/Write mode - */ -__maybe_unused -static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) -{ - uint32_t val; - uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; -#ifdef CONFIG_AM33XX - uint32_t unused_length = 0; +#ifdef CONFIG_BCH + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: #endif - uint32_t wr_mode = BCH_WRAPMODE_6; - struct nand_bch_priv *bch = chip->priv; - - /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - -#ifdef CONFIG_AM33XX - wr_mode = BCH_WRAPMODE_1; - - switch (bch->nibbles) { - case ECC_BCH4_NIBBLES: - unused_length = 3; - break; - case ECC_BCH8_NIBBLES: - unused_length = 2; + case OMAP_ECC_BCH8_CODE_HW: + ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; + val = readl(ptr); + ecc_code[i++] = (val >> 0) & 0xFF; + ptr--; + for (j = 0; j < 3; j++) { + val = readl(ptr); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + ptr--; + } break; - case ECC_BCH16_NIBBLES: - unused_length = 0; + case OMAP_ECC_BCH16_CODE_HW: + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]); + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + for (j = 3; j >= 0; j--) { + val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j] + ); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + } break; + default: + return -EINVAL; } - - /* - * This is ecc_size_config for ELM mode. - * Here we are using different settings for read and write access and - * also depending on BCH strength. - */ - switch (mode) { - case NAND_ECC_WRITE: - /* write access only setup eccsize1 config */ - val = ((unused_length + bch->nibbles) << 22); + /* ECC scheme specific syndrome customizations */ + switch (info->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_HW: break; +#ifdef CONFIG_BCH + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: - case NAND_ECC_READ: - default: - /* - * by default eccsize0 selected for ecc1resultsize - * eccsize0 config. - */ - val = (bch->nibbles << 12); - /* eccsize1 config */ - val |= (unused_length << 22); + for (i = 0; i < chip->ecc.bytes; i++) + *(ecc_code + i) = *(ecc_code + i) ^ + bch8_polynomial[i]; break; - } -#else - /* - * This ecc_size_config setting is for BCH sw library. - * - * Note: we only support BCH8 currently with BCH sw library! - * Should be really easy to adopt to BCH4, however some omap3 have - * flaws with BCH4. - * - * Here we are using wrapping mode 6 both for reading and writing, with: - * size0 = 0 (no additional protected byte in spare area) - * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) - */ - val = (32 << 22) | (0 << 12); #endif - /* ecc size configuration */ - writel(val, &gpmc_cfg->ecc_size_config); - - /* - * Configure the ecc engine in gpmc - * We assume 512 Byte sector pages for access to NAND. - */ - val = 1 << 16; /* select BCH mode */ - val |= bch->type << 12; /* setup BCH type */ - val |= wr_mode << 8; /* setup wrapping mode */ - val |= dev_width << 7; /* setup device width (16 or 8 bit) */ - val |= (chip->ecc.size / 512 - 1) << 4; /* set ECC size */ - val |= cs << 1; /* setup chip select to work on */ - val |= 1 << 0; /* enable ECC engine */ - - debug("set ECC_CONFIG=0x%08x\n", val); - writel(val, &gpmc_cfg->ecc_config); -} - -/* - * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality - * @mtd: MTD device structure - * @mode: Read/Write mode - */ -__maybe_unused -static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode) -{ - struct nand_chip *chip = mtd->priv; - - omap_hwecc_init_bch(chip, mode); -} - -/* - * omap_ecc_disable - Disable H/W ECC calculation - * - * @mtd: MTD device structure - */ -static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd) -{ - writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config); + case OMAP_ECC_BCH8_CODE_HW: + ecc_code[chip->ecc.bytes - 1] = 0x00; + break; + case OMAP_ECC_BCH16_CODE_HW: + break; + default: + return -EINVAL; + } + return 0; } +#ifdef CONFIG_NAND_OMAP_ELM /* - * BCH8 support (needs ELM and thus AM33xx-only) - */ -#ifdef CONFIG_AM33XX -/* - * omap_read_bch8_result - Read BCH result for BCH8 level - * - * @mtd: MTD device structure - * @big_endian: When set read register 3 first - * @ecc_code: Read syndrome from BCH result registers - */ -static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, - uint8_t *ecc_code) + * omap_reverse_list - re-orders list elements in reverse order [internal] + * @list: pointer to start of list + * @length: length of list +*/ +static void omap_reverse_list(u8 *list, unsigned int length) { - uint32_t *ptr; - int8_t i = 0, j, k; - struct nand_chip *chip = mtd->priv; - int num_steps = chip->ecc.size / 512; - - for (k = 0; k < num_steps; k++) { - if (big_endian) { - ptr = &gpmc_cfg->bch_result_0_3[k].bch_result_x[3]; - ecc_code[i++] = readl(ptr) & 0xFF; - ptr--; - for (j = 0; j < 3; j++) { - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; - ecc_code[i++] = readl(ptr) & 0xFF; - ptr--; - } - } else { - ptr = &gpmc_cfg->bch_result_0_3[k].bch_result_x[0]; - for (j = 0; j < 3; j++) { - ecc_code[i++] = readl(ptr) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ptr++; - } - ecc_code[i++] = readl(ptr) & 0xFF; - } - ecc_code[i++] = 0; /* 14th byte is always zero */ + unsigned int i, j; + unsigned int half_length = length / 2; + u8 tmp; + for (i = 0, j = length - 1; i < half_length; i++, j--) { + tmp = list[i]; + list[i] = list[j]; + list[j] = tmp; } } /* - * omap_rotate_ecc_bch - Rotate the syndrome bytes + * omap_correct_data_bch - Compares the ecc read from nand spare area + * with ECC registers values and corrects one bit error if it has occured * * @mtd: MTD device structure - * @calc_ecc: ECC read from ECC registers - * @syndrome: Rotated syndrome will be returned in this array + * @dat: page data + * @read_ecc: ecc read from nand flash (ignored) + * @calc_ecc: ecc read from ECC registers * + * @return 0 if data is OK or corrected, else returns -1 */ -static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, - uint8_t *syndrome) +static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, uint8_t *calc_ecc) { struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t n_bytes = 0; - int8_t i, j; + struct omap_nand_info *info = chip->priv; + struct nand_ecc_ctrl *ecc = &chip->ecc; + uint32_t error_count = 0, error_max; + uint32_t error_loc[ELM_MAX_ERROR_COUNT]; + enum bch_level bch_type; + uint32_t i, ecc_flag = 0; + uint8_t count; + uint32_t byte_pos, bit_pos; + int err = 0; + + /* check calculated ecc */ + for (i = 0; i < ecc->bytes && !ecc_flag; i++) { + if (calc_ecc[i] != 0x00) + ecc_flag = 1; + } + if (!ecc_flag) + return 0; + + /* check for whether its a erased-page */ + ecc_flag = 0; + for (i = 0; i < ecc->bytes && !ecc_flag; i++) { + if (read_ecc[i] != 0xff) + ecc_flag = 1; + } + if (!ecc_flag) + return 0; - switch (bch->type) { - case ECC_BCH4: - n_bytes = 8; + /* + * while reading ECC result we read it in big endian. + * Hence while loading to ELM we have rotate to get the right endian. + */ + switch (info->ecc_scheme) { + case OMAP_ECC_BCH8_CODE_HW: + bch_type = BCH_8_BIT; + omap_reverse_list(calc_ecc, ecc->bytes - 1); break; - - case ECC_BCH16: - n_bytes = 28; + case OMAP_ECC_BCH16_CODE_HW: + bch_type = BCH_16_BIT; + omap_reverse_list(calc_ecc, ecc->bytes); break; - - case ECC_BCH8: default: - n_bytes = 13; - break; + return -EINVAL; } + /* use elm module to check for errors */ + elm_config(bch_type); + err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc); + if (err) + return err; - for (i = 0, j = n_bytes - 1; i < n_bytes; i++, j--) - syndrome[i] = calc_ecc[j]; + /* correct bch error */ + for (count = 0; count < error_count; count++) { + switch (info->ecc_scheme) { + case OMAP_ECC_BCH8_CODE_HW: + /* 14th byte in ECC is reserved to match ROM layout */ + error_max = SECTOR_BYTES + (ecc->bytes - 1); + break; + case OMAP_ECC_BCH16_CODE_HW: + error_max = SECTOR_BYTES + ecc->bytes; + break; + default: + return -EINVAL; + } + byte_pos = error_max - (error_loc[count] / 8) - 1; + bit_pos = error_loc[count] % 8; + if (byte_pos < SECTOR_BYTES) { + dat[byte_pos] ^= 1 << bit_pos; + printf("nand: bit-flip corrected @data=%d\n", byte_pos); + } else if (byte_pos < error_max) { + read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos; + printf("nand: bit-flip corrected @oob=%d\n", byte_pos - + SECTOR_BYTES); + } else { + err = -EBADMSG; + printf("nand: error: invalid bit-flip location\n"); + } + } + return (err) ? err : error_count; } -/* - * omap_calculate_ecc_bch - Read BCH ECC result - * - * @mtd: MTD structure - * @dat: unused - * @ecc_code: ecc_code buffer +#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH + +#define PREFETCH_CONFIG1_CS_SHIFT 24 +#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 +#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) +#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) +#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) +#define ENABLE_PREFETCH (1 << 7) + +/** + * omap_prefetch_enable - configures and starts prefetch transfer + * @fifo_th: fifo threshold to be used for read/ write + * @count: number of bytes to be transferred + * @is_write: prefetch read(0) or write post(1) mode + * @cs: chip select to use */ -static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc_code) +static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs) { - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t big_endian = 1; - int8_t ret = 0; + uint32_t val; - if (bch->type == ECC_BCH8) - omap_read_bch8_result(mtd, big_endian, ecc_code); - else /* BCH4 and BCH16 currently not supported */ - ret = -1; + if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) + return -EINVAL; - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - omap_ecc_disable(mtd); + if (readl(&gpmc_cfg->prefetch_control)) + return -EBUSY; + + /* Set the amount of bytes to be prefetched */ + writel(count, &gpmc_cfg->prefetch_config2); - return ret; + val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) | + PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH; + writel(val, &gpmc_cfg->prefetch_config1); + + /* Start the prefetch engine */ + writel(1, &gpmc_cfg->prefetch_control); + + return 0; } -/* - * omap_fix_errors_bch - Correct bch error in the data - * - * @mtd: MTD device structure - * @data: Data read from flash - * @error_count:Number of errors in data - * @error_loc: Locations of errors in the data - * +/** + * omap_prefetch_reset - disables and stops the prefetch engine */ -static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data, - uint32_t error_count, uint32_t *error_loc) +static void omap_prefetch_reset(void) { - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t count = 0; - uint32_t error_byte_pos; - uint32_t error_bit_mask; - uint32_t last_bit = (bch->nibbles * 4) - 1; - - /* Flip all bits as specified by the error location array. */ - /* FOR( each found error location flip the bit ) */ - for (count = 0; count < error_count; count++) { - if (error_loc[count] > last_bit) { - /* Remove the ECC spare bits from correction. */ - error_loc[count] -= (last_bit + 1); - /* Offset bit in data region */ - error_byte_pos = ((512 * 8) - - (error_loc[count]) - 1) / 8; - /* Error Bit mask */ - error_bit_mask = 0x1 << (error_loc[count] % 8); - /* Toggle the error bit to make the correction. */ - data[error_byte_pos] ^= error_bit_mask; - } - } + writel(0, &gpmc_cfg->prefetch_control); + writel(0, &gpmc_cfg->prefetch_config1); } -/* - * omap_correct_data_bch - Compares the ecc read from nand spare area - * with ECC registers values and corrects one bit error if it has occured - * - * @mtd: MTD device structure - * @dat: page data - * @read_ecc: ecc read from nand flash (ignored) - * @calc_ecc: ecc read from ECC registers - * - * @return 0 if data is OK or corrected, else returns -1 - */ -static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, - uint8_t *read_ecc, uint8_t *calc_ecc) +static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len) { - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t syndrome[28]; - uint32_t error_count = 0; - uint32_t error_loc[8]; - uint32_t i, ecc_flag; - int k, ecc_bytes, num_steps; - - num_steps = chip->ecc.size / 512; - ecc_bytes = chip->ecc.bytes / num_steps; - - for (k = 0; k < num_steps; k++) { - ecc_flag = 0; - /* check if area is flashed */ - for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) - if (read_ecc[i] != 0xff) - ecc_flag = 1; - - if (ecc_flag) { - ecc_flag = 0; - /* check if any ecc error */ - for (i = 0; (i < ecc_bytes) && !ecc_flag; i++) - if (calc_ecc[i] != 0) - ecc_flag = 1; - } + int ret; + uint32_t cnt; + struct omap_nand_info *info = chip->priv; - if (!ecc_flag) - return 0; + ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs); + if (ret < 0) + return ret; - elm_reset(); - elm_config((enum bch_level)(bch->type)); + do { + int i; - /* - * while reading ECC result we read it in big endian. - * Hence while loading to ELM we have rotate to get the right endian. - */ - omap_rotate_ecc_bch(mtd, calc_ecc, syndrome); + cnt = readl(&gpmc_cfg->prefetch_status); + cnt = PREFETCH_STATUS_FIFO_CNT(cnt); - /* use elm module to check for errors */ - if (elm_check_error(syndrome, bch->nibbles, &error_count, - error_loc) != 0) { - printf("ECC: uncorrectable.\n"); - return -1; + for (i = 0; i < cnt / 4; i++) { + *buf++ = readl(CONFIG_SYS_NAND_BASE); + len -= 4; } + } while (len); + + omap_prefetch_reset(); - /* correct bch error */ - if (error_count > 0) - omap_fix_errors_bch(mtd, dat, error_count, error_loc); - dat += 512; - read_ecc += ecc_bytes; - calc_ecc += ecc_bytes; - } return 0; } +static void omap_nand_read_prefetch8(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int ret; + uint32_t head, tail; + struct nand_chip *chip = mtd->priv; + + /* + * If the destination buffer is unaligned, start with reading + * the overlap byte-wise. + */ + head = ((uint32_t) buf) % 4; + if (head) { + nand_read_buf(mtd, buf, head); + buf += head; + len -= head; + } + + /* + * Only transfer multiples of 4 bytes in a pre-fetched fashion. + * If there's a residue, care for it byte-wise afterwards. + */ + tail = len % 4; + + ret = __read_prefetch_aligned(chip, (uint32_t *) buf, len - tail); + if (ret < 0) { + /* fallback in case the prefetch engine is busy */ + nand_read_buf(mtd, buf, len); + } else if (tail) { + buf += len - tail; + nand_read_buf(mtd, buf, tail); + } +} +#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ + /** * omap_read_page_bch - hardware ecc based page read function * @mtd: mtd info structure @@ -805,11 +765,11 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, oob += eccbytes) { chip->ecc.hwctl(mtd, NAND_ECC_READ); /* read data */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page); + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1); chip->read_buf(mtd, p, eccsize); /* read respective ecc from oob area */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page); + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); chip->read_buf(mtd, oob, eccbytes); /* read syndrome */ chip->ecc.calculate(mtd, p, &ecc_calc[i]); @@ -841,81 +801,30 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, } return 0; } -#endif /* CONFIG_AM33XX */ +#endif /* CONFIG_NAND_OMAP_ELM */ /* * OMAP3 BCH8 support (with BCH library) */ -#ifdef CONFIG_NAND_OMAP_BCH8 -/* - * omap_calculate_ecc_bch - Read BCH ECC result - * - * @mtd: MTD device structure - * @dat: The pointer to data on which ecc is computed (unused here) - * @ecc: The ECC output buffer - */ -static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc) -{ - int ret = 0; - size_t i; - unsigned long nsectors, val1, val2, val3, val4; - - nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1; - - for (i = 0; i < nsectors; i++) { - /* Read hw-computed remainder */ - val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]); - val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]); - val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]); - val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]); - - /* - * Add constant polynomial to remainder, in order to get an ecc - * sequence of 0xFFs for a buffer filled with 0xFFs. - */ - *ecc++ = 0xef ^ (val4 & 0xFF); - *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF); - *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF); - *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF); - *ecc++ = 0xed ^ (val3 & 0xFF); - *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF); - *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF); - *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF); - *ecc++ = 0x97 ^ (val2 & 0xFF); - *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF); - *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF); - *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); - *ecc++ = 0xb5 ^ (val1 & 0xFF); - } - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - omap_ecc_disable(mtd); - - return ret; -} - +#ifdef CONFIG_BCH /** - * omap_correct_data_bch - Decode received data and correct errors + * omap_correct_data_bch_sw - Decode received data and correct errors * @mtd: MTD device structure * @data: page data * @read_ecc: ecc read from nand flash * @calc_ecc: ecc read from HW ECC registers */ -static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data, +static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, u_char *read_ecc, u_char *calc_ecc) { int i, count; /* cannot correct more than 8 errors */ unsigned int errloc[8]; struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *chip_priv = chip->priv; - struct bch_control *bch = chip_priv->control; + struct omap_nand_info *info = chip->priv; - count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc); + count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc, + NULL, errloc); if (count > 0) { /* correct errors */ for (i = 0; i < count; i++) { @@ -951,18 +860,194 @@ static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data, static void __maybe_unused omap_free_bch(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *chip_priv = chip->priv; - struct bch_control *bch = NULL; + struct omap_nand_info *info = chip->priv; + + if (info->control) { + free_bch(info->control); + info->control = NULL; + } +} +#endif /* CONFIG_BCH */ + +/** + * omap_select_ecc_scheme - configures driver for particular ecc-scheme + * @nand: NAND chip device structure + * @ecc_scheme: ecc scheme to configure + * @pagesize: number of main-area bytes per page of NAND device + * @oobsize: number of OOB/spare bytes per page of NAND device + */ +static int omap_select_ecc_scheme(struct nand_chip *nand, + enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { + struct omap_nand_info *info = nand->priv; + struct nand_ecclayout *ecclayout = &omap_ecclayout; + int eccsteps = pagesize / SECTOR_BYTES; + int i; + + switch (ecc_scheme) { + case OMAP_ECC_HAM1_CODE_SW: + debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); + /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are + * initialized in nand_scan_tail(), so just set ecc.mode */ + info->control = NULL; + nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = NULL; + nand->ecc.size = 0; + break; + + case OMAP_ECC_HAM1_CODE_HW: + debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (3 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + info->control = NULL; + /* populate ecc specific fields */ + memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 1; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 3; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) { + if (nand->options & NAND_BUSWIDTH_16) + ecclayout->eccpos[i] = i + 2; + else + ecclayout->eccpos[i] = i + 1; + } + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + break; + + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: +#ifdef CONFIG_BCH + debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (13 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* check if BCH S/W library can be used for error detection */ + info->control = init_bch(13, 8, 0x201b); + if (!info->control) { + printf("nand: error: could not init_bch()\n"); + return -ENODEV; + } + /* populate ecc specific fields */ + memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 8; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 13; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data_bch_sw; + nand->ecc.calculate = omap_calculate_ecc; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; + for (i = 1; i < ecclayout->eccbytes; i++) { + if (i % nand->ecc.bytes) + ecclayout->eccpos[i] = + ecclayout->eccpos[i - 1] + 1; + else + ecclayout->eccpos[i] = + ecclayout->eccpos[i - 1] + 2; + } + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + break; +#else + printf("nand: error: CONFIG_BCH required for ECC\n"); + return -EINVAL; +#endif - if (chip_priv) - bch = chip_priv->control; + case OMAP_ECC_BCH8_CODE_HW: +#ifdef CONFIG_NAND_OMAP_ELM + debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (14 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* intialize ELM for ECC error detection */ + elm_init(); + info->control = NULL; + /* populate ecc specific fields */ + memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 8; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 14; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.read_page = omap_read_page_bch; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + break; +#else + printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); + return -EINVAL; +#endif - if (bch) { - free_bch(bch); - chip_priv->control = NULL; + case OMAP_ECC_BCH16_CODE_HW: +#ifdef CONFIG_NAND_OMAP_ELM + debug("nand: using OMAP_ECC_BCH16_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (26 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* intialize ELM for ECC error detection */ + elm_init(); + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 26; + nand->ecc.strength = 16; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.read_page = omap_read_page_bch; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes - + BADBLOCK_MARKER_LENGTH; + break; +#else + printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); + return -EINVAL; +#endif + default: + debug("nand: error: ecc scheme not enabled or supported\n"); + return -EINVAL; } + + /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */ + if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW) + nand->ecc.layout = ecclayout; + + info->ecc_scheme = ecc_scheme; + return 0; } -#endif /* CONFIG_NAND_OMAP_BCH8 */ #ifndef CONFIG_SPL_BUILD /* @@ -973,77 +1058,46 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) * @eccstrength - the number of bits that could be corrected * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16) */ -void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) +int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) { struct nand_chip *nand; struct mtd_info *mtd; + int err = 0; if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[nand_curr_device].name) { - printf("Error: Can't switch ecc, no devices available\n"); - return; + printf("nand: error: no NAND devices found\n"); + return -ENODEV; } mtd = &nand_info[nand_curr_device]; nand = mtd->priv; - nand->options |= NAND_OWN_BUFFERS; - - /* Reset ecc interface */ - nand->ecc.mode = NAND_ECC_NONE; - nand->ecc.read_page = NULL; - nand->ecc.write_page = NULL; - nand->ecc.read_oob = NULL; - nand->ecc.write_oob = NULL; - nand->ecc.hwctl = NULL; - nand->ecc.correct = NULL; - nand->ecc.calculate = NULL; - nand->ecc.strength = eccstrength; - + nand->options &= ~NAND_SUBPAGE_READ; /* Setup the ecc configurations again */ if (hardware) { if (eccstrength == 1) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_nand_oob; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.calculate = omap_calculate_ecc; - omap_hwecc_init(nand); - printf("1-bit hamming HW ECC selected\n"); - } -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) - else if (eccstrength == 8) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_bch8_nand_oob; - nand->ecc.size = 512; -#ifdef CONFIG_AM33XX - nand->ecc.bytes = 14; - nand->ecc.read_page = omap_read_page_bch; -#else - nand->ecc.bytes = 13; -#endif - nand->ecc.hwctl = omap_enable_ecc_bch; - nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; - omap_hwecc_init_bch(nand, NAND_ECC_READ); - printf("8-bit BCH HW ECC selected\n"); + err = omap_select_ecc_scheme(nand, + OMAP_ECC_HAM1_CODE_HW, + mtd->writesize, mtd->oobsize); + } else if (eccstrength == 8) { + err = omap_select_ecc_scheme(nand, + OMAP_ECC_BCH8_CODE_HW, + mtd->writesize, mtd->oobsize); + } else { + printf("nand: error: unsupported ECC scheme\n"); + return -EINVAL; } -#endif } else { - nand->ecc.mode = NAND_ECC_SOFT; - /* Use mtd default settings */ - nand->ecc.layout = NULL; - nand->ecc.size = 0; - printf("SW ECC selected\n"); + err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, + mtd->writesize, mtd->oobsize); } /* Update NAND handling after ECC mode switch */ - nand_scan_tail(mtd); - - nand->options &= ~NAND_OWN_BUFFERS; + if (!err) + err = nand_scan_tail(mtd); + return err; } #endif /* CONFIG_SPL_BUILD */ @@ -1065,8 +1119,8 @@ void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) int board_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; - cs = 0; - + int cs = cs_next++; + int err = 0; /* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the @@ -1083,7 +1137,7 @@ int board_nand_init(struct nand_chip *nand) cs++; } if (cs >= GPMC_MAX_CS) { - printf("NAND: Unable to find NAND settings in " + printf("nand: error: Unable to find NAND settings in " "GPMC Configuration - quitting\n"); return -ENODEV; } @@ -1095,69 +1149,34 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - - nand->cmd_ctrl = omap_nand_hwcontrol; - nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_SUBPAGE_WRITE; - /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) - nand->options |= NAND_BUSWIDTH_16; - + omap_nand_info[cs].control = NULL; + omap_nand_info[cs].cs = cs; + nand->priv = &omap_nand_info[cs]; + nand->cmd_ctrl = omap_nand_hwcontrol; + nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; nand->chip_delay = 100; + nand->ecc.layout = &omap_ecclayout; -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) -#ifdef CONFIG_AM33XX - /* AM33xx uses the ELM */ - /* required in case of BCH */ - elm_init(); + /* configure driver and controller based on NAND device bus-width */ + gpmc_config = readl(&gpmc_cfg->cs[cs].config1); +#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT) + nand->options |= NAND_BUSWIDTH_16; + writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1); #else - /* - * Whereas other OMAP based SoC do not have the ELM, they use the BCH - * SW library. - */ - bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */); - if (!bch_priv.control) { - printf("Failed to initialize BCH engine\n"); - return -ENODEV; - } -#endif - /* BCH info that will be correct for SPL or overridden otherwise. */ - nand->priv = &bch_priv; -#endif - - /* Default ECC mode */ -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_bch8_nand_oob; -#ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE * 4; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES * 4; -#else - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + nand->options &= ~NAND_BUSWIDTH_16; + writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1); #endif - nand->ecc.strength = 8; - nand->ecc.hwctl = omap_enable_ecc_bch; - nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; -#ifdef CONFIG_AM33XX - nand->ecc.read_page = omap_read_page_bch; -#endif - omap_hwecc_init_bch(nand, NAND_ECC_READ); -#else -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) - nand->ecc.mode = NAND_ECC_SOFT; + /* select ECC scheme */ +#if defined(CONFIG_NAND_OMAP_ECCSCHEME) + err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, + CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); #else - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_nand_oob; - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.calculate = omap_calculate_ecc; - nand->ecc.strength = 1; - omap_hwecc_init(nand); -#endif + /* pagesize and oobsize are not required to configure sw ecc-scheme */ + err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, + 0, 0); #endif + if (err) + return err; #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT if (nand->ecc.layout) { bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset; @@ -1174,18 +1193,15 @@ int board_nand_init(struct nand_chip *nand) nand->bbt_md = &bbt_mirror_descr; #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH + /* TODO: Implement for 16-bit bus width */ if (nand->options & NAND_BUSWIDTH_16) nand->read_buf = nand_read_buf16; else - nand->read_buf = nand_read_buf; - nand->dev_ready = omap_spl_dev_ready; -#else -#ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE - nand->write_buf = write_buf_pref; - nand->read_buf = read_buf_pref; -#endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */ -#endif /* CONFIG_SPL_BUILD */ + nand->read_buf = omap_nand_read_prefetch8; +#endif + + nand->dev_ready = omap_dev_ready; return 0; } diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index db87d07269..b3a2a60bb2 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -38,10 +38,10 @@ static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } #endif -static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; - struct s3c2410_nand *nand = s3c2410_get_base_nand(); + struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); @@ -67,35 +67,35 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) writeb(cmd, chip->IO_ADDR_W); } -static int s3c2410_dev_ready(struct mtd_info *mtd) +static int s3c24x0_dev_ready(struct mtd_info *mtd) { - struct s3c2410_nand *nand = s3c2410_get_base_nand(); + struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); debug("dev_ready\n"); return readl(&nand->nfstat) & 0x01; } #ifdef CONFIG_S3C2410_NAND_HWECC -void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) +void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode) { - struct s3c2410_nand *nand = s3c2410_get_base_nand(); - debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); + struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); + debug("s3c24x0_nand_enable_hwecc(%p, %d)\n", mtd, mode); writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); } -static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, +static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { - struct s3c2410_nand *nand = s3c2410_get_base_nand(); + struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); ecc_code[0] = readb(&nand->nfecc); ecc_code[1] = readb(&nand->nfecc + 1); ecc_code[2] = readb(&nand->nfecc + 2); - debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", - mtd , ecc_code[0], ecc_code[1], ecc_code[2]); + debug("s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", + mtd , ecc_code[0], ecc_code[1], ecc_code[2]); return 0; } -static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, +static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { if (read_ecc[0] == calc_ecc[0] && @@ -103,7 +103,7 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, read_ecc[2] == calc_ecc[2]) return 0; - printf("s3c2410_nand_correct_data: not implemented\n"); + printf("s3c24x0_nand_correct_data: not implemented\n"); return -1; } #endif @@ -113,7 +113,7 @@ int board_nand_init(struct nand_chip *nand) u_int32_t cfg; u_int8_t tacls, twrph0, twrph1; struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c2410_nand *nand_reg = s3c2410_get_base_nand(); + struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand(); debug("board_nand_init()\n"); @@ -149,14 +149,14 @@ int board_nand_init(struct nand_chip *nand) #endif /* hwcontrol always must be implemented */ - nand->cmd_ctrl = s3c2410_hwcontrol; + nand->cmd_ctrl = s3c24x0_hwcontrol; - nand->dev_ready = s3c2410_dev_ready; + nand->dev_ready = s3c24x0_dev_ready; #ifdef CONFIG_S3C2410_NAND_HWECC - nand->ecc.hwctl = s3c2410_nand_enable_hwecc; - nand->ecc.calculate = s3c2410_nand_calculate_ecc; - nand->ecc.correct = s3c2410_nand_correct_data; + nand->ecc.hwctl = s3c24x0_nand_enable_hwecc; + nand->ecc.calculate = s3c24x0_nand_calculate_ecc; + nand->ecc.correct = s3c24x0_nand_correct_data; nand->ecc.mode = NAND_ECC_HW; nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index 163cf29a39..b660f3b206 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -79,7 +79,7 @@ enum { struct fdt_nand { struct nand_ctlr *reg; int enabled; /* 1 to enable, 0 to disable */ - struct fdt_gpio_state wp_gpio; /* write-protect GPIO */ + struct gpio_desc wp_gpio; /* write-protect GPIO */ s32 width; /* bit width, normally 8 */ u32 timing[FDT_NAND_TIMING_COUNT]; }; @@ -945,8 +945,8 @@ static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config) config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg"); config->enabled = fdtdec_get_is_enabled(blob, node); config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8); - err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios", - &config->wp_gpio); + err = gpio_request_by_name_nodev(blob, node, "nvidia,wp-gpios", 0, + &config->wp_gpio, GPIOD_IS_OUT); if (err) return err; err = fdtdec_get_int_array(blob, node, "nvidia,timing", @@ -1009,8 +1009,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) /* Adjust timing for NAND device */ setup_timing(config->timing, info->reg); - fdtdec_setup_gpio(&config->wp_gpio); - gpio_direction_output(config->wp_gpio.gpio, 1); + dm_gpio_set_value(&config->wp_gpio, 1); our_mtd = &nand_info[devnum]; our_mtd->priv = nand; diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c new file mode 100644 index 0000000000..921c06c6c8 --- /dev/null +++ b/drivers/mtd/nand/vf610_nfc.c @@ -0,0 +1,727 @@ +/* + * Copyright 2009-2014 Freescale Semiconductor, Inc. and others + * + * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. + * Ported to U-Boot by Stefan Agner + * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir + * Jason ported to M54418TWR and MVFA5. + * Authors: Stefan Agner + * Bill Pringlemeir + * Shaohui Xie + * Jason Jin + * + * Based on original driver mpc5121_nfc.c. + * + * This is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Limitations: + * - Untested on MPC5125 and M54418. + * - DMA not used. + * - 2K pages or less. + * - Only 2K page w. 64+OOB and hardware ECC. + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +/* Register Offsets */ +#define NFC_FLASH_CMD1 0x3F00 +#define NFC_FLASH_CMD2 0x3F04 +#define NFC_COL_ADDR 0x3F08 +#define NFC_ROW_ADDR 0x3F0c +#define NFC_ROW_ADDR_INC 0x3F14 +#define NFC_FLASH_STATUS1 0x3F18 +#define NFC_FLASH_STATUS2 0x3F1c +#define NFC_CACHE_SWAP 0x3F28 +#define NFC_SECTOR_SIZE 0x3F2c +#define NFC_FLASH_CONFIG 0x3F30 +#define NFC_IRQ_STATUS 0x3F38 + +/* Addresses for NFC MAIN RAM BUFFER areas */ +#define NFC_MAIN_AREA(n) ((n) * 0x1000) + +#define PAGE_2K 0x0800 +#define OOB_64 0x0040 + +/* + * NFC_CMD2[CODE] values. See section: + * - 31.4.7 Flash Command Code Description, Vybrid manual + * - 23.8.6 Flash Command Sequencer, MPC5125 manual + * + * Briefly these are bitmasks of controller cycles. + */ +#define READ_PAGE_CMD_CODE 0x7EE0 +#define PROGRAM_PAGE_CMD_CODE 0x7FC0 +#define ERASE_CMD_CODE 0x4EC0 +#define READ_ID_CMD_CODE 0x4804 +#define RESET_CMD_CODE 0x4040 +#define STATUS_READ_CMD_CODE 0x4068 + +/* NFC ECC mode define */ +#define ECC_BYPASS 0 +#define ECC_45_BYTE 6 + +/*** Register Mask and bit definitions */ + +/* NFC_FLASH_CMD1 Field */ +#define CMD_BYTE2_MASK 0xFF000000 +#define CMD_BYTE2_SHIFT 24 + +/* NFC_FLASH_CM2 Field */ +#define CMD_BYTE1_MASK 0xFF000000 +#define CMD_BYTE1_SHIFT 24 +#define CMD_CODE_MASK 0x00FFFF00 +#define CMD_CODE_SHIFT 8 +#define BUFNO_MASK 0x00000006 +#define BUFNO_SHIFT 1 +#define START_BIT (1<<0) + +/* NFC_COL_ADDR Field */ +#define COL_ADDR_MASK 0x0000FFFF +#define COL_ADDR_SHIFT 0 + +/* NFC_ROW_ADDR Field */ +#define ROW_ADDR_MASK 0x00FFFFFF +#define ROW_ADDR_SHIFT 0 +#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 +#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 +#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 +#define ROW_ADDR_CHIP_SEL_SHIFT 24 + +/* NFC_FLASH_STATUS2 Field */ +#define STATUS_BYTE1_MASK 0x000000FF + +/* NFC_FLASH_CONFIG Field */ +#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 +#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 +#define CONFIG_ECC_SRAM_REQ_BIT (1<<21) +#define CONFIG_DMA_REQ_BIT (1<<20) +#define CONFIG_ECC_MODE_MASK 0x000E0000 +#define CONFIG_ECC_MODE_SHIFT 17 +#define CONFIG_FAST_FLASH_BIT (1<<16) +#define CONFIG_16BIT (1<<7) +#define CONFIG_BOOT_MODE_BIT (1<<6) +#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) +#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) +#define CONFIG_PAGE_CNT_MASK 0xF +#define CONFIG_PAGE_CNT_SHIFT 0 + +/* NFC_IRQ_STATUS Field */ +#define IDLE_IRQ_BIT (1<<29) +#define IDLE_EN_BIT (1<<20) +#define CMD_DONE_CLEAR_BIT (1<<18) +#define IDLE_CLEAR_BIT (1<<17) + +#define NFC_TIMEOUT (1000) + +/* ECC status placed at end of buffers. */ +#define ECC_SRAM_ADDR ((PAGE_2K+256-8) >> 3) +#define ECC_STATUS_MASK 0x80 +#define ECC_ERR_COUNT 0x3F + +/* + * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian + * and +7 for big-endian SOC. + */ +#ifdef CONFIG_SOC_VF610 +#define ECC_OFFSET 4 +#else +#define ECC_OFFSET 7 +#endif + +struct vf610_nfc { + struct mtd_info *mtd; + struct nand_chip chip; + void __iomem *regs; + uint column; + int spareonly; + int page; + /* Status and ID are in alternate locations. */ + int alt_buf; +#define ALT_BUF_ID 1 +#define ALT_BUF_STAT 2 + struct clk *clk; +}; + +#define mtd_to_nfc(_mtd) \ + (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv + +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 11, + .len = 4, + .veroffs = 15, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 11, + .len = 4, + .veroffs = 15, + .maxblocks = 4, + .pattern = mirror_pattern, +}; + +static struct nand_ecclayout vf610_nfc_ecc45 = { + .eccbytes = 45, + .eccpos = {19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = { + {.offset = 8, + .length = 11} } +}; + +static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + return readl(nfc->regs + reg); +} + +static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + writel(val, nfc->regs + reg); +} + +static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits) +{ + vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits); +} + +static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits) +{ + vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits); +} + +static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg, + u32 mask, u32 shift, u32 val) +{ + vf610_nfc_write(mtd, reg, + (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift); +} + +static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) +{ + /* + * Use this accessor for the interal SRAM buffers. On ARM we can + * treat the SRAM buffer as if its memory, hence use memcpy + */ + memcpy(dst, src, n); +} + +/* Clear flags for upcoming command */ +static inline void vf610_nfc_clear_status(void __iomem *regbase) +{ + void __iomem *reg = regbase + NFC_IRQ_STATUS; + u32 tmp = __raw_readl(reg); + tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; + __raw_writel(tmp, reg); +} + +/* Wait for complete operation */ +static inline void vf610_nfc_done(struct mtd_info *mtd) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + uint start; + + /* + * Barrier is needed after this write. This write need + * to be done before reading the next register the first + * time. + * vf610_nfc_set implicates such a barrier by using writel + * to write to the register. + */ + vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT); + + start = get_timer(0); + + while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) { + if (get_timer(start) > NFC_TIMEOUT) { + printf("Timeout while waiting for !BUSY.\n"); + return; + } + } + vf610_nfc_clear_status(nfc->regs); +} + +static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col) +{ + u32 flash_id; + + if (col < 4) { + flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1); + return (flash_id >> (3-col)*8) & 0xff; + } else { + flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2); + return flash_id >> 24; + } +} + +static u8 vf610_nfc_get_status(struct mtd_info *mtd) +{ + return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; +} + +/* Single command */ +static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1, + u32 cmd_code) +{ + void __iomem *reg = regbase + NFC_FLASH_CMD2; + u32 tmp; + vf610_nfc_clear_status(regbase); + + tmp = __raw_readl(reg); + tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); + tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; + tmp |= cmd_code << CMD_CODE_SHIFT; + __raw_writel(tmp, reg); +} + +/* Two commands */ +static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1, + u32 cmd_byte2, u32 cmd_code) +{ + void __iomem *reg = regbase + NFC_FLASH_CMD1; + u32 tmp; + vf610_nfc_send_command(regbase, cmd_byte1, cmd_code); + + tmp = __raw_readl(reg); + tmp &= ~CMD_BYTE2_MASK; + tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; + __raw_writel(tmp, reg); +} + +static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) +{ + if (column != -1) { + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + if (nfc->chip.options | NAND_BUSWIDTH_16) + column = column/2; + vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK, + COL_ADDR_SHIFT, column); + } + if (page != -1) + vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, + ROW_ADDR_SHIFT, page); +} + +/* Send command to NAND chip */ +static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, + int column, int page) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + nfc->column = max(column, 0); + nfc->spareonly = 0; + nfc->alt_buf = 0; + + switch (command) { + case NAND_CMD_PAGEPROG: + nfc->page = -1; + vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN, + command, PROGRAM_PAGE_CMD_CODE); + vf610_nfc_addr_cycle(mtd, column, page); + break; + + case NAND_CMD_RESET: + vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE); + break; + /* + * NFC does not support sub-page reads and writes, + * so emulate them using full page transfers. + */ + case NAND_CMD_READOOB: + nfc->spareonly = 1; + case NAND_CMD_SEQIN: /* Pre-read for partial writes. */ + case NAND_CMD_READ0: + column = 0; + /* Already read? */ + if (nfc->page == page) + return; + nfc->page = page; + vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, + NAND_CMD_READSTART, READ_PAGE_CMD_CODE); + vf610_nfc_addr_cycle(mtd, column, page); + break; + + case NAND_CMD_ERASE1: + if (nfc->page == page) + nfc->page = -1; + vf610_nfc_send_commands(nfc->regs, command, + NAND_CMD_ERASE2, ERASE_CMD_CODE); + vf610_nfc_addr_cycle(mtd, column, page); + break; + + case NAND_CMD_READID: + nfc->alt_buf = ALT_BUF_ID; + vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE); + break; + + case NAND_CMD_STATUS: + nfc->alt_buf = ALT_BUF_STAT; + vf610_nfc_send_command(nfc->regs, command, + STATUS_READ_CMD_CODE); + break; + default: + return; + } + + vf610_nfc_done(mtd); +} + +static inline void vf610_nfc_read_spare(struct mtd_info *mtd, void *buf, + int len) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + len = min(mtd->oobsize, (uint)len); + if (len > 0) + vf610_nfc_memcpy(buf, nfc->regs + mtd->writesize, len); +} + +/* Read data from NFC buffers */ +static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + uint c = nfc->column; + uint l; + + /* Handle main area */ + if (!nfc->spareonly) { + l = min((uint)len, mtd->writesize - c); + nfc->column += l; + + if (!nfc->alt_buf) + vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, + l); + else + if (nfc->alt_buf & ALT_BUF_ID) + *buf = vf610_nfc_get_id(mtd, c); + else + *buf = vf610_nfc_get_status(mtd); + + buf += l; + len -= l; + } + + /* Handle spare area access */ + if (len) { + nfc->column += len; + vf610_nfc_read_spare(mtd, buf, len); + } +} + +/* Write data to NFC buffers */ +static void vf610_nfc_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + uint c = nfc->column; + uint l; + + l = min((uint)len, mtd->writesize + mtd->oobsize - c); + nfc->column += l; + vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); +} + +/* Read byte from NFC buffers */ +static u8 vf610_nfc_read_byte(struct mtd_info *mtd) +{ + u8 tmp; + vf610_nfc_read_buf(mtd, &tmp, sizeof(tmp)); + return tmp; +} + +/* Read word from NFC buffers */ +static u16 vf610_nfc_read_word(struct mtd_info *mtd) +{ + u16 tmp; + vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); + return tmp; +} + +/* If not provided, upper layers apply a fixed delay. */ +static int vf610_nfc_dev_ready(struct mtd_info *mtd) +{ + /* NFC handles R/B internally; always ready. */ + return 1; +} + +/* + * This function supports Vybrid only (MPC5125 would have full RB and four CS) + */ +static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) +{ +#ifdef CONFIG_SOC_VF610 + u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR); + tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); + tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; + + if (chip == 0) + tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT; + else if (chip == 1) + tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT; + + vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp); +#endif +} + +/* Count the number of 0's in buff upto max_bits */ +static inline int count_written_bits(uint8_t *buff, int size, int max_bits) +{ + uint32_t *buff32 = (uint32_t *)buff; + int k, written_bits = 0; + + for (k = 0; k < (size / 4); k++) { + written_bits += hweight32(~buff32[k]); + if (written_bits > max_bits) + break; + } + + return written_bits; +} + +static inline int vf610_nfc_correct_data(struct mtd_info *mtd, u_char *dat) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + u8 ecc_status; + u8 ecc_count; + int flip; + + ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET); + ecc_count = ecc_status & ECC_ERR_COUNT; + if (!(ecc_status & ECC_STATUS_MASK)) + return ecc_count; + + /* If 'ecc_count' zero or less then buffer is all 0xff or erased. */ + flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count); + + /* ECC failed. */ + if (flip > ecc_count) { + nfc->page = -1; + return -1; + } + + /* Erased page. */ + memset(dat, 0xff, nfc->chip.ecc.size); + return 0; +} + + +static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + int eccsize = chip->ecc.size; + int stat; + uint8_t *p = buf; + + + vf610_nfc_read_buf(mtd, p, eccsize); + + if (oob_required) + vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); + + stat = vf610_nfc_correct_data(mtd, p); + + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + + return 0; +} + +/* + * ECC will be calculated automatically + */ +static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + vf610_nfc_write_buf(mtd, buf, mtd->writesize); + if (oob_required) + vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; +} + +struct vf610_nfc_config { + int hardware_ecc; + int width; + int flash_bbt; +}; + +static int vf610_nfc_nand_init(int devnum, void __iomem *addr) +{ + struct mtd_info *mtd = &nand_info[devnum]; + struct nand_chip *chip; + struct vf610_nfc *nfc; + int err = 0; + int page_sz; + struct vf610_nfc_config cfg = { + .hardware_ecc = 1, +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + .width = 16, +#else + .width = 8, +#endif + .flash_bbt = 1, + }; + + nfc = malloc(sizeof(*nfc)); + if (!nfc) { + printf(KERN_ERR "%s: Memory exhausted!\n", __func__); + return -ENOMEM; + } + + chip = &nfc->chip; + nfc->regs = addr; + + mtd->priv = chip; + chip->priv = nfc; + + if (cfg.width == 16) { + chip->options |= NAND_BUSWIDTH_16; + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); + } else { + chip->options &= ~NAND_BUSWIDTH_16; + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); + } + + /* Disable subpage writes as we do not provide ecc->hwctl */ + chip->options |= NAND_NO_SUBPAGE_WRITE; + + chip->dev_ready = vf610_nfc_dev_ready; + chip->cmdfunc = vf610_nfc_command; + chip->read_byte = vf610_nfc_read_byte; + chip->read_word = vf610_nfc_read_word; + chip->read_buf = vf610_nfc_read_buf; + chip->write_buf = vf610_nfc_write_buf; + chip->select_chip = vf610_nfc_select_chip; + + /* Bad block options. */ + if (cfg.flash_bbt) + chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_CREATE; + + /* Default to software ECC until flash ID. */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, + CONFIG_ECC_MODE_MASK, + CONFIG_ECC_MODE_SHIFT, ECC_BYPASS); + + chip->bbt_td = &bbt_main_descr; + chip->bbt_md = &bbt_mirror_descr; + + page_sz = PAGE_2K + OOB_64; + page_sz += cfg.width == 16 ? 1 : 0; + vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz); + + /* Set configuration register. */ + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); + + /* Enable Idle IRQ */ + vf610_nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT); + + /* PAGE_CNT = 1 */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, + CONFIG_PAGE_CNT_SHIFT, 1); + + /* Set ECC_STATUS offset */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, + CONFIG_ECC_SRAM_ADDR_MASK, + CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR); + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) { + err = -ENXIO; + goto error; + } + + chip->ecc.mode = NAND_ECC_SOFT; /* default */ + + page_sz = mtd->writesize + mtd->oobsize; + + /* Single buffer only, max 256 OOB minus ECC status */ + if (page_sz > PAGE_2K + 256 - 8) { + dev_err(nfc->dev, "Unsupported flash size\n"); + err = -ENXIO; + goto error; + } + page_sz += cfg.width == 16 ? 1 : 0; + vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz); + + if (cfg.hardware_ecc) { + if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { + dev_err(nfc->dev, "Unsupported flash with hwecc\n"); + err = -ENXIO; + goto error; + } + + chip->ecc.layout = &vf610_nfc_ecc45; + + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = chip->ecc.layout; + chip->ecc.read_page = vf610_nfc_read_page; + chip->ecc.write_page = vf610_nfc_write_page; + chip->ecc.mode = NAND_ECC_HW; + + chip->ecc.bytes = 45; + chip->ecc.size = PAGE_2K; + chip->ecc.strength = 24; + + /* set ECC mode to 45 bytes OOB with 24 bits correction */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, + CONFIG_ECC_MODE_MASK, + CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE); + + /* Enable ECC_STATUS */ + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); + } + + /* second phase scan */ + err = nand_scan_tail(mtd); + if (err) + return err; + + err = nand_register(devnum); + if (err) + return err; + + return 0; + +error: + return err; +} + +void board_nand_init(void) +{ + int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE); + if (err) + printf("VF610 NAND init failed (err %d)\n", err); +} diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile index 993d317476..b249348814 100644 --- a/drivers/mtd/onenand/Makefile +++ b/drivers/mtd/onenand/Makefile @@ -5,30 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libonenand.o - ifndef CONFIG_SPL_BUILD -COBJS-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o -COBJS-$(CONFIG_SAMSUNG_ONENAND) += samsung.o +obj-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o +obj-$(CONFIG_SAMSUNG_ONENAND) += samsung.o else -COBJS-y := onenand_spl.o +obj-y := onenand_spl.o endif - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index ddfe7e7c75..03deabce10 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -22,6 +22,7 @@ #include #include #include +#include "linux/mtd/flashchip.h" #include #include @@ -91,7 +92,13 @@ static struct nand_ecclayout onenand_oob_32 = { .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } }; -static const unsigned char ffchars[] = { +/* + * Warning! This array is used with the memcpy_16() function, thus + * it must be aligned to 2 bytes. GCC can make this array unaligned + * as the array is made of unsigned char, which memcpy16() doesn't + * like and will cause unaligned access. + */ +static const unsigned char __aligned(2) ffchars[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -761,7 +768,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, uint8_t *oob_buf = this->oob_buf; free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { if (readcol >= lastgap) readcol += free->offset - lastgap; if (readend >= lastgap) @@ -770,7 +778,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, } this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { int free_end = free->offset + free->length; if (free->offset < readend && free_end > readcol) { int st = max_t(int,free->offset,readcol); @@ -969,7 +978,8 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, if (mtd->ecc_stats.failed - stats.failed) return -EBADMSG; - return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; + /* return max bitflips per ecc step; ONENANDs correct 1 bit only */ + return mtd->ecc_stats.corrected != stats.corrected ? 1 : 0; } /** @@ -1355,7 +1365,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, unsigned int i; free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { if (writecol >= lastgap) writecol += free->offset - lastgap; if (writeend >= lastgap) @@ -1363,7 +1374,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, lastgap = free->offset + free->length; } free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { int free_end = free->offset + free->length; if (free->offset < writeend && free_end > writecol) { int st = max_t(int,free->offset,writecol); @@ -2749,7 +2761,8 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) * the out of band area */ this->ecclayout->oobavail = 0; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && + + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && this->ecclayout->oobfree[i].length; i++) this->ecclayout->oobavail += this->ecclayout->oobfree[i].length; diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index 0267c2c5c9..52509f1ae9 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -140,7 +140,6 @@ static inline int onenand_memory_bbt(struct mtd_info *mtd, { unsigned char data_buf[MAX_ONENAND_PAGESIZE]; - bd->options &= ~NAND_BBT_SCANEMPTY; return create_bbt(mtd, data_buf, bd, -1); } diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c index df04c2bb48..5e56a2954d 100644 --- a/drivers/mtd/onenand/samsung.c +++ b/drivers/mtd/onenand/samsung.c @@ -15,20 +15,12 @@ #include #include #include +#include #include #include #include -#ifdef ONENAND_DEBUG -#define DPRINTK(format, args...) \ -do { \ - printf("%s[%d]: " format "\n", __func__, __LINE__, ##args); \ -} while (0) -#else -#define DPRINTK(...) do { } while (0) -#endif - #define ONENAND_ERASE_STATUS 0x00 #define ONENAND_MULTI_ERASE_SET 0x01 #define ONENAND_ERASE_START 0x03 diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index e537fcf54c..c61b784e17 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -5,40 +5,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libspi_flash.o +obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o ifdef CONFIG_SPL_BUILD -COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o +obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o +obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o endif -COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o -COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o -COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o -COBJS-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.o -COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o -COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o -COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o -COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o -COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o -COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o -COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +#ifndef CONFIG_DM_SPI +obj-$(CONFIG_SPI_FLASH) += sf_probe.o +#endif +obj-$(CONFIG_CMD_SF) += sf.o +obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o +obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o +obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c deleted file mode 100644 index 6a92c4b774..0000000000 --- a/drivers/mtd/spi/atmel.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Atmel SPI DataFlash support - * - * Copyright (C) 2008 Atmel Corporation - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -#include "spi_flash_internal.h" - -/* AT45-specific commands */ -#define CMD_AT45_READ_STATUS 0xd7 -#define CMD_AT45_ERASE_PAGE 0x81 -#define CMD_AT45_LOAD_PROG_BUF1 0x82 -#define CMD_AT45_LOAD_BUF1 0x84 -#define CMD_AT45_LOAD_PROG_BUF2 0x85 -#define CMD_AT45_LOAD_BUF2 0x87 -#define CMD_AT45_PROG_BUF1 0x88 -#define CMD_AT45_PROG_BUF2 0x89 - -/* AT45 status register bits */ -#define AT45_STATUS_P2_PAGE_SIZE (1 << 0) -#define AT45_STATUS_READY (1 << 7) - -/* DataFlash family IDs, as obtained from the second idcode byte */ -#define DF_FAMILY_AT26F 0 -#define DF_FAMILY_AT45 1 -#define DF_FAMILY_AT26DF 2 /* AT25DF and AT26DF */ - -struct atmel_spi_flash_params { - u8 idcode1; - /* Log2 of page size in power-of-two mode */ - u8 l2_page_size; - u8 pages_per_block; - u8 blocks_per_sector; - u8 nr_sectors; - const char *name; -}; - -/* spi_flash needs to be first so upper layers can free() it */ -struct atmel_spi_flash { - struct spi_flash flash; - const struct atmel_spi_flash_params *params; -}; - -static inline struct atmel_spi_flash * -to_atmel_spi_flash(struct spi_flash *flash) -{ - return container_of(flash, struct atmel_spi_flash, flash); -} - -static const struct atmel_spi_flash_params atmel_spi_flash_table[] = { - { - .idcode1 = 0x22, - .l2_page_size = 8, - .pages_per_block = 8, - .blocks_per_sector = 16, - .nr_sectors = 4, - .name = "AT45DB011D", - }, - { - .idcode1 = 0x23, - .l2_page_size = 8, - .pages_per_block = 8, - .blocks_per_sector = 16, - .nr_sectors = 8, - .name = "AT45DB021D", - }, - { - .idcode1 = 0x24, - .l2_page_size = 8, - .pages_per_block = 8, - .blocks_per_sector = 32, - .nr_sectors = 8, - .name = "AT45DB041D", - }, - { - .idcode1 = 0x25, - .l2_page_size = 8, - .pages_per_block = 8, - .blocks_per_sector = 32, - .nr_sectors = 16, - .name = "AT45DB081D", - }, - { - .idcode1 = 0x26, - .l2_page_size = 9, - .pages_per_block = 8, - .blocks_per_sector = 32, - .nr_sectors = 16, - .name = "AT45DB161D", - }, - { - .idcode1 = 0x27, - .l2_page_size = 9, - .pages_per_block = 8, - .blocks_per_sector = 64, - .nr_sectors = 64, - .name = "AT45DB321D", - }, - { - .idcode1 = 0x28, - .l2_page_size = 10, - .pages_per_block = 8, - .blocks_per_sector = 32, - .nr_sectors = 32, - .name = "AT45DB642D", - }, - { - .idcode1 = 0x47, - .l2_page_size = 8, - .pages_per_block = 16, - .blocks_per_sector = 16, - .nr_sectors = 64, - .name = "AT25DF321", - }, -}; - -static int at45_wait_ready(struct spi_flash *flash, unsigned long timeout) -{ - struct spi_slave *spi = flash->spi; - unsigned long timebase; - int ret; - u8 cmd = CMD_AT45_READ_STATUS; - u8 status; - - timebase = get_timer(0); - - ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); - if (ret) - return -1; - - do { - ret = spi_xfer(spi, 8, NULL, &status, 0); - if (ret) - return -1; - - if (status & AT45_STATUS_READY) - break; - } while (get_timer(timebase) < timeout); - - /* Deactivate CS */ - spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); - - if (status & AT45_STATUS_READY) - return 0; - - /* Timed out */ - return -1; -} - -/* - * Assemble the address part of a command for AT45 devices in - * non-power-of-two page size mode. - */ -static void at45_build_address(struct atmel_spi_flash *asf, u8 *cmd, u32 offset) -{ - unsigned long page_addr; - unsigned long byte_addr; - unsigned long page_size; - unsigned int page_shift; - - /* - * The "extra" space per page is the power-of-two page size - * divided by 32. - */ - page_shift = asf->params->l2_page_size; - page_size = (1 << page_shift) + (1 << (page_shift - 5)); - page_shift++; - page_addr = offset / page_size; - byte_addr = offset % page_size; - - cmd[0] = page_addr >> (16 - page_shift); - cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8); - cmd[2] = byte_addr; -} - -static int dataflash_read_fast_at45(struct spi_flash *flash, - u32 offset, size_t len, void *buf) -{ - struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); - u8 cmd[5]; - - cmd[0] = CMD_READ_ARRAY_FAST; - at45_build_address(asf, cmd + 1, offset); - cmd[4] = 0x00; - - return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); -} - -/* - * TODO: the two write funcs (_p2/_at45) should get unified ... - */ -static int dataflash_write_p2(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) -{ - struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); - unsigned long page_size; - u32 addr = offset; - size_t chunk_len; - size_t actual; - int ret; - u8 cmd[4]; - - /* - * TODO: This function currently uses only page buffer #1. We can - * speed this up by using both buffers and loading one buffer while - * the other is being programmed into main memory. - */ - - page_size = (1 << asf->params->l2_page_size); - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - (addr % page_size)); - - /* Use the same address bits for both commands */ - cmd[0] = CMD_AT45_LOAD_BUF1; - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr; - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: Loading AT45 buffer failed\n"); - goto out; - } - - cmd[0] = CMD_AT45_PROG_BUF1; - ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); - if (ret < 0) { - debug("SF: AT45 page programming failed\n"); - goto out; - } - - ret = at45_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret < 0) { - debug("SF: AT45 page programming timed out\n"); - goto out; - } - - addr += chunk_len; - } - - debug("SF: AT45: Successfully programmed %zu bytes @ 0x%x\n", - len, offset); - ret = 0; - -out: - spi_release_bus(flash->spi); - return ret; -} - -static int dataflash_write_at45(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) -{ - struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); - unsigned long page_addr; - unsigned long byte_addr; - unsigned long page_size; - unsigned int page_shift; - size_t chunk_len; - size_t actual; - int ret; - u8 cmd[4]; - - /* - * TODO: This function currently uses only page buffer #1. We can - * speed this up by using both buffers and loading one buffer while - * the other is being programmed into main memory. - */ - - page_shift = asf->params->l2_page_size; - page_size = (1 << page_shift) + (1 << (page_shift - 5)); - page_shift++; - page_addr = offset / page_size; - byte_addr = offset % page_size; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); - - /* Use the same address bits for both commands */ - cmd[0] = CMD_AT45_LOAD_BUF1; - cmd[1] = page_addr >> (16 - page_shift); - cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8); - cmd[3] = byte_addr; - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: Loading AT45 buffer failed\n"); - goto out; - } - - cmd[0] = CMD_AT45_PROG_BUF1; - ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); - if (ret < 0) { - debug("SF: AT45 page programming failed\n"); - goto out; - } - - ret = at45_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret < 0) { - debug("SF: AT45 page programming timed out\n"); - goto out; - } - - page_addr++; - byte_addr = 0; - } - - debug("SF: AT45: Successfully programmed %zu bytes @ 0x%x\n", - len, offset); - ret = 0; - -out: - spi_release_bus(flash->spi); - return ret; -} - -/* - * TODO: the two erase funcs (_p2/_at45) should get unified ... - */ -static int dataflash_erase_p2(struct spi_flash *flash, u32 offset, size_t len) -{ - struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); - unsigned long page_size; - - size_t actual; - int ret; - u8 cmd[4]; - - /* - * TODO: This function currently uses page erase only. We can - * probably speed things up by using block and/or sector erase - * when possible. - */ - - page_size = (1 << asf->params->l2_page_size); - - if (offset % page_size || len % page_size) { - debug("SF: Erase offset/length not multiple of page size\n"); - return -1; - } - - cmd[0] = CMD_AT45_ERASE_PAGE; - cmd[3] = 0x00; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - for (actual = 0; actual < len; actual += page_size) { - cmd[1] = offset >> 16; - cmd[2] = offset >> 8; - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); - if (ret < 0) { - debug("SF: AT45 page erase failed\n"); - goto out; - } - - ret = at45_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); - if (ret < 0) { - debug("SF: AT45 page erase timed out\n"); - goto out; - } - - offset += page_size; - } - - debug("SF: AT45: Successfully erased %zu bytes @ 0x%x\n", - len, offset); - ret = 0; - -out: - spi_release_bus(flash->spi); - return ret; -} - -static int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len) -{ - struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); - unsigned long page_addr; - unsigned long page_size; - unsigned int page_shift; - size_t actual; - int ret; - u8 cmd[4]; - - /* - * TODO: This function currently uses page erase only. We can - * probably speed things up by using block and/or sector erase - * when possible. - */ - - page_shift = asf->params->l2_page_size; - page_size = (1 << page_shift) + (1 << (page_shift - 5)); - page_shift++; - page_addr = offset / page_size; - - if (offset % page_size || len % page_size) { - debug("SF: Erase offset/length not multiple of page size\n"); - return -1; - } - - cmd[0] = CMD_AT45_ERASE_PAGE; - cmd[3] = 0x00; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - for (actual = 0; actual < len; actual += page_size) { - cmd[1] = page_addr >> (16 - page_shift); - cmd[2] = page_addr << (page_shift - 8); - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); - if (ret < 0) { - debug("SF: AT45 page erase failed\n"); - goto out; - } - - ret = at45_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); - if (ret < 0) { - debug("SF: AT45 page erase timed out\n"); - goto out; - } - - page_addr++; - } - - debug("SF: AT45: Successfully erased %zu bytes @ 0x%x\n", - len, offset); - ret = 0; - -out: - spi_release_bus(flash->spi); - return ret; -} - -struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) -{ - const struct atmel_spi_flash_params *params; - unsigned page_size; - unsigned int family; - struct atmel_spi_flash *asf; - unsigned int i; - int ret; - u8 status; - - for (i = 0; i < ARRAY_SIZE(atmel_spi_flash_table); i++) { - params = &atmel_spi_flash_table[i]; - if (params->idcode1 == idcode[1]) - break; - } - - if (i == ARRAY_SIZE(atmel_spi_flash_table)) { - debug("SF: Unsupported DataFlash ID %02x\n", - idcode[1]); - return NULL; - } - - asf = spi_flash_alloc(struct atmel_spi_flash, spi, params->name); - if (!asf) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - - asf->params = params; - - /* Assuming power-of-two page size initially. */ - page_size = 1 << params->l2_page_size; - - family = idcode[1] >> 5; - - switch (family) { - case DF_FAMILY_AT45: - /* - * AT45 chips have configurable page size. The status - * register indicates which configuration is active. - */ - ret = spi_flash_cmd(spi, CMD_AT45_READ_STATUS, &status, 1); - if (ret) - goto err; - - debug("SF: AT45 status register: %02x\n", status); - - if (!(status & AT45_STATUS_P2_PAGE_SIZE)) { - asf->flash.read = dataflash_read_fast_at45; - asf->flash.write = dataflash_write_at45; - asf->flash.erase = dataflash_erase_at45; - page_size += 1 << (params->l2_page_size - 5); - } else { - asf->flash.write = dataflash_write_p2; - asf->flash.erase = dataflash_erase_p2; - } - - asf->flash.page_size = page_size; - asf->flash.sector_size = page_size; - break; - - case DF_FAMILY_AT26F: - case DF_FAMILY_AT26DF: - asf->flash.page_size = page_size; - asf->flash.sector_size = 4096; - /* clear SPRL# bit for locked flash */ - spi_flash_cmd_write_status(&asf->flash, 0); - break; - - default: - debug("SF: Unsupported DataFlash family %u\n", family); - goto err; - } - - asf->flash.size = page_size * params->pages_per_block - * params->blocks_per_sector - * params->nr_sectors; - - return &asf->flash; - -err: - free(asf); - return NULL; -} diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c deleted file mode 100644 index b16e7ab098..0000000000 --- a/drivers/mtd/spi/eon.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2010, ucRobotics Inc. - * Author: Chong Huang - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -#include "spi_flash_internal.h" - -struct eon_spi_flash_params { - u8 idcode1; - u16 nr_sectors; - const char *name; -}; - -static const struct eon_spi_flash_params eon_spi_flash_table[] = { - { - .idcode1 = 0x16, - .nr_sectors = 1024, - .name = "EN25Q32B", - }, - { - .idcode1 = 0x18, - .nr_sectors = 4096, - .name = "EN25Q128", - }, -}; - -struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) -{ - const struct eon_spi_flash_params *params; - struct spi_flash *flash; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { - params = &eon_spi_flash_table[i]; - if (params->idcode1 == idcode[2]) - break; - } - - if (i == ARRAY_SIZE(eon_spi_flash_table)) { - debug("SF: Unsupported EON ID %02x\n", idcode[1]); - return NULL; - } - - flash = spi_flash_alloc_base(spi, params->name); - if (!flash) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - - flash->page_size = 256; - flash->sector_size = 256 * 16 * 16; - flash->size = 256 * 16 - * params->nr_sectors; - - return flash; -} diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c new file mode 100644 index 0000000000..b915469b40 --- /dev/null +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -0,0 +1,90 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define ESPI_BOOT_IMAGE_SIZE 0x48 +#define ESPI_BOOT_IMAGE_ADDR 0x50 +#define CONFIG_CFG_DATA_SECTOR 0 + +void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst) +{ + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (flash == NULL) { + puts("\nspi_flash_probe failed"); + hang(); + } + + spi_flash_read(flash, offs, size, vdst); +} + +/* + * The main entry for SPI booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from SPI into SDRAM and starts it from there. + */ +void spi_boot(void) +{ + void (*uboot)(void) __noreturn; + u32 offset, code_len, copy_len = 0; +#ifndef CONFIG_FSL_CORENET + unsigned char *buf = NULL; +#endif + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (flash == NULL) { + puts("\nspi_flash_probe failed"); + hang(); + } + +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE; +#else + /* + * Load U-Boot image from SPI flash into RAM + */ + buf = malloc(flash->page_size); + if (buf == NULL) { + puts("\nmalloc failed"); + hang(); + } + memset(buf, 0, flash->page_size); + + spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR, + flash->page_size, (void *)buf); + offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR); + /* Skip spl code */ + offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + /* Get the code size from offset 0x48 */ + code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); + /* Skip spl code */ + code_len = code_len - CONFIG_SPL_MAX_SIZE; +#endif + /* copy code to DDR */ + printf("Loading second stage boot loader "); + while (copy_len <= code_len) { + spi_flash_read(flash, offset + copy_len, 0x2000, + (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST + + copy_len)); + copy_len = copy_len + 0x2000; + putc('.'); + } + + /* + * Jump to U-Boot image + */ + flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len); + uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START; + (*uboot)(); +} diff --git a/drivers/mtd/spi/gigadevice.c b/drivers/mtd/spi/gigadevice.c deleted file mode 100644 index 950c7770a9..0000000000 --- a/drivers/mtd/spi/gigadevice.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Gigadevice SPI flash driver - * Copyright 2013, Samsung Electronics Co., Ltd. - * Author: Banajit Goswami - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "spi_flash_internal.h" - -struct gigadevice_spi_flash_params { - uint16_t id; - uint16_t nr_blocks; - const char *name; -}; - -static const struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] = { - { - .id = 0x6016, - .nr_blocks = 64, - .name = "GD25LQ", - }, - { - .id = 0x4017, - .nr_blocks = 128, - .name = "GD25Q64B", - }, -}; - -struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode) -{ - const struct gigadevice_spi_flash_params *params; - struct spi_flash *flash; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(gigadevice_spi_flash_table); i++) { - params = &gigadevice_spi_flash_table[i]; - if (params->id == ((idcode[1] << 8) | idcode[2])) - break; - } - - if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) { - debug("SF: Unsupported Gigadevice ID %02x%02x\n", - idcode[1], idcode[2]); - return NULL; - } - - flash = spi_flash_alloc_base(spi, params->name); - if (!flash) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - /* page_size */ - flash->page_size = 256; - /* sector_size = page_size * pages_per_sector */ - flash->sector_size = flash->page_size * 16; - /* size = sector_size * sector_per_block * number of blocks */ - flash->size = flash->sector_size * 16 * params->nr_blocks; - - return flash; -} diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c deleted file mode 100644 index 70435eb5a3..0000000000 --- a/drivers/mtd/spi/macronix.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright 2009(C) Marvell International Ltd. and its affiliates - * Prafulla Wadaskar - * - * Based on drivers/mtd/spi/stmicro.c - * - * Copyright 2008, Network Appliance Inc. - * Jason McMullan - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "spi_flash_internal.h" - -struct macronix_spi_flash_params { - u16 idcode; - u16 nr_blocks; - const char *name; -}; - -static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { - { - .idcode = 0x2013, - .nr_blocks = 8, - .name = "MX25L4005", - }, - { - .idcode = 0x2014, - .nr_blocks = 16, - .name = "MX25L8005", - }, - { - .idcode = 0x2015, - .nr_blocks = 32, - .name = "MX25L1605D", - }, - { - .idcode = 0x2016, - .nr_blocks = 64, - .name = "MX25L3205D", - }, - { - .idcode = 0x2017, - .nr_blocks = 128, - .name = "MX25L6405D", - }, - { - .idcode = 0x2018, - .nr_blocks = 256, - .name = "MX25L12805D", - }, - { - .idcode = 0x2618, - .nr_blocks = 256, - .name = "MX25L12855E", - }, -}; - -struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) -{ - const struct macronix_spi_flash_params *params; - struct spi_flash *flash; - unsigned int i; - u16 id = idcode[2] | idcode[1] << 8; - - for (i = 0; i < ARRAY_SIZE(macronix_spi_flash_table); i++) { - params = ¯onix_spi_flash_table[i]; - if (params->idcode == id) - break; - } - - if (i == ARRAY_SIZE(macronix_spi_flash_table)) { - debug("SF: Unsupported Macronix ID %04x\n", id); - return NULL; - } - - flash = spi_flash_alloc_base(spi, params->name); - if (!flash) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - - flash->page_size = 256; - flash->sector_size = 256 * 16 * 16; - flash->size = flash->sector_size * params->nr_blocks; - - /* Clear BP# bits for read-only flash */ - spi_flash_cmd_write_status(flash, 0); - - return flash; -} diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c deleted file mode 100644 index f67ddd696b..0000000000 --- a/drivers/mtd/spi/ramtron.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Note: RAMTRON SPI FRAMs are ferroelectric, nonvolatile RAMs - * with an interface identical to SPI flash devices. - * However since they behave like RAM there are no delays or - * busy polls required. They can sustain read or write at the - * allowed SPI bus speed, which can be 40 MHz for some devices. - * - * Unfortunately some RAMTRON devices do not have a means of - * identifying them. They will leave the SO line undriven when - * the READ-ID command is issued. It is therefore mandatory - * that the MISO line has a proper pull-up, so that READ-ID - * will return a row of 0xff. This 0xff pseudo-id will cause - * probes by all vendor specific functions that are designed - * to handle it. If the MISO line is not pulled up, READ-ID - * could return any random noise, even mimicking another - * device. - * - * We use CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC - * to define which device will be assumed after a simple status - * register verify. This method is prone to false positive - * detection and should therefore be the last to be tried. - * Enter it in the last position in the table in spi_flash.c! - * - * The define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC both activates - * compilation of the special handler and defines the device - * to assume. - */ - -#include -#include -#include -#include "spi_flash_internal.h" - -/* - * Properties of supported FRAMs - * Note: speed is currently not used because we have no method to deliver that - * value to the upper layers - */ -struct ramtron_spi_fram_params { - u32 size; /* size in bytes */ - u8 addr_len; /* number of address bytes */ - u8 merge_cmd; /* some address bits are in the command byte */ - u8 id1; /* device ID 1 (family, density) */ - u8 id2; /* device ID 2 (sub, rev, rsvd) */ - u32 speed; /* max. SPI clock in Hz */ - const char *name; /* name for display and/or matching */ -}; - -struct ramtron_spi_fram { - struct spi_flash flash; - const struct ramtron_spi_fram_params *params; -}; - -static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash - *flash) -{ - return container_of(flash, struct ramtron_spi_fram, flash); -} - -/* - * table describing supported FRAM chips: - * chips without RDID command must have the values 0xff for id1 and id2 - */ -static const struct ramtron_spi_fram_params ramtron_spi_fram_table[] = { - { - .size = 32*1024, - .addr_len = 2, - .merge_cmd = 0, - .id1 = 0x22, - .id2 = 0x00, - .speed = 40000000, - .name = "FM25V02", - }, - { - .size = 32*1024, - .addr_len = 2, - .merge_cmd = 0, - .id1 = 0x22, - .id2 = 0x01, - .speed = 40000000, - .name = "FM25VN02", - }, - { - .size = 64*1024, - .addr_len = 2, - .merge_cmd = 0, - .id1 = 0x23, - .id2 = 0x00, - .speed = 40000000, - .name = "FM25V05", - }, - { - .size = 64*1024, - .addr_len = 2, - .merge_cmd = 0, - .id1 = 0x23, - .id2 = 0x01, - .speed = 40000000, - .name = "FM25VN05", - }, - { - .size = 128*1024, - .addr_len = 3, - .merge_cmd = 0, - .id1 = 0x24, - .id2 = 0x00, - .speed = 40000000, - .name = "FM25V10", - }, - { - .size = 128*1024, - .addr_len = 3, - .merge_cmd = 0, - .id1 = 0x24, - .id2 = 0x01, - .speed = 40000000, - .name = "FM25VN10", - }, -#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC - { - .size = 256*1024, - .addr_len = 3, - .merge_cmd = 0, - .id1 = 0xff, - .id2 = 0xff, - .speed = 40000000, - .name = "FM25H20", - }, -#endif -}; - -static int ramtron_common(struct spi_flash *flash, - u32 offset, size_t len, void *buf, u8 command) -{ - struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash); - u8 cmd[4]; - int cmd_len; - int ret; - - if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) { - cmd[0] = command; - cmd[1] = offset >> 16; - cmd[2] = offset >> 8; - cmd[3] = offset; - cmd_len = 4; - } else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) { - cmd[0] = command; - cmd[1] = offset >> 8; - cmd[2] = offset; - cmd_len = 3; - } else { - printf("SF: unsupported addr_len or merge_cmd\n"); - return -1; - } - - /* claim the bus */ - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - if (command == CMD_PAGE_PROGRAM) { - /* send WREN */ - ret = spi_flash_cmd_write_enable(flash); - if (ret < 0) { - debug("SF: Enabling Write failed\n"); - goto releasebus; - } - } - - /* do the transaction */ - if (command == CMD_PAGE_PROGRAM) - ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len); - else - ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len); - if (ret < 0) - debug("SF: Transaction failed\n"); - -releasebus: - /* release the bus */ - spi_release_bus(flash->spi); - return ret; -} - -static int ramtron_read(struct spi_flash *flash, - u32 offset, size_t len, void *buf) -{ - return ramtron_common(flash, offset, len, buf, - CMD_READ_ARRAY_SLOW); -} - -static int ramtron_write(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) -{ - return ramtron_common(flash, offset, len, (void *)buf, - CMD_PAGE_PROGRAM); -} - -static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - debug("SF: Erase of RAMTRON FRAMs is pointless\n"); - return -1; -} - -/* - * nore: we are called here with idcode pointing to the first non-0x7f byte - * already! - */ -struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) -{ - const struct ramtron_spi_fram_params *params; - struct ramtron_spi_fram *sn; - unsigned int i; -#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC - int ret; - u8 sr; -#endif - - /* NOTE: the bus has been claimed before this function is called! */ - switch (idcode[0]) { - case 0xc2: - /* JEDEC conformant RAMTRON id */ - for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { - params = &ramtron_spi_fram_table[i]; - if (idcode[1] == params->id1 && idcode[2] == params->id2) - goto found; - } - break; -#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC - case 0xff: - /* - * probably open MISO line, pulled up. - * We COULD have a non JEDEC conformant FRAM here, - * read the status register to verify - */ - ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1); - if (ret) - return NULL; - - /* Bits 5,4,0 are fixed 0 for all devices */ - if ((sr & 0x31) != 0x00) - return NULL; - /* now find the device */ - for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { - params = &ramtron_spi_fram_table[i]; - if (!strcmp(params->name, CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC)) - goto found; - } - debug("SF: Unsupported non-JEDEC RAMTRON device " - CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "\n"); - break; -#endif - default: - break; - } - - /* arriving here means no method has found a device we can handle */ - debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n", - idcode[0], idcode[1], idcode[2]); - return NULL; - -found: - sn = spi_flash_alloc(struct ramtron_spi_fram, spi, params->name); - if (!sn) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - - sn->params = params; - - sn->flash.write = ramtron_write; - sn->flash.read = ramtron_read; - sn->flash.erase = ramtron_erase; - sn->flash.size = params->size; - - return &sn->flash; -} diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c new file mode 100644 index 0000000000..d576d31243 --- /dev/null +++ b/drivers/mtd/spi/sandbox.c @@ -0,0 +1,697 @@ +/* + * Simulate a SPI flash + * + * Copyright (c) 2011-2013 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include +#include + +#include +#include "sf_internal.h" + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The different states that our SPI flash transitions between. + * We need to keep track of this across multiple xfer calls since + * the SPI bus could possibly call down into us multiple times. + */ +enum sandbox_sf_state { + SF_CMD, /* default state -- we're awaiting a command */ + SF_ID, /* read the flash's (jedec) ID code */ + SF_ADDR, /* processing the offset in the flash to read/etc... */ + SF_READ, /* reading data from the flash */ + SF_WRITE, /* writing data to the flash, i.e. page programming */ + SF_ERASE, /* erase the flash */ + SF_READ_STATUS, /* read the flash's status register */ + SF_READ_STATUS1, /* read the flash's status register upper 8 bits*/ + SF_WRITE_STATUS, /* write the flash's status register */ +}; + +static const char *sandbox_sf_state_name(enum sandbox_sf_state state) +{ + static const char * const states[] = { + "CMD", "ID", "ADDR", "READ", "WRITE", "ERASE", "READ_STATUS", + "READ_STATUS1", "WRITE_STATUS", + }; + return states[state]; +} + +/* Bits for the status register */ +#define STAT_WIP (1 << 0) +#define STAT_WEL (1 << 1) + +/* Assume all SPI flashes have 3 byte addresses since they do atm */ +#define SF_ADDR_LEN 3 + +#define IDCODE_LEN 3 + +/* Used to quickly bulk erase backing store */ +static u8 sandbox_sf_0xff[0x1000]; + +/* Internal state data for each SPI flash */ +struct sandbox_spi_flash { + unsigned int cs; /* Chip select we are attached to */ + /* + * As we receive data over the SPI bus, our flash transitions + * between states. For example, we start off in the SF_CMD + * state where the first byte tells us what operation to perform + * (such as read or write the flash). But the operation itself + * can go through a few states such as first reading in the + * offset in the flash to perform the requested operation. + * Thus "state" stores the exact state that our machine is in + * while "cmd" stores the overall command we're processing. + */ + enum sandbox_sf_state state; + uint cmd; + /* Erase size of current erase command */ + uint erase_size; + /* Current position in the flash; used when reading/writing/etc... */ + uint off; + /* How many address bytes we've consumed */ + uint addr_bytes, pad_addr_bytes; + /* The current flash status (see STAT_XXX defines above) */ + u16 status; + /* Data describing the flash we're emulating */ + const struct spi_flash_params *data; + /* The file on disk to serv up data from */ + int fd; +}; + +struct sandbox_spi_flash_plat_data { + const char *filename; + const char *device_name; + int bus; + int cs; +}; + +/** + * This is a very strange probe function. If it has platform data (which may + * have come from the device tree) then this function gets the filename and + * device type from there. Failing that it looks at the command line + * parameter. + */ +static int sandbox_sf_probe(struct udevice *dev) +{ + /* spec = idcode:file */ + struct sandbox_spi_flash *sbsf = dev_get_priv(dev); + const char *file; + size_t len, idname_len; + const struct spi_flash_params *data; + struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev); + struct sandbox_state *state = state_get_current(); + struct udevice *bus = dev->parent; + const char *spec = NULL; + int ret = 0; + int cs = -1; + int i; + + debug("%s: bus %d, looking for emul=%p: ", __func__, bus->seq, dev); + if (bus->seq >= 0 && bus->seq < CONFIG_SANDBOX_SPI_MAX_BUS) { + for (i = 0; i < CONFIG_SANDBOX_SPI_MAX_CS; i++) { + if (state->spi[bus->seq][i].emul == dev) + cs = i; + } + } + if (cs == -1) { + printf("Error: Unknown chip select for device '%s'", + dev->name); + return -EINVAL; + } + debug("found at cs %d\n", cs); + + if (!pdata->filename) { + struct sandbox_state *state = state_get_current(); + + assert(bus->seq != -1); + if (bus->seq < CONFIG_SANDBOX_SPI_MAX_BUS) + spec = state->spi[bus->seq][cs].spec; + if (!spec) { + ret = -ENOENT; + goto error; + } + + file = strchr(spec, ':'); + if (!file) { + printf("sandbox_sf: unable to parse file\n"); + ret = -EINVAL; + goto error; + } + idname_len = file - spec; + pdata->filename = file + 1; + pdata->device_name = spec; + ++file; + } else { + spec = strchr(pdata->device_name, ','); + if (spec) + spec++; + else + spec = pdata->device_name; + idname_len = strlen(spec); + } + debug("%s: device='%s'\n", __func__, spec); + + for (data = spi_flash_params_table; data->name; data++) { + len = strlen(data->name); + if (idname_len != len) + continue; + if (!strncasecmp(spec, data->name, len)) + break; + } + if (!data->name) { + printf("sandbox_sf: unknown flash '%*s'\n", (int)idname_len, + spec); + ret = -EINVAL; + goto error; + } + + if (sandbox_sf_0xff[0] == 0x00) + memset(sandbox_sf_0xff, 0xff, sizeof(sandbox_sf_0xff)); + + sbsf->fd = os_open(pdata->filename, 02); + if (sbsf->fd == -1) { + free(sbsf); + printf("sandbox_sf: unable to open file '%s'\n", + pdata->filename); + ret = -EIO; + goto error; + } + + sbsf->data = data; + sbsf->cs = cs; + + return 0; + + error: + debug("%s: Got error %d\n", __func__, ret); + return ret; +} + +static int sandbox_sf_remove(struct udevice *dev) +{ + struct sandbox_spi_flash *sbsf = dev_get_priv(dev); + + os_close(sbsf->fd); + + return 0; +} + +static void sandbox_sf_cs_activate(struct udevice *dev) +{ + struct sandbox_spi_flash *sbsf = dev_get_priv(dev); + + debug("sandbox_sf: CS activated; state is fresh!\n"); + + /* CS is asserted, so reset state */ + sbsf->off = 0; + sbsf->addr_bytes = 0; + sbsf->pad_addr_bytes = 0; + sbsf->state = SF_CMD; + sbsf->cmd = SF_CMD; +} + +static void sandbox_sf_cs_deactivate(struct udevice *dev) +{ + debug("sandbox_sf: CS deactivated; cmd done processing!\n"); +} + +/* + * There are times when the data lines are allowed to tristate. What + * is actually sensed on the line depends on the hardware. It could + * always be 0xFF/0x00 (if there are pull ups/downs), or things could + * float and so we'd get garbage back. This func encapsulates that + * scenario so we can worry about the details here. + */ +static void sandbox_spi_tristate(u8 *buf, uint len) +{ + /* XXX: make this into a user config option ? */ + memset(buf, 0xff, len); +} + +/* Figure out what command this stream is telling us to do */ +static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx, + u8 *tx) +{ + enum sandbox_sf_state oldstate = sbsf->state; + + /* We need to output a byte for the cmd byte we just ate */ + if (tx) + sandbox_spi_tristate(tx, 1); + + sbsf->cmd = rx[0]; + switch (sbsf->cmd) { + case CMD_READ_ID: + sbsf->state = SF_ID; + sbsf->cmd = SF_ID; + break; + case CMD_READ_ARRAY_FAST: + sbsf->pad_addr_bytes = 1; + case CMD_READ_ARRAY_SLOW: + case CMD_PAGE_PROGRAM: + sbsf->state = SF_ADDR; + break; + case CMD_WRITE_DISABLE: + debug(" write disabled\n"); + sbsf->status &= ~STAT_WEL; + break; + case CMD_READ_STATUS: + sbsf->state = SF_READ_STATUS; + break; + case CMD_READ_STATUS1: + sbsf->state = SF_READ_STATUS1; + break; + case CMD_WRITE_ENABLE: + debug(" write enabled\n"); + sbsf->status |= STAT_WEL; + break; + case CMD_WRITE_STATUS: + sbsf->state = SF_WRITE_STATUS; + break; + default: { + int flags = sbsf->data->flags; + + /* we only support erase here */ + if (sbsf->cmd == CMD_ERASE_CHIP) { + sbsf->erase_size = sbsf->data->sector_size * + sbsf->data->nr_sectors; + } else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) { + sbsf->erase_size = 4 << 10; + } else if (sbsf->cmd == CMD_ERASE_32K && (flags & SECT_32K)) { + sbsf->erase_size = 32 << 10; + } else if (sbsf->cmd == CMD_ERASE_64K && + !(flags & (SECT_4K | SECT_32K))) { + sbsf->erase_size = 64 << 10; + } else { + debug(" cmd unknown: %#x\n", sbsf->cmd); + return -EIO; + } + sbsf->state = SF_ADDR; + break; + } + } + + if (oldstate != sbsf->state) + debug(" cmd: transition to %s state\n", + sandbox_sf_state_name(sbsf->state)); + + return 0; +} + +int sandbox_erase_part(struct sandbox_spi_flash *sbsf, int size) +{ + int todo; + int ret; + + while (size > 0) { + todo = min(size, (int)sizeof(sandbox_sf_0xff)); + ret = os_write(sbsf->fd, sandbox_sf_0xff, todo); + if (ret != todo) + return ret; + size -= todo; + } + + return 0; +} + +static int sandbox_sf_xfer(struct udevice *dev, unsigned int bitlen, + const void *rxp, void *txp, unsigned long flags) +{ + struct sandbox_spi_flash *sbsf = dev_get_priv(dev); + const uint8_t *rx = rxp; + uint8_t *tx = txp; + uint cnt, pos = 0; + int bytes = bitlen / 8; + int ret; + + debug("sandbox_sf: state:%x(%s) bytes:%u\n", sbsf->state, + sandbox_sf_state_name(sbsf->state), bytes); + + if ((flags & SPI_XFER_BEGIN)) + sandbox_sf_cs_activate(dev); + + if (sbsf->state == SF_CMD) { + /* Figure out the initial state */ + ret = sandbox_sf_process_cmd(sbsf, rx, tx); + if (ret) + return ret; + ++pos; + } + + /* Process the remaining data */ + while (pos < bytes) { + switch (sbsf->state) { + case SF_ID: { + u8 id; + + debug(" id: off:%u tx:", sbsf->off); + if (sbsf->off < IDCODE_LEN) { + /* Extract correct byte from ID 0x00aabbcc */ + id = sbsf->data->jedec >> + (8 * (IDCODE_LEN - 1 - sbsf->off)); + } else { + id = 0; + } + debug("%d %02x\n", sbsf->off, id); + tx[pos++] = id; + ++sbsf->off; + break; + } + case SF_ADDR: + debug(" addr: bytes:%u rx:%02x ", sbsf->addr_bytes, + rx[pos]); + + if (sbsf->addr_bytes++ < SF_ADDR_LEN) + sbsf->off = (sbsf->off << 8) | rx[pos]; + debug("addr:%06x\n", sbsf->off); + + if (tx) + sandbox_spi_tristate(&tx[pos], 1); + pos++; + + /* See if we're done processing */ + if (sbsf->addr_bytes < + SF_ADDR_LEN + sbsf->pad_addr_bytes) + break; + + /* Next state! */ + if (os_lseek(sbsf->fd, sbsf->off, OS_SEEK_SET) < 0) { + puts("sandbox_sf: os_lseek() failed"); + return -EIO; + } + switch (sbsf->cmd) { + case CMD_READ_ARRAY_FAST: + case CMD_READ_ARRAY_SLOW: + sbsf->state = SF_READ; + break; + case CMD_PAGE_PROGRAM: + sbsf->state = SF_WRITE; + break; + default: + /* assume erase state ... */ + sbsf->state = SF_ERASE; + goto case_sf_erase; + } + debug(" cmd: transition to %s state\n", + sandbox_sf_state_name(sbsf->state)); + break; + case SF_READ: + /* + * XXX: need to handle exotic behavior: + * - reading past end of device + */ + + cnt = bytes - pos; + debug(" tx: read(%u)\n", cnt); + assert(tx); + ret = os_read(sbsf->fd, tx + pos, cnt); + if (ret < 0) { + puts("sandbox_sf: os_read() failed\n"); + return -EIO; + } + pos += ret; + break; + case SF_READ_STATUS: + debug(" read status: %#x\n", sbsf->status); + cnt = bytes - pos; + memset(tx + pos, sbsf->status, cnt); + pos += cnt; + break; + case SF_READ_STATUS1: + debug(" read status: %#x\n", sbsf->status); + cnt = bytes - pos; + memset(tx + pos, sbsf->status >> 8, cnt); + pos += cnt; + break; + case SF_WRITE_STATUS: + debug(" write status: %#x (ignored)\n", rx[pos]); + pos = bytes; + break; + case SF_WRITE: + /* + * XXX: need to handle exotic behavior: + * - unaligned addresses + * - more than a page (256) worth of data + * - reading past end of device + */ + if (!(sbsf->status & STAT_WEL)) { + puts("sandbox_sf: write enable not set before write\n"); + goto done; + } + + cnt = bytes - pos; + debug(" rx: write(%u)\n", cnt); + if (tx) + sandbox_spi_tristate(&tx[pos], cnt); + ret = os_write(sbsf->fd, rx + pos, cnt); + if (ret < 0) { + puts("sandbox_spi: os_write() failed\n"); + return -EIO; + } + pos += ret; + sbsf->status &= ~STAT_WEL; + break; + case SF_ERASE: + case_sf_erase: { + if (!(sbsf->status & STAT_WEL)) { + puts("sandbox_sf: write enable not set before erase\n"); + goto done; + } + + /* verify address is aligned */ + if (sbsf->off & (sbsf->erase_size - 1)) { + debug(" sector erase: cmd:%#x needs align:%#x, but we got %#x\n", + sbsf->cmd, sbsf->erase_size, + sbsf->off); + sbsf->status &= ~STAT_WEL; + goto done; + } + + debug(" sector erase addr: %u, size: %u\n", sbsf->off, + sbsf->erase_size); + + cnt = bytes - pos; + if (tx) + sandbox_spi_tristate(&tx[pos], cnt); + pos += cnt; + + /* + * TODO(vapier@gentoo.org): latch WIP in status, and + * delay before clearing it ? + */ + ret = sandbox_erase_part(sbsf, sbsf->erase_size); + sbsf->status &= ~STAT_WEL; + if (ret) { + debug("sandbox_sf: Erase failed\n"); + goto done; + } + goto done; + } + default: + debug(" ??? no idea what to do ???\n"); + goto done; + } + } + + done: + if (flags & SPI_XFER_END) + sandbox_sf_cs_deactivate(dev); + return pos == bytes ? 0 : -EIO; +} + +int sandbox_sf_ofdata_to_platdata(struct udevice *dev) +{ + struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + + pdata->filename = fdt_getprop(blob, node, "sandbox,filename", NULL); + pdata->device_name = fdt_getprop(blob, node, "compatible", NULL); + if (!pdata->filename || !pdata->device_name) { + debug("%s: Missing properties, filename=%s, device_name=%s\n", + __func__, pdata->filename, pdata->device_name); + return -EINVAL; + } + + return 0; +} + +static const struct dm_spi_emul_ops sandbox_sf_emul_ops = { + .xfer = sandbox_sf_xfer, +}; + +#ifdef CONFIG_SPI_FLASH +static int sandbox_cmdline_cb_spi_sf(struct sandbox_state *state, + const char *arg) +{ + unsigned long bus, cs; + const char *spec = sandbox_spi_parse_spec(arg, &bus, &cs); + + if (!spec) + return 1; + + /* + * It is safe to not make a copy of 'spec' because it comes from the + * command line. + * + * TODO(sjg@chromium.org): It would be nice if we could parse the + * spec here, but the problem is that no U-Boot init has been done + * yet. Perhaps we can figure something out. + */ + state->spi[bus][cs].spec = spec; + return 0; +} +SANDBOX_CMDLINE_OPT(spi_sf, 1, "connect a SPI flash: :::"); + +int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs, + struct udevice *bus, int of_offset, const char *spec) +{ + struct udevice *emul; + char name[20], *str; + struct driver *drv; + int ret; + + /* now the emulator */ + strncpy(name, spec, sizeof(name) - 6); + name[sizeof(name) - 6] = '\0'; + strcat(name, "-emul"); + str = strdup(name); + if (!str) + return -ENOMEM; + drv = lists_driver_lookup_name("sandbox_sf_emul"); + if (!drv) { + puts("Cannot find sandbox_sf_emul driver\n"); + return -ENOENT; + } + ret = device_bind(bus, drv, str, NULL, of_offset, &emul); + if (ret) { + printf("Cannot create emul device for spec '%s' (err=%d)\n", + spec, ret); + return ret; + } + state->spi[busnum][cs].emul = emul; + + return 0; +} + +void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs) +{ + struct udevice *dev; + + dev = state->spi[busnum][cs].emul; + device_remove(dev); + device_unbind(dev); + state->spi[busnum][cs].emul = NULL; +} + +static int sandbox_sf_bind_bus_cs(struct sandbox_state *state, int busnum, + int cs, const char *spec) +{ + struct udevice *bus, *slave; + int ret; + + ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, true, &bus); + if (ret) { + printf("Invalid bus %d for spec '%s' (err=%d)\n", busnum, + spec, ret); + return ret; + } + ret = spi_find_chip_select(bus, cs, &slave); + if (!ret) { + printf("Chip select %d already exists for spec '%s'\n", cs, + spec); + return -EEXIST; + } + + ret = device_bind_driver(bus, "spi_flash_std", spec, &slave); + if (ret) + return ret; + + return sandbox_sf_bind_emul(state, busnum, cs, bus, -1, spec); +} + +int sandbox_spi_get_emul(struct sandbox_state *state, + struct udevice *bus, struct udevice *slave, + struct udevice **emulp) +{ + struct sandbox_spi_info *info; + int busnum = bus->seq; + int cs = spi_chip_select(slave); + int ret; + + info = &state->spi[busnum][cs]; + if (!info->emul) { + /* Use the same device tree node as the SPI flash device */ + debug("%s: busnum=%u, cs=%u: binding SPI flash emulation: ", + __func__, busnum, cs); + ret = sandbox_sf_bind_emul(state, busnum, cs, bus, + slave->of_offset, slave->name); + if (ret) { + debug("failed (err=%d)\n", ret); + return ret; + } + debug("OK\n"); + } + *emulp = info->emul; + + return 0; +} + +int dm_scan_other(bool pre_reloc_only) +{ + struct sandbox_state *state = state_get_current(); + int busnum, cs; + + if (pre_reloc_only) + return 0; + for (busnum = 0; busnum < CONFIG_SANDBOX_SPI_MAX_BUS; busnum++) { + for (cs = 0; cs < CONFIG_SANDBOX_SPI_MAX_CS; cs++) { + const char *spec = state->spi[busnum][cs].spec; + int ret; + + if (spec) { + ret = sandbox_sf_bind_bus_cs(state, busnum, + cs, spec); + if (ret) { + debug("%s: Bind failed for bus %d, cs %d\n", + __func__, busnum, cs); + return ret; + } + } + } + } + + return 0; +} +#endif + +static const struct udevice_id sandbox_sf_ids[] = { + { .compatible = "sandbox,spi-flash" }, + { } +}; + +U_BOOT_DRIVER(sandbox_sf_emul) = { + .name = "sandbox_sf_emul", + .id = UCLASS_SPI_EMUL, + .of_match = sandbox_sf_ids, + .ofdata_to_platdata = sandbox_sf_ofdata_to_platdata, + .probe = sandbox_sf_probe, + .remove = sandbox_sf_remove, + .priv_auto_alloc_size = sizeof(struct sandbox_spi_flash), + .platdata_auto_alloc_size = sizeof(struct sandbox_spi_flash_plat_data), + .ops = &sandbox_sf_emul_ops, +}; diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c new file mode 100644 index 0000000000..376d815026 --- /dev/null +++ b/drivers/mtd/spi/sf-uclass.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "sf_internal.h" + +/* + * TODO(sjg@chromium.org): This is an old-style function. We should remove + * it when all SPI flash drivers use dm + */ +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct udevice *dev; + + if (spi_flash_probe_bus_cs(bus, cs, max_hz, spi_mode, &dev)) + return NULL; + + return dev->uclass_priv; +} + +void spi_flash_free(struct spi_flash *flash) +{ + spi_flash_remove(flash->spi->dev); +} + +int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode, + struct udevice **devp) +{ + struct spi_slave *slave; + struct udevice *bus; + char name[20], *str; + int ret; + + snprintf(name, sizeof(name), "%d:%d", busnum, cs); + str = strdup(name); + ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode, + "spi_flash_std", str, &bus, &slave); + if (ret) + return ret; + + *devp = slave->dev; + return 0; +} + +int spi_flash_remove(struct udevice *dev) +{ + return device_remove(dev); +} + +UCLASS_DRIVER(spi_flash) = { + .id = UCLASS_SPI_FLASH, + .name = "spi_flash", + .per_device_auto_alloc_size = sizeof(struct spi_flash), +}; diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c new file mode 100644 index 0000000000..664e86082b --- /dev/null +++ b/drivers/mtd/spi/sf.c @@ -0,0 +1,58 @@ +/* + * SPI flash interface + * + * Copyright (C) 2008 Atmel Corporation + * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +static int spi_flash_read_write(struct spi_slave *spi, + const u8 *cmd, size_t cmd_len, + const u8 *data_out, u8 *data_in, + size_t data_len) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + +#ifdef CONFIG_SF_DUAL_FLASH + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; +#endif + if (data_len == 0) + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("SF: Failed to send command (%zu bytes): %d\n", + cmd_len, ret); + } else if (data_len != 0) { + ret = spi_xfer(spi, data_len * 8, data_out, data_in, + SPI_XFER_END); + if (ret) + debug("SF: Failed to transfer %zu bytes of data: %d\n", + data_len, ret); + } + + return ret; +} + +int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len) +{ + return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len); +} + +int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) +{ + return spi_flash_cmd_read(spi, &cmd, 1, response, len); +} + +int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, + const void *data, size_t data_len) +{ + return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len); +} diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h new file mode 100644 index 0000000000..785f7a96fe --- /dev/null +++ b/drivers/mtd/spi/sf_internal.h @@ -0,0 +1,224 @@ +/* + * SPI flash internal definitions + * + * Copyright (C) 2008 Atmel Corporation + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SF_INTERNAL_H_ +#define _SF_INTERNAL_H_ + +#include +#include + +/* Dual SPI flash memories - see SPI_COMM_DUAL_... */ +enum spi_dual_flash { + SF_SINGLE_FLASH = 0, + SF_DUAL_STACKED_FLASH = 1 << 0, + SF_DUAL_PARALLEL_FLASH = 1 << 1, +}; + +/* Enum list - Full read commands */ +enum spi_read_cmds { + ARRAY_SLOW = 1 << 0, + ARRAY_FAST = 1 << 1, + DUAL_OUTPUT_FAST = 1 << 2, + DUAL_IO_FAST = 1 << 3, + QUAD_OUTPUT_FAST = 1 << 4, + QUAD_IO_FAST = 1 << 5, +}; + +/* Normal - Extended - Full command set */ +#define RD_NORM (ARRAY_SLOW | ARRAY_FAST) +#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) +#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) + +/* sf param flags */ +enum { + SECT_4K = 1 << 0, + SECT_32K = 1 << 1, + E_FSR = 1 << 2, + SST_BP = 1 << 3, + SST_WP = 1 << 4, + WR_QPP = 1 << 5, +}; + +#define SST_WR (SST_BP | SST_WP) + +#define SPI_FLASH_3B_ADDR_LEN 3 +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_16MB_BOUN 0x1000000 + +/* CFI Manufacture ID's */ +#define SPI_FLASH_CFI_MFR_SPANSION 0x01 +#define SPI_FLASH_CFI_MFR_STMICRO 0x20 +#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 +#define SPI_FLASH_CFI_MFR_WINBOND 0xef + +/* Erase commands */ +#define CMD_ERASE_4K 0x20 +#define CMD_ERASE_32K 0x52 +#define CMD_ERASE_CHIP 0xc7 +#define CMD_ERASE_64K 0xd8 + +/* Write commands */ +#define CMD_WRITE_STATUS 0x01 +#define CMD_PAGE_PROGRAM 0x02 +#define CMD_WRITE_DISABLE 0x04 +#define CMD_READ_STATUS 0x05 +#define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_READ_STATUS1 0x35 +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_CONFIG 0x35 +#define CMD_FLAG_STATUS 0x70 + +/* Read commands */ +#define CMD_READ_ARRAY_SLOW 0x03 +#define CMD_READ_ARRAY_FAST 0x0b +#define CMD_READ_DUAL_OUTPUT_FAST 0x3b +#define CMD_READ_DUAL_IO_FAST 0xbb +#define CMD_READ_QUAD_OUTPUT_FAST 0x6b +#define CMD_READ_QUAD_IO_FAST 0xeb +#define CMD_READ_ID 0x9f + +/* Bank addr access commands */ +#ifdef CONFIG_SPI_FLASH_BAR +# define CMD_BANKADDR_BRWR 0x17 +# define CMD_BANKADDR_BRRD 0x16 +# define CMD_EXTNADDR_WREAR 0xC5 +# define CMD_EXTNADDR_RDEAR 0xC8 +#endif + +/* Common status */ +#define STATUS_WIP (1 << 0) +#define STATUS_QEB_WINSPAN (1 << 1) +#define STATUS_QEB_MXIC (1 << 6) +#define STATUS_PEC (1 << 7) + +#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN +#define STATUS_SRWD (1 << 7) /* SR write protect */ +#endif + +/* Flash timeout values */ +#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) +#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) +#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) + +/* SST specific */ +#ifdef CONFIG_SPI_FLASH_SST +# define CMD_SST_BP 0x02 /* Byte Program */ +# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ + +int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); +#endif + +/** + * struct spi_flash_params - SPI/QSPI flash device params structure + * + * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) + * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) + * @ext_jedec: Device ext_jedec ID + * @sector_size: Sector size of this device + * @nr_sectors: No.of sectors on this device + * @e_rd_cmd: Enum list for read commands + * @flags: Important param, for flash specific behaviour + */ +struct spi_flash_params { + const char *name; + u32 jedec; + u16 ext_jedec; + u32 sector_size; + u32 nr_sectors; + u8 e_rd_cmd; + u16 flags; +}; + +extern const struct spi_flash_params spi_flash_params_table[]; + +/* Send a single-byte command to the device and read the response */ +int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); + +/* + * Send a multi-byte command to the device and read the response. Used + * for flash array reads, etc. + */ +int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len); + +/* + * Send a multi-byte command to the device followed by (optional) + * data. Used for programming the flash array, etc. + */ +int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, + const void *data, size_t data_len); + + +/* Flash erase(sectors) operation, support all possible erase commands */ +int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); + +/* Read the status register */ +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); + +/* Program the status register */ +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); + +/* Read the config register */ +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); + +/* Program the config register */ +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); + +/* Enable writing on the SPI flash */ +static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); +} + +/* Disable writing on the SPI flash */ +static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); +} + +/* + * Send the read status command to the device and wait for the wip + * (write-in-progress) bit to clear itself. + */ +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); + +/* + * Used for spi_flash write operation + * - SPI claim + * - spi_flash_cmd_write_enable + * - spi_flash_cmd_write + * - spi_flash_cmd_wait_ready + * - SPI release + */ +int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, const void *buf, size_t buf_len); + +/* + * Flash write operation, support all possible write commands. + * Write the requested data out breaking it up into multiple write + * commands as needed per the write size. + */ +int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + size_t len, const void *buf); + +/* + * Same as spi_flash_cmd_read() except it also claims/releases the SPI + * bus. Used as common part of the ->read() operation. + */ +int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len); + +/* Flash read operation, support all possible read commands */ +int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + size_t len, void *data); + +#endif /* _SF_INTERNAL_H_ */ diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c new file mode 100644 index 0000000000..34bc54e73e --- /dev/null +++ b/drivers/mtd/spi/sf_ops.c @@ -0,0 +1,551 @@ +/* + * SPI flash operations + * + * Copyright (C) 2008 Atmel Corporation + * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "sf_internal.h" + +static void spi_flash_addr(u32 addr, u8 *cmd) +{ + /* cmd[0] is actual command */ + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; +} + +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs) +{ + int ret; + u8 cmd; + + cmd = CMD_READ_STATUS; + ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); + if (ret < 0) { + debug("SF: fail to read status register\n"); + return ret; + } + + return 0; +} + +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws) +{ + u8 cmd; + int ret; + + cmd = CMD_WRITE_STATUS; + ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); + if (ret < 0) { + debug("SF: fail to write status register\n"); + return ret; + } + + return 0; +} + +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc) +{ + int ret; + u8 cmd; + + cmd = CMD_READ_CONFIG; + ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return ret; + } + + return 0; +} + +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) +{ + u8 data[2]; + u8 cmd; + int ret; + + ret = spi_flash_cmd_read_status(flash, &data[0]); + if (ret < 0) + return ret; + + cmd = CMD_WRITE_STATUS; + data[1] = wc; + ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); + if (ret) { + debug("SF: fail to write config register\n"); + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_SPI_FLASH_BAR +static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) +{ + u8 cmd; + int ret; + + if (flash->bank_curr == bank_sel) { + debug("SF: not require to enable bank%d\n", bank_sel); + return 0; + } + + cmd = flash->bank_write_cmd; + ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); + if (ret < 0) { + debug("SF: fail to write bank register\n"); + return ret; + } + flash->bank_curr = bank_sel; + + return 0; +} + +static int spi_flash_bank(struct spi_flash *flash, u32 offset) +{ + u8 bank_sel; + int ret; + + bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); + + ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); + if (ret) { + debug("SF: fail to set bank%d\n", bank_sel); + return ret; + } + + return bank_sel; +} +#endif + +#ifdef CONFIG_SF_DUAL_FLASH +static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) +{ + switch (flash->dual_flash) { + case SF_DUAL_STACKED_FLASH: + if (*addr >= (flash->size >> 1)) { + *addr -= flash->size >> 1; + flash->spi->flags |= SPI_XFER_U_PAGE; + } else { + flash->spi->flags &= ~SPI_XFER_U_PAGE; + } + break; + case SF_DUAL_PARALLEL_FLASH: + *addr >>= flash->shift; + break; + default: + debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); + break; + } +} +#endif + +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + unsigned long flags = SPI_XFER_BEGIN; + int ret; + u8 status; + u8 check_status = 0x0; + u8 poll_bit = STATUS_WIP; + u8 cmd = flash->poll_cmd; + + if (cmd == CMD_FLAG_STATUS) { + poll_bit = STATUS_PEC; + check_status = poll_bit; + } + +#ifdef CONFIG_SF_DUAL_FLASH + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; +#endif + ret = spi_xfer(spi, 8, &cmd, NULL, flags); + if (ret) { + debug("SF: fail to read %s status register\n", + cmd == CMD_READ_STATUS ? "read" : "flag"); + return ret; + } + + timebase = get_timer(0); + do { + WATCHDOG_RESET(); + + ret = spi_xfer(spi, 8, NULL, &status, 0); + if (ret) + return -1; + + if ((status & poll_bit) == check_status) + break; + + } while (get_timer(timebase) < timeout); + + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); + + if ((status & poll_bit) == check_status) + return 0; + + /* Timed out */ + debug("SF: time out!\n"); + return -1; +} + +int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, const void *buf, size_t buf_len) +{ + struct spi_slave *spi = flash->spi; + unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; + int ret; + + if (buf == NULL) + timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } + + ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); + if (ret < 0) { + debug("SF: write cmd failed\n"); + return ret; + } + + ret = spi_flash_cmd_wait_ready(flash, timeout); + if (ret < 0) { + debug("SF: write %s timed out\n", + timeout == SPI_FLASH_PROG_TIMEOUT ? + "program" : "page erase"); + return ret; + } + + spi_release_bus(spi); + + return ret; +} + +int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) +{ + u32 erase_size, erase_addr; + u8 cmd[SPI_FLASH_CMD_LEN]; + int ret = -1; + + erase_size = flash->erase_size; + if (offset % erase_size || len % erase_size) { + debug("SF: Erase offset/length not multiple of erase size\n"); + return -1; + } + + cmd[0] = flash->erase_cmd; + while (len) { + erase_addr = offset; + +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &erase_addr); +#endif +#ifdef CONFIG_SPI_FLASH_BAR + ret = spi_flash_bank(flash, erase_addr); + if (ret < 0) + return ret; +#endif + spi_flash_addr(erase_addr, cmd); + + debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], + cmd[2], cmd[3], erase_addr); + + ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); + if (ret < 0) { + debug("SF: erase failed\n"); + break; + } + + offset += erase_size; + len -= erase_size; + } + + return ret; +} + +int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + unsigned long byte_addr, page_size; + u32 write_addr; + size_t chunk_len, actual; + u8 cmd[SPI_FLASH_CMD_LEN]; + int ret = -1; + + page_size = flash->page_size; + + cmd[0] = flash->write_cmd; + for (actual = 0; actual < len; actual += chunk_len) { + write_addr = offset; + +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &write_addr); +#endif +#ifdef CONFIG_SPI_FLASH_BAR + ret = spi_flash_bank(flash, write_addr); + if (ret < 0) + return ret; +#endif + byte_addr = offset % page_size; + chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); + + if (flash->spi->max_write_size) + chunk_len = min(chunk_len, + (size_t)flash->spi->max_write_size); + + spi_flash_addr(write_addr, cmd); + + debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_write_common(flash, cmd, sizeof(cmd), + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: write failed\n"); + break; + } + + offset += chunk_len; + } + + return ret; +} + +int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len) +{ + struct spi_slave *spi = flash->spi; + int ret; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); + if (ret < 0) { + debug("SF: read cmd failed\n"); + return ret; + } + + spi_release_bus(spi); + + return ret; +} + +int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + size_t len, void *data) +{ + u8 *cmd, cmdsz; + u32 remain_len, read_len, read_addr; + int bank_sel = 0; + int ret = -1; + + /* Handle memory-mapped SPI */ + if (flash->memory_map) { + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP); + memcpy(data, flash->memory_map + offset, len); + spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END); + spi_release_bus(flash->spi); + return 0; + } + + cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmd = calloc(1, cmdsz); + if (!cmd) { + debug("SF: Failed to allocate cmd\n"); + return -ENOMEM; + } + + cmd[0] = flash->read_cmd; + while (len) { + read_addr = offset; + +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &read_addr); +#endif +#ifdef CONFIG_SPI_FLASH_BAR + bank_sel = spi_flash_bank(flash, read_addr); + if (bank_sel < 0) + return ret; +#endif + remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * + (bank_sel + 1)) - offset; + if (len < remain_len) + read_len = len; + else + read_len = remain_len; + + spi_flash_addr(read_addr, cmd); + + ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); + if (ret < 0) { + debug("SF: read failed\n"); + break; + } + + offset += read_len; + len -= read_len; + data += read_len; + } + + free(cmd); + return ret; +} + +#ifdef CONFIG_SPI_FLASH_SST +static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) +{ + int ret; + u8 cmd[4] = { + CMD_SST_BP, + offset >> 16, + offset >> 8, + offset, + }; + + debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); + + ret = spi_flash_cmd_write_enable(flash); + if (ret) + return ret; + + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); + if (ret) + return ret; + + return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); +} + +int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf) +{ + size_t actual, cmd_len; + int ret; + u8 cmd[4]; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + /* If the data is not word aligned, write out leading single byte */ + actual = offset % 2; + if (actual) { + ret = sst_byte_write(flash, offset, buf); + if (ret) + goto done; + } + offset += actual; + + ret = spi_flash_cmd_write_enable(flash); + if (ret) + goto done; + + cmd_len = 4; + cmd[0] = CMD_SST_AAI_WP; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + + for (; actual < len - 1; actual += 2) { + debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, + cmd[0], offset); + + ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, + buf + actual, 2); + if (ret) { + debug("SF: sst word program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + cmd_len = 1; + offset += 2; + } + + if (!ret) + ret = spi_flash_cmd_write_disable(flash); + + /* If there is a single trailing byte, write it out */ + if (!ret && actual != len) + ret = sst_byte_write(flash, offset, buf + actual); + + done: + debug("SF: sst: program %s %zu bytes @ 0x%zx\n", + ret ? "failure" : "success", len, offset - actual); + + spi_release_bus(flash->spi); + return ret; +} + +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf) +{ + size_t actual; + int ret; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual++) { + ret = sst_byte_write(flash, offset, buf + actual); + if (ret) { + debug("SF: sst byte program failed\n"); + break; + } + offset++; + } + + if (!ret) + ret = spi_flash_cmd_write_disable(flash); + + debug("SF: sst: program %s %zu bytes @ 0x%zx\n", + ret ? "failure" : "success", len, offset - actual); + + spi_release_bus(flash->spi); + return ret; +} +#endif diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c new file mode 100644 index 0000000000..c12e8c6fe7 --- /dev/null +++ b/drivers/mtd/spi/sf_params.c @@ -0,0 +1,140 @@ +/* + * SPI flash Params table + * + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "sf_internal.h" + +/* SPI/QSPI flash device params structure */ +const struct spi_flash_params spi_flash_params_table[] = { +#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ + {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K}, + {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, + {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, + {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, + {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, + {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, + {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_EON /* EON */ + {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0}, + {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0}, +#endif +#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ + {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ + {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, + {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0}, + {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0}, + {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, +#endif +#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ + {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0}, + {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, RD_NORM, 0}, + {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, RD_NORM, 0}, + {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, + {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, + {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, + {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP}, + {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP}, + {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP}, + {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP}, +#endif +#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ + {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0}, + {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0}, + {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0}, + {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0}, + {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0}, + {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, + {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, + {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_SST /* SST */ + {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, + {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, + {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR}, + {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR}, + {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, +#endif +#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ + {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, + {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, + {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, + {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, +#endif + {}, /* Empty entry to terminate the list */ + /* + * Note: + * Below paired flash devices has similar spi_flash params. + * (S25FL129P_64K, S25FL128S_64K) + * (W25Q80BL, W25Q80BV) + * (W25Q16CL, W25Q16DV) + * (W25Q32BV, W25Q32FV_SPI) + * (W25Q64CV, W25Q64FV_SPI) + * (W25Q128BV, W25Q128FV_SPI) + * (W25Q32DW, W25Q32FV_QPI) + * (W25Q64DW, W25Q64FV_QPI) + * (W25Q128FW, W25Q128FV_QPI) + */ +}; diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c new file mode 100644 index 0000000000..4103723859 --- /dev/null +++ b/drivers/mtd/spi/sf_probe.c @@ -0,0 +1,513 @@ +/* + * SPI flash probing + * + * Copyright (C) 2008 Atmel Corporation + * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sf_internal.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* Read commands array */ +static u8 spi_read_cmds_array[] = { + CMD_READ_ARRAY_SLOW, + CMD_READ_ARRAY_FAST, + CMD_READ_DUAL_OUTPUT_FAST, + CMD_READ_DUAL_IO_FAST, + CMD_READ_QUAD_OUTPUT_FAST, + CMD_READ_QUAD_IO_FAST, +}; + +#ifdef CONFIG_SPI_FLASH_MACRONIX +static int spi_flash_set_qeb_mxic(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = spi_flash_cmd_read_status(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_MXIC) { + debug("SF: mxic: QEB is already set\n"); + } else { + ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC); + if (ret < 0) + return ret; + } + + return ret; +} +#endif + +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +static int spi_flash_set_qeb_winspan(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = spi_flash_cmd_read_config(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_WINSPAN) { + debug("SF: winspan: QEB is already set\n"); + } else { + ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN); + if (ret < 0) + return ret; + } + + return ret; +} +#endif + +static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) +{ + switch (idcode0) { +#ifdef CONFIG_SPI_FLASH_MACRONIX + case SPI_FLASH_CFI_MFR_MACRONIX: + return spi_flash_set_qeb_mxic(flash); +#endif +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) + case SPI_FLASH_CFI_MFR_SPANSION: + case SPI_FLASH_CFI_MFR_WINBOND: + return spi_flash_set_qeb_winspan(flash); +#endif +#ifdef CONFIG_SPI_FLASH_STMICRO + case SPI_FLASH_CFI_MFR_STMICRO: + debug("SF: QEB is volatile for %02x flash\n", idcode0); + return 0; +#endif + default: + printf("SF: Need set QEB func for %02x flash\n", idcode0); + return -1; + } +} + +static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, + struct spi_flash *flash) +{ + const struct spi_flash_params *params; + u8 cmd; + u16 jedec = idcode[1] << 8 | idcode[2]; + u16 ext_jedec = idcode[3] << 8 | idcode[4]; + + /* Validate params from spi_flash_params table */ + params = spi_flash_params_table; + for (; params->name != NULL; params++) { + if ((params->jedec >> 16) == idcode[0]) { + if ((params->jedec & 0xFFFF) == jedec) { + if (params->ext_jedec == 0) + break; + else if (params->ext_jedec == ext_jedec) + break; + } + } + } + + if (!params->name) { + printf("SF: Unsupported flash IDs: "); + printf("manuf %02x, jedec %04x, ext_jedec %04x\n", + idcode[0], jedec, ext_jedec); + return -EPROTONOSUPPORT; + } + + /* Assign spi data */ + flash->spi = spi; + flash->name = params->name; + flash->memory_map = spi->memory_map; + flash->dual_flash = flash->spi->option; + + /* Assign spi_flash ops */ +#ifndef CONFIG_DM_SPI_FLASH + flash->write = spi_flash_cmd_write_ops; +#if defined(CONFIG_SPI_FLASH_SST) + if (params->flags & SST_WR) { + if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + flash->write = sst_write_bp; + else + flash->write = sst_write_wp; + } +#endif + flash->erase = spi_flash_cmd_erase_ops; + flash->read = spi_flash_cmd_read_ops; +#endif + + /* Compute the flash size */ + flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; + /* + * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the + * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with + * the 0x4d00 Extended JEDEC code have 512b pages. All of the others + * have 256b pages. + */ + if (ext_jedec == 0x4d00) { + if ((jedec == 0x0215) || (jedec == 0x216)) + flash->page_size = 256; + else + flash->page_size = 512; + } else { + flash->page_size = 256; + } + flash->page_size <<= flash->shift; + flash->sector_size = params->sector_size << flash->shift; + flash->size = flash->sector_size * params->nr_sectors << flash->shift; +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash & SF_DUAL_STACKED_FLASH) + flash->size <<= 1; +#endif + + /* Compute erase sector and command */ + if (params->flags & SECT_4K) { + flash->erase_cmd = CMD_ERASE_4K; + flash->erase_size = 4096 << flash->shift; + } else if (params->flags & SECT_32K) { + flash->erase_cmd = CMD_ERASE_32K; + flash->erase_size = 32768 << flash->shift; + } else { + flash->erase_cmd = CMD_ERASE_64K; + flash->erase_size = flash->sector_size; + } + + /* Look for the fastest read cmd */ + cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); + if (cmd) { + cmd = spi_read_cmds_array[cmd - 1]; + flash->read_cmd = cmd; + } else { + /* Go for default supported read cmd */ + flash->read_cmd = CMD_READ_ARRAY_FAST; + } + + /* Not require to look for fastest only two write cmds yet */ + if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) + flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; + else + /* Go for default supported write cmd */ + flash->write_cmd = CMD_PAGE_PROGRAM; + + /* Read dummy_byte: dummy byte is determined based on the + * dummy cycles of a particular command. + * Fast commands - dummy_byte = dummy_cycles/8 + * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 + * For I/O commands except cmd[0] everything goes on no.of lines + * based on particular command but incase of fast commands except + * data all go on single line irrespective of command. + */ + switch (flash->read_cmd) { + case CMD_READ_QUAD_IO_FAST: + flash->dummy_byte = 2; + break; + case CMD_READ_ARRAY_SLOW: + flash->dummy_byte = 0; + break; + default: + flash->dummy_byte = 1; + } + + /* Poll cmd selection */ + flash->poll_cmd = CMD_READ_STATUS; +#ifdef CONFIG_SPI_FLASH_STMICRO + if (params->flags & E_FSR) + flash->poll_cmd = CMD_FLAG_STATUS; +#endif + + /* Configure the BAR - discover bank cmds and read current bank */ +#ifdef CONFIG_SPI_FLASH_BAR + u8 curr_bank = 0; + if (flash->size > SPI_FLASH_16MB_BOUN) { + int ret; + + flash->bank_read_cmd = (idcode[0] == 0x01) ? + CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR; + flash->bank_write_cmd = (idcode[0] == 0x01) ? + CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR; + + ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, + &curr_bank, 1); + if (ret) { + debug("SF: fail to read bank addr register\n"); + return ret; + } + flash->bank_curr = curr_bank; + } else { + flash->bank_curr = curr_bank; + } +#endif + + /* Flash powers up read-only, so clear BP# bits */ +#if defined(CONFIG_SPI_FLASH_ATMEL) || \ + defined(CONFIG_SPI_FLASH_MACRONIX) || \ + defined(CONFIG_SPI_FLASH_SST) + spi_flash_cmd_write_status(flash, 0); +#endif + + return 0; +} + +#ifdef CONFIG_OF_CONTROL +int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) +{ + fdt_addr_t addr; + fdt_size_t size; + int node; + + /* If there is no node, do nothing */ + node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); + if (node < 0) + return 0; + + addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); + if (addr == FDT_ADDR_T_NONE) { + debug("%s: Cannot decode address\n", __func__); + return 0; + } + + if (flash->size != size) { + debug("%s: Memory map must cover entire device\n", __func__); + return -1; + } + flash->memory_map = map_sysmem(addr, size); + + return 0; +} +#endif /* CONFIG_OF_CONTROL */ + +#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN +/* enable the W#/Vpp signal to disable writing to the status register */ +static int spi_enable_wp_pin(struct spi_flash *flash) +{ + u8 status; + int ret; + + ret = spi_flash_cmd_read_status(flash, &status); + if (ret < 0) + return ret; + + ret = spi_flash_cmd_write_status(flash, STATUS_SRWD); + if (ret < 0) + return ret; + + ret = spi_flash_cmd_write_disable(flash); + if (ret < 0) + return ret; + + return 0; +} +#else +static int spi_enable_wp_pin(struct spi_flash *flash) +{ + return 0; +} +#endif + +/** + * spi_flash_probe_slave() - Probe for a SPI flash device on a bus + * + * @spi: Bus to probe + * @flashp: Pointer to place to put flash info, which may be NULL if the + * space should be allocated + */ +int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) +{ + u8 idcode[5]; + int ret; + + /* Setup spi_slave */ + if (!spi) { + printf("SF: Failed to set up slave\n"); + return -ENODEV; + } + + /* Claim spi bus */ + ret = spi_claim_bus(spi); + if (ret) { + debug("SF: Failed to claim SPI bus: %d\n", ret); + return ret; + } + + /* Read the ID codes */ + ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); + if (ret) { + printf("SF: Failed to get idcodes\n"); + goto err_read_id; + } + +#ifdef DEBUG + printf("SF: Got idcodes\n"); + print_buffer(0, idcode, 1, sizeof(idcode), 0); +#endif + + if (spi_flash_validate_params(spi, idcode, flash)) { + ret = -EINVAL; + goto err_read_id; + } + + /* Set the quad enable bit - only for quad commands */ + if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || + (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || + (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { + if (spi_flash_set_qeb(flash, idcode[0])) { + debug("SF: Fail to set QEB for %02x\n", idcode[0]); + ret = -EINVAL; + goto err_read_id; + } + } + +#ifdef CONFIG_OF_CONTROL + if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { + debug("SF: FDT decode error\n"); + ret = -EINVAL; + goto err_read_id; + } +#endif +#ifndef CONFIG_SPL_BUILD + printf("SF: Detected %s with page size ", flash->name); + print_size(flash->page_size, ", erase size "); + print_size(flash->erase_size, ", total "); + print_size(flash->size, ""); + if (flash->memory_map) + printf(", mapped at %p", flash->memory_map); + puts("\n"); +#endif +#ifndef CONFIG_SPI_FLASH_BAR + if (((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || + ((flash->dual_flash > SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN << 1))) { + puts("SF: Warning - Only lower 16MiB accessible,"); + puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); + } +#endif + if (spi_enable_wp_pin(flash)) + puts("Enable WP pin failed\n"); + + /* Release spi bus */ + spi_release_bus(spi); + + return 0; + +err_read_id: + spi_release_bus(spi); + return ret; +} + +#ifndef CONFIG_DM_SPI_FLASH +struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus) +{ + struct spi_flash *flash; + + /* Allocate space if needed (not used by sf-uclass */ + flash = calloc(1, sizeof(*flash)); + if (!flash) { + debug("SF: Failed to allocate spi_flash\n"); + return NULL; + } + + if (spi_flash_probe_slave(bus, flash)) { + spi_free_slave(bus); + free(flash); + return NULL; + } + + return flash; +} + +struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *bus; + + bus = spi_setup_slave(busnum, cs, max_hz, spi_mode); + return spi_flash_probe_tail(bus); +} + +#ifdef CONFIG_OF_SPI_FLASH +struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node, + int spi_node) +{ + struct spi_slave *bus; + + bus = spi_setup_slave_fdt(blob, slave_node, spi_node); + return spi_flash_probe_tail(bus); +} +#endif + +void spi_flash_free(struct spi_flash *flash) +{ + spi_free_slave(flash->spi); + free(flash); +} + +#else /* defined CONFIG_DM_SPI_FLASH */ + +static int spi_flash_std_read(struct udevice *dev, u32 offset, size_t len, + void *buf) +{ + struct spi_flash *flash = dev->uclass_priv; + + return spi_flash_cmd_read_ops(flash, offset, len, buf); +} + +int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len, + const void *buf) +{ + struct spi_flash *flash = dev->uclass_priv; + + return spi_flash_cmd_write_ops(flash, offset, len, buf); +} + +int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len) +{ + struct spi_flash *flash = dev->uclass_priv; + + return spi_flash_cmd_erase_ops(flash, offset, len); +} + +int spi_flash_std_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parentdata(dev); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + struct spi_flash *flash; + + flash = dev->uclass_priv; + flash->dev = dev; + debug("%s: slave=%p, cs=%d\n", __func__, slave, plat->cs); + return spi_flash_probe_slave(slave, flash); +} + +static const struct dm_spi_flash_ops spi_flash_std_ops = { + .read = spi_flash_std_read, + .write = spi_flash_std_write, + .erase = spi_flash_std_erase, +}; + +static const struct udevice_id spi_flash_std_ids[] = { + { .compatible = "spi-flash" }, + { } +}; + +U_BOOT_DRIVER(spi_flash_std) = { + .name = "spi_flash_std", + .id = UCLASS_SPI_FLASH, + .of_match = spi_flash_std_ids, + .probe = spi_flash_std_probe, + .priv_auto_alloc_size = sizeof(struct spi_flash), + .ops = &spi_flash_std_ops, +}; + +#endif /* CONFIG_DM_SPI_FLASH */ diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c deleted file mode 100644 index 47a48976b9..0000000000 --- a/drivers/mtd/spi/spansion.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2009 Freescale Semiconductor, Inc. - * - * Author: Mingkai Hu (Mingkai.hu@freescale.com) - * Based on stmicro.c by Wolfgang Denk (wd@denx.de), - * TsiChung Liew (Tsi-Chung.Liew@freescale.com), - * and Jason McMullan (mcmullan@netapp.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "spi_flash_internal.h" - -struct spansion_spi_flash_params { - u16 idcode1; - u16 idcode2; - u16 pages_per_sector; - u16 nr_sectors; - const char *name; -}; - -static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { - { - .idcode1 = 0x0213, - .idcode2 = 0, - .pages_per_sector = 256, - .nr_sectors = 16, - .name = "S25FL008A", - }, - { - .idcode1 = 0x0214, - .idcode2 = 0, - .pages_per_sector = 256, - .nr_sectors = 32, - .name = "S25FL016A", - }, - { - .idcode1 = 0x0215, - .idcode2 = 0, - .pages_per_sector = 256, - .nr_sectors = 64, - .name = "S25FL032A", - }, - { - .idcode1 = 0x0216, - .idcode2 = 0, - .pages_per_sector = 256, - .nr_sectors = 128, - .name = "S25FL064A", - }, - { - .idcode1 = 0x2018, - .idcode2 = 0x0301, - .pages_per_sector = 256, - .nr_sectors = 256, - .name = "S25FL128P_64K", - }, - { - .idcode1 = 0x2018, - .idcode2 = 0x0300, - .pages_per_sector = 1024, - .nr_sectors = 64, - .name = "S25FL128P_256K", - }, - { - .idcode1 = 0x0215, - .idcode2 = 0x4d00, - .pages_per_sector = 256, - .nr_sectors = 64, - .name = "S25FL032P", - }, - { - .idcode1 = 0x0216, - .idcode2 = 0x4d00, - .pages_per_sector = 256, - .nr_sectors = 128, - .name = "S25FL064P", - }, - { - .idcode1 = 0x2018, - .idcode2 = 0x4d01, - .pages_per_sector = 256, - .nr_sectors = 256, - .name = "S25FL129P_64K/S25FL128S_64K", - }, - { - .idcode1 = 0x0219, - .idcode2 = 0x4d01, - .pages_per_sector = 256, - .nr_sectors = 512, - .name = "S25FL256S_64K", - }, - { - .idcode1 = 0x0220, - .idcode2 = 0x4d01, - .pages_per_sector = 256, - .nr_sectors = 1024, - .name = "S25FL512S_64K", - }, -}; - -struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) -{ - const struct spansion_spi_flash_params *params; - struct spi_flash *flash; - unsigned int i; - unsigned short jedec, ext_jedec; - - jedec = idcode[1] << 8 | idcode[2]; - ext_jedec = idcode[3] << 8 | idcode[4]; - - for (i = 0; i < ARRAY_SIZE(spansion_spi_flash_table); i++) { - params = &spansion_spi_flash_table[i]; - if (params->idcode1 == jedec) { - if (params->idcode2 == ext_jedec) - break; - } - } - - if (i == ARRAY_SIZE(spansion_spi_flash_table)) { - debug("SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec); - return NULL; - } - - flash = spi_flash_alloc_base(spi, params->name); - if (!flash) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - - flash->page_size = 256; - flash->sector_size = 256 * params->pages_per_sector; - flash->size = flash->sector_size * params->nr_sectors; - - return flash; -} diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c deleted file mode 100644 index 6a6fe37e0e..0000000000 --- a/drivers/mtd/spi/spi_flash.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * SPI flash interface - * - * Copyright (C) 2008 Atmel Corporation - * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include - -#include "spi_flash_internal.h" - -DECLARE_GLOBAL_DATA_PTR; - -static void spi_flash_addr(u32 addr, u8 *cmd) -{ - /* cmd[0] is actual command */ - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr >> 0; -} - -static int spi_flash_read_write(struct spi_slave *spi, - const u8 *cmd, size_t cmd_len, - const u8 *data_out, u8 *data_in, - size_t data_len) -{ - unsigned long flags = SPI_XFER_BEGIN; - int ret; - - if (data_len == 0) - flags |= SPI_XFER_END; - - ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); - if (ret) { - debug("SF: Failed to send command (%zu bytes): %d\n", - cmd_len, ret); - } else if (data_len != 0) { - ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END); - if (ret) - debug("SF: Failed to transfer %zu bytes of data: %d\n", - data_len, ret); - } - - return ret; -} - -int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) -{ - return spi_flash_cmd_read(spi, &cmd, 1, response, len); -} - -int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, - size_t cmd_len, void *data, size_t data_len) -{ - return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len); -} - -int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, - const void *data, size_t data_len) -{ - return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len); -} - -int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) -{ - struct spi_slave *spi = flash->spi; - unsigned long timebase; - int ret; - u8 status; - u8 check_status = 0x0; - u8 poll_bit = STATUS_WIP; - u8 cmd = flash->poll_cmd; - - if (cmd == CMD_FLAG_STATUS) { - poll_bit = STATUS_PEC; - check_status = poll_bit; - } - - ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); - if (ret) { - debug("SF: fail to read %s status register\n", - cmd == CMD_READ_STATUS ? "read" : "flag"); - return ret; - } - - timebase = get_timer(0); - do { - WATCHDOG_RESET(); - - ret = spi_xfer(spi, 8, NULL, &status, 0); - if (ret) - return -1; - - if ((status & poll_bit) == check_status) - break; - - } while (get_timer(timebase) < timeout); - - spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); - - if ((status & poll_bit) == check_status) - return 0; - - /* Timed out */ - debug("SF: time out!\n"); - return -1; -} - -int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, - size_t cmd_len, const void *buf, size_t buf_len) -{ - struct spi_slave *spi = flash->spi; - unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; - int ret; - - if (buf == NULL) - timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: unable to claim SPI bus\n"); - return ret; - } - - ret = spi_flash_cmd_write_enable(flash); - if (ret < 0) { - debug("SF: enabling write failed\n"); - return ret; - } - - ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); - if (ret < 0) { - debug("SF: write cmd failed\n"); - return ret; - } - - ret = spi_flash_cmd_wait_ready(flash, timeout); - if (ret < 0) { - debug("SF: write %s timed out\n", - timeout == SPI_FLASH_PROG_TIMEOUT ? - "program" : "page erase"); - return ret; - } - - spi_release_bus(spi); - - return ret; -} - -int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - u32 erase_size; - u8 cmd[4]; - int ret = -1; - - erase_size = flash->sector_size; - if (offset % erase_size || len % erase_size) { - debug("SF: Erase offset/length not multiple of erase size\n"); - return -1; - } - - if (erase_size == 4096) - cmd[0] = CMD_ERASE_4K; - else - cmd[0] = CMD_ERASE_64K; - - while (len) { -#ifdef CONFIG_SPI_FLASH_BAR - u8 bank_sel; - - bank_sel = offset / SPI_FLASH_16MB_BOUN; - - ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); - if (ret) { - debug("SF: fail to set bank%d\n", bank_sel); - return ret; - } -#endif - spi_flash_addr(offset, cmd); - - debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], - cmd[2], cmd[3], offset); - - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); - if (ret < 0) { - debug("SF: erase failed\n"); - break; - } - - offset += erase_size; - len -= erase_size; - } - - return ret; -} - -int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, - size_t len, const void *buf) -{ - unsigned long byte_addr, page_size; - size_t chunk_len, actual; - u8 cmd[4]; - int ret = -1; - - page_size = flash->page_size; - - cmd[0] = CMD_PAGE_PROGRAM; - for (actual = 0; actual < len; actual += chunk_len) { -#ifdef CONFIG_SPI_FLASH_BAR - u8 bank_sel; - - bank_sel = offset / SPI_FLASH_16MB_BOUN; - - ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); - if (ret) { - debug("SF: fail to set bank%d\n", bank_sel); - return ret; - } -#endif - byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); - - if (flash->spi->max_write_size) - chunk_len = min(chunk_len, flash->spi->max_write_size); - - spi_flash_addr(offset, cmd); - - debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", - buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: write failed\n"); - break; - } - - offset += chunk_len; - } - - return ret; -} - -int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, - size_t cmd_len, void *data, size_t data_len) -{ - struct spi_slave *spi = flash->spi; - int ret; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: unable to claim SPI bus\n"); - return ret; - } - - ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); - if (ret < 0) { - debug("SF: read cmd failed\n"); - return ret; - } - - spi_release_bus(spi); - - return ret; -} - -int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, - size_t len, void *data) -{ - u8 cmd[5], bank_sel = 0; - u32 remain_len, read_len; - int ret = -1; - - /* Handle memory-mapped SPI */ - if (flash->memory_map) { - memcpy(data, flash->memory_map + offset, len); - return 0; - } - - cmd[0] = CMD_READ_ARRAY_FAST; - cmd[4] = 0x00; - - while (len) { -#ifdef CONFIG_SPI_FLASH_BAR - bank_sel = offset / SPI_FLASH_16MB_BOUN; - - ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); - if (ret) { - debug("SF: fail to set bank%d\n", bank_sel); - return ret; - } -#endif - remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset); - if (len < remain_len) - read_len = len; - else - read_len = remain_len; - - spi_flash_addr(offset, cmd); - - ret = spi_flash_read_common(flash, cmd, sizeof(cmd), - data, read_len); - if (ret < 0) { - debug("SF: read failed\n"); - break; - } - - offset += read_len; - len -= read_len; - data += read_len; - } - - return ret; -} - -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) -{ - u8 cmd; - int ret; - - cmd = CMD_WRITE_STATUS; - ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1); - if (ret < 0) { - debug("SF: fail to write status register\n"); - return ret; - } - - return 0; -} - -#ifdef CONFIG_SPI_FLASH_BAR -int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) -{ - u8 cmd; - int ret; - - if (flash->bank_curr == bank_sel) { - debug("SF: not require to enable bank%d\n", bank_sel); - return 0; - } - - cmd = flash->bank_write_cmd; - ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); - if (ret < 0) { - debug("SF: fail to write bank register\n"); - return ret; - } - flash->bank_curr = bank_sel; - - return 0; -} - -int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0) -{ - u8 cmd; - u8 curr_bank = 0; - - /* discover bank cmds */ - switch (idcode0) { - case SPI_FLASH_SPANSION_IDCODE0: - flash->bank_read_cmd = CMD_BANKADDR_BRRD; - flash->bank_write_cmd = CMD_BANKADDR_BRWR; - break; - case SPI_FLASH_STMICRO_IDCODE0: - case SPI_FLASH_WINBOND_IDCODE0: - flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; - flash->bank_write_cmd = CMD_EXTNADDR_WREAR; - break; - default: - printf("SF: Unsupported bank commands %02x\n", idcode0); - return -1; - } - - /* read the bank reg - on which bank the flash is in currently */ - cmd = flash->bank_read_cmd; - if (flash->size > SPI_FLASH_16MB_BOUN) { - if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) { - debug("SF: fail to read bank addr register\n"); - return -1; - } - flash->bank_curr = curr_bank; - } else { - flash->bank_curr = curr_bank; - } - - return 0; -} -#endif - -#ifdef CONFIG_OF_CONTROL -int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) -{ - fdt_addr_t addr; - fdt_size_t size; - int node; - - /* If there is no node, do nothing */ - node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); - if (node < 0) - return 0; - - addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); - if (addr == FDT_ADDR_T_NONE) { - debug("%s: Cannot decode address\n", __func__); - return 0; - } - - if (flash->size != size) { - debug("%s: Memory map must cover entire device\n", __func__); - return -1; - } - flash->memory_map = (void *)addr; - - return 0; -} -#endif /* CONFIG_OF_CONTROL */ - -/* - * The following table holds all device probe functions - * - * shift: number of continuation bytes before the ID - * idcode: the expected IDCODE or 0xff for non JEDEC devices - * probe: the function to call - * - * Non JEDEC devices should be ordered in the table such that - * the probe functions with best detection algorithms come first. - * - * Several matching entries are permitted, they will be tried - * in sequence until a probe function returns non NULL. - * - * IDCODE_CONT_LEN may be redefined if a device needs to declare a - * larger "shift" value. IDCODE_PART_LEN generally shouldn't be - * changed. This is the max number of bytes probe functions may - * examine when looking up part-specific identification info. - * - * Probe functions will be given the idcode buffer starting at their - * manu id byte (the "idcode" in the table below). In other words, - * all of the continuation bytes will be skipped (the "shift" below). - */ -#define IDCODE_CONT_LEN 0 -#define IDCODE_PART_LEN 5 -static const struct { - const u8 shift; - const u8 idcode; - struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); -} flashes[] = { - /* Keep it sorted by define name */ -#ifdef CONFIG_SPI_FLASH_ATMEL - { 0, 0x1f, spi_flash_probe_atmel, }, -#endif -#ifdef CONFIG_SPI_FLASH_EON - { 0, 0x1c, spi_flash_probe_eon, }, -#endif -#ifdef CONFIG_SPI_FLASH_GIGADEVICE - { 0, 0xc8, spi_flash_probe_gigadevice, }, -#endif -#ifdef CONFIG_SPI_FLASH_MACRONIX - { 0, 0xc2, spi_flash_probe_macronix, }, -#endif -#ifdef CONFIG_SPI_FLASH_SPANSION - { 0, 0x01, spi_flash_probe_spansion, }, -#endif -#ifdef CONFIG_SPI_FLASH_SST - { 0, 0xbf, spi_flash_probe_sst, }, -#endif -#ifdef CONFIG_SPI_FLASH_STMICRO - { 0, 0x20, spi_flash_probe_stmicro, }, -#endif -#ifdef CONFIG_SPI_FLASH_WINBOND - { 0, 0xef, spi_flash_probe_winbond, }, -#endif -#ifdef CONFIG_SPI_FRAM_RAMTRON - { 6, 0xc2, spi_fram_probe_ramtron, }, -# undef IDCODE_CONT_LEN -# define IDCODE_CONT_LEN 6 -#endif - /* Keep it sorted by best detection */ -#ifdef CONFIG_SPI_FLASH_STMICRO - { 0, 0xff, spi_flash_probe_stmicro, }, -#endif -#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC - { 0, 0xff, spi_fram_probe_ramtron, }, -#endif -}; -#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) - -struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int spi_mode) -{ - struct spi_slave *spi; - struct spi_flash *flash = NULL; - int ret, i, shift; - u8 idcode[IDCODE_LEN], *idp; - - spi = spi_setup_slave(bus, cs, max_hz, spi_mode); - if (!spi) { - printf("SF: Failed to set up slave\n"); - return NULL; - } - - ret = spi_claim_bus(spi); - if (ret) { - debug("SF: Failed to claim SPI bus: %d\n", ret); - goto err_claim_bus; - } - - /* Read the ID codes */ - ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); - if (ret) - goto err_read_id; - -#ifdef DEBUG - printf("SF: Got idcodes\n"); - print_buffer(0, idcode, 1, sizeof(idcode), 0); -#endif - - /* count the number of continuation bytes */ - for (shift = 0, idp = idcode; - shift < IDCODE_CONT_LEN && *idp == 0x7f; - ++shift, ++idp) - continue; - - /* search the table for matches in shift and id */ - for (i = 0; i < ARRAY_SIZE(flashes); ++i) - if (flashes[i].shift == shift && flashes[i].idcode == *idp) { - /* we have a match, call probe */ - flash = flashes[i].probe(spi, idp); - if (flash) - break; - } - - if (!flash) { - printf("SF: Unsupported manufacturer %02x\n", *idp); - goto err_manufacturer_probe; - } - -#ifdef CONFIG_SPI_FLASH_BAR - /* Configure the BAR - disover bank cmds and read current bank */ - ret = spi_flash_bank_config(flash, *idp); - if (ret < 0) - goto err_manufacturer_probe; -#endif - -#ifdef CONFIG_OF_CONTROL - if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { - debug("SF: FDT decode error\n"); - goto err_manufacturer_probe; - } -#endif - printf("SF: Detected %s with page size ", flash->name); - print_size(flash->sector_size, ", total "); - print_size(flash->size, ""); - if (flash->memory_map) - printf(", mapped at %p", flash->memory_map); - puts("\n"); -#ifndef CONFIG_SPI_FLASH_BAR - if (flash->size > SPI_FLASH_16MB_BOUN) { - puts("SF: Warning - Only lower 16MiB accessible,"); - puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); - } -#endif - - spi_release_bus(spi); - - return flash; - -err_manufacturer_probe: -err_read_id: - spi_release_bus(spi); -err_claim_bus: - spi_free_slave(spi); - return NULL; -} - -void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, - const char *name) -{ - struct spi_flash *flash; - void *ptr; - - ptr = malloc(size); - if (!ptr) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - memset(ptr, '\0', size); - flash = (struct spi_flash *)(ptr + offset); - - /* Set up some basic fields - caller will sort out sizes */ - flash->spi = spi; - flash->name = name; - flash->poll_cmd = CMD_READ_STATUS; - - flash->read = spi_flash_cmd_read_fast; - flash->write = spi_flash_cmd_write_multi; - flash->erase = spi_flash_cmd_erase; - - return flash; -} - -void spi_flash_free(struct spi_flash *flash) -{ - spi_free_slave(flash->spi); - free(flash); -} diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h deleted file mode 100644 index af1afa96c9..0000000000 --- a/drivers/mtd/spi/spi_flash_internal.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * SPI flash internal definitions - * - * Copyright (C) 2008 Atmel Corporation - */ - -/* Common parameters -- kind of high, but they should only occur when there - * is a problem (and well your system already is broken), so err on the side - * of caution in case we're dealing with slower SPI buses and/or processors. - */ -#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) -#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) -#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) - -/* Common commands */ -#define CMD_READ_ID 0x9f - -#define CMD_READ_ARRAY_SLOW 0x03 -#define CMD_READ_ARRAY_FAST 0x0b - -#define CMD_WRITE_STATUS 0x01 -#define CMD_PAGE_PROGRAM 0x02 -#define CMD_WRITE_DISABLE 0x04 -#define CMD_READ_STATUS 0x05 -#define CMD_FLAG_STATUS 0x70 -#define CMD_WRITE_ENABLE 0x06 -#define CMD_ERASE_4K 0x20 -#define CMD_ERASE_32K 0x52 -#define CMD_ERASE_64K 0xd8 -#define CMD_ERASE_CHIP 0xc7 - -#define SPI_FLASH_16MB_BOUN 0x1000000 - -/* Manufacture ID's */ -#define SPI_FLASH_SPANSION_IDCODE0 0x01 -#define SPI_FLASH_STMICRO_IDCODE0 0x20 -#define SPI_FLASH_WINBOND_IDCODE0 0xef - -#ifdef CONFIG_SPI_FLASH_BAR -/* Bank addr access commands */ -# define CMD_BANKADDR_BRWR 0x17 -# define CMD_BANKADDR_BRRD 0x16 -# define CMD_EXTNADDR_WREAR 0xC5 -# define CMD_EXTNADDR_RDEAR 0xC8 -#endif - -/* Common status */ -#define STATUS_WIP 0x01 -#define STATUS_PEC 0x80 - -/* Send a single-byte command to the device and read the response */ -int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); - -/* - * Send a multi-byte command to the device and read the response. Used - * for flash array reads, etc. - */ -int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, - size_t cmd_len, void *data, size_t data_len); - -int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, - size_t len, void *data); - -/* - * Send a multi-byte command to the device followed by (optional) - * data. Used for programming the flash array, etc. - */ -int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, - const void *data, size_t data_len); - -/* - * Write the requested data out breaking it up into multiple write - * commands as needed per the write size. - */ -int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, - size_t len, const void *buf); - -/* - * Enable writing on the SPI flash. - */ -static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) -{ - return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); -} - -/* - * Disable writing on the SPI flash. - */ -static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) -{ - return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); -} - -/* Program the status register. */ -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); - -#ifdef CONFIG_SPI_FLASH_BAR -/* Program the bank address register */ -int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel); - -/* Configure the BAR - discover the bank cmds */ -int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0); -#endif - -/* - * Same as spi_flash_cmd_read() except it also claims/releases the SPI - * bus. Used as common part of the ->read() operation. - */ -int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, - size_t cmd_len, void *data, size_t data_len); -/* - * Used for spi_flash write operation - * - SPI claim - * - spi_flash_cmd_write_enable - * - spi_flash_cmd_write - * - spi_flash_cmd_wait_ready - * - SPI release - */ -int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, - size_t cmd_len, const void *buf, size_t buf_len); - -/* - * Send the read status command to the device and wait for the wip - * (write-in-progress) bit to clear itself. - */ -int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); - -/* Erase sectors. */ -int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len); - -/* Manufacturer-specific probe functions */ -struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); -struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); -struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode); -struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode); -struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); -struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); -struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); -struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode); -struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c index 7c799ca482..2e0c871219 100644 --- a/drivers/mtd/spi/spi_spl_load.c +++ b/drivers/mtd/spi/spi_spl_load.c @@ -10,9 +10,39 @@ */ #include +#include #include #include +#ifdef CONFIG_SPL_OS_BOOT +/* + * Load the kernel, check for a valid header we can parse, and if found load + * the kernel and then device tree. + */ +static int spi_load_image_os(struct spi_flash *flash, + struct image_header *header) +{ + /* Read for a header, parse or error out. */ + spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40, + (void *)header); + + if (image_get_magic(header) != IH_MAGIC) + return -1; + + spl_parse_image_header(header); + + spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, + spl_image.size, (void *)spl_image.load_addr); + + /* Read device tree. */ + spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, + CONFIG_SYS_SPI_ARGS_SIZE, + (void *)CONFIG_SYS_SPL_ARGS_ADDR); + + return 0; +} +#endif + /* * The main entry for SPI booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image @@ -27,8 +57,10 @@ void spl_spi_load_image(void) * Load U-Boot image from SPI flash into RAM */ - flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS, - CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3); + flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); if (!flash) { puts("SPI probe failed.\n"); hang(); @@ -37,10 +69,15 @@ void spl_spi_load_image(void) /* use CONFIG_SYS_TEXT_BASE as temporary storage area */ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); - /* Load u-boot, mkimage header is 64 bytes. */ - spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40, - (void *) header); - spl_parse_image_header(header); - spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, - spl_image.size, (void *)spl_image.load_addr); +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spi_load_image_os(flash, header)) +#endif + { + /* Load u-boot, mkimage header is 64 bytes. */ + spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40, + (void *)header); + spl_parse_image_header(header); + spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, + spl_image.size, (void *)spl_image.load_addr); + } } diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c deleted file mode 100644 index 95f5490c35..0000000000 --- a/drivers/mtd/spi/sst.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Driver for SST serial flashes - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Copyright 2008, Network Appliance Inc. - * Jason McMullan - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * Copyright (c) 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -#include "spi_flash_internal.h" - -#define CMD_SST_BP 0x02 /* Byte Program */ -#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ - -#define SST_SR_WIP (1 << 0) /* Write-in-Progress */ -#define SST_SR_WEL (1 << 1) /* Write enable */ -#define SST_SR_BP0 (1 << 2) /* Block Protection 0 */ -#define SST_SR_BP1 (1 << 3) /* Block Protection 1 */ -#define SST_SR_BP2 (1 << 4) /* Block Protection 2 */ -#define SST_SR_AAI (1 << 6) /* Addressing mode */ -#define SST_SR_BPL (1 << 7) /* BP bits lock */ - -#define SST_FEAT_WP (1 << 0) /* Supports AAI word program */ -#define SST_FEAT_MBP (1 << 1) /* Supports multibyte program */ - -struct sst_spi_flash_params { - u8 idcode1; - u8 flags; - u16 nr_sectors; - const char *name; -}; - -struct sst_spi_flash { - struct spi_flash flash; - const struct sst_spi_flash_params *params; -}; - -static const struct sst_spi_flash_params sst_spi_flash_table[] = { - { - .idcode1 = 0x8d, - .flags = SST_FEAT_WP, - .nr_sectors = 128, - .name = "SST25VF040B", - },{ - .idcode1 = 0x8e, - .flags = SST_FEAT_WP, - .nr_sectors = 256, - .name = "SST25VF080B", - },{ - .idcode1 = 0x41, - .flags = SST_FEAT_WP, - .nr_sectors = 512, - .name = "SST25VF016B", - },{ - .idcode1 = 0x4a, - .flags = SST_FEAT_WP, - .nr_sectors = 1024, - .name = "SST25VF032B", - },{ - .idcode1 = 0x4b, - .flags = SST_FEAT_MBP, - .nr_sectors = 2048, - .name = "SST25VF064C", - },{ - .idcode1 = 0x01, - .flags = SST_FEAT_WP, - .nr_sectors = 16, - .name = "SST25WF512", - },{ - .idcode1 = 0x02, - .flags = SST_FEAT_WP, - .nr_sectors = 32, - .name = "SST25WF010", - },{ - .idcode1 = 0x03, - .flags = SST_FEAT_WP, - .nr_sectors = 64, - .name = "SST25WF020", - },{ - .idcode1 = 0x04, - .flags = SST_FEAT_WP, - .nr_sectors = 128, - .name = "SST25WF040", - }, -}; - -static int -sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) -{ - int ret; - u8 cmd[4] = { - CMD_SST_BP, - offset >> 16, - offset >> 8, - offset, - }; - - debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); - - ret = spi_flash_cmd_write_enable(flash); - if (ret) - return ret; - - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); - if (ret) - return ret; - - return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); -} - -static int -sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) -{ - size_t actual, cmd_len; - int ret; - u8 cmd[4]; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - /* If the data is not word aligned, write out leading single byte */ - actual = offset % 2; - if (actual) { - ret = sst_byte_write(flash, offset, buf); - if (ret) - goto done; - } - offset += actual; - - ret = spi_flash_cmd_write_enable(flash); - if (ret) - goto done; - - cmd_len = 4; - cmd[0] = CMD_SST_AAI_WP; - cmd[1] = offset >> 16; - cmd[2] = offset >> 8; - cmd[3] = offset; - - for (; actual < len - 1; actual += 2) { - debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0], - offset); - - ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, - buf + actual, 2); - if (ret) { - debug("SF: sst word program failed\n"); - break; - } - - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret) - break; - - cmd_len = 1; - offset += 2; - } - - if (!ret) - ret = spi_flash_cmd_write_disable(flash); - - /* If there is a single trailing byte, write it out */ - if (!ret && actual != len) - ret = sst_byte_write(flash, offset, buf + actual); - - done: - debug("SF: sst: program %s %zu bytes @ 0x%zx\n", - ret ? "failure" : "success", len, offset - actual); - - spi_release_bus(flash->spi); - return ret; -} - -struct spi_flash * -spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) -{ - const struct sst_spi_flash_params *params; - struct sst_spi_flash *stm; - size_t i; - - for (i = 0; i < ARRAY_SIZE(sst_spi_flash_table); ++i) { - params = &sst_spi_flash_table[i]; - if (params->idcode1 == idcode[2]) - break; - } - - if (i == ARRAY_SIZE(sst_spi_flash_table)) { - debug("SF: Unsupported SST ID %02x\n", idcode[1]); - return NULL; - } - - stm = spi_flash_alloc(struct sst_spi_flash, spi, params->name); - if (!stm) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - - stm->params = params; - - if (stm->params->flags & SST_FEAT_WP) - stm->flash.write = sst_write_wp; - stm->flash.page_size = 256; - stm->flash.sector_size = 4096; - stm->flash.size = stm->flash.sector_size * params->nr_sectors; - - /* Flash powers up read-only, so clear BP# bits */ - spi_flash_cmd_write_status(&stm->flash, 0); - - return &stm->flash; -} diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c deleted file mode 100644 index 0ca00f158c..0000000000 --- a/drivers/mtd/spi/stmicro.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright 2008, Network Appliance Inc. - * Jason McMullan - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "spi_flash_internal.h" - -/* M25Pxx-specific commands */ -#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ - -struct stmicro_spi_flash_params { - u16 id; - u16 pages_per_sector; - u16 nr_sectors; - const char *name; -}; - -static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { - { - .id = 0x2011, - .pages_per_sector = 128, - .nr_sectors = 4, - .name = "M25P10", - }, - { - .id = 0x2015, - .pages_per_sector = 256, - .nr_sectors = 32, - .name = "M25P16", - }, - { - .id = 0x2012, - .pages_per_sector = 256, - .nr_sectors = 4, - .name = "M25P20", - }, - { - .id = 0x2016, - .pages_per_sector = 256, - .nr_sectors = 64, - .name = "M25P32", - }, - { - .id = 0x2013, - .pages_per_sector = 256, - .nr_sectors = 8, - .name = "M25P40", - }, - { - .id = 0x2017, - .pages_per_sector = 256, - .nr_sectors = 128, - .name = "M25P64", - }, - { - .id = 0x2014, - .pages_per_sector = 256, - .nr_sectors = 16, - .name = "M25P80", - }, - { - .id = 0x2018, - .pages_per_sector = 1024, - .nr_sectors = 64, - .name = "M25P128", - }, - { - .id = 0xba16, - .pages_per_sector = 256, - .nr_sectors = 64, - .name = "N25Q32", - }, - { - .id = 0xbb16, - .pages_per_sector = 256, - .nr_sectors = 64, - .name = "N25Q32A", - }, - { - .id = 0xba17, - .pages_per_sector = 256, - .nr_sectors = 128, - .name = "N25Q064", - }, - { - .id = 0xbb17, - .pages_per_sector = 256, - .nr_sectors = 128, - .name = "N25Q64A", - }, - { - .id = 0xba18, - .pages_per_sector = 256, - .nr_sectors = 256, - .name = "N25Q128", - }, - { - .id = 0xbb18, - .pages_per_sector = 256, - .nr_sectors = 256, - .name = "N25Q128A", - }, - { - .id = 0xba19, - .pages_per_sector = 256, - .nr_sectors = 512, - .name = "N25Q256", - }, - { - .id = 0xbb19, - .pages_per_sector = 256, - .nr_sectors = 512, - .name = "N25Q256A", - }, - { - .id = 0xba20, - .pages_per_sector = 256, - .nr_sectors = 1024, - .name = "N25Q512", - }, - { - .id = 0xbb20, - .pages_per_sector = 256, - .nr_sectors = 1024, - .name = "N25Q512A", - }, - { - .id = 0xba21, - .pages_per_sector = 256, - .nr_sectors = 2048, - .name = "N25Q1024", - }, - { - .id = 0xbb21, - .pages_per_sector = 256, - .nr_sectors = 2048, - .name = "N25Q1024A", - }, -}; - -struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) -{ - const struct stmicro_spi_flash_params *params; - struct spi_flash *flash; - unsigned int i; - u16 id; - - if (idcode[0] == 0xff) { - i = spi_flash_cmd(spi, CMD_M25PXX_RES, - idcode, 4); - if (i) - return NULL; - if ((idcode[3] & 0xf0) == 0x10) { - idcode[0] = 0x20; - idcode[1] = 0x20; - idcode[2] = idcode[3] + 1; - } else - return NULL; - } - - id = ((idcode[1] << 8) | idcode[2]); - - for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) { - params = &stmicro_spi_flash_table[i]; - if (params->id == id) { - break; - } - } - - if (i == ARRAY_SIZE(stmicro_spi_flash_table)) { - debug("SF: Unsupported STMicro ID %04x\n", id); - return NULL; - } - - flash = spi_flash_alloc_base(spi, params->name); - if (!flash) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - - flash->page_size = 256; - flash->sector_size = 256 * params->pages_per_sector; - flash->size = flash->sector_size * params->nr_sectors; - - /* for >= 512MiB flashes, use flag status instead of read_status */ - if (flash->size >= 0x4000000) - flash->poll_cmd = CMD_FLAG_STATUS; - - return flash; -} diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c deleted file mode 100644 index c399bf14d1..0000000000 --- a/drivers/mtd/spi/winbond.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2008, Network Appliance Inc. - * Author: Jason McMullan netapp.com> - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -#include "spi_flash_internal.h" - -struct winbond_spi_flash_params { - uint16_t id; - uint16_t nr_blocks; - const char *name; -}; - -static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { - { - .id = 0x2014, - .nr_blocks = 16, - .name = "W25P80", - }, - { - .id = 0x2015, - .nr_blocks = 32, - .name = "W25P16", - }, - { - .id = 0x2016, - .nr_blocks = 64, - .name = "W25P32", - }, - { - .id = 0x3013, - .nr_blocks = 8, - .name = "W25X40", - }, - { - .id = 0x3015, - .nr_blocks = 32, - .name = "W25X16", - }, - { - .id = 0x3016, - .nr_blocks = 64, - .name = "W25X32", - }, - { - .id = 0x3017, - .nr_blocks = 128, - .name = "W25X64", - }, - { - .id = 0x4014, - .nr_blocks = 16, - .name = "W25Q80BL/W25Q80BV", - }, - { - .id = 0x4015, - .nr_blocks = 32, - .name = "W25Q16CL/W25Q16DV", - }, - { - .id = 0x4016, - .nr_blocks = 64, - .name = "W25Q32BV/W25Q32FV_SPI", - }, - { - .id = 0x4017, - .nr_blocks = 128, - .name = "W25Q64CV/W25Q64FV_SPI", - }, - { - .id = 0x4018, - .nr_blocks = 256, - .name = "W25Q128BV/W25Q128FV_SPI", - }, - { - .id = 0x4019, - .nr_blocks = 512, - .name = "W25Q256", - }, - { - .id = 0x5014, - .nr_blocks = 16, - .name = "W25Q80BW", - }, - { - .id = 0x6015, - .nr_blocks = 32, - .name = "W25Q16DW", - }, - { - .id = 0x6016, - .nr_blocks = 64, - .name = "W25Q32DW/W25Q32FV_QPI", - }, - { - .id = 0x6017, - .nr_blocks = 128, - .name = "W25Q64DW/W25Q64FV_QPI", - }, - { - .id = 0x6018, - .nr_blocks = 256, - .name = "W25Q128FW/W25Q128FV_QPI", - }, -}; - -struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) -{ - const struct winbond_spi_flash_params *params; - struct spi_flash *flash; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { - params = &winbond_spi_flash_table[i]; - if (params->id == ((idcode[1] << 8) | idcode[2])) - break; - } - - if (i == ARRAY_SIZE(winbond_spi_flash_table)) { - debug("SF: Unsupported Winbond ID %02x%02x\n", - idcode[1], idcode[2]); - return NULL; - } - - flash = spi_flash_alloc_base(spi, params->name); - if (!flash) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - - flash->page_size = 256; - flash->sector_size = (idcode[1] == 0x20) ? 65536 : 4096; - flash->size = 4096 * 16 * params->nr_blocks; - - return flash; -} diff --git a/drivers/mtd/ubi/Makefile b/drivers/mtd/ubi/Makefile index 1a88e9499d..4807f94fab 100644 --- a/drivers/mtd/ubi/Makefile +++ b/drivers/mtd/ubi/Makefile @@ -5,31 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libubi.o - -ifdef CONFIG_CMD_UBI -COBJS-y += build.o vtbl.o vmt.o upd.o kapi.o eba.o io.o wl.o scan.o crc32.o - -COBJS-y += misc.o -COBJS-y += debug.o -endif - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += attach.o build.o vtbl.o vmt.o upd.o kapi.o eba.o io.o wl.o crc32.o +obj-$(CONFIG_MTD_UBI_FASTMAP) += fastmap.o +obj-y += misc.o +obj-y += debug.o diff --git a/drivers/mtd/ubi/attach.c b/drivers/mtd/ubi/attach.c new file mode 100644 index 0000000000..1bdbfa71d9 --- /dev/null +++ b/drivers/mtd/ubi/attach.c @@ -0,0 +1,1753 @@ +/* + * Copyright (c) International Business Machines Corp., 2006 + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Author: Artem Bityutskiy (Битюцкий Артём) + */ + +/* + * UBI attaching sub-system. + * + * This sub-system is responsible for attaching MTD devices and it also + * implements flash media scanning. + * + * The attaching information is represented by a &struct ubi_attach_info' + * object. Information about volumes is represented by &struct ubi_ainf_volume + * objects which are kept in volume RB-tree with root at the @volumes field. + * The RB-tree is indexed by the volume ID. + * + * Logical eraseblocks are represented by &struct ubi_ainf_peb objects. These + * objects are kept in per-volume RB-trees with the root at the corresponding + * &struct ubi_ainf_volume object. To put it differently, we keep an RB-tree of + * per-volume objects and each of these objects is the root of RB-tree of + * per-LEB objects. + * + * Corrupted physical eraseblocks are put to the @corr list, free physical + * eraseblocks are put to the @free list and the physical eraseblock to be + * erased are put to the @erase list. + * + * About corruptions + * ~~~~~~~~~~~~~~~~~ + * + * UBI protects EC and VID headers with CRC-32 checksums, so it can detect + * whether the headers are corrupted or not. Sometimes UBI also protects the + * data with CRC-32, e.g., when it executes the atomic LEB change operation, or + * when it moves the contents of a PEB for wear-leveling purposes. + * + * UBI tries to distinguish between 2 types of corruptions. + * + * 1. Corruptions caused by power cuts. These are expected corruptions and UBI + * tries to handle them gracefully, without printing too many warnings and + * error messages. The idea is that we do not lose important data in these + * cases - we may lose only the data which were being written to the media just + * before the power cut happened, and the upper layers (e.g., UBIFS) are + * supposed to handle such data losses (e.g., by using the FS journal). + * + * When UBI detects a corruption (CRC-32 mismatch) in a PEB, and it looks like + * the reason is a power cut, UBI puts this PEB to the @erase list, and all + * PEBs in the @erase list are scheduled for erasure later. + * + * 2. Unexpected corruptions which are not caused by power cuts. During + * attaching, such PEBs are put to the @corr list and UBI preserves them. + * Obviously, this lessens the amount of available PEBs, and if at some point + * UBI runs out of free PEBs, it switches to R/O mode. UBI also loudly informs + * about such PEBs every time the MTD device is attached. + * + * However, it is difficult to reliably distinguish between these types of + * corruptions and UBI's strategy is as follows (in case of attaching by + * scanning). UBI assumes corruption type 2 if the VID header is corrupted and + * the data area does not contain all 0xFFs, and there were no bit-flips or + * integrity errors (e.g., ECC errors in case of NAND) while reading the data + * area. Otherwise UBI assumes corruption type 1. So the decision criteria + * are as follows. + * o If the data area contains only 0xFFs, there are no data, and it is safe + * to just erase this PEB - this is corruption type 1. + * o If the data area has bit-flips or data integrity errors (ECC errors on + * NAND), it is probably a PEB which was being erased when power cut + * happened, so this is corruption type 1. However, this is just a guess, + * which might be wrong. + * o Otherwise this is corruption type 2. + */ + +#ifndef __UBOOT__ +#include +#include +#include +#include +#else +#include +#include +#endif + +#include + +#include +#include "ubi.h" + +static int self_check_ai(struct ubi_device *ubi, struct ubi_attach_info *ai); + +/* Temporary variables used during scanning */ +static struct ubi_ec_hdr *ech; +static struct ubi_vid_hdr *vidh; + +/** + * add_to_list - add physical eraseblock to a list. + * @ai: attaching information + * @pnum: physical eraseblock number to add + * @vol_id: the last used volume id for the PEB + * @lnum: the last used LEB number for the PEB + * @ec: erase counter of the physical eraseblock + * @to_head: if not zero, add to the head of the list + * @list: the list to add to + * + * This function allocates a 'struct ubi_ainf_peb' object for physical + * eraseblock @pnum and adds it to the "free", "erase", or "alien" lists. + * It stores the @lnum and @vol_id alongside, which can both be + * %UBI_UNKNOWN if they are not available, not readable, or not assigned. + * If @to_head is not zero, PEB will be added to the head of the list, which + * basically means it will be processed first later. E.g., we add corrupted + * PEBs (corrupted due to power cuts) to the head of the erase list to make + * sure we erase them first and get rid of corruptions ASAP. This function + * returns zero in case of success and a negative error code in case of + * failure. + */ +static int add_to_list(struct ubi_attach_info *ai, int pnum, int vol_id, + int lnum, int ec, int to_head, struct list_head *list) +{ + struct ubi_ainf_peb *aeb; + + if (list == &ai->free) { + dbg_bld("add to free: PEB %d, EC %d", pnum, ec); + } else if (list == &ai->erase) { + dbg_bld("add to erase: PEB %d, EC %d", pnum, ec); + } else if (list == &ai->alien) { + dbg_bld("add to alien: PEB %d, EC %d", pnum, ec); + ai->alien_peb_count += 1; + } else + BUG(); + + aeb = kmem_cache_alloc(ai->aeb_slab_cache, GFP_KERNEL); + if (!aeb) + return -ENOMEM; + + aeb->pnum = pnum; + aeb->vol_id = vol_id; + aeb->lnum = lnum; + aeb->ec = ec; + if (to_head) + list_add(&aeb->u.list, list); + else + list_add_tail(&aeb->u.list, list); + return 0; +} + +/** + * add_corrupted - add a corrupted physical eraseblock. + * @ai: attaching information + * @pnum: physical eraseblock number to add + * @ec: erase counter of the physical eraseblock + * + * This function allocates a 'struct ubi_ainf_peb' object for a corrupted + * physical eraseblock @pnum and adds it to the 'corr' list. The corruption + * was presumably not caused by a power cut. Returns zero in case of success + * and a negative error code in case of failure. + */ +static int add_corrupted(struct ubi_attach_info *ai, int pnum, int ec) +{ + struct ubi_ainf_peb *aeb; + + dbg_bld("add to corrupted: PEB %d, EC %d", pnum, ec); + + aeb = kmem_cache_alloc(ai->aeb_slab_cache, GFP_KERNEL); + if (!aeb) + return -ENOMEM; + + ai->corr_peb_count += 1; + aeb->pnum = pnum; + aeb->ec = ec; + list_add(&aeb->u.list, &ai->corr); + return 0; +} + +/** + * validate_vid_hdr - check volume identifier header. + * @vid_hdr: the volume identifier header to check + * @av: information about the volume this logical eraseblock belongs to + * @pnum: physical eraseblock number the VID header came from + * + * This function checks that data stored in @vid_hdr is consistent. Returns + * non-zero if an inconsistency was found and zero if not. + * + * Note, UBI does sanity check of everything it reads from the flash media. + * Most of the checks are done in the I/O sub-system. Here we check that the + * information in the VID header is consistent to the information in other VID + * headers of the same volume. + */ +static int validate_vid_hdr(const struct ubi_vid_hdr *vid_hdr, + const struct ubi_ainf_volume *av, int pnum) +{ + int vol_type = vid_hdr->vol_type; + int vol_id = be32_to_cpu(vid_hdr->vol_id); + int used_ebs = be32_to_cpu(vid_hdr->used_ebs); + int data_pad = be32_to_cpu(vid_hdr->data_pad); + + if (av->leb_count != 0) { + int av_vol_type; + + /* + * This is not the first logical eraseblock belonging to this + * volume. Ensure that the data in its VID header is consistent + * to the data in previous logical eraseblock headers. + */ + + if (vol_id != av->vol_id) { + ubi_err("inconsistent vol_id"); + goto bad; + } + + if (av->vol_type == UBI_STATIC_VOLUME) + av_vol_type = UBI_VID_STATIC; + else + av_vol_type = UBI_VID_DYNAMIC; + + if (vol_type != av_vol_type) { + ubi_err("inconsistent vol_type"); + goto bad; + } + + if (used_ebs != av->used_ebs) { + ubi_err("inconsistent used_ebs"); + goto bad; + } + + if (data_pad != av->data_pad) { + ubi_err("inconsistent data_pad"); + goto bad; + } + } + + return 0; + +bad: + ubi_err("inconsistent VID header at PEB %d", pnum); + ubi_dump_vid_hdr(vid_hdr); + ubi_dump_av(av); + return -EINVAL; +} + +/** + * add_volume - add volume to the attaching information. + * @ai: attaching information + * @vol_id: ID of the volume to add + * @pnum: physical eraseblock number + * @vid_hdr: volume identifier header + * + * If the volume corresponding to the @vid_hdr logical eraseblock is already + * present in the attaching information, this function does nothing. Otherwise + * it adds corresponding volume to the attaching information. Returns a pointer + * to the allocated "av" object in case of success and a negative error code in + * case of failure. + */ +static struct ubi_ainf_volume *add_volume(struct ubi_attach_info *ai, + int vol_id, int pnum, + const struct ubi_vid_hdr *vid_hdr) +{ + struct ubi_ainf_volume *av; + struct rb_node **p = &ai->volumes.rb_node, *parent = NULL; + + ubi_assert(vol_id == be32_to_cpu(vid_hdr->vol_id)); + + /* Walk the volume RB-tree to look if this volume is already present */ + while (*p) { + parent = *p; + av = rb_entry(parent, struct ubi_ainf_volume, rb); + + if (vol_id == av->vol_id) + return av; + + if (vol_id > av->vol_id) + p = &(*p)->rb_left; + else + p = &(*p)->rb_right; + } + + /* The volume is absent - add it */ + av = kmalloc(sizeof(struct ubi_ainf_volume), GFP_KERNEL); + if (!av) + return ERR_PTR(-ENOMEM); + + av->highest_lnum = av->leb_count = 0; + av->vol_id = vol_id; + av->root = RB_ROOT; + av->used_ebs = be32_to_cpu(vid_hdr->used_ebs); + av->data_pad = be32_to_cpu(vid_hdr->data_pad); + av->compat = vid_hdr->compat; + av->vol_type = vid_hdr->vol_type == UBI_VID_DYNAMIC ? UBI_DYNAMIC_VOLUME + : UBI_STATIC_VOLUME; + if (vol_id > ai->highest_vol_id) + ai->highest_vol_id = vol_id; + + rb_link_node(&av->rb, parent, p); + rb_insert_color(&av->rb, &ai->volumes); + ai->vols_found += 1; + dbg_bld("added volume %d", vol_id); + return av; +} + +/** + * ubi_compare_lebs - find out which logical eraseblock is newer. + * @ubi: UBI device description object + * @aeb: first logical eraseblock to compare + * @pnum: physical eraseblock number of the second logical eraseblock to + * compare + * @vid_hdr: volume identifier header of the second logical eraseblock + * + * This function compares 2 copies of a LEB and informs which one is newer. In + * case of success this function returns a positive value, in case of failure, a + * negative error code is returned. The success return codes use the following + * bits: + * o bit 0 is cleared: the first PEB (described by @aeb) is newer than the + * second PEB (described by @pnum and @vid_hdr); + * o bit 0 is set: the second PEB is newer; + * o bit 1 is cleared: no bit-flips were detected in the newer LEB; + * o bit 1 is set: bit-flips were detected in the newer LEB; + * o bit 2 is cleared: the older LEB is not corrupted; + * o bit 2 is set: the older LEB is corrupted. + */ +int ubi_compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb, + int pnum, const struct ubi_vid_hdr *vid_hdr) +{ + int len, err, second_is_newer, bitflips = 0, corrupted = 0; + uint32_t data_crc, crc; + struct ubi_vid_hdr *vh = NULL; + unsigned long long sqnum2 = be64_to_cpu(vid_hdr->sqnum); + + if (sqnum2 == aeb->sqnum) { + /* + * This must be a really ancient UBI image which has been + * created before sequence numbers support has been added. At + * that times we used 32-bit LEB versions stored in logical + * eraseblocks. That was before UBI got into mainline. We do not + * support these images anymore. Well, those images still work, + * but only if no unclean reboots happened. + */ + ubi_err("unsupported on-flash UBI format"); + return -EINVAL; + } + + /* Obviously the LEB with lower sequence counter is older */ + second_is_newer = (sqnum2 > aeb->sqnum); + + /* + * Now we know which copy is newer. If the copy flag of the PEB with + * newer version is not set, then we just return, otherwise we have to + * check data CRC. For the second PEB we already have the VID header, + * for the first one - we'll need to re-read it from flash. + * + * Note: this may be optimized so that we wouldn't read twice. + */ + + if (second_is_newer) { + if (!vid_hdr->copy_flag) { + /* It is not a copy, so it is newer */ + dbg_bld("second PEB %d is newer, copy_flag is unset", + pnum); + return 1; + } + } else { + if (!aeb->copy_flag) { + /* It is not a copy, so it is newer */ + dbg_bld("first PEB %d is newer, copy_flag is unset", + pnum); + return bitflips << 1; + } + + vh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); + if (!vh) + return -ENOMEM; + + pnum = aeb->pnum; + err = ubi_io_read_vid_hdr(ubi, pnum, vh, 0); + if (err) { + if (err == UBI_IO_BITFLIPS) + bitflips = 1; + else { + ubi_err("VID of PEB %d header is bad, but it was OK earlier, err %d", + pnum, err); + if (err > 0) + err = -EIO; + + goto out_free_vidh; + } + } + + vid_hdr = vh; + } + + /* Read the data of the copy and check the CRC */ + + len = be32_to_cpu(vid_hdr->data_size); + + mutex_lock(&ubi->buf_mutex); + err = ubi_io_read_data(ubi, ubi->peb_buf, pnum, 0, len); + if (err && err != UBI_IO_BITFLIPS && !mtd_is_eccerr(err)) + goto out_unlock; + + data_crc = be32_to_cpu(vid_hdr->data_crc); + crc = crc32(UBI_CRC32_INIT, ubi->peb_buf, len); + if (crc != data_crc) { + dbg_bld("PEB %d CRC error: calculated %#08x, must be %#08x", + pnum, crc, data_crc); + corrupted = 1; + bitflips = 0; + second_is_newer = !second_is_newer; + } else { + dbg_bld("PEB %d CRC is OK", pnum); + bitflips = !!err; + } + mutex_unlock(&ubi->buf_mutex); + + ubi_free_vid_hdr(ubi, vh); + + if (second_is_newer) + dbg_bld("second PEB %d is newer, copy_flag is set", pnum); + else + dbg_bld("first PEB %d is newer, copy_flag is set", pnum); + + return second_is_newer | (bitflips << 1) | (corrupted << 2); + +out_unlock: + mutex_unlock(&ubi->buf_mutex); +out_free_vidh: + ubi_free_vid_hdr(ubi, vh); + return err; +} + +/** + * ubi_add_to_av - add used physical eraseblock to the attaching information. + * @ubi: UBI device description object + * @ai: attaching information + * @pnum: the physical eraseblock number + * @ec: erase counter + * @vid_hdr: the volume identifier header + * @bitflips: if bit-flips were detected when this physical eraseblock was read + * + * This function adds information about a used physical eraseblock to the + * 'used' tree of the corresponding volume. The function is rather complex + * because it has to handle cases when this is not the first physical + * eraseblock belonging to the same logical eraseblock, and the newer one has + * to be picked, while the older one has to be dropped. This function returns + * zero in case of success and a negative error code in case of failure. + */ +int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum, + int ec, const struct ubi_vid_hdr *vid_hdr, int bitflips) +{ + int err, vol_id, lnum; + unsigned long long sqnum; + struct ubi_ainf_volume *av; + struct ubi_ainf_peb *aeb; + struct rb_node **p, *parent = NULL; + + vol_id = be32_to_cpu(vid_hdr->vol_id); + lnum = be32_to_cpu(vid_hdr->lnum); + sqnum = be64_to_cpu(vid_hdr->sqnum); + + dbg_bld("PEB %d, LEB %d:%d, EC %d, sqnum %llu, bitflips %d", + pnum, vol_id, lnum, ec, sqnum, bitflips); + + av = add_volume(ai, vol_id, pnum, vid_hdr); + if (IS_ERR(av)) + return PTR_ERR(av); + + if (ai->max_sqnum < sqnum) + ai->max_sqnum = sqnum; + + /* + * Walk the RB-tree of logical eraseblocks of volume @vol_id to look + * if this is the first instance of this logical eraseblock or not. + */ + p = &av->root.rb_node; + while (*p) { + int cmp_res; + + parent = *p; + aeb = rb_entry(parent, struct ubi_ainf_peb, u.rb); + if (lnum != aeb->lnum) { + if (lnum < aeb->lnum) + p = &(*p)->rb_left; + else + p = &(*p)->rb_right; + continue; + } + + /* + * There is already a physical eraseblock describing the same + * logical eraseblock present. + */ + + dbg_bld("this LEB already exists: PEB %d, sqnum %llu, EC %d", + aeb->pnum, aeb->sqnum, aeb->ec); + + /* + * Make sure that the logical eraseblocks have different + * sequence numbers. Otherwise the image is bad. + * + * However, if the sequence number is zero, we assume it must + * be an ancient UBI image from the era when UBI did not have + * sequence numbers. We still can attach these images, unless + * there is a need to distinguish between old and new + * eraseblocks, in which case we'll refuse the image in + * 'ubi_compare_lebs()'. In other words, we attach old clean + * images, but refuse attaching old images with duplicated + * logical eraseblocks because there was an unclean reboot. + */ + if (aeb->sqnum == sqnum && sqnum != 0) { + ubi_err("two LEBs with same sequence number %llu", + sqnum); + ubi_dump_aeb(aeb, 0); + ubi_dump_vid_hdr(vid_hdr); + return -EINVAL; + } + + /* + * Now we have to drop the older one and preserve the newer + * one. + */ + cmp_res = ubi_compare_lebs(ubi, aeb, pnum, vid_hdr); + if (cmp_res < 0) + return cmp_res; + + if (cmp_res & 1) { + /* + * This logical eraseblock is newer than the one + * found earlier. + */ + err = validate_vid_hdr(vid_hdr, av, pnum); + if (err) + return err; + + err = add_to_list(ai, aeb->pnum, aeb->vol_id, + aeb->lnum, aeb->ec, cmp_res & 4, + &ai->erase); + if (err) + return err; + + aeb->ec = ec; + aeb->pnum = pnum; + aeb->vol_id = vol_id; + aeb->lnum = lnum; + aeb->scrub = ((cmp_res & 2) || bitflips); + aeb->copy_flag = vid_hdr->copy_flag; + aeb->sqnum = sqnum; + + if (av->highest_lnum == lnum) + av->last_data_size = + be32_to_cpu(vid_hdr->data_size); + + return 0; + } else { + /* + * This logical eraseblock is older than the one found + * previously. + */ + return add_to_list(ai, pnum, vol_id, lnum, ec, + cmp_res & 4, &ai->erase); + } + } + + /* + * We've met this logical eraseblock for the first time, add it to the + * attaching information. + */ + + err = validate_vid_hdr(vid_hdr, av, pnum); + if (err) + return err; + + aeb = kmem_cache_alloc(ai->aeb_slab_cache, GFP_KERNEL); + if (!aeb) + return -ENOMEM; + + aeb->ec = ec; + aeb->pnum = pnum; + aeb->vol_id = vol_id; + aeb->lnum = lnum; + aeb->scrub = bitflips; + aeb->copy_flag = vid_hdr->copy_flag; + aeb->sqnum = sqnum; + + if (av->highest_lnum <= lnum) { + av->highest_lnum = lnum; + av->last_data_size = be32_to_cpu(vid_hdr->data_size); + } + + av->leb_count += 1; + rb_link_node(&aeb->u.rb, parent, p); + rb_insert_color(&aeb->u.rb, &av->root); + return 0; +} + +/** + * ubi_find_av - find volume in the attaching information. + * @ai: attaching information + * @vol_id: the requested volume ID + * + * This function returns a pointer to the volume description or %NULL if there + * are no data about this volume in the attaching information. + */ +struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai, + int vol_id) +{ + struct ubi_ainf_volume *av; + struct rb_node *p = ai->volumes.rb_node; + + while (p) { + av = rb_entry(p, struct ubi_ainf_volume, rb); + + if (vol_id == av->vol_id) + return av; + + if (vol_id > av->vol_id) + p = p->rb_left; + else + p = p->rb_right; + } + + return NULL; +} + +/** + * ubi_remove_av - delete attaching information about a volume. + * @ai: attaching information + * @av: the volume attaching information to delete + */ +void ubi_remove_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av) +{ + struct rb_node *rb; + struct ubi_ainf_peb *aeb; + + dbg_bld("remove attaching information about volume %d", av->vol_id); + + while ((rb = rb_first(&av->root))) { + aeb = rb_entry(rb, struct ubi_ainf_peb, u.rb); + rb_erase(&aeb->u.rb, &av->root); + list_add_tail(&aeb->u.list, &ai->erase); + } + + rb_erase(&av->rb, &ai->volumes); + kfree(av); + ai->vols_found -= 1; +} + +/** + * early_erase_peb - erase a physical eraseblock. + * @ubi: UBI device description object + * @ai: attaching information + * @pnum: physical eraseblock number to erase; + * @ec: erase counter value to write (%UBI_UNKNOWN if it is unknown) + * + * This function erases physical eraseblock 'pnum', and writes the erase + * counter header to it. This function should only be used on UBI device + * initialization stages, when the EBA sub-system had not been yet initialized. + * This function returns zero in case of success and a negative error code in + * case of failure. + */ +static int early_erase_peb(struct ubi_device *ubi, + const struct ubi_attach_info *ai, int pnum, int ec) +{ + int err; + struct ubi_ec_hdr *ec_hdr; + + if ((long long)ec >= UBI_MAX_ERASECOUNTER) { + /* + * Erase counter overflow. Upgrade UBI and use 64-bit + * erase counters internally. + */ + ubi_err("erase counter overflow at PEB %d, EC %d", pnum, ec); + return -EINVAL; + } + + ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); + if (!ec_hdr) + return -ENOMEM; + + ec_hdr->ec = cpu_to_be64(ec); + + err = ubi_io_sync_erase(ubi, pnum, 0); + if (err < 0) + goto out_free; + + err = ubi_io_write_ec_hdr(ubi, pnum, ec_hdr); + +out_free: + kfree(ec_hdr); + return err; +} + +/** + * ubi_early_get_peb - get a free physical eraseblock. + * @ubi: UBI device description object + * @ai: attaching information + * + * This function returns a free physical eraseblock. It is supposed to be + * called on the UBI initialization stages when the wear-leveling sub-system is + * not initialized yet. This function picks a physical eraseblocks from one of + * the lists, writes the EC header if it is needed, and removes it from the + * list. + * + * This function returns a pointer to the "aeb" of the found free PEB in case + * of success and an error code in case of failure. + */ +struct ubi_ainf_peb *ubi_early_get_peb(struct ubi_device *ubi, + struct ubi_attach_info *ai) +{ + int err = 0; + struct ubi_ainf_peb *aeb, *tmp_aeb; + + if (!list_empty(&ai->free)) { + aeb = list_entry(ai->free.next, struct ubi_ainf_peb, u.list); + list_del(&aeb->u.list); + dbg_bld("return free PEB %d, EC %d", aeb->pnum, aeb->ec); + return aeb; + } + + /* + * We try to erase the first physical eraseblock from the erase list + * and pick it if we succeed, or try to erase the next one if not. And + * so forth. We don't want to take care about bad eraseblocks here - + * they'll be handled later. + */ + list_for_each_entry_safe(aeb, tmp_aeb, &ai->erase, u.list) { + if (aeb->ec == UBI_UNKNOWN) + aeb->ec = ai->mean_ec; + + err = early_erase_peb(ubi, ai, aeb->pnum, aeb->ec+1); + if (err) + continue; + + aeb->ec += 1; + list_del(&aeb->u.list); + dbg_bld("return PEB %d, EC %d", aeb->pnum, aeb->ec); + return aeb; + } + + ubi_err("no free eraseblocks"); + return ERR_PTR(-ENOSPC); +} + +/** + * check_corruption - check the data area of PEB. + * @ubi: UBI device description object + * @vid_hdr: the (corrupted) VID header of this PEB + * @pnum: the physical eraseblock number to check + * + * This is a helper function which is used to distinguish between VID header + * corruptions caused by power cuts and other reasons. If the PEB contains only + * 0xFF bytes in the data area, the VID header is most probably corrupted + * because of a power cut (%0 is returned in this case). Otherwise, it was + * probably corrupted for some other reasons (%1 is returned in this case). A + * negative error code is returned if a read error occurred. + * + * If the corruption reason was a power cut, UBI can safely erase this PEB. + * Otherwise, it should preserve it to avoid possibly destroying important + * information. + */ +static int check_corruption(struct ubi_device *ubi, struct ubi_vid_hdr *vid_hdr, + int pnum) +{ + int err; + + mutex_lock(&ubi->buf_mutex); + memset(ubi->peb_buf, 0x00, ubi->leb_size); + + err = ubi_io_read(ubi, ubi->peb_buf, pnum, ubi->leb_start, + ubi->leb_size); + if (err == UBI_IO_BITFLIPS || mtd_is_eccerr(err)) { + /* + * Bit-flips or integrity errors while reading the data area. + * It is difficult to say for sure what type of corruption is + * this, but presumably a power cut happened while this PEB was + * erased, so it became unstable and corrupted, and should be + * erased. + */ + err = 0; + goto out_unlock; + } + + if (err) + goto out_unlock; + + if (ubi_check_pattern(ubi->peb_buf, 0xFF, ubi->leb_size)) + goto out_unlock; + + ubi_err("PEB %d contains corrupted VID header, and the data does not contain all 0xFF", + pnum); + ubi_err("this may be a non-UBI PEB or a severe VID header corruption which requires manual inspection"); + ubi_dump_vid_hdr(vid_hdr); + pr_err("hexdump of PEB %d offset %d, length %d", + pnum, ubi->leb_start, ubi->leb_size); + ubi_dbg_print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + ubi->peb_buf, ubi->leb_size, 1); + err = 1; + +out_unlock: + mutex_unlock(&ubi->buf_mutex); + return err; +} + +/** + * scan_peb - scan and process UBI headers of a PEB. + * @ubi: UBI device description object + * @ai: attaching information + * @pnum: the physical eraseblock number + * @vid: The volume ID of the found volume will be stored in this pointer + * @sqnum: The sqnum of the found volume will be stored in this pointer + * + * This function reads UBI headers of PEB @pnum, checks them, and adds + * information about this PEB to the corresponding list or RB-tree in the + * "attaching info" structure. Returns zero if the physical eraseblock was + * successfully handled and a negative error code in case of failure. + */ +static int scan_peb(struct ubi_device *ubi, struct ubi_attach_info *ai, + int pnum, int *vid, unsigned long long *sqnum) +{ + long long uninitialized_var(ec); + int err, bitflips = 0, vol_id = -1, ec_err = 0; + + dbg_bld("scan PEB %d", pnum); + + /* Skip bad physical eraseblocks */ + err = ubi_io_is_bad(ubi, pnum); + if (err < 0) + return err; + else if (err) { + ai->bad_peb_count += 1; + return 0; + } + + err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); + if (err < 0) + return err; + switch (err) { + case 0: + break; + case UBI_IO_BITFLIPS: + bitflips = 1; + break; + case UBI_IO_FF: + ai->empty_peb_count += 1; + return add_to_list(ai, pnum, UBI_UNKNOWN, UBI_UNKNOWN, + UBI_UNKNOWN, 0, &ai->erase); + case UBI_IO_FF_BITFLIPS: + ai->empty_peb_count += 1; + return add_to_list(ai, pnum, UBI_UNKNOWN, UBI_UNKNOWN, + UBI_UNKNOWN, 1, &ai->erase); + case UBI_IO_BAD_HDR_EBADMSG: + case UBI_IO_BAD_HDR: + /* + * We have to also look at the VID header, possibly it is not + * corrupted. Set %bitflips flag in order to make this PEB be + * moved and EC be re-created. + */ + ec_err = err; + ec = UBI_UNKNOWN; + bitflips = 1; + break; + default: + ubi_err("'ubi_io_read_ec_hdr()' returned unknown code %d", err); + return -EINVAL; + } + + if (!ec_err) { + int image_seq; + + /* Make sure UBI version is OK */ + if (ech->version != UBI_VERSION) { + ubi_err("this UBI version is %d, image version is %d", + UBI_VERSION, (int)ech->version); + return -EINVAL; + } + + ec = be64_to_cpu(ech->ec); + if (ec > UBI_MAX_ERASECOUNTER) { + /* + * Erase counter overflow. The EC headers have 64 bits + * reserved, but we anyway make use of only 31 bit + * values, as this seems to be enough for any existing + * flash. Upgrade UBI and use 64-bit erase counters + * internally. + */ + ubi_err("erase counter overflow, max is %d", + UBI_MAX_ERASECOUNTER); + ubi_dump_ec_hdr(ech); + return -EINVAL; + } + + /* + * Make sure that all PEBs have the same image sequence number. + * This allows us to detect situations when users flash UBI + * images incorrectly, so that the flash has the new UBI image + * and leftovers from the old one. This feature was added + * relatively recently, and the sequence number was always + * zero, because old UBI implementations always set it to zero. + * For this reasons, we do not panic if some PEBs have zero + * sequence number, while other PEBs have non-zero sequence + * number. + */ + image_seq = be32_to_cpu(ech->image_seq); + if (!ubi->image_seq) + ubi->image_seq = image_seq; + if (image_seq && ubi->image_seq != image_seq) { + ubi_err("bad image sequence number %d in PEB %d, expected %d", + image_seq, pnum, ubi->image_seq); + ubi_dump_ec_hdr(ech); + return -EINVAL; + } + } + + /* OK, we've done with the EC header, let's look at the VID header */ + + err = ubi_io_read_vid_hdr(ubi, pnum, vidh, 0); + if (err < 0) + return err; + switch (err) { + case 0: + break; + case UBI_IO_BITFLIPS: + bitflips = 1; + break; + case UBI_IO_BAD_HDR_EBADMSG: + if (ec_err == UBI_IO_BAD_HDR_EBADMSG) + /* + * Both EC and VID headers are corrupted and were read + * with data integrity error, probably this is a bad + * PEB, bit it is not marked as bad yet. This may also + * be a result of power cut during erasure. + */ + ai->maybe_bad_peb_count += 1; + case UBI_IO_BAD_HDR: + if (ec_err) + /* + * Both headers are corrupted. There is a possibility + * that this a valid UBI PEB which has corresponding + * LEB, but the headers are corrupted. However, it is + * impossible to distinguish it from a PEB which just + * contains garbage because of a power cut during erase + * operation. So we just schedule this PEB for erasure. + * + * Besides, in case of NOR flash, we deliberately + * corrupt both headers because NOR flash erasure is + * slow and can start from the end. + */ + err = 0; + else + /* + * The EC was OK, but the VID header is corrupted. We + * have to check what is in the data area. + */ + err = check_corruption(ubi, vidh, pnum); + + if (err < 0) + return err; + else if (!err) + /* This corruption is caused by a power cut */ + err = add_to_list(ai, pnum, UBI_UNKNOWN, + UBI_UNKNOWN, ec, 1, &ai->erase); + else + /* This is an unexpected corruption */ + err = add_corrupted(ai, pnum, ec); + if (err) + return err; + goto adjust_mean_ec; + case UBI_IO_FF_BITFLIPS: + err = add_to_list(ai, pnum, UBI_UNKNOWN, UBI_UNKNOWN, + ec, 1, &ai->erase); + if (err) + return err; + goto adjust_mean_ec; + case UBI_IO_FF: + if (ec_err || bitflips) + err = add_to_list(ai, pnum, UBI_UNKNOWN, + UBI_UNKNOWN, ec, 1, &ai->erase); + else + err = add_to_list(ai, pnum, UBI_UNKNOWN, + UBI_UNKNOWN, ec, 0, &ai->free); + if (err) + return err; + goto adjust_mean_ec; + default: + ubi_err("'ubi_io_read_vid_hdr()' returned unknown code %d", + err); + return -EINVAL; + } + + vol_id = be32_to_cpu(vidh->vol_id); + if (vid) + *vid = vol_id; + if (sqnum) + *sqnum = be64_to_cpu(vidh->sqnum); + if (vol_id > UBI_MAX_VOLUMES && vol_id != UBI_LAYOUT_VOLUME_ID) { + int lnum = be32_to_cpu(vidh->lnum); + + /* Unsupported internal volume */ + switch (vidh->compat) { + case UBI_COMPAT_DELETE: + if (vol_id != UBI_FM_SB_VOLUME_ID + && vol_id != UBI_FM_DATA_VOLUME_ID) { + ubi_msg("\"delete\" compatible internal volume %d:%d found, will remove it", + vol_id, lnum); + } + err = add_to_list(ai, pnum, vol_id, lnum, + ec, 1, &ai->erase); + if (err) + return err; + return 0; + + case UBI_COMPAT_RO: + ubi_msg("read-only compatible internal volume %d:%d found, switch to read-only mode", + vol_id, lnum); + ubi->ro_mode = 1; + break; + + case UBI_COMPAT_PRESERVE: + ubi_msg("\"preserve\" compatible internal volume %d:%d found", + vol_id, lnum); + err = add_to_list(ai, pnum, vol_id, lnum, + ec, 0, &ai->alien); + if (err) + return err; + return 0; + + case UBI_COMPAT_REJECT: + ubi_err("incompatible internal volume %d:%d found", + vol_id, lnum); + return -EINVAL; + } + } + + if (ec_err) + ubi_warn("valid VID header but corrupted EC header at PEB %d", + pnum); + err = ubi_add_to_av(ubi, ai, pnum, ec, vidh, bitflips); + if (err) + return err; + +adjust_mean_ec: + if (!ec_err) { + ai->ec_sum += ec; + ai->ec_count += 1; + if (ec > ai->max_ec) + ai->max_ec = ec; + if (ec < ai->min_ec) + ai->min_ec = ec; + } + + return 0; +} + +/** + * late_analysis - analyze the overall situation with PEB. + * @ubi: UBI device description object + * @ai: attaching information + * + * This is a helper function which takes a look what PEBs we have after we + * gather information about all of them ("ai" is compete). It decides whether + * the flash is empty and should be formatted of whether there are too many + * corrupted PEBs and we should not attach this MTD device. Returns zero if we + * should proceed with attaching the MTD device, and %-EINVAL if we should not. + */ +static int late_analysis(struct ubi_device *ubi, struct ubi_attach_info *ai) +{ + struct ubi_ainf_peb *aeb; + int max_corr, peb_count; + + peb_count = ubi->peb_count - ai->bad_peb_count - ai->alien_peb_count; + max_corr = peb_count / 20 ?: 8; + + /* + * Few corrupted PEBs is not a problem and may be just a result of + * unclean reboots. However, many of them may indicate some problems + * with the flash HW or driver. + */ + if (ai->corr_peb_count) { + ubi_err("%d PEBs are corrupted and preserved", + ai->corr_peb_count); + pr_err("Corrupted PEBs are:"); + list_for_each_entry(aeb, &ai->corr, u.list) + pr_cont(" %d", aeb->pnum); + pr_cont("\n"); + + /* + * If too many PEBs are corrupted, we refuse attaching, + * otherwise, only print a warning. + */ + if (ai->corr_peb_count >= max_corr) { + ubi_err("too many corrupted PEBs, refusing"); + return -EINVAL; + } + } + + if (ai->empty_peb_count + ai->maybe_bad_peb_count == peb_count) { + /* + * All PEBs are empty, or almost all - a couple PEBs look like + * they may be bad PEBs which were not marked as bad yet. + * + * This piece of code basically tries to distinguish between + * the following situations: + * + * 1. Flash is empty, but there are few bad PEBs, which are not + * marked as bad so far, and which were read with error. We + * want to go ahead and format this flash. While formatting, + * the faulty PEBs will probably be marked as bad. + * + * 2. Flash contains non-UBI data and we do not want to format + * it and destroy possibly important information. + */ + if (ai->maybe_bad_peb_count <= 2) { + ai->is_empty = 1; + ubi_msg("empty MTD device detected"); + get_random_bytes(&ubi->image_seq, + sizeof(ubi->image_seq)); + } else { + ubi_err("MTD device is not UBI-formatted and possibly contains non-UBI data - refusing it"); + return -EINVAL; + } + + } + + return 0; +} + +/** + * destroy_av - free volume attaching information. + * @av: volume attaching information + * @ai: attaching information + * + * This function destroys the volume attaching information. + */ +static void destroy_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av) +{ + struct ubi_ainf_peb *aeb; + struct rb_node *this = av->root.rb_node; + + while (this) { + if (this->rb_left) + this = this->rb_left; + else if (this->rb_right) + this = this->rb_right; + else { + aeb = rb_entry(this, struct ubi_ainf_peb, u.rb); + this = rb_parent(this); + if (this) { + if (this->rb_left == &aeb->u.rb) + this->rb_left = NULL; + else + this->rb_right = NULL; + } + + kmem_cache_free(ai->aeb_slab_cache, aeb); + } + } + kfree(av); +} + +/** + * destroy_ai - destroy attaching information. + * @ai: attaching information + */ +static void destroy_ai(struct ubi_attach_info *ai) +{ + struct ubi_ainf_peb *aeb, *aeb_tmp; + struct ubi_ainf_volume *av; + struct rb_node *rb; + + list_for_each_entry_safe(aeb, aeb_tmp, &ai->alien, u.list) { + list_del(&aeb->u.list); + kmem_cache_free(ai->aeb_slab_cache, aeb); + } + list_for_each_entry_safe(aeb, aeb_tmp, &ai->erase, u.list) { + list_del(&aeb->u.list); + kmem_cache_free(ai->aeb_slab_cache, aeb); + } + list_for_each_entry_safe(aeb, aeb_tmp, &ai->corr, u.list) { + list_del(&aeb->u.list); + kmem_cache_free(ai->aeb_slab_cache, aeb); + } + list_for_each_entry_safe(aeb, aeb_tmp, &ai->free, u.list) { + list_del(&aeb->u.list); + kmem_cache_free(ai->aeb_slab_cache, aeb); + } + + /* Destroy the volume RB-tree */ + rb = ai->volumes.rb_node; + while (rb) { + if (rb->rb_left) + rb = rb->rb_left; + else if (rb->rb_right) + rb = rb->rb_right; + else { + av = rb_entry(rb, struct ubi_ainf_volume, rb); + + rb = rb_parent(rb); + if (rb) { + if (rb->rb_left == &av->rb) + rb->rb_left = NULL; + else + rb->rb_right = NULL; + } + + destroy_av(ai, av); + } + } + + if (ai->aeb_slab_cache) + kmem_cache_destroy(ai->aeb_slab_cache); + + kfree(ai); +} + +/** + * scan_all - scan entire MTD device. + * @ubi: UBI device description object + * @ai: attach info object + * @start: start scanning at this PEB + * + * This function does full scanning of an MTD device and returns complete + * information about it in form of a "struct ubi_attach_info" object. In case + * of failure, an error code is returned. + */ +static int scan_all(struct ubi_device *ubi, struct ubi_attach_info *ai, + int start) +{ + int err, pnum; + struct rb_node *rb1, *rb2; + struct ubi_ainf_volume *av; + struct ubi_ainf_peb *aeb; + + err = -ENOMEM; + + ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); + if (!ech) + return err; + + vidh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); + if (!vidh) + goto out_ech; + + for (pnum = start; pnum < ubi->peb_count; pnum++) { + cond_resched(); + + dbg_gen("process PEB %d", pnum); + err = scan_peb(ubi, ai, pnum, NULL, NULL); + if (err < 0) + goto out_vidh; + } + + ubi_msg("scanning is finished"); + + /* Calculate mean erase counter */ + if (ai->ec_count) + ai->mean_ec = div_u64(ai->ec_sum, ai->ec_count); + + err = late_analysis(ubi, ai); + if (err) + goto out_vidh; + + /* + * In case of unknown erase counter we use the mean erase counter + * value. + */ + ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) { + ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb) + if (aeb->ec == UBI_UNKNOWN) + aeb->ec = ai->mean_ec; + } + + list_for_each_entry(aeb, &ai->free, u.list) { + if (aeb->ec == UBI_UNKNOWN) + aeb->ec = ai->mean_ec; + } + + list_for_each_entry(aeb, &ai->corr, u.list) + if (aeb->ec == UBI_UNKNOWN) + aeb->ec = ai->mean_ec; + + list_for_each_entry(aeb, &ai->erase, u.list) + if (aeb->ec == UBI_UNKNOWN) + aeb->ec = ai->mean_ec; + + err = self_check_ai(ubi, ai); + if (err) + goto out_vidh; + + ubi_free_vid_hdr(ubi, vidh); + kfree(ech); + + return 0; + +out_vidh: + ubi_free_vid_hdr(ubi, vidh); +out_ech: + kfree(ech); + return err; +} + +#ifdef CONFIG_MTD_UBI_FASTMAP + +/** + * scan_fastmap - try to find a fastmap and attach from it. + * @ubi: UBI device description object + * @ai: attach info object + * + * Returns 0 on success, negative return values indicate an internal + * error. + * UBI_NO_FASTMAP denotes that no fastmap was found. + * UBI_BAD_FASTMAP denotes that the found fastmap was invalid. + */ +static int scan_fast(struct ubi_device *ubi, struct ubi_attach_info *ai) +{ + int err, pnum, fm_anchor = -1; + unsigned long long max_sqnum = 0; + + err = -ENOMEM; + + ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); + if (!ech) + goto out; + + vidh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); + if (!vidh) + goto out_ech; + + for (pnum = 0; pnum < UBI_FM_MAX_START; pnum++) { + int vol_id = -1; + unsigned long long sqnum = -1; + cond_resched(); + + dbg_gen("process PEB %d", pnum); + err = scan_peb(ubi, ai, pnum, &vol_id, &sqnum); + if (err < 0) + goto out_vidh; + + if (vol_id == UBI_FM_SB_VOLUME_ID && sqnum > max_sqnum) { + max_sqnum = sqnum; + fm_anchor = pnum; + } + } + + ubi_free_vid_hdr(ubi, vidh); + kfree(ech); + + if (fm_anchor < 0) + return UBI_NO_FASTMAP; + + return ubi_scan_fastmap(ubi, ai, fm_anchor); + +out_vidh: + ubi_free_vid_hdr(ubi, vidh); +out_ech: + kfree(ech); +out: + return err; +} + +#endif + +static struct ubi_attach_info *alloc_ai(const char *slab_name) +{ + struct ubi_attach_info *ai; + + ai = kzalloc(sizeof(struct ubi_attach_info), GFP_KERNEL); + if (!ai) + return ai; + + INIT_LIST_HEAD(&ai->corr); + INIT_LIST_HEAD(&ai->free); + INIT_LIST_HEAD(&ai->erase); + INIT_LIST_HEAD(&ai->alien); + ai->volumes = RB_ROOT; + ai->aeb_slab_cache = kmem_cache_create(slab_name, + sizeof(struct ubi_ainf_peb), + 0, 0, NULL); + if (!ai->aeb_slab_cache) { + kfree(ai); + ai = NULL; + } + + return ai; +} + +/** + * ubi_attach - attach an MTD device. + * @ubi: UBI device descriptor + * @force_scan: if set to non-zero attach by scanning + * + * This function returns zero in case of success and a negative error code in + * case of failure. + */ +int ubi_attach(struct ubi_device *ubi, int force_scan) +{ + int err; + struct ubi_attach_info *ai; + + ai = alloc_ai("ubi_aeb_slab_cache"); + if (!ai) + return -ENOMEM; + +#ifdef CONFIG_MTD_UBI_FASTMAP + /* On small flash devices we disable fastmap in any case. */ + if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) { + ubi->fm_disabled = 1; + force_scan = 1; + } + + if (force_scan) + err = scan_all(ubi, ai, 0); + else { + err = scan_fast(ubi, ai); + if (err > 0) { + if (err != UBI_NO_FASTMAP) { + destroy_ai(ai); + ai = alloc_ai("ubi_aeb_slab_cache2"); + if (!ai) + return -ENOMEM; + + err = scan_all(ubi, ai, 0); + } else { + err = scan_all(ubi, ai, UBI_FM_MAX_START); + } + } + } +#else + err = scan_all(ubi, ai, 0); +#endif + if (err) + goto out_ai; + + ubi->bad_peb_count = ai->bad_peb_count; + ubi->good_peb_count = ubi->peb_count - ubi->bad_peb_count; + ubi->corr_peb_count = ai->corr_peb_count; + ubi->max_ec = ai->max_ec; + ubi->mean_ec = ai->mean_ec; + dbg_gen("max. sequence number: %llu", ai->max_sqnum); + + err = ubi_read_volume_table(ubi, ai); + if (err) + goto out_ai; + + err = ubi_wl_init(ubi, ai); + if (err) + goto out_vtbl; + + err = ubi_eba_init(ubi, ai); + if (err) + goto out_wl; + +#ifdef CONFIG_MTD_UBI_FASTMAP + if (ubi->fm && ubi_dbg_chk_gen(ubi)) { + struct ubi_attach_info *scan_ai; + + scan_ai = alloc_ai("ubi_ckh_aeb_slab_cache"); + if (!scan_ai) { + err = -ENOMEM; + goto out_wl; + } + + err = scan_all(ubi, scan_ai, 0); + if (err) { + destroy_ai(scan_ai); + goto out_wl; + } + + err = self_check_eba(ubi, ai, scan_ai); + destroy_ai(scan_ai); + + if (err) + goto out_wl; + } +#endif + + destroy_ai(ai); + return 0; + +out_wl: + ubi_wl_close(ubi); +out_vtbl: + ubi_free_internal_volumes(ubi); + vfree(ubi->vtbl); +out_ai: + destroy_ai(ai); + return err; +} + +/** + * self_check_ai - check the attaching information. + * @ubi: UBI device description object + * @ai: attaching information + * + * This function returns zero if the attaching information is all right, and a + * negative error code if not or if an error occurred. + */ +static int self_check_ai(struct ubi_device *ubi, struct ubi_attach_info *ai) +{ + int pnum, err, vols_found = 0; + struct rb_node *rb1, *rb2; + struct ubi_ainf_volume *av; + struct ubi_ainf_peb *aeb, *last_aeb; + uint8_t *buf; + + if (!ubi_dbg_chk_gen(ubi)) + return 0; + + /* + * At first, check that attaching information is OK. + */ + ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) { + int leb_count = 0; + + cond_resched(); + + vols_found += 1; + + if (ai->is_empty) { + ubi_err("bad is_empty flag"); + goto bad_av; + } + + if (av->vol_id < 0 || av->highest_lnum < 0 || + av->leb_count < 0 || av->vol_type < 0 || av->used_ebs < 0 || + av->data_pad < 0 || av->last_data_size < 0) { + ubi_err("negative values"); + goto bad_av; + } + + if (av->vol_id >= UBI_MAX_VOLUMES && + av->vol_id < UBI_INTERNAL_VOL_START) { + ubi_err("bad vol_id"); + goto bad_av; + } + + if (av->vol_id > ai->highest_vol_id) { + ubi_err("highest_vol_id is %d, but vol_id %d is there", + ai->highest_vol_id, av->vol_id); + goto out; + } + + if (av->vol_type != UBI_DYNAMIC_VOLUME && + av->vol_type != UBI_STATIC_VOLUME) { + ubi_err("bad vol_type"); + goto bad_av; + } + + if (av->data_pad > ubi->leb_size / 2) { + ubi_err("bad data_pad"); + goto bad_av; + } + + last_aeb = NULL; + ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb) { + cond_resched(); + + last_aeb = aeb; + leb_count += 1; + + if (aeb->pnum < 0 || aeb->ec < 0) { + ubi_err("negative values"); + goto bad_aeb; + } + + if (aeb->ec < ai->min_ec) { + ubi_err("bad ai->min_ec (%d), %d found", + ai->min_ec, aeb->ec); + goto bad_aeb; + } + + if (aeb->ec > ai->max_ec) { + ubi_err("bad ai->max_ec (%d), %d found", + ai->max_ec, aeb->ec); + goto bad_aeb; + } + + if (aeb->pnum >= ubi->peb_count) { + ubi_err("too high PEB number %d, total PEBs %d", + aeb->pnum, ubi->peb_count); + goto bad_aeb; + } + + if (av->vol_type == UBI_STATIC_VOLUME) { + if (aeb->lnum >= av->used_ebs) { + ubi_err("bad lnum or used_ebs"); + goto bad_aeb; + } + } else { + if (av->used_ebs != 0) { + ubi_err("non-zero used_ebs"); + goto bad_aeb; + } + } + + if (aeb->lnum > av->highest_lnum) { + ubi_err("incorrect highest_lnum or lnum"); + goto bad_aeb; + } + } + + if (av->leb_count != leb_count) { + ubi_err("bad leb_count, %d objects in the tree", + leb_count); + goto bad_av; + } + + if (!last_aeb) + continue; + + aeb = last_aeb; + + if (aeb->lnum != av->highest_lnum) { + ubi_err("bad highest_lnum"); + goto bad_aeb; + } + } + + if (vols_found != ai->vols_found) { + ubi_err("bad ai->vols_found %d, should be %d", + ai->vols_found, vols_found); + goto out; + } + + /* Check that attaching information is correct */ + ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) { + last_aeb = NULL; + ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb) { + int vol_type; + + cond_resched(); + + last_aeb = aeb; + + err = ubi_io_read_vid_hdr(ubi, aeb->pnum, vidh, 1); + if (err && err != UBI_IO_BITFLIPS) { + ubi_err("VID header is not OK (%d)", err); + if (err > 0) + err = -EIO; + return err; + } + + vol_type = vidh->vol_type == UBI_VID_DYNAMIC ? + UBI_DYNAMIC_VOLUME : UBI_STATIC_VOLUME; + if (av->vol_type != vol_type) { + ubi_err("bad vol_type"); + goto bad_vid_hdr; + } + + if (aeb->sqnum != be64_to_cpu(vidh->sqnum)) { + ubi_err("bad sqnum %llu", aeb->sqnum); + goto bad_vid_hdr; + } + + if (av->vol_id != be32_to_cpu(vidh->vol_id)) { + ubi_err("bad vol_id %d", av->vol_id); + goto bad_vid_hdr; + } + + if (av->compat != vidh->compat) { + ubi_err("bad compat %d", vidh->compat); + goto bad_vid_hdr; + } + + if (aeb->lnum != be32_to_cpu(vidh->lnum)) { + ubi_err("bad lnum %d", aeb->lnum); + goto bad_vid_hdr; + } + + if (av->used_ebs != be32_to_cpu(vidh->used_ebs)) { + ubi_err("bad used_ebs %d", av->used_ebs); + goto bad_vid_hdr; + } + + if (av->data_pad != be32_to_cpu(vidh->data_pad)) { + ubi_err("bad data_pad %d", av->data_pad); + goto bad_vid_hdr; + } + } + + if (!last_aeb) + continue; + + if (av->highest_lnum != be32_to_cpu(vidh->lnum)) { + ubi_err("bad highest_lnum %d", av->highest_lnum); + goto bad_vid_hdr; + } + + if (av->last_data_size != be32_to_cpu(vidh->data_size)) { + ubi_err("bad last_data_size %d", av->last_data_size); + goto bad_vid_hdr; + } + } + + /* + * Make sure that all the physical eraseblocks are in one of the lists + * or trees. + */ + buf = kzalloc(ubi->peb_count, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + for (pnum = 0; pnum < ubi->peb_count; pnum++) { + err = ubi_io_is_bad(ubi, pnum); + if (err < 0) { + kfree(buf); + return err; + } else if (err) + buf[pnum] = 1; + } + + ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) + ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb) + buf[aeb->pnum] = 1; + + list_for_each_entry(aeb, &ai->free, u.list) + buf[aeb->pnum] = 1; + + list_for_each_entry(aeb, &ai->corr, u.list) + buf[aeb->pnum] = 1; + + list_for_each_entry(aeb, &ai->erase, u.list) + buf[aeb->pnum] = 1; + + list_for_each_entry(aeb, &ai->alien, u.list) + buf[aeb->pnum] = 1; + + err = 0; + for (pnum = 0; pnum < ubi->peb_count; pnum++) + if (!buf[pnum]) { + ubi_err("PEB %d is not referred", pnum); + err = 1; + } + + kfree(buf); + if (err) + goto out; + return 0; + +bad_aeb: + ubi_err("bad attaching information about LEB %d", aeb->lnum); + ubi_dump_aeb(aeb, 0); + ubi_dump_av(av); + goto out; + +bad_av: + ubi_err("bad attaching information about volume %d", av->vol_id); + ubi_dump_av(av); + goto out; + +bad_vid_hdr: + ubi_err("bad attaching information about volume %d", av->vol_id); + ubi_dump_av(av); + ubi_dump_vid_hdr(vidh); + +out: + dump_stack(); + return -EINVAL; +} diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 6d86c0b6bc..584cf5f22b 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -15,56 +15,87 @@ * module load parameters or the kernel boot parameters. If MTD devices were * specified, UBI does not attach any MTD device, but it is possible to do * later using the "UBI control device". - * - * At the moment we only attach UBI devices by scanning, which will become a - * bottleneck when flashes reach certain large size. Then one may improve UBI - * and add other methods, although it does not seem to be easy to do. */ -#ifdef UBI_LINUX -#include +#ifndef __UBOOT__ #include #include #include +#include #include #include #include #include +#include +#include +#include +#else +#include #endif +#include #include +#include + #include "ubi.h" +/* Maximum length of the 'mtd=' parameter */ +#define MTD_PARAM_LEN_MAX 64 + +/* Maximum number of comma-separated items in the 'mtd=' parameter */ +#define MTD_PARAM_MAX_COUNT 4 + +/* Maximum value for the number of bad PEBs per 1024 PEBs */ +#define MAX_MTD_UBI_BEB_LIMIT 768 + +#ifdef CONFIG_MTD_UBI_MODULE +#define ubi_is_module() 1 +#else +#define ubi_is_module() 0 +#endif + #if (CONFIG_SYS_MALLOC_LEN < (512 << 10)) #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k #endif -/* Maximum length of the 'mtd=' parameter */ -#define MTD_PARAM_LEN_MAX 64 - /** * struct mtd_dev_param - MTD device parameter description data structure. - * @name: MTD device name or number string + * @name: MTD character device node path, MTD device name, or MTD device number + * string * @vid_hdr_offs: VID header offset + * @max_beb_per1024: maximum expected number of bad PEBs per 1024 PEBs */ -struct mtd_dev_param -{ +struct mtd_dev_param { char name[MTD_PARAM_LEN_MAX]; + int ubi_num; int vid_hdr_offs; + int max_beb_per1024; }; /* Numbers of elements set in the @mtd_dev_param array */ -static int mtd_devs = 0; +static int __initdata mtd_devs; /* MTD devices specification parameters */ -static struct mtd_dev_param mtd_dev_param[UBI_MAX_DEVICES]; - +static struct mtd_dev_param __initdata mtd_dev_param[UBI_MAX_DEVICES]; +#ifndef __UBOOT__ +#ifdef CONFIG_MTD_UBI_FASTMAP +/* UBI module parameter to enable fastmap automatically on non-fastmap images */ +static bool fm_autoconvert; +#endif +#else +#ifdef CONFIG_MTD_UBI_FASTMAP +#if !defined(CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT) +#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 0 +#endif +static bool fm_autoconvert = CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT; +#endif +#endif /* Root UBI "class" object (corresponds to '//class/ubi/') */ struct class *ubi_class; -#ifdef UBI_LINUX /* Slab cache for wear-leveling entries */ struct kmem_cache *ubi_wl_entry_slab; +#ifndef __UBOOT__ /* UBI control character device */ static struct miscdevice ubi_ctrl_cdev = { .minor = MISC_DYNAMIC_MINOR, @@ -74,9 +105,13 @@ static struct miscdevice ubi_ctrl_cdev = { #endif /* All UBI devices in system */ +#ifndef __UBOOT__ +static struct ubi_device *ubi_devices[UBI_MAX_DEVICES]; +#else struct ubi_device *ubi_devices[UBI_MAX_DEVICES]; +#endif -#ifdef UBI_LINUX +#ifndef __UBOOT__ /* Serializes UBI devices creations and removals */ DEFINE_MUTEX(ubi_devices_mutex); @@ -84,7 +119,8 @@ DEFINE_MUTEX(ubi_devices_mutex); static DEFINE_SPINLOCK(ubi_devices_lock); /* "Show" method for files in '//class/ubi/' */ -static ssize_t ubi_version_show(struct class *class, char *buf) +static ssize_t ubi_version_show(struct class *class, + struct class_attribute *attr, char *buf) { return sprintf(buf, "%d\n", UBI_VERSION); } @@ -121,6 +157,112 @@ static struct device_attribute dev_mtd_num = __ATTR(mtd_num, S_IRUGO, dev_attribute_show, NULL); #endif +/** + * ubi_volume_notify - send a volume change notification. + * @ubi: UBI device description object + * @vol: volume description object of the changed volume + * @ntype: notification type to send (%UBI_VOLUME_ADDED, etc) + * + * This is a helper function which notifies all subscribers about a volume + * change event (creation, removal, re-sizing, re-naming, updating). Returns + * zero in case of success and a negative error code in case of failure. + */ +int ubi_volume_notify(struct ubi_device *ubi, struct ubi_volume *vol, int ntype) +{ + struct ubi_notification nt; + + ubi_do_get_device_info(ubi, &nt.di); + ubi_do_get_volume_info(ubi, vol, &nt.vi); + +#ifdef CONFIG_MTD_UBI_FASTMAP + switch (ntype) { + case UBI_VOLUME_ADDED: + case UBI_VOLUME_REMOVED: + case UBI_VOLUME_RESIZED: + case UBI_VOLUME_RENAMED: + if (ubi_update_fastmap(ubi)) { + ubi_err("Unable to update fastmap!"); + ubi_ro_mode(ubi); + } + } +#endif + return blocking_notifier_call_chain(&ubi_notifiers, ntype, &nt); +} + +/** + * ubi_notify_all - send a notification to all volumes. + * @ubi: UBI device description object + * @ntype: notification type to send (%UBI_VOLUME_ADDED, etc) + * @nb: the notifier to call + * + * This function walks all volumes of UBI device @ubi and sends the @ntype + * notification for each volume. If @nb is %NULL, then all registered notifiers + * are called, otherwise only the @nb notifier is called. Returns the number of + * sent notifications. + */ +int ubi_notify_all(struct ubi_device *ubi, int ntype, struct notifier_block *nb) +{ + struct ubi_notification nt; + int i, count = 0; +#ifndef __UBOOT__ + int ret; +#endif + + ubi_do_get_device_info(ubi, &nt.di); + + mutex_lock(&ubi->device_mutex); + for (i = 0; i < ubi->vtbl_slots; i++) { + /* + * Since the @ubi->device is locked, and we are not going to + * change @ubi->volumes, we do not have to lock + * @ubi->volumes_lock. + */ + if (!ubi->volumes[i]) + continue; + + ubi_do_get_volume_info(ubi, ubi->volumes[i], &nt.vi); +#ifndef __UBOOT__ + if (nb) + nb->notifier_call(nb, ntype, &nt); + else + ret = blocking_notifier_call_chain(&ubi_notifiers, ntype, + &nt); +#endif + count += 1; + } + mutex_unlock(&ubi->device_mutex); + + return count; +} + +/** + * ubi_enumerate_volumes - send "add" notification for all existing volumes. + * @nb: the notifier to call + * + * This function walks all UBI devices and volumes and sends the + * %UBI_VOLUME_ADDED notification for each volume. If @nb is %NULL, then all + * registered notifiers are called, otherwise only the @nb notifier is called. + * Returns the number of sent notifications. + */ +int ubi_enumerate_volumes(struct notifier_block *nb) +{ + int i, count = 0; + + /* + * Since the @ubi_devices_mutex is locked, and we are not going to + * change @ubi_devices, we do not have to lock @ubi_devices_lock. + */ + for (i = 0; i < UBI_MAX_DEVICES; i++) { + struct ubi_device *ubi = ubi_devices[i]; + + if (!ubi) + continue; + count += ubi_notify_all(ubi, UBI_VOLUME_ADDED, nb); + } + + return count; +} + /** * ubi_get_device - get UBI device. * @ubi_num: UBI device number @@ -159,8 +301,7 @@ void ubi_put_device(struct ubi_device *ubi) } /** - * ubi_get_by_major - get UBI device description object by character device - * major number. + * ubi_get_by_major - get UBI device by character device major number. * @major: major number * * This function is similar to 'ubi_get_device()', but it searches the device @@ -213,7 +354,7 @@ int ubi_major2num(int major) return ubi_num; } -#ifdef UBI_LINUX +#ifndef __UBOOT__ /* "Show" method for files in '//class/ubi/ubiX/' */ static ssize_t dev_attribute_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -265,28 +406,35 @@ static ssize_t dev_attribute_show(struct device *dev, return ret; } -/* Fake "release" method for UBI devices */ -static void dev_release(struct device *dev) { } +static void dev_release(struct device *dev) +{ + struct ubi_device *ubi = container_of(dev, struct ubi_device, dev); + + kfree(ubi); +} /** * ubi_sysfs_init - initialize sysfs for an UBI device. * @ubi: UBI device description object + * @ref: set to %1 on exit in case of failure if a reference to @ubi->dev was + * taken * * This function returns zero in case of success and a negative error code in * case of failure. */ -static int ubi_sysfs_init(struct ubi_device *ubi) +static int ubi_sysfs_init(struct ubi_device *ubi, int *ref) { int err; ubi->dev.release = dev_release; ubi->dev.devt = ubi->cdev.dev; ubi->dev.class = ubi_class; - sprintf(&ubi->dev.bus_id[0], UBI_NAME_STR"%d", ubi->ubi_num); + dev_set_name(&ubi->dev, UBI_NAME_STR"%d", ubi->ubi_num); err = device_register(&ubi->dev); if (err) return err; + *ref = 1; err = device_create_file(&ubi->dev, &dev_eraseblock_size); if (err) return err; @@ -343,7 +491,7 @@ static void ubi_sysfs_close(struct ubi_device *ubi) #endif /** - * kill_volumes - destroy all volumes. + * kill_volumes - destroy all user volumes. * @ubi: UBI device description object */ static void kill_volumes(struct ubi_device *ubi) @@ -358,17 +506,29 @@ static void kill_volumes(struct ubi_device *ubi) /** * uif_init - initialize user interfaces for an UBI device. * @ubi: UBI device description object + * @ref: set to %1 on exit in case of failure if a reference to @ubi->dev was + * taken, otherwise set to %0 + * + * This function initializes various user interfaces for an UBI device. If the + * initialization fails at an early stage, this function frees all the + * resources it allocated, returns an error, and @ref is set to %0. However, + * if the initialization fails after the UBI device was registered in the + * driver core subsystem, this function takes a reference to @ubi->dev, because + * otherwise the release function ('dev_release()') would free whole @ubi + * object. The @ref argument is set to %1 in this case. The caller has to put + * this reference. * * This function returns zero in case of success and a negative error code in * case of failure. */ -static int uif_init(struct ubi_device *ubi) +static int uif_init(struct ubi_device *ubi, int *ref) { int i, err; -#ifdef UBI_LINUX +#ifndef __UBOOT__ dev_t dev; #endif + *ref = 0; sprintf(ubi->ubi_name, UBI_NAME_STR "%d", ubi->ubi_num); /* @@ -387,7 +547,7 @@ static int uif_init(struct ubi_device *ubi) ubi_assert(MINOR(dev) == 0); cdev_init(&ubi->cdev, &ubi_cdev_operations); - dbg_msg("%s major is %u", ubi->ubi_name, MAJOR(dev)); + dbg_gen("%s major is %u", ubi->ubi_name, MAJOR(dev)); ubi->cdev.owner = THIS_MODULE; err = cdev_add(&ubi->cdev, dev, 1); @@ -396,7 +556,7 @@ static int uif_init(struct ubi_device *ubi) goto out_unreg; } - err = ubi_sysfs_init(ubi); + err = ubi_sysfs_init(ubi, ref); if (err) goto out_sysfs; @@ -414,6 +574,8 @@ static int uif_init(struct ubi_device *ubi) out_volumes: kill_volumes(ubi); out_sysfs: + if (*ref) + get_device(&ubi->dev); ubi_sysfs_close(ubi); cdev_del(&ubi->cdev); out_unreg: @@ -425,6 +587,10 @@ out_unreg: /** * uif_close - close user interfaces for an UBI device. * @ubi: UBI device description object + * + * Note, since this function un-registers UBI volume device objects (@vol->dev), + * the memory allocated voe the volumes is freed as well (in the release + * function). */ static void uif_close(struct ubi_device *ubi) { @@ -435,58 +601,52 @@ static void uif_close(struct ubi_device *ubi) } /** - * attach_by_scanning - attach an MTD device using scanning method. - * @ubi: UBI device descriptor - * - * This function returns zero in case of success and a negative error code in - * case of failure. - * - * Note, currently this is the only method to attach UBI devices. Hopefully in - * the future we'll have more scalable attaching methods and avoid full media - * scanning. But even in this case scanning will be needed as a fall-back - * attaching method if there are some on-flash table corruptions. + * ubi_free_internal_volumes - free internal volumes. + * @ubi: UBI device description object */ -static int attach_by_scanning(struct ubi_device *ubi) +void ubi_free_internal_volumes(struct ubi_device *ubi) { - int err; - struct ubi_scan_info *si; - - si = ubi_scan(ubi); - if (IS_ERR(si)) - return PTR_ERR(si); + int i; - ubi->bad_peb_count = si->bad_peb_count; - ubi->good_peb_count = ubi->peb_count - ubi->bad_peb_count; - ubi->max_ec = si->max_ec; - ubi->mean_ec = si->mean_ec; + for (i = ubi->vtbl_slots; + i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) { + kfree(ubi->volumes[i]->eba_tbl); + kfree(ubi->volumes[i]); + } +} - err = ubi_read_volume_table(ubi, si); - if (err) - goto out_si; +static int get_bad_peb_limit(const struct ubi_device *ubi, int max_beb_per1024) +{ + int limit, device_pebs; + uint64_t device_size; - err = ubi_eba_init_scan(ubi, si); - if (err) - goto out_vtbl; + if (!max_beb_per1024) + return 0; - err = ubi_wl_init_scan(ubi, si); - if (err) - goto out_eba; + /* + * Here we are using size of the entire flash chip and + * not just the MTD partition size because the maximum + * number of bad eraseblocks is a percentage of the + * whole device and bad eraseblocks are not fairly + * distributed over the flash chip. So the worst case + * is that all the bad eraseblocks of the chip are in + * the MTD partition we are attaching (ubi->mtd). + */ + device_size = mtd_get_device_size(ubi->mtd); + device_pebs = mtd_div_by_eb(device_size, ubi->mtd); + limit = mult_frac(device_pebs, max_beb_per1024, 1024); - ubi_scan_destroy_si(si); - return 0; + /* Round it up */ + if (mult_frac(limit, 1024, max_beb_per1024) < device_pebs) + limit += 1; -out_eba: - ubi_eba_close(ubi); -out_vtbl: - vfree(ubi->vtbl); -out_si: - ubi_scan_destroy_si(si); - return err; + return limit; } /** - * io_init - initialize I/O unit for a given UBI device. + * io_init - initialize I/O sub-system for a given UBI device. * @ubi: UBI device description object + * @max_beb_per1024: maximum expected number of bad PEB per 1024 PEBs * * If @ubi->vid_hdr_offset or @ubi->leb_start is zero, default offsets are * assumed: @@ -499,8 +659,11 @@ out_si: * This function returns zero in case of success and a negative error code in * case of failure. */ -static int io_init(struct ubi_device *ubi) +static int io_init(struct ubi_device *ubi, int max_beb_per1024) { + dbg_gen("sizeof(struct ubi_ainf_peb) %zu", sizeof(struct ubi_ainf_peb)); + dbg_gen("sizeof(struct ubi_wl_entry) %zu", sizeof(struct ubi_wl_entry)); + if (ubi->mtd->numeraseregions != 0) { /* * Some flashes have several erase regions. Different regions @@ -527,8 +690,15 @@ static int io_init(struct ubi_device *ubi) ubi->peb_count = mtd_div_by_eb(ubi->mtd->size, ubi->mtd); ubi->flash_size = ubi->mtd->size; - if (mtd_can_have_bb(ubi->mtd)) + if (mtd_can_have_bb(ubi->mtd)) { ubi->bad_allowed = 1; + ubi->bad_peb_limit = get_bad_peb_limit(ubi, max_beb_per1024); + } + + if (ubi->mtd->type == MTD_NORFLASH) { + ubi_assert(ubi->mtd->writesize == 1); + ubi->nor_flash = 1; + } ubi->min_io_size = ubi->mtd->writesize; ubi->hdrs_min_io_size = ubi->mtd->writesize >> ubi->mtd->subpage_sft; @@ -548,14 +718,28 @@ static int io_init(struct ubi_device *ubi) ubi_assert(ubi->hdrs_min_io_size <= ubi->min_io_size); ubi_assert(ubi->min_io_size % ubi->hdrs_min_io_size == 0); + ubi->max_write_size = ubi->mtd->writebufsize; + /* + * Maximum write size has to be greater or equivalent to min. I/O + * size, and be multiple of min. I/O size. + */ + if (ubi->max_write_size < ubi->min_io_size || + ubi->max_write_size % ubi->min_io_size || + !is_power_of_2(ubi->max_write_size)) { + ubi_err("bad write buffer size %d for %d min. I/O unit", + ubi->max_write_size, ubi->min_io_size); + return -EINVAL; + } + /* Calculate default aligned sizes of EC and VID headers */ ubi->ec_hdr_alsize = ALIGN(UBI_EC_HDR_SIZE, ubi->hdrs_min_io_size); ubi->vid_hdr_alsize = ALIGN(UBI_VID_HDR_SIZE, ubi->hdrs_min_io_size); - dbg_msg("min_io_size %d", ubi->min_io_size); - dbg_msg("hdrs_min_io_size %d", ubi->hdrs_min_io_size); - dbg_msg("ec_hdr_alsize %d", ubi->ec_hdr_alsize); - dbg_msg("vid_hdr_alsize %d", ubi->vid_hdr_alsize); + dbg_gen("min_io_size %d", ubi->min_io_size); + dbg_gen("max_write_size %d", ubi->max_write_size); + dbg_gen("hdrs_min_io_size %d", ubi->hdrs_min_io_size); + dbg_gen("ec_hdr_alsize %d", ubi->ec_hdr_alsize); + dbg_gen("vid_hdr_alsize %d", ubi->vid_hdr_alsize); if (ubi->vid_hdr_offset == 0) /* Default offset */ @@ -569,13 +753,13 @@ static int io_init(struct ubi_device *ubi) } /* Similar for the data offset */ - ubi->leb_start = ubi->vid_hdr_offset + UBI_EC_HDR_SIZE; + ubi->leb_start = ubi->vid_hdr_offset + UBI_VID_HDR_SIZE; ubi->leb_start = ALIGN(ubi->leb_start, ubi->min_io_size); - dbg_msg("vid_hdr_offset %d", ubi->vid_hdr_offset); - dbg_msg("vid_hdr_aloffset %d", ubi->vid_hdr_aloffset); - dbg_msg("vid_hdr_shift %d", ubi->vid_hdr_shift); - dbg_msg("leb_start %d", ubi->leb_start); + dbg_gen("vid_hdr_offset %d", ubi->vid_hdr_offset); + dbg_gen("vid_hdr_aloffset %d", ubi->vid_hdr_aloffset); + dbg_gen("vid_hdr_shift %d", ubi->vid_hdr_shift); + dbg_gen("leb_start %d", ubi->leb_start); /* The shift must be aligned to 32-bit boundary */ if (ubi->vid_hdr_shift % 4) { @@ -594,42 +778,39 @@ static int io_init(struct ubi_device *ubi) return -EINVAL; } + /* + * Set maximum amount of physical erroneous eraseblocks to be 10%. + * Erroneous PEB are those which have read errors. + */ + ubi->max_erroneous = ubi->peb_count / 10; + if (ubi->max_erroneous < 16) + ubi->max_erroneous = 16; + dbg_gen("max_erroneous %d", ubi->max_erroneous); + /* * It may happen that EC and VID headers are situated in one minimal * I/O unit. In this case we can only accept this UBI image in * read-only mode. */ if (ubi->vid_hdr_offset + UBI_VID_HDR_SIZE <= ubi->hdrs_min_io_size) { - ubi_warn("EC and VID headers are in the same minimal I/O unit, " - "switch to read-only mode"); + ubi_warn("EC and VID headers are in the same minimal I/O unit, switch to read-only mode"); ubi->ro_mode = 1; } ubi->leb_size = ubi->peb_size - ubi->leb_start; if (!(ubi->mtd->flags & MTD_WRITEABLE)) { - ubi_msg("MTD device %d is write-protected, attach in " - "read-only mode", ubi->mtd->index); + ubi_msg("MTD device %d is write-protected, attach in read-only mode", + ubi->mtd->index); ubi->ro_mode = 1; } - ubi_msg("physical eraseblock size: %d bytes (%d KiB)", - ubi->peb_size, ubi->peb_size >> 10); - ubi_msg("logical eraseblock size: %d bytes", ubi->leb_size); - ubi_msg("smallest flash I/O unit: %d", ubi->min_io_size); - if (ubi->hdrs_min_io_size != ubi->min_io_size) - ubi_msg("sub-page size: %d", - ubi->hdrs_min_io_size); - ubi_msg("VID header offset: %d (aligned %d)", - ubi->vid_hdr_offset, ubi->vid_hdr_aloffset); - ubi_msg("data offset: %d", ubi->leb_start); - /* - * Note, ideally, we have to initialize ubi->bad_peb_count here. But + * Note, ideally, we have to initialize @ubi->bad_peb_count here. But * unfortunately, MTD does not provide this information. We should loop * over all physical eraseblocks and invoke mtd->block_is_bad() for - * each physical eraseblock. So, we skip ubi->bad_peb_count - * uninitialized and initialize it after scanning. + * each physical eraseblock. So, we leave @ubi->bad_peb_count + * uninitialized so far. */ return 0; @@ -640,7 +821,7 @@ static int io_init(struct ubi_device *ubi) * @ubi: UBI device description object * @vol_id: ID of the volume to re-size * - * This function re-sizes the volume marked by the @UBI_VTBL_AUTORESIZE_FLG in + * This function re-sizes the volume marked by the %UBI_VTBL_AUTORESIZE_FLG in * the volume table to the largest possible size. See comments in ubi-header.h * for more description of the flag. Returns zero in case of success and a * negative error code in case of failure. @@ -651,9 +832,14 @@ static int autoresize(struct ubi_device *ubi, int vol_id) struct ubi_volume *vol = ubi->volumes[vol_id]; int err, old_reserved_pebs = vol->reserved_pebs; + if (ubi->ro_mode) { + ubi_warn("skip auto-resize because of R/O mode"); + return 0; + } + /* * Clear the auto-resize flag in the volume in-memory copy of the - * volume table, and 'ubi_resize_volume()' will propogate this change + * volume table, and 'ubi_resize_volume()' will propagate this change * to the flash. */ ubi->vtbl[vol_id].flags &= ~UBI_VTBL_AUTORESIZE_FLG; @@ -662,11 +848,10 @@ static int autoresize(struct ubi_device *ubi, int vol_id) struct ubi_vtbl_record vtbl_rec; /* - * No avalilable PEBs to re-size the volume, clear the flag on + * No available PEBs to re-size the volume, clear the flag on * flash and exit. */ - memcpy(&vtbl_rec, &ubi->vtbl[vol_id], - sizeof(struct ubi_vtbl_record)); + vtbl_rec = ubi->vtbl[vol_id]; err = ubi_change_vtbl_record(ubi, vol_id, &vtbl_rec); if (err) ubi_err("cannot clean auto-resize flag for volume %d", @@ -689,23 +874,31 @@ static int autoresize(struct ubi_device *ubi, int vol_id) /** * ubi_attach_mtd_dev - attach an MTD device. - * @mtd_dev: MTD device description object + * @mtd: MTD device description object * @ubi_num: number to assign to the new UBI device * @vid_hdr_offset: VID header offset + * @max_beb_per1024: maximum expected number of bad PEB per 1024 PEBs * * This function attaches MTD device @mtd_dev to UBI and assign @ubi_num number * to the newly created UBI device, unless @ubi_num is %UBI_DEV_NUM_AUTO, in - * which case this function finds a vacant device nubert and assings it + * which case this function finds a vacant device number and assigns it * automatically. Returns the new UBI device number in case of success and a * negative error code in case of failure. * * Note, the invocations of this function has to be serialized by the * @ubi_devices_mutex. */ -int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) +int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, + int vid_hdr_offset, int max_beb_per1024) { struct ubi_device *ubi; - int i, err; + int i, err, ref = 0; + + if (max_beb_per1024 < 0 || max_beb_per1024 > MAX_MTD_UBI_BEB_LIMIT) + return -EINVAL; + + if (!max_beb_per1024) + max_beb_per1024 = CONFIG_MTD_UBI_BEB_LIMIT; /* * Check if we already have the same MTD device attached. @@ -716,7 +909,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) for (i = 0; i < UBI_MAX_DEVICES; i++) { ubi = ubi_devices[i]; if (ubi && mtd->index == ubi->mtd->index) { - dbg_err("mtd%d is already attached to ubi%d", + ubi_err("mtd%d is already attached to ubi%d", mtd->index, i); return -EEXIST; } @@ -731,8 +924,8 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) * no sense to attach emulated MTD devices, so we prohibit this. */ if (mtd->type == MTD_UBIVOLUME) { - ubi_err("refuse attaching mtd%d - it is already emulated on " - "top of UBI", mtd->index); + ubi_err("refuse attaching mtd%d - it is already emulated on top of UBI", + mtd->index); return -EINVAL; } @@ -742,7 +935,8 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) if (!ubi_devices[ubi_num]) break; if (ubi_num == UBI_MAX_DEVICES) { - dbg_err("only %d UBI devices may be created", UBI_MAX_DEVICES); + ubi_err("only %d UBI devices may be created", + UBI_MAX_DEVICES); return -ENFILE; } } else { @@ -751,7 +945,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) /* Make sure ubi_num is not busy */ if (ubi_devices[ubi_num]) { - dbg_err("ubi%d already exists", ubi_num); + ubi_err("ubi%d already exists", ubi_num); return -EEXIST; } } @@ -765,36 +959,61 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) ubi->vid_hdr_offset = vid_hdr_offset; ubi->autoresize_vol_id = -1; +#ifdef CONFIG_MTD_UBI_FASTMAP + ubi->fm_pool.used = ubi->fm_pool.size = 0; + ubi->fm_wl_pool.used = ubi->fm_wl_pool.size = 0; + + /* + * fm_pool.max_size is 5% of the total number of PEBs but it's also + * between UBI_FM_MAX_POOL_SIZE and UBI_FM_MIN_POOL_SIZE. + */ + ubi->fm_pool.max_size = min(((int)mtd_div_by_eb(ubi->mtd->size, + ubi->mtd) / 100) * 5, UBI_FM_MAX_POOL_SIZE); + if (ubi->fm_pool.max_size < UBI_FM_MIN_POOL_SIZE) + ubi->fm_pool.max_size = UBI_FM_MIN_POOL_SIZE; + + ubi->fm_wl_pool.max_size = UBI_FM_WL_POOL_SIZE; + ubi->fm_disabled = !fm_autoconvert; + + if (!ubi->fm_disabled && (int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) + <= UBI_FM_MAX_START) { + ubi_err("More than %i PEBs are needed for fastmap, sorry.", + UBI_FM_MAX_START); + ubi->fm_disabled = 1; + } + + ubi_msg("default fastmap pool size: %d", ubi->fm_pool.max_size); + ubi_msg("default fastmap WL pool size: %d", ubi->fm_wl_pool.max_size); +#else + ubi->fm_disabled = 1; +#endif mutex_init(&ubi->buf_mutex); mutex_init(&ubi->ckvol_mutex); - mutex_init(&ubi->volumes_mutex); + mutex_init(&ubi->device_mutex); spin_lock_init(&ubi->volumes_lock); + mutex_init(&ubi->fm_mutex); + init_rwsem(&ubi->fm_sem); ubi_msg("attaching mtd%d to ubi%d", mtd->index, ubi_num); - err = io_init(ubi); + err = io_init(ubi, max_beb_per1024); if (err) goto out_free; err = -ENOMEM; - ubi->peb_buf1 = vmalloc(ubi->peb_size); - if (!ubi->peb_buf1) - goto out_free; - - ubi->peb_buf2 = vmalloc(ubi->peb_size); - if (!ubi->peb_buf2) + ubi->peb_buf = vmalloc(ubi->peb_size); + if (!ubi->peb_buf) goto out_free; -#ifdef CONFIG_MTD_UBI_DEBUG - mutex_init(&ubi->dbg_buf_mutex); - ubi->dbg_peb_buf = vmalloc(ubi->peb_size); - if (!ubi->dbg_peb_buf) +#ifdef CONFIG_MTD_UBI_FASTMAP + ubi->fm_size = ubi_calc_fm_size(ubi); + ubi->fm_buf = vzalloc(ubi->fm_size); + if (!ubi->fm_buf) goto out_free; #endif - - err = attach_by_scanning(ubi); + err = ubi_attach(ubi, 0); if (err) { - dbg_err("failed to attach by scanning, error %d", err); + ubi_err("failed to attach mtd%d, error %d", mtd->index, err); goto out_free; } @@ -804,56 +1023,71 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) goto out_detach; } - err = uif_init(ubi); + err = uif_init(ubi, &ref); if (err) goto out_detach; - ubi->bgt_thread = kthread_create(ubi_thread, ubi, ubi->bgt_name); + err = ubi_debugfs_init_dev(ubi); + if (err) + goto out_uif; + + ubi->bgt_thread = kthread_create(ubi_thread, ubi, "%s", ubi->bgt_name); if (IS_ERR(ubi->bgt_thread)) { err = PTR_ERR(ubi->bgt_thread); ubi_err("cannot spawn \"%s\", error %d", ubi->bgt_name, err); - goto out_uif; + goto out_debugfs; } - ubi_msg("attached mtd%d to ubi%d", mtd->index, ubi_num); - ubi_msg("MTD device name: \"%s\"", mtd->name); - ubi_msg("MTD device size: %llu MiB", ubi->flash_size >> 20); - ubi_msg("number of good PEBs: %d", ubi->good_peb_count); - ubi_msg("number of bad PEBs: %d", ubi->bad_peb_count); - ubi_msg("max. allowed volumes: %d", ubi->vtbl_slots); - ubi_msg("wear-leveling threshold: %d", CONFIG_MTD_UBI_WL_THRESHOLD); - ubi_msg("number of internal volumes: %d", UBI_INT_VOL_COUNT); - ubi_msg("number of user volumes: %d", - ubi->vol_count - UBI_INT_VOL_COUNT); - ubi_msg("available PEBs: %d", ubi->avail_pebs); - ubi_msg("total number of reserved PEBs: %d", ubi->rsvd_pebs); - ubi_msg("number of PEBs reserved for bad PEB handling: %d", - ubi->beb_rsvd_pebs); - ubi_msg("max/mean erase counter: %d/%d", ubi->max_ec, ubi->mean_ec); - - /* Enable the background thread */ - if (!DBG_DISABLE_BGT) { - ubi->thread_enabled = 1; - wake_up_process(ubi->bgt_thread); - } + ubi_msg("attached mtd%d (name \"%s\", size %llu MiB) to ubi%d", + mtd->index, mtd->name, ubi->flash_size >> 20, ubi_num); + ubi_msg("PEB size: %d bytes (%d KiB), LEB size: %d bytes", + ubi->peb_size, ubi->peb_size >> 10, ubi->leb_size); + ubi_msg("min./max. I/O unit sizes: %d/%d, sub-page size %d", + ubi->min_io_size, ubi->max_write_size, ubi->hdrs_min_io_size); + ubi_msg("VID header offset: %d (aligned %d), data offset: %d", + ubi->vid_hdr_offset, ubi->vid_hdr_aloffset, ubi->leb_start); + ubi_msg("good PEBs: %d, bad PEBs: %d, corrupted PEBs: %d", + ubi->good_peb_count, ubi->bad_peb_count, ubi->corr_peb_count); + ubi_msg("user volume: %d, internal volumes: %d, max. volumes count: %d", + ubi->vol_count - UBI_INT_VOL_COUNT, UBI_INT_VOL_COUNT, + ubi->vtbl_slots); + ubi_msg("max/mean erase counter: %d/%d, WL threshold: %d, image sequence number: %u", + ubi->max_ec, ubi->mean_ec, CONFIG_MTD_UBI_WL_THRESHOLD, + ubi->image_seq); + ubi_msg("available PEBs: %d, total reserved PEBs: %d, PEBs reserved for bad PEB handling: %d", + ubi->avail_pebs, ubi->rsvd_pebs, ubi->beb_rsvd_pebs); + + /* + * The below lock makes sure we do not race with 'ubi_thread()' which + * checks @ubi->thread_enabled. Otherwise we may fail to wake it up. + */ + spin_lock(&ubi->wl_lock); + ubi->thread_enabled = 1; + wake_up_process(ubi->bgt_thread); + spin_unlock(&ubi->wl_lock); ubi_devices[ubi_num] = ubi; + ubi_notify_all(ubi, UBI_VOLUME_ADDED, NULL); return ubi_num; +out_debugfs: + ubi_debugfs_exit_dev(ubi); out_uif: + get_device(&ubi->dev); + ubi_assert(ref); uif_close(ubi); out_detach: - ubi_eba_close(ubi); ubi_wl_close(ubi); + ubi_free_internal_volumes(ubi); vfree(ubi->vtbl); out_free: - vfree(ubi->peb_buf1); - vfree(ubi->peb_buf2); -#ifdef CONFIG_MTD_UBI_DEBUG - vfree(ubi->dbg_peb_buf); -#endif - kfree(ubi); + vfree(ubi->peb_buf); + vfree(ubi->fm_buf); + if (ref) + put_device(&ubi->dev); + else + kfree(ubi); return err; } @@ -877,13 +1111,13 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway) if (ubi_num < 0 || ubi_num >= UBI_MAX_DEVICES) return -EINVAL; - spin_lock(&ubi_devices_lock); - ubi = ubi_devices[ubi_num]; - if (!ubi) { - spin_unlock(&ubi_devices_lock); + ubi = ubi_get_device(ubi_num); + if (!ubi) return -EINVAL; - } + spin_lock(&ubi_devices_lock); + put_device(&ubi->dev); + ubi->ref_count -= 1; if (ubi->ref_count) { if (!anyway) { spin_unlock(&ubi_devices_lock); @@ -897,8 +1131,13 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway) spin_unlock(&ubi_devices_lock); ubi_assert(ubi_num == ubi->ubi_num); - dbg_msg("detaching mtd%d from ubi%d", ubi->mtd->index, ubi_num); - + ubi_notify_all(ubi, UBI_VOLUME_REMOVED, NULL); + ubi_msg("detaching mtd%d from ubi%d", ubi->mtd->index, ubi_num); +#ifdef CONFIG_MTD_UBI_FASTMAP + /* If we don't write a new fastmap at detach time we lose all + * EC updates that have been made since the last written fastmap. */ + ubi_update_fastmap(ubi); +#endif /* * Before freeing anything, we have to stop the background thread to * prevent it from doing anything on this device while we are freeing. @@ -906,29 +1145,73 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway) if (ubi->bgt_thread) kthread_stop(ubi->bgt_thread); + /* + * Get a reference to the device in order to prevent 'dev_release()' + * from freeing the @ubi object. + */ + get_device(&ubi->dev); + + ubi_debugfs_exit_dev(ubi); uif_close(ubi); - ubi_eba_close(ubi); + ubi_wl_close(ubi); + ubi_free_internal_volumes(ubi); vfree(ubi->vtbl); put_mtd_device(ubi->mtd); - vfree(ubi->peb_buf1); - vfree(ubi->peb_buf2); -#ifdef CONFIG_MTD_UBI_DEBUG - vfree(ubi->dbg_peb_buf); -#endif + vfree(ubi->peb_buf); + vfree(ubi->fm_buf); ubi_msg("mtd%d is detached from ubi%d", ubi->mtd->index, ubi->ubi_num); - kfree(ubi); + put_device(&ubi->dev); return 0; } +#ifndef __UBOOT__ +/** + * open_mtd_by_chdev - open an MTD device by its character device node path. + * @mtd_dev: MTD character device node path + * + * This helper function opens an MTD device by its character node device path. + * Returns MTD device description object in case of success and a negative + * error code in case of failure. + */ +static struct mtd_info * __init open_mtd_by_chdev(const char *mtd_dev) +{ + int err, major, minor, mode; + struct path path; + + /* Probably this is an MTD character device node path */ + err = kern_path(mtd_dev, LOOKUP_FOLLOW, &path); + if (err) + return ERR_PTR(err); + + /* MTD device number is defined by the major / minor numbers */ + major = imajor(path.dentry->d_inode); + minor = iminor(path.dentry->d_inode); + mode = path.dentry->d_inode->i_mode; + path_put(&path); + if (major != MTD_CHAR_MAJOR || !S_ISCHR(mode)) + return ERR_PTR(-EINVAL); + + if (minor & 1) + /* + * Just do not think the "/dev/mtdrX" devices support is need, + * so do not support them to avoid doing extra work. + */ + return ERR_PTR(-EINVAL); + + return get_mtd_device(NULL, minor / 2); +} +#endif + /** - * find_mtd_device - open an MTD device by its name or number. - * @mtd_dev: name or number of the device + * open_mtd_device - open MTD device by name, character device path, or number. + * @mtd_dev: name, character device node path, or MTD device device number * * This function tries to open and MTD device described by @mtd_dev string, - * which is first treated as an ASCII number, and if it is not true, it is - * treated as MTD device name. Returns MTD device description object in case of - * success and a negative error code in case of failure. + * which is first treated as ASCII MTD device number, and if it is not true, it + * is treated as MTD device name, and if that is also not true, it is treated + * as MTD character device node path. Returns MTD device description object in + * case of success and a negative error code in case of failure. */ static struct mtd_info * __init open_mtd_device(const char *mtd_dev) { @@ -943,13 +1226,22 @@ static struct mtd_info * __init open_mtd_device(const char *mtd_dev) * MTD device name. */ mtd = get_mtd_device_nm(mtd_dev); +#ifndef __UBOOT__ + if (IS_ERR(mtd) && PTR_ERR(mtd) == -ENODEV) + /* Probably this is an MTD character device node path */ + mtd = open_mtd_by_chdev(mtd_dev); +#endif } else mtd = get_mtd_device(NULL, mtd_num); return mtd; } -int __init ubi_init(void) +#ifndef __UBOOT__ +static int __init ubi_init(void) +#else +int ubi_init(void) +#endif { int err, i, k; @@ -982,13 +1274,18 @@ int __init ubi_init(void) goto out_version; } -#ifdef UBI_LINUX ubi_wl_entry_slab = kmem_cache_create("ubi_wl_entry_slab", sizeof(struct ubi_wl_entry), 0, 0, NULL); - if (!ubi_wl_entry_slab) + if (!ubi_wl_entry_slab) { + err = -ENOMEM; goto out_dev_unreg; -#endif + } + + err = ubi_debugfs_init(); + if (err) + goto out_slab; + /* Attach MTD devices */ for (i = 0; i < mtd_devs; i++) { @@ -1000,20 +1297,48 @@ int __init ubi_init(void) mtd = open_mtd_device(p->name); if (IS_ERR(mtd)) { err = PTR_ERR(mtd); - goto out_detach; + ubi_err("cannot open mtd %s, error %d", p->name, err); + /* See comment below re-ubi_is_module(). */ + if (ubi_is_module()) + goto out_detach; + continue; } mutex_lock(&ubi_devices_mutex); - err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, - p->vid_hdr_offs); + err = ubi_attach_mtd_dev(mtd, p->ubi_num, + p->vid_hdr_offs, p->max_beb_per1024); mutex_unlock(&ubi_devices_mutex); if (err < 0) { - put_mtd_device(mtd); ubi_err("cannot attach mtd%d", mtd->index); - goto out_detach; + put_mtd_device(mtd); + + /* + * Originally UBI stopped initializing on any error. + * However, later on it was found out that this + * behavior is not very good when UBI is compiled into + * the kernel and the MTD devices to attach are passed + * through the command line. Indeed, UBI failure + * stopped whole boot sequence. + * + * To fix this, we changed the behavior for the + * non-module case, but preserved the old behavior for + * the module case, just for compatibility. This is a + * little inconsistent, though. + */ + if (ubi_is_module()) + goto out_detach; } } + err = ubiblock_init(); + if (err) { + ubi_err("block: cannot initialize, error %d", err); + + /* See comment above re-ubi_is_module(). */ + if (ubi_is_module()) + goto out_detach; + } + return 0; out_detach: @@ -1023,43 +1348,47 @@ out_detach: ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1); mutex_unlock(&ubi_devices_mutex); } -#ifdef UBI_LINUX + ubi_debugfs_exit(); +out_slab: kmem_cache_destroy(ubi_wl_entry_slab); out_dev_unreg: -#endif misc_deregister(&ubi_ctrl_cdev); out_version: class_remove_file(ubi_class, &ubi_version); out_class: class_destroy(ubi_class); out: - mtd_devs = 0; - ubi_err("UBI error: cannot initialize UBI, error %d", err); + ubi_err("cannot initialize UBI, error %d", err); return err; } -module_init(ubi_init); +late_initcall(ubi_init); -void __exit ubi_exit(void) +#ifndef __UBOOT__ +static void __exit ubi_exit(void) +#else +void ubi_exit(void) +#endif { int i; + ubiblock_exit(); + for (i = 0; i < UBI_MAX_DEVICES; i++) if (ubi_devices[i]) { mutex_lock(&ubi_devices_mutex); ubi_detach_mtd_dev(ubi_devices[i]->ubi_num, 1); mutex_unlock(&ubi_devices_mutex); } + ubi_debugfs_exit(); kmem_cache_destroy(ubi_wl_entry_slab); misc_deregister(&ubi_ctrl_cdev); class_remove_file(ubi_class, &ubi_version); class_destroy(ubi_class); - mtd_devs = 0; } module_exit(ubi_exit); /** - * bytes_str_to_int - convert a string representing number of bytes to an - * integer. + * bytes_str_to_int - convert a number of bytes string into an integer. * @str: the string to convert * * This function returns positive resulting integer in case of success and a @@ -1071,9 +1400,8 @@ static int __init bytes_str_to_int(const char *str) unsigned long result; result = simple_strtoul(str, &endp, 0); - if (str == endp || result < 0) { - printk(KERN_ERR "UBI error: incorrect bytes count: \"%s\"\n", - str); + if (str == endp || result >= INT_MAX) { + ubi_err("incorrect bytes count: \"%s\"\n", str); return -EINVAL; } @@ -1089,14 +1417,24 @@ static int __init bytes_str_to_int(const char *str) case '\0': break; default: - printk(KERN_ERR "UBI error: incorrect bytes count: \"%s\"\n", - str); + ubi_err("incorrect bytes count: \"%s\"\n", str); return -EINVAL; } return result; } +int kstrtoint(const char *s, unsigned int base, int *res) +{ + unsigned long long tmp; + + tmp = simple_strtoull(s, NULL, base); + if (tmp != (unsigned long long)(int)tmp) + return -ERANGE; + + return (int)tmp; +} + /** * ubi_mtd_param_parse - parse the 'mtd=' UBI parameter. * @val: the parameter value to parse @@ -1105,33 +1443,36 @@ static int __init bytes_str_to_int(const char *str) * This function returns zero in case of success and a negative error code in * case of error. */ -int __init ubi_mtd_param_parse(const char *val, struct kernel_param *kp) +#ifndef __UBOOT__ +static int __init ubi_mtd_param_parse(const char *val, struct kernel_param *kp) +#else +int ubi_mtd_param_parse(const char *val, struct kernel_param *kp) +#endif { int i, len; struct mtd_dev_param *p; char buf[MTD_PARAM_LEN_MAX]; char *pbuf = &buf[0]; - char *tokens[2] = {NULL, NULL}; + char *tokens[MTD_PARAM_MAX_COUNT], *token; if (!val) return -EINVAL; if (mtd_devs == UBI_MAX_DEVICES) { - printk(KERN_ERR "UBI error: too many parameters, max. is %d\n", - UBI_MAX_DEVICES); + ubi_err("too many parameters, max. is %d\n", + UBI_MAX_DEVICES); return -EINVAL; } len = strnlen(val, MTD_PARAM_LEN_MAX); if (len == MTD_PARAM_LEN_MAX) { - printk(KERN_ERR "UBI error: parameter \"%s\" is too long, " - "max. is %d\n", val, MTD_PARAM_LEN_MAX); + ubi_err("parameter \"%s\" is too long, max. is %d\n", + val, MTD_PARAM_LEN_MAX); return -EINVAL; } if (len == 0) { - printk(KERN_WARNING "UBI warning: empty 'mtd=' parameter - " - "ignored\n"); + pr_warn("UBI warning: empty 'mtd=' parameter - ignored\n"); return 0; } @@ -1141,40 +1482,69 @@ int __init ubi_mtd_param_parse(const char *val, struct kernel_param *kp) if (buf[len - 1] == '\n') buf[len - 1] = '\0'; - for (i = 0; i < 2; i++) + for (i = 0; i < MTD_PARAM_MAX_COUNT; i++) tokens[i] = strsep(&pbuf, ","); if (pbuf) { - printk(KERN_ERR "UBI error: too many arguments at \"%s\"\n", - val); + ubi_err("too many arguments at \"%s\"\n", val); return -EINVAL; } p = &mtd_dev_param[mtd_devs]; strcpy(&p->name[0], tokens[0]); - if (tokens[1]) - p->vid_hdr_offs = bytes_str_to_int(tokens[1]); + token = tokens[1]; + if (token) { + p->vid_hdr_offs = bytes_str_to_int(token); + + if (p->vid_hdr_offs < 0) + return p->vid_hdr_offs; + } + + token = tokens[2]; + if (token) { + int err = kstrtoint(token, 10, &p->max_beb_per1024); + + if (err) { + ubi_err("bad value for max_beb_per1024 parameter: %s", + token); + return -EINVAL; + } + } - if (p->vid_hdr_offs < 0) - return p->vid_hdr_offs; + token = tokens[3]; + if (token) { + int err = kstrtoint(token, 10, &p->ubi_num); + + if (err) { + ubi_err("bad value for ubi_num parameter: %s", token); + return -EINVAL; + } + } else + p->ubi_num = UBI_DEV_NUM_AUTO; mtd_devs += 1; return 0; } module_param_call(mtd, ubi_mtd_param_parse, NULL, NULL, 000); -MODULE_PARM_DESC(mtd, "MTD devices to attach. Parameter format: " - "mtd=[,].\n" +MODULE_PARM_DESC(mtd, "MTD devices to attach. Parameter format: mtd=[,[,max_beb_per1024[,ubi_num]]].\n" "Multiple \"mtd\" parameters may be specified.\n" - "MTD devices may be specified by their number or name.\n" - "Optional \"vid_hdr_offs\" parameter specifies UBI VID " - "header position and data starting position to be used " - "by UBI.\n" - "Example: mtd=content,1984 mtd=4 - attach MTD device" - "with name \"content\" using VID header offset 1984, and " - "MTD device number 4 with default VID header offset."); - + "MTD devices may be specified by their number, name, or path to the MTD character device node.\n" + "Optional \"vid_hdr_offs\" parameter specifies UBI VID header position to be used by UBI. (default value if 0)\n" + "Optional \"max_beb_per1024\" parameter specifies the maximum expected bad eraseblock per 1024 eraseblocks. (default value (" + __stringify(CONFIG_MTD_UBI_BEB_LIMIT) ") if 0)\n" + "Optional \"ubi_num\" parameter specifies UBI device number which have to be assigned to the newly created UBI device (assigned automatically by default)\n" + "\n" + "Example 1: mtd=/dev/mtd0 - attach MTD device /dev/mtd0.\n" + "Example 2: mtd=content,1984 mtd=4 - attach MTD device with name \"content\" using VID header offset 1984, and MTD device number 4 with default VID header offset.\n" + "Example 3: mtd=/dev/mtd1,0,25 - attach MTD device /dev/mtd1 using default VID header offset and reserve 25*nand_size_in_blocks/1024 erase blocks for bad block handling.\n" + "Example 4: mtd=/dev/mtd1,0,0,5 - attach MTD device /dev/mtd1 to UBI 5 and using default values for the other fields.\n" + "\t(e.g. if the NAND *chipset* has 4096 PEB, 100 will be reserved for this UBI device)."); +#ifdef CONFIG_MTD_UBI_FASTMAP +module_param(fm_autoconvert, bool, 0644); +MODULE_PARM_DESC(fm_autoconvert, "Set this parameter to enable fastmap automatically on images without a fastmap."); +#endif MODULE_VERSION(__stringify(UBI_VERSION)); MODULE_DESCRIPTION("UBI - Unsorted Block Images"); MODULE_AUTHOR("Artem Bityutskiy"); diff --git a/drivers/mtd/ubi/crc32.c b/drivers/mtd/ubi/crc32.c index ab439b3e20..9c54ea4db0 100644 --- a/drivers/mtd/ubi/crc32.c +++ b/drivers/mtd/ubi/crc32.c @@ -20,7 +20,7 @@ * Version 2. See the file COPYING for more details. */ -#ifdef UBI_LINUX +#ifndef __UBOOT__ #include #include #include @@ -30,7 +30,7 @@ #include -#ifdef UBI_LINUX +#ifndef __UBOOT__ #include #include #include @@ -46,7 +46,7 @@ #define tobe(x) (x) #endif #include "crc32table.h" -#ifdef UBI_LINUX +#ifndef __UBOOT__ MODULE_AUTHOR("Matt Domsch "); MODULE_DESCRIPTION("Ethernet CRC32 calculations"); MODULE_LICENSE("GPL"); @@ -102,7 +102,7 @@ u32 crc32_le(u32 crc, unsigned char const *p, size_t len) if((len >= 4)){ /* load data 32 bits wide, xor data 32 bits wide. */ size_t save_len = len & 3; - len = len >> 2; + len = len >> 2; --b; /* use pre increment below(*++b) for speed */ do { crc ^= *++b; @@ -146,7 +146,7 @@ u32 crc32_le(u32 crc, unsigned char const *p, size_t len) # endif } #endif -#ifdef UBI_LINUX +#ifndef __UBOOT__ /** * crc32_be() - Calculate bitwise big-endian Ethernet AUTODIN II CRC32 * @crc: seed value for computation. ~0 for Ethernet, sometimes 0 for @@ -200,7 +200,7 @@ u32 __attribute_pure__ crc32_be(u32 crc, unsigned char const *p, size_t len) if(likely(len >= 4)){ /* load data 32 bits wide, xor data 32 bits wide. */ size_t save_len = len & 3; - len = len >> 2; + len = len >> 2; --b; /* use pre increment below(*++b) for speed */ do { crc ^= *++b; @@ -379,7 +379,7 @@ EXPORT_SYMBOL(crc32_be); #include #include -#ifdef UBI_LINUX /*Not used at present */ +#ifndef __UBOOT__ static void buf_dump(char const *prefix, unsigned char const *buf, size_t len) { @@ -405,7 +405,7 @@ static void random_garbage(unsigned char *buf, size_t len) *buf++ = (unsigned char) random(); } -#ifdef UBI_LINUX /* Not used at present */ +#ifndef __UBOOT__ static void store_le(u32 x, unsigned char *buf) { buf[0] = (unsigned char) x; diff --git a/drivers/mtd/ubi/crc32table.h b/drivers/mtd/ubi/crc32table.h index 0438af4350..02ce6fd901 100644 --- a/drivers/mtd/ubi/crc32table.h +++ b/drivers/mtd/ubi/crc32table.h @@ -66,7 +66,7 @@ tole(0xbad03605L), tole(0xcdd70693L), tole(0x54de5729L), tole(0x23d967bfL), tole(0xb3667a2eL), tole(0xc4614ab8L), tole(0x5d681b02L), tole(0x2a6f2b94L), tole(0xb40bbe37L), tole(0xc30c8ea1L), tole(0x5a05df1bL), tole(0x2d02ef8dL) }; -#ifdef UBI_LINUX +#ifndef __UBOOT__ static const u32 crc32table_be[] = { tobe(0x00000000L), tobe(0x04c11db7L), tobe(0x09823b6eL), tobe(0x0d4326d9L), tobe(0x130476dcL), tobe(0x17c56b6bL), tobe(0x1a864db2L), tobe(0x1e475005L), diff --git a/drivers/mtd/ubi/debug.c b/drivers/mtd/ubi/debug.c index 6c22301d93..6dcc4e4844 100644 --- a/drivers/mtd/ubi/debug.c +++ b/drivers/mtd/ubi/debug.c @@ -6,175 +6,454 @@ * Author: Artem Bityutskiy (Битюцкий Артём) */ -/* - * Here we keep all the UBI debugging stuff which should normally be disabled - * and compiled-out, but it is extremely helpful when hunting bugs or doing big - * changes. - */ #include +#include "ubi.h" +#ifndef __UBOOT__ +#include +#include +#include +#endif -#ifdef CONFIG_MTD_UBI_DEBUG_MSG +/** + * ubi_dump_flash - dump a region of flash. + * @ubi: UBI device description object + * @pnum: the physical eraseblock number to dump + * @offset: the starting offset within the physical eraseblock to dump + * @len: the length of the region to dump + */ +void ubi_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len) +{ + int err; + size_t read; + void *buf; + loff_t addr = (loff_t)pnum * ubi->peb_size + offset; -#include "ubi.h" + buf = vmalloc(len); + if (!buf) + return; + err = mtd_read(ubi->mtd, addr, len, &read, buf); + if (err && err != -EUCLEAN) { + ubi_err("error %d while reading %d bytes from PEB %d:%d, read %zd bytes", + err, len, pnum, offset, read); + goto out; + } + + ubi_msg("dumping %d bytes of data from PEB %d, offset %d", + len, pnum, offset); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, buf, len, 1); +out: + vfree(buf); + return; +} /** - * ubi_dbg_dump_ec_hdr - dump an erase counter header. + * ubi_dump_ec_hdr - dump an erase counter header. * @ec_hdr: the erase counter header to dump */ -void ubi_dbg_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr) -{ - dbg_msg("erase counter header dump:"); - dbg_msg("magic %#08x", be32_to_cpu(ec_hdr->magic)); - dbg_msg("version %d", (int)ec_hdr->version); - dbg_msg("ec %llu", (long long)be64_to_cpu(ec_hdr->ec)); - dbg_msg("vid_hdr_offset %d", be32_to_cpu(ec_hdr->vid_hdr_offset)); - dbg_msg("data_offset %d", be32_to_cpu(ec_hdr->data_offset)); - dbg_msg("hdr_crc %#08x", be32_to_cpu(ec_hdr->hdr_crc)); - dbg_msg("erase counter header hexdump:"); +void ubi_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr) +{ + pr_err("Erase counter header dump:\n"); + pr_err("\tmagic %#08x\n", be32_to_cpu(ec_hdr->magic)); + pr_err("\tversion %d\n", (int)ec_hdr->version); + pr_err("\tec %llu\n", (long long)be64_to_cpu(ec_hdr->ec)); + pr_err("\tvid_hdr_offset %d\n", be32_to_cpu(ec_hdr->vid_hdr_offset)); + pr_err("\tdata_offset %d\n", be32_to_cpu(ec_hdr->data_offset)); + pr_err("\timage_seq %d\n", be32_to_cpu(ec_hdr->image_seq)); + pr_err("\thdr_crc %#08x\n", be32_to_cpu(ec_hdr->hdr_crc)); + pr_err("erase counter header hexdump:\n"); print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, ec_hdr, UBI_EC_HDR_SIZE, 1); } /** - * ubi_dbg_dump_vid_hdr - dump a volume identifier header. + * ubi_dump_vid_hdr - dump a volume identifier header. * @vid_hdr: the volume identifier header to dump */ -void ubi_dbg_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr) -{ - dbg_msg("volume identifier header dump:"); - dbg_msg("magic %08x", be32_to_cpu(vid_hdr->magic)); - dbg_msg("version %d", (int)vid_hdr->version); - dbg_msg("vol_type %d", (int)vid_hdr->vol_type); - dbg_msg("copy_flag %d", (int)vid_hdr->copy_flag); - dbg_msg("compat %d", (int)vid_hdr->compat); - dbg_msg("vol_id %d", be32_to_cpu(vid_hdr->vol_id)); - dbg_msg("lnum %d", be32_to_cpu(vid_hdr->lnum)); - dbg_msg("leb_ver %u", be32_to_cpu(vid_hdr->leb_ver)); - dbg_msg("data_size %d", be32_to_cpu(vid_hdr->data_size)); - dbg_msg("used_ebs %d", be32_to_cpu(vid_hdr->used_ebs)); - dbg_msg("data_pad %d", be32_to_cpu(vid_hdr->data_pad)); - dbg_msg("sqnum %llu", +void ubi_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr) +{ + pr_err("Volume identifier header dump:\n"); + pr_err("\tmagic %08x\n", be32_to_cpu(vid_hdr->magic)); + pr_err("\tversion %d\n", (int)vid_hdr->version); + pr_err("\tvol_type %d\n", (int)vid_hdr->vol_type); + pr_err("\tcopy_flag %d\n", (int)vid_hdr->copy_flag); + pr_err("\tcompat %d\n", (int)vid_hdr->compat); + pr_err("\tvol_id %d\n", be32_to_cpu(vid_hdr->vol_id)); + pr_err("\tlnum %d\n", be32_to_cpu(vid_hdr->lnum)); + pr_err("\tdata_size %d\n", be32_to_cpu(vid_hdr->data_size)); + pr_err("\tused_ebs %d\n", be32_to_cpu(vid_hdr->used_ebs)); + pr_err("\tdata_pad %d\n", be32_to_cpu(vid_hdr->data_pad)); + pr_err("\tsqnum %llu\n", (unsigned long long)be64_to_cpu(vid_hdr->sqnum)); - dbg_msg("hdr_crc %08x", be32_to_cpu(vid_hdr->hdr_crc)); - dbg_msg("volume identifier header hexdump:"); + pr_err("\thdr_crc %08x\n", be32_to_cpu(vid_hdr->hdr_crc)); + pr_err("Volume identifier header hexdump:\n"); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + vid_hdr, UBI_VID_HDR_SIZE, 1); } /** - * ubi_dbg_dump_vol_info- dump volume information. + * ubi_dump_vol_info - dump volume information. * @vol: UBI volume description object */ -void ubi_dbg_dump_vol_info(const struct ubi_volume *vol) -{ - dbg_msg("volume information dump:"); - dbg_msg("vol_id %d", vol->vol_id); - dbg_msg("reserved_pebs %d", vol->reserved_pebs); - dbg_msg("alignment %d", vol->alignment); - dbg_msg("data_pad %d", vol->data_pad); - dbg_msg("vol_type %d", vol->vol_type); - dbg_msg("name_len %d", vol->name_len); - dbg_msg("usable_leb_size %d", vol->usable_leb_size); - dbg_msg("used_ebs %d", vol->used_ebs); - dbg_msg("used_bytes %lld", vol->used_bytes); - dbg_msg("last_eb_bytes %d", vol->last_eb_bytes); - dbg_msg("corrupted %d", vol->corrupted); - dbg_msg("upd_marker %d", vol->upd_marker); +void ubi_dump_vol_info(const struct ubi_volume *vol) +{ + printf("Volume information dump:\n"); + printf("\tvol_id %d\n", vol->vol_id); + printf("\treserved_pebs %d\n", vol->reserved_pebs); + printf("\talignment %d\n", vol->alignment); + printf("\tdata_pad %d\n", vol->data_pad); + printf("\tvol_type %d\n", vol->vol_type); + printf("\tname_len %d\n", vol->name_len); + printf("\tusable_leb_size %d\n", vol->usable_leb_size); + printf("\tused_ebs %d\n", vol->used_ebs); + printf("\tused_bytes %lld\n", vol->used_bytes); + printf("\tlast_eb_bytes %d\n", vol->last_eb_bytes); + printf("\tcorrupted %d\n", vol->corrupted); + printf("\tupd_marker %d\n", vol->upd_marker); if (vol->name_len <= UBI_VOL_NAME_MAX && strnlen(vol->name, vol->name_len + 1) == vol->name_len) { - dbg_msg("name %s", vol->name); + printf("\tname %s\n", vol->name); } else { - dbg_msg("the 1st 5 characters of the name: %c%c%c%c%c", - vol->name[0], vol->name[1], vol->name[2], - vol->name[3], vol->name[4]); + printf("\t1st 5 characters of name: %c%c%c%c%c\n", + vol->name[0], vol->name[1], vol->name[2], + vol->name[3], vol->name[4]); } } /** - * ubi_dbg_dump_vtbl_record - dump a &struct ubi_vtbl_record object. + * ubi_dump_vtbl_record - dump a &struct ubi_vtbl_record object. * @r: the object to dump * @idx: volume table index */ -void ubi_dbg_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx) +void ubi_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx) { int name_len = be16_to_cpu(r->name_len); - dbg_msg("volume table record %d dump:", idx); - dbg_msg("reserved_pebs %d", be32_to_cpu(r->reserved_pebs)); - dbg_msg("alignment %d", be32_to_cpu(r->alignment)); - dbg_msg("data_pad %d", be32_to_cpu(r->data_pad)); - dbg_msg("vol_type %d", (int)r->vol_type); - dbg_msg("upd_marker %d", (int)r->upd_marker); - dbg_msg("name_len %d", name_len); + pr_err("Volume table record %d dump:\n", idx); + pr_err("\treserved_pebs %d\n", be32_to_cpu(r->reserved_pebs)); + pr_err("\talignment %d\n", be32_to_cpu(r->alignment)); + pr_err("\tdata_pad %d\n", be32_to_cpu(r->data_pad)); + pr_err("\tvol_type %d\n", (int)r->vol_type); + pr_err("\tupd_marker %d\n", (int)r->upd_marker); + pr_err("\tname_len %d\n", name_len); if (r->name[0] == '\0') { - dbg_msg("name NULL"); + pr_err("\tname NULL\n"); return; } if (name_len <= UBI_VOL_NAME_MAX && strnlen(&r->name[0], name_len + 1) == name_len) { - dbg_msg("name %s", &r->name[0]); + pr_err("\tname %s\n", &r->name[0]); } else { - dbg_msg("1st 5 characters of the name: %c%c%c%c%c", + pr_err("\t1st 5 characters of name: %c%c%c%c%c\n", r->name[0], r->name[1], r->name[2], r->name[3], r->name[4]); } - dbg_msg("crc %#08x", be32_to_cpu(r->crc)); + pr_err("\tcrc %#08x\n", be32_to_cpu(r->crc)); } /** - * ubi_dbg_dump_sv - dump a &struct ubi_scan_volume object. - * @sv: the object to dump + * ubi_dump_av - dump a &struct ubi_ainf_volume object. + * @av: the object to dump */ -void ubi_dbg_dump_sv(const struct ubi_scan_volume *sv) +void ubi_dump_av(const struct ubi_ainf_volume *av) { - dbg_msg("volume scanning information dump:"); - dbg_msg("vol_id %d", sv->vol_id); - dbg_msg("highest_lnum %d", sv->highest_lnum); - dbg_msg("leb_count %d", sv->leb_count); - dbg_msg("compat %d", sv->compat); - dbg_msg("vol_type %d", sv->vol_type); - dbg_msg("used_ebs %d", sv->used_ebs); - dbg_msg("last_data_size %d", sv->last_data_size); - dbg_msg("data_pad %d", sv->data_pad); + pr_err("Volume attaching information dump:\n"); + pr_err("\tvol_id %d\n", av->vol_id); + pr_err("\thighest_lnum %d\n", av->highest_lnum); + pr_err("\tleb_count %d\n", av->leb_count); + pr_err("\tcompat %d\n", av->compat); + pr_err("\tvol_type %d\n", av->vol_type); + pr_err("\tused_ebs %d\n", av->used_ebs); + pr_err("\tlast_data_size %d\n", av->last_data_size); + pr_err("\tdata_pad %d\n", av->data_pad); } /** - * ubi_dbg_dump_seb - dump a &struct ubi_scan_leb object. - * @seb: the object to dump + * ubi_dump_aeb - dump a &struct ubi_ainf_peb object. + * @aeb: the object to dump * @type: object type: 0 - not corrupted, 1 - corrupted */ -void ubi_dbg_dump_seb(const struct ubi_scan_leb *seb, int type) +void ubi_dump_aeb(const struct ubi_ainf_peb *aeb, int type) { - dbg_msg("eraseblock scanning information dump:"); - dbg_msg("ec %d", seb->ec); - dbg_msg("pnum %d", seb->pnum); + pr_err("eraseblock attaching information dump:\n"); + pr_err("\tec %d\n", aeb->ec); + pr_err("\tpnum %d\n", aeb->pnum); if (type == 0) { - dbg_msg("lnum %d", seb->lnum); - dbg_msg("scrub %d", seb->scrub); - dbg_msg("sqnum %llu", seb->sqnum); - dbg_msg("leb_ver %u", seb->leb_ver); + pr_err("\tlnum %d\n", aeb->lnum); + pr_err("\tscrub %d\n", aeb->scrub); + pr_err("\tsqnum %llu\n", aeb->sqnum); } } /** - * ubi_dbg_dump_mkvol_req - dump a &struct ubi_mkvol_req object. + * ubi_dump_mkvol_req - dump a &struct ubi_mkvol_req object. * @req: the object to dump */ -void ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req) +void ubi_dump_mkvol_req(const struct ubi_mkvol_req *req) { char nm[17]; - dbg_msg("volume creation request dump:"); - dbg_msg("vol_id %d", req->vol_id); - dbg_msg("alignment %d", req->alignment); - dbg_msg("bytes %lld", (long long)req->bytes); - dbg_msg("vol_type %d", req->vol_type); - dbg_msg("name_len %d", req->name_len); + pr_err("Volume creation request dump:\n"); + pr_err("\tvol_id %d\n", req->vol_id); + pr_err("\talignment %d\n", req->alignment); + pr_err("\tbytes %lld\n", (long long)req->bytes); + pr_err("\tvol_type %d\n", req->vol_type); + pr_err("\tname_len %d\n", req->name_len); memcpy(nm, req->name, 16); nm[16] = 0; - dbg_msg("the 1st 16 characters of the name: %s", nm); + pr_err("\t1st 16 characters of name: %s\n", nm); } -#endif /* CONFIG_MTD_UBI_DEBUG_MSG */ +#ifndef __UBOOT__ +/* + * Root directory for UBI stuff in debugfs. Contains sub-directories which + * contain the stuff specific to particular UBI devices. + */ +static struct dentry *dfs_rootdir; + +/** + * ubi_debugfs_init - create UBI debugfs directory. + * + * Create UBI debugfs directory. Returns zero in case of success and a negative + * error code in case of failure. + */ +int ubi_debugfs_init(void) +{ + if (!IS_ENABLED(CONFIG_DEBUG_FS)) + return 0; + + dfs_rootdir = debugfs_create_dir("ubi", NULL); + if (IS_ERR_OR_NULL(dfs_rootdir)) { + int err = dfs_rootdir ? -ENODEV : PTR_ERR(dfs_rootdir); + + ubi_err("cannot create \"ubi\" debugfs directory, error %d\n", + err); + return err; + } + + return 0; +} + +/** + * ubi_debugfs_exit - remove UBI debugfs directory. + */ +void ubi_debugfs_exit(void) +{ + if (IS_ENABLED(CONFIG_DEBUG_FS)) + debugfs_remove(dfs_rootdir); +} + +/* Read an UBI debugfs file */ +static ssize_t dfs_file_read(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + unsigned long ubi_num = (unsigned long)file->private_data; + struct dentry *dent = file->f_path.dentry; + struct ubi_device *ubi; + struct ubi_debug_info *d; + char buf[3]; + int val; + + ubi = ubi_get_device(ubi_num); + if (!ubi) + return -ENODEV; + d = &ubi->dbg; + + if (dent == d->dfs_chk_gen) + val = d->chk_gen; + else if (dent == d->dfs_chk_io) + val = d->chk_io; + else if (dent == d->dfs_disable_bgt) + val = d->disable_bgt; + else if (dent == d->dfs_emulate_bitflips) + val = d->emulate_bitflips; + else if (dent == d->dfs_emulate_io_failures) + val = d->emulate_io_failures; + else { + count = -EINVAL; + goto out; + } + + if (val) + buf[0] = '1'; + else + buf[0] = '0'; + buf[1] = '\n'; + buf[2] = 0x00; + + count = simple_read_from_buffer(user_buf, count, ppos, buf, 2); + +out: + ubi_put_device(ubi); + return count; +} + +/* Write an UBI debugfs file */ +static ssize_t dfs_file_write(struct file *file, const char __user *user_buf, + size_t count, loff_t *ppos) +{ + unsigned long ubi_num = (unsigned long)file->private_data; + struct dentry *dent = file->f_path.dentry; + struct ubi_device *ubi; + struct ubi_debug_info *d; + size_t buf_size; + char buf[8]; + int val; + + ubi = ubi_get_device(ubi_num); + if (!ubi) + return -ENODEV; + d = &ubi->dbg; + + buf_size = min_t(size_t, count, (sizeof(buf) - 1)); + if (copy_from_user(buf, user_buf, buf_size)) { + count = -EFAULT; + goto out; + } + + if (buf[0] == '1') + val = 1; + else if (buf[0] == '0') + val = 0; + else { + count = -EINVAL; + goto out; + } + + if (dent == d->dfs_chk_gen) + d->chk_gen = val; + else if (dent == d->dfs_chk_io) + d->chk_io = val; + else if (dent == d->dfs_disable_bgt) + d->disable_bgt = val; + else if (dent == d->dfs_emulate_bitflips) + d->emulate_bitflips = val; + else if (dent == d->dfs_emulate_io_failures) + d->emulate_io_failures = val; + else + count = -EINVAL; + +out: + ubi_put_device(ubi); + return count; +} + +/* File operations for all UBI debugfs files */ +static const struct file_operations dfs_fops = { + .read = dfs_file_read, + .write = dfs_file_write, + .open = simple_open, + .llseek = no_llseek, + .owner = THIS_MODULE, +}; + +/** + * ubi_debugfs_init_dev - initialize debugfs for an UBI device. + * @ubi: UBI device description object + * + * This function creates all debugfs files for UBI device @ubi. Returns zero in + * case of success and a negative error code in case of failure. + */ +int ubi_debugfs_init_dev(struct ubi_device *ubi) +{ + int err, n; + unsigned long ubi_num = ubi->ubi_num; + const char *fname; + struct dentry *dent; + struct ubi_debug_info *d = &ubi->dbg; + + if (!IS_ENABLED(CONFIG_DEBUG_FS)) + return 0; + + n = snprintf(d->dfs_dir_name, UBI_DFS_DIR_LEN + 1, UBI_DFS_DIR_NAME, + ubi->ubi_num); + if (n == UBI_DFS_DIR_LEN) { + /* The array size is too small */ + fname = UBI_DFS_DIR_NAME; + dent = ERR_PTR(-EINVAL); + goto out; + } + + fname = d->dfs_dir_name; + dent = debugfs_create_dir(fname, dfs_rootdir); + if (IS_ERR_OR_NULL(dent)) + goto out; + d->dfs_dir = dent; + + fname = "chk_gen"; + dent = debugfs_create_file(fname, S_IWUSR, d->dfs_dir, (void *)ubi_num, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_chk_gen = dent; + + fname = "chk_io"; + dent = debugfs_create_file(fname, S_IWUSR, d->dfs_dir, (void *)ubi_num, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_chk_io = dent; + + fname = "tst_disable_bgt"; + dent = debugfs_create_file(fname, S_IWUSR, d->dfs_dir, (void *)ubi_num, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_disable_bgt = dent; + + fname = "tst_emulate_bitflips"; + dent = debugfs_create_file(fname, S_IWUSR, d->dfs_dir, (void *)ubi_num, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_emulate_bitflips = dent; + + fname = "tst_emulate_io_failures"; + dent = debugfs_create_file(fname, S_IWUSR, d->dfs_dir, (void *)ubi_num, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_emulate_io_failures = dent; + + return 0; + +out_remove: + debugfs_remove_recursive(d->dfs_dir); +out: + err = dent ? PTR_ERR(dent) : -ENODEV; + ubi_err("cannot create \"%s\" debugfs file or directory, error %d\n", + fname, err); + return err; +} + +/** + * dbg_debug_exit_dev - free all debugfs files corresponding to device @ubi + * @ubi: UBI device description object + */ +void ubi_debugfs_exit_dev(struct ubi_device *ubi) +{ + if (IS_ENABLED(CONFIG_DEBUG_FS)) + debugfs_remove_recursive(ubi->dbg.dfs_dir); +} +#else +int ubi_debugfs_init(void) +{ + return 0; +} + +void ubi_debugfs_exit(void) +{ +} + +int ubi_debugfs_init_dev(struct ubi_device *ubi) +{ + return 0; +} + +void ubi_debugfs_exit_dev(struct ubi_device *ubi) +{ +} +#endif diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h index 222b2b8ae9..bfa9dfb42b 100644 --- a/drivers/mtd/ubi/debug.h +++ b/drivers/mtd/ubi/debug.h @@ -9,132 +9,112 @@ #ifndef __UBI_DEBUG_H__ #define __UBI_DEBUG_H__ -#ifdef CONFIG_MTD_UBI_DEBUG -#ifdef UBI_LINUX -#include -#endif - -#define ubi_assert(expr) BUG_ON(!(expr)) -#define dbg_err(fmt, ...) ubi_err(fmt, ##__VA_ARGS__) -#else -#define ubi_assert(expr) ({}) -#define dbg_err(fmt, ...) ({}) -#endif - -#ifdef CONFIG_MTD_UBI_DEBUG_DISABLE_BGT -#define DBG_DISABLE_BGT 1 -#else -#define DBG_DISABLE_BGT 0 -#endif - -#ifdef CONFIG_MTD_UBI_DEBUG_MSG -/* Generic debugging message */ -#define dbg_msg(fmt, ...) \ - printk(KERN_DEBUG "UBI DBG: %s: " fmt "\n", \ - __FUNCTION__, ##__VA_ARGS__) - -#define ubi_dbg_dump_stack() dump_stack() - -struct ubi_ec_hdr; -struct ubi_vid_hdr; -struct ubi_volume; -struct ubi_vtbl_record; -struct ubi_scan_volume; -struct ubi_scan_leb; -struct ubi_mkvol_req; - -void ubi_dbg_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr); -void ubi_dbg_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr); -void ubi_dbg_dump_vol_info(const struct ubi_volume *vol); -void ubi_dbg_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx); -void ubi_dbg_dump_sv(const struct ubi_scan_volume *sv); -void ubi_dbg_dump_seb(const struct ubi_scan_leb *seb, int type); -void ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req); - -#else - -#define dbg_msg(fmt, ...) ({}) -#define ubi_dbg_dump_stack() ({}) -#define ubi_dbg_dump_ec_hdr(ec_hdr) ({}) -#define ubi_dbg_dump_vid_hdr(vid_hdr) ({}) -#define ubi_dbg_dump_vol_info(vol) ({}) -#define ubi_dbg_dump_vtbl_record(r, idx) ({}) -#define ubi_dbg_dump_sv(sv) ({}) -#define ubi_dbg_dump_seb(seb, type) ({}) -#define ubi_dbg_dump_mkvol_req(req) ({}) - -#endif /* CONFIG_MTD_UBI_DEBUG_MSG */ - -#ifdef CONFIG_MTD_UBI_DEBUG_MSG_EBA -/* Messages from the eraseblock association unit */ -#define dbg_eba(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#else -#define dbg_eba(fmt, ...) ({}) -#endif - -#ifdef CONFIG_MTD_UBI_DEBUG_MSG_WL -/* Messages from the wear-leveling unit */ -#define dbg_wl(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#else -#define dbg_wl(fmt, ...) ({}) -#endif +void ubi_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len); +void ubi_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr); +void ubi_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr); -#ifdef CONFIG_MTD_UBI_DEBUG_MSG_IO -/* Messages from the input/output unit */ -#define dbg_io(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#else -#define dbg_io(fmt, ...) ({}) +#ifndef __UBOOT__ +#include #endif -#ifdef CONFIG_MTD_UBI_DEBUG_MSG_BLD +#define ubi_assert(expr) do { \ + if (unlikely(!(expr))) { \ + pr_crit("UBI assert failed in %s at %u (pid %d)\n", \ + __func__, __LINE__, current->pid); \ + dump_stack(); \ + } \ +} while (0) + +#define ubi_dbg_print_hex_dump(l, ps, pt, r, g, b, len, a) \ + print_hex_dump(l, ps, pt, r, g, b, len, a) + +#define ubi_dbg_msg(type, fmt, ...) \ + pr_debug("UBI DBG " type " (pid %d): " fmt "\n", current->pid, \ + ##__VA_ARGS__) + +/* General debugging messages */ +#define dbg_gen(fmt, ...) ubi_dbg_msg("gen", fmt, ##__VA_ARGS__) +/* Messages from the eraseblock association sub-system */ +#define dbg_eba(fmt, ...) ubi_dbg_msg("eba", fmt, ##__VA_ARGS__) +/* Messages from the wear-leveling sub-system */ +#define dbg_wl(fmt, ...) ubi_dbg_msg("wl", fmt, ##__VA_ARGS__) +/* Messages from the input/output sub-system */ +#define dbg_io(fmt, ...) ubi_dbg_msg("io", fmt, ##__VA_ARGS__) /* Initialization and build messages */ -#define dbg_bld(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#else -#define dbg_bld(fmt, ...) ({}) -#endif +#define dbg_bld(fmt, ...) ubi_dbg_msg("bld", fmt, ##__VA_ARGS__) + +void ubi_dump_vol_info(const struct ubi_volume *vol); +void ubi_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx); +void ubi_dump_av(const struct ubi_ainf_volume *av); +void ubi_dump_aeb(const struct ubi_ainf_peb *aeb, int type); +void ubi_dump_mkvol_req(const struct ubi_mkvol_req *req); +int ubi_self_check_all_ff(struct ubi_device *ubi, int pnum, int offset, + int len); +int ubi_debugfs_init(void); +void ubi_debugfs_exit(void); +int ubi_debugfs_init_dev(struct ubi_device *ubi); +void ubi_debugfs_exit_dev(struct ubi_device *ubi); + +/** + * ubi_dbg_is_bgt_disabled - if the background thread is disabled. + * @ubi: UBI device description object + * + * Returns non-zero if the UBI background thread is disabled for testing + * purposes. + */ +static inline int ubi_dbg_is_bgt_disabled(const struct ubi_device *ubi) +{ + return ubi->dbg.disable_bgt; +} -#ifdef CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS /** * ubi_dbg_is_bitflip - if it is time to emulate a bit-flip. + * @ubi: UBI device description object * * Returns non-zero if a bit-flip should be emulated, otherwise returns zero. */ -static inline int ubi_dbg_is_bitflip(void) +static inline int ubi_dbg_is_bitflip(const struct ubi_device *ubi) { - return !(random32() % 200); + if (ubi->dbg.emulate_bitflips) + return !(prandom_u32() % 200); + return 0; } -#else -#define ubi_dbg_is_bitflip() 0 -#endif -#ifdef CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES /** * ubi_dbg_is_write_failure - if it is time to emulate a write failure. + * @ubi: UBI device description object * * Returns non-zero if a write failure should be emulated, otherwise returns * zero. */ -static inline int ubi_dbg_is_write_failure(void) +static inline int ubi_dbg_is_write_failure(const struct ubi_device *ubi) { - return !(random32() % 500); + if (ubi->dbg.emulate_io_failures) + return !(prandom_u32() % 500); + return 0; } -#else -#define ubi_dbg_is_write_failure() 0 -#endif -#ifdef CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES /** * ubi_dbg_is_erase_failure - if its time to emulate an erase failure. + * @ubi: UBI device description object * * Returns non-zero if an erase failure should be emulated, otherwise returns * zero. */ -static inline int ubi_dbg_is_erase_failure(void) +static inline int ubi_dbg_is_erase_failure(const struct ubi_device *ubi) { - return !(random32() % 400); + if (ubi->dbg.emulate_io_failures) + return !(prandom_u32() % 400); + return 0; +} + +static inline int ubi_dbg_chk_io(const struct ubi_device *ubi) +{ + return ubi->dbg.chk_io; } -#else -#define ubi_dbg_is_erase_failure() 0 -#endif +static inline int ubi_dbg_chk_gen(const struct ubi_device *ubi) +{ + return ubi->dbg.chk_gen; +} #endif /* !__UBI_DEBUG_H__ */ diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index 7d27edaee2..fce0ff8bdf 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -7,20 +7,20 @@ */ /* - * The UBI Eraseblock Association (EBA) unit. + * The UBI Eraseblock Association (EBA) sub-system. * - * This unit is responsible for I/O to/from logical eraseblock. + * This sub-system is responsible for I/O to/from logical eraseblock. * * Although in this implementation the EBA table is fully kept and managed in * RAM, which assumes poor scalability, it might be (partially) maintained on * flash in future implementations. * - * The EBA unit implements per-logical eraseblock locking. Before accessing a - * logical eraseblock it is locked for reading or writing. The per-logical - * eraseblock locking is implemented by means of the lock tree. The lock tree - * is an RB-tree which refers all the currently locked logical eraseblocks. The - * lock tree elements are &struct ubi_ltree_entry objects. They are indexed by - * (@vol_id, @lnum) pairs. + * The EBA sub-system implements per-logical eraseblock locking. Before + * accessing a logical eraseblock it is locked for reading or writing. The + * per-logical eraseblock locking is implemented by means of the lock tree. The + * lock tree is an RB-tree which refers all the currently locked logical + * eraseblocks. The lock tree elements are &struct ubi_ltree_entry objects. + * They are indexed by (@vol_id, @lnum) pairs. * * EBA also maintains the global sequence counter which is incremented each * time a logical eraseblock is mapped to a physical eraseblock and it is @@ -29,13 +29,14 @@ * 64 bits is enough to never overflow. */ -#ifdef UBI_LINUX +#ifndef __UBOOT__ #include #include -#include +#else +#include #endif -#include +#include #include "ubi.h" /* Number of physical eraseblocks reserved for atomic LEB change operation */ @@ -49,7 +50,7 @@ * global sequence counter value. It also increases the global sequence * counter. */ -static unsigned long long next_sqnum(struct ubi_device *ubi) +unsigned long long ubi_next_sqnum(struct ubi_device *ubi) { unsigned long long sqnum; @@ -181,9 +182,7 @@ static struct ubi_ltree_entry *ltree_add_entry(struct ubi_device *ubi, le->users += 1; spin_unlock(&ubi->ltree_lock); - if (le_free) - kfree(le_free); - + kfree(le_free); return le; } @@ -215,22 +214,18 @@ static int leb_read_lock(struct ubi_device *ubi, int vol_id, int lnum) */ static void leb_read_unlock(struct ubi_device *ubi, int vol_id, int lnum) { - int _free = 0; struct ubi_ltree_entry *le; spin_lock(&ubi->ltree_lock); le = ltree_lookup(ubi, vol_id, lnum); le->users -= 1; ubi_assert(le->users >= 0); + up_read(&le->mutex); if (le->users == 0) { rb_erase(&le->rb, &ubi->ltree); - _free = 1; + kfree(le); } spin_unlock(&ubi->ltree_lock); - - up_read(&le->mutex); - if (_free) - kfree(le); } /** @@ -266,7 +261,6 @@ static int leb_write_lock(struct ubi_device *ubi, int vol_id, int lnum) */ static int leb_write_trylock(struct ubi_device *ubi, int vol_id, int lnum) { - int _free; struct ubi_ltree_entry *le; le = ltree_add_entry(ubi, vol_id, lnum); @@ -281,12 +275,9 @@ static int leb_write_trylock(struct ubi_device *ubi, int vol_id, int lnum) ubi_assert(le->users >= 0); if (le->users == 0) { rb_erase(&le->rb, &ubi->ltree); - _free = 1; - } else - _free = 0; - spin_unlock(&ubi->ltree_lock); - if (_free) kfree(le); + } + spin_unlock(&ubi->ltree_lock); return 1; } @@ -299,23 +290,18 @@ static int leb_write_trylock(struct ubi_device *ubi, int vol_id, int lnum) */ static void leb_write_unlock(struct ubi_device *ubi, int vol_id, int lnum) { - int _free; struct ubi_ltree_entry *le; spin_lock(&ubi->ltree_lock); le = ltree_lookup(ubi, vol_id, lnum); le->users -= 1; ubi_assert(le->users >= 0); + up_write(&le->mutex); if (le->users == 0) { rb_erase(&le->rb, &ubi->ltree); - _free = 1; - } else - _free = 0; - spin_unlock(&ubi->ltree_lock); - - up_write(&le->mutex); - if (_free) kfree(le); + } + spin_unlock(&ubi->ltree_lock); } /** @@ -347,8 +333,10 @@ int ubi_eba_unmap_leb(struct ubi_device *ubi, struct ubi_volume *vol, dbg_eba("erase LEB %d:%d, PEB %d", vol_id, lnum, pnum); + down_read(&ubi->fm_sem); vol->eba_tbl[lnum] = UBI_LEB_UNMAPPED; - err = ubi_wl_put_peb(ubi, pnum, 0); + up_read(&ubi->fm_sem); + err = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 0); out_unlock: leb_write_unlock(ubi, vol_id, lnum); @@ -425,9 +413,10 @@ retry: * may try to recover data. FIXME: but this is * not implemented. */ - if (err == UBI_IO_BAD_VID_HDR) { - ubi_warn("bad VID header at PEB %d, LEB" - "%d:%d", pnum, vol_id, lnum); + if (err == UBI_IO_BAD_HDR_EBADMSG || + err == UBI_IO_BAD_HDR) { + ubi_warn("corrupted VID header at PEB %d, LEB %d:%d", + pnum, vol_id, lnum); err = -EBADMSG; } else ubi_ro_mode(ubi); @@ -508,16 +497,12 @@ static int recover_peb(struct ubi_device *ubi, int pnum, int vol_id, int lnum, struct ubi_vid_hdr *vid_hdr; vid_hdr = ubi_zalloc_vid_hdr(ubi, GFP_NOFS); - if (!vid_hdr) { + if (!vid_hdr) return -ENOMEM; - } - - mutex_lock(&ubi->buf_mutex); retry: - new_pnum = ubi_wl_get_peb(ubi, UBI_UNKNOWN); + new_pnum = ubi_wl_get_peb(ubi); if (new_pnum < 0) { - mutex_unlock(&ubi->buf_mutex); ubi_free_vid_hdr(ubi, vid_hdr); return new_pnum; } @@ -531,39 +516,45 @@ retry: goto out_put; } - vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi)); + vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); err = ubi_io_write_vid_hdr(ubi, new_pnum, vid_hdr); if (err) goto write_error; data_size = offset + len; - memset(ubi->peb_buf1 + offset, 0xFF, len); + mutex_lock(&ubi->buf_mutex); + memset(ubi->peb_buf + offset, 0xFF, len); /* Read everything before the area where the write failure happened */ if (offset > 0) { - err = ubi_io_read_data(ubi, ubi->peb_buf1, pnum, 0, offset); + err = ubi_io_read_data(ubi, ubi->peb_buf, pnum, 0, offset); if (err && err != UBI_IO_BITFLIPS) - goto out_put; + goto out_unlock; } - memcpy(ubi->peb_buf1 + offset, buf, len); + memcpy(ubi->peb_buf + offset, buf, len); - err = ubi_io_write_data(ubi, ubi->peb_buf1, new_pnum, 0, data_size); - if (err) + err = ubi_io_write_data(ubi, ubi->peb_buf, new_pnum, 0, data_size); + if (err) { + mutex_unlock(&ubi->buf_mutex); goto write_error; + } mutex_unlock(&ubi->buf_mutex); ubi_free_vid_hdr(ubi, vid_hdr); + down_read(&ubi->fm_sem); vol->eba_tbl[lnum] = new_pnum; - ubi_wl_put_peb(ubi, pnum, 1); + up_read(&ubi->fm_sem); + ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1); ubi_msg("data was successfully recovered"); return 0; -out_put: +out_unlock: mutex_unlock(&ubi->buf_mutex); - ubi_wl_put_peb(ubi, new_pnum, 1); +out_put: + ubi_wl_put_peb(ubi, vol_id, lnum, new_pnum, 1); ubi_free_vid_hdr(ubi, vid_hdr); return err; @@ -573,9 +564,8 @@ write_error: * get another one. */ ubi_warn("failed to write to PEB %d", new_pnum); - ubi_wl_put_peb(ubi, new_pnum, 1); + ubi_wl_put_peb(ubi, vol_id, lnum, new_pnum, 1); if (++tries > UBI_IO_RETRIES) { - mutex_unlock(&ubi->buf_mutex); ubi_free_vid_hdr(ubi, vid_hdr); return err; } @@ -591,7 +581,6 @@ write_error: * @buf: the data to write * @offset: offset within the logical eraseblock where to write * @len: how many bytes to write - * @dtype: data type * * This function writes data to logical eraseblock @lnum of a dynamic volume * @vol. Returns zero in case of success and a negative error code in case @@ -599,7 +588,7 @@ write_error: * written to the flash media, but may be some garbage. */ int ubi_eba_write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, - const void *buf, int offset, int len, int dtype) + const void *buf, int offset, int len) { int err, pnum, tries = 0, vol_id = vol->vol_id; struct ubi_vid_hdr *vid_hdr; @@ -640,14 +629,14 @@ int ubi_eba_write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, } vid_hdr->vol_type = UBI_VID_DYNAMIC; - vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi)); + vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); vid_hdr->vol_id = cpu_to_be32(vol_id); vid_hdr->lnum = cpu_to_be32(lnum); vid_hdr->compat = ubi_get_compat(ubi, vol_id); vid_hdr->data_pad = cpu_to_be32(vol->data_pad); retry: - pnum = ubi_wl_get_peb(ubi, dtype); + pnum = ubi_wl_get_peb(ubi); if (pnum < 0) { ubi_free_vid_hdr(ubi, vid_hdr); leb_write_unlock(ubi, vol_id, lnum); @@ -667,14 +656,15 @@ retry: if (len) { err = ubi_io_write_data(ubi, buf, pnum, offset, len); if (err) { - ubi_warn("failed to write %d bytes at offset %d of " - "LEB %d:%d, PEB %d", len, offset, vol_id, - lnum, pnum); + ubi_warn("failed to write %d bytes at offset %d of LEB %d:%d, PEB %d", + len, offset, vol_id, lnum, pnum); goto write_error; } } + down_read(&ubi->fm_sem); vol->eba_tbl[lnum] = pnum; + up_read(&ubi->fm_sem); leb_write_unlock(ubi, vol_id, lnum); ubi_free_vid_hdr(ubi, vid_hdr); @@ -693,7 +683,7 @@ write_error: * eraseblock, so just put it and request a new one. We assume that if * this physical eraseblock went bad, the erase code will handle that. */ - err = ubi_wl_put_peb(ubi, pnum, 1); + err = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1); if (err || ++tries > UBI_IO_RETRIES) { ubi_ro_mode(ubi); leb_write_unlock(ubi, vol_id, lnum); @@ -701,7 +691,7 @@ write_error: return err; } - vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi)); + vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); ubi_msg("try another PEB"); goto retry; } @@ -713,7 +703,6 @@ write_error: * @lnum: logical eraseblock number * @buf: data to write * @len: how many bytes to write - * @dtype: data type * @used_ebs: how many logical eraseblocks will this volume contain * * This function writes data to logical eraseblock @lnum of static volume @@ -725,13 +714,12 @@ write_error: * to the real data size, although the @buf buffer has to contain the * alignment. In all other cases, @len has to be aligned. * - * It is prohibited to write more then once to logical eraseblocks of static + * It is prohibited to write more than once to logical eraseblocks of static * volumes. This function returns zero in case of success and a negative error * code in case of failure. */ int ubi_eba_write_leb_st(struct ubi_device *ubi, struct ubi_volume *vol, - int lnum, const void *buf, int len, int dtype, - int used_ebs) + int lnum, const void *buf, int len, int used_ebs) { int err, pnum, tries = 0, data_size = len, vol_id = vol->vol_id; struct ubi_vid_hdr *vid_hdr; @@ -756,7 +744,7 @@ int ubi_eba_write_leb_st(struct ubi_device *ubi, struct ubi_volume *vol, return err; } - vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi)); + vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); vid_hdr->vol_id = cpu_to_be32(vol_id); vid_hdr->lnum = cpu_to_be32(lnum); vid_hdr->compat = ubi_get_compat(ubi, vol_id); @@ -769,7 +757,7 @@ int ubi_eba_write_leb_st(struct ubi_device *ubi, struct ubi_volume *vol, vid_hdr->data_crc = cpu_to_be32(crc); retry: - pnum = ubi_wl_get_peb(ubi, dtype); + pnum = ubi_wl_get_peb(ubi); if (pnum < 0) { ubi_free_vid_hdr(ubi, vid_hdr); leb_write_unlock(ubi, vol_id, lnum); @@ -794,7 +782,9 @@ retry: } ubi_assert(vol->eba_tbl[lnum] < 0); + down_read(&ubi->fm_sem); vol->eba_tbl[lnum] = pnum; + up_read(&ubi->fm_sem); leb_write_unlock(ubi, vol_id, lnum); ubi_free_vid_hdr(ubi, vid_hdr); @@ -813,7 +803,7 @@ write_error: return err; } - err = ubi_wl_put_peb(ubi, pnum, 1); + err = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1); if (err || ++tries > UBI_IO_RETRIES) { ubi_ro_mode(ubi); leb_write_unlock(ubi, vol_id, lnum); @@ -821,7 +811,7 @@ write_error: return err; } - vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi)); + vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); ubi_msg("try another PEB"); goto retry; } @@ -833,7 +823,6 @@ write_error: * @lnum: logical eraseblock number * @buf: data to write * @len: how many bytes to write - * @dtype: data type * * This function changes the contents of a logical eraseblock atomically. @buf * has to contain new logical eraseblock data, and @len - the length of the @@ -845,7 +834,7 @@ write_error: * LEB change may be done at a time. This is ensured by @ubi->alc_mutex. */ int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol, - int lnum, const void *buf, int len, int dtype) + int lnum, const void *buf, int len) { int err, pnum, tries = 0, vol_id = vol->vol_id; struct ubi_vid_hdr *vid_hdr; @@ -862,7 +851,7 @@ int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol, err = ubi_eba_unmap_leb(ubi, vol, lnum); if (err) return err; - return ubi_eba_write_leb(ubi, vol, lnum, NULL, 0, 0, dtype); + return ubi_eba_write_leb(ubi, vol, lnum, NULL, 0, 0); } vid_hdr = ubi_zalloc_vid_hdr(ubi, GFP_NOFS); @@ -874,7 +863,7 @@ int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol, if (err) goto out_mutex; - vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi)); + vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); vid_hdr->vol_id = cpu_to_be32(vol_id); vid_hdr->lnum = cpu_to_be32(lnum); vid_hdr->compat = ubi_get_compat(ubi, vol_id); @@ -887,7 +876,7 @@ int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol, vid_hdr->data_crc = cpu_to_be32(crc); retry: - pnum = ubi_wl_get_peb(ubi, dtype); + pnum = ubi_wl_get_peb(ubi); if (pnum < 0) { err = pnum; goto out_leb_unlock; @@ -911,12 +900,14 @@ retry: } if (vol->eba_tbl[lnum] >= 0) { - err = ubi_wl_put_peb(ubi, vol->eba_tbl[lnum], 1); + err = ubi_wl_put_peb(ubi, vol_id, lnum, vol->eba_tbl[lnum], 0); if (err) goto out_leb_unlock; } + down_read(&ubi->fm_sem); vol->eba_tbl[lnum] = pnum; + up_read(&ubi->fm_sem); out_leb_unlock: leb_write_unlock(ubi, vol_id, lnum); @@ -936,17 +927,44 @@ write_error: goto out_leb_unlock; } - err = ubi_wl_put_peb(ubi, pnum, 1); + err = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1); if (err || ++tries > UBI_IO_RETRIES) { ubi_ro_mode(ubi); goto out_leb_unlock; } - vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi)); + vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); ubi_msg("try another PEB"); goto retry; } +/** + * is_error_sane - check whether a read error is sane. + * @err: code of the error happened during reading + * + * This is a helper function for 'ubi_eba_copy_leb()' which is called when we + * cannot read data from the target PEB (an error @err happened). If the error + * code is sane, then we treat this error as non-fatal. Otherwise the error is + * fatal and UBI will be switched to R/O mode later. + * + * The idea is that we try not to switch to R/O mode if the read error is + * something which suggests there was a real read problem. E.g., %-EIO. Or a + * memory allocation failed (-%ENOMEM). Otherwise, it is safer to switch to R/O + * mode, simply because we do not know what happened at the MTD level, and we + * cannot handle this. E.g., the underlying driver may have become crazy, and + * it is safer to switch to R/O mode to preserve the data. + * + * And bear in mind, this is about reading from the target PEB, i.e. the PEB + * which we have just written. + */ +static int is_error_sane(int err) +{ + if (err == -EIO || err == -ENOMEM || err == UBI_IO_BAD_HDR || + err == UBI_IO_BAD_HDR_EBADMSG || err == -ETIMEDOUT) + return 0; + return 1; +} + /** * ubi_eba_copy_leb - copy logical eraseblock. * @ubi: UBI device description object @@ -957,10 +975,9 @@ write_error: * This function copies logical eraseblock from physical eraseblock @from to * physical eraseblock @to. The @vid_hdr buffer may be changed by this * function. Returns: - * o %0 in case of success; - * o %1 if the operation was canceled and should be tried later (e.g., - * because a bit-flip was detected at the target PEB); - * o %2 if the volume is being deleted and this LEB should not be moved. + * o %0 in case of success; + * o %MOVE_CANCEL_RACE, %MOVE_TARGET_WR_ERR, %MOVE_TARGET_BITFLIPS, etc; + * o a negative error code in case of failure. */ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, struct ubi_vid_hdr *vid_hdr) @@ -972,7 +989,7 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, vol_id = be32_to_cpu(vid_hdr->vol_id); lnum = be32_to_cpu(vid_hdr->lnum); - dbg_eba("copy LEB %d:%d, PEB %d to PEB %d", vol_id, lnum, from, to); + dbg_wl("copy LEB %d:%d, PEB %d to PEB %d", vol_id, lnum, from, to); if (vid_hdr->vol_type == UBI_VID_STATIC) { data_size = be32_to_cpu(vid_hdr->data_size); @@ -986,17 +1003,16 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, /* * Note, we may race with volume deletion, which means that the volume * this logical eraseblock belongs to might be being deleted. Since the - * volume deletion unmaps all the volume's logical eraseblocks, it will + * volume deletion un-maps all the volume's logical eraseblocks, it will * be locked in 'ubi_wl_put_peb()' and wait for the WL worker to finish. */ vol = ubi->volumes[idx]; + spin_unlock(&ubi->volumes_lock); if (!vol) { /* No need to do further work, cancel */ - dbg_eba("volume %d is being removed, cancel", vol_id); - spin_unlock(&ubi->volumes_lock); - return 2; + dbg_wl("volume %d is being removed, cancel", vol_id); + return MOVE_CANCEL_RACE; } - spin_unlock(&ubi->volumes_lock); /* * We do not want anybody to write to this logical eraseblock while we @@ -1008,12 +1024,15 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, * (@from). This task locks the LEB and goes sleep in the * 'ubi_wl_put_peb()' function on the @ubi->move_mutex. In turn, we are * holding @ubi->move_mutex and go sleep on the LEB lock. So, if the - * LEB is already locked, we just do not move it and return %1. + * LEB is already locked, we just do not move it and return + * %MOVE_RETRY. Note, we do not return %MOVE_CANCEL_RACE here because + * we do not know the reasons of the contention - it may be just a + * normal I/O on this LEB, so we want to re-try. */ err = leb_write_trylock(ubi, vol_id, lnum); if (err) { - dbg_eba("contention on LEB %d:%d, cancel", vol_id, lnum); - return err; + dbg_wl("contention on LEB %d:%d, cancel", vol_id, lnum); + return MOVE_RETRY; } /* @@ -1022,30 +1041,30 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, * cancel it. */ if (vol->eba_tbl[lnum] != from) { - dbg_eba("LEB %d:%d is no longer mapped to PEB %d, mapped to " - "PEB %d, cancel", vol_id, lnum, from, - vol->eba_tbl[lnum]); - err = 1; + dbg_wl("LEB %d:%d is no longer mapped to PEB %d, mapped to PEB %d, cancel", + vol_id, lnum, from, vol->eba_tbl[lnum]); + err = MOVE_CANCEL_RACE; goto out_unlock_leb; } /* - * OK, now the LEB is locked and we can safely start moving iy. Since - * this function utilizes thie @ubi->peb1_buf buffer which is shared - * with some other functions, so lock the buffer by taking the + * OK, now the LEB is locked and we can safely start moving it. Since + * this function utilizes the @ubi->peb_buf buffer which is shared + * with some other functions - we lock the buffer by taking the * @ubi->buf_mutex. */ mutex_lock(&ubi->buf_mutex); - dbg_eba("read %d bytes of data", aldata_size); - err = ubi_io_read_data(ubi, ubi->peb_buf1, from, 0, aldata_size); + dbg_wl("read %d bytes of data", aldata_size); + err = ubi_io_read_data(ubi, ubi->peb_buf, from, 0, aldata_size); if (err && err != UBI_IO_BITFLIPS) { ubi_warn("error %d while reading data from PEB %d", err, from); + err = MOVE_SOURCE_RD_ERR; goto out_unlock_buf; } /* - * Now we have got to calculate how much data we have to to copy. In + * Now we have got to calculate how much data we have to copy. In * case of a static volume it is fairly easy - the VID header contains * the data size. In case of a dynamic volume it is more difficult - we * have to read the contents, cut 0xFF bytes from the end and copy only @@ -1056,14 +1075,14 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, */ if (vid_hdr->vol_type == UBI_VID_DYNAMIC) aldata_size = data_size = - ubi_calc_data_len(ubi, ubi->peb_buf1, data_size); + ubi_calc_data_len(ubi, ubi->peb_buf, data_size); cond_resched(); - crc = crc32(UBI_CRC32_INIT, ubi->peb_buf1, data_size); + crc = crc32(UBI_CRC32_INIT, ubi->peb_buf, data_size); cond_resched(); /* - * It may turn out to me that the whole @from physical eraseblock + * It may turn out to be that the whole @from physical eraseblock * contains only 0xFF bytes. Then we have to only write the VID header * and do not write any data. This also means we should not set * @vid_hdr->copy_flag, @vid_hdr->data_size, and @vid_hdr->data_crc. @@ -1073,28 +1092,37 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, vid_hdr->data_size = cpu_to_be32(data_size); vid_hdr->data_crc = cpu_to_be32(crc); } - vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi)); + vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); err = ubi_io_write_vid_hdr(ubi, to, vid_hdr); - if (err) + if (err) { + if (err == -EIO) + err = MOVE_TARGET_WR_ERR; goto out_unlock_buf; + } cond_resched(); /* Read the VID header back and check if it was written correctly */ err = ubi_io_read_vid_hdr(ubi, to, vid_hdr, 1); if (err) { - if (err != UBI_IO_BITFLIPS) - ubi_warn("cannot read VID header back from PEB %d", to); - else - err = 1; + if (err != UBI_IO_BITFLIPS) { + ubi_warn("error %d while reading VID header back from PEB %d", + err, to); + if (is_error_sane(err)) + err = MOVE_TARGET_RD_ERR; + } else + err = MOVE_TARGET_BITFLIPS; goto out_unlock_buf; } if (data_size > 0) { - err = ubi_io_write_data(ubi, ubi->peb_buf1, to, 0, aldata_size); - if (err) + err = ubi_io_write_data(ubi, ubi->peb_buf, to, 0, aldata_size); + if (err) { + if (err == -EIO) + err = MOVE_TARGET_WR_ERR; goto out_unlock_buf; + } cond_resched(); @@ -1102,28 +1130,33 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, * We've written the data and are going to read it back to make * sure it was written correctly. */ - - err = ubi_io_read_data(ubi, ubi->peb_buf2, to, 0, aldata_size); + memset(ubi->peb_buf, 0xFF, aldata_size); + err = ubi_io_read_data(ubi, ubi->peb_buf, to, 0, aldata_size); if (err) { - if (err != UBI_IO_BITFLIPS) - ubi_warn("cannot read data back from PEB %d", - to); - else - err = 1; + if (err != UBI_IO_BITFLIPS) { + ubi_warn("error %d while reading data back from PEB %d", + err, to); + if (is_error_sane(err)) + err = MOVE_TARGET_RD_ERR; + } else + err = MOVE_TARGET_BITFLIPS; goto out_unlock_buf; } cond_resched(); - if (memcmp(ubi->peb_buf1, ubi->peb_buf2, aldata_size)) { - ubi_warn("read data back from PEB %d - it is different", + if (crc != crc32(UBI_CRC32_INIT, ubi->peb_buf, data_size)) { + ubi_warn("read data back from PEB %d and it is different", to); + err = -EINVAL; goto out_unlock_buf; } } ubi_assert(vol->eba_tbl[lnum] == from); + down_read(&ubi->fm_sem); vol->eba_tbl[lnum] = to; + up_read(&ubi->fm_sem); out_unlock_buf: mutex_unlock(&ubi->buf_mutex); @@ -1133,28 +1166,165 @@ out_unlock_leb: } /** - * ubi_eba_init_scan - initialize the EBA unit using scanning information. + * print_rsvd_warning - warn about not having enough reserved PEBs. * @ubi: UBI device description object - * @si: scanning information + * + * This is a helper function for 'ubi_eba_init()' which is called when UBI + * cannot reserve enough PEBs for bad block handling. This function makes a + * decision whether we have to print a warning or not. The algorithm is as + * follows: + * o if this is a new UBI image, then just print the warning + * o if this is an UBI image which has already been used for some time, print + * a warning only if we can reserve less than 10% of the expected amount of + * the reserved PEB. + * + * The idea is that when UBI is used, PEBs become bad, and the reserved pool + * of PEBs becomes smaller, which is normal and we do not want to scare users + * with a warning every time they attach the MTD device. This was an issue + * reported by real users. + */ +static void print_rsvd_warning(struct ubi_device *ubi, + struct ubi_attach_info *ai) +{ + /* + * The 1 << 18 (256KiB) number is picked randomly, just a reasonably + * large number to distinguish between newly flashed and used images. + */ + if (ai->max_sqnum > (1 << 18)) { + int min = ubi->beb_rsvd_level / 10; + + if (!min) + min = 1; + if (ubi->beb_rsvd_pebs > min) + return; + } + + ubi_warn("cannot reserve enough PEBs for bad PEB handling, reserved %d, need %d", + ubi->beb_rsvd_pebs, ubi->beb_rsvd_level); + if (ubi->corr_peb_count) + ubi_warn("%d PEBs are corrupted and not used", + ubi->corr_peb_count); +} + +/** + * self_check_eba - run a self check on the EBA table constructed by fastmap. + * @ubi: UBI device description object + * @ai_fastmap: UBI attach info object created by fastmap + * @ai_scan: UBI attach info object created by scanning + * + * Returns < 0 in case of an internal error, 0 otherwise. + * If a bad EBA table entry was found it will be printed out and + * ubi_assert() triggers. + */ +int self_check_eba(struct ubi_device *ubi, struct ubi_attach_info *ai_fastmap, + struct ubi_attach_info *ai_scan) +{ + int i, j, num_volumes, ret = 0; + int **scan_eba, **fm_eba; + struct ubi_ainf_volume *av; + struct ubi_volume *vol; + struct ubi_ainf_peb *aeb; + struct rb_node *rb; + + num_volumes = ubi->vtbl_slots + UBI_INT_VOL_COUNT; + + scan_eba = kmalloc(sizeof(*scan_eba) * num_volumes, GFP_KERNEL); + if (!scan_eba) + return -ENOMEM; + + fm_eba = kmalloc(sizeof(*fm_eba) * num_volumes, GFP_KERNEL); + if (!fm_eba) { + kfree(scan_eba); + return -ENOMEM; + } + + for (i = 0; i < num_volumes; i++) { + vol = ubi->volumes[i]; + if (!vol) + continue; + + scan_eba[i] = kmalloc(vol->reserved_pebs * sizeof(**scan_eba), + GFP_KERNEL); + if (!scan_eba[i]) { + ret = -ENOMEM; + goto out_free; + } + + fm_eba[i] = kmalloc(vol->reserved_pebs * sizeof(**fm_eba), + GFP_KERNEL); + if (!fm_eba[i]) { + ret = -ENOMEM; + goto out_free; + } + + for (j = 0; j < vol->reserved_pebs; j++) + scan_eba[i][j] = fm_eba[i][j] = UBI_LEB_UNMAPPED; + + av = ubi_find_av(ai_scan, idx2vol_id(ubi, i)); + if (!av) + continue; + + ubi_rb_for_each_entry(rb, aeb, &av->root, u.rb) + scan_eba[i][aeb->lnum] = aeb->pnum; + + av = ubi_find_av(ai_fastmap, idx2vol_id(ubi, i)); + if (!av) + continue; + + ubi_rb_for_each_entry(rb, aeb, &av->root, u.rb) + fm_eba[i][aeb->lnum] = aeb->pnum; + + for (j = 0; j < vol->reserved_pebs; j++) { + if (scan_eba[i][j] != fm_eba[i][j]) { + if (scan_eba[i][j] == UBI_LEB_UNMAPPED || + fm_eba[i][j] == UBI_LEB_UNMAPPED) + continue; + + ubi_err("LEB:%i:%i is PEB:%i instead of %i!", + vol->vol_id, i, fm_eba[i][j], + scan_eba[i][j]); + ubi_assert(0); + } + } + } + +out_free: + for (i = 0; i < num_volumes; i++) { + if (!ubi->volumes[i]) + continue; + + kfree(scan_eba[i]); + kfree(fm_eba[i]); + } + + kfree(scan_eba); + kfree(fm_eba); + return ret; +} + +/** + * ubi_eba_init - initialize the EBA sub-system using attaching information. + * @ubi: UBI device description object + * @ai: attaching information * * This function returns zero in case of success and a negative error code in * case of failure. */ -int ubi_eba_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) +int ubi_eba_init(struct ubi_device *ubi, struct ubi_attach_info *ai) { int i, j, err, num_volumes; - struct ubi_scan_volume *sv; + struct ubi_ainf_volume *av; struct ubi_volume *vol; - struct ubi_scan_leb *seb; + struct ubi_ainf_peb *aeb; struct rb_node *rb; - dbg_eba("initialize EBA unit"); + dbg_eba("initialize EBA sub-system"); spin_lock_init(&ubi->ltree_lock); mutex_init(&ubi->alc_mutex); ubi->ltree = RB_ROOT; - ubi->global_sqnum = si->max_sqnum + 1; + ubi->global_sqnum = ai->max_sqnum + 1; num_volumes = ubi->vtbl_slots + UBI_INT_VOL_COUNT; for (i = 0; i < num_volumes; i++) { @@ -1174,24 +1344,27 @@ int ubi_eba_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) for (j = 0; j < vol->reserved_pebs; j++) vol->eba_tbl[j] = UBI_LEB_UNMAPPED; - sv = ubi_scan_find_sv(si, idx2vol_id(ubi, i)); - if (!sv) + av = ubi_find_av(ai, idx2vol_id(ubi, i)); + if (!av) continue; - ubi_rb_for_each_entry(rb, seb, &sv->root, u.rb) { - if (seb->lnum >= vol->reserved_pebs) + ubi_rb_for_each_entry(rb, aeb, &av->root, u.rb) { + if (aeb->lnum >= vol->reserved_pebs) /* * This may happen in case of an unclean reboot * during re-size. */ - ubi_scan_move_to_list(sv, seb, &si->erase); - vol->eba_tbl[seb->lnum] = seb->pnum; + ubi_move_aeb_to_list(av, aeb, &ai->erase); + vol->eba_tbl[aeb->lnum] = aeb->pnum; } } if (ubi->avail_pebs < EBA_RESERVED_PEBS) { ubi_err("no enough physical eraseblocks (%d, need %d)", ubi->avail_pebs, EBA_RESERVED_PEBS); + if (ubi->corr_peb_count) + ubi_err("%d PEBs are corrupted and not used", + ubi->corr_peb_count); err = -ENOSPC; goto out_free; } @@ -1204,9 +1377,7 @@ int ubi_eba_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) if (ubi->avail_pebs < ubi->beb_rsvd_level) { /* No enough free physical eraseblocks */ ubi->beb_rsvd_pebs = ubi->avail_pebs; - ubi_warn("cannot reserve enough PEBs for bad PEB " - "handling, reserved %d, need %d", - ubi->beb_rsvd_pebs, ubi->beb_rsvd_level); + print_rsvd_warning(ubi, ai); } else ubi->beb_rsvd_pebs = ubi->beb_rsvd_level; @@ -1214,7 +1385,7 @@ int ubi_eba_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) ubi->rsvd_pebs += ubi->beb_rsvd_pebs; } - dbg_eba("EBA unit is initialized"); + dbg_eba("EBA sub-system is initialized"); return 0; out_free: @@ -1222,23 +1393,7 @@ out_free: if (!ubi->volumes[i]) continue; kfree(ubi->volumes[i]->eba_tbl); + ubi->volumes[i]->eba_tbl = NULL; } return err; } - -/** - * ubi_eba_close - close EBA unit. - * @ubi: UBI device description object - */ -void ubi_eba_close(const struct ubi_device *ubi) -{ - int i, num_volumes = ubi->vtbl_slots + UBI_INT_VOL_COUNT; - - dbg_eba("close EBA unit"); - - for (i = 0; i < num_volumes; i++) { - if (!ubi->volumes[i]) - continue; - kfree(ubi->volumes[i]->eba_tbl); - } -} diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c new file mode 100644 index 0000000000..a2166e431c --- /dev/null +++ b/drivers/mtd/ubi/fastmap.c @@ -0,0 +1,1583 @@ +/* + * Copyright (c) 2012 Linutronix GmbH + * Author: Richard Weinberger + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __UBOOT__ +#include +#else +#include +#include +#include +#endif + +#include +#include +#include "ubi.h" + +/** + * ubi_calc_fm_size - calculates the fastmap size in bytes for an UBI device. + * @ubi: UBI device description object + */ +size_t ubi_calc_fm_size(struct ubi_device *ubi) +{ + size_t size; + + size = sizeof(struct ubi_fm_hdr) + \ + sizeof(struct ubi_fm_scan_pool) + \ + sizeof(struct ubi_fm_scan_pool) + \ + (ubi->peb_count * sizeof(struct ubi_fm_ec)) + \ + (sizeof(struct ubi_fm_eba) + \ + (ubi->peb_count * sizeof(__be32))) + \ + sizeof(struct ubi_fm_volhdr) * UBI_MAX_VOLUMES; + return roundup(size, ubi->leb_size); +} + + +/** + * new_fm_vhdr - allocate a new volume header for fastmap usage. + * @ubi: UBI device description object + * @vol_id: the VID of the new header + * + * Returns a new struct ubi_vid_hdr on success. + * NULL indicates out of memory. + */ +static struct ubi_vid_hdr *new_fm_vhdr(struct ubi_device *ubi, int vol_id) +{ + struct ubi_vid_hdr *new; + + new = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); + if (!new) + goto out; + + new->vol_type = UBI_VID_DYNAMIC; + new->vol_id = cpu_to_be32(vol_id); + + /* UBI implementations without fastmap support have to delete the + * fastmap. + */ + new->compat = UBI_COMPAT_DELETE; + +out: + return new; +} + +/** + * add_aeb - create and add a attach erase block to a given list. + * @ai: UBI attach info object + * @list: the target list + * @pnum: PEB number of the new attach erase block + * @ec: erease counter of the new LEB + * @scrub: scrub this PEB after attaching + * + * Returns 0 on success, < 0 indicates an internal error. + */ +static int add_aeb(struct ubi_attach_info *ai, struct list_head *list, + int pnum, int ec, int scrub) +{ + struct ubi_ainf_peb *aeb; + + aeb = kmem_cache_alloc(ai->aeb_slab_cache, GFP_KERNEL); + if (!aeb) + return -ENOMEM; + + aeb->pnum = pnum; + aeb->ec = ec; + aeb->lnum = -1; + aeb->scrub = scrub; + aeb->copy_flag = aeb->sqnum = 0; + + ai->ec_sum += aeb->ec; + ai->ec_count++; + + if (ai->max_ec < aeb->ec) + ai->max_ec = aeb->ec; + + if (ai->min_ec > aeb->ec) + ai->min_ec = aeb->ec; + + list_add_tail(&aeb->u.list, list); + + return 0; +} + +/** + * add_vol - create and add a new volume to ubi_attach_info. + * @ai: ubi_attach_info object + * @vol_id: VID of the new volume + * @used_ebs: number of used EBS + * @data_pad: data padding value of the new volume + * @vol_type: volume type + * @last_eb_bytes: number of bytes in the last LEB + * + * Returns the new struct ubi_ainf_volume on success. + * NULL indicates an error. + */ +static struct ubi_ainf_volume *add_vol(struct ubi_attach_info *ai, int vol_id, + int used_ebs, int data_pad, u8 vol_type, + int last_eb_bytes) +{ + struct ubi_ainf_volume *av; + struct rb_node **p = &ai->volumes.rb_node, *parent = NULL; + + while (*p) { + parent = *p; + av = rb_entry(parent, struct ubi_ainf_volume, rb); + + if (vol_id > av->vol_id) + p = &(*p)->rb_left; + else if (vol_id > av->vol_id) + p = &(*p)->rb_right; + } + + av = kmalloc(sizeof(struct ubi_ainf_volume), GFP_KERNEL); + if (!av) + goto out; + + av->highest_lnum = av->leb_count = 0; + av->vol_id = vol_id; + av->used_ebs = used_ebs; + av->data_pad = data_pad; + av->last_data_size = last_eb_bytes; + av->compat = 0; + av->vol_type = vol_type; + av->root = RB_ROOT; + + dbg_bld("found volume (ID %i)", vol_id); + + rb_link_node(&av->rb, parent, p); + rb_insert_color(&av->rb, &ai->volumes); + +out: + return av; +} + +/** + * assign_aeb_to_av - assigns a SEB to a given ainf_volume and removes it + * from it's original list. + * @ai: ubi_attach_info object + * @aeb: the to be assigned SEB + * @av: target scan volume + */ +static void assign_aeb_to_av(struct ubi_attach_info *ai, + struct ubi_ainf_peb *aeb, + struct ubi_ainf_volume *av) +{ + struct ubi_ainf_peb *tmp_aeb; + struct rb_node **p = &ai->volumes.rb_node, *parent = NULL; + + p = &av->root.rb_node; + while (*p) { + parent = *p; + + tmp_aeb = rb_entry(parent, struct ubi_ainf_peb, u.rb); + if (aeb->lnum != tmp_aeb->lnum) { + if (aeb->lnum < tmp_aeb->lnum) + p = &(*p)->rb_left; + else + p = &(*p)->rb_right; + + continue; + } else + break; + } + + list_del(&aeb->u.list); + av->leb_count++; + + rb_link_node(&aeb->u.rb, parent, p); + rb_insert_color(&aeb->u.rb, &av->root); +} + +/** + * update_vol - inserts or updates a LEB which was found a pool. + * @ubi: the UBI device object + * @ai: attach info object + * @av: the volume this LEB belongs to + * @new_vh: the volume header derived from new_aeb + * @new_aeb: the AEB to be examined + * + * Returns 0 on success, < 0 indicates an internal error. + */ +static int update_vol(struct ubi_device *ubi, struct ubi_attach_info *ai, + struct ubi_ainf_volume *av, struct ubi_vid_hdr *new_vh, + struct ubi_ainf_peb *new_aeb) +{ + struct rb_node **p = &av->root.rb_node, *parent = NULL; + struct ubi_ainf_peb *aeb, *victim; + int cmp_res; + + while (*p) { + parent = *p; + aeb = rb_entry(parent, struct ubi_ainf_peb, u.rb); + + if (be32_to_cpu(new_vh->lnum) != aeb->lnum) { + if (be32_to_cpu(new_vh->lnum) < aeb->lnum) + p = &(*p)->rb_left; + else + p = &(*p)->rb_right; + + continue; + } + + /* This case can happen if the fastmap gets written + * because of a volume change (creation, deletion, ..). + * Then a PEB can be within the persistent EBA and the pool. + */ + if (aeb->pnum == new_aeb->pnum) { + ubi_assert(aeb->lnum == new_aeb->lnum); + kmem_cache_free(ai->aeb_slab_cache, new_aeb); + + return 0; + } + + cmp_res = ubi_compare_lebs(ubi, aeb, new_aeb->pnum, new_vh); + if (cmp_res < 0) + return cmp_res; + + /* new_aeb is newer */ + if (cmp_res & 1) { + victim = kmem_cache_alloc(ai->aeb_slab_cache, + GFP_KERNEL); + if (!victim) + return -ENOMEM; + + victim->ec = aeb->ec; + victim->pnum = aeb->pnum; + list_add_tail(&victim->u.list, &ai->erase); + + if (av->highest_lnum == be32_to_cpu(new_vh->lnum)) + av->last_data_size = \ + be32_to_cpu(new_vh->data_size); + + dbg_bld("vol %i: AEB %i's PEB %i is the newer", + av->vol_id, aeb->lnum, new_aeb->pnum); + + aeb->ec = new_aeb->ec; + aeb->pnum = new_aeb->pnum; + aeb->copy_flag = new_vh->copy_flag; + aeb->scrub = new_aeb->scrub; + kmem_cache_free(ai->aeb_slab_cache, new_aeb); + + /* new_aeb is older */ + } else { + dbg_bld("vol %i: AEB %i's PEB %i is old, dropping it", + av->vol_id, aeb->lnum, new_aeb->pnum); + list_add_tail(&new_aeb->u.list, &ai->erase); + } + + return 0; + } + /* This LEB is new, let's add it to the volume */ + + if (av->highest_lnum <= be32_to_cpu(new_vh->lnum)) { + av->highest_lnum = be32_to_cpu(new_vh->lnum); + av->last_data_size = be32_to_cpu(new_vh->data_size); + } + + if (av->vol_type == UBI_STATIC_VOLUME) + av->used_ebs = be32_to_cpu(new_vh->used_ebs); + + av->leb_count++; + + rb_link_node(&new_aeb->u.rb, parent, p); + rb_insert_color(&new_aeb->u.rb, &av->root); + + return 0; +} + +/** + * process_pool_aeb - we found a non-empty PEB in a pool. + * @ubi: UBI device object + * @ai: attach info object + * @new_vh: the volume header derived from new_aeb + * @new_aeb: the AEB to be examined + * + * Returns 0 on success, < 0 indicates an internal error. + */ +static int process_pool_aeb(struct ubi_device *ubi, struct ubi_attach_info *ai, + struct ubi_vid_hdr *new_vh, + struct ubi_ainf_peb *new_aeb) +{ + struct ubi_ainf_volume *av, *tmp_av = NULL; + struct rb_node **p = &ai->volumes.rb_node, *parent = NULL; + int found = 0; + + if (be32_to_cpu(new_vh->vol_id) == UBI_FM_SB_VOLUME_ID || + be32_to_cpu(new_vh->vol_id) == UBI_FM_DATA_VOLUME_ID) { + kmem_cache_free(ai->aeb_slab_cache, new_aeb); + + return 0; + } + + /* Find the volume this SEB belongs to */ + while (*p) { + parent = *p; + tmp_av = rb_entry(parent, struct ubi_ainf_volume, rb); + + if (be32_to_cpu(new_vh->vol_id) > tmp_av->vol_id) + p = &(*p)->rb_left; + else if (be32_to_cpu(new_vh->vol_id) < tmp_av->vol_id) + p = &(*p)->rb_right; + else { + found = 1; + break; + } + } + + if (found) + av = tmp_av; + else { + ubi_err("orphaned volume in fastmap pool!"); + return UBI_BAD_FASTMAP; + } + + ubi_assert(be32_to_cpu(new_vh->vol_id) == av->vol_id); + + return update_vol(ubi, ai, av, new_vh, new_aeb); +} + +/** + * unmap_peb - unmap a PEB. + * If fastmap detects a free PEB in the pool it has to check whether + * this PEB has been unmapped after writing the fastmap. + * + * @ai: UBI attach info object + * @pnum: The PEB to be unmapped + */ +static void unmap_peb(struct ubi_attach_info *ai, int pnum) +{ + struct ubi_ainf_volume *av; + struct rb_node *node, *node2; + struct ubi_ainf_peb *aeb; + + for (node = rb_first(&ai->volumes); node; node = rb_next(node)) { + av = rb_entry(node, struct ubi_ainf_volume, rb); + + for (node2 = rb_first(&av->root); node2; + node2 = rb_next(node2)) { + aeb = rb_entry(node2, struct ubi_ainf_peb, u.rb); + if (aeb->pnum == pnum) { + rb_erase(&aeb->u.rb, &av->root); + kmem_cache_free(ai->aeb_slab_cache, aeb); + return; + } + } + } +} + +/** + * scan_pool - scans a pool for changed (no longer empty PEBs). + * @ubi: UBI device object + * @ai: attach info object + * @pebs: an array of all PEB numbers in the to be scanned pool + * @pool_size: size of the pool (number of entries in @pebs) + * @max_sqnum: pointer to the maximal sequence number + * @eba_orphans: list of PEBs which need to be scanned + * @free: list of PEBs which are most likely free (and go into @ai->free) + * + * Returns 0 on success, if the pool is unusable UBI_BAD_FASTMAP is returned. + * < 0 indicates an internal error. + */ +#ifndef __UBOOT__ +static int scan_pool(struct ubi_device *ubi, struct ubi_attach_info *ai, + int *pebs, int pool_size, unsigned long long *max_sqnum, + struct list_head *eba_orphans, struct list_head *freef) +#else +static int scan_pool(struct ubi_device *ubi, struct ubi_attach_info *ai, + __be32 *pebs, int pool_size, unsigned long long *max_sqnum, + struct list_head *eba_orphans, struct list_head *freef) +#endif +{ + struct ubi_vid_hdr *vh; + struct ubi_ec_hdr *ech; + struct ubi_ainf_peb *new_aeb, *tmp_aeb; + int i, pnum, err, found_orphan, ret = 0; + + ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); + if (!ech) + return -ENOMEM; + + vh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); + if (!vh) { + kfree(ech); + return -ENOMEM; + } + + dbg_bld("scanning fastmap pool: size = %i", pool_size); + + /* + * Now scan all PEBs in the pool to find changes which have been made + * after the creation of the fastmap + */ + for (i = 0; i < pool_size; i++) { + int scrub = 0; + int image_seq; + + pnum = be32_to_cpu(pebs[i]); + + if (ubi_io_is_bad(ubi, pnum)) { + ubi_err("bad PEB in fastmap pool!"); + ret = UBI_BAD_FASTMAP; + goto out; + } + + err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); + if (err && err != UBI_IO_BITFLIPS) { + ubi_err("unable to read EC header! PEB:%i err:%i", + pnum, err); + ret = err > 0 ? UBI_BAD_FASTMAP : err; + goto out; + } else if (ret == UBI_IO_BITFLIPS) + scrub = 1; + + /* + * Older UBI implementations have image_seq set to zero, so + * we shouldn't fail if image_seq == 0. + */ + image_seq = be32_to_cpu(ech->image_seq); + + if (image_seq && (image_seq != ubi->image_seq)) { + ubi_err("bad image seq: 0x%x, expected: 0x%x", + be32_to_cpu(ech->image_seq), ubi->image_seq); + ret = UBI_BAD_FASTMAP; + goto out; + } + + err = ubi_io_read_vid_hdr(ubi, pnum, vh, 0); + if (err == UBI_IO_FF || err == UBI_IO_FF_BITFLIPS) { + unsigned long long ec = be64_to_cpu(ech->ec); + unmap_peb(ai, pnum); + dbg_bld("Adding PEB to free: %i", pnum); + if (err == UBI_IO_FF_BITFLIPS) + add_aeb(ai, freef, pnum, ec, 1); + else + add_aeb(ai, freef, pnum, ec, 0); + continue; + } else if (err == 0 || err == UBI_IO_BITFLIPS) { + dbg_bld("Found non empty PEB:%i in pool", pnum); + + if (err == UBI_IO_BITFLIPS) + scrub = 1; + + found_orphan = 0; + list_for_each_entry(tmp_aeb, eba_orphans, u.list) { + if (tmp_aeb->pnum == pnum) { + found_orphan = 1; + break; + } + } + if (found_orphan) { + list_del(&tmp_aeb->u.list); + kmem_cache_free(ai->aeb_slab_cache, tmp_aeb); + } + + new_aeb = kmem_cache_alloc(ai->aeb_slab_cache, + GFP_KERNEL); + if (!new_aeb) { + ret = -ENOMEM; + goto out; + } + + new_aeb->ec = be64_to_cpu(ech->ec); + new_aeb->pnum = pnum; + new_aeb->lnum = be32_to_cpu(vh->lnum); + new_aeb->sqnum = be64_to_cpu(vh->sqnum); + new_aeb->copy_flag = vh->copy_flag; + new_aeb->scrub = scrub; + + if (*max_sqnum < new_aeb->sqnum) + *max_sqnum = new_aeb->sqnum; + + err = process_pool_aeb(ubi, ai, vh, new_aeb); + if (err) { + ret = err > 0 ? UBI_BAD_FASTMAP : err; + goto out; + } + } else { + /* We are paranoid and fall back to scanning mode */ + ubi_err("fastmap pool PEBs contains damaged PEBs!"); + ret = err > 0 ? UBI_BAD_FASTMAP : err; + goto out; + } + + } + +out: + ubi_free_vid_hdr(ubi, vh); + kfree(ech); + return ret; +} + +/** + * count_fastmap_pebs - Counts the PEBs found by fastmap. + * @ai: The UBI attach info object + */ +static int count_fastmap_pebs(struct ubi_attach_info *ai) +{ + struct ubi_ainf_peb *aeb; + struct ubi_ainf_volume *av; + struct rb_node *rb1, *rb2; + int n = 0; + + list_for_each_entry(aeb, &ai->erase, u.list) + n++; + + list_for_each_entry(aeb, &ai->free, u.list) + n++; + + ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) + ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb) + n++; + + return n; +} + +/** + * ubi_attach_fastmap - creates ubi_attach_info from a fastmap. + * @ubi: UBI device object + * @ai: UBI attach info object + * @fm: the fastmap to be attached + * + * Returns 0 on success, UBI_BAD_FASTMAP if the found fastmap was unusable. + * < 0 indicates an internal error. + */ +static int ubi_attach_fastmap(struct ubi_device *ubi, + struct ubi_attach_info *ai, + struct ubi_fastmap_layout *fm) +{ + struct list_head used, eba_orphans, freef; + struct ubi_ainf_volume *av; + struct ubi_ainf_peb *aeb, *tmp_aeb, *_tmp_aeb; + struct ubi_ec_hdr *ech; + struct ubi_fm_sb *fmsb; + struct ubi_fm_hdr *fmhdr; + struct ubi_fm_scan_pool *fmpl1, *fmpl2; + struct ubi_fm_ec *fmec; + struct ubi_fm_volhdr *fmvhdr; + struct ubi_fm_eba *fm_eba; + int ret, i, j, pool_size, wl_pool_size; + size_t fm_pos = 0, fm_size = ubi->fm_size; + unsigned long long max_sqnum = 0; + void *fm_raw = ubi->fm_buf; + + INIT_LIST_HEAD(&used); + INIT_LIST_HEAD(&freef); + INIT_LIST_HEAD(&eba_orphans); + INIT_LIST_HEAD(&ai->corr); + INIT_LIST_HEAD(&ai->free); + INIT_LIST_HEAD(&ai->erase); + INIT_LIST_HEAD(&ai->alien); + ai->volumes = RB_ROOT; + ai->min_ec = UBI_MAX_ERASECOUNTER; + + ai->aeb_slab_cache = kmem_cache_create("ubi_ainf_peb_slab", + sizeof(struct ubi_ainf_peb), + 0, 0, NULL); + if (!ai->aeb_slab_cache) { + ret = -ENOMEM; + goto fail; + } + + fmsb = (struct ubi_fm_sb *)(fm_raw); + ai->max_sqnum = fmsb->sqnum; + fm_pos += sizeof(struct ubi_fm_sb); + if (fm_pos >= fm_size) + goto fail_bad; + + fmhdr = (struct ubi_fm_hdr *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmhdr); + if (fm_pos >= fm_size) + goto fail_bad; + + if (be32_to_cpu(fmhdr->magic) != UBI_FM_HDR_MAGIC) { + ubi_err("bad fastmap header magic: 0x%x, expected: 0x%x", + be32_to_cpu(fmhdr->magic), UBI_FM_HDR_MAGIC); + goto fail_bad; + } + + fmpl1 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmpl1); + if (fm_pos >= fm_size) + goto fail_bad; + if (be32_to_cpu(fmpl1->magic) != UBI_FM_POOL_MAGIC) { + ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x", + be32_to_cpu(fmpl1->magic), UBI_FM_POOL_MAGIC); + goto fail_bad; + } + + fmpl2 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmpl2); + if (fm_pos >= fm_size) + goto fail_bad; + if (be32_to_cpu(fmpl2->magic) != UBI_FM_POOL_MAGIC) { + ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x", + be32_to_cpu(fmpl2->magic), UBI_FM_POOL_MAGIC); + goto fail_bad; + } + + pool_size = be16_to_cpu(fmpl1->size); + wl_pool_size = be16_to_cpu(fmpl2->size); + fm->max_pool_size = be16_to_cpu(fmpl1->max_size); + fm->max_wl_pool_size = be16_to_cpu(fmpl2->max_size); + + if (pool_size > UBI_FM_MAX_POOL_SIZE || pool_size < 0) { + ubi_err("bad pool size: %i", pool_size); + goto fail_bad; + } + + if (wl_pool_size > UBI_FM_MAX_POOL_SIZE || wl_pool_size < 0) { + ubi_err("bad WL pool size: %i", wl_pool_size); + goto fail_bad; + } + + + if (fm->max_pool_size > UBI_FM_MAX_POOL_SIZE || + fm->max_pool_size < 0) { + ubi_err("bad maximal pool size: %i", fm->max_pool_size); + goto fail_bad; + } + + if (fm->max_wl_pool_size > UBI_FM_MAX_POOL_SIZE || + fm->max_wl_pool_size < 0) { + ubi_err("bad maximal WL pool size: %i", fm->max_wl_pool_size); + goto fail_bad; + } + + /* read EC values from free list */ + for (i = 0; i < be32_to_cpu(fmhdr->free_peb_count); i++) { + fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmec); + if (fm_pos >= fm_size) + goto fail_bad; + + add_aeb(ai, &ai->free, be32_to_cpu(fmec->pnum), + be32_to_cpu(fmec->ec), 0); + } + + /* read EC values from used list */ + for (i = 0; i < be32_to_cpu(fmhdr->used_peb_count); i++) { + fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmec); + if (fm_pos >= fm_size) + goto fail_bad; + + add_aeb(ai, &used, be32_to_cpu(fmec->pnum), + be32_to_cpu(fmec->ec), 0); + } + + /* read EC values from scrub list */ + for (i = 0; i < be32_to_cpu(fmhdr->scrub_peb_count); i++) { + fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmec); + if (fm_pos >= fm_size) + goto fail_bad; + + add_aeb(ai, &used, be32_to_cpu(fmec->pnum), + be32_to_cpu(fmec->ec), 1); + } + + /* read EC values from erase list */ + for (i = 0; i < be32_to_cpu(fmhdr->erase_peb_count); i++) { + fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmec); + if (fm_pos >= fm_size) + goto fail_bad; + + add_aeb(ai, &ai->erase, be32_to_cpu(fmec->pnum), + be32_to_cpu(fmec->ec), 1); + } + + ai->mean_ec = div_u64(ai->ec_sum, ai->ec_count); + ai->bad_peb_count = be32_to_cpu(fmhdr->bad_peb_count); + + /* Iterate over all volumes and read their EBA table */ + for (i = 0; i < be32_to_cpu(fmhdr->vol_count); i++) { + fmvhdr = (struct ubi_fm_volhdr *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmvhdr); + if (fm_pos >= fm_size) + goto fail_bad; + + if (be32_to_cpu(fmvhdr->magic) != UBI_FM_VHDR_MAGIC) { + ubi_err("bad fastmap vol header magic: 0x%x, " \ + "expected: 0x%x", + be32_to_cpu(fmvhdr->magic), UBI_FM_VHDR_MAGIC); + goto fail_bad; + } + + av = add_vol(ai, be32_to_cpu(fmvhdr->vol_id), + be32_to_cpu(fmvhdr->used_ebs), + be32_to_cpu(fmvhdr->data_pad), + fmvhdr->vol_type, + be32_to_cpu(fmvhdr->last_eb_bytes)); + + if (!av) + goto fail_bad; + + ai->vols_found++; + if (ai->highest_vol_id < be32_to_cpu(fmvhdr->vol_id)) + ai->highest_vol_id = be32_to_cpu(fmvhdr->vol_id); + + fm_eba = (struct ubi_fm_eba *)(fm_raw + fm_pos); + fm_pos += sizeof(*fm_eba); + fm_pos += (sizeof(__be32) * be32_to_cpu(fm_eba->reserved_pebs)); + if (fm_pos >= fm_size) + goto fail_bad; + + if (be32_to_cpu(fm_eba->magic) != UBI_FM_EBA_MAGIC) { + ubi_err("bad fastmap EBA header magic: 0x%x, " \ + "expected: 0x%x", + be32_to_cpu(fm_eba->magic), UBI_FM_EBA_MAGIC); + goto fail_bad; + } + + for (j = 0; j < be32_to_cpu(fm_eba->reserved_pebs); j++) { + int pnum = be32_to_cpu(fm_eba->pnum[j]); + + if ((int)be32_to_cpu(fm_eba->pnum[j]) < 0) + continue; + + aeb = NULL; + list_for_each_entry(tmp_aeb, &used, u.list) { + if (tmp_aeb->pnum == pnum) { + aeb = tmp_aeb; + break; + } + } + + /* This can happen if a PEB is already in an EBA known + * by this fastmap but the PEB itself is not in the used + * list. + * In this case the PEB can be within the fastmap pool + * or while writing the fastmap it was in the protection + * queue. + */ + if (!aeb) { + aeb = kmem_cache_alloc(ai->aeb_slab_cache, + GFP_KERNEL); + if (!aeb) { + ret = -ENOMEM; + + goto fail; + } + + aeb->lnum = j; + aeb->pnum = be32_to_cpu(fm_eba->pnum[j]); + aeb->ec = -1; + aeb->scrub = aeb->copy_flag = aeb->sqnum = 0; + list_add_tail(&aeb->u.list, &eba_orphans); + continue; + } + + aeb->lnum = j; + + if (av->highest_lnum <= aeb->lnum) + av->highest_lnum = aeb->lnum; + + assign_aeb_to_av(ai, aeb, av); + + dbg_bld("inserting PEB:%i (LEB %i) to vol %i", + aeb->pnum, aeb->lnum, av->vol_id); + } + + ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); + if (!ech) { + ret = -ENOMEM; + goto fail; + } + + list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &eba_orphans, + u.list) { + int err; + + if (ubi_io_is_bad(ubi, tmp_aeb->pnum)) { + ubi_err("bad PEB in fastmap EBA orphan list"); + ret = UBI_BAD_FASTMAP; + kfree(ech); + goto fail; + } + + err = ubi_io_read_ec_hdr(ubi, tmp_aeb->pnum, ech, 0); + if (err && err != UBI_IO_BITFLIPS) { + ubi_err("unable to read EC header! PEB:%i " \ + "err:%i", tmp_aeb->pnum, err); + ret = err > 0 ? UBI_BAD_FASTMAP : err; + kfree(ech); + + goto fail; + } else if (err == UBI_IO_BITFLIPS) + tmp_aeb->scrub = 1; + + tmp_aeb->ec = be64_to_cpu(ech->ec); + assign_aeb_to_av(ai, tmp_aeb, av); + } + + kfree(ech); + } + + ret = scan_pool(ubi, ai, fmpl1->pebs, pool_size, &max_sqnum, + &eba_orphans, &freef); + if (ret) + goto fail; + + ret = scan_pool(ubi, ai, fmpl2->pebs, wl_pool_size, &max_sqnum, + &eba_orphans, &freef); + if (ret) + goto fail; + + if (max_sqnum > ai->max_sqnum) + ai->max_sqnum = max_sqnum; + + list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &freef, u.list) + list_move_tail(&tmp_aeb->u.list, &ai->free); + + ubi_assert(list_empty(&used)); + ubi_assert(list_empty(&eba_orphans)); + ubi_assert(list_empty(&freef)); + + /* + * If fastmap is leaking PEBs (must not happen), raise a + * fat warning and fall back to scanning mode. + * We do this here because in ubi_wl_init() it's too late + * and we cannot fall back to scanning. + */ +#ifndef __UBOOT__ + if (WARN_ON(count_fastmap_pebs(ai) != ubi->peb_count - + ai->bad_peb_count - fm->used_blocks)) + goto fail_bad; +#else + if (count_fastmap_pebs(ai) != ubi->peb_count - + ai->bad_peb_count - fm->used_blocks) { + WARN_ON(1); + goto fail_bad; + } +#endif + + return 0; + +fail_bad: + ret = UBI_BAD_FASTMAP; +fail: + list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &used, u.list) { + list_del(&tmp_aeb->u.list); + kmem_cache_free(ai->aeb_slab_cache, tmp_aeb); + } + list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &eba_orphans, u.list) { + list_del(&tmp_aeb->u.list); + kmem_cache_free(ai->aeb_slab_cache, tmp_aeb); + } + list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &freef, u.list) { + list_del(&tmp_aeb->u.list); + kmem_cache_free(ai->aeb_slab_cache, tmp_aeb); + } + + return ret; +} + +/** + * ubi_scan_fastmap - scan the fastmap. + * @ubi: UBI device object + * @ai: UBI attach info to be filled + * @fm_anchor: The fastmap starts at this PEB + * + * Returns 0 on success, UBI_NO_FASTMAP if no fastmap was found, + * UBI_BAD_FASTMAP if one was found but is not usable. + * < 0 indicates an internal error. + */ +int ubi_scan_fastmap(struct ubi_device *ubi, struct ubi_attach_info *ai, + int fm_anchor) +{ + struct ubi_fm_sb *fmsb, *fmsb2; + struct ubi_vid_hdr *vh; + struct ubi_ec_hdr *ech; + struct ubi_fastmap_layout *fm; + int i, used_blocks, pnum, ret = 0; + size_t fm_size; + __be32 crc, tmp_crc; + unsigned long long sqnum = 0; + + mutex_lock(&ubi->fm_mutex); + memset(ubi->fm_buf, 0, ubi->fm_size); + + fmsb = kmalloc(sizeof(*fmsb), GFP_KERNEL); + if (!fmsb) { + ret = -ENOMEM; + goto out; + } + + fm = kzalloc(sizeof(*fm), GFP_KERNEL); + if (!fm) { + ret = -ENOMEM; + kfree(fmsb); + goto out; + } + + ret = ubi_io_read(ubi, fmsb, fm_anchor, ubi->leb_start, sizeof(*fmsb)); + if (ret && ret != UBI_IO_BITFLIPS) + goto free_fm_sb; + else if (ret == UBI_IO_BITFLIPS) + fm->to_be_tortured[0] = 1; + + if (be32_to_cpu(fmsb->magic) != UBI_FM_SB_MAGIC) { + ubi_err("bad super block magic: 0x%x, expected: 0x%x", + be32_to_cpu(fmsb->magic), UBI_FM_SB_MAGIC); + ret = UBI_BAD_FASTMAP; + goto free_fm_sb; + } + + if (fmsb->version != UBI_FM_FMT_VERSION) { + ubi_err("bad fastmap version: %i, expected: %i", + fmsb->version, UBI_FM_FMT_VERSION); + ret = UBI_BAD_FASTMAP; + goto free_fm_sb; + } + + used_blocks = be32_to_cpu(fmsb->used_blocks); + if (used_blocks > UBI_FM_MAX_BLOCKS || used_blocks < 1) { + ubi_err("number of fastmap blocks is invalid: %i", used_blocks); + ret = UBI_BAD_FASTMAP; + goto free_fm_sb; + } + + fm_size = ubi->leb_size * used_blocks; + if (fm_size != ubi->fm_size) { + ubi_err("bad fastmap size: %zi, expected: %zi", fm_size, + ubi->fm_size); + ret = UBI_BAD_FASTMAP; + goto free_fm_sb; + } + + ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); + if (!ech) { + ret = -ENOMEM; + goto free_fm_sb; + } + + vh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); + if (!vh) { + ret = -ENOMEM; + goto free_hdr; + } + + for (i = 0; i < used_blocks; i++) { + int image_seq; + + pnum = be32_to_cpu(fmsb->block_loc[i]); + + if (ubi_io_is_bad(ubi, pnum)) { + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + + ret = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); + if (ret && ret != UBI_IO_BITFLIPS) { + ubi_err("unable to read fastmap block# %i EC (PEB: %i)", + i, pnum); + if (ret > 0) + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } else if (ret == UBI_IO_BITFLIPS) + fm->to_be_tortured[i] = 1; + + image_seq = be32_to_cpu(ech->image_seq); + if (!ubi->image_seq) + ubi->image_seq = image_seq; + + /* + * Older UBI implementations have image_seq set to zero, so + * we shouldn't fail if image_seq == 0. + */ + if (image_seq && (image_seq != ubi->image_seq)) { + ubi_err("wrong image seq:%d instead of %d", + be32_to_cpu(ech->image_seq), ubi->image_seq); + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + + ret = ubi_io_read_vid_hdr(ubi, pnum, vh, 0); + if (ret && ret != UBI_IO_BITFLIPS) { + ubi_err("unable to read fastmap block# %i (PEB: %i)", + i, pnum); + goto free_hdr; + } + + if (i == 0) { + if (be32_to_cpu(vh->vol_id) != UBI_FM_SB_VOLUME_ID) { + ubi_err("bad fastmap anchor vol_id: 0x%x," \ + " expected: 0x%x", + be32_to_cpu(vh->vol_id), + UBI_FM_SB_VOLUME_ID); + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + } else { + if (be32_to_cpu(vh->vol_id) != UBI_FM_DATA_VOLUME_ID) { + ubi_err("bad fastmap data vol_id: 0x%x," \ + " expected: 0x%x", + be32_to_cpu(vh->vol_id), + UBI_FM_DATA_VOLUME_ID); + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + } + + if (sqnum < be64_to_cpu(vh->sqnum)) + sqnum = be64_to_cpu(vh->sqnum); + + ret = ubi_io_read(ubi, ubi->fm_buf + (ubi->leb_size * i), pnum, + ubi->leb_start, ubi->leb_size); + if (ret && ret != UBI_IO_BITFLIPS) { + ubi_err("unable to read fastmap block# %i (PEB: %i, " \ + "err: %i)", i, pnum, ret); + goto free_hdr; + } + } + + kfree(fmsb); + fmsb = NULL; + + fmsb2 = (struct ubi_fm_sb *)(ubi->fm_buf); + tmp_crc = be32_to_cpu(fmsb2->data_crc); + fmsb2->data_crc = 0; + crc = crc32(UBI_CRC32_INIT, ubi->fm_buf, fm_size); + if (crc != tmp_crc) { + ubi_err("fastmap data CRC is invalid"); + ubi_err("CRC should be: 0x%x, calc: 0x%x", tmp_crc, crc); + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + + fmsb2->sqnum = sqnum; + + fm->used_blocks = used_blocks; + + ret = ubi_attach_fastmap(ubi, ai, fm); + if (ret) { + if (ret > 0) + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + + for (i = 0; i < used_blocks; i++) { + struct ubi_wl_entry *e; + + e = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL); + if (!e) { + while (i--) + kfree(fm->e[i]); + + ret = -ENOMEM; + goto free_hdr; + } + + e->pnum = be32_to_cpu(fmsb2->block_loc[i]); + e->ec = be32_to_cpu(fmsb2->block_ec[i]); + fm->e[i] = e; + } + + ubi->fm = fm; + ubi->fm_pool.max_size = ubi->fm->max_pool_size; + ubi->fm_wl_pool.max_size = ubi->fm->max_wl_pool_size; + ubi_msg("attached by fastmap"); + ubi_msg("fastmap pool size: %d", ubi->fm_pool.max_size); + ubi_msg("fastmap WL pool size: %d", ubi->fm_wl_pool.max_size); + ubi->fm_disabled = 0; + + ubi_free_vid_hdr(ubi, vh); + kfree(ech); +out: + mutex_unlock(&ubi->fm_mutex); + if (ret == UBI_BAD_FASTMAP) + ubi_err("Attach by fastmap failed, doing a full scan!"); + return ret; + +free_hdr: + ubi_free_vid_hdr(ubi, vh); + kfree(ech); +free_fm_sb: + kfree(fmsb); + kfree(fm); + goto out; +} + +/** + * ubi_write_fastmap - writes a fastmap. + * @ubi: UBI device object + * @new_fm: the to be written fastmap + * + * Returns 0 on success, < 0 indicates an internal error. + */ +static int ubi_write_fastmap(struct ubi_device *ubi, + struct ubi_fastmap_layout *new_fm) +{ + size_t fm_pos = 0; + void *fm_raw; + struct ubi_fm_sb *fmsb; + struct ubi_fm_hdr *fmh; + struct ubi_fm_scan_pool *fmpl1, *fmpl2; + struct ubi_fm_ec *fec; + struct ubi_fm_volhdr *fvh; + struct ubi_fm_eba *feba; + struct rb_node *node; + struct ubi_wl_entry *wl_e; + struct ubi_volume *vol; + struct ubi_vid_hdr *avhdr, *dvhdr; + struct ubi_work *ubi_wrk; + int ret, i, j, free_peb_count, used_peb_count, vol_count; + int scrub_peb_count, erase_peb_count; + + fm_raw = ubi->fm_buf; + memset(ubi->fm_buf, 0, ubi->fm_size); + + avhdr = new_fm_vhdr(ubi, UBI_FM_SB_VOLUME_ID); + if (!avhdr) { + ret = -ENOMEM; + goto out; + } + + dvhdr = new_fm_vhdr(ubi, UBI_FM_DATA_VOLUME_ID); + if (!dvhdr) { + ret = -ENOMEM; + goto out_kfree; + } + + spin_lock(&ubi->volumes_lock); + spin_lock(&ubi->wl_lock); + + fmsb = (struct ubi_fm_sb *)fm_raw; + fm_pos += sizeof(*fmsb); + ubi_assert(fm_pos <= ubi->fm_size); + + fmh = (struct ubi_fm_hdr *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmh); + ubi_assert(fm_pos <= ubi->fm_size); + + fmsb->magic = cpu_to_be32(UBI_FM_SB_MAGIC); + fmsb->version = UBI_FM_FMT_VERSION; + fmsb->used_blocks = cpu_to_be32(new_fm->used_blocks); + /* the max sqnum will be filled in while *reading* the fastmap */ + fmsb->sqnum = 0; + + fmh->magic = cpu_to_be32(UBI_FM_HDR_MAGIC); + free_peb_count = 0; + used_peb_count = 0; + scrub_peb_count = 0; + erase_peb_count = 0; + vol_count = 0; + + fmpl1 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmpl1); + fmpl1->magic = cpu_to_be32(UBI_FM_POOL_MAGIC); + fmpl1->size = cpu_to_be16(ubi->fm_pool.size); + fmpl1->max_size = cpu_to_be16(ubi->fm_pool.max_size); + + for (i = 0; i < ubi->fm_pool.size; i++) + fmpl1->pebs[i] = cpu_to_be32(ubi->fm_pool.pebs[i]); + + fmpl2 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmpl2); + fmpl2->magic = cpu_to_be32(UBI_FM_POOL_MAGIC); + fmpl2->size = cpu_to_be16(ubi->fm_wl_pool.size); + fmpl2->max_size = cpu_to_be16(ubi->fm_wl_pool.max_size); + + for (i = 0; i < ubi->fm_wl_pool.size; i++) + fmpl2->pebs[i] = cpu_to_be32(ubi->fm_wl_pool.pebs[i]); + + for (node = rb_first(&ubi->free); node; node = rb_next(node)) { + wl_e = rb_entry(node, struct ubi_wl_entry, u.rb); + fec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + + fec->pnum = cpu_to_be32(wl_e->pnum); + fec->ec = cpu_to_be32(wl_e->ec); + + free_peb_count++; + fm_pos += sizeof(*fec); + ubi_assert(fm_pos <= ubi->fm_size); + } + fmh->free_peb_count = cpu_to_be32(free_peb_count); + + for (node = rb_first(&ubi->used); node; node = rb_next(node)) { + wl_e = rb_entry(node, struct ubi_wl_entry, u.rb); + fec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + + fec->pnum = cpu_to_be32(wl_e->pnum); + fec->ec = cpu_to_be32(wl_e->ec); + + used_peb_count++; + fm_pos += sizeof(*fec); + ubi_assert(fm_pos <= ubi->fm_size); + } + fmh->used_peb_count = cpu_to_be32(used_peb_count); + + for (node = rb_first(&ubi->scrub); node; node = rb_next(node)) { + wl_e = rb_entry(node, struct ubi_wl_entry, u.rb); + fec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + + fec->pnum = cpu_to_be32(wl_e->pnum); + fec->ec = cpu_to_be32(wl_e->ec); + + scrub_peb_count++; + fm_pos += sizeof(*fec); + ubi_assert(fm_pos <= ubi->fm_size); + } + fmh->scrub_peb_count = cpu_to_be32(scrub_peb_count); + + + list_for_each_entry(ubi_wrk, &ubi->works, list) { + if (ubi_is_erase_work(ubi_wrk)) { + wl_e = ubi_wrk->e; + ubi_assert(wl_e); + + fec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + + fec->pnum = cpu_to_be32(wl_e->pnum); + fec->ec = cpu_to_be32(wl_e->ec); + + erase_peb_count++; + fm_pos += sizeof(*fec); + ubi_assert(fm_pos <= ubi->fm_size); + } + } + fmh->erase_peb_count = cpu_to_be32(erase_peb_count); + + for (i = 0; i < UBI_MAX_VOLUMES + UBI_INT_VOL_COUNT; i++) { + vol = ubi->volumes[i]; + + if (!vol) + continue; + + vol_count++; + + fvh = (struct ubi_fm_volhdr *)(fm_raw + fm_pos); + fm_pos += sizeof(*fvh); + ubi_assert(fm_pos <= ubi->fm_size); + + fvh->magic = cpu_to_be32(UBI_FM_VHDR_MAGIC); + fvh->vol_id = cpu_to_be32(vol->vol_id); + fvh->vol_type = vol->vol_type; + fvh->used_ebs = cpu_to_be32(vol->used_ebs); + fvh->data_pad = cpu_to_be32(vol->data_pad); + fvh->last_eb_bytes = cpu_to_be32(vol->last_eb_bytes); + + ubi_assert(vol->vol_type == UBI_DYNAMIC_VOLUME || + vol->vol_type == UBI_STATIC_VOLUME); + + feba = (struct ubi_fm_eba *)(fm_raw + fm_pos); + fm_pos += sizeof(*feba) + (sizeof(__be32) * vol->reserved_pebs); + ubi_assert(fm_pos <= ubi->fm_size); + + for (j = 0; j < vol->reserved_pebs; j++) + feba->pnum[j] = cpu_to_be32(vol->eba_tbl[j]); + + feba->reserved_pebs = cpu_to_be32(j); + feba->magic = cpu_to_be32(UBI_FM_EBA_MAGIC); + } + fmh->vol_count = cpu_to_be32(vol_count); + fmh->bad_peb_count = cpu_to_be32(ubi->bad_peb_count); + + avhdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); + avhdr->lnum = 0; + + spin_unlock(&ubi->wl_lock); + spin_unlock(&ubi->volumes_lock); + + dbg_bld("writing fastmap SB to PEB %i", new_fm->e[0]->pnum); + ret = ubi_io_write_vid_hdr(ubi, new_fm->e[0]->pnum, avhdr); + if (ret) { + ubi_err("unable to write vid_hdr to fastmap SB!"); + goto out_kfree; + } + + for (i = 0; i < new_fm->used_blocks; i++) { + fmsb->block_loc[i] = cpu_to_be32(new_fm->e[i]->pnum); + fmsb->block_ec[i] = cpu_to_be32(new_fm->e[i]->ec); + } + + fmsb->data_crc = 0; + fmsb->data_crc = cpu_to_be32(crc32(UBI_CRC32_INIT, fm_raw, + ubi->fm_size)); + + for (i = 1; i < new_fm->used_blocks; i++) { + dvhdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); + dvhdr->lnum = cpu_to_be32(i); + dbg_bld("writing fastmap data to PEB %i sqnum %llu", + new_fm->e[i]->pnum, be64_to_cpu(dvhdr->sqnum)); + ret = ubi_io_write_vid_hdr(ubi, new_fm->e[i]->pnum, dvhdr); + if (ret) { + ubi_err("unable to write vid_hdr to PEB %i!", + new_fm->e[i]->pnum); + goto out_kfree; + } + } + + for (i = 0; i < new_fm->used_blocks; i++) { + ret = ubi_io_write(ubi, fm_raw + (i * ubi->leb_size), + new_fm->e[i]->pnum, ubi->leb_start, ubi->leb_size); + if (ret) { + ubi_err("unable to write fastmap to PEB %i!", + new_fm->e[i]->pnum); + goto out_kfree; + } + } + + ubi_assert(new_fm); + ubi->fm = new_fm; + + dbg_bld("fastmap written!"); + +out_kfree: + ubi_free_vid_hdr(ubi, avhdr); + ubi_free_vid_hdr(ubi, dvhdr); +out: + return ret; +} + +/** + * erase_block - Manually erase a PEB. + * @ubi: UBI device object + * @pnum: PEB to be erased + * + * Returns the new EC value on success, < 0 indicates an internal error. + */ +static int erase_block(struct ubi_device *ubi, int pnum) +{ + int ret; + struct ubi_ec_hdr *ec_hdr; + long long ec; + + ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); + if (!ec_hdr) + return -ENOMEM; + + ret = ubi_io_read_ec_hdr(ubi, pnum, ec_hdr, 0); + if (ret < 0) + goto out; + else if (ret && ret != UBI_IO_BITFLIPS) { + ret = -EINVAL; + goto out; + } + + ret = ubi_io_sync_erase(ubi, pnum, 0); + if (ret < 0) + goto out; + + ec = be64_to_cpu(ec_hdr->ec); + ec += ret; + if (ec > UBI_MAX_ERASECOUNTER) { + ret = -EINVAL; + goto out; + } + + ec_hdr->ec = cpu_to_be64(ec); + ret = ubi_io_write_ec_hdr(ubi, pnum, ec_hdr); + if (ret < 0) + goto out; + + ret = ec; +out: + kfree(ec_hdr); + return ret; +} + +/** + * invalidate_fastmap - destroys a fastmap. + * @ubi: UBI device object + * @fm: the fastmap to be destroyed + * + * Returns 0 on success, < 0 indicates an internal error. + */ +static int invalidate_fastmap(struct ubi_device *ubi, + struct ubi_fastmap_layout *fm) +{ + int ret; + struct ubi_vid_hdr *vh; + + ret = erase_block(ubi, fm->e[0]->pnum); + if (ret < 0) + return ret; + + vh = new_fm_vhdr(ubi, UBI_FM_SB_VOLUME_ID); + if (!vh) + return -ENOMEM; + + /* deleting the current fastmap SB is not enough, an old SB may exist, + * so create a (corrupted) SB such that fastmap will find it and fall + * back to scanning mode in any case */ + vh->sqnum = cpu_to_be64(ubi_next_sqnum(ubi)); + ret = ubi_io_write_vid_hdr(ubi, fm->e[0]->pnum, vh); + + return ret; +} + +/** + * ubi_update_fastmap - will be called by UBI if a volume changes or + * a fastmap pool becomes full. + * @ubi: UBI device object + * + * Returns 0 on success, < 0 indicates an internal error. + */ +int ubi_update_fastmap(struct ubi_device *ubi) +{ + int ret, i; + struct ubi_fastmap_layout *new_fm, *old_fm; + struct ubi_wl_entry *tmp_e; + + mutex_lock(&ubi->fm_mutex); + + ubi_refill_pools(ubi); + + if (ubi->ro_mode || ubi->fm_disabled) { + mutex_unlock(&ubi->fm_mutex); + return 0; + } + + ret = ubi_ensure_anchor_pebs(ubi); + if (ret) { + mutex_unlock(&ubi->fm_mutex); + return ret; + } + + new_fm = kzalloc(sizeof(*new_fm), GFP_KERNEL); + if (!new_fm) { + mutex_unlock(&ubi->fm_mutex); + return -ENOMEM; + } + + new_fm->used_blocks = ubi->fm_size / ubi->leb_size; + + for (i = 0; i < new_fm->used_blocks; i++) { + new_fm->e[i] = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL); + if (!new_fm->e[i]) { + while (i--) + kfree(new_fm->e[i]); + + kfree(new_fm); + mutex_unlock(&ubi->fm_mutex); + return -ENOMEM; + } + } + + old_fm = ubi->fm; + ubi->fm = NULL; + + if (new_fm->used_blocks > UBI_FM_MAX_BLOCKS) { + ubi_err("fastmap too large"); + ret = -ENOSPC; + goto err; + } + + for (i = 1; i < new_fm->used_blocks; i++) { + spin_lock(&ubi->wl_lock); + tmp_e = ubi_wl_get_fm_peb(ubi, 0); + spin_unlock(&ubi->wl_lock); + + if (!tmp_e && !old_fm) { + int j; + ubi_err("could not get any free erase block"); + + for (j = 1; j < i; j++) + ubi_wl_put_fm_peb(ubi, new_fm->e[j], j, 0); + + ret = -ENOSPC; + goto err; + } else if (!tmp_e && old_fm) { + ret = erase_block(ubi, old_fm->e[i]->pnum); + if (ret < 0) { + int j; + + for (j = 1; j < i; j++) + ubi_wl_put_fm_peb(ubi, new_fm->e[j], + j, 0); + + ubi_err("could not erase old fastmap PEB"); + goto err; + } + + new_fm->e[i]->pnum = old_fm->e[i]->pnum; + new_fm->e[i]->ec = old_fm->e[i]->ec; + } else { + new_fm->e[i]->pnum = tmp_e->pnum; + new_fm->e[i]->ec = tmp_e->ec; + + if (old_fm) + ubi_wl_put_fm_peb(ubi, old_fm->e[i], i, + old_fm->to_be_tortured[i]); + } + } + + spin_lock(&ubi->wl_lock); + tmp_e = ubi_wl_get_fm_peb(ubi, 1); + spin_unlock(&ubi->wl_lock); + + if (old_fm) { + /* no fresh anchor PEB was found, reuse the old one */ + if (!tmp_e) { + ret = erase_block(ubi, old_fm->e[0]->pnum); + if (ret < 0) { + int i; + ubi_err("could not erase old anchor PEB"); + + for (i = 1; i < new_fm->used_blocks; i++) + ubi_wl_put_fm_peb(ubi, new_fm->e[i], + i, 0); + goto err; + } + + new_fm->e[0]->pnum = old_fm->e[0]->pnum; + new_fm->e[0]->ec = ret; + } else { + /* we've got a new anchor PEB, return the old one */ + ubi_wl_put_fm_peb(ubi, old_fm->e[0], 0, + old_fm->to_be_tortured[0]); + + new_fm->e[0]->pnum = tmp_e->pnum; + new_fm->e[0]->ec = tmp_e->ec; + } + } else { + if (!tmp_e) { + int i; + ubi_err("could not find any anchor PEB"); + + for (i = 1; i < new_fm->used_blocks; i++) + ubi_wl_put_fm_peb(ubi, new_fm->e[i], i, 0); + + ret = -ENOSPC; + goto err; + } + + new_fm->e[0]->pnum = tmp_e->pnum; + new_fm->e[0]->ec = tmp_e->ec; + } + + down_write(&ubi->work_sem); + down_write(&ubi->fm_sem); + ret = ubi_write_fastmap(ubi, new_fm); + up_write(&ubi->fm_sem); + up_write(&ubi->work_sem); + + if (ret) + goto err; + +out_unlock: + mutex_unlock(&ubi->fm_mutex); + kfree(old_fm); + return ret; + +err: + kfree(new_fm); + + ubi_warn("Unable to write new fastmap, err=%i", ret); + + ret = 0; + if (old_fm) { + ret = invalidate_fastmap(ubi, old_fm); + if (ret < 0) + ubi_err("Unable to invalidiate current fastmap!"); + else if (ret) + ret = 0; + } + goto out_unlock; +} diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 960befc6dd..0e2e9335fe 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -1,22 +1,21 @@ /* * Copyright (c) International Business Machines Corp., 2006 * Copyright (c) Nokia Corporation, 2006, 2007 - * * SPDX-License-Identifier: GPL-2.0+ * * Author: Artem Bityutskiy (Битюцкий Артём) */ /* - * UBI input/output unit. + * UBI input/output sub-system. * - * This unit provides a uniform way to work with all kinds of the underlying - * MTD devices. It also implements handy functions for reading and writing UBI - * headers. + * This sub-system provides a uniform way to work with all kinds of the + * underlying MTD devices. It also implements handy functions for reading and + * writing UBI headers. * * We are trying to have a paranoid mindset and not to trust to what we read - * from the flash media in order to be more secure and robust. So this unit - * validates every single header it reads from the flash media. + * from the flash media in order to be more secure and robust. So this + * sub-system validates every single header it reads from the flash media. * * Some words about how the eraseblock headers are stored. * @@ -52,9 +51,9 @@ * device, e.g., make @ubi->min_io_size = 512 in the example above? * * A: because when writing a sub-page, MTD still writes a full 2K page but the - * bytes which are no relevant to the sub-page are 0xFF. So, basically, writing - * 4x512 sub-pages is 4 times slower then writing one 2KiB NAND page. Thus, we - * prefer to use sub-pages only for EV and VID headers. + * bytes which are not relevant to the sub-page are 0xFF. So, basically, + * writing 4x512 sub-pages is 4 times slower than writing one 2KiB NAND page. + * Thus, we prefer to use sub-pages only for EC and VID headers. * * As it was noted above, the VID header may start at a non-aligned offset. * For example, in case of a 2KiB page NAND flash with a 512 bytes sub-page, @@ -67,39 +66,32 @@ * 512-byte chunks, we have to allocate one more buffer and copy our VID header * to offset 448 of this buffer. * - * The I/O unit does the following trick in order to avoid this extra copy. - * It always allocates a @ubi->vid_hdr_alsize bytes buffer for the VID header - * and returns a pointer to offset @ubi->vid_hdr_shift of this buffer. When the - * VID header is being written out, it shifts the VID header pointer back and - * writes the whole sub-page. + * The I/O sub-system does the following trick in order to avoid this extra + * copy. It always allocates a @ubi->vid_hdr_alsize bytes buffer for the VID + * header and returns a pointer to offset @ubi->vid_hdr_shift of this buffer. + * When the VID header is being written out, it shifts the VID header pointer + * back and writes the whole sub-page. */ -#ifdef UBI_LINUX +#ifndef __UBOOT__ #include #include +#include +#else +#include #endif -#include #include "ubi.h" -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID -static int paranoid_check_not_bad(const struct ubi_device *ubi, int pnum); -static int paranoid_check_peb_ec_hdr(const struct ubi_device *ubi, int pnum); -static int paranoid_check_ec_hdr(const struct ubi_device *ubi, int pnum, - const struct ubi_ec_hdr *ec_hdr); -static int paranoid_check_peb_vid_hdr(const struct ubi_device *ubi, int pnum); -static int paranoid_check_vid_hdr(const struct ubi_device *ubi, int pnum, - const struct ubi_vid_hdr *vid_hdr); -static int paranoid_check_all_ff(struct ubi_device *ubi, int pnum, int offset, - int len); -#else -#define paranoid_check_not_bad(ubi, pnum) 0 -#define paranoid_check_peb_ec_hdr(ubi, pnum) 0 -#define paranoid_check_ec_hdr(ubi, pnum, ec_hdr) 0 -#define paranoid_check_peb_vid_hdr(ubi, pnum) 0 -#define paranoid_check_vid_hdr(ubi, pnum, vid_hdr) 0 -#define paranoid_check_all_ff(ubi, pnum, offset, len) 0 -#endif +static int self_check_not_bad(const struct ubi_device *ubi, int pnum); +static int self_check_peb_ec_hdr(const struct ubi_device *ubi, int pnum); +static int self_check_ec_hdr(const struct ubi_device *ubi, int pnum, + const struct ubi_ec_hdr *ec_hdr); +static int self_check_peb_vid_hdr(const struct ubi_device *ubi, int pnum); +static int self_check_vid_hdr(const struct ubi_device *ubi, int pnum, + const struct ubi_vid_hdr *vid_hdr); +static int self_check_write(struct ubi_device *ubi, const void *buf, int pnum, + int offset, int len); /** * ubi_io_read - read data from a physical eraseblock. @@ -136,51 +128,77 @@ int ubi_io_read(const struct ubi_device *ubi, void *buf, int pnum, int offset, ubi_assert(offset >= 0 && offset + len <= ubi->peb_size); ubi_assert(len > 0); - err = paranoid_check_not_bad(ubi, pnum); + err = self_check_not_bad(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; + return err; + + /* + * Deliberately corrupt the buffer to improve robustness. Indeed, if we + * do not do this, the following may happen: + * 1. The buffer contains data from previous operation, e.g., read from + * another PEB previously. The data looks like expected, e.g., if we + * just do not read anything and return - the caller would not + * notice this. E.g., if we are reading a VID header, the buffer may + * contain a valid VID header from another PEB. + * 2. The driver is buggy and returns us success or -EBADMSG or + * -EUCLEAN, but it does not actually put any data to the buffer. + * + * This may confuse UBI or upper layers - they may think the buffer + * contains valid data while in fact it is just old data. This is + * especially possible because UBI (and UBIFS) relies on CRC, and + * treats data as correct even in case of ECC errors if the CRC is + * correct. + * + * Try to prevent this situation by changing the first byte of the + * buffer. + */ + *((uint8_t *)buf) ^= 0xFF; addr = (loff_t)pnum * ubi->peb_size + offset; retry: err = mtd_read(ubi->mtd, addr, len, &read, buf); if (err) { - if (err == -EUCLEAN) { + const char *errstr = mtd_is_eccerr(err) ? " (ECC error)" : ""; + + if (mtd_is_bitflip(err)) { /* * -EUCLEAN is reported if there was a bit-flip which * was corrected, so this is harmless. + * + * We do not report about it here unless debugging is + * enabled. A corresponding message will be printed + * later, when it is has been scrubbed. */ ubi_msg("fixable bit-flip detected at PEB %d", pnum); ubi_assert(len == read); return UBI_IO_BITFLIPS; } - if (read != len && retries++ < UBI_IO_RETRIES) { - dbg_io("error %d while reading %d bytes from PEB %d:%d, " - "read only %zd bytes, retry", - err, len, pnum, offset, read); + if (retries++ < UBI_IO_RETRIES) { + ubi_warn("error %d%s while reading %d bytes from PEB %d:%d, read only %zd bytes, retry", + err, errstr, len, pnum, offset, read); yield(); goto retry; } - ubi_err("error %d while reading %d bytes from PEB %d:%d, " - "read %zd bytes", err, len, pnum, offset, read); - ubi_dbg_dump_stack(); + ubi_err("error %d%s while reading %d bytes from PEB %d:%d, read %zd bytes", + err, errstr, len, pnum, offset, read); + dump_stack(); /* * The driver should never return -EBADMSG if it failed to read * all the requested data. But some buggy drivers might do * this, so we change it to -EIO. */ - if (read != len && err == -EBADMSG) { + if (read != len && mtd_is_eccerr(err)) { ubi_assert(0); - printk("%s[%d] not here\n", __func__, __LINE__); -/* err = -EIO; */ + err = -EIO; } } else { ubi_assert(len == read); - if (ubi_dbg_is_bitflip()) { - dbg_msg("bit-flip (emulated)"); + if (ubi_dbg_is_bitflip(ubi)) { + dbg_gen("bit-flip (emulated)"); err = UBI_IO_BITFLIPS; } } @@ -224,46 +242,60 @@ int ubi_io_write(struct ubi_device *ubi, const void *buf, int pnum, int offset, return -EROFS; } - /* The below has to be compiled out if paranoid checks are disabled */ - - err = paranoid_check_not_bad(ubi, pnum); + err = self_check_not_bad(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; + return err; /* The area we are writing to has to contain all 0xFF bytes */ - err = paranoid_check_all_ff(ubi, pnum, offset, len); + err = ubi_self_check_all_ff(ubi, pnum, offset, len); if (err) - return err > 0 ? -EINVAL : err; + return err; if (offset >= ubi->leb_start) { /* * We write to the data area of the physical eraseblock. Make * sure it has valid EC and VID headers. */ - err = paranoid_check_peb_ec_hdr(ubi, pnum); + err = self_check_peb_ec_hdr(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; - err = paranoid_check_peb_vid_hdr(ubi, pnum); + return err; + err = self_check_peb_vid_hdr(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; + return err; } - if (ubi_dbg_is_write_failure()) { - dbg_err("cannot write %d bytes to PEB %d:%d " - "(emulated)", len, pnum, offset); - ubi_dbg_dump_stack(); + if (ubi_dbg_is_write_failure(ubi)) { + ubi_err("cannot write %d bytes to PEB %d:%d (emulated)", + len, pnum, offset); + dump_stack(); return -EIO; } addr = (loff_t)pnum * ubi->peb_size + offset; err = mtd_write(ubi->mtd, addr, len, &written, buf); if (err) { - ubi_err("error %d while writing %d bytes to PEB %d:%d, written" - " %zd bytes", err, len, pnum, offset, written); - ubi_dbg_dump_stack(); + ubi_err("error %d while writing %d bytes to PEB %d:%d, written %zd bytes", + err, len, pnum, offset, written); + dump_stack(); + ubi_dump_flash(ubi, pnum, offset, len); } else ubi_assert(written == len); + if (!err) { + err = self_check_write(ubi, buf, pnum, offset, len); + if (err) + return err; + + /* + * Since we always write sequentially, the rest of the PEB has + * to contain only 0xFF bytes. + */ + offset += len; + len = ubi->peb_size - offset; + if (len) + err = ubi_self_check_all_ff(ubi, pnum, offset, len); + } + return err; } @@ -295,6 +327,12 @@ static int do_sync_erase(struct ubi_device *ubi, int pnum) wait_queue_head_t wq; dbg_io("erase PEB %d", pnum); + ubi_assert(pnum >= 0 && pnum < ubi->peb_count); + + if (ubi->ro_mode) { + ubi_err("read-only mode"); + return -EROFS; + } retry: init_waitqueue_head(&wq); @@ -309,13 +347,13 @@ retry: err = mtd_erase(ubi->mtd, &ei); if (err) { if (retries++ < UBI_IO_RETRIES) { - dbg_io("error %d while erasing PEB %d, retry", - err, pnum); + ubi_warn("error %d while erasing PEB %d, retry", + err, pnum); yield(); goto retry; } ubi_err("cannot erase PEB %d, error %d", pnum, err); - ubi_dbg_dump_stack(); + dump_stack(); return err; } @@ -328,46 +366,27 @@ retry: if (ei.state == MTD_ERASE_FAILED) { if (retries++ < UBI_IO_RETRIES) { - dbg_io("error while erasing PEB %d, retry", pnum); + ubi_warn("error while erasing PEB %d, retry", pnum); yield(); goto retry; } ubi_err("cannot erase PEB %d", pnum); - ubi_dbg_dump_stack(); + dump_stack(); return -EIO; } - err = paranoid_check_all_ff(ubi, pnum, 0, ubi->peb_size); + err = ubi_self_check_all_ff(ubi, pnum, 0, ubi->peb_size); if (err) - return err > 0 ? -EINVAL : err; + return err; - if (ubi_dbg_is_erase_failure() && !err) { - dbg_err("cannot erase PEB %d (emulated)", pnum); + if (ubi_dbg_is_erase_failure(ubi)) { + ubi_err("cannot erase PEB %d (emulated)", pnum); return -EIO; } return 0; } -/** - * check_pattern - check if buffer contains only a certain byte pattern. - * @buf: buffer to check - * @patt: the pattern to check - * @size: buffer size in bytes - * - * This function returns %1 in there are only @patt bytes in @buf, and %0 if - * something else was also found. - */ -static int check_pattern(const void *buf, uint8_t patt, int size) -{ - int i; - - for (i = 0; i < size; i++) - if (((const uint8_t *)buf)[i] != patt) - return 0; - return 1; -} - /* Patterns to write to a physical eraseblock when torturing it */ static uint8_t patterns[] = {0xa5, 0x5a, 0x0}; @@ -384,6 +403,7 @@ static int torture_peb(struct ubi_device *ubi, int pnum) { int err, i, patt_count; + ubi_msg("run torture test for PEB %d", pnum); patt_count = ARRAY_SIZE(patterns); ubi_assert(patt_count > 0); @@ -394,11 +414,11 @@ static int torture_peb(struct ubi_device *ubi, int pnum) goto out; /* Make sure the PEB contains only 0xFF bytes */ - err = ubi_io_read(ubi, ubi->peb_buf1, pnum, 0, ubi->peb_size); + err = ubi_io_read(ubi, ubi->peb_buf, pnum, 0, ubi->peb_size); if (err) goto out; - err = check_pattern(ubi->peb_buf1, 0xFF, ubi->peb_size); + err = ubi_check_pattern(ubi->peb_buf, 0xFF, ubi->peb_size); if (err == 0) { ubi_err("erased PEB %d, but a non-0xFF byte found", pnum); @@ -407,17 +427,18 @@ static int torture_peb(struct ubi_device *ubi, int pnum) } /* Write a pattern and check it */ - memset(ubi->peb_buf1, patterns[i], ubi->peb_size); - err = ubi_io_write(ubi, ubi->peb_buf1, pnum, 0, ubi->peb_size); + memset(ubi->peb_buf, patterns[i], ubi->peb_size); + err = ubi_io_write(ubi, ubi->peb_buf, pnum, 0, ubi->peb_size); if (err) goto out; - memset(ubi->peb_buf1, ~patterns[i], ubi->peb_size); - err = ubi_io_read(ubi, ubi->peb_buf1, pnum, 0, ubi->peb_size); + memset(ubi->peb_buf, ~patterns[i], ubi->peb_size); + err = ubi_io_read(ubi, ubi->peb_buf, pnum, 0, ubi->peb_size); if (err) goto out; - err = check_pattern(ubi->peb_buf1, patterns[i], ubi->peb_size); + err = ubi_check_pattern(ubi->peb_buf, patterns[i], + ubi->peb_size); if (err == 0) { ubi_err("pattern %x checking failed for PEB %d", patterns[i], pnum); @@ -427,10 +448,11 @@ static int torture_peb(struct ubi_device *ubi, int pnum) } err = patt_count; + ubi_msg("PEB %d passed torture test, do not mark it as bad", pnum); out: mutex_unlock(&ubi->buf_mutex); - if (err == UBI_IO_BITFLIPS || err == -EBADMSG) { + if (err == UBI_IO_BITFLIPS || mtd_is_eccerr(err)) { /* * If a bit-flip or data integrity error was detected, the test * has not passed because it happened on a freshly erased @@ -443,6 +465,80 @@ out: return err; } +/** + * nor_erase_prepare - prepare a NOR flash PEB for erasure. + * @ubi: UBI device description object + * @pnum: physical eraseblock number to prepare + * + * NOR flash, or at least some of them, have peculiar embedded PEB erasure + * algorithm: the PEB is first filled with zeroes, then it is erased. And + * filling with zeroes starts from the end of the PEB. This was observed with + * Spansion S29GL512N NOR flash. + * + * This means that in case of a power cut we may end up with intact data at the + * beginning of the PEB, and all zeroes at the end of PEB. In other words, the + * EC and VID headers are OK, but a large chunk of data at the end of PEB is + * zeroed. This makes UBI mistakenly treat this PEB as used and associate it + * with an LEB, which leads to subsequent failures (e.g., UBIFS fails). + * + * This function is called before erasing NOR PEBs and it zeroes out EC and VID + * magic numbers in order to invalidate them and prevent the failures. Returns + * zero in case of success and a negative error code in case of failure. + */ +static int nor_erase_prepare(struct ubi_device *ubi, int pnum) +{ + int err; + size_t written; + loff_t addr; + uint32_t data = 0; + struct ubi_ec_hdr ec_hdr; + + /* + * Note, we cannot generally define VID header buffers on stack, + * because of the way we deal with these buffers (see the header + * comment in this file). But we know this is a NOR-specific piece of + * code, so we can do this. But yes, this is error-prone and we should + * (pre-)allocate VID header buffer instead. + */ + struct ubi_vid_hdr vid_hdr; + + /* + * If VID or EC is valid, we have to corrupt them before erasing. + * It is important to first invalidate the EC header, and then the VID + * header. Otherwise a power cut may lead to valid EC header and + * invalid VID header, in which case UBI will treat this PEB as + * corrupted and will try to preserve it, and print scary warnings. + */ + addr = (loff_t)pnum * ubi->peb_size; + err = ubi_io_read_ec_hdr(ubi, pnum, &ec_hdr, 0); + if (err != UBI_IO_BAD_HDR_EBADMSG && err != UBI_IO_BAD_HDR && + err != UBI_IO_FF){ + err = mtd_write(ubi->mtd, addr, 4, &written, (void *)&data); + if(err) + goto error; + } + + err = ubi_io_read_vid_hdr(ubi, pnum, &vid_hdr, 0); + if (err != UBI_IO_BAD_HDR_EBADMSG && err != UBI_IO_BAD_HDR && + err != UBI_IO_FF){ + addr += ubi->vid_hdr_aloffset; + err = mtd_write(ubi->mtd, addr, 4, &written, (void *)&data); + if (err) + goto error; + } + return 0; + +error: + /* + * The PEB contains a valid VID or EC header, but we cannot invalidate + * it. Supposedly the flash media or the driver is screwed up, so + * return an error. + */ + ubi_err("cannot invalidate PEB %d, write returned %d", pnum, err); + ubi_dump_flash(ubi, pnum, 0, ubi->peb_size); + return -EIO; +} + /** * ubi_io_sync_erase - synchronously erase a physical eraseblock. * @ubi: UBI device description object @@ -452,7 +548,7 @@ out: * This function synchronously erases physical eraseblock @pnum. If @torture * flag is not zero, the physical eraseblock is checked by means of writing * different patterns to it and reading them back. If the torturing is enabled, - * the physical eraseblock is erased more then once. + * the physical eraseblock is erased more than once. * * This function returns the number of erasures made in case of success, %-EIO * if the erasure failed or the torturing test failed, and other negative error @@ -465,15 +561,21 @@ int ubi_io_sync_erase(struct ubi_device *ubi, int pnum, int torture) ubi_assert(pnum >= 0 && pnum < ubi->peb_count); - err = paranoid_check_not_bad(ubi, pnum); + err = self_check_not_bad(ubi, pnum); if (err != 0) - return err > 0 ? -EINVAL : err; + return err; if (ubi->ro_mode) { ubi_err("read-only mode"); return -EROFS; } + if (ubi->nor_flash) { + err = nor_erase_prepare(ubi, pnum); + if (err) + return err; + } + if (torture) { ret = torture_peb(ubi, pnum); if (ret < 0) @@ -564,8 +666,7 @@ static int validate_ec_hdr(const struct ubi_device *ubi, leb_start = be32_to_cpu(ec_hdr->data_offset); if (ec_hdr->version != UBI_VERSION) { - ubi_err("node with incompatible UBI version found: " - "this UBI version is %d, image version is %d", + ubi_err("node with incompatible UBI version found: this UBI version is %d, image version is %d", UBI_VERSION, (int)ec_hdr->version); goto bad; } @@ -591,8 +692,8 @@ static int validate_ec_hdr(const struct ubi_device *ubi, bad: ubi_err("bad EC header"); - ubi_dbg_dump_ec_hdr(ec_hdr); - ubi_dbg_dump_stack(); + ubi_dump_ec_hdr(ec_hdr); + dump_stack(); return 1; } @@ -612,67 +713,58 @@ bad: * o %UBI_IO_BITFLIPS if the CRC is correct, but bit-flips were detected * and corrected by the flash driver; this is harmless but may indicate that * this eraseblock may become bad soon (but may be not); - * o %UBI_IO_BAD_EC_HDR if the erase counter header is corrupted (a CRC error); - * o %UBI_IO_PEB_EMPTY if the physical eraseblock is empty; + * o %UBI_IO_BAD_HDR if the erase counter header is corrupted (a CRC error); + * o %UBI_IO_BAD_HDR_EBADMSG is the same as %UBI_IO_BAD_HDR, but there also was + * a data integrity error (uncorrectable ECC error in case of NAND); + * o %UBI_IO_FF if only 0xFF bytes were read (the PEB is supposedly empty) * o a negative error code in case of failure. */ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum, struct ubi_ec_hdr *ec_hdr, int verbose) { - int err, read_err = 0; + int err, read_err; uint32_t crc, magic, hdr_crc; dbg_io("read EC header from PEB %d", pnum); ubi_assert(pnum >= 0 && pnum < ubi->peb_count); - if (UBI_IO_DEBUG) - verbose = 1; - err = ubi_io_read(ubi, ec_hdr, pnum, 0, UBI_EC_HDR_SIZE); - if (err) { - if (err != UBI_IO_BITFLIPS && err != -EBADMSG) - return err; + read_err = ubi_io_read(ubi, ec_hdr, pnum, 0, UBI_EC_HDR_SIZE); + if (read_err) { + if (read_err != UBI_IO_BITFLIPS && !mtd_is_eccerr(read_err)) + return read_err; /* * We read all the data, but either a correctable bit-flip - * occurred, or MTD reported about some data integrity error, - * like an ECC error in case of NAND. The former is harmless, - * the later may mean that the read data is corrupted. But we - * have a CRC check-sum and we will detect this. If the EC - * header is still OK, we just report this as there was a - * bit-flip. + * occurred, or MTD reported a data integrity error + * (uncorrectable ECC error in case of NAND). The former is + * harmless, the later may mean that the read data is + * corrupted. But we have a CRC check-sum and we will detect + * this. If the EC header is still OK, we just report this as + * there was a bit-flip, to force scrubbing. */ - read_err = err; } magic = be32_to_cpu(ec_hdr->magic); if (magic != UBI_EC_HDR_MAGIC) { + if (mtd_is_eccerr(read_err)) + return UBI_IO_BAD_HDR_EBADMSG; + /* * The magic field is wrong. Let's check if we have read all * 0xFF. If yes, this physical eraseblock is assumed to be * empty. - * - * But if there was a read error, we do not test it for all - * 0xFFs. Even if it does contain all 0xFFs, this error - * indicates that something is still wrong with this physical - * eraseblock and we anyway cannot treat it as empty. */ - if (read_err != -EBADMSG && - check_pattern(ec_hdr, 0xFF, UBI_EC_HDR_SIZE)) { + if (ubi_check_pattern(ec_hdr, 0xFF, UBI_EC_HDR_SIZE)) { /* The physical eraseblock is supposedly empty */ - - /* - * The below is just a paranoid check, it has to be - * compiled out if paranoid checks are disabled. - */ - err = paranoid_check_all_ff(ubi, pnum, 0, - ubi->peb_size); - if (err) - return err > 0 ? UBI_IO_BAD_EC_HDR : err; - if (verbose) - ubi_warn("no EC header found at PEB %d, " - "only 0xFF bytes", pnum); - return UBI_IO_PEB_EMPTY; + ubi_warn("no EC header found at PEB %d, only 0xFF bytes", + pnum); + dbg_bld("no EC header found at PEB %d, only 0xFF bytes", + pnum); + if (!read_err) + return UBI_IO_FF; + else + return UBI_IO_FF_BITFLIPS; } /* @@ -680,11 +772,13 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum, * 0xFF bytes. Report that the header is corrupted. */ if (verbose) { - ubi_warn("bad magic number at PEB %d: %08x instead of " - "%08x", pnum, magic, UBI_EC_HDR_MAGIC); - ubi_dbg_dump_ec_hdr(ec_hdr); + ubi_warn("bad magic number at PEB %d: %08x instead of %08x", + pnum, magic, UBI_EC_HDR_MAGIC); + ubi_dump_ec_hdr(ec_hdr); } - return UBI_IO_BAD_EC_HDR; + dbg_bld("bad magic number at PEB %d: %08x instead of %08x", + pnum, magic, UBI_EC_HDR_MAGIC); + return UBI_IO_BAD_HDR; } crc = crc32(UBI_CRC32_INIT, ec_hdr, UBI_EC_HDR_SIZE_CRC); @@ -692,11 +786,17 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum, if (hdr_crc != crc) { if (verbose) { - ubi_warn("bad EC header CRC at PEB %d, calculated %#08x," - " read %#08x", pnum, crc, hdr_crc); - ubi_dbg_dump_ec_hdr(ec_hdr); + ubi_warn("bad EC header CRC at PEB %d, calculated %#08x, read %#08x", + pnum, crc, hdr_crc); + ubi_dump_ec_hdr(ec_hdr); } - return UBI_IO_BAD_EC_HDR; + dbg_bld("bad EC header CRC at PEB %d, calculated %#08x, read %#08x", + pnum, crc, hdr_crc); + + if (!read_err) + return UBI_IO_BAD_HDR; + else + return UBI_IO_BAD_HDR_EBADMSG; } /* And of course validate what has just been read from the media */ @@ -706,6 +806,10 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum, return -EINVAL; } + /* + * If there was %-EBADMSG, but the header CRC is still OK, report about + * a bit-flip to force scrubbing on this PEB. + */ return read_err ? UBI_IO_BITFLIPS : 0; } @@ -737,12 +841,13 @@ int ubi_io_write_ec_hdr(struct ubi_device *ubi, int pnum, ec_hdr->version = UBI_VERSION; ec_hdr->vid_hdr_offset = cpu_to_be32(ubi->vid_hdr_offset); ec_hdr->data_offset = cpu_to_be32(ubi->leb_start); + ec_hdr->image_seq = cpu_to_be32(ubi->image_seq); crc = crc32(UBI_CRC32_INIT, ec_hdr, UBI_EC_HDR_SIZE_CRC); ec_hdr->hdr_crc = cpu_to_be32(crc); - err = paranoid_check_ec_hdr(ubi, pnum, ec_hdr); + err = self_check_ec_hdr(ubi, pnum, ec_hdr); if (err) - return -EINVAL; + return err; err = ubi_io_write(ubi, ec_hdr, pnum, 0, ubi->ec_hdr_alsize); return err; @@ -771,40 +876,40 @@ static int validate_vid_hdr(const struct ubi_device *ubi, int usable_leb_size = ubi->leb_size - data_pad; if (copy_flag != 0 && copy_flag != 1) { - dbg_err("bad copy_flag"); + ubi_err("bad copy_flag"); goto bad; } if (vol_id < 0 || lnum < 0 || data_size < 0 || used_ebs < 0 || data_pad < 0) { - dbg_err("negative values"); + ubi_err("negative values"); goto bad; } if (vol_id >= UBI_MAX_VOLUMES && vol_id < UBI_INTERNAL_VOL_START) { - dbg_err("bad vol_id"); + ubi_err("bad vol_id"); goto bad; } if (vol_id < UBI_INTERNAL_VOL_START && compat != 0) { - dbg_err("bad compat"); + ubi_err("bad compat"); goto bad; } if (vol_id >= UBI_INTERNAL_VOL_START && compat != UBI_COMPAT_DELETE && compat != UBI_COMPAT_RO && compat != UBI_COMPAT_PRESERVE && compat != UBI_COMPAT_REJECT) { - dbg_err("bad compat"); + ubi_err("bad compat"); goto bad; } if (vol_type != UBI_VID_DYNAMIC && vol_type != UBI_VID_STATIC) { - dbg_err("bad vol_type"); + ubi_err("bad vol_type"); goto bad; } if (data_pad >= ubi->leb_size / 2) { - dbg_err("bad data_pad"); + ubi_err("bad data_pad"); goto bad; } @@ -816,45 +921,45 @@ static int validate_vid_hdr(const struct ubi_device *ubi, * mapped logical eraseblocks. */ if (used_ebs == 0) { - dbg_err("zero used_ebs"); + ubi_err("zero used_ebs"); goto bad; } if (data_size == 0) { - dbg_err("zero data_size"); + ubi_err("zero data_size"); goto bad; } if (lnum < used_ebs - 1) { if (data_size != usable_leb_size) { - dbg_err("bad data_size"); + ubi_err("bad data_size"); goto bad; } } else if (lnum == used_ebs - 1) { if (data_size == 0) { - dbg_err("bad data_size at last LEB"); + ubi_err("bad data_size at last LEB"); goto bad; } } else { - dbg_err("too high lnum"); + ubi_err("too high lnum"); goto bad; } } else { if (copy_flag == 0) { if (data_crc != 0) { - dbg_err("non-zero data CRC"); + ubi_err("non-zero data CRC"); goto bad; } if (data_size != 0) { - dbg_err("non-zero data_size"); + ubi_err("non-zero data_size"); goto bad; } } else { if (data_size == 0) { - dbg_err("zero data_size of copy"); + ubi_err("zero data_size of copy"); goto bad; } } if (used_ebs != 0) { - dbg_err("bad used_ebs"); + ubi_err("bad used_ebs"); goto bad; } } @@ -863,8 +968,8 @@ static int validate_vid_hdr(const struct ubi_device *ubi, bad: ubi_err("bad VID header"); - ubi_dbg_dump_vid_hdr(vid_hdr); - ubi_dbg_dump_stack(); + ubi_dump_vid_hdr(vid_hdr); + dump_stack(); return 1; } @@ -878,88 +983,53 @@ bad: * * This function reads the volume identifier header from physical eraseblock * @pnum and stores it in @vid_hdr. It also checks CRC checksum of the read - * volume identifier header. The following codes may be returned: + * volume identifier header. The error codes are the same as in + * 'ubi_io_read_ec_hdr()'. * - * o %0 if the CRC checksum is correct and the header was successfully read; - * o %UBI_IO_BITFLIPS if the CRC is correct, but bit-flips were detected - * and corrected by the flash driver; this is harmless but may indicate that - * this eraseblock may become bad soon; - * o %UBI_IO_BAD_VID_HRD if the volume identifier header is corrupted (a CRC - * error detected); - * o %UBI_IO_PEB_FREE if the physical eraseblock is free (i.e., there is no VID - * header there); - * o a negative error code in case of failure. + * Note, the implementation of this function is also very similar to + * 'ubi_io_read_ec_hdr()', so refer commentaries in 'ubi_io_read_ec_hdr()'. */ int ubi_io_read_vid_hdr(struct ubi_device *ubi, int pnum, struct ubi_vid_hdr *vid_hdr, int verbose) { - int err, read_err = 0; + int err, read_err; uint32_t crc, magic, hdr_crc; void *p; dbg_io("read VID header from PEB %d", pnum); ubi_assert(pnum >= 0 && pnum < ubi->peb_count); - if (UBI_IO_DEBUG) - verbose = 1; p = (char *)vid_hdr - ubi->vid_hdr_shift; - err = ubi_io_read(ubi, p, pnum, ubi->vid_hdr_aloffset, + read_err = ubi_io_read(ubi, p, pnum, ubi->vid_hdr_aloffset, ubi->vid_hdr_alsize); - if (err) { - if (err != UBI_IO_BITFLIPS && err != -EBADMSG) - return err; - - /* - * We read all the data, but either a correctable bit-flip - * occurred, or MTD reported about some data integrity error, - * like an ECC error in case of NAND. The former is harmless, - * the later may mean the read data is corrupted. But we have a - * CRC check-sum and we will identify this. If the VID header is - * still OK, we just report this as there was a bit-flip. - */ - read_err = err; - } + if (read_err && read_err != UBI_IO_BITFLIPS && !mtd_is_eccerr(read_err)) + return read_err; magic = be32_to_cpu(vid_hdr->magic); if (magic != UBI_VID_HDR_MAGIC) { - /* - * If we have read all 0xFF bytes, the VID header probably does - * not exist and the physical eraseblock is assumed to be free. - * - * But if there was a read error, we do not test the data for - * 0xFFs. Even if it does contain all 0xFFs, this error - * indicates that something is still wrong with this physical - * eraseblock and it cannot be regarded as free. - */ - if (read_err != -EBADMSG && - check_pattern(vid_hdr, 0xFF, UBI_VID_HDR_SIZE)) { - /* The physical eraseblock is supposedly free */ - - /* - * The below is just a paranoid check, it has to be - * compiled out if paranoid checks are disabled. - */ - err = paranoid_check_all_ff(ubi, pnum, ubi->leb_start, - ubi->leb_size); - if (err) - return err > 0 ? UBI_IO_BAD_VID_HDR : err; + if (mtd_is_eccerr(read_err)) + return UBI_IO_BAD_HDR_EBADMSG; + if (ubi_check_pattern(vid_hdr, 0xFF, UBI_VID_HDR_SIZE)) { if (verbose) - ubi_warn("no VID header found at PEB %d, " - "only 0xFF bytes", pnum); - return UBI_IO_PEB_FREE; + ubi_warn("no VID header found at PEB %d, only 0xFF bytes", + pnum); + dbg_bld("no VID header found at PEB %d, only 0xFF bytes", + pnum); + if (!read_err) + return UBI_IO_FF; + else + return UBI_IO_FF_BITFLIPS; } - /* - * This is not a valid VID header, and these are not 0xFF - * bytes. Report that the header is corrupted. - */ if (verbose) { - ubi_warn("bad magic number at PEB %d: %08x instead of " - "%08x", pnum, magic, UBI_VID_HDR_MAGIC); - ubi_dbg_dump_vid_hdr(vid_hdr); + ubi_warn("bad magic number at PEB %d: %08x instead of %08x", + pnum, magic, UBI_VID_HDR_MAGIC); + ubi_dump_vid_hdr(vid_hdr); } - return UBI_IO_BAD_VID_HDR; + dbg_bld("bad magic number at PEB %d: %08x instead of %08x", + pnum, magic, UBI_VID_HDR_MAGIC); + return UBI_IO_BAD_HDR; } crc = crc32(UBI_CRC32_INIT, vid_hdr, UBI_VID_HDR_SIZE_CRC); @@ -967,14 +1037,18 @@ int ubi_io_read_vid_hdr(struct ubi_device *ubi, int pnum, if (hdr_crc != crc) { if (verbose) { - ubi_warn("bad CRC at PEB %d, calculated %#08x, " - "read %#08x", pnum, crc, hdr_crc); - ubi_dbg_dump_vid_hdr(vid_hdr); + ubi_warn("bad CRC at PEB %d, calculated %#08x, read %#08x", + pnum, crc, hdr_crc); + ubi_dump_vid_hdr(vid_hdr); } - return UBI_IO_BAD_VID_HDR; + dbg_bld("bad CRC at PEB %d, calculated %#08x, read %#08x", + pnum, crc, hdr_crc); + if (!read_err) + return UBI_IO_BAD_HDR; + else + return UBI_IO_BAD_HDR_EBADMSG; } - /* Validate the VID header that we have just read */ err = validate_vid_hdr(ubi, vid_hdr); if (err) { ubi_err("validation failed for PEB %d", pnum); @@ -1009,18 +1083,18 @@ int ubi_io_write_vid_hdr(struct ubi_device *ubi, int pnum, dbg_io("write VID header to PEB %d", pnum); ubi_assert(pnum >= 0 && pnum < ubi->peb_count); - err = paranoid_check_peb_ec_hdr(ubi, pnum); + err = self_check_peb_ec_hdr(ubi, pnum); if (err) - return err > 0 ? -EINVAL: err; + return err; vid_hdr->magic = cpu_to_be32(UBI_VID_HDR_MAGIC); vid_hdr->version = UBI_VERSION; crc = crc32(UBI_CRC32_INIT, vid_hdr, UBI_VID_HDR_SIZE_CRC); vid_hdr->hdr_crc = cpu_to_be32(crc); - err = paranoid_check_vid_hdr(ubi, pnum, vid_hdr); + err = self_check_vid_hdr(ubi, pnum, vid_hdr); if (err) - return -EINVAL; + return err; p = (char *)vid_hdr - ubi->vid_hdr_shift; err = ubi_io_write(ubi, p, pnum, ubi->vid_hdr_aloffset, @@ -1028,44 +1102,48 @@ int ubi_io_write_vid_hdr(struct ubi_device *ubi, int pnum, return err; } -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID - /** - * paranoid_check_not_bad - ensure that a physical eraseblock is not bad. + * self_check_not_bad - ensure that a physical eraseblock is not bad. * @ubi: UBI device description object * @pnum: physical eraseblock number to check * - * This function returns zero if the physical eraseblock is good, a positive - * number if it is bad and a negative error code if an error occurred. + * This function returns zero if the physical eraseblock is good, %-EINVAL if + * it is bad and a negative error code if an error occurred. */ -static int paranoid_check_not_bad(const struct ubi_device *ubi, int pnum) +static int self_check_not_bad(const struct ubi_device *ubi, int pnum) { int err; + if (!ubi_dbg_chk_io(ubi)) + return 0; + err = ubi_io_is_bad(ubi, pnum); if (!err) return err; - ubi_err("paranoid check failed for PEB %d", pnum); - ubi_dbg_dump_stack(); - return err; + ubi_err("self-check failed for PEB %d", pnum); + dump_stack(); + return err > 0 ? -EINVAL : err; } /** - * paranoid_check_ec_hdr - check if an erase counter header is all right. + * self_check_ec_hdr - check if an erase counter header is all right. * @ubi: UBI device description object * @pnum: physical eraseblock number the erase counter header belongs to * @ec_hdr: the erase counter header to check * * This function returns zero if the erase counter header contains valid - * values, and %1 if not. + * values, and %-EINVAL if not. */ -static int paranoid_check_ec_hdr(const struct ubi_device *ubi, int pnum, - const struct ubi_ec_hdr *ec_hdr) +static int self_check_ec_hdr(const struct ubi_device *ubi, int pnum, + const struct ubi_ec_hdr *ec_hdr) { int err; uint32_t magic; + if (!ubi_dbg_chk_io(ubi)) + return 0; + magic = be32_to_cpu(ec_hdr->magic); if (magic != UBI_EC_HDR_MAGIC) { ubi_err("bad magic %#08x, must be %#08x", @@ -1075,53 +1153,55 @@ static int paranoid_check_ec_hdr(const struct ubi_device *ubi, int pnum, err = validate_ec_hdr(ubi, ec_hdr); if (err) { - ubi_err("paranoid check failed for PEB %d", pnum); + ubi_err("self-check failed for PEB %d", pnum); goto fail; } return 0; fail: - ubi_dbg_dump_ec_hdr(ec_hdr); - ubi_dbg_dump_stack(); - return 1; + ubi_dump_ec_hdr(ec_hdr); + dump_stack(); + return -EINVAL; } /** - * paranoid_check_peb_ec_hdr - check that the erase counter header of a - * physical eraseblock is in-place and is all right. + * self_check_peb_ec_hdr - check erase counter header. * @ubi: UBI device description object * @pnum: the physical eraseblock number to check * - * This function returns zero if the erase counter header is all right, %1 if - * not, and a negative error code if an error occurred. + * This function returns zero if the erase counter header is all right and and + * a negative error code if not or if an error occurred. */ -static int paranoid_check_peb_ec_hdr(const struct ubi_device *ubi, int pnum) +static int self_check_peb_ec_hdr(const struct ubi_device *ubi, int pnum) { int err; uint32_t crc, hdr_crc; struct ubi_ec_hdr *ec_hdr; + if (!ubi_dbg_chk_io(ubi)) + return 0; + ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_NOFS); if (!ec_hdr) return -ENOMEM; err = ubi_io_read(ubi, ec_hdr, pnum, 0, UBI_EC_HDR_SIZE); - if (err && err != UBI_IO_BITFLIPS && err != -EBADMSG) + if (err && err != UBI_IO_BITFLIPS && !mtd_is_eccerr(err)) goto exit; crc = crc32(UBI_CRC32_INIT, ec_hdr, UBI_EC_HDR_SIZE_CRC); hdr_crc = be32_to_cpu(ec_hdr->hdr_crc); if (hdr_crc != crc) { ubi_err("bad CRC, calculated %#08x, read %#08x", crc, hdr_crc); - ubi_err("paranoid check failed for PEB %d", pnum); - ubi_dbg_dump_ec_hdr(ec_hdr); - ubi_dbg_dump_stack(); - err = 1; + ubi_err("self-check failed for PEB %d", pnum); + ubi_dump_ec_hdr(ec_hdr); + dump_stack(); + err = -EINVAL; goto exit; } - err = paranoid_check_ec_hdr(ubi, pnum, ec_hdr); + err = self_check_ec_hdr(ubi, pnum, ec_hdr); exit: kfree(ec_hdr); @@ -1129,20 +1209,23 @@ exit: } /** - * paranoid_check_vid_hdr - check that a volume identifier header is all right. + * self_check_vid_hdr - check that a volume identifier header is all right. * @ubi: UBI device description object * @pnum: physical eraseblock number the volume identifier header belongs to * @vid_hdr: the volume identifier header to check * * This function returns zero if the volume identifier header is all right, and - * %1 if not. + * %-EINVAL if not. */ -static int paranoid_check_vid_hdr(const struct ubi_device *ubi, int pnum, - const struct ubi_vid_hdr *vid_hdr) +static int self_check_vid_hdr(const struct ubi_device *ubi, int pnum, + const struct ubi_vid_hdr *vid_hdr) { int err; uint32_t magic; + if (!ubi_dbg_chk_io(ubi)) + return 0; + magic = be32_to_cpu(vid_hdr->magic); if (magic != UBI_VID_HDR_MAGIC) { ubi_err("bad VID header magic %#08x at PEB %d, must be %#08x", @@ -1152,36 +1235,38 @@ static int paranoid_check_vid_hdr(const struct ubi_device *ubi, int pnum, err = validate_vid_hdr(ubi, vid_hdr); if (err) { - ubi_err("paranoid check failed for PEB %d", pnum); + ubi_err("self-check failed for PEB %d", pnum); goto fail; } return err; fail: - ubi_err("paranoid check failed for PEB %d", pnum); - ubi_dbg_dump_vid_hdr(vid_hdr); - ubi_dbg_dump_stack(); - return 1; + ubi_err("self-check failed for PEB %d", pnum); + ubi_dump_vid_hdr(vid_hdr); + dump_stack(); + return -EINVAL; } /** - * paranoid_check_peb_vid_hdr - check that the volume identifier header of a - * physical eraseblock is in-place and is all right. + * self_check_peb_vid_hdr - check volume identifier header. * @ubi: UBI device description object * @pnum: the physical eraseblock number to check * * This function returns zero if the volume identifier header is all right, - * %1 if not, and a negative error code if an error occurred. + * and a negative error code if not or if an error occurred. */ -static int paranoid_check_peb_vid_hdr(const struct ubi_device *ubi, int pnum) +static int self_check_peb_vid_hdr(const struct ubi_device *ubi, int pnum) { int err; uint32_t crc, hdr_crc; struct ubi_vid_hdr *vid_hdr; void *p; + if (!ubi_dbg_chk_io(ubi)) + return 0; + vid_hdr = ubi_zalloc_vid_hdr(ubi, GFP_NOFS); if (!vid_hdr) return -ENOMEM; @@ -1189,22 +1274,22 @@ static int paranoid_check_peb_vid_hdr(const struct ubi_device *ubi, int pnum) p = (char *)vid_hdr - ubi->vid_hdr_shift; err = ubi_io_read(ubi, p, pnum, ubi->vid_hdr_aloffset, ubi->vid_hdr_alsize); - if (err && err != UBI_IO_BITFLIPS && err != -EBADMSG) + if (err && err != UBI_IO_BITFLIPS && !mtd_is_eccerr(err)) goto exit; crc = crc32(UBI_CRC32_INIT, vid_hdr, UBI_EC_HDR_SIZE_CRC); hdr_crc = be32_to_cpu(vid_hdr->hdr_crc); if (hdr_crc != crc) { - ubi_err("bad VID header CRC at PEB %d, calculated %#08x, " - "read %#08x", pnum, crc, hdr_crc); - ubi_err("paranoid check failed for PEB %d", pnum); - ubi_dbg_dump_vid_hdr(vid_hdr); - ubi_dbg_dump_stack(); - err = 1; + ubi_err("bad VID header CRC at PEB %d, calculated %#08x, read %#08x", + pnum, crc, hdr_crc); + ubi_err("self-check failed for PEB %d", pnum); + ubi_dump_vid_hdr(vid_hdr); + dump_stack(); + err = -EINVAL; goto exit; } - err = paranoid_check_vid_hdr(ubi, pnum, vid_hdr); + err = self_check_vid_hdr(ubi, pnum, vid_hdr); exit: ubi_free_vid_hdr(ubi, vid_hdr); @@ -1212,51 +1297,123 @@ exit: } /** - * paranoid_check_all_ff - check that a region of flash is empty. + * self_check_write - make sure write succeeded. + * @ubi: UBI device description object + * @buf: buffer with data which were written + * @pnum: physical eraseblock number the data were written to + * @offset: offset within the physical eraseblock the data were written to + * @len: how many bytes were written + * + * This functions reads data which were recently written and compares it with + * the original data buffer - the data have to match. Returns zero if the data + * match and a negative error code if not or in case of failure. + */ +static int self_check_write(struct ubi_device *ubi, const void *buf, int pnum, + int offset, int len) +{ + int err, i; + size_t read; + void *buf1; + loff_t addr = (loff_t)pnum * ubi->peb_size + offset; + + if (!ubi_dbg_chk_io(ubi)) + return 0; + + buf1 = __vmalloc(len, GFP_NOFS, PAGE_KERNEL); + if (!buf1) { + ubi_err("cannot allocate memory to check writes"); + return 0; + } + + err = mtd_read(ubi->mtd, addr, len, &read, buf1); + if (err && !mtd_is_bitflip(err)) + goto out_free; + + for (i = 0; i < len; i++) { + uint8_t c = ((uint8_t *)buf)[i]; + uint8_t c1 = ((uint8_t *)buf1)[i]; +#if !defined(CONFIG_UBI_SILENCE_MSG) + int dump_len = max_t(int, 128, len - i); +#endif + + if (c == c1) + continue; + + ubi_err("self-check failed for PEB %d:%d, len %d", + pnum, offset, len); + ubi_msg("data differ at position %d", i); + ubi_msg("hex dump of the original buffer from %d to %d", + i, i + dump_len); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + buf + i, dump_len, 1); + ubi_msg("hex dump of the read buffer from %d to %d", + i, i + dump_len); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + buf1 + i, dump_len, 1); + dump_stack(); + err = -EINVAL; + goto out_free; + } + + vfree(buf1); + return 0; + +out_free: + vfree(buf1); + return err; +} + +/** + * ubi_self_check_all_ff - check that a region of flash is empty. * @ubi: UBI device description object * @pnum: the physical eraseblock number to check * @offset: the starting offset within the physical eraseblock to check * @len: the length of the region to check * * This function returns zero if only 0xFF bytes are present at offset - * @offset of the physical eraseblock @pnum, %1 if not, and a negative error - * code if an error occurred. + * @offset of the physical eraseblock @pnum, and a negative error code if not + * or if an error occurred. */ -static int paranoid_check_all_ff(struct ubi_device *ubi, int pnum, int offset, - int len) +int ubi_self_check_all_ff(struct ubi_device *ubi, int pnum, int offset, int len) { size_t read; int err; + void *buf; loff_t addr = (loff_t)pnum * ubi->peb_size + offset; - mutex_lock(&ubi->dbg_buf_mutex); - err = mtd_read(ubi->mtd, addr, len, &read, ubi->dbg_peb_buf); - if (err && err != -EUCLEAN) { - ubi_err("error %d while reading %d bytes from PEB %d:%d, " - "read %zd bytes", err, len, pnum, offset, read); + if (!ubi_dbg_chk_io(ubi)) + return 0; + + buf = __vmalloc(len, GFP_NOFS, PAGE_KERNEL); + if (!buf) { + ubi_err("cannot allocate memory to check for 0xFFs"); + return 0; + } + + err = mtd_read(ubi->mtd, addr, len, &read, buf); + if (err && !mtd_is_bitflip(err)) { + ubi_err("error %d while reading %d bytes from PEB %d:%d, read %zd bytes", + err, len, pnum, offset, read); goto error; } - err = check_pattern(ubi->dbg_peb_buf, 0xFF, len); + err = ubi_check_pattern(buf, 0xFF, len); if (err == 0) { - ubi_err("flash region at PEB %d:%d, length %d does not " - "contain all 0xFF bytes", pnum, offset, len); + ubi_err("flash region at PEB %d:%d, length %d does not contain all 0xFF bytes", + pnum, offset, len); goto fail; } - mutex_unlock(&ubi->dbg_buf_mutex); + vfree(buf); return 0; fail: - ubi_err("paranoid check failed for PEB %d", pnum); - dbg_msg("hex dump of the %d-%d region", offset, offset + len); - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, - ubi->dbg_peb_buf, len, 1); - err = 1; + ubi_err("self-check failed for PEB %d", pnum); + ubi_msg("hex dump of the %d-%d region", offset, offset + len); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, buf, len, 1); + err = -EINVAL; error: - ubi_dbg_dump_stack(); - mutex_unlock(&ubi->dbg_buf_mutex); + dump_stack(); + vfree(buf); return err; } - -#endif /* CONFIG_MTD_UBI_DEBUG_PARANOID */ diff --git a/drivers/mtd/ubi/kapi.c b/drivers/mtd/ubi/kapi.c index 63c56c998e..fd2bbd64f1 100644 --- a/drivers/mtd/ubi/kapi.c +++ b/drivers/mtd/ubi/kapi.c @@ -8,15 +8,41 @@ /* This file mostly implements UBI kernel API functions */ -#ifdef UBI_LINUX +#ifndef __UBOOT__ #include -#include +#include +#include +#include #include +#else +#include #endif +#include -#include #include "ubi.h" +/** + * ubi_do_get_device_info - get information about UBI device. + * @ubi: UBI device description object + * @di: the information is stored here + * + * This function is the same as 'ubi_get_device_info()', but it assumes the UBI + * device is locked and cannot disappear. + */ +void ubi_do_get_device_info(struct ubi_device *ubi, struct ubi_device_info *di) +{ + di->ubi_num = ubi->ubi_num; + di->leb_size = ubi->leb_size; + di->leb_start = ubi->leb_start; + di->min_io_size = ubi->min_io_size; + di->max_write_size = ubi->max_write_size; + di->ro_mode = ubi->ro_mode; +#ifndef __UBOOT__ + di->cdev = ubi->cdev.dev; +#endif +} +EXPORT_SYMBOL_GPL(ubi_do_get_device_info); + /** * ubi_get_device_info - get information about UBI device. * @ubi_num: UBI device number @@ -31,33 +57,24 @@ int ubi_get_device_info(int ubi_num, struct ubi_device_info *di) if (ubi_num < 0 || ubi_num >= UBI_MAX_DEVICES) return -EINVAL; - ubi = ubi_get_device(ubi_num); if (!ubi) return -ENODEV; - - di->ubi_num = ubi->ubi_num; - di->leb_size = ubi->leb_size; - di->min_io_size = ubi->min_io_size; - di->ro_mode = ubi->ro_mode; - di->cdev = ubi->cdev.dev; - + ubi_do_get_device_info(ubi, di); ubi_put_device(ubi); return 0; } EXPORT_SYMBOL_GPL(ubi_get_device_info); /** - * ubi_get_volume_info - get information about UBI volume. - * @desc: volume descriptor + * ubi_do_get_volume_info - get information about UBI volume. + * @ubi: UBI device description object + * @vol: volume description object * @vi: the information is stored here */ -void ubi_get_volume_info(struct ubi_volume_desc *desc, - struct ubi_volume_info *vi) +void ubi_do_get_volume_info(struct ubi_device *ubi, struct ubi_volume *vol, + struct ubi_volume_info *vi) { - const struct ubi_volume *vol = desc->vol; - const struct ubi_device *ubi = vol->ubi; - vi->vol_id = vol->vol_id; vi->ubi_num = ubi->ubi_num; vi->size = vol->reserved_pebs; @@ -71,6 +88,17 @@ void ubi_get_volume_info(struct ubi_volume_desc *desc, vi->name = vol->name; vi->cdev = vol->cdev.dev; } + +/** + * ubi_get_volume_info - get information about UBI volume. + * @desc: volume descriptor + * @vi: the information is stored here + */ +void ubi_get_volume_info(struct ubi_volume_desc *desc, + struct ubi_volume_info *vi) +{ + ubi_do_get_volume_info(desc->vol->ubi, desc->vol, vi); +} EXPORT_SYMBOL_GPL(ubi_get_volume_info); /** @@ -98,7 +126,7 @@ struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode) struct ubi_device *ubi; struct ubi_volume *vol; - dbg_msg("open device %d volume %d, mode %d", ubi_num, vol_id, mode); + dbg_gen("open device %d, volume %d, mode %d", ubi_num, vol_id, mode); if (ubi_num < 0 || ubi_num >= UBI_MAX_DEVICES) return ERR_PTR(-EINVAL); @@ -188,6 +216,8 @@ out_free: kfree(desc); out_put_ubi: ubi_put_device(ubi); + ubi_err("cannot open device %d, volume %d, error %d", + ubi_num, vol_id, err); return ERR_PTR(err); } EXPORT_SYMBOL_GPL(ubi_open_volume); @@ -207,7 +237,7 @@ struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name, struct ubi_device *ubi; struct ubi_volume_desc *ret; - dbg_msg("open volume %s, mode %d", name, mode); + dbg_gen("open device %d, volume %s, mode %d", ubi_num, name, mode); if (!name) return ERR_PTR(-EINVAL); @@ -249,6 +279,45 @@ struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name, } EXPORT_SYMBOL_GPL(ubi_open_volume_nm); +#ifndef __UBOOT__ +/** + * ubi_open_volume_path - open UBI volume by its character device node path. + * @pathname: volume character device node path + * @mode: open mode + * + * This function is similar to 'ubi_open_volume()', but opens a volume the path + * to its character device node. + */ +struct ubi_volume_desc *ubi_open_volume_path(const char *pathname, int mode) +{ + int error, ubi_num, vol_id, mod; + struct inode *inode; + struct path path; + + dbg_gen("open volume %s, mode %d", pathname, mode); + + if (!pathname || !*pathname) + return ERR_PTR(-EINVAL); + + error = kern_path(pathname, LOOKUP_FOLLOW, &path); + if (error) + return ERR_PTR(error); + + inode = path.dentry->d_inode; + mod = inode->i_mode; + ubi_num = ubi_major2num(imajor(inode)); + vol_id = iminor(inode) - 1; + path_put(&path); + + if (!S_ISCHR(mod)) + return ERR_PTR(-EINVAL); + if (vol_id >= 0 && ubi_num >= 0) + return ubi_open_volume(ubi_num, vol_id, mode); + return ERR_PTR(-ENODEV); +} +EXPORT_SYMBOL_GPL(ubi_open_volume_path); +#endif + /** * ubi_close_volume - close UBI volume. * @desc: volume descriptor @@ -258,7 +327,8 @@ void ubi_close_volume(struct ubi_volume_desc *desc) struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; - dbg_msg("close volume %d, mode %d", vol->vol_id, desc->mode); + dbg_gen("close device %d, volume %d, mode %d", + ubi->ubi_num, vol->vol_id, desc->mode); spin_lock(&ubi->volumes_lock); switch (desc->mode) { @@ -315,7 +385,7 @@ int ubi_leb_read(struct ubi_volume_desc *desc, int lnum, char *buf, int offset, struct ubi_device *ubi = vol->ubi; int err, vol_id = vol->vol_id; - dbg_msg("read %d bytes from LEB %d:%d:%d", len, vol_id, lnum, offset); + dbg_gen("read %d bytes from LEB %d:%d:%d", len, vol_id, lnum, offset); if (vol_id < 0 || vol_id >= ubi->vtbl_slots || lnum < 0 || lnum >= vol->used_ebs || offset < 0 || len < 0 || @@ -353,11 +423,9 @@ EXPORT_SYMBOL_GPL(ubi_leb_read); * @buf: data to write * @offset: offset within the logical eraseblock where to write * @len: how many bytes to write - * @dtype: expected data type * * This function writes @len bytes of data from @buf to offset @offset of - * logical eraseblock @lnum. The @dtype argument describes expected lifetime of - * the data. + * logical eraseblock @lnum. * * This function takes care of physical eraseblock write failures. If write to * the physical eraseblock write operation fails, the logical eraseblock is @@ -374,13 +442,13 @@ EXPORT_SYMBOL_GPL(ubi_leb_read); * returns immediately with %-EBADF code. */ int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf, - int offset, int len, int dtype) + int offset, int len) { struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; int vol_id = vol->vol_id; - dbg_msg("write %d bytes to LEB %d:%d:%d", len, vol_id, lnum, offset); + dbg_gen("write %d bytes to LEB %d:%d:%d", len, vol_id, lnum, offset); if (vol_id < 0 || vol_id >= ubi->vtbl_slots) return -EINVAL; @@ -393,17 +461,13 @@ int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf, offset & (ubi->min_io_size - 1) || len & (ubi->min_io_size - 1)) return -EINVAL; - if (dtype != UBI_LONGTERM && dtype != UBI_SHORTTERM && - dtype != UBI_UNKNOWN) - return -EINVAL; - if (vol->upd_marker) return -EBADF; if (len == 0) return 0; - return ubi_eba_write_leb(ubi, vol, lnum, buf, offset, len, dtype); + return ubi_eba_write_leb(ubi, vol, lnum, buf, offset, len); } EXPORT_SYMBOL_GPL(ubi_leb_write); @@ -413,24 +477,23 @@ EXPORT_SYMBOL_GPL(ubi_leb_write); * @lnum: logical eraseblock number to change * @buf: data to write * @len: how many bytes to write - * @dtype: expected data type * * This function changes the contents of a logical eraseblock atomically. @buf * has to contain new logical eraseblock data, and @len - the length of the - * data, which has to be aligned. The length may be shorter then the logical + * data, which has to be aligned. The length may be shorter than the logical * eraseblock size, ant the logical eraseblock may be appended to more times * later on. This function guarantees that in case of an unclean reboot the old * contents is preserved. Returns zero in case of success and a negative error * code in case of failure. */ int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf, - int len, int dtype) + int len) { struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; int vol_id = vol->vol_id; - dbg_msg("atomically write %d bytes to LEB %d:%d", len, vol_id, lnum); + dbg_gen("atomically write %d bytes to LEB %d:%d", len, vol_id, lnum); if (vol_id < 0 || vol_id >= ubi->vtbl_slots) return -EINVAL; @@ -442,17 +505,13 @@ int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf, len > vol->usable_leb_size || len & (ubi->min_io_size - 1)) return -EINVAL; - if (dtype != UBI_LONGTERM && dtype != UBI_SHORTTERM && - dtype != UBI_UNKNOWN) - return -EINVAL; - if (vol->upd_marker) return -EBADF; if (len == 0) return 0; - return ubi_eba_atomic_leb_change(ubi, vol, lnum, buf, len, dtype); + return ubi_eba_atomic_leb_change(ubi, vol, lnum, buf, len); } EXPORT_SYMBOL_GPL(ubi_leb_change); @@ -474,7 +533,7 @@ int ubi_leb_erase(struct ubi_volume_desc *desc, int lnum) struct ubi_device *ubi = vol->ubi; int err; - dbg_msg("erase LEB %d:%d", vol->vol_id, lnum); + dbg_gen("erase LEB %d:%d", vol->vol_id, lnum); if (desc->mode == UBI_READONLY || vol->vol_type == UBI_STATIC_VOLUME) return -EROFS; @@ -489,7 +548,7 @@ int ubi_leb_erase(struct ubi_volume_desc *desc, int lnum) if (err) return err; - return ubi_wl_flush(ubi); + return ubi_wl_flush(ubi, vol->vol_id, lnum); } EXPORT_SYMBOL_GPL(ubi_leb_erase); @@ -500,7 +559,7 @@ EXPORT_SYMBOL_GPL(ubi_leb_erase); * * This function un-maps logical eraseblock @lnum and schedules the * corresponding physical eraseblock for erasure, so that it will eventually be - * physically erased in background. This operation is much faster then the + * physically erased in background. This operation is much faster than the * erase operation. * * Unlike erase, the un-map operation does not guarantee that the logical @@ -519,7 +578,7 @@ EXPORT_SYMBOL_GPL(ubi_leb_erase); * * The main and obvious use-case of this function is when the contents of a * logical eraseblock has to be re-written. Then it is much more efficient to - * first un-map it, then write new data, rather then first erase it, then write + * first un-map it, then write new data, rather than first erase it, then write * new data. Note, once new data has been written to the logical eraseblock, * UBI guarantees that the old contents has gone forever. In other words, if an * unclean reboot happens after the logical eraseblock has been un-mapped and @@ -534,7 +593,7 @@ int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum) struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; - dbg_msg("unmap LEB %d:%d", vol->vol_id, lnum); + dbg_gen("unmap LEB %d:%d", vol->vol_id, lnum); if (desc->mode == UBI_READONLY || vol->vol_type == UBI_STATIC_VOLUME) return -EROFS; @@ -550,13 +609,12 @@ int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum) EXPORT_SYMBOL_GPL(ubi_leb_unmap); /** - * ubi_leb_map - map logical erasblock to a physical eraseblock. + * ubi_leb_map - map logical eraseblock to a physical eraseblock. * @desc: volume descriptor * @lnum: logical eraseblock number - * @dtype: expected data type * * This function maps an un-mapped logical eraseblock @lnum to a physical - * eraseblock. This means, that after a successfull invocation of this + * eraseblock. This means, that after a successful invocation of this * function the logical eraseblock @lnum will be empty (contain only %0xFF * bytes) and be mapped to a physical eraseblock, even if an unclean reboot * happens. @@ -566,12 +624,12 @@ EXPORT_SYMBOL_GPL(ubi_leb_unmap); * eraseblock is already mapped, and other negative error codes in case of * other failures. */ -int ubi_leb_map(struct ubi_volume_desc *desc, int lnum, int dtype) +int ubi_leb_map(struct ubi_volume_desc *desc, int lnum) { struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; - dbg_msg("unmap LEB %d:%d", vol->vol_id, lnum); + dbg_gen("unmap LEB %d:%d", vol->vol_id, lnum); if (desc->mode == UBI_READONLY || vol->vol_type == UBI_STATIC_VOLUME) return -EROFS; @@ -579,17 +637,13 @@ int ubi_leb_map(struct ubi_volume_desc *desc, int lnum, int dtype) if (lnum < 0 || lnum >= vol->reserved_pebs) return -EINVAL; - if (dtype != UBI_LONGTERM && dtype != UBI_SHORTTERM && - dtype != UBI_UNKNOWN) - return -EINVAL; - if (vol->upd_marker) return -EBADF; if (vol->eba_tbl[lnum] >= 0) return -EBADMSG; - return ubi_eba_write_leb(ubi, vol, lnum, NULL, 0, 0, dtype); + return ubi_eba_write_leb(ubi, vol, lnum, NULL, 0, 0); } EXPORT_SYMBOL_GPL(ubi_leb_map); @@ -613,7 +667,7 @@ int ubi_is_mapped(struct ubi_volume_desc *desc, int lnum) { struct ubi_volume *vol = desc->vol; - dbg_msg("test LEB %d:%d", vol->vol_id, lnum); + dbg_gen("test LEB %d:%d", vol->vol_id, lnum); if (lnum < 0 || lnum >= vol->reserved_pebs) return -EINVAL; @@ -624,3 +678,110 @@ int ubi_is_mapped(struct ubi_volume_desc *desc, int lnum) return vol->eba_tbl[lnum] >= 0; } EXPORT_SYMBOL_GPL(ubi_is_mapped); + +/** + * ubi_sync - synchronize UBI device buffers. + * @ubi_num: UBI device to synchronize + * + * The underlying MTD device may cache data in hardware or in software. This + * function ensures the caches are flushed. Returns zero in case of success and + * a negative error code in case of failure. + */ +int ubi_sync(int ubi_num) +{ + struct ubi_device *ubi; + + ubi = ubi_get_device(ubi_num); + if (!ubi) + return -ENODEV; + + mtd_sync(ubi->mtd); + ubi_put_device(ubi); + return 0; +} +EXPORT_SYMBOL_GPL(ubi_sync); + +/** + * ubi_flush - flush UBI work queue. + * @ubi_num: UBI device to flush work queue + * @vol_id: volume id to flush for + * @lnum: logical eraseblock number to flush for + * + * This function executes all pending works for a particular volume id / logical + * eraseblock number pair. If either value is set to %UBI_ALL, then it acts as + * a wildcard for all of the corresponding volume numbers or logical + * eraseblock numbers. It returns zero in case of success and a negative error + * code in case of failure. + */ +int ubi_flush(int ubi_num, int vol_id, int lnum) +{ + struct ubi_device *ubi; + int err = 0; + + ubi = ubi_get_device(ubi_num); + if (!ubi) + return -ENODEV; + + err = ubi_wl_flush(ubi, vol_id, lnum); + ubi_put_device(ubi); + return err; +} +EXPORT_SYMBOL_GPL(ubi_flush); + +#ifndef __UBOOT__ +BLOCKING_NOTIFIER_HEAD(ubi_notifiers); + +/** + * ubi_register_volume_notifier - register a volume notifier. + * @nb: the notifier description object + * @ignore_existing: if non-zero, do not send "added" notification for all + * already existing volumes + * + * This function registers a volume notifier, which means that + * 'nb->notifier_call()' will be invoked when an UBI volume is created, + * removed, re-sized, re-named, or updated. The first argument of the function + * is the notification type. The second argument is pointer to a + * &struct ubi_notification object which describes the notification event. + * Using UBI API from the volume notifier is prohibited. + * + * This function returns zero in case of success and a negative error code + * in case of failure. + */ +int ubi_register_volume_notifier(struct notifier_block *nb, + int ignore_existing) +{ + int err; + + err = blocking_notifier_chain_register(&ubi_notifiers, nb); + if (err != 0) + return err; + if (ignore_existing) + return 0; + + /* + * We are going to walk all UBI devices and all volumes, and + * notify the user about existing volumes by the %UBI_VOLUME_ADDED + * event. We have to lock the @ubi_devices_mutex to make sure UBI + * devices do not disappear. + */ + mutex_lock(&ubi_devices_mutex); + ubi_enumerate_volumes(nb); + mutex_unlock(&ubi_devices_mutex); + + return err; +} +EXPORT_SYMBOL_GPL(ubi_register_volume_notifier); + +/** + * ubi_unregister_volume_notifier - unregister the volume notifier. + * @nb: the notifier description object + * + * This function unregisters volume notifier @nm and returns zero in case of + * success and a negative error code in case of failure. + */ +int ubi_unregister_volume_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&ubi_notifiers, nb); +} +EXPORT_SYMBOL_GPL(ubi_unregister_volume_notifier); +#endif diff --git a/drivers/mtd/ubi/misc.c b/drivers/mtd/ubi/misc.c index 5ff55b4f77..49530b7448 100644 --- a/drivers/mtd/ubi/misc.c +++ b/drivers/mtd/ubi/misc.c @@ -81,14 +81,62 @@ int ubi_check_volume(struct ubi_device *ubi, int vol_id) } /** - * ubi_calculate_rsvd_pool - calculate how many PEBs must be reserved for bad + * ubi_update_reserved - update bad eraseblock handling accounting data. + * @ubi: UBI device description object + * + * This function calculates the gap between current number of PEBs reserved for + * bad eraseblock handling and the required level of PEBs that must be + * reserved, and if necessary, reserves more PEBs to fill that gap, according + * to availability. Should be called with ubi->volumes_lock held. + */ +void ubi_update_reserved(struct ubi_device *ubi) +{ + int need = ubi->beb_rsvd_level - ubi->beb_rsvd_pebs; + + if (need <= 0 || ubi->avail_pebs == 0) + return; + + need = min_t(int, need, ubi->avail_pebs); + ubi->avail_pebs -= need; + ubi->rsvd_pebs += need; + ubi->beb_rsvd_pebs += need; + ubi_msg("reserved more %d PEBs for bad PEB handling", need); +} + +/** + * ubi_calculate_reserved - calculate how many PEBs must be reserved for bad * eraseblock handling. * @ubi: UBI device description object */ void ubi_calculate_reserved(struct ubi_device *ubi) { - ubi->beb_rsvd_level = ubi->good_peb_count/100; - ubi->beb_rsvd_level *= CONFIG_MTD_UBI_BEB_RESERVE; - if (ubi->beb_rsvd_level < MIN_RESEVED_PEBS) - ubi->beb_rsvd_level = MIN_RESEVED_PEBS; + /* + * Calculate the actual number of PEBs currently needed to be reserved + * for future bad eraseblock handling. + */ + ubi->beb_rsvd_level = ubi->bad_peb_limit - ubi->bad_peb_count; + if (ubi->beb_rsvd_level < 0) { + ubi->beb_rsvd_level = 0; + ubi_warn("number of bad PEBs (%d) is above the expected limit (%d), not reserving any PEBs for bad PEB handling, will use available PEBs (if any)", + ubi->bad_peb_count, ubi->bad_peb_limit); + } +} + +/** + * ubi_check_pattern - check if buffer contains only a certain byte pattern. + * @buf: buffer to check + * @patt: the pattern to check + * @size: buffer size in bytes + * + * This function returns %1 in there are only @patt bytes in @buf, and %0 if + * something else was also found. + */ +int ubi_check_pattern(const void *buf, uint8_t patt, int size) +{ + int i; + + for (i = 0; i < size; i++) + if (((const uint8_t *)buf)[i] != patt) + return 0; + return 1; } diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c deleted file mode 100644 index a6d0fbcbee..0000000000 --- a/drivers/mtd/ubi/scan.c +++ /dev/null @@ -1,1348 +0,0 @@ -/* - * Copyright (c) International Business Machines Corp., 2006 - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Author: Artem Bityutskiy (Битюцкий Артём) - */ - -/* - * UBI scanning unit. - * - * This unit is responsible for scanning the flash media, checking UBI - * headers and providing complete information about the UBI flash image. - * - * The scanning information is represented by a &struct ubi_scan_info' object. - * Information about found volumes is represented by &struct ubi_scan_volume - * objects which are kept in volume RB-tree with root at the @volumes field. - * The RB-tree is indexed by the volume ID. - * - * Found logical eraseblocks are represented by &struct ubi_scan_leb objects. - * These objects are kept in per-volume RB-trees with the root at the - * corresponding &struct ubi_scan_volume object. To put it differently, we keep - * an RB-tree of per-volume objects and each of these objects is the root of - * RB-tree of per-eraseblock objects. - * - * Corrupted physical eraseblocks are put to the @corr list, free physical - * eraseblocks are put to the @free list and the physical eraseblock to be - * erased are put to the @erase list. - */ - -#ifdef UBI_LINUX -#include -#include -#include -#endif - -#include -#include "ubi.h" - -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID -static int paranoid_check_si(struct ubi_device *ubi, struct ubi_scan_info *si); -#else -#define paranoid_check_si(ubi, si) 0 -#endif - -/* Temporary variables used during scanning */ -static struct ubi_ec_hdr *ech; -static struct ubi_vid_hdr *vidh; - -/** - * add_to_list - add physical eraseblock to a list. - * @si: scanning information - * @pnum: physical eraseblock number to add - * @ec: erase counter of the physical eraseblock - * @list: the list to add to - * - * This function adds physical eraseblock @pnum to free, erase, corrupted or - * alien lists. Returns zero in case of success and a negative error code in - * case of failure. - */ -static int add_to_list(struct ubi_scan_info *si, int pnum, int ec, - struct list_head *list) -{ - struct ubi_scan_leb *seb; - - if (list == &si->free) - dbg_bld("add to free: PEB %d, EC %d", pnum, ec); - else if (list == &si->erase) - dbg_bld("add to erase: PEB %d, EC %d", pnum, ec); - else if (list == &si->corr) - dbg_bld("add to corrupted: PEB %d, EC %d", pnum, ec); - else if (list == &si->alien) - dbg_bld("add to alien: PEB %d, EC %d", pnum, ec); - else - BUG(); - - seb = kmalloc(sizeof(struct ubi_scan_leb), GFP_KERNEL); - if (!seb) - return -ENOMEM; - - seb->pnum = pnum; - seb->ec = ec; - list_add_tail(&seb->u.list, list); - return 0; -} - -/** - * validate_vid_hdr - check that volume identifier header is correct and - * consistent. - * @vid_hdr: the volume identifier header to check - * @sv: information about the volume this logical eraseblock belongs to - * @pnum: physical eraseblock number the VID header came from - * - * This function checks that data stored in @vid_hdr is consistent. Returns - * non-zero if an inconsistency was found and zero if not. - * - * Note, UBI does sanity check of everything it reads from the flash media. - * Most of the checks are done in the I/O unit. Here we check that the - * information in the VID header is consistent to the information in other VID - * headers of the same volume. - */ -static int validate_vid_hdr(const struct ubi_vid_hdr *vid_hdr, - const struct ubi_scan_volume *sv, int pnum) -{ - int vol_type = vid_hdr->vol_type; - int vol_id = be32_to_cpu(vid_hdr->vol_id); - int used_ebs = be32_to_cpu(vid_hdr->used_ebs); - int data_pad = be32_to_cpu(vid_hdr->data_pad); - - if (sv->leb_count != 0) { - int sv_vol_type; - - /* - * This is not the first logical eraseblock belonging to this - * volume. Ensure that the data in its VID header is consistent - * to the data in previous logical eraseblock headers. - */ - - if (vol_id != sv->vol_id) { - dbg_err("inconsistent vol_id"); - goto bad; - } - - if (sv->vol_type == UBI_STATIC_VOLUME) - sv_vol_type = UBI_VID_STATIC; - else - sv_vol_type = UBI_VID_DYNAMIC; - - if (vol_type != sv_vol_type) { - dbg_err("inconsistent vol_type"); - goto bad; - } - - if (used_ebs != sv->used_ebs) { - dbg_err("inconsistent used_ebs"); - goto bad; - } - - if (data_pad != sv->data_pad) { - dbg_err("inconsistent data_pad"); - goto bad; - } - } - - return 0; - -bad: - ubi_err("inconsistent VID header at PEB %d", pnum); - ubi_dbg_dump_vid_hdr(vid_hdr); - ubi_dbg_dump_sv(sv); - return -EINVAL; -} - -/** - * add_volume - add volume to the scanning information. - * @si: scanning information - * @vol_id: ID of the volume to add - * @pnum: physical eraseblock number - * @vid_hdr: volume identifier header - * - * If the volume corresponding to the @vid_hdr logical eraseblock is already - * present in the scanning information, this function does nothing. Otherwise - * it adds corresponding volume to the scanning information. Returns a pointer - * to the scanning volume object in case of success and a negative error code - * in case of failure. - */ -static struct ubi_scan_volume *add_volume(struct ubi_scan_info *si, int vol_id, - int pnum, - const struct ubi_vid_hdr *vid_hdr) -{ - struct ubi_scan_volume *sv; - struct rb_node **p = &si->volumes.rb_node, *parent = NULL; - - ubi_assert(vol_id == be32_to_cpu(vid_hdr->vol_id)); - - /* Walk the volume RB-tree to look if this volume is already present */ - while (*p) { - parent = *p; - sv = rb_entry(parent, struct ubi_scan_volume, rb); - - if (vol_id == sv->vol_id) - return sv; - - if (vol_id > sv->vol_id) - p = &(*p)->rb_left; - else - p = &(*p)->rb_right; - } - - /* The volume is absent - add it */ - sv = kmalloc(sizeof(struct ubi_scan_volume), GFP_KERNEL); - if (!sv) - return ERR_PTR(-ENOMEM); - - sv->highest_lnum = sv->leb_count = 0; - sv->vol_id = vol_id; - sv->root = RB_ROOT; - sv->used_ebs = be32_to_cpu(vid_hdr->used_ebs); - sv->data_pad = be32_to_cpu(vid_hdr->data_pad); - sv->compat = vid_hdr->compat; - sv->vol_type = vid_hdr->vol_type == UBI_VID_DYNAMIC ? UBI_DYNAMIC_VOLUME - : UBI_STATIC_VOLUME; - if (vol_id > si->highest_vol_id) - si->highest_vol_id = vol_id; - - rb_link_node(&sv->rb, parent, p); - rb_insert_color(&sv->rb, &si->volumes); - si->vols_found += 1; - dbg_bld("added volume %d", vol_id); - return sv; -} - -/** - * compare_lebs - find out which logical eraseblock is newer. - * @ubi: UBI device description object - * @seb: first logical eraseblock to compare - * @pnum: physical eraseblock number of the second logical eraseblock to - * compare - * @vid_hdr: volume identifier header of the second logical eraseblock - * - * This function compares 2 copies of a LEB and informs which one is newer. In - * case of success this function returns a positive value, in case of failure, a - * negative error code is returned. The success return codes use the following - * bits: - * o bit 0 is cleared: the first PEB (described by @seb) is newer then the - * second PEB (described by @pnum and @vid_hdr); - * o bit 0 is set: the second PEB is newer; - * o bit 1 is cleared: no bit-flips were detected in the newer LEB; - * o bit 1 is set: bit-flips were detected in the newer LEB; - * o bit 2 is cleared: the older LEB is not corrupted; - * o bit 2 is set: the older LEB is corrupted. - */ -static int compare_lebs(struct ubi_device *ubi, const struct ubi_scan_leb *seb, - int pnum, const struct ubi_vid_hdr *vid_hdr) -{ - void *buf; - int len, err, second_is_newer, bitflips = 0, corrupted = 0; - uint32_t data_crc, crc; - struct ubi_vid_hdr *vh = NULL; - unsigned long long sqnum2 = be64_to_cpu(vid_hdr->sqnum); - - if (seb->sqnum == 0 && sqnum2 == 0) { - long long abs, v1 = seb->leb_ver, v2 = be32_to_cpu(vid_hdr->leb_ver); - - /* - * UBI constantly increases the logical eraseblock version - * number and it can overflow. Thus, we have to bear in mind - * that versions that are close to %0xFFFFFFFF are less then - * versions that are close to %0. - * - * The UBI WL unit guarantees that the number of pending tasks - * is not greater then %0x7FFFFFFF. So, if the difference - * between any two versions is greater or equivalent to - * %0x7FFFFFFF, there was an overflow and the logical - * eraseblock with lower version is actually newer then the one - * with higher version. - * - * FIXME: but this is anyway obsolete and will be removed at - * some point. - */ - dbg_bld("using old crappy leb_ver stuff"); - - if (v1 == v2) { - ubi_err("PEB %d and PEB %d have the same version %lld", - seb->pnum, pnum, v1); - return -EINVAL; - } - - abs = v1 - v2; - if (abs < 0) - abs = -abs; - - if (abs < 0x7FFFFFFF) - /* Non-overflow situation */ - second_is_newer = (v2 > v1); - else - second_is_newer = (v2 < v1); - } else - /* Obviously the LEB with lower sequence counter is older */ - second_is_newer = sqnum2 > seb->sqnum; - - /* - * Now we know which copy is newer. If the copy flag of the PEB with - * newer version is not set, then we just return, otherwise we have to - * check data CRC. For the second PEB we already have the VID header, - * for the first one - we'll need to re-read it from flash. - * - * FIXME: this may be optimized so that we wouldn't read twice. - */ - - if (second_is_newer) { - if (!vid_hdr->copy_flag) { - /* It is not a copy, so it is newer */ - dbg_bld("second PEB %d is newer, copy_flag is unset", - pnum); - return 1; - } - } else { - pnum = seb->pnum; - - vh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); - if (!vh) - return -ENOMEM; - - err = ubi_io_read_vid_hdr(ubi, pnum, vh, 0); - if (err) { - if (err == UBI_IO_BITFLIPS) - bitflips = 1; - else { - dbg_err("VID of PEB %d header is bad, but it " - "was OK earlier", pnum); - if (err > 0) - err = -EIO; - - goto out_free_vidh; - } - } - - if (!vh->copy_flag) { - /* It is not a copy, so it is newer */ - dbg_bld("first PEB %d is newer, copy_flag is unset", - pnum); - err = bitflips << 1; - goto out_free_vidh; - } - - vid_hdr = vh; - } - - /* Read the data of the copy and check the CRC */ - - len = be32_to_cpu(vid_hdr->data_size); - buf = vmalloc(len); - if (!buf) { - err = -ENOMEM; - goto out_free_vidh; - } - - err = ubi_io_read_data(ubi, buf, pnum, 0, len); - if (err && err != UBI_IO_BITFLIPS) - goto out_free_buf; - - data_crc = be32_to_cpu(vid_hdr->data_crc); - crc = crc32(UBI_CRC32_INIT, buf, len); - if (crc != data_crc) { - dbg_bld("PEB %d CRC error: calculated %#08x, must be %#08x", - pnum, crc, data_crc); - corrupted = 1; - bitflips = 0; - second_is_newer = !second_is_newer; - } else { - dbg_bld("PEB %d CRC is OK", pnum); - bitflips = !!err; - } - - vfree(buf); - ubi_free_vid_hdr(ubi, vh); - - if (second_is_newer) - dbg_bld("second PEB %d is newer, copy_flag is set", pnum); - else - dbg_bld("first PEB %d is newer, copy_flag is set", pnum); - - return second_is_newer | (bitflips << 1) | (corrupted << 2); - -out_free_buf: - vfree(buf); -out_free_vidh: - ubi_free_vid_hdr(ubi, vh); - return err; -} - -/** - * ubi_scan_add_used - add information about a physical eraseblock to the - * scanning information. - * @ubi: UBI device description object - * @si: scanning information - * @pnum: the physical eraseblock number - * @ec: erase counter - * @vid_hdr: the volume identifier header - * @bitflips: if bit-flips were detected when this physical eraseblock was read - * - * This function adds information about a used physical eraseblock to the - * 'used' tree of the corresponding volume. The function is rather complex - * because it has to handle cases when this is not the first physical - * eraseblock belonging to the same logical eraseblock, and the newer one has - * to be picked, while the older one has to be dropped. This function returns - * zero in case of success and a negative error code in case of failure. - */ -int ubi_scan_add_used(struct ubi_device *ubi, struct ubi_scan_info *si, - int pnum, int ec, const struct ubi_vid_hdr *vid_hdr, - int bitflips) -{ - int err, vol_id, lnum; - uint32_t leb_ver; - unsigned long long sqnum; - struct ubi_scan_volume *sv; - struct ubi_scan_leb *seb; - struct rb_node **p, *parent = NULL; - - vol_id = be32_to_cpu(vid_hdr->vol_id); - lnum = be32_to_cpu(vid_hdr->lnum); - sqnum = be64_to_cpu(vid_hdr->sqnum); - leb_ver = be32_to_cpu(vid_hdr->leb_ver); - - dbg_bld("PEB %d, LEB %d:%d, EC %d, sqnum %llu, ver %u, bitflips %d", - pnum, vol_id, lnum, ec, sqnum, leb_ver, bitflips); - - sv = add_volume(si, vol_id, pnum, vid_hdr); - if (IS_ERR(sv) < 0) - return PTR_ERR(sv); - - if (si->max_sqnum < sqnum) - si->max_sqnum = sqnum; - - /* - * Walk the RB-tree of logical eraseblocks of volume @vol_id to look - * if this is the first instance of this logical eraseblock or not. - */ - p = &sv->root.rb_node; - while (*p) { - int cmp_res; - - parent = *p; - seb = rb_entry(parent, struct ubi_scan_leb, u.rb); - if (lnum != seb->lnum) { - if (lnum < seb->lnum) - p = &(*p)->rb_left; - else - p = &(*p)->rb_right; - continue; - } - - /* - * There is already a physical eraseblock describing the same - * logical eraseblock present. - */ - - dbg_bld("this LEB already exists: PEB %d, sqnum %llu, " - "LEB ver %u, EC %d", seb->pnum, seb->sqnum, - seb->leb_ver, seb->ec); - - /* - * Make sure that the logical eraseblocks have different - * versions. Otherwise the image is bad. - */ - if (seb->leb_ver == leb_ver && leb_ver != 0) { - ubi_err("two LEBs with same version %u", leb_ver); - ubi_dbg_dump_seb(seb, 0); - ubi_dbg_dump_vid_hdr(vid_hdr); - return -EINVAL; - } - - /* - * Make sure that the logical eraseblocks have different - * sequence numbers. Otherwise the image is bad. - * - * FIXME: remove 'sqnum != 0' check when leb_ver is removed. - */ - if (seb->sqnum == sqnum && sqnum != 0) { - ubi_err("two LEBs with same sequence number %llu", - sqnum); - ubi_dbg_dump_seb(seb, 0); - ubi_dbg_dump_vid_hdr(vid_hdr); - return -EINVAL; - } - - /* - * Now we have to drop the older one and preserve the newer - * one. - */ - cmp_res = compare_lebs(ubi, seb, pnum, vid_hdr); - if (cmp_res < 0) - return cmp_res; - - if (cmp_res & 1) { - /* - * This logical eraseblock is newer then the one - * found earlier. - */ - err = validate_vid_hdr(vid_hdr, sv, pnum); - if (err) - return err; - - if (cmp_res & 4) - err = add_to_list(si, seb->pnum, seb->ec, - &si->corr); - else - err = add_to_list(si, seb->pnum, seb->ec, - &si->erase); - if (err) - return err; - - seb->ec = ec; - seb->pnum = pnum; - seb->scrub = ((cmp_res & 2) || bitflips); - seb->sqnum = sqnum; - seb->leb_ver = leb_ver; - - if (sv->highest_lnum == lnum) - sv->last_data_size = - be32_to_cpu(vid_hdr->data_size); - - return 0; - } else { - /* - * This logical eraseblock is older then the one found - * previously. - */ - if (cmp_res & 4) - return add_to_list(si, pnum, ec, &si->corr); - else - return add_to_list(si, pnum, ec, &si->erase); - } - } - - /* - * We've met this logical eraseblock for the first time, add it to the - * scanning information. - */ - - err = validate_vid_hdr(vid_hdr, sv, pnum); - if (err) - return err; - - seb = kmalloc(sizeof(struct ubi_scan_leb), GFP_KERNEL); - if (!seb) - return -ENOMEM; - - seb->ec = ec; - seb->pnum = pnum; - seb->lnum = lnum; - seb->sqnum = sqnum; - seb->scrub = bitflips; - seb->leb_ver = leb_ver; - - if (sv->highest_lnum <= lnum) { - sv->highest_lnum = lnum; - sv->last_data_size = be32_to_cpu(vid_hdr->data_size); - } - - sv->leb_count += 1; - rb_link_node(&seb->u.rb, parent, p); - rb_insert_color(&seb->u.rb, &sv->root); - return 0; -} - -/** - * ubi_scan_find_sv - find information about a particular volume in the - * scanning information. - * @si: scanning information - * @vol_id: the requested volume ID - * - * This function returns a pointer to the volume description or %NULL if there - * are no data about this volume in the scanning information. - */ -struct ubi_scan_volume *ubi_scan_find_sv(const struct ubi_scan_info *si, - int vol_id) -{ - struct ubi_scan_volume *sv; - struct rb_node *p = si->volumes.rb_node; - - while (p) { - sv = rb_entry(p, struct ubi_scan_volume, rb); - - if (vol_id == sv->vol_id) - return sv; - - if (vol_id > sv->vol_id) - p = p->rb_left; - else - p = p->rb_right; - } - - return NULL; -} - -/** - * ubi_scan_find_seb - find information about a particular logical - * eraseblock in the volume scanning information. - * @sv: a pointer to the volume scanning information - * @lnum: the requested logical eraseblock - * - * This function returns a pointer to the scanning logical eraseblock or %NULL - * if there are no data about it in the scanning volume information. - */ -struct ubi_scan_leb *ubi_scan_find_seb(const struct ubi_scan_volume *sv, - int lnum) -{ - struct ubi_scan_leb *seb; - struct rb_node *p = sv->root.rb_node; - - while (p) { - seb = rb_entry(p, struct ubi_scan_leb, u.rb); - - if (lnum == seb->lnum) - return seb; - - if (lnum > seb->lnum) - p = p->rb_left; - else - p = p->rb_right; - } - - return NULL; -} - -/** - * ubi_scan_rm_volume - delete scanning information about a volume. - * @si: scanning information - * @sv: the volume scanning information to delete - */ -void ubi_scan_rm_volume(struct ubi_scan_info *si, struct ubi_scan_volume *sv) -{ - struct rb_node *rb; - struct ubi_scan_leb *seb; - - dbg_bld("remove scanning information about volume %d", sv->vol_id); - - while ((rb = rb_first(&sv->root))) { - seb = rb_entry(rb, struct ubi_scan_leb, u.rb); - rb_erase(&seb->u.rb, &sv->root); - list_add_tail(&seb->u.list, &si->erase); - } - - rb_erase(&sv->rb, &si->volumes); - kfree(sv); - si->vols_found -= 1; -} - -/** - * ubi_scan_erase_peb - erase a physical eraseblock. - * @ubi: UBI device description object - * @si: scanning information - * @pnum: physical eraseblock number to erase; - * @ec: erase counter value to write (%UBI_SCAN_UNKNOWN_EC if it is unknown) - * - * This function erases physical eraseblock 'pnum', and writes the erase - * counter header to it. This function should only be used on UBI device - * initialization stages, when the EBA unit had not been yet initialized. This - * function returns zero in case of success and a negative error code in case - * of failure. - */ -int ubi_scan_erase_peb(struct ubi_device *ubi, const struct ubi_scan_info *si, - int pnum, int ec) -{ - int err; - struct ubi_ec_hdr *ec_hdr; - - if ((long long)ec >= UBI_MAX_ERASECOUNTER) { - /* - * Erase counter overflow. Upgrade UBI and use 64-bit - * erase counters internally. - */ - ubi_err("erase counter overflow at PEB %d, EC %d", pnum, ec); - return -EINVAL; - } - - ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); - if (!ec_hdr) - return -ENOMEM; - - ec_hdr->ec = cpu_to_be64(ec); - - err = ubi_io_sync_erase(ubi, pnum, 0); - if (err < 0) - goto out_free; - - err = ubi_io_write_ec_hdr(ubi, pnum, ec_hdr); - -out_free: - kfree(ec_hdr); - return err; -} - -/** - * ubi_scan_get_free_peb - get a free physical eraseblock. - * @ubi: UBI device description object - * @si: scanning information - * - * This function returns a free physical eraseblock. It is supposed to be - * called on the UBI initialization stages when the wear-leveling unit is not - * initialized yet. This function picks a physical eraseblocks from one of the - * lists, writes the EC header if it is needed, and removes it from the list. - * - * This function returns scanning physical eraseblock information in case of - * success and an error code in case of failure. - */ -struct ubi_scan_leb *ubi_scan_get_free_peb(struct ubi_device *ubi, - struct ubi_scan_info *si) -{ - int err = 0, i; - struct ubi_scan_leb *seb; - - if (!list_empty(&si->free)) { - seb = list_entry(si->free.next, struct ubi_scan_leb, u.list); - list_del(&seb->u.list); - dbg_bld("return free PEB %d, EC %d", seb->pnum, seb->ec); - return seb; - } - - for (i = 0; i < 2; i++) { - struct list_head *head; - struct ubi_scan_leb *tmp_seb; - - if (i == 0) - head = &si->erase; - else - head = &si->corr; - - /* - * We try to erase the first physical eraseblock from the @head - * list and pick it if we succeed, or try to erase the - * next one if not. And so forth. We don't want to take care - * about bad eraseblocks here - they'll be handled later. - */ - list_for_each_entry_safe(seb, tmp_seb, head, u.list) { - if (seb->ec == UBI_SCAN_UNKNOWN_EC) - seb->ec = si->mean_ec; - - err = ubi_scan_erase_peb(ubi, si, seb->pnum, seb->ec+1); - if (err) - continue; - - seb->ec += 1; - list_del(&seb->u.list); - dbg_bld("return PEB %d, EC %d", seb->pnum, seb->ec); - return seb; - } - } - - ubi_err("no eraseblocks found"); - return ERR_PTR(-ENOSPC); -} - -/** - * process_eb - read UBI headers, check them and add corresponding data - * to the scanning information. - * @ubi: UBI device description object - * @si: scanning information - * @pnum: the physical eraseblock number - * - * This function returns a zero if the physical eraseblock was successfully - * handled and a negative error code in case of failure. - */ -static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, int pnum) -{ - long long uninitialized_var(ec); - int err, bitflips = 0, vol_id, ec_corr = 0; - - dbg_bld("scan PEB %d", pnum); - - /* Skip bad physical eraseblocks */ - err = ubi_io_is_bad(ubi, pnum); - if (err < 0) - return err; - else if (err) { - /* - * FIXME: this is actually duty of the I/O unit to initialize - * this, but MTD does not provide enough information. - */ - si->bad_peb_count += 1; - return 0; - } - - err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); - if (err < 0) - return err; - else if (err == UBI_IO_BITFLIPS) - bitflips = 1; - else if (err == UBI_IO_PEB_EMPTY) - return add_to_list(si, pnum, UBI_SCAN_UNKNOWN_EC, &si->erase); - else if (err == UBI_IO_BAD_EC_HDR) { - /* - * We have to also look at the VID header, possibly it is not - * corrupted. Set %bitflips flag in order to make this PEB be - * moved and EC be re-created. - */ - ec_corr = 1; - ec = UBI_SCAN_UNKNOWN_EC; - bitflips = 1; - } - - si->is_empty = 0; - - if (!ec_corr) { - /* Make sure UBI version is OK */ - if (ech->version != UBI_VERSION) { - ubi_err("this UBI version is %d, image version is %d", - UBI_VERSION, (int)ech->version); - return -EINVAL; - } - - ec = be64_to_cpu(ech->ec); - if (ec > UBI_MAX_ERASECOUNTER) { - /* - * Erase counter overflow. The EC headers have 64 bits - * reserved, but we anyway make use of only 31 bit - * values, as this seems to be enough for any existing - * flash. Upgrade UBI and use 64-bit erase counters - * internally. - */ - ubi_err("erase counter overflow, max is %d", - UBI_MAX_ERASECOUNTER); - ubi_dbg_dump_ec_hdr(ech); - return -EINVAL; - } - } - - /* OK, we've done with the EC header, let's look at the VID header */ - - err = ubi_io_read_vid_hdr(ubi, pnum, vidh, 0); - if (err < 0) - return err; - else if (err == UBI_IO_BITFLIPS) - bitflips = 1; - else if (err == UBI_IO_BAD_VID_HDR || - (err == UBI_IO_PEB_FREE && ec_corr)) { - /* VID header is corrupted */ - err = add_to_list(si, pnum, ec, &si->corr); - if (err) - return err; - goto adjust_mean_ec; - } else if (err == UBI_IO_PEB_FREE) { - /* No VID header - the physical eraseblock is free */ - err = add_to_list(si, pnum, ec, &si->free); - if (err) - return err; - goto adjust_mean_ec; - } - - vol_id = be32_to_cpu(vidh->vol_id); - if (vol_id > UBI_MAX_VOLUMES && vol_id != UBI_LAYOUT_VOLUME_ID) { - int lnum = be32_to_cpu(vidh->lnum); - - /* Unsupported internal volume */ - switch (vidh->compat) { - case UBI_COMPAT_DELETE: - ubi_msg("\"delete\" compatible internal volume %d:%d" - " found, remove it", vol_id, lnum); - err = add_to_list(si, pnum, ec, &si->corr); - if (err) - return err; - break; - - case UBI_COMPAT_RO: - ubi_msg("read-only compatible internal volume %d:%d" - " found, switch to read-only mode", - vol_id, lnum); - ubi->ro_mode = 1; - break; - - case UBI_COMPAT_PRESERVE: - ubi_msg("\"preserve\" compatible internal volume %d:%d" - " found", vol_id, lnum); - err = add_to_list(si, pnum, ec, &si->alien); - if (err) - return err; - si->alien_peb_count += 1; - return 0; - - case UBI_COMPAT_REJECT: - ubi_err("incompatible internal volume %d:%d found", - vol_id, lnum); - return -EINVAL; - } - } - - /* Both UBI headers seem to be fine */ - err = ubi_scan_add_used(ubi, si, pnum, ec, vidh, bitflips); - if (err) - return err; - -adjust_mean_ec: - if (!ec_corr) { - si->ec_sum += ec; - si->ec_count += 1; - if (ec > si->max_ec) - si->max_ec = ec; - if (ec < si->min_ec) - si->min_ec = ec; - } - - return 0; -} - -/** - * ubi_scan - scan an MTD device. - * @ubi: UBI device description object - * - * This function does full scanning of an MTD device and returns complete - * information about it. In case of failure, an error code is returned. - */ -struct ubi_scan_info *ubi_scan(struct ubi_device *ubi) -{ - int err, pnum; - struct rb_node *rb1, *rb2; - struct ubi_scan_volume *sv; - struct ubi_scan_leb *seb; - struct ubi_scan_info *si; - - si = kzalloc(sizeof(struct ubi_scan_info), GFP_KERNEL); - if (!si) - return ERR_PTR(-ENOMEM); - - INIT_LIST_HEAD(&si->corr); - INIT_LIST_HEAD(&si->free); - INIT_LIST_HEAD(&si->erase); - INIT_LIST_HEAD(&si->alien); - si->volumes = RB_ROOT; - si->is_empty = 1; - - err = -ENOMEM; - ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL); - if (!ech) - goto out_si; - - vidh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); - if (!vidh) - goto out_ech; - - for (pnum = 0; pnum < ubi->peb_count; pnum++) { - cond_resched(); - - dbg_msg("process PEB %d", pnum); - err = process_eb(ubi, si, pnum); - if (err < 0) - goto out_vidh; - } - - dbg_msg("scanning is finished"); - - /* Calculate mean erase counter */ - if (si->ec_count) { - do_div(si->ec_sum, si->ec_count); - si->mean_ec = si->ec_sum; - } - - if (si->is_empty) - ubi_msg("empty MTD device detected"); - - /* - * In case of unknown erase counter we use the mean erase counter - * value. - */ - ubi_rb_for_each_entry(rb1, sv, &si->volumes, rb) { - ubi_rb_for_each_entry(rb2, seb, &sv->root, u.rb) - if (seb->ec == UBI_SCAN_UNKNOWN_EC) - seb->ec = si->mean_ec; - } - - list_for_each_entry(seb, &si->free, u.list) { - if (seb->ec == UBI_SCAN_UNKNOWN_EC) - seb->ec = si->mean_ec; - } - - list_for_each_entry(seb, &si->corr, u.list) - if (seb->ec == UBI_SCAN_UNKNOWN_EC) - seb->ec = si->mean_ec; - - list_for_each_entry(seb, &si->erase, u.list) - if (seb->ec == UBI_SCAN_UNKNOWN_EC) - seb->ec = si->mean_ec; - - err = paranoid_check_si(ubi, si); - if (err) { - if (err > 0) - err = -EINVAL; - goto out_vidh; - } - - ubi_free_vid_hdr(ubi, vidh); - kfree(ech); - - return si; - -out_vidh: - ubi_free_vid_hdr(ubi, vidh); -out_ech: - kfree(ech); -out_si: - ubi_scan_destroy_si(si); - return ERR_PTR(err); -} - -/** - * destroy_sv - free the scanning volume information - * @sv: scanning volume information - * - * This function destroys the volume RB-tree (@sv->root) and the scanning - * volume information. - */ -static void destroy_sv(struct ubi_scan_volume *sv) -{ - struct ubi_scan_leb *seb; - struct rb_node *this = sv->root.rb_node; - - while (this) { - if (this->rb_left) - this = this->rb_left; - else if (this->rb_right) - this = this->rb_right; - else { - seb = rb_entry(this, struct ubi_scan_leb, u.rb); - this = rb_parent(this); - if (this) { - if (this->rb_left == &seb->u.rb) - this->rb_left = NULL; - else - this->rb_right = NULL; - } - - kfree(seb); - } - } - kfree(sv); -} - -/** - * ubi_scan_destroy_si - destroy scanning information. - * @si: scanning information - */ -void ubi_scan_destroy_si(struct ubi_scan_info *si) -{ - struct ubi_scan_leb *seb, *seb_tmp; - struct ubi_scan_volume *sv; - struct rb_node *rb; - - list_for_each_entry_safe(seb, seb_tmp, &si->alien, u.list) { - list_del(&seb->u.list); - kfree(seb); - } - list_for_each_entry_safe(seb, seb_tmp, &si->erase, u.list) { - list_del(&seb->u.list); - kfree(seb); - } - list_for_each_entry_safe(seb, seb_tmp, &si->corr, u.list) { - list_del(&seb->u.list); - kfree(seb); - } - list_for_each_entry_safe(seb, seb_tmp, &si->free, u.list) { - list_del(&seb->u.list); - kfree(seb); - } - - /* Destroy the volume RB-tree */ - rb = si->volumes.rb_node; - while (rb) { - if (rb->rb_left) - rb = rb->rb_left; - else if (rb->rb_right) - rb = rb->rb_right; - else { - sv = rb_entry(rb, struct ubi_scan_volume, rb); - - rb = rb_parent(rb); - if (rb) { - if (rb->rb_left == &sv->rb) - rb->rb_left = NULL; - else - rb->rb_right = NULL; - } - - destroy_sv(sv); - } - } - - kfree(si); -} - -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID - -/** - * paranoid_check_si - check if the scanning information is correct and - * consistent. - * @ubi: UBI device description object - * @si: scanning information - * - * This function returns zero if the scanning information is all right, %1 if - * not and a negative error code if an error occurred. - */ -static int paranoid_check_si(struct ubi_device *ubi, struct ubi_scan_info *si) -{ - int pnum, err, vols_found = 0; - struct rb_node *rb1, *rb2; - struct ubi_scan_volume *sv; - struct ubi_scan_leb *seb, *last_seb; - uint8_t *buf; - - /* - * At first, check that scanning information is OK. - */ - ubi_rb_for_each_entry(rb1, sv, &si->volumes, rb) { - int leb_count = 0; - - cond_resched(); - - vols_found += 1; - - if (si->is_empty) { - ubi_err("bad is_empty flag"); - goto bad_sv; - } - - if (sv->vol_id < 0 || sv->highest_lnum < 0 || - sv->leb_count < 0 || sv->vol_type < 0 || sv->used_ebs < 0 || - sv->data_pad < 0 || sv->last_data_size < 0) { - ubi_err("negative values"); - goto bad_sv; - } - - if (sv->vol_id >= UBI_MAX_VOLUMES && - sv->vol_id < UBI_INTERNAL_VOL_START) { - ubi_err("bad vol_id"); - goto bad_sv; - } - - if (sv->vol_id > si->highest_vol_id) { - ubi_err("highest_vol_id is %d, but vol_id %d is there", - si->highest_vol_id, sv->vol_id); - goto out; - } - - if (sv->vol_type != UBI_DYNAMIC_VOLUME && - sv->vol_type != UBI_STATIC_VOLUME) { - ubi_err("bad vol_type"); - goto bad_sv; - } - - if (sv->data_pad > ubi->leb_size / 2) { - ubi_err("bad data_pad"); - goto bad_sv; - } - - last_seb = NULL; - ubi_rb_for_each_entry(rb2, seb, &sv->root, u.rb) { - cond_resched(); - - last_seb = seb; - leb_count += 1; - - if (seb->pnum < 0 || seb->ec < 0) { - ubi_err("negative values"); - goto bad_seb; - } - - if (seb->ec < si->min_ec) { - ubi_err("bad si->min_ec (%d), %d found", - si->min_ec, seb->ec); - goto bad_seb; - } - - if (seb->ec > si->max_ec) { - ubi_err("bad si->max_ec (%d), %d found", - si->max_ec, seb->ec); - goto bad_seb; - } - - if (seb->pnum >= ubi->peb_count) { - ubi_err("too high PEB number %d, total PEBs %d", - seb->pnum, ubi->peb_count); - goto bad_seb; - } - - if (sv->vol_type == UBI_STATIC_VOLUME) { - if (seb->lnum >= sv->used_ebs) { - ubi_err("bad lnum or used_ebs"); - goto bad_seb; - } - } else { - if (sv->used_ebs != 0) { - ubi_err("non-zero used_ebs"); - goto bad_seb; - } - } - - if (seb->lnum > sv->highest_lnum) { - ubi_err("incorrect highest_lnum or lnum"); - goto bad_seb; - } - } - - if (sv->leb_count != leb_count) { - ubi_err("bad leb_count, %d objects in the tree", - leb_count); - goto bad_sv; - } - - if (!last_seb) - continue; - - seb = last_seb; - - if (seb->lnum != sv->highest_lnum) { - ubi_err("bad highest_lnum"); - goto bad_seb; - } - } - - if (vols_found != si->vols_found) { - ubi_err("bad si->vols_found %d, should be %d", - si->vols_found, vols_found); - goto out; - } - - /* Check that scanning information is correct */ - ubi_rb_for_each_entry(rb1, sv, &si->volumes, rb) { - last_seb = NULL; - ubi_rb_for_each_entry(rb2, seb, &sv->root, u.rb) { - int vol_type; - - cond_resched(); - - last_seb = seb; - - err = ubi_io_read_vid_hdr(ubi, seb->pnum, vidh, 1); - if (err && err != UBI_IO_BITFLIPS) { - ubi_err("VID header is not OK (%d)", err); - if (err > 0) - err = -EIO; - return err; - } - - vol_type = vidh->vol_type == UBI_VID_DYNAMIC ? - UBI_DYNAMIC_VOLUME : UBI_STATIC_VOLUME; - if (sv->vol_type != vol_type) { - ubi_err("bad vol_type"); - goto bad_vid_hdr; - } - - if (seb->sqnum != be64_to_cpu(vidh->sqnum)) { - ubi_err("bad sqnum %llu", seb->sqnum); - goto bad_vid_hdr; - } - - if (sv->vol_id != be32_to_cpu(vidh->vol_id)) { - ubi_err("bad vol_id %d", sv->vol_id); - goto bad_vid_hdr; - } - - if (sv->compat != vidh->compat) { - ubi_err("bad compat %d", vidh->compat); - goto bad_vid_hdr; - } - - if (seb->lnum != be32_to_cpu(vidh->lnum)) { - ubi_err("bad lnum %d", seb->lnum); - goto bad_vid_hdr; - } - - if (sv->used_ebs != be32_to_cpu(vidh->used_ebs)) { - ubi_err("bad used_ebs %d", sv->used_ebs); - goto bad_vid_hdr; - } - - if (sv->data_pad != be32_to_cpu(vidh->data_pad)) { - ubi_err("bad data_pad %d", sv->data_pad); - goto bad_vid_hdr; - } - - if (seb->leb_ver != be32_to_cpu(vidh->leb_ver)) { - ubi_err("bad leb_ver %u", seb->leb_ver); - goto bad_vid_hdr; - } - } - - if (!last_seb) - continue; - - if (sv->highest_lnum != be32_to_cpu(vidh->lnum)) { - ubi_err("bad highest_lnum %d", sv->highest_lnum); - goto bad_vid_hdr; - } - - if (sv->last_data_size != be32_to_cpu(vidh->data_size)) { - ubi_err("bad last_data_size %d", sv->last_data_size); - goto bad_vid_hdr; - } - } - - /* - * Make sure that all the physical eraseblocks are in one of the lists - * or trees. - */ - buf = kzalloc(ubi->peb_count, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - for (pnum = 0; pnum < ubi->peb_count; pnum++) { - err = ubi_io_is_bad(ubi, pnum); - if (err < 0) { - kfree(buf); - return err; - } - else if (err) - buf[pnum] = 1; - } - - ubi_rb_for_each_entry(rb1, sv, &si->volumes, rb) - ubi_rb_for_each_entry(rb2, seb, &sv->root, u.rb) - buf[seb->pnum] = 1; - - list_for_each_entry(seb, &si->free, u.list) - buf[seb->pnum] = 1; - - list_for_each_entry(seb, &si->corr, u.list) - buf[seb->pnum] = 1; - - list_for_each_entry(seb, &si->erase, u.list) - buf[seb->pnum] = 1; - - list_for_each_entry(seb, &si->alien, u.list) - buf[seb->pnum] = 1; - - err = 0; - for (pnum = 0; pnum < ubi->peb_count; pnum++) - if (!buf[pnum]) { - ubi_err("PEB %d is not referred", pnum); - err = 1; - } - - kfree(buf); - if (err) - goto out; - return 0; - -bad_seb: - ubi_err("bad scanning information about LEB %d", seb->lnum); - ubi_dbg_dump_seb(seb, 0); - ubi_dbg_dump_sv(sv); - goto out; - -bad_sv: - ubi_err("bad scanning information about volume %d", sv->vol_id); - ubi_dbg_dump_sv(sv); - goto out; - -bad_vid_hdr: - ubi_err("bad scanning information about volume %d", sv->vol_id); - ubi_dbg_dump_sv(sv); - ubi_dbg_dump_vid_hdr(vidh); - -out: - ubi_dbg_dump_stack(); - return 1; -} - -#endif /* CONFIG_MTD_UBI_DEBUG_PARANOID */ diff --git a/drivers/mtd/ubi/scan.h b/drivers/mtd/ubi/scan.h deleted file mode 100644 index 252b1f1e82..0000000000 --- a/drivers/mtd/ubi/scan.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) International Business Machines Corp., 2006 - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Author: Artem Bityutskiy (Битюцкий Артём) - */ - -#ifndef __UBI_SCAN_H__ -#define __UBI_SCAN_H__ - -/* The erase counter value for this physical eraseblock is unknown */ -#define UBI_SCAN_UNKNOWN_EC (-1) - -/** - * struct ubi_scan_leb - scanning information about a physical eraseblock. - * @ec: erase counter (%UBI_SCAN_UNKNOWN_EC if it is unknown) - * @pnum: physical eraseblock number - * @lnum: logical eraseblock number - * @scrub: if this physical eraseblock needs scrubbing - * @sqnum: sequence number - * @u: unions RB-tree or @list links - * @u.rb: link in the per-volume RB-tree of &struct ubi_scan_leb objects - * @u.list: link in one of the eraseblock lists - * @leb_ver: logical eraseblock version (obsolete) - * - * One object of this type is allocated for each physical eraseblock during - * scanning. - */ -struct ubi_scan_leb { - int ec; - int pnum; - int lnum; - int scrub; - unsigned long long sqnum; - union { - struct rb_node rb; - struct list_head list; - } u; - uint32_t leb_ver; -}; - -/** - * struct ubi_scan_volume - scanning information about a volume. - * @vol_id: volume ID - * @highest_lnum: highest logical eraseblock number in this volume - * @leb_count: number of logical eraseblocks in this volume - * @vol_type: volume type - * @used_ebs: number of used logical eraseblocks in this volume (only for - * static volumes) - * @last_data_size: amount of data in the last logical eraseblock of this - * volume (always equivalent to the usable logical eraseblock size in case of - * dynamic volumes) - * @data_pad: how many bytes at the end of logical eraseblocks of this volume - * are not used (due to volume alignment) - * @compat: compatibility flags of this volume - * @rb: link in the volume RB-tree - * @root: root of the RB-tree containing all the eraseblock belonging to this - * volume (&struct ubi_scan_leb objects) - * - * One object of this type is allocated for each volume during scanning. - */ -struct ubi_scan_volume { - int vol_id; - int highest_lnum; - int leb_count; - int vol_type; - int used_ebs; - int last_data_size; - int data_pad; - int compat; - struct rb_node rb; - struct rb_root root; -}; - -/** - * struct ubi_scan_info - UBI scanning information. - * @volumes: root of the volume RB-tree - * @corr: list of corrupted physical eraseblocks - * @free: list of free physical eraseblocks - * @erase: list of physical eraseblocks which have to be erased - * @alien: list of physical eraseblocks which should not be used by UBI (e.g., - * @bad_peb_count: count of bad physical eraseblocks - * those belonging to "preserve"-compatible internal volumes) - * @vols_found: number of volumes found during scanning - * @highest_vol_id: highest volume ID - * @alien_peb_count: count of physical eraseblocks in the @alien list - * @is_empty: flag indicating whether the MTD device is empty or not - * @min_ec: lowest erase counter value - * @max_ec: highest erase counter value - * @max_sqnum: highest sequence number value - * @mean_ec: mean erase counter value - * @ec_sum: a temporary variable used when calculating @mean_ec - * @ec_count: a temporary variable used when calculating @mean_ec - * - * This data structure contains the result of scanning and may be used by other - * UBI units to build final UBI data structures, further error-recovery and so - * on. - */ -struct ubi_scan_info { - struct rb_root volumes; - struct list_head corr; - struct list_head free; - struct list_head erase; - struct list_head alien; - int bad_peb_count; - int vols_found; - int highest_vol_id; - int alien_peb_count; - int is_empty; - int min_ec; - int max_ec; - unsigned long long max_sqnum; - int mean_ec; - uint64_t ec_sum; - int ec_count; -}; - -struct ubi_device; -struct ubi_vid_hdr; - -/* - * ubi_scan_move_to_list - move a physical eraseblock from the volume tree to a - * list. - * - * @sv: volume scanning information - * @seb: scanning eraseblock infprmation - * @list: the list to move to - */ -static inline void ubi_scan_move_to_list(struct ubi_scan_volume *sv, - struct ubi_scan_leb *seb, - struct list_head *list) -{ - rb_erase(&seb->u.rb, &sv->root); - list_add_tail(&seb->u.list, list); -} - -int ubi_scan_add_used(struct ubi_device *ubi, struct ubi_scan_info *si, - int pnum, int ec, const struct ubi_vid_hdr *vid_hdr, - int bitflips); -struct ubi_scan_volume *ubi_scan_find_sv(const struct ubi_scan_info *si, - int vol_id); -struct ubi_scan_leb *ubi_scan_find_seb(const struct ubi_scan_volume *sv, - int lnum); -void ubi_scan_rm_volume(struct ubi_scan_info *si, struct ubi_scan_volume *sv); -struct ubi_scan_leb *ubi_scan_get_free_peb(struct ubi_device *ubi, - struct ubi_scan_info *si); -int ubi_scan_erase_peb(struct ubi_device *ubi, const struct ubi_scan_info *si, - int pnum, int ec); -struct ubi_scan_info *ubi_scan(struct ubi_device *ubi); -void ubi_scan_destroy_si(struct ubi_scan_info *si); - -#endif /* !__UBI_SCAN_H__ */ diff --git a/drivers/mtd/ubi/ubi-media.h b/drivers/mtd/ubi/ubi-media.h index 9012326d61..2809805c2c 100644 --- a/drivers/mtd/ubi/ubi-media.h +++ b/drivers/mtd/ubi/ubi-media.h @@ -86,10 +86,11 @@ enum { * Compatibility constants used by internal volumes. * * @UBI_COMPAT_DELETE: delete this internal volume before anything is written - * to the flash + * to the flash * @UBI_COMPAT_RO: attach this device in read-only mode * @UBI_COMPAT_PRESERVE: preserve this internal volume - do not touch its - * physical eraseblocks, don't allow the wear-leveling unit to move them + * physical eraseblocks, don't allow the wear-leveling + * sub-system to move them * @UBI_COMPAT_REJECT: reject this UBI image */ enum { @@ -111,18 +112,19 @@ enum { * struct ubi_ec_hdr - UBI erase counter header. * @magic: erase counter header magic number (%UBI_EC_HDR_MAGIC) * @version: version of UBI implementation which is supposed to accept this - * UBI image + * UBI image * @padding1: reserved for future, zeroes * @ec: the erase counter * @vid_hdr_offset: where the VID header starts * @data_offset: where the user data start + * @image_seq: image sequence number * @padding2: reserved for future, zeroes * @hdr_crc: erase counter header CRC checksum * * The erase counter header takes 64 bytes and has a plenty of unused space for * future usage. The unused fields are zeroed. The @version field is used to * indicate the version of UBI implementation which is supposed to be able to - * work with this UBI image. If @version is greater then the current UBI + * work with this UBI image. If @version is greater than the current UBI * version, the image is rejected. This may be useful in future if something * is changed radically. This field is duplicated in the volume identifier * header. @@ -131,6 +133,14 @@ enum { * volume identifier header and user data, relative to the beginning of the * physical eraseblock. These values have to be the same for all physical * eraseblocks. + * + * The @image_seq field is used to validate a UBI image that has been prepared + * for a UBI device. The @image_seq value can be any value, but it must be the + * same on all eraseblocks. UBI will ensure that all new erase counter headers + * also contain this value, and will check the value when attaching the flash. + * One way to make use of @image_seq is to increase its value by one every time + * an image is flashed over an existing image, then, if the flashing does not + * complete, UBI will detect the error when attaching the media. */ struct ubi_ec_hdr { __be32 magic; @@ -139,32 +149,32 @@ struct ubi_ec_hdr { __be64 ec; /* Warning: the current limit is 31-bit anyway! */ __be32 vid_hdr_offset; __be32 data_offset; - __u8 padding2[36]; + __be32 image_seq; + __u8 padding2[32]; __be32 hdr_crc; -} __attribute__ ((packed)); +} __packed; /** * struct ubi_vid_hdr - on-flash UBI volume identifier header. * @magic: volume identifier header magic number (%UBI_VID_HDR_MAGIC) * @version: UBI implementation version which is supposed to accept this UBI - * image (%UBI_VERSION) + * image (%UBI_VERSION) * @vol_type: volume type (%UBI_VID_DYNAMIC or %UBI_VID_STATIC) * @copy_flag: if this logical eraseblock was copied from another physical - * eraseblock (for wear-leveling reasons) + * eraseblock (for wear-leveling reasons) * @compat: compatibility of this volume (%0, %UBI_COMPAT_DELETE, - * %UBI_COMPAT_IGNORE, %UBI_COMPAT_PRESERVE, or %UBI_COMPAT_REJECT) + * %UBI_COMPAT_IGNORE, %UBI_COMPAT_PRESERVE, or %UBI_COMPAT_REJECT) * @vol_id: ID of this volume * @lnum: logical eraseblock number - * @leb_ver: version of this logical eraseblock (IMPORTANT: obsolete, to be - * removed, kept only for not breaking older UBI users) + * @padding1: reserved for future, zeroes * @data_size: how many bytes of data this logical eraseblock contains * @used_ebs: total number of used logical eraseblocks in this volume * @data_pad: how many bytes at the end of this physical eraseblock are not - * used + * used * @data_crc: CRC checksum of the data stored in this logical eraseblock - * @padding1: reserved for future, zeroes - * @sqnum: sequence number * @padding2: reserved for future, zeroes + * @sqnum: sequence number + * @padding3: reserved for future, zeroes * @hdr_crc: volume identifier header CRC checksum * * The @sqnum is the value of the global sequence counter at the time when this @@ -175,7 +185,7 @@ struct ubi_ec_hdr { * (sequence number) is used to distinguish between older and newer versions of * logical eraseblocks. * - * There are 2 situations when there may be more then one physical eraseblock + * There are 2 situations when there may be more than one physical eraseblock * corresponding to the same logical eraseblock, i.e., having the same @vol_id * and @lnum values in the volume identifier header. Suppose we have a logical * eraseblock L and it is mapped to the physical eraseblock P. @@ -212,10 +222,6 @@ struct ubi_ec_hdr { * checksum is correct, this physical eraseblock is selected (P1). Otherwise * the older one (P) is selected. * - * Note, there is an obsolete @leb_ver field which was used instead of @sqnum - * in the past. But it is not used anymore and we keep it in order to be able - * to deal with old UBI images. It will be removed at some point. - * * There are 2 sorts of volumes in UBI: user volumes and internal volumes. * Internal volumes are not seen from outside and are used for various internal * UBI purposes. In this implementation there is only one internal volume - the @@ -236,9 +242,9 @@ struct ubi_ec_hdr { * The @data_crc field contains the CRC checksum of the contents of the logical * eraseblock if this is a static volume. In case of dynamic volumes, it does * not contain the CRC checksum as a rule. The only exception is when the - * data of the physical eraseblock was moved by the wear-leveling unit, then - * the wear-leveling unit calculates the data CRC and stores it in the - * @data_crc field. And of course, the @copy_flag is %in this case. + * data of the physical eraseblock was moved by the wear-leveling sub-system, + * then the wear-leveling sub-system calculates the data CRC and stores it in + * the @data_crc field. And of course, the @copy_flag is %in this case. * * The @data_size field is used only for static volumes because UBI has to know * how many bytes of data are stored in this eraseblock. For dynamic volumes, @@ -265,23 +271,23 @@ struct ubi_vid_hdr { __u8 compat; __be32 vol_id; __be32 lnum; - __be32 leb_ver; /* obsolete, to be removed, don't use */ + __u8 padding1[4]; __be32 data_size; __be32 used_ebs; __be32 data_pad; __be32 data_crc; - __u8 padding1[4]; + __u8 padding2[4]; __be64 sqnum; - __u8 padding2[12]; + __u8 padding3[12]; __be32 hdr_crc; -} __attribute__ ((packed)); +} __packed; /* Internal UBI volumes count */ #define UBI_INT_VOL_COUNT 1 /* - * Starting ID of internal volumes. There is reserved room for 4096 internal - * volumes. + * Starting ID of internal volumes: 0x7fffefff. + * There is reserved room for 4096 internal volumes. */ #define UBI_INTERNAL_VOL_START (0x7FFFFFFF - 4096) @@ -351,10 +357,151 @@ struct ubi_vtbl_record { __u8 vol_type; __u8 upd_marker; __be16 name_len; +#ifndef __UBOOT__ __u8 name[UBI_VOL_NAME_MAX+1]; +#else + char name[UBI_VOL_NAME_MAX+1]; +#endif __u8 flags; __u8 padding[23]; __be32 crc; -} __attribute__ ((packed)); +} __packed; + +/* UBI fastmap on-flash data structures */ + +#define UBI_FM_SB_VOLUME_ID (UBI_LAYOUT_VOLUME_ID + 1) +#define UBI_FM_DATA_VOLUME_ID (UBI_LAYOUT_VOLUME_ID + 2) +/* fastmap on-flash data structure format version */ +#define UBI_FM_FMT_VERSION 1 + +#define UBI_FM_SB_MAGIC 0x7B11D69F +#define UBI_FM_HDR_MAGIC 0xD4B82EF7 +#define UBI_FM_VHDR_MAGIC 0xFA370ED1 +#define UBI_FM_POOL_MAGIC 0x67AF4D08 +#define UBI_FM_EBA_MAGIC 0xf0c040a8 + +/* A fastmap supber block can be located between PEB 0 and + * UBI_FM_MAX_START */ +#define UBI_FM_MAX_START 64 + +/* A fastmap can use up to UBI_FM_MAX_BLOCKS PEBs */ +#define UBI_FM_MAX_BLOCKS 32 + +/* 5% of the total number of PEBs have to be scanned while attaching + * from a fastmap. + * But the size of this pool is limited to be between UBI_FM_MIN_POOL_SIZE and + * UBI_FM_MAX_POOL_SIZE */ +#define UBI_FM_MIN_POOL_SIZE 8 +#define UBI_FM_MAX_POOL_SIZE 256 + +#define UBI_FM_WL_POOL_SIZE 25 + +/** + * struct ubi_fm_sb - UBI fastmap super block + * @magic: fastmap super block magic number (%UBI_FM_SB_MAGIC) + * @version: format version of this fastmap + * @data_crc: CRC over the fastmap data + * @used_blocks: number of PEBs used by this fastmap + * @block_loc: an array containing the location of all PEBs of the fastmap + * @block_ec: the erase counter of each used PEB + * @sqnum: highest sequence number value at the time while taking the fastmap + * + */ +struct ubi_fm_sb { + __be32 magic; + __u8 version; + __u8 padding1[3]; + __be32 data_crc; + __be32 used_blocks; + __be32 block_loc[UBI_FM_MAX_BLOCKS]; + __be32 block_ec[UBI_FM_MAX_BLOCKS]; + __be64 sqnum; + __u8 padding2[32]; +} __packed; + +/** + * struct ubi_fm_hdr - header of the fastmap data set + * @magic: fastmap header magic number (%UBI_FM_HDR_MAGIC) + * @free_peb_count: number of free PEBs known by this fastmap + * @used_peb_count: number of used PEBs known by this fastmap + * @scrub_peb_count: number of to be scrubbed PEBs known by this fastmap + * @bad_peb_count: number of bad PEBs known by this fastmap + * @erase_peb_count: number of bad PEBs which have to be erased + * @vol_count: number of UBI volumes known by this fastmap + */ +struct ubi_fm_hdr { + __be32 magic; + __be32 free_peb_count; + __be32 used_peb_count; + __be32 scrub_peb_count; + __be32 bad_peb_count; + __be32 erase_peb_count; + __be32 vol_count; + __u8 padding[4]; +} __packed; + +/* struct ubi_fm_hdr is followed by two struct ubi_fm_scan_pool */ + +/** + * struct ubi_fm_scan_pool - Fastmap pool PEBs to be scanned while attaching + * @magic: pool magic numer (%UBI_FM_POOL_MAGIC) + * @size: current pool size + * @max_size: maximal pool size + * @pebs: an array containing the location of all PEBs in this pool + */ +struct ubi_fm_scan_pool { + __be32 magic; + __be16 size; + __be16 max_size; + __be32 pebs[UBI_FM_MAX_POOL_SIZE]; + __be32 padding[4]; +} __packed; + +/* ubi_fm_scan_pool is followed by nfree+nused struct ubi_fm_ec records */ + +/** + * struct ubi_fm_ec - stores the erase counter of a PEB + * @pnum: PEB number + * @ec: ec of this PEB + */ +struct ubi_fm_ec { + __be32 pnum; + __be32 ec; +} __packed; + +/** + * struct ubi_fm_volhdr - Fastmap volume header + * it identifies the start of an eba table + * @magic: Fastmap volume header magic number (%UBI_FM_VHDR_MAGIC) + * @vol_id: volume id of the fastmapped volume + * @vol_type: type of the fastmapped volume + * @data_pad: data_pad value of the fastmapped volume + * @used_ebs: number of used LEBs within this volume + * @last_eb_bytes: number of bytes used in the last LEB + */ +struct ubi_fm_volhdr { + __be32 magic; + __be32 vol_id; + __u8 vol_type; + __u8 padding1[3]; + __be32 data_pad; + __be32 used_ebs; + __be32 last_eb_bytes; + __u8 padding2[8]; +} __packed; + +/* struct ubi_fm_volhdr is followed by one struct ubi_fm_eba records */ + +/** + * struct ubi_fm_eba - denotes an association beween a PEB and LEB + * @magic: EBA table magic number + * @reserved_pebs: number of table entries + * @pnum: PEB number of LEB (LEB is the index) + */ +struct ubi_fm_eba { + __be32 magic; + __be32 reserved_pebs; + __be32 pnum[0]; +} __packed; #endif /* !__UBI_MEDIA_H__ */ diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index f4f71655ed..754b3371d2 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -10,8 +10,7 @@ #ifndef __UBI_UBI_H__ #define __UBI_UBI_H__ -#ifdef UBI_LINUX -#include +#ifndef __UBOOT__ #include #include #include @@ -23,22 +22,18 @@ #include #include #include +#include #include #include -#include -#include +#include +#include +#else +#include #endif - -#include -#include -#include -#include #include #include - #include "ubi-media.h" -#include "scan.h" -#include "debug.h" +#include /* Maximum number of supported UBI devices */ #define UBI_MAX_DEVICES 32 @@ -52,20 +47,21 @@ #else #define ubi_msg(fmt, ...) printk(KERN_NOTICE "UBI: " fmt "\n", ##__VA_ARGS__) #endif + /* UBI warning messages */ -#define ubi_warn(fmt, ...) printk(KERN_WARNING "UBI warning: %s: " fmt "\n", \ - __func__, ##__VA_ARGS__) +#define ubi_warn(fmt, ...) pr_warn("UBI warning: %s: " fmt "\n", \ + __func__, ##__VA_ARGS__) /* UBI error messages */ -#define ubi_err(fmt, ...) printk(KERN_ERR "UBI error: %s: " fmt "\n", \ +#define ubi_err(fmt, ...) pr_err("UBI error: %s: " fmt "\n", \ __func__, ##__VA_ARGS__) -/* Lowest number PEBs reserved for bad PEB handling */ -#define MIN_RESEVED_PEBS 2 - /* Background thread name pattern */ #define UBI_BGT_NAME_PATTERN "ubi_bgt%dd" -/* This marker in the EBA table means that the LEB is um-mapped */ +/* + * This marker in the EBA table means that the LEB is um-mapped. + * NOTE! It has to have the same value as %UBI_ALL. + */ #define UBI_LEB_UNMAPPED -1 /* @@ -75,37 +71,98 @@ #define UBI_IO_RETRIES 3 /* - * Error codes returned by the I/O unit. - * - * UBI_IO_PEB_EMPTY: the physical eraseblock is empty, i.e. it contains only - * 0xFF bytes - * UBI_IO_PEB_FREE: the physical eraseblock is free, i.e. it contains only a - * valid erase counter header, and the rest are %0xFF bytes - * UBI_IO_BAD_EC_HDR: the erase counter header is corrupted (bad magic or CRC) - * UBI_IO_BAD_VID_HDR: the volume identifier header is corrupted (bad magic or - * CRC) + * Length of the protection queue. The length is effectively equivalent to the + * number of (global) erase cycles PEBs are protected from the wear-leveling + * worker. + */ +#define UBI_PROT_QUEUE_LEN 10 + +/* The volume ID/LEB number/erase counter is unknown */ +#define UBI_UNKNOWN -1 + +/* + * The UBI debugfs directory name pattern and maximum name length (3 for "ubi" + * + 2 for the number plus 1 for the trailing zero byte. + */ +#define UBI_DFS_DIR_NAME "ubi%d" +#define UBI_DFS_DIR_LEN (3 + 2 + 1) + +/* + * Error codes returned by the I/O sub-system. + * + * UBI_IO_FF: the read region of flash contains only 0xFFs + * UBI_IO_FF_BITFLIPS: the same as %UBI_IO_FF, but also also there was a data + * integrity error reported by the MTD driver + * (uncorrectable ECC error in case of NAND) + * UBI_IO_BAD_HDR: the EC or VID header is corrupted (bad magic or CRC) + * UBI_IO_BAD_HDR_EBADMSG: the same as %UBI_IO_BAD_HDR, but also there was a + * data integrity error reported by the MTD driver + * (uncorrectable ECC error in case of NAND) * UBI_IO_BITFLIPS: bit-flips were detected and corrected + * + * Note, it is probably better to have bit-flip and ebadmsg as flags which can + * be or'ed with other error code. But this is a big change because there are + * may callers, so it does not worth the risk of introducing a bug + */ +enum { + UBI_IO_FF = 1, + UBI_IO_FF_BITFLIPS, + UBI_IO_BAD_HDR, + UBI_IO_BAD_HDR_EBADMSG, + UBI_IO_BITFLIPS, +}; + +/* + * Return codes of the 'ubi_eba_copy_leb()' function. + * + * MOVE_CANCEL_RACE: canceled because the volume is being deleted, the source + * PEB was put meanwhile, or there is I/O on the source PEB + * MOVE_SOURCE_RD_ERR: canceled because there was a read error from the source + * PEB + * MOVE_TARGET_RD_ERR: canceled because there was a read error from the target + * PEB + * MOVE_TARGET_WR_ERR: canceled because there was a write error to the target + * PEB + * MOVE_TARGET_BITFLIPS: canceled because a bit-flip was detected in the + * target PEB + * MOVE_RETRY: retry scrubbing the PEB */ enum { - UBI_IO_PEB_EMPTY = 1, - UBI_IO_PEB_FREE, - UBI_IO_BAD_EC_HDR, - UBI_IO_BAD_VID_HDR, - UBI_IO_BITFLIPS + MOVE_CANCEL_RACE = 1, + MOVE_SOURCE_RD_ERR, + MOVE_TARGET_RD_ERR, + MOVE_TARGET_WR_ERR, + MOVE_TARGET_BITFLIPS, + MOVE_RETRY, +}; + +/* + * Return codes of the fastmap sub-system + * + * UBI_NO_FASTMAP: No fastmap super block was found + * UBI_BAD_FASTMAP: A fastmap was found but it's unusable + */ +enum { + UBI_NO_FASTMAP = 1, + UBI_BAD_FASTMAP, }; /** * struct ubi_wl_entry - wear-leveling entry. - * @rb: link in the corresponding RB-tree + * @u.rb: link in the corresponding (free/used) RB-tree + * @u.list: link in the protection queue * @ec: erase counter * @pnum: physical eraseblock number * - * This data structure is used in the WL unit. Each physical eraseblock has a - * corresponding &struct wl_entry object which may be kept in different - * RB-trees. See WL unit for details. + * This data structure is used in the WL sub-system. Each physical eraseblock + * has a corresponding &struct wl_entry object which may be kept in different + * RB-trees. See WL sub-system for details. */ struct ubi_wl_entry { - struct rb_node rb; + union { + struct rb_node rb; + struct list_head list; + } u; int ec; int pnum; }; @@ -119,10 +176,10 @@ struct ubi_wl_entry { * @mutex: read/write mutex to implement read/write access serialization to * the (@vol_id, @lnum) logical eraseblock * - * This data structure is used in the EBA unit to implement per-LEB locking. - * When a logical eraseblock is being locked - corresponding + * This data structure is used in the EBA sub-system to implement per-LEB + * locking. When a logical eraseblock is being locked - corresponding * &struct ubi_ltree_entry object is inserted to the lock tree (@ubi->ltree). - * See EBA unit for details. + * See EBA sub-system for details. */ struct ubi_ltree_entry { struct rb_node rb; @@ -132,8 +189,64 @@ struct ubi_ltree_entry { struct rw_semaphore mutex; }; +/** + * struct ubi_rename_entry - volume re-name description data structure. + * @new_name_len: new volume name length + * @new_name: new volume name + * @remove: if not zero, this volume should be removed, not re-named + * @desc: descriptor of the volume + * @list: links re-name entries into a list + * + * This data structure is utilized in the multiple volume re-name code. Namely, + * UBI first creates a list of &struct ubi_rename_entry objects from the + * &struct ubi_rnvol_req request object, and then utilizes this list to do all + * the job. + */ +struct ubi_rename_entry { + int new_name_len; + char new_name[UBI_VOL_NAME_MAX + 1]; + int remove; + struct ubi_volume_desc *desc; + struct list_head list; +}; + struct ubi_volume_desc; +/** + * struct ubi_fastmap_layout - in-memory fastmap data structure. + * @e: PEBs used by the current fastmap + * @to_be_tortured: if non-zero tortured this PEB + * @used_blocks: number of used PEBs + * @max_pool_size: maximal size of the user pool + * @max_wl_pool_size: maximal size of the pool used by the WL sub-system + */ +struct ubi_fastmap_layout { + struct ubi_wl_entry *e[UBI_FM_MAX_BLOCKS]; + int to_be_tortured[UBI_FM_MAX_BLOCKS]; + int used_blocks; + int max_pool_size; + int max_wl_pool_size; +}; + +/** + * struct ubi_fm_pool - in-memory fastmap pool + * @pebs: PEBs in this pool + * @used: number of used PEBs + * @size: total number of PEBs in this pool + * @max_size: maximal size of the pool + * + * A pool gets filled with up to max_size. + * If all PEBs within the pool are used a new fastmap will be written + * to the flash and the pool gets refilled with empty PEBs. + * + */ +struct ubi_fm_pool { + int pebs[UBI_FM_MAX_POOL_SIZE]; + int used; + int size; + int max_size; +}; + /** * struct ubi_volume - UBI volume description data structure. * @dev: device object to make use of the the Linux device model @@ -160,8 +273,6 @@ struct ubi_volume_desc; * @upd_ebs: how many eraseblocks are expected to be updated * @ch_lnum: LEB number which is being changing by the atomic LEB change * operation - * @ch_dtype: data persistency type which is being changing by the atomic LEB - * change operation * @upd_bytes: how many bytes are expected to be received for volume update or * atomic LEB change * @upd_received: how many bytes were already received for volume update or @@ -175,10 +286,7 @@ struct ubi_volume_desc; * @upd_marker: %1 if the update marker is set for this volume * @updating: %1 if the volume is being updated * @changing_leb: %1 if the atomic LEB change ioctl command is in progress - * - * @gluebi_desc: gluebi UBI volume descriptor - * @gluebi_refcount: reference count of the gluebi MTD device - * @gluebi_mtd: MTD device description object of the gluebi MTD device + * @direct_writes: %1 if direct writes are enabled for this volume * * The @corrupted field indicates that the volume's contents is corrupted. * Since UBI protects only static volumes, this field is not relevant to @@ -202,16 +310,19 @@ struct ubi_volume { int vol_type; int usable_leb_size; int used_ebs; +#ifndef __UBOOT__ int last_eb_bytes; +#else + u32 last_eb_bytes; +#endif long long used_bytes; int alignment; int data_pad; int name_len; - char name[UBI_VOL_NAME_MAX+1]; + char name[UBI_VOL_NAME_MAX + 1]; int upd_ebs; int ch_lnum; - int ch_dtype; long long upd_bytes; long long upd_received; void *upd_buf; @@ -222,22 +333,11 @@ struct ubi_volume { unsigned int upd_marker:1; unsigned int updating:1; unsigned int changing_leb:1; - -#ifdef CONFIG_MTD_UBI_GLUEBI - /* - * Gluebi-related stuff may be compiled out. - * TODO: this should not be built into UBI but should be a separate - * ubimtd driver which works on top of UBI and emulates MTD devices. - */ - struct ubi_volume_desc *gluebi_desc; - int gluebi_refcount; - struct mtd_info gluebi_mtd; -#endif + unsigned int direct_writes:1; }; /** - * struct ubi_volume_desc - descriptor of the UBI volume returned when it is - * opened. + * struct ubi_volume_desc - UBI volume descriptor returned when it is opened. * @vol: reference to the corresponding volume description object * @mode: open mode (%UBI_READONLY, %UBI_READWRITE, or %UBI_EXCLUSIVE) */ @@ -248,6 +348,37 @@ struct ubi_volume_desc { struct ubi_wl_entry; +/** + * struct ubi_debug_info - debugging information for an UBI device. + * + * @chk_gen: if UBI general extra checks are enabled + * @chk_io: if UBI I/O extra checks are enabled + * @disable_bgt: disable the background task for testing purposes + * @emulate_bitflips: emulate bit-flips for testing purposes + * @emulate_io_failures: emulate write/erase failures for testing purposes + * @dfs_dir_name: name of debugfs directory containing files of this UBI device + * @dfs_dir: direntry object of the UBI device debugfs directory + * @dfs_chk_gen: debugfs knob to enable UBI general extra checks + * @dfs_chk_io: debugfs knob to enable UBI I/O extra checks + * @dfs_disable_bgt: debugfs knob to disable the background task + * @dfs_emulate_bitflips: debugfs knob to emulate bit-flips + * @dfs_emulate_io_failures: debugfs knob to emulate write/erase failures + */ +struct ubi_debug_info { + unsigned int chk_gen:1; + unsigned int chk_io:1; + unsigned int disable_bgt:1; + unsigned int emulate_bitflips:1; + unsigned int emulate_io_failures:1; + char dfs_dir_name[UBI_DFS_DIR_LEN + 1]; + struct dentry *dfs_dir; + struct dentry *dfs_chk_gen; + struct dentry *dfs_chk_io; + struct dentry *dfs_disable_bgt; + struct dentry *dfs_emulate_bitflips; + struct dentry *dfs_emulate_io_failures; +}; + /** * struct ubi_device - UBI device description structure * @dev: UBI device object to use the the Linux device model @@ -261,6 +392,7 @@ struct ubi_wl_entry; * @vol->readers, @vol->writers, @vol->exclusive, * @vol->ref_count, @vol->mapping and @vol->eba_tbl. * @ref_count: count of references on the UBI device + * @image_seq: image sequence number recorded on EC headers * * @rsvd_pebs: count of reserved physical eraseblocks * @avail_pebs: count of available physical eraseblocks @@ -269,12 +401,13 @@ struct ubi_wl_entry; * @beb_rsvd_level: normal level of PEBs reserved for bad PEB handling * * @autoresize_vol_id: ID of the volume which has to be auto-resized at the end - * of UBI ititializetion + * of UBI initialization * @vtbl_slots: how many slots are available in the volume table * @vtbl_size: size of the volume table in bytes * @vtbl: in-RAM volume table copy - * @volumes_mutex: protects on-flash volume table and serializes volume - * changes, like creation, deletion, update, resize + * @device_mutex: protects on-flash volume table and serializes volume + * creation, deletion, update, re-size, re-name and set + * property * * @max_ec: current highest erase counter value * @mean_ec: current mean erase counter value @@ -284,20 +417,33 @@ struct ubi_wl_entry; * @ltree: the lock tree * @alc_mutex: serializes "atomic LEB change" operations * + * @fm_disabled: non-zero if fastmap is disabled (default) + * @fm: in-memory data structure of the currently used fastmap + * @fm_pool: in-memory data structure of the fastmap pool + * @fm_wl_pool: in-memory data structure of the fastmap pool used by the WL + * sub-system + * @fm_mutex: serializes ubi_update_fastmap() and protects @fm_buf + * @fm_buf: vmalloc()'d buffer which holds the raw fastmap + * @fm_size: fastmap size in bytes + * @fm_sem: allows ubi_update_fastmap() to block EBA table changes + * @fm_work: fastmap work queue + * * @used: RB-tree of used physical eraseblocks + * @erroneous: RB-tree of erroneous used physical eraseblocks * @free: RB-tree of free physical eraseblocks + * @free_count: Contains the number of elements in @free * @scrub: RB-tree of physical eraseblocks which need scrubbing - * @prot: protection trees - * @prot.pnum: protection tree indexed by physical eraseblock numbers - * @prot.aec: protection tree indexed by absolute erase counter value - * @wl_lock: protects the @used, @free, @prot, @lookuptbl, @abs_ec, @move_from, - * @move_to, @move_to_put @erase_pending, @wl_scheduled, and @works - * fields + * @pq: protection queue (contain physical eraseblocks which are temporarily + * protected from the wear-leveling worker) + * @pq_head: protection queue head + * @wl_lock: protects the @used, @free, @pq, @pq_head, @lookuptbl, @move_from, + * @move_to, @move_to_put @erase_pending, @wl_scheduled, @works, + * @erroneous, and @erroneous_peb_count fields * @move_mutex: serializes eraseblock moves + * @work_sem: synchronizes the WL worker with use tasks * @wl_scheduled: non-zero if the wear-leveling was scheduled * @lookuptbl: a table to quickly find a &struct ubi_wl_entry object for any * physical eraseblock - * @abs_ec: absolute erase counter * @move_from: physical eraseblock from where the data is being moved * @move_to: physical eraseblock where the data is being moved to * @move_to_put: if the "to" PEB was put @@ -310,30 +456,38 @@ struct ubi_wl_entry; * @flash_size: underlying MTD device size (in bytes) * @peb_count: count of physical eraseblocks on the MTD device * @peb_size: physical eraseblock size + * @bad_peb_limit: top limit of expected bad physical eraseblocks * @bad_peb_count: count of bad physical eraseblocks * @good_peb_count: count of good physical eraseblocks + * @corr_peb_count: count of corrupted physical eraseblocks (preserved and not + * used by UBI) + * @erroneous_peb_count: count of erroneous physical eraseblocks in @erroneous + * @max_erroneous: maximum allowed amount of erroneous physical eraseblocks * @min_io_size: minimal input/output unit size of the underlying MTD device * @hdrs_min_io_size: minimal I/O unit size used for VID and EC headers * @ro_mode: if the UBI device is in read-only mode * @leb_size: logical eraseblock size * @leb_start: starting offset of logical eraseblocks within physical - * eraseblocks + * eraseblocks * @ec_hdr_alsize: size of the EC header aligned to @hdrs_min_io_size * @vid_hdr_alsize: size of the VID header aligned to @hdrs_min_io_size * @vid_hdr_offset: starting offset of the volume identifier header (might be - * unaligned) + * unaligned) * @vid_hdr_aloffset: starting offset of the VID header aligned to * @hdrs_min_io_size * @vid_hdr_shift: contains @vid_hdr_offset - @vid_hdr_aloffset * @bad_allowed: whether the MTD device admits of bad physical eraseblocks or * not + * @nor_flash: non-zero if working on top of NOR flash + * @max_write_size: maximum amount of bytes the underlying flash can write at a + * time (MTD write buffer size) * @mtd: MTD device descriptor * - * @peb_buf1: a buffer of PEB size used for different purposes - * @peb_buf2: another buffer of PEB size used for different purposes - * @buf_mutex: proptects @peb_buf1 and @peb_buf2 - * @dbg_peb_buf: buffer of PEB size used for debugging - * @dbg_buf_mutex: proptects @dbg_peb_buf + * @peb_buf: a buffer of PEB size used for different purposes + * @buf_mutex: protects @peb_buf + * @ckvol_mutex: serializes static volume checking when opening + * + * @dbg: debugging information for this UBI device */ struct ubi_device { struct cdev cdev; @@ -344,42 +498,56 @@ struct ubi_device { struct ubi_volume *volumes[UBI_MAX_VOLUMES+UBI_INT_VOL_COUNT]; spinlock_t volumes_lock; int ref_count; + int image_seq; int rsvd_pebs; int avail_pebs; int beb_rsvd_pebs; int beb_rsvd_level; + int bad_peb_limit; int autoresize_vol_id; int vtbl_slots; int vtbl_size; struct ubi_vtbl_record *vtbl; - struct mutex volumes_mutex; + struct mutex device_mutex; int max_ec; - /* TODO: mean_ec is not updated run-time, fix */ + /* Note, mean_ec is not updated run-time - should be fixed */ int mean_ec; - /* EBA unit's stuff */ + /* EBA sub-system's stuff */ unsigned long long global_sqnum; spinlock_t ltree_lock; struct rb_root ltree; struct mutex alc_mutex; - /* Wear-leveling unit's stuff */ + /* Fastmap stuff */ + int fm_disabled; + struct ubi_fastmap_layout *fm; + struct ubi_fm_pool fm_pool; + struct ubi_fm_pool fm_wl_pool; + struct rw_semaphore fm_sem; + struct mutex fm_mutex; + void *fm_buf; + size_t fm_size; +#ifndef __UBOOT__ + struct work_struct fm_work; +#endif + + /* Wear-leveling sub-system's stuff */ struct rb_root used; + struct rb_root erroneous; struct rb_root free; + int free_count; struct rb_root scrub; - struct { - struct rb_root pnum; - struct rb_root aec; - } prot; + struct list_head pq[UBI_PROT_QUEUE_LEN]; + int pq_head; spinlock_t wl_lock; struct mutex move_mutex; struct rw_semaphore work_sem; int wl_scheduled; struct ubi_wl_entry **lookuptbl; - unsigned long long abs_ec; struct ubi_wl_entry *move_from; struct ubi_wl_entry *move_to; int move_to_put; @@ -389,12 +557,15 @@ struct ubi_device { int thread_enabled; char bgt_name[sizeof(UBI_BGT_NAME_PATTERN)+2]; - /* I/O unit's stuff */ + /* I/O sub-system's stuff */ long long flash_size; int peb_count; int peb_size; int bad_peb_count; int good_peb_count; + int corr_peb_count; + int erroneous_peb_count; + int max_erroneous; int min_io_size; int hdrs_min_io_size; int ro_mode; @@ -405,35 +576,195 @@ struct ubi_device { int vid_hdr_offset; int vid_hdr_aloffset; int vid_hdr_shift; - int bad_allowed; + unsigned int bad_allowed:1; + unsigned int nor_flash:1; + int max_write_size; struct mtd_info *mtd; - void *peb_buf1; - void *peb_buf2; + void *peb_buf; struct mutex buf_mutex; struct mutex ckvol_mutex; -#ifdef CONFIG_MTD_UBI_DEBUG - void *dbg_peb_buf; - struct mutex dbg_buf_mutex; -#endif + + struct ubi_debug_info dbg; +}; + +/** + * struct ubi_ainf_peb - attach information about a physical eraseblock. + * @ec: erase counter (%UBI_UNKNOWN if it is unknown) + * @pnum: physical eraseblock number + * @vol_id: ID of the volume this LEB belongs to + * @lnum: logical eraseblock number + * @scrub: if this physical eraseblock needs scrubbing + * @copy_flag: this LEB is a copy (@copy_flag is set in VID header of this LEB) + * @sqnum: sequence number + * @u: unions RB-tree or @list links + * @u.rb: link in the per-volume RB-tree of &struct ubi_ainf_peb objects + * @u.list: link in one of the eraseblock lists + * + * One object of this type is allocated for each physical eraseblock when + * attaching an MTD device. Note, if this PEB does not belong to any LEB / + * volume, the @vol_id and @lnum fields are initialized to %UBI_UNKNOWN. + */ +struct ubi_ainf_peb { + int ec; + int pnum; + int vol_id; + int lnum; + unsigned int scrub:1; + unsigned int copy_flag:1; + unsigned long long sqnum; + union { + struct rb_node rb; + struct list_head list; + } u; +}; + +/** + * struct ubi_ainf_volume - attaching information about a volume. + * @vol_id: volume ID + * @highest_lnum: highest logical eraseblock number in this volume + * @leb_count: number of logical eraseblocks in this volume + * @vol_type: volume type + * @used_ebs: number of used logical eraseblocks in this volume (only for + * static volumes) + * @last_data_size: amount of data in the last logical eraseblock of this + * volume (always equivalent to the usable logical eraseblock + * size in case of dynamic volumes) + * @data_pad: how many bytes at the end of logical eraseblocks of this volume + * are not used (due to volume alignment) + * @compat: compatibility flags of this volume + * @rb: link in the volume RB-tree + * @root: root of the RB-tree containing all the eraseblock belonging to this + * volume (&struct ubi_ainf_peb objects) + * + * One object of this type is allocated for each volume when attaching an MTD + * device. + */ +struct ubi_ainf_volume { + int vol_id; + int highest_lnum; + int leb_count; + int vol_type; + int used_ebs; + int last_data_size; + int data_pad; + int compat; + struct rb_node rb; + struct rb_root root; }; +/** + * struct ubi_attach_info - MTD device attaching information. + * @volumes: root of the volume RB-tree + * @corr: list of corrupted physical eraseblocks + * @free: list of free physical eraseblocks + * @erase: list of physical eraseblocks which have to be erased + * @alien: list of physical eraseblocks which should not be used by UBI (e.g., + * those belonging to "preserve"-compatible internal volumes) + * @corr_peb_count: count of PEBs in the @corr list + * @empty_peb_count: count of PEBs which are presumably empty (contain only + * 0xFF bytes) + * @alien_peb_count: count of PEBs in the @alien list + * @bad_peb_count: count of bad physical eraseblocks + * @maybe_bad_peb_count: count of bad physical eraseblocks which are not marked + * as bad yet, but which look like bad + * @vols_found: number of volumes found + * @highest_vol_id: highest volume ID + * @is_empty: flag indicating whether the MTD device is empty or not + * @min_ec: lowest erase counter value + * @max_ec: highest erase counter value + * @max_sqnum: highest sequence number value + * @mean_ec: mean erase counter value + * @ec_sum: a temporary variable used when calculating @mean_ec + * @ec_count: a temporary variable used when calculating @mean_ec + * @aeb_slab_cache: slab cache for &struct ubi_ainf_peb objects + * + * This data structure contains the result of attaching an MTD device and may + * be used by other UBI sub-systems to build final UBI data structures, further + * error-recovery and so on. + */ +struct ubi_attach_info { + struct rb_root volumes; + struct list_head corr; + struct list_head free; + struct list_head erase; + struct list_head alien; + int corr_peb_count; + int empty_peb_count; + int alien_peb_count; + int bad_peb_count; + int maybe_bad_peb_count; + int vols_found; + int highest_vol_id; + int is_empty; + int min_ec; + int max_ec; + unsigned long long max_sqnum; + int mean_ec; + uint64_t ec_sum; + int ec_count; + struct kmem_cache *aeb_slab_cache; +}; + +/** + * struct ubi_work - UBI work description data structure. + * @list: a link in the list of pending works + * @func: worker function + * @e: physical eraseblock to erase + * @vol_id: the volume ID on which this erasure is being performed + * @lnum: the logical eraseblock number + * @torture: if the physical eraseblock has to be tortured + * @anchor: produce a anchor PEB to by used by fastmap + * + * The @func pointer points to the worker function. If the @cancel argument is + * not zero, the worker has to free the resources and exit immediately. The + * worker has to return zero in case of success and a negative error code in + * case of failure. + */ +struct ubi_work { + struct list_head list; + int (*func)(struct ubi_device *ubi, struct ubi_work *wrk, int cancel); + /* The below fields are only relevant to erasure works */ + struct ubi_wl_entry *e; + int vol_id; + int lnum; + int torture; + int anchor; +}; + +#include "debug.h" + extern struct kmem_cache *ubi_wl_entry_slab; -extern struct file_operations ubi_ctrl_cdev_operations; -extern struct file_operations ubi_cdev_operations; -extern struct file_operations ubi_vol_cdev_operations; +extern const struct file_operations ubi_ctrl_cdev_operations; +extern const struct file_operations ubi_cdev_operations; +extern const struct file_operations ubi_vol_cdev_operations; extern struct class *ubi_class; extern struct mutex ubi_devices_mutex; +extern struct blocking_notifier_head ubi_notifiers; + +/* attach.c */ +int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum, + int ec, const struct ubi_vid_hdr *vid_hdr, int bitflips); +struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai, + int vol_id); +void ubi_remove_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av); +struct ubi_ainf_peb *ubi_early_get_peb(struct ubi_device *ubi, + struct ubi_attach_info *ai); +int ubi_attach(struct ubi_device *ubi, int force_scan); +void ubi_destroy_ai(struct ubi_attach_info *ai); /* vtbl.c */ int ubi_change_vtbl_record(struct ubi_device *ubi, int idx, struct ubi_vtbl_record *vtbl_rec); -int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_scan_info *si); +int ubi_vtbl_rename_volumes(struct ubi_device *ubi, + struct list_head *rename_list); +int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_attach_info *ai); /* vmt.c */ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req); -int ubi_remove_volume(struct ubi_volume_desc *desc); +int ubi_remove_volume(struct ubi_volume_desc *desc, int no_vtbl); int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs); +int ubi_rename_volumes(struct ubi_device *ubi, struct list_head *rename_list); int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol); void ubi_free_volume(struct ubi_device *ubi, struct ubi_volume *vol); @@ -448,9 +779,12 @@ int ubi_more_leb_change_data(struct ubi_device *ubi, struct ubi_volume *vol, const void __user *buf, int count); /* misc.c */ -int ubi_calc_data_len(const struct ubi_device *ubi, const void *buf, int length); +int ubi_calc_data_len(const struct ubi_device *ubi, const void *buf, + int length); int ubi_check_volume(struct ubi_device *ubi, int vol_id); +void ubi_update_reserved(struct ubi_device *ubi); void ubi_calculate_reserved(struct ubi_device *ubi); +int ubi_check_pattern(const void *buf, uint8_t patt, int size); /* gluebi.c */ #ifdef CONFIG_MTD_UBI_GLUEBI @@ -474,25 +808,33 @@ int ubi_eba_unmap_leb(struct ubi_device *ubi, struct ubi_volume *vol, int ubi_eba_read_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, void *buf, int offset, int len, int check); int ubi_eba_write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, - const void *buf, int offset, int len, int dtype); + const void *buf, int offset, int len); int ubi_eba_write_leb_st(struct ubi_device *ubi, struct ubi_volume *vol, - int lnum, const void *buf, int len, int dtype, - int used_ebs); + int lnum, const void *buf, int len, int used_ebs); int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol, - int lnum, const void *buf, int len, int dtype); + int lnum, const void *buf, int len); int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, struct ubi_vid_hdr *vid_hdr); -int ubi_eba_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si); -void ubi_eba_close(const struct ubi_device *ubi); +int ubi_eba_init(struct ubi_device *ubi, struct ubi_attach_info *ai); +unsigned long long ubi_next_sqnum(struct ubi_device *ubi); +int self_check_eba(struct ubi_device *ubi, struct ubi_attach_info *ai_fastmap, + struct ubi_attach_info *ai_scan); /* wl.c */ -int ubi_wl_get_peb(struct ubi_device *ubi, int dtype); -int ubi_wl_put_peb(struct ubi_device *ubi, int pnum, int torture); -int ubi_wl_flush(struct ubi_device *ubi); +int ubi_wl_get_peb(struct ubi_device *ubi); +int ubi_wl_put_peb(struct ubi_device *ubi, int vol_id, int lnum, + int pnum, int torture); +int ubi_wl_flush(struct ubi_device *ubi, int vol_id, int lnum); int ubi_wl_scrub_peb(struct ubi_device *ubi, int pnum); -int ubi_wl_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si); +int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai); void ubi_wl_close(struct ubi_device *ubi); int ubi_thread(void *u); +struct ubi_wl_entry *ubi_wl_get_fm_peb(struct ubi_device *ubi, int anchor); +int ubi_wl_put_fm_peb(struct ubi_device *ubi, struct ubi_wl_entry *used_e, + int lnum, int torture); +int ubi_is_erase_work(struct ubi_work *wrk); +void ubi_refill_pools(struct ubi_device *ubi); +int ubi_ensure_anchor_pebs(struct ubi_device *ubi); /* io.c */ int ubi_io_read(const struct ubi_device *ubi, void *buf, int pnum, int offset, @@ -512,16 +854,57 @@ int ubi_io_write_vid_hdr(struct ubi_device *ubi, int pnum, struct ubi_vid_hdr *vid_hdr); /* build.c */ -int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset); +int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, + int vid_hdr_offset, int max_beb_per1024); int ubi_detach_mtd_dev(int ubi_num, int anyway); struct ubi_device *ubi_get_device(int ubi_num); void ubi_put_device(struct ubi_device *ubi); struct ubi_device *ubi_get_by_major(int major); int ubi_major2num(int major); +int ubi_volume_notify(struct ubi_device *ubi, struct ubi_volume *vol, + int ntype); +int ubi_notify_all(struct ubi_device *ubi, int ntype, + struct notifier_block *nb); +int ubi_enumerate_volumes(struct notifier_block *nb); +void ubi_free_internal_volumes(struct ubi_device *ubi); + +/* kapi.c */ +void ubi_do_get_device_info(struct ubi_device *ubi, struct ubi_device_info *di); +void ubi_do_get_volume_info(struct ubi_device *ubi, struct ubi_volume *vol, + struct ubi_volume_info *vi); +/* scan.c */ +int ubi_compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb, + int pnum, const struct ubi_vid_hdr *vid_hdr); + +/* fastmap.c */ +size_t ubi_calc_fm_size(struct ubi_device *ubi); +int ubi_update_fastmap(struct ubi_device *ubi); +int ubi_scan_fastmap(struct ubi_device *ubi, struct ubi_attach_info *ai, + int fm_anchor); + +/* block.c */ +#ifdef CONFIG_MTD_UBI_BLOCK +int ubiblock_init(void); +void ubiblock_exit(void); +int ubiblock_create(struct ubi_volume_info *vi); +int ubiblock_remove(struct ubi_volume_info *vi); +#else +static inline int ubiblock_init(void) { return 0; } +static inline void ubiblock_exit(void) {} +static inline int ubiblock_create(struct ubi_volume_info *vi) +{ + return -ENOSYS; +} +static inline int ubiblock_remove(struct ubi_volume_info *vi) +{ + return -ENOSYS; +} +#endif + /* * ubi_rb_for_each_entry - walk an RB-tree. - * @rb: a pointer to type 'struct rb_node' to to use as a loop counter + * @rb: a pointer to type 'struct rb_node' to use as a loop counter * @pos: a pointer to RB-tree entry type to use as a loop counter * @root: RB-tree's root * @member: the name of the 'struct rb_node' within the RB-tree entry @@ -530,7 +913,23 @@ int ubi_major2num(int major); for (rb = rb_first(root), \ pos = (rb ? container_of(rb, typeof(*pos), member) : NULL); \ rb; \ - rb = rb_next(rb), pos = container_of(rb, typeof(*pos), member)) + rb = rb_next(rb), \ + pos = (rb ? container_of(rb, typeof(*pos), member) : NULL)) + +/* + * ubi_move_aeb_to_list - move a PEB from the volume tree to a list. + * + * @av: volume attaching information + * @aeb: attaching eraseblock information + * @list: the list to move to + */ +static inline void ubi_move_aeb_to_list(struct ubi_ainf_volume *av, + struct ubi_ainf_peb *aeb, + struct list_head *list) +{ + rb_erase(&aeb->u.rb, &av->root); + list_add_tail(&aeb->u.list, list); +} /** * ubi_zalloc_vid_hdr - allocate a volume identifier header object. @@ -606,6 +1005,7 @@ static inline void ubi_ro_mode(struct ubi_device *ubi) if (!ubi->ro_mode) { ubi->ro_mode = 1; ubi_warn("switch to read-only mode"); + dump_stack(); } } diff --git a/drivers/mtd/ubi/upd.c b/drivers/mtd/ubi/upd.c index e597f82b87..c52c9ce776 100644 --- a/drivers/mtd/ubi/upd.c +++ b/drivers/mtd/ubi/upd.c @@ -26,13 +26,15 @@ * transaction with a roll-back capability. */ -#ifdef UBI_LINUX -#include -#include -#include +#ifndef __UBOOT__ +#include +#else +#include +#include #endif +#include +#include -#include #include "ubi.h" /** @@ -48,22 +50,21 @@ static int set_update_marker(struct ubi_device *ubi, struct ubi_volume *vol) int err; struct ubi_vtbl_record vtbl_rec; - dbg_msg("set update marker for volume %d", vol->vol_id); + dbg_gen("set update marker for volume %d", vol->vol_id); if (vol->upd_marker) { ubi_assert(ubi->vtbl[vol->vol_id].upd_marker); - dbg_msg("already set"); + dbg_gen("already set"); return 0; } - memcpy(&vtbl_rec, &ubi->vtbl[vol->vol_id], - sizeof(struct ubi_vtbl_record)); + vtbl_rec = ubi->vtbl[vol->vol_id]; vtbl_rec.upd_marker = 1; - mutex_lock(&ubi->volumes_mutex); + mutex_lock(&ubi->device_mutex); err = ubi_change_vtbl_record(ubi, vol->vol_id, &vtbl_rec); - mutex_unlock(&ubi->volumes_mutex); vol->upd_marker = 1; + mutex_unlock(&ubi->device_mutex); return err; } @@ -81,31 +82,29 @@ static int clear_update_marker(struct ubi_device *ubi, struct ubi_volume *vol, long long bytes) { int err; - uint64_t tmp; struct ubi_vtbl_record vtbl_rec; - dbg_msg("clear update marker for volume %d", vol->vol_id); + dbg_gen("clear update marker for volume %d", vol->vol_id); - memcpy(&vtbl_rec, &ubi->vtbl[vol->vol_id], - sizeof(struct ubi_vtbl_record)); + vtbl_rec = ubi->vtbl[vol->vol_id]; ubi_assert(vol->upd_marker && vtbl_rec.upd_marker); vtbl_rec.upd_marker = 0; if (vol->vol_type == UBI_STATIC_VOLUME) { vol->corrupted = 0; - vol->used_bytes = tmp = bytes; - vol->last_eb_bytes = do_div(tmp, vol->usable_leb_size); - vol->used_ebs = tmp; + vol->used_bytes = bytes; + vol->used_ebs = div_u64_rem(bytes, vol->usable_leb_size, + &vol->last_eb_bytes); if (vol->last_eb_bytes) vol->used_ebs += 1; else vol->last_eb_bytes = vol->usable_leb_size; } - mutex_lock(&ubi->volumes_mutex); + mutex_lock(&ubi->device_mutex); err = ubi_change_vtbl_record(ubi, vol->vol_id, &vtbl_rec); - mutex_unlock(&ubi->volumes_mutex); vol->upd_marker = 0; + mutex_unlock(&ubi->device_mutex); return err; } @@ -123,9 +122,8 @@ int ubi_start_update(struct ubi_device *ubi, struct ubi_volume *vol, long long bytes) { int i, err; - uint64_t tmp; - dbg_msg("start update of volume %d, %llu bytes", vol->vol_id, bytes); + dbg_gen("start update of volume %d, %llu bytes", vol->vol_id, bytes); ubi_assert(!vol->updating && !vol->changing_leb); vol->updating = 1; @@ -141,21 +139,23 @@ int ubi_start_update(struct ubi_device *ubi, struct ubi_volume *vol, } if (bytes == 0) { + err = ubi_wl_flush(ubi, UBI_ALL, UBI_ALL); + if (err) + return err; + err = clear_update_marker(ubi, vol, 0); if (err) return err; - err = ubi_wl_flush(ubi); - if (!err) - vol->updating = 0; + vol->updating = 0; + return 0; } vol->upd_buf = vmalloc(ubi->leb_size); if (!vol->upd_buf) return -ENOMEM; - tmp = bytes; - vol->upd_ebs = !!do_div(tmp, vol->usable_leb_size); - vol->upd_ebs += tmp; + vol->upd_ebs = div_u64(bytes + vol->usable_leb_size - 1, + vol->usable_leb_size); vol->upd_bytes = bytes; vol->upd_received = 0; return 0; @@ -175,17 +175,15 @@ int ubi_start_leb_change(struct ubi_device *ubi, struct ubi_volume *vol, { ubi_assert(!vol->updating && !vol->changing_leb); - dbg_msg("start changing LEB %d:%d, %u bytes", + dbg_gen("start changing LEB %d:%d, %u bytes", vol->vol_id, req->lnum, req->bytes); if (req->bytes == 0) - return ubi_eba_atomic_leb_change(ubi, vol, req->lnum, NULL, 0, - req->dtype); + return ubi_eba_atomic_leb_change(ubi, vol, req->lnum, NULL, 0); vol->upd_bytes = req->bytes; vol->upd_received = 0; vol->changing_leb = 1; vol->ch_lnum = req->lnum; - vol->ch_dtype = req->dtype; vol->upd_buf = vmalloc(req->bytes); if (!vol->upd_buf) @@ -234,11 +232,11 @@ static int write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, memset(buf + len, 0xFF, l - len); len = ubi_calc_data_len(ubi, buf, l); if (len == 0) { - dbg_msg("all %d bytes contain 0xFF - skip", len); + dbg_gen("all %d bytes contain 0xFF - skip", len); return 0; } - err = ubi_eba_write_leb(ubi, vol, lnum, buf, 0, len, UBI_UNKNOWN); + err = ubi_eba_write_leb(ubi, vol, lnum, buf, 0, len); } else { /* * When writing static volume, and this is the last logical @@ -250,8 +248,7 @@ static int write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, * contain zeros, not random trash. */ memset(buf + len, 0, vol->usable_leb_size - len); - err = ubi_eba_write_leb_st(ubi, vol, lnum, buf, len, - UBI_UNKNOWN, used_ebs); + err = ubi_eba_write_leb_st(ubi, vol, lnum, buf, len, used_ebs); } return err; @@ -259,6 +256,7 @@ static int write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, /** * ubi_more_update_data - write more update data. + * @ubi: UBI device description object * @vol: volume description object * @buf: write data (user-space memory buffer) * @count: how much bytes to write @@ -272,19 +270,20 @@ static int write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, int ubi_more_update_data(struct ubi_device *ubi, struct ubi_volume *vol, const void __user *buf, int count) { - uint64_t tmp; +#ifndef __UBOOT__ int lnum, offs, err = 0, len, to_write = count; +#else + int lnum, err = 0, len, to_write = count; + u32 offs; +#endif - dbg_msg("write %d of %lld bytes, %lld already passed", + dbg_gen("write %d of %lld bytes, %lld already passed", count, vol->upd_bytes, vol->upd_received); if (ubi->ro_mode) return -EROFS; - tmp = vol->upd_received; - offs = do_div(tmp, vol->usable_leb_size); - lnum = tmp; - + lnum = div_u64_rem(vol->upd_received, vol->usable_leb_size, &offs); if (vol->upd_received + count > vol->upd_bytes) to_write = count = vol->upd_bytes - vol->upd_received; @@ -359,16 +358,16 @@ int ubi_more_update_data(struct ubi_device *ubi, struct ubi_volume *vol, ubi_assert(vol->upd_received <= vol->upd_bytes); if (vol->upd_received == vol->upd_bytes) { + err = ubi_wl_flush(ubi, UBI_ALL, UBI_ALL); + if (err) + return err; /* The update is finished, clear the update marker */ err = clear_update_marker(ubi, vol, vol->upd_bytes); if (err) return err; - err = ubi_wl_flush(ubi); - if (err == 0) { - vol->updating = 0; - err = to_write; - vfree(vol->upd_buf); - } + vol->updating = 0; + err = to_write; + vfree(vol->upd_buf); } return err; @@ -376,6 +375,7 @@ int ubi_more_update_data(struct ubi_device *ubi, struct ubi_volume *vol, /** * ubi_more_leb_change_data - accept more data for atomic LEB change. + * @ubi: UBI device description object * @vol: volume description object * @buf: write data (user-space memory buffer) * @count: how much bytes to write @@ -392,7 +392,7 @@ int ubi_more_leb_change_data(struct ubi_device *ubi, struct ubi_volume *vol, { int err; - dbg_msg("write %d of %lld bytes, %lld already passed", + dbg_gen("write %d of %lld bytes, %lld already passed", count, vol->upd_bytes, vol->upd_received); if (ubi->ro_mode) @@ -410,10 +410,11 @@ int ubi_more_leb_change_data(struct ubi_device *ubi, struct ubi_volume *vol, if (vol->upd_received == vol->upd_bytes) { int len = ALIGN((int)vol->upd_bytes, ubi->min_io_size); - memset(vol->upd_buf + vol->upd_bytes, 0xFF, len - vol->upd_bytes); + memset(vol->upd_buf + vol->upd_bytes, 0xFF, + len - vol->upd_bytes); len = ubi_calc_data_len(ubi, vol->upd_buf, len); err = ubi_eba_atomic_leb_change(ubi, vol, vol->ch_lnum, - vol->upd_buf, len, UBI_UNKNOWN); + vol->upd_buf, len); if (err) return err; } diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index c4e894b43a..f4392f5969 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -11,21 +11,21 @@ * resizing. */ -#ifdef UBI_LINUX +#ifndef __UBOOT__ #include -#include +#include +#include +#else +#include +#include #endif +#include -#include #include "ubi.h" -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID -static void paranoid_check_volumes(struct ubi_device *ubi); -#else -#define paranoid_check_volumes(ubi) -#endif +static int self_check_volumes(struct ubi_device *ubi); -#ifdef UBI_LINUX +#ifndef __UBOOT__ static ssize_t vol_attribute_show(struct device *dev, struct device_attribute *attr, char *buf); @@ -121,10 +121,11 @@ static void vol_release(struct device *dev) { struct ubi_volume *vol = container_of(dev, struct ubi_volume, dev); + kfree(vol->eba_tbl); kfree(vol); } -#ifdef UBI_LINUX +#ifndef __UBOOT__ /** * volume_sysfs_init - initialize sysfs for new volume. * @ubi: UBI device description object @@ -193,14 +194,13 @@ static void volume_sysfs_close(struct ubi_volume *vol) * %UBI_VOL_NUM_AUTO, this function automatically assign ID to the new volume * and saves it in @req->vol_id. Returns zero in case of success and a negative * error code in case of failure. Note, the caller has to have the - * @ubi->volumes_mutex locked. + * @ubi->device_mutex locked. */ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) { - int i, err, vol_id = req->vol_id, dont_free = 0; + int i, err, vol_id = req->vol_id, do_free = 1; struct ubi_volume *vol; struct ubi_vtbl_record vtbl_rec; - uint64_t bytes; dev_t dev; if (ubi->ro_mode) @@ -213,7 +213,7 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) spin_lock(&ubi->volumes_lock); if (vol_id == UBI_VOL_NUM_AUTO) { /* Find unused volume ID */ - dbg_msg("search for vacant volume ID"); + dbg_gen("search for vacant volume ID"); for (i = 0; i < ubi->vtbl_slots; i++) if (!ubi->volumes[i]) { vol_id = i; @@ -221,21 +221,21 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) } if (vol_id == UBI_VOL_NUM_AUTO) { - dbg_err("out of volume IDs"); + ubi_err("out of volume IDs"); err = -ENFILE; goto out_unlock; } req->vol_id = vol_id; } - dbg_msg("volume ID %d, %llu bytes, type %d, name %s", - vol_id, (unsigned long long)req->bytes, + dbg_gen("create device %d, volume %d, %llu bytes, type %d, name %s", + ubi->ubi_num, vol_id, (unsigned long long)req->bytes, (int)req->vol_type, req->name); /* Ensure that this volume does not exist */ err = -EEXIST; if (ubi->volumes[vol_id]) { - dbg_err("volume %d already exists", vol_id); + ubi_err("volume %d already exists", vol_id); goto out_unlock; } @@ -244,20 +244,21 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) if (ubi->volumes[i] && ubi->volumes[i]->name_len == req->name_len && !strcmp(ubi->volumes[i]->name, req->name)) { - dbg_err("volume \"%s\" exists (ID %d)", req->name, i); + ubi_err("volume \"%s\" exists (ID %d)", req->name, i); goto out_unlock; } /* Calculate how many eraseblocks are requested */ vol->usable_leb_size = ubi->leb_size - ubi->leb_size % req->alignment; - bytes = req->bytes; - if (do_div(bytes, vol->usable_leb_size)) - vol->reserved_pebs = 1; - vol->reserved_pebs += bytes; + vol->reserved_pebs += div_u64(req->bytes + vol->usable_leb_size - 1, + vol->usable_leb_size); /* Reserve physical eraseblocks */ if (vol->reserved_pebs > ubi->avail_pebs) { - dbg_err("not enough PEBs, only %d available", ubi->avail_pebs); + ubi_err("not enough PEBs, only %d available", ubi->avail_pebs); + if (ubi->corr_peb_count) + ubi_err("%d PEBs are corrupted and not used", + ubi->corr_peb_count); err = -ENOSPC; goto out_unlock; } @@ -270,14 +271,14 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) vol->data_pad = ubi->leb_size % vol->alignment; vol->vol_type = req->vol_type; vol->name_len = req->name_len; - memcpy(vol->name, req->name, vol->name_len + 1); + memcpy(vol->name, req->name, vol->name_len); vol->ubi = ubi; /* * Finish all pending erases because there may be some LEBs belonging * to the same volume ID. */ - err = ubi_wl_flush(ubi); + err = ubi_wl_flush(ubi, vol_id, UBI_ALL); if (err) goto out_acc; @@ -296,10 +297,10 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) vol->used_bytes = (long long)vol->used_ebs * vol->usable_leb_size; } else { - bytes = vol->used_bytes; - vol->last_eb_bytes = do_div(bytes, vol->usable_leb_size); - vol->used_ebs = bytes; - if (vol->last_eb_bytes) + vol->used_ebs = div_u64_rem(vol->used_bytes, + vol->usable_leb_size, + &vol->last_eb_bytes); + if (vol->last_eb_bytes != 0) vol->used_ebs += 1; else vol->last_eb_bytes = vol->usable_leb_size; @@ -315,20 +316,16 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) goto out_mapping; } - err = ubi_create_gluebi(ubi, vol); - if (err) - goto out_cdev; - vol->dev.release = vol_release; vol->dev.parent = &ubi->dev; vol->dev.devt = dev; vol->dev.class = ubi_class; - sprintf(&vol->dev.bus_id[0], "%s_%d", ubi->ubi_name, vol->vol_id); + dev_set_name(&vol->dev, "%s_%d", ubi->ubi_name, vol->vol_id); err = device_register(&vol->dev); if (err) { ubi_err("cannot register device"); - goto out_gluebi; + goto out_cdev; } err = volume_sysfs_init(ubi, vol); @@ -345,7 +342,7 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) vtbl_rec.vol_type = UBI_VID_DYNAMIC; else vtbl_rec.vol_type = UBI_VID_STATIC; - memcpy(vtbl_rec.name, vol->name, vol->name_len + 1); + memcpy(vtbl_rec.name, vol->name, vol->name_len); err = ubi_change_vtbl_record(ubi, vol_id, &vtbl_rec); if (err) @@ -356,39 +353,37 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) ubi->vol_count += 1; spin_unlock(&ubi->volumes_lock); - paranoid_check_volumes(ubi); - return 0; + ubi_volume_notify(ubi, vol, UBI_VOLUME_ADDED); + self_check_volumes(ubi); + return err; out_sysfs: /* - * We have registered our device, we should not free the volume* + * We have registered our device, we should not free the volume * description object in this function in case of an error - it is * freed by the release function. * * Get device reference to prevent the release function from being * called just after sysfs has been closed. */ - dont_free = 1; + do_free = 0; get_device(&vol->dev); volume_sysfs_close(vol); -out_gluebi: - if (ubi_destroy_gluebi(vol)) - dbg_err("cannot destroy gluebi for volume %d:%d", - ubi->ubi_num, vol_id); out_cdev: cdev_del(&vol->cdev); out_mapping: - kfree(vol->eba_tbl); + if (do_free) + kfree(vol->eba_tbl); out_acc: spin_lock(&ubi->volumes_lock); ubi->rsvd_pebs -= vol->reserved_pebs; ubi->avail_pebs += vol->reserved_pebs; out_unlock: spin_unlock(&ubi->volumes_lock); - if (dont_free) - put_device(&vol->dev); - else + if (do_free) kfree(vol); + else + put_device(&vol->dev); ubi_err("cannot create volume %d, error %d", vol_id, err); return err; } @@ -396,19 +391,20 @@ out_unlock: /** * ubi_remove_volume - remove volume. * @desc: volume descriptor + * @no_vtbl: do not change volume table if not zero * * This function removes volume described by @desc. The volume has to be opened * in "exclusive" mode. Returns zero in case of success and a negative error - * code in case of failure. The caller has to have the @ubi->volumes_mutex + * code in case of failure. The caller has to have the @ubi->device_mutex * locked. */ -int ubi_remove_volume(struct ubi_volume_desc *desc) +int ubi_remove_volume(struct ubi_volume_desc *desc, int no_vtbl) { struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; int i, err, vol_id = vol->vol_id, reserved_pebs = vol->reserved_pebs; - dbg_msg("remove UBI volume %d", vol_id); + dbg_gen("remove device %d, volume %d", ubi->ubi_num, vol_id); ubi_assert(desc->mode == UBI_EXCLUSIVE); ubi_assert(vol == ubi->volumes[vol_id]); @@ -427,13 +423,11 @@ int ubi_remove_volume(struct ubi_volume_desc *desc) ubi->volumes[vol_id] = NULL; spin_unlock(&ubi->volumes_lock); - err = ubi_destroy_gluebi(vol); - if (err) - goto out_err; - - err = ubi_change_vtbl_record(ubi, vol_id, NULL); - if (err) - goto out_err; + if (!no_vtbl) { + err = ubi_change_vtbl_record(ubi, vol_id, NULL); + if (err) + goto out_err; + } for (i = 0; i < vol->reserved_pebs; i++) { err = ubi_eba_unmap_leb(ubi, vol, i); @@ -441,28 +435,21 @@ int ubi_remove_volume(struct ubi_volume_desc *desc) goto out_err; } - kfree(vol->eba_tbl); - vol->eba_tbl = NULL; cdev_del(&vol->cdev); volume_sysfs_close(vol); spin_lock(&ubi->volumes_lock); ubi->rsvd_pebs -= reserved_pebs; ubi->avail_pebs += reserved_pebs; - i = ubi->beb_rsvd_level - ubi->beb_rsvd_pebs; - if (i > 0) { - i = ubi->avail_pebs >= i ? i : ubi->avail_pebs; - ubi->avail_pebs -= i; - ubi->rsvd_pebs += i; - ubi->beb_rsvd_pebs += i; - if (i > 0) - ubi_msg("reserve more %d PEBs", i); - } + ubi_update_reserved(ubi); ubi->vol_count -= 1; spin_unlock(&ubi->volumes_lock); - paranoid_check_volumes(ubi); - return 0; + ubi_volume_notify(ubi, vol, UBI_VOLUME_REMOVED); + if (!no_vtbl) + self_check_volumes(ubi); + + return err; out_err: ubi_err("cannot remove volume %d, error %d", vol_id, err); @@ -480,7 +467,7 @@ out_unlock: * * This function re-sizes the volume and returns zero in case of success, and a * negative error code in case of failure. The caller has to have the - * @ubi->volumes_mutex locked. + * @ubi->device_mutex locked. */ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) { @@ -493,12 +480,12 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) if (ubi->ro_mode) return -EROFS; - dbg_msg("re-size volume %d to from %d to %d PEBs", - vol_id, vol->reserved_pebs, reserved_pebs); + dbg_gen("re-size device %d, volume %d to from %d to %d PEBs", + ubi->ubi_num, vol_id, vol->reserved_pebs, reserved_pebs); if (vol->vol_type == UBI_STATIC_VOLUME && reserved_pebs < vol->used_ebs) { - dbg_err("too small size %d, %d LEBs contain data", + ubi_err("too small size %d, %d LEBs contain data", reserved_pebs, vol->used_ebs); return -EINVAL; } @@ -527,8 +514,11 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) if (pebs > 0) { spin_lock(&ubi->volumes_lock); if (pebs > ubi->avail_pebs) { - dbg_err("not enough PEBs: requested %d, available %d", + ubi_err("not enough PEBs: requested %d, available %d", pebs, ubi->avail_pebs); + if (ubi->corr_peb_count) + ubi_err("%d PEBs are corrupted and not used", + ubi->corr_peb_count); spin_unlock(&ubi->volumes_lock); err = -ENOSPC; goto out_free; @@ -543,7 +533,7 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) } /* Change volume table record */ - memcpy(&vtbl_rec, &ubi->vtbl[vol_id], sizeof(struct ubi_vtbl_record)); + vtbl_rec = ubi->vtbl[vol_id]; vtbl_rec.reserved_pebs = cpu_to_be32(reserved_pebs); err = ubi_change_vtbl_record(ubi, vol_id, &vtbl_rec); if (err) @@ -558,15 +548,7 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) spin_lock(&ubi->volumes_lock); ubi->rsvd_pebs += pebs; ubi->avail_pebs -= pebs; - pebs = ubi->beb_rsvd_level - ubi->beb_rsvd_pebs; - if (pebs > 0) { - pebs = ubi->avail_pebs >= pebs ? pebs : ubi->avail_pebs; - ubi->avail_pebs -= pebs; - ubi->rsvd_pebs += pebs; - ubi->beb_rsvd_pebs += pebs; - if (pebs > 0) - ubi_msg("reserve more %d PEBs", pebs); - } + ubi_update_reserved(ubi); for (i = 0; i < reserved_pebs; i++) new_mapping[i] = vol->eba_tbl[i]; kfree(vol->eba_tbl); @@ -582,8 +564,9 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) (long long)vol->used_ebs * vol->usable_leb_size; } - paranoid_check_volumes(ubi); - return 0; + ubi_volume_notify(ubi, vol, UBI_VOLUME_RESIZED); + self_check_volumes(ubi); + return err; out_acc: if (pebs > 0) { @@ -597,6 +580,45 @@ out_free: return err; } +/** + * ubi_rename_volumes - re-name UBI volumes. + * @ubi: UBI device description object + * @rename_list: list of &struct ubi_rename_entry objects + * + * This function re-names or removes volumes specified in the re-name list. + * Returns zero in case of success and a negative error code in case of + * failure. + */ +int ubi_rename_volumes(struct ubi_device *ubi, struct list_head *rename_list) +{ + int err; + struct ubi_rename_entry *re; + + err = ubi_vtbl_rename_volumes(ubi, rename_list); + if (err) + return err; + + list_for_each_entry(re, rename_list, list) { + if (re->remove) { + err = ubi_remove_volume(re->desc, 1); + if (err) + break; + } else { + struct ubi_volume *vol = re->desc->vol; + + spin_lock(&ubi->volumes_lock); + vol->name_len = re->new_name_len; + memcpy(vol->name, re->new_name, re->new_name_len + 1); + spin_unlock(&ubi->volumes_lock); + ubi_volume_notify(ubi, vol, UBI_VOLUME_RENAMED); + } + } + + if (!err) + self_check_volumes(ubi); + return err; +} + /** * ubi_add_volume - add volume. * @ubi: UBI device description object @@ -611,8 +633,7 @@ int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol) int err, vol_id = vol->vol_id; dev_t dev; - dbg_msg("add volume %d", vol_id); - ubi_dbg_dump_vol_info(vol); + dbg_gen("add volume %d", vol_id); /* Register character device for the volume */ cdev_init(&vol->cdev, &ubi_vol_cdev_operations); @@ -625,32 +646,25 @@ int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol) return err; } - err = ubi_create_gluebi(ubi, vol); - if (err) - goto out_cdev; - vol->dev.release = vol_release; vol->dev.parent = &ubi->dev; vol->dev.devt = dev; vol->dev.class = ubi_class; - sprintf(&vol->dev.bus_id[0], "%s_%d", ubi->ubi_name, vol->vol_id); + dev_set_name(&vol->dev, "%s_%d", ubi->ubi_name, vol->vol_id); err = device_register(&vol->dev); if (err) - goto out_gluebi; + goto out_cdev; err = volume_sysfs_init(ubi, vol); if (err) { cdev_del(&vol->cdev); - err = ubi_destroy_gluebi(vol); volume_sysfs_close(vol); return err; } - paranoid_check_volumes(ubi); - return 0; + self_check_volumes(ubi); + return err; -out_gluebi: - err = ubi_destroy_gluebi(vol); out_cdev: cdev_del(&vol->cdev); return err; @@ -666,22 +680,21 @@ out_cdev: */ void ubi_free_volume(struct ubi_device *ubi, struct ubi_volume *vol) { - dbg_msg("free volume %d", vol->vol_id); + dbg_gen("free volume %d", vol->vol_id); ubi->volumes[vol->vol_id] = NULL; - ubi_destroy_gluebi(vol); cdev_del(&vol->cdev); volume_sysfs_close(vol); } -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID - /** - * paranoid_check_volume - check volume information. + * self_check_volume - check volume information. * @ubi: UBI device description object * @vol_id: volume ID + * + * Returns zero if volume is all right and a a negative error code if not. */ -static void paranoid_check_volume(struct ubi_device *ubi, int vol_id) +static int self_check_volume(struct ubi_device *ubi, int vol_id) { int idx = vol_id2idx(ubi, vol_id); int reserved_pebs, alignment, data_pad, vol_type, name_len, upd_marker; @@ -699,16 +712,7 @@ static void paranoid_check_volume(struct ubi_device *ubi, int vol_id) goto fail; } spin_unlock(&ubi->volumes_lock); - return; - } - - if (vol->exclusive) { - /* - * The volume may be being created at the moment, do not check - * it (e.g., it may be in the middle of ubi_create_volume(). - */ - spin_unlock(&ubi->volumes_lock); - return; + return 0; } if (vol->reserved_pebs < 0 || vol->alignment < 0 || vol->data_pad < 0 || @@ -740,7 +744,7 @@ static void paranoid_check_volume(struct ubi_device *ubi, int vol_id) } if (vol->upd_marker && vol->corrupted) { - dbg_err("update marker and corrupted simultaneously"); + ubi_err("update marker and corrupted simultaneously"); goto fail; } @@ -760,11 +764,6 @@ static void paranoid_check_volume(struct ubi_device *ubi, int vol_id) goto fail; } - if (!vol->name) { - ubi_err("NULL volume name"); - goto fail; - } - n = strnlen(vol->name, vol->name_len + 1); if (n != vol->name_len) { ubi_err("bad name_len %lld", n); @@ -818,31 +817,42 @@ static void paranoid_check_volume(struct ubi_device *ubi, int vol_id) if (alignment != vol->alignment || data_pad != vol->data_pad || upd_marker != vol->upd_marker || vol_type != vol->vol_type || - name_len!= vol->name_len || strncmp(name, vol->name, name_len)) { + name_len != vol->name_len || strncmp(name, vol->name, name_len)) { ubi_err("volume info is different"); goto fail; } spin_unlock(&ubi->volumes_lock); - return; + return 0; fail: - ubi_err("paranoid check failed for volume %d", vol_id); - ubi_dbg_dump_vol_info(vol); - ubi_dbg_dump_vtbl_record(&ubi->vtbl[vol_id], vol_id); + ubi_err("self-check failed for volume %d", vol_id); + if (vol) + ubi_dump_vol_info(vol); + ubi_dump_vtbl_record(&ubi->vtbl[vol_id], vol_id); + dump_stack(); spin_unlock(&ubi->volumes_lock); - BUG(); + return -EINVAL; } /** - * paranoid_check_volumes - check information about all volumes. + * self_check_volumes - check information about all volumes. * @ubi: UBI device description object + * + * Returns zero if volumes are all right and a a negative error code if not. */ -static void paranoid_check_volumes(struct ubi_device *ubi) +static int self_check_volumes(struct ubi_device *ubi) { - int i; + int i, err = 0; - for (i = 0; i < ubi->vtbl_slots; i++) - paranoid_check_volume(ubi, i); + if (!ubi_dbg_chk_gen(ubi)) + return 0; + + for (i = 0; i < ubi->vtbl_slots; i++) { + err = self_check_volume(ubi, i); + if (err) + break; + } + + return err; } -#endif diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c index 3fbb4a0a9d..ae8ea38c62 100644 --- a/drivers/mtd/ubi/vtbl.c +++ b/drivers/mtd/ubi/vtbl.c @@ -25,16 +25,15 @@ * LEB 1. This scheme guarantees recoverability from unclean reboots. * * In this UBI implementation the on-flash volume table does not contain any - * information about how many data static volumes contain. This information may - * be found from the scanning data. + * information about how much data static volumes contain. * * But it would still be beneficial to store this information in the volume * table. For example, suppose we have a static volume X, and all its physical * eraseblocks became bad for some reasons. Suppose we are attaching the - * corresponding MTD device, the scanning has found no logical eraseblocks + * corresponding MTD device, for some reason we find no logical eraseblocks * corresponding to the volume X. According to the volume table volume X does * exist. So we don't know whether it is just empty or all its physical - * eraseblocks went bad. So we cannot alarm the user about this corruption. + * eraseblocks went bad. So we cannot alarm the user properly. * * The volume table also stores so-called "update marker", which is used for * volume updates. Before updating the volume, the update marker is set, and @@ -44,20 +43,19 @@ * damaged. */ -#ifdef UBI_LINUX +#ifndef __UBOOT__ #include #include +#include #include +#else +#include #endif -#include +#include #include "ubi.h" -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID -static void paranoid_vtbl_check(const struct ubi_device *ubi); -#else -#define paranoid_vtbl_check(ubi) -#endif +static void self_vtbl_check(const struct ubi_device *ubi); /* Empty volume table record */ static struct ubi_vtbl_record empty_vtbl_record; @@ -97,18 +95,68 @@ int ubi_change_vtbl_record(struct ubi_device *ubi, int idx, return err; err = ubi_eba_write_leb(ubi, layout_vol, i, ubi->vtbl, 0, - ubi->vtbl_size, UBI_LONGTERM); + ubi->vtbl_size); + if (err) + return err; + } + + self_vtbl_check(ubi); + return 0; +} + +/** + * ubi_vtbl_rename_volumes - rename UBI volumes in the volume table. + * @ubi: UBI device description object + * @rename_list: list of &struct ubi_rename_entry objects + * + * This function re-names multiple volumes specified in @req in the volume + * table. Returns zero in case of success and a negative error code in case of + * failure. + */ +int ubi_vtbl_rename_volumes(struct ubi_device *ubi, + struct list_head *rename_list) +{ + int i, err; + struct ubi_rename_entry *re; + struct ubi_volume *layout_vol; + + list_for_each_entry(re, rename_list, list) { + uint32_t crc; + struct ubi_volume *vol = re->desc->vol; + struct ubi_vtbl_record *vtbl_rec = &ubi->vtbl[vol->vol_id]; + + if (re->remove) { + memcpy(vtbl_rec, &empty_vtbl_record, + sizeof(struct ubi_vtbl_record)); + continue; + } + + vtbl_rec->name_len = cpu_to_be16(re->new_name_len); + memcpy(vtbl_rec->name, re->new_name, re->new_name_len); + memset(vtbl_rec->name + re->new_name_len, 0, + UBI_VOL_NAME_MAX + 1 - re->new_name_len); + crc = crc32(UBI_CRC32_INIT, vtbl_rec, + UBI_VTBL_RECORD_SIZE_CRC); + vtbl_rec->crc = cpu_to_be32(crc); + } + + layout_vol = ubi->volumes[vol_id2idx(ubi, UBI_LAYOUT_VOLUME_ID)]; + for (i = 0; i < UBI_LAYOUT_VOLUME_EBS; i++) { + err = ubi_eba_unmap_leb(ubi, layout_vol, i); + if (err) + return err; + + err = ubi_eba_write_leb(ubi, layout_vol, i, ubi->vtbl, 0, + ubi->vtbl_size); if (err) return err; } - paranoid_vtbl_check(ubi); return 0; } /** - * vtbl_check - check if volume table is not corrupted and contains sensible - * data. + * vtbl_check - check if volume table is not corrupted and sensible. * @ubi: UBI device description object * @vtbl: volume table * @@ -132,13 +180,13 @@ static int vtbl_check(const struct ubi_device *ubi, upd_marker = vtbl[i].upd_marker; vol_type = vtbl[i].vol_type; name_len = be16_to_cpu(vtbl[i].name_len); - name = (const char *) &vtbl[i].name[0]; + name = &vtbl[i].name[0]; crc = crc32(UBI_CRC32_INIT, &vtbl[i], UBI_VTBL_RECORD_SIZE_CRC); if (be32_to_cpu(vtbl[i].crc) != crc) { ubi_err("bad CRC at record %u: %#08x, not %#08x", i, crc, be32_to_cpu(vtbl[i].crc)); - ubi_dbg_dump_vtbl_record(&vtbl[i], i); + ubi_dump_vtbl_record(&vtbl[i], i); return 1; } @@ -170,7 +218,7 @@ static int vtbl_check(const struct ubi_device *ubi, n = ubi->leb_size % alignment; if (data_pad != n) { - dbg_err("bad data_pad, has to be %d", n); + ubi_err("bad data_pad, has to be %d", n); err = 6; goto bad; } @@ -186,8 +234,8 @@ static int vtbl_check(const struct ubi_device *ubi, } if (reserved_pebs > ubi->good_peb_count) { - dbg_err("too large reserved_pebs, good PEBs %d", - ubi->good_peb_count); + ubi_err("too large reserved_pebs %d, good PEBs %d", + reserved_pebs, ubi->good_peb_count); err = 9; goto bad; } @@ -215,11 +263,15 @@ static int vtbl_check(const struct ubi_device *ubi, int len2 = be16_to_cpu(vtbl[n].name_len); if (len1 > 0 && len1 == len2 && - !strncmp((char *)vtbl[i].name, (char *)vtbl[n].name, len1)) { - ubi_err("volumes %d and %d have the same name" - " \"%s\"", i, n, vtbl[i].name); - ubi_dbg_dump_vtbl_record(&vtbl[i], i); - ubi_dbg_dump_vtbl_record(&vtbl[n], n); +#ifndef __UBOOT__ + !strncmp(vtbl[i].name, vtbl[n].name, len1)) { +#else + !strncmp((char *)vtbl[i].name, vtbl[n].name, len1)) { +#endif + ubi_err("volumes %d and %d have the same name \"%s\"", + i, n, vtbl[i].name); + ubi_dump_vtbl_record(&vtbl[i], i); + ubi_dump_vtbl_record(&vtbl[n], n); return -EINVAL; } } @@ -229,76 +281,64 @@ static int vtbl_check(const struct ubi_device *ubi, bad: ubi_err("volume table check failed: record %d, error %d", i, err); - ubi_dbg_dump_vtbl_record(&vtbl[i], i); + ubi_dump_vtbl_record(&vtbl[i], i); return -EINVAL; } /** * create_vtbl - create a copy of volume table. * @ubi: UBI device description object - * @si: scanning information + * @ai: attaching information * @copy: number of the volume table copy * @vtbl: contents of the volume table * * This function returns zero in case of success and a negative error code in * case of failure. */ -static int create_vtbl(struct ubi_device *ubi, struct ubi_scan_info *si, +static int create_vtbl(struct ubi_device *ubi, struct ubi_attach_info *ai, int copy, void *vtbl) { int err, tries = 0; - static struct ubi_vid_hdr *vid_hdr; - struct ubi_scan_volume *sv; - struct ubi_scan_leb *new_seb, *old_seb = NULL; + struct ubi_vid_hdr *vid_hdr; + struct ubi_ainf_peb *new_aeb; - ubi_msg("create volume table (copy #%d)", copy + 1); + dbg_gen("create volume table (copy #%d)", copy + 1); vid_hdr = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL); if (!vid_hdr) return -ENOMEM; - /* - * Check if there is a logical eraseblock which would have to contain - * this volume table copy was found during scanning. It has to be wiped - * out. - */ - sv = ubi_scan_find_sv(si, UBI_LAYOUT_VOLUME_ID); - if (sv) - old_seb = ubi_scan_find_seb(sv, copy); - retry: - new_seb = ubi_scan_get_free_peb(ubi, si); - if (IS_ERR(new_seb)) { - err = PTR_ERR(new_seb); + new_aeb = ubi_early_get_peb(ubi, ai); + if (IS_ERR(new_aeb)) { + err = PTR_ERR(new_aeb); goto out_free; } - vid_hdr->vol_type = UBI_VID_DYNAMIC; + vid_hdr->vol_type = UBI_LAYOUT_VOLUME_TYPE; vid_hdr->vol_id = cpu_to_be32(UBI_LAYOUT_VOLUME_ID); vid_hdr->compat = UBI_LAYOUT_VOLUME_COMPAT; vid_hdr->data_size = vid_hdr->used_ebs = vid_hdr->data_pad = cpu_to_be32(0); vid_hdr->lnum = cpu_to_be32(copy); - vid_hdr->sqnum = cpu_to_be64(++si->max_sqnum); - vid_hdr->leb_ver = cpu_to_be32(old_seb ? old_seb->leb_ver + 1: 0); + vid_hdr->sqnum = cpu_to_be64(++ai->max_sqnum); /* The EC header is already there, write the VID header */ - err = ubi_io_write_vid_hdr(ubi, new_seb->pnum, vid_hdr); + err = ubi_io_write_vid_hdr(ubi, new_aeb->pnum, vid_hdr); if (err) goto write_error; /* Write the layout volume contents */ - err = ubi_io_write_data(ubi, vtbl, new_seb->pnum, 0, ubi->vtbl_size); + err = ubi_io_write_data(ubi, vtbl, new_aeb->pnum, 0, ubi->vtbl_size); if (err) goto write_error; /* - * And add it to the scanning information. Don't delete the old - * @old_seb as it will be deleted and freed in 'ubi_scan_add_used()'. + * And add it to the attaching information. Don't delete the old version + * of this LEB as it will be deleted and freed in 'ubi_add_to_av()'. */ - err = ubi_scan_add_used(ubi, si, new_seb->pnum, new_seb->ec, - vid_hdr, 0); - kfree(new_seb); + err = ubi_add_to_av(ubi, ai, new_aeb->pnum, new_aeb->ec, vid_hdr, 0); + kmem_cache_free(ai->aeb_slab_cache, new_aeb); ubi_free_vid_hdr(ubi, vid_hdr); return err; @@ -308,10 +348,10 @@ write_error: * Probably this physical eraseblock went bad, try to pick * another one. */ - list_add_tail(&new_seb->u.list, &si->corr); + list_add(&new_aeb->u.list, &ai->erase); goto retry; } - kfree(new_seb); + kmem_cache_free(ai->aeb_slab_cache, new_aeb); out_free: ubi_free_vid_hdr(ubi, vid_hdr); return err; @@ -321,20 +361,20 @@ out_free: /** * process_lvol - process the layout volume. * @ubi: UBI device description object - * @si: scanning information - * @sv: layout volume scanning information + * @ai: attaching information + * @av: layout volume attaching information * * This function is responsible for reading the layout volume, ensuring it is * not corrupted, and recovering from corruptions if needed. Returns volume * table in case of success and a negative error code in case of failure. */ static struct ubi_vtbl_record *process_lvol(struct ubi_device *ubi, - struct ubi_scan_info *si, - struct ubi_scan_volume *sv) + struct ubi_attach_info *ai, + struct ubi_ainf_volume *av) { int err; struct rb_node *rb; - struct ubi_scan_leb *seb; + struct ubi_ainf_peb *aeb; struct ubi_vtbl_record *leb[UBI_LAYOUT_VOLUME_EBS] = { NULL, NULL }; int leb_corrupted[UBI_LAYOUT_VOLUME_EBS] = {1, 1}; @@ -356,25 +396,24 @@ static struct ubi_vtbl_record *process_lvol(struct ubi_device *ubi, * 0 contains more recent information. * * So the plan is to first check LEB 0. Then - * a. if LEB 0 is OK, it must be containing the most resent data; then + * a. if LEB 0 is OK, it must be containing the most recent data; then * we compare it with LEB 1, and if they are different, we copy LEB * 0 to LEB 1; * b. if LEB 0 is corrupted, but LEB 1 has to be OK, and we copy LEB 1 * to LEB 0. */ - dbg_msg("check layout volume"); + dbg_gen("check layout volume"); /* Read both LEB 0 and LEB 1 into memory */ - ubi_rb_for_each_entry(rb, seb, &sv->root, u.rb) { - leb[seb->lnum] = vmalloc(ubi->vtbl_size); - if (!leb[seb->lnum]) { + ubi_rb_for_each_entry(rb, aeb, &av->root, u.rb) { + leb[aeb->lnum] = vzalloc(ubi->vtbl_size); + if (!leb[aeb->lnum]) { err = -ENOMEM; goto out_free; } - memset(leb[seb->lnum], 0, ubi->vtbl_size); - err = ubi_io_read_data(ubi, leb[seb->lnum], seb->pnum, 0, + err = ubi_io_read_data(ubi, leb[aeb->lnum], aeb->pnum, 0, ubi->vtbl_size); if (err == UBI_IO_BITFLIPS || mtd_is_eccerr(err)) /* @@ -382,12 +421,12 @@ static struct ubi_vtbl_record *process_lvol(struct ubi_device *ubi, * uncorrectable ECC error, but we have our own CRC and * the data will be checked later. If the data is OK, * the PEB will be scrubbed (because we set - * seb->scrub). If the data is not OK, the contents of + * aeb->scrub). If the data is not OK, the contents of * the PEB will be recovered from the second copy, and - * seb->scrub will be cleared in - * 'ubi_scan_add_used()'. + * aeb->scrub will be cleared in + * 'ubi_add_to_av()'. */ - seb->scrub = 1; + aeb->scrub = 1; else if (err) goto out_free; } @@ -402,10 +441,11 @@ static struct ubi_vtbl_record *process_lvol(struct ubi_device *ubi, if (!leb_corrupted[0]) { /* LEB 0 is OK */ if (leb[1]) - leb_corrupted[1] = memcmp(leb[0], leb[1], ubi->vtbl_size); + leb_corrupted[1] = memcmp(leb[0], leb[1], + ubi->vtbl_size); if (leb_corrupted[1]) { ubi_warn("volume table copy #2 is corrupted"); - err = create_vtbl(ubi, si, 1, leb[0]); + err = create_vtbl(ubi, ai, 1, leb[0]); if (err) goto out_free; ubi_msg("volume table was restored"); @@ -428,7 +468,7 @@ static struct ubi_vtbl_record *process_lvol(struct ubi_device *ubi, } ubi_warn("volume table copy #1 is corrupted"); - err = create_vtbl(ubi, si, 0, leb[1]); + err = create_vtbl(ubi, ai, 0, leb[1]); if (err) goto out_free; ubi_msg("volume table was restored"); @@ -446,21 +486,20 @@ out_free: /** * create_empty_lvol - create empty layout volume. * @ubi: UBI device description object - * @si: scanning information + * @ai: attaching information * * This function returns volume table contents in case of success and a * negative error code in case of failure. */ static struct ubi_vtbl_record *create_empty_lvol(struct ubi_device *ubi, - struct ubi_scan_info *si) + struct ubi_attach_info *ai) { int i; struct ubi_vtbl_record *vtbl; - vtbl = vmalloc(ubi->vtbl_size); + vtbl = vzalloc(ubi->vtbl_size); if (!vtbl) return ERR_PTR(-ENOMEM); - memset(vtbl, 0, ubi->vtbl_size); for (i = 0; i < ubi->vtbl_slots; i++) memcpy(&vtbl[i], &empty_vtbl_record, UBI_VTBL_RECORD_SIZE); @@ -468,7 +507,7 @@ static struct ubi_vtbl_record *create_empty_lvol(struct ubi_device *ubi, for (i = 0; i < UBI_LAYOUT_VOLUME_EBS; i++) { int err; - err = create_vtbl(ubi, si, i, vtbl); + err = create_vtbl(ubi, ai, i, vtbl); if (err) { vfree(vtbl); return ERR_PTR(err); @@ -481,18 +520,19 @@ static struct ubi_vtbl_record *create_empty_lvol(struct ubi_device *ubi, /** * init_volumes - initialize volume information for existing volumes. * @ubi: UBI device description object - * @si: scanning information + * @ai: scanning information * @vtbl: volume table * * This function allocates volume description objects for existing volumes. * Returns zero in case of success and a negative error code in case of * failure. */ -static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si, +static int init_volumes(struct ubi_device *ubi, + const struct ubi_attach_info *ai, const struct ubi_vtbl_record *vtbl) { int i, reserved_pebs = 0; - struct ubi_scan_volume *sv; + struct ubi_ainf_volume *av; struct ubi_volume *vol; for (i = 0; i < ubi->vtbl_slots; i++) { @@ -520,8 +560,8 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si, if (vtbl[i].flags & UBI_VTBL_AUTORESIZE_FLG) { /* Auto re-size flag may be set only for one volume */ if (ubi->autoresize_vol_id != -1) { - ubi_err("more then one auto-resize volume (%d " - "and %d)", ubi->autoresize_vol_id, i); + ubi_err("more than one auto-resize volume (%d and %d)", + ubi->autoresize_vol_id, i); kfree(vol); return -EINVAL; } @@ -548,8 +588,8 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si, } /* Static volumes only */ - sv = ubi_scan_find_sv(si, i); - if (!sv) { + av = ubi_find_av(ai, i); + if (!av) { /* * No eraseblocks belonging to this volume found. We * don't actually know whether this static volume is @@ -561,22 +601,22 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si, continue; } - if (sv->leb_count != sv->used_ebs) { + if (av->leb_count != av->used_ebs) { /* * We found a static volume which misses several * eraseblocks. Treat it as corrupted. */ ubi_warn("static volume %d misses %d LEBs - corrupted", - sv->vol_id, sv->used_ebs - sv->leb_count); + av->vol_id, av->used_ebs - av->leb_count); vol->corrupted = 1; continue; } - vol->used_ebs = sv->used_ebs; + vol->used_ebs = av->used_ebs; vol->used_bytes = (long long)(vol->used_ebs - 1) * vol->usable_leb_size; - vol->used_bytes += sv->last_data_size; - vol->last_eb_bytes = sv->last_data_size; + vol->used_bytes += av->last_data_size; + vol->last_eb_bytes = av->last_data_size; } /* And add the layout volume */ @@ -585,7 +625,7 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si, return -ENOMEM; vol->reserved_pebs = UBI_LAYOUT_VOLUME_EBS; - vol->alignment = 1; + vol->alignment = UBI_LAYOUT_VOLUME_ALIGN; vol->vol_type = UBI_DYNAMIC_VOLUME; vol->name_len = sizeof(UBI_LAYOUT_VOLUME_NAME) - 1; memcpy(vol->name, UBI_LAYOUT_VOLUME_NAME, vol->name_len + 1); @@ -603,9 +643,13 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si, ubi->vol_count += 1; vol->ubi = ubi; - if (reserved_pebs > ubi->avail_pebs) + if (reserved_pebs > ubi->avail_pebs) { ubi_err("not enough PEBs, required %d, available %d", reserved_pebs, ubi->avail_pebs); + if (ubi->corr_peb_count) + ubi_err("%d PEBs are corrupted and not used", + ubi->corr_peb_count); + } ubi->rsvd_pebs += reserved_pebs; ubi->avail_pebs -= reserved_pebs; @@ -613,105 +657,104 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si, } /** - * check_sv - check volume scanning information. + * check_av - check volume attaching information. * @vol: UBI volume description object - * @sv: volume scanning information + * @av: volume attaching information * - * This function returns zero if the volume scanning information is consistent + * This function returns zero if the volume attaching information is consistent * to the data read from the volume tabla, and %-EINVAL if not. */ -static int check_sv(const struct ubi_volume *vol, - const struct ubi_scan_volume *sv) +static int check_av(const struct ubi_volume *vol, + const struct ubi_ainf_volume *av) { int err; - if (sv->highest_lnum >= vol->reserved_pebs) { + if (av->highest_lnum >= vol->reserved_pebs) { err = 1; goto bad; } - if (sv->leb_count > vol->reserved_pebs) { + if (av->leb_count > vol->reserved_pebs) { err = 2; goto bad; } - if (sv->vol_type != vol->vol_type) { + if (av->vol_type != vol->vol_type) { err = 3; goto bad; } - if (sv->used_ebs > vol->reserved_pebs) { + if (av->used_ebs > vol->reserved_pebs) { err = 4; goto bad; } - if (sv->data_pad != vol->data_pad) { + if (av->data_pad != vol->data_pad) { err = 5; goto bad; } return 0; bad: - ubi_err("bad scanning information, error %d", err); - ubi_dbg_dump_sv(sv); - ubi_dbg_dump_vol_info(vol); + ubi_err("bad attaching information, error %d", err); + ubi_dump_av(av); + ubi_dump_vol_info(vol); return -EINVAL; } /** - * check_scanning_info - check that scanning information. + * check_attaching_info - check that attaching information. * @ubi: UBI device description object - * @si: scanning information + * @ai: attaching information * * Even though we protect on-flash data by CRC checksums, we still don't trust - * the media. This function ensures that scanning information is consistent to - * the information read from the volume table. Returns zero if the scanning + * the media. This function ensures that attaching information is consistent to + * the information read from the volume table. Returns zero if the attaching * information is OK and %-EINVAL if it is not. */ -static int check_scanning_info(const struct ubi_device *ubi, - struct ubi_scan_info *si) +static int check_attaching_info(const struct ubi_device *ubi, + struct ubi_attach_info *ai) { int err, i; - struct ubi_scan_volume *sv; + struct ubi_ainf_volume *av; struct ubi_volume *vol; - if (si->vols_found > UBI_INT_VOL_COUNT + ubi->vtbl_slots) { - ubi_err("scanning found %d volumes, maximum is %d + %d", - si->vols_found, UBI_INT_VOL_COUNT, ubi->vtbl_slots); + if (ai->vols_found > UBI_INT_VOL_COUNT + ubi->vtbl_slots) { + ubi_err("found %d volumes while attaching, maximum is %d + %d", + ai->vols_found, UBI_INT_VOL_COUNT, ubi->vtbl_slots); return -EINVAL; } - if (si->highest_vol_id >= ubi->vtbl_slots + UBI_INT_VOL_COUNT && - si->highest_vol_id < UBI_INTERNAL_VOL_START) { - ubi_err("too large volume ID %d found by scanning", - si->highest_vol_id); + if (ai->highest_vol_id >= ubi->vtbl_slots + UBI_INT_VOL_COUNT && + ai->highest_vol_id < UBI_INTERNAL_VOL_START) { + ubi_err("too large volume ID %d found", ai->highest_vol_id); return -EINVAL; } for (i = 0; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) { cond_resched(); - sv = ubi_scan_find_sv(si, i); + av = ubi_find_av(ai, i); vol = ubi->volumes[i]; if (!vol) { - if (sv) - ubi_scan_rm_volume(si, sv); + if (av) + ubi_remove_av(ai, av); continue; } if (vol->reserved_pebs == 0) { ubi_assert(i < ubi->vtbl_slots); - if (!sv) + if (!av) continue; /* - * During scanning we found a volume which does not + * During attaching we found a volume which does not * exist according to the information in the volume * table. This must have happened due to an unclean * reboot while the volume was being removed. Discard * these eraseblocks. */ - ubi_msg("finish volume %d removal", sv->vol_id); - ubi_scan_rm_volume(si, sv); - } else if (sv) { - err = check_sv(vol, sv); + ubi_msg("finish volume %d removal", av->vol_id); + ubi_remove_av(ai, av); + } else if (av) { + err = check_av(vol, av); if (err) return err; } @@ -721,19 +764,18 @@ static int check_scanning_info(const struct ubi_device *ubi, } /** - * ubi_read_volume_table - read volume table. - * information. + * ubi_read_volume_table - read the volume table. * @ubi: UBI device description object - * @si: scanning information + * @ai: attaching information * * This function reads volume table, checks it, recover from errors if needed, * or creates it if needed. Returns zero in case of success and a negative * error code in case of failure. */ -int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_scan_info *si) +int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_attach_info *ai) { int i, err; - struct ubi_scan_volume *sv; + struct ubi_ainf_volume *av; empty_vtbl_record.crc = cpu_to_be32(0xf116c36b); @@ -748,8 +790,8 @@ int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_scan_info *si) ubi->vtbl_size = ubi->vtbl_slots * UBI_VTBL_RECORD_SIZE; ubi->vtbl_size = ALIGN(ubi->vtbl_size, ubi->min_io_size); - sv = ubi_scan_find_sv(si, UBI_LAYOUT_VOLUME_ID); - if (!sv) { + av = ubi_find_av(ai, UBI_LAYOUT_VOLUME_ID); + if (!av) { /* * No logical eraseblocks belonging to the layout volume were * found. This could mean that the flash is just empty. In @@ -758,8 +800,8 @@ int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_scan_info *si) * But if flash is not empty this must be a corruption or the * MTD device just contains garbage. */ - if (si->is_empty) { - ubi->vtbl = create_empty_lvol(ubi, si); + if (ai->is_empty) { + ubi->vtbl = create_empty_lvol(ubi, ai); if (IS_ERR(ubi->vtbl)) return PTR_ERR(ubi->vtbl); } else { @@ -767,33 +809,33 @@ int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_scan_info *si) return -EINVAL; } } else { - if (sv->leb_count > UBI_LAYOUT_VOLUME_EBS) { + if (av->leb_count > UBI_LAYOUT_VOLUME_EBS) { /* This must not happen with proper UBI images */ - dbg_err("too many LEBs (%d) in layout volume", - sv->leb_count); + ubi_err("too many LEBs (%d) in layout volume", + av->leb_count); return -EINVAL; } - ubi->vtbl = process_lvol(ubi, si, sv); + ubi->vtbl = process_lvol(ubi, ai, av); if (IS_ERR(ubi->vtbl)) return PTR_ERR(ubi->vtbl); } - ubi->avail_pebs = ubi->good_peb_count; + ubi->avail_pebs = ubi->good_peb_count - ubi->corr_peb_count; /* * The layout volume is OK, initialize the corresponding in-RAM data * structures. */ - err = init_volumes(ubi, si, ubi->vtbl); + err = init_volumes(ubi, ai, ubi->vtbl); if (err) goto out_free; /* - * Get sure that the scanning information is consistent to the + * Make sure that the attaching information is consistent to the * information stored in the volume table. */ - err = check_scanning_info(ubi, si); + err = check_attaching_info(ubi, ai); if (err) goto out_free; @@ -801,26 +843,24 @@ int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_scan_info *si) out_free: vfree(ubi->vtbl); - for (i = 0; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) - if (ubi->volumes[i]) { - kfree(ubi->volumes[i]); - ubi->volumes[i] = NULL; - } + for (i = 0; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) { + kfree(ubi->volumes[i]); + ubi->volumes[i] = NULL; + } return err; } -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID - /** - * paranoid_vtbl_check - check volume table. + * self_vtbl_check - check volume table. * @ubi: UBI device description object */ -static void paranoid_vtbl_check(const struct ubi_device *ubi) +static void self_vtbl_check(const struct ubi_device *ubi) { + if (!ubi_dbg_chk_gen(ubi)) + return; + if (vtbl_check(ubi, ubi->vtbl)) { - ubi_err("paranoid check failed"); + ubi_err("self-check failed"); BUG(); } } - -#endif /* CONFIG_MTD_UBI_DEBUG_PARANOID */ diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 1eaa88b36f..6886f89df2 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -7,97 +7,116 @@ */ /* - * UBI wear-leveling unit. + * UBI wear-leveling sub-system. * - * This unit is responsible for wear-leveling. It works in terms of physical - * eraseblocks and erase counters and knows nothing about logical eraseblocks, - * volumes, etc. From this unit's perspective all physical eraseblocks are of - * two types - used and free. Used physical eraseblocks are those that were - * "get" by the 'ubi_wl_get_peb()' function, and free physical eraseblocks are - * those that were put by the 'ubi_wl_put_peb()' function. + * This sub-system is responsible for wear-leveling. It works in terms of + * physical eraseblocks and erase counters and knows nothing about logical + * eraseblocks, volumes, etc. From this sub-system's perspective all physical + * eraseblocks are of two types - used and free. Used physical eraseblocks are + * those that were "get" by the 'ubi_wl_get_peb()' function, and free physical + * eraseblocks are those that were put by the 'ubi_wl_put_peb()' function. * * Physical eraseblocks returned by 'ubi_wl_get_peb()' have only erase counter - * header. The rest of the physical eraseblock contains only 0xFF bytes. + * header. The rest of the physical eraseblock contains only %0xFF bytes. * - * When physical eraseblocks are returned to the WL unit by means of the + * When physical eraseblocks are returned to the WL sub-system by means of the * 'ubi_wl_put_peb()' function, they are scheduled for erasure. The erasure is * done asynchronously in context of the per-UBI device background thread, - * which is also managed by the WL unit. + * which is also managed by the WL sub-system. * * The wear-leveling is ensured by means of moving the contents of used * physical eraseblocks with low erase counter to free physical eraseblocks * with high erase counter. * - * The 'ubi_wl_get_peb()' function accepts data type hints which help to pick - * an "optimal" physical eraseblock. For example, when it is known that the - * physical eraseblock will be "put" soon because it contains short-term data, - * the WL unit may pick a free physical eraseblock with low erase counter, and - * so forth. + * If the WL sub-system fails to erase a physical eraseblock, it marks it as + * bad. * - * If the WL unit fails to erase a physical eraseblock, it marks it as bad. + * This sub-system is also responsible for scrubbing. If a bit-flip is detected + * in a physical eraseblock, it has to be moved. Technically this is the same + * as moving it for wear-leveling reasons. * - * This unit is also responsible for scrubbing. If a bit-flip is detected in a - * physical eraseblock, it has to be moved. Technically this is the same as - * moving it for wear-leveling reasons. + * As it was said, for the UBI sub-system all physical eraseblocks are either + * "free" or "used". Free eraseblock are kept in the @wl->free RB-tree, while + * used eraseblocks are kept in @wl->used, @wl->erroneous, or @wl->scrub + * RB-trees, as well as (temporarily) in the @wl->pq queue. * - * As it was said, for the UBI unit all physical eraseblocks are either "free" - * or "used". Free eraseblock are kept in the @wl->free RB-tree, while used - * eraseblocks are kept in a set of different RB-trees: @wl->used, - * @wl->prot.pnum, @wl->prot.aec, and @wl->scrub. + * When the WL sub-system returns a physical eraseblock, the physical + * eraseblock is protected from being moved for some "time". For this reason, + * the physical eraseblock is not directly moved from the @wl->free tree to the + * @wl->used tree. There is a protection queue in between where this + * physical eraseblock is temporarily stored (@wl->pq). + * + * All this protection stuff is needed because: + * o we don't want to move physical eraseblocks just after we have given them + * to the user; instead, we first want to let users fill them up with data; + * + * o there is a chance that the user will put the physical eraseblock very + * soon, so it makes sense not to move it for some time, but wait. + * + * Physical eraseblocks stay protected only for limited time. But the "time" is + * measured in erase cycles in this case. This is implemented with help of the + * protection queue. Eraseblocks are put to the tail of this queue when they + * are returned by the 'ubi_wl_get_peb()', and eraseblocks are removed from the + * head of the queue on each erase operation (for any eraseblock). So the + * length of the queue defines how may (global) erase cycles PEBs are protected. + * + * To put it differently, each physical eraseblock has 2 main states: free and + * used. The former state corresponds to the @wl->free tree. The latter state + * is split up on several sub-states: + * o the WL movement is allowed (@wl->used tree); + * o the WL movement is disallowed (@wl->erroneous) because the PEB is + * erroneous - e.g., there was a read error; + * o the WL movement is temporarily prohibited (@wl->pq queue); + * o scrubbing is needed (@wl->scrub tree). + * + * Depending on the sub-state, wear-leveling entries of the used physical + * eraseblocks may be kept in one of those structures. * * Note, in this implementation, we keep a small in-RAM object for each physical * eraseblock. This is surely not a scalable solution. But it appears to be good * enough for moderately large flashes and it is simple. In future, one may - * re-work this unit and make it more scalable. + * re-work this sub-system and make it more scalable. * - * At the moment this unit does not utilize the sequence number, which was - * introduced relatively recently. But it would be wise to do this because the - * sequence number of a logical eraseblock characterizes how old is it. For + * At the moment this sub-system does not utilize the sequence number, which + * was introduced relatively recently. But it would be wise to do this because + * the sequence number of a logical eraseblock characterizes how old is it. For * example, when we move a PEB with low erase counter, and we need to pick the * target PEB, we pick a PEB with the highest EC if our PEB is "old" and we * pick target PEB with an average EC if our PEB is not very "old". This is a - * room for future re-works of the WL unit. - * - * FIXME: looks too complex, should be simplified (later). + * room for future re-works of the WL sub-system. */ -#ifdef UBI_LINUX +#ifndef __UBOOT__ #include #include #include #include +#else +#include #endif -#include #include "ubi.h" /* Number of physical eraseblocks reserved for wear-leveling purposes */ #define WL_RESERVED_PEBS 1 -/* - * How many erase cycles are short term, unknown, and long term physical - * eraseblocks protected. - */ -#define ST_PROTECTION 16 -#define U_PROTECTION 10 -#define LT_PROTECTION 4 - /* * Maximum difference between two erase counters. If this threshold is - * exceeded, the WL unit starts moving data from used physical eraseblocks with - * low erase counter to free physical eraseblocks with high erase counter. + * exceeded, the WL sub-system starts moving data from used physical + * eraseblocks with low erase counter to free physical eraseblocks with high + * erase counter. */ #define UBI_WL_THRESHOLD CONFIG_MTD_UBI_WL_THRESHOLD /* - * When a physical eraseblock is moved, the WL unit has to pick the target + * When a physical eraseblock is moved, the WL sub-system has to pick the target * physical eraseblock to move to. The simplest way would be just to pick the * one with the highest erase counter. But in certain workloads this could lead * to an unlimited wear of one or few physical eraseblock. Indeed, imagine a * situation when the picked physical eraseblock is constantly erased after the * data is written to it. So, we have a constant which limits the highest erase - * counter of the free physical eraseblock to pick. Namely, the WL unit does - * not pick eraseblocks with erase counter greater then the lowest erase + * counter of the free physical eraseblock to pick. Namely, the WL sub-system + * does not pick eraseblocks with erase counter greater than the lowest erase * counter plus %WL_FREE_MAX_DIFF. */ #define WL_FREE_MAX_DIFF (2*UBI_WL_THRESHOLD) @@ -108,89 +127,48 @@ */ #define WL_MAX_FAILURES 32 +static int self_check_ec(struct ubi_device *ubi, int pnum, int ec); +static int self_check_in_wl_tree(const struct ubi_device *ubi, + struct ubi_wl_entry *e, struct rb_root *root); +static int self_check_in_pq(const struct ubi_device *ubi, + struct ubi_wl_entry *e); + +#ifdef CONFIG_MTD_UBI_FASTMAP +#ifndef __UBOOT__ /** - * struct ubi_wl_prot_entry - PEB protection entry. - * @rb_pnum: link in the @wl->prot.pnum RB-tree - * @rb_aec: link in the @wl->prot.aec RB-tree - * @abs_ec: the absolute erase counter value when the protection ends - * @e: the wear-leveling entry of the physical eraseblock under protection - * - * When the WL unit returns a physical eraseblock, the physical eraseblock is - * protected from being moved for some "time". For this reason, the physical - * eraseblock is not directly moved from the @wl->free tree to the @wl->used - * tree. There is one more tree in between where this physical eraseblock is - * temporarily stored (@wl->prot). - * - * All this protection stuff is needed because: - * o we don't want to move physical eraseblocks just after we have given them - * to the user; instead, we first want to let users fill them up with data; - * - * o there is a chance that the user will put the physical eraseblock very - * soon, so it makes sense not to move it for some time, but wait; this is - * especially important in case of "short term" physical eraseblocks. - * - * Physical eraseblocks stay protected only for limited time. But the "time" is - * measured in erase cycles in this case. This is implemented with help of the - * absolute erase counter (@wl->abs_ec). When it reaches certain value, the - * physical eraseblocks are moved from the protection trees (@wl->prot.*) to - * the @wl->used tree. - * - * Protected physical eraseblocks are searched by physical eraseblock number - * (when they are put) and by the absolute erase counter (to check if it is - * time to move them to the @wl->used tree). So there are actually 2 RB-trees - * storing the protected physical eraseblocks: @wl->prot.pnum and - * @wl->prot.aec. They are referred to as the "protection" trees. The - * first one is indexed by the physical eraseblock number. The second one is - * indexed by the absolute erase counter. Both trees store - * &struct ubi_wl_prot_entry objects. - * - * Each physical eraseblock has 2 main states: free and used. The former state - * corresponds to the @wl->free tree. The latter state is split up on several - * sub-states: - * o the WL movement is allowed (@wl->used tree); - * o the WL movement is temporarily prohibited (@wl->prot.pnum and - * @wl->prot.aec trees); - * o scrubbing is needed (@wl->scrub tree). - * - * Depending on the sub-state, wear-leveling entries of the used physical - * eraseblocks may be kept in one of those trees. + * update_fastmap_work_fn - calls ubi_update_fastmap from a work queue + * @wrk: the work description object */ -struct ubi_wl_prot_entry { - struct rb_node rb_pnum; - struct rb_node rb_aec; - unsigned long long abs_ec; - struct ubi_wl_entry *e; -}; +static void update_fastmap_work_fn(struct work_struct *wrk) +{ + struct ubi_device *ubi = container_of(wrk, struct ubi_device, fm_work); + ubi_update_fastmap(ubi); +} +#endif /** - * struct ubi_work - UBI work description data structure. - * @list: a link in the list of pending works - * @func: worker function - * @priv: private data of the worker function - * - * @e: physical eraseblock to erase - * @torture: if the physical eraseblock has to be tortured - * - * The @func pointer points to the worker function. If the @cancel argument is - * not zero, the worker has to free the resources and exit immediately. The - * worker has to return zero in case of success and a negative error code in - * case of failure. + * ubi_ubi_is_fm_block - returns 1 if a PEB is currently used in a fastmap. + * @ubi: UBI device description object + * @pnum: the to be checked PEB */ -struct ubi_work { - struct list_head list; - int (*func)(struct ubi_device *ubi, struct ubi_work *wrk, int cancel); - /* The below fields are only relevant to erasure works */ - struct ubi_wl_entry *e; - int torture; -}; +static int ubi_is_fm_block(struct ubi_device *ubi, int pnum) +{ + int i; + + if (!ubi->fm) + return 0; + + for (i = 0; i < ubi->fm->used_blocks; i++) + if (ubi->fm->e[i]->pnum == pnum) + return 1; -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID -static int paranoid_check_ec(struct ubi_device *ubi, int pnum, int ec); -static int paranoid_check_in_wl_tree(struct ubi_wl_entry *e, - struct rb_root *root); + return 0; +} #else -#define paranoid_check_ec(ubi, pnum, ec) 0 -#define paranoid_check_in_wl_tree(e, root) +static int ubi_is_fm_block(struct ubi_device *ubi, int pnum) +{ + return 0; +} #endif /** @@ -210,7 +188,7 @@ static void wl_tree_add(struct ubi_wl_entry *e, struct rb_root *root) struct ubi_wl_entry *e1; parent = *p; - e1 = rb_entry(parent, struct ubi_wl_entry, rb); + e1 = rb_entry(parent, struct ubi_wl_entry, u.rb); if (e->ec < e1->ec) p = &(*p)->rb_left; @@ -225,8 +203,8 @@ static void wl_tree_add(struct ubi_wl_entry *e, struct rb_root *root) } } - rb_link_node(&e->rb, parent, p); - rb_insert_color(&e->rb, root); + rb_link_node(&e->u.rb, parent, p); + rb_insert_color(&e->u.rb, root); } /** @@ -289,18 +267,16 @@ static int produce_free_peb(struct ubi_device *ubi) { int err; - spin_lock(&ubi->wl_lock); while (!ubi->free.rb_node) { spin_unlock(&ubi->wl_lock); dbg_wl("do one work synchronously"); err = do_work(ubi); - if (err) - return err; spin_lock(&ubi->wl_lock); + if (err) + return err; } - spin_unlock(&ubi->wl_lock); return 0; } @@ -321,7 +297,7 @@ static int in_wl_tree(struct ubi_wl_entry *e, struct rb_root *root) while (p) { struct ubi_wl_entry *e1; - e1 = rb_entry(p, struct ubi_wl_entry, rb); + e1 = rb_entry(p, struct ubi_wl_entry, u.rb); if (e->pnum == e1->pnum) { ubi_assert(e == e1); @@ -345,223 +321,406 @@ static int in_wl_tree(struct ubi_wl_entry *e, struct rb_root *root) } /** - * prot_tree_add - add physical eraseblock to protection trees. + * prot_queue_add - add physical eraseblock to the protection queue. * @ubi: UBI device description object * @e: the physical eraseblock to add - * @pe: protection entry object to use - * @abs_ec: absolute erase counter value when this physical eraseblock has - * to be removed from the protection trees. * - * @wl->lock has to be locked. + * This function adds @e to the tail of the protection queue @ubi->pq, where + * @e will stay for %UBI_PROT_QUEUE_LEN erase operations and will be + * temporarily protected from the wear-leveling worker. Note, @wl->lock has to + * be locked. */ -static void prot_tree_add(struct ubi_device *ubi, struct ubi_wl_entry *e, - struct ubi_wl_prot_entry *pe, int abs_ec) +static void prot_queue_add(struct ubi_device *ubi, struct ubi_wl_entry *e) { - struct rb_node **p, *parent = NULL; - struct ubi_wl_prot_entry *pe1; + int pq_tail = ubi->pq_head - 1; - pe->e = e; - pe->abs_ec = ubi->abs_ec + abs_ec; - - p = &ubi->prot.pnum.rb_node; - while (*p) { - parent = *p; - pe1 = rb_entry(parent, struct ubi_wl_prot_entry, rb_pnum); - - if (e->pnum < pe1->e->pnum) - p = &(*p)->rb_left; - else - p = &(*p)->rb_right; - } - rb_link_node(&pe->rb_pnum, parent, p); - rb_insert_color(&pe->rb_pnum, &ubi->prot.pnum); - - p = &ubi->prot.aec.rb_node; - parent = NULL; - while (*p) { - parent = *p; - pe1 = rb_entry(parent, struct ubi_wl_prot_entry, rb_aec); - - if (pe->abs_ec < pe1->abs_ec) - p = &(*p)->rb_left; - else - p = &(*p)->rb_right; - } - rb_link_node(&pe->rb_aec, parent, p); - rb_insert_color(&pe->rb_aec, &ubi->prot.aec); + if (pq_tail < 0) + pq_tail = UBI_PROT_QUEUE_LEN - 1; + ubi_assert(pq_tail >= 0 && pq_tail < UBI_PROT_QUEUE_LEN); + list_add_tail(&e->u.list, &ubi->pq[pq_tail]); + dbg_wl("added PEB %d EC %d to the protection queue", e->pnum, e->ec); } /** * find_wl_entry - find wear-leveling entry closest to certain erase counter. + * @ubi: UBI device description object * @root: the RB-tree where to look for - * @max: highest possible erase counter + * @diff: maximum possible difference from the smallest erase counter * * This function looks for a wear leveling entry with erase counter closest to - * @max and less then @max. + * min + @diff, where min is the smallest erase counter. */ -static struct ubi_wl_entry *find_wl_entry(struct rb_root *root, int max) +static struct ubi_wl_entry *find_wl_entry(struct ubi_device *ubi, + struct rb_root *root, int diff) { struct rb_node *p; - struct ubi_wl_entry *e; + struct ubi_wl_entry *e, *prev_e = NULL; + int max; - e = rb_entry(rb_first(root), struct ubi_wl_entry, rb); - max += e->ec; + e = rb_entry(rb_first(root), struct ubi_wl_entry, u.rb); + max = e->ec + diff; p = root->rb_node; while (p) { struct ubi_wl_entry *e1; - e1 = rb_entry(p, struct ubi_wl_entry, rb); + e1 = rb_entry(p, struct ubi_wl_entry, u.rb); if (e1->ec >= max) p = p->rb_left; else { p = p->rb_right; + prev_e = e; e = e1; } } + /* If no fastmap has been written and this WL entry can be used + * as anchor PEB, hold it back and return the second best WL entry + * such that fastmap can use the anchor PEB later. */ + if (prev_e && !ubi->fm_disabled && + !ubi->fm && e->pnum < UBI_FM_MAX_START) + return prev_e; + return e; } /** - * ubi_wl_get_peb - get a physical eraseblock. + * find_mean_wl_entry - find wear-leveling entry with medium erase counter. * @ubi: UBI device description object - * @dtype: type of data which will be stored in this physical eraseblock + * @root: the RB-tree where to look for * - * This function returns a physical eraseblock in case of success and a - * negative error code in case of failure. Might sleep. + * This function looks for a wear leveling entry with medium erase counter, + * but not greater or equivalent than the lowest erase counter plus + * %WL_FREE_MAX_DIFF/2. */ -int ubi_wl_get_peb(struct ubi_device *ubi, int dtype) +static struct ubi_wl_entry *find_mean_wl_entry(struct ubi_device *ubi, + struct rb_root *root) { - int err, protect, medium_ec; struct ubi_wl_entry *e, *first, *last; - struct ubi_wl_prot_entry *pe; - ubi_assert(dtype == UBI_LONGTERM || dtype == UBI_SHORTTERM || - dtype == UBI_UNKNOWN); + first = rb_entry(rb_first(root), struct ubi_wl_entry, u.rb); + last = rb_entry(rb_last(root), struct ubi_wl_entry, u.rb); - pe = kmalloc(sizeof(struct ubi_wl_prot_entry), GFP_NOFS); - if (!pe) - return -ENOMEM; + if (last->ec - first->ec < WL_FREE_MAX_DIFF) { + e = rb_entry(root->rb_node, struct ubi_wl_entry, u.rb); + +#ifdef CONFIG_MTD_UBI_FASTMAP + /* If no fastmap has been written and this WL entry can be used + * as anchor PEB, hold it back and return the second best + * WL entry such that fastmap can use the anchor PEB later. */ + if (e && !ubi->fm_disabled && !ubi->fm && + e->pnum < UBI_FM_MAX_START) + e = rb_entry(rb_next(root->rb_node), + struct ubi_wl_entry, u.rb); +#endif + } else + e = find_wl_entry(ubi, root, WL_FREE_MAX_DIFF/2); + + return e; +} + +#ifdef CONFIG_MTD_UBI_FASTMAP +/** + * find_anchor_wl_entry - find wear-leveling entry to used as anchor PEB. + * @root: the RB-tree where to look for + */ +static struct ubi_wl_entry *find_anchor_wl_entry(struct rb_root *root) +{ + struct rb_node *p; + struct ubi_wl_entry *e, *victim = NULL; + int max_ec = UBI_MAX_ERASECOUNTER; + + ubi_rb_for_each_entry(p, e, root, u.rb) { + if (e->pnum < UBI_FM_MAX_START && e->ec < max_ec) { + victim = e; + max_ec = e->ec; + } + } + + return victim; +} + +static int anchor_pebs_avalible(struct rb_root *root) +{ + struct rb_node *p; + struct ubi_wl_entry *e; + + ubi_rb_for_each_entry(p, e, root, u.rb) + if (e->pnum < UBI_FM_MAX_START) + return 1; + + return 0; +} + +/** + * ubi_wl_get_fm_peb - find a physical erase block with a given maximal number. + * @ubi: UBI device description object + * @anchor: This PEB will be used as anchor PEB by fastmap + * + * The function returns a physical erase block with a given maximal number + * and removes it from the wl subsystem. + * Must be called with wl_lock held! + */ +struct ubi_wl_entry *ubi_wl_get_fm_peb(struct ubi_device *ubi, int anchor) +{ + struct ubi_wl_entry *e = NULL; + + if (!ubi->free.rb_node || (ubi->free_count - ubi->beb_rsvd_pebs < 1)) + goto out; + + if (anchor) + e = find_anchor_wl_entry(&ubi->free); + else + e = find_mean_wl_entry(ubi, &ubi->free); + + if (!e) + goto out; + + self_check_in_wl_tree(ubi, e, &ubi->free); + + /* remove it from the free list, + * the wl subsystem does no longer know this erase block */ + rb_erase(&e->u.rb, &ubi->free); + ubi->free_count--; +out: + return e; +} +#endif + +/** + * __wl_get_peb - get a physical eraseblock. + * @ubi: UBI device description object + * + * This function returns a physical eraseblock in case of success and a + * negative error code in case of failure. + */ +static int __wl_get_peb(struct ubi_device *ubi) +{ + int err; + struct ubi_wl_entry *e; retry: - spin_lock(&ubi->wl_lock); if (!ubi->free.rb_node) { if (ubi->works_count == 0) { - ubi_assert(list_empty(&ubi->works)); ubi_err("no free eraseblocks"); - spin_unlock(&ubi->wl_lock); - kfree(pe); + ubi_assert(list_empty(&ubi->works)); return -ENOSPC; } - spin_unlock(&ubi->wl_lock); err = produce_free_peb(ubi); - if (err < 0) { - kfree(pe); + if (err < 0) return err; - } goto retry; } - switch (dtype) { - case UBI_LONGTERM: - /* - * For long term data we pick a physical eraseblock - * with high erase counter. But the highest erase - * counter we can pick is bounded by the the lowest - * erase counter plus %WL_FREE_MAX_DIFF. - */ - e = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF); - protect = LT_PROTECTION; - break; - case UBI_UNKNOWN: - /* - * For unknown data we pick a physical eraseblock with - * medium erase counter. But we by no means can pick a - * physical eraseblock with erase counter greater or - * equivalent than the lowest erase counter plus - * %WL_FREE_MAX_DIFF. - */ - first = rb_entry(rb_first(&ubi->free), - struct ubi_wl_entry, rb); - last = rb_entry(rb_last(&ubi->free), - struct ubi_wl_entry, rb); - - if (last->ec - first->ec < WL_FREE_MAX_DIFF) - e = rb_entry(ubi->free.rb_node, - struct ubi_wl_entry, rb); - else { - medium_ec = (first->ec + WL_FREE_MAX_DIFF)/2; - e = find_wl_entry(&ubi->free, medium_ec); - } - protect = U_PROTECTION; - break; - case UBI_SHORTTERM: - /* - * For short term data we pick a physical eraseblock - * with the lowest erase counter as we expect it will - * be erased soon. - */ - e = rb_entry(rb_first(&ubi->free), - struct ubi_wl_entry, rb); - protect = ST_PROTECTION; - break; - default: - protect = 0; - e = NULL; - BUG(); + e = find_mean_wl_entry(ubi, &ubi->free); + if (!e) { + ubi_err("no free eraseblocks"); + return -ENOSPC; } + self_check_in_wl_tree(ubi, e, &ubi->free); + /* - * Move the physical eraseblock to the protection trees where it will + * Move the physical eraseblock to the protection queue where it will * be protected from being moved for some time. */ - paranoid_check_in_wl_tree(e, &ubi->free); - rb_erase(&e->rb, &ubi->free); - prot_tree_add(ubi, e, pe, protect); + rb_erase(&e->u.rb, &ubi->free); + ubi->free_count--; + dbg_wl("PEB %d EC %d", e->pnum, e->ec); +#ifndef CONFIG_MTD_UBI_FASTMAP + /* We have to enqueue e only if fastmap is disabled, + * is fastmap enabled prot_queue_add() will be called by + * ubi_wl_get_peb() after removing e from the pool. */ + prot_queue_add(ubi, e); +#endif + return e->pnum; +} - dbg_wl("PEB %d EC %d, protection %d", e->pnum, e->ec, protect); - spin_unlock(&ubi->wl_lock); +#ifdef CONFIG_MTD_UBI_FASTMAP +/** + * return_unused_pool_pebs - returns unused PEB to the free tree. + * @ubi: UBI device description object + * @pool: fastmap pool description object + */ +static void return_unused_pool_pebs(struct ubi_device *ubi, + struct ubi_fm_pool *pool) +{ + int i; + struct ubi_wl_entry *e; - return e->pnum; + for (i = pool->used; i < pool->size; i++) { + e = ubi->lookuptbl[pool->pebs[i]]; + wl_tree_add(e, &ubi->free); + ubi->free_count++; + } } /** - * prot_tree_del - remove a physical eraseblock from the protection trees + * refill_wl_pool - refills all the fastmap pool used by the + * WL sub-system. * @ubi: UBI device description object - * @pnum: the physical eraseblock to remove + */ +static void refill_wl_pool(struct ubi_device *ubi) +{ + struct ubi_wl_entry *e; + struct ubi_fm_pool *pool = &ubi->fm_wl_pool; + + return_unused_pool_pebs(ubi, pool); + + for (pool->size = 0; pool->size < pool->max_size; pool->size++) { + if (!ubi->free.rb_node || + (ubi->free_count - ubi->beb_rsvd_pebs < 5)) + break; + + e = find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF); + self_check_in_wl_tree(ubi, e, &ubi->free); + rb_erase(&e->u.rb, &ubi->free); + ubi->free_count--; + + pool->pebs[pool->size] = e->pnum; + } + pool->used = 0; +} + +/** + * refill_wl_user_pool - refills all the fastmap pool used by ubi_wl_get_peb. + * @ubi: UBI device description object + */ +static void refill_wl_user_pool(struct ubi_device *ubi) +{ + struct ubi_fm_pool *pool = &ubi->fm_pool; + + return_unused_pool_pebs(ubi, pool); + + for (pool->size = 0; pool->size < pool->max_size; pool->size++) { + pool->pebs[pool->size] = __wl_get_peb(ubi); + if (pool->pebs[pool->size] < 0) + break; + } + pool->used = 0; +} + +/** + * ubi_refill_pools - refills all fastmap PEB pools. + * @ubi: UBI device description object + */ +void ubi_refill_pools(struct ubi_device *ubi) +{ + spin_lock(&ubi->wl_lock); + refill_wl_pool(ubi); + refill_wl_user_pool(ubi); + spin_unlock(&ubi->wl_lock); +} + +/* ubi_wl_get_peb - works exaclty like __wl_get_peb but keeps track of + * the fastmap pool. + */ +int ubi_wl_get_peb(struct ubi_device *ubi) +{ + int ret; + struct ubi_fm_pool *pool = &ubi->fm_pool; + struct ubi_fm_pool *wl_pool = &ubi->fm_wl_pool; + + if (!pool->size || !wl_pool->size || pool->used == pool->size || + wl_pool->used == wl_pool->size) + ubi_update_fastmap(ubi); + + /* we got not a single free PEB */ + if (!pool->size) + ret = -ENOSPC; + else { + spin_lock(&ubi->wl_lock); + ret = pool->pebs[pool->used++]; + prot_queue_add(ubi, ubi->lookuptbl[ret]); + spin_unlock(&ubi->wl_lock); + } + + return ret; +} + +/* get_peb_for_wl - returns a PEB to be used internally by the WL sub-system. * - * This function returns PEB @pnum from the protection trees and returns zero - * in case of success and %-ENODEV if the PEB was not found in the protection - * trees. + * @ubi: UBI device description object */ -static int prot_tree_del(struct ubi_device *ubi, int pnum) +static struct ubi_wl_entry *get_peb_for_wl(struct ubi_device *ubi) { - struct rb_node *p; - struct ubi_wl_prot_entry *pe = NULL; + struct ubi_fm_pool *pool = &ubi->fm_wl_pool; + int pnum; + + if (pool->used == pool->size || !pool->size) { + /* We cannot update the fastmap here because this + * function is called in atomic context. + * Let's fail here and refill/update it as soon as possible. */ +#ifndef __UBOOT__ + schedule_work(&ubi->fm_work); +#else + /* In U-Boot we must call this directly */ + ubi_update_fastmap(ubi); +#endif + return NULL; + } else { + pnum = pool->pebs[pool->used++]; + return ubi->lookuptbl[pnum]; + } +} +#else +static struct ubi_wl_entry *get_peb_for_wl(struct ubi_device *ubi) +{ + struct ubi_wl_entry *e; - p = ubi->prot.pnum.rb_node; - while (p) { + e = find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF); + self_check_in_wl_tree(ubi, e, &ubi->free); + ubi->free_count--; + ubi_assert(ubi->free_count >= 0); + rb_erase(&e->u.rb, &ubi->free); - pe = rb_entry(p, struct ubi_wl_prot_entry, rb_pnum); + return e; +} - if (pnum == pe->e->pnum) - goto found; +int ubi_wl_get_peb(struct ubi_device *ubi) +{ + int peb, err; - if (pnum < pe->e->pnum) - p = p->rb_left; - else - p = p->rb_right; + spin_lock(&ubi->wl_lock); + peb = __wl_get_peb(ubi); + spin_unlock(&ubi->wl_lock); + + if (peb < 0) + return peb; + + err = ubi_self_check_all_ff(ubi, peb, ubi->vid_hdr_aloffset, + ubi->peb_size - ubi->vid_hdr_aloffset); + if (err) { + ubi_err("new PEB %d does not contain all 0xFF bytes", peb); + return err; } - return -ENODEV; + return peb; +} +#endif + +/** + * prot_queue_del - remove a physical eraseblock from the protection queue. + * @ubi: UBI device description object + * @pnum: the physical eraseblock to remove + * + * This function deletes PEB @pnum from the protection queue and returns zero + * in case of success and %-ENODEV if the PEB was not found. + */ +static int prot_queue_del(struct ubi_device *ubi, int pnum) +{ + struct ubi_wl_entry *e; -found: - ubi_assert(pe->e->pnum == pnum); - rb_erase(&pe->rb_aec, &ubi->prot.aec); - rb_erase(&pe->rb_pnum, &ubi->prot.pnum); - kfree(pe); + e = ubi->lookuptbl[pnum]; + if (!e) + return -ENODEV; + + if (self_check_in_pq(ubi, e)) + return -ENODEV; + + list_del(&e->u.list); + dbg_wl("deleted PEB %d from the protection queue", e->pnum); return 0; } @@ -574,7 +733,8 @@ found: * This function returns zero in case of success and a negative error code in * case of failure. */ -static int sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, int torture) +static int sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, + int torture) { int err; struct ubi_ec_hdr *ec_hdr; @@ -582,8 +742,8 @@ static int sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, int tortur dbg_wl("erase PEB %d, old EC %llu", e->pnum, ec); - err = paranoid_check_ec(ubi, e->pnum, e->ec); - if (err > 0) + err = self_check_ec(ubi, e->pnum, e->ec); + if (err) return -EINVAL; ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_NOFS); @@ -626,105 +786,213 @@ out_free: } /** - * check_protection_over - check if it is time to stop protecting some - * physical eraseblocks. + * serve_prot_queue - check if it is time to stop protecting PEBs. * @ubi: UBI device description object * - * This function is called after each erase operation, when the absolute erase - * counter is incremented, to check if some physical eraseblock have not to be - * protected any longer. These physical eraseblocks are moved from the - * protection trees to the used tree. + * This function is called after each erase operation and removes PEBs from the + * tail of the protection queue. These PEBs have been protected for long enough + * and should be moved to the used tree. */ -static void check_protection_over(struct ubi_device *ubi) +static void serve_prot_queue(struct ubi_device *ubi) { - struct ubi_wl_prot_entry *pe; + struct ubi_wl_entry *e, *tmp; + int count; /* * There may be several protected physical eraseblock to remove, * process them all. */ - while (1) { - spin_lock(&ubi->wl_lock); - if (!ubi->prot.aec.rb_node) { - spin_unlock(&ubi->wl_lock); - break; - } - - pe = rb_entry(rb_first(&ubi->prot.aec), - struct ubi_wl_prot_entry, rb_aec); +repeat: + count = 0; + spin_lock(&ubi->wl_lock); + list_for_each_entry_safe(e, tmp, &ubi->pq[ubi->pq_head], u.list) { + dbg_wl("PEB %d EC %d protection over, move to used tree", + e->pnum, e->ec); - if (pe->abs_ec > ubi->abs_ec) { + list_del(&e->u.list); + wl_tree_add(e, &ubi->used); + if (count++ > 32) { + /* + * Let's be nice and avoid holding the spinlock for + * too long. + */ spin_unlock(&ubi->wl_lock); - break; + cond_resched(); + goto repeat; } - - dbg_wl("PEB %d protection over, abs_ec %llu, PEB abs_ec %llu", - pe->e->pnum, ubi->abs_ec, pe->abs_ec); - rb_erase(&pe->rb_aec, &ubi->prot.aec); - rb_erase(&pe->rb_pnum, &ubi->prot.pnum); - wl_tree_add(pe->e, &ubi->used); - spin_unlock(&ubi->wl_lock); - - kfree(pe); - cond_resched(); } + + ubi->pq_head += 1; + if (ubi->pq_head == UBI_PROT_QUEUE_LEN) + ubi->pq_head = 0; + ubi_assert(ubi->pq_head >= 0 && ubi->pq_head < UBI_PROT_QUEUE_LEN); + spin_unlock(&ubi->wl_lock); } /** - * schedule_ubi_work - schedule a work. + * __schedule_ubi_work - schedule a work. * @ubi: UBI device description object * @wrk: the work to schedule * - * This function enqueues a work defined by @wrk to the tail of the pending - * works list. + * This function adds a work defined by @wrk to the tail of the pending works + * list. Can only be used of ubi->work_sem is already held in read mode! */ -static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk) +static void __schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk) { spin_lock(&ubi->wl_lock); list_add_tail(&wrk->list, &ubi->works); ubi_assert(ubi->works_count >= 0); ubi->works_count += 1; - +#ifndef __UBOOT__ + if (ubi->thread_enabled && !ubi_dbg_is_bgt_disabled(ubi)) + wake_up_process(ubi->bgt_thread); +#else /* * U-Boot special: We have no bgt_thread in U-Boot! * So just call do_work() here directly. */ do_work(ubi); - +#endif spin_unlock(&ubi->wl_lock); } -static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, - int cancel); - /** - * schedule_erase - schedule an erase work. + * schedule_ubi_work - schedule a work. + * @ubi: UBI device description object + * @wrk: the work to schedule + * + * This function adds a work defined by @wrk to the tail of the pending works + * list. + */ +static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk) +{ + down_read(&ubi->work_sem); + __schedule_ubi_work(ubi, wrk); + up_read(&ubi->work_sem); +} + +static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, + int cancel); + +#ifdef CONFIG_MTD_UBI_FASTMAP +/** + * ubi_is_erase_work - checks whether a work is erase work. + * @wrk: The work object to be checked + */ +int ubi_is_erase_work(struct ubi_work *wrk) +{ + return wrk->func == erase_worker; +} +#endif + +/** + * schedule_erase - schedule an erase work. + * @ubi: UBI device description object + * @e: the WL entry of the physical eraseblock to erase + * @vol_id: the volume ID that last used this PEB + * @lnum: the last used logical eraseblock number for the PEB + * @torture: if the physical eraseblock has to be tortured + * + * This function returns zero in case of success and a %-ENOMEM in case of + * failure. + */ +static int schedule_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, + int vol_id, int lnum, int torture) +{ + struct ubi_work *wl_wrk; + + ubi_assert(e); + ubi_assert(!ubi_is_fm_block(ubi, e->pnum)); + + dbg_wl("schedule erasure of PEB %d, EC %d, torture %d", + e->pnum, e->ec, torture); + + wl_wrk = kmalloc(sizeof(struct ubi_work), GFP_NOFS); + if (!wl_wrk) + return -ENOMEM; + + wl_wrk->func = &erase_worker; + wl_wrk->e = e; + wl_wrk->vol_id = vol_id; + wl_wrk->lnum = lnum; + wl_wrk->torture = torture; + + schedule_ubi_work(ubi, wl_wrk); + return 0; +} + +/** + * do_sync_erase - run the erase worker synchronously. * @ubi: UBI device description object * @e: the WL entry of the physical eraseblock to erase + * @vol_id: the volume ID that last used this PEB + * @lnum: the last used logical eraseblock number for the PEB * @torture: if the physical eraseblock has to be tortured * - * This function returns zero in case of success and a %-ENOMEM in case of - * failure. */ -static int schedule_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, - int torture) +static int do_sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, + int vol_id, int lnum, int torture) { struct ubi_work *wl_wrk; - dbg_wl("schedule erasure of PEB %d, EC %d, torture %d", - e->pnum, e->ec, torture); + dbg_wl("sync erase of PEB %i", e->pnum); wl_wrk = kmalloc(sizeof(struct ubi_work), GFP_NOFS); if (!wl_wrk) return -ENOMEM; - wl_wrk->func = &erase_worker; wl_wrk->e = e; + wl_wrk->vol_id = vol_id; + wl_wrk->lnum = lnum; wl_wrk->torture = torture; - schedule_ubi_work(ubi, wl_wrk); - return 0; + return erase_worker(ubi, wl_wrk, 0); +} + +#ifdef CONFIG_MTD_UBI_FASTMAP +/** + * ubi_wl_put_fm_peb - returns a PEB used in a fastmap to the wear-leveling + * sub-system. + * see: ubi_wl_put_peb() + * + * @ubi: UBI device description object + * @fm_e: physical eraseblock to return + * @lnum: the last used logical eraseblock number for the PEB + * @torture: if this physical eraseblock has to be tortured + */ +int ubi_wl_put_fm_peb(struct ubi_device *ubi, struct ubi_wl_entry *fm_e, + int lnum, int torture) +{ + struct ubi_wl_entry *e; + int vol_id, pnum = fm_e->pnum; + + dbg_wl("PEB %d", pnum); + + ubi_assert(pnum >= 0); + ubi_assert(pnum < ubi->peb_count); + + spin_lock(&ubi->wl_lock); + e = ubi->lookuptbl[pnum]; + + /* This can happen if we recovered from a fastmap the very + * first time and writing now a new one. In this case the wl system + * has never seen any PEB used by the original fastmap. + */ + if (!e) { + e = fm_e; + ubi_assert(e->ec >= 0); + ubi->lookuptbl[pnum] = e; + } else { + e->ec = fm_e->ec; + kfree(fm_e); + } + + spin_unlock(&ubi->wl_lock); + + vol_id = lnum ? UBI_FM_DATA_VOLUME_ID : UBI_FM_SB_VOLUME_ID; + return schedule_erase(ubi, e, vol_id, lnum, torture); } +#endif /** * wear_leveling_worker - wear-leveling worker function. @@ -739,13 +1007,15 @@ static int schedule_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk, int cancel) { - int err, put = 0, scrubbing = 0, protect = 0; - struct ubi_wl_prot_entry *uninitialized_var(pe); + int err, scrubbing = 0, torture = 0, protect = 0, erroneous = 0; + int vol_id = -1, uninitialized_var(lnum); +#ifdef CONFIG_MTD_UBI_FASTMAP + int anchor = wrk->anchor; +#endif struct ubi_wl_entry *e1, *e2; struct ubi_vid_hdr *vid_hdr; kfree(wrk); - if (cancel) return 0; @@ -775,36 +1045,62 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk, goto out_cancel; } +#ifdef CONFIG_MTD_UBI_FASTMAP + /* Check whether we need to produce an anchor PEB */ + if (!anchor) + anchor = !anchor_pebs_avalible(&ubi->free); + + if (anchor) { + e1 = find_anchor_wl_entry(&ubi->used); + if (!e1) + goto out_cancel; + e2 = get_peb_for_wl(ubi); + if (!e2) + goto out_cancel; + + self_check_in_wl_tree(ubi, e1, &ubi->used); + rb_erase(&e1->u.rb, &ubi->used); + dbg_wl("anchor-move PEB %d to PEB %d", e1->pnum, e2->pnum); + } else if (!ubi->scrub.rb_node) { +#else if (!ubi->scrub.rb_node) { +#endif /* * Now pick the least worn-out used physical eraseblock and a * highly worn-out free physical eraseblock. If the erase * counters differ much enough, start wear-leveling. */ - e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, rb); - e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF); + e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, u.rb); + e2 = get_peb_for_wl(ubi); + if (!e2) + goto out_cancel; if (!(e2->ec - e1->ec >= UBI_WL_THRESHOLD)) { dbg_wl("no WL needed: min used EC %d, max free EC %d", e1->ec, e2->ec); + + /* Give the unused PEB back */ + wl_tree_add(e2, &ubi->free); + ubi->free_count++; goto out_cancel; } - paranoid_check_in_wl_tree(e1, &ubi->used); - rb_erase(&e1->rb, &ubi->used); + self_check_in_wl_tree(ubi, e1, &ubi->used); + rb_erase(&e1->u.rb, &ubi->used); dbg_wl("move PEB %d EC %d to PEB %d EC %d", e1->pnum, e1->ec, e2->pnum, e2->ec); } else { /* Perform scrubbing */ scrubbing = 1; - e1 = rb_entry(rb_first(&ubi->scrub), struct ubi_wl_entry, rb); - e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF); - paranoid_check_in_wl_tree(e1, &ubi->scrub); - rb_erase(&e1->rb, &ubi->scrub); + e1 = rb_entry(rb_first(&ubi->scrub), struct ubi_wl_entry, u.rb); + e2 = get_peb_for_wl(ubi); + if (!e2) + goto out_cancel; + + self_check_in_wl_tree(ubi, e1, &ubi->scrub); + rb_erase(&e1->u.rb, &ubi->scrub); dbg_wl("scrub PEB %d to PEB %d", e1->pnum, e2->pnum); } - paranoid_check_in_wl_tree(e2, &ubi->free); - rb_erase(&e2->rb, &ubi->free); ubi->move_from = e1; ubi->move_to = e2; spin_unlock(&ubi->wl_lock); @@ -822,81 +1118,127 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk, err = ubi_io_read_vid_hdr(ubi, e1->pnum, vid_hdr, 0); if (err && err != UBI_IO_BITFLIPS) { - if (err == UBI_IO_PEB_FREE) { + if (err == UBI_IO_FF) { /* * We are trying to move PEB without a VID header. UBI * always write VID headers shortly after the PEB was - * given, so we have a situation when it did not have - * chance to write it down because it was preempted. - * Just re-schedule the work, so that next time it will - * likely have the VID header in place. + * given, so we have a situation when it has not yet + * had a chance to write it, because it was preempted. + * So add this PEB to the protection queue so far, + * because presumably more data will be written there + * (including the missing VID header), and then we'll + * move it. */ dbg_wl("PEB %d has no VID header", e1->pnum); + protect = 1; + goto out_not_moved; + } else if (err == UBI_IO_FF_BITFLIPS) { + /* + * The same situation as %UBI_IO_FF, but bit-flips were + * detected. It is better to schedule this PEB for + * scrubbing. + */ + dbg_wl("PEB %d has no VID header but has bit-flips", + e1->pnum); + scrubbing = 1; goto out_not_moved; } ubi_err("error %d while reading VID header from PEB %d", err, e1->pnum); - if (err > 0) - err = -EIO; goto out_error; } + vol_id = be32_to_cpu(vid_hdr->vol_id); + lnum = be32_to_cpu(vid_hdr->lnum); + err = ubi_eba_copy_leb(ubi, e1->pnum, e2->pnum, vid_hdr); if (err) { - - if (err < 0) - goto out_error; - if (err == 1) + if (err == MOVE_CANCEL_RACE) { + /* + * The LEB has not been moved because the volume is + * being deleted or the PEB has been put meanwhile. We + * should prevent this PEB from being selected for + * wear-leveling movement again, so put it to the + * protection queue. + */ + protect = 1; + goto out_not_moved; + } + if (err == MOVE_RETRY) { + scrubbing = 1; + goto out_not_moved; + } + if (err == MOVE_TARGET_BITFLIPS || err == MOVE_TARGET_WR_ERR || + err == MOVE_TARGET_RD_ERR) { + /* + * Target PEB had bit-flips or write error - torture it. + */ + torture = 1; goto out_not_moved; + } - /* - * For some reason the LEB was not moved - it might be because - * the volume is being deleted. We should prevent this PEB from - * being selected for wear-levelling movement for some "time", - * so put it to the protection tree. - */ + if (err == MOVE_SOURCE_RD_ERR) { + /* + * An error happened while reading the source PEB. Do + * not switch to R/O mode in this case, and give the + * upper layers a possibility to recover from this, + * e.g. by unmapping corresponding LEB. Instead, just + * put this PEB to the @ubi->erroneous list to prevent + * UBI from trying to move it over and over again. + */ + if (ubi->erroneous_peb_count > ubi->max_erroneous) { + ubi_err("too many erroneous eraseblocks (%d)", + ubi->erroneous_peb_count); + goto out_error; + } + erroneous = 1; + goto out_not_moved; + } - dbg_wl("cancelled moving PEB %d", e1->pnum); - pe = kmalloc(sizeof(struct ubi_wl_prot_entry), GFP_NOFS); - if (!pe) { - err = -ENOMEM; + if (err < 0) goto out_error; - } - protect = 1; + ubi_assert(0); } + /* The PEB has been successfully moved */ + if (scrubbing) + ubi_msg("scrubbed PEB %d (LEB %d:%d), data moved to PEB %d", + e1->pnum, vol_id, lnum, e2->pnum); ubi_free_vid_hdr(ubi, vid_hdr); + spin_lock(&ubi->wl_lock); - if (protect) - prot_tree_add(ubi, e1, pe, protect); - if (!ubi->move_to_put) + if (!ubi->move_to_put) { wl_tree_add(e2, &ubi->used); - else - put = 1; + e2 = NULL; + } ubi->move_from = ubi->move_to = NULL; ubi->move_to_put = ubi->wl_scheduled = 0; spin_unlock(&ubi->wl_lock); - if (put) { + err = do_sync_erase(ubi, e1, vol_id, lnum, 0); + if (err) { + kmem_cache_free(ubi_wl_entry_slab, e1); + if (e2) + kmem_cache_free(ubi_wl_entry_slab, e2); + goto out_ro; + } + + if (e2) { /* * Well, the target PEB was put meanwhile, schedule it for * erasure. */ - dbg_wl("PEB %d was put meanwhile, erase", e2->pnum); - err = schedule_erase(ubi, e2, 0); - if (err) - goto out_error; - } - - if (!protect) { - err = schedule_erase(ubi, e1, 0); - if (err) - goto out_error; + dbg_wl("PEB %d (LEB %d:%d) was put meanwhile, erase", + e2->pnum, vol_id, lnum); + err = do_sync_erase(ubi, e2, vol_id, lnum, 0); + if (err) { + kmem_cache_free(ubi_wl_entry_slab, e2); + goto out_ro; + } } - dbg_wl("done"); mutex_unlock(&ubi->move_mutex); return 0; @@ -904,42 +1246,60 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk, /* * For some reasons the LEB was not moved, might be an error, might be * something else. @e1 was not changed, so return it back. @e2 might - * be changed, schedule it for erasure. + * have been changed, schedule it for erasure. */ out_not_moved: - ubi_free_vid_hdr(ubi, vid_hdr); + if (vol_id != -1) + dbg_wl("cancel moving PEB %d (LEB %d:%d) to PEB %d (%d)", + e1->pnum, vol_id, lnum, e2->pnum, err); + else + dbg_wl("cancel moving PEB %d to PEB %d (%d)", + e1->pnum, e2->pnum, err); spin_lock(&ubi->wl_lock); - if (scrubbing) + if (protect) + prot_queue_add(ubi, e1); + else if (erroneous) { + wl_tree_add(e1, &ubi->erroneous); + ubi->erroneous_peb_count += 1; + } else if (scrubbing) wl_tree_add(e1, &ubi->scrub); else wl_tree_add(e1, &ubi->used); + ubi_assert(!ubi->move_to_put); ubi->move_from = ubi->move_to = NULL; - ubi->move_to_put = ubi->wl_scheduled = 0; + ubi->wl_scheduled = 0; spin_unlock(&ubi->wl_lock); - err = schedule_erase(ubi, e2, 0); - if (err) - goto out_error; - + ubi_free_vid_hdr(ubi, vid_hdr); + err = do_sync_erase(ubi, e2, vol_id, lnum, torture); + if (err) { + kmem_cache_free(ubi_wl_entry_slab, e2); + goto out_ro; + } mutex_unlock(&ubi->move_mutex); return 0; out_error: - ubi_err("error %d while moving PEB %d to PEB %d", - err, e1->pnum, e2->pnum); - - ubi_free_vid_hdr(ubi, vid_hdr); + if (vol_id != -1) + ubi_err("error %d while moving PEB %d to PEB %d", + err, e1->pnum, e2->pnum); + else + ubi_err("error %d while moving PEB %d (LEB %d:%d) to PEB %d", + err, e1->pnum, vol_id, lnum, e2->pnum); spin_lock(&ubi->wl_lock); ubi->move_from = ubi->move_to = NULL; ubi->move_to_put = ubi->wl_scheduled = 0; spin_unlock(&ubi->wl_lock); + ubi_free_vid_hdr(ubi, vid_hdr); kmem_cache_free(ubi_wl_entry_slab, e1); kmem_cache_free(ubi_wl_entry_slab, e2); - ubi_ro_mode(ubi); +out_ro: + ubi_ro_mode(ubi); mutex_unlock(&ubi->move_mutex); - return err; + ubi_assert(err != 0); + return err < 0 ? err : -EIO; out_cancel: ubi->wl_scheduled = 0; @@ -952,12 +1312,13 @@ out_cancel: /** * ensure_wear_leveling - schedule wear-leveling if it is needed. * @ubi: UBI device description object + * @nested: set to non-zero if this function is called from UBI worker * * This function checks if it is time to start wear-leveling and schedules it * if yes. This function returns zero in case of success and a negative error * code in case of failure. */ -static int ensure_wear_leveling(struct ubi_device *ubi) +static int ensure_wear_leveling(struct ubi_device *ubi, int nested) { int err = 0; struct ubi_wl_entry *e1; @@ -981,11 +1342,11 @@ static int ensure_wear_leveling(struct ubi_device *ubi) /* * We schedule wear-leveling only if the difference between the * lowest erase counter of used physical eraseblocks and a high - * erase counter of free physical eraseblocks is greater then + * erase counter of free physical eraseblocks is greater than * %UBI_WL_THRESHOLD. */ - e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, rb); - e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF); + e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, u.rb); + e2 = find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF); if (!(e2->ec - e1->ec >= UBI_WL_THRESHOLD)) goto out_unlock; @@ -1002,8 +1363,12 @@ static int ensure_wear_leveling(struct ubi_device *ubi) goto out_cancel; } + wrk->anchor = 0; wrk->func = &wear_leveling_worker; - schedule_ubi_work(ubi, wrk); + if (nested) + __schedule_ubi_work(ubi, wrk); + else + schedule_ubi_work(ubi, wrk); return err; out_cancel: @@ -1014,6 +1379,38 @@ out_unlock: return err; } +#ifdef CONFIG_MTD_UBI_FASTMAP +/** + * ubi_ensure_anchor_pebs - schedule wear-leveling to produce an anchor PEB. + * @ubi: UBI device description object + */ +int ubi_ensure_anchor_pebs(struct ubi_device *ubi) +{ + struct ubi_work *wrk; + + spin_lock(&ubi->wl_lock); + if (ubi->wl_scheduled) { + spin_unlock(&ubi->wl_lock); + return 0; + } + ubi->wl_scheduled = 1; + spin_unlock(&ubi->wl_lock); + + wrk = kmalloc(sizeof(struct ubi_work), GFP_NOFS); + if (!wrk) { + spin_lock(&ubi->wl_lock); + ubi->wl_scheduled = 0; + spin_unlock(&ubi->wl_lock); + return -ENOMEM; + } + + wrk->anchor = 1; + wrk->func = &wear_leveling_worker; + schedule_ubi_work(ubi, wrk); + return 0; +} +#endif + /** * erase_worker - physical eraseblock erase worker function. * @ubi: UBI device description object @@ -1029,7 +1426,10 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, int cancel) { struct ubi_wl_entry *e = wl_wrk->e; - int pnum = e->pnum, err, need; + int pnum = e->pnum; + int vol_id = wl_wrk->vol_id; + int lnum = wl_wrk->lnum; + int err, available_consumed = 0; if (cancel) { dbg_wl("cancel erasure of PEB %d EC %d", pnum, e->ec); @@ -1038,7 +1438,10 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, return 0; } - dbg_wl("erase PEB %d EC %d", pnum, e->ec); + dbg_wl("erase PEB %d EC %d LEB %d:%d", + pnum, e->ec, wl_wrk->vol_id, wl_wrk->lnum); + + ubi_assert(!ubi_is_fm_block(ubi, e->pnum)); err = sync_erase(ubi, e, wl_wrk->torture); if (!err) { @@ -1046,44 +1449,45 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, kfree(wl_wrk); spin_lock(&ubi->wl_lock); - ubi->abs_ec += 1; wl_tree_add(e, &ubi->free); + ubi->free_count++; spin_unlock(&ubi->wl_lock); /* - * One more erase operation has happened, take care about protected - * physical eraseblocks. + * One more erase operation has happened, take care about + * protected physical eraseblocks. */ - check_protection_over(ubi); + serve_prot_queue(ubi); /* And take care about wear-leveling */ - err = ensure_wear_leveling(ubi); + err = ensure_wear_leveling(ubi, 1); return err; } ubi_err("failed to erase PEB %d, error %d", pnum, err); kfree(wl_wrk); - kmem_cache_free(ubi_wl_entry_slab, e); if (err == -EINTR || err == -ENOMEM || err == -EAGAIN || err == -EBUSY) { int err1; /* Re-schedule the LEB for erasure */ - err1 = schedule_erase(ubi, e, 0); + err1 = schedule_erase(ubi, e, vol_id, lnum, 0); if (err1) { err = err1; goto out_ro; } return err; - } else if (err != -EIO) { + } + + kmem_cache_free(ubi_wl_entry_slab, e); + if (err != -EIO) /* * If this is not %-EIO, we have no idea what to do. Scheduling * this physical eraseblock for erasure again would cause - * errors again and again. Well, lets switch to RO mode. + * errors again and again. Well, lets switch to R/O mode. */ goto out_ro; - } /* It is %-EIO, the PEB went bad */ @@ -1093,48 +1497,62 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, } spin_lock(&ubi->volumes_lock); - need = ubi->beb_rsvd_level - ubi->beb_rsvd_pebs + 1; - if (need > 0) { - need = ubi->avail_pebs >= need ? need : ubi->avail_pebs; - ubi->avail_pebs -= need; - ubi->rsvd_pebs += need; - ubi->beb_rsvd_pebs += need; - if (need > 0) - ubi_msg("reserve more %d PEBs", need); - } - if (ubi->beb_rsvd_pebs == 0) { - spin_unlock(&ubi->volumes_lock); - ubi_err("no reserved physical eraseblocks"); - goto out_ro; + if (ubi->avail_pebs == 0) { + spin_unlock(&ubi->volumes_lock); + ubi_err("no reserved/available physical eraseblocks"); + goto out_ro; + } + ubi->avail_pebs -= 1; + available_consumed = 1; } - spin_unlock(&ubi->volumes_lock); - ubi_msg("mark PEB %d as bad", pnum); + ubi_msg("mark PEB %d as bad", pnum); err = ubi_io_mark_bad(ubi, pnum); if (err) goto out_ro; spin_lock(&ubi->volumes_lock); - ubi->beb_rsvd_pebs -= 1; + if (ubi->beb_rsvd_pebs > 0) { + if (available_consumed) { + /* + * The amount of reserved PEBs increased since we last + * checked. + */ + ubi->avail_pebs += 1; + available_consumed = 0; + } + ubi->beb_rsvd_pebs -= 1; + } ubi->bad_peb_count += 1; ubi->good_peb_count -= 1; ubi_calculate_reserved(ubi); - if (ubi->beb_rsvd_pebs == 0) - ubi_warn("last PEB from the reserved pool was used"); + if (available_consumed) + ubi_warn("no PEBs in the reserved pool, used an available PEB"); + else if (ubi->beb_rsvd_pebs) + ubi_msg("%d PEBs left in the reserve", ubi->beb_rsvd_pebs); + else + ubi_warn("last PEB from the reserve was used"); spin_unlock(&ubi->volumes_lock); return err; out_ro: + if (available_consumed) { + spin_lock(&ubi->volumes_lock); + ubi->avail_pebs += 1; + spin_unlock(&ubi->volumes_lock); + } ubi_ro_mode(ubi); return err; } /** - * ubi_wl_put_peb - return a physical eraseblock to the wear-leveling unit. + * ubi_wl_put_peb - return a PEB to the wear-leveling sub-system. * @ubi: UBI device description object + * @vol_id: the volume ID that last used this PEB + * @lnum: the last used logical eraseblock number for the PEB * @pnum: physical eraseblock to return * @torture: if this physical eraseblock has to be tortured * @@ -1143,7 +1561,8 @@ out_ro: * occurred to this @pnum and it has to be tested. This function returns zero * in case of success, and a negative error code in case of failure. */ -int ubi_wl_put_peb(struct ubi_device *ubi, int pnum, int torture) +int ubi_wl_put_peb(struct ubi_device *ubi, int vol_id, int lnum, + int pnum, int torture) { int err; struct ubi_wl_entry *e; @@ -1172,11 +1591,11 @@ retry: /* * User is putting the physical eraseblock which was selected * as the target the data is moved to. It may happen if the EBA - * unit already re-mapped the LEB in 'ubi_eba_copy_leb()' but - * the WL unit has not put the PEB to the "used" tree yet, but - * it is about to do this. So we just set a flag which will - * tell the WL worker that the PEB is not needed anymore and - * should be scheduled for erasure. + * sub-system already re-mapped the LEB in 'ubi_eba_copy_leb()' + * but the WL sub-system has not put the PEB to the "used" tree + * yet, but it is about to do this. So we just set a flag which + * will tell the WL worker that the PEB is not needed anymore + * and should be scheduled for erasure. */ dbg_wl("PEB %d is the target of data moving", pnum); ubi_assert(!ubi->move_to_put); @@ -1185,13 +1604,20 @@ retry: return 0; } else { if (in_wl_tree(e, &ubi->used)) { - paranoid_check_in_wl_tree(e, &ubi->used); - rb_erase(&e->rb, &ubi->used); + self_check_in_wl_tree(ubi, e, &ubi->used); + rb_erase(&e->u.rb, &ubi->used); } else if (in_wl_tree(e, &ubi->scrub)) { - paranoid_check_in_wl_tree(e, &ubi->scrub); - rb_erase(&e->rb, &ubi->scrub); + self_check_in_wl_tree(ubi, e, &ubi->scrub); + rb_erase(&e->u.rb, &ubi->scrub); + } else if (in_wl_tree(e, &ubi->erroneous)) { + self_check_in_wl_tree(ubi, e, &ubi->erroneous); + rb_erase(&e->u.rb, &ubi->erroneous); + ubi->erroneous_peb_count -= 1; + ubi_assert(ubi->erroneous_peb_count >= 0); + /* Erroneous PEBs should be tortured */ + torture = 1; } else { - err = prot_tree_del(ubi, e->pnum); + err = prot_queue_del(ubi, e->pnum); if (err) { ubi_err("PEB %d not found", pnum); ubi_ro_mode(ubi); @@ -1202,7 +1628,7 @@ retry: } spin_unlock(&ubi->wl_lock); - err = schedule_erase(ubi, e, torture); + err = schedule_erase(ubi, e, vol_id, lnum, torture); if (err) { spin_lock(&ubi->wl_lock); wl_tree_add(e, &ubi->used); @@ -1231,7 +1657,8 @@ int ubi_wl_scrub_peb(struct ubi_device *ubi, int pnum) retry: spin_lock(&ubi->wl_lock); e = ubi->lookuptbl[pnum]; - if (e == ubi->move_from || in_wl_tree(e, &ubi->scrub)) { + if (e == ubi->move_from || in_wl_tree(e, &ubi->scrub) || + in_wl_tree(e, &ubi->erroneous)) { spin_unlock(&ubi->wl_lock); return 0; } @@ -1250,12 +1677,12 @@ retry: } if (in_wl_tree(e, &ubi->used)) { - paranoid_check_in_wl_tree(e, &ubi->used); - rb_erase(&e->rb, &ubi->used); + self_check_in_wl_tree(ubi, e, &ubi->used); + rb_erase(&e->u.rb, &ubi->used); } else { int err; - err = prot_tree_del(ubi, e->pnum); + err = prot_queue_del(ubi, e->pnum); if (err) { ubi_err("PEB %d not found", pnum); ubi_ro_mode(ubi); @@ -1271,29 +1698,60 @@ retry: * Technically scrubbing is the same as wear-leveling, so it is done * by the WL worker. */ - return ensure_wear_leveling(ubi); + return ensure_wear_leveling(ubi, 0); } /** * ubi_wl_flush - flush all pending works. * @ubi: UBI device description object + * @vol_id: the volume id to flush for + * @lnum: the logical eraseblock number to flush for * - * This function returns zero in case of success and a negative error code in - * case of failure. + * This function executes all pending works for a particular volume id / + * logical eraseblock number pair. If either value is set to %UBI_ALL, then it + * acts as a wildcard for all of the corresponding volume numbers or logical + * eraseblock numbers. It returns zero in case of success and a negative error + * code in case of failure. */ -int ubi_wl_flush(struct ubi_device *ubi) +int ubi_wl_flush(struct ubi_device *ubi, int vol_id, int lnum) { - int err; + int err = 0; + int found = 1; /* - * Erase while the pending works queue is not empty, but not more then + * Erase while the pending works queue is not empty, but not more than * the number of currently pending works. */ - dbg_wl("flush (%d pending works)", ubi->works_count); - while (ubi->works_count) { - err = do_work(ubi); - if (err) - return err; + dbg_wl("flush pending work for LEB %d:%d (%d pending works)", + vol_id, lnum, ubi->works_count); + + while (found) { + struct ubi_work *wrk; + found = 0; + + down_read(&ubi->work_sem); + spin_lock(&ubi->wl_lock); + list_for_each_entry(wrk, &ubi->works, list) { + if ((vol_id == UBI_ALL || wrk->vol_id == vol_id) && + (lnum == UBI_ALL || wrk->lnum == lnum)) { + list_del(&wrk->list); + ubi->works_count -= 1; + ubi_assert(ubi->works_count >= 0); + spin_unlock(&ubi->wl_lock); + + err = wrk->func(ubi, wrk, 0); + if (err) { + up_read(&ubi->work_sem); + return err; + } + + spin_lock(&ubi->wl_lock); + found = 1; + break; + } + } + spin_unlock(&ubi->wl_lock); + up_read(&ubi->work_sem); } /* @@ -1303,18 +1761,7 @@ int ubi_wl_flush(struct ubi_device *ubi) down_write(&ubi->work_sem); up_write(&ubi->work_sem); - /* - * And in case last was the WL worker and it cancelled the LEB - * movement, flush again. - */ - while (ubi->works_count) { - dbg_wl("flush more (%d pending works)", ubi->works_count); - err = do_work(ubi); - if (err) - return err; - } - - return 0; + return err; } /** @@ -1333,11 +1780,11 @@ static void tree_destroy(struct rb_root *root) else if (rb->rb_right) rb = rb->rb_right; else { - e = rb_entry(rb, struct ubi_wl_entry, rb); + e = rb_entry(rb, struct ubi_wl_entry, u.rb); rb = rb_parent(rb); if (rb) { - if (rb->rb_left == &e->rb) + if (rb->rb_left == &e->u.rb) rb->rb_left = NULL; else rb->rb_right = NULL; @@ -1372,7 +1819,7 @@ int ubi_thread(void *u) spin_lock(&ubi->wl_lock); if (list_empty(&ubi->works) || ubi->ro_mode || - !ubi->thread_enabled) { + !ubi->thread_enabled || ubi_dbg_is_bgt_disabled(ubi)) { set_current_state(TASK_INTERRUPTIBLE); spin_unlock(&ubi->wl_lock); schedule(); @@ -1392,7 +1839,8 @@ int ubi_thread(void *u) ubi_msg("%s: %d consecutive failures", ubi->bgt_name, WL_MAX_FAILURES); ubi_ro_mode(ubi); - break; + ubi->thread_enabled = 0; + continue; } } else failures = 0; @@ -1422,30 +1870,32 @@ static void cancel_pending(struct ubi_device *ubi) } /** - * ubi_wl_init_scan - initialize the wear-leveling unit using scanning - * information. + * ubi_wl_init - initialize the WL sub-system using attaching information. * @ubi: UBI device description object - * @si: scanning information + * @ai: attaching information * * This function returns zero in case of success, and a negative error code in * case of failure. */ -int ubi_wl_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) +int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai) { - int err; + int err, i, reserved_pebs, found_pebs = 0; struct rb_node *rb1, *rb2; - struct ubi_scan_volume *sv; - struct ubi_scan_leb *seb, *tmp; + struct ubi_ainf_volume *av; + struct ubi_ainf_peb *aeb, *tmp; struct ubi_wl_entry *e; - - ubi->used = ubi->free = ubi->scrub = RB_ROOT; - ubi->prot.pnum = ubi->prot.aec = RB_ROOT; + ubi->used = ubi->erroneous = ubi->free = ubi->scrub = RB_ROOT; spin_lock_init(&ubi->wl_lock); mutex_init(&ubi->move_mutex); init_rwsem(&ubi->work_sem); - ubi->max_ec = si->max_ec; + ubi->max_ec = ai->max_ec; INIT_LIST_HEAD(&ubi->works); +#ifndef __UBOOT__ +#ifdef CONFIG_MTD_UBI_FASTMAP + INIT_WORK(&ubi->fm_work, update_fastmap_work_fn); +#endif +#endif sprintf(ubi->bgt_name, UBI_BGT_NAME_PATTERN, ubi->ubi_num); @@ -1454,64 +1904,63 @@ int ubi_wl_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) if (!ubi->lookuptbl) return err; - list_for_each_entry_safe(seb, tmp, &si->erase, u.list) { + for (i = 0; i < UBI_PROT_QUEUE_LEN; i++) + INIT_LIST_HEAD(&ubi->pq[i]); + ubi->pq_head = 0; + + list_for_each_entry_safe(aeb, tmp, &ai->erase, u.list) { cond_resched(); e = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL); if (!e) goto out_free; - e->pnum = seb->pnum; - e->ec = seb->ec; + e->pnum = aeb->pnum; + e->ec = aeb->ec; + ubi_assert(!ubi_is_fm_block(ubi, e->pnum)); ubi->lookuptbl[e->pnum] = e; - if (schedule_erase(ubi, e, 0)) { + if (schedule_erase(ubi, e, aeb->vol_id, aeb->lnum, 0)) { kmem_cache_free(ubi_wl_entry_slab, e); goto out_free; } + + found_pebs++; } - list_for_each_entry(seb, &si->free, u.list) { + ubi->free_count = 0; + list_for_each_entry(aeb, &ai->free, u.list) { cond_resched(); e = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL); if (!e) goto out_free; - e->pnum = seb->pnum; - e->ec = seb->ec; + e->pnum = aeb->pnum; + e->ec = aeb->ec; ubi_assert(e->ec >= 0); - wl_tree_add(e, &ubi->free); - ubi->lookuptbl[e->pnum] = e; - } - - list_for_each_entry(seb, &si->corr, u.list) { - cond_resched(); + ubi_assert(!ubi_is_fm_block(ubi, e->pnum)); - e = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL); - if (!e) - goto out_free; + wl_tree_add(e, &ubi->free); + ubi->free_count++; - e->pnum = seb->pnum; - e->ec = seb->ec; ubi->lookuptbl[e->pnum] = e; - if (schedule_erase(ubi, e, 0)) { - kmem_cache_free(ubi_wl_entry_slab, e); - goto out_free; - } + + found_pebs++; } - ubi_rb_for_each_entry(rb1, sv, &si->volumes, rb) { - ubi_rb_for_each_entry(rb2, seb, &sv->root, u.rb) { + ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) { + ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb) { cond_resched(); e = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL); if (!e) goto out_free; - e->pnum = seb->pnum; - e->ec = seb->ec; + e->pnum = aeb->pnum; + e->ec = aeb->ec; ubi->lookuptbl[e->pnum] = e; - if (!seb->scrub) { + + if (!aeb->scrub) { dbg_wl("add PEB %d EC %d to the used tree", e->pnum, e->ec); wl_tree_add(e, &ubi->used); @@ -1520,20 +1969,38 @@ int ubi_wl_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) e->pnum, e->ec); wl_tree_add(e, &ubi->scrub); } + + found_pebs++; } } - if (ubi->avail_pebs < WL_RESERVED_PEBS) { + dbg_wl("found %i PEBs", found_pebs); + + if (ubi->fm) + ubi_assert(ubi->good_peb_count == \ + found_pebs + ubi->fm->used_blocks); + else + ubi_assert(ubi->good_peb_count == found_pebs); + + reserved_pebs = WL_RESERVED_PEBS; +#ifdef CONFIG_MTD_UBI_FASTMAP + /* Reserve enough LEBs to store two fastmaps. */ + reserved_pebs += (ubi->fm_size / ubi->leb_size) * 2; +#endif + + if (ubi->avail_pebs < reserved_pebs) { ubi_err("no enough physical eraseblocks (%d, need %d)", - ubi->avail_pebs, WL_RESERVED_PEBS); - err = -ENOSPC; + ubi->avail_pebs, reserved_pebs); + if (ubi->corr_peb_count) + ubi_err("%d PEBs are corrupted and not used", + ubi->corr_peb_count); goto out_free; } - ubi->avail_pebs -= WL_RESERVED_PEBS; - ubi->rsvd_pebs += WL_RESERVED_PEBS; + ubi->avail_pebs -= reserved_pebs; + ubi->rsvd_pebs += reserved_pebs; /* Schedule wear-leveling if needed */ - err = ensure_wear_leveling(ubi); + err = ensure_wear_leveling(ubi, 0); if (err) goto out_free; @@ -1549,72 +2016,57 @@ out_free: } /** - * protection_trees_destroy - destroy the protection RB-trees. + * protection_queue_destroy - destroy the protection queue. * @ubi: UBI device description object */ -static void protection_trees_destroy(struct ubi_device *ubi) +static void protection_queue_destroy(struct ubi_device *ubi) { - struct rb_node *rb; - struct ubi_wl_prot_entry *pe; - - rb = ubi->prot.aec.rb_node; - while (rb) { - if (rb->rb_left) - rb = rb->rb_left; - else if (rb->rb_right) - rb = rb->rb_right; - else { - pe = rb_entry(rb, struct ubi_wl_prot_entry, rb_aec); - - rb = rb_parent(rb); - if (rb) { - if (rb->rb_left == &pe->rb_aec) - rb->rb_left = NULL; - else - rb->rb_right = NULL; - } + int i; + struct ubi_wl_entry *e, *tmp; - kmem_cache_free(ubi_wl_entry_slab, pe->e); - kfree(pe); + for (i = 0; i < UBI_PROT_QUEUE_LEN; ++i) { + list_for_each_entry_safe(e, tmp, &ubi->pq[i], u.list) { + list_del(&e->u.list); + kmem_cache_free(ubi_wl_entry_slab, e); } } } /** - * ubi_wl_close - close the wear-leveling unit. + * ubi_wl_close - close the wear-leveling sub-system. * @ubi: UBI device description object */ void ubi_wl_close(struct ubi_device *ubi) { - dbg_wl("close the UBI wear-leveling unit"); - + dbg_wl("close the WL sub-system"); cancel_pending(ubi); - protection_trees_destroy(ubi); + protection_queue_destroy(ubi); tree_destroy(&ubi->used); + tree_destroy(&ubi->erroneous); tree_destroy(&ubi->free); tree_destroy(&ubi->scrub); kfree(ubi->lookuptbl); } -#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID - /** - * paranoid_check_ec - make sure that the erase counter of a physical eraseblock - * is correct. + * self_check_ec - make sure that the erase counter of a PEB is correct. * @ubi: UBI device description object * @pnum: the physical eraseblock number to check * @ec: the erase counter to check * * This function returns zero if the erase counter of physical eraseblock @pnum - * is equivalent to @ec, %1 if not, and a negative error code if an error + * is equivalent to @ec, and a negative error code if not or if an error * occurred. */ -static int paranoid_check_ec(struct ubi_device *ubi, int pnum, int ec) +static int self_check_ec(struct ubi_device *ubi, int pnum, int ec) { int err; long long read_ec; struct ubi_ec_hdr *ec_hdr; + if (!ubi_dbg_chk_gen(ubi)) + return 0; + ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_NOFS); if (!ec_hdr) return -ENOMEM; @@ -1627,10 +2079,10 @@ static int paranoid_check_ec(struct ubi_device *ubi, int pnum, int ec) } read_ec = be64_to_cpu(ec_hdr->ec); - if (ec != read_ec) { - ubi_err("paranoid check failed for PEB %d", pnum); + if (ec != read_ec && read_ec - ec > 1) { + ubi_err("self-check failed for PEB %d", pnum); ubi_err("read EC is %lld, should be %d", read_ec, ec); - ubi_dbg_dump_stack(); + dump_stack(); err = 1; } else err = 0; @@ -1641,24 +2093,53 @@ out_free: } /** - * paranoid_check_in_wl_tree - make sure that a wear-leveling entry is present - * in a WL RB-tree. + * self_check_in_wl_tree - check that wear-leveling entry is in WL RB-tree. + * @ubi: UBI device description object * @e: the wear-leveling entry to check * @root: the root of the tree * - * This function returns zero if @e is in the @root RB-tree and %1 if it + * This function returns zero if @e is in the @root RB-tree and %-EINVAL if it * is not. */ -static int paranoid_check_in_wl_tree(struct ubi_wl_entry *e, - struct rb_root *root) +static int self_check_in_wl_tree(const struct ubi_device *ubi, + struct ubi_wl_entry *e, struct rb_root *root) { + if (!ubi_dbg_chk_gen(ubi)) + return 0; + if (in_wl_tree(e, root)) return 0; - ubi_err("paranoid check failed for PEB %d, EC %d, RB-tree %p ", + ubi_err("self-check failed for PEB %d, EC %d, RB-tree %p ", e->pnum, e->ec, root); - ubi_dbg_dump_stack(); - return 1; + dump_stack(); + return -EINVAL; } -#endif /* CONFIG_MTD_UBI_DEBUG_PARANOID */ +/** + * self_check_in_pq - check if wear-leveling entry is in the protection + * queue. + * @ubi: UBI device description object + * @e: the wear-leveling entry to check + * + * This function returns zero if @e is in @ubi->pq and %-EINVAL if it is not. + */ +static int self_check_in_pq(const struct ubi_device *ubi, + struct ubi_wl_entry *e) +{ + struct ubi_wl_entry *p; + int i; + + if (!ubi_dbg_chk_gen(ubi)) + return 0; + + for (i = 0; i < UBI_PROT_QUEUE_LEN; ++i) + list_for_each_entry(p, &ubi->pq[i], u.list) + if (p == e) + return 0; + + ubi_err("self-check failed for PEB %d, EC %d, Protect queue", + e->pnum, e->ec); + dump_stack(); + return -EINVAL; +} diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 7c6e362f0e..381ec42864 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -1,25 +1,6 @@ -/*-----------------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /*-----------------------------------------------------------------------------+ * * File Name: enetemac.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig new file mode 100644 index 0000000000..6c0abccb9d --- /dev/null +++ b/drivers/net/Kconfig @@ -0,0 +1,29 @@ +menuconfig NETDEVICES + bool "Network device support" + depends on NET + +if NETDEVICES + +config MII + bool + +config FEC_MXC + bool "Freescale FEC ethernet controller" + select MII + +config GET_FEC_MAC_ADDR_FROM_IIM + bool "Read FEC MAC address from fuses" + depends on FEC_MXC + +if FEC_MXC + +config FEC_MXC_PHYADDR + int "FEC Ethernet PHY address" + default 0 + depends on !FEC_MXC_MULTI + +endif + +source "drivers/net/phy/Kconfig" + +endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 18fd54fc66..46c4ac697d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -5,83 +5,65 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libnet.o - -COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o -COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o -COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o -COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o -COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o -COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o -COBJS-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o -COBJS-$(CONFIG_CS8900) += cs8900.o -COBJS-$(CONFIG_TULIP) += dc2114x.o -COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o -COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o -COBJS-$(CONFIG_DNET) += dnet.o -COBJS-$(CONFIG_E1000) += e1000.o -COBJS-$(CONFIG_E1000_SPI) += e1000_spi.o -COBJS-$(CONFIG_EEPRO100) += eepro100.o -COBJS-$(CONFIG_ENC28J60) += enc28j60.o -COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o -COBJS-$(CONFIG_ETHOC) += ethoc.o -COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o -COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o -COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o -COBJS-$(CONFIG_FTMAC110) += ftmac110.o -COBJS-$(CONFIG_FTMAC100) += ftmac100.o -COBJS-$(CONFIG_GRETH) += greth.o -COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o -COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o -COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o -COBJS-$(CONFIG_LAN91C96) += lan91c96.o -COBJS-$(CONFIG_MACB) += macb.o -COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o -COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o -COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o -COBJS-$(CONFIG_MVGBE) += mvgbe.o -COBJS-$(CONFIG_NATSEMI) += natsemi.o -COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o -COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o -COBJS-$(CONFIG_NETCONSOLE) += netconsole.o -COBJS-$(CONFIG_NS8382X) += ns8382x.o -COBJS-$(CONFIG_PCNET) += pcnet.o -COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o -COBJS-$(CONFIG_RTL8139) += rtl8139.o -COBJS-$(CONFIG_RTL8169) += rtl8169.o -COBJS-$(CONFIG_SH_ETHER) += sh_eth.o -COBJS-$(CONFIG_SMC91111) += smc91111.o -COBJS-$(CONFIG_SMC911X) += smc911x.o -COBJS-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o -COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o -COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o -COBJS-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o -COBJS-$(CONFIG_FMAN_ENET) += fsl_mdio.o -COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o -COBJS-$(CONFIG_ULI526X) += uli526x.o -COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o -COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o -COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o -COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ +obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o +obj-$(CONFIG_ALTERA_TSE) += altera_tse.o +obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o +obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o +obj-$(CONFIG_DRIVER_AX88180) += ax88180.o +obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o +obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o +obj-$(CONFIG_BFIN_MAC) += bfin_mac.o +obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o +obj-$(CONFIG_CS8900) += cs8900.o +obj-$(CONFIG_TULIP) += dc2114x.o +obj-$(CONFIG_DESIGNWARE_ETH) += designware.o +obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o +obj-$(CONFIG_DNET) += dnet.o +obj-$(CONFIG_E1000) += e1000.o +obj-$(CONFIG_E1000_SPI) += e1000_spi.o +obj-$(CONFIG_EEPRO100) += eepro100.o +obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o +obj-$(CONFIG_ENC28J60) += enc28j60.o +obj-$(CONFIG_EP93XX) += ep93xx_eth.o +obj-$(CONFIG_ETHOC) += ethoc.o +obj-$(CONFIG_FEC_MXC) += fec_mxc.o +obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +obj-$(CONFIG_FTGMAC100) += ftgmac100.o +obj-$(CONFIG_FTMAC110) += ftmac110.o +obj-$(CONFIG_FTMAC100) += ftmac100.o +obj-$(CONFIG_GRETH) += greth.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o +obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o +obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o +obj-$(CONFIG_LAN91C96) += lan91c96.o +obj-$(CONFIG_MACB) += macb.o +obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o +obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o +obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +obj-$(CONFIG_MVGBE) += mvgbe.o +obj-$(CONFIG_MVNETA) += mvneta.o +obj-$(CONFIG_NATSEMI) += natsemi.o +obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o +obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o +obj-$(CONFIG_NETCONSOLE) += netconsole.o +obj-$(CONFIG_NS8382X) += ns8382x.o +obj-$(CONFIG_PCNET) += pcnet.o +obj-$(CONFIG_RTL8139) += rtl8139.o +obj-$(CONFIG_RTL8169) += rtl8169.o +obj-$(CONFIG_SH_ETHER) += sh_eth.o +obj-$(CONFIG_SMC91111) += smc91111.o +obj-$(CONFIG_SMC911X) += smc911x.o +obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o +obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o +obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o +obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o +obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o +obj-$(CONFIG_ULI526X) += uli526x.o +obj-$(CONFIG_VSC7385_ENET) += vsc7385.o +obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o +obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o -COBJS-$(CONFIG_ZYNQ_GEM) += zynq_gem.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o +obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/ +obj-$(CONFIG_VSC9953) += vsc9953.o diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index 73612ea069..64d4c56ac5 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -10,19 +10,10 @@ #include #include -#ifndef CONFIG_AT91_LEGACY #include #include #include #include -#else -/* remove next 5 lines, if all RM9200 boards convert to at91 arch */ -#include -#include -#include -#include -#include -#endif #include #include #include diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c index f5017682d4..7f0cfe5940 100644 --- a/drivers/net/ax88180.c +++ b/drivers/net/ax88180.c @@ -157,7 +157,7 @@ static void ax88180_mac_reset (struct eth_device *dev) OUTW (dev, MISC_RESET_MAC, MISC); tmpval = INW (dev, MISC); - for (i = 0; i < (sizeof (program_seq) / sizeof (program_seq[0])); i++) + for (i = 0; i < ARRAY_SIZE(program_seq); i++) OUTW (dev, program_seq[i].value, program_seq[i].offset); } diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c new file mode 100644 index 0000000000..977feec351 --- /dev/null +++ b/drivers/net/bcm-sf2-eth-gmac.c @@ -0,0 +1,971 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef BCM_GMAC_DEBUG +#ifndef DEBUG +#define DEBUG +#endif +#endif + +#include +#include +#include +#include +#include +#include + +#include "bcm-sf2-eth.h" +#include "bcm-sf2-eth-gmac.h" + +#define SPINWAIT(exp, us) { \ + uint countdown = (us) + 9; \ + while ((exp) && (countdown >= 10)) {\ + udelay(10); \ + countdown -= 10; \ + } \ +} + +static int gmac_disable_dma(struct eth_dma *dma, int dir); +static int gmac_enable_dma(struct eth_dma *dma, int dir); + +/* DMA Descriptor */ +typedef struct { + /* misc control bits */ + uint32_t ctrl1; + /* buffer count and address extension */ + uint32_t ctrl2; + /* memory address of the date buffer, bits 31:0 */ + uint32_t addrlow; + /* memory address of the date buffer, bits 63:32 */ + uint32_t addrhigh; +} dma64dd_t; + +uint32_t g_dmactrlflags; + +static uint32_t dma_ctrlflags(uint32_t mask, uint32_t flags) +{ + debug("%s enter\n", __func__); + + g_dmactrlflags &= ~mask; + g_dmactrlflags |= flags; + + /* If trying to enable parity, check if parity is actually supported */ + if (g_dmactrlflags & DMA_CTRL_PEN) { + uint32_t control; + + control = readl(GMAC0_DMA_TX_CTRL_ADDR); + writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR); + if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) { + /* + * We *can* disable it, therefore it is supported; + * restore control register + */ + writel(control, GMAC0_DMA_TX_CTRL_ADDR); + } else { + /* Not supported, don't allow it to be enabled */ + g_dmactrlflags &= ~DMA_CTRL_PEN; + } + } + + return g_dmactrlflags; +} + +static inline void reg32_clear_bits(uint32_t reg, uint32_t value) +{ + uint32_t v = readl(reg); + v &= ~(value); + writel(v, reg); +} + +static inline void reg32_set_bits(uint32_t reg, uint32_t value) +{ + uint32_t v = readl(reg); + v |= value; + writel(v, reg); +} + +#ifdef BCM_GMAC_DEBUG +static void dma_tx_dump(struct eth_dma *dma) +{ + dma64dd_t *descp = NULL; + uint8_t *bufp; + int i; + + printf("TX DMA Register:\n"); + printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n", + readl(GMAC0_DMA_TX_CTRL_ADDR), + readl(GMAC0_DMA_TX_PTR_ADDR), + readl(GMAC0_DMA_TX_ADDR_LOW_ADDR), + readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR), + readl(GMAC0_DMA_TX_STATUS0_ADDR), + readl(GMAC0_DMA_TX_STATUS1_ADDR)); + + printf("TX Descriptors:\n"); + for (i = 0; i < TX_BUF_NUM; i++) { + descp = (dma64dd_t *)(dma->tx_desc_aligned) + i; + printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n", + descp->ctrl1, descp->ctrl2, + descp->addrhigh, descp->addrlow); + } + + printf("TX Buffers:\n"); + /* Initialize TX DMA descriptor table */ + for (i = 0; i < TX_BUF_NUM; i++) { + bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE); + printf("buf%d:0x%x; ", i, (uint32_t)bufp); + } + printf("\n"); +} + +static void dma_rx_dump(struct eth_dma *dma) +{ + dma64dd_t *descp = NULL; + uint8_t *bufp; + int i; + + printf("RX DMA Register:\n"); + printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n", + readl(GMAC0_DMA_RX_CTRL_ADDR), + readl(GMAC0_DMA_RX_PTR_ADDR), + readl(GMAC0_DMA_RX_ADDR_LOW_ADDR), + readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR), + readl(GMAC0_DMA_RX_STATUS0_ADDR), + readl(GMAC0_DMA_RX_STATUS1_ADDR)); + + printf("RX Descriptors:\n"); + for (i = 0; i < RX_BUF_NUM; i++) { + descp = (dma64dd_t *)(dma->rx_desc_aligned) + i; + printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n", + descp->ctrl1, descp->ctrl2, + descp->addrhigh, descp->addrlow); + } + + printf("RX Buffers:\n"); + for (i = 0; i < RX_BUF_NUM; i++) { + bufp = dma->rx_buf + i * RX_BUF_SIZE; + printf("buf%d:0x%x; ", i, (uint32_t)bufp); + } + printf("\n"); +} +#endif + +static int dma_tx_init(struct eth_dma *dma) +{ + dma64dd_t *descp = NULL; + uint8_t *bufp; + int i; + uint32_t ctrl; + + debug("%s enter\n", __func__); + + /* clear descriptor memory */ + memset((void *)(dma->tx_desc_aligned), 0, + TX_BUF_NUM * sizeof(dma64dd_t)); + memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE); + + /* Initialize TX DMA descriptor table */ + for (i = 0; i < TX_BUF_NUM; i++) { + descp = (dma64dd_t *)(dma->tx_desc_aligned) + i; + bufp = dma->tx_buf + i * TX_BUF_SIZE; + /* clear buffer memory */ + memset((void *)bufp, 0, TX_BUF_SIZE); + + ctrl = 0; + /* if last descr set endOfTable */ + if (i == (TX_BUF_NUM-1)) + ctrl = D64_CTRL1_EOT; + descp->ctrl1 = ctrl; + descp->ctrl2 = 0; + descp->addrlow = (uint32_t)bufp; + descp->addrhigh = 0; + } + + /* flush descriptor and buffer */ + descp = dma->tx_desc_aligned; + bufp = dma->tx_buf; + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + + sizeof(dma64dd_t) * TX_BUF_NUM)); + flush_dcache_range((unsigned long)(bufp), + (unsigned long)(bufp + TX_BUF_SIZE * TX_BUF_NUM)); + + /* initialize the DMA channel */ + writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR); + writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR); + + /* now update the dma last descriptor */ + writel(((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK, + GMAC0_DMA_TX_PTR_ADDR); + + return 0; +} + +static int dma_rx_init(struct eth_dma *dma) +{ + uint32_t last_desc; + dma64dd_t *descp = NULL; + uint8_t *bufp; + uint32_t ctrl; + int i; + + debug("%s enter\n", __func__); + + /* clear descriptor memory */ + memset((void *)(dma->rx_desc_aligned), 0, + RX_BUF_NUM * sizeof(dma64dd_t)); + /* clear buffer memory */ + memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE); + + /* Initialize RX DMA descriptor table */ + for (i = 0; i < RX_BUF_NUM; i++) { + descp = (dma64dd_t *)(dma->rx_desc_aligned) + i; + bufp = dma->rx_buf + i * RX_BUF_SIZE; + ctrl = 0; + /* if last descr set endOfTable */ + if (i == (RX_BUF_NUM - 1)) + ctrl = D64_CTRL1_EOT; + descp->ctrl1 = ctrl; + descp->ctrl2 = RX_BUF_SIZE; + descp->addrlow = (uint32_t)bufp; + descp->addrhigh = 0; + + last_desc = ((uint32_t)(descp) & D64_XP_LD_MASK) + + sizeof(dma64dd_t); + } + + descp = dma->rx_desc_aligned; + bufp = dma->rx_buf; + /* flush descriptor and buffer */ + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + + sizeof(dma64dd_t) * RX_BUF_NUM)); + flush_dcache_range((unsigned long)(bufp), + (unsigned long)(bufp + RX_BUF_SIZE * RX_BUF_NUM)); + + /* initailize the DMA channel */ + writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR); + writel(0, GMAC0_DMA_RX_ADDR_HIGH_ADDR); + + /* now update the dma last descriptor */ + writel(last_desc, GMAC0_DMA_RX_PTR_ADDR); + + return 0; +} + +static int dma_init(struct eth_dma *dma) +{ + debug(" %s enter\n", __func__); + + /* + * Default flags: For backwards compatibility both + * Rx Overflow Continue and Parity are DISABLED. + */ + dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN, 0); + + debug("rx burst len 0x%x\n", + (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK) + >> D64_RC_BL_SHIFT); + debug("tx burst len 0x%x\n", + (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK) + >> D64_XC_BL_SHIFT); + + dma_tx_init(dma); + dma_rx_init(dma); + + /* From end of chip_init() */ + /* enable the overflow continue feature and disable parity */ + dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN /* mask */, + DMA_CTRL_ROC /* value */); + + return 0; +} + +static int dma_deinit(struct eth_dma *dma) +{ + debug(" %s enter\n", __func__); + + gmac_disable_dma(dma, MAC_DMA_RX); + gmac_disable_dma(dma, MAC_DMA_TX); + + free(dma->tx_buf); + dma->tx_buf = NULL; + free(dma->tx_desc); + dma->tx_desc = NULL; + dma->tx_desc_aligned = NULL; + + free(dma->rx_buf); + dma->rx_buf = NULL; + free(dma->rx_desc); + dma->rx_desc = NULL; + dma->rx_desc_aligned = NULL; + + return 0; +} + +int gmac_tx_packet(struct eth_dma *dma, void *packet, int length) +{ + uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE; + + /* kick off the dma */ + size_t len = length; + int txout = dma->cur_tx_index; + uint32_t flags; + dma64dd_t *descp = NULL; + uint32_t ctrl; + uint32_t last_desc = (((uint32_t)dma->tx_desc_aligned) + + sizeof(dma64dd_t)) & D64_XP_LD_MASK; + size_t buflen; + + debug("%s enter\n", __func__); + + /* load the buffer */ + memcpy(bufp, packet, len); + + /* Add 4 bytes for Ethernet FCS/CRC */ + buflen = len + 4; + + ctrl = (buflen & D64_CTRL2_BC_MASK); + + /* the transmit will only be one frame or set SOF, EOF */ + /* also set int on completion */ + flags = D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF; + + /* txout points to the descriptor to uset */ + /* if last descriptor then set EOT */ + if (txout == (TX_BUF_NUM - 1)) { + flags |= D64_CTRL1_EOT; + last_desc = ((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK; + } + + /* write the descriptor */ + descp = ((dma64dd_t *)(dma->tx_desc_aligned)) + txout; + descp->addrlow = (uint32_t)bufp; + descp->addrhigh = 0; + descp->ctrl1 = flags; + descp->ctrl2 = ctrl; + + /* flush descriptor and buffer */ + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + sizeof(dma64dd_t))); + flush_dcache_range((unsigned long)bufp, + (unsigned long)(bufp + TX_BUF_SIZE)); + + /* now update the dma last descriptor */ + writel(last_desc, GMAC0_DMA_TX_PTR_ADDR); + + /* tx dma should be enabled so packet should go out */ + + /* update txout */ + dma->cur_tx_index = (txout + 1) & (TX_BUF_NUM - 1); + + return 0; +} + +bool gmac_check_tx_done(struct eth_dma *dma) +{ + /* wait for tx to complete */ + uint32_t intstatus; + bool xfrdone = false; + + debug("%s enter\n", __func__); + + intstatus = readl(GMAC0_INT_STATUS_ADDR); + + debug("int(0x%x)\n", intstatus); + if (intstatus & (I_XI0 | I_XI1 | I_XI2 | I_XI3)) { + xfrdone = true; + /* clear the int bits */ + intstatus &= ~(I_XI0 | I_XI1 | I_XI2 | I_XI3); + writel(intstatus, GMAC0_INT_STATUS_ADDR); + } else { + debug("Tx int(0x%x)\n", intstatus); + } + + return xfrdone; +} + +int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf) +{ + void *bufp, *datap; + size_t rcvlen = 0, buflen = 0; + uint32_t stat0 = 0, stat1 = 0; + uint32_t control, offset; + uint8_t statbuf[HWRXOFF*2]; + + int index, curr, active; + dma64dd_t *descp = NULL; + + /* udelay(50); */ + + /* + * this api will check if a packet has been received. + * If so it will return the address of the buffer and current + * descriptor index will be incremented to the + * next descriptor. Once done with the frame the buffer should be + * added back onto the descriptor and the lastdscr should be updated + * to this descriptor. + */ + index = dma->cur_rx_index; + offset = (uint32_t)(dma->rx_desc_aligned); + stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK; + stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK; + curr = ((stat0 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t); + active = ((stat1 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t); + + /* check if any frame */ + if (index == curr) + return -1; + + debug("received packet\n"); + debug("expect(0x%x) curr(0x%x) active(0x%x)\n", index, curr, active); + /* remove warning */ + if (index == active) + ; + + /* get the packet pointer that corresponds to the rx descriptor */ + bufp = dma->rx_buf + index * RX_BUF_SIZE; + + descp = (dma64dd_t *)(dma->rx_desc_aligned) + index; + /* flush descriptor and buffer */ + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + sizeof(dma64dd_t))); + flush_dcache_range((unsigned long)bufp, + (unsigned long)(bufp + RX_BUF_SIZE)); + + buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK); + + stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR); + stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR); + + debug("bufp(0x%x) index(0x%x) buflen(0x%x) stat0(0x%x) stat1(0x%x)\n", + (uint32_t)bufp, index, buflen, stat0, stat1); + + dma->cur_rx_index = (index + 1) & (RX_BUF_NUM - 1); + + /* get buffer offset */ + control = readl(GMAC0_DMA_RX_CTRL_ADDR); + offset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT; + rcvlen = *(uint16_t *)bufp; + + debug("Received %d bytes\n", rcvlen); + /* copy status into temp buf then copy data from rx buffer */ + memcpy(statbuf, bufp, offset); + datap = (void *)((uint32_t)bufp + offset); + memcpy(buf, datap, rcvlen); + + /* update descriptor that is being added back on ring */ + descp->ctrl2 = RX_BUF_SIZE; + descp->addrlow = (uint32_t)bufp; + descp->addrhigh = 0; + /* flush descriptor */ + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + sizeof(dma64dd_t))); + + /* set the lastdscr for the rx ring */ + writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR); + + return (int)rcvlen; +} + +static int gmac_disable_dma(struct eth_dma *dma, int dir) +{ + int status; + + debug("%s enter\n", __func__); + + if (dir == MAC_DMA_TX) { + /* address PR8249/PR7577 issue */ + /* suspend tx DMA first */ + writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR); + SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) & + D64_XS0_XS_MASK)) != + D64_XS0_XS_DISABLED) && + (status != D64_XS0_XS_IDLE) && + (status != D64_XS0_XS_STOPPED), 10000); + + /* + * PR2414 WAR: DMA engines are not disabled until + * transfer finishes + */ + writel(0, GMAC0_DMA_TX_CTRL_ADDR); + SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) & + D64_XS0_XS_MASK)) != + D64_XS0_XS_DISABLED), 10000); + + /* wait for the last transaction to complete */ + udelay(2); + + status = (status == D64_XS0_XS_DISABLED); + } else { + /* + * PR2414 WAR: DMA engines are not disabled until + * transfer finishes + */ + writel(0, GMAC0_DMA_RX_CTRL_ADDR); + SPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) & + D64_RS0_RS_MASK)) != + D64_RS0_RS_DISABLED), 10000); + + status = (status == D64_RS0_RS_DISABLED); + } + + return status; +} + +static int gmac_enable_dma(struct eth_dma *dma, int dir) +{ + uint32_t control; + + debug("%s enter\n", __func__); + + if (dir == MAC_DMA_TX) { + dma->cur_tx_index = 0; + + /* + * These bits 20:18 (burstLen) of control register can be + * written but will take effect only if these bits are + * valid. So this will not affect previous versions + * of the DMA. They will continue to have those bits set to 0. + */ + control = readl(GMAC0_DMA_TX_CTRL_ADDR); + + control |= D64_XC_XE; + if ((g_dmactrlflags & DMA_CTRL_PEN) == 0) + control |= D64_XC_PD; + + writel(control, GMAC0_DMA_TX_CTRL_ADDR); + + /* initailize the DMA channel */ + writel((uint32_t)(dma->tx_desc_aligned), + GMAC0_DMA_TX_ADDR_LOW_ADDR); + writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR); + } else { + dma->cur_rx_index = 0; + + control = (readl(GMAC0_DMA_RX_CTRL_ADDR) & + D64_RC_AE) | D64_RC_RE; + + if ((g_dmactrlflags & DMA_CTRL_PEN) == 0) + control |= D64_RC_PD; + + if (g_dmactrlflags & DMA_CTRL_ROC) + control |= D64_RC_OC; + + /* + * These bits 20:18 (burstLen) of control register can be + * written but will take effect only if these bits are + * valid. So this will not affect previous versions + * of the DMA. They will continue to have those bits set to 0. + */ + control &= ~D64_RC_BL_MASK; + /* Keep default Rx burstlen */ + control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK; + control |= HWRXOFF << D64_RC_RO_SHIFT; + + writel(control, GMAC0_DMA_RX_CTRL_ADDR); + + /* + * the rx descriptor ring should have + * the addresses set properly; + * set the lastdscr for the rx ring + */ + writel(((uint32_t)(dma->rx_desc_aligned) + + (RX_BUF_NUM - 1) * RX_BUF_SIZE) & + D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR); + } + + return 0; +} + +bool gmac_mii_busywait(unsigned int timeout) +{ + uint32_t tmp = 0; + + while (timeout > 10) { + tmp = readl(GMAC_MII_CTRL_ADDR); + if (tmp & (1 << GMAC_MII_BUSY_SHIFT)) { + udelay(10); + timeout -= 10; + } else { + break; + } + } + return tmp & (1 << GMAC_MII_BUSY_SHIFT); +} + +int gmac_miiphy_read(const char *devname, unsigned char phyaddr, + unsigned char reg, unsigned short *value) +{ + uint32_t tmp = 0; + + (void)devname; + + /* Busy wait timeout is 1ms */ + if (gmac_mii_busywait(1000)) { + error("%s: Prepare MII read: MII/MDIO busy\n", __func__); + return -1; + } + + /* Read operation */ + tmp = GMAC_MII_DATA_READ_CMD; + tmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) | + (reg << GMAC_MII_PHY_REG_SHIFT); + debug("MII read cmd 0x%x, phy 0x%x, reg 0x%x\n", tmp, phyaddr, reg); + writel(tmp, GMAC_MII_DATA_ADDR); + + if (gmac_mii_busywait(1000)) { + error("%s: MII read failure: MII/MDIO busy\n", __func__); + return -1; + } + + *value = readl(GMAC_MII_DATA_ADDR) & 0xffff; + debug("MII read data 0x%x\n", *value); + return 0; +} + +int gmac_miiphy_write(const char *devname, unsigned char phyaddr, + unsigned char reg, unsigned short value) +{ + uint32_t tmp = 0; + + (void)devname; + + /* Busy wait timeout is 1ms */ + if (gmac_mii_busywait(1000)) { + error("%s: Prepare MII write: MII/MDIO busy\n", __func__); + return -1; + } + + /* Write operation */ + tmp = GMAC_MII_DATA_WRITE_CMD | (value & 0xffff); + tmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) | + (reg << GMAC_MII_PHY_REG_SHIFT)); + debug("MII write cmd 0x%x, phy 0x%x, reg 0x%x, data 0x%x\n", + tmp, phyaddr, reg, value); + writel(tmp, GMAC_MII_DATA_ADDR); + + if (gmac_mii_busywait(1000)) { + error("%s: MII write failure: MII/MDIO busy\n", __func__); + return -1; + } + + return 0; +} + +void gmac_init_reset(void) +{ + debug("%s enter\n", __func__); + + /* set command config reg CC_SR */ + reg32_set_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR); + udelay(GMAC_RESET_DELAY); +} + +void gmac_clear_reset(void) +{ + debug("%s enter\n", __func__); + + /* clear command config reg CC_SR */ + reg32_clear_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR); + udelay(GMAC_RESET_DELAY); +} + +static void gmac_enable_local(bool en) +{ + uint32_t cmdcfg; + + debug("%s enter\n", __func__); + + /* read command config reg */ + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); + + /* put mac in reset */ + gmac_init_reset(); + + cmdcfg |= CC_SR; + + /* first deassert rx_ena and tx_ena while in reset */ + cmdcfg &= ~(CC_RE | CC_TE); + /* write command config reg */ + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + + /* bring mac out of reset */ + gmac_clear_reset(); + + /* if not enable exit now */ + if (!en) + return; + + /* enable the mac transmit and receive paths now */ + udelay(2); + cmdcfg &= ~CC_SR; + cmdcfg |= (CC_RE | CC_TE); + + /* assert rx_ena and tx_ena when out of reset to enable the mac */ + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + + return; +} + +int gmac_enable(void) +{ + gmac_enable_local(1); + + /* clear interrupts */ + writel(I_INTMASK, GMAC0_INT_STATUS_ADDR); + return 0; +} + +int gmac_disable(void) +{ + gmac_enable_local(0); + return 0; +} + +int gmac_set_speed(int speed, int duplex) +{ + uint32_t cmdcfg; + uint32_t hd_ena; + uint32_t speed_cfg; + + hd_ena = duplex ? 0 : CC_HD; + if (speed == 1000) { + speed_cfg = 2; + } else if (speed == 100) { + speed_cfg = 1; + } else if (speed == 10) { + speed_cfg = 0; + } else { + error("%s: Invalid GMAC speed(%d)!\n", __func__, speed); + return -1; + } + + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); + cmdcfg &= ~(CC_ES_MASK | CC_HD); + cmdcfg |= ((speed_cfg << CC_ES_SHIFT) | hd_ena); + + printf("Change GMAC speed to %dMB\n", speed); + debug("GMAC speed cfg 0x%x\n", cmdcfg); + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + + return 0; +} + +int gmac_set_mac_addr(unsigned char *mac) +{ + /* set our local address */ + debug("GMAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + writel(htonl(*(uint32_t *)mac), UNIMAC0_MAC_MSB_ADDR); + writew(htons(*(uint32_t *)&mac[4]), UNIMAC0_MAC_LSB_ADDR); + + return 0; +} + +int gmac_mac_init(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + + uint32_t tmp; + uint32_t cmdcfg; + int chipid; + + debug("%s enter\n", __func__); + + /* Always use GMAC0 */ + printf("Using GMAC%d\n", 0); + + /* Reset AMAC0 core */ + writel(0, AMAC0_IDM_RESET_ADDR); + tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR); + /* Set clock */ + tmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT); + tmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT); + /* Set Tx clock */ + tmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT); + writel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR); + + /* reset gmac */ + /* + * As AMAC is just reset, NO need? + * set eth_data into loopback mode to ensure no rx traffic + * gmac_loopback(eth_data, TRUE); + * ET_TRACE(("%s gmac loopback\n", __func__)); + * udelay(1); + */ + + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); + cmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML | + CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI | + CC_PAD_EN | CC_PF); + cmdcfg |= (CC_PROM | CC_NLC | CC_CFE); + /* put mac in reset */ + gmac_init_reset(); + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + gmac_clear_reset(); + + /* enable clear MIB on read */ + reg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR); + /* PHY: set smi_master to drive mdc_clk */ + reg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE); + + /* clear persistent sw intstatus */ + writel(0, GMAC0_INT_STATUS_ADDR); + + if (dma_init(dma) < 0) { + error("%s: GMAC dma_init failed\n", __func__); + goto err_exit; + } + + chipid = CHIPID; + printf("%s: Chip ID: 0x%x\n", __func__, chipid); + + /* set switch bypass mode */ + tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR); + tmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); + + /* Switch mode */ + /* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */ + + writel(tmp, SWITCH_GLOBAL_CONFIG_ADDR); + + tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR); + tmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT); + writel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR); + + /* Set MDIO to internal GPHY */ + tmp = readl(GMAC_MII_CTRL_ADDR); + /* Select internal MDC/MDIO bus*/ + tmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT); + /* select MDC/MDIO connecting to on-chip internal PHYs */ + tmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT); + /* + * give bit[6:0](MDCDIV) with required divisor to set + * the MDC clock frequency, 66MHZ/0x1A=2.5MHZ + */ + tmp |= 0x1A; + + writel(tmp, GMAC_MII_CTRL_ADDR); + + if (gmac_mii_busywait(1000)) { + error("%s: Configure MDIO: MII/MDIO busy\n", __func__); + goto err_exit; + } + + /* Configure GMAC0 */ + /* enable one rx interrupt per received frame */ + writel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR); + + /* read command config reg */ + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); + /* enable 802.3x tx flow control (honor received PAUSE frames) */ + cmdcfg &= ~CC_RPI; + /* enable promiscuous mode */ + cmdcfg |= CC_PROM; + /* Disable loopback mode */ + cmdcfg &= ~CC_ML; + /* set the speed */ + cmdcfg &= ~(CC_ES_MASK | CC_HD); + /* Set to 1Gbps and full duplex by default */ + cmdcfg |= (2 << CC_ES_SHIFT); + + /* put mac in reset */ + gmac_init_reset(); + /* write register */ + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + /* bring mac out of reset */ + gmac_clear_reset(); + + /* set max frame lengths; account for possible vlan tag */ + writel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR); + + return 0; + +err_exit: + dma_deinit(dma); + return -1; +} + +int gmac_add(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + void *tmp; + + /* + * Desc has to be 16-byte aligned ? + * If it is 8-byte aligned by malloc, fail Tx + */ + tmp = malloc(sizeof(dma64dd_t) * TX_BUF_NUM + 8); + if (tmp == NULL) { + printf("%s: Failed to allocate TX desc Buffer\n", __func__); + return -1; + } + + dma->tx_desc = (void *)tmp; + dma->tx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf)); + debug("TX Descriptor Buffer: %p; length: 0x%x\n", + dma->tx_desc_aligned, sizeof(dma64dd_t) * TX_BUF_NUM); + + tmp = malloc(TX_BUF_SIZE * TX_BUF_NUM); + if (tmp == NULL) { + printf("%s: Failed to allocate TX Data Buffer\n", __func__); + free(dma->tx_desc); + return -1; + } + dma->tx_buf = (uint8_t *)tmp; + debug("TX Data Buffer: %p; length: 0x%x\n", + dma->tx_buf, TX_BUF_SIZE * TX_BUF_NUM); + + /* Desc has to be 16-byte aligned ? */ + tmp = malloc(sizeof(dma64dd_t) * RX_BUF_NUM + 8); + if (tmp == NULL) { + printf("%s: Failed to allocate RX Descriptor\n", __func__); + free(dma->tx_desc); + free(dma->tx_buf); + return -1; + } + dma->rx_desc = tmp; + dma->rx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf)); + debug("RX Descriptor Buffer: %p, length: 0x%x\n", + dma->rx_desc_aligned, sizeof(dma64dd_t) * RX_BUF_NUM); + + tmp = malloc(RX_BUF_SIZE * RX_BUF_NUM); + if (tmp == NULL) { + printf("%s: Failed to allocate RX Data Buffer\n", __func__); + free(dma->tx_desc); + free(dma->tx_buf); + free(dma->rx_desc); + return -1; + } + dma->rx_buf = tmp; + debug("RX Data Buffer: %p; length: 0x%x\n", + dma->rx_buf, RX_BUF_SIZE * RX_BUF_NUM); + + g_dmactrlflags = 0; + + eth->phy_interface = PHY_INTERFACE_MODE_GMII; + + dma->tx_packet = gmac_tx_packet; + dma->check_tx_done = gmac_check_tx_done; + + dma->check_rx_done = gmac_check_rx_done; + + dma->enable_dma = gmac_enable_dma; + dma->disable_dma = gmac_disable_dma; + + eth->miiphy_read = gmac_miiphy_read; + eth->miiphy_write = gmac_miiphy_write; + + eth->mac_init = gmac_mac_init; + eth->disable_mac = gmac_disable; + eth->enable_mac = gmac_enable; + eth->set_mac_addr = gmac_set_mac_addr; + eth->set_mac_speed = gmac_set_speed; + + return 0; +} diff --git a/drivers/net/bcm-sf2-eth-gmac.h b/drivers/net/bcm-sf2-eth-gmac.h new file mode 100644 index 0000000000..810a617269 --- /dev/null +++ b/drivers/net/bcm-sf2-eth-gmac.h @@ -0,0 +1,224 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BCM_SF2_ETH_GMAC_H_ +#define _BCM_SF2_ETH_GMAC_H_ + +#define BCM_SF2_ETH_MAC_NAME "gmac" + +#ifndef ETHHW_PORT_INT +#define ETHHW_PORT_INT 8 +#endif + +#define GMAC0_REG_BASE 0x18042000 +#define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE +#define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020) +#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100) +#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188) + + +#define GMAC_DMA_PTR_OFFSET 0x04 +#define GMAC_DMA_ADDR_LOW_OFFSET 0x08 +#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c +#define GMAC_DMA_STATUS0_OFFSET 0x10 +#define GMAC_DMA_STATUS1_OFFSET 0x14 + +#define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200) +#define GMAC0_DMA_TX_PTR_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) +#define GMAC0_DMA_TX_ADDR_LOW_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) +#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) +#define GMAC0_DMA_TX_STATUS0_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) +#define GMAC0_DMA_TX_STATUS1_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) + +#define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220) +#define GMAC0_DMA_RX_PTR_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) +#define GMAC0_DMA_RX_ADDR_LOW_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) +#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) +#define GMAC0_DMA_RX_STATUS0_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) +#define GMAC0_DMA_RX_STATUS1_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) + +#define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808) +#define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c) +#define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810) +#define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814) + +#define GMAC0_IRL_FRAMECOUNT_SHIFT 24 + +/* transmit channel control */ +/* transmit enable */ +#define D64_XC_XE 0x00000001 +/* transmit suspend request */ +#define D64_XC_SE 0x00000002 +/* parity check disable */ +#define D64_XC_PD 0x00000800 +/* BurstLen bits */ +#define D64_XC_BL_MASK 0x001C0000 +#define D64_XC_BL_SHIFT 18 + +/* transmit descriptor table pointer */ +/* last valid descriptor */ +#define D64_XP_LD_MASK 0x00001fff + +/* transmit channel status */ +/* transmit state */ +#define D64_XS0_XS_MASK 0xf0000000 +#define D64_XS0_XS_SHIFT 28 +#define D64_XS0_XS_DISABLED 0x00000000 +#define D64_XS0_XS_ACTIVE 0x10000000 +#define D64_XS0_XS_IDLE 0x20000000 +#define D64_XS0_XS_STOPPED 0x30000000 +#define D64_XS0_XS_SUSP 0x40000000 + +/* receive channel control */ +/* receive enable */ +#define D64_RC_RE 0x00000001 +/* address extension bits */ +#define D64_RC_AE 0x00030000 +/* overflow continue */ +#define D64_RC_OC 0x00000400 +/* parity check disable */ +#define D64_RC_PD 0x00000800 +/* receive frame offset */ +#define D64_RC_RO_MASK 0x000000fe +#define D64_RC_RO_SHIFT 1 +/* BurstLen bits */ +#define D64_RC_BL_MASK 0x001C0000 +#define D64_RC_BL_SHIFT 18 + +/* flags for dma controller */ +/* partity enable */ +#define DMA_CTRL_PEN (1 << 0) +/* rx overflow continue */ +#define DMA_CTRL_ROC (1 << 1) + +/* receive descriptor table pointer */ +/* last valid descriptor */ +#define D64_RP_LD_MASK 0x00001fff + +/* receive channel status */ +/* current descriptor pointer */ +#define D64_RS0_CD_MASK 0x00001fff +/* receive state */ +#define D64_RS0_RS_MASK 0xf0000000 +#define D64_RS0_RS_SHIFT 28 +#define D64_RS0_RS_DISABLED 0x00000000 +#define D64_RS0_RS_ACTIVE 0x10000000 +#define D64_RS0_RS_IDLE 0x20000000 +#define D64_RS0_RS_STOPPED 0x30000000 +#define D64_RS0_RS_SUSP 0x40000000 + +/* descriptor control flags 1 */ +/* core specific flags */ +#define D64_CTRL_COREFLAGS 0x0ff00000 +/* end of descriptor table */ +#define D64_CTRL1_EOT ((uint32_t)1 << 28) +/* interrupt on completion */ +#define D64_CTRL1_IOC ((uint32_t)1 << 29) +/* end of frame */ +#define D64_CTRL1_EOF ((uint32_t)1 << 30) +/* start of frame */ +#define D64_CTRL1_SOF ((uint32_t)1 << 31) + +/* descriptor control flags 2 */ +/* buffer byte count. real data len must <= 16KB */ +#define D64_CTRL2_BC_MASK 0x00007fff +/* address extension bits */ +#define D64_CTRL2_AE 0x00030000 +#define D64_CTRL2_AE_SHIFT 16 +/* parity bit */ +#define D64_CTRL2_PARITY 0x00040000 +/* control flags in the range [27:20] are core-specific and not defined here */ +#define D64_CTRL_CORE_MASK 0x0ff00000 + +#define DC_MROR 0x00000010 +#define PC_MTE 0x00800000 + +/* command config */ +#define CC_TE 0x00000001 +#define CC_RE 0x00000002 +#define CC_ES_MASK 0x0000000c +#define CC_ES_SHIFT 2 +#define CC_PROM 0x00000010 +#define CC_PAD_EN 0x00000020 +#define CC_CF 0x00000040 +#define CC_PF 0x00000080 +#define CC_RPI 0x00000100 +#define CC_TAI 0x00000200 +#define CC_HD 0x00000400 +#define CC_HD_SHIFT 10 +#define CC_SR 0x00002000 +#define CC_ML 0x00008000 +#define CC_AE 0x00400000 +#define CC_CFE 0x00800000 +#define CC_NLC 0x01000000 +#define CC_RL 0x02000000 +#define CC_RED 0x04000000 +#define CC_PE 0x08000000 +#define CC_TPI 0x10000000 +#define CC_AT 0x20000000 + +#define I_PDEE 0x00000400 +#define I_PDE 0x00000800 +#define I_DE 0x00001000 +#define I_RDU 0x00002000 +#define I_RFO 0x00004000 +#define I_XFU 0x00008000 +#define I_RI 0x00010000 +#define I_XI0 0x01000000 +#define I_XI1 0x02000000 +#define I_XI2 0x04000000 +#define I_XI3 0x08000000 +#define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU) +#define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS) + +#define I_INTMASK 0x0f01fcff + +#define CHIP_DRU_BASE 0x0301d000 +#define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc) +#define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194) + +#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0 +#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13 + +#define AMAC0_IDM_RESET_ADDR 0x18110800 +#define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408 +#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6 +#define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5 +#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3 + +#define CHIPA_CHIP_ID_ADDR 0x18000000 +#define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF) +#define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF) +#define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF) + +#define GMAC_MII_CTRL_ADDR 0x18002000 +#define GMAC_MII_CTRL_BYP_SHIFT 10 +#define GMAC_MII_CTRL_EXT_SHIFT 9 +#define GMAC_MII_DATA_ADDR 0x18002004 +#define GMAC_MII_DATA_READ_CMD 0x60020000 +#define GMAC_MII_DATA_WRITE_CMD 0x50020000 +#define GMAC_MII_BUSY_SHIFT 8 +#define GMAC_MII_PHY_ADDR_SHIFT 23 +#define GMAC_MII_PHY_REG_SHIFT 18 + +#define GMAC_RESET_DELAY 2 +#define HWRXOFF 30 +#define MAXNAMEL 8 +#define NUMTXQ 4 + +int gmac_add(struct eth_device *dev); + +#endif /* _BCM_SF2_ETH_GMAC_H_ */ diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c new file mode 100644 index 0000000000..5252d49de9 --- /dev/null +++ b/drivers/net/bcm-sf2-eth.c @@ -0,0 +1,268 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include "bcm-sf2-eth.h" + +#if defined(CONFIG_BCM_SF2_ETH_GMAC) +#include "bcm-sf2-eth-gmac.h" +#else +#error "bcm_sf2_eth: NEED to define a MAC!" +#endif + +#define BCM_NET_MODULE_DESCRIPTION "Broadcom Starfighter2 Ethernet driver" +#define BCM_NET_MODULE_VERSION "0.1" +#define BCM_SF2_ETH_DEV_NAME "bcm_sf2" + +static const char banner[] = + BCM_NET_MODULE_DESCRIPTION " " BCM_NET_MODULE_VERSION "\n"; + +static int bcm_sf2_eth_init(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + struct phy_device *phydev; + int rc = 0; + int i; + + rc = eth->mac_init(dev); + if (rc) { + error("%s: Couldn't cofigure MAC!\n", __func__); + return rc; + } + + /* disable DMA */ + dma->disable_dma(dma, MAC_DMA_RX); + dma->disable_dma(dma, MAC_DMA_TX); + + eth->port_num = 0; + debug("Connecting PHY 0...\n"); + phydev = phy_connect(miiphy_get_dev_by_name(dev->name), + 0, dev, eth->phy_interface); + if (phydev != NULL) { + eth->port[0] = phydev; + eth->port_num += 1; + } else { + debug("No PHY found for port 0\n"); + } + + for (i = 0; i < eth->port_num; i++) + phy_config(eth->port[i]); + + return rc; +} + +/* + * u-boot net functions + */ + +static int bcm_sf2_eth_send(struct eth_device *dev, void *packet, int length) +{ + struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma); + uint8_t *buf = (uint8_t *)packet; + int rc = 0; + int i = 0; + + debug("%s enter\n", __func__); + + /* load buf and start transmit */ + rc = dma->tx_packet(dma, buf, length); + if (rc) { + debug("ERROR - Tx failed\n"); + return rc; + } + + while (!(dma->check_tx_done(dma))) { + udelay(100); + debug("."); + i++; + if (i > 20) { + error("%s: Tx timeout: retried 20 times\n", __func__); + rc = -1; + break; + } + } + + debug("%s exit rc(0x%x)\n", __func__, rc); + return rc; +} + +static int bcm_sf2_eth_receive(struct eth_device *dev) +{ + struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma); + uint8_t *buf = (uint8_t *)NetRxPackets[0]; + int rcvlen; + int rc = 0; + int i = 0; + + while (1) { + /* Poll Rx queue to get a packet */ + rcvlen = dma->check_rx_done(dma, buf); + if (rcvlen < 0) { + /* No packet received */ + rc = -1; + debug("\nNO More Rx\n"); + break; + } else if ((rcvlen == 0) || (rcvlen > RX_BUF_SIZE)) { + error("%s: Wrong Ethernet packet size (%d B), skip!\n", + __func__, rcvlen); + break; + } else { + debug("recieved\n"); + + /* Forward received packet to uboot network handler */ + NetReceive(buf, rcvlen); + + if (++i >= PKTBUFSRX) + i = 0; + buf = NetRxPackets[i]; + } + } + + return rc; +} + +static int bcm_sf2_eth_write_hwaddr(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + + printf(" ETH MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->enetaddr[0], dev->enetaddr[1], dev->enetaddr[2], + dev->enetaddr[3], dev->enetaddr[4], dev->enetaddr[5]); + + return eth->set_mac_addr(dev->enetaddr); +} + +static int bcm_sf2_eth_open(struct eth_device *dev, bd_t *bt) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + int i; + + debug("Enabling BCM SF2 Ethernet.\n"); + + /* Set MAC address from env */ + if (bcm_sf2_eth_write_hwaddr(dev) != 0) { + error("%s: MAC set error when opening !\n", __func__); + return -1; + } + + eth->enable_mac(); + + /* enable tx and rx DMA */ + dma->enable_dma(dma, MAC_DMA_RX); + dma->enable_dma(dma, MAC_DMA_TX); + + /* + * Need to start PHY here because link speed can change + * before each ethernet operation + */ + for (i = 0; i < eth->port_num; i++) { + if (phy_startup(eth->port[i])) { + error("%s: PHY %d startup failed!\n", __func__, i); + if (i == CONFIG_BCM_SF2_ETH_DEFAULT_PORT) { + error("%s: No default port %d!\n", __func__, i); + return -1; + } + } + } + + /* Set MAC speed using default port */ + i = CONFIG_BCM_SF2_ETH_DEFAULT_PORT; + debug("PHY %d: speed:%d, duplex:%d, link:%d\n", i, + eth->port[i]->speed, eth->port[i]->duplex, eth->port[i]->link); + eth->set_mac_speed(eth->port[i]->speed, eth->port[i]->duplex); + + debug("Enable Ethernet Done.\n"); + + return 0; +} + +static void bcm_sf2_eth_close(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + + /* disable DMA */ + dma->disable_dma(dma, MAC_DMA_RX); + dma->disable_dma(dma, MAC_DMA_TX); + + eth->disable_mac(); +} + +int bcm_sf2_eth_register(bd_t *bis, u8 dev_num) +{ + struct eth_device *dev; + struct eth_info *eth; + int rc; + + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (dev == NULL) { + error("%s: Not enough memory!\n", __func__); + return -1; + } + + eth = (struct eth_info *)malloc(sizeof(struct eth_info)); + if (eth == NULL) { + error("%s: Not enough memory!\n", __func__); + return -1; + } + + printf(banner); + + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "%s_%s-%hu", BCM_SF2_ETH_DEV_NAME, + BCM_SF2_ETH_MAC_NAME, dev_num); + + dev->priv = (void *)eth; + dev->iobase = 0; + + dev->init = bcm_sf2_eth_open; + dev->halt = bcm_sf2_eth_close; + dev->send = bcm_sf2_eth_send; + dev->recv = bcm_sf2_eth_receive; + dev->write_hwaddr = bcm_sf2_eth_write_hwaddr; + +#ifdef CONFIG_BCM_SF2_ETH_GMAC + if (gmac_add(dev)) { + free(eth); + free(dev); + error("%s: Adding GMAC failed!\n", __func__); + return -1; + } +#else +#error "bcm_sf2_eth: NEED to register a MAC!" +#endif + + eth_register(dev); + +#ifdef CONFIG_CMD_MII + miiphy_register(dev->name, eth->miiphy_read, eth->miiphy_write); +#endif + + /* Initialization */ + debug("Ethernet initialization ..."); + + rc = bcm_sf2_eth_init(dev); + if (rc != 0) { + error("%s: configuration failed!\n", __func__); + return -1; + } + + printf("Basic ethernet functionality initialized\n"); + + return 0; +} diff --git a/drivers/net/bcm-sf2-eth.h b/drivers/net/bcm-sf2-eth.h new file mode 100644 index 0000000000..49a5836132 --- /dev/null +++ b/drivers/net/bcm-sf2-eth.h @@ -0,0 +1,70 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BCM_SF2_ETH_H_ +#define _BCM_SF2_ETH_H_ + +#include + +#define RX_BUF_SIZE 2048 +/* RX_BUF_NUM must be power of 2 */ +#define RX_BUF_NUM 32 + +#define TX_BUF_SIZE 2048 +/* TX_BUF_NUM must be power of 2 */ +#define TX_BUF_NUM 2 + +/* Support 2 Ethernet ports now */ +#define BCM_ETH_MAX_PORT_NUM 2 + +#define CONFIG_BCM_SF2_ETH_DEFAULT_PORT 0 + +enum { + MAC_DMA_TX = 1, + MAC_DMA_RX = 2 +}; + +struct eth_dma { + void *tx_desc_aligned; + void *rx_desc_aligned; + void *tx_desc; + void *rx_desc; + + uint8_t *tx_buf; + uint8_t *rx_buf; + + int cur_tx_index; + int cur_rx_index; + + int (*tx_packet)(struct eth_dma *dma, void *packet, int length); + bool (*check_tx_done)(struct eth_dma *dma); + + int (*check_rx_done)(struct eth_dma *dma, uint8_t *buf); + + int (*enable_dma)(struct eth_dma *dma, int dir); + int (*disable_dma)(struct eth_dma *dma, int dir); +}; + +struct eth_info { + struct eth_dma dma; + phy_interface_t phy_interface; + struct phy_device *port[BCM_ETH_MAX_PORT_NUM]; + int port_num; + + int (*miiphy_read)(const char *devname, unsigned char phyaddr, + unsigned char reg, unsigned short *value); + int (*miiphy_write)(const char *devname, unsigned char phyaddr, + unsigned char reg, unsigned short value); + + int (*mac_init)(struct eth_device *dev); + int (*enable_mac)(void); + int (*disable_mac)(void); + int (*set_mac_addr)(unsigned char *mac); + int (*set_mac_speed)(int speed, int duplex); + +}; + +#endif /* _BCM_SF2_ETH_H_ */ diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 0ffd59d497..0c2d2ef1a9 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -259,6 +260,8 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) *opmode = 0; bfin_write_EMAC_MMC_CTL(RSTC | CROLL); + bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL); + bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL); /* Initialize the TX DMA channel registers */ bfin_write_DMA2_X_COUNT(0); diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index 2c617105f5..ff94865c5d 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -390,7 +390,7 @@ static int xgmac_init(struct eth_device *dev, bd_t * bis) /* set flow control parameters and store and forward mode */ value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) | (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) | - XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF; + XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF; writel(value, ®s->core_opmode); /* enable pause frames */ diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 63f7ab4735..725108d0ea 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -63,8 +63,6 @@ #define DMASTATUS_IDLE BIT(31) -#define CPDMA_RAM_ADDR 0x4a102000 - /* Descriptor mode bits */ #define CPDMA_DESC_SOP BIT(31) #define CPDMA_DESC_EOP BIT(30) @@ -228,6 +226,8 @@ struct cpdma_chan { #define chan_read(chan, fld) __raw_readl((chan)->fld) #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) +#define for_active_slave(slave, priv) \ + slave = (priv)->slaves + (priv)->data.active_slave; if (slave) #define for_each_slave(slave, priv) \ for (slave = (priv)->slaves; slave != (priv)->slaves + \ (priv)->data->slaves; slave++) @@ -250,7 +250,6 @@ struct cpsw_priv { struct phy_device *phydev; struct mii_dev *bus; - u32 mdio_link; u32 phy_mask; }; @@ -505,7 +504,7 @@ static inline void wait_for_idle(void) static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, int dev_addr, int phy_reg) { - unsigned short data; + int data; u32 reg; if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) @@ -599,7 +598,7 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave, static void cpsw_slave_update_link(struct cpsw_slave *slave, struct cpsw_priv *priv, int *link) { - struct phy_device *phy = priv->phydev; + struct phy_device *phy; u32 mac_control = 0; int retries = NUM_TRIES; @@ -642,21 +641,10 @@ static int cpsw_update_link(struct cpsw_priv *priv) int link = 0; struct cpsw_slave *slave; - for_each_slave(slave, priv) + for_active_slave(slave, priv) cpsw_slave_update_link(slave, priv, &link); - priv->mdio_link = readl(&mdio_regs->link); - return link; -} - -static int cpsw_check_link(struct cpsw_priv *priv) -{ - u32 link; - - link = __raw_readl(&mdio_regs->link) & priv->phy_mask; - if (link && (link == priv->mdio_link)) - return 1; - return cpsw_update_link(priv); + return link; } static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) @@ -690,7 +678,7 @@ static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port); - priv->phy_mask |= 1 << slave->data->phy_id; + priv->phy_mask |= 1 << slave->data->phy_addr; } static void cpdma_desc_get(struct cpsw_desc *desc) @@ -839,6 +827,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis) /* enable statistics collection only on the host port */ __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); + __raw_writel(0x7, &priv->regs->stat_port_en); cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); @@ -846,7 +835,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis) ALE_SECURE); cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port); - for_each_slave(slave, priv) + for_active_slave(slave, priv) cpsw_slave_init(slave, priv); cpsw_update_link(priv); @@ -970,10 +959,6 @@ static int cpsw_send(struct eth_device *dev, void *packet, int length) void *buffer; int len; - if (!priv->data->mac_control && !cpsw_check_link(priv)) { - printf("%s: Cannot send packet; link is down\n", __func__); - return -EIO; - } /* first reap completed packets */ while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0) @@ -1019,11 +1004,7 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) { struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv; struct phy_device *phydev; - u32 supported = (SUPPORTED_10baseT_Half | - SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | - SUPPORTED_100baseT_Full | - SUPPORTED_1000baseT_Full); + u32 supported = PHY_GBIT_FEATURES; if (slave->data->phy_id < 0) { u32 phy_addr; @@ -1047,6 +1028,9 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) return -EINVAL; } + if (!phydev) + return -1; + phydev->supported &= supported; phydev->advertising = phydev->supported; @@ -1088,28 +1072,12 @@ int cpsw_register(struct cpsw_platform_data *data) return -ENOMEM; } - for (i = 0; i < NUM_DESCS; i++) { - priv->descs[i].dma_desc = memalign(CONFIG_SYS_CACHELINE_SIZE, - sizeof(struct cpsw_desc) * NUM_DESCS); - if (!priv->descs[i].dma_desc) { - while (--i >= 0) { - free(priv->descs[i].dma_desc); - } - free(priv->slaves); - free(priv); - free(dev); - return -ENOMEM; - } - debug("DMA desc[%d] allocated @ %p desc_size %u\n", - i, priv->descs[i].dma_desc, - sizeof(*priv->descs[i].dma_desc)); - } - priv->host_port = data->host_port_num; priv->regs = regs; priv->host_port_regs = regs + data->host_port_reg_ofs; priv->dma_regs = regs + data->cpdma_reg_ofs; priv->ale_regs = regs + data->ale_reg_ofs; + priv->descs = (void *)regs + data->bd_ram_ofs; for_each_slave(slave, priv) { cpsw_slave_setup(slave, idx, priv); @@ -1128,7 +1096,7 @@ int cpsw_register(struct cpsw_platform_data *data) cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div); priv->bus = miiphy_get_dev_by_name(dev->name); - for_each_slave(slave, priv) { + for_active_slave(slave, priv) { ret = cpsw_phy_init(dev, slave); if (ret < 0) break; diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 439f8ae99e..08bc1afcf6 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 994ebf2fc9..799839c4f1 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -1,5 +1,5 @@ /* - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 8413d57767..c03e935e2f 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -17,7 +17,75 @@ #include #include "designware.h" -static int configure_phy(struct eth_device *dev); +#if !defined(CONFIG_PHYLIB) +# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + return readl(&mac_p->miidata); + udelay(10); + }; + + return -1; +} + +static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -1; + } + + bus->read = dw_mdio_read; + bus->write = dw_mdio_write; + sprintf(bus->name, name); + + bus->priv = (void *)mac_regs_p; + + return mdio_register(bus); +} static void tx_descs_init(struct eth_device *dev) { @@ -51,7 +119,13 @@ static void tx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->tx_mac_descrtable, + (unsigned int)priv->tx_mac_descrtable + + sizeof(priv->tx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + priv->tx_currdescnum = 0; } static void rx_descs_init(struct eth_device *dev) @@ -63,6 +137,15 @@ static void rx_descs_init(struct eth_device *dev) struct dmamacdescr *desc_p; u32 idx; + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; @@ -78,56 +161,68 @@ static void rx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Rx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->rx_mac_descrtable, + (unsigned int)priv->rx_mac_descrtable + + sizeof(priv->rx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); + priv->rx_currdescnum = 0; } -static void descs_init(struct eth_device *dev) +static int dw_write_hwaddr(struct eth_device *dev) { - tx_descs_init(dev); - rx_descs_init(dev); + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; } -static int mac_reset(struct eth_device *dev) +static void dw_adjust_link(struct eth_mac_regs *mac_p, + struct phy_device *phydev) { - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; - ulong start; - int timeout = CONFIG_MACRESET_TIMEOUT; + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } - writel(DMAMAC_SRST, &dma_p->busmode); + if (phydev->speed != 1000) + conf |= MII_PORTSELECT; - if (priv->interface != PHY_INTERFACE_MODE_RGMII) - writel(MII_PORTSELECT, &mac_p->conf); + if (phydev->speed == 100) + conf |= FES_100; - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) - return 0; + if (phydev->duplex) + conf |= FULLDPLXMODE; - /* Try again after 10usec */ - udelay(10); - }; + writel(conf, &mac_p->conf); - return -1; + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); } -static int dw_write_hwaddr(struct eth_device *dev) +static void dw_eth_halt(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; - u32 macid_lo, macid_hi; - u8 *mac_id = &dev->enetaddr[0]; - - macid_lo = mac_id[0] + (mac_id[1] << 8) + \ - (mac_id[2] << 16) + (mac_id[3] << 24); - macid_hi = mac_id[4] + (mac_id[5] << 8); + struct eth_dma_regs *dma_p = priv->dma_regs_p; - writel(macid_hi, &mac_p->macaddr0hi); - writel(macid_lo, &mac_p->macaddr0lo); + writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); + writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); - return 0; + phy_shutdown(priv->phydev); } static int dw_eth_init(struct eth_device *dev, bd_t *bis) @@ -135,55 +230,45 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; - u32 conf; + unsigned int start; - if (priv->phy_configured != 1) - configure_phy(dev); + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); - /* Print link status only once */ - if (!priv->link_printed) { - printf("ENET Speed is %d Mbps - %s duplex connection\n", - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); - priv->link_printed = 1; - } + start = get_timer(0); + while (readl(&dma_p->busmode) & DMAMAC_SRST) { + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { + printf("DMA reset timeout\n"); + return -1; + } - /* Reset ethernet hardware */ - if (mac_reset(dev) < 0) - return -1; + mdelay(100); + }; - /* Resore the HW MAC address as it has been lost during MAC reset */ + /* Soft reset above clears HW address registers. + * So we have to set it here once again */ dw_write_hwaddr(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, - &dma_p->busmode); - - writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | - TXSECONDFRAME, &dma_p->opmode); + rx_descs_init(dev); + tx_descs_init(dev); - conf = FRAMEBURSTENABLE | DISABLERXOWN; + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); - if (priv->speed != 1000) - conf |= MII_PORTSELECT; + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, + &dma_p->opmode); - if ((priv->interface != PHY_INTERFACE_MODE_MII) && - (priv->interface != PHY_INTERFACE_MODE_GMII)) { + writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); - if (priv->speed == 100) - conf |= FES_100; + /* Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; } - if (priv->duplex == FULL) - conf |= FULLDPLXMODE; - - writel(conf, &mac_p->conf); - - descs_init(dev); + dw_adjust_link(mac_p, priv->phydev); - /* - * Start/Enable xfer at dma as well as mac level - */ - writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); - writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + if (!priv->phydev->link) + return -1; writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); @@ -196,6 +281,21 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) struct eth_dma_regs *dma_p = priv->dma_regs_p; u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end = data_start + + roundup(length, ARCH_DMA_MINALIGN); + /* + * Strictly we only need to invalidate the "txrx_status" field + * for the following check, but on some platforms we cannot + * invalidate only 4 bytes, so we flush the entire descriptor, + * which is 16 bytes in total. This is safe because the + * individual descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN and padded appropriately. + */ + invalidate_dcache_range(desc_start, desc_end); /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { @@ -203,7 +303,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) return -1; } - memcpy((void *)desc_p->dmamac_addr, packet, length); + memcpy(desc_p->dmamac_addr, packet, length); + + /* Flush data to be sent */ + flush_dcache_range(data_start, data_end); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; @@ -220,6 +323,9 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; #endif + /* Flush modified buffer descriptor */ + flush_dcache_range(desc_start, desc_end); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_TX_DESCR_NUM) desc_num = 0; @@ -235,11 +341,19 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) static int dw_eth_recv(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - u32 desc_num = priv->rx_currdescnum; + u32 status, desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; - - u32 status = desc_p->txrx_status; int length = 0; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end; + + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range(desc_start, desc_end); + + status = desc_p->txrx_status; /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { @@ -247,6 +361,10 @@ static int dw_eth_recv(struct eth_device *dev) length = (status & DESC_RXSTS_FRMLENMSK) >> \ DESC_RXSTS_FRMLENSHFT; + /* Invalidate received data */ + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start, data_end); + NetReceive(desc_p->dmamac_addr, length); /* @@ -255,6 +373,9 @@ static int dw_eth_recv(struct eth_device *dev) */ desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + /* Flush only status field - others weren't changed */ + flush_dcache_range(desc_start, desc_end); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) desc_num = 0; @@ -265,251 +386,32 @@ static int dw_eth_recv(struct eth_device *dev) return length; } -static void dw_eth_halt(struct eth_device *dev) +static int dw_phy_init(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; + struct phy_device *phydev; + int mask = 0xffffffff; - mac_reset(dev); - priv->tx_currdescnum = priv->rx_currdescnum = 0; -} - -static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) -{ - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int timeout = CONFIG_MDIO_TIMEOUT; - - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK); - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - *val = readl(&mac_p->miidata); - return 0; - } - - /* Try again after 10usec */ - udelay(10); - }; - - return -1; -} - -static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) -{ - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; - u16 value; - - writel(val, &mac_p->miidata); - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - ret = 0; - break; - } - - /* Try again after 10usec */ - udelay(10); - }; - - /* Needed as a fix for ST-Phy */ - eth_mdio_read(dev, addr, reg, &value); - - return ret; -} - -#if defined(CONFIG_DW_SEARCH_PHY) -static int find_phy(struct eth_device *dev) -{ - int phy_addr = 0; - u16 ctrl, oldctrl; - - do { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - oldctrl = ctrl & BMCR_ANENABLE; - - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - ctrl &= BMCR_ANENABLE; - - if (ctrl == oldctrl) { - phy_addr++; - } else { - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - - return phy_addr; - } - } while (phy_addr < 32); - - return -1; -} -#endif - -static int dw_reset_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - u16 ctrl; - ulong start; - int timeout = CONFIG_PHYRESET_TIMEOUT; - u32 phy_addr = priv->address; - - eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); - - start = get_timer(0); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - if (!(ctrl & BMCR_RESET)) - break; - - /* Try again after 10usec */ - udelay(10); - }; - - if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT) - return -1; - -#ifdef CONFIG_PHY_RESET_DELAY - udelay(CONFIG_PHY_RESET_DELAY); +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; #endif - return 0; -} - -/* - * Add weak default function for board specific PHY configuration - */ -int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) -{ - return 0; -} -static int configure_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - int phy_addr; - u16 bmcr; -#if defined(CONFIG_DW_AUTONEG) - u16 bmsr; - u32 timeout; - ulong start; -#endif - -#if defined(CONFIG_DW_SEARCH_PHY) - phy_addr = find_phy(dev); - if (phy_addr >= 0) - priv->address = phy_addr; - else + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) return -1; -#else - phy_addr = priv->address; -#endif - - /* - * Some boards need board specific PHY initialization. This is - * after the main driver init code but before the auto negotiation - * is run. - */ - if (designware_board_phy_init(dev, phy_addr, - eth_mdio_write, dw_reset_phy) < 0) - return -1; - - if (dw_reset_phy(dev) < 0) - return -1; - -#if defined(CONFIG_DW_AUTONEG) - /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */ - eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1); - - bmcr = BMCR_ANENABLE | BMCR_ANRESTART; -#else - bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; - -#if defined(CONFIG_DW_SPEED10M) - bmcr &= ~BMCR_SPEED100; -#endif -#if defined(CONFIG_DW_DUPLEXHALF) - bmcr &= ~BMCR_FULLDPLX; -#endif -#endif - if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) - return -1; - - /* Read the phy status register and populate priv structure */ -#if defined(CONFIG_DW_AUTONEG) - timeout = CONFIG_AUTONEG_TIMEOUT; - start = get_timer(0); - puts("Waiting for PHY auto negotiation to complete"); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); - if (bmsr & BMSR_ANEGCOMPLETE) { - priv->phy_configured = 1; - break; - } - - /* Print dot all 1s to show progress */ - if ((get_timer(start) % 1000) == 0) - putc('.'); - - /* Try again after 1msec */ - udelay(1000); - }; - - if (!(bmsr & BMSR_ANEGCOMPLETE)) - puts(" TIMEOUT!\n"); - else - puts(" done\n"); -#else - priv->phy_configured = 1; -#endif - - priv->speed = miiphy_speed(dev->name, phy_addr); - priv->duplex = miiphy_duplex(dev->name, phy_addr); - return 0; -} + phy_connect_dev(phydev, dev); -#if defined(CONFIG_MII) -static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) -{ - struct eth_device *dev; + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_read(dev, addr, reg, val); + priv->phydev = phydev; + phy_config(phydev); - return 0; -} - -static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_write(dev, addr, reg, val); - - return 0; + return 1; } -#endif -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) +int designware_initialize(ulong base_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv; @@ -522,7 +424,8 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) * Since the priv structure contains the descriptors which need a strict * buswidth alignment, memalign is used to allocate memory */ - priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, + sizeof(struct dw_eth_dev)); if (!priv) { free(dev); return -ENOMEM; @@ -531,19 +434,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) memset(dev, 0, sizeof(struct eth_device)); memset(priv, 0, sizeof(struct dw_eth_dev)); - sprintf(dev->name, "mii%d", id); + sprintf(dev->name, "dwmac.%lx", base_addr); dev->iobase = (int)base_addr; dev->priv = priv; - eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); - priv->dev = dev; priv->mac_regs_p = (struct eth_mac_regs *)base_addr; priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + DW_DMA_BASE_OFFSET); - priv->address = phy_addr; - priv->phy_configured = 0; - priv->interface = interface; dev->init = dw_eth_init; dev->send = dw_eth_send; @@ -553,8 +451,10 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) eth_register(dev); -#if defined(CONFIG_MII) - miiphy_register(dev->name, dw_mii_read, dw_mii_write); -#endif - return 1; + priv->interface = interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return dw_phy_init(dev); } diff --git a/drivers/net/designware.h b/drivers/net/designware.h index e80002a0e4..ce51102052 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -16,8 +16,6 @@ #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) struct eth_mac_regs { u32 conf; /* 0x00 */ @@ -79,18 +77,18 @@ struct eth_dma_regs { #define DW_DMA_BASE_OFFSET (0x1000) +/* Default DMA Burst length */ +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 +#endif + /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) #define PRIORXTX_41 (3 << 14) #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) -#define BURST_1 (1 << 8) -#define BURST_2 (2 << 8) -#define BURST_4 (4 << 8) -#define BURST_8 (8 << 8) -#define BURST_16 (16 << 8) -#define BURST_32 (32 << 8) +#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0) @@ -112,7 +110,7 @@ struct dmamacdescr { u32 dmamac_cntl; void *dmamac_addr; struct dmamacdescr *dmamac_next; -}; +} __aligned(ARCH_DMA_MINALIGN); /* * txrx_status definitions @@ -217,35 +215,21 @@ struct dmamacdescr { #endif struct dw_eth_dev { - u32 address; - u32 interface; - u32 speed; - u32 duplex; - u32 tx_currdescnum; - u32 rx_currdescnum; - u32 phy_configured; - int link_printed; - u32 padding; - struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); - char txbuffs[TX_TOTAL_BUFSIZE]; - char rxbuffs[RX_TOTAL_BUFSIZE]; + u32 interface; + u32 tx_currdescnum; + u32 rx_currdescnum; struct eth_mac_regs *mac_regs_p; struct eth_dma_regs *dma_regs_p; struct eth_device *dev; -} __attribute__ ((aligned(8))); - -/* Speed specific definitions */ -#define SPEED_10M 1 -#define SPEED_100M 2 -#define SPEED_1000M 3 - -/* Duplex mode specific definitions */ -#define HALF_DUPLEX 1 -#define FULL_DUPLEX 2 + struct phy_device *phydev; + struct mii_dev *bus; +}; #endif diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index ffb8ea01dc..4de9d41642 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -17,7 +17,7 @@ V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match R17 = (R17 & 0xfff0) | NF v1.00 modify by simon 2001.9.5 - change for kernel 2.4.x + change for kernel 2.4.x v1.1 11/09/2001 fix force mode bug @@ -342,6 +342,15 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); printf("MAC: %pM\n", dev->enetaddr); + if (!is_valid_ether_addr(dev->enetaddr)) { +#ifdef CONFIG_RANDOM_MACADDR + printf("Bad MAC address (uninitialized EEPROM?), randomizing\n"); + eth_random_addr(dev->enetaddr); + printf("MAC: %pM\n", dev->enetaddr); +#else + printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n"); +#endif + } /* fill device MAC address registers */ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 57aa53dbae..cd4422215f 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -41,12 +41,12 @@ tested on both gig copper and gig fiber boards /* NIC specific static variables go here */ -static char tx_pool[128 + 16]; -static char rx_pool[128 + 16]; -static char packet[2096]; +/* Intel i210 needs the DMA descriptor rings aligned to 128b */ +#define E1000_BUFFER_ALIGN 128 -static struct e1000_tx_desc *tx_base; -static struct e1000_rx_desc *rx_base; +DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); +DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); +DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); static int tx_tail; static int rx_tail, rx_last; @@ -92,6 +92,15 @@ static struct pci_device_id e1000_supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX}, + {} }; @@ -114,12 +123,13 @@ static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); static int e1000_phy_reset(struct e1000_hw *hw); static int e1000_detect_gig_phy(struct e1000_hw *hw); -static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); static void e1000_set_media_type(struct e1000_hw *hw); static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); +#ifndef CONFIG_E1000_NO_NVM +static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); @@ -339,7 +349,7 @@ int32_t e1000_acquire_eeprom(struct e1000_hw *hw) return -E1000_ERR_SWFW_SYNC; eecd = E1000_READ_REG(hw, EECD); - if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) { + if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { /* Request EEPROM Access */ if (hw->mac_type > e1000_82544) { eecd |= E1000_EECD_REQ; @@ -390,10 +400,15 @@ int32_t e1000_acquire_eeprom(struct e1000_hw *hw) static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd = E1000_READ_REG(hw, EECD); + uint32_t eecd; int32_t ret_val = E1000_SUCCESS; uint16_t eeprom_size; + if (hw->mac_type == e1000_igb) + eecd = E1000_READ_REG(hw, I210_EECD); + else + eecd = E1000_READ_REG(hw, EECD); + DEBUGFUNC(); switch (hw->mac_type) { @@ -484,9 +499,10 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = true; - eeprom->use_eewr = true; if (e1000_is_onboard_nvm_eeprom(hw) == false) { + eeprom->use_eerd = true; + eeprom->use_eewr = true; + eeprom->type = e1000_eeprom_flash; eeprom->word_size = 2048; @@ -510,6 +526,16 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->use_eerd = true; eeprom->use_eewr = false; break; + case e1000_igb: + /* i210 has 4k of iNVM mapped as EEPROM */ + eeprom->type = e1000_eeprom_invm; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + eeprom->page_size = 32; + eeprom->address_bits = 16; + eeprom->use_eerd = true; + eeprom->use_eewr = false; + break; /* ich8lan does not support currently. if needed, please * add corresponding code and functions. @@ -551,7 +577,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) break; } - if (eeprom->type == e1000_eeprom_spi) { + if (eeprom->type == e1000_eeprom_spi || + eeprom->type == e1000_eeprom_invm) { /* eeprom_size will be an enum [0..8] that maps * to eeprom sizes 128B to * 32KB (incremented by powers of 2). @@ -595,10 +622,17 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) int32_t done = E1000_ERR_EEPROM; for (i = 0; i < attempts; i++) { - if (eerd == E1000_EEPROM_POLL_READ) - reg = E1000_READ_REG(hw, EERD); - else - reg = E1000_READ_REG(hw, EEWR); + if (eerd == E1000_EEPROM_POLL_READ) { + if (hw->mac_type == e1000_igb) + reg = E1000_READ_REG(hw, I210_EERD); + else + reg = E1000_READ_REG(hw, EERD); + } else { + if (hw->mac_type == e1000_igb) + reg = E1000_READ_REG(hw, I210_EEWR); + else + reg = E1000_READ_REG(hw, EEWR); + } if (reg & E1000_EEPROM_RW_REG_DONE) { done = E1000_SUCCESS; @@ -631,13 +665,23 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw, eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + E1000_EEPROM_RW_REG_START; - E1000_WRITE_REG(hw, EERD, eerd); + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_EERD, eerd); + else + E1000_WRITE_REG(hw, EERD, eerd); + error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); if (error) break; - data[i] = (E1000_READ_REG(hw, EERD) >> + + if (hw->mac_type == e1000_igb) { + data[i] = (E1000_READ_REG(hw, I210_EERD) >> E1000_EEPROM_RW_REG_DATA); + } else { + data[i] = (E1000_READ_REG(hw, EERD) >> + E1000_EEPROM_RW_REG_DATA); + } } @@ -885,6 +929,7 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) return -E1000_ERR_EEPROM; } +#endif /* CONFIG_E1000_NO_NVM */ /***************************************************************************** * Set PHY to class A mode @@ -897,6 +942,7 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) static int32_t e1000_set_phy_mode(struct e1000_hw *hw) { +#ifndef CONFIG_E1000_NO_NVM int32_t ret_val; uint16_t eeprom_data; @@ -923,10 +969,11 @@ e1000_set_phy_mode(struct e1000_hw *hw) hw->phy_reset_disable = false; } } - +#endif return E1000_SUCCESS; } +#ifndef CONFIG_E1000_NO_NVM /*************************************************************************** * * Obtaining software semaphore bit (SMBI) before resetting PHY. @@ -945,6 +992,10 @@ e1000_get_software_semaphore(struct e1000_hw *hw) DEBUGFUNC(); + swsm = E1000_READ_REG(hw, SWSM); + swsm &= ~E1000_SWSM_SMBI; + E1000_WRITE_REG(hw, SWSM, swsm); + if (hw->mac_type != e1000_80003es2lan) return E1000_SUCCESS; @@ -965,6 +1016,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw) return E1000_SUCCESS; } +#endif /*************************************************************************** * This function clears HW semaphore bits. @@ -977,6 +1029,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw) static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) { +#ifndef CONFIG_E1000_NO_NVM uint32_t swsm; DEBUGFUNC(); @@ -991,6 +1044,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) } else swsm &= ~(E1000_SWSM_SWESMBI); E1000_WRITE_REG(hw, SWSM, swsm); +#endif } /*************************************************************************** @@ -1007,6 +1061,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) { +#ifndef CONFIG_E1000_NO_NVM int32_t timeout; uint32_t swsm; @@ -1043,7 +1098,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) "SWESMBI bit is set.\n"); return -E1000_ERR_EEPROM; } - +#endif return E1000_SUCCESS; } @@ -1060,7 +1115,10 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) if (e1000_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; - swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); + if (hw->mac_type == e1000_igb) + swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC); + else + swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); if (!(swfw_sync & (fwmask | swmask))) break; @@ -1097,6 +1155,7 @@ static bool e1000_is_second_port(struct e1000_hw *hw) } } +#ifndef CONFIG_E1000_NO_NVM /****************************************************************************** * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the * second function of dual function devices @@ -1109,13 +1168,23 @@ e1000_read_mac_addr(struct eth_device *nic) struct e1000_hw *hw = nic->priv; uint16_t offset; uint16_t eeprom_data; + uint32_t reg_data = 0; int i; DEBUGFUNC(); for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { offset = i >> 1; - if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { + if (hw->mac_type == e1000_igb) { + /* i210 preloads MAC address into RAL/RAH registers */ + if (offset == 0) + reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); + else if (offset == 1) + reg_data >>= 16; + else if (offset == 2) + reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); + eeprom_data = reg_data & 0xffff; + } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } @@ -1136,6 +1205,7 @@ e1000_read_mac_addr(struct eth_device *nic) #endif return 0; } +#endif /****************************************************************************** * Initializes receive address filters. @@ -1310,6 +1380,16 @@ e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_ICH8_IGP_M: hw->mac_type = e1000_ich8lan; break; + case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: + case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: + case PCI_DEVICE_ID_INTEL_I210_COPPER: + case PCI_DEVICE_ID_INTEL_I211_COPPER: + case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: + case PCI_DEVICE_ID_INTEL_I210_SERDES: + case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: + case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: + hw->mac_type = e1000_igb; + break; default: /* Should never have loaded on this device */ return -E1000_ERR_MAC_TYPE; @@ -1329,6 +1409,7 @@ e1000_reset_hw(struct e1000_hw *hw) uint32_t ctrl_ext; uint32_t manc; uint32_t pba = 0; + uint32_t reg; DEBUGFUNC(); @@ -1347,6 +1428,8 @@ e1000_reset_hw(struct e1000_hw *hw) /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_IAM, 0); E1000_WRITE_REG(hw, IMC, 0xffffffff); /* Disable the Transmit and Receive units. Then delay to allow @@ -1376,7 +1459,15 @@ e1000_reset_hw(struct e1000_hw *hw) E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); /* Force a reload from the EEPROM if necessary */ - if (hw->mac_type < e1000_82540) { + if (hw->mac_type == e1000_igb) { + mdelay(20); + reg = E1000_READ_REG(hw, STATUS); + if (reg & E1000_STATUS_PF_RST_DONE) + DEBUGOUT("PF OK\n"); + reg = E1000_READ_REG(hw, I210_EECD); + if (reg & E1000_EECD_AUTO_RD) + DEBUGOUT("EEC OK\n"); + } else if (hw->mac_type < e1000_82540) { /* Wait for reset to complete */ udelay(10); ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); @@ -1396,6 +1487,8 @@ e1000_reset_hw(struct e1000_hw *hw) /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_IAM, 0); E1000_WRITE_REG(hw, IMC, 0xffffffff); /* Clear any pending interrupt events. */ @@ -1405,7 +1498,8 @@ e1000_reset_hw(struct e1000_hw *hw) if (hw->mac_type == e1000_82542_rev2_0) { pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); } - E1000_WRITE_REG(hw, PBA, pba); + if (hw->mac_type != e1000_igb) + E1000_WRITE_REG(hw, PBA, pba); } /****************************************************************************** @@ -1441,6 +1535,10 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); + /* IGB is cool */ + if (hw->mac_type == e1000_igb) + return; + switch (hw->mac_type) { case e1000_82571: case e1000_82572: @@ -1631,6 +1729,7 @@ e1000_init_hw(struct eth_device *nic) switch (hw->mac_type) { case e1000_82545_rev_3: case e1000_82546_rev_3: + case e1000_igb: break; default: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ @@ -1660,6 +1759,8 @@ e1000_init_hw(struct eth_device *nic) /* More time needed for PHY to initialize */ if (hw->mac_type == e1000_ich8lan) mdelay(15); + if (hw->mac_type == e1000_igb) + mdelay(15); /* Call a subroutine to configure the link and setup flow control. */ ret_val = e1000_setup_link(nic); @@ -1674,7 +1775,6 @@ e1000_init_hw(struct eth_device *nic) } /* Set the receive descriptor write back policy */ - if (hw->mac_type >= e1000_82571) { ctrl = E1000_READ_REG(hw, RXDCTL); ctrl = @@ -1721,6 +1821,8 @@ e1000_init_hw(struct eth_device *nic) reg_data = E1000_READ_REG(hw, GCR); reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; E1000_WRITE_REG(hw, GCR, reg_data); + case e1000_igb: + break; } #if 0 @@ -1764,9 +1866,11 @@ static int e1000_setup_link(struct eth_device *nic) { struct e1000_hw *hw = nic->priv; - uint32_t ctrl_ext; int32_t ret_val; +#ifndef CONFIG_E1000_NO_NVM + uint32_t ctrl_ext; uint16_t eeprom_data; +#endif DEBUGFUNC(); @@ -1775,6 +1879,7 @@ e1000_setup_link(struct eth_device *nic) if (e1000_check_phy_reset_block(hw)) return E1000_SUCCESS; +#ifndef CONFIG_E1000_NO_NVM /* Read and store word 0x0F of the EEPROM. This word contains bits * that determine the hardware's default PAUSE (flow control) mode, * a bit that determines whether the HW defaults to enabling or @@ -1788,15 +1893,17 @@ e1000_setup_link(struct eth_device *nic) DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } - +#endif if (hw->fc == e1000_fc_default) { switch (hw->mac_type) { case e1000_ich8lan: case e1000_82573: case e1000_82574: + case e1000_igb: hw->fc = e1000_fc_full; break; default: +#ifndef CONFIG_E1000_NO_NVM ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); if (ret_val) { @@ -1809,6 +1916,7 @@ e1000_setup_link(struct eth_device *nic) EEPROM_WORD0F_ASM_DIR) hw->fc = e1000_fc_tx_pause; else +#endif hw->fc = e1000_fc_full; break; } @@ -1828,6 +1936,7 @@ e1000_setup_link(struct eth_device *nic) DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); +#ifndef CONFIG_E1000_NO_NVM /* Take the 4 bits from EEPROM word 0x0F that determine the initial * polarity value for the SW controlled pins, and setup the * Extended Device Control reg with that info. @@ -1840,6 +1949,7 @@ e1000_setup_link(struct eth_device *nic) SWDPIO__EXT_SHIFT); E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); } +#endif /* Call the necessary subroutine to configure the link. */ ret_val = (hw->media_type == e1000_media_type_fiber) ? @@ -2250,6 +2360,8 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) if (hw->mac_type == e1000_ich8lan) { phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); } else { ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); @@ -2261,6 +2373,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) if (hw->mac_type == e1000_ich8lan) { phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); } else { phy_data &= ~IGP02E1000_PM_D0_LPLU; ret_val = e1000_write_phy_reg(hw, @@ -2269,6 +2384,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) return ret_val; } + if (hw->mac_type == e1000_igb) + return E1000_SUCCESS; + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during * Dx states where the power conservation is most important. During * driver activity we should enable SmartSpeed, so performance is @@ -2303,6 +2421,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) if (hw->mac_type == e1000_ich8lan) { phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); } else { phy_data |= IGP02E1000_PM_D0_LPLU; ret_val = e1000_write_phy_reg(hw, @@ -2311,6 +2432,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) return ret_val; } + if (hw->mac_type == e1000_igb) + return E1000_SUCCESS; + /* When LPLU is enabled we should disable SmartSpeed */ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); @@ -2532,8 +2656,10 @@ e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) if (e1000_is_second_port(hw)) swfw = E1000_SWFW_PHY1_SM; - if (e1000_swfw_sync_acquire(hw, swfw)) + if (e1000_swfw_sync_acquire(hw, swfw)) { + debug("%s[%i]\n", __func__, __LINE__); return -E1000_ERR_SWFW_SYNC; + } /* Write register address */ reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & @@ -2968,7 +3094,8 @@ e1000_setup_copper_link(struct eth_device *nic) ret_val = e1000_copper_link_igp_setup(hw); if (ret_val) return ret_val; - } else if (hw->phy_type == e1000_phy_m88) { + } else if (hw->phy_type == e1000_phy_m88 || + hw->phy_type == e1000_phy_igb) { ret_val = e1000_copper_link_mgp_setup(hw); if (ret_val) return ret_val; @@ -3212,7 +3339,8 @@ e1000_config_mac_to_phy(struct e1000_hw *hw) */ ctrl = E1000_READ_REG(hw, CTRL); ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); - ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); + ctrl &= ~(E1000_CTRL_ILOS); + ctrl |= (E1000_CTRL_SPD_SEL); /* Set up duplex in the Device Control and Transmit Control * registers depending on negotiated values. @@ -4238,11 +4366,16 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) case e1000_82571: case e1000_82572: + case e1000_igb: while (timeout) { - if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) - break; - else - mdelay(1); + if (hw->mac_type == e1000_igb) { + if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) + break; + } else { + if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) + break; + } + mdelay(1); timeout--; } if (!timeout) { @@ -4305,7 +4438,6 @@ e1000_phy_hw_reset(struct e1000_hw *hw) if (hw->mac_type >= e1000_82571) mdelay(10); - } else { /* Read the Extended Device Control Register, assert the PHY_RESET_DIR * bit to put the PHY into reset. Then, take it out of reset. @@ -4471,6 +4603,7 @@ e1000_phy_reset(struct e1000_hw *hw) case e1000_phy_igp_2: case e1000_phy_igp_3: case e1000_phy_ife: + case e1000_phy_igb: ret_val = e1000_phy_hw_reset(hw); if (ret_val) return ret_val; @@ -4515,7 +4648,6 @@ static int e1000_set_phy_type (struct e1000_hw *hw) hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) { hw->phy_type = e1000_phy_igp; - hw->phy_type = e1000_phy_igp; break; } case IGP03E1000_E_PHY_ID: @@ -4534,6 +4666,9 @@ static int e1000_set_phy_type (struct e1000_hw *hw) case BME1000_E_PHY_ID: hw->phy_type = e1000_phy_bm; break; + case I210_I_PHY_ID: + hw->phy_type = e1000_phy_igb; + break; /* Fall Through */ default: /* Should never have loaded on this device */ @@ -4638,6 +4773,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw) if (hw->phy_id == IFE_C_E_PHY_ID) match = true; break; + case e1000_igb: + if (hw->phy_id == I210_I_PHY_ID) + match = true; + break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); return -E1000_ERR_CONFIG; @@ -4689,6 +4828,7 @@ e1000_set_media_type(struct e1000_hw *hw) case e1000_ich8lan: case e1000_82573: case e1000_82574: + case e1000_igb: /* The STATUS_TBIMODE bit is reserved or reused * for the this device. */ @@ -4757,6 +4897,7 @@ e1000_sw_init(struct eth_device *nic) hw->fc_send_xon = 1; /* Media type - copper or fiber */ + hw->tbi_compatibility_en = true; e1000_set_media_type(hw); if (hw->mac_type >= e1000_82543) { @@ -4773,7 +4914,6 @@ e1000_sw_init(struct eth_device *nic) hw->media_type = e1000_media_type_fiber; } - hw->tbi_compatibility_en = true; hw->wait_autoneg_complete = true; if (hw->mac_type < e1000_82543) hw->report_tx_early = 0; @@ -4787,12 +4927,26 @@ void fill_rx(struct e1000_hw *hw) { struct e1000_rx_desc *rd; + unsigned long flush_start, flush_end; rx_last = rx_tail; rd = rx_base + rx_tail; rx_tail = (rx_tail + 1) % 8; memset(rd, 0, 16); - rd->buffer_addr = cpu_to_le64((u32) & packet); + rd->buffer_addr = cpu_to_le64((unsigned long)packet); + + /* + * Make sure there are no stale data in WB over this area, which + * might get written into the memory while the e1000 also writes + * into the same memory area. + */ + invalidate_dcache_range((unsigned long)packet, + (unsigned long)packet + 4096); + /* Dump the DMA descriptor into RAM. */ + flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); + flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); + flush_dcache_range(flush_start, flush_end); + E1000_WRITE_REG(hw, RDT, rx_tail); } @@ -4806,18 +4960,11 @@ fill_rx(struct e1000_hw *hw) static void e1000_configure_tx(struct e1000_hw *hw) { - unsigned long ptr; unsigned long tctl; unsigned long tipg, tarc; uint32_t ipgr1, ipgr2; - ptr = (u32) tx_pool; - if (ptr & 0xf) - ptr = (ptr + 0x10) & (~0xf); - - tx_base = (typeof(tx_base)) ptr; - - E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); + E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base); E1000_WRITE_REG(hw, TDBAH, 0); E1000_WRITE_REG(hw, TDLEN, 128); @@ -4885,7 +5032,22 @@ e1000_configure_tx(struct e1000_hw *hw) hw->txd_cmd |= E1000_TXD_CMD_RPS; else hw->txd_cmd |= E1000_TXD_CMD_RS; + + + if (hw->mac_type == e1000_igb) { + E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); + + uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); + reg_txdctl |= 1 << 25; + E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); + mdelay(20); + } + + + E1000_WRITE_REG(hw, TCTL, tctl); + + } /** @@ -4925,7 +5087,6 @@ e1000_setup_rctl(struct e1000_hw *hw) static void e1000_configure_rx(struct e1000_hw *hw) { - unsigned long ptr; unsigned long rctl, ctrl_ext; rx_tail = 0; /* make sure receives are disabled while setting up the descriptors */ @@ -4947,11 +5108,7 @@ e1000_configure_rx(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); } /* Setup the Base and Length of the Rx Descriptor Ring */ - ptr = (u32) rx_pool; - if (ptr & 0xf) - ptr = (ptr + 0x10) & (~0xf); - rx_base = (typeof(rx_base)) ptr; - E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); + E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base); E1000_WRITE_REG(hw, RDBAH, 0); E1000_WRITE_REG(hw, RDLEN, 128); @@ -4961,7 +5118,16 @@ e1000_configure_rx(struct e1000_hw *hw) E1000_WRITE_REG(hw, RDT, 0); /* Enable Receives */ + if (hw->mac_type == e1000_igb) { + + uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); + reg_rxdctl |= 1 << 25; + E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); + mdelay(20); + } + E1000_WRITE_REG(hw, RCTL, rctl); + fill_rx(hw); } @@ -4973,12 +5139,26 @@ e1000_poll(struct eth_device *nic) { struct e1000_hw *hw = nic->priv; struct e1000_rx_desc *rd; + unsigned long inval_start, inval_end; + uint32_t len; + /* return true if there's an ethernet packet ready to read */ rd = rx_base + rx_last; + + /* Re-load the descriptor from RAM. */ + inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); + inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); + invalidate_dcache_range(inval_start, inval_end); + if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) return 0; /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ - NetReceive((uchar *)packet, le32_to_cpu(rd->length)); + /* Packet received, make sure the data are re-loaded from RAM. */ + len = le32_to_cpu(rd->length); + invalidate_dcache_range((unsigned long)packet, + (unsigned long)packet + + roundup(len, ARCH_DMA_MINALIGN)); + NetReceive((uchar *)packet, len); fill_rx(hw); return 1; } @@ -4986,12 +5166,13 @@ e1000_poll(struct eth_device *nic) /************************************************************************** TRANSMIT - Transmit a frame ***************************************************************************/ -static int e1000_transmit(struct eth_device *nic, void *packet, int length) +static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) { - void *nv_packet = (void *)packet; + void *nv_packet = (void *)txpacket; struct e1000_hw *hw = nic->priv; struct e1000_tx_desc *txp; int i = 0; + unsigned long flush_start, flush_end; txp = tx_base + tx_tail; tx_tail = (tx_tail + 1) % 8; @@ -4999,10 +5180,23 @@ static int e1000_transmit(struct eth_device *nic, void *packet, int length) txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); txp->lower.data = cpu_to_le32(hw->txd_cmd | length); txp->upper.data = 0; + + /* Dump the packet into RAM so e1000 can pick them. */ + flush_dcache_range((unsigned long)nv_packet, + (unsigned long)nv_packet + + roundup(length, ARCH_DMA_MINALIGN)); + /* Dump the descriptor into RAM as well. */ + flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); + flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); + flush_dcache_range(flush_start, flush_end); + E1000_WRITE_REG(hw, TDT, tx_tail); E1000_WRITE_FLUSH(hw); - while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { + while (1) { + invalidate_dcache_range(flush_start, flush_end); + if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) + break; if (i++ > TOUT_LOOP) { DEBUGOUT("e1000: tx timeout\n"); return 0; @@ -5097,9 +5291,8 @@ void e1000_get_bus_type(struct e1000_hw *hw) case e1000_82573: case e1000_82574: case e1000_80003es2lan: - hw->bus_type = e1000_bus_type_pci_express; - break; case e1000_ich8lan: + case e1000_igb: hw->bus_type = e1000_bus_type_pci_express; break; default: @@ -5180,6 +5373,9 @@ e1000_initialize(bd_t * bis) hw->autoneg_failed = 0; hw->autoneg = 1; hw->get_link_status = true; +#ifndef CONFIG_E1000_NO_NVM + hw->eeprom_semaphore_present = true; +#endif hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); hw->mac_type = e1000_undefined; @@ -5196,21 +5392,29 @@ e1000_initialize(bd_t * bis) e1000_reset_hw(hw); list_add_tail(&hw->list_node, &e1000_hw_list); +#ifndef CONFIG_E1000_NO_NVM /* Validate the EEPROM and get chipset information */ #if !defined(CONFIG_MVBC_1G) if (e1000_init_eeprom_params(hw)) { E1000_ERR(nic, "EEPROM is invalid!\n"); continue; } - if (e1000_validate_eeprom_checksum(hw)) + if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && + e1000_validate_eeprom_checksum(hw)) continue; #endif e1000_read_mac_addr(nic); +#endif e1000_get_bus_type(hw); +#ifndef CONFIG_E1000_NO_NVM printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); +#else + memset(nic->enetaddr, 0, 6); + printf("e1000: no NVM\n"); +#endif /* Set up the function pointers and register the device */ nic->init = e1000_init; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 25884f5bc5..6d110eb5d5 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -63,11 +63,14 @@ struct e1000_hw_stats; /* Internal E1000 helper functions */ struct e1000_hw *e1000_find_card(unsigned int cardnum); + +#ifndef CONFIG_E1000_NO_NVM int32_t e1000_acquire_eeprom(struct e1000_hw *hw); void e1000_standby_eeprom(struct e1000_hw *hw); void e1000_release_eeprom(struct e1000_hw *hw); void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); +#endif #ifdef CONFIG_E1000_SPI int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, @@ -97,6 +100,7 @@ typedef enum { e1000_82574, e1000_80003es2lan, e1000_ich8lan, + e1000_igb, e1000_num_macs } e1000_mac_type; @@ -115,6 +119,7 @@ typedef enum { e1000_eeprom_flash, e1000_eeprom_ich8, e1000_eeprom_none, /* No NVM support */ + e1000_eeprom_invm, e1000_num_eeprom_types } e1000_eeprom_type; @@ -209,6 +214,7 @@ typedef enum { e1000_phy_gg82563, e1000_phy_igp_3, e1000_phy_ife, + e1000_phy_igb, e1000_phy_bm, e1000_phy_undefined = 0xFF } e1000_phy_type; @@ -683,7 +689,9 @@ struct e1000_ffvt_entry { #define E1000_CTRL 0x00000 /* Device Control - RW */ #define E1000_STATUS 0x00008 /* Device Status - RO */ #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +#define E1000_I210_EECD 0x12010 /* EEPROM/Flash Control - RW */ #define E1000_EERD 0x00014 /* EEPROM Read - RW */ +#define E1000_I210_EERD 0x12014 /* EEPROM Read - RW */ #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ #define E1000_MDIC 0x00020 /* MDI Control - RW */ #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ @@ -695,6 +703,7 @@ struct e1000_ffvt_entry { #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +#define E1000_I210_IAM 0x000E0 /* Interrupt Ack Auto Mask - RW */ #define E1000_RCTL 0x00100 /* RX Control - RW */ #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ @@ -708,14 +717,17 @@ struct e1000_ffvt_entry { #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ +#define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */ #define FEXTNVM_SW_CONFIG 0x0001 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ #define E1000_PBS 0x01008 /* Packet Buffer Size */ #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ +#define E1000_I210_EEMNGCTL 0x12030 /* MNG EEprom Control */ #define E1000_FLASH_UPDATES 1000 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ +#define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */ #define E1000_FLSWCTL 0x01030 /* FLASH control register */ #define E1000_FLSWDATA 0x01034 /* FLASH data register */ #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ @@ -1019,6 +1031,7 @@ struct e1000_hw_stats { uint64_t tsctfc; }; +#ifndef CONFIG_E1000_NO_NVM struct e1000_eeprom_info { e1000_eeprom_type type; uint16_t word_size; @@ -1029,6 +1042,7 @@ e1000_eeprom_type type; bool use_eerd; bool use_eewr; }; +#endif typedef enum { e1000_smart_speed_default = 0, @@ -1081,10 +1095,14 @@ struct e1000_hw { uint32_t io_base; #endif uint32_t asf_firmware_present; +#ifndef CONFIG_E1000_NO_NVM uint32_t eeprom_semaphore_present; +#endif uint32_t swfw_sync_present; uint32_t swfwhw_semaphore_present; +#ifndef CONFIG_E1000_NO_NVM struct e1000_eeprom_info eeprom; +#endif e1000_ms_type master_slave; e1000_ms_type original_master_slave; e1000_ffe_config ffe_config_state; @@ -1213,6 +1231,7 @@ struct e1000_hw { #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ +#define E1000_STATUS_PF_RST_DONE 0x00200000 /* PCI-X bus speed */ /* Constants used to intrepret the masked PCI-X bus speed. */ #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ @@ -2429,6 +2448,8 @@ struct e1000_hw { #define BME1000_E_PHY_ID 0x01410CB0 +#define I210_I_PHY_ID 0x01410C00 + /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF #define PHY_SOF 0x01 @@ -2476,6 +2497,7 @@ struct e1000_hw { #define ICH_GFPREG_BASE_MASK 0x1FFF #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF +#define E1000_I210_SW_FW_SYNC 0x5B50 /* Software-Firmware Synchronization - RW */ #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ /* SPI EEPROM Status Register */ diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 1e4ea0c892..a23a5852ee 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -230,7 +230,7 @@ static int eepro100_send(struct eth_device *dev, void *packet, int length); static int eepro100_recv (struct eth_device *dev); static void eepro100_halt (struct eth_device *dev); -#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) +#if defined(CONFIG_E500) #define bus_to_phys(a) (a) #define phys_to_bus(a) (a) #else diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index af06d4fb82..46c82bbb40 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -189,12 +189,12 @@ struct ethoc_bd { u32 addr; }; -static inline u32 ethoc_read(struct eth_device *dev, loff_t offset) +static inline u32 ethoc_read(struct eth_device *dev, size_t offset) { return readl(dev->iobase + offset); } -static inline void ethoc_write(struct eth_device *dev, loff_t offset, u32 data) +static inline void ethoc_write(struct eth_device *dev, size_t offset, u32 data) { writel(data, dev->iobase + offset); } @@ -202,7 +202,7 @@ static inline void ethoc_write(struct eth_device *dev, loff_t offset, u32 data) static inline void ethoc_read_bd(struct eth_device *dev, int index, struct ethoc_bd *bd) { - loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); bd->stat = ethoc_read(dev, offset + 0); bd->addr = ethoc_read(dev, offset + 4); } @@ -210,7 +210,7 @@ static inline void ethoc_read_bd(struct eth_device *dev, int index, static inline void ethoc_write_bd(struct eth_device *dev, int index, const struct ethoc_bd *bd) { - loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); ethoc_write(dev, offset + 0, bd->stat); ethoc_write(dev, offset + 4, bd->addr); } diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 720813687b..7e732d4df4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -30,6 +31,14 @@ DECLARE_GLOBAL_DATA_PTR; */ #define FEC_XFER_TIMEOUT 5000 +/* + * The standard 32-byte DMA alignment does not work on mx6solox, which requires + * 64-byte alignment in the DMA RX FEC buffer. + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also + * satisfies the alignment on other SoCs (32-bytes) + */ +#define FEC_DMA_RX_MINALIGN 64 + #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif @@ -42,7 +51,7 @@ DECLARE_GLOBAL_DATA_PTR; * The i.MX28 operates with packets in big endian. We need to swap them before * sending and after receiving. */ -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 #define CONFIG_FEC_MXC_SWAP_PACKET #endif @@ -134,8 +143,12 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, - ð->mii_speed); + register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); +#ifdef FEC_QUIRK_ENET_MAC + speed--; +#endif + speed <<= 1; + writel(speed, ð->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } @@ -175,13 +188,14 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, return 0; } -int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) +static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, + int regAddr) { return fec_mdio_read(bus->priv, phyAddr, regAddr); } -int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, - u16 data) +static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, + int regAddr, u16 data) { return fec_mdio_write(bus->priv, phyAddr, regAddr, data); } @@ -198,7 +212,7 @@ static int miiphy_restart_aneg(struct eth_device *dev) * Wake up from sleep if necessary * Reset PHY, then delay 300ns */ -#ifdef CONFIG_MX27 +#ifdef CONFIG_SOC_MX27 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); #endif fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); @@ -274,49 +288,34 @@ static inline void fec_tx_task_disable(struct fec_priv *fec) * @param[in] dsize desired size of each receive buffer * @return 0 on success * - * For this task we need additional memory for the data buffers. And each - * data buffer requires some alignment. Thy must be aligned to a specific - * boundary each. + * Init all RX descriptors to default values. */ -static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) +static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) { uint32_t size; + uint8_t *data; int i; /* - * Allocate memory for the buffers. This allocation respects the - * alignment + * Reload the RX descriptors with default values and wipe + * the RX buffers. */ size = roundup(dsize, ARCH_DMA_MINALIGN); for (i = 0; i < count; i++) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - if (data_ptr == 0) { - uint8_t *data = memalign(ARCH_DMA_MINALIGN, - size); - if (!data) { - printf("%s: error allocating rxbuf %d\n", - __func__, i); - goto err; - } - writel((uint32_t)data, &fec->rbd_base[i].data_pointer); - } /* needs allocation */ - writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); - writew(0, &fec->rbd_base[i].data_length); + data = (uint8_t *)fec->rbd_base[i].data_pointer; + memset(data, 0, dsize); + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; } /* Mark the last RBD to close the ring. */ - writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; fec->rbd_index = 0; - return 0; - -err: - for (; i >= 0; i--) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - free((void *)data_ptr); - } - - return -ENOMEM; + flush_dcache_range((unsigned)fec->rbd_base, + (unsigned)fec->rbd_base + size); } /** @@ -336,8 +335,10 @@ static void fec_tbd_init(struct fec_priv *fec) unsigned addr = (unsigned)fec->tbd_base; unsigned size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); - writew(0x0000, &fec->tbd_base[0].status); - writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); + + memset(fec->tbd_base, 0, size); + fec->tbd_base[0].status = 0; + fec->tbd_base[1].status = FEC_TBD_WRAP; fec->tbd_index = 0; flush_dcache_range(addr, addr + size); } @@ -457,7 +458,7 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6SL) udelay(100); /* * setup the MII gasket for RMII mode @@ -516,7 +517,7 @@ static int fec_open(struct eth_device *edev) writel(ecr, &fec->eth->ecntrl); writel(rcr, &fec->eth->r_cntrl); } -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) { u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; @@ -540,51 +541,18 @@ static int fec_init(struct eth_device *dev, bd_t* bd) { struct fec_priv *fec = dev->priv; uint32_t *mib_ptr = (uint32_t *)&fec->eth->rmon_t_drop; - uint32_t size; - int i, ret; + int i; /* Initialize MAC address */ fec_set_hwaddr(dev); /* - * Allocate transmit descriptors, there are two in total. This - * allocation respects cache alignment. + * Setup transmit descriptors, there are two in total. */ - if (!fec->tbd_base) { - size = roundup(2 * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->tbd_base) { - ret = -ENOMEM; - goto err1; - } - memset(fec->tbd_base, 0, size); - fec_tbd_init(fec); - } + fec_tbd_init(fec); - /* - * Allocate receive descriptors. This allocation respects cache - * alignment. - */ - if (!fec->rbd_base) { - size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->rbd_base) { - ret = -ENOMEM; - goto err2; - } - memset(fec->rbd_base, 0, size); - /* - * Initialize RxBD ring - */ - if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { - ret = -ENOMEM; - goto err3; - } - flush_dcache_range((unsigned)fec->rbd_base, - (unsigned)fec->rbd_base + size); - } + /* Setup receive descriptors. */ + fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); fec_reg_setup(fec); @@ -621,13 +589,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd) #endif fec_open(dev); return 0; - -err3: - free(fec->rbd_base); -err2: - free(fec->tbd_base); -err1: - return ret; } /** @@ -774,13 +735,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length) break; } - if (!timeout) + if (!timeout) { ret = -EINVAL; + goto out; + } - invalidate_dcache_range(addr, addr + size); - if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) + /* + * The TDAR bit is cleared when the descriptors are all out from TX + * but on mx6solox we noticed that the READY bit is still not cleared + * right after TDAR. + * These are two distinct signals, and in IC simulation, we found that + * TDAR always gets cleared prior than the READY bit of last BD becomes + * cleared. + * In mx6solox, we use a later version of FEC IP. It looks like that + * this intrinsic behaviour of TDAR bit has changed in this newer FEC + * version. + * + * Fix this by polling the READY bit of BD after the TDAR polling, + * which covers the mx6solox case and does not harm the other SoCs. + */ + timeout = FEC_XFER_TIMEOUT; + while (--timeout) { + invalidate_dcache_range(addr, addr + size); + if (!(readw(&fec->tbd_base[fec->tbd_index].status) & + FEC_TBD_READY)) + break; + } + + if (!timeout) ret = -EINVAL; +out: debug("fec_send: status 0x%x index %d ret %i\n", readw(&fec->tbd_base[fec->tbd_index].status), fec->tbd_index, ret); @@ -925,6 +910,74 @@ static void fec_set_dev_name(char *dest, int dev_id) sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); } +static int fec_alloc_descs(struct fec_priv *fec) +{ + unsigned int size; + int i; + uint8_t *data; + + /* Allocate TX descriptors. */ + size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->tbd_base) + goto err_tx; + + /* Allocate RX descriptors. */ + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->rbd_base) + goto err_rx; + + memset(fec->rbd_base, 0, size); + + /* Allocate RX buffers. */ + + /* Maximum RX buffer size. */ + size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); + for (i = 0; i < FEC_RBD_NUM; i++) { + data = memalign(FEC_DMA_RX_MINALIGN, size); + if (!data) { + printf("%s: error allocating rxbuf %d\n", __func__, i); + goto err_ring; + } + + memset(data, 0, size); + + fec->rbd_base[i].data_pointer = (uint32_t)data; + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; + /* Flush the buffer to memory. */ + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + } + + /* Mark the last RBD to close the ring. */ + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; + + fec->rbd_index = 0; + fec->tbd_index = 0; + + return 0; + +err_ring: + for (; i >= 0; i--) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); +err_rx: + free(fec->tbd_base); +err_tx: + return -ENOMEM; +} + +static void fec_free_descs(struct fec_priv *fec) +{ + int i; + + for (i = 0; i < FEC_RBD_NUM; i++) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); + free(fec->tbd_base); +} + #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, struct mii_dev *bus, struct phy_device *phydev) @@ -954,6 +1007,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, goto err2; } + ret = fec_alloc_descs(fec); + if (ret) + goto err3; + edev->priv = fec; edev->init = fec_init; edev->send = fec_send; @@ -972,7 +1029,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("FEC MXC: Timeout reseting chip\n"); - goto err3; + goto err4; } udelay(10); } @@ -998,8 +1055,12 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, else debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); + if (!getenv("ethaddr")) + eth_setenv_enetaddr("ethaddr", ethaddr); } return ret; +err4: + fec_free_descs(fec); err3: free(fec); err2: @@ -1043,7 +1104,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) #endif int ret; -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 /* * The i.MX28 has two ethernet interfaces, but they are not equal. * Only the first one can access the MDIO bus. diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 7cfef86c7b..66b81cc7d5 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -133,7 +133,7 @@ struct ethernet_regs { uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6SL) uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ @@ -200,7 +200,7 @@ struct ethernet_regs { #define FEC_X_DES_ACTIVE_TDAR 0x01000000 #define FEC_R_DES_ACTIVE_RDAR 0x01000000 -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) +#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6SL) /* defines for MIIGSK */ /* RMII frequency control: 0=50MHz, 1=5MHz */ #define MIIGSK_CFGR_FRCONT (1 << 6) diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 4edd849268..d052fcb372 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -4,50 +4,36 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libfm.o - -ifdef CONFIG_FMAN_ENET -COBJS-y += dtsec.o -COBJS-y += eth.o -COBJS-y += fm.o -COBJS-y += init.o -COBJS-y += tgec.o -COBJS-y += tgec_phy.o +obj-y += dtsec.o +obj-y += eth.o +obj-y += fm.o +obj-y += init.o +obj-y += tgec.o +obj-y += tgec_phy.o # Soc have FMAN v3 with mEMAC -COBJS-$(CONFIG_SYS_FMAN_V3) += memac_phy.o -COBJS-$(CONFIG_SYS_FMAN_V3) += memac.o +obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o +obj-$(CONFIG_SYS_FMAN_V3) += memac.o # SoC specific SERDES support -COBJS-$(CONFIG_P1017) += p1023.o -COBJS-$(CONFIG_P1023) += p1023.o +obj-$(CONFIG_P1017) += p1023.o +obj-$(CONFIG_P1023) += p1023.o # The P204x, P304x, and P5020 are the same -COBJS-$(CONFIG_PPC_P2041) += p5020.o -COBJS-$(CONFIG_PPC_P3041) += p5020.o -COBJS-$(CONFIG_PPC_P4080) += p4080.o -COBJS-$(CONFIG_PPC_P5020) += p5020.o -COBJS-$(CONFIG_PPC_P5040) += p5040.o -COBJS-$(CONFIG_PPC_T4240) += t4240.o -COBJS-$(CONFIG_PPC_T4160) += t4240.o -COBJS-$(CONFIG_PPC_B4420) += b4860.o -COBJS-$(CONFIG_PPC_B4860) += b4860.o -endif - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_PPC_P2041) += p5020.o +obj-$(CONFIG_PPC_P3041) += p5020.o +obj-$(CONFIG_PPC_P4080) += p4080.o +obj-$(CONFIG_PPC_P5020) += p5020.o +obj-$(CONFIG_PPC_P5040) += p5040.o +obj-$(CONFIG_PPC_T1040) += t1040.o +obj-$(CONFIG_PPC_T1042) += t1040.o +obj-$(CONFIG_PPC_T1020) += t1040.o +obj-$(CONFIG_PPC_T1022) += t1040.o +obj-$(CONFIG_PPC_T1023) += t1024.o +obj-$(CONFIG_PPC_T1024) += t1024.o +obj-$(CONFIG_PPC_T2080) += t2080.o +obj-$(CONFIG_PPC_T2081) += t2080.o +obj-$(CONFIG_PPC_T4240) += t4240.o +obj-$(CONFIG_PPC_T4160) += t4240.o +obj-$(CONFIG_PPC_T4080) += t4240.o +obj-$(CONFIG_PPC_B4420) += b4860.o +obj-$(CONFIG_PPC_B4860) += b4860.o diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 9b3d5324e0..eb058c9c3d 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -10,6 +10,7 @@ #include #include #include +#include u32 port_to_devdisr[] = { [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, @@ -37,17 +38,85 @@ void fman_disable_port(enum fm_port port) setbits_be32(&gur->devdisr2, port_to_devdisr[port]); } +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { +#if defined(CONFIG_B4860QDS) + u32 serdes2_prtcl; + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; /*B4860 has two 10Gig Mac*/ if ((port == FM1_10GEC1 || port == FM1_10GEC2) && ((is_serdes_configured(XAUI_FM1_MAC9)) || - (is_serdes_configured(XAUI_FM1_MAC10)))) + #if !defined(CONFIG_B4860QDS) + (is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)) || + #endif + (is_serdes_configured(XAUI_FM1_MAC10)) + )) return PHY_INTERFACE_MODE_XGMII; +#if defined(CONFIG_B4860QDS) + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + if (serdes2_prtcl) { + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + switch (serdes2_prtcl) { + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0xb1: + case 0xb2: + /* + * Extract hwconfig from environment since environment + * is not setup yet + */ + getenv_f("hwconfig", buffer, sizeof(buffer)); + buf = buffer; + + /* check if XFI interface enable in hwconfig for 10g */ + if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", + "sfp_amc", "sfp", buf)) { + if ((port == FM1_10GEC1 || + port == FM1_10GEC2) && + ((is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + else if ((port == FM1_DTSEC1) || + (port == FM1_DTSEC2) || + (port == FM1_DTSEC3) || + (port == FM1_DTSEC4)) + return PHY_INTERFACE_MODE_NONE; + } + } + } +#endif + /* Fix me need to handle RGMII here first */ switch (port) { diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c index 78bbd439f1..8d3dc0e308 100644 --- a/drivers/net/fm/dtsec.c +++ b/drivers/net/fm/dtsec.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 422c2c691e..1d1089d017 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -39,9 +39,14 @@ static void dtsec_configure_serdes(struct fm_eth *priv) u32 value; struct mii_dev bus; bus.priv = priv->mac->phyregs; + bool sgmii_2500 = (priv->enet_if == + PHY_INTERFACE_MODE_SGMII_2500) ? true : false; + + /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ + value = PHY_SGMII_IF_MODE_SGMII; + if (!sgmii_2500) + value |= PHY_SGMII_IF_MODE_AN; - /* SGMII IF mode + AN enable */ - value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII; memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value); /* Dev ability according to SGMII specification */ @@ -54,7 +59,9 @@ static void dtsec_configure_serdes(struct fm_eth *priv) memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40); /* Restart AN */ - value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN; + value = PHY_SGMII_CR_DEF_VAL; + if (!sgmii_2500) + value |= PHY_SGMII_CR_RESET_AN; memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value); #else struct dtsec *regs = priv->mac->base; @@ -83,7 +90,8 @@ static void dtsec_init_phy(struct eth_device *dev) out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); #endif - if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) + if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || + fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) dtsec_configure_serdes(fm_eth); } @@ -341,7 +349,9 @@ static int fm_eth_startup(struct fm_eth *fm_eth) mac->init_mac(mac); /* For some reason we need to set SPEED_100 */ - if ((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) && mac->set_if_mode) + if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) || + (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) && + mac->set_if_mode) mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); /* init bmi rx port, IM mode and disable */ @@ -400,10 +410,15 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd) fmc_tx_port_graceful_stop_disable(fm_eth); #ifdef CONFIG_PHYLIB - ret = phy_startup(fm_eth->phydev); - if (ret) { - printf("%s: Could not initialize\n", fm_eth->phydev->dev->name); - return ret; + if (fm_eth->phydev) { + ret = phy_startup(fm_eth->phydev); + if (ret) { + printf("%s: Could not initialize\n", + fm_eth->phydev->dev->name); + return ret; + } + } else { + return 0; } #else fm_eth->phydev->speed = SPEED_1000; @@ -437,7 +452,8 @@ static void fm_eth_halt(struct eth_device *dev) /* disable bmi Rx port */ bmi_rx_port_disable(fm_eth->rx_port); - phy_shutdown(fm_eth->phydev); + if (fm_eth->phydev) + phy_shutdown(fm_eth->phydev); } static int fm_eth_send(struct eth_device *dev, void *buf, int len) @@ -555,8 +571,19 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) num = fm_eth->num; #ifdef CONFIG_SYS_FMAN_V3 - if (fm_eth->type == FM_ETH_10G_E) - num += 8; +#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION + if (fm_eth->type == FM_ETH_10G_E) { + /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240. + * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080. + * 10GEC1 uses mEMAC1 on T1024. + * so it needs to change the num. + */ + if (fm_eth->num >= 2) + num -= 2; + else + num += 8; + } +#endif base = ®->memac[num].fm_memac; phyregs = ®->memac[num].fm_memac_mdio; #else @@ -604,11 +631,12 @@ static int init_phy(struct eth_device *dev) if (fm_eth->bus) { phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev, fm_eth->enet_if); - } - - if (!phydev) { - printf("Failed to connect\n"); - return -1; + if (!phydev) { + printf("Failed to connect\n"); + return -1; + } + } else { + return 0; } if (fm_eth->type == FM_ETH_1G_E) { @@ -690,8 +718,7 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) if (!fm_eth_startup(fm_eth)) return 0; - if (init_phy(dev)) - return 0; + init_phy(dev); /* clear the ethernet address */ for (i = 0; i < 6; i++) diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 4bc8f35a1c..400e9dd5e2 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -350,16 +350,16 @@ int fm_init_common(int index, struct ccsr_fman *reg) { int rc; #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND) size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR, + rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR, &fw_length, (u_char *)addr); if (rc == -EUCLEAN) { printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", - CONFIG_SYS_QE_FMAN_FW_ADDR, rc); + CONFIG_SYS_FMAN_FW_ADDR, rc); } #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) struct spi_flash *ucode_flash; @@ -371,7 +371,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) if (!ucode_flash) printf("SF: probe for ucode failed\n"); else { - ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR, + ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR, CONFIG_SYS_QE_FMAN_FW_LENGTH, addr); if (ret) printf("SF: read for ucode failed\n"); @@ -381,7 +381,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) int dev = CONFIG_SYS_MMC_ENV_DEV; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; - u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) @@ -395,7 +395,9 @@ int fm_init_common(int index, struct ccsr_fman *reg) flush_cache((ulong)addr, cnt * 512); } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; +#else + void *addr = NULL; #endif /* Upload the Fman microcode if it's present */ diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index 38fdbcdc42..a9691c635a 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -8,8 +8,8 @@ #define __FM_H__ #include +#include #include -#include #include /* Port ID */ @@ -18,9 +18,12 @@ #define RX_PORT_1G_BASE 0x08 #define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC #define RX_PORT_10G_BASE 0x10 +#define RX_PORT_10G_BASE2 0x08 #define TX_PORT_1G_BASE 0x28 #define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC #define TX_PORT_10G_BASE 0x30 +#define TX_PORT_10G_BASE2 0x28 +#define MIIM_TIMEOUT 0xFFFF struct fm_muram { u32 base; @@ -98,6 +101,7 @@ int fm_init_common(int index, struct ccsr_fman *reg); int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info); phy_interface_t fman_port_enet_if(enum fm_port port); void fman_disable_port(enum fm_port port); +void fman_enable_port(enum fm_port port); struct fsl_enet_mac { void *base; /* MAC controller registers base address */ @@ -139,6 +143,7 @@ struct fm_eth { #define MAX_RXBUF_LOG2 11 #define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2) -#define PORT_IS_ENABLED(port) fm_info[fm_port_to_index(port)].enabled +#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \ + 0 : fm_info[fm_port_to_index(port)].enabled) #endif /* __FM_H__ */ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 14fa2ce59c..9a8a007861 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "fm.h" @@ -64,6 +65,12 @@ struct fm_eth_info fm_info[] = { #if (CONFIG_SYS_NUM_FM1_10GEC >= 2) FM_TGEC_INFO_INITIALIZER(1, 2), #endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) + FM_TGEC_INFO_INITIALIZER2(1, 3), +#endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 4) + FM_TGEC_INFO_INITIALIZER2(1, 4), +#endif #if (CONFIG_SYS_NUM_FM2_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(2, 1), #endif @@ -141,10 +148,24 @@ void fm_disable_port(enum fm_port port) { int i = fm_port_to_index(port); + if (i == -1) + return; + fm_info[i].enabled = 0; fman_disable_port(port); } +void fm_enable_port(enum fm_port port) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return; + + fm_info[i].enabled = 1; + fman_enable_port(port); +} + void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus) { int i = fm_port_to_index(port); @@ -226,21 +247,38 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) } #ifdef CONFIG_SYS_FMAN_V3 +#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION /* - * Physically FM1_DTSEC9 and FM1_10GEC1 use the same dual-role MAC, when - * FM1_10GEC1 is enabled and FM1_DTSEC9 is disabled, ensure that the - * dual-role MAC is not disabled, ditto for other dual-role MACs. + * On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same + * dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9 + * is disabled, ensure that the dual-role MAC is not disabled, + * ditto for other dual-role MACs. */ - if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || - ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || - ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || - ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) + if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || + ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || + ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) || + ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) || + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || + ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || + ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || + ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2))) #if (CONFIG_SYS_NUM_FMAN == 2) || ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) || ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) || ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) || ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10))) +#endif +#else + /* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */ + if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) || + ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) || + ((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) || + ((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) || + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) || + ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) || + ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) || + ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4))) #endif ) return; @@ -274,3 +312,47 @@ void fdt_fixup_fman_ethernet(void *blob) } #endif } + +/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different. + *This function scans which Riser Card being used(QSGMII or SGMII Riser Card), + *then set the correct PHY address + */ +void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port, + unsigned int port_num, int phy_base_addr) +{ + unsigned int regnum = 0; + int qsgmii; + int i; + int phy_real_addr; + + qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum); + + if (!qsgmii) + return; + + for (i = base_port; i < base_port + port_num; i++) { + if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) { + phy_real_addr = phy_base_addr + i - base_port; + fm_info_set_phy_address(i, phy_real_addr); + } + } +} + +/*to check whether qsgmii riser card is used*/ +int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr, + unsigned int port_num, unsigned regnum) +{ + int i; + int val; + + if (!bus) + return 0; + + for (i = phy_base_addr; i < phy_base_addr + port_num; i++) { + val = bus->read(bus, i, MDIO_DEVAD_NONE, regnum); + if (val != MIIM_TIMEOUT) + return 1; + } + + return 0; +} diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 144e109fd0..60e898cd7c 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include "fm.h" @@ -38,7 +37,8 @@ static void memac_enable_mac(struct fsl_enet_mac *mac) { struct memac *regs = mac->base; - setbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); + setbits_be32(®s->command_config, + MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK); } static void memac_disable_mac(struct fsl_enet_mac *mac) @@ -90,14 +90,20 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode |= (IF_MODE_GMII | IF_MODE_RM); break; case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); break; + case PHY_INTERFACE_MODE_XGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= IF_MODE_XGMII; + break; default: break; } - /* Enable automatic speed selection */ - if_mode |= IF_MODE_EN_AUTO; + /* Enable automatic speed selection for Non-XGMII */ + if (type != PHY_INTERFACE_MODE_XGMII) + if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII) { if_mode &= ~IF_MODE_EN_AUTO; diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 140e59b75c..a155d8930b 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -1,6 +1,6 @@ /* * Copyright 2012 Freescale Semiconductor, Inc. - * Andy Fleming + * Andy Fleming * Roy Zang * * SPDX-License-Identifier: GPL-2.0+ @@ -29,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) @@ -73,13 +71,13 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, u32 c45 = 1; if (dev_addr == MDIO_DEVAD_NONE) { + if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME)) + return 0xffff; c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) @@ -133,5 +131,20 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) bus->priv = info->regs; + /* + * On some platforms like B4860, default value of MDIO_CLK_DIV bits + * in mdio_stat(mdio_cfg) register generates MDIO clock too high + * (much higher than 2.5MHz), violating the IEEE specs. + * On other platforms like T1040, default value of MDIO_CLK_DIV bits + * is zero, so MDIO clock is disabled. + * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to + * be properly initialized. + * NEG bit default should be '1' as per FMAN-v3 RM, but on platform + * like T2080QDS, this bit default is '0', which leads to MDIO failure + * on XAUI PHY, so set this bit definitely. + */ + setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, + MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG); + return mdio_register(bus); } diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index 0eaad0f45d..b25d10ae0f 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -34,6 +34,13 @@ void fman_disable_port(enum fm_port port) setbits_be32(&gur->devdisr, port_to_devdisr[port]); } +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index febfdd4e87..de71911355 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -42,6 +42,13 @@ void fman_disable_port(enum fm_port port) setbits_be32(&gur->devdisr2, port_to_devdisr[port]); } +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index 8d49c7bc1f..5c158cd5df 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -38,6 +38,13 @@ void fman_disable_port(enum fm_port port) setbits_be32(&gur->devdisr2, port_to_devdisr[port]); } +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c index 546ebce567..403d7d7948 100644 --- a/drivers/net/fm/p5040.c +++ b/drivers/net/fm/p5040.c @@ -44,6 +44,13 @@ void fman_disable_port(enum fm_port port) setbits_be32(&gur->devdisr2, port_to_devdisr[port]); } +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c new file mode 100644 index 0000000000..9b3117341e --- /dev/null +++ b/drivers/net/fm/t1024.c @@ -0,0 +1,88 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */ +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_RGMII) && + (!is_serdes_configured(QSGMII_FM1_A))) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_RGMII) && + (!is_serdes_configured(QSGMII_FM1_A))) + return PHY_INTERFACE_MODE_RGMII; + + /* handle SGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 + + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII_2500; + break; + default: + break; + } + + /* handle QSGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + /* check lane A on SerDes1 */ + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c new file mode 100644 index 0000000000..04583661ec --- /dev/null +++ b/drivers/net/fm/t1040.c @@ -0,0 +1,67 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + /* handle RGMII first */ + if ((port == FM1_DTSEC2) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + } + + if ((port == FM1_DTSEC4) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + } + + if (port == FM1_DTSEC5) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) + return PHY_INTERFACE_MODE_MII; + } + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || + is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_QSGMII; + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c new file mode 100644 index 0000000000..3b6212f858 --- /dev/null +++ b/drivers/net/fm/t2080.c @@ -0,0 +1,93 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, + [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3, + [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1 || port == FM1_10GEC2) && + ((is_serdes_configured(XAUI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_10GEC3 || port == FM1_10GEC4) && + ((is_serdes_configured(XFI_FM1_MAC1)) || + (is_serdes_configured(XFI_FM1_MAC2)))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index 10c141fa26..ae5aca4bb4 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -49,6 +49,13 @@ void fman_disable_port(enum fm_port port) setbits_be32(&gur->devdisr2, port_to_devdisr[port]); } +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -64,6 +71,11 @@ phy_interface_t fman_port_enet_if(enum fm_port port) (is_serdes_configured(XFI_FM1_MAC10)))) return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) && + ((is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + if ((port == FM2_10GEC1 || port == FM2_10GEC2) && ((is_serdes_configured(XAUI_FM2_MAC9)) || (is_serdes_configured(XAUI_FM2_MAC10)) || @@ -114,7 +126,45 @@ phy_interface_t fman_port_enet_if(enum fm_port port) return PHY_INTERFACE_MODE_SGMII; break; default: - return PHY_INTERFACE_MODE_NONE; + break; + } + + /* handle QSGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + /* check lane G on SerDes1 */ + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + /* check lane C on SerDes1 */ + if (is_serdes_configured(QSGMII_FM1_B)) + return PHY_INTERFACE_MODE_QSGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + /* check lane G on SerDes2 */ + if (is_serdes_configured(QSGMII_FM2_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + case FM2_DTSEC5: + case FM2_DTSEC6: + case FM2_DTSEC9: + case FM2_DTSEC10: + /* check lane C on SerDes2 */ + if (is_serdes_configured(QSGMII_FM2_B)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; } return PHY_INTERFACE_MODE_NONE; diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c index f450f800e2..50171230ea 100644 --- a/drivers/net/fm/tgec.c +++ b/drivers/net/fm/tgec.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include "fm.h" diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c index faec317a0a..095f00cf97 100644 --- a/drivers/net/fm/tgec_phy.c +++ b/drivers/net/fm/tgec_phy.c @@ -1,6 +1,6 @@ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Andy Fleming + * Andy Fleming * * SPDX-License-Identifier: GPL-2.0+ * Some part is taken from tsec.c diff --git a/drivers/net/fsl_mc/Makefile b/drivers/net/fsl_mc/Makefile new file mode 100644 index 0000000000..483408623c --- /dev/null +++ b/drivers/net/fsl_mc/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Layerscape MC driver +obj-y += mc.o diff --git a/drivers/net/fsl_mc/mc.c b/drivers/net/fsl_mc/mc.c new file mode 100644 index 0000000000..df84568a94 --- /dev/null +++ b/drivers/net/fsl_mc/mc.c @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +static int mc_boot_status; + +/** + * Copying MC firmware or DPL image to DDR + */ +static int mc_copy_image(const char *title, + u64 image_addr, u32 image_size, u64 mc_ram_addr) +{ + debug("%s copied to address %p\n", title, (void *)mc_ram_addr); + memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); + return 0; +} + +/** + * MC firmware FIT image parser checks if the image is in FIT + * format, verifies integrity of the image and calculates + * raw image address and size values. + * Returns 0 if success and 1 if any of the above mentioned + * task fail. + **/ + +int parse_mc_firmware_fit_image(const void **raw_image_addr, + size_t *raw_image_size) +{ + int format; + void *fit_hdr; + int node_offset; + const void *data; + size_t size; + const char *uname = "firmware"; + + /* Check if the image is in NOR flash*/ +#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR + fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR; +#else +#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined" +#endif + + /* Check if Image is in FIT format */ + format = genimg_get_format(fit_hdr); + + if (format != IMAGE_FORMAT_FIT) { + debug("Not a FIT image\n"); + return 1; + } + + if (!fit_check_format(fit_hdr)) { + debug("Bad FIT image format\n"); + return 1; + } + + node_offset = fit_image_get_node(fit_hdr, uname); + + if (node_offset < 0) { + debug("Can not find %s subimage\n", uname); + return 1; + } + + /* Verify MC firmware image */ + if (!(fit_image_verify(fit_hdr, node_offset))) { + debug("Bad MC firmware hash"); + return 1; + } + + /* Get address and size of raw image */ + fit_image_get_data(fit_hdr, node_offset, &data, &size); + + *raw_image_addr = data; + *raw_image_size = size; + + return 0; +} + +int mc_init(bd_t *bis) +{ + int error = 0; + int timeout = 200000; + struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; + u64 mc_ram_addr; + u64 mc_dpl_offset; + u32 reg_gsr; + u32 mc_fw_boot_status; + void *fdt_hdr; + int dpl_size; + const void *raw_image_addr; + size_t raw_image_size = 0; + + BUILD_BUG_ON(CONFIG_SYS_LS_MC_FW_LENGTH % 4 != 0); + + /* + * The MC private DRAM block was already carved at the end of DRAM + * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: + */ + if (gd->bd->bi_dram[1].start) { + mc_ram_addr = + gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; + } else { + mc_ram_addr = + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; + } + + /* + * Management Complex cores should be held at reset out of POR. + * U-boot should be the first software to touch MC. To be safe, + * we reset all cores again by setting GCR1 to 0. It doesn't do + * anything if they are held at reset. After we setup the firmware + * we kick off MC by deasserting the reset bit for core 0, and + * deasserting the reset bits for Command Portal Managers. + * The stop bits are not touched here. They are used to stop the + * cores when they are active. Setting stop bits doesn't stop the + * cores from fetching instructions when they are released from + * reset. + */ + out_le32(&mc_ccsr_regs->reg_gcr1, 0); + dmb(); + + error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size); + if (error != 0) + goto out; + /* + * Load the MC FW at the beginning of the MC private DRAM block: + */ + mc_copy_image( + "MC Firmware", + (u64)raw_image_addr, + raw_image_size, + mc_ram_addr); + + /* + * Calculate offset in the MC private DRAM block at which the MC DPL + * blob is to be placed: + */ +#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET + BUILD_BUG_ON( + (CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || + CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); + + mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; +#else + mc_dpl_offset = mc_get_dram_block_size() - + roundup(CONFIG_SYS_LS_MC_DPL_LENGTH, 4096); + + if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) { + printf("%s: Invalid MC DPL offset: %llu\n", + __func__, mc_dpl_offset); + error = -EINVAL; + goto out; + } +#endif + + /* Check if DPL image is in NOR flash */ +#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR + fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR; +#else +#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined" +#endif + + dpl_size = fdt_totalsize(fdt_hdr); + + /* + * Load the MC DPL blob at the far end of the MC private DRAM block: + */ + mc_copy_image( + "MC DPL blob", + (u64)fdt_hdr, + dpl_size, + mc_ram_addr + mc_dpl_offset); + + debug("mc_ccsr_regs %p\n", mc_ccsr_regs); + + /* + * Tell MC where the MC Firmware image was loaded in DDR: + */ + out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr); + out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32)); + out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK); + + /* + * Tell MC where the DPL blob was loaded in DDR, by indicating + * its offset relative to the beginning of the DDR block + * allocated to the MC firmware. The MC firmware is responsible + * for checking that there is no overlap between the DPL blob + * and the runtime heap and stack of the MC firmware itself. + * + * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of + * the GSR MC CCSR register. So, this offset is assumed to be 4-byte + * aligned. + * Care must be taken not to write 1s into bits 31 and 30 of the GSR in + * this case as the SoC COP or PIC will be signaled. + */ + out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2)); + + /* + * Deassert reset and release MC core 0 to run + */ + out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST); + dmb(); + debug("Polling mc_ccsr_regs->reg_gsr ...\n"); + + for (;;) { + reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr); + mc_fw_boot_status = (reg_gsr & GSR_FS_MASK); + if (mc_fw_boot_status & 0x1) + break; + + udelay(1000); /* throttle polling */ + if (timeout-- <= 0) + break; + } + + if (timeout <= 0) { + printf("%s: timeout booting management complex firmware\n", + __func__); + + /* TODO: Get an error status from an MC CCSR register */ + error = -ETIMEDOUT; + goto out; + } + + printf("Management complex booted (boot status: %#x)\n", + mc_fw_boot_status); + + if (mc_fw_boot_status != 0x1) { + /* + * TODO: Identify critical errors from the GSR register's FS + * field and for those errors, set error to -ENODEV or other + * appropriate errno, so that the status property is set to + * failure in the fsl,dprc device tree node. + */ + } + +out: + if (error != 0) + mc_boot_status = -error; + else + mc_boot_status = 0; + + return error; +} + +int get_mc_boot_status(void) +{ + return mc_boot_status; +} + +/** + * Return the actual size of the MC private DRAM block. + * + * NOTE: For now this function always returns the minimum required size, + * However, in the future, the actual size may be obtained from an environment + * variable. + */ +unsigned long mc_get_dram_block_size(void) +{ + return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; +} diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 1ad952d3a9..6391f9b32f 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -504,7 +504,7 @@ int mcdmafec_initialize(bd_t * bis) u32 tmp = CONFIG_SYS_INTSRAM + 0x2000; #endif - for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { + for (i = 0; i < ARRAY_SIZE(fec_info); i++) { dev = (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index ce36bd7a34..d6b181b386 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc. * Jun-jie Zhang * Mingkai Hu * @@ -11,22 +11,22 @@ #include #include #include -#include -void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, +void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, int dev_addr, int regnum, int value) { int timeout = 1000000; out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f)); out_be32(&phyregs->miimcon, value); - asm("sync"); + /* Memory barrier */ + mb(); while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--) ; } -int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, +int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, int dev_addr, int regnum) { int value; @@ -38,11 +38,13 @@ int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, /* Clear the command register, and wait */ out_be32(&phyregs->miimcom, 0); - asm("sync"); + /* Memory barrier */ + mb(); /* Initiate a read command, and wait */ out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE); - asm("sync"); + /* Memory barrier */ + mb(); /* Wait for the the indication that the read is done */ while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)) @@ -57,7 +59,8 @@ int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, static int fsl_pq_mdio_reset(struct mii_dev *bus) { - struct tsec_mii_mng *regs = bus->priv; + struct tsec_mii_mng __iomem *regs = + (struct tsec_mii_mng __iomem *)bus->priv; /* Reset MII (due to new addresses) */ out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT); @@ -72,7 +75,8 @@ static int fsl_pq_mdio_reset(struct mii_dev *bus) int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum) { - struct tsec_mii_mng *phyregs = bus->priv; + struct tsec_mii_mng __iomem *phyregs = + (struct tsec_mii_mng __iomem *)bus->priv; return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum); } @@ -80,7 +84,8 @@ int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum) int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, u16 value) { - struct tsec_mii_mng *phyregs = bus->priv; + struct tsec_mii_mng __iomem *phyregs = + (struct tsec_mii_mng __iomem *)bus->priv; tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value); @@ -101,7 +106,7 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info) bus->reset = fsl_pq_mdio_reset; sprintf(bus->name, info->name); - bus->priv = info->regs; + bus->priv = (void *)info->regs; return mdio_register(bus); } diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c index e911dd31ec..98c4f09629 100644 --- a/drivers/net/ftmac110.c +++ b/drivers/net/ftmac110.c @@ -1,7 +1,7 @@ /* * Faraday 10/100Mbps Ethernet Controller * - * (C) Copyright 2010 Faraday Technology + * (C) Copyright 2013 Faraday Technology * Dante Su * * SPDX-License-Identifier: GPL-2.0+ @@ -54,11 +54,11 @@ struct ftmac110_chip { uint32_t lnkup; uint32_t phy_addr; - struct ftmac110_rxd *rxd; + struct ftmac110_desc *rxd; ulong rxd_dma; uint32_t rxd_idx; - struct ftmac110_txd *txd; + struct ftmac110_desc *txd; ulong txd_dma; uint32_t txd_idx; }; @@ -69,7 +69,7 @@ static uint16_t mdio_read(struct eth_device *dev, uint8_t phyaddr, uint8_t phyreg) { struct ftmac110_chip *chip = dev->priv; - struct ftmac110_regs __iomem *regs = chip->regs; + struct ftmac110_regs *regs = chip->regs; uint32_t tmp, ts; uint16_t ret = 0xffff; @@ -98,7 +98,7 @@ static void mdio_write(struct eth_device *dev, uint8_t phyaddr, uint8_t phyreg, uint16_t phydata) { struct ftmac110_chip *chip = dev->priv; - struct ftmac110_regs __iomem *regs = chip->regs; + struct ftmac110_regs *regs = chip->regs; uint32_t tmp, ts; tmp = PHYCR_WRITE @@ -195,7 +195,7 @@ static int ftmac110_reset(struct eth_device *dev) uint8_t *a; uint32_t i, maccr; struct ftmac110_chip *chip = dev->priv; - struct ftmac110_regs __iomem *regs = chip->regs; + struct ftmac110_regs *regs = chip->regs; /* 1. MAC reset */ writel(MACCR_RESET, ®s->maccr); @@ -212,14 +212,15 @@ static int ftmac110_reset(struct eth_device *dev) /* 1-1. Init tx ring */ for (i = 0; i < CFG_TXDES_NUM; ++i) { /* owned by SW */ - chip->txd[i].ct[0] = 0; + chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK); } chip->txd_idx = 0; /* 1-2. Init rx ring */ for (i = 0; i < CFG_RXDES_NUM; ++i) { /* owned by HW */ - chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER); + chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK); + chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER); } chip->rxd_idx = 0; @@ -268,7 +269,7 @@ static int ftmac110_probe(struct eth_device *dev, bd_t *bis) static void ftmac110_halt(struct eth_device *dev) { struct ftmac110_chip *chip = dev->priv; - struct ftmac110_regs __iomem *regs = chip->regs; + struct ftmac110_regs *regs = chip->regs; writel(0, ®s->imr); writel(0, ®s->maccr); @@ -279,8 +280,9 @@ static void ftmac110_halt(struct eth_device *dev) static int ftmac110_send(struct eth_device *dev, void *pkt, int len) { struct ftmac110_chip *chip = dev->priv; - struct ftmac110_regs __iomem *regs = chip->regs; - struct ftmac110_txd *des; + struct ftmac110_regs *regs = chip->regs; + struct ftmac110_desc *txd; + uint64_t ctrl; if (!chip->lnkup) return 0; @@ -292,24 +294,26 @@ static int ftmac110_send(struct eth_device *dev, void *pkt, int len) len = max(60, len); - des = &chip->txd[chip->txd_idx]; - if (le32_to_cpu(des->ct[0]) & FTMAC110_TXCT0_OWNER) { + txd = &chip->txd[chip->txd_idx]; + ctrl = le64_to_cpu(txd->ctrl); + if (ctrl & FTMAC110_TXD_OWNER) { /* kick-off Tx DMA */ writel(0xffffffff, ®s->txpd); printf("ftmac110: out of txd\n"); return 0; } - memcpy(des->vbuf, (void *)pkt, len); - dma_map_single(des->vbuf, len, DMA_TO_DEVICE); + memcpy(txd->vbuf, (void *)pkt, len); + dma_map_single(txd->vbuf, len, DMA_TO_DEVICE); - /* update len, fts and lts */ - des->ct[1] &= cpu_to_le32(FTMAC110_TXCT1_END); - des->ct[1] |= cpu_to_le32(FTMAC110_TXCT1_LEN(len) - | FTMAC110_TXCT1_FTS | FTMAC110_TXCT1_LTS); - - /* set owner bit and clear others */ - des->ct[0] = cpu_to_le32(FTMAC110_TXCT0_OWNER); + /* clear control bits */ + ctrl &= FTMAC110_TXD_CLRMASK; + /* set len, fts and lts */ + ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS; + /* set owner bit */ + ctrl |= FTMAC110_TXD_OWNER; + /* write back to descriptor */ + txd->ctrl = cpu_to_le64(ctrl); /* kick-off Tx DMA */ writel(0xffffffff, ®s->txpd); @@ -322,23 +326,24 @@ static int ftmac110_send(struct eth_device *dev, void *pkt, int len) static int ftmac110_recv(struct eth_device *dev) { struct ftmac110_chip *chip = dev->priv; - struct ftmac110_rxd *des; - uint32_t ct0, len, rlen = 0; + struct ftmac110_desc *rxd; + uint32_t len, rlen = 0; + uint64_t ctrl; uint8_t *buf; if (!chip->lnkup) return 0; do { - des = &chip->rxd[chip->rxd_idx]; - ct0 = le32_to_cpu(des->ct[0]); - if (ct0 & FTMAC110_RXCT0_OWNER) + rxd = &chip->rxd[chip->rxd_idx]; + ctrl = le64_to_cpu(rxd->ctrl); + if (ctrl & FTMAC110_RXD_OWNER) break; - len = FTMAC110_RXCT0_LEN(ct0); - buf = des->vbuf; + len = (uint32_t)FTMAC110_RXD_LEN(ctrl); + buf = rxd->vbuf; - if (ct0 & FTMAC110_RXCT0_ERRMASK) { + if (ctrl & FTMAC110_RXD_ERRMASK) { printf("ftmac110: rx error\n"); } else { dma_map_single(buf, len, DMA_FROM_DEVICE); @@ -347,7 +352,9 @@ static int ftmac110_recv(struct eth_device *dev) } /* owned by hardware */ - des->ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER); + ctrl &= FTMAC110_RXD_CLRMASK; + ctrl |= FTMAC110_RXD_OWNER; + rxd->ctrl |= cpu_to_le64(ctrl); chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM; } while (0); @@ -418,46 +425,47 @@ int ftmac110_initialize(bd_t *bis) dev->recv = ftmac110_recv; if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr)) - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); /* allocate tx descriptors (it must be 16 bytes aligned) */ chip->txd = dma_alloc_coherent( - sizeof(struct ftmac110_txd) * CFG_TXDES_NUM, &chip->txd_dma); + sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma); if (!chip->txd) panic("ftmac110: out of memory 3\n"); memset(chip->txd, 0, - sizeof(struct ftmac110_txd) * CFG_TXDES_NUM); + sizeof(struct ftmac110_desc) * CFG_TXDES_NUM); for (i = 0; i < CFG_TXDES_NUM; ++i) { void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE); + if (!va) panic("ftmac110: out of memory 4\n"); - chip->txd[i].vbuf = va; - chip->txd[i].buf = cpu_to_le32(virt_to_phys(va)); - chip->txd[i].ct[1] = 0; - chip->txd[i].ct[0] = 0; /* owned by SW */ + chip->txd[i].vbuf = va; + chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va)); + chip->txd[i].ctrl = 0; /* owned by SW */ } - chip->txd[i - 1].ct[1] |= cpu_to_le32(FTMAC110_TXCT1_END); + chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END); chip->txd_idx = 0; /* allocate rx descriptors (it must be 16 bytes aligned) */ chip->rxd = dma_alloc_coherent( - sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM, &chip->rxd_dma); + sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma); if (!chip->rxd) panic("ftmac110: out of memory 4\n"); memset((void *)chip->rxd, 0, - sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM); + sizeof(struct ftmac110_desc) * CFG_RXDES_NUM); for (i = 0; i < CFG_RXDES_NUM; ++i) { void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2); + if (!va) panic("ftmac110: out of memory 5\n"); /* it needs to be exactly 2 bytes aligned */ va = ((uint8_t *)va + 2); - chip->rxd[i].vbuf = va; - chip->rxd[i].buf = cpu_to_le32(virt_to_phys(va)); - chip->rxd[i].ct[1] = cpu_to_le32(CFG_XBUF_SIZE); - chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER); + chip->rxd[i].vbuf = va; + chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va)); + chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER + | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE)); } - chip->rxd[i - 1].ct[1] |= cpu_to_le32(FTMAC110_RXCT1_END); + chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END); chip->rxd_idx = 0; eth_register(dev); diff --git a/drivers/net/ftmac110.h b/drivers/net/ftmac110.h index 19e4248bd3..2772ae7b70 100644 --- a/drivers/net/ftmac110.h +++ b/drivers/net/ftmac110.h @@ -1,7 +1,7 @@ /* * Faraday 10/100Mbps Ethernet Controller * - * (C) Copyright 2010 Faraday Technology + * (C) Copyright 2013 Faraday Technology * Dante Su * * SPDX-License-Identifier: GPL-2.0+ @@ -135,42 +135,42 @@ struct ftmac110_regs { /* * descriptor structure */ -struct ftmac110_rxd { - uint32_t ct[2]; - uint32_t buf; - void *vbuf; /* reserved */ +struct ftmac110_desc { + uint64_t ctrl; + uint32_t pbuf; + void *vbuf; }; -#define FTMAC110_RXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */ -#define FTMAC110_RXCT0_FRS BIT_MASK(29) /* first pkt desc */ -#define FTMAC110_RXCT0_LRS BIT_MASK(28) /* last pkt desc */ -#define FTMAC110_RXCT0_ODDNB BIT_MASK(22) /* odd nibble */ -#define FTMAC110_RXCT0_RUNT BIT_MASK(21) /* runt pkt */ -#define FTMAC110_RXCT0_FTL BIT_MASK(20) /* frame too long */ -#define FTMAC110_RXCT0_CRC BIT_MASK(19) /* pkt crc error */ -#define FTMAC110_RXCT0_ERR BIT_MASK(18) /* bus error */ -#define FTMAC110_RXCT0_ERRMASK (0x1f << 18) /* all errors */ -#define FTMAC110_RXCT0_BCST BIT_MASK(17) /* Bcst pkt */ -#define FTMAC110_RXCT0_MCST BIT_MASK(16) /* Mcst pkt */ -#define FTMAC110_RXCT0_LEN(x) ((x) & 0x7ff) - -#define FTMAC110_RXCT1_END BIT_MASK(31) -#define FTMAC110_RXCT1_BUFSZ(x) ((x) & 0x7ff) - -struct ftmac110_txd { - uint32_t ct[2]; - uint32_t buf; - void *vbuf; /* reserved */ -}; - -#define FTMAC110_TXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */ -#define FTMAC110_TXCT0_COL 0x00000003 /* collision */ - -#define FTMAC110_TXCT1_END BIT_MASK(31) /* end of ring */ -#define FTMAC110_TXCT1_TXIC BIT_MASK(30) /* tx done interrupt */ -#define FTMAC110_TXCT1_TX2FIC BIT_MASK(29) /* tx fifo interrupt */ -#define FTMAC110_TXCT1_FTS BIT_MASK(28) /* first pkt desc */ -#define FTMAC110_TXCT1_LTS BIT_MASK(27) /* last pkt desc */ -#define FTMAC110_TXCT1_LEN(x) ((x) & 0x7ff) +#define FTMAC110_RXD_END ((uint64_t)1 << 63) +#define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32) + +#define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ +#define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */ +#define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */ +#define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */ +#define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */ +#define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */ +#define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */ +#define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */ +#define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18) +#define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */ +#define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */ +#define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff)) + +#define FTMAC110_RXD_CLRMASK \ + (FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff)) + +#define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */ +#define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */ +#define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */ +#define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */ +#define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */ +#define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32) + +#define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ +#define FTMAC110_TXD_COL ((uint64_t)3) /* collision */ + +#define FTMAC110_TXD_CLRMASK \ + (FTMAC110_TXD_END) #endif /* FTMAC110_H */ diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c deleted file mode 100644 index cdfbfa67d8..0000000000 --- a/drivers/net/inca-ip_sw.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * INCA-IP internal switch ethernet driver. - * - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include - -#include -#include -#include -#include -#include - - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 3 -#define TOUT_LOOP 1000000 - - -#define DELAY udelay(10000) - /* Sometimes the store word instruction hangs while writing to one - * of the Switch registers. Moving the instruction into a separate - * function somehow makes the problem go away. - */ -static void SWORD(volatile u32 * reg, u32 value) -{ - *reg = value; -} - -#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; -#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) -#define SW_WRITE_REG(reg, value) \ - SWORD(reg, value);\ - DELAY;\ - SWORD(reg, value); - -#define SW_READ_REG(reg, value) \ - value = (u32)*((volatile u32*)reg);\ - DELAY;\ - value = (u32)*((volatile u32*)reg); - -#define INCA_DMA_TX_POLLING_TIME 0x07 -#define INCA_DMA_RX_POLLING_TIME 0x07 - -#define INCA_DMA_TX_HOLD 0x80000000 -#define INCA_DMA_TX_EOP 0x40000000 -#define INCA_DMA_TX_SOP 0x20000000 -#define INCA_DMA_TX_ICPT 0x10000000 -#define INCA_DMA_TX_IEOP 0x08000000 - -#define INCA_DMA_RX_C 0x80000000 -#define INCA_DMA_RX_SOP 0x40000000 -#define INCA_DMA_RX_EOP 0x20000000 - -#define INCA_SWITCH_PHY_SPEED_10H 0x1 -#define INCA_SWITCH_PHY_SPEED_10F 0x5 -#define INCA_SWITCH_PHY_SPEED_100H 0x2 -#define INCA_SWITCH_PHY_SPEED_100F 0x6 - -/************************ Auto MDIX settings ************************/ -#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR -#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL -#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT -#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 - -#define WAIT_SIGNAL_RETRIES 100 -#define WAIT_LINK_RETRIES 100 -#define LINK_RETRY_DELAY 2000 /* ms */ -/********************************************************************/ - -typedef struct -{ - union { - struct { - volatile u32 HOLD :1; - volatile u32 ICpt :1; - volatile u32 IEop :1; - volatile u32 offset :3; - volatile u32 reserved0 :4; - volatile u32 NFB :22; - }field; - - volatile u32 word; - }params; - - volatile u32 nextRxDescPtr; - - volatile u32 RxDataPtr; - - union { - struct { - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 reserved3 :12; - volatile u32 NBT :17; - }field; - - volatile u32 word; - }status; - -} inca_rx_descriptor_t; - - -typedef struct -{ - union { - struct { - volatile u32 HOLD :1; - volatile u32 Eop :1; - volatile u32 Sop :1; - volatile u32 ICpt :1; - volatile u32 IEop :1; - volatile u32 reserved0 :5; - volatile u32 NBA :22; - }field; - - volatile u32 word; - }params; - - volatile u32 nextTxDescPtr; - - volatile u32 TxDataPtr; - - volatile u32 C :1; - volatile u32 reserved3 :31; - -} inca_tx_descriptor_t; - - -static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16))); -static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16))); - -static int tx_new, rx_new, tx_hold, rx_hold; -static int tx_old_hold = -1; -static int initialized = 0; - - -static int inca_switch_init(struct eth_device *dev, bd_t * bis); -static int inca_switch_send(struct eth_device *dev, void *packet, int length); -static int inca_switch_recv(struct eth_device *dev); -static void inca_switch_halt(struct eth_device *dev); -static void inca_init_switch_chip(void); -static void inca_dma_init(void); -static int inca_amdix(void); - - -int inca_switch_initialize(bd_t * bis) -{ - struct eth_device *dev; - -#if 0 - printf("Entered inca_switch_initialize()\n"); -#endif - - if (!(dev = (struct eth_device *) malloc (sizeof *dev))) { - printf("Failed to allocate memory\n"); - return 0; - } - memset(dev, 0, sizeof(*dev)); - - inca_dma_init(); - - inca_init_switch_chip(); - -#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) - inca_amdix(); -#endif - - sprintf(dev->name, "INCA-IP Switch"); - dev->init = inca_switch_init; - dev->halt = inca_switch_halt; - dev->send = inca_switch_send; - dev->recv = inca_switch_recv; - - eth_register(dev); - -#if 0 - printf("Leaving inca_switch_initialize()\n"); -#endif - - return 0; -} - - -static int inca_switch_init(struct eth_device *dev, bd_t * bis) -{ - int i; - u32 v, regValue; - u16 wTmp; - -#if 0 - printf("Entering inca_switch_init()\n"); -#endif - - /* Set MAC address. - */ - wTmp = (u16)dev->enetaddr[0]; - regValue = (wTmp << 8) | dev->enetaddr[1]; - - SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue); - - wTmp = (u16)dev->enetaddr[2]; - regValue = (wTmp << 8) | dev->enetaddr[3]; - regValue = regValue << 16; - wTmp = (u16)dev->enetaddr[4]; - regValue |= (wTmp<<8) | dev->enetaddr[5]; - - SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue); - - /* Initialize the descriptor rings. - */ - for (i = 0; i < NUM_RX_DESC; i++) { - inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]); - memset(rx_desc, 0, sizeof(rx_ring[i])); - - /* Set maximum size of receive buffer. - */ - rx_desc->params.field.NFB = PKTSIZE_ALIGN; - - /* Set the offset of the receive buffer. Zero means - * that the offset mechanism is not used. - */ - rx_desc->params.field.offset = 0; - - /* Check if it is the last descriptor. - */ - if (i == (NUM_RX_DESC - 1)) { - /* Let the last descriptor point to the first - * one. - */ - rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring); - } else { - /* Set the address of the next descriptor. - */ - rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]); - } - - rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]); - } - -#if 0 - printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]); - printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]); -#endif - - for (i = 0; i < NUM_TX_DESC; i++) { - inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]); - - memset(tx_desc, 0, sizeof(tx_ring[i])); - - tx_desc->params.word = 0; - tx_desc->params.field.HOLD = 1; - tx_desc->C = 1; - - /* Check if it is the last descriptor. - */ - if (i == (NUM_TX_DESC - 1)) { - /* Let the last descriptor point to the - * first one. - */ - tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring); - } else { - /* Set the address of the next descriptor. - */ - tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]); - } - } - - /* Initialize RxDMA. - */ - DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v); - debug("RX status = 0x%08X\n", v); - - /* Writing to the FRDA of CHANNEL. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring); - - /* Writing to the COMMAND REG. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT); - - /* Initialize TxDMA. - */ - DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v); - debug("TX status = 0x%08X\n", v); - - /* Writing to the FRDA of CHANNEL. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring); - - tx_new = rx_new = 0; - - tx_hold = NUM_TX_DESC - 1; - rx_hold = NUM_RX_DESC - 1; - -#if 0 - rx_ring[rx_hold].params.field.HOLD = 1; -#endif - /* enable spanning tree forwarding, enable the CPU port */ - /* ST_PT: - * CPS (CPU port status) 0x3 (forwarding) - * LPS (LAN port status) 0x3 (forwarding) - * PPS (PC port status) 0x3 (forwarding) - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f); - -#if 0 - printf("Leaving inca_switch_init()\n"); -#endif - - return 0; -} - - -static int inca_switch_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int res = -1; - u32 command; - u32 regValue; - inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]); - -#if 0 - printf("Entered inca_switch_send()\n"); -#endif - - if (length <= 0) { - printf ("%s: bad packet size: %d\n", dev->name, length); - goto Done; - } - - for(i = 0; tx_desc->C == 0; i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx error buffer not ready\n", dev->name); - goto Done; - } - } - - if (tx_old_hold >= 0) { - ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1; - } - tx_old_hold = tx_hold; - - tx_desc->params.word = - (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD); - - tx_desc->C = 0; - tx_desc->TxDataPtr = (u32)packet; - tx_desc->params.field.NBA = length; - - ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0; - - tx_hold = tx_new; - tx_new = (tx_new + 1) % NUM_TX_DESC; - - - if (! initialized) { - command = INCA_IP_DMA_DMA_TXCCR0_INIT; - initialized = 1; - } else { - command = INCA_IP_DMA_DMA_TXCCR0_HR; - } - - DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); - regValue |= command; -#if 0 - printf("regValue = 0x%x\n", regValue); -#endif - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); - -#if 1 - for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx buffer not ready\n", dev->name); - goto Done; - } - } -#endif - res = length; -Done: -#if 0 - printf("Leaving inca_switch_send()\n"); -#endif - return res; -} - - -static int inca_switch_recv(struct eth_device *dev) -{ - int length = 0; - inca_rx_descriptor_t * rx_desc; - -#if 0 - printf("Entered inca_switch_recv()\n"); -#endif - - for (;;) { - rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]); - - if (rx_desc->status.field.C == 0) { - break; - } - -#if 0 - rx_ring[rx_new].params.field.HOLD = 1; -#endif - - if (! rx_desc->status.field.Eop) { - printf("Partly received packet!!!\n"); - break; - } - - length = rx_desc->status.field.NBT; - rx_desc->status.word &= - ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C); -#if 0 -{ - int i; - for (i=0;iparams.field.HOLD = 0; - - rx_hold = rx_new; - - rx_new = (rx_new + 1) % NUM_RX_DESC; - } - -#if 0 - printf("Leaving inca_switch_recv()\n"); -#endif - - return length; -} - - -static void inca_switch_halt(struct eth_device *dev) -{ -#if 0 - printf("Entered inca_switch_halt()\n"); -#endif - -#if 1 - initialized = 0; -#endif -#if 1 - /* Disable forwarding to the CPU port. - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); - - /* Close RxDMA channel. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - - /* Close TxDMA channel. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF); - - -#endif -#if 0 - printf("Leaving inca_switch_halt()\n"); -#endif -} - - -static void inca_init_switch_chip(void) -{ - u32 regValue; - - /* To workaround a problem with collision counter - * (see Errata sheet). - */ - SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001); - SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001); - -#if 1 - /* init MDIO configuration: - * MDS (Poll speed): 0x01 (4ms) - * PHY_LAN_ADDR: 0x06 - * PHY_PC_ADDR: 0x05 - * UEP (Use External PHY): 0x00 (Internal PHY is used) - * PS (Port Select): 0x00 (PT/UMM for LAN) - * PT (PHY Test): 0x00 (no test mode) - * UMM (Use MDIO Mode): 0x00 (state machine is disabled) - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50); - - /* init PHY: - * SL (Auto Neg. Speed for LAN) - * SP (Auto Neg. Speed for PC) - * LL (Link Status for LAN) - * LP (Link Status for PC) - * DL (Duplex Status for LAN) - * DP (Duplex Status for PC) - * PL (Auto Neg. Pause Status for LAN) - * PP (Auto Neg. Pause Status for PC) - */ - SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff); - - /* MDIO_ACC: - * RA (Request/Ack) 0x01 (Request) - * RW (Read/Write) 0x01 (Write) - * PHY_ADDR 0x05 (PC) - * REG_ADDR 0x00 (PHY_BCR: basic control register) - * PHY_DATA 0x8000 - * Reset - software reset - * LB (loop back) - normal - * SS (speed select) - 10 Mbit/s - * ANE (auto neg. enable) - enable - * PD (power down) - normal - * ISO (isolate) - normal - * RAN (restart auto neg.) - normal - * DM (duplex mode) - half duplex - * CT (collision test) - enable - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000); - - /* MDIO_ACC: - * RA (Request/Ack) 0x01 (Request) - * RW (Read/Write) 0x01 (Write) - * PHY_ADDR 0x06 (LAN) - * REG_ADDR 0x00 (PHY_BCR: basic control register) - * PHY_DATA 0x8000 - * Reset - software reset - * LB (loop back) - normal - * SS (speed select) - 10 Mbit/s - * ANE (auto neg. enable) - enable - * PD (power down) - normal - * ISO (isolate) - normal - * RAN (restart auto neg.) - normal - * DM (duplex mode) - half duplex - * CT (collision test) - enable - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000); - -#endif - - /* Make sure the CPU port is disabled for now. We - * don't want packets to get stacked for us until - * we enable DMA and are prepared to receive them. - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); - - SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue); - - /* CRC GEN is enabled. - */ - regValue |= 0x00000200; - SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue); - - /* ADD TAG is disabled. - */ - SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); - regValue &= ~0x00000002; - SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); -} - - -static void inca_dma_init(void) -{ - /* Switch off all DMA channels. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF); - - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF); - - /* Setup TX channel polling time. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME); - - /* Setup RX channel polling time. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME); - - /* ERRATA: write reset value into the DMA RX IMR register. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF); - - /* Just in case: disable all transmit interrupts also. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF); - - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF); -} - -#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) -static int inca_amdix(void) -{ - u32 phyReg1 = 0; - u32 phyReg4 = 0; - u32 phyReg5 = 0; - u32 phyReg6 = 0; - u32 phyReg31 = 0; - u32 regEphy = 0; - int mdi_flag; - int retries; - - /* Setup GPIO pins. - */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - -#if 0 - /* Wait for signal. - */ - retries = WAIT_SIGNAL_RETRIES; - while (--retries) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (17 << 16)); /* PHY_MCSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - if (phyReg1 & (1 << 1)) { - /* Signal detected */ - break; - } - } - - if (!retries) - goto Fail; -#endif - - /* Set MDI mode. - */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 1; - - /* Wait for link. - */ - retries = WAIT_LINK_RETRIES; - while (--retries) { - udelay(LINK_RETRY_DELAY * 1000); - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (1 << 16)); /* PHY_BSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - if (phyReg1 & (1 << 2)) { - /* Link is up */ - break; - } else if (mdi_flag) { - /* Set MDIX mode */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 0; - } else { - /* Set MDI mode */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 1; - } - } - - if (!retries) { - goto Fail; - } else { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (1 << 16)); /* PHY_BSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - /* Auto-negotiation / Parallel detection complete - */ - if (phyReg1 & (1 << 5)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (31 << 16)); /* PHY_SCSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31); - } while (phyReg31 & (1 << 31)); - - switch ((phyReg31 >> 2) & 0x7) { - case INCA_SWITCH_PHY_SPEED_10H: - /* 10Base-T Half-duplex */ - regEphy = 0; - break; - case INCA_SWITCH_PHY_SPEED_10F: - /* 10Base-T Full-duplex */ - regEphy = INCA_IP_Switch_EPHY_DL; - break; - case INCA_SWITCH_PHY_SPEED_100H: - /* 100Base-TX Half-duplex */ - regEphy = INCA_IP_Switch_EPHY_SL; - break; - case INCA_SWITCH_PHY_SPEED_100F: - /* 100Base-TX Full-duplex */ - regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL; - break; - } - - /* In case of Auto-negotiation, - * update the negotiated PAUSE support status - */ - if (phyReg1 & (1 << 3)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (6 << 16)); /* MII_EXPANSION */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); - } while (phyReg6 & (1 << 31)); - - /* We are Autoneg-able. - * Is Link partner also able to autoneg? - */ - if (phyReg6 & (1 << 0)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (4 << 16)); /* MII_ADVERTISE */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); - } while (phyReg4 & (1 << 31)); - - /* We advertise PAUSE capab. - * Does link partner also advertise it? - */ - if (phyReg4 & (1 << 10)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (5 << 16)); /* MII_LPA */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); - } while (phyReg5 & (1 << 31)); - - /* Link partner is PAUSE capab. - */ - if (phyReg5 & (1 << 10)) { - regEphy |= INCA_IP_Switch_EPHY_PL; - } - } - } - - } - - /* Link is up */ - regEphy |= INCA_IP_Switch_EPHY_LL; - - SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy); - } - } - - return 0; - -Fail: - printf("No Link on LAN port\n"); - return -1; -} -#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c new file mode 100644 index 0000000000..bedab1d606 --- /dev/null +++ b/drivers/net/keystone_net.c @@ -0,0 +1,596 @@ +/* + * Ethernet driver for TI K2HK EVM. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned int emac_open; +static struct mii_dev *mdio_bus; +static unsigned int sys_has_mdio = 1; + +#ifdef KEYSTONE2_EMAC_GIG_ENABLE +#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) +#else +#define emac_gigabit_enable(x) /* no gigabit to enable */ +#endif + +#define RX_BUFF_NUMS 24 +#define RX_BUFF_LEN 1520 +#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN +#define SGMII_ANEG_TIMEOUT 4000 + +static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); + +struct rx_buff_desc net_rx_buffs = { + .buff_ptr = rx_buffs, + .num_buffs = RX_BUFF_NUMS, + .buff_len = RX_BUFF_LEN, + .rx_flow = 22, +}; + +static void keystone2_net_serdes_setup(void); + +int keystone2_eth_read_mac_addr(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv; + u32 maca = 0; + u32 macb = 0; + + eth_priv = (struct eth_priv_t *)dev->priv; + + /* Read the e-fuse mac address */ + if (eth_priv->slave_port == 1) { + maca = __raw_readl(MAC_ID_BASE_ADDR); + macb = __raw_readl(MAC_ID_BASE_ADDR + 4); + } + + dev->enetaddr[0] = (macb >> 8) & 0xff; + dev->enetaddr[1] = (macb >> 0) & 0xff; + dev->enetaddr[2] = (maca >> 24) & 0xff; + dev->enetaddr[3] = (maca >> 16) & 0xff; + dev->enetaddr[4] = (maca >> 8) & 0xff; + dev->enetaddr[5] = (maca >> 0) & 0xff; + + return 0; +} + +/* MDIO */ + +static int keystone2_mdio_reset(struct mii_dev *bus) +{ + u_int32_t clkdiv; + struct mdio_regs *adap_mdio = bus->priv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE, + &adap_mdio->control); + + while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) + ; + + return 0; +} + +/** + * keystone2_mdio_read - read a PHY register via MDIO interface. + * Blocks until operation is complete. + */ +static int keystone2_mdio_read(struct mii_dev *bus, + int addr, int devad, int reg) +{ + int tmp; + struct mdio_regs *adap_mdio = bus->priv; + + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | + ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16), + &adap_mdio->useraccess0); + + /* Wait for command to complete */ + while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) + ; + + if (tmp & MDIO_USERACCESS0_ACK) + return tmp & 0xffff; + + return -1; +} + +/** + * keystone2_mdio_write - write to a PHY register via MDIO interface. + * Blocks until operation is complete. + */ +static int keystone2_mdio_write(struct mii_dev *bus, + int addr, int devad, int reg, u16 val) +{ + struct mdio_regs *adap_mdio = bus->priv; + + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | + ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) | + (val & 0xffff), &adap_mdio->useraccess0); + + /* Wait for command to complete */ + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + return 0; +} + +static void __attribute__((unused)) + keystone2_eth_gigabit_enable(struct eth_device *dev) +{ + u_int16_t data; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + + if (sys_has_mdio) { + data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr, + MDIO_DEVAD_NONE, 0); + /* speed selection MSB */ + if (!(data & (1 << 6))) + return; + } + + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + + CPGMACSL_REG_CTL) | + EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, + DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); +} + +int keystone_sgmii_link_status(int port) +{ + u32 status = 0; + + status = __raw_readl(SGMII_STATUS_REG(port)); + + return (status & SGMII_REG_STATUS_LOCK) && + (status & SGMII_REG_STATUS_LINK); +} + +int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) +{ + unsigned int i, status, mask; + unsigned int mr_adv_ability, control; + + switch (interface) { + case SGMII_LINK_MAC_MAC_AUTONEG: + mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | + SGMII_REG_MR_ADV_LINK | + SGMII_REG_MR_ADV_FULL_DUPLEX | + SGMII_REG_MR_ADV_GIG_MODE); + control = (SGMII_REG_CONTROL_MASTER | + SGMII_REG_CONTROL_AUTONEG); + + break; + case SGMII_LINK_MAC_PHY: + case SGMII_LINK_MAC_PHY_FORCED: + mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; + control = SGMII_REG_CONTROL_AUTONEG; + + break; + case SGMII_LINK_MAC_MAC_FORCED: + mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | + SGMII_REG_MR_ADV_LINK | + SGMII_REG_MR_ADV_FULL_DUPLEX | + SGMII_REG_MR_ADV_GIG_MODE); + control = SGMII_REG_CONTROL_MASTER; + + break; + case SGMII_LINK_MAC_FIBER: + mr_adv_ability = 0x20; + control = SGMII_REG_CONTROL_AUTONEG; + + break; + default: + mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; + control = SGMII_REG_CONTROL_AUTONEG; + } + + __raw_writel(0, SGMII_CTL_REG(port)); + + /* + * Wait for the SerDes pll to lock, + * but don't trap if lock is never read + */ + for (i = 0; i < 1000; i++) { + udelay(2000); + status = __raw_readl(SGMII_STATUS_REG(port)); + if ((status & SGMII_REG_STATUS_LOCK) != 0) + break; + } + + __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); + __raw_writel(control, SGMII_CTL_REG(port)); + + + mask = SGMII_REG_STATUS_LINK; + + if (control & SGMII_REG_CONTROL_AUTONEG) + mask |= SGMII_REG_STATUS_AUTONEG; + + status = __raw_readl(SGMII_STATUS_REG(port)); + if ((status & mask) == mask) + return 0; + + printf("\n%s Waiting for SGMII auto negotiation to complete", + phy_dev->dev->name); + while ((status & mask) != mask) { + /* + * Timeout reached ? + */ + if (i > SGMII_ANEG_TIMEOUT) { + puts(" TIMEOUT !\n"); + phy_dev->link = 0; + return 0; + } + + if (ctrlc()) { + puts("user interrupt!\n"); + phy_dev->link = 0; + return -EINTR; + } + + if ((i++ % 500) == 0) + printf("."); + + udelay(1000); /* 1 ms */ + status = __raw_readl(SGMII_STATUS_REG(port)); + } + puts(" done\n"); + + return 0; +} + +int mac_sl_reset(u32 port) +{ + u32 i, v; + + if (port >= DEVICE_N_GMACSL_PORTS) + return GMACSL_RET_INVALID_PORT; + + /* Set the soft reset bit */ + writel(CPGMAC_REG_RESET_VAL_RESET, + DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); + + /* Wait for the bit to clear */ + for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { + v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); + if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != + CPGMAC_REG_RESET_VAL_RESET) + return GMACSL_RET_OK; + } + + /* Timeout on the reset */ + return GMACSL_RET_WARN_RESET_INCOMPLETE; +} + +int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) +{ + u32 v, i; + int ret = GMACSL_RET_OK; + + if (port >= DEVICE_N_GMACSL_PORTS) + return GMACSL_RET_INVALID_PORT; + + if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { + cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; + ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; + } + + /* Must wait if the device is undergoing reset */ + for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { + v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); + if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != + CPGMAC_REG_RESET_VAL_RESET) + break; + } + + if (i == DEVICE_EMACSL_RESET_POLL_COUNT) + return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; + + writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); + writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); + +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + /* Map RX packet flow priority to 0 */ + writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); +#endif + + return ret; +} + +int ethss_config(u32 ctl, u32 max_pkt_size) +{ + u32 i; + + /* Max length register */ + writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN); + + /* Control register */ + writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL); + + /* All statistics enabled by default */ + writel(CPSW_REG_VAL_STAT_ENABLE_ALL, + DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN); + + /* Reset and enable the ALE */ + writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | + CPSW_REG_VAL_ALE_CTL_BYPASS, + DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL); + + /* All ports put into forward mode */ + for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) + writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE, + DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i)); + + return 0; +} + +int ethss_start(void) +{ + int i; + struct mac_sl_cfg cfg; + + cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; + cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; + + for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { + mac_sl_reset(i); + mac_sl_config(i, &cfg); + } + + return 0; +} + +int ethss_stop(void) +{ + int i; + + for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) + mac_sl_reset(i); + + return 0; +} + +int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) +{ + if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) + num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; + + return ksnav_send(&netcp_pktdma, buffer, + num_bytes, (slave_port_num) << 16); +} + +/* Eth device open */ +static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) +{ + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; + + debug("+ emac_open\n"); + + net_rx_buffs.rx_flow = eth_priv->rx_flow; + + sys_has_mdio = + (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; + + keystone2_net_serdes_setup(); + + if (sys_has_mdio) + keystone2_mdio_reset(mdio_bus); + + keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1, + eth_priv->sgmii_link_type); + + udelay(10000); + + /* On chip switch configuration */ + ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); + + /* TODO: add error handling code */ + if (qm_init()) { + printf("ERROR: qm_init()\n"); + return -1; + } + if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) { + qm_close(); + printf("ERROR: netcp_init()\n"); + return -1; + } + + /* + * Streaming switch configuration. If not present this + * statement is defined to void in target.h. + * If present this is usually defined to a series of register writes + */ + hw_config_streaming_switch(); + + if (sys_has_mdio) { + keystone2_mdio_reset(mdio_bus); + + phy_startup(phy_dev); + if (phy_dev->link == 0) { + ksnav_close(&netcp_pktdma); + qm_close(); + return -1; + } + } + + emac_gigabit_enable(dev); + + ethss_start(); + + debug("- emac_open\n"); + + emac_open = 1; + + return 0; +} + +/* Eth device close */ +void keystone2_eth_close(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; + + debug("+ emac_close\n"); + + if (!emac_open) + return; + + ethss_stop(); + + ksnav_close(&netcp_pktdma); + qm_close(); + phy_shutdown(phy_dev); + + emac_open = 0; + + debug("- emac_close\n"); +} + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int keystone2_eth_send_packet(struct eth_device *dev, + void *packet, int length) +{ + int ret_status = -1; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; + + genphy_update_link(phy_dev); + if (phy_dev->link == 0) + return -1; + + if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) + return ret_status; + + return length; +} + +/* + * This function handles receipt of a packet from the network + */ +static int keystone2_eth_rcv_packet(struct eth_device *dev) +{ + void *hd; + int pkt_size; + u32 *pkt; + + hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size); + if (hd == NULL) + return 0; + + NetReceive((uchar *)pkt, pkt_size); + + ksnav_release_rxhd(&netcp_pktdma, hd); + + return pkt_size; +} + +/* + * This function initializes the EMAC hardware. + */ +int keystone2_emac_initialize(struct eth_priv_t *eth_priv) +{ + int res; + struct eth_device *dev; + struct phy_device *phy_dev; + + dev = malloc(sizeof(struct eth_device)); + if (dev == NULL) + return -1; + + memset(dev, 0, sizeof(struct eth_device)); + + strcpy(dev->name, eth_priv->int_name); + dev->priv = eth_priv; + + keystone2_eth_read_mac_addr(dev); + + dev->iobase = 0; + dev->init = keystone2_eth_open; + dev->halt = keystone2_eth_close; + dev->send = keystone2_eth_send_packet; + dev->recv = keystone2_eth_rcv_packet; + + eth_register(dev); + + /* Register MDIO bus if it's not registered yet */ + if (!mdio_bus) { + mdio_bus = mdio_alloc(); + mdio_bus->read = keystone2_mdio_read; + mdio_bus->write = keystone2_mdio_write; + mdio_bus->reset = keystone2_mdio_reset; + mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR; + sprintf(mdio_bus->name, "ethernet-mdio"); + + res = mdio_register(mdio_bus); + if (res) + return res; + } + + /* Create phy device and bind it with driver */ +#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, + dev, PHY_INTERFACE_MODE_SGMII); + phy_config(phy_dev); +#else + phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, + PHY_INTERFACE_MODE_SGMII); + phy_dev->dev = dev; +#endif + eth_priv->phy_dev = phy_dev; + + return 0; +} + +struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { + .clk = SERDES_CLOCK_156P25M, + .rate = SERDES_RATE_5G, + .rate_mode = SERDES_QUARTER_RATE, + .intf = SERDES_PHY_SGMII, + .loopback = 0, +}; + +static void keystone2_net_serdes_setup(void) +{ + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); + +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#endif + + /* wait till setup */ + udelay(5000); +} diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index 2bf0068533..229658abc8 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -766,7 +766,7 @@ static int lan91c96_detect_chip(struct eth_device *dev) SMC_SELECT_BANK(dev, 3); chip_id = (SMC_inw(dev, 0xA) & LAN91C96_REV_CHIPID) >> 4; SMC_SELECT_BANK(dev, 0); - for (r = 0; r < sizeof(supported_chips) / sizeof(struct id_type); r++) + for (r = 0; r < ARRAY_SIZE(supported_chips); r++) if (chip_id == supported_chips[r].id) return r; return 0; diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 2f0d640ade..3e914ce5ad 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -58,13 +58,7 @@ typedef unsigned long int dword; #ifdef CONFIG_CPU_PXA25X -#ifdef CONFIG_LUBBOCK -#define SMC_IO_SHIFT 2 -#undef USE_32_BIT - -#else #define SMC_IO_SHIFT 0 -#endif #define SMCREG(edev, r) ((edev)->iobase+((r)< #include #include +#include #include "macb.h" -#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096 -#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128) -#define CONFIG_SYS_MACB_TX_RING_SIZE 16 -#define CONFIG_SYS_MACB_TX_TIMEOUT 1000 -#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000 +#define MACB_RX_BUFFER_SIZE 4096 +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 struct macb_dma_desc { u32 addr; u32 ctrl; }; +#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) +#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) +#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) + #define RXADDR_USED 0x00000001 #define RXADDR_WRAP 0x00000002 @@ -169,7 +174,7 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) struct eth_device *dev = eth_get_dev_by_name(devname); struct macb_device *macb = to_macb(dev); - if ( macb->phy_addr != phy_adr ) + if (macb->phy_addr != phy_adr) return -1; arch_get_mdio_control(devname); @@ -183,7 +188,7 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) struct eth_device *dev = eth_get_dev_by_name(devname); struct macb_device *macb = to_macb(dev); - if ( macb->phy_addr != phy_adr ) + if (macb->phy_addr != phy_adr) return -1; arch_get_mdio_control(devname); @@ -193,6 +198,39 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) } #endif +#define RX 1 +#define TX 0 +static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) +{ + if (rx) + invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + + MACB_RX_DMA_DESC_SIZE); + else + invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + + MACB_TX_DMA_DESC_SIZE); +} + +static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) +{ + if (rx) + flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + + MACB_RX_DMA_DESC_SIZE); + else + flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + + MACB_TX_DMA_DESC_SIZE); +} + +static inline void macb_flush_rx_buffer(struct macb_device *macb) +{ + flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + + MACB_RX_BUFFER_SIZE); +} + +static inline void macb_invalidate_rx_buffer(struct macb_device *macb) +{ + invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + + MACB_RX_BUFFER_SIZE); +} #if defined(CONFIG_CMD_NET) @@ -207,23 +245,28 @@ static int macb_send(struct eth_device *netdev, void *packet, int length) ctrl = length & TXBUF_FRMLEN_MASK; ctrl |= TXBUF_FRAME_END; - if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) { + if (tx_head == (MACB_TX_RING_SIZE - 1)) { ctrl |= TXBUF_WRAP; macb->tx_head = 0; - } else + } else { macb->tx_head++; + } macb->tx_ring[tx_head].ctrl = ctrl; macb->tx_ring[tx_head].addr = paddr; barrier(); + macb_flush_ring_desc(macb, TX); + /* Do we need check paddr and length is dcache line aligned? */ + flush_dcache_range(paddr, paddr + length); macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); /* * I guess this is necessary because the networking core may * re-use the transmit buffer as soon as we return... */ - for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) { + for (i = 0; i <= MACB_TX_TIMEOUT; i++) { barrier(); + macb_invalidate_ring_desc(macb, TX); ctrl = macb->tx_ring[tx_head].ctrl; if (ctrl & TXBUF_USED) break; @@ -232,7 +275,7 @@ static int macb_send(struct eth_device *netdev, void *packet, int length) dma_unmap_single(packet, length, paddr); - if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) { + if (i <= MACB_TX_TIMEOUT) { if (ctrl & TXBUF_UNDERRUN) printf("%s: TX underrun\n", netdev->name); if (ctrl & TXBUF_EXHAUSTED) @@ -252,10 +295,12 @@ static void reclaim_rx_buffers(struct macb_device *macb, unsigned int i; i = macb->rx_tail; + + macb_invalidate_ring_desc(macb, RX); while (i > new_tail) { macb->rx_ring[i].addr &= ~RXADDR_USED; i++; - if (i > CONFIG_SYS_MACB_RX_RING_SIZE) + if (i > MACB_RX_RING_SIZE) i = 0; } @@ -265,6 +310,7 @@ static void reclaim_rx_buffers(struct macb_device *macb, } barrier(); + macb_flush_ring_desc(macb, RX); macb->rx_tail = new_tail; } @@ -278,6 +324,8 @@ static int macb_recv(struct eth_device *netdev) u32 status; for (;;) { + macb_invalidate_ring_desc(macb, RX); + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) return -1; @@ -291,10 +339,12 @@ static int macb_recv(struct eth_device *netdev) if (status & RXBUF_FRAME_END) { buffer = macb->rx_buffer + 128 * macb->rx_tail; length = status & RXBUF_FRMLEN_MASK; + + macb_invalidate_rx_buffer(macb); if (wrapped) { unsigned int headlen, taillen; - headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE + headlen = 128 * (MACB_RX_RING_SIZE - macb->rx_tail); taillen = length - headlen; memcpy((void *)NetRxPackets[0], @@ -305,11 +355,11 @@ static int macb_recv(struct eth_device *netdev) } NetReceive(buffer, length); - if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) + if (++rx_tail >= MACB_RX_RING_SIZE) rx_tail = 0; reclaim_rx_buffers(macb, rx_tail); } else { - if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) { + if (++rx_tail >= MACB_RX_RING_SIZE) { wrapped = 1; rx_tail = 0; } @@ -332,7 +382,7 @@ static void macb_phy_reset(struct macb_device *macb) macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); - for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { status = macb_mdio_read(macb, MII_BMSR); if (status & BMSR_ANEGCOMPLETE) break; @@ -369,6 +419,15 @@ static int macb_phy_find(struct macb_device *macb) } #endif /* CONFIG_MACB_SEARCH_PHY */ +#ifdef CONFIG_PHYLIB +#define gbit_phy_support(p) ((p)->supported & \ + (SUPPORTED_1000baseT_Full | \ + SUPPORTED_1000baseT_Half)) +#elif defined(CONFIG_RGMII) || defined(CONFIG_GMII) +#define gbit_phy_support(p) 1 +#else +#define gbit_phy_support(p) 0 +#endif static int macb_phy_init(struct macb_device *macb) { @@ -384,9 +443,8 @@ static int macb_phy_init(struct macb_device *macb) arch_get_mdio_control(netdev->name); #ifdef CONFIG_MACB_SEARCH_PHY /* Auto-detect phy_addr */ - if (!macb_phy_find(macb)) { + if (!macb_phy_find(macb)) return 0; - } #endif /* CONFIG_MACB_SEARCH_PHY */ /* Check if the PHY is up to snuff... */ @@ -397,9 +455,14 @@ static int macb_phy_init(struct macb_device *macb) } #ifdef CONFIG_PHYLIB - phydev->bus = macb->bus; - phydev->dev = netdev; - phydev->addr = macb->phy_addr; + /* need to consider other phy interface mode */ + phydev = phy_connect(macb->bus, macb->phy_addr, netdev, + PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + printf("phy_connect failed\n"); + return -ENODEV; + } + phy_config(phydev); #endif @@ -408,7 +471,7 @@ static int macb_phy_init(struct macb_device *macb) /* Try to re-negotiate if we don't have link already. */ macb_phy_reset(macb); - for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { status = macb_mdio_read(macb, MII_BMSR); if (status & BMSR_LSTATUS) break; @@ -424,35 +487,28 @@ static int macb_phy_init(struct macb_device *macb) /* First check for GMAC */ if (macb_is_gem(macb)) { - lpa = macb_mdio_read(macb, MII_STAT1000); - if (lpa & (1 << 11)) { - speed = 1000; - duplex = 1; - } else { - if (lpa & (1 << 10)) { - speed = 1000; - duplex = 1; - } else { - speed = 0; - } - } + if (gbit_phy_support(phydev)) { + lpa = macb_mdio_read(macb, MII_STAT1000); + + if (lpa & (LPA_1000FULL | LPA_1000HALF)) { + duplex = ((lpa & LPA_1000FULL) ? 1 : 0); - if (speed == 1000) { - printf("%s: link up, %dMbps %s-duplex (lpa: 0x%04x)\n", - netdev->name, - speed, - duplex ? "full" : "half", - lpa); + printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", + netdev->name, + duplex ? "full" : "half", + lpa); - ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); ncfgr |= GEM_BIT(GBE); - if (duplex) - ncfgr |= MACB_BIT(FD); - macb_writel(macb, NCFGR, ncfgr); - return 1; + if (duplex) + ncfgr |= MACB_BIT(FD); + + macb_writel(macb, NCFGR, ncfgr); + + return 1; + } } } @@ -480,6 +536,7 @@ static int macb_phy_init(struct macb_device *macb) return 1; } +static int macb_write_hwaddr(struct eth_device *dev); static int macb_init(struct eth_device *netdev, bd_t *bd) { struct macb_device *macb = to_macb(netdev); @@ -493,27 +550,40 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) /* initialize DMA descriptors */ paddr = macb->rx_buffer_dma; - for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) { - if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1)) + for (i = 0; i < MACB_RX_RING_SIZE; i++) { + if (i == (MACB_RX_RING_SIZE - 1)) paddr |= RXADDR_WRAP; macb->rx_ring[i].addr = paddr; macb->rx_ring[i].ctrl = 0; paddr += 128; } - for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) { + macb_flush_ring_desc(macb, RX); + macb_flush_rx_buffer(macb); + + for (i = 0; i < MACB_TX_RING_SIZE; i++) { macb->tx_ring[i].addr = 0; - if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) + if (i == (MACB_TX_RING_SIZE - 1)) macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; else macb->tx_ring[i].ctrl = TXBUF_USED; } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + macb_flush_ring_desc(macb, TX); + + macb->rx_tail = 0; + macb->tx_head = 0; + macb->tx_tail = 0; macb_writel(macb, RBQP, macb->rx_ring_dma); macb_writel(macb, TBQP, macb->tx_ring_dma); if (macb_is_gem(macb)) { -#ifdef CONFIG_RGMII + /* + * When the GMAC IP with GE feature, this bit is used to + * select interface between RGMII and GMII. + * When the GMAC IP without GE feature, this bit is used + * to select interface between RMII and MII. + */ +#if defined(CONFIG_RGMII) || defined(CONFIG_RMII) gem_writel(macb, UR, GEM_BIT(RGMII)); #else gem_writel(macb, UR, 0); @@ -535,6 +605,14 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) #endif /* CONFIG_RMII */ } + /* update the ethaddr */ + if (is_valid_ether_addr(netdev->enetaddr)) { + macb_write_hwaddr(netdev); + } else { + printf("%s: mac address is not valid\n", netdev->name); + return -1; + } + if (!macb_phy_init(macb)) return -1; @@ -615,6 +693,24 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb) return config; } +/* + * Get the DMA bus width field of the network configuration register that we + * should program. We find the width from decoding the design configuration + * register to find the maximum supported data bus width. + */ +static u32 macb_dbw(struct macb_device *macb) +{ + switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { + case 4: + return GEM_BF(DBW, GEM_DBW128); + case 2: + return GEM_BF(DBW, GEM_DBW64); + case 1: + default: + return GEM_BF(DBW, GEM_DBW32); + } +} + int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; @@ -630,15 +726,15 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) netdev = &macb->netdev; - macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, + macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, &macb->rx_buffer_dma); - macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE - * sizeof(struct macb_dma_desc), + macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, &macb->rx_ring_dma); - macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE - * sizeof(struct macb_dma_desc), + macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, &macb->tx_ring_dma); + /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ + macb->regs = regs; macb->phy_addr = phy_addr; @@ -659,7 +755,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) */ if (macb_is_gem(macb)) { ncfgr = gem_mdc_clk_div(id, macb); - ncfgr |= GEM_BF(DBW, 1); + ncfgr |= macb_dbw(macb); } else { ncfgr = macb_mdc_clk_div(id, macb); } diff --git a/drivers/net/macb.h b/drivers/net/macb.h index de5214fe6e..06f7c66dfd 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -58,6 +58,9 @@ #define MACB_WOL 0x00c4 #define MACB_MID 0x00fc +/* GEM specific register offsets */ +#define GEM_DCFG1 0x0280 + /* Bitfields in NCR */ #define MACB_LB_OFFSET 0 #define MACB_LB_SIZE 1 @@ -242,6 +245,14 @@ #define MACB_IDNUM_SIZE 16 /* Bitfields in DCFG1 */ +#define GEM_DBWDEF_OFFSET 25 +#define GEM_DBWDEF_SIZE 3 + +/* constants for data bus width */ +#define GEM_DBW32 0 +#define GEM_DBW64 1 +#define GEM_DBW128 2 + /* Constants for CLK */ #define MACB_CLK_DIV8 0 #define MACB_CLK_DIV16 1 diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 6b537d505e..7c4b210b00 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -543,7 +543,7 @@ int mcffec_initialize(bd_t * bis) u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; #endif - for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { + for (i = 0; i < ARRAY_SIZE(fec_info); i++) { dev = (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 2f2269d531..17a780c854 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -170,7 +170,7 @@ int mii_discover_phy(struct eth_device *dev) printf("PHY @ 0x%x pass %d\n", phyno, pass); #endif - for (i = 0; (i < (sizeof(phyinfo) / sizeof(phy_info_t))) + for (i = 0; (i < ARRAY_SIZE(phyinfo)) && (phyinfo[i].phyid != 0); i++) { if (phyinfo[i].phyid == phytype) { #ifdef ET_DEBUG diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index 1093ba59da..d2a8ae0868 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -407,13 +407,8 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) */ if (fec->xcv_type == SEVENWIRE) { /* 10MBit with 7-wire operation */ -#if defined(CONFIG_TOTAL5200) - /* 7-wire and USB2 on Ethernet */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000; -#else /* !CONFIG_TOTAL5200 */ /* 7-wire only */ *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000; -#endif /* CONFIG_TOTAL5200 */ } else { /* 100MBit with MD operation */ *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000; @@ -476,11 +471,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) miiphy_write(dev->name, phyAddr, 0x0, 0x8000); udelay(1000); -#if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52) - /* Set the LED configuration Register for the UC101 - and MUCMC52 Board */ - miiphy_write(dev->name, phyAddr, 0x14, 0x4122); -#endif if (fec->xcv_type == MII10) { /* * Force 10Base-T, FDX operation diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 6c901d1eaa..6b31a82ec4 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -24,7 +24,7 @@ #include #if defined(CONFIG_KIRKWOOD) -#include +#include #elif defined(CONFIG_ORION5X) #include #elif defined(CONFIG_DOVE) @@ -35,6 +35,10 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_MVGBE_PORTS +# define CONFIG_MVGBE_PORTS {0, 0} +#endif + #define MV_PHY_ADR_REQUEST 0xee #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) @@ -420,8 +424,9 @@ static int mvgbe_init(struct eth_device *dev) { struct mvgbe_device *dmvgbe = to_mvgbe(dev); struct mvgbe_registers *regs = dmvgbe->regs; -#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ - && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ + !defined(CONFIG_PHYLIB) && \ + defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) int i; #endif /* setup RX rings */ diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c new file mode 100644 index 0000000000..a2a69b4219 --- /dev/null +++ b/drivers/net/mvneta.c @@ -0,0 +1,1653 @@ +/* + * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. + * + * U-Boot version: + * Copyright (C) 2014 Stefan Roese + * + * Based on the Linux version which is: + * Copyright (C) 2012 Marvell + * + * Rami Rosen + * Thomas Petazzoni + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if !defined(CONFIG_PHYLIB) +# error Marvell mvneta requires PHYLIB +#endif + +/* Some linux -> U-Boot compatibility stuff */ +#define netdev_err(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_warn(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_info(dev, fmt, args...) \ + printf(fmt, ##args) + +#define CONFIG_NR_CPUS 1 +#define BIT(nr) (1UL << (nr)) +#define ETH_HLEN 14 /* Total octets in header */ + +/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ +#define WRAP (2 + ETH_HLEN + 4 + 32) +#define MTU 1500 +#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) + +#define MVNETA_SMI_TIMEOUT 10000 + +/* Registers */ +#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) +#define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) +#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) +#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) +#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) +#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) +#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) +#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) +#define MVNETA_RXQ_BUF_SIZE_SHIFT 19 +#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) +#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) +#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff +#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) +#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 +#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 +#define MVNETA_PORT_RX_RESET 0x1cc0 +#define MVNETA_PORT_RX_DMA_RESET BIT(0) +#define MVNETA_PHY_ADDR 0x2000 +#define MVNETA_PHY_ADDR_MASK 0x1f +#define MVNETA_SMI 0x2004 +#define MVNETA_PHY_REG_MASK 0x1f +/* SMI register fields */ +#define MVNETA_SMI_DATA_OFFS 0 /* Data */ +#define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS) +#define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ +#define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) +#define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ +#define MVNETA_SMI_BUSY (1 << 28) /* Busy */ +#define MVNETA_MBUS_RETRY 0x2010 +#define MVNETA_UNIT_INTR_CAUSE 0x2080 +#define MVNETA_UNIT_CONTROL 0x20B0 +#define MVNETA_PHY_POLLING_ENABLE BIT(1) +#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) +#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) +#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) +#define MVNETA_BASE_ADDR_ENABLE 0x2290 +#define MVNETA_PORT_CONFIG 0x2400 +#define MVNETA_UNI_PROMISC_MODE BIT(0) +#define MVNETA_DEF_RXQ(q) ((q) << 1) +#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) +#define MVNETA_TX_UNSET_ERR_SUM BIT(12) +#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) +#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) +#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) +#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) +#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ + MVNETA_DEF_RXQ_ARP(q) | \ + MVNETA_DEF_RXQ_TCP(q) | \ + MVNETA_DEF_RXQ_UDP(q) | \ + MVNETA_DEF_RXQ_BPDU(q) | \ + MVNETA_TX_UNSET_ERR_SUM | \ + MVNETA_RX_CSUM_WITH_PSEUDO_HDR) +#define MVNETA_PORT_CONFIG_EXTEND 0x2404 +#define MVNETA_MAC_ADDR_LOW 0x2414 +#define MVNETA_MAC_ADDR_HIGH 0x2418 +#define MVNETA_SDMA_CONFIG 0x241c +#define MVNETA_SDMA_BRST_SIZE_16 4 +#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) +#define MVNETA_RX_NO_DATA_SWAP BIT(4) +#define MVNETA_TX_NO_DATA_SWAP BIT(5) +#define MVNETA_DESC_SWAP BIT(6) +#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) +#define MVNETA_PORT_STATUS 0x2444 +#define MVNETA_TX_IN_PRGRS BIT(1) +#define MVNETA_TX_FIFO_EMPTY BIT(8) +#define MVNETA_RX_MIN_FRAME_SIZE 0x247c +#define MVNETA_SERDES_CFG 0x24A0 +#define MVNETA_SGMII_SERDES_PROTO 0x0cc7 +#define MVNETA_QSGMII_SERDES_PROTO 0x0667 +#define MVNETA_TYPE_PRIO 0x24bc +#define MVNETA_FORCE_UNI BIT(21) +#define MVNETA_TXQ_CMD_1 0x24e4 +#define MVNETA_TXQ_CMD 0x2448 +#define MVNETA_TXQ_DISABLE_SHIFT 8 +#define MVNETA_TXQ_ENABLE_MASK 0x000000ff +#define MVNETA_ACC_MODE 0x2500 +#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) +#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff +#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 +#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) + +/* Exception Interrupt Port/Queue Cause register */ + +#define MVNETA_INTR_NEW_CAUSE 0x25a0 +#define MVNETA_INTR_NEW_MASK 0x25a4 + +/* bits 0..7 = TXQ SENT, one bit per queue. + * bits 8..15 = RXQ OCCUP, one bit per queue. + * bits 16..23 = RXQ FREE, one bit per queue. + * bit 29 = OLD_REG_SUM, see old reg ? + * bit 30 = TX_ERR_SUM, one bit for 4 ports + * bit 31 = MISC_SUM, one bit for 4 ports + */ +#define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) +#define MVNETA_TX_INTR_MASK_ALL (0xff << 0) +#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) +#define MVNETA_RX_INTR_MASK_ALL (0xff << 8) + +#define MVNETA_INTR_OLD_CAUSE 0x25a8 +#define MVNETA_INTR_OLD_MASK 0x25ac + +/* Data Path Port/Queue Cause Register */ +#define MVNETA_INTR_MISC_CAUSE 0x25b0 +#define MVNETA_INTR_MISC_MASK 0x25b4 +#define MVNETA_INTR_ENABLE 0x25b8 + +#define MVNETA_RXQ_CMD 0x2680 +#define MVNETA_RXQ_DISABLE_SHIFT 8 +#define MVNETA_RXQ_ENABLE_MASK 0x000000ff +#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) +#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) +#define MVNETA_GMAC_CTRL_0 0x2c00 +#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 +#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc +#define MVNETA_GMAC0_PORT_ENABLE BIT(0) +#define MVNETA_GMAC_CTRL_2 0x2c08 +#define MVNETA_GMAC2_PCS_ENABLE BIT(3) +#define MVNETA_GMAC2_PORT_RGMII BIT(4) +#define MVNETA_GMAC2_PORT_RESET BIT(6) +#define MVNETA_GMAC_STATUS 0x2c10 +#define MVNETA_GMAC_LINK_UP BIT(0) +#define MVNETA_GMAC_SPEED_1000 BIT(1) +#define MVNETA_GMAC_SPEED_100 BIT(2) +#define MVNETA_GMAC_FULL_DUPLEX BIT(3) +#define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) +#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) +#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) +#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) +#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c +#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) +#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) +#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) +#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) +#define MVNETA_GMAC_AN_SPEED_EN BIT(7) +#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) +#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) +#define MVNETA_MIB_COUNTERS_BASE 0x3080 +#define MVNETA_MIB_LATE_COLLISION 0x7c +#define MVNETA_DA_FILT_SPEC_MCAST 0x3400 +#define MVNETA_DA_FILT_OTH_MCAST 0x3500 +#define MVNETA_DA_FILT_UCAST_BASE 0x3600 +#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) +#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) +#define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 +#define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) +#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) +#define MVNETA_TXQ_DEC_SENT_SHIFT 16 +#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) +#define MVNETA_TXQ_SENT_DESC_SHIFT 16 +#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 +#define MVNETA_PORT_TX_RESET 0x3cf0 +#define MVNETA_PORT_TX_DMA_RESET BIT(0) +#define MVNETA_TX_MTU 0x3e0c +#define MVNETA_TX_TOKEN_SIZE 0x3e14 +#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff +#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) +#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff + +/* Descriptor ring Macros */ +#define MVNETA_QUEUE_NEXT_DESC(q, index) \ + (((index) < (q)->last_desc) ? ((index) + 1) : 0) + +/* Various constants */ + +/* Coalescing */ +#define MVNETA_TXDONE_COAL_PKTS 16 +#define MVNETA_RX_COAL_PKTS 32 +#define MVNETA_RX_COAL_USEC 100 + +/* The two bytes Marvell header. Either contains a special value used + * by Marvell switches when a specific hardware mode is enabled (not + * supported by this driver) or is filled automatically by zeroes on + * the RX side. Those two bytes being at the front of the Ethernet + * header, they allow to have the IP header aligned on a 4 bytes + * boundary automatically: the hardware skips those two bytes on its + * own. + */ +#define MVNETA_MH_SIZE 2 + +#define MVNETA_VLAN_TAG_LEN 4 + +#define MVNETA_CPU_D_CACHE_LINE_SIZE 32 +#define MVNETA_TX_CSUM_MAX_SIZE 9800 +#define MVNETA_ACC_MODE_EXT 1 + +/* Timeout constants */ +#define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 +#define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 +#define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 + +#define MVNETA_TX_MTU_MAX 0x3ffff + +/* Max number of Rx descriptors */ +#define MVNETA_MAX_RXD 16 + +/* Max number of Tx descriptors */ +#define MVNETA_MAX_TXD 16 + +/* descriptor aligned size */ +#define MVNETA_DESC_ALIGNED_SIZE 32 + +struct mvneta_port { + void __iomem *base; + struct mvneta_rx_queue *rxqs; + struct mvneta_tx_queue *txqs; + + u8 mcast_count[256]; + u16 tx_ring_size; + u16 rx_ring_size; + + phy_interface_t phy_interface; + unsigned int link; + unsigned int duplex; + unsigned int speed; + + int init; + int phyaddr; + struct phy_device *phydev; + struct mii_dev *bus; +}; + +/* The mvneta_tx_desc and mvneta_rx_desc structures describe the + * layout of the transmit and reception DMA descriptors, and their + * layout is therefore defined by the hardware design + */ + +#define MVNETA_TX_L3_OFF_SHIFT 0 +#define MVNETA_TX_IP_HLEN_SHIFT 8 +#define MVNETA_TX_L4_UDP BIT(16) +#define MVNETA_TX_L3_IP6 BIT(17) +#define MVNETA_TXD_IP_CSUM BIT(18) +#define MVNETA_TXD_Z_PAD BIT(19) +#define MVNETA_TXD_L_DESC BIT(20) +#define MVNETA_TXD_F_DESC BIT(21) +#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ + MVNETA_TXD_L_DESC | \ + MVNETA_TXD_F_DESC) +#define MVNETA_TX_L4_CSUM_FULL BIT(30) +#define MVNETA_TX_L4_CSUM_NOT BIT(31) + +#define MVNETA_RXD_ERR_CRC 0x0 +#define MVNETA_RXD_ERR_SUMMARY BIT(16) +#define MVNETA_RXD_ERR_OVERRUN BIT(17) +#define MVNETA_RXD_ERR_LEN BIT(18) +#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) +#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) +#define MVNETA_RXD_L3_IP4 BIT(25) +#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) +#define MVNETA_RXD_L4_CSUM_OK BIT(30) + +struct mvneta_tx_desc { + u32 command; /* Options used by HW for packet transmitting.*/ + u16 reserverd1; /* csum_l4 (for future use) */ + u16 data_size; /* Data size of transmitted packet in bytes */ + u32 buf_phys_addr; /* Physical addr of transmitted buffer */ + u32 reserved2; /* hw_cmd - (for future use, PMT) */ + u32 reserved3[4]; /* Reserved - (for future use) */ +}; + +struct mvneta_rx_desc { + u32 status; /* Info about received packet */ + u16 reserved1; /* pnc_info - (for future use, PnC) */ + u16 data_size; /* Size of received packet in bytes */ + + u32 buf_phys_addr; /* Physical address of the buffer */ + u32 reserved2; /* pnc_flow_id (for future use, PnC) */ + + u32 buf_cookie; /* cookie for access to RX buffer in rx path */ + u16 reserved3; /* prefetch_cmd, for future use */ + u16 reserved4; /* csum_l4 - (for future use, PnC) */ + + u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ + u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ +}; + +struct mvneta_tx_queue { + /* Number of this TX queue, in the range 0-7 */ + u8 id; + + /* Number of TX DMA descriptors in the descriptor ring */ + int size; + + /* Index of last TX DMA descriptor that was inserted */ + int txq_put_index; + + /* Index of the TX DMA descriptor to be cleaned up */ + int txq_get_index; + + /* Virtual address of the TX DMA descriptors array */ + struct mvneta_tx_desc *descs; + + /* DMA address of the TX DMA descriptors array */ + dma_addr_t descs_phys; + + /* Index of the last TX DMA descriptor */ + int last_desc; + + /* Index of the next TX DMA descriptor to process */ + int next_desc_to_proc; +}; + +struct mvneta_rx_queue { + /* rx queue number, in the range 0-7 */ + u8 id; + + /* num of rx descriptors in the rx descriptor ring */ + int size; + + /* Virtual address of the RX DMA descriptors array */ + struct mvneta_rx_desc *descs; + + /* DMA address of the RX DMA descriptors array */ + dma_addr_t descs_phys; + + /* Index of the last RX DMA descriptor */ + int last_desc; + + /* Index of the next RX DMA descriptor to process */ + int next_desc_to_proc; +}; + +/* U-Boot doesn't use the queues, so set the number to 1 */ +static int rxq_number = 1; +static int txq_number = 1; +static int rxq_def; + +struct buffer_location { + struct mvneta_tx_desc *tx_descs; + struct mvneta_rx_desc *rx_descs; + u32 rx_buffers; +}; + +/* + * All 4 interfaces use the same global buffer, since only one interface + * can be enabled at once + */ +static struct buffer_location buffer_loc; + +/* + * Page table entries are set to 1MB, or multiples of 1MB + * (not < 1MB). driver uses less bd's so use 1MB bdspace. + */ +#define BD_SPACE (1 << 20) + +/* Utility/helper methods */ + +/* Write helper method */ +static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) +{ + writel(data, pp->base + offset); +} + +/* Read helper method */ +static u32 mvreg_read(struct mvneta_port *pp, u32 offset) +{ + return readl(pp->base + offset); +} + +/* Clear all MIB counters */ +static void mvneta_mib_counters_clear(struct mvneta_port *pp) +{ + int i; + + /* Perform dummy reads from MIB counters */ + for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) + mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); +} + +/* Rx descriptors helper methods */ + +/* Checks whether the RX descriptor having this status is both the first + * and the last descriptor for the RX packet. Each RX packet is currently + * received through a single RX descriptor, so not having each RX + * descriptor with its first and last bits set is an error + */ +static int mvneta_rxq_desc_is_first_last(u32 status) +{ + return (status & MVNETA_RXD_FIRST_LAST_DESC) == + MVNETA_RXD_FIRST_LAST_DESC; +} + +/* Add number of descriptors ready to receive new packets */ +static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq, + int ndescs) +{ + /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can + * be added at once + */ + while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), + (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << + MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); + ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; + } + + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), + (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); +} + +/* Get number of RX descriptors occupied by received packets */ +static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq) +{ + u32 val; + + val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); + return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; +} + +/* Update num of rx desc called upon return from rx path or + * from mvneta_rxq_drop_pkts(). + */ +static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq, + int rx_done, int rx_filled) +{ + u32 val; + + if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { + val = rx_done | + (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); + return; + } + + /* Only 255 descriptors can be added at once */ + while ((rx_done > 0) || (rx_filled > 0)) { + if (rx_done <= 0xff) { + val = rx_done; + rx_done = 0; + } else { + val = 0xff; + rx_done -= 0xff; + } + if (rx_filled <= 0xff) { + val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; + rx_filled = 0; + } else { + val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; + rx_filled -= 0xff; + } + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); + } +} + +/* Get pointer to next RX descriptor to be processed by SW */ +static struct mvneta_rx_desc * +mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) +{ + int rx_desc = rxq->next_desc_to_proc; + + rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); + return rxq->descs + rx_desc; +} + +/* Tx descriptors helper methods */ + +/* Update HW with number of TX descriptors to be sent */ +static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, + struct mvneta_tx_queue *txq, + int pend_desc) +{ + u32 val; + + /* Only 255 descriptors can be added at once ; Assume caller + * process TX desriptors in quanta less than 256 + */ + val = pend_desc; + mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); +} + +/* Get pointer to next TX descriptor to be processed (send) by HW */ +static struct mvneta_tx_desc * +mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) +{ + int tx_desc = txq->next_desc_to_proc; + + txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); + return txq->descs + tx_desc; +} + +/* Set rxq buf size */ +static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq, + int buf_size) +{ + u32 val; + + val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); + + val &= ~MVNETA_RXQ_BUF_SIZE_MASK; + val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); + + mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); +} + +/* Start the Ethernet port RX and TX activity */ +static void mvneta_port_up(struct mvneta_port *pp) +{ + int queue; + u32 q_map; + + /* Enable all initialized TXs. */ + mvneta_mib_counters_clear(pp); + q_map = 0; + for (queue = 0; queue < txq_number; queue++) { + struct mvneta_tx_queue *txq = &pp->txqs[queue]; + if (txq->descs != NULL) + q_map |= (1 << queue); + } + mvreg_write(pp, MVNETA_TXQ_CMD, q_map); + + /* Enable all initialized RXQs. */ + q_map = 0; + for (queue = 0; queue < rxq_number; queue++) { + struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; + if (rxq->descs != NULL) + q_map |= (1 << queue); + } + mvreg_write(pp, MVNETA_RXQ_CMD, q_map); +} + +/* Stop the Ethernet port activity */ +static void mvneta_port_down(struct mvneta_port *pp) +{ + u32 val; + int count; + + /* Stop Rx port activity. Check port Rx activity. */ + val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; + + /* Issue stop command for active channels only */ + if (val != 0) + mvreg_write(pp, MVNETA_RXQ_CMD, + val << MVNETA_RXQ_DISABLE_SHIFT); + + /* Wait for all Rx activity to terminate. */ + count = 0; + do { + if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { + netdev_warn(pp->dev, + "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", + val); + break; + } + mdelay(1); + + val = mvreg_read(pp, MVNETA_RXQ_CMD); + } while (val & 0xff); + + /* Stop Tx port activity. Check port Tx activity. Issue stop + * command for active channels only + */ + val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; + + if (val != 0) + mvreg_write(pp, MVNETA_TXQ_CMD, + (val << MVNETA_TXQ_DISABLE_SHIFT)); + + /* Wait for all Tx activity to terminate. */ + count = 0; + do { + if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { + netdev_warn(pp->dev, + "TIMEOUT for TX stopped status=0x%08x\n", + val); + break; + } + mdelay(1); + + /* Check TX Command reg that all Txqs are stopped */ + val = mvreg_read(pp, MVNETA_TXQ_CMD); + + } while (val & 0xff); + + /* Double check to verify that TX FIFO is empty */ + count = 0; + do { + if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { + netdev_warn(pp->dev, + "TX FIFO empty timeout status=0x08%x\n", + val); + break; + } + mdelay(1); + + val = mvreg_read(pp, MVNETA_PORT_STATUS); + } while (!(val & MVNETA_TX_FIFO_EMPTY) && + (val & MVNETA_TX_IN_PRGRS)); + + udelay(200); +} + +/* Enable the port by setting the port enable bit of the MAC control register */ +static void mvneta_port_enable(struct mvneta_port *pp) +{ + u32 val; + + /* Enable port */ + val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); + val |= MVNETA_GMAC0_PORT_ENABLE; + mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); +} + +/* Disable the port and wait for about 200 usec before retuning */ +static void mvneta_port_disable(struct mvneta_port *pp) +{ + u32 val; + + /* Reset the Enable bit in the Serial Control Register */ + val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); + val &= ~MVNETA_GMAC0_PORT_ENABLE; + mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); + + udelay(200); +} + +/* Multicast tables methods */ + +/* Set all entries in Unicast MAC Table; queue==-1 means reject all */ +static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) +{ + int offset; + u32 val; + + if (queue == -1) { + val = 0; + } else { + val = 0x1 | (queue << 1); + val |= (val << 24) | (val << 16) | (val << 8); + } + + for (offset = 0; offset <= 0xc; offset += 4) + mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); +} + +/* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ +static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) +{ + int offset; + u32 val; + + if (queue == -1) { + val = 0; + } else { + val = 0x1 | (queue << 1); + val |= (val << 24) | (val << 16) | (val << 8); + } + + for (offset = 0; offset <= 0xfc; offset += 4) + mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); +} + +/* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ +static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) +{ + int offset; + u32 val; + + if (queue == -1) { + memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); + val = 0; + } else { + memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); + val = 0x1 | (queue << 1); + val |= (val << 24) | (val << 16) | (val << 8); + } + + for (offset = 0; offset <= 0xfc; offset += 4) + mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); +} + +/* This method sets defaults to the NETA port: + * Clears interrupt Cause and Mask registers. + * Clears all MAC tables. + * Sets defaults to all registers. + * Resets RX and TX descriptor rings. + * Resets PHY. + * This method can be called after mvneta_port_down() to return the port + * settings to defaults. + */ +static void mvneta_defaults_set(struct mvneta_port *pp) +{ + int cpu; + int queue; + u32 val; + + /* Clear all Cause registers */ + mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); + mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); + mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); + + /* Mask all interrupts */ + mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); + mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); + mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); + mvreg_write(pp, MVNETA_INTR_ENABLE, 0); + + /* Enable MBUS Retry bit16 */ + mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); + + /* Set CPU queue access map - all CPUs have access to all RX + * queues and to all TX queues + */ + for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) + mvreg_write(pp, MVNETA_CPU_MAP(cpu), + (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | + MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); + + /* Reset RX and TX DMAs */ + mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); + mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); + + /* Disable Legacy WRR, Disable EJP, Release from reset */ + mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); + for (queue = 0; queue < txq_number; queue++) { + mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); + mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); + } + + mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); + mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); + + /* Set Port Acceleration Mode */ + val = MVNETA_ACC_MODE_EXT; + mvreg_write(pp, MVNETA_ACC_MODE, val); + + /* Update val of portCfg register accordingly with all RxQueue types */ + val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); + mvreg_write(pp, MVNETA_PORT_CONFIG, val); + + val = 0; + mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); + mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); + + /* Build PORT_SDMA_CONFIG_REG */ + val = 0; + + /* Default burst size */ + val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); + val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); + val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; + + /* Assign port SDMA configuration */ + mvreg_write(pp, MVNETA_SDMA_CONFIG, val); + + /* Enable PHY polling in hardware for U-Boot */ + val = mvreg_read(pp, MVNETA_UNIT_CONTROL); + val |= MVNETA_PHY_POLLING_ENABLE; + mvreg_write(pp, MVNETA_UNIT_CONTROL, val); + + mvneta_set_ucast_table(pp, -1); + mvneta_set_special_mcast_table(pp, -1); + mvneta_set_other_mcast_table(pp, -1); +} + +/* Set unicast address */ +static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, + int queue) +{ + unsigned int unicast_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the Unicast table entry */ + last_nibble = (0xf & last_nibble); + + /* offset from unicast tbl base */ + tbl_offset = (last_nibble / 4) * 4; + + /* offset within the above reg */ + reg_offset = last_nibble % 4; + + unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); + + if (queue == -1) { + /* Clear accepts frame bit at specified unicast DA tbl entry */ + unicast_reg &= ~(0xff << (8 * reg_offset)); + } else { + unicast_reg &= ~(0xff << (8 * reg_offset)); + unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); + } + + mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); +} + +/* Set mac address */ +static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, + int queue) +{ + unsigned int mac_h; + unsigned int mac_l; + + if (queue != -1) { + mac_l = (addr[4] << 8) | (addr[5]); + mac_h = (addr[0] << 24) | (addr[1] << 16) | + (addr[2] << 8) | (addr[3] << 0); + + mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); + mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); + } + + /* Accept frames of this address */ + mvneta_set_ucast_addr(pp, addr[5], queue); +} + +/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ +static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, + u32 phys_addr, u32 cookie) +{ + rx_desc->buf_cookie = cookie; + rx_desc->buf_phys_addr = phys_addr; +} + +/* Decrement sent descriptors counter */ +static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, + struct mvneta_tx_queue *txq, + int sent_desc) +{ + u32 val; + + /* Only 255 TX descriptors can be updated at once */ + while (sent_desc > 0xff) { + val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; + mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); + sent_desc = sent_desc - 0xff; + } + + val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; + mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); +} + +/* Get number of TX descriptors already sent by HW */ +static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, + struct mvneta_tx_queue *txq) +{ + u32 val; + int sent_desc; + + val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); + sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> + MVNETA_TXQ_SENT_DESC_SHIFT; + + return sent_desc; +} + +/* Display more error info */ +static void mvneta_rx_error(struct mvneta_port *pp, + struct mvneta_rx_desc *rx_desc) +{ + u32 status = rx_desc->status; + + if (!mvneta_rxq_desc_is_first_last(status)) { + netdev_err(pp->dev, + "bad rx status %08x (buffer oversize), size=%d\n", + status, rx_desc->data_size); + return; + } + + switch (status & MVNETA_RXD_ERR_CODE_MASK) { + case MVNETA_RXD_ERR_CRC: + netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", + status, rx_desc->data_size); + break; + case MVNETA_RXD_ERR_OVERRUN: + netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", + status, rx_desc->data_size); + break; + case MVNETA_RXD_ERR_LEN: + netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", + status, rx_desc->data_size); + break; + case MVNETA_RXD_ERR_RESOURCE: + netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", + status, rx_desc->data_size); + break; + } +} + +static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, + int rxq) +{ + return &pp->rxqs[rxq]; +} + + +/* Drop packets received by the RXQ and free buffers */ +static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq) +{ + int rx_done; + + rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); + if (rx_done) + mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); +} + +/* Handle rxq fill: allocates rxq skbs; called when initializing a port */ +static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, + int num) +{ + int i; + + for (i = 0; i < num; i++) { + u32 addr; + + /* U-Boot special: Fill in the rx buffer addresses */ + addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE); + mvneta_rx_desc_fill(rxq->descs + i, addr, addr); + } + + /* Add this number of RX descriptors as non occupied (ready to + * get packets) + */ + mvneta_rxq_non_occup_desc_add(pp, rxq, i); + + return 0; +} + +/* Rx/Tx queue initialization/cleanup methods */ + +/* Create a specified RX queue */ +static int mvneta_rxq_init(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq) + +{ + rxq->size = pp->rx_ring_size; + + /* Allocate memory for RX descriptors */ + rxq->descs_phys = (dma_addr_t)rxq->descs; + if (rxq->descs == NULL) + return -ENOMEM; + + rxq->last_desc = rxq->size - 1; + + /* Set Rx descriptors queue starting address */ + mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); + mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); + + /* Fill RXQ with buffers from RX pool */ + mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE); + mvneta_rxq_fill(pp, rxq, rxq->size); + + return 0; +} + +/* Cleanup Rx queue */ +static void mvneta_rxq_deinit(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq) +{ + mvneta_rxq_drop_pkts(pp, rxq); + + rxq->descs = NULL; + rxq->last_desc = 0; + rxq->next_desc_to_proc = 0; + rxq->descs_phys = 0; +} + +/* Create and initialize a tx queue */ +static int mvneta_txq_init(struct mvneta_port *pp, + struct mvneta_tx_queue *txq) +{ + txq->size = pp->tx_ring_size; + + /* Allocate memory for TX descriptors */ + txq->descs_phys = (u32)txq->descs; + if (txq->descs == NULL) + return -ENOMEM; + + txq->last_desc = txq->size - 1; + + /* Set maximum bandwidth for enabled TXQs */ + mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); + mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); + + /* Set Tx descriptors queue starting address */ + mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); + mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); + + return 0; +} + +/* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ +static void mvneta_txq_deinit(struct mvneta_port *pp, + struct mvneta_tx_queue *txq) +{ + txq->descs = NULL; + txq->last_desc = 0; + txq->next_desc_to_proc = 0; + txq->descs_phys = 0; + + /* Set minimum bandwidth for disabled TXQs */ + mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); + mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); + + /* Set Tx descriptors queue starting address and size */ + mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); + mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); +} + +/* Cleanup all Tx queues */ +static void mvneta_cleanup_txqs(struct mvneta_port *pp) +{ + int queue; + + for (queue = 0; queue < txq_number; queue++) + mvneta_txq_deinit(pp, &pp->txqs[queue]); +} + +/* Cleanup all Rx queues */ +static void mvneta_cleanup_rxqs(struct mvneta_port *pp) +{ + int queue; + + for (queue = 0; queue < rxq_number; queue++) + mvneta_rxq_deinit(pp, &pp->rxqs[queue]); +} + + +/* Init all Rx queues */ +static int mvneta_setup_rxqs(struct mvneta_port *pp) +{ + int queue; + + for (queue = 0; queue < rxq_number; queue++) { + int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); + if (err) { + netdev_err(pp->dev, "%s: can't create rxq=%d\n", + __func__, queue); + mvneta_cleanup_rxqs(pp); + return err; + } + } + + return 0; +} + +/* Init all tx queues */ +static int mvneta_setup_txqs(struct mvneta_port *pp) +{ + int queue; + + for (queue = 0; queue < txq_number; queue++) { + int err = mvneta_txq_init(pp, &pp->txqs[queue]); + if (err) { + netdev_err(pp->dev, "%s: can't create txq=%d\n", + __func__, queue); + mvneta_cleanup_txqs(pp); + return err; + } + } + + return 0; +} + +static void mvneta_start_dev(struct mvneta_port *pp) +{ + /* start the Rx/Tx activity */ + mvneta_port_enable(pp); +} + +static void mvneta_adjust_link(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + struct phy_device *phydev = pp->phydev; + int status_change = 0; + + if (phydev->link) { + if ((pp->speed != phydev->speed) || + (pp->duplex != phydev->duplex)) { + u32 val; + + val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); + val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | + MVNETA_GMAC_CONFIG_GMII_SPEED | + MVNETA_GMAC_CONFIG_FULL_DUPLEX | + MVNETA_GMAC_AN_SPEED_EN | + MVNETA_GMAC_AN_DUPLEX_EN); + + if (phydev->duplex) + val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; + + if (phydev->speed == SPEED_1000) + val |= MVNETA_GMAC_CONFIG_GMII_SPEED; + else + val |= MVNETA_GMAC_CONFIG_MII_SPEED; + + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); + + pp->duplex = phydev->duplex; + pp->speed = phydev->speed; + } + } + + if (phydev->link != pp->link) { + if (!phydev->link) { + pp->duplex = -1; + pp->speed = 0; + } + + pp->link = phydev->link; + status_change = 1; + } + + if (status_change) { + if (phydev->link) { + u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); + val |= (MVNETA_GMAC_FORCE_LINK_PASS | + MVNETA_GMAC_FORCE_LINK_DOWN); + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); + mvneta_port_up(pp); + } else { + mvneta_port_down(pp); + } + } +} + +static int mvneta_open(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + int ret; + + ret = mvneta_setup_rxqs(pp); + if (ret) + return ret; + + ret = mvneta_setup_txqs(pp); + if (ret) + return ret; + + mvneta_adjust_link(dev); + + mvneta_start_dev(pp); + + return 0; +} + +/* Initialize hw */ +static int mvneta_init(struct mvneta_port *pp) +{ + int queue; + + /* Disable port */ + mvneta_port_disable(pp); + + /* Set port default values */ + mvneta_defaults_set(pp); + + pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), + GFP_KERNEL); + if (!pp->txqs) + return -ENOMEM; + + /* U-Boot special: use preallocated area */ + pp->txqs[0].descs = buffer_loc.tx_descs; + + /* Initialize TX descriptor rings */ + for (queue = 0; queue < txq_number; queue++) { + struct mvneta_tx_queue *txq = &pp->txqs[queue]; + txq->id = queue; + txq->size = pp->tx_ring_size; + } + + pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), + GFP_KERNEL); + if (!pp->rxqs) { + kfree(pp->txqs); + return -ENOMEM; + } + + /* U-Boot special: use preallocated area */ + pp->rxqs[0].descs = buffer_loc.rx_descs; + + /* Create Rx descriptor rings */ + for (queue = 0; queue < rxq_number; queue++) { + struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; + rxq->id = queue; + rxq->size = pp->rx_ring_size; + } + + return 0; +} + +/* platform glue : initialize decoding windows */ +static void mvneta_conf_mbus_windows(struct mvneta_port *pp) +{ + const struct mbus_dram_target_info *dram; + u32 win_enable; + u32 win_protect; + int i; + + dram = mvebu_mbus_dram_info(); + for (i = 0; i < 6; i++) { + mvreg_write(pp, MVNETA_WIN_BASE(i), 0); + mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); + + if (i < 4) + mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); + } + + win_enable = 0x3f; + win_protect = 0; + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | + (cs->mbus_attr << 8) | dram->mbus_dram_target_id); + + mvreg_write(pp, MVNETA_WIN_SIZE(i), + (cs->size - 1) & 0xffff0000); + + win_enable &= ~(1 << i); + win_protect |= 3 << (2 * i); + } + + mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); +} + +/* Power up the port */ +static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) +{ + u32 ctrl; + + /* MAC Cause register should be cleared */ + mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); + + ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); + + /* Even though it might look weird, when we're configured in + * SGMII or QSGMII mode, the RGMII bit needs to be set. + */ + switch (phy_mode) { + case PHY_INTERFACE_MODE_QSGMII: + mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); + ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; + break; + case PHY_INTERFACE_MODE_SGMII: + mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); + ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + ctrl |= MVNETA_GMAC2_PORT_RGMII; + break; + default: + return -EINVAL; + } + + /* Cancel Port Reset */ + ctrl &= ~MVNETA_GMAC2_PORT_RESET; + mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); + + while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & + MVNETA_GMAC2_PORT_RESET) != 0) + continue; + + return 0; +} + +/* Device initialization routine */ +static int mvneta_probe(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + int err; + + pp->tx_ring_size = MVNETA_MAX_TXD; + pp->rx_ring_size = MVNETA_MAX_RXD; + + err = mvneta_init(pp); + if (err < 0) { + dev_err(&pdev->dev, "can't init eth hal\n"); + return err; + } + + mvneta_conf_mbus_windows(pp); + + mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def); + + err = mvneta_port_power_up(pp, pp->phy_interface); + if (err < 0) { + dev_err(&pdev->dev, "can't power up port\n"); + return err; + } + + /* Call open() now as it needs to be done before runing send() */ + mvneta_open(dev); + + return 0; +} + +/* U-Boot only functions follow here */ + +/* SMI / MDIO functions */ + +static int smi_wait_ready(struct mvneta_port *pp) +{ + u32 timeout = MVNETA_SMI_TIMEOUT; + u32 smi_reg; + + /* wait till the SMI is not busy */ + do { + /* read smi register */ + smi_reg = mvreg_read(pp, MVNETA_SMI); + if (timeout-- == 0) { + printf("Error: SMI busy timeout\n"); + return -EFAULT; + } + } while (smi_reg & MVNETA_SMI_BUSY); + + return 0; +} + +/* + * smi_reg_read - miiphy_read callback function. + * + * Returns 16bit phy register value, or 0xffff on error + */ +static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct mvneta_port *pp = dev->priv; + u32 smi_reg; + u32 timeout; + + /* check parameters */ + if (phy_adr > MVNETA_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", phy_adr); + return -EFAULT; + } + + if (reg_ofs > MVNETA_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg_ofs); + return -EFAULT; + } + + /* wait till the SMI is not busy */ + if (smi_wait_ready(pp) < 0) + return -EFAULT; + + /* fill the phy address and regiser offset and read opcode */ + smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) + | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS) + | MVNETA_SMI_OPCODE_READ; + + /* write the smi register */ + mvreg_write(pp, MVNETA_SMI, smi_reg); + + /*wait till read value is ready */ + timeout = MVNETA_SMI_TIMEOUT; + + do { + /* read smi register */ + smi_reg = mvreg_read(pp, MVNETA_SMI); + if (timeout-- == 0) { + printf("Err: SMI read ready timeout\n"); + return -EFAULT; + } + } while (!(smi_reg & MVNETA_SMI_READ_VALID)); + + /* Wait for the data to update in the SMI register */ + for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) + ; + + *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK); + + return 0; +} + +/* + * smi_reg_write - imiiphy_write callback function. + * + * Returns 0 if write succeed, -EINVAL on bad parameters + * -ETIME on timeout + */ +static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct mvneta_port *pp = dev->priv; + u32 smi_reg; + + /* check parameters */ + if (phy_adr > MVNETA_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", phy_adr); + return -EFAULT; + } + + if (reg_ofs > MVNETA_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg_ofs); + return -EFAULT; + } + + /* wait till the SMI is not busy */ + if (smi_wait_ready(pp) < 0) + return -EFAULT; + + /* fill the phy addr and reg offset and write opcode and data */ + smi_reg = (data << MVNETA_SMI_DATA_OFFS); + smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) + | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS); + smi_reg &= ~MVNETA_SMI_OPCODE_READ; + + /* write the smi register */ + mvreg_write(pp, MVNETA_SMI, smi_reg); + + return 0; +} + +static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) +{ + struct mvneta_port *pp = dev->priv; + struct phy_device *phydev; + + mvneta_port_power_up(pp, pp->phy_interface); + + if (!pp->init || pp->link == 0) { + /* Set phy address of the port */ + mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); + phydev = phy_connect(pp->bus, pp->phyaddr, dev, + pp->phy_interface); + + pp->phydev = phydev; + phy_config(phydev); + phy_startup(phydev); + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return -1; + } + + /* Full init on first call */ + mvneta_probe(dev); + pp->init = 1; + } else { + /* Upon all following calls, this is enough */ + mvneta_port_up(pp); + mvneta_port_enable(pp); + } + + return 0; +} + +static int mvneta_send(struct eth_device *dev, void *ptr, int len) +{ + struct mvneta_port *pp = dev->priv; + struct mvneta_tx_queue *txq = &pp->txqs[0]; + struct mvneta_tx_desc *tx_desc; + int sent_desc; + u32 timeout = 0; + + /* Get a descriptor for the first part of the packet */ + tx_desc = mvneta_txq_next_desc_get(txq); + + tx_desc->buf_phys_addr = (u32)ptr; + tx_desc->data_size = len; + flush_dcache_range((u32)ptr, (u32)ptr + len); + + /* First and Last descriptor */ + tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; + mvneta_txq_pend_desc_add(pp, txq, 1); + + /* Wait for packet to be sent (queue might help with speed here) */ + sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); + while (!sent_desc) { + if (timeout++ > 10000) { + printf("timeout: packet not sent\n"); + return -1; + } + sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); + } + + /* txDone has increased - hw sent packet */ + mvneta_txq_sent_desc_dec(pp, txq, sent_desc); + return 0; + + return 0; +} + +static int mvneta_recv(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + int rx_done; + int packets_done; + struct mvneta_rx_queue *rxq; + + /* get rx queue */ + rxq = mvneta_rxq_handle_get(pp, rxq_def); + rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); + packets_done = rx_done; + + while (packets_done--) { + struct mvneta_rx_desc *rx_desc; + unsigned char *data; + u32 rx_status; + int rx_bytes; + + /* + * No cache invalidation needed here, since the desc's are + * located in a uncached memory region + */ + rx_desc = mvneta_rxq_next_desc_get(rxq); + + rx_status = rx_desc->status; + if (!mvneta_rxq_desc_is_first_last(rx_status) || + (rx_status & MVNETA_RXD_ERR_SUMMARY)) { + mvneta_rx_error(pp, rx_desc); + /* leave the descriptor untouched */ + continue; + } + + /* 2 bytes for marvell header. 4 bytes for crc */ + rx_bytes = rx_desc->data_size - 6; + + /* give packet to stack - skip on first 2 bytes */ + data = (u8 *)rx_desc->buf_cookie + 2; + /* + * No cache invalidation needed here, since the rx_buffer's are + * located in a uncached memory region + */ + NetReceive(data, rx_bytes); + } + + /* Update rxq management counters */ + if (rx_done) + mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); + + return 0; +} + +static void mvneta_halt(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + + mvneta_port_down(pp); + mvneta_port_disable(pp); +} + +int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr) +{ + struct eth_device *dev; + struct mvneta_port *pp; + void *bd_space; + + dev = calloc(1, sizeof(*dev)); + if (dev == NULL) + return -ENOMEM; + + pp = calloc(1, sizeof(*pp)); + if (pp == NULL) + return -ENOMEM; + + dev->priv = pp; + + /* + * Allocate buffer area for descs and rx_buffers. This is only + * done once for all interfaces. As only one interface can + * be active. Make this area DMA save by disabling the D-cache + */ + if (!buffer_loc.tx_descs) { + /* Align buffer area for descs and rx_buffers to 1MiB */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, + DCACHE_OFF); + buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; + buffer_loc.rx_descs = (struct mvneta_rx_desc *) + ((u32)bd_space + + MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); + buffer_loc.rx_buffers = (u32) + (bd_space + + MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + + MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); + } + + sprintf(dev->name, "neta%d", devnum); + + pp->base = (void __iomem *)base_addr; + dev->iobase = base_addr; + dev->init = mvneta_init_u_boot; + dev->halt = mvneta_halt; + dev->send = mvneta_send; + dev->recv = mvneta_recv; + dev->write_hwaddr = NULL; + + /* + * The PHY interface type is configured via the + * board specific CONFIG_SYS_NETA_INTERFACE_TYPE + * define. + */ + pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE; + + eth_register(dev); + + pp->phyaddr = phy_addr; + miiphy_register(dev->name, smi_reg_read, smi_reg_write); + pp->bus = miiphy_get_dev_by_name(dev->name); + + return 1; +} diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index 39391580fe..e6cd3e9ba0 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -228,7 +228,7 @@ int get_prom(u8* mac_addr, u8* base_addr) mdelay (10); - for (i = 0; i < sizeof (program_seq) / sizeof (program_seq[0]); i++) + for (i = 0; i < ARRAY_SIZE(program_seq); i++) n2k_outb (program_seq[i].value, program_seq[i].offset); PRINTK ("PROM:"); diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index df8ab07b94..677c89f048 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -184,7 +184,9 @@ static void nc_send_packet(const char *buf, int len) return; /* inside net loop */ output_packet = buf; output_packet_len = len; + input_recursion = 1; NetLoop(NETCONS); /* wait for arp reply and send packet */ + input_recursion = 0; output_packet_len = 0; return; } @@ -213,7 +215,7 @@ static void nc_send_packet(const char *buf, int len) } } -static int nc_start(void) +static int nc_start(struct stdio_dev *dev) { int retval; @@ -233,7 +235,7 @@ static int nc_start(void) return 0; } -static void nc_putc(char c) +static void nc_putc(struct stdio_dev *dev, char c) { if (output_recursion) return; @@ -244,7 +246,7 @@ static void nc_putc(char c) output_recursion = 0; } -static void nc_puts(const char *s) +static void nc_puts(struct stdio_dev *dev, const char *s) { int len; @@ -254,7 +256,7 @@ static void nc_puts(const char *s) len = strlen(s); while (len) { - int send_len = min(len, sizeof(input_buffer)); + int send_len = min(len, (int)sizeof(input_buffer)); nc_send_packet(s, send_len); len -= send_len; s += send_len; @@ -263,7 +265,7 @@ static void nc_puts(const char *s) output_recursion = 0; } -static int nc_getc(void) +static int nc_getc(struct stdio_dev *dev) { uchar c; @@ -284,7 +286,7 @@ static int nc_getc(void) return c; } -static int nc_tstc(void) +static int nc_tstc(struct stdio_dev *dev) { struct eth_device *eth; diff --git a/drivers/net/nicext.h b/drivers/net/nicext.h deleted file mode 100644 index ff422e7737..0000000000 --- a/drivers/net/nicext.h +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - * - * Name: nicext.h - * - * Description: Broadcom Network Interface Card Extension (NICE) is an - * extension to Linux NET device kernel mode drivers. - * NICE is designed to provide additional functionalities, - * such as receive packet intercept. To support Broadcom NICE, - * the network device driver can be modified by adding an - * device ioctl handler and by indicating receiving packets - * to the NICE receive handler. Broadcom NICE will only be - * enabled by a NICE-aware intermediate driver, such as - * Broadcom Advanced Server Program Driver (BASP). When NICE - * is not enabled, the modified network device drivers - * functions exactly as other non-NICE aware drivers. - * - * Author: Frankie Fan - * - * Created: September 17, 2000 - * - ****************************************************************************/ -#ifndef _nicext_h_ -#define _nicext_h_ - -/* - * ioctl for NICE - */ -#define SIOCNICE SIOCDEVPRIVATE+7 - -/* - * SIOCNICE: - * - * The following structure needs to be less than IFNAMSIZ (16 bytes) because - * we're overloading ifreq.ifr_ifru. - * - * If 16 bytes is not enough, we should consider relaxing this because - * this is no field after ifr_ifru in the ifreq structure. But we may - * run into future compatiability problem in case of changing struct ifreq. - */ -struct nice_req -{ - __u32 cmd; - - union - { -#ifdef __KERNEL__ - /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ - struct - { - void (*nrqus1_rx)( struct sk_buff*, void* ); - void* nrqus1_ctx; - } nrqu_nrqus1; - - /* cmd = NICE_CMD_QUERY_SUPPORT */ - struct - { - __u32 nrqus2_magic; - __u32 nrqus2_support_rx:1; - __u32 nrqus2_support_vlan:1; - __u32 nrqus2_support_get_speed:1; - } nrqu_nrqus2; -#endif - - /* cmd = NICE_CMD_GET_SPEED */ - struct - { - unsigned int nrqus3_speed; /* 0 if link is down, */ - /* otherwise speed in Mbps */ - } nrqu_nrqus3; - - /* cmd = NICE_CMD_BLINK_LED */ - struct - { - unsigned int nrqus4_blink_time; /* blink duration in seconds */ - } nrqu_nrqus4; - - } nrq_nrqu; -}; - -#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx -#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx -#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx -#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic -#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan -#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed -#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed -#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time - -/* - * magic constants - */ -#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */ -#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */ - -/* - * command field - */ -#define NICE_CMD_QUERY_SUPPORT 0x00000001 -#define NICE_CMD_SET_RX 0x00000002 -#define NICE_CMD_GET_RX 0x00000003 -#define NICE_CMD_GET_SPEED 0x00000004 -#define NICE_CMD_BLINK_LED 0x00000005 - -#endif /* _nicext_h_ */ diff --git a/drivers/net/npe/IxEthAcc.c b/drivers/net/npe/IxEthAcc.c deleted file mode 100644 index 7185558955..0000000000 --- a/drivers/net/npe/IxEthAcc.c +++ /dev/null @@ -1,261 +0,0 @@ -/** - * @file IxEthAcc.c - * - * @author Intel Corporation - * @date 20-Feb-2001 - * - * @brief This file contains the implementation of the IXP425 Ethernet Access Component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - - - -#include "IxEthAcc.h" -#ifdef CONFIG_IXP425_COMPONENT_ETHDB -#include "IxEthDB.h" -#endif -#include "IxFeatureCtrl.h" - -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" -#include "IxEthAccMii_p.h" - -/** - * @addtogroup IxEthAcc - *@{ - */ - - -/** - * @brief System-wide information data strucure. - * - * @ingroup IxEthAccPri - * - */ - -IxEthAccInfo ixEthAccDataInfo; -extern PUBLIC IxEthAccMacState ixEthAccMacState[]; -extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex; - -/** - * @brief System-wide information - * - * @ingroup IxEthAccPri - * - */ -BOOL ixEthAccServiceInit = false; - -/* global filtering bit mask */ -PUBLIC UINT32 ixEthAccNewSrcMask; - -/** - * @brief Per port information data strucure. - * - * @ingroup IxEthAccPri - * - */ - -IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS]; - -PUBLIC IxEthAccStatus ixEthAccInit() -{ -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* - * Initialize Control plane - */ - if (ixEthDBInit() != IX_ETH_DB_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } -#endif - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - ixEthAccNewSrcMask = (~0); /* want all the bits */ - } - else - { - ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */ - } - - /* - * Initialize Data plane - */ - if ( ixEthAccInitDataPlane() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - - if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize MII - */ - if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize MAC I/O memory - */ - if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize control plane interface lock - */ - if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* initialiasation is complete */ - ixEthAccServiceInit = true; - - return IX_ETH_ACC_SUCCESS; - -} - -PUBLIC void ixEthAccUnload(void) -{ - IxEthAccPortId portId; - - if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) - { - /* check none of the port is still active */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) - { - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0); - return; - } - } - } - - /* unmap the memory areas */ - ixEthAccMiiUnload(); - ixEthAccMacUnload(); - - /* set all ports as uninitialized */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - ixEthAccPortData[portId].portInitialized = false; - } - - /* uninitialize the service */ - ixEthAccServiceInit = false; - } -} - -PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) -{ - - IxEthAccStatus ret=IX_ETH_ACC_SUCCESS; - - if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) - { - return(IX_ETH_ACC_FAIL); - } - - /* - * Check for valid port - */ - - if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) ) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) - { - /* Already initialized */ - return(IX_ETH_ACC_FAIL); - } - - if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set the port init flag. - */ - - ixEthAccPortData[portId].portInitialized = true; - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* init learning/filtering database structures for this port */ - ixEthDBPortInit(portId); -#endif - - return(ret); -} - - diff --git a/drivers/net/npe/IxEthAccCommon.c b/drivers/net/npe/IxEthAccCommon.c deleted file mode 100644 index b93a8c8a31..0000000000 --- a/drivers/net/npe/IxEthAccCommon.c +++ /dev/null @@ -1,1049 +0,0 @@ -/** - * @file IxEthAccCommon.c - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief This file contains the implementation common support routines for the component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/* - * Component header files - */ - -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthDB.h" -#include "IxNpeMh.h" -#include "IxEthDBPortDefs.h" -#include "IxFeatureCtrl.h" -#include "IxEthAcc_p.h" -#include "IxEthAccQueueAssign_p.h" - -#include "IxEthAccDataPlane_p.h" -#include "IxEthAccMii_p.h" - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -extern IxEthAccInfo ixEthAccDataInfo; - -/** - * - * @brief Maximum number of RX queues set to be the maximum number - * of traffic calsses. - * - */ -#define IX_ETHACC_MAX_RX_QUEUES \ - (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \ - - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \ - + 1) - -/** - * - * @brief Maximum number of 128 entry RX queues - * - */ -#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4 - -/** - * - * @brief Data structure template for Default RX Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = - { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ - "Eth Rx Q", - ixEthRxFrameQMCallback, /**< Functional callback */ - (IxQMgrCallbackId) 0, /**< Callback tag */ - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ - }; - -/** - * - * @brief Data structure template for Small RX Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = - { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ - "Eth Rx Q", - ixEthRxFrameQMCallback, /**< Functional callback */ - (IxQMgrCallbackId) 0, /**< Callback tag */ - IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ - }; - - -/** - * - * @brief Data structure used to register & initialize the Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= -{ - { - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, - "Eth Rx Fr Q 1", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_1, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, - - { - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, - "Eth Rx Fr Q 2", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_2, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#ifdef __ixp46X - { - IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, - "Eth Rx Fr Q 3", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_3, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#endif - { - IX_ETH_ACC_TX_FRAME_ENET0_Q, - "Eth Tx Q 1", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_1, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, - - { - IX_ETH_ACC_TX_FRAME_ENET1_Q, - "Eth Tx Q 2", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_2, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#ifdef __ixp46X - { - IX_ETH_ACC_TX_FRAME_ENET2_Q, - "Eth Tx Q 3", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_3, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */ - false, /** Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ - IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */ - }, -#endif - { - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, - "Eth Tx Done Q", - ixEthTxFrameDoneQMCallback, - (IxQMgrCallbackId) 0, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */ - }, - - { /* Null Termination entry - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - } - -}; - -/** - * - * @brief Data structure used to register & initialize the Queues - * - * The structure will be filled at run time depending on the NPE - * image already loaded and the QoS configured in ethDB. - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]= -{ - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* Null Termination entry - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - } - -}; - -/* forward declarations */ -IX_ETH_ACC_PRIVATE IxEthAccStatus -ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes); - -/** - * @fn ixEthAccQMgrQueueSetup(void) - * - * @brief Setup one queue and its event, and register the callback required - * by this component to the QMgr - * - * @internal - */ -IX_ETH_ACC_PRIVATE IxEthAccStatus -ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes) -{ - /* - * Configure each Q. - */ - if ( ixQMgrQConfig( qInfoDes->qName, - qInfoDes->qId, - qInfoDes->qSize, - qInfoDes->qWords) != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - if ( ixQMgrWatermarkSet( qInfoDes->qId, - qInfoDes->AlmostEmptyThreshold, - qInfoDes->AlmostFullThreshold - ) != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set dispatcher priority. - */ - if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId, - IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY) - != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Register callbacks for each Q. - */ - if ( ixQMgrNotificationCallbackSet(qInfoDes->qId, - qInfoDes->qCallback, - qInfoDes->callbackTag) - != IX_SUCCESS ) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set notification condition for Q - */ - if (qInfoDes->qNotificationEnableAtStartup == true) - { - if ( ixQMgrNotificationEnable(qInfoDes->qId, - qInfoDes->qConditionSource) - != IX_SUCCESS ) - { - return IX_ETH_ACC_FAIL; - } - } - - return(IX_ETH_ACC_SUCCESS); -} - -/** - * @fn ixEthAccQMgrQueuesConfig(void) - * - * @brief Setup all the queues and register all callbacks required - * by this component to the QMgr - * - * The RxFree queues, tx queues, rx queues are configured statically - * - * Rx queues configuration is driven by QoS setup. - * Many Rx queues may be required when QoS is enabled (this depends - * on IxEthDB setup and the images being downloaded). The configuration - * of the rxQueues is done in many steps as follows: - * - * @li select all Rx queues as configured by ethDB for all ports - * @li sort the queues by traffic class - * @li build the priority dependency for all queues - * @li fill the configuration for all rx queues - * @li configure all statically configured queues - * @li configure all dynamically configured queues - * - * @param none - * - * @return IxEthAccStatus - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccQMgrQueuesConfig(void) -{ - struct - { - int npeCount; - UINT32 npeId; - IxQMgrQId qId; - IxEthDBProperty trafficClass; - } rxQueues[IX_ETHACC_MAX_RX_QUEUES]; - - UINT32 rxQueue = 0; - UINT32 rxQueueCount = 0; - IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES; - IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS; - IxEthDBPortId ixEthDbPortId = 0; - IxEthAccPortId ixEthAccPortId = 0; - UINT32 ixNpeId = 0; - UINT32 ixHighestNpeId = 0; - UINT32 sortIterations = 0; - IxEthAccStatus ret = IX_ETH_ACC_SUCCESS; - IxEthAccQregInfo *qInfoDes = NULL; - IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY; - UINT32 ixEthDBParameter = 0; - BOOL completelySorted = false; - - /* Fill the corspondance between ports and queues - * This defines the mapping from port to queue Ids. - */ - - ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q; - ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q; -#endif - ixEthAccPortData[IX_ETH_PORT_1].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET0_Q; - ixEthAccPortData[IX_ETH_PORT_2].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET1_Q; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET2_Q; -#endif - /* Fill the corspondance between ports and NPEs - * This defines the mapping from port to npeIds. - */ - - ixEthAccPortData[IX_ETH_PORT_1].npeId = IX_NPEMH_NPEID_NPEB; - ixEthAccPortData[IX_ETH_PORT_2].npeId = IX_NPEMH_NPEID_NPEC; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].npeId = IX_NPEMH_NPEID_NPEA; -#endif - /* set the default rx scheduling discipline */ - ixEthAccDataInfo.schDiscipline = FIFO_NO_PRIORITY; - - /* - * Queue Selection step: - * - * The following code selects all the queues and build - * a temporary array which contains for each queue - * - the queue Id, - * - the highest traffic class (in case of many - * priorities configured for the same queue on different - * ports) - * - the number of different Npes which are - * configured to write to this queue. - * - * The output of this loop is a temporary array of RX queues - * in any order. - * - */ -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - for (ixEthAccPortId = 0; - (ixEthAccPortId < IX_ETH_ACC_NUMBER_OF_PORTS) - && (ret == IX_ETH_ACC_SUCCESS); - ixEthAccPortId++) - { - /* map between ethDb and ethAcc port Ids */ - ixEthDbPortId = (IxEthDBPortId)ixEthAccPortId; - - /* map between npeId and ethAcc port Ids */ - ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId); - - /* Iterate thru the different priorities */ - for (ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - ixEthDBTrafficClass <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY; - ixEthDBTrafficClass++) - { - ixEthDBStatus = ixEthDBFeaturePropertyGet( - ixEthDbPortId, - IX_ETH_DB_VLAN_QOS, - ixEthDBTrafficClass, - &ixEthDBPropertyType, - (void *)&ixEthDBParameter); - - if (ixEthDBStatus == IX_ETH_DB_SUCCESS) - { - /* This port and QoS class are mapped to - * a RX queue. - */ - if (ixEthDBPropertyType == IX_ETH_DB_INTEGER_PROPERTY) - { - /* remember the highest npe Id supporting ethernet */ - if (ixNpeId > ixHighestNpeId) - { - ixHighestNpeId = ixNpeId; - } - - /* search the queue in the list of queues - * already used by an other port or QoS - */ - for (rxQueue = 0; - rxQueue < rxQueueCount; - rxQueue++) - { - if (rxQueues[rxQueue].qId == (IxQMgrQId)ixEthDBParameter) - { - /* found an existing setup, update the number of ports - * for this queue if the port maps to - * a different NPE. - */ - if (rxQueues[rxQueue].npeId != ixNpeId) - { - rxQueues[rxQueue].npeCount++; - rxQueues[rxQueue].npeId = ixNpeId; - } - /* get the highest traffic class for this queue */ - if (rxQueues[rxQueue].trafficClass > ixEthDBTrafficClass) - { - rxQueues[rxQueue].trafficClass = ixEthDBTrafficClass; - } - break; - } - } - if (rxQueue == rxQueueCount) - { - /* new queue not found in the current list, - * add a new entry. - */ - IX_OSAL_ASSERT(rxQueueCount < IX_ETHACC_MAX_RX_QUEUES); - rxQueues[rxQueueCount].qId = ixEthDBParameter; - rxQueues[rxQueueCount].npeCount = 1; - rxQueues[rxQueueCount].npeId = ixNpeId; - rxQueues[rxQueueCount].trafficClass = ixEthDBTrafficClass; - rxQueueCount++; - } - } - else - { - /* unexpected property type (not Integer) */ - ret = IX_ETH_ACC_FAIL; - - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: unexpected property type returned by EthDB\n", 0, 0, 0, 0, 0, 0); - - /* no point to continue to iterate */ - break; - } - } - else - { - /* No Rx queue configured for this port - * and this traffic class. Do nothing. - */ - } - } - - /* notify EthDB that queue initialization is complete and traffic class allocation is frozen */ - ixEthDBFeaturePropertySet(ixEthDbPortId, - IX_ETH_DB_VLAN_QOS, - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE, - NULL /* ignored */); - } - -#else - - ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId); - rxQueues[0].qId = 4; - rxQueues[0].npeCount = 1; - rxQueues[0].npeId = ixNpeId; - rxQueues[0].trafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - rxQueueCount++; - -#endif - - /* check there is at least 1 rx queue : there is no point - * to continue if there is no rx queue configured - */ - if ((rxQueueCount == 0) || (ret == IX_ETH_ACC_FAIL)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: no queues configured, bailing out\n", 0, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - /* Queue sort step: - * - * Re-order the array of queues by decreasing traffic class - * using a bubble sort. (trafficClass 0 is the lowest - * priority traffic, trafficClass 7 is the highest priority traffic) - * - * Primary sort order is traffic class - * Secondary sort order is npeId - * - * Note that a bubble sort algorithm is not very efficient when - * the number of queues grows . However, this is not a very bad choice - * considering the very small number of entries to sort. Also, bubble - * sort is extremely fast when the list is already sorted. - * - * The output of this loop is a sorted array of queues. - * - */ - sortIterations = 0; - do - { - sortIterations++; - completelySorted = true; - for (rxQueue = 0; - rxQueue < rxQueueCount - sortIterations; - rxQueue++) - { - /* compare adjacent elements */ - if ((rxQueues[rxQueue].trafficClass < - rxQueues[rxQueue+1].trafficClass) - || ((rxQueues[rxQueue].trafficClass == - rxQueues[rxQueue+1].trafficClass) - &&(rxQueues[rxQueue].npeId < - rxQueues[rxQueue+1].npeId))) - { - /* swap adjacent elements */ - int npeCount = rxQueues[rxQueue].npeCount; - UINT32 npeId = rxQueues[rxQueue].npeId; - IxQMgrQId qId = rxQueues[rxQueue].qId; - IxEthDBProperty trafficClass = rxQueues[rxQueue].trafficClass; - rxQueues[rxQueue].npeCount = rxQueues[rxQueue+1].npeCount; - rxQueues[rxQueue].npeId = rxQueues[rxQueue+1].npeId; - rxQueues[rxQueue].qId = rxQueues[rxQueue+1].qId; - rxQueues[rxQueue].trafficClass = rxQueues[rxQueue+1].trafficClass; - rxQueues[rxQueue+1].npeCount = npeCount; - rxQueues[rxQueue+1].npeId = npeId; - rxQueues[rxQueue+1].qId = qId; - rxQueues[rxQueue+1].trafficClass = trafficClass; - completelySorted = false; - } - } - } - while (!completelySorted); - - /* Queue traffic class list: - * - * Fill an array of rx queues linked by ascending traffic classes. - * - * If the queues are configured as follows - * qId 6 -> traffic class 0 (lowest) - * qId 7 -> traffic class 0 - * qId 8 -> traffic class 6 - * qId 12 -> traffic class 7 (highest) - * - * Then the output of this loop will be - * - * higherPriorityQueue[6] = 8 - * higherPriorityQueue[7] = 8 - * higherPriorityQueue[8] = 12 - * higherPriorityQueue[12] = Invalid queueId - * higherPriorityQueue[...] = Invalid queueId - * - * Note that this queue ordering does not handle all possibilities - * that could result from different rules associated with different - * ports, and inconsistencies in the rules. In all cases, the - * output of this algorithm is a simple linked list of queues, - * without closed circuit. - - * This list is implemented as an array with invalid values initialized - * with an "invalid" queue id which is the maximum number of queues. - * - */ - - /* - * Initialise the rx queue list. - */ - for (rxQueue = 0; rxQueue < IX_QMGR_MAX_NUM_QUEUES; rxQueue++) - { - ixEthAccDataInfo.higherPriorityQueue[rxQueue] = IX_QMGR_MAX_NUM_QUEUES; - } - - /* build the linked list for this NPE. - */ - for (ixNpeId = 0; - ixNpeId <= ixHighestNpeId; - ixNpeId++) - { - /* iterate thru the sorted list of queues - */ - ixQId = IX_QMGR_MAX_NUM_QUEUES; - for (rxQueue = 0; - rxQueue < rxQueueCount; - rxQueue++) - { - if (rxQueues[rxQueue].npeId == ixNpeId) - { - ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId; - /* iterate thru queues with the same traffic class - * than the current queue. (queues are ordered by descending - * traffic classes and npeIds). - */ - while ((rxQueue < rxQueueCount - 1) - && (rxQueues[rxQueue].trafficClass - == rxQueues[rxQueue+1].trafficClass) - && (ixNpeId == rxQueues[rxQueue].npeId)) - { - rxQueue++; - ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId; - } - ixQId = rxQueues[rxQueue].qId; - } - } - } - - /* point on the first dynamic queue description */ - qInfoDes = ixEthAccQmgrRxQueuesInfo; - - /* update the list of queues with the rx queues */ - for (rxQueue = 0; - (rxQueue < rxQueueCount) && (ret == IX_ETH_ACC_SUCCESS); - rxQueue++) - { - /* Don't utilize more than IX_ETHACC_MAX_LARGE_RX_QUEUES queues - * with the full 128 entries. For the lower priority queues, use - * a smaller number of entries. This ensures queue resources - * remain available for other components. - */ - if( (rxQueueCount > IX_ETHACC_MAX_LARGE_RX_QUEUES) && - (rxQueue < rxQueueCount - IX_ETHACC_MAX_LARGE_RX_QUEUES) ) - { - /* add the small RX Queue setup template to the list of queues */ - memcpy(qInfoDes, &ixEthAccQmgrRxSmallTemplate, sizeof(*qInfoDes)); - } else { - /* add the default RX Queue setup template to the list of queues */ - memcpy(qInfoDes, &ixEthAccQmgrRxDefaultTemplate, sizeof(*qInfoDes)); - } - - /* setup the RxQueue ID */ - qInfoDes->qId = rxQueues[rxQueue].qId; - - /* setup the RxQueue watermark level - * - * Each queue can be filled by many NPEs. To avoid the - * NPEs to write to a full queue, need to set the - * high watermark level for nearly full condition. - * (the high watermark level are a power of 2 - * starting from the top of the queue) - * - * Number of watermark - * ports level - * 1 0 - * 2 1 - * 3 2 - * 4 4 - * 5 4 - * 6 8 - * n approx. 2**ceil(log2(n)) - */ - if (rxQueues[rxQueue].npeCount == 1) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL0; - } - else if (rxQueues[rxQueue].npeCount == 2) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL1; - } - else if (rxQueues[rxQueue].npeCount == 3) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL2; - } - else - { - /* reach the maximum number for CSR 2.0 */ - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: maximum number of NPEs per queue reached, bailing out\n", 0, 0, 0, 0, 0, 0); - ret = IX_ETH_ACC_FAIL; - break; - } - - /* move to next queue entry */ - ++qInfoDes; - } - - /* configure the static list (RxFree, Tx and TxDone queues) */ - for (qInfoDes = ixEthAccQmgrStaticInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - ret = ixEthAccQMgrQueueSetup(qInfoDes); - } - - /* configure the dynamic list (Rx queues) */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - ret = ixEthAccQMgrQueueSetup(qInfoDes); - } - - return(ret); -} - -/** - * @fn ixEthAccQMgrRxQEntryGet(UINT32 *rxQueueEntries) - * - * @brief Add and return the total number of entries in all Rx queues - * - * @param UINT32 rxQueueEntries[in] number of entries in all queues - * - * @return void - * - * @note Rx queues configuration is driven by Qos Setup. There is a - * variable number of rx queues which are set at initialisation. - * - * @internal - */ -IX_ETH_ACC_PUBLIC -void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries) -{ - UINT32 rxQueueLevel; - IxEthAccQregInfo *qInfoDes;; - - *numRxQueueEntries = 0; - - /* iterate thru rx queues */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - qInfoDes->qCallback != (IxQMgrCallback)NULL; - ++qInfoDes) - { - /* retrieve the rx queue level */ - rxQueueLevel = 0; - ixQMgrQNumEntriesGet(qInfoDes->qId, &rxQueueLevel); - (*numRxQueueEntries) += rxQueueLevel; - } -} - -/** - * @fn ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback) - * - * @brief Change the callback registered to all rx queues. - * - * @param IxQMgrCallback ixQMgrCallback[in] QMgr callback to register - * - * @return IxEthAccStatus - * - * @note The user may decide to use different Rx mechanisms - * (e.g. receive many frames at the same time , or receive - * one frame at a time, depending on the overall application - * performances). A different QMgr callback is registered. This - * way, there is no excessive pointer checks in the datapath. - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback) -{ - IxEthAccQregInfo *qInfoDes; - IxEthAccStatus ret = IX_ETH_ACC_SUCCESS; - - /* parameter check */ - if (NULL == ixQMgrCallback) - { - ret = IX_ETH_ACC_FAIL; - } - - /* iterate thru rx queues */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - /* register the rx callback for all queues */ - if (ixQMgrNotificationCallbackSet(qInfoDes->qId, - ixQMgrCallback, - qInfoDes->callbackTag - ) != IX_SUCCESS) - { - ret = IX_ETH_ACC_FAIL; - } - } - return(ret); -} - -/** - * @fn ixEthAccSingleEthNpeCheck(IxEthAccPortId portId) - * - * @brief Check the npe exists for this port - * - * @param IxEthAccPortId portId[in] port - * - * @return IxEthAccStatus - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId) -{ - - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((IX_ETH_PORT_1 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - if ((IX_ETH_PORT_2 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - if ((IX_ETH_PORT_3 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -/** - * @fn ixEthAccStatsShow(void) - * - * @brief Displays all EthAcc stats - * - * @return void - * - */ -void ixEthAccStatsShow(IxEthAccPortId portId) -{ - ixEthAccMdioShow(); - - printf("\nPort %u\nUnicast MAC : ", portId); - ixEthAccPortUnicastAddressShow(portId); - ixEthAccPortMulticastAddressShow(portId); - printf("\n"); - - ixEthAccDataPlaneShow(); -} - - - diff --git a/drivers/net/npe/IxEthAccControlInterface.c b/drivers/net/npe/IxEthAccControlInterface.c deleted file mode 100644 index 44328473e6..0000000000 --- a/drivers/net/npe/IxEthAccControlInterface.c +++ /dev/null @@ -1,533 +0,0 @@ -/** - * @file IxEthAccControlInterface.c - * - * @author Intel Corporation - * @date - * - * @brief IX_ETH_ACC_PUBLIC wrappers for control plane functions - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthAcc_p.h" - -PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex; - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: (Mac) cannot enable port %d, service not initialized\n", portId); - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - /* check the context is iinitialized */ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortEnabledQueryPriv(portId, enabled); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortPromiscuousModeClearPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortPromiscuousModeSetPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastMacAddressSetPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastMacAddressGetPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressJoinPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressJoinAllPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressLeavePriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressLeaveAllPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastAddressShow(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastAddressShowPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC void -ixEthAccPortMulticastAddressShow(IxEthAccPortId portId) -{ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return; - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - ixEthAccPortMulticastAddressShowPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeSet(IxEthAccPortId portId, IxEthAccDuplexMode mode) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDuplexModeSetPriv(portId, mode); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeGet(IxEthAccPortId portId, IxEthAccDuplexMode *mode) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDuplexModeGetPriv(portId, mode); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendPaddingEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendPaddingDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendFCSEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendFCSDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxFrameAppendFCSEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxFrameAppendFCSDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccTxSchedulingDisciplineSetPriv(portId, sched); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccRxSchedulingDisciplineSetPriv(sched); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccNpeLoopbackEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccNpeLoopbackDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMacReset(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMacResetPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} diff --git a/drivers/net/npe/IxEthAccDataPlane.c b/drivers/net/npe/IxEthAccDataPlane.c deleted file mode 100644 index 6df3307e5d..0000000000 --- a/drivers/net/npe/IxEthAccDataPlane.c +++ /dev/null @@ -1,2483 +0,0 @@ -/** - * @file IxEthDataPlane.c - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief This file contains the implementation of the IXPxxx - * Ethernet Access Data plane component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxNpeMh.h" -#include "IxEthAcc.h" -#include "IxEthDB.h" -#include "IxOsal.h" -#include "IxEthDBPortDefs.h" -#include "IxFeatureCtrl.h" -#include "IxEthAcc_p.h" -#include "IxEthAccQueueAssign_p.h" - -extern PUBLIC IxEthAccMacState ixEthAccMacState[]; -extern PUBLIC UINT32 ixEthAccNewSrcMask; - -/** - * private functions prototype - */ -PRIVATE IX_OSAL_MBUF * -ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask); - -PRIVATE UINT32 -ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf); - -PRIVATE UINT32 -ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf); - -PRIVATE IxEthAccStatus -ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId, - IxEthAccTxPriority *priorityPtr); - -PRIVATE IxEthAccStatus -ixEthAccTxFromSwQ(IxEthAccPortId portId, - IxEthAccTxPriority priority); - -PRIVATE IxEthAccStatus -ixEthAccRxFreeFromSwQ(IxEthAccPortId portId); - -PRIVATE void -ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf); - -PRIVATE IX_STATUS -ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, - UINT32 qBuffer); - -PRIVATE IX_STATUS -ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, - UINT32 qBuffer); - -PRIVATE IX_STATUS -ixEthAccQmgrTxWrite(IxEthAccPortId portId, - UINT32 qBuffer, - UINT32 priority); - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* increment a counter only when stats are enabled */ -#define TX_STATS_INC(port,field) \ - IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field) -#define RX_STATS_INC(port,field) \ - IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field) - -/* always increment the counter (mainly used for unexpected errors) */ -#define TX_INC(port,field) \ - ixEthAccPortData[port].ixEthAccTxData.stats.field++ -#define RX_INC(port,field) \ - ixEthAccPortData[port].ixEthAccRxData.stats.field++ - -PRIVATE IxEthAccDataPlaneStats ixEthAccDataStats; - -extern IxEthAccPortDataInfo ixEthAccPortData[]; -extern IxEthAccInfo ixEthAccDataInfo; - -PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS]; -PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/** - * - * @brief Mbuf header conversion macros : they implement the - * different conversions using a temporary value. They also double-check - * that the parameters can be converted to/from NPE format. - * - */ -#if defined(__wince) && !defined(IN_KERNEL) -#define PTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#define PTR_NPE2VIRT(type,src,ptrDst) \ - do { void *temp; \ - IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \ - (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \ - while(0) -#else -#define PTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#define PTR_NPE2VIRT(type,src,ptrDst) \ - do { void *temp; \ - IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \ - (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \ - while(0) -#endif - -/** - * - * @brief Mbuf payload pointer conversion macros : Wince has its own - * method to convert the buffer pointers - */ -#if defined(__wince) && !defined(IN_KERNEL) -#define DATAPTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#else -#define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst) -#endif - - -/* Flush the shared part of the mbuf header */ -#define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \ - do { \ - IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \ - sizeof(IxEthAccNe)); \ - } \ - while(0) - -/* Invalidate the shared part of the mbuf header */ -#define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \ - do { \ - IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \ - sizeof(IxEthAccNe)); \ - } \ - while(0) - -/* Preload one cache line (shared mbuf headers are aligned - * and their size is 1 cache line) - * - * IX_OSAL_CACHED is defined when the mbuf headers are - * allocated from cached memory. - * - * Other processor on emulation environment may not implement - * preload function - */ -#ifdef IX_OSAL_CACHED - #if (CPU!=SIMSPARCSOLARIS) && !defined (__wince) - #define IX_ACC_DATA_CACHE_PRELOAD(ptr) \ - do { /* preload a cache line (Xscale Processor) */ \ - __asm__ (" pld [%0]\n": : "r" (ptr)); \ - } \ - while(0) - #else - /* preload not implemented on different processor */ - #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \ - do { /* nothing */ } while (0) - #endif -#else - /* preload not needed if cache is not enabled */ - #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \ - do { /* nothing */ } while (0) -#endif - -/** - * - * @brief function to retrieve the correct pointer from - * a queue entry posted by the NPE - * - * @param qEntry : entry from qmgr queue - * mask : applicable mask for this queue - * (4 most significant bits are used for additional informations) - * - * @return IX_OSAL_MBUF * pointer to mbuf header - * - * @internal - */ -PRIVATE IX_OSAL_MBUF * -ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask) -{ - IX_OSAL_MBUF *mbufPtr; - - if (qEntry != 0) - { - /* mask NPE bits (e.g. priority, port ...) */ - qEntry &= mask; - -#if IX_ACC_DRAM_PHYS_OFFSET != 0 - /* restore the original address pointer (if PHYS_OFFSET is not 0) */ - qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); -#endif - /* get the mbuf pointer address from the npe-shared address */ - qEntry -= offsetof(IX_OSAL_MBUF,ix_ne); - - /* phys2virt mbuf */ - mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry); - - /* preload the cacheline shared with NPE */ - IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr)); - - /* preload the cacheline used by xscale */ - IX_ACC_DATA_CACHE_PRELOAD(mbufPtr); - } - else - { - mbufPtr = NULL; - } - - return mbufPtr; -} - -/* Convert the mbuf header for NPE transmission */ -PRIVATE UINT32 -ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf) -{ - UINT32 qbuf; - UINT32 len; - - /* endianess swap for tci and flags - note: this is done only once, even for chained buffers */ - IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf)); - IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf)); - - /* test for unchained mbufs */ - if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL) - { - /* "best case" scenario : unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs); - - /* payload pointer conversion */ - DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf)); - - /* unchained mbufs : the frame length is the mbuf length - * and the 2 identical lengths are stored in the same - * word. - */ - len = IX_OSAL_MBUF_MLEN(mbuf); - - /* set the length in both length and pktLen 16-bits fields */ - len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* unchained mbufs : next contains 0 */ - IX_ETHACC_NE_NEXT(mbuf) = 0; - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(mbuf); - } - else - { - /* chained mbufs */ - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - UINT32 frmLen; - - /* get the frame length from the header of the first buffer */ - frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf); - - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs); - - /* payload pointer */ - DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr)); - /* Buffer length and frame length are stored in the same word */ - len = IX_OSAL_MBUF_MLEN(ptr); - len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* get the virtual next chain pointer */ - nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - if (nextPtr != NULL) - { - /* shared pointer of the next buffer is chained */ - PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr), - IX_ETHACC_NE_NEXT(ptr)); - } - else - { - IX_ETHACC_NE_NEXT(ptr) = 0; - } - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(ptr); - - /* move to next buffer */ - ptr = nextPtr; - - /* the frame length field is set only in the first buffer - * and is zeroed in the next buffers - */ - frmLen = 0; - } - while(ptr != NULL); - - } - - /* virt2phys mbuf itself */ - qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS( - IX_ETHACC_NE_SHARED(mbuf)); - - /* Ensure the bits which are reserved to exchange information with - * the NPE are cleared - * - * If the mbuf address is not correctly aligned, or from an - * incompatible memory range, there is no point to continue - */ - IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0), - "Invalid address range"); - - return qbuf; -} - -/* Convert the mbuf header for NPE reception */ -PRIVATE UINT32 -ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf) -{ - UINT32 len; - UINT32 qbuf; - - if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL) - { - /* "best case" scenario : unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs); - - /* unchained mbufs : payload pointer */ - DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf)); - - /* unchained mbufs : set the buffer length - * and the frame length field is zeroed - */ - len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* unchained mbufs : next pointer is null */ - IX_ETHACC_NE_NEXT(mbuf) = 0; - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(mbuf); - - /* remove shared header cache line */ - IX_ETHACC_NE_CACHE_INVALIDATE(mbuf); - } - else - { - /* chained mbufs */ - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - - do - { - /* chained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs); - - /* we must save virtual next chain pointer */ - nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - - if (nextPtr != NULL) - { - /* chaining pointer for NPE */ - PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr), - IX_ETHACC_NE_NEXT(ptr)); - } - else - { - IX_ETHACC_NE_NEXT(ptr) = 0; - } - - /* payload pointer */ - DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr)); - - /* buffer length */ - len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(ptr); - - /* remove shared header cache line */ - IX_ETHACC_NE_CACHE_INVALIDATE(ptr); - - /* next mbuf in the chain */ - ptr = nextPtr; - } - while(ptr != NULL); - } - - /* virt2phys mbuf itself */ - qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS( - IX_ETHACC_NE_SHARED(mbuf)); - - /* Ensure the bits which are reserved to exchange information with - * the NPE are cleared - * - * If the mbuf address is not correctly aligned, or from an - * incompatible memory range, there is no point to continue - */ - IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0), - "Invalid address range"); - - return qbuf; -} - -/* Convert the mbuf header after NPE transmission - * Since there is nothing changed by the NPE, there is no need - * to process anything but the update of internal stats - * when they are enabled -*/ -PRIVATE void -ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf) -{ -#ifndef NDEBUG - /* test for unchained mbufs */ - if (IX_ETHACC_NE_NEXT(mbuf) == 0) - { - /* unchained mbufs : update the stats */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs); - } - else - { - /* chained mbufs : walk the chain and update the stats */ - IX_OSAL_MBUF *ptr = mbuf; - - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs); - ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - } - while (ptr != NULL); - } -#endif -} - -/* Convert the mbuf header after NPE reception */ -PRIVATE void -ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf) -{ - UINT32 len; - - /* endianess swap for tci and flags - note: this is done only once, even for chained buffers */ - IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf)); - IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf)); - - /* test for unchained mbufs */ - if (IX_ETHACC_NE_NEXT(mbuf) == 0) - { - /* unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs); - - /* get the frame length. it is the same than the buffer length */ - len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf)); - len &= IX_ETHNPE_ACC_PKTLENGTH_MASK; - IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len; - - /* clears the next packet field */ - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL; - } - else - { - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - UINT32 frmLen; - - /* convert the frame length */ - frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf)); - IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK); - - /* chained mbufs */ - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs); - - /* convert the length */ - len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr)); - IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET); - - /* get the next pointer */ - PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr); - if (nextPtr != NULL) - { - nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne)); - } - /* set the next pointer */ - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr; - - /* move to the next buffer */ - ptr = nextPtr; - } - while (ptr != NULL); - } -} - -/* write to qmgr if possible and report an overflow if not possible - * Use a fast lock to protect the queue write. - * This way, the tx feature is reentrant. - */ -PRIVATE IX_STATUS -ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer) -{ - IX_STATUS qStatus; - if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS) - { - qStatus = ixQMgrQWrite( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - &qBuffer); -#ifndef NDEBUG - if (qStatus != IX_SUCCESS) - { - TX_STATS_INC(portId, txOverflow); - } -#endif - ixOsalFastMutexUnlock(&txWriteMutex[portId]); - } - else - { - TX_STATS_INC(portId, txLock); - qStatus = IX_QMGR_Q_OVERFLOW; - } - return qStatus; -} - -/* write to qmgr if possible and report an overflow if not possible - * Use a fast lock to protect the queue write. - * This way, the Rx feature is reentrant. - */ -PRIVATE IX_STATUS -ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer) -{ - IX_STATUS qStatus; - if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS) - { - qStatus = ixQMgrQWrite( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId), - &qBuffer); -#ifndef NDEBUG - if (qStatus != IX_SUCCESS) - { - RX_STATS_INC(portId, rxFreeOverflow); - } -#endif - ixOsalFastMutexUnlock(&rxWriteMutex[portId]); - } - else - { - RX_STATS_INC(portId, rxFreeLock); - qStatus = IX_QMGR_Q_OVERFLOW; - } - return qStatus; -} - -/* - * Set the priority and write to a qmgr queue. - */ -PRIVATE IX_STATUS -ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority) -{ - /* fill the priority field */ - qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R); - - return ixEthAccQmgrLockTxWrite(portId, qBuffer); -} - -/** - * - * @brief This function will discover the highest priority S/W Tx Q that - * has entries in it - * - * @param portId - (in) the id of the port whose S/W Tx queues are to be searched - * priorityPtr - (out) the priority of the highest priority occupied q will be written - * here - * - * @return IX_ETH_ACC_SUCCESS if an occupied Q is found - * IX_ETH_ACC_FAIL if no Q has entries - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId, - IxEthAccTxPriority *priorityPtr) -{ - if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline - == FIFO_NO_PRIORITY) - { - if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY])) - { - return IX_ETH_ACC_FAIL; - } - else - { - *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY; - TX_STATS_INC(portId,txPriority[*priorityPtr]); - return IX_ETH_ACC_SUCCESS; - } - } - else - { - IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7; - while(1) - { - if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccTxData.txQ[highestPriority])) - { - - *priorityPtr = highestPriority; - TX_STATS_INC(portId,txPriority[highestPriority]); - return IX_ETH_ACC_SUCCESS; - - } - if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0) - { - return IX_ETH_ACC_FAIL; - } - highestPriority--; - } - } -} - -/** - * - * @brief This function will take a buffer from a TX S/W Q and attempt - * to add it to the relevant TX H/W Q - * - * @param portId - the port whose TX queue is to be written to - * priority - identifies the queue from which the entry is to be read - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccTxFromSwQ(IxEthAccPortId portId, - IxEthAccTxPriority priority) -{ - IX_OSAL_MBUF *mbuf; - IX_STATUS qStatus; - - IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority"); - - IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - if (mbuf != NULL) - { - /* - * Add the Tx buffer to the H/W Tx Q - * We do not need to flush here as it is already done - * in TxFrameSubmit(). - */ - qStatus = ixEthAccQmgrTxWrite( - portId, - IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)), - priority); - - if (qStatus == IX_SUCCESS) - { - TX_STATS_INC(portId,txFromSwQOK); - return IX_SUCCESS; - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * H/W Q overflow, need to save the buffer - * back on the s/w Q. - * we must put it back on the head of the q to avoid - * reordering packet tx - */ - TX_STATS_INC(portId,txFromSwQDelayed); - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - /*enable Q notification*/ - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING) - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccTxFromSwQ:Unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - TX_INC(portId,txUnexpectedError); - - /* recovery attempt */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - IX_ETH_ACC_FATAL_LOG( - "ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - /* sw queue is empty */ - } - return IX_ETH_ACC_FAIL; -} - -/** - * - * @brief This function will take a buffer from a RXfree S/W Q and attempt - * to add it to the relevant RxFree H/W Q - * - * @param portId - the port whose RXFree queue is to be written to - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccRxFreeFromSwQ(IxEthAccPortId portId) -{ - IX_OSAL_MBUF *mbuf; - IX_STATUS qStatus = IX_SUCCESS; - - IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - if (mbuf != NULL) - { - /* - * Add The Rx Buffer to the H/W Free buffer Q if possible - */ - qStatus = ixEthAccQmgrLockRxWrite(portId, - IX_OSAL_MMU_VIRT_TO_PHYS( - (UINT32)IX_ETHACC_NE_SHARED(mbuf))); - - if (qStatus == IX_SUCCESS) - { - RX_STATS_INC(portId,rxFreeRepFromSwQOK); - /* - * Buffer added to h/w Q. - */ - return IX_SUCCESS; - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * H/W Q overflow, need to save the buffer back on the s/w Q. - */ - RX_STATS_INC(portId,rxFreeRepFromSwQDelayed); - - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - } - else - { - /* unexpected qmgr error */ - RX_INC(portId,rxUnexpectedError); - - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - - IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - /* sw queue is empty */ - } - return IX_ETH_ACC_FAIL; -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccInitDataPlane() -{ - UINT32 portId; - - /* - * Initialize the service and register callback to other services. - */ - - IX_ETH_ACC_MEMSET(&ixEthAccDataStats, - 0, - sizeof(ixEthAccDataStats)); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - ixOsalFastMutexInit(&txWriteMutex[portId]); - ixOsalFastMutexInit(&rxWriteMutex[portId]); - - IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId], - 0, - sizeof(ixEthAccPortData[portId])); - - ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY; - } - - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId, - IxEthAccPortTxDoneCallback - txCallbackFn, - UINT32 callbackTag) -{ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - -/* HACK: removing this code to enable NPE-A preliminary testing - * if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - * { - * IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0); - * return IX_ETH_ACC_SUCCESS ; - * } - */ - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - if (txCallbackFn == 0) - /* Check for null function pointer here. */ - { - return (IX_ETH_ACC_INVALID_ARG); - } - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag; - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortRxCallback - rxCallbackFn, - UINT32 callbackTag) -{ - IxEthAccPortId port; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* Check for null function pointer here. */ - if (rxCallbackFn == NULL) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - /* Check the user is not changing the callback type - * when the port is enabled. - */ - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) - { - if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true)) - { - /* one of the active ports has a different rx callback type. - * Changing the callback type when the port is enabled - * is not safe - */ - return (IX_ETH_ACC_INVALID_ARG); - } - } - } - - /* update the callback pointer : this is done before - * registering the new qmgr callback - */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag; - - /* update the qmgr callback for rx queues */ - if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback) - != IX_ETH_ACC_SUCCESS) - { - /* unexpected qmgr error */ - IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \ - "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0); - - RX_INC(portId,rxUnexpectedError); - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false; - - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister( - IxEthAccPortId portId, - IxEthAccPortMultiBufferRxCallback - rxCallbackFn, - UINT32 callbackTag) -{ - IxEthAccPortId port; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* Check for null function pointer here. */ - if (rxCallbackFn == NULL) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - /* Check the user is not changing the callback type - * when the port is enabled. - */ - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) - { - if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false)) - { - /* one of the active ports has a different rx callback type. - * Changing the callback type when the port is enabled - * is not safe - */ - return (IX_ETH_ACC_INVALID_ARG); - } - } - } - - /* update the callback pointer : this is done before - * registering the new qmgr callback - */ - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag; - - /* update the qmgr callback for rx queues */ - if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback) - != IX_ETH_ACC_SUCCESS) - { - /* unexpected qmgr error */ - RX_INC(portId,rxUnexpectedError); - - IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \ - "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0); - - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true; - - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority) -{ - IX_STATUS qStatus = IX_SUCCESS; - UINT32 qBuffer; - IxEthAccTxPriority highestPriority; - IxQMgrQStatus txQStatus; - -#ifndef NDEBUG - if (buffer == NULL) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n", - (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_PORT_UNINITIALIZED ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7) - { - return (IX_ETH_ACC_INVALID_ARG); - } -#endif - - /* - * Need to Flush the MBUF and its contents (data) as it may be - * read from the NPE. Convert virtual addresses to physical addresses also. - */ - qBuffer = ixEthAccMbufTxQPrepare(buffer); - - /* - * If no fifo priority set on Xscale ... - */ - if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_NO_PRIORITY) - { - /* - * Add The Tx Buffer to the H/W Tx Q if possible - * (the priority is passed to the NPE, because - * the NPE is able to reorder the frames - * before transmission to the underlying hardware) - */ - qStatus = ixEthAccQmgrTxWrite(portId, - qBuffer, - IX_ETH_ACC_TX_DEFAULT_PRIORITY); - - if (qStatus == IX_SUCCESS) - { - TX_STATS_INC(portId,txQOK); - - /* - * "best case" scenario : Buffer added to h/w Q. - */ - return (IX_SUCCESS); - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * We were unable to write the buffer to the - * appropriate H/W Q, Save it in the sw Q. - * (use the default priority queue regardless of - * input parameter) - */ - priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY; - } - else - { - /* unexpected qmgr error */ - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n", - (UINT32)qStatus, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - } - else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_PRIORITY) - { - - /* - * For priority transmission, put the frame directly on the H/W queue - * if the H/W queue is empty, otherwise, put it in a S/W Q - */ - ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus); - if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0) - { - /*The tx queue is empty, check whether there are buffers on the s/w queues*/ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - /*there are buffers on the s/w queues, submit them*/ - ixEthAccTxFromSwQ(portId, highestPriority); - - /* the queue was empty, 1 buffer is already supplied - * but is likely to be immediately transmitted and the - * hw queue is likely to be empty again, so submit - * more from the sw queues - */ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - ixEthAccTxFromSwQ(portId, highestPriority); - /* - * and force the buffer supplied to be placed - * on a priority queue - */ - qStatus = IX_QMGR_Q_OVERFLOW; - } - else - { - /*there are no buffers in the s/w queues, submit directly*/ - qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority); - } - } - else - { - /*there are no buffers in the s/w queues, submit directly*/ - qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority); - } - } - else - { - qStatus = IX_QMGR_Q_OVERFLOW; - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n", - 0, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - if(qStatus == IX_SUCCESS ) - { - TX_STATS_INC(portId,txQOK); - return IX_ETH_ACC_SUCCESS; - } - else if(qStatus == IX_QMGR_Q_OVERFLOW) - { - TX_STATS_INC(portId,txQDelayed); - /* - * We were unable to write the buffer to the - * appropriate H/W Q, Save it in a s/w Q. - */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL( - ixEthAccPortData[portId]. - ixEthAccTxData.txQ[priority], - buffer); - - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS) - { - if (qStatus == IX_QMGR_WARNING) - { - /* notification is enabled for a queue - * which is already empty (the condition is already met) - * and there will be no more queue event to drain the sw queue - */ - TX_STATS_INC(portId,txLateNotificationEnabled); - - /* pull a buffer from the sw queue */ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - /*there are buffers on the s/w queues, submit from them*/ - ixEthAccTxFromSwQ(portId, highestPriority); - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - return (IX_ETH_ACC_SUCCESS); -} - - -/** - * - * @brief replenish: convert a chain of mbufs to the format - * expected by the NPE - * - */ - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId, - IX_OSAL_MBUF *buffer) -{ - IX_STATUS qStatus = IX_SUCCESS; - UINT32 qBuffer; - - /* - * Check buffer is valid. - */ - -#ifndef NDEBUG - /* check parameter value */ - if (buffer == 0) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - /* check initialisation is done */ - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_PORT_UNINITIALIZED ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - /* check boundaries and constraints */ - if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN) - { - return (IX_ETH_ACC_FAIL); - } -#endif - - qBuffer = ixEthAccMbufRxQPrepare(buffer); - - /* - * Add The Rx Buffer to the H/W Free buffer Q if possible - */ - qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer); - - if (qStatus == IX_SUCCESS) - { - RX_STATS_INC(portId,rxFreeRepOK); - /* - * Buffer added to h/w Q. - */ - return (IX_SUCCESS); - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - RX_STATS_INC(portId,rxFreeRepDelayed); - /* - * We were unable to write the buffer to the approprate H/W Q, - * Save it in a s/w Q. - */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - buffer); - - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId), - IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS) - { - if (qStatus == IX_QMGR_WARNING) - { - /* notification is enabled for a queue - * which is already empty (the condition is already met) - * and there will be no more queue event to drain the sw queue - * move an entry from the sw queue to the hw queue */ - RX_STATS_INC(portId,rxFreeLateNotificationEnabled); - ixEthAccRxFreeFromSwQ(portId); - } - else - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccRxPortFreeReplenish:Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - } - else - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n", - (UINT32)qStatus, 0, 0, 0, 0, 0); - return(IX_ETH_ACC_FAIL); - } - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, - IxEthAccSchedulerDiscipline - sched) -{ - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched; - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline - sched) -{ - if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccDataInfo.schDiscipline = sched; - - return (IX_ETH_ACC_SUCCESS); -} - - -/** - * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) - * - * @brief process incoming frame : - * - * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback - * - * @return none - * - * @internal - * - */ -IX_ETH_ACC_PRIVATE BOOL -ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) -{ - UINT32 flags; - IxEthDBStatus result; - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameProcess: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return false; - } -#endif - - /* convert fields from mbuf header */ - ixEthAccMbufFromRxQ(mbufPtr); - - /* check about any special processing for this frame */ - flags = IX_ETHACC_NE_FLAGS(mbufPtr); - if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0) - { - /* "best case" scenario : nothing special to do for this frame */ - return true; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* if a new source MAC address is detected by the NPE, - * update IxEthDB with the portId and the MAC address. - */ - if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0) - { - result = ixEthDBFilteringDynamicEntryProvision(portId, - (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr)); - - if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE) - { - if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY)) - { - RX_STATS_INC(portId, rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \ - to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0); - } - else - { - /* we expect this to fail during PortDisable, as EthDB is disabled for - * that port and will refuse to learn new addresses - */ - } - } - else - { - RX_STATS_INC(portId, rxUnlearnedMacAddress); - } - } -#endif - - /* check if this frame should have been filtered - * by the NPE and take the appropriate action - */ - if (((flags & IX_ETHACC_NE_FILTERMASK) != 0) - && (ixEthAccMacState[portId].portDisableState == ACTIVE)) - { - /* If the mbuf was allocated with a small data size, or the current data pointer is not - * within the allocated data area, then the buffer is non-standard and has to be - * replenished with the minimum size only - */ - if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN) - || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr)) - || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) + - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr)) - < IX_OSAL_MBUF_MDATA(mbufPtr)) ) - { - /* set to minimum length */ - IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) = - IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN; - } - else - { - /* restore original length */ - IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) = - ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) - - (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) ); - } - - /* replenish from here */ - if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS) - { - IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\ - on port %d\n", portId, 0, 0, 0, 0, 0); - } - - RX_STATS_INC(portId, rxFiltered); - - /* indicate that frame should not be subjected to further processing */ - return false; - } - - return true; -} - - -/** - * @fn ixEthRxFrameQMCallback - * - * @brief receive callback for Frame receive Q from NPE - * - * Frames are passed one-at-a-time to the user - * - * @param @ref IxQMgrCallback - * - * @return none - * - * @internal - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ -void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - IX_OSAL_MBUF *nextMbufPtr; - UINT32 qEntry; - UINT32 nextQEntry; - UINT32 *qEntryPtr; - UINT32 portId; - UINT32 destPortId; - UINT32 npeId; - UINT32 rxQReadStatus; - - /* - * Design note : entries are read in a buffer, This buffer contains - * an extra zeroed entry so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - - /* - * Indication of the number of times the callback is used. - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter); - - do - { - /* - * Indication of the number of times the queue is drained - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead); - - /* ensure the last entry of the array contains a zeroed value */ - qEntryPtr = rxQEntry; - qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0; - - rxQReadStatus = ixQMgrQBurstRead(qId, - IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW) - && (rxQReadStatus != IX_SUCCESS)) - { - ixEthAccDataStats.unexpectedError++; - /*major error*/ - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameQMCallback:Error: %u\n", - (UINT32)rxQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert and preload the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *qEntryPtr; - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - while(nextQEntry != 0) - { - /* get the next entry */ - qEntry = nextQEntry; - mbufPtr = nextMbufPtr; - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameQMCallback: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *(++qEntryPtr); - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - /* - * Get Port and Npe ID from message. - */ - npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK & - qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - - /* process frame, check the return code and skip the remaining of - * the loop if the frame is to be filtered out - */ - if (ixEthRxFrameProcess(portId, mbufPtr)) - { - /* destination portId for this packet */ - destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr); - - if (destPortId != IX_ETH_DB_UNKNOWN_PORT) - { - destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId); - } - - /* test if QoS is enabled in ethAcc - */ - if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY) - { - /* check if there is a higher priority queue - * which may require processing and then process it. - */ - if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES) - { - ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId], - callbackId); - } - } - - /* - * increment priority stats - */ - RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]); - - /* - * increment callback count stats - */ - RX_STATS_INC(portId,rxFrameClientCallback); - - /* - * Call user level callback. - */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn( - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag, - mbufPtr, - destPortId); - } - } - } while (rxQReadStatus == IX_SUCCESS); -} - -/** - * @fn ixEthRxMultiBufferQMCallback - * - * @brief receive callback for Frame receive Q from NPE - * - * Frames are passed as an array to the user - * - * @param @ref IxQMgrCallback - * - * @return none - * - * @internal - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ -void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - IX_OSAL_MBUF *nextMbufPtr; - UINT32 qEntry; - UINT32 nextQEntry; - UINT32 *qEntryPtr; - UINT32 portId; - UINT32 npeId; - UINT32 rxQReadStatus; - /* - * Design note : entries are read in a static buffer, This buffer contains - * an extra zeroed entry so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS]; - - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - rxMbufPtr[portId] = rxMbufPortArray[portId]; - } - - /* - * Indication of the number of times the callback is used. - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter); - - do - { - /* - * Indication of the number of times the queue is drained - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead); - - /* ensure the last entry of the array contains a zeroed value */ - qEntryPtr = rxQEntry; - qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0; - - rxQReadStatus = ixQMgrQBurstRead(qId, - IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW) - && (rxQReadStatus != IX_SUCCESS)) - { - ixEthAccDataStats.unexpectedError++; - /*major error*/ - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameMultiBufferQMCallback:Error: %u\n", - (UINT32)rxQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert and preload the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *qEntryPtr; - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - while(nextQEntry != 0) - { - /* get the next entry */ - qEntry = nextQEntry; - mbufPtr = nextMbufPtr; - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *(++qEntryPtr); - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - /* - * Get Port and Npe ID from message. - */ - npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK & - qEntry) >> - IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - - /* skip the remaining of the loop if the frame is - * to be filtered out - */ - if (ixEthRxFrameProcess(portId, mbufPtr)) - { - /* store a mbuf pointer in an array */ - *rxMbufPtr[portId]++ = mbufPtr; - - /* - * increment priority stats - */ - RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]); - } - - /* test for QoS enabled in ethAcc */ - if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY) - { - /* check if there is a higher priority queue - * which may require processing and then process it. - */ - if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES) - { - ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId], - callbackId); - } - } - } - - /* check if any of the the arrays contains any entry */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - if (rxMbufPtr[portId] != rxMbufPortArray[portId]) - { - /* add a last NULL pointer at the end of the - * array of mbuf pointers - */ - *rxMbufPtr[portId] = NULL; - - /* - * increment callback count stats - */ - RX_STATS_INC(portId,rxFrameClientCallback); - - /* - * Call user level callback with an array of - * buffers (NULL terminated) - */ - ixEthAccPortData[portId].ixEthAccRxData. - rxMultiBufferCallbackFn( - ixEthAccPortData[portId].ixEthAccRxData. - rxMultiBufferCallbackTag, - rxMbufPortArray[portId]); - - /* reset the buffer pointer to the beginning of - * the array - */ - rxMbufPtr[portId] = rxMbufPortArray[portId]; - } - } - - } while (rxQReadStatus == IX_SUCCESS); -} - - -/** - * @brief rxFree low event handler - * - */ -void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IxEthAccPortId portId = (IxEthAccPortId) callbackId; - int lockVal; - UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD; - IX_STATUS qStatus = IX_SUCCESS; - - /* - * We have reached a low threshold on one of the Rx Free Qs - */ - - /*note that due to the fact that we are working off an Empty threshold, this callback - need only write a single entry to the Rx Free queue in order to re-arm the notification - */ - - RX_STATS_INC(portId,rxFreeLowCallback); - - /* - * Get buffers from approprite S/W Rx freeBufferList Q. - */ - -#ifndef NDEBUG - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n", - portId, 0, 0, 0, 0, 0); - return; - } -#endif - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccRxData.freeBufferList)) - { - /* - * Turn off Q callback notification for Q in Question. - */ - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId)); - - - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - - if (qStatus != IX_SUCCESS) - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - return; - } - } - else - { - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - /* - * Load the H/W Q with buffers from the s/w Q. - */ - - do - { - /* - * Consume Q entries. - Note Q contains Physical addresss, - * and have already been flushed to memory, - * And endianess converted if required. - */ - if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS) - { - /* - * No more entries in s/w Q. - * Turn off Q callback indication - */ - - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccRxData.freeBufferList)) - { - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId)); - } - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - break; - } - } - while (--maxQWritesToPerform); - } -} -/** - * @fn Tx queue low event handler - * - */ -void -ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IxEthAccPortId portId = (IxEthAccPortId) callbackId; - int lockVal; - UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK; - IX_STATUS qStatus = IX_SUCCESS; - IxEthAccTxPriority highestPriority; - - - /* - * We have reached a low threshold on the Tx Q, and are being asked to - * supply a buffer for transmission from our S/W TX queues - */ - TX_STATS_INC(portId,txLowThreshCallback); - - /* - * Get buffers from approprite Q. - */ - -#ifndef NDEBUG - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n", - portId, 0, 0, 0, 0, 0); - return; - } -#endif - - do - { - /* - * Consume Q entries. - Note Q contains Physical addresss, - * and have already been flushed to memory, - * and endianess already sone if required. - */ - - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) == - IX_ETH_ACC_FAIL) - { - /* - * No more entries in s/w Q. - * Turn off Q callback indication - */ - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId)); - - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - - if (qStatus != IX_SUCCESS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - - return; - } - else - { - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS) - { - /* nothing left in the sw queue or the hw queues are - * full. There is no point to continue to drain the - * sw queues - */ - return; - } - } - } - while (--maxQWritesToPerform); -} - -/** - * @brief TxDone event handler - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ - -void -ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - UINT32 qEntry; - UINT32 *qEntryPtr; - UINT32 txDoneQReadStatus; - UINT32 portId; - UINT32 npeId; - - /* - * Design note : entries are read in a static buffer, This buffer contains - * an extra entyry (which is zeroed by the compiler), so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1]; - - /* - * Indication that Tx frames have been transmitted from the NPE. - */ - - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter); - - do{ - qEntryPtr = txDoneQEntry; - txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, - IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW - && (txDoneQReadStatus != IX_SUCCESS)) - { - /*major error*/ - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback:Error: %u\n", - (UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - qEntry = *qEntryPtr; - - while(qEntry != 0) - { - mbufPtr = ixEthAccEntryFromQConvert(qEntry, - IX_ETHNPE_QM_Q_TXENET_ADDR_MASK); - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* endianness conversions and stats updates */ - ixEthAccMbufFromTxQ(mbufPtr); - - /* - * Get NPE id from message, then convert to portId. - */ - npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK & - qEntry) >> - IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - TX_STATS_INC(portId,txDoneClientCallback); - - /* - * Call user level callback. - */ - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn( - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag, - mbufPtr); - - /* move to next queue entry */ - qEntry = *(++qEntryPtr); - - } - } while( txDoneQReadStatus == IX_SUCCESS ); -} - -IX_ETH_ACC_PUBLIC -void ixEthAccDataPlaneShow(void) -{ - UINT32 numTx0Entries; - UINT32 numTx1Entries; - UINT32 numTxDoneEntries; - UINT32 numRxEntries; - UINT32 numRxFree0Entries; - UINT32 numRxFree1Entries; - UINT32 portId; -#ifdef __ixp46X - UINT32 numTx2Entries; - UINT32 numRxFree2Entries; -#endif -#ifndef NDEBUG - UINT32 priority; - UINT32 numBuffersInRx=0; - UINT32 numBuffersInTx=0; - UINT32 numBuffersInSwQ=0; - UINT32 totalBuffers=0; - UINT32 rxFreeCallbackCounter = 0; - UINT32 txCallbackCounter = 0; -#endif - UINT32 key; - - /* snapshot of stats */ - IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS]; - IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS]; - IxEthAccDataPlaneStats stats; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return; - } - - /* get a reliable snapshot */ - key = ixOsalIrqLock(); - - numTx0Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries); - numTx1Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries); - numTxDoneEntries = 0; - ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries); - numRxEntries = 0; - ixEthAccQMgrRxQEntryGet(&numRxEntries); - numRxFree0Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries); - numRxFree1Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries); - -#ifdef __ixp46X - numTx2Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries); - numRxFree2Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries); -#endif - - for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - memcpy(&tx[portId], - &ixEthAccPortData[portId].ixEthAccTxData.stats, - sizeof(tx[portId])); - memcpy(&rx[portId], - &ixEthAccPortData[portId].ixEthAccRxData.stats, - sizeof(rx[portId])); - } - memcpy(&stats, &ixEthAccDataStats, sizeof(stats)); - - ixOsalIrqUnlock(key); - -#ifdef NDEBUG - printf("Detailed statistics collection not supported in this load\n"); -#endif - - /* print snapshot */ - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((IX_ETH_PORT_1 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - if ((IX_ETH_PORT_2 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - if ((IX_ETH_PORT_3 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - } - - printf("PORT %u --------------------------------\n", - portId); -#ifndef NDEBUG - printf("Tx Done Frames : %u\n", - tx[portId].txDoneClientCallback + - tx[portId].txDoneSwQDuringDisable + - tx[portId].txDoneDuringDisable); - printf("Tx Frames : %u\n", - tx[portId].txQOK + tx[portId].txQDelayed); - printf("Tx H/W Q Added OK : %u\n", - tx[portId].txQOK); - printf("Tx H/W Q Delayed : %u\n", - tx[portId].txQDelayed); - printf("Tx From S/W Q Added OK : %u\n", - tx[portId].txFromSwQOK); - printf("Tx From S/W Q Delayed : %u\n", - tx[portId].txFromSwQDelayed); - printf("Tx Overflow : %u\n", - tx[portId].txOverflow); - printf("Tx Mutual Lock : %u\n", - tx[portId].txLock); - printf("Tx Late Ntf Enabled : %u\n", - tx[portId].txLateNotificationEnabled); - printf("Tx Low Thresh CB : %u\n", - tx[portId].txLowThreshCallback); - printf("Tx Done from H/W Q (Disable) : %u\n", - tx[portId].txDoneDuringDisable); - printf("Tx Done from S/W Q (Disable) : %u\n", - tx[portId].txDoneSwQDuringDisable); - for (priority = IX_ETH_ACC_TX_PRIORITY_0; - priority <= IX_ETH_ACC_TX_PRIORITY_7; - priority++) - { - if (tx[portId].txPriority[priority]) - { - printf("Tx Priority %u : %u\n", - priority, - tx[portId].txPriority[priority]); - } - } -#endif - printf("Tx unexpected errors : %u (should be 0)\n", - tx[portId].txUnexpectedError); - -#ifndef NDEBUG - printf("Rx Frames : %u\n", - rx[portId].rxFrameClientCallback + - rx[portId].rxSwQDuringDisable+ - rx[portId].rxDuringDisable); - printf("Rx Free Replenish : %u\n", - rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed); - printf("Rx Free H/W Q Added OK : %u\n", - rx[portId].rxFreeRepOK); - printf("Rx Free H/W Q Delayed : %u\n", - rx[portId].rxFreeRepDelayed); - printf("Rx Free From S/W Q Added OK : %u\n", - rx[portId].rxFreeRepFromSwQOK); - printf("Rx Free From S/W Q Delayed : %u\n", - rx[portId].rxFreeRepFromSwQDelayed); - printf("Rx Free Overflow : %u\n", - rx[portId].rxFreeOverflow); - printf("Rx Free Mutual Lock : %u\n", - rx[portId].rxFreeLock); - printf("Rx Free Late Ntf Enabled : %u\n", - rx[portId].rxFreeLateNotificationEnabled); - printf("Rx Free Low CB : %u\n", - rx[portId].rxFreeLowCallback); - printf("Rx From H/W Q (Disable) : %u\n", - rx[portId].rxDuringDisable); - printf("Rx From S/W Q (Disable) : %u\n", - rx[portId].rxSwQDuringDisable); - printf("Rx unlearned Mac Address : %u\n", - rx[portId].rxUnlearnedMacAddress); - printf("Rx Filtered (Rx => RxFree) : %u\n", - rx[portId].rxFiltered); - - for (priority = IX_ETH_ACC_TX_PRIORITY_0; - priority <= IX_ETH_ACC_TX_PRIORITY_7; - priority++) - { - if (rx[portId].rxPriority[priority]) - { - printf("Rx Priority %u : %u\n", - priority, - rx[portId].rxPriority[priority]); - } - } -#endif - printf("Rx unexpected errors : %u (should be 0)\n", - rx[portId].rxUnexpectedError); - -#ifndef NDEBUG - numBuffersInTx = tx[portId].txQOK + - tx[portId].txQDelayed - - tx[portId].txDoneClientCallback - - tx[portId].txDoneSwQDuringDisable - - tx[portId].txDoneDuringDisable; - - printf("# Tx Buffers currently for transmission : %u\n", - numBuffersInTx); - - numBuffersInRx = rx[portId].rxFreeRepOK + - rx[portId].rxFreeRepDelayed - - rx[portId].rxFrameClientCallback - - rx[portId].rxSwQDuringDisable - - rx[portId].rxDuringDisable; - - printf("# Rx Buffers currently for reception : %u\n", - numBuffersInRx); - - totalBuffers += numBuffersInRx + numBuffersInTx; -#endif - } - - printf("---------------------------------------\n"); - -#ifndef NDEBUG - printf("\n"); - printf("Mbufs :\n"); - printf("Tx Unchained mbufs : %u\n", - stats.unchainedTxMBufs); - printf("Tx Chained bufs : %u\n", - stats.chainedTxMBufs); - printf("TxDone Unchained mbufs : %u\n", - stats.unchainedTxDoneMBufs); - printf("TxDone Chained bufs : %u\n", - stats.chainedTxDoneMBufs); - printf("RxFree Unchained mbufs : %u\n", - stats.unchainedRxFreeMBufs); - printf("RxFree Chained bufs : %u\n", - stats.chainedRxFreeMBufs); - printf("Rx Unchained mbufs : %u\n", - stats.unchainedRxMBufs); - printf("Rx Chained bufs : %u\n", - stats.chainedRxMBufs); - - printf("\n"); - printf("Software queue usage :\n"); - printf("Buffers added to S/W Q : %u\n", - stats.addToSwQ); - printf("Buffers removed from S/W Q : %u\n", - stats.removeFromSwQ); - - printf("\n"); - printf("Hardware queues callbacks :\n"); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - rxFreeCallbackCounter += rx[portId].rxFreeLowCallback; - txCallbackCounter += tx[portId].txLowThreshCallback; - } - printf("Tx Done QM Callback invoked : %u\n", - stats.txDoneCallbackCounter); - printf("Tx QM Callback invoked : %u\n", - txCallbackCounter); - printf("Rx QM Callback invoked : %u\n", - stats.rxCallbackCounter); - printf("Rx QM Callback burst read : %u\n", - stats.rxCallbackBurstRead); - printf("Rx Free QM Callback invoked : %u\n", - rxFreeCallbackCounter); -#endif - printf("Unexpected errors in CB : %u (should be 0)\n", - stats.unexpectedError); - printf("\n"); - - printf("Hardware queues levels :\n"); - printf("Transmit Port 1 Q : %u \n",numTx0Entries); - printf("Transmit Port 2 Q : %u \n",numTx1Entries); -#ifdef __ixp46X - printf("Transmit Port 3 Q : %u \n",numTx2Entries); -#endif - printf("Transmit Done Q : %u \n",numTxDoneEntries); - printf("Receive Q : %u \n",numRxEntries); - printf("Receive Free Port 1 Q : %u \n",numRxFree0Entries); - printf("Receive Free Port 2 Q : %u \n",numRxFree1Entries); -#ifdef __ixp46X - printf("Receive Free Port 3 Q : %u \n",numRxFree2Entries); -#endif - -#ifndef NDEBUG - printf("\n"); - printf("# Total Buffers accounted for : %u\n", - totalBuffers); - - numBuffersInSwQ = ixEthAccDataStats.addToSwQ - - ixEthAccDataStats.removeFromSwQ; - - printf(" Buffers in S/W Qs : %u\n", - numBuffersInSwQ); - printf(" Buffers in H/W Qs or NPEs : %u\n", - totalBuffers - numBuffersInSwQ); -#endif - - printf("Rx QoS Discipline : %s\n", - (ixEthAccDataInfo.schDiscipline == - FIFO_PRIORITY ) ? "Enabled" : "Disabled"); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - printf("Tx QoS Discipline port %u : %s\n", - portId, - (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_PRIORITY ) ? "Enabled" : "Disabled"); - } - printf("\n"); -} - - - - - diff --git a/drivers/net/npe/IxEthAccMac.c b/drivers/net/npe/IxEthAccMac.c deleted file mode 100644 index 5540b33ae8..0000000000 --- a/drivers/net/npe/IxEthAccMac.c +++ /dev/null @@ -1,2641 +0,0 @@ -/** - * @file IxEthAccMac.c - * - * @author Intel Corporation - * @date - * - * @brief MAC control functions - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxNpeMh.h" -#ifdef CONFIG_IXP425_COMPONENT_ETHDB -#include "IxEthDB.h" -#endif -#include "IxEthDBPortDefs.h" -#include "IxEthNpe.h" -#include "IxEthAcc.h" -#include "IxEthAccDataPlane_p.h" -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" - -/* Maximum number of retries during ixEthAccPortDisable, which - * is approximately 10 seconds -*/ -#define IX_ETH_ACC_MAX_RETRY 500 - -/* Maximum number of retries during ixEthAccPortDisable when expecting - * timeout - */ -#define IX_ETH_ACC_MAX_RETRY_TIMEOUT 5 - -#define IX_ETH_ACC_VALIDATE_PORT_ID(portId) \ - do \ - { \ - if(!IX_ETH_ACC_IS_PORT_VALID(portId)) \ - { \ - return IX_ETH_ACC_INVALID_PORT; \ - } \ - } while(0) - -PUBLIC IxEthAccMacState ixEthAccMacState[IX_ETH_ACC_NUMBER_OF_PORTS]; - -PRIVATE UINT32 ixEthAccMacBase[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/*Forward function declarations*/ -PRIVATE void -ixEthAccPortDisableRx (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); - -PRIVATE void -ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); - -PRIVATE void -ixEthAccPortDisableTxDone (UINT32 cbTag, - IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccPortDisableTxDoneAndSubmit (UINT32 cbTag, - IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccPortDisableRxCallback (UINT32 cbTag, - IX_OSAL_MBUF * mBufPtr, - UINT32 learnedPortId); - -PRIVATE void -ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag, - IX_OSAL_MBUF **mBufPtr); - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryTransmit(UINT32 portId); - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryReplenish(UINT32 portId); - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -PRIVATE void -ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccMulticastAddressSet(IxEthAccPortId portId); - -PRIVATE BOOL -ixEthAccMacEqual(IxEthAccMacAddr *macAddr1, - IxEthAccMacAddr *macAddr2); - -PRIVATE void -ixEthAccMacPrint(IxEthAccMacAddr *m); - -PRIVATE void -ixEthAccMacStateUpdate(IxEthAccPortId portId); - -IxEthAccStatus -ixEthAccMacMemInit(void) -{ - ixEthAccMacBase[IX_ETH_PORT_1] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, - IX_OSAL_IXP400_ETHA_MAP_SIZE); - ixEthAccMacBase[IX_ETH_PORT_2] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_1_BASE, - IX_OSAL_IXP400_ETHB_MAP_SIZE); -#ifdef __ixp46X - ixEthAccMacBase[IX_ETH_PORT_3] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_2_BASE, - IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE); - if (ixEthAccMacBase[IX_ETH_PORT_3] == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MAC I/O memory\n", - 0, 0, 0, 0, 0 ,0); - - return IX_ETH_ACC_FAIL; - } -#endif - - if (ixEthAccMacBase[IX_ETH_PORT_1] == 0 - || ixEthAccMacBase[IX_ETH_PORT_2] == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MAC I/O memory\n", - 0, 0, 0, 0, 0 ,0); - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -void -ixEthAccMacUnload(void) -{ - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_1]); - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_2]); -#ifdef __ixp46X - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_3]); - ixEthAccMacBase[IX_ETH_PORT_3] = 0; -#endif - ixEthAccMacBase[IX_ETH_PORT_2] = 0; - ixEthAccMacBase[IX_ETH_PORT_1] = 0; -} - -IxEthAccStatus -ixEthAccPortEnablePriv(IxEthAccPortId portId) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: (Mac) cannot enable port %d, port not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if (ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn == NULL) - { - /* TxDone callback not registered */ - printf("EthAcc: (Mac) cannot enable port %d, TxDone callback not registered\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if ((ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn == NULL) - && (ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn == NULL)) - { - /* Receive callback not registered */ - printf("EthAcc: (Mac) cannot enable port %d, Rx callback not registered\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if(!ixEthAccMacState[portId].initDone) - { - printf("EthAcc: (Mac) cannot enable port %d, MAC address not set\n", portId); - return (IX_ETH_ACC_MAC_UNINITIALIZED); - } - - /* if the state is being set to what it is already at, do nothing*/ - if (ixEthAccMacState[portId].enabled) - { - return IX_ETH_ACC_SUCCESS; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* enable ethernet database for this port */ - if (ixEthDBPortEnable(portId) != IX_ETH_DB_SUCCESS) - { - printf("EthAcc: (Mac) cannot enable port %d, EthDB failure\n", portId); - return IX_ETH_ACC_FAIL; - } -#endif - - /* set the MAC core registers */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL2, - IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RANDOM_SEED, - IX_ETH_ACC_RANDOM_SEED_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_THRESH_P_EMPTY, - IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_THRESH_P_FULL, - IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_DEFER, - IX_ETH_ACC_MAC_TX_DEFER_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_TWO_DEFER_1, - IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_TWO_DEFER_2, - IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_SLOT_TIME, - IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_BUF_SIZE_TX, - IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - IX_ETH_ACC_TX_CNTRL1_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - IX_ETH_ACC_RX_CNTRL1_DEFAULT); - - /* set the global state */ - ixEthAccMacState[portId].portDisableState = ACTIVE; - ixEthAccMacState[portId].enabled = true; - - /* rewrite the setup (including mac filtering) depending - * on current options - */ - ixEthAccMacStateUpdate(portId); - - return IX_ETH_ACC_SUCCESS; -} - -/* - * PortDisable local variables. They contain the intermediate steps - * while the port is being disabled and the buffers being drained out - * of the NPE. - */ -typedef void (*IxEthAccPortDisableRx)(IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); -static IxEthAccPortRxCallback -ixEthAccPortDisableFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static IxEthAccPortMultiBufferRxCallback -ixEthAccPortDisableMultiBufferFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static IxEthAccPortDisableRx -ixEthAccPortDisableRxTable[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableMultiBufferCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; - -static IxEthAccPortTxDoneCallback -ixEthAccPortDisableTxDoneFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableTxDoneCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; - -static UINT32 -ixEthAccPortDisableUserBufferCount[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/* - * PortDisable private callbacks functions. They handle the user - * traffic, and the special buffers (one for tx, one for rx) used - * in portDisable. - */ -PRIVATE void -ixEthAccPortDisableTxDone(UINT32 cbTag, - IX_OSAL_MBUF *mbuf) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - - /* check for the special mbuf used in portDisable */ - if (mbuf == ixEthAccMacState[portId].portDisableTxMbufPtr) - { - *txState = TRANSMIT_DONE; - } - else - { - /* increment the count of user traffic during portDisable */ - ixEthAccPortDisableUserBufferCount[portId]++; - - /* call client TxDone function */ - ixEthAccPortDisableTxDoneFn[portId](ixEthAccPortDisableTxDoneCbTag[portId], mbuf); - } -} - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryTransmit(UINT32 portId) -{ - int key; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - /* transmit the special buffer again if it is transmitted - * and update the txState - * This section is protected because the portDisable context - * run an identical code, so the system keeps transmitting at the - * maximum rate. - */ - key = ixOsalIrqLock(); - if (*txState == TRANSMIT_DONE) - { - IX_OSAL_MBUF *mbufTxPtr = ixEthAccMacState[portId].portDisableTxMbufPtr; - *txState = TRANSMIT; - status = ixEthAccPortTxFrameSubmit(portId, - mbufTxPtr, - IX_ETH_ACC_TX_DEFAULT_PRIORITY); - } - ixOsalIrqUnlock(key); - - return status; -} - -PRIVATE void -ixEthAccPortDisableTxDoneAndSubmit(UINT32 cbTag, - IX_OSAL_MBUF *mbuf) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - /* call the callback which forwards the traffic to the client */ - ixEthAccPortDisableTxDone(cbTag, mbuf); - - /* try to transmit the buffer used in portDisable - * if seen in TxDone - */ - ixEthAccPortDisableTryTransmit(portId); -} - -PRIVATE void -ixEthAccPortDisableRx (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback) -{ - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - IX_OSAL_MBUF *mNextPtr; - - while (mBufPtr) - { - mNextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr); - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr) = NULL; - - /* check for the special mbuf used in portDisable */ - if (mBufPtr == ixEthAccMacState[portId].portDisableRxMbufPtr) - { - *rxState = RECEIVE; - } - else - { - /* increment the count of user traffic during portDisable */ - ixEthAccPortDisableUserBufferCount[portId]++; - - /* reset the received payload length during portDisable */ - IX_OSAL_MBUF_MLEN(mBufPtr) = 0; - IX_OSAL_MBUF_PKT_LEN(mBufPtr) = 0; - - if (useMultiBufferCallback) - { - /* call the user callback with one unchained - * buffer, without payload. A small array is built - * to be used as a parameter (the user callback expects - * to receive an array ended by a NULL pointer. - */ - IX_OSAL_MBUF *mBufPtrArray[2]; - - mBufPtrArray[0] = mBufPtr; - mBufPtrArray[1] = NULL; - ixEthAccPortDisableMultiBufferFn[portId]( - ixEthAccPortDisableMultiBufferCbTag[portId], - mBufPtrArray); - } - else - { - /* call the user callback with a unchained - * buffer, without payload and the destination port is - * unknown. - */ - ixEthAccPortDisableFn[portId]( - ixEthAccPortDisableCbTag[portId], - mBufPtr, - IX_ETH_DB_UNKNOWN_PORT /* port not found */); - } - } - - mBufPtr = mNextPtr; - } -} - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryReplenish(UINT32 portId) -{ - int key; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - /* replenish with the special buffer again if it is received - * and update the rxState - * This section is protected because the portDisable context - * run an identical code, so the system keeps replenishing at the - * maximum rate. - */ - key = ixOsalIrqLock(); - if (*rxState == RECEIVE) - { - IX_OSAL_MBUF *mbufRxPtr = ixEthAccMacState[portId].portDisableRxMbufPtr; - *rxState = REPLENISH; - IX_OSAL_MBUF_MLEN(mbufRxPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE; - status = ixEthAccPortRxFreeReplenish(portId, mbufRxPtr); - } - ixOsalIrqUnlock(key); - - return status; -} - -PRIVATE void -ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback) -{ - /* call the callback which forwards the traffic to the client */ - ixEthAccPortDisableRx(portId, mBufPtr, useMultiBufferCallback); - - /* try to replenish with the buffer used in portDisable - * if seen in Rx - */ - ixEthAccPortDisableTryReplenish(portId); -} - -PRIVATE void -ixEthAccPortDisableRxCallback (UINT32 cbTag, - IX_OSAL_MBUF * mBufPtr, - UINT32 learnedPortId) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - /* call the portDisable receive callback */ - (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false); -} - -PRIVATE void -ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag, - IX_OSAL_MBUF **mBufPtr) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - while (*mBufPtr) - { - /* call the portDisable receive callback with one buffer at a time */ - (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true); - } -} - -IxEthAccStatus -ixEthAccPortDisablePriv(IxEthAccPortId portId) -{ - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - int key; - int retry, retryTimeout; - volatile IxEthAccPortDisableState *state = &ixEthAccMacState[portId].portDisableState; - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable port.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* if the state is being set to what it is already at, do nothing */ - if (!ixEthAccMacState[portId].enabled) - { - return IX_ETH_ACC_SUCCESS; - } - - *state = DISABLED; - - /* disable MAC receive first */ - ixEthAccPortRxDisablePriv(portId); - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* disable ethernet database for this port - It is done now to avoid - * issuing ELT maintenance after requesting 'port disable' in an NPE - */ - if (ixEthDBPortDisable(portId) != IX_ETH_DB_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - IX_ETH_ACC_FATAL_LOG("ixEthAccPortDisable: failed to disable EthDB for this port\n", 0, 0, 0, 0, 0, 0); - } -#endif - - /* enter the critical section */ - key = ixOsalIrqLock(); - - /* swap the Rx and TxDone callbacks */ - ixEthAccPortDisableFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn; - ixEthAccPortDisableMultiBufferFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn; - ixEthAccPortDisableCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag; - ixEthAccPortDisableMultiBufferCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag; - ixEthAccPortDisableTxDoneFn[portId] = ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn; - ixEthAccPortDisableTxDoneCbTag[portId] = ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag; - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx; - - /* register temporary callbacks */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableRxCallback; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = portId; - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferRxCallback; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = portId; - - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDone; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = portId; - - /* initialise the Rx state and Tx states */ - *txState = TRANSMIT_DONE; - *rxState = RECEIVE; - - /* exit the critical section */ - ixOsalIrqUnlock(key); - - /* enable a NPE loopback */ - if (ixEthAccNpeLoopbackEnablePriv(portId) != IX_ETH_ACC_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - - if (status == IX_ETH_ACC_SUCCESS) - { - retry = 0; - - /* Step 1 : Drain Tx traffic and TxDone queues : - * - * Transmit and replenish at least once with the - * special buffers until both of them are seen - * in the callback hook - * - * (the receive callback keeps replenishing, so once we see - * the special Tx buffer, we can be sure that Tx drain is complete) - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRxAndReplenish; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDone; - - do - { - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* keep transmitting */ - status = ixEthAccPortDisableTryTransmit(portId); - } - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && (*txState == TRANSMIT)); - - /* Step 2 : Drain Rx traffic, RxFree and Rx queues : - * - * Transmit and replenish at least once with the - * special buffers until both of them are seen - * in the callback hook - * (the transmit callback keeps transmitting, and when we see - * the special Rx buffer, we can be sure that rxFree drain - * is complete) - * - * The nested loop helps to retry if the user was keeping - * replenishing or transmitting during portDisable. - * - * The 2 nested loops ensure more retries if user traffic is - * seen during portDisable : the user should not replenish - * or transmit while portDisable is running. However, because of - * the queueing possibilities in ethAcc dataplane, it is possible - * that a lot of traffic is left in the queues (e.g. when - * transmitting over a low speed link) and therefore, more - * retries are allowed to help flushing the buffers out. - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRx; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDoneAndSubmit; - - do - { - do - { - ixEthAccPortDisableUserBufferCount[portId] = 0; - - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* keep transmitting */ - status = ixEthAccPortDisableTryTransmit(portId); - } - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && ((ixEthAccPortDisableUserBufferCount[portId] != 0) - || (*rxState == REPLENISH))); - - /* After the first iteration, change the receive callbacks, - * to process only 1 buffer at a time - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRx; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDone; - - /* repeat the whole process while user traffic is seen in TxDone - * - * The conditions to stop the loop are - * - Xscale has both Rx and Tx special buffers - * (txState = transmit, rxState = receive) - * - any error in txSubmit or rxReplenish - * - no user traffic seen - * - an excessive amount of retries - */ - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry < IX_ETH_ACC_MAX_RETRY) - && (*txState == TRANSMIT)); - - /* check the loop exit conditions. The NPE should not hold - * the special buffers. - */ - if ((*rxState == REPLENISH) || (*txState == TRANSMIT)) - { - status = IX_ETH_ACC_FAIL; - } - - if (status == IX_ETH_ACC_SUCCESS) - { - /* Step 3 : Replenish without transmitting until a timeout - * occurs, in order to drain the internal NPE fifos - * - * we can expect a few frames srill held - * in the NPE. - * - * The 2 nested loops take care about the NPE dropping traffic - * (including loopback traffic) when the Rx queue is full. - * - * The timeout value is very conservative - * since the loopback used keeps replenishhing. - * - */ - do - { - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRxAndReplenish; - ixEthAccPortDisableUserBufferCount[portId] = 0; - retryTimeout = 0; - do - { - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT)); - - /* Step 4 : Transmit once. Stop replenish - * - * After the Rx timeout, we are sure that the NPE does not - * hold any frame in its internal NPE fifos. - * - * At this point, the NPE still holds the last rxFree buffer. - * By transmitting a single frame, this should unblock the - * last rxFree buffer. This code just transmit once and - * wait for both frames seen in TxDone and in rxFree. - * - */ - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx; - status = ixEthAccPortDisableTryTransmit(portId); - - /* the NPE should immediatelyt release - * the last Rx buffer and the last transmitted buffer - * unless the last Tx frame was dropped (rx queue full) - */ - if (status == IX_ETH_ACC_SUCCESS) - { - retryTimeout = 0; - do - { - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - while ((*rxState == REPLENISH) - && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT)); - } - - /* the NPE may have dropped the traffic because of Rx - * queue being full. This code ensures that the last - * Tx and Rx frames are both received. - */ - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && ((*txState == TRANSMIT) - || (*rxState == REPLENISH) - || (ixEthAccPortDisableUserBufferCount[portId] != 0))); - - /* Step 5 : check the final states : the NPE has - * no buffer left, nor in Tx , nor in Rx directions. - */ - if ((*rxState == REPLENISH) || (*txState == TRANSMIT)) - { - status = IX_ETH_ACC_FAIL; - } - } - - /* now all the buffers are drained, disable NPE loopback - * This is done regardless of the logic to drain the queues and - * the internal buffers held by the NPE. - */ - if (ixEthAccNpeLoopbackDisablePriv(portId) != IX_ETH_ACC_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - /* disable MAC Tx and Rx services */ - ixEthAccMacState[portId].enabled = false; - ixEthAccMacStateUpdate(portId); - - /* restore the Rx and TxDone callbacks (within a critical section) */ - key = ixOsalIrqLock(); - - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableFn[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = ixEthAccPortDisableCbTag[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferFn[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = ixEthAccPortDisableMultiBufferCbTag[portId]; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDoneFn[portId]; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = ixEthAccPortDisableTxDoneCbTag[portId]; - - ixOsalIrqUnlock(key); - - /* the MAC core rx/tx disable may left the MAC hardware in an - * unpredictable state. A hw reset is executed before resetting - * all the MAC parameters to a known value. - */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - /* rewrite all parameters to their current value */ - ixEthAccMacStateUpdate(portId); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - return status; -} - -IxEthAccStatus -ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0); - - /* Since Eth NPE is not available, port must be disabled */ - *enabled = false ; - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - /* Since Eth NPE is not available, port must be disabled */ - *enabled = false ; - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - *enabled = ixEthAccMacState[portId].enabled; - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMacResetPriv(IxEthAccPortId portId) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot reset Ethernet coprocessor.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - /* rewrite all parameters to their current value */ - ixEthAccMacStateUpdate(portId); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortLoopbackEnable(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_LOOP_EN); - - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE void -ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg) -{ - IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG("IXETHACC:ixEthAccPortDisableMessageCallback: Illegal port: %u\n", - (UINT32) portId, 0, 0, 0, 0, 0); - - return; - } -#endif - - /* unlock message reception mutex */ - ixOsalMutexUnlock(&ixEthAccMacState[portId].npeLoopbackMessageLock); -} - -IxEthAccStatus -ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId) -{ - IX_STATUS npeMhStatus; - IxNpeMhMessage message; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* enable NPE loopback (lsb of the message contains the value 1) */ - message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL) - | 0x01; - message.data[1] = 0; - - npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_SETLOOPBACK_MODE_ACK, - ixEthAccNpeLoopbackMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT); - - if (npeMhStatus != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - else - { - /* wait for NPE loopbackEnable response */ - if (ixOsalMutexLock(&ixEthAccMacState[portId]. npeLoopbackMessageLock, - IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS) - != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - return status; -} - -IxEthAccStatus -ixEthAccPortTxEnablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable TX.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval | IX_ETH_ACC_TX_CNTRL1_TX_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortRxEnablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable RX.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_RX_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortLoopbackDisable(IxEthAccPortId portId) -{ - UINT32 regval; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*disable MAC loopabck */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - (regval & ~IX_ETH_ACC_RX_CNTRL1_LOOP_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId) -{ - IX_STATUS npeMhStatus; - IxNpeMhMessage message; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* disable NPE loopback (lsb of the message contains the value 0) */ - message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL); - message.data[1] = 0; - - npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_SETLOOPBACK_MODE_ACK, - ixEthAccNpeLoopbackMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT); - - if (npeMhStatus != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - else - { - /* wait for NPE loopbackEnable response */ - if (ixOsalMutexLock(&ixEthAccMacState[portId].npeLoopbackMessageLock, - IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS) - != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - return status; -} - -IxEthAccStatus -ixEthAccPortTxDisablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable TX.\n", (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - (regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortRxDisablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable RX.\n", (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - (regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear promiscuous mode.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*set bit 5 of Rx control 1 - enable address filtering*/ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - - ixEthAccMacState[portId].promiscuous = false; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId) -{ - UINT32 regval; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set promiscuous mode.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* - * Set bit 5 of Rx control 1 - We enable address filtering even in - * promiscuous mode because we want the MAC to set the appropriate - * bits in m_flags which doesn't happen if we turn off filtering. - */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - - ixEthAccMacState[portId].promiscuous = true; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - - if (macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - if ( macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ) - { - /* This is a multicast/broadcast address cant set it ! */ - return IX_ETH_ACC_FAIL; - } - - if ( macAddr->macAddress[0] == 0 && - macAddr->macAddress[1] == 0 && - macAddr->macAddress[2] == 0 && - macAddr->macAddress[3] == 0 && - macAddr->macAddress[4] == 0 && - macAddr->macAddress[5] == 0 ) - { - /* This is an invalid mac address cant set it ! */ - return IX_ETH_ACC_FAIL; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* update the MAC address in the ethernet database */ - if (ixEthDBPortAddressSet(portId, (IxEthDBMacAddr *) macAddr) != IX_ETH_DB_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } -#endif - - /*Set the Unicast MAC to the specified value*/ - for(i=0;imacAddress[i]); - } - ixEthAccMacState[portId].initDone = true; - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortUnicastMacAddressGetPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Unicast MAC from h/w - for the specified port*/ - UINT32 i; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - /* Since Eth Npe is unavailable, return invalid MAC Address = 00:00:00:00:00:00 */ - for(i=0;imacAddress[i] = 0; - } - return IX_ETH_ACC_SUCCESS ; - } - - if(!ixEthAccMacState[portId].initDone) - { - return (IX_ETH_ACC_MAC_UNINITIALIZED); - } - - if (macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - - for(i=0;imacAddress[i]); - } - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Multicast MAC from h/w - for the specified port*/ - UINT32 i; - - for(i=0;imacAddress[i]); - } - - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Multicast MAC from h/w - for the specified port*/ - UINT32 i; - - for(i=0;imacAddress[i]); - } - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMulticastAddressJoinPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - IxEthAccMacAddr broadcastAddr = {{0xff,0xff,0xff,0xff,0xff,0xff}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join Multicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*Check that the mac address is valid*/ - if(macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - /* Check that this is a multicast address */ - if (!(macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT)) - { - return IX_ETH_ACC_FAIL; - } - - /* We don't add the Broadcast address */ - if(ixEthAccMacEqual(&broadcastAddr, macAddr)) - { - return IX_ETH_ACC_FAIL; - } - - for (i = 0; - i= IX_ETH_ACC_MAX_MULTICAST_ADDRESSES) - { - return IX_ETH_ACC_FAIL; - } - - /*First add the address to the multicast table for the - specified port*/ - i=ixEthAccMacState[portId].mcastAddrIndex; - - memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i], - &macAddr->macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - - /*Increment the index into the table, this must be done here - as MulticastAddressSet below needs to know about the latest - entry. - */ - ixEthAccMacState[portId].mcastAddrIndex++; - - /*Then calculate the new value to be written to the address and - address mask registers*/ - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - - -IxEthAccStatus -ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId) -{ - IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join all Multicast Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* remove all entries from the database and - * insert a multicast entry - */ - memcpy(&ixEthAccMacState[portId].mcastAddrsTable[0], - &mcastMacAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - - ixEthAccMacState[portId].mcastAddrIndex = 1; - ixEthAccMacState[portId].joinAll = true; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave Multicast Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*Check that the mac address is valid*/ - if(macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - /* Remove this mac address from the mask for the specified port - * we copy down all entries above the blanked entry, and - * decrement the index - */ - i=0; - - while(i= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG( - "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - /*Unblock Stats Get call*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock); - -} - -PRIVATE void -ixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats) -{ - /* endianness conversion */ - - /* Rx stats */ - retStats->dot3StatsAlignmentErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors); - retStats->dot3StatsFCSErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors); - retStats->dot3StatsInternalMacReceiveErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors); - retStats->RxOverrunDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards); - retStats->RxLearnedEntryDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards); - retStats->RxLargeFramesDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards); - retStats->RxSTPBlockedDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards); - retStats->RxVLANTypeFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards); - retStats->RxVLANIdFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards); - retStats->RxInvalidSourceDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards); - retStats->RxBlackListDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards); - retStats->RxWhiteListDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards); - retStats->RxUnderflowEntryDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards); - - /* Tx stats */ - retStats->dot3StatsSingleCollisionFrames = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames); - retStats->dot3StatsMultipleCollisionFrames = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames); - retStats->dot3StatsDeferredTransmissions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions); - retStats->dot3StatsLateCollisions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions); - retStats->dot3StatsExcessiveCollsions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions); - retStats->dot3StatsInternalMacTransmitErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors); - retStats->dot3StatsCarrierSenseErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors); - retStats->TxLargeFrameDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards); - retStats->TxVLANIdFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards); -} - -IxEthAccStatus -ixEthAccMibIIStatsGet (IxEthAccPortId portId, - IxEthEthObjStats *retStats ) -{ - IxNpeMhMessage message; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n"); - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (retStats == NULL) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n"); - return (IX_ETH_ACC_FAIL); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId); - - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0); - - /* Return all zero stats */ - IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats)); - - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats)); - - message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL; - message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats); - - /* Permit only one task to request MIB statistics Get operation - at a time */ - ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER); - - if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_GETSTATS, - ixEthAccMacNpeStatsMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT) - != IX_SUCCESS) - { - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - printf("EthAcc: (Mac) StatsGet failed to send NPE message\n"); - - return IX_ETH_ACC_FAIL; - } - - /* Wait for callback invocation indicating response to - this request - we need this mutex in order to ensure - that the return from this function is synchronous */ - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS); - - /* Permit other tasks to perform MIB statistics Get operation */ - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - ixEthAccMibIIStatsEndianConvert (retStats); - - return IX_ETH_ACC_SUCCESS; -} - - -PRIVATE void -ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg) -{ - IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG( - "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - /*Unblock Stats Get & reset call*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock); - -} - - - -IxEthAccStatus -ixEthAccMibIIStatsGetClear (IxEthAccPortId portId, - IxEthEthObjStats *retStats) -{ - IxNpeMhMessage message; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n"); - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (retStats == NULL) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n"); - return (IX_ETH_ACC_FAIL); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId); - - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0); - - /* Return all zero stats */ - IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats)); - - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats)); - - message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL; - message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats); - - /* Permit only one task to request MIB statistics Get-Reset operation at a time */ - ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER); - - if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_RESETSTATS, - ixEthAccMacNpeStatsResetMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT) - != IX_SUCCESS) - { - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n"); - - return IX_ETH_ACC_FAIL; - } - - /* Wait for callback invocation indicating response to this request */ - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS); - - /* permit other tasks to get and reset MIB stats*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - ixEthAccMibIIStatsEndianConvert(retStats); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccMibIIStatsClear (IxEthAccPortId portId) -{ - static IxEthEthObjStats retStats; - IxEthAccStatus status; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear MIB II Stats.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - /* there is no reset operation without a corresponding Get */ - status = ixEthAccMibIIStatsGetClear(portId, &retStats); - - return status; -} - -/* Initialize the ethernet MAC settings */ -IxEthAccStatus -ixEthAccMacInit(IxEthAccPortId portId) -{ - IX_OSAL_MBUF_POOL* portDisablePool; - UINT8 *data; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Mac.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if(ixEthAccMacState[portId].macInitialised == false) - { - ixEthAccMacState[portId].fullDuplex = true; - ixEthAccMacState[portId].rxFCSAppend = true; - ixEthAccMacState[portId].txFCSAppend = true; - ixEthAccMacState[portId].txPADAppend = true; - ixEthAccMacState[portId].enabled = false; - ixEthAccMacState[portId].promiscuous = true; - ixEthAccMacState[portId].joinAll = false; - ixEthAccMacState[portId].initDone = false; - ixEthAccMacState[portId].macInitialised = true; - - /* initialize MIB stats mutexes */ - ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock); - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_OSAL_WAIT_FOREVER); - - ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsResetLock); - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_OSAL_WAIT_FOREVER); - - ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - ixOsalMutexInit(&ixEthAccMacState[portId].npeLoopbackMessageLock); - - ixEthAccMacState[portId].portDisableRxMbufPtr = NULL; - ixEthAccMacState[portId].portDisableTxMbufPtr = NULL; - - portDisablePool = IX_OSAL_MBUF_POOL_INIT(2, - IX_ETHACC_RX_MBUF_MIN_SIZE, - "portDisable Pool"); - - IX_OSAL_ENSURE(portDisablePool != NULL, "Failed to initialize PortDisable pool"); - - ixEthAccMacState[portId].portDisableRxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool); - ixEthAccMacState[portId].portDisableTxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool); - - IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableRxMbufPtr != NULL, - "Pool allocation failed"); - IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableTxMbufPtr != NULL, - "Pool allocation failed"); - /* fill the payload of the Rx mbuf used in portDisable */ - IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableRxMbufPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE; - - memset(IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableRxMbufPtr), - 0xAA, - IX_ETHACC_RX_MBUF_MIN_SIZE); - - /* fill the payload of the Tx mbuf used in portDisable (64 bytes) */ - IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64; - IX_OSAL_MBUF_PKT_LEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64; - - data = (UINT8 *) IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableTxMbufPtr); - memset(data, 0xBB, 64); - data[0] = 0x00; /* unicast destination MAC address */ - data[6] = 0x00; /* unicast source MAC address */ - data[12] = 0x08; /* typelength : IP frame */ - data[13] = 0x00; /* typelength : IP frame */ - - IX_OSAL_CACHE_FLUSH(data, 64); - } - - IX_OSAL_ASSERT (ixEthAccMacBase[portId] != 0); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - ixEthAccMacStateUpdate(portId); - - return IX_ETH_ACC_SUCCESS; -} - -/* PRIVATE Functions*/ - -PRIVATE void -ixEthAccMacStateUpdate(IxEthAccPortId portId) -{ - UINT32 regval; - - if ( ixEthAccMacState[portId].enabled == false ) - { - /* Just disable both the transmitter and reciver in the MAC. */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN); - - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN); - } - - if(ixEthAccMacState[portId].fullDuplex) - { - ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_FULL_DUPLEX); - } - else - { - ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_HALF_DUPLEX); - } - - if(ixEthAccMacState[portId].rxFCSAppend) - { - ixEthAccPortRxFrameAppendFCSEnablePriv (portId); - } - else - { - ixEthAccPortRxFrameAppendFCSDisablePriv (portId); - } - - if(ixEthAccMacState[portId].txFCSAppend) - { - ixEthAccPortTxFrameAppendFCSEnablePriv (portId); - } - else - { - ixEthAccPortTxFrameAppendFCSDisablePriv (portId); - } - - if(ixEthAccMacState[portId].txPADAppend) - { - ixEthAccPortTxFrameAppendPaddingEnablePriv (portId); - } - else - { - ixEthAccPortTxFrameAppendPaddingDisablePriv (portId); - } - - if(ixEthAccMacState[portId].promiscuous) - { - ixEthAccPortPromiscuousModeSetPriv(portId); - } - else - { - ixEthAccPortPromiscuousModeClearPriv(portId); - } - - if ( ixEthAccMacState[portId].enabled == true ) - { - /* Enable both the transmitter and reciver in the MAC. */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_RX_EN); - - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval | IX_ETH_ACC_TX_CNTRL1_TX_EN); - } -} - - -PRIVATE BOOL -ixEthAccMacEqual(IxEthAccMacAddr *macAddr1, - IxEthAccMacAddr *macAddr2) -{ - UINT32 i; - for(i=0;imacAddress[i] != macAddr2->macAddress[i]) - { - return false; - } - } - return true; -} - -PRIVATE void -ixEthAccMacPrint(IxEthAccMacAddr *m) -{ - printf("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x", - m->macAddress[0], m->macAddress[1], - m->macAddress[2], m->macAddress[3], - m->macAddress[4], m->macAddress[5]); -} - -/* Set the multicast address and address mask registers - * - * A bit in the address mask register must be set if - * all multicast addresses always have that bit set, or if - * all multicast addresses always have that bit cleared. - * - * A bit in the address register must be set if all multicast - * addresses have that bit set, otherwise, it should be cleared - */ - -PRIVATE void -ixEthAccMulticastAddressSet(IxEthAccPortId portId) -{ - UINT32 i; - UINT32 j; - IxEthAccMacAddr addressMask; - IxEthAccMacAddr address; - IxEthAccMacAddr alwaysClearBits; - IxEthAccMacAddr alwaysSetBits; - - /* calculate alwaysClearBits and alwaysSetBits: - * alwaysClearBits is calculated by ORing all - * multicast addresses, those bits that are always - * clear are clear in the result - * - * alwaysSetBits is calculated by ANDing all - * multicast addresses, those bits that are always set - * are set in the result - */ - - if (ixEthAccMacState[portId].promiscuous == true) - { - /* Promiscuous Mode is set, and filtering - * allow all packets, and enable the mcast and - * bcast detection. - */ - memset(&addressMask.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(&address.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else - { - if(ixEthAccMacState[portId].joinAll == true) - { - /* Join all is set. The mask and address are - * the multicast settings. - */ - IxEthAccMacAddr macAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - memcpy(addressMask.macAddress, - macAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - memcpy(address.macAddress, - macAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else if(ixEthAccMacState[portId].mcastAddrIndex == 0) - { - /* No entry in the filtering database, - * Promiscuous Mode is cleared, Broadcast filtering - * is configured. - */ - memset(addressMask.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(address.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else - { - /* build a mask and an address which mix all entreis - * from the list of multicast addresses - */ - memset(alwaysClearBits.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(alwaysSetBits.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - - for(i=0;i> 8) & 0xff); - - REG_WRITE(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_3, - (mdioCommand >> 16) & 0xff); - - REG_WRITE(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_4, - (mdioCommand >> 24) & 0xff); -} - -PRIVATE void -ixEthAccMdioCmdRead(UINT32 *data) -{ - UINT32 regval; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_1, - regval); - - *data = regval & 0xff; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_2, - regval); - - *data |= (regval & 0xff) << 8; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_3, - regval); - - *data |= (regval & 0xff) << 16; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_4, - regval); - - *data |= (regval & 0xff) << 24; - -} - -PRIVATE void -ixEthAccMdioStatusRead(UINT32 *data) -{ - UINT32 regval; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_1, - regval); - - *data = regval & 0xff; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_2, - regval); - - *data |= (regval & 0xff) << 8; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_3, - regval); - - *data |= (regval & 0xff) << 16; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_4, - regval); - - *data |= (regval & 0xff) << 24; - -} - - -/******************************************************************** - * ixEthAccMiiInit - */ -IxEthAccStatus -ixEthAccMiiInit() -{ - if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE); - - if (miiBaseAddressVirt == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MII I/O mapped memory\n", - 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -void -ixEthAccMiiUnload(void) -{ - IX_OSAL_MEM_UNMAP(miiBaseAddressVirt); - - miiBaseAddressVirt = 0; -} - -PUBLIC IxEthAccStatus -ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount) -{ - if (retryCount < 1) return IX_ETH_ACC_FAIL; - - ixEthAccMiiRetryCount = retryCount; - ixEthAccMiiAccessTimeout = timeout; - - return IX_ETH_ACC_SUCCESS; -} - -/********************************************************************* - * ixEthAccMiiReadRtn - read a 16 bit value from a PHY - */ -IxEthAccStatus -ixEthAccMiiReadRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 *value) -{ - UINT32 mdioCommand; - UINT32 regval; - UINT32 miiTimeout; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) - || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG)) - { - return (IX_ETH_ACC_FAIL); - } - - if (value == NULL) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL - | phyAddr << IX_ETH_ACC_MII_ADDR_SHL; - mdioCommand |= IX_ETH_ACC_MII_GO; - - ixEthAccMdioCmdWrite(mdioCommand); - - miiTimeout = ixEthAccMiiRetryCount; - - while(miiTimeout) - { - - ixEthAccMdioCmdRead(®val); - - if((regval & IX_ETH_ACC_MII_GO) == 0x0) - { - break; - } - /* Sleep for a while */ - ixOsalSleep(ixEthAccMiiAccessTimeout); - miiTimeout--; - } - - - - if(miiTimeout == 0) - { - ixOsalMutexUnlock(&miiAccessLock); - *value = 0xffff; - return IX_ETH_ACC_FAIL; - } - - - ixEthAccMdioStatusRead(®val); - if(regval & IX_ETH_ACC_MII_READ_FAIL) - { - ixOsalMutexUnlock(&miiAccessLock); - *value = 0xffff; - return IX_ETH_ACC_FAIL; - } - - *value = regval & 0xffff; - ixOsalMutexUnlock(&miiAccessLock); - return IX_ETH_ACC_SUCCESS; - -} - - -/********************************************************************* - * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY - */ -IxEthAccStatus -ixEthAccMiiWriteRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 value) -{ - UINT32 mdioCommand; - UINT32 regval; - UINT16 readVal; - UINT32 miiTimeout; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) - || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG)) - { - return (IX_ETH_ACC_FAIL); - } - - /* ensure that a PHY is present at this address */ - if(ixEthAccMiiReadRtn(phyAddr, - IX_ETH_ACC_MII_CTRL_REG, - &readVal) != IX_ETH_ACC_SUCCESS) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL - | phyAddr << IX_ETH_ACC_MII_ADDR_SHL ; - mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value; - - ixEthAccMdioCmdWrite(mdioCommand); - - miiTimeout = ixEthAccMiiRetryCount; - - while(miiTimeout) - { - - ixEthAccMdioCmdRead(®val); - - /*The "GO" bit is reset to 0 when the write completes*/ - if((regval & IX_ETH_ACC_MII_GO) == 0x0) - { - break; - } - /* Sleep for a while */ - ixOsalSleep(ixEthAccMiiAccessTimeout); - miiTimeout--; - } - - ixOsalMutexUnlock(&miiAccessLock); - if(miiTimeout == 0) - { - return IX_ETH_ACC_FAIL; - } - return IX_ETH_ACC_SUCCESS; -} - - -/***************************************************************** - * - * Phy query functions - * - */ -IxEthAccStatus -ixEthAccMiiStatsShow (UINT32 phyAddr) -{ - UINT16 regval; - printf("Regisers on PHY at address 0x%x\n", phyAddr); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, ®val); - printf(" Control Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_STAT_REG, ®val); - printf(" Status Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID1_REG, ®val); - printf(" PHY ID1 Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID2_REG, ®val); - printf(" PHY ID2 Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_ADS_REG, ®val); - printf(" Auto Neg ADS Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_PRTN_REG, ®val); - printf(" Auto Neg Partner Ability Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_EXP_REG, ®val); - printf(" Auto Neg Expansion Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_NEXT_REG, ®val); - printf(" Auto Neg Next Register : 0x%4.4x\n", regval); - - return IX_ETH_ACC_SUCCESS; -} - - -/***************************************************************** - * - * Interface query functions - * - */ -IxEthAccStatus -ixEthAccMdioShow (void) -{ - UINT32 regval; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - ixEthAccMdioCmdRead(®val); - ixOsalMutexUnlock(&miiAccessLock); - - printf("MDIO command register\n"); - printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31); - printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26); - printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f); - printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f); - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - ixEthAccMdioStatusRead(®val); - ixOsalMutexUnlock(&miiAccessLock); - - printf("MDIO status register\n"); - printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31); - printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff); - - return IX_ETH_ACC_SUCCESS; -} - diff --git a/drivers/net/npe/IxEthDBAPI.c b/drivers/net/npe/IxEthDBAPI.c deleted file mode 100644 index d46c47c2ef..0000000000 --- a/drivers/net/npe/IxEthDBAPI.c +++ /dev/null @@ -1,448 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" -#include "IxFeatureCtrl.h" - -extern HashTable dbHashtable; -extern IxEthDBPortMap overflowUpdatePortList; -extern BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - return ixEthDBTriggerAddPortUpdate(macAddr, portID, true); -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - return ixEthDBTriggerAddPortUpdate(macAddr, portID, false); -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - ixEthDBReleaseHashNode(searchResult); - - /* build a remove event and place it on the event queue */ - return ixEthDBTriggerRemovePortUpdate(macAddr, ((MacDescriptor *) searchResult->data)->portID); -} - -IX_ETH_DB_PUBLIC -void ixEthDBDatabaseMaintenance() -{ - HashIterator iterator; - UINT32 portIndex; - BOOL agingRequired = false; - - /* ports who will have deleted records and therefore will need updating */ - IxEthDBPortMap triggerPorts; - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED != - ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - return; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - /* check if there's at least a port that needs aging */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled) - { - agingRequired = true; - } - } - - if (agingRequired) - { - /* ask each NPE port to write back the database for aging inspection */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE - && ixEthDBPortInfo[portIndex].agingEnabled - && ixEthDBPortInfo[portIndex].enabled) - { - IxNpeMhMessage message; - IX_STATUS result; - - /* send EDB_GetMACAddressDatabase message */ - FILL_GETMACADDRESSDATABASE(message, - 0 /* unused */, - IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), message, result); - - if (result == IX_SUCCESS) - { - /* analyze NPE copy */ - ixEthDBNPESyncScan(portIndex, ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone, FULL_ELT_BYTE_SIZE); - - IX_ETH_DB_SUPPORT_TRACE("DB: (API) Finished scanning NPE tree on port %d\n", portIndex); - } - else - { - ixEthDBPortInfo[portIndex].agingEnabled = false; - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; - ixEthDBPortInfo[portIndex].updateMethod.userControlled = true; - - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthDB: (Maintenance) warning, disabling aging and updates for port %d (assumed dead)\n", - portIndex, 0, 0, 0, 0, 0); - - ixEthDBDatabaseClear(portIndex, IX_ETH_DB_ALL_RECORD_TYPES); - } - } - } - - /* browse database and age entries */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - UINT32 *age = NULL; - BOOL staticEntry = true; - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - age = &descriptor->recordData.filteringData.age; - staticEntry = descriptor->recordData.filteringData.staticEntry; - } - else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - age = &descriptor->recordData.filteringVlanData.age; - staticEntry = descriptor->recordData.filteringVlanData.staticEntry; - } - else - { - staticEntry = true; - } - - if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false)) - { - /* manually increment the age if the port has no such capability */ - if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0) - { - *age += (IX_ETH_DB_MAINTENANCE_TIME / 60); - } - - /* age entry if it exceeded the maximum time to live */ - if (*age >= (IX_ETH_DB_LEARNING_ENTRY_AGE_TIME / 60)) - { - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID); - - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - /* update ports which lost records */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - } -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType) -{ - IxEthDBPortMap triggerPorts; - HashIterator iterator; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS && portID != IX_ETH_DB_ALL_PORTS) - { - return IX_ETH_DB_INVALID_PORT; - } - - /* check if the user passes some extra bits */ - if ((recordType | IX_ETH_DB_ALL_RECORD_TYPES) != IX_ETH_DB_ALL_RECORD_TYPES) - { - return IX_ETH_DB_INVALID_ARG; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - /* browse database and age entries */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (((descriptor->portID == portID) || (portID == IX_ETH_DB_ALL_PORTS)) - && ((descriptor->type & recordType) != 0)) - { - /* add to trigger if automatic updates are required */ - if (ixEthDBPortUpdateRequired[descriptor->type]) - { - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID); - } - - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - /* update ports which lost records */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - IxEthDBStatus result = IX_ETH_DB_NO_SUCH_ADDR; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - if (((MacDescriptor *) (searchResult->data))->portID == portID) - { - result = IX_ETH_DB_SUCCESS; /* address and port match */ - } - - ixEthDBReleaseHashNode(searchResult); - - return result; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - - IX_ETH_DB_CHECK_REFERENCE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - /* return the port ID */ - *portID = ((MacDescriptor *) searchResult->data)->portID; - - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - ixEthDBPortInfo[portID].agingEnabled = false; - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - ixEthDBPortInfo[portID].agingEnabled = true; - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* return the port ID */ - *portID = descriptor->portID; - - /* reset entry age */ - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - descriptor->recordData.filteringData.age = 0; - } - else - { - descriptor->recordData.filteringVlanData.age = 0; - } - - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - /* force bit at offset 255 to 0 (reserved) */ - dependencyPortMap[31] &= 0xFE; - - COPY_DEPENDENCY_MAP(ixEthDBPortInfo[portID].dependencyPortMap, dependencyPortMap); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - COPY_DEPENDENCY_MAP(dependencyPortMap, ixEthDBPortInfo[portID].dependencyPortMap); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate; - ixEthDBPortInfo[portID].updateMethod.userControlled = true; - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBAPISupport.c b/drivers/net/npe/IxEthDBAPISupport.c deleted file mode 100644 index 1facb89fd8..0000000000 --- a/drivers/net/npe/IxEthDBAPISupport.c +++ /dev/null @@ -1,675 +0,0 @@ -/** - * @file IxEthDBAPISupport.c - * - * @brief Public API support functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include -#include -#include - -#include "IxEthDB_p.h" -#include "IxEthDBMessages_p.h" -#include "IxEthDB_p.h" -#include "IxEthDBLog_p.h" - -#ifdef IX_UNIT_TEST - -int dbAccessCounter = 0; -int overflowEvent = 0; - -#endif - -/* - * External declaration - */ -extern HashTable dbHashtable; - -/* - * Internal declaration - */ -IX_ETH_DB_PUBLIC -PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS]; - -IX_ETH_DB_PRIVATE -struct -{ - BOOL saved; - IxEthDBPriorityTable priorityTable; - IxEthDBVlanSet vlanMembership; - IxEthDBVlanSet transmitTaggingInfo; - IxEthDBFrameFilter frameFilter; - IxEthDBTaggingAction taggingAction; - IxEthDBFirewallMode firewallMode; - BOOL stpBlocked; - BOOL srcAddressFilterEnabled; - UINT32 maxRxFrameSize; - UINT32 maxTxFrameSize; -} ixEthDBPortState[IX_ETH_DB_NUMBER_OF_PORTS]; - -#define IX_ETH_DB_DEFAULT_FRAME_SIZE (1518) - -/** - * @brief initializes a port - * - * @param portID ID of the port to be initialized - * - * Note that redundant initializations are silently - * dealt with and do not constitute an error - * - * This function is fully documented in the main - * header file, IxEthDB.h - */ -IX_ETH_DB_PUBLIC -void ixEthDBPortInit(IxEthDBPortId portID) -{ - PortInfo *portInfo; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS) - { - return; - } - - portInfo = &ixEthDBPortInfo[portID]; - - if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) - { - WARNING_LOG("EthDB: Unavailable Eth %d: Cannot initialize EthDB Port.\n", (UINT32) portID); - - return; - } - - if (portInfo->initialized) - { - /* redundant */ - return; - } - - /* initialize core fields */ - portInfo->portID = portID; - SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID); - - /* default values */ - portInfo->agingEnabled = false; - portInfo->enabled = false; - portInfo->macAddressUploaded = false; - portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; - portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; - - /* default update control values */ - portInfo->updateMethod.searchTree = NULL; - portInfo->updateMethod.searchTreePendingWrite = false; - portInfo->updateMethod.treeInitialized = false; - portInfo->updateMethod.updateEnabled = false; - portInfo->updateMethod.userControlled = false; - - /* default WiFi parameters */ - memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid)); - portInfo->frameControlDurationID = 0; - - /* Ethernet NPE-specific initializations */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - /* update handler */ - portInfo->updateMethod.updateHandler = ixEthDBNPEUpdateHandler; - } - - /* initialize state save */ - ixEthDBPortState[portID].saved = false; - - portInfo->initialized = true; -} - -/** - * @brief enables a port - * - * @param portID ID of the port to enable - * - * This function is fully documented in the main - * header file, IxEthDB.h - * - * @return IX_ETH_DB_SUCCESS if enabling was - * accomplished, or a meaningful error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) -{ - IxEthDBPortMap triggerPorts; - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - if (portInfo->enabled) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - SET_DEPENDENCY_MAP(triggerPorts, portID); - - /* mark as enabled */ - portInfo->enabled = true; - - /* Operation stops here when Ethernet Learning is not enabled */ - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == - ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) - { - return IX_ETH_DB_SUCCESS; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE && !portInfo->macAddressUploaded) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) MAC address not set on port %d, enable failed\n", portID); - - /* must use UnicastAddressSet() before enabling an NPE port */ - return IX_ETH_DB_MAC_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Attempting to enable the NPE callback for port %d...\n", portID); - - if (!portInfo->updateMethod.userControlled - && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)) - { - portInfo->updateMethod.updateEnabled = true; - } - - /* if this is first time initialization then we already have - write access to the tree and can AccessRelease directly */ - if (!portInfo->updateMethod.treeInitialized) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Initializing tree for port %d\n", portID); - - /* create an initial tree and release access into it */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - - /* mark tree as being initialized */ - portInfo->updateMethod.treeInitialized = true; - } - } - - if (ixEthDBPortState[portID].saved) - { - /* previous configuration data stored, restore state */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - ixEthDBFirewallModeSet(portID, ixEthDBPortState[portID].firewallMode); - ixEthDBFirewallInvalidAddressFilterEnable(portID, ixEthDBPortState[portID].srcAddressFilterEnabled); - } - -#if 0 /* test-only */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - ixEthDBAcceptableFrameTypeSet(portID, ixEthDBPortState[portID].frameFilter); - ixEthDBIngressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].taggingAction); - - ixEthDBEgressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].transmitTaggingInfo); - ixEthDBPortVlanMembershipSet(portID, ixEthDBPortState[portID].vlanMembership); - - ixEthDBPriorityMappingTableSet(portID, ixEthDBPortState[portID].priorityTable); - } -#endif - - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - ixEthDBSpanningTreeBlockingStateSet(portID, ixEthDBPortState[portID].stpBlocked); - } - - ixEthDBFilteringPortMaximumRxFrameSizeSet(portID, ixEthDBPortState[portID].maxRxFrameSize); - ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize); - - /* discard previous save */ - ixEthDBPortState[portID].saved = false; - } - - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief disables a port - * - * @param portID ID of the port to disable - * - * This function is fully documented in the - * main header file, IxEthDB.h - * - * @return IX_ETH_DB_SUCCESS if disabling was - * successful or an appropriate error message - * otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) -{ - HashIterator iterator; - IxEthDBPortMap triggerPorts; /* ports who will have deleted records and therefore will need updating */ - BOOL result; - PortInfo *portInfo; - IxEthDBFeature learningEnabled; -#if 0 /* test-only */ - IxEthDBPriorityTable classZeroTable; -#endif - - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - if (!portInfo->enabled) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - /* save filtering state */ - ixEthDBPortState[portID].firewallMode = portInfo->firewallMode; - ixEthDBPortState[portID].frameFilter = portInfo->frameFilter; - ixEthDBPortState[portID].taggingAction = portInfo->taggingAction; - ixEthDBPortState[portID].stpBlocked = portInfo->stpBlocked; - ixEthDBPortState[portID].srcAddressFilterEnabled = portInfo->srcAddressFilterEnabled; - ixEthDBPortState[portID].maxRxFrameSize = portInfo->maxRxFrameSize; - ixEthDBPortState[portID].maxTxFrameSize = portInfo->maxTxFrameSize; - - memcpy(ixEthDBPortState[portID].vlanMembership, portInfo->vlanMembership, sizeof (IxEthDBVlanSet)); - memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet)); - memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable)); - - ixEthDBPortState[portID].saved = true; - - /* now turn off all EthDB filtering features on the port */ - -#if 0 /* test-only */ - /* VLAN & QoS */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); - ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false); - ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH); - - memset(classZeroTable, 0, sizeof (classZeroTable)); - ixEthDBPriorityMappingTableSet((IxEthDBPortId) portID, classZeroTable); - } -#endif - - /* STP */ - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false); - } - - /* Firewall */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - ixEthDBFirewallTableDownload((IxEthDBPortId) portID); - ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false); - } - - /* Frame size filter */ - ixEthDBFilteringPortMaximumFrameSizeSet((IxEthDBPortId) portID, IX_ETH_DB_DEFAULT_FRAME_SIZE); - - /* WiFi */ - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - ixEthDBWiFiConversionTableDownload((IxEthDBPortId) portID); - } - - /* save and disable the learning feature bit */ - learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING; - portInfo->featureStatus &= ~IX_ETH_DB_LEARNING; - } - else - { - /* save the learning feature bit */ - learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - ixEthDBUpdateLock(); - - /* wipe out current entries for this port */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - /* check if the port match. If so, remove the entry */ - if (descriptor->portID == portID - && (descriptor->type == IX_ETH_DB_FILTERING_RECORD || descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - && !descriptor->recordData.filteringData.staticEntry) - { - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, portID); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if (portInfo->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(portInfo->updateMethod.searchTree); - portInfo->updateMethod.searchTree = NULL; - } - - ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FILTERING_RECORD); - } - - /* mark as disabled */ - portInfo->enabled = false; - - /* disable updates unless the user has specifically altered the default behavior */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if (!portInfo->updateMethod.userControlled) - { - portInfo->updateMethod.updateEnabled = false; - } - - /* make sure we re-initialize the NPE learning tree when the port is re-enabled */ - portInfo->updateMethod.treeInitialized = false; - } - - ixEthDBUpdateUnlock(); - - /* restore learning feature bit */ - portInfo->featureStatus |= learningEnabled; - - /* if we've removed any records or lost any events make sure to force an update */ - IS_EMPTY_DEPENDENCY_MAP(result, triggerPorts); - - if (!result) - { - ixEthDBUpdatePortLearningTrees(triggerPorts); - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sends the updated maximum Tx/Rx frame lengths to the NPE - * - * @param portID ID of the port to update - * - * @return IX_ETH_DB_SUCCESS if the update completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortFrameLengthsUpdate(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IX_STATUS result; - - FILL_SETMAXFRAMELENGTHS_MSG(message, portID, portInfo->maxRxFrameSize, portInfo->maxTxFrameSize); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the port maximum Rx frame size - * - * @param portID ID of the port to set the frame size on - * @param maximumRxFrameSize maximum Rx frame size - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumRxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumRxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxRxFrameSize = maximumRxFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the port maximum Tx frame size - * - * @param portID ID of the port to set the frame size on - * @param maximumTxFrameSize maximum Tx frame size - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumTxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumTxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxTxFrameSize = maximumTxFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the port maximum Tx and Rx frame sizes - * - * @param portID ID of the port to set the frame size on - * @param maximumFrameSize maximum Tx and Rx frame sizes - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * Note that both the maximum Tx and Rx frame size are set - * to the same value. This function is kept for compatibility - * reasons. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxRxFrameSize = maximumFrameSize; - ixEthDBPortInfo[portID].maxTxFrameSize = maximumFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the MAC address of an NPE port - * - * @param portID port ID to set the MAC address on - * @param macAddr pointer to the 6-byte MAC address - * - * This function is called by the EthAcc - * ixEthAccUnicastMacAddressSet() and should not be - * manually invoked unless required by special circumstances. - * - * @return IX_ETH_DB_SUCCESS if the operation succeeded - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IxNpeMhMessage message; - IX_STATUS result; - - /* use this macro instead CHECK_PORT - as the port doesn't need to be enabled */ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - /* Operation stops here when Ethernet Learning is not enabled */ - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == - ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) - { - return IX_ETH_DB_SUCCESS; - } - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - /* exit if the port is not an Ethernet NPE */ - if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE) - { - return IX_ETH_DB_INVALID_PORT; - } - - /* populate message */ - FILL_SETPORTADDRESS_MSG(message, portID, macAddr->macAddress); - - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Sending SetPortAddress on port %d...\n", portID); - - /* send a SetPortAddress message */ - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - ixEthDBPortInfo[portID].macAddressUploaded = true; - } - - return result; -} diff --git a/drivers/net/npe/IxEthDBCore.c b/drivers/net/npe/IxEthDBCore.c deleted file mode 100644 index 8b3c1d9a80..0000000000 --- a/drivers/net/npe/IxEthDBCore.c +++ /dev/null @@ -1,463 +0,0 @@ -/** - * @file IxEthDBDBCore.c - * - * @brief Database support functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* list of database hashtables */ -IX_ETH_DB_PUBLIC HashTable dbHashtable; -IX_ETH_DB_PUBLIC MatchFunction matchFunctions[IX_ETH_DB_MAX_KEY_INDEX + 1]; -IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -/* private initialization flag */ -IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false; - -/** - * @brief initializes EthDB - * - * This function must be called to initialize the component. - * - * It does the following things: - * - checks the port definition structure - * - scans the capabilities of the NPE images and sets the - * capabilities of the ports accordingly - * - initializes the memory pools internally used in EthDB - * for storing database records and handling data - * - registers automatic update handlers for add and remove - * operations - * - registers hashing match functions, depending on key sets - * - initializes the main database hashtable - * - allocates contiguous memory zones to be used for NPE - * updates - * - registers the serialize methods used to convert data - * into NPE-readable format - * - starts the event processor - * - * Note that this function is documented in the public - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS or an appropriate error if the - * component failed to initialize correctly - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBInit(void) -{ - IxEthDBStatus result; - - if (ethDBInitializationComplete) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - /* trap an invalid port definition structure */ - IX_ETH_DB_PORTS_ASSERTION; - - /* memory management */ - ixEthDBInitMemoryPools(); - - /* register hashing search methods */ - ixEthDBMatchMethodsRegister(matchFunctions); - - /* register type-based automatic port updates */ - ixEthDBUpdateTypeRegister(ixEthDBPortUpdateRequired); - - /* register record to key type mappings */ - ixEthDBKeyTypeRegister(ixEthDBKeyType); - - /* hash table */ - ixEthDBInitHash(&dbHashtable, NUM_BUCKETS, ixEthDBEntryXORHash, matchFunctions, (FreeFunction) ixEthDBFreeMacDescriptor); - - /* NPE update zones */ - ixEthDBNPEUpdateAreasInit(); - - /* register record serialization methods */ - ixEthDBRecordSerializeMethodsRegister(); - - /* start the event processor */ - result = ixEthDBEventProcessorInit(); - - /* scan NPE features */ - if (result == IX_ETH_DB_SUCCESS) - { - ixEthDBFeatureCapabilityScan(); - } - - ethDBInitializationComplete = true; - - return result; -} - -/** - * @brief prepares EthDB for unloading - * - * This function must be called before removing the - * EthDB component from memory (e.g. doing rmmod in - * Linux) if the component is to be re-initialized again - * without rebooting the platform. - * - * All the EthDB ports must be disabled before this - * function is to be called. Failure to disable all - * the ports will return the IX_ETH_DB_BUSY error. - * - * This function will destroy mutexes, deallocate - * memory and stop the event processor. - * - * Note that this function is fully documented in the - * main component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if de-initialization - * completed successfully or an appropriate error - * message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUnload(void) -{ - IxEthDBPortId portIndex; - - if (!ethDBInitializationComplete) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - /* check if any ports are enabled */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortInfo[portIndex].enabled) - { - return IX_ETH_DB_BUSY; - } - } - - /* free port resources */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock); - } - - ixEthDBPortInfo[portIndex].initialized = false; - } - - /* shutdown event processor */ - ixEthDBStopLearningFunction(); - - /* deallocate NPE update zones */ - ixEthDBNPEUpdateAreasUnload(); - - ethDBInitializationComplete = false; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief adds a new entry to the Ethernet database - * - * @param newRecordTemplate address of the record template to use - * @param updateTrigger port map containing the update triggers - * resulting from this update operation - * - * Creates a new database entry, populates it with the data - * copied from the given template and adds the record to the - * database hash table. - * It also checks whether the new record type is registered to trigger - * automatic updates; if it is, the update trigger will contain the - * port on which the record insertion was performed, as well as the - * old port in case the addition was a record migration (from one port - * to the other). The caller can use the updateTrigger to trigger - * automatic updates on the ports changed as a result of this addition. - * - * @retval IX_ETH_DB_SUCCESS addition successful - * @retval IX_ETH_DB_NOMEM insertion failed, no memory left in the mac descriptor memory pool - * @retval IX_ETH_DB_BUSY database busy, cannot insert due to locking - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger) -{ - IxEthDBStatus result; - MacDescriptor *newDescriptor; - IxEthDBPortId originalPortID; - HashNode *node = NULL; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, ixEthDBKeyType[newRecordTemplate->type], newRecordTemplate, &node)); - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (node == NULL) - { - /* not found, create a new one */ - newDescriptor = ixEthDBAllocMacDescriptor(); - - if (newDescriptor == NULL) - { - return IX_ETH_DB_NOMEM; /* no memory */ - } - - /* old port does not exist, avoid unnecessary updates */ - originalPortID = newRecordTemplate->portID; - } - else - { - /* a node with the same key exists, will update node */ - newDescriptor = (MacDescriptor *) node->data; - - /* save original port id */ - originalPortID = newDescriptor->portID; - } - - /* copy/update fields into new record */ - memcpy(newDescriptor->macAddress, newRecordTemplate->macAddress, sizeof (IxEthDBMacAddr)); - memcpy(&newDescriptor->recordData, &newRecordTemplate->recordData, sizeof (IxEthDBRecordData)); - - newDescriptor->type = newRecordTemplate->type; - newDescriptor->portID = newRecordTemplate->portID; - newDescriptor->user = newRecordTemplate->user; - - if (node == NULL) - { - /* new record, insert into hashtable */ - BUSY_RETRY_WITH_RESULT(ixEthDBAddHashEntry(&dbHashtable, newDescriptor), result); - - if (result != IX_ETH_DB_SUCCESS) - { - ixEthDBFreeMacDescriptor(newDescriptor); - - return result; /* insertion failed */ - } - } - - if (node != NULL) - { - /* release access */ - ixEthDBReleaseHashNode(node); - } - - /* trigger add/remove update if required by type */ - if (updateTrigger != NULL && - ixEthDBPortUpdateRequired[newRecordTemplate->type]) - { - /* add new port to update list */ - JOIN_PORT_TO_MAP(updateTrigger, newRecordTemplate->portID); - - /* check if record has moved, we'll need to update the old port as well */ - if (originalPortID != newDescriptor->portID) - { - JOIN_PORT_TO_MAP(updateTrigger, originalPortID); - } - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief remove a record from the Ethernet database - * - * @param templateRecord template record used to determine - * what record is to be removed - * @param updateTrigger port map containing the update triggers - * resulting from this update operation - * - * This function will examine the template record it receives - * and attempts to delete a record of the same type and containing - * the same keys as the template record. If deletion is successful - * and the record type is registered for automatic port updates the - * port will also be set in the updateTrigger port map, so that the - * client can perform an update of the port. - * - * @retval IX_ETH_DB_SUCCESS removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR the record with the given MAC address was not found - * @retval IX_ETH_DB_BUSY database busy, cannot remove due to locking - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger) -{ - IxEthDBStatus result; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - BUSY_RETRY_WITH_RESULT(ixEthDBRemoveHashEntry(&dbHashtable, ixEthDBKeyType[templateRecord->type], templateRecord), result); - - if (result != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - /* trigger add/remove update if required by type */ - if (updateTrigger != NULL - &&ixEthDBPortUpdateRequired[templateRecord->type]) - { - /* add new port to update list */ - JOIN_PORT_TO_MAP(updateTrigger, templateRecord->portID); - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief register record key types - * - * This function registers the appropriate key types, - * depending on record types. - * - * All filtering records use the MAC address as the key. - * WiFi and Firewall records use a compound key consisting - * in both the MAC address and the port ID. - * - * @return the number of registered record types - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType) -{ - /* safety */ - memset(keyType, 0, sizeof (keyType)); - - /* register all known record types */ - keyType[IX_ETH_DB_FILTERING_RECORD] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_FILTERING_VLAN_RECORD] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_ALL_FILTERING_RECORDS] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_WIFI_RECORD] = IX_ETH_DB_MAC_PORT_KEY; - keyType[IX_ETH_DB_FIREWALL_RECORD] = IX_ETH_DB_MAC_PORT_KEY; - - return 5; -} - -/** - * @brief Sets a user-defined field into a database record - * - * Note that this function is fully documented in the main component - * header file. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field) -{ - HashNode *result = NULL; - - if (macAddr == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - if (recordType == IX_ETH_DB_FILTERING_RECORD) - { - result = ixEthDBSearch(macAddr, recordType); - } - else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - result = ixEthDBVlanSearch(macAddr, vlanID, recordType); - } - else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD) - { - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - result = ixEthDBPortSearch(macAddr, portID, recordType); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - if (result == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - ((MacDescriptor *) result->data)->user = field; - - ixEthDBReleaseHashNode(result); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief Retrieves a user-defined field from a database record - * - * Note that this function is fully documented in the main component - * header file. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field) -{ - HashNode *result = NULL; - - if (macAddr == NULL || field == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - if (recordType == IX_ETH_DB_FILTERING_RECORD) - { - result = ixEthDBSearch(macAddr, recordType); - } - else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - result = ixEthDBVlanSearch(macAddr, vlanID, recordType); - } - else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD) - { - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - result = ixEthDBPortSearch(macAddr, portID, recordType); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - if (result == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - *field = ((MacDescriptor *) result->data)->user; - - ixEthDBReleaseHashNode(result); - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBEvents.c b/drivers/net/npe/IxEthDBEvents.c deleted file mode 100644 index 529063d1ff..0000000000 --- a/drivers/net/npe/IxEthDBEvents.c +++ /dev/null @@ -1,520 +0,0 @@ -/** - * @file IxEthDBEvents.c - * - * @brief Implementation of the event processor component - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include -#include - -#include "IxEthDB_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *); -IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PRIVATE void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts); -IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void); - -/* data */ -IX_ETH_DB_PRIVATE IxOsalSemaphore eventQueueSemaphore; -IX_ETH_DB_PRIVATE PortEventQueue eventQueue; -IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock; -IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock; - -IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = false; -IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false; - -/* imported data */ -extern HashTable dbHashtable; - -/** - * @brief initializes the event processor - * - * Initializes the event processor queue and processing thread. - * Called from ixEthDBInit() DB-subcomponent master init function. - * - * @warning do not call directly - * - * @retval IX_ETH_DB_SUCCESS initialization was successful - * @retval IX_ETH_DB_FAIL initialization failed (OSAL or mutex init failure) - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEventProcessorInit(void) -{ - if (ixOsalMutexInit(&portUpdateLock) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - if (ixOsalMutexInit(&eventQueueLock) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == - ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - - /* start processor loop thread */ - if (ixEthDBStartLearningFunction() != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief initializes the event queue and the event processor - * - * This function is called by the component initialization - * function, ixEthDBInit(). - * - * @warning do not call directly - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBStartLearningFunction(void) -{ - IxOsalThread eventProcessorThread; - IxOsalThreadAttr threadAttr; - - threadAttr.name = "EthDB event thread"; - threadAttr.stackSize = 32 * 1024; /* 32kbytes */ - threadAttr.priority = 128; - - /* reset event queue */ - ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); - - RESET_QUEUE(&eventQueue); - - ixOsalMutexUnlock(&eventQueueLock); - - /* init event queue semaphore */ - if (ixOsalSemaphoreInit(&eventQueueSemaphore, 0) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - ixEthDBLearningShutdown = false; - - /* create processor loop thread */ - if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - /* start event processor */ - ixOsalThreadStart(&eventProcessorThread); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief stops the event processor - * - * Stops the event processor and frees the event queue semaphore - * Called by the component de-initialization function, ixEthDBUnload() - * - * @warning do not call directly - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise; - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBStopLearningFunction(void) -{ - ixEthDBLearningShutdown = true; - - /* wake up event processing loop to actually process the shutdown event */ - ixOsalSemaphorePost(&eventQueueSemaphore); - - if (ixOsalSemaphoreDestroy(&eventQueueSemaphore) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief default NPE event processing callback - * - * @param npeID ID of the NPE that generated the event - * @param msg NPE message (encapsulated event) - * - * Creates an event object on the Ethernet event processor queue - * and signals the new event by incrementing the event queue semaphore. - * Events are processed by @ref ixEthDBEventProcessorLoop() which runs - * at user level. - * - * @see ixEthDBEventProcessorLoop() - * - * @warning do not call directly - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg) -{ - PortEvent *local_event; - - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) new event received by processor callback from port %d, id 0x%X\n", IX_ETH_DB_NPE_TO_PORT_ID(npeID), NPE_MSG_ID(msg), 0, 0, 0, 0); - - if (CAN_ENQUEUE(&eventQueue)) - { - TEST_FIXTURE_LOCK_EVENT_QUEUE; - - local_event = QUEUE_HEAD(&eventQueue); - - /* create event structure on queue */ - local_event->eventType = NPE_MSG_ID(msg); - local_event->portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID); - - /* update queue */ - PUSH_UPDATE_QUEUE(&eventQueue); - - TEST_FIXTURE_UNLOCK_EVENT_QUEUE; - - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Waking up main processor loop...\n", 0, 0, 0, 0, 0, 0); - - /* increment event queue semaphore */ - ixOsalSemaphorePost(&eventQueueSemaphore); - } - else - { - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Warning: could not enqueue event (overflow)\n", 0, 0, 0, 0, 0, 0); - } -} - -/** - * @brief Ethernet event processor loop - * - * Extracts at most EVENT_PROCESSING_LIMIT batches of events and - * sends them for processing to @ref ixEthDBProcessEvent(). - * Triggers port updates which normally follow learning events. - * - * @warning do not call directly, executes in separate thread - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBEventProcessorLoop(void *unused1) -{ - IxEthDBPortMap triggerPorts; - IxEthDBPortId portIndex; - - ixEthDBEventProcessorRunning = true; - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n"); - - while (!ixEthDBLearningShutdown) - { - BOOL keepProcessing = true; - UINT32 processedEvents = 0; - - IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n"); - - ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER); - - IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n"); - - if (!ixEthDBLearningShutdown) - { - /* port update handling */ - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - while (keepProcessing) - { - PortEvent local_event; - UINT32 intLockKey; - - /* lock queue */ - ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); - - /* lock NPE interrupts */ - intLockKey = ixOsalIrqLock(); - - /* extract event */ - local_event = *(QUEUE_TAIL(&eventQueue)); - - SHIFT_UPDATE_QUEUE(&eventQueue); - - ixOsalIrqUnlock(intLockKey); - - ixOsalMutexUnlock(&eventQueueLock); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType); - - ixEthDBProcessEvent(&local_event, triggerPorts); - - processedEvents++; - - if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */ - || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */ - { - keepProcessing = false; - } - } - - ixEthDBUpdatePortLearningTrees(triggerPorts); - } - } - - /* turn off automatic updates */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; - } - - ixEthDBEventProcessorRunning = false; -} - -/** - * @brief event processor routine - * - * @param event event to be processed - * @param triggerPorts port map accumulating ports to be updated - * - * Processes learning events by synchronizing the database with - * newly learnt data. Called only by @ref ixEthDBEventProcessorLoop(). - * - * @warning do not call directly - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts) -{ - MacDescriptor recordTemplate; - - switch (local_event->eventType) - { - case IX_ETH_DB_ADD_FILTERING_RECORD: - /* add record */ - memset(&recordTemplate, 0, sizeof (recordTemplate)); - memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FILTERING_RECORD; - recordTemplate.portID = local_event->portID; - recordTemplate.recordData.filteringData.staticEntry = local_event->staticEntry; - - ixEthDBAdd(&recordTemplate, triggerPorts); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Added record on port %d\n", local_event->portID); - - break; - - case IX_ETH_DB_REMOVE_FILTERING_RECORD: - /* remove record */ - memset(&recordTemplate, 0, sizeof (recordTemplate)); - memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD; - - ixEthDBRemove(&recordTemplate, triggerPorts); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Removed record on port %d\n", local_event->portID); - - break; - - default: - /* can't handle/not interested in this event type */ - ERROR_LOG("DB: (Events) Event processor received an unknown event type (0x%X)\n", local_event->eventType); - - return; - } -} - -/** - * @brief asynchronously adds a filtering record - * by posting an ADD_FILTERING_RECORD event to the event queue - * - * @param macAddr MAC address of the new record - * @param portID port ID of the new record - * @param staticEntry true if record is static, false if dynamic - * - * @return IX_ETH_DB_SUCCESS if the event creation was - * successfull or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry) -{ - MacDescriptor reference; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - /* fill search fields */ - memcpy(reference.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - reference.portID = portID; - - /* set acceptable record types */ - reference.type = IX_ETH_DB_ALL_FILTERING_RECORDS; - - if (ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference) == IX_ETH_DB_SUCCESS) - { - /* already have an identical record */ - return IX_ETH_DB_SUCCESS; - } - else - { - return ixEthDBTriggerPortUpdate(IX_ETH_DB_ADD_FILTERING_RECORD, macAddr, portID, staticEntry); - } -} - -/** - * @brief asynchronously removes a filtering record - * by posting a REMOVE_FILTERING_RECORD event to the event queue - * - * @param macAddr MAC address of the record to remove - * @param portID port ID of the record to remove - * - * @return IX_ETH_DB_SUCCESS if the event creation was - * successfull or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID) -{ - if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR) - { - return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false); - } - else - { - return IX_ETH_DB_NO_SUCH_ADDR; - } -} - -/** - * @brief adds an ADD or REMOVE event to the main event queue - * - * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD - * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a - * record. - * - * @return IX_ETH_DB_SUCCESS if the event was successfully - * sent or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry) -{ - UINT32 intLockKey; - - /* lock interrupts to protect queue */ - intLockKey = ixOsalIrqLock(); - - if (CAN_ENQUEUE(&eventQueue)) - { - PortEvent *queueEvent = QUEUE_HEAD(&eventQueue); - - /* update fields on the queue */ - memcpy(queueEvent->macAddr.macAddress, macAddr->macAddress, sizeof (IxEthDBMacAddr)); - - queueEvent->eventType = eventType; - queueEvent->portID = portID; - queueEvent->staticEntry = staticEntry; - - PUSH_UPDATE_QUEUE(&eventQueue); - - /* imcrement event queue semaphore */ - ixOsalSemaphorePost(&eventQueueSemaphore); - - /* unlock interrupts */ - ixOsalIrqUnlock(intLockKey); - - return IX_ETH_DB_SUCCESS; - } - else /* event queue full */ - { - /* unlock interrupts */ - ixOsalIrqUnlock(intLockKey); - - return IX_ETH_DB_BUSY; - } -} - -/** - * @brief Locks learning tree updates and port disable - * - * - * This function locks portUpdateLock single mutex. It is primarily used - * to avoid executing 'port disable' during ELT maintenance. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdateLock(void) -{ - ixOsalMutexLock(&portUpdateLock, IX_OSAL_WAIT_FOREVER); -} - -/** - * @brief Unlocks learning tree updates and port disable - * - * - * This function unlocks a portUpdateLock mutex. It is primarily used - * to avoid executing 'port disable' during ELT maintenance. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdateUnlock(void) -{ - ixOsalMutexUnlock(&portUpdateLock); -} - diff --git a/drivers/net/npe/IxEthDBFeatures.c b/drivers/net/npe/IxEthDBFeatures.c deleted file mode 100644 index c5b680a742..0000000000 --- a/drivers/net/npe/IxEthDBFeatures.c +++ /dev/null @@ -1,662 +0,0 @@ -/** - * @file IxEthDBFeatures.c - * - * @brief Implementation of the EthDB feature control API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxNpeDl.h" -#include "IxEthDBQoS.h" -#include "IxEthDB_p.h" - -/** - * @brief scans the capabilities of the loaded NPE images - * - * This function MUST be called by the ixEthDBInit() function. - * No EthDB features (including learning and filtering) are enabled - * before this function is called. - * - * @return none - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFeatureCapabilityScan(void) -{ - IxNpeDlImageId imageId, npeAImageId; - IxEthDBPortId portIndex; - PortInfo *portInfo; - IxEthDBPriorityTable defaultPriorityTable; - IX_STATUS result; - UINT32 queueIndex; - UINT32 queueStructureIndex; - UINT32 trafficClassDefinitionIndex; - - /* read version of NPE A - required to set the AQM queues for B and C */ - npeAImageId.functionalityId = 0; - ixNpeDlLoadedImageGet(IX_NPEDL_NPEID_NPEA, &npeAImageId); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - IxNpeMhMessage msg; - - portInfo = &ixEthDBPortInfo[portIndex]; - - /* check and bypass if NPE B or C is fused out */ - if (ixEthDBSingleEthNpeCheck(portIndex) != IX_ETH_DB_SUCCESS) continue; - - /* all ports are capable of LEARNING by default */ - portInfo->featureCapability |= IX_ETH_DB_LEARNING; - portInfo->featureStatus |= IX_ETH_DB_LEARNING; - - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - - if (ixNpeDlLoadedImageGet(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), &imageId) != IX_SUCCESS) - { - WARNING_LOG("DB: (FeatureScan) NpeDl did not provide the image ID for NPE port %d\n", portIndex); - } - else - { - /* initialize and empty NPE response mutex */ - ixOsalMutexInit(&portInfo->npeAckLock); - ixOsalMutexLock(&portInfo->npeAckLock, IX_OSAL_WAIT_FOREVER); - - /* check NPE response to GetStatus */ - msg.data[0] = IX_ETHNPE_NPE_GETSTATUS << 24; - msg.data[1] = 0; - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), msg, result); - if (result != IX_SUCCESS) - { - WARNING_LOG("DB: (FeatureScan) warning, could not send message to the NPE\n"); - continue; - } - - - if (imageId.functionalityId == 0x00 - || imageId.functionalityId == 0x03 - || imageId.functionalityId == 0x04 - || imageId.functionalityId == 0x80) - { - portInfo->featureCapability |= IX_ETH_DB_FILTERING; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - } - else if (imageId.functionalityId == 0x01 - || imageId.functionalityId == 0x81) - { - portInfo->featureCapability |= IX_ETH_DB_FILTERING; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS; - } - else if (imageId.functionalityId == 0x02 - || imageId.functionalityId == 0x82) - { - portInfo->featureCapability |= IX_ETH_DB_WIFI_HEADER_CONVERSION; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS; - } - - /* reset AQM queues */ - memset(portInfo->ixEthDBTrafficClassAQMAssignments, 0, sizeof (portInfo->ixEthDBTrafficClassAQMAssignments)); - - /* ensure there's at least one traffic class record in the definition table, otherwise we have no default case, hence no queues */ - IX_ENSURE(sizeof (ixEthDBTrafficClassDefinitions) != 0, "DB: no traffic class definitions found, check IxEthDBQoS.h"); - - /* find the traffic class definition index compatible with the current NPE A functionality ID */ - for (trafficClassDefinitionIndex = 0 ; - trafficClassDefinitionIndex < sizeof (ixEthDBTrafficClassDefinitions) / sizeof (ixEthDBTrafficClassDefinitions[0]); - trafficClassDefinitionIndex++) - { - if (ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX] == npeAImageId.functionalityId) - { - /* found it */ - break; - } - } - - /* select the default case if we went over the array boundary */ - if (trafficClassDefinitionIndex == sizeof (ixEthDBTrafficClassDefinitions) / sizeof (ixEthDBTrafficClassDefinitions[0])) - { - trafficClassDefinitionIndex = 0; /* the first record is the default case */ - } - - /* select queue assignment structure based on the traffic class configuration index */ - queueStructureIndex = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX]; - - /* only traffic class 0 is active at initialization time */ - portInfo->ixEthDBTrafficClassCount = 1; - - /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */ - portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS; - portInfo->featureStatus |= IX_ETH_DB_FIREWALL; - portInfo->enabled = true; - -#define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* set VLAN initial configuration (permissive) */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) /* QoS-enabled image */ - { - /* QoS capable */ - portInfo->ixEthDBTrafficClassAvailable = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX]; - - /* set AQM queues */ - for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++) - { - portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = ixEthDBQueueAssignments[queueStructureIndex][queueIndex]; - } - - /* set default PVID (0) and default traffic class 0 */ - ixEthDBPortVlanTagSet(portIndex, 0); - - /* enable reception of all frames */ - ixEthDBAcceptableFrameTypeSet(portIndex, IX_ETH_DB_ACCEPT_ALL_FRAMES); - - /* clear full VLAN membership */ - ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); - - /* clear TTI table - no VLAN tagged frames will be transmitted */ - ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false); - - /* set membership on 0, otherwise no Tx or Rx is working */ - ixEthDBPortVlanMembershipAdd(portIndex, 0); - } - else /* QoS not available in this image */ -#endif /* test-only */ - { - /* initialize traffic class availability (only class 0 is available) */ - portInfo->ixEthDBTrafficClassAvailable = 1; - - /* point all AQM queues to traffic class 0 */ - for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++) - { - portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = - ixEthDBQueueAssignments[queueStructureIndex][0]; - } - } - -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* download priority mapping table and Rx queue configuration */ - memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable)); - ixEthDBPriorityMappingTableSet(portIndex, defaultPriorityTable); -#endif - - /* by default we turn off invalid source MAC address filtering */ - ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false); - - /* disable port, VLAN, Firewall feature bits */ - portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS; - portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL; - portInfo->enabled = false; - - /* enable filtering by default if present */ - if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0) - { - portInfo->featureStatus |= IX_ETH_DB_FILTERING; - } - } - } - } -} - -/** - * @brief returns the capability of a port - * - * @param portID ID of the port - * @param featureSet location to store the port capability in - * - * This function will save the capability set of the given port - * into the given location. Capabilities are bit-ORed, each representing - * a bit of the feature set. - * - * Note that this function is documented in the main component - * public header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or IX_ETH_DB_INVALID_PORT if the given port is invalid - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet) -{ - IX_ETH_DB_CHECK_PORT_INITIALIZED(portID); - - IX_ETH_DB_CHECK_REFERENCE(featureSet); - - *featureSet = ixEthDBPortInfo[portID].featureCapability; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables a port capability - * - * @param portID ID of the port - * @param feature feature to enable or disable - * @param enabled true to enable the selected feature or false to disable it - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enable) -{ - PortInfo *portInfo; - IxEthDBPriorityTable defaultPriorityTable; - IxEthDBVlanSet vlanSet; - IxEthDBStatus status = IX_ETH_DB_SUCCESS; - BOOL portEnabled; - - IX_ETH_DB_CHECK_PORT_INITIALIZED(portID); - - portInfo = &ixEthDBPortInfo[portID]; - portEnabled = portInfo->enabled; - - /* check that only one feature is selected */ - if (!ixEthDBCheckSingleBitValue(feature)) - { - return IX_ETH_DB_FEATURE_UNAVAILABLE; - } - - /* port capable of this feature? */ - if ((portInfo->featureCapability & feature) == 0) - { - return IX_ETH_DB_FEATURE_UNAVAILABLE; - } - - /* mutual exclusion between learning and WiFi header conversion */ - if (enable && ((feature | portInfo->featureStatus) & (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION)) - == (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* learning must be enabled before filtering */ - if (enable && (feature == IX_ETH_DB_FILTERING) && ((portInfo->featureStatus & IX_ETH_DB_LEARNING) == 0)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* filtering must be disabled before learning */ - if (!enable && (feature == IX_ETH_DB_LEARNING) && ((portInfo->featureStatus & IX_ETH_DB_FILTERING) != 0)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* redundant enabling or disabling */ - if ((!enable && ((portInfo->featureStatus & feature) == 0)) - || (enable && ((portInfo->featureStatus & feature) != 0))) - { - /* do nothing */ - return IX_ETH_DB_SUCCESS; - } - - /* force port enabled */ - portInfo->enabled = true; - - if (enable) - { - /* turn on enable bit */ - portInfo->featureStatus |= feature; - -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* if this is VLAN/QoS set the default priority table */ - if (feature == IX_ETH_DB_VLAN_QOS) - { - /* turn on VLAN/QoS (most permissive mode): - - set default 802.1Q priority mapping table, in accordance to the - availability of traffic classes - - set the acceptable frame filter to accept all - - set the Ingress tagging mode to pass-through - - set full VLAN membership list - - set full TTI table - - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0) - - enable TPID port extraction - */ - - portInfo->ixEthDBTrafficClassCount = portInfo->ixEthDBTrafficClassAvailable; - - /* set default 802.1Q priority mapping table - note that C indexing starts from 0, so we substract 1 here */ - memcpy (defaultPriorityTable, - (const void *) ixEthIEEE802_1QUserPriorityToTrafficClassMapping[portInfo->ixEthDBTrafficClassCount - 1], - sizeof (defaultPriorityTable)); - - /* update priority mapping and AQM queue assignments */ - status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH); - } - - /* set membership and TTI tables */ - memset (vlanSet, 0xFF, sizeof (vlanSet)); - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet); - } - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet); - } - - /* reset the PVID */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBPortVlanTagSet(portID, 0); - } - - /* enable TPID port extraction */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBVlanPortExtractionEnable(portID, true); - } - } - else if (feature == IX_ETH_DB_FIREWALL) -#endif - { - /* firewall starts in black-list mode unless otherwise configured before * - * note that invalid source MAC address filtering is disabled by default */ - if (portInfo->firewallMode != IX_ETH_DB_FIREWALL_BLACK_LIST - && portInfo->firewallMode != IX_ETH_DB_FIREWALL_WHITE_LIST) - { - status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); - } - } - } - - if (status != IX_ETH_DB_SUCCESS) - { - /* checks failed, disable */ - portInfo->featureStatus &= ~feature; - } - } - else - { - /* turn off features */ - if (feature == IX_ETH_DB_FIREWALL) - { - /* turning off the firewall is equivalent to: - - set to black-list mode - - clear all the entries and download the new table - - turn off the invalid source address checking - */ - - status = ixEthDBDatabaseClear(portID, IX_ETH_DB_FIREWALL_RECORD); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallTableDownload(portID); - } - } - else if (feature == IX_ETH_DB_WIFI_HEADER_CONVERSION) - { - /* turn off header conversion */ - status = ixEthDBDatabaseClear(portID, IX_ETH_DB_WIFI_RECORD); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBWiFiConversionTableDownload(portID); - } - } -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - else if (feature == IX_ETH_DB_VLAN_QOS) - { - /* turn off VLAN/QoS: - - set a priority mapping table with one traffic class - - set the acceptable frame filter to accept all - - set the Ingress tagging mode to pass-through - - clear the VLAN membership list - - clear the TTI table - - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0) - - disable TPID port extraction - */ - - /* initialize all => traffic class 0 priority mapping table */ - memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable)); - portInfo->ixEthDBTrafficClassCount = 1; - status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH); - } - - /* clear membership and TTI tables */ - memset (vlanSet, 0, sizeof (vlanSet)); - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet); - } - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet); - } - - /* reset the PVID */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBPortVlanTagSet(portID, 0); - } - - /* disable TPID port extraction */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBVlanPortExtractionEnable(portID, false); - } - } -#endif - - if (status == IX_ETH_DB_SUCCESS) - { - /* checks passed, disable */ - portInfo->featureStatus &= ~feature; - } - } - - /* restore port enabled state */ - portInfo->enabled = portEnabled; - - return status; -} - -/** - * @brief returns the status of a feature - * - * @param portID port ID - * @param present location to store a boolean value indicating - * if the feature is present (true) or not (false) - * @param enabled location to store a booleam value indicating - * if the feature is present (true) or not (false) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled) -{ - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_REFERENCE(present); - - IX_ETH_DB_CHECK_REFERENCE(enabled); - - portInfo = &ixEthDBPortInfo[portID]; - - *present = (portInfo->featureCapability & feature) != 0; - *enabled = (portInfo->featureStatus & feature) != 0; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief returns the value of an EthDB property - * - * @param portID ID of the port - * @param feature feature owning the property - * @param property ID of the property - * @param type location to store the property type into - * @param value location to store the property value into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_REFERENCE(type); - - IX_ETH_DB_CHECK_REFERENCE(value); - - if (feature == IX_ETH_DB_VLAN_QOS) - { - if (property == IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY) - { - * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount; - *type = IX_ETH_DB_INTEGER_PROPERTY; - - return IX_ETH_DB_SUCCESS; - } - else if (property >= IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY - && property <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY) - { - UINT32 classDelta = property - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - - if (classDelta >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_FAIL; - } - - * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[classDelta]; - *type = IX_ETH_DB_INTEGER_PROPERTY; - - return IX_ETH_DB_SUCCESS; - } - } - - return IX_ETH_DB_INVALID_ARG; -} - -/** - * @brief sets the value of an EthDB property - * - * @param portID ID of the port - * @param feature feature owning the property - * @param property ID of the property - * @param value location containing the property value - * - * This function implements a private property intended - * only for EthAcc usage. Upon setting the IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE - * property (the value is ignored), the availability of traffic classes is - * frozen to whatever traffic class structure is currently in use. - * This means that if VLAN_QOS has been enabled before EthAcc - * initialization then all the defined traffic classes will be available; - * otherwise only one traffic class (0) will be available. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h as not accepting any parameters. The - * current implementation is only intended for the private use of EthAcc. - * - * Also note that once this function is called the effect is irreversible, - * unless EthDB is complete unloaded and re-initialized. - * - * @return IX_ETH_DB_INVALID_ARG (no read-write properties are - * supported in this release) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - if ((feature == IX_ETH_DB_VLAN_QOS) && (property == IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE)) - { - ixEthDBPortInfo[portID].ixEthDBTrafficClassAvailable = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount; - - return IX_ETH_DB_SUCCESS; - } - - return IX_ETH_DB_INVALID_ARG; -} diff --git a/drivers/net/npe/IxEthDBFirewall.c b/drivers/net/npe/IxEthDBFirewall.c deleted file mode 100644 index 6fb5ab6acd..0000000000 --- a/drivers/net/npe/IxEthDBFirewall.c +++ /dev/null @@ -1,266 +0,0 @@ -/** - * @file IxEthDBFirewall.c - * - * @brief Implementation of the firewall API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -/** - * @brief updates the NPE firewall operating mode and - * firewall address table - * - * @param portID ID of the port - * @param epDelta initial entry point for binary searches (NPE optimization) - * @param address address of the firewall MAC address table - * - * This function will send a message to the NPE configuring the - * firewall mode (white list or black list), invalid source - * address filtering and downloading a new MAC address database - * to be used for firewall matching. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta) -{ - IxNpeMhMessage message; - IX_STATUS result; - - UINT32 mode = 0; - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - - mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST); - - FILL_SETFIREWALLMODE_MSG(message, - IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - epDelta, - mode, - IX_OSAL_MMU_VIRT_TO_PHYS(address)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief configures the firewall white list/black list - * access mode - * - * @param portID ID of the port - * @param mode firewall filtering mode (IX_ETH_DB_FIREWALL_WHITE_LIST - * or IX_ETH_DB_FIREWALL_BLACK_LIST) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - if (mode != IX_ETH_DB_FIREWALL_WHITE_LIST - && mode != IX_ETH_DB_FIREWALL_BLACK_LIST) - { - return IX_ETH_DB_INVALID_ARG; - } - - ixEthDBPortInfo[portID].firewallMode = mode; - - return ixEthDBFirewallTableDownload(portID); -} - -/** - * @brief enables or disables the invalid source MAC address filter - * - * @param portID ID of the port - * @param enable true to enable invalid source MAC address filtering - * or false to disable it - * - * The invalid source MAC address filter will discard, when enabled, - * frames whose source MAC address is a multicast or the broadcast MAC - * address. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - ixEthDBPortInfo[portID].srcAddressFilterEnabled = enable; - - return ixEthDBFirewallTableDownload(portID); -} - -/** - * @brief adds a firewall record - * - * @param portID ID of the port - * @param macAddr MAC address of the new record - * - * This function will add a new firewall record - * on the specified port, using the specified - * MAC address. If the record already exists this - * function will silently return IX_ETH_DB_SUCCESS, - * although no duplicate records are added. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD; - recordTemplate.portID = portID; - - return ixEthDBAdd(&recordTemplate, NULL); -} - -/** - * @brief removes a firewall record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to remove - * - * This function will attempt to remove a firewall - * record from the given port, using the specified - * MAC address. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully of an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD; - recordTemplate.portID = portID; - - return ixEthDBRemove(&recordTemplate, NULL); -} - -/** - * @brief downloads the firewall address table to an NPE - * - * @param portID ID of the port - * - * This function will download the firewall address table to - * an NPE port. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID) -{ - IxEthDBPortMap query; - IxEthDBStatus result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - SET_DEPENDENCY_MAP(query, portID); - - ixEthDBUpdateLock(); - - ixEthDBPortInfo[portID].updateMethod.searchTree = ixEthDBQuery(NULL, query, IX_ETH_DB_FIREWALL_RECORD, MAX_FW_SIZE); - - result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FIREWALL_RECORD); - - ixEthDBUpdateUnlock(); - - return result; -} diff --git a/drivers/net/npe/IxEthDBHashtable.c b/drivers/net/npe/IxEthDBHashtable.c deleted file mode 100644 index f1b18e6b48..0000000000 --- a/drivers/net/npe/IxEthDBHashtable.c +++ /dev/null @@ -1,642 +0,0 @@ -/** - * @file ethHash.c - * - * @brief Hashtable implementation - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" -#include "IxEthDBLocks_p.h" - -/** - * @addtogroup EthDB - * - * @{ - */ - -/** - * @brief initializes a hash table object - * - * @param hashTable uninitialized hash table structure - * @param numBuckets number of buckets to use - * @param entryHashFunction hash function used - * to hash entire hash node data block (for adding) - * @param matchFunctions array of match functions, indexed on type, - * used to differentiate records with the same hash value - * @param freeFunction function used to free node data blocks - * - * Initializes the given hash table object. - * - * @internal - */ -void ixEthDBInitHash(HashTable *hashTable, - UINT32 numBuckets, - HashFunction entryHashFunction, - MatchFunction *matchFunctions, - FreeFunction freeFunction) -{ - UINT32 bucketIndex; - UINT32 hashSize = numBuckets * sizeof(HashNode *); - - /* entry hashing, matching and freeing methods */ - hashTable->entryHashFunction = entryHashFunction; - hashTable->matchFunctions = matchFunctions; - hashTable->freeFunction = freeFunction; - - /* buckets */ - hashTable->numBuckets = numBuckets; - - /* set to 0 all buckets */ - memset(hashTable->hashBuckets, 0, hashSize); - - /* init bucket locks - note that initially all mutexes are unlocked after MutexInit()*/ - for (bucketIndex = 0 ; bucketIndex < numBuckets ; bucketIndex++) - { - ixOsalFastMutexInit(&hashTable->bucketLocks[bucketIndex]); - } -} - -/** - * @brief adds an entry to the hash table - * - * @param hashTable hash table to add the entry to - * @param entry entry to add - * - * The entry will be hashed using the entry hashing function and added to the - * hash table, unless a locking blockage occurs, in which case the caller - * should retry. - * - * @retval IX_ETH_DB_SUCCESS if adding entry has succeeded - * @retval IX_ETH_DB_NOMEM if there's no memory left in the hash node pool - * @retval IX_ETH_DB_BUSY if there's a locking failure on the insertion path - * - * @internal - */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry) -{ - UINT32 hashValue = hashTable->entryHashFunction(entry); - UINT32 bucketIndex = hashValue % hashTable->numBuckets; - HashNode *bucket = hashTable->hashBuckets[bucketIndex]; - HashNode *newNode; - - LockStack locks; - - INIT_STACK(&locks); - - /* lock bucket */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]); - - /* lock insertion element (first in chain), if any */ - if (bucket != NULL) - { - PUSH_LOCK(&locks, &bucket->lock); - } - - /* get new node */ - newNode = ixEthDBAllocHashNode(); - - if (newNode == NULL) - { - /* unlock everything */ - UNROLL_STACK(&locks); - - return IX_ETH_DB_NOMEM; - } - - /* init lock - note that mutexes are unlocked after MutexInit */ - ixOsalFastMutexInit(&newNode->lock); - - /* populate new link */ - newNode->data = entry; - - /* add to bucket */ - newNode->next = bucket; - hashTable->hashBuckets[bucketIndex] = newNode; - - /* unlock bucket and insertion point */ - UNROLL_STACK(&locks); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief removes an entry from the hashtable - * - * @param hashTable hash table to remove entry from - * @param keyType type of record key used for matching - * @param reference reference key used to identify the entry - * - * The reference key will be hashed using the key hashing function, - * the entry is searched using the hashed value and then examined - * against the reference entry using the match function. A positive - * match will trigger the deletion of the entry. - * Locking failures are reported and the caller should retry. - * - * @retval IX_ETH_DB_SUCCESS if the removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR if the entry was not found - * @retval IX_ETH_DB_BUSY if a locking failure occured during the process - * - * @internal - */ -IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference) -{ - UINT32 hashValue = hashTable->entryHashFunction(reference); - UINT32 bucketIndex = hashValue % hashTable->numBuckets; - HashNode *node = hashTable->hashBuckets[bucketIndex]; - HashNode *previousNode = NULL; - - LockStack locks; - - INIT_STACK(&locks); - - while (node != NULL) - { - /* try to lock node */ - PUSH_LOCK(&locks, &node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - /* found entry */ - if (node->next != NULL) - { - PUSH_LOCK(&locks, &node->next->lock); - } - - if (previousNode == NULL) - { - /* node is head of chain */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]); - - hashTable->hashBuckets[bucketIndex] = node->next; - - POP_LOCK(&locks); - } - else - { - /* relink */ - previousNode->next = node->next; - } - - UNROLL_STACK(&locks); - - /* free node */ - hashTable->freeFunction(node->data); - ixEthDBFreeHashNode(node); - - return IX_ETH_DB_SUCCESS; - } - else - { - if (previousNode != NULL) - { - /* unlock previous node */ - SHIFT_STACK(&locks); - } - - /* advance to next element in chain */ - previousNode = node; - node = node->next; - } - } - - UNROLL_STACK(&locks); - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief retrieves an entry from the hash table - * - * @param hashTable hash table to perform the search into - * @param reference search key (a MAC address) - * @param keyType type of record key used for matching - * @param searchResult pointer where a reference to the located hash node - * is placed - * - * Searches the entry with the same key as reference and places the - * pointer to the resulting node in searchResult. - * An implicit write access lock is granted after a search, which gives the - * caller the opportunity to modify the entry. - * Access should be released as soon as possible using @ref ixEthDBReleaseHashNode(). - * - * @see ixEthDBReleaseHashNode() - * - * @retval IX_ETH_DB_SUCCESS if the search was completed successfully - * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case - * the caller should retry - * - * @warning unless the return value is IX_ETH_DB_SUCCESS the searchResult - * location is NOT modified and therefore using a NULL comparison test when the - * value was not properly initialized would be an error - * - * @internal - */ -IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult) -{ - UINT32 hashValue; - HashNode *node; - - hashValue = hashTable->entryHashFunction(reference); - node = hashTable->hashBuckets[hashValue % hashTable->numBuckets]; - - while (node != NULL) - { - TRY_LOCK(&node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - *searchResult = node; - - return IX_ETH_DB_SUCCESS; - } - else - { - UNLOCK(&node->lock); - - node = node->next; - } - } - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief reports the existence of an entry in the hash table - * - * @param hashTable hash table to perform the search into - * @param reference search key (a MAC address) - * @param keyType type of record key used for matching - * - * Searches the entry with the same key as reference. - * No implicit write access lock is granted after a search, hence the - * caller cannot access or modify the entry. The result is only temporary. - * - * @see ixEthDBReleaseHashNode() - * - * @retval IX_ETH_DB_SUCCESS if the search was completed successfully - * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case - * the caller should retry - * - * @internal - */ -IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference) -{ - UINT32 hashValue; - HashNode *node; - - hashValue = hashTable->entryHashFunction(reference); - node = hashTable->hashBuckets[hashValue % hashTable->numBuckets]; - - while (node != NULL) - { - TRY_LOCK(&node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - UNLOCK(&node->lock); - - return IX_ETH_DB_SUCCESS; - } - else - { - UNLOCK(&node->lock); - - node = node->next; - } - } - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief releases the write access lock - * - * @pre the node should have been obtained via @ref ixEthDBSearchHashEntry() - * - * @see ixEthDBSearchHashEntry() - * - * @internal - */ -void ixEthDBReleaseHashNode(HashNode *node) -{ - UNLOCK(&node->lock); -} - -/** - * @brief initializes a hash iterator - * - * @param hashTable hash table to be iterated - * @param iterator iterator object - * - * If the initialization is successful the iterator will point to the - * first hash table record (if any). - * Testing if the iterator has not passed the end of the table should be - * done using the IS_ITERATOR_VALID(iteratorPtr) macro. - * An implicit write access lock is granted on the entry pointed by the iterator. - * The access is automatically revoked when the iterator is incremented. - * If the caller decides to terminate the iteration before the end of the table is - * passed then the manual access release method, @ref ixEthDBReleaseHashIterator, - * must be called. - * - * @see ixEthDBReleaseHashIterator() - * - * @retval IX_ETH_DB_SUCCESS if initialization was successful and the iterator points - * to the first valid table node - * @retval IX_ETH_DB_FAIL if the table is empty - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this - * might place the database in a permanent invalid lock state - * - * @internal - */ -IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - iterator->bucketIndex = 0; - iterator->node = NULL; - iterator->previousNode = NULL; - - return ixEthDBIncrementHashIterator(hashTable, iterator); -} - -/** - * @brief releases the write access locks of the iterator nodes - * - * @warning use of this function is required only when the caller terminates an iteration - * before reaching the end of the table - * - * @see ixEthDBInitHashIterator() - * @see ixEthDBIncrementHashIterator() - * - * @param iterator iterator whose node(s) should be unlocked - * - * @internal - */ -void ixEthDBReleaseHashIterator(HashIterator *iterator) -{ - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - } -} - -/** - * @brief incremenents an iterator so that it points to the next valid entry of the table - * (if any) - * - * @param hashTable hash table to iterate - * @param iterator iterator object - * - * @pre the iterator object must be initialized using @ref ixEthDBInitHashIterator() - * - * If the increment operation is successful the iterator will point to the - * next hash table record (if any). - * Testing if the iterator has not passed the end of the table should be - * done using the IS_ITERATOR_VALID(iteratorPtr) macro. - * An implicit write access lock is granted on the entry pointed by the iterator. - * The access is automatically revoked when the iterator is re-incremented. - * If the caller decides to terminate the iteration before the end of the table is - * passed then the manual access release method, @ref ixEthDBReleaseHashIterator, - * must be called. - * Is is guaranteed that no other thread can remove or change the iterated entry until - * the iterator is incremented successfully. - * - * @see ixEthDBReleaseHashIterator() - * - * @retval IX_ETH_DB_SUCCESS if the operation was successful and the iterator points - * to the next valid table node - * @retval IX_ETH_DB_FAIL if the iterator has passed the end of the table - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this - * might place the database in a permanent invalid lock state - * - * @internal - */ -IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - /* unless iterator is just initialized... */ - if (iterator->node != NULL) - { - /* try next in chain */ - if (iterator->node->next != NULL) - { - TRY_LOCK(&iterator->node->next->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - iterator->previousNode = iterator->node; - iterator->node = iterator->node->next; - - return IX_ETH_DB_SUCCESS; - } - else - { - /* last in chain, prepare for next bucket */ - iterator->bucketIndex++; - } - } - - /* try next used bucket */ - for (; iterator->bucketIndex < hashTable->numBuckets ; iterator->bucketIndex++) - { - HashNode **nodePtr = &(hashTable->hashBuckets[iterator->bucketIndex]); - HashNode *node = *nodePtr; -#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince) - if (((iterator->bucketIndex & IX_ETHDB_BUCKET_INDEX_MASK) == 0) && - (iterator->bucketIndex < (hashTable->numBuckets - IX_ETHDB_BUCKETPTR_AHEAD))) - { - /* preload next cache line (2 cache line ahead) */ - nodePtr += IX_ETHDB_BUCKETPTR_AHEAD; - __asm__ ("pld [%0];\n": : "r" (nodePtr)); - } -#endif - if (node != NULL) - { - TRY_LOCK(&node->lock); - - /* unlock last one or two nodes in the previous chain */ - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - } - - /* redirect iterator */ - iterator->previousNode = NULL; - iterator->node = node; - - return IX_ETH_DB_SUCCESS; - } - } - - /* could not advance iterator */ - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - iterator->node = NULL; - } - - return IX_ETH_DB_END; -} - -/** - * @brief removes an entry pointed by an iterator - * - * @param hashTable iterated hash table - * @param iterator iterator object - * - * Removes the entry currently pointed by the iterator and repositions the iterator - * on the next valid entry (if any). Handles locking issues automatically and - * implicitely grants write access lock to the new pointed entry. - * Failures due to concurrent threads having write access locks in the same region - * preserve the state of the database and the iterator object, leaving the caller - * free to retry without loss of access. It is guaranteed that only the thread owning - * the iterator can remove the object pointed by the iterator. - * - * @retval IX_ETH_DB_SUCCESS if removal has succeeded - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @internal - */ -IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - HashIterator nextIteratorPos; - LockStack locks; - - INIT_STACK(&locks); - - /* set initial bucket index for next position */ - nextIteratorPos.bucketIndex = iterator->bucketIndex; - - /* compute iterator position before removing anything and lock ahead */ - if (iterator->node->next != NULL) - { - PUSH_LOCK(&locks, &iterator->node->next->lock); - - /* reposition on the next node in the chain */ - nextIteratorPos.node = iterator->node->next; - nextIteratorPos.previousNode = iterator->previousNode; - } - else - { - /* try next chain - don't know yet if we'll find anything */ - nextIteratorPos.node = NULL; - - /* if we find something it's a chain head */ - nextIteratorPos.previousNode = NULL; - - /* browse up in the buckets to find a non-null chain */ - while (++nextIteratorPos.bucketIndex < hashTable->numBuckets) - { - nextIteratorPos.node = hashTable->hashBuckets[nextIteratorPos.bucketIndex]; - - if (nextIteratorPos.node != NULL) - { - /* found a non-empty chain, try to lock head */ - PUSH_LOCK(&locks, &nextIteratorPos.node->lock); - - break; - } - } - } - - /* restore links over the to-be-deleted item */ - if (iterator->previousNode == NULL) - { - /* first in chain, lock bucket */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[iterator->bucketIndex]); - - hashTable->hashBuckets[iterator->bucketIndex] = iterator->node->next; - - POP_LOCK(&locks); - } - else - { - /* relink */ - iterator->previousNode->next = iterator->node->next; - - /* unlock last remaining node in current chain when moving between chains */ - if (iterator->node->next == NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - } - - /* delete entry */ - hashTable->freeFunction(iterator->node->data); - ixEthDBFreeHashNode(iterator->node); - - /* reposition iterator */ - *iterator = nextIteratorPos; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @} - */ diff --git a/drivers/net/npe/IxEthDBLearning.c b/drivers/net/npe/IxEthDBLearning.c deleted file mode 100644 index 840674152f..0000000000 --- a/drivers/net/npe/IxEthDBLearning.c +++ /dev/null @@ -1,149 +0,0 @@ -/** - * @file IxEthDBLearning.c - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/** - * @brief hashes the mac address in a mac descriptor with a XOR function - * - * @param entry pointer to a mac descriptor to be hashed - * - * This function only extracts the mac address and employs ixEthDBKeyXORHash() - * to do the actual hashing. - * Used only to add a whole entry to a hash table, as opposed to searching which - * takes only a key and uses the key hashing directly. - * - * @see ixEthDBKeyXORHash() - * - * @return the hash value - * - * @internal - */ -UINT32 ixEthDBEntryXORHash(void *entry) -{ - MacDescriptor *descriptor = (MacDescriptor *) entry; - - return ixEthDBKeyXORHash(descriptor->macAddress); -} - -/** - * @brief hashes a mac address - * - * @param key pointer to a 6 byte structure (typically an IxEthDBMacAddr pointer) - * to be hashed - * - * Given a 6 bytes MAC address, the hash used is: - * - * hash(MAC[0:5]) = MAC[0:1] ^ MAC[2:3] ^ MAC[4:5] - * - * Used by the hash table to search and remove entries based - * solely on their keys (mac addresses). - * - * @return the hash value - * - * @internal - */ -UINT32 ixEthDBKeyXORHash(void *key) -{ - UINT32 hashValue; - UINT8 *value = (UINT8 *) key; - - hashValue = (value[5] << 8) | value[4]; - hashValue ^= (value[3] << 8) | value[2]; - hashValue ^= (value[1] << 8) | value[0]; - - return hashValue; -} - -/** - * @brief mac descriptor match function - * - * @param reference mac address (typically an IxEthDBMacAddr pointer) structure - * @param entry pointer to a mac descriptor whose key (mac address) is to be - * matched against the reference key - * - * Used by the hash table to retrieve entries. Hashing entries can produce - * collisions, i.e. descriptors with different mac addresses and the same - * hash value, where this function is used to differentiate entries. - * - * @retval true if the entry matches the reference key (equal addresses) - * @retval false if the entry does not match the reference key - * - * @internal - */ -BOOL ixEthDBAddressMatch(void *reference, void *entry) -{ - return (ixEthDBAddressCompare(reference, ((MacDescriptor *) entry)->macAddress) == 0); -} - -/** - * @brief compares two mac addresses - * - * @param mac1 first mac address to compare - * @param mac2 second mac address to compare - * - * This comparison works in a similar way to strcmp, producing similar results. - * Used to insert values keyed on mac addresses into binary search trees. - * - * @retval -1 if mac1 < mac2 - * @retval 0 if ma1 == mac2 - * @retval 1 if mac1 > mac2 - */ -UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2) -{ - UINT32 local_index; - - for (local_index = 0 ; local_index < IX_IEEE803_MAC_ADDRESS_SIZE ; local_index++) - { - if (mac1[local_index] > mac2[local_index]) - { - return 1; - } - else if (mac1[local_index] < mac2[local_index]) - { - return -1; - } - } - - return 0; -} - diff --git a/drivers/net/npe/IxEthDBMem.c b/drivers/net/npe/IxEthDBMem.c deleted file mode 100644 index 133cbef8d6..0000000000 --- a/drivers/net/npe/IxEthDBMem.c +++ /dev/null @@ -1,649 +0,0 @@ -/** - * @file IxEthDBDBMem.c - * - * @brief Memory handling routines for the MAC address database - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -IX_ETH_DB_PRIVATE HashNode *nodePool = NULL; -IX_ETH_DB_PRIVATE MacDescriptor *macPool = NULL; -IX_ETH_DB_PRIVATE MacTreeNode *treePool = NULL; - -IX_ETH_DB_PRIVATE HashNode nodePoolArea[NODE_POOL_SIZE]; -IX_ETH_DB_PRIVATE MacDescriptor macPoolArea[MAC_POOL_SIZE]; -IX_ETH_DB_PRIVATE MacTreeNode treePoolArea[TREE_POOL_SIZE]; - -IX_ETH_DB_PRIVATE IxOsalMutex nodePoolLock; -IX_ETH_DB_PRIVATE IxOsalMutex macPoolLock; -IX_ETH_DB_PRIVATE IxOsalMutex treePoolLock; - -#define LOCK_NODE_POOL { ixOsalMutexLock(&nodePoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_NODE_POOL { ixOsalMutexUnlock(&nodePoolLock); } - -#define LOCK_MAC_POOL { ixOsalMutexLock(&macPoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_MAC_POOL { ixOsalMutexUnlock(&macPoolLock); } - -#define LOCK_TREE_POOL { ixOsalMutexLock(&treePoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_TREE_POOL { ixOsalMutexUnlock(&treePoolLock); } - -/* private function prototypes */ -IX_ETH_DB_PRIVATE MacDescriptor* ixEthDBPoolAllocMacDescriptor(void); -IX_ETH_DB_PRIVATE void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor); - -/** - * @addtogroup EthMemoryManagement - * - * @{ - */ - -/** - * @brief initializes the memory pools used by the ethernet database component - * - * Initializes the hash table node, mac descriptor and mac tree node pools. - * Called at initialization time by @ref ixEthDBInit(). - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBInitMemoryPools(void) -{ - int local_index; - - /* HashNode pool */ - ixOsalMutexInit(&nodePoolLock); - - for (local_index = 0 ; local_index < NODE_POOL_SIZE ; local_index++) - { - HashNode *freeNode = &nodePoolArea[local_index]; - - freeNode->nextFree = nodePool; - nodePool = freeNode; - } - - /* MacDescriptor pool */ - ixOsalMutexInit(&macPoolLock); - - for (local_index = 0 ; local_index < MAC_POOL_SIZE ; local_index++) - { - MacDescriptor *freeDescriptor = &macPoolArea[local_index]; - - freeDescriptor->nextFree = macPool; - macPool = freeDescriptor; - } - - /* MacTreeNode pool */ - ixOsalMutexInit(&treePoolLock); - - for (local_index = 0 ; local_index < TREE_POOL_SIZE ; local_index++) - { - MacTreeNode *freeNode = &treePoolArea[local_index]; - - freeNode->nextFree = treePool; - treePool = freeNode; - } -} - -/** - * @brief allocates a hash node from the pool - * - * Allocates a hash node and resets its value. - * - * @return the allocated hash node or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBAllocHashNode(void) -{ - HashNode *allocatedNode = NULL; - - if (nodePool != NULL) - { - LOCK_NODE_POOL; - - allocatedNode = nodePool; - nodePool = nodePool->nextFree; - - UNLOCK_NODE_POOL; - - memset(allocatedNode, 0, sizeof(HashNode)); - } - - return allocatedNode; -} - -/** - * @brief frees a hash node into the pool - * - * @param hashNode node to be freed - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeHashNode(HashNode *hashNode) -{ - if (hashNode != NULL) - { - LOCK_NODE_POOL; - - hashNode->nextFree = nodePool; - nodePool = hashNode; - - UNLOCK_NODE_POOL; - } -} - -/** - * @brief allocates a mac descriptor from the pool - * - * Allocates a mac descriptor and resets its value. - * This function is not used directly, instead @ref ixEthDBAllocMacDescriptor() - * is used, which keeps track of the pointer reference count. - * - * @see ixEthDBAllocMacDescriptor() - * - * @warning this function is not used directly by any other function - * apart from ixEthDBAllocMacDescriptor() - * - * @return the allocated mac descriptor or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacDescriptor* ixEthDBPoolAllocMacDescriptor(void) -{ - MacDescriptor *allocatedDescriptor = NULL; - - if (macPool != NULL) - { - LOCK_MAC_POOL; - - allocatedDescriptor = macPool; - macPool = macPool->nextFree; - - UNLOCK_MAC_POOL; - - memset(allocatedDescriptor, 0, sizeof(MacDescriptor)); - } - - return allocatedDescriptor; -} - -/** - * @brief allocates and initializes a mac descriptor smart pointer - * - * Uses @ref ixEthDBPoolAllocMacDescriptor() to allocate a mac descriptor - * from the pool and initializes its reference count. - * - * @see ixEthDBPoolAllocMacDescriptor() - * - * @return the allocated mac descriptor or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacDescriptor* ixEthDBAllocMacDescriptor(void) -{ - MacDescriptor *allocatedDescriptor = ixEthDBPoolAllocMacDescriptor(); - - if (allocatedDescriptor != NULL) - { - LOCK_MAC_POOL; - - allocatedDescriptor->refCount++; - - UNLOCK_MAC_POOL; - } - - return allocatedDescriptor; -} - -/** - * @brief frees a mac descriptor back into the pool - * - * @param macDescriptor mac descriptor to be freed - * - * @warning this function is not to be called by anyone but - * ixEthDBFreeMacDescriptor() - * - * @see ixEthDBFreeMacDescriptor() - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor) -{ - LOCK_MAC_POOL; - - macDescriptor->nextFree = macPool; - macPool = macDescriptor; - - UNLOCK_MAC_POOL; -} - -/** - * @brief frees or reduces the usage count of a mac descriptor smart pointer - * - * If the reference count reaches 0 (structure is no longer used anywhere) - * then the descriptor is freed back into the pool using ixEthDBPoolFreeMacDescriptor(). - * - * @see ixEthDBPoolFreeMacDescriptor() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeMacDescriptor(MacDescriptor *macDescriptor) -{ - if (macDescriptor != NULL) - { - LOCK_MAC_POOL; - - if (macDescriptor->refCount > 0) - { - macDescriptor->refCount--; - - if (macDescriptor->refCount == 0) - { - UNLOCK_MAC_POOL; - - ixEthDBPoolFreeMacDescriptor(macDescriptor); - } - else - { - UNLOCK_MAC_POOL; - } - } - else - { - UNLOCK_MAC_POOL; - } - } -} - -/** - * @brief clones a mac descriptor smart pointer - * - * @param macDescriptor mac descriptor to clone - * - * Increments the usage count of the smart pointer - * - * @returns the cloned smart pointer - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor) -{ - LOCK_MAC_POOL; - - if (macDescriptor->refCount == 0) - { - UNLOCK_MAC_POOL; - - return NULL; - } - - macDescriptor->refCount++; - - UNLOCK_MAC_POOL; - - return macDescriptor; -} - -/** - * @brief allocates a mac tree node from the pool - * - * Allocates and initializes a mac tree node from the pool. - * - * @return the allocated mac tree node or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBAllocMacTreeNode(void) -{ - MacTreeNode *allocatedNode = NULL; - - if (treePool != NULL) - { - LOCK_TREE_POOL; - - allocatedNode = treePool; - treePool = treePool->nextFree; - - UNLOCK_TREE_POOL; - - memset(allocatedNode, 0, sizeof(MacTreeNode)); - } - - return allocatedNode; -} - -/** - * @brief frees a mac tree node back into the pool - * - * @param macNode mac tree node to be freed - * - * @warning not to be used except from ixEthDBFreeMacTreeNode(). - * - * @see ixEthDBFreeMacTreeNode() - * - * @internal - */ -void ixEthDBPoolFreeMacTreeNode(MacTreeNode *macNode) -{ - if (macNode != NULL) - { - LOCK_TREE_POOL; - - macNode->nextFree = treePool; - treePool = macNode; - - UNLOCK_TREE_POOL; - } -} - -/** - * @brief frees or reduces the usage count of a mac tree node smart pointer - * - * @param macNode mac tree node to free - * - * Reduces the usage count of the given mac node. If the usage count - * reaches 0 the node is freed back into the pool using ixEthDBPoolFreeMacTreeNode() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeMacTreeNode(MacTreeNode *macNode) -{ - if (macNode->descriptor != NULL) - { - ixEthDBFreeMacDescriptor(macNode->descriptor); - } - - if (macNode->left != NULL) - { - ixEthDBFreeMacTreeNode(macNode->left); - } - - if (macNode->right != NULL) - { - ixEthDBFreeMacTreeNode(macNode->right); - } - - ixEthDBPoolFreeMacTreeNode(macNode); -} - -/** - * @brief clones a mac tree node - * - * @param macNode mac tree node to be cloned - * - * Increments the usage count of the node, its associated descriptor - * and recursively of all its child nodes. - * - * @warning this function is recursive and clones whole trees/subtrees, use only for - * root nodes - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *macNode) -{ - if (macNode != NULL) - { - MacTreeNode *clonedMacNode = ixEthDBAllocMacTreeNode(); - - if (clonedMacNode != NULL) - { - if (macNode->right != NULL) - { - clonedMacNode->right = ixEthDBCloneMacTreeNode(macNode->right); - } - - if (macNode->left != NULL) - { - clonedMacNode->left = ixEthDBCloneMacTreeNode(macNode->left); - } - - if (macNode->descriptor != NULL) - { - clonedMacNode->descriptor = ixEthDBCloneMacDescriptor(macNode->descriptor); - } - } - - return clonedMacNode; - } - else - { - return NULL; - } -} - -#ifndef NDEBUG -/* Debug statistical functions for memory usage */ - -extern HashTable dbHashtable; -int ixEthDBNumHashElements(void); - -int ixEthDBNumHashElements(void) -{ - UINT32 bucketIndex; - int numElements = 0; - HashTable *hashTable = &dbHashtable; - - for (bucketIndex = 0 ; bucketIndex < hashTable->numBuckets ; bucketIndex++) - { - if (hashTable->hashBuckets[bucketIndex] != NULL) - { - HashNode *node = hashTable->hashBuckets[bucketIndex]; - - while (node != NULL) - { - numElements++; - - node = node->next; - } - } - } - - return numElements; -} - -UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree) -{ - if (tree == NULL) - { - return 0; - } - else - { - return 1 /* this node */ + ixEthDBSearchTreeUsageGet(tree->left) + ixEthDBSearchTreeUsageGet(tree->right); - } -} - -int ixEthDBShowMemoryStatus(void) -{ - MacDescriptor *mac; - MacTreeNode *tree; - HashNode *node; - - int macCounter = 0; - int treeCounter = 0; - int nodeCounter = 0; - - int totalTreeUsage = 0; - int totalDescriptorUsage = 0; - int totalCloneDescriptorUsage = 0; - int totalNodeUsage = 0; - - UINT32 portIndex; - - LOCK_NODE_POOL; - LOCK_MAC_POOL; - LOCK_TREE_POOL; - - mac = macPool; - tree = treePool; - node = nodePool; - - while (mac != NULL) - { - macCounter++; - - mac = mac->nextFree; - - if (macCounter > MAC_POOL_SIZE) - { - break; - } - } - - while (tree != NULL) - { - treeCounter++; - - tree = tree->nextFree; - - if (treeCounter > TREE_POOL_SIZE) - { - break; - } - } - - while (node != NULL) - { - nodeCounter++; - - node = node->nextFree; - - if (nodeCounter > NODE_POOL_SIZE) - { - break; - } - } - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - int treeUsage = ixEthDBSearchTreeUsageGet(ixEthDBPortInfo[portIndex].updateMethod.searchTree); - - totalTreeUsage += treeUsage; - totalCloneDescriptorUsage += treeUsage; /* each tree node contains a descriptor */ - } - - totalNodeUsage = ixEthDBNumHashElements(); - totalDescriptorUsage += totalNodeUsage; /* each hash table entry contains a descriptor */ - - UNLOCK_NODE_POOL; - UNLOCK_MAC_POOL; - UNLOCK_TREE_POOL; - - printf("Ethernet database memory usage stats:\n\n"); - - if (macCounter <= MAC_POOL_SIZE) - { - printf("\tMAC descriptor pool : %d free out of %d entries (%d%%)\n", macCounter, MAC_POOL_SIZE, macCounter * 100 / MAC_POOL_SIZE); - } - else - { - printf("\tMAC descriptor pool : invalid state (ring within the pool), normally %d entries\n", MAC_POOL_SIZE); - } - - if (treeCounter <= TREE_POOL_SIZE) - { - printf("\tTree node pool : %d free out of %d entries (%d%%)\n", treeCounter, TREE_POOL_SIZE, treeCounter * 100 / TREE_POOL_SIZE); - } - else - { - printf("\tTREE descriptor pool : invalid state (ring within the pool), normally %d entries\n", TREE_POOL_SIZE); - } - - if (nodeCounter <= NODE_POOL_SIZE) - { - printf("\tHash node pool : %d free out of %d entries (%d%%)\n", nodeCounter, NODE_POOL_SIZE, nodeCounter * 100 / NODE_POOL_SIZE); - } - else - { - printf("\tNODE descriptor pool : invalid state (ring within the pool), normally %d entries\n", NODE_POOL_SIZE); - } - - printf("\n"); - printf("\tMAC descriptor usage : %d entries, %d cloned\n", totalDescriptorUsage, totalCloneDescriptorUsage); - printf("\tTree node usage : %d entries\n", totalTreeUsage); - printf("\tHash node usage : %d entries\n", totalNodeUsage); - printf("\n"); - - /* search for duplicate nodes in the mac pool */ - { - MacDescriptor *reference = macPool; - - while (reference != NULL) - { - MacDescriptor *comparison = reference->nextFree; - - while (comparison != NULL) - { - if (reference == comparison) - { - printf("Warning: reached a duplicate (%p), invalid MAC pool state\n", reference); - - return 1; - } - - comparison = comparison->nextFree; - } - - reference = reference->nextFree; - } - } - - printf("No duplicates found in the MAC pool (sanity check ok)\n"); - - return 0; -} - -#endif /* NDEBUG */ - -/** - * @} EthMemoryManagement - */ diff --git a/drivers/net/npe/IxEthDBNPEAdaptor.c b/drivers/net/npe/IxEthDBNPEAdaptor.c deleted file mode 100644 index d47ffec8b5..0000000000 --- a/drivers/net/npe/IxEthDBNPEAdaptor.c +++ /dev/null @@ -1,719 +0,0 @@ -/** - * @file IxEthDBDBNPEAdaptor.c - * - * @brief Routines that read and write learning/search trees in NPE-specific format - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" -#include "IxEthDBLog_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PUBLIC void ixEthDBELTShow(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBShowNpeMsgHistory(void); - -/* data */ -UINT8* ixEthDBNPEUpdateArea[IX_ETH_DB_NUMBER_OF_PORTS]; -UINT32 dumpEltSize; - -/* private data */ -IX_ETH_DB_PRIVATE IxEthDBNoteWriteFn ixEthDBNPENodeWrite[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -#define IX_ETH_DB_MAX_DELTA_ZONES (6) /* at most 6 EP Delta zones, according to NPE FS */ -IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDeltaOffset[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES]; -IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDelta[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES]; - -/** - * @brief allocates non-cached or contiguous NPE tree update areas for all the ports - * - * This function is called only once at initialization time from - * @ref ixEthDBInit(). - * - * @warning do not call manually - * - * @see ixEthDBInit() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEUpdateAreasInit(void) -{ - UINT32 portIndex; - PortUpdateMethod *update; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - update = &ixEthDBPortInfo[portIndex].updateMethod; - - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - update->npeUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_ELT_BYTE_SIZE); - update->npeGwUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_GW_BYTE_SIZE); - update->vlanUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_VLAN_BYTE_SIZE); - - if (update->npeUpdateZone == NULL - || update->npeGwUpdateZone == NULL - || update->vlanUpdateZone == NULL) - { - ERROR_LOG("Fatal error: IX_ACC_DRV_DMA_MALLOC() returned NULL, no NPE update zones available\n"); - } - else - { - memset(update->npeUpdateZone, 0, FULL_ELT_BYTE_SIZE); - memset(update->npeGwUpdateZone, 0, FULL_GW_BYTE_SIZE); - memset(update->vlanUpdateZone, 0, FULL_VLAN_BYTE_SIZE); - } - } - else - { - /* unused */ - update->npeUpdateZone = NULL; - update->npeGwUpdateZone = NULL; - update->vlanUpdateZone = NULL; - } - } -} - -/** - * @brief deallocates the NPE update areas for all the ports - * - * This function is called at component de-initialization time - * by @ref ixEthDBUnload(). - * - * @warning do not call manually - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEUpdateAreasUnload(void) -{ - UINT32 portIndex; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone); - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeGwUpdateZone); - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.vlanUpdateZone); - } - } -} - -/** - * @brief general-purpose NPE callback function - * - * @param npeID NPE ID - * @param msg NPE message - * - * This function will unblock the caller by unlocking - * the npeAckLock mutex defined for each NPE port - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg) -{ - IxEthDBPortId portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID); - PortInfo *portInfo; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS) - { - /* invalid port */ - return; - } - - if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE) - { - /* not an NPE */ - return; - } - - portInfo = &ixEthDBPortInfo[portID]; - - ixOsalMutexUnlock(&portInfo->npeAckLock); -} - -/** - * @brief synchronizes the database with tree - * - * @param portID port ID of the NPE whose tree is to be scanned - * @param eltBaseAddress memory base address of the NPE serialized tree - * @param eltSize size in bytes of the NPE serialized tree - * - * Scans the NPE learning tree and resets the age of active database records. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize) -{ - UINT32 eltEntryOffset; - UINT32 entryPortID; - - /* invalidate cache */ - IX_OSAL_CACHE_INVALIDATE(eltBaseAddress, eltSize); - - for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE) - { - /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node - * - * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit] - * therefore we can just use the pointer for database searches as only the first 6 bytes are checked - */ - void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset); - - /* debug */ - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE); - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true) - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n"); - } - else if (eltEntryOffset == ELT_ROOT_OFFSET) - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is root\n"); - } - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress)) - { - entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress)); - - /* check only active entries belonging to this port */ - if (ixEthDBPortInfo[portID].agingEnabled && IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) && (portID == entryPortID) - && ((ixEthDBPortDefinitions[portID].capabilities & IX_ETH_ENTRY_AGING) == 0)) - { - /* search record */ - HashNode *node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_FILTERING_RECORDS); - - /* safety check, maybe user deleted record right before sync? */ - if (node != NULL) - { - /* found record */ - MacDescriptor *descriptor = (MacDescriptor *) node->data; - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) synced entry [%s] already in the database, updating fields\n", mac2string(eltNodeAddress)); - - /* reset age - set to -1 so that maintenance will restore it to 0 (or more) when incrementing */ - if (!descriptor->recordData.filteringData.staticEntry) - { - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - descriptor->recordData.filteringData.age = AGE_RESET; - } - else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - descriptor->recordData.filteringVlanData.age = AGE_RESET; - } - } - - /* end transaction */ - ixEthDBReleaseHashNode(node); - } - } - else - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... found portID %d, we check only port %d\n", entryPortID, portID); - } - } - } -} - -/** - * @brief writes a search tree in NPE format - * - * @param type type of records to be written into the NPE update zone - * @param totalSize maximum size of the linearized tree - * @param baseAddress memory base address where to write the NPE tree into - * @param tree search tree to write in NPE format - * @param blocks number of written 64-byte blocks - * @param startIndex optimal binary search start index - * - * Serializes the given tree in NPE linear format - * - * @return none - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *epDelta, UINT32 *blocks) -{ - MacTreeNodeStack *stack; - UINT32 maxOffset = 0; - UINT32 emptyOffset; - - stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack)); - - if (stack == NULL) - { - ERROR_LOG("DB: (NPEAdaptor) failed to allocate the node stack for learning tree linearization, out of memory?\n"); - return; - } - - /* zero out empty root */ - memset(baseAddress, 0, ELT_ENTRY_SIZE); - - NODE_STACK_INIT(stack); - - if (tree != NULL) - { - /* push tree root at offset 1 */ - NODE_STACK_PUSH(stack, tree, 1); - - maxOffset = 1; - } - - while (NODE_STACK_NONEMPTY(stack)) - { - MacTreeNode *node; - UINT32 offset; - - NODE_STACK_POP(stack, node, offset); - - /* update maximum offset */ - if (offset > maxOffset) - { - maxOffset = offset; - } - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing MAC [%s] at offset %d\n", mac2string(node->descriptor->macAddress), offset); - - /* add node to NPE ELT at position indicated by offset */ - if (offset < MAX_ELT_SIZE) - { - ixEthDBNPENodeWrite[type]((void *) (((UINT32) baseAddress) + offset * ELT_ENTRY_SIZE), node); - } - - if (node->left != NULL) - { - NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset)); - } - else - { - /* ensure this entry is zeroed */ - memset((void *) ((UINT32) baseAddress + LEFT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE); - } - - if (node->right != NULL) - { - NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset)); - } - else - { - /* ensure this entry is zeroed */ - memset((void *) ((UINT32) baseAddress + RIGHT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE); - } - } - - emptyOffset = maxOffset + 1; - - /* zero out rest of the tree */ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Emptying tree from offset %d, address 0x%08X, %d bytes\n", - emptyOffset, ((UINT32) baseAddress) + emptyOffset * ELT_ENTRY_SIZE, totalSize - (emptyOffset * ELT_ENTRY_SIZE)); - - if (emptyOffset < MAX_ELT_SIZE - 1) - { - memset((void *) (((UINT32) baseAddress) + (emptyOffset * ELT_ENTRY_SIZE)), 0, totalSize - (emptyOffset * ELT_ENTRY_SIZE)); - } - - /* flush cache */ - IX_OSAL_CACHE_FLUSH(baseAddress, totalSize); - - /* debug */ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Ethernet learning/filtering tree XScale wrote at address 0x%08X (max %d bytes):\n\n", - (UINT32) baseAddress, FULL_ELT_BYTE_SIZE); - - IX_ETH_DB_NPE_DUMP_ELT(baseAddress, FULL_ELT_BYTE_SIZE); - - /* compute number of 64-byte blocks */ - if (blocks != NULL) - { - *blocks = maxOffset != 0 ? 1 + maxOffset / 8 : 0; - - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Wrote %d 64-byte blocks\n", *blocks); - } - - /* compute epDelta - start index for binary search */ - if (epDelta != NULL) - { - UINT32 deltaIndex = 0; - - *epDelta = 0; - - for (; deltaIndex < IX_ETH_DB_MAX_DELTA_ZONES ; deltaIndex ++) - { - if (ixEthDBEPDeltaOffset[type][deltaIndex] >= maxOffset) - { - *epDelta = ixEthDBEPDelta[type][deltaIndex]; - break; - } - } - - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Computed epDelta %d (based on maxOffset %d)\n", *epDelta, maxOffset); - } - - ixOsalCacheDmaFree(stack); -} - -/** - * @brief implements a dummy node serialization function - * - * @param address address of where the node is to be serialized (unused) - * @param node tree node to be serialized (unused) - * - * This function is registered for safety reasons and should - * never be called. It will display an error message if this - * function is called. - * - * @return none - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNullSerialize(void *address, MacTreeNode *node) -{ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Warning, the NullSerialize function was called, wrong record type?\n"); -} - -/** - * @brief writes a filtering entry in NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPELearningNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* copy port ID */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET) = IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(node->descriptor->portID); - - /* copy flags (valid and not active, as the NPE sets it to active) and clear reserved section (bits 2-7) */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) = (UINT8) IX_EDB_FLAGS_INACTIVE_VALID; - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing ELT node 0x%08x:0x%08x\n", * (UINT32 *) address, * (((UINT32 *) (address)) + 1)); -} - -/** - * @brief writes a WiFi header conversion record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPEWiFiNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* copy index */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET) = node->descriptor->recordData.wifiData.gwAddressIndex; - - /* copy flags (type and valid) */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET) = node->descriptor->recordData.wifiData.type << 1 | IX_EDB_FLAGS_VALID; -} - -/** - * @brief writes a WiFi gateway header conversion record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->recordData.wifiData.gwMacAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* set reserved field, two bytes */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0; - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET + 1) = 0; -} - -/** - * @brief writes a firewall record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPEFirewallNodeWrite(void *address, MacTreeNode *node) -{ - /* set reserved field */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0; - - /* set flags */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_FLAGS_OFFSET) = IX_EDB_FLAGS_VALID; - - /* copy mac address */ - memcpy((void *) ((UINT32) address + IX_EDB_NPE_NODE_FW_ADDR_OFFSET), node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); -} - -/** - * @brief registers the NPE serialization methods - * - * This functions registers NPE serialization methods - * for writing the following types of records in NPE - * readable linear format: - * - filtering records - * - WiFi header conversion records - * - WiFi gateway header conversion records - * - firewall records - * - * Note that this function should be called by the - * component initialization function. - * - * @return number of registered record types - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBRecordSerializeMethodsRegister() -{ - int i; - - /* safety - register a blank method for everybody first */ - for ( i = 0 ; i < IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1 ; i++) - { - ixEthDBNPENodeWrite[i] = ixEthDBNullSerialize; - } - - /* register real methods */ - ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_RECORD] = ixEthDBNPELearningNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_VLAN_RECORD] = ixEthDBNPELearningNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_WIFI_RECORD] = ixEthDBNPEWiFiNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_FIREWALL_RECORD] = ixEthDBNPEFirewallNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_GATEWAY_RECORD] = ixEthDBNPEGatewayNodeWrite; - - /* EP Delta arrays */ - memset(ixEthDBEPDeltaOffset, 0, sizeof (ixEthDBEPDeltaOffset)); - memset(ixEthDBEPDelta, 0, sizeof (ixEthDBEPDelta)); - - /* filtering records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][0] = 1; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][1] = 3; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][1] = 7; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][2] = 511; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][2] = 14; - - /* wifi records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][0] = 1; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][1] = 3; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][1] = 7; - - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][2] = 511; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][2] = 14; - - /* firewall records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][0] = 0; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][1] = 1; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][1] = 5; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][2] = 3; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][2] = 13; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][3] = 7; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][3] = 21; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][4] = 15; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][4] = 29; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][5] = 31; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][5] = 37; - - return 5; /* 5 methods registered */ -} - -#ifndef IX_NDEBUG - -IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2]; -IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen = 0; - -/** - * When compiled in DEBUG mode, this function can be used to display - * the history of messages sent to the NPEs (up to 100). - */ -IX_ETH_DB_PUBLIC -void ixEthDBShowNpeMsgHistory() -{ - UINT32 i = 0; - UINT32 base, len; - - if (npeMsgHistoryLen <= IX_ETH_DB_NPE_MSG_HISTORY_DEPTH) - { - base = 0; - len = npeMsgHistoryLen; - } - else - { - base = npeMsgHistoryLen % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - len = IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - } - - printf("NPE message history [last %d messages, from least to most recent]:\n", len); - - for (; i < len ; i++) - { - UINT32 pos = (base + i) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - printf("msg[%d]: 0x%08x:0x%08x\n", i, npeMsgHistory[pos][0], npeMsgHistory[pos][1]); - } -} - -IX_ETH_DB_PUBLIC -void ixEthDBELTShow(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - IX_STATUS result; - - /* send EDB_GetMACAddressDatabase message */ - FILL_GETMACADDRESSDATABASE(message, - 0 /* reserved */, - IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portID].updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - /* analyze NPE copy */ - UINT32 eltEntryOffset; - UINT32 entryPortID; - - UINT32 eltBaseAddress = (UINT32) ixEthDBPortInfo[portID].updateMethod.npeUpdateZone; - UINT32 eltSize = FULL_ELT_BYTE_SIZE; - - /* invalidate cache */ - IX_OSAL_CACHE_INVALIDATE((void *) eltBaseAddress, eltSize); - - printf("Listing records in main learning tree for port %d\n", portID); - - for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE) - { - /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node - * - * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit] - * therefore we can just use the pointer for database searches as only the first 6 bytes are checked - */ - void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset); - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress)) - { - HashNode *node; - - entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress)); - - /* search record */ - node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_RECORD_TYPES); - - printf("%s - port %d - %s ", mac2string((unsigned char *) eltNodeAddress), entryPortID, - IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) ? "active" : "inactive"); - - /* safety check, maybe user deleted record right before sync? */ - if (node != NULL) - { - /* found record */ - MacDescriptor *descriptor = (MacDescriptor *) node->data; - - printf("- %s ", - descriptor->type == IX_ETH_DB_FILTERING_RECORD ? "filtering" : - descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD ? "vlan" : - descriptor->type == IX_ETH_DB_WIFI_RECORD ? "wifi" : "other (check main DB)"); - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) printf("- age %d - %s ", - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) printf("- age %d - %s - tci %d ", - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic", - descriptor->recordData.filteringVlanData.ieee802_1qTag); - - /* end transaction */ - ixEthDBReleaseHashNode(node); - } - else - { - printf("- not synced"); - } - - printf("\n"); - } - } - } - else - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT, - "EthDB: (ShowELT) Could not complete action (communication failure)\n", - portID, 0, 0, 0, 0, 0); - } -} - -#endif diff --git a/drivers/net/npe/IxEthDBPortUpdate.c b/drivers/net/npe/IxEthDBPortUpdate.c deleted file mode 100644 index 813e4ee6b5..0000000000 --- a/drivers/net/npe/IxEthDBPortUpdate.c +++ /dev/null @@ -1,740 +0,0 @@ -/** - * @file IxEthDBDBPortUpdate.c - * - * @brief Implementation of dependency and port update handling - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor); -IX_ETH_DB_PRIVATE void ixEthDBCreateTrees(IxEthDBPortMap updatePorts); -IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count); -IX_ETH_DB_PRIVATE UINT32 ixEthDBRebalanceLog2Floor(UINT32 x); - -extern HashTable dbHashtable; - -/** - * @brief register types requiring automatic updates - * - * @param typeArray array indexed on record types, each - * element indicating whether the record type requires an - * automatic update (true) or not (false) - * - * Automatic updates are done for registered record types - * upon adding, updating (that is, updating the record portID) - * and removing records. Whenever an automatic update is triggered - * the appropriate ports will be provided with new database - * information. - * - * It is assumed that the typeArray parameter is allocated large - * enough to hold all the user defined types. Also, the type - * array should be initialized to false as this function only - * caters for types which do require automatic updates. - * - * Note that this function should be called by the component - * initialization function. - * - * @return number of record types registered for automatic - * updates - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray) -{ - typeArray[IX_ETH_DB_FILTERING_RECORD] = true; - typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true; - - return 2; -} - -/** - * @brief computes dependencies and triggers port learning tree updates - * - * @param triggerPorts port map consisting in the ports which triggered the update - * - * This function browses through all the ports and determines how to waterfall the update - * event from the trigger ports to all other ports depending on them. - * - * Once the list of ports to be updated is determined this function - * calls @ref ixEthDBCreateTrees. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts) -{ - IxEthDBPortMap updatePorts; - UINT32 portIndex; - - ixEthDBUpdateLock(); - - SET_EMPTY_DEPENDENCY_MAP(updatePorts); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *port = &ixEthDBPortInfo[portIndex]; - BOOL mapsCollide; - - MAPS_COLLIDE(mapsCollide, triggerPorts, port->dependencyPortMap); - - if (mapsCollide /* do triggers influence this port? */ - && !IS_PORT_INCLUDED(portIndex, updatePorts) /* and it's not already in the update list */ - && port->updateMethod.updateEnabled) /* and we're allowed to update it */ - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding port %d to update set\n", portIndex); - - JOIN_PORT_TO_MAP(updatePorts, portIndex); - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Didn't add port %d to update set, reasons follow:\n", portIndex); - - if (!mapsCollide) - { - IX_ETH_DB_UPDATE_TRACE("\tMaps don't collide on port %d\n", portIndex); - } - - if (IS_PORT_INCLUDED(portIndex, updatePorts)) - { - IX_ETH_DB_UPDATE_TRACE("\tPort %d is already in the update set\n", portIndex); - } - - if (!port->updateMethod.updateEnabled) - { - IX_ETH_DB_UPDATE_TRACE("\tPort %d doesn't have updateEnabled set\n", portIndex); - } - } - } - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Updating port set\n"); - - ixEthDBCreateTrees(updatePorts); - - ixEthDBUpdateUnlock(); -} - -/** - * @brief creates learning trees and calls the port update handlers - * - * @param updatePorts set of ports in need of learning trees - * - * This function determines the optimal method of creating learning - * trees using a minimal number of database queries, keeping in mind - * that different ports can either use the same learning trees or they - * can partially share them. The actual tree building routine is - * @ref ixEthDBQuery. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBCreateTrees(IxEthDBPortMap updatePorts) -{ - UINT32 portIndex; - BOOL result; - BOOL portsLeft = true; - - while (portsLeft) - { - /* get port with minimal dependency map and NULL search tree */ - UINT32 minPortIndex = MAX_PORT_SIZE; - UINT32 minimalSize = MAX_PORT_SIZE; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - UINT32 size; - PortInfo *port = &ixEthDBPortInfo[portIndex]; - - /* generate trees only for ports that need them */ - if (!port->updateMethod.searchTreePendingWrite && IS_PORT_INCLUDED(portIndex, updatePorts)) - { - GET_MAP_SIZE(port->dependencyPortMap, size); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Dependency map for port %d: size %d\n", - portIndex, size); - - if (size < minimalSize) - { - minPortIndex = portIndex; - minimalSize = size; - } - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Skipped port %d from tree diff (%s)\n", portIndex, - port->updateMethod.searchTreePendingWrite ? "pending write access" : "ignored by query"); - } - } - - /* if a port was found than minimalSize is not MAX_PORT_SIZE */ - if (minimalSize != MAX_PORT_SIZE) - { - /* minPortIndex is the port we seek */ - PortInfo *port = &ixEthDBPortInfo[minPortIndex]; - - IxEthDBPortMap query; - MacTreeNode *baseTree; - - /* now try to find a port with minimal map difference */ - PortInfo *minimalDiffPort = NULL; - UINT32 minimalDiff = MAX_PORT_SIZE; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal size port is %d\n", minPortIndex); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *diffPort = &ixEthDBPortInfo[portIndex]; - BOOL mapIsSubset; - - IS_MAP_SUBSET(mapIsSubset, diffPort->dependencyPortMap, port->dependencyPortMap); - - - if (portIndex != minPortIndex - && diffPort->updateMethod.searchTree != NULL - && mapIsSubset) - { - /* compute size and pick only minimal size difference */ - UINT32 diffPortSize; - UINT32 sizeDifference; - - GET_MAP_SIZE(diffPort->dependencyPortMap, diffPortSize); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Checking port %d for differences...\n", portIndex); - - sizeDifference = minimalSize - diffPortSize; - - if (sizeDifference < minimalDiff) - { - minimalDiffPort = diffPort; - minimalDiff = sizeDifference; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal difference 0x%x was found on port %d\n", - minimalDiff, portIndex); - } - } - } - - /* check if filtering is enabled on this port */ - if ((port->featureStatus & IX_ETH_DB_FILTERING) != 0) - { - /* if minimalDiff is not MAX_PORT_SIZE minimalDiffPort points to the most similar port */ - if (minimalDiff != MAX_PORT_SIZE) - { - baseTree = ixEthDBCloneMacTreeNode(minimalDiffPort->updateMethod.searchTree); - DIFF_MAPS(query, port->dependencyPortMap , minimalDiffPort->dependencyPortMap); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Found minimal diff, extending tree %d on query\n", - minimalDiffPort->portID); - } - else /* .. otherwise no similar port was found, build tree from scratch */ - { - baseTree = NULL; - - COPY_DEPENDENCY_MAP(query, port->dependencyPortMap); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) No similar diff, creating tree from query\n"); - } - - IS_EMPTY_DEPENDENCY_MAP(result, query); - - if (!result) /* otherwise we don't need anything more on top of the cloned tree */ - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding query tree to port %d\n", minPortIndex); - - /* build learning tree */ - port->updateMethod.searchTree = ixEthDBQuery(baseTree, query, IX_ETH_DB_ALL_FILTERING_RECORDS, MAX_ELT_SIZE); - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Query is empty, assuming identical nearest tree\n"); - - port->updateMethod.searchTree = baseTree; - } - } - else - { - /* filtering is not enabled, will download an empty tree */ - if (port->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(port->updateMethod.searchTree); - } - - port->updateMethod.searchTree = NULL; - } - - /* mark tree as valid */ - port->updateMethod.searchTreePendingWrite = true; - } - else - { - portsLeft = false; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n"); - } - } - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *updatePort = &ixEthDBPortInfo[portIndex]; - - if (updatePort->updateMethod.searchTreePendingWrite) - { - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Starting procedure to upload new search tree (%snull) into NPE %d\n", - updatePort->updateMethod.searchTree != NULL ? "not " : "", - portIndex); - - updatePort->updateMethod.updateHandler(portIndex, IX_ETH_DB_FILTERING_RECORD); - } - } -} - -/** - * @brief standard NPE update handler - * - * @param portID id of the port to be updated - * @param type record type to be pushed during this update - * - * The NPE update handler manages updating the NPE databases - * given a certain record type. - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type) -{ - UINT32 epDelta, blockCount; - IxNpeMhMessage message; - UINT32 treeSize = 0; - PortInfo *port = &ixEthDBPortInfo[portID]; - - /* size selection and type check */ - if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD) - { - treeSize = FULL_ELT_BYTE_SIZE; - } - else if (type == IX_ETH_DB_FIREWALL_RECORD) - { - treeSize = FULL_FW_BYTE_SIZE; - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - /* serialize tree into memory */ - ixEthDBNPETreeWrite(type, treeSize, port->updateMethod.npeUpdateZone, port->updateMethod.searchTree, &epDelta, &blockCount); - - /* free internal copy */ - if (port->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(port->updateMethod.searchTree); - } - - /* forget last used search tree */ - port->updateMethod.searchTree = NULL; - port->updateMethod.searchTreePendingWrite = false; - - /* dependending on the update type we do different things */ - if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD) - { - IX_STATUS result; - - FILL_SETMACADDRESSDATABASE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - epDelta, blockCount, - IX_OSAL_MMU_VIRT_TO_PHYS(port->updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Finished downloading NPE tree on port %d\n", portID); - } - else - { - ixEthDBPortInfo[portID].agingEnabled = false; - ixEthDBPortInfo[portID].updateMethod.updateEnabled = false; - ixEthDBPortInfo[portID].updateMethod.userControlled = true; - - ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID); - - ixEthDBDatabaseClear(portID, IX_ETH_DB_ALL_RECORD_TYPES); - - return IX_ETH_DB_FAIL; - } - - return IX_ETH_DB_SUCCESS; - } - else if (type == IX_ETH_DB_FIREWALL_RECORD) - { - return ixEthDBFirewallUpdate(portID, port->updateMethod.npeUpdateZone, epDelta); - } - - return IX_ETH_DB_INVALID_ARG; -} - -/** - * @brief queries the database for a set of records to be inserted into a given tree - * - * @param searchTree pointer to a tree where insertions will be performed; can be NULL - * @param query set of ports that a database record must match to be inserted into the tree - * - * The query method browses through the database, extracts all the descriptors matching - * the given query parameter and inserts them into the given learning tree. - * Note that this is an append procedure, the given tree needs not to be empty. - * A "descriptor matching the query" is a descriptor whose port id is in the query map. - * If the given tree is empty (NULL) a new tree is created and returned. - * - * @return the tree root - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maxEntries) -{ - HashIterator iterator; - UINT32 entryCount = 0; - - /* browse database */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) querying [%s]:%d on port map ... ", - mac2string(descriptor->macAddress), - descriptor->portID); - - if ((descriptor->type & recordFilter) != 0 - && IS_PORT_INCLUDED(descriptor->portID, query)) - { - MacDescriptor *descriptorClone = ixEthDBCloneMacDescriptor(descriptor); - - IX_ETH_DB_UPDATE_TRACE("match\n"); - - if (descriptorClone != NULL) - { - /* add descriptor to tree */ - searchTree = ixEthDBTreeInsert(searchTree, descriptorClone); - - entryCount++; - } - } - else - { - IX_ETH_DB_UPDATE_TRACE("no match\n"); - } - - if (entryCount < maxEntries) - { - /* advance to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - else - { - /* the NPE won't accept more entries so we can stop now */ - ixEthDBReleaseHashIterator(&iterator); - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) number of elements reached maximum supported by port\n"); - - break; - } - } - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) query inserted %d records in the search tree\n", entryCount); - - return ixEthDBTreeRebalance(searchTree); -} - -/** - * @brief inserts a mac descriptor into an tree - * - * @param searchTree tree where the insertion is to be performed (may be NULL) - * @param descriptor descriptor to insert into tree - * - * @return the tree root - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor) -{ - MacTreeNode *currentNode = searchTree; - MacTreeNode *insertLocation = NULL; - MacTreeNode *newNode; - INT32 insertPosition = RIGHT; - - if (descriptor == NULL) - { - return searchTree; - } - - /* create a new node */ - newNode = ixEthDBAllocMacTreeNode(); - - if (newNode == NULL) - { - /* out of memory */ - ERROR_LOG("Warning: ixEthDBAllocMacTreeNode returned NULL in file %s:%d (out of memory?)\n", __FILE__, __LINE__); - - ixEthDBFreeMacDescriptor(descriptor); - - return NULL; - } - - /* populate node */ - newNode->descriptor = descriptor; - - /* an empty initial tree is a special case */ - if (searchTree == NULL) - { - return newNode; - } - - /* get insertion location */ - while (insertLocation == NULL) - { - MacTreeNode *nextNode; - - /* compare given key with current node key */ - insertPosition = ixEthDBAddressCompare(descriptor->macAddress, currentNode->descriptor->macAddress); - - /* navigate down */ - if (insertPosition == RIGHT) - { - nextNode = currentNode->right; - } - else if (insertPosition == LEFT) - { - nextNode = currentNode->left; - } - else - { - /* error, duplicate key */ - ERROR_LOG("Warning: trapped insertion of a duplicate MAC address in an NPE search tree\n"); - - /* this will free the MAC descriptor as well */ - ixEthDBFreeMacTreeNode(newNode); - - return searchTree; - } - - /* when we can no longer dive through the tree we found the insertion place */ - if (nextNode != NULL) - { - currentNode = nextNode; - } - else - { - insertLocation = currentNode; - } - } - - /* insert node */ - if (insertPosition == RIGHT) - { - insertLocation->right = newNode; - } - else - { - insertLocation->left = newNode; - } - - return searchTree; -} - -/** - * @brief balance a tree - * - * @param searchTree tree to balance - * - * Converts a tree into a balanced tree and returns the root of - * the balanced tree. The resulting tree is route balanced - * not perfectly balanced. This makes no difference to the - * average tree search time which is the same in both cases, O(log2(n)). - * - * @return root of the balanced tree or NULL if there's no memory left - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree) -{ - MacTreeNode *pseudoRoot = ixEthDBAllocMacTreeNode(); - UINT32 size; - - if (pseudoRoot == NULL) - { - /* out of memory */ - return NULL; - } - - pseudoRoot->right = searchTree; - - ixEthDBRebalanceTreeToVine(pseudoRoot, &size); - ixEthDBRebalanceVineToTree(pseudoRoot, size); - - searchTree = pseudoRoot->right; - - /* remove pseudoRoot right branch, otherwise it will free the entire tree */ - pseudoRoot->right = NULL; - - ixEthDBFreeMacTreeNode(pseudoRoot); - - return searchTree; -} - -/** - * @brief converts a tree into a vine - * - * @param root root of tree to convert - * @param size depth of vine (equal to the number of nodes in the tree) - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size) -{ - MacTreeNode *vineTail = root; - MacTreeNode *remainder = vineTail->right; - MacTreeNode *tempPtr; - - *size = 0; - - while (remainder != NULL) - { - if (remainder->left == NULL) - { - /* move tail down one */ - vineTail = remainder; - remainder = remainder->right; - (*size)++; - } - else - { - /* rotate around remainder */ - tempPtr = remainder->left; - remainder->left = tempPtr->right; - tempPtr->right = remainder; - remainder = tempPtr; - vineTail->right = tempPtr; - } - } -} - -/** - * @brief converts a vine into a balanced tree - * - * @param root vine to convert - * @param size depth of vine - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size) -{ - UINT32 leafCount = size + 1 - (1 << ixEthDBRebalanceLog2Floor(size + 1)); - - ixEthDBRebalanceCompression(root, leafCount); - - size = size - leafCount; - - while (size > 1) - { - ixEthDBRebalanceCompression(root, size / 2); - - size /= 2; - } -} - -/** - * @brief compresses a vine/tree stage into a more balanced vine/tree - * - * @param root root of the tree to compress - * @param count number of "spine" nodes - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count) -{ - MacTreeNode *scanner = root; - MacTreeNode *child; - UINT32 local_index; - - for (local_index = 0 ; local_index < count ; local_index++) - { - child = scanner->right; - scanner->right = child->right; - scanner = scanner->right; - child->right = scanner->left; - scanner->left = child; - } -} - -/** - * @brief computes |_log2(x)_| (a.k.a. floor(log2(x))) - * - * @param x number to compute |_log2(x)_| for - * - * @return |_log2(x)_| - * - * @internal - */ -IX_ETH_DB_PRIVATE -UINT32 ixEthDBRebalanceLog2Floor(UINT32 x) -{ - UINT32 log = 0; - UINT32 val = 1; - - while (val < x) - { - log++; - val <<= 1; - } - - return val == x ? log : log - 1; -} - diff --git a/drivers/net/npe/IxEthDBReports.c b/drivers/net/npe/IxEthDBReports.c deleted file mode 100644 index 912e608613..0000000000 --- a/drivers/net/npe/IxEthDBReports.c +++ /dev/null @@ -1,652 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -extern HashTable dbHashtable; -IX_ETH_DB_PRIVATE void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter); -IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map); - -/** - * @brief displays a port dependency map - * - * @param portID ID of the port - * @param map port map to display - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map) -{ - UINT32 portIndex; - BOOL mapSelf = true, mapNone = true, firstPort = true; - - /* dependency port maps */ - printf("Dependency port map: "); - - /* browse the port map */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (IS_PORT_INCLUDED(portIndex, map)) - { - mapNone = false; - - if (portIndex != portID) - { - mapSelf = false; - } - - printf("%s%d", firstPort ? "{" : ", ", portIndex); - - firstPort = false; - } - } - - if (mapNone) - { - mapSelf = false; - } - - printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group"); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays all the filtering records belonging to a port - * - * @param portID ID of the port to display - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() - * instead. Calling this function is equivalent to calling - * ixEthDBFilteringDatabaseShowRecords(portID, IX_ETH_DB_FILTERING_RECORD) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID) -{ - IxEthDBStatus local_result; - HashIterator iterator; - PortInfo *portInfo; - UINT32 recordCount = 0; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - /* display table header */ - printf("Ethernet database records for port ID [%d]\n", portID); - - ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap); - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - printf("NPE updates are %s\n\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled"); - } - else - { - printf("updates disabled (not an NPE)\n\n"); - } - - printf(" MAC address | Age | Type \n"); - printf("___________________________________\n"); - - /* browse database */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (descriptor->portID == portID && descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - recordCount++; - - /* display entry */ - printf(" %02X:%02X:%02X:%02X:%02X:%02X | %5d | %s\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - - /* move to the next record */ - BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result); - - /* debug */ - if (local_result == IX_ETH_DB_BUSY) - { - return IX_ETH_DB_FAIL; - } - } - - /* display number of records */ - printf("\nFound %d records\n", recordCount); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays all the filtering records belonging to all the ports - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() - * instead. Calling this function is equivalent to calling - * ixEthDBFilteringDatabaseShowRecords(IX_ETH_DB_ALL_PORTS, IX_ETH_DB_FILTERING_RECORD) - */ -IX_ETH_DB_PUBLIC -void ixEthDBFilteringDatabaseShowAll() -{ - IxEthDBPortId portIndex; - - printf("\nEthernet learning/filtering database: listing %d ports\n\n", (UINT32) IX_ETH_DB_NUMBER_OF_PORTS); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - ixEthDBFilteringDatabaseShow(portIndex); - - if (portIndex < IX_ETH_DB_NUMBER_OF_PORTS - 1) - { - printf("\n"); - } - } -} - -/** - * @brief displays one record in a format depending on the record filter - * - * @param descriptor pointer to the record - * @param recordFilter format filter - * - * This function will display the fields in a record depending on the - * selected record filter. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRecordShow(MacDescriptor *descriptor, IxEthDBRecordType recordFilter) -{ - if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD - || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD)) - { - /* display VLAN record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n"); - printf("___________________________________________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | %d | %d | %d\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic", - IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag), - (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12, - IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag)); - } - else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | - | - | -\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - } - else if (recordFilter == IX_ETH_DB_FILTERING_RECORD) - { - /* display filtering record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Age | Type \n"); - printf("_______________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - } - else if (recordFilter == IX_ETH_DB_WIFI_RECORD) - { - /* display WiFi record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | GW MAC address \n"); - printf("_______________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_WIFI_RECORD) - { - if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* gateway address present */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | %02X:%02X:%02X:%02X:%02X:%02X \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.wifiData.gwMacAddress[0], - descriptor->recordData.wifiData.gwMacAddress[1], - descriptor->recordData.wifiData.gwMacAddress[2], - descriptor->recordData.wifiData.gwMacAddress[3], - descriptor->recordData.wifiData.gwMacAddress[4], - descriptor->recordData.wifiData.gwMacAddress[5]); - } - else - { - /* no gateway */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | ----no gateway----- \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - } - else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD) - { - /* display Firewall record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address \n"); - printf("__________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES) - { - /* display composite record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n"); - printf("_______________________________________________________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | VLAN | %2d | %s | %4d | %1d | %1d | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static " : "dynamic", - IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag), - (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12, - IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag)); - } - else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | Filter | %2d | %s | ---- | - | --- | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static " : "dynamic"); - } - else if (descriptor->type == IX_ETH_DB_WIFI_RECORD) - { - if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* gateway address present */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>AP | ---- | - | --- | %02X:%02X:%02X:%02X:%02X:%02X\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.wifiData.gwMacAddress[0], - descriptor->recordData.wifiData.gwMacAddress[1], - descriptor->recordData.wifiData.gwMacAddress[2], - descriptor->recordData.wifiData.gwMacAddress[3], - descriptor->recordData.wifiData.gwMacAddress[4], - descriptor->recordData.wifiData.gwMacAddress[5]); - } - else - { - /* no gateway */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>ST | ---- | - | --- | -- no gateway -- \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | FW | -- | ------- | ---- | - | --- | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else - { - printf("invalid record filter\n"); - } -} - -/** - * @brief displays the status, records and configuration information of a port - * - * @param portID ID of the port - * @param recordFilter record filter to display - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - UINT32 recordCount = 0; - HashIterator iterator; - IxEthDBStatus local_result; - - /* display port status */ - printf("== Port ID %d ==\n", portID); - - /* display capabilities */ - printf("- Capabilities: "); - - if ((portInfo->featureCapability & IX_ETH_DB_LEARNING) != 0) - { - printf("Learning (%s) ", ((portInfo->featureStatus & IX_ETH_DB_LEARNING) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - printf("VLAN/QoS (%s) ", ((portInfo->featureStatus & IX_ETH_DB_VLAN_QOS) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - printf("Firewall (%s) ", ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - printf("WiFi (%s) ", ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - printf("STP (%s) ", ((portInfo->featureStatus & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) ? "on" : "off"); - } - - printf("\n"); - - /* dependency map */ - ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap); - - /* NPE dynamic updates */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - printf(" - NPE dynamic update is %s\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled"); - } - else - { - printf(" - dynamic update disabled (not an NPE)\n"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - if ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - /* WiFi header conversion */ - if ((portInfo->frameControlDurationID - + portInfo->bbsid[0] - + portInfo->bbsid[1] - + portInfo->bbsid[2] - + portInfo->bbsid[3] - + portInfo->bbsid[4] - + portInfo->bbsid[5]) == 0) - { - printf(" - WiFi header conversion not configured\n"); - } - else - { - printf(" - WiFi header conversion: BBSID [%02X:%02X:%02X:%02X:%02X:%02X], Frame Control 0x%X, Duration/ID 0x%X\n", - portInfo->bbsid[0], - portInfo->bbsid[1], - portInfo->bbsid[2], - portInfo->bbsid[3], - portInfo->bbsid[4], - portInfo->bbsid[5], - portInfo->frameControlDurationID >> 16, - portInfo->frameControlDurationID & 0xFFFF); - } - } - else - { - printf(" - WiFi header conversion not enabled\n"); - } - } - - /* Firewall */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - if ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) - { - printf(" - Firewall is in %s-list mode\n", portInfo->firewallMode == IX_ETH_DB_FIREWALL_BLACK_LIST ? "black" : "white"); - printf(" - Invalid source MAC address filtering is %s\n", portInfo->srcAddressFilterEnabled ? "enabled" : "disabled"); - } - else - { - printf(" - Firewall not enabled\n"); - } - } - - /* browse database if asked to display records */ - if (recordFilter != IX_ETH_DB_NO_RECORD_TYPE) - { - printf("\n"); - ixEthDBHeaderShow(recordFilter); - - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (descriptor->portID == portID && (descriptor->type & recordFilter) != 0) - { - recordCount++; - - /* display entry */ - ixEthDBRecordShow(descriptor, recordFilter); - } - - /* move to the next record */ - BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result); - - /* debug */ - if (local_result == IX_ETH_DB_BUSY) - { - printf("EthDB (API): Error, database browser failed (no access), giving up\n"); - } - } - - printf("\nFound %d records\n\n", recordCount); - } -} - -/** - * @brief displays a record header - * - * @param recordFilter record type filter - * - * This function displays a record header, depending on - * the given record type filter. It is useful when used - * in conjunction with ixEthDBRecordShow which will display - * record fields formatted for the header, provided the same - * record filter is used. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_INVALID_ARG if the recordFilter - * parameter is invalid or not supported - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter) -{ - if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD - || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD)) - { - /* display VLAN record header */ - printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n"); - printf("___________________________________________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_FILTERING_RECORD) - { - /* display filtering record header */ - printf(" MAC address | Age | Type \n"); - printf("_______________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_WIFI_RECORD) - { - /* display WiFi record header */ - printf(" MAC address | GW MAC address \n"); - printf("_______________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD) - { - /* display Firewall record header */ - printf(" MAC address \n"); - printf("__________________\n"); - } - else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES) - { - /* display composite record header */ - printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n"); - printf("_______________________________________________________________________________\n"); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays database information (records and port information) - * - * @param portID ID of the port to display (or IX_ETH_DB_ALL_PORTS for all the ports) - * @param recordFilter record filter (use IX_ETH_DB_NO_RECORD_TYPE to display only - * port information) - * - * Note that this function is documented in the main component header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully or - * an appropriate error code otherwise - * - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter) -{ - IxEthDBPortId currentPort; - BOOL showAllPorts = (portID == IX_ETH_DB_ALL_PORTS); - - IX_ETH_DB_CHECK_PORT_ALL(portID); - - printf("\nEthernet learning/filtering database: listing %d port(s)\n\n", showAllPorts ? (UINT32) IX_ETH_DB_NUMBER_OF_PORTS : 1); - - currentPort = showAllPorts ? 0 : portID; - - while (currentPort != IX_ETH_DB_NUMBER_OF_PORTS) - { - /* display port info */ - ixEthDBPortInfoShow(currentPort, recordFilter); - - /* next port */ - currentPort = showAllPorts ? currentPort + 1 : IX_ETH_DB_NUMBER_OF_PORTS; - } - - return IX_ETH_DB_SUCCESS; -} - diff --git a/drivers/net/npe/IxEthDBSearch.c b/drivers/net/npe/IxEthDBSearch.c deleted file mode 100644 index 75fdebe483..0000000000 --- a/drivers/net/npe/IxEthDBSearch.c +++ /dev/null @@ -1,327 +0,0 @@ -/** - * @file IxEthDBSearch.c - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -extern HashTable dbHashtable; - -/** - * @brief matches two database records based on their MAC addresses - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0); -} - -/** - * @brief matches two database records based on their MAC addresses - * and VLAN IDs - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) == - IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) && - (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0); -} - -/** - * @brief matches two database records based on their MAC addresses - * and port IDs - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (entry->portID == reference->portID) && - (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0); -} - -/** - * @brief dummy matching function, registered for safety - * - * @param reference record to match against (unused) - * @param entry record to match (unused) - * - * This function is registered in the matching functions - * array on invalid types. Calling it will display an - * error message, indicating an error in the component logic. - * - * @return false - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBNullMatch(void *reference, void *entry) -{ - /* display an error message */ - - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0); - - - return false; -} - -/** - * @brief registers hash matching methods - * - * @param matchFunctions table of match functions to be populated - * - * This function registers the available record matching functions - * by indexing them on record types into the given function array. - * - * Note that it is compulsory to call this in ixEthDBInit(), - * otherwise hashtable searching and removal will not work - * - * @return number of registered functions - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions) -{ - UINT32 i; - - /* safety first */ - for ( i = 0 ; i < IX_ETH_DB_MAX_KEY_INDEX + 1 ; i++) - { - matchFunctions[i] = ixEthDBNullMatch; - } - - /* register MAC search method */ - matchFunctions[IX_ETH_DB_MAC_KEY] = ixEthDBAddressRecordMatch; - - /* register MAC/PortID search method */ - matchFunctions[IX_ETH_DB_MAC_PORT_KEY] = ixEthDBPortRecordMatch; - - /* register MAC/VLAN ID search method */ - matchFunctions[IX_ETH_DB_MAC_VLAN_KEY] = ixEthDBVlanRecordMatch; - - return 3; /* three methods */ -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference, &searchResult)); - - return searchResult; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter) -{ - MacDescriptor reference; - IxEthDBStatus result; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (macAddress == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - - /* set acceptable record types */ - reference.type = typeFilter; - - result = ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference); - - return result; -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param portID port ID to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address/port ID combination was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - reference.portID = portID; - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference, &searchResult)); - - return searchResult; -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param vlanID VLAN ID to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address/VLAN ID combination was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - reference.recordData.filteringVlanData.ieee802_1qTag = - IX_ETH_DB_SET_VLAN_ID(reference.recordData.filteringVlanData.ieee802_1qTag, vlanID); - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_VLAN_KEY, &reference, &searchResult)); - - return searchResult; -} diff --git a/drivers/net/npe/IxEthDBSpanningTree.c b/drivers/net/npe/IxEthDBSpanningTree.c deleted file mode 100644 index 029f7ac93c..0000000000 --- a/drivers/net/npe/IxEthDBSpanningTree.c +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file IxEthDBSpanningTree.c - * - * @brief Implementation of the STP API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -/** - * @brief sets the STP blocking state of a port - * - * @param portID ID of the port - * @param blocked true to block the port or false to unblock it - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL); - - ixEthDBPortInfo[portID].stpBlocked = blocked; - - FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief retrieves the STP blocking state of a port - * - * @param portID ID of the port - * @param blocked address to write the blocked status into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL); - - IX_ETH_DB_CHECK_REFERENCE(blocked); - - *blocked = ixEthDBPortInfo[portID].stpBlocked; - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBUtil.c b/drivers/net/npe/IxEthDBUtil.c deleted file mode 100644 index 24acc246b7..0000000000 --- a/drivers/net/npe/IxEthDBUtil.c +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file ethUtil.c - * - * @brief Utility functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxFeatureCtrl.h" -#include "IxEthDB_p.h" - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID) -{ - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((portID == 0) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - - if ((portID == 1) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - - if ((portID == 2) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -BOOL ixEthDBCheckSingleBitValue(UINT32 value) -{ -#if (CPU != SIMSPARCSOLARIS) && !defined (__wince) - UINT32 shift; - - /* use the count-leading-zeros XScale instruction */ - __asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value)); - - return ((value << shift) == 0x80000000UL); - -#else - - while (value != 0) - { - if (value == 1) return true; - else if ((value & 1) == 1) return false; - - value >>= 1; - } - - return false; - -#endif -} - -const char *mac2string(const unsigned char *mac) -{ - static char str[19]; - - if (mac == NULL) - { - return NULL; - } - - sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - - return str; -} diff --git a/drivers/net/npe/IxEthDBVlan.c b/drivers/net/npe/IxEthDBVlan.c deleted file mode 100644 index 522a30b1dd..0000000000 --- a/drivers/net/npe/IxEthDBVlan.c +++ /dev/null @@ -1,1179 +0,0 @@ -/** - * @file IxEthDBVlan.c - * - * @brief Implementation of the VLAN API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB.h" -#include "IxEthDB_p.h" - -/* forward prototypes */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex); -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet); - -/* contants used by various functions as "action" parameter */ -#define ADD_VLAN (0x1) -#define REMOVE_VLAN (0x2) - -/** - * @brief adds or removes a VLAN from a VLAN set - * - * @param vlanID VLAN ID to add or remove - * @param table VLAN set to add into or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBLocalVlanMembershipChange(UINT32 vlanID, IxEthDBVlanSet table, UINT32 action) -{ - UINT32 setOffset; - - /* add/remove VID to membership table */ - setOffset = VLAN_SET_OFFSET(vlanID); /* we need 9 bits to index the 512 byte membership array */ - - if (action == ADD_VLAN) - { - table[setOffset] |= 1 << VLAN_SET_MASK(vlanID); - } - else if (action == REMOVE_VLAN) - { - table[setOffset] &= ~(1 << VLAN_SET_MASK(vlanID)); - } -} - -/** - * @brief updates a set of 8 VLANs in an NPE - * - * @param portID ID of the port - * @param setOffset offset of the 8 VLANs - * - * This function updates the VLAN membership table - * and Transmit Tagging Info table for 8 consecutive - * VLAN IDs indexed by setOffset. - * - * For example, a setOffset of 0 indexes VLAN IDs 0 - * through 7, 1 indexes VLAN IDs 8 through 9 etc. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBVlanTableEntryUpdate(IxEthDBPortId portID, UINT32 setOffset) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETPORTVLANTABLEENTRY_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - 2 * setOffset, - portInfo->vlanMembership[setOffset], - portInfo->transmitTaggingInfo[setOffset]); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief updates a VLAN range in an NPE - * - * @param portID ID of the port - * - * This function is similar to @ref ixEthDBVlanTableEntryUpdate - * except that it can update more than one VLAN set (up to - * the entire VLAN membership and TTI tables if the offset is 0 - * and length is sizeof (IxEthDBVlanSet) (512 bytes). - * - * Updating the NPE via this method is slower as it requires - * a memory copy from SDRAM, hence it is recommended that the - * ixEthDBVlanTableEntryUpdate function is used where possible. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBVlanTableRangeUpdate(IxEthDBPortId portID) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - UINT8 *vlanUpdateZone = (UINT8 *) portInfo->updateMethod.vlanUpdateZone; - IxNpeMhMessage message; - UINT32 setIndex; - IX_STATUS result; - - /* copy membership info and transmit tagging into into exchange area */ - for (setIndex = 0 ; setIndex < sizeof (portInfo->vlanMembership) ; setIndex++) - { - /* membership and TTI data are interleaved */ - vlanUpdateZone[setIndex * 2] = portInfo->vlanMembership[setIndex]; - vlanUpdateZone[setIndex * 2 + 1] = portInfo->transmitTaggingInfo[setIndex]; - } - - IX_OSAL_CACHE_FLUSH(vlanUpdateZone, FULL_VLAN_BYTE_SIZE); - - /* build NPE message */ - FILL_SETPORTVLANTABLERANGE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 0, 0, - IX_OSAL_MMU_VIRT_TO_PHYS(vlanUpdateZone)); - - /* send message */ - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief adds or removes a VLAN from a port's VLAN membership table - * or Transmit Tagging Information table - * - * @param portID ID of the port - * @param vlanID VLAN ID to add or remove - * @param table to add or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortVlanMembershipChange(IxEthDBPortId portID, IxEthDBVlanId vlanID, IxEthDBVlanSet table, UINT32 action) -{ - /* change VLAN in local membership table */ - ixEthDBLocalVlanMembershipChange(vlanID, table, action); - - /* send updated entry to NPE */ - return ixEthDBVlanTableEntryUpdate(portID, VLAN_SET_OFFSET(vlanID)); -} - -/** - * @brief sets the default port VLAN tag (the lower 3 bytes are the PVID) - * - * @param portID ID of the port - * @param vlanTag port VLAN tag (802.1Q tag) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_TAG(vlanTag); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* add VLAN ID to local membership table */ - ixEthDBPortVlanMembershipChange(portID, - vlanTag & IX_ETH_DB_802_1Q_VLAN_MASK, - ixEthDBPortInfo[portID].vlanMembership, - ADD_VLAN); - - /* set tag in portInfo */ - ixEthDBPortInfo[portID].vlanTag = vlanTag; - - /* build VLAN_SetDefaultRxVID message */ - FILL_SETDEFAULTRXVID_MSG(message, - IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - IX_IEEE802_1Q_VLAN_TPID, - vlanTag); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief retrieves the default port VLAN tag (the lower 3 bytes are the PVID) - * - * @param portID ID of the port - * @param vlanTag address to write the port VLAN tag (802.1Q tag) into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanTag); - - *vlanTag = ixEthDBPortInfo[portID].vlanTag; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets the VLAN tag (the lower 3 bytes are the PVID) of a - * database filtering record - * - * @param portID ID of the port - * @param vlanTag VLAN tag (802.1Q tag) - * - * Important: filtering records are automatically converted to - * IX_ETH_DB_FILTERING_VLAN record when added a VLAN tag. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_VLAN_TAG(vlanTag); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* set record type to VLAN if not already set */ - descriptor->type = IX_ETH_DB_FILTERING_VLAN_RECORD; - - /* add vlan tag */ - descriptor->recordData.filteringVlanData.ieee802_1qTag = vlanTag; - - /* transaction completed */ - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief retrieves the VLAN tag (the lower 3 bytes are the PVID) from a - * database VLAN filtering record - * - * @param portID ID of the port - * @param vlanTag address to write the VLAN tag (802.1Q tag) into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_REFERENCE(vlanTag); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_FILTERING_VLAN_RECORD); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* get vlan tag */ - *vlanTag = descriptor->recordData.filteringVlanData.ieee802_1qTag; - - /* transaction completed */ - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief adds a VLAN to a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanID VLAN ID to add - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN); -} - -/** - * @brief removes a VLAN from a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanID VLAN ID to remove - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - /* for safety isolate only the VLAN ID in the tag (the lower 12 bits) */ - vlanID = vlanID & IX_ETH_DB_802_1Q_VLAN_MASK; - - /* check we're not asked to remove the default port VID */ - if (vlanID == IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN); -} - -/** - * @brief adds or removes a VLAN range from a port's - * VLAN membership table or TTI table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * @param table VLAN set to add or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortVlanMembershipRangeChange(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, IxEthDBVlanSet table, UINT32 action) -{ - UINT32 setOffsetMin, setOffsetMax; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_VLAN_ID(vlanIDMin); - - IX_ETH_DB_CHECK_VLAN_ID(vlanIDMax); - - /* for safety isolate only the VLAN ID in the tags (the lower 12 bits) */ - vlanIDMin = vlanIDMin & IX_ETH_DB_802_1Q_VLAN_MASK; - vlanIDMax = vlanIDMax & IX_ETH_DB_802_1Q_VLAN_MASK; - - /* is this a range? */ - if (vlanIDMax < vlanIDMin) - { - return IX_ETH_DB_INVALID_VLAN; - } - - /* check that we're not specifically asked to remove the default port VID */ - if (action == REMOVE_VLAN && vlanIDMax == vlanIDMin && IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag) == vlanIDMin) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* compute set offsets */ - setOffsetMin = VLAN_SET_OFFSET(vlanIDMin); - setOffsetMax = VLAN_SET_OFFSET(vlanIDMax); - - /* change VLAN range */ - for (; vlanIDMin <= vlanIDMax ; vlanIDMin++) - { - /* change vlan in local membership table */ - ixEthDBLocalVlanMembershipChange(vlanIDMin, table, action); - } - - /* if the range is within one set (max 8 VLANs in one table byte) we can just update that entry in the NPE */ - if (setOffsetMin == setOffsetMax) - { - /* send updated entry to NPE */ - return ixEthDBVlanTableEntryUpdate(portID, setOffsetMin); - } - else - { - /* update a zone of the membership/transmit tag info table */ - return ixEthDBVlanTableRangeUpdate(portID); - } -} - -/** - * @brief adds a VLAN range to a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN); -} - -/** - * @brief removes a VLAN range from a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN); -} - -/** - * @brief sets a port's VLAN membership table or TTI table and - * updates the NPE VLAN configuration - * - * @param portID ID of the port - * @param portVlanTable port VLAN table to set - * @param vlanSet new set contents - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - memcpy(portVlanTable, vlanSet, sizeof (IxEthDBVlanSet)); - - return ixEthDBVlanTableRangeUpdate(portID); -} - -/** - * @brief retireves a port's VLAN membership table or TTI table - * - * @param portID ID of the port - * @param portVlanTable port VLAN table to retrieve - * @param vlanSet address to - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - memcpy(vlanSet, portVlanTable, sizeof (IxEthDBVlanSet)); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanSet new VLAN membership table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IxEthDBVlanId vlanID; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - /* set the bit corresponding to the PVID just in case */ - vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag); - vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID); - - return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet); -} - -/** - * @brief retrieves a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanSet location to store the port's VLAN membership table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet); -} - -/** - * @brief enables or disables Egress tagging for one VLAN ID - * - * @param portID ID of the port - * @param vlanID VLAN ID to enable or disable Egress tagging on - * @param enabled true to enable and false to disable tagging - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN); -} - -/** - * @brief retrieves the Egress tagging status for one VLAN ID - * - * @param portID ID of the port - * @param vlanID VLAN ID to retrieve the tagging status for - * @param enabled location to store the tagging status - * (true - tagging enabled, false - tagging disabled) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(enabled); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - *enabled = ((ixEthDBPortInfo[portID].transmitTaggingInfo[VLAN_SET_OFFSET(vlanID)] & (1 << VLAN_SET_MASK(vlanID))) != 0); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables Egress VLAN tagging for a VLAN range - * - * @param portID ID of the port - * @param vlanIDMin start of VLAN range - * @param vlanIDMax end of VLAN range - * @param enabled true to enable or false to disable VLAN tagging - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN); -} - -/** - * @brief sets the Egress VLAN tagging table (the Transmit Tagging - * Information table) - * - * @param portID ID of the port - * @param vlanSet new TTI table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IxEthDBVlanId vlanID; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - /* set the PVID bit just in case */ - vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag); - vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID); - - return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet); -} - -/** - * @brief retrieves the Egress VLAN tagging table (the Transmit - * Tagging Information table) - * - * @param portID ID of the port - * @param vlanSet location to store the port's TTI table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet); -} - -/** - * @brief sends the NPE the updated frame filter and default - * Ingress tagging - * - * @param portID ID of the port - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBIngressVlanModeUpdate(IxEthDBPortId portID) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETRXTAGMODE_MSG(message, portID, portInfo->npeFrameFilter, portInfo->npeTaggingAction); - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the default Ingress tagging behavior - * - * @param portID ID of the port - * @param taggingAction default tagging behavior - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction) -{ - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - portInfo = &ixEthDBPortInfo[portID]; - - if (taggingAction == IX_ETH_DB_PASS_THROUGH) - { - portInfo->npeTaggingAction = 0x00; - } - else if (taggingAction == IX_ETH_DB_ADD_TAG) - { - portInfo->npeTaggingAction = 0x02; - } - else if (taggingAction == IX_ETH_DB_REMOVE_TAG) - { - portInfo->npeTaggingAction = 0x01; - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - portInfo->taggingAction = taggingAction; - - return ixEthDBIngressVlanModeUpdate(portID); -} - -/** - * @brief retrieves the default Ingress tagging behavior of a port - * - * @param portID ID of the port - * @param taggingAction location to save the default tagging behavior - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(taggingAction); - - *taggingAction = ixEthDBPortInfo[portID].taggingAction; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets the Ingress acceptable frame type filter - * - * @param portID ID of the port - * @param frameFilter acceptable frame type filter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter) -{ - PortInfo *portInfo; - IxEthDBStatus result = IX_ETH_DB_SUCCESS; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* check parameter range - the ORed value of the valid values is 0x7 - a value having extra bits is invalid */ - if ((frameFilter | 0x7) != 0x7 || frameFilter == 0) - { - return IX_ETH_DB_INVALID_ARG; - } - - portInfo = &ixEthDBPortInfo[portID]; - - portInfo->frameFilter = frameFilter; - portInfo->npeFrameFilter = 0; /* allow all by default */ - - /* if accepting priority tagged but not all VLAN tagged - set the membership table to contain only VLAN ID 0 - hence remove vlans 1-4094 and add VLAN ID 0 */ - if (((frameFilter & IX_ETH_DB_PRIORITY_TAGGED_FRAMES) != 0) - && ((frameFilter & IX_ETH_DB_VLAN_TAGGED_FRAMES) == 0)) - { - result = ixEthDBPortVlanMembershipRangeChange(portID, - 1, IX_ETH_DB_802_1Q_MAX_VLAN_ID, portInfo->vlanMembership, REMOVE_VLAN); - - if (result == IX_ETH_DB_SUCCESS) - { - ixEthDBLocalVlanMembershipChange(0, portInfo->vlanMembership, ADD_VLAN); - result = ixEthDBVlanTableRangeUpdate(portID); - } - } - - /* untagged only? */ - if (frameFilter == IX_ETH_DB_UNTAGGED_FRAMES) - { - portInfo->npeFrameFilter = 0x01; - } - - /* tagged only? */ - if ((frameFilter & IX_ETH_DB_UNTAGGED_FRAMES) == 0) - { - portInfo->npeFrameFilter = 0x02; - } - - if (result == IX_ETH_DB_SUCCESS) - { - result = ixEthDBIngressVlanModeUpdate(portID); - } - - return result; -} - -/** - * @brief retrieves the acceptable frame type filter for a port - * - * @param portID ID of the port - * @param frameFilter location to store the frame filter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(frameFilter); - - *frameFilter = ixEthDBPortInfo[portID].frameFilter; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sends an NPE the updated configuration related - * to one QoS priority (associated traffic class and AQM mapping) - * - * @param portID ID of the port - * @param classIndex QoS priority (traffic class index) - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex) -{ - IxNpeMhMessage message; - IX_STATUS result; - - UINT32 trafficClass = ixEthDBPortInfo[portID].priorityTable[classIndex]; - UINT32 aqmQueue = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[trafficClass]; - - FILL_SETRXQOSENTRY(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), classIndex, trafficClass, aqmQueue); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the priority mapping table - * - * @param portID ID of the port - * @param priorityTable new priority mapping table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) -{ - UINT32 classIndex; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(priorityTable); - - for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++) - { - /* check range */ - if (priorityTable[classIndex] >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - } - - /* set new traffic classes */ - for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++) - { - ixEthDBPortInfo[portID].priorityTable[classIndex] = priorityTable[classIndex]; - - if (ixEthDBUpdateTrafficClass(portID, classIndex) != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; - } - -/** - * @brief retrieves a port's priority mapping table - * - * @param portID ID of the port - * @param priorityTable location to store the priority table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(priorityTable); - - memcpy(priorityTable, ixEthDBPortInfo[portID].priorityTable, sizeof (IxEthDBPriorityTable)); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets one QoS priority => traffic class mapping - * - * @param portID ID of the port - * @param userPriority QoS (user) priority - * @param trafficClass associated traffic class - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* check ranges for userPriority and trafficClass */ - if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT || trafficClass >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - - ixEthDBPortInfo[portID].priorityTable[userPriority] = trafficClass; - - return ixEthDBUpdateTrafficClass(portID, userPriority); -} - -/** - * @brief retrieves one QoS priority => traffic class mapping - * - * @param portID ID of the port - * @param userPriority QoS (user) priority - * @param trafficClass location to store the associated traffic class - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(trafficClass); - - /* check userPriority range */ - if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - - *trafficClass = ixEthDBPortInfo[portID].priorityTable[userPriority]; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables the source port extraction - * from the VLAN TPID field - * - * @param portID ID of the port - * @param enable true to enable or false to disable - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} diff --git a/drivers/net/npe/IxEthDBWiFi.c b/drivers/net/npe/IxEthDBWiFi.c deleted file mode 100644 index 0a6043f364..0000000000 --- a/drivers/net/npe/IxEthDBWiFi.c +++ /dev/null @@ -1,480 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* forward prototypes */ -IX_ETH_DB_PUBLIC -MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations); - -/** - * @brief sets the BBSID value for the WiFi header conversion feature - * - * @param portID ID of the port - * @param bbsid pointer to the 6-byte BBSID value - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - IX_ETH_DB_CHECK_REFERENCE(bbsid); - - memcpy(ixEthDBPortInfo[portID].bbsid, bbsid, sizeof (IxEthDBMacAddr)); - - FILL_SETBBSID_MSG(message, portID, bbsid); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief updates the Frame Control and Duration/ID WiFi header - * conversion parameters in an NPE - * - * @param portID ID of the port - * - * This function will send a message to the NPE updating the - * frame conversion parameters for 802.3 => 802.11 header conversion. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBWiFiFrameControlDurationIDUpdate(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETFRAMECONTROLDURATIONID(message, portID, ixEthDBPortInfo[portID].frameControlDurationID); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the Duration/ID WiFi frame header conversion parameter - * - * @param portID ID of the port - * @param durationID 16-bit value containing the new Duration/ID parameter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF0000) | durationID; - - return ixEthDBWiFiFrameControlDurationIDUpdate(portID); -} - -/** - * @brief sets the Frame Control WiFi frame header conversion parameter - * - * @param portID ID of the port - * @param durationID 16-bit value containing the new Frame Control parameter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF) | (frameControl << 16); - - return ixEthDBWiFiFrameControlDurationIDUpdate(portID); -} - -/** - * @brief removes a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to remove - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_WIFI_RECORD; - recordTemplate.portID = portID; - - return ixEthDBRemove(&recordTemplate, NULL); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * @param gatewayMacAddr address of the gateway (or - * NULL if this is a station record) - * - * This function adds a record of type AP_TO_AP (gateway is not NULL) - * or AP_TO_STA (gateway is NULL) in the main database as a - * WiFi header conversion record. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBWiFiEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_WIFI_RECORD; - recordTemplate.portID = portID; - - if (gatewayMacAddr != NULL) - { - memcpy(recordTemplate.recordData.wifiData.gwMacAddress, gatewayMacAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_AP; - } - else - { - memset(recordTemplate.recordData.wifiData.gwMacAddress, 0, sizeof (IxEthDBMacAddr)); - - recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_STA; - } - - return ixEthDBAdd(&recordTemplate, NULL); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * @param gatewayMacAddr address of the gateway - * - * This function adds a record of type AP_TO_AP - * in the main database as a WiFi header conversion record. - * - * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd(). - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) -{ - IX_ETH_DB_CHECK_REFERENCE(gatewayMacAddr); - - return ixEthDBWiFiEntryAdd(portID, macAddr, gatewayMacAddr); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * - * This function adds a record of type AP_TO_STA - * in the main database as a WiFi header conversion record. - * - * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd(). - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - return ixEthDBWiFiEntryAdd(portID, macAddr, NULL); -} - -/** - * @brief selects a set of gateways from a tree of - * WiFi header conversion records - * - * @param stations binary tree containing pointers to WiFi header - * conversion records - * - * This function browses through the input binary tree, identifies - * records of type AP_TO_AP, clones these records and appends them - * to a vine (a single right-branch binary tree) which is returned - * as result. A maximum of MAX_GW_SIZE entries containing gateways - * will be cloned from the original tree. - * - * @return vine (linear binary tree) containing record - * clones of AP_TO_AP type, which have a gateway field - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations) -{ - MacTreeNodeStack *stack; - MacTreeNode *gateways, *insertionPlace; - UINT32 gwIndex = 1; /* skip the empty root */ - - if (stations == NULL) - { - return NULL; - } - - stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack)); - - if (stack == NULL) - { - ERROR_LOG("DB: (WiFi) failed to allocate the node stack for gateway tree linearization, out of memory?\n"); - return NULL; - } - - /* initialize root node */ - gateways = insertionPlace = NULL; - - /* start browsing the station tree */ - NODE_STACK_INIT(stack); - - /* initialize stack by pushing the tree root at offset 0 */ - NODE_STACK_PUSH(stack, stations, 0); - - while (NODE_STACK_NONEMPTY(stack)) - { - MacTreeNode *node; - UINT32 offset; - - NODE_STACK_POP(stack, node, offset); - - /* we can store maximum 31 (32 total, 1 empty root) entries in the gateway tree */ - if (offset > (MAX_GW_SIZE - 1)) break; - - /* check if this record has a gateway address */ - if (node->descriptor != NULL && node->descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* found a record, create an insertion place */ - if (insertionPlace != NULL) - { - insertionPlace->right = ixEthDBAllocMacTreeNode(); - insertionPlace = insertionPlace->right; - } - else - { - gateways = ixEthDBAllocMacTreeNode(); - insertionPlace = gateways; - } - - if (insertionPlace == NULL) - { - /* no nodes left, bail out with what we have */ - ixOsalCacheDmaFree(stack); - return gateways; - } - - /* clone the original record for the gateway tree */ - insertionPlace->descriptor = ixEthDBCloneMacDescriptor(node->descriptor); - - /* insert and update the offset in the original record */ - node->descriptor->recordData.wifiData.gwAddressIndex = gwIndex++; - } - - /* browse the tree */ - if (node->left != NULL) - { - NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset)); - } - - if (node->right != NULL) - { - NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset)); - } - } - - ixOsalCacheDmaFree(stack); - return gateways; -} - -/** - * @brief downloads the WiFi header conversion table to an NPE - * - * @param portID ID of the port - * - * This function prepares the WiFi header conversion tables and - * downloads them to the specified NPE port. - * - * The header conversion tables consist in the main table of - * addresses and the secondary table of gateways. AP_TO_AP records - * from the first table contain index fields into the second table - * for gateway selection. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID) -{ - IxEthDBPortMap query; - MacTreeNode *stations = NULL, *gateways = NULL, *gateway = NULL; - IxNpeMhMessage message; - PortInfo *portInfo; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - portInfo = &ixEthDBPortInfo[portID]; - - SET_DEPENDENCY_MAP(query, portID); - - ixEthDBUpdateLock(); - - stations = ixEthDBQuery(NULL, query, IX_ETH_DB_WIFI_RECORD, MAX_ELT_SIZE); - gateways = ixEthDBGatewaySelect(stations); - - /* clean up gw area */ - memset((void *) portInfo->updateMethod.npeGwUpdateZone, FULL_GW_BYTE_SIZE, 0); - - /* write all gateways */ - gateway = gateways; - - while (gateway != NULL) - { - ixEthDBNPEGatewayNodeWrite((void *) (((UINT32) portInfo->updateMethod.npeGwUpdateZone) - + gateway->descriptor->recordData.wifiData.gwAddressIndex * ELT_ENTRY_SIZE), - gateway); - - gateway = gateway->right; - } - - /* free the gateway tree */ - if (gateways != NULL) - { - ixEthDBFreeMacTreeNode(gateways); - } - - FILL_SETAPMACTABLE_MSG(message, - IX_OSAL_MMU_VIRT_TO_PHYS(portInfo->updateMethod.npeGwUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - /* update the main tree (the stations tree) */ - portInfo->updateMethod.searchTree = stations; - - result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_WIFI_RECORD); - } - - ixEthDBUpdateUnlock(); - - return result; -} diff --git a/drivers/net/npe/IxEthMii.c b/drivers/net/npe/IxEthMii.c deleted file mode 100644 index f8b439d9da..0000000000 --- a/drivers/net/npe/IxEthMii.c +++ /dev/null @@ -1,497 +0,0 @@ -/** - * @file IxEthMii.c - * - * @author Intel Corporation - * @date - * - * @brief MII control functions - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -#include "IxEthAcc.h" -#include "IxEthMii_p.h" - -#ifdef __wince -#include "IxOsPrintf.h" -#endif - -/* Array to store the phy IDs of the discovered phys */ -PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR]; - -/********************************************************* - * - * Scan for PHYs on the MII bus. This function returns - * an array of booleans, one for each PHY address. - * If a PHY is found at a particular address, the - * corresponding entry in the array is set to true. - * - */ - -PUBLIC IX_STATUS -ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) -{ - UINT32 i; - UINT16 regval, regvalId1, regvalId2; - - /*Search for PHYs on the MII*/ - /*Search for existant phys on the MDIO bus*/ - - if ((phyPresent == NULL) || - (maxPhyCount > IXP425_ETH_ACC_MII_MAX_ADDR)) - { - return IX_FAIL; - } - - /* fill the array */ - for(i=0; - i 0 && i= IX_ETH_MII_RESET_DELAY_MS) - { - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_FAIL; - } - - return IX_SUCCESS; - } /* end of if(ixEthMiiPhyId) */ - else if (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_KS8995_PHY_ID) - { - /* reset bit is reserved, just reset the control register */ - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_SUCCESS; - } - else - { - /* unknown PHY, set the control register reset bit, - * wait 2 s. and clear the control register. - */ - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_RESET); - - ixOsalSleep (IX_ETH_MII_RESET_DELAY_MS); - - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_SUCCESS; - } /* end of if-else(ixEthMiiPhyId) */ - } /* end of if(phyAddr) */ - return IX_FAIL; -} - -/***************************************************************** - * - * Link state query functions - */ - -PUBLIC IX_STATUS -ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) -{ - UINT16 ctrlRegval, statRegval, regval, regval4, regval5; - - /* check the parameters */ - if ((linkUp == NULL) || - (speed100 == NULL) || - (fullDuplex == NULL) || - (autoneg == NULL)) - { - return IX_FAIL; - } - - *linkUp = false; - *speed100 = false; - *fullDuplex = false; - *autoneg = false; - - if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && - (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID)) - { - if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) || - (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) || - (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID) - ) - { - /* --------------------------------------------------*/ - /* Retrieve information from PHY specific register */ - /* --------------------------------------------------*/ - if (ixEthAccMiiReadRtn(phyAddr, - IX_ETH_MII_STAT2_REG, - ®val) != IX_ETH_ACC_SUCCESS) - { - return IX_FAIL; - } - *linkUp = ((regval & IX_ETH_MII_SR2_LINK) != 0); - *speed100 = ((regval & IX_ETH_MII_SR2_100) != 0); - *fullDuplex = ((regval & IX_ETH_MII_SR2_FD) != 0); - *autoneg = ((regval & IX_ETH_MII_SR2_AUTO) != 0); - return IX_SUCCESS; - } /* end of if(ixEthMiiPhyId) */ - else - { - /* ----------------------------------------------------*/ - /* Retrieve information from status and ctrl registers */ - /* ----------------------------------------------------*/ - if (ixEthAccMiiReadRtn(phyAddr, - IX_ETH_MII_CTRL_REG, - &ctrlRegval) != IX_ETH_ACC_SUCCESS) - { - return IX_FAIL; - } - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &statRegval); - - *linkUp = ((statRegval & IX_ETH_MII_SR_LINK_STATUS) != 0); - if (*linkUp) - { - *autoneg = ((ctrlRegval & IX_ETH_MII_CR_AUTO_EN) != 0) && - ((statRegval & IX_ETH_MII_SR_AUTO_SEL) != 0) && - ((statRegval & IX_ETH_MII_SR_AUTO_NEG) != 0); - - if (*autoneg) - { - /* mask the current stat values with the capabilities */ - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_ADS_REG, ®val4); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_PRTN_REG, ®val5); - /* merge the flags from the 3 registers */ - regval = (statRegval & ((regval4 & regval5) << 6)); - /* initialise from status register values */ - if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0) - { - /* 100 Base X full dplx */ - *speed100 = true; - *fullDuplex = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0) - { - /* 100 Base X half dplx */ - *speed100 = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0) - { - /* 10 mb full dplx */ - *fullDuplex = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0) - { - /* 10 mb half dplx */ - return IX_SUCCESS; - } - } /* end of if(autoneg) */ - else - { - /* autonegotiate not complete, return setup parameters */ - *speed100 = ((ctrlRegval & IX_ETH_MII_CR_100) != 0); - *fullDuplex = ((ctrlRegval & IX_ETH_MII_CR_FDX) != 0); - } - } /* end of if(linkUp) */ - } /* end of if-else(ixEthMiiPhyId) */ - } /* end of if(phyAddr) */ - else - { - return IX_FAIL; - } /* end of if-else(phyAddr) */ - return IX_SUCCESS; -} - -/***************************************************************** - * - * Link state display functions - */ - -PUBLIC IX_STATUS -ixEthMiiPhyShow (UINT32 phyAddr) -{ - BOOL linkUp, speed100, fullDuplex, autoneg; - UINT16 cregval; - UINT16 sregval; - - - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &sregval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_CTRL_REG, &cregval); - - /* get link information */ - if (ixEthMiiLinkStatus(phyAddr, - &linkUp, - &speed100, - &fullDuplex, - &autoneg) != IX_ETH_ACC_SUCCESS) - { - printf("PHY Status unknown\n"); - return IX_FAIL; - } - - printf("PHY ID [phyAddr]: %8.8x\n",ixEthMiiPhyId[phyAddr]); - printf( " Status reg: %4.4x\n",sregval); - printf( " control reg: %4.4x\n",cregval); - /* display link information */ - printf("PHY Status:\n"); - printf(" Link is %s\n", - (linkUp ? "Up" : "Down")); - if((sregval & IX_ETH_MII_SR_REMOTE_FAULT) != 0) - { - printf(" Remote fault detected\n"); - } - printf(" Auto Negotiation %s\n", - (autoneg ? "Completed" : "Not Completed")); - - printf("PHY Configuration:\n"); - printf(" Speed %sMb/s\n", - (speed100 ? "100" : "10")); - printf(" %s Duplex\n", - (fullDuplex ? "Full" : "Half")); - printf(" Auto Negotiation %s\n", - (autoneg ? "Enabled" : "Disabled")); - return IX_SUCCESS; -} - diff --git a/drivers/net/npe/IxFeatureCtrl.c b/drivers/net/npe/IxFeatureCtrl.c deleted file mode 100644 index b6728e4a44..0000000000 --- a/drivers/net/npe/IxFeatureCtrl.c +++ /dev/null @@ -1,422 +0,0 @@ -/** - * @file IxFeatureCtrl.c - * - * @author Intel Corporation - * @date 29-Jan-2003 - * - * @brief Feature Control Public API Implementation - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -#include "IxOsal.h" -#include "IxVersionId.h" -#include "IxFeatureCtrl.h" - -/* Macro to read from the Feature Control Register */ -#define IX_FEATURE_CTRL_READ(result) \ -do { \ -ixFeatureCtrlExpMap(); \ -(result) = IX_OSAL_READ_LONG(ixFeatureCtrlRegister); \ -} while (0) - -/* Macro to write to the Feature Control Register */ -#define IX_FEATURE_CTRL_WRITE(value) \ -do { \ -ixFeatureCtrlExpMap(); \ -IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \ -} while (0) - -/* - * This is the offset of the feature register relative to the base of the - * Expansion Bus Controller MMR. - */ -#define IX_FEATURE_CTRL_REG_OFFSET (0x00000028) - - -/* Boolean to mark the fact that the EXP_CONFIG address space was mapped */ -PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false; - -/* Pointer holding the virtual address of the Feature Control Register */ -PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL; - -/* Place holder to store the software configuration */ -PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX]; - -/* Flag to control swConfiguration[] is initialized once */ -PRIVATE BOOL swConfigurationFlag = false ; - -/* Array containing component mask values */ -#ifdef __ixp42X -UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = { - (0x1<> IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET) - & IX_FEATURE_CTRL_DEVICE_TYPE_MASK); -} /* End function ixFeatureCtrlDeviceRead */ - - -/** - * Function definition: ixFeatureCtrlSwConfigurationCheck - */ -IX_STATUS -ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType) -{ - if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX) - { - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDOUT, - "FeatureCtrl: Invalid software configuraiton input.\n", - 0, 0, 0, 0, 0, 0); - - return IX_FEATURE_CTRL_SWCONFIG_DISABLED; - } - - /* The function will only initialize once. */ - ixFeatureCtrlSwConfigurationInit(); - - /* Check and return software configuration */ - return ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED); -} - -/** - * Function definition: ixFeatureCtrlSwConfigurationWrite - */ -void -ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled) -{ - if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX) - { - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDOUT, - "FeatureCtrl: Invalid software configuraiton input.\n", - 0, 0, 0, 0, 0, 0); - - return; - } - - /* The function will only initialize once. */ - ixFeatureCtrlSwConfigurationInit(); - - /* Write software configuration */ - swConfiguration[(UINT32)swConfigType]=enabled ; -} - -/** - * Function definition: ixFeatureCtrlIxp400SwVersionShow - */ -void -ixFeatureCtrlIxp400SwVersionShow (void) -{ - printf ("\nIXP400 Software Release %s %s\n\n", IX_VERSION_ID, IX_VERSION_INTERNAL_ID); - -} - -/** - * Function definition: ixFeatureCtrlSoftwareBuildGet - */ -IxFeatureCtrlBuildDevice -ixFeatureCtrlSoftwareBuildGet (void) -{ - #ifdef __ixp42X - return IX_FEATURE_CTRL_SW_BUILD_IXP42X; - #else - return IX_FEATURE_CTRL_SW_BUILD_IXP46X; - #endif -} diff --git a/drivers/net/npe/IxNpeDl.c b/drivers/net/npe/IxNpeDl.c deleted file mode 100644 index bfeac87790..0000000000 --- a/drivers/net/npe/IxNpeDl.c +++ /dev/null @@ -1,940 +0,0 @@ -/** - * @file IxNpeDl.c - * - * @author Intel Corporation - * @date 08 January 2002 - * - * @brief This file contains the implementation of the public API for the - * IXP425 NPE Downloader component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required - */ - -/* - * Put the user defined include files required - */ -#include "IxNpeDl.h" -#include "IxNpeDlImageMgr_p.h" -#include "IxNpeDlNpeMgr_p.h" -#include "IxNpeDlMacros_p.h" -#include "IxFeatureCtrl.h" -#include "IxOsal.h" -/* - * #defines used in this file - */ - #define IMAGEID_MAJOR_NUMBER_DEFAULT 0 - #define IMAGEID_MINOR_NUMBER_DEFAULT 0 - -/* - * Typedefs whose scope is limited to this file. - */ -typedef struct -{ - BOOL validImage; - IxNpeDlImageId imageId; -} IxNpeDlNpeState; - -/* module statistics counters */ -typedef struct -{ - UINT32 attemptedDownloads; - UINT32 successfulDownloads; - UINT32 criticalFailDownloads; -} IxNpeDlStats; - -/* - * Variable declarations global to this file only. Externs are followed - * by static variables. - */ -static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] = -{ - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}} -}; - -static IxNpeDlStats ixNpeDlStats; - -/* - * Software guard to prevent NPE from being started multiple times. - */ -static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ; - - -/* - * static function prototypes. - */ -PRIVATE IX_STATUS -ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId); - -/* - * Function definition: ixNpeDlImageDownload - */ -PUBLIC IX_STATUS -ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr, - BOOL verify) -{ - UINT32 imageSize; - UINT32 *imageCodePtr = NULL; - IX_STATUS status; - IxNpeDlNpeId npeId = imageIdPtr->npeId; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageDownload\n"); - - ixNpeDlStats.attemptedDownloads++; - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageDownload - invalid parameter\n"); - } - else - { - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } - } /* end of if(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEB) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEC) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - } /* end of if(IX_FEATURE_CTRL_SILICON_TYPE_B0) */ /*End of Silicon Type Check*/ - - /* stop and reset the NPE */ - if (IX_SUCCESS != ixNpeDlNpeStopAndReset (npeId)) - { - IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n"); - return IX_FAIL; - } - - /* Locate image */ - status = ixNpeDlImageMgrImageLocate (imageIdPtr, &imageCodePtr, - &imageSize); - if (IX_SUCCESS == status) - { - /* - * If download was successful, store image Id in list of - * currently loaded images. If a critical error occured - * during download, record that the NPE has an invalid image - */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, - verify); - if (IX_SUCCESS == status) - { - ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = true; - ixNpeDlStats.successfulDownloads++; - - status = ixNpeDlNpeExecutionStart (npeId); - } - else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || - (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) - { - ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = false; - ixNpeDlStats.criticalFailDownloads++; - } - } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ - } /* end of if-else(npeId) */ /* condition: parameter checks ok */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageDownload : status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlAvailableImagesCountGet - */ -PUBLIC IX_STATUS -ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlAvailableImagesCountGet\n"); - - /* Check input parameters */ - if (numImagesPtr == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesCountGet - " - "invalid parameter\n"); - } - else - { - /* - * Use ImageMgr module to get no. of images listed in Image Library Header. - * If NULL is passed as imageListPtr parameter to following function, - * it will only fill number of images into numImagesPtr - */ - status = ixNpeDlImageMgrImageListExtract (NULL, numImagesPtr); - } /* end of if-else(numImagesPtr) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlAvailableImagesCountGet : " - "status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlAvailableImagesListGet - */ -PUBLIC IX_STATUS -ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr, - UINT32 *listSizePtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlAvailableImagesListGet\n"); - - /* Check input parameters */ - if ((imageIdListPtr == NULL) || (listSizePtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesListGet - " - "invalid parameter\n"); - } - else - { - /* Call ImageMgr to get list of images listed in Image Library Header */ - status = ixNpeDlImageMgrImageListExtract (imageIdListPtr, - listSizePtr); - } /* end of if-else(imageIdListPtr) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlAvailableImagesListGet : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlLoadedImageGet - */ -PUBLIC IX_STATUS -ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId, - IxNpeDlImageId *imageIdPtr) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlLoadedImageGet\n"); - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0) || (imageIdPtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageGet - invalid parameter\n"); - } - else - { - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEB && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEC && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - } /* end of if not IXP42x-A0 silicon */ - - if (ixNpeDlNpeState[npeId].validImage) - { - /* use npeId to get imageId from list of currently loaded - images */ - *imageIdPtr = ixNpeDlNpeState[npeId].imageId; - } - else - { - status = IX_FAIL; - } /* end of if-else(ixNpeDlNpeState) */ - } /* end of if-else(npeId) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlLoadedImageGet : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlLatestImageGet - */ -PUBLIC IX_STATUS -ixNpeDlLatestImageGet ( - IxNpeDlNpeId npeId, - IxNpeDlFunctionalityId functionalityId, - IxNpeDlImageId *imageIdPtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlLatestImageGet\n"); - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || - (npeId < 0) || - (imageIdPtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlLatestImageGet - " - "invalid parameter\n"); - } /* end of if(npeId) */ - else - { - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEB && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEC && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - } /* end of if not IXP42x-A0 silicon */ - - imageIdPtr->npeId = npeId; - imageIdPtr->functionalityId = functionalityId; - imageIdPtr->major = IMAGEID_MAJOR_NUMBER_DEFAULT; - imageIdPtr->minor = IMAGEID_MINOR_NUMBER_DEFAULT; - /* Call ImageMgr to get list of images listed in Image Library Header */ - status = ixNpeDlImageMgrLatestImageExtract(imageIdPtr); - } /* end of if-else(npeId) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlLatestImageGet : status = %d\n", - status); - - return status; -} - -/* - * Function definition: ixNpeDlNpeStopAndReset - */ -PUBLIC IX_STATUS -ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeStopAndReset\n"); - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeStopAndReset - invalid Npe ID\n"); - status = IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42x-A0 Silicon */ - - if (status == IX_SUCCESS) - { - /* call NpeMgr function to stop the NPE */ - status = ixNpeDlNpeMgrNpeStop (npeId); - if (status == IX_SUCCESS) - { - /* call NpeMgr function to reset the NPE */ - status = ixNpeDlNpeMgrNpeReset (npeId); - } - } /* end of if(status) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeStopAndReset : status = %d\n", status); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = false ; - } - - return status; -} - -/* - * Function definition: ixNpeDlNpeExecutionStart - */ -PUBLIC IX_STATUS -ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeExecutionStart\n"); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStart - invalid Npe ID\n"); - return IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42x-A0 Silicon */ - - if (true == ixNpeDlNpeStarted[npeId]) - { - /* NPE has been started. */ - return IX_SUCCESS ; - } - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* call NpeMgr function to start the NPE */ - status = ixNpeDlNpeMgrNpeStart (npeId); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has started */ - ixNpeDlNpeStarted[npeId] = true ; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeExecutionStart : status = %d\n", - status); - - return status; -} - -/* - * Function definition: ixNpeDlNpeExecutionStop - */ -PUBLIC IX_STATUS -ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeExecutionStop\n"); - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStop - invalid Npe ID\n"); - status = IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42X-AO Silicon */ - - if (status == IX_SUCCESS) - { - /* call NpeMgr function to stop the NPE */ - status = ixNpeDlNpeMgrNpeStop (npeId); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeExecutionStop : status = %d\n", - status); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = false ; - } - - return status; -} - -/* - * Function definition: ixNpeDlUnload - */ -PUBLIC IX_STATUS -ixNpeDlUnload (void) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlUnload\n"); - - status = ixNpeDlNpeMgrUninit(); - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlUnload : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlStatsShow - */ -PUBLIC void -ixNpeDlStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlStatsShow:\n" - "\tDownloads Attempted by user: %u\n" - "\tSuccessful Downloads: %u\n" - "\tFailed Downloads (due to Critical Error): %u\n\n", - ixNpeDlStats.attemptedDownloads, - ixNpeDlStats.successfulDownloads, - ixNpeDlStats.criticalFailDownloads, - 0,0,0); - - ixNpeDlImageMgrStatsShow (); - ixNpeDlNpeMgrStatsShow (); -} - -/* - * Function definition: ixNpeDlStatsReset - */ -PUBLIC void -ixNpeDlStatsReset (void) -{ - ixNpeDlStats.attemptedDownloads = 0; - ixNpeDlStats.successfulDownloads = 0; - ixNpeDlStats.criticalFailDownloads = 0; - - ixNpeDlImageMgrStatsReset (); - ixNpeDlNpeMgrStatsReset (); -} - -/* - * Function definition: ixNpeDlNpeInitAndStartInternal - */ -PRIVATE IX_STATUS -ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, - UINT32 imageId) -{ - UINT32 imageSize; - UINT32 *imageCodePtr = NULL; - IX_STATUS status; - IxNpeDlNpeId npeId = IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId); - IxFeatureCtrlDeviceId deviceId = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId); - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeInitAndStartInternal\n"); - - ixNpeDlStats.attemptedDownloads++; - - /* Check input parameter device correctness */ - if ((deviceId >= IX_FEATURE_CTRL_DEVICE_TYPE_MAX) || - (deviceId < IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "invalid parameter\n"); - } /* End valid device id checking */ - - /* Check input parameters */ - else if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "invalid parameter\n"); - } - - else - { - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* Checking if image being loaded is meant for device that is running. - * Image is forward compatible. i.e Image built for IXP42X should run - * on IXP46X but not vice versa.*/ - if (deviceId > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "Device type mismatch. NPE Image not " - "meant for device in use \n"); - return IX_NPEDL_DEVICE_ERR; - }/* if statement - matching image device and current device */ - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } - } /* end of if(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEB) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEC) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - } /* end of if not IXP42X-A0 Silicon */ - - /* stop and reset the NPE */ - status = ixNpeDlNpeStopAndReset (npeId); - if (IX_SUCCESS != status) - { - IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n"); - return status; - } - - /* Locate image */ - status = ixNpeDlImageMgrImageFind (imageLibrary, imageId, - &imageCodePtr, &imageSize); - if (IX_SUCCESS == status) - { - /* - * If download was successful, store image Id in list of - * currently loaded images. If a critical error occured - * during download, record that the NPE has an invalid image - */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true); - if (IX_SUCCESS == status) - { - ixNpeDlNpeState[npeId].validImage = true; - ixNpeDlStats.successfulDownloads++; - - status = ixNpeDlNpeExecutionStart (npeId); - } - else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || - (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) - { - ixNpeDlNpeState[npeId].validImage = false; - ixNpeDlStats.criticalFailDownloads++; - } - - /* NOTE - The following section of code is here to support - * a deprecated function ixNpeDlLoadedImageGet(). When that - * function is removed from the API, this code should be revised. - */ - ixNpeDlNpeState[npeId].imageId.npeId = npeId; - ixNpeDlNpeState[npeId].imageId.functionalityId = - IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId); - ixNpeDlNpeState[npeId].imageId.major = - IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId); - ixNpeDlNpeState[npeId].imageId.minor = - IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId); - } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ - } /* end of if-else(npeId-deviceId) */ /* condition: parameter checks ok */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeInitAndStartInternal : " - "status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlCustomImageNpeInitAndStart - */ -PUBLIC IX_STATUS -ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary, - UINT32 imageId) -{ - IX_STATUS status; - - if (imageLibrary == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlCustomImageNpeInitAndStart " - "- invalid parameter\n"); - } - else - { - status = ixNpeDlNpeInitAndStartInternal (imageLibrary, imageId); - } /* end of if-else(imageLibrary) */ - - return status; -} - -/* - * Function definition: ixNpeDlNpeInitAndStart - */ -PUBLIC IX_STATUS -ixNpeDlNpeInitAndStart (UINT32 imageId) -{ - return ixNpeDlNpeInitAndStartInternal (NULL, imageId); -} - -/* - * Function definition: ixNpeDlLoadedImageFunctionalityGet - */ -PUBLIC IX_STATUS -ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId, - UINT8 *functionalityId) -{ - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet " - "- invalid parameter\n"); - return IX_NPEDL_PARAM_ERR; - } - if (functionalityId == NULL) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet " - "- invalid parameter\n"); - return IX_NPEDL_PARAM_ERR; - } - - if (ixNpeDlNpeState[npeId].validImage) - { - *functionalityId = ixNpeDlNpeState[npeId].imageId.functionalityId; - return IX_SUCCESS; - } - else - { - return IX_FAIL; - } -} diff --git a/drivers/net/npe/IxNpeDlImageMgr.c b/drivers/net/npe/IxNpeDlImageMgr.c deleted file mode 100644 index 0484483882..0000000000 --- a/drivers/net/npe/IxNpeDlImageMgr.c +++ /dev/null @@ -1,687 +0,0 @@ -/** - * @file IxNpeDlImageMgr.c - * - * @author Intel Corporation - * @date 09 January 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader ImageMgr module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the system defined include files required. - */ -#include "IxOsal.h" - -/* - * Put the user defined include files required. - */ -#include "IxNpeDlImageMgr_p.h" -#include "IxNpeDlMacros_p.h" - -/* - * define the flag which toggles the firmare inclusion - */ -#define IX_NPE_MICROCODE_FIRMWARE_INCLUDED 1 -#include "IxNpeMicrocode.h" - -/* - * Indicates the start of an NPE Image, in new NPE Image Library format. - * 2 consecutive occurances indicates the end of the NPE Image Library - */ -#define NPE_IMAGE_MARKER 0xfeedf00d - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef struct -{ - UINT32 size; - UINT32 offset; - UINT32 id; -} IxNpeDlImageMgrImageEntry; - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef union -{ - IxNpeDlImageMgrImageEntry image; - UINT32 eohMarker; -} IxNpeDlImageMgrHeaderEntry; - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef struct -{ - UINT32 signature; - /* 1st entry in the header (there may be more than one) */ - IxNpeDlImageMgrHeaderEntry entry[1]; -} IxNpeDlImageMgrImageLibraryHeader; - - -/* - * NPE Image Header definition, used in new NPE Image Library format - */ -typedef struct -{ - UINT32 marker; - UINT32 id; - UINT32 size; -} IxNpeDlImageMgrImageHeader; - -/* module statistics counters */ -typedef struct -{ - UINT32 invalidSignature; - UINT32 imageIdListOverflow; - UINT32 imageIdNotFound; -} IxNpeDlImageMgrStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ -static IxNpeDlImageMgrStats ixNpeDlImageMgrStats; - -static UINT32* getIxNpeMicroCodeImageLibrary(void) -{ - char *s; - - if ((s = getenv("npe_ucode")) != NULL) - return (UINT32*) simple_strtoul(s, NULL, 16); - else - return NULL; -} - -/* - * static function prototypes. - */ -PRIVATE BOOL -ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary); - -PRIVATE void -ixNpeDlImageMgrImageIdFormat (UINT32 rawImageId, IxNpeDlImageId *imageId); - -PRIVATE BOOL -ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); - -PRIVATE BOOL -ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); - -#if 0 -PRIVATE IX_STATUS -ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize); - -/* - * Function definition: ixNpeDlImageMgrMicrocodeImageLibraryOverride - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrMicrocodeImageLibraryOverride ( - UINT32 *clientImageLibrary) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrMicrocodeImageLibraryOverride\n"); - - if (ixNpeDlImageMgrSignatureCheck (clientImageLibrary)) - { - IxNpeMicroCodeImageLibrary = clientImageLibrary; - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrMicrocodeImageLibraryOverride: " - "Client-supplied image has invalid signature\n"); - status = IX_FAIL; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrMicrocodeImageLibraryOverride: status = %d\n", - status); - return status; -} -#endif - -/* - * Function definition: ixNpeDlImageMgrImageListExtract - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrImageListExtract ( - IxNpeDlImageId *imageListPtr, - UINT32 *numImages) -{ - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - IX_STATUS status = IX_SUCCESS; - UINT32 imageCount = 0; - IxNpeDlImageMgrImageLibraryHeader *header; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageListExtract\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - /* - * if the image list container from calling function has capacity, - * add the image id to the list - */ - if ((imageListPtr != NULL) && (imageCount < *numImages)) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - imageListPtr[imageCount] = formattedImageId; - } - /* imageCount reflects no. of image entries in image library header */ - imageCount++; - } - - /* - * if image list container from calling function was too small to - * contain all image ids in the header, set return status to FAIL - */ - if ((imageListPtr != NULL) && (imageCount > *numImages)) - { - status = IX_FAIL; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: " - "number of Ids found exceeds list capacity\n"); - ixNpeDlImageMgrStats.imageIdListOverflow++; - } - /* return number of image ids found in image library header */ - *numImages = imageCount; - } - else - { - status = IX_FAIL; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: " - "invalid signature in image\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageListExtract: status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlImageMgrImageLocate - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrImageLocate ( - IxNpeDlImageId *imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - UINT32 imageOffset; - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - /* used to index image entries in image library header */ - UINT32 imageCount = 0; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageLocate\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image library header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - /* if a match for imageId is found in the image library header... */ - if (ixNpeDlImageMgrImageIdCompare (imageId, &formattedImageId)) - { - /* - * get pointer to the image in the image library using offset from - * 1st word in image library - */ - UINT32 *tmp=getIxNpeMicroCodeImageLibrary(); - imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &tmp[imageOffset]; - /* get the image size */ - *imageSize = header->entry[imageCount].image.size; - status = IX_SUCCESS; - break; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageLocate: status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageMgrLatestImageExtract - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId) -{ - UINT32 imageCount = 0; - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrLatestImageExtract\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image library header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - /* - * if a match for the npe Id and functionality Id of the imageId is - * found in the image library header... - */ - if(ixNpeDlImageMgrNpeFunctionIdCompare(imageId, &formattedImageId)) - { - if(imageId->major <= formattedImageId.major) - { - if(imageId->minor < formattedImageId.minor) - { - imageId->minor = formattedImageId.minor; - } - imageId->major = formattedImageId.major; - } - status = IX_SUCCESS; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageExtract: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageGet: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrLatestImageGet: status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageMgrSignatureCheck - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary) -{ - IxNpeDlImageMgrImageLibraryHeader *header = - (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary; - BOOL result = true; - - if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE) - { - result = false; - ixNpeDlImageMgrStats.invalidSignature++; - } - - return result; -} - - -/* - * Function definition: ixNpeDlImageMgrImageIdFormat - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE void -ixNpeDlImageMgrImageIdFormat ( - UINT32 rawImageId, - IxNpeDlImageId *imageId) -{ - imageId->npeId = (rawImageId >> - IX_NPEDL_IMAGEID_NPEID_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->functionalityId = (rawImageId >> - IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->major = (rawImageId >> - IX_NPEDL_IMAGEID_MAJOR_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->minor = (rawImageId >> - IX_NPEDL_IMAGEID_MINOR_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - -} - - -/* - * Function definition: ixNpeDlImageMgrImageIdCompare - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrImageIdCompare ( - IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB) -{ - if ((imageIdA->npeId == imageIdB->npeId) && - (imageIdA->functionalityId == imageIdB->functionalityId) && - (imageIdA->major == imageIdB->major) && - (imageIdA->minor == imageIdB->minor)) - { - return true; - } - else - { - return false; - } -} - -/* - * Function definition: ixNpeDlImageMgrNpeFunctionIdCompare - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrNpeFunctionIdCompare ( - IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB) -{ - if ((imageIdA->npeId == imageIdB->npeId) && - (imageIdA->functionalityId == imageIdB->functionalityId)) - { - return true; - } - else - { - return false; - } -} - - -/* - * Function definition: ixNpeDlImageMgrStatsShow - */ -void -ixNpeDlImageMgrStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlImageMgrStatsShow:\n" - "\tInvalid Image Signatures: %u\n" - "\tImage Id List capacity too small: %u\n" - "\tImage Id not found: %u\n\n", - ixNpeDlImageMgrStats.invalidSignature, - ixNpeDlImageMgrStats.imageIdListOverflow, - ixNpeDlImageMgrStats.imageIdNotFound, - 0,0,0); -} - - -/* - * Function definition: ixNpeDlImageMgrStatsReset - */ -void -ixNpeDlImageMgrStatsReset (void) -{ - ixNpeDlImageMgrStats.invalidSignature = 0; - ixNpeDlImageMgrStats.imageIdListOverflow = 0; - ixNpeDlImageMgrStats.imageIdNotFound = 0; -} - - -#if 0 -/* - * Function definition: ixNpeDlImageMgrImageFind_legacy - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE IX_STATUS -ixNpeDlImageMgrImageFind_legacy ( - UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - UINT32 imageOffset; - /* used to index image entries in image library header */ - UINT32 imageCount = 0; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - BOOL imageFound = false; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageFind\n"); - - - /* If user didn't specify a library to use, use the default - * one from IxNpeMicrocode.h - */ - if (imageLibrary == NULL) - { - imageLibrary = IxNpeMicroCodeImageLibrary; - } - - if (ixNpeDlImageMgrSignatureCheck (imageLibrary)) - { - header = (IxNpeDlImageMgrImageLibraryHeader *) imageLibrary; - - /* for each image entry in the image library header ... */ - while ((header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) && !(imageFound)) - { - /* if a match for imageId is found in the image library header... */ - if (imageId == header->entry[imageCount].image.id) - { - /* - * get pointer to the image in the image library using offset from - * 1st word in image library - */ - imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &imageLibrary[imageOffset]; - /* get the image size */ - *imageSize = header->entry[imageCount].image.size; - status = IX_SUCCESS; - imageFound = true; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status); - return status; -} -#endif - -/* - * Function definition: ixNpeDlImageMgrImageFind - */ -IX_STATUS -ixNpeDlImageMgrImageFind ( - UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - IxNpeDlImageMgrImageHeader *image; - UINT32 offset = 0; - - /* If user didn't specify a library to use, use the default - * one from IxNpeMicrocode.h - */ - if (imageLibrary == NULL) - { -#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE - if (ixNpeMicrocode_binaryArray == NULL) - { - printk (KERN_ERR "ixp400.o: ERROR, no Microcode found in memory\n"); - return IX_FAIL; - } - else - { - imageLibrary = ixNpeMicrocode_binaryArray; - } -#else - imageLibrary = getIxNpeMicroCodeImageLibrary(); - if (imageLibrary == NULL) - { - printf ("npe: ERROR, no Microcode found in memory\n"); - return IX_FAIL; - } -#endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */ - } - -#if 0 - /* For backward's compatibility with previous image format */ - if (ixNpeDlImageMgrSignatureCheck(imageLibrary)) - { - return ixNpeDlImageMgrImageFind_legacy(imageLibrary, - imageId, - imagePtr, - imageSize); - } -#endif - - while (*(imageLibrary+offset) == NPE_IMAGE_MARKER) - { - image = (IxNpeDlImageMgrImageHeader *)(imageLibrary+offset); - offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32); - - if (image->id == imageId) - { - *imagePtr = imageLibrary + offset; - *imageSize = image->size; - return IX_SUCCESS; - } - /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */ - else if (image->id == NPE_IMAGE_MARKER) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - /* reached end of library, image not found */ - return IX_FAIL; - } - offset += image->size; - } - - /* If we get here, our image library may be corrupted */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "image library format may be invalid or corrupted\n"); - return IX_FAIL; -} - diff --git a/drivers/net/npe/IxNpeDlNpeMgr.c b/drivers/net/npe/IxNpeDlNpeMgr.c deleted file mode 100644 index aaffeeb0cc..0000000000 --- a/drivers/net/npe/IxNpeDlNpeMgr.c +++ /dev/null @@ -1,931 +0,0 @@ -/** - * @file IxNpeDlNpeMgr.c - * - * @author Intel Corporation - * @date 09 January 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader NpeMgr module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeDl.h" -#include "IxNpeDlNpeMgr_p.h" -#include "IxNpeDlNpeMgrUtils_p.h" -#include "IxNpeDlNpeMgrEcRegisters_p.h" -#include "IxNpeDlMacros_p.h" -#include "IxFeatureCtrl.h" - -/* - * #defines and macros used in this file. - */ -#define IX_NPEDL_BYTES_PER_WORD 4 - -/* used to read download map from version in microcode image */ -#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000 -#define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001 -#define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002 -#define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F - -/* - * masks used to extract address info from State information context - * register addresses as read from microcode image - */ -#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F -#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0 - -/* LSB offset of Context Number field in State-Info Context Address */ -#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4 - -/* size (in words) of single State Information entry (ctxt reg address|data) */ -#define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2 - - - #define IX_NPEDL_RESET_NPE_PARITY 0x0800 - #define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF - #define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF - - -/* - * Typedefs whose scope is limited to this file. - */ - -typedef struct -{ - UINT32 type; - UINT32 offset; -} IxNpeDlNpeMgrDownloadMapBlockEntry; - -typedef union -{ - IxNpeDlNpeMgrDownloadMapBlockEntry block; - UINT32 eodmMarker; -} IxNpeDlNpeMgrDownloadMapEntry; - -typedef struct -{ - /* 1st entry in the download map (there may be more than one) */ - IxNpeDlNpeMgrDownloadMapEntry entry[1]; -} IxNpeDlNpeMgrDownloadMap; - - -/* used to access an instruction or data block in a microcode image */ -typedef struct -{ - UINT32 npeMemAddress; - UINT32 size; - UINT32 data[1]; -} IxNpeDlNpeMgrCodeBlock; - -/* used to access each Context Reg entry state-information block */ -typedef struct -{ - UINT32 addressInfo; - UINT32 value; -} IxNpeDlNpeMgrStateInfoCtxtRegEntry; - -/* used to access a state-information block in a microcode image */ -typedef struct -{ - UINT32 size; - IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1]; -} IxNpeDlNpeMgrStateInfoBlock; - -/* used to store some useful NPE information for easy access */ -typedef struct -{ - UINT32 baseAddress; - UINT32 insMemSize; - UINT32 dataMemSize; -} IxNpeDlNpeInfo; - -/* used to distinguish instruction and data memory operations */ -typedef enum -{ - IX_NPEDL_MEM_TYPE_INSTRUCTION = 0, - IX_NPEDL_MEM_TYPE_DATA -} IxNpeDlNpeMemType; - -/* used to hold a reset value for a particular ECS register */ -typedef struct -{ - UINT32 regAddr; - UINT32 regResetVal; -} IxNpeDlEcsRegResetValue; - -/* prototype of function to write either Instruction or Data memory */ -typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress, - UINT32 npeMemAddress, - UINT32 npeMemData, - BOOL verify); - -/* module statistics counters */ -typedef struct -{ - UINT32 instructionBlocksLoaded; - UINT32 dataBlocksLoaded; - UINT32 stateInfoBlocksLoaded; - UINT32 criticalNpeErrors; - UINT32 criticalMicrocodeErrors; - UINT32 npeStarts; - UINT32 npeStops; - UINT32 npeResets; -} IxNpeDlNpeMgrStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ -static IxNpeDlNpeInfo ixNpeDlNpeInfo[] = -{ - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEA, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA - }, - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEB, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB - }, - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEC, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC - } -}; - -/* contains Reset values for Context Store Registers */ -static UINT32 ixNpeDlCtxtRegResetValues[] = -{ - IX_NPEDL_CTXT_REG_RESET_STEVT, - IX_NPEDL_CTXT_REG_RESET_STARTPC, - IX_NPEDL_CTXT_REG_RESET_REGMAP, - IX_NPEDL_CTXT_REG_RESET_CINDEX, -}; - -/* contains Reset values for Context Store Registers */ -static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] = -{ - {IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET} -}; - -static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats; - -/* Set when NPE register memory has been mapped */ -static BOOL ixNpeDlMemInitialised = false; - - -/* - * static function prototypes. - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress, - IxNpeDlNpeMgrCodeBlock *codeBlockPtr, - BOOL verify, IxNpeDlNpeMemType npeMemType); -PRIVATE IX_STATUS -ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress, - IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr, - BOOL verify); -PRIVATE BOOL -ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset, - UINT32 expectedBitsSet); - -PRIVATE UINT32 -ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId); - -/* - * Function definition: ixNpeDlNpeMgrBaseAddressGet - */ -PRIVATE UINT32 -ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId) -{ - IX_OSAL_ASSERT (ixNpeDlMemInitialised); - return ixNpeDlNpeInfo[npeId].baseAddress; -} - - -/* - * Function definition: ixNpeDlNpeMgrInit - */ -void -ixNpeDlNpeMgrInit (void) -{ - /* Only map the memory once */ - if (!ixNpeDlMemInitialised) - { - UINT32 virtAddr; - - /* map the register memory for NPE-A */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA, - IX_OSAL_IXP400_NPEA_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr; - - /* map the register memory for NPE-B */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB, - IX_OSAL_IXP400_NPEB_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr; - - /* map the register memory for NPE-C */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC, - IX_OSAL_IXP400_NPEC_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr; - - ixNpeDlMemInitialised = true; - } -} - - -/* - * Function definition: ixNpeDlNpeMgrUninit - */ -IX_STATUS -ixNpeDlNpeMgrUninit (void) -{ - if (!ixNpeDlMemInitialised) - { - return IX_FAIL; - } - - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress); - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress); - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress); - - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0; - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0; - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0; - - ixNpeDlMemInitialised = false; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeDlNpeMgrImageLoad - */ -IX_STATUS -ixNpeDlNpeMgrImageLoad ( - IxNpeDlNpeId npeId, - UINT32 *imageCodePtr, - BOOL verify) -{ - UINT32 npeBaseAddress; - IxNpeDlNpeMgrDownloadMap *downloadMap; - UINT32 *blockPtr; - UINT32 mapIndex = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrImageLoad\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* check execution status of NPE to verify NPE Stop was successful */ - if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_STOP)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - " - "NPE was not stopped before download\n"); - status = IX_FAIL; - } - else - { - /* - * Read Download Map, checking each block type and calling - * appropriate function to perform download - */ - downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr; - while ((downloadMap->entry[mapIndex].eodmMarker != - IX_NPEDL_END_OF_DOWNLOAD_MAP) - && (status == IX_SUCCESS)) - { - /* calculate pointer to block to be downloaded */ - blockPtr = imageCodePtr + - downloadMap->entry[mapIndex].block.offset; - - switch (downloadMap->entry[mapIndex].block.type) - { - case IX_NPEDL_BLOCK_TYPE_INSTRUCTION: - status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress, - (IxNpeDlNpeMgrCodeBlock *)blockPtr, - verify, - IX_NPEDL_MEM_TYPE_INSTRUCTION); - break; - case IX_NPEDL_BLOCK_TYPE_DATA: - status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress, - (IxNpeDlNpeMgrCodeBlock *)blockPtr, - verify, IX_NPEDL_MEM_TYPE_DATA); - break; - case IX_NPEDL_BLOCK_TYPE_STATE: - status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress, - (IxNpeDlNpeMgrStateInfoBlock *) blockPtr, - verify); - break; - default: - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: " - "unknown block type in download map\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - break; - } - mapIndex++; - }/* loop: for each entry in download map, while status == SUCCESS */ - }/* condition: NPE stopped before attempting download */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrMemLoad - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrMemLoad ( - IxNpeDlNpeId npeId, - UINT32 npeBaseAddress, - IxNpeDlNpeMgrCodeBlock *blockPtr, - BOOL verify, - IxNpeDlNpeMemType npeMemType) -{ - UINT32 npeMemAddress; - UINT32 blockSize; - UINT32 memSize = 0; - IxNpeDlNpeMgrMemWrite memWriteFunc = NULL; - UINT32 localIndex = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrMemLoad\n"); - - /* - * select NPE EXCTL reg read/write commands depending on memory - * type (instruction/data) to be accessed - */ - if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION) - { - memSize = ixNpeDlNpeInfo[npeId].insMemSize; - memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite; - } - else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA) - { - memSize = ixNpeDlNpeInfo[npeId].dataMemSize; - memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite; - } - - /* - * NPE memory is loaded contiguously from each block, so only address - * of 1st word in block is needed - */ - npeMemAddress = blockPtr->npeMemAddress; - /* number of words of instruction/data microcode in block to download */ - blockSize = blockPtr->size; - if ((npeMemAddress + blockSize) > memSize) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: " - "Block size too big for NPE memory\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - } - else - { - for (localIndex = 0; localIndex < blockSize; localIndex++) - { - status = memWriteFunc (npeBaseAddress, npeMemAddress, - blockPtr->data[localIndex], verify); - - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: " - "write to NPE memory failed\n"); - status = IX_NPEDL_CRITICAL_NPE_ERR; - ixNpeDlNpeMgrStats.criticalNpeErrors++; - break; /* abort download */ - } - /* increment target (word)address in NPE memory */ - npeMemAddress++; - } - }/* condition: block size will fit in NPE memory */ - - if (status == IX_SUCCESS) - { - if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION) - { - ixNpeDlNpeMgrStats.instructionBlocksLoaded++; - } - else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA) - { - ixNpeDlNpeMgrStats.dataBlocksLoaded++; - } - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrStateInfoLoad - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrStateInfoLoad ( - UINT32 npeBaseAddress, - IxNpeDlNpeMgrStateInfoBlock *blockPtr, - BOOL verify) -{ - UINT32 blockSize; - UINT32 ctxtRegAddrInfo; - UINT32 ctxtRegVal; - IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ - UINT32 ctxtNum; /* identifies Context number (0-16) */ - UINT32 i; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrStateInfoLoad\n"); - - /* block size contains number of words of state-info in block */ - blockSize = blockPtr->size; - - ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress); - - /* for each state-info context register entry in block */ - for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++) - { - /* each state-info entry is 2 words (address, value) in length */ - ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo; - ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value; - - ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG); - ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >> - IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM; - - /* error-check Context Register No. and Context Number values */ - /* NOTE that there is no STEVT register for Context 0 */ - if ((ctxtReg < 0) || - (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) || - (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) || - ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT))) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: " - "invalid Context Register Address\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - break; /* abort download */ - } - - status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg, - ctxtRegVal, verify); - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: " - "write of state-info to NPE failed\n"); - status = IX_NPEDL_CRITICAL_NPE_ERR; - ixNpeDlNpeMgrStats.criticalNpeErrors++; - break; /* abort download */ - } - }/* loop: for each context reg entry in State Info block */ - - ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress); - - if (status == IX_SUCCESS) - { - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeReset - */ -IX_STATUS -ixNpeDlNpeMgrNpeReset ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ - UINT32 ctxtNum; /* identifies Context number (0-16) */ - UINT32 regAddr; - UINT32 regVal; - UINT32 localIndex; - UINT32 indexMax; - IX_STATUS status = IX_SUCCESS; - IxFeatureCtrlReg unitFuseReg; - UINT32 ixNpeConfigCtrlRegVal; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeReset\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* pre-store the NPE Config Control Register Value */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal); - - ixNpeConfigCtrlRegVal |= 0x3F000000; - - /* disable the parity interrupt */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK)); - - ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress); - - /* - * clear the FIFOs - */ - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_WFIFO, - IX_NPEDL_MASK_WFIFO_VALID)) - { - /* read from the Watch-point FIFO until empty */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO, - ®Val); - } - - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_STAT, - IX_NPEDL_MASK_STAT_OFNE)) - { - /* read from the outFIFO until empty */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO, - ®Val); - } - - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_STAT, - IX_NPEDL_MASK_STAT_IFNE)) - { - /* - * step execution of the NPE intruction to read inFIFO using - * the Debug Executing Context stack - */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, - IX_NPEDL_INSTR_RD_FIFO, 0, 0); - - if (IX_SUCCESS != status) - { - return status; - } - - } - - /* - * Reset the mailbox reg - */ - /* ...from XScale side */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST, - IX_NPEDL_REG_RESET_MBST); - /* ...from NPE side */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, - IX_NPEDL_INSTR_RESET_MBOX, 0, 0); - - if (IX_SUCCESS != status) - { - return status; - } - - /* - * Reset the physical registers in the NPE register file: - * Note: no need to save/restore REGMAP for Context 0 here - * since all Context Store regs are reset in subsequent code - */ - for (regAddr = 0; - (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL); - regAddr++) - { - /* for each physical register in the NPE reg file, write 0 : */ - status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr, - 0, true); - if (status != IX_SUCCESS) - { - return status; /* abort reset */ - } - } - - - /* - * Reset the context store: - */ - for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN; - ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++) - { - /* set each context's Context Store registers to reset values: */ - for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++) - { - /* NOTE that there is no STEVT register for Context 0 */ - if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT))) - { - regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; - status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, - ctxtReg, regVal, true); - if (status != IX_SUCCESS) - { - return status; /* abort reset */ - } - } - } - } - - ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress); - - /* write Reset values to Execution Context Stack registers */ - indexMax = sizeof (ixNpeDlEcsRegResetValues) / - sizeof (IxNpeDlEcsRegResetValue); - for (localIndex = 0; localIndex < indexMax; localIndex++) - { - regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr; - regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal); - } - - /* clear the profile counter */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT); - - /* clear registers EXCT, AP0, AP1, AP2 and AP3 */ - for (regAddr = IX_NPEDL_REG_OFFSET_EXCT; - regAddr <= IX_NPEDL_REG_OFFSET_AP3; - regAddr += IX_NPEDL_BYTES_PER_WORD) - { - IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0); - } - - /* Reset the Watch-count register */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0); - - /* - * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation - */ - - /* - * Call the feature control API to fused out and reset the NPE and its - * coprocessor - to reset internal states and remove parity error - */ - unitFuseReg = ixFeatureCtrlRead (); - unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId); - ixFeatureCtrlWrite (unitFuseReg); - - /* call the feature control API to un-fused and un-reset the NPE & COP */ - unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId)); - ixFeatureCtrlWrite (unitFuseReg); - - /* - * Call NpeMgr function to stop the NPE again after the Feature Control - * has unfused and Un-Reset the NPE and its associated Coprocessors - */ - status = ixNpeDlNpeMgrNpeStop (npeId); - - /* restore NPE configuration bus Control Register - Parity Settings */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, - (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK)); - - ixNpeDlNpeMgrStats.npeResets++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeStart - */ -IX_STATUS -ixNpeDlNpeMgrNpeStart ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - UINT32 ecsRegVal; - BOOL npeRunning; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeStart\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* - * ensure only Background Context Stack Level is Active by turning off - * the Active bit in each of the other Executing Context Stack levels - */ - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_PRI_1_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0, - ecsRegVal); - - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_PRI_2_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0, - ecsRegVal); - - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_DBG_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - ecsRegVal); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* start NPE execution by issuing command through EXCTL register on NPE */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START); - - /* - * check execution status of NPE to verify NPE Start operation was - * successful - */ - npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_RUN); - if (npeRunning) - { - ixNpeDlNpeMgrStats.npeStarts++; - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: " - "failed to start NPE execution\n"); - status = IX_FAIL; - } - - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeStop - */ -IX_STATUS -ixNpeDlNpeMgrNpeStop ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeStop\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* stop NPE execution by issuing command through EXCTL register on NPE */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP); - - /* verify that NPE Stop was successful */ - if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_STOP)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: " - "failed to stop NPE execution\n"); - status = IX_FAIL; - } - - ixNpeDlNpeMgrStats.npeStops++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrBitsSetCheck - */ -PRIVATE BOOL -ixNpeDlNpeMgrBitsSetCheck ( - UINT32 npeBaseAddress, - UINT32 regOffset, - UINT32 expectedBitsSet) -{ - UINT32 regVal; - IX_NPEDL_REG_READ (npeBaseAddress, regOffset, ®Val); - - return expectedBitsSet == (expectedBitsSet & regVal); -} - - -/* - * Function definition: ixNpeDlNpeMgrStatsShow - */ -void -ixNpeDlNpeMgrStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlNpeMgrStatsShow:\n" - "\tInstruction Blocks loaded: %u\n" - "\tData Blocks loaded: %u\n" - "\tState Information Blocks loaded: %u\n" - "\tCritical NPE errors: %u\n" - "\tCritical Microcode errors: %u\n", - ixNpeDlNpeMgrStats.instructionBlocksLoaded, - ixNpeDlNpeMgrStats.dataBlocksLoaded, - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded, - ixNpeDlNpeMgrStats.criticalNpeErrors, - ixNpeDlNpeMgrStats.criticalMicrocodeErrors, - 0); - - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\tSuccessful NPE Starts: %u\n" - "\tSuccessful NPE Stops: %u\n" - "\tSuccessful NPE Resets: %u\n\n", - ixNpeDlNpeMgrStats.npeStarts, - ixNpeDlNpeMgrStats.npeStops, - ixNpeDlNpeMgrStats.npeResets, - 0,0,0); - - ixNpeDlNpeMgrUtilsStatsShow (); -} - - -/* - * Function definition: ixNpeDlNpeMgrStatsReset - */ -void -ixNpeDlNpeMgrStatsReset (void) -{ - ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0; - ixNpeDlNpeMgrStats.dataBlocksLoaded = 0; - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0; - ixNpeDlNpeMgrStats.criticalNpeErrors = 0; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0; - ixNpeDlNpeMgrStats.npeStarts = 0; - ixNpeDlNpeMgrStats.npeStops = 0; - ixNpeDlNpeMgrStats.npeResets = 0; - - ixNpeDlNpeMgrUtilsStatsReset (); -} diff --git a/drivers/net/npe/IxNpeDlNpeMgrUtils.c b/drivers/net/npe/IxNpeDlNpeMgrUtils.c deleted file mode 100644 index 18cac50208..0000000000 --- a/drivers/net/npe/IxNpeDlNpeMgrUtils.c +++ /dev/null @@ -1,806 +0,0 @@ -/** - * @file IxNpeDlNpeMgrUtils.c - * - * @author Intel Corporation - * @date 18 February 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader NpeMgr Utils module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the system defined include files required. - */ -#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of - * retries before - * timeout - */ - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeDl.h" -#include "IxNpeDlNpeMgrUtils_p.h" -#include "IxNpeDlNpeMgrEcRegisters_p.h" -#include "IxNpeDlMacros_p.h" - -/* - * #defines and macros used in this file. - */ - -/* used to bit-mask a number of bytes */ -#define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF -#define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF -#define IX_NPEDL_MASK_FULL_WORD 0xFFFFFFFF - -#define IX_NPEDL_BYTES_PER_WORD 4 -#define IX_NPEDL_BYTES_PER_SHORT 2 - -#define IX_NPEDL_REG_SIZE_BYTE 8 -#define IX_NPEDL_REG_SIZE_SHORT 16 -#define IX_NPEDL_REG_SIZE_WORD 32 - -/* - * Introduce extra read cycles after issuing read command to NPE - * so that we read the register after the NPE has updated it - * This is to overcome race condition between XScale and NPE - */ -#define IX_NPEDL_DELAY_READ_CYCLES 2 -/* - * To mask top three MSBs of 32bit word to download into NPE IMEM - */ -#define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF; - - -/* - * typedefs - */ -typedef struct -{ - UINT32 regAddress; - UINT32 regSize; -} IxNpeDlCtxtRegAccessInfo; - -/* module statistics counters */ -typedef struct -{ - UINT32 insMemWrites; - UINT32 insMemWriteFails; - UINT32 dataMemWrites; - UINT32 dataMemWriteFails; - UINT32 ecsRegWrites; - UINT32 ecsRegReads; - UINT32 dbgInstructionExecs; - UINT32 contextRegWrites; - UINT32 physicalRegWrites; - UINT32 nextPcWrites; -} IxNpeDlNpeMgrUtilsStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * contains useful address and function pointers to read/write Context Regs, - * eliminating some switch or if-else statements in places - */ -static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] = -{ - { - IX_NPEDL_CTXT_REG_ADDR_STEVT, - IX_NPEDL_REG_SIZE_BYTE - }, - { - IX_NPEDL_CTXT_REG_ADDR_STARTPC, - IX_NPEDL_REG_SIZE_SHORT - }, - { - IX_NPEDL_CTXT_REG_ADDR_REGMAP, - IX_NPEDL_REG_SIZE_SHORT - }, - { - IX_NPEDL_CTXT_REG_ADDR_CINDEX, - IX_NPEDL_REG_SIZE_BYTE - } -}; - -static UINT32 ixNpeDlSavedExecCount = 0; -static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0; - -static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats; - - -/* - * static function prototypes. - */ -PRIVATE __inline__ void -ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, - UINT32 addr, UINT32 data); - -PRIVATE __inline__ UINT32 -ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr); - -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr, - UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal); - -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr, - UINT32 regVal, UINT32 regSize, - UINT32 ctxtNum, BOOL verify); - -/* - * Function definition: ixNpeDlNpeMgrWriteCommandIssue - */ -PRIVATE __inline__ void -ixNpeDlNpeMgrWriteCommandIssue ( - UINT32 npeBaseAddress, - UINT32 cmd, - UINT32 addr, - UINT32 data) -{ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd); -} - - -/* - * Function definition: ixNpeDlNpeMgrReadCommandIssue - */ -PRIVATE __inline__ UINT32 -ixNpeDlNpeMgrReadCommandIssue ( - UINT32 npeBaseAddress, - UINT32 cmd, - UINT32 addr) -{ - UINT32 data = 0; - int i; - - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd); - for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++) - { - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data); - } - - return data; -} - -/* - * Function definition: ixNpeDlNpeMgrInsMemWrite - */ -IX_STATUS -ixNpeDlNpeMgrInsMemWrite ( - UINT32 npeBaseAddress, - UINT32 insMemAddress, - UINT32 insMemData, - BOOL verify) -{ - UINT32 insMemDataRtn; - - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_INS_MEM, - insMemAddress, insMemData); - if (verify) - { - /* write invalid data to this reg, so we can see if we're reading - the EXDATA register too early */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, - ~insMemData); - - /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/ - insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS; - - insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_INS_MEM, - insMemAddress); - - insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS; - - if (insMemData != insMemDataRtn) - { - ixNpeDlNpeMgrUtilsStats.insMemWriteFails++; - return IX_FAIL; - } - } - - ixNpeDlNpeMgrUtilsStats.insMemWrites++; - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrDataMemWrite - */ -IX_STATUS -ixNpeDlNpeMgrDataMemWrite ( - UINT32 npeBaseAddress, - UINT32 dataMemAddress, - UINT32 dataMemData, - BOOL verify) -{ - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_DATA_MEM, - dataMemAddress, dataMemData); - if (verify) - { - /* write invalid data to this reg, so we can see if we're reading - the EXDATA register too early */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData); - - if (dataMemData != - ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_DATA_MEM, - dataMemAddress)) - { - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++; - return IX_FAIL; - } - } - - ixNpeDlNpeMgrUtilsStats.dataMemWrites++; - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrExecAccRegWrite - */ -void -ixNpeDlNpeMgrExecAccRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddress, - UINT32 regData) -{ - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_ECS_REG, - regAddress, regData); - ixNpeDlNpeMgrUtilsStats.ecsRegWrites++; -} - - -/* - * Function definition: ixNpeDlNpeMgrExecAccRegRead - */ -UINT32 -ixNpeDlNpeMgrExecAccRegRead ( - UINT32 npeBaseAddress, - UINT32 regAddress) -{ - ixNpeDlNpeMgrUtilsStats.ecsRegReads++; - return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_ECS_REG, - regAddress); -} - - -/* - * Function definition: ixNpeDlNpeMgrCommandIssue - */ -void -ixNpeDlNpeMgrCommandIssue ( - UINT32 npeBaseAddress, - UINT32 command) -{ - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrCommandIssue\n"); - - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command); - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrCommandIssue\n"); -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec - */ -void -ixNpeDlNpeMgrDebugInstructionPreExec( - UINT32 npeBaseAddress) -{ - /* turn off the halt bit by clearing Execution Count register. */ - /* save reg contents 1st and restore later */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, - &ixNpeDlSavedExecCount); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0); - - /* ensure that IF and IE are on (temporarily), so that we don't end up - * stepping forever */ - ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_DBG_CTXT_REG_2); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2, - (ixNpeDlSavedEcsDbgCtxtReg2 | - IX_NPEDL_MASK_ECS_DBG_REG_2_IF | - IX_NPEDL_MASK_ECS_DBG_REG_2_IE)); -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionExec - */ -IX_STATUS -ixNpeDlNpeMgrDebugInstructionExec( - UINT32 npeBaseAddress, - UINT32 npeInstruction, - UINT32 ctxtNum, - UINT32 ldur) -{ - UINT32 ecsDbgRegVal; - UINT32 oldWatchcount, newWatchcount; - UINT32 retriesCount = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrDebugInstructionExec\n"); - - /* set the Active bit, and the LDUR, in the debug level */ - ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE | - (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - ecsDbgRegVal); - - /* - * set CCTXT at ECS DEBUG L3 to specify in which context to execute the - * instruction, and set SELCTXT at ECS DEBUG Level to specify which context - * store to access. - * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number - */ - ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) | - (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1, - ecsDbgRegVal); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* load NPE instruction into the instruction register */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG, - npeInstruction); - - /* we need this value later to wait for completion of NPE execution step */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount); - - /* issue a Step One command via the Execution Control register */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP); - - /* Watch Count register increments when NPE completes an instruction */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, - &newWatchcount); - - /* - * force the XScale to wait until the NPE has finished execution step - * NOTE that this delay will be very small, just long enough to allow a - * single NPE instruction to complete execution; if instruction execution - * is not completed before timeout retries, exit the while loop - */ - while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount) - && (newWatchcount == oldWatchcount)) - { - /* Watch Count register increments when NPE completes an instruction */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, - &newWatchcount); - - retriesCount++; - } - - if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount) - { - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++; - } - else - { - /* Return timeout status as the instruction has not been executed - * after maximum retries */ - status = IX_NPEDL_CRITICAL_NPE_ERR; - } - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrDebugInstructionExec\n"); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec - */ -void -ixNpeDlNpeMgrDebugInstructionPostExec( - UINT32 npeBaseAddress) -{ - /* clear active bit in debug level */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - 0); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* restore Execution Count register contents. */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, - ixNpeDlSavedExecCount); - - /* restore IF and IE bits to original values */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2, - ixNpeDlSavedEcsDbgCtxtReg2); -} - - -/* - * Function definition: ixNpeDlNpeMgrLogicalRegRead - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegRead ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regSize, - UINT32 ctxtNum, - UINT32 *regVal) -{ - IX_STATUS status = IX_SUCCESS; - UINT32 npeInstruction = 0; - UINT32 mask = 0; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrLogicalRegRead\n"); - - switch (regSize) - { - case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE; - mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break; - case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT; - mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break; - case IX_NPEDL_REG_SIZE_WORD: - npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD; - mask = IX_NPEDL_MASK_FULL_WORD; break; - } - - /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */ - npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) | - (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - - /* step execution of NPE intruction using Debug Executing Context stack */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction, - ctxtNum, IX_NPEDL_RD_INSTR_LDUR); - - if (IX_SUCCESS != status) - { - return status; - } - - /* read value of register from Execution Data register */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, regVal); - - /* align value from left to right */ - *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrLogicalRegRead\n"); - - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrLogicalRegWrite - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regVal, - UINT32 regSize, - UINT32 ctxtNum, - BOOL verify) -{ - UINT32 npeInstruction = 0; - UINT32 mask = 0; - IX_STATUS status = IX_SUCCESS; - UINT32 retRegVal; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrLogicalRegWrite\n"); - - if (regSize == IX_NPEDL_REG_SIZE_WORD) - { - /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */ - /* Write upper half-word (short) to |d0|d1| */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, - regVal >> IX_NPEDL_REG_SIZE_SHORT, - IX_NPEDL_REG_SIZE_SHORT, - ctxtNum, verify); - - if (IX_SUCCESS != status) - { - return status; - } - - /* Write lower half-word (short) to |d2|d3| */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, - regAddr + IX_NPEDL_BYTES_PER_SHORT, - regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD, - IX_NPEDL_REG_SIZE_SHORT, - ctxtNum, verify); - - if (IX_SUCCESS != status) - { - return status; - } - } - else - { - switch (regSize) - { - case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE; - mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break; - case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT; - mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break; - } - /* mask out any redundant bits, so verify will work later */ - regVal &= mask; - - /* fill dest operand field of instruction with destination reg addr */ - npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - - /* fill src operand field of instruction with least-sig 5 bits of val*/ - npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) << - IX_NPEDL_OFFSET_INSTR_SRC); - - /* fill coprocessor field of instruction with most-sig 11 bits of val*/ - npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) << - IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA); - - /* step execution of NPE intruction using Debug ECS */ - status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction, - ctxtNum, IX_NPEDL_WR_INSTR_LDUR); - - if (IX_SUCCESS != status) - { - return status; - } - }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */ - - if (verify) - { - status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr, - regSize, ctxtNum, &retRegVal); - - if (IX_SUCCESS == status) - { - if (regVal != retRegVal) - { - status = IX_FAIL; - } - } - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n", - status); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrPhysicalRegWrite - */ -IX_STATUS -ixNpeDlNpeMgrPhysicalRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regValue, - BOOL verify) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrPhysicalRegWrite\n"); - -/* - * There are 32 physical registers used in an NPE. These are - * treated as 16 pairs of 32-bit registers. To write one of the pair, - * write the pair number (0-16) to the REGMAP for Context 0. Then write - * the value to register 0 or 4 in the regfile, depending on which - * register of the pair is to be written - */ - - /* - * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16) - * of physical registers to write - */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, - IX_NPEDL_CTXT_REG_ADDR_REGMAP, - (regAddr >> - IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP), - IX_NPEDL_REG_SIZE_SHORT, 0, verify); - if (status == IX_SUCCESS) - { - /* regAddr = 0 or 4 */ - regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) * - IX_NPEDL_BYTES_PER_WORD; - - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue, - IX_NPEDL_REG_SIZE_WORD, 0, verify); - } - - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: " - "error writing to physical register\n"); - } - - ixNpeDlNpeMgrUtilsStats.physicalRegWrites++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrCtxtRegWrite - */ -IX_STATUS -ixNpeDlNpeMgrCtxtRegWrite ( - UINT32 npeBaseAddress, - UINT32 ctxtNum, - IxNpeDlCtxtRegNum ctxtReg, - UINT32 ctxtRegVal, - BOOL verify) -{ - UINT32 tempRegVal; - UINT32 ctxtRegAddr; - UINT32 ctxtRegSize; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrCtxtRegWrite\n"); - - /* - * Context 0 has no STARTPC. Instead, this value is used to set - * NextPC for Background ECS, to set where NPE starts executing code - */ - if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC)) - { - /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */ - tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_BG_CTXT_REG_0); - tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC; - tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) & - IX_NPEDL_MASK_ECS_REG_0_NEXTPC; - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, - IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal); - - ixNpeDlNpeMgrUtilsStats.nextPcWrites++; - } - else - { - ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress; - ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize; - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr, - ctxtRegVal, ctxtRegSize, - ctxtNum, verify); - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: " - "error writing to context store register\n"); - } - - ixNpeDlNpeMgrUtilsStats.contextRegWrites++; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n", - status); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrUtilsStatsShow - */ -void -ixNpeDlNpeMgrUtilsStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlNpeMgrUtilsStatsShow:\n" - "\tInstruction Memory writes: %u\n" - "\tInstruction Memory writes failed: %u\n" - "\tData Memory writes: %u\n" - "\tData Memory writes failed: %u\n", - ixNpeDlNpeMgrUtilsStats.insMemWrites, - ixNpeDlNpeMgrUtilsStats.insMemWriteFails, - ixNpeDlNpeMgrUtilsStats.dataMemWrites, - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails, - 0,0); - - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\tExecuting Context Stack Register writes: %u\n" - "\tExecuting Context Stack Register reads: %u\n" - "\tPhysical Register writes: %u\n" - "\tContext Store Register writes: %u\n" - "\tExecution Backgound Context NextPC writes: %u\n" - "\tDebug Instructions Executed: %u\n\n", - ixNpeDlNpeMgrUtilsStats.ecsRegWrites, - ixNpeDlNpeMgrUtilsStats.ecsRegReads, - ixNpeDlNpeMgrUtilsStats.physicalRegWrites, - ixNpeDlNpeMgrUtilsStats.contextRegWrites, - ixNpeDlNpeMgrUtilsStats.nextPcWrites, - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs); -} - - -/* - * Function definition: ixNpeDlNpeMgrUtilsStatsReset - */ -void -ixNpeDlNpeMgrUtilsStatsReset (void) -{ - ixNpeDlNpeMgrUtilsStats.insMemWrites = 0; - ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0; - ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0; - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0; - ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0; - ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0; - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0; -} diff --git a/drivers/net/npe/IxNpeMh.c b/drivers/net/npe/IxNpeMh.c deleted file mode 100644 index 2870ff7da5..0000000000 --- a/drivers/net/npe/IxNpeMh.c +++ /dev/null @@ -1,582 +0,0 @@ -/** - * @file IxNpeMh.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the public API for the - * IXP425 NPE Message Handler component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMh.h" - -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhReceive_p.h" -#include "IxNpeMhSend_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhUnsolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE BOOL ixNpeMhInitialized = false; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhInitialize - */ - -PUBLIC IX_STATUS ixNpeMhInitialize ( - IxNpeMhNpeInterrupts npeInterrupts) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhInitialize\n"); - - /* check the npeInterrupts parameter */ - if ((npeInterrupts != IX_NPEMH_NPEINTERRUPTS_NO) && - (npeInterrupts != IX_NPEMH_NPEINTERRUPTS_YES)) - { - IX_NPEMH_ERROR_REPORT ("Illegal npeInterrupts parameter value\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* initialize the Receive module */ - ixNpeMhReceiveInitialize (); - - /* initialize the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrInitialize (); - - /* initialize the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrInitialize (); - - /* initialize the Configuration module - * - * NOTE: This module was originally configured before the - * others, but the sequence was changed so that interrupts - * would only be enabled after the handler functions were - * set up. The above modules need to be initialised to - * handle the NPE interrupts. See SCR #2231. - */ - ixNpeMhConfigInitialize (npeInterrupts); - - ixNpeMhInitialized = true; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhInitialize\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhUnload - */ - -PUBLIC IX_STATUS ixNpeMhUnload (void) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnload\n"); - - if (!ixNpeMhInitialized) - { - return IX_FAIL; - } - - /* Uninitialize the Configuration module */ - ixNpeMhConfigUninit (); - - ixNpeMhInitialized = false; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnload\n"); - - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeMhUnsolicitedCallbackRegister - */ - -PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId messageId, - IxNpeMhCallback unsolicitedCallback) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCallbackRegister\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the messageId parameter */ - if ((messageId < IX_NPEMH_MIN_MESSAGE_ID) - || (messageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Message ID is out of range\n"); - return IX_FAIL; - } - - /* the unsolicitedCallback parameter is allowed to be NULL */ - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* save the unsolicited callback for the message ID */ - ixNpeMhUnsolicitedCbMgrCallbackSave ( - npeId, messageId, unsolicitedCallback); - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCallbackRegister\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhUnsolicitedCallbackForRangeRegister - */ - -PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId minMessageId, - IxNpeMhMessageId maxMessageId, - IxNpeMhCallback unsolicitedCallback) -{ - IxNpeMhMessageId messageId; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCallbackForRangeRegister\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the minMessageId parameter */ - if ((minMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (minMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Min message ID is out of range\n"); - return IX_FAIL; - } - - /* check the maxMessageId parameter */ - if ((maxMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (maxMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Max message ID is out of range\n"); - return IX_FAIL; - } - - /* check the semantics of the message range parameters */ - if (minMessageId > maxMessageId) - { - IX_NPEMH_ERROR_REPORT ("Min message ID greater than max message " - "ID\n"); - return IX_FAIL; - } - - /* the unsolicitedCallback parameter is allowed to be NULL */ - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* for each message ID in the range ... */ - for (messageId = minMessageId; messageId <= maxMessageId; messageId++) - { - /* save the unsolicited callback for the message ID */ - ixNpeMhUnsolicitedCbMgrCallbackSave ( - npeId, messageId, unsolicitedCallback); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCallbackForRangeRegister\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhMessageSend - */ - -PUBLIC IX_STATUS ixNpeMhMessageSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessageSend\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* send the message */ - status = ixNpeMhSendMessageSend (npeId, message, maxSendRetries); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to send message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessageSend" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhMessageWithResponseSend - */ - -PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - IxNpeMhCallback unsolicitedCallback = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessageWithResponseSend\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* the solicitecCallback parameter is allowed to be NULL. this */ - /* signifies the client is not interested in the response message */ - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the solicitedMessageId parameter */ - if ((solicitedMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (solicitedMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Solicited message ID is out of range\n"); - return IX_FAIL; - } - - /* check the solicitedMessageId parameter. if an unsolicited */ - /* callback has been registered for the specified message ID then */ - /* report an error and return failure */ - ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - npeId, solicitedMessageId, &unsolicitedCallback); - if (unsolicitedCallback != NULL) - { - IX_NPEMH_ERROR_REPORT ("Solicited message ID conflicts with " - "unsolicited message ID\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* send the message */ - status = ixNpeMhSendMessageWithResponseSend ( - npeId, message, solicitedMessageId, solicitedCallback, - maxSendRetries); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to send message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessageWithResponseSend" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhMessagesReceive - */ - -PUBLIC IX_STATUS ixNpeMhMessagesReceive ( - IxNpeMhNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessagesReceive\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* receive messages from the NPE */ - status = ixNpeMhReceiveMessagesReceive (npeId); - - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to receive message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessagesReceive" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhShow - */ - -PUBLIC IX_STATUS ixNpeMhShow ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhShow\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* note we don't get the lock here as printing the statistics */ - /* to a console may take some time and we don't want to impact */ - /* system performance. this means that the statistics displayed */ - /* may be in a state of flux and make not represent a consistent */ - /* snapshot. */ - - /* display a header */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "Current state of NPE ID %d:\n\n", npeId, 0, 0, 0, 0, 0); - - /* show the current state of each module */ - - /* show the current state of the Configuration module */ - ixNpeMhConfigShow (npeId); - - /* show the current state of the Receive module */ - ixNpeMhReceiveShow (npeId); - - /* show the current state of the Send module */ - ixNpeMhSendShow (npeId); - - /* show the current state of the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrShow (npeId); - - /* show the current state of the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrShow (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhShow\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhShowReset - */ - -PUBLIC IX_STATUS ixNpeMhShowReset ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhShowReset\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* note we don't get the lock here as resetting the statistics */ - /* shouldn't impact system performance. */ - - /* reset the current state of each module */ - - /* reset the current state of the Configuration module */ - ixNpeMhConfigShowReset (npeId); - - /* reset the current state of the Receive module */ - ixNpeMhReceiveShowReset (npeId); - - /* reset the current state of the Send module */ - ixNpeMhSendShowReset (npeId); - - /* reset the current state of the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrShowReset (npeId); - - /* reset the current state of the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrShowReset (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhShowReset\n"); - - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxNpeMhConfig.c b/drivers/net/npe/IxNpeMhConfig.c deleted file mode 100644 index 092d480c65..0000000000 --- a/drivers/net/npe/IxNpeMhConfig.c +++ /dev/null @@ -1,608 +0,0 @@ -/** - * @file IxNpeMhConfig.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Configuration module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhConfig_p.h" - -/* - * #defines and macros used in this file. - */ -#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of - * retries before - * timeout - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhConfigStats - * - * @brief This structure is used to maintain statistics for the - * Configuration module. - */ - -typedef struct -{ - UINT32 outFifoReads; /**< outFifo reads */ - UINT32 inFifoWrites; /**< inFifo writes */ - UINT32 maxInFifoFullRetries; /**< max retries if inFIFO full */ - UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */ -} IxNpeMhConfigStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = -{ - { - 0, - IX_NPEMH_NPEA_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - }, - { - 0, - IX_NPEMH_NPEB_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - }, - { - 0, - IX_NPEMH_NPEC_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - } -}; - -PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -void ixNpeMhConfigIsr (void *parameter); - -/* - * Function definition: ixNpeMhConfigIsr - */ - -PRIVATE -void ixNpeMhConfigIsr (void *parameter) -{ - IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter; - UINT32 ofint; - volatile UINT32 *statusReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigIsr\n"); - - /* get the OFINT (OutFifo interrupt) bit of the status register */ - IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT); - - /* if the OFINT status bit is set */ - if (ofint) - { - /* if there is an ISR registered for this NPE */ - if (ixNpeMhConfigNpeInfo[npeId].isr != NULL) - { - /* invoke the ISR routine */ - ixNpeMhConfigNpeInfo[npeId].isr (npeId); - } - else - { - /* if we don't service the interrupt the NPE will continue */ - /* to trigger the interrupt indefinitely */ - IX_NPEMH_ERROR_REPORT ("No ISR registered to service " - "interrupt\n"); - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigIsr\n"); -} - -/* - * Function definition: ixNpeMhConfigInitialize - */ - -void ixNpeMhConfigInitialize ( - IxNpeMhNpeInterrupts npeInterrupts) -{ - IxNpeMhNpeId npeId; - UINT32 virtualAddr[IX_NPEMH_NUM_NPES]; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigInitialize\n"); - - /* Request a mapping for the NPE-A config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEA] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE, - IX_OSAL_IXP400_NPEA_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]); - - /* Request a mapping for the NPE-B config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEB] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE, - IX_OSAL_IXP400_NPEB_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]); - - /* Request a mapping for the NPE-C config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEC] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE, - IX_OSAL_IXP400_NPEC_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* declare a convenience pointer */ - IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId]; - - /* store the virtual addresses of the NPE registers for later use */ - npeInfo->virtualRegisterBase = virtualAddr[npeId]; - npeInfo->statusRegister = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET; - npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET; - npeInfo->inFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET; - npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET; - - /* for test purposes - to verify the register addresses */ - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register = " - "0x%08X\n", npeId, npeInfo->statusRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = " - "0x%08X\n", npeId, npeInfo->controlRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register = " - "0x%08X\n", npeId, npeInfo->inFifoRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = " - "0x%08X\n", npeId, npeInfo->outFifoRegister); - - /* connect our ISR to the NPE interrupt */ - (void) ixOsalIrqBind ( - npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId); - - /* initialise a mutex for this NPE */ - (void) ixOsalMutexInit (&npeInfo->mutex); - - /* if we should service the NPE's "outFIFO not empty" interrupt */ - if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES) - { - /* enable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInterruptEnable (npeId); - } - else - { - /* disable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInterruptDisable (npeId); - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigInitialize\n"); -} - -/* - * Function definition: ixNpeMhConfigUninit - */ - -void ixNpeMhConfigUninit (void) -{ - IxNpeMhNpeId npeId; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigUninit\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* declare a convenience pointer */ - IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId]; - - /* disconnect ISR */ - ixOsalIrqUnbind(npeInfo->interruptId); - - /* destroy mutex associated with this NPE */ - ixOsalMutexDestroy(&npeInfo->mutex); - - IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase); - - npeInfo->virtualRegisterBase = 0; - npeInfo->statusRegister = 0; - npeInfo->controlRegister = 0; - npeInfo->inFifoRegister = 0; - npeInfo->outFifoRegister = 0; - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigUninit\n"); -} - -/* - * Function definition: ixNpeMhConfigIsrRegister - */ - -void ixNpeMhConfigIsrRegister ( - IxNpeMhNpeId npeId, - IxNpeMhConfigIsr isr) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigIsrRegister\n"); - - /* check if there is already an ISR registered for this NPE */ - if (ixNpeMhConfigNpeInfo[npeId].isr != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n"); - } - - /* save the ISR routine with the NPE info */ - ixNpeMhConfigNpeInfo[npeId].isr = isr; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigIsrRegister\n"); -} - -/* - * Function definition: ixNpeMhConfigNpeInterruptEnable - */ - -BOOL ixNpeMhConfigNpeInterruptEnable ( - IxNpeMhNpeId npeId) -{ - UINT32 ofe; - volatile UINT32 *controlReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister; - - /* get the OFE (OutFifoEnable) bit of the control register */ - IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE); - - /* if the interrupt is disabled then we must enable it */ - if (!ofe) - { - /* set the OFE (OutFifoEnable) bit of the control register */ - /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ - /* time for the write to have effect */ - IX_NPEMH_REGISTER_WRITE_BITS (controlReg, - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE), - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE)); - } - - /* return the previous state of the interrupt */ - return (ofe != 0); -} - -/* - * Function definition: ixNpeMhConfigNpeInterruptDisable - */ - -BOOL ixNpeMhConfigNpeInterruptDisable ( - IxNpeMhNpeId npeId) -{ - UINT32 ofe; - volatile UINT32 *controlReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister; - - /* get the OFE (OutFifoEnable) bit of the control register */ - IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE); - - /* if the interrupt is enabled then we must disable it */ - if (ofe) - { - /* unset the OFE (OutFifoEnable) bit of the control register */ - /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ - /* time for the write to have effect */ - IX_NPEMH_REGISTER_WRITE_BITS (controlReg, - (0 | - IX_NPEMH_NPE_CTL_OFEWE), - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE)); - } - - /* return the previous state of the interrupt */ - return (ofe != 0); -} - -/* - * Function definition: ixNpeMhConfigMessageIdGet - */ - -IxNpeMhMessageId ixNpeMhConfigMessageIdGet ( - IxNpeMhMessage message) -{ - /* return the most-significant byte of the first word of the */ - /* message */ - return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF)); -} - -/* - * Function definition: ixNpeMhConfigNpeIdIsValid - */ - -BOOL ixNpeMhConfigNpeIdIsValid ( - IxNpeMhNpeId npeId) -{ - /* check that the npeId parameter is within the range of valid IDs */ - return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES); -} - -/* - * Function definition: ixNpeMhConfigLockGet - */ - -void ixNpeMhConfigLockGet ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigLockGet\n"); - - /* lock the mutex for this NPE */ - (void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex, - IX_OSAL_WAIT_FOREVER); - - /* disable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInfo[npeId].oldInterruptState = - ixNpeMhConfigNpeInterruptDisable (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigLockGet\n"); -} - -/* - * Function definition: ixNpeMhConfigLockRelease - */ - -void ixNpeMhConfigLockRelease ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigLockRelease\n"); - - /* if the interrupt was previously enabled */ - if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState) - { - /* enable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInfo[npeId].oldInterruptState = - ixNpeMhConfigNpeInterruptEnable (npeId); - } - - /* unlock the mutex for this NPE */ - (void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigLockRelease\n"); -} - -/* - * Function definition: ixNpeMhConfigInFifoWrite - */ - -IX_STATUS ixNpeMhConfigInFifoWrite ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message) -{ - volatile UINT32 *npeInFifo = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister; - UINT32 retriesCount = 0; - - /* write the first word of the message to the NPE's inFIFO */ - IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]); - - /* need to wait for room to write second word - see SCR #493, - poll for maximum number of retries, if exceed maximum - retries, exit from while loop */ - while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount) - && ixNpeMhConfigInFifoIsFull (npeId)) - { - retriesCount++; - } - - /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */ - if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount) - { - return IX_NPEMH_CRITICAL_NPE_ERR; - } - - /* write the second word of the message to the NPE's inFIFO */ - IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]); - - /* record in the stats the maximum number of retries needed */ - if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount) - { - ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount; - } - - /* update statistical info */ - ixNpeMhConfigStats[npeId].inFifoWrites++; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhConfigOutFifoRead - */ - -IX_STATUS ixNpeMhConfigOutFifoRead ( - IxNpeMhNpeId npeId, - IxNpeMhMessage *message) -{ - volatile UINT32 *npeOutFifo = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister; - UINT32 retriesCount = 0; - - /* read the first word of the message from the NPE's outFIFO */ - IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]); - - /* need to wait for NPE to write second word - see SCR #493 - poll for maximum number of retries, if exceed maximum - retries, exit from while loop */ - while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount) - && ixNpeMhConfigOutFifoIsEmpty (npeId)) - { - retriesCount++; - } - - /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */ - if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount) - { - return IX_NPEMH_CRITICAL_NPE_ERR; - } - - /* read the second word of the message from the NPE's outFIFO */ - IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]); - - /* record in the stats the maximum number of retries needed */ - if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount) - { - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount; - } - - /* update statistical info */ - ixNpeMhConfigStats[npeId].outFifoReads++; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhConfigShow - */ - -void ixNpeMhConfigShow ( - IxNpeMhNpeId npeId) -{ - /* show the message fifo read counter */ - IX_NPEMH_SHOW ("Message FIFO reads", - ixNpeMhConfigStats[npeId].outFifoReads); - - /* show the message fifo write counter */ - IX_NPEMH_SHOW ("Message FIFO writes", - ixNpeMhConfigStats[npeId].inFifoWrites); - - /* show the max retries performed when inFIFO full */ - IX_NPEMH_SHOW ("Max inFIFO Full retries", - ixNpeMhConfigStats[npeId].maxInFifoFullRetries); - - /* show the max retries performed when outFIFO empty */ - IX_NPEMH_SHOW ("Max outFIFO Empty retries", - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries); - - /* show the current status of the inFifo */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "InFifo is %s and %s\n", - (ixNpeMhConfigInFifoIsEmpty (npeId) ? - (int) "EMPTY" : (int) "NOT EMPTY"), - (ixNpeMhConfigInFifoIsFull (npeId) ? - (int) "FULL" : (int) "NOT FULL"), - 0, 0, 0, 0); - - /* show the current status of the outFifo */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "OutFifo is %s and %s\n", - (ixNpeMhConfigOutFifoIsEmpty (npeId) ? - (int) "EMPTY" : (int) "NOT EMPTY"), - (ixNpeMhConfigOutFifoIsFull (npeId) ? - (int) "FULL" : (int) "NOT FULL"), - 0, 0, 0, 0); -} - -/* - * Function definition: ixNpeMhConfigShowReset - */ - -void ixNpeMhConfigShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the message fifo read counter */ - ixNpeMhConfigStats[npeId].outFifoReads = 0; - - /* reset the message fifo write counter */ - ixNpeMhConfigStats[npeId].inFifoWrites = 0; - - /* reset the max inFIFO Full retries counter */ - ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0; - - /* reset the max outFIFO empty retries counter */ - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0; -} - - diff --git a/drivers/net/npe/IxNpeMhReceive.c b/drivers/net/npe/IxNpeMhReceive.c deleted file mode 100644 index 57c8be30e5..0000000000 --- a/drivers/net/npe/IxNpeMhReceive.c +++ /dev/null @@ -1,320 +0,0 @@ -/** - * @file IxNpeMhReceive.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Receive module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeMhMacros_p.h" -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhReceive_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhUnsolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhReceiveStats - * - * @brief This structure is used to maintain statistics for the Receive - * module. - */ - -typedef struct -{ - UINT32 isrs; /**< receive ISR invocations */ - UINT32 receives; /**< receive messages invocations */ - UINT32 messages; /**< messages received */ - UINT32 solicited; /**< solicited messages received */ - UINT32 unsolicited; /**< unsolicited messages received */ - UINT32 callbacks; /**< callbacks invoked */ -} IxNpeMhReceiveStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhReceiveStats ixNpeMhReceiveStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -void ixNpeMhReceiveIsr (int npeId); - -PRIVATE -void ixNpeMhReceiveIsr (int npeId) -{ - int lockKey; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveIsr\n"); - - lockKey = ixOsalIrqLock (); - - /* invoke the message receive routine to get messages from the NPE */ - ixNpeMhReceiveMessagesReceive (npeId); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].isrs++; - - ixOsalIrqUnlock (lockKey); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveIsr\n"); -} - -/* - * Function definition: ixNpeMhReceiveInitialize - */ - -void ixNpeMhReceiveInitialize (void) -{ - IxNpeMhNpeId npeId = 0; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* register our internal ISR for the NPE to handle "outFIFO not */ - /* empty" interrupts */ - ixNpeMhConfigIsrRegister (npeId, ixNpeMhReceiveIsr); - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveInitialize\n"); -} - -/* - * Function definition: ixNpeMhReceiveMessagesReceive - */ - -IX_STATUS ixNpeMhReceiveMessagesReceive ( - IxNpeMhNpeId npeId) -{ - IxNpeMhMessage message = { { 0, 0 } }; - IxNpeMhMessageId messageId = 0; - IxNpeMhCallback callback = NULL; - IX_STATUS status; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveMessagesReceive\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].receives++; - - /* while the NPE has messages in its outFIFO */ - while (!ixNpeMhConfigOutFifoIsEmpty (npeId)) - { - /* read a message from the NPE's outFIFO */ - status = ixNpeMhConfigOutFifoRead (npeId, &message); - - if (IX_SUCCESS != status) - { - return status; - } - - /* get the ID of the message */ - messageId = ixNpeMhConfigMessageIdGet (message); - - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, - "Received message from NPE %d with ID 0x%02X\n", - npeId, messageId); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].messages++; - - /* try to find a matching unsolicited callback for this message. */ - - /* we assume the message is unsolicited. only if there is no */ - /* unsolicited callback for this message type do we assume the */ - /* message is solicited. it is much faster to check for an */ - /* unsolicited callback, so doing this check first should result */ - /* in better performance. */ - - ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - npeId, messageId, &callback); - - if (callback != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, - "Found matching unsolicited callback\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].unsolicited++; - } - - /* if no unsolicited callback was found try to find a matching */ - /* solicited callback for this message */ - if (callback == NULL) - { - ixNpeMhSolicitedCbMgrCallbackRetrieve ( - npeId, messageId, &callback); - - if (callback != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, - "Found matching solicited callback\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].solicited++; - } - } - - /* if a callback (either unsolicited or solicited) was found */ - if (callback != NULL) - { - /* invoke the callback to pass the message back to the client */ - callback (npeId, message); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].callbacks++; - } - else /* no callback (neither unsolicited nor solicited) was found */ - { - IX_NPEMH_TRACE2 (IX_NPEMH_WARNING, - "No matching callback for NPE %d" - " and ID 0x%02X, discarding message\n", - npeId, messageId); - - /* the message will be discarded. this is normal behaviour */ - /* if the client passes a NULL solicited callback when */ - /* sending a message. this indicates that the client is not */ - /* interested in receiving the response. alternatively a */ - /* NULL callback here may signify an unsolicited message */ - /* with no appropriate registered callback. */ - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveMessagesReceive\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhReceiveShow - */ - -void ixNpeMhReceiveShow ( - IxNpeMhNpeId npeId) -{ - /* show the ISR invocation counter */ - IX_NPEMH_SHOW ("Receive ISR invocations", - ixNpeMhReceiveStats[npeId].isrs); - - /* show the receive message invocation counter */ - IX_NPEMH_SHOW ("Receive messages invocations", - ixNpeMhReceiveStats[npeId].receives); - - /* show the message received counter */ - IX_NPEMH_SHOW ("Messages received", - ixNpeMhReceiveStats[npeId].messages); - - /* show the solicited message counter */ - IX_NPEMH_SHOW ("Solicited messages received", - ixNpeMhReceiveStats[npeId].solicited); - - /* show the unsolicited message counter */ - IX_NPEMH_SHOW ("Unsolicited messages received", - ixNpeMhReceiveStats[npeId].unsolicited); - - /* show the callback invoked counter */ - IX_NPEMH_SHOW ("Callbacks invoked", - ixNpeMhReceiveStats[npeId].callbacks); - - /* show the message discarded counter */ - IX_NPEMH_SHOW ("Received messages discarded", - (ixNpeMhReceiveStats[npeId].messages - - ixNpeMhReceiveStats[npeId].callbacks)); -} - -/* - * Function definition: ixNpeMhReceiveShowReset - */ - -void ixNpeMhReceiveShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the ISR invocation counter */ - ixNpeMhReceiveStats[npeId].isrs = 0; - - /* reset the receive message invocation counter */ - ixNpeMhReceiveStats[npeId].receives = 0; - - /* reset the message received counter */ - ixNpeMhReceiveStats[npeId].messages = 0; - - /* reset the solicited message counter */ - ixNpeMhReceiveStats[npeId].solicited = 0; - - /* reset the unsolicited message counter */ - ixNpeMhReceiveStats[npeId].unsolicited = 0; - - /* reset the callback invoked counter */ - ixNpeMhReceiveStats[npeId].callbacks = 0; -} diff --git a/drivers/net/npe/IxNpeMhSend.c b/drivers/net/npe/IxNpeMhSend.c deleted file mode 100644 index 27bc9b730c..0000000000 --- a/drivers/net/npe/IxNpeMhSend.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - * @file IxNpeMhSend.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Send module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhSend_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/** - * @def IX_NPEMH_INFIFO_RETRY_DELAY_US - * - * @brief Amount of time (uSecs) to delay between retries - * while inFIFO is Full when attempting to send a message - */ -#define IX_NPEMH_INFIFO_RETRY_DELAY_US (1) - - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhSendStats - * - * @brief This structure is used to maintain statistics for the Send - * module. - */ - -typedef struct -{ - UINT32 sends; /**< send invocations */ - UINT32 sendWithResponses; /**< send with response invocations */ - UINT32 queueFulls; /**< fifo queue full occurrences */ - UINT32 queueFullRetries; /**< fifo queue full retry occurrences */ - UINT32 maxQueueFullRetries; /**< max fifo queue full retries */ - UINT32 callbackFulls; /**< callback list full occurrences */ -} IxNpeMhSendStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhSendStats ixNpeMhSendStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -BOOL ixNpeMhSendInFifoIsFull( - IxNpeMhNpeId npeId, - UINT32 maxSendRetries); - -/* - * Function definition: ixNpeMhSendInFifoIsFull - */ - -PRIVATE -BOOL ixNpeMhSendInFifoIsFull( - IxNpeMhNpeId npeId, - UINT32 maxSendRetries) -{ - BOOL isFull = false; - UINT32 numRetries = 0; - - /* check the NPE's inFIFO */ - isFull = ixNpeMhConfigInFifoIsFull (npeId); - - /* we retry a few times, just to give the NPE a chance to read from */ - /* the FIFO if the FIFO is currently full */ - while (isFull && (numRetries++ < maxSendRetries)) - { - if (numRetries >= IX_NPEMH_SEND_RETRIES_DEFAULT) - { - /* Delay here for as short a time as possible (1 us). */ - /* Adding a delay here should ensure we are not hogging */ - /* the AHB bus while we are retrying */ - ixOsalBusySleep (IX_NPEMH_INFIFO_RETRY_DELAY_US); - } - - /* re-check the NPE's inFIFO */ - isFull = ixNpeMhConfigInFifoIsFull (npeId); - - /* update statistical info */ - ixNpeMhSendStats[npeId].queueFullRetries++; - } - - /* record the highest number of retries that occurred */ - if (ixNpeMhSendStats[npeId].maxQueueFullRetries < numRetries) - { - ixNpeMhSendStats[npeId].maxQueueFullRetries = numRetries; - } - - if (isFull) - { - /* update statistical info */ - ixNpeMhSendStats[npeId].queueFulls++; - } - - return isFull; -} - -/* - * Function definition: ixNpeMhSendMessageSend - */ - -IX_STATUS ixNpeMhSendMessageSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - UINT32 maxSendRetries) -{ - IX_STATUS status; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSendMessageSend\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].sends++; - - /* check if the NPE's inFIFO is full - if so return an error */ - if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries)) - { - IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n"); - return IX_FAIL; - } - - /* write the message to the NPE's inFIFO */ - status = ixNpeMhConfigInFifoWrite (npeId, message); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSendMessageSend\n"); - - return status; -} - -/* - * Function definition: ixNpeMhSendMessageWithResponseSend - */ - -IX_STATUS ixNpeMhSendMessageWithResponseSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSendMessageWithResponseSend\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].sendWithResponses++; - - /* sr: this sleep will call the receive routine (no interrupts used!!!) */ - ixOsalSleep (IX_NPEMH_INFIFO_RETRY_DELAY_US); - - /* check if the NPE's inFIFO is full - if so return an error */ - if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries)) - { - IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n"); - return IX_FAIL; - } - - /* save the solicited callback */ - status = ixNpeMhSolicitedCbMgrCallbackSave ( - npeId, solicitedMessageId, solicitedCallback); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to save solicited callback\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].callbackFulls++; - - return status; - } - - /* write the message to the NPE's inFIFO */ - status = ixNpeMhConfigInFifoWrite (npeId, message); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSendMessageWithResponseSend\n"); - - return status; -} - -/* - * Function definition: ixNpeMhSendShow - */ - -void ixNpeMhSendShow ( - IxNpeMhNpeId npeId) -{ - /* show the message send invocation counter */ - IX_NPEMH_SHOW ("Send invocations", - ixNpeMhSendStats[npeId].sends); - - /* show the message send with response invocation counter */ - IX_NPEMH_SHOW ("Send with response invocations", - ixNpeMhSendStats[npeId].sendWithResponses); - - /* show the fifo queue full occurrence counter */ - IX_NPEMH_SHOW ("Fifo queue full occurrences", - ixNpeMhSendStats[npeId].queueFulls); - - /* show the fifo queue full retry occurrence counter */ - IX_NPEMH_SHOW ("Fifo queue full retry occurrences", - ixNpeMhSendStats[npeId].queueFullRetries); - - /* show the fifo queue full maximum retries counter */ - IX_NPEMH_SHOW ("Maximum fifo queue full retries", - ixNpeMhSendStats[npeId].maxQueueFullRetries); - - /* show the callback list full occurrence counter */ - IX_NPEMH_SHOW ("Solicited callback list full occurrences", - ixNpeMhSendStats[npeId].callbackFulls); -} - -/* - * Function definition: ixNpeMhSendShowReset - */ - -void ixNpeMhSendShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the message send invocation counter */ - ixNpeMhSendStats[npeId].sends = 0; - - /* reset the message send with response invocation counter */ - ixNpeMhSendStats[npeId].sendWithResponses = 0; - - /* reset the fifo queue full occurrence counter */ - ixNpeMhSendStats[npeId].queueFulls = 0; - - /* reset the fifo queue full retry occurrence counter */ - ixNpeMhSendStats[npeId].queueFullRetries = 0; - - /* reset the max fifo queue full retries counter */ - ixNpeMhSendStats[npeId].maxQueueFullRetries = 0; - - /* reset the callback list full occurrence counter */ - ixNpeMhSendStats[npeId].callbackFulls = 0; -} diff --git a/drivers/net/npe/IxNpeMhSolicitedCbMgr.c b/drivers/net/npe/IxNpeMhSolicitedCbMgr.c deleted file mode 100644 index 8e083a63bf..0000000000 --- a/drivers/net/npe/IxNpeMhSolicitedCbMgr.c +++ /dev/null @@ -1,358 +0,0 @@ -/** - * @file IxNpeMhSolicitedCbMgr.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Solicited Callback Manager module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ -#ifndef IXNPEMHCONFIG_P_H -# define IXNPEMHSOLICITEDCBMGR_C -#else -# error "Error, IxNpeMhConfig_p.h should not be included before this definition." -#endif - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhConfig_p.h" -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhSolicitedCallbackListEntry - * - * @brief This structure is used to store the information associated with - * an entry in the callback list. This consists of the ID of the send - * message (which indicates the ID of the corresponding response message) - * and the callback function pointer itself. - * - */ - -typedef struct IxNpeMhSolicitedCallbackListEntry -{ - /** message ID */ - IxNpeMhMessageId messageId; - - /** callback function pointer */ - IxNpeMhCallback callback; - - /** pointer to next entry in the list */ - struct IxNpeMhSolicitedCallbackListEntry *next; -} IxNpeMhSolicitedCallbackListEntry; - -/** - * @struct IxNpeMhSolicitedCallbackList - * - * @brief This structure is used to maintain the list of response - * callbacks. The number of entries in this list will be variable, and - * they will be stored in a linked list fashion for ease of addition and - * removal. The entries themselves are statically allocated, and are - * organised into a "free" list and a "callback" list. Adding an entry - * means taking an entry from the "free" list and adding it to the - * "callback" list. Removing an entry means removing it from the - * "callback" list and returning it to the "free" list. - */ - -typedef struct -{ - /** pointer to the head of the free list */ - IxNpeMhSolicitedCallbackListEntry *freeHead; - - /** pointer to the head of the callback list */ - IxNpeMhSolicitedCallbackListEntry *callbackHead; - - /** pointer to the tail of the callback list */ - IxNpeMhSolicitedCallbackListEntry *callbackTail; - - /** array of entries - the first entry is used as a dummy entry to */ - /* avoid the scenario of having an empty list, hence '+ 1' */ - IxNpeMhSolicitedCallbackListEntry entries[IX_NPEMH_MAX_CALLBACKS + 1]; -} IxNpeMhSolicitedCallbackList; - -/** - * @struct IxNpeMhSolicitedCbMgrStats - * - * @brief This structure is used to maintain statistics for the Solicited - * Callback Manager module. - */ - -typedef struct -{ - UINT32 saves; /**< callback list saves */ - UINT32 retrieves; /**< callback list retrieves */ -} IxNpeMhSolicitedCbMgrStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhSolicitedCallbackList -ixNpeMhSolicitedCbMgrCallbackLists[IX_NPEMH_NUM_NPES]; - -PRIVATE IxNpeMhSolicitedCbMgrStats -ixNpeMhSolicitedCbMgrStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhSolicitedCbMgrInitialize - */ - -void ixNpeMhSolicitedCbMgrInitialize (void) -{ - IxNpeMhNpeId npeId; - UINT32 localIndex; - IxNpeMhSolicitedCallbackList *list = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSolicitedCbMgrInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* for each entry in the list, after the dummy entry ... */ - for (localIndex = 1; localIndex <= IX_NPEMH_MAX_CALLBACKS; localIndex++) - { - /* initialise the entry */ - list->entries[localIndex].messageId = 0x00; - list->entries[localIndex].callback = NULL; - - /* if this entry is before the last entry */ - if (localIndex < IX_NPEMH_MAX_CALLBACKS) - { - /* chain this entry to the following entry */ - list->entries[localIndex].next = &(list->entries[localIndex + 1]); - } - else /* this entry is the last entry */ - { - /* the last entry isn't chained to anything */ - list->entries[localIndex].next = NULL; - } - } - - /* set the free list pointer to point to the first real entry */ - /* (all real entries begin chained together on the free list) */ - list->freeHead = &(list->entries[1]); - - /* set the callback list pointers to point to the dummy entry */ - /* (the callback list is initially empty) */ - list->callbackHead = &(list->entries[0]); - list->callbackTail = &(list->entries[0]); - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSolicitedCbMgrInitialize\n"); -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrCallbackSave - */ - -IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback) -{ - IxNpeMhSolicitedCallbackList *list = NULL; - IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSolicitedCbMgrCallbackSave\n"); - - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* check to see if there are any entries in the free list */ - if (list->freeHead == NULL) - { - IX_NPEMH_ERROR_REPORT ("Solicited callback list is full\n"); - return IX_FAIL; - } - - /* there is an entry in the free list we can use */ - - /* update statistical info */ - ixNpeMhSolicitedCbMgrStats[npeId].saves++; - - /* remove a callback entry from the start of the free list */ - callbackEntry = list->freeHead; - list->freeHead = callbackEntry->next; - - /* fill in the callback entry with the new data */ - callbackEntry->messageId = solicitedMessageId; - callbackEntry->callback = solicitedCallback; - - /* the new callback entry will be added to the tail of the callback */ - /* list, so it isn't chained to anything */ - callbackEntry->next = NULL; - - /* chain new callback entry to the last entry of the callback list */ - list->callbackTail->next = callbackEntry; - list->callbackTail = callbackEntry; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSolicitedCbMgrCallbackSave\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrCallbackRetrieve - */ - -void ixNpeMhSolicitedCbMgrCallbackRetrieve ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback *solicitedCallback) -{ - IxNpeMhSolicitedCallbackList *list = NULL; - IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL; - IxNpeMhSolicitedCallbackListEntry *previousEntry = NULL; - - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* initialise the callback entry to the first entry of the callback */ - /* list - we must skip over the dummy entry, which is the previous */ - callbackEntry = list->callbackHead->next; - previousEntry = list->callbackHead; - - /* traverse the callback list looking for an entry with a matching */ - /* message ID. note we also save the previous entry's pointer to */ - /* allow us to unchain the matching entry from the callback list */ - while ((callbackEntry != NULL) && - (callbackEntry->messageId != solicitedMessageId)) - { - previousEntry = callbackEntry; - callbackEntry = callbackEntry->next; - } - - /* if we didn't find a matching callback entry */ - if (callbackEntry == NULL) - { - /* return a NULL callback in the outgoing parameter */ - *solicitedCallback = NULL; - } - else /* we found a matching callback entry */ - { - /* update statistical info */ - ixNpeMhSolicitedCbMgrStats[npeId].retrieves++; - - /* return the callback in the outgoing parameter */ - *solicitedCallback = callbackEntry->callback; - - /* unchain callback entry by chaining previous entry to next */ - previousEntry->next = callbackEntry->next; - - /* if the callback entry is at the tail of the list */ - if (list->callbackTail == callbackEntry) - { - /* update the tail of the callback list */ - list->callbackTail = previousEntry; - } - - /* re-initialise the callback entry */ - callbackEntry->messageId = 0x00; - callbackEntry->callback = NULL; - - /* add the callback entry to the start of the free list */ - callbackEntry->next = list->freeHead; - list->freeHead = callbackEntry; - } -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrShow - */ - -void ixNpeMhSolicitedCbMgrShow ( - IxNpeMhNpeId npeId) -{ - /* show the solicited callback list save counter */ - IX_NPEMH_SHOW ("Solicited callback list saves", - ixNpeMhSolicitedCbMgrStats[npeId].saves); - - /* show the solicited callback list retrieve counter */ - IX_NPEMH_SHOW ("Solicited callback list retrieves", - ixNpeMhSolicitedCbMgrStats[npeId].retrieves); -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrShowReset - */ - -void ixNpeMhSolicitedCbMgrShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the solicited callback list save counter */ - ixNpeMhSolicitedCbMgrStats[npeId].saves = 0; - - /* reset the solicited callback list retrieve counter */ - ixNpeMhSolicitedCbMgrStats[npeId].retrieves = 0; -} diff --git a/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c b/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c deleted file mode 100644 index d37f9f9306..0000000000 --- a/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c +++ /dev/null @@ -1,246 +0,0 @@ -/** - * @file IxNpeMhUnsolicitedCbMgr.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for - * the Unsolicited Callback Manager module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhUnsolicitedCbMgr_p.h" - - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhUnsolicitedCallbackTable - * - * @brief This structure is used to maintain the list of registered - * callbacks. One entry exists for each message ID, and a NULL entry will - * signify that no callback has been registered for that ID. - */ - -typedef struct -{ - /** array of entries */ - IxNpeMhCallback entries[IX_NPEMH_MAX_MESSAGE_ID + 1]; -} IxNpeMhUnsolicitedCallbackTable; - -/** - * @struct IxNpeMhUnsolicitedCbMgrStats - * - * @brief This structure is used to maintain statistics for the Unsolicited - * Callback Manager module. - */ - -typedef struct -{ - UINT32 saves; /**< callback table saves */ - UINT32 overwrites; /**< callback table overwrites */ -} IxNpeMhUnsolicitedCbMgrStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhUnsolicitedCallbackTable -ixNpeMhUnsolicitedCallbackTables[IX_NPEMH_NUM_NPES]; - -PRIVATE IxNpeMhUnsolicitedCbMgrStats -ixNpeMhUnsolicitedCbMgrStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrInitialize - */ - -void ixNpeMhUnsolicitedCbMgrInitialize (void) -{ - IxNpeMhNpeId npeId = 0; - IxNpeMhUnsolicitedCallbackTable *table = NULL; - IxNpeMhMessageId messageId = 0; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCbMgrInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - /* for each message ID ... */ - for (messageId = IX_NPEMH_MIN_MESSAGE_ID; - messageId <= IX_NPEMH_MAX_MESSAGE_ID; messageId++) - { - /* initialise the callback for this message ID to NULL */ - table->entries[messageId] = NULL; - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCbMgrInitialize\n"); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrCallbackSave - */ - -void ixNpeMhUnsolicitedCbMgrCallbackSave ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId unsolicitedMessageId, - IxNpeMhCallback unsolicitedCallback) -{ - IxNpeMhUnsolicitedCallbackTable *table = NULL; - - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCbMgrCallbackSave\n"); - - /* update statistical info */ - ixNpeMhUnsolicitedCbMgrStats[npeId].saves++; - - /* check if there is a callback already registered for this NPE and */ - /* message ID */ - if (table->entries[unsolicitedMessageId] != NULL) - { - /* if we are overwriting an existing callback */ - if (unsolicitedCallback != NULL) - { - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "Unsolicited callback " - "overwriting existing callback for NPE ID %d " - "message ID 0x%02X\n", npeId, unsolicitedMessageId); - } - else /* if we are clearing an existing callback */ - { - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NULL unsolicited callback " - "clearing existing callback for NPE ID %d " - "message ID 0x%02X\n", npeId, unsolicitedMessageId); - } - - /* update statistical info */ - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites++; - } - - /* save the callback into the table */ - table->entries[unsolicitedMessageId] = unsolicitedCallback; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCbMgrCallbackSave\n"); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrCallbackRetrieve - */ - -void ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId unsolicitedMessageId, - IxNpeMhCallback *unsolicitedCallback) -{ - IxNpeMhUnsolicitedCallbackTable *table = NULL; - - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - /* retrieve the callback from the table */ - *unsolicitedCallback = table->entries[unsolicitedMessageId]; -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrShow - */ - -void ixNpeMhUnsolicitedCbMgrShow ( - IxNpeMhNpeId npeId) -{ - /* show the unsolicited callback table save counter */ - IX_NPEMH_SHOW ("Unsolicited callback table saves", - ixNpeMhUnsolicitedCbMgrStats[npeId].saves); - - /* show the unsolicited callback table overwrite counter */ - IX_NPEMH_SHOW ("Unsolicited callback table overwrites", - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrShowReset - */ - -void ixNpeMhUnsolicitedCbMgrShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the unsolicited callback table save counter */ - ixNpeMhUnsolicitedCbMgrStats[npeId].saves = 0; - - /* reset the unsolicited callback table overwrite counter */ - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites = 0; -} diff --git a/drivers/net/npe/IxOsalBufferMgt.c b/drivers/net/npe/IxOsalBufferMgt.c deleted file mode 100644 index fa8db477af..0000000000 --- a/drivers/net/npe/IxOsalBufferMgt.c +++ /dev/null @@ -1,800 +0,0 @@ -/** - * @file IxOsalBufferMgt.c - * - * @brief Default buffer pool management and buffer management - * Implementation. - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/* - * OS may choose to use default bufferMgt by defining - * IX_OSAL_USE_DEFAULT_BUFFER_MGT in IxOsalOsBufferMgt.h - */ - -#include "IxOsal.h" - -#define IX_OSAL_BUFFER_FREE_PROTECTION /* Define this to enable Illegal MBuf Freed Protection*/ - -/* - * The implementation is only used when the following - * is defined. - */ -#ifdef IX_OSAL_USE_DEFAULT_BUFFER_MGT - - -#define IX_OSAL_MBUF_SYS_SIGNATURE (0x8BADF00D) -#define IX_OSAL_MBUF_SYS_SIGNATURE_MASK (0xEFFFFFFF) -#define IX_OSAL_MBUF_USED_FLAG (0x10000000) -#define IX_OSAL_MBUF_SYS_SIGNATURE_INIT(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = (UINT32)IX_OSAL_MBUF_SYS_SIGNATURE - -/* -* This implementation is protect, the buffer pool management's ixOsalMBufFree -* against an invalid MBUF pointer argument that already has been freed earlier -* or in other words resides in the free pool of MBUFs. This added feature, -* checks the MBUF "USED" FLAG. The Flag tells if the MBUF is still not freed -* back to the Buffer Pool. -* Disable this feature for performance reasons by undef -* IX_OSAL_BUFFER_FREE_PROTECTION macro. -*/ -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/ - -#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&(IX_OSAL_MBUF_SYS_SIGNATURE_MASK) ) -#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) do { \ - IX_OSAL_MBUF_SIGNATURE (bufPtr)&(~IX_OSAL_MBUF_SYS_SIGNATURE_MASK);\ - IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_SYS_SIGNATURE; \ - }while(0) - -#define IX_OSAL_MBUF_SET_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_USED_FLAG -#define IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)&=~IX_OSAL_MBUF_USED_FLAG -#define IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&IX_OSAL_MBUF_USED_FLAG) - -#else - -#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) -#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = IX_OSAL_MBUF_SYS_SIGNATURE - -#endif /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/ -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * A unit of 32, used to provide bit-shift for pool - * management. Needs some work if users want more than 32 pools. - */ -#define IX_OSAL_BUFF_FREE_BITS 32 - -PRIVATE UINT32 ixOsalBuffFreePools[IX_OSAL_MBUF_MAX_POOLS / - IX_OSAL_BUFF_FREE_BITS]; - -PUBLIC IX_OSAL_MBUF_POOL ixOsalBuffPools[IX_OSAL_MBUF_MAX_POOLS]; - -static int ixOsalBuffPoolsInUse = 0; - -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY -PRIVATE IX_OSAL_MBUF * -ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned, - UINT32 dataSizeAligned, - IX_OSAL_MBUF_POOL *poolPtr); -#endif - -PRIVATE IX_OSAL_MBUF_POOL * ixOsalPoolAlloc (void); - -/* - * Function definition: ixOsalPoolAlloc - */ - -/****************************/ - -PRIVATE IX_OSAL_MBUF_POOL * -ixOsalPoolAlloc (void) -{ - register unsigned int i = 0; - - /* - * Scan for the first free buffer. Free buffers are indicated by 0 - * on the corrsponding bit in ixOsalBuffFreePools. - */ - if (ixOsalBuffPoolsInUse >= IX_OSAL_MBUF_MAX_POOLS) - { - /* - * Fail to grab a ptr this time - */ - return NULL; - } - - while (ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] & - (1 << (i % IX_OSAL_BUFF_FREE_BITS))) - i++; - /* - * Free buffer found. Mark it as busy and initialize. - */ - ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] |= - (1 << (i % IX_OSAL_BUFF_FREE_BITS)); - - memset (&ixOsalBuffPools[i], 0, sizeof (IX_OSAL_MBUF_POOL)); - - ixOsalBuffPools[i].poolIdx = i; - ixOsalBuffPoolsInUse++; - - return &ixOsalBuffPools[i]; -} - - -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY -PRIVATE IX_OSAL_MBUF * -ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned, - UINT32 dataSizeAligned, - IX_OSAL_MBUF_POOL *poolPtr) -{ - UINT8 *dataPtr; - IX_OSAL_MBUF *realMbufPtr; - /* Allocate cache-aligned memory for mbuf header */ - realMbufPtr = (IX_OSAL_MBUF *) IX_OSAL_CACHE_DMA_MALLOC (mbufSizeAligned); - IX_OSAL_ASSERT (realMbufPtr != NULL); - memset (realMbufPtr, 0, mbufSizeAligned); - - /* Allocate cache-aligned memory for mbuf data */ - dataPtr = (UINT8 *) IX_OSAL_CACHE_DMA_MALLOC (dataSizeAligned); - IX_OSAL_ASSERT (dataPtr != NULL); - memset (dataPtr, 0, dataSizeAligned); - - /* Fill in mbuf header fields */ - IX_OSAL_MBUF_MDATA (realMbufPtr) = dataPtr; - IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (realMbufPtr) = (UINT32)dataPtr; - - IX_OSAL_MBUF_MLEN (realMbufPtr) = dataSizeAligned; - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN (realMbufPtr) = dataSizeAligned; - - IX_OSAL_MBUF_NET_POOL (realMbufPtr) = (IX_OSAL_MBUF_POOL *) poolPtr; - - IX_OSAL_MBUF_SYS_SIGNATURE_INIT(realMbufPtr); - - /* update some statistical information */ - poolPtr->mbufMemSize += mbufSizeAligned; - poolPtr->dataMemSize += dataSizeAligned; - - return realMbufPtr; -} -#endif /* #ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY */ - -/* - * Function definition: ixOsalBuffPoolInit - */ - -PUBLIC IX_OSAL_MBUF_POOL * -ixOsalPoolInit (UINT32 count, UINT32 size, const char *name) -{ - - /* These variables are only used if UX_OSAL_BUFFER_ALLOC_SEPERATELY - * is defined . - */ -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - UINT32 i, mbufSizeAligned, dataSizeAligned; - IX_OSAL_MBUF *currentMbufPtr = NULL; -#else - void *poolBufPtr; - void *poolDataPtr; - int mbufMemSize; - int dataMemSize; -#endif - - IX_OSAL_MBUF_POOL *poolPtr = NULL; - - if (count <= 0) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "count = 0 \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (name == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "NULL name \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " - "ERROR - name length should be no greater than %d \n", - IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0); - return NULL; - } - -/* OS can choose whether to allocate all buffers all together (if it - * can handle a huge single alloc request), or to allocate buffers - * separately by the defining IX_OSAL_BUFFER_ALLOC_SEPARATELY. - */ -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - /* Get a pool Ptr */ - poolPtr = ixOsalPoolAlloc (); - - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "Fail to Get PoolPtr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - mbufSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - dataSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN(size); - - poolPtr->nextFreeBuf = NULL; - poolPtr->mbufMemPtr = NULL; - poolPtr->dataMemPtr = NULL; - poolPtr->bufDataSize = dataSizeAligned; - poolPtr->totalBufsInPool = count; - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC; - strcpy (poolPtr->name, name); - - - for (i = 0; i < count; i++) - { - /* create an mbuf */ - currentMbufPtr = ixOsalBuffPoolMbufInit (mbufSizeAligned, - dataSizeAligned, - poolPtr); - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION -/* Set the Buffer USED Flag. If not, ixOsalMBufFree will fail. - ixOsalMbufFree used here is in a special case whereby, it's - used to add MBUF to the Pool. By specification, ixOsalMbufFree - deallocates an allocated MBUF from Pool. -*/ - IX_OSAL_MBUF_SET_USED_FLAG(currentMbufPtr); -#endif - /* Add it to the pool */ - ixOsalMbufFree (currentMbufPtr); - - /* flush the pool information to RAM */ - IX_OSAL_CACHE_FLUSH (currentMbufPtr, mbufSizeAligned); - } - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool = count; - -#else -/* Otherwise allocate buffers in a continuous block fashion */ - poolBufPtr = IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC (count, mbufMemSize); - IX_OSAL_ASSERT (poolBufPtr != NULL); - poolDataPtr = - IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC (count, size, dataMemSize); - IX_OSAL_ASSERT (poolDataPtr != NULL); - - poolPtr = ixOsalNoAllocPoolInit (poolBufPtr, poolDataPtr, - count, size, name); - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "Fail to get pool ptr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC; - -#endif /* IX_OSAL_BUFFER_ALLOC_SEPARATELY */ - return poolPtr; -} - -PUBLIC IX_OSAL_MBUF_POOL * -ixOsalNoAllocPoolInit (void *poolBufPtr, - void *poolDataPtr, UINT32 count, UINT32 size, const char *name) -{ - UINT32 i, mbufSizeAligned, sizeAligned; - IX_OSAL_MBUF *currentMbufPtr = NULL; - IX_OSAL_MBUF *nextMbufPtr = NULL; - IX_OSAL_MBUF_POOL *poolPtr = NULL; - - /* - * check parameters - */ - if (poolBufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - NULL poolBufPtr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (count <= 0) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - count must > 0 \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (name == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - NULL name ptr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - name length should be no greater than %d \n", - IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0); - return NULL; - } - - poolPtr = ixOsalPoolAlloc (); - - if (poolPtr == NULL) - { - return NULL; - } - - /* - * Adjust sizes to ensure alignment on cache line boundaries - */ - mbufSizeAligned = - IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - /* - * clear the mbuf memory area - */ - memset (poolBufPtr, 0, mbufSizeAligned * count); - - if (poolDataPtr != NULL) - { - /* - * Adjust sizes to ensure alignment on cache line boundaries - */ - sizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (size); - /* - * clear the data memory area - */ - memset (poolDataPtr, 0, sizeAligned * count); - } - else - { - sizeAligned = 0; - } - - /* - * initialise pool fields - */ - strcpy ((poolPtr)->name, name); - - poolPtr->dataMemPtr = poolDataPtr; - poolPtr->mbufMemPtr = poolBufPtr; - poolPtr->bufDataSize = sizeAligned; - poolPtr->totalBufsInPool = count; - poolPtr->mbufMemSize = mbufSizeAligned * count; - poolPtr->dataMemSize = sizeAligned * count; - - currentMbufPtr = (IX_OSAL_MBUF *) poolBufPtr; - - poolPtr->nextFreeBuf = currentMbufPtr; - - for (i = 0; i < count; i++) - { - if (i < (count - 1)) - { - nextMbufPtr = - (IX_OSAL_MBUF *) ((unsigned) currentMbufPtr + - mbufSizeAligned); - } - else - { /* last mbuf in chain */ - nextMbufPtr = NULL; - } - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (currentMbufPtr) = nextMbufPtr; - IX_OSAL_MBUF_NET_POOL (currentMbufPtr) = poolPtr; - - IX_OSAL_MBUF_SYS_SIGNATURE_INIT(currentMbufPtr); - - if (poolDataPtr != NULL) - { - IX_OSAL_MBUF_MDATA (currentMbufPtr) = poolDataPtr; - IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(currentMbufPtr) = (UINT32) poolDataPtr; - - IX_OSAL_MBUF_MLEN (currentMbufPtr) = sizeAligned; - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(currentMbufPtr) = sizeAligned; - - poolDataPtr = (void *) ((unsigned) poolDataPtr + sizeAligned); - } - - currentMbufPtr = nextMbufPtr; - } - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool = count; - - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC; - - return poolPtr; -} - -/* - * Get a mbuf ptr from the pool - */ -PUBLIC IX_OSAL_MBUF * -ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * poolPtr) -{ - int lock; - IX_OSAL_MBUF *newBufPtr = NULL; - - /* - * check parameters - */ - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalMbufAlloc(): " - "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - lock = ixOsalIrqLock (); - - newBufPtr = poolPtr->nextFreeBuf; - if (newBufPtr) - { - poolPtr->nextFreeBuf = - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr); - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr) = NULL; - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool--; - } - else - { - /* Return NULL to indicate to caller that request is denied. */ - ixOsalIrqUnlock (lock); - - return NULL; - } - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION - /* Set Buffer Used Flag to indicate state.*/ - IX_OSAL_MBUF_SET_USED_FLAG(newBufPtr); -#endif - - ixOsalIrqUnlock (lock); - - return newBufPtr; -} - -PUBLIC IX_OSAL_MBUF * -ixOsalMbufFree (IX_OSAL_MBUF * bufPtr) -{ - int lock; - IX_OSAL_MBUF_POOL *poolPtr; - - IX_OSAL_MBUF *nextBufPtr = NULL; - - /* - * check parameters - */ - if (bufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalMbufFree(): " - "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - - - lock = ixOsalIrqLock (); - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION - - /* Prevention for Buffer freed more than once*/ - if(!IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr)) - { - return NULL; - } - IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr); -#endif - - poolPtr = IX_OSAL_MBUF_NET_POOL (bufPtr); - - /* - * check the mbuf wrapper signature (if mbuf wrapper was used) - */ - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { - IX_OSAL_ENSURE ( (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) == IX_OSAL_MBUF_SYS_SIGNATURE), - "ixOsalBuffPoolBufFree: ERROR - Invalid mbuf signature."); - } - - nextBufPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr); - - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr) = poolPtr->nextFreeBuf; - poolPtr->nextFreeBuf = bufPtr; - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool++; - - ixOsalIrqUnlock (lock); - - return nextBufPtr; -} - -PUBLIC void -ixOsalMbufChainFree (IX_OSAL_MBUF * bufPtr) -{ - while ((bufPtr = ixOsalMbufFree (bufPtr))); -} - -/* - * Function definition: ixOsalBuffPoolShow - */ -PUBLIC void -ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * poolPtr) -{ - IX_OSAL_MBUF *nextBufPtr; - int count = 0; - int lock; - - /* - * check parameters - */ - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolShow(): " - "ERROR - Invalid Parameter", 0, 0, 0, 0, 0, 0); - /* - * return IX_FAIL; - */ - return; - } - - lock = ixOsalIrqLock (); - count = poolPtr->freeBufsInPool; - nextBufPtr = poolPtr->nextFreeBuf; - ixOsalIrqUnlock (lock); - - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, "=== POOL INFORMATION ===\n", 0, 0, 0, - 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Name: %s\n", - (unsigned int) poolPtr->name, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Allocation Type: %d\n", - (unsigned int) poolPtr->poolAllocType, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Mbuf Mem Usage (bytes): %d\n", - (unsigned int) poolPtr->mbufMemSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Data Mem Usage (bytes): %d\n", - (unsigned int) poolPtr->dataMemSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Mbuf Data Capacity (bytes): %d\n", - (unsigned int) poolPtr->bufDataSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Total Mbufs in Pool: %d\n", - (unsigned int) poolPtr->totalBufsInPool, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Available Mbufs: %d\n", (unsigned int) count, 0, - 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Next Available Mbuf: %p\n", (unsigned int) nextBufPtr, - 0, 0, 0, 0, 0); - - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC) - { - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, - "Mbuf Mem Area Start address: %p\n", - (unsigned int) poolPtr->mbufMemPtr, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Data Mem Area Start address: %p\n", - (unsigned int) poolPtr->dataMemPtr, 0, 0, 0, 0, 0); - } -} - -PUBLIC void -ixOsalMbufDataPtrReset (IX_OSAL_MBUF * bufPtr) -{ - IX_OSAL_MBUF_POOL *poolPtr; - UINT8 *poolDataPtr; - - if (bufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return; - } - - poolPtr = (IX_OSAL_MBUF_POOL *) IX_OSAL_MBUF_NET_POOL (bufPtr); - poolDataPtr = poolPtr->dataMemPtr; - - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { - if (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) != IX_OSAL_MBUF_SYS_SIGNATURE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": invalid mbuf, cannot reset mData pointer\n", 0, 0, - 0, 0, 0, 0); - return; - } - IX_OSAL_MBUF_MDATA (bufPtr) = (UINT8*)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (bufPtr); - } - else - { - if (poolDataPtr) - { - unsigned int bufSize = poolPtr->bufDataSize; - unsigned int bufDataAddr = - (unsigned int) IX_OSAL_MBUF_MDATA (bufPtr); - unsigned int poolDataAddr = (unsigned int) poolDataPtr; - - /* - * the pointer is still pointing somewhere in the mbuf payload. - * This operation moves the pointer to the beginning of the - * mbuf payload - */ - bufDataAddr = ((bufDataAddr - poolDataAddr) / bufSize) * bufSize; - IX_OSAL_MBUF_MDATA (bufPtr) = &poolDataPtr[bufDataAddr]; - } - else - { - ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": cannot be used if user supplied NULL pointer for pool data area " - "when pool was created\n", 0, 0, 0, 0, 0, 0); - return; - } - } - -} - -/* - * Function definition: ixOsalBuffPoolUninit - */ -PUBLIC IX_STATUS -ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool) -{ - if (!pool) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolUninit: NULL ptr \n", 0, 0, 0, 0, 0, 0); - return IX_FAIL; - } - - if (pool->freeBufsInPool != pool->totalBufsInPool) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolUninit: need to return all ptrs to the pool first! \n", - 0, 0, 0, 0, 0, 0); - return IX_FAIL; - } - - if (pool->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - UINT32 i; - IX_OSAL_MBUF* pBuf; - - pBuf = pool->nextFreeBuf; - /* Freed the Buffer one by one till all the Memory is freed*/ - for (i= pool->freeBufsInPool; i >0 && pBuf!=NULL ;i--){ - IX_OSAL_MBUF* pBufTemp; - pBufTemp = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(pBuf); - /* Freed MBUF Data Memory area*/ - IX_OSAL_CACHE_DMA_FREE( (void *) (IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(pBuf)) ); - /* Freed MBUF Struct Memory area*/ - IX_OSAL_CACHE_DMA_FREE(pBuf); - pBuf = pBufTemp; - } - -#else - IX_OSAL_CACHE_DMA_FREE (pool->mbufMemPtr); - IX_OSAL_CACHE_DMA_FREE (pool->dataMemPtr); -#endif - } - - ixOsalBuffFreePools[pool->poolIdx / IX_OSAL_BUFF_FREE_BITS] &= - ~(1 << (pool->poolIdx % IX_OSAL_BUFF_FREE_BITS)); - ixOsalBuffPoolsInUse--; - return IX_SUCCESS; -} - -/* - * Function definition: ixOsalBuffPoolDataAreaSizeGet - */ -PUBLIC UINT32 -ixOsalBuffPoolDataAreaSizeGet (int count, int size) -{ - UINT32 memorySize; - memorySize = count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (size); - return memorySize; -} - -/* - * Function definition: ixOsalBuffPoolMbufAreaSizeGet - */ -PUBLIC UINT32 -ixOsalBuffPoolMbufAreaSizeGet (int count) -{ - UINT32 memorySize; - memorySize = - count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - return memorySize; -} - -/* - * Function definition: ixOsalBuffPoolFreeCountGet - */ -PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * poolPtr) - -{ - - return poolPtr->freeBufsInPool; - -} - -#endif /* IX_OSAL_USE_DEFAULT_BUFFER_MGT */ diff --git a/drivers/net/npe/IxOsalIoMem.c b/drivers/net/npe/IxOsalIoMem.c deleted file mode 100644 index 34df92bf79..0000000000 --- a/drivers/net/npe/IxOsalIoMem.c +++ /dev/null @@ -1,332 +0,0 @@ -/** - * @file IxOsalIoMem.c - * - * @brief OS-independent IO/Mem implementation - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/* Access to the global mem map is only allowed in this file */ -#define IxOsalIoMem_C - -#include "IxOsal.h" - -#define SEARCH_PHYSICAL_ADDRESS (1) -#define SEARCH_VIRTUAL_ADDRESS (2) - -/* - * Searches for map using one of the following criteria: - * - * - enough room to include a zone starting with the physical "requestedAddress" of size "size" (for mapping) - * - includes the virtual "requestedAddress" in its virtual address space (already mapped, for unmapping) - * - correct coherency - * - * Returns a pointer to the map or NULL if a suitable map is not found. - */ -PRIVATE IxOsalMemoryMap * -ixOsalMemMapFind (UINT32 requestedAddress, - UINT32 size, UINT32 searchCriteria, UINT32 requestedEndianType) -{ - UINT32 mapIndex; - - UINT32 numMapElements = - sizeof (ixOsalGlobalMemoryMap) / sizeof (IxOsalMemoryMap); - - for (mapIndex = 0; mapIndex < numMapElements; mapIndex++) - { - IxOsalMemoryMap *map = &ixOsalGlobalMemoryMap[mapIndex]; - - if (searchCriteria == SEARCH_PHYSICAL_ADDRESS - && requestedAddress >= map->physicalAddress - && (requestedAddress + size) <= (map->physicalAddress + map->size) - && (map->mapEndianType & requestedEndianType) != 0) - { - return map; - } - else if (searchCriteria == SEARCH_VIRTUAL_ADDRESS - && requestedAddress >= map->virtualAddress - && requestedAddress <= (map->virtualAddress + map->size) - && (map->mapEndianType & requestedEndianType) != 0) - { - return map; - } - else if (searchCriteria == SEARCH_PHYSICAL_ADDRESS) - { - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - "Osal: Checking [phys addr 0x%x:size 0x%x:endianType %d]\n", - map->physicalAddress, map->size, map->mapEndianType, 0, 0, 0); - } - } - - /* - * not found - */ - return NULL; -} - -/* - * This function maps an I/O mapped physical memory zone of the given size - * into a virtual memory zone accessible by the caller and returns a cookie - - * the start address of the virtual memory zone. - * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned - * virtual address. - * The memory zone is to be unmapped using ixOsalMemUnmap once the caller has - * finished using this zone (e.g. on driver unload) using the cookie as - * parameter. - * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write - * the mapped memory, adding the necessary offsets to the address cookie. - * - * Note: this function is not to be used directly. Use IX_OSAL_MEM_MAP - * instead. - */ -PUBLIC void * -ixOsalIoMemMap (UINT32 requestedAddress, - UINT32 size, IxOsalMapEndianessType requestedEndianType) -{ - IxOsalMemoryMap *map; - - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - "OSAL: Mapping [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - - if (requestedEndianType == IX_OSAL_LE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalIoMemMap: Please specify component coherency mode to use MEM functions \n", - 0, 0, 0, 0, 0, 0); - return (NULL); - } - map = ixOsalMemMapFind (requestedAddress, - size, SEARCH_PHYSICAL_ADDRESS, requestedEndianType); - if (map != NULL) - { - UINT32 offset = requestedAddress - map->physicalAddress; - - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, "OSAL: Found map [", 0, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, map->name, 0, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - ":addr 0x%x: virt 0x%x:size 0x%x:ref %d:endianType %d]\n", - map->physicalAddress, map->virtualAddress, - map->size, map->refCount, map->mapEndianType, 0); - - if (map->type == IX_OSAL_DYNAMIC_MAP && map->virtualAddress == 0) - { - if (map->mapFunction != NULL) - { - map->mapFunction (map); - - if (map->virtualAddress == 0) - { - /* - * failed - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: Remap failed - [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - return NULL; - } - } - else - { - /* - * error, no map function for a dynamic map - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: No map function for a dynamic map - " - "[addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - - return NULL; - } - } - - /* - * increment reference count - */ - map->refCount++; - - return (void *) (map->virtualAddress + offset); - } - - /* - * requested address is not described in the global memory map - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: No mapping found - [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - return NULL; -} - -/* - * This function unmaps a previously mapped I/O memory zone using - * the cookie obtained in the mapping operation. The memory zone in question - * becomes unavailable to the caller once unmapped and the cookie should be - * discarded. - * - * This function cannot fail if the given parameter is correct and does not - * return a value. - * - * Note: this function is not to be used directly. Use IX_OSAL_MEM_UNMAP - * instead. - */ -PUBLIC void -ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType) -{ - IxOsalMemoryMap *map; - - if (endianType == IX_OSAL_LE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalIoMemUnmap: Please specify component coherency mode to use MEM functions \n", - 0, 0, 0, 0, 0, 0); - return; - } - - if (requestedAddress == 0) - { - /* - * invalid virtual address - */ - return; - } - - map = - ixOsalMemMapFind (requestedAddress, 0, SEARCH_VIRTUAL_ADDRESS, - endianType); - - if (map != NULL) - { - if (map->refCount > 0) - { - /* - * decrement reference count - */ - map->refCount--; - - if (map->refCount == 0) - { - /* - * no longer used, deallocate - */ - if (map->type == IX_OSAL_DYNAMIC_MAP - && map->unmapFunction != NULL) - { - map->unmapFunction (map); - } - } - } - } - else - { - ixOsalLog (IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: ixOsServMemUnmap didn't find the requested map " - "[virt addr 0x%x: endianType %d], ignoring call\n", - requestedAddress, endianType, 0, 0, 0, 0); - } -} - -/* - * This function Converts a virtual address into a physical - * address, including the dynamically mapped memory. - * - * Parameters virtAddr - virtual address to convert - * Return value: corresponding physical address, or NULL - * if there is no physical address addressable - * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos - * Reentrant: Yes - * IRQ safe: Yes - */ -PUBLIC UINT32 -ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency) -{ - IxOsalMemoryMap *map = - ixOsalMemMapFind (virtualAddress, 0, SEARCH_VIRTUAL_ADDRESS, - requestedCoherency); - - if (map != NULL) - { - return map->physicalAddress + virtualAddress - map->virtualAddress; - } - else - { - return (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS (virtualAddress); - } -} - -/* - * This function Converts a virtual address into a physical - * address, including the dynamically mapped memory. - * - * Parameters virtAddr - virtual address to convert - * Return value: corresponding physical address, or NULL - * if there is no physical address addressable - * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos - * Reentrant: Yes - * IRQ safe: Yes - */ -PUBLIC UINT32 -ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 requestedCoherency) -{ - IxOsalMemoryMap *map = - ixOsalMemMapFind (physicalAddress, 0, SEARCH_PHYSICAL_ADDRESS, - requestedCoherency); - - if (map != NULL) - { - return map->virtualAddress + physicalAddress - map->physicalAddress; - } - else - { - return (UINT32) IX_OSAL_MMU_PHYS_TO_VIRT (physicalAddress); - } -} diff --git a/drivers/net/npe/IxOsalOsCacheMMU.c b/drivers/net/npe/IxOsalOsCacheMMU.c deleted file mode 100644 index 3db1a70da9..0000000000 --- a/drivers/net/npe/IxOsalOsCacheMMU.c +++ /dev/null @@ -1,67 +0,0 @@ -/** - * @file IxOsalOsCacheMMU.c (linux) - * - * @brief Cache MemAlloc and MemFree. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -#include - -/* - * Allocate on a cache line boundary (null pointers are - * not affected by this operation). This operation is NOT cache safe. - */ -void * -ixOsalCacheDmaMalloc (UINT32 n) -{ - return malloc(n); -} - -/* - * - */ -void -ixOsalCacheDmaFree (void *ptr) -{ - free(ptr); -} diff --git a/drivers/net/npe/IxOsalOsMsgQ.c b/drivers/net/npe/IxOsalOsMsgQ.c deleted file mode 100644 index 45a5c68b16..0000000000 --- a/drivers/net/npe/IxOsalOsMsgQ.c +++ /dev/null @@ -1,79 +0,0 @@ -/** - * @file IxOsalOsMsgQ.c (eCos) - * - * @brief OS-specific Message Queue implementation. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -/******************************* - * Public functions - *******************************/ -PUBLIC IX_STATUS -ixOsalMessageQueueCreate (IxOsalMessageQueue * queue, - UINT32 msgCount, UINT32 msgLen) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueDelete (IxOsalMessageQueue * queue) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueSend (IxOsalMessageQueue * queue, UINT8 * message) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - diff --git a/drivers/net/npe/IxOsalOsSemaphore.c b/drivers/net/npe/IxOsalOsSemaphore.c deleted file mode 100644 index 672bec1189..0000000000 --- a/drivers/net/npe/IxOsalOsSemaphore.c +++ /dev/null @@ -1,233 +0,0 @@ -/** - * @file IxOsalOsSemaphore.c (eCos) - * - * @brief Implementation for semaphore and mutex. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxNpeMhReceive_p.h" - -/* Define a large number */ -#define IX_OSAL_MAX_LONG (0x7FFFFFFF) - -/* Max timeout in MS, used to guard against possible overflow */ -#define IX_OSAL_MAX_TIMEOUT_MS (IX_OSAL_MAX_LONG/HZ) - - -PUBLIC IX_STATUS -ixOsalSemaphoreInit (IxOsalSemaphore * sid, UINT32 start_value) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -/** - * DESCRIPTION: If the semaphore is 'empty', the calling thread is blocked. - * If the semaphore is 'full', it is taken and control is returned - * to the caller. If the time indicated in 'timeout' is reached, - * the thread will unblock and return an error indication. If the - * timeout is set to 'IX_OSAL_WAIT_NONE', the thread will never block; - * if it is set to 'IX_OSAL_WAIT_FOREVER', the thread will block until - * the semaphore is available. - * - * - */ - - -PUBLIC IX_STATUS -ixOsalSemaphoreWait (IxOsalOsSemaphore * sid, INT32 timeout) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -/* - * Attempt to get semaphore, return immediately, - * no error info because users expect some failures - * when using this API. - */ -PUBLIC IX_STATUS -ixOsalSemaphoreTryWait (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -/** - * - * DESCRIPTION: This function causes the next available thread in the pend queue - * to be unblocked. If no thread is pending on this semaphore, the - * semaphore becomes 'full'. - */ -PUBLIC IX_STATUS -ixOsalSemaphorePost (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalSemaphoreGetValue (IxOsalSemaphore * sid, UINT32 * value) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalSemaphoreDestroy (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -/**************************** - * Mutex - ****************************/ - -static void drv_mutex_init(IxOsalMutex *mutex) -{ - *mutex = 0; -} - -static void drv_mutex_destroy(IxOsalMutex *mutex) -{ - *mutex = -1; -} - -static int drv_mutex_trylock(IxOsalMutex *mutex) -{ - int result = true; - - if (*mutex == 1) - result = false; - - return result; -} - -static void drv_mutex_unlock(IxOsalMutex *mutex) -{ - if (*mutex == 1) - printf("Trying to unlock unlocked mutex!"); - - *mutex = 0; -} - -PUBLIC IX_STATUS -ixOsalMutexInit (IxOsalMutex * mutex) -{ - drv_mutex_init(mutex); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout) -{ - int tries; - - if (timeout == IX_OSAL_WAIT_NONE) { - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - else - return IX_FAIL; - } - - tries = (timeout * 1000) / 50; - while (1) { - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - if (timeout != IX_OSAL_WAIT_FOREVER && tries-- <= 0) - break; - udelay(50); - } - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMutexUnlock (IxOsalMutex * mutex) -{ - drv_mutex_unlock(mutex); - return IX_SUCCESS; -} - -/* - * Attempt to get mutex, return immediately, - * no error info because users expect some failures - * when using this API. - */ -PUBLIC IX_STATUS -ixOsalMutexTryLock (IxOsalMutex * mutex) -{ - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMutexDestroy (IxOsalMutex * mutex) -{ - drv_mutex_destroy(mutex); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalFastMutexInit (IxOsalFastMutex * mutex) -{ - return ixOsalMutexInit(mutex); -} - -PUBLIC IX_STATUS ixOsalFastMutexTryLock(IxOsalFastMutex *mutex) -{ - return ixOsalMutexTryLock(mutex); -} - - -PUBLIC IX_STATUS -ixOsalFastMutexUnlock (IxOsalFastMutex * mutex) -{ - return ixOsalMutexUnlock(mutex); -} - -PUBLIC IX_STATUS -ixOsalFastMutexDestroy (IxOsalFastMutex * mutex) -{ - return ixOsalMutexDestroy(mutex); -} diff --git a/drivers/net/npe/IxOsalOsServices.c b/drivers/net/npe/IxOsalOsServices.c deleted file mode 100644 index e18c6c4c1e..0000000000 --- a/drivers/net/npe/IxOsalOsServices.c +++ /dev/null @@ -1,251 +0,0 @@ -/** - * @file IxOsalOsServices.c (linux) - * - * @brief Implementation for Irq, Mem, sleep. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include -#include -#include "IxOsal.h" -#include -#include -#include -#include -#include - -static char *traceHeaders[] = { - "", - "[fatal] ", - "[error] ", - "[warning] ", - "[message] ", - "[debug1] ", - "[debug2] ", - "[debug3] ", - "[all]" -}; - -/* by default trace all but debug message */ -PRIVATE int ixOsalCurrLogLevel = IX_OSAL_LOG_LVL_MESSAGE; - -/************************************** - * Irq services - *************************************/ - -PUBLIC IX_STATUS -ixOsalIrqBind (UINT32 vector, IxOsalVoidFnVoidPtr routine, void *parameter) -{ - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalIrqUnbind (UINT32 vector) -{ - return IX_FAIL; -} - -PUBLIC UINT32 -ixOsalIrqLock () -{ - return 0; -} - -/* Enable interrupts and task scheduling, - * input parameter: irqEnable status returned - * by ixOsalIrqLock(). - */ -PUBLIC void -ixOsalIrqUnlock (UINT32 lockKey) -{ -} - -PUBLIC UINT32 -ixOsalIrqLevelSet (UINT32 level) -{ - return IX_FAIL; -} - -PUBLIC void -ixOsalIrqEnable (UINT32 irqLevel) -{ -} - -PUBLIC void -ixOsalIrqDisable (UINT32 irqLevel) -{ -} - -/********************* - * Log function - *********************/ - -INT32 -ixOsalLog (IxOsalLogLevel level, - IxOsalLogDevice device, - char *format, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) -{ - /* - * Return -1 for custom display devices - */ - if ((device != IX_OSAL_LOG_DEV_STDOUT) - && (device != IX_OSAL_LOG_DEV_STDERR)) - { - debug("ixOsalLog: only IX_OSAL_LOG_DEV_STDOUT and IX_OSAL_LOG_DEV_STDERR are supported \n"); - return (IX_OSAL_LOG_ERROR); - } - - if (level <= ixOsalCurrLogLevel && level != IX_OSAL_LOG_LVL_NONE) - { -#if 0 /* sr: U-Boots printf or debug doesn't return a length */ - int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : diag_printf(traceHeaders[level - 1]); - - return headerByteCount + diag_printf (format, arg1, arg2, arg3, arg4, arg5, arg6); -#else - int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : strlen(traceHeaders[level - 1]); - - return headerByteCount + strlen(format); -#endif - } - else - { - /* - * Return error - */ - return (IX_OSAL_LOG_ERROR); - } -} - -PUBLIC UINT32 -ixOsalLogLevelSet (UINT32 level) -{ - UINT32 oldLevel; - - /* - * Check value first - */ - if ((level < IX_OSAL_LOG_LVL_NONE) || (level > IX_OSAL_LOG_LVL_ALL)) - { - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalLogLevelSet: Log Level is between %d and%d \n", - IX_OSAL_LOG_LVL_NONE, IX_OSAL_LOG_LVL_ALL, 0, 0, 0, 0); - return IX_OSAL_LOG_LVL_NONE; - } - oldLevel = ixOsalCurrLogLevel; - - ixOsalCurrLogLevel = level; - - return oldLevel; -} - -/************************************** - * Task services - *************************************/ - -PUBLIC void -ixOsalBusySleep (UINT32 microseconds) -{ - udelay(microseconds); -} - -PUBLIC void -ixOsalSleep (UINT32 milliseconds) -{ - if (milliseconds != 0) { -#if 1 - /* - * sr: We poll while we wait because interrupts are off in U-Boot - * and CSR expects messages, etc to be dispatched while sleeping. - */ - int i; - IxQMgrDispatcherFuncPtr qDispatcherFunc; - - ixQMgrDispatcherLoopGet(&qDispatcherFunc); - - while (milliseconds--) { - for (i = 1; i <= 2; i++) - ixNpeMhMessagesReceive(i); - (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP); - - udelay(1000); - } -#endif - } -} - -/************************************** - * Memory functions - *************************************/ - -void * -ixOsalMemAlloc (UINT32 size) -{ - return (void *)0; -} - -void -ixOsalMemFree (void *ptr) -{ -} - -/* - * Copy count bytes from src to dest , - * returns pointer to the dest mem zone. - */ -void * -ixOsalMemCopy (void *dest, void *src, UINT32 count) -{ - IX_OSAL_ASSERT (dest != NULL); - IX_OSAL_ASSERT (src != NULL); - return (memcpy (dest, src, count)); -} - -/* - * Fills a memory zone with a given constant byte, - * returns pointer to the memory zone. - */ -void * -ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count) -{ - IX_OSAL_ASSERT (ptr != NULL); - return (memset (ptr, filler, count)); -} diff --git a/drivers/net/npe/IxOsalOsThread.c b/drivers/net/npe/IxOsalOsThread.c deleted file mode 100644 index e6a4967fcd..0000000000 --- a/drivers/net/npe/IxOsalOsThread.c +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file IxOsalOsThread.c (eCos) - * - * @brief OS-specific thread implementation. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -/* Thread attribute is ignored */ -PUBLIC IX_STATUS -ixOsalThreadCreate (IxOsalThread * ptrTid, - IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg) -{ - return IX_SUCCESS; -} - -/* - * Start thread after given its thread handle - */ -PUBLIC IX_STATUS -ixOsalThreadStart (IxOsalThread * tId) -{ - /* Thread already started upon creation */ - return IX_SUCCESS; -} - -/* - * In Linux threadKill does not actually destroy the thread, - * it will stop the signal handling. - */ -PUBLIC IX_STATUS -ixOsalThreadKill (IxOsalThread * tid) -{ - return IX_SUCCESS; -} - -PUBLIC void -ixOsalThreadExit (void) -{ -} - -PUBLIC IX_STATUS -ixOsalThreadPrioritySet (IxOsalOsThread * tid, UINT32 priority) -{ - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalThreadSuspend (IxOsalThread * tId) -{ - return IX_SUCCESS; - -} - -PUBLIC IX_STATUS -ixOsalThreadResume (IxOsalThread * tId) -{ - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxQMgrAqmIf.c b/drivers/net/npe/IxQMgrAqmIf.c deleted file mode 100644 index 738651322c..0000000000 --- a/drivers/net/npe/IxQMgrAqmIf.c +++ /dev/null @@ -1,963 +0,0 @@ -/* - * @file: IxQMgrAqmIf.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This component provides a set of functions for - * perfoming I/O on the AQM hardware. - * - * Design Notes: - * These functions are intended to be as fast as possible - * and as a result perform NO PARAMETER CHECKING. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Inlines are compiled as function when this is defined. - * N.B. Must be placed before #include of "IxQMgrAqmIf_p.h - */ -#ifndef IXQMGRAQMIF_P_H -# define IXQMGRAQMIF_C -#else -# error -#endif - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrLog_p.h" - - -/* - * #defines and macros used in this file. - */ - -/* These defines are the bit offsets of the various fields of - * the queue configuration register - */ -#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00 -#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07 -#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E -#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16 -#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18 -#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A -#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D - -#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 0x40 -#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 0x6 - -#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF -#define IX_QMGR_NE_MASK 0x7 -#define IX_QMGR_NF_MASK 0x7 -#define IX_QMGR_SIZE_MASK 0x3 -#define IX_QMGR_ENTRY_SIZE_MASK 0x3 -#define IX_QMGR_BADDR_MASK 0x003FC000 -#define IX_QMGR_RDPTR_MASK 0x7F -#define IX_QMGR_WRPTR_MASK 0x7F -#define IX_QMGR_RDWRPTR_MASK 0x00003FFF - -#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000 - -/* Base address of AQM SRAM */ -#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \ -((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE)) - -/* Min buffer size used for generating buffer size in QUECONFIG */ -#define IX_QMGR_MIN_BUFFER_SIZE 16 - -/* Reset values of QMgr hardware registers */ -#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333 -#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000 -#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF -#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000 -#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000 -#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000 -#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF -#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000 - -#define IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS IX_OSAL_IXP400_QMGR_PHYS_BASE - -#define IX_QMGR_QUELOWSTAT_BITS_PER_Q (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) - -#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7 -#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\ - (((qId) * IX_QMGR_NUM_BYTES_PER_WORD) +\ - IX_QMGR_QUECONFIG_BASE_OFFSET) - -#define IX_QMGR_ENTRY1_OFFSET 0 -#define IX_QMGR_ENTRY2_OFFSET 1 -#define IX_QMGR_ENTRY4_OFFSET 3 - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ -UINT32 aqmBaseAddress = 0; -/* Store addresses and bit-masks for certain queue access and status registers. - * This is to facilitate inlining of QRead, QWrite and QStatusGet functions - * in IxQMgr,h - */ -extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; -UINT32 * ixQMgrAqmIfQueAccRegAddr[IX_QMGR_MAX_NUM_QUEUES]; -UINT32 ixQMgrAqmIfQueLowStatRegAddr[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueLowStatBitsOffset[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueLowStatBitsMask; -UINT32 ixQMgrAqmIfQueUppStat0RegAddr; -UINT32 ixQMgrAqmIfQueUppStat1RegAddr; -UINT32 ixQMgrAqmIfQueUppStat0BitMask[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueUppStat1BitMask[IX_QMGR_MIN_QUEUPP_QID]; - -/* - * Fast mutexes, one for each queue, used to protect peek & poke functions - */ -IxOsalFastMutex ixQMgrAqmIfPeekPokeFastMutex[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * Function prototypes - */ -PRIVATE unsigned -watermarkToAqmWatermark (IxQMgrWMLevel watermark ); - -PRIVATE unsigned -entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize); - -PRIVATE unsigned -bufferSizeToAqmBufferSize (unsigned bufferSizeInWords); - -PRIVATE void -ixQMgrAqmIfRegistersReset (void); - -PRIVATE void -ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex, - UINT32 configRegWord, - unsigned int qEntrySizeInwords, - unsigned int qSizeInWords, - UINT32 **address); -/* - * Function definitions - */ -void -ixQMgrAqmIfInit (void) -{ - UINT32 aqmVirtualAddr; - int i; - - /* The value of aqmBaseAddress depends on the logical address - * assigned by the MMU. - */ - aqmVirtualAddr = - (UINT32) IX_OSAL_MEM_MAP(IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS, - IX_OSAL_IXP400_QMGR_MAP_SIZE); - IX_OSAL_ASSERT (aqmVirtualAddr); - - ixQMgrAqmIfBaseAddressSet (aqmVirtualAddr); - - ixQMgrAqmIfRegistersReset (); - - for (i = 0; i< IX_QMGR_MAX_NUM_QUEUES; i++) - { - ixOsalFastMutexInit(&ixQMgrAqmIfPeekPokeFastMutex[i]); - - /******************************************************************** - * Register addresses and bit masks are calculated and stored here to - * facilitate inlining of QRead, QWrite and QStatusGet functions in - * IxQMgr.h. - * These calculations are normally performed dynamically in inlined - * functions in IxQMgrAqmIf_p.h, and their semantics are reused here. - */ - - /* AQM Queue access reg addresses, per queue */ - ixQMgrAqmIfQueAccRegAddr[i] = - (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); - ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = - (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); - - - ixQMgrQInlinedReadWriteInfo[i].qConfigRegAddr = - (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(i)); - - /* AQM Queue lower-group (0-31), only */ - if (i < IX_QMGR_MIN_QUEUPP_QID) - { - /* AQM Q underflow/overflow status register addresses, per queue */ - ixQMgrQInlinedReadWriteInfo[i].qUOStatRegAddr = - (volatile UINT32 *)(aqmBaseAddress + - IX_QMGR_QUEUOSTAT0_OFFSET + - ((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_NUM_BYTES_PER_WORD)); - - /* AQM Q underflow status bit masks for status register per queue */ - ixQMgrQInlinedReadWriteInfo[i].qUflowStatBitMask = - (IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) << - ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD)); - - /* AQM Q overflow status bit masks for status register, per queue */ - ixQMgrQInlinedReadWriteInfo[i].qOflowStatBitMask = - (IX_QMGR_OVERFLOW_BIT_OFFSET + 1) << - ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD)); - - /* AQM Q lower-group (0-31) status register addresses, per queue */ - ixQMgrAqmIfQueLowStatRegAddr[i] = aqmBaseAddress + - IX_QMGR_QUELOWSTAT0_OFFSET + - ((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_NUM_BYTES_PER_WORD); - - /* AQM Q lower-group (0-31) status register bit offset */ - ixQMgrAqmIfQueLowStatBitsOffset[i] = - (i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD); - } - else /* AQM Q upper-group (32-63), only */ - { - /* AQM Q upper-group (32-63) Nearly Empty status reg bit masks */ - ixQMgrAqmIfQueUppStat0BitMask[i - IX_QMGR_MIN_QUEUPP_QID] = - (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); - - /* AQM Q upper-group (32-63) Full status register bit masks */ - ixQMgrAqmIfQueUppStat1BitMask[i - IX_QMGR_MIN_QUEUPP_QID] = - (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); - } - } - - /* AQM Q lower-group (0-31) status register bit mask */ - ixQMgrAqmIfQueLowStatBitsMask = (1 << - (BITS_PER_WORD / - IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)) - 1; - - /* AQM Q upper-group (32-63) Nearly Empty status register address */ - ixQMgrAqmIfQueUppStat0RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET; - - /* AQM Q upper-group (32-63) Full status register address */ - ixQMgrAqmIfQueUppStat1RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET; -} - -/* - * Uninitialise the AqmIf module by unmapping memory, etc - */ -void -ixQMgrAqmIfUninit (void) -{ - UINT32 virtAddr; - - ixQMgrAqmIfBaseAddressGet (&virtAddr); - IX_OSAL_MEM_UNMAP (virtAddr); - ixQMgrAqmIfBaseAddressSet (0); -} - -/* - * Set the the logical base address of AQM - */ -void -ixQMgrAqmIfBaseAddressSet (UINT32 address) -{ - aqmBaseAddress = address; -} - -/* - * Get the logical base address of AQM - */ -void -ixQMgrAqmIfBaseAddressGet (UINT32 *address) -{ - *address = aqmBaseAddress; -} - -/* - * Get the logical base address of AQM SRAM - */ -void -ixQMgrAqmIfSramBaseAddressGet (UINT32 *address) -{ - *address = aqmBaseAddress + - IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET; -} - -/* - * This function will write the status bits of a queue - * specified by qId. - */ -void -ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, - UINT32 registerBaseAddrOffset, - unsigned queuesPerRegWord, - UINT32 value) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 statusBitsMask; - UINT32 bitsPerQueue; - - bitsPerQueue = BITS_PER_WORD / queuesPerRegWord; - - /* - * Calculate the registerAddress - * multiple queues split accross registers - */ - registerAddress = (UINT32*)(aqmBaseAddress + - registerBaseAddrOffset + - ((qId / queuesPerRegWord) * - IX_QMGR_NUM_BYTES_PER_WORD)); - - /* Read the current data */ - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - - - if( (registerBaseAddrOffset == IX_QMGR_INT0SRCSELREG0_OFFSET) && - (qId == IX_QMGR_QUEUE_0) ) - { - statusBitsMask = 0x7 ; - - /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */ - value &= 0x7 ; - } - else - { - /* Calculate the mask for the status bits for this queue. */ - statusBitsMask = ((1 << bitsPerQueue) - 1); - statusBitsMask <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue); - - /* Mask out bits in value that would overwrite other q data */ - value <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue); - value &= statusBitsMask; - } - - /* Mask out bits to write to */ - registerWord &= ~statusBitsMask; - - - /* Set the write bits */ - registerWord |= value; - - /* - * Write the data - */ - ixQMgrAqmIfWordWrite (registerAddress, registerWord); -} - -/* - * This function generates the parameters that can be used to - * check if a Qs status matches the specified source select. - * It calculates which status word to check (statusWordOffset), - * the value to check the status against (checkValue) and the - * mask (mask) to mask out all but the bits to check in the status word. - */ -void -ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId, - IxQMgrSourceId srcSel, - unsigned int *statusWordOffset, - UINT32 *checkValue, - UINT32 *mask) -{ - UINT32 shiftVal; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - switch (srcSel) - { - case IX_QMGR_Q_SOURCE_ID_E: - *checkValue = IX_QMGR_Q_STATUS_E_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_E_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NE: - *checkValue = IX_QMGR_Q_STATUS_NE_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NF: - *checkValue = IX_QMGR_Q_STATUS_NF_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_F: - *checkValue = IX_QMGR_Q_STATUS_F_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_F_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_E: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_E_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NE: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NF: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_F: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_F_BIT_MASK; - break; - default: - /* Should never hit */ - IX_OSAL_ASSERT(0); - break; - } - - /* One nibble of status per queue so need to shift the - * check value and mask out to the correct position. - */ - shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_QUELOWSTAT_BITS_PER_Q; - - /* Calculate the which status word to check from the qId, - * 8 Qs status per word - */ - *statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD; - - *checkValue <<= shiftVal; - *mask <<= shiftVal; - } - else - { - /* One status word */ - *statusWordOffset = 0; - /* Single bits per queue and int source bit hardwired NE, - * Qs start at 32. - */ - *mask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID); - *checkValue = *mask; - } -} - -void -ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 actualBitOffset; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET); - } - else - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET); - } - - actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID); - - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - ixQMgrAqmIfWordWrite (registerAddress, (registerWord | actualBitOffset)); -} - -void -ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 actualBitOffset; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET); - } - else - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET); - } - - actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID); - - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset)); -} - -void -ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId, - IxQMgrQSizeInWords qSizeInWords, - IxQMgrQEntrySizeInWords entrySizeInWords, - UINT32 freeSRAMAddress) -{ - volatile UINT32 *cfgAddress = NULL; - UINT32 qCfg = 0; - UINT32 baseAddress = 0; - unsigned aqmEntrySize = 0; - unsigned aqmBufferSize = 0; - - /* Build config register */ - aqmEntrySize = entrySizeToAqmEntrySize (entrySizeInWords); - qCfg |= (aqmEntrySize&IX_QMGR_ENTRY_SIZE_MASK) << - IX_QMGR_Q_CONFIG_ESIZE_OFFSET; - - aqmBufferSize = bufferSizeToAqmBufferSize (qSizeInWords); - qCfg |= (aqmBufferSize&IX_QMGR_SIZE_MASK) << IX_QMGR_Q_CONFIG_BSIZE_OFFSET; - - /* baseAddress, calculated relative to aqmBaseAddress and start address */ - baseAddress = freeSRAMAddress - - (aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET); - - /* Verify base address aligned to a 16 word boundary */ - if ((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) != 0) - { - IX_QMGR_LOG_ERROR0("ixQMgrAqmIfQueCfgWrite () address is not on 16 word boundary\n"); - } - /* Now convert it to a 16 word pointer as required by QUECONFIG register */ - baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - - - qCfg |= (baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET); - - - cfgAddress = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - - - /* NOTE: High and Low watermarks are set to zero */ - ixQMgrAqmIfWordWrite (cfgAddress, qCfg); -} - -void -ixQMgrAqmIfQueCfgRead (IxQMgrQId qId, - unsigned int numEntries, - UINT32 *baseAddress, - unsigned int *ne, - unsigned int *nf, - UINT32 *readPtr, - UINT32 *writePtr) -{ - UINT32 qcfg; - UINT32 *cfgAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - UINT32 *readPtr_ = NULL; - - /* Read the queue configuration register */ - ixQMgrAqmIfWordRead (cfgAddress, &qcfg); - - /* Extract the base address */ - *baseAddress = (UINT32)((qcfg & IX_QMGR_BADDR_MASK) >> - (IX_QMGR_Q_CONFIG_BADDR_OFFSET)); - - /* Base address is a 16 word pointer from the start of AQM SRAM. - * Convert to absolute word address. - */ - *baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - *baseAddress += (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET; - - /* - * Extract the watermarks. 0->0 entries, 1->1 entries, 2->2 entries, 3->4 entries...... - * If ne > 0 ==> neInEntries = 2^(ne - 1) - * If ne == 0 ==> neInEntries = 0 - * The same applies. - */ - *ne = ((qcfg) >> (IX_QMGR_Q_CONFIG_NE_OFFSET)) & IX_QMGR_NE_MASK; - *nf = ((qcfg) >> (IX_QMGR_Q_CONFIG_NF_OFFSET)) & IX_QMGR_NF_MASK; - - if (0 != *ne) - { - *ne = 1 << (*ne - 1); - } - if (0 != *nf) - { - *nf = 1 << (*nf - 1); - } - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - ixQMgrAqmIfEntryAddressGet (0/* Entry 0. i.e the readPtr*/, - qcfg, - qEntrySizeInwords, - qSizeInWords, - &readPtr_); - *readPtr = (UINT32)readPtr_; - *readPtr -= (UINT32)aqmBaseAddress;/* Offset, not absolute address */ - - *writePtr = (qcfg >> IX_QMGR_Q_CONFIG_WRPTR_OFFSET) & IX_QMGR_WRPTR_MASK; - *writePtr = *baseAddress + (*writePtr * (IX_QMGR_NUM_BYTES_PER_WORD)); - return; -} - -unsigned -ixQMgrAqmIfLog2 (unsigned number) -{ - unsigned count = 0; - - /* - * N.B. this function will return 0 - * for ixQMgrAqmIfLog2 (0) - */ - while (number/2) - { - number /=2; - count++; - } - - return count; -} - -void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void) -{ - - volatile UINT32 *registerAddress; - UINT32 registerWord; - - /* - * Calculate the registerAddress - * multiple queues split accross registers - */ - registerAddress = (UINT32*)(aqmBaseAddress + - IX_QMGR_INT0SRCSELREG0_OFFSET); - - /* Read the current data */ - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - - /* Set the write bits */ - registerWord |= (1<> - (IX_QMGR_Q_CONFIG_BADDR_OFFSET)); - - /* Base address is a 16 word pointer from the start of AQM SRAM. - * Convert to absolute word address. - */ - baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - baseAddress += ((UINT32)aqmBaseAddress + (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET); - - /* Extract the read pointer. Read pointer is a word pointer */ - readPtr = (UINT32)((configRegWord >> - IX_QMGR_Q_CONFIG_RDPTR_OFFSET)&IX_QMGR_RDPTR_MASK); - - /* Read/Write pointers(word pointers) are offsets from the queue buffer space base address. - * Calculate the absolute read pointer address. NOTE: Queues are circular buffers. - */ - readPtr = (readPtr + (entryIndex * qEntrySizeInwords)) & (qSizeInWords - 1); /* Mask by queue size */ - *address = (UINT32 *)(baseAddress + (readPtr * (IX_QMGR_NUM_BYTES_PER_WORD))); - - switch (qEntrySizeInwords) - { - case IX_QMGR_Q_ENTRY_SIZE1: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY1_OFFSET) < topOfAqmSram); - break; - case IX_QMGR_Q_ENTRY_SIZE2: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY2_OFFSET) < topOfAqmSram); - break; - case IX_QMGR_Q_ENTRY_SIZE4: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY4_OFFSET) < topOfAqmSram); - break; - default: - IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfEntryAddressGet"); - break; - } - -} - -IX_STATUS -ixQMgrAqmIfQPeek (IxQMgrQId qId, - unsigned int entryIndex, - unsigned int *entry) -{ - UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - UINT32 *entryAddress = NULL; - UINT32 configRegWordOnEntry; - UINT32 configRegWordOnExit; - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry); - - /* Get the entry address */ - ixQMgrAqmIfEntryAddressGet (entryIndex, - configRegWordOnEntry, - qEntrySizeInwords, - qSizeInWords, - &entryAddress); - - /* Get the lock or return busy */ - if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId])) - { - return IX_FAIL; - } - - while(qEntrySizeInwords--) - { - ixQMgrAqmIfWordRead (entryAddress++, entry++); - } - - /* Release the lock */ - ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit); - - /* Check that the read and write pointers have not changed */ - if (configRegWordOnEntry != configRegWordOnExit) - { - return IX_FAIL; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrAqmIfQPoke (IxQMgrQId qId, - unsigned entryIndex, - unsigned int *entry) -{ - UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - UINT32 *entryAddress = NULL; - UINT32 configRegWordOnEntry; - UINT32 configRegWordOnExit; - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry); - - /* Get the entry address */ - ixQMgrAqmIfEntryAddressGet (entryIndex, - configRegWordOnEntry, - qEntrySizeInwords, - qSizeInWords, - &entryAddress); - - /* Get the lock or return busy */ - if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId])) - { - return IX_FAIL; - } - - /* Else read the entry directly from SRAM. This will not move the read pointer */ - while(qEntrySizeInwords--) - { - ixQMgrAqmIfWordWrite (entryAddress++, *entry++); - } - - /* Release the lock */ - ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit); - - /* Check that the read and write pointers have not changed */ - if (configRegWordOnEntry != configRegWordOnExit) - { - return IX_FAIL; - } - - return IX_SUCCESS; -} - -PRIVATE unsigned -watermarkToAqmWatermark (IxQMgrWMLevel watermark ) -{ - unsigned aqmWatermark = 0; - - /* - * Watermarks 0("000"),1("001"),2("010"),4("011"), - * 8("100"),16("101"),32("110"),64("111") - */ - aqmWatermark = ixQMgrAqmIfLog2 (watermark * 2); - - return aqmWatermark; -} - -PRIVATE unsigned -entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize) -{ - /* entrySize 1("00"),2("01"),4("10") */ - return (ixQMgrAqmIfLog2 (entrySize)); -} - -PRIVATE unsigned -bufferSizeToAqmBufferSize (unsigned bufferSizeInWords) -{ - /* bufferSize 16("00"),32("01),64("10"),128("11") */ - return (ixQMgrAqmIfLog2 (bufferSizeInWords / IX_QMGR_MIN_BUFFER_SIZE)); -} - -/* - * Reset AQM registers to default values. - */ -PRIVATE void -ixQMgrAqmIfRegistersReset (void) -{ - volatile UINT32 *qConfigWordAddress = NULL; - unsigned int i; - - /* - * Need to initialize AQM hardware registers to an initial - * value as init may have been called as a result of a soft - * reset. i.e. soft reset does not reset hardware registers. - */ - - /* Reset queues 0..31 status registers 0..3 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT0_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT1_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT2_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT3_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - - /* Reset underflow/overflow status registers 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT0_OFFSET), - IX_QMGR_QUEUOSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT1_OFFSET), - IX_QMGR_QUEUOSTAT_RESET_VALUE); - - /* Reset queues 32..63 nearly empty status registers */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET), - IX_QMGR_QUEUPPSTAT0_RESET_VALUE); - - /* Reset queues 32..63 full status registers */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET), - IX_QMGR_QUEUPPSTAT1_RESET_VALUE); - - /* Reset int0 status flag source select registers 0..3 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG0_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG1_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG2_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG3_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - - /* Reset queue interrupt enable register 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET), - IX_QMGR_QUEIEREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET), - IX_QMGR_QUEIEREG_RESET_VALUE); - - /* Reset queue interrupt register 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG0_OFFSET), - IX_QMGR_QINTREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG1_OFFSET), - IX_QMGR_QINTREG_RESET_VALUE); - - /* Reset queue configuration words 0..63 */ - qConfigWordAddress = (UINT32 *)(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET); - for (i = 0; i < (IX_QMGR_QUECONFIG_SIZE / sizeof(UINT32)); i++) - { - ixQMgrAqmIfWordWrite(qConfigWordAddress, - IX_QMGR_QUECONFIG_RESET_VALUE); - /* Next word */ - qConfigWordAddress++; - } -} - diff --git a/drivers/net/npe/IxQMgrDispatcher.c b/drivers/net/npe/IxQMgrDispatcher.c deleted file mode 100644 index 25a3e8539e..0000000000 --- a/drivers/net/npe/IxQMgrDispatcher.c +++ /dev/null @@ -1,1344 +0,0 @@ -/** - * @file IxQMgrDispatcher.c - * - * @author Intel Corporation - * @date 20-Dec-2001 - * - * @brief This file contains the implementation of the Dispatcher sub component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * User defined include files. - */ -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDispatcher_p.h" -#include "IxQMgrLog_p.h" -#include "IxQMgrDefines_p.h" -#include "IxFeatureCtrl.h" -#include "IxOsal.h" - - - -/* - * #defines and macros used in this file. - */ - - -/* - * This constant is used to indicate the number of priority levels supported - */ -#define IX_QMGR_NUM_PRIORITY_LEVELS 3 - -/* - * This constant is used to set the size of the array of status words - */ -#define MAX_Q_STATUS_WORDS 4 - -/* - * This macro is used to check if a given priority is valid - */ -#define IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority) \ -(((priority) >= IX_QMGR_Q_PRIORITY_0) && ((priority) <= IX_QMGR_Q_PRIORITY_2)) - -/* - * This macto is used to check that a given interrupt source is valid - */ -#define IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel) \ -(((srcSel) >= IX_QMGR_Q_SOURCE_ID_E) && ((srcSel) <= IX_QMGR_Q_SOURCE_ID_NOT_F)) - -/* - * Number of times a dummy callback is called before logging a trace - * message - */ -#define LOG_THROTTLE_COUNT 1000000 - -/* Priority tables limits */ -#define IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX (0) -#define IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX (16) -#define IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX (31) -#define IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX (32) -#define IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX (48) -#define IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX (63) - -/* - * This macro is used to check if a given callback type is valid - */ -#define IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type) \ - (((type) >= IX_QMGR_TYPE_REALTIME_OTHER) && \ - ((type) <= IX_QMGR_TYPE_REALTIME_SPORADIC)) - -/* - * define max index in lower queue to use in loops - */ -#define IX_QMGR_MAX_LOW_QUE_TABLE_INDEX (31) - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * Information on a queue needed by the Dispatcher - */ -typedef struct -{ - IxQMgrCallback callback; /* Notification callback */ - IxQMgrCallbackId callbackId; /* Notification callback identifier */ - unsigned dummyCallbackCount; /* Number of times runs of dummy callback */ - IxQMgrPriority priority; /* Dispatch priority */ - unsigned int statusWordOffset; /* Offset to the status word to check */ - UINT32 statusMask; /* Status mask */ - UINT32 statusCheckValue; /* Status check value */ - UINT32 intRegCheckMask; /* Interrupt register check mask */ -} IxQMgrQInfo; - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ - -/* - * Flag to keep record of what dispatcher set in featureCtrl when ixQMgrInit() - * is called. This is needed because it is possible that a client might - * change whether the live lock prevention dispatcher is used between - * calls to ixQMgrInit() and ixQMgrDispatcherLoopGet(). - */ -PRIVATE IX_STATUS ixQMgrOrigB0Dispatcher = IX_FEATURE_CTRL_COMPONENT_ENABLED; - -/* - * keep record of Q types - not in IxQMgrQInfo for performance as - * it is only used with ixQMgrDispatcherLoopRunB0LLP() - */ -PRIVATE IxQMgrType ixQMgrQTypes[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * This array contains a list of queue identifiers ordered by priority. The table - * is split logically between queue identifiers 0-31 and 32-63. - */ -static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * This flag indicates to the dispatcher that the priority table needs to be rebuilt. - */ -static BOOL rebuildTable = false; - -/* Dispatcher statistics */ -static IxQMgrDispatcherStats dispatcherStats; - -/* Table of queue information */ -static IxQMgrQInfo dispatchQInfo[IX_QMGR_MAX_NUM_QUEUES]; - -/* Masks use to identify the first queues in the priority tables -* when comparing with the interrupt register -*/ -static unsigned int lowPriorityTableFirstHalfMask; -static unsigned int uppPriorityTableFirstHalfMask; - -/* - * Static function prototypes - */ - -/* - * This function is the default callback for all queues - */ -PRIVATE void -dummyCallback (IxQMgrQId qId, - IxQMgrCallbackId cbId); - -PRIVATE void -ixQMgrDispatcherReBuildPriorityTable (void); - -/* - * Function definitions. - */ -void -ixQMgrDispatcherInit (void) -{ - int i; - IxFeatureCtrlProductId productId = 0; - IxFeatureCtrlDeviceId deviceId = 0; - BOOL stickyIntSilicon = true; - - /* Set default priorities */ - for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++) - { - dispatchQInfo[i].callback = dummyCallback; - dispatchQInfo[i].callbackId = 0; - dispatchQInfo[i].dummyCallbackCount = 0; - dispatchQInfo[i].priority = IX_QMGR_Q_PRIORITY_2; - dispatchQInfo[i].statusWordOffset = 0; - dispatchQInfo[i].statusCheckValue = 0; - dispatchQInfo[i].statusMask = 0; - /* - * There are two interrupt registers, 32 bits each. One for the lower - * queues(0-31) and one for the upper queues(32-63). Therefore need to - * mod by 32 i.e the min upper queue identifier. - */ - dispatchQInfo[i].intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID))); - - /* - * Set the Q types - will only be used with livelock - */ - ixQMgrQTypes[i] = IX_QMGR_TYPE_REALTIME_OTHER; - - /* Reset queue statistics */ - dispatcherStats.queueStats[i].callbackCnt = 0; - dispatcherStats.queueStats[i].priorityChangeCnt = 0; - dispatcherStats.queueStats[i].intNoCallbackCnt = 0; - dispatcherStats.queueStats[i].intLostCallbackCnt = 0; - dispatcherStats.queueStats[i].notificationEnabled = false; - dispatcherStats.queueStats[i].srcSel = 0; - - } - - /* Priority table. Order the table from queue 0 to 63 */ - ixQMgrDispatcherReBuildPriorityTable(); - - /* Reset statistics */ - dispatcherStats.loopRunCnt = 0; - - /* Get the device ID for the underlying silicon */ - deviceId = ixFeatureCtrlDeviceRead(); - - /* Get the product ID for the underlying silicon */ - productId = ixFeatureCtrlProductIdRead(); - - /* - * Check featureCtrl to see if Livelock prevention is required - */ - ixQMgrOrigB0Dispatcher = ixFeatureCtrlSwConfigurationCheck( - IX_FEATURECTRL_ORIGB0_DISPATCHER); - - /* - * Check if the silicon supports the sticky interrupt feature. - * IF (IXP42X AND A0) -> No sticky interrupt feature supported - */ - if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X == - (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) && - (IX_FEATURE_CTRL_SILICON_TYPE_A0 == - (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) - { - stickyIntSilicon = false; - } - - /* - * IF user wants livelock prev option AND silicon supports sticky interrupt - * feature -> enable the sticky interrupt bit - */ - if ((IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixQMgrOrigB0Dispatcher) && - stickyIntSilicon) - { - ixQMgrStickyInterruptRegEnable(); - } -} - -IX_STATUS -ixQMgrDispatcherPrioritySet (IxQMgrQId qId, - IxQMgrPriority priority) -{ - int ixQMgrLockKey; - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (!IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority)) - { - return IX_QMGR_Q_INVALID_PRIORITY; - } - - ixQMgrLockKey = ixOsalIrqLock(); - - /* Change priority */ - dispatchQInfo[qId].priority = priority; - /* Set flag */ - rebuildTable = true; - - ixOsalIrqUnlock(ixQMgrLockKey); - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qId].priorityChangeCnt++; -#endif - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrNotificationCallbackSet (IxQMgrQId qId, - IxQMgrCallback callback, - IxQMgrCallbackId callbackId) -{ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (NULL == callback) - { - /* Reset to dummy callback */ - dispatchQInfo[qId].callback = dummyCallback; - dispatchQInfo[qId].dummyCallbackCount = 0; - dispatchQInfo[qId].callbackId = 0; - } - else - { - dispatchQInfo[qId].callback = callback; - dispatchQInfo[qId].callbackId = callbackId; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrNotificationEnable (IxQMgrQId qId, - IxQMgrSourceId srcSel) -{ - IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */ - IxQMgrQStatus qStatusOnExit; /* to this function */ - int ixQMgrLockKey; - -#ifndef NDEBUG - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if ((qId < IX_QMGR_MIN_QUEUPP_QID) && - !IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel)) - { - /* QId 0-31 source id invalid */ - return IX_QMGR_INVALID_INT_SOURCE_ID; - } - - if ((IX_QMGR_Q_SOURCE_ID_NE != srcSel) && - (qId >= IX_QMGR_MIN_QUEUPP_QID)) - { - /* - * For queues 32-63 the interrupt source is fixed to the Nearly - * Empty status flag and therefore should have a srcSel of NE. - */ - return IX_QMGR_INVALID_INT_SOURCE_ID; - } -#endif - -#ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = true; - dispatcherStats.queueStats[qId].srcSel = srcSel; -#endif - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry); - - /* - * Enabling interrupts results in Read-Modify-Write - * so need critical section - */ - - ixQMgrLockKey = ixOsalIrqLock(); - - /* Calculate the checkMask and checkValue for this q */ - ixQMgrAqmIfQStatusCheckValsCalc (qId, - srcSel, - &dispatchQInfo[qId].statusWordOffset, - &dispatchQInfo[qId].statusCheckValue, - &dispatchQInfo[qId].statusMask); - - - /* Set the interrupt source is this queue is in the range 0-31 */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - ixQMgrAqmIfIntSrcSelWrite (qId, srcSel); - } - - /* Enable the interrupt */ - ixQMgrAqmIfQInterruptEnable (qId); - - ixOsalIrqUnlock(ixQMgrLockKey); - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit); - - /* If the status has changed return a warning */ - if (qStatusOnEntry != qStatusOnExit) - { - return IX_QMGR_WARNING; - } - - return IX_SUCCESS; -} - - -IX_STATUS -ixQMgrNotificationDisable (IxQMgrQId qId) -{ - int ixQMgrLockKey; - -#ifndef NDEBUG - /* Validate parameters */ - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - /* - * Enabling interrupts results in Read-Modify-Write - * so need critical section - */ -#ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = false; -#endif - - ixQMgrLockKey = ixOsalIrqLock(); - - ixQMgrAqmIfQInterruptDisable (qId); - - ixOsalIrqUnlock(ixQMgrLockKey); - - return IX_SUCCESS; -} - -void -ixQMgrStickyInterruptRegEnable(void) -{ - /* Use Aqm If function to set Interrupt Register0 Bit-3 */ - ixQMgrAqmIfIntSrcSelReg0Bit3Set (); -} - -#if !defined __XSCALE__ || defined __linux - -/* Count the number of leading zero bits in a word, - * and return the same value than the CLZ instruction. - * - * word (in) return value (out) - * 0x80000000 0 - * 0x40000000 1 - * ,,, ,,, - * 0x00000002 30 - * 0x00000001 31 - * 0x00000000 32 - * - * The C version of this function is used as a replacement - * for system not providing the equivalent of the CLZ - * assembly language instruction. - * - * Note that this version is big-endian - */ -unsigned int -ixQMgrCountLeadingZeros(UINT32 word) -{ - unsigned int leadingZerosCount = 0; - - if (word == 0) - { - return 32; - } - /* search the first bit set by testing the MSB and shifting the input word */ - while ((word & 0x80000000) == 0) - { - word <<= 1; - leadingZerosCount++; - } - return leadingZerosCount; -} -#endif /* not __XSCALE__ or __linux */ - -void -ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr) -{ - IxFeatureCtrlProductId productId = 0; - IxFeatureCtrlDeviceId deviceId = 0; - - /* Get the device ID for the underlying silicon */ - deviceId = ixFeatureCtrlDeviceRead(); - - /* Get the product ID for the underlying silicon */ - productId = ixFeatureCtrlProductIdRead (); - - /* IF (IXP42X AND A0 silicon) -> use ixQMgrDispatcherLoopRunA0 */ - if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X == - (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) && - (IX_FEATURE_CTRL_SILICON_TYPE_A0 == - (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) - { - /*For IXP42X A0 silicon */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunA0 ; - } - else /*For IXP42X B0 or IXP46X silicon*/ - { - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixQMgrOrigB0Dispatcher) - { - /* Default for IXP42X B0 and IXP46X silicon */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0; - } - else - { - /* FeatureCtrl indicated that livelock dispatcher be used */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0LLP; - } - } -} - -void -ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal; /* Interrupt reg val */ - UINT32 intRegValAfterWrite; /* Interrupt reg val after writing back */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - UINT32 qStatusWordsB4Write[MAX_Q_STATUS_WORDS]; /* Status b4 interrupt write */ - UINT32 qStatusWordsAfterWrite[MAX_Q_STATUS_WORDS]; /* Status after interrupt write */ - IxQMgrQInfo *currDispatchQInfo; - BOOL statusChangeFlag; - - int priorityTableIndex;/* Priority table index */ - int qIndex; /* Current queue being processed */ - int endIndex; /* Index of last queue to process */ - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read Q status registers before interrupt status read/write */ - ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsB4Write); - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - /* No bit set : nothing to process (the reaminder of the algorithm is - * based on the fact that the interrupt register value contains at - * least one bit set - */ - if (intRegVal == 0) - { -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } - - return; - } - - /* Write it back to clear the interrupt */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - - /* Read Q status registers after interrupt status read/write */ - ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsAfterWrite); - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - /* check if any change occured during hw register modifications */ - if (IX_QMGR_QUELOW_GROUP == group) - { - statusChangeFlag = - (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]) || - (qStatusWordsB4Write[1] != qStatusWordsAfterWrite[1]) || - (qStatusWordsB4Write[2] != qStatusWordsAfterWrite[2]) || - (qStatusWordsB4Write[3] != qStatusWordsAfterWrite[3]); - } - else - { - statusChangeFlag = - (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]); - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - if (statusChangeFlag == false) - { - /* check if the interrupt register contains - * only 1 bit set (happy day scenario) - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - /* only 1 queue event triggered a notification * - * Call the callback function for this queue - */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } - } - else - { - /* A change in queue status occured during the hw interrupt - * register update. To maintain the interrupt consistency, it - * is necessary to iterate through all queues of the queue group. - */ - - /* Read interrupt status again */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegValAfterWrite); - - if (IX_QMGR_QUELOW_GROUP == group) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - endIndex = IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - endIndex = IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX; - } - - for ( ; priorityTableIndex<=endIndex; priorityTableIndex++) - { - qIndex = priorityTable[priorityTableIndex]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - } /* if (intRegVal .. */ - - /* - * If interrupt bit is set in intRegValAfterWrite don't - * proceed as this will be caught in next interrupt - */ - else if ((intRegValAfterWrite & intRegCheckMask) == 0) - { - /* Check if an interrupt was lost for this Q */ - if (ixQMgrAqmIfQStatusCheck(qStatusWordsB4Write, - qStatusWordsAfterWrite, - currDispatchQInfo->statusWordOffset, - currDispatchQInfo->statusCheckValue, - currDispatchQInfo->statusMask)) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - dispatchQInfo[qIndex].callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; - dispatcherStats.queueStats[qIndex].intLostCallbackCnt++; -#endif - } /* if ixQMgrAqmIfQStatusCheck(.. */ - } /* else if ((intRegValAfterWrite ... */ - } /* for (priorityTableIndex=0 ... */ - } - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif -} - - - -void -ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal; /* Interrupt reg val */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - IxQMgrQInfo *currDispatchQInfo; - - - int priorityTableIndex; /* Priority table index */ - int qIndex; /* Current queue being processed */ - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - - /* No queue has interrupt register set */ - if (intRegVal != 0) - { - - /* Write it back to clear the interrupt */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - if (IX_QMGR_QUEUPP_GROUP == group) - { - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - /* check if the interrupt register contains - * only 1 bit set - * For example: - * intRegVal = 0x0010 - * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is true. - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - /* only 1 queue event triggered a notification * - * Call the callback function for this queue - */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */ - } /* End of intRegVal != 0 */ - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } -} - -void -ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal =0; /* Interrupt reg val */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - IxQMgrQInfo *currDispatchQInfo; - - int priorityTableIndex; /* Priority table index */ - int qIndex; /* Current queue being processed */ - - UINT32 intRegValCopy = 0; - UINT32 intEnableRegVal = 0; - UINT8 i = 0; - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - /* - * mask any interrupts that are not enabled - */ - ixQMgrAqmIfQInterruptEnableRegRead (group, &intEnableRegVal); - intRegVal &= intEnableRegVal; - - /* No queue has interrupt register set */ - if (intRegVal != 0) - { - if (IX_QMGR_QUELOW_GROUP == group) - { - /* - * As the sticky bit is set, the interrupt register will - * not clear if write back at this point because the condition - * has not been cleared. Take a copy and write back later after - * the condition has been cleared - */ - intRegValCopy = intRegVal; - } - else - { - /* no sticky for upper Q's, so write back now */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - } - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - if (IX_QMGR_QUEUPP_GROUP == group) - { - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - /* check if the interrupt register contains - * only 1 bit set - * For example: - * intRegVal = 0x0010 - * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is true. - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - - /* - * check if Q type periodic - only lower queues can - * have there type set to periodic - */ - if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex]) - { - /* - * Disable the notifications on any sporadics - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i]) - { - ixQMgrNotificationDisable(i); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[i].disableCount++; -#endif - } - } - } - - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = - IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = - IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = - IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = - IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* - * check if Q type periodic - only lower queues can - * have there type set to periodic. There can only be one - * periodic queue, so the sporadics are only disabled once. - */ - if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex]) - { - /* - * Disable the notifications on any sporadics - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (IX_QMGR_TYPE_REALTIME_SPORADIC == - ixQMgrQTypes[i]) - { - ixQMgrNotificationDisable(i); - /* - * remove from intRegVal as we don't want - * to service any sporadics now - */ - intRegVal &= ~dispatchQInfo[i].intRegCheckMask; -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[i].disableCount++; -#endif - } - } - } - - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */ - } /* End of intRegVal != 0 */ - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - if ((intRegValCopy != 0) && (IX_QMGR_QUELOW_GROUP == group)) - { - /* - * lower groups (therefore sticky) AND at least one enabled interrupt - * Write back to clear the interrupt - */ - ixQMgrAqmIfQInterruptRegWrite (IX_QMGR_QUELOW_GROUP, intRegValCopy); - } - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } -} - -PRIVATE void -ixQMgrDispatcherReBuildPriorityTable (void) -{ - UINT32 qIndex; - UINT32 priority; - int lowQuePriorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - - /* Reset the rebuild flag */ - rebuildTable = false; - - /* initialize the mak used to identify the queues in the first half - * of the priority table - */ - lowPriorityTableFirstHalfMask = 0; - uppPriorityTableFirstHalfMask = 0; - - /* For each priority level */ - for(priority=0; priority dummyCallback: qId (%d), callbackId (%d)\n",qId,cbId); - } - dispatchQInfo[qId].dummyCallbackCount++; - -#ifndef NDEBUG - /* Update statistcs */ - dispatcherStats.queueStats[qId].intNoCallbackCnt++; -#endif -} -void -ixQMgrLLPShow (int resetStats) -{ -#ifndef NDEBUG - UINT8 i = 0; - UINT32 intEnableRegVal = 0; - - printf ("Livelock statistics are printed on the fly.\n"); - printf ("qId Type EnableCnt DisableCnt IntEnableState Callbacks\n"); - printf ("=== ======== ========= ========== ============== =========\n"); - - for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER) - { - printf (" %2d ", i); - - if (ixQMgrQTypes[i] == IX_QMGR_TYPE_REALTIME_SPORADIC) - { - printf ("Sporadic"); - } - else - { - printf ("Periodic"); - } - - - ixQMgrAqmIfQInterruptEnableRegRead (IX_QMGR_QUELOW_GROUP, - &intEnableRegVal); - - - intEnableRegVal &= dispatchQInfo[i].intRegCheckMask; - intEnableRegVal = intEnableRegVal >> i; - - printf (" %10d %10d %10d %10d\n", - dispatcherStats.queueStats[i].enableCount, - dispatcherStats.queueStats[i].disableCount, - intEnableRegVal, - dispatcherStats.queueStats[i].callbackCnt); - - if (resetStats) - { - dispatcherStats.queueStats[i].enableCount = - dispatcherStats.queueStats[i].disableCount = - dispatcherStats.queueStats[i].callbackCnt = 0; - } - } - } -#else - IX_QMGR_LOG0("Livelock Prevention statistics are only collected in debug mode\n"); -#endif -} - -void -ixQMgrPeriodicDone (void) -{ - UINT32 i = 0; - UINT32 ixQMgrLockKey = 0; - - /* - * for the lower queues - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - /* - * check for sporadics - */ - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i]) - { - /* - * enable any sporadics - */ - ixQMgrLockKey = ixOsalIrqLock(); - ixQMgrAqmIfQInterruptEnable(i); - ixOsalIrqUnlock(ixQMgrLockKey); -#ifndef NDEBUG - /* - * Update statistics - */ - dispatcherStats.queueStats[i].enableCount++; - dispatcherStats.queueStats[i].notificationEnabled = true; -#endif - } - } -} -IX_STATUS -ixQMgrCallbackTypeSet (IxQMgrQId qId, - IxQMgrType type) -{ - UINT32 ixQMgrLockKey = 0; - IxQMgrType ixQMgrOldType =0; - -#ifndef NDEBUG - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - if (qId >= IX_QMGR_MIN_QUEUPP_QID) - { - return IX_QMGR_PARAMETER_ERROR; - } - if(!IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type)) - { - return IX_QMGR_PARAMETER_ERROR; - } -#endif - - ixQMgrOldType = ixQMgrQTypes[qId]; - ixQMgrQTypes[qId] = type; - - /* - * check if Q has been changed from type SPORADIC - */ - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrOldType) - { - /* - * previously Q was a SPORADIC, this means that LLP - * might have had it disabled. enable it now. - */ - ixQMgrLockKey = ixOsalIrqLock(); - ixQMgrAqmIfQInterruptEnable(qId); - ixOsalIrqUnlock(ixQMgrLockKey); - -#ifndef NDEBUG - /* - * Update statistics - */ - dispatcherStats.queueStats[qId].enableCount++; -#endif - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrCallbackTypeGet (IxQMgrQId qId, - IxQMgrType *type) -{ -#ifndef NDEBUG - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - if (qId >= IX_QMGR_MIN_QUEUPP_QID) - { - return IX_QMGR_PARAMETER_ERROR; - } - if(type == NULL) - { - return IX_QMGR_PARAMETER_ERROR; - } -#endif - - *type = ixQMgrQTypes[qId]; - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxQMgrInit.c b/drivers/net/npe/IxQMgrInit.c deleted file mode 100644 index 61ca96c977..0000000000 --- a/drivers/net/npe/IxQMgrInit.c +++ /dev/null @@ -1,233 +0,0 @@ -/** - * @file IxQMgrInit.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief: Provided initialization of the QMgr component and its subcomponents. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDispatcher_p.h" -#include "IxQMgrLog_p.h" -#include "IxQMgrQAccess_p.h" -#include "IxQMgrDefines_p.h" -#include "IxQMgrAqmIf_p.h" - -/* - * Set to true if initialized - * N.B. global so integration/unit tests can reinitialize - */ -BOOL qMgrIsInitialized = false; - -/* - * Function definitions. - */ -IX_STATUS -ixQMgrInit (void) -{ - if (qMgrIsInitialized) - { - IX_QMGR_LOG0("ixQMgrInit: IxQMgr already initialised\n"); - return IX_FAIL; - } - - /* Initialise the QCfg component */ - ixQMgrQCfgInit (); - - /* Initialise the Dispatcher component */ - ixQMgrDispatcherInit (); - - /* Initialise the Access component */ - ixQMgrQAccessInit (); - - /* Initialization complete */ - qMgrIsInitialized = true; - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrUnload (void) -{ - if (!qMgrIsInitialized) - { - return IX_FAIL; - } - - /* Uninitialise the QCfg component */ - ixQMgrQCfgUninit (); - - /* Uninitialization complete */ - qMgrIsInitialized = false; - - return IX_SUCCESS; -} - -void -ixQMgrShow (void) -{ - IxQMgrQCfgStats *qCfgStats = NULL; - IxQMgrDispatcherStats *dispatcherStats = NULL; - int i; - UINT32 lowIntRegRead, upIntRegRead; - - qCfgStats = ixQMgrQCfgStatsGet (); - dispatcherStats = ixQMgrDispatcherStatsGet (); - ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUELOW_GROUP, &lowIntRegRead); - ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUEUPP_GROUP, &upIntRegRead); - printf("Generic Stats........\n"); - printf("=====================\n"); - printf("Loop Run Count..........%u\n",dispatcherStats->loopRunCnt); - printf("Watermark set count.....%d\n", qCfgStats->wmSetCnt); - printf("===========================================\n"); - printf("On the fly Interrupt Register Stats........\n"); - printf("===========================================\n"); - printf("Lower Interrupt Register............0x%08x\n",lowIntRegRead); - printf("Upper Interrupt Register............0x%08x\n",upIntRegRead); - printf("==============================================\n"); - printf("Queue Specific Stats........\n"); - printf("============================\n"); - - for (i=0; iqStats[qId].qName); - printf(" Size in words............ %u\n", qCfgStats->qStats[qId].qSizeInWords); - printf(" Entry size in words...... %u\n", qCfgStats->qStats[qId].qEntrySizeInWords); - printf(" Nearly empty watermark... %u\n", qCfgStats->qStats[qId].ne); - printf(" Nearly full watermark.... %u\n", qCfgStats->qStats[qId].nf); - printf(" Number of full entries... %u\n", qCfgStats->qStats[qId].numEntries); - printf(" Sram base address........ 0x%X\n", qCfgStats->qStats[qId].baseAddress); - printf(" Read pointer............. 0x%X\n", qCfgStats->qStats[qId].readPtr); - printf(" Write pointer............ 0x%X\n", qCfgStats->qStats[qId].writePtr); - -#ifndef NDEBUG - if (dispatcherStats->queueStats[qId].notificationEnabled) - { - char *localEvent = "none ????"; - switch (dispatcherStats->queueStats[qId].srcSel) - { - case IX_QMGR_Q_SOURCE_ID_E: - localEvent = "Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NE: - localEvent = "Nearly Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NF: - localEvent = "Nearly Full"; - break; - case IX_QMGR_Q_SOURCE_ID_F: - localEvent = "Full"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_E: - localEvent = "Not Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NE: - localEvent = "Not Nearly Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NF: - localEvent = "Not Nearly Full"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_F: - localEvent = "Not Full"; - break; - default : - break; - } - printf(" Notifications localEvent...... %s\n", localEvent); - } - else - { - printf(" Notifications............ not enabled\n"); - } - printf(" IxQMgrDispatcher Stats\n"); - printf(" Callback count................%d\n", - dispatcherStats->queueStats[qId].callbackCnt); - printf(" Priority change count.........%d\n", - dispatcherStats->queueStats[qId].priorityChangeCnt); - printf(" Interrupt no callback count...%d\n", - dispatcherStats->queueStats[qId].intNoCallbackCnt); - printf(" Interrupt lost callback count...%d\n", - dispatcherStats->queueStats[qId].intLostCallbackCnt); -#endif - - return IX_SUCCESS; -} - - - - diff --git a/drivers/net/npe/IxQMgrQAccess.c b/drivers/net/npe/IxQMgrQAccess.c deleted file mode 100644 index 8885736246..0000000000 --- a/drivers/net/npe/IxQMgrQAccess.c +++ /dev/null @@ -1,796 +0,0 @@ -/** - * @file IxQMgrQAccess.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This file contains functions for putting entries on a queue and - * removing entries from a queue. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Inlines are compiled as function when this is defined. - * N.B. Must be placed before #include of "IxQMgr.h" - */ -#ifndef IXQMGR_H -# define IXQMGRQACCESS_C -#else -# error -#endif - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQAccess_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDefines_p.h" - -/* - * Global variables and extern definitions - */ -extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - -/* - * Function definitions. - */ -void -ixQMgrQAccessInit (void) -{ -} - -IX_STATUS -ixQMgrQReadWithChecks (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQEntrySizeInWords entrySizeInWords; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - if (NULL == entry) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - /* Get the q entry size in words */ - entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId); - - ixQMgrAqmIfQPop (qId, entrySizeInWords, entry); - - /* reset the current read count if the counter wrapped around - * (unsigned arithmetic) - */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - if (infoPtr->qReadCount-- > infoPtr->qSizeInEntries) - { - infoPtr->qReadCount = 0; - } - - /* Check if underflow occurred on the read */ - if (ixQMgrAqmIfUnderflowCheck (qId)) - { - return IX_QMGR_Q_UNDERFLOW; - } - - return IX_SUCCESS; -} - -/* this function reads the remaining of the q entry - * for queues configured with many words. - * (the first word of the entry is already read - * in the inlined function and the entry pointer already - * incremented - */ -IX_STATUS -ixQMgrQReadMWordsMinus1 (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entrySize = infoPtr->qEntrySizeInWords; - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - - while (--entrySize) - { - /* read the entry and accumulate the result */ - *(++entry) = IX_OSAL_READ_LONG(++qAccRegAddr); - } - /* underflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* check the underflow status */ - if (status & infoPtr->qUflowStatBitMask) - { - /* the queue is empty - * clear the underflow status bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - return IX_QMGR_Q_UNDERFLOW; - } - } - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQWriteWithChecks (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQEntrySizeInWords entrySizeInWords; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - if (NULL == entry) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - /* Get the q entry size in words */ - entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId); - - ixQMgrAqmIfQPush (qId, entrySizeInWords, entry); - - /* reset the current read count if the counter wrapped around - * (unsigned arithmetic) - */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - if (infoPtr->qWriteCount++ >= infoPtr->qSizeInEntries) - { - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - } - - /* Check if overflow occurred on the write*/ - if (ixQMgrAqmIfOverflowCheck (qId)) - { - return IX_QMGR_Q_OVERFLOW; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQPeek (IxQMgrQId qId, - unsigned int entryIndex, - UINT32 *entry) -{ - unsigned int numEntries; - -#ifndef NDEBUG - if ((NULL == entry) || (entryIndex >= IX_QMGR_Q_SIZE_INVALID)) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries)) - { - return IX_FAIL; - } - - if (entryIndex >= numEntries) /* entryIndex starts at 0 */ - { - return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS; - } - - return ixQMgrAqmIfQPeek (qId, entryIndex, entry); -} - -IX_STATUS -ixQMgrQPoke (IxQMgrQId qId, - unsigned entryIndex, - UINT32 *entry) -{ - unsigned int numEntries; - -#ifndef NDEBUG - if ((NULL == entry) || (entryIndex > 128)) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries)) - { - return IX_FAIL; - } - - if (numEntries < (entryIndex + 1)) /* entryIndex starts at 0 */ - { - return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS; - } - - return ixQMgrAqmIfQPoke (qId, entryIndex, entry); -} - -IX_STATUS -ixQMgrQStatusGetWithChecks (IxQMgrQId qId, - IxQMgrQStatus *qStatus) -{ - if (NULL == qStatus) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - ixQMgrAqmIfQueStatRead (qId, qStatus); - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQNumEntriesGet (IxQMgrQId qId, - unsigned *numEntriesPtr) -{ - UINT32 qPtrs; - UINT32 qStatus; - unsigned numEntries; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - -#ifndef NDEBUG - if (NULL == numEntriesPtr) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - /* get fast access data */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - - /* get snapshot */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - numEntries = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (numEntries == 0) - { - /* - * Could mean either full or empty queue - * so look at status - */ - ixQMgrAqmIfQueStatRead (qId, &qStatus); - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - if (qStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) - { - /* Empty */ - *numEntriesPtr = 0; - } - else if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK) - { - /* Full */ - *numEntriesPtr = infoPtr->qSizeInEntries; - } - else - { - /* - * Queue status and read/write pointers are volatile. - * The queue state has changed since we took the - * snapshot of the read and write pointers. - * Client can retry if they wish - */ - *numEntriesPtr = 0; - return IX_QMGR_WARNING; - } - } - else /* It is an upper queue which does not have an empty status bit maintained */ - { - if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK) - { - /* The queue is Full at the time of snapshot. */ - *numEntriesPtr = infoPtr->qSizeInEntries; - } - else - { - /* The queue is either empty, either moving, - * Client can retry if they wish - */ - *numEntriesPtr = 0; - return IX_QMGR_WARNING; - } - } - } - else - { - *numEntriesPtr = (numEntries / infoPtr->qEntrySizeInWords) & (infoPtr->qSizeInEntries - 1); - } - - return IX_SUCCESS; -} - -#if defined(__wince) && defined(NO_INLINE_APIS) - -PUBLIC IX_STATUS -ixQMgrQRead (IxQMgrQId qId, - UINT32 *entryPtr) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entry, entrySize; - - /* get a new entry */ - entrySize = infoPtr->qEntrySizeInWords; - entry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr); - - if (entrySize != IX_QMGR_Q_ENTRY_SIZE1) - { - *entryPtr = entry; - /* process the remaining part of the entry */ - return ixQMgrQReadMWordsMinus1(qId, entryPtr); - } - - /* underflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* the counter of queue entries is decremented. In happy - * day scenario there are many entries in the queue - * and the counter does not reach zero. - */ - if (infoPtr->qReadCount-- == 0) - { - /* There is maybe no entry in the queue - * qReadCount is now negative, but will be corrected before - * the function returns. - */ - UINT32 qPtrs; /* queue internal pointers */ - - /* when a queue is empty, the hw guarantees to return - * a null value. If the value is not null, the queue is - * not empty. - */ - if (entry == 0) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* check the underflow status */ - if (status & infoPtr->qUflowStatBitMask) - { - /* the queue is empty - * clear the underflow status bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - *entryPtr = 0; - infoPtr->qReadCount = 0; - return IX_QMGR_Q_UNDERFLOW; - } - } - /* store the result */ - *entryPtr = entry; - - /* No underflow occured : someone is filling the queue - * or the queue contains null entries. - * The current counter needs to be - * updated from the current number of entries in the queue - */ - - /* get snapshot of queue pointers */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (qPtrs == 0) - { - /* no entry in the queue */ - infoPtr->qReadCount = 0; - } - else - { - /* convert the number of words inside the queue - * to a number of entries - */ - infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1); - } - return IX_SUCCESS; - } - } - *entryPtr = entry; - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQBurstRead (IxQMgrQId qId, - UINT32 numEntries, - UINT32 *entries) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 nullCheckEntry; - - if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1) - { - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - - /* the code is optimized to take care of data dependencies: - * Durig a read, there are a few cycles needed to get the - * read complete. During these cycles, it is poossible to - * do some CPU, e.g. increment pointers and decrement - * counters. - */ - - /* fetch a queue entry */ - nullCheckEntry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr); - - /* iterate the specified number of queue entries */ - while (--numEntries) - { - /* check the result of the previous read */ - if (nullCheckEntry == 0) - { - /* if we read a NULL entry, stop. We have underflowed */ - break; - } - else - { - /* write the entry */ - *entries = nullCheckEntry; - /* fetch next entry */ - nullCheckEntry = IX_OSAL_READ_LONG(qAccRegAddr); - /* increment the write address */ - entries++; - } - } - /* write the pre-fetched entry */ - *entries = nullCheckEntry; - } - else - { - IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords; - /* read the specified number of queue entries */ - nullCheckEntry = 0; - while (numEntries--) - { - int i; - - for (i = 0; i < entrySizeInWords; i++) - { - *entries = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr + i); - nullCheckEntry |= *entries++; - } - - /* if we read a NULL entry, stop. We have underflowed */ - if (nullCheckEntry == 0) - { - break; - } - nullCheckEntry = 0; - } - } - - /* reset the current read count : next access to the read function - * will force a underflow status check - */ - infoPtr->qWriteCount = 0; - - /* Check if underflow occurred on the read */ - if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - if (status & infoPtr->qUflowStatBitMask) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - return IX_QMGR_Q_UNDERFLOW; - } - } - - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQWrite (IxQMgrQId qId, - UINT32 *entry) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entrySize; - - /* write the entry */ - IX_OSAL_WRITE_LONG(infoPtr->qAccRegAddr, *entry); - entrySize = infoPtr->qEntrySizeInWords; - - if (entrySize != IX_QMGR_Q_ENTRY_SIZE1) - { - /* process the remaining part of the entry */ - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - while (--entrySize) - { - ++entry; - IX_OSAL_WRITE_LONG(++qAccRegAddr, *entry); - } - entrySize = infoPtr->qEntrySizeInWords; - } - - /* overflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - UINT32 qSize = infoPtr->qSizeInEntries; - /* increment the current number of entries in the queue - * and check for overflow - */ - if (infoPtr->qWriteCount++ == qSize) - { - /* the queue may have overflow */ - UINT32 qPtrs; /* queue internal pointers */ - - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* read the status twice because the status may - * not be immediately ready after the write operation - */ - if ((status & infoPtr->qOflowStatBitMask) || - ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr)) - & infoPtr->qOflowStatBitMask)) - { - /* the queue is full, clear the overflow status - * bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qOflowStatBitMask); - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - return IX_QMGR_Q_OVERFLOW; - } - /* No overflow occured : someone is draining the queue - * and the current counter needs to be - * updated from the current number of entries in the queue - */ - - /* get q pointer snapshot */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (qPtrs == 0) - { - /* the queue may be full at the time of the - * snapshot. Next access will check - * the overflow status again. - */ - infoPtr->qWriteCount = qSize; - } - else - { - /* convert the number of words to a number of entries */ - if (entrySize == IX_QMGR_Q_ENTRY_SIZE1) - { - infoPtr->qWriteCount = qPtrs & (qSize - 1); - } - else - { - infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1); - } - } - } - } - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQBurstWrite (IxQMgrQId qId, - unsigned numEntries, - UINT32 *entries) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 status; - - /* update the current write count */ - infoPtr->qWriteCount += numEntries; - - if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1) - { - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - while (numEntries--) - { - IX_OSAL_WRITE_LONG(qAccRegAddr, *entries); - entries++; - } - } - else - { - IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords; - int i; - - /* write each queue entry */ - while (numEntries--) - { - /* write the queueEntrySize number of words for each entry */ - for (i = 0; i < entrySizeInWords; i++) - { - IX_OSAL_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries); - entries++; - } - } - } - - /* check if the write count overflows */ - if (infoPtr->qWriteCount > infoPtr->qSizeInEntries) - { - /* reset the current write count */ - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - } - - /* Check if overflow occurred on the write operation */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* read the status twice because the status may - * not be ready at the time of the write - */ - if ((status & infoPtr->qOflowStatBitMask) || - ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr)) - & infoPtr->qOflowStatBitMask)) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qOflowStatBitMask); - return IX_QMGR_Q_OVERFLOW; - } - } - - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQStatusGet (IxQMgrQId qId, - IxQMgrQStatus *qStatus) -{ - /* read the status of a queue in the range 0-31 */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[]; - extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[]; - extern UINT32 ixQMgrAqmIfQueLowStatBitsMask; - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId]; - volatile UINT32 *qUOStatRegAddr = infoPtr->qUOStatRegAddr; - - UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId]; - UINT32 lowStatBitsMask = ixQMgrAqmIfQueLowStatBitsMask; - UINT32 underflowBitMask = infoPtr->qUflowStatBitMask; - UINT32 overflowBitMask = infoPtr->qOflowStatBitMask; - - /* read the status register for this queue */ - *qStatus = IX_OSAL_READ_LONG(lowStatRegAddr); - /* mask out the status bits relevant only to this queue */ - *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask; - - /* Check if the queue has overflowed */ - if (IX_OSAL_READ_LONG(qUOStatRegAddr) & overflowBitMask) - { - /* clear the overflow status bit if it was set */ - IX_OSAL_WRITE_LONG(qUOStatRegAddr, - (IX_OSAL_READ_LONG(qUOStatRegAddr) & - ~overflowBitMask)); - *qStatus |= IX_QMGR_Q_STATUS_OF_BIT_MASK; - } - - /* Check if the queue has underflowed */ - if (IX_OSAL_READ_LONG(qUOStatRegAddr) & underflowBitMask) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(qUOStatRegAddr, - (IX_OSAL_READ_LONG(qUOStatRegAddr) & - ~underflowBitMask)); - *qStatus |= IX_QMGR_Q_STATUS_UF_BIT_MASK; - } - } - else /* read status of a queue in the range 32-63 */ - { - extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr; - extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr; - extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[]; - extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[]; - - volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr; - volatile UINT32 *qFullStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr; - int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID; - UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex]; - UINT32 qFullStatBitMask = ixQMgrAqmIfQueUppStat1BitMask[maskIndex]; - - /* Reset the status bits */ - *qStatus = 0; - - /* Check if the queue is nearly empty */ - if (IX_OSAL_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask) - { - *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK; - } - - /* Check if the queue is full */ - if (IX_OSAL_READ_LONG(qFullStatRegAddr) & qFullStatBitMask) - { - *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK; - } - } - return IX_SUCCESS; -} -#endif /* def NO_INLINE_APIS */ diff --git a/drivers/net/npe/IxQMgrQCfg.c b/drivers/net/npe/IxQMgrQCfg.c deleted file mode 100644 index 26ec327a8e..0000000000 --- a/drivers/net/npe/IxQMgrQCfg.c +++ /dev/null @@ -1,543 +0,0 @@ -/** - * @file QMgrQCfg.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This modules provides an interface for setting up the static - * configuration of AQM queues.This file contains the following - * functions: - * - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDefines_p.h" - -/* - * #defines and macros used in this file. - */ - -#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16 - -/* Total size of SRAM */ -#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000 - -/* - * Check that qId is a valid queue identifier. This is provided to - * make the code easier to read. - */ -#define IX_QMGR_QID_IS_VALID(qId) \ -(((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID))) - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * This struct describes an AQM queue. - * N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue - * as these are requested by Access in the data path. sizeInEntries is - * not required by the data path so it can be calculated dynamically. - * - */ -typedef struct -{ - char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/ - IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */ - IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/ - BOOL isConfigured; /* This flag is true if the queue has - * been configured - */ -} IxQMgrCfgQ; - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ - -extern UINT32 * ixQMgrAqmIfQueAccRegAddr[]; - -/* Store data required to inline read and write access - */ -IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES]; - -static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES]; - -/* This pointer holds the starting address of AQM SRAM not used by - * the AQM queues. - */ -static UINT32 freeSramAddress=0; - -/* 4 words of zeroed memory for inline access */ -static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 }; - -static BOOL cfgInitialized = false; - -static IxOsalMutex ixQMgrQCfgMutex; - -/* - * Statistics - */ -static IxQMgrQCfgStats stats; - -/* - * Function declarations - */ -PRIVATE BOOL -watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level); - -PRIVATE BOOL -qSizeInWordsIsOk (IxQMgrQSizeInWords qSize); - -PRIVATE BOOL -qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize); - -/* - * Function definitions. - */ -void -ixQMgrQCfgInit (void) -{ - int loopIndex; - - for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++) - { - /* info for code inlining */ - ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder; - - /* info for code inlining */ - ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder; - ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder; - ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder; - } - - /* Initialise the AqmIf component */ - ixQMgrAqmIfInit (); - - /* Reset all queues to have queue name = NULL, entry size = 0 and - * isConfigured = false - */ - for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++) - { - strcpy (cfgQueueInfo[loopIndex].qName, ""); - cfgQueueInfo[loopIndex].qSizeInWords = 0; - cfgQueueInfo[loopIndex].qEntrySizeInWords = 0; - cfgQueueInfo[loopIndex].isConfigured = false; - - /* Statistics */ - stats.qStats[loopIndex].isConfigured = false; - stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName; - } - - /* Statistics */ - stats.wmSetCnt = 0; - - ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress); - - ixOsalMutexInit(&ixQMgrQCfgMutex); - - cfgInitialized = true; -} - -void -ixQMgrQCfgUninit (void) -{ - cfgInitialized = false; - - /* Uninitialise the AqmIf component */ - ixQMgrAqmIfUninit (); -} - -IX_STATUS -ixQMgrQConfig (char *qName, - IxQMgrQId qId, - IxQMgrQSizeInWords qSizeInWords, - IxQMgrQEntrySizeInWords qEntrySizeInWords) -{ - UINT32 aqmLocalBaseAddress; - - if (!cfgInitialized) - { - return IX_FAIL; - } - - if (!IX_QMGR_QID_IS_VALID(qId)) - { - return IX_QMGR_INVALID_Q_ID; - } - - else if (NULL == qName) - { - return IX_QMGR_PARAMETER_ERROR; - } - - else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN) - { - return IX_QMGR_PARAMETER_ERROR; - } - - else if (!qSizeInWordsIsOk (qSizeInWords)) - { - return IX_QMGR_INVALID_QSIZE; - } - - else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords)) - { - return IX_QMGR_INVALID_Q_ENTRY_SIZE; - } - - else if (cfgQueueInfo[qId].isConfigured) - { - return IX_QMGR_Q_ALREADY_CONFIGURED; - } - - ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER); - - /* Write the config register */ - ixQMgrAqmIfQueCfgWrite (qId, - qSizeInWords, - qEntrySizeInWords, - freeSramAddress); - - - strcpy (cfgQueueInfo[qId].qName, qName); - cfgQueueInfo[qId].qSizeInWords = qSizeInWords; - cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords; - - /* store pre-computed information in the same cache line - * to facilitate inlining of QRead and QWrite functions - * in IxQMgr.h - */ - ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0; - ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0; - ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords; - ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries = - (UINT32)qSizeInWords / (UINT32)qEntrySizeInWords; - - /* Calculate the new freeSramAddress from the size of the queue - * currently being configured. - */ - freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD); - - /* Get the virtual SRAM address */ - ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress); - - IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <= - IX_QMGR_QUE_BUFFER_SPACE_SIZE); - - /* The queue is now configured */ - cfgQueueInfo[qId].isConfigured = true; - - ixOsalMutexUnlock(&ixQMgrQCfgMutex); - -#ifndef NDEBUG - /* Update statistics */ - stats.qStats[qId].isConfigured = true; - stats.qStats[qId].qName = cfgQueueInfo[qId].qName; -#endif - return IX_SUCCESS; -} - -IxQMgrQSizeInWords -ixQMgrQSizeInWordsGet (IxQMgrQId qId) -{ - /* No parameter checking as this is used on the data path */ - return (cfgQueueInfo[qId].qSizeInWords); -} - -IX_STATUS -ixQMgrQSizeInEntriesGet (IxQMgrQId qId, - unsigned *qSizeInEntries) -{ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if(NULL == qSizeInEntries) - { - return IX_QMGR_PARAMETER_ERROR; - } - - *qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) / - (UINT32)cfgQueueInfo[qId].qEntrySizeInWords; - - return IX_SUCCESS; -} - -IxQMgrQEntrySizeInWords -ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId) -{ - /* No parameter checking as this is used on the data path */ - return (cfgQueueInfo[qId].qEntrySizeInWords); -} - -IX_STATUS -ixQMgrWatermarkSet (IxQMgrQId qId, - IxQMgrWMLevel ne, - IxQMgrWMLevel nf) -{ - IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */ - IxQMgrQStatus qStatusOnExit; /* to this function */ - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (!watermarkLevelIsOk (qId, ne)) - { - return IX_QMGR_INVALID_Q_WM; - } - - if (!watermarkLevelIsOk (qId, nf)) - { - return IX_QMGR_INVALID_Q_WM; - } - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry); - -#ifndef NDEBUG - /* Update statistics */ - stats.wmSetCnt++; -#endif - - ixQMgrAqmIfWatermarkSet (qId, - ne, - nf); - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit); - - /* If the status has changed return a warning */ - if (qStatusOnEntry != qStatusOnExit) - { - return IX_QMGR_WARNING; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrAvailableSramAddressGet (UINT32 *address, - unsigned *sizeOfFreeRam) -{ - UINT32 aqmLocalBaseAddress; - - if ((NULL == address)||(NULL == sizeOfFreeRam)) - { - return IX_QMGR_PARAMETER_ERROR; - } - if (!cfgInitialized) - { - return IX_FAIL; - } - - *address = freeSramAddress; - - /* Get the virtual SRAM address */ - ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress); - - /* - * Calculate the size in bytes of free sram - * i.e. current free SRAM virtual pointer from - * (base + total size) - */ - *sizeOfFreeRam = - (aqmLocalBaseAddress + - IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) - - freeSramAddress; - - if (0 == *sizeOfFreeRam) - { - return IX_QMGR_NO_AVAILABLE_SRAM; - } - - return IX_SUCCESS; -} - -BOOL -ixQMgrQIsConfigured (IxQMgrQId qId) -{ - if (!IX_QMGR_QID_IS_VALID(qId)) - { - return false; - } - - return cfgQueueInfo[qId].isConfigured; -} - -IxQMgrQCfgStats* -ixQMgrQCfgStatsGet (void) -{ - return &stats; -} - -IxQMgrQCfgStats* -ixQMgrQCfgQStatsGet (IxQMgrQId qId) -{ - unsigned int ne; - unsigned int nf; - UINT32 baseAddress; - UINT32 readPtr; - UINT32 writePtr; - - stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords; - stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords; - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries)) - { - if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries)) - { - IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId); - } - } - - ixQMgrAqmIfQueCfgRead (qId, - stats.qStats[qId].numEntries, - &baseAddress, - &ne, - &nf, - &readPtr, - &writePtr); - - stats.qStats[qId].baseAddress = baseAddress; - stats.qStats[qId].ne = ne; - stats.qStats[qId].nf = nf; - stats.qStats[qId].readPtr = readPtr; - stats.qStats[qId].writePtr = writePtr; - - return &stats; -} - -/* - * Static function definitions - */ - -PRIVATE BOOL -watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level) -{ - unsigned qSizeInEntries; - - switch (level) - { - case IX_QMGR_Q_WM_LEVEL0: - case IX_QMGR_Q_WM_LEVEL1: - case IX_QMGR_Q_WM_LEVEL2: - case IX_QMGR_Q_WM_LEVEL4: - case IX_QMGR_Q_WM_LEVEL8: - case IX_QMGR_Q_WM_LEVEL16: - case IX_QMGR_Q_WM_LEVEL32: - case IX_QMGR_Q_WM_LEVEL64: - break; - default: - return false; - } - - /* Check watermark is not bigger than the qSizeInEntries */ - ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries); - - if ((unsigned)level > qSizeInEntries) - { - return false; - } - - return true; -} - -PRIVATE BOOL -qSizeInWordsIsOk (IxQMgrQSizeInWords qSize) -{ - BOOL status; - - switch (qSize) - { - case IX_QMGR_Q_SIZE16: - case IX_QMGR_Q_SIZE32: - case IX_QMGR_Q_SIZE64: - case IX_QMGR_Q_SIZE128: - status = true; - break; - default: - status = false; - break; - } - - return status; -} - -PRIVATE BOOL -qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize) -{ - BOOL status; - - switch (entrySize) - { - case IX_QMGR_Q_ENTRY_SIZE1: - case IX_QMGR_Q_ENTRY_SIZE2: - case IX_QMGR_Q_ENTRY_SIZE4: - status = true; - break; - default: - status = false; - break; - } - - return status; -} diff --git a/drivers/net/npe/Makefile b/drivers/net/npe/Makefile deleted file mode 100644 index a982678d89..0000000000 --- a/drivers/net/npe/Makefile +++ /dev/null @@ -1,83 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB := $(obj)libnpe.o - -LOCAL_CFLAGS += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux -CFLAGS += $(LOCAL_CFLAGS) -CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend -HOSTCFLAGS += $(LOCAL_CFLAGS) - -COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \ - miiphy.o \ - IxOsalBufferMgt.o \ - IxOsalIoMem.o \ - IxOsalOsCacheMMU.o \ - IxOsalOsMsgQ.o \ - IxOsalOsSemaphore.o \ - IxOsalOsServices.o \ - IxOsalOsThread.o \ - IxEthAcc.o \ - IxEthAccCommon.o \ - IxEthAccControlInterface.o \ - IxEthAccDataPlane.o \ - IxEthAccMac.o \ - IxEthAccMii.o \ - IxEthDBAPI.o \ - IxEthDBAPISupport.o \ - IxEthDBCore.o \ - IxEthDBEvents.o \ - IxEthDBFeatures.o \ - IxEthDBFirewall.o \ - IxEthDBHashtable.o \ - IxEthDBLearning.o \ - IxEthDBMem.o \ - IxEthDBNPEAdaptor.o \ - IxEthDBPortUpdate.o \ - IxEthDBReports.o \ - IxEthDBSearch.o \ - IxEthDBSpanningTree.o \ - IxEthDBUtil.o \ - IxEthDBVlan.o \ - IxEthDBWiFi.o \ - IxEthMii.o \ - IxQMgrAqmIf.o \ - IxQMgrDispatcher.o \ - IxQMgrInit.o \ - IxQMgrQAccess.o \ - IxQMgrQCfg.o \ - IxFeatureCtrl.o \ - IxNpeDl.o \ - IxNpeDlImageMgr.o \ - IxNpeDlNpeMgr.o \ - IxNpeDlNpeMgrUtils.o \ - IxNpeMh.o \ - IxNpeMhConfig.o \ - IxNpeMhReceive.o \ - IxNpeMhSend.o \ - IxNpeMhSolicitedCbMgr.o \ - IxNpeMhUnsolicitedCbMgr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/drivers/net/npe/include/IxAssert.h b/drivers/net/npe/include/IxAssert.h deleted file mode 100644 index eae8b3f273..0000000000 --- a/drivers/net/npe/include/IxAssert.h +++ /dev/null @@ -1,71 +0,0 @@ -/** - * @file IxAssert.h - * - * @date 21-MAR-2002 (replaced by OSAL) - * - * @brief This file contains assert and ensure macros used by the IXP400 software - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxAssert IXP400 Assertion Macros (IxAssert) API - * - * @brief Assertion support - * - * @{ - */ - -#ifndef IXASSERT_H - -#ifndef __doxygen_HIDE -#define IXASSERT_H -#endif /* __doxygen_HIDE */ - -#include "IxOsalBackward.h" - -#endif /* IXASSERT_H */ - -/** - * @} addtogroup IxAssert - */ - - - diff --git a/drivers/net/npe/include/IxAtmSch.h b/drivers/net/npe/include/IxAtmSch.h deleted file mode 100644 index 73c3be29ab..0000000000 --- a/drivers/net/npe/include/IxAtmSch.h +++ /dev/null @@ -1,504 +0,0 @@ -/** - * @file IxAtmSch.h - * - * @date 23-NOV-2001 - * - * @brief Header file for the IXP400 ATM Traffic Shaper - * - * This component demonstrates an ATM Traffic Shaper implementation. It - * will perform shaping on upto 12 ports and total of 44 VCs accross all ports, - * 32 are intended for AAL0/5 and 12 for OAM (1 per port). - * The supported traffic types are;1 rt-VBR VC where PCR = SCR. - * (Effectively CBR) and Up-to 44 VBR VCs. - * - * This component models the ATM ports and VCs and is capable of producing - * a schedule of ATM cells per port which can be supplied to IxAtmdAcc - * for execution on the data path. - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * - * @sa IxAtmm.h - * - */ - -/** - * @defgroup IxAtmSch IXP400 ATM Transmit Scheduler (IxAtmSch) API - * - * @brief IXP400 ATM scheduler component Public API - * - * @{ - */ - -#ifndef IXATMSCH_H -#define IXATMSCH_H - -#include "IxOsalTypes.h" -#include "IxAtmTypes.h" - -/* - * #defines and macros used in this file. - */ - -/* Return codes */ - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_NOT_ADMITTED - * @brief Indicates that CAC function has rejected VC registration due - * to insufficient line capacity. -*/ -#define IX_ATMSCH_RET_NOT_ADMITTED 2 - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_QUEUE_FULL - * @brief Indicates that the VC queue is full, no more demand can be - * queued at this time. - */ -#define IX_ATMSCH_RET_QUEUE_FULL 3 - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_QUEUE_EMPTY - * @brief Indicates that all VC queues on this port are empty and - * therefore there are no cells to be scheduled at this time. - */ -#define IX_ATMSCH_RET_QUEUE_EMPTY 4 - -/* - * Function declarations - */ - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchInit(void) - * - * @brief This function is used to initialize the ixAtmSch component. It - * should be called before any other IxAtmSch API function. - * - * @param None - * - * @return - * - IX_SUCCESS : indicates that - * -# The ATM scheduler component has been successfully initialized. - * -# The scheduler is ready to accept Port modelling requests. - * - IX_FAIL : Some internal error has prevented the scheduler component - * from initialising. - */ -PUBLIC IX_STATUS -ixAtmSchInit(void); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchPortModelInitialize( IxAtmLogicalPort port, - unsigned int portRate, - unsigned int minCellsToSchedule) - * - * @brief This function shall be called first to initialize an ATM port before - * any other ixAtmSch API calls may be made for that port. - * - * @param port @ref IxAtmLogicalPort [in] - The specific port to initialize. Valid - * values range from 0 to IX_UTOPIA_MAX_PORTS - 1, representing a - * maximum of IX_UTOPIA_MAX_PORTS possible ports. - * - * @param portRate unsigned int [in] - Value indicating the upstream capacity - * of the indicated port. The value should be supplied in - * units of ATM (53 bytes) cells per second. - * A port rate of 800Kbits/s is the equivalent - * of 1886 cells per second - * - * @param minCellsToSchedule unsigned int [in] - This parameter specifies the minimum - * number of cells which the scheduler will put in a schedule - * table for this port. This value sets the worst case CDVT for VCs - * on this port i.e. CDVT = 1*minCellsToSchedule/portRate. - * @return - * - IX_SUCCESS : indicates that - * -# The ATM scheduler has been successfully initialized. - * -# The requested port model has been established. - * -# The scheduler is ready to accept VC modelling requests - * on the ATM port. - * - IX_FAIL : indicates the requested port could not be - * initialized. */ -PUBLIC IX_STATUS -ixAtmSchPortModelInitialize( IxAtmLogicalPort port, - unsigned int portRate, - unsigned int minCellsToSchedule); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchPortRateModify( IxAtmLogicalPort port, - unsigned int portRate) - * - * @brief This function is called to modify the portRate on a - * previously initialized port, typically in the event that - * the line condition of the port changes. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port which is to be - * modified. - * - * @param portRate unsigned int [in] - Value indicating the new upstream - * capacity for this port in cells/second. - * A port rate of 800Kbits/s is the equivalent - * of 1886 cells per second - * - * @return - * - IX_SUCCESS : The port rate has been successfully modified.
- * - IX_FAIL : The port rate could not be modified, either - * because the input data was invalid, or the new port rate is - * insufficient to support established ATM VC contracts on this - * port. - * - * @warning The IxAtmSch component will validate the supplied port - * rate is sufficient to support all established VC - * contracts on the port. If the new port rate is - * insufficient to support all established contracts then - * the request to modify the port rate will be rejected. - * In this event, the user is expected to remove - * established contracts using the ixAtmSchVcModelRemove - * interface and then retry this interface. - * - * @sa ixAtmSchVcModelRemove() */ -PUBLIC IX_STATUS -ixAtmSchPortRateModify( IxAtmLogicalPort port, - unsigned int portRate); - - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcModelSetup( IxAtmLogicalPort port, - IxAtmTrafficDescriptor *trafficDesc, - IxAtmSchedulerVcId *vcId) - * - * @brief A client calls this interface to set up an upstream - * (transmitting) virtual connection model (VC) on the - * specified ATM port. This function also provides the - * virtual * connection admission control (CAC) service to the - * client. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream - * VC is to be established. - * - * @param *trafficDesc @ref IxAtmTrafficDescriptor [in] - Pointer to a structure - * describing the requested traffic contract of the VC to be - * established. This structure contains the typical ATM - * traffic descriptor values (e.g. PCR, SCR, MBS, CDVT, etc.) - * defined by the ATM standard. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - This value will be filled with the - * port-unique identifier for this virtual connection. A - * valid identification is a non-negative number. - * - * @return - * - IX_SUCCESS : The VC has been successfully established on - * this port. The client may begin to submit demand on this VC. - * - IX_ATMSCH_RET_NOT_ADMITTED : The VC cannot be established - * on this port because there is insufficient upstream capacity - * available to support the requested traffic contract descriptor - * - IX_FAIL :Input data are invalid. VC has not been - * established. - */ -PUBLIC IX_STATUS -ixAtmSchVcModelSetup( IxAtmLogicalPort port, - IxAtmTrafficDescriptor *trafficDesc, - IxAtmSchedulerVcId *vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcConnIdSet( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - IxAtmConnId vcUserConnId) - * - * @brief A client calls this interface to set the vcUserConnId for a VC on - * the specified ATM port. This vcUserConnId will default to - * IX_ATM_IDLE_CELLS_CONNID if this function is not called for a VC. - * Hence if the client does not call this function for a VC then only idle - * cells will be scheduled for this VC. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream - * VC is has been established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - This is the unique identifier for this virtual - * connection. A valid identification is a non-negative number and is - * all ports. - * - * @param vcUserConnId @ref IxAtmConnId [in] - The connId is used to refer to a VC in schedule - * table entries. It is treated as the Id by which the scheduler client - * knows the VC. It is used in any communicatations from the Scheduler - * to the scheduler user e.g. schedule table entries. - * - * @return - * - IX_SUCCESS : The id has successfully been set. - * - IX_FAIL :Input data are invalid. connId id is not established. - */ -PUBLIC IX_STATUS -ixAtmSchVcConnIdSet( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - IxAtmConnId vcUserConnId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcModelRemove( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId) - * - * @brief Interface called by the client to remove a previously - * established VC on a particular port. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * removed is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be removed. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @return - * - IX_SUCCESS : The VC has been successfully removed from - * this port. It is no longer modelled on this port. - * - IX_FAIL :Input data are invalid. The VC is still being modeled - * by the traffic shaper. - * - * @sa ixAtmSchVcModelSetup() - */ -PUBLIC IX_STATUS -ixAtmSchVcModelRemove( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcQueueUpdate( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - unsigned int numberOfCells) - * - * @brief The client calls this function to notify IxAtmSch that the - * user of a VC has submitted cells for transmission. - * - * This information is stored, aggregated from a number of calls to - * ixAtmSchVcQueueUpdate and eventually used in the call to - * ixAtmSchTableUpdate. - * - * Normally IxAtmSch will update the VC queue by adding the number of - * cells to the current queue length. However, if IxAtmSch - * determines that the user has over-submitted for the VC and - * exceeded its transmission quota the queue request can be rejected. - * The user should resubmit the request later when the queue has been - * depleted. - * - * This implementation of ixAtmSchVcQueueUpdate uses no operating - * system or external facilities, either directly or indirectly. - * This allows clients to call this function form within an interrupt handler. - * - * This interface is structurally compatible with the - * IxAtmdAccSchQueueUpdate callback type definition required for - * IXP400 ATM scheduler interoperability. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * updated is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be updated. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @param numberOfCells unsigned int [in] - Indicates how many ATM cells should - * be added to the queue for this VC. - * - * @return - * - IX_SUCCESS : The VC queue has been successfully updated. - * - IX_ATMSCH_RET_QUEUE_FULL : The VC queue has reached a - * preset limit. This indicates the client has over-submitted - * and exceeded its transmission quota. The request is - * rejected. The VC queue is not updated. The VC user is - * advised to resubmit the request later. - * - IX_FAIL : The input are invalid. No VC queue is updated. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchVcQueueUpdate( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - unsigned int numberOfCells); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcQueueClear( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId) - * - * @brief The client calls this function to remove all currently - * queued cells from a registered VC. The pending cell count - * for the specified VC is reset to zero. - * - * This interface is structurally compatible with the - * IxAtmdAccSchQueueClear callback type definition required for - * IXP400 ATM scheduler interoperability. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * cleared is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be cleared. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @return - * - IX_SUCCESS : The VC queue has been successfully cleared. - * - IX_FAIL : The input are invalid. No VC queue is modified. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchVcQueueClear( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchTableUpdate( IxAtmLogicalPort port, - unsigned int maxCells, - IxAtmScheduleTable **rettable) - * - * @brief The client calls this function to request an update of the - * schedule table for a particular ATM port. - * - * This is called when the client decides it needs a new sequence of - * cells to send (probably because the transmit queue is near to - * empty for this ATM port). The scheduler will use its stored - * information on the cells submitted for transmit (i.e. data - * supplied via @ref ixAtmSchVcQueueUpdate function) with the traffic - * descriptor information of all established VCs on the ATM port to - * decide the sequence of cells to be sent and fill the schedule - * table for a period of time into the future. - * - * IxAtmSch will guarantee a minimum of minCellsToSchedule if there - * is at least one cell ready to send. If there are no cells then - * IX_ATMSCH_RET_QUEUE_EMPTY is returned. - * - * This implementation of ixAtmSchTableUpdate uses no operating - * system or external facilities, either directly or indirectly. - * This allows clients to call this function form within an FIQ - * interrupt handler. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port for which requested - * schedule table is to be generated. - * - * @param maxCells unsigned [in] - Specifies the maximum number of cells - * that must be scheduled in the supplied table during any - * call to the interface. - * - * @param **table @ref IxAtmScheduleTable [out] - A pointer to an area of - * storage is returned which contains the generated - * schedule table. The client should not modify the - * contents of this table. - * - * @return - * - IX_SUCCESS : The schedule table has been published. - * Currently there is at least one VC queue that is nonempty. - * - IX_ATMSCH_RET_QUEUE_EMPTY : Currently all VC queues on - * this port are empty. The schedule table returned is set to - * NULL. The client is not expected to invoke this function - * again until more cells have been submitted on this port - * through the @ref ixAtmSchVcQueueUpdate function. - * - IX_FAIL : The input are invalid. No action is taken. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @warning Subsequent calls to this function for the same port will - * overwrite the contents of previously supplied schedule - * tables. The client must be completely finished with the - * previously supplied schedule table before calling this - * function again for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchTableUpdate( IxAtmLogicalPort port, - unsigned int maxCells, - IxAtmScheduleTable **rettable); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchShow(void) - * - * @brief Utility function which will print statistics on the current - * and accumulated state of VCs and traffic in the ATM - * scheduler component. Output is sent to the default output - * device. - * - * @param none - * @return none - */ -PUBLIC void -ixAtmSchShow(void); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchStatsClear(void) - * - * @brief Utility function which will reset all counter statistics in - * the ATM scheduler to zero. - * - * @param none - * @return none - */ -PUBLIC void -ixAtmSchStatsClear(void); - -#endif -/* IXATMSCH_H */ - -/** @} */ diff --git a/drivers/net/npe/include/IxAtmTypes.h b/drivers/net/npe/include/IxAtmTypes.h deleted file mode 100644 index 8624c3328e..0000000000 --- a/drivers/net/npe/include/IxAtmTypes.h +++ /dev/null @@ -1,409 +0,0 @@ -/** - * @file IxAtmTypes.h - * - * @date 24-MAR-2002 - * - * @brief This file contains Atm types common to a number of Atm components. - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes) - * - * @brief The common set of types used in many Atm components - * - * @{ */ - -#ifndef IXATMTYPES_H -#define IXATMTYPES_H - -#include "IxNpeA.h" - -/** - * @enum IxAtmLogicalPort - * - * @brief Logical Port Definitions : - * - * Only 1 port is available in SPHY configuration - * 12 ports are enabled in MPHY configuration - * - */ -typedef enum -{ - IX_UTOPIA_PORT_0 = 0, /**< Port 0 */ -#ifdef IX_NPE_MPHYMULTIPORT - IX_UTOPIA_PORT_1, /**< Port 1 */ - IX_UTOPIA_PORT_2, /**< Port 2 */ - IX_UTOPIA_PORT_3, /**< Port 3 */ - IX_UTOPIA_PORT_4, /**< Port 4 */ - IX_UTOPIA_PORT_5, /**< Port 5 */ - IX_UTOPIA_PORT_6, /**< Port 6 */ - IX_UTOPIA_PORT_7, /**< Port 7 */ - IX_UTOPIA_PORT_8, /**< Port 8 */ - IX_UTOPIA_PORT_9, /**< Port 9 */ - IX_UTOPIA_PORT_10, /**< Port 10 */ - IX_UTOPIA_PORT_11, /**< Port 11 */ -#endif /* IX_NPE_MPHY */ - IX_UTOPIA_MAX_PORTS /**< Not a port - just a definition for the - * maximum possible ports - */ -} IxAtmLogicalPort; - -/** - * @def IX_ATM_CELL_PAYLOAD_SIZE - * @brief Size of a ATM cell payload - */ -#define IX_ATM_CELL_PAYLOAD_SIZE (48) - -/** - * @def IX_ATM_CELL_SIZE - * @brief Size of a ATM cell, including header - */ -#define IX_ATM_CELL_SIZE (53) - -/** - * @def IX_ATM_CELL_SIZE_NO_HEC - * @brief Size of a ATM cell, excluding HEC byte - */ -#define IX_ATM_CELL_SIZE_NO_HEC (IX_ATM_CELL_SIZE - 1) - -/** - * @def IX_ATM_OAM_CELL_SIZE_NO_HEC - * @brief Size of a OAM cell, excluding HEC byte - */ -#define IX_ATM_OAM_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC - -/** - * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE - * @brief Size of a AAL0 48 Cell payload - */ -#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE - -/** - * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE - * @brief Size of a AAL5 Cell payload - */ -#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE - -/** - * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC - * @brief Size of a AAL0 52 Cell, excluding HEC byte - */ -#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC - - -/** - * @def IX_ATM_MAX_VPI - * @brief Maximum value of an ATM VPI - */ -#define IX_ATM_MAX_VPI 255 - -/** - * @def IX_ATM_MAX_VCI - * @brief Maximum value of an ATM VCI - */ -#define IX_ATM_MAX_VCI 65535 - - /** - * @def IX_ATM_MAX_NUM_AAL_VCS - * @brief Maximum number of active AAL5/AAL0 VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_VCS 32 - -/** - * @def IX_ATM_MAX_NUM_VC - * @brief Maximum number of active AAL5/AAL0 VCs in the system - * The use of this macro is depreciated, it is retained for - * backward compatiblity. For current software release - * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used. - */ -#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS - - - -/** - * @def IX_ATM_MAX_NUM_OAM_TX_VCS - * @brief Maximum number of active OAM Tx VCs in the system, - * 1 OAM VC per port - */ -#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS - -/** - * @def IX_ATM_MAX_NUM_OAM_RX_VCS - * @brief Maximum number of active OAM Rx VCs in the system, - * 1 OAM VC shared accross all ports - */ -#define IX_ATM_MAX_NUM_OAM_RX_VCS 1 - -/** - * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS - * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS) - -/** - * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS - * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS) - -/** - * @def IX_ATM_IDLE_CELLS_CONNID - * @brief VC Id used to indicate idle cells in the returned schedule table. - */ -#define IX_ATM_IDLE_CELLS_CONNID 0 - - -/** - * @def IX_ATM_CELL_HEADER_VCI_GET - * @brief get the VCI field from a cell header - */ -#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \ - (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK); - -/** - * @def IX_ATM_CELL_HEADER_VPI_GET - * @brief get the VPI field from a cell header - */ -#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \ - (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK); - -/** - * @def IX_ATM_CELL_HEADER_PTI_GET - * @brief get the PTI field from a cell header - */ -#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \ - ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK; - -/** - * @typedef IxAtmCellHeader - * - * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A - */ -typedef unsigned int IxAtmCellHeader; - - -/** - * @enum IxAtmServiceCategory - * - * @brief Enumerated type representing available ATM service categories. - * For more informatoin on these categories, see "Traffic Management - * Specification" v4.1, published by the ATM Forum - - * http://www.atmforum.com - */ -typedef enum -{ - IX_ATM_CBR, /**< Constant Bit Rate */ - IX_ATM_RTVBR, /**< Real Time Variable Bit Rate */ - IX_ATM_VBR, /**< Variable Bit Rate */ - IX_ATM_UBR, /**< Unspecified Bit Rate */ - IX_ATM_ABR /**< Available Bit Rate (not supported) */ - -} IxAtmServiceCategory; - -/** - * - * @enum IxAtmRxQueueId - * - * @brief Rx Queue Type for RX traffic - * - * IxAtmRxQueueId defines the queues involved for receiving data. - * - * There are two queues to facilitate prioritisation handling - * and processing the 2 queues with different algorithms and - * constraints - * - * e.g. : one queue can carry voice (or time-critical traffic), the - * other queue can carry non-voice traffic - * - */ -typedef enum -{ - IX_ATM_RX_A = 0, /**< RX queue A */ - IX_ATM_RX_B, /**< RX queue B */ - IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */ -} IxAtmRxQueueId; - -/** - * @brief Structure describing an ATM traffic contract for a Virtual - * Connection (VC). - * - * Structure is used to specify the requested traffic contract for a - * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup - * interface. - * - * These parameters are defined by the ATM forum working group - * (http://www.atmforum.com). - * - * @note Typical values for a voice channel 64 Kbit/s - * - atmService @a IX_ATM_RTVBR - * - pcr 400 (include IP overhead, and AAL5 trailer) - * - cdvt 5000000 (5 ms) - * - scr = pcr - * - * @note Typical values for a data channel 800 Kbit/s - * - atmService @a IX_ATM_UBR - * - pcr 1962 (include IP overhead, and AAL5 trailer) - * - cdvt 5000000 (5 ms) - * - */ -typedef struct -{ - IxAtmServiceCategory atmService; /**< ATM service category */ - unsigned pcr; /**< Peak Cell Rate - cells per second */ - unsigned cdvt; /**< Cell Delay Variation Tolerance - in nanoseconds */ - unsigned scr; /**< Sustained Cell Rate - cells per second */ - unsigned mbs; /**< Max Burst Size - cells */ - unsigned mcr; /**< Minimum Cell Rate - cells per second */ - unsigned mfs; /**< Max Frame Size - cells */ -} IxAtmTrafficDescriptor; - -/** - * @typedef IxAtmConnId - * - * @brief ATM VC data connection identifier. - * - * This is is generated by IxAtmdAcc when a successful connection is - * made on a VC. The is the ID by which IxAtmdAcc knows an active - * VC and should be used in IxAtmdAcc API calls to reference a - * specific VC. - */ -typedef unsigned int IxAtmConnId; - -/** - * @typedef IxAtmSchedulerVcId - * - * @brief ATM VC scheduling connection identifier. - * - * This id is generated and used by ATM Tx controller, generally - * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component - * will request one of these Ids whenever a data connection on - * a Tx VC is requested. This ID will be used in callbacks to - * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a - * particular VC. - */ -typedef int IxAtmSchedulerVcId; - -/** - * @typedef IxAtmNpeRxVcId - * - * @brief ATM Rx VC identifier used by the ATM Npe. - * - * This Id is generated by IxAtmdAcc when a successful data connection - * is made on a rx VC. - */ -typedef unsigned int IxAtmNpeRxVcId; - -/** - * @brief ATM Schedule Table entry - * - * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform - * IxAtmdAcc about the data to transmit (in term of cells per VC) - * - * This structure defines - * @li the number of cells to be transmitted (numberOfCells) - * @li the VC connection to be used for transmission (connId). - * - * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the - * corresponding number of idle cells will be transmitted to the hardware. - * - */ -typedef struct -{ - IxAtmConnId connId; /**< connection Id - * - * Identifier of VC from which cells are to be transmitted. - * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates - * that the system should transmit the specified number - * of idle cells. Unknown connIds result in the transmission - * idle cells. - */ - unsigned int numberOfCells; /**< number of cells to transmit - * - * The number of contiguous cells to schedule from this VC - * at this point. The valid range is from 1 to - * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This - * number can swap over mbufs and pdus. OverSchduling results - * in the transmission of idle cells. - */ -} IxAtmScheduleTableEntry; - -/** - * @brief This structure defines a schedule table which gives details - * on which data (from which VCs) should be transmitted for a - * forthcoming period of time for a particular port and the - * order in which that data should be transmitted. - * - * The schedule table consists of a series of entries each of which - * will schedule one or more cells from a particular registered VC. - * The total number of cells scheduled and the total number of - * entries in the table are also indicated. - * - */ -typedef struct -{ - unsigned tableSize; /**< Number of entries - * - * Indicates the total number of - * entries in the table. - */ - unsigned totalCellSlots; /**< Number of cells - * - * Indicates the total number of ATM - * cells which are scheduled by all the - * entries in the table. - */ - IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries - * - * Pointer to an array - * containing tableSize entries - */ -} IxAtmScheduleTable; - -#endif /* IXATMTYPES_H */ - -/** - * @} defgroup IxAtmTypes - */ - - diff --git a/drivers/net/npe/include/IxAtmdAcc.h b/drivers/net/npe/include/IxAtmdAcc.h deleted file mode 100644 index ae7b2434c3..0000000000 --- a/drivers/net/npe/include/IxAtmdAcc.h +++ /dev/null @@ -1,1194 +0,0 @@ - -/** - * @file IxAtmdAcc.h - * - * @date 07-Nov-2001 - * - * @brief IxAtmdAcc Public API - * - * This file contains the public API of IxAtmdAcc, related to the - * data functions of the component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ - -/** - * - * @defgroup IxAtmdAccAPI IXP400 ATM Driver Access (IxAtmdAcc) API - * - * @brief The public API for the IXP400 Atm Driver Data component - * - * IxAtmdAcc is the low level interface by which AAL0/AAL5 and - * OAM data gets transmitted to,and received from the Utopia bus. - * - * For AAL0/AAL5 services transmit and receive connections may - * be established independantly for unique combinations of - * port,VPI,and VCI. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service the client must format - * the PDU with an ATM cell header (excluding HEC) at the start of - * each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * OAM cells cannot be received over the AAL0 service but instead - * are received over a dedicated OAM service. - * - * For the OAM service an "OAM Tx channel" may be enabled for a port - * by establishing a single dedicated OAM Tx connection on that port. - * A single "OAM Rx channel" for all ports may be enabled by - * establishing a dedicated OAM Rx connection. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values defined below. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. Note that AtmdAcc does not validate the cell headers - * in a submitted OAM PDU. - * - * - * - * This part is related to the User datapath processing - * - * @{ - */ - -#ifndef IXATMDACC_H -#define IXATMDACC_H - -#include "IxAtmTypes.h" - -/* ------------------------------------------------------ - AtmdAcc Data Types definition - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_WARNING - * - * @brief Warning return code - * - * This constant is used to tell IxAtmDAcc user about a special case. - * - */ -#define IX_ATMDACC_WARNING 2 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_BUSY - * - * @brief Busy return code - * - * This constant is used to tell IxAtmDAcc user that the request - * is correct, but cannot be processed because the IxAtmAcc resources - * are already used. The user has to retry its request later - * - */ -#define IX_ATMDACC_BUSY 3 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_RESOURCES_STILL_ALLOCATED - * - * @brief Disconnect return code - * - * This constant is used to tell IxAtmDAcc user that the disconnect - * functions are not complete because the resources used by the driver - * are not yet released. The user has to retry the disconnect call - * later. - * - */ -#define IX_ATMDACC_RESOURCES_STILL_ALLOCATED 4 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_DEFAULT_REPLENISH_COUNT - * - * @brief Default resources usage for RxVcFree replenish mechanism - * - * This constant is used to tell IxAtmDAcc to allocate and use - * the minimum of resources for rx free replenish. - * - * @sa ixAtmdAccRxVcConnect - */ -#define IX_ATMDACC_DEFAULT_REPLENISH_COUNT 0 - - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_TX_VPI - * - * @brief The reserved value used for the dedicated OAM - * Tx connection. This "well known" value is used by atmdAcc and - * its clients to dsicriminate the OAM channel, and should be chosen so - * that it does not coencide with the VPI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VPI will fail. - * - * - */ -#define IX_ATMDACC_OAM_TX_VPI 0 - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_TX_VCI - * - * @brief The reserved value used for the dedicated OAM - * Tx connection. This "well known" value is used by atmdAcc and - * its clients to dsicriminate the OAM channel, and should be chosen so - * that it does not coencide with the VCI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VCI will fail. - */ -#define IX_ATMDACC_OAM_TX_VCI 0 - - - /** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_PORT - * - * @brief The reserved dummy PORT used for all dedicated OAM - * Rx connections. Note that this is not a real port but must - * have a value that lies within the valid range of port values. - */ -#define IX_ATMDACC_OAM_RX_PORT IX_UTOPIA_PORT_0 - - /** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_VPI - * - * @brief The reserved value value used for the dedicated OAM - * Rx connection. This value should be chosen so that it does not - * coencide with the VPI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VPI will fail. - */ -#define IX_ATMDACC_OAM_RX_VPI 0 - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_VCI - * - * @brief The reserved value value used for the dedicated OAM - * Rx connection. This value should be chosen so that it does not - * coencide with the VCI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VCI will fail. - */ -#define IX_ATMDACC_OAM_RX_VCI 0 - - -/** - * @enum IxAtmdAccPduStatus - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc Pdu status : - * - * IxAtmdAccPduStatus is used during a RX operation to indicate - * the status of the received PDU - * - */ - -typedef enum -{ - IX_ATMDACC_AAL0_VALID = 0, /**< aal0 pdu */ - IX_ATMDACC_OAM_VALID, /**< OAM pdu */ - IX_ATMDACC_AAL2_VALID, /**< aal2 pdu @b reserved for future use */ - IX_ATMDACC_AAL5_VALID, /**< aal5 pdu complete and trailer is valid */ - IX_ATMDACC_AAL5_PARTIAL, /**< aal5 pdu not complete, trailer is missing */ - IX_ATMDACC_AAL5_CRC_ERROR, /**< aal5 pdu not complete, crc error/length error */ - IX_ATMDACC_MBUF_RETURN /**< empty buffer returned to the user */ -} IxAtmdAccPduStatus; - - -/** - * - * @enum IxAtmdAccAalType - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc AAL Service Type : - * - * IxAtmdAccAalType defines the type of traffic to run on this VC - * - */ -typedef enum -{ - IX_ATMDACC_AAL5, /**< ITU-T AAL5 */ - IX_ATMDACC_AAL2, /**< ITU-T AAL2 @b reserved for future use */ - IX_ATMDACC_AAL0_48, /**< AAL0 48 byte payloads (cell header is added by NPE)*/ - IX_ATMDACC_AAL0_52, /**< AAL0 52 byte cell data (HEC is added by NPE) */ - IX_ATMDACC_OAM, /**< OAM cell transport service (HEC is added by NPE)*/ - IX_ATMDACC_MAX_SERVICE_TYPE /**< not a service, used for parameter validation */ -} IxAtmdAccAalType; - -/** - * - * @enum IxAtmdAccClpStatus - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc CLP indication - * - * IxAtmdAccClpStatus defines the CLP status of the current PDU - * - */ -typedef enum -{ - IX_ATMDACC_CLP_NOT_SET = 0, /**< CLP indication is not set */ - IX_ATMDACC_CLP_SET = 1 /**< CLP indication is set */ -} IxAtmdAccClpStatus; - -/** - * @typedef IxAtmdAccUserId - * - * @ingroup IxAtmdAccAPI - * - * @brief User-supplied Id - * - * IxAtmdAccUserId is passed through callbacks and allows the - * IxAtmdAcc user to identify the source of a call back. The range of - * this user-owned Id is [0...2^32-1)]. - * - * The user provides this own Ids on a per-channel basis as a parameter - * in a call to @a ixAtmdAccRxVcConnect() or @a ixAtmdAccRxVcConnect() - * - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccTxVcConnect - * - */ -typedef unsigned int IxAtmdAccUserId; - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Rx callback prototype - * - * IxAtmdAccRxVcRxCallback is the prototype of the Rx callback user - * function called once per PDU to pass a receive Pdu to a user on a - * partilcular connection. The callback is likely to push the mbufs - * to a protocol layer, and recycle the mbufs for a further use. - * - * @note -This function is called ONLY in the context of - * the @a ixAtmdAccRxDispatch() function - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcConnect - * - * @param port @ref IxAtmLogicalPort [in] - the port on which this PDU was received - * a logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call - * to @a ixAtmdAccRxVcConnect() - * @param status @ref IxAtmdAccPduStatus [in] - an indication about the PDU validity. - * In the case of AAL0 the only possibile value is - * AAL0_VALID, in this case the client may optionally determine - * that an rx timeout occured by checking if the mbuf is - * compleletly or only partially filled, the later case - * indicating a timeout. - * In the case of OAM the only possible value is OAM valid. - * The status is set to @a IX_ATMDACC_MBUF_RETURN when - * the mbuf is released during a disconnect process. - * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. - * For AAL5/AAL0_48 this information - * is set if the clp bit of any rx cell is set - * For AAL0-52/OAM the client may inspect the CLP in individual - * cell headers in the PDU, and this parameter is set to 0. - * @param *mbufPtr @ref IX_OSAL_MBUF [in] - depending on the servive type a pointer to - * an mbuf (AAL5/AAL0/OAM) or mbuf chain (AAL5 only), - * that comprises the complete PDU data. - * - * This parameter is guaranteed not to be a null pointer. - * - */ -typedef void (*IxAtmdAccRxVcRxCallback) (IxAtmLogicalPort port, - IxAtmdAccUserId userId, - IxAtmdAccPduStatus status, - IxAtmdAccClpStatus clp, - IX_OSAL_MBUF * mbufPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Callback prototype for free buffer level is low. - * - * IxAtmdAccRxVcFreeLowCallback is the prototype of the user function - * which get called on a per-VC basis, when more mbufs are needed to - * continue the ATM data reception. This function is likely to supply - * more available mbufs by one or many calls to the replenish function - * @a ixAtmdAccRxVcFreeReplenish() - * - * This function is called when the number of available buffers for - * reception is going under the threshold level as defined - * in @a ixAtmdAccRxVcFreeLowCallbackRegister() - * - * This function is called inside an Qmgr dispatch context. No system - * resource or interrupt-unsafe feature should be used inside this - * callback. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcFreeReplenish - * @sa ixAtmdAccRxVcFreeEntriesQuery - * @sa ixAtmdAccRxVcConnect - * - * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call - * to @a ixAtmdAccRxVcConnect() - * - * @return None - * - */ -typedef void (*IxAtmdAccRxVcFreeLowCallback) (IxAtmdAccUserId userId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Buffer callback prototype. - * - * This function is called to relinguish ownership of a transmitted - * buffer chain to the user. - * - * @note -In the case of a chained mbuf the AmtdAcc component can - * chain many user buffers together and pass ownership to the user in - * one function call. - * - * @param userId @ref IxAtmdAccUserId [in] - user If provided at registration of this - * callback. - * @param mbufPtr @ref IX_OSAL_MBUF [in] - a pointer to mbufs or chain of mbufs and is - * guaranteed not to be a null pointer. - * - */ -typedef void (*IxAtmdAccTxVcBufferReturnCallback) (IxAtmdAccUserId userId, - IX_OSAL_MBUF * mbufPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to Initialisation - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccInit (void) - * - * @brief Initialise the IxAtmdAcc Component - * - * This function initialise the IxAtmdAcc component. This function shall - * be called before any other function of the API. Its role is to - * initialise all internal resources of the IxAtmdAcc component. - * - * The ixQmgr component needs to be initialized prior the use of - * @a ixAtmdAccInit() - * - * @param none - * - * Failing to initilialize the IxAtmdAcc API before any use of it will - * result in a failed status. - * If the specified component is not present, a success status will still be - * returned, however, a warning indicating the NPE to download to is not - * present will be issued. - * - * @return @li IX_SUCCESS initialisation is complete (in case of component not - * being present, a warning is clearly indicated) - * @return @li IX_FAIL unable to process this request either - * because this IxAtmdAcc is already initialised - * or some unspecified error has occrred. - */ -PUBLIC IX_STATUS ixAtmdAccInit (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccShow (void) - * - * @brief Show IxAtmdAcc configuration on a per port basis - * - * @param none - * - * @return none - * - * @note - Display use printf() and are redirected to stdout - */ -PUBLIC void -ixAtmdAccShow (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccStatsShow (void) - * - * @brief Show all IxAtmdAcc stats - * - * @param none - * - * @return none - * - * @note - Stats display use printf() and are redirected to stdout - */ -PUBLIC void -ixAtmdAccStatsShow (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccStatsReset (void) - * - * @brief Reset all IxAtmdAcc stats - * - * @param none - * - * @return none - * - */ -PUBLIC void -ixAtmdAccStatsReset (void); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmRxQueueId rxQueueId, - IxAtmdAccUserId userCallbackId, - IxAtmdAccRxVcRxCallback rxCallback, - unsigned int minimumReplenishCount, - IxAtmConnId * connIdPtr, - IxAtmNpeRxVcId * npeVcIdPtr ) - * - * @brief Connect to a Aal Pdu receive service for a particular - * port/vpi/vci, and service type. - * - * This function allows a user to connect to an Aal5/Aal0/OAM Pdu receive service - * for a particular port/vpi/vci. It registers the callback and allocates - * internal resources and a Connection Id to be used in further API calls - * related to this VCC. - * - * The function will setup VC receive service on the specified rx queue. - * - * This function is blocking and makes use internal locks, and hence - * should not be called from an interrupt context. - * - * On return from @a ixAtmdAccRxVcConnect() with a failure status, the - * connection Id parameter is unspecified. Its value cannot be used. - * A connId is the reference by which IxAtmdAcc refers to a - * connected VC. This identifier is the result of a succesful call - * to a connect function. This identifier is invalid after a - * sucessful call to a disconnect function. - * - * Calling this function for the same combination of Vpi, Vci and more - * than once without calling @a ixAtmdAccRxVcTryDisconnect() will result in a - * failure status. - * - * If this function returns success the user should supply receive - * buffers by calling @a ixAtmdAccRxVcFreeReplenish() and then call - * @a ixAtmdAccRxVcEnable() to begin receiving pdus. - * - * There is a choice of two receive Qs on which the VC pdus could be - * receive. The user must associate the VC with one of these. Essentially - * having two qs allows more flexible system configuration such as have - * high prioriy traffic on one q (e.g. voice) and low priority traffic on - * the other (e.g. data). The high priority Q could be serviced in - * preference to the low priority Q. One queue may be configured to be - * serviced as soon as there is traffic, the other queue may be configured - * to be serviced by a polling mechanism running at idle time. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Received AAL0 PDUs will be be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service and includes an ATM cell header - * (excluding HEC) at the start of each cell. - * - * A single "OAM Rx channel" for all ports may be enabled by - * establishing a dedicated OAM Rx connection. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. - * - * Calling this function prior to enable the port will fail. - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcEnable - * @sa ixAtmdAccRxVcDisable - * @sa ixAtmdAccRxVcTryDisconnect - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port - * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI - * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI - * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service: AAL5, AAL0_48, AAL0_52, or OAM - * @param rxQueueId @ref IxAtmRxQueueId [in] - this identifieds which of two Qs the VC - * should use.when icoming traffic is processed - * @param userCallbackId @ref IxAtmdAccUserId [in] - user Id used later as a parameter to - * the supplied rxCallback. - * @param rxCallback [in] @ref IxAtmdAccRxVxRxCallback - function called when mbufs are received. - * This parameter cannot be a null pointer. - * @param bufferFreeCallback [in] - function to be called to return - * ownership of buffers to IxAtmdAcc user. - * @param minimumReplenishCount unsigned int [in] - For AAL5/AAL0 the number of free mbufs - * to be used with this channel. Use a high number when the expected traffic - * rate on this channel is high, or when the user's mbufs are small, or when - * the RxVcFreeLow Notification has to be invoked less often. When this - * value is IX_ATMDACC_DEFAULT_REPLENISH_COUNT, the minimum of - * resources will be used. Depending on traffic rate, pdu - * size and mbuf size, rxfree queue size, polling/interrupt rate, this value may - * require to be replaced by a different value in the range 1-128 - * For OAM the rxFree queue size is fixed by atmdAcc and this parameter is ignored. - * @param connIdPtr @ref IxAtmConnId [out] - pointer to a connection Id - * This parameter cannot be a null pointer. - * @param npeVcIdPtr @ref IxAtmNpeRxVcId [out] - pointer to an npe Vc Id - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful call to IxAtmdAccRxVcConnect - * @return @li IX_ATMDACC_BUSY cannot process this request : - * no VC is available - * @return @li IX_FAIL - * parameter error, - * VC already in use, - * attempt to connect AAL service on reserved OAM VPI/VCI, - * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI, - * port is not initialised, - * or some other error occurs during processing. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmRxQueueId rxQueueId, - IxAtmdAccUserId userCallbackId, - IxAtmdAccRxVcRxCallback rxCallback, - unsigned int minimumReplenishCount, - IxAtmConnId * connIdPtr, - IxAtmNpeRxVcId * npeVcIdPtr ); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr) - * - * @brief Provide free mbufs for data reception on a connection. - * - * This function provides mbufs for data reception by the hardware. This - * function needs to be called by the user on a regular basis to ensure - * no packet loss. Providing free buffers is a connection-based feature; - * each connection can have different requirements in terms of buffer size - * number of buffers, recycling rate. This function could be invoked from - * within the context of a @a IxAtmdAccRxVcFreeLowCallback() callback - * for a particular VC - * - * Mbufs provided through this function call can be chained. They will be - * unchained internally. A call to this function with chained mbufs or - * multiple calls with unchained mbufs are equivalent, but calls with - * unchained mbufs are more efficients. - * - * Mbufs provided to this interface need to be able to hold at least one - * full cell payload (48/52 bytes, depending on service type). - * Chained buffers with a size less than the size supported by the hardware - * will be returned through the rx callback provided during the connect step. - * - * Failing to invoke this function prior to enabling the RX traffic - * can result in packet loss. - * - * This function is not reentrant for the same connId. - * - * This function does not use system resources and can be - * invoked from an interrupt context. - * - * @note - Over replenish is detected, and extra mbufs are returned through - * the rx callback provided during the connect step. - * - * @note - Mbuf provided to the replenish function should have a length greater or - * equal to 48/52 bytes according to service type. - * - * @note - The memory cache of mMbuf payload should be invalidated prior to Mbuf - * submission. Flushing the Mbuf headers is handled by IxAtmdAcc. - * - * @note - When a chained mbuf is provided, this function process the mbufs - * up to the hardware limit and invokes the user-supplied callback - * to release extra buffers. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcConnect - * - * @param connId @ref IxAtmConnId [in] - connection Id as returned from a succesfull call to - * @a IxAtmdAccRxVcConnect() - * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a mbuf structure to be used for data - * reception. The mbuf pointed to by this parameter can be chained - * to an other mbuf. - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcFreeReplenish() - * and the mbuf is now ready to use for incoming traffic. - * @return @li IX_ATMDACC_BUSY cannot process this request because - * the max number of outstanding free buffers has been reached - * or the internal resources have exhausted for this VC. - * The user is responsible for retrying this request later. - * @return @li IX_FAIL cannot process this request because of parameter - * errors or some unspecified internal error has occurred. - * - * @note - It is not always guaranteed the replenish step to be as fast as the - * hardware is consuming Rx Free mbufs. There is nothing in IxAtmdAcc to - * guarantee that replenish reaches the rxFree threshold level. If the - * threshold level is not reached, the next rxFree low notification for - * this channel will not be triggered. - * The preferred ways to replenish can be as follows (depending on - * applications and implementations) : - * @li Replenish in a rxFree low notification until the function - * ixAtmdAccRxVcFreeReplenish() returns IX_ATMDACC_BUSY - * @li Query the queue level using @sa ixAtmdAccRxVcFreeEntriesQuery, then - * , replenish using @a ixAtmdAccRxVcFreeReplenish(), then query the queue - * level again, and replenish if the threshold is still not reached. - * @li Trigger replenish from an other event source and use rxFree starvation - * to throttle the Rx traffic. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId, - unsigned int numberOfMbufs, - IxAtmdAccRxVcFreeLowCallback callback) - * - * @brief Configure the RX Free threshold value and register a callback - * to handle threshold notifications. - * - * The function ixAtmdAccRxVcFreeLowCallbackRegister sets the threshold value for - * a particular RX VC. When the number of buffers reaches this threshold - * the callback is invoked. - * - * This function should be called once per VC before RX traffic is - * enabled.This function will fail if the curent level of the free buffers - * is equal or less than the threshold value. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcFreeReplenish - * @sa ixAtmdAccRxVcFreeEntriesQuery - * @sa ixAtmdAccRxVcConnect - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * @param numberOfMbufs unsigned int [in] - threshold number of buffers. This number - * has to be a power of 2, one of the values 0,1,2,4,8,16,32.... - * The maximum value cannot be more than half of the rxFree queue - * size (which can be retrieved using @a ixAtmdAccRxVcFreeEntriesQuery() - * before any use of the @a ixAtmdAccRxVcFreeReplenish() function) - * @param callback @ref IxAtmdAccRxVcFreeLowCallback [in] - function telling the user that the number of - * free buffers has reduced to the threshold value. - * - * @return @li IX_SUCCESS Threshold set successfully. - * @return @li IX_FAIL parameter error or the current number of free buffers - * is less than or equal to the threshold supplied or some - * unspecified error has occrred. - * - * @note - the callback will be called when the threshold level will drop from - * exactly (numberOfMbufs + 1) to (numberOfMbufs). - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId, - unsigned int numberOfMbufs, - IxAtmdAccRxVcFreeLowCallback callback); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId, - unsigned int *numberOfMbufsPtr) - * - * @brief Get the number of rx mbufs the system can accept to replenish the - * the rx reception mechanism on a particular channel - * - * The ixAtmdAccRxVcFreeEntriesQuery function is used to retrieve the current - * number of available mbuf entries for reception, on a per-VC basis. This - * function can be used to know the number of mbufs which can be provided - * using @a ixAtmdAccRxVcFreeReplenish(). - * - * This function can be used from a timer context, or can be associated - * with a threshold event, or can be used inside an active polling - * mechanism which is under user control. - * - * This function is reentrant and does not use system resources and can - * be invoked from an interrupt context. - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * @param numberOfMbufsPtr unsigned int [out] - Pointer to the number of available entries. - * . This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the current number of mbufs not yet used for incoming traffic - * @return @li IX_FAIL invalid parameter - * - * @sa ixAtmdAccRxVcFreeReplenish - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId, - unsigned int *numberOfMbufsPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcEnable (IxAtmConnId connId) - * - * @brief Start the RX service on a VC. - * - * This functions kicks-off the traffic reception for a particular VC. - * Once invoked, incoming PDUs will be made available by the hardware - * and are eventually directed to the @a IxAtmdAccRxVcRxCallback() callback - * registered for the connection. - * - * If the traffic is already running, this function returns IX_SUCCESS. - * This function can be invoked many times. - * - * IxAtmdAccRxVcFreeLowCallback event will occur only after - * @a ixAtmdAccRxVcEnable() function is invoked. - * - * Before using this function, the @a ixAtmdAccRxVcFreeReplenish() function - * has to be used to replenish the RX Free queue. If not, incoming traffic - * may be discarded.and in the case of interrupt driven reception the - * @a IxAtmdAccRxVcFreeLowCallback() callback may be invoked as a side effect - * during a replenish action. - * - * This function is not reentrant and should not be used inside an - * interrupt context. - * - * For an VC connection this function can be called after a call to - * @a ixAtmdAccRxVcDisable() and should not be called after - * @a ixAtmdAccRxVcTryDisconnect() - * - * @sa ixAtmdAccRxVcDisable - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxVcFreeReplenish - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcEnable - * @return @li IX_ATMDACC_WARNING the channel is already enabled - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcEnable (IxAtmConnId connId); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcDisable (IxAtmConnId connId) - * - * @brief Stop the RX service on a VC. - * - * This functions stops the traffic reception for a particular VC connection. - * - * Once invoked, incoming Pdus are discarded by the hardware. Any Pdus - * pending will be freed to the user - * - * Hence once this function returns no more receive callbacks will be - * called for that VC. However, buffer free callbacks will be invoked - * until such time as all buffers supplied by the user have been freed - * back to the user - * - * Calling this function doe not invalidate the connId. - * @a ixAtmdAccRxVcEnable() can be invoked to enable Pdu reception again. - * - * If the traffic is already stopped, this function returns IX_SUCCESS. - * - * This function is not reentrant and should not be used inside an - * interrupt context. - * - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxVcEnable - * @sa ixAtmdAccRxVcDisable - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to @a - * IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcDisable(). - * @return @li IX_ATMDACC_WARNING the channel is already disabled - * @return @li IX_FAIL invalid parameters or some unspecified internal error occured - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcDisable (IxAtmConnId connId); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId) - * - * @brief Disconnect a VC from the RX service. - * - * This function deregisters the VC and guarantees that all resources - * associated with this VC are free. After its execution, the connection - * Id is not available. - * - * This function will fail until such time as all resources allocated to - * the VC connection have been freed. The user is responsible to delay and - * call again this function many times until a success status is returned. - * - * This function needs internal locks and should not be called from an - * interrupt context - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcDisable - * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources - * associated with the connection have been freed. - * @return @li IX_FAIL cannot process this request because of a parameter - * error - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmdAccUserId userId, - IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback, - IxAtmConnId * connIdPtr) - * - * @brief Connect to a Aal Pdu transmit service for a particular - * port/vpi/vci and service type. - * - * This function allows a user to connect to an Aal5/Aal0/OAM Pdu transmit service - * for a particular port/vpi/vci. It registers the callback and allocates - * internal resources and a Connection Id to be used in further API calls - * related to this VC. - * - * The function will setup VC transmit service on the specified on the - * specified port. A connId is the reference by which IxAtmdAcc refers to a - * connected VC. This identifier is the result of a succesful call - * to a connect function. This identifier is invalid after a - * sucessful call to a disconnect function. - * - * This function needs internal locks, and hence should not be called - * from an interrupt context. - * - * On return from @a ixAtmdAccTxVcConnect() with a failure status, the - * connection Id parameter is unspecified. Its value cannot be used. - * - * Calling this function for the same combination of port, Vpi, Vci and - * more than once without calling @a ixAtmdAccTxVcTryDisconnect() will result - * in a failure status. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service the client must format - * the PDU with an ATM cell header (excluding HEC) at the start of - * each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * For the OAM service an "OAM Tx channel" may be enabled for a port - * by establishing a single dedicated OAM Tx connection on that port. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. - * - * Calling this function before enabling the port will fail. - * - * @sa ixAtmdAccTxVcTryDisconnect - * @sa ixAtmdAccPortTxScheduledModeEnable - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port - * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI - * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI - * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service AAL5, AAL0_48, AAL0_52, or OAM - * @param userId @ref IxAtmdAccUserId [in] - user id to be used later during callbacks related - * to this channel - * @param bufferFreeCallback @ref IxAtmdAccTxVcBufferReturnCallback [in] - function called when mbufs - * transmission is complete. This parameter cannot be a null - * pointer. - * @param connIdPtr @ref IxAtmConnId [out] - Pointer to a connection Id. - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful call to @a IxAtmdAccRxVcConnect(). - * @return @li IX_ATMDACC_BUSY cannot process this request - * because no VC is available - * @return @li IX_FAIL - * parameter error, - * VC already in use, - * attempt to connect AAL service on reserved OAM VPI/VCI, - * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI, - * port is not initialised, - * or some other error occurs during processing. - * - * @note - Unscheduled mode is not supported in ixp425 1.0. Therefore, the - * function @a ixAtmdAccPortTxScheduledModeEnable() need to be called - * for this port before any establishing a Tx Connection - */ -PUBLIC IX_STATUS ixAtmdAccTxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmdAccUserId userId, - IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback, - IxAtmConnId * connIdPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcPduSubmit (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr, - IxAtmdAccClpStatus clp, - unsigned int numberOfCells) - * - * @brief Submit a Pdu for transmission on connection. - * - * A data user calls this function to submit an mbufs containing a Pdu - * to be transmitted. The buffer supplied can be chained and the Pdu it - * contains must be complete. - * - * The transmission behavior of this call depends on the operational mode - * of the port on which the connection is made. - * - * In unscheduled mode the mbuf will be submitted to the hardware - * immediately if sufficent resource is available. Otherwise the function - * will return failure. - * - * In scheduled mode the buffer is queued internally in IxAtmdAcc. The cell - * demand is made known to the traffic shaping entity. Cells from the - * buffers are MUXed onto the port some time later as dictated by the - * traffic shaping entity. The traffic shaping entity does this by sending - * transmit schedules to IxAtmdAcc via @a ixAtmdAccPortTxProcess() function call. - * - * Note that the dedicated OAM channel is scheduled just like any - * other channel. This means that any OAM traffic relating to an - * active AAL0/AAL5 connection will be scheduled independantly of the - * AAL0/AAL5 traffic for that connection. - * - * When transmission is complete, the TX Done mechanism will give the - * owmnership of these buffers back to the customer. The tx done mechanism - * must be in operation before transmission is attempted. - * - * For AAL0/OAM submitted AAL0 PDUs must be a multiple of the cell data - * size (48/52). AAL0_52 and OAM are raw cell services, and the client - * must format the PDU with an ATM cell header (excluding HEC) at the - * start of each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * - * @sa IxAtmdAccTxVcBufferReturnCallback - * @sa ixAtmdAccTxDoneDispatch - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a ixAtmdAccTxVcConnect() - * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a chained structure of mbufs to transmit. - * This parameter cannot be a null pointer. - * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. All cells of this pdu - * will be sent with the clp bit set - * @param numberOfCells unsigned int [in] - number of cells in the PDU. - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcPduSubmit() - * The pdu pointed by the mbufPtr parameter will be - * transmitted - * @return @li IX_ATMDACC_BUSY unable to process this request because - * internal resources are all used. The caller is responsible - * for retrying this request later. - * @return @li IX_FAIL unable to process this request because of error - * in the parameters (wrong connId supplied, - * or wrong mbuf pointer supplied), the total length of all buffers - * in the chain should be a multiple of the cell size - * ( 48/52 depending on the service type ), - * or unspecified error during processing - * - * @note - This function in not re-entrant for the same VC (e.g. : two - * thread cannot send PDUs for the same VC). But two threads can - * safely call this function with a different connection Id - * - * @note - In unscheduled mode, this function is not re-entrant on a per - * port basis. The size of pdus is limited to 8Kb. - * - * @note - 0-length mbufs should be removed from the chain before submission. - * The total length of the pdu (sdu + padding +trailer) has to be - * updated in the header of the first mbuf of a chain of mbufs. - * - * @note - Aal5 trailer information (UUI, CPI, SDU length) has to be supplied - * before submission. - * - * @note - The payload memory cache should be flushed, if needed, prior to - * transmission. Mbuf headers are flushed by IxAtmdAcc - * - * @note - This function does not use system resources and can be used - * inside an interrupt context - */ -PUBLIC IX_STATUS ixAtmdAccTxVcPduSubmit (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr, - IxAtmdAccClpStatus clp, - unsigned int numberOfCells); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId) - * - * @brief Disconnect from a Aal Pdu transmit service for a particular - * port/vpi/vci. - * - * This function deregisters the VC and guarantees that all resources - * associated with this VC are free. After its execution, the connection - * Id is not available. - * - * This function will fail until such time as all resources allocated to - * the VC connection have been freed. The user is responsible to delay - * and call again this function many times until a success status is - * returned. - * - * After its execution, the connection Id is not available. - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a ixAtmdAccTxVcConnect() - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcTryDisconnect() - * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources - * associated with the connection have been freed. This condition will - * disappear after Tx and TxDone is complete for this channel. - * @return @li IX_FAIL unable to process this request because of errors - * in the parameters (wrong connId supplied) - * - * @note - This function needs internal locks and should not be called - * from an interrupt context - * - * @note - If the @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED error does not - * clear after a while, this may be linked to a previous problem - * of cell overscheduling. Diabling the port and retry a disconnect - * will free the resources associated with this channel. - * - * @sa ixAtmdAccPortTxProcess - * - */ -PUBLIC IX_STATUS ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId); - -#endif /* IXATMDACC_H */ - -/** - * @} defgroup IxAtmdAccAPI - */ - - diff --git a/drivers/net/npe/include/IxAtmdAccCtrl.h b/drivers/net/npe/include/IxAtmdAccCtrl.h deleted file mode 100644 index 7b8734563a..0000000000 --- a/drivers/net/npe/include/IxAtmdAccCtrl.h +++ /dev/null @@ -1,1958 +0,0 @@ - -/** - * @file IxAtmdAccCtrl.h - * - * @date 20-Mar-2002 - * - * @brief IxAtmdAcc Public API - * - * This file contains the public API of IxAtmdAcc, related to the - * control functions of the component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ - -/** - * - * @defgroup IxAtmdAccCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Control API - * - * @brief The public API for the IXP400 Atm Driver Control component - * - * IxAtmdAcc is the low level interface by which AAL PDU get transmitted - * to,and received from the Utopia bus - * - * This part is related to the Control configuration - * - * @{ - */ - -#ifndef IXATMDACCCTRL_H -#define IXATMDACCCTRL_H - -#include "IxAtmdAcc.h" - -/* ------------------------------------------------------ - AtmdAccCtrl Data Types definition - ------------------------------------------------------ */ - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @def IX_ATMDACC_PORT_DISABLE_IN_PROGRESS -* -* @brief Port enable return code -* -* This constant is used to tell IxAtmDAcc user that the port disable -* functions are not complete. The user can call ixAtmdAccPortDisableComplete() -* to find out when the disable has finished. The port enable can then proceed. -* -*/ -#define IX_ATMDACC_PORT_DISABLE_IN_PROGRESS 5 - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @def IX_ATMDACC_ALLPDUS -* -* @brief All PDUs -* -* This constant is used to tell IxAtmDAcc to process all PDUs from -* the RX queue or the TX Done -* -* @sa IxAtmdAccRxDispatcher -* @sa IxAtmdAccTxDoneDispatcher -* -*/ -#define IX_ATMDACC_ALLPDUS 0xffffffff - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @brief Callback prototype for notification of available PDUs for - * an Rx Q. - * - * This a protoype for a function which is called when there is at - * least one Pdu available for processing on a particular Rx Q. - * - * This function should call @a ixAtmdAccRxDispatch() with - * the aprropriate number of parameters to read and process the Rx Q. - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxDispatcherRegister - * - * @param rxQueueId @ref IxAtmRxQueueId [in] indicates which RX queue to has Pdus to process. - * @param numberOfPdusToProcess unsigned int [in] indicates the minimum number of - * PDUs available to process all PDUs from the queue. - * @param reservedPtr unsigned int* [out] pointer to a int location which can - * be written to, but does not retain written values. This is - * provided to make this prototype compatible - * with @a ixAtmdAccRxDispatch() - * - * @return @li int - ignored. - * - */ -typedef IX_STATUS (*IxAtmdAccRxDispatcher) (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *reservedPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @brief Callback prototype for transmitted mbuf when threshold level is - * crossed. - * - * IxAtmdAccTxDoneDispatcher is the prototype of the user function - * which get called when pdus are completely transmitted. This function - * is likely to call the @a ixAtmdAccTxDoneDispatch() function. - * - * This function is called when the number of available pdus for - * reception is crossing the threshold level as defined - * in @a ixAtmdAccTxDoneDispatcherRegister() - * - * This function is called inside an Qmgr dispatch context. No system - * resource or interrupt-unsafe feature should be used inside this - * callback. - * - * Transmitted buffers recycling implementation is a sytem-wide mechanism - * and needs to be set before any traffic is started. If this threshold - * mechanism is not used, the user is responsible for polling the - * transmitted buffers with @a ixAtmdAccTxDoneDispatch() - * and @a ixAtmdAccTxDoneLevelQuery() functions. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa ixAtmdAccTxDoneDispatch - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdusToProcess unsigned int [in] - The current number of pdus currently - * available for recycling - * @param *reservedPtr unsigned int [out] - pointer to a int location which can be - * written to but does not retain written values. This is provided - * to make this prototype compatible - * with @a ixAtmdAccTxDoneDispatch() - * - * @return @li IX_SUCCESS This is provided to make - * this prototype compatible with @a ixAtmdAccTxDoneDispatch() - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. This is provided to make - * this prototype compatible with @a ixAtmdAccTxDoneDispatch() - * - */ -typedef IX_STATUS (*IxAtmdAccTxDoneDispatcher) (unsigned int numberOfPdusToProcess, - unsigned int *reservedPtr); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief Notification that the threshold number of scheduled cells -* remains in a port's transmit Q. -* -* The is the prototype for of the user notification function which -* gets called on a per-port basis, when the number of remaining -* scheduled cells to be transmitted decreases to the threshold level. -* The number of cells passed as a parameter can be used for scheduling -* purposes as the maximum number of cells that can be passed in a -* schedule table to the @a ixAtmdAccPortTxProcess() function. -* -* @sa ixAtmdAccPortTxCallbackRegister -* @sa ixAtmdAccPortTxProcess -* @sa ixAtmdAccPortTxFreeEntriesQuery -* -* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] -* @param numberOfAvailableCells unsigned int [in] - number of available -* cell entries.for the port -* -* @note - This functions shall not use system resources when used -* inside an interrupt context. -* -*/ -typedef void (*IxAtmdAccPortTxLowCallback) (IxAtmLogicalPort port, - unsigned int numberOfAvailableCells); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief Prototype to submit cells for transmission -* -* IxAtmdAccTxVcDemandUpdateCallback is the prototype of the callback -* function used by AtmD to notify an ATM Scheduler that the user of -* a VC has submitted cells for transmission. -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be updated -* is established -* @param vcId int [in] - Identifies the VC to be updated. This is the value -* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call . -* @param numberOfCells unsigned int [in] - Indicates how many ATM cells should be added -* to the queue for this VC. -* -* @return @li IX_SUCCESS the function is registering the cell demand for -* this VC. -* @return @li IX_FAIL the function cannot register cell for this VC : the -* scheduler maybe overloaded or misconfigured -* -*/ -typedef IX_STATUS (*IxAtmdAccTxVcDemandUpdateCallback) (IxAtmLogicalPort port, - int vcId, - unsigned int numberOfCells); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief prototype to remove all currently queued cells from a -* registered VC -* -* IxAtmdAccTxVcDemandClearCallback is the prototype of the function -* to remove all currently queued cells from a registered VC. The -* pending cell count for the specified VC is reset to zero. After the -* use of this callback, the scheduler shall not schedule more cells -* for this VC. -* -* This callback function is called during a VC disconnection -* @a ixAtmdAccTxVcTryDisconnect() -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* @sa ixAtmdAccTxVcTryDisconnect -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be cleared -* is established -* @param vcId int [in] - Identifies the VC to be cleared. This is the value -* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call . -* -* @return none -* -*/ -typedef void (*IxAtmdAccTxVcDemandClearCallback) (IxAtmLogicalPort port, - int vcId); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief prototype to get a scheduler vc id -* -* IxAtmdAccTxSchVcIdGetCallback is the prototype of the function to get -* a scheduler vcId -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM logical port on which the VC is -* established -* @param vpi unsigned int [in] - For AAL0/AAL5 specifies the ATM vpi on which the -* VC is established. -* For OAM specifies the dedicated "OAM Tx channel" VPI. -* @param vci unsigned int [in] - For AAL0/AAL5 specifies the ATM vci on which the -* VC is established. -* For OAM specifies the dedicated "OAM Tx channel" VCI. -* @param connId @ref IxAtmConnId [in] - specifies the IxAtmdAcc connection Id already -* associated with this VC -* @param vcId int* [out] - pointer to a vcId -* -* @return @li IX_SUCCESS the function is returning a Scheduler vcId for this -* VC -* @return @li IX_FAIL the function cannot process scheduling for this VC. -* the contents of vcId is unspecified -* -*/ -typedef IX_STATUS (*IxAtmdAccTxSchVcIdGetCallback) (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmConnId connId, - int *vcId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxDispatcherRegister ( - IxAtmRxQueueId queueId, - IxAtmdAccRxDispatcher callback) - * - * @brief Register a notification callback to be invoked when there is - * at least one entry on a particular Rx queue. - * - * This function registers a callback to be invoked when there is at - * least one entry in a particular queue. The registered callback is - * called every time when the hardware adds one or more pdus to the - * specified Rx queue. - * - * This function cannot be used when a Rx Vc using this queue is - * already existing. - * - * @note -The callback function can be the API function - * @a ixAtmdAccRxDispatch() : every time the threhold level - * of the queue is reached, the ixAtmdAccRxDispatch() is - * invoked to remove all entries from the queue. - * - * @sa ixAtmdAccRxDispatch - * @sa IxAtmdAccRxDispatcher - * - * @param queueId @ref IxAtmRxQueueId [in] RX queue identification - * @param callback @ref IxAtmdAccRxDispatcher [in] function triggering the delivery of incoming - * traffic. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS Successful call to @a ixAtmdAccRxDispatcherRegister() - * @return @li IX_FAIL error in the parameters, or there is an - * already active RX VC for this queue or some unspecified - * internal error occurred. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxDispatcherRegister ( - IxAtmRxQueueId queueId, - IxAtmdAccRxDispatcher callback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr) - * - * - * @brief Control function which executes Rx processing for a particular - * Rx stream. - * - * The @a IxAtmdAccRxDispatch() function is used to process received Pdus - * available from one of the two incoming RX streams. When this function - * is invoked, the incoming traffic (up to the number of PDUs passed as - * a parameter) will be transferred to the IxAtmdAcc users through the - * callback @a IxAtmdAccRxVcRxCallback(), as registered during the - * @a ixAtmdAccRxVcConnect() call. - * - * The user receive callbacks will be executed in the context of this - * function. - * - * Failing to use this function on a regular basis when there is traffic - * will block incoming traffic and can result in Pdus being dropped by - * the hardware. - * - * This should be used to control when received pdus are handed off from - * the hardware to Aal users from a particluar stream. The function can - * be used from a timer context, or can be registered as a callback in - * response to an rx stream threshold event, or can be used inside an - * active polling mechanism which is under user control. - * - * @note - The signature of this function is directly compatible with the - * callback prototype which can be register with @a ixAtmdAccRxDispatcherRegister(). - * - * @sa ixAtmdAccRxDispatcherRegister - * @sa IxAtmdAccRxVcRxCallback - * @sa ixAtmdAccRxVcFreeEntriesQuery - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which RX queue to process. - * @param numberOfPdusToProcess unsigned int [in] - indicates the maxiumum number of PDU to - * remove from the RX queue. A value of IX_ATMDACC_ALLPDUS indicates - * to process all PDUs from the queue. This includes at least the PDUs - * in the queue when the fuction is invoked. Because of real-time - * constraints, there is no guarantee thatthe queue will be empty - * when the function exits. If this parameter is greater than the - * number of entries of the queues, the function will succeed - * and the parameter numberOfPdusProcessedPtr will reflect the exact - * number of PDUs processed. - * @param *numberOfPdusProcessedPtr unsigned int [out] - indicates the actual number of PDU - * processed during this call. This parameter cannot be a null - * pointer. - * - * @return @li IX_SUCCESS the number of PDUs as indicated in - * numberOfPdusProcessedPtr are removed from the RX queue and the VC callback - * are called. - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr) - * - * @brief Query the number of entries in a particular RX queue. - * - * This function is used to retrieve the number of pdus received by - * the hardware and ready for distribution to users. - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query. - * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of available - * PDUs in the RX queue. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the - * number of incoming pdus waiting in this queue - * @return @li IX_FAIL an error occurs during processing. - * The value in numberOfPdusPtr is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr) - * - * @brief Query the size of a particular RX queue. - * - * This function is used to retrieve the number of pdus the system is - * able to queue when reception is complete. - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query. - * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of pdus - * the system is able to queue in the RX queue. This parameter - * cannot be a null pointer. - * - * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the - * number of pdus the system is able to queue. - * @return @li IX_FAIL an error occurs during processing. - * The value in numberOfPdusPtr is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port, - unsigned int *numberOfCellsPtr) - * - * @brief Get the number of available cells the system can accept for - * transmission. - * - * The function is used to retrieve the number of cells that can be - * queued for transmission to the hardware. - * - * This number is based on the worst schedule table where one cell - * is stored in one schedule table entry, depending on the pdus size - * and mbuf size and fragmentation. - * - * This function doesn't use system resources and can be used from a - * timer context, or can be associated with a threshold event, or can - * be used inside an active polling mechanism - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param numberOfCellsPtr unsigned int* [out] - number of available cells. - * This parameter cannot be a null pointer. - * - * @sa ixAtmdAccPortTxProcess - * - * @return @li IX_SUCCESS numberOfCellsPtr contains the number of cells that can be scheduled - * for this port. - * @return @li IX_FAIL error in the parameters, or some processing error - * occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port, - unsigned int *numberOfCellsPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port, - unsigned int numberOfCells, - IxAtmdAccPortTxLowCallback callback) - * - * @brief Configure the Tx port threshold value and register a callback to handle - * threshold notifications. - * - * This function sets the threshold in cells - * - * @sa ixAtmdAccPortTxCallbackRegister - * @sa ixAtmdAccPortTxProcess - * @sa ixAtmdAccPortTxFreeEntriesQuery - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param numberOfCells unsigned int [in] - threshold value which triggers the callback - * invocation, This number has to be one of the - * values 0,1,2,4,8,16,32 .... - * The maximum value cannot be more than half of the txVc queue - * size (which can be retrieved using @a ixAtmdAccPortTxFreeEntriesQuery() - * before any Tx traffic is sent for this port) - * @param callback @ref IxAtmdAccPortTxLowCallback [in] - callback function to invoke when the threshold - * level is reached. - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS Successful call to @a ixAtmdAccPortTxCallbackRegister() - * @return @li IX_FAIL error in the parameters, Tx channel already set for this port - * threshold level is not correct or within the range regarding the - * queue size:or unspecified error during processing: - * - * @note - This callback function get called when the threshold level drops from - * (numberOfCells+1) cells to (numberOfCells) cells - * - * @note - This function should be called during system initialisation, - * outside an interrupt context - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port, - unsigned int numberOfCells, - IxAtmdAccPortTxLowCallback callback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port, - IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback, - IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback, - IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback) - * - * @brief Put the port into Scheduled Mode - * - * This function puts the specified port into scheduled mode of - * transmission which means an external s/w entity controls the - * transmission of cells on this port. This faciltates traffic shaping on - * the port. - * - * Any buffers submitted on a VC for this port will be queued in IxAtmdAcc. - * The transmission of these buffers to and by the hardware will be driven - * by a transmit schedule submitted regulary in calls to - * @a ixAtmdAccPortTxProcess() by traffic shaping entity. - * - * The transmit schedule is expected to be dynamic in nature based on - * the demand in cells for each VC on the port. Hence the callback - * parameters provided to this function allow IxAtmdAcc to inform the - * shaping entity of demand changes for each VC on the port. - * - * By default a port is in Unscheduled Mode so if this function is not - * called, transmission of data is done without sheduling rules, on a - * first-come, first-out basis. - * - * Once a port is put in scheduled mode it cannot be reverted to - * un-scheduled mode. Note that unscheduled mode is not supported - * in ixp425 1.0 - * - * @note - This function should be called before any VCs have be - * connected on a port. Otherwise this function call will return failure. - * - * @note - This function uses internal locks and should not be called from - * an interrupt context - * - * @sa IxAtmdAccTxVcDemandUpdateCallback - * @sa IxAtmdAccTxVcDemandClearCallback - * @sa IxAtmdAccTxSchVcIdGetCallback - * @sa ixAtmdAccPortTxProcess - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vcDemandUpdateCallback @ref IxAtmdAccTxVcDemandUpdateCallback [in] - callback function used to update - * the number of outstanding cells for transmission. This parameter - * cannot be a null pointer. - * @param vcDemandClearCallback @ref IxAtmdAccTxVcDemandClearCallback [in] - callback function used to remove all - * clear the number of outstanding cells for a VC. This parameter - * cannot be a null pointer. - * @param vcIdGetCallback @ref IxAtmdAccTxSchVcIdGetCallback [in] - callback function used to exchange vc - * Identifiers between IxAtmdAcc and the entity supplying the - * transmit schedule. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS scheduler registration is complete and the port - * is now in scheduled mode. - * @return @li IX_FAIL failed (wrong parameters, or traffic is already - * enabled on this port, possibly without ATM shaping) - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port, - IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback, - IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback, - IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxProcess (IxAtmLogicalPort port, - IxAtmScheduleTable* scheduleTablePtr) - * - * @brief Transmit queue cells to the H/W based on the supplied schedule - * table. - * - * This function @a ixAtmdAccPortTxProcess() process the schedule - * table provided as a parameter to the function. As a result cells are - * sent to the underlaying hardware for transmission. - * - * The schedule table is executed in its entirety or not at all. So the - * onus is on the caller not to submit a table containing more cells than - * can be transmitted at that point. The maximum numbers that can be - * transmitted is guaranteed to be the number of cells as returned by the - * function @a ixAtmdAccPortTxFreeEntriesQuery(). - * - * When the scheduler is invoked on a threshold level, IxAtmdAcc gives the - * minimum number of cells (to ensure the callback will fire again later) - * and the maximum number of cells that @a ixAtmdAccPortTxProcess() - * will be able to process (assuming the ATM scheduler is able - * to produce the worst-case schedule table, i.e. one entry per cell). - * - * When invoked ouside a threshold level, the overall number of cells of - * the schedule table should be less than the number of cells returned - * by the @a ixAtmdAccPortTxFreeEntriesQuery() function. - * - * After invoking the @a ixAtmdAccPortTxProcess() function, it is the - * user choice to query again the queue level with the function - * @a ixAtmdAccPortTxFreeEntriesQuery() and, depending on a new cell - * number, submit an other schedule table. - * - * IxAtmdAcc will check that the number of cells in the schedule table - * is compatible with the current transmit level. If the - * - * Obsolete or invalid connection Id will be silently discarded. - * - * This function is not reentrant for the same port. - * - * This functions doesn't use system resources and can be used inside an - * interrupt context. - * - * This function is used as a response to the hardware requesting more - * cells to transmit. - * - * @sa ixAtmdAccPortTxScheduledModeEnable - * @sa ixAtmdAccPortTxFreeEntriesQuery - * @sa ixAtmdAccPortTxCallbackRegister - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param scheduleTablePtr @ref IxAtmScheduleTable* [in] - pointer to a scheduler update table. The - * content of this table is not modified by this function. This - * parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the schedule table process is complete - * and cells are transmitted to the hardware - * @return @li IX_ATMDACC_WARNING : Traffic will be dropped: the schedule table exceed - * the hardware capacity If this error is ignored, further traffic - * and schedule will work correctly. - * Overscheduling does not occur when the schedule table does - * not contain more entries that the number of free entries returned - * by @a ixAtmdAccPortTxFreeEntriesQuery(). - * However, Disconnect attempts just after this error will fail permanently - * with the error code @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED, and it is - * necessary to disable the port to make @a ixAtmdAccTxVcTryDisconnect() - * successful. - * @return @li IX_FAIL a wrong parameter is supplied, or the format of - * the schedule table is invalid, or the port is not Enabled, or - * an internal severe error occured. No cells is transmitted to the hardware - * - * @note - If the failure is linked to an overschedule of data cells - * the result is an inconsistency in the output traffic (one or many - * cells may be missing and the traffic contract is not respected). - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxProcess (IxAtmLogicalPort port, - IxAtmScheduleTable* scheduleTablePtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr) - * - * @brief Process a number of pending transmit done pdus from the hardware. - * - * As a by-product of Atm transmit operation buffers which transmission - * is complete need to be recycled to users. This function is invoked - * to service the oustanding list of transmitted buffers and pass them - * to VC users. - * - * Users are handed back pdus by invoking the free callback registered - * during the @a ixAtmdAccTxVcConnect() call. - * - * There is a single Tx done stream servicing all active Atm Tx ports - * which can contain a maximum of 64 entries. If this stream fills port - * transmission will stop so this function must be call sufficently - * frequently to ensure no disruption to the transmit operation. - * - * This function can be used from a timer context, or can be associated - * with a TxDone level threshold event (see @a ixAtmdAccTxDoneDispatcherRegister() ), - * or can be used inside an active polling mechanism under user control. - * - * For ease of use the signature of this function is compatible with the - * TxDone threshold event callback prototype. - * - * This functions can be used inside an interrupt context. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa IxAtmdAccTxVcBufferReturnCallback - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdusToProcess unsigned int [in] - maxiumum number of pdus to remove - * from the TX Done queue - * @param *numberOfPdusProcessedPtr unsigned int [out] - number of pdus removed from - * the TX Done queue. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the number of pdus as indicated in - * numberOfPdusToProcess are removed from the TX Done hardware - * and passed to the user through the Tx Done callback registered - * during a call to @a ixAtmdAccTxVcConnect() - * @return @li IX_FAIL invalid parameters or numberOfPdusProcessedPtr is - * a null pointer or some unspecified internal error occured. - * - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr) - * - * @brief Query the current number of transmit pdus ready for - * recycling. - * - * This function is used to get the number of transmitted pdus which - * the hardware is ready to hand back to user. - * - * This function can be used from a timer context, or can be associated - * with a threshold event, on can be used inside an active polling - * mechanism - * - * @sa ixAtmdAccTxDoneDispatch - * - * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus transmitted - * at the time of this function call, and ready for recycling - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS numberOfPdusPtr contains the number of pdus - * ready for recycling at the time of this function call - * - * @return @li IX_FAIL wrong parameter (null pointer as parameter).or - * unspecified rocessing error occurs..The value in numberOfPdusPtr - * is unspecified. - * - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr) - * - * @brief Query the TxDone queue size. - * - * This function is used to get the number of pdus which - * the hardware is able to store after transmission is complete - * - * The returned value can be used to set a threshold and enable - * a callback to be notified when the number of pdus is going over - * the threshold. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * - * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus the system - * is able to queue after transmission - * - * @return @li IX_SUCCESS numberOfPdusPtr contains the the number of - * pdus the system is able to queue after transmission - * @return @li IX_FAIL wrong parameter (null pointer as parameter).or - * unspecified rocessing error occurs..The value in numberOfPdusPtr - * is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus, - IxAtmdAccTxDoneDispatcher notificationCallback) - * - * @brief Configure the Tx Done stream threshold value and register a - * callback to handle threshold notifications. - * - * This function sets the threshold level in term of number of pdus at - * which the supplied notification function should be called. - * - * The higher the threshold value is, the less events will be necessary - * to process transmitted buffers. - * - * Transmitted buffers recycling implementation is a sytem-wide mechanism - * and needs to be set prior any traffic is started. If this threshold - * mechanism is not used, the user is responsible for polling the - * transmitted buffers thanks to @a ixAtmdAccTxDoneDispatch() and - * @a ixAtmdAccTxDoneLevelQuery() functions. - * - * This function should be called during system initialisation outside - * an interrupt context - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa ixAtmdAccTxDoneDispatch - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdus unsigned int [in] - The number of TxDone pdus which triggers the - * callback invocation This number has to be a power of 2, one of the - * values 0,1,2,4,8,16,32 ... - * The maximum value cannot be more than half of the txDone queue - * size (which can be retrieved using @a ixAtmdAccTxDoneQueueSizeQuery()) - * @param notificationCallback @ref IxAtmdAccTxDoneDispatcher [in] - The function to invoke. (This - * parameter can be @a ixAtmdAccTxDoneDispatch()).This - * parameter ust not be a null pointer. - * - * @return @li IX_SUCCESS Successful call to ixAtmdAccTxDoneDispatcherRegister - * @return @li IX_FAIL error in the parameters: - * - * @note - The notificationCallback will be called exactly when the threshold level - * will increase from (numberOfPdus) to (numberOfPdus+1) - * - * @note - If there is no Tx traffic, there is no guarantee that TxDone Pdus will - * be released to the user (when txDone level is permanently under the threshold - * level. One of the preffered way to return resources to the user is to use - * a mix of txDone notifications, used together with a slow - * rate timer and an exclusion mechanism protecting from re-entrancy - * - * @note - The TxDone threshold will only hand back buffers when the threshold level is - * crossed. Setting this threshold to a great number reduce the interrupt rate - * and the cpu load, but also increase the number of outstanding mbufs and has - * a system wide impact when these mbufs are needed by other components. - * - */ -PUBLIC IX_STATUS ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus, - IxAtmdAccTxDoneDispatcher notificationCallback); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to Utopia config - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @defgroup IxAtmdAccUtopiaCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Utopia Control API - * - * @brief The public API for the IXP400 Atm Driver Control component - * - * IxAtmdAcc is the low level interface by which AAL PDU get - * transmitted to,and received from the Utopia bus - * - * This part is related to the UTOPIA configuration. - * - * @{ - */ - -/** - * - * @brief Utopia configuration - * - * This structure is used to set the Utopia parameters - * @li contains the values of Utopia registers, to be set during initialisation - * @li contains debug commands for NPE, to be used during development steps - * - * @note - the exact description of all parameters is done in the Utopia reference - * documents. - * - */ -typedef struct -{ - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxConfig_ - * @brief Utopia Tx Config Register - */ - struct UtTxConfig_ - { - - unsigned int reserved_1:1; /**< [31] These bits are always 0.*/ - unsigned int txInterface:1; /**< [30] Utopia Transmit Interface. The following encoding - * is used to set the Utopia Transmit interface as ATM master - * or PHY slave: - * @li 1 - PHY - * @li 0 - ATM - */ - unsigned int txMode:1; /**< [29] Utopia Transmit Mode. The following encoding is used - * to set the Utopia Transmit mode to SPHY or MPHY: - * @li 1 - SPHY - * @li 0 - MPHY - */ - unsigned int txOctet:1; /**< [28] Utopia Transmit cell transfer protocol. Used to set - * the Utopia cell transfer protocol to Octet-level handshaking. - * Note this is only applicable in SPHY mode. - * @li 1 - Octet-handshaking enabled - * @li 0 - Cell-handshaking enabled - */ - unsigned int txParity:1; /**< [27] Utopia Transmit parity enabled when set. TxEvenParity - * defines the parity format odd/even. - * @li 1 - Enable Parity generation. - * @li 0 - ut_op_prty held low. - */ - unsigned int txEvenParity:1; /**< [26] Utopia Transmit Parity Mode - * @li 1 - Even Parity Generated. - * @li 0 - Odd Parity Generated. - */ - unsigned int txHEC:1; /**< [25] Header Error Check Insertion Mode. Specifies if the transmit - * cell header check byte is calculated and inserted when set. - * @li 1 - Generate HEC. - * @li 0 - Disable HEC generation. - */ - unsigned int txCOSET:1; /**< [24] If enabled the HEC is Exclusive-OR'ed with the value 0x55 before - * being presented on the Utopia bus. - * @li 1 - Enable HEC ExOR with value 0x55 - * @li 0 - Use generated HEC value. - */ - - unsigned int reserved_2:1; /**< [23] These bits are always 0 - */ - unsigned int txCellSize:7; /**< [22:16] Transmit expected cell size. Configures the cell size - * for the transmit module: Values between 52-64 are valid. - */ - unsigned int reserved_3:3; /**< [15:13] These bits are always 0 */ - unsigned int txAddrRange:5; /**< [12:8] When configured as an ATM master in MPHY mode this - * register specifies the upper limit of the PHY polling logical - * range. The number of active PHYs are TxAddrRange + 1. - */ - unsigned int reserved_4:3; /**< [7:5] These bits are always 0 */ - unsigned int txPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register - * specifies the physical address of the PHY. - */ - } - - utTxConfig; /**< Tx config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxStatsConfig_ - * @brief Utopia Tx stats Register - */ - struct UtTxStatsConfig_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCStatsTxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] or PHY Address[4] */ - - unsigned int pti:3; /**< [3:1] ATM PTI [2:0] or PHY Address[3:1] - @li Note: if VCStatsTxPTI is set to 0 the PTI field is ignored in test. - @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port - address as defined by this register is used for ATM statistics [4:0]. */ - - unsigned int clp:1; /**< [0] ATM CLP or PHY Address [0] - @li Note: if VCStatsTxCLP is set to 0 the CLP field is ignored in test. - @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port - address as defined by this register is used for ATM statistics [4:0]. */ - } - - utTxStatsConfig; /**< Tx stats config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxDefineIdle_ - * @brief Utopia Tx idle cells Register - */ - struct UtTxDefineIdle_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCIdleTxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */ - - unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0] - @li Note: if VCIdleTxPTI is set to 0 the PTI field is ignored in test.*/ - - unsigned int clp:1; /**< [0] ATM CLP [0] - @li Note: if VCIdleTxCLP is set to 0 the CLP field is ignored in test.*/ - } - - utTxDefineIdle; /**< Tx idle cell config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxEnableFields_ - * @brief Utopia Tx ienable fields Register - */ - struct UtTxEnableFields_ - { - - unsigned int defineTxIdleGFC:1; /**< [31] This register is used to include or exclude the GFC - field of the ATM header when testing for Idle cells. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored.*/ - - unsigned int defineTxIdlePTI:1; /**< [30] This register is used to include or exclude the PTI - field of the ATM header when testing for Idle cells. - @li 1 - PTI field is valid - @li 0 - PTI field ignored.*/ - - unsigned int defineTxIdleCLP:1; /**< [29] This register is used to include or - exclude the CLP field of the ATM header when testing for Idle cells. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored. */ - - unsigned int phyStatsTxEnb:1; /**< [28] This register is used to enable or disable ATM - statistics gathering based on the specified PHY address as defined - in TxStatsConfig register. - @li 1 - Enable statistics for specified transmit PHY address. - @li 0 - Disable statistics for specified transmit PHY address. */ - - unsigned int vcStatsTxEnb:1; /**< [27] This register is used to change the ATM - statistics-gathering mode from the specified logical PHY address - to a specific VPI/VCI address. - @li 1 - Enable statistics for specified VPI/VCI address. - @li 0 - Disable statistics for specified VPI/VCI address */ - - unsigned int vcStatsTxGFC:1; /**< [26] This register is used to include or exclude the GFC - field of the ATM header when ATM VPI/VCI statistics are enabled. - GFC is only available at the UNI and uses the first 4-bits of - the VPI field. - @li 1 - GFC field is valid - @li 0 - GFC field ignored.*/ - - unsigned int vcStatsTxPTI:1; /**< [25] This register is used to include or exclude the PTI - field of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - PTI field is valid - @li 0 - PTI field ignored.*/ - - unsigned int vcStatsTxCLP:1; /**< [24] This register is used to include or exclude the CLP - field of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - CLP field is valid - @li 0 - CLP field ignored. */ - - unsigned int reserved_1:3; /**< [23-21] These bits are always 0 */ - - unsigned int txPollStsInt:1; /**< [20] Enable the assertion of the ucp_tx_poll_sts condition - where there is a change in polling status. - @li 1 - ucp_tx_poll_sts asserted whenever there is a change in status - @li 0 - ucp_tx_poll_sts asserted if ANY transmit PHY is available - */ - unsigned int txCellOvrInt:1; /**< [19] Enable TxCellCount overflow CBI Transmit Status condition - assertion. - @li 1 - If TxCellCountOvr is set assert the Transmit Status Condition. - @li 0 - No CBI Transmit Status condition assertion */ - - unsigned int txIdleCellOvrInt:1; /**< [18] Enable TxIdleCellCount overflow Transmit Status Condition - @li 1 - If TxIdleCellCountOvr is set assert the Transmit Status Condition - @li 0 - No CBI Transmit Status condition assertion..*/ - - unsigned int enbIdleCellCnt:1; /**< [17] Enable Transmit Idle Cell Count. - @li 1 - Enable count of Idle cells transmitted. - @li 0 - No count is maintained. */ - - unsigned int enbTxCellCnt:1; /**< [16] Enable Transmit Valid Cell Count of non-idle/non-error cells - @li 1 - Enable count of valid cells transmitted- non-idle/non-error - @li 0 - No count is maintained.*/ - - unsigned int reserved_2:16; /**< [15:0] These bits are always 0 */ - } utTxEnableFields; /**< Tx enable Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable0_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable0_ - { - - unsigned int phy0:5; /**< [31-27] Tx Mapping value of logical phy 0 */ - - unsigned int phy1:5; /**< [26-22] Tx Mapping value of logical phy 1 */ - - unsigned int phy2:5; /**< [21-17] Tx Mapping value of logical phy 2 */ - - unsigned int reserved_1:1; /**< [16] These bits are always 0.*/ - - unsigned int phy3:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy4:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy5:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable0; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable1_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable1_ - { - - unsigned int phy6:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy7:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy8:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy9:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy10:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy11:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable1; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable2_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable2_ - { - - unsigned int phy12:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy13:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy14:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy15:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy16:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy17:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable2; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable3_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable3_ - { - - unsigned int phy18:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy19:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy20:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy21:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy22:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy23:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable3; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable4_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable4_ - { - - unsigned int phy24:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy25:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy26:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy27:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy28:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy29:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable4; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable5_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable5_ - { - - unsigned int phy30:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */ - - } utTxTransTable5; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxConfig_ - * @brief Utopia Rx config Register - */ - struct UtRxConfig_ - { - - unsigned int rxInterface:1; /**< [31] Utopia Receive Interface. The following encoding is used - to set the Utopia Receive interface as ATM master or PHY slave: - @li 1 - PHY - @li 0 - ATM */ - - unsigned int rxMode:1; /**< [30] Utopia Receive Mode. The following encoding is used to set - the Utopia Receive mode to SPHY or MPHY: - @li 1 - SPHY - @li 0 - MPHY */ - - unsigned int rxOctet:1; /**< [29] Utopia Receive cell transfer protocol. Used to set the Utopia - cell transfer protocol to Octet-level handshaking. Note this is only - applicable in SPHY mode. - @li 1 - Octet-handshaking enabled - @li 0 - Cell-handshaking enabled */ - - unsigned int rxParity:1; /**< [28] Utopia Receive Parity Checking enable. - @li 1 - Parity checking enabled - @li 0 - Parity checking disabled */ - - unsigned int rxEvenParity:1;/**< [27] Utopia Receive Parity Mode - @li 1 - Check for Even Parity - @li 0 - Check for Odd Parity.*/ - - unsigned int rxHEC:1; /**< [26] RxHEC Header Error Check Mode. Enables/disables cell header - error checking on the received cell header. - @li 1 - HEC checking enabled - @li 0 - HEC checking disabled */ - - unsigned int rxCOSET:1; /**< [25] If enabled the HEC is Exclusive-OR'ed with the value 0x55 - before being tested with the received HEC. - @li 1 - Enable HEC ExOR with value 0x55. - @li 0 - Use generated HEC value.*/ - - unsigned int rxHECpass:1; /**< [24] Specifies if the incoming cell HEC byte should be transferred - after optional processing to the NPE2 Coprocessor Bus Interface or - if it should be discarded. - @li 1 - HEC maintained 53-byte/UDC cell sent to NPE2. - @li 0 - HEC discarded 52-byte/UDC cell sent to NPE2 coprocessor.*/ - - unsigned int reserved_1:1; /**< [23] These bits are always 0 */ - - unsigned int rxCellSize:7; /**< [22:16] Receive cell size. Configures the receive cell size. - Values between 52-64 are valid */ - - unsigned int rxHashEnbGFC:1; /**< [15] Specifies if the VPI field [11:8]/GFC field should be - included in the Hash data input or if the bits should be padded - with 1'b0. - @li 1 - VPI [11:8]/GFC field valid and used in Hash residue calculation. - @li 0 - VPI [11:8]/GFC field padded with 1'b0 */ - - unsigned int rxPreHash:1; /**< [14] Enable Pre-hash value generation. Specifies if the - incoming cell data should be pre-hashed to allow VPI/VCI header look-up - in a hash table. - @li 1 - Pre-hashing enabled - @li 0 - Pre-hashing disabled */ - - unsigned int reserved_2:1; /**< [13] These bits are always 0 */ - - unsigned int rxAddrRange:5; /**< [12:8] In ATM master, MPHY mode, - * this register specifies the upper - * limit of the PHY polling logical range. The number of active PHYs are - * RxAddrRange + 1. - */ - unsigned int reserved_3:3; /**< [7-5] These bits are always 0 .*/ - unsigned int rxPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register - * specifies the physical address of the PHY. - */ - } utRxConfig; /**< Rx config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxStatsConfig_ - * @brief Utopia Rx stats config Register - */ - struct UtRxStatsConfig_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCStatsRxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] VCI [15:0] or PHY Address [4] */ - - unsigned int pti:3; /**< [3:1] PTI [2:0] or or PHY Address [3:1] - @li Note: if VCStatsRxPTI is set to 0 the PTI field is ignored in test. - @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used - for statistics gathering.. */ - - unsigned int clp:1; /**< [0] CLP [0] or PHY Address [0] - @li Note: if VCStatsRxCLP is set to 0 the CLP field is ignored in test. - @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used - for statistics gathering.. */ - } utRxStatsConfig; /**< Rx stats config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxDefineIdle_ - * @brief Utopia Rx idle cells config Register - */ - struct UtRxDefineIdle_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCIdleRxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */ - - unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0] - @li Note: if VCIdleRxPTI is set to 0 the PTI field is ignored in test.*/ - - unsigned int clp:1; /**< [0] ATM CLP [0] - @li Note: if VCIdleRxCLP is set to 0 the CLP field is ignored in test.*/ - } utRxDefineIdle; /**< Rx idle cell config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxEnableFields_ - * @brief Utopia Rx enable Register - */ - struct UtRxEnableFields_ - { - - unsigned int defineRxIdleGFC:1;/**< [31] This register is used to include or exclude the GFC - field of the ATM header when testing for Idle cells. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored.*/ - - unsigned int defineRxIdlePTI:1;/**< [30] This register is used to include or exclude the PTI - field of the ATM header when testing for Idle cells. - @li 1 - PTI field is valid. - @li 0 - PTI field ignored.*/ - - unsigned int defineRxIdleCLP:1;/**< [29] This register is used to include or exclude the CLP - field of the ATM header when testing for Idle cells. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored.*/ - - unsigned int phyStatsRxEnb:1;/**< [28] This register is used to enable or disable ATM statistics - gathering based on the specified PHY address as defined in RxStatsConfig - register. - @li 1 - Enable statistics for specified receive PHY address. - @li 0 - Disable statistics for specified receive PHY address.*/ - - unsigned int vcStatsRxEnb:1;/**< [27] This register is used to enable or disable ATM statistics - gathering based on a specific VPI/VCI address. - @li 1 - Enable statistics for specified VPI/VCI address. - @li 0 - Disable statistics for specified VPI/VCI address.*/ - - unsigned int vcStatsRxGFC:1;/**< [26] This register is used to include or exclude the GFC field - of the ATM header when ATM VPI/VCI statistics are enabled. GFC is only - available at the UNI and uses the first 4-bits of the VPI field. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored. */ - - unsigned int vcStatsRxPTI:1;/**< [25] This register is used to include or exclude the PTI field - of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - PTI field is valid. - @li 0 - PTI field ignored.*/ - - unsigned int vcStatsRxCLP:1;/**< [24] This register is used to include or exclude the CLP field - of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored. */ - - unsigned int discardHecErr:1;/**< [23] Discard cells with an invalid HEC. - @li 1 - Discard cells with HEC errors - @li 0 - Cells with HEC errors are passed */ - - unsigned int discardParErr:1;/**< [22] Discard cells containing parity errors. - @li 1 - Discard cells with parity errors - @li 0 - Cells with parity errors are passed */ - - unsigned int discardIdle:1; /**< [21] Discard Idle Cells based on DefineIdle register values - @li 1 - Discard IDLE cells - @li 0 - IDLE cells passed */ - - unsigned int enbHecErrCnt:1;/**< [20] Enable Receive HEC Error Count. - @li 1 - Enable count of received cells containing HEC errors - @li 0 - No count is maintained. */ - - unsigned int enbParErrCnt:1;/**< [19] Enable Parity Error Count - @li 1 - Enable count of received cells containing Parity errors - @li 0 - No count is maintained. */ - - unsigned int enbIdleCellCnt:1;/**< [18] Enable Receive Idle Cell Count. - @li 1 - Enable count of Idle cells received. - @li 0 - No count is maintained.*/ - - unsigned int enbSizeErrCnt:1;/**< [17] Enable Receive Size Error Count. - @li 1 - Enable count of received cells of incorrect size - @li 0 - No count is maintained. */ - - unsigned int enbRxCellCnt:1;/**< [16] Enable Receive Valid Cell Count of non-idle/non-error cells. - @li 1 - Enable count of valid cells received - non-idle/non-error - @li 0 - No count is maintained. */ - - unsigned int reserved_1:3; /**< [15:13] These bits are always 0 */ - - unsigned int rxCellOvrInt:1; /**< [12] Enable CBI Utopia Receive Status Condition if the RxCellCount - register overflows. - @li 1 - CBI Receive Status asserted. - @li 0 - No CBI Receive Status asserted.*/ - - unsigned int invalidHecOvrInt:1; /**< [11] Enable CBI Receive Status Condition if the InvalidHecCount - register overflows. - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int invalidParOvrInt:1; /**< [10] Enable CBI Receive Status Condition if the InvalidParCount - register overflows - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int invalidSizeOvrInt:1; /**< [9] Enable CBI Receive Status Condition if the InvalidSizeCount - register overflows. - @li 1 - CBI Receive Status Condition asserted. - @li 0 - No CBI Receive Status asserted */ - - unsigned int rxIdleOvrInt:1; /**< [8] Enable CBI Receive Status Condition if the RxIdleCount overflows. - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int reserved_2:3; /**< [7:5] These bits are always 0 */ - - unsigned int rxAddrMask:5; /**< [4:0] This register is used as a mask to allow the user to increase - the PHY receive address range. The register should be programmed with - the address-range limit, i.e. if set to 0x3 the address range increases - to a maximum of 4 addresses. */ - } utRxEnableFields; /**< Rx enable Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable0_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable0_ - { - - unsigned int phy0:5; /**< [31-27] Rx Mapping value of logical phy 0 */ - - unsigned int phy1:5; /**< [26-22] Rx Mapping value of logical phy 1 */ - - unsigned int phy2:5; /**< [21-17] Rx Mapping value of logical phy 2 */ - - unsigned int reserved_1:1; /**< [16] These bits are always 0 */ - - unsigned int phy3:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy4:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy5:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } - - utRxTransTable0; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable1_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable1_ - { - - unsigned int phy6:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy7:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy8:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy9:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy10:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy11:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } - - utRxTransTable1; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable2_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable2_ - { - - unsigned int phy12:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy13:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy14:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy15:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy16:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy17:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable2; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable3_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable3_ - { - - unsigned int phy18:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy19:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy20:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy21:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy22:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy23:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable3; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable4_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable4_ - { - - unsigned int phy24:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy25:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy26:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy27:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy28:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy29:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable4; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable5_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable5_ - { - - unsigned int phy30:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */ - - } utRxTransTable5; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtSysConfig_ - * @brief NPE setup Register - */ - struct UtSysConfig_ - { - - unsigned int reserved_1:2; /**< [31-30] These bits are always 0 */ - unsigned int txEnbFSM:1; /**< [29] Enables the operation ofthe Utopia Transmit FSM - * @li 1 - FSM enabled - * @li 0 - FSM inactive - */ - unsigned int rxEnbFSM:1; /**< [28] Enables the operation ofthe Utopia Revieve FSM - * @li 1 - FSM enabled - * @li 0 - FSM inactive - */ - unsigned int disablePins:1; /**< [27] Disable Utopia interface I/O pins forcing the signals to an - * inactive state. Note that this bit is set on reset and must be - * de-asserted - * @li 0 - Normal data transfer - * @li 1 - Utopia interface pins are forced inactive - */ - unsigned int tstLoop:1; /**< [26] Test Loop Back Enable. - * @li Note: For loop back to function RxMode and Tx Mode must both be set - * to single PHY mode. - * @li 0 - Loop back - * @li 1 - Normal operating mode - */ - - unsigned int txReset:1; /**< [25] Resets the Utopia Coprocessor transmit module to a known state. - * @li Note: All transmit configuration and status registers will be reset - * to their reset values. - * @li 0 - Normal operating mode - * @li 1 - Reset transmit modules - */ - - unsigned int rxReset:1; /**< [24] Resets the Utopia Coprocessor receive module to a known state. - * @li Note: All receive configuration and status registers will be reset - * to their reset values. - * @li 0 - Normal operating mode - * @li 1 - Reset receive modules - */ - - unsigned int reserved_2:24; /**< [23-0] These bits are always 0 */ - } utSysConfig; /**< NPE debug config */ - -} -IxAtmdAccUtopiaConfig; - -/** -* -* @brief Utopia status -* -* This structure is used to set/get the Utopia status parameters -* @li contains debug cell counters, to be accessed during a read operation -* -* @note - the exact description of all parameters is done in the Utopia reference -* documents. -* -*/ -typedef struct -{ - - unsigned int utTxCellCount; /**< count of cells transmitted */ - - unsigned int utTxIdleCellCount; /**< count of idle cells transmitted */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxCellConditionStatus_ - * @brief Utopia Tx Status Register - */ - struct UtTxCellConditionStatus_ - { - - unsigned int reserved_1:2; /**< [31:30] These bits are always 0 */ - unsigned int txFIFO2Underflow:1; /**< [29] This bit is set if 64-byte - * Transmit FIFO2 indicates a FIFO underflow - * error condition. - */ - unsigned int txFIFO1Underflow:1; /**< [28] This bit is set if - * 64-byte Transmit FIFO1 indicates a FIFO - * underflow error condition. - */ - unsigned int txFIFO2Overflow:1; /**< [27] This bit is set if 64-byte - * Transmit FIFO2 indicates a FIFO overflow - * error condition. - */ - unsigned int txFIFO1Overflow:1; /**< [26] This bit is set if 64-byte - * Transmit FIFO1 indicates a FIFO overflow - * error condition. - */ - unsigned int txIdleCellCountOvr:1; /**< [25] This bit is set if the - * TxIdleCellCount register overflows. - */ - unsigned int txCellCountOvr:1; /**< [24] This bit is set if the - * TxCellCount register overflows - */ - unsigned int reserved_2:24; /**< [23:0] These bits are always 0 */ - } utTxCellConditionStatus; /**< Tx cells condition status */ - - unsigned int utRxCellCount; /**< count of cell received */ - unsigned int utRxIdleCellCount; /**< count of idle cell received */ - unsigned int utRxInvalidHECount; /**< count of invalid cell - * received because of HEC errors - */ - unsigned int utRxInvalidParCount; /**< count of invalid cell received - * because of parity errors - */ - unsigned int utRxInvalidSizeCount; /**< count of invalid cell - * received because of cell - * size errors - */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxCellConditionStatus_ - * @brief Utopia Rx Status Register - */ - struct UtRxCellConditionStatus_ - { - - unsigned int reserved_1:3; /**< [31:29] These bits are always 0.*/ - unsigned int rxCellCountOvr:1; /**< [28] This bit is set if the RxCellCount register overflows. */ - unsigned int invalidHecCountOvr:1; /**< [27] This bit is set if the InvalidHecCount register overflows.*/ - unsigned int invalidParCountOvr:1; /**< [26] This bit is set if the InvalidParCount register overflows.*/ - unsigned int invalidSizeCountOvr:1; /**< [25] This bit is set if the InvalidSizeCount register overflows.*/ - unsigned int rxIdleCountOvr:1; /**< [24] This bit is set if the RxIdleCount register overflows.*/ - unsigned int reserved_2:4; /**< [23:20] These bits are always 0 */ - unsigned int rxFIFO2Underflow:1; /**< [19] This bit is set if 64-byte Receive FIFO2 - * indicates a FIFO underflow error condition. - */ - unsigned int rxFIFO1Underflow:1; /**< [18] This bit is set if 64-byte Receive - * FIFO1 indicates a FIFO underflow error condition - . */ - unsigned int rxFIFO2Overflow:1; /**< [17] This bit is set if 64-byte Receive FIFO2 - * indicates a FIFO overflow error condition. - */ - unsigned int rxFIFO1Overflow:1; /**< [16] This bit is set if 64-byte Receive FIFO1 - * indicates a FIFO overflow error condition. - */ - unsigned int reserved_3:16; /**< [15:0] These bits are always 0. */ - } utRxCellConditionStatus; /**< Rx cells condition status */ - -} IxAtmdAccUtopiaStatus; - -/** - * @} defgroup IxAtmdAccUtopiaCtrlAPI - */ - - /** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig * - ixAtmdAccUtopiaConfigPtr) - * - * @brief Send the configuration structure to the Utopia interface - * - * This function downloads the @a IxAtmdAccUtopiaConfig structure to - * the Utopia and has the following effects - * @li setup the Utopia interface - * @li initialise the NPE - * @li reset the Utopia cell counters and status registers to known values - * - * This action has to be done once at initialisation. A lock is preventing - * the concurrent use of @a ixAtmdAccUtopiaStatusGet() and - * @A ixAtmdAccUtopiaConfigSet() - * - * @param *ixAtmdAccNPEConfigPtr @ref IxAtmdAccUtopiaConfig [in] - pointer to a structure to download to - * Utopia. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful download - * @return @li IX_FAIL error in the parameters, or configuration is not - * complete or failed - * - * @sa ixAtmdAccUtopiaStatusGet - * - */ -PUBLIC IX_STATUS ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig * - ixAtmdAccUtopiaConfigPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus * - ixAtmdAccUtopiaStatus) - * - * @brief Get the Utopia interface configuration. - * - * This function reads the Utopia registers and the Cell counts - * and fills the @a IxAtmdAccUtopiaStatus structure - * - * A lock is preventing the concurrent - * use of @a ixAtmdAccUtopiaStatusGet() and @A ixAtmdAccUtopiaConfigSet() - * - * @param ixAtmdAccUtopiaStatus @ref IxAtmdAccUtopiaStatus [out] - pointer to structure to be updated from internal - * hardware counters. This parameter cannot be a NULL pointer. - * - * @return @li IX_SUCCESS successful read - * @return @li IX_FAIL error in the parameters null pointer, or - * configuration read is not complete or failed - * - * @sa ixAtmdAccUtopiaConfigSet - * - */ -PUBLIC IX_STATUS ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus * - ixAtmdAccUtopiaStatus); - -/** - * - * @ingroup IxAtmdAcc - * - * @fn ixAtmdAccPortEnable (IxAtmLogicalPort port) - * - * @brief enable a PHY logical port - * - * This function enables the transmission over one port. It should be - * called before accessing any resource from this port and before the - * establishment of a VC. - * - * When a port is enabled, the cell transmission to the Utopia interface - * is started. If there is no traffic already running, idle cells are - * sent over the interface. - * - * This function can be called multiple times. - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * - * @return @li IX_SUCCESS enable is complete - * @return @li IX_ATMDACC_WARNING port already enabled - * @return @li IX_FAIL enable failed, wrong parameter, or cannot - * initialise this port (the port is maybe already in use, - * or there is a hardware issue) - * - * @note - This function needs internal locks and should not be - * called from an interrupt context - * - * @sa ixAtmdAccPortDisable - * - */ -PUBLIC IX_STATUS ixAtmdAccPortEnable (IxAtmLogicalPort port); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortDisable (IxAtmLogicalPort port) - * - * @brief disable a PHY logical port - * - * This function disable the transmission over one port. - * - * When a port is disabled, the cell transmission to the Utopia interface - * is stopped. - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * - * @return @li IX_SUCCESS disable is complete - * @return @li IX_ATMDACC_WARNING port already disabled - * @return @li IX_FAIL disable failed, wrong parameter . - * - * @note - This function needs internal locks and should not be called - * from an interrupt context - * - * @note - The response from hardware is done through the txDone mechanism - * to ensure the synchrnisation with tx resources. Therefore, the - * txDone mechanism needs to be serviced to make a PortDisable complete. - * - * @sa ixAtmdAccPortEnable - * @sa ixAtmdAccPortDisableComplete - * @sa ixAtmdAccTxDoneDispatch - * - */ -PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @fn ixAtmdAccPortDisableComplete (IxAtmLogicalPort port) -* -* @brief disable a PHY logical port -* -* This function indicates if the port disable for a port has completed. This -* function will return true if the port has never been enabled. -* -* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] -* -* @return @li true disable is complete -* @return @li false disable failed, wrong parameter . -* -* @note - This function needs internal locks and should not be called -* from an interrupt context -* -* @sa ixAtmdAccPortEnable -* @sa ixAtmdAccPortDisable -* -*/ -PUBLIC BOOL ixAtmdAccPortDisableComplete (IxAtmLogicalPort port); - -#endif /* IXATMDACCCTRL_H */ - -/** - * @} defgroup IxAtmdAccCtrlAPI - */ - - diff --git a/drivers/net/npe/include/IxAtmm.h b/drivers/net/npe/include/IxAtmm.h deleted file mode 100644 index fcf523fca4..0000000000 --- a/drivers/net/npe/include/IxAtmm.h +++ /dev/null @@ -1,795 +0,0 @@ -/** - * @file IxAtmm.h - * - * @date 3-DEC-2001 - * - * @brief Header file for the IXP400 ATM Manager component (IxAtmm) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - - -/** - * @defgroup IxAtmm IXP400 ATM Manager (IxAtmm) API - * - * @brief IXP400 ATM Manager component Public API - * - * @{ - */ - -#ifndef IXATMM_H -#define IXATMM_H - -/* - * Put the user defined include files required - */ -#include "IxAtmSch.h" -#include "IxOsalTypes.h" - -/* - * #defines and macros used in this file. - */ - -/** - * @def IX_ATMM_RET_ALREADY_INITIALIZED - * - * @brief Component has already been initialized - */ -#define IX_ATMM_RET_ALREADY_INITIALIZED 2 - -/** - * @def IX_ATMM_RET_INVALID_PORT - * - * @brief Specified port does not exist or is out of range */ -#define IX_ATMM_RET_INVALID_PORT 3 - -/** - * @def IX_ATMM_RET_INVALID_VC_DESCRIPTOR - * - * @brief The VC description does not adhere to ATM standards */ -#define IX_ATMM_RET_INVALID_VC_DESCRIPTOR 4 - -/** - * @def IX_ATMM_RET_VC_CONFLICT - * - * @brief The VPI/VCI values supplied are either reserved, or they - * conflict with a previously registered VC on this port */ -#define IX_ATMM_RET_VC_CONFLICT 5 - -/** - * @def IX_ATMM_RET_PORT_CAPACITY_IS_FULL - * - * @brief The virtual connection cannot be established on the port - * because the remaining port capacity is not sufficient to - * support it */ -#define IX_ATMM_RET_PORT_CAPACITY_IS_FULL 6 - -/** - * @def IX_ATMM_RET_NO_SUCH_VC - * - * @brief No registered VC, as described by the supplied VCI/VPI or - * VC identifier values, exists on this port */ -#define IX_ATMM_RET_NO_SUCH_VC 7 - -/** - * @def IX_ATMM_RET_INVALID_VC_ID - * - * @brief The specified VC identifier is out of range. */ -#define IX_ATMM_RET_INVALID_VC_ID 8 - -/** - * @def IX_ATMM_RET_INVALID_PARAM_PTR - * - * @brief A pointer parameter was NULL. */ -#define IX_ATMM_RET_INVALID_PARAM_PTR 9 - -/** - * @def IX_ATMM_UTOPIA_SPHY_ADDR - * - * @brief The phy address when in SPHY mode */ -#define IX_ATMM_UTOPIA_SPHY_ADDR 31 - -/** - * @def IX_ATMM_THREAD_PRI_HIGH - * - * @brief The value of high priority thread */ -#define IX_ATMM_THREAD_PRI_HIGH 90 - -/* - * Typedefs whose scope is limited to this file. - */ - -/** @brief Definition for use in the @ref IxAtmmVc structure. - * Indicates the direction of a VC */ -typedef enum -{ - IX_ATMM_VC_DIRECTION_TX=0, /**< Atmm Vc direction transmit*/ - IX_ATMM_VC_DIRECTION_RX, /**< Atmm Vc direction receive*/ - IX_ATMM_VC_DIRECTION_INVALID /**< Atmm Vc direction invalid*/ -} IxAtmmVcDirection; - -/** @brief Definition for use with @ref IxAtmmVcChangeCallback - * callback. Indicates that the event type represented by the - * callback for this VC. */ -typedef enum -{ - IX_ATMM_VC_CHANGE_EVENT_REGISTER=0, /**< Atmm Vc event register*/ - IX_ATMM_VC_CHANGE_EVENT_DEREGISTER, /**< Atmm Vc event de-register*/ - IX_ATMM_VC_CHANGE_EVENT_INVALID /**< Atmm Vc event invalid*/ -} IxAtmmVcChangeEvent; - -/** @brief Definitions for use with @ref ixAtmmUTOPIAInit interface to - * indicate that UTOPIA loopback should be enabled or disabled - * on initialisation. */ -typedef enum -{ - IX_ATMM_UTOPIA_LOOPBACK_DISABLED=0, /**< Atmm Utopia loopback mode disabled*/ - IX_ATMM_UTOPIA_LOOPBACK_ENABLED, /**< Atmm Utopia loopback mode enabled*/ - IX_ATMM_UTOPIA_LOOPBACK_INVALID /**< Atmm Utopia loopback mode invalid*/ -} IxAtmmUtopiaLoopbackMode; - -/** @brief This structure describes the required attributes of a - * virtual connection. -*/ -typedef struct { - unsigned vpi; /**< VPI value of this virtual connection */ - unsigned vci; /**< VCI value of this virtual connection. */ - IxAtmmVcDirection direction; /**< VC direction */ - - /** Traffic descriptor of this virtual connection. This structure - * is defined by the @ref IxAtmSch component. */ - IxAtmTrafficDescriptor trafficDesc; -} IxAtmmVc; - - -/** @brief Definitions for use with @ref ixAtmmUtopiaInit interface to - * indicate that UTOPIA multi-phy/single-phy mode is used. - */ -typedef enum -{ - IX_ATMM_MPHY_MODE = 0, /**< Atmm phy mode mphy*/ - IX_ATMM_SPHY_MODE, /**< Atmm phy mode sphy*/ - IX_ATMM_PHY_MODE_INVALID /**< Atmm phy mode invalid*/ -} IxAtmmPhyMode; - - -/** @brief Structure contains port-specific information required to - * initialize IxAtmm, and specifically, the IXP400 UTOPIA - * Level-2 device. */ -typedef struct { - unsigned reserved_1:11; /**< [31:21] Should be zero */ - unsigned UtopiaTxPhyAddr:5; /**< [20:16] Address of the - * transmit (Tx) PHY for this - * port on the 5-bit UTOPIA - * Level-2 address bus */ - unsigned reserved_2:11; /**< [15:5] Should be zero */ - unsigned UtopiaRxPhyAddr:5; /**< [4:0] Address of the receive - * (Rx) PHY for this port on the - * 5-bit UTOPIA Level-2 - * address bus */ -} IxAtmmPortCfg; - -/** @brief Callback type used with @ref ixAtmmVcChangeCallbackRegister interface - * Defines a callback type which will be used to notify registered - * users of registration/deregistration events on a particular port - * - * @param eventType @ref IxAtmmVcChangeEvent [in] - Event indicating - * whether the VC supplied has been added or - * removed - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the port on which the event has - * occurred - * - * @param vcChanged @ref IxAtmmVc* [in] - Pointer to a structure which gives - * details of the VC which has been added - * or removed on the port - */ -typedef void (*IxAtmmVcChangeCallback) (IxAtmmVcChangeEvent eventType, - IxAtmLogicalPort port, - const IxAtmmVc* vcChanged); - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * Extern function prototypes - */ - -/* - * Function declarations - */ - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmInit (void) - * - * @brief Interface to initialize the IxAtmm software component. Can - * be called once only. - * - * Must be called before any other IxAtmm API is called. - * - * @param "none" - * - * @return @li IX_SUCCESS : IxAtmm has been successfully initialized. - * Calls to other IxAtmm interfaces may now be performed. - * @return @li IX_FAIL : IxAtmm has already been initialized. - */ -PUBLIC IX_STATUS -ixAtmmInit (void); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaInit (unsigned numPorts, - IxAtmmPhyMode phyMode, - IxAtmmPortCfg portCfgs[], - IxAtmmUtopiaLoopbackMode loopbackMode) - * - * @brief Interface to initialize the UTOPIA Level-2 ATM coprocessor - * for the specified number of physical ports. The function - * must be called before the ixAtmmPortInitialize interface - * can operate successfully. - * - * @param numPorts unsigned [in] - Indicates the total number of logical - * ports that are active on the device. Up to 12 ports are - * supported. - * - * @param phyMode @ref IxAtmmPhyMode [in] - Put the Utopia coprocessor in SPHY - * or MPHY mode. - * - * @param portCfgs[] @ref IxAtmmPortCfg [in] - Pointer to an array of elements - * detailing the UTOPIA specific port characteristics. The - * length of the array must be equal to the number of ports - * activated. ATM ports are referred to by the relevant - * offset in this array in all subsequent IxAtmm interface - * calls. - * - * @param loopbackMode @ref IxAtmmUtopiaLoopbackMode [in] - Value must be one of - * @ref IX_ATMM_UTOPIA_LOOPBACK_ENABLED or @ref - * IX_ATMM_UTOPIA_LOOPBACK_DISABLED indicating whether - * loopback should be enabled on the device. Loopback can - * only be supported on a single PHY, therefore the numPorts - * parameter must be 1 if loopback is enabled. - * - * @return @li IX_SUCCESS : Indicates that the UTOPIA device has been - * successfully initialized for the supplied ports. - * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : The UTOPIA device has - * already been initialized. - * @return @li IX_FAIL : The supplied parameters are invalid or have been - * rejected by the UTOPIA-NPE device. - * - * @warning - * This interface may only be called once. - * Port identifiers are assumed to range from 0 to (numPorts - 1) in all - * instances. - * In all subsequent calls to interfaces supplied by IxAtmm, the specified - * port value is expected to represent the offset in the portCfgs array - * specified in this interface. i.e. The first port in this array will - * subsequently be represented as port 0, the second port as port 1, - * and so on.*/ -PUBLIC IX_STATUS -ixAtmmUtopiaInit (unsigned numPorts, - IxAtmmPhyMode phyMode, - IxAtmmPortCfg portCfgs[], - IxAtmmUtopiaLoopbackMode loopbackMode); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortInitialize (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate) - * - * @brief The interface is called following @ref ixAtmmUtopiaInit () - * and before calls to any other IxAtmm interface. It serves - * to activate the registered ATM port with IxAtmm. - * - * The transmit and receive port rates are specified in bits per - * second. This translates to ATM cells per second according to the - * following formula: CellsPerSecond = portRate / (53*8) The - * IXP400 device supports only 53 byte cells. The client shall make - * sure that the off-chip physical layer device has already been - * initialized. - * - * IxAtmm will configure IxAtmdAcc and IxAtmSch to enable scheduling - * on the port. - * - * This interface must be called once for each active port in the - * system. The first time the interface is invoked, it will configure - * the mechanism by which the handling of transmit, transmit-done and - * receive are driven with the IxAtmdAcc component. - * - * This function is reentrant. - * - * @note The minimum tx rate that will be accepted is 424 bit/s which equates - * to 1 cell (53 bytes) per second. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be - * initialized. - * - * @param txPortRate unsigned [in] - Value specifies the - * transmit port rate for this port in - * bits/second. This value is used by the ATM Scheduler - * component is evaluating VC access requests for the port. - * - * @param rxPortRate unsigned [in] - Value specifies the - * receive port rate for this port in bits/second. - * - * @return @li IX_SUCCESS : The specificed ATM port has been successfully - * initialized. IxAtmm is ready to accept VC registrations on - * this port. - * - * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : ixAtmmPortInitialize has - * already been called successfully on this port. The current - * call is rejected. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_FAIL : IxAtmm could not initialize the port because the - * inputs are not understood. - * - * @sa ixAtmmPortEnable, ixAtmmPortDisable - * - */ -PUBLIC IX_STATUS -ixAtmmPortInitialize (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortModify (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate) - * - * @brief A client may call this interface to change the existing - * port rate (expressed in bits/second) on an established ATM - * port. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be - * initialized. - * - * @param txPortRate unsigned [in] - Value specifies the`` - * transmit port rate for this port in - * bits/second. This value is used by the ATM Scheduler - * component is evaluating VC access requests for the port. - * - * @param rxPortRate unsigned [in] - Value specifies the - * receive port rate for this port in - * bits/second. - * - * @return @li IX_SUCCESS : The indicated ATM port rates have been - * successfully modified. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_FAIL : IxAtmm could not update the port because the - * inputs are not understood, or the interface was called before - * the port was initialized. */ -PUBLIC IX_STATUS -ixAtmmPortModify (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortQuery (IxAtmLogicalPort port, - unsigned *txPortRate, - unsigned *rxPortRate); - - * - * @brief The client may call this interface to request details on - * currently registered transmit and receive rates for an ATM - * port. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port from which the - * rate details are requested. - * - * @param *txPortRate unsigned [out] - Pointer to a value - * which will be filled with the value of the transmit port - * rate specified in bits/second. - * - * @param *rxPortRate unsigned [out] - Pointer to a value - * which will be filled with the value of the receive port - * rate specified in bits/second. - * - * @return @li IX_SUCCESS : The information requested on the specified - * port has been successfully supplied in the output. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - * @return @li IX_FAIL : IxAtmm could not update the port because the - * inputs are not understood, or the interface was called before - * the port was initialized. */ -PUBLIC IX_STATUS -ixAtmmPortQuery (IxAtmLogicalPort port, - unsigned *txPortRate, - unsigned *rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortEnable(IxAtmLogicalPort port) - * - * @brief The client call this interface to enable transmit for an ATM - * port. At initialisation, all the ports are disabled. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port - * - * @return @li IX_SUCCESS : Transmission over this port is started. - * - * @return @li IX_FAIL : The port parameter is not valid, or the - * port is already enabled - * - * @note - When a port is disabled, Rx and Tx VC Connect requests will fail - * - * @note - This function uses system resources and should not be used - * inside an interrupt context. - * - * @sa ixAtmmPortDisable */ -PUBLIC IX_STATUS -ixAtmmPortEnable(IxAtmLogicalPort port); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortDisable(IxAtmLogicalPort port) - * - * @brief The client call this interface to disable transmit for an ATM - * port. At initialisation, all the ports are disabled. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port - * - * @return @li IX_SUCCESS : Transmission over this port is stopped. - * - * @return @li IX_FAIL : The port parameter is not valid, or the - * port is already disabled - * - * @note - When a port is disabled, Rx and Tx VC Connect requests will fail - * - * @note - This function call does not stop RX traffic. It is supposed - * that this function is invoked when a serious problem - * is detected (e.g. physical layer broken). Then, the RX traffic - * is not passing. - * - * @note - This function is blocking until the hw acknowledge that the - * transmission is stopped. - * - * @note - This function uses system resources and should not be used - * inside an interrupt context. - * - * @sa ixAtmmPortEnable */ -PUBLIC IX_STATUS -ixAtmmPortDisable(IxAtmLogicalPort port); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcRegister (IxAtmLogicalPort port, - IxAtmmVc *vcToAdd, - IxAtmSchedulerVcId *vcId) - * - * @brief This interface is used to register an ATM Virtual - * Connection on the specified ATM port. - * - * Each call to this interface registers a unidirectional virtual - * connection with the parameters specified. If a bi-directional VC - * is needed, the function should be called twice (once for each - * direction, Tx & Rx) where the VPI and VCI and port parameters in - * each call are identical. - * - * With the addition of each new VC to a port, a series of - * callback functions are invoked by the IxAtmm component to notify - * possible external components of the change. The callback functions - * are registered using the @ref ixAtmmVcChangeCallbackRegister interface. - * - * The IxAtmSch component is notified of the registration of transmit - * VCs. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the specified VC is - * to be registered. - * - * @param *vcToAdd @ref IxAtmmVc [in] - Pointer to an @ref IxAtmmVc structure - * containing a description of the VC to be registered. The - * client shall fill the vpi, vci and direction and relevant - * trafficDesc members of this structure before calling this - * function. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which is filled - * with the per-port unique identifier value for this VC. - * This identifier will be required when a request is - * made to deregister or change this VC. VC identifiers - * for transmit VCs will have a value between 0-43, - * i.e. 32 data Tx VCs + 12 OAM Tx Port VCs. - * Receive VCs will have a value between 44-66, - * i.e. 32 data Rx VCs + 1 OAM Rx VC. - * - * @return @li IX_SUCCESS : The VC has been successfully registered on - * this port. The VC is ready for a client to configure IxAtmdAcc - * for receive and transmit operations on the VC. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_INVALID_VC_DESCRIPTOR : The descriptor - * pointed to by vcToAdd is invalid. The registration request - * is rejected. - * @return @li IX_ATMM_RET_VC_CONFLICT : The VC requested conflicts with - * reserved VPI and/or VCI values or with another VC already activated - * on this port. - * @return @li IX_ATMM_RET_PORT_CAPACITY_IS_FULL : The VC cannot be - * registered in the port becuase the port capacity is - * insufficient to support the requested ATM traffic contract. - * The registration request is rejected. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - * @warning IxAtmm has no capability of signaling or negotiating a virtual - * connection. Negotiation of the admission of the VC to the network - * is beyond the scope of this function. This is assumed to be - * performed by the calling client, if appropriate, - * before or after this function is called. - */ -PUBLIC IX_STATUS -ixAtmmVcRegister (IxAtmLogicalPort port, - IxAtmmVc *vcToAdd, - IxAtmSchedulerVcId *vcId); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId) - * - * @brief Function called by a client to deregister a VC from the - * system. - * - * With the removal of each new VC from a port, a series of - * registered callback functions are invoked by the IxAtmm component - * to notify possible external components of the change. The callback - * functions are registered using the @ref ixAtmmVcChangeCallbackRegister. - * - * The IxAtmSch component is notified of the removal of transmit VCs. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * removed is currently registered. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - VC identifier value of the VC to - * be deregistered. This value was supplied to the client when - the VC was originally registered. This value can also be - queried from the IxAtmm component through the @ref ixAtmmVcQuery - * interface. - * - * @return @li IX_SUCCESS : The specified VC has been successfully - * removed from this port. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_FAIL : There is no registered VC associated with the - * supplied identifier registered on this port. */ -PUBLIC IX_STATUS -ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcQuery (IxAtmLogicalPort port, - unsigned vpi, - unsigned vci, - IxAtmmVcDirection direction, - IxAtmSchedulerVcId *vcId, - IxAtmmVc *vcDesc) - * - * @brief This interface supplies information about an active VC on a - * particular port when supplied with the VPI, VCI and - * direction of that VC. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * queried is currently registered. - * - * @param vpi unsigned [in] - ATM VPI value of the requested VC. - * - * @param vci unsigned [in] - ATM VCI value of the requested VC. - * - * @param direction @ref IxAtmmVcDirection [in] - One of @ref - * IX_ATMM_VC_DIRECTION_TX or @ref IX_ATMM_VC_DIRECTION_RX - * indicating the direction (Tx or Rx) of the requested VC. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which will be - * filled with the VC identifier value for the requested - * VC (as returned by @ref ixAtmmVcRegister), if it - * exists on this port. - * - * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure - * which will be filled with the specific details of the - * requested VC, if it exists on this port. - * - * @return @li IX_SUCCESS : The specified VC has been found on this port - * and the requested details have been returned. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified - * port which matches the search criteria (VPI, VCI, direction) - * given. No data is returned. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - */ -PUBLIC IX_STATUS -ixAtmmVcQuery (IxAtmLogicalPort port, - unsigned vpi, - unsigned vci, - IxAtmmVcDirection direction, - IxAtmSchedulerVcId *vcId, - IxAtmmVc *vcDesc); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc) - * - * @brief This interface supplies information about an active VC on a - * particular port when supplied with a vcId for that VC. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * queried is currently registered. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Value returned by @ref ixAtmmVcRegister which - * uniquely identifies the requested VC on this port. - * - * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure - * which will be filled with the specific details of the - * requested VC, if it exists on this port. - * - * @return @li IX_SUCCESS : The specified VC has been found on this port - * and the requested details have been returned. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified - * port which matches the supplied identifier. No data is - * returned. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - */ -PUBLIC IX_STATUS -ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback) - * - * @brief This interface is invoked to supply a function to IxAtmm - * which will be called to notify the client if a new VC is - * registered with IxAtmm or an existing VC is removed. - * - * The callback, when invoked, will run within the context of the call - * to @ref ixAtmmVcRegister or @ref ixAtmmVcDeregister which caused - * the change of state. - * - * A maximum of 32 calbacks may be registered in with IxAtmm. - * - * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies - * with the @ref IxAtmmVcChangeCallback definition. This - * function will be invoked by IxAtmm with the appropiate - * parameters for the relevant VC when any VC has been - * registered or deregistered with IxAtmm. - * - * @return @li IX_SUCCESS : The specified callback has been registered - * successfully with IxAtmm and will be invoked when appropriate. - * @return @li IX_FAIL : Either the supplied callback is invalid, or - * IxAtmm has already registered 32 and connot accommodate - * any further registrations of this type. The request is - * rejected. - * - * @warning The client must not call either the @ref - * ixAtmmVcRegister or @ref ixAtmmVcDeregister interfaces - * from within the supplied callback function. */ -PUBLIC IX_STATUS ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback) - * - * @brief This interface is invoked to deregister a previously supplied - * callback function. - * - * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies - * with the @ref IxAtmmVcChangeCallback definition. This - * function will removed from the table of callbacks. - * - * @return @li IX_SUCCESS : The specified callback has been deregistered - * successfully from IxAtmm. - * @return @li IX_FAIL : Either the supplied callback is invalid, or - * is not currently registered with IxAtmm. - */ -PUBLIC IX_STATUS -ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaStatusShow (void) - * - * @brief Display utopia status counters - * - * @param "none" - * - * @return @li IX_SUCCESS : Show function was successful - * @return @li IX_FAIL : Internal failure - */ -PUBLIC IX_STATUS -ixAtmmUtopiaStatusShow (void); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaCfgShow (void) - * - * @brief Display utopia information(config registers and status registers) - * - * @param "none" - * - * @return @li IX_SUCCESS : Show function was successful - * @return @li IX_FAIL : Internal failure - */ -PUBLIC IX_STATUS -ixAtmmUtopiaCfgShow (void); - -#endif -/* IXATMM_H */ - -/** @} */ diff --git a/drivers/net/npe/include/IxDmaAcc.h b/drivers/net/npe/include/IxDmaAcc.h deleted file mode 100644 index 45c7527de9..0000000000 --- a/drivers/net/npe/include/IxDmaAcc.h +++ /dev/null @@ -1,260 +0,0 @@ -/** - * @file IxDmaAcc.h - * - * @date 15 October 2002 - * - * @brief API of the IXP400 DMA Access Driver Component (IxDma) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/*--------------------------------------------------------------------- - Doxygen group definitions - ---------------------------------------------------------------------*/ - -#ifndef IXDMAACC_H -#define IXDMAACC_H - -#include "IxOsal.h" -#include "IxNpeDl.h" -/** - * @defgroup IxDmaTypes IXP400 DMA Types (IxDmaTypes) - * @brief The common set of types used in the DMA component - * @{ - */ - -/** - * @ingroup IxDmaTypes - * @enum IxDmaReturnStatus - * @brief Dma return status definitions - */ -typedef enum -{ - IX_DMA_SUCCESS = IX_SUCCESS, /**< DMA Transfer Success */ - IX_DMA_FAIL = IX_FAIL, /**< DMA Transfer Fail */ - IX_DMA_INVALID_TRANSFER_WIDTH, /**< Invalid transfer width */ - IX_DMA_INVALID_TRANSFER_LENGTH, /**< Invalid transfer length */ - IX_DMA_INVALID_TRANSFER_MODE, /**< Invalid transfer mode */ - IX_DMA_INVALID_ADDRESS_MODE, /**< Invalid address mode */ - IX_DMA_REQUEST_FIFO_FULL /**< DMA request queue is full */ -} IxDmaReturnStatus; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaTransferMode - * @brief Dma transfer mode definitions - * @note Copy and byte swap, and copy and reverse modes only support multiples of word data length. - */ -typedef enum -{ - IX_DMA_COPY_CLEAR = 0, /**< copy and clear source*/ - IX_DMA_COPY, /**< copy */ - IX_DMA_COPY_BYTE_SWAP, /**< copy and byte swap (endian) */ - IX_DMA_COPY_REVERSE, /**< copy and reverse */ - IX_DMA_TRANSFER_MODE_INVALID /**< Invalid transfer mode */ -} IxDmaTransferMode; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaAddressingMode - * @brief Dma addressing mode definitions - * @note Fixed source address to fixed destination address addressing mode is not supported. - */ -typedef enum -{ - IX_DMA_INC_SRC_INC_DST = 0, /**< Incremental source address to incremental destination address */ - IX_DMA_INC_SRC_FIX_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_FIX_SRC_INC_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_FIX_SRC_FIX_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_ADDRESSING_MODE_INVALID /**< Invalid Addressing Mode */ -} IxDmaAddressingMode; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaTransferWidth - * @brief Dma transfer width definitions - * @Note Fixed addresses (either source or destination) do not support burst transfer width. - */ -typedef enum -{ - IX_DMA_32_SRC_32_DST = 0, /**< 32-bit src to 32-bit dst */ - IX_DMA_32_SRC_16_DST, /**< 32-bit src to 16-bit dst */ - IX_DMA_32_SRC_8_DST, /**< 32-bit src to 8-bit dst */ - IX_DMA_16_SRC_32_DST, /**< 16-bit src to 32-bit dst */ - IX_DMA_16_SRC_16_DST, /**< 16-bit src to 16-bit dst */ - IX_DMA_16_SRC_8_DST, /**< 16-bit src to 8-bit dst */ - IX_DMA_8_SRC_32_DST, /**< 8-bit src to 32-bit dst */ - IX_DMA_8_SRC_16_DST, /**< 8-bit src to 16-bit dst */ - IX_DMA_8_SRC_8_DST, /**< 8-bit src to 8-bit dst */ - IX_DMA_8_SRC_BURST_DST, /**< 8-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_16_SRC_BURST_DST, /**< 16-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_32_SRC_BURST_DST, /**< 32-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_BURST_SRC_8_DST, /**< burst src to 8-bit dst - Not supported for fixed source address */ - IX_DMA_BURST_SRC_16_DST, /**< burst src to 16-bit dst - Not supported for fixed source address */ - IX_DMA_BURST_SRC_32_DST, /**< burst src to 32-bit dst - Not supported for fixed source address*/ - IX_DMA_BURST_SRC_BURST_DST, /**< burst src to burst dst - Not supported for fixed source and destination address -*/ - IX_DMA_TRANSFER_WIDTH_INVALID /**< Invalid transfer width */ -} IxDmaTransferWidth; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaNpeId - * @brief NpeId numbers to identify NPE A, B or C - */ -typedef enum -{ - IX_DMA_NPEID_NPEA = 0, /**< Identifies NPE A */ - IX_DMA_NPEID_NPEB, /**< Identifies NPE B */ - IX_DMA_NPEID_NPEC, /**< Identifies NPE C */ - IX_DMA_NPEID_MAX /**< Total Number of NPEs */ -} IxDmaNpeId; -/* @} */ -/** - * @defgroup IxDmaAcc IXP400 DMA Access Driver (IxDmaAcc) API - * - * @brief The public API for the IXP400 IxDmaAcc component - * - * @{ - */ - -/** - * @ingroup IxDmaAcc - * @brief DMA Request Id type - */ -typedef UINT32 IxDmaAccRequestId; - -/** - * @ingroup IxDmaAcc - * @def IX_DMA_REQUEST_FULL - * @brief DMA request queue is full - * This constant is a return value used to tell the user that the IxDmaAcc - * queue is full. - * - */ -#define IX_DMA_REQUEST_FULL 16 - -/** - * @ingroup IxDmaAcc - * @brief DMA completion notification - * This function is called to notify a client that the DMA has been completed - * @param status @ref IxDmaReturnStatus [out] - reporting to client - * - */ -typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status); - -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccInit(IxNpeDlNpeId npeId) - * - * @brief Initialise the DMA Access component - * This function will initialise the DMA Access component internals - * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer - * @return @li IX_SUCCESS succesfully initialised the component - * @return @li IX_FAIL Initialisation failed for some unspecified - * internal reason. - */ -PUBLIC IX_STATUS -ixDmaAccInit(IxNpeDlNpeId npeId); - -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccDmaTransfer( - IxDmaAccDmaCompleteCallback callback, - UINT32 SourceAddr, - UINT32 DestinationAddr, - UINT16 TransferLength, - IxDmaTransferMode TransferMode, - IxDmaAddressingMode AddressingMode, - IxDmaTransferWidth TransferWidth) - * - * @brief Perform DMA transfer - * This function will perform DMA transfer between devices within the - * IXP400 memory map. - * @note The following are restrictions for IxDmaAccDmaTransfer: - * @li The function is non re-entrant. - * @li The function assumes host devices are operating in big-endian mode. - * @li Fixed address does not suport burst transfer width - * @li Fixed source address to fixed destinatiom address mode is not suported - * @li The incrementing source address for expansion bus will not support a burst transfer width and copy and clear mode - * - * @param callback @ref IxDmaAccDmaCompleteCallback [in] - function pointer to be stored and called when the DMA transfer is completed. This cannot be NULL. - * @param SourceAddr UINT32 [in] - Starting address of DMA source. Must be a valid IXP400 memory map address. - * @param DestinationAddr UINT32 [in] - Starting address of DMA destination. Must be a valid IXP400 memory map address. - * @param TransferLength UINT16 [in] - The size of DMA data transfer. The range must be from 1-64Kbyte - * @param TransferMode @ref IxDmaTransferMode [in] - The DMA transfer mode - * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode - * @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width - * - * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful - * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured - * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid - * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range - * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid - * @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full - */ -PUBLIC IxDmaReturnStatus -ixDmaAccDmaTransfer( - IxDmaAccDmaCompleteCallback callback, - UINT32 SourceAddr, - UINT32 DestinationAddr, - UINT16 TransferLength, - IxDmaTransferMode TransferMode, - IxDmaAddressingMode AddressingMode, - IxDmaTransferWidth TransferWidth); -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccShow(void) - * - * @brief Display some component information for debug purposes - * Show some internal operation information relating to the DMA service. - * At a minimum the following will show. - * - the number of the DMA pend (in queue) - * @param None - * @return @li None - */ -PUBLIC IX_STATUS -ixDmaAccShow(void); - -#endif /* IXDMAACC_H */ - diff --git a/drivers/net/npe/include/IxEthAcc.h b/drivers/net/npe/include/IxEthAcc.h deleted file mode 100644 index ff706c451d..0000000000 --- a/drivers/net/npe/include/IxEthAcc.h +++ /dev/null @@ -1,2512 +0,0 @@ -/** @file IxEthAcc.h - * - * @brief this file contains the public API of @ref IxEthAcc component - * - * Design notes: - * The IX_OSAL_MBUF address is to be specified on bits [31-5] and must - * be cache aligned (bits[4-0] cleared) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * - */ - -#ifndef IxEthAcc_H -#define IxEthAcc_H - -#include -#include - -/** - * @defgroup IxEthAcc IXP400 Ethernet Access (IxEthAcc) API - * - * @brief ethAcc is a library that does provides access to the internal IXP400 10/100Bt Ethernet MACs. - * - *@{ - */ - -/** - * @ingroup IxEthAcc - * @brief Definition of the Ethernet Access status - */ -typedef enum /* IxEthAccStatus */ -{ - IX_ETH_ACC_SUCCESS = IX_SUCCESS, /**< return success*/ - IX_ETH_ACC_FAIL = IX_FAIL, /**< return fail*/ - IX_ETH_ACC_INVALID_PORT, /**< return invalid port*/ - IX_ETH_ACC_PORT_UNINITIALIZED, /**< return uninitialized*/ - IX_ETH_ACC_MAC_UNINITIALIZED, /**< return MAC uninitialized*/ - IX_ETH_ACC_INVALID_ARG, /**< return invalid arg*/ - IX_ETH_TX_Q_FULL, /**< return tx queue is full*/ - IX_ETH_ACC_NO_SUCH_ADDR /**< return no such address*/ -} IxEthAccStatus; - -/** - * @ingroup IxEthAcc - * @enum IxEthAccPortId - * @brief Definition of the IXP400 Mac Ethernet device. - */ -typedef enum -{ - IX_ETH_PORT_1 = 0, /**< Ethernet Port 1 */ - IX_ETH_PORT_2 = 1 /**< Ethernet port 2 */ - ,IX_ETH_PORT_3 = 2 /**< Ethernet port 3 */ -} IxEthAccPortId; - -/** - * @ingroup IxEthAcc - * - * @def IX_ETH_ACC_NUMBER_OF_PORTS - * - * @brief Definition of the number of ports - * - */ -#ifdef __ixp46X -#define IX_ETH_ACC_NUMBER_OF_PORTS (3) -#else -#define IX_ETH_ACC_NUMBER_OF_PORTS (2) -#endif - -/** - * @ingroup IxEthAcc - * - * @def IX_IEEE803_MAC_ADDRESS_SIZE - * - * @brief Definition of the size of the MAC address - * - */ -#define IX_IEEE803_MAC_ADDRESS_SIZE (6) - - -/** - * - * @brief Definition of the IEEE 802.3 Ethernet MAC address structure. - * - * The data should be packed with bytes xx:xx:xx:xx:xx:xx - * @note - * The data must be packed in network byte order. - */ -typedef struct -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< MAC address */ -} IxEthAccMacAddr; - -/** - * @ingroup IxEthAcc - * @def IX_ETH_ACC_NUM_TX_PRIORITIES - * @brief Definition of the number of transmit priorities - * - */ -#define IX_ETH_ACC_NUM_TX_PRIORITIES (8) - -/** - * @ingroup IxEthAcc - * @enum IxEthAccTxPriority - * @brief Definition of the relative priority used to transmit a frame - * - */ -typedef enum -{ - IX_ETH_ACC_TX_PRIORITY_0 = 0, /** STA */ - IX_ETHACC_RX_APTYPE = 0x30 /**< 802.11, AP <=> AP */ -} IxEthAccRxFrameType; - -/** - * @ingroup IxEthAcc - * @enum IxEthAccDuplexMode - * @brief Definition to provision the duplex mode of the MAC. - * - */ -typedef enum -{ - IX_ETH_ACC_FULL_DUPLEX, /**< Full duplex operation of the MAC */ - IX_ETH_ACC_HALF_DUPLEX /**< Half duplex operation of the MAC */ -} IxEthAccDuplexMode; - - -/** - * @ingroup IxEthAcc - * @struct IxEthAccNe - * @brief Definition of service-specific informations. - * - * This structure defines the Ethernet service-specific informations - * and enable QoS and VLAN features. - */ -typedef struct -{ - UINT32 ixReserved_next; /**< reserved for chaining */ - UINT32 ixReserved_lengths; /**< reserved for buffer lengths */ - UINT32 ixReserved_data; /**< reserved for buffer pointer */ - UINT8 ixDestinationPortId; /**< Destination portId for this packet, if known by NPE */ - UINT8 ixSourcePortId; /**< Source portId for this packet */ - UINT16 ixFlags; /**< BitField of option for this frame */ - UINT8 ixQoS; /**< QoS class of the frame */ - UINT8 ixReserved; /**< reserved */ - UINT16 ixVlanTCI; /**< Vlan TCI */ - UINT8 ixDestMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Destination MAC address */ - UINT8 ixSourceMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Source MAC address */ -} IxEthAccNe; - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_PORT_UNKNOWN - * - * @brief Contents of the field @a IX_ETHACC_NE_DESTPORTID when no - * destination port can be found by the NPE for this frame. - * - */ -#define IX_ETHACC_NE_PORT_UNKNOWN (0xff) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_DESTMAC - * - * @brief The location of the destination MAC address in the Mbuf header. - * - */ -#define IX_ETHACC_NE_DESTMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestMac - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_SOURCEMAC - * - * @brief The location of the source MAC address in the Mbuf header. - * - */ -#define IX_ETHACC_NE_SOURCEMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourceMac - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANTCI - * - * @brief The VLAN Tag Control Information associated with this frame - * - * The VLAN Tag Control Information associated with this frame. On Rx - * path, this field is extracted from the packet header. - * On Tx path, the value of this field is inserted in the frame when - * the port is configured to insert or replace vlan tags in the - * egress frames. - * - * @sa IX_ETHACC_NE_FLAGS - */ -#define IX_ETHACC_NE_VLANTCI(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixVlanTCI - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_SOURCEPORTID - * - * @brief The port where this frame came from. - * - * The port where this frame came from. This field is set on receive - * with the port information. This field is ignored on Transmit path. - */ -#define IX_ETHACC_NE_SOURCEPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourcePortId - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_DESTPORTID - * - * @brief The destination port where this frame should be sent. - * - * The destination port where this frame should be sent. - * - * @li In the transmit direction, this field contains the destination port - * and is ignored unless @a IX_ETHACC_NE_FLAG_DST is set. - * - * @li In the receive direction, this field contains the port where the - * destination MAC addresses has been learned. If the destination - * MAC address is unknown, then this value is set to the reserved value - * @a IX_ETHACC_NE_PORT_UNKNOWN - * - */ -#define IX_ETHACC_NE_DESTPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestinationPortId - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_QOS - * - * @brief QualityOfService class (QoS) for this received frame. - * - */ -#define IX_ETHACC_NE_QOS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixQoS - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_FLAGS - * - * @brief Bit Mask of the different flags associated with a frame - * - * The flags are the bit-oring combination - * of the following different fields : - * - * @li IP flag (Rx @a IX_ETHACC_NE_IPMASK) - * @li Spanning Tree flag (Rx @a IX_ETHACC_NE_STMASK) - * @li Link layer type (Rx and Tx @a IX_ETHACC_NE_LINKMASK) - * @li VLAN Tagged Frame (Rx @a IX_ETHACC_NE_VLANMASK) - * @li New source MAC address (Rx @a IX_ETHACC_NE_NEWSRCMASK) - * @li Multicast flag (Rx @a IX_ETHACC_NE_MCASTMASK) - * @li Broadcast flag (Rx @a IX_ETHACC_NE_BCASTMASK) - * @li Destination port flag (Tx @a IX_ETHACC_NE_PORTMASK) - * @li Tag/Untag Tx frame (Tx @a IX_ETHACC_NE_TAGMODEMASK) - * @li Overwrite destination port (Tx @a IX_ETHACC_NE_PORTOVERMASK) - * @li Filtered frame (Rx @a IX_ETHACC_NE_STMASK) - * @li VLAN Enabled (Rx and Tx @a IX_ETHACC_NE_VLANENABLEMASK) - */ -#define IX_ETHACC_NE_FLAGS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixFlags - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_BCASTMASK - * - * @brief This mask defines if a received frame is a broadcast frame. - * - * This mask defines if a received frame is a broadcast frame. - * The BCAST flag is set when the destination MAC address of - * a frame is broadcast. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_BCASTMASK (0x1) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_MCASTMASK - * - * @brief This mask defines if a received frame is a multicast frame. - * - * This mask defines if a received frame is a multicast frame. - * The MCAST flag is set when the destination MAC address of - * a frame is multicast. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_MCASTMASK (0x1 << 1) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_IPMASK - * - * @brief This mask defines if a received frame is a IP frame. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS and defines if a received - * frame is a IP frame. The IP flag is set on Rx direction, depending on - * the frame contents. The flag is set when the length/type field of a - * received frame is 0x8000. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_IPMASK (0x1 << 2) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANMASK - * - * @brief This mask defines if a received frame is VLAN tagged. - * - * This mask defines if a received frame is VLAN tagged. - * When set, the Rx frame is VLAN-tagged and the tag value - * is available thru @a IX_ETHACC_NE_VLANID. - * Note that when sending frames which are already tagged - * this flag should be set, to avoid inserting another VLAN tag. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_VLANID - * - */ -#define IX_ETHACC_NE_VLANMASK (0x1 << 3) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_LINKMASK - * - * @brief This mask is the link layer protocol indicator - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * It reflects the state of a frame as it exits an NPE on the Rx path - * or enters an NPE on the Tx path. Its values are as follows: - * @li 0x00 - IEEE802.3 - 8802 (Rx) / IEEE802.3 - 8802 (Tx) - * @li 0x01 - IEEE802.3 - Ethernet (Rx) / IEEE802.3 - Ethernet (Tx) - * @li 0x02 - IEEE802.11 AP -> STA (Rx) / IEEE802.11 STA -> AP (Tx) - * @li 0x03 - IEEE802.11 AP -> AP (Rx) / IEEE802.11 AP->AP (Tx) - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_LINKMASK (0x3 << 4) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_STMASK - * - * @brief This mask defines if a received frame is a Spanning Tree frame. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * On rx direction, it defines if a received if frame is a Spanning Tree frame. - * Setting this fkag on transmit direction overrides the port settings - * regarding the VLAN options and - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_STMASK (0x1 << 6) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_FILTERMASK - * - * @brief This bit indicates whether a frame has been filtered by the Rx service. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * Certain frames, which should normally be fully filtered by the NPE to due - * the destination MAC address being on the same segment as the Rx port are - * still forwarded to the XScale (although the payload is invalid) in order - * to learn the MAC address of the transmitting station, if this is unknown. - * Normally EthAcc will filter and recycle these framess internally and no - * frames with the FILTER bit set will be received by the client. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_FILTERMASK (0x1 << 7) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_PORTMASK - * - * @brief This mask defines the rule to transmit a frame - * - * This mask defines the rule to transmit a frame. When set, a frame - * is transmitted to the destination port as set by the macro - * @a IX_ETHACC_NE_DESTPORTID. If not set, the destination port - * is searched using the destination MAC address. - * - * @note This flag is meaningful only for multiport Network Engines. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_DESTPORTID - * - */ -#define IX_ETHACC_NE_PORTOVERMASK (0x1 << 8) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_TAGMODEMASK - * - * @brief This mask defines the tagging rules to apply to a transmit frame. - * - * This mask defines the tagging rules to apply to a transmit frame - * regardless of the default setting for a port. When used together - * with @a IX_ETHACC_NE_TAGOVERMASK and when set, the - * frame will be tagged prior to transmission. When not set, - * the frame will be untagged prior to transmission. This is accomplished - * irrespective of the Egress tagging rules, constituting a per-frame override. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_TAGOVERMASK - * - */ -#define IX_ETHACC_NE_TAGMODEMASK (0x1 << 9) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_TAGOVERMASK - * - * @brief This mask defines the rule to transmit a frame - * - * This mask defines the rule to transmit a frame. When set, the - * default transmit rules of a port are overriden. - * When not set, the default rules as set by @ref IxEthDB should apply. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_TAGMODEMASK - * - */ -#define IX_ETHACC_NE_TAGOVERMASK (0x1 << 10) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANENABLEMASK - * - * @brief This mask defines if a frame is a VLAN frame or not - * - * When set, frames undergo normal VLAN processing on the Tx path - * (membership filtering, tagging, tag removal etc). If this flag is - * not set, the frame is considered to be a regular non-VLAN frame - * and no VLAN processing will be performed. - * - * Note that VLAN-enabled NPE images will always set this flag in all - * Rx frames, and images which are not VLAN enabled will clear this - * flag for all received frames. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_VLANENABLEMASK (0x1 << 14) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_NEWSRCMASK - * - * @brief This mask defines if a received frame has been learned. - * - * This mask defines if the source MAC address of a frame is - * already known. If the bit is set, the source MAC address was - * unknown to the NPE at the time the frame was received. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_NEWSRCMASK (0x1 << 15) - -/** - * @ingroup IxEthAcc - * - * @brief This defines the recommanded minimum size of MBUF's submitted - * to the frame receive service. - * - */ -#define IX_ETHACC_RX_MBUF_MIN_SIZE (2048) - -/** - * @ingroup IxEthAcc - * - * @brief This defines the highest MII address of any attached PHYs - * - * The maximum number for PHY address is 31, add on for range checking. - * - */ -#define IXP425_ETH_ACC_MII_MAX_ADDR 32 - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccInit(void) - * - * @brief Initializes the IXP400 Ethernet Access Service. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * This should be called once per module initialization. - * @pre - * The NPE must first be downloaded with the required microcode which supports all - * required features. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Service has failed to initialize. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccInit(void); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccUnload(void) - * - * @brief Unload the Ethernet Access Service. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @return void - * - *
- */ -PUBLIC void ixEthAccUnload(void); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortInit( IxEthAccPortId portId) - * - * @brief Initializes an NPE/Ethernet MAC Port. - * - * The NPE/Ethernet port initialisation includes the following steps - * @li Initialize the NPE/Ethernet MAC hardware. - * @li Verify NPE downloaded and operational. - * @li The NPE shall be available for usage once this API returns. - * @li Verify that the Ethernet port is present before initializing - * - * @li Reentrant - no - * @li ISR Callable - no - * - * This should be called once per mac device. - * The NPE/MAC shall be in disabled state after init. - * - * @pre - * The component must be initialized via @a ixEthAccInit - * The NPE must first be downloaded with the required microcode which supports all - * required features. - * - * Dependant on Services: (Must be initialized before using this service may be initialized) - * ixNPEmh - NPE Message handling service. - * ixQmgr - Queue Manager component. - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS: if the ethernet port is not present, a warning is issued. - * @li @a IX_ETH_ACC_FAIL : The NPE processor has failed to initialize. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortInit(IxEthAccPortId portId); - - -/************************************************************************* - - ##### ## ##### ## ##### ## ##### # # - # # # # # # # # # # # # # # - # # # # # # # # # # # # ###### - # # ###### # ###### ##### ###### # # # - # # # # # # # # # # # # # - ##### # # # # # # # # # # # - -*************************************************************************/ - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameSubmit( - IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority) - * - * @brief This function shall be used to submit MBUFs buffers for transmission on a particular MAC device. - * - * When the frame is transmitted, the buffer shall be returned thru the - * callback @a IxEthAccPortTxDoneCallback. - * - * In case of over-submitting, the order of the frames on the - * network may be modified. - * - * Buffers shall be not queued for transmission if the port is disabled. - * The port can be enabled using @a ixEthAccPortEnable - * - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @pre - * @a ixEthAccPortTxDoneCallbackRegister must be called to register a function to allow this service to - * return the buffer to the calling service. - * - * @note - * If the buffer submit fails for any reason the user has retained ownership of the buffer. - * - * @param portId @ref IxEthAccPortId [in] - MAC port ID to transmit Ethernet frame on. - * @param buffer @ref IX_OSAL_MBUF [in] - pointer to an MBUF formatted buffer. Chained buffers are supported for transmission. - * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is ignored. - * @param priority @ref IxEthAccTxPriority [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Failed to queue frame for transmission. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ - -PUBLIC IxEthAccStatus ixEthAccPortTxFrameSubmit( - IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority); - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Tx Buffer Done callback. Registered - * via @a ixEthAccTxBufferDoneCallbackRegister - * - * This function is called once the previously submitted buffer is no longer required by this service. - * It may be returned upon successful transmission of the frame or during the shutdown of - * the port prior to the transmission of a queued frame. - * The calling of this registered function is not a guarantee of successful transmission of the buffer. - * - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortTxDoneCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Tx mbuf descriptor. - * - * @return void - * - * @note - * The field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified by the access layer and reset to NULL. - * - *
- */ -typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *buffer ); - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, - IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the transmitted buffers to return to the user. - * - * This function registers the transmit buffer done function callback for a particular port. - * - * The registered callback function is called once the previously submitted buffer is no longer required by this service. - * It may be returned upon successful transmission of the frame or shutdown of port prior to submission. - * The calling of this registered function is not a guarantee of successful transmission of the buffer. - * - * If called several times the latest callback shall be registered for a particular port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre - * The port must be initialized via @a ixEthAccPortInit - * - * - * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device. - * @param txCallbackFn @ref IxEthAccPortTxDoneCallback [in] - Function to be called to return transmit buffers to the user. - * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId, - IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag); - - - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortRxCallbackRegister - * - * It is the responsibility of the user function to free any MBUF's which it receives. - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * @par - * - * This function dispatches frames to the user level - * via the provided function. The invocation shall be made for each - * frame dequeued from the Ethernet QM queue. The user is required to free any MBUF's - * supplied via this callback. In addition the registered callback must free up MBUF's - * from the receive free queue when the port is disabled - * - * If called several times the latest callback shall be registered for a particular port. - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * - * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortRxCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Rx mbuf header. Mbufs may be chained if - * the frame length is greater than the supplied mbuf length. - * @param reserved [in] - deprecated parameter The information is passed - * thru the IxEthAccNe header destination port ID field - * (@sa IX_ETHACC_NE_DESTPORTID). For backward - * compatibility,the value is equal to IX_ETH_DB_UNKNOWN_PORT (0xff). - * - * @return void - * - * @note - * Buffers may not be filled up to the length supplied in - * @a ixEthAccPortRxFreeReplenish(). The firmware fills - * them to the previous 64 bytes boundary. The user has to be aware - * that the length of the received mbufs may be smaller than the length - * of the supplied mbufs. - * The mbuf header contains the following modified field - * @li @a IX_OSAL_MBUF_PKT_LEN is set in the header of the first mbuf and indicates - * the total frame size - * @li @a IX_OSAL_MBUF_MLEN is set each mbuf header and indicates the payload length - * @li @a IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR contains a pointer to the next - * mbuf, or NULL at the end of a chain. - * @li @a IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified. Its value is reset to NULL - * @li @a IX_OSAL_MBUF_FLAGS contains the bit 4 set for a broadcast packet and the bit 5 - * set for a multicast packet. Other bits are unmodified. - * - *
- */ -typedef void (*IxEthAccPortRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF *buffer, UINT32 reserved); - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortMultiBufferRxCallbackRegister - * - * It is the responsibility of the user function to free any MBUF's which it receives. - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * @par - * - * This function dispatches many frames to the user level - * via the provided function. The invocation shall be made for multiple frames - * dequeued from the Ethernet QM queue. The user is required to free any MBUF's - * supplied via this callback. In addition the registered callback must free up MBUF's - * from the receive free queue when the port is disabled - * - * If called several times the latest callback shall be registered for a particular port. - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * - * @param callbackTag - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortMultiBufferRxCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf - Pointer to an array of Rx mbuf headers. Mbufs - * may be chained if - * the frame length is greater than the supplied mbuf length. - * The end of the array contains a zeroed entry (NULL pointer). - * - * @return void - * - * @note The mbufs passed to this callback have the same structure than the - * buffers passed to @a IxEthAccPortRxCallback interfac. - * - * @note The usage of this callback is exclusive with the usage of - * @a ixEthAccPortRxCallbackRegister and @a IxEthAccPortRxCallback - * - * @sa ixEthAccPortMultiBufferRxCallbackRegister - * @sa IxEthAccPortMultiBufferRxCallback - * @sa ixEthAccPortRxCallbackRegister - * @sa IxEthAccPortRxCallback - *
- */ - -typedef void (*IxEthAccPortMultiBufferRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF **buffer); - - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortRxCallback rxCallbackFn, UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the reception of frames. - * - * The registered callback function is called once a frame is received by this service. - * - * If called several times the latest callback shall be registered for a particular port. - * - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device. - * @param rxCallbackFn @ref IxEthAccPortRxCallback [in] - Function to be called when Ethernet frames are availble. - * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortRxCallback rxCallbackFn, - UINT32 callbackTag); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMultiBufferRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortMultiBufferRxCallback rxCallbackFn, UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the reception of frames. - * - * The registered callback function is called once a frame is - * received by this service. If many frames are already received, - * the function is called once. - * - * If called several times the latest callback shall be registered for a particular port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @param portId - Register callback for a particular MAC device. - * @param rxCallbackFn - @a IxEthAccMultiBufferRxCallbackFn - Function to be called when Ethernet frames are availble. - * @param callbackTag - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - * @sa ixEthAccPortMultiBufferRxCallbackRegister - * @sa IxEthAccPortMultiBufferRxCallback - * @sa ixEthAccPortRxCallbackRegister - * @sa IxEthAccPortRxCallback - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMultiBufferRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortMultiBufferRxCallback rxCallbackFn, - UINT32 callbackTag); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer) - * - * @brief This function provides buffers for the Ethernet receive path. - * - * This component does not have a buffer management mechanisms built in. All Rx buffers must be supplied to it - * via this interface. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @param portId @ref IxEthAccPortId [in] - Provide buffers only to specific Rx MAC. - * @param buffer @ref IX_OSAL_MBUF [in] - Provide an MBUF to the Ethernet receive mechanism. - * Buffers size smaller than IX_ETHACC_RX_MBUF_MIN_SIZE may result in poor - * performances and excessive buffer chaining. Buffers - * larger than this size may be suitable for jumbo frames. - * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR must be NULL. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Buffer has was not able to queue the - * buffer in the receive service. - * @li @a IX_ETH_ACC_FAIL : Buffer size is less than IX_ETHACC_RX_MBUF_MIN_SIZE - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - * @note - * If the buffer replenish operation fails it is the responsibility - * of the user to free the buffer. - * - * @note - * Sufficient buffers must be supplied to the component to maintain - * receive throughput and avoid rx buffer underflow conditions. - * To meet this goal, It is expected that the user preload the - * component with a sufficent number of buffers prior to enabling the - * NPE Ethernet receive path. The recommended minimum number of - * buffers is 8. - * - * @note - * For maximum performances, the mbuf size should be greater - * than the maximum frame size (Ethernet header, payload and FCS) + 64. - * Supplying smaller mbufs to the service results in mbuf - * chaining and degraded performances. The recommended size - * is @a IX_ETHACC_RX_MBUF_MIN_SIZE, which is - * enough to take care of 802.3 frames and "baby jumbo" frames without - * chaining, and "jumbo" frame within chaining. - * - * @note - * Buffers may not be filled up to their length. The firware fills - * them up to the previous 64 bytes boundary. The user has to be aware - * that the length of the received mbufs may be smaller than the length - * of the supplied mbufs. - * - * @warning This function checks the parameters if the NDEBUG - * flag is not defined. Turning on the argument checking (disabled by - * default) results in a lower EthAcc performance as this function - * is part of the data path. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer); - - - -/*************************************************************** - - #### #### # # ##### ##### #### # - # # # # ## # # # # # # # - # # # # # # # # # # # # - # # # # # # # ##### # # # - # # # # # ## # # # # # # - #### #### # # # # # #### ###### - - - ##### # ## # # ###### - # # # # # ## # # - # # # # # # # # ##### - ##### # ###### # # # # - # # # # # ## # - # ###### # # # # ###### - -***************************************************************/ - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortEnable(IxEthAccPortId portId) - * - * @brief This enables an Ethernet port for both Tx and Rx. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre The port must first be initialized via @a ixEthAccPortInit and the MAC address - * must be set using @a ixEthAccUnicastMacAddressSet before enabling it - * The rx and Tx Done callbacks registration via @a - * ixEthAccPortTxDoneCallbackRegister amd @a ixEthAccPortRxCallbackRegister - * has to be done before enabling the traffic. - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDisable(IxEthAccPortId portId) - * - * @brief This disables an Ethernet port for both Tx and Rx. - * - * Free MBufs are returned to the user via the registered callback when the port is disabled - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre The port must be enabled with @a ixEthAccPortEnable, otherwise this - * function has no effect - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled) - * - * @brief Get the enabled state of a port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre The port must first be initialized via @a ixEthAccPortInit - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * @param enabled BOOL [out] - location to store the state of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId) - * - * @brief Put the Ethernet MAC device in non-promiscuous mode. - * - * In non-promiscuous mode the MAC filters all frames other than - * destination MAC address which matches the following criteria: - * @li Unicast address provisioned via @a ixEthAccUnicastMacAddressSet - * @li All broadcast frames. - * @li Multicast addresses provisioned via @a ixEthAccMulticastAddressJoin - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortPromiscuousModeSet - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId) - * - * @brief Put the MAC device in promiscuous mode. - * - * If the device is in promiscuous mode then all all received frames shall be forwared - * to the NPE for processing. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortPromiscuousModeClear - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastMacAddressSet( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Configure unicast MAC address for a particular port - * - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastMacAddressGet( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Get unicast MAC address for a particular MAC port - * - * @pre - * The MAC address must first be set via @a ixEthAccMacPromiscuousModeSet - * If the MAC address has not been set, the function returns a - * IX_ETH_ACC_MAC_UNINITIALIZED status - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [out] - Ethernet MAC address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized. - * @li @a IX_ETH_ACC_FAIL : macAddr is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressJoin( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Add a multicast address to the MAC address table. - * - * @note - * Due to the operation of the Ethernet MAC multicast filtering mechanism, frames which do not - * have a multicast destination address which were provisioned via this API may be forwarded - * to the NPE's. This is a result of the hardware comparison algorithm used in the destination mac address logic - * within the Ethernet MAC. - * - * See Also: IXP425 hardware development manual. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Error writing to the MAC registers - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressJoinAll( IxEthAccPortId portId) - * - * @brief Filter all frames with multicast dest. - * - * This function clears the MAC address table, and then sets - * the MAC to forward ALL multicast frames to the NPE. - * Specifically, it forwards all frames whose destination address - * has the LSB of the highest byte set (01:00:00:00:00:00). This - * bit is commonly referred to as the "multicast bit". - * Broadcast frames will still be forwarded. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressLeave( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Remove a multicast address from the MAC address table. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_NO_SUCH_ADDR : Failed if MAC address was not in the table. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressLeaveAll( IxEthAccPortId portId) - * - * @brief This function unconfigures the multicast filtering settings - * - * This function first clears the MAC address table, and then sets - * the MAC as configured by the promiscuous mode current settings. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastAddressShow(IxEthAccPortId portId) - * - * @brief Displays unicast MAC address - * - * Displays unicast address which is configured using - * @a ixEthAccUnicastMacAddressSet. This function also displays the MAC filter used - * to filter multicast frames. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return void - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShow(IxEthAccPortId portId); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressShow( IxEthAccPortId portId) - * - * @brief Displays multicast MAC address - * - * Displays multicast address which have been configured using @a ixEthAccMulticastAddressJoin - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return void - * - *
- */ -PUBLIC void ixEthAccPortMulticastAddressShow( IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDuplexModeSet( IxEthAccPortId portId, IxEthAccDuplexMode mode ) - * - * @brief Set the duplex mode for the MAC. - * - * Configure the IXP400 MAC to either full or half duplex. - * - * @note - * The configuration should match that provisioned on the PHY. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * @param mode @ref IxEthAccDuplexMode [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeSet(IxEthAccPortId portId,IxEthAccDuplexMode mode); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDuplexModeGet( IxEthAccPortId portId, IxEthAccDuplexMode *mode ) - * - * @brief Get the duplex mode for the MAC. - * - * return the duplex configuration of the IXP400 MAC. - * - * @note - * The configuration should match that provisioned on the PHY. - * See @a ixEthAccDuplexModeSet - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * @param *mode @ref IxEthAccDuplexMode [out] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- * - */ -PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeGet(IxEthAccPortId portId,IxEthAccDuplexMode *mode ); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendPaddingEnable( IxEthAccPortId portId) - * - * @brief Enable padding bytes to be appended to runt frames submitted to - * this port - * - * Enable up to 60 null-bytes padding bytes to be appended to runt frames - * submitted to this port. This is the default behavior of the access - * component. - * - * @warning Do not change this behaviour while the port is enabled. - * - * @note When Tx padding is enabled, Tx FCS generation is turned on - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortTxFrameAppendFCSDusable - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendPaddingDisable( IxEthAccPortId portId) - * - * @brief Disable padding bytes to be appended to runt frames submitted to - * this port - * - * Disable padding bytes to be appended to runt frames - * submitted to this port. This is not the default behavior of the access - * component. - * - * @warning Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendFCSEnable( IxEthAccPortId portId) - * - * @brief Enable the appending of Ethernet FCS to all frames submitted to this port - * - * When enabled, the FCS is added to the submitted frames. This is the default - * behavior of the access component. - * Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendFCSDisable( IxEthAccPortId portId) - * - * @brief Disable the appending of Ethernet FCS to all frames submitted to this port. - * - * When disabled, the Ethernet FCS is not added to the submitted frames. - * This is not the default - * behavior of the access component. - * - * @note Since the FCS is not appended to the frame it is expected that the frame submitted to the - * component includes a valid FCS at the end of the data, although this will not be validated. - * - * The component shall forward the frame to the Ethernet MAC WITHOUT modification. - * - * Do not change this behaviour while the port is enabled. - * - * @note Tx FCS append is not disabled while Tx padding is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortTxFrameAppendPaddingEnable - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFrameAppendFCSEnable( IxEthAccPortId portId) - * - * @brief Forward frames with FCS included in the receive buffer. - * - * The FCS is not striped from the receive buffer. - * The received frame length includes the FCS size (4 bytes). ie. - * A minimum sized ethernet frame shall have a length of 64bytes. - * - * Frame FCS validity checks are still carried out on all received frames. - * - * This is not the default - * behavior of the access component. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFrameAppendFCSDisable( IxEthAccPortId portId) - * - * @brief Do not forward the FCS portion of the received Ethernet frame to the user. - * The FCS is striped from the receive buffer. - * The received frame length does not include the FCS size (4 bytes). - * Frame FCS validity checks are still carried out on all received frames. - * - * This is the default behavior of the component. - * Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId); - - - - -/** - * @ingroup IxEthAcc - * - * @enum IxEthAccSchedulerDiscipline - * - * @brief Definition for the port scheduling discipline - * - * Select the port scheduling discipline on receive and transmit path - * @li FIFO : No Priority : In this configuration all frames are processed - * in the access component in the strict order in which - * the component received them. - * @li FIFO : Priority : This shall be a very simple priority mechanism. - * Higher prior-ity frames shall be forwarded - * before lower priority frames. There shall be no - * fairness mechanisms applied across different - * priorities. Higher priority frames could starve - * lower priority frames indefinitely. - */ -typedef enum -{ - FIFO_NO_PRIORITY, /** - */ -PUBLIC IxEthAccStatus -ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, - IxEthAccSchedulerDiscipline sched); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched) - * - * @brief Set the Rx scheduling to one of @a IxEthAccSchedulerDiscipline - * - * The default behavior of the component is @a FIFO_NO_PRIORITY. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param sched : @a IxEthAccSchedulerDiscipline - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline. - * @li @a IX_ETH_ACC_FAIL : Invalid/unsupported discipline. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccNpeLoopbackEnable(IxEthAccPortId portId) - * - * @brief Enable NPE loopback - * - * When this loopback mode is enabled all the transmitted frames are - * received on the same port, without payload. - * - * This function is recommended for power-up diagnostic checks and - * should never be used under normal Ethernet traffic operations. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param portId : ID of the port - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : NPE loopback mode enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId) - * - * @brief Disable NPE loopback - * - * This function is used to disable the NPE loopback if previously - * enabled using ixEthAccNpeLoopbackEnable. - * - * This function is recommended for power-up diagnostic checks and - * should never be used under normal Ethernet traffic operations. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : NPE loopback successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortTxEnable(IxEthAccPortId portId) - * - * @brief Enable Tx on the port - * - * This function is the complement of ixEthAccPortTxDisable and should - * be used only after Tx was disabled. A MAC core reset is required before - * this function is called (see @a ixEthAccPortMacReset). - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Tx successfully enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortTxDisable(IxEthAccPortId portId) - * - * @brief Disable Tx on the port - * - * This function can be used to disable Tx in the MAC core. - * Tx can be re-enabled, although this is not guaranteed, by performing - * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortTxEnable. - * Note that using this function is not recommended, except for shutting - * down Tx for emergency reasons. For proper port shutdown and re-enabling - * see ixEthAccPortEnable and ixEthAccPortDisable. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @pre - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Tx successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortRxEnable(IxEthAccPortId portId) - * - * @brief Enable Rx on the port - * - * This function is the complement of ixEthAccPortRxDisable and should - * be used only after Rx was disabled. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @pre - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Rx successfully enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortRxDisable(IxEthAccPortId portId) - * - * @brief Disable Rx on the port - * - * This function can be used to disable Rx in the MAC core. - * Rx can be re-enabled, although this is not guaranteed, by performing - * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortRxEnable. - * Note that using this function is not recommended, except for shutting - * down Rx for emergency reasons. For proper port shutdown and re-enabling - * see ixEthAccPortEnable and ixEthAccPortDisable. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Rx successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortMacReset(IxEthAccPortId portId) - * - * @brief Reset MAC core on the port - * - * This function will perform a MAC core reset (NPE Ethernet coprocessor). - * This function is inherently unsafe and the NPE recovery is not guaranteed - * after this function is called. The proper manner of performing port disable - * and enable (which will reset the MAC as well) is ixEthAccPortEnable/ixEthAccPortDisable. - * - * This function is the recommended usage scenario for hardware failure recovery - * and should never be used for throttling traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : MAC core reset - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMacReset(IxEthAccPortId portId); - -/********************************************************************************* - #### ##### ## ##### # #### ##### # #### #### - # # # # # # # # # # # # - #### # # # # # #### # # # #### - # # ###### # # # # # # # - # # # # # # # # # # # # # # # - #### # # # # # #### # # #### #### -**********************************************************************************/ - - -/** - * - * @brief This struct defines the statistics returned by this component. - * - * The component returns MIB2 EthObj variables which are obtained from the - * hardware or maintained by this component. - * - * - */ -typedef struct -{ - UINT32 dot3StatsAlignmentErrors; /**< link error count (rx) */ - UINT32 dot3StatsFCSErrors; /**< link error count (rx) */ - UINT32 dot3StatsInternalMacReceiveErrors; /**< link error count (rx) */ - UINT32 RxOverrunDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxLearnedEntryDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxLargeFramesDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxSTPBlockedDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxVLANTypeFilterDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxVLANIdFilterDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxInvalidSourceDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxBlackListDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxWhiteListDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxUnderflowEntryDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 dot3StatsSingleCollisionFrames; /**< link error count (tx) */ - UINT32 dot3StatsMultipleCollisionFrames; /**< link error count (tx) */ - UINT32 dot3StatsDeferredTransmissions; /**< link error count (tx) */ - UINT32 dot3StatsLateCollisions; /**< link error count (tx) */ - UINT32 dot3StatsExcessiveCollsions; /**< link error count (tx) */ - UINT32 dot3StatsInternalMacTransmitErrors; /**< link error count (tx) */ - UINT32 dot3StatsCarrierSenseErrors; /**< link error count (tx) */ - UINT32 TxLargeFrameDiscards; /**< NPE: discarded frames count (tx) */ - UINT32 TxVLANIdFilterDiscards; /**< NPE: discarded frames count (tx) */ - -}IxEthEthObjStats; - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsGet(IxEthAccPortId portId ,IxEthEthObjStats *retStats ) - * - * @brief Returns the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * - * @param portId @ref IxEthAccPortId [in] - * @param retStats @ref IxEthEthObjStats [out] - * @note Please note the user is responsible for cache coheriency of the retStat - * buffer. The data is actually populated via the NPE's. As such cache safe - * memory should be used in the retStats argument. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMibIIStatsGet(IxEthAccPortId portId, IxEthEthObjStats *retStats ); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats) - * - * @brief Returns and clears the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * @param retStats @ref IxEthEthObjStats [out] - * @note Please note the user is responsible for cache coheriency of the retStats - * buffer. The data is actually populated via the NPE's. As such cache safe - * memory should be used in the retStats argument. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsClear(IxEthAccPortId portId) - * - * @brief Clears the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMibIIStatsClear(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMacInit(IxEthAccPortId portId) - * - * @brief Initializes the ethernet MAC settings - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMacInit(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccStatsShow(IxEthAccPortId portId) - * - * - * @brief Displays a ports statistics on the standard io console using printf. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * - * @return void - * - *
- */ -PUBLIC void ixEthAccStatsShow(IxEthAccPortId portId); - -/************************************************************************* - - # # # # # # ##### # #### - ## ## # # ## ## # # # # # - # ## # # # # ## # # # # # # - # # # # # # # # # # # - # # # # # # # # # # # - # # # # # # ##### # #### - -*************************************************************************/ - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiReadRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 *value) - * - * - * @brief Reads a 16 bit value from a PHY - * - * Reads a 16-bit word from a register of a MII-compliant PHY. Reading - * is performed through the MII management interface. This function returns - * when the read operation has successfully completed, or when a timeout has elapsed. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31) - * @param phyReg UINT8 [in] - the number of the MII register to read (0-31) - * @param value UINT16 [in] - the value read from the register - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : failed to read the register. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiReadRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 *value); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiWriteRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 value) - * - * - * @brief Writes a 16 bit value to a PHY - * - * Writes a 16-bit word from a register of a MII-compliant PHY. Writing - * is performed through the MII management interface. This function returns - * when the write operation has successfully completed, or when a timeout has elapsed. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31) - * @param phyReg UINT8 [in] - the number of the MII register to write (0-31) - * @param value UINT16 [out] - the value to write to the register - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : failed to write register. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiWriteRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 value); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiAccessTimeoutSet(UINT32 timeout) - * - * @brief Overrides the default timeout value and retry count when reading or - * writing MII registers using ixEthAccMiiWriteRtn or ixEthAccMiiReadRtn - * - * The default behavior of the component is to use a IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS ms - * timeout (declared as 100 in IxEthAccMii_p.h) and a retry count of IX_ETH_ACC_MII_TIMEOUT_10TH_SECS - * (declared as 5 in IxEthAccMii_p.h). - * - * The MII read and write functions will attempt to read the status of the register up - * to the retry count times, delaying between each attempt with the timeout value. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre - * - * @param timeout UINT32 [in] - new timeout value, in milliseconds - * @param timeout UINT32 [in] - new retry count (a minimum value of 1 must be used) - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid parameter(s) - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiStatsShow (UINT32 phyAddr) - * - * - * @brief Displays detailed information on a specified PHY - * - * Displays the current values of the first eigth MII registers for a PHY, - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and - * generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid arguments. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMiiStatsShow (UINT32 phyAddr); - - - -/******* BOARD SPECIFIC DEPRECATED API *********/ - -/* The following functions are high level functions which rely - * on the properties and interface of some Ethernet PHYs. The - * implementation is hardware specific and has been moved to - * the hardware-specific component IxEthMii. - */ - - #include "IxEthMii.h" - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyScan - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyScan - * - * @note this feature is board specific - * - */ -#define ixEthAccMiiPhyScan(phyPresent) ixEthMiiPhyScan(phyPresent,IXP425_ETH_ACC_MII_MAX_ADDR) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyConfig - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyConfig - * - * @note this feature is board specific - */ -#define ixEthAccMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) \ - ixEthMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyReset - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyReset - * - * @note this feature is board specific - */ -#define ixEthAccMiiPhyReset(phyAddr) \ - ixEthMiiPhyReset(phyAddr) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiLinkStatus - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiLinkStatus - * - * @note this feature is board specific - */ -#define ixEthAccMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) \ - ixEthMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) - - - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiShow - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyShow - * - * @note this feature is board specific - */ -#define ixEthAccMiiShow(phyAddr) \ - ixEthMiiPhyShow(phyAddr) - -#endif /* ndef IxEthAcc_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthAccDataPlane_p.h b/drivers/net/npe/include/IxEthAccDataPlane_p.h deleted file mode 100644 index 8b8e6b256c..0000000000 --- a/drivers/net/npe/include/IxEthAccDataPlane_p.h +++ /dev/null @@ -1,245 +0,0 @@ -/** - * @file IxEthAccDataPlane_p.h - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief Internal Header file for IXP425 Ethernet Access component. - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - - - -#ifndef IxEthAccDataPlane_p_H -#define IxEthAccDataPlane_p_H - -#include -#include - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* typedefs global to this file*/ - -typedef struct -{ - IX_OSAL_MBUF *pHead; - IX_OSAL_MBUF *pTail; -}IxEthAccDataPlaneQList; - - -/** - * @struct IxEthAccDataPlaneStats - * @brief Statistics data structure associated with the data plane - * - */ -typedef struct -{ - UINT32 addToSwQ; - UINT32 removeFromSwQ; - UINT32 unchainedTxMBufs; - UINT32 chainedTxMBufs; - UINT32 unchainedTxDoneMBufs; - UINT32 chainedTxDoneMBufs; - UINT32 unchainedRxMBufs; - UINT32 chainedRxMBufs; - UINT32 unchainedRxFreeMBufs; - UINT32 chainedRxFreeMBufs; - UINT32 rxCallbackCounter; - UINT32 rxCallbackBurstRead; - UINT32 txDoneCallbackCounter; - UINT32 unexpectedError; -} IxEthAccDataPlaneStats; - -/** - * @fn ixEthAccMbufFromSwQ - * @brief used during disable steps to convert mbufs from - * swq format, ready to be pushed into hw queues for NPE, - * back into XScale format - */ -IX_OSAL_MBUF *ixEthAccMbufFromSwQ(IX_OSAL_MBUF *mbuf); - -/** - * @fn ixEthAccDataPlaneShow - * @brief Show function (for data plane statistics - */ -void ixEthAccDataPlaneShow(void); - -/* - * lock dataplane when atomic operation is required - */ -#define IX_ETH_ACC_DATA_PLANE_LOCK(arg) arg = ixOsalIrqLock(); -#define IX_ETH_ACC_DATA_PLANE_UNLOCK(arg) ixOsalIrqUnlock(arg); - -/* - * Use MBUF fields - */ -#define IX_ETHACC_NE_SHARED(mBufPtr) \ - ((IxEthAccNe *)&((mBufPtr)->ix_ne)) - -#if 1 - -#define IX_ETHACC_NE_NEXT(mBufPtr) (mBufPtr)->ix_ne.reserved[0] - -/* tm - wrong!! len and pkt_len are in the second word - #define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[3] */ -#define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[1] - -#define IX_ETHACC_NE_DATA(mBufPtr)(mBufPtr)->ix_ne.reserved[2] - -#else - -#define IX_ETHACC_NE_NEXT(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_next - -#define IX_ETHACC_NE_LEN(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_lengths - -#define IX_ETHACC_NE_DATA(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_data -#endif - -/* - * Use MBUF next pointer field to chain data. - */ -#define IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER(mbuf) (mbuf)->ix_ctrl.ix_chain - - - -#define IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(mbuf_list) ((mbuf_list.pHead) == NULL) - - -#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(mbuf_list,mbuf_to_add) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \ - if ( (mbuf_list.pHead) != NULL ) \ - { \ - (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add))) = (mbuf_list.pHead);\ - (mbuf_list.pHead) = (mbuf_to_add); \ - } \ - else { \ - (mbuf_list.pTail) = (mbuf_list.pHead) = (mbuf_to_add); \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while(0) - - -#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(mbuf_list,mbuf_to_add) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \ - if ( (mbuf_list.pHead) == NULL ) \ - { \ - (mbuf_list.pHead) = mbuf_to_add; \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - else { \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_list.pTail)) = (mbuf_to_add); \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - (mbuf_list.pTail) = mbuf_to_add; \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while (0) - - -#define IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(mbuf_list,mbuf_to_rem) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - if ( (mbuf_list.pHead) != NULL ) \ - { \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.removeFromSwQ); \ - (mbuf_to_rem) = (mbuf_list.pHead) ; \ - (mbuf_list.pHead) = (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_rem)));\ - } \ - else { \ - (mbuf_to_rem) = NULL; \ - } \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while (0) - - -/** - * @brief message handler QManager entries for NPE id => port ID conversion (NPE_B => 0, NPE_C => 1) - */ -#define IX_ETH_ACC_PORT_TO_NPE_ID(port) \ - ixEthAccPortData[(port)].npeId - -#define IX_ETH_ACC_NPE_TO_PORT_ID(npe) ((npe == 0 ? 2 : (npe == 1 ? 0 : ( npe == 2 ? 1 : -1 )))) - -#define IX_ETH_ACC_PORT_TO_TX_Q_ID(port) \ - ixEthAccPortData[(port)].ixEthAccTxData.txQueue - -#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(port) \ - ixEthAccPortData[(port)].ixEthAccRxData.rxFreeQueue - -#define IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE : IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE)) - -#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE : IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE )) - -/* Flush the mbufs chain and all data pointed to by the mbuf */ - -#ifndef NDEBUG -#define IX_ETH_ACC_STATS_INC(x) (x++) -#else -#define IX_ETH_ACC_STATS_INC(x) -#endif - -#define IX_ETH_ACC_MAX_TX_FRAMES_TO_SUBMIT 128 - -void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); -void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); -void ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); - -#endif /* IxEthAccDataPlane_p_H */ - - -/** - *@} - */ - diff --git a/drivers/net/npe/include/IxEthAccMac_p.h b/drivers/net/npe/include/IxEthAccMac_p.h deleted file mode 100644 index 93e9d98e76..0000000000 --- a/drivers/net/npe/include/IxEthAccMac_p.h +++ /dev/null @@ -1,248 +0,0 @@ -/* - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - - -#ifndef IxEthAccMac_p_H -#define IxEthAccMac_p_H - -#include "IxOsal.h" - -#define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256 -#define IX_ETH_ACC_NUM_PORTS 3 -#define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536 -#define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64) -#define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64 - -/* - * - * MAC register definitions - * - */ -#define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE -#define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE -#define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE - -#define IX_ETH_ACC_MAC_TX_CNTRL1 0x000 -#define IX_ETH_ACC_MAC_TX_CNTRL2 0x004 -#define IX_ETH_ACC_MAC_RX_CNTRL1 0x010 -#define IX_ETH_ACC_MAC_RX_CNTRL2 0x014 -#define IX_ETH_ACC_MAC_RANDOM_SEED 0x020 -#define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030 -#define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038 -#define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040 -#define IX_ETH_ACC_MAC_TX_DEFER 0x050 -#define IX_ETH_ACC_MAC_RX_DEFER 0x054 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064 -#define IX_ETH_ACC_MAC_SLOT_TIME 0x070 -#define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080 -#define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084 -#define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088 -#define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c -#define IX_ETH_ACC_MAC_MDIO_STS_1 0x090 -#define IX_ETH_ACC_MAC_MDIO_STS_2 0x094 -#define IX_ETH_ACC_MAC_MDIO_STS_3 0x098 -#define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c -#define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0 -#define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4 -#define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8 -#define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC -#define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0 -#define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4 -#define IX_ETH_ACC_MAC_ADDR_1 0x0C0 -#define IX_ETH_ACC_MAC_ADDR_2 0x0C4 -#define IX_ETH_ACC_MAC_ADDR_3 0x0C8 -#define IX_ETH_ACC_MAC_ADDR_4 0x0CC -#define IX_ETH_ACC_MAC_ADDR_5 0x0D0 -#define IX_ETH_ACC_MAC_ADDR_6 0x0D4 -#define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0 -#define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0 -#define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4 -#define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8 -#define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC -#define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100 -#define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104 -#define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC - - -/* - * - *Bit definitions - * - */ - -/* TX Control Register 1*/ - -#define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0) -#define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1) -#define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2) -#define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3) -#define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4) -#define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5) -#define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6) - -/* TX Control Register 2 */ -#define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf - -/* RX Control Register 1 */ -#define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0) -#define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1) -#define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2) -#define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3) -#define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4) -#define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5) -#define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6) -#define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7) - -/* RX Control Register 2 */ -#define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0) - - - -/* Core Control Register */ -#define IX_ETH_ACC_CORE_RESET BIT(0) -#define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1) -#define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2) -#define IX_ETH_ACC_CORE_SEND_JAM BIT(3) -#define IX_ETH_ACC_CORE_MDC_EN BIT(4) - -/* 1st bit of 1st MAC octet */ -#define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1) - - -/* - * - * Default values - * - */ - - -#define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \ - IX_ETH_ACC_TX_CNTRL1_RETRY | \ - IX_ETH_ACC_TX_CNTRL1_FCS_EN | \ - IX_ETH_ACC_TX_CNTRL1_2DEFER | \ - IX_ETH_ACC_TX_CNTRL1_PAD_EN) - -#define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f - -#define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \ - | IX_ETH_ACC_RX_CNTRL1_RX_EN) - -#define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0 - -/* Thresholds determined by NPE firmware FS */ -#define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12 -#define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30 - -/* Number of bytes that must be in the tx fifo before - transmission commences*/ -#define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8 - -/* One-part deferral values */ -#define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15 -#define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16 - -/* Two-part deferral values... */ -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07 - -/* This value applies to MII */ -#define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80 - -/* This value applies to RMII */ -#define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF - -#define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF - -#define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1 -/*The following is a value chosen at random*/ -#define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8 - -/*By default we must configure the MAC to generate the - MDC clock*/ -#define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN) - -#define IXP425_ETH_ACC_MAX_PHY 2 -#define IXP425_ETH_ACC_MAX_AN_ENTRIES 20 -#define IX_ETH_ACC_MAC_RESET_DELAY 1 - -#define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF - -#define IX_ETH_ACC_MAC_MSGID_SHL 24 - -#define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20 -#define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */ -#define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3 -#define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */ - -/*Register access macros*/ -#if (CPU == SIMSPARCSOLARIS) -extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val); -extern UINT32 registerReadStub (UINT32 base, UINT32 offset); - -#define REG_WRITE(b,o,v) registerWriteStub(b, o, v) -#define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0) -#else -#define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v) -#define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o))) - -#endif - -void ixEthAccMacUnload(void); -IxEthAccStatus ixEthAccMacMemInit(void); - -/* MAC core loopback */ -IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId); - -/* MAC core traffic control */ -IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId); - -/* NPE software loopback */ -IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId); - -#endif /*IxEthAccMac_p_H*/ - diff --git a/drivers/net/npe/include/IxEthAccMii_p.h b/drivers/net/npe/include/IxEthAccMii_p.h deleted file mode 100644 index 568d4a0fa4..0000000000 --- a/drivers/net/npe/include/IxEthAccMii_p.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * @file IxEthAccMii_p.h - * - * @author Intel Corporation - * @date - * - * @brief MII Header file - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthAccMii_p_H -#define IxEthAccMii_p_H - -/* MII definitions - these have been verified against the LXT971 and LXT972 PHYs*/ - -#define IXP425_ETH_ACC_MII_MAX_REG 32 /* max register per phy */ - -#define IX_ETH_ACC_MII_REG_SHL 16 -#define IX_ETH_ACC_MII_ADDR_SHL 21 - -/* Definitions for MII access routines*/ - -#define IX_ETH_ACC_MII_GO BIT(31) -#define IX_ETH_ACC_MII_WRITE BIT(26) -#define IX_ETH_ACC_MII_TIMEOUT_10TH_SECS 5 -#define IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS 100 -#define IX_ETH_ACC_MII_READ_FAIL BIT(31) - -#define IX_ETH_ACC_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */ -#define IX_ETH_ACC_MII_PHY_NO_DELAY 0x0 /* do not delay */ -#define IX_ETH_ACC_MII_PHY_NULL 0xff /* PHY is not present */ -#define IX_ETH_ACC_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */ - -#ifndef IX_ETH_ACC_MII_MONITOR_DELAY -# define IX_ETH_ACC_MII_MONITOR_DELAY 0x5 /* in seconds */ -#endif - -/* Register definition */ - -#define IX_ETH_ACC_MII_CTRL_REG 0x0 /* Control Register */ -#define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */ -#define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ -#define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ - /* Advertisement Register */ -#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ - /* partner ability Register */ -#define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ - /* Expansion Register */ -#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ - /* next-page transmit Register */ - -IxEthAccStatus ixEthAccMdioShow (void); -IxEthAccStatus ixEthAccMiiInit(void); -void ixEthAccMiiUnload(void); - -#endif /*IxEthAccMii_p_H*/ diff --git a/drivers/net/npe/include/IxEthAccQueueAssign_p.h b/drivers/net/npe/include/IxEthAccQueueAssign_p.h deleted file mode 100644 index e5fd16e2fb..0000000000 --- a/drivers/net/npe/include/IxEthAccQueueAssign_p.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file IxEthAccQueueAssign_p.h - * - * @author Intel Corporation - * @date 06-Mar-2002 - * - * @brief Mapping from QMgr Q's to internal assignment - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* - * Os/System dependancies. - */ -#include "IxOsal.h" - -/* - * Intermodule dependancies - */ -#include "IxQMgr.h" -#include "IxQueueAssignments.h" - -/* Check range of Q's assigned to this component. */ -#if IX_ETH_ACC_RX_FRAME_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID ) | \ - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID) -#error "Not all Ethernet Access Queues are betweem 1-31, requires full functionalty Q's unless otherwise validated " -#endif - -/** -* -* @typedef IxEthAccQregInfo -* -* @brief -* -*/ -typedef struct -{ - IxQMgrQId qId; - char *qName; - IxQMgrCallback qCallback; - IxQMgrCallbackId callbackTag; - IxQMgrQSizeInWords qSize; - IxQMgrQEntrySizeInWords qWords; - BOOL qNotificationEnableAtStartup; - IxQMgrSourceId qConditionSource; - IxQMgrWMLevel AlmostEmptyThreshold; - IxQMgrWMLevel AlmostFullThreshold; - -} IxEthAccQregInfo; - -/* - * Prototypes for all QM callbacks. - */ - -/* - * Rx Callbacks - */ -IX_ETH_ACC_PUBLIC -void ixEthRxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthRxMultiBufferQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthRxFreeQMCallback(IxQMgrQId, IxQMgrCallbackId); - -/* - * Tx Callback. - */ -IX_ETH_ACC_PUBLIC -void ixEthTxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthTxFrameDoneQMCallback(IxQMgrQId, IxQMgrCallbackId ); - - -#define IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY (IX_QMGR_Q_PRIORITY_0) /* Highest priority */ - -/* - * Queue watermarks - */ -#define IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E ) diff --git a/drivers/net/npe/include/IxEthAcc_p.h b/drivers/net/npe/include/IxEthAcc_p.h deleted file mode 100644 index eda3e303be..0000000000 --- a/drivers/net/npe/include/IxEthAcc_p.h +++ /dev/null @@ -1,325 +0,0 @@ -/** - * @file IxEthAcc_p.h - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief Internal Header file for IXP425 Ethernet Access component. - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -#ifndef IxEthAcc_p_H -#define IxEthAcc_p_H - -/* - * Os/System dependancies. - */ -#include "IxOsal.h" - -/* - * Intermodule dependancies - */ -#include "IxNpeDl.h" -#include "IxQMgr.h" - -#include "IxEthNpe.h" - -/* - * Intra module dependancies - */ - -#include "IxEthAccDataPlane_p.h" -#include "IxEthAccMac_p.h" - - -#define INLINE __inline__ - -#ifdef NDEBUG - -#define IX_ETH_ACC_PRIVATE static - -#else - -#define IX_ETH_ACC_PRIVATE - -#endif /* ndef NDEBUG */ - -#define IX_ETH_ACC_PUBLIC - - -#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false ) - - - -#ifndef NDEBUG -#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#else -#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {} -#endif - -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries); - -/* prototypes for the private control plane functions (used by the control interface wrapper) */ -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched); - -/** - * @struct ixEthAccRxDataStats - * @brief Stats data structures for data path. - Not obtained from h/w - * - */ -typedef struct -{ - UINT32 rxFrameClientCallback; - UINT32 rxFreeRepOK; - UINT32 rxFreeRepDelayed; - UINT32 rxFreeRepFromSwQOK; - UINT32 rxFreeRepFromSwQDelayed; - UINT32 rxFreeLateNotificationEnabled; - UINT32 rxFreeLowCallback; - UINT32 rxFreeOverflow; - UINT32 rxFreeLock; - UINT32 rxDuringDisable; - UINT32 rxSwQDuringDisable; - UINT32 rxUnlearnedMacAddress; - UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1]; - UINT32 rxUnexpectedError; - UINT32 rxFiltered; -} IxEthAccRxDataStats; - -/** - * @struct IxEthAccTxDataStats - * @brief Stats data structures for data path. - Not obtained from h/w - * - */ -typedef struct -{ - UINT32 txQOK; - UINT32 txQDelayed; - UINT32 txFromSwQOK; - UINT32 txFromSwQDelayed; - UINT32 txLowThreshCallback; - UINT32 txDoneClientCallback; - UINT32 txDoneClientCallbackDisable; - UINT32 txOverflow; - UINT32 txLock; - UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1]; - UINT32 txLateNotificationEnabled; - UINT32 txDoneDuringDisable; - UINT32 txDoneSwQDuringDisable; - UINT32 txUnexpectedError; -} IxEthAccTxDataStats; - -/* port Disable state machine : list of states */ -typedef enum -{ - /* general port states */ - DISABLED = 0, - ACTIVE, - - /* particular Tx/Rx states */ - REPLENISH, - RECEIVE, - TRANSMIT, - TRANSMIT_DONE -} IxEthAccPortDisableState; - -typedef struct -{ - BOOL fullDuplex; - BOOL rxFCSAppend; - BOOL txFCSAppend; - BOOL txPADAppend; - BOOL enabled; - BOOL promiscuous; - BOOL joinAll; - IxOsalMutex ackMIBStatsLock; - IxOsalMutex ackMIBStatsResetLock; - IxOsalMutex MIBStatsGetAccessLock; - IxOsalMutex MIBStatsGetResetAccessLock; - IxOsalMutex npeLoopbackMessageLock; - IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES]; - UINT32 mcastAddrIndex; - IX_OSAL_MBUF *portDisableTxMbufPtr; - IX_OSAL_MBUF *portDisableRxMbufPtr; - - volatile IxEthAccPortDisableState portDisableState; - volatile IxEthAccPortDisableState rxState; - volatile IxEthAccPortDisableState txState; - - BOOL initDone; - BOOL macInitialised; -} IxEthAccMacState; - -/** - * @struct IxEthAccRxInfo - * @brief System-wide data structures associated with the data plane. - * - */ -typedef struct -{ - IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */ - IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */ -} IxEthAccInfo; - -/** - * @struct IxEthAccRxDataInfo - * @brief Per Port data structures associated with the receive data plane. - * - */ -typedef struct -{ - IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */ - IxEthAccPortRxCallback rxCallbackFn; - UINT32 rxCallbackTag; - IxEthAccDataPlaneQList freeBufferList; - IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn; - UINT32 rxMultiBufferCallbackTag; - BOOL rxMultiBufferCallbackInUse; - IxEthAccRxDataStats stats; /**< Receive s/w stats */ -} IxEthAccRxDataInfo; - -/** - * @struct IxEthAccTxDataInfo - * @brief Per Port data structures associated with the transmit data plane. - * - */ -typedef struct -{ - IxEthAccPortTxDoneCallback txBufferDoneCallbackFn; - UINT32 txCallbackTag; - IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ - IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */ - IxQMgrQId txQueue; /**< txQueue for this port */ - IxEthAccTxDataStats stats; /**< Transmit s/w stats */ -} IxEthAccTxDataInfo; - - -/** - * @struct IxEthAccPortDataInfo - * @brief Per Port data structures associated with the port data plane. - * - */ -typedef struct -{ - BOOL portInitialized; - UINT32 npeId; /**< NpeId for this port */ - IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */ - IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */ -} IxEthAccPortDataInfo; - -extern IxEthAccPortDataInfo ixEthAccPortData[]; -#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized) - -extern BOOL ixEthAccServiceInit; -#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true ) - -/* - * Maximum number of frames to consume from the Rx Frame Q. - */ - -#define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128) - -/* - * Max number of times to load the Rx Free Q from callback. - */ -#define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */ - -/* - * Max number of times to read from the Tx Done Q in one sitting. - */ - -#define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256) - -/* - * Max number of times to take buffers from S/w queues and write them to the H/w Tx - * queues on receipt of a Tx low threshold callback - */ - -#define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16) - - -#define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size)) -#define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size)) - - -#define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size) - -#endif /* ndef IxEthAcc_p_H */ - - - diff --git a/drivers/net/npe/include/IxEthDB.h b/drivers/net/npe/include/IxEthDB.h deleted file mode 100644 index dfdfe1ae57..0000000000 --- a/drivers/net/npe/include/IxEthDB.h +++ /dev/null @@ -1,2373 +0,0 @@ -/** @file IxEthDB.h - * - * @brief this file contains the public API of @ref IxEthDB component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * - */ - -#ifndef IxEthDB_H -#define IxEthDB_H - -#include -#include - -/** - * @defgroup IxEthDB IXP400 Ethernet Database (IxEthDB) API - * - * @brief ethDB is a library that does provides a MAC address database learning/filtering capability - * - *@{ - */ - -#define INLINE __inline__ - -#define IX_ETH_DB_PRIVATE PRIVATE /* imported from IxTypes.h */ - -#define IX_ETH_DB_PUBLIC PUBLIC - -/** - * @brief port ID => message handler NPE id conversion (0 => NPE_B, 1 => NPE_C) - */ -#define IX_ETH_DB_PORT_ID_TO_NPE(id) (id == 0 ? 1 : (id == 1 ? 2 : (id == 2 ? 0 : -1))) - -/** - * @def IX_ETH_DB_NPE_TO_PORT_ID(npe) - * @brief message handler NPE id => port ID conversion (NPE_B => 0, NPE_C => 1) - */ -#define IX_ETH_DB_NPE_TO_PORT_ID(npe) (npe == 0 ? 2 : (npe == 1 ? 0 : (npe == 2 ? 1 : -1))) - -/* temporary define - won't work for Azusa */ -#define IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(id) (IX_ETH_DB_PORT_ID_TO_NPE(id) << 4) -#define IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(id) (IX_ETH_DB_NPE_TO_PORT_ID(id >> 4)) - -/** - * @def IX_IEEE803_MAC_ADDRESS_SIZE - * @brief The size of the MAC address - */ -#define IX_IEEE803_MAC_ADDRESS_SIZE (6) - -/** - * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT - * @brief Number of QoS priorities defined by IEEE802.1Q - */ -#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8) - -/** - * @enum IxEthDBStatus - * @brief Ethernet Database API return values - */ -typedef enum /* IxEthDBStatus */ -{ - IX_ETH_DB_SUCCESS = IX_SUCCESS, /**< Success */ - IX_ETH_DB_FAIL = IX_FAIL, /**< Failure */ - IX_ETH_DB_INVALID_PORT, /**< Invalid port */ - IX_ETH_DB_PORT_UNINITIALIZED, /**< Port not initialized */ - IX_ETH_DB_MAC_UNINITIALIZED, /**< MAC not initialized */ - IX_ETH_DB_INVALID_ARG, /**< Invalid argument */ - IX_ETH_DB_NO_SUCH_ADDR, /**< Address not found for search or delete operations */ - IX_ETH_DB_NOMEM, /**< Learning database memory full */ - IX_ETH_DB_BUSY, /**< Learning database cannot complete operation, access temporarily blocked */ - IX_ETH_DB_END, /**< Database browser passed the end of the record set */ - IX_ETH_DB_INVALID_VLAN, /**< Invalid VLAN ID (valid range is 0..4094, 0 signifies no VLAN membership, used for priority tagged frames) */ - IX_ETH_DB_INVALID_PRIORITY, /**< Invalid QoS priority/traffic class (valid range for QoS priority is 0..7, valid range for traffic class depends on run-time configuration) */ - IX_ETH_DB_NO_PERMISSION, /**< No permission for attempted operation */ - IX_ETH_DB_FEATURE_UNAVAILABLE, /**< Feature not available (or not enabled) */ - IX_ETH_DB_INVALID_KEY, /**< Invalid search key */ - IX_ETH_DB_INVALID_RECORD_TYPE /**< Invalid record type */ -} IxEthDBStatus; - -/** @brief VLAN ID type, valid range is 0..4094, 0 signifying no VLAN membership */ -typedef UINT32 IxEthDBVlanId; - -/** @brief 802.1Q VLAN tag, contains 3 bits user priority, 1 bit CFI, 12 bits VLAN ID */ -typedef UINT32 IxEthDBVlanTag; - -/** @brief QoS priority/traffic class type, valid range is 0..7, 0 being the lowest */ -typedef UINT32 IxEthDBPriority; - -/** @brief Priority mapping table; 0..7 QoS priorities used to index, table contains traffic classes */ -typedef UINT8 IxEthDBPriorityTable[8]; - -/** @brief A 4096 bit array used to map the complete VLAN ID range */ -typedef UINT8 IxEthDBVlanSet[512]; - -#define IX_ETH_DB_802_1Q_VLAN_MASK (0xFFF) -#define IX_ETH_DB_802_1Q_QOS_MASK (0x7) - -#define IX_ETH_DB_802_1Q_MAX_VLAN_ID (0xFFE) - -/** - * @def IX_ETH_DB_SET_VLAN_ID - * @brief returns the given 802.1Q tag with the VLAN ID field substituted with the given VLAN ID - * - * This macro is used to change the VLAN ID in a 802.1Q tag. - * - * Example: - * - * tag = IX_ETH_DB_SET_VLAN_ID(tag, 32) - * - * inserts the VLAN ID "32" in the given tag. - */ -#define IX_ETH_DB_SET_VLAN_ID(vlanTag, vlanID) (((vlanTag) & 0xF000) | ((vlanID) & IX_ETH_DB_802_1Q_VLAN_MASK)) - -/** -* @def IX_ETH_DB_GET_VLAN_ID -* @brief returns the VLAN ID from the given 802.1Q tag -*/ -#define IX_ETH_DB_GET_VLAN_ID(vlanTag) ((vlanTag) & IX_ETH_DB_802_1Q_VLAN_MASK) - -#define IX_ETH_DB_GET_QOS_PRIORITY(vlanTag) (((vlanTag) >> 13) & IX_ETH_DB_802_1Q_QOS_MASK) - -#define IX_ETH_DB_SET_QOS_PRIORITY(vlanTag, priority) (((vlanTag) & 0x1FFF) | (((priority) & IX_ETH_DB_802_1Q_QOS_MASK) << 13)) - -#define IX_ETH_DB_CHECK_VLAN_TAG(vlanTag) { if(((vlanTag & 0xFFFF0000) != 0) || (IX_ETH_DB_GET_VLAN_ID(vlanTag) > 4094)) return IX_ETH_DB_INVALID_VLAN; } - -#define IX_ETH_DB_CHECK_VLAN_ID(vlanId) { if (vlanId > IX_ETH_DB_802_1Q_MAX_VLAN_ID) return IX_ETH_DB_INVALID_VLAN; } - -#define IX_IEEE802_1Q_VLAN_TPID (0x8100) - -typedef enum -{ - IX_ETH_DB_UNTAGGED_FRAMES = 0x1, /**< Accepts untagged frames */ - IX_ETH_DB_VLAN_TAGGED_FRAMES = 0x2, /**< Accepts tagged frames */ - IX_ETH_DB_PRIORITY_TAGGED_FRAMES = 0x4, /**< Accepts tagged frames with VLAN ID set to 0 (no VLAN membership) */ - IX_ETH_DB_ACCEPT_ALL_FRAMES = - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES /**< Accepts all the frames */ -} IxEthDBFrameFilter; - -typedef enum -{ - IX_ETH_DB_PASS_THROUGH = 0x1, /**< Leave frame as-is */ - IX_ETH_DB_ADD_TAG = 0x2, /**< Add default port VLAN tag */ - IX_ETH_DB_REMOVE_TAG = 0x3 /**< Remove VLAN tag from frame */ -} IxEthDBTaggingAction; - -typedef enum -{ - IX_ETH_DB_FIREWALL_WHITE_LIST = 0x1, /**< Firewall operates in white-list mode (MAC address based admission) */ - IX_ETH_DB_FIREWALL_BLACK_LIST = 0x2 /**< Firewall operates in black-list mode (MAC address based blocking) */ -} IxEthDBFirewallMode; - -typedef enum -{ - IX_ETH_DB_FILTERING_RECORD = 0x01, /**< - *
Filtering record
MAC address static/dynamic type age - *
- */ - IX_ETH_DB_FILTERING_VLAN_RECORD = 0x02, /**< - *
VLAN-enabled filtering record
MAC address static/dynamic type age 802.1Q tag - *
- */ - IX_ETH_DB_WIFI_RECORD = 0x04, /**< - *
WiFi header conversion record
MAC address optional gateway MAC address - *
- */ - IX_ETH_DB_FIREWALL_RECORD = 0x08, /**< - *
Firewall record
MAC address - *
- */ - IX_ETH_DB_GATEWAY_RECORD = 0x10, /**< For internal use only */ - IX_ETH_DB_MAX_RECORD_TYPE_INDEX = 0x10, /**< For internal use only */ - IX_ETH_DB_NO_RECORD_TYPE = 0, /**< None of the registered record types */ - IX_ETH_DB_ALL_FILTERING_RECORDS = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD, /**< All the filtering records */ - IX_ETH_DB_ALL_RECORD_TYPES = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | - IX_ETH_DB_WIFI_RECORD | IX_ETH_DB_FIREWALL_RECORD /**< All the record types registered within EthDB */ -} IxEthDBRecordType; - -typedef enum -{ - IX_ETH_DB_LEARNING = 0x01, /**< Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records */ - IX_ETH_DB_FILTERING = 0x02, /**< Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature */ - IX_ETH_DB_VLAN_QOS = 0x04, /**< VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes */ - IX_ETH_DB_FIREWALL = 0x08, /**< Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists */ - IX_ETH_DB_SPANNING_TREE_PROTOCOL = 0x10, /**< Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes */ - IX_ETH_DB_WIFI_HEADER_CONVERSION = 0x20 /**< WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data */ -} IxEthDBFeature; - -typedef UINT32 IxEthDBProperty; /**< Property ID type */ - -typedef enum -{ - IX_ETH_DB_INTEGER_PROPERTY = 0x1, /**< 4 byte unsigned integer type */ - IX_ETH_DB_STRING_PROPERTY = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */ - IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */ - IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only true and false values */ -} IxEthDBPropertyType; - -/* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY (0x01) /**< Property identifying number the supported number of traffic classes */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY (0x10) /**< Rx queue assigned to traffic class 0 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY (0x11) /**< Rx queue assigned to traffic class 1 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY (0x12) /**< Rx queue assigned to traffic class 2 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY (0x13) /**< Rx queue assigned to traffic class 3 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY (0x14) /**< Rx queue assigned to traffic class 4 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY (0x15) /**< Rx queue assigned to traffic class 5 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY (0x16) /**< Rx queue assigned to traffic class 6 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY (0x17) /**< Rx queue assigned to traffic class 7 */ - -/* private property used by EthAcc to indicate queue configuration complete */ -#define IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (0x18) - -/** - * - * @brief The IEEE 802.3 Ethernet MAC address structure. - * - * The data should be packed with bytes xx:xx:xx:xx:xx:xx - * - * @note The data must be packed in network byte order. - */ -typedef struct -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; -} IxEthDBMacAddr; - -/** - * @ingroup IxEthDB - * - * @brief Definition of an IXP400 port. - */ -typedef UINT32 IxEthDBPortId; - -/** - * @ingroup IxEthDB - * - * @brief Port dependency map definition - */ -typedef UINT8 IxEthDBPortMap[32]; - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBInit(void) - * - * @brief Initializes the Ethernet learning/filtering database - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored, returning IX_ETH_DB_SUCCESS - * - * @retval IX_ETH_DB_SUCCESS initialization was successful - * @retval IX_ETH_DB_FAIL initialization failed (OS error) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBInit(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUnload(void) - * - * @brief Stops and prepares the EthDB component for unloading. - * - * @retval IX_ETH_DB_SUCCESS de-initialization was successful - * @retval IX_ETH_DB_BUSY de-initialization failed, ports must be disabled first - * @retval IX_ETH_DB_FAIL de-initialization failed (OS error) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUnload(void); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBPortInit(IxEthDBPortId portID) - * - * @brief Initializes a port - * - * This function is called automatically by the Ethernet Access - * ixEthAccPortInit() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the two Ethernet NPEs). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to be initialized - * - * @see IxEthDBPortDefs.h for port definitions - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored - */ -IX_ETH_DB_PUBLIC -void ixEthDBPortInit(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) - * - * @brief Enables a port - * - * This function is called automatically from the Ethernet Access component - * ixEthAccPortEnable() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the Ethernet NPEs). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable processing on - * - * @retval IX_ETH_DB_SUCCESS if enabling is successful - * @retval IX_ETH_DB_FAIL if the enabling was not successful due to - * a message handler error - * @retval IX_ETH_DB_MAC_UNINITIALIZED the MAC address of this port was - * not initialized (only for Ethernet NPEs) - * @retval IX_ETH_DB_INVALID_PORT if portID is invalid - * - * @pre ixEthDBPortAddressSet needs to be called prior to enabling the port events - * for Ethernet NPEs - * - * @see ixEthDBPortAddressSet - * - * @see IxEthDBPortDefs.h for port definitions - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) - * - * @brief Disables processing on a port - * - * This function is called automatically from the Ethernet Access component - * ixEthAccPortDisable() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the Ethernet NPEs). - * - * @note Calling ixEthAccPortDisable() will disable the respective Ethernet NPE. - * After Ethernet NPEs are disabled they are stopped therefore - * when re-enabled they need to be reset, downloaded with microcode and started. - * For learning to restart working the user needs to call again - * ixEthAccPortUnicastMacAddressSet or ixEthDBUnicastAddressSet - * with the respective port MAC address. - * Residual MAC addresses learnt before the port was disabled are deleted as soon - * as the port is disabled. This only applies to dynamic (learnt) entries, static - * entries do not dissapear when the port is disabled. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to disable processing on - * - * @retval IX_ETH_DB_SUCCESS if disabling is successful - * @retval IX_ETH_DB_FAIL if the disabling was not successful due to - * a message handler error - * @retval IX_ETH_DB_INVALID_PORT if portID is invalid - * - * @note calling this function multiple times after the first time completed successfully - * does not constitute an error; redundant calls will be ignored and return IX_ETH_DB_SUCCESS -*/ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Sets the port MAC address - * - * This function is to be called from the Ethernet Access component top-level - * ixEthDBUnicastAddressSet(). Event processing cannot be enabled for a port - * until its MAC address has been set. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose MAC address is set - * @param macAddr @ref IxEthDBMacAddr [in] - port MAC address - * - * @retval IX_ETH_DB_SUCCESS MAC address was set successfully - * @retval IX_ETH_DB_FAIL MAC address was not set due to a message handler failure - * @retval IX_ETH_DB_INVALID_PORT if the port is not an Ethernet NPE - * - * @see IxEthDBPortDefs.h for port definitions - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize) - * - * @brief Set the maximum frame size supported on the given port ID - * - * This functions set the maximum frame size supported on a specific port ID - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to configure - * @param maximumFrameSize UINT32 [in] - maximum frame size to configure - * - * @retval IX_ETH_DB_SUCCESS the port is configured - * @retval IX_ETH_DB_PORT_UNINITIALIZED the port has not been initialized - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_INVALID_ARG size parameter is out of range - * @retval IX_ETH_DB_NO_PERMISSION selected port is not an Ethernet NPE - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note - * This maximum frame size is used to filter the frames based on their - * destination addresses and the capabilities of the destination port. - * The mximum value that can be set for a NPE port is 16320. - * (IX_ETHNPE_ACC_FRAME_LENGTH_MAX) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Populate the Ethernet learning/filtering database with a static MAC address - * - * Populates the Ethernet learning/filtering database with a static MAC address. The entry will not be subject to aging. - * If there is an entry (static or dynamic) with the corresponding MAC address on any port this entry will take precedence. - * Any other entry with the same MAC address will be removed. - * - * - Reentrant - yes - * - ISR Callable - yes - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the static address to - * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add - * - * @retval IX_ETH_DB_SUCCESS the add was successful - * @retval IX_ETH_DB_FAIL failed to populate the database entry - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Populate the Ethernet learning/filtering database with a dynamic MAC address - * - * Populates the Ethernet learning/filtering database with a dynamic MAC address. This entry will be subject to normal - * aging function, if aging is enabled on its port. - * If there is an entry (static or dynamic) with the same MAC address on any port this entry will take precedence. - * Any other entry with the same MAC address will be removed. - * - * - Reentrant - yes - * - ISR Callable - yes - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the dynamic address to - * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add - * - * @retval IX_ETH_DB_SUCCESS the add was successful - * @retval IX_ETH_DB_FAIL failed to populate the database entry - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr) - * - * @brief Removes a MAC address entry from the Ethernet learning/filtering database - * - * @param macAddr IxEthDBMacAddr [in] - MAC address to remove - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS the removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR failed to remove the address (not in the database) - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the Ethernet learning/filtering database for the given MAC address and port ID - * - * This functions searches the database for a specific port ID and MAC address. Both the port ID - * and the MAC address have to match in order for the record to be reported as found. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to search for - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for - * - * @retval IX_ETH_DB_SUCCESS the record exists in the database - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the Ethernet learning/filtering database for a MAC address and return the port ID - * - * Searches the database for a MAC address. The function returns the portID for the - * MAC address record, if found. If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. - * The portID is only valid if the function finds a match. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID the address belongs to (populated only on a successful search) - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for - * - * @retval IX_ETH_DB_SUCCESS the record exists in the database - * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the filtering database for a MAC address, return the port ID and reset the record age - * - * Searches the database for a MAC address. The function returns the portID for the - * MAC address record and resets the entry age to 0, if found. - * If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. - * The portID is only valid if the function finds a match. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS the MAC address was found - * @retval IX_ETH_DB_NO_SUCH_ADDR the MAC address was not found - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @def IX_ETH_DB_MAINTENANCE_TIME - * - * @brief The @ref ixEthDBDatabaseMaintenance must be called by the user at a frequency of - * IX_ETH_DB_MAINTENANCE_TIME - * - */ -#define IX_ETH_DB_MAINTENANCE_TIME (1 * 60) /* 1 Minute */ - -/** - * @ingroup IxEthDB - * - * @def IX_ETH_DB_LEARNING_ENTRY_AGE_TIME - * - * @brief The define specifies the filtering database age entry time. Static entries older than - * IX_ETH_DB_LEARNING_ENTRY_AGE_TIME +/- IX_ETH_DB_MAINTENANCE_TIME shall be removed. - * - */ -#define IX_ETH_DB_LEARNING_ENTRY_AGE_TIME (15 * 60 ) /* 15 Mins */ - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID) - * - * @brief Disable the aging function for a specific port - * - * @param portID @ref IxEthDBPortId [in] - port ID to disable aging on - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS aging disabled successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID) - * - * @brief Enable the aging function for a specific port - * - * Enables the aging of dynamic MAC address entries stored in the learning/filtering database - * - * @note The aging function relies on the @ref ixEthDBDatabaseMaintenance being called with a period of - * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to enable aging on - * - * @retval IX_ETH_DB_SUCCESS aging enabled successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBDatabaseMaintenance(void) - * - * @brief Performs a maintenance operation on the Ethernet learning/filtering database - * - * In order to perform a database maintenance this function must be called every - * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. It should be called regardless of whether learning is - * enabled or not. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note this function call will be ignored if the learning feature is disabled - */ -IX_ETH_DB_PUBLIC -void ixEthDBDatabaseMaintenance(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID) - * - * @brief This function displays the Mac Ethernet MAC address filtering tables. - * - * It displays the MAC address, port ID, entry type (dynamic/static),and age for - * the given port ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to display the MAC address entries - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FAIL record browser failed due to an internal busy or lock condition - * - * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead - * - * @see ixEthDBFilteringDatabaseShowRecords - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBFilteringDatabaseShowAll(void) - * - * @brief Displays the MAC address recorded in the filtering database for all registered - * ports (see IxEthDBPortDefs.h), grouped by port ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval void - * - * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead - * - * @see ixEthDBFilteringDatabaseShowRecords - */ -IX_ETH_DB_PUBLIC -void ixEthDBFilteringDatabaseShowAll(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter) - * - * @brief This function displays per port database records, given a record type filter - * - * The supported record type filters are: - * - * - IX_ETH_DB_FILTERING_RECORD - displays the non-VLAN filtering records (MAC address, age, static/dynamic) - * - IX_ETH_DB_FILTERING_VLAN_RECORD - displays the VLAN filtering records (MAC address, age, static/dynamic, VLAN ID, CFI, QoS class) - * - IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD - displays the previous two types of records - * - IX_ETH_DB_WIFI_RECORD - displays the WiFi header conversion records (MAC address, optional gateway MAC address) and WiFi header conversion parameters (BBSID, Duration/ID) - * - IX_ETH_DB_FIREWALL_RECORD - displays the firewall MAC address table and firewall operating mode (white list/black list) - * - IX_ETH_DB_ALL_RECORD_TYPES - displays all the record types - * - IX_ETH_DB_NO_RECORD_TYPE - displays only the port status (no records are displayed) - * - * Additionally, the status of each port will be displayed, containg the following information: type, capabilities, enabled status, - * aging enabled status, group membership and maximum frame size. - * - * The port ID can either be an actual port or IX_ETH_DB_ALL_PORTS, in which case the requested information - * will be displayed for all the ports (grouped by port) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID ID of the port to display information on (use IX_ETH_DB_ALL_PORTS for all the ports) - * @param recordFilter record type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) - * - * @brief Sets the dependency port map for a port - * - * @param portID ID of the port to set the dependency map to - * @param dependencyPortMap new dependency map (as bitmap, each bit set indicates a port being included) - * - * This function is used to share filtering information between ports. - * By adding a port into another port's dependency map the target port - * filtering data will import the filtering data from the port it depends on. - * Any changes to filtering data for a port - such as adding, updating or removing records - - * will trigger updates in the filtering information for all the ports depending on - * on the updated port. - * - * For example, if ports 2 and 3 are set in the port 0 dependency map the filtering - * information for port 0 will also include the filtering information from ports 2 and 3. - * Adding a record to port 2 will also trigger an update not only on port 2 but also on - * port 0. - * - * The dependency map is a 256 bit array where each bit corresponds to a port corresponding to the - * bit offset (bit 0 - port 0, bit 1 - port 1 etc). Setting a bit to 1 indicates that the corresponding - * port is the port map. For example, a dependency port map of 0x14 consists in the ports with IDs 2 and 4. - * Note that the last bit (offset 255) is reserved and should never be set (it will be automatically - * cleared by the function). - * - * By default, each port has a dependency port map consisting only of itself, i.e. - * - * @verbatim - IxEthDBPortMap portMap; - - // clear all ports from port map - memset(portMap, 0, sizeof (portMap)); - - // include portID in port map - portMap[portID / 8] = 1 << (portID % 8); - @endverbatim - * - * - Reentrant - no - * - ISR Callable - no - * - * @note Setting dependency maps is useful for NPE ports, which benefit from automatic updates - * of filtering information. Setting dependency maps for user-defined ports is not an error - * but will have no actual effect. - * - * @note Including a port in its own dependency map is not compulsory, however note that - * in this case updating the port will not trigger an update on the port itself, which - * might not be the intended behavior - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid dependencyPortMap pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) - * - * @brief Retrieves the dependency port map for a port - * - * @param portID ID of the port to set the dependency map to - * @param dependencyPortMap location where the port dependency map is to be copied - * - * This function will copy the port dependency map to a user specified location. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid dependencyPortMap pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag) - * - * @brief Sets the default 802.1Q VLAN tag for a given port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the default VLAN tag to - * @param vlanTag @ref IxEthDBVlanTag [in] - default 802.1Q VLAN tag - * - * The tag format has 16 bits and it is defined in the IEEE802.1Q specification. - * This tag will be used for tagging untagged frames (if enabled) and classifying - * unexpedited traffic into an internal traffic class (using the user priority field). - * - * - *
802.1Q tag format
3 bits 1 bit 12 bits - *
user priority CFI VID - *
- * - * User Priority : Defines user priority, giving eight (2^3) priority levels. IEEE 802.1P defines - * the operation for these 3 user priority bits - * - * CFI : Canonical Format Indicator is always set to zero for Ethernet switches. CFI is used for - * compatibility reason between Ethernet type network and Token Ring type network. If a frame received - * at an Ethernet port has a CFI set to 1, then that frame should not be forwarded as it is to an untagged port. - * - * VID : VLAN ID is the identification of the VLAN, which is basically used by the standard 802.1Q. - * It has 12 bits and allow the id entification of 4096 (2^12) VLANs. Of the 4096 possible VIDs, a VID of 0 - * is used to identify priority frames and value 4095 (FFF) is reserved, so the maximum possible VLAN - * configurations are 4,094. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_INVALID_VLAN vlanTag argument does not parse to a valid 802.1Q VLAN tag - * - * @note a VLAN ID value of 0 indicates that the port is not part of any VLAN - * @note the value of the cannonical frame indicator (CFI) field is ignored, the - * field being used only in frame tagging operations - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag) - * - * @brief Retrieves the default 802.1Q port VLAN tag for a given port (see also @ref ixEthDBPortVlanTagSet) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the default VLAN tag from - * @param vlanTag @ref IxEthDBVlanTag [out] - location to write the default port 802.1Q VLAN tag to - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanTag pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag) - * - * @brief Sets the 802.1Q VLAN tag for a database record - * - * @param macAddr MAC address - * @param vlanTag 802.1Q VLAN tag - * - * This function is used together with @ref ixEthDBVlanTagGet to provide MAC-based VLAN classification support. - * Please note that the bridging application must contain specific code to make use of this feature (see below). - * - * VLAN tags can be set only in IX_ETH_DB_FILTERING_RECORD or IX_ETH_DB_FILTERING_VLAN_RECORD type records. - * If to an IX_ETH_DB_FILTERING_RECORD type record is added a VLAN tag the record type is automatically - * changed to IX_ETH_DB_FILTERING_VLAN_RECORD. Once this has occurred the record type will never - * revert to a non-VLAN type (unless deleted and re-added). - * - * Record types used for different purposes (such as IX_ETH_DB_WIFI_RECORD) will be ignored by - * this function. - * - * After using this function to associate a VLAN ID with a MAC address the VLAN ID can be extracted knowing the - * MAC address using @ref ixEthDBVlanTagGet. This mechanism can be used to implement MAC-based VLAN classification - * if a bridging application searches for the VLAN tag when receiving a frame based on the source MAC address - * (contained in the ixp_ne_src_mac field of the buffer header). - * If found in the database, the application can instruct the NPE to tag the frame by writing the VLAN tag - * in the ixp_ne_vlan_tci field of the buffer header. This way the NPE will inspect the Egress tagging - * rule associated with the given VLAN ID on the Tx port and tag the frame if Egress tagging on the VLAN is - * allowed. Additionally, Egress tagging can be forced by setting the ixp_ne_tx_flags.tag_over and - * ixp_ne_tx_flags.tag_mode flags in the buffer header. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note this function will not add a filtering record, it can only be used to update an existing one - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer - * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found - * @retval IX_ETH_DB_INVALID_VLAN vlanTag argument does not parse to a valid 802.1Q VLAN tag - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag) - * - * @brief Retrieves the 802.1Q VLAN tag from a database record given the record MAC address - * - * @param macAddr MAC address - * @param vlanTag location to write the record 802.1Q VLAN tag to - * - * @note VLAN tags can be retrieved only from IX_ETH_DB_FILTERING_VLAN_RECORD type records - * - * This function is used together with ixEthDBVlanTagSet to provide MAC-based VLAN classification support. - * Please note that the bridging application must contain specific code to make use of this feature (see @ref ixEthDBVlanTagSet). - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or vlanTag pointer - * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID) - * - * @brief Adds a VLAN ID to a port's VLAN membership table - * - * Adding a VLAN ID to a port's VLAN membership table will cause frames tagged with the specified - * VLAN ID to be accepted by the frame filter, if Ingress VLAN membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to add the VLAN ID membership to - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be added to the port membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note A port's default VLAN ID is always in its own membership table, hence there - * is no need to explicitly add it using this function (although it is not an error - * to do so) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) - * - * @brief Adds a VLAN ID range to a port's VLAN membership table - * - * All the VLAN IDs in the specified range will be added to the port VLAN - * membership table, including the range start and end VLAN IDs. Tagged frames with - * VLAN IDs in the specified range will be accepted by the frame filter, if Ingress VLAN - * membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the VLAN membership range into - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case this - * function will behave as @ref ixEthDBPortVlanMembershipAdd - * - * @note A port's default VLAN ID is always in its own membership table, hence there is no need - * to explicitly add it using this function (although it is not an error to do so) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID) - * - * @brief Removes a VLAN ID from a port's VLAN membership table - * - * Frames tagged with a VLAN ID which is not in a port's VLAN membership table - * will be discarded by the frame filter, if Ingress membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN ID membership from - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be removed from the port membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID - * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID - * from the port membership table (vlanID was set to the default port VLAN ID) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note A port's default VLAN ID cannot be removed from the port's membership - * table; attempting it will return IX_ETH_DB_NO_PERMISSION - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) - * - * @brief Removes a VLAN ID range from a port's VLAN membership table - * - * All the VLAN IDs in the specified range will be removed from the port VLAN - * membership table, including the range start and end VLAN IDs. Tagged frames - * with VLAN IDs in the range will be discarded by the frame filter, if Ingress - * membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN membership range from - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range - * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID - * from the port membership table (both vlanIDMin and vlanIDMax were set to the default port VLAN ID) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case - * function will behave as @ref ixEthDBPortVlanMembershipRemove - * - * @note If the given range overlaps the default port VLAN ID this function - * will remove all the VLAN IDs in the range except for the port VLAN ID from its - * own membership table. This situation will be silently dealt with (no error message - * will be returned) as long as the range contains more than one value (i.e. at least - * one other value, apart from the default port VLAN ID). If the function is called - * with the vlanIDMin and vlanIDMax parameters both set to the port default VLAN ID, the - * function will infer that an attempt was specifically made to remove the default port - * VLAN ID from the port membership table, in which case the return value will be - * IX_ETH_DB_NO_PERMISSION. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Sets a port's VLAN membership table - * - * Sets a port's VLAN membership table from a complete VLAN table containing all the possible - * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit - * indicates whether the VLAN at that bit index is in the port's membership list (if set) or - * not (unset). - * - * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no - * other bit must be set if bit 0 is set. - * - * The bit at index 4095 is reserved and should never be set (it will be ignored if set). - * - * The bit referencing the same VLAN ID as the default port VLAN ID should always be set, as - * the membership list must contain at least the default port VLAN ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to set the VLAN membership table to - * @param vlanSet @ref IxEthDBVlanSet [in] - pointer to the VLAN membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Retrieves a port's VLAN membership table - * - * Retrieves the complete VLAN membership table from a port, containing all the possible - * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit - * indicates whether the VLAN at that bit index is in the port's membership list (if set) or - * not (unset). - * - * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no - * other bit will be set if bit 0 is set. - * - * The bit at index 4095 is reserved and will not be set (it will be ignored if set). - * - * The bit referencing the same VLAN ID as the default port VLAN ID will always be set, as - * the membership list must contain at least the default port VLAN ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the VLAN membership table from - * @param vlanSet @ref IxEthDBVlanSet [out] - pointer a location where the VLAN membership table will be - * written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter) - * - * @brief Sets a port's acceptable frame type filter - * - * The acceptable frame type is one (or a combination) of the following values: - * - IX_ETH_DB_ACCEPT_ALL_FRAMES - accepts all the frames - * - IX_ETH_DB_UNTAGGED_FRAMES - accepts untagged frames - * - IX_ETH_DB_VLAN_TAGGED_FRAMES - accepts tagged frames - * - IX_ETH_DB_PRIORITY_TAGGED_FRAMES - accepts tagged frames with VLAN ID set to 0 (no VLAN membership) - * - * Except for using the exact values given above only the following combinations are valid: - * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES - * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_PRIORITY_TAGGED_FRAMES - * - * Please note that IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES is equivalent - * to IX_ETH_DB_ACCEPT_ALL_FRAMES. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note by default the acceptable frame type filter is set to IX_ETH_DB_ACCEPT_ALL_FRAMES - * - * @note setting the acceptable frame type to PRIORITY_TAGGED_FRAMES is internally - * accomplished by changing the frame filter to VLAN_TAGGED_FRAMES and setting the - * VLAN membership list to include only VLAN ID 0; the membership list will need - * to be restored manually to an appropriate value if the acceptable frame type - * filter is changed back to ACCEPT_ALL_FRAMES or VLAN_TAGGED_FRAMES; failure to do so - * will filter all VLAN traffic bar frames tagged with VLAN ID 0 - * - * @param portID @ref IxEthDBPortId [in] - port ID to set the acceptable frame type filter to - * @param frameFilter @ref IxEthDBFrameFilter [in] - acceptable frame type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid frame type filter - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter) - * - * @brief Retrieves a port's acceptable frame type filter - * - * For a description of the acceptable frame types see @ref ixEthDBAcceptableFrameTypeSet - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the acceptable frame type filter from - * @param frameFilter @ref IxEthDBFrameFilter [out] - location to store the acceptable frame type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid frameFilter pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) - * - * @brief Sets a port's priority mapping table - * - * The priority mapping table is an 8x2 table mapping a QoS (user) priority into an internal - * traffic class. There are 8 valid QoS priorities (0..7, 0 being the lowest) which can be - * mapped into one of the 4 available traffic classes (0..3, 0 being the lowest). - * If a custom priority mapping table is not specified using this function the following - * default priority table will be used (as per IEEE 802.1Q and IEEE 802.1D): - * - * - *
QoS traffic classes
QoS priority Default traffic class Traffic type - *
0 1 Best effort, default class for unexpedited traffic - *
1 0 Background traffic - *
2 0 Spare bandwidth - *
3 1 Excellent effort - *
4 2 Controlled load - *
5 2 Video traffic - *
6 3 Voice traffic - *
7 3 Network control - *
- * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID of the port to set the priority mapping table to - * @param priorityTable @ref IxEthDBPriorityTable [in] - location of the user priority table - * - * @note The provided table will be copied into internal data structures in EthDB and - * can be deallocated by the called after this function has completed its execution, if - * so desired - * - * @warning The number of available traffic classes differs depending on the NPE images - * and queue configuration. Check IxEthDBQoS.h for up-to-date information on the availability of - * traffic classes. Note that specifiying a traffic class in the priority map which exceeds - * the system availability will produce an IX_ETH_DB_INVALID_PRIORITY return error code and no - * priority will be remapped. - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer - * @retval IX_ETH_DB_INVALID_PRIORITY at least one priority value exceeds - * the current number of available traffic classes - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) - * - * @brief Retrieves a port's priority mapping table - * - * The priority mapping table for the given port will be copied in the location - * specified by the caller using "priorityTable" - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID ID @ref IxEthDBPortId [in] - of the port to retrieve the priority mapping table from - * @param priorityTable @ref IxEthDBPriorityTable [out] - pointer to a user specified location where the table will be copied to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass) - * - * @brief Sets one QoS/user priority => traffic class mapping in a port's priority mapping table - * - * This function establishes a mapping between a user (QoS) priority and an internal traffic class. - * The mapping will be saved in the port's priority mapping table. Use this function when not all - * the QoS priorities need remapping (see also @ref ixEthDBPriorityMappingTableSet) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to - * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest) - * @param trafficClass @ref IxEthDBPriority [in] - internal traffic class, between 0 and 3 (0 being the lowest) - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_PRIORITY userPriority out of range or - * trafficClass is beyond the number of currently available traffic classes - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass) - * - * @brief Retrieves one QoS/user priority => traffic class mapping in a port's priority mapping table - * - * This function retrieves the internal traffic class associated with a QoS (user) priority from a given - * port's priority mapping table. Use this function when not all the QoS priority mappings are - * required (see also @ref ixEthDBPriorityMappingTableGet) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to - * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest) - * @param trafficClass @ref IxEthDBPriority [out] - location to write the corresponding internal traffic class to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_PRIORITY invalid userPriority value (out of range) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_INVALID_ARG invalid trafficClass pointer argument - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled) - * - * @brief Enables or disables Egress VLAN tagging for a port and a given VLAN - * - * This function enables or disables Egress VLAN tagging for the given port and VLAN ID. - * If the VLAN tagging for a certain VLAN ID is enabled then all the frames to be - * transmitted on the given port tagged with the same VLAN ID will be transmitted in a tagged format. - * If tagging is not enabled for the given VLAN ID, the VLAN tag from the frames matching - * this VLAN ID will be removed (the frames will be untagged). - * - * VLAN ID 4095 is reserved and should never be used with this function. - * VLAN ID 0 has the special meaning of "No VLAN membership" and it is used in this - * context to allow the port to send priority-tagged frames or not. - * - * By default, no Egress VLAN tagging is enabled on any port. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames - * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN, and - * false to disable Egress VLAN tagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled) - * - * @brief Retrieves the Egress VLAN tagging enabling status for a port and VLAN ID - * - * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from - * @param vlanID VLAN [in] - ID whose tagging status is to be extracted - * @param enabled [in] - user-specifed location where the status is copied to; following - * the successfull execution of this function the value will be true if Egress VLAN - * tagging is enabled for the given port and VLAN ID, and false otherwise - * - * - Reentrant - no - * - ISR Callable - no - * - * @see ixEthDBEgressVlanEntryTaggingEnabledGet - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range) - * @retval IX_ETH_DB_INVALID_ARG invalid enabled argument pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled) - * - * @brief Enables or disables Egress VLAN tagging for a port and given VLAN range - * - * This function is very similar to @ref ixEthDBEgressVlanEntryTaggingEnabledSet with the - * difference that it can manipulate the Egress tagging status on multiple VLAN IDs, - * defined by a contiguous range. Note that both limits in the range are explicitly - * included in the execution of this function. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames - * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN range, - * and false to disable Egress VLAN tagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range), or do not constitute a range - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_NO_PERMISSION attempted to explicitly remove the default port VLAN ID from the tagging table - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Specifically removing the default port VLAN ID from the Egress tagging table by setting both vlanIDMin and vlanIDMax - * to the VLAN ID portion of the PVID is not allowed by this function and will return IX_ETH_DB_NO_PERMISSION. - * However, this can be circumvented, should the user specifically desire this, by either using a - * larger range (vlanIDMin < vlanIDMax) or by using ixEthDBEgressVlanEntryTaggingEnabledSet. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Sets the complete Egress VLAN tagging table for a port - * - * This function is used to set the VLAN tagging/untagging per VLAN ID for a given port - * covering the entire VLAN ID range (0..4094). The vlanSet parameter is a 4096 - * bit array, each bit indicating the Egress behavior for the corresponding VLAN ID. - * If a bit is set then outgoing frames with the corresponding VLAN ID will be transmitted - * with the VLAN tag, otherwise the frame will be transmitted without the VLAN tag. - * - * Bit 0 has a special significance, indicating tagging or tag removal for priority-tagged - * frames. - * - * Bit 4095 is reserved and should never be set (it will be ignored if set). - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is set - * @param vlanSet @ref IxEthDBVlanSet [in] - 4096 bit array controlling per-VLAN tagging and untagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @warning This function will automatically add the default port VLAN ID to the Egress tagging table - * every time it is called. The user should manually call ixEthDBEgressVlanEntryTaggingEnabledSet to - * prevent tagging on the default port VLAN ID if the default behavior is not intended. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Retrieves the complete Egress VLAN tagging table from a port - * - * This function copies the 4096 bit table controlling the Egress VLAN tagging into a user specified - * area. Each bit in the array indicates whether tagging for the corresponding VLAN (the bit position - * in the array) is enabled (the bit is set) or not (the bit is unset). - * - * Bit 4095 is reserved and should not be set (it will be ignored if set). - * - * @see ixEthDBEgressVlanTaggingEnabledSet - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is retrieved - * @param vlanSet @ref IxEthDBVlanSet [out] - user location to copy the Egress tagging table into; should have - * room to store 4096 bits (512 bytes) - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction) - * - * @brief Sets the Ingress VLAN tagging behavior for a port - * - * A port's Ingress tagging behavior is controlled by the taggingAction parameter, - * which can take one of the following values: - * - * - IX_ETH_DB_PASS_THROUGH - leaves the frame unchanged (does not add or remove the VLAN tag) - * - IX_ETH_DB_ADD_TAG - adds the VLAN tag if not present, using the default port VID - * - IX_ETH_DB_REMOVE_TAG - removes the VLAN tag if present - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set - * @param taggingAction @ref IxEthDBTaggingAction [in] - tagging behavior for the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid taggingAction argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction) - * - * @brief Retrieves the Ingress VLAN tagging behavior from a port (see @ref ixEthDBIngressVlanTaggingEnabledSet) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set - * @param taggingAction @ref IxEthDBTaggingAction [out] - location where the tagging behavior for the port is written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid taggingAction pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable) - * - * @brief Enables or disables port ID extraction - * - * This feature can be used in the situation when a multi-port device (e.g. a switch) - * is connected to an IXP4xx port and the device can provide incoming frame port - * identification by tagging the TPID field in the Ethernet frame. Enabling - * port extraction will instruct the NPE to copy the TPID field from the frame and - * place it in the ixp_ne_src_port of the ixp_buf header. In addition, - * the NPE restores the TPID field to 0. - * - * If the frame is not tagged the NPE will fill the ixp_ne_src_port with the - * port ID of the MII interface the frame was received from. - * - * The TPID field is the least significant byte of the type/length field, which is - * normally set to 0x8100 for 802.1Q-tagged frames. - * - * This feature is disabled by default. - * - * @param portID ID of the port to configure port ID extraction on - * @param enable true to enable port ID extraction and false to disable it - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet) - * - * @brief Retrieves the feature capability set for a port - * - * This function retrieves the feature capability set for a port or the common capabilities shared between all - * the ports, writing the feature capability set in a user specified location. - * - * The feature capability set will consist of a set formed by OR-ing one or more of the following values: - * - IX_ETH_DB_LEARNING - Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records - * - IX_ETH_DB_FILTERING - Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature - * - IX_ETH_DB_VLAN_QOS - VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes - * - IX_ETH_DB_FIREWALL - Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists - * - IX_ETH_DB_SPANNING_TREE_PROTOCOL - Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes - * - IX_ETH_DB_WIFI_HEADER_CONVERSION - WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data - * - * Note that EthDB provides only the LEARNING feature for non-NPE ports. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the capability set for - * (use IX_ETH_DB_ALL_PORTS to retrieve the common capabilities shared between all the ports) - * @param featureSet @ref IxEthDBFeature [out] - location where the capability set will be written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid featureSet pointer - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled) - * - * @brief Enables or disables one or more EthDB features - * - * Selects one or more features (see @ref ixEthDBFeatureCapabilityGet for a description of the supported - * features) to be enabled or disabled on the selected port (or all the ports). - * - * Note that some features are mutually incompatible: - * - IX_ETH_DB_FILTERING is incompatible with IX_ETH_DB_WIFI_HEADER_CONVERSION - * - * Also note that some features require other features to be enabled: - * - IX_ETH_DB_FILTERING requires IX_ETH_DB_LEARNING - * - * This function will either enable the entire selected feature set for the selected port (or all the ports), - * in which case it will return IX_ETH_DB_SUCCESS, or in case of error it will not enable any feature at all - * and return an appropriate error message. - * - * The following features are enabled by default (for ports with the respective capability), - * for compatibility reasons with previous versions of CSR: - * - IX_ETH_DB_LEARNING - * - IX_ETH_DB_FILTERING - * - * All other features are disabled by default and require manual enabling using ixEthDBFeatureEnable. - * - * Default settings for VLAN, QoS, Firewall and WiFi header conversion features: - * - * VLAN - * - * When the VLAN/QoS feature is enabled for a port for the first time the default VLAN behavior - * of the port is set to be as permissive (it will accept all the frames) and - * non-interferential (it will not change any frames) as possible: - * - the port VLAN ID (VID) is set to 0 - * - the Ingress acceptable frame filter is set to accept all frames - * - the VLAN port membership is set to the complete VLAN range (0 - 4094) - * - the Ingress tagging mode is set to pass-through (will not change frames) - * - the Egress tagging mode is to send tagged frames in the entire VLAN range (0 - 4094) - * - * Note that further disabling and re-enabling the VLAN feature for a given port will not reset the port VLAN behavior - * to the settings listed above. Any VLAN settings made by the user are kept. - * - * QoS - * - * The following default priority mapping table will be used (as per IEEE 802.1Q and IEEE 802.1D): - * - * - *
QoS traffic classes
QoS priority Default traffic class Traffic type - *
0 1 Best effort, default class for unexpedited traffic - *
1 0 Background traffic - *
2 0 Spare bandwidth - *
3 1 Excellent effort - *
4 2 Controlled load - *
5 2 Video traffic - *
6 3 Voice traffic - *
7 3 Network control - *
- * - * Firewall - * - * The port firewall is configured by default in black-list mode, and the firewall address table is empty. - * This means the firewall will not filter any frames until the feature is configured and the firewall table is - * downloaded to the NPE. - * - * Spanning Tree - * - * The port is set to STP unblocked mode, therefore it will accept all frames until re-configured. - * - * WiFi header conversion - * - * The WiFi header conversion database is empty, therefore no actual header conversion will take place until this - * feature is configured and the conversion table downloaded to the NPE. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports) - * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable - * @param enabled BOOL [in] - true to enable the feature and false to disable it - * - * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level; - * when such features are set to disabled using the EthDB API they will be configured in such - * a way to determine a behavior equivalent to the feature being disabled. As well as this, disabled - * features cannot be configured or accessed via the EthDB API (except for getting their status). - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_NO_PERMISSION attempted to enable mutually exclusive features, - * or a feature that depends on another feature which is not present or enabled - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE at least one of the features selected is unavailable - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled) - * - * @brief Retrieves the availability and status of a feature set - * - * This function returns the availability and status for a feature set. - * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING) - * the "present" and "enabled" return values will be set to true only if all the features in the - * feature set are present and enabled (not only some). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - identifier of the feature to retrieve the status for - * @param present BOOL [out] - location where a boolean flag indicating whether this feature is present will be written to - * @param enabled BOOL [out] - location where a boolean flag indicating whether this feature is enabled will be written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG either present or enabled pointer argument is invalid - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value) - * - * @brief Retrieves the value of a feature property - * - * The EthDB features usually contain feature-specific properties describing or - * controlling how the feature operates. While essential properties (e.g. the - * firewall operating mode) have their own API, secondary properties can be - * retrieved using this function. - * - * Properties can be read-only or read-write. ixEthDBFeaturePropertyGet operates with - * both types of features. - * - * Properties have types associated with them. A descriptor indicating the property - * type is returned in the type argument for convenience. - * - * The currently supported properties and their corresponding features are as follows: - * - * - *
Properties for IX_ETH_DB_VLAN_QOS
Property identifier Property type Property value Read-Only - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY IX_ETH_DB_INTEGER_PROPERTY number of internal traffic classes Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 0 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 1 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 2 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 3 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 4 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 5 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 6 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 7 Yes - *
- * - * @see ixEthDBFeaturePropertySet - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is retrieved - * @param property @ref IxEthDBProperty [in] - property identifier - * @param type @ref IxEthDBPropertyType [out] - location where the property type will be stored - * @param value void [out] - location where the property value will be stored - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, type or value pointer arguments - * @retval IX_ETH_DB_FAIL incorrect property value or unknown error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value) - * - * @brief Sets the value of a feature property - * - * Unlike @ref ixEthDBFeaturePropertyGet, this function operates only with read-write properties - * - * The currently supported properties and their corresponding features are as follows: - * - * - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (for IX_ETH_DB_VLAN_QOS): freezes the availability of traffic classes - * to the number of traffic classes currently in use - * - * Note that this function creates deep copies of the property values; once the function is invoked the client - * can free or reuse the memory area containing the original property value. - * - * Copy behavior for different property types is defined as follows: - * - * - IX_ETH_DB_INTEGER_PROPERTY - 4 bytes are copied from the source location - * - IX_ETH_DB_STRING_PROPERTY - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters - * - IX_ETH_DB_MAC_ADDR_PROPERTY - 6 bytes are copied from the source location - * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are true (1L) and false (0L) - * - * @see ixEthDBFeaturePropertySet - * - * @warning IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE is provided for EthAcc internal use; - * do not attempt to set this property directly - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is set - * @param property @ref IxEthDBProperty [in] - property identifier - * @param value void [in] - location where the property value is to be copied from - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, value pointer, or invalid property value - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType) - * - * @brief Deletes a set of record types from the Ethernet Database - * - * This function deletes all the records of certain types (specified in the recordType filter) - * associated with a port. Additionally, the IX_ETH_DB_ALL_PORTS value can be used as port ID - * to indicate that the specified record types should be deleted for all the ports. - * - * The record type filter can be an ORed combination of the following types: - * - * Record types - * - IX_ETH_DB_FILTERING_RECORD - * - *
Filtering record
MAC address static/dynamic type age
- * - * - IX_ETH_DB_FILTERING_VLAN_RECORD - * - *
VLAN-enabled filtering record
MAC address static/dynamic type age 802.1Q tag
- * - * - IX_ETH_DB_WIFI_RECORD - * - *
WiFi header conversion record
MAC address optional gateway MAC address
- * - * - IX_ETH_DB_FIREWALL_RECORD - * - *
Firewall record
MAC address
- * - IX_ETH_DB_ALL_RECORD_TYPES - * - * Any combination of the above types is valid e.g. - * - * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | IX_ETH_DB_FIREWALL_RECORD), - * - * although some might be redundant (it is not an error to do so) e.g. - * - * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_ALL_RECORD_TYPES) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param recordType @ref IxEthDBRecordType [in] - record type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid recordType filter - * - * @note If the record type filter contains any unrecognized value (hence the - * IX_ETH_DB_INVALID_ARG error value is returned) no actual records will be deleted. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Adds an "Access Point to Station" record to the database, for 802.3 => 802.11 frame - * header conversion - * - * Frame header conversion is controlled by the set of MAC addresses - * added using @ref ixEthDBWiFiStationEntryAdd and @ref ixEthDBWiFiAccessPointEntryAdd. - * Conversion arguments are added using @ref ixEthDBWiFiFrameControlSet, - * @ref ixEthDBWiFiDurationIDSet and @ref ixEthDBWiFiBBSIDSet. - * - * Note that adding the same MAC address twice will not return an error - * (but will not accomplish anything either), while re-adding a record previously added - * as an "Access Point to Access Point" will migrate the record to the "Access Point - * to Station" type. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) - * - * @brief Adds an "Access Point to Access Point" record to the database - * - * @see ixEthDBWiFiStationEntryAdd - * - * Note that adding the same MAC address twice will simply overwrite the previously - * defined gateway MAC address value in the same record, if the record was previously of the - * "Access Point to Access Point" type. - * - * Re-adding a MAC address as "Access Point to Access Point", which was previously added as - * "Access Point to Station" will migrate the record type to "Access Point to Access Point" and - * record the gateway MAC address. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add - * @param gatewayMacAddr @ref IxEthDBMacAddr [in] - MAC address of the gateway Access Point - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or gatewayMacAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Removes a WiFi station record - * - * This function removes both types of WiFi records ("Access Point to Station" and - * "Access Point to Access Point"). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to remove - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR specified address was not found in the database - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID) - * - * @brief Downloads the MAC address table for 802.3 => 802.11 frame header - * conversion to the NPE - * - * Note that the frame conversion MAC address table must be individually downloaded - * to each NPE for which the frame header conversion feature is enabled (i.e. it - * is not possible to specify IX_ETH_DB_ALL_PORTS). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl) - * - * @brief Sets the GlobalFrameControl field - * - * The GlobalFrameControl field is a 2-byte value inserted in the Frame Control - * field for all 802.3 to 802.11 frame header conversions - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param frameControl UINT16 [in] - GlobalFrameControl value - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID) - * - * @brief Sets the GlobalDurationID field - * - * The GlobalDurationID field is a 2-byte value inserted in the Duration/ID - * field for all 802.3 to 802.11 frame header conversions - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param durationID UINT16 [in] - GlobalDurationID field - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid) - * - * @brief Sets the BBSID field - * - * The BBSID field is a 6-byte value which - * identifies the infrastructure of the service set managed - * by the Access Point having the IXP400 as its processor. The value - * is written in the BBSID field of the 802.11 frame header. - * The BBSID value is the MAC address of the Access Point. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param bbsid @ref IxEthDBMacAddr [in] - pointer to 6 bytes containing the BSSID - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid bbsid pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked) - * - * @brief Sets the STP blocked/unblocked state for a port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL [in] - true to set the port as STP blocked, false to set it as unblocked - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked) - * - * @brief Retrieves the STP blocked/unblocked state for a port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL * [in] - set to true if the port is STP blocked, false otherwise - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid blocked pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode) - * - * @brief Sets the firewall mode to use white or black listing - * - * When enabled, the NPE MAC address based firewall support operates in two modes: - * - * - white-list mode (MAC address based admission) - * - mode set to IX_ETH_DB_FIREWALL_WHITE_LIST - * - only packets originating from MAC addresses contained in the firewall address list - * are allowed on the Rx path - * - black-list mode (MAC address based blocking) - * - mode set to IX_ETH_DB_FIREWALL_BLACK_LIST - * - packets originating from MAC addresses contained in the firewall address list - * are discarded - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param mode @ref IxEthDBFirewallMode [in] - firewall mode (IX_ETH_DB_FIREWALL_WHITE_LIST or IX_ETH_DB_FIREWALL_BLACK_LIST) - * - * @note by default the firewall operates in black-list mode with an empty address - * list, hence it doesn't filter any packets - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_INVALID_ARGUMENT mode argument is not a valid firewall configuration mode - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error -*/ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode); - -/** - * @ingroup IxEthDB - * - * @fn ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable) - * - * @brief Enables or disables invalid MAC address filtering - * - * According to IEEE802 it is illegal for a source address to be a multicast - * or broadcast address. If this feature is enabled the NPE inspects the source - * MAC addresses of incoming frames and discards them if invalid addresses are - * detected. - * - * By default this service is enabled, if the firewall feature is supported by the - * NPE image. - * - * @param portID ID of the port - * @param enable true to enable invalid MAC address filtering and false to disable it - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Adds a MAC address to the firewall address list - * - * Note that adding the same MAC address twice will not return an error - * but will not actually accomplish anything. - * - * The firewall MAC address list has a limited number of entries; once - * the maximum number of entries has been reached this function will failed - * to add more addresses, returning IX_ETH_DB_NOMEM. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be added - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Removes a MAC address from the firewall address list - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be removed - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR address not found - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID) - * - * @brief Downloads the MAC firewall table to a port - * - * @param portID ID of the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field) - * - * @brief Adds a user-defined field to a database record - * - * This function associates a user-defined field to a database record. - * The user-defined field is passed as a (void *) parameter, hence it can be used - * for any purpose (such as identifying a structure). Retrieving the user-defined field from - * a record is done using @ref ixEthDBUserFieldGet. Note that EthDB never uses the user-defined - * field for any internal operation and it is not aware of the significance of its contents. The - * field is only stored as a pointer. - * - * The database record is identified using a combination of the given parameters, depending on the record type. - * All the record types require the record MAC address. - * - * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address - * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID - * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID - * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID - * - * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking). - * The user-defined field can be cleared using a NULL field parameter. - * - * @param recordType @ref IxEthDBRecordType [in] - type of record (can be IX_ETH_DB_FILTERING_RECORD, - * IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD or IX_ETH_DB_FIREWALL_RECORD) - * @param portID @ref IxEthDBPortId [in] - ID of the port (required only for WIFI and FIREWALL records) - * @param macAddr @ref IxEthDBMacAddr * [in] - MAC address of the record - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID of the record (required only for FILTERING_VLAN records) - * @param field void * [in] - user defined field - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR record not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field) - * - * @brief Retrieves a user-defined field from a database record - * - * The database record is identified using a combination of the given parameters, depending on the record type. - * All the record types require the record MAC address. - * - * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address - * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID - * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID - * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID - * - * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking). - * - * If no user-defined field was registered with the specified record then NULL will be written - * at the location specified by field. - * - * @param recordType type of record (can be IX_ETH_DB_FILTERING_RECORD, IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD - * or IX_ETH_DB_FIREWALL_RECORD) - * @param portID ID of the port (required only for WIFI and FIREWALL records) - * @param macAddr MAC address of the record - * @param vlanID VLAN ID of the record (required only for FILTERING_VLAN records) - * @param field location to write the user defined field into - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or field pointer arguments - * @retval IX_ETH_DB_NO_SUCH_ADDR record not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portId, IxEthDBVlanId vlanID, void **field); - -/** - * @} - */ - -#endif /* IxEthDB_H */ diff --git a/drivers/net/npe/include/IxEthDBLocks_p.h b/drivers/net/npe/include/IxEthDBLocks_p.h deleted file mode 100644 index 1d8b24fdf6..0000000000 --- a/drivers/net/npe/include/IxEthDBLocks_p.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - * @file IxEthAccDBLocks_p.h - * - * @brief Definition of transaction lock stacks and lock utility macros - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthAccDBLocks_p_H -#define IxEthAccDBLocks_p_H - -#include "IxOsPrintf.h" - -/* Lock and lock stacks */ -typedef struct -{ - IxOsalFastMutex* locks[MAX_LOCKS]; - UINT32 stackPointer, basePointer; -} LockStack; - -#define TRY_LOCK(mutex) \ - { \ - if (ixOsalFastMutexTryLock(mutex) != IX_SUCCESS) \ - { \ - return IX_ETH_DB_BUSY; \ - } \ - } - - -#define UNLOCK(mutex) { ixOsalFastMutexUnlock(mutex); } - -#define INIT_STACK(stack) \ - { \ - (stack)->basePointer = 0; \ - (stack)->stackPointer = 0; \ - } - -#define PUSH_LOCK(stack, lock) \ - { \ - if ((stack)->stackPointer == MAX_LOCKS) \ - { \ - ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on push, heavy chaining?\n"); \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_NOMEM; \ - } \ - \ - if (ixOsalFastMutexTryLock(lock) == IX_SUCCESS) \ - { \ - (stack)->locks[(stack)->stackPointer++] = (lock); \ - } \ - else \ - { \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_BUSY; \ - } \ - } - -#define POP_LOCK(stack) \ - { \ - ixOsalFastMutexUnlock((stack)->locks[--(stack)->stackPointer]); \ - } - -#define UNROLL_STACK(stack) \ - { \ - while ((stack)->stackPointer > (stack)->basePointer) \ - { \ - POP_LOCK(stack); \ - } \ - } - -#define SHIFT_STACK(stack) \ - { \ - if ((stack)->basePointer == MAX_LOCKS - 1) \ - { \ - ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on shift, heavy chaining?\n"); \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_BUSY; \ - } \ - \ - ixOsalFastMutexUnlock((stack)->locks[(stack)->basePointer++]); \ - } - -#endif /* IxEthAccDBLocks_p_H */ diff --git a/drivers/net/npe/include/IxEthDBLog_p.h b/drivers/net/npe/include/IxEthDBLog_p.h deleted file mode 100644 index 1d6b0bb20d..0000000000 --- a/drivers/net/npe/include/IxEthDBLog_p.h +++ /dev/null @@ -1,227 +0,0 @@ -/** - * @file IxEthDBLog_p.h - * - * @brief definitions of log macros and log configuration - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#include - -#ifdef IX_UNIT_TEST -#define NULL_PRINT_ROUTINE(format, arg...) /* nothing */ -#else -#define NULL_PRINT_ROUTINE if(0) printf -#endif - -/*************************************************** - * Globals * - ***************************************************/ -/* safe to permanently leave these on */ -#define HAS_ERROR_LOG -#define HAS_ERROR_IRQ_LOG -#define HAS_WARNING_LOG - -/*************************************************** - * Log Configuration * - ***************************************************/ - -/* debug output can be turned on unless specifically - declared as a non-debug build */ -#ifndef NDEBUG - -#undef HAS_EVENTS_TRACE -#undef HAS_EVENTS_VERBOSE_TRACE - -#undef HAS_SUPPORT_TRACE -#undef HAS_SUPPORT_VERBOSE_TRACE - -#undef HAS_NPE_TRACE -#undef HAS_NPE_VERBOSE_TRACE -#undef HAS_DUMP_NPE_TREE - -#undef HAS_UPDATE_TRACE -#undef HAS_UPDATE_VERBOSE_TRACE - -#endif /* NDEBUG */ - - -/*************************************************** - * Log Macros * - ***************************************************/ - -/************** Globals ******************/ - -#ifdef HAS_ERROR_LOG - - #define ERROR_LOG printf - -#else - - #define ERROR_LOG NULL_PRINT_ROUTINE - -#endif - -#ifdef HAS_ERROR_IRQ_LOG - - #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - -#else - - #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif - -#ifdef HAS_WARNING_LOG - - #define WARNING_LOG printf - -#else - - #define WARNING_LOG NULL_PRINT_ROUTINE - -#endif - -/************** Events *******************/ - -#ifdef HAS_EVENTS_TRACE - - #define IX_ETH_DB_EVENTS_TRACE printf - #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_EVENTS_VERBOSE_TRACE - - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_EVENTS_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_EVENTS_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_EVENTS_TRACE */ - -/************** Support *******************/ - -#ifdef HAS_SUPPORT_TRACE - - #define IX_ETH_DB_SUPPORT_TRACE printf - #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_SUPPORT_VERBOSE_TRACE - - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_SUPPORT_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_SUPPORT_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_SUPPORT_TRACE */ - -/************** NPE Adaptor *******************/ - -#ifdef HAS_NPE_TRACE - - #define IX_ETH_DB_NPE_TRACE printf - #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_NPE_VERBOSE_TRACE - - #define IX_ETH_DB_NPE_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_NPE_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_NPE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_NPE_TRACE */ - -#ifdef HAS_DUMP_NPE_TREE - -#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) ixEthELTDumpTree(eltBaseAddress, eltSize) - -#else - -#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) /* nothing */ - -#endif /* HAS_DUMP_NPE_TREE */ - -/************** Port Update *******************/ - -#ifdef HAS_UPDATE_TRACE - - #define IX_ETH_DB_UPDATE_TRACE printf - - #ifdef HAS_UPDATE_VERBOSE_TRACE - - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif - -#else /* HAS_UPDATE_VERBOSE_TRACE */ - - #define IX_ETH_DB_UPDATE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE - -#endif /* HAS_UPDATE_TRACE */ diff --git a/drivers/net/npe/include/IxEthDBMessages_p.h b/drivers/net/npe/include/IxEthDBMessages_p.h deleted file mode 100644 index ff18160c1f..0000000000 --- a/drivers/net/npe/include/IxEthDBMessages_p.h +++ /dev/null @@ -1,258 +0,0 @@ -/** - * @file IxEthDBMessages_p.h - * - * @brief Definitions of NPE messages - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthDBMessages_p_H -#define IxEthDBMessages_p_H - -#include -#include -#include "IxEthDB_p.h" - -/* events watched by the Eth event processor */ -#define IX_ETH_DB_MIN_EVENT_ID (IX_ETHNPE_EDB_GETMACADDRESSDATABASE) -#define IX_ETH_DB_MAX_EVENT_ID (IX_ETHNPE_PC_SETAPMACTABLE) - -/* macros to fill and extract data from NPE messages - place any endian conversions here */ -#define RESET_ELT_MESSAGE(message) { memset((void *) &(message), 0, sizeof((message))); } -#define NPE_MSG_ID(msg) ((msg).data[0] >> 24) - -#define FILL_SETPORTVLANTABLEENTRY_MSG(message, portID, setOffset, vlanMembershipSet, ttiSet) \ - do { \ - message.data[0] = (IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY << 24) | (portID << 16) | (setOffset * 2); \ - message.data[1] = (vlanMembershipSet << 8) | ttiSet; \ - } while (0); - -#define FILL_SETPORTVLANTABLERANGE_MSG(message, portID, offset, length, zone) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE << 24 | portID << 16 | offset << 9 | length << 1; \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETDEFAULTRXVID_MSG(message, portID, tpid, vlanTag) \ - do { \ - message.data[0] = (IX_ETHNPE_VLAN_SETDEFAULTRXVID << 24) \ - | (portID << 16); \ - \ - message.data[1] = (tpid << 16) | vlanTag; \ - } while (0); - -#define FILL_SETRXTAGMODE_MSG(message, portID, filterMode, tagMode) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETRXTAGMODE << 24 \ - | portID << 16 \ - | filterMode << 2 \ - | tagMode; \ - \ - message.data[1] = 0; \ - } while (0); - -#define FILL_SETRXQOSENTRY(message, portID, classIndex, trafficClass, aqmQueue) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETRXQOSENTRY << 24 \ - | portID << 16 \ - | classIndex; \ - \ - message.data[1] = trafficClass << 24 \ - | 0x1 << 23 \ - | aqmQueue << 16 \ - | aqmQueue << 4; \ - } while (0); - -#define FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE << 24 \ - | portID << 16 \ - | (enable ? 0x1 : 0x0); \ - \ - message.data[1] = 0; \ - } while (0); - - -#define FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked) \ - do { \ - message.data[0] = IX_ETHNPE_STP_SETBLOCKINGSTATE << 24 \ - | portID << 16 \ - | (blocked ? 0x1 : 0x0); \ - \ - message.data[1] = 0; \ - } while (0); - -#define FILL_SETBBSID_MSG(message, portID, bbsid) \ - do { \ - message.data[0] = IX_ETHNPE_PC_SETBBSID << 24 \ - | portID << 16 \ - | bbsid->macAddress[0] << 8 \ - | bbsid->macAddress[1]; \ - \ - message.data[1] = bbsid->macAddress[2] << 24 \ - | bbsid->macAddress[3] << 16 \ - | bbsid->macAddress[4] << 8 \ - | bbsid->macAddress[5]; \ - } while (0); - -#define FILL_SETFRAMECONTROLDURATIONID(message, portID, frameControlDurationID) \ - do { \ - message.data[0] = (IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID << 24) | (portID << 16); \ - message.data[1] = frameControlDurationID; \ - } while (0); - -#define FILL_SETAPMACTABLE_MSG(message, zone) \ - do { \ - message.data[0] = IX_ETHNPE_PC_SETAPMACTABLE << 24 \ - | 0 << 8 /* always use index 0 */ \ - | 64; /* 32 entries, 8 bytes each, 4 bytes in a word */ \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETFIREWALLMODE_MSG(message, portID, epDelta, mode, address) \ - do { \ - message.data[0] = IX_ETHNPE_FW_SETFIREWALLMODE << 24 \ - | portID << 16 \ - | (epDelta & 0xFF) << 8 \ - | mode; \ - \ - message.data[1] = (UINT32) address; \ - } while (0); - -#define FILL_SETMACADDRESSDATABASE_MSG(message, portID, epDelta, blockCount, address) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_SETMACADDRESSSDATABASE << 24 \ - | (epDelta & 0xFF) << 8 \ - | (blockCount & 0xFF); \ - \ - message.data[1] = (UINT32) address; \ - } while (0); - -#define FILL_GETMACADDRESSDATABASE(message, npeId, zone) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_GETMACADDRESSDATABASE << 24; \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETMAXFRAMELENGTHS_MSG(message, portID, maxRxFrameSize, maxTxFrameSize) \ - do { \ - message.data[0] = IX_ETHNPE_SETMAXFRAMELENGTHS << 24 \ - | portID << 16 \ - | ((maxRxFrameSize + 63) / 64) << 8 /* max Rx 64-byte blocks */ \ - | (maxTxFrameSize + 63) / 64; /* max Tx 64-byte blocks */ \ - \ - message.data[1] = maxRxFrameSize << 16 | maxTxFrameSize; \ - } while (0); - -#define FILL_SETPORTADDRESS_MSG(message, portID, macAddress) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_SETPORTADDRESS << 24 \ - | portID << 16 \ - | macAddress[0] << 8 \ - | macAddress[1]; \ - \ - message.data[1] = macAddress[2] << 24 \ - | macAddress[3] << 16 \ - | macAddress[4] << 8 \ - | macAddress[5]; \ - } while (0); - -/* access to a MAC node in the NPE tree */ -#define NPE_NODE_BYTE(eltNodeAddr, offset) (((UINT8 *) (eltNodeAddr))[offset]) - -/* browsing of the implicit linear binary tree structure of the NPE tree */ -#define LEFT_CHILD_OFFSET(offset) ((offset) << 1) -#define RIGHT_CHILD_OFFSET(offset) (((offset) << 1) + 1) - -#define IX_EDB_FLAGS_ACTIVE (0x2) -#define IX_EDB_FLAGS_VALID (0x1) -#define IX_EDB_FLAGS_RESERVED (0xfc) -#define IX_EDB_FLAGS_INACTIVE_VALID (0x1) - -#define IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET (6) -#define IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET (7) -#define IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET (6) -#define IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET (7) -#define IX_EDB_NPE_NODE_FW_FLAGS_OFFSET (1) -#define IX_EDB_NPE_NODE_FW_RESERVED_OFFSET (6) -#define IX_EDB_NPE_NODE_FW_ADDR_OFFSET (2) - -#define IX_EDB_NPE_NODE_VALID(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_VALID) != 0) -#define IX_EDB_NPE_NODE_ACTIVE(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_ACTIVE) != 0) -#define IX_EDB_NPE_NODE_PORT_ID(address) (NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET)) - -/* macros to send messages to the NPEs */ -#define IX_ETHDB_ASYNC_SEND_NPE_MSG(npeId, msg, result) \ - do { \ - result = ixNpeMhMessageSend(npeId, msg, IX_NPEMH_SEND_RETRIES_DEFAULT); \ - \ - if (result != IX_SUCCESS) \ - { \ - ERROR_LOG("DB: Failed to send NPE message\n"); \ - } \ - } while (0); - -#define IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result) \ - do { \ - result = ixNpeMhMessageWithResponseSend(npeId, msg, msg.data[0] >> 24, ixEthDBNpeMsgAck, IX_NPEMH_SEND_RETRIES_DEFAULT); \ - \ - if (result == IX_SUCCESS) \ - { \ - result = ixOsalMutexLock(&ixEthDBPortInfo[IX_ETH_DB_NPE_TO_PORT_ID(npeId)].npeAckLock, IX_ETH_DB_NPE_TIMEOUT); \ - \ - if (result != IX_SUCCESS) \ - { \ - ERROR_LOG("DB: NPE failed to respond within %dms\n", IX_ETH_DB_NPE_TIMEOUT); \ - } \ - } \ - else \ - { \ - ERROR_LOG("DB: Failed to send NPE message\n"); \ - } \ - } while (0); - -#ifndef IX_NDEBUG -#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100) -extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2]; -extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen; -#endif - -#define IX_ETHDB_SEND_NPE_MSG(npeId, msg, result) { LOG_NPE_MSG(msg); IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result); } - -#endif /* IxEthDBMessages_p_H */ diff --git a/drivers/net/npe/include/IxEthDBPortDefs.h b/drivers/net/npe/include/IxEthDBPortDefs.h deleted file mode 100644 index c3acbdddef..0000000000 --- a/drivers/net/npe/include/IxEthDBPortDefs.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - * @file IxEthDBPortDefs.h - * - * @brief Public definition of the ports and port capabilities - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxEthDBPortDefs IXP400 Ethernet Database Port Definitions (IxEthDBPortDefs) - * - * @brief IXP400 Public definition of the ports and port capabilities - * - * @{ - */ - -#ifndef IxEthDBPortDefs_H -#define IxEthDBPortDefs_H - -/** - * @brief Port types - currently only Ethernet NPEs are recognized as specific types - * All other (user-defined) ports must be specified as IX_ETH_GENERIC - */ -typedef enum -{ - IX_ETH_GENERIC = 0, /**< generic ethernet port */ - IX_ETH_NPE /**< specific Ethernet NPE */ -} IxEthDBPortType; - -/** - * @brief Port capabilities - used by ixEthAccDatabaseMaintenance to decide whether it - * should manually age entries or not depending on the port capabilities. - * - * Ethernet NPEs have aging capabilities, meaning that they will age the entries - * automatically (by themselves).*/ -typedef enum -{ - IX_ETH_NO_CAPABILITIES = 0, /**< no aging capabilities */ - IX_ETH_ENTRY_AGING = 0x1 /**< aging capabilities present */ -} IxEthDBPortCapability; - -/** - * @brief Port Definition - a structure contains the Port type and capabilities - */ -typedef struct -{ - IxEthDBPortType type; - IxEthDBPortCapability capabilities; -} IxEthDBPortDefinition; - -/** - * @brief Port definitions structure, indexed on the port ID - * @warning Ports 0 and 1 are used by the Ethernet access component therefore - * it is essential to be left untouched. Port 2 here (WAN) is given as - * an example port. The NPE firmware also assumes the NPE B to be - * the port 0 and NPE C to be the port 1. - * - * @note that only 32 ports (0..31) are supported by EthDB - */ -static const IxEthDBPortDefinition ixEthDBPortDefinitions[] = -{ - /* id type capabilities */ - { /* 0 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE B */ - { /* 1 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE C */ - { /* 2 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE A */ - { /* 3 */ IX_ETH_GENERIC, IX_ETH_NO_CAPABILITIES }, /* WAN port */ -}; - -/** - * @def IX_ETH_DB_NUMBER_OF_PORTS - * @brief number of supported ports - */ -#define IX_ETH_DB_NUMBER_OF_PORTS (sizeof (ixEthDBPortDefinitions) / sizeof (ixEthDBPortDefinitions[0])) - -/** - * @def IX_ETH_DB_UNKNOWN_PORT - * @brief definition of an unknown port - */ -#define IX_ETH_DB_UNKNOWN_PORT (0xff) - -/** - * @def IX_ETH_DB_ALL_PORTS - * @brief Special port ID indicating all the ports - * @note This port ID can be used only by a subset of the EthDB API; each - * function specifically mentions whether this is a valid parameter as the port ID - */ -#define IX_ETH_DB_ALL_PORTS (IX_ETH_DB_NUMBER_OF_PORTS + 1) - -/** - * @def IX_ETH_DB_PORTS_ASSERTION - * @brief catch invalid port definitions (<2) with a - * compile-time assertion resulting in a duplicate case error. - */ -#define IX_ETH_DB_PORTS_ASSERTION { switch(0) { case 0 : ; case 1 : ; case IX_ETH_DB_NUMBER_OF_PORTS : ; }} - -/** - * @def IX_ETH_DB_CHECK_PORT(portID) - * @brief safety checks to verify whether the port is invalid or uninitialized - */ -#define IX_ETH_DB_CHECK_PORT(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ - \ - if (!ixEthDBPortInfo[(portID)].enabled) \ - { \ - return IX_ETH_DB_PORT_UNINITIALIZED; \ - } \ -} - -/** - * @def IX_ETH_DB_CHECK_PORT_ALL(portID) - * @brief safety checks to verify whether the port is invalid or uninitialized; - * tolerates the use of IX_ETH_DB_ALL_PORTS - */ -#define IX_ETH_DB_CHECK_PORT_ALL(portID) \ -{ \ - if ((portID) != IX_ETH_DB_ALL_PORTS) \ - IX_ETH_DB_CHECK_PORT(portID) \ -} - -#endif /* IxEthDBPortDefs_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthDBQoS.h b/drivers/net/npe/include/IxEthDBQoS.h deleted file mode 100644 index 6d34889452..0000000000 --- a/drivers/net/npe/include/IxEthDBQoS.h +++ /dev/null @@ -1,154 +0,0 @@ -/** - * @file IxEthDBQoS.h - * - * @brief Public definitions for QoS traffic classes - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxEthDBPortDefs IXP400 Ethernet QoS definitions - * - * @brief IXP00 Public definitions for QoS traffic classes - * - * @{ - */ - -#ifndef IxEthDBQoS_H -#define IxEthDBQoS_H - -/** - * @def IX_ETH_DB_QUEUE_UNAVAILABLE - * @brief alias to indicate a queue (traffic class) is not available - */ -#define IX_ETH_DB_QUEUE_UNAVAILABLE (0) - -#ifndef IX_IEEE802_1Q_QOS_PRIORITY_COUNT -/** - * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT - * @brief number of QoS priorities, according to IEEE 802.1Q - */ -#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8) -#endif - -/** - * @brief array containing all the supported traffic class configurations - */ -static const -UINT8 ixEthDBQueueAssignments[][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = -{ - { 4, 5, 6, 7, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 15, 16, 17, 18, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 11, 23, 26, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 4, 5, 6, 7, 8, 9, 10, 11 } - /* add here all other cases of queue configuration structures and update ixEthDBTrafficClassDefinitions to use them */ -}; - -/** - * @brief value used to index the NPE A functionality ID in the traffic class definition table - */ -#define IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX (0) - -/** - * @brief value used to index the traffic class count in the traffic class definition table - */ -#define IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX (1) - -/** - * @brief value used to index the queue assignment index in the traffic class definition table - */ -#define IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX (2) - -/** - * @brief traffic class definitions - * - * This array contains the default traffic class definition configuration, - * as well as any special cases dictated by the functionality ID of NPE A. - * - * The default case should not be removed (otherwise the Ethernet - * components will assert a fatal failure on initialization). - */ -static const -UINT8 ixEthDBTrafficClassDefinitions[][3] = -{ - /* NPE A functionality ID | traffic class count | queue assignment index (points to the queue enumeration in ixEthDBQueueAssignments) */ - { 0x00, 4, 0 }, /* default case - DO NOT REMOVE */ - { 0x04, 4, 1 }, /* NPE A image ID 0.4.0.0 */ - { 0x09, 3, 2 }, /* NPE A image ID 0.9.0.0 */ - { 0x80, 8, 3 }, /* NPE A image ID 10.80.02.0 */ - { 0x81, 8, 3 }, /* NPE A image ID 10.81.02.0 */ - { 0x82, 8, 3 } /* NPE A image ID 10.82.02.0 */ -}; - -/** - * @brief IEEE 802.1Q recommended QoS Priority => traffic class maps - * - * @verbatim - Number of available traffic classes - 1 2 3 4 5 6 7 8 - QoS Priority - 0 0 0 0 1 1 1 1 2 - 1 0 0 0 0 0 0 0 0 - 2 0 0 0 0 0 0 0 1 - 3 0 0 0 1 1 2 2 3 - 4 0 1 1 2 2 3 3 4 - 5 0 1 1 2 3 4 4 5 - 6 0 1 2 3 4 5 5 6 - 7 0 1 2 3 4 5 6 7 - - @endverbatim - */ -static const -UINT8 ixEthIEEE802_1QUserPriorityToTrafficClassMapping[IX_IEEE802_1Q_QOS_PRIORITY_COUNT][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = - { - { 0, 0, 0, 0, 0, 0, 0, 0 }, /* 1 traffic class available */ - { 0, 0, 0, 0, 1, 1, 1, 1 }, /* 2 traffic classes available */ - { 0, 0, 0, 0, 1, 1, 2, 2 }, /* 3 traffic classes available */ - { 1, 0, 0, 1, 2, 2, 3, 3 }, /* 4 traffic classes available */ - { 1, 0, 0, 1, 2, 3, 4, 4 }, /* 5 traffic classes available */ - { 1, 0, 0, 2, 3, 4, 5, 5 }, /* 6 traffic classes available */ - { 1, 0, 0, 2, 3, 4, 5, 6 }, /* 7 traffic classes available */ - { 2, 0, 1, 3, 4, 5, 6, 7 } /* 8 traffic classes available */ - }; - -#endif /* IxEthDBQoS_H */ - -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthDB_p.h b/drivers/net/npe/include/IxEthDB_p.h deleted file mode 100644 index d173d12082..0000000000 --- a/drivers/net/npe/include/IxEthDB_p.h +++ /dev/null @@ -1,710 +0,0 @@ -/** - * @file IxEthDB_p.h - * - * @brief Private MAC learning API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthDB_p_H -#define IxEthDB_p_H - -#include -#include -#include -#include -#include - -#include "IxEthDBMessages_p.h" -#include "IxEthDBLog_p.h" - -#if (CPU==SIMSPARCSOLARIS) - -/* when running unit tests intLock() won't protect the event queue so we lock it manually */ -#define TEST_FIXTURE_LOCK_EVENT_QUEUE { ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); } -#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE { ixOsalMutexUnlock(&eventQueueLock); } - -#else - -#define TEST_FIXTURE_LOCK_EVENT_QUEUE /* nothing */ -#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE /* nothing */ - -#endif /* #if(CPU==SIMSPARCSOLARIS) */ - -#ifndef IX_UNIT_TEST - -#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER /* nothing */ -#define TEST_FIXTURE_MARK_OVERFLOW_EVENT /* nothing */ - -#else - -extern int dbAccessCounter; -extern int overflowEvent; - -#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER { dbAccessCounter++; } -#define TEST_FIXTURE_MARK_OVERFLOW_EVENT { overflowEvent = 1; } - -#endif - -/* code readability markers */ -#define __mempool__ /* memory pool marker */ -#define __lock__ /* hash write locking marker */ -#define __smartpointer__ /* smart pointer marker - warning: use only clone() when duplicating! */ -#define __alignment__ /* marker for data used only as alignment zones */ - -/* constants */ -#define IX_ETH_DB_NPE_TIMEOUT (100) /* NPE response timeout, in ms */ - -/** - * number of hash table buckets - * it should be at least 8x the predicted number of entries for performance - * each bucket needs 8 bytes - */ -#define NUM_BUCKETS (8192) - -/** - * number of hash table buckets to preload when incrementing bucket iterator - * = two cache lines - */ -#define IX_ETHDB_CACHE_LINE_AHEAD (2) - -#define IX_ETHDB_BUCKETPTR_AHEAD ((IX_ETHDB_CACHE_LINE_AHEAD * IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - -#define IX_ETHDB_BUCKET_INDEX_MASK (((IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - 1) - -/* locks */ -#define MAX_LOCKS (20) /**< maximum number of locks used simultaneously, do not tamper with */ - -/* learning tree constants */ -#define INITIAL_ELT_SIZE (8) /**< initial byte size of tree (empty unused root size) */ -#define MAX_ELT_SIZE (512) /**< maximum number of entries (includes unused root) */ -#define MAX_GW_SIZE (32) /**< maximum number of gateway entries (including unused root) */ -#define MAX_FW_SIZE (32) /**< maximum number of firewall entries (including unused root) */ -#define ELT_ENTRY_SIZE (8) /**< entry size, in bytes */ -#define ELT_ROOT_OFFSET (ELT_ENTRY_SIZE) /**< tree root offset, in bytes - node preceeding root is unused */ -#define FULL_ELT_BYTE_SIZE (MAX_ELT_SIZE * ELT_ENTRY_SIZE) /**< full size of tree, in bytes, including unused root */ -#define FULL_GW_BYTE_SIZE (MAX_GW_SIZE * ELT_ENTRY_SIZE) /**< full size of gateway list, in bytes, including unused root */ -#define FULL_FW_BYTE_SIZE (MAX_FW_SIZE * ELT_ENTRY_SIZE) /**< full size of firewall table, in bytes, including unused root */ - -/* maximum size of the VLAN table: - * 4096 bits (one per VLAN) - * 8 bits in one byte - * interleaved VLAN membership and VLAN TTI (*2) */ -#define FULL_VLAN_BYTE_SIZE (4096 / 8 * 2) - -/* upper 9 bits used as set index, lower 3 bits as byte index */ -#define VLAN_SET_OFFSET(vlanID) ((vlanID) >> 3) -#define VLAN_SET_MASK(vlanID) (0x7 - ((vlanID) & 0x7)) - -/* Update zone definitions */ -#define NPE_TREE_MEM_SIZE (4096) /* ((511 entries + 1 unused root) * 8 bytes/entry) */ - -/* check the above value, we rely on 4k */ -#if NPE_TREE_MEM_SIZE != 4096 - #error NPE_TREE_MEM_SIZE is not defined to 4096 bytes! -#endif - -/* Size Filtering limits (Jumbo frame filtering) */ -#define IX_ETHDB_MAX_FRAME_SIZE 65535 /* other ports than NPE ports */ -#define IX_ETHDB_MIN_FRAME_SIZE 1 /* other ports than NPE ports */ -#define IX_ETHDB_MAX_NPE_FRAME_SIZE 16320 /* NPE ports firmware limit */ -#define IX_ETHDB_MIN_NPE_FRAME_SIZE 1 /* NPE ports firmware limit */ -#define IX_ETHDB_DEFAULT_FRAME_SIZE 1522 - -/* memory management pool sizes */ - -/* - * Note: - * - * NODE_POOL_SIZE controls the maximum number of elements in the database at any one time. - * It should be large enough to cover all the search trees of all the ports simultaneously. - * - * MAC_POOL_SIZE should be higher than NODE_POOL_SIZE by at least the total number of MAC addresses - * possible to be held at any time in all the ports. - * - * TREE_POOL_SIZE should follow the same guideline as for MAC_POOL_SIZE. - * - * The database structure described here (2000/4000/4000) is enough for two NPEs holding at most 511 - * entries each plus one PCI NIC holding at most 900 entries. - */ - -#define NODE_POOL_SIZE (2000) /**< number of HashNode objects - also master number of elements in the database; each entry has 16 bytes */ -#define MAC_POOL_SIZE (4000) /**< number of MacDescriptor objects; each entry has 28 bytes */ -#define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */ - -/* retry policies */ -#define BUSY_RETRY_ENABLED (true) /**< if set to true the API will retry automatically calls returning BUSY */ -#define FOREVER_RETRY (true) /**< if set to true the API will retry forever BUSY calls */ -#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is false */ -#define BUSY_RETRY_YIELD (5) /**< ticks to yield for every failed retry */ - -/* event management */ -#define EVENT_QUEUE_SIZE (500) /**< size of the sink collecting events from the Message Handler FIFO */ -#define EVENT_PROCESSING_LIMIT (100) /**< batch processing control size (how many events are extracted from the queue at once) */ - -/* MAC descriptors */ -#define STATIC_ENTRY (true) -#define DYNAMIC_ENTRY (false) - -/* age reset on next maintenance - incrementing by 1 will reset to 0 */ -#define AGE_RESET (0xFFFFFFFF) - -/* dependency maps */ -#define EMPTY_DEPENDENCY_MAP (0) - -/* trees */ -#define RIGHT (1) -#define LEFT (-1) - -/* macros */ -#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ -} - -#define IX_ETH_DB_CHECK_PORT_INITIALIZED(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ - else \ - { \ - if (!ixEthDBPortInfo[portID].initialized) \ - { \ - return IX_ETH_DB_PORT_UNINITIALIZED; \ - } \ - } \ -} - -/* single NPE check */ -#define IX_ETH_DB_CHECK_SINGLE_NPE(portID) \ - if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) \ - { \ - WARNING_LOG("EthDB: port ID %d is unavailable\n",(UINT32) portID); \ - \ - return IX_ETH_DB_INVALID_PORT; \ - } - -/* feature check */ -#define IX_ETH_DB_CHECK_FEATURE(portID, feature) \ - if ((ixEthDBPortInfo[portID].featureStatus & feature) == 0) \ - { \ - return IX_ETH_DB_FEATURE_UNAVAILABLE; \ - } - -/* busy retrying */ -#define BUSY_RETRY(functionCall) \ - { \ - UINT32 retries = 0; \ - IxEthDBStatus br_result; \ - \ - while ((br_result = functionCall) == IX_ETH_DB_BUSY \ - && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \ - \ - if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (br_result == IX_ETH_DB_FAIL)) \ - {\ - ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY failed at %s:%d\n", __FILE__, __LINE__); \ - }\ - } - -#define BUSY_RETRY_WITH_RESULT(functionCall, brwr_result) \ - { \ - UINT32 retries = 0; \ - \ - while ((brwr_result = functionCall) == IX_ETH_DB_BUSY \ - && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \ - \ - if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (brwr_result == IX_ETH_DB_FAIL)) \ - {\ - ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY_WITH_RESULT failed at %s:%d\n", __FILE__, __LINE__); \ - }\ - } - -/* iterators */ -#define IS_ITERATOR_VALID(iteratorPtr) ((iteratorPtr)->node != NULL) - -/* dependency port maps */ - -/* Warning: if port indexing starts from 1 replace (portID) with (portID - 1) in DEPENDENCY_MAP (and make sure IX_ETH_DB_NUMBER_OF_PORTS is big enough) */ - -/* gives an empty dependency map */ -#define SET_EMPTY_DEPENDENCY_MAP(map) { int i = 0; for (; i < 32 ; i++) map[i] = 0; } - -#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = true; for (; i < 32 ; i++) if (map[i] != 0) { result = false; break; }} - -/** - * gives a map consisting only of 'portID' - */ -#define SET_DEPENDENCY_MAP(map, portID) {SET_EMPTY_DEPENDENCY_MAP(map); map[portID >> 3] = 1 << (portID & 0x7);} - -/** - * gives a map resulting from joining map1 and map2 - */ -#define JOIN_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] | map2[i]; } - -/** - * gives the map resulting from joining portID and map - */ -#define JOIN_PORT_TO_MAP(map, portID) { map[portID >> 3] |= 1 << (portID & 0x7); } - -/** - * gives the map resulting from excluding portID from map - */ -#define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); } - -/** - * returns true if map1 is a subset of map2 and false otherwise - */ -#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = true; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = false; } - -/** - * returns true is portID is part of map and false otherwise - */ -#define IS_PORT_INCLUDED(portID, map) ((map[portID >> 3] & (1 << (portID & 0x7))) != 0) - -/** - * returns the difference between map1 and map2 (ports included in map1 and not included in map2) - */ -#define DIFF_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); } - -/** - * returns true if the maps collide (have at least one port in common) and false otherwise - */ -#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = false; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = true; } - -/* size (number of ports) of a dependency map */ -#define GET_MAP_SIZE(map, size) { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }} - -/* copy map2 into map1 */ -#define COPY_DEPENDENCY_MAP(map1, map2) { memcpy (map1, map2, sizeof (map1)); } - -/* definition of a port map size/port number which cannot be reached (we support at most 32 ports) */ -#define MAX_PORT_SIZE (0xFF) -#define MAX_PORT_NUMBER (0xFF) - -#define IX_ETH_DB_CHECK_REFERENCE(ptr) { if ((ptr) == NULL) { return IX_ETH_DB_INVALID_ARG; } } -#define IX_ETH_DB_CHECK_MAP(portID, map) { if (!IS_PORT_INCLUDED(portID, map)) { return IX_ETH_DB_INVALID_ARG; } } - -/* event queue macros */ -#define EVENT_QUEUE_WRAP(offset) ((offset) >= EVENT_QUEUE_SIZE ? (offset) - EVENT_QUEUE_SIZE : (offset)) - -#define CAN_ENQUEUE(eventQueuePtr) ((eventQueuePtr)->length < EVENT_QUEUE_SIZE) - -#define QUEUE_HEAD(eventQueuePtr) (&(eventQueuePtr)->queue[EVENT_QUEUE_WRAP((eventQueuePtr)->base + (eventQueuePtr)->length)]) - -#define QUEUE_TAIL(eventQueuePtr) (&(eventQueuePtr)->queue[(eventQueuePtr)->base]) - -#define PUSH_UPDATE_QUEUE(eventQueuePtr) { (eventQueuePtr)->length++; } - -#define SHIFT_UPDATE_QUEUE(eventQueuePtr) \ - { \ - (eventQueuePtr)->base = EVENT_QUEUE_WRAP((eventQueuePtr)->base + 1); \ - (eventQueuePtr)->length--; \ - } - -#define RESET_QUEUE(eventQueuePtr) \ - { \ - (eventQueuePtr)->base = 0; \ - (eventQueuePtr)->length = 0; \ - } - -/* node stack macros - used to browse a tree without using a recursive function */ -#define NODE_STACK_INIT(stack) { (stack)->nodeCount = 0; } -#define NODE_STACK_PUSH(stack, node, offset) { (stack)->nodes[(stack)->nodeCount] = (node); (stack)->offsets[(stack)->nodeCount++] = (offset); } -#define NODE_STACK_POP(stack, node, offset) { (node) = (stack)->nodes[--(stack)->nodeCount]; offset = (stack)->offsets[(stack)->nodeCount]; } -#define NODE_STACK_NONEMPTY(stack) ((stack)->nodeCount != 0) - -#ifndef IX_NDEBUG -#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100) -#define LOG_NPE_MSG(msg) \ - do { \ - UINT32 npeMsgHistoryIndex = (npeMsgHistoryLen++) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; \ - npeMsgHistory[npeMsgHistoryIndex][0] = msg.data[0]; \ - npeMsgHistory[npeMsgHistoryIndex][1] = msg.data[1]; \ - } while (0); -#else -#define LOG_NPE_MSG() /* nothing */ -#endif - -/* ----------- Data -------------- */ - -/* typedefs */ - -typedef UINT32 (*HashFunction)(void *entity); -typedef BOOL (*MatchFunction)(void *reference, void *entry); -typedef void (*FreeFunction)(void *entry); - -/** - * basic component of a hash table - */ -typedef struct HashNode_t -{ - void *data; /**< specific data */ - struct HashNode_t *next; /**< used for bucket chaining */ - - __mempool__ struct HashNode_t *nextFree; /**< memory pool management */ - - __lock__ IxOsalFastMutex lock; /**< node lock */ -} HashNode; - -/** - * @brief hash table iterator definition - * - * an iterator is an object which can be used - * to browse a hash table - */ -typedef struct -{ - UINT32 bucketIndex; /**< index of the currently iterated bucket */ - HashNode *previousNode; /**< reference to the previously iterated node within the current bucket */ - HashNode *node; /**< reference to the currently iterated node */ -} HashIterator; - -/** - * definition of a MAC descriptor (a database record) - */ - -typedef enum -{ - IX_ETH_DB_WIFI_AP_TO_STA = 0x0, - IX_ETH_DB_WIFI_AP_TO_AP = 0x1 -} IxEthDBWiFiRecordType; - -typedef union -{ - struct - { - UINT32 age; - BOOL staticEntry; /**< true if this address is static (doesn't age) */ - } filteringData; - - struct - { - UINT32 age; - BOOL staticEntry; - UINT32 ieee802_1qTag; - } filteringVlanData; - - struct - { - IxEthDBWiFiRecordType type; /**< AP_TO_AP (0x1) or AP_TO_STA (0x0) */ - UINT32 gwAddressIndex; /**< used only when linearizing the entries for NPE usage */ - UINT8 gwMacAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; - - __alignment__ UINT8 reserved2[2]; - } wifiData; -} IxEthDBRecordData; - -typedef struct MacDescriptor_t -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; - - __alignment__ UINT8 reserved1[2]; - - UINT32 portID; - IxEthDBRecordType type; - IxEthDBRecordData recordData; - - /* used for internal operations, such as NPE linearization */ - void *internal; - - /* custom user data */ - void *user; - - __mempool__ struct MacDescriptor_t *nextFree; /**< memory pool management */ - __smartpointer__ UINT32 refCount; /**< smart pointer reference counter */ -} MacDescriptor; - -/** - * hash table definition - */ -typedef struct -{ - HashNode *hashBuckets[NUM_BUCKETS]; - UINT32 numBuckets; - - __lock__ IxOsalFastMutex bucketLocks[NUM_BUCKETS]; - - HashFunction entryHashFunction; - MatchFunction *matchFunctions; - FreeFunction freeFunction; -} HashTable; - -typedef enum -{ - IX_ETH_DB_MAC_KEY = 1, - IX_ETH_DB_MAC_PORT_KEY = 2, - IX_ETH_DB_MAC_VLAN_KEY = 3, - IX_ETH_DB_MAX_KEY_INDEX = 3 -} IxEthDBSearchKeyType; - -typedef struct MacTreeNode_t -{ - __smartpointer__ MacDescriptor *descriptor; - struct MacTreeNode_t *left, *right; - - __mempool__ struct MacTreeNode_t *nextFree; -} MacTreeNode; - -typedef IxEthDBStatus (*IxEthDBPortUpdateHandler)(IxEthDBPortId portID, IxEthDBRecordType type); - -typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node); - -typedef struct -{ - BOOL updateEnabled; /**< true if updates are enabled for port */ - BOOL userControlled; /**< true if the user has manually used ixEthDBPortUpdateEnableSet */ - BOOL treeInitialized; /**< true if the NPE has received an initial tree */ - IxEthDBPortUpdateHandler updateHandler; /**< port update handler routine */ - void *npeUpdateZone; /**< port update memory zone */ - void *npeGwUpdateZone; /**< port update memory zone for gateways */ - void *vlanUpdateZone; /**< port update memory zone for VLAN tables */ - MacTreeNode *searchTree; /**< internal search tree, in MacTreeNode representation */ - BOOL searchTreePendingWrite; /**< true if searchTree holds a tree pending write to the port */ -} PortUpdateMethod; - -typedef struct -{ - IxEthDBPortId portID; /**< port ID */ - BOOL enabled; /**< true if the port is enabled */ - BOOL agingEnabled; /**< true if aging on this port is enabled */ - BOOL initialized; - IxEthDBPortMap dependencyPortMap; /**< dependency port map for this port */ - PortUpdateMethod updateMethod; /**< update method structure */ - BOOL macAddressUploaded; /**< true if the MAC address was uploaded into the port */ - UINT32 maxRxFrameSize; /**< maximum Rx frame size for this port */ - UINT32 maxTxFrameSize; /**< maximum Rx frame size for this port */ - - UINT8 bbsid[6]; - __alignment__ UINT8 reserved[2]; - UINT32 frameControlDurationID; /**< Frame Control - Duration/ID WiFi control */ - - IxEthDBVlanTag vlanTag; /**< default VLAN tag for port */ - IxEthDBPriorityTable priorityTable; /**< QoS <=> internal priority mapping */ - IxEthDBVlanSet vlanMembership; - IxEthDBVlanSet transmitTaggingInfo; - IxEthDBFrameFilter frameFilter; - IxEthDBTaggingAction taggingAction; - - UINT32 npeFrameFilter; - UINT32 npeTaggingAction; - - IxEthDBFirewallMode firewallMode; - BOOL srcAddressFilterEnabled; - - BOOL stpBlocked; - - IxEthDBFeature featureCapability; - IxEthDBFeature featureStatus; - - UINT32 ixEthDBTrafficClassAQMAssignments[IX_IEEE802_1Q_QOS_PRIORITY_COUNT]; - - UINT32 ixEthDBTrafficClassCount; - - UINT32 ixEthDBTrafficClassAvailable; - - - - __lock__ IxOsalMutex npeAckLock; -} PortInfo; - -/* list of port information structures indexed on port Ids */ -extern IX_ETH_DB_PUBLIC PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS]; - -typedef enum -{ - IX_ETH_DB_ADD_FILTERING_RECORD = 0xFF0001, - IX_ETH_DB_REMOVE_FILTERING_RECORD = 0xFF0002 -} PortEventType; - -typedef struct -{ - UINT32 eventType; - IxEthDBPortId portID; - IxEthDBMacAddr macAddr; - BOOL staticEntry; -} PortEvent; - -typedef struct -{ - PortEvent queue[EVENT_QUEUE_SIZE]; - UINT32 base; - UINT32 length; -} PortEventQueue; - -typedef struct -{ - IxEthDBPortId portID; /**< originating port */ - MacDescriptor *macDescriptors[MAX_ELT_SIZE]; /**< addresses to be synced into db */ - UINT32 addressCount; /**< number of addresses */ -} TreeSyncInfo; - -typedef struct -{ - MacTreeNode *nodes[MAX_ELT_SIZE]; - UINT32 offsets[MAX_ELT_SIZE]; - UINT32 nodeCount; -} MacTreeNodeStack; - -/* Prototypes */ - -/* ----------- Memory management -------------- */ - -IX_ETH_DB_PUBLIC void ixEthDBInitMemoryPools(void); - -IX_ETH_DB_PUBLIC HashNode* ixEthDBAllocHashNode(void); -IX_ETH_DB_PUBLIC void ixEthDBFreeHashNode(HashNode *); - -IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBAllocMacDescriptor(void); -IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor); -IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacDescriptor(MacDescriptor *); - -IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBAllocMacTreeNode(void); -IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *); -IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacTreeNode(MacTreeNode *); - -IX_ETH_DB_PUBLIC void ixEthDBPoolFreeMacTreeNode(MacTreeNode *); -IX_ETH_DB_PUBLIC UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree); -IX_ETH_DB_PUBLIC int ixEthDBShowMemoryStatus(void); - -/* Hash Table */ -IX_ETH_DB_PUBLIC void ixEthDBInitHash(HashTable *hashTable, UINT32 numBuckets, HashFunction entryHashFunction, MatchFunction *matchFunctions, FreeFunction freeFunction); - -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference); -IX_ETH_DB_PUBLIC void ixEthDBReleaseHashNode(HashNode *node); - -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC void ixEthDBReleaseHashIterator(HashIterator *iterator); - -/* API Support */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); -IX_ETH_DB_PUBLIC void ixEthDBMaximumFrameSizeAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); - -/* DB Core functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInit(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger); -IX_ETH_DB_PUBLIC HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter); - -/* Learning support */ -IX_ETH_DB_PUBLIC UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2); -IX_ETH_DB_PUBLIC BOOL ixEthDBAddressMatch(void *reference, void *entry); -IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORHash(void *macDescriptor); -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress); - -/* Port updates */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type); -IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts); -IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void); -IX_ETH_DB_PUBLIC void ixEthDBUpdateUnlock(void); -IX_ETH_DB_PUBLIC MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maximumEntries); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta); - -/* Init/unload */ -IX_ETH_DB_PUBLIC void ixEthDBPortSetAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBEventProcessorInit(void); -IX_ETH_DB_PUBLIC void ixEthDBPortInit(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasInit(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions); -IX_ETH_DB_PUBLIC UINT32 ixEthDBRecordSerializeMethodsRegister(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray); -IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasUnload(void); -IX_ETH_DB_PUBLIC void ixEthDBFeatureCapabilityScan(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType); - -/* Event processing */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDefaultEventCallbackEnable(IxEthDBPortId portID, BOOL enable); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); - -/* NPE adaptor */ -IX_ETH_DB_PUBLIC void ixEthDBGetMacDatabaseCbk(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize); -IX_ETH_DB_PUBLIC void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *blocks, UINT32 *startIndex); -IX_ETH_DB_PUBLIC void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node); - -/* Other public API functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate); - -/* Maximum Tx/Rx public functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize); - -/* VLAN-related */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet); - -/* Record search */ -IX_ETH_DB_PUBLIC BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBNullMatch(void *reference, void *entry); -IX_ETH_DB_PUBLIC HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter); -IX_ETH_DB_PUBLIC HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter); - -/* Utilities */ -IX_ETH_DB_PUBLIC const char* mac2string(const unsigned char *mac); -IX_ETH_DB_PUBLIC void showHashInfo(void); -IX_ETH_DB_PUBLIC int ixEthDBAnalyzeHash(void); -IX_ETH_DB_PUBLIC const char* errorString(IxEthDBStatus error); -IX_ETH_DB_PUBLIC int numHashElements(void); -IX_ETH_DB_PUBLIC void zapHashtable(void); -IX_ETH_DB_PUBLIC BOOL ixEthDBCheckSingleBitValue(UINT32 value); - -/* Single Eth NPE Check */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portId); - -#endif /* IxEthDB_p_H */ - diff --git a/drivers/net/npe/include/IxEthMii.h b/drivers/net/npe/include/IxEthMii.h deleted file mode 100644 index 93d3b790b2..0000000000 --- a/drivers/net/npe/include/IxEthMii.h +++ /dev/null @@ -1,270 +0,0 @@ -/** - * @file IxEthMii.h - * - * @brief this file contains the public API of @ref IxEthMii component - * - * Design notes : - * The main intent of this API is to inplement MII high level fonctionalitoes - * to support the codelets provided with the IXP400 software releases. It - * superceedes previous interfaces provided with @ref IxEThAcc component. - * - * This API has been tested with the PHYs provided with the - * IXP400 development platforms. It may not work for specific Ethernet PHYs - * used on specific boards. - * - * This source code detects and interface the LXT972, LXT973 and KS6995 - * Ethernet PHYs. - * - * This source code should be considered as an example which may need - * to be adapted for different hardware implementations. - * - * It is strongly recommended to use public domain and GPL utilities - * like libmii, mii-diag for MII interface support. - * - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthMii_H -#define IxEthMii_H - -#include - -/** - * @defgroup IxEthMii IXP400 Ethernet Phy Access (IxEthMii) API - * - * @brief ethMii is a library that does provides access to the - * Ethernet PHYs - * - *@{ - */ - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) - * - * @brief Scan the MDIO bus for PHYs - * This function scans PHY addresses 0 through 31, and sets phyPresent[n] to - * true if a phy is discovered at address n. - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyPresent BOOL [in] - boolean array of IXP425_ETH_ACC_MII_MAX_ADDR entries - * @param maxPhyCount UINT32 [in] - number of PHYs to search for (the scan will stop when - * the indicated number of PHYs is found). - * - * @return IX_STATUS - * - IX_ETH_ACC_SUCCESS - * - IX_ETH_ACC_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate) - * - * - * @brief Configure a PHY - * Configure a PHY's speed, duplex and autonegotiation status - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - * @param speed100 BOOL [in] - set to true for 100Mbit/s operation, false for 10Mbit/s - * @param fullDuplex BOOL [in] - set to true for Full Duplex, false for Half Duplex - * @param autonegotiate BOOL [in] - set to true to enable autonegotiation - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyLoopbackEnable(UINT32 phyAddr) - * - * - * @brief Enable PHY Loopback in a specific Eth MII port - * - * @note When PHY Loopback is enabled, frames sent out to the PHY from the - * IXP400 will be looped back to the IXP400. They will not be transmitted out - * on the wire. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - *
- */ -PUBLIC IX_STATUS -ixEthMiiPhyLoopbackEnable (UINT32 phyAddr); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyLoopbackDisable(UINT32 phyAddr) - * - * - * @brief Disable PHY Loopback in a specific Eth MII port - * - * - Reentrant - no - * - ISR Callable - no - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - *
- */ -PUBLIC IX_STATUS -ixEthMiiPhyLoopbackDisable (UINT32 phyAddr); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyReset(UINT32 phyAddr) - * - * @brief Reset a PHY - * Reset a PHY - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr); - - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) - * - * @brief Retrieve the current status of a PHY - * Retrieve the link, speed, duplex and autonegotiation status of a PHY - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * @param linkUp BOOL [out] - set to true if the link is up - * @param speed100 BOOL [out] - set to true indicates 100Mbit/s, false indicates 10Mbit/s - * @param fullDuplex BOOL [out] - set to true indicates Full Duplex, false indicates Half Duplex - * @param autoneg BOOL [out] - set to true indicates autonegotiation is enabled, false indicates autonegotiation is disabled - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyShow (UINT32 phyAddr) - * - * - * @brief Display information on a specified PHY - * Display link status, speed, duplex and Auto Negotiation status - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyShow (UINT32 phyAddr); - -#endif /* ndef IxEthMii_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthMii_p.h b/drivers/net/npe/include/IxEthMii_p.h deleted file mode 100644 index 104b65c1f0..0000000000 --- a/drivers/net/npe/include/IxEthMii_p.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * @file IxEthMii_p.h - * - * @author Intel Corporation - * @date - * - * @brief MII Header file - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthMii_p_H -#define IxEthMii_p_H - - -/* MII definitions - these have been verified against the LXT971 and - LXT972 PHYs*/ - -#define IX_ETH_MII_MAX_REG_NUM 0x20 /* max number of registers */ - -#define IX_ETH_MII_CTRL_REG 0x0 /* Control Register */ -#define IX_ETH_MII_STAT_REG 0x1 /* Status Register */ -#define IX_ETH_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ -#define IX_ETH_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ - /* Advertisement Register */ -#define IX_ETH_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ - /* partner ability Register */ -#define IX_ETH_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ - /* Expansion Register */ -#define IX_ETH_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ - /* next-page transmit Register */ - -#define IX_ETH_MII_STAT2_REG 0x11 /* Status Register 2*/ - - -/* MII control register bit */ - -#define IX_ETH_MII_CR_COLL_TEST 0x0080 /* collision test */ -#define IX_ETH_MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */ -#define IX_ETH_MII_CR_RESTART 0x0200 /* restart auto negotiation */ -#define IX_ETH_MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */ -#define IX_ETH_MII_CR_POWER_DOWN 0x0800 /* power down */ -#define IX_ETH_MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */ -#define IX_ETH_MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */ -#define IX_ETH_MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ -#define IX_ETH_MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ -#define IX_ETH_MII_CR_NORM_EN 0x0000 /* just enable the PHY */ -#define IX_ETH_MII_CR_DEF_0_MASK 0xca7f /* they must return zero */ -#define IX_ETH_MII_CR_RES_MASK 0x007f /* reserved bits, return zero */ - -/* MII Status register bit definitions */ - -#define IX_ETH_MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */ -#define IX_ETH_MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */ -#define IX_ETH_MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */ -#define IX_ETH_MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */ -#define IX_ETH_MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */ -#define IX_ETH_MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */ -#define IX_ETH_MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */ -#define IX_ETH_MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */ -#define IX_ETH_MII_SR_T4 0x8000 /* T4 capable */ -#define IX_ETH_MII_SR_ABIL_MASK 0xff80 /* abilities mask */ -#define IX_ETH_MII_SR_EXT_CAP 0x0001 /* extended capabilities */ - - -/* LXT971/2 Status 2 register bit definitions */ -#define IX_ETH_MII_SR2_100 0x4000 -#define IX_ETH_MII_SR2_TX 0x2000 -#define IX_ETH_MII_SR2_RX 0x1000 -#define IX_ETH_MII_SR2_COL 0x0800 -#define IX_ETH_MII_SR2_LINK 0x0400 -#define IX_ETH_MII_SR2_FD 0x0200 -#define IX_ETH_MII_SR2_AUTO 0x0100 -#define IX_ETH_MII_SR2_AUTO_CMPLT 0x0080 -#define IX_ETH_MII_SR2_POLARITY 0x0020 -#define IX_ETH_MII_SR2_PAUSE 0x0010 -#define IX_ETH_MII_SR2_ERROR 0x0008 - -/* MII Link Code word bit definitions */ - -#define IX_ETH_MII_BP_FAULT 0x2000 /* remote fault */ -#define IX_ETH_MII_BP_ACK 0x4000 /* acknowledge */ -#define IX_ETH_MII_BP_NP 0x8000 /* nexp page is supported */ - -/* MII Next Page bit definitions */ - -#define IX_ETH_MII_NP_TOGGLE 0x0800 /* toggle bit */ -#define IX_ETH_MII_NP_ACK2 0x1000 /* acknowledge two */ -#define IX_ETH_MII_NP_MSG 0x2000 /* message page */ -#define IX_ETH_MII_NP_ACK1 0x4000 /* acknowledge one */ -#define IX_ETH_MII_NP_NP 0x8000 /* nexp page will follow */ - -/* MII Expansion Register bit definitions */ - -#define IX_ETH_MII_EXP_FAULT 0x0010 /* parallel detection fault */ -#define IX_ETH_MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */ -#define IX_ETH_MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */ -#define IX_ETH_MII_EXP_PR 0x0002 /* full page received */ -#define IX_ETH_MII_EXP_PRT_AN 0x0001 /* link partner auto neg able */ - -/* technology ability field bit definitions */ - -#define IX_ETH_MII_TECH_10BASE_T 0x0020 /* 10Base-T */ -#define IX_ETH_MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */ -#define IX_ETH_MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */ -#define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */ - -#define IX_ETH_MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */ -#define IX_ETH_MII_ADS_TECH_MASK 0x1fe0 /* technology abilities mask */ -#define IX_ETH_MII_TECH_MASK IX_ETH_MII_ADS_TECH_MASK -#define IX_ETH_MII_ADS_SEL_MASK 0x001f /* selector field mask */ - -#define IX_ETH_MII_AN_FAIL 0x10 /* auto-negotiation fail */ -#define IX_ETH_MII_STAT_FAIL 0x20 /* errors in the status register */ -#define IX_ETH_MII_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */ - -/* Definitions for MII access routines*/ - -#define IX_ETH_MII_GO BIT(31) -#define IX_ETH_MII_WRITE BIT(26) -#define IX_ETH_MII_TIMEOUT_10TH_SECS (5) -#define IX_ETH_MII_10TH_SEC_IN_MILLIS (100) -#define IX_ETH_MII_READ_FAIL BIT(31) - -/* When we reset the PHY we delay for 2 seconds to allow the reset to - complete*/ -#define IX_ETH_MII_RESET_DELAY_MS (2000) -#define IX_ETH_MII_RESET_POLL_MS (50) - -#define IX_ETH_MII_REG_SHL 16 -#define IX_ETH_MII_ADDR_SHL 21 - -/* supported PHYs */ -#define IX_ETH_MII_LXT971_PHY_ID 0x001378E0 -#define IX_ETH_MII_LXT972_PHY_ID 0x001378E2 -#define IX_ETH_MII_LXT973_PHY_ID 0x00137A10 -#define IX_ETH_MII_LXT973A3_PHY_ID 0x00137A11 -#define IX_ETH_MII_KS8995_PHY_ID 0x00221450 -#define IX_ETH_MII_LXT9785_PHY_ID 0x001378FF - - -#define IX_ETH_MII_INVALID_PHY_ID 0x00000000 -#define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff - -#endif /*IxEthAccMii_p_H*/ diff --git a/drivers/net/npe/include/IxEthNpe.h b/drivers/net/npe/include/IxEthNpe.h deleted file mode 100644 index 21bdedc5a7..0000000000 --- a/drivers/net/npe/include/IxEthNpe.h +++ /dev/null @@ -1,695 +0,0 @@ -#ifndef __doxygen_HIDE /* This file is not part of the API */ - -/** - * @file IxEthNpe.h - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxEthNpe IXP400 Ethernet NPE (IxEthNpe) API - * - * @brief Contains the API for Ethernet NPE. - * - * All messages given to NPE, get back an acknowledgment. The acknowledgment - * is identical to the message sent to the NPE (except for NPE_GETSTATUS message). - * - * @{ - */ - - -/*-------------------------------------------------------------------------- - * APB Message IDs - XScale->NPE - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_NPE_GETSTATUS - * - * @brief Request from the XScale client for the NPE to return the firmware - * version of the currently executing image. - * - * Acknowledgment message id is same as the request message id. - * NPE returns the firmware version ID to XScale. - */ -#define IX_ETHNPE_NPE_GETSTATUS 0x00 - -/** - * @def IX_ETHNPE_EDB_SETPORTADDRESS - * - * @brief Request from the XScale client for the NPE to set the Ethernet - * port's port ID and MAC address. - */ -#define IX_ETHNPE_EDB_SETPORTADDRESS 0x01 - -/** - * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE - * - * @brief Request from XScale client to the NPE requesting upload of - * Ethernet Filtering Database or Header Conversion Database from NPE's - * data memory to XScale accessible SDRAM. - */ -#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE 0x02 - -/** - * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE - * - * @brief Request from XScale client to the NPE requesting download of - * Ethernet Filtering Database or Header Conversion Database from SDRAM - * to the NPE's datamemory. - */ -#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE 0x03 - -/** - * @def IX_ETHNPE_GETSTATS - * - * @brief Request from the XScale client for the current MAC port statistics - * data to be written to the (empty) statistics structure and the specified - * location in externa memory. - */ -#define IX_ETHNPE_GETSTATS 0x04 - -/** - * @def IX_ETHNPE_RESETSTATS - * - * @brief Request from the XScale client to the NPE to reset all of its internal - * MAC port statistics state variables. - * - * As a side effect, this message entails an implicit request that the NPE - * write the current MAC port statistics into the MAC statistics structure - * at the specified location in external memory. - */ -#define IX_ETHNPE_RESETSTATS 0x05 - -/** - * @def IX_ETHNPE_SETMAXFRAMELENGTHS - * - * @brief Request from the XScale client to the NPE to configure maximum framelengths - * and block sizes in receive and transmit direction. - */ -#define IX_ETHNPE_SETMAXFRAMELENGTHS 0x06 - -/** - * @def IX_ETHNPE_VLAN_SETRXTAGMODE - * - * @brief Request from the XScale client to the NPE to configure VLAN frame type - * filtering and VLAN the tagging mode for the receiver. - */ -#define IX_ETHNPE_VLAN_SETRXTAGMODE 0x07 - -/** - * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID - * - * @brief Request from the XScale client to the NPE to set receiver's default - * VLAN tag (PVID)and internal traffic class. - */ -#define IX_ETHNPE_VLAN_SETDEFAULTRXVID 0x08 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY - * - * @brief Request from the XScale client to the NPE to configure VLAN Port - * membership and Tx tagging for 8 consecutive VLANID's. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY 0x09 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE - * - * @brief Request from the XScale client to the NPE to configure VLAN Port - * membership and Tx tagging for a range of VLANID's. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE 0x0A - -/** - * @def IX_ETHNPE_VLAN_SETRXQOSENTRY - * - * @brief Request from the XScale client to the NPE to map a user priority - * to QoS class and an AQM queue number. - */ -#define IX_ETHNPE_VLAN_SETRXQOSENTRY 0x0B - -/** - * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE - * - * @brief Request from the XScale client to the NPE to enable or disable - * portID extraction from VLAN-tagged frames for the specified port. - */ -#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C - -/** - * @def IX_ETHNPE_STP_SETBLOCKINGSTATE - * - * @brief Request from the XScale client to the NPE to block or unblock - * forwarding for spanning tree BPDUs. - */ -#define IX_ETHNPE_STP_SETBLOCKINGSTATE 0x0D - -/** - * @def IX_ETHNPE_FW_SETFIREWALLMODE - * - * @brief Request from the XScale client to the NPE to configure firewall - * services modes of operation and/or download Ethernet Firewall Database from - * SDRAM to NPE. - */ -#define IX_ETHNPE_FW_SETFIREWALLMODE 0x0E - -/** - * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID - * - * @brief Request from the XScale client to the NPE to set global frame control - * and duration/ID field for the 802.3 to 802.11 protocol header conversion - * service. - */ -#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID 0x0F - -/** - * @def IX_ETHNPE_PC_SETBBSID - * - * @brief Request from the XScale client to the NPE to set global BBSID field - * value for the 802.3 to 802.11 protocol header conversion service. - */ -#define IX_ETHNPE_PC_SETBBSID 0x10 - -/** - * @def IX_ETHNPE_PC_SETAPMACTABLE - * - * @brief Request from the XScale client to the NPE to update a block/section/ - * range of the AP MAC Address Table. - */ -#define IX_ETHNPE_PC_SETAPMACTABLE 0x11 - -/** - * @def IX_ETHNPE_SETLOOPBACK_MODE - * - * @brief Turn on or off the NPE frame loopback. - */ -#define IX_ETHNPE_SETLOOPBACK_MODE (0x12) - -/*-------------------------------------------------------------------------- - * APB Message IDs - NPE->XScale - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_NPE_GETSTATUS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_NPE_GETSTATUS message. NPE firmware version - * id is returned in the message. - */ -#define IX_ETHNPE_NPE_GETSTATUS_ACK 0x00 - -/** - * @def IX_ETHNPE_EDB_SETPORTADDRESS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_SETPORTADDRESS message. - */ -#define IX_ETHNPE_EDB_SETPORTADDRESS_ACK 0x01 - -/** - * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_GETMACADDRESSDATABASE message - */ -#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK 0x02 - -/** - * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_SETMACADDRESSSDATABASE message. - */ -#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK 0x03 - -/** - * @def IX_ETHNPE_GETSTATS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_GETSTATS message. - */ -#define IX_ETHNPE_GETSTATS_ACK 0x04 - -/** - * @def IX_ETHNPE_RESETSTATS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_RESETSTATS message. - */ -#define IX_ETHNPE_RESETSTATS_ACK 0x05 - -/** - * @def IX_ETHNPE_SETMAXFRAMELENGTHS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_SETMAXFRAMELENGTHS message. - */ -#define IX_ETHNPE_SETMAXFRAMELENGTHS_ACK 0x06 - -/** - * @def IX_ETHNPE_VLAN_SETRXTAGMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXTAGMODE message. - */ -#define IX_ETHNPE_VLAN_SETRXTAGMODE_ACK 0x07 - -/** - * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETDEFAULTRXVID message. - */ -#define IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK 0x08 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY message. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK 0x09 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE message. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK 0x0A - -/** - * @def IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXQOSENTRY message. - */ -#define IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK 0x0B - -/** - * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE message. - */ -#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK 0x0C - -/** - * @def IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_STP_SETBLOCKINGSTATE message. - */ -#define IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK 0x0D - -/** - * @def IX_ETHNPE_FW_SETFIREWALLMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_FW_SETFIREWALLMODE message. - */ -#define IX_ETHNPE_FW_SETFIREWALLMODE_ACK 0x0E - -/** - * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID message. - */ -#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK 0x0F - -/** - * @def IX_ETHNPE_PC_SETBBSID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETBBSID message. - */ -#define IX_ETHNPE_PC_SETBBSID_ACK 0x10 - -/** - * @def IX_ETHNPE_PC_SETAPMACTABLE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETAPMACTABLE message. - */ -#define IX_ETHNPE_PC_SETAPMACTABLE_ACK 0x11 - -/** - * @def IX_ETHNPE_SETLOOPBACK_MODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_SETLOOPBACK_MODE message. - */ -#define IX_ETHNPE_SETLOOPBACK_MODE_ACK (0x12) - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field boundary definitions - *------------------------------------------------------------------------*/ - -/** - * @def MASK(hi,lo) - * - * @brief Macro for mask - */ -#define MASK(hi,lo) (((1 << (1 + ((hi) - (lo)))) - 1) << (lo)) - -/** - * @def BITS(x,hi,lo) - * - * @brief Macro for bits - */ -#define BITS(x,hi,lo) (((x) & MASK(hi,lo)) >> (lo)) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK - * - * @brief QMgr Queue LENGTH field mask - */ -#define IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK 0x3fff - -/** - * @def IX_ETHNPE_QM_Q_FIELD_FLAG_R - * - * @brief QMgr Queue FLAG field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_FLAG_R 20 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_FLAG_MASK - * - * @brief QMgr Queue FLAG field mask - * - * Multicast bit : BIT(4) - * Broadcast bit : BIT(5) - * IP bit : BIT(6) (linux only) - * - */ -#ifdef __vxworks -#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x30 -#else -#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x70 -#endif - - -/** - * @def IX_ETHNPE_QM_Q_FIELD_NPEID_L - * - * @brief QMgr Queue NPE ID field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_NPEID_L 1 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_NPEID_R - * - * @brief QMgr Queue NPE ID field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_NPEID_R 0 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_L - * - * @brief QMgr Queue Priority field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_PRIOR_L 2 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_R - * - * @brief QMgr Queue Priority field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_PRIOR_R 0 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_ADDR_L - * - * @brief QMgr Queue Address field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_ADDR_L 31 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_ADDR_R - * - * @brief QMgr Queue Address field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_ADDR_R 5 - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field masks - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK - * - * @brief Macro to mask the Address field of the FreeEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_NPEID_MASK - * - * @brief Macro to mask the NPE ID field of the RxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_RXENET_NPEID_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the RxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_RXENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK - * - * @brief Macro to mask the Priority field of the TxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \ - IX_ETHNPE_QM_Q_FIELD_PRIOR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the TxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK - * - * @brief Macro to mask the NPE ID field of the TxEnetDone Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the TxEnetDone Queue Manager - * Entry - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field value extraction macros - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of FreeNet Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) - * - * @brief Extraction macro for NPE ID field of RxEnet Queue Manager Entry - * - * Set to 0 for entries originating from the Eth0 NPE; - * Set to 1 for entries originating from the Eth1 NPE. - */ -#define IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) - * - * @brief Extraction macro for Port ID field of RxEnet Queue Manager Entry - * - * 0-5: Assignable (by the XScale client) to any of the physical ports. - * 6: It is reserved - * 7: Indication that the NPE did not find the associated frame's destination MAC address within - * its internal filtering database. - */ -#define IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_PORTID_L, \ - IX_ETHNPE_QM_Q_Field_PortID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of RxEnet Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) - * - * @brief Extraction macro for Priority field of TxEnet Queue Manager Entry - * - * Priority of the packet (as described in IEEE 802.1D). This field is - * cleared upon return from the Ethernet NPE to the TxEnetDone queue. - */ -#define IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \ - IX_ETHNPE_QM_Q_FIELD_PRIOR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of Queue Manager TxEnet Queue - * Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) - * - * @brief Extraction macro for NPE ID field of TxEnetDone Queue Manager Entry - * - * Set to 0 for entries originating from the Eth0 NPE; set to 1 for en-tries - * originating from the Eth1 NPE. - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of TxEnetDone Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK) - - -/*-------------------------------------------------------------------------- - * NPE limits - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN - * - * @brief Macro to check the minimum length of a rx free buffer - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN (64) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK - * - * @brief Mask to apply to the mbuf length before submitting it to the NPE - * (the NPE handles only rx free mbufs which are multiple of 64) - * - * @sa IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK (~63) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) - * - * @brief Round up to get the size necessary to receive without chaining - * the frames which are (size) bytes (the NPE operates by multiple of 64) - * e.g. To receive 1514 bytes frames, the size of the buffers in replenish - * has to be at least (1514+63)&(~63) = 1536 bytes. - * - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) (((size) + 63) & ~63) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) - * - * @brief Round down to apply to the mbuf length before submitting - * it to the NPE. (the NPE operates by multiple of 64) - * - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) ((size) & ~63) - -/** - * @def IX_ETHNPE_ACC_FRAME_LENGTH_MAX - * - * @brief maximum mbuf length supported by the NPE - * - * @sa IX_ETHNPE_ACC_FRAME_LENGTH_MAX - */ -#define IX_ETHNPE_ACC_FRAME_LENGTH_MAX (16320) - -/** - * @def IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT - * - * @brief default mbuf length supported by the NPE - * - * @sa IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT - */ -#define IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT (1522) - -/** - * @def IX_ETHNPE_ACC_LENGTH_OFFSET - * - * @brief Offset of the cluster length field in the word shared with the NPEs - */ -#define IX_ETHNPE_ACC_LENGTH_OFFSET 16 - -/** - * @def IX_ETHNPE_ACC_PKTLENGTH_MASK - * - * @brief Mask of the cluster length field in the word shared with the NPEs - */ -#define IX_ETHNPE_ACC_PKTLENGTH_MASK 0x3fff - - -/** - *@} - */ - -#endif /* __doxygen_HIDE */ diff --git a/drivers/net/npe/include/IxFeatureCtrl.h b/drivers/net/npe/include/IxFeatureCtrl.h deleted file mode 100644 index 1662a00139..0000000000 --- a/drivers/net/npe/include/IxFeatureCtrl.h +++ /dev/null @@ -1,742 +0,0 @@ -/** - * @file IxFeatureCtrl.h - * - * @date 30-Jan-2003 - - * @brief This file contains the public API of the IXP400 Feature Control - * component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxFeatureCtrlAPI IXP400 Feature Control (IxFeatureCtrl) API - * - * @brief The Public API for the IXP400 Feature Control. - * - * @{ - */ - -#ifndef IXFEATURECTRL_H -#define IXFEATURECTRL_H - -/* - * User defined include files - */ -#include "IxOsal.h" - -/* - * #defines and macros - */ - -/************************************************************* - * The following are IxFeatureCtrlComponentCheck return values. - ************************************************************/ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_COMPONENT_DISABLED - * - * @brief Hardware Component is disabled/unavailable. - * Return status by ixFeatureCtrlComponentCheck() - */ -#define IX_FEATURE_CTRL_COMPONENT_DISABLED 0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_COMPONENT_ENABLED - * - * @brief Hardware Component is available. - * Return status by ixFeatureCtrlComponentCheck() - */ -#define IX_FEATURE_CTRL_COMPONENT_ENABLED 1 - -/*********************************************************************************** - * Product ID in XScale CP15 - Register 0 - * - It contains information on the maximum XScale Core Frequency and - * Silicon Stepping. - * - XScale Core Frequency Id indicates only the maximum XScale frequency - * achievable and not the running XScale frequency (maybe stepped down). - * - The register is read by using ixFeatureCtrlProductIdRead. - * - Usage example: - * productId = ixFeatureCtrlProductIdRead(); - * if( (productId & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) == - * IX_FEATURE_CTRL_SILICON_TYPE_A0 ) - * if( (productId & IX_FEATURE_CTRL_XSCALE_FREQ_MASK) == - * IX_FEATURE_CTRL_XSCALE_FREQ_533 ) - * - * 31 28 27 24 23 20 19 16 15 12 11 9 8 4 3 0 - * -------------------------------------------------------------------------------- - * | 0x6 | 0x9 | 0x0 | 0x5 | 0x4 | Device ID | XScale Core Freq Id | Si Stepping Id | - * -------------------------------------------------------------------------------- - * - * Maximum Achievable XScale Core Frequency Id : 533MHz - 0x1C - * 400MHz - 0x1D - * 266MHz - 0x1F - * - * THE CORE FREQUENCY ID IS NOT APPLICABLE TO IXP46X <\b> - * - * The above is applicable to IXP42X only. CP15 in IXP46X does not contain any - * Frequency ID. - * - * Si Stepping Id : A - 0x0 - * B - 0x1 - * - * XScale Core freq Id - Device ID [11:9] : IXP42X - 0x0 - * IXP46X - 0x1 - *************************************************************************************/ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_TYPE_A0 - * - * @brief This is the value of A0 Silicon in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_TYPE_A0 0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_TYPE_B0 - * - * @brief This is the value of B0 Silicon in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_TYPE_B0 1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_STEPPING_MASK - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_STEPPING_MASK 0xF - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_DEVICE_TYPE_MASK - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_DEVICE_TYPE_MASK (0x7) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET 9 - - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_533 - * - * @brief This is the value of 533MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_533 ((0x1C)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_400 - * - * @brief This is the value of 400MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_400 ((0x1D)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_266 - * - * @brief This is the value of 266MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_266 ((0x1F)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_MASK - * - * @brief This is the mask of XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_MASK ((0xFF)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_32PHY - * - * @brief Maximum UTOPIA PHY available is 32. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_32PHY 0x0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_16PHY - * - * @brief Maximum UTOPIA PHY available is 16. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_16PHY 0x1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_8PHY - * - * @brief Maximum UTOPIA PHY available to is 8. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_8PHY 0x2 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_4PHY - * - * @brief Maximum UTOPIA PHY available to is 4. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_4PHY 0x3 - -#ifdef __ixp46X - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_533FREQ - * - * @brief Maximum frequency available to IXP46x is 533 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_533FREQ 0x0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_667FREQ - * - * @brief Maximum frequency available to IXP46x is 667 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_667FREQ 0x1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_400FREQ - * - * @brief Maximum frequency available to IXP46x is 400 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_400FREQ 0x2 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_266FREQ - * - * @brief Maximum frequency available to IXP46x is 266 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_266FREQ 0x3 - -#endif /* __ixp46X */ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE - * - * @brief Component selected is not available for device - * - */ -#define IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE 0x0000 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE - * - * @brief Component selected is not available for device - * - */ -#define IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE 0xffff - -/** - * @defgroup IxFeatureCtrlSwConfig Software Configuration for Access Component - * - * @ingroup IxFeatureCtrlAPI - * - * @brief This section describes software configuration in access component. The - * configuration can be changed at run-time. ixFeatureCtrlSwConfigurationCheck( ) - * will be used across applicable access component to check the configuration. - * ixFeatureCtrlSwConfigurationWrite( ) is used to write the software configuration. - * - * @note All software configurations are default to be enabled. - * - * @{ - */ -/** - * @ingroup IxFeatureCtrlSwConfig - * - * @def IX_FEATURE_CTRL_SWCONFIG_DISABLED - * - * @brief Software configuration is disabled. - * - */ -#define IX_FEATURE_CTRL_SWCONFIG_DISABLED 0 - -/** - * @ingroup IxFeatureCtrlSwConfig - * - * @def IX_FEATURE_CTRL_SWCONFIG_ENABLED - * - * @brief Software configuration is enabled. - * - */ -#define IX_FEATURE_CTRL_SWCONFIG_ENABLED 1 - -/** - * Section for enums - **/ - -/** - * @ingroup IxFeatureCtrlBuildDevice - * - * @enum IxFeatureCtrlBuildDevice - * - * @brief Indicates software build type. - * - * Default build type is IXP42X - * - */ -typedef enum -{ - IX_FEATURE_CTRL_SW_BUILD_IXP42X = 0, /** - * - if(IX_FEATURE_CTRL_COMPONENT_DISABLED != - * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0))
- * - if(IX_FEATURE_CTRL_COMPONENT_ENABLED == - * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_PCI))
- * - * This function is typically called during component initialization time. - * - * @param componentType @ref IxFeatureCtrlComponentType [in] - the type of a component as - * defined above as IX_FEATURECTRL_XXX (Exp: IX_FEATURECTRL_PCI, IX_FEATURECTRL_ETH0) - - * - * @return - * - IX_FEATURE_CTRL_COMPONENT_ENABLED if component is available - * - IX_FEATURE_CTRL_COMPONENT_DISABLED if component is unavailable - */ -PUBLIC IX_STATUS -ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn IxFeatureCtrlProductId ixFeatureCtrlProductIdRead (void) - * - * @brief This function will return IXP400 product ID i.e. CP15, - * Register 0. - * - * @return - * - IxFeatureCtrlProductId - the value of product ID. - * - */ -PUBLIC IxFeatureCtrlProductId -ixFeatureCtrlProductIdRead (void) ; - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn IX_STATUS ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType) - * - * @brief This function checks whether the specified software configuration is - * enabled or disabled. - * - * Usage Example:
- * - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED != - * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- * - if(IX_FEATURE_CTRL_SWCONFIG_ENABLED == - * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- * - * This function is typically called during access component initialization time. - * - * @param swConfigType @ref IxFeatureCtrlSwConfig [in] - the type of a software configuration - * defined in IxFeatureCtrlSwConfig enumeration. - * - * @return - * - IX_FEATURE_CTRL_SWCONFIG_ENABLED if software configuration is enabled. - * - IX_FEATURE_CTRL_SWCONFIG_DISABLED if software configuration is disabled. - */ -PUBLIC IX_STATUS -ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn void ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled) - * - * @brief This function enable/disable the specified software configuration. - * - * Usage Example:
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, true) is used - * to enable Ethernet Learning Feature
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false) is used - * to disable Ethernet Learning Feature
- * - * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration - * defined in IxFeatureCtrlSwConfig enumeration. - * @param enabled BOOL [in] - To enable(true) / disable (false) the specified software - * configuration. - * - * @return none - * - */ -PUBLIC void -ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn void ixFeatureCtrlIxp400SwVersionShow (void) - * - * @brief This function shows the current software release information for IXP400 - * - * @return none - * - */ -PUBLIC void -ixFeatureCtrlIxp400SwVersionShow (void); - -#endif /* IXFEATURECTRL_H */ - -/** - * @} defgroup IxFeatureCtrlAPI - */ diff --git a/drivers/net/npe/include/IxHssAcc.h b/drivers/net/npe/include/IxHssAcc.h deleted file mode 100644 index 52d5716f72..0000000000 --- a/drivers/net/npe/include/IxHssAcc.h +++ /dev/null @@ -1,1316 +0,0 @@ -/** - * @file IxHssAcc.h - * - * @date 07-DEC-2001 - * - * @brief This file contains the public API of the IXP400 HSS Access - * component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxHssAccAPI IXP400 HSS Access (IxHssAcc) API - * - * @brief The public API for the IXP400 HssAccess component - * - * IxHssAcc is the access layer to the HSS packetised and channelised - * services - * - * Design Notes
- *
    - *
  • When a packet-pipe is configured for 56Kbps RAW mode, byte alignment of - * the transmitted data is not preserved. All raw data that is transmitted - * will be received in proper order by the receiver, but the first bit of - * the packet may be seen at any offset within a byte; all subsequent bytes - * will have the same offset for the duration of the packet. The same offset - * also applies to all subsequent packets received on the packet-pipe too. - * (Similar results will occur for data received from remote end.) While - * this behavior will also occur for 56Kbps HDLC mode, the HDLC - * encoding/decoding will preserve the original byte alignment at the - * receiver end. - *
- * - * 56Kbps Packetised Service Bandwidth Limitation
- *
    - *
  • IxHssAcc supports 56Kbps packetised service at a maximum aggregate rate - * for all HSS ports/HDLC channels of 12.288Mbps[1] in each direction, i.e. - * it supports 56Kbps packetised service on up to 8 T1 trunks. It does - * not support 56Kbps packetised service on 8 E1 trunks (i.e. 4 trunks per - * HSS port) unless those trunks are running 'fractional E1' with maximum - * aggregate rate of 12.288 Mbps in each direction.
    - * [1] 12.288Mbps = 1.536Mbp * 8 T1 - *
- * @{ */ - -#ifndef IXHSSACC_H -#define IXHSSACC_H - -#include "IxOsal.h" - -/* - * #defines for function return types, etc. - */ - -/** - * @def IX_HSSACC_TSLOTS_PER_HSS_PORT - * - * @brief The max number of TDM timeslots supported per HSS port - 4E1's = - * 32x4 = 128 - */ -#define IX_HSSACC_TSLOTS_PER_HSS_PORT 128 - -/* ----------------------------------------------------------- - The following are HssAccess return values returned through - service interfaces. The globally defined IX_SUCCESS (0) and - IX_FAIL (1) in IxOsalTypes.h are also used. - ----------------------------------------------------------- */ -/** - * @def IX_HSSACC_PARAM_ERR - * - * @brief HssAccess function return value for a parameter error - */ -#define IX_HSSACC_PARAM_ERR 2 - -/** - * @def IX_HSSACC_RESOURCE_ERR - * - * @brief HssAccess function return value for a resource error - */ -#define IX_HSSACC_RESOURCE_ERR 3 - -/** - * @def IX_HSSACC_PKT_DISCONNECTING - * - * @brief Indicates that a disconnect call is progressing and will - * disconnect soon - */ -#define IX_HSSACC_PKT_DISCONNECTING 4 - -/** - * @def IX_HSSACC_Q_WRITE_OVERFLOW - * - * @brief Indicates that an attempt to Tx or to replenish an - * RxFree Q failed due to Q overflow. - */ -#define IX_HSSACC_Q_WRITE_OVERFLOW 5 - -/* ------------------------------------------------------------------- - The following errors are HSS/NPE errors returned on error retrieval - ------------------------------------------------------------------- */ -/** - * @def IX_HSSACC_NO_ERROR - * - * @brief HSS port no error present - */ -#define IX_HSSACC_NO_ERROR 0 - -/** - * @def IX_HSSACC_TX_FRM_SYNC_ERR - * - * @brief HSS port TX Frame Sync error - */ -#define IX_HSSACC_TX_FRM_SYNC_ERR 1 - -/** - * @def IX_HSSACC_TX_OVER_RUN_ERR - * - * @brief HSS port TX over-run error - */ -#define IX_HSSACC_TX_OVER_RUN_ERR 2 - -/** - * @def IX_HSSACC_CHANNELISED_SW_TX_ERR - * - * @brief NPE software error in channelised TX - */ -#define IX_HSSACC_CHANNELISED_SW_TX_ERR 3 - -/** - * @def IX_HSSACC_PACKETISED_SW_TX_ERR - * - * @brief NPE software error in packetised TX - */ -#define IX_HSSACC_PACKETISED_SW_TX_ERR 4 - -/** - * @def IX_HSSACC_RX_FRM_SYNC_ERR - * - * @brief HSS port RX Frame Sync error - */ -#define IX_HSSACC_RX_FRM_SYNC_ERR 5 - -/** - * @def IX_HSSACC_RX_OVER_RUN_ERR - * - * @brief HSS port RX over-run error - */ -#define IX_HSSACC_RX_OVER_RUN_ERR 6 - -/** - * @def IX_HSSACC_CHANNELISED_SW_RX_ERR - * - * @brief NPE software error in channelised RX - */ -#define IX_HSSACC_CHANNELISED_SW_RX_ERR 7 - -/** - * @def IX_HSSACC_PACKETISED_SW_RX_ERR - * - * @brief NPE software error in packetised TX - */ -#define IX_HSSACC_PACKETISED_SW_RX_ERR 8 - -/* ----------------------------------- - Packetised service specific defines - ----------------------------------- */ - -/** - * @def IX_HSSACC_PKT_MIN_RX_MBUF_SIZE - * - * @brief Minimum size of the Rx mbuf in bytes which the client must supply - * to the component. - */ -#define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64 - -/* -------------------------------------------------------------------- - Enumerated Types - these enumerated values may be used in setting up - the contents of hardware registers - -------------------------------------------------------------------- */ -/** - * @enum IxHssAccHssPort - * @brief The HSS port ID - There are two identical ports (0-1). - * - */ -typedef enum -{ - IX_HSSACC_HSS_PORT_0, /**< HSS Port 0 */ - IX_HSSACC_HSS_PORT_1, /**< HSS Port 1 */ - IX_HSSACC_HSS_PORT_MAX /**< Delimiter for error checks */ -} IxHssAccHssPort; - -/** - * @enum IxHssAccHdlcPort - * @brief The HDLC port ID - There are four identical HDLC ports (0-3) per - * HSS port and they correspond to the 4 E1/T1 trunks. - * - */ -typedef enum -{ - IX_HSSACC_HDLC_PORT_0, /**< HDLC Port 0 */ - IX_HSSACC_HDLC_PORT_1, /**< HDLC Port 1 */ - IX_HSSACC_HDLC_PORT_2, /**< HDLC Port 2 */ - IX_HSSACC_HDLC_PORT_3, /**< HDLC Port 3 */ - IX_HSSACC_HDLC_PORT_MAX /**< Delimiter for error checks */ -} IxHssAccHdlcPort; - -/** - * @enum IxHssAccTdmSlotUsage - * @brief The HSS TDM stream timeslot assignment types - * - */ -typedef enum -{ - IX_HSSACC_TDMMAP_UNASSIGNED, /**< Unassigned */ - IX_HSSACC_TDMMAP_HDLC, /**< HDLC - packetised */ - IX_HSSACC_TDMMAP_VOICE56K, /**< Voice56K - channelised */ - IX_HSSACC_TDMMAP_VOICE64K, /**< Voice64K - channelised */ - IX_HSSACC_TDMMAP_MAX /**< Delimiter for error checks */ -} IxHssAccTdmSlotUsage; - -/** - * @enum IxHssAccFrmSyncType - * @brief The HSS frame sync pulse type - * - */ -typedef enum -{ - IX_HSSACC_FRM_SYNC_ACTIVE_LOW, /**< Frame sync is sampled low */ - IX_HSSACC_FRM_SYNC_ACTIVE_HIGH, /**< sampled high */ - IX_HSSACC_FRM_SYNC_FALLINGEDGE, /**< sampled on a falling edge */ - IX_HSSACC_FRM_SYNC_RISINGEDGE, /**< sampled on a rising edge */ - IX_HSSACC_FRM_SYNC_TYPE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmSyncType; - -/** - * @enum IxHssAccFrmSyncEnable - * @brief The IxHssAccFrmSyncEnable determines how the frame sync pulse is - * used - * */ -typedef enum -{ - IX_HSSACC_FRM_SYNC_INPUT, /**< Frame sync is sampled as an input */ - IX_HSSACC_FRM_SYNC_INVALID_VALUE, /**< 1 is not used */ - IX_HSSACC_FRM_SYNC_OUTPUT_FALLING, /**< Frame sync is an output generated - off a falling clock edge */ - IX_HSSACC_FRM_SYNC_OUTPUT_RISING, /**< Frame sync is an output generated - off a rising clock edge */ - IX_HSSACC_FRM_SYNC_ENABLE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmSyncEnable; - -/** - * @enum IxHssAccClkEdge - * @brief IxHssAccClkEdge is used to determine the clk edge to use for - * framing and data - * - */ -typedef enum -{ - IX_HSSACC_CLK_EDGE_FALLING, /**< Clock sampled off a falling edge */ - IX_HSSACC_CLK_EDGE_RISING, /**< Clock sampled off a rising edge */ - IX_HSSACC_CLK_EDGE_MAX /**< Delimiter for error checks */ -} IxHssAccClkEdge; - -/** - * @enum IxHssAccClkDir - * @brief The HSS clock direction - * - */ -typedef enum -{ - IX_HSSACC_SYNC_CLK_DIR_INPUT, /**< Clock is an input */ - IX_HSSACC_SYNC_CLK_DIR_OUTPUT, /**< Clock is an output */ - IX_HSSACC_SYNC_CLK_DIR_MAX /**< Delimiter for error checks */ -} IxHssAccClkDir; - -/** - * @enum IxHssAccFrmPulseUsage - * @brief The HSS frame pulse usage - * - */ -typedef enum -{ - IX_HSSACC_FRM_PULSE_ENABLED, /**< Generate/Receive frame pulses */ - IX_HSSACC_FRM_PULSE_DISABLED, /**< Disregard frame pulses */ - IX_HSSACC_FRM_PULSE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmPulseUsage; - -/** - * @enum IxHssAccDataRate - * @brief The HSS Data rate in relation to the clock - * - */ -typedef enum -{ - IX_HSSACC_CLK_RATE, /**< Data rate is at the configured clk speed */ - IX_HSSACC_HALF_CLK_RATE, /**< Data rate is half the configured clk speed */ - IX_HSSACC_DATA_RATE_MAX /**< Delimiter for error checks */ -} IxHssAccDataRate; - -/** - * @enum IxHssAccDataPolarity - * @brief The HSS data polarity type - * - */ -typedef enum -{ - IX_HSSACC_DATA_POLARITY_SAME, /**< Don't invert data between NPE and - HSS FIFOs */ - IX_HSSACC_DATA_POLARITY_INVERT, /**< Invert data between NPE and HSS - FIFOs */ - IX_HSSACC_DATA_POLARITY_MAX /**< Delimiter for error checks */ -} IxHssAccDataPolarity; - -/** - * @enum IxHssAccBitEndian - * @brief HSS Data endianness - * - */ -typedef enum -{ - IX_HSSACC_LSB_ENDIAN, /**< TX/RX Least Significant Bit first */ - IX_HSSACC_MSB_ENDIAN, /**< TX/RX Most Significant Bit first */ - IX_HSSACC_ENDIAN_MAX /**< Delimiter for the purposes of error checks */ -} IxHssAccBitEndian; - - -/** - * @enum IxHssAccDrainMode - * @brief Tx pin open drain mode - * - */ -typedef enum -{ - IX_HSSACC_TX_PINS_NORMAL, /**< Normal mode */ - IX_HSSACC_TX_PINS_OPEN_DRAIN, /**< Open Drain mode */ - IX_HSSACC_TX_PINS_MAX /**< Delimiter for error checks */ -} IxHssAccDrainMode; - -/** - * @enum IxHssAccSOFType - * @brief HSS start of frame types - * - */ -typedef enum -{ - IX_HSSACC_SOF_FBIT, /**< Framing bit transmitted and expected on rx */ - IX_HSSACC_SOF_DATA, /**< Framing bit not transmitted nor expected on rx */ - IX_HSSACC_SOF_MAX /**< Delimiter for error checks */ -} IxHssAccSOFType; - -/** - * @enum IxHssAccDataEnable - * @brief IxHssAccDataEnable is used to determine whether or not to drive - * the data pins - * - */ -typedef enum -{ - IX_HSSACC_DE_TRI_STATE, /**< TRI-State the data pins */ - IX_HSSACC_DE_DATA, /**< Push data out the data pins */ - IX_HSSACC_DE_MAX /**< Delimiter for error checks */ -} IxHssAccDataEnable; - -/** - * @enum IxHssAccTxSigType - * @brief IxHssAccTxSigType is used to determine how to drive the data pins - * - */ -typedef enum -{ - IX_HSSACC_TXSIG_LOW, /**< Drive the data pins low */ - IX_HSSACC_TXSIG_HIGH, /**< Drive the data pins high */ - IX_HSSACC_TXSIG_HIGH_IMP, /**< Drive the data pins with high impedance */ - IX_HSSACC_TXSIG_MAX /**< Delimiter for error checks */ -} IxHssAccTxSigType; - -/** - * @enum IxHssAccFbType - * @brief IxHssAccFbType determines how to drive the Fbit - * - * @warning This will only be used for T1 @ 1.544MHz - * - */ -typedef enum -{ - IX_HSSACC_FB_FIFO, /**< Fbit is dictated in FIFO */ - IX_HSSACC_FB_HIGH_IMP, /**< Fbit is high impedance */ - IX_HSSACC_FB_MAX /**< Delimiter for error checks */ -} IxHssAccFbType; - -/** - * @enum IxHssAcc56kEndianness - * @brief 56k data endianness when using the 56k type - * - */ -typedef enum -{ - IX_HSSACC_56KE_BIT_7_UNUSED, /**< High bit is unused */ - IX_HSSACC_56KE_BIT_0_UNUSED, /**< Low bit is unused */ - IX_HSSACC_56KE_MAX /**< Delimiter for error checks */ -} IxHssAcc56kEndianness; - -/** - * @enum IxHssAcc56kSel - * @brief 56k data transmission type when using the 56k type - * - */ -typedef enum -{ - IX_HSSACC_56KS_32_8_DATA, /**< 32/8 bit data */ - IX_HSSACC_56KS_56K_DATA, /**< 56K data */ - IX_HSSACC_56KS_MAX /**< Delimiter for error checks */ -} IxHssAcc56kSel; - - -/** - * @enum IxHssAccClkSpeed - * @brief IxHssAccClkSpeed represents the HSS clock speeds available - * - */ -typedef enum -{ - IX_HSSACC_CLK_SPEED_512KHZ, /**< 512KHz */ - IX_HSSACC_CLK_SPEED_1536KHZ, /**< 1.536MHz */ - IX_HSSACC_CLK_SPEED_1544KHZ, /**< 1.544MHz */ - IX_HSSACC_CLK_SPEED_2048KHZ, /**< 2.048MHz */ - IX_HSSACC_CLK_SPEED_4096KHZ, /**< 4.096MHz */ - IX_HSSACC_CLK_SPEED_8192KHZ, /**< 8.192MHz */ - IX_HSSACC_CLK_SPEED_MAX /**< Delimiter for error checking */ -} IxHssAccClkSpeed; - -/** - * @enum IxHssAccPktStatus - * @brief Indicates the status of packets passed to the client - * - */ -typedef enum -{ - IX_HSSACC_PKT_OK, /**< Error free.*/ - IX_HSSACC_STOP_SHUTDOWN_ERROR, /**< Errored due to stop or shutdown - occurrance.*/ - IX_HSSACC_HDLC_ALN_ERROR, /**< HDLC alignment error */ - IX_HSSACC_HDLC_FCS_ERROR, /**< HDLC Frame Check Sum error.*/ - IX_HSSACC_RXFREE_Q_EMPTY_ERROR, /**< RxFree Q became empty - while receiving this packet.*/ - IX_HSSACC_HDLC_MAX_FRAME_SIZE_EXCEEDED, /**< HDLC frame size - received is greater than - max specified at connect.*/ - IX_HSSACC_HDLC_ABORT_ERROR, /**< HDLC frame received is invalid due to an - abort sequence received.*/ - IX_HSSACC_DISCONNECT_IN_PROGRESS /**< Packet returned - because a disconnect is in progress */ -} IxHssAccPktStatus; - - -/** - * @enum IxHssAccPktCrcType - * @brief HDLC CRC type - * - */ -typedef enum -{ - IX_HSSACC_PKT_16_BIT_CRC = 16, /**< 16 bit CRC is being used */ - IX_HSSACC_PKT_32_BIT_CRC = 32 /**< 32 bit CRC is being used */ -} IxHssAccPktCrcType; - -/** - * @enum IxHssAccPktHdlcIdleType - * @brief HDLC idle transmission type - * - */ -typedef enum -{ - IX_HSSACC_HDLC_IDLE_ONES, /**< idle tx/rx will be a succession of ones */ - IX_HSSACC_HDLC_IDLE_FLAGS /**< idle tx/rx will be repeated flags */ -} IxHssAccPktHdlcIdleType; - -/** - * @brief Structure containing HSS port configuration parameters - * - * Note: All of these are used for TX. Only some are specific to RX. - * - */ -typedef struct -{ - IxHssAccFrmSyncType frmSyncType; /**< frame sync pulse type (tx/rx) */ - IxHssAccFrmSyncEnable frmSyncIO; /**< how the frame sync pulse is - used (tx/rx) */ - IxHssAccClkEdge frmSyncClkEdge; /**< frame sync clock edge type - (tx/rx) */ - IxHssAccClkEdge dataClkEdge; /**< data clock edge type (tx/rx) */ - IxHssAccClkDir clkDirection; /**< clock direction (tx/rx) */ - IxHssAccFrmPulseUsage frmPulseUsage; /**< whether to use the frame sync - pulse or not (tx/rx) */ - IxHssAccDataRate dataRate; /**< data rate in relation to the - clock (tx/rx) */ - IxHssAccDataPolarity dataPolarity; /**< data polarity type (tx/rx) */ - IxHssAccBitEndian dataEndianness; /**< data endianness (tx/rx) */ - IxHssAccDrainMode drainMode; /**< tx pin open drain mode (tx) */ - IxHssAccSOFType fBitUsage; /**< start of frame types (tx/rx) */ - IxHssAccDataEnable dataEnable; /**< whether or not to drive the data - pins (tx) */ - IxHssAccTxSigType voice56kType; /**< how to drive the data pins for - voice56k type (tx) */ - IxHssAccTxSigType unassignedType; /**< how to drive the data pins for - unassigned type (tx) */ - IxHssAccFbType fBitType; /**< how to drive the Fbit (tx) */ - IxHssAcc56kEndianness voice56kEndian;/**< 56k data endianness when using - the 56k type (tx) */ - IxHssAcc56kSel voice56kSel; /**< 56k data transmission type when - using the 56k type (tx) */ - unsigned frmOffset; /**< frame pulse offset in bits wrt - the first timeslot (0-1023) (tx/rx) */ - unsigned maxFrmSize; /**< frame size in bits (1-1024) - (tx/rx) */ -} IxHssAccPortConfig; - -/** - * @brief Structure containing HSS configuration parameters - * - */ -typedef struct -{ - IxHssAccPortConfig txPortConfig; /**< HSS tx port configuration */ - IxHssAccPortConfig rxPortConfig; /**< HSS rx port configuration */ - unsigned numChannelised; /**< The number of channelised - timeslots (0-32) */ - unsigned hssPktChannelCount; /**< The number of packetised - clients (0 - 4) */ - UINT8 channelisedIdlePattern; /**< The byte to be transmitted on - channelised service when there - is no client data to tx */ - BOOL loopback; /**< The HSS loopback state */ - unsigned packetizedIdlePattern; /**< The data to be transmitted on - packetised service when there is - no client data to tx */ - IxHssAccClkSpeed clkSpeed; /**< The HSS clock speed */ -} IxHssAccConfigParams; - -/** - * @brief This structure contains 56Kbps, HDLC-mode configuration parameters - * - */ -typedef struct -{ - BOOL hdlc56kMode; /**< 56kbps(true)/64kbps(false) HDLC */ - IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness - - ignored if hdlc56kMode is false*/ - BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(true)/'1'(false) of the unused - bit while in 56kbps mode - - ignored if hdlc56kMode is false*/ -} IxHssAccHdlcMode; - -/** - * @brief This structure contains information required by the NPE to - * configure the HDLC co-processor - * - */ -typedef struct -{ - IxHssAccPktHdlcIdleType hdlcIdleType; /**< What to transmit when a HDLC port is idle */ - IxHssAccBitEndian dataEndian; /**< The HDLC data endianness */ - IxHssAccPktCrcType crcType; /**< The CRC type to be used for this HDLC port */ -} IxHssAccPktHdlcFraming; - -/** - * @typedef UINT32 IxHssAccPktUserId - * - * @brief The client supplied value which will be supplied as a parameter - * with a given callback. - * - * This value will be passed into the ixHssAccPktPortConnect function once each - * with given callbacks. This value will then be passed back to the client - * as one of the parameters to each of these callbacks, - * when these callbacks are called. - */ -typedef UINT32 IxHssAccPktUserId; - - -/** - * @typedef IxHssAccLastErrorCallback - * @brief Prototype of the clients function to accept notification of the - * last error - * - * This function is registered through the config. The client will initiate - * the last error retrieval. The HssAccess component will send a message to - * the NPE through the NPE Message Handler. When a response to the read is - * received, the NPE Message Handler will callback the HssAccess component - * which will execute this function in the same IxNpeMh context. The client - * will be passed the last error and the related service port (packetised - * 0-3, channelised 0) - * - * @param lastHssError unsigned [in] - The last Hss error registered that - * has been registered. - * @param servicePort unsigned [in] - This is the service port number. - * (packetised 0-3, channelised 0) - * - * @return void - */ -typedef void (*IxHssAccLastErrorCallback) (unsigned lastHssError, - unsigned servicePort); - -/** - * @typedef IxHssAccPktRxCallback - * @brief Prototype of the clients function to accept notification of - * packetised rx - * - * This function is registered through the ixHssAccPktPortConnect. hssPktAcc will pass - * received data in the form of mbufs to the client. The mbuf passed back - * to the client could contain a chain of buffers, depending on the packet - * size received. - * - * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contains the - * payload received. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the - * mbuf that has been received. - * @param rxUserId @ref IxHssAccPktUserId [in] - This is the client supplied value - * passed in at ixHssAccPktPortConnect time which is now returned to the client. - * - * @return void - */ -typedef void (*IxHssAccPktRxCallback) (IX_OSAL_MBUF *buffer, - unsigned numHssErrs, - IxHssAccPktStatus pktStatus, - IxHssAccPktUserId rxUserId); - -/** - * @typedef IxHssAccPktRxFreeLowCallback - * @brief Prototype of the clients function to accept notification of - * requirement of more Rx Free buffers - * - * The client can choose to register a callback of this type when - * calling a connecting. This function is registered through the ixHssAccPktPortConnect. - * If defined, the access layer will provide the trigger for - * this callback. The callback will be responsible for supplying mbufs to - * the access layer for use on the receive path from the HSS using - * ixHssPktAccFreeBufReplenish. - * - * @return void - */ -typedef void (*IxHssAccPktRxFreeLowCallback) (IxHssAccPktUserId rxFreeLowUserId); - -/** - * @typedef IxHssAccPktTxDoneCallback - * @brief Prototype of the clients function to accept notification of - * completion with Tx buffers - * - * This function is registered through the ixHssAccPktPortConnect. It enables - * the hssPktAcc to pass buffers back to the client - * when transmission is complete. - * - * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contained - * the payload that was for Tx. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the - * mbuf that has been transmitted. - * @param txDoneUserId @ref IxHssAccPktUserId [in] - This is the client supplied value - * passed in at ixHssAccPktPortConnect time which is now returned to the client. - * - * @return void - */ -typedef void (*IxHssAccPktTxDoneCallback) (IX_OSAL_MBUF *buffer, - unsigned numHssErrs, - IxHssAccPktStatus pktStatus, - IxHssAccPktUserId txDoneUserId); - -/** - * @typedef IxHssAccChanRxCallback - * @brief Prototype of the clients function to accept notification of - * channelised rx - * - * This callback, if defined by the client in the connect, will get called - * in the context of an IRQ. The IRQ will be triggered when the hssSyncQMQ - * is not empty. The queued entry will be dequeued and this function will - * be executed. - * - * @param hssPortId @ref IxHssAccHssPort - The HSS port Id. There are two - * identical ports (0-1). - * @param txOffset unsigned [in] - an offset indicating from where within - * the txPtrList the NPE is currently transmitting from. - * @param rxOffset unsigned [in] - an offset indicating where within the - * receive buffers the NPE has just written the received data to. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * - * @return void - */ -typedef void (*IxHssAccChanRxCallback) (IxHssAccHssPort hssPortId, - unsigned rxOffset, - unsigned txOffset, - unsigned numHssErrs); - -/* - * Prototypes for interface functions. - */ - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPortInit (IxHssAccHssPort hssPortId, - IxHssAccConfigParams *configParams, - IxHssAccTdmSlotUsage *tdmMap, - IxHssAccLastErrorCallback lastHssErrorCallback) - * - * @brief Initialise a HSS port. No channelised or packetised connections - * should exist in the HssAccess layer while this interface is being called. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param *configParams @ref IxHssAccConfigParams [in] - A pointer to the HSS - * configuration structure - * @param *tdmMap @ref IxHssAccTdmSlotUsage [in] - A pointer to an array of size - * IX_HSSACC_TSLOTS_PER_HSS_PORT, defining the slot usage over the HSS port - * @param lastHssErrorCallback @ref IxHssAccLastErrorCallback [in] - Client - * callback to report last error - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPortInit (IxHssAccHssPort hssPortId, - IxHssAccConfigParams *configParams, - IxHssAccTdmSlotUsage *tdmMap, - IxHssAccLastErrorCallback lastHssErrorCallback); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccLastErrorRetrievalInitiate ( - IxHssAccHssPort hssPortId) - * - * @brief Initiate the retrieval of the last HSS error. The HSS port - * should be configured before attempting to call this interface. - * - * @param hssPortId @ref IxHssAccHssPort [in] - the HSS port ID - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccLastErrorRetrievalInitiate (IxHssAccHssPort hssPortId); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccInit () - * - * @brief This function is responsible for initialising resources for use - * by the packetised and channelised clients. It should be called after - * HSS NPE image has been downloaded into NPE-A and before any other - * HssAccess interface is called. - * No other HssAccPacketised interface should be called while this interface - * is being processed. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - */ -PUBLIC IX_STATUS -ixHssAccInit (void); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - BOOL hdlcFraming, - IxHssAccHdlcMode hdlcMode, - BOOL hdlcBitInvert, - unsigned blockSizeInWords, - UINT32 rawIdleBlockPattern, - IxHssAccPktHdlcFraming hdlcTxFraming, - IxHssAccPktHdlcFraming hdlcRxFraming, - unsigned frmFlagStart, - IxHssAccPktRxCallback rxCallback, - IxHssAccPktUserId rxUserId, - IxHssAccPktRxFreeLowCallback rxFreeLowCallback, - IxHssAccPktUserId rxFreeLowUserId, - IxHssAccPktTxDoneCallback txDoneCallback, - IxHssAccPktUserId txDoneUserId) - * - * @brief This function is responsible for connecting a client to one of - * the 4 available HDLC ports. The HSS port should be configured before - * attempting a connect. No other HssAccPacketised interface should be - * called while this connect is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port and - * it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param hdlcFraming BOOL [in] - This value determines whether the service - * will use HDLC data or the debug, raw data type i.e. no HDLC processing - * @param hdlcMode @ref IxHssAccHdlcMode [in] - This structure contains 56Kbps, HDLC-mode - * configuration parameters - * @param hdlcBitInvert BOOL [in] - This value determines whether bit inversion - * will occur between HDLC and HSS co-processors i.e. post-HDLC processing for - * transmit and pre-HDLC processing for receive, for the specified HDLC Termination - * Point - * @param blockSizeInWords unsigned [in] - The max tx/rx block size - * @param rawIdleBlockPattern UINT32 [in] - Tx idle pattern in raw mode - * @param hdlcTxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains - * the following information required by the NPE to configure the HDLC - * co-processor for TX - * @param hdlcRxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains - * the following information required by the NPE to configure the HDLC - * co-processor for RX - * @param frmFlagStart unsigned - Number of flags to precede to - * transmitted flags (0-2). - * @param rxCallback @ref IxHssAccPktRxCallback [in] - Pointer to - * the clients packet receive function. - * @param rxUserId @ref IxHssAccPktUserId [in] - The client supplied rx value - * to be passed back as an argument to the supplied rxCallback - * @param rxFreeLowCallback @ref IxHssAccPktRxFreeLowCallback [in] - Pointer to - * the clients Rx free buffer request function. If NULL, assume client will - * trigger independently. - * @param rxFreeLowUserId @ref IxHssAccPktUserId [in] - The client supplied RxFreeLow value - * to be passed back as an argument to the supplied rxFreeLowCallback - * @param txDoneCallback @ref IxHssAccPktTxDoneCallback [in] - Pointer to the - * clients Tx done callback function - * @param txDoneUserId @ref IxHssAccPktUserId [in] - The client supplied txDone value - * to be passed back as an argument to the supplied txDoneCallback - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - */ -PUBLIC IX_STATUS -ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - BOOL hdlcFraming, - IxHssAccHdlcMode hdlcMode, - BOOL hdlcBitInvert, - unsigned blockSizeInWords, - UINT32 rawIdleBlockPattern, - IxHssAccPktHdlcFraming hdlcTxFraming, - IxHssAccPktHdlcFraming hdlcRxFraming, - unsigned frmFlagStart, - IxHssAccPktRxCallback rxCallback, - IxHssAccPktUserId rxUserId, - IxHssAccPktRxFreeLowCallback rxFreeLowCallback, - IxHssAccPktUserId rxFreeLowUserId, - IxHssAccPktTxDoneCallback txDoneCallback, - IxHssAccPktUserId txDoneUserId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for enabling a packetised service - * for the specified HSS/HDLC port combination. It enables the RX flow. The - * client must have already connected to a packetised service and is responsible - * for ensuring an adequate amount of RX mbufs have been supplied to the access - * component before enabling the packetised service. This function must be called - * on a given port before any call to ixHssAccPktPortTx on the same port. - * No other HssAccPacketised interface should be called while this interface is - * being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to enable the service - * on. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * @fn IX_STATUS ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for disabling a packetised service - * for the specified HSS/HDLC port combination. It disables the RX flow. - * The client must have already connected to and enabled a packetised service - * for the specified HDLC port. This disable interface can be called before a - * disconnect, but is not required to. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to disable - * the service on. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for disconnecting a client from one - * of the 4 available HDLC ports. It is not required that the Rx Flow - * has been disabled before calling this function. If the RX Flow has not been - * disabled, the disconnect will disable it before proceeding with the - * disconnect. No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PKT_DISCONNECTING The function has initiated the disconnecting - * procedure but it has not completed yet. - */ -PUBLIC IX_STATUS -ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn BOOL ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is called to check if a given HSS/HDLC port - * combination is in a connected state or not. This function may be called - * at any time to determine a ports state. No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * - * @return - * - true The state of this HSS/HDLC port combination is disconnected, - * so if a disconnect was called, it is now completed. - * - false The state of this HSS/HDLC port combination is connected, - * so if a disconnect was called, it is not yet completed. - */ -PUBLIC BOOL -ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer) - * - * @brief Function which the client calls at regular intervals to provide - * mbufs to the access component for RX. A connection should exist for - * the specified hssPortId/hdlcPortId combination before attempting to call this - * interface. Also, the connection should not be in a disconnecting state. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a free mbuf to filled with payload. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q - * overflow - */ -PUBLIC IX_STATUS -ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortTx (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer) - * - * @brief Function which the client calls when it wants to transmit - * packetised data. An enabled connection should exist on the specified - * hssPortId/hdlcPortId combination before attempting to call this interface. - * No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a chain of mbufs which the - * client has filled with the payload - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error. See note. - * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q - * overflow - * - * @note IX_HSSACC_RESOURCE_ERR is returned when a free descriptor cannot be - * obtained to send the chain of mbufs to the NPE. This is a normal scenario. - * HssAcc has a pool of descriptors and this error means that they are currently - * all in use. - * The recommended approach to this is to retry until a descriptor becomes free - * and the packet is successfully transmitted. - * Alternatively, the user could wait until the next IxHssAccPktTxDoneCallback - * callback is triggered, and then retry, as it is this event that causes a - * transmit descriptor to be freed. - */ -PUBLIC IX_STATUS -ixHssAccPktPortTx (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanConnect (IxHssAccHssPort hssPortId, - unsigned bytesPerTSTrigger, - UINT8 *rxCircular, - unsigned numRxBytesPerTS, - UINT32 *txPtrList, - unsigned numTxPtrLists, - unsigned numTxBytesPerBlk, - IxHssAccChanRxCallback rxCallback) - * - * @brief This function allows the client to connect to the Tx/Rx NPE - * Channelised Service. There can only be one client per HSS port. The - * client is responsible for ensuring that the HSS port is configured - * appropriately before its connect request. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param bytesPerTSTrigger unsigned [in] - The NPE will trigger the access - * component after bytesPerTSTrigger have been received for all trunk - * timeslots. This figure is a multiple of 8 e.g. 8 for 1ms trigger, 16 for - * 2ms trigger. - * @param *rxCircular UINT8 [in] - A pointer to memory allocated by the - * client to be filled by data received. The buffer at this address is part - * of a pool of buffers to be accessed in a circular fashion. This address - * will be written to by the NPE. Therefore, it needs to be a physical address. - * @param numRxBytesPerTS unsigned [in] - The number of bytes allocated per - * timeslot within the receive memory. This figure will depend on the - * latency of the system. It needs to be deep enough for data to be read by - * the client before the NPE re-writes over that memory e.g. if the client - * samples at a rate of 40bytes per timeslot, numRxBytesPerTS may need to - * be 40bytes * 3. This would give the client 3 * 5ms of time before - * received data is over-written. - * @param *txPtrList UINT32 [in] - The address of an area of contiguous - * memory allocated by the client to be populated with pointers to data for - * transmission. Each pointer list contains a pointer per active channel. - * The txPtrs will point to data to be transmitted by the NPE. Therefore, - * they must point to physical addresses. - * @param numTxPtrLists unsigned [in] - The number of pointer lists in - * txPtrList. This figure is dependent on jitter. - * @param numTxBytesPerBlk unsigned [in] - The size of the Tx data, in - * bytes, that each pointer within the PtrList points to. - * @param rxCallback @ref IxHssAccChanRxCallback [in] - A client function - * pointer to be called back to handle the actual tx/rx of channelised - * data. If this is not NULL, an ISR will call this function. If this - * pointer is NULL, it implies that the client will use a polling mechanism - * to detect when the tx and rx of channelised data is to occur. The client - * will use hssChanAccStatus for this. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ - -PUBLIC IX_STATUS -ixHssAccChanConnect (IxHssAccHssPort hssPortId, - unsigned bytesPerTSTrigger, - UINT8 *rxCircular, - unsigned numRxBytesPerTS, - UINT32 *txPtrList, - unsigned numTxPtrLists, - unsigned numTxBytesPerBlk, - IxHssAccChanRxCallback rxCallback); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanPortEnable (IxHssAccHssPort hssPortId) - * - * @brief This function is responsible for enabling a channelised service - * for the specified HSS port. It enables the NPE RX flow. The client must - * have already connected to a channelised service before enabling the - * channelised service. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanPortEnable (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanPortDisable (IxHssAccHssPort hssPortId) - * - * @brief This function is responsible for disabling a channelised service - * for the specified HSS port. It disables the NPE RX flow. The client must - * have already connected to and enabled a channelised service for the - * specified HSS port. This disable interface can be called before a - * disconnect, but is not required to. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanPortDisable (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanDisconnect (IxHssAccHssPort hssPortId) - * - * @brief This function allows the client to Disconnect from a channelised - * service. If the NPE RX Flow has not been disabled, the disconnect will - * disable it before proceeding with other disconnect functionality. - * No other HssAccChannelised interface should be called while this - * interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanDisconnect (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, - BOOL *dataRecvd, - unsigned *rxOffset, - unsigned *txOffset, - unsigned *numHssErrs) - * - * @brief This function is called by the client to query whether or not - * channelised data has been received. If there is, hssChanAcc will return - * the details in the output parameters. An enabled connection should - * exist on the specified hssPortId before attempting to call this interface. - * No other HssAccChannelised interface should be called while this - * interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether - * or not the access component has read any data for the client. If - * false, the other output parameters will not have been written to. - * @param *rxOffset unsigned [out] - An offset to indicate to the client - * where within the receive buffers the NPE has just written the received - * data to. - * @param *txOffset unsigned [out] - An offset to indicate to the client - * from where within the txPtrList the NPE is currently transmitting from - * @param *numHssErrs unsigned [out] - The total number of HSS port errors - * since initial port configuration - * - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, - BOOL *dataRecvd, - unsigned *rxOffset, - unsigned *txOffset, - unsigned *numHssErrs); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn void ixHssAccShow (void) - * - * @brief This function will display the current state of the IxHssAcc - * component. The output is sent to stdout. - * - * @return void - */ -PUBLIC void -ixHssAccShow (void); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn void ixHssAccStatsInit (void) - * - * @brief This function will reset the IxHssAcc statistics. - * - * @return void - */ -PUBLIC void -ixHssAccStatsInit (void); - -#endif /* IXHSSACC_H */ - -/** - * @} defgroup IxHssAcc - */ diff --git a/drivers/net/npe/include/IxI2cDrv.h b/drivers/net/npe/include/IxI2cDrv.h deleted file mode 100644 index 92c6b24b46..0000000000 --- a/drivers/net/npe/include/IxI2cDrv.h +++ /dev/null @@ -1,867 +0,0 @@ -/** - * @file IxI2cDrv.h - * - * @brief Header file for the IXP400 I2C Driver (IxI2cDrv) - * - * @version $Revision: 0.1 $ - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxI2cDrv IXP400 I2C Driver(IxI2cDrv) API - * - * @brief IXP400 I2C Driver Public API - * - * @{ - */ -#ifndef IXI2CDRV_H -#define IXI2CDRV_H - -#ifdef __ixp46X -#include "IxOsal.h" - -/* - * Section for #define - */ - -/** - * @ingroup IxI2cDrv - * @brief The interval of micro/mili seconds the IXP will wait before it polls for - * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ - * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected - * through the API ixI2cDrvDelayTypeSelect. - */ -#define IX_I2C_US_POLL_FOR_XFER_STATUS 20 - -/** - * @ingroup IxI2cDrv - * @brief The number of tries that will be attempted to call a callback - * function if the callback does not or is unable to resolve the - * issue it is called to resolve - */ -#define IX_I2C_NUM_OF_TRIES_TO_CALL_CALLBACK_FUNC 10 - - -/** - * @ingroup IxI2cDrv - * @brief Number of tries slave will poll the IDBR Rx full bit before it - * gives up - */ -#define IX_I2C_NUM_TO_POLL_IDBR_RX_FULL 0x100 - -/** - * @ingroup IxI2cDrv - * @brief Number of tries slave will poll the IDBR Tx empty bit before it - * gives up - */ -#define IX_I2C_NUM_TO_POLL_IDBR_TX_EMPTY 0x100 - -/* - * Section for enum - */ - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cMasterStatus - * - * @brief The master status - transfer complete, bus error or arbitration loss - */ -typedef enum -{ - IX_I2C_MASTER_XFER_COMPLETE = IX_SUCCESS, - IX_I2C_MASTER_XFER_BUS_ERROR, - IX_I2C_MASTER_XFER_ARB_LOSS -} IxI2cMasterStatus; - - -/** - * @ingroup IxI2cDrv - * - * @enum IX_I2C_STATUS - * - * @brief The status that can be returned in a I2C driver initialization - */ -typedef enum -{ - IX_I2C_SUCCESS = IX_SUCCESS, /**< Success status */ - IX_I2C_FAIL, /**< Fail status */ - IX_I2C_NOT_SUPPORTED, /**< hardware does not have dedicated I2C hardware */ - IX_I2C_NULL_POINTER, /**< parameter passed in is NULL */ - IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE, /**< speed mode selected is invalid */ - IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE, /**< flow mode selected is invalid */ - IX_I2C_SLAVE_ADDR_CB_MISSING, /**< slave callback is NULL */ - IX_I2C_GEN_CALL_CB_MISSING, /**< general callback is NULL */ - IX_I2C_INVALID_SLAVE_ADDR, /**< invalid slave address specified */ - IX_I2C_INT_BIND_FAIL, /**< interrupt bind fail */ - IX_I2C_INT_UNBIND_FAIL, /**< interrupt unbind fail */ - IX_I2C_NOT_INIT, /**< I2C is not initialized yet */ - IX_I2C_MASTER_BUS_BUSY, /**< master detected a I2C bus busy */ - IX_I2C_MASTER_ARB_LOSS, /**< master experienced arbitration loss */ - IX_I2C_MASTER_XFER_ERROR, /**< master experienced a transfer error */ - IX_I2C_MASTER_BUS_ERROR, /**< master detected a I2C bus error */ - IX_I2C_MASTER_NO_BUFFER, /**< no buffer provided for master transfer */ - IX_I2C_MASTER_INVALID_XFER_MODE, /**< xfer mode selected is invalid */ - IX_I2C_SLAVE_ADDR_NOT_DETECTED, /**< polled slave addr not detected */ - IX_I2C_GEN_CALL_ADDR_DETECTED, /**< polling detected general call */ - IX_I2C_SLAVE_READ_DETECTED, /**< polling detected slave read request */ - IX_I2C_SLAVE_WRITE_DETECTED, /**< polling detected slave write request */ - IX_I2C_SLAVE_NO_BUFFER, /**< no buffer provided for slave transfers */ - IX_I2C_DATA_SIZE_ZERO, /**< data size transfer is zero - invalid */ - IX_I2C_SLAVE_WRITE_BUFFER_EMPTY, /**< slave buffer is used till empty */ - IX_I2C_SLAVE_WRITE_ERROR, /**< slave write experienced an error */ - IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL, /**< slave buffer is filled up */ - IX_I2C_SLAVE_OR_GEN_READ_ERROR /**< slave read experienced an error */ -} IX_I2C_STATUS; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cSpeedMode - * - * @brief Type of speed modes supported by the I2C hardware. - */ -typedef enum -{ - IX_I2C_NORMAL_MODE = 0x0, - IX_I2C_FAST_MODE -} IxI2cSpeedMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cXferMode - * - * @brief Used for indicating it is a repeated start or normal transfer - */ -typedef enum -{ - IX_I2C_NORMAL = 0x0, - IX_I2C_REPEATED_START -} IxI2cXferMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cFlowMode - * - * @brief Used for indicating it is a poll or interrupt mode - */ -typedef enum -{ - IX_I2C_POLL_MODE = 0x0, - IX_I2C_INTERRUPT_MODE -} IxI2cFlowMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cDelayMode - * - * @brief Used for selecting looping delay or OS scheduler delay - */ -typedef enum -{ - IX_I2C_LOOP_DELAY = 1, /**< delay in microseconds */ - IX_I2C_SCHED_DELAY /**< delay in miliseconds */ -} IxI2cDelayMode; - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when the master - * has completed its receive. The parameter that is passed will - * provide the status of the read (success, arb loss, or bus - * error), the transfer mode (normal or repeated start, the - * buffer pointer and number of bytes transferred. - */ -typedef void (*IxI2cMasterReadCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when the master - * has completed its transmit. The parameter that is passed will - * provide the status of the write (success, arb loss, or buss - * error), the transfer mode (normal or repeated start), the - * buffer pointer and number of bytes transferred. - */ -typedef void (*IxI2cMasterWriteCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a slave - * address detected in interrupt mode for a read. The parameters - * that is passed will provide the read status, buffer pointer, - * buffer size, and the bytes received. When a start of a read - * is initiated there will be no buffer allocated and this callback - * will be called to request for a buffer. While receiving, if the - * buffer gets filled, this callback will be called to request for - * a new buffer while sending the filled buffer's pointer and size, - * and data size received. When the receive is complete, this - * callback will be called to process the data and free the memory - * by passing the buffer's pointer and size, and data size received. - */ -typedef void (*IxI2cSlaveReadCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a slave - * address detected in interrupt mode for a write. The parameters - * that is passed will provide the write status, buffer pointer, - * buffer size, and the bytes received. When a start of a write is - * initiated there will be no buffer allocated and this callback - * will be called to request for a buffer and to fill it with data. - * While transmitting, if the data in the buffer empties, this - * callback will be called to request for more data to be filled in - * the same or new buffer. When the transmit is complete, this - * callback will be called to free the memory or other actions to - * be taken. - */ -typedef void (*IxI2cSlaveWriteCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a general - * call detected in interrupt mode for a read. The parameters that - * is passed will provide the read status, buffer pointer, buffer - * size, and the bytes received. When a start of a read is - * initiated there will be no buffer allocated and this callback - * will be called to request for a buffer. While receiving, if the - * buffer gets filled, this callback will be called to request for - * a new buffer while sending the filled buffer's pointer and size, - * and data size received. When the receive is complete, this - * callback will be called to process the data and free the memory - * by passing the buffer's pointer and size, and data size received. - */ -typedef void (*IxI2cGenCallCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/* - * Section for struct - */ - -/** - * @brief contains all the variables required to initialize the I2C unit - * - * Structure to be filled and used for calling initialization - */ -typedef struct -{ - IxI2cSpeedMode I2cSpeedSelect; /** - * NOTE: 1) An individual callback is to be registered for each Slave and Master - * Auxiliary Time Stamp registers. Thus to register for both Master and Slave time - * stamp interrupts either the same callback or two separate callbacks the API has - * to be invoked twice. - * 2) On the IXDP465 Development Platform, the Auxiliary Timestamp signal for - * slave mode is tied to GPIO 8 pin. This signal is software routed by default to - * PCI for backwards compatibility with the IXDP425 Development Platform. This - * routing must be disabled for the auxiliary slave time stamp register to work - * properly. The following commands may be used to accomplish this. However, refer - * to the IXDP465 Development Platform Users Guide or the BSP/LSP documentation for - * more specific information. - * - * For Linux (at the Redboot prompt i.e., before loading zImage): - * mfill -b 0x54100000 -1 -l 1 -p 8 - * mfill -b 0x54100001 -1 -l 1 -p 0x7f - * For vxWorks, at the prompt: - * intDisable(25) - * ixdp400FpgaIODetach(8) - * - * - * @li Re-entrant : no - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback or - invalid auxiliary snapshot mode - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimeInterruptEnable(IxTimeSyncAccAuxMode auxMode, - IxTimeSyncAccAuxTimeCallback auxTimeCallback); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptDisable( - IxTimeSyncAccAuxMode auxMode) - * - * @brief Disables the interrupt for the indicated mode of Auxiliary Time Stamp - * in the IEEE 1588 hardware assist block - * - * @param auxMode [in] - Auxiliary time stamp mode (slave or master) using which - * the interrupt will be disabled. - * - * This API will disable the Auxiliary Time Stamp Interrupt (Master or Slave) - * - * @li Re-entrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimePoll( - IxTimeSyncAccAuxMode auxMode, - BOOL *auxPollFlag, - IxTimeSyncAccTimeValue *auxTime) - * - * @brief Poll for the Auxiliary Time Stamp captured for the mode indicated - * (Master or Slave) - * - * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked - * @param auxPollFlag [out] - true if the time stamp captured in auxiliary - snapshot register - * false if the time stamp not captured in - auxiliary snapshot register - * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the - * client provided buffer - * - * Polls for the Time stamp in the appropriate Auxiliary Snapshot Registers based - * on the mode specified. Return true and the contents of the Auxiliary snapshot, - * if it is available else return false. - * - * Please refer to the note #2 of the API @ref ixTimeSyncAccAuxTimeInterruptEnable - * for more information for Auxiliary Slave mode. - * - * @li Re-entrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for auxPollFlag, - callback or invalid auxiliary snapshot mode - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - * @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimePoll(IxTimeSyncAccAuxMode auxMode, - BOOL *auxPollFlag, - IxTimeSyncAccTimeValue *auxTime); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccReset(void) - * - * @brief Resets the IEEE 1588 hardware assist block - * - * Sets the reset bit in the IEEE1588 silicon which fully resets the silicon block - * - * @li Reentrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccReset(void); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccStatsGet(IxTimeSyncAccStats - *timeSyncStats) - * - * @brief Returns the IxTimeSyncAcc Statistics in the client supplied buffer - * - * @param timeSyncStats [out] - TimeSync statistics counter values - * - * This API will return the statistics of the received or transmitted messages. - * - * NOTE: 1) These counters are updated only when the client polls for the time - * stamps or interrupt are enabled. This is because the IxTimeSyncAcc module - * does not either transmit or receive messages and does only run the code - * when explicit requests received by client application. - * - * 2) These statistics reflect the number of valid PTP messages exchanged - * in Master and Slave modes but includes all the messages (including valid - * non-PTP messages) while operating in the Any mode. - * - * @li Reentrant : no - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - NULL parameter passed - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccStatsGet(IxTimeSyncAccStats *timeSyncStats); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn void ixTimeSyncAccStatsReset(void) - * - * @brief Reset Time Sync statistics - * - * This API will reset the statistics counters of the TimeSync access layer. - * - * @li Reentrant : yes - * @li ISR Callable: no - * - * @return @li None - */ -PUBLIC void -ixTimeSyncAccStatsReset(void); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccShow(void) - * - * @brief Displays the Time Sync current status - * - * This API will display status on the current configuration of the IEEE - * 1588 hardware assist block, contents of the various time stamp registers, - * outstanding interrupts and/or events. - * - * Note that this is intended for debug only, and in contrast to the other - * functions, it does not clear the any of the status bits associated with - * active timestamps and so is passive in its nature. - * - * @li Reentrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccShow(void); - -#endif /* __ixp46X */ -#endif /* IXTIMESYNCACC_H */ - -/** - * @} defgroup IxTimeSyncAcc - */ - diff --git a/drivers/net/npe/include/IxTimerCtrl.h b/drivers/net/npe/include/IxTimerCtrl.h deleted file mode 100644 index 669dd3ef28..0000000000 --- a/drivers/net/npe/include/IxTimerCtrl.h +++ /dev/null @@ -1,263 +0,0 @@ -/** - * @file IxTimerCtrl.h - * @brief - * This is the header file for the Timer Control component. - * - * The timer callback control component provides a mechanism by which different - * client components can start a timer and have a supplied callback function - * invoked when the timer expires. - * The callbacks are all dispatched from one thread inside this component. - * Any component that needs to be called periodically should use this facility - * rather than create its own task with a sleep loop. - * - * @par - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxTimerCtrl IXP400 Timer Control (IxTimerCtrl) API - * - * @brief The public API for the IXP400 Timer Control Component. - * - * @{ - */ - -#ifndef IxTimerCtrl_H -#define IxTimerCtrl_H - - -#include "IxTypes.h" -/* #include "Ossl.h" */ - -/* - * #defines and macros used in this file. - */ - -/** - * @ingroup IxTimerCtrl - * - * @def IX_TIMERCTRL_NO_FREE_TIMERS - * - * @brief Timer schedule return code. - * - * Indicates that the request to start a timer failed because - * all available timer resources are used. - */ -#define IX_TIMERCTRL_NO_FREE_TIMERS 2 - - -/** - * @ingroup IxTimerCtrl - * - * @def IX_TIMERCTRL_PARAM_ERROR - * - * @brief Timer schedule return code. - * - * Indicates that the request to start a timer failed because - * the client has supplied invalid parameters. - */ -#define IX_TIMERCTRL_PARAM_ERROR 3 - - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @ingroup IxTimerCtrl - * - * @brief A typedef for a pointer to a timer callback function. - * @para void * - This parameter is supplied by the client when the - * timer is started and passed back to the client in the callback. - * @note in general timer callback functions should not block or - * take longer than 100ms. This constraint is required to ensure that - * higher priority callbacks are not held up. - * All callbacks are called from the same thread. - * This thread is a shared resource. - * The parameter passed is provided when the timer is scheduled. - */ -typedef void (*IxTimerCtrlTimerCallback)(void *userParam); - - -/** - * @ingroup IxTimerCtrl - * - * @brief List used to identify the users of timers. - * @note The order in this list indicates priority. Components appearing - * higher in the list will be given priority over components lower in the - * list. When adding components, please insert at an appropriate position - * for priority ( i.e values should be less than IxTimerCtrlMaxPurpose ) . - */ -typedef enum -{ - IxTimerCtrlAdslPurpose, - /* Insert new purposes above this line only - */ - IxTimerCtrlMaxPurpose -} -IxTimerCtrlPurpose; - - -/* - * Function definition - */ - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, - void *userParam, - IxTimerCtrlPurpose purpose, - UINT32 relativeTime, - unsigned *timerId ) - * - * @brief Schedules a callback function to be called after a period of "time". - * The callback function should not block or run for more than 100ms. - * This function - * - * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called. - * @param userParam void [in] - a parameter to send to the callback function, can be NULL. - * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will - * decide the priority of callbacks with different purpose. - * @param relativeTime UINT32 [in] - time relative to now in milliseconds after which the callback - * will be called. The time must be greater than the duration of one OS tick. - * @param *timerId unsigned [out] - An id for the callback scheduled. - * This id can be used to cancel the callback. - * @return - * @li IX_SUCCESS - The timer was started successfully. - * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number - * of running timers has been exceeded. - * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied - * a NULL callback func, or the requested timeout is less than one OS tick. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, - void *userParam, - IxTimerCtrlPurpose purpose, - UINT32 relativeTime, - unsigned *timerId ); - - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, - void *param, - IxTimerCtrlPurpose purpose, - UINT32 interval, - unsigned *timerId ) - * - * @brief Schedules a callback function to be called after a period of "time". - * The callback function should not block or run for more than 100ms. - * - * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called. - * @param userParam void [in] - a parameter to send to the callback function, can be NULL. - * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will - * decide the priority of callbacks with different purpose. - * @param interval UINT32 [in] - the interval in milliseconds between calls to func. - * @param timerId unsigned [out] - An id for the callback scheduled. - * This id can be used to cancel the callback. - * @return - * @li IX_SUCCESS - The timer was started successfully. - * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number - * of running timers has been exceeded. - * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied - * a NULL callback func, or the requested timeout is less than one OS tick. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, - void *param, - IxTimerCtrlPurpose purpose, - UINT32 interval, - unsigned *timerId ); - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlCancel (unsigned id) - * - * @brief Cancels a scheduled callback. - * - * @param id unsigned [in] - the id of the callback to be cancelled. - * @return - * @li IX_SUCCESS - The timer was successfully stopped. - * @li IX_FAIL - The id parameter did not corrrespond to any running timer.. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlCancel (unsigned id); - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlInit(void) - * - * @brief Initialise the Timer Control Component. - * @return - * @li IX_SUCCESS - The timer control component initialized successfully. - * @li IX_FAIL - The timer control component initialization failed, - * or the component was already initialized. - * @note This must be done before any other API function is called. - * This function should be called once only and is not re-entrant. - */ -PUBLIC IX_STATUS -ixTimerCtrlInit(void); - - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlShow( void ) - * - * @brief Display the status of the Timer Control Component. - * @return void - * @note Displays a list of running timers. - * This function is not re-entrant. This function does not suspend the calling thread. - */ -PUBLIC void -ixTimerCtrlShow( void ); - -#endif /* IXTIMERCTRL_H */ - diff --git a/drivers/net/npe/include/IxTypes.h b/drivers/net/npe/include/IxTypes.h deleted file mode 100644 index c4c5a2d267..0000000000 --- a/drivers/net/npe/include/IxTypes.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * @file IxTypes.h (Replaced by OSAL) - * - * @date 28-NOV-2001 - - * @brief This file contains basic types used by the IXP400 software - * - * Design Notes: - * This file shall only include fundamental types and definitions to be - * shared by all the IXP400 components. - * Please DO NOT add component-specific types here. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxTypes IXP400 Types (IxTypes) - * - * @brief Basic data types used by the IXP400 project - * - * @{ - */ - -#ifndef IxTypes_H - -#ifndef __doxygen_HIDE - -#define IxTypes_H - -#endif /* __doxygen_HIDE */ - - -/* WR51880: Undefined data types workaround for backward compatibility */ -#ifdef __linux -#ifndef __INCvxTypesOldh -typedef int (*FUNCPTR)(void); -typedef int STATUS; -#define OK (0) -#define ERROR (-1) -#endif -#endif - -#include "IxOsalBackward.h" - -#endif /* IxTypes_H */ - -/** - * @} addtogroup IxTypes - */ diff --git a/drivers/net/npe/include/IxUART.h b/drivers/net/npe/include/IxUART.h deleted file mode 100644 index 03a44441c5..0000000000 --- a/drivers/net/npe/include/IxUART.h +++ /dev/null @@ -1,458 +0,0 @@ -/** - * @file IxUART.h - * - * @date 12-OCT-01 - * - * @brief Public header for the Intel IXP400 internal UART, generic driver. - * - * Design Notes: - * This driver allows you to perform the following functions: - * Device Initialization, - * send/receive characters. - * - * Perform Uart IOCTL for the following: - * Set/Get the current baud rate, - * set parity, - * set the number of Stop bits, - * set the character Length (5,6,7,8), - * enable/disable Hardware flow control. - * - * Only Polled mode is supported for now. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxUARTAccAPI IXP400 UART Access (IxUARTAcc) API - * - * @brief IXP400 UARTAcc Driver Public API - * - * @{ - */ - - -/* Defaults */ - -/** - * @defgroup DefaultDefines Defines for Default Values - * - * @brief Default values which can be used for UART configuration - * - * @sa ixUARTDev - */ - -/** - * @def IX_UART_DEF_OPTS - * - * @brief The default hardware options to set the UART to - - * no flow control, 8 bit word, 1 stop bit, no parity - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_OPTS (CLOCAL | CS8) - -/** - * @def IX_UART_DEF_XMIT - * - * @brief The default UART FIFO size - must be no bigger than 64 - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_XMIT 64 - -/** - * @def IX_UART_DEF_BAUD - * - * @brief The default UART baud rate - 9600 - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_BAUD 9600 - -/** - * @def IX_UART_MIN_BAUD - * - * @brief The minimum UART baud rate - 9600 - * - * @ingroup DefaultDefines - */ -#define IX_UART_MIN_BAUD 9600 - -/** - * @def IX_UART_MAX_BAUD - * - * @brief The maximum UART baud rate - 926100 - * - * @ingroup DefaultDefines - */ -#define IX_UART_MAX_BAUD 926100 - -/** - * @def IX_UART_XTAL - * - * @brief The UART clock speed - * - * @ingroup DefaultDefines - */ -#define IX_UART_XTAL 14745600 - - - -/* IOCTL commands (Request codes) */ - -/** - * @defgroup IoctlCommandDefines Defines for IOCTL Commands - * - * @brief IOCTL Commands (Request codes) which can be used - * with @ref ixUARTIoctl - */ - - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_BAUD_SET - * - * @brief Set the baud rate - */ -#define IX_BAUD_SET 0 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_BAUD_GET - * - * @brief Get the baud rate - */ -#define IX_BAUD_GET 1 - -/** - * @ingroup IoctlCommandDefines - * @def IX_MODE_SET - * @brief Set the UART mode of operation - */ -#define IX_MODE_SET 2 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_MODE_GET - * - * @brief Get the current UART mode of operation - */ -#define IX_MODE_GET 3 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_OPTS_SET - * - * @brief Set the UART device options - */ -#define IX_OPTS_SET 4 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_OPTS_GET - * - * @brief Get the UART device options - */ -#define IX_OPTS_GET 5 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_STATS_GET - * - * @brief Get the UART statistics - */ -#define IX_STATS_GET 6 - - -/* POSIX style ioctl arguments */ - -/** - * @defgroup IoctlArgDefines Defines for IOCTL Arguments - * - * @brief POSIX style IOCTL arguments which can be used - * with @ref ixUARTIoctl - * - * @sa ixUARTMode - */ - - -/** - * @ingroup IoctlArgDefines - * - * @def CLOCAL - * - * @brief Software flow control - */ -#ifdef CLOCAL -#undef CLOCAL -#endif -#define CLOCAL 0x1 - -/** - * @ingroup IoctlArgDefines - * - * @def CREAD - * - * @brief Enable interrupt receiver - */ -#ifdef CREAD -#undef CREAD -#endif -#define CREAD 0x2 - -/** - * @ingroup IoctlArgDefines - * - * @def CSIZE - * - * @brief Characters size - */ -#ifdef CSIZE -#undef CSIZE -#endif -#define CSIZE 0xc - -/** - * @ingroup IoctlArgDefines - * - * @def CS5 - * - * @brief 5 bits - */ -#ifdef CS5 -#undef CS5 -#endif -#define CS5 0x0 - -/** - * @ingroup IoctlArgDefines - * - * @def CS6 - * - * @brief 6 bits - */ -#ifdef CS6 -#undef CS6 -#endif -#define CS6 0x4 - -/** - * @ingroup IoctlArgDefines - * - * @def CS7 - * - * @brief 7 bits - */ -#ifdef CS7 -#undef CS7 -#endif -#define CS7 0x8 - -/** - * @ingroup IoctlArgDefines - * - * @def CS8 - * - * @brief 8 bits - */ -#ifdef CS8 -#undef CS8 -#endif -#define CS8 0xc - -/** - * @ingroup IoctlArgDefines - * - * @def STOPB - * - * @brief Send two stop bits (else one) - */ -#define STOPB 0x20 - -/** - * @ingroup IoctlArgDefines - * - * @def PARENB - * - * @brief Parity detection enabled (else disabled) - */ -#ifdef PARENB -#undef PARENB -#endif -#define PARENB 0x40 - -/** - * @ingroup IoctlArgDefines - * - * @def PARODD - * - * @brief Odd parity (else even) - */ -#ifdef PARODD -#undef PARODD -#endif -#define PARODD 0x80 - -/** - * @enum ixUARTMode - * @brief The mode to set to UART to. - */ -typedef enum -{ - INTERRUPT=0, /**< Interrupt mode */ - POLLED, /**< Polled mode */ - LOOPBACK /**< Loopback mode */ -} ixUARTMode; - -/** - * @struct ixUARTStats - * @brief Statistics for the UART. - */ -typedef struct -{ - UINT32 rxCount; - UINT32 txCount; - UINT32 overrunErr; - UINT32 parityErr; - UINT32 framingErr; - UINT32 breakErr; -} ixUARTStats; - -/** - * @struct ixUARTDev - * @brief Device descriptor for the UART. - */ -typedef struct -{ - UINT8 *addr; /**< device base address */ - ixUARTMode mode; /**< interrupt, polled or loopback */ - int baudRate; /**< baud rate */ - int freq; /**< UART clock frequency */ - int options; /**< hardware options */ - int fifoSize; /**< FIFO xmit size */ - - ixUARTStats stats; /**< device statistics */ -} ixUARTDev; - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTInit(ixUARTDev* pUART) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * - * @brief Initialise the UART. This puts the chip in a quiescent state. - * - * @pre The base address for the UART must contain a valid value. - * Also the baud rate and hardware options must contain sensible values - * otherwise the defaults will be used as defined in ixUART.h - * - * @post UART is initialized and ready to send and receive data. - * - * @note This function should only be called once per device. - * - * @retval IX_SUCCESS - UART device successfully initialised. - * @retval IX_FAIL - Critical error, device not initialised. - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTInit(ixUARTDev* pUART); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar) - * - * @param pUART @ref ixUARTDev [out] - pointer to UART structure describing our device. - * @param outChar int [out] - character to transmit. - * - * @brief Transmit a character in polled mode. - * - * @pre UART device must be initialised. - * - * @retval IX_SUCCESS - character was successfully transmitted. - * @retval IX_FAIL - output buffer is full (try again). - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * @param *inChar char [in] - character read from the device. - * - * @brief Receive a character in polled mode. - * - * @pre UART device must be initialised. - * - * @retval IX_SUCCESS - character was successfully read. - * @retval IX_FAIL - input buffer empty (try again). - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * @param cmd int [in] - an ioctl request code. - * @param arg void* [in] - optional argument used to set the device mode, - * baud rate, and hardware options. - * - * @brief Perform I/O control routines on the device. - * - * @retval IX_SUCCESS - requested feature was set/read successfully. - * @retval IX_FAIL - error setting/reading the requested feature. - * - * @sa IoctlCommandDefines - * @sa IoctlArgDefines - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg); - -/** - * @} defgroup IxUARTAcc - */ diff --git a/drivers/net/npe/include/IxVersionId.h b/drivers/net/npe/include/IxVersionId.h deleted file mode 100644 index 27796ede84..0000000000 --- a/drivers/net/npe/include/IxVersionId.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - * @file IxVersionId.h - * - * @date 22-Aug-2002 - * - * @brief This file contains the IXP400 Software version identifier - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxVersionId IXP400 Version ID (IxVersionId) - * - * @brief Version Identifiers - * - * @{ - */ - -#ifndef IXVERSIONID_H -#define IXVERSIONID_H - -/** - * @brief Version Identifier String - * - * This string will be updated with each customer release of the IXP400 - * Software. - */ -#define IX_VERSION_ID "2_0" - -/** - * This string will be updated with each customer release of the IXP400 - * ADSL driver package. - */ -#define IX_VERSION_ADSL_ID "1_12" - - -/** - * This string will be updated with each customer release of the IXP400 - * USB Client driver package. - */ -#define IX_VERSION_USBRNDIS_ID "1_9" - -/** - * This string will be updated with each customer release of the IXP400 - * I2C Linux driver package. - */ -#define IX_VERSION_I2C_LINUX_ID "1_0" - -/** - * @brief Linux Ethernet Driver Patch Version Identifier String - * - * This string will be updated with each release of Linux Ethernet Patch - */ -#define LINUX_ETHERNET_DRIVER_PATCH_ID "1_4" - -/** - * @brief Linux Integration Patch Version Identifier String - * - * This String will be updated with each release of Linux Integration Patch - */ -#define LINUX_INTEGRATION_PATCH_ID "1_3" - -/** - * @brief Linux Ethernet Readme version Identifier String - * - * This string will be updated with each release of Linux Ethernet Readme - */ -#define LINUX_ETHERNET_README_ID "1_3" - -/** - * @brief Linux Integration Readme version Identifier String - * - * This string will be updated with each release of Linux Integration Readme - */ - -#define LINUX_INTEGRATION_README_ID "1_3" - -/** - * @brief Linux I2C driver Readme version Identifier String - * - * This string will be updated with each release of Linux I2C Driver Readme - */ -#define LINUX_I2C_DRIVER_README_ID "1_0" - -/** - * @brief ixp425_eth_update_nf_bridge.patch version Identifier String - * - * This string will be updated with each release of ixp425_eth_update_nf_bridge. -patch - * - */ - -#define IXP425_ETH_UPDATE_NF_BRIDGE_ID "1_3" - -/** - * @brief Internal Release Identifier String - * - * This string will be updated with each internal release (SQA drop) - * of the IXP400 Software. - */ -#define IX_VERSION_INTERNAL_ID "SQA3_5" - -/** - * @brief Compatible Tornado Version Identifier - */ -#define IX_VERSION_COMPATIBLE_TORNADO "Tornado2_2_1-PNE2_0" - -/** - * @brief Compatible Linux Version Identifier - */ -#define IX_VERSION_COMPATIBLE_LINUX "MVL3_1" - - -#endif /* IXVERSIONID_H */ - -/** - * @} addtogroup IxVersionId - */ diff --git a/drivers/net/npe/include/ix_error.h b/drivers/net/npe/include/ix_error.h deleted file mode 100644 index d32ace20b5..0000000000 --- a/drivers/net/npe/include/ix_error.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_error.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file will describe the basic error type and support functions that - * will be used by the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:19:03 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_ERROR_H__) -#define __IX_ERROR_H__ - -#include "IxOsalBackward.h" - -#endif /* end !defined(__IX_ERROR_H__) */ - diff --git a/drivers/net/npe/include/ix_macros.h b/drivers/net/npe/include/ix_macros.h deleted file mode 100644 index 53f5942f97..0000000000 --- a/drivers/net/npe/include/ix_macros.h +++ /dev/null @@ -1,266 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_macros.h - * - * = DESCRIPTION - * This file will define the basic preprocessor macros that are going to be used - * the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:41:05 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_MACROS_H__) -#define __IX_MACROS_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - - -/** - * MACRO NAME: IX_BIT_FIELD_MASK16 - * - * DESCRIPTION: Builds the mask required to extract the bit field from a 16 bit unsigned integer value. - * - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a 16 bit mask that will extract the bit field from a 16 bit unsigned integer value. - */ -#define IX_BIT_FIELD_MASK16( \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - ((ix_bit_mask16)((((ix_uint16)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \ - (ix_uint16)1) << arg_FieldLSBBit)) - - - -/** - * MACRO NAME: IX_GET_BIT_FIELD16 - * - * DESCRIPTION: Extracts a bit field from 16 bit unsigned integer. The returned value is normalized in - * in the sense that will be right aligned. - * - * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 - - * arg_FieldLSBBit)) - 1. - */ -#define IX_GET_BIT_FIELD16( \ - arg_PackedData16, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint16)(arg_PackedData16) & IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) >> \ - arg_FieldLSBBit) - - -/** - * MACRO NAME: IX_MAKE_BIT_FIELD16 - * - * DESCRIPTION: This macro will create a temporary 16 bit value with the bit field - * desired set to the desired value. - * - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a temporary ix_uint16 value that has the bit field set to the appropriate value. - */ -#define IX_MAKE_BIT_FIELD16( \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint16)(arg_BitFieldValue) << arg_FieldLSBBit) & \ - IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) - -/** - * MACRO NAME: IX_SET_BIT_FIELD16 - * - * DESCRIPTION: Sets a new value for a bit field from a 16 bit unsigned integer. - * - * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_BitFieldValue is the new vale of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the updated value of arg_PackedData16. - */ -#define IX_SET_BIT_FIELD16( \ - arg_PackedData16, \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (arg_PackedData16 = (((ix_uint16)(arg_PackedData16) & \ - ~(IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))) | \ - IX_MAKE_BIT_FIELD16(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) - - -/** - * MACRO NAME: IX_BIT_FIELD_MASK32 - * - * DESCRIPTION: Builds the mask required to extract the bit field from a 32 bit unsigned integer value. - * - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a 32 bit mask that will extract the bit field from a 32 bit unsigned integer value. - */ -#define IX_BIT_FIELD_MASK32( \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - ((ix_bit_mask32)((((ix_uint32)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \ - (ix_uint32)1) << arg_FieldLSBBit)) - - - -/** - * MACRO NAME: IX_GET_BIT_FIELD32 - * - * DESCRIPTION: Extracts a bit field from 32 bit unsigned integer. The returned value is normalized in - * in the sense that will be right aligned. - * - * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 - - * arg_FieldLSBBit)) - 1. - */ -#define IX_GET_BIT_FIELD32( \ - arg_PackedData32, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint32)(arg_PackedData32) & IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) >> \ - arg_FieldLSBBit) - - - - -/** - * MACRO NAME: IX_MAKE_BIT_FIELD32 - * - * DESCRIPTION: This macro will create a temporary 32 bit value with the bit field - * desired set to the desired value. - * - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a temporary ix_uint32 value that has the bit field set to the appropriate value. - */ -#define IX_MAKE_BIT_FIELD32( \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint32)(arg_BitFieldValue) << arg_FieldLSBBit) & \ - IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) - - -/** - * MACRO NAME: IX_SET_BIT_FIELD32 - * - * DESCRIPTION: Sets a new value for a bit field from a 32 bit unsigned integer. - * - * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the updated value of arg_PackedData32. - */ -#define IX_SET_BIT_FIELD32( \ - arg_PackedData32, \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (arg_PackedData32 = (((ix_uint32)(arg_PackedData32) & \ - ~(IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))) | \ - IX_MAKE_BIT_FIELD32(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) - - - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_MACROS_H__) */ diff --git a/drivers/net/npe/include/ix_os_type.h b/drivers/net/npe/include/ix_os_type.h deleted file mode 100644 index 8575096722..0000000000 --- a/drivers/net/npe/include/ix_os_type.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_os_type.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file provides protable symbol definitions for the current OS type. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:43:30 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_OS_TYPE_H__) -#define __IX_OS_TYPE_H__ - -#include "IxOsalBackward.h" - -#endif /* end !defined(__IX_OS_TYPE_H__) */ - diff --git a/drivers/net/npe/include/ix_ossl.h b/drivers/net/npe/include/ix_ossl.h deleted file mode 100644 index b59f7d0873..0000000000 --- a/drivers/net/npe/include/ix_ossl.h +++ /dev/null @@ -1,160 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = LIBRARY - * OSSL - Operating System Services Library - * - * = MODULE - * OSSL Abstraction layer header file - * - * = FILENAME - * ix_ossl.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file contains the prototypes of OS-independent wrapper - * functions which allow the programmer not to be tied to a specific - * operating system. The OSSL functions can be divided into three classes: - * - * 1) synchronization-related wrapper functions around thread system calls - * 2) thread-related wrapper functions around thread calls - * 3) transactor/workbench osapi calls -- defined in osApi.h - * - * Both 1 and 2 classes of functions provide Thread Management, Thread - * Synchronization, Mutual Exclusion and Timer primitives. Namely, - * creation and deletion functions as well as the standard "wait" and - * "exit". Additionally, a couple of utility functions which enable to - * pause the execution of a thread are also provided. - * - * The 3rd class provides a slew of other OSAPI functions to handle - * Transactor/WorkBench OS calls. - * - * - * OSSL Thread APIs: - * The OSSL thread functions that allow for thread creation, - * get thread id, thread deletion and set thread priroity. - * - * ix_ossl_thread_create - * ix_ossl_thread_get_id - * ix_ossl_thread_exit - * ix_ossl_thread_kill - * ix_ossl_thread_set_priority - * ix_ossl_thread__delay - * - * OSSL Semaphore APIs: - * The OSSL semaphore functions that allow for initialization, - * posting, waiting and deletion of semaphores. - * - * ix_ossl_sem_init - * ix_ossl_sem_fini - * ix_ossl_sem_take - * ix_ossl_sem_give - * ix_ossl_sem_flush - * - * OSSL Mutex APIs: - * The OSSL wrapper functions that allow for initialization, - * posting, waiting and deletion of mutexes. - * - * ix_ossl_mutex_init - * ix_ossl_mutex_fini - * ix_ossl_mutex_lock - * ix_ossl_mutex_unlock - * - * OSSL Timer APIs: - * The timer APIs provide sleep and get time functions. - * - * ix_ossl_sleep - * ix_ossl_sleep_tick - * ix_ossl_time_get - * - * OSAPIs for Transactor/WorkBench: - * These OSAPI functions are used for transator OS calls. - * They are defined in osApi.h. - * - * Sem_Init - * Sem_Destroy - * Sem_Wait - * Sem_Wait - * Thread_Create - * Thread_Cancel - * Thread_SetPriority - * delayMs - * delayTick - * - * - * - ********************************************************************** - * - * - * = AUTHOR - * Intel Corporation - * - * = ACKNOWLEDGEMENTS - * - * - * = CREATION TIME - * 1/8/2002 1:53:42 PM - * - * = CHANGE HISTORY - * 02/22/2002 : Renamed osapi.h os_api.h - * Moved OS header file includes from OSSL.h to os_api.h - * Moved OS specific datatypes to os_api.h - * Modified data types, macros and functions as per - * 'C' coding guidelines. - * - * - * ============================================================================ - */ - -#ifndef _IX_OSSL_H -#ifndef __doxygen_hide -#define _IX_OSSL_H -#endif /* __doxygen_hide */ - -#include "IxOsalBackward.h" - -#endif /* _IX_OSSL_H */ - -/** - * @} defgroup IxOSSL - */ diff --git a/drivers/net/npe/include/ix_symbols.h b/drivers/net/npe/include/ix_symbols.h deleted file mode 100644 index f7bb029d66..0000000000 --- a/drivers/net/npe/include/ix_symbols.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_symbols.h - * - * = DESCRIPTION - * This file declares all the global preprocessor symbols required by - * the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/23/2002 10:41:13 AM - creation time - * ============================================================================ - */ - -#if !defined(__IX_SYMBOLS_H__) -#define __IX_SYMBOLS_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - -/** - * The IX_EXPORT_FUNCTION symbol will be used for compilation on different platforms. - * We are planning to provide a simulation version of the library that should work - * with the Transactor rather than the hardware. This implementation will be done on - * WIN32 in the form of a DLL that will need to export functions and symbols. - */ -#if (_IX_OS_TYPE_ == _IX_OS_WIN32_) -# if defined(_IX_LIB_INTERFACE_IMPLEMENTATION_) -# define IX_EXPORT_FUNCTION __declspec( dllexport ) -# elif defined(_IX_LIB_INTERFACE_IMPORT_DLL_) -# define IX_EXPORT_FUNCTION __declspec( dllimport ) -# else -# define IX_EXPORT_FUNCTION extern -# endif -#elif (_IX_OS_TYPE_ == _IX_OS_WINCE_) -# define IX_EXPORT_FUNCTION __declspec(dllexport) -#else -# define IX_EXPORT_FUNCTION extern -#endif - - -/** - * This symbols should be defined when we want to build for a multithreaded environment - */ -#define _IX_MULTI_THREADED_ 1 - - -/** - * This symbol should be defined in the case we to buils for a multithreaded environment - * but we want that our modules to work as if they are used in a single threaded environment. - */ -/* #define _IX_RM_EXPLICIT_SINGLE_THREADED_ 1 */ - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_SYMBOLS_H__) */ diff --git a/drivers/net/npe/include/ix_types.h b/drivers/net/npe/include/ix_types.h deleted file mode 100644 index fc7b1e993a..0000000000 --- a/drivers/net/npe/include/ix_types.h +++ /dev/null @@ -1,208 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_types.h - * - * = DESCRIPTION - * This file will define generic types that will guarantee the protability - * between different architectures and compilers. It should be used the entire - * IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:44:17 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_TYPES_H__) -#define __IX_TYPES_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - - -/** - * Define generic integral data types that will guarantee the size. - */ - -/** - * TYPENAME: ix_int8 - * - * DESCRIPTION: This type defines an 8 bit signed integer value. - * - */ -typedef signed char ix_int8; - - -/** - * TYPENAME: ix_uint8 - * - * DESCRIPTION: This type defines an 8 bit unsigned integer value. - * - */ -typedef unsigned char ix_uint8; - - -/** - * TYPENAME: ix_int16 - * - * DESCRIPTION: This type defines an 16 bit signed integer value. - * - */ -typedef signed short int ix_int16; - - -/** - * TYPENAME: ix_uint16 - * - * DESCRIPTION: This type defines an 16 bit unsigned integer value. - * - */ -typedef unsigned short int ix_uint16; - - -/** - * TYPENAME: ix_int32 - * - * DESCRIPTION: This type defines an 32 bit signed integer value. - * - */ -typedef signed int ix_int32; - - -/** - * TYPENAME: ix_uint32 - * - * DESCRIPTION: This type defines an 32 bit unsigned integer value. - * - */ -#ifndef __wince -typedef unsigned int ix_uint32; -#else -typedef unsigned long ix_uint32; -#endif - -/** - * TYPENAME: ix_int64 - * - * DESCRIPTION: This type defines an 64 bit signed integer value. - * - */ -#ifndef __wince -__extension__ typedef signed long long int ix_int64; -#endif - -/** - * TYPENAME: ix_uint64 - * - * DESCRIPTION: This type defines an 64 bit unsigned integer value. - * - */ -#ifndef __wince -__extension__ typedef unsigned long long int ix_uint64; -#endif - - -/** - * TYPENAME: ix_bit_mask8 - * - * DESCRIPTION: This is a generic type for a 8 bit mask. - */ -typedef ix_uint8 ix_bit_mask8; - - -/** - * TYPENAME: ix_bit_mask16 - * - * DESCRIPTION: This is a generic type for a 16 bit mask. - */ -typedef ix_uint16 ix_bit_mask16; - - -/** - * TYPENAME: ix_bit_mask32 - * - * DESCRIPTION: This is a generic type for a 32 bit mask. - */ -typedef ix_uint32 ix_bit_mask32; - - -/** - * TYPENAME: ix_bit_mask64 - * - * DESCRIPTION: This is a generic type for a 64 bit mask. - */ -#ifndef __wince -typedef ix_uint64 ix_bit_mask64; -#endif - - -/** - * TYPENAME: ix_handle - * - * DESCRIPTION: This type defines a generic handle. - * - */ -typedef ix_uint32 ix_handle; - - - -/** - * DESCRIPTION: This symbol defines a NULL handle - * - */ -#define IX_NULL_HANDLE ((ix_handle)0) - - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_TYPES_H__) */ diff --git a/drivers/net/npe/include/npe.h b/drivers/net/npe/include/npe.h deleted file mode 100644 index 1c6ae26ddc..0000000000 --- a/drivers/net/npe/include/npe.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef NPE_H -#define NPE_H - -/* - * defines... - */ -#define CONFIG_SYS_NPE_NUMS 1 -#ifdef CONFIG_HAS_ETH1 -#undef CONFIG_SYS_NPE_NUMS -#define CONFIG_SYS_NPE_NUMS 2 -#endif - -#define NPE_NUM_PORTS 3 -#define ACTIVE_PORTS 1 - -#define NPE_PKT_SIZE 1600 - -#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS 64 -#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS 2 - -#define NPE_MBUF_POOL_SIZE \ - ((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS + \ - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) * \ - sizeof(IX_OSAL_MBUF) * ACTIVE_PORTS) - -#define NPE_PKT_POOL_SIZE \ - ((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS + \ - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) * \ - NPE_PKT_SIZE * ACTIVE_PORTS) - -#define NPE_MEM_POOL_SIZE (NPE_MBUF_POOL_SIZE + NPE_PKT_POOL_SIZE) - -#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ - -/* - * structs... - */ -struct npe { - u8 active; /* NPE active */ - u8 eth_id; /* IX_ETH_PORT_1 or IX_ETH_PORT_2 */ - u8 phy_no; /* which PHY (0 - 31) */ - u8 mac_address[6]; - - IX_OSAL_MBUF *rxQHead; - IX_OSAL_MBUF *txQHead; - - u8 *tx_pkts; - u8 *rx_pkts; - IX_OSAL_MBUF *rx_mbufs; - IX_OSAL_MBUF *tx_mbufs; - - int print_speed; - - int rx_read; - int rx_write; - int rx_len[PKTBUFSRX]; -}; - -/* - * prototypes... - */ -extern int npe_miiphy_read (const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -extern int npe_miiphy_write (const char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -#endif /* ifndef NPE_H */ diff --git a/drivers/net/npe/include/os_datatypes.h b/drivers/net/npe/include/os_datatypes.h deleted file mode 100644 index 4387b2a052..0000000000 --- a/drivers/net/npe/include/os_datatypes.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * @par - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = LIBRARY - * OSSL - Operating System Services Library - * - * = MODULE - * OS Specific Data Types header file - * - * = FILENAME - * OSSL.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file contains definitions and encapsulations for OS specific data types. These - * encapsulated data types are used by OSSL header files and OS API functions. - * - * - ********************************************************************** - * - * - * = AUTHOR - * Intel Corporation - * - * = AKNOWLEDGEMENTS - * - * - * = CREATION TIME - * 1/8/2002 1:53:42 PM - * - * = CHANGE HISTORY - - * ============================================================================ - */ - -#ifndef _OS_DATATYPES_H -#define _OS_DATATYPES_H - -#include "IxOsalBackward.h" - -#endif /* _OS_DATATYPES_H */ - diff --git a/drivers/net/npe/miiphy.c b/drivers/net/npe/miiphy.c deleted file mode 100644 index a04779ab46..0000000000 --- a/drivers/net/npe/miiphy.c +++ /dev/null @@ -1,120 +0,0 @@ -/*-----------------------------------------------------------------------------+ - | This source code is dual-licensed. You may use it under the terms of the - | GNU General Public License version 2, or under the license below. - | - | This source code has been made available to you by IBM on an AS-IS - | basis. Anyone receiving this source is licensed under IBM - | copyrights to use it in any way he or she deems fit, including - | copying it, modifying it, compiling it, and redistributing it either - | with or without modifications. No license under IBM patents or - | patent applications is to be implied by the copyright license. - | - | Any user of this software should understand that IBM cannot provide - | technical support for this software and will not be responsible for - | any consequences resulting from the use of this software. - | - | Any person who transfers this source code or any derivative work - | must include the IBM copyright notice, this paragraph, and the - | preceding two paragraphs in the transferred software. - | - | COPYRIGHT I B M CORPORATION 1995 - | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - +-----------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------+ - | - | File Name: miiphy.c - | - | Function: This module has utilities for accessing the MII PHY through - | the EMAC3 macro. - | - | Author: Mark Wisner - | - | Change Activity- - | - | Date Description of Change BY - | --------- --------------------- --- - | 05-May-99 Created MKW - | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to - | better match OPB speed. Also modified delay times. JWB - | 29-Jul-99 Added Full duplex support MKW - | 24-Aug-99 Removed printf from dp83843_duplex() JWB - | 19-Jul-00 Ported to esd cpci405 sr - | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS - | - | - +-----------------------------------------------------------------------------*/ - -#include -#include -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" -#include "IxEthAccMii_p.h" - -/***********************************************************/ -/* Dump out to the screen PHY regs */ -/***********************************************************/ - -void miiphy_dump (char *devname, unsigned char addr) -{ - unsigned long i; - unsigned short data; - - - for (i = 0; i < 0x1A; i++) { - if (miiphy_read (devname, addr, i, &data)) { - printf ("read error for reg %lx\n", i); - return; - } - printf ("Phy reg %lx ==> %4x\n", i, data); - - /* jump to the next set of regs */ - if (i == 0x07) - i = 0x0f; - - } /* end for loop */ -} /* end dump */ - - -/***********************************************************/ -/* (Re)start autonegotiation */ -/***********************************************************/ -int phy_setup_aneg (char *devname, unsigned char addr) -{ - unsigned short ctl, adv; - - /* Setup standard advertise */ - miiphy_read (devname, addr, MII_ADVERTISE, &adv); - adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | - LPA_100FULL | LPA_100HALF | LPA_10FULL | - LPA_10HALF); - miiphy_write (devname, addr, MII_ADVERTISE, adv); - - /* Start/Restart aneg */ - miiphy_read (devname, addr, MII_BMCR, &ctl); - ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); - miiphy_write (devname, addr, MII_BMCR, ctl); - - return 0; -} - - -int npe_miiphy_read (const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - u16 val; - - ixEthAccMiiReadRtn(addr, reg, &val); - *value = val; - - return 0; -} /* phy_read */ - - -int npe_miiphy_write (const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - ixEthAccMiiWriteRtn(addr, reg, value); - return 0; -} /* phy_write */ diff --git a/drivers/net/npe/npe.c b/drivers/net/npe/npe.c deleted file mode 100644 index 00b381ec4a..0000000000 --- a/drivers/net/npe/npe.c +++ /dev/null @@ -1,680 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#if 0 -#define DEBUG /* define for debug output */ -#endif - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -static IxQMgrDispatcherFuncPtr qDispatcherFunc = NULL; -static int npe_exists[NPE_NUM_PORTS]; -static int npe_used[NPE_NUM_PORTS]; - -/* A little extra so we can align to cacheline. */ -static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1]; -static u8 *npe_alloc_end; -static u8 *npe_alloc_free; - -static void *npe_alloc(int size) -{ - static int count = 0; - void *p = NULL; - - size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1); - count++; - - if ((npe_alloc_free + size) < npe_alloc_end) { - p = npe_alloc_free; - npe_alloc_free += size; - } else { - printf("npe_alloc: failed (count=%d, size=%d)!\n", count, size); - } - return p; -} - -/* Not interrupt safe! */ -static void mbuf_enqueue(IX_OSAL_MBUF **q, IX_OSAL_MBUF *new) -{ - IX_OSAL_MBUF *m = *q; - - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(new) = NULL; - - if (m) { - while(IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m)) - m = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m); - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = new; - } else - *q = new; -} - -/* Not interrupt safe! */ -static IX_OSAL_MBUF *mbuf_dequeue(IX_OSAL_MBUF **q) -{ - IX_OSAL_MBUF *m = *q; - if (m) - *q = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m); - return m; -} - -static void reset_tx_mbufs(struct npe* p_npe) -{ - IX_OSAL_MBUF *m; - int i; - - p_npe->txQHead = NULL; - - for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS; i++) { - m = &p_npe->tx_mbufs[i]; - - memset(m, 0, sizeof(*m)); - - IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->tx_pkts[i * NPE_PKT_SIZE]; - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - mbuf_enqueue(&p_npe->txQHead, m); - } -} - -static void reset_rx_mbufs(struct npe* p_npe) -{ - IX_OSAL_MBUF *m; - int i; - - p_npe->rxQHead = NULL; - - HAL_DCACHE_INVALIDATE(p_npe->rx_pkts, NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - - for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS; i++) { - m = &p_npe->rx_mbufs[i]; - - memset(m, 0, sizeof(*m)); - - IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->rx_pkts[i * NPE_PKT_SIZE]; - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - - if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) { - printf("ixEthAccPortRxFreeReplenish failed for port %d\n", p_npe->eth_id); - break; - } - } -} - -static void init_rx_mbufs(struct npe* p_npe) -{ - p_npe->rxQHead = NULL; - - p_npe->rx_pkts = npe_alloc(NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - if (p_npe->rx_pkts == NULL) { - printf("alloc of packets failed.\n"); - return; - } - - p_npe->rx_mbufs = (IX_OSAL_MBUF *) - npe_alloc(sizeof(IX_OSAL_MBUF) * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - if (p_npe->rx_mbufs == NULL) { - printf("alloc of mbufs failed.\n"); - return; - } - - reset_rx_mbufs(p_npe); -} - -static void init_tx_mbufs(struct npe* p_npe) -{ - p_npe->tx_pkts = npe_alloc(NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS); - if (p_npe->tx_pkts == NULL) { - printf("alloc of packets failed.\n"); - return; - } - - p_npe->tx_mbufs = (IX_OSAL_MBUF *) - npe_alloc(sizeof(IX_OSAL_MBUF) * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS); - if (p_npe->tx_mbufs == NULL) { - printf("alloc of mbufs failed.\n"); - return; - } - - reset_tx_mbufs(p_npe); -} - -/* Convert IX_ETH_PORT_n to IX_NPEMH_NPEID_NPEx */ -static int __eth_to_npe(int eth_id) -{ - switch(eth_id) { - case IX_ETH_PORT_1: - return IX_NPEMH_NPEID_NPEB; - - case IX_ETH_PORT_2: - return IX_NPEMH_NPEID_NPEC; - - case IX_ETH_PORT_3: - return IX_NPEMH_NPEID_NPEA; - } - return 0; -} - -/* Poll the CSR machinery. */ -static void npe_poll(int eth_id) -{ - if (qDispatcherFunc != NULL) { - ixNpeMhMessagesReceive(__eth_to_npe(eth_id)); - (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP); - } -} - -/* ethAcc RX callback */ -static void npe_rx_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid) -{ - struct npe* p_npe = (struct npe *)cbTag; - - if (IX_OSAL_MBUF_MLEN(m) > 0) { - mbuf_enqueue(&p_npe->rxQHead, m); - - if (p_npe->rx_write == ((p_npe->rx_read-1) & (PKTBUFSRX-1))) { - debug("Rx overflow: rx_write=%d rx_read=%d\n", - p_npe->rx_write, p_npe->rx_read); - } else { - debug("Received message #%d (len=%d)\n", p_npe->rx_write, - IX_OSAL_MBUF_MLEN(m)); - memcpy((void *)NetRxPackets[p_npe->rx_write], IX_OSAL_MBUF_MDATA(m), - IX_OSAL_MBUF_MLEN(m)); - p_npe->rx_len[p_npe->rx_write] = IX_OSAL_MBUF_MLEN(m); - p_npe->rx_write++; - if (p_npe->rx_write == PKTBUFSRX) - p_npe->rx_write = 0; - -#ifdef CONFIG_PRINT_RX_FRAMES - { - u8 *ptr = IX_OSAL_MBUF_MDATA(m); - int i; - - for (i=0; i<60; i++) { - debug("%02x ", *ptr++); - } - debug("\n"); - } -#endif - } - - m = mbuf_dequeue(&p_npe->rxQHead); - } else { - debug("Received frame with length 0!!!\n"); - m = mbuf_dequeue(&p_npe->rxQHead); - } - - /* Now return mbuf to NPE */ - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL; - IX_OSAL_MBUF_FLAGS(m) = 0; - - if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) { - debug("npe_rx_callback: Error returning mbuf.\n"); - } -} - -/* ethAcc TX callback */ -static void npe_tx_callback(u32 cbTag, IX_OSAL_MBUF *m) -{ - struct npe* p_npe = (struct npe *)cbTag; - - debug("%s\n", __FUNCTION__); - - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL; - IX_OSAL_MBUF_FLAGS(m) = 0; - - mbuf_enqueue(&p_npe->txQHead, m); -} - - -static int npe_set_mac_address(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - IxEthAccMacAddr npeMac; - - debug("%s\n", __FUNCTION__); - - /* Set MAC address */ - memcpy(npeMac.macAddress, dev->enetaddr, 6); - - if (ixEthAccPortUnicastMacAddressSet(p_npe->eth_id, &npeMac) != IX_ETH_ACC_SUCCESS) { - printf("Error setting unicast address! %02x:%02x:%02x:%02x:%02x:%02x\n", - npeMac.macAddress[0], npeMac.macAddress[1], - npeMac.macAddress[2], npeMac.macAddress[3], - npeMac.macAddress[4], npeMac.macAddress[5]); - return 0; - } - - return 1; -} - -/* Boot-time CSR library initialization. */ -static int npe_csr_load(void) -{ - int i; - - if (ixQMgrInit() != IX_SUCCESS) { - debug("Error initialising queue manager!\n"); - return 0; - } - - ixQMgrDispatcherLoopGet(&qDispatcherFunc); - - if(ixNpeMhInitialize(IX_NPEMH_NPEINTERRUPTS_YES) != IX_SUCCESS) { - printf("Error initialising NPE Message handler!\n"); - return 0; - } - - if (npe_used[IX_ETH_PORT_1] && npe_exists[IX_ETH_PORT_1] && - ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS) - != IX_SUCCESS) { - printf("Error downloading firmware to NPE-B!\n"); - return 0; - } - - if (npe_used[IX_ETH_PORT_2] && npe_exists[IX_ETH_PORT_2] && - ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS) - != IX_SUCCESS) { - printf("Error downloading firmware to NPE-C!\n"); - return 0; - } - - /* don't need this for U-Boot */ - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false); - - if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) { - printf("Error initialising Ethernet access driver!\n"); - return 0; - } - - for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) { - if (!npe_used[i] || !npe_exists[i]) - continue; - if (ixEthAccPortInit(i) != IX_ETH_ACC_SUCCESS) { - printf("Error initialising Ethernet port%d!\n", i); - } - if (ixEthAccTxSchedulingDisciplineSet(i, FIFO_NO_PRIORITY) != IX_ETH_ACC_SUCCESS) { - printf("Error setting scheduling discipline for port %d.\n", i); - } - if (ixEthAccPortRxFrameAppendFCSDisable(i) != IX_ETH_ACC_SUCCESS) { - printf("Error disabling RX FCS for port %d.\n", i); - } - if (ixEthAccPortTxFrameAppendFCSEnable(i) != IX_ETH_ACC_SUCCESS) { - printf("Error enabling TX FCS for port %d.\n", i); - } - } - - return 1; -} - -static int npe_init(struct eth_device *dev, bd_t * bis) -{ - struct npe *p_npe = (struct npe *)dev->priv; - int i; - u16 reg_short; - int speed; - int duplex; - - debug("%s: 1\n", __FUNCTION__); - -#ifdef CONFIG_MII_NPE0_FIXEDLINK - if (0 == p_npe->eth_id) { - speed = CONFIG_MII_NPE0_SPEED; - duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF; - } else -#endif -#ifdef CONFIG_MII_NPE1_FIXEDLINK - if (1 == p_npe->eth_id) { - speed = CONFIG_MII_NPE1_SPEED; - duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF; - } else -#endif - { - miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, ®_short); - - /* - * Wait if PHY is capable of autonegotiation and - * autonegotiation is not complete - */ - if ((reg_short & BMSR_ANEGCAPABLE) && - !(reg_short & BMSR_ANEGCOMPLETE)) { - puts("Waiting for PHY auto negotiation to complete"); - i = 0; - while (!(reg_short & BMSR_ANEGCOMPLETE)) { - /* - * Timeout reached ? - */ - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts(" TIMEOUT !\n"); - break; - } - - if ((i++ % 1000) == 0) { - putc('.'); - miiphy_read(dev->name, p_npe->phy_no, - MII_BMSR, ®_short); - } - udelay(1000); /* 1 ms */ - } - puts(" done\n"); - /* another 500 ms (results in faster booting) */ - udelay(500000); - } - speed = miiphy_speed(dev->name, p_npe->phy_no); - duplex = miiphy_duplex(dev->name, p_npe->phy_no); - } - - if (p_npe->print_speed) { - p_npe->print_speed = 0; - printf ("ENET Speed is %d Mbps - %s duplex connection\n", - (int) speed, (duplex == HALF) ? "HALF" : "FULL"); - } - - npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool); - npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool + - CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1)); - - /* initialize mbuf pool */ - init_rx_mbufs(p_npe); - init_tx_mbufs(p_npe); - - if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - printf("can't register RX callback!\n"); - return -1; - } - - if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - printf("can't register TX callback!\n"); - return -1; - } - - npe_set_mac_address(dev); - - if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { - printf("can't enable port!\n"); - return -1; - } - - p_npe->active = 1; - - return 0; -} - -#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ -/* Uninitialize CSR library. */ -static void npe_csr_unload(void) -{ - ixEthAccUnload(); - ixEthDBUnload(); - ixNpeMhUnload(); - ixQMgrUnload(); -} - -/* callback which is used by ethAcc to recover RX buffers when stopping */ -static void npe_rx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid) -{ - debug("%s\n", __FUNCTION__); -} - -/* callback which is used by ethAcc to recover TX buffers when stopping */ -static void npe_tx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m) -{ - debug("%s\n", __FUNCTION__); -} -#endif - -static void npe_halt(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - int i; - - debug("%s\n", __FUNCTION__); - - /* Delay to give time for recovery of mbufs */ - for (i = 0; i < 100; i++) { - npe_poll(p_npe->eth_id); - udelay(100); - } - -#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ - if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_stop_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - debug("Error registering rx callback!\n"); - } - - if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_stop_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - debug("Error registering tx callback!\n"); - } - - if (ixEthAccPortDisable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { - debug("npe_stop: Error disabling NPEB!\n"); - } - - /* Delay to give time for recovery of mbufs */ - for (i = 0; i < 100; i++) { - npe_poll(p_npe->eth_id); - udelay(10000); - } - - /* - * For U-Boot only, we are probably launching Linux or other OS that - * needs a clean slate for its NPE library. - */ -#if 0 /* test-only */ - for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) { - if (npe_used[i] && npe_exists[i]) - if (ixNpeDlNpeStopAndReset(__eth_to_npe(i)) != IX_SUCCESS) - printf("Failed to stop and reset NPE B.\n"); - } -#endif - -#endif - p_npe->active = 0; -} - - -static int npe_send(struct eth_device *dev, void *packet, int len) -{ - struct npe *p_npe = (struct npe *)dev->priv; - u8 *dest; - int err; - IX_OSAL_MBUF *m; - - debug("%s\n", __FUNCTION__); - m = mbuf_dequeue(&p_npe->txQHead); - dest = IX_OSAL_MBUF_MDATA(m); - IX_OSAL_MBUF_PKT_LEN(m) = IX_OSAL_MBUF_MLEN(m) = len; - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = NULL; - - memcpy(dest, (char *)packet, len); - - if ((err = ixEthAccPortTxFrameSubmit(p_npe->eth_id, m, IX_ETH_ACC_TX_DEFAULT_PRIORITY)) - != IX_ETH_ACC_SUCCESS) { - printf("npe_send: Can't submit frame. err[%d]\n", err); - mbuf_enqueue(&p_npe->txQHead, m); - return 0; - } - -#ifdef DEBUG_PRINT_TX_FRAMES - { - u8 *ptr = IX_OSAL_MBUF_MDATA(m); - int i; - - for (i=0; ieth_id); - - return len; -} - -static int npe_rx(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - - debug("%s\n", __FUNCTION__); - npe_poll(p_npe->eth_id); - - debug("%s: rx_write=%d rx_read=%d\n", __FUNCTION__, p_npe->rx_write, p_npe->rx_read); - while (p_npe->rx_write != p_npe->rx_read) { - debug("Reading message #%d\n", p_npe->rx_read); - NetReceive(NetRxPackets[p_npe->rx_read], p_npe->rx_len[p_npe->rx_read]); - p_npe->rx_read++; - if (p_npe->rx_read == PKTBUFSRX) - p_npe->rx_read = 0; - } - - return 0; -} - -int npe_initialize(bd_t * bis) -{ - static int virgin = 0; - struct eth_device *dev; - int eth_num = 0; - struct npe *p_npe = NULL; - uchar enetaddr[6]; - - for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) { - - /* See if we can actually bring up the interface, otherwise, skip it */ -#ifdef CONFIG_HAS_ETH1 - if (eth_num == 1) { - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) - continue; - } else -#endif - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - continue; - - /* Allocate device structure */ - dev = (struct eth_device *)malloc(sizeof(*dev)); - if (dev == NULL) { - printf ("%s: Cannot allocate eth_device %d\n", __FUNCTION__, eth_num); - return -1; - } - memset(dev, 0, sizeof(*dev)); - - /* Allocate our private use data */ - p_npe = (struct npe *)malloc(sizeof(struct npe)); - if (p_npe == NULL) { - printf("%s: Cannot allocate private hw data for eth_device %d", - __FUNCTION__, eth_num); - free(dev); - return -1; - } - memset(p_npe, 0, sizeof(struct npe)); - - p_npe->eth_id = eth_num; - memcpy(dev->enetaddr, enetaddr, 6); -#ifdef CONFIG_HAS_ETH1 - if (eth_num == 1) - p_npe->phy_no = CONFIG_PHY1_ADDR; - else -#endif - p_npe->phy_no = CONFIG_PHY_ADDR; - - sprintf(dev->name, "NPE%d", eth_num); - dev->priv = (void *)p_npe; - dev->init = npe_init; - dev->halt = npe_halt; - dev->send = npe_send; - dev->recv = npe_rx; - - p_npe->print_speed = 1; - - if (0 == virgin) { - virgin = 1; - - if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) { - switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) { - case IX_FEATURE_CTRL_SILICON_TYPE_B0: - default: /* newer than B0 */ - /* - * If it is B0 or newer Silicon, we - * only enable port when its - * corresponding Eth Coprocessor is - * available. - */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = true; - - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = true; - break; - case IX_FEATURE_CTRL_SILICON_TYPE_A0: - /* - * If it is A0 Silicon, we enable both as both Eth Coprocessors - * are available. - */ - npe_exists[IX_ETH_PORT_1] = true; - npe_exists[IX_ETH_PORT_2] = true; - break; - } - } else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = true; - - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = true; - } - - npe_used[IX_ETH_PORT_1] = 1; - npe_used[IX_ETH_PORT_2] = 1; - - npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool); - npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool + - CONFIG_SYS_CACHELINE_SIZE - 1) - & ~(CONFIG_SYS_CACHELINE_SIZE - 1)); - - if (!npe_csr_load()) - return 0; - } - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write); -#endif - - } /* end for each supported device */ - - return 1; -} diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 283cb48b4e..237fbba513 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -71,12 +71,16 @@ struct pcnet_init_block { u32 reserved2; }; -typedef struct pcnet_priv { +struct pcnet_uncached_priv { struct pcnet_rx_head rx_ring[RX_RING_SIZE]; struct pcnet_tx_head tx_ring[TX_RING_SIZE]; struct pcnet_init_block init_block; +}; + +typedef struct pcnet_priv { + struct pcnet_uncached_priv *uc; /* Receive Buffer space */ - unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; + unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; int cur_rx; int cur_tx; } pcnet_priv_t; @@ -89,39 +93,39 @@ static pcnet_priv_t *lp; #define PCNET_RESET 0x14 #define PCNET_BDP 0x16 -static u16 pcnet_read_csr (struct eth_device *dev, int index) +static u16 pcnet_read_csr(struct eth_device *dev, int index) { - outw (index, dev->iobase + PCNET_RAP); - return inw (dev->iobase + PCNET_RDP); + outw(index, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_RDP); } -static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) +static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) { - outw (index, dev->iobase + PCNET_RAP); - outw (val, dev->iobase + PCNET_RDP); + outw(index, dev->iobase + PCNET_RAP); + outw(val, dev->iobase + PCNET_RDP); } -static u16 pcnet_read_bcr (struct eth_device *dev, int index) +static u16 pcnet_read_bcr(struct eth_device *dev, int index) { - outw (index, dev->iobase + PCNET_RAP); - return inw (dev->iobase + PCNET_BDP); + outw(index, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_BDP); } -static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) +static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) { - outw (index, dev->iobase + PCNET_RAP); - outw (val, dev->iobase + PCNET_BDP); + outw(index, dev->iobase + PCNET_RAP); + outw(val, dev->iobase + PCNET_BDP); } -static void pcnet_reset (struct eth_device *dev) +static void pcnet_reset(struct eth_device *dev) { - inw (dev->iobase + PCNET_RESET); + inw(dev->iobase + PCNET_RESET); } -static int pcnet_check (struct eth_device *dev) +static int pcnet_check(struct eth_device *dev) { - outw (88, dev->iobase + PCNET_RAP); - return (inw (dev->iobase + PCNET_RAP) == 88); + outw(88, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_RAP) == 88; } static int pcnet_init (struct eth_device *dev, bd_t * bis); @@ -139,63 +143,64 @@ static struct pci_device_id supported[] = { }; -int pcnet_initialize (bd_t * bis) +int pcnet_initialize(bd_t *bis) { pci_dev_t devbusfn; struct eth_device *dev; u16 command, status; int dev_nr = 0; - PCNET_DEBUG1 ("\npcnet_initialize...\n"); + PCNET_DEBUG1("\npcnet_initialize...\n"); for (dev_nr = 0;; dev_nr++) { /* * Find the PCnet PCI device(s). */ - if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { + devbusfn = pci_find_devices(supported, dev_nr); + if (devbusfn < 0) break; - } /* * Allocate and pre-fill the device structure. */ - dev = (struct eth_device *) malloc (sizeof *dev); + dev = (struct eth_device *)malloc(sizeof(*dev)); if (!dev) { printf("pcnet: Can not allocate memory\n"); break; } memset(dev, 0, sizeof(*dev)); - dev->priv = (void *) devbusfn; - sprintf (dev->name, "pcnet#%d", dev_nr); + dev->priv = (void *)devbusfn; + sprintf(dev->name, "pcnet#%d", dev_nr); /* * Setup the PCI device. */ - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - (unsigned int *) &dev->iobase); - dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, + (unsigned int *)&dev->iobase); + dev->iobase = pci_io_to_phys(devbusfn, dev->iobase); dev->iobase &= ~0xf; - PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", - dev->name, devbusfn, dev->iobase); + PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", + dev->name, devbusfn, dev->iobase); command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; - pci_write_config_word (devbusfn, PCI_COMMAND, command); - pci_read_config_word (devbusfn, PCI_COMMAND, &status); + pci_write_config_word(devbusfn, PCI_COMMAND, command); + pci_read_config_word(devbusfn, PCI_COMMAND, &status); if ((status & command) != command) { - printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); - free (dev); + printf("%s: Couldn't enable IO access or Bus Mastering\n", + dev->name); + free(dev); continue; } - pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); /* * Probe the PCnet chip. */ - if (pcnet_probe (dev, bis, dev_nr) < 0) { - free (dev); + if (pcnet_probe(dev, bis, dev_nr) < 0) { + free(dev); continue; } @@ -207,15 +212,15 @@ int pcnet_initialize (bd_t * bis) dev->send = pcnet_send; dev->recv = pcnet_recv; - eth_register (dev); + eth_register(dev); } - udelay (10 * 1000); + udelay(10 * 1000); return dev_nr; } -static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) +static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) { int chip_version; char *chipname; @@ -225,17 +230,17 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) #endif /* Reset the PCnet controller */ - pcnet_reset (dev); + pcnet_reset(dev); /* Check if register access is working */ - if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { - printf ("%s: CSR register access check failed\n", dev->name); + if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { + printf("%s: CSR register access check failed\n", dev->name); return -1; } /* Identify the chip */ chip_version = - pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); + pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); if ((chip_version & 0xfff) != 0x003) return -1; chip_version = (chip_version >> 12) & 0xffff; @@ -254,12 +259,12 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) break; #endif default: - printf ("%s: PCnet version %#x not supported\n", - dev->name, chip_version); + printf("%s: PCnet version %#x not supported\n", + dev->name, chip_version); return -1; } - PCNET_DEBUG1 ("AMD %s\n", chipname); + PCNET_DEBUG1("AMD %s\n", chipname); #ifdef PCNET_HAS_PROM /* @@ -270,7 +275,7 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) for (i = 0; i < 3; i++) { unsigned int val; - val = pcnet_read_csr (dev, i + 12) & 0x0ffff; + val = pcnet_read_csr(dev, i + 12) & 0x0ffff; /* There may be endianness issues here. */ dev->enetaddr[2 * i] = val & 0x0ff; dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; @@ -280,35 +285,41 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) return 0; } -static int pcnet_init (struct eth_device *dev, bd_t * bis) +static int pcnet_init(struct eth_device *dev, bd_t *bis) { + struct pcnet_uncached_priv *uc; int i, val; u32 addr; - PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); + PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); /* Switch pcnet to 32bit mode */ - pcnet_write_bcr (dev, 20, 2); - -#ifdef CONFIG_PN62 - /* Setup LED registers */ - val = pcnet_read_bcr (dev, 2) | 0x1000; - pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ - pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ - pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ - pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ - pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ -#endif + pcnet_write_bcr(dev, 20, 2); /* Set/reset autoselect bit */ - val = pcnet_read_bcr (dev, 2) & ~2; + val = pcnet_read_bcr(dev, 2) & ~2; val |= 2; - pcnet_write_bcr (dev, 2, val); + pcnet_write_bcr(dev, 2, val); /* Enable auto negotiate, setup, disable fd */ - val = pcnet_read_bcr (dev, 32) & ~0x98; + val = pcnet_read_bcr(dev, 32) & ~0x98; val |= 0x20; - pcnet_write_bcr (dev, 32, val); + pcnet_write_bcr(dev, 32, val); + + /* + * Enable NOUFLO on supported controllers, with the transmit + * start point set to the full packet. This will cause entire + * packets to be buffered by the ethernet controller before + * transmission, eliminating underflows which are common on + * slower devices. Controllers which do not support NOUFLO will + * simply be left with a larger transmit FIFO threshold. + */ + val = pcnet_read_bcr(dev, 18); + val |= 1 << 11; + pcnet_write_bcr(dev, 18, val); + val = pcnet_read_csr(dev, 80); + val |= 0x3 << 10; + pcnet_write_csr(dev, 80, val); /* * We only maintain one structure because the drivers will never @@ -316,27 +327,38 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis) * must be aligned on 16-byte boundaries. */ if (lp == NULL) { - addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); + addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); addr = (addr + 0xf) & ~0xf; - lp = (pcnet_priv_t *) addr; + lp = (pcnet_priv_t *)addr; + + addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); + flush_dcache_range(addr, addr + sizeof(*lp->uc)); + addr = UNCACHED_SDRAM(addr); + lp->uc = (struct pcnet_uncached_priv *)addr; + + addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf)); + flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); + lp->rx_buf = (void *)addr; } - lp->init_block.mode = cpu_to_le16 (0x0000); - lp->init_block.filter[0] = 0x00000000; - lp->init_block.filter[1] = 0x00000000; + uc = lp->uc; + + uc->init_block.mode = cpu_to_le16(0x0000); + uc->init_block.filter[0] = 0x00000000; + uc->init_block.filter[1] = 0x00000000; /* * Initialize the Rx ring. */ lp->cur_rx = 0; for (i = 0; i < RX_RING_SIZE; i++) { - lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); - lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); - lp->rx_ring[i].status = cpu_to_le16 (0x8000); + uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]); + uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); + uc->rx_ring[i].status = cpu_to_le16(0x8000); PCNET_DEBUG1 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, - lp->rx_ring[i].base, lp->rx_ring[i].buf_length, - lp->rx_ring[i].status); + uc->rx_ring[i].base, uc->rx_ring[i].buf_length, + uc->rx_ring[i].status); } /* @@ -345,55 +367,56 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis) */ lp->cur_tx = 0; for (i = 0; i < TX_RING_SIZE; i++) { - lp->tx_ring[i].base = 0; - lp->tx_ring[i].status = 0; + uc->tx_ring[i].base = 0; + uc->tx_ring[i].status = 0; } /* * Setup Init Block. */ - PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); + PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); for (i = 0; i < 6; i++) { - lp->init_block.phys_addr[i] = dev->enetaddr[i]; - PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); + lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; + PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); } - lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | - RX_RING_LEN_BITS); - lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); - lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); + uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | + RX_RING_LEN_BITS); + uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring); + uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring); - PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", - lp->init_block.tlen_rlen, - lp->init_block.rx_ring, lp->init_block.tx_ring); + PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", + uc->init_block.tlen_rlen, + uc->init_block.rx_ring, uc->init_block.tx_ring); /* * Tell the controller where the Init Block is located. */ - addr = PCI_TO_MEM (dev, &lp->init_block); - pcnet_write_csr (dev, 1, addr & 0xffff); - pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); + barrier(); + addr = PCI_TO_MEM(dev, &lp->uc->init_block); + pcnet_write_csr(dev, 1, addr & 0xffff); + pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); - pcnet_write_csr (dev, 4, 0x0915); - pcnet_write_csr (dev, 0, 0x0001); /* start */ + pcnet_write_csr(dev, 4, 0x0915); + pcnet_write_csr(dev, 0, 0x0001); /* start */ /* Wait for Init Done bit */ for (i = 10000; i > 0; i--) { - if (pcnet_read_csr (dev, 0) & 0x0100) + if (pcnet_read_csr(dev, 0) & 0x0100) break; - udelay (10); + udelay(10); } if (i <= 0) { - printf ("%s: TIMEOUT: controller init failed\n", dev->name); - pcnet_reset (dev); + printf("%s: TIMEOUT: controller init failed\n", dev->name); + pcnet_reset(dev); return -1; } /* * Finally start network controller operation. */ - pcnet_write_csr (dev, 0, 0x0002); + pcnet_write_csr(dev, 0, 0x0002); return 0; } @@ -401,22 +424,25 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis) static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) { int i, status; - struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; - PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, - packet); + PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, + packet); + + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + pkt_len); /* Wait for completion by testing the OWN bit */ for (i = 1000; i > 0; i--) { - status = le16_to_cpu (entry->status); + status = readw(&entry->status); if ((status & 0x8000) == 0) break; - udelay (100); - PCNET_DEBUG2 ("."); + udelay(100); + PCNET_DEBUG2("."); } if (i <= 0) { - printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", - dev->name, lp->cur_tx, status); + printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", + dev->name, lp->cur_tx, status); pkt_len = 0; goto failure; } @@ -425,68 +451,70 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) * Setup Tx ring. Caution: the write order is important here, * set the status with the "ownership" bits last. */ - status = 0x8300; - entry->length = le16_to_cpu (-pkt_len); - entry->misc = 0x00000000; - entry->base = PCI_TO_MEM_LE (dev, packet); - entry->status = le16_to_cpu (status); + writew(-pkt_len, &entry->length); + writel(0, &entry->misc); + writel(PCI_TO_MEM(dev, packet), &entry->base); + writew(0x8300, &entry->status); /* Trigger an immediate send poll. */ - pcnet_write_csr (dev, 0, 0x0008); + pcnet_write_csr(dev, 0, 0x0008); failure: if (++lp->cur_tx >= TX_RING_SIZE) lp->cur_tx = 0; - PCNET_DEBUG2 ("done\n"); + PCNET_DEBUG2("done\n"); return pkt_len; } static int pcnet_recv (struct eth_device *dev) { struct pcnet_rx_head *entry; + unsigned char *buf; int pkt_len = 0; - u16 status; + u16 status, err_status; while (1) { - entry = &lp->rx_ring[lp->cur_rx]; + entry = &lp->uc->rx_ring[lp->cur_rx]; /* * If we own the next entry, it's a new packet. Send it up. */ - if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { + status = readw(&entry->status); + if ((status & 0x8000) != 0) break; - } - status >>= 8; - - if (status != 0x03) { /* There was an error. */ - - printf ("%s: Rx%d", dev->name, lp->cur_rx); - PCNET_DEBUG1 (" (status=0x%x)", status); - if (status & 0x20) - printf (" Frame"); - if (status & 0x10) - printf (" Overflow"); - if (status & 0x08) - printf (" CRC"); - if (status & 0x04) - printf (" Fifo"); - printf (" Error\n"); - entry->status &= le16_to_cpu (0x03ff); + err_status = status >> 8; + + if (err_status != 0x03) { /* There was an error. */ + printf("%s: Rx%d", dev->name, lp->cur_rx); + PCNET_DEBUG1(" (status=0x%x)", err_status); + if (err_status & 0x20) + printf(" Frame"); + if (err_status & 0x10) + printf(" Overflow"); + if (err_status & 0x08) + printf(" CRC"); + if (err_status & 0x04) + printf(" Fifo"); + printf(" Error\n"); + status &= 0x03ff; } else { - - pkt_len = - (le32_to_cpu (entry->msg_length) & 0xfff) - 4; + pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; if (pkt_len < 60) { - printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); + printf("%s: Rx%d: invalid packet length %d\n", + dev->name, lp->cur_rx, pkt_len); } else { - NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); - PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", - lp->cur_rx, pkt_len, - lp->rx_buf[lp->cur_rx]); + buf = (*lp->rx_buf)[lp->cur_rx]; + invalidate_dcache_range((unsigned long)buf, + (unsigned long)buf + pkt_len); + NetReceive(buf, pkt_len); + PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", + lp->cur_rx, pkt_len, buf); } } - entry->status |= cpu_to_le16 (0x8000); + + status |= 0x8000; + writew(status, &entry->status); if (++lp->cur_rx >= RX_RING_SIZE) lp->cur_rx = 0; @@ -494,22 +522,21 @@ static int pcnet_recv (struct eth_device *dev) return pkt_len; } -static void pcnet_halt (struct eth_device *dev) +static void pcnet_halt(struct eth_device *dev) { int i; - PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); + PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); /* Reset the PCnet controller */ - pcnet_reset (dev); + pcnet_reset(dev); /* Wait for Stop bit */ for (i = 1000; i > 0; i--) { - if (pcnet_read_csr (dev, 0) & 0x4) + if (pcnet_read_csr(dev, 0) & 0x4) break; - udelay (10); - } - if (i <= 0) { - printf ("%s: TIMEOUT: controller reset failed\n", dev->name); + udelay(10); } + if (i <= 0) + printf("%s: TIMEOUT: controller reset failed\n", dev->name); } diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig new file mode 100644 index 0000000000..c72785cce8 --- /dev/null +++ b/drivers/net/phy/Kconfig @@ -0,0 +1,5 @@ +config PHYLIB + bool "Generic PHY support" + +config PHY_SMSC + bool "SMSC PHY support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index fe762e9de3..d096db87a2 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -5,44 +5,23 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libphy.o - -COBJS-$(CONFIG_BITBANGMII) += miiphybb.o -COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o -COBJS-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o - -COBJS-$(CONFIG_PHYLIB) += phy.o -COBJS-$(CONFIG_PHYLIB_10G) += generic_10g.o -COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o -COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o -COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o -COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o -COBJS-$(CONFIG_PHY_ICPLUS) += icplus.o -COBJS-$(CONFIG_PHY_LXT) += lxt.o -COBJS-$(CONFIG_PHY_MARVELL) += marvell.o -COBJS-$(CONFIG_PHY_MICREL) += micrel.o -COBJS-$(CONFIG_PHY_NATSEMI) += natsemi.o -COBJS-$(CONFIG_PHY_REALTEK) += realtek.o -COBJS-$(CONFIG_PHY_SMSC) += smsc.o -COBJS-$(CONFIG_PHY_TERANETICS) += teranetics.o -COBJS-$(CONFIG_PHY_VITESSE) += vitesse.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_BITBANGMII) += miiphybb.o +obj-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o +obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o + +obj-$(CONFIG_PHYLIB) += phy.o +obj-$(CONFIG_PHYLIB_10G) += generic_10g.o +obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o +obj-$(CONFIG_PHY_ATHEROS) += atheros.o +obj-$(CONFIG_PHY_BROADCOM) += broadcom.o +obj-$(CONFIG_PHY_CORTINA) += cortina.o +obj-$(CONFIG_PHY_DAVICOM) += davicom.o +obj-$(CONFIG_PHY_ET1011C) += et1011c.o +obj-$(CONFIG_PHY_LXT) += lxt.o +obj-$(CONFIG_PHY_MARVELL) += marvell.o +obj-$(CONFIG_PHY_MICREL) += micrel.o +obj-$(CONFIG_PHY_NATSEMI) += natsemi.o +obj-$(CONFIG_PHY_REALTEK) += realtek.o +obj-$(CONFIG_PHY_SMSC) += smsc.o +obj-$(CONFIG_PHY_TERANETICS) += teranetics.o +obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c new file mode 100644 index 0000000000..ef4da4e2ec --- /dev/null +++ b/drivers/net/phy/aquantia.c @@ -0,0 +1,156 @@ +/* + * Aquantia PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2014 Freescale Semiconductor, Inc. + */ +#include +#include +#include + +#ifndef CONFIG_PHYLIB_10G +#error The Aquantia PHY needs 10G support +#endif + +#define AQUNTIA_10G_CTL 0x20 +#define AQUNTIA_VENDOR_P1 0xc400 + +#define AQUNTIA_SPEED_LSB_MASK 0x2000 +#define AQUNTIA_SPEED_MSB_MASK 0x40 + +int aquantia_config(struct phy_device *phydev) +{ + u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + /* 1000BASE-T mode */ + phydev->advertising = SUPPORTED_1000baseT_Full; + phydev->supported = phydev->advertising; + + val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK; + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); + } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) { + /* 10GBASE-T mode */ + phydev->advertising = SUPPORTED_10000baseT_Full; + phydev->supported = phydev->advertising; + + if (!(val & AQUNTIA_SPEED_LSB_MASK) || + !(val & AQUNTIA_SPEED_MSB_MASK)) + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, + AQUNTIA_SPEED_LSB_MASK | + AQUNTIA_SPEED_MSB_MASK); + } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { + /* 2.5GBASE-T mode */ + phydev->advertising = SUPPORTED_1000baseT_Full; + phydev->supported = phydev->advertising; + + phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1); + phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440); + } else if (phydev->interface == PHY_INTERFACE_MODE_MII) { + /* 100BASE-TX mode */ + phydev->advertising = SUPPORTED_100baseT_Full; + phydev->supported = phydev->advertising; + + val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK; + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); + } + return 0; +} + +int aquantia_startup(struct phy_device *phydev) +{ + u32 reg, speed; + int i = 0; + + phydev->duplex = DUPLEX_FULL; + + /* if the AN is still in progress, wait till timeout. */ + phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if (!(reg & MDIO_AN_STAT1_COMPLETE)) { + printf("%s Waiting for PHY auto negotiation to complete", + phydev->dev->name); + do { + udelay(1000); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if ((i++ % 500) == 0) + printf("."); + } while (!(reg & MDIO_AN_STAT1_COMPLETE) && + i < (4 * PHY_ANEG_TIMEOUT)); + + if (i > PHY_ANEG_TIMEOUT) + printf(" TIMEOUT !\n"); + } + + /* Read twice because link state is latched and a + * read moves the current state into the register */ + phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS)) + phydev->link = 0; + else + phydev->link = 1; + + speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + if (speed & AQUNTIA_SPEED_MSB_MASK) { + if (speed & AQUNTIA_SPEED_LSB_MASK) + phydev->speed = SPEED_10000; + else + phydev->speed = SPEED_1000; + } else { + if (speed & AQUNTIA_SPEED_LSB_MASK) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + } + + return 0; +} + +struct phy_driver aq1202_driver = { + .name = "Aquantia AQ1202", + .uid = 0x3a1b445, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + +struct phy_driver aq2104_driver = { + .name = "Aquantia AQ2104", + .uid = 0x3a1b460, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + +struct phy_driver aqr105_driver = { + .name = "Aquantia AQR105", + .uid = 0x3a1b4a2, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; +int phy_aquantia_init(void) +{ + phy_register(&aq1202_driver); + phy_register(&aq2104_driver); + phy_register(&aqr105_driver); + + return 0; +} diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 0f2dfd6126..d509e30d35 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -13,6 +13,7 @@ static int ar8021_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); + phydev->supported = phydev->drv->features; return 0; } @@ -30,9 +31,7 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); - genphy_config_aneg(phydev); - - phy_reset(phydev); + phydev->supported = phydev->drv->features; return 0; } @@ -40,7 +39,7 @@ static int ar8035_config(struct phy_device *phydev) static struct phy_driver AR8021_driver = { .name = "AR8021", .uid = 0x4dd040, - .mask = 0xfffff0, + .mask = 0x4ffff0, .features = PHY_GBIT_FEATURES, .config = ar8021_config, .startup = genphy_startup, @@ -48,11 +47,11 @@ static struct phy_driver AR8021_driver = { }; static struct phy_driver AR8031_driver = { - .name = "AR8031", + .name = "AR8031/AR8033", .uid = 0x4dd074, - .mask = 0xfffff0, + .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = genphy_config, + .config = ar8021_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; @@ -60,7 +59,7 @@ static struct phy_driver AR8031_driver = { static struct phy_driver AR8035_driver = { .name = "AR8035", .uid = 0x4dd072, - .mask = 0x4fffff, + .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, .config = ar8035_config, .startup = genphy_startup, diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c new file mode 100644 index 0000000000..254f056df4 --- /dev/null +++ b/drivers/net/phy/cortina.c @@ -0,0 +1,333 @@ +/* + * Cortina CS4315/CS4340 10G PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND +#include +#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) +#include +#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) +#include +#endif + +#ifndef CONFIG_PHYLIB_10G +#error The Cortina PHY needs 10G support +#endif + +struct cortina_reg_config cortina_reg_cfg[] = { + /* CS4315_enable_sr_mode */ + {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, + {VILLA_MSEQ_OPTIONS, 0xf}, + {VILLA_MSEQ_PC, 0x0}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30}, + {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1}, + {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003}, + {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047}, + {VILLA_MSEQ_ENABLE_MSB, 0x0000}, + {VILLA_MSEQ_SPARE21_LSB, 0x6}, + {VILLA_MSEQ_RESET_COUNT_LSB, 0x0}, + {VILLA_MSEQ_SPARE12_MSB, 0x0000}, + /* + * to invert the receiver path, uncomment the next line + * write (VILLA_MSEQ_SPARE12_MSB, 0x4000) + * + * SPARE2_LSB is used to configure the device while in sr mode to + * enable power savings and to use the optical module LOS signal. + * in power savings mode, the internal prbs checker can not be used. + * if the optical module LOS signal is used as an input to the micro + * code, then the micro code will wait until the optical module + * LOS = 0 before turning on the adaptive equalizer. + * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode + * while setting bit 0 to 0 disables power savings mode. + * Setting SPARE2_LSB bit 2 to 0 configures the device to use the + * optical module LOS signal while setting bit 2 to 1 configures the + * device so that it will ignore the optical module LOS SPARE2_LSB = 0 + */ + + /* enable power savings, ignore optical module LOS */ + {VILLA_MSEQ_SPARE2_LSB, 0x5}, + + {VILLA_MSEQ_SPARE7_LSB, 0x1e}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_MSEQ_SPARE9_LSB, 0x2}, + {VILLA_MSEQ_SPARE3_LSB, 0x0F53}, + {VILLA_MSEQ_SPARE3_MSB, 0x2006}, + {VILLA_MSEQ_SPARE8_LSB, 0x3FF7}, + {VILLA_MSEQ_SPARE8_MSB, 0x0A46}, + {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500}, + {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200}, + {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00}, + {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100}, + {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300}, + {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300}, + {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700}, + {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00}, + {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00}, + {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2}, + {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000}, + {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF}, + {VILLA_MSEQ_POWER_DOWN_MSB, 0x0}, + {VILLA_MSEQ_CAL_RX_SLICER, 0x80}, + {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f}, + {VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, + {VILLA_MSEQ_OPTIONS, 0x7}, + + /* set up min value for ffe1 */ + {VILLA_MSEQ_COEF_INIT_SEL, 0x2}, + {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41}, + + /* CS4315_sr_rx_pre_eq_set_4in */ + {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, + {VILLA_MSEQ_OPTIONS, 0xf}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_MSEQ_PC, 0x0}, + + /* for lengths from 3.5 to 4.5inches */ + {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306}, + {VILLA_MSEQ_SPARE25_LSB, 0x0306}, + {VILLA_MSEQ_SPARE21_LSB, 0x2}, + {VILLA_MSEQ_SPARE23_LSB, 0x2}, + {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0}, + + {VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, + {VILLA_MSEQ_OPTIONS, 0x7}, + + /* CS4315_rx_drive_4inch */ + /* for length 4inches */ + {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, + {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, + + /* CS4315_tx_drive_4inch */ + /* for length 4inches */ + {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, +}; + +void cs4340_upload_firmware(struct phy_device *phydev) +{ + char line_temp[0x50] = {0}; + char reg_addr[0x50] = {0}; + char reg_data[0x50] = {0}; + int i, line_cnt = 0, column_cnt = 0; + struct cortina_reg_config fw_temp; + char *addr = NULL; + +#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \ + defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE) + + addr = (char *)CONFIG_CORTINA_FW_ADDR; +#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND) + int ret; + size_t fw_length = CONFIG_CORTINA_FW_LENGTH; + + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR, + &fw_length, (u_char *)addr); + if (ret == -EUCLEAN) { + printf("NAND read of Cortina firmware at 0x%x failed %d\n", + CONFIG_CORTINA_FW_ADDR, ret); + } +#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) + int ret; + struct spi_flash *ucode_flash; + + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!ucode_flash) { + puts("SF: probe for Cortina ucode failed\n"); + } else { + ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR, + CONFIG_CORTINA_FW_LENGTH, addr); + if (ret) + puts("SF: read for Cortina ucode failed\n"); + spi_flash_free(ucode_flash); + } +#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) + int dev = CONFIG_SYS_MMC_ENV_DEV; + u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; + u32 blk = CONFIG_CORTINA_FW_ADDR / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + puts("Failed to find MMC device for Cortina ucode\n"); + } else { + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + printf("MMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)mmc->block_dev.block_read(dev, blk, cnt, addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); + } +#endif + + while (*addr != 'Q') { + i = 0; + + while (*addr != 0x0a) { + line_temp[i++] = *addr++; + if (0x50 < i) { + printf("Not found Cortina PHY ucode at 0x%x\n", + CONFIG_CORTINA_FW_ADDR); + return; + } + } + + addr++; /* skip '\n' */ + line_cnt++; + column_cnt = i; + line_temp[column_cnt] = '\0'; + + if (CONFIG_CORTINA_FW_LENGTH < line_cnt) + return; + + for (i = 0; i < column_cnt; i++) { + if (isspace(line_temp[i++])) + break; + } + + memcpy(reg_addr, line_temp, i); + memcpy(reg_data, &line_temp[i], column_cnt - i); + strim(reg_addr); + strim(reg_data); + fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; + fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & + 0xffff; + phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); + } +} + +int cs4340_phy_init(struct phy_device *phydev) +{ + int timeout = 100; /* 100ms */ + int reg_value; + + /* step1: BIST test */ + phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); + phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); + phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); + while (--timeout) { + reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); + if (reg_value & mseq_edc_bist_done) { + if (0 == (reg_value & mseq_edc_bist_fail)) + break; + } + udelay(1000); + } + + if (!timeout) { + printf("%s BIST mseq_edc_bist_done timeout!\n", __func__); + return -1; + } + + /* setp2: upload ucode */ + cs4340_upload_firmware(phydev); + reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); + if (reg_value) { + debug("%s checksum status failed.\n", __func__); + return -1; + } + + return 0; +} + +int cs4340_config(struct phy_device *phydev) +{ + cs4340_phy_init(phydev); + return 0; +} + +int cs4340_startup(struct phy_device *phydev) +{ + phydev->link = 1; + + /* For now just lie and say it's 10G all the time */ + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + return 0; +} + +struct phy_driver cs4340_driver = { + .name = "Cortina CS4315/CS4340", + .uid = PHY_UID_CS4340, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | + MDIO_DEVS_PHYXS | MDIO_DEVS_AN | + MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), + .config = &cs4340_config, + .startup = &cs4340_startup, + .shutdown = &gen10g_shutdown, +}; + +int phy_cortina_init(void) +{ + phy_register(&cs4340_driver); + return 0; +} + +int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +{ + int phy_reg; + bool is_cortina_phy = false; + + switch (addr) { +#ifdef CORTINA_PHY_ADDR1 + case CORTINA_PHY_ADDR1: +#endif +#ifdef CORTINA_PHY_ADDR2 + case CORTINA_PHY_ADDR2: +#endif +#ifdef CORTINA_PHY_ADDR3 + case CORTINA_PHY_ADDR3: +#endif +#ifdef CORTINA_PHY_ADDR4 + case CORTINA_PHY_ADDR4: +#endif + is_cortina_phy = true; + break; + default: + break; + } + + /* Cortina PHY has non-standard offset of PHY ID registers */ + if (is_cortina_phy) + phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB); + else + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + + if (phy_reg < 0) + return -EIO; + + *phy_id = (phy_reg & 0xffff) << 16; + if (is_cortina_phy) + phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB); + else + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + + if (phy_reg < 0) + return -EIO; + + *phy_id |= (phy_reg & 0xffff); + + return 0; +} diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c deleted file mode 100644 index 597195580b..0000000000 --- a/drivers/net/phy/icplus.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * ICPlus PHY drivers - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (c) 2007 Freescale Semiconductor, Inc. - */ -#include - -/* IP101A/G - IP1001 */ -#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */ -#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ -#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */ -#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ -#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ -#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ -#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */ -#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED - -static int ip1001_config(struct phy_device *phydev) -{ - int c; - - /* Enable Auto Power Saving mode */ - c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2); - if (c < 0) - return c; - c |= IP1001_APS_ON; - c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c); - if (c < 0) - return c; - - /* INTR pin used: speed/link/duplex will cause an interrupt */ - c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS, - IP101A_G_IRQ_DEFAULT); - if (c < 0) - return c; - - if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { - /* - * Additional delay (2ns) used to adjust RX clock phase - * at RGMII interface - */ - c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS); - if (c < 0) - return c; - - c |= IP1001_PHASE_SEL_MASK; - c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS, - c); - if (c < 0) - return c; - } - - return 0; -} - -static int ip1001_startup(struct phy_device *phydev) -{ - genphy_update_link(phydev); - genphy_parse_link(phydev); - - return 0; -} -static struct phy_driver IP1001_driver = { - .name = "ICPlus IP1001", - .uid = 0x02430d90, - .mask = 0x0ffffff0, - .features = PHY_GBIT_FEATURES, - .config = &ip1001_config, - .startup = &ip1001_startup, - .shutdown = &genphy_shutdown, -}; - -int phy_icplus_init(void) -{ - phy_register(&IP1001_driver); - - return 0; -} diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index d2ecadc890..9437c3bbcc 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -276,6 +276,57 @@ static int m88e1111s_config(struct phy_device *phydev) return 0; } +/** + * m88e1518_phy_writebits - write bits to a register + */ +void m88e1518_phy_writebits(struct phy_device *phydev, + u8 reg_num, u16 offset, u16 len, u16 data) +{ + u16 reg, mask; + + if ((len + offset) >= 16) + mask = 0 - (1 << offset); + else + mask = (1 << (len + offset)) - (1 << offset); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); + + reg &= ~mask; + reg |= data << offset; + + phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); +} + +static int m88e1518_config(struct phy_device *phydev) +{ + /* + * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 + * /88E1514 Rev A0, Errata Section 3.1 + */ + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); /* page 0xff */ + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); /* reg page 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); /* reg page 18 */ + /* Write HWCFG_MODE = SGMII to Copper */ + m88e1518_phy_writebits(phydev, 20, 0, 3, 1); + + /* Phy reset */ + m88e1518_phy_writebits(phydev, 20, 15, 1, 1); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); /* reg page 18 */ + udelay(100); + } + + return m88e1111s_config(phydev); +} + /* Marvell 88E1118 */ static int m88e1118_config(struct phy_device *phydev) { @@ -493,7 +544,7 @@ static struct phy_driver M88E1518_driver = { .uid = 0x1410dd1, .mask = 0xffffff0, .features = PHY_GBIT_FEATURES, - .config = &m88e1111s_config, + .config = &m88e1518_config, .startup = &m88e1011s_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index a7450f8326..1815b2900d 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -22,11 +22,67 @@ static struct phy_driver KSZ804_driver = { .shutdown = &genphy_shutdown, }; +/** + * KSZ8895 + */ + +static unsigned short smireg_to_phy(unsigned short reg) +{ + return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5); +} + +static unsigned short smireg_to_reg(unsigned short reg) +{ + return reg & 0x1F; +} + +static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val) +{ + phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, + smireg_to_reg(smireg), val); +} + +#if 0 +static int ksz8895_read_smireg(struct phy_device *phydev, int smireg) +{ + return phydev->bus->read(phydev->bus, smireg_to_phy(smireg), + MDIO_DEVAD_NONE, smireg_to_reg(smireg)); +} +#endif + +int ksz8895_config(struct phy_device *phydev) +{ + /* we are connected directly to the switch without + * dedicated PHY. SCONF1 == 001 */ + phydev->link = 1; + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_100; + + /* Force the switch to start */ + ksz8895_write_smireg(phydev, 1, 1); + + return 0; +} + +static int ksz8895_startup(struct phy_device *phydev) +{ + return 0; +} + +static struct phy_driver ksz8895_driver = { + .name = "Micrel KSZ8895/KSZ8864", + .uid = 0x221450, + .mask = 0xffffe1, + .features = PHY_BASIC_FEATURES, + .config = &ksz8895_config, + .startup = &ksz8895_startup, + .shutdown = &genphy_shutdown, +}; + #ifndef CONFIG_PHY_MICREL_KSZ9021 /* * I can't believe Micrel used the exact same part number - * for the KSZ9021 - * Shame Micrel, Shame!!!!! + * for the KSZ9021. Shame Micrel, Shame! */ static struct phy_driver KS8721_driver = { .name = "Micrel KS8721BL", @@ -40,7 +96,7 @@ static struct phy_driver KS8721_driver = { #endif -/** +/* * KSZ9021 - KSZ9031 common */ @@ -69,8 +125,8 @@ static int ksz90xx_startup(struct phy_device *phydev) phydev->speed = SPEED_10; return 0; } -#ifdef CONFIG_PHY_MICREL_KSZ9021 +#ifdef CONFIG_PHY_MICREL_KSZ9021 /* * KSZ9021 */ @@ -100,6 +156,19 @@ int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum) return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); } + +static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr, + int regnum) +{ + return ksz9021_phy_extended_read(phydev, regnum); +} + +static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + return ksz9021_phy_extended_write(phydev, regnum, val); +} + /* Micrel ksz9021 */ static int ksz9021_config(struct phy_device *phydev) { @@ -131,6 +200,8 @@ static struct phy_driver ksz9021_driver = { .config = &ksz9021_config, .startup = &ksz90xx_startup, .shutdown = &genphy_shutdown, + .writeext = &ksz9021_phy_extwrite, + .readext = &ksz9021_phy_extread, }; #endif @@ -171,14 +242,31 @@ int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr, return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA); } +static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr, + int regnum) +{ + return ksz9031_phy_extended_read(phydev, devaddr, regnum, + MII_KSZ9031_MOD_DATA_NO_POST_INC); +}; + +static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + return ksz9031_phy_extended_write(phydev, devaddr, regnum, + MII_KSZ9031_MOD_DATA_POST_INC_RW, val); +}; + + static struct phy_driver ksz9031_driver = { .name = "Micrel ksz9031", .uid = 0x221620, - .mask = 0xfffffe, + .mask = 0xfffff0, .features = PHY_GBIT_FEATURES, .config = &genphy_config, .startup = &ksz90xx_startup, .shutdown = &genphy_shutdown, + .writeext = &ksz9031_phy_extwrite, + .readext = &ksz9031_phy_extread, }; int phy_micrel_init(void) @@ -190,5 +278,6 @@ int phy_micrel_init(void) phy_register(&KS8721_driver); #endif phy_register(&ksz9031_driver); + phy_register(&ksz8895_driver); return 0; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 58ba5c2c2c..d35e35f7ed 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -18,6 +18,7 @@ #include #include #include +#include /* Generic PHY support and helper functions */ @@ -43,7 +44,6 @@ static int genphy_config_advert(struct phy_device *phydev) /* Setup standard advertisement */ oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); - if (adv < 0) return adv; @@ -78,7 +78,6 @@ static int genphy_config_advert(struct phy_device *phydev) if (phydev->supported & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)) { oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); - if (adv < 0) return adv; @@ -136,7 +135,6 @@ int genphy_restart_aneg(struct phy_device *phydev) int ctl; ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - if (ctl < 0) return ctl; @@ -287,20 +285,23 @@ int genphy_parse_link(struct phy_device *phydev) return mii_reg; /* We're using autonegotiation */ - if (mii_reg & BMSR_ANEGCAPABLE) { + if (phydev->supported & SUPPORTED_Autoneg) { int ret; - u16 lpa; - u16 gblpa = 0; - int estatus = 0; + u32 lpa = 0; + u32 gblpa = 0; + u32 estatus = 0; /* Check for gigabit capability */ - if (mii_reg & BMSR_ERCAP) { + if (phydev->supported & (SUPPORTED_1000baseT_Full | + SUPPORTED_1000baseT_Half)) { /* We want a list of states supported by * both PHYs in the link */ ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); - if (ret < 0) - return ret; + if (ret < 0) { + debug("Could not read MII_STAT1000. Ignoring gigabit capability\n"); + ret = 0; + } gblpa = ret; ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); @@ -400,7 +401,6 @@ int genphy_config(struct phy_device *phydev) /* Do we support autonegotiation? */ val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); - if (val < 0) return val; @@ -467,21 +467,24 @@ static LIST_HEAD(phy_drivers); int phy_init(void) { +#ifdef CONFIG_PHY_AQUANTIA + phy_aquantia_init(); +#endif #ifdef CONFIG_PHY_ATHEROS phy_atheros_init(); #endif #ifdef CONFIG_PHY_BROADCOM phy_broadcom_init(); #endif +#ifdef CONFIG_PHY_CORTINA + phy_cortina_init(); +#endif #ifdef CONFIG_PHY_DAVICOM phy_davicom_init(); #endif #ifdef CONFIG_PHY_ET1011C phy_et1011c_init(); #endif -#ifdef CONFIG_PHY_ICPLUS - phy_icplus_init(); -#endif #ifdef CONFIG_PHY_LXT phy_lxt_init(); #endif @@ -726,10 +729,8 @@ static struct phy_device *create_phy_by_mask(struct mii_dev *bus, while (phy_mask) { int addr = ffs(phy_mask) - 1; int r = get_phy_id(bus, addr, devad, &phy_id); - if (r < 0) - return ERR_PTR(r); /* If the PHY ID is mostly f's, we didn't find anything */ - if ((phy_id & 0x1fffffff) != 0x1fffffff) + if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) return phy_device_create(bus, addr, phy_id, interface); phy_mask &= ~(1 << addr); } @@ -770,7 +771,7 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, if (phydev) return phydev; } - printf("Phy not found\n"); + printf("Phy %d not found\n", ffs(phy_mask) - 1); return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface); } @@ -909,16 +910,13 @@ int phy_startup(struct phy_device *phydev) return 0; } -static int __board_phy_config(struct phy_device *phydev) +__weak int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) return phydev->drv->config(phydev); return 0; } -int board_phy_config(struct phy_device *phydev) - __attribute__((weak, alias("__board_phy_config"))); - int phy_config(struct phy_device *phydev) { /* Invoke an optional board-specific helper */ diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 606a103ce6..a3ace68526 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -12,18 +12,18 @@ #define PHY_AUTONEGOTIATE_TIMEOUT 5000 -/* RTL8211B PHY Status Register */ -#define MIIM_RTL8211B_PHY_STATUS 0x11 -#define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000 -#define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000 -#define MIIM_RTL8211B_PHYSTAT_100 0x4000 -#define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000 -#define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800 -#define MIIM_RTL8211B_PHYSTAT_LINK 0x0400 - - -/* RealTek RTL8211B */ -static int rtl8211b_config(struct phy_device *phydev) +/* RTL8211x PHY Status Register */ +#define MIIM_RTL8211x_PHY_STATUS 0x11 +#define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000 +#define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000 +#define MIIM_RTL8211x_PHYSTAT_100 0x4000 +#define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000 +#define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800 +#define MIIM_RTL8211x_PHYSTAT_LINK 0x0400 + + +/* RealTek RTL8211x */ +static int rtl8211x_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); @@ -32,20 +32,20 @@ static int rtl8211b_config(struct phy_device *phydev) return 0; } -static int rtl8211b_parse_status(struct phy_device *phydev) +static int rtl8211x_parse_status(struct phy_device *phydev) { unsigned int speed; unsigned int mii_reg; - mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211B_PHY_STATUS); + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS); - if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { + if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { int i = 0; /* in case of timeout ->link is cleared */ phydev->link = 1; puts("Waiting for PHY realtime link"); - while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { + while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { /* Timeout reached ? */ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts(" TIMEOUT !\n"); @@ -57,29 +57,29 @@ static int rtl8211b_parse_status(struct phy_device *phydev) putc('.'); udelay(1000); /* 1 ms */ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, - MIIM_RTL8211B_PHY_STATUS); + MIIM_RTL8211x_PHY_STATUS); } puts(" done\n"); udelay(500000); /* another 500 ms (results in faster booting) */ } else { - if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) + if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK) phydev->link = 1; else phydev->link = 0; } - if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) + if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX) phydev->duplex = DUPLEX_FULL; else phydev->duplex = DUPLEX_HALF; - speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); + speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED); switch (speed) { - case MIIM_RTL8211B_PHYSTAT_GBIT: + case MIIM_RTL8211x_PHYSTAT_GBIT: phydev->speed = SPEED_1000; break; - case MIIM_RTL8211B_PHYSTAT_100: + case MIIM_RTL8211x_PHYSTAT_100: phydev->speed = SPEED_100; break; default: @@ -89,28 +89,53 @@ static int rtl8211b_parse_status(struct phy_device *phydev) return 0; } -static int rtl8211b_startup(struct phy_device *phydev) +static int rtl8211x_startup(struct phy_device *phydev) { /* Read the Status (2x to make sure link is right) */ genphy_update_link(phydev); - rtl8211b_parse_status(phydev); + rtl8211x_parse_status(phydev); return 0; } +/* Support for RTL8211B PHY */ static struct phy_driver RTL8211B_driver = { .name = "RealTek RTL8211B", .uid = 0x1cc910, - .mask = 0xfffff0, + .mask = 0xffffff, .features = PHY_GBIT_FEATURES, - .config = &rtl8211b_config, - .startup = &rtl8211b_startup, + .config = &rtl8211x_config, + .startup = &rtl8211x_startup, + .shutdown = &genphy_shutdown, +}; + +/* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */ +static struct phy_driver RTL8211E_driver = { + .name = "RealTek RTL8211E", + .uid = 0x1cc915, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .config = &rtl8211x_config, + .startup = &rtl8211x_startup, + .shutdown = &genphy_shutdown, +}; + +/* Support for RTL8211DN PHY */ +static struct phy_driver RTL8211DN_driver = { + .name = "RealTek RTL8211DN", + .uid = 0x1cc914, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .config = &rtl8211x_config, + .startup = &rtl8211x_startup, .shutdown = &genphy_shutdown, }; int phy_realtek_init(void) { phy_register(&RTL8211B_driver); + phy_register(&RTL8211E_driver); + phy_register(&RTL8211DN_driver); return 0; } diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index c562f9f0be..1001d44852 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -7,7 +7,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming * - * Some code get from linux kenrel + * Some code copied from linux kernel * Copyright (c) 2006 Herbert Valerio Riedel */ #include @@ -17,6 +17,7 @@ #define MII_LAN83C185_EDPWRDOWN (1 << 13) /* EDPWRDOWN */ #define MII_LAN83C185_ENERGYON (1 << 1) /* ENERGYON */ +/* This code does not check the partner abilities. */ static int smsc_parse_status(struct phy_device *phydev) { int bmcr; @@ -182,7 +183,7 @@ static struct phy_driver lan8710_driver = { .name = "SMSC LAN8710/LAN8720", .uid = 0x0007c0f0, .mask = 0xffff0, - .features = PHY_GBIT_FEATURES, + .features = PHY_BASIC_FEATURES, .config = &smsc_config, .startup = &smsc_startup, .shutdown = &genphy_shutdown, diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 5cf103e5a1..20a67466a7 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -1,8 +1,8 @@ /* * Vitesse PHY drivers * - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * Author: Andy Fleming + * Copyright 2010-2014 Freescale Semiconductor, Inc. + * Original Author: Andy Fleming * Add vsc8662 phy support - Priyanka Jain * SPDX-License-Identifier: GPL-2.0+ */ @@ -49,6 +49,24 @@ #define MIIM_VSC8574_18G_QSGMII 0x80e0 #define MIIM_VSC8574_18G_CMDSTAT 0x8000 +/* Vitesse VSC8514 control register */ +#define MIIM_VSC8514_MAC_SERDES_CON 0x10 +#define MIIM_VSC8514_GENERAL18 0x12 +#define MIIM_VSC8514_GENERAL19 0x13 +#define MIIM_VSC8514_GENERAL23 0x17 + +/* Vitesse VSC8514 gerenal purpose register 18 */ +#define MIIM_VSC8514_18G_QSGMII 0x80e0 +#define MIIM_VSC8514_18G_CMDSTAT 0x8000 + +/* Vitesse VSC8664 Control/Status Register */ +#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13 +#define MIIM_VSC8664_ADDITIONAL_DEV 0x16 +#define MIIM_VSC8664_EPHY_CON 0x17 +#define MIIM_VSC8664_LED_CON 0x1E + +#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001 + /* CIS8201 */ static int vitesse_config(struct phy_device *phydev) { @@ -109,7 +127,6 @@ static int cis8204_config(struct phy_device *phydev) genphy_config_aneg(phydev); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, @@ -148,7 +165,7 @@ static int vsc8601_config(struct phy_device *phydev) static int vsc8574_config(struct phy_device *phydev) { u32 val; - /* configure regiser 19G for MAC */ + /* configure register 19G for MAC */ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, PHY_EXT_PAGE_ACCESS_GENERAL); @@ -188,6 +205,88 @@ static int vsc8574_config(struct phy_device *phydev) return 0; } +static int vsc8514_config(struct phy_device *phydev) +{ + u32 val; + int timeout = 1000000; + + /* configure register to access 19G */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_GENERAL); + + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19); + if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { + /* set bit 15:14 to '01' for QSGMII mode */ + val = (val & 0x3fff) | (1 << 14); + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_VSC8514_GENERAL19, val); + /* Enable 4 ports MAC QSGMII */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18, + MIIM_VSC8514_18G_QSGMII); + } else { + /*TODO Add SGMII functionality once spec sheet + * for VSC8514 defines complete functionality + */ + } + + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); + /* When bit 15 is cleared the command has completed */ + while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--) + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); + + if (0 == timeout) { + printf("PHY 8514 config failed\n"); + return -1; + } + + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + /* configure register to access 23 */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23); + /* set bits 10:8 to '000' */ + val = (val & 0xf8ff); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val); + + /* Enable Serdes Auto-negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_EXTENDED3); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON); + val = val | MIIM_VSC8574_MAC_SERDES_ANEG; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val); + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + genphy_config_aneg(phydev); + + return 0; +} + +static int vsc8664_config(struct phy_device *phydev) +{ + u32 val; + + /* Enable MAC interface auto-negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON); + val |= (1 << 13); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val); + + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_EXTENDED); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET); + val |= (1 << 11); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val); + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + /* Enable LED blink */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON); + val &= ~(1 << 2); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val); + + genphy_config_aneg(phydev); + + return 0; +} + static struct phy_driver VSC8211_driver = { .name = "Vitesse VSC8211", .uid = 0xfc4b0, @@ -238,6 +337,16 @@ static struct phy_driver VSC8574_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver VSC8514_driver = { + .name = "Vitesse VSC8514", + .uid = 0x70670, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8514_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + static struct phy_driver VSC8601_driver = { .name = "Vitesse VSC8601", .uid = 0x70420, @@ -268,6 +377,16 @@ static struct phy_driver VSC8662_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver VSC8664_driver = { + .name = "Vitesse VSC8664", + .uid = 0x70660, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8664_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + /* Vitesse bought Cicada, so we'll put these here */ static struct phy_driver cis8201_driver = { .name = "CIS8201", @@ -298,7 +417,9 @@ int phy_vitesse_init(void) phy_register(&VSC8211_driver); phy_register(&VSC8221_driver); phy_register(&VSC8574_driver); + phy_register(&VSC8514_driver); phy_register(&VSC8662_driver); + phy_register(&VSC8664_driver); phy_register(&cis8201_driver); phy_register(&cis8204_driver); diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c deleted file mode 100644 index 8aefc14144..0000000000 --- a/drivers/net/plb2800_eth.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * PLB2800 internal switch ethernet driver. - * - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - - -#define NUM_RX_DESC PKTBUFSRX -#define TOUT_LOOP 1000000 - -#define LONG_REF(addr) (*((volatile unsigned long*)addr)) - -#define CMAC_CRX_CTRL LONG_REF(0xb800c870) -#define CMAC_CTX_CTRL LONG_REF(0xb800c874) -#define SYS_MAC_ADDR_0 LONG_REF(0xb800c878) -#define SYS_MAC_ADDR_1 LONG_REF(0xb800c87c) -#define MIPS_H_MASK LONG_REF(0xB800C810) - -#define MA_LEARN LONG_REF(0xb8008004) -#define DA_LOOKUP LONG_REF(0xb8008008) - -#define CMAC_CRX_CTRL_PD 0x00000001 -#define CMAC_CRX_CTRL_CG 0x00000002 -#define CMAC_CRX_CTRL_PL_SHIFT 2 -#define CMAC_CRIT 0x0 -#define CMAC_NON_CRIT 0x1 -#define MBOX_STAT_ID_SHF 28 -#define MBOX_STAT_CP 0x80000000 -#define MBOX_STAT_MB 0x00000001 -#define EN_MA_LEARN 0x02000000 -#define EN_DA_LKUP 0x01000000 -#define MA_DEST_SHF 11 -#define DA_DEST_SHF 11 -#define DA_STATE_SHF 19 -#define TSTAMP_MS 0x00000000 -#define SW_H_MBOX4_MASK 0x08000000 -#define SW_H_MBOX3_MASK 0x04000000 -#define SW_H_MBOX2_MASK 0x02000000 -#define SW_H_MBOX1_MASK 0x01000000 - -typedef volatile struct { - unsigned int stat; - unsigned int cmd; - unsigned int cnt; - unsigned int adr; -} mailbox_t; - -#define MBOX_REG(mb) ((mailbox_t*)(0xb800c830+(mb<<4))) - -typedef volatile struct { - unsigned int word0; - unsigned int word1; - unsigned int word2; -} mbhdr_t; - -#define MBOX_MEM(mb) ((void*)(0xb800a000+((3-mb)<<11))) - - -static int plb2800_eth_init(struct eth_device *dev, bd_t * bis); -static int plb2800_eth_send(struct eth_device *dev, void *packet, int length); -static int plb2800_eth_recv(struct eth_device *dev); -static void plb2800_eth_halt(struct eth_device *dev); - -static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr); -static unsigned char * plb2800_get_mac_addr(void); - -static int rx_new; -static int mac_addr_set = 0; - - -int plb2800_eth_initialize(bd_t * bis) -{ - struct eth_device *dev; - ulong temp; - -#ifdef DEBUG - printf("Entered plb2800_eth_initialize()\n"); -#endif - - if (!(dev = (struct eth_device *) malloc (sizeof *dev))) - { - printf("Failed to allocate memory\n"); - return -1; - } - memset(dev, 0, sizeof(*dev)); - - sprintf(dev->name, "PLB2800 Switch"); - dev->init = plb2800_eth_init; - dev->halt = plb2800_eth_halt; - dev->send = plb2800_eth_send; - dev->recv = plb2800_eth_recv; - - eth_register(dev); - - /* bug fix */ - *(ulong *)0xb800e800 = 0x838; - - /* Set MBOX ownership */ - temp = CMAC_CRIT << MBOX_STAT_ID_SHF; - MBOX_REG(0)->stat = temp; - MBOX_REG(1)->stat = temp; - - temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF; - MBOX_REG(2)->stat = temp; - MBOX_REG(3)->stat = temp; - - plb2800_set_mac_addr(dev, plb2800_get_mac_addr()); - - /* Disable all Mbox interrupt */ - temp = MIPS_H_MASK; - temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ; - MIPS_H_MASK = temp; - -#ifdef DEBUG - printf("Leaving plb2800_eth_initialize()\n"); -#endif - - return 0; -} - -static int plb2800_eth_init(struct eth_device *dev, bd_t * bis) -{ -#ifdef DEBUG - printf("Entering plb2800_eth_init()\n"); -#endif - - plb2800_set_mac_addr(dev, dev->enetaddr); - - rx_new = 0; - -#ifdef DEBUG - printf("Leaving plb2800_eth_init()\n"); -#endif - - return 0; -} - - -static int plb2800_eth_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int res = -1; - u32 temp; - mailbox_t * mb = MBOX_REG(0); - char * mem = MBOX_MEM(0); - -#ifdef DEBUG - printf("Entered plb2800_eth_send()\n"); -#endif - - if (length <= 0) - { - printf ("%s: bad packet size: %d\n", dev->name, length); - goto Done; - } - - if (length < 64) - { - length = 64; - } - - temp = CMAC_CRX_CTRL_CG | ((length + 4) << CMAC_CRX_CTRL_PL_SHIFT); - -#ifdef DEBUG - printf("0 mb->stat = 0x%x\n", mb->stat); -#endif - - for(i = 0; mb->stat & (MBOX_STAT_CP | MBOX_STAT_MB); i++) - { - if (i >= TOUT_LOOP) - { - printf("%s: tx buffer not ready\n", dev->name); - printf("1 mb->stat = 0x%x\n", mb->stat); - goto Done; - } - } - - /* For some strange reason, memcpy doesn't work, here! - */ - do - { - int words = (length >> 2) + 1; - unsigned int* dst = (unsigned int*)(mem); - unsigned int* src = (unsigned int*)(packet); - for (i = 0; i < words; i++) - { - *dst = *src; - dst++; - src++; - }; - } while(0); - - CMAC_CRX_CTRL = temp; - mb->cmd = MBOX_STAT_CP; - -#ifdef DEBUG - printf("2 mb->stat = 0x%x\n", mb->stat); -#endif - - res = length; -Done: - -#ifdef DEBUG - printf("Leaving plb2800_eth_send()\n"); -#endif - - return res; -} - - -static int plb2800_eth_recv(struct eth_device *dev) -{ - int length = 0; - mailbox_t * mbox = MBOX_REG(3); - unsigned char * hdr = MBOX_MEM(3); - unsigned int stat; - -#ifdef DEBUG - printf("Entered plb2800_eth_recv()\n"); -#endif - - for (;;) - { - stat = mbox->stat; - - if (!(stat & MBOX_STAT_CP)) - { - break; - } - - length = ((*(hdr + 6) & 0x3f) << 8) + *(hdr + 7); - memcpy((void *)NetRxPackets[rx_new], hdr + 12, length); - - stat &= ~MBOX_STAT_CP; - mbox->stat = stat; -#ifdef DEBUG - { - int i; - for (i=0;i +#include #include #include #include @@ -79,7 +80,11 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ -#define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ +#ifdef CONFIG_SYS_RX_ETH_BUFFER + #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER +#else + #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ +#endif #define RX_BUF_SIZE 1536 /* Rx Buffer size */ #define RX_BUF_LEN 8192 @@ -246,6 +251,9 @@ static struct { {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, + {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, + {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, + {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, {"RTL-8101e", 0x34, 0xff7e1880,}, {"RTL-8100e", 0x32, 0xff7e1880,}, }; @@ -271,23 +279,40 @@ struct RxDesc { u32 buf_Haddr; }; -/* Define the TX Descriptor */ -static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; -/* __attribute__ ((aligned(256))); */ +#define RTL8169_DESC_SIZE 16 -/* Create a static buffer of size RX_BUF_SZ for each -TX Descriptor. All descriptors point to a -part of this buffer */ -static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; +#if ARCH_DMA_MINALIGN > 256 +# define RTL8169_ALIGN ARCH_DMA_MINALIGN +#else +# define RTL8169_ALIGN 256 +#endif -/* Define the RX Descriptor */ -static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; - /* __attribute__ ((aligned(256))); */ +/* + * Warn if the cache-line size is larger than the descriptor size. In such + * cases the driver will likely fail because the CPU needs to flush the cache + * when requeuing RX buffers, therefore descriptors written by the hardware + * may be discarded. + * + * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause + * the driver to allocate descriptors from a pool of non-cached memory. + */ +#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN +#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && !defined(CONFIG_SYS_DCACHE_OFF) +#warning cache-line size is larger than descriptor size +#endif +#endif + +/* + * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All + * descriptors point to a part of this buffer. + */ +DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); -/* Create a static buffer of size RX_BUF_SZ for each -RX Descriptor All descriptors point to a -part of this buffer */ -static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; +/* + * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All + * descriptors point to a part of this buffer. + */ +DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); struct rtl8169_private { void *mmio_addr; /* memory map physical address */ @@ -295,8 +320,6 @@ struct rtl8169_private { unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ unsigned long dirty_tx; - unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ - unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ unsigned char *RxBufferRings; /* Index of Rx Buffer */ @@ -314,6 +337,7 @@ static const unsigned int rtl8169_rx_config = static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, 0x8167}, + {PCI_VENDOR_ID_REALTEK, 0x8168}, {PCI_VENDOR_ID_REALTEK, 0x8169}, {} }; @@ -394,6 +418,87 @@ match: return 0; } +/* + * TX and RX descriptors are 16 bytes. This causes problems with the cache + * maintenance on CPUs where the cache-line size exceeds the size of these + * descriptors. What will happen is that when the driver receives a packet + * it will be immediately requeued for the hardware to reuse. The CPU will + * therefore need to flush the cache-line containing the descriptor, which + * will cause all other descriptors in the same cache-line to be flushed + * along with it. If one of those descriptors had been written to by the + * device those changes (and the associated packet) will be lost. + * + * To work around this, we make use of non-cached memory if available. If + * descriptors are mapped uncached there's no need to manually flush them + * or invalidate them. + * + * Note that this only applies to descriptors. The packet data buffers do + * not have the same constraints since they are 1536 bytes large, so they + * are unlikely to share cache-lines. + */ +static void *rtl_alloc_descs(unsigned int num) +{ + size_t size = num * RTL8169_DESC_SIZE; + +#ifdef CONFIG_SYS_NONCACHED_MEMORY + return (void *)noncached_alloc(size, RTL8169_ALIGN); +#else + return memalign(RTL8169_ALIGN, size); +#endif +} + +/* + * Cache maintenance functions. These are simple wrappers around the more + * general purpose flush_cache() and invalidate_dcache_range() functions. + */ + +static void rtl_inval_rx_desc(struct RxDesc *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +#endif +} + +static void rtl_flush_rx_desc(struct RxDesc *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + flush_cache((unsigned long)desc, sizeof(*desc)); +#endif +} + +static void rtl_inval_tx_desc(struct TxDesc *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +#endif +} + +static void rtl_flush_tx_desc(struct TxDesc *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + flush_cache((unsigned long)desc, sizeof(*desc)); +#endif +} + +static void rtl_inval_buffer(void *buf, size_t size) +{ + unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +static void rtl_flush_buffer(void *buf, size_t size) +{ + flush_cache((unsigned long)buf, size); +} + /************************************************************************** RECV - Receive a frame ***************************************************************************/ @@ -411,16 +516,17 @@ static int rtl_recv(struct eth_device *dev) ioaddr = dev->iobase; cur_rx = tpc->cur_rx; - flush_cache((unsigned long)&tpc->RxDescArray[cur_rx], - sizeof(struct RxDesc)); + + rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); + if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { unsigned char rxdata[RX_BUF_LEN]; length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. status) & 0x00001FFF) - 4; + rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); - NetReceive(rxdata, length); if (cur_rx == NUM_RX_DESC - 1) tpc->RxDescArray[cur_rx].status = @@ -430,8 +536,9 @@ static int rtl_recv(struct eth_device *dev) cpu_to_le32(OWNbit + RX_BUF_SIZE); tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); - flush_cache((unsigned long)tpc->RxBufferRing[cur_rx], - RX_BUF_SIZE); + rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); + + NetReceive(rxdata, length); } else { puts("Error Rx"); } @@ -473,7 +580,7 @@ static int rtl_send(struct eth_device *dev, void *packet, int length) /* point to the current txb incase multiple tx_rings are used */ ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; memcpy(ptxb, (char *)packet, (int)length); - flush_cache((unsigned long)ptxb, length); + rtl_flush_buffer(ptxb, length); while (len < ETH_ZLEN) ptxb[len++] = '\0'; @@ -489,20 +596,20 @@ static int rtl_send(struct eth_device *dev, void *packet, int length) cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? len : ETH_ZLEN)); } + rtl_flush_tx_desc(&tpc->TxDescArray[entry]); RTL_W8(TxPoll, 0x40); /* set polling bit */ tpc->cur_tx++; to = currticks() + TX_TIMEOUT; do { - flush_cache((unsigned long)&tpc->TxDescArray[entry], - sizeof(struct TxDesc)); + rtl_inval_tx_desc(&tpc->TxDescArray[entry]); } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) && (currticks() < to)); /* wait */ if (currticks() >= to) { #ifdef DEBUG_RTL8169_TX - puts ("tx timeout/error\n"); - printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + puts("tx timeout/error\n"); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif ret = 0; } else { @@ -604,7 +711,7 @@ static void rtl8169_hw_start(struct eth_device *dev) RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); #ifdef DEBUG_RTL8169 - printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif } @@ -638,11 +745,11 @@ static void rtl8169_init_ring(struct eth_device *dev) tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; tpc->RxDescArray[i].buf_addr = cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); - flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE); + rtl_flush_rx_desc(&tpc->RxDescArray[i]); } #ifdef DEBUG_RTL8169 - printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif } @@ -658,16 +765,6 @@ static int rtl_reset(struct eth_device *dev, bd_t *bis) printf ("%s\n", __FUNCTION__); #endif - tpc->TxDescArrays = tx_ring; - /* Tx Desscriptor needs 256 bytes alignment; */ - tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + - 255) & ~255); - - tpc->RxDescArrays = rx_ring; - /* Rx Desscriptor needs 256 bytes alignment; */ - tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + - 255) & ~255); - rtl8169_init_ring(dev); rtl8169_hw_start(dev); /* Construct a perfect filter frame with the mac address as first match @@ -683,7 +780,7 @@ static int rtl_reset(struct eth_device *dev, bd_t *bis) txb[5] = dev->enetaddr[5]; #ifdef DEBUG_RTL8169 - printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif return 0; } @@ -709,10 +806,6 @@ static void rtl_halt(struct eth_device *dev) RTL_W32(RxMissed, 0); - tpc->TxDescArrays = NULL; - tpc->RxDescArrays = NULL; - tpc->TxDescArray = NULL; - tpc->RxDescArray = NULL; for (i = 0; i < NUM_RX_DESC; i++) { tpc->RxBufferRing[i] = NULL; } @@ -857,7 +950,16 @@ static int rtl_init(struct eth_device *dev, bd_t *bis) #endif } - return 1; + + tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); + if (!tpc->RxDescArray) + return -ENOMEM; + + tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); + if (!tpc->TxDescArray) + return -ENOMEM; + + return 0; } int rtl8169_initialize(bd_t *bis) @@ -869,11 +971,26 @@ int rtl8169_initialize(bd_t *bis) int idx=0; while(1){ + unsigned int region; + u16 device; + int err; + /* Find RTL8169 */ if ((devno = pci_find_devices(supported, idx++)) < 0) break; - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + pci_read_config_word(devno, PCI_DEVICE_ID, &device); + switch (device) { + case 0x8168: + region = 2; + break; + + default: + region = 1; + break; + } + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); iobase &= ~0xf; debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); @@ -895,9 +1012,14 @@ int rtl8169_initialize(bd_t *bis) dev->send = rtl_send; dev->recv = rtl_recv; - eth_register (dev); + err = rtl_init(dev, bis); + if (err < 0) { + printf(pr_fmt("failed to initialize card: %d\n"), err); + free(dev); + continue; + } - rtl_init(dev, bis); + eth_register (dev); card_number++; } diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index d5a83e0bf5..4bf493ed45 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -2,8 +2,9 @@ * sh_eth.c - Driver for Renesas ethernet controler. * * Copyright (C) 2008, 2011 Renesas Solutions Corp. - * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu + * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu * Copyright (c) 2007 Carlos Munoz + * Copyright (C) 2013, 2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -25,13 +26,31 @@ #ifndef CONFIG_SH_ETHER_PHY_ADDR # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif -#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK -#define flush_cache_wback(addr, len) \ - dcache_wback_range((u32)addr, (u32)(addr + len - 1)) + +#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) +#define flush_cache_wback(addr, len) \ + flush_dcache_range((u32)addr, (u32)(addr + len - 1)) #else #define flush_cache_wback(...) #endif +#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) +#define invalidate_cache(addr, len) \ + { \ + u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ + u32 start, end; \ + \ + start = (u32)addr; \ + end = start + len; \ + start &= ~(line_size - 1); \ + end = ((end + line_size - 1) & ~(line_size - 1)); \ + \ + invalidate_dcache_range(start, end); \ + } +#else +#define invalidate_cache(...) +#endif + #define TIMEOUT_CNT 1000 int sh_eth_send(struct eth_device *dev, void *packet, int len) @@ -48,7 +67,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len) /* packet must be a 4 byte boundary */ if ((int)packet & 3) { - printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); + printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n" + , __func__); ret = -EFAULT; goto err; } @@ -63,14 +83,19 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len) else port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; + flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s)); + /* Restart the transmitter if disabled */ if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) sh_eth_write(eth, EDTRR_TRNS, EDTRR); /* Wait until packet is transmitted */ timeout = TIMEOUT_CNT; - while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) + do { + invalidate_cache(port_info->tx_desc_cur, + sizeof(struct tx_desc_s)); udelay(100); + } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); if (timeout < 0) { printf(SHETHER_NAME ": transmit timeout\n"); @@ -94,12 +119,14 @@ int sh_eth_recv(struct eth_device *dev) uchar *packet; /* Check if the rx descriptor is ready */ + invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { /* Check for errors */ if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { len = port_info->rx_desc_cur->rd1 & 0xffff; packet = (uchar *) ADDR_TO_P2(port_info->rx_desc_cur->rd2); + invalidate_cache(packet, len); NetReceive(packet, len); } @@ -109,6 +136,9 @@ int sh_eth_recv(struct eth_device *dev) else port_info->rx_desc_cur->rd0 = RD_RACT; + flush_cache_wback(port_info->rx_desc_cur, + sizeof(struct rx_desc_s)); + /* Point to the next descriptor */ port_info->rx_desc_cur++; if (port_info->rx_desc_cur >= @@ -125,7 +155,7 @@ int sh_eth_recv(struct eth_device *dev) static int sh_eth_reset(struct sh_eth_dev *eth) { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) int ret = 0, i; /* Start e-dmac transmitter and receiver */ @@ -133,7 +163,7 @@ static int sh_eth_reset(struct sh_eth_dev *eth) /* Perform a software reset and wait for it to complete */ sh_eth_write(eth, EDMR_SRST, EDMR); - for (i = 0; i < TIMEOUT_CNT ; i++) { + for (i = 0; i < TIMEOUT_CNT; i++) { if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) break; udelay(1000); @@ -157,27 +187,27 @@ static int sh_eth_reset(struct sh_eth_dev *eth) static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) { int port = eth->port, i, ret = 0; - u32 tmp_addr; + u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); struct sh_eth_info *port_info = ð->port_info[port]; struct tx_desc_s *cur_tx_desc; /* - * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned + * Allocate rx descriptors. They must be aligned to size of struct + * tx_desc_s. */ - port_info->tx_desc_malloc = malloc(NUM_TX_DESC * - sizeof(struct tx_desc_s) + - TX_DESC_SIZE - 1); - if (!port_info->tx_desc_malloc) { - printf(SHETHER_NAME ": malloc failed\n"); + port_info->tx_desc_alloc = + memalign(sizeof(struct tx_desc_s), alloc_desc_size); + if (!port_info->tx_desc_alloc) { + printf(SHETHER_NAME ": memalign failed\n"); ret = -ENOMEM; goto err; } - tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & - ~(TX_DESC_SIZE - 1)); - flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); + flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size); + /* Make sure we use a P2 address (non-cacheable) */ - port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); + port_info->tx_desc_base = + (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc); port_info->tx_desc_cur = port_info->tx_desc_base; /* Initialize all descriptors */ @@ -195,7 +225,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the tx descriptor list. Must use physical addresses */ sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ @@ -208,45 +238,44 @@ err: static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) { int port = eth->port, i , ret = 0; + u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); struct sh_eth_info *port_info = ð->port_info[port]; struct rx_desc_s *cur_rx_desc; - u32 tmp_addr; u8 *rx_buf; /* - * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned + * Allocate rx descriptors. They must be aligned to size of struct + * rx_desc_s. */ - port_info->rx_desc_malloc = malloc(NUM_RX_DESC * - sizeof(struct rx_desc_s) + - RX_DESC_SIZE - 1); - if (!port_info->rx_desc_malloc) { - printf(SHETHER_NAME ": malloc failed\n"); + port_info->rx_desc_alloc = + memalign(sizeof(struct rx_desc_s), alloc_desc_size); + if (!port_info->rx_desc_alloc) { + printf(SHETHER_NAME ": memalign failed\n"); ret = -ENOMEM; goto err; } - tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & - ~(RX_DESC_SIZE - 1)); - flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); + flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); + /* Make sure we use a P2 address (non-cacheable) */ - port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); + port_info->rx_desc_base = + (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc); port_info->rx_desc_cur = port_info->rx_desc_base; /* - * Allocate rx data buffers. They must be 32 bytes aligned and in - * P2 area + * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes + * aligned and in P2 area. */ - port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); - if (!port_info->rx_buf_malloc) { - printf(SHETHER_NAME ": malloc failed\n"); + port_info->rx_buf_alloc = + memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE); + if (!port_info->rx_buf_alloc) { + printf(SHETHER_NAME ": alloc failed\n"); ret = -ENOMEM; - goto err_buf_malloc; + goto err_buf_alloc; } - tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & - ~(32 - 1)); - port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); + port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc); /* Initialize all descriptors */ for (cur_rx_desc = port_info->rx_desc_base, @@ -263,7 +292,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the rx descriptor list */ sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); sh_eth_write(eth, RDFFR_RDLF, RDFFR); @@ -271,9 +300,9 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) return ret; -err_buf_malloc: - free(port_info->rx_desc_malloc); - port_info->rx_desc_malloc = NULL; +err_buf_alloc: + free(port_info->rx_desc_alloc); + port_info->rx_desc_alloc = NULL; err: return ret; @@ -284,9 +313,9 @@ static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) int port = eth->port; struct sh_eth_info *port_info = ð->port_info[port]; - if (port_info->tx_desc_malloc) { - free(port_info->tx_desc_malloc); - port_info->tx_desc_malloc = NULL; + if (port_info->tx_desc_alloc) { + free(port_info->tx_desc_alloc); + port_info->tx_desc_alloc = NULL; } } @@ -295,14 +324,14 @@ static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) int port = eth->port; struct sh_eth_info *port_info = ð->port_info[port]; - if (port_info->rx_desc_malloc) { - free(port_info->rx_desc_malloc); - port_info->rx_desc_malloc = NULL; + if (port_info->rx_desc_alloc) { + free(port_info->rx_desc_alloc); + port_info->rx_desc_alloc = NULL; } - if (port_info->rx_buf_malloc) { - free(port_info->rx_buf_malloc); - port_info->rx_buf_malloc = NULL; + if (port_info->rx_buf_alloc) { + free(port_info->rx_buf_alloc); + port_info->rx_buf_alloc = NULL; } } @@ -351,14 +380,15 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) struct phy_device *phy; /* Configure e-dmac registers */ - sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, - EDMR); + sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | + (EMDR_DESC | EDMR_EL), EDMR); + sh_eth_write(eth, 0, EESIPR); sh_eth_write(eth, 0, TRSCER); sh_eth_write(eth, 0, TFTR); sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); sh_eth_write(eth, RMCR_RST, RMCR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, 0, RPADIR); #endif sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); @@ -377,6 +407,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, RFLR_RFL_MIN, RFLR); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, 0, PIPR); +#endif +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, APR_AP, APR); sh_eth_write(eth, MPR_MP, MPR); sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); @@ -384,6 +416,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) + sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); #endif /* Configure phy */ ret = sh_eth_phy_config(eth); @@ -407,7 +442,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) sh_eth_write(eth, 1, RTRATE); -#elif defined(CONFIG_CPU_SH7724) +#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ + defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ + defined(CONFIG_R8A7794) val = ECMR_RTM; #endif } else if (phy->speed == 10) { @@ -492,41 +529,41 @@ void sh_eth_halt(struct eth_device *dev) int sh_eth_initialize(bd_t *bd) { - int ret = 0; + int ret = 0; struct sh_eth_dev *eth = NULL; - struct eth_device *dev = NULL; + struct eth_device *dev = NULL; - eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); + eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); if (!eth) { printf(SHETHER_NAME ": %s: malloc failed\n", __func__); ret = -ENOMEM; goto err; } - dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) { printf(SHETHER_NAME ": %s: malloc failed\n", __func__); ret = -ENOMEM; goto err; } - memset(dev, 0, sizeof(struct eth_device)); - memset(eth, 0, sizeof(struct sh_eth_dev)); + memset(dev, 0, sizeof(struct eth_device)); + memset(eth, 0, sizeof(struct sh_eth_dev)); eth->port = CONFIG_SH_ETHER_USE_PORT; eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; - dev->priv = (void *)eth; - dev->iobase = 0; - dev->init = sh_eth_init; - dev->halt = sh_eth_halt; - dev->send = sh_eth_send; - dev->recv = sh_eth_recv; - eth->port_info[eth->port].dev = dev; + dev->priv = (void *)eth; + dev->iobase = 0; + dev->init = sh_eth_init; + dev->halt = sh_eth_halt; + dev->send = sh_eth_send; + dev->recv = sh_eth_recv; + eth->port_info[eth->port].dev = dev; sprintf(dev->name, SHETHER_NAME); - /* Register Device to EtherNet subsystem */ - eth_register(dev); + /* Register Device to EtherNet subsystem */ + eth_register(dev); bb_miiphy_buses[0].priv = eth; miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 9ad800e427..5cb520c63e 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -31,6 +31,11 @@ #define ADDR_TO_P2(addr) (addr) #endif /* defined(CONFIG_SH) */ +/* base padding size is 16 */ +#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 16 +#endif + /* Number of supported ports */ #define MAX_PORT_NUM 2 @@ -45,15 +50,14 @@ /* The size of the tx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define TX_DESC_PADDING 4 -#define TX_DESC_SIZE (12 + TX_DESC_PADDING) +#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) /* Tx descriptor. We always use 3 bytes of padding */ struct tx_desc_s { volatile u32 td0; u32 td1; u32 td2; /* Buffer start */ - u32 padding; + u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ }; /* There is no limitation in the number of rx descriptors */ @@ -61,25 +65,26 @@ struct tx_desc_s { /* The size of the rx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define RX_DESC_PADDING 4 -#define RX_DESC_SIZE (12 + RX_DESC_PADDING) +#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +/* aligned cache line size */ +#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) /* Rx descriptor. We always use 4 bytes of padding */ struct rx_desc_s { volatile u32 rd0; volatile u32 rd1; u32 rd2; /* Buffer start */ - u32 padding; + u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ }; struct sh_eth_info { - struct tx_desc_s *tx_desc_malloc; + struct tx_desc_s *tx_desc_alloc; struct tx_desc_s *tx_desc_base; struct tx_desc_s *tx_desc_cur; - struct rx_desc_s *rx_desc_malloc; + struct rx_desc_s *rx_desc_alloc; struct rx_desc_s *rx_desc_base; struct rx_desc_s *rx_desc_cur; - u8 *rx_buf_malloc; + u8 *rx_buf_alloc; u8 *rx_buf_base; u8 mac_addr[6]; u8 phy_addr; @@ -157,6 +162,7 @@ enum { TLFRCR, CERCR, CEECR, + RMIIMR, /* R8A7790 */ MAFCR, RTRATE, CSMR, @@ -220,6 +226,61 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { [RMII_MII] = 0x0790, }; +#if defined(SH_ETH_TYPE_RZ) +static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; +#endif + static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { [ECMR] = 0x0100, [RFLR] = 0x0108, @@ -263,6 +324,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { [RMCR] = 0x0058, [TFUCR] = 0x0064, [RFOCR] = 0x0068, + [RMIIMR] = 0x006C, [FCFTR] = 0x0070, [RPADIR] = 0x0078, [TRIMD] = 0x007c, @@ -276,7 +338,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xfee00000 -#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) +#elif defined(CONFIG_CPU_SH7757) || \ + defined(CONFIG_CPU_SH7752) || \ + defined(CONFIG_CPU_SH7753) #if defined(CONFIG_SH_ETHER_USE_GETHER) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xfee00000 @@ -290,13 +354,20 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R8A7740) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xE9A00000 +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +#define SH_ETH_TYPE_ETHER +#define BASE_IO_ADDR 0xEE700200 +#elif defined(CONFIG_R7S72100) +#define SH_ETH_TYPE_RZ +#define BASE_IO_ADDR 0xE8203000 #endif /* * Register's bits * Copy from Linux driver source code */ -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) /* EDSR */ enum EDSR_BIT { EDSR_ENT = 0x01, EDSR_ENR = 0x02, @@ -307,7 +378,7 @@ enum EDSR_BIT { /* EDMR */ enum DMAC_M_BIT { EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDMR_SRST = 0x03, /* Receive/Send reset */ EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ @@ -320,12 +391,20 @@ enum DMAC_M_BIT { #endif }; +#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 +# define EMDR_DESC EDMR_DL1 +#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 +# define EMDR_DESC EDMR_DL0 +#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +# define EMDR_DESC 0 +#endif + /* RFLR */ #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ /* EDTRR */ enum DMAC_T_BIT { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDTRR_TRNS = 0x03, #else EDTRR_TRNS = 0x01, @@ -334,7 +413,9 @@ enum DMAC_T_BIT { /* GECMR */ enum GECMR_BIT { -#if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) +#if defined(CONFIG_CPU_SH7757) || \ + defined(CONFIG_CPU_SH7752) || \ + defined(CONFIG_CPU_SH7753) GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, #else GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, @@ -368,7 +449,6 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; /* EESR */ enum EESR_BIT { - #if defined(SH_ETH_TYPE_ETHER) EESR_TWB = 0x40000000, #else @@ -393,12 +473,12 @@ enum EESR_BIT { EESR_CD = 0x00000200, EESR_RTO = 0x00000100, EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, - rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, + EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define TX_CHECK (EESR_TC1 | EESR_FTC) # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) @@ -458,7 +538,8 @@ enum FCFTR_BIT { /* Transfer descriptor bit */ enum TD_STS_BIT { -#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \ + defined(SH_ETH_TYPE_RZ) TD_TACT = 0x80000000, #else TD_TACT = 0x7fffffff, @@ -474,9 +555,9 @@ enum TD_STS_BIT { enum RECV_RST_BIT { RMCR_RST = 0x01, }; /* ECMR */ enum FELIC_MODE_BIT { -#if defined(SH_ETH_TYPE_GETHER) - ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, - ECMR_RZPF = 0x00100000, +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, + ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, #endif ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, @@ -485,13 +566,16 @@ enum FELIC_MODE_BIT { ECMR_PRM = 0x00000001, #ifdef CONFIG_CPU_SH7724 ECMR_RTM = 0x00000010, +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) + ECMR_RTM = 0x00000004, #endif }; -#if defined(SH_ETH_TYPE_GETHER) -#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ - ECMR_TXF | ECMR_MCT) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) +#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \ + ECMR_RXF | ECMR_TXF | ECMR_MCT) #elif defined(SH_ETH_TYPE_ETHER) #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) #else @@ -507,7 +591,7 @@ enum ECSR_STATUS_BIT { ECSR_MPD = 0x02, ECSR_ICD = 0x01, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) #else # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ @@ -528,7 +612,7 @@ enum ECSIPR_STATUS_MASK_BIT { ECSIPR_ICDIP = 0x01, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) #else # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ @@ -559,7 +643,7 @@ enum RPADIR_BIT { RPADIR_PADR = 0x0003f, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define RPADIR_INIT (0x00) #else # define RPADIR_INIT (RPADIR_PADS1) @@ -577,6 +661,8 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, const u16 *reg_offset = sh_eth_offset_gigabit; #elif defined(SH_ETH_TYPE_ETHER) const u16 *reg_offset = sh_eth_offset_fast_sh4; +#elif defined(SH_ETH_TYPE_RZ) + const u16 *reg_offset = sh_eth_offset_rz; #else #error #endif diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 9deee9bd2a..e19c491cbc 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -236,7 +236,36 @@ struct smc91111_priv{ *(__b2 + __i) = SMC_inb((a),(r)); \ }; \ }while(0) - +#elif defined(CONFIG_MS7206SE) +#define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); }) +#define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) +#define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) +#define SMC_insw(a, r, b, l) \ + do { \ + int __i; \ + word *__b2 = (word *)(b); \ + for (__i = 0; __i < (l); __i++) { \ + *__b2++ = SWAB7206(SMC_inw(a, r)); \ + } \ + } while (0) +#define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d) +#define SMC_outb(a, d, r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((a), ((r)&(~1))); \ + if (((r) & 1)) \ + __w = (__w & 0x00ff) | (__d << 8); \ + else \ + __w = (__w & 0xff00) | (__d); \ + SMC_outw((a), __w, ((r)&(~1))); \ + }) +#define SMC_outsw(a, r, b, l) \ + do { \ + int __i; \ + word *__b2 = (word *)(b); \ + for (__i = 0; __i < (l); __i++) { \ + SMC_outw(a, SWAB7206(*__b2), r); \ + __b2++; \ + } \ + } while (0) #else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ @@ -248,17 +277,26 @@ struct smc91111_priv{ #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) #elif CONFIG_BLACKFIN #define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) +#elif CONFIG_ARM64 +#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) #else -#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) +#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) #endif #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) #ifdef CONFIG_ADNPESC1 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) #elif CONFIG_BLACKFIN -#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();} +#define SMC_outw(a, d, r) \ + ({ (*((volatile word*)((a)->iobase+((r)))) = d); \ + SSYNC(); \ + }) +#elif CONFIG_ARM64 +#define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+((dword)(r)))) = d) #else -#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) +#define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+(r))) = d) #endif #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ word __w = SMC_inw((a),(r)&~1); \ diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index b097c1a56f..5959672370 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -187,6 +187,7 @@ static int smc911x_send(struct eth_device *dev, void *packet, int length) static void smc911x_halt(struct eth_device *dev) { smc911x_reset(dev); + smc911x_handle_mac_address(dev); } static int smc911x_rx(struct eth_device *dev) diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c new file mode 100644 index 0000000000..5a06d68af7 --- /dev/null +++ b/drivers/net/sunxi_emac.c @@ -0,0 +1,521 @@ +/* + * sunxi_emac.c -- Allwinner A10 ethernet driver + * + * (C) Copyright 2012, Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* EMAC register */ +struct emac_regs { + u32 ctl; /* 0x00 */ + u32 tx_mode; /* 0x04 */ + u32 tx_flow; /* 0x08 */ + u32 tx_ctl0; /* 0x0c */ + u32 tx_ctl1; /* 0x10 */ + u32 tx_ins; /* 0x14 */ + u32 tx_pl0; /* 0x18 */ + u32 tx_pl1; /* 0x1c */ + u32 tx_sta; /* 0x20 */ + u32 tx_io_data; /* 0x24 */ + u32 tx_io_data1;/* 0x28 */ + u32 tx_tsvl0; /* 0x2c */ + u32 tx_tsvh0; /* 0x30 */ + u32 tx_tsvl1; /* 0x34 */ + u32 tx_tsvh1; /* 0x38 */ + u32 rx_ctl; /* 0x3c */ + u32 rx_hash0; /* 0x40 */ + u32 rx_hash1; /* 0x44 */ + u32 rx_sta; /* 0x48 */ + u32 rx_io_data; /* 0x4c */ + u32 rx_fbc; /* 0x50 */ + u32 int_ctl; /* 0x54 */ + u32 int_sta; /* 0x58 */ + u32 mac_ctl0; /* 0x5c */ + u32 mac_ctl1; /* 0x60 */ + u32 mac_ipgt; /* 0x64 */ + u32 mac_ipgr; /* 0x68 */ + u32 mac_clrt; /* 0x6c */ + u32 mac_maxf; /* 0x70 */ + u32 mac_supp; /* 0x74 */ + u32 mac_test; /* 0x78 */ + u32 mac_mcfg; /* 0x7c */ + u32 mac_mcmd; /* 0x80 */ + u32 mac_madr; /* 0x84 */ + u32 mac_mwtd; /* 0x88 */ + u32 mac_mrdd; /* 0x8c */ + u32 mac_mind; /* 0x90 */ + u32 mac_ssrr; /* 0x94 */ + u32 mac_a0; /* 0x98 */ + u32 mac_a1; /* 0x9c */ +}; + +/* SRAMC register */ +struct sunxi_sramc_regs { + u32 ctrl0; + u32 ctrl1; +}; + +/* 0: Disable 1: Aborted frame enable(default) */ +#define EMAC_TX_AB_M (0x1 << 0) +/* 0: CPU 1: DMA(default) */ +#define EMAC_TX_TM (0x1 << 1) + +#define EMAC_TX_SETUP (0) + +/* 0: DRQ asserted 1: DRQ automatically(default) */ +#define EMAC_RX_DRQ_MODE (0x1 << 1) +/* 0: CPU 1: DMA(default) */ +#define EMAC_RX_TM (0x1 << 2) +/* 0: Normal(default) 1: Pass all Frames */ +#define EMAC_RX_PA (0x1 << 4) +/* 0: Normal(default) 1: Pass Control Frames */ +#define EMAC_RX_PCF (0x1 << 5) +/* 0: Normal(default) 1: Pass Frames with CRC Error */ +#define EMAC_RX_PCRCE (0x1 << 6) +/* 0: Normal(default) 1: Pass Frames with Length Error */ +#define EMAC_RX_PLE (0x1 << 7) +/* 0: Normal 1: Pass Frames length out of range(default) */ +#define EMAC_RX_POR (0x1 << 8) +/* 0: Not accept 1: Accept unicast Packets(default) */ +#define EMAC_RX_UCAD (0x1 << 16) +/* 0: Normal(default) 1: DA Filtering */ +#define EMAC_RX_DAF (0x1 << 17) +/* 0: Not accept 1: Accept multicast Packets(default) */ +#define EMAC_RX_MCO (0x1 << 20) +/* 0: Disable(default) 1: Enable Hash filter */ +#define EMAC_RX_MHF (0x1 << 21) +/* 0: Not accept 1: Accept Broadcast Packets(default) */ +#define EMAC_RX_BCO (0x1 << 22) +/* 0: Disable(default) 1: Enable SA Filtering */ +#define EMAC_RX_SAF (0x1 << 24) +/* 0: Normal(default) 1: Inverse Filtering */ +#define EMAC_RX_SAIF (0x1 << 25) + +#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \ + EMAC_RX_MCO | EMAC_RX_BCO) + +/* 0: Disable 1: Enable Receive Flow Control(default) */ +#define EMAC_MAC_CTL0_RFC (0x1 << 2) +/* 0: Disable 1: Enable Transmit Flow Control(default) */ +#define EMAC_MAC_CTL0_TFC (0x1 << 3) + +#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) + +/* 0: Disable 1: Enable MAC Frame Length Checking(default) */ +#define EMAC_MAC_CTL1_FLC (0x1 << 1) +/* 0: Disable(default) 1: Enable Huge Frame */ +#define EMAC_MAC_CTL1_HF (0x1 << 2) +/* 0: Disable(default) 1: Enable MAC Delayed CRC */ +#define EMAC_MAC_CTL1_DCRC (0x1 << 3) +/* 0: Disable 1: Enable MAC CRC(default) */ +#define EMAC_MAC_CTL1_CRC (0x1 << 4) +/* 0: Disable 1: Enable MAC PAD Short frames(default) */ +#define EMAC_MAC_CTL1_PC (0x1 << 5) +/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */ +#define EMAC_MAC_CTL1_VC (0x1 << 6) +/* 0: Disable(default) 1: Enable MAC auto detect Short frames */ +#define EMAC_MAC_CTL1_ADP (0x1 << 7) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_PRE (0x1 << 8) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_LPE (0x1 << 9) +/* 0: Disable(default) 1: Enable no back off */ +#define EMAC_MAC_CTL1_NB (0x1 << 12) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_BNB (0x1 << 13) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_ED (0x1 << 14) + +#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ + EMAC_MAC_CTL1_PC) + +#define EMAC_MAC_IPGT 0x15 + +#define EMAC_MAC_NBTB_IPG1 0xc +#define EMAC_MAC_NBTB_IPG2 0x12 + +#define EMAC_MAC_CW 0x37 +#define EMAC_MAC_RM 0xf + +#define EMAC_MAC_MFL 0x0600 + +/* Receive status */ +#define EMAC_CRCERR (0x1 << 4) +#define EMAC_LENERR (0x3 << 5) + +#define DMA_CPU_TRRESHOLD 2000 + +struct emac_eth_dev { + u32 speed; + u32 duplex; + u32 phy_configured; + int link_printed; +}; + +struct emac_rxhdr { + s16 rx_len; + u16 rx_status; +}; + +static void emac_inblk_32bit(void *reg, void *data, int count) +{ + int cnt = (count + 3) >> 2; + + if (cnt) { + u32 *buf = data; + + do { + u32 x = readl(reg); + *buf++ = x; + } while (--cnt); + } +} + +static void emac_outblk_32bit(void *reg, void *data, int count) +{ + int cnt = (count + 3) >> 2; + + if (cnt) { + const u32 *buf = data; + + do { + writel(*buf++, reg); + } while (--cnt); + } +} + +/* Read a word from phyxcer */ +static int emac_phy_read(const char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + + /* issue the phy address and reg */ + writel(addr << 8 | reg, ®s->mac_madr); + + /* pull up the phy io line */ + writel(0x1, ®s->mac_mcmd); + + /* Wait read complete */ + mdelay(1); + + /* push down the phy io line */ + writel(0x0, ®s->mac_mcmd); + + /* and write data */ + *value = readl(®s->mac_mrdd); + + return 0; +} + +/* Write a word to phyxcer */ +static int emac_phy_write(const char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + + /* issue the phy address and reg */ + writel(addr << 8 | reg, ®s->mac_madr); + + /* pull up the phy io line */ + writel(0x1, ®s->mac_mcmd); + + /* Wait write complete */ + mdelay(1); + + /* push down the phy io line */ + writel(0x0, ®s->mac_mcmd); + + /* and write data */ + writel(value, ®s->mac_mwtd); + + return 0; +} + +static void emac_setup(struct eth_device *dev) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + u32 reg_val; + u16 phy_val; + u32 duplex_flag; + + /* Set up TX */ + writel(EMAC_TX_SETUP, ®s->tx_mode); + + /* Set up RX */ + writel(EMAC_RX_SETUP, ®s->rx_ctl); + + /* Set MAC */ + /* Set MAC CTL0 */ + writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0); + + /* Set MAC CTL1 */ + emac_phy_read(dev->name, 1, 0, &phy_val); + debug("PHY SETUP, reg 0 value: %x\n", phy_val); + duplex_flag = !!(phy_val & (1 << 8)); + + reg_val = 0; + if (duplex_flag) + reg_val = (0x1 << 0); + writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1); + + /* Set up IPGT */ + writel(EMAC_MAC_IPGT, ®s->mac_ipgt); + + /* Set up IPGR */ + writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr); + + /* Set up Collison window */ + writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt); + + /* Set up Max Frame Length */ + writel(EMAC_MAC_MFL, ®s->mac_maxf); +} + +static void emac_reset(struct eth_device *dev) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + + debug("resetting device\n"); + + /* RESET device */ + writel(0, ®s->ctl); + udelay(200); + + writel(1, ®s->ctl); + udelay(200); +} + +static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + struct emac_eth_dev *priv = dev->priv; + u16 phy_reg; + + /* Init EMAC */ + + /* Flush RX FIFO */ + setbits_le32(®s->rx_ctl, 0x8); + udelay(1); + + /* Init MAC */ + + /* Soft reset MAC */ + clrbits_le32(®s->mac_ctl0, 0x1 << 15); + + /* Clear RX counter */ + writel(0x0, ®s->rx_fbc); + udelay(1); + + /* Set up EMAC */ + emac_setup(dev); + + writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 | + dev->enetaddr[2], ®s->mac_a1); + writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 | + dev->enetaddr[5], ®s->mac_a0); + + mdelay(1); + + emac_reset(dev); + + /* PHY POWER UP */ + emac_phy_read(dev->name, 1, 0, &phy_reg); + emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11))); + mdelay(1); + + emac_phy_read(dev->name, 1, 0, &phy_reg); + + priv->speed = miiphy_speed(dev->name, 0); + priv->duplex = miiphy_duplex(dev->name, 0); + + /* Print link status only once */ + if (!priv->link_printed) { + printf("ENET Speed is %d Mbps - %s duplex connection\n", + priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); + priv->link_printed = 1; + } + + /* Set EMAC SPEED depend on PHY */ + clrsetbits_le32(®s->mac_supp, 1 << 8, + ((phy_reg & (0x1 << 13)) >> 13) << 8); + + /* Set duplex depend on phy */ + clrsetbits_le32(®s->mac_ctl1, 1 << 0, + ((phy_reg & (0x1 << 8)) >> 8) << 0); + + /* Enable RX/TX */ + setbits_le32(®s->ctl, 0x7); + + return 0; +} + +static void sunxi_emac_eth_halt(struct eth_device *dev) +{ + /* Nothing to do here */ +} + +static int sunxi_emac_eth_recv(struct eth_device *dev) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + struct emac_rxhdr rxhdr; + u32 rxcount; + u32 reg_val; + int rx_len; + int rx_status; + int good_packet; + + /* Check packet ready or not */ + + /* Race warning: The first packet might arrive with + * the interrupts disabled, but the second will fix + */ + rxcount = readl(®s->rx_fbc); + if (!rxcount) { + /* Had one stuck? */ + rxcount = readl(®s->rx_fbc); + if (!rxcount) + return 0; + } + + reg_val = readl(®s->rx_io_data); + if (reg_val != 0x0143414d) { + /* Disable RX */ + clrbits_le32(®s->ctl, 0x1 << 2); + + /* Flush RX FIFO */ + setbits_le32(®s->rx_ctl, 0x1 << 3); + while (readl(®s->rx_ctl) & (0x1 << 3)) + ; + + /* Enable RX */ + setbits_le32(®s->ctl, 0x1 << 2); + + return 0; + } + + /* A packet ready now + * Get status/length + */ + good_packet = 1; + + emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr)); + + rx_len = rxhdr.rx_len; + rx_status = rxhdr.rx_status; + + /* Packet Status check */ + if (rx_len < 0x40) { + good_packet = 0; + debug("RX: Bad Packet (runt)\n"); + } + + /* rx_status is identical to RSR register. */ + if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) { + good_packet = 0; + if (rx_status & EMAC_CRCERR) + printf("crc error\n"); + if (rx_status & EMAC_LENERR) + printf("length error\n"); + } + + /* Move data from EMAC */ + if (good_packet) { + if (rx_len > DMA_CPU_TRRESHOLD) { + printf("Received packet is too big (len=%d)\n", rx_len); + } else { + emac_inblk_32bit((void *)®s->rx_io_data, + NetRxPackets[0], rx_len); + + /* Pass to upper layer */ + NetReceive(NetRxPackets[0], rx_len); + return rx_len; + } + } + + return 0; +} + +static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + + /* Select channel 0 */ + writel(0, ®s->tx_ins); + + /* Write packet */ + emac_outblk_32bit((void *)®s->tx_io_data, packet, len); + + /* Set TX len */ + writel(len, ®s->tx_pl0); + + /* Start translate from fifo to phy */ + setbits_le32(®s->tx_ctl0, 1); + + return 0; +} + +int sunxi_emac_initialize(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_sramc_regs *sram = + (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; + struct emac_regs *regs = + (struct emac_regs *)SUNXI_EMAC_BASE; + struct eth_device *dev; + struct emac_eth_dev *priv; + int pin; + + dev = malloc(sizeof(*dev)); + if (dev == NULL) + return -ENOMEM; + + priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev)); + if (!priv) { + free(dev); + return -ENOMEM; + } + + memset(dev, 0, sizeof(*dev)); + memset(priv, 0, sizeof(struct emac_eth_dev)); + + /* Map SRAM to EMAC */ + setbits_le32(&sram->ctrl1, 0x5 << 2); + + /* Configure pin mux settings for MII Ethernet */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC); + + /* Set up clock gating */ + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); + + /* Set MII clock */ + clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); + + dev->iobase = (int)regs; + dev->priv = priv; + dev->init = sunxi_emac_eth_init; + dev->halt = sunxi_emac_eth_halt; + dev->send = sunxi_emac_eth_send; + dev->recv = sunxi_emac_eth_recv; + strcpy(dev->name, "emac"); + + eth_register(dev); + + miiphy_register(dev->name, emac_phy_read, emac_phy_write); + + return 0; +} diff --git a/drivers/net/sunxi_wemac.c b/drivers/net/sunxi_wemac.c deleted file mode 100644 index 699a381582..0000000000 --- a/drivers/net/sunxi_wemac.c +++ /dev/null @@ -1,525 +0,0 @@ -/* - * sunxi_wemac.c -- Allwinner A10 ethernet driver - * - * (C) Copyright 2012, Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* EMAC register */ -struct wemac_regs { - u32 ctl; /* 0x00 */ - u32 tx_mode; /* 0x04 */ - u32 tx_flow; /* 0x08 */ - u32 tx_ctl0; /* 0x0c */ - u32 tx_ctl1; /* 0x10 */ - u32 tx_ins; /* 0x14 */ - u32 tx_pl0; /* 0x18 */ - u32 tx_pl1; /* 0x1c */ - u32 tx_sta; /* 0x20 */ - u32 tx_io_data; /* 0x24 */ - u32 tx_io_data1; /* 0x28 */ - u32 tx_tsvl0; /* 0x2c */ - u32 tx_tsvh0; /* 0x30 */ - u32 tx_tsvl1; /* 0x34 */ - u32 tx_tsvh1; /* 0x38 */ - u32 rx_ctl; /* 0x3c */ - u32 rx_hash0; /* 0x40 */ - u32 rx_hash1; /* 0x44 */ - u32 rx_sta; /* 0x48 */ - u32 rx_io_data; /* 0x4c */ - u32 rx_fbc; /* 0x50 */ - u32 int_ctl; /* 0x54 */ - u32 int_sta; /* 0x58 */ - u32 mac_ctl0; /* 0x5c */ - u32 mac_ctl1; /* 0x60 */ - u32 mac_ipgt; /* 0x64 */ - u32 mac_ipgr; /* 0x68 */ - u32 mac_clrt; /* 0x6c */ - u32 mac_maxf; /* 0x70 */ - u32 mac_supp; /* 0x74 */ - u32 mac_test; /* 0x78 */ - u32 mac_mcfg; /* 0x7c */ - u32 mac_mcmd; /* 0x80 */ - u32 mac_madr; /* 0x84 */ - u32 mac_mwtd; /* 0x88 */ - u32 mac_mrdd; /* 0x8c */ - u32 mac_mind; /* 0x90 */ - u32 mac_ssrr; /* 0x94 */ - u32 mac_a0; /* 0x98 */ - u32 mac_a1; /* 0x9c */ -}; - -/* SRAMC register */ -struct sunxi_sramc_regs { - u32 ctrl0; - u32 ctrl1; -}; - -/* 0: Disable 1: Aborted frame enable(default) */ -#define EMAC_TX_AB_M (0x1 << 0) -/* 0: CPU 1: DMA(default) */ -#define EMAC_TX_TM (0x1 << 1) - -#define EMAC_TX_SETUP (0) - -/* 0: DRQ asserted 1: DRQ automatically(default) */ -#define EMAC_RX_DRQ_MODE (0x1 << 1) -/* 0: CPU 1: DMA(default) */ -#define EMAC_RX_TM (0x1 << 2) -/* 0: Normal(default) 1: Pass all Frames */ -#define EMAC_RX_PA (0x1 << 4) -/* 0: Normal(default) 1: Pass Control Frames */ -#define EMAC_RX_PCF (0x1 << 5) -/* 0: Normal(default) 1: Pass Frames with CRC Error */ -#define EMAC_RX_PCRCE (0x1 << 6) -/* 0: Normal(default) 1: Pass Frames with Length Error */ -#define EMAC_RX_PLE (0x1 << 7) -/* 0: Normal 1: Pass Frames length out of range(default) */ -#define EMAC_RX_POR (0x1 << 8) -/* 0: Not accept 1: Accept unicast Packets(default) */ -#define EMAC_RX_UCAD (0x1 << 16) -/* 0: Normal(default) 1: DA Filtering */ -#define EMAC_RX_DAF (0x1 << 17) -/* 0: Not accept 1: Accept multicast Packets(default) */ -#define EMAC_RX_MCO (0x1 << 20) -/* 0: Disable(default) 1: Enable Hash filter */ -#define EMAC_RX_MHF (0x1 << 21) -/* 0: Not accept 1: Accept Broadcast Packets(default) */ -#define EMAC_RX_BCO (0x1 << 22) -/* 0: Disable(default) 1: Enable SA Filtering */ -#define EMAC_RX_SAF (0x1 << 24) -/* 0: Normal(default) 1: Inverse Filtering */ -#define EMAC_RX_SAIF (0x1 << 25) - -#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \ - EMAC_RX_MCO | EMAC_RX_BCO) - -/* 0: Disable 1: Enable Receive Flow Control(default) */ -#define EMAC_MAC_CTL0_RFC (0x1 << 2) -/* 0: Disable 1: Enable Transmit Flow Control(default) */ -#define EMAC_MAC_CTL0_TFC (0x1 << 3) - -#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) - -/* 0: Disable 1: Enable MAC Frame Length Checking(default) */ -#define EMAC_MAC_CTL1_FLC (0x1 << 1) -/* 0: Disable(default) 1: Enable Huge Frame */ -#define EMAC_MAC_CTL1_HF (0x1 << 2) -/* 0: Disable(default) 1: Enable MAC Delayed CRC */ -#define EMAC_MAC_CTL1_DCRC (0x1 << 3) -/* 0: Disable 1: Enable MAC CRC(default) */ -#define EMAC_MAC_CTL1_CRC (0x1 << 4) -/* 0: Disable 1: Enable MAC PAD Short frames(default) */ -#define EMAC_MAC_CTL1_PC (0x1 << 5) -/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */ -#define EMAC_MAC_CTL1_VC (0x1 << 6) -/* 0: Disable(default) 1: Enable MAC auto detect Short frames */ -#define EMAC_MAC_CTL1_ADP (0x1 << 7) -/* 0: Disable(default) 1: Enable */ -#define EMAC_MAC_CTL1_PRE (0x1 << 8) -/* 0: Disable(default) 1: Enable */ -#define EMAC_MAC_CTL1_LPE (0x1 << 9) -/* 0: Disable(default) 1: Enable no back off */ -#define EMAC_MAC_CTL1_NB (0x1 << 12) -/* 0: Disable(default) 1: Enable */ -#define EMAC_MAC_CTL1_BNB (0x1 << 13) -/* 0: Disable(default) 1: Enable */ -#define EMAC_MAC_CTL1_ED (0x1 << 14) - -#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ - EMAC_MAC_CTL1_PC) - -#define EMAC_MAC_IPGT 0x15 - -#define EMAC_MAC_NBTB_IPG1 0xC -#define EMAC_MAC_NBTB_IPG2 0x12 - -#define EMAC_MAC_CW 0x37 -#define EMAC_MAC_RM 0xF - -#define EMAC_MAC_MFL 0x0600 - -/* Receive status */ -#define EMAC_CRCERR (1 << 4) -#define EMAC_LENERR (3 << 5) - -#define DMA_CPU_TRRESHOLD 2000 - -struct wemac_eth_dev { - u32 speed; - u32 duplex; - u32 phy_configured; - int link_printed; -}; - -struct wemac_rxhdr { - s16 rx_len; - u16 rx_status; -}; - -static void wemac_inblk_32bit(void *reg, void *data, int count) -{ - int cnt = (count + 3) >> 2; - - if (cnt) { - u32 *buf = data; - - do { - u32 x = readl(reg); - *buf++ = x; - } while (--cnt); - } -} - -static void wemac_outblk_32bit(void *reg, void *data, int count) -{ - int cnt = (count + 3) >> 2; - - if (cnt) { - const u32 *buf = data; - - do { - writel(*buf++, reg); - } while (--cnt); - } -} - -/* - * Read a word from phyxcer - */ -static int wemac_phy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - struct eth_device *dev = eth_get_dev_by_name(devname); - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - - /* issue the phy address and reg */ - writel(addr << 8 | reg, ®s->mac_madr); - - /* pull up the phy io line */ - writel(0x1, ®s->mac_mcmd); - - /* Wait read complete */ - mdelay(1); - - /* push down the phy io line */ - writel(0x0, ®s->mac_mcmd); - - /* and write data */ - *value = readl(®s->mac_mrdd); - - return 0; -} - -/* - * Write a word to phyxcer - */ -static int wemac_phy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - struct eth_device *dev = eth_get_dev_by_name(devname); - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - - /* issue the phy address and reg */ - writel(addr << 8 | reg, ®s->mac_madr); - - /* pull up the phy io line */ - writel(0x1, ®s->mac_mcmd); - - /* Wait write complete */ - mdelay(1); - - /* push down the phy io line */ - writel(0x0, ®s->mac_mcmd); - - /* and write data */ - writel(value, ®s->mac_mwtd); - - return 0; -} - -static void emac_setup(struct eth_device *dev) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - u32 reg_val; - u16 phy_val; - u32 duplex_flag; - - /* Set up TX */ - writel(EMAC_TX_SETUP, ®s->tx_mode); - - /* Set up RX */ - writel(EMAC_RX_SETUP, ®s->rx_ctl); - - /* Set MAC */ - /* Set MAC CTL0 */ - writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0); - - /* Set MAC CTL1 */ - wemac_phy_read(dev->name, 1, 0, &phy_val); - debug("PHY SETUP, reg 0 value: %x\n", phy_val); - duplex_flag = !!(phy_val & (1 << 8)); - - reg_val = 0; - if (duplex_flag) - reg_val = (0x1 << 0); - writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1); - - /* Set up IPGT */ - writel(EMAC_MAC_IPGT, ®s->mac_ipgt); - - /* Set up IPGR */ - writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr); - - /* Set up Collison window */ - writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt); - - /* Set up Max Frame Length */ - writel(EMAC_MAC_MFL, ®s->mac_maxf); -} - -static void wemac_reset(struct eth_device *dev) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - - debug("resetting device\n"); - - /* RESET device */ - writel(0, ®s->ctl); - udelay(200); - - writel(1, ®s->ctl); - udelay(200); -} - -static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - struct wemac_eth_dev *priv = dev->priv; - u16 phy_reg; - - /* Init EMAC */ - - /* Flush RX FIFO */ - setbits_le32(®s->rx_ctl, 0x8); - udelay(1); - - /* Init MAC */ - - /* Soft reset MAC */ - clrbits_le32(®s->mac_ctl0, 1 << 15); - - /* Set MII clock */ - clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); - - /* Clear RX counter */ - writel(0x0, ®s->rx_fbc); - udelay(1); - - /* Set up EMAC */ - emac_setup(dev); - - writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 | - dev->enetaddr[2], ®s->mac_a1); - writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 | - dev->enetaddr[5], ®s->mac_a0); - - mdelay(1); - - wemac_reset(dev); - - /* PHY POWER UP */ - wemac_phy_read(dev->name, 1, 0, &phy_reg); - wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11))); - mdelay(1); - - wemac_phy_read(dev->name, 1, 0, &phy_reg); - - priv->speed = miiphy_speed(dev->name, 0); - priv->duplex = miiphy_duplex(dev->name, 0); - - /* Print link status only once */ - if (!priv->link_printed) { - printf("ENET Speed is %d Mbps - %s duplex connection\n", - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); - priv->link_printed = 1; - } - - /* Set EMAC SPEED depend on PHY */ - clrsetbits_le32(®s->mac_supp, 1 << 8, - ((phy_reg & (1 << 13)) >> 13) << 8); - - /* Set duplex depend on phy */ - clrsetbits_le32(®s->mac_ctl1, 1 << 0, - ((phy_reg & (1 << 8)) >> 8) << 0); - - /* Enable RX/TX */ - setbits_le32(®s->ctl, 0x7); - - return 0; -} - -static void sunxi_wemac_eth_halt(struct eth_device *dev) -{ - /* Nothing to do here */ -} - -static int sunxi_wemac_eth_recv(struct eth_device *dev) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - struct wemac_rxhdr rxhdr; - u32 rxcount; - u32 reg_val; - int rx_len; - int rx_status; - int good_packet; - - /* Check packet ready or not */ - - /* - * Race warning: The first packet might arrive with - * the interrupts disabled, but the second will fix - */ - rxcount = readl(®s->rx_fbc); - if (!rxcount) { - /* Had one stuck? */ - rxcount = readl(®s->rx_fbc); - if (!rxcount) - return 0; - } - - reg_val = readl(®s->rx_io_data); - if (reg_val != 0x0143414d) { - /* Disable RX */ - clrbits_le32(®s->ctl, 1 << 2); - - /* Flush RX FIFO */ - setbits_le32(®s->rx_ctl, 1 << 3); - while (readl(®s->rx_ctl) & (1 << 3)) - ; - - /* Enable RX */ - setbits_le32(®s->ctl, 1 << 2); - - return 0; - } - - /* - * A packet ready now - * Get status/length - */ - good_packet = 1; - - wemac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr)); - - rx_len = rxhdr.rx_len; - rx_status = rxhdr.rx_status; - - /* Packet Status check */ - if (rx_len < 0x40) { - good_packet = 0; - debug("RX: Bad Packet (runt)\n"); - } - - /* rx_status is identical to RSR register. */ - if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) { - good_packet = 0; - if (rx_status & EMAC_CRCERR) - printf("crc error\n"); - if (rx_status & EMAC_LENERR) - printf("length error\n"); - } - - /* Move data from WEMAC */ - if (good_packet) { - if (rx_len > DMA_CPU_TRRESHOLD) { - printf("Received packet is too big (len=%d)\n", rx_len); - } else { - wemac_inblk_32bit((void *)®s->rx_io_data, - NetRxPackets[0], rx_len); - - /* Pass to upper layer */ - NetReceive(NetRxPackets[0], rx_len); - return rx_len; - } - } - - return 0; -} - -static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - - /* Select channel 0 */ - writel(0, ®s->tx_ins); - - /* Write packet */ - wemac_outblk_32bit((void *)®s->tx_io_data, packet, len); - - /* Set TX len */ - writel(len, ®s->tx_pl0); - - /* Start translate from fifo to phy */ - setbits_le32(®s->tx_ctl0, 1); - - return 0; -} - -int sunxi_wemac_initialize(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_sramc_regs *sram = - (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; - struct eth_device *dev; - struct wemac_eth_dev *priv; - int pin; - - dev = malloc(sizeof(*dev)); - if (dev == NULL) - return -ENOMEM; - - priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev)); - if (!priv) { - free(dev); - return -ENOMEM; - } - - memset(dev, 0, sizeof(*dev)); - memset(priv, 0, sizeof(struct wemac_eth_dev)); - - /* Map SRAM to EMAC */ - setbits_le32(&sram->ctrl1, 0x5 << 2); - - /* Configure pin mux settings for MII Ethernet */ - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) - sunxi_gpio_set_cfgpin(pin, 2); - - /* Set up clock gating */ - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC); - - dev->iobase = SUNXI_EMAC_BASE; - dev->priv = priv; - dev->init = sunxi_wemac_eth_init; - dev->halt = sunxi_wemac_eth_halt; - dev->send = sunxi_wemac_eth_send; - dev->recv = sunxi_wemac_eth_recv; - strcpy(dev->name, "wemac"); - - eth_register(dev); - - miiphy_register(dev->name, wemac_phy_read, wemac_phy_write); - - return 0; -} diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index f5e314b9ee..c4cf80a3f8 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -5,7 +5,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004-2011 Freescale Semiconductor, Inc. + * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * @@ -20,26 +20,19 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; #define TX_BUF_CNT 2 -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -typedef volatile struct rtxbd { - txbd8_t txbd[TX_BUF_CNT]; - rxbd8_t rxbd[PKTBUFSRX]; -} RTXBD; - -#define MAXCONTROLLERS (8) - -static struct tsec_private *privlist[MAXCONTROLLERS]; -static int num_tsecs = 0; +static uint rx_idx; /* index of the current RX buffer */ +static uint tx_idx; /* index of the current TX buffer */ #ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); +static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8); +static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8); + #else #error "rtx must be 64-bit aligned" #endif @@ -57,7 +50,7 @@ static struct tsec_info_struct tsec_info[] = { #endif #ifdef CONFIG_MPC85XX_FEC { - .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), + .regs = TSEC_GET_REGS(2, 0x2000), .devname = CONFIG_MPC85XX_FEC_NAME, .phyaddr = FEC_PHY_ADDR, .flags = FEC_FLAGS, @@ -113,32 +106,31 @@ static void tsec_configure_serdes(struct tsec_private *priv) * result. * 2) Use the 8 most significant bits as a hash into a 256-entry * table. The table is controlled through 8 32-bit registers: - * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is - * gaddr7. This means that the 3 most significant bits in the + * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry + * 255. This means that the 3 most significant bits in the * hash index which gaddr register to use, and the 5 other bits * indicate which bit (assuming an IBM numbering scheme, which - * for PowerPC (tm) is usually the case) in the tregister holds + * for PowerPC (tm) is usually the case) in the register holds * the entry. */ static int -tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) +tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) { - struct tsec_private *priv = privlist[1]; - volatile tsec_t *regs = priv->regs; - volatile u32 *reg_array, value; - u8 result, whichbit, whichreg; - - result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); - whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ - whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ - value = (1 << (31-whichbit)); - - reg_array = &(regs->hash.gaddr0); - - if (set) { - reg_array[whichreg] |= value; - } else { - reg_array[whichreg] &= ~value; - } + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + u32 result, value; + u8 whichbit, whichreg; + + result = ether_crc(MAC_ADDR_LEN, mcast_mac); + whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */ + whichreg = result >> 29; /* the 3 MSB = which reg to set it in */ + + value = 1 << (31-whichbit); + + if (set) + setbits_be32(®s->hash.gaddr0 + whichreg, value); + else + clrbits_be32(®s->hash.gaddr0 + whichreg, value); + return 0; } #endif /* Multicast TFTP ? */ @@ -147,7 +139,7 @@ tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) * those we don't care about (unless zero is bad, in which case, * choose a more appropriate value) */ -static void init_registers(tsec_t *regs) +static void init_registers(struct tsec __iomem *regs) { /* Clear IEVENT */ out_be32(®s->ievent, IEVENT_INIT_CLEAR); @@ -175,7 +167,7 @@ static void init_registers(tsec_t *regs) out_be32(®s->rctrl, 0x00000000); /* Init RMON mib registers */ - memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); + memset((void *)®s->rmon, 0, sizeof(regs->rmon)); out_be32(®s->rmon.cam1, 0xffffffff); out_be32(®s->rmon.cam2, 0xffffffff); @@ -194,7 +186,7 @@ static void init_registers(tsec_t *regs) */ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) { - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; u32 ecntrl, maccfg2; if (!phydev->link) { @@ -248,7 +240,7 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) void redundant_init(struct eth_device *dev) { struct tsec_private *priv = dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; uint t, count = 0; int fail = 1; static const u8 pkt[] = { @@ -279,25 +271,31 @@ void redundant_init(struct eth_device *dev) out_be32(®s->tstat, TSTAT_CLEAR_THALT); out_be32(®s->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); +#ifdef CONFIG_SOC_LS102XA + setbits_be32(®s->dmactrl, DMACTRL_LE); +#endif do { + uint16_t status; tsec_send(dev, (void *)pkt, sizeof(pkt)); /* Wait for buffer to be received */ - for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) { + for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) { if (t >= 10 * TOUT_LOOP) { printf("%s: tsec: rx error\n", dev->name); break; } } - if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt))) + if (!memcmp(pkt, (void *)NetRxPackets[rx_idx], sizeof(pkt))) fail = 0; - rtx.rxbd[rxIdx].length = 0; - rtx.rxbd[rxIdx].status = - RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); - rxIdx = (rxIdx + 1) % PKTBUFSRX; + out_be16(&rxbd[rx_idx].length, 0); + status = RXBD_EMPTY; + if ((rx_idx + 1) == PKTBUFSRX) + status |= RXBD_WRAP; + out_be16(&rxbd[rx_idx].status, status); + rx_idx = (rx_idx + 1) % PKTBUFSRX; if (in_be32(®s->ievent) & IEVENT_BSY) { out_be32(®s->ievent, IEVENT_BSY); @@ -325,36 +323,39 @@ void redundant_init(struct eth_device *dev) */ static void startup_tsec(struct eth_device *dev) { - int i; struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; + uint16_t status; + int i; /* reset the indices to zero */ - rxIdx = 0; - txIdx = 0; + rx_idx = 0; + tx_idx = 0; #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 uint svr; #endif /* Point to the buffer descriptors */ - out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); - out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx])); + out_be32(®s->tbase, (u32)&txbd[0]); + out_be32(®s->rbase, (u32)&rxbd[0]); /* Initialize the Rx Buffer descriptors */ for (i = 0; i < PKTBUFSRX; i++) { - rtx.rxbd[i].status = RXBD_EMPTY; - rtx.rxbd[i].length = 0; - rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; + out_be16(&rxbd[i].status, RXBD_EMPTY); + out_be16(&rxbd[i].length, 0); + out_be32(&rxbd[i].bufptr, (u32)NetRxPackets[i]); } - rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; + status = in_be16(&rxbd[PKTBUFSRX - 1].status); + out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); /* Initialize the TX Buffer Descriptors */ for (i = 0; i < TX_BUF_CNT; i++) { - rtx.txbd[i].status = 0; - rtx.txbd[i].length = 0; - rtx.txbd[i].bufPtr = 0; + out_be16(&txbd[i].status, 0); + out_be16(&txbd[i].length, 0); + out_be32(&txbd[i].bufptr, 0); } - rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; + status = in_be16(&txbd[TX_BUF_CNT - 1].status); + out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 svr = get_svr(); @@ -369,6 +370,9 @@ static void startup_tsec(struct eth_device *dev) out_be32(®s->tstat, TSTAT_CLEAR_THALT); out_be32(®s->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); +#ifdef CONFIG_SOC_LS102XA + setbits_be32(®s->dmactrl, DMACTRL_LE); +#endif } /* This returns the status bits of the device. The return value @@ -378,66 +382,67 @@ static void startup_tsec(struct eth_device *dev) */ static int tsec_send(struct eth_device *dev, void *packet, int length) { - int i; - int result = 0; struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; + uint16_t status; + int result = 0; + int i; /* Find an empty buffer descriptor */ - for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { if (i >= TOUT_LOOP) { debug("%s: tsec: tx buffers full\n", dev->name); return result; } } - rtx.txbd[txIdx].bufPtr = (uint) packet; - rtx.txbd[txIdx].length = length; - rtx.txbd[txIdx].status |= - (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); + out_be32(&txbd[tx_idx].bufptr, (u32)packet); + out_be16(&txbd[tx_idx].length, length); + status = in_be16(&txbd[tx_idx].status); + out_be16(&txbd[tx_idx].status, status | + (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); /* Tell the DMA to go */ out_be32(®s->tstat, TSTAT_CLEAR_THALT); /* Wait for buffer to be transmitted */ - for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { if (i >= TOUT_LOOP) { debug("%s: tsec: tx error\n", dev->name); return result; } } - txIdx = (txIdx + 1) % TX_BUF_CNT; - result = rtx.txbd[txIdx].status & TXBD_STATS; + tx_idx = (tx_idx + 1) % TX_BUF_CNT; + result = in_be16(&txbd[tx_idx].status) & TXBD_STATS; return result; } static int tsec_recv(struct eth_device *dev) { - int length; struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; - while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { - - length = rtx.rxbd[rxIdx].length; + while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) { + int length = in_be16(&rxbd[rx_idx].length); + uint16_t status = in_be16(&rxbd[rx_idx].status); /* Send the packet up if there were no errors */ - if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { - NetReceive(NetRxPackets[rxIdx], length - 4); - } else { - printf("Got error %x\n", - (rtx.rxbd[rxIdx].status & RXBD_STATS)); - } + if (!(status & RXBD_STATS)) + NetReceive(NetRxPackets[rx_idx], length - 4); + else + printf("Got error %x\n", (status & RXBD_STATS)); - rtx.rxbd[rxIdx].length = 0; + out_be16(&rxbd[rx_idx].length, 0); + status = RXBD_EMPTY; /* Set the wrap bit if this is the last element in the list */ - rtx.rxbd[rxIdx].status = - RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + if ((rx_idx + 1) == PKTBUFSRX) + status |= RXBD_WRAP; + out_be16(&rxbd[rx_idx].status, status); - rxIdx = (rxIdx + 1) % PKTBUFSRX; + rx_idx = (rx_idx + 1) % PKTBUFSRX; } if (in_be32(®s->ievent) & IEVENT_BSY) { @@ -453,7 +458,7 @@ static int tsec_recv(struct eth_device *dev) static void tsec_halt(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); @@ -475,11 +480,9 @@ static void tsec_halt(struct eth_device *dev) */ static int tsec_init(struct eth_device *dev, bd_t * bd) { - uint tempval; - char tmpbuf[MAC_ADDR_LEN]; - int i; struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; + u32 tempval; int ret; /* Make sure the controller is stopped */ @@ -492,16 +495,16 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); /* Copy the station address into the address registers. - * Backwards, because little endian MACS are dumb */ - for (i = 0; i < MAC_ADDR_LEN; i++) - tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; - - tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | - tmpbuf[3]; + * For a station address of 0x12345678ABCD in transmission + * order (BE), MACnADDR1 is set to 0xCDAB7856 and + * MACnADDR2 is set to 0x34120000. + */ + tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) | + (dev->enetaddr[3] << 8) | dev->enetaddr[2]; out_be32(®s->macstnaddr1, tempval); - tempval = *((uint *) (tmpbuf + 4)); + tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16); out_be32(®s->macstnaddr2, tempval); @@ -527,7 +530,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) static phy_interface_t tsec_get_interface(struct tsec_private *priv) { - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; u32 ecntrl; ecntrl = in_be32(®s->ecntrl); @@ -576,7 +579,7 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_device *phydev; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; u32 supported = (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -594,6 +597,8 @@ static int init_phy(struct eth_device *dev) tsec_configure_serdes(priv); phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); + if (!phydev) + return 0; phydev->supported &= supported; phydev->advertising = phydev->supported; @@ -626,7 +631,6 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) if (NULL == priv) return 0; - privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs_sgmii = tsec_info->miiregs_sgmii; @@ -684,7 +688,7 @@ int tsec_standard_init(bd_t *bis) { struct fsl_pq_mdio_info info; - info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + info.regs = TSEC_GET_MDIO_REGS_BASE(1); info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &info); diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 538f11e3eb..9526faa4af 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -548,7 +548,7 @@ static int uli526x_rx_packet(struct eth_device *dev) rdes0 = le32_to_cpu(rxptr->rdes0); #ifdef RX_DEBUG - printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0); + printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0); #endif if (!(rdes0 & 0x80000000)) { /* packet owner check */ if ((rdes0 & 0x300) != 0x300) { diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c new file mode 100644 index 0000000000..9fc3c18ba2 --- /dev/null +++ b/drivers/net/vsc9953.c @@ -0,0 +1,497 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Driver for the Vitesse VSC9953 L2 Switch + */ + +#include +#include +#include +#include +#include + +static struct vsc9953_info vsc9953_l2sw = { + .port[0] = VSC9953_PORT_INFO_INITIALIZER(0), + .port[1] = VSC9953_PORT_INFO_INITIALIZER(1), + .port[2] = VSC9953_PORT_INFO_INITIALIZER(2), + .port[3] = VSC9953_PORT_INFO_INITIALIZER(3), + .port[4] = VSC9953_PORT_INFO_INITIALIZER(4), + .port[5] = VSC9953_PORT_INFO_INITIALIZER(5), + .port[6] = VSC9953_PORT_INFO_INITIALIZER(6), + .port[7] = VSC9953_PORT_INFO_INITIALIZER(7), + .port[8] = VSC9953_PORT_INFO_INITIALIZER(8), + .port[9] = VSC9953_PORT_INFO_INITIALIZER(9), +}; + +void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus) +{ + if (!VSC9953_PORT_CHECK(port)) + return; + + vsc9953_l2sw.port[port].bus = bus; +} + +void vsc9953_port_info_set_phy_address(int port, int address) +{ + if (!VSC9953_PORT_CHECK(port)) + return; + + vsc9953_l2sw.port[port].phyaddr = address; +} + +void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int) +{ + if (!VSC9953_PORT_CHECK(port)) + return; + + vsc9953_l2sw.port[port].enet_if = phy_int; +} + +void vsc9953_port_enable(int port) +{ + if (!VSC9953_PORT_CHECK(port)) + return; + + vsc9953_l2sw.port[port].enabled = 1; +} + +void vsc9953_port_disable(int port) +{ + if (!VSC9953_PORT_CHECK(port)) + return; + + vsc9953_l2sw.port[port].enabled = 0; +} + +static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr, + int regnum, int value) +{ + int timeout = 50000; + + out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | + ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | + (0x1 << 1)); + asm("sync"); + + while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout) + udelay(1); + + if (timeout == 0) + debug("Timeout waiting for MDIO write\n"); +} + +static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr, + int regnum) +{ + int value = 0xFFFF; + int timeout = 50000; + + while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout) + udelay(1); + if (timeout == 0) { + debug("Timeout waiting for MDIO operation to finish\n"); + return value; + } + + /* Put the address of the phy, and the register + * number into MIICMD + */ + out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | + ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | + (0x2 << 1)); + + timeout = 50000; + /* Wait for the the indication that the read is done */ + while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout) + udelay(1); + if (timeout == 0) + debug("Timeout waiting for MDIO read\n"); + + /* Grab the value read from the PHY */ + value = in_le32(&phyregs->miimdata); + + if ((value & 0x00030000) == 0) + return value & 0x0000ffff; + + return value; +} + +static int init_phy(struct eth_device *dev) +{ + struct vsc9953_port_info *l2sw_port = dev->priv; + struct phy_device *phydev = NULL; + +#ifdef CONFIG_PHYLIB + if (!l2sw_port->bus) + return 0; + phydev = phy_connect(l2sw_port->bus, l2sw_port->phyaddr, dev, + l2sw_port->enet_if); + if (!phydev) { + printf("Failed to connect\n"); + return -1; + } + + phydev->supported &= SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full; + phydev->advertising = phydev->supported; + + l2sw_port->phydev = phydev; + + phy_config(phydev); +#endif + + return 0; +} + +static int vsc9953_port_init(int port) +{ + struct eth_device *dev; + + /* Internal ports never have a PHY */ + if (VSC9953_INTERNAL_PORT_CHECK(port)) + return 0; + + /* alloc eth device */ + dev = (struct eth_device *)calloc(1, sizeof(struct eth_device)); + if (!dev) + return 1; + + sprintf(dev->name, "SW@PORT%d", port); + dev->priv = &vsc9953_l2sw.port[port]; + dev->init = NULL; + dev->halt = NULL; + dev->send = NULL; + dev->recv = NULL; + + if (init_phy(dev)) { + free(dev); + return 1; + } + + return 0; +} + +void vsc9953_init(bd_t *bis) +{ + u32 i, hdx_cfg = 0, phy_addr = 0; + int timeout; + struct vsc9953_system_reg *l2sys_reg; + struct vsc9953_qsys_reg *l2qsys_reg; + struct vsc9953_dev_gmii *l2dev_gmii_reg; + struct vsc9953_analyzer *l2ana_reg; + struct vsc9953_devcpu_gcb *l2dev_gcb; + + l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET + + VSC9953_DEV_GMII_OFFSET); + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + + VSC9953_SYS_OFFSET); + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + l2dev_gcb = (struct vsc9953_devcpu_gcb *)(VSC9953_OFFSET + + VSC9953_DEVCPU_GCB); + + out_le32(&l2dev_gcb->chip_regs.soft_rst, + CONFIG_VSC9953_SOFT_SWC_RST_ENA); + timeout = 50000; + while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) & + CONFIG_VSC9953_SOFT_SWC_RST_ENA) && --timeout) + udelay(1); /* busy wait for vsc9953 soft reset */ + if (timeout == 0) + debug("Timeout waiting for VSC9953 to reset\n"); + + out_le32(&l2sys_reg->sys.reset_cfg, CONFIG_VSC9953_MEM_ENABLE | + CONFIG_VSC9953_MEM_INIT); + + timeout = 50000; + while ((in_le32(&l2sys_reg->sys.reset_cfg) & + CONFIG_VSC9953_MEM_INIT) && --timeout) + udelay(1); /* busy wait for vsc9953 memory init */ + if (timeout == 0) + debug("Timeout waiting for VSC9953 memory to initialize\n"); + + out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg) + | CONFIG_VSC9953_CORE_ENABLE)); + + /* VSC9953 Setting to be done once only */ + out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00); + + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_init(i)) + printf("Failed to initialize l2switch port %d\n", i); + + /* Enable VSC9953 GMII Ports Port ID 0 - 7 */ + if (VSC9953_INTERNAL_PORT_CHECK(i)) { + out_le32(&l2ana_reg->pfc[i].pfc_cfg, + CONFIG_VSC9953_PFC_FC_QSGMII); + out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], + CONFIG_VSC9953_MAC_FC_CFG_QSGMII); + } else { + out_le32(&l2ana_reg->pfc[i].pfc_cfg, + CONFIG_VSC9953_PFC_FC); + out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], + CONFIG_VSC9953_MAC_FC_CFG); + } + out_le32(&l2dev_gmii_reg->port_mode.clock_cfg, + CONFIG_VSC9953_CLOCK_CFG); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg, + CONFIG_VSC9953_MAC_ENA_CFG); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg, + CONFIG_VSC9953_MAC_MODE_CFG); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg, + CONFIG_VSC9953_MAC_IFG_CFG); + /* mac_hdx_cfg varies with port id*/ + hdx_cfg = (CONFIG_VSC9953_MAC_HDX_CFG | (i << 16)); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg); + out_le32(&l2sys_reg->sys.front_port_mode[i], + CONFIG_VSC9953_FRONT_PORT_MODE); + out_le32(&l2qsys_reg->sys.switch_port_mode[i], + CONFIG_VSC9953_PORT_ENA); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg, + CONFIG_VSC9953_MAC_MAX_LEN); + out_le32(&l2sys_reg->pause_cfg.pause_cfg[i], + CONFIG_VSC9953_PAUSE_CFG); + /* WAIT FOR 2 us*/ + udelay(2); + + l2dev_gmii_reg = (struct vsc9953_dev_gmii *)( + (char *)l2dev_gmii_reg + + T1040_SWITCH_GMII_DEV_OFFSET); + + /* Initialize Lynx PHY Wrappers */ + phy_addr = 0; + if (vsc9953_l2sw.port[i].enet_if == + PHY_INTERFACE_MODE_QSGMII) + phy_addr = (i + 0x4) & 0x1F; + else if (vsc9953_l2sw.port[i].enet_if == + PHY_INTERFACE_MODE_SGMII) + phy_addr = (i + 1) & 0x1F; + + if (phy_addr) { + /* SGMII IF mode + AN enable */ + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x14, PHY_SGMII_IF_MODE_AN | + PHY_SGMII_IF_MODE_SGMII); + /* Dev ability according to SGMII specification */ + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x4, PHY_SGMII_DEV_ABILITY_SGMII); + /* Adjust link timer for SGMII + * 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 + */ + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x13, 0x0003); + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x12, 0x0d40); + /* Restart AN */ + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x0, PHY_SGMII_CR_DEF_VAL | + PHY_SGMII_CR_RESET_AN); + + timeout = 50000; + while ((vsc9953_mdio_read(&l2dev_gcb->mii_mng[0], + phy_addr, 0x01) & 0x0020) && --timeout) + udelay(1); /* wait for AN to complete */ + if (timeout == 0) + debug("Timeout waiting for AN to complete\n"); + } + } + + printf("VSC9953 L2 switch initialized\n"); + return; +} + +#ifdef CONFIG_VSC9953_CMD +/* Enable/disable status of a VSC9953 port */ +static void vsc9953_port_status_set(int port_nr, u8 enabled) +{ + u32 val; + struct vsc9953_qsys_reg *l2qsys_reg; + + /* Administrative down */ + if (vsc9953_l2sw.port[port_nr].enabled == 0) + return; + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]); + if (enabled == 1) + val |= (1 << 13); + else + val &= ~(1 << 13); + + out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val); +} + +/* Set all VSC9953 ports' status */ +static void vsc9953_port_all_status_set(u8 enabled) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_status_set(i, enabled); +} + +/* Start autonegotiation for a VSC9953 PHY */ +static void vsc9953_phy_autoneg(int port_nr) +{ + if (!vsc9953_l2sw.port[port_nr].phydev) + return; + + if (vsc9953_l2sw.port[port_nr].phydev->drv->startup( + vsc9953_l2sw.port[port_nr].phydev)) + printf("Failed to start PHY for port %d\n", port_nr); +} + +/* Start autonegotiation for all VSC9953 PHYs */ +static void vsc9953_phy_all_autoneg(void) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_phy_autoneg(i); +} + +/* Print a VSC9953 port's configuration */ +static void vsc9953_port_config_show(int port) +{ + int speed; + int duplex; + int link; + u8 enabled; + u32 val; + struct vsc9953_qsys_reg *l2qsys_reg; + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + val = in_le32(&l2qsys_reg->sys.switch_port_mode[port]); + enabled = vsc9953_l2sw.port[port].enabled & + ((val & 0x00002000) >> 13); + + /* internal ports (8 and 9) are fixed */ + if (VSC9953_INTERNAL_PORT_CHECK(port)) { + link = 1; + speed = SPEED_2500; + duplex = DUPLEX_FULL; + } else { + if (vsc9953_l2sw.port[port].phydev) { + link = vsc9953_l2sw.port[port].phydev->link; + speed = vsc9953_l2sw.port[port].phydev->speed; + duplex = vsc9953_l2sw.port[port].phydev->duplex; + } else { + link = -1; + speed = -1; + duplex = -1; + } + } + + printf("%8d ", port); + printf("%8s ", enabled == 1 ? "enabled" : "disabled"); + printf("%8s ", link == 1 ? "up" : "down"); + + switch (speed) { + case SPEED_10: + printf("%8d ", 10); + break; + case SPEED_100: + printf("%8d ", 100); + break; + case SPEED_1000: + printf("%8d ", 1000); + break; + case SPEED_2500: + printf("%8d ", 2500); + break; + case SPEED_10000: + printf("%8d ", 10000); + break; + default: + printf("%8s ", "-"); + } + + printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); +} + +/* Print VSC9953 ports' configuration */ +static void vsc9953_port_all_config_show(void) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_config_show(i); +} + +/* function to interpret commands starting with "ethsw " */ +static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u8 enable; + u32 port; + + if (argc < 4) + return -1; + + if (strcmp(argv[1], "port")) + return -1; + + if (!strcmp(argv[3], "show")) { + if (!strcmp(argv[2], "all")) { + vsc9953_phy_all_autoneg(); + printf("%8s %8s %8s %8s %8s\n", + "Port", "Status", "Link", "Speed", + "Duplex"); + vsc9953_port_all_config_show(); + return 0; + } else { + port = simple_strtoul(argv[2], NULL, 10); + if (!VSC9953_PORT_CHECK(port)) + return -1; + vsc9953_phy_autoneg(port); + printf("%8s %8s %8s %8s %8s\n", + "Port", "Status", "Link", "Speed", + "Duplex"); + vsc9953_port_config_show(port); + return 0; + } + } else if (!strcmp(argv[3], "enable")) { + enable = 1; + } else if (!strcmp(argv[3], "disable")) { + enable = 0; + } else { + return -1; + } + + if (!strcmp(argv[2], "all")) { + vsc9953_port_all_status_set(enable); + return 0; + } else { + port = simple_strtoul(argv[2], NULL, 10); + if (!VSC9953_PORT_CHECK(port)) + return -1; + vsc9953_port_status_set(port, enable); + return 0; + } + + return -1; +} + +U_BOOT_CMD(ethsw, 5, 0, do_ethsw, + "vsc9953 l2 switch commands", + "port enable|disable\n" + " - enable/disable an l2 switch port\n" + " port_nr=0..9; use \"all\" for all ports\n" + "ethsw port show\n" + " - show an l2 switch port's configuration\n" + " port_nr=0..9; use \"all\" for all ports\n" +); +#endif /* CONFIG_VSC9953_CMD */ diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index bb5044b31f..262b67b6cf 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -261,6 +261,10 @@ static int setup_phy(struct eth_device *dev) phydev->dev->name); return 0; } + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } switch (phydev->speed) { case 1000: diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 987af39bc9..2a5cc44553 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -4,7 +4,7 @@ * * Michal SIMEK * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -14,8 +14,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #undef DEBUG #define ENET_ADDR_LENGTH 6 @@ -364,24 +362,27 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, } #ifdef CONFIG_OF_CONTROL -int xilinx_emaclite_init(bd_t *bis) +int xilinx_emaclite_of_init(const void *blob) { int offset = 0; u32 ret = 0; u32 reg; do { - offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + offset = fdt_node_offset_by_compatible(blob, offset, "xlnx,xps-ethernetlite-1.00.a"); if (offset != -1) { - reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg"); + reg = fdtdec_get_addr(blob, offset, "reg"); if (reg != FDT_ADDR_T_NONE) { - u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset, + u32 rxpp = fdtdec_get_int(blob, offset, "xlnx,rx-ping-pong", 0); - u32 txpp = fdtdec_get_int(gd->fdt_blob, offset, + u32 txpp = fdtdec_get_int(blob, offset, "xlnx,tx-ping-pong", 0); - ret |= xilinx_emaclite_initialize(bis, reg, + ret |= xilinx_emaclite_initialize(NULL, reg, txpp, rxpp); + } else { + debug("EMACLITE: Can't get base address\n"); + return -1; } } } while (offset != -1); diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c index dab78d073d..7cc86571e4 100644 --- a/drivers/net/xilinx_ll_temac.c +++ b/drivers/net/xilinx_ll_temac.c @@ -231,7 +231,7 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis) struct ll_temac *ll_temac = dev->priv; int ret; - printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n", + printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08lx.\n", dev->name, dev->index, dev->iobase); if (!ll_temac_setup_ctrl(dev)) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index b3ed6eaaf6..430e22821c 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -6,12 +6,15 @@ * Based on Xilinx gmac driver: * (C) Copyright 2011 Xilinx * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include #include +#include +#include #include #include #include @@ -43,11 +46,6 @@ #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ -#define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */ -#define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */ -/* Transmit buffs exhausted mid frame */ -#define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010 - #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ @@ -90,6 +88,16 @@ */ #define PHY_DETECT_MASK 0x1808 +/* TX BD status masks */ +#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff +#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 +#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 + +/* Clock frequencies for different speeds */ +#define ZYNQ_GEM_FREQUENCY_10 2500000UL +#define ZYNQ_GEM_FREQUENCY_100 25000000UL +#define ZYNQ_GEM_FREQUENCY_1000 125000000UL + /* Device registers */ struct zynq_gem_regs { u32 nwctrl; /* Network Control reg */ @@ -123,12 +131,18 @@ struct emac_bd { }; #define RX_BUF 3 +/* Page table entries are set to 1MB, or multiples of 1MB + * (not < 1MB). driver uses less bd's so use 1MB bdspace. + */ +#define BD_SPACE 0x100000 +/* BD separation space */ +#define BD_SEPRN_SPACE 64 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ struct zynq_gem_priv { - struct emac_bd tx_bd; - struct emac_bd rx_bd[RX_BUF]; - char rxbuffers[RX_BUF * PKTSIZE_ALIGN]; + struct emac_bd *tx_bd; + struct emac_bd *rx_bd; + char *rxbuffers; u32 rxbd_current; u32 rx_first_buf; int phyaddr; @@ -264,7 +278,8 @@ static int zynq_gem_setup_mac(struct eth_device *dev) static int zynq_gem_init(struct eth_device *dev, bd_t * bis) { - u32 i, rclk, clk = 0; + u32 i; + unsigned long clk_rate = 0; struct phy_device *phydev; const u32 stat_size = (sizeof(struct zynq_gem_regs) - offsetof(struct zynq_gem_regs, stat)) / 4; @@ -299,20 +314,18 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) readl(®s->stat[i]); /* Setup RxBD space */ - memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd)); - /* Create the RxBD ring */ - memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers)); + memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); for (i = 0; i < RX_BUF; i++) { priv->rx_bd[i].status = 0xF0000000; priv->rx_bd[i].addr = - (u32)((char *)&(priv->rxbuffers) + + ((u32)(priv->rxbuffers) + (i * PKTSIZE_ALIGN)); } /* WRAP bit to last BD */ priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; /* Write RxBDs to IP */ - writel((u32)&(priv->rx_bd), ®s->rxqbase); + writel((u32)priv->rx_bd, ®s->rxqbase); /* Setup for DMA Configuration register */ writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); @@ -326,7 +339,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) phy_detection(dev); /* interface - look at tsec */ - phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); + phydev = phy_connect(priv->bus, priv->phyaddr, dev, + PHY_INTERFACE_MODE_MII); phydev->supported = supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; @@ -335,30 +349,31 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) phy_config(phydev); phy_startup(phydev); + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return -1; + } + switch (phydev->speed) { case SPEED_1000: writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); - rclk = (0 << 4) | (1 << 0); - clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); - rclk = 1 << 0; - clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + clk_rate = ZYNQ_GEM_FREQUENCY_100; break; case SPEED_10: - rclk = 1 << 0; - /* FIXME untested */ - clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + clk_rate = ZYNQ_GEM_FREQUENCY_10; break; } /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) zynq_slcr_gem_clk_setup(dev->iobase != - ZYNQ_GEM_BASEADDR0, rclk, clk); + ZYNQ_GEM_BASEADDR0, clk_rate); setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); @@ -368,32 +383,35 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) { - u32 status; + u32 addr, size; struct zynq_gem_priv *priv = dev->priv; struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; - const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \ - ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK; /* setup BD */ - writel((u32)&(priv->tx_bd), ®s->txqbase); + writel((u32)priv->tx_bd, ®s->txqbase); /* Setup Tx BD */ - memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd)); + memset(priv->tx_bd, 0, sizeof(struct emac_bd)); + + priv->tx_bd->addr = (u32)ptr; + priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | + ZYNQ_GEM_TXBUF_LAST_MASK; - priv->tx_bd.addr = (u32)ptr; - priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK; + addr = (u32) ptr; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup(len, ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); + barrier(); /* Start transmit */ setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); - /* Read the stat register to know if the packet has been transmitted */ - status = readl(®s->txsr); - if (status & mask) - printf("Something has gone wrong here!? Status is 0x%x.\n", - status); + /* Read TX BD status */ + if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN) + printf("TX underrun\n"); + if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) + printf("TX buffers exhausted in mid frame\n"); - /* Clear Tx status register before leaving . */ - writel(status, ®s->txsr); return 0; } @@ -416,8 +434,12 @@ static int zynq_gem_recv(struct eth_device *dev) frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; if (frame_len) { - NetReceive((u8 *) (current_bd->addr & - ZYNQ_GEM_RXBUF_ADD_MASK), frame_len); + u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; + addr &= ~(ARCH_DMA_MINALIGN - 1); + u32 size = roundup(frame_len, ARCH_DMA_MINALIGN); + invalidate_dcache_range(addr, addr + size); + + NetReceive((u8 *)addr, frame_len); if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) priv->rx_first_buf = priv->rxbd_current; @@ -467,10 +489,12 @@ static int zynq_gem_miiphy_write(const char *devname, uchar addr, return phywrite(dev, addr, reg, val); } -int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) +int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, + int phy_addr, u32 emio) { struct eth_device *dev; struct zynq_gem_priv *priv; + void *bd_space; dev = calloc(1, sizeof(*dev)); if (dev == NULL) @@ -483,10 +507,22 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) } priv = dev->priv; + /* Align rxbuffers to ARCH_DMA_MINALIGN */ + priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); + memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); + + /* Align bd_space to 1MB */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF); + + /* Initialize the bd spaces for tx and rx bd's */ + priv->tx_bd = (struct emac_bd *)bd_space; + priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); + priv->phyaddr = phy_addr; priv->emio = emio; - sprintf(dev->name, "Gem.%x", base_addr); + sprintf(dev->name, "Gem.%lx", base_addr); dev->iobase = base_addr; @@ -503,3 +539,43 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) return 1; } + +#ifdef CONFIG_OF_CONTROL +int zynq_gem_of_init(const void *blob) +{ + int offset = 0; + u32 ret = 0; + u32 reg, phy_reg; + + debug("ZYNQ GEM: Initialization\n"); + + do { + offset = fdt_node_offset_by_compatible(blob, offset, + "xlnx,ps7-ethernet-1.00.a"); + if (offset != -1) { + reg = fdtdec_get_addr(blob, offset, "reg"); + if (reg != FDT_ADDR_T_NONE) { + offset = fdtdec_lookup_phandle(blob, offset, + "phy-handle"); + if (offset != -1) + phy_reg = fdtdec_get_addr(blob, offset, + "reg"); + else + phy_reg = 0; + + debug("ZYNQ GEM: addr %x, phyaddr %x\n", + reg, phy_reg); + + ret |= zynq_gem_initialize(NULL, reg, + phy_reg, 0); + + } else { + debug("ZYNQ GEM: Can't get base address\n"); + return -1; + } + } + } while (offset != -1); + + return ret; +} +#endif diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index be26b60592..50b7be53ca 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -5,36 +5,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libpci.o - -COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o -COBJS-$(CONFIG_PCI) += pci.o pci_auto.o -COBJS-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o -COBJS-$(CONFIG_PCI_GT64120) += pci_gt64120.o -COBJS-$(CONFIG_FTPCI100) += pci_ftpci100.o -COBJS-$(CONFIG_IXP_PCI) += pci_ixp.o -COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o -COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o -COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o -COBJS-$(CONFIG_TSI108_PCI) += tsi108_pci.o -COBJS-$(CONFIG_WINBOND_83C553) += w83c553f.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o +obj-$(CONFIG_PCI) += pci.o pci_auto.o pci_rom.o +obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o +obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o +obj-$(CONFIG_PCI_MSC01) += pci_msc01.o +obj-$(CONFIG_PCIE_IMX) += pcie_imx.o +obj-$(CONFIG_FTPCI100) += pci_ftpci100.o +obj-$(CONFIG_SH4_PCI) += pci_sh4.o +obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o +obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o +obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o +obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o +obj-$(CONFIG_WINBOND_83C553) += w83c553f.o +obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 17ca961abf..231b07573f 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -28,12 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; #include #include -/* Freescale-specific PCI config registers */ -#define FSL_PCI_PBFR 0x44 -#define FSL_PCIE_CAP_ID 0x4c -#define FSL_PCIE_CFG_RDY 0x4b0 -#define FSL_PROG_IF_AGENT 0x1 - #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS 0 #endif @@ -55,8 +49,13 @@ static void set_inbound_window(volatile pit_t *pi, u64 size) { u32 sz = (__ilog2_u64(size) - 1); - u32 flag = PIWAR_EN | PIWAR_LOCAL | - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + u32 flag = 0; +#else + u32 flag = PIWAR_LOCAL; +#endif + + flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; out_be32(&pi->pitar, r->phys_start >> 12); out_be32(&pi->piwbar, r->bus_start >> 12); @@ -301,6 +300,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int enabled, r, inbound = 0; u16 ltssm; u8 temp8, pcie_cap; + int pcie_cap_pos; + int pci_dcr; + int pci_dsr; + int pci_lsr; + +#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + int pci_lcr; +#endif + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; struct pci_region *reg = hose->regions + hose->region_count; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); @@ -373,7 +381,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) hose->region_count++; /* see if we are a PCIe or PCI controller */ - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_dcr = pcie_cap_pos + 0x08; + pci_dsr = pcie_cap_pos + 0x0a; + pci_lsr = pcie_cap_pos + 0x12; + + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ @@ -412,18 +425,28 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) * - Master PERR (pci) * - ICCA (PCIe) */ - pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); + pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32); temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ - pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); + pci_hose_write_config_dword(hose, dev, pci_dcr, temp32); #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + pci_lcr = pcie_cap_pos + 0x10; temp32 = 0; - pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); + pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32); temp32 &= ~0x03; /* Disable ASPM */ - pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); + pci_hose_write_config_dword(hose, dev, pci_lcr, temp32); udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { + if (block_rev >= PEX_IP_BLK_REV_3_0) { +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 + ltssm = (in_be32(&pci->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + enabled = (ltssm == 0x11) ? 1 : 0; + } else { + /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ + /* enabled = ltssm >= PCI_LTSSM_L0; */ pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); enabled = ltssm >= PCI_LTSSM_L0; @@ -456,6 +479,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) PCI_BASE_ADDRESS_0, pcicsrbar); } #endif + } #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { @@ -480,8 +504,14 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) } #endif if (!enabled) { - /* Let the user know there's no PCIe link */ - printf("no link, regs @ 0x%lx\n", pci_info->regs); + /* Let the user know there's no PCIe link for root + * complex. for endpoint, the link may not setup, so + * print undetermined. + */ + if (fsl_is_pci_agent(hose)) + printf("undetermined, regs @ 0x%lx\n", pci_info->regs); + else + printf("no link, regs @ 0x%lx\n", pci_info->regs); hose->last_busno = hose->first_busno; return; } @@ -490,9 +520,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) out_be32(&pci->pme_msg_int_en, 0xffffffff); /* Print the negotiated PCIe link width */ - pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); - printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, - pci_info->regs); + pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); + printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, + (temp16 & 0xf), pci_info->regs); hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); @@ -537,9 +567,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) out_be32(&pci->pme_msg_det, 0xffffffff); out_be32(&pci->pedr, 0xffffffff); - pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); + pci_hose_read_config_word(hose, dev, pci_dsr, &temp16); if (temp16) { - pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); + pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff); } pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); @@ -550,10 +580,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int fsl_is_pci_agent(struct pci_controller *hose) { + int pcie_cap_pos; u8 pcie_cap; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap == PCI_CAP_ID_EXP) { u8 header_type; @@ -564,6 +596,10 @@ int fsl_is_pci_agent(struct pci_controller *hose) u8 prog_if; pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + /* Programming Interface (PCI_CLASS_PROG) + * 0 == pci host or pcie root-complex, + * 1 == pci agent or pcie end-point + */ return (prog_if == FSL_PROG_IF_AGENT); } } @@ -574,6 +610,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, volatile ccsr_fsl_pci_t *pci; struct pci_region *r; pci_dev_t dev = PCI_BDF(busno,0,0); + int pcie_cap_pos; u8 pcie_cap; pci = (ccsr_fsl_pci_t *) pci_info->regs; @@ -623,11 +660,11 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, #endif } - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? "e" : "", pci_info->pci_num, hose->first_busno, hose->last_busno); - return(hose->last_busno + 1); } @@ -635,13 +672,15 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, void fsl_pci_config_unlock(struct pci_controller *hose) { pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); + int pcie_cap_pos; u8 pcie_cap; u16 pbfr; if (!fsl_is_pci_agent(hose)) return; - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap != 0x0) { /* PCIe - set CFG_READY bit of Configuration Ready Register */ pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 2c071589b4..950a2475c5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -19,6 +19,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #define PCI_HOSE_OP(rw, size, type) \ int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ pci_dev_t dev, \ @@ -123,6 +125,14 @@ void *pci_map_bar(pci_dev_t pdev, int bar, int flags) static struct pci_controller* hose_head; +struct pci_controller *pci_get_hose_head(void) +{ + if (gd->hose) + return gd->hose; + + return hose_head; +} + void pci_register_hose(struct pci_controller* hose) { struct pci_controller **phose = &hose_head; @@ -139,7 +149,7 @@ struct pci_controller *pci_bus_to_hose(int bus) { struct pci_controller *hose; - for (hose = hose_head; hose; hose = hose->next) { + for (hose = pci_get_hose_head(); hose; hose = hose->next) { if (bus >= hose->first_busno && bus <= hose->last_busno) return hose; } @@ -152,7 +162,7 @@ struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) { struct pci_controller *hose; - for (hose = hose_head; hose; hose = hose->next) { + for (hose = pci_get_hose_head(); hose; hose = hose->next) { if (hose->cfg_addr == cfg_addr) return hose; } @@ -162,7 +172,7 @@ struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) int pci_last_busno(void) { - struct pci_controller *hose = hose_head; + struct pci_controller *hose = pci_get_hose_head(); if (!hose) return -1; @@ -181,20 +191,18 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) pci_dev_t bdf; int i, bus, found_multi = 0; - for (hose = hose_head; hose; hose = hose->next) { + for (hose = pci_get_hose_head(); hose; hose = hose->next) { #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE for (bus = hose->last_busno; bus >= hose->first_busno; bus--) #else for (bus = hose->first_busno; bus <= hose->last_busno; bus++) #endif for (bdf = PCI_BDF(bus, 0, 0); -#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX) - bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, - PCI_MAX_PCI_FUNCTIONS - 1); -#else bdf < PCI_BDF(bus + 1, 0, 0); -#endif bdf += PCI_BDF(0, 0, 1)) { + if (pci_skip_dev(hose, bdf)) + continue; + if (!PCI_FUNC(bdf)) { pci_read_config_byte(bdf, PCI_HEADER_TYPE, @@ -230,7 +238,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) { - static struct pci_device_id ids[2] = {{}, {0, 0}}; + struct pci_device_id ids[2] = { {}, {0, 0} }; ids[0].vendor = vendor; ids[0].device = device; @@ -323,7 +331,7 @@ int __pci_hose_bus_to_phys(struct pci_controller *hose, continue; if (bus_addr >= res->bus_start && - bus_addr < res->bus_start + res->size) { + (bus_addr - res->bus_start) < res->size) { *pa = (bus_addr - res->bus_start + res->phys_start); return 0; } @@ -363,9 +371,27 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, return phys_addr; } -/* - * - */ +void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, + u32 addr_and_ctrl) +{ + int bar; + + bar = PCI_BASE_ADDRESS_0 + barnum * 4; + pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl); +} + +u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum) +{ + u32 addr; + int bar; + + bar = PCI_BASE_ADDRESS_0 + barnum * 4; + pci_hose_read_config_dword(hose, dev, bar, &addr); + if (addr & PCI_BASE_ADDRESS_SPACE_IO) + return addr & PCI_BASE_ADDRESS_IO_MASK; + else + return addr & PCI_BASE_ADDRESS_MEM_MASK; +} int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, @@ -572,7 +598,7 @@ const char * pci_class_str(u8 class) } #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */ -int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) +__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) { /* * Check if pci device should be skipped in configuration @@ -591,19 +617,15 @@ int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) return 0; } -int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) - __attribute__((weak, alias("__pci_skip_dev"))); #ifdef CONFIG_PCI_SCAN_SHOW -int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev) +__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) { if (dev == PCI_BDF(hose->first_busno, 0, 0)) return 0; return 1; } -int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) - __attribute__((weak, alias("__pci_print_dev"))); #endif /* CONFIG_PCI_SCAN_SHOW */ int pci_hose_scan_bus(struct pci_controller *hose, int bus) @@ -648,6 +670,10 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); +#ifdef CONFIG_PCI_FIXUP_DEV + board_pci_fixup_dev(hose, dev, vendor, device, class); +#endif + #ifdef CONFIG_PCI_SCAN_SHOW indent++; @@ -662,13 +688,15 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) #endif #ifdef CONFIG_PCI_PNP - sub_bus = max(pciauto_config_device(hose, dev), sub_bus); + sub_bus = max((unsigned int)pciauto_config_device(hose, dev), + sub_bus); #else cfg = pci_find_config(hose, class, vendor, device, PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); if (cfg) { cfg->config_device(hose, dev, cfg); - sub_bus = max(sub_bus, hose->current_busno); + sub_bus = max(sub_bus, + (unsigned int)hose->current_busno); } #endif @@ -686,11 +714,10 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) int pci_hose_scan(struct pci_controller *hose) { #if defined(CONFIG_PCI_BOOTDELAY) - static int pcidelay_done; char *s; int i; - if (!pcidelay_done) { + if (!gd->pcidelay_done) { /* wait "pcidelay" ms (if defined)... */ s = getenv("pcidelay"); if (s) { @@ -698,7 +725,7 @@ int pci_hose_scan(struct pci_controller *hose) for (i = 0; i < val; i++) udelay(1000); } - pcidelay_done = 1; + gd->pcidelay_done = 1; } #endif /* CONFIG_PCI_BOOTDELAY */ @@ -722,3 +749,68 @@ void pci_init(void) /* now call board specific pci_init()... */ pci_init_board(); } + +/* Returns the address of the requested capability structure within the + * device's PCI configuration space or 0 in case the device does not + * support it. + * */ +int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, + int cap) +{ + int pos; + u8 hdr_type; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); + + pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); + + if (pos) + pos = pci_find_cap(hose, dev, pos, cap); + + return pos; +} + +/* Find the header pointer to the Capabilities*/ +int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, + u8 hdr_type) +{ + u16 status; + + pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); + + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + switch (hdr_type) { + case PCI_HEADER_TYPE_NORMAL: + case PCI_HEADER_TYPE_BRIDGE: + return PCI_CAPABILITY_LIST; + case PCI_HEADER_TYPE_CARDBUS: + return PCI_CB_CAPABILITY_LIST; + default: + return 0; + } +} + +int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) +{ + int ttl = PCI_FIND_CAP_TTL; + u8 id; + u8 next_pos; + + while (ttl--) { + pci_hose_read_config_byte(hose, dev, pos, &next_pos); + if (next_pos < CAP_START_POS) + break; + next_pos &= ~3; + pos = (int) next_pos; + pci_hose_read_config_byte(hose, dev, + pos + PCI_CAP_LIST_ID, &id); + if (id == 0xff) + break; + if (id == cap) + return pos; + pos += PCI_CAP_LIST_NEXT; + } + return 0; +} diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index c4ed8ba6c3..ed92857406 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -11,7 +11,7 @@ */ #include - +#include #include #undef DEBUG @@ -191,6 +191,32 @@ void pciauto_setup_device(struct pci_controller *hose, pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } +int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev) +{ + pci_addr_t bar_value; + pci_size_t bar_size; + u32 bar_response; + u16 cmdstat = 0; + + pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe); + pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response); + if (!bar_response) + return -ENOENT; + + bar_size = -(bar_response & ~1); + DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size); + if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) { + pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, + bar_value); + } + DEBUGF("\n"); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); + + return 0; +} + void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { @@ -297,7 +323,7 @@ void pciauto_config_init(struct pci_controller *hose) { int i; - hose->pci_io = hose->pci_mem = NULL; + hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL; for (i = 0; i < hose->region_count; i++) { switch(hose->regions[i].flags) { @@ -387,7 +413,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) n = pci_hose_scan_bus(hose, hose->current_busno); /* figure out the deepest we've gone for this leg */ - sub_bus = max(n, sub_bus); + sub_bus = max((unsigned int)n, sub_bus); pciauto_postscan_setup_bridge(hose, dev, sub_bus); sub_bus = hose->current_busno; diff --git a/drivers/pci/pci_ixp.c b/drivers/pci/pci_ixp.c deleted file mode 100644 index d71fda2846..0000000000 --- a/drivers/pci/pci_ixp.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * IXP PCI Init - * - * (C) Copyright 2011 - * Michael Schwingen, michael@schwingen.org - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void non_prefetch_read(unsigned int addr, unsigned int cmd, - unsigned int *data); -static void non_prefetch_write(unsigned int addr, unsigned int cmd, - unsigned int data); - -/*define the sub vendor and subsystem to be used */ -#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 - -#define PCI_MEMORY_BUS 0x00000000 -#define PCI_MEMORY_PHY 0x00000000 -#define PCI_MEMORY_SIZE 0x04000000 - -#define PCI_MEM_BUS 0x48000000 -#define PCI_MEM_PHY 0x00000000 -#define PCI_MEM_SIZE 0x04000000 - -#define PCI_IO_BUS 0x00000000 -#define PCI_IO_PHY 0x00000000 -#define PCI_IO_SIZE 0x00010000 - -/* build address value for config sycle */ -static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg) -{ - unsigned int bus = PCI_BUS(bdf); - unsigned int dev = PCI_DEV(bdf); - unsigned int func = PCI_FUNC(bdf); - unsigned int addr; - - if (bus) { /* secondary bus, use type 1 config cycle */ - addr = bdf | (reg & ~3) | 1; - } else { - /* - primary bus, type 0 config cycle. address bits 31:28 - specify the device 10:8 specify the function - */ - addr = BIT((31 - dev)) | (func << 8) | (reg & ~3); - } - - return addr; -} - -static int pci_config_status(void) -{ - unsigned int regval; - - regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET); - if ((regval & PCI_ISR_PFE) == 0) - return OK; - - /* no device present, make sure that the master abort bit is reset */ - writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET); - return ERROR; -} - -static int pci_ixp_hose_read_config_dword(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned int *val) -{ - unsigned int retval; - unsigned int addr; - int stat; - - debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where); - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval); - *val = retval; - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_read_config_word(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned short *val) -{ - unsigned int n; - unsigned int retval; - unsigned int addr; - unsigned int byteEnables; - int stat; - - debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT(n) | BIT((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - - /*Pick out the word we are interested in */ - *val = retval >> (8 * n); - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_read_config_byte(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned char *val) -{ - unsigned int retval; - unsigned int n; - unsigned int byteEnables; - unsigned int addr; - int stat; - - debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where); - n = where % 4; - /*byte enables are 4 bits, active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - /*Pick out the byte we are interested in */ - *val = retval >> (8 * n); - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_write_config_byte(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned char val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - int stat; - - debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x", - bdf, where, val); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static int pci_ixp_hose_write_config_word(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned short val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - int stat; - - debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x", - bdf, where, val); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT(n) | BIT((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static int pci_ixp_hose_write_config_dword(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned int val) -{ - unsigned int addr; - int stat; - - debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x", - bdf, where, val); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static void non_prefetch_read(unsigned int addr, - unsigned int cmd, unsigned int *data) -{ - writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); - - /*set up and execute the read */ - writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); - - /*The result of the read is now in np_rdata */ - *data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET); - - return; -} - -static void non_prefetch_write(unsigned int addr, - unsigned int cmd, unsigned int data) -{ - - writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); - /*set up the write */ - writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); - /*Execute the write by writing to NP_WDATA */ - writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET); - - return; -} - -static void crp_write(unsigned int offset, unsigned int data) -{ - /* - * The CRP address register bit 16 indicates that we want to do a - * write - */ - writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET); - writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET); -} - -void pci_ixp_init(struct pci_controller *hose) -{ - unsigned int csr; - - /* - * Specify that the AHB bus is operating in big endian mode. Set up - * byte lane swapping between little-endian PCI and the big-endian - * AHB bus - */ -#ifdef __ARMEB__ - csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; -#else - csr = PCI_CSR_ABE; -#endif - writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET); - - writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET); - - /* - * We configure the PCI inbound memory windows to be - * 1:1 mapped to SDRAM - */ - crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000); - crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000); - crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000); - crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000); - - /* - * Enable CSR window at 64 MiB to allow PCI masters - * to continue prefetching past 64 MiB boundary. - */ - crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000); - /* - * Enable the IO window to be way up high, at 0xfffffc00 - */ - crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01); - - /*Setup PCI-AHB and AHB-PCI address mappings */ - writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET); - - writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET); - - writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET); - - crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); - - crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); - udelay(1000); - - /* clear error bits in status register */ - writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE, - PCI_CSR_BASE + PCI_ISR_OFFSET); - - /* - * Set Initialize Complete in PCI Control Register: allow IXP4XX to - * respond to PCI configuration cycles. - */ - csr |= PCI_CSR_IC; - writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET); - - hose->first_busno = 0; - hose->last_busno = 0; - - /* System memory space */ - pci_set_region(hose->regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - PCI_MEM_BUS, - PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); - /* PCI I/O space */ - pci_set_region(hose->regions + 2, - PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_set_ops(hose, - pci_ixp_hose_read_config_byte, - pci_ixp_hose_read_config_word, - pci_ixp_hose_read_config_dword, - pci_ixp_hose_write_config_byte, - pci_ixp_hose_write_config_word, - pci_ixp_hose_write_config_dword); - - pci_register_hose(hose); - hose->last_busno = pci_hose_scan(hose); -} diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c new file mode 100644 index 0000000000..284ffa09b6 --- /dev/null +++ b/drivers/pci/pci_msc01.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +struct msc01_pci_controller { + struct pci_controller hose; + void *base; +}; + +static inline struct msc01_pci_controller * +hose_to_msc01(struct pci_controller *hose) +{ + return container_of(hose, struct msc01_pci_controller, hose); +} + +static int msc01_config_access(struct msc01_pci_controller *msc01, + unsigned char access_type, pci_dev_t bdf, + int where, u32 *data) +{ + const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK; + void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS; + void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS; + unsigned int bus = PCI_BUS(bdf); + unsigned int dev = PCI_DEV(bdf); + unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf); + + /* clear abort status */ + __raw_writel(aborts, intstat); + + /* setup address */ + __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) | + (dev << MSC01_PCI_CFGADDR_DNUM_SHF) | + (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) | + ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF), + msc01->base + MSC01_PCI_CFGADDR_OFS); + + /* perform access */ + if (access_type == PCI_ACCESS_WRITE) + __raw_writel(*data, cfgdata); + else + *data = __raw_readl(cfgdata); + + /* check for aborts */ + if (__raw_readl(intstat) & aborts) { + /* clear abort status */ + __raw_writel(aborts, intstat); + return -1; + } + + return 0; +} + +static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev, + int where, u32 *value) +{ + struct msc01_pci_controller *msc01 = hose_to_msc01(hose); + + *value = 0xffffffff; + return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value); +} + +static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev, + int where, u32 value) +{ + struct msc01_pci_controller *gt = hose_to_msc01(hose); + u32 data = value; + + return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data); +} + +void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys, + unsigned long sys_size, unsigned long mem_bus, + unsigned long mem_phys, unsigned long mem_size, + unsigned long io_bus, unsigned long io_phys, + unsigned long io_size) +{ + static struct msc01_pci_controller global_msc01; + struct msc01_pci_controller *msc01; + struct pci_controller *hose; + + msc01 = &global_msc01; + msc01->base = base; + + hose = &msc01->hose; + + hose->first_busno = 0; + hose->last_busno = 0; + + /* System memory space */ + pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + /* PCI memory space */ + pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(&hose->regions[2], io_bus, io_phys, io_size, + PCI_REGION_IO); + + hose->region_count = 3; + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + msc01_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + msc01_write_config_dword); + + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); +} diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c new file mode 100644 index 0000000000..5729a152e5 --- /dev/null +++ b/drivers/pci/pci_rom.c @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c). + * + * Modifications are: + * Copyright (C) 2003-2004 Linux Networx + * (Written by Eric Biederman for Linux Networx) + * Copyright (C) 2003-2006 Ronald G. Minnich + * Copyright (C) 2004-2005 Li-Ta Lo + * Copyright (C) 2005-2006 Tyan + * (Written by Yinghai Lu for Tyan) + * Copyright (C) 2005-2009 coresystems GmbH + * (Written by Stefan Reinauer for coresystems GmbH) + * + * PCI Bus Services, see include/linux/pci.h for further explanation. + * + * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, + * David Mosberger-Tang + * + * Copyright 1997 -- 1999 Martin Mares + + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_HAVE_ACPI_RESUME +#include +#endif + +__weak bool board_should_run_oprom(pci_dev_t dev) +{ + return true; +} + +static bool should_load_oprom(pci_dev_t dev) +{ +#ifdef CONFIG_HAVE_ACPI_RESUME + if (acpi_get_slp_type() == 3) + return false; +#endif + if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + return 1; + if (board_should_run_oprom(dev)) + return 1; + + return 0; +} + +__weak uint32_t board_map_oprom_vendev(uint32_t vendev) +{ + return vendev; +} + +static int pci_rom_probe(pci_dev_t dev, uint class, + struct pci_rom_header **hdrp) +{ + struct pci_rom_header *rom_header; + struct pci_rom_data *rom_data; + u16 vendor, device; + u16 rom_vendor, rom_device; + u32 vendev; + u32 mapped_vendev; + u32 rom_address; + + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); + pci_read_config_word(dev, PCI_DEVICE_ID, &device); + vendev = vendor << 16 | device; + mapped_vendev = board_map_oprom_vendev(vendev); + if (vendev != mapped_vendev) + debug("Device ID mapped to %#08x\n", mapped_vendev); + +#ifdef CONFIG_X86_OPTION_ROM_ADDR + rom_address = CONFIG_X86_OPTION_ROM_ADDR; +#else + + if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) { + debug("Cannot find option ROM\n"); + return -ENOENT; + } + + pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address); + if (rom_address == 0x00000000 || rom_address == 0xffffffff) { + debug("%s: rom_address=%x\n", __func__, rom_address); + return -ENOENT; + } + + /* Enable expansion ROM address decoding. */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, + rom_address | PCI_ROM_ADDRESS_ENABLE); +#endif + debug("Option ROM address %x\n", rom_address); + rom_header = (struct pci_rom_header *)(unsigned long)rom_address; + + debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n", + le16_to_cpu(rom_header->signature), + rom_header->size * 512, le16_to_cpu(rom_header->data)); + + if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) { + printf("Incorrect expansion ROM header signature %04x\n", + le16_to_cpu(rom_header->signature)); + return -EINVAL; + } + + rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data)); + rom_vendor = le16_to_cpu(rom_data->vendor); + rom_device = le16_to_cpu(rom_data->device); + + debug("PCI ROM image, vendor ID %04x, device ID %04x,\n", + rom_vendor, rom_device); + + /* If the device id is mapped, a mismatch is expected */ + if ((vendor != rom_vendor || device != rom_device) && + (vendev == mapped_vendev)) { + printf("ID mismatch: vendor ID %04x, device ID %04x\n", + rom_vendor, rom_device); + /* Continue anyway */ + } + + debug("PCI ROM image, Class Code %04x%02x, Code Type %02x\n", + rom_data->class_hi, rom_data->class_lo, rom_data->type); + + if (class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { + debug("Class Code mismatch ROM %08x, dev %08x\n", + (rom_data->class_hi << 8) | rom_data->class_lo, + class); + } + *hdrp = rom_header; + + return 0; +} + +int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header, + struct pci_rom_header **ram_headerp) +{ + struct pci_rom_data *rom_data; + unsigned int rom_size; + unsigned int image_size = 0; + void *target; + + do { + /* Get next image, until we see an x86 version */ + rom_header = (struct pci_rom_header *)((void *)rom_header + + image_size); + + rom_data = (struct pci_rom_data *)((void *)rom_header + + le16_to_cpu(rom_header->data)); + + image_size = le16_to_cpu(rom_data->ilen) * 512; + } while ((rom_data->type != 0) && (rom_data->indicator == 0)); + + if (rom_data->type != 0) + return -EACCES; + + rom_size = rom_header->size * 512; + +#ifdef PCI_VGA_RAM_IMAGE_START + target = (void *)PCI_VGA_RAM_IMAGE_START; +#else + target = (void *)malloc(rom_size); + if (!target) + return -ENOMEM; +#endif + if (target != rom_header) { + ulong start = get_timer(0); + + debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n", + rom_header, target, rom_size); + memcpy(target, rom_header, rom_size); + if (memcmp(target, rom_header, rom_size)) { + printf("VGA ROM copy failed\n"); + return -EFAULT; + } + debug("Copy took %lums\n", get_timer(start)); + } + *ram_headerp = target; + + return 0; +} + +static struct vbe_mode_info mode_info; + +int vbe_get_video_info(struct graphic_device *gdev) +{ +#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE + struct vesa_mode_info *vesa = &mode_info.vesa; + + gdev->winSizeX = vesa->x_resolution; + gdev->winSizeY = vesa->y_resolution; + + gdev->plnSizeX = vesa->x_resolution; + gdev->plnSizeY = vesa->y_resolution; + + gdev->gdfBytesPP = vesa->bits_per_pixel / 8; + + switch (vesa->bits_per_pixel) { + case 24: + gdev->gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + gdev->gdfIndex = GDF_16BIT_565RGB; + break; + default: + gdev->gdfIndex = GDF__8BIT_INDEX; + break; + } + + gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; + gdev->pciBase = vesa->phys_base_ptr; + + gdev->frameAdrs = vesa->phys_base_ptr; + gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution; + + gdev->vprBase = vesa->phys_base_ptr; + gdev->cprBase = vesa->phys_base_ptr; + + return gdev->winSizeX ? 0 : -ENOSYS; +#else + return -ENOSYS; +#endif +} + +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate) +{ + struct pci_rom_header *rom, *ram; + int vesa_mode = -1; + uint16_t class; + int ret; + + /* Only execute VGA ROMs */ + pci_read_config_word(dev, PCI_CLASS_DEVICE, &class); + if ((class ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) { + debug("%s: Class %#x, should be %#x\n", __func__, class, + PCI_CLASS_DISPLAY_VGA); + return -ENODEV; + } + + if (!should_load_oprom(dev)) + return -ENXIO; + + ret = pci_rom_probe(dev, class, &rom); + if (ret) + return ret; + + ret = pci_rom_load(class, rom, &ram); + if (ret) + return ret; + + if (!board_should_run_oprom(dev)) + return -ENXIO; + +#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \ + defined(CONFIG_FRAMEBUFFER_VESA_MODE) + vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE; +#endif + debug("Selected vesa mode %#x\n", vesa_mode); + if (emulate) { +#ifdef CONFIG_BIOSEMU + BE_VGAInfo *info; + + ret = biosemu_setup(dev, &info); + if (ret) + return ret; + biosemu_set_interrupt_handler(0x15, int15_handler); + ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true, + vesa_mode, &mode_info); + if (ret) + return ret; +#else + printf("BIOS emulation not available - see CONFIG_BIOSEMU\n"); + return -ENOSYS; +#endif + } else { +#ifdef CONFIG_X86 + bios_set_interrupt_handler(0x15, int15_handler); + + bios_run_on_x86(dev, (unsigned long)ram, vesa_mode, + &mode_info); +#else + printf("BIOS native execution is only available on x86\n"); + return -ENOSYS; +#endif + } + debug("Final vesa mode %#x\n", mode_info.video_mode); + + return 0; +} diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c new file mode 100644 index 0000000000..67b5fdf07c --- /dev/null +++ b/drivers/pci/pci_tegra.c @@ -0,0 +1,1143 @@ +/* + * Copyright (c) 2010, CompuLab, Ltd. + * Author: Mike Rapoport + * + * Based on NVIDIA PCIe driver + * Copyright (c) 2008-2009, NVIDIA Corporation. + * + * Copyright (c) 2013-2014, NVIDIA Corporation. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#define DEBUG +#define pr_fmt(fmt) "tegra-pcie: " fmt + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define AFI_AXI_BAR0_SZ 0x00 +#define AFI_AXI_BAR1_SZ 0x04 +#define AFI_AXI_BAR2_SZ 0x08 +#define AFI_AXI_BAR3_SZ 0x0c +#define AFI_AXI_BAR4_SZ 0x10 +#define AFI_AXI_BAR5_SZ 0x14 + +#define AFI_AXI_BAR0_START 0x18 +#define AFI_AXI_BAR1_START 0x1c +#define AFI_AXI_BAR2_START 0x20 +#define AFI_AXI_BAR3_START 0x24 +#define AFI_AXI_BAR4_START 0x28 +#define AFI_AXI_BAR5_START 0x2c + +#define AFI_FPCI_BAR0 0x30 +#define AFI_FPCI_BAR1 0x34 +#define AFI_FPCI_BAR2 0x38 +#define AFI_FPCI_BAR3 0x3c +#define AFI_FPCI_BAR4 0x40 +#define AFI_FPCI_BAR5 0x44 + +#define AFI_CACHE_BAR0_SZ 0x48 +#define AFI_CACHE_BAR0_ST 0x4c +#define AFI_CACHE_BAR1_SZ 0x50 +#define AFI_CACHE_BAR1_ST 0x54 + +#define AFI_MSI_BAR_SZ 0x60 +#define AFI_MSI_FPCI_BAR_ST 0x64 +#define AFI_MSI_AXI_BAR_ST 0x68 + +#define AFI_CONFIGURATION 0xac +#define AFI_CONFIGURATION_EN_FPCI (1 << 0) + +#define AFI_FPCI_ERROR_MASKS 0xb0 + +#define AFI_INTR_MASK 0xb4 +#define AFI_INTR_MASK_INT_MASK (1 << 0) +#define AFI_INTR_MASK_MSI_MASK (1 << 8) + +#define AFI_SM_INTR_ENABLE 0xc4 +#define AFI_SM_INTR_INTA_ASSERT (1 << 0) +#define AFI_SM_INTR_INTB_ASSERT (1 << 1) +#define AFI_SM_INTR_INTC_ASSERT (1 << 2) +#define AFI_SM_INTR_INTD_ASSERT (1 << 3) +#define AFI_SM_INTR_INTA_DEASSERT (1 << 4) +#define AFI_SM_INTR_INTB_DEASSERT (1 << 5) +#define AFI_SM_INTR_INTC_DEASSERT (1 << 6) +#define AFI_SM_INTR_INTD_DEASSERT (1 << 7) + +#define AFI_AFI_INTR_ENABLE 0xc8 +#define AFI_INTR_EN_INI_SLVERR (1 << 0) +#define AFI_INTR_EN_INI_DECERR (1 << 1) +#define AFI_INTR_EN_TGT_SLVERR (1 << 2) +#define AFI_INTR_EN_TGT_DECERR (1 << 3) +#define AFI_INTR_EN_TGT_WRERR (1 << 4) +#define AFI_INTR_EN_DFPCI_DECERR (1 << 5) +#define AFI_INTR_EN_AXI_DECERR (1 << 6) +#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) +#define AFI_INTR_EN_PRSNT_SENSE (1 << 8) + +#define AFI_PCIE_CONFIG 0x0f8 +#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) +#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) + +#define AFI_FUSE 0x104 +#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) + +#define AFI_PEX0_CTRL 0x110 +#define AFI_PEX1_CTRL 0x118 +#define AFI_PEX2_CTRL 0x128 +#define AFI_PEX_CTRL_RST (1 << 0) +#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) +#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) +#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) + +#define AFI_PLLE_CONTROL 0x160 +#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) +#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) + +#define AFI_PEXBIAS_CTRL_0 0x168 + +#define PADS_CTL_SEL 0x0000009C + +#define PADS_CTL 0x000000A0 +#define PADS_CTL_IDDQ_1L (1 << 0) +#define PADS_CTL_TX_DATA_EN_1L (1 << 6) +#define PADS_CTL_RX_DATA_EN_1L (1 << 10) + +#define PADS_PLL_CTL_TEGRA20 0x000000B8 +#define PADS_PLL_CTL_TEGRA30 0x000000B4 +#define PADS_PLL_CTL_RST_B4SM (0x1 << 1) +#define PADS_PLL_CTL_LOCKDET (0x1 << 8) +#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) +#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) +#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) +#define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) +#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) +#define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) +#define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) +#define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) + +#define PADS_REFCLK_CFG0 0x000000C8 +#define PADS_REFCLK_CFG1 0x000000CC + +/* + * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit + * entries, one entry per PCIe port. These field definitions and desired + * values aren't in the TRM, but do come from NVIDIA. + */ +#define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ +#define PADS_REFCLK_CFG_E_TERM_SHIFT 7 +#define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ +#define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ + +/* Default value provided by HW engineering is 0xfa5c */ +#define PADS_REFCLK_CFG_VALUE \ + ( \ + (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ + (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ + (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ + (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ + ) + +#define RP_VEND_XP 0x00000F00 +#define RP_VEND_XP_DL_UP (1 << 30) + +#define RP_PRIV_MISC 0x00000FE0 +#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) + +#define RP_LINK_CONTROL_STATUS 0x00000090 +#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 +#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 + +struct tegra_pcie; + +struct tegra_pcie_port { + struct tegra_pcie *pcie; + + struct fdt_resource regs; + unsigned int num_lanes; + unsigned int index; + + struct list_head list; +}; + +struct tegra_pcie_soc { + unsigned int num_ports; + unsigned long pads_pll_ctl; + unsigned long tx_ref_sel; + bool has_pex_clkreq_en; + bool has_pex_bias_ctrl; + bool has_cml_clk; + bool has_gen2; +}; + +struct tegra_pcie { + struct pci_controller hose; + + struct fdt_resource pads; + struct fdt_resource afi; + struct fdt_resource cs; + + struct fdt_resource prefetch; + struct fdt_resource mem; + struct fdt_resource io; + + struct list_head ports; + unsigned long xbar; + + const struct tegra_pcie_soc *soc; + struct tegra_xusb_phy *phy; +}; + +static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose) +{ + return container_of(hose, struct tegra_pcie, hose); +} + +static void afi_writel(struct tegra_pcie *pcie, unsigned long value, + unsigned long offset) +{ + writel(value, pcie->afi.start + offset); +} + +static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) +{ + return readl(pcie->afi.start + offset); +} + +static void pads_writel(struct tegra_pcie *pcie, unsigned long value, + unsigned long offset) +{ + writel(value, pcie->pads.start + offset); +} + +static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) +{ + return readl(pcie->pads.start + offset); +} + +static unsigned long rp_readl(struct tegra_pcie_port *port, + unsigned long offset) +{ + return readl(port->regs.start + offset); +} + +static void rp_writel(struct tegra_pcie_port *port, unsigned long value, + unsigned long offset) +{ + writel(value, port->regs.start + offset); +} + +static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) +{ + return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | + (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | + (where & 0xfc); +} + +static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, + int where, unsigned long *address) +{ + unsigned int bus = PCI_BUS(bdf); + + if (bus == 0) { + unsigned int dev = PCI_DEV(bdf); + struct tegra_pcie_port *port; + + list_for_each_entry(port, &pcie->ports, list) { + if (port->index + 1 == dev) { + *address = port->regs.start + (where & ~3); + return 0; + } + } + } else { + *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); + return 0; + } + + return -1; +} + +static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf, + int where, u32 *value) +{ + struct tegra_pcie *pcie = to_tegra_pcie(hose); + unsigned long address; + int err; + + err = tegra_pcie_conf_address(pcie, bdf, where, &address); + if (err < 0) { + *value = 0xffffffff; + return 1; + } + + *value = readl(address); + + /* fixup root port class */ + if (PCI_BUS(bdf) == 0) { + if (where == PCI_CLASS_REVISION) { + *value &= ~0x00ff0000; + *value |= PCI_CLASS_BRIDGE_PCI << 16; + } + } + + return 0; +} + +static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf, + int where, u32 value) +{ + struct tegra_pcie *pcie = to_tegra_pcie(hose); + unsigned long address; + int err; + + err = tegra_pcie_conf_address(pcie, bdf, where, &address); + if (err < 0) + return 1; + + writel(value, address); + + return 0; +} + +static int tegra_pcie_port_parse_dt(const void *fdt, int node, + struct tegra_pcie_port *port) +{ + const u32 *addr; + int len; + + addr = fdt_getprop(fdt, node, "assigned-addresses", &len); + if (!addr) { + error("property \"assigned-addresses\" not found"); + return -FDT_ERR_NOTFOUND; + } + + port->regs.start = fdt32_to_cpu(addr[2]); + port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); + + return 0; +} + +static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, + unsigned long *xbar) +{ + enum fdt_compat_id id = fdtdec_lookup(fdt, node); + + switch (id) { + case COMPAT_NVIDIA_TEGRA20_PCIE: + switch (lanes) { + case 0x00000004: + debug("single-mode configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; + return 0; + + case 0x00000202: + debug("dual-mode configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; + return 0; + } + break; + + case COMPAT_NVIDIA_TEGRA30_PCIE: + switch (lanes) { + case 0x00000204: + debug("4x1, 2x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; + return 0; + + case 0x00020202: + debug("2x3 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; + return 0; + + case 0x00010104: + debug("4x1, 1x2 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; + return 0; + } + break; + + case COMPAT_NVIDIA_TEGRA124_PCIE: + switch (lanes) { + case 0x0000104: + debug("4x1, 1x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; + return 0; + + case 0x0000102: + debug("2x1, 1x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; + return 0; + } + break; + + default: + break; + } + + return -FDT_ERR_NOTFOUND; +} + +static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, + struct tegra_pcie *pcie) +{ + const u32 *ptr, *end; + int len; + + ptr = fdt_getprop(fdt, node, "ranges", &len); + if (!ptr) { + error("missing \"ranges\" property"); + return -FDT_ERR_NOTFOUND; + } + + end = ptr + len / 4; + + while (ptr < end) { + struct fdt_resource *res = NULL; + u32 space = fdt32_to_cpu(*ptr); + + switch ((space >> 24) & 0x3) { + case 0x01: + res = &pcie->io; + break; + + case 0x02: /* 32 bit */ + case 0x03: /* 64 bit */ + if (space & (1 << 30)) + res = &pcie->prefetch; + else + res = &pcie->mem; + + break; + } + + if (res) { + res->start = fdt32_to_cpu(ptr[3]); + res->end = res->start + fdt32_to_cpu(ptr[5]); + } + + ptr += 3 + 1 + 2; + } + + debug("PCI regions:\n"); + debug(" I/O: %#x-%#x\n", pcie->io.start, pcie->io.end); + debug(" non-prefetchable memory: %#x-%#x\n", pcie->mem.start, + pcie->mem.end); + debug(" prefetchable memory: %#x-%#x\n", pcie->prefetch.start, + pcie->prefetch.end); + + return 0; +} + +static int tegra_pcie_parse_port_info(const void *fdt, int node, + unsigned int *index, + unsigned int *lanes) +{ + struct fdt_pci_addr addr; + int err; + + err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); + if (err < 0) { + error("failed to parse \"nvidia,num-lanes\" property"); + return err; + } + + *lanes = err; + + err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr); + if (err < 0) { + error("failed to parse \"reg\" property"); + return err; + } + + *index = PCI_DEV(addr.phys_hi) - 1; + + return 0; +} + +static int tegra_pcie_parse_dt(const void *fdt, int node, + struct tegra_pcie *pcie) +{ + int err, subnode; + u32 lanes = 0; + + err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads", + &pcie->pads); + if (err < 0) { + error("resource \"pads\" not found"); + return err; + } + + err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi", + &pcie->afi); + if (err < 0) { + error("resource \"afi\" not found"); + return err; + } + + err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs", + &pcie->cs); + if (err < 0) { + error("resource \"cs\" not found"); + return err; + } + + pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); + if (pcie->phy) { + err = tegra_xusb_phy_prepare(pcie->phy); + if (err < 0) { + error("failed to prepare PHY: %d", err); + return err; + } + } + + err = tegra_pcie_parse_dt_ranges(fdt, node, pcie); + if (err < 0) { + error("failed to parse \"ranges\" property"); + return err; + } + + fdt_for_each_subnode(fdt, subnode, node) { + unsigned int index = 0, num_lanes = 0; + struct tegra_pcie_port *port; + + err = tegra_pcie_parse_port_info(fdt, subnode, &index, + &num_lanes); + if (err < 0) { + error("failed to obtain root port info"); + continue; + } + + lanes |= num_lanes << (index << 3); + + if (!fdtdec_get_is_enabled(fdt, subnode)) + continue; + + port = malloc(sizeof(*port)); + if (!port) + continue; + + memset(port, 0, sizeof(*port)); + port->num_lanes = num_lanes; + port->index = index; + + err = tegra_pcie_port_parse_dt(fdt, subnode, port); + if (err < 0) { + free(port); + continue; + } + + list_add_tail(&port->list, &pcie->ports); + port->pcie = pcie; + } + + err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar); + if (err < 0) { + error("invalid lane configuration"); + return err; + } + + return 0; +} + +int __weak tegra_pcie_board_init(void) +{ + return 0; +} + +static int tegra_pcie_power_on(struct tegra_pcie *pcie) +{ + const struct tegra_pcie_soc *soc = pcie->soc; + unsigned long value; + int err; + + /* reset PCIEXCLK logic, AFI controller and PCIe controller */ + reset_set_enable(PERIPH_ID_PCIEXCLK, 1); + reset_set_enable(PERIPH_ID_AFI, 1); + reset_set_enable(PERIPH_ID_PCIE, 1); + + err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); + if (err < 0) { + error("failed to power off PCIe partition: %d", err); + return err; + } + + tegra_pcie_board_init(); + + err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, + PERIPH_ID_PCIE); + if (err < 0) { + error("failed to power up PCIe partition: %d", err); + return err; + } + + /* take AFI controller out of reset */ + reset_set_enable(PERIPH_ID_AFI, 0); + + /* enable AFI clock */ + clock_enable(PERIPH_ID_AFI); + + if (soc->has_cml_clk) { + /* enable CML clock */ + value = readl(NV_PA_CLK_RST_BASE + 0x48c); + value |= (1 << 0); + value &= ~(1 << 1); + writel(value, NV_PA_CLK_RST_BASE + 0x48c); + } + + err = tegra_plle_enable(); + if (err < 0) { + error("failed to enable PLLE: %d\n", err); + return err; + } + + return 0; +} + +static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) +{ + const struct tegra_pcie_soc *soc = pcie->soc; + unsigned long start = get_timer(0); + u32 value; + + while (get_timer(start) < timeout) { + value = pads_readl(pcie, soc->pads_pll_ctl); + if (value & PADS_PLL_CTL_LOCKDET) + return 0; + } + + return -ETIMEDOUT; +} + +static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) +{ + const struct tegra_pcie_soc *soc = pcie->soc; + u32 value; + int err; + + /* initialize internal PHY, enable up to 16 PCIe lanes */ + pads_writel(pcie, 0, PADS_CTL_SEL); + + /* override IDDQ to 1 on all 4 lanes */ + value = pads_readl(pcie, PADS_CTL); + value |= PADS_CTL_IDDQ_1L; + pads_writel(pcie, value, PADS_CTL); + + /* + * Set up PHY PLL inputs select PLLE output as refclock, set TX + * ref sel to div10 (not div5). + */ + value = pads_readl(pcie, soc->pads_pll_ctl); + value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); + value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; + pads_writel(pcie, value, soc->pads_pll_ctl); + + /* reset PLL */ + value = pads_readl(pcie, soc->pads_pll_ctl); + value &= ~PADS_PLL_CTL_RST_B4SM; + pads_writel(pcie, value, soc->pads_pll_ctl); + + udelay(20); + + /* take PLL out of reset */ + value = pads_readl(pcie, soc->pads_pll_ctl); + value |= PADS_PLL_CTL_RST_B4SM; + pads_writel(pcie, value, soc->pads_pll_ctl); + + /* configure the reference clock driver */ + value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); + pads_writel(pcie, value, PADS_REFCLK_CFG0); + + if (soc->num_ports > 2) + pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); + + /* wait for the PLL to lock */ + err = tegra_pcie_pll_wait(pcie, 500); + if (err < 0) { + error("PLL failed to lock: %d", err); + return err; + } + + /* turn off IDDQ override */ + value = pads_readl(pcie, PADS_CTL); + value &= ~PADS_CTL_IDDQ_1L; + pads_writel(pcie, value, PADS_CTL); + + /* enable TX/RX data */ + value = pads_readl(pcie, PADS_CTL); + value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; + pads_writel(pcie, value, PADS_CTL); + + return 0; +} + +static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) +{ + const struct tegra_pcie_soc *soc = pcie->soc; + struct tegra_pcie_port *port; + u32 value; + int err; + + if (pcie->phy) { + value = afi_readl(pcie, AFI_PLLE_CONTROL); + value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; + value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; + afi_writel(pcie, value, AFI_PLLE_CONTROL); + } + + if (soc->has_pex_bias_ctrl) + afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); + + value = afi_readl(pcie, AFI_PCIE_CONFIG); + value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; + value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; + + list_for_each_entry(port, &pcie->ports, list) + value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); + + afi_writel(pcie, value, AFI_PCIE_CONFIG); + + value = afi_readl(pcie, AFI_FUSE); + + if (soc->has_gen2) + value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; + else + value |= AFI_FUSE_PCIE_T0_GEN2_DIS; + + afi_writel(pcie, value, AFI_FUSE); + + if (pcie->phy) + err = tegra_xusb_phy_enable(pcie->phy); + else + err = tegra_pcie_phy_enable(pcie); + + if (err < 0) { + error("failed to power on PHY: %d\n", err); + return err; + } + + /* take the PCIEXCLK logic out of reset */ + reset_set_enable(PERIPH_ID_PCIEXCLK, 0); + + /* finally enable PCIe */ + value = afi_readl(pcie, AFI_CONFIGURATION); + value |= AFI_CONFIGURATION_EN_FPCI; + afi_writel(pcie, value, AFI_CONFIGURATION); + + /* disable all interrupts */ + afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); + afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); + afi_writel(pcie, 0, AFI_INTR_MASK); + afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); + + return 0; +} + +static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) +{ + unsigned long fpci, axi, size; + + /* BAR 0: type 1 extended configuration space */ + fpci = 0xfe100000; + size = fdt_resource_size(&pcie->cs); + axi = pcie->cs.start; + + afi_writel(pcie, axi, AFI_AXI_BAR0_START); + afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); + afi_writel(pcie, fpci, AFI_FPCI_BAR0); + + /* BAR 1: downstream I/O */ + fpci = 0xfdfc0000; + size = fdt_resource_size(&pcie->io); + axi = pcie->io.start; + + afi_writel(pcie, axi, AFI_AXI_BAR1_START); + afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); + afi_writel(pcie, fpci, AFI_FPCI_BAR1); + + /* BAR 2: prefetchable memory */ + fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; + size = fdt_resource_size(&pcie->prefetch); + axi = pcie->prefetch.start; + + afi_writel(pcie, axi, AFI_AXI_BAR2_START); + afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); + afi_writel(pcie, fpci, AFI_FPCI_BAR2); + + /* BAR 3: non-prefetchable memory */ + fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; + size = fdt_resource_size(&pcie->mem); + axi = pcie->mem.start; + + afi_writel(pcie, axi, AFI_AXI_BAR3_START); + afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); + afi_writel(pcie, fpci, AFI_FPCI_BAR3); + + /* NULL out the remaining BARs as they are not used */ + afi_writel(pcie, 0, AFI_AXI_BAR4_START); + afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); + afi_writel(pcie, 0, AFI_FPCI_BAR4); + + afi_writel(pcie, 0, AFI_AXI_BAR5_START); + afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); + afi_writel(pcie, 0, AFI_FPCI_BAR5); + + /* map all upstream transactions as uncached */ + afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); + afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); + + /* MSI translations are setup only when needed */ + afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); + afi_writel(pcie, 0, AFI_MSI_BAR_SZ); + afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); + afi_writel(pcie, 0, AFI_MSI_BAR_SZ); +} + +static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) +{ + unsigned long ret = 0; + + switch (port->index) { + case 0: + ret = AFI_PEX0_CTRL; + break; + + case 1: + ret = AFI_PEX1_CTRL; + break; + + case 2: + ret = AFI_PEX2_CTRL; + break; + } + + return ret; +} + +static void tegra_pcie_port_reset(struct tegra_pcie_port *port) +{ + unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); + unsigned long value; + + /* pulse reset signel */ + value = afi_readl(port->pcie, ctrl); + value &= ~AFI_PEX_CTRL_RST; + afi_writel(port->pcie, value, ctrl); + + udelay(2000); + + value = afi_readl(port->pcie, ctrl); + value |= AFI_PEX_CTRL_RST; + afi_writel(port->pcie, value, ctrl); +} + +static void tegra_pcie_port_enable(struct tegra_pcie_port *port) +{ + unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); + unsigned long value; + + /* enable reference clock */ + value = afi_readl(port->pcie, ctrl); + value |= AFI_PEX_CTRL_REFCLK_EN; + + if (port->pcie->soc->has_pex_clkreq_en) + value |= AFI_PEX_CTRL_CLKREQ_EN; + + value |= AFI_PEX_CTRL_OVERRIDE_EN; + + afi_writel(port->pcie, value, ctrl); + + tegra_pcie_port_reset(port); +} + +static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) +{ + unsigned int retries = 3; + unsigned long value; + + value = rp_readl(port, RP_PRIV_MISC); + value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; + value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; + rp_writel(port, value, RP_PRIV_MISC); + + do { + unsigned int timeout = 200; + + do { + value = rp_readl(port, RP_VEND_XP); + if (value & RP_VEND_XP_DL_UP) + break; + + udelay(2000); + } while (--timeout); + + if (!timeout) { + debug("link %u down, retrying\n", port->index); + goto retry; + } + + timeout = 200; + + do { + value = rp_readl(port, RP_LINK_CONTROL_STATUS); + if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) + return true; + + udelay(2000); + } while (--timeout); + +retry: + tegra_pcie_port_reset(port); + } while (--retries); + + return false; +} + +static void tegra_pcie_port_disable(struct tegra_pcie_port *port) +{ + unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); + unsigned long value; + + /* assert port reset */ + value = afi_readl(port->pcie, ctrl); + value &= ~AFI_PEX_CTRL_RST; + afi_writel(port->pcie, value, ctrl); + + /* disable reference clock */ + value = afi_readl(port->pcie, ctrl); + value &= ~AFI_PEX_CTRL_REFCLK_EN; + afi_writel(port->pcie, value, ctrl); +} + +static void tegra_pcie_port_free(struct tegra_pcie_port *port) +{ + list_del(&port->list); + free(port); +} + +static int tegra_pcie_enable(struct tegra_pcie *pcie) +{ + struct tegra_pcie_port *port, *tmp; + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + debug("probing port %u, using %u lanes\n", port->index, + port->num_lanes); + + tegra_pcie_port_enable(port); + + if (tegra_pcie_port_check_link(port)) + continue; + + debug("link %u down, ignoring\n", port->index); + + tegra_pcie_port_disable(port); + tegra_pcie_port_free(port); + } + + return 0; +} + +static const struct tegra_pcie_soc tegra20_pcie_soc = { + .num_ports = 2, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, + .has_pex_clkreq_en = false, + .has_pex_bias_ctrl = false, + .has_cml_clk = false, + .has_gen2 = false, +}; + +static const struct tegra_pcie_soc tegra30_pcie_soc = { + .num_ports = 3, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_cml_clk = true, + .has_gen2 = false, +}; + +static const struct tegra_pcie_soc tegra124_pcie_soc = { + .num_ports = 2, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_cml_clk = true, + .has_gen2 = true, +}; + +static int process_nodes(const void *fdt, int nodes[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) { + const struct tegra_pcie_soc *soc; + struct tegra_pcie *pcie; + enum fdt_compat_id id; + int err; + + if (!fdtdec_get_is_enabled(fdt, nodes[i])) + continue; + + id = fdtdec_lookup(fdt, nodes[i]); + switch (id) { + case COMPAT_NVIDIA_TEGRA20_PCIE: + soc = &tegra20_pcie_soc; + break; + + case COMPAT_NVIDIA_TEGRA30_PCIE: + soc = &tegra30_pcie_soc; + break; + + case COMPAT_NVIDIA_TEGRA124_PCIE: + soc = &tegra124_pcie_soc; + break; + + default: + error("unsupported compatible: %s", + fdtdec_get_compatible(id)); + continue; + } + + pcie = malloc(sizeof(*pcie)); + if (!pcie) { + error("failed to allocate controller"); + continue; + } + + memset(pcie, 0, sizeof(*pcie)); + pcie->soc = soc; + + INIT_LIST_HEAD(&pcie->ports); + + err = tegra_pcie_parse_dt(fdt, nodes[i], pcie); + if (err < 0) { + free(pcie); + continue; + } + + err = tegra_pcie_power_on(pcie); + if (err < 0) { + error("failed to power on"); + continue; + } + + err = tegra_pcie_enable_controller(pcie); + if (err < 0) { + error("failed to enable controller"); + continue; + } + + tegra_pcie_setup_translations(pcie); + + err = tegra_pcie_enable(pcie); + if (err < 0) { + error("failed to enable PCIe"); + continue; + } + + pcie->hose.first_busno = 0; + pcie->hose.current_busno = 0; + pcie->hose.last_busno = 0; + + pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, + NV_PA_SDRAM_BASE, gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + pci_set_region(&pcie->hose.regions[1], pcie->io.start, + pcie->io.start, fdt_resource_size(&pcie->io), + PCI_REGION_IO); + + pci_set_region(&pcie->hose.regions[2], pcie->mem.start, + pcie->mem.start, fdt_resource_size(&pcie->mem), + PCI_REGION_MEM); + + pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start, + pcie->prefetch.start, + fdt_resource_size(&pcie->prefetch), + PCI_REGION_MEM | PCI_REGION_PREFETCH); + + pcie->hose.region_count = 4; + + pci_set_ops(&pcie->hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + tegra_pcie_read_conf, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + tegra_pcie_write_conf); + + pci_register_hose(&pcie->hose); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Enumerating devices...\n"); + printf("---------------------------------------\n"); + printf(" Device ID Description\n"); + printf(" ------ -- -----------\n"); +#endif + + pcie->hose.last_busno = pci_hose_scan(&pcie->hose); + } + + return 0; +} + +void pci_init_board(void) +{ + const void *fdt = gd->fdt_blob; + int count, nodes[1]; + + count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", + COMPAT_NVIDIA_TEGRA124_PCIE, + nodes, ARRAY_SIZE(nodes)); + if (process_nodes(fdt, nodes, count)) + return; + + count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", + COMPAT_NVIDIA_TEGRA30_PCIE, + nodes, ARRAY_SIZE(nodes)); + if (process_nodes(fdt, nodes, count)) + return; + + count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", + COMPAT_NVIDIA_TEGRA20_PCIE, + nodes, ARRAY_SIZE(nodes)); + if (process_nodes(fdt, nodes, count)) + return; +} + +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) +{ + if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0) + return 1; + + return 0; +} diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c new file mode 100644 index 0000000000..67450cb578 --- /dev/null +++ b/drivers/pci/pcie_imx.c @@ -0,0 +1,649 @@ +/* + * Freescale i.MX6 PCI Express Root-Complex driver + * + * Copyright (C) 2013 Marek Vasut + * + * Based on upstream Linux kernel driver: + * pci-imx6.c: Sean Cross + * pcie-designware.c: Jingoo Han + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#ifdef CONFIG_SOC_MX6SX +#define MX6_DBI_ADDR 0x08ffc000 +#define MX6_IO_ADDR 0x08000000 +#define MX6_MEM_ADDR 0x08100000 +#define MX6_ROOT_ADDR 0x08f00000 +#else +#define MX6_DBI_ADDR 0x01ffc000 +#define MX6_IO_ADDR 0x01000000 +#define MX6_MEM_ADDR 0x01100000 +#define MX6_ROOT_ADDR 0x01f00000 +#endif +#define MX6_DBI_SIZE 0x4000 +#define MX6_IO_SIZE 0x100000 +#define MX6_MEM_SIZE 0xe00000 +#define MX6_ROOT_SIZE 0xfc000 + +/* PCIe Port Logic registers (memory-mapped) */ +#define PL_OFFSET 0x700 +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) + +#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) +#define PCIE_PHY_CTRL_DATA_LOC 0 +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 +#define PCIE_PHY_CTRL_WR_LOC 18 +#define PCIE_PHY_CTRL_RD_LOC 19 + +#define PCIE_PHY_STAT (PL_OFFSET + 0x110) +#define PCIE_PHY_STAT_DATA_LOC 0 +#define PCIE_PHY_STAT_ACK_LOC 16 + +/* PHY registers (not memory-mapped) */ +#define PCIE_PHY_RX_ASIC_OUT 0x100D + +#define PHY_RX_OVRD_IN_LO 0x1005 +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) + +#define PCIE_PHY_PUP_REQ (1 << 7) + +/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + +/* + * PHY access functions + */ +static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) +{ + u32 val; + u32 max_iterations = 10; + u32 wait_counter = 0; + + do { + val = readl(dbi_base + PCIE_PHY_STAT); + val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; + wait_counter++; + + if (val == exp_val) + return 0; + + udelay(1); + } while (wait_counter < max_iterations); + + return -ETIMEDOUT; +} + +static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) +{ + u32 val; + int ret; + + val = addr << PCIE_PHY_CTRL_DATA_LOC; + writel(val, dbi_base + PCIE_PHY_CTRL); + + val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); + writel(val, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + val = addr << PCIE_PHY_CTRL_DATA_LOC; + writel(val, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + return 0; +} + +/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ +static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) +{ + u32 val, phy_ctl; + int ret; + + ret = pcie_phy_wait_ack(dbi_base, addr); + if (ret) + return ret; + + /* assert Read signal */ + phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; + writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + val = readl(dbi_base + PCIE_PHY_STAT); + *data = val & 0xffff; + + /* deassert Read signal */ + writel(0x00, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + return 0; +} + +static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) +{ + u32 var; + int ret; + + /* write addr */ + /* cap addr */ + ret = pcie_phy_wait_ack(dbi_base, addr); + if (ret) + return ret; + + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* capture data */ + var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); + writel(var, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + /* deassert cap data */ + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack de-assertion */ + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + /* assert wr signal */ + var = 0x1 << PCIE_PHY_CTRL_WR_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack */ + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + /* deassert wr signal */ + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack de-assertion */ + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + writel(0x0, dbi_base + PCIE_PHY_CTRL); + + return 0; +} + +static int imx6_pcie_link_up(void) +{ + u32 rc, ltssm; + int rx_valid, temp; + + /* link is debug bit 36, debug register 1 starts at bit 32 */ + rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1); + if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) && + !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)) + return -EAGAIN; + + /* + * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. + * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). + * If (MAC/LTSSM.state == Recovery.RcvrLock) + * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition + * to gen2 is stuck + */ + pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid); + ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F; + + if (rx_valid & 0x01) + return 0; + + if (ltssm != 0x0d) + return 0; + + printf("transition to gen2 is stuck, reset PHY!\n"); + + pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); + temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); + + udelay(3000); + + pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); + temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); + + return 0; +} + +/* + * iATU region setup + */ +static int imx_pcie_regions_setup(void) +{ + /* + * i.MX6 defines 16MB in the AXI address map for PCIe. + * + * That address space excepted the pcie registers is + * split and defined into different regions by iATU, + * with sizes and offsets as follows: + * + * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO + * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM + * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers + */ + + /* CMD reg:I/O space, MEM space, and Bus Master Enable */ + setbits_le32(MX6_DBI_ADDR | PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ + setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION, + PCI_CLASS_BRIDGE_PCI << 16); + + /* Region #0 is used for Outbound CFG space access. */ + writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); + + writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE); + writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE); + writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT); + + writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); + writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET); + writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); + writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2); + + return 0; +} + +/* + * PCI Express accessors + */ +static uint32_t get_bus_address(pci_dev_t d, int where) +{ + uint32_t va_address; + + /* Reconfigure Region #0 */ + writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); + + if (PCI_BUS(d) < 2) + writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); + else + writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1); + + if (PCI_BUS(d) == 0) { + va_address = MX6_DBI_ADDR; + } else { + writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); + va_address = MX6_IO_ADDR + SZ_16M - SZ_1M; + } + + va_address += (where & ~0x3); + + return va_address; +} + +static int imx_pcie_addr_valid(pci_dev_t d) +{ + if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1)) + return -EINVAL; + if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0)) + return -EINVAL; + return 0; +} + +/* + * Replace the original ARM DABT handler with a simple jump-back one. + * + * The problem here is that if we have a PCIe bridge attached to this PCIe + * controller, but no PCIe device is connected to the bridges' downstream + * port, the attempt to read/write from/to the config space will produce + * a DABT. This is a behavior of the controller and can not be disabled + * unfortuatelly. + * + * To work around the problem, we backup the current DABT handler address + * and replace it with our own DABT handler, which only bounces right back + * into the code. + */ +static void imx_pcie_fix_dabt_handler(bool set) +{ + extern uint32_t *_data_abort; + uint32_t *data_abort_addr = (uint32_t *)&_data_abort; + + static const uint32_t data_abort_bounce_handler = 0xe25ef004; + uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler; + + static uint32_t data_abort_backup; + + if (set) { + data_abort_backup = *data_abort_addr; + *data_abort_addr = data_abort_bounce_addr; + } else { + *data_abort_addr = data_abort_backup; + } +} + +static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 *val) +{ + uint32_t va_address; + int ret; + + ret = imx_pcie_addr_valid(d); + if (ret) { + *val = 0xffffffff; + return ret; + } + + va_address = get_bus_address(d, where); + + /* + * Read the PCIe config space. We must replace the DABT handler + * here in case we got data abort from the PCIe controller, see + * imx_pcie_fix_dabt_handler() description. Note that writing the + * "val" with valid value is also imperative here as in case we + * did got DABT, the val would contain random value. + */ + imx_pcie_fix_dabt_handler(true); + writel(0xffffffff, val); + *val = readl(va_address); + imx_pcie_fix_dabt_handler(false); + + return 0; +} + +static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 val) +{ + uint32_t va_address = 0; + int ret; + + ret = imx_pcie_addr_valid(d); + if (ret) + return ret; + + va_address = get_bus_address(d, where); + + /* + * Write the PCIe config space. We must replace the DABT handler + * here in case we got data abort from the PCIe controller, see + * imx_pcie_fix_dabt_handler() description. + */ + imx_pcie_fix_dabt_handler(true); + writel(val, va_address); + imx_pcie_fix_dabt_handler(false); + + return 0; +} + +/* + * Initial bus setup + */ +static int imx6_pcie_assert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; +#if defined(CONFIG_SOC_MX6SX) + struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; + + /* SSP_EN is not used on MX6SX anymore */ + setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); + /* Force PCIe PHY reset */ + setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); + /* Power up PCIe PHY */ + setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); +#else + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); +#endif + + return 0; +} + +static int imx6_pcie_init_phy(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_DEVICE_TYPE_MASK, + IOMUXC_GPR12_DEVICE_TYPE_RC); + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_LOS_LEVEL_MASK, + IOMUXC_GPR12_LOS_LEVEL_9); + +#ifdef CONFIG_SOC_MX6SX + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_RX_EQ_MASK, + IOMUXC_GPR12_RX_EQ_2); +#endif + + writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | + (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | + (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET), + &iomuxc_regs->gpr[8]); + + return 0; +} + +__weak int imx6_pcie_toggle_power(void) +{ +#ifdef CONFIG_PCIE_IMX_POWER_GPIO + gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); + mdelay(20); + gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); + mdelay(20); +#endif + return 0; +} + +__weak int imx6_pcie_toggle_reset(void) +{ + /* + * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1' + * for detailed understanding of the PCIe CR reset logic. + * + * The PCIe #PERST reset line _MUST_ be connected, otherwise your + * design does not conform to the specification. You must wait at + * least 20 mS after de-asserting the #PERST so the EP device can + * do self-initialisation. + * + * In case your #PERST pin is connected to a plain GPIO pin of the + * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's + * configuration file and the condition below will handle the rest + * of the reset toggling. + * + * In case your #PERST toggling logic is more complex, for example + * connected via CPLD or somesuch, you can override this function + * in your board file and implement reset logic as needed. You must + * not forget to wait at least 20 mS after de-asserting #PERST in + * this case either though. + * + * In case your #PERST line of the PCIe EP device is not connected + * at all, your design is broken and you should fix your design, + * otherwise you will observe problems like for example the link + * not coming up after rebooting the system back from running Linux + * that uses the PCIe as well OR the PCIe link might not come up in + * Linux at all in the first place since it's in some non-reset + * state due to being previously used in U-Boot. + */ +#ifdef CONFIG_PCIE_IMX_PERST_GPIO + gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); + mdelay(20); + gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); + mdelay(20); +#else + puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); +#endif + return 0; +} + +static int imx6_pcie_deassert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + imx6_pcie_toggle_power(); + + enable_pcie_clock(); + + /* + * Wait for the clock to settle a bit, when the clock are sourced + * from the CPU, we need about 30mS to settle. + */ + mdelay(50); + +#if defined(CONFIG_SOC_MX6SX) + /* SSP_EN is not used on MX6SX anymore */ + clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); + /* Clear PCIe PHY reset bit */ + clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); +#else + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); +#endif + + imx6_pcie_toggle_reset(); + + return 0; +} + +static int imx_pcie_link_up(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + uint32_t tmp; + int count = 0; + + imx6_pcie_assert_core_reset(); + imx6_pcie_init_phy(); + imx6_pcie_deassert_core_reset(); + + imx_pcie_regions_setup(); + + /* + * FIXME: Force the PCIe RC to Gen1 operation + * The RC must be forced into Gen1 mode before bringing the link + * up, otherwise no downstream devices are detected. After the + * link is up, a managed Gen1->Gen2 transition can be initiated. + */ + tmp = readl(MX6_DBI_ADDR + 0x7c); + tmp &= ~0xf; + tmp |= 0x1; + writel(tmp, MX6_DBI_ADDR + 0x7c); + + /* LTSSM enable, starting link. */ + setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + while (!imx6_pcie_link_up()) { + udelay(10); + count++; + if (count >= 2000) { + debug("phy link never came up\n"); + debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", + readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), + readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); + return -EINVAL; + } + } + + return 0; +} + +void imx_pcie_init(void) +{ + /* Static instance of the controller. */ + static struct pci_controller pcc; + struct pci_controller *hose = &pcc; + int ret; + + memset(&pcc, 0, sizeof(pcc)); + + /* PCI I/O space */ + pci_set_region(&hose->regions[0], + MX6_IO_ADDR, MX6_IO_ADDR, + MX6_IO_SIZE, PCI_REGION_IO); + + /* PCI memory space */ + pci_set_region(&hose->regions[1], + MX6_MEM_ADDR, MX6_MEM_ADDR, + MX6_MEM_SIZE, PCI_REGION_MEM); + + /* System memory space */ + pci_set_region(&hose->regions[2], + MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR, + 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 3; + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + imx_pcie_read_config, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + imx_pcie_write_config); + + /* Start the controller. */ + ret = imx_pcie_link_up(); + + if (!ret) { + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); + } +} + +/* Probe function. */ +void pci_init_board(void) +{ + imx_pcie_init(); +} diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c new file mode 100644 index 0000000000..291c249c86 --- /dev/null +++ b/drivers/pci/pcie_layerscape.c @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Layerscape PCIe driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_OF_BOARD_SETUP +#include +#include + +static void ft_pcie_ls_setup(void *blob, const char *pci_compat, + unsigned long ctrl_addr, enum srds_prtcl dev) +{ + int off; + + off = fdt_node_offset_by_compat_reg(blob, pci_compat, + (phys_addr_t)ctrl_addr); + if (off < 0) + return; + + if (!is_serdes_configured(dev)) + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +} + +void ft_pcie_setup(void *blob, bd_t *bd) +{ + #ifdef CONFIG_PCIE1 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); + #endif + + #ifdef CONFIG_PCIE2 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); + #endif +} + +#else +void ft_pcie_setup(void *blob, bd_t *bd) +{ +} +#endif + +void pci_init_board(void) +{ +} diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 80a132eb4b..c506f796fa 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -5,31 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libpcmcia.o - -COBJS-$(CONFIG_I82365) += i82365.o -COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o -COBJS-y += rpx_pcmcia.o -COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o -COBJS-y += tqm8xx_pcmcia.o -COBJS-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o +obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o +obj-y += tqm8xx_pcmcia.o +obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o diff --git a/drivers/pcmcia/i82365.c b/drivers/pcmcia/i82365.c deleted file mode 100644 index 84a3d2ecb3..0000000000 --- a/drivers/pcmcia/i82365.c +++ /dev/null @@ -1,989 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - ******************************************************************** - * - * Lots of code copied from: - * - * i82365.c 1.352 - Linux driver for Intel 82365 and compatible - * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. - * (C) 1999 David A. Hinds - */ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#ifdef CONFIG_CPC45 -#include -#else -#include -#endif - -static struct pci_device_id supported[] = { -#ifdef CONFIG_CPC45 - {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, -#else - {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510}, -#endif - {0, 0} -}; - -#define CYCLE_TIME 120 - -#ifdef CONFIG_CPC45 -extern int SPD67290Init (void); -#endif - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev); -#endif - -typedef struct socket_info_t { - pci_dev_t dev; - u_short bcr; - u_char pci_lat, cb_lat, sub_bus, cache; - u_int cb_phys; - - socket_cap_t cap; - u_short type; - u_int flags; -#ifdef CONFIG_CPC45 - cirrus_state_t c_state; -#else - ti113x_state_t state; -#endif -} socket_info_t; - -#ifdef CONFIG_CPC45 -/* These definitions must match the pcic table! */ -typedef enum pcic_id { - IS_PD6710, IS_PD672X, IS_VT83C469 -} pcic_id; - -typedef struct pcic_t { - char *name; -} pcic_t; - -static pcic_t pcic[] = { - {" Cirrus PD6710: "}, - {" Cirrus PD672x: "}, - {" VIA VT83C469: "}, -}; -#endif - -static socket_info_t socket; -static socket_state_t state; -static struct pccard_mem_map mem; -static struct pccard_io_map io; - -/*====================================================================*/ - -/* Some PCI shortcuts */ - -static int pci_readb (socket_info_t * s, int r, u_char * v) -{ - return pci_read_config_byte (s->dev, r, v); -} -static int pci_writeb (socket_info_t * s, int r, u_char v) -{ - return pci_write_config_byte (s->dev, r, v); -} -static int pci_readw (socket_info_t * s, int r, u_short * v) -{ - return pci_read_config_word (s->dev, r, v); -} -static int pci_writew (socket_info_t * s, int r, u_short v) -{ - return pci_write_config_word (s->dev, r, v); -} -#ifndef CONFIG_CPC45 -static int pci_readl (socket_info_t * s, int r, u_int * v) -{ - return pci_read_config_dword (s->dev, r, v); -} -static int pci_writel (socket_info_t * s, int r, u_int v) -{ - return pci_write_config_dword (s->dev, r, v); -} -#endif /* !CONFIG_CPC45 */ - -/*====================================================================*/ - -#ifdef CONFIG_CPC45 - -#define cb_readb(s) readb((s)->cb_phys + 1) -#define cb_writeb(s, v) writeb(v, (s)->cb_phys) -#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1) -#define cb_readl(s, r) readl((s)->cb_phys + (r)) -#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) - - -static u_char i365_get (socket_info_t * s, u_short reg) -{ - u_char val; -#ifdef CONFIG_PCMCIA_SLOT_A - int slot = 0; -#else - int slot = 1; -#endif - - val = I365_REG (slot, reg); - - cb_writeb (s, val); - val = cb_readb (s); - - debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val); - return val; -} - -static void i365_set (socket_info_t * s, u_short reg, u_char data) -{ -#ifdef CONFIG_PCMCIA_SLOT_A - int slot = 0; -#else - int slot = 1; -#endif - u_char val; - - val = I365_REG (slot, reg); - - cb_writeb (s, val); - cb_writeb2 (s, data); - - debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data); -} - -#else /* ! CONFIG_CPC45 */ - -#define cb_readb(s, r) readb((s)->cb_phys + (r)) -#define cb_readl(s, r) readl((s)->cb_phys + (r)) -#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r)) -#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) - -static u_char i365_get (socket_info_t * s, u_short reg) -{ - return cb_readb (s, 0x0800 + reg); -} - -static void i365_set (socket_info_t * s, u_short reg, u_char data) -{ - cb_writeb (s, 0x0800 + reg, data); -} -#endif /* CONFIG_CPC45 */ - -static void i365_bset (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) | mask); -} - -static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) & ~mask); -} - -#if 0 /* not used */ -static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) -{ - u_char d = i365_get (s, reg); - - i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); -} - -static u_short i365_get_pair (socket_info_t * s, u_short reg) -{ - return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); -} -#endif /* not used */ - -static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) -{ - i365_set (s, reg, data & 0xff); - i365_set (s, reg + 1, data >> 8); -} - -#ifdef CONFIG_CPC45 -/*====================================================================== - - Code to save and restore global state information for Cirrus - PD67xx controllers, and to set and report global configuration - options. - -======================================================================*/ - -#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) - -static void cirrus_get_state (socket_info_t * s) -{ - int i; - cirrus_state_t *p = &s->c_state; - - p->misc1 = i365_get (s, PD67_MISC_CTL_1); - p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); - p->misc2 = i365_get (s, PD67_MISC_CTL_2); - for (i = 0; i < 6; i++) - p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i); - -} - -static void cirrus_set_state (socket_info_t * s) -{ - int i; - u_char misc; - cirrus_state_t *p = &s->c_state; - - misc = i365_get (s, PD67_MISC_CTL_2); - i365_set (s, PD67_MISC_CTL_2, p->misc2); - if (misc & PD67_MC2_SUSPEND) - udelay (50000); - misc = i365_get (s, PD67_MISC_CTL_1); - misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); - i365_set (s, PD67_MISC_CTL_1, misc | p->misc1); - for (i = 0; i < 6; i++) - i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]); -} - -static u_int cirrus_set_opts (socket_info_t * s) -{ - cirrus_state_t *p = &s->c_state; - u_int mask = 0xffff; - char buf[200] = {0}; - - if (has_ring == -1) - has_ring = 1; - flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring); - flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); -#if DEBUG - if (p->misc2 & PD67_MC2_IRQ15_RI) - strcat (buf, " [ring]"); - if (p->misc2 & PD67_MC2_DYNAMIC_MODE) - strcat (buf, " [dyn mode]"); - if (p->misc1 & PD67_MC1_INPACK_ENA) - strcat (buf, " [inpack]"); -#endif - - if (p->misc2 & PD67_MC2_IRQ15_RI) - mask &= ~0x8000; - if (has_led > 0) { -#if DEBUG - strcat (buf, " [led]"); -#endif - mask &= ~0x1000; - } - if (has_dma > 0) { -#if DEBUG - strcat (buf, " [dma]"); -#endif - mask &= ~0x0600; - flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); -#if DEBUG - if (p->misc2 & PD67_MC2_FREQ_BYPASS) - strcat (buf, " [freq bypass]"); -#endif - } - - if (setup_time >= 0) - p->timer[0] = p->timer[3] = setup_time; - if (cmd_time > 0) { - p->timer[1] = cmd_time; - p->timer[4] = cmd_time * 2 + 4; - } - if (p->timer[1] == 0) { - p->timer[1] = 6; - p->timer[4] = 16; - if (p->timer[0] == 0) - p->timer[0] = p->timer[3] = 1; - } - if (recov_time >= 0) - p->timer[2] = p->timer[5] = recov_time; - - debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n", - buf, - p->timer[0], p->timer[1], p->timer[2], - p->timer[3], p->timer[4], p->timer[5]); - - return mask; -} - -#else /* !CONFIG_CPC45 */ - -/*====================================================================== - - Code to save and restore global state information for TI 1130 and - TI 1131 controllers, and to set and report global configuration - options. - -======================================================================*/ - -static void ti113x_get_state (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - - pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl); - pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl); - pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl); - pci_readb (s, TI1250_DIAGNOSTIC, &p->diag); - pci_readl (s, TI12XX_IRQMUX, &p->irqmux); -} - -static void ti113x_set_state (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - - pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl); - pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl); - pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl); - pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0); - pci_writeb (s, TI1250_DIAGNOSTIC, p->diag); - pci_writel (s, TI12XX_IRQMUX, p->irqmux); - i365_set_pair (s, TI113X_IO_OFFSET (0), 0); - i365_set_pair (s, TI113X_IO_OFFSET (1), 0); -} - -static u_int ti113x_set_opts (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - u_int mask = 0xffff; - - p->cardctl &= ~TI113X_CCR_ZVENABLE; - p->cardctl |= TI113X_CCR_SPKROUTEN; - - return mask; -} -#endif /* CONFIG_CPC45 */ - -/*====================================================================== - - Routines to handle common CardBus options - -======================================================================*/ - -/* Default settings for PCI command configuration register */ -#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ - PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) - -static void cb_get_state (socket_info_t * s) -{ - pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); - pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); - pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); - pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); - pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); - pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); -} - -static void cb_set_state (socket_info_t * s) -{ -#ifndef CONFIG_CPC45 - pci_writel (s, CB_LEGACY_MODE_BASE, 0); - pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys); -#endif - pci_writew (s, PCI_COMMAND, CMD_DFLT); - pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); - pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); - pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); - pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); - pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); - pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); -} - -static void cb_set_opts (socket_info_t * s) -{ -#ifndef CONFIG_CPC45 - if (s->cache == 0) - s->cache = 8; - if (s->pci_lat == 0) - s->pci_lat = 0xa8; - if (s->cb_lat == 0) - s->cb_lat = 0xb0; -#endif -} - -/*====================================================================== - - Power control for Cardbus controllers: used both for 16-bit and - Cardbus cards. - -======================================================================*/ - -static int cb_set_power (socket_info_t * s, socket_state_t * state) -{ - u_int reg = 0; - -#ifdef CONFIG_CPC45 - - reg = I365_PWR_NORESET; - if (state->flags & SS_PWR_AUTO) - reg |= I365_PWR_AUTO; - if (state->flags & SS_OUTPUT_ENA) - reg |= I365_PWR_OUT; - if (state->Vpp != 0) { - if (state->Vpp == 120) { - reg |= I365_VPP1_12V; - puts (" 12V card found: "); - } else if (state->Vpp == state->Vcc) { - reg |= I365_VPP1_5V; - } else { - puts (" power not found: "); - return -1; - } - } - if (state->Vcc != 0) { - reg |= I365_VCC_5V; - if (state->Vcc == 33) { - puts (" 3.3V card found: "); - i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else if (state->Vcc == 50) { - puts (" 5V card found: "); - i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else { - puts (" power not found: "); - return -1; - } - } - - if (reg != i365_get (s, I365_POWER)) { - reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V); - i365_set (s, I365_POWER, reg); - } - -#else /* ! CONFIG_CPC45 */ - - /* restart card voltage detection if it seems appropriate */ - if ((state->Vcc == 0) && (state->Vpp == 0) && - !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE)) - cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST); - switch (state->Vcc) { - case 0: - reg = 0; - break; - case 33: - reg = CB_SC_VCC_3V; - break; - case 50: - reg = CB_SC_VCC_5V; - break; - default: - return -1; - } - switch (state->Vpp) { - case 0: - break; - case 33: - reg |= CB_SC_VPP_3V; - break; - case 50: - reg |= CB_SC_VPP_5V; - break; - case 120: - reg |= CB_SC_VPP_12V; - break; - default: - return -1; - } - if (reg != cb_readl (s, CB_SOCKET_CONTROL)) - cb_writel (s, CB_SOCKET_CONTROL, reg); -#endif /* CONFIG_CPC45 */ - return 0; -} - -/*====================================================================== - - Generic routines to get and set controller options - -======================================================================*/ - -static void get_bridge_state (socket_info_t * s) -{ -#ifdef CONFIG_CPC45 - cirrus_get_state (s); -#else - ti113x_get_state (s); -#endif - cb_get_state (s); -} - -static void set_bridge_state (socket_info_t * s) -{ - cb_set_state (s); - i365_set (s, I365_GBLCTL, 0x00); - i365_set (s, I365_GENCTL, 0x00); -#ifdef CONFIG_CPC45 - cirrus_set_state (s); -#else - ti113x_set_state (s); -#endif -} - -static void set_bridge_opts (socket_info_t * s) -{ -#ifdef CONFIG_CPC45 - cirrus_set_opts (s); -#else - ti113x_set_opts (s); -#endif - cb_set_opts (s); -} - -/*====================================================================*/ -#define PD67_EXT_INDEX 0x2e /* Extension index */ -#define PD67_EXT_DATA 0x2f /* Extension data */ -#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) - -#define pd67_ext_get(s, r) \ - (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) - -static int i365_get_status (socket_info_t * s, u_int * value) -{ - u_int status; -#ifdef CONFIG_CPC45 - u_char val; - u_char power, vcc, vpp; - u_int powerstate; -#endif - - status = i365_get (s, I365_IDENT); - status = i365_get (s, I365_STATUS); - *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; - if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { - *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; - } else { - *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; - *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; - } - *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; - *value |= (status & I365_CS_READY) ? SS_READY : 0; - *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; - -#ifdef CONFIG_CPC45 - /* Check for Cirrus CL-PD67xx chips */ - i365_set (s, PD67_CHIP_INFO, 0); - val = i365_get (s, PD67_CHIP_INFO); - s->type = -1; - if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { - val = i365_get (s, PD67_CHIP_INFO); - if ((val & PD67_INFO_CHIP_ID) == 0) { - s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; - i365_set (s, PD67_EXT_INDEX, 0xe5); - if (i365_get (s, PD67_EXT_INDEX) != 0xe5) - s->type = IS_VT83C469; - } - } else { - printf ("no Cirrus Chip found\n"); - *value = 0; - return -1; - } - - power = i365_get (s, I365_POWER); - state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; - state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; - vcc = power & I365_VCC_MASK; - vpp = power & I365_VPP1_MASK; - state.Vcc = state.Vpp = 0; - if((vcc== 0) || (vpp == 0)) { - /* - * On the Cirrus we get the info which card voltage - * we have in EXTERN DATA and write it to MISC_CTL1 - */ - powerstate = pd67_ext_get(s, PD67_EXTERN_DATA); - if (powerstate & PD67_EXD_VS1(0)) { - /* 5V Card */ - i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else { - /* 3.3V Card */ - i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } - i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V)); - power = i365_get (s, I365_POWER); - } - if (power & I365_VCC_5V) { - state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50; - } - - if (power == I365_VPP1_12V) - state.Vpp = 120; - - /* IO card, RESET flags, IO interrupt */ - power = i365_get (s, I365_INTCTL); - state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET; - if (power & I365_PC_IOCARD) - state.flags |= SS_IOCARD; - state.io_irq = power & I365_IRQ_MASK; - - /* Card status change mask */ - power = i365_get (s, I365_CSCINT); - state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0; - if (state.flags & SS_IOCARD) - state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0; - else { - state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0; - state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0; - state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0; - } - debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, " - "io_irq %d, csc_mask %#2.2x\n", state.flags, - state.Vcc, state.Vpp, state.io_irq, state.csc_mask); - -#else /* !CONFIG_CPC45 */ - - status = cb_readl (s, CB_SOCKET_STATE); - *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0; - *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0; - *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0; - *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING; - /* For now, ignore cards with unsupported voltage keys */ - if (*value & SS_XVCARD) - *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD); -#endif /* CONFIG_CPC45 */ - return 0; -} /* i365_get_status */ - -static int i365_set_socket (socket_info_t * s, socket_state_t * state) -{ - u_char reg; - - set_bridge_state (s); - - /* IO card, RESET flag */ - reg = 0; - reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; - reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; - i365_set (s, I365_INTCTL, reg); - -#ifdef CONFIG_CPC45 - cb_set_power (s, state); - -#if 0 - /* Card status change interrupt mask */ - reg = s->cs_irq << 4; - if (state->csc_mask & SS_DETECT) - reg |= I365_CSC_DETECT; - if (state->flags & SS_IOCARD) { - if (state->csc_mask & SS_STSCHG) - reg |= I365_CSC_STSCHG; - } else { - if (state->csc_mask & SS_BATDEAD) - reg |= I365_CSC_BVD1; - if (state->csc_mask & SS_BATWARN) - reg |= I365_CSC_BVD2; - if (state->csc_mask & SS_READY) - reg |= I365_CSC_READY; - } - i365_set (s, I365_CSCINT, reg); - i365_get (s, I365_CSC); -#endif /* 0 */ - -#else /* !CONFIG_CPC45 */ - - reg = I365_PWR_NORESET; - if (state->flags & SS_PWR_AUTO) - reg |= I365_PWR_AUTO; - if (state->flags & SS_OUTPUT_ENA) - reg |= I365_PWR_OUT; - - cb_set_power (s, state); - reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK); - - if (reg != i365_get (s, I365_POWER)) - i365_set (s, I365_POWER, reg); -#endif /* CONFIG_CPC45 */ - - return 0; -} /* i365_set_socket */ - -/*====================================================================*/ - -static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) -{ - u_short base, i; - u_char map; - - debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", - mem->map, mem->flags, mem->speed, - mem->sys_start, mem->sys_stop, mem->card_start); - - map = mem->map; - if ((map > 4) || - (mem->card_start > 0x3ffffff) || - (mem->sys_start > mem->sys_stop) || - (mem->speed > 1000)) { - return -1; - } - - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); - - /* Take care of high byte, for PCI controllers */ - i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); - - base = I365_MEM (map); - i = (mem->sys_start >> 12) & 0x0fff; - if (mem->flags & MAP_16BIT) - i |= I365_MEM_16BIT; - if (mem->flags & MAP_0WS) - i |= I365_MEM_0WS; - i365_set_pair (s, base + I365_W_START, i); - - i = (mem->sys_stop >> 12) & 0x0fff; - switch (mem->speed / CYCLE_TIME) { - case 0: - break; - case 1: - i |= I365_MEM_WS0; - break; - case 2: - i |= I365_MEM_WS1; - break; - default: - i |= I365_MEM_WS1 | I365_MEM_WS0; - break; - } - i365_set_pair (s, base + I365_W_STOP, i); - -#ifdef CONFIG_CPC45 - i = 0; -#else - i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff; -#endif - if (mem->flags & MAP_WRPROT) - i |= I365_MEM_WRPROT; - if (mem->flags & MAP_ATTRIB) - i |= I365_MEM_REG; - i365_set_pair (s, base + I365_W_OFF, i); - -#ifdef CONFIG_CPC45 - /* set System Memory map Upper Adress */ - i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map)); - i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff)); -#endif - - /* Turn on the window if necessary */ - if (mem->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); - return 0; -} /* i365_set_mem_map */ - -static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) -{ - u_char map, ioctl; - - map = io->map; - /* comment out: comparison is always false due to limited range of data type */ - if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ - (io->stop < io->start)) - return -1; - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); - i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); - i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); - ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); - if (io->speed) - ioctl |= I365_IOCTL_WAIT (map); - if (io->flags & MAP_0WS) - ioctl |= I365_IOCTL_0WS (map); - if (io->flags & MAP_16BIT) - ioctl |= I365_IOCTL_16BIT (map); - if (io->flags & MAP_AUTOSZ) - ioctl |= I365_IOCTL_IOCS16 (map); - i365_set (s, I365_IOCTL, ioctl); - /* Turn on the window if necessary */ - if (io->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); - return 0; -} /* i365_set_io_map */ - -/*====================================================================*/ - -int i82365_init (void) -{ - u_int val; - int i; - -#ifdef CONFIG_CPC45 - if (SPD67290Init () != 0) - return 1; -#endif - if ((socket.dev = pci_find_devices (supported, 0)) < 0) { - /* Controller not found */ - return 1; - } - debug ("i82365 Device Found!\n"); - - pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys); - socket.cb_phys &= ~0xf; - -#ifdef CONFIG_CPC45 - /* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */ - socket.cb_phys += 0xfe000000; -#endif - - get_bridge_state (&socket); - set_bridge_opts (&socket); - - i = i365_get_status (&socket, &val); - -#ifdef CONFIG_CPC45 - if (i > -1) { - puts (pcic[socket.type].name); - } else { - printf ("i82365: Controller not found.\n"); - return 1; - } - if((val & SS_DETECT) != SS_DETECT){ - puts ("No card\n"); - return 1; - } -#else /* !CONFIG_CPC45 */ - if (val & SS_DETECT) { - if (val & SS_3VCARD) { - state.Vcc = state.Vpp = 33; - puts (" 3.3V card found: "); - } else if (!(val & SS_XVCARD)) { - state.Vcc = state.Vpp = 50; - puts (" 5.0V card found: "); - } else { - puts ("i82365: unsupported voltage key\n"); - state.Vcc = state.Vpp = 0; - } - } else { - /* No card inserted */ - puts ("No card\n"); - return 1; - } -#endif /* CONFIG_CPC45 */ - -#ifdef CONFIG_CPC45 - state.flags |= SS_OUTPUT_ENA; -#else - state.flags = SS_IOCARD | SS_OUTPUT_ENA; - state.csc_mask = 0; - state.io_irq = 0; -#endif - - i365_set_socket (&socket, &state); - - for (i = 500; i; i--) { - if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) - break; - udelay (1000); - } - - if (i == 0) { - /* PC Card not ready for data transfer */ - puts ("i82365 PC Card not ready for data transfer\n"); - return 1; - } - debug (" PC Card ready for data transfer: "); - - mem.map = 0; - mem.flags = MAP_ATTRIB | MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - -#ifdef CONFIG_CPC45 - mem.map = 1; - mem.flags = MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - -#else /* !CONFIG_CPC45 */ - - io.map = 0; - io.flags = MAP_AUTOSZ | MAP_ACTIVE; - io.speed = 0; - io.start = 0x0100; - io.stop = 0x010F; - i365_set_io_map (&socket, &io); - -#endif /* CONFIG_CPC45 */ - -#ifdef DEBUG - i82365_dump_regions (socket.dev); -#endif - - return 0; -} - -void i82365_exit (void) -{ - io.map = 0; - io.flags = 0; - io.speed = 0; - io.start = 0; - io.stop = 0x1; - - i365_set_io_map (&socket, &io); - - mem.map = 0; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); - -#ifdef CONFIG_CPC45 - mem.map = 1; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); -#else /* !CONFIG_CPC45 */ - socket.state.sysctl &= 0xFFFF00FF; -#endif - state.Vcc = state.Vpp = 0; - - i365_set_socket (&socket, &state); -} - -/*====================================================================== - - Debug stuff - -======================================================================*/ - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev) -{ - u_int tmp[2]; - u_int *mem = (void *) socket.cb_phys; - u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR; - u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET); - - pci_read_config_dword (dev, 0x00, tmp + 0); - pci_read_config_dword (dev, 0x80, tmp + 1); - - printf ("PCI CONF: %08X ... %08X\n", - tmp[0], tmp[1]); - printf ("PCI MEM: ... %08X ... %08X\n", - mem[0x8 / 4], mem[0x800 / 4]); - printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", - cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], - cis[0x40], cis[0x42], cis[0x44], cis[0x48]); - printf ("CIS CONF: %02X %02X %02X ...\n", - cis[0x200], cis[0x202], cis[0x204]); - printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", - ide[0], ide[1], ide[2], ide[3], - ide[4], ide[5], ide[6], ide[7]); -} -#endif /* DEBUG */ diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c index 3732583838..1b41e39158 100644 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ b/drivers/pcmcia/mpc8xx_pcmcia.c @@ -58,15 +58,9 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = /* -------------------------------------------------------------------- */ -#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU) -#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \ - | PCMCIA_SST(3) \ - | PCMCIA_SL(12)) -#else #define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \ | PCMCIA_SST(4) \ | PCMCIA_SL(9)) -#endif /* -------------------------------------------------------------------- */ @@ -211,16 +205,6 @@ static u_int m8xx_get_graycode(u_int size) #if 0 -#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) - -/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. - * SYPCR is write once only, therefore must the slowest memory be faster - * than the bus monitor or we will get a machine check due to the bus timeout. - */ -#undef PCMCIA_BMT_LIMIT -#define PCMCIA_BMT_LIMIT (6*8) -#endif - static u_int m8xx_get_speed(u_int ns, u_int is_io) { u_int reg, clocks, psst, psl, psht; diff --git a/drivers/pcmcia/rpx_pcmcia.c b/drivers/pcmcia/rpx_pcmcia.c deleted file mode 100644 index c7c425b93c..0000000000 --- a/drivers/pcmcia/rpx_pcmcia.c +++ /dev/null @@ -1,73 +0,0 @@ -/* -------------------------------------------------------------------- */ -/* RPX Boards from Embedded Planet */ -/* -------------------------------------------------------------------- */ -#include -#ifdef CONFIG_8xx -#include -#endif -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_PCMCIA) \ - && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)) - -#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - u_long reg = 0; - - switch(vcc) { - case 0: break; - case 33: reg |= BCSR1_PCVCTL4; break; - case 50: reg |= BCSR1_PCVCTL5; break; - default: return 1; - } - - switch(vpp) { - case 0: break; - case 33: - case 50: - if(vcc == vpp) - reg |= BCSR1_PCVCTL6; - else - return 1; - break; - case 120: - reg |= BCSR1_PCVCTL7; - default: return 1; - } - - /* first, turn off all power */ - *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 - | BCSR1_PCVCTL6 | BCSR1_PCVCTL7); - - /* enable new powersettings */ - *((uint *)RPX_CSR_ADDR) |= reg; - - return 0; -} - -int pcmcia_hardware_enable (int slot) -{ - return 0; /* No hardware to enable */ -} - -#if defined(CONFIG_CMD_PCMCIA) -static int pcmcia_hardware_disable(int slot) -{ - return 0; /* No hardware to disable */ -} -#endif - - -#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */ diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c index dda7d37445..45dcb54d71 100644 --- a/drivers/pcmcia/tqm8xx_pcmcia.c +++ b/drivers/pcmcia/tqm8xx_pcmcia.c @@ -20,55 +20,12 @@ #endif #if defined(CONFIG_PCMCIA) \ - && (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)) + && defined(CONFIG_TQM8xxL) -#if defined(CONFIG_VIRTLAB2) -#define PCMCIA_BOARD_MSG "Virtlab2" -#elif defined(CONFIG_TQM8xxL) +#if defined(CONFIG_TQM8xxL) #define PCMCIA_BOARD_MSG "TQM8xxL" -#elif defined(CONFIG_SVM_SC8xx) -#define PCMCIA_BOARD_MSG "SC8xx" #endif -#if defined(CONFIG_NSCU) - -static inline void power_config(int slot) {} -static inline void power_off(int slot) {} -static inline void power_on_5_0(int slot) {} -static inline void power_on_3_3(int slot) {} - -#elif defined(CONFIG_VIRTLAB2) - -static inline void power_config(int slot) {} - -static inline void power_off(int slot) -{ - volatile unsigned __iomem *addr; - addr = (volatile unsigned __iomem *)PCMCIA_CTRL; - - out_be32(addr, 0); -} - -static inline void power_on_5_0(int slot) -{ - volatile unsigned __iomem *addr; - addr = (volatile unsigned __iomem *)PCMCIA_CTRL; - - /* Enable 5V Vccout */ - out_be32(addr, 2); -} - -static inline void power_on_3_3(int slot) -{ - volatile unsigned __iomem *addr; - addr = (volatile unsigned __iomem *)PCMCIA_CTRL; - - /* Enable 3.3V Vccout */ - out_be32(addr, 1); -} - -#else - static inline void power_config(int slot) { immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; @@ -100,8 +57,6 @@ static inline void power_on_3_3(int slot) setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004); } -#endif - /* * Function to retrieve the PIPR register, used for debuging purposes. */ @@ -123,11 +78,7 @@ static inline int check_card_is_absent(int slot) return pipr & (0x18000000 >> (slot << 4)); } -#ifdef NSCU_OE_INV -#define NSCU_GCRX_CXOE 0 -#else #define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE -#endif int pcmcia_hardware_enable(int slot) { @@ -245,7 +196,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { -#ifndef CONFIG_NSCU u_long reg; uint32_t pipr = 0; @@ -298,8 +248,7 @@ done: udelay(500); debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A'); -#endif /* CONFIG_NSCU */ return 0; } -#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */ +#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */ diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig new file mode 100644 index 0000000000..f8f0239484 --- /dev/null +++ b/drivers/power/Kconfig @@ -0,0 +1,75 @@ +config AXP221_POWER + boolean "axp221 / axp223 pmic support" + depends on MACH_SUN6I || MACH_SUN8I + default y + ---help--- + Say y here to enable support for the axp221 / axp223 pmic found on most + sun6i (A31) / sun8i (A23) boards. + +config AXP221_DCDC1_VOLT + int "axp221 dcdc1 voltage" + depends on AXP221_POWER + default 3000 + ---help--- + Set the voltage (mV) to program the axp221 dcdc1 at, set to 0 to + disable dcdc1. This is typically used as generic 3.3V IO voltage for + things like GPIO-s, sdcard interfaces, etc. On most boards this is + undervolted to 3.0V to safe battery. + +config AXP221_DLDO1_VOLT + int "axp221 dldo1 voltage" + depends on AXP221_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp221 dldo1 at, set to 0 to + disable dldo1. On sun6i (A31) boards with ethernet this is often used + to power the ethernet phy. On sun8i (A23) boards this is often used to + power the wifi. + +config AXP221_DLDO4_VOLT + int "axp221 dldo4 voltage" + depends on AXP221_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp221 dldo4 at, set to 0 to + disable dldo4. + +config AXP221_ALDO1_VOLT + int "axp221 aldo1 voltage" + depends on AXP221_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp221 aldo1 at, set to 0 to + disable aldo1. On sun6i (A31) boards which have a wifi module this is + often used to power the wifi module. + +config AXP221_ALDO2_VOLT + int "axp221 aldo2 voltage" + depends on AXP221_POWER + default 0 if MACH_SUN6I + default 2500 if MACH_SUN8I + ---help--- + Set the voltage (mV) to program the axp221 aldo2 at, set to 0 to + disable aldo2. On sun6i (A31) boards this is typically unused and + should be disabled, if it is used for LPDDR2 it should be set to 1.8V. + On sun8i (A23) this is typically connected to VDD-DLL and must be set + to 2.5V. + +config AXP221_ALDO3_VOLT + int "axp221 aldo3 voltage" + depends on AXP221_POWER + default 3000 + ---help--- + Set the voltage (mV) to program the axp221 aldo3 at, set to 0 to + disable aldo3. This is typically connected to VCC-PLL and AVCC and + must be set to 3V. + +config AXP221_ELDO3_VOLT + int "axp221 eldo3 voltage" + depends on AXP221_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp221 eldo3 at, set to 0 to + disable eldo3. On some A31(s) tablets it might be used to supply + 1.2V for the SSD2828 chip (converter of parallel LCD interface + into MIPI DSI). diff --git a/drivers/power/Makefile b/drivers/power/Makefile index b2812dc65e..214565241e 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -5,38 +5,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libpower.o - -COBJS-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o -COBJS-$(CONFIG_FTPMU010_POWER) += ftpmu010.o -COBJS-$(CONFIG_TPS6586X_POWER) += tps6586x.o -COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o -COBJS-$(CONFIG_TWL6030_POWER) += twl6030.o -COBJS-$(CONFIG_PALMAS_POWER) += palmas.o - -COBJS-$(CONFIG_POWER) += power_core.o -COBJS-$(CONFIG_DIALOG_POWER) += power_dialog.o -COBJS-$(CONFIG_POWER_FSL) += power_fsl.o -COBJS-$(CONFIG_POWER_I2C) += power_i2c.o -COBJS-$(CONFIG_POWER_SPI) += power_spi.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################## +obj-$(CONFIG_AS3722_POWER) += as3722.o +obj-$(CONFIG_AXP152_POWER) += axp152.o +obj-$(CONFIG_AXP209_POWER) += axp209.o +obj-$(CONFIG_AXP221_POWER) += axp221.o +obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o +obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o +obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o +obj-$(CONFIG_TWL4030_POWER) += twl4030.o +obj-$(CONFIG_TWL6030_POWER) += twl6030.o +obj-$(CONFIG_PALMAS_POWER) += palmas.o + +obj-$(CONFIG_POWER) += power_core.o +obj-$(CONFIG_DIALOG_POWER) += power_dialog.o +obj-$(CONFIG_POWER_FSL) += power_fsl.o +obj-$(CONFIG_POWER_I2C) += power_i2c.o +obj-$(CONFIG_POWER_SPI) += power_spi.o diff --git a/drivers/power/as3722.c b/drivers/power/as3722.c new file mode 100644 index 0000000000..a60bb5f83f --- /dev/null +++ b/drivers/power/as3722.c @@ -0,0 +1,264 @@ +/* + * Copyright (C) 2014 NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define pr_fmt(fmt) "as3722: " fmt + +#include +#include +#include +#include +#include + +#include + +#define AS3722_SD_VOLTAGE(n) (0x00 + (n)) +#define AS3722_GPIO_CONTROL(n) (0x08 + (n)) +#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0) +#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0) +#define AS3722_GPIO_CONTROL_INVERT (1 << 7) +#define AS3722_LDO_VOLTAGE(n) (0x10 + (n)) +#define AS3722_GPIO_SIGNAL_OUT 0x20 +#define AS3722_SD_CONTROL 0x4d +#define AS3722_LDO_CONTROL 0x4e +#define AS3722_ASIC_ID1 0x90 +#define AS3722_DEVICE_ID 0x0c +#define AS3722_ASIC_ID2 0x91 + +static int as3722_read(struct udevice *pmic, u8 reg, u8 *value) +{ + int err; + + err = dm_i2c_read(pmic, reg, value, 1); + if (err < 0) + return err; + + return 0; +} + +static int as3722_write(struct udevice *pmic, u8 reg, u8 value) +{ + int err; + + err = dm_i2c_write(pmic, reg, &value, 1); + if (err < 0) + return err; + + return 0; +} + +static int as3722_read_id(struct udevice *pmic, u8 *id, u8 *revision) +{ + int err; + + err = as3722_read(pmic, AS3722_ASIC_ID1, id); + if (err) { + error("failed to read ID1 register: %d", err); + return err; + } + + err = as3722_read(pmic, AS3722_ASIC_ID2, revision); + if (err) { + error("failed to read ID2 register: %d", err); + return err; + } + + return 0; +} + +int as3722_sd_enable(struct udevice *pmic, unsigned int sd) +{ + u8 value; + int err; + + if (sd > 6) + return -EINVAL; + + err = as3722_read(pmic, AS3722_SD_CONTROL, &value); + if (err) { + error("failed to read SD control register: %d", err); + return err; + } + + value |= 1 << sd; + + err = as3722_write(pmic, AS3722_SD_CONTROL, value); + if (err < 0) { + error("failed to write SD control register: %d", err); + return err; + } + + return 0; +} + +int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value) +{ + int err; + + if (sd > 6) + return -EINVAL; + + err = as3722_write(pmic, AS3722_SD_VOLTAGE(sd), value); + if (err < 0) { + error("failed to write SD%u voltage register: %d", sd, err); + return err; + } + + return 0; +} + +int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo) +{ + u8 value; + int err; + + if (ldo > 11) + return -EINVAL; + + err = as3722_read(pmic, AS3722_LDO_CONTROL, &value); + if (err) { + error("failed to read LDO control register: %d", err); + return err; + } + + value |= 1 << ldo; + + err = as3722_write(pmic, AS3722_LDO_CONTROL, value); + if (err < 0) { + error("failed to write LDO control register: %d", err); + return err; + } + + return 0; +} + +int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value) +{ + int err; + + if (ldo > 11) + return -EINVAL; + + err = as3722_write(pmic, AS3722_LDO_VOLTAGE(ldo), value); + if (err < 0) { + error("failed to write LDO%u voltage register: %d", ldo, + err); + return err; + } + + return 0; +} + +int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio, + unsigned long flags) +{ + u8 value = 0; + int err; + + if (flags & AS3722_GPIO_OUTPUT_VDDH) + value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH; + + if (flags & AS3722_GPIO_INVERT) + value |= AS3722_GPIO_CONTROL_INVERT; + + err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value); + if (err) { + error("failed to configure GPIO#%u: %d", gpio, err); + return err; + } + + return 0; +} + +static int as3722_gpio_set(struct udevice *pmic, unsigned int gpio, + unsigned int level) +{ + const char *l; + u8 value; + int err; + + if (gpio > 7) + return -EINVAL; + + err = as3722_read(pmic, AS3722_GPIO_SIGNAL_OUT, &value); + if (err < 0) { + error("failed to read GPIO signal out register: %d", err); + return err; + } + + if (level == 0) { + value &= ~(1 << gpio); + l = "low"; + } else { + value |= 1 << gpio; + l = "high"; + } + + err = as3722_write(pmic, AS3722_GPIO_SIGNAL_OUT, value); + if (err) { + error("failed to set GPIO#%u %s: %d", gpio, l, err); + return err; + } + + return 0; +} + +int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio, + unsigned int level) +{ + u8 value; + int err; + + if (gpio > 7) + return -EINVAL; + + if (level == 0) + value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL; + else + value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH; + + err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value); + if (err) { + error("failed to configure GPIO#%u as output: %d", gpio, err); + return err; + } + + err = as3722_gpio_set(pmic, gpio, level); + if (err < 0) { + error("failed to set GPIO#%u high: %d", gpio, err); + return err; + } + + return 0; +} + +int as3722_init(struct udevice **devp) +{ + struct udevice *pmic; + u8 id, revision; + const unsigned int bus = 0; + const unsigned int address = 0x40; + int err; + + err = i2c_get_chip_for_busnum(bus, address, 1, &pmic); + if (err) + return err; + err = as3722_read_id(pmic, &id, &revision); + if (err < 0) { + error("failed to read ID: %d", err); + return err; + } + + if (id != AS3722_DEVICE_ID) { + error("unknown device"); + return -ENOENT; + } + + debug("AS3722 revision %#x found on I2C bus %u, address %#x\n", + revision, bus, address); + *devp = pmic; + + return 0; +} diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c new file mode 100644 index 0000000000..27c2c4c8da --- /dev/null +++ b/drivers/power/axp152.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2012 + * Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +enum axp152_reg { + AXP152_CHIP_VERSION = 0x3, + AXP152_DCDC2_VOLTAGE = 0x23, + AXP152_DCDC3_VOLTAGE = 0x27, + AXP152_DCDC4_VOLTAGE = 0x2B, + AXP152_LDO2_VOLTAGE = 0x2A, + AXP152_SHUTDOWN = 0x32, +}; + +#define AXP152_POWEROFF (1 << 7) + +static int axp152_write(enum axp152_reg reg, u8 val) +{ + return i2c_write(0x30, reg, 1, &val, 1); +} + +static int axp152_read(enum axp152_reg reg, u8 *val) +{ + return i2c_read(0x30, reg, 1, val, 1); +} + +static u8 axp152_mvolt_to_target(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int axp152_set_dcdc2(int mvolt) +{ + int rc; + u8 current, target; + + target = axp152_mvolt_to_target(mvolt, 700, 2275, 25); + + /* Do we really need to be this gentle? It has built-in voltage slope */ + while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, ¤t)) == 0 && + current != target) { + if (current < target) + current++; + else + current--; + rc = axp152_write(AXP152_DCDC2_VOLTAGE, current); + if (rc) + break; + } + return rc; +} + +int axp152_set_dcdc3(int mvolt) +{ + u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 50); + + return axp152_write(AXP152_DCDC3_VOLTAGE, target); +} + +int axp152_set_dcdc4(int mvolt) +{ + u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25); + + return axp152_write(AXP152_DCDC4_VOLTAGE, target); +} + +int axp152_set_ldo2(int mvolt) +{ + u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 100); + + return axp152_write(AXP152_LDO2_VOLTAGE, target); +} + +int axp152_init(void) +{ + u8 ver; + int rc; + + rc = axp152_read(AXP152_CHIP_VERSION, &ver); + if (rc) + return rc; + + if (ver != 0x05) + return -1; + + return 0; +} diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c new file mode 100644 index 0000000000..4565398b0b --- /dev/null +++ b/drivers/power/axp209.c @@ -0,0 +1,251 @@ +/* + * (C) Copyright 2012 + * Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +enum axp209_reg { + AXP209_POWER_STATUS = 0x00, + AXP209_CHIP_VERSION = 0x03, + AXP209_DCDC2_VOLTAGE = 0x23, + AXP209_DCDC3_VOLTAGE = 0x27, + AXP209_LDO24_VOLTAGE = 0x28, + AXP209_LDO3_VOLTAGE = 0x29, + AXP209_IRQ_ENABLE1 = 0x40, + AXP209_IRQ_ENABLE2 = 0x41, + AXP209_IRQ_ENABLE3 = 0x42, + AXP209_IRQ_ENABLE4 = 0x43, + AXP209_IRQ_ENABLE5 = 0x44, + AXP209_IRQ_STATUS5 = 0x4c, + AXP209_SHUTDOWN = 0x32, + AXP209_GPIO0_CTRL = 0x90, + AXP209_GPIO1_CTRL = 0x92, + AXP209_GPIO2_CTRL = 0x93, + AXP209_GPIO_STATE = 0x94, + AXP209_GPIO3_CTRL = 0x95, +}; + +#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0) + +#define AXP209_IRQ5_PEK_UP (1 << 6) +#define AXP209_IRQ5_PEK_DOWN (1 << 5) + +#define AXP209_POWEROFF (1 << 7) + +#define AXP209_GPIO_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP209_GPIO_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP209_GPIO_INPUT 0x02 /* Float pin */ + +/* GPIO3 is different from the others */ +#define AXP209_GPIO3_OUTPUT_LOW 0x00 /* Drive pin low, Output mode */ +#define AXP209_GPIO3_OUTPUT_HIGH 0x02 /* Float pin, Output mode */ +#define AXP209_GPIO3_INPUT 0x06 /* Float pin, Input mode */ + +static int axp209_write(enum axp209_reg reg, u8 val) +{ + return i2c_write(0x34, reg, 1, &val, 1); +} + +static int axp209_read(enum axp209_reg reg, u8 *val) +{ + return i2c_read(0x34, reg, 1, val, 1); +} + +static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int axp209_set_dcdc2(int mvolt) +{ + int rc; + u8 cfg, current; + + cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); + + /* Do we really need to be this gentle? It has built-in voltage slope */ + while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, ¤t)) == 0 && + current != cfg) { + if (current < cfg) + current++; + else + current--; + + rc = axp209_write(AXP209_DCDC2_VOLTAGE, current); + if (rc) + break; + } + + return rc; +} + +int axp209_set_dcdc3(int mvolt) +{ + u8 cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); + + return axp209_write(AXP209_DCDC3_VOLTAGE, cfg); +} + +int axp209_set_ldo2(int mvolt) +{ + int rc; + u8 cfg, reg; + + cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100); + + rc = axp209_read(AXP209_LDO24_VOLTAGE, ®); + if (rc) + return rc; + + /* LDO2 configuration is in upper 4 bits */ + reg = (reg & 0x0f) | (cfg << 4); + return axp209_write(AXP209_LDO24_VOLTAGE, reg); +} + +int axp209_set_ldo3(int mvolt) +{ + u8 cfg; + + if (mvolt == -1) + cfg = 0x80; /* determined by LDO3IN pin */ + else + cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); + + return axp209_write(AXP209_LDO3_VOLTAGE, cfg); +} + +int axp209_set_ldo4(int mvolt) +{ + int rc; + static const int vindex[] = { + 1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500, + 2700, 2800, 3000, 3100, 3200, 3300 + }; + u8 cfg, reg; + + /* Translate mvolt to register cfg value, requested <= selected */ + for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--); + + rc = axp209_read(AXP209_LDO24_VOLTAGE, ®); + if (rc) + return rc; + + /* LDO4 configuration is in lower 4 bits */ + reg = (reg & 0xf0) | (cfg << 0); + return axp209_write(AXP209_LDO24_VOLTAGE, reg); +} + +int axp209_init(void) +{ + u8 ver; + int i, rc; + + rc = axp209_read(AXP209_CHIP_VERSION, &ver); + if (rc) + return rc; + + /* Low 4 bits is chip version */ + ver &= 0x0f; + + if (ver != 0x1) + return -1; + + /* Mask all interrupts */ + for (i = AXP209_IRQ_ENABLE1; i <= AXP209_IRQ_ENABLE5; i++) { + rc = axp209_write(i, 0); + if (rc) + return rc; + } + + return 0; +} + +int axp209_poweron_by_dc(void) +{ + u8 v; + + if (axp209_read(AXP209_POWER_STATUS, &v)) + return 0; + + return (v & AXP209_POWER_STATUS_ON_BY_DC); +} + +int axp209_power_button(void) +{ + u8 v; + + if (axp209_read(AXP209_IRQ_STATUS5, &v)) + return 0; + + axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN); + + return v & AXP209_IRQ5_PEK_DOWN; +} + +static u8 axp209_get_gpio_ctrl_reg(unsigned int pin) +{ + switch (pin) { + case 0: return AXP209_GPIO0_CTRL; + case 1: return AXP209_GPIO1_CTRL; + case 2: return AXP209_GPIO2_CTRL; + case 3: return AXP209_GPIO3_CTRL; + } + return 0; +} + +int axp_gpio_direction_input(unsigned int pin) +{ + u8 reg = axp209_get_gpio_ctrl_reg(pin); + /* GPIO3 is "special" */ + u8 val = (pin == 3) ? AXP209_GPIO3_INPUT : AXP209_GPIO_INPUT; + + return axp209_write(reg, val); +} + +int axp_gpio_direction_output(unsigned int pin, unsigned int val) +{ + u8 reg = axp209_get_gpio_ctrl_reg(pin); + + if (val) { + val = (pin == 3) ? AXP209_GPIO3_OUTPUT_HIGH : + AXP209_GPIO_OUTPUT_HIGH; + } else { + val = (pin == 3) ? AXP209_GPIO3_OUTPUT_LOW : + AXP209_GPIO_OUTPUT_LOW; + } + + return axp209_write(reg, val); +} + +int axp_gpio_get_value(unsigned int pin) +{ + u8 val, mask; + int rc; + + if (pin == 3) { + rc = axp209_read(AXP209_GPIO3_CTRL, &val); + mask = 1; + } else { + rc = axp209_read(AXP209_GPIO_STATE, &val); + mask = 1 << (pin + 4); + } + if (rc) + return rc; + + return (val & mask) ? 1 : 0; +} + +int axp_gpio_set_value(unsigned int pin, unsigned int val) +{ + return axp_gpio_direction_output(pin, val); +} diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c new file mode 100644 index 0000000000..3e07f23c20 --- /dev/null +++ b/drivers/power/axp221.c @@ -0,0 +1,422 @@ +/* + * AXP221 and AXP223 driver + * + * IMPORTANT when making changes to this file check that the registers + * used are the same for the axp221 and axp223. + * + * (C) Copyright 2014 Hans de Goede + * (C) Copyright 2013 Oliver Schinagl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * The axp221 uses the p2wi bus, the axp223 is identical (for all registers + * used sofar) but uses the rsb bus. These functions abstract this. + */ +static int pmic_bus_init(void) +{ +#ifdef CONFIG_MACH_SUN6I + p2wi_init(); + return p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, + AXP221_INIT_DATA); +#else + int ret; + + ret = rsb_init(); + if (ret) + return ret; + + return rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR); +#endif +} + +static int pmic_bus_read(const u8 addr, u8 *data) +{ +#ifdef CONFIG_MACH_SUN6I + return p2wi_read(addr, data); +#else + return rsb_read(AXP223_RUNTIME_ADDR, addr, data); +#endif +} + +static int pmic_bus_write(const u8 addr, u8 data) +{ +#ifdef CONFIG_MACH_SUN6I + return p2wi_write(addr, data); +#else + return rsb_write(AXP223_RUNTIME_ADDR, addr, data); +#endif +} + +static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +static int axp221_setbits(u8 reg, u8 bits) +{ + int ret; + u8 val; + + ret = pmic_bus_read(reg, &val); + if (ret) + return ret; + + val |= bits; + return pmic_bus_write(reg, val); +} + +static int axp221_clrbits(u8 reg, u8 bits) +{ + int ret; + u8 val; + + ret = pmic_bus_read(reg, &val); + if (ret) + return ret; + + val &= ~bits; + return pmic_bus_write(reg, val); +} + +int axp221_set_dcdc1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC1_EN); + + ret = pmic_bus_write(AXP221_DCDC1_CTRL, cfg); + if (ret) + return ret; + + ret = axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DCDC1SW_EN); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC1_EN); +} + +int axp221_set_dcdc2(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC2_EN); + + ret = pmic_bus_write(AXP221_DCDC2_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC2_EN); +} + +int axp221_set_dcdc3(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC3_EN); + + ret = pmic_bus_write(AXP221_DCDC3_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC3_EN); +} + +int axp221_set_dcdc4(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC4_EN); + + ret = pmic_bus_write(AXP221_DCDC4_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC4_EN); +} + +int axp221_set_dcdc5(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC5_EN); + + ret = pmic_bus_write(AXP221_DCDC5_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_DCDC5_EN); +} + +int axp221_set_dldo1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO1_EN); + + ret = pmic_bus_write(AXP221_DLDO1_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO1_EN); +} + +int axp221_set_dldo2(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO2_EN); + + ret = pmic_bus_write(AXP221_DLDO2_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO2_EN); +} + +int axp221_set_dldo3(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO3_EN); + + ret = pmic_bus_write(AXP221_DLDO3_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO3_EN); +} + +int axp221_set_dldo4(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO4_EN); + + ret = pmic_bus_write(AXP221_DLDO4_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, + AXP221_OUTPUT_CTRL2_DLDO4_EN); +} + +int axp221_set_aldo1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_ALDO1_EN); + + ret = pmic_bus_write(AXP221_ALDO1_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_ALDO1_EN); +} + +int axp221_set_aldo2(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_ALDO2_EN); + + ret = pmic_bus_write(AXP221_ALDO2_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL1, + AXP221_OUTPUT_CTRL1_ALDO2_EN); +} + +int axp221_set_aldo3(unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL3, + AXP221_OUTPUT_CTRL3_ALDO3_EN); + + ret = pmic_bus_write(AXP221_ALDO3_CTRL, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL3, + AXP221_OUTPUT_CTRL3_ALDO3_EN); +} + +int axp221_set_eldo(int eldo_num, unsigned int mvolt) +{ + int ret; + u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); + u8 addr, bits; + + switch (eldo_num) { + case 3: + addr = AXP221_ELDO3_CTRL; + bits = AXP221_OUTPUT_CTRL2_ELDO3_EN; + break; + case 2: + addr = AXP221_ELDO2_CTRL; + bits = AXP221_OUTPUT_CTRL2_ELDO2_EN; + break; + case 1: + addr = AXP221_ELDO1_CTRL; + bits = AXP221_OUTPUT_CTRL2_ELDO1_EN; + break; + default: + return -EINVAL; + } + + if (mvolt == 0) + return axp221_clrbits(AXP221_OUTPUT_CTRL2, bits); + + ret = pmic_bus_write(addr, cfg); + if (ret) + return ret; + + return axp221_setbits(AXP221_OUTPUT_CTRL2, bits); +} + +int axp221_init(void) +{ + /* This cannot be 0 because it is used in SPL before BSS is ready */ + static int needs_init = 1; + u8 axp_chip_id; + int ret; + + if (!needs_init) + return 0; + + ret = pmic_bus_init(); + if (ret) + return ret; + + ret = pmic_bus_read(AXP221_CHIP_ID, &axp_chip_id); + if (ret) + return ret; + + if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17)) + return -ENODEV; + + needs_init = 0; + return 0; +} + +int axp221_get_sid(unsigned int *sid) +{ + u8 *dest = (u8 *)sid; + int i, ret; + + ret = axp221_init(); + if (ret) + return ret; + + ret = pmic_bus_write(AXP221_PAGE, 1); + if (ret) + return ret; + + for (i = 0; i < 16; i++) { + ret = pmic_bus_read(AXP221_SID + i, &dest[i]); + if (ret) + return ret; + } + + pmic_bus_write(AXP221_PAGE, 0); + + for (i = 0; i < 4; i++) + sid[i] = be32_to_cpu(sid[i]); + + return 0; +} + +static int axp_drivebus_setup(void) +{ + int ret; + + ret = axp221_init(); + if (ret) + return ret; + + /* Set N_VBUSEN pin to output / DRIVEBUS function */ + return axp221_clrbits(AXP221_MISC_CTRL, AXP221_MISC_CTRL_N_VBUSEN_FUNC); +} + +int axp_drivebus_enable(void) +{ + int ret; + + ret = axp_drivebus_setup(); + if (ret) + return ret; + + /* Set DRIVEBUS high */ + return axp221_setbits(AXP221_VBUS_IPSOUT, AXP221_VBUS_IPSOUT_DRIVEBUS); +} + +int axp_drivebus_disable(void) +{ + int ret; + + ret = axp_drivebus_setup(); + if (ret) + return ret; + + /* Set DRIVEBUS low */ + return axp221_clrbits(AXP221_VBUS_IPSOUT, AXP221_VBUS_IPSOUT_DRIVEBUS); +} diff --git a/drivers/power/battery/Makefile b/drivers/power/battery/Makefile index 637d1ffb3e..f864f0439d 100644 --- a/drivers/power/battery/Makefile +++ b/drivers/power/battery/Makefile @@ -5,27 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libbattery.o - -COBJS-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################## +obj-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o +obj-$(CONFIG_POWER_BATTERY_TRATS2) += bat_trats2.o diff --git a/drivers/power/battery/bat_trats.c b/drivers/power/battery/bat_trats.c index 41b179fc54..bfde692176 100644 --- a/drivers/power/battery/bat_trats.c +++ b/drivers/power/battery/bat_trats.c @@ -19,7 +19,7 @@ static int power_battery_charge(struct pmic *bat) struct battery *battery = p_bat->bat; int k; - if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450)) + if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) return -1; for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) && @@ -42,7 +42,7 @@ static int power_battery_charge(struct pmic *bat) } } exit: - bat->chrg->chrg_state(p_bat->chrg, CHARGER_DISABLE, 0); + bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0); return 0; } diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c new file mode 100644 index 0000000000..57221adf81 --- /dev/null +++ b/drivers/power/battery/bat_trats2.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Piotr Wilczek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static struct battery battery_trats; + +static int power_battery_charge(struct pmic *bat) +{ + struct power_battery *p_bat = bat->pbat; + + if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) + return -1; + + return 0; +} + +static int power_battery_init_trats2(struct pmic *bat_, + struct pmic *fg_, + struct pmic *chrg_, + struct pmic *muic_) +{ + bat_->pbat->fg = fg_; + bat_->pbat->chrg = chrg_; + bat_->pbat->muic = muic_; + + bat_->fg = fg_->fg; + bat_->chrg = chrg_->chrg; + bat_->chrg->chrg_type = muic_->chrg->chrg_type; + return 0; +} + +static struct power_battery power_bat_trats2 = { + .bat = &battery_trats, + .battery_init = power_battery_init_trats2, + .battery_charge = power_battery_charge, +}; + +int power_bat_init(unsigned char bus) +{ + static const char name[] = "BAT_TRATS2"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + debug("Board BAT init\n"); + + p->interface = PMIC_NONE; + p->name = name; + p->bus = bus; + + p->pbat = &power_bat_trats2; + return 0; +} diff --git a/drivers/power/fuel_gauge/Makefile b/drivers/power/fuel_gauge/Makefile index 5166a30f62..3b349f939a 100644 --- a/drivers/power/fuel_gauge/Makefile +++ b/drivers/power/fuel_gauge/Makefile @@ -5,27 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libfuel_gauge.o - -COBJS-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################## +obj-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o diff --git a/drivers/power/fuel_gauge/fg_max17042.c b/drivers/power/fuel_gauge/fg_max17042.c index c285747f34..154ca6a695 100644 --- a/drivers/power/fuel_gauge/fg_max17042.c +++ b/drivers/power/fuel_gauge/fg_max17042.c @@ -20,21 +20,30 @@ static int fg_write_regs(struct pmic *p, u8 addr, u16 *data, int num) int ret = 0; int i; - for (i = 0; i < num; i++, addr++) - ret |= pmic_reg_write(p, addr, *(data + i)); + for (i = 0; i < num; i++, addr++) { + ret = pmic_reg_write(p, addr, *(data + i)); + if (ret) + return ret; + } - return ret; + return 0; } static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num) { + unsigned int dat; int ret = 0; int i; - for (i = 0; i < num; i++, addr++) - ret |= pmic_reg_read(p, addr, (u32 *) (data + i)); + for (i = 0; i < num; i++, addr++) { + ret = pmic_reg_read(p, addr, &dat); + if (ret) + return ret; - return ret; + *(data + i) = (u16)dat; + } + + return 0; } static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data) @@ -57,9 +66,13 @@ static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data) static void por_fuelgauge_init(struct pmic *p) { u16 r_data0[16], r_data1[16], r_data2[16]; - u32 rewrite_count = 5, i = 0; - unsigned int val; - int ret = 0; + u32 rewrite_count = 5; + u32 check_count; + u32 lock_count; + u32 i = 0; + u32 val; + s32 ret = 0; + char *status_msg; /* Delay 500 ms */ mdelay(500); @@ -67,29 +80,55 @@ static void por_fuelgauge_init(struct pmic *p) pmic_reg_write(p, MAX17042_CONFIG, 0x2310); rewrite_model: + check_count = 5; + lock_count = 5; + + if (!rewrite_count--) { + status_msg = "init failed!"; + goto error; + } + /* Unlock Model Access */ pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_UNLOCK1); pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_UNLOCK2); /* Write/Read/Verify the Custom Model */ - ret |= fg_write_regs(p, MAX17042_MODEL1, cell_character0, + ret = fg_write_regs(p, MAX17042_MODEL1, cell_character0, ARRAY_SIZE(cell_character0)); - ret |= fg_write_regs(p, MAX17042_MODEL2, cell_character1, + if (ret) + goto rewrite_model; + + ret = fg_write_regs(p, MAX17042_MODEL2, cell_character1, ARRAY_SIZE(cell_character1)); - ret |= fg_write_regs(p, MAX17042_MODEL3, cell_character2, + if (ret) + goto rewrite_model; + + ret = fg_write_regs(p, MAX17042_MODEL3, cell_character2, ARRAY_SIZE(cell_character2)); + if (ret) + goto rewrite_model; - if (ret) { - printf("%s: Cell parameters write failed!\n", __func__); - return; +check_model: + if (!check_count--) { + if (rewrite_count) + goto rewrite_model; + else + status_msg = "check failed!"; + + goto error; } - ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); + if (ret) + goto check_model; + + ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); + if (ret) + goto check_model; + ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); if (ret) - printf("%s: Cell parameters read failed!\n", __func__); + goto check_model; for (i = 0; i < 16; i++) { if ((cell_character0[i] != r_data0[i]) @@ -98,29 +137,37 @@ rewrite_model: goto rewrite_model; } +lock_model: + if (!lock_count--) { + if (rewrite_count) + goto rewrite_model; + else + status_msg = "lock failed!"; + + goto error; + } + /* Lock model access */ pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_LOCK1); pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_LOCK2); /* Verify the model access is locked */ - ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); + if (ret) + goto lock_model; - if (ret) { - printf("%s: Cell parameters read failed!\n", __func__); - return; - } + ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); + if (ret) + goto lock_model; + + ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + if (ret) + goto lock_model; for (i = 0; i < ARRAY_SIZE(r_data0); i++) { /* Check if model locked */ - if (r_data0[i] || r_data1[i] || r_data2[i]) { - /* Rewrite model data - prevent from endless loop */ - if (rewrite_count--) { - puts("FG - Lock model access failed!\n"); - goto rewrite_model; - } - } + if (r_data0[i] || r_data1[i] || r_data2[i]) + goto lock_model; } /* Write Custom Parameters */ @@ -137,6 +184,11 @@ rewrite_model: /* Delay at least 350 ms */ mdelay(350); + + status_msg = "OK!"; +error: + debug("%s: model init status: %s\n", p->name, status_msg); + return; } static int power_update_battery(struct pmic *p, struct pmic *bat) @@ -178,7 +230,7 @@ static int power_check_battery(struct pmic *p, struct pmic *bat) ret |= pmic_reg_read(p, MAX17042_STATUS, &val); debug("fg status: 0x%x\n", val); - if (val == MAX17042_POR) + if (val & MAX17042_POR) por_fuelgauge_init(p); ret |= pmic_reg_read(p, MAX17042_VERSION, &val); diff --git a/drivers/power/mfd/Makefile b/drivers/power/mfd/Makefile new file mode 100644 index 0000000000..43afe842ae --- /dev/null +++ b/drivers/power/mfd/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2013 Samsung Electronics +# Piotr Wilczek +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o +obj-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o +obj-$(CONFIG_POWER_FG_MAX77693) += fg_max77693.o diff --git a/drivers/power/mfd/fg_max77693.c b/drivers/power/mfd/fg_max77693.c new file mode 100644 index 0000000000..4519fed497 --- /dev/null +++ b/drivers/power/mfd/fg_max77693.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Piotr Wilczek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int max77693_get_vcell(u32 *vcell) +{ + u16 value; + u8 ret; + + ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VCELL, 1, + (u8 *)&value, 2); + if (ret) + return ret; + + *vcell = (u32)(value >> 3); + *vcell = *vcell * 625; + + return 0; +} + +static int max77693_get_soc(u32 *soc) +{ + u16 value; + u8 ret; + + ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VFSOC, 1, + (u8 *)&value, 2); + if (ret) + return ret; + + *soc = (u32)(value >> 8); + + return 0; +} + +static int power_update_battery(struct pmic *p, struct pmic *bat) +{ + struct power_battery *pb = bat->pbat; + int ret; + + if (pmic_probe(p)) { + puts("Can't find max77693 fuel gauge\n"); + return -1; + } + + ret = max77693_get_soc(&pb->bat->state_of_chrg); + if (ret) + return ret; + + max77693_get_vcell(&pb->bat->voltage_uV); + if (ret) + return ret; + + return 0; +} + +static int power_check_battery(struct pmic *p, struct pmic *bat) +{ + struct power_battery *pb = bat->pbat; + unsigned int val; + int ret = 0; + + if (pmic_probe(p)) { + puts("Can't find max77693 fuel gauge\n"); + return -1; + } + + ret = pmic_reg_read(p, MAX77693_STATUS, &val); + if (ret) + return ret; + debug("fg status: 0x%x\n", val); + + ret = pmic_reg_read(p, MAX77693_VERSION, &pb->bat->version); + if (ret) + return ret; + + ret = power_update_battery(p, bat); + if (ret) + return ret; + debug("fg ver: 0x%x\n", pb->bat->version); + printf("BAT: state_of_charge(SOC):%d%%\n", + pb->bat->state_of_chrg); + + printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n", + pb->bat->voltage_uV / 1000000, + pb->bat->voltage_uV % 1000000, + pb->bat->capacity); + + if (pb->bat->voltage_uV > 3850000) + pb->bat->state = EXT_SOURCE; + else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5) + pb->bat->state = CHARGE; + else + pb->bat->state = NORMAL; + + return 0; +} + +static struct power_fg power_fg_ops = { + .fg_battery_check = power_check_battery, + .fg_battery_update = power_update_battery, +}; + +int power_fg_init(unsigned char bus) +{ + static const char name[] = "MAX77693_FG"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + debug("Board Fuel Gauge init\n"); + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = FG_NUM_OF_REGS; + p->hw.i2c.addr = MAX77693_FUEL_I2C_ADDR; + p->hw.i2c.tx_num = 2; + p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG; + p->bus = bus; + + p->fg = &power_fg_ops; + + return 0; +} diff --git a/drivers/power/mfd/muic_max77693.c b/drivers/power/mfd/muic_max77693.c new file mode 100644 index 0000000000..e71012de1f --- /dev/null +++ b/drivers/power/mfd/muic_max77693.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Piotr Wilczek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static int power_chrg_get_type(struct pmic *p) +{ + unsigned int val; + unsigned int charge_type, charger; + + /* if probe failed, return cable none */ + if (pmic_probe(p)) + return CHARGER_NO; + + pmic_reg_read(p, MAX77693_MUIC_STATUS2, &val); + + charge_type = val & MAX77693_MUIC_CHG_MASK; + + switch (charge_type) { + case MAX77693_MUIC_CHG_NO: + charger = CHARGER_NO; + break; + case MAX77693_MUIC_CHG_USB: + case MAX77693_MUIC_CHG_USB_D: + charger = CHARGER_USB; + break; + case MAX77693_MUIC_CHG_TA: + case MAX77693_MUIC_CHG_TA_1A: + charger = CHARGER_TA; + break; + case MAX77693_MUIC_CHG_TA_500: + charger = CHARGER_TA_500; + break; + default: + charger = CHARGER_UNKNOWN; + break; + } + + return charger; +} + +static struct power_chrg power_chrg_muic_ops = { + .chrg_type = power_chrg_get_type, +}; + +int power_muic_init(unsigned int bus) +{ + static const char name[] = "MAX77693_MUIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + debug("Board Micro USB Interface Controller init\n"); + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = MUIC_NUM_OF_REGS; + p->hw.i2c.addr = MAX77693_MUIC_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + p->chrg = &power_chrg_muic_ops; + + return 0; +} diff --git a/drivers/power/mfd/pmic_max77693.c b/drivers/power/mfd/pmic_max77693.c new file mode 100644 index 0000000000..6b28e28b3f --- /dev/null +++ b/drivers/power/mfd/pmic_max77693.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Piotr Wilczek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static int max77693_charger_state(struct pmic *p, int state, int current) +{ + unsigned int val; + + if (pmic_probe(p)) + return -1; + + /* unlock write capability */ + val = MAX77693_CHG_UNLOCK; + pmic_reg_write(p, MAX77693_CHG_CNFG_06, val); + + if (state == PMIC_CHARGER_DISABLE) { + puts("Disable the charger.\n"); + pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val); + val &= ~0x01; + pmic_reg_write(p, MAX77693_CHG_CNFG_00, val); + return -1; + } + + if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) { + printf("%s: Wrong charge current: %d [mA]\n", + __func__, current); + return -1; + } + + /* set charging current */ + pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val); + val &= ~MAX77693_CHG_CC; + val |= current * 10 / 333; /* 0.1A/3 steps */ + pmic_reg_write(p, MAX77693_CHG_CNFG_02, val); + + /* enable charging */ + val = MAX77693_CHG_MODE_ON; + pmic_reg_write(p, MAX77693_CHG_CNFG_00, val); + + /* check charging current */ + pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val); + val &= 0x3f; + printf("Enable the charger @ %d [mA]\n", val * 333 / 10); + + return 0; +} + +static int max77693_charger_bat_present(struct pmic *p) +{ + unsigned int val; + + if (pmic_probe(p)) + return -1; + + pmic_reg_read(p, MAX77693_CHG_INT_OK, &val); + + return !(val & MAX77693_CHG_DETBAT); +} + +static struct power_chrg power_chrg_pmic_ops = { + .chrg_bat_present = max77693_charger_bat_present, + .chrg_state = max77693_charger_state, +}; + +int pmic_init_max77693(unsigned char bus) +{ + static const char name[] = "MAX77693_PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + debug("Board PMIC init\n"); + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = PMIC_NUM_OF_REGS; + p->hw.i2c.addr = MAX77693_PMIC_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + p->chrg = &power_chrg_pmic_ops; + + return 0; +} diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index c7b0cbe8b5..6430fe004d 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -27,7 +27,7 @@ int palmas_mmc1_poweron_ldo(void) { u8 val = 0; -#if defined(CONFIG_DRA7XX) +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) /* * Currently valid for the dra7xx_evm board: * Set TPS659038 LDO1 to 3.0 V @@ -127,6 +127,21 @@ int twl603x_audio_power(u8 on) } #endif +#ifdef CONFIG_PALMAS_USB_SS_PWR +/** + * @brief palmas_enable_ss_ldo - Configure EVM board specific configurations + * for the USB Super speed SMPS10 regulator. + * + * @return 0 + */ +int palmas_enable_ss_ldo(void) +{ + /* Enable smps10 regulator */ + return palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS10_CTRL, + SMPS10_MODE_ACTIVE_D); +} +#endif + /* * Enable/disable back-up battery (or super cap) charging on TWL6035/37. * Please use defined BB_xxx values. diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index f054470552..985cfdb901 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -5,30 +5,15 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libpmic.o - -COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o -COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o -COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o -COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################## +obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o +obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o +obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o +obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o +obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o +obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o +obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o +obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o +obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o +obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o +obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_ltc3676.c b/drivers/power/pmic/pmic_ltc3676.c new file mode 100644 index 0000000000..9b874cb07c --- /dev/null +++ b/drivers/power/pmic/pmic_ltc3676.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int power_ltc3676_init(unsigned char bus) +{ + static const char name[] = "LTC3676_PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = LTC3676_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_LTC3676_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c index 7208e5b679..95b1a57ca2 100644 --- a/drivers/power/pmic/pmic_max77686.c +++ b/drivers/power/pmic/pmic_max77686.c @@ -14,10 +14,252 @@ DECLARE_GLOBAL_DATA_PTR; +static const char max77686_buck_addr[] = { + 0xff, 0x10, 0x12, 0x1c, 0x26, 0x30, 0x32, 0x34, 0x36, 0x38 +}; + +static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV) +{ + unsigned int hex = 0; + + switch (ldo) { + case 1: + case 2: + case 6: + case 7: + case 8: + case 15: + hex = (uV - 800000) / 25000; + break; + default: + hex = (uV - 800000) / 50000; + } + + if (hex >= 0 && hex <= MAX77686_LDO_VOLT_MAX_HEX) + return hex; + + debug("%s: %ld is wrong voltage value for LDO%d\n", __func__, uV, ldo); + return 0; +} + +static int max77686_buck_volt2hex(int buck, ulong uV) +{ + int hex = 0; + + if (buck < 5 || buck > 9) { + debug("%s: buck %d is not supported\n", __func__, buck); + return -EINVAL; + } + + hex = (uV - 750000) / 50000; + + if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX) + return hex; + + debug("%s: %ld is wrong voltage value for BUCK%d\n", + __func__, uV, buck); + return -EINVAL; +} + +int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV) +{ + unsigned int val, ret, hex, adr; + + if (ldo < 1 || ldo > 26) { + printf("%s: %d is wrong ldo number\n", __func__, ldo); + return -1; + } + + adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1; + hex = max77686_ldo_volt2hex(ldo, uV); + + if (!hex) + return -1; + + ret = pmic_reg_read(p, adr, &val); + if (ret) + return ret; + + val &= ~MAX77686_LDO_VOLT_MASK; + val |= hex; + ret |= pmic_reg_write(p, adr, val); + + return ret; +} + +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV) +{ + unsigned int val, adr; + int hex, ret; + + if (buck < 5 || buck > 9) { + printf("%s: %d is an unsupported bucket number\n", + __func__, buck); + return -EINVAL; + } + + adr = max77686_buck_addr[buck] + 1; + hex = max77686_buck_volt2hex(buck, uV); + + if (hex < 0) + return hex; + + ret = pmic_reg_read(p, adr, &val); + if (ret) + return ret; + + val &= ~MAX77686_BUCK_VOLT_MASK; + ret |= pmic_reg_write(p, adr, val | hex); + + return ret; +} + +int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode) +{ + unsigned int val, ret, adr, mode; + + if (ldo < 1 || 26 < ldo) { + printf("%s: %d is wrong ldo number\n", __func__, ldo); + return -1; + } + + adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1; + + /* mode */ + switch (opmode) { + case OPMODE_OFF: + mode = MAX77686_LDO_MODE_OFF; + break; + case OPMODE_STANDBY: + switch (ldo) { + case 2: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 14: + case 15: + case 16: + mode = MAX77686_LDO_MODE_STANDBY; + break; + default: + mode = 0xff; + } + break; + case OPMODE_LPM: + mode = MAX77686_LDO_MODE_LPM; + break; + case OPMODE_ON: + mode = MAX77686_LDO_MODE_ON; + break; + default: + mode = 0xff; + } + + if (mode == 0xff) { + printf("%s: %d is not supported on LDO%d\n", + __func__, opmode, ldo); + return -1; + } + + ret = pmic_reg_read(p, adr, &val); + if (ret) + return ret; + + val &= ~MAX77686_LDO_MODE_MASK; + val |= mode; + ret |= pmic_reg_write(p, adr, val); + + return ret; +} + +int max77686_set_buck_mode(struct pmic *p, int buck, char opmode) +{ + unsigned int val, ret, mask, adr, size, mode, mode_shift; + + size = ARRAY_SIZE(max77686_buck_addr); + if (buck >= size) { + printf("%s: %d is wrong buck number\n", __func__, buck); + return -1; + } + + adr = max77686_buck_addr[buck]; + + /* mask */ + switch (buck) { + case 2: + case 3: + case 4: + mode_shift = MAX77686_BUCK_MODE_SHIFT_2; + break; + default: + mode_shift = MAX77686_BUCK_MODE_SHIFT_1; + } + + mask = MAX77686_BUCK_MODE_MASK << mode_shift; + + /* mode */ + switch (opmode) { + case OPMODE_OFF: + mode = MAX77686_BUCK_MODE_OFF << mode_shift; + break; + case OPMODE_STANDBY: + switch (buck) { + case 1: + case 2: + case 3: + case 4: + mode = MAX77686_BUCK_MODE_STANDBY << mode_shift; + break; + default: + mode = 0xff; + } + break; + case OPMODE_LPM: + switch (buck) { + case 2: + case 3: + case 4: + mode = MAX77686_BUCK_MODE_LPM << mode_shift; + break; + default: + mode = 0xff; + } + break; + case OPMODE_ON: + mode = MAX77686_BUCK_MODE_ON << mode_shift; + break; + default: + mode = 0xff; + } + + if (mode == 0xff) { + printf("%s: %d is not supported on BUCK%d\n", + __func__, opmode, buck); + return -1; + } + + ret = pmic_reg_read(p, adr, &val); + if (ret) + return ret; + + val &= ~mask; + val |= mode; + ret |= pmic_reg_write(p, adr, val); + + return ret; +} + int pmic_init(unsigned char bus) { static const char name[] = "MAX77686_PMIC"; struct pmic *p = pmic_alloc(); +#ifdef CONFIG_OF_CONTROL + const void *blob = gd->fdt_blob; + int node, parent, tmp; +#endif if (!p) { printf("%s: POWER allocation error!\n", __func__); @@ -25,9 +267,6 @@ int pmic_init(unsigned char bus) } #ifdef CONFIG_OF_CONTROL - const void *blob = gd->fdt_blob; - int node, parent; - node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_MAX77686_PMIC); if (node < 0) { debug("PMIC: No node for PMIC Chip in device tree\n"); @@ -41,11 +280,13 @@ int pmic_init(unsigned char bus) return -1; } - p->bus = i2c_get_bus_num_fdt(parent); - if (p->bus < 0) { + /* tmp since p->bus is unsigned */ + tmp = i2c_get_bus_num_fdt(parent); + if (tmp < 0) { debug("%s: Cannot find I2C bus\n", __func__); return -1; } + p->bus = tmp; p->hw.i2c.addr = fdtdec_get_int(blob, node, "reg", 9); #else p->bus = bus; diff --git a/drivers/power/pmic/pmic_max8997.c b/drivers/power/pmic/pmic_max8997.c index ba01692327..a36a9a08bf 100644 --- a/drivers/power/pmic/pmic_max8997.c +++ b/drivers/power/pmic/pmic_max8997.c @@ -35,7 +35,7 @@ static int pmic_charger_state(struct pmic *p, int state, int current) if (pmic_probe(p)) return -1; - if (state == CHARGER_DISABLE) { + if (state == PMIC_CHARGER_DISABLE) { puts("Disable the charger.\n"); pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val); val &= ~(MBCHOSTEN | VCHGR_FC); diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c new file mode 100644 index 0000000000..22a04c02a3 --- /dev/null +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int power_pfuze100_init(unsigned char bus) +{ + static const char name[] = "PFUZE100"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = PMIC_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c new file mode 100644 index 0000000000..2123685a6a --- /dev/null +++ b/drivers/power/pmic/pmic_tps62362.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com + * Author: Felipe Balbi + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/** + * tps62362_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @reg: Register address to write to + * @volt_sel: Voltage register value to write + * @return: 0 on success, 1 on failure + */ +int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel) +{ + if (reg > TPS62362_NUM_REGS) + return 1; + + return i2c_write(TPS62362_I2C_ADDR, reg, 1, &volt_sel, 1); +} + +int power_tps62362_init(unsigned char bus) +{ + static const char name[] = "TPS62362"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = TPS62362_NUM_REGS; + p->hw.i2c.addr = TPS62362_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/power/pmic/pmic_tps65090.c b/drivers/power/pmic/pmic_tps65090.c new file mode 100644 index 0000000000..337903acec --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090.c @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_NAME "TPS65090_PMIC" + +/* TPS65090 register addresses */ +enum { + REG_IRQ1 = 0, + REG_CG_CTRL0 = 4, + REG_CG_STATUS1 = 0xa, + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + IRQ1_VBATG = 1 << 3, + CG_CTRL0_ENC_MASK = 0x01, + + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -EINVAL if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -EINVAL; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param pmic pmic structure for the tps65090 + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return -EIO if we got a comms error, -EAGAIN if the FET failed to + * change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(struct pmic *pmic, int fet_id, bool set) +{ + int retry; + u32 reg, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (pmic_reg_write(pmic, REG_FET1_CTRL + fet_id - 1, value)) + return -EIO; + + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®)) + return -EIO; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return -EAGAIN; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + struct pmic *pmic; + ulong start; + int loops; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + start = get_timer(0); + for (loops = 0;; loops++) { + ret = tps65090_fet_set(pmic, fet_id, true); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(pmic, fet_id, false); + } + + if (ret) + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + else if (loops) + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == -EAGAIN) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + struct pmic *pmic; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + ret = tps65090_fet_set(pmic, fet_id, false); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + struct pmic *pmic; + u32 reg; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -ENODEV; + ret = pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -EIO; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_get_charging(void) +{ + struct pmic *pmic; + u32 val; + int ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val); + if (ret) + return ret; + + return !!(val & CG_CTRL0_ENC_MASK); +} + +static int tps65090_charger_state(struct pmic *pmic, int state, + int current) +{ + u32 val; + int ret; + + ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val); + if (!ret) { + if (state == PMIC_CHARGER_ENABLE) + val |= CG_CTRL0_ENC_MASK; + else + val &= ~CG_CTRL0_ENC_MASK; + ret = pmic_reg_write(pmic, REG_CG_CTRL0, val); + } + if (ret) { + debug("%s: Failed to read/write register\n", __func__); + return ret; + } + + return 0; +} + +int tps65090_get_status(void) +{ + struct pmic *pmic; + u32 val; + int ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + ret = pmic_reg_read(pmic, REG_CG_STATUS1, &val); + if (ret) + return ret; + + return val; +} + +static int tps65090_charger_bat_present(struct pmic *pmic) +{ + u32 val; + int ret; + + ret = pmic_reg_read(pmic, REG_IRQ1, &val); + if (ret) + return ret; + + return !!(val & IRQ1_VBATG); +} + +static struct power_chrg power_chrg_pmic_ops = { + .chrg_bat_present = tps65090_charger_bat_present, + .chrg_state = tps65090_charger_state, +}; + +int tps65090_init(void) +{ + struct pmic *p; + int bus; + int addr; + const void *blob = gd->fdt_blob; + int node, parent; + + node = fdtdec_next_compatible(blob, 0, COMPAT_TI_TPS65090); + if (node < 0) { + debug("PMIC: No node for PMIC Chip in device tree\n"); + debug("node = %d\n", node); + return -ENODEV; + } + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("%s: Cannot find node parent\n", __func__); + return -EINVAL; + } + + bus = i2c_get_bus_num_fdt(parent); + if (bus < 0) { + debug("%s: Cannot find I2C bus\n", __func__); + return -ENOENT; + } + addr = fdtdec_get_int(blob, node, "reg", TPS65090_I2C_ADDR); + p = pmic_alloc(); + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = TPS65090_NAME; + p->bus = bus; + p->interface = PMIC_I2C; + p->number_of_regs = TPS65090_NUM_REGS; + p->hw.i2c.addr = addr; + p->hw.i2c.tx_num = 1; + p->chrg = &power_chrg_pmic_ops; + + puts("TPS65090 PMIC init\n"); + + return 0; +} diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c new file mode 100644 index 0000000000..ac0d44fec8 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_ADDR 0x48 + +static struct tps65090 { + struct cros_ec_dev *dev; /* The CROS_EC device */ +} config; + +/* TPS65090 register addresses */ +enum { + REG_IRQ1 = 0, + REG_CG_CTRL0 = 4, + REG_CG_STATUS1 = 0xa, + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + IRQ1_VBATG = 1 << 3, + CG_CTRL0_ENC_MASK = 0x01, + + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * tps65090_read - read a byte from tps6090 + * + * @param reg The register address to read from. + * @param val We'll return value value read here. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_read(u32 reg, u8 *val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + val, 1, true); +} + +/** + * tps65090_write - write a byte to tps6090 + * + * @param reg The register address to write to. + * @param val The value to write. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_write(u32 reg, u8 val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + &val, 1, false); +} + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -EINVAL if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -EINVAL; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return -EIO if we got a comms error, -EAGAIN if the FET failed to + * change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(int fet_id, bool set) +{ + int retry; + u8 reg, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value)) + return -EIO; + + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®)) + return -EIO; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return -EAGAIN; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + ulong start; + int loops; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + start = get_timer(0); + for (loops = 0;; loops++) { + ret = tps65090_fet_set(fet_id, true); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(fet_id, false); + } + + if (ret) { + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } else if (loops) { + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == -EAGAIN) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + ret = tps65090_fet_set(fet_id, false); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + u8 reg = 0; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -EIO; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_init(void) +{ + puts("TPS65090 PMIC EC init\n"); + + config.dev = board_get_cros_ec_dev(); + if (!config.dev) { + debug("%s: no cros_ec device: cannot init tps65090\n", + __func__); + return -ENODEV; + } + + return 0; +} diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c new file mode 100644 index 0000000000..36e9024bf8 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65217.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/** + * tps65217_reg_read() - Generic function that can read a TPS65217 register + * @src_reg: Source register address + * @src_val: Address of destination variable + * @return: 0 for success, not 0 on failure. + */ +int tps65217_reg_read(uchar src_reg, uchar *src_val) +{ + return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1); +} + +/** + * tps65217_reg_write() - Generic function that can write a TPS65217 PMIC + * register or bit field regardless of protection + * level. + * + * @prot_level: Register password protection. Use + * TPS65217_PROT_LEVEL_NONE, + * TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2 + * @dest_reg: Register address to write. + * @dest_val: Value to write. + * @mask: Bit mask (8 bits) to be applied. Function will only + * change bits that are set in the bit mask. + * + * @return: 0 for success, not 0 on failure, as per the i2c API + */ +int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask) +{ + uchar read_val; + uchar xor_reg; + int ret; + + /* + * If we are affecting only a bit field, read dest_reg and apply the + * mask + */ + if (mask != TPS65217_MASK_ALL_BITS) { + ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK; + ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + } + + ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + + if (prot_level == TPS65217_PROT_LEVEL_2) { + ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + + ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * tps65217_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @dc_cntrl_reg: DC voltage control register to change. + * @volt_sel: New value for the voltage register + * @return: 0 for success, not 0 on failure. + */ +int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) +{ + if ((dc_cntrl_reg != TPS65217_DEFDCDC1) && + (dc_cntrl_reg != TPS65217_DEFDCDC2) && + (dc_cntrl_reg != TPS65217_DEFDCDC3)) + return 1; + + /* set voltage level */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel, + TPS65217_MASK_ALL_BITS)) + return 1; + + /* set GO bit to initiate voltage transition */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW, + TPS65217_DCDC_GO, TPS65217_DCDC_GO)) + return 1; + + return 0; +} diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c new file mode 100644 index 0000000000..dbc7a73a72 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65218.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/** + * tps65218_reg_write() - Generic function that can write a TPS65218 PMIC + * register or bit field regardless of protection + * level. + * + * @prot_level: Register password protection. Use + * TPS65218_PROT_LEVEL_NONE, + * TPS65218_PROT_LEVEL_1 or TPS65218_PROT_LEVEL_2 + * @dest_reg: Register address to write. + * @dest_val: Value to write. + * @mask: Bit mask (8 bits) to be applied. Function will only + * change bits that are set in the bit mask. + * + * @return: 0 for success, not 0 on failure, as per the i2c API + */ +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask) +{ + uchar read_val; + uchar xor_reg; + int ret; + + /* + * If we are affecting only a bit field, read dest_reg and apply the + * mask + */ + if (mask != TPS65218_MASK_ALL_BITS) { + ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ TPS65218_PASSWORD_UNLOCK; + ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + } + + ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + + if (prot_level == TPS65218_PROT_LEVEL_2) { + ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + + ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * tps65218_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @dc_cntrl_reg: DC voltage control register to change. + * @volt_sel: New value for the voltage register + * @return: 0 for success, not 0 on failure. + */ +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) +{ + if ((dc_cntrl_reg != TPS65218_DCDC1) && + (dc_cntrl_reg != TPS65218_DCDC2)) + return 1; + + /* set voltage level */ + if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel, + TPS65218_MASK_ALL_BITS)) + return 1; + + /* set GO bit to initiate voltage transition */ + if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_SLEW, + TPS65218_DCDC_GO, TPS65218_DCDC_GO)) + return 1; + + return 0; +} + +int power_tps65218_init(unsigned char bus) +{ + static const char name[] = "TPS65218_PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = TPS65218_PMIC_NUM_OF_REGS; + p->hw.i2c.addr = TPS65218_CHIP_PM; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c new file mode 100644 index 0000000000..7ee1160e0d --- /dev/null +++ b/drivers/power/pmic/pmic_tps65910.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C + * interface. + * @return: 0 on success, not 0 on failure + */ +int tps65910_set_i2c_control(void) +{ + int ret; + uchar buf; + + /* VDD1/2 voltage selection register access by control i/f */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, + &buf, 1); + + if (ret) + return ret; + + buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, + &buf, 1); +} + +/* + * tps65910_voltage_update() - Voltage switching for MPU frequency switching. + * @module: mpu - 0, core - 1 + * @vddx_op_vol_sel: vdd voltage to set + * @return: 0 on success, not 0 on failure + */ +int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf; + unsigned int reg_offset; + int ret; + + if (module == MPU) + reg_offset = TPS65910_VDD1_OP_REG; + else + reg_offset = TPS65910_VDD2_OP_REG; + + /* Select VDDx OP */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + buf &= ~TPS65910_OP_REG_CMD_MASK; + + ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + /* Configure VDDx OP Voltage */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + buf &= ~TPS65910_OP_REG_SEL_MASK; + buf |= vddx_op_vol_sel; + + ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel) + return 1; + + return 0; +} diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c index d79971ba88..fe1f316021 100644 --- a/drivers/power/power_core.c +++ b/drivers/power/power_core.c @@ -140,6 +140,9 @@ int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_SUCCESS; } + if (argc < 3) + return CMD_RET_USAGE; + name = argv[1]; cmd = argv[2]; @@ -184,18 +187,21 @@ int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc < 4) return CMD_RET_USAGE; + if (!p->pbat) { + printf("%s is not a battery\n", p->name); + return CMD_RET_FAILURE; + } + if (strcmp(argv[3], "state") == 0) p->fg->fg_battery_check(p->pbat->fg, p); if (strcmp(argv[3], "charge") == 0) { - if (p->pbat) { - printf("BAT: %s charging (ctrl+c to break)\n", - p->name); - if (p->low_power_mode) - p->low_power_mode(); - if (p->pbat->battery_charge) - p->pbat->battery_charge(p); - } + printf("BAT: %s charging (ctrl+c to break)\n", + p->name); + if (p->low_power_mode) + p->low_power_mode(); + if (p->pbat->battery_charge) + p->pbat->battery_charge(p); } return CMD_RET_SUCCESS; diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index ed778f333e..a64161b243 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -11,9 +11,9 @@ #include #include -#if defined(CONFIG_PMIC_FSL_MC13892) +#if defined(CONFIG_POWER_FSL_MC13892) #define FSL_PMIC_I2C_LENGTH 3 -#elif defined(CONFIG_PMIC_FSL_MC34704) +#elif defined(CONFIG_POWER_FSL_MC34704) #define FSL_PMIC_I2C_LENGTH 1 #endif @@ -36,10 +36,10 @@ int pmic_init(unsigned char bus) p->name = name; p->number_of_regs = PMIC_NUM_OF_REGS; + p->bus = bus; #if defined(CONFIG_POWER_SPI) p->interface = PMIC_SPI; - p->bus = CONFIG_FSL_PMIC_BUS; p->hw.spi.cs = CONFIG_FSL_PMIC_CS; p->hw.spi.clk = CONFIG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; @@ -50,9 +50,8 @@ int pmic_init(unsigned char bus) p->interface = PMIC_I2C; p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR; p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH; - p->bus = bus; #else -#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C" +#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C" #endif return 0; diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index 66b3bab462..0dcf9fe918 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include int pmic_reg_write(struct pmic *p, u32 reg, u32 val) { @@ -23,6 +23,8 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) if (check_reg(p, reg)) return -1; + I2C_SET_BUS(p->bus); + switch (pmic_i2c_tx_num) { case 3: if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) { @@ -66,6 +68,8 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) if (check_reg(p, reg)) return -1; + I2C_SET_BUS(p->bus); + if (i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num)) return -1; @@ -98,7 +102,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) int pmic_probe(struct pmic *p) { - I2C_SET_BUS(p->bus); + i2c_set_bus_num(p->bus); debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name); if (i2c_probe(pmic_i2c_addr)) { printf("Can't find PMIC:%s\n", p->name); diff --git a/drivers/power/power_spi.c b/drivers/power/power_spi.c index fb455a0061..1e554461f3 100644 --- a/drivers/power/power_spi.c +++ b/drivers/power/power_spi.c @@ -17,27 +17,14 @@ static struct spi_slave *slave; -void pmic_spi_free(struct spi_slave *slave) -{ - if (slave) - spi_free_slave(slave); -} - -struct spi_slave *pmic_spi_probe(struct pmic *p) -{ - return spi_setup_slave(p->bus, - p->hw.spi.cs, - p->hw.spi.clk, - p->hw.spi.mode); -} - static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write) { u32 pmic_tx, pmic_rx; u32 tmp; if (!slave) { - slave = pmic_spi_probe(p); + slave = spi_setup_slave(p->bus, p->hw.spi.cs, p->hw.spi.clk, + p->hw.spi.mode); if (!slave) return -1; @@ -54,25 +41,25 @@ static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write) tmp = cpu_to_be32(pmic_tx); if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx, - pmic_spi_flags)) { - spi_release_bus(slave); - return -1; - } + pmic_spi_flags)) + goto err; if (write) { pmic_tx = p->hw.spi.prepare_tx(reg, val, 0); tmp = cpu_to_be32(pmic_tx); if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx, - pmic_spi_flags)) { - spi_release_bus(slave); - return -1; - } + pmic_spi_flags)) + goto err; } spi_release_bus(slave); *val = cpu_to_be32(pmic_rx); return 0; + +err: + spi_release_bus(slave); + return -1; } int pmic_reg_write(struct pmic *p, u32 reg, u32 val) diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c index 704c2439b1..865098386d 100644 --- a/drivers/power/tps6586x.c +++ b/drivers/power/tps6586x.c @@ -10,9 +10,7 @@ #include #include -static int bus_num; /* I2C bus we are on */ -#define I2C_ADDRESS 0x34 /* chip requires this address */ -static char inited; /* 1 if we have been inited */ +static struct udevice *tps6586x_dev; enum { /* Registers that we access */ @@ -32,18 +30,14 @@ enum { }; #define MAX_I2C_RETRY 3 -int tps6586x_read(int reg) +static int tps6586x_read(int reg) { int i; uchar data; int retval = -1; - int old_bus_num; - - old_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(bus_num); for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (!i2c_read(I2C_ADDRESS, reg, 1, &data, 1)) { + if (!dm_i2c_read(tps6586x_dev, reg, &data, 1)) { retval = (int)data; goto exit; } @@ -53,7 +47,6 @@ int tps6586x_read(int reg) } exit: - i2c_set_bus_num(old_bus_num); debug("pmu_read %x=%x\n", reg, retval); if (retval < 0) debug("%s: failed to read register %#x: %d\n", __func__, reg, @@ -61,17 +54,13 @@ exit: return retval; } -int tps6586x_write(int reg, uchar *data, uint len) +static int tps6586x_write(int reg, uchar *data, uint len) { int i; int retval = -1; - int old_bus_num; - - old_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(bus_num); for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (!i2c_write(I2C_ADDRESS, reg, 1, data, len)) { + if (!dm_i2c_write(tps6586x_dev, reg, data, len)) { retval = 0; goto exit; } @@ -81,7 +70,6 @@ int tps6586x_write(int reg, uchar *data, uint len) } exit: - i2c_set_bus_num(old_bus_num); debug("pmu_write %x=%x: ", reg, retval); for (i = 0; i < len; i++) debug("%x ", data[i]); @@ -163,7 +151,7 @@ int tps6586x_set_pwm_mode(int mask) uchar val; int ret; - assert(inited); + assert(tps6586x_dev); ret = tps6586x_read(PFM_MODE); if (ret != -1) { val = (uchar)ret; @@ -184,7 +172,7 @@ int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate, int sm0, sm1; int bad; - assert(inited); + assert(tps6586x_dev); /* get current voltage settings */ if (read_voltages(&sm0, &sm1)) { @@ -255,10 +243,9 @@ int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate, return bad ? -1 : 0; } -int tps6586x_init(int bus) +int tps6586x_init(struct udevice *dev) { - bus_num = bus; - inited = 1; + tps6586x_dev = dev; return 0; } diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index 3e50310464..7f1fdd1534 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -91,11 +91,23 @@ void twl4030_power_init(void) TWL4030_PM_RECEIVER_DEV_GRP_P1); } -void twl4030_power_mmc_init(void) +void twl4030_power_mmc_init(int dev_index) { - /* Set VMMC1 to 3.15 Volts */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED, - TWL4030_PM_RECEIVER_VMMC1_VSEL_32, - TWL4030_PM_RECEIVER_VMMC1_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); + if (dev_index == 0) { + /* Set VMMC1 to 3.15 Volts */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED, + TWL4030_PM_RECEIVER_VMMC1_VSEL_32, + TWL4030_PM_RECEIVER_VMMC1_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + mdelay(100); /* ramp-up delay from Linux code */ + } else if (dev_index == 1) { + /* Set VMMC2 to 3.15 Volts */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED, + TWL4030_PM_RECEIVER_VMMC2_VSEL_32, + TWL4030_PM_RECEIVER_VMMC2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + mdelay(100); /* ramp-up delay from Linux code */ + } } diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c index 0858b60e06..a1c6663a2e 100644 --- a/drivers/power/twl6030.c +++ b/drivers/power/twl6030.c @@ -9,6 +9,26 @@ #include +static struct twl6030_data *twl; + +static struct twl6030_data twl6030_info = { + .chip_type = chip_TWL6030, + .adc_rbase = GPCH0_LSB, + .adc_ctrl = CTRL_P2, + .adc_enable = CTRL_P2_SP2, + .vbat_mult = TWL6030_VBAT_MULT, + .vbat_shift = TWL6030_VBAT_SHIFT, +}; + +static struct twl6030_data twl6032_info = { + .chip_type = chip_TWL6032, + .adc_rbase = TWL6032_GPCH0_LSB, + .adc_ctrl = TWL6032_CTRL_P1, + .adc_enable = CTRL_P1_SP1, + .vbat_mult = TWL6032_VBAT_MULT, + .vbat_shift = TWL6032_VBAT_SHIFT, +}; + static int twl6030_gpadc_read_channel(u8 channel_no) { u8 lsb = 0; @@ -16,12 +36,12 @@ static int twl6030_gpadc_read_channel(u8 channel_no) int ret = 0; ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, - GPCH0_LSB + channel_no * 2, &lsb); + twl->adc_rbase + channel_no * 2, &lsb); if (ret) return ret; ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, - GPCH0_MSB + channel_no * 2, &msb); + twl->adc_rbase + 1 + channel_no * 2, &msb); if (ret) return ret; @@ -33,7 +53,8 @@ static int twl6030_gpadc_sw2_trigger(void) u8 val; int ret = 0; - ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2, CTRL_P2_SP2); + ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, + twl->adc_ctrl, twl->adc_enable); if (ret) return ret; @@ -41,7 +62,8 @@ static int twl6030_gpadc_sw2_trigger(void) val = CTRL_P2_BUSY; while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) { - ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, CTRL_P2, &val); + ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, + twl->adc_ctrl, &val); if (ret) return ret; udelay(1000); @@ -102,6 +124,18 @@ int twl6030_get_battery_voltage(void) { int battery_volt = 0; int ret = 0; + u8 vbatch; + + if (twl->chip_type == chip_TWL6030) { + vbatch = TWL6030_GPADC_VBAT_CHNL; + } else { + ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, + TWL6032_GPSELECT_ISB, + TWL6032_GPADC_VBAT_CHNL); + if (ret) + return ret; + vbatch = 0; + } /* Start GPADC SW conversion */ ret = twl6030_gpadc_sw2_trigger(); @@ -111,12 +145,12 @@ int twl6030_get_battery_voltage(void) } /* measure Vbat voltage */ - battery_volt = twl6030_gpadc_read_channel(7); + battery_volt = twl6030_gpadc_read_channel(vbatch); if (battery_volt < 0) { printf("Failed to read battery voltage\n"); return ret; } - battery_volt = (battery_volt * 25 * 1000) >> (10 + 2); + battery_volt = (battery_volt * twl->vbat_mult) >> twl->vbat_shift; printf("Battery Voltage: %d mV\n", battery_volt); return battery_volt; @@ -124,12 +158,35 @@ int twl6030_get_battery_voltage(void) void twl6030_init_battery_charging(void) { - u8 stat1 = 0; + u8 val = 0; int battery_volt = 0; int ret = 0; + ret = twl6030_i2c_read_u8(TWL6030_CHIP_USB, USB_PRODUCT_ID_LSB, &val); + if (ret) { + puts("twl6030_init_battery_charging(): could not determine chip!\n"); + return; + } + if (val == 0x30) { + twl = &twl6030_info; + } else if (val == 0x32) { + twl = &twl6032_info; + } else { + puts("twl6030_init_battery_charging(): unsupported chip type\n"); + return; + } + /* Enable VBAT measurement */ - twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS); + if (twl->chip_type == chip_TWL6030) { + twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS); + twl6030_i2c_write_u8(TWL6030_CHIP_ADC, + TWL6030_GPADC_CTRL, + GPADC_CTRL_SCALER_DIV4); + } else { + twl6030_i2c_write_u8(TWL6030_CHIP_ADC, + TWL6032_GPADC_CTRL2, + GPADC_CTRL2_CH18_SCALER_EN); + } /* Enable GPADC module */ ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS); @@ -146,10 +203,10 @@ void twl6030_init_battery_charging(void) printf("Main battery voltage too low!\n"); /* Check for the presence of USB charger */ - twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &stat1); + twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &val); /* check for battery presence indirectly via Fuel gauge */ - if ((stat1 & VBUS_DET) && (battery_volt < 3300)) + if ((val & VBUS_DET) && (battery_volt < 3300)) twl6030_start_usb_charging(); return; diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile new file mode 100644 index 0000000000..c0c4883317 --- /dev/null +++ b/drivers/pwm/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2001 +# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#ccflags-y += -DDEBUG + +obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c new file mode 100644 index 0000000000..f1d0b35d27 --- /dev/null +++ b/drivers/pwm/pwm-imx-util.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Basic support for the pwm modul on imx6. + * + * Based on linux:drivers/pwm/pwm-imx.c + * from + * Sascha Hauer + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +/* pwm_id from 0..3 */ +struct pwm_regs *pwm_id_to_reg(int pwm_id) +{ + switch (pwm_id) { + case 0: + return (struct pwm_regs *)PWM1_BASE_ADDR; + break; + case 1: + return (struct pwm_regs *)PWM2_BASE_ADDR; + break; + case 2: + return (struct pwm_regs *)PWM3_BASE_ADDR; + break; + case 3: + return (struct pwm_regs *)PWM4_BASE_ADDR; + break; + default: + printf("unknown pwm_id: %d\n", pwm_id); + break; + } + return NULL; +} + +int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c, + unsigned long *duty_c, unsigned long *prescale) +{ + unsigned long long c; + + /* + * we have not yet a clock framework for imx6, so add the clock + * value here as a define. Replace it when we have the clock + * framework. + */ + c = CONFIG_IMX6_PWM_PER_CLK; + c = c * period_ns; + do_div(c, 1000000000); + *period_c = c; + + *prescale = *period_c / 0x10000 + 1; + + *period_c /= *prescale; + c = (unsigned long long)(*period_c * duty_ns); + do_div(c, period_ns); + *duty_c = c; + + /* + * according to imx pwm RM, the real period value should be + * PERIOD value in PWMPR plus 2. + */ + if (*period_c > 2) + *period_c -= 2; + else + *period_c = 0; + + return 0; +} diff --git a/drivers/pwm/pwm-imx-util.h b/drivers/pwm/pwm-imx-util.h new file mode 100644 index 0000000000..45465c4fde --- /dev/null +++ b/drivers/pwm/pwm-imx-util.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Basic support for the pwm modul on imx6. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _pwm_imx_util_h_ +#define _pwm_imx_util_h_ + +struct pwm_regs *pwm_id_to_reg(int pwm_id); +int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c, + unsigned long *duty_c, unsigned long *prescale); +#endif diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c new file mode 100644 index 0000000000..40bf027543 --- /dev/null +++ b/drivers/pwm/pwm-imx.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Basic support for the pwm modul on imx6. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "pwm-imx-util.h" + +int pwm_init(int pwm_id, int div, int invert) +{ + struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id); + + writel(0, &pwm->ir); + return 0; +} + +int pwm_config(int pwm_id, int duty_ns, int period_ns) +{ + struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id); + unsigned long period_cycles, duty_cycles, prescale; + u32 cr; + + pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles, + &prescale); + + cr = PWMCR_PRESCALER(prescale) | + PWMCR_DOZEEN | PWMCR_WAITEN | + PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH; + + writel(cr, &pwm->cr); + /* set duty cycles */ + writel(duty_cycles, &pwm->sar); + /* set period cycles */ + writel(period_cycles, &pwm->pr); + return 0; +} + +int pwm_enable(int pwm_id) +{ + struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id); + + setbits_le32(&pwm->cr, PWMCR_EN); + return 0; +} + +void pwm_disable(int pwm_id) +{ + struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id); + + clrbits_le32(&pwm->cr, PWMCR_EN); +} diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile index 3aaf757934..8fa48667ec 100644 --- a/drivers/qe/Makefile +++ b/drivers/qe/Makefile @@ -4,26 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libqe.o - -COBJS-$(and $(CONFIG_QE),$(CONFIG_OF_LIBFDT)) += fdt.o -COBJS-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_U_QE) += qe.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index d9a7d8206f..dfae4bf64d 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -12,6 +12,7 @@ #include #include "qe.h" +#ifdef CONFIG_QE DECLARE_GLOBAL_DATA_PTR; /* @@ -72,3 +73,4 @@ void ft_qe_setup(void *blob) "clock-frequency", gd->arch.qe_clk / 2, 1); fdt_fixup_qe_firmware(blob); } +#endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index b5ddc4b474..fd72259a57 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -11,8 +11,13 @@ #include #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" +#ifdef CONFIG_SOC_LS102XA +#include +#endif + +#define MPC85xx_DEVDISR_QE_DISABLE 0x1 qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; @@ -38,6 +43,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) return; } +#ifdef CONFIG_QE uint qe_muram_alloc(uint size, uint align) { uint retloc; @@ -68,6 +74,7 @@ uint qe_muram_alloc(uint size, uint align) return retloc; } +#endif void *qe_muram_addr(uint offset) { @@ -165,7 +172,7 @@ void qe_init(uint qe_base) /* * Upload microcode to IRAM for those SOCs which do not have ROM in QE. */ - qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR); + qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); /* enable the microcode in IRAM */ out_be32(&qe_immr->iram.iready,QE_IRAM_READY); @@ -178,6 +185,17 @@ void qe_init(uint qe_base) qe_snums_init(); } +#ifdef CONFIG_U_QE +void u_qe_init(void) +{ + uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */ + qe_immr = (qe_map_t *)qe_base; + + u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); +} +#endif + void qe_reset(void) { qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, @@ -210,6 +228,7 @@ void qe_assign_page(uint snum, uint para_ram_base) #define BRG_CLK (gd->arch.brg_clk) +#ifdef CONFIG_QE int qe_set_brg(uint brg, uint rate) { volatile uint *bp; @@ -237,6 +256,7 @@ int qe_set_brg(uint brg, uint rate) return 0; } +#endif /* Set ethernet MII clock master */ @@ -317,7 +337,13 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t calc_size = sizeof(struct qe_firmware); size_t length; const struct qe_header *hdr; - +#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_SOC_LS102XA + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; +#else + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif +#endif if (!firmware) { printf("Invalid address\n"); return -EINVAL; @@ -329,7 +355,10 @@ int qe_upload_firmware(const struct qe_firmware *firmware) /* Check the magic */ if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { - printf("Not a microcode\n"); + printf("QE microcode not found\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif return -EPERM; } @@ -422,6 +451,135 @@ int qe_upload_firmware(const struct qe_firmware *firmware) return 0; } +#ifdef CONFIG_U_QE +/* + * Upload a microcode to the I-RAM at a specific address. + * + * See docs/README.qe_firmware for information on QE microcode uploading. + * + * Currently, only version 1 is supported, so the 'version' field must be + * set to 1. + * + * The SOC model and revision are not validated, they are only displayed for + * informational purposes. + * + * 'calc_size' is the calculated size, in bytes, of the firmware structure and + * all of the microcode structures, minus the CRC. + * + * 'length' is the size that the structure says it is, including the CRC. + */ +int u_qe_upload_firmware(const struct qe_firmware *firmware) +{ + unsigned int i; + unsigned int j; + u32 crc; + size_t calc_size = sizeof(struct qe_firmware); + size_t length; + const struct qe_header *hdr; +#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_SOC_LS102XA + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; +#else + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif +#endif + if (!firmware) { + printf("Invalid address\n"); + return -EINVAL; + } + + hdr = &firmware->header; + length = be32_to_cpu(hdr->length); + + /* Check the magic */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Not a microcode\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif + return -EPERM; + } + + /* Check the version */ + if (hdr->version != 1) { + printf("Unsupported version\n"); + return -EPERM; + } + + /* Validate some of the fields */ + if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) { + printf("Invalid data\n"); + return -EINVAL; + } + + /* Validate the length and check if there's a CRC */ + calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); + + for (i = 0; i < firmware->count; i++) + /* + * For situations where the second RISC uses the same microcode + * as the first, the 'code_offset' and 'count' fields will be + * zero, so it's okay to add those. + */ + calc_size += sizeof(u32) * + be32_to_cpu(firmware->microcode[i].count); + + /* Validate the length */ + if (length != calc_size + sizeof(u32)) { + printf("Invalid length\n"); + return -EPERM; + } + + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ + crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); + if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) { + printf("Firmware CRC is invalid\n"); + return -EIO; + } + + /* + * If the microcode calls for it, split the I-RAM. + */ + if (!firmware->split) { + out_be16(&qe_immr->cp.cercr, + in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR); + } + + if (firmware->soc.model) + printf("Firmware '%s' for %u V%u.%u\n", + firmware->id, be16_to_cpu(firmware->soc.model), + firmware->soc.major, firmware->soc.minor); + else + printf("Firmware '%s'\n", firmware->id); + + /* Loop through each microcode. */ + for (i = 0; i < firmware->count; i++) { + const struct qe_microcode *ucode = &firmware->microcode[i]; + + /* Upload a microcode if it's present */ + if (ucode->code_offset) + qe_upload_microcode(firmware, ucode); + + /* Program the traps for this processor */ + for (j = 0; j < 16; j++) { + u32 trap = be32_to_cpu(ucode->traps[j]); + + if (trap) + out_be32(&qe_immr->rsp[i].tibcr[j], trap); + } + + /* Enable traps */ + out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr)); + } + + return 0; +} +#endif + struct qe_firmware_info *qe_get_firmware_info(void) { return qe_firmware_uploaded ? &qe_firmware_info : NULL; diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index c82ac7b071..33878f897b 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -282,5 +282,12 @@ int qe_set_mii_clk_src(int ucc_num); int qe_upload_firmware(const struct qe_firmware *firmware); struct qe_firmware_info *qe_get_firmware_info(void); void ft_qe_setup(void *blob); +void qe_init(uint qe_base); +void qe_reset(void); + +#ifdef CONFIG_U_QE +void u_qe_init(void); +int u_qe_upload_firmware(const struct qe_firmware *firmware); +#endif #endif /* __QE_H__ */ diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c index 593d96d1a2..85386bfc70 100644 --- a/drivers/qe/uccf.c +++ b/drivers/qe/uccf.c @@ -11,7 +11,7 @@ #include "malloc.h" #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" #include "uccf.h" diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h index 0b57e2f422..55941e4601 100644 --- a/drivers/qe/uccf.h +++ b/drivers/qe/uccf.h @@ -12,7 +12,7 @@ #include "common.h" #include "qe.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" /* Fast or Giga ethernet */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 68045733b8..c91f084a7c 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -11,7 +11,7 @@ #include "malloc.h" #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" #include "uccf.h" #include "uec.h" diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 48a163411c..6b559f7974 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -13,7 +13,6 @@ #include "qe.h" #include "uccf.h" #include -#include #define MAX_TX_THREADS 8 #define MAX_RX_THREADS 8 diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 5dc4641bf6..e701787c41 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -14,7 +14,7 @@ #include "net.h" #include "malloc.h" #include "asm/errno.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "asm/io.h" #include "qe.h" #include "uccf.h" diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index b477c23ebd..fdcbc00295 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -5,71 +5,48 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -#CFLAGS += -DDEBUG - -LIB = $(obj)librtc.o - -COBJS-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o -COBJS-$(CONFIG_RTC_BFIN) += bfin_rtc.o -COBJS-y += date.o -COBJS-$(CONFIG_RTC_DAVINCI) += davinci.o -COBJS-$(CONFIG_RTC_DS12887) += ds12887.o -COBJS-$(CONFIG_RTC_DS1302) += ds1302.o -COBJS-$(CONFIG_RTC_DS1306) += ds1306.o -COBJS-$(CONFIG_RTC_DS1307) += ds1307.o -COBJS-$(CONFIG_RTC_DS1338) += ds1307.o -COBJS-$(CONFIG_RTC_DS1337) += ds1337.o -COBJS-$(CONFIG_RTC_DS1374) += ds1374.o -COBJS-$(CONFIG_RTC_DS1388) += ds1337.o -COBJS-$(CONFIG_RTC_DS1556) += ds1556.o -COBJS-$(CONFIG_RTC_DS164x) += ds164x.o -COBJS-$(CONFIG_RTC_DS174x) += ds174x.o -COBJS-$(CONFIG_RTC_DS3231) += ds3231.o -COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o -COBJS-$(CONFIG_RTC_IMXDI) += imxdi.o -COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o -COBJS-$(CONFIG_RTC_M41T11) += m41t11.o -COBJS-$(CONFIG_RTC_M41T60) += m41t60.o -COBJS-$(CONFIG_RTC_M41T62) += m41t62.o -COBJS-$(CONFIG_RTC_M41T94) += m41t94.o -COBJS-$(CONFIG_RTC_M48T35A) += m48t35ax.o -COBJS-$(CONFIG_RTC_MAX6900) += max6900.o -COBJS-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o -COBJS-$(CONFIG_RTC_MC146818) += mc146818.o -COBJS-$(CONFIG_MCFRTC) += mcfrtc.o -COBJS-$(CONFIG_RTC_MK48T59) += mk48t59.o -COBJS-$(CONFIG_RTC_MPC5200) += mpc5xxx.o -COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o -COBJS-$(CONFIG_RTC_MV) += mvrtc.o -COBJS-$(CONFIG_RTC_MX27) += mx27rtc.o -COBJS-$(CONFIG_RTC_MXS) += mxsrtc.o -COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o -COBJS-$(CONFIG_RTC_PL031) += pl031.o -COBJS-$(CONFIG_RTC_PT7C4338) += pt7c4338.o -COBJS-$(CONFIG_RTC_RS5C372A) += rs5c372.o -COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o -COBJS-$(CONFIG_RTC_RV3029) += rv3029.o -COBJS-$(CONFIG_RTC_RX8025) += rx8025.o -COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o -COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o -COBJS-$(CONFIG_RTC_X1205) += x1205.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +#ccflags-y += -DDEBUG + +obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o +obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o +obj-y += date.o +obj-$(CONFIG_RTC_DAVINCI) += davinci.o +obj-$(CONFIG_RTC_DS1302) += ds1302.o +obj-$(CONFIG_RTC_DS1306) += ds1306.o +obj-$(CONFIG_RTC_DS1307) += ds1307.o +obj-$(CONFIG_RTC_DS1338) += ds1307.o +obj-$(CONFIG_RTC_DS1339) += ds1307.o +obj-$(CONFIG_RTC_DS1337) += ds1337.o +obj-$(CONFIG_RTC_DS1374) += ds1374.o +obj-$(CONFIG_RTC_DS1388) += ds1337.o +obj-$(CONFIG_RTC_DS1556) += ds1556.o +obj-$(CONFIG_RTC_DS164x) += ds164x.o +obj-$(CONFIG_RTC_DS174x) += ds174x.o +obj-$(CONFIG_RTC_DS3231) += ds3231.o +obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o +obj-$(CONFIG_RTC_IMXDI) += imxdi.o +obj-$(CONFIG_RTC_ISL1208) += isl1208.o +obj-$(CONFIG_RTC_M41T11) += m41t11.o +obj-$(CONFIG_RTC_M41T60) += m41t60.o +obj-$(CONFIG_RTC_M41T62) += m41t62.o +obj-$(CONFIG_RTC_M41T94) += m41t94.o +obj-$(CONFIG_RTC_M48T35A) += m48t35ax.o +obj-$(CONFIG_RTC_MAX6900) += max6900.o +obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o +obj-$(CONFIG_RTC_MC146818) += mc146818.o +obj-$(CONFIG_MCFRTC) += mcfrtc.o +obj-$(CONFIG_RTC_MK48T59) += mk48t59.o +obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o +obj-$(CONFIG_RTC_MPC8xx) += mpc8xx.o +obj-$(CONFIG_RTC_MV) += mvrtc.o +obj-$(CONFIG_RTC_MX27) += mx27rtc.o +obj-$(CONFIG_RTC_MXS) += mxsrtc.o +obj-$(CONFIG_RTC_PCF8563) += pcf8563.o +obj-$(CONFIG_RTC_PL031) += pl031.o +obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o +obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o +obj-$(CONFIG_RTC_RTC4543) += rtc4543.o +obj-$(CONFIG_RTC_RV3029) += rv3029.o +obj-$(CONFIG_RTC_RX8025) += rx8025.o +obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o +obj-$(CONFIG_RTC_X1205) += x1205.o diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c index 5de695384f..4cf2d834b2 100644 --- a/drivers/rtc/bfin_rtc.c +++ b/drivers/rtc/bfin_rtc.c @@ -27,7 +27,7 @@ #define NUM_SECS_IN_DAY DAYS_TO_SECS(1) /* Enable the RTC prescaler enable register */ -static void rtc_init(void) +void rtc_init(void) { if (!(bfin_read_RTC_PREN() & 0x1)) bfin_write_RTC_PREN(0x1); @@ -68,7 +68,7 @@ int rtc_set(struct rtc_time *tmp) /* Calculate number of seconds this incoming time represents */ remain = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); /* Figure out how many days since epoch */ days = remain / NUM_SECS_IN_DAY; diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index e60c0da64c..f862e2f951 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -8,12 +8,12 @@ #include #include #include -#include +#include #if defined(CONFIG_CMD_DATE) int rtc_get(struct rtc_time *tmp) { - struct davinci_rtc *rtc = davinci_rtc_base; + struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; unsigned long sec, min, hour, mday, wday, mon_cent, year; unsigned long status; @@ -57,7 +57,7 @@ int rtc_get(struct rtc_time *tmp) int rtc_set(struct rtc_time *tmp) { - struct davinci_rtc *rtc = davinci_rtc_base; + struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, @@ -75,7 +75,7 @@ int rtc_set(struct rtc_time *tmp) void rtc_reset(void) { - struct davinci_rtc *rtc = davinci_rtc_base; + struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; /* run RTC counter */ writel(0x01, &rtc->ctrl); diff --git a/drivers/rtc/ds12887.c b/drivers/rtc/ds12887.c deleted file mode 100644 index d8a519b8fe..0000000000 --- a/drivers/rtc/ds12887.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * (C) Copyright 2003 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Date & Time support for the DS12887 RTC - */ - -#undef RTC_DEBUG - -#include -#include -#include -#include - -#if defined(CONFIG_CMD_DATE) - -#define RTC_SECONDS 0x00 -#define RTC_SECONDS_ALARM 0x01 -#define RTC_MINUTES 0x02 -#define RTC_MINUTES_ALARM 0x03 -#define RTC_HOURS 0x04 -#define RTC_HOURS_ALARM 0x05 -#define RTC_DAY_OF_WEEK 0x06 -#define RTC_DATE_OF_MONTH 0x07 -#define RTC_MONTH 0x08 -#define RTC_YEAR 0x09 -#define RTC_CONTROL_A 0x0A -#define RTC_CONTROL_B 0x0B -#define RTC_CONTROL_C 0x0C -#define RTC_CONTROL_D 0x0D - -#define RTC_CA_UIP 0x80 -#define RTC_CB_DM 0x04 -#define RTC_CB_24_12 0x02 -#define RTC_CB_SET 0x80 - -#if defined(CONFIG_ATC) - -static uchar rtc_read (uchar reg) -{ - uchar val; - - *(volatile unsigned char*)(RTC_PORT_ADDR) = reg; - __asm__ __volatile__ ("sync"); - - val = *(volatile unsigned char*)(RTC_PORT_DATA); - return (val); -} - -static void rtc_write (uchar reg, uchar val) -{ - *(volatile unsigned char*)(RTC_PORT_ADDR) = reg; - __asm__ __volatile__ ("sync"); - - *(volatile unsigned char*)(RTC_PORT_DATA) = val; - __asm__ __volatile__ ("sync"); -} - -#else -# error Board specific rtc access functions should be supplied -#endif - -int rtc_get (struct rtc_time *tmp) -{ - uchar sec, min, hour, mday, wday, mon, year; - - /* check if rtc is available for access */ - while( rtc_read(RTC_CONTROL_A) & RTC_CA_UIP) - ; - - sec = rtc_read(RTC_SECONDS); - min = rtc_read(RTC_MINUTES); - hour = rtc_read(RTC_HOURS); - mday = rtc_read(RTC_DATE_OF_MONTH); - wday = rtc_read(RTC_DAY_OF_WEEK); - mon = rtc_read(RTC_MONTH); - year = rtc_read(RTC_YEAR); - -#ifdef RTC_DEBUG - printf( "Get RTC year: %d; mon: %d; mday: %d; wday: %d; " - "hr: %d; min: %d; sec: %d\n", - year, mon, mday, wday, hour, min, sec ); - - printf ( "Alarms: hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_HOURS_ALARM), - rtc_read (RTC_MINUTES_ALARM), - rtc_read (RTC_SECONDS_ALARM) ); -#endif - - if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM)) - { /* Information is in BCD format */ -printf(" Get: Convert BSD to BIN\n"); - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon & 0x1F); - tmp->tm_year = bcd2bin (year); - tmp->tm_wday = bcd2bin (wday & 0x07); - } -else - { - tmp->tm_sec = sec & 0x7F; - tmp->tm_min = min & 0x7F; - tmp->tm_hour = hour & 0x3F; - tmp->tm_mday = mday & 0x3F; - tmp->tm_mon = mon & 0x1F; - tmp->tm_year = year; - tmp->tm_wday = wday & 0x07; - } - - - if(tmp->tm_year<70) - tmp->tm_year+=2000; - else - tmp->tm_year+=1900; - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - uchar save_ctrl_b; - uchar sec, min, hour, mday, wday, mon, year; - -#ifdef RTC_DEBUG - printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM)) - { /* Information is in BCD format */ - year = bin2bcd(tmp->tm_year % 100); - mon = bin2bcd(tmp->tm_mon); - wday = bin2bcd(tmp->tm_wday); - mday = bin2bcd(tmp->tm_mday); - hour = bin2bcd(tmp->tm_hour); - min = bin2bcd(tmp->tm_min); - sec = bin2bcd(tmp->tm_sec); - } - else - { - year = tmp->tm_year % 100; - mon = tmp->tm_mon; - wday = tmp->tm_wday; - mday = tmp->tm_mday; - hour = tmp->tm_hour; - min = tmp->tm_min; - sec = tmp->tm_sec; - } - - /* disables the RTC to update the regs */ - save_ctrl_b = rtc_read(RTC_CONTROL_B); - save_ctrl_b |= RTC_CB_SET; - rtc_write(RTC_CONTROL_B, save_ctrl_b); - - rtc_write (RTC_YEAR, year); - rtc_write (RTC_MONTH, mon); - rtc_write (RTC_DAY_OF_WEEK, wday); - rtc_write (RTC_DATE_OF_MONTH, mday); - rtc_write (RTC_HOURS, hour); - rtc_write (RTC_MINUTES, min); - rtc_write (RTC_SECONDS, sec); - - /* enables the RTC to update the regs */ - save_ctrl_b &= ~RTC_CB_SET; - rtc_write(RTC_CONTROL_B, save_ctrl_b); - - return 0; -} - -void rtc_reset (void) -{ - struct rtc_time tmp; - uchar ctrl_rg; - - ctrl_rg = RTC_CB_SET; - rtc_write(RTC_CONTROL_B,ctrl_rg); - - tmp.tm_year = 1970 % 100; - tmp.tm_mon = 1; - tmp.tm_mday= 1; - tmp.tm_hour = 0; - tmp.tm_min = 0; - tmp.tm_sec = 0; - -#ifdef RTC_DEBUG - printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", - tmp.tm_year, tmp.tm_mon, tmp.tm_mday, - tmp.tm_hour, tmp.tm_min, tmp.tm_sec); -#endif - - ctrl_rg = RTC_CB_SET | RTC_CB_24_12 | RTC_CB_DM; - rtc_write(RTC_CONTROL_B,ctrl_rg); - rtc_set(&tmp); - - rtc_write(RTC_HOURS_ALARM, 0), - rtc_write(RTC_MINUTES_ALARM, 0), - rtc_write(RTC_SECONDS_ALARM, 0); - - ctrl_rg = RTC_CB_24_12 | RTC_CB_DM; - rtc_write(RTC_CONTROL_B,ctrl_rg); -} - -#endif diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 1a2bad3c5c..03ab1a8c5d 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -9,7 +9,7 @@ /* * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) - * DS1307 and DS1338 Real Time Clock (RTC). + * DS1307 and DS1338/9 Real Time Clock (RTC). * * based on ds1337.c */ diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 5f9d359590..c9d318c0a7 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -14,8 +14,9 @@ #include #include #include +#include -#ifdef __I386__ +#if defined(__I386__) || defined(CONFIG_MALTA) #include #define in8(p) inb(p) #define out8(p, v) outb(v, p) @@ -23,8 +24,8 @@ #if defined(CONFIG_CMD_DATE) -static uchar rtc_read (uchar reg); -static void rtc_write (uchar reg, uchar val); +/* Set this to 1 to clear the CMOS RAM */ +#define CLEAR_CMOS 0 #define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70 #define RTC_SECONDS 0x00 @@ -41,7 +42,14 @@ static void rtc_write (uchar reg, uchar val); #define RTC_CONFIG_B 0x0B #define RTC_CONFIG_C 0x0C #define RTC_CONFIG_D 0x0D +#define RTC_REG_SIZE 0x80 +#define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5) +#define RTC_CONFIG_A_RATE_1024HZ 6 + +#define RTC_CONFIG_B_24H (1 << 1) + +#define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80 /* ------------------------------------------------------------------------- */ @@ -49,24 +57,24 @@ int rtc_get (struct rtc_time *tmp) { uchar sec, min, hour, mday, wday, mon, year; /* here check if rtc can be accessed */ - while((rtc_read(RTC_CONFIG_A)&0x80)==0x80); - sec = rtc_read (RTC_SECONDS); - min = rtc_read (RTC_MINUTES); - hour = rtc_read (RTC_HOURS); - mday = rtc_read (RTC_DATE_OF_MONTH); - wday = rtc_read (RTC_DAY_OF_WEEK); - mon = rtc_read (RTC_MONTH); - year = rtc_read (RTC_YEAR); + while ((rtc_read8(RTC_CONFIG_A) & 0x80) == 0x80); + sec = rtc_read8(RTC_SECONDS); + min = rtc_read8(RTC_MINUTES); + hour = rtc_read8(RTC_HOURS); + mday = rtc_read8(RTC_DATE_OF_MONTH); + wday = rtc_read8(RTC_DAY_OF_WEEK); + mon = rtc_read8(RTC_MONTH); + year = rtc_read8(RTC_YEAR); #ifdef RTC_DEBUG printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " "hr: %02x min: %02x sec: %02x\n", year, mon, mday, wday, hour, min, sec ); printf ( "Alarms: month: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_CONFIG_D) & 0x3F, - rtc_read (RTC_HOURS_ALARM), - rtc_read (RTC_MINUTES_ALARM), - rtc_read (RTC_SECONDS_ALARM) ); + rtc_read8(RTC_CONFIG_D) & 0x3F, + rtc_read8(RTC_HOURS_ALARM), + rtc_read8(RTC_MINUTES_ALARM), + rtc_read8(RTC_SECONDS_ALARM)); #endif tmp->tm_sec = bcd2bin (sec & 0x7F); tmp->tm_min = bcd2bin (min & 0x7F); @@ -97,56 +105,108 @@ int rtc_set (struct rtc_time *tmp) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif - rtc_write(RTC_CONFIG_B,0x82); /* disables the RTC to update the regs */ + rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */ - rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100)); - rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon)); - rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); - rtc_write (RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday)); - rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour)); - rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min )); - rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec )); - rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */ + rtc_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100)); + rtc_write8(RTC_MONTH, bin2bcd(tmp->tm_mon)); + rtc_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); + rtc_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday)); + rtc_write8(RTC_HOURS, bin2bcd(tmp->tm_hour)); + rtc_write8(RTC_MINUTES, bin2bcd(tmp->tm_min)); + rtc_write8(RTC_SECONDS, bin2bcd(tmp->tm_sec)); + rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */ return 0; } void rtc_reset (void) { - rtc_write(RTC_CONFIG_B,0x82); /* disables the RTC to update the regs */ - rtc_write(RTC_CONFIG_A,0x20); /* Normal OP */ - rtc_write(RTC_CONFIG_B,0x00); - rtc_write(RTC_CONFIG_B,0x00); - rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */ + rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */ + rtc_write8(RTC_CONFIG_A, 0x20); /* Normal OP */ + rtc_write8(RTC_CONFIG_B, 0x00); + rtc_write8(RTC_CONFIG_B, 0x00); + rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */ } /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR /* * use direct memory access */ -static uchar rtc_read (uchar reg) +int rtc_read8(int reg) { - return(in8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg)); +#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR + return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg); +#else + int ofs = 0; + + if (reg >= 128) { + ofs = 2; + reg -= 128; + } + out8(RTC_PORT_MC146818 + ofs, reg); + + return in8(RTC_PORT_MC146818 + ofs + 1); +#endif } -static void rtc_write (uchar reg, uchar val) +void rtc_write8(int reg, uchar val) { - out8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg, val); -} +#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR + out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val); #else -static uchar rtc_read (uchar reg) + int ofs = 0; + + if (reg >= 128) { + ofs = 2; + reg -= 128; + } + out8(RTC_PORT_MC146818 + ofs, reg); + out8(RTC_PORT_MC146818 + ofs + 1, val); +#endif +} + +u32 rtc_read32(int reg) { - out8(RTC_PORT_MC146818,reg); - return(in8(RTC_PORT_MC146818+1)); + u32 value = 0; + int i; + + for (i = 0; i < sizeof(value); i++) + value |= rtc_read8(reg + i) << (i << 3); + + return value; } -static void rtc_write (uchar reg, uchar val) +void rtc_write32(int reg, u32 value) { - out8(RTC_PORT_MC146818,reg); - out8(RTC_PORT_MC146818+1,val); + int i; + + for (i = 0; i < sizeof(value); i++) + rtc_write8(reg + i, (value >> (i << 3)) & 0xff); } + +void rtc_init(void) +{ +#if CLEAR_CMOS + int i; + + rtc_write8(RTC_SECONDS_ALARM, 0); + rtc_write8(RTC_MINUTES_ALARM, 0); + rtc_write8(RTC_HOURS_ALARM, 0); + for (i = RTC_CONFIG_A; i < RTC_REG_SIZE; i++) + rtc_write8(i, 0); + printf("RTC: zeroing CMOS RAM\n"); #endif + /* Setup the real time clock */ + rtc_write8(RTC_CONFIG_B, RTC_CONFIG_B_24H); + /* Setup the frequency it operates at */ + rtc_write8(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ | + RTC_CONFIG_A_RATE_1024HZ); + /* Ensure all reserved bits are 0 in register D */ + rtc_write8(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME); + + /* Clear any pending interrupts */ + rtc_read8(RTC_CONFIG_C); +} #endif diff --git a/drivers/rtc/mvrtc.h b/drivers/rtc/mvrtc.h index ce7a69bab5..424743c990 100644 --- a/drivers/rtc/mvrtc.h +++ b/drivers/rtc/mvrtc.h @@ -12,8 +12,8 @@ #ifndef _MVRTC_H_ #define _MVRTC_H_ -#include -#include +#include +#include /* RTC registers */ struct mvrtc_registers { diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c index 11cc719828..c4d1259a89 100644 --- a/drivers/rtc/pl031.c +++ b/drivers/rtc/pl031.c @@ -73,7 +73,7 @@ int rtc_set(struct rtc_time *tmp) /* Calculate number of seconds this incoming time represents */ tim = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); RTC_WRITE_REG(RTC_LR, tim); diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c index 1a179beadd..65f45ea5e3 100644 --- a/drivers/rtc/rs5c372.c +++ b/drivers/rtc/rs5c372.c @@ -16,7 +16,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * published by the Free Software Foundation. */ #include diff --git a/drivers/rtc/s3c44b0_rtc.c b/drivers/rtc/s3c44b0_rtc.c deleted file mode 100644 index de7898cc34..0000000000 --- a/drivers/rtc/s3c44b0_rtc.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * S3C44B0 CPU specific code - */ - -#include -#include -#include -#include - -int rtc_get (struct rtc_time* tm) -{ - RTCCON |= 1; - tm->tm_year = bcd2bin(BCDYEAR); - tm->tm_mon = bcd2bin(BCDMON); - tm->tm_wday = bcd2bin(BCDDATE); - tm->tm_mday = bcd2bin(BCDDAY); - tm->tm_hour = bcd2bin(BCDHOUR); - tm->tm_min = bcd2bin(BCDMIN); - tm->tm_sec = bcd2bin(BCDSEC); - - if (tm->tm_sec==0) { - /* we have to re-read the rtc data because of the "one second deviation" problem */ - /* see RTC datasheet for more info about it */ - tm->tm_year = bcd2bin(BCDYEAR); - tm->tm_mon = bcd2bin(BCDMON); - tm->tm_mday = bcd2bin(BCDDAY); - tm->tm_wday = bcd2bin(BCDDATE); - tm->tm_hour = bcd2bin(BCDHOUR); - tm->tm_min = bcd2bin(BCDMIN); - tm->tm_sec = bcd2bin(BCDSEC); - } - - RTCCON &= ~1; - - if(tm->tm_year >= 70) - tm->tm_year += 1900; - else - tm->tm_year += 2000; - - return 0; -} - -int rtc_set (struct rtc_time* tm) -{ - if(tm->tm_year < 2000) - tm->tm_year -= 1900; - else - tm->tm_year -= 2000; - - RTCCON |= 1; - BCDYEAR = bin2bcd(tm->tm_year); - BCDMON = bin2bcd(tm->tm_mon); - BCDDAY = bin2bcd(tm->tm_mday); - BCDDATE = bin2bcd(tm->tm_wday); - BCDHOUR = bin2bcd(tm->tm_hour); - BCDMIN = bin2bcd(tm->tm_min); - BCDSEC = bin2bcd(tm->tm_sec); - RTCCON &= 1; - - return 0; -} - -void rtc_reset (void) -{ - RTCCON |= 1; - BCDYEAR = 0; - BCDMON = 0; - BCDDAY = 0; - BCDDATE = 0; - BCDHOUR = 0; - BCDMIN = 0; - BCDSEC = 0; - RTCCON &= 1; -} diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig new file mode 100644 index 0000000000..a0b6e02b54 --- /dev/null +++ b/drivers/serial/Kconfig @@ -0,0 +1,12 @@ +config DM_SERIAL + bool "Enable Driver Model for serial drivers" + depends on DM + help + If you want to use driver model for serial drivers, say Y. + To use legacy serial drivers, say N. + +config UNIPHIER_SERIAL + bool "UniPhier on-chip UART support" + depends on ARCH_UNIPHIER && DM_SERIAL + help + Support for the on-chip UARTs on the Panasonic UniPhier platform. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 697f2bb4e8..4cc00cd2f8 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -5,58 +5,46 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libserial.o - -COBJS-y += serial.o +ifdef CONFIG_DM_SERIAL +obj-y += serial-uclass.o +obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o +else +obj-y += serial.o +obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o +obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o +obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o +endif -COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o -COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o -COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o -COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o -COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o -COBJS-$(CONFIG_MCFUART) += mcfuart.o -COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o -COBJS-$(CONFIG_SYS_NS16550) += ns16550.o -COBJS-$(CONFIG_S5P) += serial_s5p.o -COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o -COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o -COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o -COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o -COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o -COBJS-$(CONFIG_MXC_UART) += serial_mxc.o -COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o -COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o -COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o -COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o -COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o -COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o -COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o -COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o -COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o -COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o -COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o -COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o +obj-$(CONFIG_ALTERA_UART) += altera_uart.o +obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_ARM_DCC) += arm_dcc.o +obj-$(CONFIG_ATMEL_USART) += atmel_usart.o +obj-$(CONFIG_DW_SERIAL) += serial_dw.o +obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o +obj-$(CONFIG_MCFUART) += mcfuart.o +obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o +obj-$(CONFIG_SYS_NS16550) += ns16550.o +obj-$(CONFIG_S5P) += serial_s5p.o +obj-$(CONFIG_IMX_SERIAL) += serial_imx.o +obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o +obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o +obj-$(CONFIG_MXC_UART) += serial_mxc.o +obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o +obj-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o +obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o +obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o +obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o +obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o +obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o +obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o +obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o +obj-$(CONFIG_MXS_AUART) += mxs_auart.o +obj-$(CONFIG_ARC_SERIAL) += serial_arc.o +obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o +obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o +obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o +obj-$(CONFIG_X86_SERIAL) += serial_x86.o ifndef CONFIG_SPL_BUILD -COBJS-$(CONFIG_USB_TTY) += usbtty.o +obj-$(CONFIG_USB_TTY) += usbtty.o endif - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 0573c7a987..9a81402ffb 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -8,10 +8,28 @@ #include #include #include -#include #include #include +typedef volatile struct { + unsigned data; /* Data register */ + unsigned control; /* Control register */ +} nios_jtag_t; + +/* data register */ +#define NIOS_JTAG_RVALID (1<<15) /* Read valid */ +#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */ +#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ + +/* control register */ +#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ +#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ +#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ +#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ +#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ +#define NIOS_JTAG_RRDY (1 << 12) /* read available */ +#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ + DECLARE_GLOBAL_DATA_PTR; /*------------------------------------------------------------------ diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index d620528e3e..d6b14844d6 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -9,10 +9,47 @@ #include #include #include -#include #include #include +typedef volatile struct { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned divisor; /* Baud rate divisor reg */ + unsigned endofpacket; /* End-of-packet reg */ +} nios_uart_t; + +/* status register */ +#define NIOS_UART_PE (1 << 0) /* parity error */ +#define NIOS_UART_FE (1 << 1) /* frame error */ +#define NIOS_UART_BRK (1 << 2) /* break detect */ +#define NIOS_UART_ROE (1 << 3) /* rx overrun */ +#define NIOS_UART_TOE (1 << 4) /* tx overrun */ +#define NIOS_UART_TMT (1 << 5) /* tx empty */ +#define NIOS_UART_TRDY (1 << 6) /* tx ready */ +#define NIOS_UART_RRDY (1 << 7) /* rx ready */ +#define NIOS_UART_E (1 << 8) /* exception */ +#define NIOS_UART_DCTS (1 << 10) /* cts change */ +#define NIOS_UART_CTS (1 << 11) /* cts */ +#define NIOS_UART_EOP (1 << 12) /* eop detected */ + +/* control register */ +#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ +#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ +#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ +#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ +#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_UART_IE (1 << 8) /* exception int ena */ +#define NIOS_UART_TBRK (1 << 9) /* transmit break */ +#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ +#define NIOS_UART_RTS (1 << 11) /* rts */ +#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ + DECLARE_GLOBAL_DATA_PTR; /*------------------------------------------------------------------ diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index c217c88e59..5dfb02f470 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -27,7 +27,7 @@ */ #include -#include +#include #if defined(CONFIG_CPU_V6) /* @@ -89,12 +89,12 @@ #define TIMEOUT_COUNT 0x4000000 -int arm_dcc_init(void) +static int arm_dcc_init(void) { return 0; } -int arm_dcc_getc(void) +static int arm_dcc_getc(void) { int ch; register unsigned int reg; @@ -107,7 +107,7 @@ int arm_dcc_getc(void) return ch; } -void arm_dcc_putc(char ch) +static void arm_dcc_putc(char ch) { register unsigned int reg; unsigned int timeout_count = TIMEOUT_COUNT; @@ -123,13 +123,7 @@ void arm_dcc_putc(char ch) write_dcc(ch); } -void arm_dcc_puts(const char *s) -{ - while (*s) - arm_dcc_putc(*s++); -} - -int arm_dcc_tstc(void) +static int arm_dcc_tstc(void) { register unsigned int reg; @@ -138,22 +132,27 @@ int arm_dcc_tstc(void) return reg; } -static struct stdio_dev arm_dcc_dev; +static void arm_dcc_setbrg(void) +{ +} -int drv_arm_dcc_init(void) +static struct serial_device arm_dcc_drv = { + .name = "arm_dcc", + .start = arm_dcc_init, + .stop = NULL, + .setbrg = arm_dcc_setbrg, + .putc = arm_dcc_putc, + .puts = default_serial_puts, + .getc = arm_dcc_getc, + .tstc = arm_dcc_tstc, +}; + +void arm_dcc_initialize(void) { - strcpy(arm_dcc_dev.name, "dcc"); - arm_dcc_dev.ext = 0; /* No extensions */ - arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT; - arm_dcc_dev.tstc = arm_dcc_tstc; /* 'tstc' function */ - arm_dcc_dev.getc = arm_dcc_getc; /* 'getc' function */ - arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */ - arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */ - - return stdio_register(&arm_dcc_dev); + serial_register(&arm_dcc_drv); } __weak struct serial_device *default_serial_console(void) { - return NULL; + return &arm_dcc_drv; } diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 8f0e3489a0..4fe992bf2b 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -7,11 +7,16 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include #include #include #include #include +#ifdef CONFIG_DM_SERIAL +#include +#endif #include #include @@ -19,9 +24,9 @@ DECLARE_GLOBAL_DATA_PTR; -static void atmel_serial_setbrg(void) +static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id, + int baudrate) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; unsigned long divisor; unsigned long usart_hz; @@ -30,15 +35,13 @@ static void atmel_serial_setbrg(void) * Baud Rate = -------------- * 16 * CD */ - usart_hz = get_usart_clk_rate(CONFIG_USART_ID); - divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; + usart_hz = get_usart_clk_rate(id); + divisor = (usart_hz / 16 + baudrate / 2) / baudrate; writel(USART3_BF(CD, divisor), &usart->brgr); } -static int atmel_serial_init(void) +static void atmel_serial_init_internal(atmel_usart3_t *usart) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; - /* * Just in case: drain transmitter register * 1000us is enough for baudrate >= 9600 @@ -47,9 +50,10 @@ static int atmel_serial_init(void) __udelay(1000); writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); +} - serial_setbrg(); - +static void atmel_serial_activate(atmel_usart3_t *usart) +{ writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) | USART3_BF(USCLKS, USART3_USCLKS_MCK) | USART3_BF(CHRL, USART3_CHRL_8) @@ -59,6 +63,22 @@ static int atmel_serial_init(void) writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr); /* 100us is enough for the new settings to be settled */ __udelay(100); +} + +#ifndef CONFIG_DM_SERIAL +static void atmel_serial_setbrg(void) +{ + atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE, + CONFIG_USART_ID, gd->baudrate); +} + +static int atmel_serial_init(void) +{ + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + + atmel_serial_init_internal(usart); + serial_setbrg(); + atmel_serial_activate(usart); return 0; } @@ -109,3 +129,81 @@ __weak struct serial_device *default_serial_console(void) { return &atmel_serial_drv; } +#endif + +#ifdef CONFIG_DM_SERIAL + +struct atmel_serial_priv { + atmel_usart3_t *usart; +}; + +int atmel_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + atmel_serial_setbrg_internal(priv->usart, 0 /* ignored */, baudrate); + atmel_serial_activate(priv->usart); + + return 0; +} + +static int atmel_serial_getc(struct udevice *dev) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY))) + return -EAGAIN; + + return readl(&priv->usart->rhr); +} + +static int atmel_serial_putc(struct udevice *dev, const char ch) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY))) + return -EAGAIN; + + writel(ch, &priv->usart->thr); + + return 0; +} + +static int atmel_serial_pending(struct udevice *dev, bool input) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + uint32_t csr = readl(&priv->usart->csr); + + if (input) + return csr & USART3_BIT(RXRDY) ? 1 : 0; + else + return csr & USART3_BIT(TXEMPTY) ? 0 : 1; +} + +static const struct dm_serial_ops atmel_serial_ops = { + .putc = atmel_serial_putc, + .pending = atmel_serial_pending, + .getc = atmel_serial_getc, + .setbrg = atmel_serial_setbrg, +}; + +static int atmel_serial_probe(struct udevice *dev) +{ + struct atmel_serial_platdata *plat = dev->platdata; + struct atmel_serial_priv *priv = dev_get_priv(dev); + + priv->usart = (atmel_usart3_t *)plat->base_addr; + atmel_serial_init_internal(priv->usart); + + return 0; +} + +U_BOOT_DRIVER(serial_atmel) = { + .name = "serial_atmel", + .id = UCLASS_SERIAL, + .probe = atmel_serial_probe, + .ops = &atmel_serial_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct atmel_serial_priv), +}; +#endif diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c index 9c7c6213a5..c8926a8945 100644 --- a/drivers/serial/lpc32xx_hsuart.c +++ b/drivers/serial/lpc32xx_hsuart.c @@ -38,6 +38,9 @@ static int lpc32xx_serial_getc(void) static void lpc32xx_serial_putc(const char c) { + if (c == '\n') + serial_putc('\r'); + writel(c, &hsuart->tx); /* Wait for character to be sent */ diff --git a/drivers/serial/mxs_auart.c b/drivers/serial/mxs_auart.c new file mode 100644 index 0000000000..fc0fa96a0e --- /dev/null +++ b/drivers/serial/mxs_auart.c @@ -0,0 +1,151 @@ +/* + * Freescale i.MX23/i.MX28 AUART driver + * + * Copyright (C) 2013 Andreas Wass + * + * Based on the MXC serial driver: + * + * (c) 2007 Sascha Hauer + * + * Further based on the Linux mxs-auart.c driver: + * + * Freescale STMP37XX/STMP38X Application UART drkiver + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_MXS_AUART_BASE +#error "CONFIG_MXS_AUART_BASE must be set to the base UART to use" +#endif + +/* AUART clock always supplied by XTAL and always 24MHz */ +#define MXS_AUART_CLK 24000000 + +static struct mxs_uartapp_regs *get_uartapp_registers(void) +{ + return (struct mxs_uartapp_regs *)CONFIG_MXS_AUART_BASE; +} + +/** + * Sets the baud rate and settings. + * The settings are: 8 data bits, no parit and 1 stop bit. + */ +static void mxs_auart_setbrg(void) +{ + u32 div; + u32 linectrl = 0; + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + /* + * From i.MX28 datasheet: + * div is calculated by calculating UARTCLK*32/baudrate, rounded to int + * div must be between 0xEC and 0x003FFFC0 inclusive + * Lowest 6 bits of div goes in BAUD_DIVFRAC part of LINECTRL register + * Next 16 bits goes in BAUD_DIVINT part of LINECTRL register + */ + div = (MXS_AUART_CLK * 32) / gd->baudrate; + if (div < 0xEC || div > 0x003FFFC0) + return; + + linectrl |= ((div & UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK) << + UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET) & + UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK; + linectrl |= ((div >> UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET) << + UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET) & + UARTAPP_LINECTRL_BAUD_DIVINT_MASK; + + /* Word length: 8 bits */ + linectrl |= UARTAPP_LINECTRL_WLEN_8BITS; + + /* Enable FIFOs. */ + linectrl |= UARTAPP_LINECTRL_FEN_MASK; + + /* Write above settings, no parity, 1 stop bit */ + writel(linectrl, ®s->hw_uartapp_linectrl); +} + +static int mxs_auart_init(void) +{ + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + /* Reset everything */ + mxs_reset_block(®s->hw_uartapp_ctrl0_reg); + /* Disable interrupts */ + writel(0, ®s->hw_uartapp_intr); + /* Set baud rate and settings */ + serial_setbrg(); + /* Disable RTS and CTS, ignore LINECTRL2 register */ + writel(UARTAPP_CTRL2_RTSEN_MASK | + UARTAPP_CTRL2_CTSEN_MASK | + UARTAPP_CTRL2_USE_LCR2_MASK, + ®s->hw_uartapp_ctrl2_clr); + /* Enable receiver, transmitter and UART */ + writel(UARTAPP_CTRL2_RXE_MASK | + UARTAPP_CTRL2_TXE_MASK | + UARTAPP_CTRL2_UARTEN_MASK, + ®s->hw_uartapp_ctrl2_set); + return 0; +} + +static void mxs_auart_putc(const char c) +{ + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + /* Wait in loop while the transmit FIFO is full */ + while (readl(®s->hw_uartapp_stat) & UARTAPP_STAT_TXFF_MASK) + ; + + writel(c, ®s->hw_uartapp_data); + + if (c == '\n') + mxs_auart_putc('\r'); +} + +static int mxs_auart_tstc(void) +{ + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + /* Checks if receive FIFO is empty */ + return !(readl(®s->hw_uartapp_stat) & UARTAPP_STAT_RXFE_MASK); +} + +static int mxs_auart_getc(void) +{ + struct mxs_uartapp_regs *regs = get_uartapp_registers(); + /* Wait until a character is available to read */ + while (!mxs_auart_tstc()) + ; + /* Read the character from the data register */ + return readl(®s->hw_uartapp_data) & 0xFF; +} + +static struct serial_device mxs_auart_drv = { + .name = "mxs_auart_serial", + .start = mxs_auart_init, + .stop = NULL, + .setbrg = mxs_auart_setbrg, + .putc = mxs_auart_putc, + .puts = default_serial_puts, + .getc = mxs_auart_getc, + .tstc = mxs_auart_tstc, +}; + +void mxs_auart_initialize(void) +{ + serial_register(&mxs_auart_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &mxs_auart_drv; +} diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index d77c25fa9b..70c946249f 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -4,18 +4,26 @@ * modified to use CONFIG_SYS_ISA_MEM and new defines */ -#include +#include +#include +#include +#include #include +#include #include #include #include +DECLARE_GLOBAL_DATA_PTR; + #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ UART_MCR_RTS) /* RTS/DTR */ #define UART_FCRVAL (UART_FCR_FIFO_EN | \ UART_FCR_RXSR | \ UART_FCR_TXSR) /* Clear & enable FIFOs */ + +#ifndef CONFIG_DM_SERIAL #ifdef CONFIG_SYS_NS16550_PORT_MAPPED #define serial_out(x, y) outb(x, (ulong)y) #define serial_in(y) inb((ulong)y) @@ -29,25 +37,112 @@ #define serial_out(x, y) writeb(x, y) #define serial_in(y) readb(y) #endif +#endif /* !CONFIG_DM_SERIAL */ + +#if defined(CONFIG_SOC_KEYSTONE) +#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 +#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) +#undef UART_MCRVAL +#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL +#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) +#else +#define UART_MCRVAL (UART_MCR_RTS) +#endif +#endif #ifndef CONFIG_SYS_NS16550_IER #define CONFIG_SYS_NS16550_IER 0x00 #endif /* CONFIG_SYS_NS16550_IER */ +#ifdef CONFIG_DM_SERIAL +static void ns16550_writeb(NS16550_t port, int offset, int value) +{ + struct ns16550_platdata *plat = port->plat; + unsigned char *addr; + + offset *= 1 << plat->reg_shift; + addr = map_sysmem(plat->base, 0) + offset; + /* + * As far as we know it doesn't make sense to support selection of + * these options at run-time, so use the existing CONFIG options. + */ +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + outb(value, (ulong)addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) + out_le32(addr, value); +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) + out_be32(addr, value); +#elif defined(CONFIG_SYS_BIG_ENDIAN) + writeb(value, addr + (1 << plat->reg_shift) - 1); +#else + writeb(value, addr); +#endif +} + +static int ns16550_readb(NS16550_t port, int offset) +{ + struct ns16550_platdata *plat = port->plat; + unsigned char *addr; + + offset *= 1 << plat->reg_shift; + addr = map_sysmem(plat->base, 0) + offset; +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + return inb((ulong)addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) + return in_le32(addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) + return in_be32(addr); +#elif defined(CONFIG_SYS_BIG_ENDIAN) + return readb(addr + (1 << plat->reg_shift) - 1); +#else + return readb(addr); +#endif +} + +/* We can clean these up once everything is moved to driver model */ +#define serial_out(value, addr) \ + ns16550_writeb(com_port, addr - (unsigned char *)com_port, value) +#define serial_in(addr) \ + ns16550_readb(com_port, addr - (unsigned char *)com_port) +#endif + +int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) +{ + const unsigned int mode_x_div = 16; + +#ifdef CONFIG_OMAP1510 + /* If can't cleanly clock 115200 set div to 1 */ + if ((clock == 12000000) && (baudrate == 115200)) { + port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ + return 1; /* return 1 for base divisor */ + } + port->osc_12m_sel = 0; /* clear if previsouly set */ +#endif + + return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); +} + +static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) +{ + serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + serial_out(baud_divisor & 0xff, &com_port->dll); + serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); +} + void NS16550_init(NS16550_t com_port, int baud_divisor) { -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX)) +#if (defined(CONFIG_SPL_BUILD) && \ + (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) /* - * On some OMAP3 devices when UART3 is configured for boot mode before - * SPL starts only THRE bit is set. We have to empty the transmitter - * before initialization starts. + * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode + * before SPL starts only THRE bit is set. We have to empty the + * transmitter before initialization starts. */ if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) == UART_LSR_THRE) { - serial_out(UART_LCR_DLAB, &com_port->lcr); - serial_out(baud_divisor & 0xff, &com_port->dll); - serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); - serial_out(UART_LCRVAL, &com_port->lcr); + if (baud_divisor != -1) + NS16550_setbrg(com_port, baud_divisor); serial_out(0, &com_port->mdr1); } #endif @@ -56,43 +151,35 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_TI814X) +#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \ + defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif - serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); - serial_out(0, &com_port->dll); - serial_out(0, &com_port->dlm); - serial_out(UART_LCRVAL, &com_port->lcr); + NS16550_setbrg(com_port, 0); serial_out(UART_MCRVAL, &com_port->mcr); serial_out(UART_FCRVAL, &com_port->fcr); - serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); - serial_out(baud_divisor & 0xff, &com_port->dll); - serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); - serial_out(UART_LCRVAL, &com_port->lcr); -#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ + if (baud_divisor != -1) + NS16550_setbrg(com_port, baud_divisor); +#if defined(CONFIG_OMAP) || \ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ - defined(CONFIG_TI814X) + defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif /* CONFIG_OMAP */ +#if defined(CONFIG_SOC_KEYSTONE) + serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); +#endif } #ifndef CONFIG_NS16550_MIN_FUNCTIONS void NS16550_reinit(NS16550_t com_port, int baud_divisor) { serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); - serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); - serial_out(0, &com_port->dll); - serial_out(0, &com_port->dlm); - serial_out(UART_LCRVAL, &com_port->lcr); + NS16550_setbrg(com_port, 0); serial_out(UART_MCRVAL, &com_port->mcr); serial_out(UART_FCRVAL, &com_port->fcr); - serial_out(UART_LCR_BKSE, &com_port->lcr); - serial_out(baud_divisor & 0xff, &com_port->dll); - serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); - serial_out(UART_LCRVAL, &com_port->lcr); + NS16550_setbrg(com_port, baud_divisor); } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ @@ -131,3 +218,124 @@ int NS16550_tstc(NS16550_t com_port) } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ + +#ifdef CONFIG_DM_SERIAL +static int ns16550_serial_putc(struct udevice *dev, const char ch) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + + if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) + return -EAGAIN; + serial_out(ch, &com_port->thr); + + /* + * Call watchdog_reset() upon newline. This is done here in putc + * since the environment code uses a single puts() to print the complete + * environment upon "printenv". So we can't put this watchdog call + * in puts(). + */ + if (ch == '\n') + WATCHDOG_RESET(); + + return 0; +} + +static int ns16550_serial_pending(struct udevice *dev, bool input) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + + if (input) + return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0; + else + return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1; +} + +static int ns16550_serial_getc(struct udevice *dev) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + + if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) + return -EAGAIN; + + return serial_in(&com_port->rbr); +} + +static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + struct ns16550_platdata *plat = com_port->plat; + int clock_divisor; + + clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); + + NS16550_setbrg(com_port, clock_divisor); + + return 0; +} + +int ns16550_serial_probe(struct udevice *dev) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + + com_port->plat = dev_get_platdata(dev); + NS16550_init(com_port, -1); + + return 0; +} + +#ifdef CONFIG_OF_CONTROL +int ns16550_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev->platdata; + fdt_addr_t addr; + + /* try Processor Local Bus device first */ + addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); +#ifdef CONFIG_PCI + if (addr == FDT_ADDR_T_NONE) { + /* then try pci device */ + struct fdt_pci_addr pci_addr; + u32 bar; + int ret; + + /* we prefer to use a memory-mapped register */ + ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, + FDT_PCI_SPACE_MEM32, "reg", + &pci_addr); + if (ret) { + /* try if there is any i/o-mapped register */ + ret = fdtdec_get_pci_addr(gd->fdt_blob, + dev->of_offset, + FDT_PCI_SPACE_IO, + "reg", &pci_addr); + if (ret) + return ret; + } + + ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset, + &pci_addr, &bar); + if (ret) + return ret; + + addr = bar; + } +#endif + + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = addr; + plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "reg-shift", 1); + + return 0; +} +#endif + +const struct dm_serial_ops ns16550_serial_ops = { + .putc = ns16550_serial_putc, + .pending = ns16550_serial_pending, + .getc = ns16550_serial_getc, + .setbrg = ns16550_serial_setbrg, +}; +#endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index 8de2eca2ac..f68c8d0f04 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -1,4 +1,8 @@ /* + * Altera NiosII YANU serial interface by Imagos + * please see http://www.opencores.org/project,yanu for + * information/downloads + * * Copyright 2010, Renato Andreola * * SPDX-License-Identifier: GPL-2.0+ @@ -7,7 +11,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -15,64 +19,118 @@ DECLARE_GLOBAL_DATA_PTR; /* YANU Imagos serial port */ /*-----------------------------------------------------------------*/ -static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; +#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ +#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ +#define YANU_FIFO_SIZE (16) +#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) +#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) + +#define YANU_RXFIFO_DLY (10*11) +#define YANU_TXFIFO_THR (10) +#define YANU_DATA_CHAR_MASK (0xFF) + +/* data register */ +#define YANU_DATA_OFFSET (0) /* data register offset */ + +#define YANU_CONTROL_OFFSET (4) /* control register offset */ +/* interrupt enable */ +#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ +#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ +#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ +#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ +#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ +#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ +/* control bits */ +#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ +#define YANU_CONTROL_BITS (1<= 0; n--) { - if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - (unsigned)CONFIG_BAUDRATE) { - best_n = n; - break; - } - } - for (k = 0;; k++) { - if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k))) - break; - } - best_m = - ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) / - ((unsigned)CONFIG_SYS_CLK_FREQ >> k); - - baud = best_m + best_n * YANU_BAUDE; - writel(baud, &uart->baud); - - return; -} - +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + /* Everything's already setup for fixed-baud PTF assignment */ + baudrate = CONFIG_BAUDRATE; #else - -static void oc_serial_setbrg(void) -{ - int n, k; - const unsigned max_uns = 0xFFFFFFFF; - unsigned best_n, best_m, baud; - + baudrate = gd->baudrate; +#endif /* compute best N and M couple */ best_n = YANU_MAX_PRESCALER_N; for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - gd->baudrate) { + baudrate) { best_n = n; break; } } for (k = 0;; k++) { - if (gd->baudrate <= (max_uns >> (15+n-k))) + if (baudrate <= (max_uns >> (15+n-k))) break; } best_m = - (gd->baudrate * (1 << (15 + n - k))) / + (baudrate * (1 << (15 + n - k))) / ((unsigned)CONFIG_SYS_CLK_FREQ >> k); baud = best_m + best_n * YANU_BAUDE; @@ -81,9 +139,6 @@ static void oc_serial_setbrg(void) return; } - -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - static int oc_serial_init(void) { unsigned action,control; @@ -154,7 +209,7 @@ static int oc_serial_tstc(void) ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); } -statoc int oc_serial_getc(void) +static int oc_serial_getc(void) { while (serial_tstc() == 0) WATCHDOG_RESET (); diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index ffff5e1497..cd2f91e28e 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -11,9 +11,15 @@ */ #include +#include +#include +#include #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; /* * @@ -28,24 +34,69 @@ static char serial_buf[16]; static unsigned int serial_buf_write; static unsigned int serial_buf_read; -static int sandbox_serial_init(void) +struct sandbox_serial_platdata { + int colour; /* Text colour to use for output, -1 for none */ +}; + +struct sandbox_serial_priv { + bool start_of_line; +}; + +/** + * output_ansi_colour() - Output an ANSI colour code + * + * @colour: Colour to output (0-7) + */ +static void output_ansi_colour(int colour) { - os_tty_raw(0); - return 0; + char ansi_code[] = "\x1b[1;3Xm"; + + ansi_code[5] = '0' + colour; + os_write(1, ansi_code, sizeof(ansi_code) - 1); } -static void sandbox_serial_setbrg(void) +static void output_ansi_reset(void) { + os_write(1, "\x1b[0m", 4); } -static void sandbox_serial_putc(const char ch) +static int sandbox_serial_probe(struct udevice *dev) { - os_write(1, &ch, 1); + struct sandbox_state *state = state_get_current(); + struct sandbox_serial_priv *priv = dev_get_priv(dev); + + if (state->term_raw != STATE_TERM_COOKED) + os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS); + priv->start_of_line = 0; + + return 0; } -static void sandbox_serial_puts(const char *str) +static int sandbox_serial_remove(struct udevice *dev) { - os_write(1, str, strlen(str)); + struct sandbox_serial_platdata *plat = dev->platdata; + + if (plat->colour != -1) + output_ansi_reset(); + + return 0; +} + +static int sandbox_serial_putc(struct udevice *dev, const char ch) +{ + struct sandbox_serial_priv *priv = dev_get_priv(dev); + struct sandbox_serial_platdata *plat = dev->platdata; + + if (priv->start_of_line && plat->colour != -1) { + priv->start_of_line = false; + output_ansi_colour(plat->colour); + } + + os_write(1, &ch, 1); + if (ch == '\n') + priv->start_of_line = true; + + return 0; } static unsigned int increment_buffer_index(unsigned int index) @@ -53,51 +104,96 @@ static unsigned int increment_buffer_index(unsigned int index) return (index + 1) % ARRAY_SIZE(serial_buf); } -static int sandbox_serial_tstc(void) +static int sandbox_serial_pending(struct udevice *dev, bool input) { const unsigned int next_index = increment_buffer_index(serial_buf_write); ssize_t count; + if (!input) + return 0; + os_usleep(100); +#ifdef CONFIG_LCD + lcd_sync(); +#endif if (next_index == serial_buf_read) return 1; /* buffer full */ count = os_read_no_block(0, &serial_buf[serial_buf_write], 1); if (count == 1) serial_buf_write = next_index; + return serial_buf_write != serial_buf_read; } -static int sandbox_serial_getc(void) +static int sandbox_serial_getc(struct udevice *dev) { int result; - while (!sandbox_serial_tstc()) - ; /* buffer empty */ + if (!sandbox_serial_pending(dev, true)) + return -EAGAIN; /* buffer empty */ result = serial_buf[serial_buf_read]; serial_buf_read = increment_buffer_index(serial_buf_read); return result; } -static struct serial_device sandbox_serial_drv = { - .name = "sandbox_serial", - .start = sandbox_serial_init, - .stop = NULL, - .setbrg = sandbox_serial_setbrg, - .putc = sandbox_serial_putc, - .puts = sandbox_serial_puts, - .getc = sandbox_serial_getc, - .tstc = sandbox_serial_tstc, +static const char * const ansi_colour[] = { + "black", "red", "green", "yellow", "blue", "megenta", "cyan", + "white", }; -void sandbox_serial_initialize(void) +static int sandbox_serial_ofdata_to_platdata(struct udevice *dev) { - serial_register(&sandbox_serial_drv); -} + struct sandbox_serial_platdata *plat = dev->platdata; + const char *colour; + int i; + + plat->colour = -1; + colour = fdt_getprop(gd->fdt_blob, dev->of_offset, + "sandbox,text-colour", NULL); + if (colour) { + for (i = 0; i < ARRAY_SIZE(ansi_colour); i++) { + if (!strcmp(colour, ansi_colour[i])) { + plat->colour = i; + break; + } + } + } -__weak struct serial_device *default_serial_console(void) -{ - return &sandbox_serial_drv; + return 0; } + +static const struct dm_serial_ops sandbox_serial_ops = { + .putc = sandbox_serial_putc, + .pending = sandbox_serial_pending, + .getc = sandbox_serial_getc, +}; + +static const struct udevice_id sandbox_serial_ids[] = { + { .compatible = "sandbox,serial" }, + { } +}; + +U_BOOT_DRIVER(serial_sandbox) = { + .name = "serial_sandbox", + .id = UCLASS_SERIAL, + .of_match = sandbox_serial_ids, + .ofdata_to_platdata = sandbox_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sandbox_serial_platdata), + .priv_auto_alloc_size = sizeof(struct sandbox_serial_priv), + .probe = sandbox_serial_probe, + .remove = sandbox_serial_remove, + .ops = &sandbox_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +static const struct sandbox_serial_platdata platdata_non_fdt = { + .colour = -1, +}; + +U_BOOT_DEVICE(serial_sandbox_non_fdt) = { + .name = "serial_sandbox", + .platdata = &platdata_non_fdt, +}; diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c new file mode 100644 index 0000000000..9131a8f93d --- /dev/null +++ b/drivers/serial/serial-uclass.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Table with supported baudrates (defined in config_xyz.h) + */ +static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; + +#ifndef CONFIG_SYS_MALLOC_F_LEN +#error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work" +#endif + +static void serial_find_console_or_panic(void) +{ + struct udevice *dev; + +#ifdef CONFIG_OF_CONTROL + int node; + + /* Check for a chosen console */ + node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path"); + if (node < 0) + node = fdt_path_offset(gd->fdt_blob, "console"); + if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) { + gd->cur_serial_dev = dev; + return; + } + + /* + * If the console is not marked to be bound before relocation, bind + * it anyway. + */ + if (node > 0 && + !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) { + if (!device_probe(dev)) { + gd->cur_serial_dev = dev; + return; + } + } +#endif + /* + * Try to use CONFIG_CONS_INDEX if available (it is numbered from 1!). + * + * Failing that, get the device with sequence number 0, or in extremis + * just the first serial device we can find. But we insist on having + * a console (even if it is silent). + */ +#ifdef CONFIG_CONS_INDEX +#define INDEX (CONFIG_CONS_INDEX - 1) +#else +#define INDEX 0 +#endif + if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) && + uclass_get_device(UCLASS_SERIAL, INDEX, &dev) && + (uclass_first_device(UCLASS_SERIAL, &dev) || !dev)) + panic("No serial driver found"); +#undef INDEX + gd->cur_serial_dev = dev; +} + +/* Called prior to relocation */ +int serial_init(void) +{ + serial_find_console_or_panic(); + gd->flags |= GD_FLG_SERIAL_READY; + + return 0; +} + +/* Called after relocation */ +void serial_initialize(void) +{ + serial_find_console_or_panic(); +} + +static void _serial_putc(struct udevice *dev, char ch) +{ + struct dm_serial_ops *ops = serial_get_ops(dev); + int err; + + do { + err = ops->putc(dev, ch); + } while (err == -EAGAIN); + if (ch == '\n') + _serial_putc(dev, '\r'); +} + +static void _serial_puts(struct udevice *dev, const char *str) +{ + while (*str) + _serial_putc(dev, *str++); +} + +static int _serial_getc(struct udevice *dev) +{ + struct dm_serial_ops *ops = serial_get_ops(dev); + int err; + + do { + err = ops->getc(dev); + if (err == -EAGAIN) + WATCHDOG_RESET(); + } while (err == -EAGAIN); + + return err >= 0 ? err : 0; +} + +static int _serial_tstc(struct udevice *dev) +{ + struct dm_serial_ops *ops = serial_get_ops(dev); + + if (ops->pending) + return ops->pending(dev, true); + + return 1; +} + +void serial_putc(char ch) +{ + _serial_putc(gd->cur_serial_dev, ch); +} + +void serial_puts(const char *str) +{ + _serial_puts(gd->cur_serial_dev, str); +} + +int serial_getc(void) +{ + return _serial_getc(gd->cur_serial_dev); +} + +int serial_tstc(void) +{ + return _serial_tstc(gd->cur_serial_dev); +} + +void serial_setbrg(void) +{ + struct dm_serial_ops *ops = serial_get_ops(gd->cur_serial_dev); + + if (ops->setbrg) + ops->setbrg(gd->cur_serial_dev, gd->baudrate); +} + +void serial_stdio_init(void) +{ +} + +#ifdef CONFIG_DM_STDIO +static void serial_stub_putc(struct stdio_dev *sdev, const char ch) +{ + _serial_putc(sdev->priv, ch); +} +#endif + +void serial_stub_puts(struct stdio_dev *sdev, const char *str) +{ + _serial_puts(sdev->priv, str); +} + +int serial_stub_getc(struct stdio_dev *sdev) +{ + return _serial_getc(sdev->priv); +} + +int serial_stub_tstc(struct stdio_dev *sdev) +{ + return _serial_tstc(sdev->priv); +} + +/** + * on_baudrate() - Update the actual baudrate when the env var changes + * + * This will check for a valid baudrate and only apply it if valid. + */ +static int on_baudrate(const char *name, const char *value, enum env_op op, + int flags) +{ + int i; + int baudrate; + + switch (op) { + case env_op_create: + case env_op_overwrite: + /* + * Switch to new baudrate if new baudrate is supported + */ + baudrate = simple_strtoul(value, NULL, 10); + + /* Not actually changing */ + if (gd->baudrate == baudrate) + return 0; + + for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) { + if (baudrate == baudrate_table[i]) + break; + } + if (i == ARRAY_SIZE(baudrate_table)) { + if ((flags & H_FORCE) == 0) + printf("## Baudrate %d bps not supported\n", + baudrate); + return 1; + } + if ((flags & H_INTERACTIVE) != 0) { + printf("## Switch baudrate to %d bps and press ENTER ...\n", + baudrate); + udelay(50000); + } + + gd->baudrate = baudrate; + + serial_setbrg(); + + udelay(50000); + + if ((flags & H_INTERACTIVE) != 0) + while (1) { + if (getc() == '\r') + break; + } + + return 0; + case env_op_delete: + printf("## Baudrate may not be deleted\n"); + return 1; + default: + return 0; + } +} +U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); + +static int serial_post_probe(struct udevice *dev) +{ + struct dm_serial_ops *ops = serial_get_ops(dev); +#ifdef CONFIG_DM_STDIO + struct serial_dev_priv *upriv = dev->uclass_priv; + struct stdio_dev sdev; +#endif + int ret; + + /* Set the baud rate */ + if (ops->setbrg) { + ret = ops->setbrg(dev, gd->baudrate); + if (ret) + return ret; + } + +#ifdef CONFIG_DM_STDIO + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + memset(&sdev, '\0', sizeof(sdev)); + + strncpy(sdev.name, dev->name, sizeof(sdev.name)); + sdev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; + sdev.priv = dev; + sdev.putc = serial_stub_putc; + sdev.puts = serial_stub_puts; + sdev.getc = serial_stub_getc; + sdev.tstc = serial_stub_tstc; + stdio_register_dev(&sdev, &upriv->sdev); +#endif + return 0; +} + +static int serial_pre_remove(struct udevice *dev) +{ +#ifdef CONFIG_SYS_STDIO_DEREGISTER + struct serial_dev_priv *upriv = dev->uclass_priv; + + if (stdio_deregister_dev(upriv->sdev, 0)) + return -EPERM; +#endif + + return 0; +} + +UCLASS_DRIVER(serial) = { + .id = UCLASS_SERIAL, + .name = "serial", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .post_probe = serial_post_probe, + .pre_remove = serial_pre_remove, + .per_device_auto_alloc_size = sizeof(struct serial_dev_priv), +}; diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 67301355d7..95c992a5a3 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -74,9 +74,6 @@ static int on_baudrate(const char *name, const char *value, enum env_op op, } gd->baudrate = baudrate; -#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2) - gd->bd->bi_baudrate = baudrate; -#endif serial_setbrg(); @@ -112,53 +109,54 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); void name(void) \ __attribute__((weak, alias("serial_null"))); -serial_initfunc(mpc8xx_serial_initialize); -serial_initfunc(ns16550_serial_initialize); -serial_initfunc(pxa_serial_initialize); -serial_initfunc(s3c24xx_serial_initialize); -serial_initfunc(s5p_serial_initialize); -serial_initfunc(zynq_serial_initalize); -serial_initfunc(bfin_serial_initialize); -serial_initfunc(bfin_jtag_initialize); -serial_initfunc(mpc512x_serial_initialize); -serial_initfunc(uartlite_serial_initialize); -serial_initfunc(au1x00_serial_initialize); -serial_initfunc(asc_serial_initialize); -serial_initfunc(jz_serial_initialize); -serial_initfunc(mpc5xx_serial_initialize); -serial_initfunc(mpc8260_scc_serial_initialize); -serial_initfunc(mpc8260_smc_serial_initialize); -serial_initfunc(mpc85xx_serial_initialize); -serial_initfunc(iop480_serial_initialize); -serial_initfunc(leon2_serial_initialize); -serial_initfunc(leon3_serial_initialize); -serial_initfunc(marvell_serial_initialize); +serial_initfunc(altera_jtag_serial_initialize); +serial_initfunc(altera_serial_initialize); serial_initfunc(amirix_serial_initialize); +serial_initfunc(arc_serial_initialize); +serial_initfunc(arm_dcc_initialize); +serial_initfunc(asc_serial_initialize); +serial_initfunc(atmel_serial_initialize); +serial_initfunc(au1x00_serial_initialize); +serial_initfunc(bfin_jtag_initialize); +serial_initfunc(bfin_serial_initialize); serial_initfunc(bmw_serial_initialize); +serial_initfunc(clps7111_serial_initialize); serial_initfunc(cogent_serial_initialize); serial_initfunc(cpci750_serial_initialize); serial_initfunc(evb64260_serial_initialize); -serial_initfunc(ml2_serial_initialize); -serial_initfunc(sconsole_serial_initialize); -serial_initfunc(p3mx_serial_initialize); -serial_initfunc(altera_jtag_serial_initialize); -serial_initfunc(altera_serial_initialize); -serial_initfunc(atmel_serial_initialize); -serial_initfunc(lpc32xx_serial_initialize); -serial_initfunc(mcf_serial_initialize); -serial_initfunc(oc_serial_initialize); -serial_initfunc(sandbox_serial_initialize); -serial_initfunc(clps7111_serial_initialize); serial_initfunc(imx_serial_initialize); -serial_initfunc(ixp_serial_initialize); +serial_initfunc(iop480_serial_initialize); +serial_initfunc(jz_serial_initialize); serial_initfunc(ks8695_serial_initialize); +serial_initfunc(leon2_serial_initialize); +serial_initfunc(leon3_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); +serial_initfunc(lpc32xx_serial_initialize); +serial_initfunc(marvell_serial_initialize); serial_initfunc(max3100_serial_initialize); +serial_initfunc(mcf_serial_initialize); +serial_initfunc(ml2_serial_initialize); +serial_initfunc(mpc512x_serial_initialize); +serial_initfunc(mpc5xx_serial_initialize); +serial_initfunc(mpc8260_scc_serial_initialize); +serial_initfunc(mpc8260_smc_serial_initialize); +serial_initfunc(mpc85xx_serial_initialize); +serial_initfunc(mpc8xx_serial_initialize); serial_initfunc(mxc_serial_initialize); +serial_initfunc(mxs_auart_initialize); +serial_initfunc(ns16550_serial_initialize); +serial_initfunc(oc_serial_initialize); +serial_initfunc(p3mx_serial_initialize); serial_initfunc(pl01x_serial_initialize); -serial_initfunc(s3c44b0_serial_initialize); +serial_initfunc(pxa_serial_initialize); +serial_initfunc(s3c24xx_serial_initialize); +serial_initfunc(s5p_serial_initialize); serial_initfunc(sa1100_serial_initialize); +serial_initfunc(sandbox_serial_initialize); +serial_initfunc(sconsole_serial_initialize); serial_initfunc(sh_serial_initialize); +serial_initfunc(uartlite_serial_initialize); +serial_initfunc(zynq_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -204,57 +202,100 @@ void serial_register(struct serial_device *dev) */ void serial_initialize(void) { - mpc8xx_serial_initialize(); - ns16550_serial_initialize(); - pxa_serial_initialize(); - s3c24xx_serial_initialize(); - s5p_serial_initialize(); - mpc512x_serial_initialize(); - bfin_serial_initialize(); - bfin_jtag_initialize(); - uartlite_serial_initialize(); - zynq_serial_initalize(); - au1x00_serial_initialize(); - asc_serial_initialize(); - jz_serial_initialize(); - mpc5xx_serial_initialize(); - mpc8260_scc_serial_initialize(); - mpc8260_smc_serial_initialize(); - mpc85xx_serial_initialize(); - iop480_serial_initialize(); - leon2_serial_initialize(); - leon3_serial_initialize(); - marvell_serial_initialize(); + altera_jtag_serial_initialize(); + altera_serial_initialize(); amirix_serial_initialize(); + arc_serial_initialize(); + arm_dcc_initialize(); + asc_serial_initialize(); + atmel_serial_initialize(); + au1x00_serial_initialize(); + bfin_jtag_initialize(); + bfin_serial_initialize(); bmw_serial_initialize(); + clps7111_serial_initialize(); cogent_serial_initialize(); cpci750_serial_initialize(); evb64260_serial_initialize(); - ml2_serial_initialize(); - sconsole_serial_initialize(); - p3mx_serial_initialize(); - altera_jtag_serial_initialize(); - altera_serial_initialize(); - atmel_serial_initialize(); - lpc32xx_serial_initialize(); - mcf_serial_initialize(); - oc_serial_initialize(); - sandbox_serial_initialize(); - clps7111_serial_initialize(); imx_serial_initialize(); - ixp_serial_initialize(); + iop480_serial_initialize(); + jz_serial_initialize(); ks8695_serial_initialize(); + leon2_serial_initialize(); + leon3_serial_initialize(); lh7a40x_serial_initialize(); + lpc32xx_serial_initialize(); + marvell_serial_initialize(); max3100_serial_initialize(); + mcf_serial_initialize(); + ml2_serial_initialize(); + mpc512x_serial_initialize(); + mpc5xx_serial_initialize(); + mpc8260_scc_serial_initialize(); + mpc8260_smc_serial_initialize(); + mpc85xx_serial_initialize(); + mpc8xx_serial_initialize(); mxc_serial_initialize(); + mxs_auart_initialize(); + ns16550_serial_initialize(); + oc_serial_initialize(); + p3mx_serial_initialize(); pl01x_serial_initialize(); - s3c44b0_serial_initialize(); + pxa_serial_initialize(); + s3c24xx_serial_initialize(); + s5p_serial_initialize(); sa1100_serial_initialize(); + sandbox_serial_initialize(); + sconsole_serial_initialize(); sh_serial_initialize(); + uartlite_serial_initialize(); + zynq_serial_initialize(); serial_assign(default_serial_console()->name); } +static int serial_stub_start(struct stdio_dev *sdev) +{ + struct serial_device *dev = sdev->priv; + + return dev->start(); +} + +static int serial_stub_stop(struct stdio_dev *sdev) +{ + struct serial_device *dev = sdev->priv; + + return dev->stop(); +} + +static void serial_stub_putc(struct stdio_dev *sdev, const char ch) +{ + struct serial_device *dev = sdev->priv; + + dev->putc(ch); +} + +static void serial_stub_puts(struct stdio_dev *sdev, const char *str) +{ + struct serial_device *dev = sdev->priv; + + dev->puts(str); +} + +int serial_stub_getc(struct stdio_dev *sdev) +{ + struct serial_device *dev = sdev->priv; + + return dev->getc(); +} + +int serial_stub_tstc(struct stdio_dev *sdev) +{ + struct serial_device *dev = sdev->priv; + + return dev->tstc(); +} + /** * serial_stdio_init() - Register serial ports with STDIO core * @@ -273,12 +314,13 @@ void serial_stdio_init(void) strcpy(dev.name, s->name); dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; - dev.start = s->start; - dev.stop = s->stop; - dev.putc = s->putc; - dev.puts = s->puts; - dev.getc = s->getc; - dev.tstc = s->tstc; + dev.start = serial_stub_start; + dev.stop = serial_stub_stop; + dev.putc = serial_stub_putc; + dev.puts = serial_stub_puts; + dev.getc = serial_stub_getc; + dev.tstc = serial_stub_tstc; + dev.priv = s; stdio_register(&dev); @@ -377,6 +419,7 @@ static struct serial_device *get_current(void) */ int serial_init(void) { + gd->flags |= GD_FLG_SERIAL_READY; return get_current()->start(); } @@ -500,12 +543,11 @@ int uart_post_test(int flags) unsigned char c; int ret, saved_baud, b; struct serial_device *saved_dev, *s; - bd_t *bd = gd->bd; /* Save current serial state */ ret = 0; saved_dev = serial_current; - saved_baud = bd->bi_baudrate; + saved_baud = gd->baudrate; for (s = serial_devices; s; s = s->next) { /* If this driver doesn't support loop back, skip it */ @@ -528,7 +570,7 @@ int uart_post_test(int flags) /* Test every available baud rate */ for (b = 0; b < ARRAY_SIZE(bauds); ++b) { - bd->bi_baudrate = bauds[b]; + gd->baudrate = bauds[b]; serial_setbrg(); /* @@ -570,7 +612,7 @@ int uart_post_test(int flags) done: /* Restore previous serial state */ serial_current = saved_dev; - bd->bi_baudrate = saved_baud; + gd->baudrate = saved_baud; serial_reinit_all(); serial_setbrg(); diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c new file mode 100644 index 0000000000..2ddbf32a50 --- /dev/null +++ b/drivers/serial/serial_arc.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct arc_serial_regs { + unsigned int id0; + unsigned int id1; + unsigned int id2; + unsigned int id3; + unsigned int data; + unsigned int status; + unsigned int baudl; + unsigned int baudh; +}; + +/* Bit definitions of STATUS register */ +#define UART_RXEMPTY (1 << 5) +#define UART_OVERFLOW_ERR (1 << 1) +#define UART_TXEMPTY (1 << 7) + +struct arc_serial_regs *regs; + +static void arc_serial_setbrg(void) +{ + int arc_console_baud; + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1; + writeb(arc_console_baud & 0xff, ®s->baudl); + +#ifdef CONFIG_ARC + /* + * UART ISS(Instruction Set simulator) emulation has a subtle bug: + * A existing value of Baudh = 0 is used as a indication to startup + * it's internal state machine. + * Thus if baudh is set to 0, 2 times, it chokes. + * This happens with BAUD=115200 and the formaula above + * Until that is fixed, when running on ISS, we will set baudh to !0 + */ + if (gd->arch.running_on_hw) + writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh); + else + writeb(1, ®s->baudh); +#else + writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh); +#endif +} + +static int arc_serial_init(void) +{ + regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE; + serial_setbrg(); + return 0; +} + +static void arc_serial_putc(const char c) +{ + if (c == '\n') + arc_serial_putc('\r'); + + while (!(readb(®s->status) & UART_TXEMPTY)) + ; + + writeb(c, ®s->data); +} + +static int arc_serial_tstc(void) +{ + return !(readb(®s->status) & UART_RXEMPTY); +} + +static int arc_serial_getc(void) +{ + while (!arc_serial_tstc()) + ; + + /* Check for overflow errors */ + if (readb(®s->status) & UART_OVERFLOW_ERR) + return 0; + + return readb(®s->data) & 0xFF; +} + +static struct serial_device arc_serial_drv = { + .name = "arc_serial", + .start = arc_serial_init, + .stop = NULL, + .setbrg = arc_serial_setbrg, + .putc = arc_serial_putc, + .puts = default_serial_puts, + .getc = arc_serial_getc, + .tstc = arc_serial_tstc, +}; + +void arc_serial_initialize(void) +{ + serial_register(&arc_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &arc_serial_drv; +} diff --git a/drivers/serial/serial_dw.c b/drivers/serial/serial_dw.c new file mode 100644 index 0000000000..a348f2956a --- /dev/null +++ b/drivers/serial/serial_dw.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id dw_serial_ids[] = { + { .compatible = "snps,dw-apb-uart" }, + { } +}; + +static int dw_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + plat->clock = CONFIG_SYS_NS16550_CLK; + + return 0; +} + +U_BOOT_DRIVER(serial_ns16550) = { + .name = "serial_dw", + .id = UCLASS_SERIAL, + .of_match = dw_serial_ids, + .ofdata_to_platdata = dw_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, +}; diff --git a/drivers/serial/serial_ixp.c b/drivers/serial/serial_ixp.c deleted file mode 100644 index b9d0f5bfa5..0000000000 --- a/drivers/serial/serial_ixp.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * 14.7456 MHz - * Baud Rate = -------------- - * 16 x Divisor - */ -#define SERIAL_CLOCK 921600 - -DECLARE_GLOBAL_DATA_PTR; - -static void ixp_serial_setbrg(void) -{ - unsigned int quot = 0; - int uart = CONFIG_SYS_IXP425_CONSOLE; - - if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0)) - quot = SERIAL_CLOCK / gd->baudrate; - else - hang (); - - IER(uart) = 0; /* Disable for now */ - FCR(uart) = 0; /* No fifos enabled */ - - /* set baud rate */ - LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - DLL(uart) = quot & 0xff; - DLH(uart) = quot >> 8; - LCR(uart) = LCR_WLS0 | LCR_WLS1; -#ifdef CONFIG_SERIAL_RTS_ACTIVE - MCR(uart) = MCR_RTS; /* set RTS active */ -#else - MCR(uart) = 0; /* set RTS inactive */ -#endif - IER(uart) = IER_UUE; -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int ixp_serial_init(void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void ixp_serial_putc(const char c) -{ - /* wait for room in the tx FIFO on UART */ - while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ - - THR(CONFIG_SYS_IXP425_CONSOLE) = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int ixp_serial_tstc(void) -{ - return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int ixp_serial_getc(void) -{ - while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR)) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ - - return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff; -} - -static struct serial_device ixp_serial_drv = { - .name = "ixp_serial", - .start = ixp_serial_init, - .stop = NULL, - .setbrg = ixp_serial_setbrg, - .putc = ixp_serial_putc, - .puts = default_serial_puts, - .getc = ixp_serial_getc, - .tstc = ixp_serial_tstc, -}; - -void ixp_serial_initialize(void) -{ - serial_register(&ixp_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &ixp_serial_drv; -} diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index da5f9a21f4..63fc388b26 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -14,13 +14,42 @@ #define US1_TDRE (1 << 7) #define US1_RDRF (1 << 5) +#define US1_OR (1 << 3) #define UC2_TE (1 << 3) #define UC2_RE (1 << 2) +#define CFIFO_TXFLUSH (1 << 7) +#define CFIFO_RXFLUSH (1 << 6) +#define SFIFO_RXOF (1 << 2) +#define SFIFO_RXUF (1 << 0) + +#define STAT_LBKDIF (1 << 31) +#define STAT_RXEDGIF (1 << 30) +#define STAT_TDRE (1 << 23) +#define STAT_RDRF (1 << 21) +#define STAT_IDLE (1 << 20) +#define STAT_OR (1 << 19) +#define STAT_NF (1 << 18) +#define STAT_FE (1 << 17) +#define STAT_PF (1 << 16) +#define STAT_MA1F (1 << 15) +#define STAT_MA2F (1 << 14) +#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \ + STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F) + +#define CTRL_TE (1 << 19) +#define CTRL_RE (1 << 18) + +#define FIFO_TXFE 0x80 +#define FIFO_RXFE 0x40 + +#define WATER_TXWATER_OFF 1 +#define WATER_RXWATER_OFF 16 DECLARE_GLOBAL_DATA_PTR; struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE; +#ifndef CONFIG_LPUART_32B_REG static void lpuart_serial_setbrg(void) { u32 clk = mxc_get_clock(MXC_UART_CLK); @@ -38,14 +67,10 @@ static void lpuart_serial_setbrg(void) static int lpuart_serial_getc(void) { - u8 status; - - while (!(__raw_readb(&base->us1) & US1_RDRF)) + while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) WATCHDOG_RESET(); - status = __raw_readb(&base->us1); - status |= US1_RDRF; - __raw_writeb(status, &base->us1); + barrier(); return __raw_readb(&base->ud); } @@ -88,6 +113,12 @@ static int lpuart_serial_init(void) __raw_writeb(0, &base->umodem); __raw_writeb(0, &base->uc1); + /* Disable FIFO and flush buffer */ + __raw_writeb(0x0, &base->upfifo); + __raw_writeb(0x0, &base->utwfifo); + __raw_writeb(0x1, &base->urwfifo); + __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo); + /* provide data bits, parity, stop bit, etc */ serial_setbrg(); @@ -107,13 +138,107 @@ static struct serial_device lpuart_serial_drv = { .getc = lpuart_serial_getc, .tstc = lpuart_serial_tstc, }; +#else +static void lpuart32_serial_setbrg(void) +{ + u32 clk = CONFIG_SYS_CLK_FREQ; + u32 sbr; + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + sbr = (clk / (16 * gd->baudrate)); + /* place adjustment later - n/32 BRFA */ + + out_be32(&base->baud, sbr); +} + +static int lpuart32_serial_getc(void) +{ + u32 stat; + + while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) { + out_be32(&base->stat, STAT_FLAGS); + WATCHDOG_RESET(); + } + + return in_be32(&base->data) & 0x3ff; +} + +static void lpuart32_serial_putc(const char c) +{ + if (c == '\n') + serial_putc('\r'); + + while (!(in_be32(&base->stat) & STAT_TDRE)) + WATCHDOG_RESET(); + + out_be32(&base->data, c); +} + +/* + * Test whether a character is in the RX buffer + */ +static int lpuart32_serial_tstc(void) +{ + if ((in_be32(&base->water) >> 24) == 0) + return 0; + + return 1; +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +static int lpuart32_serial_init(void) +{ + u8 ctrl; + + ctrl = in_be32(&base->ctrl); + ctrl &= ~CTRL_RE; + ctrl &= ~CTRL_TE; + out_be32(&base->ctrl, ctrl); + + out_be32(&base->modir, 0); + out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); + + out_be32(&base->match, 0); + /* provide data bits, parity, stop bit, etc */ + + serial_setbrg(); + + out_be32(&base->ctrl, CTRL_RE | CTRL_TE); + + return 0; +} + +static struct serial_device lpuart32_serial_drv = { + .name = "lpuart32_serial", + .start = lpuart32_serial_init, + .stop = NULL, + .setbrg = lpuart32_serial_setbrg, + .putc = lpuart32_serial_putc, + .puts = default_serial_puts, + .getc = lpuart32_serial_getc, + .tstc = lpuart32_serial_tstc, +}; +#endif void lpuart_serial_initialize(void) { +#ifdef CONFIG_LPUART_32B_REG + serial_register(&lpuart32_serial_drv); +#else serial_register(&lpuart_serial_drv); +#endif } __weak struct serial_device *default_serial_console(void) { +#ifdef CONFIG_LPUART_32B_REG + return &lpuart32_serial_drv; +#else return &lpuart_serial_drv; +#endif } diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 451e9a228f..a9ca921071 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -5,37 +5,15 @@ */ #include +#include +#include #include #include #include +#include #include #include -#define __REG(x) (*((volatile u32 *)(x))) - -#ifndef CONFIG_MXC_UART_BASE -#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" -#endif - -#define UART_PHYS CONFIG_MXC_UART_BASE - -/* Register definitions */ -#define URXD 0x0 /* Receiver Register */ -#define UTXD 0x40 /* Transmitter Register */ -#define UCR1 0x80 /* Control Register 1 */ -#define UCR2 0x84 /* Control Register 2 */ -#define UCR3 0x88 /* Control Register 3 */ -#define UCR4 0x8c /* Control Register 4 */ -#define UFCR 0x90 /* FIFO Control Register */ -#define USR1 0x94 /* Status Register 1 */ -#define USR2 0x98 /* Status Register 2 */ -#define UESC 0x9c /* Escape Character Register */ -#define UTIM 0xa0 /* Escape Timer Register */ -#define UBIR 0xa4 /* BRM Incremental Register */ -#define UBMR 0xa8 /* BRM Modulator Register */ -#define UBRC 0xac /* Baud Rate Count Register */ -#define UTS 0xb4 /* UART Test Register (mx31) */ - /* UART Control Register Bit Fields.*/ #define URXD_CHARRDY (1<<15) #define URXD_ERR (1<<14) @@ -77,7 +55,7 @@ #define UCR3_DSR (1<<10) /* Data set ready */ #define UCR3_DCD (1<<9) /* Data carrier detect */ #define UCR3_RI (1<<8) /* Ring indicator */ -#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ @@ -128,6 +106,33 @@ #define UTS_RXFULL (1<<3) /* RxFIFO full */ #define UTS_SOFTRST (1<<0) /* Software reset */ +#ifndef CONFIG_DM_SERIAL + +#ifndef CONFIG_MXC_UART_BASE +#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" +#endif + +#define UART_PHYS CONFIG_MXC_UART_BASE + +#define __REG(x) (*((volatile u32 *)(x))) + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + DECLARE_GLOBAL_DATA_PTR; static void mxc_serial_setbrg(void) @@ -186,7 +191,7 @@ static int mxc_serial_init(void) while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); - __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP; __REG(UART_PHYS + UCR4) = 0x8000; __REG(UART_PHYS + UESC) = 0x002b; __REG(UART_PHYS + UTIM) = 0x0; @@ -222,3 +227,118 @@ __weak struct serial_device *default_serial_console(void) { return &mxc_serial_drv; } +#endif + +#ifdef CONFIG_DM_SERIAL + +struct mxc_uart { + u32 rxd; + u32 spare0[15]; + + u32 txd; + u32 spare1[15]; + + u32 cr1; + u32 cr2; + u32 cr3; + u32 cr4; + + u32 fcr; + u32 sr1; + u32 sr2; + u32 esc; + + u32 tim; + u32 bir; + u32 bmr; + u32 brc; + + u32 onems; + u32 ts; +}; + +int mxc_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct mxc_serial_platdata *plat = dev->platdata; + struct mxc_uart *const uart = plat->reg; + u32 clk = imx_get_uartclk(); + + writel(4 << 7, &uart->fcr); /* divide input clock by 2 */ + writel(0xf, &uart->bir); + writel(clk / (2 * baudrate), &uart->bmr); + + writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST, + &uart->cr2); + writel(UCR1_UARTEN, &uart->cr1); + + return 0; +} + +static int mxc_serial_probe(struct udevice *dev) +{ + struct mxc_serial_platdata *plat = dev->platdata; + struct mxc_uart *const uart = plat->reg; + + writel(0, &uart->cr1); + writel(0, &uart->cr2); + while (!(readl(&uart->cr2) & UCR2_SRST)); + writel(0x704 | UCR3_ADNIMP, &uart->cr3); + writel(0x8000, &uart->cr4); + writel(0x2b, &uart->esc); + writel(0, &uart->tim); + writel(0, &uart->ts); + + return 0; +} + +static int mxc_serial_getc(struct udevice *dev) +{ + struct mxc_serial_platdata *plat = dev->platdata; + struct mxc_uart *const uart = plat->reg; + + if (readl(&uart->ts) & UTS_RXEMPTY) + return -EAGAIN; + + return readl(&uart->rxd) & URXD_RX_DATA; +} + +static int mxc_serial_putc(struct udevice *dev, const char ch) +{ + struct mxc_serial_platdata *plat = dev->platdata; + struct mxc_uart *const uart = plat->reg; + + if (!(readl(&uart->ts) & UTS_TXEMPTY)) + return -EAGAIN; + + writel(ch, &uart->txd); + + return 0; +} + +static int mxc_serial_pending(struct udevice *dev, bool input) +{ + struct mxc_serial_platdata *plat = dev->platdata; + struct mxc_uart *const uart = plat->reg; + uint32_t sr2 = readl(&uart->sr2); + + if (input) + return sr2 & USR2_RDR ? 1 : 0; + else + return sr2 & USR2_TXDC ? 0 : 1; +} + +static const struct dm_serial_ops mxc_serial_ops = { + .putc = mxc_serial_putc, + .pending = mxc_serial_pending, + .getc = mxc_serial_getc, + .setbrg = mxc_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_mxc) = { + .name = "serial_mxc", + .id = UCLASS_SERIAL, + .probe = mxc_serial_probe, + .ops = &mxc_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; +#endif diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index ba68d46948..799ef6a667 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -81,7 +81,8 @@ static NS16550_t serial_ports[6] = { static int eserial##port##_init(void) \ { \ int clock_divisor; \ - clock_divisor = calc_divisor(serial_ports[port-1]); \ + clock_divisor = ns16550_calc_divisor(serial_ports[port-1], \ + CONFIG_SYS_NS16550_CLK, gd->baudrate); \ NS16550_init(serial_ports[port-1], clock_divisor); \ return 0 ; \ } \ @@ -118,35 +119,7 @@ static NS16550_t serial_ports[6] = { .puts = eserial##port##_puts, \ } -static int calc_divisor (NS16550_t port) -{ -#ifdef CONFIG_OMAP1510 - /* If can't cleanly clock 115200 set div to 1 */ - if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) { - port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ - return (1); /* return 1 for base divisor */ - } - port->osc_12m_sel = 0; /* clear if previsouly set */ -#endif -#ifdef CONFIG_OMAP1610 - /* If can't cleanly clock 115200 set div to 1 */ - if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) { - return (26); /* return 26 for base divisor */ - } -#endif - -#define MODE_X_DIV 16 - /* Compute divisor value. Normally, we should simply return: - * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate - * but we need to round that value by adding 0.5. - * Rounding is especially important at high baud rates. - */ - return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) / - (MODE_X_DIV * gd->baudrate); -} - -void -_serial_putc(const char c,const int port) +static void _serial_putc(const char c, const int port) { if (c == '\n') NS16550_putc(PORT, '\r'); @@ -154,39 +127,34 @@ _serial_putc(const char c,const int port) NS16550_putc(PORT, c); } -void -_serial_putc_raw(const char c,const int port) +static void _serial_putc_raw(const char c, const int port) { NS16550_putc(PORT, c); } -void -_serial_puts (const char *s,const int port) +static void _serial_puts(const char *s, const int port) { while (*s) { - _serial_putc (*s++,port); + _serial_putc(*s++, port); } } - -int -_serial_getc(const int port) +static int _serial_getc(const int port) { return NS16550_getc(PORT); } -int -_serial_tstc(const int port) +static int _serial_tstc(const int port) { return NS16550_tstc(PORT); } -void -_serial_setbrg (const int port) +static void _serial_setbrg(const int port) { int clock_divisor; - clock_divisor = calc_divisor(PORT); + clock_divisor = ns16550_calc_divisor(PORT, CONFIG_SYS_NS16550_CLK, + gd->baudrate); NS16550_reinit(PORT, clock_divisor); } diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c new file mode 100644 index 0000000000..265fe007a0 --- /dev/null +++ b/drivers/serial/serial_omap.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_OF_CONTROL +static const struct udevice_id omap_serial_ids[] = { + { .compatible = "ti,omap3-uart" }, + { } +}; + +static int omap_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", -1); + plat->reg_shift = 2; + + return 0; +} +#endif + +U_BOOT_DRIVER(serial_omap_ns16550) = { + .name = "serial_omap", + .id = UCLASS_SERIAL, + .of_match = of_match_ptr(omap_serial_ids), + .ofdata_to_platdata = of_match_ptr(omap_serial_ofdata_to_platdata), + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index dfb610e1a9..75eb6bd729 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -12,123 +12,97 @@ /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ #include +#include +#include #include #include #include +#include #include -#include "serial_pl01x.h" +#include "serial_pl01x_internal.h" + +#ifndef CONFIG_DM_SERIAL -/* - * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 - * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 - * Versatile PB has four UARTs. - */ -#define CONSOLE_PORT CONFIG_CONS_INDEX static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +static enum pl01x_type pl01x_type __attribute__ ((section(".data"))); +static struct pl01x_regs *base_regs __attribute__ ((section(".data"))); #define NUM_PORTS (sizeof(port)/sizeof(port[0])) -static void pl01x_putc (int portnum, char c); -static int pl01x_getc (int portnum); -static int pl01x_tstc (int portnum); -unsigned int baudrate = CONFIG_BAUDRATE; DECLARE_GLOBAL_DATA_PTR; +#endif -static struct pl01x_regs *pl01x_get_regs(int portnum) +static int pl01x_putc(struct pl01x_regs *regs, char c) { - return (struct pl01x_regs *) port[portnum]; -} + /* Wait until there is space in the FIFO */ + if (readl(®s->fr) & UART_PL01x_FR_TXFF) + return -EAGAIN; -#ifdef CONFIG_PL010_SERIAL + /* Send the character */ + writel(c, ®s->dr); -static int pl01x_serial_init(void) + return 0; +} + +static int pl01x_getc(struct pl01x_regs *regs) { - struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); - unsigned int divisor; + unsigned int data; - /* First, disable everything */ - writel(0, ®s->pl010_cr); + /* Wait until there is data in the FIFO */ + if (readl(®s->fr) & UART_PL01x_FR_RXFE) + return -EAGAIN; - /* Set baud rate */ - switch (baudrate) { - case 9600: - divisor = UART_PL010_BAUD_9600; - break; + data = readl(®s->dr); - case 19200: - divisor = UART_PL010_BAUD_9600; - break; + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + writel(0xFFFFFFFF, ®s->ecr); + return -1; + } - case 38400: - divisor = UART_PL010_BAUD_38400; - break; + return (int) data; +} - case 57600: - divisor = UART_PL010_BAUD_57600; - break; +static int pl01x_tstc(struct pl01x_regs *regs) +{ + WATCHDOG_RESET(); + return !(readl(®s->fr) & UART_PL01x_FR_RXFE); +} - case 115200: - divisor = UART_PL010_BAUD_115200; +static int pl01x_generic_serial_init(struct pl01x_regs *regs, + enum pl01x_type type) +{ + switch (type) { + case TYPE_PL010: + /* disable everything */ + writel(0, ®s->pl010_cr); + break; + case TYPE_PL011: +#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT + /* Empty RX fifo if necessary */ + if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { + while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) + readl(®s->dr); + } +#endif + /* disable everything */ + writel(0, ®s->pl011_cr); break; - default: - divisor = UART_PL010_BAUD_38400; + return -EINVAL; } - writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); - writel(divisor & 0xff, ®s->pl010_lcrl); - - /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ - writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh); - - /* Finally, enable the UART */ - writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); - return 0; } -#endif /* CONFIG_PL010_SERIAL */ - -#ifdef CONFIG_PL011_SERIAL - -static int pl01x_serial_init(void) +static int set_line_control(struct pl01x_regs *regs) { - struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); - unsigned int temp; - unsigned int divider; - unsigned int remainder; - unsigned int fraction; unsigned int lcr; - -#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT - /* Empty RX fifo if necessary */ - if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { - while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) - readl(®s->dr); - } -#endif - - /* First, disable everything */ - writel(0, ®s->pl011_cr); - /* - * Set baud rate - * - * IBRD = UART_CLK / (16 * BAUD_RATE) - * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) + * Internal update of baud rate register require line + * control register write */ - temp = 16 * baudrate; - divider = CONFIG_PL011_CLOCK / temp; - remainder = CONFIG_PL011_CLOCK % temp; - temp = (8 * remainder) / baudrate; - fraction = (temp >> 1) + (temp & 1); - - writel(divider, ®s->pl011_ibrd); - writel(fraction, ®s->pl011_fbrd); - - /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; - writel(lcr, ®s->pl011_lcrh); - #ifdef CONFIG_PL011_SERIAL_RLCR { int i; @@ -142,92 +116,148 @@ static int pl01x_serial_init(void) writel(lcr, ®s->fr); writel(lcr, ®s->pl011_rlcr); - /* lcrh needs to be set again for change to be effective */ - writel(lcr, ®s->pl011_lcrh); } #endif - /* Finally, enable the UART */ - writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE | - UART_PL011_CR_RTS, ®s->pl011_cr); - + writel(lcr, ®s->pl011_lcrh); return 0; } -#endif /* CONFIG_PL011_SERIAL */ - -static void pl01x_serial_putc(const char c) +static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, + int clock, int baudrate) { - if (c == '\n') - pl01x_putc (CONSOLE_PORT, '\r'); + switch (type) { + case TYPE_PL010: { + unsigned int divisor; + + switch (baudrate) { + case 9600: + divisor = UART_PL010_BAUD_9600; + break; + case 19200: + divisor = UART_PL010_BAUD_9600; + break; + case 38400: + divisor = UART_PL010_BAUD_38400; + break; + case 57600: + divisor = UART_PL010_BAUD_57600; + break; + case 115200: + divisor = UART_PL010_BAUD_115200; + break; + default: + divisor = UART_PL010_BAUD_38400; + } + + writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); + writel(divisor & 0xff, ®s->pl010_lcrl); + + /* Finally, enable the UART */ + writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); + break; + } + case TYPE_PL011: { + unsigned int temp; + unsigned int divider; + unsigned int remainder; + unsigned int fraction; - pl01x_putc (CONSOLE_PORT, c); -} + /* + * Set baud rate + * + * IBRD = UART_CLK / (16 * BAUD_RATE) + * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) + * / (16 * BAUD_RATE)) + */ + temp = 16 * baudrate; + divider = clock / temp; + remainder = clock % temp; + temp = (8 * remainder) / baudrate; + fraction = (temp >> 1) + (temp & 1); + + writel(divider, ®s->pl011_ibrd); + writel(fraction, ®s->pl011_fbrd); + + set_line_control(regs); + /* Finally, enable the UART */ + writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | + UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr); + break; + } + default: + return -EINVAL; + } -static int pl01x_serial_getc(void) -{ - return pl01x_getc (CONSOLE_PORT); + return 0; } -static int pl01x_serial_tstc(void) +#ifndef CONFIG_DM_SERIAL +static void pl01x_serial_init_baud(int baudrate) { - return pl01x_tstc (CONSOLE_PORT); + int clock = 0; + +#if defined(CONFIG_PL010_SERIAL) + pl01x_type = TYPE_PL010; +#elif defined(CONFIG_PL011_SERIAL) + pl01x_type = TYPE_PL011; + clock = CONFIG_PL011_CLOCK; +#endif + base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX]; + + pl01x_generic_serial_init(base_regs, pl01x_type); + pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate); } -static void pl01x_serial_setbrg(void) +/* + * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 + * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 + * Versatile PB has four UARTs. + */ +int pl01x_serial_init(void) { - struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); + pl01x_serial_init_baud(CONFIG_BAUDRATE); - baudrate = gd->baudrate; - /* - * Flush FIFO and wait for non-busy before changing baudrate to avoid - * crap in console - */ - while (!(readl(®s->fr) & UART_PL01x_FR_TXFE)) - WATCHDOG_RESET(); - while (readl(®s->fr) & UART_PL01x_FR_BUSY) - WATCHDOG_RESET(); - serial_init(); + return 0; } -static void pl01x_putc (int portnum, char c) +static void pl01x_serial_putc(const char c) { - struct pl01x_regs *regs = pl01x_get_regs(portnum); - - /* Wait until there is space in the FIFO */ - while (readl(®s->fr) & UART_PL01x_FR_TXFF) - WATCHDOG_RESET(); + if (c == '\n') + while (pl01x_putc(base_regs, '\r') == -EAGAIN); - /* Send the character */ - writel(c, ®s->dr); + while (pl01x_putc(base_regs, c) == -EAGAIN); } -static int pl01x_getc (int portnum) +static int pl01x_serial_getc(void) { - struct pl01x_regs *regs = pl01x_get_regs(portnum); - unsigned int data; + while (1) { + int ch = pl01x_getc(base_regs); - /* Wait until there is data in the FIFO */ - while (readl(®s->fr) & UART_PL01x_FR_RXFE) - WATCHDOG_RESET(); - - data = readl(®s->dr); + if (ch == -EAGAIN) { + WATCHDOG_RESET(); + continue; + } - /* Check for an error flag */ - if (data & 0xFFFFFF00) { - /* Clear the error */ - writel(0xFFFFFFFF, ®s->ecr); - return -1; + return ch; } - - return (int) data; } -static int pl01x_tstc (int portnum) +static int pl01x_serial_tstc(void) { - struct pl01x_regs *regs = pl01x_get_regs(portnum); + return pl01x_tstc(base_regs); +} - WATCHDOG_RESET(); - return !(readl(®s->fr) & UART_PL01x_FR_RXFE); +static void pl01x_serial_setbrg(void) +{ + /* + * Flush FIFO and wait for non-busy before changing baudrate to avoid + * crap in console + */ + while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE)) + WATCHDOG_RESET(); + while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY) + WATCHDOG_RESET(); + pl01x_serial_init_baud(gd->baudrate); } static struct serial_device pl01x_serial_drv = { @@ -250,3 +280,75 @@ __weak struct serial_device *default_serial_console(void) { return &pl01x_serial_drv; } + +#endif /* nCONFIG_DM_SERIAL */ + +#ifdef CONFIG_DM_SERIAL + +struct pl01x_priv { + struct pl01x_regs *regs; + enum pl01x_type type; +}; + +static int pl01x_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct pl01x_serial_platdata *plat = dev_get_platdata(dev); + struct pl01x_priv *priv = dev_get_priv(dev); + + pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate); + + return 0; +} + +static int pl01x_serial_probe(struct udevice *dev) +{ + struct pl01x_serial_platdata *plat = dev_get_platdata(dev); + struct pl01x_priv *priv = dev_get_priv(dev); + + priv->regs = (struct pl01x_regs *)plat->base; + priv->type = plat->type; + return pl01x_generic_serial_init(priv->regs, priv->type); +} + +static int pl01x_serial_getc(struct udevice *dev) +{ + struct pl01x_priv *priv = dev_get_priv(dev); + + return pl01x_getc(priv->regs); +} + +static int pl01x_serial_putc(struct udevice *dev, const char ch) +{ + struct pl01x_priv *priv = dev_get_priv(dev); + + return pl01x_putc(priv->regs, ch); +} + +static int pl01x_serial_pending(struct udevice *dev, bool input) +{ + struct pl01x_priv *priv = dev_get_priv(dev); + unsigned int fr = readl(&priv->regs->fr); + + if (input) + return pl01x_tstc(priv->regs); + else + return fr & UART_PL01x_FR_TXFF ? 0 : 1; +} + +static const struct dm_serial_ops pl01x_serial_ops = { + .putc = pl01x_serial_putc, + .pending = pl01x_serial_pending, + .getc = pl01x_serial_getc, + .setbrg = pl01x_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_pl01x) = { + .name = "serial_pl01x", + .id = UCLASS_SERIAL, + .probe = pl01x_serial_probe, + .ops = &pl01x_serial_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct pl01x_priv), +}; + +#endif diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x_internal.h similarity index 100% rename from drivers/serial/serial_pl01x.h rename to drivers/serial/serial_pl01x_internal.h diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index c07f4c9b47..7afc5044a8 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -69,7 +69,7 @@ DECLARE_GLOBAL_DATA_PTR; static int hwflow; #endif -void _serial_setbrg(const int dev_index) +static void _serial_setbrg(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); unsigned int reg = 0; @@ -131,7 +131,7 @@ static int serial_init_dev(const int dev_index) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int _serial_getc(const int dev_index) +static int _serial_getc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); @@ -181,7 +181,7 @@ void enable_putc(void) /* * Output a single byte to the serial port. */ -void _serial_putc(const char c, const int dev_index) +static void _serial_putc(const char c, const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); #ifdef CONFIG_MODEM_SUPPORT @@ -212,7 +212,7 @@ static inline void serial_putc_dev(unsigned int dev_index, const char c) /* * Test whether a character is in the RX buffer */ -int _serial_tstc(const int dev_index) +static int _serial_tstc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); @@ -224,7 +224,7 @@ static inline int serial_tstc_dev(unsigned int dev_index) return _serial_tstc(dev_index); } -void _serial_puts(const char *s, const int dev_index) +static void _serial_puts(const char *s, const int dev_index) { while (*s) { _serial_putc(*s++, dev_index); diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c deleted file mode 100644 index 2a07498c1e..0000000000 --- a/drivers/serial/serial_s3c44b0.c +++ /dev/null @@ -1,216 +0,0 @@ -pyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * ght 2002-2004 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* flush serial input queue. returns 0 on success or negative error - * number otherwise - */ -static int serial_flush_input(void) -{ - volatile u32 tmp; - - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0&0x01) { - tmp = REGB(URXH0); - } - - return 0; -} - - -/* flush output queue. returns 0 on success or negative error number - * otherwise - */ -static int serial_flush_output(void) -{ - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & 0x02)) { - } - - return 0; -} - - -static void s3c44b0_serial_setbrg(void) -{ - u32 divisor = 0; - - /* get correct divisor */ - switch(gd->baudrate) { - - case 1200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 3124; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 3905; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 9600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 390; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 487; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 19200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 194; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 243; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 38400: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 97; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 121; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 57600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 64; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 80; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 115200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 32; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 40; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - } - - serial_flush_output(); - serial_flush_input(); - UFCON0 = 0x0; - ULCON0 = 0x03; - UCON0 = 0x05; - UBRDIV0 = divisor; - - UFCON1 = 0x0; - ULCON1 = 0x03; - UCON1 = 0x05; - UBRDIV1 = divisor; - - for(divisor=0; divisor<100; divisor++) { - /* NOP */ - } -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int s3c44b0_serial_init(void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void s3c44b0_serial_putc(const char c) -{ - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & 0x02)); - - UTXH0 = (unsigned char)c; - - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n') - serial_putc('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int s3c44b0_serial_tstc(void) -{ - return (UTRSTAT0 & 0x01); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int s3c44b0_serial_getc(void) -{ - int rv; - - for(;;) { - rv = s3c44b0_serial_tstc(); - - if(rv > 0) - return URXH0; - } -} - -static struct serial_device s3c44b0_serial_drv = { - .name = "s3c44b0_serial", - .start = s3c44b0_serial_init, - .stop = NULL, - .setbrg = s3c44b0_serial_setbrg, - .putc = s3c44b0_serial_putc, - .puts = default_serial_puts, - .getc = s3c44b0_serial_getc, - .tstc = s3c44b0_serial_tstc, -}; - -void s3c44b0_serial_initialize(void) -{ - serial_register(&s3c44b0_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &s3c44b0_serial_drv; -} diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index f98b422632..8469afdaae 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -9,6 +9,8 @@ */ #include +#include +#include #include #include #include @@ -18,26 +20,18 @@ DECLARE_GLOBAL_DATA_PTR; -#define RX_FIFO_COUNT_MASK 0xff -#define RX_FIFO_FULL_MASK (1 << 8) -#define TX_FIFO_FULL_MASK (1 << 24) +#define RX_FIFO_COUNT_SHIFT 0 +#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT) +#define RX_FIFO_FULL (1 << 8) +#define TX_FIFO_COUNT_SHIFT 16 +#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT) +#define TX_FIFO_FULL (1 << 24) /* Information about a serial port */ -struct fdt_serial { - u32 base_addr; /* address of registers in physical memory */ +struct s5p_serial_platdata { + struct s5p_uart *reg; /* address of registers in physical memory */ u8 port_id; /* uart port number */ - u8 enabled; /* 1 if enabled, 0 if disabled */ -} config __attribute__ ((section(".data"))); - -static inline struct s5p_uart *s5p_get_base_uart(int dev_index) -{ -#ifdef CONFIG_OF_CONTROL - return (struct s5p_uart *)(config.base_addr); -#else - u32 offset = dev_index * sizeof(struct s5p_uart); - return (struct s5p_uart *)(samsung_get_base_uart() + offset); -#endif -} +}; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -65,23 +59,13 @@ static const int udivslot[] = { 0xffdf, }; -void serial_setbrg_dev(const int dev_index) +int s5p_serial_setbrg(struct udevice *dev, int baudrate) { - struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - u32 uclk = get_uart_clk(dev_index); - u32 baudrate = gd->baudrate; + struct s5p_serial_platdata *plat = dev->platdata; + struct s5p_uart *const uart = plat->reg; + u32 uclk = get_uart_clk(plat->port_id); u32 val; -#if defined(CONFIG_SILENT_CONSOLE) && \ - defined(CONFIG_OF_CONTROL) && \ - !defined(CONFIG_SPL_BUILD) - if (fdtdec_get_config_int(gd->fdt_blob, "silent_console", 0)) - gd->flags |= GD_FLG_SILENT; -#endif - - if (!config.enabled) - return; - val = uclk / baudrate; writel(val / 16 - 1, &uart->ubrdiv); @@ -90,32 +74,28 @@ void serial_setbrg_dev(const int dev_index) writew(udivslot[val % 16], &uart->rest.slot); else writeb(val % 16, &uart->rest.value); + + return 0; } -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -int serial_init_dev(const int dev_index) +static int s5p_serial_probe(struct udevice *dev) { - struct s5p_uart *const uart = s5p_get_base_uart(dev_index); + struct s5p_serial_platdata *plat = dev->platdata; + struct s5p_uart *const uart = plat->reg; - /* enable FIFOs */ - writel(0x1, &uart->ufcon); + /* enable FIFOs, auto clear Rx FIFO */ + writel(0x3, &uart->ufcon); writel(0, &uart->umcon); /* 8N1 */ writel(0x3, &uart->ulcon); /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(dev_index); - return 0; } -static int serial_err_check(const int dev_index, int op) +static int serial_err_check(const struct s5p_uart *const uart, int op) { - struct s5p_uart *const uart = s5p_get_base_uart(dev_index); unsigned int mask; /* @@ -133,169 +113,78 @@ static int serial_err_check(const int dev_index, int op) return readl(&uart->uerstat) & mask; } -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc_dev(const int dev_index) +static int s5p_serial_getc(struct udevice *dev) { - struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - - if (!config.enabled) - return 0; + struct s5p_serial_platdata *plat = dev->platdata; + struct s5p_uart *const uart = plat->reg; - /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | - RX_FIFO_FULL_MASK))) { - if (serial_err_check(dev_index, 0)) - return 0; - } + if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK)) + return -EAGAIN; + serial_err_check(uart, 0); return (int)(readb(&uart->urxh) & 0xff); } -/* - * Output a single byte to the serial port. - */ -void serial_putc_dev(const char c, const int dev_index) +static int s5p_serial_putc(struct udevice *dev, const char ch) { - struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - - if (!config.enabled) - return; - - /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (serial_err_check(dev_index, 1)) - return; - } + struct s5p_serial_platdata *plat = dev->platdata; + struct s5p_uart *const uart = plat->reg; - writeb(c, &uart->utxh); + if (readl(&uart->ufstat) & TX_FIFO_FULL) + return -EAGAIN; - /* If \n, also do \r */ - if (c == '\n') - serial_putc('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc_dev(const int dev_index) -{ - struct s5p_uart *const uart = s5p_get_base_uart(dev_index); + writeb(ch, &uart->utxh); + serial_err_check(uart, 1); - if (!config.enabled) - return 0; - - return (int)(readl(&uart->utrstat) & 0x1); + return 0; } -void serial_puts_dev(const char *s, const int dev_index) +static int s5p_serial_pending(struct udevice *dev, bool input) { - while (*s) - serial_putc_dev(*s++, dev_index); -} + struct s5p_serial_platdata *plat = dev->platdata; + struct s5p_uart *const uart = plat->reg; + uint32_t ufstat = readl(&uart->ufstat); -/* Multi serial device functions */ -#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \ -int s5p_serial##port##_init(void) { return serial_init_dev(port); } \ -void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \ -int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \ -int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \ -void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \ -void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); } - -#define INIT_S5P_SERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = s5p_serial##port##_init, \ - .stop = NULL, \ - .setbrg = s5p_serial##port##_setbrg, \ - .getc = s5p_serial##port##_getc, \ - .tstc = s5p_serial##port##_tstc, \ - .putc = s5p_serial##port##_putc, \ - .puts = s5p_serial##port##_puts, \ + if (input) + return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT; + else + return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT; } -DECLARE_S5P_SERIAL_FUNCTIONS(0); -struct serial_device s5p_serial0_device = - INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0"); -DECLARE_S5P_SERIAL_FUNCTIONS(1); -struct serial_device s5p_serial1_device = - INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1"); -DECLARE_S5P_SERIAL_FUNCTIONS(2); -struct serial_device s5p_serial2_device = - INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2"); -DECLARE_S5P_SERIAL_FUNCTIONS(3); -struct serial_device s5p_serial3_device = - INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3"); - -#ifdef CONFIG_OF_CONTROL -int fdtdec_decode_console(int *index, struct fdt_serial *uart) +static int s5p_serial_ofdata_to_platdata(struct udevice *dev) { - const void *blob = gd->fdt_blob; - int node; + struct s5p_serial_platdata *plat = dev->platdata; + fdt_addr_t addr; - node = fdt_path_offset(blob, "console"); - if (node < 0) - return node; + addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; - uart->base_addr = fdtdec_get_addr(blob, node, "reg"); - if (uart->base_addr == FDT_ADDR_T_NONE) - return -FDT_ERR_NOTFOUND; - - uart->port_id = fdtdec_get_int(blob, node, "id", -1); - uart->enabled = fdtdec_get_is_enabled(blob, node); + plat->reg = (struct s5p_uart *)addr; + plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1); return 0; } -#endif -__weak struct serial_device *default_serial_console(void) -{ -#ifdef CONFIG_OF_CONTROL - int index = 0; - - if ((!config.base_addr) && (fdtdec_decode_console(&index, &config))) { - debug("Cannot decode default console node\n"); - return NULL; - } - - switch (config.port_id) { - case 0: - return &s5p_serial0_device; - case 1: - return &s5p_serial1_device; - case 2: - return &s5p_serial2_device; - case 3: - return &s5p_serial3_device; - default: - debug("Unknown config.port_id: %d", config.port_id); - break; - } - - return NULL; -#else - config.enabled = 1; -#if defined(CONFIG_SERIAL0) - return &s5p_serial0_device; -#elif defined(CONFIG_SERIAL1) - return &s5p_serial1_device; -#elif defined(CONFIG_SERIAL2) - return &s5p_serial2_device; -#elif defined(CONFIG_SERIAL3) - return &s5p_serial3_device; -#else -#error "CONFIG_SERIAL? missing." -#endif -#endif -} +static const struct dm_serial_ops s5p_serial_ops = { + .putc = s5p_serial_putc, + .pending = s5p_serial_pending, + .getc = s5p_serial_getc, + .setbrg = s5p_serial_setbrg, +}; -void s5p_serial_initialize(void) -{ - serial_register(&s5p_serial0_device); - serial_register(&s5p_serial1_device); - serial_register(&s5p_serial2_device); - serial_register(&s5p_serial3_device); -} +static const struct udevice_id s5p_serial_ids[] = { + { .compatible = "samsung,exynos4210-uart" }, + { } +}; + +U_BOOT_DRIVER(serial_s5p) = { + .name = "serial_s5p", + .id = UCLASS_SERIAL, + .of_match = s5p_serial_ids, + .ofdata_to_platdata = s5p_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata), + .probe = s5p_serial_probe, + .ops = &s5p_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index ff2cdc5847..7c1f271376 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -1,5 +1,6 @@ /* * SuperH SCIF device driver. + * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu * Copyright (C) 2002 - 2008 Paul Mundt * @@ -48,7 +49,15 @@ static struct uart_port sh_sci = { static void sh_serial_setbrg(void) { DECLARE_GLOBAL_DATA_PTR; - sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ)); +#ifdef CONFIG_SCIF_USE_EXT_CLK + unsigned short dl = DL_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ); + sci_out(&sh_sci, DL, dl); + /* Need wait: Clock * 1/dl $B!_(B 1/16 */ + udelay((1000000 * dl * 16 / CONFIG_SYS_CLK_FREQ) * 1000 + 1); +#else + sci_out(&sh_sci, SCBRR, + SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ)); +#endif } static int sh_serial_init(void) @@ -113,7 +122,7 @@ static void handle_error(void) sci_out(&sh_sci, SCLSR, 0x00); } -void serial_raw_putc(const char c) +static void serial_raw_putc(const char c) { while (1) { /* Tx fifo is empty */ @@ -143,7 +152,7 @@ static int sh_serial_tstc(void) } -int serial_getc_check(void) +static int serial_getc_check(void) { unsigned short status; diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 7e38a3fd53..ef88c8f273 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -143,7 +143,9 @@ struct uart_port { #elif defined(CONFIG_H8S2678) # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) -#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) +#elif defined(CONFIG_CPU_SH7757) || \ + defined(CONFIG_CPU_SH7752) || \ + defined(CONFIG_CPU_SH7753) # define SCSPTR0 0xfe4b0020 # define SCSPTR1 0xfe4b0020 # define SCSPTR2 0xfe4b0020 @@ -224,6 +226,10 @@ struct uart_port { # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +# define SCIF_ORER 0x0001 +# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else # error CPU subtype not defined #endif @@ -298,6 +304,10 @@ struct uart_port { /* SH7763 SCIF2 support */ # define SCIF2_RFDC_MASK 0x001f # define SCIF2_TXROOM_MAX 16 +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) +# define SCIF_RFDC_MASK 0x003f #else # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) # define SCIF_RFDC_MASK 0x001f @@ -423,7 +433,7 @@ static inline void sci_##name##_out(struct uart_port *port,\ SCI_OUT(sci_size, sci_offset, value);\ } -#if defined(CONFIG_SH3) || \ +#if defined(CONFIG_CPU_SH3) || \ defined(CONFIG_ARCH_SH7367) || \ defined(CONFIG_ARCH_SH7377) || \ defined(CONFIG_ARCH_SH7372) || \ @@ -579,6 +589,11 @@ SCIF_FNS(SCSPTR, 0, 0, 0, 0) #else SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) #endif +#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +SCIF_FNS(DL, 0, 0, 0x30, 16) +SCIF_FNS(CKS, 0, 0, 0x34, 16) +#endif SCIF_FNS(SCLSR, 0, 0, 0x24, 16) #endif #endif @@ -720,6 +735,10 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk) #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ +#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif diff --git a/drivers/serial/serial_tegra.c b/drivers/serial/serial_tegra.c new file mode 100644 index 0000000000..b9227f0563 --- /dev/null +++ b/drivers/serial/serial_tegra.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifdef CONFIG_OF_CONTROL +static const struct udevice_id tegra_serial_ids[] = { + { .compatible = "nvidia,tegra20-uart" }, + { } +}; + +static int tegra_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + plat->clock = V_NS16550_CLK; + + return 0; +} +#else +struct ns16550_platdata tegra_serial = { + .base = CONFIG_SYS_NS16550_COM1, + .reg_shift = 2, + .clock = V_NS16550_CLK, +}; + +U_BOOT_DEVICE(ns16550_serial) = { + "serial_tegra20", &tegra_serial +}; +#endif + +U_BOOT_DRIVER(serial_ns16550) = { + .name = "serial_tegra20", + .id = UCLASS_SERIAL, +#ifdef CONFIG_OF_CONTROL + .of_match = tegra_serial_ids, + .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), +#endif + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c new file mode 100644 index 0000000000..e8a1608b99 --- /dev/null +++ b/drivers/serial/serial_uniphier.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define UART_REG(x) \ + u8 x; \ + u8 postpad_##x[3]; + +/* + * Note: Register map is slightly different from that of 16550. + */ +struct uniphier_serial { + UART_REG(rbr); /* 0x00 */ + UART_REG(ier); /* 0x04 */ + UART_REG(iir); /* 0x08 */ + UART_REG(fcr); /* 0x0c */ + u8 mcr; /* 0x10 */ + u8 lcr; + u16 __postpad; + UART_REG(lsr); /* 0x14 */ + UART_REG(msr); /* 0x18 */ + u32 __none1; + u32 __none2; + u16 dlr; + u16 __postpad2; +}; + +#define thr rbr + +struct uniphier_serial_private_data { + struct uniphier_serial __iomem *membase; +}; + +#define uniphier_serial_port(dev) \ + ((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase + +static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct uniphier_serial_platform_data *plat = dev_get_platdata(dev); + struct uniphier_serial __iomem *port = uniphier_serial_port(dev); + const unsigned int mode_x_div = 16; + unsigned int divisor; + + writeb(UART_LCR_WLEN8, &port->lcr); + + divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate); + + writew(divisor, &port->dlr); + + return 0; +} + +static int uniphier_serial_getc(struct udevice *dev) +{ + struct uniphier_serial __iomem *port = uniphier_serial_port(dev); + + if (!(readb(&port->lsr) & UART_LSR_DR)) + return -EAGAIN; + + return readb(&port->rbr); +} + +static int uniphier_serial_putc(struct udevice *dev, const char c) +{ + struct uniphier_serial __iomem *port = uniphier_serial_port(dev); + + if (!(readb(&port->lsr) & UART_LSR_THRE)) + return -EAGAIN; + + writeb(c, &port->thr); + + return 0; +} + +static int uniphier_serial_pending(struct udevice *dev, bool input) +{ + struct uniphier_serial __iomem *port = uniphier_serial_port(dev); + + if (input) + return readb(&port->lsr) & UART_LSR_DR; + else + return !(readb(&port->lsr) & UART_LSR_THRE); +} + +static int uniphier_serial_probe(struct udevice *dev) +{ + struct uniphier_serial_private_data *priv = dev_get_priv(dev); + struct uniphier_serial_platform_data *plat = dev_get_platdata(dev); + + priv->membase = map_sysmem(plat->base, sizeof(struct uniphier_serial)); + + if (!priv->membase) + return -ENOMEM; + + return 0; +} + +static int uniphier_serial_remove(struct udevice *dev) +{ + unmap_sysmem(uniphier_serial_port(dev)); + + return 0; +} + +#ifdef CONFIG_OF_CONTROL +static const struct udevice_id uniphier_uart_of_match[] = { + { .compatible = "panasonic,uniphier-uart" }, + {}, +}; + +static int uniphier_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct uniphier_serial_platform_data *plat = dev_get_platdata(dev); + DECLARE_GLOBAL_DATA_PTR; + + plat->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + return 0; +} +#endif + +static const struct dm_serial_ops uniphier_serial_ops = { + .setbrg = uniphier_serial_setbrg, + .getc = uniphier_serial_getc, + .putc = uniphier_serial_putc, + .pending = uniphier_serial_pending, +}; + +U_BOOT_DRIVER(uniphier_serial) = { + .name = DRIVER_NAME, + .id = UCLASS_SERIAL, + .of_match = of_match_ptr(uniphier_uart_of_match), + .ofdata_to_platdata = of_match_ptr(uniphier_serial_ofdata_to_platdata), + .probe = uniphier_serial_probe, + .remove = uniphier_serial_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data), + .platdata_auto_alloc_size = + sizeof(struct uniphier_serial_platform_data), + .ops = &uniphier_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c new file mode 100644 index 0000000000..4bf6062c64 --- /dev/null +++ b/drivers/serial/serial_x86.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct udevice_id x86_serial_ids[] = { + { .compatible = "x86-uart" }, + { } +}; + +static int x86_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + + plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 1843200); + + return 0; +} + +U_BOOT_DRIVER(serial_ns16550) = { + .name = "serial_x86", + .id = UCLASS_SERIAL, + .of_match = x86_serial_ids, + .ofdata_to_platdata = x86_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, +}; diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 9c1d025c40..988438e754 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -18,10 +18,14 @@ #define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ #define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define ULITE_CONTROL_RST_TX 0x01 +#define ULITE_CONTROL_RST_RX 0x02 + struct uartlite { unsigned int rx_fifo; unsigned int tx_fifo; unsigned int status; + unsigned int control; }; static struct uartlite *userial_ports[4] = { @@ -39,7 +43,7 @@ static struct uartlite *userial_ports[4] = { #endif }; -void uartlite_serial_putc(const char c, const int port) +static void uartlite_serial_putc(const char c, const int port) { struct uartlite *regs = userial_ports[port]; @@ -51,13 +55,13 @@ void uartlite_serial_putc(const char c, const int port) out_be32(®s->tx_fifo, c & 0xff); } -void uartlite_serial_puts(const char *s, const int port) +static void uartlite_serial_puts(const char *s, const int port) { while (*s) uartlite_serial_putc(*s++, port); } -int uartlite_serial_getc(const int port) +static int uartlite_serial_getc(const int port) { struct uartlite *regs = userial_ports[port]; @@ -66,7 +70,7 @@ int uartlite_serial_getc(const int port) return in_be32(®s->rx_fifo) & 0xff; } -int uartlite_serial_tstc(const int port) +static int uartlite_serial_tstc(const int port) { struct uartlite *regs = userial_ports[port]; @@ -75,23 +79,31 @@ int uartlite_serial_tstc(const int port) static int uartlite_serial_init(const int port) { - if (userial_ports[port]) + struct uartlite *regs = userial_ports[port]; + + if (regs) { + out_be32(®s->control, 0); + out_be32(®s->control, + ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); + in_be32(®s->control); return 0; + } + return -1; } /* Multi serial device functions */ #define DECLARE_ESERIAL_FUNCTIONS(port) \ - int userial##port##_init(void) \ + static int userial##port##_init(void) \ { return uartlite_serial_init(port); } \ - void userial##port##_setbrg(void) {} \ - int userial##port##_getc(void) \ + static void userial##port##_setbrg(void) {} \ + static int userial##port##_getc(void) \ { return uartlite_serial_getc(port); } \ - int userial##port##_tstc(void) \ + static int userial##port##_tstc(void) \ { return uartlite_serial_tstc(port); } \ - void userial##port##_putc(const char c) \ + static void userial##port##_putc(const char c) \ { uartlite_serial_putc(c, port); } \ - void userial##port##_puts(const char *s) \ + static void userial##port##_puts(const char *s) \ { uartlite_serial_puts(s, port); } /* Serial device descriptor */ diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 050b9c0625..3e2b8dc183 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -6,10 +6,15 @@ */ #include +#include #include #include #include #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ @@ -21,44 +26,20 @@ #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ -/* Some clock/baud constants */ -#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ -#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ - struct uart_zynq { - u32 control; /* Control Register [8:0] */ - u32 mode; /* Mode Register [10:0] */ + u32 control; /* 0x0 - Control Register [8:0] */ + u32 mode; /* 0x4 - Mode Register [10:0] */ u32 reserved1[4]; - u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ + u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ u32 reserved2[4]; - u32 channel_sts; /* Channel Status [11:0] */ - u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ - u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ + u32 channel_sts; /* 0x2c - Channel Status [11:0] */ + u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ + u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ }; static struct uart_zynq *uart_zynq_ports[2] = { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 - [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, -#endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 - [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, -#endif -}; - -struct uart_zynq_params { - u32 baudrate; - u32 clock; -}; - -static struct uart_zynq_params uart_zynq_ports_param[2] = { -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) - [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, - [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, -#endif -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) - [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, - [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, -#endif + [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, + [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, }; /* Set up the baud rate in gd struct */ @@ -67,8 +48,8 @@ static void uart_zynq_serial_setbrg(const int port) /* Calculation results. */ unsigned int calc_bauderror, bdiv, bgen; unsigned long calc_baud = 0; - unsigned long baud = uart_zynq_ports_param[port].baudrate; - unsigned long clock = uart_zynq_ports_param[port].clock; + unsigned long baud = gd->baudrate; + unsigned long clock = get_uart_clk(port); struct uart_zynq *regs = uart_zynq_ports[port]; /* master clock @@ -156,17 +137,17 @@ static int uart_zynq_serial_getc(const int port) /* Multi serial device functions */ #define DECLARE_PSSERIAL_FUNCTIONS(port) \ - int uart_zynq##port##_init(void) \ + static int uart_zynq##port##_init(void) \ { return uart_zynq_serial_init(port); } \ - void uart_zynq##port##_setbrg(void) \ + static void uart_zynq##port##_setbrg(void) \ { return uart_zynq_serial_setbrg(port); } \ - int uart_zynq##port##_getc(void) \ + static int uart_zynq##port##_getc(void) \ { return uart_zynq_serial_getc(port); } \ - int uart_zynq##port##_tstc(void) \ + static int uart_zynq##port##_tstc(void) \ { return uart_zynq_serial_tstc(port); } \ - void uart_zynq##port##_putc(const char c) \ + static void uart_zynq##port##_putc(const char c) \ { uart_zynq_serial_putc(c, port); } \ - void uart_zynq##port##_puts(const char *s) \ + static void uart_zynq##port##_puts(const char *s) \ { uart_zynq_serial_puts(s, port); } /* Serial device descriptor */ @@ -182,28 +163,52 @@ static int uart_zynq_serial_getc(const int port) } DECLARE_PSSERIAL_FUNCTIONS(0); -struct serial_device uart_zynq_serial0_device = +static struct serial_device uart_zynq_serial0_device = INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); DECLARE_PSSERIAL_FUNCTIONS(1); -struct serial_device uart_zynq_serial1_device = +static struct serial_device uart_zynq_serial1_device = INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); +#ifdef CONFIG_OF_CONTROL __weak struct serial_device *default_serial_console(void) { + const void *blob = gd->fdt_blob; + int node; + unsigned int base_addr; + + node = fdt_path_offset(blob, "serial0"); + if (node < 0) + return NULL; + + base_addr = fdtdec_get_addr(blob, node, "reg"); + if (base_addr == FDT_ADDR_T_NONE) + return NULL; + + if (base_addr == ZYNQ_SERIAL_BASEADDR0) + return &uart_zynq_serial0_device; + + if (base_addr == ZYNQ_SERIAL_BASEADDR1) + return &uart_zynq_serial1_device; + + return NULL; +} +#else +__weak struct serial_device *default_serial_console(void) +{ +#if defined(CONFIG_ZYNQ_SERIAL_UART0) if (uart_zynq_ports[0]) return &uart_zynq_serial0_device; +#endif +#if defined(CONFIG_ZYNQ_SERIAL_UART1) if (uart_zynq_ports[1]) return &uart_zynq_serial1_device; - +#endif return NULL; } +#endif -void zynq_serial_initalize(void) +void zynq_serial_initialize(void) { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 serial_register(&uart_zynq_serial0_device); -#endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 serial_register(&uart_zynq_serial1_device); -#endif } diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index 6b912efafd..75f0ec31bb 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -389,7 +389,7 @@ static void str2wide (char *str, u16 * wide) * Test whether a character is in the RX buffer */ -int usbtty_tstc (void) +int usbtty_tstc(struct stdio_dev *dev) { struct usb_endpoint_instance *endpoint = &endpoint_instance[rx_endpoint]; @@ -409,7 +409,7 @@ int usbtty_tstc (void) * written into its argument c. */ -int usbtty_getc (void) +int usbtty_getc(struct stdio_dev *dev) { char c; struct usb_endpoint_instance *endpoint = @@ -429,7 +429,7 @@ int usbtty_getc (void) /* * Output a single byte to the usb client port. */ -void usbtty_putc (const char c) +void usbtty_putc(struct stdio_dev *dev, const char c) { if (!usbtty_configured ()) return; @@ -475,7 +475,7 @@ static void __usbtty_puts (const char *str, int len) if (space) { write_buffer (&usbtty_output); - n = MIN (space, MIN (len, maxlen)); + n = min(space, min(len, maxlen)); buf_push (&usbtty_output, str, n); str += n; @@ -484,7 +484,7 @@ static void __usbtty_puts (const char *str, int len) } } -void usbtty_puts (const char *str) +void usbtty_puts(struct stdio_dev *dev, const char *str) { int n; int len; @@ -882,7 +882,7 @@ static int write_buffer (circbuf_t * buf) space_avail = current_urb->buffer_length - current_urb->actual_length; - popnum = MIN (space_avail, buf->size); + popnum = min(space_avail, (int)buf->size); if (popnum == 0) break; diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index e243a8e3b2..538b6d715d 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -14,18 +14,15 @@ #include #if defined(CONFIG_PPC) #include -#elif defined(CONFIG_OMAP1510) -#include -#elif defined(CONFIG_MUSB_UDC) -#include #elif defined(CONFIG_CPU_PXA27X) #include #elif defined(CONFIG_DW_UDC) #include -#elif defined(CONFIG_MV_UDC) -#include +#elif defined(CONFIG_CI_UDC) +#include #endif +#include #include /* If no VendorID/ProductID is defined in config.h, pretend to be Linux diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile new file mode 100644 index 0000000000..3d4baa51d6 --- /dev/null +++ b/drivers/soc/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the U-boot SOC specific device drivers. +# + +obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ diff --git a/drivers/soc/keystone/Makefile b/drivers/soc/keystone/Makefile new file mode 100644 index 0000000000..c000ecac76 --- /dev/null +++ b/drivers/soc/keystone/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o diff --git a/drivers/soc/keystone/keystone_serdes.c b/drivers/soc/keystone/keystone_serdes.c new file mode 100644 index 0000000000..dd5eac9bb3 --- /dev/null +++ b/drivers/soc/keystone/keystone_serdes.c @@ -0,0 +1,210 @@ +/* + * TI serdes driver for keystone2. + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x))) +#define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x))) +#define SERDES_COMLANE_REGS 0x0a00 +#define SERDES_WIZ_REGS 0x1fc0 + +#define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000) +#define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010) +#define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000) +#define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000) +#define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028) +#define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x))) +#define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034) + +#define SERDES_RESET BIT(28) +#define SERDES_LANE_RESET BIT(29) +#define SERDES_LANE_LOOPBACK BIT(30) +#define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10)) + +#define SERDES_CMU_CFG_NUM 5 +#define SERDES_COMLANE_CFG_NUM 10 +#define SERDES_LANE_CFG_NUM 10 + +struct serdes_cfg { + u32 ofs; + u32 val; + u32 mask; +}; + +struct cfg_entry { + enum ks2_serdes_clock clk; + enum ks2_serdes_rate rate; + struct serdes_cfg cmu[SERDES_CMU_CFG_NUM]; + struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM]; + struct serdes_cfg lane[SERDES_LANE_CFG_NUM]; +}; + +/* SERDES PHY lane enable configuration value, indexed by PHY interface */ +static u32 serdes_cfg_lane_enable[] = { + 0xf000f0c0, /* SGMII */ + 0xf0e9f038, /* PCSR */ +}; + +/* SERDES PHY PLL enable configuration value, indexed by PHY interface */ +static u32 serdes_cfg_pll_enable[] = { + 0xe0000000, /* SGMII */ + 0xee000000, /* PCSR */ +}; + +/** + * Array to hold all possible serdes configurations. + * Combination for 5 clock settings and 6 baud rates. + */ +static struct cfg_entry cfgs[] = { + { + .clk = SERDES_CLOCK_156P25M, + .rate = SERDES_RATE_5G, + .cmu = { + {0x0000, 0x00800000, 0xffff0000}, + {0x0014, 0x00008282, 0x0000ffff}, + {0x0060, 0x00142438, 0x00ffffff}, + {0x0064, 0x00c3c700, 0x00ffff00}, + {0x0078, 0x0000c000, 0x0000ff00} + }, + .comlane = { + {0x0a00, 0x00000800, 0x0000ff00}, + {0x0a08, 0x38a20000, 0xffff0000}, + {0x0a30, 0x008a8a00, 0x00ffff00}, + {0x0a84, 0x00000600, 0x0000ff00}, + {0x0a94, 0x10000000, 0xff000000}, + {0x0aa0, 0x81000000, 0xff000000}, + {0x0abc, 0xff000000, 0xff000000}, + {0x0ac0, 0x0000008b, 0x000000ff}, + {0x0b08, 0x583f0000, 0xffff0000}, + {0x0b0c, 0x0000004e, 0x000000ff} + }, + .lane = { + {0x0004, 0x38000080, 0xff0000ff}, + {0x0008, 0x00000000, 0x000000ff}, + {0x000c, 0x02000000, 0xff000000}, + {0x0010, 0x1b000000, 0xff000000}, + {0x0014, 0x00006fb8, 0x0000ffff}, + {0x0018, 0x758000e4, 0xffff00ff}, + {0x00ac, 0x00004400, 0x0000ff00}, + {0x002c, 0x00100800, 0x00ffff00}, + {0x0080, 0x00820082, 0x00ff00ff}, + {0x0084, 0x1d0f0385, 0xffffffff} + }, + }, +}; + +static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask) +{ + writel(((readl(addr) & (~mask)) | (value & mask)), addr); +} + +static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size) +{ + u32 i; + + for (i = 0; i < size; i++) + ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask); +} + +static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane, + u32 size, u32 lane) +{ + u32 i; + + for (i = 0; i < size; i++) + ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane), + cfg_lane[i].val, cfg_lane[i].mask); +} + +static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes) +{ + u32 i; + + ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM); + ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM); + + for (i = 0; i < num_lanes; i++) + ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i); + + return 0; +} + +static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes) +{ + /* Bring SerDes out of Reset */ + ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET); + if (serdes->intf == SERDES_PHY_PCSR) + ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET); + + /* Enable CMU and COMLANE */ + ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff); + if (serdes->intf == SERDES_PHY_PCSR) + ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff); + + ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff); +} + +static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes) +{ + writel(serdes_cfg_pll_enable[serdes->intf], + base + SERDES_PLL_CTL_REG); +} + +static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane) +{ + if (reset) + ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), + 0x1, SERDES_LANE_RESET); + else + ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), + 0x0, SERDES_LANE_RESET); +} + +static void ks2_serdes_lane_enable(u32 base, + struct ks2_serdes *serdes, u32 lane) +{ + /* Bring lane out of reset */ + ks2_serdes_lane_reset(base, 0, lane); + + writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf, + serdes->rate_mode), + base + SERDES_LANE_CTL_STATUS_REG(lane)); + + /* Set NES bit if Loopback Enabled */ + if (serdes->loopback) + ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane), + 0x1, SERDES_LANE_LOOPBACK); +} + +int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes) +{ + int i; + int ret = 0; + + for (i = 0; i < ARRAY_SIZE(cfgs); i++) + if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate) + break; + + if (i >= ARRAY_SIZE(cfgs)) { + puts("Cannot find keystone SerDes configuration"); + return -EINVAL; + } + + ks2_serdes_init_cfg(base, &cfgs[i], num_lanes); + + ks2_serdes_cmu_comlane_enable(base, serdes); + for (i = 0; i < num_lanes; i++) + ks2_serdes_lane_enable(base, serdes, i); + + ks2_serdes_pll_enable(base, serdes); + + return ret; +} diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index c50dd1583f..981ed614b1 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -5,29 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libsound.o - -COBJS-$(CONFIG_SOUND) += sound.o -COBJS-$(CONFIG_I2S) += samsung-i2s.o -COBJS-$(CONFIG_SOUND_WM8994) += wm8994.o -COBJS-$(CONFIG_SOUND_MAX98095) += max98095.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -# +obj-$(CONFIG_SOUND) += sound.o +obj-$(CONFIG_I2S) += sound-i2s.o +obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o +obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o +obj-$(CONFIG_SOUND_WM8994) += wm8994.o +obj-$(CONFIG_SOUND_MAX98095) += max98095.o diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c index d69db58dcd..febf4195ba 100644 --- a/drivers/sound/max98095.c +++ b/drivers/sound/max98095.c @@ -52,7 +52,7 @@ int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, static int max98095_i2c_write(unsigned int reg, unsigned char data) { debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n", - __func__, reg, data); + __func__, reg, data); return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1); } @@ -71,7 +71,7 @@ static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data) ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1); if (ret != 0) { debug("%s: Error while reading register %#04x\n", - __func__, reg); + __func__, reg); return -1; } @@ -138,43 +138,57 @@ static int rate_value(int rate, u8 *value) * @return -1 for error and 0 Success. */ static int max98095_hw_params(struct max98095_priv *max98095, - unsigned int rate, unsigned int bits_per_sample) + enum en_max_audio_interface aif_id, + unsigned int rate, unsigned int bits_per_sample) { u8 regval; int error; + unsigned short M98095_DAI_CLKMODE; + unsigned short M98095_DAI_FORMAT; + unsigned short M98095_DAI_FILTERS; + + if (aif_id == AIF1) { + M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE; + M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT; + M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS; + } else { + M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE; + M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT; + M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS; + } switch (bits_per_sample) { case 16: - error = max98095_update_bits(M98095_034_DAI2_FORMAT, - M98095_DAI_WS, 0); + error = max98095_update_bits(M98095_DAI_FORMAT, + M98095_DAI_WS, 0); break; case 24: - error = max98095_update_bits(M98095_034_DAI2_FORMAT, - M98095_DAI_WS, M98095_DAI_WS); + error = max98095_update_bits(M98095_DAI_FORMAT, + M98095_DAI_WS, M98095_DAI_WS); break; default: debug("%s: Illegal bits per sample %d.\n", - __func__, bits_per_sample); + __func__, bits_per_sample); return -1; } if (rate_value(rate, ®val)) { debug("%s: Failed to set sample rate to %d.\n", - __func__, rate); + __func__, rate); return -1; } max98095->rate = rate; - error |= max98095_update_bits(M98095_031_DAI2_CLKMODE, - M98095_CLKMODE_MASK, regval); + error |= max98095_update_bits(M98095_DAI_CLKMODE, + M98095_CLKMODE_MASK, regval); /* Update sample rate mode */ if (rate < 50000) - error |= max98095_update_bits(M98095_038_DAI2_FILTERS, - M98095_DAI_DHF, 0); + error |= max98095_update_bits(M98095_DAI_FILTERS, + M98095_DAI_DHF, 0); else - error |= max98095_update_bits(M98095_038_DAI2_FILTERS, - M98095_DAI_DHF, M98095_DAI_DHF); + error |= max98095_update_bits(M98095_DAI_FILTERS, + M98095_DAI_DHF, M98095_DAI_DHF); if (error < 0) { debug("%s: Error setting hardware params.\n", __func__); @@ -193,7 +207,7 @@ static int max98095_hw_params(struct max98095_priv *max98095, * @return -1 for error and 0 success. */ static int max98095_set_sysclk(struct max98095_priv *max98095, - unsigned int freq) + unsigned int freq) { int error = 0; @@ -235,22 +249,39 @@ static int max98095_set_sysclk(struct max98095_priv *max98095, * * @return -1 for error and 0 Success. */ -static int max98095_set_fmt(struct max98095_priv *max98095, int fmt) +static int max98095_set_fmt(struct max98095_priv *max98095, int fmt, + enum en_max_audio_interface aif_id) { u8 regval = 0; int error = 0; + unsigned short M98095_DAI_CLKCFG_HI; + unsigned short M98095_DAI_CLKCFG_LO; + unsigned short M98095_DAI_FORMAT; + unsigned short M98095_DAI_CLOCK; if (fmt == max98095->fmt) return 0; max98095->fmt = fmt; + if (aif_id == AIF1) { + M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI; + M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO; + M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT; + M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK; + } else { + M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI; + M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO; + M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT; + M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK; + } + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* Slave mode PLL */ - error |= max98095_i2c_write(M98095_032_DAI2_CLKCFG_HI, + error |= max98095_i2c_write(M98095_DAI_CLKCFG_HI, 0x80); - error |= max98095_i2c_write(M98095_033_DAI2_CLKCFG_LO, + error |= max98095_i2c_write(M98095_DAI_CLKCFG_LO, 0x00); break; case SND_SOC_DAIFMT_CBM_CFM: @@ -292,12 +323,13 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt) return -1; } - error |= max98095_update_bits(M98095_034_DAI2_FORMAT, - M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | - M98095_DAI_WCI, regval); + error |= max98095_update_bits(M98095_DAI_FORMAT, + M98095_DAI_MAS | M98095_DAI_DLY | + M98095_DAI_BCI | M98095_DAI_WCI, + regval); - error |= max98095_i2c_write(M98095_035_DAI2_CLOCK, - M98095_DAI_BSEL64); + error |= max98095_i2c_write(M98095_DAI_CLOCK, + M98095_DAI_BSEL64); if (error < 0) { debug("%s: Error setting i2s format.\n", __func__); @@ -354,7 +386,8 @@ static int max98095_reset(void) * * @returns -1 for error and 0 Success. */ -static int max98095_device_init(struct max98095_priv *max98095) +static int max98095_device_init(struct max98095_priv *max98095, + enum en_max_audio_interface aif_id) { unsigned char id; int error = 0; @@ -374,7 +407,7 @@ static int max98095_device_init(struct max98095_priv *max98095) error = max98095_i2c_read(M98095_0FF_REV_ID, &id); if (error < 0) { debug("%s: Failure reading hardware revision: %d\n", - __func__, id); + __func__, id); goto err_access; } debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A'); @@ -385,26 +418,28 @@ static int max98095_device_init(struct max98095_priv *max98095) * initialize registers to hardware default configuring audio * interface2 to DAC */ - error |= max98095_i2c_write(M98095_048_MIX_DAC_LR, - M98095_DAI2M_TO_DACL|M98095_DAI2M_TO_DACR); + if (aif_id == AIF1) + error |= max98095_i2c_write(M98095_048_MIX_DAC_LR, + M98095_DAI1L_TO_DACL | + M98095_DAI1R_TO_DACR); + else + error |= max98095_i2c_write(M98095_048_MIX_DAC_LR, + M98095_DAI2M_TO_DACL | + M98095_DAI2M_TO_DACR); error |= max98095_i2c_write(M98095_092_PWR_EN_OUT, - M98095_SPK_SPREADSPECTRUM); - error |= max98095_i2c_write(M98095_045_CFG_DSP, M98095_DSPNORMAL); + M98095_SPK_SPREADSPECTRUM); error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL); - - error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG, - M98095_S1NORMAL|M98095_SDATA); - - error |= max98095_i2c_write(M98095_036_DAI2_IOCFG, - M98095_S2NORMAL|M98095_SDATA); - - error |= max98095_i2c_write(M98095_040_DAI3_IOCFG, - M98095_S3NORMAL|M98095_SDATA); + if (aif_id == AIF1) + error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG, + M98095_S1NORMAL | M98095_SDATA); + else + error |= max98095_i2c_write(M98095_036_DAI2_IOCFG, + M98095_S2NORMAL | M98095_SDATA); /* take the codec out of the shut down */ error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN, - M98095_SHDNRUN); + M98095_SHDNRUN); /* route DACL and DACR output to HO and Spekers */ error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */ error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */ @@ -422,7 +457,10 @@ static int max98095_device_init(struct max98095_priv *max98095) /* Enable DAIs */ error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30); - error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07); + if (aif_id == AIF1) + error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x01); + else + error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07); err_access: if (error < 0) @@ -432,8 +470,9 @@ err_access: } static int max98095_do_init(struct sound_codec_info *pcodec_info, - int sampling_rate, int mclk_freq, - int bits_per_sample) + enum en_max_audio_interface aif_id, + int sampling_rate, int mclk_freq, + int bits_per_sample) { int ret = 0; @@ -443,15 +482,15 @@ static int max98095_do_init(struct sound_codec_info *pcodec_info, /* shift the device address by 1 for 7 bit addressing */ g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1; - if (pcodec_info->codec_type == CODEC_MAX_98095) + if (pcodec_info->codec_type == CODEC_MAX_98095) { g_max98095_info.devtype = MAX98095; - else { + } else { debug("%s: Codec id [%d] not defined\n", __func__, - pcodec_info->codec_type); + pcodec_info->codec_type); return -1; } - ret = max98095_device_init(&g_max98095_info); + ret = max98095_device_init(&g_max98095_info, aif_id); if (ret < 0) { debug("%s: max98095 codec chip init failed\n", __func__); return ret; @@ -463,14 +502,15 @@ static int max98095_do_init(struct sound_codec_info *pcodec_info, return ret; } - ret = max98095_hw_params(&g_max98095_info, sampling_rate, - bits_per_sample); + ret = max98095_hw_params(&g_max98095_info, aif_id, sampling_rate, + bits_per_sample); if (ret == 0) { ret = max98095_set_fmt(&g_max98095_info, - SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBS_CFS); + SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS, + aif_id); } return ret; @@ -529,8 +569,9 @@ static int get_max98095_codec_values(struct sound_codec_info *pcodec_info, } /* max98095 Device Initialisation */ -int max98095_init(const void *blob, int sampling_rate, int mclk_freq, - int bits_per_sample) +int max98095_init(const void *blob, enum en_max_audio_interface aif_id, + int sampling_rate, int mclk_freq, + int bits_per_sample) { int ret; int old_bus = i2c_get_bus_num(); @@ -538,12 +579,12 @@ int max98095_init(const void *blob, int sampling_rate, int mclk_freq, if (get_max98095_codec_values(pcodec_info, blob) < 0) { debug("FDT Codec values failed\n"); - return -1; + return -1; } i2c_set_bus_num(pcodec_info->i2c_bus); - ret = max98095_do_init(pcodec_info, sampling_rate, mclk_freq, - bits_per_sample); + ret = max98095_do_init(pcodec_info, aif_id, sampling_rate, mclk_freq, + bits_per_sample); i2c_set_bus_num(old_bus); return ret; diff --git a/drivers/sound/max98095.h b/drivers/sound/max98095.h index ae5eb14dbb..44b1e3a97b 100644 --- a/drivers/sound/max98095.h +++ b/drivers/sound/max98095.h @@ -11,6 +11,12 @@ #ifndef _MAX98095_H #define _MAX98095_H +/* Available audio interface ports in wm8994 codec */ +enum en_max_audio_interface { + AIF1 = 1, + AIF2, +}; + /* * MAX98095 Registers Definition */ @@ -305,7 +311,7 @@ * * @returns -1 for error and 0 Success. */ -int max98095_init(const void *blob, int sampling_rate, int mclk_freq, - int bits_per_sample); +int max98095_init(const void *blob, enum en_max_audio_interface aif_id, + int sampling_rate, int mclk_freq, int bits_per_sample); #endif diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c index 49921e5526..47f155f85d 100644 --- a/drivers/sound/samsung-i2s.c +++ b/drivers/sound/samsung-i2s.c @@ -65,9 +65,7 @@ static void i2s_txctrl(struct i2s_reg *i2s_reg, int on) if (on) { con |= CON_ACTIVE; con &= ~CON_TXCH_PAUSE; - } else { - con |= CON_TXCH_PAUSE; con &= ~CON_ACTIVE; } @@ -172,7 +170,7 @@ int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) break; default: debug("%s: Invalid format priority [0x%x]\n", __func__, - (fmt & SND_SOC_DAIFMT_FORMAT_MASK)); + (fmt & SND_SOC_DAIFMT_FORMAT_MASK)); return -1; } @@ -191,7 +189,7 @@ int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) break; default: debug("%s: Invalid clock ploarity input [0x%x]\n", __func__, - (fmt & SND_SOC_DAIFMT_INV_MASK)); + (fmt & SND_SOC_DAIFMT_INV_MASK)); return -1; } @@ -209,7 +207,7 @@ int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) break; default: debug("%s: Invalid master selection [0x%x]\n", __func__, - (fmt & SND_SOC_DAIFMT_MASTER_MASK)); + (fmt & SND_SOC_DAIFMT_MASTER_MASK)); return -1; } @@ -250,7 +248,7 @@ int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc) break; default: debug("%s: Invalid sample size input [0x%x]\n", - __func__, blc); + __func__, blc); return -1; } writel(mod, &i2s_reg->mod); @@ -301,27 +299,58 @@ int i2s_tx_init(struct i2stx_info *pi2s_tx) int ret; struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address; + if (pi2s_tx->id == 0) { + /* Initialize GPIO for I2S-0 */ + exynos_pinmux_config(PERIPH_ID_I2S0, 0); + + /* Set EPLL Clock */ + ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4); + } else if (pi2s_tx->id == 1) { + /* Initialize GPIO for I2S-1 */ + exynos_pinmux_config(PERIPH_ID_I2S1, 0); + + /* Set EPLL Clock */ + ret = set_epll_clk(pi2s_tx->audio_pll_clk); + } else { + debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id); + return -1; + } - /* Initialize GPIO for I2s */ - exynos_pinmux_config(PERIPH_ID_I2S1, 0); - - /* Set EPLL Clock */ - ret = set_epll_clk(pi2s_tx->audio_pll_clk); if (ret != 0) { - debug("%s: epll clock set rate falied\n", __func__); + debug("%s: epll clock set rate failed\n", __func__); return -1; } - /* Select Clk Source for Audio1 */ - set_i2s_clk_source(); + /* Select Clk Source for Audio 0 or 1 */ + ret = set_i2s_clk_source(pi2s_tx->id); + if (ret == -1) { + debug("%s: unsupported clock for i2s-%d\n", __func__, + pi2s_tx->id); + return -1; + } + + if (pi2s_tx->id == 0) { + /*Reset the i2s module */ + writel(CON_RESET, &i2s_reg->con); - /* Set Prescaler to get MCLK */ - set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk, - (pi2s_tx->samplingrate * (pi2s_tx->rfs))); + writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod); + /* set i2s prescaler */ + writel(PSREN | PSVAL, &i2s_reg->psr); + } else { + /* Set Prescaler to get MCLK */ + ret = set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk, + (pi2s_tx->samplingrate * (pi2s_tx->rfs)), + pi2s_tx->id); + } + if (ret == -1) { + debug("%s: unsupported prescalar for i2s-%d\n", __func__, + pi2s_tx->id); + return -1; + } /* Configure I2s format */ ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBM_CFM)); + SND_SOC_DAIFMT_CBM_CFM)); if (ret == 0) { i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs); ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample); diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c new file mode 100644 index 0000000000..5599bb948f --- /dev/null +++ b/drivers/sound/sandbox.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int sound_play(uint32_t msec, uint32_t frequency) +{ + sandbox_sdl_sound_start(frequency); + mdelay(msec); + sandbox_sdl_sound_stop(); + + return 0; +} + +int sound_init(const void *blob) +{ + return sandbox_sdl_sound_init(); +} diff --git a/drivers/sound/sound-i2s.c b/drivers/sound/sound-i2s.c new file mode 100644 index 0000000000..749bbbd031 --- /dev/null +++ b/drivers/sound/sound-i2s.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * R. Chandrasekar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wm8994.h" +#include "max98095.h" + +/* defines */ +#define SOUND_400_HZ 400 +#define SOUND_BITS_IN_BYTE 8 + +static struct i2stx_info g_i2stx_pri; + +/* + * get_sound_i2s_values gets values for i2s parameters + * + * @param i2stx_info i2s transmitter transfer param structure + * @param blob FDT blob if enabled else NULL + */ +static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob) +{ + int node; + int error = 0; + int base; + + node = fdt_path_offset(blob, "i2s"); + if (node <= 0) { + debug("EXYNOS_SOUND: No node for sound in device tree\n"); + return -1; + } + + /* + * Get the pre-defined sound specific values from FDT. + * All of these are expected to be correct otherwise + * wrong register values in i2s setup parameters + * may result in no sound play. + */ + base = fdtdec_get_addr(blob, node, "reg"); + if (base == FDT_ADDR_T_NONE) { + debug("%s: Missing i2s base\n", __func__); + return -1; + } + i2s->base_address = base; + + i2s->audio_pll_clk = fdtdec_get_int(blob, + node, "samsung,i2s-epll-clock-frequency", -1); + error |= i2s->audio_pll_clk; + debug("audio_pll_clk = %d\n", i2s->audio_pll_clk); + i2s->samplingrate = fdtdec_get_int(blob, + node, "samsung,i2s-sampling-rate", -1); + error |= i2s->samplingrate; + debug("samplingrate = %d\n", i2s->samplingrate); + i2s->bitspersample = fdtdec_get_int(blob, + node, "samsung,i2s-bits-per-sample", -1); + error |= i2s->bitspersample; + debug("bitspersample = %d\n", i2s->bitspersample); + i2s->channels = fdtdec_get_int(blob, + node, "samsung,i2s-channels", -1); + error |= i2s->channels; + debug("channels = %d\n", i2s->channels); + i2s->rfs = fdtdec_get_int(blob, + node, "samsung,i2s-lr-clk-framesize", -1); + error |= i2s->rfs; + debug("rfs = %d\n", i2s->rfs); + i2s->bfs = fdtdec_get_int(blob, + node, "samsung,i2s-bit-clk-framesize", -1); + error |= i2s->bfs; + debug("bfs = %d\n", i2s->bfs); + + i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1); + error |= i2s->id; + debug("id = %d\n", i2s->id); + + if (error == -1) { + debug("fail to get sound i2s node properties\n"); + return -1; + } + + return 0; +} + +/* + * Init codec + * + * @param blob FDT blob + * @param pi2s_tx i2s parameters required by codec + * @return int value, 0 for success + */ +static int codec_init(const void *blob, struct i2stx_info *pi2s_tx) +{ + int ret; + const char *codectype; + int node; + + /* Get the node from FDT for sound */ + node = fdt_path_offset(blob, "i2s"); + if (node <= 0) { + debug("EXYNOS_SOUND: No node for sound in device tree\n"); + debug("node = %d\n", node); + return -1; + } + + /* + * Get the pre-defined sound codec specific values from FDT. + * All of these are expected to be correct otherwise sound + * can not be played + */ + codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL); + debug("device = %s\n", codectype); + if (!strcmp(codectype, "wm8994")) { + /* Check the codec type and initialise the same */ + ret = wm8994_init(blob, pi2s_tx->id + 1, + pi2s_tx->samplingrate, + (pi2s_tx->samplingrate * (pi2s_tx->rfs)), + pi2s_tx->bitspersample, pi2s_tx->channels); + } else if (!strcmp(codectype, "max98095")) { + ret = max98095_init(blob, pi2s_tx->id + 1, + pi2s_tx->samplingrate, + (pi2s_tx->samplingrate * (pi2s_tx->rfs)), + pi2s_tx->bitspersample); + } else { + debug("%s: Unknown codec type %s\n", __func__, codectype); + return -1; + } + + if (ret) { + debug("%s: Codec init failed\n", __func__); + return -1; + } + + return 0; +} + +int sound_init(const void *blob) +{ + int ret; + struct i2stx_info *pi2s_tx = &g_i2stx_pri; + + /* Get the I2S Values */ + if (get_sound_i2s_values(pi2s_tx, blob) < 0) { + debug(" FDT I2S values failed\n"); + return -1; + } + + if (codec_init(blob, pi2s_tx) < 0) { + debug(" Codec init failed\n"); + return -1; + } + + ret = i2s_tx_init(pi2s_tx); + if (ret) { + debug("%s: Failed to init i2c transmit: ret=%d\n", __func__, + ret); + return ret; + } + + + return ret; +} + +int sound_play(uint32_t msec, uint32_t frequency) +{ + unsigned int *data; + unsigned long data_size; + unsigned int ret = 0; + + /*Buffer length computation */ + data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels; + data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE); + data = malloc(data_size); + + if (data == NULL) { + debug("%s: malloc failed\n", __func__); + return -1; + } + + sound_create_square_wave((unsigned short *)data, + data_size / sizeof(unsigned short), + frequency); + + while (msec >= 1000) { + ret = i2s_transfer_tx_data(&g_i2stx_pri, data, + (data_size / sizeof(int))); + msec -= 1000; + } + if (msec) { + unsigned long size = + (data_size * msec) / (sizeof(int) * 1000); + + ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size); + } + + free(data); + + return ret; +} diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c index 6fcc75da58..9dda2dba82 100644 --- a/drivers/sound/sound.c +++ b/drivers/sound/sound.c @@ -5,187 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include -#include -#include -#include -#include -#include #include -#include -#include "wm8994.h" -#include "max98095.h" -/* defines */ -#define SOUND_400_HZ 400 -#define SOUND_BITS_IN_BYTE 8 - -static struct i2stx_info g_i2stx_pri; - -/* - * get_sound_i2s_values gets values for i2s parameters - * - * @param i2stx_info i2s transmitter transfer param structure - * @param blob FDT blob if enabled else NULL - */ -static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob) -{ -#ifdef CONFIG_OF_CONTROL - int node; - int error = 0; - int base; - - node = fdtdec_next_compatible(blob, 0, - COMPAT_SAMSUNG_EXYNOS5_SOUND); - if (node <= 0) { - debug("EXYNOS_SOUND: No node for sound in device tree\n"); - return -1; - } - - /* - * Get the pre-defined sound specific values from FDT. - * All of these are expected to be correct otherwise - * wrong register values in i2s setup parameters - * may result in no sound play. - */ - base = fdtdec_get_addr(blob, node, "reg"); - if (base == FDT_ADDR_T_NONE) { - debug("%s: Missing i2s base\n", __func__); - return -1; - } - i2s->base_address = base; - - i2s->audio_pll_clk = fdtdec_get_int(blob, - node, "samsung,i2s-epll-clock-frequency", -1); - error |= i2s->audio_pll_clk; - debug("audio_pll_clk = %d\n", i2s->audio_pll_clk); - i2s->samplingrate = fdtdec_get_int(blob, - node, "samsung,i2s-sampling-rate", -1); - error |= i2s->samplingrate; - debug("samplingrate = %d\n", i2s->samplingrate); - i2s->bitspersample = fdtdec_get_int(blob, - node, "samsung,i2s-bits-per-sample", -1); - error |= i2s->bitspersample; - debug("bitspersample = %d\n", i2s->bitspersample); - i2s->channels = fdtdec_get_int(blob, - node, "samsung,i2s-channels", -1); - error |= i2s->channels; - debug("channels = %d\n", i2s->channels); - i2s->rfs = fdtdec_get_int(blob, - node, "samsung,i2s-lr-clk-framesize", -1); - error |= i2s->rfs; - debug("rfs = %d\n", i2s->rfs); - i2s->bfs = fdtdec_get_int(blob, - node, "samsung,i2s-bit-clk-framesize", -1); - error |= i2s->bfs; - debug("bfs = %d\n", i2s->bfs); - if (error == -1) { - debug("fail to get sound i2s node properties\n"); - return -1; - } -#else - i2s->base_address = samsung_get_base_i2s(); - i2s->audio_pll_clk = I2S_PLL_CLK; - i2s->samplingrate = I2S_SAMPLING_RATE; - i2s->bitspersample = I2S_BITS_PER_SAMPLE; - i2s->channels = I2S_CHANNELS; - i2s->rfs = I2S_RFS; - i2s->bfs = I2S_BFS; -#endif - return 0; -} - -/* - * Init codec - * - * @param blob FDT blob - * @param pi2s_tx i2s parameters required by codec - * @return int value, 0 for success - */ -static int codec_init(const void *blob, struct i2stx_info *pi2s_tx) -{ - int ret; - const char *codectype; -#ifdef CONFIG_OF_CONTROL - int node; - - /* Get the node from FDT for sound */ - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SOUND); - if (node <= 0) { - debug("EXYNOS_SOUND: No node for sound in device tree\n"); - debug("node = %d\n", node); - return -1; - } - - /* - * Get the pre-defined sound codec specific values from FDT. - * All of these are expected to be correct otherwise sound - * can not be played - */ - codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL); - debug("device = %s\n", codectype); -#else - codectype = AUDIO_CODEC; -#endif - if (!strcmp(codectype, "wm8994")) { - /* Check the codec type and initialise the same */ - ret = wm8994_init(blob, WM8994_AIF2, - pi2s_tx->samplingrate, - (pi2s_tx->samplingrate * (pi2s_tx->rfs)), - pi2s_tx->bitspersample, pi2s_tx->channels); - } else if (!strcmp(codectype, "max98095")) { - ret = max98095_init(blob, pi2s_tx->samplingrate, - (pi2s_tx->samplingrate * (pi2s_tx->rfs)), - pi2s_tx->bitspersample); - } else { - debug("%s: Unknown codec type %s\n", __func__, codectype); - return -1; - } - - if (ret) { - debug("%s: Codec init failed\n", __func__); - return -1; - } - - return 0; -} - -int sound_init(const void *blob) -{ - int ret; - struct i2stx_info *pi2s_tx = &g_i2stx_pri; - - /* Get the I2S Values */ - if (get_sound_i2s_values(pi2s_tx, blob) < 0) { - debug(" FDT I2S values failed\n"); - return -1; - } - - if (codec_init(blob, pi2s_tx) < 0) { - debug(" Codec init failed\n"); - return -1; - } - - ret = i2s_tx_init(pi2s_tx); - if (ret) { - debug("%s: Failed to init i2c transmit: ret=%d\n", __func__, - ret); - return ret; - } - - - return ret; -} - -/* - * Generates square wave sound data for 1 second - * - * @param data data buffer pointer - * @param size size of the buffer - * @param freq frequency of the wave - */ -static void sound_prepare_buffer(unsigned short *data, int size, uint32_t freq) +void sound_create_square_wave(unsigned short *data, int size, uint32_t freq) { const int sample = 48000; const unsigned short amplitude = 16000; /* between 1 and 32767 */ @@ -212,39 +35,3 @@ static void sound_prepare_buffer(unsigned short *data, int size, uint32_t freq) } } } - -int sound_play(uint32_t msec, uint32_t frequency) -{ - unsigned int *data; - unsigned long data_size; - unsigned int ret = 0; - - /*Buffer length computation */ - data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels; - data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE); - data = malloc(data_size); - - if (data == NULL) { - debug("%s: malloc failed\n", __func__); - return -1; - } - - sound_prepare_buffer((unsigned short *)data, - data_size / sizeof(unsigned short), frequency); - - while (msec >= 1000) { - ret = i2s_transfer_tx_data(&g_i2stx_pri, data, - (data_size / sizeof(int))); - msec -= 1000; - } - if (msec) { - unsigned long size = - (data_size * msec) / (sizeof(int) * 1000); - - ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size); - } - - free(data); - - return ret; -} diff --git a/drivers/sound/wm8994.c b/drivers/sound/wm8994.c index 37e354c5c8..f8e9a6eadd 100644 --- a/drivers/sound/wm8994.c +++ b/drivers/sound/wm8994.c @@ -432,12 +432,12 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) int ret; /* AIF(1/0) register adress offset calculated */ - if (aif) + if (aif-1) offset = 4; else offset = 0; - switch (wm8994->sysclk[aif]) { + switch (wm8994->sysclk[aif-1]) { case WM8994_SYSCLK_MCLK1: reg1 |= SEL_MCLK1; rate = wm8994->mclk[0]; @@ -460,7 +460,7 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) default: debug("%s: Invalid input clock selection [%d]\n", - __func__, wm8994->sysclk[aif]); + __func__, wm8994->sysclk[aif-1]); return -1; } @@ -470,13 +470,18 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) reg1 |= WM8994_AIF1CLK_DIV; } - wm8994->aifclk[aif] = rate; + wm8994->aifclk[aif-1] = rate; ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset, WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, reg1); - ret |= wm8994_update_bits(WM8994_CLOCKING_1, + if (aif == WM8994_AIF1) + ret |= wm8994_update_bits(WM8994_CLOCKING_1, + WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK, + WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); + else if (aif == WM8994_AIF2) + ret |= wm8994_update_bits(WM8994_CLOCKING_1, WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); @@ -536,7 +541,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, break; if (i == ARRAY_SIZE(opclk_divs)) { debug("%s frequency divisor not found\n", - __func__); + __func__); return -1; } ret = wm8994_update_bits(WM8994_CLOCKING_2, @@ -554,7 +559,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, return -1; } - ret |= configure_aif_clock(wm8994, aif_id - 1); + ret |= configure_aif_clock(wm8994, aif_id); if (ret < 0) { debug("%s: codec register access error\n", __func__); @@ -607,6 +612,38 @@ static int wm8994_init_volume_aif2_dac1(void) return 0; } +/* + * Initializes Volume for AIF1 to HP path + * + * @returns -1 for error and 0 Success. + * + */ +static int wm8994_init_volume_aif1_dac1(void) +{ + int ret = 0; + + /* Unmute AIF1DAC */ + ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000); + + ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, + WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | + WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); + + ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, + WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | + WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); + /* Head Phone Volume */ + ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); + ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); + + if (ret < 0) { + debug("%s: codec register access error\n", __func__); + return -1; + } + + return 0; +} + /* * Intialise wm8994 codec device * @@ -614,7 +651,8 @@ static int wm8994_init_volume_aif2_dac1(void) * * @returns -1 for error and 0 Success. */ -static int wm8994_device_init(struct wm8994_priv *wm8994) +static int wm8994_device_init(struct wm8994_priv *wm8994, + enum en_audio_interface aif_id) { const char *devname; unsigned short reg_data; @@ -661,13 +699,30 @@ static int wm8994_device_init(struct wm8994_priv *wm8994) ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA); - /* Power enable for AIF2 and DAC1 */ - ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, - WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | - WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, - WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA | - WM8994_DAC1R_ENA); - + if (aif_id == WM8994_AIF1) { + ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2, + WM8994_TSHUT_ENA | WM8994_MIXINL_ENA | + WM8994_MIXINR_ENA | WM8994_IN2L_ENA | + WM8994_IN2R_ENA); + + ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4, + WM8994_ADCL_ENA | WM8994_ADCR_ENA | + WM8994_AIF1ADC1R_ENA | + WM8994_AIF1ADC1L_ENA); + + /* Power enable for AIF1 and DAC1 */ + ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5, + WM8994_AIF1DACL_ENA | + WM8994_AIF1DACR_ENA | + WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); + } else if (aif_id == WM8994_AIF2) { + /* Power enable for AIF2 and DAC1 */ + ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, + WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | + WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, + WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | + WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); + } /* Head Phone Initialisation */ ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK, @@ -695,35 +750,49 @@ static int wm8994_device_init(struct wm8994_priv *wm8994) ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2, WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R); - /* Routing AIF2 to DAC1 */ - ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, - WM8994_AIF2DACL_TO_DAC1L_MASK, - WM8994_AIF2DACL_TO_DAC1L); - - ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, - WM8994_AIF2DACR_TO_DAC1R_MASK, - WM8994_AIF2DACR_TO_DAC1R); - - /* GPIO Settings for AIF2 */ - /* B CLK */ - ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | - WM8994_GPIO_FUNCTION_MASK , - WM8994_GPIO_DIR_OUTPUT | - WM8994_GPIO_FUNCTION_I2S_CLK); - - /* LR CLK */ - ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | - WM8994_GPIO_FUNCTION_MASK, - WM8994_GPIO_DIR_OUTPUT | - WM8994_GPIO_FUNCTION_I2S_CLK); - - /* DATA */ - ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | - WM8994_GPIO_FUNCTION_MASK, - WM8994_GPIO_DIR_OUTPUT | - WM8994_GPIO_FUNCTION_I2S_CLK); - - ret |= wm8994_init_volume_aif2_dac1(); + if (aif_id == WM8994_AIF1) { + /* Routing AIF1 to DAC1 */ + ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING, + WM8994_AIF1DAC1L_TO_DAC1L); + + ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING, + WM8994_AIF1DAC1R_TO_DAC1R); + + /* GPIO Settings for AIF1 */ + ret |= wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT + | WM8994_GPIO_FUNCTION_I2S_CLK + | WM8994_GPIO_INPUT_DEBOUNCE); + + ret |= wm8994_init_volume_aif1_dac1(); + } else if (aif_id == WM8994_AIF2) { + /* Routing AIF2 to DAC1 */ + ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, + WM8994_AIF2DACL_TO_DAC1L_MASK, + WM8994_AIF2DACL_TO_DAC1L); + + ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, + WM8994_AIF2DACR_TO_DAC1R_MASK, + WM8994_AIF2DACR_TO_DAC1R); + + /* GPIO Settings for AIF2 */ + /* B CLK */ + ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | + WM8994_GPIO_FUNCTION_MASK , + WM8994_GPIO_DIR_OUTPUT); + + /* LR CLK */ + ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | + WM8994_GPIO_FUNCTION_MASK, + WM8994_GPIO_DIR_OUTPUT); + + /* DATA */ + ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | + WM8994_GPIO_FUNCTION_MASK, + WM8994_GPIO_DIR_OUTPUT); + + ret |= wm8994_init_volume_aif2_dac1(); + } + if (ret < 0) goto err; @@ -795,7 +864,7 @@ static int get_codec_values(struct sound_codec_info *pcodec_info, return 0; } -/*wm8994 Device Initialisation */ +/* WM8994 Device Initialisation */ int wm8994_init(const void *blob, enum en_audio_interface aif_id, int sampling_rate, int mclk_freq, int bits_per_sample, unsigned int channels) @@ -813,15 +882,15 @@ int wm8994_init(const void *blob, enum en_audio_interface aif_id, g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr; wm8994_i2c_init(pcodec_info->i2c_bus); - if (pcodec_info->codec_type == CODEC_WM_8994) + if (pcodec_info->codec_type == CODEC_WM_8994) { g_wm8994_info.type = WM8994; - else { + } else { debug("%s: Codec id [%d] not defined\n", __func__, - pcodec_info->codec_type); + pcodec_info->codec_type); return -1; } - ret = wm8994_device_init(&g_wm8994_info); + ret = wm8994_device_init(&g_wm8994_info, aif_id); if (ret < 0) { debug("%s: wm8994 codec chip init failed\n", __func__); return ret; diff --git a/drivers/sound/wm8994_registers.h b/drivers/sound/wm8994_registers.h index 1e987c2fd1..0aba2fdfd8 100644 --- a/drivers/sound/wm8994_registers.h +++ b/drivers/sound/wm8994_registers.h @@ -13,6 +13,7 @@ #define WM8994_SOFTWARE_RESET 0x00 #define WM8994_POWER_MANAGEMENT_1 0x01 #define WM8994_POWER_MANAGEMENT_2 0x02 +#define WM8994_POWER_MANAGEMENT_4 0x04 #define WM8994_POWER_MANAGEMENT_5 0x05 #define WM8994_LEFT_OUTPUT_VOLUME 0x1C #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D @@ -38,6 +39,7 @@ #define WM8994_AIF2_CONTROL_2 0x311 #define WM8994_AIF2_MASTER_SLAVE 0x312 #define WM8994_AIF2_BCLK 0x313 +#define WM8994_AIF1_DAC_FILTERS_1 0x420 #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 #define WM8994_AIF2_DAC_FILTERS_1 0x520 @@ -45,6 +47,7 @@ #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 #define WM8994_DAC1_LEFT_VOLUME 0x610 #define WM8994_DAC1_RIGHT_VOLUME 0x611 +#define WM8994_GPIO_1 0x700 #define WM8994_GPIO_3 0x702 #define WM8994_GPIO_4 0x703 #define WM8994_GPIO_5 0x704 @@ -82,6 +85,20 @@ /* OPCLK_ENA */ #define WM8994_OPCLK_ENA 0x0800 +#define WM8994_TSHUT_ENA 0x4000 +#define WM8994_MIXINL_ENA 0x0200 +#define WM8994_MIXINR_ENA 0x0100 +#define WM8994_IN2L_ENA 0x0080 +#define WM8994_IN2R_ENA 0x0020 + +/* + * R5 (0x04) - Power Management (4) + */ +#define WM8994_ADCL_ENA 0x0001 +#define WM8994_ADCR_ENA 0x0002 +#define WM8994_AIF1ADC1R_ENA 0x0100 +#define WM8994_AIF1ADC1L_ENA 0x0200 + /* * R5 (0x05) - Power Management (5) */ @@ -91,6 +108,12 @@ /* AIF2DACR_ENA */ #define WM8994_AIF2DACR_ENA 0x1000 #define WM8994_AIF2DACR_ENA_MASK 0x1000 +/* AIF1DACL_ENA */ +#define WM8994_AIF1DACL_ENA 0x0200 +#define WM8994_AIF1DACL_ENA_MASK 0x0200 +/* AIF1DACR_ENA */ +#define WM8994_AIF1DACR_ENA 0x0100 +#define WM8994_AIF1DACR_ENA_MASK 0x0100 /* DAC1L_ENA */ #define WM8994_DAC1L_ENA 0x0002 #define WM8994_DAC1L_ENA_MASK 0x0002 @@ -170,6 +193,9 @@ /* * R520 (0x208) - Clocking (1) */ +/* AIF1DSPCLK_ENA */ +#define WM8994_AIF1DSPCLK_ENA 0x0008 +#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF2DSPCLK_ENA */ #define WM8994_AIF2DSPCLK_ENA 0x0004 #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 @@ -254,6 +280,8 @@ /* AIF2DACL_TO_DAC1L */ #define WM8994_AIF2DACL_TO_DAC1L 0x0004 #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 +/* AIF1DAC1L_TO_DAC1L */ +#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* * R1538 (0x602) - DAC1 Right Mixer Routing @@ -261,6 +289,8 @@ /* AIF2DACR_TO_DAC1R */ #define WM8994_AIF2DACR_TO_DAC1R 0x0004 #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 +/* AIF1DAC1R_TO_DAC1R */ +#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* * R1552 (0x610) - DAC1 Left Volume @@ -285,11 +315,12 @@ * GPIO */ /* OUTPUT PIN */ -#define WM8994_GPIO_DIR_OUTPUT 0x8000 +#define WM8994_GPIO_DIR_OUTPUT 0x8000 /* GPIO PIN MASK */ -#define WM8994_GPIO_DIR_MASK 0xFFE0 +#define WM8994_GPIO_DIR_MASK 0xFFE0 /* I2S CLK */ -#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000 +#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0001 +#define WM8994_GPIO_INPUT_DEBOUNCE 0x0100 /* GPn FN */ -#define WM8994_GPIO_FUNCTION_MASK 0x001F +#define WM8994_GPIO_FUNCTION_MASK 0x001F #endif diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig new file mode 100644 index 0000000000..e1678e63e6 --- /dev/null +++ b/drivers/spi/Kconfig @@ -0,0 +1,6 @@ +config DM_SPI + bool "Enable Driver Model for SPI drivers" + depends on DM + help + If you want to use driver model for SPI drivers, say Y. + To use legacy SPI drivers, say N. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 019132e853..edbd520141 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -5,55 +5,47 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libspi.o - # There are many options which enable SPI, so make this library available -COBJS-y += spi.o - -COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o -COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o -COBJS-$(CONFIG_ARMADA100_SPI) += armada100_spi.o -COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o -COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o -COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o -COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o -COBJS-$(CONFIG_CF_SPI) += cf_spi.o -COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o -COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o -COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o -COBJS-$(CONFIG_ICH_SPI) += ich.o -COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o -COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o -COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o -COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o -COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o -COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o -COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o -COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o -COBJS-$(CONFIG_SH_SPI) += sh_spi.o -COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o -COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o -COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o -COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o -COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o -COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ifdef CONFIG_DM_SPI +obj-y += spi-uclass.o +obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o +obj-$(CONFIG_SOFT_SPI) += soft_spi.o +else +obj-y += spi.o +obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o +endif + +obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o +obj-$(CONFIG_ALTERA_SPI) += altera_spi.o +obj-$(CONFIG_ANDES_SPI) += andes_spi.o +obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o +obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BFIN_SPI) += bfin_spi.o +obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o +obj-$(CONFIG_CF_SPI) += cf_spi.o +obj-$(CONFIG_CF_QSPI) += cf_qspi.o +obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o +obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o +obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o +obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o +obj-$(CONFIG_ICH_SPI) += ich.o +obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o +obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o +obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MXC_SPI) += mxc_spi.o +obj-$(CONFIG_MXS_SPI) += mxs_spi.o +obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o +obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o +obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o +obj-$(CONFIG_SH_SPI) += sh_spi.o +obj-$(CONFIG_SH_QSPI) += sh_qspi.o +obj-$(CONFIG_FSL_ESPI) += fsl_espi.o +obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o +obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o +obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o +obj-$(CONFIG_TI_QSPI) += ti_qspi.o +obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o +obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o +obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index b53607a4ec..a4d03d97cf 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -5,65 +5,69 @@ * Copyright (c) 2005-2008 Analog Devices Inc. * Copyright (C) 2010 Thomas Chou * - * Licensed under the GPL-2 or later. + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include -#define ALTERA_SPI_RXDATA 0 -#define ALTERA_SPI_TXDATA 4 -#define ALTERA_SPI_STATUS 8 -#define ALTERA_SPI_CONTROL 12 -#define ALTERA_SPI_SLAVE_SEL 20 - -#define ALTERA_SPI_STATUS_ROE_MSK (0x8) -#define ALTERA_SPI_STATUS_TOE_MSK (0x10) -#define ALTERA_SPI_STATUS_TMT_MSK (0x20) -#define ALTERA_SPI_STATUS_TRDY_MSK (0x40) -#define ALTERA_SPI_STATUS_RRDY_MSK (0x80) -#define ALTERA_SPI_STATUS_E_MSK (0x100) - -#define ALTERA_SPI_CONTROL_IROE_MSK (0x8) -#define ALTERA_SPI_CONTROL_ITOE_MSK (0x10) -#define ALTERA_SPI_CONTROL_ITRDY_MSK (0x40) -#define ALTERA_SPI_CONTROL_IRRDY_MSK (0x80) -#define ALTERA_SPI_CONTROL_IE_MSK (0x100) -#define ALTERA_SPI_CONTROL_SSO_MSK (0x400) +#ifndef CONFIG_ALTERA_SPI_IDLE_VAL +#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff +#endif #ifndef CONFIG_SYS_ALTERA_SPI_LIST #define CONFIG_SYS_ALTERA_SPI_LIST { CONFIG_SYS_SPI_BASE } #endif +struct altera_spi_regs { + u32 rxdata; + u32 txdata; + u32 status; + u32 control; + u32 _reserved; + u32 slave_sel; +}; + +#define ALTERA_SPI_STATUS_ROE_MSK (1 << 3) +#define ALTERA_SPI_STATUS_TOE_MSK (1 << 4) +#define ALTERA_SPI_STATUS_TMT_MSK (1 << 5) +#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6) +#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7) +#define ALTERA_SPI_STATUS_E_MSK (1 << 8) + +#define ALTERA_SPI_CONTROL_IROE_MSK (1 << 3) +#define ALTERA_SPI_CONTROL_ITOE_MSK (1 << 4) +#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 << 6) +#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 << 7) +#define ALTERA_SPI_CONTROL_IE_MSK (1 << 8) +#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10) + static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST; struct altera_spi_slave { - struct spi_slave slave; - ulong base; + struct spi_slave slave; + struct altera_spi_regs *regs; }; #define to_altera_spi_slave(s) container_of(s, struct altera_spi_slave, slave) -__attribute__((weak)) -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +__weak int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus < ARRAY_SIZE(altera_spi_base_list) && cs < 32; } -__attribute__((weak)) -void spi_cs_activate(struct spi_slave *slave) +__weak void spi_cs_activate(struct spi_slave *slave) { struct altera_spi_slave *altspi = to_altera_spi_slave(slave); - writel(1 << slave->cs, altspi->base + ALTERA_SPI_SLAVE_SEL); - writel(ALTERA_SPI_CONTROL_SSO_MSK, altspi->base + ALTERA_SPI_CONTROL); + writel(1 << slave->cs, &altspi->regs->slave_sel); + writel(ALTERA_SPI_CONTROL_SSO_MSK, &altspi->regs->control); } -__attribute__((weak)) -void spi_cs_deactivate(struct spi_slave *slave) +__weak void spi_cs_deactivate(struct spi_slave *slave) { struct altera_spi_slave *altspi = to_altera_spi_slave(slave); - writel(0, altspi->base + ALTERA_SPI_CONTROL); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->control); + writel(0, &altspi->regs->slave_sel); } void spi_init(void) @@ -87,9 +91,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!altspi) return NULL; - altspi->base = altera_spi_base_list[bus]; - debug("%s: bus:%i cs:%i base:%lx\n", __func__, - bus, cs, altspi->base); + altspi->regs = (struct altera_spi_regs *)altera_spi_base_list[bus]; + debug("%s: bus:%i cs:%i base:%p\n", __func__, bus, cs, altspi->regs); return &altspi->slave; } @@ -105,8 +108,8 @@ int spi_claim_bus(struct spi_slave *slave) struct altera_spi_slave *altspi = to_altera_spi_slave(slave); debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - writel(0, altspi->base + ALTERA_SPI_CONTROL); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->control); + writel(0, &altspi->regs->slave_sel); return 0; } @@ -115,24 +118,22 @@ void spi_release_bus(struct spi_slave *slave) struct altera_spi_slave *altspi = to_altera_spi_slave(slave); debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->slave_sel); } -#ifndef CONFIG_ALTERA_SPI_IDLE_VAL -# define CONFIG_ALTERA_SPI_IDLE_VAL 0xff -#endif - int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct altera_spi_slave *altspi = to_altera_spi_slave(slave); /* assume spi core configured to do 8 bit transfers */ - uint bytes = bitlen / 8; - const uchar *txp = dout; - uchar *rxp = din; + unsigned int bytes = bitlen / 8; + const unsigned char *txp = dout; + unsigned char *rxp = din; + uint32_t reg, data, start; debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, - slave->bus, slave->cs, bitlen, bytes, flags); + slave->bus, slave->cs, bitlen, bytes, flags); + if (bitlen == 0) goto done; @@ -142,25 +143,40 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } /* empty read buffer */ - if (readl(altspi->base + ALTERA_SPI_STATUS) & - ALTERA_SPI_STATUS_RRDY_MSK) - readl(altspi->base + ALTERA_SPI_RXDATA); + if (readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK) + readl(&altspi->regs->rxdata); + if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); while (bytes--) { - uchar d = txp ? *txp++ : CONFIG_ALTERA_SPI_IDLE_VAL; - debug("%s: tx:%x ", __func__, d); - writel(d, altspi->base + ALTERA_SPI_TXDATA); - while (!(readl(altspi->base + ALTERA_SPI_STATUS) & - ALTERA_SPI_STATUS_RRDY_MSK)) - ; - d = readl(altspi->base + ALTERA_SPI_RXDATA); + if (txp) + data = *txp++; + else + data = CONFIG_ALTERA_SPI_IDLE_VAL; + + debug("%s: tx:%x ", __func__, data); + writel(data, &altspi->regs->txdata); + + start = get_timer(0); + while (1) { + reg = readl(&altspi->regs->status); + if (reg & ALTERA_SPI_STATUS_RRDY_MSK) + break; + if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { + printf("%s: Transmission timed out!\n", __func__); + goto done; + } + } + + data = readl(&altspi->regs->rxdata); if (rxp) - *rxp++ = d; - debug("rx:%x\n", d); + *rxp++ = data & 0xff; + + debug("rx:%x\n", data); } - done: + +done: if (flags & SPI_XFER_END) spi_cs_deactivate(slave); diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 8a5eddcbfd..a2e9c00ea6 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -102,33 +102,26 @@ void AT91F_SpiEnable(int cs) { unsigned long mode; + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); + mode &= ~AT91_SPI_PCS; + switch (cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); - mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + case 0: + mode |= AT91_SPI_PCS0_DATAFLASH_CARD << 16; break; - case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); - mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + case 1: + mode |= AT91_SPI_PCS1_DATAFLASH_CARD << 16; break; - case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); - mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + case 2: + mode |= AT91_SPI_PCS2_DATAFLASH_CARD << 16; break; case 3: - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); - mode &= 0xFFF0FFFF; - writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + mode |= AT91_SPI_PCS3_DATAFLASH_CARD << 16; break; } + writel(mode, ATMEL_BASE_SPI0 + AT91_SPI_MR); + /* SPI_Enable */ writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); } diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index d2409454f9..1538a235a5 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -94,3 +94,7 @@ static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave) readl(as->regs + ATMEL_SPI_##reg) #define spi_writel(as, reg, value) \ writel(value, as->regs + ATMEL_SPI_##reg) + +#if !defined(CONFIG_SYS_SPI_WRITE_TOUT) +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#endif diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index f7192c2340..71a31d0127 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -3,7 +3,7 @@ * * Copyright (c) 2005-2010 Analog Devices Inc. * - * Licensed under the GPL-2 or later. + * SPDX-License-Identifier: GPL-2.0+ */ /*#define DEBUG*/ @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -140,12 +141,12 @@ static const unsigned short cs_pins[][7] = { void spi_set_speed(struct spi_slave *slave, uint hz) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - ulong sclk; + ulong clk; u32 baud; - sclk = get_sclk(); + clk = get_spi_clk(); /* baud should be rounded up */ - baud = DIV_ROUND_UP(sclk, 2 * hz); + baud = DIV_ROUND_UP(clk, 2 * hz); if (baud < 2) baud = 2; else if (baud > (u16)-1) @@ -162,21 +163,22 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) { - debug("%s: invalid bus %u\n", __func__, bus); - return NULL; - } switch (bus) { #ifdef SPI0_CTL - case 0: mmr_base = SPI0_CTL; break; + case 0: + mmr_base = SPI0_CTL; break; #endif #ifdef SPI1_CTL - case 1: mmr_base = SPI1_CTL; break; + case 1: + mmr_base = SPI1_CTL; break; #endif #ifdef SPI2_CTL - case 2: mmr_base = SPI2_CTL; break; + case 2: + mmr_base = SPI2_CTL; break; #endif - default: return NULL; + default: + debug("%s: invalid bus %u\n", __func__, bus); + return NULL; } bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs); diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c index c25c4a9aea..eba01d16f5 100644 --- a/drivers/spi/bfin_spi6xx.c +++ b/drivers/spi/bfin_spi6xx.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -135,11 +136,11 @@ static const unsigned short cs_pins[][7] = { void spi_set_speed(struct spi_slave *slave, uint hz) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - ulong sclk; + ulong clk; u32 clock; - sclk = get_sclk1(); - clock = sclk / hz; + clk = get_spi_clk(); + clock = clk / hz; if (clock) clock--; bss->clock = clock; @@ -154,10 +155,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) { - debug("%s: invalid bus %u\n", __func__, bus); - return NULL; - } switch (bus) { #ifdef SPI0_REGBASE case 0: @@ -175,6 +172,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, break; #endif default: + debug("%s: invalid bus %u\n", __func__, bus); return NULL; } diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c new file mode 100644 index 0000000000..a75fc46e95 --- /dev/null +++ b/drivers/spi/cadence_qspi.c @@ -0,0 +1,344 @@ +/* + * Copyright (C) 2012 + * Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "cadence_qspi.h" + +#define CQSPI_STIG_READ 0 +#define CQSPI_STIG_WRITE 1 +#define CQSPI_INDIRECT_READ 2 +#define CQSPI_INDIRECT_WRITE 3 + +DECLARE_GLOBAL_DATA_PTR; + +static int cadence_spi_write_speed(struct udevice *bus, uint hz) +{ + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + + cadence_qspi_apb_config_baudrate_div(priv->regbase, + CONFIG_CQSPI_REF_CLK, hz); + + /* Reconfigure delay timing if speed is changed. */ + cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, + plat->tshsl_ns, plat->tsd2d_ns, + plat->tchsh_ns, plat->tslch_ns); + + return 0; +} + +/* Calibration sequence to determine the read data capture delay register */ +static int spi_calibration(struct udevice *bus) +{ + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + void *base = priv->regbase; + u8 opcode_rdid = 0x9F; + unsigned int idcode = 0, temp = 0; + int err = 0, i, range_lo = -1, range_hi = -1; + + /* start with slowest clock (1 MHz) */ + cadence_spi_write_speed(bus, 1000000); + + /* configure the read data capture delay register to 0 */ + cadence_qspi_apb_readdata_capture(base, 1, 0); + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(base); + + /* read the ID which will be our golden value */ + err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, + 3, (u8 *)&idcode); + if (err) { + puts("SF: Calibration failed (read)\n"); + return err; + } + + /* use back the intended clock and find low range */ + cadence_spi_write_speed(bus, plat->max_hz); + for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(base); + + /* reconfigure the read data capture delay register */ + cadence_qspi_apb_readdata_capture(base, 1, i); + + /* Enable back QSPI */ + cadence_qspi_apb_controller_enable(base); + + /* issue a RDID to get the ID value */ + err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, + 3, (u8 *)&temp); + if (err) { + puts("SF: Calibration failed (read)\n"); + return err; + } + + /* search for range lo */ + if (range_lo == -1 && temp == idcode) { + range_lo = i; + continue; + } + + /* search for range hi */ + if (range_lo != -1 && temp != idcode) { + range_hi = i - 1; + break; + } + range_hi = i; + } + + if (range_lo == -1) { + puts("SF: Calibration failed (low range)\n"); + return err; + } + + /* Disable QSPI for subsequent initialization */ + cadence_qspi_apb_controller_disable(base); + + /* configure the final value for read data capture delay register */ + cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2); + debug("SF: Read data capture delay calibrated to %i (%i - %i)\n", + (range_hi + range_lo) / 2, range_lo, range_hi); + + /* just to ensure we do once only when speed or chip select change */ + priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_cs = spi_chip_select(bus); + + return 0; +} + +static int cadence_spi_set_speed(struct udevice *bus, uint hz) +{ + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + int err; + + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(priv->regbase); + + cadence_spi_write_speed(bus, hz); + + /* Calibration required for different SCLK speed or chip select */ + if (priv->qspi_calibrated_hz != plat->max_hz || + priv->qspi_calibrated_cs != spi_chip_select(bus)) { + err = spi_calibration(bus); + if (err) + return err; + } + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(priv->regbase); + + debug("%s: speed=%d\n", __func__, hz); + + return 0; +} + +static int cadence_spi_probe(struct udevice *bus) +{ + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + + priv->regbase = plat->regbase; + priv->ahbbase = plat->ahbbase; + + if (!priv->qspi_is_init) { + cadence_qspi_apb_controller_init(plat); + priv->qspi_is_init = 1; + } + + return 0; +} + +static int cadence_spi_set_mode(struct udevice *bus, uint mode) +{ + struct cadence_spi_priv *priv = dev_get_priv(bus); + unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0; + unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0; + + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(priv->regbase); + + /* Set SPI mode */ + cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha); + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(priv->regbase); + + return 0; +} + +static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + void *base = priv->regbase; + u8 *cmd_buf = priv->cmd_buf; + size_t data_bytes; + int err = 0; + u32 mode = CQSPI_STIG_WRITE; + + if (flags & SPI_XFER_BEGIN) { + /* copy command to local buffer */ + priv->cmd_len = bitlen / 8; + memcpy(cmd_buf, dout, priv->cmd_len); + } + + if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { + /* if start and end bit are set, the data bytes is 0. */ + data_bytes = 0; + } else { + data_bytes = bitlen / 8; + } + debug("%s: len=%d [bytes]\n", __func__, data_bytes); + + /* Set Chip select */ + cadence_qspi_apb_chipselect(base, spi_chip_select(dev), + CONFIG_CQSPI_DECODER); + + if ((flags & SPI_XFER_END) || (flags == 0)) { + if (priv->cmd_len == 0) { + printf("QSPI: Error, command is empty.\n"); + return -1; + } + + if (din && data_bytes) { + /* read */ + /* Use STIG if no address. */ + if (!CQSPI_IS_ADDR(priv->cmd_len)) + mode = CQSPI_STIG_READ; + else + mode = CQSPI_INDIRECT_READ; + } else if (dout && !(flags & SPI_XFER_BEGIN)) { + /* write */ + if (!CQSPI_IS_ADDR(priv->cmd_len)) + mode = CQSPI_STIG_WRITE; + else + mode = CQSPI_INDIRECT_WRITE; + } + + switch (mode) { + case CQSPI_STIG_READ: + err = cadence_qspi_apb_command_read( + base, priv->cmd_len, cmd_buf, + data_bytes, din); + + break; + case CQSPI_STIG_WRITE: + err = cadence_qspi_apb_command_write(base, + priv->cmd_len, cmd_buf, + data_bytes, dout); + break; + case CQSPI_INDIRECT_READ: + err = cadence_qspi_apb_indirect_read_setup(plat, + priv->cmd_len, cmd_buf); + if (!err) { + err = cadence_qspi_apb_indirect_read_execute + (plat, data_bytes, din); + } + break; + case CQSPI_INDIRECT_WRITE: + err = cadence_qspi_apb_indirect_write_setup + (plat, priv->cmd_len, cmd_buf); + if (!err) { + err = cadence_qspi_apb_indirect_write_execute + (plat, data_bytes, dout); + } + break; + default: + err = -1; + break; + } + + if (flags & SPI_XFER_END) { + /* clear command buffer */ + memset(cmd_buf, 0, sizeof(priv->cmd_buf)); + priv->cmd_len = 0; + } + } + + return err; +} + +static int cadence_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct cadence_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + int subnode; + u32 data[4]; + int ret; + + /* 2 base addresses are needed, lets get them from the DT */ + ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); + if (ret) { + printf("Error: Can't get base addresses (ret=%d)!\n", ret); + return -ENODEV; + } + + plat->regbase = (void *)data[0]; + plat->ahbbase = (void *)data[2]; + + /* Use 500KHz as a suitable default */ + plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + + /* All other paramters are embedded in the child node */ + subnode = fdt_first_subnode(blob, node); + if (subnode < 0) { + printf("Error: subnode with SPI flash config missing!\n"); + return -ENODEV; + } + + /* Read other parameters from DT */ + plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); + plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); + plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200); + plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); + plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); + plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); + + debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", + __func__, plat->regbase, plat->ahbbase, plat->max_hz, + plat->page_size); + + return 0; +} + +static const struct dm_spi_ops cadence_spi_ops = { + .xfer = cadence_spi_xfer, + .set_speed = cadence_spi_set_speed, + .set_mode = cadence_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id cadence_spi_ids[] = { + { .compatible = "cadence,qspi" }, + { } +}; + +U_BOOT_DRIVER(cadence_spi) = { + .name = "cadence_spi", + .id = UCLASS_SPI, + .of_match = cadence_spi_ids, + .ops = &cadence_spi_ops, + .ofdata_to_platdata = cadence_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata), + .priv_auto_alloc_size = sizeof(struct cadence_spi_priv), + .probe = cadence_spi_probe, +}; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h new file mode 100644 index 0000000000..c9a6142e82 --- /dev/null +++ b/drivers/spi/cadence_qspi.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2012 + * Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CADENCE_QSPI_H__ +#define __CADENCE_QSPI_H__ + +#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) + +#define CQSPI_NO_DECODER_MAX_CS 4 +#define CQSPI_DECODER_MAX_CS 16 +#define CQSPI_READ_CAPTURE_MAX_DELAY 16 + +struct cadence_spi_platdata { + unsigned int max_hz; + void *regbase; + void *ahbbase; + + u32 page_size; + u32 block_size; + u32 tshsl_ns; + u32 tsd2d_ns; + u32 tchsh_ns; + u32 tslch_ns; +}; + +struct cadence_spi_priv { + void *regbase; + void *ahbbase; + size_t cmd_len; + u8 cmd_buf[32]; + size_t data_len; + + int qspi_is_init; + unsigned int qspi_calibrated_hz; + unsigned int qspi_calibrated_cs; +}; + +/* Functions call declaration */ +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat); +void cadence_qspi_apb_controller_enable(void *reg_base_addr); +void cadence_qspi_apb_controller_disable(void *reg_base_addr); + +int cadence_qspi_apb_command_read(void *reg_base_addr, + unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf); +int cadence_qspi_apb_command_write(void *reg_base_addr, + unsigned int cmdlen, const u8 *cmdbuf, + unsigned int txlen, const u8 *txbuf); + +int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, + unsigned int cmdlen, const u8 *cmdbuf); +int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, + unsigned int rxlen, u8 *rxbuf); +int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, + unsigned int cmdlen, const u8 *cmdbuf); +int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, + unsigned int txlen, const u8 *txbuf); + +void cadence_qspi_apb_chipselect(void *reg_base, + unsigned int chip_select, unsigned int decoder_enable); +void cadence_qspi_apb_set_clk_mode(void *reg_base_addr, + unsigned int clk_pol, unsigned int clk_pha); +void cadence_qspi_apb_config_baudrate_div(void *reg_base, + unsigned int ref_clk_hz, unsigned int sclk_hz); +void cadence_qspi_apb_delay(void *reg_base, + unsigned int ref_clk, unsigned int sclk_hz, + unsigned int tshsl_ns, unsigned int tsd2d_ns, + unsigned int tchsh_ns, unsigned int tslch_ns); +void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); +void cadence_qspi_apb_readdata_capture(void *reg_base, + unsigned int bypass, unsigned int delay); + +#endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c new file mode 100644 index 0000000000..00a115f3fb --- /dev/null +++ b/drivers/spi/cadence_qspi_apb.c @@ -0,0 +1,898 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of the Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "cadence_qspi.h" + +#define CQSPI_REG_POLL_US (1) /* 1us */ +#define CQSPI_REG_RETRY (10000) +#define CQSPI_POLL_IDLE_RETRY (3) + +#define CQSPI_FIFO_WIDTH (4) + +/* Controller sram size in word */ +#define CQSPI_REG_SRAM_SIZE_WORD (128) +#define CQSPI_REG_SRAM_RESV_WORDS (2) +#define CQSPI_REG_SRAM_PARTITION_WR (1) +#define CQSPI_REG_SRAM_PARTITION_RD \ + (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS) +#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) + +/* Transfer mode */ +#define CQSPI_INST_TYPE_SINGLE (0) +#define CQSPI_INST_TYPE_DUAL (1) +#define CQSPI_INST_TYPE_QUAD (2) + +#define CQSPI_STIG_DATA_LEN_MAX (8) +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) + +#define CQSPI_DUMMY_CLKS_PER_BYTE (8) +#define CQSPI_DUMMY_BYTES_MAX (4) + + +#define CQSPI_REG_SRAM_FILL_THRESHOLD \ + ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) +/**************************************************************************** + * Controller's configuration and status register (offset from QSPI_BASE) + ****************************************************************************/ +#define CQSPI_REG_CONFIG 0x00 +#define CQSPI_REG_CONFIG_CLK_POL_LSB 1 +#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 +#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0) +#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7) +#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9) +#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18) +#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 +#define CQSPI_REG_CONFIG_BAUD_LSB 19 +#define CQSPI_REG_CONFIG_IDLE_LSB 31 +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF +#define CQSPI_REG_CONFIG_BAUD_MASK 0xF + +#define CQSPI_REG_RD_INSTR 0x04 +#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 +#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 +#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 +#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F + +#define CQSPI_REG_WR_INSTR 0x08 +#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 + +#define CQSPI_REG_DELAY 0x0C +#define CQSPI_REG_DELAY_TSLCH_LSB 0 +#define CQSPI_REG_DELAY_TCHSH_LSB 8 +#define CQSPI_REG_DELAY_TSD2D_LSB 16 +#define CQSPI_REG_DELAY_TSHSL_LSB 24 +#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF +#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF +#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF +#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF + +#define CQSPI_READLCAPTURE 0x10 +#define CQSPI_READLCAPTURE_BYPASS_LSB 0 +#define CQSPI_READLCAPTURE_DELAY_LSB 1 +#define CQSPI_READLCAPTURE_DELAY_MASK 0xF + +#define CQSPI_REG_SIZE 0x14 +#define CQSPI_REG_SIZE_ADDRESS_LSB 0 +#define CQSPI_REG_SIZE_PAGE_LSB 4 +#define CQSPI_REG_SIZE_BLOCK_LSB 16 +#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF +#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF +#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F + +#define CQSPI_REG_SRAMPARTITION 0x18 +#define CQSPI_REG_INDIRECTTRIGGER 0x1C + +#define CQSPI_REG_REMAP 0x24 +#define CQSPI_REG_MODE_BIT 0x28 + +#define CQSPI_REG_SDRAMLEVEL 0x2C +#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 +#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 +#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF +#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF + +#define CQSPI_REG_IRQSTATUS 0x40 +#define CQSPI_REG_IRQMASK 0x44 + +#define CQSPI_REG_INDIRECTRD 0x60 +#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0) +#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2) +#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5) + +#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 +#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 +#define CQSPI_REG_INDIRECTRDBYTES 0x6C + +#define CQSPI_REG_CMDCTRL 0x90 +#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0) +#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1) +#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 +#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 +#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 +#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 +#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 +#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 +#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF + +#define CQSPI_REG_INDIRECTWR 0x70 +#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0) +#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2) +#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5) + +#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 +#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 +#define CQSPI_REG_INDIRECTWRBYTES 0x7C + +#define CQSPI_REG_CMDADDRESS 0x94 +#define CQSPI_REG_CMDREADDATALOWER 0xA0 +#define CQSPI_REG_CMDREADDATAUPPER 0xA4 +#define CQSPI_REG_CMDWRITEDATALOWER 0xA8 +#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC + +#define CQSPI_REG_IS_IDLE(base) \ + ((readl(base + CQSPI_REG_CONFIG) >> \ + CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) + +#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \ + ((((tdelay_ns) - (tsclk_ns)) / (tref_ns))) + +#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ + (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) + +#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ + (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) + +static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf, + unsigned int addr_width) +{ + unsigned int addr; + + addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2]; + + if (addr_width == 4) + addr = (addr << 8) | addr_buf[3]; + + return addr; +} + +static void cadence_qspi_apb_read_fifo_data(void *dest, + const void *src_ahb_addr, unsigned int bytes) +{ + unsigned int temp; + int remaining = bytes; + unsigned int *dest_ptr = (unsigned int *)dest; + unsigned int *src_ptr = (unsigned int *)src_ahb_addr; + + while (remaining > 0) { + if (remaining >= CQSPI_FIFO_WIDTH) { + *dest_ptr = readl(src_ptr); + remaining -= CQSPI_FIFO_WIDTH; + } else { + /* dangling bytes */ + temp = readl(src_ptr); + memcpy(dest_ptr, &temp, remaining); + break; + } + dest_ptr++; + } + + return; +} + +static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr, + const void *src, unsigned int bytes) +{ + unsigned int temp; + int remaining = bytes; + unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr; + unsigned int *src_ptr = (unsigned int *)src; + + while (remaining > 0) { + if (remaining >= CQSPI_FIFO_WIDTH) { + writel(*src_ptr, dest_ptr); + remaining -= sizeof(unsigned int); + } else { + /* dangling bytes */ + memcpy(&temp, src_ptr, remaining); + writel(temp, dest_ptr); + break; + } + src_ptr++; + } + + return; +} + +/* Read from SRAM FIFO with polling SRAM fill level. */ +static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr, + const void *src_addr, unsigned int num_bytes) +{ + unsigned int remaining = num_bytes; + unsigned int retry; + unsigned int sram_level = 0; + unsigned char *dest = (unsigned char *)dest_addr; + + while (remaining > 0) { + retry = CQSPI_REG_RETRY; + while (retry--) { + sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base); + if (sram_level) + break; + udelay(1); + } + + if (!retry) { + printf("QSPI: No receive data after polling for %d times\n", + CQSPI_REG_RETRY); + return -1; + } + + sram_level *= CQSPI_FIFO_WIDTH; + sram_level = sram_level > remaining ? remaining : sram_level; + + /* Read data from FIFO. */ + cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level); + dest += sram_level; + remaining -= sram_level; + udelay(1); + } + return 0; +} + +/* Write to SRAM FIFO with polling SRAM fill level. */ +static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, + const void *src_addr, unsigned int num_bytes) +{ + const void *reg_base = plat->regbase; + void *dest_addr = plat->ahbbase; + unsigned int retry = CQSPI_REG_RETRY; + unsigned int sram_level; + unsigned int wr_bytes; + unsigned char *src = (unsigned char *)src_addr; + int remaining = num_bytes; + unsigned int page_size = plat->page_size; + unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS; + + while (remaining > 0) { + retry = CQSPI_REG_RETRY; + while (retry--) { + sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base); + if (sram_level <= sram_threshold_words) + break; + } + if (!retry) { + printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)", + sram_level, sram_threshold_words); + return -1; + } + /* Write a page or remaining bytes. */ + wr_bytes = (remaining > page_size) ? + page_size : remaining; + + cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes); + src += wr_bytes; + remaining -= wr_bytes; + } + + return 0; +} + +void cadence_qspi_apb_controller_enable(void *reg_base) +{ + unsigned int reg; + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + writel(reg, reg_base + CQSPI_REG_CONFIG); + return; +} + +void cadence_qspi_apb_controller_disable(void *reg_base) +{ + unsigned int reg; + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; + writel(reg, reg_base + CQSPI_REG_CONFIG); + return; +} + +/* Return 1 if idle, otherwise return 0 (busy). */ +static unsigned int cadence_qspi_wait_idle(void *reg_base) +{ + unsigned int start, count = 0; + /* timeout in unit of ms */ + unsigned int timeout = 5000; + + start = get_timer(0); + for ( ; get_timer(start) < timeout ; ) { + if (CQSPI_REG_IS_IDLE(reg_base)) + count++; + else + count = 0; + /* + * Ensure the QSPI controller is in true idle state after + * reading back the same idle status consecutively + */ + if (count >= CQSPI_POLL_IDLE_RETRY) + return 1; + } + + /* Timeout, still in busy mode. */ + printf("QSPI: QSPI is still busy after poll for %d times.\n", + CQSPI_REG_RETRY); + return 0; +} + +void cadence_qspi_apb_readdata_capture(void *reg_base, + unsigned int bypass, unsigned int delay) +{ + unsigned int reg; + cadence_qspi_apb_controller_disable(reg_base); + + reg = readl(reg_base + CQSPI_READLCAPTURE); + + if (bypass) + reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB); + else + reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB); + + reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK + << CQSPI_READLCAPTURE_DELAY_LSB); + + reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK) + << CQSPI_READLCAPTURE_DELAY_LSB); + + writel(reg, reg_base + CQSPI_READLCAPTURE); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_config_baudrate_div(void *reg_base, + unsigned int ref_clk_hz, unsigned int sclk_hz) +{ + unsigned int reg; + unsigned int div; + + cadence_qspi_apb_controller_disable(reg_base); + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); + + div = ref_clk_hz / sclk_hz; + + if (div > 32) + div = 32; + + /* Check if even number. */ + if ((div & 1)) { + div = (div / 2); + } else { + if (ref_clk_hz % sclk_hz) + /* ensure generated SCLK doesn't exceed user + specified sclk_hz */ + div = (div / 2); + else + div = (div / 2) - 1; + } + + debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, + ref_clk_hz, sclk_hz, div); + + div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; + reg |= div; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_set_clk_mode(void *reg_base, + unsigned int clk_pol, unsigned int clk_pha) +{ + unsigned int reg; + + cadence_qspi_apb_controller_disable(reg_base); + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~(1 << + (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); + + reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); + reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); + + writel(reg, reg_base + CQSPI_REG_CONFIG); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_chipselect(void *reg_base, + unsigned int chip_select, unsigned int decoder_enable) +{ + unsigned int reg; + + cadence_qspi_apb_controller_disable(reg_base); + + debug("%s : chipselect %d decode %d\n", __func__, chip_select, + decoder_enable); + + reg = readl(reg_base + CQSPI_REG_CONFIG); + /* docoder */ + if (decoder_enable) { + reg |= CQSPI_REG_CONFIG_DECODE_MASK; + } else { + reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; + /* Convert CS if without decoder. + * CS0 to 4b'1110 + * CS1 to 4b'1101 + * CS2 to 4b'1011 + * CS3 to 4b'0111 + */ + chip_select = 0xF & ~(1 << chip_select); + } + + reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK + << CQSPI_REG_CONFIG_CHIPSELECT_LSB); + reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) + << CQSPI_REG_CONFIG_CHIPSELECT_LSB; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_delay(void *reg_base, + unsigned int ref_clk, unsigned int sclk_hz, + unsigned int tshsl_ns, unsigned int tsd2d_ns, + unsigned int tchsh_ns, unsigned int tslch_ns) +{ + unsigned int ref_clk_ns; + unsigned int sclk_ns; + unsigned int tshsl, tchsh, tslch, tsd2d; + unsigned int reg; + + cadence_qspi_apb_controller_disable(reg_base); + + /* Convert to ns. */ + ref_clk_ns = (1000000000) / ref_clk; + + /* Convert to ns. */ + sclk_ns = (1000000000) / sclk_hz; + + /* Plus 1 to round up 1 clock cycle. */ + tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1; + tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1; + tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1; + tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1; + + reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) + << CQSPI_REG_DELAY_TSHSL_LSB); + reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) + << CQSPI_REG_DELAY_TCHSH_LSB); + reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) + << CQSPI_REG_DELAY_TSLCH_LSB); + reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) + << CQSPI_REG_DELAY_TSD2D_LSB); + writel(reg, reg_base + CQSPI_REG_DELAY); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) +{ + unsigned reg; + + cadence_qspi_apb_controller_disable(plat->regbase); + + /* Configure the device size and address bytes */ + reg = readl(plat->regbase + CQSPI_REG_SIZE); + /* Clear the previous value */ + reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); + reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); + reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB); + reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB); + writel(reg, plat->regbase + CQSPI_REG_SIZE); + + /* Configure the remap address register, no remap */ + writel(0, plat->regbase + CQSPI_REG_REMAP); + + /* Disable all interrupts */ + writel(0, plat->regbase + CQSPI_REG_IRQMASK); + + cadence_qspi_apb_controller_enable(plat->regbase); + return; +} + +static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, + unsigned int reg) +{ + unsigned int retry = CQSPI_REG_RETRY; + + /* Write the CMDCTRL without start execution. */ + writel(reg, reg_base + CQSPI_REG_CMDCTRL); + /* Start execute */ + reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; + writel(reg, reg_base + CQSPI_REG_CMDCTRL); + + while (retry--) { + reg = readl(reg_base + CQSPI_REG_CMDCTRL); + if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0) + break; + udelay(1); + } + + if (!retry) { + printf("QSPI: flash command execution timeout\n"); + return -EIO; + } + + /* Polling QSPI idle status. */ + if (!cadence_qspi_wait_idle(reg_base)) + return -EIO; + + return 0; +} + +/* For command RDID, RDSR. */ +int cadence_qspi_apb_command_read(void *reg_base, + unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, + u8 *rxbuf) +{ + unsigned int reg; + unsigned int read_len; + int status; + + if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) { + printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n", + cmdlen, rxlen); + return -EINVAL; + } + + reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + + /* 0 means 1 byte. */ + reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); + if (status != 0) + return status; + + reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); + + /* Put the read value into rx_buf */ + read_len = (rxlen > 4) ? 4 : rxlen; + memcpy(rxbuf, ®, read_len); + rxbuf += read_len; + + if (rxlen > 4) { + reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); + + read_len = rxlen - read_len; + memcpy(rxbuf, ®, read_len); + } + return 0; +} + +/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ +int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen, + const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf) +{ + unsigned int reg = 0; + unsigned int addr_value; + unsigned int wr_data; + unsigned int wr_len; + + if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) { + printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n", + cmdlen, txlen); + return -EINVAL; + } + + reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + if (cmdlen == 4 || cmdlen == 5) { + /* Command with address */ + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + /* Number of bytes to write. */ + reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + /* Get address */ + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], + cmdlen >= 5 ? 4 : 3); + + writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS); + } + + if (txlen) { + /* writing data = yes */ + reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); + reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) + << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; + + wr_len = txlen > 4 ? 4 : txlen; + memcpy(&wr_data, txbuf, wr_len); + writel(wr_data, reg_base + + CQSPI_REG_CMDWRITEDATALOWER); + + if (txlen > 4) { + txbuf += wr_len; + wr_len = txlen - wr_len; + memcpy(&wr_data, txbuf, wr_len); + writel(wr_data, reg_base + + CQSPI_REG_CMDWRITEDATAUPPER); + } + } + + /* Execute the command */ + return cadence_qspi_apb_exec_flash_cmd(reg_base, reg); +} + +/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ +int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, + unsigned int cmdlen, const u8 *cmdbuf) +{ + unsigned int reg; + unsigned int rd_reg; + unsigned int addr_value; + unsigned int dummy_clk; + unsigned int dummy_bytes; + unsigned int addr_bytes; + + /* + * Identify addr_byte. All NOR flash device drivers are using fast read + * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte. + * With that, the length is in value of 5 or 6. Only FRAM chip from + * ramtron using normal read (which won't need dummy byte). + * Unlikely NOR flash using normal read due to performance issue. + */ + if (cmdlen >= 5) + /* to cater fast read where cmd + addr + dummy */ + addr_bytes = cmdlen - 2; + else + /* for normal read (only ramtron as of now) */ + addr_bytes = cmdlen - 1; + + /* Setup the indirect trigger address */ + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + plat->regbase + CQSPI_REG_INDIRECTTRIGGER); + + /* Configure SRAM partition for read. */ + writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase + + CQSPI_REG_SRAMPARTITION); + + /* Configure the opcode */ + rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; + +#if (CONFIG_SPI_FLASH_QUAD == 1) + /* Instruction and address at DQ0, data at DQ0-3. */ + rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; +#endif + + /* Get address */ + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); + writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); + + /* The remaining lenght is dummy bytes. */ + dummy_bytes = cmdlen - addr_bytes - 1; + if (dummy_bytes) { + if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX) + dummy_bytes = CQSPI_DUMMY_BYTES_MAX; + + rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); +#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) + writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); +#else + writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT); +#endif + + /* Convert to clock cycles. */ + dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE; + /* Need to minus the mode byte (8 clocks). */ + dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE; + + if (dummy_clk) + rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) + << CQSPI_REG_RD_INSTR_DUMMY_LSB; + } + + writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR); + + /* set device size */ + reg = readl(plat->regbase + CQSPI_REG_SIZE); + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; + reg |= (addr_bytes - 1); + writel(reg, plat->regbase + CQSPI_REG_SIZE); + return 0; +} + +int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, + unsigned int rxlen, u8 *rxbuf) +{ + unsigned int reg; + + writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); + + /* Start the indirect read transfer */ + writel(CQSPI_REG_INDIRECTRD_START_MASK, + plat->regbase + CQSPI_REG_INDIRECTRD); + + if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf, + (const void *)plat->ahbbase, rxlen)) + goto failrd; + + /* Check flash indirect controller */ + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD); + if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) { + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD); + printf("QSPI: indirect completion status error with reg 0x%08x\n", + reg); + goto failrd; + } + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTRD_DONE_MASK, + plat->regbase + CQSPI_REG_INDIRECTRD); + return 0; + +failrd: + /* Cancel the indirect read */ + writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, + plat->regbase + CQSPI_REG_INDIRECTRD); + return -1; +} + +/* Opcode + Address (3/4 bytes) */ +int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, + unsigned int cmdlen, const u8 *cmdbuf) +{ + unsigned int reg; + unsigned int addr_bytes = cmdlen > 4 ? 4 : 3; + + if (cmdlen < 4 || cmdbuf == NULL) { + printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n", + cmdlen, (unsigned int)cmdbuf); + return -EINVAL; + } + /* Setup the indirect trigger address */ + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + plat->regbase + CQSPI_REG_INDIRECTTRIGGER); + + writel(CQSPI_REG_SRAM_PARTITION_WR, + plat->regbase + CQSPI_REG_SRAMPARTITION); + + /* Configure the opcode */ + reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; + writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); + + /* Setup write address. */ + reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); + writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); + + reg = readl(plat->regbase + CQSPI_REG_SIZE); + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; + reg |= (addr_bytes - 1); + writel(reg, plat->regbase + CQSPI_REG_SIZE); + return 0; +} + +int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, + unsigned int txlen, const u8 *txbuf) +{ + unsigned int reg = 0; + unsigned int retry; + + /* Configure the indirect read transfer bytes */ + writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); + + /* Start the indirect write transfer */ + writel(CQSPI_REG_INDIRECTWR_START_MASK, + plat->regbase + CQSPI_REG_INDIRECTWR); + + if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen)) + goto failwr; + + /* Wait until last write is completed (FIFO empty) */ + retry = CQSPI_REG_RETRY; + while (retry--) { + reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase); + if (reg == 0) + break; + + udelay(1); + } + + if (reg != 0) { + printf("QSPI: timeout for indirect write\n"); + goto failwr; + } + + /* Check flash indirect controller status */ + retry = CQSPI_REG_RETRY; + while (retry--) { + reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR); + if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK) + break; + udelay(1); + } + + if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) { + printf("QSPI: indirect completion status error with reg 0x%08x\n", + reg); + goto failwr; + } + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTWR_DONE_MASK, + plat->regbase + CQSPI_REG_INDIRECTWR); + return 0; + +failwr: + /* Cancel the indirect write */ + writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, + plat->regbase + CQSPI_REG_INDIRECTWR); + return -1; +} + +void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy) +{ + unsigned int reg; + + /* enter XiP mode immediately and enable direct mode */ + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + reg |= CQSPI_REG_CONFIG_DIRECT_MASK; + reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + /* keep the XiP mode */ + writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT); + + /* Enable mode bit at devrd */ + reg = readl(reg_base + CQSPI_REG_RD_INSTR); + reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); +} diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index e3fb3212aa..0ec5b9d859 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -32,7 +32,27 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!ds) return NULL; - ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE; + ds->slave.bus = bus; + ds->slave.cs = cs; + + switch (bus) { + case SPI0_BUS: + ds->regs = (struct davinci_spi_regs *)SPI0_BASE; + break; +#ifdef CONFIG_SYS_SPI1 + case SPI1_BUS: + ds->regs = (struct davinci_spi_regs *)SPI1_BASE; + break; +#endif +#ifdef CONFIG_SYS_SPI2 + case SPI2_BUS: + ds->regs = (struct davinci_spi_regs *)SPI2_BASE; + break; +#endif + default: /* Invalid bus number */ + return NULL; + } + ds->freq = max_hz; return &ds->slave; @@ -59,7 +79,7 @@ int spi_claim_bus(struct spi_slave *slave) writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); /* CS, CLK, SIMO and SOMI are functional pins */ - writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK | + writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); /* setup format */ @@ -264,7 +284,30 @@ out: int spi_cs_is_valid(unsigned int bus, unsigned int cs) { - return bus == 0 && cs == 0; + int ret = 0; + + switch (bus) { + case SPI0_BUS: + if (cs < SPI0_NUM_CS) + ret = 1; + break; +#ifdef CONFIG_SYS_SPI1 + case SPI1_BUS: + if (cs < SPI1_NUM_CS) + ret = 1; + break; +#endif +#ifdef CONFIG_SYS_SPI2 + case SPI2_BUS: + if (cs < SPI2_NUM_CS) + ret = 1; + break; +#endif + default: + /* Invalid bus number. Do nothing */ + break; + } + return ret; } void spi_cs_activate(struct spi_slave *slave) diff --git a/drivers/spi/davinci_spi.h b/drivers/spi/davinci_spi.h index 33f69b5ca9..d4612d3527 100644 --- a/drivers/spi/davinci_spi.h +++ b/drivers/spi/davinci_spi.h @@ -74,6 +74,39 @@ struct davinci_spi_regs { /* SPIDEF */ #define SPIDEF_CSDEF0_MASK BIT(0) +#define SPI0_BUS 0 +#define SPI0_BASE CONFIG_SYS_SPI_BASE +/* + * Define default SPI0_NUM_CS as 1 for existing platforms that uses this + * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS + * if more than one CS is supported and by defining CONFIG_SYS_SPI0. + */ +#ifndef CONFIG_SYS_SPI0 +#define SPI0_NUM_CS 1 +#else +#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS +#endif + +/* + * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and + * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus + */ +#ifdef CONFIG_SYS_SPI1 +#define SPI1_BUS 1 +#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS +#define SPI1_BASE CONFIG_SYS_SPI1_BASE +#endif + +/* + * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and + * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus + */ +#ifdef CONFIG_SYS_SPI2 +#define SPI2_BUS 2 +#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS +#define SPI2_BASE CONFIG_SYS_SPI2_BASE +#endif + struct davinci_spi_slave { struct spi_slave slave; struct davinci_spi_regs *regs; diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c new file mode 100644 index 0000000000..2624844d52 --- /dev/null +++ b/drivers/spi/designware_spi.c @@ -0,0 +1,425 @@ +/* + * Designware master SPI core controller driver + * + * Copyright (C) 2014 Stefan Roese + * + * Very loosely based on the Linux driver: + * drivers/spi/spi-dw.c, which is: + * Copyright (c) 2009, Intel Corporation. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Register offsets */ +#define DW_SPI_CTRL0 0x00 +#define DW_SPI_CTRL1 0x04 +#define DW_SPI_SSIENR 0x08 +#define DW_SPI_MWCR 0x0c +#define DW_SPI_SER 0x10 +#define DW_SPI_BAUDR 0x14 +#define DW_SPI_TXFLTR 0x18 +#define DW_SPI_RXFLTR 0x1c +#define DW_SPI_TXFLR 0x20 +#define DW_SPI_RXFLR 0x24 +#define DW_SPI_SR 0x28 +#define DW_SPI_IMR 0x2c +#define DW_SPI_ISR 0x30 +#define DW_SPI_RISR 0x34 +#define DW_SPI_TXOICR 0x38 +#define DW_SPI_RXOICR 0x3c +#define DW_SPI_RXUICR 0x40 +#define DW_SPI_MSTICR 0x44 +#define DW_SPI_ICR 0x48 +#define DW_SPI_DMACR 0x4c +#define DW_SPI_DMATDLR 0x50 +#define DW_SPI_DMARDLR 0x54 +#define DW_SPI_IDR 0x58 +#define DW_SPI_VERSION 0x5c +#define DW_SPI_DR 0x60 + +/* Bit fields in CTRLR0 */ +#define SPI_DFS_OFFSET 0 + +#define SPI_FRF_OFFSET 4 +#define SPI_FRF_SPI 0x0 +#define SPI_FRF_SSP 0x1 +#define SPI_FRF_MICROWIRE 0x2 +#define SPI_FRF_RESV 0x3 + +#define SPI_MODE_OFFSET 6 +#define SPI_SCPH_OFFSET 6 +#define SPI_SCOL_OFFSET 7 + +#define SPI_TMOD_OFFSET 8 +#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) +#define SPI_TMOD_TR 0x0 /* xmit & recv */ +#define SPI_TMOD_TO 0x1 /* xmit only */ +#define SPI_TMOD_RO 0x2 /* recv only */ +#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ + +#define SPI_SLVOE_OFFSET 10 +#define SPI_SRL_OFFSET 11 +#define SPI_CFS_OFFSET 12 + +/* Bit fields in SR, 7 bits */ +#define SR_MASK 0x7f /* cover 7 bits */ +#define SR_BUSY (1 << 0) +#define SR_TF_NOT_FULL (1 << 1) +#define SR_TF_EMPT (1 << 2) +#define SR_RF_NOT_EMPT (1 << 3) +#define SR_RF_FULL (1 << 4) +#define SR_TX_ERR (1 << 5) +#define SR_DCOL (1 << 6) + +#define RX_TIMEOUT 1000 /* timeout in ms */ + +struct dw_spi_platdata { + s32 frequency; /* Default clock frequency, -1 for none */ + void __iomem *regs; +}; + +struct dw_spi_priv { + void __iomem *regs; + unsigned int freq; /* Default frequency */ + unsigned int mode; + + int bits_per_word; + u8 cs; /* chip select pin */ + u8 tmode; /* TR/TO/RO/EEPROM */ + u8 type; /* SPI/SSP/MicroWire */ + int len; + + u32 fifo_len; /* depth of the FIFO buffer */ + void *tx; + void *tx_end; + void *rx; + void *rx_end; +}; + +static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset) +{ + return __raw_readl(priv->regs + offset); +} + +static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val) +{ + __raw_writel(val, priv->regs + offset); +} + +static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset) +{ + return __raw_readw(priv->regs + offset); +} + +static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val) +{ + __raw_writew(val, priv->regs + offset); +} + +static int dw_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct dw_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->regs = (struct dw_spi *)fdtdec_get_addr(blob, node, "reg"); + + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs, + plat->frequency); + + return 0; +} + +static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) +{ + dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0)); +} + +/* Restart the controller, disable all interrupts, clean rx fifo */ +static void spi_hw_init(struct dw_spi_priv *priv) +{ + spi_enable_chip(priv, 0); + dw_writel(priv, DW_SPI_IMR, 0xff); + spi_enable_chip(priv, 1); + + /* + * Try to detect the FIFO depth if not set by interface driver, + * the depth could be from 2 to 256 from HW spec + */ + if (!priv->fifo_len) { + u32 fifo; + + for (fifo = 2; fifo <= 256; fifo++) { + dw_writew(priv, DW_SPI_TXFLTR, fifo); + if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) + break; + } + + priv->fifo_len = (fifo == 2) ? 0 : fifo - 1; + dw_writew(priv, DW_SPI_TXFLTR, 0); + } + debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); +} + +static int dw_spi_probe(struct udevice *bus) +{ + struct dw_spi_platdata *plat = dev_get_platdata(bus); + struct dw_spi_priv *priv = dev_get_priv(bus); + + priv->regs = plat->regs; + priv->freq = plat->frequency; + + /* Currently only bits_per_word == 8 supported */ + priv->bits_per_word = 8; + + priv->tmode = 0; /* Tx & Rx */ + + /* Basic HW init */ + spi_hw_init(priv); + + return 0; +} + +/* Return the max entries we can fill into tx fifo */ +static inline u32 tx_max(struct dw_spi_priv *priv) +{ + u32 tx_left, tx_room, rxtx_gap; + + tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3); + tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR); + + /* + * Another concern is about the tx/rx mismatch, we + * thought about using (priv->fifo_len - rxflr - txflr) as + * one maximum value for tx, but it doesn't cover the + * data which is out of tx/rx fifo and inside the + * shift registers. So a control from sw point of + * view is taken. + */ + rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) / + (priv->bits_per_word >> 3); + + return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap)); +} + +/* Return the max entries we should read out of rx fifo */ +static inline u32 rx_max(struct dw_spi_priv *priv) +{ + u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3); + + return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR)); +} + +static void dw_writer(struct dw_spi_priv *priv) +{ + u32 max = tx_max(priv); + u16 txw = 0; + + while (max--) { + /* Set the tx word if the transfer's original "tx" is not null */ + if (priv->tx_end - priv->len) { + if (priv->bits_per_word == 8) + txw = *(u8 *)(priv->tx); + else + txw = *(u16 *)(priv->tx); + } + dw_writew(priv, DW_SPI_DR, txw); + debug("%s: tx=0x%02x\n", __func__, txw); + priv->tx += priv->bits_per_word >> 3; + } +} + +static int dw_reader(struct dw_spi_priv *priv) +{ + unsigned start = get_timer(0); + u32 max; + u16 rxw; + + /* Wait for rx data to be ready */ + while (rx_max(priv) == 0) { + if (get_timer(start) > RX_TIMEOUT) + return -ETIMEDOUT; + } + + max = rx_max(priv); + + while (max--) { + rxw = dw_readw(priv, DW_SPI_DR); + debug("%s: rx=0x%02x\n", __func__, rxw); + + /* + * Care about rx only if the transfer's original "rx" is + * not null + */ + if (priv->rx_end - priv->len) { + if (priv->bits_per_word == 8) + *(u8 *)(priv->rx) = rxw; + else + *(u16 *)(priv->rx) = rxw; + } + priv->rx += priv->bits_per_word >> 3; + } + + return 0; +} + +static int poll_transfer(struct dw_spi_priv *priv) +{ + int ret; + + do { + dw_writer(priv); + ret = dw_reader(priv); + if (ret < 0) + return ret; + } while (priv->rx_end > priv->rx); + + return 0; +} + +static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct dw_spi_priv *priv = dev_get_priv(bus); + const u8 *tx = dout; + u8 *rx = din; + int ret = 0; + u32 cr0 = 0; + u32 cs; + + /* spi core configured to do 8 bit transfers */ + if (bitlen % 8) { + debug("Non byte aligned SPI transfer.\n"); + return -1; + } + + cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) | + (priv->mode << SPI_MODE_OFFSET) | + (priv->tmode << SPI_TMOD_OFFSET); + + if (rx && tx) + priv->tmode = SPI_TMOD_TR; + else if (rx) + priv->tmode = SPI_TMOD_RO; + else + priv->tmode = SPI_TMOD_TO; + + cr0 &= ~SPI_TMOD_MASK; + cr0 |= (priv->tmode << SPI_TMOD_OFFSET); + + priv->len = bitlen >> 3; + debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len); + + priv->tx = (void *)tx; + priv->tx_end = priv->tx + priv->len; + priv->rx = rx; + priv->rx_end = priv->rx + priv->len; + + /* Disable controller before writing control registers */ + spi_enable_chip(priv, 0); + + debug("%s: cr0=%08x\n", __func__, cr0); + /* Reprogram cr0 only if changed */ + if (dw_readw(priv, DW_SPI_CTRL0) != cr0) + dw_writew(priv, DW_SPI_CTRL0, cr0); + + /* + * Configure the desired SS (slave select 0...3) in the controller + * The DW SPI controller will activate and deactivate this CS + * automatically. So no cs_activate() etc is needed in this driver. + */ + cs = spi_chip_select(dev); + dw_writel(priv, DW_SPI_SER, 1 << cs); + + /* Enable controller after writing control registers */ + spi_enable_chip(priv, 1); + + /* Start transfer in a polling loop */ + ret = poll_transfer(priv); + + return ret; +} + +static int dw_spi_set_speed(struct udevice *bus, uint speed) +{ + struct dw_spi_platdata *plat = bus->platdata; + struct dw_spi_priv *priv = dev_get_priv(bus); + u16 clk_div; + + if (speed > plat->frequency) + speed = plat->frequency; + + /* Disable controller before writing control registers */ + spi_enable_chip(priv, 0); + + /* clk_div doesn't support odd number */ + clk_div = cm_get_spi_controller_clk_hz() / speed; + clk_div = (clk_div + 1) & 0xfffe; + dw_writel(priv, DW_SPI_BAUDR, clk_div); + + /* Enable controller after writing control registers */ + spi_enable_chip(priv, 1); + + priv->freq = speed; + debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs, + priv->freq, clk_div); + + return 0; +} + +static int dw_spi_set_mode(struct udevice *bus, uint mode) +{ + struct dw_spi_priv *priv = dev_get_priv(bus); + + /* + * Can't set mode yet. Since this depends on if rx, tx, or + * rx & tx is requested. So we have to defer this to the + * real transfer function. + */ + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops dw_spi_ops = { + .xfer = dw_spi_xfer, + .set_speed = dw_spi_set_speed, + .set_mode = dw_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id dw_spi_ids[] = { + { .compatible = "snps,dw-apb-ssi" }, + { } +}; + +U_BOOT_DRIVER(dw_spi) = { + .name = "dw_spi", + .id = UCLASS_SPI, + .of_match = dw_spi_ids, + .ops = &dw_spi_ops, + .ofdata_to_platdata = dw_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata), + .priv_auto_alloc_size = sizeof(struct dw_spi_priv), + .probe = dw_spi_probe, +}; diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c new file mode 100644 index 0000000000..235557ea3c --- /dev/null +++ b/drivers/spi/ep93xx_spi.c @@ -0,0 +1,274 @@ +/* + * SPI Driver for EP93xx + * + * Copyright (C) 2013 Sergey Kostanabev fairwaves.ru> + * + * Inspired form linux kernel driver and atmel uboot driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include + +#include + + +#define BIT(x) (1<<(x)) +#define SSPBASE SPI_BASE + +#define SSPCR0 0x0000 +#define SSPCR0_MODE_SHIFT 6 +#define SSPCR0_SCR_SHIFT 8 +#define SSPCR0_SPH BIT(7) +#define SSPCR0_SPO BIT(6) +#define SSPCR0_FRF_SPI 0 +#define SSPCR0_DSS_8BIT 7 + +#define SSPCR1 0x0004 +#define SSPCR1_RIE BIT(0) +#define SSPCR1_TIE BIT(1) +#define SSPCR1_RORIE BIT(2) +#define SSPCR1_LBM BIT(3) +#define SSPCR1_SSE BIT(4) +#define SSPCR1_MS BIT(5) +#define SSPCR1_SOD BIT(6) + +#define SSPDR 0x0008 + +#define SSPSR 0x000c +#define SSPSR_TFE BIT(0) +#define SSPSR_TNF BIT(1) +#define SSPSR_RNE BIT(2) +#define SSPSR_RFF BIT(3) +#define SSPSR_BSY BIT(4) +#define SSPCPSR 0x0010 + +#define SSPIIR 0x0014 +#define SSPIIR_RIS BIT(0) +#define SSPIIR_TIS BIT(1) +#define SSPIIR_RORIS BIT(2) +#define SSPICR SSPIIR + +#define SSPCLOCK 14745600 +#define SSP_MAX_RATE (SSPCLOCK / 2) +#define SSP_MIN_RATE (SSPCLOCK / (254 * 256)) + +/* timeout in milliseconds */ +#define SPI_TIMEOUT 5 +/* maximum depth of RX/TX FIFO */ +#define SPI_FIFO_SIZE 8 + +struct ep93xx_spi_slave { + struct spi_slave slave; + + unsigned sspcr0; + unsigned sspcpsr; +}; + +static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ep93xx_spi_slave, slave); +} + +void spi_init() +{ +} + +static inline void ep93xx_spi_write_u8(u16 reg, u8 value) +{ + writel(value, (unsigned int *)(SSPBASE + reg)); +} + +static inline u8 ep93xx_spi_read_u8(u16 reg) +{ + return readl((unsigned int *)(SSPBASE + reg)); +} + +static inline void ep93xx_spi_write_u16(u16 reg, u16 value) +{ + writel(value, (unsigned int *)(SSPBASE + reg)); +} + +static inline u16 ep93xx_spi_read_u16(u16 reg) +{ + return (u16)readl((unsigned int *)(SSPBASE + reg)); +} + +static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode, + struct ep93xx_spi_slave *slave) +{ + unsigned cpsr, scr; + + if (rate > SSP_MAX_RATE) + rate = SSP_MAX_RATE; + + if (rate < SSP_MIN_RATE) + return -1; + + /* Calculate divisors so that we can get speed according the + * following formula: + * rate = spi_clock_rate / (cpsr * (1 + scr)) + * + * cpsr must be even number and starts from 2, scr can be any number + * between 0 and 255. + */ + for (cpsr = 2; cpsr <= 254; cpsr += 2) { + for (scr = 0; scr <= 255; scr++) { + if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) { + /* Set CHPA and CPOL, SPI format and 8bit */ + unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) | + SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT; + if (mode & SPI_CPHA) + sspcr0 |= SSPCR0_SPH; + if (mode & SPI_CPOL) + sspcr0 |= SSPCR0_SPO; + + slave->sspcr0 = sspcr0; + slave->sspcpsr = cpsr; + return 0; + } + } + } + + return -1; +} + +void spi_set_speed(struct spi_slave *slave, unsigned int hz) +{ + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); + + unsigned int mode = 0; + if (as->sspcr0 & SSPCR0_SPH) + mode |= SPI_CPHA; + if (as->sspcr0 & SSPCR0_SPO) + mode |= SPI_CPOL; + + ep93xx_spi_init_hw(hz, mode, as); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ep93xx_spi_slave *as; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs); + if (!as) + return NULL; + + if (ep93xx_spi_init_hw(max_hz, mode, as)) { + free(as); + return NULL; + } + + return &as->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); + + free(as); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); + + /* Enable the SPI hardware */ + ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE); + + + ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr); + ep93xx_spi_write_u16(SSPCR0, as->sspcr0); + + debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n", + slave->cs, as->sspcpsr, as->sspcr0); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Disable the SPI hardware */ + ep93xx_spi_write_u8(SSPCR1, 0); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + unsigned int len_tx; + unsigned int len_rx; + unsigned int len; + u32 status; + const u8 *txp = dout; + u8 *rxp = din; + u8 value; + + debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n", + slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen); + + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + + if (flags & SPI_XFER_BEGIN) { + /* Empty RX FIFO */ + while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE)) + ep93xx_spi_read_u8(SSPDR); + + spi_cs_activate(slave); + } + + for (len_tx = 0, len_rx = 0; len_rx < len; ) { + status = ep93xx_spi_read_u8(SSPSR); + + if ((len_tx < len) && (status & SSPSR_TNF)) { + if (txp) + value = *txp++; + else + value = 0xff; + + ep93xx_spi_write_u8(SSPDR, value); + len_tx++; + } + + if (status & SSPSR_RNE) { + value = ep93xx_spi_read_u8(SSPDR); + + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) { + /* + * Wait until the transfer is completely done before + * we deactivate CS. + */ + do { + status = ep93xx_spi_read_u8(SSPSR); + } while (status & SSPSR_BSY); + + spi_cs_deactivate(slave); + } + + return 0; +} diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index efc8b1e3a5..a46d8c1876 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -6,6 +6,8 @@ */ #include +#include +#include #include #include #include @@ -19,171 +21,35 @@ DECLARE_GLOBAL_DATA_PTR; -/* Information about each SPI controller */ -struct spi_bus { +struct exynos_spi_platdata { enum periph_id periph_id; s32 frequency; /* Default clock frequency, -1 for none */ struct exynos_spi *regs; - int inited; /* 1 if this bus is ready for use */ - int node; + uint deactivate_delay_us; /* Delay to wait after deactivate */ }; -/* A list of spi buses that we know about */ -static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS]; -static unsigned int bus_count; - -struct exynos_spi_slave { - struct spi_slave slave; +struct exynos_spi_priv { struct exynos_spi *regs; unsigned int freq; /* Default frequency */ unsigned int mode; enum periph_id periph_id; /* Peripheral ID for this device */ unsigned int fifo_size; int skip_preamble; + ulong last_transaction_us; /* Time of last transaction end */ }; -static struct spi_bus *spi_get_bus(unsigned dev_index) -{ - if (dev_index < bus_count) - return &spi_bus[dev_index]; - debug("%s: invalid bus %d", __func__, dev_index); - - return NULL; -} - -static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave) -{ - return container_of(slave, struct exynos_spi_slave, slave); -} - -/** - * Setup the driver private data - * - * @param bus ID of the bus that the slave is attached to - * @param cs ID of the chip select connected to the slave - * @param max_hz Required spi frequency - * @param mode Required spi mode (clk polarity, clk phase and - * master or slave) - * @return new device or NULL - */ -struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct exynos_spi_slave *spi_slave; - struct spi_bus *bus; - - if (!spi_cs_is_valid(busnum, cs)) { - debug("%s: Invalid bus/chip select %d, %d\n", __func__, - busnum, cs); - return NULL; - } - - spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs); - if (!spi_slave) { - debug("%s: Could not allocate spi_slave\n", __func__); - return NULL; - } - - bus = &spi_bus[busnum]; - spi_slave->regs = bus->regs; - spi_slave->mode = mode; - spi_slave->periph_id = bus->periph_id; - if (bus->periph_id == PERIPH_ID_SPI1 || - bus->periph_id == PERIPH_ID_SPI2) - spi_slave->fifo_size = 64; - else - spi_slave->fifo_size = 256; - - spi_slave->skip_preamble = 0; - - spi_slave->freq = bus->frequency; - if (max_hz) - spi_slave->freq = min(max_hz, spi_slave->freq); - - return &spi_slave->slave; -} - -/** - * Free spi controller - * - * @param slave Pointer to spi_slave to which controller has to - * communicate with - */ -void spi_free_slave(struct spi_slave *slave) -{ - struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); - - free(spi_slave); -} - /** * Flush spi tx, rx fifos and reset the SPI controller * - * @param slave Pointer to spi_slave to which controller has to - * communicate with + * @param regs Pointer to SPI registers */ -static void spi_flush_fifo(struct spi_slave *slave) +static void spi_flush_fifo(struct exynos_spi *regs) { - struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); - struct exynos_spi *regs = spi_slave->regs; - clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); clrbits_le32(®s->ch_cfg, SPI_CH_RST); setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); } -/** - * Initialize the spi base registers, set the required clock frequency and - * initialize the gpios - * - * @param slave Pointer to spi_slave to which controller has to - * communicate with - * @return zero on success else a negative value - */ -int spi_claim_bus(struct spi_slave *slave) -{ - struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); - struct exynos_spi *regs = spi_slave->regs; - u32 reg = 0; - int ret; - - ret = set_spi_clk(spi_slave->periph_id, - spi_slave->freq); - if (ret < 0) { - debug("%s: Failed to setup spi clock\n", __func__); - return ret; - } - - exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE); - - spi_flush_fifo(slave); - - reg = readl(®s->ch_cfg); - reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L); - - if (spi_slave->mode & SPI_CPHA) - reg |= SPI_CH_CPHA_B; - - if (spi_slave->mode & SPI_CPOL) - reg |= SPI_CH_CPOL_L; - - writel(reg, ®s->ch_cfg); - writel(SPI_FB_DELAY_180, ®s->fb_clk); - - return 0; -} - -/** - * Reset the spi H/W and flush the tx and rx fifos - * - * @param slave Pointer to spi_slave to which controller has to - * communicate with - */ -void spi_release_bus(struct spi_slave *slave) -{ - spi_flush_fifo(slave); -} - static void spi_get_fifo_levels(struct exynos_spi *regs, int *rx_lvl, int *tx_lvl) { @@ -199,19 +65,38 @@ static void spi_get_fifo_levels(struct exynos_spi *regs, * * @param regs SPI peripheral registers * @param count Number of bytes to transfer + * @param step Number of bytes to transfer in each packet (1 or 4) */ -static void spi_request_bytes(struct exynos_spi *regs, int count) +static void spi_request_bytes(struct exynos_spi *regs, int count, int step) { + debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step); + + /* For word address we need to swap bytes */ + if (step == 4) { + setbits_le32(®s->mode_cfg, + SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + count /= 4; + setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN | + SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | + SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP); + } else { + /* Select byte access and clear the swap configuration */ + clrbits_le32(®s->mode_cfg, + SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + writel(0, ®s->swap_cfg); + } + assert(count && count < (1 << 16)); setbits_le32(®s->ch_cfg, SPI_CH_RST); clrbits_le32(®s->ch_cfg, SPI_CH_RST); + writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt); } -static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, +static int spi_rx_tx(struct exynos_spi_priv *priv, int todo, void **dinp, void const **doutp, unsigned long flags) { - struct exynos_spi *regs = spi_slave->regs; + struct exynos_spi *regs = priv->regs; uchar *rxp = *dinp; const uchar *txp = *doutp; int rx_lvl, tx_lvl; @@ -219,17 +104,27 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, int toread; unsigned start = get_timer(0); int stopping; + int step; out_bytes = in_bytes = todo; - stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) && - !(spi_slave->mode & SPI_SLAVE); + stopping = priv->skip_preamble && (flags & SPI_XFER_END) && + !(priv->mode & SPI_SLAVE); + + /* + * Try to transfer words if we can. This helps read performance at + * SPI clock speeds above about 20MHz. + */ + step = 1; + if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) && + !priv->skip_preamble) + step = 4; /* * If there's something to send, do a software reset and set a * transaction size. */ - spi_request_bytes(regs, todo); + spi_request_bytes(regs, todo, step); /* * Bytes are transmitted/received in pairs. Wait to receive all the @@ -242,24 +137,45 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, /* Keep the fifos full/empty. */ spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); - if (tx_lvl < spi_slave->fifo_size && out_bytes) { - temp = txp ? *txp++ : 0xff; + + /* + * Don't completely fill the txfifo, since we don't want our + * rxfifo to overflow, and it may already contain data. + */ + while (tx_lvl < priv->fifo_size/2 && out_bytes) { + if (!txp) + temp = -1; + else if (step == 4) + temp = *(uint32_t *)txp; + else + temp = *txp; writel(temp, ®s->tx_data); - out_bytes--; + out_bytes -= step; + if (txp) + txp += step; + tx_lvl += step; } - if (rx_lvl > 0) { - temp = readl(®s->rx_data); - if (spi_slave->skip_preamble) { - if (temp == SPI_PREAMBLE_END_BYTE) { - spi_slave->skip_preamble = 0; - stopping = 0; + if (rx_lvl >= step) { + while (rx_lvl >= step) { + temp = readl(®s->rx_data); + if (priv->skip_preamble) { + if (temp == SPI_PREAMBLE_END_BYTE) { + priv->skip_preamble = 0; + stopping = 0; + } + } else { + if (rxp || stopping) { + if (step == 4) + *(uint32_t *)rxp = temp; + else + *rxp = temp; + rxp += step; + } + in_bytes -= step; } - } else { - if (rxp || stopping) - *rxp++ = temp; - in_bytes--; + toread -= step; + rx_lvl -= step; } - toread--; } else if (!toread) { /* * We have run out of input data, but haven't read @@ -271,9 +187,9 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, out_bytes = in_bytes; toread = in_bytes; txp = NULL; - spi_request_bytes(regs, toread); + spi_request_bytes(regs, toread, step); } - if (spi_slave->skip_preamble && get_timer(start) > 100) { + if (priv->skip_preamble && get_timer(start) > 100) { printf("SPI timeout: in_bytes=%d, out_bytes=%d, ", in_bytes, out_bytes); return -1; @@ -286,82 +202,30 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, return 0; } -/** - * Transfer and receive data - * - * @param slave Pointer to spi_slave to which controller has to - * communicate with - * @param bitlen No of bits to tranfer or receive - * @param dout Pointer to transfer buffer - * @param din Pointer to receive buffer - * @param flags Flags for transfer begin and end - * @return zero on success else a negative value - */ -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); - int upto, todo; - int bytelen; - int ret = 0; - - /* spi core configured to do 8 bit transfers */ - if (bitlen % 8) { - debug("Non byte aligned SPI transfer.\n"); - return -1; - } - - /* Start the transaction, if necessary. */ - if ((flags & SPI_XFER_BEGIN)) - spi_cs_activate(slave); - - /* Exynos SPI limits each transfer to 65535 bytes */ - bytelen = bitlen / 8; - for (upto = 0; !ret && upto < bytelen; upto += todo) { - todo = min(bytelen - upto, (1 << 16) - 1); - ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags); - if (ret) - break; - } - - /* Stop the transaction, if necessary. */ - if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) { - spi_cs_deactivate(slave); - if (spi_slave->skip_preamble) { - assert(!spi_slave->skip_preamble); - debug("Failed to complete premable transaction\n"); - ret = -1; - } - } - - return ret; -} - -/** - * Validates the bus and chip select numbers - * - * @param bus ID of the bus that the slave is attached to - * @param cs ID of the chip select connected to the slave - * @return one on success else zero - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return spi_get_bus(bus) && cs == 0; -} - /** * Activate the CS by driving it LOW * * @param slave Pointer to spi_slave to which controller has to * communicate with */ -void spi_cs_activate(struct spi_slave *slave) +static void spi_cs_activate(struct udevice *dev) { - struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); + struct udevice *bus = dev->parent; + struct exynos_spi_platdata *pdata = dev_get_platdata(bus); + struct exynos_spi_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } - clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); - debug("Activate CS, bus %d\n", spi_slave->slave.bus); - spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE; + clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT); + debug("Activate CS, bus '%s'\n", bus->name); + priv->skip_preamble = priv->mode & SPI_PREAMBLE; } /** @@ -370,141 +234,196 @@ void spi_cs_activate(struct spi_slave *slave) * @param slave Pointer to spi_slave to which controller has to * communicate with */ -void spi_cs_deactivate(struct spi_slave *slave) +static void spi_cs_deactivate(struct udevice *dev) { - struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); + struct udevice *bus = dev->parent; + struct exynos_spi_platdata *pdata = dev_get_platdata(bus); + struct exynos_spi_priv *priv = dev_get_priv(bus); - setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); - debug("Deactivate CS, bus %d\n", spi_slave->slave.bus); -} + setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT); -static inline struct exynos_spi *get_spi_base(int dev_index) -{ - if (dev_index < 3) - return (struct exynos_spi *)samsung_get_base_spi() + dev_index; - else - return (struct exynos_spi *)samsung_get_base_spi_isp() + - (dev_index - 3); + /* Remember time of this transaction so we can honour the bus delay */ + if (pdata->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); + + debug("Deactivate CS, bus '%s'\n", bus->name); } -/* - * Read the SPI config from the device tree node. - * - * @param blob FDT blob to read from - * @param node Node offset to read from - * @param bus SPI bus structure to fill with information - * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing - */ -#ifdef CONFIG_OF_CONTROL -static int spi_get_config(const void *blob, int node, struct spi_bus *bus) +static int exynos_spi_ofdata_to_platdata(struct udevice *bus) { - bus->node = node; - bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg"); - bus->periph_id = pinmux_decode_periph_id(blob, node); + struct exynos_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg"); + plat->periph_id = pinmux_decode_periph_id(blob, node); - if (bus->periph_id == PERIPH_ID_NONE) { + if (plat->periph_id == PERIPH_ID_NONE) { debug("%s: Invalid peripheral ID %d\n", __func__, - bus->periph_id); + plat->periph_id); return -FDT_ERR_NOTFOUND; } /* Use 500KHz as a suitable default */ - bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->regs, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); return 0; } -/* - * Process a list of nodes, adding them to our list of SPI ports. - * - * @param blob fdt blob - * @param node_list list of nodes to process (any <=0 are ignored) - * @param count number of nodes to process - * @param is_dvc 1 if these are DVC ports, 0 if standard I2C - * @return 0 if ok, -1 on error - */ -static int process_nodes(const void *blob, int node_list[], int count) +static int exynos_spi_probe(struct udevice *bus) { - int i; + struct exynos_spi_platdata *plat = dev_get_platdata(bus); + struct exynos_spi_priv *priv = dev_get_priv(bus); - /* build the i2c_controllers[] for each controller */ - for (i = 0; i < count; i++) { - int node = node_list[i]; - struct spi_bus *bus; + priv->regs = plat->regs; + if (plat->periph_id == PERIPH_ID_SPI1 || + plat->periph_id == PERIPH_ID_SPI2) + priv->fifo_size = 64; + else + priv->fifo_size = 256; - if (node <= 0) - continue; + priv->skip_preamble = 0; + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; - bus = &spi_bus[i]; - if (spi_get_config(blob, node, bus)) { - printf("exynos spi_init: failed to decode bus %d\n", - i); - return -1; - } + return 0; +} - debug("spi: controller bus %d at %p, periph_id %d\n", - i, bus->regs, bus->periph_id); - bus->inited = 1; - bus_count++; - } +static int exynos_spi_claim_bus(struct udevice *bus) +{ + struct exynos_spi_priv *priv = dev_get_priv(bus); + + exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE); + spi_flush_fifo(priv->regs); + + writel(SPI_FB_DELAY_180, &priv->regs->fb_clk); return 0; } -#endif -/** - * Set up a new SPI slave for an fdt node - * - * @param blob Device tree blob - * @param node SPI peripheral node to use - * @return 0 if ok, -1 on error - */ -struct spi_slave *spi_setup_slave_fdt(const void *blob, int node, - unsigned int cs, unsigned int max_hz, unsigned int mode) +static int exynos_spi_release_bus(struct udevice *bus) +{ + struct exynos_spi_priv *priv = dev_get_priv(bus); + + spi_flush_fifo(priv->regs); + + return 0; +} + +static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { - struct spi_bus *bus; - unsigned int i; + struct udevice *bus = dev->parent; + struct exynos_spi_priv *priv = dev_get_priv(bus); + int upto, todo; + int bytelen; + int ret = 0; + + /* spi core configured to do 8 bit transfers */ + if (bitlen % 8) { + debug("Non byte aligned SPI transfer.\n"); + return -1; + } + + /* Start the transaction, if necessary. */ + if ((flags & SPI_XFER_BEGIN)) + spi_cs_activate(dev); - for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) { - if (bus->node == node) - return spi_setup_slave(i, cs, max_hz, mode); + /* + * Exynos SPI limits each transfer to 65535 transfers. To keep + * things simple, allow a maximum of 65532 bytes. We could allow + * more in word mode, but the performance difference is small. + */ + bytelen = bitlen / 8; + for (upto = 0; !ret && upto < bytelen; upto += todo) { + todo = min(bytelen - upto, (1 << 16) - 4); + ret = spi_rx_tx(priv, todo, &din, &dout, flags); + if (ret) + break; + } + + /* Stop the transaction, if necessary. */ + if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) { + spi_cs_deactivate(dev); + if (priv->skip_preamble) { + assert(!priv->skip_preamble); + debug("Failed to complete premable transaction\n"); + ret = -1; + } } - debug("%s: Failed to find bus node %d\n", __func__, node); - return NULL; + return ret; } -/* Sadly there is no error return from this function */ -void spi_init(void) +static int exynos_spi_set_speed(struct udevice *bus, uint speed) { - int count; + struct exynos_spi_platdata *plat = bus->platdata; + struct exynos_spi_priv *priv = dev_get_priv(bus); + int ret; -#ifdef CONFIG_OF_CONTROL - int node_list[EXYNOS5_SPI_NUM_CONTROLLERS]; - const void *blob = gd->fdt_blob; + if (speed > plat->frequency) + speed = plat->frequency; + ret = set_spi_clk(priv->periph_id, speed); + if (ret) + return ret; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} - count = fdtdec_find_aliases_for_id(blob, "spi", - COMPAT_SAMSUNG_EXYNOS_SPI, node_list, - EXYNOS5_SPI_NUM_CONTROLLERS); - if (process_nodes(blob, node_list, count)) - return; +static int exynos_spi_set_mode(struct udevice *bus, uint mode) +{ + struct exynos_spi_priv *priv = dev_get_priv(bus); + uint32_t reg; -#else - struct spi_bus *bus; + reg = readl(&priv->regs->ch_cfg); + reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L); - for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) { - bus = &spi_bus[count]; - bus->regs = get_spi_base(count); - bus->periph_id = PERIPH_ID_SPI0 + count; + if (mode & SPI_CPHA) + reg |= SPI_CH_CPHA_B; - /* Although Exynos5 supports upto 50Mhz speed, - * we are setting it to 10Mhz for safe side - */ - bus->frequency = 10000000; - bus->inited = 1; - bus->node = 0; - bus_count = EXYNOS5_SPI_NUM_CONTROLLERS; - } -#endif + if (mode & SPI_CPOL) + reg |= SPI_CH_CPOL_L; + + writel(reg, &priv->regs->ch_cfg); + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; } + +static const struct dm_spi_ops exynos_spi_ops = { + .claim_bus = exynos_spi_claim_bus, + .release_bus = exynos_spi_release_bus, + .xfer = exynos_spi_xfer, + .set_speed = exynos_spi_set_speed, + .set_mode = exynos_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id exynos_spi_ids[] = { + { .compatible = "samsung,exynos-spi" }, + { } +}; + +U_BOOT_DRIVER(exynos_spi) = { + .name = "exynos_spi", + .id = UCLASS_SPI, + .of_match = exynos_spi_ids, + .ops = &exynos_spi_ops, + .ofdata_to_platdata = exynos_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata), + .priv_auto_alloc_size = sizeof(struct exynos_spi_priv), + .probe = exynos_spi_probe, +}; diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c deleted file mode 100644 index 58f139a54e..0000000000 --- a/drivers/spi/fdt_spi.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Common fdt based SPI driver front end - * - * Copyright (c) 2013 NVIDIA Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct fdt_spi_driver { - int compat; - int max_ctrls; - int (*init)(int *node_list, int count); - int (*claim_bus)(struct spi_slave *slave); - int (*release_bus)(struct spi_slave *slave); - int (*cs_is_valid)(unsigned int bus, unsigned int cs); - struct spi_slave *(*setup_slave)(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); - void (*free_slave)(struct spi_slave *slave); - void (*cs_activate)(struct spi_slave *slave); - void (*cs_deactivate)(struct spi_slave *slave); - int (*xfer)(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); -}; - -static struct fdt_spi_driver fdt_spi_drivers[] = { -#ifdef CONFIG_TEGRA20_SFLASH - { - .compat = COMPAT_NVIDIA_TEGRA20_SFLASH, - .max_ctrls = 1, - .init = tegra20_spi_init, - .claim_bus = tegra20_spi_claim_bus, - .cs_is_valid = tegra20_spi_cs_is_valid, - .setup_slave = tegra20_spi_setup_slave, - .free_slave = tegra20_spi_free_slave, - .cs_activate = tegra20_spi_cs_activate, - .cs_deactivate = tegra20_spi_cs_deactivate, - .xfer = tegra20_spi_xfer, - }, -#endif -#ifdef CONFIG_TEGRA20_SLINK - { - .compat = COMPAT_NVIDIA_TEGRA20_SLINK, - .max_ctrls = CONFIG_TEGRA_SLINK_CTRLS, - .init = tegra30_spi_init, - .claim_bus = tegra30_spi_claim_bus, - .cs_is_valid = tegra30_spi_cs_is_valid, - .setup_slave = tegra30_spi_setup_slave, - .free_slave = tegra30_spi_free_slave, - .cs_activate = tegra30_spi_cs_activate, - .cs_deactivate = tegra30_spi_cs_deactivate, - .xfer = tegra30_spi_xfer, - }, -#endif -#ifdef CONFIG_TEGRA114_SPI - { - .compat = COMPAT_NVIDIA_TEGRA114_SPI, - .max_ctrls = CONFIG_TEGRA114_SPI_CTRLS, - .init = tegra114_spi_init, - .claim_bus = tegra114_spi_claim_bus, - .cs_is_valid = tegra114_spi_cs_is_valid, - .setup_slave = tegra114_spi_setup_slave, - .free_slave = tegra114_spi_free_slave, - .cs_activate = tegra114_spi_cs_activate, - .cs_deactivate = tegra114_spi_cs_deactivate, - .xfer = tegra114_spi_xfer, - }, -#endif -}; - -static struct fdt_spi_driver *driver; - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - if (!driver) - return 0; - else if (!driver->cs_is_valid) - return 1; - else - return driver->cs_is_valid(bus, cs); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - if (!driver || !driver->setup_slave) - return NULL; - - return driver->setup_slave(bus, cs, max_hz, mode); -} - -void spi_free_slave(struct spi_slave *slave) -{ - if (driver && driver->free_slave) - return driver->free_slave(slave); -} - -static int spi_init_driver(struct fdt_spi_driver *driver) -{ - int count; - int node_list[driver->max_ctrls]; - - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi", - driver->compat, - node_list, - driver->max_ctrls); - return driver->init(node_list, count); -} - -void spi_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(fdt_spi_drivers); i++) { - driver = &fdt_spi_drivers[i]; - if (!spi_init_driver(driver)) - break; - } - if (i == ARRAY_SIZE(fdt_spi_drivers)) - driver = NULL; -} - -int spi_claim_bus(struct spi_slave *slave) -{ - if (!driver) - return 1; - if (!driver->claim_bus) - return 0; - - return driver->claim_bus(slave); -} - -void spi_release_bus(struct spi_slave *slave) -{ - if (driver && driver->release_bus) - driver->release_bus(slave); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - if (driver && driver->cs_activate) - driver->cs_activate(slave); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - if (driver && driver->cs_deactivate) - driver->cs_deactivate(slave); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags) -{ - if (!driver || !driver->xfer) - return -1; - - return driver->xfer(slave, bitlen, data_out, data_in, flags); -} diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index fc0a58be29..375dc07f5f 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -15,8 +15,10 @@ struct fsl_spi_slave { struct spi_slave slave; + ccsr_espi_t *espi; unsigned int div16; unsigned int pm; + int tx_timeout; unsigned int mode; size_t cmd_len; u8 cmd_buf[16]; @@ -25,11 +27,17 @@ struct fsl_spi_slave { }; #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) +#define US_PER_SECOND 1000000UL #define ESPI_MAX_CS_NUM 4 +#define ESPI_FIFO_WIDTH_BIT 32 #define ESPI_EV_RNE (1 << 9) #define ESPI_EV_TNF (1 << 8) +#define ESPI_EV_DON (1 << 14) +#define ESPI_EV_TXE (1 << 15) +#define ESPI_EV_RFCNT_SHIFT 24 +#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT) #define ESPI_MODE_EN (1 << 31) /* Enable interface */ #define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ @@ -61,6 +69,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, struct fsl_spi_slave *fsl; sys_info_t sysinfo; unsigned long spibrg = 0; + unsigned long spi_freq = 0; unsigned char pm = 0; if (!spi_cs_is_valid(bus, cs)) @@ -70,12 +79,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!fsl) return NULL; + fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); fsl->mode = mode; fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; /* Set eSPI BRG clock source */ get_sys_info(&sysinfo); - spibrg = sysinfo.freqSystemBus / 2; + spibrg = sysinfo.freq_systembus / 2; fsl->div16 = 0; if ((spibrg / max_hz) > 32) { fsl->div16 = ESPI_CSMODE_DIV16; @@ -91,6 +101,15 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, pm--; fsl->pm = pm; + if (fsl->div16) + spi_freq = spibrg / ((pm + 1) * 2 * 16); + else + spi_freq = spibrg / ((pm + 1) * 2); + + /* set tx_timeout to 10 times of one espi FIFO entry go out */ + fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT + * 10), spi_freq); + return &fsl->slave; } @@ -108,7 +127,7 @@ void spi_init(void) int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + ccsr_espi_t *espi = fsl->espi; unsigned char pm = fsl->pm; unsigned int cs = slave->cs; unsigned int mode = fsl->mode; @@ -161,24 +180,86 @@ void spi_release_bus(struct spi_slave *slave) } +static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned int tmpdout, event; + int tmp_tx_timeout; + + if (dout) + tmpdout = *(u32 *)dout; + else + tmpdout = 0; + + out_be32(&espi->tx, tmpdout); + out_be32(&espi->event, ESPI_EV_TNF); + debug("***spi_xfer:...%08x written\n", tmpdout); + + tmp_tx_timeout = fsl->tx_timeout; + /* Wait for eSPI transmit to go out */ + while (tmp_tx_timeout--) { + event = in_be32(&espi->event); + if (event & ESPI_EV_DON || event & ESPI_EV_TXE) { + out_be32(&espi->event, ESPI_EV_TXE); + break; + } + udelay(1); + } + + if (tmp_tx_timeout < 0) + debug("***spi_xfer:...Tx timeout! event = %08x\n", event); +} + +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned int tmpdin, rx_times; + unsigned char *buf, *p_cursor; + + if (bytes <= 0) + return 0; + + rx_times = DIV_ROUND_UP(bytes, 4); + buf = (unsigned char *)malloc(4 * rx_times); + if (!buf) { + debug("SF: Failed to malloc memory.\n"); + return -1; + } + p_cursor = buf; + while (rx_times--) { + tmpdin = in_be32(&espi->rx); + debug("***spi_xfer:...%08x readed\n", tmpdin); + *(u32 *)p_cursor = tmpdin; + p_cursor += 4; + } + + if (din) + memcpy(din, buf, bytes); + + free(buf); + out_be32(&espi->event, ESPI_EV_RNE); + + return bytes; +} + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - unsigned int tmpdout, tmpdin, event; + ccsr_espi_t *espi = fsl->espi; + unsigned int event, rx_bytes; const void *dout = NULL; void *din = NULL; int len = 0; int num_blks, num_chunks, max_tran_len, tran_len; int num_bytes; - unsigned char *ch; unsigned char *buffer = NULL; size_t buf_len; u8 *cmd_buf = fsl->cmd_buf; size_t cmd_len = fsl->cmd_len; size_t data_len = bitlen / 8; size_t rx_offset = 0; + int rf_cnt; max_tran_len = fsl->max_transfer_length; switch (flags) { @@ -192,7 +273,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, spi_cs_deactivate(slave); return 0; } - buf_len = 2 * cmd_len + min(data_len, max_tran_len); + buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); len = cmd_len + data_len; rx_offset = cmd_len; buffer = (unsigned char *)malloc(buf_len); @@ -217,19 +298,16 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, break; } - debug("spi_xfer: slave %u:%u dout %08X(%p) din %08X(%p) len %u\n", - slave->bus, slave->cs, *(uint *) dout, - dout, *(uint *) din, din, len); + debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n", + *(uint *)data_out, data_out, *(uint *)data_in, data_in, len); - num_chunks = data_len / max_tran_len + - (data_len % max_tran_len ? 1 : 0); + num_chunks = DIV_ROUND_UP(data_len, max_tran_len); while (num_chunks--) { if (data_in) din = buffer + rx_offset; dout = buffer; - tran_len = min(data_len , max_tran_len); - num_blks = (tran_len + cmd_len) / 4 + - ((tran_len + cmd_len) % 4 ? 1 : 0); + tran_len = min(data_len, (size_t)max_tran_len); + num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; spi_cs_activate(slave); @@ -237,41 +315,34 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, /* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); /* handle data in 32-bit chunks */ - while (num_blks--) { - + while (num_blks) { event = in_be32(&espi->event); if (event & ESPI_EV_TNF) { - tmpdout = *(u32 *)dout; - + fsl_espi_tx(fsl, dout); /* Set up the next iteration */ if (len > 4) { len -= 4; dout += 4; } - - out_be32(&espi->tx, tmpdout); - out_be32(&espi->event, ESPI_EV_TNF); - debug("***spi_xfer:...%08x written\n", tmpdout); } - /* Wait for eSPI transmit to get out */ - udelay(80); - event = in_be32(&espi->event); if (event & ESPI_EV_RNE) { - tmpdin = in_be32(&espi->rx); - if (num_blks == 0 && num_bytes != 0) { - ch = (unsigned char *)&tmpdin; - while (num_bytes--) - *(unsigned char *)din++ = *ch++; - } else { - *(u32 *) din = tmpdin; - din += 4; + rf_cnt = ((event & ESPI_EV_RFCNT_MASK) + >> ESPI_EV_RFCNT_SHIFT); + if (rf_cnt >= 4) + rx_bytes = 4; + else if (num_blks == 1 && rf_cnt == num_bytes) + rx_bytes = num_bytes; + else + continue; + if (fsl_espi_rx(fsl, din, rx_bytes) + == rx_bytes) { + num_blks--; + if (din) + din = (unsigned char *)din + + rx_bytes; } - - out_be32(&espi->event, in_be32(&espi->event) - | ESPI_EV_RNE); - debug("***spi_xfer:...%08x readed\n", tmpdin); } } if (data_in) { @@ -297,7 +368,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + ccsr_espi_t *espi = fsl->espi; unsigned int com = 0; size_t data_len = fsl->data_len; @@ -309,7 +380,8 @@ void spi_cs_activate(struct spi_slave *slave) void spi_cs_deactivate(struct spi_slave *slave) { - ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = fsl->espi; /* clear the RXCNT and TXCNT */ out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c new file mode 100644 index 0000000000..b00a4328cb --- /dev/null +++ b/drivers/spi/fsl_qspi.c @@ -0,0 +1,784 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * Freescale Quad Serial Peripheral Interface (QSPI) driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "fsl_qspi.h" + +#define RX_BUFFER_SIZE 0x80 +#ifdef CONFIG_SOC_MX6SX +#define TX_BUFFER_SIZE 0x200 +#else +#define TX_BUFFER_SIZE 0x40 +#endif + +#define OFFSET_BITS_MASK 0x00ffffff + +#define FLASH_STATUS_WEL 0x02 + +/* SEQID */ +#define SEQID_WREN 1 +#define SEQID_FAST_READ 2 +#define SEQID_RDSR 3 +#define SEQID_SE 4 +#define SEQID_CHIP_ERASE 5 +#define SEQID_PP 6 +#define SEQID_RDID 7 +#define SEQID_BE_4K 8 +#ifdef CONFIG_SPI_FLASH_BAR +#define SEQID_BRRD 9 +#define SEQID_BRWR 10 +#define SEQID_RDEAR 11 +#define SEQID_WREAR 12 +#endif + +/* QSPI CMD */ +#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ +#define QSPI_CMD_RDSR 0x05 /* Read status register */ +#define QSPI_CMD_WREN 0x06 /* Write enable */ +#define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define QSPI_CMD_BE_4K 0x20 /* 4K erase */ +#define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ + +/* Used for Micron, winbond and Macronix flashes */ +#define QSPI_CMD_WREAR 0xc5 /* EAR register write */ +#define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */ + +/* Used for Spansion flashes only. */ +#define QSPI_CMD_BRRD 0x16 /* Bank register read */ +#define QSPI_CMD_BRWR 0x17 /* Bank register write */ + +/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ +#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ + +#ifdef CONFIG_SYS_FSL_QSPI_LE +#define qspi_read32 in_le32 +#define qspi_write32 out_le32 +#elif defined(CONFIG_SYS_FSL_QSPI_BE) +#define qspi_read32 in_be32 +#define qspi_write32 out_be32 +#endif + +static unsigned long spi_bases[] = { + QSPI0_BASE_ADDR, +#ifdef CONFIG_SOC_MX6SX + QSPI1_BASE_ADDR, +#endif +}; + +static unsigned long amba_bases[] = { + QSPI0_AMBA_BASE, +#ifdef CONFIG_SOC_MX6SX + QSPI1_AMBA_BASE, +#endif +}; + +struct fsl_qspi { + struct spi_slave slave; + unsigned long reg_base; + unsigned long amba_base; + u32 sf_addr; + u8 cur_seqid; +}; + +/* QSPI support swapping the flash read/write data + * in hardware for LS102xA, but not for VF610 */ +static inline u32 qspi_endian_xchg(u32 data) +{ +#ifdef CONFIG_SOC_VF610 + return swab32(data); +#else + return data; +#endif +} + +static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) +{ + return container_of(slave, struct fsl_qspi, slave); +} + +static void qspi_set_lut(struct fsl_qspi *qspi) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 lut_base; + + /* Unlock the LUT */ + qspi_write32(®s->lutkey, LUT_KEY_VALUE); + qspi_write32(®s->lckcr, QSPI_LCKCR_UNLOCK); + + /* Write Enable */ + lut_base = SEQID_WREN * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Fast Read */ + lut_base = SEQID_FAST_READ * 4; +#ifdef CONFIG_SPI_FLASH_BAR + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#else + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(®s->lut[lut_base], + OPRND0(QSPI_CMD_FAST_READ_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | + OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | + INSTR1(LUT_ADDR)); +#endif + qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) | + INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | + INSTR1(LUT_READ)); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Read Status */ + lut_base = SEQID_RDSR * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Erase a sector */ + lut_base = SEQID_SE * 4; +#ifdef CONFIG_SPI_FLASH_BAR + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#else + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#endif + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Erase the whole chip */ + lut_base = SEQID_CHIP_ERASE * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Page Program */ + lut_base = SEQID_PP * 4; +#ifdef CONFIG_SPI_FLASH_BAR + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#else + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#endif +#ifdef CONFIG_SOC_MX6SX + /* + * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. + * So, Use IDATSZ in IPCR to determine the size and here set 0. + */ + qspi_write32(®s->lut[lut_base + 1], OPRND0(0) | + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); +#else + qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); +#endif + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* READ ID */ + lut_base = SEQID_RDID * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* SUB SECTOR 4K ERASE */ + lut_base = SEQID_BE_4K * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + +#ifdef CONFIG_SPI_FLASH_BAR + /* + * BRRD BRWR RDEAR WREAR are all supported, because it is hard to + * dynamically check whether to set BRRD BRWR or RDEAR WREAR during + * initialization. + */ + lut_base = SEQID_BRRD * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BRRD) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + + lut_base = SEQID_BRWR * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BRWR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); + + lut_base = SEQID_RDEAR * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + + lut_base = SEQID_WREAR * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREAR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); +#endif + /* Lock the LUT */ + qspi_write32(®s->lutkey, LUT_KEY_VALUE); + qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK); +} + +#if defined(CONFIG_SYS_FSL_QSPI_AHB) +/* + * If we have changed the content of the flash by writing or erasing, + * we need to invalidate the AHB buffer. If we do not do so, we may read out + * the wrong data. The spec tells us reset the AHB domain and Serial Flash + * domain at the same time. + */ +static inline void qspi_ahb_invalid(struct fsl_qspi *q) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base; + u32 reg; + + reg = qspi_read32(®s->mcr); + reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK; + qspi_write32(®s->mcr, reg); + + /* + * The minimum delay : 1 AHB + 2 SFCK clocks. + * Delay 1 us is enough. + */ + udelay(1); + + reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK); + qspi_write32(®s->mcr, reg); +} + +/* Read out the data from the AHB buffer. */ +static inline void qspi_ahb_read(struct fsl_qspi *q, u8 *rxbuf, int len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base; + u32 mcr_reg; + + mcr_reg = qspi_read32(®s->mcr); + + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + + /* Read out the data directly from the AHB buffer. */ + memcpy(rxbuf, (u8 *)(q->amba_base + q->sf_addr), len); + + qspi_write32(®s->mcr, mcr_reg); +} + +static void qspi_enable_ddr_mode(struct fsl_qspi_regs *regs) +{ + u32 reg, reg2; + + reg = qspi_read32(®s->mcr); + /* Disable the module */ + qspi_write32(®s->mcr, reg | QSPI_MCR_MDIS_MASK); + + /* Set the Sampling Register for DDR */ + reg2 = qspi_read32(®s->smpr); + reg2 &= ~QSPI_SMPR_DDRSMP_MASK; + reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT); + qspi_write32(®s->smpr, reg2); + + /* Enable the module again (enable the DDR too) */ + reg |= QSPI_MCR_DDR_EN_MASK; + /* Enable bit 29 for imx6sx */ + reg |= (1 << 29); + + qspi_write32(®s->mcr, reg); +} + +/* + * There are two different ways to read out the data from the flash: + * the "IP Command Read" and the "AHB Command Read". + * + * The IC guy suggests we use the "AHB Command Read" which is faster + * then the "IP Command Read". (What's more is that there is a bug in + * the "IP Command Read" in the Vybrid.) + * + * After we set up the registers for the "AHB Command Read", we can use + * the memcpy to read the data directly. A "missed" access to the buffer + * causes the controller to clear the buffer, and use the sequence pointed + * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash. + */ +static void qspi_init_ahb_read(struct fsl_qspi_regs *regs) +{ + /* AHB configuration for access buffer 0/1/2 .*/ + qspi_write32(®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); + qspi_write32(®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); + qspi_write32(®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); + qspi_write32(®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | + (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); + + /* We only use the buffer3 */ + qspi_write32(®s->buf0ind, 0); + qspi_write32(®s->buf1ind, 0); + qspi_write32(®s->buf2ind, 0); + + /* + * Set the default lut sequence for AHB Read. + * Parallel mode is disabled. + */ + qspi_write32(®s->bfgencr, + SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT); + + /*Enable DDR Mode*/ + qspi_enable_ddr_mode(regs); +} +#endif + +void spi_init() +{ + /* do nothing */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_qspi *qspi; + struct fsl_qspi_regs *regs; + u32 smpr_val; + u32 total_size; + + if (bus >= ARRAY_SIZE(spi_bases)) + return NULL; + + if (cs >= FSL_QSPI_FLASH_NUM) + return NULL; + + qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); + if (!qspi) + return NULL; + + qspi->reg_base = spi_bases[bus]; + /* + * According cs, use different amba_base to choose the + * corresponding flash devices. + * + * If not, only one flash device is used even if passing + * different cs using `sf probe` + */ + qspi->amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; + + qspi->slave.max_write_size = TX_BUFFER_SIZE; + + regs = (struct fsl_qspi_regs *)qspi->reg_base; + qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + + smpr_val = qspi_read32(®s->smpr); + qspi_write32(®s->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK | + QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK)); + qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK); + + total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; + /* + * Any read access to non-implemented addresses will provide + * undefined results. + * + * In case single die flash devices, TOP_ADDR_MEMA2 and + * TOP_ADDR_MEMB2 should be initialized/programmed to + * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, + * setting the size of these devices to 0. This would ensure + * that the complete memory map is assigned to only one flash device. + */ + qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]); + qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]); + qspi_write32(®s->sfb1ad, total_size | amba_bases[bus]); + qspi_write32(®s->sfb2ad, total_size | amba_bases[bus]); + + qspi_set_lut(qspi); + + smpr_val = qspi_read32(®s->smpr); + smpr_val &= ~QSPI_SMPR_DDRSMP_MASK; + qspi_write32(®s->smpr, smpr_val); + qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK); + +#ifdef CONFIG_SYS_FSL_QSPI_AHB + qspi_init_ahb_read(regs); +#endif + return &qspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct fsl_qspi *qspi = to_qspi_spi(slave); + + free(qspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +#ifdef CONFIG_SPI_FLASH_BAR +/* Bank register read/write, EAR register read/write */ +static void qspi_op_rdbank(struct fsl_qspi *qspi, u8 *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 reg, mcr_reg, data, seqid; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(®s->sfar, qspi->amba_base); + + if (qspi->cur_seqid == QSPI_CMD_BRRD) + seqid = SEQID_BRRD; + else + seqid = SEQID_RDEAR; + + qspi_write32(®s->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | len); + + /* Wait previous command complete */ + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + while (1) { + reg = qspi_read32(®s->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(®s->rbdr[0]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, len); + qspi_write32(®s->mcr, qspi_read32(®s->mcr) | + QSPI_MCR_CLR_RXF_MASK); + break; + } + } + + qspi_write32(®s->mcr, mcr_reg); +} +#endif + +static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, rbsr_reg, data; + int i, size; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(®s->sfar, qspi->amba_base); + + qspi_write32(®s->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + i = 0; + size = len; + while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + rbsr_reg = qspi_read32(®s->rbsr); + if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(®s->rbdr[i]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + rxbuf++; + size -= 4; + i++; + } + } + + qspi_write32(®s->mcr, mcr_reg); +} + +#ifndef CONFIG_SYS_FSL_QSPI_AHB +/* If not use AHB read, read data from ip interface */ +static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, data; + int i, size; + u32 to_or_from; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + to_or_from = qspi->sf_addr + qspi->amba_base; + + while (len > 0) { + qspi_write32(®s->sfar, to_or_from); + + size = (len > RX_BUFFER_SIZE) ? + RX_BUFFER_SIZE : len; + + qspi_write32(®s->ipcr, + (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + to_or_from += size; + len -= size; + + i = 0; + while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + data = qspi_read32(®s->rbdr[i]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + rxbuf++; + size -= 4; + i++; + } + qspi_write32(®s->mcr, qspi_read32(®s->mcr) | + QSPI_MCR_CLR_RXF_MASK); + } + + qspi_write32(®s->mcr, mcr_reg); +} +#endif + +static void qspi_op_write(struct fsl_qspi *qspi, u8 *txbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, data, reg, status_reg, seqid; + int i, size, tx_size; + u32 to_or_from = 0; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + status_reg = 0; + while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { + qspi_write32(®s->ipcr, + (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(®s->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + reg = qspi_read32(®s->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + status_reg = qspi_read32(®s->rbdr[0]); + status_reg = qspi_endian_xchg(status_reg); + } + qspi_write32(®s->mcr, + qspi_read32(®s->mcr) | QSPI_MCR_CLR_RXF_MASK); + } + + /* Default is page programming */ + seqid = SEQID_PP; +#ifdef CONFIG_SPI_FLASH_BAR + if (qspi->cur_seqid == QSPI_CMD_BRWR) + seqid = SEQID_BRWR; + else if (qspi->cur_seqid == QSPI_CMD_WREAR) + seqid = SEQID_WREAR; +#endif + + to_or_from = qspi->sf_addr + qspi->amba_base; + + qspi_write32(®s->sfar, to_or_from); + + tx_size = (len > TX_BUFFER_SIZE) ? + TX_BUFFER_SIZE : len; + + size = tx_size / 4; + for (i = 0; i < size; i++) { + memcpy(&data, txbuf, 4); + data = qspi_endian_xchg(data); + qspi_write32(®s->tbdr, data); + txbuf += 4; + } + + size = tx_size % 4; + if (size) { + data = 0; + memcpy(&data, txbuf, size); + data = qspi_endian_xchg(data); + qspi_write32(®s->tbdr, data); + } + + qspi_write32(®s->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(®s->mcr, mcr_reg); +} + +static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, reg, data; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(®s->sfar, qspi->amba_base); + + qspi_write32(®s->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + while (1) { + reg = qspi_read32(®s->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(®s->rbdr[0]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + qspi_write32(®s->mcr, qspi_read32(®s->mcr) | + QSPI_MCR_CLR_RXF_MASK); + break; + } + } + + qspi_write32(®s->mcr, mcr_reg); +} + +static void qspi_op_erase(struct fsl_qspi *qspi) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg; + u32 to_or_from = 0; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + to_or_from = qspi->sf_addr + qspi->amba_base; + qspi_write32(®s->sfar, to_or_from); + + qspi_write32(®s->ipcr, + (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + if (qspi->cur_seqid == QSPI_CMD_SE) { + qspi_write32(®s->ipcr, + (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); + } else if (qspi->cur_seqid == QSPI_CMD_BE_4K) { + qspi_write32(®s->ipcr, + (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0); + } + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(®s->mcr, mcr_reg); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct fsl_qspi *qspi = to_qspi_spi(slave); + u32 bytes = DIV_ROUND_UP(bitlen, 8); + static u32 wr_sfaddr; + u32 txbuf; + + if (dout) { + if (flags & SPI_XFER_BEGIN) { + qspi->cur_seqid = *(u8 *)dout; + memcpy(&txbuf, dout, 4); + } + + if (flags == SPI_XFER_END) { + qspi->sf_addr = wr_sfaddr; + qspi_op_write(qspi, (u8 *)dout, bytes); + return 0; + } + + if (qspi->cur_seqid == QSPI_CMD_FAST_READ) { + qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if ((qspi->cur_seqid == QSPI_CMD_SE) || + (qspi->cur_seqid == QSPI_CMD_BE_4K)) { + qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + qspi_op_erase(qspi); + } else if (qspi->cur_seqid == QSPI_CMD_PP) + wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; +#ifdef CONFIG_SPI_FLASH_BAR + else if ((qspi->cur_seqid == QSPI_CMD_BRWR) || + (qspi->cur_seqid == QSPI_CMD_WREAR)) { + wr_sfaddr = 0; + } +#endif + } + + if (din) { + if (qspi->cur_seqid == QSPI_CMD_FAST_READ) { +#ifdef CONFIG_SYS_FSL_QSPI_AHB + qspi_ahb_read(qspi, din, bytes); +#else + qspi_op_read(qspi, din, bytes); +#endif + } + else if (qspi->cur_seqid == QSPI_CMD_RDID) + qspi_op_rdid(qspi, din, bytes); + else if (qspi->cur_seqid == QSPI_CMD_RDSR) + qspi_op_rdsr(qspi, din); +#ifdef CONFIG_SPI_FLASH_BAR + else if ((qspi->cur_seqid == QSPI_CMD_BRRD) || + (qspi->cur_seqid == QSPI_CMD_RDEAR)) { + qspi->sf_addr = 0; + qspi_op_rdbank(qspi, din, bytes); + } +#endif + } + +#ifdef CONFIG_SYS_FSL_QSPI_AHB + if ((qspi->cur_seqid == QSPI_CMD_SE) || + (qspi->cur_seqid == QSPI_CMD_PP) || + (qspi->cur_seqid == QSPI_CMD_BE_4K) || + (qspi->cur_seqid == QSPI_CMD_WREAR) || + (qspi->cur_seqid == QSPI_CMD_BRWR)) + qspi_ahb_invalid(qspi); +#endif + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Nothing to do */ +} diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h new file mode 100644 index 0000000000..6cb361018b --- /dev/null +++ b/drivers/spi/fsl_qspi.h @@ -0,0 +1,142 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * Register definitions for Freescale QSPI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_QSPI_H_ +#define _FSL_QSPI_H_ + +struct fsl_qspi_regs { + u32 mcr; + u32 rsvd0[1]; + u32 ipcr; + u32 flshcr; + u32 buf0cr; + u32 buf1cr; + u32 buf2cr; + u32 buf3cr; + u32 bfgencr; + u32 soccr; + u32 rsvd1[2]; + u32 buf0ind; + u32 buf1ind; + u32 buf2ind; + u32 rsvd2[49]; + u32 sfar; + u32 rsvd3[1]; + u32 smpr; + u32 rbsr; + u32 rbct; + u32 rsvd4[15]; + u32 tbsr; + u32 tbdr; + u32 rsvd5[1]; + u32 sr; + u32 fr; + u32 rser; + u32 spndst; + u32 sptrclr; + u32 rsvd6[4]; + u32 sfa1ad; + u32 sfa2ad; + u32 sfb1ad; + u32 sfb2ad; + u32 rsvd7[28]; + u32 rbdr[32]; + u32 rsvd8[32]; + u32 lutkey; + u32 lckcr; + u32 rsvd9[2]; + u32 lut[64]; +}; + +#define QSPI_IPCR_SEQID_SHIFT 24 +#define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT) + +#define QSPI_MCR_END_CFD_SHIFT 2 +#define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT) +#ifdef CONFIG_SYS_FSL_QSPI_AHB +/* AHB needs 64bit operation */ +#define QSPI_MCR_END_CFD_LE (3 << QSPI_MCR_END_CFD_SHIFT) +#else +#define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT) +#endif +#define QSPI_MCR_DDR_EN_SHIFT 7 +#define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT) +#define QSPI_MCR_CLR_RXF_SHIFT 10 +#define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT) +#define QSPI_MCR_CLR_TXF_SHIFT 11 +#define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT) +#define QSPI_MCR_MDIS_SHIFT 14 +#define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT) +#define QSPI_MCR_RESERVED_SHIFT 16 +#define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT) +#define QSPI_MCR_SWRSTHD_SHIFT 1 +#define QSPI_MCR_SWRSTHD_MASK (1 << QSPI_MCR_SWRSTHD_SHIFT) +#define QSPI_MCR_SWRSTSD_SHIFT 0 +#define QSPI_MCR_SWRSTSD_MASK (1 << QSPI_MCR_SWRSTSD_SHIFT) + +#define QSPI_SMPR_HSENA_SHIFT 0 +#define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT) +#define QSPI_SMPR_FSPHS_SHIFT 5 +#define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT) +#define QSPI_SMPR_FSDLY_SHIFT 6 +#define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT) +#define QSPI_SMPR_DDRSMP_SHIFT 16 +#define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT) + +#define QSPI_BUFXCR_INVALID_MSTRID 0xe +#define QSPI_BUF3CR_ALLMST_SHIFT 31 +#define QSPI_BUF3CR_ALLMST_MASK (1 << QSPI_BUF3CR_ALLMST_SHIFT) +#define QSPI_BUF3CR_ADATSZ_SHIFT 8 +#define QSPI_BUF3CR_ADATSZ_MASK (0xFF << QSPI_BUF3CR_ADATSZ_SHIFT) + +#define QSPI_BFGENCR_SEQID_SHIFT 12 +#define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT) +#define QSPI_BFGENCR_PAR_EN_SHIFT 16 +#define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT) + +#define QSPI_RBSR_RDBFL_SHIFT 8 +#define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT) + +#define QSPI_RBCT_RXBRD_SHIFT 8 +#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT) + +#define QSPI_SR_BUSY_SHIFT 0 +#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT) + +#define QSPI_LCKCR_LOCK 0x1 +#define QSPI_LCKCR_UNLOCK 0x2 + +#define LUT_KEY_VALUE 0x5af05af0 + +#define OPRND0_SHIFT 0 +#define OPRND0(x) ((x) << OPRND0_SHIFT) +#define PAD0_SHIFT 8 +#define PAD0(x) ((x) << PAD0_SHIFT) +#define INSTR0_SHIFT 10 +#define INSTR0(x) ((x) << INSTR0_SHIFT) +#define OPRND1_SHIFT 16 +#define OPRND1(x) ((x) << OPRND1_SHIFT) +#define PAD1_SHIFT 24 +#define PAD1(x) ((x) << PAD1_SHIFT) +#define INSTR1_SHIFT 26 +#define INSTR1(x) ((x) << INSTR1_SHIFT) + +#define LUT_CMD 1 +#define LUT_ADDR 2 +#define LUT_DUMMY 3 +#define LUT_READ 7 +#define LUT_WRITE 8 + +#define LUT_PAD1 0 +#define LUT_PAD2 1 +#define LUT_PAD4 2 + +#define ADDR24BIT 0x18 +#define ADDR32BIT 0x20 + +#endif /* _FSL_QSPI_H_ */ diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c new file mode 100644 index 0000000000..267e4d83bd --- /dev/null +++ b/drivers/spi/ftssp010_spi.c @@ -0,0 +1,496 @@ +/* + * (C) Copyright 2013 + * Faraday Technology Corporation. + * Kuo-Jung Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifndef CONFIG_FTSSP010_BASE_LIST +#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE } +#endif + +#ifndef CONFIG_FTSSP010_GPIO_BASE +#define CONFIG_FTSSP010_GPIO_BASE 0 +#endif + +#ifndef CONFIG_FTSSP010_GPIO_LIST +#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE } +#endif + +#ifndef CONFIG_FTSSP010_CLOCK +#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP"); +#endif + +#ifndef CONFIG_FTSSP010_TIMEOUT +#define CONFIG_FTSSP010_TIMEOUT 100 +#endif + +/* FTSSP010 chip registers */ +struct ftssp010_regs { + uint32_t cr[3];/* control register */ + uint32_t sr; /* status register */ + uint32_t icr; /* interrupt control register */ + uint32_t isr; /* interrupt status register */ + uint32_t dr; /* data register */ + uint32_t rsvd[17]; + uint32_t revr; /* revision register */ + uint32_t fear; /* feature register */ +}; + +/* Control Register 0 */ +#define CR0_FFMT_MASK (7 << 12) +#define CR0_FFMT_SSP (0 << 12) +#define CR0_FFMT_SPI (1 << 12) +#define CR0_FFMT_MICROWIRE (2 << 12) +#define CR0_FFMT_I2S (3 << 12) +#define CR0_FFMT_AC97 (4 << 12) +#define CR0_FLASH (1 << 11) +#define CR0_FSDIST(x) (((x) & 0x03) << 8) +#define CR0_LOOP (1 << 7) /* loopback mode */ +#define CR0_LSB (1 << 6) /* LSB */ +#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */ +#define CR0_FSJUSTIFY (1 << 4) +#define CR0_OPM_SLAVE (0 << 2) +#define CR0_OPM_MASTER (3 << 2) +#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */ +#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */ +#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */ +#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */ +#define CR0_SCLKPO (1 << 1) /* clock polarity */ +#define CR0_SCLKPH (1 << 0) /* clock phase */ + +/* Control Register 1 */ +#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */ +#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */ +#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */ + +/* Control Register 2 */ +#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */ +#define CR2_FS (1 << 9) /* CS/FS signal level */ +#define CR2_TXEN (1 << 8) /* tx enable */ +#define CR2_RXEN (1 << 7) /* rx enable */ +#define CR2_RESET (1 << 6) /* chip reset */ +#define CR2_TXFC (1 << 3) /* tx fifo Clear */ +#define CR2_RXFC (1 << 2) /* rx fifo Clear */ +#define CR2_TXDOE (1 << 1) /* tx data output enable */ +#define CR2_EN (1 << 0) /* chip enable */ + +/* Status Register */ +#define SR_RFF (1 << 0) /* rx fifo full */ +#define SR_TFNF (1 << 1) /* tx fifo not full */ +#define SR_BUSY (1 << 2) /* chip busy */ +#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */ +#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */ + +/* Feature Register */ +#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */ +#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */ +#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */ +#define FEAR_AC97 (1 << 24) +#define FEAR_I2S (1 << 25) +#define FEAR_SPI_MWR (1 << 26) +#define FEAR_SSP (1 << 27) +#define FEAR_SPDIF (1 << 28) + +/* FTGPIO010 chip registers */ +struct ftgpio010_regs { + uint32_t out; /* 0x00: Data Output */ + uint32_t in; /* 0x04: Data Input */ + uint32_t dir; /* 0x08: Direction */ + uint32_t bypass; /* 0x0c: Bypass */ + uint32_t set; /* 0x10: Data Set */ + uint32_t clr; /* 0x14: Data Clear */ + uint32_t pull_up; /* 0x18: Pull-Up Enabled */ + uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */ +}; + +struct ftssp010_gpio { + struct ftgpio010_regs *regs; + uint32_t pin; +}; + +struct ftssp010_spi { + struct spi_slave slave; + struct ftssp010_gpio gpio; + struct ftssp010_regs *regs; + uint32_t fifo; + uint32_t mode; + uint32_t div; + uint32_t clk; + uint32_t speed; + uint32_t revision; +}; + +static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ftssp010_spi, slave); +} + +static int get_spi_chip(int bus, struct ftssp010_spi *chip) +{ + uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST; + + if (bus >= ARRAY_SIZE(base) || !base[bus]) + return -1; + + chip->regs = (struct ftssp010_regs *)base[bus]; + + chip->revision = readl(&chip->regs->revr); + + fear = readl(&chip->regs->fear); + chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear)); + + return 0; +} + +static int get_spi_gpio(int bus, struct ftssp010_gpio *chip) +{ + uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST; + + if (bus >= ARRAY_SIZE(base) || !base[bus]) + return -1; + + chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000); + chip->pin = base[bus] & 0x1f; + + /* make it an output pin */ + setbits_le32(&chip->regs->dir, 1 << chip->pin); + + return 0; +} + +static int ftssp010_wait(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + ulong t; + + /* wait until device idle */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (!(readl(®s->sr) & SR_BUSY)) + return 0; + } + + puts("ftspi010: busy timeout\n"); + + return -1; +} + +static int ftssp010_wait_tx(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + ulong t; + + /* wait until tx fifo not full */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (readl(®s->sr) & SR_TFNF) + return 0; + } + + puts("ftssp010: tx timeout\n"); + + return -1; +} + +static int ftssp010_wait_rx(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + ulong t; + + /* wait until rx fifo not empty */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (SR_RFVE(readl(®s->sr))) + return 0; + } + + puts("ftssp010: rx timeout\n"); + + return -1; +} + +static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip, + const void *tx_buf, void *rx_buf, int len, uint flags) +{ + struct ftssp010_regs *regs = chip->regs; + const uint8_t *txb = tx_buf; + uint8_t *rxb = rx_buf; + + while (len > 0) { + int i, depth = min(chip->fifo >> 2, len); + uint32_t xmsk = 0; + + if (tx_buf) { + for (i = 0; i < depth; ++i) { + ftssp010_wait_tx(chip); + writel(*txb++, ®s->dr); + } + xmsk |= CR2_TXEN | CR2_TXDOE; + if ((readl(®s->cr[2]) & xmsk) != xmsk) + setbits_le32(®s->cr[2], xmsk); + } + if (rx_buf) { + xmsk |= CR2_RXEN; + if ((readl(®s->cr[2]) & xmsk) != xmsk) + setbits_le32(®s->cr[2], xmsk); + for (i = 0; i < depth; ++i) { + ftssp010_wait_rx(chip); + *rxb++ = (uint8_t)readl(®s->dr); + } + } + + len -= depth; + } + + return 0; +} + +static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip, + const void *tx_buf, void *rx_buf, int len, uint flags) +{ + struct ftssp010_regs *regs = chip->regs; + const uint8_t *txb = tx_buf; + uint8_t *rxb = rx_buf; + + while (len > 0) { + int i, depth = min(chip->fifo >> 2, len); + uint32_t tmp; + + for (i = 0; i < depth; ++i) { + ftssp010_wait_tx(chip); + writel(txb ? (*txb++) : 0, ®s->dr); + } + for (i = 0; i < depth; ++i) { + ftssp010_wait_rx(chip); + tmp = readl(®s->dr); + if (rxb) + *rxb++ = (uint8_t)tmp; + } + + len -= depth; + } + + return 0; +} + +static void ftssp010_cs_set(struct ftssp010_spi *chip, int high) +{ + struct ftssp010_regs *regs = chip->regs; + struct ftssp010_gpio *gpio = &chip->gpio; + uint32_t mask; + + /* cs pull high/low */ + if (chip->revision >= 0x11900) { + mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0); + writel(mask, ®s->cr[2]); + } else if (gpio->regs) { + mask = 1 << gpio->pin; + if (high) + writel(mask, &gpio->regs->set); + else + writel(mask, &gpio->regs->clr); + } + + /* extra delay for signal propagation */ + udelay_masked(1); +} + +/* + * Determine if a SPI chipselect is valid. + * This function is provided by the board if the low-level SPI driver + * needs it to determine if a given chipselect is actually valid. + * + * Returns: 1 if bus:cs identifies a valid chip on this board, 0 + * otherwise. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + struct ftssp010_spi chip; + + if (get_spi_chip(bus, &chip)) + return 0; + + if (!cs) + return 1; + else if ((cs < 4) && (chip.revision >= 0x11900)) + return 1; + + return 0; +} + +/* + * Activate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should activate the chip select + * to the device identified by "slave". + */ +void spi_cs_activate(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + /* cs pull */ + if (chip->mode & SPI_CS_HIGH) + ftssp010_cs_set(chip, 1); + else + ftssp010_cs_set(chip, 0); + + /* chip enable + fifo clear */ + setbits_le32(®s->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC); +} + +/* + * Deactivate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should deactivate the chip + * select to the device identified by "slave". + */ +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + + /* wait until chip idle */ + ftssp010_wait(chip); + + /* cs pull */ + if (chip->mode & SPI_CS_HIGH) + ftssp010_cs_set(chip, 0); + else + ftssp010_cs_set(chip, 1); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +{ + struct ftssp010_spi *chip; + + if (mode & SPI_3WIRE) { + puts("ftssp010: can't do 3-wire\n"); + return NULL; + } + + if (mode & SPI_SLAVE) { + puts("ftssp010: can't do slave mode\n"); + return NULL; + } + + if (mode & SPI_PREAMBLE) { + puts("ftssp010: can't skip preamble bytes\n"); + return NULL; + } + + if (!spi_cs_is_valid(bus, cs)) { + puts("ftssp010: invalid (bus, cs)\n"); + return NULL; + } + + chip = spi_alloc_slave(struct ftssp010_spi, bus, cs); + if (!chip) + return NULL; + + if (get_spi_chip(bus, chip)) + goto free_out; + + if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) { + puts("ftssp010: Before revision 1.19.0, its clock & cs are\n" + "controlled by tx engine which is not synced with rx engine,\n" + "so the clock & cs might be shutdown before rx engine\n" + "finishs its jobs.\n" + "If possible, please add a dedicated gpio for it.\n"); + } + + chip->mode = mode; + chip->clk = CONFIG_FTSSP010_CLOCK; + chip->div = 2; + if (max_hz) { + while (chip->div < 0xffff) { + if ((chip->clk / (2 * chip->div)) <= max_hz) + break; + chip->div += 1; + } + } + chip->speed = chip->clk / (2 * chip->div); + + return &chip->slave; + +free_out: + free(chip); + return NULL; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + writel(CR1_SDL(8) | CR1_DIV(chip->div), ®s->cr[1]); + + if (chip->revision >= 0x11900) { + writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH, + ®s->cr[0]); + writel(CR2_TXFC | CR2_RXFC, + ®s->cr[2]); + } else { + writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO, + ®s->cr[0]); + writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE, + ®s->cr[2]); + } + + if (chip->mode & SPI_LOOP) + setbits_le32(®s->cr[0], CR0_LOOP); + + if (chip->mode & SPI_CPOL) + setbits_le32(®s->cr[0], CR0_SCLKPO); + + if (chip->mode & SPI_CPHA) + setbits_le32(®s->cr[0], CR0_SCLKPH); + + spi_cs_deactivate(slave); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + writel(0, ®s->cr[2]); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + uint32_t len = bitlen >> 3; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + if (chip->revision >= 0x11900) + ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags); + else + ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags); + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index f5c6f3e7d2..fdff158637 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -141,9 +141,25 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ich->slave.max_write_size = ctlr.databytes; ich->speed = max_hz; + /* + * ICH 7 SPI controller only supports array read command + * and byte program command for SST flash + */ + if (ctlr.ich_version == 7) { + ich->slave.op_mode_rx = SPI_OPM_RX_AS; + ich->slave.op_mode_tx = SPI_OPM_TX_BP; + } + return &ich->slave; } +struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, + int spi_node) +{ + /* We only support a single SPI at present */ + return spi_setup_slave(0, 0, 20000000, 0); +} + void spi_free_slave(struct spi_slave *slave) { struct ich_spi_slave *ich = to_ich_spi(slave); @@ -158,7 +174,8 @@ void spi_free_slave(struct spi_slave *slave) */ static int get_ich_version(uint16_t device_id) { - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || + device_id == PCI_DEVICE_ID_INTEL_ITC_LPC) return 7; if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && @@ -483,8 +500,6 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, struct spi_trans *trans = &ich->trans; unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); int using_cmd = 0; - /* Align read transactions to 64-byte boundaries */ - char buff[ctlr.databytes]; /* Ee don't support writing partial bytes. */ if (bitlen % 8) { @@ -632,14 +647,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, */ while (trans->bytesout || trans->bytesin) { uint32_t data_length; - uint32_t aligned_offset; - uint32_t diff; - - aligned_offset = trans->offset & ~(ctlr.databytes - 1); - diff = trans->offset - aligned_offset; /* SPI addresses are 24 bit only */ - ich_writel(aligned_offset & 0x00FFFFFF, ctlr.addr); + ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); if (trans->bytesout) data_length = min(trans->bytesout, ctlr.databytes); @@ -673,13 +683,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } if (trans->bytesin) { - if (diff) { - data_length -= diff; - read_reg(ctlr.data, buff, ctlr.databytes); - memcpy(trans->in, buff + diff, data_length); - } else { - read_reg(ctlr.data, trans->in, data_length); - } + read_reg(ctlr.data, trans->in, data_length); spi_use_in(trans, data_length); if (with_address) trans->offset += data_length; diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 942a208c2c..e7b0982fb6 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -12,23 +12,30 @@ #include #include #include -#include -#include +#include +#ifdef CONFIG_KIRKWOOD #include +#endif +#include -static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE; +static struct kwspi_registers *spireg = + (struct kwspi_registers *)MVEBU_SPI_BASE; -u32 cs_spi_mpp_back[2]; +#ifdef CONFIG_KIRKWOOD +static u32 cs_spi_mpp_back[2]; +#endif struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct spi_slave *slave; u32 data; +#ifdef CONFIG_KIRKWOOD static const u32 kwspi_mpp_config[2][2] = { { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ { MPP7_SPI_SCn, 0 } /* if cs != 0 */ }; +#endif if (!spi_cs_is_valid(bus, cs)) return NULL; @@ -37,7 +44,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!slave) return NULL; - writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl); + writel(KWSPI_SMEMRDY, &spireg->ctrl); /* calculate spi clock prescaller using max_hz */ data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10; @@ -46,20 +53,24 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, /* program spi clock prescaller using max_hz */ writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg); - debug("data = 0x%08x \n", data); + debug("data = 0x%08x\n", data); writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause); writel(KWSPI_IRQMASK, &spireg->irq_mask); +#ifdef CONFIG_KIRKWOOD /* program mpp registers to select SPI_CSn */ kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); +#endif return slave; } void spi_free_slave(struct spi_slave *slave) { +#ifdef CONFIG_KIRKWOOD kirkwood_mpp_conf(cs_spi_mpp_back, NULL); +#endif free(slave); } @@ -100,7 +111,6 @@ int spi_claim_bus(struct spi_slave *slave) /* set new spi mpp and save current mpp config */ kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup); - #endif return board_spi_claim_bus(slave); @@ -127,7 +137,7 @@ void spi_release_bus(struct spi_slave *slave) */ int spi_cs_is_valid(unsigned int bus, unsigned int cs) { - return (bus == 0 && (cs == 0 || cs == 1)); + return bus == 0 && (cs == 0 || cs == 1); } #endif @@ -137,12 +147,12 @@ void spi_init(void) void spi_cs_activate(struct spi_slave *slave) { - writel(readl(&spireg->ctrl) | KWSPI_IRQUNMASK, &spireg->ctrl); + setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT); } void spi_cs_deactivate(struct spi_slave *slave) { - writel(readl(&spireg->ctrl) & KWSPI_IRQMASK, &spireg->ctrl); + clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT); } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, @@ -161,8 +171,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, * handle data in 8-bit chunks * TBD: 2byte xfer mode to be enabled */ - writel(((readl(&spireg->cfg) & ~KWSPI_XFERLEN_MASK) | - KWSPI_XFERLEN_1BYTE), &spireg->cfg); + clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE); while (bitlen > 4) { debug("loopstart bitlen %d\n", bitlen); @@ -170,9 +179,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Shift data so it's msb-justified */ if (dout) - tmpdout = *(u32 *) dout & 0x0ff; + tmpdout = *(u32 *)dout & 0xff; - writel(~KWSPI_SMEMRDIRQ, &spireg->irq_cause); + clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ); writel(tmpdout, &spireg->dout); /* Write the data out */ debug("*** spi_xfer: ... %08x written, bitlen %d\n", tmpdout, bitlen); @@ -186,12 +195,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) { isread = 1; tmpdin = readl(&spireg->din); - debug - ("spi_xfer: din %p..%08x read\n", - din, tmpdin); + debug("spi_xfer: din %p..%08x read\n", + din, tmpdin); if (din) { - *((u8 *) din) = (u8) tmpdin; + *((u8 *)din) = (u8)tmpdin; din += 1; } if (dout) diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index bbfc259e47..0d59c36151 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -77,7 +77,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, { volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi; unsigned int tmpdout, tmpdin, event; - int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0); + int numBlks = DIV_ROUND_UP(bitlen, 32); int tm, isRead = 0; unsigned char charSize = 32; @@ -110,10 +110,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, if (bitlen <= 16) { if (bitlen <= 4) spi->mode = (spi->mode & 0xff0fffff) | - (3 << 20); + (3 << 20); else spi->mode = (spi->mode & 0xff0fffff) | - ((bitlen - 1) << 20); + ((bitlen - 1) << 20); } else { spi->mode = (spi->mode & 0xff0fffff); /* Set up the next iteration if sending > 32 bits */ diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index fd72a65d3a..a70dd9dbdd 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -12,8 +12,9 @@ #include #include #include +#include -#ifdef CONFIG_MX27 +#ifdef CONFIG_SOC_MX27 /* i.MX27 has a completely wrong register layout and register definitions in the * datasheet, the correct one is in the Freescale's Linux driver */ @@ -25,11 +26,20 @@ static unsigned long spi_bases[] = { MXC_SPI_BASE_ADDRESSES }; +__weak int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return -1; +} + #define OUT MXC_GPIO_DIRECTION_OUT #define reg_read readl #define reg_write(a, v) writel(v, a) +#if !defined(CONFIG_SYS_SPI_MXC_WAIT) +#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ +#endif + struct mxc_spi_slave { struct spi_slave slave; unsigned long base; @@ -39,6 +49,8 @@ struct mxc_spi_slave { #endif int gpio; int ss_pol; + unsigned int max_hz; + unsigned int mode; }; static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) @@ -73,12 +85,13 @@ u32 get_cspi_div(u32 div) } #ifdef MXC_CSPI -static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) { unsigned int ctrl_reg; u32 clk_src; u32 div; + unsigned int max_hz = mxcs->max_hz; + unsigned int mode = mxcs->mode; clk_src = mxc_get_clock(MXC_CSPI_CLK); @@ -92,7 +105,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | MXC_CSPICTRL_DATARATE(div) | MXC_CSPICTRL_EN | -#ifdef CONFIG_MX35 +#ifdef CONFIG_SOC_MX35 MXC_CSPICTRL_SSCTL | #endif MXC_CSPICTRL_MODE; @@ -110,18 +123,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, #endif #ifdef MXC_ECSPI -static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) { u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); s32 reg_ctrl, reg_config; - u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0; + u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; + u32 pre_div = 0, post_div = 0; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; - - if (max_hz == 0) { - printf("Error: desired clock is 0\n"); - return -1; - } + unsigned int max_hz = mxcs->max_hz; + unsigned int mode = mxcs->mode; /* * Reset SPI and set all CSs to master mode, if toggling @@ -158,14 +168,13 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | MXC_CSPICTRL_POSTDIV(post_div); - /* We need to disable SPI before changing registers */ - reg_ctrl &= ~MXC_CSPICTRL_EN; - if (mode & SPI_CS_HIGH) ss_pol = 1; - if (mode & SPI_CPOL) + if (mode & SPI_CPOL) { sclkpol = 1; + sclkctl = 1; + } if (mode & SPI_CPHA) sclkpha = 1; @@ -180,6 +189,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, (ss_pol << (cs + MXC_CSPICON_SSPOL)); reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | (sclkpol << (cs + MXC_CSPICON_POL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | + (sclkctl << (cs + MXC_CSPICON_CTL)); reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | (sclkpha << (cs + MXC_CSPICON_PHA)); @@ -207,6 +218,8 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, int nbytes = DIV_ROUND_UP(bitlen, 8); u32 data, cnt, i; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; + u32 ts; + int status; debug("%s: bitlen %d dout 0x%x din 0x%x\n", __func__, bitlen, (u32)dout, (u32)din); @@ -255,8 +268,8 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, } else { data = *(u32 *)dout; data = cpu_to_be32(data); + dout += 4; } - dout += 4; } debug("Sending SPI 0x%x\n", data); reg_write(®s->txdata, data); @@ -267,9 +280,16 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); + ts = get_timer(0); + status = reg_read(®s->stat); /* Wait until the TC (Transfer completed) bit is set */ - while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0) - ; + while ((status & MXC_CSPICTRL_TC) == 0) { + if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) { + printf("spi_xchg_single: Timeout!\n"); + return -1; + } + status = reg_read(®s->stat); + } /* Transfer completed, clear any pending request */ reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); @@ -295,7 +315,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, tmp = reg_read(®s->rxdata); data = cpu_to_be32(tmp); debug("SPI Rx: 0x%x 0x%x\n", tmp, data); - cnt = min(nbytes, sizeof(data)); + cnt = min_t(u32, nbytes, sizeof(data)); if (din) { memcpy(din, &data, cnt); din += cnt; @@ -353,31 +373,30 @@ void spi_init(void) { } -static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) +/* + * Some SPI devices require active chip-select over multiple + * transactions, we achieve this using a GPIO. Still, the SPI + * controller has to be configured to use one of its own chipselects. + * To use this feature you have to implement board_spi_cs_gpio() to assign + * a gpio value for each cs (-1 if cs doesn't need to use gpio). + * You must use some unused on this SPI controller cs between 0 and 3. + */ +static int setup_cs_gpio(struct mxc_spi_slave *mxcs, + unsigned int bus, unsigned int cs) { int ret; - /* - * Some SPI devices require active chip-select over multiple - * transactions, we achieve this using a GPIO. Still, the SPI - * controller has to be configured to use one of its own chipselects. - * To use this feature you have to call spi_setup_slave() with - * cs = internal_cs | (gpio << 8), and you have to use some unused - * on this SPI controller cs between 0 and 3. - */ - if (cs > 3) { - mxcs->gpio = cs >> 8; - cs &= 3; - ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); - if (ret) { - printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); - return -EINVAL; - } - } else { - mxcs->gpio = -1; + mxcs->gpio = board_spi_cs_gpio(bus, cs); + if (mxcs->gpio == -1) + return 0; + + ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); + if (ret) { + printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); + return -EINVAL; } - return cs; + return 0; } struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, @@ -389,6 +408,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (bus >= ARRAY_SIZE(spi_bases)) return NULL; + if (max_hz == 0) { + printf("Error: desired clock is 0\n"); + return NULL; + } + mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); if (!mxcs) { puts("mxc_spi: SPI Slave not allocated !\n"); @@ -397,22 +421,16 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; - ret = decode_cs(mxcs, cs); + ret = setup_cs_gpio(mxcs, bus, cs); if (ret < 0) { free(mxcs); return NULL; } - cs = ret; - mxcs->base = spi_bases[bus]; + mxcs->max_hz = max_hz; + mxcs->mode = mode; - ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); - if (ret) { - printf("mxc_spi: cannot setup SPI controller\n"); - free(mxcs); - return NULL; - } return &mxcs->slave; } @@ -425,12 +443,17 @@ void spi_free_slave(struct spi_slave *slave) int spi_claim_bus(struct spi_slave *slave) { + int ret; struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; reg_write(®s->rxdata, 1); udelay(1); - reg_write(®s->ctrl, mxcs->ctrl_reg); + ret = spi_cfg_mxc(mxcs, slave->cs); + if (ret) { + printf("mxc_spi: cannot setup SPI controller\n"); + return ret; + } reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); reg_write(®s->intr, 0); diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 3cf7142f5a..093d0c246e 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -56,8 +56,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct mxs_spi_slave *mxs_slave; - struct mxs_ssp_regs *ssp_regs; - int reg; if (!spi_cs_is_valid(bus, cs)) { printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); @@ -74,13 +72,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxs_slave->max_khz = max_hz / 1000; mxs_slave->mode = mode; mxs_slave->regs = mxs_ssp_regs_by_bus(bus); - ssp_regs = mxs_slave->regs; - reg = readl(&ssp_regs->hw_ssp_ctrl0); - reg &= ~(MXS_SSP_CHIPSELECT_MASK); - reg |= cs << MXS_SSP_CHIPSELECT_SHIFT; - - writel(reg, &ssp_regs->hw_ssp_ctrl0); return &mxs_slave->slave; err_init: @@ -102,7 +94,9 @@ int spi_claim_bus(struct spi_slave *slave) mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); - writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0); + writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) | + SSP_CTRL0_BUS_WIDTH_ONE_BIT, + &ssp_regs->hw_ssp_ctrl0); reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; @@ -142,10 +136,10 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave, while (length--) { /* We transfer 1 byte */ -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr); writel(1, &ssp_regs->hw_ssp_ctrl0_set); -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) writel(1, &ssp_regs->hw_ssp_xfer_size); #endif @@ -205,9 +199,9 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, int tl; int ret = 0; -#if defined(CONFIG_MX23) +#if defined(CONFIG_SOC_MX23) const int mxs_spi_pio_words = 1; -#elif defined(CONFIG_MX28) +#elif defined(CONFIG_SOC_MX28) const int mxs_spi_pio_words = 4; #endif @@ -291,7 +285,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, * descriptor! */ dp->cmd.pio_words[0] = ctrl0; -#ifdef CONFIG_MX28 +#ifdef CONFIG_SOC_MX28 dp->cmd.pio_words[1] = 0; dp->cmd.pio_words[2] = 0; dp->cmd.pio_words[3] = tl; diff --git a/drivers/spi/oc_tiny_spi.c b/drivers/spi/oc_tiny_spi.c index 6f7b1edd60..4de5d008aa 100644 --- a/drivers/spi/oc_tiny_spi.c +++ b/drivers/spi/oc_tiny_spi.c @@ -7,7 +7,7 @@ * Copyright (c) 2005-2008 Analog Devices Inc. * Copyright (C) 2010 Thomas Chou * - * Licensed under the GPL-2 or later. + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 6bac245721..651e46e4bd 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -20,8 +20,7 @@ #include #include "omap3_spi.h" -#define WORD_LEN 8 -#define SPI_WAIT_TIMEOUT 3000000; +#define SPI_WAIT_TIMEOUT 3000000 static void spi_reset(struct omap3_spi_slave *ds) { @@ -50,7 +49,7 @@ static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val) static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable) { writel(enable, &ds->regs->channel[ds->slave.cs].chctrl); - /* Flash post writes to make immediate effect */ + /* Flash post writes to make immediate effect */ readl(&ds->regs->channel[ds->slave.cs].chctrl); } @@ -83,7 +82,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, regs = (struct mcspi *)OMAP3_MCSPI2_BASE; break; #endif -#ifdef OMAP3_MCSPI3_BASE +#ifdef OMAP3_MCSPI3_BASE case 2: regs = (struct mcspi *)OMAP3_MCSPI3_BASE; break; @@ -185,7 +184,7 @@ int spi_claim_bus(struct spi_slave *slave) /* wordlength */ conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK; - conf |= (WORD_LEN - 1) << 7; + conf |= (ds->slave.wordlen - 1) << 7; /* set chipselect polarity; manage with FORCE */ if (!(ds->mode & SPI_CS_HIGH)) @@ -223,7 +222,7 @@ void spi_release_bus(struct spi_slave *slave) spi_reset(ds); } -int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, +int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp, unsigned long flags) { struct omap3_spi_slave *ds = to_omap3_spi(slave); @@ -234,7 +233,8 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, /* Enable the channel */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); - chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; + chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); + chconf |= (ds->slave.wordlen - 1) << 7; chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY; chconf |= OMAP3_MCSPI_CHCONF_FORCE; omap3_spi_write_chconf(ds,chconf); @@ -250,12 +250,19 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, } } /* Write the data */ - writel(txp[i], &ds->regs->channel[ds->slave.cs].tx); + unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx; + if (ds->slave.wordlen > 16) + writel(((u32 *)txp)[i], tx); + else if (ds->slave.wordlen > 8) + writel(((u16 *)txp)[i], tx); + else + writel(((u8 *)txp)[i], tx); } - /* wait to finish of transfer */ - while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & - OMAP3_MCSPI_CHSTAT_EOT)); + /* wait to finish of transfer */ + while ((readl(&ds->regs->channel[ds->slave.cs].chstat) & + (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) != + (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)); /* Disable the channel otherwise the next immediate RX will get affected */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); @@ -268,7 +275,7 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, return 0; } -int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, +int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp, unsigned long flags) { struct omap3_spi_slave *ds = to_omap3_spi(slave); @@ -279,7 +286,8 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, /* Enable the channel */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); - chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; + chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); + chconf |= (ds->slave.wordlen - 1) << 7; chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY; chconf |= OMAP3_MCSPI_CHCONF_FORCE; omap3_spi_write_chconf(ds,chconf); @@ -302,7 +310,13 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); /* Read the data */ - rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx); + unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx; + if (ds->slave.wordlen > 16) + ((u32 *)rxp)[i] = readl(rx); + else if (ds->slave.wordlen > 8) + ((u16 *)rxp)[i] = (u16)readl(rx); + else + ((u8 *)rxp)[i] = (u8)readl(rx); } if (flags & SPI_XFER_END) { @@ -314,8 +328,8 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, } /*McSPI Transmit Receive Mode*/ -int omap3_spi_txrx(struct spi_slave *slave, - unsigned int len, const u8 *txp, u8 *rxp, unsigned long flags) +int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, + const void *txp, void *rxp, unsigned long flags) { struct omap3_spi_slave *ds = to_omap3_spi(slave); int timeout = SPI_WAIT_TIMEOUT; @@ -327,7 +341,8 @@ int omap3_spi_txrx(struct spi_slave *slave, omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); /*set TRANSMIT-RECEIVE Mode*/ - chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; + chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); + chconf |= (ds->slave.wordlen - 1) << 7; chconf |= OMAP3_MCSPI_CHCONF_FORCE; omap3_spi_write_chconf(ds,chconf); @@ -344,7 +359,13 @@ int omap3_spi_txrx(struct spi_slave *slave, } } /* Write the data */ - writel(txp[i], &ds->regs->channel[ds->slave.cs].tx); + unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx; + if (ds->slave.wordlen > 16) + writel(((u32 *)txp)[i], tx); + else if (ds->slave.wordlen > 8) + writel(((u16 *)txp)[i], tx); + else + writel(((u8 *)txp)[i], tx); /*Read: wait for RX containing data (RXS == 1)*/ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & @@ -356,10 +377,16 @@ int omap3_spi_txrx(struct spi_slave *slave, } } /* Read the data */ - rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx); + unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx; + if (ds->slave.wordlen > 16) + ((u32 *)rxp)[i] = readl(rx); + else if (ds->slave.wordlen > 8) + ((u16 *)rxp)[i] = (u16)readl(rx); + else + ((u8 *)rxp)[i] = (u8)readl(rx); } /* Disable the channel */ - omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); /*if transfer must be terminated disable the channel*/ if (flags & SPI_XFER_END) { @@ -375,14 +402,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, { struct omap3_spi_slave *ds = to_omap3_spi(slave); unsigned int len; - const u8 *txp = dout; - u8 *rxp = din; int ret = -1; - if (bitlen % 8) + if (ds->slave.wordlen < 4 || ds->slave.wordlen > 32) { + printf("omap3_spi: invalid wordlen %d\n", ds->slave.wordlen); + return -1; + } + + if (bitlen % ds->slave.wordlen) return -1; - len = bitlen / 8; + len = bitlen / ds->slave.wordlen; if (bitlen == 0) { /* only change CS */ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf); @@ -400,11 +430,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, ret = 0; } else { if (dout != NULL && din != NULL) - ret = omap3_spi_txrx(slave, len, txp, rxp, flags); + ret = omap3_spi_txrx(slave, len, dout, din, flags); else if (dout != NULL) - ret = omap3_spi_write(slave, len, txp, flags); + ret = omap3_spi_write(slave, len, dout, flags); else if (din != NULL) - ret = omap3_spi_read(slave, len, rxp, flags); + ret = omap3_spi_read(slave, len, din, flags); } return ret; } diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h index 01537b6246..ab7cd84448 100644 --- a/drivers/spi/omap3_spi.h +++ b/drivers/spi/omap3_spi.h @@ -99,11 +99,11 @@ static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave) return container_of(slave, struct omap3_spi_slave, slave); } -int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp, - u8 *rxp, unsigned long flags); -int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, +int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const void *txp, + void *rxp, unsigned long flags); +int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp, unsigned long flags); -int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, +int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp, unsigned long flags); #endif /* _OMAP3_SPI_H_ */ diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c new file mode 100644 index 0000000000..bad56603ba --- /dev/null +++ b/drivers/spi/sandbox_spi.c @@ -0,0 +1,164 @@ +/* + * Simulate a SPI port + * + * Copyright (c) 2011-2013 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SPI_IDLE_VAL +# define CONFIG_SPI_IDLE_VAL 0xFF +#endif + +const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus, + unsigned long *cs) +{ + char *endp; + + *bus = simple_strtoul(arg, &endp, 0); + if (*endp != ':' || *bus >= CONFIG_SANDBOX_SPI_MAX_BUS) + return NULL; + + *cs = simple_strtoul(endp + 1, &endp, 0); + if (*endp != ':' || *cs >= CONFIG_SANDBOX_SPI_MAX_CS) + return NULL; + + return endp + 1; +} + +__weak int sandbox_spi_get_emul(struct sandbox_state *state, + struct udevice *bus, struct udevice *slave, + struct udevice **emulp) +{ + return -ENOENT; +} + +static int sandbox_spi_xfer(struct udevice *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = slave->parent; + struct sandbox_state *state = state_get_current(); + struct dm_spi_emul_ops *ops; + struct udevice *emul; + uint bytes = bitlen / 8, i; + int ret; + u8 *tx = (void *)dout, *rx = din; + uint busnum, cs; + + if (bitlen == 0) + return 0; + + /* we can only do 8 bit transfers */ + if (bitlen % 8) { + printf("sandbox_spi: xfer: invalid bitlen size %u; needs to be 8bit\n", + bitlen); + return -EINVAL; + } + + busnum = bus->seq; + cs = spi_chip_select(slave); + if (busnum >= CONFIG_SANDBOX_SPI_MAX_BUS || + cs >= CONFIG_SANDBOX_SPI_MAX_CS) { + printf("%s: busnum=%u, cs=%u: out of range\n", __func__, + busnum, cs); + return -ENOENT; + } + ret = sandbox_spi_get_emul(state, bus, slave, &emul); + if (ret) { + printf("%s: busnum=%u, cs=%u: no emulation available (err=%d)\n", + __func__, busnum, cs, ret); + return -ENOENT; + } + ret = device_probe(emul); + if (ret) + return ret; + + /* make sure rx/tx buffers are full so clients can assume */ + if (!tx) { + debug("sandbox_spi: xfer: auto-allocating tx scratch buffer\n"); + tx = malloc(bytes); + if (!tx) { + debug("sandbox_spi: Out of memory\n"); + return -ENOMEM; + } + } + if (!rx) { + debug("sandbox_spi: xfer: auto-allocating rx scratch buffer\n"); + rx = malloc(bytes); + if (!rx) { + debug("sandbox_spi: Out of memory\n"); + return -ENOMEM; + } + } + + ops = spi_emul_get_ops(emul); + ret = ops->xfer(emul, bitlen, dout, din, flags); + + debug("sandbox_spi: xfer: got back %i (that's %s)\n rx:", + ret, ret ? "bad" : "good"); + for (i = 0; i < bytes; ++i) + debug(" %u:%02x", i, rx[i]); + debug("\n"); + + if (tx != dout) + free(tx); + if (rx != din) + free(rx); + + return ret; +} + +static int sandbox_spi_set_speed(struct udevice *bus, uint speed) +{ + return 0; +} + +static int sandbox_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int sandbox_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + /* Always allow activity on CS 0 */ + if (cs >= 1) + return -ENODEV; + + return 0; +} + +static const struct dm_spi_ops sandbox_spi_ops = { + .xfer = sandbox_spi_xfer, + .set_speed = sandbox_spi_set_speed, + .set_mode = sandbox_spi_set_mode, + .cs_info = sandbox_cs_info, +}; + +static const struct udevice_id sandbox_spi_ids[] = { + { .compatible = "sandbox,spi" }, + { } +}; + +U_BOOT_DRIVER(spi_sandbox) = { + .name = "spi_sandbox", + .id = UCLASS_SPI, + .of_match = sandbox_spi_ids, + .ops = &sandbox_spi_ops, +}; diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c new file mode 100644 index 0000000000..77ede6bba3 --- /dev/null +++ b/drivers/spi/sh_qspi.c @@ -0,0 +1,278 @@ +/* + * SH QSPI (Quad SPI) driver + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +/* SH QSPI register bit masks _ */ +#define SPCR_MSTR 0x08 +#define SPCR_SPE 0x40 +#define SPSR_SPRFF 0x80 +#define SPSR_SPTEF 0x20 +#define SPPCR_IO3FV 0x04 +#define SPPCR_IO2FV 0x02 +#define SPPCR_IO1FV 0x01 +#define SPBDCR_RXBC0 (1 << 0) +#define SPCMD_SCKDEN (1 << 15) +#define SPCMD_SLNDEN (1 << 14) +#define SPCMD_SPNDEN (1 << 13) +#define SPCMD_SSLKP (1 << 7) +#define SPCMD_BRDV0 (1 << 2) +#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ + SPCMD_SPNDEN | SPCMD_SSLKP | \ + SPCMD_BRDV0 +#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ + SPCMD_BRDV0 +#define SPBFCR_TXRST (1 << 7) +#define SPBFCR_RXRST (1 << 6) + +/* SH QSPI register set */ +struct sh_qspi_regs { + unsigned char spcr; + unsigned char sslp; + unsigned char sppcr; + unsigned char spsr; + unsigned long spdr; + unsigned char spscr; + unsigned char spssr; + unsigned char spbr; + unsigned char spdcr; + unsigned char spckd; + unsigned char sslnd; + unsigned char spnd; + unsigned char dummy0; + unsigned short spcmd0; + unsigned short spcmd1; + unsigned short spcmd2; + unsigned short spcmd3; + unsigned char spbfcr; + unsigned char dummy1; + unsigned short spbdcr; + unsigned long spbmul0; + unsigned long spbmul1; + unsigned long spbmul2; + unsigned long spbmul3; +}; + +struct sh_qspi_slave { + struct spi_slave slave; + struct sh_qspi_regs *regs; +}; + +static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave) +{ + return container_of(slave, struct sh_qspi_slave, slave); +} + +static void sh_qspi_init(struct sh_qspi_slave *ss) +{ + /* QSPI initialize */ + /* Set master mode only */ + writeb(SPCR_MSTR, &ss->regs->spcr); + + /* Set SSL signal level */ + writeb(0x00, &ss->regs->sslp); + + /* Set MOSI signal value when transfer is in idle state */ + writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); + + /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */ + writeb(0x01, &ss->regs->spbr); + + /* Disable Dummy Data Transmission */ + writeb(0x00, &ss->regs->spdcr); + + /* Set clock delay value */ + writeb(0x00, &ss->regs->spckd); + + /* Set SSL negation delay value */ + writeb(0x00, &ss->regs->sslnd); + + /* Set next-access delay value */ + writeb(0x00, &ss->regs->spnd); + + /* Set equence command */ + writew(SPCMD_INIT2, &ss->regs->spcmd0); + + /* Reset transfer and receive Buffer */ + setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); + + /* Clear transfer and receive Buffer control bit */ + clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); + + /* Set equence control method. Use equence0 only */ + writeb(0x00, &ss->regs->spscr); + + /* Enable SPI function */ + setbits_8(&ss->regs->spcr, SPCR_SPE); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + + /* Set master mode only */ + writeb(SPCR_MSTR, &ss->regs->spcr); + + /* Set command */ + writew(SPCMD_INIT1, &ss->regs->spcmd0); + + /* Reset transfer and receive Buffer */ + setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); + + /* Clear transfer and receive Buffer control bit */ + clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); + + /* Set equence control method. Use equence0 only */ + writeb(0x00, &ss->regs->spscr); + + /* Enable SPI function */ + setbits_8(&ss->regs->spcr, SPCR_SPE); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + + /* Disable SPI Function */ + clrbits_8(&ss->regs->spcr, SPCR_SPE); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct sh_qspi_slave *ss; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs); + if (!ss) { + printf("SPI_error: Fail to allocate sh_qspi_slave\n"); + return NULL; + } + + ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE; + + /* Init SH QSPI */ + sh_qspi_init(ss); + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct sh_qspi_slave *spi = to_sh_qspi(slave); + + free(spi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + unsigned long nbyte; + int ret = 0; + unsigned char dtdata = 0, drdata; + unsigned char *tdata = &dtdata, *rdata = &drdata; + unsigned long *spbmul0 = &ss->regs->spbmul0; + + if (dout == NULL && din == NULL) { + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + return 0; + } + + if (bitlen % 8) { + printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); + return 1; + } + + nbyte = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) { + spi_cs_activate(slave); + + /* Set 1048576 byte */ + writel(0x100000, spbmul0); + } + + if (flags & SPI_XFER_END) + writel(nbyte, spbmul0); + + if (dout != NULL) + tdata = (unsigned char *)dout; + + if (din != NULL) + rdata = din; + + while (nbyte > 0) { + while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(10); + } + + writeb(*tdata, (unsigned char *)(&ss->regs->spdr)); + + while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(1); + } + + while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(10); + } + + *rdata = readb((unsigned char *)(&ss->regs->spdr)); + + if (dout != NULL) + tdata++; + if (din != NULL) + rdata++; + + nbyte--; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c index 744afe3295..7ca5e363da 100644 --- a/drivers/spi/sh_spi.c +++ b/drivers/spi/sh_spi.c @@ -151,7 +151,6 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, { int i, cur_len, ret = 0; int remain = (int)len; - unsigned long tmp; if (len >= SH_SPI_FIFO_SIZE) sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); @@ -183,9 +182,7 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, } if (flags & SPI_XFER_END) { - tmp = sh_spi_read(&ss->regs->cr1); - tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); - sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); udelay(100); write_fifo_empty_wait(ss); @@ -198,16 +195,13 @@ static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data, unsigned int len, unsigned long flags) { int i; - unsigned long tmp; if (len > SH_SPI_MAX_BYTE) sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3); else sh_spi_write(len, &ss->regs->cr3); - tmp = sh_spi_read(&ss->regs->cr1); - tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); - sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); for (i = 0; i < len; i++) { diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 5d22351290..6ae45f5377 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -1,4 +1,6 @@ /* + * Copyright (c) 2014 Google, Inc + * * (C) Copyright 2002 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. * @@ -9,94 +11,78 @@ */ #include +#include +#include +#include +#include #include +#include -#include +DECLARE_GLOBAL_DATA_PTR; -/*----------------------------------------------------------------------- - * Definitions - */ - -#ifdef DEBUG_SPI -#define PRINTD(fmt,args...) printf (fmt ,##args) -#else -#define PRINTD(fmt,args...) -#endif +struct soft_spi_platdata { + struct gpio_desc cs; + struct gpio_desc sclk; + struct gpio_desc mosi; + struct gpio_desc miso; + int spi_delay_us; +}; -struct soft_spi_slave { - struct spi_slave slave; +struct soft_spi_priv { unsigned int mode; }; -static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave) +static int soft_spi_scl(struct udevice *dev, int bit) { - return container_of(slave, struct soft_spi_slave, slave); -} - -/*=====================================================================*/ -/* Public Functions */ -/*=====================================================================*/ + struct soft_spi_platdata *plat = dev->platdata; -/*----------------------------------------------------------------------- - * Initialization - */ -void spi_init (void) -{ -#ifdef SPI_INIT - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + dm_gpio_set_value(&plat->sclk, bit); - SPI_INIT; -#endif + return 0; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static int soft_spi_sda(struct udevice *dev, int bit) { - struct soft_spi_slave *ss; + struct soft_spi_platdata *plat = dev->platdata; - if (!spi_cs_is_valid(bus, cs)) - return NULL; + dm_gpio_set_value(&plat->mosi, bit); - ss = spi_alloc_slave(struct soft_spi_slave, bus, cs); - if (!ss) - return NULL; + return 0; +} - ss->mode = mode; +static int soft_spi_cs_activate(struct udevice *dev) +{ + struct soft_spi_platdata *plat = dev->platdata; - /* TODO: Use max_hz to limit the SCK rate */ + dm_gpio_set_value(&plat->cs, 0); + dm_gpio_set_value(&plat->sclk, 0); + dm_gpio_set_value(&plat->cs, 1); - return &ss->slave; + return 0; } -void spi_free_slave(struct spi_slave *slave) +static int soft_spi_cs_deactivate(struct udevice *dev) { - struct soft_spi_slave *ss = to_soft_spi(slave); + struct soft_spi_platdata *plat = dev->platdata; - free(ss); + dm_gpio_set_value(&plat->cs, 0); + + return 0; } -int spi_claim_bus(struct spi_slave *slave) +static int soft_spi_claim_bus(struct udevice *dev) { -#ifdef CONFIG_SYS_IMMR - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; -#endif - struct soft_spi_slave *ss = to_soft_spi(slave); - /* * Make sure the SPI clock is in idle state as defined for * this slave. */ - if (ss->mode & SPI_CPOL) - SPI_SCL(1); - else - SPI_SCL(0); - - return 0; + return soft_spi_scl(dev, 0); } -void spi_release_bus(struct spi_slave *slave) +static int soft_spi_release_bus(struct udevice *dev) { /* Nothing to do */ + return 0; } /*----------------------------------------------------------------------- @@ -111,65 +97,140 @@ void spi_release_bus(struct spi_slave *slave) * input data overwrites the output data (since both are buffered by * temporary variables, this is OK). */ -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { -#ifdef CONFIG_SYS_IMMR - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; -#endif - struct soft_spi_slave *ss = to_soft_spi(slave); + struct soft_spi_priv *priv = dev_get_priv(dev); + struct soft_spi_platdata *plat = dev->platdata; uchar tmpdin = 0; uchar tmpdout = 0; const u8 *txd = dout; u8 *rxd = din; - int cpol = ss->mode & SPI_CPOL; - int cpha = ss->mode & SPI_CPHA; + int cpha = priv->mode & SPI_CPHA; unsigned int j; - PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", - slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen); + debug("spi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n", + dev->parent->name, dev->name, *(uint *)txd, *(uint *)rxd, + bitlen); if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + soft_spi_cs_activate(dev); - for(j = 0; j < bitlen; j++) { + for (j = 0; j < bitlen; j++) { /* * Check if it is time to work on a new byte. */ - if((j % 8) == 0) { - tmpdout = *txd++; - if(j != 0) { - *rxd++ = tmpdin; + if ((j % 8) == 0) { + if (txd) + tmpdout = *txd++; + else + tmpdout = 0; + if (j != 0) { + if (rxd) + *rxd++ = tmpdin; } tmpdin = 0; } if (!cpha) - SPI_SCL(!cpol); - SPI_SDA(tmpdout & 0x80); - SPI_DELAY; + soft_spi_scl(dev, 0); + soft_spi_sda(dev, tmpdout & 0x80); + udelay(plat->spi_delay_us); if (cpha) - SPI_SCL(!cpol); + soft_spi_scl(dev, 0); else - SPI_SCL(cpol); + soft_spi_scl(dev, 1); tmpdin <<= 1; - tmpdin |= SPI_READ; + tmpdin |= dm_gpio_get_value(&plat->miso); tmpdout <<= 1; - SPI_DELAY; + udelay(plat->spi_delay_us); if (cpha) - SPI_SCL(cpol); + soft_spi_scl(dev, 1); } /* * If the number of bits isn't a multiple of 8, shift the last * bits over to left-justify them. Then store the last byte * read in. */ - if((bitlen % 8) != 0) - tmpdin <<= 8 - (bitlen % 8); - *rxd++ = tmpdin; + if (rxd) { + if ((bitlen % 8) != 0) + tmpdin <<= 8 - (bitlen % 8); + *rxd++ = tmpdin; + } if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + soft_spi_cs_deactivate(dev); + + return 0; +} + +static int soft_spi_set_speed(struct udevice *dev, unsigned int speed) +{ + /* Accept any speed */ + return 0; +} + +static int soft_spi_set_mode(struct udevice *dev, unsigned int mode) +{ + struct soft_spi_priv *priv = dev_get_priv(dev); + + priv->mode = mode; + + return 0; +} + +static const struct dm_spi_ops soft_spi_ops = { + .claim_bus = soft_spi_claim_bus, + .release_bus = soft_spi_release_bus, + .xfer = soft_spi_xfer, + .set_speed = soft_spi_set_speed, + .set_mode = soft_spi_set_mode, +}; - return(0); +static int soft_spi_ofdata_to_platdata(struct udevice *dev) +{ + struct soft_spi_platdata *plat = dev->platdata; + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + + plat->spi_delay_us = fdtdec_get_int(blob, node, "spi-delay-us", 0); + + return 0; } + +static int soft_spi_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parentdata(dev); + struct soft_spi_platdata *plat = dev->platdata; + int cs_flags, clk_flags; + + cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW; + clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0; + if (gpio_request_by_name(dev, "cs-gpio", 0, &plat->cs, + GPIOD_IS_OUT | cs_flags) || + gpio_request_by_name(dev, "sclk-gpio", 0, &plat->sclk, + GPIOD_IS_OUT | clk_flags) || + gpio_request_by_name(dev, "mosi-gpio", 0, &plat->mosi, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE) || + gpio_request_by_name(dev, "miso-gpio", 0, &plat->miso, + GPIOD_IS_IN)) + return -EINVAL; + + return 0; +} + +static const struct udevice_id soft_spi_ids[] = { + { .compatible = "u-boot,soft-spi" }, + { } +}; + +U_BOOT_DRIVER(soft_spi) = { + .name = "soft_spi", + .id = UCLASS_SPI, + .of_match = soft_spi_ids, + .ops = &soft_spi_ops, + .ofdata_to_platdata = soft_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct soft_spi_platdata), + .priv_auto_alloc_size = sizeof(struct soft_spi_priv), + .probe = soft_spi_probe, +}; diff --git a/drivers/spi/soft_spi_legacy.c b/drivers/spi/soft_spi_legacy.c new file mode 100644 index 0000000000..941daa730b --- /dev/null +++ b/drivers/spi/soft_spi_legacy.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2002 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * Influenced by code from: + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include + +/*----------------------------------------------------------------------- + * Definitions + */ + +#ifdef DEBUG_SPI +#define PRINTD(fmt,args...) printf (fmt ,##args) +#else +#define PRINTD(fmt,args...) +#endif + +struct soft_spi_slave { + struct spi_slave slave; + unsigned int mode; +}; + +static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave) +{ + return container_of(slave, struct soft_spi_slave, slave); +} + +/*=====================================================================*/ +/* Public Functions */ +/*=====================================================================*/ + +/*----------------------------------------------------------------------- + * Initialization + */ +void spi_init (void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct soft_spi_slave *ss; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ss = spi_alloc_slave(struct soft_spi_slave, bus, cs); + if (!ss) + return NULL; + + ss->mode = mode; + + /* TODO: Use max_hz to limit the SCK rate */ + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct soft_spi_slave *ss = to_soft_spi(slave); + + free(ss); +} + +int spi_claim_bus(struct spi_slave *slave) +{ +#ifdef CONFIG_SYS_IMMR + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; +#endif + struct soft_spi_slave *ss = to_soft_spi(slave); + + /* + * Make sure the SPI clock is in idle state as defined for + * this slave. + */ + if (ss->mode & SPI_CPOL) + SPI_SCL(1); + else + SPI_SCL(0); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Nothing to do */ +} + +/*----------------------------------------------------------------------- + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks + * "bitlen" bits in the SPI MISO port. That's just the way SPI works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that "dout" + * and "din" can point to the same memory location, in which case the + * input data overwrites the output data (since both are buffered by + * temporary variables, this is OK). + */ +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ +#ifdef CONFIG_SYS_IMMR + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; +#endif + struct soft_spi_slave *ss = to_soft_spi(slave); + uchar tmpdin = 0; + uchar tmpdout = 0; + const u8 *txd = dout; + u8 *rxd = din; + int cpol = ss->mode & SPI_CPOL; + int cpha = ss->mode & SPI_CPHA; + unsigned int j; + + PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + for(j = 0; j < bitlen; j++) { + /* + * Check if it is time to work on a new byte. + */ + if ((j % 8) == 0) { + if (txd) + tmpdout = *txd++; + else + tmpdout = 0; + if(j != 0) { + if (rxd) + *rxd++ = tmpdin; + } + tmpdin = 0; + } + + if (!cpha) + SPI_SCL(!cpol); + SPI_SDA(tmpdout & 0x80); + SPI_DELAY; + if (cpha) + SPI_SCL(!cpol); + else + SPI_SCL(cpol); + tmpdin <<= 1; + tmpdin |= SPI_READ; + tmpdout <<= 1; + SPI_DELAY; + if (cpha) + SPI_SCL(cpol); + } + /* + * If the number of bits isn't a multiple of 8, shift the last + * bits over to left-justify them. Then store the last byte + * read in. + */ + if (rxd) { + if ((bitlen % 8) != 0) + tmpdin <<= 8 - (bitlen % 8); + *rxd++ = tmpdin; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return(0); +} diff --git a/drivers/spi/spi-emul-uclass.c b/drivers/spi/spi-emul-uclass.c new file mode 100644 index 0000000000..b436a0e99f --- /dev/null +++ b/drivers/spi/spi-emul-uclass.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +UCLASS_DRIVER(spi_emul) = { + .id = UCLASS_SPI_EMUL, + .name = "spi_emul", +}; diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c new file mode 100644 index 0000000000..63a6217cc6 --- /dev/null +++ b/drivers/spi/spi-uclass.c @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int spi_set_speed_mode(struct udevice *bus, int speed, int mode) +{ + struct dm_spi_ops *ops; + int ret; + + ops = spi_get_ops(bus); + if (ops->set_speed) + ret = ops->set_speed(bus, speed); + else + ret = -EINVAL; + if (ret) { + printf("Cannot set speed (err=%d)\n", ret); + return ret; + } + + if (ops->set_mode) + ret = ops->set_mode(bus, mode); + else + ret = -EINVAL; + if (ret) { + printf("Cannot set mode (err=%d)\n", ret); + return ret; + } + + return 0; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct udevice *dev = slave->dev; + struct udevice *bus = dev->parent; + struct dm_spi_ops *ops = spi_get_ops(bus); + struct dm_spi_bus *spi = bus->uclass_priv; + int speed; + int ret; + + speed = slave->max_hz; + if (spi->max_hz) { + if (speed) + speed = min(speed, (int)spi->max_hz); + else + speed = spi->max_hz; + } + if (!speed) + speed = 100000; + ret = spi_set_speed_mode(bus, speed, slave->mode); + if (ret) + return ret; + + return ops->claim_bus ? ops->claim_bus(bus) : 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct udevice *dev = slave->dev; + struct udevice *bus = dev->parent; + struct dm_spi_ops *ops = spi_get_ops(bus); + + if (ops->release_bus) + ops->release_bus(bus); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *dev = slave->dev; + struct udevice *bus = dev->parent; + + if (bus->uclass->uc_drv->id != UCLASS_SPI) + return -EOPNOTSUPP; + + return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags); +} + +int spi_post_bind(struct udevice *dev) +{ + /* Scan the bus for devices */ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + +int spi_child_post_bind(struct udevice *dev) +{ + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + + if (dev->of_offset == -1) + return 0; + + return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat); +} + +int spi_post_probe(struct udevice *bus) +{ + struct dm_spi_bus *spi = bus->uclass_priv; + + spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset, + "spi-max-frequency", 0); + + return 0; +} + +int spi_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + struct spi_slave *slave = dev_get_parentdata(dev); + + /* + * This is needed because we pass struct spi_slave around the place + * instead slave->dev (a struct udevice). So we have to have some + * way to access the slave udevice given struct spi_slave. Once we + * change the SPI API to use udevice instead of spi_slave, we can + * drop this. + */ + slave->dev = dev; + + slave->max_hz = plat->max_hz; + slave->mode = plat->mode; + + return 0; +} + +int spi_chip_select(struct udevice *dev) +{ + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + + return plat ? plat->cs : -ENOENT; +} + +int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp) +{ + struct udevice *dev; + + for (device_find_first_child(bus, &dev); dev; + device_find_next_child(&dev)) { + struct dm_spi_slave_platdata *plat; + + plat = dev_get_parent_platdata(dev); + debug("%s: plat=%p, cs=%d\n", __func__, plat, plat->cs); + if (plat->cs == cs) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + +int spi_cs_is_valid(unsigned int busnum, unsigned int cs) +{ + struct spi_cs_info info; + struct udevice *bus; + int ret; + + ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus); + if (ret) { + debug("%s: No bus %d\n", __func__, busnum); + return ret; + } + + return spi_cs_info(bus, cs, &info); +} + +int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info) +{ + struct spi_cs_info local_info; + struct dm_spi_ops *ops; + int ret; + + if (!info) + info = &local_info; + + /* If there is a device attached, return it */ + info->dev = NULL; + ret = spi_find_chip_select(bus, cs, &info->dev); + if (!ret) + return 0; + + /* + * Otherwise ask the driver. For the moment we don't have CS info. + * When we do we could provide the driver with a helper function + * to figure out what chip selects are valid, or just handle the + * request. + */ + ops = spi_get_ops(bus); + if (ops->cs_info) + return ops->cs_info(bus, cs, info); + + /* + * We could assume there is at least one valid chip select, but best + * to be sure and return an error in this case. The driver didn't + * care enough to tell us. + */ + return -ENODEV; +} + +int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, + struct udevice **devp) +{ + struct udevice *bus, *dev; + int ret; + + ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus); + if (ret) { + debug("%s: No bus %d\n", __func__, busnum); + return ret; + } + ret = spi_find_chip_select(bus, cs, &dev); + if (ret) { + debug("%s: No cs %d\n", __func__, cs); + return ret; + } + *busp = bus; + *devp = dev; + + return ret; +} + +int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, + const char *drv_name, const char *dev_name, + struct udevice **busp, struct spi_slave **devp) +{ + struct udevice *bus, *dev; + bool created = false; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus); + if (ret) { + printf("Invalid bus %d (err=%d)\n", busnum, ret); + return ret; + } + ret = spi_find_chip_select(bus, cs, &dev); + + /* + * If there is no such device, create one automatically. This means + * that we don't need a device tree node or platform data for the + * SPI flash chip - we will bind to the correct driver. + */ + if (ret == -ENODEV && drv_name) { + struct dm_spi_slave_platdata *plat; + + debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n", + __func__, dev_name, busnum, cs, drv_name); + ret = device_bind_driver(bus, drv_name, dev_name, &dev); + if (ret) + return ret; + plat = dev_get_parent_platdata(dev); + plat->cs = cs; + plat->max_hz = speed; + plat->mode = mode; + created = true; + } else if (ret) { + printf("Invalid chip select %d:%d (err=%d)\n", busnum, cs, + ret); + return ret; + } + + if (!device_active(dev)) { + struct spi_slave *slave; + + ret = device_probe(dev); + if (ret) + goto err; + slave = dev_get_parentdata(dev); + slave->dev = dev; + } + + ret = spi_set_speed_mode(bus, speed, mode); + if (ret) + goto err; + + *busp = bus; + *devp = dev_get_parentdata(dev); + debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp); + + return 0; + +err: + debug("%s: Error path, credted=%d, device '%s'\n", __func__, + created, dev->name); + if (created) { + device_remove(dev); + device_unbind(dev); + } + + return ret; +} + +/* Compatibility function - to be removed */ +struct spi_slave *spi_setup_slave_fdt(const void *blob, int node, + int bus_node) +{ + struct udevice *bus, *dev; + int ret; + + ret = uclass_get_device_by_of_offset(UCLASS_SPI, bus_node, &bus); + if (ret) + return NULL; + ret = device_get_child_by_of_offset(bus, node, &dev); + if (ret) + return NULL; + return dev_get_parentdata(dev); +} + +/* Compatibility function - to be removed */ +struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs, + unsigned int speed, unsigned int mode) +{ + struct spi_slave *slave; + struct udevice *dev; + int ret; + + ret = spi_get_bus_and_cs(busnum, cs, speed, mode, NULL, 0, &dev, + &slave); + if (ret) + return NULL; + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + device_remove(slave->dev); + slave->dev = NULL; +} + +int spi_slave_ofdata_to_platdata(const void *blob, int node, + struct dm_spi_slave_platdata *plat) +{ + int mode = 0; + + plat->cs = fdtdec_get_int(blob, node, "reg", -1); + plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0); + if (fdtdec_get_bool(blob, node, "spi-cpol")) + mode |= SPI_CPOL; + if (fdtdec_get_bool(blob, node, "spi-cpha")) + mode |= SPI_CPHA; + if (fdtdec_get_bool(blob, node, "spi-cs-high")) + mode |= SPI_CS_HIGH; + if (fdtdec_get_bool(blob, node, "spi-half-duplex")) + mode |= SPI_PREAMBLE; + plat->mode = mode; + + return 0; +} + +UCLASS_DRIVER(spi) = { + .id = UCLASS_SPI, + .name = "spi", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .post_bind = spi_post_bind, + .post_probe = spi_post_probe, + .child_pre_probe = spi_child_pre_probe, + .per_device_auto_alloc_size = sizeof(struct dm_spi_bus), + .per_child_auto_alloc_size = sizeof(struct spi_slave), + .per_child_platdata_auto_alloc_size = + sizeof(struct dm_spi_slave_platdata), + .child_post_bind = spi_child_post_bind, +}; + +UCLASS_DRIVER(spi_generic) = { + .id = UCLASS_SPI_GENERIC, + .name = "spi_generic", +}; + +U_BOOT_DRIVER(spi_generic_drv) = { + .name = "spi_generic_drv", + .id = UCLASS_SPI_GENERIC, +}; diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index ea39d1a1ee..7d81fbd7f8 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -5,9 +5,22 @@ */ #include +#include #include #include +int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen) +{ + if (wordlen == 0 || wordlen > 32) { + printf("spi: invalid wordlen %d\n", wordlen); + return -1; + } + + slave->wordlen = wordlen; + + return 0; +} + void *spi_do_alloc_slave(int offset, int size, unsigned int bus, unsigned int cs) { @@ -20,7 +33,28 @@ void *spi_do_alloc_slave(int offset, int size, unsigned int bus, slave = (struct spi_slave *)(ptr + offset); slave->bus = bus; slave->cs = cs; + slave->wordlen = SPI_DEFAULT_WORDLEN; } return ptr; } + +#ifdef CONFIG_OF_SPI +struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum, + int node) +{ + int cs, max_hz, mode = 0; + + cs = fdtdec_get_int(blob, node, "reg", -1); + max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 100000); + if (fdtdec_get_bool(blob, node, "spi-cpol")) + mode |= SPI_CPOL; + if (fdtdec_get_bool(blob, node, "spi-cpha")) + mode |= SPI_CPHA; + if (fdtdec_get_bool(blob, node, "spi-cs-high")) + mode |= SPI_CS_HIGH; + if (fdtdec_get_bool(blob, node, "spi-half-duplex")) + mode |= SPI_PREAMBLE; + return spi_setup_slave(busnum, cs, max_hz, mode); +} +#endif diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 4d2af483d7..53ff9ea221 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -22,14 +22,13 @@ */ #include -#include +#include #include -#include #include #include -#include #include #include +#include "tegra_spi.h" DECLARE_GLOBAL_DATA_PTR; @@ -104,130 +103,63 @@ struct spi_regs { u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ }; -struct tegra_spi_ctrl { +struct tegra114_spi_priv { struct spi_regs *regs; unsigned int freq; unsigned int mode; int periph_id; int valid; + int last_transaction_us; }; -struct tegra_spi_slave { - struct spi_slave slave; - struct tegra_spi_ctrl *ctrl; -}; - -static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS]; - -static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) -{ - return container_of(slave, struct tegra_spi_slave, slave); -} - -int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs) +static int tegra114_spi_ofdata_to_platdata(struct udevice *bus) { - if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid) - return 0; - else - return 1; -} + struct tegra_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; -struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct tegra_spi_slave *spi; + plat->base = fdtdec_get_addr(blob, node, "reg"); + plat->periph_id = clock_decode_periph_id(blob, node); - debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__, - bus, cs, max_hz, mode); - - if (!spi_cs_is_valid(bus, cs)) { - printf("SPI error: unsupported bus %d / chip select %d\n", - bus, cs); - return NULL; - } - - if (max_hz > TEGRA_SPI_MAX_FREQ) { - printf("SPI error: unsupported frequency %d Hz. Max frequency" - " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); - return NULL; + if (plat->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id %d\n", __func__, + plat->periph_id); + return -FDT_ERR_NOTFOUND; } - spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs); - if (!spi) { - printf("SPI error: malloc of SPI structure failed\n"); - return NULL; - } - spi->ctrl = &spi_ctrls[bus]; - if (!spi->ctrl) { - printf("SPI error: could not find controller for bus %d\n", - bus); - return NULL; - } - - if (max_hz < spi->ctrl->freq) { - debug("%s: limiting frequency from %u to %u\n", __func__, - spi->ctrl->freq, max_hz); - spi->ctrl->freq = max_hz; - } - spi->ctrl->mode = mode; + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->base, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); - return &spi->slave; -} - -void tegra114_spi_free_slave(struct spi_slave *slave) -{ - struct tegra_spi_slave *spi = to_tegra_spi(slave); - - free(spi); + return 0; } -int tegra114_spi_init(int *node_list, int count) +static int tegra114_spi_probe(struct udevice *bus) { - struct tegra_spi_ctrl *ctrl; - int i; - int node = 0; - int found = 0; - - for (i = 0; i < count; i++) { - ctrl = &spi_ctrls[i]; - node = node_list[i]; - - ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, - node, "reg"); - if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { - debug("%s: no spi register found\n", __func__); - continue; - } - ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, - "spi-max-frequency", 0); - if (!ctrl->freq) { - debug("%s: no spi max frequency found\n", __func__); - continue; - } + struct tegra_spi_platdata *plat = dev_get_platdata(bus); + struct tegra114_spi_priv *priv = dev_get_priv(bus); - ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); - if (ctrl->periph_id == PERIPH_ID_NONE) { - debug("%s: could not decode periph id\n", __func__); - continue; - } - ctrl->valid = 1; - found = 1; + priv->regs = (struct spi_regs *)plat->base; - debug("%s: found controller at %p, freq = %u, periph_id = %d\n", - __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); - } + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; - return !found; + return 0; } -int tegra114_spi_claim_bus(struct spi_slave *slave) +static int tegra114_spi_claim_bus(struct udevice *bus) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct tegra114_spi_priv *priv = dev_get_priv(bus); + struct spi_regs *regs = priv->regs; /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, - spi->ctrl->freq); + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); /* Clear stale status here */ setbits_le32(®s->fifo_status, @@ -244,33 +176,64 @@ int tegra114_spi_claim_bus(struct spi_slave *slave) /* Set master mode and sw controlled CS */ setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | - (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT)); + (priv->mode << SPI_CMD1_MODE_SHIFT)); debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); return 0; } -void tegra114_spi_cs_activate(struct spi_slave *slave) +/** + * Activate the CS by driving it LOW + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_activate(struct udevice *dev) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra114_spi_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } - clrbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL); + clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); } -void tegra114_spi_cs_deactivate(struct spi_slave *slave) +/** + * Deactivate the CS by driving it HIGH + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_deactivate(struct udevice *dev) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra114_spi_priv *priv = dev_get_priv(bus); + + setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); - setbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL); + /* Remember time of this transaction so we can honour the bus delay */ + if (pdata->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); + + debug("Deactivate CS, bus '%s'\n", bus->name); } -int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags) +static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *data_out, void *data_in, + unsigned long flags) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra114_spi_priv *priv = dev_get_priv(bus); + struct spi_regs *regs = priv->regs; u32 reg, tmpdout, tmpdin = 0; const u8 *dout = data_out; u8 *din = data_in; @@ -278,7 +241,7 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, int ret; debug("%s: slave %u:%u dout %p din %p bitlen %u\n", - __func__, slave->bus, slave->cs, dout, din, bitlen); + __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); if (bitlen % 8) return -1; num_bytes = bitlen / 8; @@ -289,23 +252,19 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, reg = readl(®s->fifo_status); writel(reg, ®s->fifo_status); - /* clear ready bit */ - setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); - clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | - (slave->cs << SPI_CMD1_CS_SEL_SHIFT)); + (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT)); /* set xfer size to 1 block (32 bits) */ writel(0, ®s->dma_blk); if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + spi_cs_activate(dev); /* handle data in 32-bit chunks */ while (num_bytes > 0) { int bytes; - int is_read = 0; int tm, i; tmpdout = 0; @@ -319,6 +278,9 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, num_bytes -= bytes; + /* clear ready bit */ + setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); + clrsetbits_le32(®s->command1, SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); @@ -329,20 +291,14 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, * Wait for SPI transmit FIFO to empty, or to time out. * The RX FIFO status will be read and cleared last */ - for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { + for (tm = 0; tm < SPI_TIMEOUT; ++tm) { u32 fifo_status, xfer_status; - fifo_status = readl(®s->fifo_status); - - /* We can exit when we've had both RX and TX activity */ - if (is_read && - (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)) - break; - xfer_status = readl(®s->xfer_status); if (!(xfer_status & SPI_XFER_STS_RDY)) continue; + fifo_status = readl(®s->fifo_status); if (fifo_status & SPI_FIFO_STS_ERR) { debug("%s: got a fifo error: ", __func__); if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) @@ -367,7 +323,6 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { tmpdin = readl(®s->rx_fifo); - is_read = 1; /* swap bytes read in */ if (din != NULL) { @@ -377,6 +332,9 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, } din += bytes; } + + /* We can exit when we've had both RX and TX */ + break; } } @@ -388,7 +346,7 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, } if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + spi_cs_deactivate(dev); debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", __func__, tmpdin, readl(®s->fifo_status)); @@ -399,5 +357,55 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, return -1; } + return ret; +} + +static int tegra114_spi_set_speed(struct udevice *bus, uint speed) +{ + struct tegra_spi_platdata *plat = bus->platdata; + struct tegra114_spi_priv *priv = dev_get_priv(bus); + + if (speed > plat->frequency) + speed = plat->frequency; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} + +static int tegra114_spi_set_mode(struct udevice *bus, uint mode) +{ + struct tegra114_spi_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + return 0; } + +static const struct dm_spi_ops tegra114_spi_ops = { + .claim_bus = tegra114_spi_claim_bus, + .xfer = tegra114_spi_xfer, + .set_speed = tegra114_spi_set_speed, + .set_mode = tegra114_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id tegra114_spi_ids[] = { + { .compatible = "nvidia,tegra114-spi" }, + { } +}; + +U_BOOT_DRIVER(tegra114_spi) = { + .name = "tegra114_spi", + .id = UCLASS_SPI, + .of_match = tegra114_spi_ids, + .ops = &tegra114_spi_ops, + .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), + .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv), + .probe = tegra114_spi_probe, +}; diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 603c024bcc..78c74cdf37 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -7,15 +7,16 @@ */ #include -#include +#include +#include #include #include #include #include #include -#include #include #include +#include "tegra_spi.h" DECLARE_GLOBAL_DATA_PTR; @@ -64,129 +65,75 @@ struct spi_regs { u32 rx_fifo; /* SPI_RX_FIFO_0 register */ }; -struct tegra_spi_ctrl { +struct tegra20_sflash_priv { struct spi_regs *regs; unsigned int freq; unsigned int mode; int periph_id; int valid; + int last_transaction_us; }; -struct tegra_spi_slave { - struct spi_slave slave; - struct tegra_spi_ctrl *ctrl; -}; - -/* tegra20 only supports one SFLASH controller */ -static struct tegra_spi_ctrl spi_ctrls[1]; - -static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) -{ - return container_of(slave, struct tegra_spi_slave, slave); -} - -int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs) +int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs, + struct spi_cs_info *info) { /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ - if (bus != 0 || cs != 0) - return 0; + if (cs != 0) + return -ENODEV; else - return 1; + return 0; } -struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus) { - struct tegra_spi_slave *spi; + struct tegra_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; - if (!spi_cs_is_valid(bus, cs)) { - printf("SPI error: unsupported bus %d / chip select %d\n", - bus, cs); - return NULL; - } + plat->base = fdtdec_get_addr(blob, node, "reg"); + plat->periph_id = clock_decode_periph_id(blob, node); - if (max_hz > TEGRA_SPI_MAX_FREQ) { - printf("SPI error: unsupported frequency %d Hz. Max frequency" - " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); - return NULL; + if (plat->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id %d\n", __func__, + plat->periph_id); + return -FDT_ERR_NOTFOUND; } - spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs); - if (!spi) { - printf("SPI error: malloc of SPI structure failed\n"); - return NULL; - } - spi->ctrl = &spi_ctrls[bus]; - if (!spi->ctrl) { - printf("SPI error: could not find controller for bus %d\n", - bus); - return NULL; - } + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->base, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); - if (max_hz < spi->ctrl->freq) { - debug("%s: limiting frequency from %u to %u\n", __func__, - spi->ctrl->freq, max_hz); - spi->ctrl->freq = max_hz; - } - spi->ctrl->mode = mode; - - return &spi->slave; + return 0; } -void tegra20_spi_free_slave(struct spi_slave *slave) +static int tegra20_sflash_probe(struct udevice *bus) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - - free(spi); -} + struct tegra_spi_platdata *plat = dev_get_platdata(bus); + struct tegra20_sflash_priv *priv = dev_get_priv(bus); -int tegra20_spi_init(int *node_list, int count) -{ - struct tegra_spi_ctrl *ctrl; - int i; - int node = 0; - int found = 0; - - for (i = 0; i < count; i++) { - ctrl = &spi_ctrls[i]; - node = node_list[i]; - - ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, - node, "reg"); - if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { - debug("%s: no slink register found\n", __func__); - continue; - } - ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, - "spi-max-frequency", 0); - if (!ctrl->freq) { - debug("%s: no slink max frequency found\n", __func__); - continue; - } + priv->regs = (struct spi_regs *)plat->base; - ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); - if (ctrl->periph_id == PERIPH_ID_NONE) { - debug("%s: could not decode periph id\n", __func__); - continue; - } - ctrl->valid = 1; - found = 1; + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; - debug("%s: found controller at %p, freq = %u, periph_id = %d\n", - __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); - } - return !found; + return 0; } -int tegra20_spi_claim_bus(struct spi_slave *slave) +static int tegra20_sflash_claim_bus(struct udevice *bus) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct tegra20_sflash_priv *priv = dev_get_priv(bus); + struct spi_regs *regs = priv->regs; u32 reg; /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, - spi->ctrl->freq); + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, + priv->freq); /* Clear stale status here */ reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ @@ -197,8 +144,8 @@ int tegra20_spi_claim_bus(struct spi_slave *slave) /* * Use sw-controlled CS, so we can clock in data after ReadID, etc. */ - reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; - if (spi->ctrl->mode & 2) + reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; + if (priv->mode & 2) reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); @@ -208,44 +155,61 @@ int tegra20_spi_claim_bus(struct spi_slave *slave) * SPI pins on Tegra20 are muxed - change pinmux later due to UART * issue. */ - pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); - pinmux_tristate_disable(PINGRP_LSPI); - pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); + pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH); + pinmux_tristate_disable(PMUX_PINGRP_LSPI); + pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH); return 0; } -void tegra20_spi_cs_activate(struct spi_slave *slave) +static void spi_cs_activate(struct udevice *dev) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra20_sflash_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } /* CS is negated on Tegra, so drive a 1 to get a 0 */ - setbits_le32(®s->command, SPI_CMD_CS_VAL); + setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL); } -void tegra20_spi_cs_deactivate(struct spi_slave *slave) +static void spi_cs_deactivate(struct udevice *dev) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra20_sflash_priv *priv = dev_get_priv(bus); /* CS is negated on Tegra, so drive a 0 to get a 1 */ - clrbits_le32(®s->command, SPI_CMD_CS_VAL); + clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL); + + /* Remember time of this transaction so we can honour the bus delay */ + if (pdata->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); } -int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags) +static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen, + const void *data_out, void *data_in, + unsigned long flags) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra20_sflash_priv *priv = dev_get_priv(bus); + struct spi_regs *regs = priv->regs; u32 reg, tmpdout, tmpdin = 0; const u8 *dout = data_out; u8 *din = data_in; int num_bytes; int ret; - debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", - slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen); + debug("%s: slave %u:%u dout %p din %p bitlen %u\n", + __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); if (bitlen % 8) return -1; num_bytes = bitlen / 8; @@ -262,7 +226,7 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + spi_cs_activate(dev); /* handle data in 32-bit chunks */ while (num_bytes > 0) { @@ -327,7 +291,7 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, } if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + spi_cs_deactivate(dev); debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", tmpdin, readl(®s->status)); @@ -339,3 +303,50 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, return 0; } + +static int tegra20_sflash_set_speed(struct udevice *bus, uint speed) +{ + struct tegra_spi_platdata *plat = bus->platdata; + struct tegra20_sflash_priv *priv = dev_get_priv(bus); + + if (speed > plat->frequency) + speed = plat->frequency; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} + +static int tegra20_sflash_set_mode(struct udevice *bus, uint mode) +{ + struct tegra20_sflash_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops tegra20_sflash_ops = { + .claim_bus = tegra20_sflash_claim_bus, + .xfer = tegra20_sflash_xfer, + .set_speed = tegra20_sflash_set_speed, + .set_mode = tegra20_sflash_set_mode, + .cs_info = tegra20_sflash_cs_info, +}; + +static const struct udevice_id tegra20_sflash_ids[] = { + { .compatible = "nvidia,tegra20-sflash" }, + { } +}; + +U_BOOT_DRIVER(tegra20_sflash) = { + .name = "tegra20_sflash", + .id = UCLASS_SPI, + .of_match = tegra20_sflash_ids, + .ops = &tegra20_sflash_ops, + .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), + .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv), + .probe = tegra20_sflash_probe, +}; diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index 664de6e916..597d6ad5cc 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -22,14 +22,13 @@ */ #include -#include +#include #include -#include #include #include -#include #include #include +#include "tegra_spi.h" DECLARE_GLOBAL_DATA_PTR; @@ -87,130 +86,70 @@ struct spi_regs { u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */ }; -struct tegra_spi_ctrl { +struct tegra30_spi_priv { struct spi_regs *regs; unsigned int freq; unsigned int mode; int periph_id; int valid; + int last_transaction_us; }; struct tegra_spi_slave { struct spi_slave slave; - struct tegra_spi_ctrl *ctrl; + struct tegra30_spi_priv *ctrl; }; -static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS]; - -static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) -{ - return container_of(slave, struct tegra_spi_slave, slave); -} - -int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs) +static int tegra30_spi_ofdata_to_platdata(struct udevice *bus) { - if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid) - return 0; - else - return 1; -} + struct tegra_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; -struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct tegra_spi_slave *spi; + plat->base = fdtdec_get_addr(blob, node, "reg"); + plat->periph_id = clock_decode_periph_id(blob, node); - debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__, - bus, cs, max_hz, mode); - - if (!spi_cs_is_valid(bus, cs)) { - printf("SPI error: unsupported bus %d / chip select %d\n", - bus, cs); - return NULL; - } - - if (max_hz > TEGRA_SPI_MAX_FREQ) { - printf("SPI error: unsupported frequency %d Hz. Max frequency" - " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); - return NULL; + if (plat->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id %d\n", __func__, + plat->periph_id); + return -FDT_ERR_NOTFOUND; } - spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs); - if (!spi) { - printf("SPI error: malloc of SPI structure failed\n"); - return NULL; - } - spi->ctrl = &spi_ctrls[bus]; - if (!spi->ctrl) { - printf("SPI error: could not find controller for bus %d\n", - bus); - return NULL; - } + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->base, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); - if (max_hz < spi->ctrl->freq) { - debug("%s: limiting frequency from %u to %u\n", __func__, - spi->ctrl->freq, max_hz); - spi->ctrl->freq = max_hz; - } - spi->ctrl->mode = mode; - - return &spi->slave; + return 0; } -void tegra30_spi_free_slave(struct spi_slave *slave) +static int tegra30_spi_probe(struct udevice *bus) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - - free(spi); -} + struct tegra_spi_platdata *plat = dev_get_platdata(bus); + struct tegra30_spi_priv *priv = dev_get_priv(bus); -int tegra30_spi_init(int *node_list, int count) -{ - struct tegra_spi_ctrl *ctrl; - int i; - int node = 0; - int found = 0; - - for (i = 0; i < count; i++) { - ctrl = &spi_ctrls[i]; - node = node_list[i]; - - ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, - node, "reg"); - if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { - debug("%s: no slink register found\n", __func__); - continue; - } - ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, - "spi-max-frequency", 0); - if (!ctrl->freq) { - debug("%s: no slink max frequency found\n", __func__); - continue; - } + priv->regs = (struct spi_regs *)plat->base; - ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); - if (ctrl->periph_id == PERIPH_ID_NONE) { - debug("%s: could not decode periph id\n", __func__); - continue; - } - ctrl->valid = 1; - found = 1; + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; - debug("%s: found controller at %p, freq = %u, periph_id = %d\n", - __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); - } - return !found; + return 0; } -int tegra30_spi_claim_bus(struct spi_slave *slave) +static int tegra30_spi_claim_bus(struct udevice *bus) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct tegra30_spi_priv *priv = dev_get_priv(bus); + struct spi_regs *regs = priv->regs; u32 reg; /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, - spi->ctrl->freq); + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, + priv->freq); /* Clear stale status here */ reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \ @@ -227,29 +166,46 @@ int tegra30_spi_claim_bus(struct spi_slave *slave) return 0; } -void tegra30_spi_cs_activate(struct spi_slave *slave) +static void spi_cs_activate(struct udevice *dev) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra30_spi_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } /* CS is negated on Tegra, so drive a 1 to get a 0 */ - setbits_le32(®s->command, SLINK_CMD_CS_VAL); + setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); } -void tegra30_spi_cs_deactivate(struct spi_slave *slave) +static void spi_cs_deactivate(struct udevice *dev) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra30_spi_priv *priv = dev_get_priv(bus); /* CS is negated on Tegra, so drive a 0 to get a 1 */ - clrbits_le32(®s->command, SLINK_CMD_CS_VAL); + clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL); + + /* Remember time of this transaction so we can honour the bus delay */ + if (pdata->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); } -int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags) +static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *data_out, void *data_in, + unsigned long flags) { - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_regs *regs = spi->ctrl->regs; + struct udevice *bus = dev->parent; + struct tegra30_spi_priv *priv = dev_get_priv(bus); + struct spi_regs *regs = priv->regs; u32 reg, tmpdout, tmpdin = 0; const u8 *dout = data_out; u8 *din = data_in; @@ -257,7 +213,7 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, int ret; debug("%s: slave %u:%u dout %p din %p bitlen %u\n", - __func__, slave->bus, slave->cs, dout, din, bitlen); + __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); if (bitlen % 8) return -1; num_bytes = bitlen / 8; @@ -276,11 +232,11 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK, SLINK_CMD2_TXEN | SLINK_CMD2_RXEN | - (slave->cs << SLINK_CMD2_SS_EN_SHIFT)); + (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT)); debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2)); if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + spi_cs_activate(dev); /* handle data in 32-bit chunks */ while (num_bytes > 0) { @@ -344,7 +300,7 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, } if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + spi_cs_deactivate(dev); debug("%s: transfer ended. Value=%08x, status = %08x\n", __func__, tmpdin, readl(®s->status)); @@ -357,3 +313,53 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, return 0; } + +static int tegra30_spi_set_speed(struct udevice *bus, uint speed) +{ + struct tegra_spi_platdata *plat = bus->platdata; + struct tegra30_spi_priv *priv = dev_get_priv(bus); + + if (speed > plat->frequency) + speed = plat->frequency; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} + +static int tegra30_spi_set_mode(struct udevice *bus, uint mode) +{ + struct tegra30_spi_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops tegra30_spi_ops = { + .claim_bus = tegra30_spi_claim_bus, + .xfer = tegra30_spi_xfer, + .set_speed = tegra30_spi_set_speed, + .set_mode = tegra30_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id tegra30_spi_ids[] = { + { .compatible = "nvidia,tegra20-slink" }, + { } +}; + +U_BOOT_DRIVER(tegra30_spi) = { + .name = "tegra20_slink", + .id = UCLASS_SPI, + .of_match = tegra30_spi_ids, + .ops = &tegra30_spi_ops, + .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), + .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv), + .probe = tegra30_spi_probe, +}; diff --git a/drivers/spi/tegra_spi.h b/drivers/spi/tegra_spi.h new file mode 100644 index 0000000000..fb2b50f0bc --- /dev/null +++ b/drivers/spi/tegra_spi.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +struct tegra_spi_platdata { + enum periph_id periph_id; + int frequency; /* Default clock frequency, -1 for none */ + ulong base; + uint deactivate_delay_us; /* Delay to wait after deactivate */ +}; diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c new file mode 100644 index 0000000000..857b60455a --- /dev/null +++ b/drivers/spi/ti_qspi.c @@ -0,0 +1,342 @@ +/* + * TI QSPI driver + * + * Copyright (C) 2013, Texas Instruments, Incorporated + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +/* ti qpsi register bit masks */ +#define QSPI_TIMEOUT 2000000 +#define QSPI_FCLK 192000000 +/* clock control */ +#define QSPI_CLK_EN (1 << 31) +#define QSPI_CLK_DIV_MAX 0xffff +/* command */ +#define QSPI_EN_CS(n) (n << 28) +#define QSPI_WLEN(n) ((n-1) << 19) +#define QSPI_3_PIN (1 << 18) +#define QSPI_RD_SNGL (1 << 16) +#define QSPI_WR_SNGL (2 << 16) +#define QSPI_INVAL (4 << 16) +#define QSPI_RD_QUAD (7 << 16) +/* device control */ +#define QSPI_DD(m, n) (m << (3 + n*8)) +#define QSPI_CKPHA(n) (1 << (2 + n*8)) +#define QSPI_CSPOL(n) (1 << (1 + n*8)) +#define QSPI_CKPOL(n) (1 << (n*8)) +/* status */ +#define QSPI_WC (1 << 1) +#define QSPI_BUSY (1 << 0) +#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) +#define QSPI_XFER_DONE QSPI_WC +#define MM_SWITCH 0x01 +#define MEM_CS 0x100 +#define MEM_CS_UNSELECT 0xfffff0ff +#define MMAP_START_ADDR_DRA 0x5c000000 +#define MMAP_START_ADDR_AM43x 0x30000000 +#define CORE_CTRL_IO 0x4a002558 + +#define QSPI_CMD_READ (0x3 << 0) +#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_FAST (0x0b << 0) +#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) +#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) +#define QSPI_SETUP0_READ_NORMAL (0x0 << 12) +#define QSPI_SETUP0_READ_QUAD (0x3 << 12) +#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_NUM_DUMMY_BITS (0x0 << 24) + +/* ti qspi register set */ +struct ti_qspi_regs { + u32 pid; + u32 pad0[3]; + u32 sysconfig; + u32 pad1[3]; + u32 int_stat_raw; + u32 int_stat_en; + u32 int_en_set; + u32 int_en_ctlr; + u32 intc_eoi; + u32 pad2[3]; + u32 clk_ctrl; + u32 dc; + u32 cmd; + u32 status; + u32 data; + u32 setup0; + u32 setup1; + u32 setup2; + u32 setup3; + u32 memswitch; + u32 data1; + u32 data2; + u32 data3; +}; + +/* ti qspi slave */ +struct ti_qspi_slave { + struct spi_slave slave; + struct ti_qspi_regs *base; + unsigned int mode; + u32 cmd; + u32 dc; +}; + +static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct ti_qspi_slave, slave); +} + +static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) +{ + struct spi_slave *slave = &qslave->slave; + u32 memval = 0; + +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + slave->memory_map = (void *)MMAP_START_ADDR_DRA; +#else + slave->memory_map = (void *)MMAP_START_ADDR_AM43x; + slave->op_mode_rx = 8; +#endif + + memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_NO_BITS | + QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS; + + writel(memval, &qslave->base->setup0); +} + +static void ti_spi_set_speed(struct spi_slave *slave, uint hz) +{ + struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + uint clk_div; + + debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); + + if (!hz) + clk_div = 0; + else + clk_div = (QSPI_FCLK / hz) - 1; + + /* disable SCLK */ + writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN, + &qslave->base->clk_ctrl); + + /* assign clk_div values */ + if (clk_div < 0) + clk_div = 0; + else if (clk_div > QSPI_CLK_DIV_MAX) + clk_div = QSPI_CLK_DIV_MAX; + + /* enable SCLK */ + writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* CS handled in xfer */ + return; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + + debug("spi_cs_deactivate: 0x%08x\n", (u32)slave); + + writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ti_qspi_slave *qslave; + +#ifdef CONFIG_AM43XX + gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); + gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); +#endif + + qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); + if (!qslave) { + printf("SPI_error: Fail to allocate ti_qspi_slave\n"); + return NULL; + } + + qslave->base = (struct ti_qspi_regs *)QSPI_BASE; + qslave->mode = mode; + + ti_spi_set_speed(&qslave->slave, max_hz); + +#ifdef CONFIG_TI_SPI_MMAP + ti_spi_setup_spi_register(qslave); +#endif + + return &qslave->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + free(qslave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + + debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); + + qslave->dc = 0; + if (qslave->mode & SPI_CPHA) + qslave->dc |= QSPI_CKPHA(slave->cs); + if (qslave->mode & SPI_CPOL) + qslave->dc |= QSPI_CKPOL(slave->cs); + if (qslave->mode & SPI_CS_HIGH) + qslave->dc |= QSPI_CSPOL(slave->cs); + + writel(qslave->dc, &qslave->base->dc); + writel(0, &qslave->base->cmd); + writel(0, &qslave->base->data); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + + debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); + + writel(0, &qslave->base->dc); + writel(0, &qslave->base->cmd); + writel(0, &qslave->base->data); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + uint words = bitlen >> 3; /* fixed 8-bit word length */ + const uchar *txp = dout; + uchar *rxp = din; + uint status; + int timeout; + +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + int val; +#endif + + debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", + slave->bus, slave->cs, bitlen, words, flags); + + /* Setup mmap flags */ + if (flags & SPI_XFER_MMAP) { + writel(MM_SWITCH, &qslave->base->memswitch); +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + val = readl(CORE_CTRL_IO); + val |= MEM_CS; + writel(val, CORE_CTRL_IO); +#endif + return 0; + } else if (flags & SPI_XFER_MMAP_END) { + writel(~MM_SWITCH, &qslave->base->memswitch); +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + val = readl(CORE_CTRL_IO); + val &= MEM_CS_UNSELECT; + writel(val, CORE_CTRL_IO); +#endif + return 0; + } + + if (bitlen == 0) + return -1; + + if (bitlen % 8) { + debug("spi_xfer: Non byte aligned SPI transfer\n"); + return -1; + } + + /* Setup command reg */ + qslave->cmd = 0; + qslave->cmd |= QSPI_WLEN(8); + qslave->cmd |= QSPI_EN_CS(slave->cs); + if (flags & SPI_3WIRE) + qslave->cmd |= QSPI_3_PIN; + qslave->cmd |= 0xfff; + +/* FIXME: This delay is required for successfull + * completion of read/write/erase. Once its root + * caused, it will be remove from the driver. + */ +#ifdef CONFIG_AM43XX + udelay(100); +#endif + while (words--) { + if (txp) { + debug("tx cmd %08x dc %08x data %02x\n", + qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); + writel(*txp++, &qslave->base->data); + writel(qslave->cmd | QSPI_WR_SNGL, + &qslave->base->cmd); + status = readl(&qslave->base->status); + timeout = QSPI_TIMEOUT; + while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { + if (--timeout < 0) { + printf("spi_xfer: TX timeout!\n"); + return -1; + } + status = readl(&qslave->base->status); + } + debug("tx done, status %08x\n", status); + } + if (rxp) { + qslave->cmd |= QSPI_RD_SNGL; + debug("rx cmd %08x dc %08x\n", + qslave->cmd, qslave->dc); + #ifdef CONFIG_DRA7XX + udelay(500); + #endif + writel(qslave->cmd, &qslave->base->cmd); + status = readl(&qslave->base->status); + timeout = QSPI_TIMEOUT; + while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { + if (--timeout < 0) { + printf("spi_xfer: RX timeout!\n"); + return -1; + } + status = readl(&qslave->base->status); + } + *rxp++ = readl(&qslave->base->data); + debug("rx done, status %08x, read %02x\n", + status, *(rxp-1)); + } + } + + /* Terminate frame */ + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index a82b056948..56d99d17c7 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -9,7 +9,7 @@ * Copyright (c) 2010 Graeme Smecher * Copyright (c) 2012 Stephan Linz * - * Licensed under the GPL-2 or later. + * SPDX-License-Identifier: GPL-2.0+ * * [0]: http://www.xilinx.com/support/documentation * @@ -149,6 +149,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, const unsigned char *txp = dout; unsigned char *rxp = din; unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */ + unsigned global_timeout; debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, slave->bus, slave->cs, bitlen, bytes, flags); @@ -176,11 +177,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); - while (bytes--) { - unsigned timeout = /* at least 1usec or greater, leftover 1 */ - xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : + /* at least 1usec or greater, leftover 1 */ + global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1; + while (bytes--) { + unsigned timeout = global_timeout; /* get Tx element from data out buffer and count up */ unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; debug("%s: tx:%x ", __func__, d); diff --git a/drivers/spi/xilinx_spi.h b/drivers/spi/xilinx_spi.h index 69d0b94058..ce7d82c394 100644 --- a/drivers/spi/xilinx_spi.h +++ b/drivers/spi/xilinx_spi.h @@ -9,7 +9,7 @@ * Copyright (c) 2010 Graeme Smecher * Copyright (c) 2012 Stephan Linz * - * Licensed under the GPL-2 or later. + * SPDX-License-Identifier: GPL-2.0+ * * [0]: http://www.xilinx.com/support/documentation * diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c new file mode 100644 index 0000000000..5da87591ce --- /dev/null +++ b/drivers/spi/zynq_spi.c @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2013 Inc. + * + * Xilinx Zynq PS SPI controller driver (master mode only) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* zynq spi register bit masks ZYNQ_SPI___MASK */ +#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ +#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ +#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ +#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ +#define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ +#define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ +#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */ +#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */ +#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ + +#define ZYNQ_SPI_FIFO_DEPTH 128 +#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT +#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ +#endif + +/* zynq spi register set */ +struct zynq_spi_regs { + u32 cr; /* 0x00 */ + u32 isr; /* 0x04 */ + u32 ier; /* 0x08 */ + u32 idr; /* 0x0C */ + u32 imr; /* 0x10 */ + u32 enr; /* 0x14 */ + u32 dr; /* 0x18 */ + u32 txdr; /* 0x1C */ + u32 rxdr; /* 0x20 */ +}; + +/* zynq spi slave */ +struct zynq_spi_slave { + struct spi_slave slave; + struct zynq_spi_regs *base; + u8 mode; + u8 fifo_depth; + u32 speed_hz; + u32 input_hz; + u32 req_hz; +}; + +static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct zynq_spi_slave, slave); +} + +static inline struct zynq_spi_regs *get_zynq_spi_base(int dev) +{ + if (dev) + return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1; + else + return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0; +} + +static void zynq_spi_init_hw(struct zynq_spi_slave *zslave) +{ + u32 confr; + + /* Disable SPI */ + writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); + + /* Disable Interrupts */ + writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->idr); + + /* Clear RX FIFO */ + while (readl(&zslave->base->isr) & + ZYNQ_SPI_IXR_RXNEMPTY_MASK) + readl(&zslave->base->rxdr); + + /* Clear Interrupts */ + writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->isr); + + /* Manual slave select and Auto start */ + confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | + ZYNQ_SPI_CR_MSTREN_MASK; + confr &= ~ZYNQ_SPI_CR_MSA_MASK; + writel(confr, &zslave->base->cr); + + /* Enable SPI */ + writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* 2 bus with 3 chipselect */ + return bus < 2 && cs < 3; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + u32 cr; + + debug("spi_cs_activate: 0x%08x\n", (u32)slave); + + clrbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK); + cr = readl(&zslave->base->cr); + /* + * CS cal logic: CS[13:10] + * xxx0 - cs0 + * xx01 - cs1 + * x011 - cs2 + */ + cr |= (~(0x1 << slave->cs) << 10) & ZYNQ_SPI_CR_CS_MASK; + writel(cr, &zslave->base->cr); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + + debug("spi_cs_deactivate: 0x%08x\n", (u32)slave); + + setbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK); +} + +void spi_init() +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct zynq_spi_slave *zslave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + zslave = spi_alloc_slave(struct zynq_spi_slave, bus, cs); + if (!zslave) { + printf("SPI_error: Fail to allocate zynq_spi_slave\n"); + return NULL; + } + + zslave->base = get_zynq_spi_base(bus); + zslave->mode = mode; + zslave->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; + zslave->input_hz = 166666700; + zslave->speed_hz = zslave->input_hz / 2; + zslave->req_hz = max_hz; + + /* init the zynq spi hw */ + zynq_spi_init_hw(zslave); + + return &zslave->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + + debug("spi_free_slave: 0x%08x\n", (u32)slave); + free(zslave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + u32 confr = 0; + u8 baud_rate_val = 0; + + writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); + + /* Set the SPI Clock phase and polarities */ + confr = readl(&zslave->base->cr); + confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK); + if (zslave->mode & SPI_CPHA) + confr |= ZYNQ_SPI_CR_CPHA_MASK; + if (zslave->mode & SPI_CPOL) + confr |= ZYNQ_SPI_CR_CPOL_MASK; + + /* Set the clock frequency */ + if (zslave->req_hz == 0) { + /* Set baudrate x8, if the req_hz is 0 */ + baud_rate_val = 0x2; + } else if (zslave->speed_hz != zslave->req_hz) { + while ((baud_rate_val < 8) && + ((zslave->input_hz / + (2 << baud_rate_val)) > zslave->req_hz)) + baud_rate_val++; + zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val); + } + confr &= ~ZYNQ_SPI_CR_BRD_MASK; + confr |= (baud_rate_val << 3); + writel(confr, &zslave->base->cr); + + writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + + debug("spi_release_bus: 0x%08x\n", (u32)slave); + writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + u32 len = bitlen / 8; + u32 tx_len = len, rx_len = len, tx_tvl; + const u8 *tx_buf = dout; + u8 *rx_buf = din, buf; + u32 ts, status; + + debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", + slave->bus, slave->cs, bitlen, len, flags); + + if (bitlen == 0) + return -1; + + if (bitlen % 8) { + debug("spi_xfer: Non byte aligned SPI transfer\n"); + return -1; + } + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (rx_len > 0) { + /* Write the data into TX FIFO - tx threshold is fifo_depth */ + tx_tvl = 0; + while ((tx_tvl < zslave->fifo_depth) && tx_len) { + if (tx_buf) + buf = *tx_buf++; + else + buf = 0; + writel(buf, &zslave->base->txdr); + tx_len--; + tx_tvl++; + } + + /* Check TX FIFO completion */ + ts = get_timer(0); + status = readl(&zslave->base->isr); + while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { + if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { + printf("spi_xfer: Timeout! TX FIFO not full\n"); + return -1; + } + status = readl(&zslave->base->isr); + } + + /* Read the data from RX FIFO */ + status = readl(&zslave->base->isr); + while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) { + buf = readl(&zslave->base->rxdr); + if (rx_buf) + *rx_buf++ = buf; + status = readl(&zslave->base->isr); + rx_len--; + } + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile new file mode 100644 index 0000000000..6d4cacdcf7 --- /dev/null +++ b/drivers/thermal/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# Author: Nitin Garg +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o +obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c new file mode 100644 index 0000000000..0bd9cfd030 --- /dev/null +++ b/drivers/thermal/imx_thermal.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + * Author: Nitin Garg + * Ye Li + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 80 +#define TEMPERATURE_MAX 125 +#define FACTOR0 10000000 +#define FACTOR1 15976 +#define FACTOR2 4297157 +#define MEASURE_FREQ 327 + +#define TEMPSENSE0_TEMP_CNT_SHIFT 8 +#define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT) +#define TEMPSENSE0_FINISHED (1 << 2) +#define TEMPSENSE0_MEASURE_TEMP (1 << 1) +#define TEMPSENSE0_POWER_DOWN (1 << 0) +#define MISC0_REFTOP_SELBIASOFF (1 << 3) +#define TEMPSENSE1_MEASURE_FREQ 0xffff + +static int read_cpu_temperature(struct udevice *dev) +{ + int temperature; + unsigned int reg, n_meas; + const struct imx_thermal_plat *pdata = dev_get_platdata(dev); + struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs; + unsigned int *priv = dev_get_priv(dev); + u32 fuse = *priv; + int t1, n1; + u32 c1, c2; + u64 temp64; + + /* + * Sensor data layout: + * [31:20] - sensor value @ 25C + * We use universal formula now and only need sensor value @ 25C + * slope = 0.4297157 - (0.0015976 * 25C fuse) + */ + n1 = fuse >> 20; + t1 = 25; /* t1 always 25C */ + + /* + * Derived from linear interpolation: + * slope = 0.4297157 - (0.0015976 * 25C fuse) + * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0 + * (Nmeas - n1) / (Tmeas - t1) = slope + * We want to reduce this down to the minimum computation necessary + * for each temperature read. Also, we want Tmeas in millicelsius + * and we don't want to lose precision from integer division. So... + * Tmeas = (Nmeas - n1) / slope + t1 + * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1 + * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1 + * Let constant c1 = (-1000 / slope) + * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1 + * Let constant c2 = n1 *c1 + 1000 * t1 + * milli_Tmeas = c2 - Nmeas * c1 + */ + temp64 = FACTOR0; + temp64 *= 1000; + do_div(temp64, FACTOR1 * n1 - FACTOR2); + c1 = temp64; + c2 = n1 * c1 + 1000 * t1; + + /* + * now we only use single measure, every time we read + * the temperature, we will power on/down anadig thermal + * module + */ + writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr); + writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); + + /* setup measure freq */ + reg = readl(&anatop->tempsense1); + reg &= ~TEMPSENSE1_MEASURE_FREQ; + reg |= MEASURE_FREQ; + writel(reg, &anatop->tempsense1); + + /* start the measurement process */ + writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr); + writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); + writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set); + + /* make sure that the latest temp is valid */ + while ((readl(&anatop->tempsense0) & + TEMPSENSE0_FINISHED) == 0) + udelay(10000); + + /* read temperature count */ + reg = readl(&anatop->tempsense0); + n_meas = (reg & TEMPSENSE0_TEMP_CNT_MASK) + >> TEMPSENSE0_TEMP_CNT_SHIFT; + writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); + + /* milli_Tmeas = c2 - Nmeas * c1 */ + temperature = (c2 - n_meas * c1)/1000; + + /* power down anatop thermal sensor */ + writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); + writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr); + + return temperature; +} + +int imx_thermal_get_temp(struct udevice *dev, int *temp) +{ + int cpu_tmp = 0; + + cpu_tmp = read_cpu_temperature(dev); + while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) { + if (cpu_tmp >= TEMPERATURE_HOT) { + printf("CPU Temperature is %d C, too hot to boot, waiting...\n", + cpu_tmp); + udelay(5000000); + cpu_tmp = read_cpu_temperature(dev); + } else { + break; + } + } + + *temp = cpu_tmp; + + return 0; +} + +static const struct dm_thermal_ops imx_thermal_ops = { + .get_temp = imx_thermal_get_temp, +}; + +static int imx_thermal_probe(struct udevice *dev) +{ + unsigned int fuse = ~0; + + const struct imx_thermal_plat *pdata = dev_get_platdata(dev); + unsigned int *priv = dev_get_priv(dev); + + /* Read Temperature calibration data fuse */ + fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse); + + /* Check for valid fuse */ + if (fuse == 0 || fuse == ~0) { + printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse); + return -EPERM; + } + + *priv = fuse; + + enable_thermal_clk(); + + return 0; +} + +U_BOOT_DRIVER(imx_thermal) = { + .name = "imx_thermal", + .id = UCLASS_THERMAL, + .ops = &imx_thermal_ops, + .probe = imx_thermal_probe, + .priv_auto_alloc_size = sizeof(unsigned int), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/thermal/thermal-uclass.c b/drivers/thermal/thermal-uclass.c new file mode 100644 index 0000000000..3bee1a7dc7 --- /dev/null +++ b/drivers/thermal/thermal-uclass.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +int thermal_get_temp(struct udevice *dev, int *temp) +{ + const struct dm_thermal_ops *ops = device_get_ops(dev); + + if (!ops->get_temp) + return -ENOSYS; + + return ops->get_temp(dev, temp); +} + +UCLASS_DRIVER(thermal) = { + .id = UCLASS_THERMAL, + .name = "thermal", +}; diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index 4457a78f8e..150570ee7e 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -3,31 +3,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libtpm.o - -$(shell mkdir -p $(obj)slb9635_i2c) - # TODO: Merge tpm_tis_lpc.c with tpm.c -COBJS-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o -COBJS-$(CONFIG_TPM_TIS_I2C) += tpm.o -COBJS-$(CONFIG_TPM_TIS_I2C) += tpm_tis_i2c.o -COBJS-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o +obj-$(CONFIG_TPM_TIS_I2C) += tpm.o +obj-$(CONFIG_TPM_TIS_I2C) += tpm_tis_i2c.o +obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o +obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o diff --git a/drivers/tpm/tis_i2c.c b/drivers/tpm/tis_i2c.c deleted file mode 100644 index 22554e1456..0000000000 --- a/drivers/tpm/tis_i2c.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include -#include -#include "slb9635_i2c/tpm.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* TPM configuration */ -struct tpm { - int i2c_bus; - int slave_addr; - char inited; - int old_bus; -} tpm; - - -static int tpm_select(void) -{ - int ret; - - tpm.old_bus = i2c_get_bus_num(); - if (tpm.old_bus != tpm.i2c_bus) { - ret = i2c_set_bus_num(tpm.i2c_bus); - if (ret) { - debug("%s: Fail to set i2c bus %d\n", __func__, - tpm.i2c_bus); - return -1; - } - } - return 0; -} - -static int tpm_deselect(void) -{ - int ret; - - if (tpm.old_bus != i2c_get_bus_num()) { - ret = i2c_set_bus_num(tpm.old_bus); - if (ret) { - debug("%s: Fail to restore i2c bus %d\n", - __func__, tpm.old_bus); - return -1; - } - } - tpm.old_bus = -1; - return 0; -} - -/** - * Decode TPM configuration. - * - * @param dev Returns a configuration of TPM device - * @return 0 if ok, -1 on error - */ -static int tpm_decode_config(struct tpm *dev) -{ -#ifdef CONFIG_OF_CONTROL - const void *blob = gd->fdt_blob; - int node, parent; - int i2c_bus; - - node = fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM); - if (node < 0) { - node = fdtdec_next_compatible(blob, 0, - COMPAT_INFINEON_SLB9645_TPM); - } - if (node < 0) { - debug("%s: Node not found\n", __func__); - return -1; - } - parent = fdt_parent_offset(blob, node); - if (parent < 0) { - debug("%s: Cannot find node parent\n", __func__); - return -1; - } - i2c_bus = i2c_get_bus_num_fdt(parent); - if (i2c_bus < 0) - return -1; - dev->i2c_bus = i2c_bus; - dev->slave_addr = fdtdec_get_addr(blob, node, "reg"); -#else - dev->i2c_bus = CONFIG_INFINEON_TPM_I2C_BUS; - dev->slave_addr = CONFIG_INFINEON_TPM_I2C_ADDR; -#endif - return 0; -} - -int tis_init(void) -{ - if (tpm.inited) - return 0; - - if (tpm_decode_config(&tpm)) - return -1; - - if (tpm_select()) - return -1; - - /* - * Probe TPM twice; the first probing might fail because TPM is asleep, - * and the probing can wake up TPM. - */ - if (i2c_probe(tpm.slave_addr) && i2c_probe(tpm.slave_addr)) { - debug("%s: fail to probe i2c addr 0x%x\n", __func__, - tpm.slave_addr); - return -1; - } - - tpm_deselect(); - - tpm.inited = 1; - - return 0; -} - -int tis_open(void) -{ - int rc; - - if (!tpm.inited) - return -1; - - if (tpm_select()) - return -1; - - rc = tpm_open(tpm.slave_addr); - - tpm_deselect(); - - return rc; -} - -int tis_close(void) -{ - if (!tpm.inited) - return -1; - - if (tpm_select()) - return -1; - - tpm_close(); - - tpm_deselect(); - - return 0; -} - -int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, - uint8_t *recvbuf, size_t *rbuf_len) -{ - int len; - uint8_t buf[4096]; - - if (!tpm.inited) - return -1; - - if (sizeof(buf) < sbuf_size) - return -1; - - memcpy(buf, sendbuf, sbuf_size); - - if (tpm_select()) - return -1; - - len = tpm_transmit(buf, sbuf_size); - - tpm_deselect(); - - if (len < 10) { - *rbuf_len = 0; - return -1; - } - - memcpy(recvbuf, buf, len); - *rbuf_len = len; - - return 0; -} diff --git a/drivers/tpm/tpm.c b/drivers/tpm/tpm.c index b657334195..31761ec338 100644 --- a/drivers/tpm/tpm.c +++ b/drivers/tpm/tpm.c @@ -34,7 +34,7 @@ #include #include -#include +#include #include #include #include @@ -411,7 +411,7 @@ static ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz) goto out_recv; } - if ((status == chip->vendor.req_canceled)) { + if (status == chip->vendor.req_canceled) { error("Operation Canceled\n"); rc = -ECANCELED; goto out; diff --git a/drivers/tpm/tpm_tis_i2c.c b/drivers/tpm/tpm_tis_i2c.c index 2dd8501f92..c1bbed4eb5 100644 --- a/drivers/tpm/tpm_tis_i2c.c +++ b/drivers/tpm/tpm_tis_i2c.c @@ -38,7 +38,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c index eecf18cbf9..d09f8cee05 100644 --- a/drivers/tpm/tpm_tis_lpc.c +++ b/drivers/tpm/tpm_tis_lpc.c @@ -274,7 +274,7 @@ static u32 tis_senddata(const u8 * const data, u32 len) * changes to zero exactly after the last byte is fed into the * FIFO. */ - count = min(burst, len - offset - 1); + count = min((u32)burst, len - offset - 1); while (count--) tpm_write_byte(data[offset++], &lpc_tpm_dev[locality].data); diff --git a/drivers/tpm/tpm_tis_sandbox.c b/drivers/tpm/tpm_tis_sandbox.c new file mode 100644 index 0000000000..ed4b039127 --- /dev/null +++ b/drivers/tpm/tpm_tis_sandbox.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* TPM NVRAM location indices. */ +#define FIRMWARE_NV_INDEX 0x1007 +#define KERNEL_NV_INDEX 0x1008 + +#define NV_DATA_PUBLIC_PERMISSIONS_OFFSET 60 + +/* Kernel TPM space - KERNEL_NV_INDEX, locked with physical presence */ +#define ROLLBACK_SPACE_KERNEL_VERSION 2 +#define ROLLBACK_SPACE_KERNEL_UID 0x4752574C /* 'GRWL' */ + +struct rollback_space_kernel { + /* Struct version, for backwards compatibility */ + uint8_t struct_version; + /* Unique ID to detect space redefinition */ + uint32_t uid; + /* Kernel versions */ + uint32_t kernel_versions; + /* Reserved for future expansion */ + uint8_t reserved[3]; + /* Checksum (v2 and later only) */ + uint8_t crc8; +} __packed rollback_space_kernel; + +/* + * These numbers derive from adding the sizes of command fields as shown in + * the TPM commands manual. + */ +#define TPM_REQUEST_HEADER_LENGTH 10 +#define TPM_RESPONSE_HEADER_LENGTH 10 + +/* These are the different non-volatile spaces that we emulate */ +enum { + NV_GLOBAL_LOCK, + NV_SEQ_FIRMWARE, + NV_SEQ_KERNEL, + NV_SEQ_COUNT, +}; + +/* Size of each non-volatile space */ +#define NV_DATA_SIZE 0x20 + +/* + * Information about our TPM emulation. This is preserved in the sandbox + * state file if enabled. + */ +static struct tpm_state { + uint8_t nvdata[NV_SEQ_COUNT][NV_DATA_SIZE]; +} state; + +/** + * sandbox_tpm_read_state() - read the sandbox EC state from the state file + * + * If data is available, then blob and node will provide access to it. If + * not this function sets up an empty TPM. + * + * @blob: Pointer to device tree blob, or NULL if no data to read + * @node: Node offset to read from + */ +static int sandbox_tpm_read_state(const void *blob, int node) +{ + const char *prop; + int len; + int i; + + if (!blob) + return 0; + + for (i = 0; i < NV_SEQ_COUNT; i++) { + char prop_name[20]; + + sprintf(prop_name, "nvdata%d", i); + prop = fdt_getprop(blob, node, prop_name, &len); + if (prop && len == NV_DATA_SIZE) + memcpy(state.nvdata[i], prop, NV_DATA_SIZE); + } + + return 0; +} + +/** + * cros_ec_write_state() - Write out our state to the state file + * + * The caller will ensure that there is a node ready for the state. The node + * may already contain the old state, in which case it is overridden. + * + * @blob: Device tree blob holding state + * @node: Node to write our state into + */ +static int sandbox_tpm_write_state(void *blob, int node) +{ + int i; + + /* + * We are guaranteed enough space to write basic properties. + * We could use fdt_add_subnode() to put each set of data in its + * own node - perhaps useful if we add access informaiton to each. + */ + for (i = 0; i < NV_SEQ_COUNT; i++) { + char prop_name[20]; + + sprintf(prop_name, "nvdata%d", i); + fdt_setprop(blob, node, prop_name, state.nvdata[i], + NV_DATA_SIZE); + } + + return 0; +} + +SANDBOX_STATE_IO(sandbox_tpm, "google,sandbox-tpm", sandbox_tpm_read_state, + sandbox_tpm_write_state); + +static int index_to_seq(uint32_t index) +{ + switch (index) { + case FIRMWARE_NV_INDEX: + return NV_SEQ_FIRMWARE; + case KERNEL_NV_INDEX: + return NV_SEQ_KERNEL; + case 0: + return NV_GLOBAL_LOCK; + } + + printf("Invalid nv index %#x\n", index); + return -1; +} + +int tis_sendrecv(const u8 *sendbuf, size_t send_size, + u8 *recvbuf, size_t *recv_len) +{ + struct tpm_state *tpm = &state; + uint32_t code, index, length, type; + uint8_t *data; + int seq; + + code = get_unaligned_be32(sendbuf + sizeof(uint16_t) + + sizeof(uint32_t)); + printf("tpm: %zd bytes, recv_len %zd, cmd = %x\n", send_size, + *recv_len, code); + print_buffer(0, sendbuf, 1, send_size, 0); + switch (code) { + case 0x65: /* get flags */ + type = get_unaligned_be32(sendbuf + 14); + switch (type) { + case 4: + index = get_unaligned_be32(sendbuf + 18); + printf("Get flags index %#02x\n", index); + *recv_len = 22; + memset(recvbuf, '\0', *recv_len); + put_unaligned_be32(22, recvbuf + + TPM_RESPONSE_HEADER_LENGTH); + data = recvbuf + TPM_RESPONSE_HEADER_LENGTH + + sizeof(uint32_t); + switch (index) { + case FIRMWARE_NV_INDEX: + break; + case KERNEL_NV_INDEX: + /* TPM_NV_PER_PPWRITE */ + put_unaligned_be32(1, data + + NV_DATA_PUBLIC_PERMISSIONS_OFFSET); + break; + } + break; + case 0x11: /* TPM_CAP_NV_INDEX */ + index = get_unaligned_be32(sendbuf + 18); + printf("Get cap nv index %#02x\n", index); + put_unaligned_be32(22, recvbuf + + TPM_RESPONSE_HEADER_LENGTH); + break; + default: + printf(" ** Unknown 0x65 command type %#02x\n", + type); + return -1; + } + break; + case 0xcd: /* nvwrite */ + index = get_unaligned_be32(sendbuf + 10); + length = get_unaligned_be32(sendbuf + 18); + seq = index_to_seq(index); + if (seq < 0) + return -1; + printf("tpm: nvwrite index=%#02x, len=%#02x\n", index, length); + memcpy(&tpm->nvdata[seq], sendbuf + 22, length); + *recv_len = 12; + memset(recvbuf, '\0', *recv_len); + break; + case 0xcf: /* nvread */ + index = get_unaligned_be32(sendbuf + 10); + length = get_unaligned_be32(sendbuf + 18); + seq = index_to_seq(index); + if (seq < 0) + return -1; + printf("tpm: nvread index=%#02x, len=%#02x\n", index, length); + *recv_len = TPM_RESPONSE_HEADER_LENGTH + sizeof(uint32_t) + + length; + memset(recvbuf, '\0', *recv_len); + put_unaligned_be32(length, recvbuf + + TPM_RESPONSE_HEADER_LENGTH); + if (seq == NV_SEQ_KERNEL) { + struct rollback_space_kernel rsk; + + data = recvbuf + TPM_RESPONSE_HEADER_LENGTH + + sizeof(uint32_t); + rsk.struct_version = 2; + rsk.uid = ROLLBACK_SPACE_KERNEL_UID; + rsk.kernel_versions = 0; + rsk.crc8 = crc8((unsigned char *)&rsk, + offsetof(struct rollback_space_kernel, + crc8)); + memcpy(data, &rsk, sizeof(rsk)); + } else { + memcpy(recvbuf + TPM_RESPONSE_HEADER_LENGTH + + sizeof(uint32_t), &tpm->nvdata[seq], length); + } + break; + case 0x14: /* tpm extend */ + case 0x15: /* pcr read */ + case 0x5d: /* force clear */ + case 0x6f: /* physical enable */ + case 0x72: /* physical set deactivated */ + case 0x99: /* startup */ + case 0x4000000a: /* assert physical presence */ + *recv_len = 12; + memset(recvbuf, '\0', *recv_len); + break; + default: + printf("Unknown tpm command %02x\n", code); + return -1; + } + + return 0; +} + +int tis_open(void) +{ + printf("%s\n", __func__); + return 0; +} + +int tis_close(void) +{ + printf("%s\n", __func__); + return 0; +} + +int tis_init(void) +{ + printf("%s\n", __func__); + return 0; +} diff --git a/drivers/twserial/Makefile b/drivers/twserial/Makefile index ac2273556c..7cc7c4de82 100644 --- a/drivers/twserial/Makefile +++ b/drivers/twserial/Makefile @@ -5,26 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libtws.o - -COBJS-$(CONFIG_SOFT_TWS) += soft_tws.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_SOFT_TWS) += soft_tws.o diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig new file mode 100644 index 0000000000..b4a9442703 --- /dev/null +++ b/drivers/usb/Kconfig @@ -0,0 +1,46 @@ +config USB_ARCH_HAS_HCD + def_bool y + +config USB + bool "Support for Host-side USB" + depends on USB_ARCH_HAS_HCD + ---help--- + Universal Serial Bus (USB) is a specification for a serial bus + subsystem which offers higher speeds and more features than the + traditional PC serial port. The bus supplies power to peripherals + and allows for hot swapping. Up to 127 USB peripherals can be + connected to a single USB host in a tree structure. + + The USB host is the root of the tree, the peripherals are the + leaves and the inner nodes are special USB devices called hubs. + Most PCs now have USB host ports, used to connect peripherals + such as scanners, keyboards, mice, modems, cameras, disks, + flash memory, network links, and printers to the PC. + + Say Y here if your computer has a host-side USB port and you want + to use USB devices. You then need to say Y to at least one of the + Host Controller Driver (HCD) options below. Choose a USB 1.1 + controller, such as "UHCI HCD support" or "OHCI HCD support", + and "EHCI HCD (USB 2.0) support" except for older systems that + do not have USB 2.0 support. It doesn't normally hurt to select + them all if you are not certain. + + If your system has a device-side USB port, used in the peripheral + side of the USB protocol, see the "USB Gadget" framework instead. + + After choosing your HCD, then select drivers for the USB peripherals + you'll be using. You may want to check out the information provided + in and especially the links given in + . + +if USB + +source "drivers/usb/host/Kconfig" + +config USB_STORAGE + bool "USB Mass Storage support" + ---help--- + Say Y here if you want to connect USB mass storage devices to your + board's USB port. + +endif diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile index 04a8b58c89..c92d2b02d2 100644 --- a/drivers/usb/eth/Makefile +++ b/drivers/usb/eth/Makefile @@ -3,31 +3,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libusb_eth.o - # new USB host ethernet layer dependencies -COBJS-$(CONFIG_USB_HOST_ETHER) += usb_ether.o -ifdef CONFIG_USB_ETHER_ASIX -COBJS-y += asix.o -endif -COBJS-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o +obj-$(CONFIG_USB_ETHER_ASIX) += asix.o +obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o +obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o +obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index 659533a8d4..11811094ed 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -468,8 +468,6 @@ static int asix_send(struct eth_device *eth, void *packet, int length) memcpy(msg, &packet_len, sizeof(packet_len)); memcpy(msg + sizeof(packet_len), (void *)packet, length); - if (length & 1) - length++; err = usb_bulk_msg(dev->pusb_dev, usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), @@ -567,7 +565,7 @@ struct asix_dongle { int flags; }; -static const struct asix_dongle const asix_dongles[] = { +static const struct asix_dongle asix_dongles[] = { { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */ { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */ { 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */ @@ -582,6 +580,7 @@ static const struct asix_dongle const asix_dongles[] = { { 0x2001, 0x3c05, FLAG_TYPE_AX88772 }, /* ASIX 88772B */ { 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC }, + { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B }, { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ }; diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c new file mode 100644 index 0000000000..0ef85db7b5 --- /dev/null +++ b/drivers/usb/eth/asix88179.c @@ -0,0 +1,714 @@ +/* + * Copyright (c) 2014 Rene Griessl + * based on the U-Boot Asix driver as well as information + * from the Linux AX88179_178a driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "usb_ether.h" +#include +#include + +/* ASIX AX88179 based USB 3.0 Ethernet Devices */ +#define AX88179_PHY_ID 0x03 +#define AX_EEPROM_LEN 0x100 +#define AX88179_EEPROM_MAGIC 0x17900b95 +#define AX_MCAST_FLTSIZE 8 +#define AX_MAX_MCAST 64 +#define AX_INT_PPLS_LINK (1 << 16) +#define AX_RXHDR_L4_TYPE_MASK 0x1c +#define AX_RXHDR_L4_TYPE_UDP 4 +#define AX_RXHDR_L4_TYPE_TCP 16 +#define AX_RXHDR_L3CSUM_ERR 2 +#define AX_RXHDR_L4CSUM_ERR 1 +#define AX_RXHDR_CRC_ERR (1 << 29) +#define AX_RXHDR_DROP_ERR (1 << 31) +#define AX_ENDPOINT_INT 0x01 +#define AX_ENDPOINT_IN 0x02 +#define AX_ENDPOINT_OUT 0x03 +#define AX_ACCESS_MAC 0x01 +#define AX_ACCESS_PHY 0x02 +#define AX_ACCESS_EEPROM 0x04 +#define AX_ACCESS_EFUS 0x05 +#define AX_PAUSE_WATERLVL_HIGH 0x54 +#define AX_PAUSE_WATERLVL_LOW 0x55 + +#define PHYSICAL_LINK_STATUS 0x02 + #define AX_USB_SS (1 << 2) + #define AX_USB_HS (1 << 1) + +#define GENERAL_STATUS 0x03 + #define AX_SECLD (1 << 2) + +#define AX_SROM_ADDR 0x07 +#define AX_SROM_CMD 0x0a + #define EEP_RD (1 << 2) + #define EEP_BUSY (1 << 4) + +#define AX_SROM_DATA_LOW 0x08 +#define AX_SROM_DATA_HIGH 0x09 + +#define AX_RX_CTL 0x0b + #define AX_RX_CTL_DROPCRCERR (1 << 8) + #define AX_RX_CTL_IPE (1 << 9) + #define AX_RX_CTL_START (1 << 7) + #define AX_RX_CTL_AP (1 << 5) + #define AX_RX_CTL_AM (1 << 4) + #define AX_RX_CTL_AB (1 << 3) + #define AX_RX_CTL_AMALL (1 << 1) + #define AX_RX_CTL_PRO (1 << 0) + #define AX_RX_CTL_STOP 0 + +#define AX_NODE_ID 0x10 +#define AX_MULFLTARY 0x16 + +#define AX_MEDIUM_STATUS_MODE 0x22 + #define AX_MEDIUM_GIGAMODE (1 << 0) + #define AX_MEDIUM_FULL_DUPLEX (1 << 1) + #define AX_MEDIUM_EN_125MHZ (1 << 3) + #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4) + #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5) + #define AX_MEDIUM_RECEIVE_EN (1 << 8) + #define AX_MEDIUM_PS (1 << 9) + #define AX_MEDIUM_JUMBO_EN 0x8040 + +#define AX_MONITOR_MOD 0x24 + #define AX_MONITOR_MODE_RWLC (1 << 1) + #define AX_MONITOR_MODE_RWMP (1 << 2) + #define AX_MONITOR_MODE_PMEPOL (1 << 5) + #define AX_MONITOR_MODE_PMETYPE (1 << 6) + +#define AX_GPIO_CTRL 0x25 + #define AX_GPIO_CTRL_GPIO3EN (1 << 7) + #define AX_GPIO_CTRL_GPIO2EN (1 << 6) + #define AX_GPIO_CTRL_GPIO1EN (1 << 5) + +#define AX_PHYPWR_RSTCTL 0x26 + #define AX_PHYPWR_RSTCTL_BZ (1 << 4) + #define AX_PHYPWR_RSTCTL_IPRL (1 << 5) + #define AX_PHYPWR_RSTCTL_AT (1 << 12) + +#define AX_RX_BULKIN_QCTRL 0x2e +#define AX_CLK_SELECT 0x33 + #define AX_CLK_SELECT_BCS (1 << 0) + #define AX_CLK_SELECT_ACS (1 << 1) + #define AX_CLK_SELECT_ULR (1 << 3) + +#define AX_RXCOE_CTL 0x34 + #define AX_RXCOE_IP (1 << 0) + #define AX_RXCOE_TCP (1 << 1) + #define AX_RXCOE_UDP (1 << 2) + #define AX_RXCOE_TCPV6 (1 << 5) + #define AX_RXCOE_UDPV6 (1 << 6) + +#define AX_TXCOE_CTL 0x35 + #define AX_TXCOE_IP (1 << 0) + #define AX_TXCOE_TCP (1 << 1) + #define AX_TXCOE_UDP (1 << 2) + #define AX_TXCOE_TCPV6 (1 << 5) + #define AX_TXCOE_UDPV6 (1 << 6) + +#define AX_LEDCTRL 0x73 + +#define GMII_PHY_PHYSR 0x11 + #define GMII_PHY_PHYSR_SMASK 0xc000 + #define GMII_PHY_PHYSR_GIGA (1 << 15) + #define GMII_PHY_PHYSR_100 (1 << 14) + #define GMII_PHY_PHYSR_FULL (1 << 13) + #define GMII_PHY_PHYSR_LINK (1 << 10) + +#define GMII_LED_ACT 0x1a + #define GMII_LED_ACTIVE_MASK 0xff8f + #define GMII_LED0_ACTIVE (1 << 4) + #define GMII_LED1_ACTIVE (1 << 5) + #define GMII_LED2_ACTIVE (1 << 6) + +#define GMII_LED_LINK 0x1c + #define GMII_LED_LINK_MASK 0xf888 + #define GMII_LED0_LINK_10 (1 << 0) + #define GMII_LED0_LINK_100 (1 << 1) + #define GMII_LED0_LINK_1000 (1 << 2) + #define GMII_LED1_LINK_10 (1 << 4) + #define GMII_LED1_LINK_100 (1 << 5) + #define GMII_LED1_LINK_1000 (1 << 6) + #define GMII_LED2_LINK_10 (1 << 8) + #define GMII_LED2_LINK_100 (1 << 9) + #define GMII_LED2_LINK_1000 (1 << 10) + #define LED0_ACTIVE (1 << 0) + #define LED0_LINK_10 (1 << 1) + #define LED0_LINK_100 (1 << 2) + #define LED0_LINK_1000 (1 << 3) + #define LED0_FD (1 << 4) + #define LED0_USB3_MASK 0x001f + #define LED1_ACTIVE (1 << 5) + #define LED1_LINK_10 (1 << 6) + #define LED1_LINK_100 (1 << 7) + #define LED1_LINK_1000 (1 << 8) + #define LED1_FD (1 << 9) + #define LED1_USB3_MASK 0x03e0 + #define LED2_ACTIVE (1 << 10) + #define LED2_LINK_1000 (1 << 13) + #define LED2_LINK_100 (1 << 12) + #define LED2_LINK_10 (1 << 11) + #define LED2_FD (1 << 14) + #define LED_VALID (1 << 15) + #define LED2_USB3_MASK 0x7c00 + +#define GMII_PHYPAGE 0x1e +#define GMII_PHY_PAGE_SELECT 0x1f + #define GMII_PHY_PGSEL_EXT 0x0007 + #define GMII_PHY_PGSEL_PAGE0 0x0000 + +/* local defines */ +#define ASIX_BASE_NAME "axg" +#define USB_CTRL_SET_TIMEOUT 5000 +#define USB_CTRL_GET_TIMEOUT 5000 +#define USB_BULK_SEND_TIMEOUT 5000 +#define USB_BULK_RECV_TIMEOUT 5000 + +#define AX_RX_URB_SIZE 1024 * 0x12 +#define BLK_FRAME_SIZE 0x200 +#define PHY_CONNECT_TIMEOUT 5000 + +#define TIMEOUT_RESOLUTION 50 /* ms */ + +#define FLAG_NONE 0 +#define FLAG_TYPE_AX88179 (1U << 0) +#define FLAG_TYPE_AX88178a (1U << 1) +#define FLAG_TYPE_DLINK_DUB1312 (1U << 2) +#define FLAG_TYPE_SITECOM (1U << 3) +#define FLAG_TYPE_SAMSUNG (1U << 4) +#define FLAG_TYPE_LENOVO (1U << 5) + +/* local vars */ +static const struct { + unsigned char ctrl, timer_l, timer_h, size, ifg; +} AX88179_BULKIN_SIZE[] = { + {7, 0x4f, 0, 0x02, 0xff}, + {7, 0x20, 3, 0x03, 0xff}, + {7, 0xae, 7, 0x04, 0xff}, + {7, 0xcc, 0x4c, 0x04, 8}, +}; + +static int curr_eth_dev; /* index for name of next device detected */ + +/* driver private */ +struct asix_private { + int flags; + int rx_urb_size; + int maxpacketsize; +}; + +/* + * Asix infrastructure commands + */ +static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, + u16 size, void *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); + + debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", + cmd, value, index, size); + + memcpy(buf, data, size); + + len = usb_control_msg( + dev->pusb_dev, + usb_sndctrlpipe(dev->pusb_dev, 0), + cmd, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + value, + index, + buf, + size, + USB_CTRL_SET_TIMEOUT); + + return len == size ? 0 : ECOMM; +} + +static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, + u16 size, void *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); + + debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", + cmd, value, index, size); + + len = usb_control_msg( + dev->pusb_dev, + usb_rcvctrlpipe(dev->pusb_dev, 0), + cmd, + USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + value, + index, + buf, + size, + USB_CTRL_GET_TIMEOUT); + + memcpy(data, buf, size); + + return len == size ? 0 : ECOMM; +} + +static int asix_read_mac(struct eth_device *eth) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + u8 buf[ETH_ALEN]; + + asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf); + debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + + memcpy(eth->enetaddr, buf, ETH_ALEN); + + return 0; +} + +static int asix_write_mac(struct eth_device *eth) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + int ret; + + ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, + ETH_ALEN, eth->enetaddr); + if (ret < 0) + debug("Failed to set MAC address: %02x\n", ret); + + return ret; +} + +static int asix_basic_reset(struct ueth_data *dev) +{ + struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; + u8 buf[5]; + u16 *tmp16; + u8 *tmp; + + tmp16 = (u16 *)buf; + tmp = (u8 *)buf; + + /* Power up ethernet PHY */ + *tmp16 = 0; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); + + *tmp16 = AX_PHYPWR_RSTCTL_IPRL; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); + mdelay(200); + + *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); + mdelay(200); + + /* RX bulk configuration */ + memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); + asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); + + dev_priv->rx_urb_size = 128 * 20; + + /* Water Level configuration */ + *tmp = 0x34; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); + + *tmp = 0x52; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp); + + /* Enable checksum offload */ + *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | + AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); + + *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | + AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); + + /* Configure RX control register => start operation */ + *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | + AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); + + *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | + AX_MONITOR_MODE_RWMP; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); + + /* Configure default medium type => giga */ + *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | + AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | + AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16); + + u16 adv = 0; + adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK | + ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; + asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv); + + adv = ADVERTISE_1000FULL; + asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); + + return 0; +} + +static int asix_wait_link(struct ueth_data *dev) +{ + int timeout = 0; + int link_detected; + u8 buf[2]; + u16 *tmp16; + + tmp16 = (u16 *)buf; + + do { + asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, + MII_BMSR, 2, buf); + link_detected = *tmp16 & BMSR_LSTATUS; + if (!link_detected) { + if (timeout == 0) + printf("Waiting for Ethernet connection... "); + mdelay(TIMEOUT_RESOLUTION); + timeout += TIMEOUT_RESOLUTION; + } + } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); + + if (link_detected) { + if (timeout > 0) + printf("done.\n"); + return 0; + } else { + printf("unable to connect.\n"); + return -ENETUNREACH; + } +} + +/* + * Asix callbacks + */ +static int asix_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; + u8 buf[2], tmp[5], link_sts; + u16 *tmp16, mode; + + + tmp16 = (u16 *)buf; + + debug("** %s()\n", __func__); + + /* Configure RX control register => start operation */ + *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | + AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; + if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0) + goto out_err; + + if (asix_wait_link(dev) != 0) { + /*reset device and try again*/ + printf("Reset Ethernet Device\n"); + asix_basic_reset(dev); + if (asix_wait_link(dev) != 0) + goto out_err; + } + + /* Configure link */ + mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | + AX_MEDIUM_RXFLOW_CTRLEN; + + asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, + 1, 1, &link_sts); + + asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, + GMII_PHY_PHYSR, 2, tmp16); + + if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) { + return 0; + } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { + mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ | + AX_MEDIUM_JUMBO_EN; + + if (link_sts & AX_USB_SS) + memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); + else if (link_sts & AX_USB_HS) + memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); + else + memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); + } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { + mode |= AX_MEDIUM_PS; + + if (link_sts & (AX_USB_SS | AX_USB_HS)) + memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); + else + memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); + } else { + memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); + } + + /* RX bulk configuration */ + asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); + + dev_priv->rx_urb_size = (1024 * (tmp[3] + 2)); + if (*tmp16 & GMII_PHY_PHYSR_FULL) + mode |= AX_MEDIUM_FULL_DUPLEX; + asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, + 2, 2, &mode); + + return 0; +out_err: + return -1; +} + +static int asix_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; + + int err; + u32 packet_len, tx_hdr2; + int actual_len, framesize; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, + PKTSIZE + (2 * sizeof(packet_len))); + + debug("** %s(), len %d\n", __func__, length); + + packet_len = length; + cpu_to_le32s(&packet_len); + + memcpy(msg, &packet_len, sizeof(packet_len)); + framesize = dev_priv->maxpacketsize; + tx_hdr2 = 0; + if (((length + 8) % framesize) == 0) + tx_hdr2 |= 0x80008000; /* Enable padding */ + + cpu_to_le32s(&tx_hdr2); + + memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2)); + + memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2), + (void *)packet, length); + + err = usb_bulk_msg(dev->pusb_dev, + usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), + (void *)msg, + length + sizeof(packet_len) + sizeof(tx_hdr2), + &actual_len, + USB_BULK_SEND_TIMEOUT); + debug("Tx: len = %u, actual = %u, err = %d\n", + length + sizeof(packet_len), actual_len, err); + + return err; +} + +static int asix_recv(struct eth_device *eth) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; + + u16 frame_pos; + int err; + int actual_len; + + int pkt_cnt; + u32 rx_hdr; + u16 hdr_off; + u32 *pkt_hdr; + ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size); + + actual_len = -1; + + debug("** %s()\n", __func__); + + err = usb_bulk_msg(dev->pusb_dev, + usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), + (void *)recv_buf, + dev_priv->rx_urb_size, + &actual_len, + USB_BULK_RECV_TIMEOUT); + debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size, + actual_len, err); + + if (err != 0) { + debug("Rx: failed to receive\n"); + return -ECOMM; + } + if (actual_len > dev_priv->rx_urb_size) { + debug("Rx: received too many bytes %d\n", actual_len); + return -EMSGSIZE; + } + + + rx_hdr = *(u32 *)(recv_buf + actual_len - 4); + le32_to_cpus(&pkt_hdr); + + pkt_cnt = (u16)rx_hdr; + hdr_off = (u16)(rx_hdr >> 16); + pkt_hdr = (u32 *)(recv_buf + hdr_off); + + + frame_pos = 0; + + while (pkt_cnt--) { + u16 pkt_len; + + le32_to_cpus(pkt_hdr); + pkt_len = (*pkt_hdr >> 16) & 0x1fff; + + frame_pos += 2; + + NetReceive(recv_buf + frame_pos, pkt_len); + + pkt_hdr++; + frame_pos += ((pkt_len + 7) & 0xFFF8)-2; + + if (pkt_cnt == 0) + return 0; + } + return err; +} + +static void asix_halt(struct eth_device *eth) +{ + debug("** %s()\n", __func__); +} + +/* + * Asix probing functions + */ +void ax88179_eth_before_probe(void) +{ + curr_eth_dev = 0; +} + +struct asix_dongle { + unsigned short vendor; + unsigned short product; + int flags; +}; + +static const struct asix_dongle asix_dongles[] = { + { 0x0b95, 0x1790, FLAG_TYPE_AX88179 }, + { 0x0b95, 0x178a, FLAG_TYPE_AX88178a }, + { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 }, + { 0x0df6, 0x0072, FLAG_TYPE_SITECOM }, + { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG }, + { 0x17ef, 0x304b, FLAG_TYPE_LENOVO }, + { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ +}; + +/* Probe to see if a new device is actually an asix device */ +int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss) +{ + struct usb_interface *iface; + struct usb_interface_descriptor *iface_desc; + struct asix_private *dev_priv; + int ep_in_found = 0, ep_out_found = 0; + int i; + + /* let's examine the device now */ + iface = &dev->config.if_desc[ifnum]; + iface_desc = &dev->config.if_desc[ifnum].desc; + + for (i = 0; asix_dongles[i].vendor != 0; i++) { + if (dev->descriptor.idVendor == asix_dongles[i].vendor && + dev->descriptor.idProduct == asix_dongles[i].product) + /* Found a supported dongle */ + break; + } + + if (asix_dongles[i].vendor == 0) + return 0; + + memset(ss, 0, sizeof(struct ueth_data)); + + /* At this point, we know we've got a live one */ + debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", + dev->descriptor.idVendor, dev->descriptor.idProduct); + + /* Initialize the ueth_data structure with some useful info */ + ss->ifnum = ifnum; + ss->pusb_dev = dev; + ss->subclass = iface_desc->bInterfaceSubClass; + ss->protocol = iface_desc->bInterfaceProtocol; + + /* alloc driver private */ + ss->dev_priv = calloc(1, sizeof(struct asix_private)); + if (!ss->dev_priv) + return 0; + dev_priv = ss->dev_priv; + dev_priv->flags = asix_dongles[i].flags; + + /* + * We are expecting a minimum of 3 endpoints - in, out (bulk), and + * int. We will ignore any others. + */ + for (i = 0; i < iface_desc->bNumEndpoints; i++) { + /* is it an interrupt endpoint? */ + if ((iface->ep_desc[i].bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { + ss->ep_int = iface->ep_desc[i].bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + ss->irqinterval = iface->ep_desc[i].bInterval; + continue; + } + + /* is it an BULK endpoint? */ + if (!((iface->ep_desc[i].bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) + continue; + + u8 ep_addr = iface->ep_desc[i].bEndpointAddress; + if ((ep_addr & USB_DIR_IN) && !ep_in_found) { + ss->ep_in = ep_addr & + USB_ENDPOINT_NUMBER_MASK; + ep_in_found = 1; + } + if (!(ep_addr & USB_DIR_IN) && !ep_out_found) { + ss->ep_out = ep_addr & + USB_ENDPOINT_NUMBER_MASK; + dev_priv->maxpacketsize = + dev->epmaxpacketout[AX_ENDPOINT_OUT]; + ep_out_found = 1; + } + } + debug("Endpoints In %d Out %d Int %d\n", + ss->ep_in, ss->ep_out, ss->ep_int); + + /* Do some basic sanity checks, and bail if we find a problem */ + if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || + !ss->ep_in || !ss->ep_out || !ss->ep_int) { + debug("Problems with device\n"); + return 0; + } + dev->privptr = (void *)ss; + return 1; +} + +int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth) +{ + if (!eth) { + debug("%s: missing parameter.\n", __func__); + return 0; + } + sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); + eth->init = asix_init; + eth->send = asix_send; + eth->recv = asix_recv; + eth->halt = asix_halt; + eth->write_hwaddr = asix_write_mac; + eth->priv = ss; + + if (asix_basic_reset(ss)) + return 0; + + /* Get the MAC address */ + if (asix_read_mac(eth)) + return 0; + debug("MAC %pM\n", eth->enetaddr); + + return 1; +} diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c new file mode 100644 index 0000000000..8e738d40e3 --- /dev/null +++ b/drivers/usb/eth/mcs7830.c @@ -0,0 +1,812 @@ +/* + * Copyright (c) 2013 Gerhard Sittig + * based on the U-Boot Asix driver as well as information + * from the Linux Moschip driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices + */ + +#include +#include +#include +#include +#include + +#include "usb_ether.h" + +#define MCS7830_BASE_NAME "mcs" + +#define USBCALL_TIMEOUT 1000 +#define LINKSTATUS_TIMEOUT 5000 /* link status, connect timeout */ +#define LINKSTATUS_TIMEOUT_RES 50 /* link status, resolution in msec */ + +#define MCS7830_RX_URB_SIZE 2048 + +/* command opcodes */ +#define MCS7830_WR_BREQ 0x0d +#define MCS7830_RD_BREQ 0x0e + +/* register layout, numerical offset specs for USB API calls */ +struct mcs7830_regs { + uint8_t multicast_hashes[8]; + uint8_t packet_gap[2]; + uint8_t phy_data[2]; + uint8_t phy_command[2]; + uint8_t configuration; + uint8_t ether_address[6]; + uint8_t frame_drop_count; + uint8_t pause_threshold; +}; +#define REG_MULTICAST_HASH offsetof(struct mcs7830_regs, multicast_hashes) +#define REG_PHY_DATA offsetof(struct mcs7830_regs, phy_data) +#define REG_PHY_CMD offsetof(struct mcs7830_regs, phy_command) +#define REG_CONFIG offsetof(struct mcs7830_regs, configuration) +#define REG_ETHER_ADDR offsetof(struct mcs7830_regs, ether_address) +#define REG_FRAME_DROP_COUNTER offsetof(struct mcs7830_regs, frame_drop_count) +#define REG_PAUSE_THRESHOLD offsetof(struct mcs7830_regs, pause_threshold) + +/* bit masks and default values for the above registers */ +#define PHY_CMD1_READ 0x40 +#define PHY_CMD1_WRITE 0x20 +#define PHY_CMD1_PHYADDR 0x01 + +#define PHY_CMD2_PEND 0x80 +#define PHY_CMD2_READY 0x40 + +#define CONF_CFG 0x80 +#define CONF_SPEED100 0x40 +#define CONF_FDX_ENABLE 0x20 +#define CONF_RXENABLE 0x10 +#define CONF_TXENABLE 0x08 +#define CONF_SLEEPMODE 0x04 +#define CONF_ALLMULTICAST 0x02 +#define CONF_PROMISCUOUS 0x01 + +#define PAUSE_THRESHOLD_DEFAULT 0 + +/* bit masks for the status byte which follows received ethernet frames */ +#define STAT_RX_FRAME_CORRECT 0x20 +#define STAT_RX_LARGE_FRAME 0x10 +#define STAT_RX_CRC_ERROR 0x08 +#define STAT_RX_ALIGNMENT_ERROR 0x04 +#define STAT_RX_LENGTH_ERROR 0x02 +#define STAT_RX_SHORT_FRAME 0x01 + +/* + * struct mcs7830_private - private driver data for an individual adapter + * @config: shadow for the network adapter's configuration register + * @mchash: shadow for the network adapter's multicast hash registers + */ +struct mcs7830_private { + uint8_t config; + uint8_t mchash[8]; +}; + +/* + * mcs7830_read_reg() - read a register of the network adapter + * @dev: network device to read from + * @idx: index of the register to start reading from + * @size: number of bytes to read + * @data: buffer to read into + * Return: zero upon success, negative upon error + */ +static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx, + uint16_t size, void *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, size); + + debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size); + + len = usb_control_msg(dev->pusb_dev, + usb_rcvctrlpipe(dev->pusb_dev, 0), + MCS7830_RD_BREQ, + USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, idx, buf, size, + USBCALL_TIMEOUT); + if (len != size) { + debug("%s() len=%d != sz=%d\n", __func__, len, size); + return -EIO; + } + memcpy(data, buf, size); + return 0; +} + +/* + * mcs7830_write_reg() - write a register of the network adapter + * @dev: network device to write to + * @idx: index of the register to start writing to + * @size: number of bytes to write + * @data: buffer holding the data to write + * Return: zero upon success, negative upon error + */ +static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx, + uint16_t size, void *data) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, size); + + debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size); + + memcpy(buf, data, size); + len = usb_control_msg(dev->pusb_dev, + usb_sndctrlpipe(dev->pusb_dev, 0), + MCS7830_WR_BREQ, + USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + 0, idx, buf, size, + USBCALL_TIMEOUT); + if (len != size) { + debug("%s() len=%d != sz=%d\n", __func__, len, size); + return -EIO; + } + return 0; +} + +/* + * mcs7830_phy_emit_wait() - emit PHY read/write access, wait for its execution + * @dev: network device to talk to + * @rwflag: PHY_CMD1_READ or PHY_CMD1_WRITE opcode + * @index: number of the PHY register to read or write + * Return: zero upon success, negative upon error + */ +static int mcs7830_phy_emit_wait(struct ueth_data *dev, + uint8_t rwflag, uint8_t index) +{ + int rc; + int retry; + uint8_t cmd[2]; + + /* send the PHY read/write request */ + cmd[0] = rwflag | PHY_CMD1_PHYADDR; + cmd[1] = PHY_CMD2_PEND | (index & 0x1f); + rc = mcs7830_write_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd); + if (rc < 0) + return rc; + + /* wait for the response to become available (usually < 1ms) */ + retry = 10; + do { + rc = mcs7830_read_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd); + if (rc < 0) + return rc; + if (cmd[1] & PHY_CMD2_READY) + return 0; + if (!retry--) + return -ETIMEDOUT; + mdelay(1); + } while (1); + /* UNREACH */ +} + +/* + * mcs7830_read_phy() - read a PHY register of the network adapter + * @dev: network device to read from + * @index: index of the PHY register to read from + * Return: non-negative 16bit register content, negative upon error + */ +static int mcs7830_read_phy(struct ueth_data *dev, uint8_t index) +{ + int rc; + uint16_t val; + + /* issue the PHY read request and wait for its execution */ + rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_READ, index); + if (rc < 0) + return rc; + + /* fetch the PHY data which was read */ + rc = mcs7830_read_reg(dev, REG_PHY_DATA, sizeof(val), &val); + if (rc < 0) + return rc; + rc = le16_to_cpu(val); + debug("%s(%s, %d) => 0x%04X\n", __func__, dev->eth_dev.name, index, rc); + return rc; +} + +/* + * mcs7830_write_phy() - write a PHY register of the network adapter + * @dev: network device to write to + * @index: index of the PHY register to write to + * @val: value to write to the PHY register + * Return: zero upon success, negative upon error + */ +static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val) +{ + int rc; + + debug("%s(%s, %d, 0x%04X)\n", __func__, dev->eth_dev.name, index, val); + + /* setup the PHY data which is to get written */ + val = cpu_to_le16(val); + rc = mcs7830_write_reg(dev, REG_PHY_DATA, sizeof(val), &val); + if (rc < 0) + return rc; + + /* issue the PHY write request and wait for its execution */ + rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_WRITE, index); + if (rc < 0) + return rc; + + return 0; +} + +/* + * mcs7830_write_config() - write to the network adapter's config register + * @eth: network device to write to + * Return: zero upon success, negative upon error + * + * the data which gets written is taken from the shadow config register + * within the device driver's private data + */ +static int mcs7830_write_config(struct ueth_data *dev) +{ + struct mcs7830_private *priv; + int rc; + + debug("%s()\n", __func__); + priv = dev->dev_priv; + + rc = mcs7830_write_reg(dev, REG_CONFIG, + sizeof(priv->config), &priv->config); + if (rc < 0) { + debug("writing config to adapter failed\n"); + return rc; + } + + return 0; +} + +/* + * mcs7830_write_mchash() - write the network adapter's multicast filter + * @eth: network device to write to + * Return: zero upon success, negative upon error + * + * the data which gets written is taken from the shadow multicast hashes + * within the device driver's private data + */ +static int mcs7830_write_mchash(struct ueth_data *dev) +{ + struct mcs7830_private *priv; + int rc; + + debug("%s()\n", __func__); + priv = dev->dev_priv; + + rc = mcs7830_write_reg(dev, REG_MULTICAST_HASH, + sizeof(priv->mchash), &priv->mchash); + if (rc < 0) { + debug("writing multicast hash to adapter failed\n"); + return rc; + } + + return 0; +} + +/* + * mcs7830_set_autoneg() - setup and trigger ethernet link autonegotiation + * @eth: network device to run link negotiation on + * Return: zero upon success, negative upon error + * + * the routine advertises available media and starts autonegotiation + */ +static int mcs7830_set_autoneg(struct ueth_data *dev) +{ + int adv, flg; + int rc; + + debug("%s()\n", __func__); + + /* + * algorithm taken from the Linux driver, which took it from + * "the original mcs7830 version 1.4 driver": + * + * enable all media, reset BMCR, enable auto neg, restart + * auto neg while keeping the enable auto neg flag set + */ + + adv = ADVERTISE_PAUSE_CAP | ADVERTISE_ALL | ADVERTISE_CSMA; + rc = mcs7830_write_phy(dev, MII_ADVERTISE, adv); + + flg = 0; + if (!rc) + rc = mcs7830_write_phy(dev, MII_BMCR, flg); + + flg |= BMCR_ANENABLE; + if (!rc) + rc = mcs7830_write_phy(dev, MII_BMCR, flg); + + flg |= BMCR_ANRESTART; + if (!rc) + rc = mcs7830_write_phy(dev, MII_BMCR, flg); + + return rc; +} + +/* + * mcs7830_get_rev() - identify a network adapter's chip revision + * @eth: network device to identify + * Return: non-negative number, reflecting the revision number + * + * currently, only "rev C and higher" and "below rev C" are needed, so + * the return value is #1 for "below rev C", and #2 for "rev C and above" + */ +static int mcs7830_get_rev(struct ueth_data *dev) +{ + uint8_t buf[2]; + int rc; + int rev; + + /* register 22 is readable in rev C and higher */ + rc = mcs7830_read_reg(dev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf); + if (rc < 0) + rev = 1; + else + rev = 2; + debug("%s() rc=%d, rev=%d\n", __func__, rc, rev); + return rev; +} + +/* + * mcs7830_apply_fixup() - identify an adapter and potentially apply fixups + * @eth: network device to identify and apply fixups to + * Return: zero upon success (no errors emitted from here) + * + * this routine identifies the network adapter's chip revision, and applies + * fixups for known issues + */ +static int mcs7830_apply_fixup(struct ueth_data *dev) +{ + int rev; + int i; + uint8_t thr; + + rev = mcs7830_get_rev(dev); + debug("%s() rev=%d\n", __func__, rev); + + /* + * rev C requires setting the pause threshold (the Linux driver + * is inconsistent, the implementation does it for "rev C + * exactly", the introductory comment says "rev C and above") + */ + if (rev == 2) { + debug("%s: applying rev C fixup\n", dev->eth_dev.name); + thr = PAUSE_THRESHOLD_DEFAULT; + for (i = 0; i < 2; i++) { + (void)mcs7830_write_reg(dev, REG_PAUSE_THRESHOLD, + sizeof(thr), &thr); + mdelay(1); + } + } + + return 0; +} + +/* + * mcs7830_basic_reset() - bring the network adapter into a known first state + * @eth: network device to act upon + * Return: zero upon success, negative upon error + * + * this routine initializes the network adapter such that subsequent invocations + * of the interface callbacks can exchange ethernet frames; link negotiation is + * triggered from here already and continues in background + */ +static int mcs7830_basic_reset(struct ueth_data *dev) +{ + struct mcs7830_private *priv; + int rc; + + debug("%s()\n", __func__); + priv = dev->dev_priv; + + /* + * comment from the respective Linux driver, which + * unconditionally sets the ALLMULTICAST flag as well: + * should not be needed, but does not work otherwise + */ + priv->config = CONF_TXENABLE; + priv->config |= CONF_ALLMULTICAST; + + rc = mcs7830_set_autoneg(dev); + if (rc < 0) { + error("setting autoneg failed\n"); + return rc; + } + + rc = mcs7830_write_mchash(dev); + if (rc < 0) { + error("failed to set multicast hash\n"); + return rc; + } + + rc = mcs7830_write_config(dev); + if (rc < 0) { + error("failed to set configuration\n"); + return rc; + } + + rc = mcs7830_apply_fixup(dev); + if (rc < 0) { + error("fixup application failed\n"); + return rc; + } + + return 0; +} + +/* + * mcs7830_read_mac() - read an ethernet adapter's MAC address + * @eth: network device to read from + * Return: zero upon success, negative upon error + * + * this routine fetches the MAC address stored within the ethernet adapter, + * and stores it in the ethernet interface's data structure + */ +static int mcs7830_read_mac(struct eth_device *eth) +{ + struct ueth_data *dev; + int rc; + uint8_t buf[ETH_ALEN]; + + debug("%s()\n", __func__); + dev = eth->priv; + + rc = mcs7830_read_reg(dev, REG_ETHER_ADDR, ETH_ALEN, buf); + if (rc < 0) { + debug("reading MAC from adapter failed\n"); + return rc; + } + + memcpy(ð->enetaddr[0], buf, ETH_ALEN); + return 0; +} + +/* + * mcs7830_write_mac() - write an ethernet adapter's MAC address + * @eth: network device to write to + * Return: zero upon success, negative upon error + * + * this routine takes the MAC address from the ethernet interface's data + * structure, and writes it into the ethernet adapter such that subsequent + * exchange of ethernet frames uses this address + */ +static int mcs7830_write_mac(struct eth_device *eth) +{ + struct ueth_data *dev; + int rc; + + debug("%s()\n", __func__); + dev = eth->priv; + + if (sizeof(eth->enetaddr) != ETH_ALEN) + return -EINVAL; + rc = mcs7830_write_reg(dev, REG_ETHER_ADDR, ETH_ALEN, eth->enetaddr); + if (rc < 0) { + debug("writing MAC to adapter failed\n"); + return rc; + } + return 0; +} + +/* + * mcs7830_init() - network interface's init callback + * @eth: network device to initialize + * @bd: board information + * Return: zero upon success, negative upon error + * + * after initial setup during probe() and get_info(), this init() callback + * ensures that the link is up and subsequent send() and recv() calls can + * exchange ethernet frames + */ +static int mcs7830_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev; + int timeout; + int have_link; + + debug("%s()\n", __func__); + dev = eth->priv; + + timeout = 0; + do { + have_link = mcs7830_read_phy(dev, MII_BMSR) & BMSR_LSTATUS; + if (have_link) + break; + udelay(LINKSTATUS_TIMEOUT_RES * 1000); + timeout += LINKSTATUS_TIMEOUT_RES; + } while (timeout < LINKSTATUS_TIMEOUT); + if (!have_link) { + debug("ethernet link is down\n"); + return -ETIMEDOUT; + } + return 0; +} + +/* + * mcs7830_send() - network interface's send callback + * @eth: network device to send the frame from + * @packet: ethernet frame content + * @length: ethernet frame length + * Return: zero upon success, negative upon error + * + * this routine send an ethernet frame out of the network interface + */ +static int mcs7830_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev; + int rc; + int gotlen; + /* there is a status byte after the ethernet frame */ + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, PKTSIZE + sizeof(uint8_t)); + + dev = eth->priv; + + memcpy(buf, packet, length); + rc = usb_bulk_msg(dev->pusb_dev, + usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), + &buf[0], length, &gotlen, + USBCALL_TIMEOUT); + debug("%s() TX want len %d, got len %d, rc %d\n", + __func__, length, gotlen, rc); + return rc; +} + +/* + * mcs7830_recv() - network interface's recv callback + * @eth: network device to receive frames from + * Return: zero upon success, negative upon error + * + * this routine checks for available ethernet frames that the network + * interface might have received, and notifies the network stack + */ +static int mcs7830_recv(struct eth_device *eth) +{ + struct ueth_data *dev; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE); + int rc, wantlen, gotlen; + uint8_t sts; + + debug("%s()\n", __func__); + dev = eth->priv; + + /* fetch input data from the adapter */ + wantlen = MCS7830_RX_URB_SIZE; + rc = usb_bulk_msg(dev->pusb_dev, + usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), + &buf[0], wantlen, &gotlen, + USBCALL_TIMEOUT); + debug("%s() RX want len %d, got len %d, rc %d\n", + __func__, wantlen, gotlen, rc); + if (rc != 0) { + error("RX: failed to receive\n"); + return rc; + } + if (gotlen > wantlen) { + error("RX: got too many bytes (%d)\n", gotlen); + return -EIO; + } + + /* + * the bulk message that we received from USB contains exactly + * one ethernet frame and a trailing status byte + */ + if (gotlen < sizeof(sts)) + return -EIO; + gotlen -= sizeof(sts); + sts = buf[gotlen]; + + if (sts == STAT_RX_FRAME_CORRECT) { + debug("%s() got a frame, len=%d\n", __func__, gotlen); + NetReceive(buf, gotlen); + return 0; + } + + debug("RX: frame error (sts 0x%02X, %s %s %s %s %s)\n", + sts, + (sts & STAT_RX_LARGE_FRAME) ? "large" : "-", + (sts & STAT_RX_LENGTH_ERROR) ? "length" : "-", + (sts & STAT_RX_SHORT_FRAME) ? "short" : "-", + (sts & STAT_RX_CRC_ERROR) ? "crc" : "-", + (sts & STAT_RX_ALIGNMENT_ERROR) ? "align" : "-"); + return -EIO; +} + +/* + * mcs7830_halt() - network interface's halt callback + * @eth: network device to cease operation of + * Return: none + * + * this routine is supposed to undo the effect of previous initialization and + * ethernet frames exchange; in this implementation it's a NOP + */ +static void mcs7830_halt(struct eth_device *eth) +{ + debug("%s()\n", __func__); +} + +/* + * mcs7830_iface_idx - index of detected network interfaces + * + * this counter keeps track of identified supported interfaces, + * to assign unique names as more interfaces are found + */ +static int mcs7830_iface_idx; + +/* + * mcs7830_eth_before_probe() - network driver's before_probe callback + * Return: none + * + * this routine initializes driver's internal data in preparation of + * subsequent probe callbacks + */ +void mcs7830_eth_before_probe(void) +{ + mcs7830_iface_idx = 0; +} + +/* + * struct mcs7830_dongle - description of a supported Moschip ethernet dongle + * @vendor: 16bit USB vendor identification + * @product: 16bit USB product identification + * + * this structure describes a supported USB ethernet dongle by means of the + * vendor and product codes found during USB enumeration; no flags are held + * here since all supported dongles have identical behaviour, and required + * fixups get determined at runtime, such that no manual configuration is + * needed + */ +struct mcs7830_dongle { + uint16_t vendor; + uint16_t product; +}; + +/* + * mcs7830_dongles - the list of supported Moschip based USB ethernet dongles + */ +static const struct mcs7830_dongle mcs7830_dongles[] = { + { 0x9710, 0x7832, }, /* Moschip 7832 */ + { 0x9710, 0x7830, }, /* Moschip 7830 */ + { 0x9710, 0x7730, }, /* Moschip 7730 */ + { 0x0df6, 0x0021, }, /* Sitecom LN 30 */ +}; + +/* + * mcs7830_eth_probe() - network driver's probe callback + * @dev: detected USB device to check + * @ifnum: detected USB interface to check + * @ss: USB ethernet data structure to fill in upon match + * Return: #1 upon match, #0 upon mismatch or error + * + * this routine checks whether the found USB device is supported by + * this ethernet driver, and upon match fills in the USB ethernet + * data structure which later is passed to the get_info callback + */ +int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss) +{ + struct usb_interface *iface; + struct usb_interface_descriptor *iface_desc; + int i; + struct mcs7830_private *priv; + int ep_in_found, ep_out_found, ep_intr_found; + + debug("%s()\n", __func__); + + /* iterate the list of supported dongles */ + iface = &dev->config.if_desc[ifnum]; + iface_desc = &iface->desc; + for (i = 0; i < ARRAY_SIZE(mcs7830_dongles); i++) { + if (dev->descriptor.idVendor == mcs7830_dongles[i].vendor && + dev->descriptor.idProduct == mcs7830_dongles[i].product) + break; + } + if (i == ARRAY_SIZE(mcs7830_dongles)) + return 0; + debug("detected USB ethernet device: %04X:%04X\n", + dev->descriptor.idVendor, dev->descriptor.idProduct); + + /* fill in driver private data */ + priv = calloc(1, sizeof(*priv)); + if (!priv) + return 0; + + /* fill in the ueth_data structure, attach private data */ + memset(ss, 0, sizeof(*ss)); + ss->ifnum = ifnum; + ss->pusb_dev = dev; + ss->subclass = iface_desc->bInterfaceSubClass; + ss->protocol = iface_desc->bInterfaceProtocol; + ss->dev_priv = priv; + + /* + * a minimum of three endpoints is expected: in (bulk), + * out (bulk), and interrupt; ignore all others + */ + ep_in_found = ep_out_found = ep_intr_found = 0; + for (i = 0; i < iface_desc->bNumEndpoints; i++) { + uint8_t eptype, epaddr; + bool is_input; + + eptype = iface->ep_desc[i].bmAttributes; + eptype &= USB_ENDPOINT_XFERTYPE_MASK; + + epaddr = iface->ep_desc[i].bEndpointAddress; + is_input = epaddr & USB_DIR_IN; + epaddr &= USB_ENDPOINT_NUMBER_MASK; + + if (eptype == USB_ENDPOINT_XFER_BULK) { + if (is_input && !ep_in_found) { + ss->ep_in = epaddr; + ep_in_found++; + } + if (!is_input && !ep_out_found) { + ss->ep_out = epaddr; + ep_out_found++; + } + } + + if (eptype == USB_ENDPOINT_XFER_INT) { + if (is_input && !ep_intr_found) { + ss->ep_int = epaddr; + ss->irqinterval = iface->ep_desc[i].bInterval; + ep_intr_found++; + } + } + } + debug("endpoints: in %d, out %d, intr %d\n", + ss->ep_in, ss->ep_out, ss->ep_int); + + /* apply basic sanity checks */ + if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || + !ss->ep_in || !ss->ep_out || !ss->ep_int) { + debug("device probe incomplete\n"); + return 0; + } + + dev->privptr = ss; + return 1; +} + +/* + * mcs7830_eth_get_info() - network driver's get_info callback + * @dev: detected USB device + * @ss: USB ethernet data structure filled in at probe() + * @eth: ethernet interface data structure to fill in + * Return: #1 upon success, #0 upon error + * + * this routine registers the mandatory init(), send(), recv(), and + * halt() callbacks with the ethernet interface, can register the + * optional write_hwaddr() callback with the ethernet interface, + * and initiates configuration of the interface such that subsequent + * calls to those callbacks results in network communication + */ +int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth) +{ + debug("%s()\n", __func__); + if (!eth) { + debug("%s: missing parameter.\n", __func__); + return 0; + } + + snprintf(eth->name, sizeof(eth->name), "%s%d", + MCS7830_BASE_NAME, mcs7830_iface_idx++); + eth->init = mcs7830_init; + eth->send = mcs7830_send; + eth->recv = mcs7830_recv; + eth->halt = mcs7830_halt; + eth->write_hwaddr = mcs7830_write_mac; + eth->priv = ss; + + if (mcs7830_basic_reset(ss)) + return 0; + + if (mcs7830_read_mac(eth)) + return 0; + debug("MAC %pM\n", eth->enetaddr); + + return 1; +} diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index b04e91cfcb..6bca34dcf5 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. * Copyright (C) 2009 NVIDIA, Corporation + * Copyright (C) 2007-2008 SMSC (Steve Glendinning) * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,6 +15,12 @@ /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ +/* LED defines */ +#define LED_GPIO_CFG (0x24) +#define LED_GPIO_CFG_SPD_LED (0x01000000) +#define LED_GPIO_CFG_LNK_LED (0x00100000) +#define LED_GPIO_CFG_FDX_LED (0x00010000) + /* Tx command words */ #define TX_CMD_A_FIRST_SEG_ 0x00002000 #define TX_CMD_A_LAST_SEG_ 0x00001000 @@ -591,6 +598,14 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd) return ret; debug("ID_REV = 0x%08x\n", read_buf); + /* Configure GPIO pins as LED outputs */ + write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | + LED_GPIO_CFG_FDX_LED; + ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf); + if (ret < 0) + return ret; + debug("LED_GPIO_CFG set\n"); + /* Init Tx */ write_buf = 0; ret = smsc95xx_write_reg(dev, FLOW, write_buf); @@ -784,6 +799,8 @@ static const struct smsc95xx_dongle smsc95xx_dongles[] = { { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ + { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */ + { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */ { 0x0000, 0x0000 } /* END - Do not remove */ }; diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c index 2c4126be36..7cb96e3bf6 100644 --- a/drivers/usb/eth/usb_ether.c +++ b/drivers/usb/eth/usb_ether.c @@ -30,6 +30,20 @@ static const struct usb_eth_prob_dev prob_dev[] = { .get_info = asix_eth_get_info, }, #endif +#ifdef CONFIG_USB_ETHER_ASIX88179 + { + .before_probe = ax88179_eth_before_probe, + .probe = ax88179_eth_probe, + .get_info = ax88179_eth_get_info, + }, +#endif +#ifdef CONFIG_USB_ETHER_MCS7830 + { + .before_probe = mcs7830_eth_before_probe, + .probe = mcs7830_eth_probe, + .get_info = mcs7830_eth_get_info, + }, +#endif #ifdef CONFIG_USB_ETHER_SMSC95XX { .before_probe = smsc95xx_eth_before_probe, diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 4c2a39a216..70bb550fa4 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -5,56 +5,34 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libusb_gadget.o - -# if defined(CONFIG_USB_GADGET) || defined(CONFIG_USB_ETHER) -# Everytime you forget how crufty makefiles can get things like -# this remind you... -ifneq (,$(CONFIG_USB_GADGET)$(CONFIG_USB_ETHER)) -COBJS-y += epautoconf.o config.o usbstring.o -endif +obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o +obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o # new USB gadget layer dependencies ifdef CONFIG_USB_GADGET -COBJS-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o -COBJS-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o -COBJS-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o -COBJS-$(CONFIG_DFU_FUNCTION) += f_dfu.o +obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o +obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o +obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o +obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o +obj-$(CONFIG_CI_UDC) += ci_udc.o +obj-$(CONFIG_THOR_FUNCTION) += f_thor.o +obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o +obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o +obj-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o +obj-$(CONFIG_CMD_FASTBOOT) += f_fastboot.o endif ifdef CONFIG_USB_ETHER -COBJS-y += ether.o -COBJS-$(CONFIG_USB_ETH_RNDIS) += rndis.o -COBJS-$(CONFIG_MV_UDC) += mv_udc.o -COBJS-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o +obj-y += ether.o +obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o +obj-$(CONFIG_CI_UDC) += ci_udc.o +obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o else # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE ifdef CONFIG_USB_DEVICE -COBJS-y += core.o -COBJS-y += ep0.o -COBJS-$(CONFIG_DW_UDC) += designware_udc.o -COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o -COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o -COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o -COBJS-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o +obj-y += core.o +obj-y += ep0.o +obj-$(CONFIG_DW_UDC) += designware_udc.o +obj-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o +obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o endif endif - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c new file mode 100644 index 0000000000..fbc74f3bed --- /dev/null +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -0,0 +1,1305 @@ +/* + * Driver for the Atmel USBA high speed USB device controller + * [Original from Linux kernel: drivers/usb/gadget/atmel_usba_udc.c] + * + * Copyright (C) 2005-2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "atmel_usba_udc.h" + +static int vbus_is_present(struct usba_udc *udc) +{ + /* No Vbus detection: Assume always present */ + return 1; +} + +static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req) +{ + unsigned int transaction_len; + + transaction_len = req->req.length - req->req.actual; + req->last_transaction = 1; + if (transaction_len > ep->ep.maxpacket) { + transaction_len = ep->ep.maxpacket; + req->last_transaction = 0; + } else if (transaction_len == ep->ep.maxpacket && req->req.zero) { + req->last_transaction = 0; + } + + DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n", + ep->ep.name, req, transaction_len, + req->last_transaction ? ", done" : ""); + + memcpy(ep->fifo, req->req.buf + req->req.actual, transaction_len); + usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); + req->req.actual += transaction_len; +} + +static void submit_request(struct usba_ep *ep, struct usba_request *req) +{ + DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d), dma: %d\n", + ep->ep.name, req, req->req.length, req->using_dma); + + req->req.actual = 0; + req->submitted = 1; + + next_fifo_transaction(ep, req); + if (req->last_transaction) { + usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); + usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); + } else { + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); + usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); + } +} + +static void submit_next_request(struct usba_ep *ep) +{ + struct usba_request *req; + + if (list_empty(&ep->queue)) { + usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY); + return; + } + + req = list_entry(ep->queue.next, struct usba_request, queue); + if (!req->submitted) + submit_request(ep, req); +} + +static void send_status(struct usba_udc *udc, struct usba_ep *ep) +{ + ep->state = STATUS_STAGE_IN; + usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); + usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); +} + +static void receive_data(struct usba_ep *ep) +{ + struct usba_udc *udc = ep->udc; + struct usba_request *req; + unsigned long status; + unsigned int bytecount, nr_busy; + int is_complete = 0; + + status = usba_ep_readl(ep, STA); + nr_busy = USBA_BFEXT(BUSY_BANKS, status); + + DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy); + + while (nr_busy > 0) { + if (list_empty(&ep->queue)) { + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); + break; + } + req = list_entry(ep->queue.next, + struct usba_request, queue); + + bytecount = USBA_BFEXT(BYTE_COUNT, status); + + if (status & USBA_SHORT_PACKET) + is_complete = 1; + if (req->req.actual + bytecount >= req->req.length) { + is_complete = 1; + bytecount = req->req.length - req->req.actual; + } + + memcpy(req->req.buf + req->req.actual, ep->fifo, bytecount); + req->req.actual += bytecount; + + usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); + + if (is_complete) { + DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name); + req->req.status = 0; + list_del_init(&req->queue); + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); + spin_lock(&udc->lock); + req->req.complete(&ep->ep, &req->req); + spin_unlock(&udc->lock); + } + + status = usba_ep_readl(ep, STA); + nr_busy = USBA_BFEXT(BUSY_BANKS, status); + + if (is_complete && ep_is_control(ep)) { + send_status(udc, ep); + break; + } + } +} + +static void +request_complete(struct usba_ep *ep, struct usba_request *req, int status) +{ + if (req->req.status == -EINPROGRESS) + req->req.status = status; + + DBG(DBG_GADGET | DBG_REQ, "%s: req %p complete: status %d, actual %u\n", + ep->ep.name, req, req->req.status, req->req.actual); + + req->req.complete(&ep->ep, &req->req); +} + +static void +request_complete_list(struct usba_ep *ep, struct list_head *list, int status) +{ + struct usba_request *req, *tmp_req; + + list_for_each_entry_safe(req, tmp_req, list, queue) { + list_del_init(&req->queue); + request_complete(ep, req, status); + } +} + +static int +usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc) +{ + struct usba_ep *ep = to_usba_ep(_ep); + struct usba_udc *udc = ep->udc; + unsigned long flags = 0, ept_cfg, maxpacket; + unsigned int nr_trans; + + DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc); + + maxpacket = usb_endpoint_maxp(desc) & 0x7ff; + + if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) + != ep->index) || + ep->index == 0 || + desc->bDescriptorType != USB_DT_ENDPOINT || + maxpacket == 0 || + maxpacket > ep->fifo_size) { + DBG(DBG_ERR, "ep_enable: Invalid argument"); + return -EINVAL; + } + + ep->is_isoc = 0; + ep->is_in = 0; + + if (maxpacket <= 8) + ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8); + else + /* LSB is bit 1, not 0 */ + ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3); + + DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n", + ep->ep.name, ept_cfg, maxpacket); + + if (usb_endpoint_dir_in(desc)) { + ep->is_in = 1; + ept_cfg |= USBA_EPT_DIR_IN; + } + + switch (usb_endpoint_type(desc)) { + case USB_ENDPOINT_XFER_CONTROL: + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL); + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE); + break; + case USB_ENDPOINT_XFER_ISOC: + if (!ep->can_isoc) { + DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n", + ep->ep.name); + return -EINVAL; + } + + /* + * Bits 11:12 specify number of _additional_ + * transactions per microframe. + */ + nr_trans = ((usb_endpoint_maxp(desc) >> 11) & 3) + 1; + if (nr_trans > 3) + return -EINVAL; + + ep->is_isoc = 1; + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO); + + /* + * Do triple-buffering on high-bandwidth iso endpoints. + */ + if (nr_trans > 1 && ep->nr_banks == 3) + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE); + else + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE); + ept_cfg |= USBA_BF(NB_TRANS, nr_trans); + break; + case USB_ENDPOINT_XFER_BULK: + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK); + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE); + break; + case USB_ENDPOINT_XFER_INT: + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT); + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE); + break; + } + + spin_lock_irqsave(&ep->udc->lock, flags); + + ep->desc = desc; + ep->ep.maxpacket = maxpacket; + + usba_ep_writel(ep, CFG, ept_cfg); + usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); + + usba_writel(udc, INT_ENB, + (usba_readl(udc, INT_ENB) + | USBA_BF(EPT_INT, 1 << ep->index))); + + spin_unlock_irqrestore(&udc->lock, flags); + + DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index, + (unsigned long)usba_ep_readl(ep, CFG)); + DBG(DBG_HW, "INT_ENB after init: %#08lx\n", + (unsigned long)usba_readl(udc, INT_ENB)); + + return 0; +} + +static int usba_ep_disable(struct usb_ep *_ep) +{ + struct usba_ep *ep = to_usba_ep(_ep); + struct usba_udc *udc = ep->udc; + LIST_HEAD(req_list); + unsigned long flags = 0; + + DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name); + + spin_lock_irqsave(&udc->lock, flags); + + if (!ep->desc) { + spin_unlock_irqrestore(&udc->lock, flags); + /* REVISIT because this driver disables endpoints in + * reset_all_endpoints() before calling disconnect(), + * most gadget drivers would trigger this non-error ... + */ + if (udc->gadget.speed != USB_SPEED_UNKNOWN) + DBG(DBG_ERR, "ep_disable: %s not enabled\n", + ep->ep.name); + return -EINVAL; + } + ep->desc = NULL; + + list_splice_init(&ep->queue, &req_list); + usba_ep_writel(ep, CFG, 0); + usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE); + usba_writel(udc, INT_ENB, + usba_readl(udc, INT_ENB) & + ~USBA_BF(EPT_INT, 1 << ep->index)); + + request_complete_list(ep, &req_list, -ESHUTDOWN); + + spin_unlock_irqrestore(&udc->lock, flags); + + return 0; +} + +static struct usb_request * +usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) +{ + struct usba_request *req; + + DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags); + + req = calloc(1, sizeof(struct usba_request)); + if (!req) + return NULL; + + INIT_LIST_HEAD(&req->queue); + + return &req->req; +} + +static void +usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) +{ + struct usba_request *req = to_usba_req(_req); + + DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req); + + free(req); +} + +static int +usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) +{ + struct usba_request *req = to_usba_req(_req); + struct usba_ep *ep = to_usba_ep(_ep); + struct usba_udc *udc = ep->udc; + unsigned long flags = 0; + int ret; + + DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n", + ep->ep.name, req, _req->length); + + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || + !ep->desc) + return -ESHUTDOWN; + + req->submitted = 0; + req->using_dma = 0; + req->last_transaction = 0; + + _req->status = -EINPROGRESS; + _req->actual = 0; + + /* May have received a reset since last time we checked */ + ret = -ESHUTDOWN; + spin_lock_irqsave(&udc->lock, flags); + if (ep->desc) { + list_add_tail(&req->queue, &ep->queue); + + if ((!ep_is_control(ep) && ep->is_in) || + (ep_is_control(ep) && (ep->state == DATA_STAGE_IN || + ep->state == STATUS_STAGE_IN))) + usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); + else + usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY); + + ret = 0; + } + spin_unlock_irqrestore(&udc->lock, flags); + + return ret; +} + +static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) +{ + struct usba_ep *ep = to_usba_ep(_ep); + struct usba_request *req = to_usba_req(_req); + + DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n", + ep->ep.name, req); + + /* + * Errors should stop the queue from advancing until the + * completion function returns. + */ + list_del_init(&req->queue); + + request_complete(ep, req, -ECONNRESET); + + /* Process the next request if any */ + submit_next_request(ep); + + return 0; +} + +static int usba_ep_set_halt(struct usb_ep *_ep, int value) +{ + struct usba_ep *ep = to_usba_ep(_ep); + unsigned long flags = 0; + int ret = 0; + + DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name, + value ? "set" : "clear"); + + if (!ep->desc) { + DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n", + ep->ep.name); + return -ENODEV; + } + + if (ep->is_isoc) { + DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n", + ep->ep.name); + return -ENOTTY; + } + + spin_lock_irqsave(&udc->lock, flags); + + /* + * We can't halt IN endpoints while there are still data to be + * transferred + */ + if (!list_empty(&ep->queue) || + ((value && ep->is_in && (usba_ep_readl(ep, STA) & + USBA_BF(BUSY_BANKS, -1L))))) { + ret = -EAGAIN; + } else { + if (value) + usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL); + else + usba_ep_writel(ep, CLR_STA, + USBA_FORCE_STALL | USBA_TOGGLE_CLR); + usba_ep_readl(ep, STA); + } + + spin_unlock_irqrestore(&udc->lock, flags); + + return ret; +} + +static int usba_ep_fifo_status(struct usb_ep *_ep) +{ + struct usba_ep *ep = to_usba_ep(_ep); + + return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA)); +} + +static void usba_ep_fifo_flush(struct usb_ep *_ep) +{ + struct usba_ep *ep = to_usba_ep(_ep); + struct usba_udc *udc = ep->udc; + + usba_writel(udc, EPT_RST, 1 << ep->index); +} + +static const struct usb_ep_ops usba_ep_ops = { + .enable = usba_ep_enable, + .disable = usba_ep_disable, + .alloc_request = usba_ep_alloc_request, + .free_request = usba_ep_free_request, + .queue = usba_ep_queue, + .dequeue = usba_ep_dequeue, + .set_halt = usba_ep_set_halt, + .fifo_status = usba_ep_fifo_status, + .fifo_flush = usba_ep_fifo_flush, +}; + +static int usba_udc_get_frame(struct usb_gadget *gadget) +{ + struct usba_udc *udc = to_usba_udc(gadget); + + return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM)); +} + +static int usba_udc_wakeup(struct usb_gadget *gadget) +{ + struct usba_udc *udc = to_usba_udc(gadget); + unsigned long flags = 0; + u32 ctrl; + int ret = -EINVAL; + + spin_lock_irqsave(&udc->lock, flags); + if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) { + ctrl = usba_readl(udc, CTRL); + usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP); + ret = 0; + } + spin_unlock_irqrestore(&udc->lock, flags); + + return ret; +} + +static int +usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) +{ + struct usba_udc *udc = to_usba_udc(gadget); + unsigned long flags = 0; + + spin_lock_irqsave(&udc->lock, flags); + if (is_selfpowered) + udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED; + else + udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED); + spin_unlock_irqrestore(&udc->lock, flags); + + return 0; +} + +static const struct usb_gadget_ops usba_udc_ops = { + .get_frame = usba_udc_get_frame, + .wakeup = usba_udc_wakeup, + .set_selfpowered = usba_udc_set_selfpowered, +}; + +static struct usb_endpoint_descriptor usba_ep0_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, + .wMaxPacketSize = cpu_to_le16(64), + /* FIXME: I have no idea what to put here */ + .bInterval = 1, +}; + +/* + * Called with interrupts disabled and udc->lock held. + */ +static void reset_all_endpoints(struct usba_udc *udc) +{ + struct usba_ep *ep; + struct usba_request *req, *tmp_req; + + usba_writel(udc, EPT_RST, ~0UL); + + ep = to_usba_ep(udc->gadget.ep0); + list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) { + list_del_init(&req->queue); + request_complete(ep, req, -ECONNRESET); + } + + /* NOTE: normally, the next call to the gadget driver is in + * charge of disabling endpoints... usually disconnect(). + * The exception would be entering a high speed test mode. + * + * FIXME remove this code ... and retest thoroughly. + */ + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { + if (ep->desc) { + spin_unlock(&udc->lock); + usba_ep_disable(&ep->ep); + spin_lock(&udc->lock); + } + } +} + +static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex) +{ + struct usba_ep *ep; + + if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0) + return to_usba_ep(udc->gadget.ep0); + + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { + u8 bEndpointAddress; + + if (!ep->desc) + continue; + bEndpointAddress = ep->desc->bEndpointAddress; + if ((wIndex ^ bEndpointAddress) & USB_DIR_IN) + continue; + if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) + == (wIndex & USB_ENDPOINT_NUMBER_MASK)) + return ep; + } + + return NULL; +} + +/* Called with interrupts disabled and udc->lock held */ +static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep) +{ + usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL); + ep->state = WAIT_FOR_SETUP; +} + +static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep) +{ + if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL) + return 1; + return 0; +} + +static inline void set_address(struct usba_udc *udc, unsigned int addr) +{ + u32 regval; + + DBG(DBG_BUS, "setting address %u...\n", addr); + regval = usba_readl(udc, CTRL); + regval = USBA_BFINS(DEV_ADDR, addr, regval); + usba_writel(udc, CTRL, regval); +} + +static int do_test_mode(struct usba_udc *udc) +{ + static const char test_packet_buffer[] = { + /* JKJKJKJK * 9 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* JJKKJJKK * 8 */ + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + /* JJKKJJKK * 8 */ + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + /* JJJJJJJKKKKKKK * 8 */ + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + /* JJJJJJJK * 8 */ + 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, + /* {JKKKKKKK * 10}, JK */ + 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E + }; + struct usba_ep *ep; + int test_mode; + + test_mode = udc->test_mode; + + /* Start from a clean slate */ + reset_all_endpoints(udc); + + switch (test_mode) { + case 0x0100: + /* Test_J */ + usba_writel(udc, TST, USBA_TST_J_MODE); + DBG(DBG_ALL, "Entering Test_J mode...\n"); + break; + case 0x0200: + /* Test_K */ + usba_writel(udc, TST, USBA_TST_K_MODE); + DBG(DBG_ALL, "Entering Test_K mode...\n"); + break; + case 0x0300: + /* + * Test_SE0_NAK: Force high-speed mode and set up ep0 + * for Bulk IN transfers + */ + ep = &udc->usba_ep[0]; + usba_writel(udc, TST, + USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH)); + usba_ep_writel(ep, CFG, + USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64) + | USBA_EPT_DIR_IN + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK) + | USBA_BF(BK_NUMBER, 1)); + if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) { + set_protocol_stall(udc, ep); + DBG(DBG_ALL, "Test_SE0_NAK: ep0 not mapped\n"); + } else { + usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); + DBG(DBG_ALL, "Entering Test_SE0_NAK mode...\n"); + } + break; + case 0x0400: + /* Test_Packet */ + ep = &udc->usba_ep[0]; + usba_ep_writel(ep, CFG, + USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64) + | USBA_EPT_DIR_IN + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK) + | USBA_BF(BK_NUMBER, 1)); + if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) { + set_protocol_stall(udc, ep); + DBG(DBG_ALL, "Test_Packet: ep0 not mapped\n"); + } else { + usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); + usba_writel(udc, TST, USBA_TST_PKT_MODE); + memcpy(ep->fifo, test_packet_buffer, + sizeof(test_packet_buffer)); + usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); + DBG(DBG_ALL, "Entering Test_Packet mode...\n"); + } + break; + default: + DBG(DBG_ERR, "Invalid test mode: 0x%04x\n", test_mode); + return -EINVAL; + } + + return 0; +} + +/* Avoid overly long expressions */ +static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq) +{ + if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP)) + return true; + return false; +} + +static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq) +{ + if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE)) + return true; + return false; +} + +static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq) +{ + if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT)) + return true; + return false; +} + +static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep, + struct usb_ctrlrequest *crq) +{ + int retval = 0; + + switch (crq->bRequest) { + case USB_REQ_GET_STATUS: { + u16 status; + + if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) { + status = cpu_to_le16(udc->devstatus); + } else if (crq->bRequestType + == (USB_DIR_IN | USB_RECIP_INTERFACE)) { + status = cpu_to_le16(0); + } else if (crq->bRequestType + == (USB_DIR_IN | USB_RECIP_ENDPOINT)) { + struct usba_ep *target; + + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); + if (!target) + goto stall; + + status = 0; + if (is_stalled(udc, target)) + status |= cpu_to_le16(1); + } else { + goto delegate; + } + + /* Write directly to the FIFO. No queueing is done. */ + if (crq->wLength != cpu_to_le16(sizeof(status))) + goto stall; + ep->state = DATA_STAGE_IN; + __raw_writew(status, ep->fifo); + usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); + break; + } + + case USB_REQ_CLEAR_FEATURE: { + if (crq->bRequestType == USB_RECIP_DEVICE) { + if (feature_is_dev_remote_wakeup(crq)) + udc->devstatus + &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); + else + /* Can't CLEAR_FEATURE TEST_MODE */ + goto stall; + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) { + struct usba_ep *target; + + if (crq->wLength != cpu_to_le16(0) || + !feature_is_ep_halt(crq)) + goto stall; + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); + if (!target) + goto stall; + + usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL); + if (target->index != 0) + usba_ep_writel(target, CLR_STA, + USBA_TOGGLE_CLR); + } else { + goto delegate; + } + + send_status(udc, ep); + break; + } + + case USB_REQ_SET_FEATURE: { + if (crq->bRequestType == USB_RECIP_DEVICE) { + if (feature_is_dev_test_mode(crq)) { + send_status(udc, ep); + ep->state = STATUS_STAGE_TEST; + udc->test_mode = le16_to_cpu(crq->wIndex); + return 0; + } else if (feature_is_dev_remote_wakeup(crq)) { + udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP; + } else { + goto stall; + } + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) { + struct usba_ep *target; + + if (crq->wLength != cpu_to_le16(0) || + !feature_is_ep_halt(crq)) + goto stall; + + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); + if (!target) + goto stall; + + usba_ep_writel(target, SET_STA, USBA_FORCE_STALL); + } else { + goto delegate; + } + + send_status(udc, ep); + break; + } + + case USB_REQ_SET_ADDRESS: + if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE)) + goto delegate; + + set_address(udc, le16_to_cpu(crq->wValue)); + send_status(udc, ep); + ep->state = STATUS_STAGE_ADDR; + break; + + default: +delegate: + spin_unlock(&udc->lock); + retval = udc->driver->setup(&udc->gadget, crq); + spin_lock(&udc->lock); + } + + return retval; + +stall: + DBG(DBG_ALL, "%s: Invalid setup request: %02x.%02x v%04x i%04x l%d\n", + ep->ep.name, crq->bRequestType, crq->bRequest, + le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex), + le16_to_cpu(crq->wLength)); + set_protocol_stall(udc, ep); + + return -1; +} + +static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep) +{ + struct usba_request *req; + u32 epstatus; + u32 epctrl; + +restart: + epstatus = usba_ep_readl(ep, STA); + epctrl = usba_ep_readl(ep, CTL); + + DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n", + ep->ep.name, ep->state, epstatus, epctrl); + + req = NULL; + if (!list_empty(&ep->queue)) + req = list_entry(ep->queue.next, + struct usba_request, queue); + + if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) { + if (req->submitted) + next_fifo_transaction(ep, req); + else + submit_request(ep, req); + + if (req->last_transaction) { + usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); + usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); + } + goto restart; + } + if ((epstatus & epctrl) & USBA_TX_COMPLETE) { + usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE); + + switch (ep->state) { + case DATA_STAGE_IN: + usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY); + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); + ep->state = STATUS_STAGE_OUT; + break; + case STATUS_STAGE_ADDR: + /* Activate our new address */ + usba_writel(udc, CTRL, (usba_readl(udc, CTRL) + | USBA_FADDR_EN)); + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); + ep->state = WAIT_FOR_SETUP; + break; + case STATUS_STAGE_IN: + if (req) { + list_del_init(&req->queue); + request_complete(ep, req, 0); + submit_next_request(ep); + } + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); + ep->state = WAIT_FOR_SETUP; + break; + case STATUS_STAGE_TEST: + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); + ep->state = WAIT_FOR_SETUP; + if (do_test_mode(udc)) + set_protocol_stall(udc, ep); + break; + default: + DBG(DBG_ALL, "%s: TXCOMP: Invalid endpoint state %d\n", + ep->ep.name, ep->state); + set_protocol_stall(udc, ep); + break; + } + + goto restart; + } + if ((epstatus & epctrl) & USBA_RX_BK_RDY) { + switch (ep->state) { + case STATUS_STAGE_OUT: + usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); + + if (req) { + list_del_init(&req->queue); + request_complete(ep, req, 0); + } + ep->state = WAIT_FOR_SETUP; + break; + + case DATA_STAGE_OUT: + receive_data(ep); + break; + + default: + usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); + DBG(DBG_ALL, "%s: RXRDY: Invalid endpoint state %d\n", + ep->ep.name, ep->state); + set_protocol_stall(udc, ep); + break; + } + + goto restart; + } + if (epstatus & USBA_RX_SETUP) { + union { + struct usb_ctrlrequest crq; + unsigned long data[2]; + } crq; + unsigned int pkt_len; + int ret; + + if (ep->state != WAIT_FOR_SETUP) { + /* + * Didn't expect a SETUP packet at this + * point. Clean up any pending requests (which + * may be successful). + */ + int status = -EPROTO; + + /* + * RXRDY and TXCOMP are dropped when SETUP + * packets arrive. Just pretend we received + * the status packet. + */ + if (ep->state == STATUS_STAGE_OUT || + ep->state == STATUS_STAGE_IN) { + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); + status = 0; + } + + if (req) { + list_del_init(&req->queue); + request_complete(ep, req, status); + } + } + + pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA)); + DBG(DBG_HW, "Packet length: %u\n", pkt_len); + if (pkt_len != sizeof(crq)) { + DBG(DBG_ALL, "udc: Invalid length %u (expected %zu)\n", + pkt_len, sizeof(crq)); + set_protocol_stall(udc, ep); + return; + } + + DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo); + memcpy(crq.data, ep->fifo, sizeof(crq)); + + /* Free up one bank in the FIFO so that we can + * generate or receive a reply right away. */ + usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP); + + if (crq.crq.bRequestType & USB_DIR_IN) { + /* + * The USB 2.0 spec states that "if wLength is + * zero, there is no data transfer phase." + * However, testusb #14 seems to actually + * expect a data phase even if wLength = 0... + */ + ep->state = DATA_STAGE_IN; + } else { + if (crq.crq.wLength != cpu_to_le16(0)) + ep->state = DATA_STAGE_OUT; + else + ep->state = STATUS_STAGE_IN; + } + + ret = -1; + if (ep->index == 0) { + ret = handle_ep0_setup(udc, ep, &crq.crq); + } else { + spin_unlock(&udc->lock); + ret = udc->driver->setup(&udc->gadget, &crq.crq); + spin_lock(&udc->lock); + } + + DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n", + crq.crq.bRequestType, crq.crq.bRequest, + le16_to_cpu(crq.crq.wLength), ep->state, ret); + + if (ret < 0) { + /* Let the host know that we failed */ + set_protocol_stall(udc, ep); + } + } +} + +static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep) +{ + struct usba_request *req; + u32 epstatus; + u32 epctrl; + + epstatus = usba_ep_readl(ep, STA); + epctrl = usba_ep_readl(ep, CTL); + + DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus); + + while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) { + DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name); + + if (list_empty(&ep->queue)) { + DBG(DBG_INT, "ep_irq: queue empty\n"); + usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); + return; + } + + req = list_entry(ep->queue.next, struct usba_request, queue); + + if (req->submitted) + next_fifo_transaction(ep, req); + else + submit_request(ep, req); + + if (req->last_transaction) { + list_del_init(&req->queue); + submit_next_request(ep); + request_complete(ep, req, 0); + } + + epstatus = usba_ep_readl(ep, STA); + epctrl = usba_ep_readl(ep, CTL); + } + + if ((epstatus & epctrl) & USBA_RX_BK_RDY) { + DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name); + receive_data(ep); + } +} + +static int usba_udc_irq(struct usba_udc *udc) +{ + u32 status, ep_status; + + spin_lock(&udc->lock); + + status = usba_readl(udc, INT_STA); + DBG(DBG_INT, "irq, status=%#08x\n", status); + + if (status & USBA_DET_SUSPEND) { + usba_writel(udc, INT_CLR, USBA_DET_SUSPEND); + DBG(DBG_BUS, "Suspend detected\n"); + if (udc->gadget.speed != USB_SPEED_UNKNOWN && + udc->driver && udc->driver->suspend) { + spin_unlock(&udc->lock); + udc->driver->suspend(&udc->gadget); + spin_lock(&udc->lock); + } + } + + if (status & USBA_WAKE_UP) { + usba_writel(udc, INT_CLR, USBA_WAKE_UP); + DBG(DBG_BUS, "Wake Up CPU detected\n"); + } + + if (status & USBA_END_OF_RESUME) { + usba_writel(udc, INT_CLR, USBA_END_OF_RESUME); + DBG(DBG_BUS, "Resume detected\n"); + if (udc->gadget.speed != USB_SPEED_UNKNOWN && + udc->driver && udc->driver->resume) { + spin_unlock(&udc->lock); + udc->driver->resume(&udc->gadget); + spin_lock(&udc->lock); + } + } + + ep_status = USBA_BFEXT(EPT_INT, status); + if (ep_status) { + int i; + + for (i = 0; i < USBA_NR_ENDPOINTS; i++) + if (ep_status & (1 << i)) { + if (ep_is_control(&udc->usba_ep[i])) + usba_control_irq(udc, &udc->usba_ep[i]); + else + usba_ep_irq(udc, &udc->usba_ep[i]); + } + } + + if (status & USBA_END_OF_RESET) { + struct usba_ep *ep0; + + usba_writel(udc, INT_CLR, USBA_END_OF_RESET); + reset_all_endpoints(udc); + + if (udc->gadget.speed != USB_SPEED_UNKNOWN && + udc->driver->disconnect) { + udc->gadget.speed = USB_SPEED_UNKNOWN; + spin_unlock(&udc->lock); + udc->driver->disconnect(&udc->gadget); + spin_lock(&udc->lock); + } + + if (status & USBA_HIGH_SPEED) + udc->gadget.speed = USB_SPEED_HIGH; + else + udc->gadget.speed = USB_SPEED_FULL; + + ep0 = &udc->usba_ep[0]; + ep0->desc = &usba_ep0_desc; + ep0->state = WAIT_FOR_SETUP; + usba_ep_writel(ep0, CFG, + (USBA_BF(EPT_SIZE, EP0_EPT_SIZE) + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL) + | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE))); + usba_ep_writel(ep0, CTL_ENB, + USBA_EPT_ENABLE | USBA_RX_SETUP); + usba_writel(udc, INT_ENB, + (usba_readl(udc, INT_ENB) + | USBA_BF(EPT_INT, 1) + | USBA_DET_SUSPEND + | USBA_END_OF_RESUME)); + + /* + * Unclear why we hit this irregularly, e.g. in usbtest, + * but it's clearly harmless... + */ + if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED)) + DBG(DBG_ALL, "ODD: EP0 configuration is invalid!\n"); + } + + spin_unlock(&udc->lock); + + return 0; +} + +static int atmel_usba_start(struct usba_udc *udc) +{ + udc->devstatus = 1 << USB_DEVICE_SELF_POWERED; + + udc->vbus_prev = 0; + + /* If Vbus is present, enable the controller and wait for reset */ + if (vbus_is_present(udc) && udc->vbus_prev == 0) { + usba_writel(udc, CTRL, USBA_ENABLE_MASK); + usba_writel(udc, INT_ENB, USBA_END_OF_RESET); + } + + return 0; +} + +static int atmel_usba_stop(struct usba_udc *udc) +{ + udc->gadget.speed = USB_SPEED_UNKNOWN; + reset_all_endpoints(udc); + + /* This will also disable the DP pullup */ + usba_writel(udc, CTRL, USBA_DISABLE_MASK); + + return 0; +} + +static struct usba_udc controller = { + .regs = (unsigned *)ATMEL_BASE_UDPHS, + .fifo = (unsigned *)ATMEL_BASE_UDPHS_FIFO, + .gadget = { + .ops = &usba_udc_ops, + .ep_list = LIST_HEAD_INIT(controller.gadget.ep_list), + .speed = USB_SPEED_HIGH, + .is_dualspeed = 1, + .name = "atmel_usba_udc", + }, +}; + +int usb_gadget_handle_interrupts(void) +{ + struct usba_udc *udc = &controller; + + return usba_udc_irq(udc); +} + + +int usb_gadget_register_driver(struct usb_gadget_driver *driver) +{ + struct usba_udc *udc = &controller; + int ret; + + if (!driver || !driver->bind || !driver->setup) { + printf("bad paramter\n"); + return -EINVAL; + } + + if (udc->driver) { + printf("UDC already has a gadget driver\n"); + return -EBUSY; + } + + atmel_usba_start(udc); + + udc->driver = driver; + + ret = driver->bind(&udc->gadget); + if (ret) { + error("driver->bind() returned %d\n", ret); + udc->driver = NULL; + } + + return ret; +} + +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) +{ + struct usba_udc *udc = &controller; + + if (!driver || !driver->unbind || !driver->disconnect) { + error("bad paramter\n"); + return -EINVAL; + } + + driver->disconnect(&udc->gadget); + driver->unbind(&udc->gadget); + udc->driver = NULL; + + atmel_usba_stop(udc); + + return 0; +} + +static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata, + struct usba_udc *udc) +{ + struct usba_ep *eps; + int i; + + eps = malloc(sizeof(struct usba_ep) * pdata->num_ep); + if (!eps) { + error("failed to alloc eps\n"); + return NULL; + } + + udc->gadget.ep0 = &eps[0].ep; + + INIT_LIST_HEAD(&udc->gadget.ep_list); + INIT_LIST_HEAD(&eps[0].ep.ep_list); + + for (i = 0; i < pdata->num_ep; i++) { + struct usba_ep *ep = &eps[i]; + + ep->ep_regs = udc->regs + USBA_EPT_BASE(i); + ep->dma_regs = udc->regs + USBA_DMA_BASE(i); + ep->fifo = udc->fifo + USBA_FIFO_BASE(i); + ep->ep.ops = &usba_ep_ops; + ep->ep.name = pdata->ep[i].name; + ep->ep.maxpacket = pdata->ep[i].fifo_size; + ep->fifo_size = ep->ep.maxpacket; + ep->udc = udc; + INIT_LIST_HEAD(&ep->queue); + ep->nr_banks = pdata->ep[i].nr_banks; + ep->index = pdata->ep[i].index; + ep->can_dma = pdata->ep[i].can_dma; + ep->can_isoc = pdata->ep[i].can_isoc; + if (i) + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); + }; + + return eps; +} + +int usba_udc_probe(struct usba_platform_data *pdata) +{ + struct usba_udc *udc; + + udc = &controller; + + udc->usba_ep = usba_udc_pdata(pdata, udc); + + return 0; +} diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h new file mode 100644 index 0000000000..92e462db60 --- /dev/null +++ b/drivers/usb/gadget/atmel_usba_udc.h @@ -0,0 +1,326 @@ +/* + * Register definition for Atmel USBA high speed USB device controller + * [Original from Linux kernel: drivers/usb/gadget/atmel_usba_udc.h] + * + * Copyright (C) 2005-2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LINUX_USB_GADGET_USBA_UDC_H__ +#define __LINUX_USB_GADGET_USBA_UDC_H__ + +/* USB register offsets */ +#define USBA_CTRL 0x0000 +#define USBA_FNUM 0x0004 +#define USBA_INT_ENB 0x0010 +#define USBA_INT_STA 0x0014 +#define USBA_INT_CLR 0x0018 +#define USBA_EPT_RST 0x001c +#define USBA_TST 0x00e0 + +/* USB endpoint register offsets */ +#define USBA_EPT_CFG 0x0000 +#define USBA_EPT_CTL_ENB 0x0004 +#define USBA_EPT_CTL_DIS 0x0008 +#define USBA_EPT_CTL 0x000c +#define USBA_EPT_SET_STA 0x0014 +#define USBA_EPT_CLR_STA 0x0018 +#define USBA_EPT_STA 0x001c + +/* USB DMA register offsets */ +#define USBA_DMA_NXT_DSC 0x0000 +#define USBA_DMA_ADDRESS 0x0004 +#define USBA_DMA_CONTROL 0x0008 +#define USBA_DMA_STATUS 0x000c + +/* Bitfields in CTRL */ +#define USBA_DEV_ADDR_OFFSET 0 +#define USBA_DEV_ADDR_SIZE 7 +#define USBA_FADDR_EN (1 << 7) +#define USBA_EN_USBA (1 << 8) +#define USBA_DETACH (1 << 9) +#define USBA_REMOTE_WAKE_UP (1 << 10) +#define USBA_PULLD_DIS (1 << 11) + +#if defined(CONFIG_AVR32) +#define USBA_ENABLE_MASK USBA_EN_USBA +#define USBA_DISABLE_MASK 0 +#elif defined(CONFIG_AT91FAMILY) +#define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS) +#define USBA_DISABLE_MASK USBA_DETACH +#endif /* CONFIG_ARCH_AT91 */ + +/* Bitfields in FNUM */ +#define USBA_MICRO_FRAME_NUM_OFFSET 0 +#define USBA_MICRO_FRAME_NUM_SIZE 3 +#define USBA_FRAME_NUMBER_OFFSET 3 +#define USBA_FRAME_NUMBER_SIZE 11 +#define USBA_FRAME_NUM_ERROR (1 << 31) + +/* Bitfields in INT_ENB/INT_STA/INT_CLR */ +#define USBA_HIGH_SPEED (1 << 0) +#define USBA_DET_SUSPEND (1 << 1) +#define USBA_MICRO_SOF (1 << 2) +#define USBA_SOF (1 << 3) +#define USBA_END_OF_RESET (1 << 4) +#define USBA_WAKE_UP (1 << 5) +#define USBA_END_OF_RESUME (1 << 6) +#define USBA_UPSTREAM_RESUME (1 << 7) +#define USBA_EPT_INT_OFFSET 8 +#define USBA_EPT_INT_SIZE 16 +#define USBA_DMA_INT_OFFSET 24 +#define USBA_DMA_INT_SIZE 8 + +/* Bitfields in EPT_RST */ +#define USBA_RST_OFFSET 0 +#define USBA_RST_SIZE 16 + +/* Bitfields in USBA_TST */ +#define USBA_SPEED_CFG_OFFSET 0 +#define USBA_SPEED_CFG_SIZE 2 +#define USBA_TST_J_MODE (1 << 2) +#define USBA_TST_K_MODE (1 << 3) +#define USBA_TST_PKT_MODE (1 << 4) +#define USBA_OPMODE2 (1 << 5) + +/* Bitfields in EPT_CFG */ +#define USBA_EPT_SIZE_OFFSET 0 +#define USBA_EPT_SIZE_SIZE 3 +#define USBA_EPT_DIR_IN (1 << 3) +#define USBA_EPT_TYPE_OFFSET 4 +#define USBA_EPT_TYPE_SIZE 2 +#define USBA_BK_NUMBER_OFFSET 6 +#define USBA_BK_NUMBER_SIZE 2 +#define USBA_NB_TRANS_OFFSET 8 +#define USBA_NB_TRANS_SIZE 2 +#define USBA_EPT_MAPPED (1 << 31) + +/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */ +#define USBA_EPT_ENABLE (1 << 0) +#define USBA_AUTO_VALID (1 << 1) +#define USBA_INTDIS_DMA (1 << 3) +#define USBA_NYET_DIS (1 << 4) +#define USBA_DATAX_RX (1 << 6) +#define USBA_MDATA_RX (1 << 7) +/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */ +#define USBA_BUSY_BANK_IE (1 << 18) + +/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */ +#define USBA_FORCE_STALL (1 << 5) +#define USBA_TOGGLE_CLR (1 << 6) +#define USBA_TOGGLE_SEQ_OFFSET 6 +#define USBA_TOGGLE_SEQ_SIZE 2 +#define USBA_ERR_OVFLW (1 << 8) +#define USBA_RX_BK_RDY (1 << 9) +#define USBA_KILL_BANK (1 << 9) +#define USBA_TX_COMPLETE (1 << 10) +#define USBA_TX_PK_RDY (1 << 11) +#define USBA_ISO_ERR_TRANS (1 << 11) +#define USBA_RX_SETUP (1 << 12) +#define USBA_ISO_ERR_FLOW (1 << 12) +#define USBA_STALL_SENT (1 << 13) +#define USBA_ISO_ERR_CRC (1 << 13) +#define USBA_ISO_ERR_NBTRANS (1 << 13) +#define USBA_NAK_IN (1 << 14) +#define USBA_ISO_ERR_FLUSH (1 << 14) +#define USBA_NAK_OUT (1 << 15) +#define USBA_CURRENT_BANK_OFFSET 16 +#define USBA_CURRENT_BANK_SIZE 2 +#define USBA_BUSY_BANKS_OFFSET 18 +#define USBA_BUSY_BANKS_SIZE 2 +#define USBA_BYTE_COUNT_OFFSET 20 +#define USBA_BYTE_COUNT_SIZE 11 +#define USBA_SHORT_PACKET (1 << 31) + +/* Bitfields in DMA_CONTROL */ +#define USBA_DMA_CH_EN (1 << 0) +#define USBA_DMA_LINK (1 << 1) +#define USBA_DMA_END_TR_EN (1 << 2) +#define USBA_DMA_END_BUF_EN (1 << 3) +#define USBA_DMA_END_TR_IE (1 << 4) +#define USBA_DMA_END_BUF_IE (1 << 5) +#define USBA_DMA_DESC_LOAD_IE (1 << 6) +#define USBA_DMA_BURST_LOCK (1 << 7) +#define USBA_DMA_BUF_LEN_OFFSET 16 +#define USBA_DMA_BUF_LEN_SIZE 16 + +/* Bitfields in DMA_STATUS */ +#define USBA_DMA_CH_ACTIVE (1 << 1) +#define USBA_DMA_END_TR_ST (1 << 4) +#define USBA_DMA_END_BUF_ST (1 << 5) +#define USBA_DMA_DESC_LOAD_ST (1 << 6) + +/* Constants for SPEED_CFG */ +#define USBA_SPEED_CFG_NORMAL 0 +#define USBA_SPEED_CFG_FORCE_HIGH 2 +#define USBA_SPEED_CFG_FORCE_FULL 3 + +/* Constants for EPT_SIZE */ +#define USBA_EPT_SIZE_8 0 +#define USBA_EPT_SIZE_16 1 +#define USBA_EPT_SIZE_32 2 +#define USBA_EPT_SIZE_64 3 +#define USBA_EPT_SIZE_128 4 +#define USBA_EPT_SIZE_256 5 +#define USBA_EPT_SIZE_512 6 +#define USBA_EPT_SIZE_1024 7 + +/* Constants for EPT_TYPE */ +#define USBA_EPT_TYPE_CONTROL 0 +#define USBA_EPT_TYPE_ISO 1 +#define USBA_EPT_TYPE_BULK 2 +#define USBA_EPT_TYPE_INT 3 + +/* Constants for BK_NUMBER */ +#define USBA_BK_NUMBER_ZERO 0 +#define USBA_BK_NUMBER_ONE 1 +#define USBA_BK_NUMBER_DOUBLE 2 +#define USBA_BK_NUMBER_TRIPLE 3 + +/* Bit manipulation macros */ +#define USBA_BF(name, value) \ + (((value) & ((1 << USBA_##name##_SIZE) - 1)) \ + << USBA_##name##_OFFSET) +#define USBA_BFEXT(name, value) \ + (((value) >> USBA_##name##_OFFSET) \ + & ((1 << USBA_##name##_SIZE) - 1)) +#define USBA_BFINS(name, value, old) \ + (((old) & ~(((1 << USBA_##name##_SIZE) - 1) \ + << USBA_##name##_OFFSET)) \ + | USBA_BF(name, value)) + +/* Register access macros */ +#define usba_readl(udc, reg) \ + __raw_readl((udc)->regs + USBA_##reg) +#define usba_writel(udc, reg, value) \ + __raw_writel((value), (udc)->regs + USBA_##reg) +#define usba_ep_readl(ep, reg) \ + __raw_readl((ep)->ep_regs + USBA_EPT_##reg) +#define usba_ep_writel(ep, reg, value) \ + __raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg) +#define usba_dma_readl(ep, reg) \ + __raw_readl((ep)->dma_regs + USBA_DMA_##reg) +#define usba_dma_writel(ep, reg, value) \ + __raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg) + +/* Calculate base address for a given endpoint or DMA controller */ +#define USBA_EPT_BASE(x) (0x100 + (x) * 0x20) +#define USBA_DMA_BASE(x) (0x300 + (x) * 0x10) +#define USBA_FIFO_BASE(x) ((x) << 16) + +/* Synth parameters */ +#define USBA_NR_ENDPOINTS 7 + +#define EP0_FIFO_SIZE 64 +#define EP0_EPT_SIZE USBA_EPT_SIZE_64 +#define EP0_NR_BANKS 1 + +#define DBG_ERR 0x0001 /* report all error returns */ +#define DBG_HW 0x0002 /* debug hardware initialization */ +#define DBG_GADGET 0x0004 /* calls to/from gadget driver */ +#define DBG_INT 0x0008 /* interrupts */ +#define DBG_BUS 0x0010 /* report changes in bus state */ +#define DBG_QUEUE 0x0020 /* debug request queue processing */ +#define DBG_FIFO 0x0040 /* debug FIFO contents */ +#define DBG_DMA 0x0080 /* debug DMA handling */ +#define DBG_REQ 0x0100 /* print out queued request length */ +#define DBG_ALL 0xffff +#define DBG_NONE 0x0000 + +#define DEBUG_LEVEL (DBG_ERR) + +#define DBG(level, fmt, ...) \ + do { \ + if ((level) & DEBUG_LEVEL) \ + debug("udc: " fmt, ## __VA_ARGS__); \ + } while (0) + +enum usba_ctrl_state { + WAIT_FOR_SETUP, + DATA_STAGE_IN, + DATA_STAGE_OUT, + STATUS_STAGE_IN, + STATUS_STAGE_OUT, + STATUS_STAGE_ADDR, + STATUS_STAGE_TEST, +}; + +struct usba_dma_desc { + dma_addr_t next; + dma_addr_t addr; + u32 ctrl; +}; + +struct usba_ep { + int state; + void *ep_regs; + void *dma_regs; + void *fifo; + struct usb_ep ep; + struct usba_udc *udc; + + struct list_head queue; + + u16 fifo_size; + u8 nr_banks; + u8 index; + unsigned int can_dma:1; + unsigned int can_isoc:1; + unsigned int is_isoc:1; + unsigned int is_in:1; + + const struct usb_endpoint_descriptor *desc; +}; + +struct usba_request { + struct usb_request req; + struct list_head queue; + + u32 ctrl; + + unsigned int submitted:1; + unsigned int last_transaction:1; + unsigned int using_dma:1; + unsigned int mapped:1; +}; + +struct usba_udc { + void *regs; + void *fifo; + + struct usb_gadget gadget; + struct usb_gadget_driver *driver; + struct platform_device *pdev; + int irq; + int vbus_pin; + int vbus_pin_inverted; + int num_ep; + struct usba_ep *usba_ep; + + u16 devstatus; + + u16 test_mode; + int vbus_prev; +}; + +static inline struct usba_ep *to_usba_ep(struct usb_ep *ep) +{ + return container_of(ep, struct usba_ep, ep); +} + +static inline struct usba_request *to_usba_req(struct usb_request *req) +{ + return container_of(req, struct usba_request, req); +} + +static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget) +{ + return container_of(gadget, struct usba_udc, gadget); +} + +#define ep_is_control(ep) ((ep)->index == 0) +#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE) + +#endif /* __LINUX_USB_GADGET_USBA_UDC_H */ diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c new file mode 100644 index 0000000000..b0ef35e745 --- /dev/null +++ b/drivers/usb/gadget/ci_udc.c @@ -0,0 +1,933 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../host/ehci.h" +#include "ci_udc.h" + +/* + * Check if the system has too long cachelines. If the cachelines are + * longer then 128b, the driver will not be able flush/invalidate data + * cache over separate QH entries. We use 128b because one QH entry is + * 64b long and there are always two QH list entries for each endpoint. + */ +#if ARCH_DMA_MINALIGN > 128 +#error This driver can not work on systems with caches longer than 128b +#endif + +/* + * Every QTD must be individually aligned, since we can program any + * QTD's address into HW. Cache flushing requires ARCH_DMA_MINALIGN, + * and the USB HW requires 32-byte alignment. Align to both: + */ +#define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32) +/* Each QTD is this size */ +#define ILIST_ENT_RAW_SZ sizeof(struct ept_queue_item) +/* + * Align the size of the QTD too, so we can add this value to each + * QTD's address to get another aligned address. + */ +#define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ILIST_ALIGN) +/* For each endpoint, we need 2 QTDs, one for each of IN and OUT */ +#define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ) + +#ifndef DEBUG +#define DBG(x...) do {} while (0) +#else +#define DBG(x...) printf(x) +static const char *reqname(unsigned r) +{ + switch (r) { + case USB_REQ_GET_STATUS: return "GET_STATUS"; + case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE"; + case USB_REQ_SET_FEATURE: return "SET_FEATURE"; + case USB_REQ_SET_ADDRESS: return "SET_ADDRESS"; + case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR"; + case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR"; + case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION"; + case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION"; + case USB_REQ_GET_INTERFACE: return "GET_INTERFACE"; + case USB_REQ_SET_INTERFACE: return "SET_INTERFACE"; + default: return "*UNKNOWN*"; + } +} +#endif + +static struct usb_endpoint_descriptor ep0_desc = { + .bLength = sizeof(struct usb_endpoint_descriptor), + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, +}; + +static int ci_pullup(struct usb_gadget *gadget, int is_on); +static int ci_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc); +static int ci_ep_disable(struct usb_ep *ep); +static int ci_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags); +static struct usb_request * +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); + +static struct usb_gadget_ops ci_udc_ops = { + .pullup = ci_pullup, +}; + +static struct usb_ep_ops ci_ep_ops = { + .enable = ci_ep_enable, + .disable = ci_ep_disable, + .queue = ci_ep_queue, + .alloc_request = ci_ep_alloc_request, + .free_request = ci_ep_free_request, +}; + +/* Init values for USB endpoints. */ +static const struct usb_ep ci_ep_init[2] = { + [0] = { /* EP 0 */ + .maxpacket = 64, + .name = "ep0", + .ops = &ci_ep_ops, + }, + [1] = { /* EP 1..n */ + .maxpacket = 512, + .name = "ep-", + .ops = &ci_ep_ops, + }, +}; + +static struct ci_drv controller = { + .gadget = { + .name = "ci_udc", + .ops = &ci_udc_ops, + .is_dualspeed = 1, + }, +}; + +/** + * ci_get_qh() - return queue head for endpoint + * @ep_num: Endpoint number + * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) + * + * This function returns the QH associated with particular endpoint + * and it's direction. + */ +static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in) +{ + return &controller.epts[(ep_num * 2) + dir_in]; +} + +/** + * ci_get_qtd() - return queue item for endpoint + * @ep_num: Endpoint number + * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) + * + * This function returns the QH associated with particular endpoint + * and it's direction. + */ +static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in) +{ + int index = (ep_num * 2) + dir_in; + uint8_t *imem = controller.items_mem + (index * ILIST_ENT_SZ); + return (struct ept_queue_item *)imem; +} + +/** + * ci_flush_qh - flush cache over queue head + * @ep_num: Endpoint number + * + * This function flushes cache over QH for particular endpoint. + */ +static void ci_flush_qh(int ep_num) +{ + struct ept_queue_head *head = ci_get_qh(ep_num, 0); + const uint32_t start = (uint32_t)head; + const uint32_t end = start + 2 * sizeof(*head); + + flush_dcache_range(start, end); +} + +/** + * ci_invalidate_qh - invalidate cache over queue head + * @ep_num: Endpoint number + * + * This function invalidates cache over QH for particular endpoint. + */ +static void ci_invalidate_qh(int ep_num) +{ + struct ept_queue_head *head = ci_get_qh(ep_num, 0); + uint32_t start = (uint32_t)head; + uint32_t end = start + 2 * sizeof(*head); + + invalidate_dcache_range(start, end); +} + +/** + * ci_flush_qtd - flush cache over queue item + * @ep_num: Endpoint number + * + * This function flushes cache over qTD pair for particular endpoint. + */ +static void ci_flush_qtd(int ep_num) +{ + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); + const uint32_t start = (uint32_t)item; + const uint32_t end = start + 2 * ILIST_ENT_SZ; + + flush_dcache_range(start, end); +} + +/** + * ci_invalidate_qtd - invalidate cache over queue item + * @ep_num: Endpoint number + * + * This function invalidates cache over qTD pair for particular endpoint. + */ +static void ci_invalidate_qtd(int ep_num) +{ + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); + const uint32_t start = (uint32_t)item; + const uint32_t end = start + 2 * ILIST_ENT_SZ; + + invalidate_dcache_range(start, end); +} + +static struct usb_request * +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + int num; + struct ci_req *ci_req; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + if (num == 0 && controller.ep0_req) + return &controller.ep0_req->req; + + ci_req = calloc(1, sizeof(*ci_req)); + if (!ci_req) + return NULL; + + INIT_LIST_HEAD(&ci_req->queue); + + if (num == 0) + controller.ep0_req = ci_req; + + return &ci_req->req; +} + +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_req *ci_req = container_of(req, struct ci_req, req); + int num; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + if (num == 0) { + if (!controller.ep0_req) + return; + controller.ep0_req = 0; + } + + if (ci_req->b_buf) + free(ci_req->b_buf); + free(ci_req); +} + +static void ep_enable(int num, int in, int maxpacket) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + unsigned n; + + n = readl(&udc->epctrl[num]); + if (in) + n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK); + else + n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); + + if (num != 0) { + struct ept_queue_head *head = ci_get_qh(num, in); + + head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; + ci_flush_qh(num); + } + writel(n, &udc->epctrl[num]); +} + +static int ci_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + int num, in; + num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (desc->bEndpointAddress & USB_DIR_IN) != 0; + ci_ep->desc = desc; + + if (num) { + int max = get_unaligned_le16(&desc->wMaxPacketSize); + + if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL)) + max = 64; + if (ep->maxpacket != max) { + DBG("%s: from %d to %d\n", __func__, + ep->maxpacket, max); + ep->maxpacket = max; + } + } + ep_enable(num, in, ep->maxpacket); + DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket); + return 0; +} + +static int ci_ep_disable(struct usb_ep *ep) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + + ci_ep->desc = NULL; + return 0; +} + +static int ci_bounce(struct ci_req *ci_req, int in) +{ + struct usb_request *req = &ci_req->req; + uint32_t addr = (uint32_t)req->buf; + uint32_t hwaddr; + uint32_t aligned_used_len; + + /* Input buffer address is not aligned. */ + if (addr & (ARCH_DMA_MINALIGN - 1)) + goto align; + + /* Input buffer length is not aligned. */ + if (req->length & (ARCH_DMA_MINALIGN - 1)) + goto align; + + /* The buffer is well aligned, only flush cache. */ + ci_req->hw_len = req->length; + ci_req->hw_buf = req->buf; + goto flush; + +align: + if (ci_req->b_buf && req->length > ci_req->b_len) { + free(ci_req->b_buf); + ci_req->b_buf = 0; + } + if (!ci_req->b_buf) { + ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN); + ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len); + if (!ci_req->b_buf) + return -ENOMEM; + } + ci_req->hw_len = ci_req->b_len; + ci_req->hw_buf = ci_req->b_buf; + + if (in) + memcpy(ci_req->hw_buf, req->buf, req->length); + +flush: + hwaddr = (uint32_t)ci_req->hw_buf; + aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN); + flush_dcache_range(hwaddr, hwaddr + aligned_used_len); + + return 0; +} + +static void ci_debounce(struct ci_req *ci_req, int in) +{ + struct usb_request *req = &ci_req->req; + uint32_t addr = (uint32_t)req->buf; + uint32_t hwaddr = (uint32_t)ci_req->hw_buf; + uint32_t aligned_used_len; + + if (in) + return; + + aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN); + invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len); + + if (addr == hwaddr) + return; /* not a bounce */ + + memcpy(req->buf, ci_req->hw_buf, req->actual); +} + +static void ci_ep_submit_next_request(struct ci_ep *ci_ep) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + struct ept_queue_item *item; + struct ept_queue_head *head; + int bit, num, len, in; + struct ci_req *ci_req; + + ci_ep->req_primed = true; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + item = ci_get_qtd(num, in); + head = ci_get_qh(num, in); + + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); + len = ci_req->req.length; + + item->info = INFO_BYTES(len) | INFO_ACTIVE; + item->page0 = (uint32_t)ci_req->hw_buf; + item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000; + item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000; + item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000; + item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000; + + head->next = (unsigned) item; + head->info = 0; + + /* + * When sending the data for an IN transaction, the attached host + * knows that all data for the IN is sent when one of the following + * occurs: + * a) A zero-length packet is transmitted. + * b) A packet with length that isn't an exact multiple of the ep's + * maxpacket is transmitted. + * c) Enough data is sent to exactly fill the host's maximum expected + * IN transaction size. + * + * One of these conditions MUST apply at the end of an IN transaction, + * or the transaction will not be considered complete by the host. If + * none of (a)..(c) already applies, then we must force (a) to apply + * by explicitly sending an extra zero-length packet. + */ + /* IN !a !b !c */ + if (in && len && !(len % ci_ep->ep.maxpacket) && ci_req->req.zero) { + /* + * Each endpoint has 2 items allocated, even though typically + * only 1 is used at a time since either an IN or an OUT but + * not both is queued. For an IN transaction, item currently + * points at the second of these items, so we know that we + * can use the other to transmit the extra zero-length packet. + */ + struct ept_queue_item *other_item = ci_get_qtd(num, 0); + item->next = (unsigned)other_item; + item = other_item; + item->info = INFO_ACTIVE; + } + + item->next = TERMINATE; + item->info |= INFO_IOC; + + ci_flush_qtd(num); + + DBG("ept%d %s queue len %x, req %p, buffer %p\n", + num, in ? "in" : "out", len, ci_req, ci_req->hw_buf); + ci_flush_qh(num); + + if (in) + bit = EPT_TX(num); + else + bit = EPT_RX(num); + + writel(bit, &udc->epprime); +} + +static int ci_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_req *ci_req = container_of(req, struct ci_req, req); + int in, ret; + int __maybe_unused num; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + + if (!num && ci_ep->req_primed) { + /* + * The flipping of ep0 between IN and OUT relies on + * ci_ep_queue consuming the current IN/OUT setting + * immediately. If this is deferred to a later point when the + * req is pulled out of ci_req->queue, then the IN/OUT setting + * may have been changed since the req was queued, and state + * will get out of sync. This condition doesn't occur today, + * but could if bugs were introduced later, and this error + * check will save a lot of debugging time. + */ + printf("%s: ep0 transaction already in progress\n", __func__); + return -EPROTO; + } + + ret = ci_bounce(ci_req, in); + if (ret) + return ret; + + DBG("ept%d %s pre-queue req %p, buffer %p\n", + num, in ? "in" : "out", ci_req, ci_req->hw_buf); + list_add_tail(&ci_req->queue, &ci_ep->queue); + + if (!ci_ep->req_primed) + ci_ep_submit_next_request(ci_ep); + + return 0; +} + +static void flip_ep0_direction(void) +{ + if (ep0_desc.bEndpointAddress == USB_DIR_IN) { + DBG("%s: Flipping ep0 to OUT\n", __func__); + ep0_desc.bEndpointAddress = 0; + } else { + DBG("%s: Flipping ep0 to IN\n", __func__); + ep0_desc.bEndpointAddress = USB_DIR_IN; + } +} + +static void handle_ep_complete(struct ci_ep *ci_ep) +{ + struct ept_queue_item *item; + int num, in, len; + struct ci_req *ci_req; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + item = ci_get_qtd(num, in); + ci_invalidate_qtd(num); + + len = (item->info >> 16) & 0x7fff; + if (item->info & 0xff) + printf("EP%d/%s FAIL info=%x pg0=%x\n", + num, in ? "in" : "out", item->info, item->page0); + + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); + list_del_init(&ci_req->queue); + ci_ep->req_primed = false; + + if (!list_empty(&ci_ep->queue)) + ci_ep_submit_next_request(ci_ep); + + ci_req->req.actual = ci_req->req.length - len; + ci_debounce(ci_req, in); + + DBG("ept%d %s req %p, complete %x\n", + num, in ? "in" : "out", ci_req, len); + if (num != 0 || controller.ep0_data_phase) + ci_req->req.complete(&ci_ep->ep, &ci_req->req); + if (num == 0 && controller.ep0_data_phase) { + /* + * Data Stage is complete, so flip ep0 dir for Status Stage, + * which always transfers a packet in the opposite direction. + */ + DBG("%s: flip ep0 dir for Status Stage\n", __func__); + flip_ep0_direction(); + controller.ep0_data_phase = false; + ci_req->req.length = 0; + usb_ep_queue(&ci_ep->ep, &ci_req->req, 0); + } +} + +#define SETUP(type, request) (((type) << 8) | (request)) + +static void handle_setup(void) +{ + struct ci_ep *ci_ep = &controller.ep[0]; + struct ci_req *ci_req; + struct usb_request *req; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + struct ept_queue_head *head; + struct usb_ctrlrequest r; + int status = 0; + int num, in, _num, _in, i; + char *buf; + + ci_req = controller.ep0_req; + req = &ci_req->req; + head = ci_get_qh(0, 0); /* EP0 OUT */ + + ci_invalidate_qh(0); + memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); +#ifdef CONFIG_CI_UDC_HAS_HOSTPC + writel(EPT_RX(0), &udc->epsetupstat); +#else + writel(EPT_RX(0), &udc->epstat); +#endif + DBG("handle setup %s, %x, %x index %x value %x length %x\n", + reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex, + r.wValue, r.wLength); + + /* Set EP0 dir for Data Stage based on Setup Stage data */ + if (r.bRequestType & USB_DIR_IN) { + DBG("%s: Set ep0 to IN for Data Stage\n", __func__); + ep0_desc.bEndpointAddress = USB_DIR_IN; + } else { + DBG("%s: Set ep0 to OUT for Data Stage\n", __func__); + ep0_desc.bEndpointAddress = 0; + } + if (r.wLength) { + controller.ep0_data_phase = true; + } else { + /* 0 length -> no Data Stage. Flip dir for Status Stage */ + DBG("%s: 0 length: flip ep0 dir for Status Stage\n", __func__); + flip_ep0_direction(); + controller.ep0_data_phase = false; + } + + list_del_init(&ci_req->queue); + ci_ep->req_primed = false; + + switch (SETUP(r.bRequestType, r.bRequest)) { + case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): + _num = r.wIndex & 15; + _in = !!(r.wIndex & 0x80); + + if ((r.wValue == 0) && (r.wLength == 0)) { + req->length = 0; + for (i = 0; i < NUM_ENDPOINTS; i++) { + struct ci_ep *ep = &controller.ep[i]; + + if (!ep->desc) + continue; + num = ep->desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (ep->desc->bEndpointAddress + & USB_DIR_IN) != 0; + if ((num == _num) && (in == _in)) { + ep_enable(num, in, ep->ep.maxpacket); + usb_ep_queue(controller.gadget.ep0, + req, 0); + break; + } + } + } + return; + + case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): + /* + * write address delayed (will take effect + * after the next IN txn) + */ + writel((r.wValue << 25) | (1 << 24), &udc->devaddr); + req->length = 0; + usb_ep_queue(controller.gadget.ep0, req, 0); + return; + + case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS): + req->length = 2; + buf = (char *)req->buf; + buf[0] = 1 << USB_DEVICE_SELF_POWERED; + buf[1] = 0; + usb_ep_queue(controller.gadget.ep0, req, 0); + return; + } + /* pass request up to the gadget driver */ + if (controller.driver) + status = controller.driver->setup(&controller.gadget, &r); + else + status = -ENODEV; + + if (!status) + return; + DBG("STALL reqname %s type %x value %x, index %x\n", + reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); + writel((1<<16) | (1 << 0), &udc->epctrl[0]); +} + +static void stop_activity(void) +{ + int i, num, in; + struct ept_queue_head *head; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + writel(readl(&udc->epcomp), &udc->epcomp); +#ifdef CONFIG_CI_UDC_HAS_HOSTPC + writel(readl(&udc->epsetupstat), &udc->epsetupstat); +#endif + writel(readl(&udc->epstat), &udc->epstat); + writel(0xffffffff, &udc->epflush); + + /* error out any pending reqs */ + for (i = 0; i < NUM_ENDPOINTS; i++) { + if (i != 0) + writel(0, &udc->epctrl[i]); + if (controller.ep[i].desc) { + num = controller.ep[i].desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (controller.ep[i].desc->bEndpointAddress + & USB_DIR_IN) != 0; + head = ci_get_qh(num, in); + head->info = INFO_ACTIVE; + ci_flush_qh(num); + } + } +} + +void udc_irq(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + unsigned n = readl(&udc->usbsts); + writel(n, &udc->usbsts); + int bit, i, num, in; + + n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); + if (n == 0) + return; + + if (n & STS_URI) { + DBG("-- reset --\n"); + stop_activity(); + } + if (n & STS_SLI) + DBG("-- suspend --\n"); + + if (n & STS_PCI) { + int max = 64; + int speed = USB_SPEED_FULL; + +#ifdef CONFIG_CI_UDC_HAS_HOSTPC + bit = (readl(&udc->hostpc1_devlc) >> 25) & 3; +#else + bit = (readl(&udc->portsc) >> 26) & 3; +#endif + DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full"); + if (bit == 2) { + speed = USB_SPEED_HIGH; + max = 512; + } + controller.gadget.speed = speed; + for (i = 1; i < NUM_ENDPOINTS; i++) { + if (controller.ep[i].ep.maxpacket > max) + controller.ep[i].ep.maxpacket = max; + } + } + + if (n & STS_UEI) + printf("\n", readl(&udc->epcomp)); + + if ((n & STS_UI) || (n & STS_UEI)) { +#ifdef CONFIG_CI_UDC_HAS_HOSTPC + n = readl(&udc->epsetupstat); +#else + n = readl(&udc->epstat); +#endif + if (n & EPT_RX(0)) + handle_setup(); + + n = readl(&udc->epcomp); + if (n != 0) + writel(n, &udc->epcomp); + + for (i = 0; i < NUM_ENDPOINTS && n; i++) { + if (controller.ep[i].desc) { + num = controller.ep[i].desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (controller.ep[i].desc->bEndpointAddress + & USB_DIR_IN) != 0; + bit = (in) ? EPT_TX(num) : EPT_RX(num); + if (n & bit) + handle_ep_complete(&controller.ep[i]); + } + } + } +} + +int usb_gadget_handle_interrupts(void) +{ + u32 value; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + value = readl(&udc->usbsts); + if (value) + udc_irq(); + + return value; +} + +void udc_disconnect(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + /* disable pullup */ + stop_activity(); + writel(USBCMD_FS2, &udc->usbcmd); + udelay(800); + if (controller.driver) + controller.driver->disconnect(&controller.gadget); +} + +static int ci_pullup(struct usb_gadget *gadget, int is_on) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + if (is_on) { + /* RESET */ + writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); + udelay(200); + + writel((unsigned)controller.epts, &udc->epinitaddr); + + /* select DEVICE mode */ + writel(USBMODE_DEVICE, &udc->usbmode); + +#if !defined(CONFIG_USB_GADGET_DUALSPEED) + /* Port force Full-Speed Connect */ + setbits_le32(&udc->portsc, PFSC); +#endif + + writel(0xffffffff, &udc->epflush); + + /* Turn on the USB connection by enabling the pullup resistor */ + writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); + } else { + udc_disconnect(); + } + + return 0; +} + +static int ci_udc_probe(void) +{ + struct ept_queue_head *head; + int i; + + const int num = 2 * NUM_ENDPOINTS; + + const int eplist_min_align = 4096; + const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); + const int eplist_raw_sz = num * sizeof(struct ept_queue_head); + const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); + + /* The QH list must be aligned to 4096 bytes. */ + controller.epts = memalign(eplist_align, eplist_sz); + if (!controller.epts) + return -ENOMEM; + memset(controller.epts, 0, eplist_sz); + + controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ); + if (!controller.items_mem) { + free(controller.epts); + return -ENOMEM; + } + memset(controller.items_mem, 0, ILIST_SZ); + + for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { + /* + * Configure QH for each endpoint. The structure of the QH list + * is such that each two subsequent fields, N and N+1 where N is + * even, in the QH list represent QH for one endpoint. The Nth + * entry represents OUT configuration and the N+1th entry does + * represent IN configuration of the endpoint. + */ + head = controller.epts + i; + if (i < 2) + head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) + | CONFIG_ZLT | CONFIG_IOS; + else + head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) + | CONFIG_ZLT; + head->next = TERMINATE; + head->info = 0; + + if (i & 1) { + ci_flush_qh(i / 2); + ci_flush_qtd(i / 2); + } + } + + INIT_LIST_HEAD(&controller.gadget.ep_list); + + /* Init EP 0 */ + memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); + controller.ep[0].desc = &ep0_desc; + INIT_LIST_HEAD(&controller.ep[0].queue); + controller.ep[0].req_primed = false; + controller.gadget.ep0 = &controller.ep[0].ep; + INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); + + /* Init EP 1..n */ + for (i = 1; i < NUM_ENDPOINTS; i++) { + memcpy(&controller.ep[i].ep, &ci_ep_init[1], + sizeof(*ci_ep_init)); + INIT_LIST_HEAD(&controller.ep[i].queue); + controller.ep[i].req_primed = false; + list_add_tail(&controller.ep[i].ep.ep_list, + &controller.gadget.ep_list); + } + + ci_ep_alloc_request(&controller.ep[0].ep, 0); + if (!controller.ep0_req) { + free(controller.items_mem); + free(controller.epts); + return -ENOMEM; + } + + return 0; +} + +int usb_gadget_register_driver(struct usb_gadget_driver *driver) +{ + int ret; + + if (!driver) + return -EINVAL; + if (!driver->bind || !driver->setup || !driver->disconnect) + return -EINVAL; + if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) + return -EINVAL; + + ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl); + if (ret) + return ret; + + ret = ci_udc_probe(); +#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS) + /* + * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all + * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection + */ + if (!ret) { + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + /* select ULPI phy */ + writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); + } +#endif + + ret = driver->bind(&controller.gadget); + if (ret) { + DBG("driver->bind() returned %d\n", ret); + return ret; + } + controller.driver = driver; + + return 0; +} + +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) +{ + udc_disconnect(); + + driver->unbind(&controller.gadget); + controller.driver = NULL; + + ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req); + free(controller.items_mem); + free(controller.epts); + + return 0; +} + +bool dfu_usb_get_reset(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + return !!(readl(&udc->usbsts) & STS_URI); +} diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h new file mode 100644 index 0000000000..346164a641 --- /dev/null +++ b/drivers/usb/gadget/ci_udc.h @@ -0,0 +1,152 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * + * Licensed under the GPL-2 or later. + */ +#ifndef __GADGET__CI_UDC_H__ +#define __GADGET__CI_UDC_H__ + +#define NUM_ENDPOINTS 6 + +#ifdef CONFIG_CI_UDC_HAS_HOSTPC +struct ci_udc { + u32 usbcmd; /* 0x130 */ + u32 usbsts; /* 0x134 */ + u32 pad1[3]; + u32 devaddr; /* 0x144 */ + u32 epinitaddr; /* 0x148 */ + u32 pad2[10]; + u32 portsc; /* 0x174 */ + u32 pad178[(0x1b4 - (0x174 + 4)) / 4]; + u32 hostpc1_devlc; /* 0x1b4 */ + u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4]; + u32 usbmode; /* 0x1f8 */ + u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4]; + u32 epsetupstat; /* 0x208 */ + u32 epprime; /* 0x20c */ + u32 epflush; /* 0x210 */ + u32 epstat; /* 0x214 */ + u32 epcomp; /* 0x218 */ + u32 epctrl[16]; /* 0x21c */ +}; +#else +struct ci_udc { + u32 usbcmd; /* 0x140 */ + u32 usbsts; /* 0x144 */ + u32 pad1[3]; + u32 devaddr; /* 0x154 */ + u32 epinitaddr; /* 0x158 */ + u32 pad2[10]; + u32 portsc; /* 0x184 */ + u32 pad3[8]; + u32 usbmode; /* 0x1a8 */ + u32 epstat; /* 0x1ac */ + u32 epprime; /* 0x1b0 */ + u32 epflush; /* 0x1b4 */ + u32 pad4; + u32 epcomp; /* 0x1bc */ + u32 epctrl[16]; /* 0x1c0 */ +}; + +#define PTS_ENABLE 2 +#define PTS(x) (((x) & 0x3) << 30) +#define PFSC (1 << 24) +#endif + +#define MICRO_8FRAME 0x8 +#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) +#define USBCMD_FS2 (1 << 15) +#define USBCMD_RST (1 << 1) +#define USBCMD_RUN (1) + +#define STS_SLI (1 << 8) +#define STS_URI (1 << 6) +#define STS_PCI (1 << 2) +#define STS_UEI (1 << 1) +#define STS_UI (1 << 0) + +#define USBMODE_DEVICE 2 + +#define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) +#define EPT_RX(x) (1 << ((x) & 0xffff)) + +#define CTRL_TXE (1 << 23) +#define CTRL_TXR (1 << 22) +#define CTRL_RXE (1 << 7) +#define CTRL_RXR (1 << 6) +#define CTRL_TXT_BULK (2 << 18) +#define CTRL_RXT_BULK (2 << 2) + +struct ci_req { + struct usb_request req; + struct list_head queue; + /* Bounce buffer allocated if needed to align the transfer */ + uint8_t *b_buf; + uint32_t b_len; + /* Buffer for the current transfer. Either req.buf/len or b_buf/len */ + uint8_t *hw_buf; + uint32_t hw_len; +}; + +struct ci_ep { + struct usb_ep ep; + struct list_head queue; + bool req_primed; + const struct usb_endpoint_descriptor *desc; +}; + +struct ci_drv { + struct usb_gadget gadget; + struct ci_req *ep0_req; + bool ep0_data_phase; + struct usb_gadget_driver *driver; + struct ehci_ctrl *ctrl; + struct ept_queue_head *epts; + uint8_t *items_mem; + struct ci_ep ep[NUM_ENDPOINTS]; +}; + +struct ept_queue_head { + unsigned config; + unsigned current; /* read-only */ + + unsigned next; + unsigned info; + unsigned page0; + unsigned page1; + unsigned page2; + unsigned page3; + unsigned page4; + unsigned reserved_0; + + unsigned char setup_data[8]; + + unsigned reserved_1; + unsigned reserved_2; + unsigned reserved_3; + unsigned reserved_4; +}; + +#define CONFIG_MAX_PKT(n) ((n) << 16) +#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ +#define CONFIG_IOS (1 << 15) /* IRQ on setup */ + +struct ept_queue_item { + unsigned next; + unsigned info; + unsigned page0; + unsigned page1; + unsigned page2; + unsigned page3; + unsigned page4; + unsigned reserved; +}; + +#define TERMINATE 1 +#define INFO_BYTES(n) ((n) << 16) +#define INFO_IOC (1 << 15) +#define INFO_ACTIVE (1 << 7) +#define INFO_HALTED (1 << 6) +#define INFO_BUFFER_ERROR (1 << 5) +#define INFO_TX_ERROR (1 << 3) +#endif diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index 7bd25629c8..98c2da6f14 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -743,8 +743,8 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) if (!gadget_is_dualspeed(gadget)) break; device_qual(cdev); - value = min(w_length, - sizeof(struct usb_qualifier_descriptor)); + value = min_t(int, w_length, + sizeof(struct usb_qualifier_descriptor)); break; case USB_DT_OTHER_SPEED_CONFIG: if (!gadget_is_dualspeed(gadget)) @@ -761,6 +761,14 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) if (value >= 0) value = min(w_length, (u16) value); break; + case USB_DT_BOS: + /* + * The USB compliance test (USB 2.0 Command Verifier) + * issues this request. We should not run into the + * default path here. But return for now until + * the superspeed support is added. + */ + break; default: goto unknown; } diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c index f563afe787..014a6791c1 100644 --- a/drivers/usb/gadget/config.c +++ b/drivers/usb/gadget/config.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -86,7 +87,8 @@ int usb_gadget_config_buf( /* config descriptor first */ if (length < USB_DT_CONFIG_SIZE || !desc) return -EINVAL; - *cp = *config; + /* config need not be aligned */ + memcpy(cp, config, sizeof(*cp)); /* then interface/endpoint/class/vendor/... */ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8 *)buf, @@ -100,7 +102,7 @@ int usb_gadget_config_buf( /* patch up the config descriptor */ cp->bLength = USB_DT_CONFIG_SIZE; cp->bDescriptorType = USB_DT_CONFIG; - cp->wTotalLength = cpu_to_le16(len); + put_unaligned_le16(len, &cp->wTotalLength); cp->bmAttributes |= USB_CONFIG_ATT_ONE; return len; } diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c index 1aab31bbae..0db7a3b6c1 100644 --- a/drivers/usb/gadget/designware_udc.c +++ b/drivers/usb/gadget/designware_udc.c @@ -14,6 +14,7 @@ #include #include "ep0.h" #include +#include #include #define UDC_INIT_MDELAY 80 /* Device settle delay */ @@ -268,8 +269,8 @@ static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d", urb->buffer, urb->buffer_length, urb->actual_length); - last = MIN(urb->actual_length - endpoint->sent, - endpoint->tx_packetSize); + last = min_t(u32, urb->actual_length - endpoint->sent, + endpoint->tx_packetSize); if (last) { u8 *cp = urb->buffer + endpoint->sent; @@ -284,7 +285,7 @@ static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance align = ((ulong)cp % sizeof(int)); if (align) - last = MIN(last, sizeof(int) - align); + last = min(last, sizeof(int) - align); UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d", endpoint->sent, endpoint->tx_packetSize, last); diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c index b3214882f7..4ba2f3d99f 100644 --- a/drivers/usb/gadget/ep0.c +++ b/drivers/usb/gadget/ep0.c @@ -315,7 +315,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device, /*copy_config(urb, &report_descriptor->bData[0], report_descriptor->wLength, max); */ if (max - urb->actual_length > 0) { int length = - MIN (report_descriptor->wLength, + min(report_descriptor->wLength, max - urb->actual_length); memcpy (urb->buffer + urb->actual_length, &report_descriptor->bData[0], length); diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 579893cbff..ba442d5ed5 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -25,15 +25,10 @@ #define atomic_read extern struct platform_data brd; -#define spin_lock(x) -#define spin_unlock(x) unsigned packet_received, packet_sent; -#define GFP_ATOMIC ((gfp_t) 0) -#define GFP_KERNEL ((gfp_t) 0) - /* * Ethernet gadget driver -- with CDC and non-CDC options * Builds on hardware support for a full duplex link. @@ -635,6 +630,7 @@ fs_source_desc = { .bEndpointAddress = USB_DIR_IN, .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(64), }; static struct usb_endpoint_descriptor @@ -644,6 +640,7 @@ fs_sink_desc = { .bEndpointAddress = USB_DIR_OUT, .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(64), }; static const struct usb_descriptor_header *fs_eth_function[11] = { @@ -849,35 +846,12 @@ static struct usb_gadget_strings stringtab = { }; /*============================================================================*/ -static u8 control_req[USB_BUFSIZ]; +DEFINE_CACHE_ALIGN_BUFFER(u8, control_req, USB_BUFSIZ); + #if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS) -static u8 status_req[STATUS_BYTECOUNT] __attribute__ ((aligned(4))); +DEFINE_CACHE_ALIGN_BUFFER(u8, status_req, STATUS_BYTECOUNT); #endif - -/** - * strlcpy - Copy a %NUL terminated string into a sized buffer - * @dest: Where to copy the string to - * @src: Where to copy the string from - * @size: size of destination buffer - * - * Compatible with *BSD: the result is always a valid - * NUL-terminated string that fits in the buffer (unless, - * of course, the buffer size is zero). It does not pad - * out the result like strncpy() does. - */ -size_t strlcpy(char *dest, const char *src, size_t size) -{ - size_t ret = strlen(src); - - if (size) { - size_t len = (ret >= size) ? size - 1 : ret; - memcpy(dest, src, len); - dest[len] = '\0'; - } - return ret; -} - /*============================================================================*/ /* @@ -1533,6 +1507,8 @@ static int rx_submit(struct eth_dev *dev, struct usb_request *req, */ debug("%s\n", __func__); + if (!req) + return -EINVAL; size = (ETHER_HDR_SIZE + dev->mtu + RX_EXTRA); size += dev->out_ep->maxpacket - 1; diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 37d04a1928..77a1567a94 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -24,6 +24,7 @@ #include #include +#include #include "f_dfu.h" struct f_dfu { @@ -40,6 +41,7 @@ struct f_dfu { /* Send/received block number is handy for data integrity check */ int blk_seq_num; + unsigned int poll_timeout; }; typedef int (*dfu_state_fn) (struct f_dfu *, @@ -79,14 +81,6 @@ static struct usb_descriptor_header *dfu_runtime_descs[] = { NULL, }; -static const struct usb_qualifier_descriptor dev_qualifier = { - .bLength = sizeof dev_qualifier, - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - .bcdUSB = __constant_cpu_to_le16(0x0200), - .bDeviceClass = USB_CLASS_VENDOR_SPEC, - .bNumConfigurations = 1, -}; - static const char dfu_name[] = "Device Firmware Upgrade"; /* @@ -128,23 +122,74 @@ static struct usb_gadget_strings *dfu_strings[] = { NULL, }; +static void dfu_set_poll_timeout(struct dfu_status *dstat, unsigned int ms) +{ + /* + * The bwPollTimeout DFU_GETSTATUS request payload provides information + * about minimum time, in milliseconds, that the host should wait before + * sending a subsequent DFU_GETSTATUS request + * + * This permits the device to vary the delay depending on its need to + * erase or program the memory + * + */ + + unsigned char *p = (unsigned char *)&ms; + + if (!ms || (ms & ~DFU_POLL_TIMEOUT_MASK)) { + dstat->bwPollTimeout[0] = 0; + dstat->bwPollTimeout[1] = 0; + dstat->bwPollTimeout[2] = 0; + + return; + } + + dstat->bwPollTimeout[0] = *p++; + dstat->bwPollTimeout[1] = *p++; + dstat->bwPollTimeout[2] = *p; +} + /*-------------------------------------------------------------------------*/ static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req) { struct f_dfu *f_dfu = req->context; + int ret; + + ret = dfu_write(dfu_get_entity(f_dfu->altsetting), req->buf, + req->length, f_dfu->blk_seq_num); + if (ret) { + f_dfu->dfu_status = DFU_STATUS_errUNKNOWN; + f_dfu->dfu_state = DFU_STATE_dfuERROR; + } +} + +static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req) +{ + struct f_dfu *f_dfu = req->context; + int ret; - dfu_write(dfu_get_entity(f_dfu->altsetting), req->buf, - req->length, f_dfu->blk_seq_num); + ret = dfu_flush(dfu_get_entity(f_dfu->altsetting), req->buf, + req->length, f_dfu->blk_seq_num); + if (ret) { + f_dfu->dfu_status = DFU_STATUS_errUNKNOWN; + f_dfu->dfu_state = DFU_STATE_dfuERROR; + } +} - if (req->length == 0) - puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n"); +static inline int dfu_get_manifest_timeout(struct dfu_entity *dfu) +{ + return dfu->poll_timeout ? dfu->poll_timeout(dfu) : + DFU_MANIFEST_POLL_TIMEOUT; } static void handle_getstatus(struct usb_request *req) { struct dfu_status *dstat = (struct dfu_status *)req->buf; struct f_dfu *f_dfu = req->context; + struct dfu_entity *dfu = dfu_get_entity(f_dfu->altsetting); + + dfu_set_poll_timeout(dstat, 0); switch (f_dfu->dfu_state) { case DFU_STATE_dfuDNLOAD_SYNC: @@ -152,16 +197,22 @@ static void handle_getstatus(struct usb_request *req) f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_IDLE; break; case DFU_STATE_dfuMANIFEST_SYNC: + f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; + break; + case DFU_STATE_dfuMANIFEST: + dfu_set_poll_timeout(dstat, dfu_get_manifest_timeout(dfu)); break; default: break; } + if (f_dfu->poll_timeout) + if (!(f_dfu->blk_seq_num % + (dfu_get_buf_size() / DFU_USB_BUFSIZ))) + dfu_set_poll_timeout(dstat, f_dfu->poll_timeout); + /* send status response */ dstat->bStatus = f_dfu->dfu_status; - dstat->bwPollTimeout[0] = 0; - dstat->bwPollTimeout[1] = 0; - dstat->bwPollTimeout[2] = 0; dstat->bState = f_dfu->dfu_state; dstat->iString = 0; } @@ -178,6 +229,7 @@ static inline void to_dfu_mode(struct f_dfu *f_dfu) { f_dfu->usb_function.strings = dfu_strings; f_dfu->usb_function.hs_descriptors = f_dfu->function; + f_dfu->usb_function.descriptors = f_dfu->function; f_dfu->dfu_state = DFU_STATE_dfuIDLE; } @@ -185,6 +237,7 @@ static inline void to_runtime_mode(struct f_dfu *f_dfu) { f_dfu->usb_function.strings = NULL; f_dfu->usb_function.hs_descriptors = dfu_runtime_descs; + f_dfu->usb_function.descriptors = dfu_runtime_descs; } static int handle_upload(struct usb_request *req, u16 len) @@ -313,7 +366,7 @@ static int state_dfu_idle(struct f_dfu *f_dfu, to_runtime_mode(f_dfu); f_dfu->dfu_state = DFU_STATE_appIDLE; - dfu_trigger_reset(); + g_dnl_trigger_detach(); break; default: f_dfu->dfu_state = DFU_STATE_dfuERROR; @@ -414,10 +467,11 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu, switch (ctrl->bRequest) { case USB_REQ_DFU_GETSTATUS: /* We're MainfestationTolerant */ - f_dfu->dfu_state = DFU_STATE_dfuIDLE; + f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; handle_getstatus(req); f_dfu->blk_seq_num = 0; value = RET_STAT_LEN; + req->complete = dnload_request_flush; break; case USB_REQ_DFU_GETSTATE: handle_getstate(req); @@ -431,6 +485,33 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu, return value; } +static int state_dfu_manifest(struct f_dfu *f_dfu, + const struct usb_ctrlrequest *ctrl, + struct usb_gadget *gadget, + struct usb_request *req) +{ + int value = 0; + + switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + /* We're MainfestationTolerant */ + f_dfu->dfu_state = DFU_STATE_dfuIDLE; + handle_getstatus(req); + f_dfu->blk_seq_num = 0; + value = RET_STAT_LEN; + puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n"); + break; + case USB_REQ_DFU_GETSTATE: + handle_getstate(req); + break; + default: + f_dfu->dfu_state = DFU_STATE_dfuERROR; + value = RET_STALL; + break; + } + return value; +} + static int state_dfu_upload_idle(struct f_dfu *f_dfu, const struct usb_ctrlrequest *ctrl, struct usb_gadget *gadget, @@ -507,7 +588,7 @@ static dfu_state_fn dfu_state[] = { state_dfu_dnbusy, /* DFU_STATE_dfuDNBUSY */ state_dfu_dnload_idle, /* DFU_STATE_dfuDNLOAD_IDLE */ state_dfu_manifest_sync, /* DFU_STATE_dfuMANIFEST_SYNC */ - NULL, /* DFU_STATE_dfuMANIFEST */ + state_dfu_manifest, /* DFU_STATE_dfuMANIFEST */ NULL, /* DFU_STATE_dfuMANIFEST_WAIT_RST */ state_dfu_upload_idle, /* DFU_STATE_dfuUPLOAD_IDLE */ state_dfu_error /* DFU_STATE_dfuERROR */ @@ -693,10 +774,19 @@ static int dfu_set_alt(struct usb_function *f, unsigned intf, unsigned alt) debug("%s: intf:%d alt:%d\n", __func__, intf, alt); f_dfu->altsetting = alt; + f_dfu->dfu_state = DFU_STATE_dfuIDLE; + f_dfu->dfu_status = DFU_STATUS_OK; return 0; } +static int __dfu_get_alt(struct usb_function *f, unsigned intf) +{ + struct f_dfu *f_dfu = func_to_dfu(f); + + return f_dfu->altsetting; +} + /* TODO: is this really what we need here? */ static void dfu_disable(struct usb_function *f) { @@ -719,12 +809,15 @@ static int dfu_bind_config(struct usb_configuration *c) return -ENOMEM; f_dfu->usb_function.name = "dfu"; f_dfu->usb_function.hs_descriptors = dfu_runtime_descs; + f_dfu->usb_function.descriptors = dfu_runtime_descs; f_dfu->usb_function.bind = dfu_bind; f_dfu->usb_function.unbind = dfu_unbind; f_dfu->usb_function.set_alt = dfu_set_alt; + f_dfu->usb_function.get_alt = __dfu_get_alt; f_dfu->usb_function.disable = dfu_disable; - f_dfu->usb_function.strings = dfu_generic_strings, - f_dfu->usb_function.setup = dfu_handle, + f_dfu->usb_function.strings = dfu_generic_strings; + f_dfu->usb_function.setup = dfu_handle; + f_dfu->poll_timeout = DFU_DEFAULT_POLL_TIMEOUT; status = usb_add_function(c, &f_dfu->usb_function); if (status) @@ -748,3 +841,5 @@ int dfu_add(struct usb_configuration *c) return dfu_bind_config(c); } + +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_dfu, dfu_add); diff --git a/drivers/usb/gadget/f_dfu.h b/drivers/usb/gadget/f_dfu.h index 34a4dde5aa..0c29954add 100644 --- a/drivers/usb/gadget/f_dfu.h +++ b/drivers/usb/gadget/f_dfu.h @@ -83,6 +83,5 @@ struct dfu_function_descriptor { __le16 bcdDFUVersion; } __packed; -/* configuration-specific linkup */ -int dfu_add(struct usb_configuration *c); +#define DFU_POLL_TIMEOUT_MASK (0xFFFFFFUL) #endif /* __F_DFU_H_ */ diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c new file mode 100644 index 0000000000..310175acfe --- /dev/null +++ b/drivers/usb/gadget/f_fastboot.c @@ -0,0 +1,578 @@ +/* + * (C) Copyright 2008 - 2009 + * Windriver, + * Tom Rix + * + * Copyright 2011 Sebastian Andrzej Siewior + * + * Copyright 2014 Linaro, Ltd. + * Rob Herring + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV +#include +#endif + +#define FASTBOOT_VERSION "0.4" + +#define FASTBOOT_INTERFACE_CLASS 0xff +#define FASTBOOT_INTERFACE_SUB_CLASS 0x42 +#define FASTBOOT_INTERFACE_PROTOCOL 0x03 + +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 (0x0200) +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040) +#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040) + +/* The 64 defined bytes plus \0 */ +#define RESPONSE_LEN (64 + 1) + +#define EP_BUFFER_SIZE 4096 + +struct f_fastboot { + struct usb_function usb_function; + + /* IN/OUT EP's and corresponding requests */ + struct usb_ep *in_ep, *out_ep; + struct usb_request *in_req, *out_req; +}; + +static inline struct f_fastboot *func_to_fastboot(struct usb_function *f) +{ + return container_of(f, struct f_fastboot, usb_function); +} + +static struct f_fastboot *fastboot_func; +static unsigned int download_size; +static unsigned int download_bytes; + +static struct usb_endpoint_descriptor fs_ep_in = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = TX_ENDPOINT_MAXIMUM_PACKET_SIZE, + .bInterval = 0x00, +}; + +static struct usb_endpoint_descriptor fs_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1, + .bInterval = 0x00, +}; + +static struct usb_endpoint_descriptor hs_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0, + .bInterval = 0x00, +}; + +static struct usb_interface_descriptor interface_desc = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = FASTBOOT_INTERFACE_CLASS, + .bInterfaceSubClass = FASTBOOT_INTERFACE_SUB_CLASS, + .bInterfaceProtocol = FASTBOOT_INTERFACE_PROTOCOL, +}; + +static struct usb_descriptor_header *fb_runtime_descs[] = { + (struct usb_descriptor_header *)&interface_desc, + (struct usb_descriptor_header *)&fs_ep_in, + (struct usb_descriptor_header *)&hs_ep_out, + NULL, +}; + +/* + * static strings, in UTF-8 + */ +static const char fastboot_name[] = "Android Fastboot"; + +static struct usb_string fastboot_string_defs[] = { + [0].s = fastboot_name, + { } /* end of list */ +}; + +static struct usb_gadget_strings stringtab_fastboot = { + .language = 0x0409, /* en-us */ + .strings = fastboot_string_defs, +}; + +static struct usb_gadget_strings *fastboot_strings[] = { + &stringtab_fastboot, + NULL, +}; + +static void rx_handler_command(struct usb_ep *ep, struct usb_request *req); + +static void fastboot_complete(struct usb_ep *ep, struct usb_request *req) +{ + int status = req->status; + if (!status) + return; + printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual); +} + +static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) +{ + int id; + struct usb_gadget *gadget = c->cdev->gadget; + struct f_fastboot *f_fb = func_to_fastboot(f); + + /* DYNAMIC interface numbers assignments */ + id = usb_interface_id(c, f); + if (id < 0) + return id; + interface_desc.bInterfaceNumber = id; + + id = usb_string_id(c->cdev); + if (id < 0) + return id; + fastboot_string_defs[0].id = id; + interface_desc.iInterface = id; + + f_fb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in); + if (!f_fb->in_ep) + return -ENODEV; + f_fb->in_ep->driver_data = c->cdev; + + f_fb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out); + if (!f_fb->out_ep) + return -ENODEV; + f_fb->out_ep->driver_data = c->cdev; + + hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + + return 0; +} + +static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f) +{ + memset(fastboot_func, 0, sizeof(*fastboot_func)); +} + +static void fastboot_disable(struct usb_function *f) +{ + struct f_fastboot *f_fb = func_to_fastboot(f); + + usb_ep_disable(f_fb->out_ep); + usb_ep_disable(f_fb->in_ep); + + if (f_fb->out_req) { + free(f_fb->out_req->buf); + usb_ep_free_request(f_fb->out_ep, f_fb->out_req); + f_fb->out_req = NULL; + } + if (f_fb->in_req) { + free(f_fb->in_req->buf); + usb_ep_free_request(f_fb->in_ep, f_fb->in_req); + f_fb->in_req = NULL; + } +} + +static struct usb_request *fastboot_start_ep(struct usb_ep *ep) +{ + struct usb_request *req; + + req = usb_ep_alloc_request(ep, 0); + if (!req) + return NULL; + + req->length = EP_BUFFER_SIZE; + req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE); + if (!req->buf) { + usb_ep_free_request(ep, req); + return NULL; + } + + memset(req->buf, 0, req->length); + return req; +} + +static int fastboot_set_alt(struct usb_function *f, + unsigned interface, unsigned alt) +{ + int ret; + struct usb_composite_dev *cdev = f->config->cdev; + struct usb_gadget *gadget = cdev->gadget; + struct f_fastboot *f_fb = func_to_fastboot(f); + + debug("%s: func: %s intf: %d alt: %d\n", + __func__, f->name, interface, alt); + + /* make sure we don't enable the ep twice */ + if (gadget->speed == USB_SPEED_HIGH) + ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out); + else + ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out); + if (ret) { + puts("failed to enable out ep\n"); + return ret; + } + + f_fb->out_req = fastboot_start_ep(f_fb->out_ep); + if (!f_fb->out_req) { + puts("failed to alloc out req\n"); + ret = -EINVAL; + goto err; + } + f_fb->out_req->complete = rx_handler_command; + + ret = usb_ep_enable(f_fb->in_ep, &fs_ep_in); + if (ret) { + puts("failed to enable in ep\n"); + goto err; + } + + f_fb->in_req = fastboot_start_ep(f_fb->in_ep); + if (!f_fb->in_req) { + puts("failed alloc req in\n"); + ret = -EINVAL; + goto err; + } + f_fb->in_req->complete = fastboot_complete; + + ret = usb_ep_queue(f_fb->out_ep, f_fb->out_req, 0); + if (ret) + goto err; + + return 0; +err: + fastboot_disable(f); + return ret; +} + +static int fastboot_add(struct usb_configuration *c) +{ + struct f_fastboot *f_fb = fastboot_func; + int status; + + debug("%s: cdev: 0x%p\n", __func__, c->cdev); + + if (!f_fb) { + f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb)); + if (!f_fb) + return -ENOMEM; + + fastboot_func = f_fb; + memset(f_fb, 0, sizeof(*f_fb)); + } + + f_fb->usb_function.name = "f_fastboot"; + f_fb->usb_function.hs_descriptors = fb_runtime_descs; + f_fb->usb_function.bind = fastboot_bind; + f_fb->usb_function.unbind = fastboot_unbind; + f_fb->usb_function.set_alt = fastboot_set_alt; + f_fb->usb_function.disable = fastboot_disable; + f_fb->usb_function.strings = fastboot_strings; + + status = usb_add_function(c, &f_fb->usb_function); + if (status) { + free(f_fb); + fastboot_func = f_fb; + } + + return status; +} +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add); + +static int fastboot_tx_write(const char *buffer, unsigned int buffer_size) +{ + struct usb_request *in_req = fastboot_func->in_req; + int ret; + + memcpy(in_req->buf, buffer, buffer_size); + in_req->length = buffer_size; + ret = usb_ep_queue(fastboot_func->in_ep, in_req, 0); + if (ret) + printf("Error %d on queue\n", ret); + return 0; +} + +static int fastboot_tx_write_str(const char *buffer) +{ + return fastboot_tx_write(buffer, strlen(buffer)); +} + +static void compl_do_reset(struct usb_ep *ep, struct usb_request *req) +{ + do_reset(NULL, 0, 0, NULL); +} + +static void cb_reboot(struct usb_ep *ep, struct usb_request *req) +{ + fastboot_func->in_req->complete = compl_do_reset; + fastboot_tx_write_str("OKAY"); +} + +static int strcmp_l1(const char *s1, const char *s2) +{ + if (!s1 || !s2) + return -1; + return strncmp(s1, s2, strlen(s1)); +} + +static void cb_getvar(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + const char *s; + size_t chars_left; + + strcpy(response, "OKAY"); + chars_left = sizeof(response) - strlen(response) - 1; + + strsep(&cmd, ":"); + if (!cmd) { + error("missing variable\n"); + fastboot_tx_write_str("FAILmissing var"); + return; + } + + if (!strcmp_l1("version", cmd)) { + strncat(response, FASTBOOT_VERSION, chars_left); + } else if (!strcmp_l1("bootloader-version", cmd)) { + strncat(response, U_BOOT_VERSION, chars_left); + } else if (!strcmp_l1("downloadsize", cmd) || + !strcmp_l1("max-download-size", cmd)) { + char str_num[12]; + + sprintf(str_num, "0x%08x", CONFIG_USB_FASTBOOT_BUF_SIZE); + strncat(response, str_num, chars_left); + } else if (!strcmp_l1("serialno", cmd)) { + s = getenv("serial#"); + if (s) + strncat(response, s, chars_left); + else + strcpy(response, "FAILValue not set"); + } else { + error("unknown variable: %s\n", cmd); + strcpy(response, "FAILVariable not implemented"); + } + fastboot_tx_write_str(response); +} + +static unsigned int rx_bytes_expected(void) +{ + int rx_remain = download_size - download_bytes; + if (rx_remain < 0) + return 0; + if (rx_remain > EP_BUFFER_SIZE) + return EP_BUFFER_SIZE; + return rx_remain; +} + +#define BYTES_PER_DOT 0x20000 +static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) +{ + char response[RESPONSE_LEN]; + unsigned int transfer_size = download_size - download_bytes; + const unsigned char *buffer = req->buf; + unsigned int buffer_size = req->actual; + unsigned int pre_dot_num, now_dot_num; + + if (req->status != 0) { + printf("Bad status: %d\n", req->status); + return; + } + + if (buffer_size < transfer_size) + transfer_size = buffer_size; + + memcpy((void *)CONFIG_USB_FASTBOOT_BUF_ADDR + download_bytes, + buffer, transfer_size); + + pre_dot_num = download_bytes / BYTES_PER_DOT; + download_bytes += transfer_size; + now_dot_num = download_bytes / BYTES_PER_DOT; + + if (pre_dot_num != now_dot_num) { + putc('.'); + if (!(now_dot_num % 74)) + putc('\n'); + } + + /* Check if transfer is done */ + if (download_bytes >= download_size) { + /* + * Reset global transfer variable, keep download_bytes because + * it will be used in the next possible flashing command + */ + download_size = 0; + req->complete = rx_handler_command; + req->length = EP_BUFFER_SIZE; + + sprintf(response, "OKAY"); + fastboot_tx_write_str(response); + + printf("\ndownloading of %d bytes finished\n", download_bytes); + } else { + req->length = rx_bytes_expected(); + if (req->length < ep->maxpacket) + req->length = ep->maxpacket; + } + + req->actual = 0; + usb_ep_queue(ep, req, 0); +} + +static void cb_download(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + + strsep(&cmd, ":"); + download_size = simple_strtoul(cmd, NULL, 16); + download_bytes = 0; + + printf("Starting download of %d bytes\n", download_size); + + if (0 == download_size) { + sprintf(response, "FAILdata invalid size"); + } else if (download_size > CONFIG_USB_FASTBOOT_BUF_SIZE) { + download_size = 0; + sprintf(response, "FAILdata too large"); + } else { + sprintf(response, "DATA%08x", download_size); + req->complete = rx_handler_dl_image; + req->length = rx_bytes_expected(); + if (req->length < ep->maxpacket) + req->length = ep->maxpacket; + } + fastboot_tx_write_str(response); +} + +static void do_bootm_on_complete(struct usb_ep *ep, struct usb_request *req) +{ + char boot_addr_start[12]; + char *bootm_args[] = { "bootm", boot_addr_start, NULL }; + + puts("Booting kernel..\n"); + + sprintf(boot_addr_start, "0x%lx", load_addr); + do_bootm(NULL, 0, 2, bootm_args); + + /* This only happens if image is somehow faulty so we start over */ + do_reset(NULL, 0, 0, NULL); +} + +static void cb_boot(struct usb_ep *ep, struct usb_request *req) +{ + fastboot_func->in_req->complete = do_bootm_on_complete; + fastboot_tx_write_str("OKAY"); +} + +static void do_exit_on_complete(struct usb_ep *ep, struct usb_request *req) +{ + g_dnl_trigger_detach(); +} + +static void cb_continue(struct usb_ep *ep, struct usb_request *req) +{ + fastboot_func->in_req->complete = do_exit_on_complete; + fastboot_tx_write_str("OKAY"); +} + +#ifdef CONFIG_FASTBOOT_FLASH +static void cb_flash(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + + strsep(&cmd, ":"); + if (!cmd) { + error("missing partition name\n"); + fastboot_tx_write_str("FAILmissing partition name"); + return; + } + + strcpy(response, "FAILno flash device defined"); +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV + fb_mmc_flash_write(cmd, (void *)CONFIG_USB_FASTBOOT_BUF_ADDR, + download_bytes, response); +#endif + fastboot_tx_write_str(response); +} +#endif + +struct cmd_dispatch_info { + char *cmd; + void (*cb)(struct usb_ep *ep, struct usb_request *req); +}; + +static const struct cmd_dispatch_info cmd_dispatch_info[] = { + { + .cmd = "reboot", + .cb = cb_reboot, + }, { + .cmd = "getvar:", + .cb = cb_getvar, + }, { + .cmd = "download:", + .cb = cb_download, + }, { + .cmd = "boot", + .cb = cb_boot, + }, { + .cmd = "continue", + .cb = cb_continue, + }, +#ifdef CONFIG_FASTBOOT_FLASH + { + .cmd = "flash", + .cb = cb_flash, + }, +#endif +}; + +static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) +{ + char *cmdbuf = req->buf; + void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL; + int i; + + for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) { + if (!strcmp_l1(cmd_dispatch_info[i].cmd, cmdbuf)) { + func_cb = cmd_dispatch_info[i].cb; + break; + } + } + + if (!func_cb) { + error("unknown command: %s\n", cmdbuf); + fastboot_tx_write_str("FAILunknown command"); + } else { + if (req->actual < req->length) { + u8 *buf = (u8 *)req->buf; + buf[req->actual] = 0; + func_cb(ep, req); + } else { + error("buffer overflow\n"); + fastboot_tx_write_str("FAILbuffer overflow"); + } + } + + if (req->status == 0) { + *cmdbuf = '\0'; + req->actual = 0; + usb_ep_queue(ep, req, 0); + } +} diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 5b348d7a6e..e045957d07 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -6,38 +6,9 @@ * Author: Michal Nazarewicz * All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The names of the above-listed copyright holders may not be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ - /* * The Mass Storage Function acts as a USB Mass Storage device, * appearing to the host as a disk drive or as a CD-ROM drive. In @@ -181,7 +152,6 @@ * . */ - /* * Driver Design * @@ -273,6 +243,7 @@ #include #include #include +#include #include #include @@ -284,6 +255,7 @@ #include #include #include +#include /*------------------------------------------------------------------------*/ @@ -292,7 +264,6 @@ static const char fsg_string_interface[] = "Mass Storage"; - #define FSG_NO_INTR_EP 1 #define FSG_NO_DEVICE_STRINGS 1 #define FSG_NO_OTG 1 @@ -472,7 +443,7 @@ static void set_bulk_out_req_length(struct fsg_common *common, /*-------------------------------------------------------------------------*/ -struct ums_board_info *ums_info; +struct ums *ums; struct fsg_common *the_fsg_common; static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep) @@ -706,6 +677,18 @@ static int sleep_thread(struct fsg_common *common) k++; } + if (k == 10) { + /* Handle CTRL+C */ + if (ctrlc()) + return -EPIPE; + + /* Check cable connection */ + if (!g_dnl_board_usb_cable_connected()) + return -EIO; + + k = 0; + } + usb_gadget_handle_interrupts(); } common->thread_wakeup_needed = 0; @@ -788,14 +771,14 @@ static int do_read(struct fsg_common *common) } /* Perform the read */ - nread = 0; - rc = ums_info->read_sector(&(ums_info->ums_dev), - file_offset / SECTOR_SIZE, - amount / SECTOR_SIZE, - (char __user *)bh->buf); - if (rc) + rc = ums->read_sector(ums, + file_offset / SECTOR_SIZE, + amount / SECTOR_SIZE, + (char __user *)bh->buf); + if (!rc) return -EIO; - nread = amount; + + nread = rc * SECTOR_SIZE; VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, (unsigned long long) file_offset, @@ -962,13 +945,13 @@ static int do_write(struct fsg_common *common) amount = bh->outreq->actual; /* Perform the write */ - rc = ums_info->write_sector(&(ums_info->ums_dev), + rc = ums->write_sector(ums, file_offset / SECTOR_SIZE, amount / SECTOR_SIZE, (char __user *)bh->buf); - if (rc) + if (!rc) return -EIO; - nwritten = amount; + nwritten = rc * SECTOR_SIZE; VLDBG(curlun, "file write %u @ %llu -> %d\n", amount, (unsigned long long) file_offset, @@ -990,6 +973,8 @@ static int do_write(struct fsg_common *common) /* If an error occurred, report it and its position */ if (nwritten < amount) { + printf("nwritten:%d amount:%d\n", nwritten, + amount); curlun->sense_data = SS_WRITE_ERROR; curlun->info_valid = 1; break; @@ -1076,14 +1061,13 @@ static int do_verify(struct fsg_common *common) } /* Perform the read */ - nread = 0; - rc = ums_info->read_sector(&(ums_info->ums_dev), - file_offset / SECTOR_SIZE, - amount / SECTOR_SIZE, - (char __user *)bh->buf); - if (rc) + rc = ums->read_sector(ums, + file_offset / SECTOR_SIZE, + amount / SECTOR_SIZE, + (char __user *)bh->buf); + if (!rc) return -EIO; - nread = amount; + nread = rc * SECTOR_SIZE; VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, (unsigned long long) file_offset, @@ -1126,12 +1110,13 @@ static int do_inquiry(struct fsg_common *common, struct fsg_buffhd *bh) memset(buf, 0, 8); buf[0] = TYPE_DISK; + buf[1] = curlun->removable ? 0x80 : 0; buf[2] = 2; /* ANSI SCSI level 2 */ buf[3] = 2; /* SCSI-2 INQUIRY data format */ buf[4] = 31; /* Additional length */ /* No special options */ sprintf((char *) (buf + 8), "%-8s%-16s%04x", (char*) vendor_id , - ums_info->name, (u16) 0xffff); + ums->name, (u16) 0xffff); return 36; } @@ -2417,6 +2402,7 @@ static void handle_exception(struct fsg_common *common) int fsg_main_thread(void *common_) { + int ret; struct fsg_common *common = the_fsg_common; /* The main loop */ do { @@ -2426,12 +2412,16 @@ int fsg_main_thread(void *common_) } if (!common->running) { - sleep_thread(common); + ret = sleep_thread(common); + if (ret) + return ret; + continue; } - if (get_next_command(common)) - continue; + ret = get_next_command(common); + if (ret) + return ret; if (!exception_in_progress(common)) common->state = FSG_STATE_DATA_PHASE; @@ -2473,12 +2463,12 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, /* Allocate? */ if (!common) { - common = calloc(sizeof *common, 1); + common = calloc(sizeof(*common), 1); if (!common) return ERR_PTR(-ENOMEM); common->free_storage_on_release = 1; } else { - memset(common, 0, sizeof common); + memset(common, 0, sizeof(*common)); common->free_storage_on_release = 0; } @@ -2527,7 +2517,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, buffhds_first_it: bh->inreq_busy = 0; bh->outreq_busy = 0; - bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL); + bh->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, FSG_BUFLEN); if (unlikely(!bh->buf)) { rc = -ENOMEM; goto error_release; @@ -2634,7 +2624,7 @@ usb_copy_descriptors(struct usb_descriptor_header **src) bytes += (*tmp)->bLength; bytes += (n_desc + 1) * sizeof(*tmp); - mem = kmalloc(bytes, GFP_KERNEL); + mem = memalign(CONFIG_SYS_CACHELINE_SIZE, bytes); if (!mem) return NULL; @@ -2657,8 +2647,6 @@ usb_copy_descriptors(struct usb_descriptor_header **src) return ret; } - - static void fsg_unbind(struct usb_configuration *c, struct usb_function *f) { struct fsg_dev *fsg = fsg_from_func(f); @@ -2786,9 +2774,11 @@ int fsg_add(struct usb_configuration *c) return fsg_bind_config(c->cdev, c, fsg_common); } -int fsg_init(struct ums_board_info *ums) +int fsg_init(struct ums *ums_dev) { - ums_info = ums; + ums = ums_dev; return 0; } + +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_ums, fsg_add); diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c new file mode 100644 index 0000000000..2d0410d795 --- /dev/null +++ b/drivers/usb/gadget/f_thor.c @@ -0,0 +1,1004 @@ +/* + * f_thor.c -- USB TIZEN THOR Downloader gadget function + * + * Copyright (C) 2013 Samsung Electronics + * Lukasz Majewski + * + * Based on code from: + * git://review.tizen.org/kernel/u-boot + * + * Developed by: + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang + * Sanghee Kim + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "f_thor.h" + +static void thor_tx_data(unsigned char *data, int len); +static void thor_set_dma(void *addr, int len); +static int thor_rx_data(void); + +static struct f_thor *thor_func; +static inline struct f_thor *func_to_thor(struct usb_function *f) +{ + return container_of(f, struct f_thor, usb_function); +} + +DEFINE_CACHE_ALIGN_BUFFER(unsigned char, thor_tx_data_buf, + sizeof(struct rsp_box)); +DEFINE_CACHE_ALIGN_BUFFER(unsigned char, thor_rx_data_buf, + sizeof(struct rqt_box)); + +/* ********************************************************** */ +/* THOR protocol - transmission handling */ +/* ********************************************************** */ +DEFINE_CACHE_ALIGN_BUFFER(char, f_name, F_NAME_BUF_SIZE); +static unsigned long long int thor_file_size; +static int alt_setting_num; + +static void send_rsp(const struct rsp_box *rsp) +{ + memcpy(thor_tx_data_buf, rsp, sizeof(struct rsp_box)); + thor_tx_data(thor_tx_data_buf, sizeof(struct rsp_box)); + + debug("-RSP: %d, %d\n", rsp->rsp, rsp->rsp_data); +} + +static void send_data_rsp(s32 ack, s32 count) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct data_rsp_box, rsp, + sizeof(struct data_rsp_box)); + + rsp->ack = ack; + rsp->count = count; + + memcpy(thor_tx_data_buf, rsp, sizeof(struct data_rsp_box)); + thor_tx_data(thor_tx_data_buf, sizeof(struct data_rsp_box)); + + debug("-DATA RSP: %d, %d\n", ack, count); +} + +static int process_rqt_info(const struct rqt_box *rqt) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box)); + memset(rsp, 0, sizeof(struct rsp_box)); + + rsp->rsp = rqt->rqt; + rsp->rsp_data = rqt->rqt_data; + + switch (rqt->rqt_data) { + case RQT_INFO_VER_PROTOCOL: + rsp->int_data[0] = VER_PROTOCOL_MAJOR; + rsp->int_data[1] = VER_PROTOCOL_MINOR; + break; + case RQT_INIT_VER_HW: + snprintf(rsp->str_data[0], sizeof(rsp->str_data[0]), + "%x", checkboard()); + break; + case RQT_INIT_VER_BOOT: + sprintf(rsp->str_data[0], "%s", U_BOOT_VERSION); + break; + case RQT_INIT_VER_KERNEL: + sprintf(rsp->str_data[0], "%s", "k unknown"); + break; + case RQT_INIT_VER_PLATFORM: + sprintf(rsp->str_data[0], "%s", "p unknown"); + break; + case RQT_INIT_VER_CSC: + sprintf(rsp->str_data[0], "%s", "c unknown"); + break; + default: + return -EINVAL; + } + + send_rsp(rsp); + return true; +} + +static int process_rqt_cmd(const struct rqt_box *rqt) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box)); + memset(rsp, 0, sizeof(struct rsp_box)); + + rsp->rsp = rqt->rqt; + rsp->rsp_data = rqt->rqt_data; + + switch (rqt->rqt_data) { + case RQT_CMD_REBOOT: + debug("TARGET RESET\n"); + send_rsp(rsp); + g_dnl_unregister(); + dfu_free_entities(); + run_command("reset", 0); + break; + case RQT_CMD_POWEROFF: + case RQT_CMD_EFSCLEAR: + send_rsp(rsp); + default: + printf("Command not supported -> cmd: %d\n", rqt->rqt_data); + return -EINVAL; + } + + return true; +} + +static long long int download_head(unsigned long long total, + unsigned int packet_size, + long long int *left, + int *cnt) +{ + long long int rcv_cnt = 0, left_to_rcv, ret_rcv; + struct dfu_entity *dfu_entity = dfu_get_entity(alt_setting_num); + void *transfer_buffer = dfu_get_buf(dfu_entity); + void *buf = transfer_buffer; + int usb_pkt_cnt = 0, ret; + + /* + * Files smaller than THOR_STORE_UNIT_SIZE (now 32 MiB) are stored on + * the medium. + * The packet response is sent on the purpose after successful data + * chunk write. There is a room for improvement when asynchronous write + * is performed. + */ + while (total - rcv_cnt >= packet_size) { + thor_set_dma(buf, packet_size); + buf += packet_size; + ret_rcv = thor_rx_data(); + if (ret_rcv < 0) + return ret_rcv; + rcv_cnt += ret_rcv; + debug("%d: RCV data count: %llu cnt: %d\n", usb_pkt_cnt, + rcv_cnt, *cnt); + + if ((rcv_cnt % THOR_STORE_UNIT_SIZE) == 0) { + ret = dfu_write(dfu_get_entity(alt_setting_num), + transfer_buffer, THOR_STORE_UNIT_SIZE, + (*cnt)++); + if (ret) { + error("DFU write failed [%d] cnt: %d", + ret, *cnt); + return ret; + } + buf = transfer_buffer; + } + send_data_rsp(0, ++usb_pkt_cnt); + } + + /* Calculate the amount of data to arrive from PC (in bytes) */ + left_to_rcv = total - rcv_cnt; + + /* + * Calculate number of data already received. but not yet stored + * on the medium (they are smaller than THOR_STORE_UNIT_SIZE) + */ + *left = left_to_rcv + buf - transfer_buffer; + debug("%s: left: %llu left_to_rcv: %llu buf: 0x%p\n", __func__, + *left, left_to_rcv, buf); + + if (left_to_rcv) { + thor_set_dma(buf, packet_size); + ret_rcv = thor_rx_data(); + if (ret_rcv < 0) + return ret_rcv; + rcv_cnt += ret_rcv; + send_data_rsp(0, ++usb_pkt_cnt); + } + + debug("%s: %llu total: %llu cnt: %d\n", __func__, rcv_cnt, total, *cnt); + + return rcv_cnt; +} + +static int download_tail(long long int left, int cnt) +{ + struct dfu_entity *dfu_entity; + void *transfer_buffer; + int ret; + + debug("%s: left: %llu cnt: %d\n", __func__, left, cnt); + + dfu_entity = dfu_get_entity(alt_setting_num); + if (!dfu_entity) { + error("Alt setting: %d entity not found!\n", alt_setting_num); + return -ENOENT; + } + + transfer_buffer = dfu_get_buf(dfu_entity); + if (!transfer_buffer) { + error("Transfer buffer not allocated!"); + return -ENXIO; + } + + if (left) { + ret = dfu_write(dfu_entity, transfer_buffer, left, cnt++); + if (ret) { + error("DFU write failed [%d]: left: %llu", ret, left); + return ret; + } + } + + /* + * To store last "packet" or write file from buffer to filesystem + * DFU storage backend requires dfu_flush + * + * This also frees memory malloc'ed by dfu_get_buf(), so no explicit + * need fo call dfu_free_buf() is needed. + */ + ret = dfu_flush(dfu_entity, transfer_buffer, 0, cnt); + if (ret) + error("DFU flush failed!"); + + return ret; +} + +static long long int process_rqt_download(const struct rqt_box *rqt) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box)); + static long long int left, ret_head; + int file_type, ret = 0; + static int cnt; + + memset(rsp, 0, sizeof(struct rsp_box)); + rsp->rsp = rqt->rqt; + rsp->rsp_data = rqt->rqt_data; + + switch (rqt->rqt_data) { + case RQT_DL_INIT: + thor_file_size = rqt->int_data[0]; + debug("INIT: total %d bytes\n", rqt->int_data[0]); + break; + case RQT_DL_FILE_INFO: + file_type = rqt->int_data[0]; + if (file_type == FILE_TYPE_PIT) { + puts("PIT table file - not supported\n"); + rsp->ack = -ENOTSUPP; + ret = rsp->ack; + break; + } + + thor_file_size = rqt->int_data[1]; + memcpy(f_name, rqt->str_data[0], F_NAME_BUF_SIZE); + + debug("INFO: name(%s, %d), size(%llu), type(%d)\n", + f_name, 0, thor_file_size, file_type); + + rsp->int_data[0] = THOR_PACKET_SIZE; + + alt_setting_num = dfu_get_alt(f_name); + if (alt_setting_num < 0) { + error("Alt setting [%d] to write not found!", + alt_setting_num); + rsp->ack = -ENODEV; + ret = rsp->ack; + } + break; + case RQT_DL_FILE_START: + send_rsp(rsp); + ret_head = download_head(thor_file_size, THOR_PACKET_SIZE, + &left, &cnt); + if (ret_head < 0) { + left = 0; + cnt = 0; + } + return ret_head; + case RQT_DL_FILE_END: + debug("DL FILE_END\n"); + rsp->ack = download_tail(left, cnt); + ret = rsp->ack; + left = 0; + cnt = 0; + break; + case RQT_DL_EXIT: + debug("DL EXIT\n"); + break; + default: + error("Operation not supported: %d", rqt->rqt_data); + ret = -ENOTSUPP; + } + + send_rsp(rsp); + return ret; +} + +static int process_data(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct rqt_box, rqt, sizeof(struct rqt_box)); + int ret = -EINVAL; + + memcpy(rqt, thor_rx_data_buf, sizeof(struct rqt_box)); + + debug("+RQT: %d, %d\n", rqt->rqt, rqt->rqt_data); + + switch (rqt->rqt) { + case RQT_INFO: + ret = process_rqt_info(rqt); + break; + case RQT_CMD: + ret = process_rqt_cmd(rqt); + break; + case RQT_DL: + ret = (int) process_rqt_download(rqt); + break; + case RQT_UL: + puts("RQT: UPLOAD not supported!\n"); + break; + default: + error("unknown request (%d)", rqt->rqt); + } + + return ret; +} + +/* ********************************************************** */ +/* THOR USB Function */ +/* ********************************************************** */ + +static inline struct usb_endpoint_descriptor * +ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *hs, + struct usb_endpoint_descriptor *fs) +{ + if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH) + return hs; + return fs; +} + +static struct usb_interface_descriptor thor_downloader_intf_data = { + .bLength = sizeof(thor_downloader_intf_data), + .bDescriptorType = USB_DT_INTERFACE, + + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_CDC_DATA, +}; + +static struct usb_endpoint_descriptor fs_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, +}; + +static struct usb_endpoint_descriptor fs_out_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, +}; + +/* CDC configuration */ +static struct usb_interface_descriptor thor_downloader_intf_int = { + .bLength = sizeof(thor_downloader_intf_int), + .bDescriptorType = USB_DT_INTERFACE, + + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_COMM, + /* 0x02 Abstract Line Control Model */ + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + /* 0x01 Common AT commands */ + .bInterfaceProtocol = USB_CDC_ACM_PROTO_AT_V25TER, +}; + +static struct usb_cdc_header_desc thor_downloader_cdc_header = { + .bLength = sizeof(thor_downloader_cdc_header), + .bDescriptorType = 0x24, /* CS_INTERFACE */ + .bDescriptorSubType = 0x00, + .bcdCDC = 0x0110, +}; + +static struct usb_cdc_call_mgmt_descriptor thor_downloader_cdc_call = { + .bLength = sizeof(thor_downloader_cdc_call), + .bDescriptorType = 0x24, /* CS_INTERFACE */ + .bDescriptorSubType = 0x01, + .bmCapabilities = 0x00, + .bDataInterface = 0x01, +}; + +static struct usb_cdc_acm_descriptor thor_downloader_cdc_abstract = { + .bLength = sizeof(thor_downloader_cdc_abstract), + .bDescriptorType = 0x24, /* CS_INTERFACE */ + .bDescriptorSubType = 0x02, + .bmCapabilities = 0x00, +}; + +static struct usb_cdc_union_desc thor_downloader_cdc_union = { + .bLength = sizeof(thor_downloader_cdc_union), + .bDescriptorType = 0x24, /* CS_INTERFACE */ + .bDescriptorSubType = USB_CDC_UNION_TYPE, +}; + +static struct usb_endpoint_descriptor fs_int_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = 3 | USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = __constant_cpu_to_le16(16), + + .bInterval = 0x9, +}; + +static struct usb_interface_assoc_descriptor +thor_iad_descriptor = { + .bLength = sizeof(thor_iad_descriptor), + .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, + + .bFirstInterface = 0, + .bInterfaceCount = 2, /* control + data */ + .bFunctionClass = USB_CLASS_COMM, + .bFunctionSubClass = USB_CDC_SUBCLASS_ACM, + .bFunctionProtocol = USB_CDC_PROTO_NONE, +}; + +static struct usb_endpoint_descriptor hs_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(512), +}; + +static struct usb_endpoint_descriptor hs_out_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(512), +}; + +static struct usb_endpoint_descriptor hs_int_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = __constant_cpu_to_le16(16), + + .bInterval = 0x9, +}; + +/* + * This attribute vendor descriptor is necessary for correct operation with + * Windows version of THOR download program + * + * It prevents windows driver from sending zero lenght packet (ZLP) after + * each THOR_PACKET_SIZE. This assures consistent behaviour with libusb + */ +static struct usb_cdc_attribute_vendor_descriptor thor_downloader_cdc_av = { + .bLength = sizeof(thor_downloader_cdc_av), + .bDescriptorType = 0x24, + .bDescriptorSubType = 0x80, + .DAUType = 0x0002, + .DAULength = 0x0001, + .DAUValue = 0x00, +}; + +static const struct usb_descriptor_header *hs_thor_downloader_function[] = { + (struct usb_descriptor_header *)&thor_iad_descriptor, + + (struct usb_descriptor_header *)&thor_downloader_intf_int, + (struct usb_descriptor_header *)&thor_downloader_cdc_header, + (struct usb_descriptor_header *)&thor_downloader_cdc_call, + (struct usb_descriptor_header *)&thor_downloader_cdc_abstract, + (struct usb_descriptor_header *)&thor_downloader_cdc_union, + (struct usb_descriptor_header *)&hs_int_desc, + + (struct usb_descriptor_header *)&thor_downloader_intf_data, + (struct usb_descriptor_header *)&thor_downloader_cdc_av, + (struct usb_descriptor_header *)&hs_in_desc, + (struct usb_descriptor_header *)&hs_out_desc, + NULL, +}; + +/*-------------------------------------------------------------------------*/ +static struct usb_request *alloc_ep_req(struct usb_ep *ep, unsigned length) +{ + struct usb_request *req; + + req = usb_ep_alloc_request(ep, 0); + if (!req) + return req; + + req->length = length; + req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, length); + if (!req->buf) { + usb_ep_free_request(ep, req); + req = NULL; + } + + return req; +} + +static int thor_rx_data(void) +{ + struct thor_dev *dev = thor_func->dev; + int data_to_rx, tmp, status; + + data_to_rx = dev->out_req->length; + tmp = data_to_rx; + do { + dev->out_req->length = data_to_rx; + debug("dev->out_req->length:%d dev->rxdata:%d\n", + dev->out_req->length, dev->rxdata); + + status = usb_ep_queue(dev->out_ep, dev->out_req, 0); + if (status) { + error("kill %s: resubmit %d bytes --> %d", + dev->out_ep->name, dev->out_req->length, status); + usb_ep_set_halt(dev->out_ep); + return -EAGAIN; + } + + while (!dev->rxdata) { + usb_gadget_handle_interrupts(); + if (ctrlc()) + return -1; + } + dev->rxdata = 0; + data_to_rx -= dev->out_req->actual; + } while (data_to_rx); + + return tmp; +} + +static void thor_tx_data(unsigned char *data, int len) +{ + struct thor_dev *dev = thor_func->dev; + unsigned char *ptr = dev->in_req->buf; + int status; + + memset(ptr, 0, len); + memcpy(ptr, data, len); + + dev->in_req->length = len; + + debug("%s: dev->in_req->length:%d to_cpy:%d\n", __func__, + dev->in_req->length, sizeof(data)); + + status = usb_ep_queue(dev->in_ep, dev->in_req, 0); + if (status) { + error("kill %s: resubmit %d bytes --> %d", + dev->in_ep->name, dev->in_req->length, status); + usb_ep_set_halt(dev->in_ep); + } + + /* Wait until tx interrupt received */ + while (!dev->txdata) + usb_gadget_handle_interrupts(); + + dev->txdata = 0; +} + +static void thor_rx_tx_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct thor_dev *dev = thor_func->dev; + int status = req->status; + + debug("%s: ep_ptr:%p, req_ptr:%p\n", __func__, ep, req); + switch (status) { + case 0: + if (ep == dev->out_ep) + dev->rxdata = 1; + else + dev->txdata = 1; + + break; + + /* this endpoint is normally active while we're configured */ + case -ECONNABORTED: /* hardware forced ep reset */ + case -ECONNRESET: /* request dequeued */ + case -ESHUTDOWN: /* disconnect from host */ + case -EREMOTEIO: /* short read */ + case -EOVERFLOW: + error("ERROR:%d", status); + break; + } + + debug("%s complete --> %d, %d/%d\n", ep->name, + status, req->actual, req->length); +} + +static struct usb_request *thor_start_ep(struct usb_ep *ep) +{ + struct usb_request *req; + + req = alloc_ep_req(ep, THOR_PACKET_SIZE); + debug("%s: ep:%p req:%p\n", __func__, ep, req); + + if (!req) + return NULL; + + memset(req->buf, 0, req->length); + req->complete = thor_rx_tx_complete; + + return req; +} + +static void thor_setup_complete(struct usb_ep *ep, struct usb_request *req) +{ + if (req->status || req->actual != req->length) + debug("setup complete --> %d, %d/%d\n", + req->status, req->actual, req->length); +} + +static int +thor_func_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) +{ + struct thor_dev *dev = thor_func->dev; + struct usb_request *req = dev->req; + struct usb_gadget *gadget = dev->gadget; + int value = 0; + + u16 len = le16_to_cpu(ctrl->wLength); + + debug("Req_Type: 0x%x Req: 0x%x wValue: 0x%x wIndex: 0x%x wLen: 0x%x\n", + ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, ctrl->wIndex, + ctrl->wLength); + + switch (ctrl->bRequest) { + case USB_CDC_REQ_SET_CONTROL_LINE_STATE: + value = 0; + break; + case USB_CDC_REQ_SET_LINE_CODING: + value = len; + /* Line Coding set done = configuration done */ + thor_func->dev->configuration_done = 1; + break; + + default: + error("thor_setup: unknown request: %d", ctrl->bRequest); + } + + if (value >= 0) { + req->length = value; + req->zero = value < len; + value = usb_ep_queue(gadget->ep0, req, 0); + if (value < 0) { + debug("%s: ep_queue: %d\n", __func__, value); + req->status = 0; + } + } + + return value; +} + +/* Specific to the THOR protocol */ +static void thor_set_dma(void *addr, int len) +{ + struct thor_dev *dev = thor_func->dev; + + debug("in_req:%p, out_req:%p\n", dev->in_req, dev->out_req); + debug("addr:%p, len:%d\n", addr, len); + + dev->out_req->buf = addr; + dev->out_req->length = len; +} + +int thor_init(void) +{ + struct thor_dev *dev = thor_func->dev; + + /* Wait for a device enumeration and configuration settings */ + debug("THOR enumeration/configuration setting....\n"); + while (!dev->configuration_done) + usb_gadget_handle_interrupts(); + + thor_set_dma(thor_rx_data_buf, strlen("THOR")); + /* detect the download request from Host PC */ + if (thor_rx_data() < 0) { + printf("%s: Data not received!\n", __func__); + return -1; + } + + if (!strncmp((char *)thor_rx_data_buf, "THOR", strlen("THOR"))) { + puts("Download request from the Host PC\n"); + udelay(30 * 1000); /* 30 ms */ + + strcpy((char *)thor_tx_data_buf, "ROHT"); + thor_tx_data(thor_tx_data_buf, strlen("ROHT")); + } else { + puts("Wrong reply information\n"); + return -1; + } + + return 0; +} + +int thor_handle(void) +{ + int ret; + + /* receive the data from Host PC */ + while (1) { + thor_set_dma(thor_rx_data_buf, sizeof(struct rqt_box)); + ret = thor_rx_data(); + + if (ret > 0) { + ret = process_data(); + if (ret < 0) + return ret; + } else { + printf("%s: No data received!\n", __func__); + break; + } + } + + return 0; +} + +static int thor_func_bind(struct usb_configuration *c, struct usb_function *f) +{ + struct usb_gadget *gadget = c->cdev->gadget; + struct f_thor *f_thor = func_to_thor(f); + struct thor_dev *dev; + struct usb_ep *ep; + int status; + + thor_func = f_thor; + dev = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*dev)); + if (!dev) + return -ENOMEM; + + memset(dev, 0, sizeof(*dev)); + dev->gadget = gadget; + f_thor->dev = dev; + + debug("%s: usb_configuration: 0x%p usb_function: 0x%p\n", + __func__, c, f); + debug("f_thor: 0x%p thor: 0x%p\n", f_thor, dev); + + /* EP0 */ + /* preallocate control response and buffer */ + dev->req = usb_ep_alloc_request(gadget->ep0, 0); + if (!dev->req) { + status = -ENOMEM; + goto fail; + } + dev->req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, + gadget->ep0->maxpacket); + if (!dev->req->buf) { + status = -ENOMEM; + goto fail; + } + + dev->req->complete = thor_setup_complete; + + /* DYNAMIC interface numbers assignments */ + status = usb_interface_id(c, f); + + if (status < 0) + goto fail; + + thor_downloader_intf_int.bInterfaceNumber = status; + thor_downloader_cdc_union.bMasterInterface0 = status; + + status = usb_interface_id(c, f); + + if (status < 0) + goto fail; + + thor_downloader_intf_data.bInterfaceNumber = status; + thor_downloader_cdc_union.bSlaveInterface0 = status; + + /* allocate instance-specific endpoints */ + ep = usb_ep_autoconfig(gadget, &fs_in_desc); + if (!ep) { + status = -ENODEV; + goto fail; + } + + if (gadget_is_dualspeed(gadget)) { + hs_in_desc.bEndpointAddress = + fs_in_desc.bEndpointAddress; + } + + dev->in_ep = ep; /* Store IN EP for enabling @ setup */ + + ep = usb_ep_autoconfig(gadget, &fs_out_desc); + if (!ep) { + status = -ENODEV; + goto fail; + } + + if (gadget_is_dualspeed(gadget)) + hs_out_desc.bEndpointAddress = + fs_out_desc.bEndpointAddress; + + dev->out_ep = ep; /* Store OUT EP for enabling @ setup */ + + ep = usb_ep_autoconfig(gadget, &fs_int_desc); + if (!ep) { + status = -ENODEV; + goto fail; + } + + dev->int_ep = ep; + + if (gadget_is_dualspeed(gadget)) { + hs_int_desc.bEndpointAddress = + fs_int_desc.bEndpointAddress; + + f->hs_descriptors = (struct usb_descriptor_header **) + &hs_thor_downloader_function; + + if (!f->hs_descriptors) + goto fail; + } + + debug("%s: out_ep:%p out_req:%p\n", __func__, + dev->out_ep, dev->out_req); + + return 0; + + fail: + free(dev); + return status; +} + +static void free_ep_req(struct usb_ep *ep, struct usb_request *req) +{ + free(req->buf); + usb_ep_free_request(ep, req); +} + +static void thor_unbind(struct usb_configuration *c, struct usb_function *f) +{ + struct f_thor *f_thor = func_to_thor(f); + struct thor_dev *dev = f_thor->dev; + + free(dev); + memset(thor_func, 0, sizeof(*thor_func)); + thor_func = NULL; +} + +static void thor_func_disable(struct usb_function *f) +{ + struct f_thor *f_thor = func_to_thor(f); + struct thor_dev *dev = f_thor->dev; + + debug("%s:\n", __func__); + + /* Avoid freeing memory when ep is still claimed */ + if (dev->in_ep->driver_data) { + free_ep_req(dev->in_ep, dev->in_req); + usb_ep_disable(dev->in_ep); + dev->in_ep->driver_data = NULL; + } + + if (dev->out_ep->driver_data) { + dev->out_req->buf = NULL; + usb_ep_free_request(dev->out_ep, dev->out_req); + usb_ep_disable(dev->out_ep); + dev->out_ep->driver_data = NULL; + } + + if (dev->int_ep->driver_data) { + usb_ep_disable(dev->int_ep); + dev->int_ep->driver_data = NULL; + } +} + +static int thor_eps_setup(struct usb_function *f) +{ + struct usb_composite_dev *cdev = f->config->cdev; + struct usb_gadget *gadget = cdev->gadget; + struct thor_dev *dev = thor_func->dev; + struct usb_endpoint_descriptor *d; + struct usb_request *req; + struct usb_ep *ep; + int result; + + ep = dev->in_ep; + d = ep_desc(gadget, &hs_in_desc, &fs_in_desc); + debug("(d)bEndpointAddress: 0x%x\n", d->bEndpointAddress); + + result = usb_ep_enable(ep, d); + if (result) + goto exit; + + ep->driver_data = cdev; /* claim */ + req = thor_start_ep(ep); + if (!req) { + usb_ep_disable(ep); + result = -EIO; + goto exit; + } + + dev->in_req = req; + ep = dev->out_ep; + d = ep_desc(gadget, &hs_out_desc, &fs_out_desc); + debug("(d)bEndpointAddress: 0x%x\n", d->bEndpointAddress); + + result = usb_ep_enable(ep, d); + if (result) + goto exit; + + ep->driver_data = cdev; /* claim */ + req = thor_start_ep(ep); + if (!req) { + usb_ep_disable(ep); + result = -EIO; + goto exit; + } + + dev->out_req = req; + /* ACM control EP */ + ep = dev->int_ep; + ep->driver_data = cdev; /* claim */ + + exit: + return result; +} + +static int thor_func_set_alt(struct usb_function *f, + unsigned intf, unsigned alt) +{ + struct thor_dev *dev = thor_func->dev; + int result; + + debug("%s: func: %s intf: %d alt: %d\n", + __func__, f->name, intf, alt); + + switch (intf) { + case 0: + debug("ACM INTR interface\n"); + break; + case 1: + debug("Communication Data interface\n"); + result = thor_eps_setup(f); + if (result) + error("%s: EPs setup failed!", __func__); + dev->configuration_done = 1; + break; + } + + return 0; +} + +static int thor_func_init(struct usb_configuration *c) +{ + struct f_thor *f_thor; + int status; + + debug("%s: cdev: 0x%p\n", __func__, c->cdev); + + f_thor = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_thor)); + if (!f_thor) + return -ENOMEM; + + memset(f_thor, 0, sizeof(*f_thor)); + + f_thor->usb_function.name = "f_thor"; + f_thor->usb_function.bind = thor_func_bind; + f_thor->usb_function.unbind = thor_unbind; + f_thor->usb_function.setup = thor_func_setup; + f_thor->usb_function.set_alt = thor_func_set_alt; + f_thor->usb_function.disable = thor_func_disable; + + status = usb_add_function(c, &f_thor->usb_function); + if (status) + free(f_thor); + + return status; +} + +int thor_add(struct usb_configuration *c) +{ + debug("%s:\n", __func__); + return thor_func_init(c); +} + +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_thor, thor_add); diff --git a/drivers/usb/gadget/f_thor.h b/drivers/usb/gadget/f_thor.h new file mode 100644 index 0000000000..833a9d24ae --- /dev/null +++ b/drivers/usb/gadget/f_thor.h @@ -0,0 +1,124 @@ +/* + * f_thor.h - USB TIZEN THOR - internal gadget definitions + * + * Copyright (C) 2013 Samsung Electronics + * Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _USB_THOR_H_ +#define _USB_THOR_H_ + +#include +#include + +/* THOR Composite Gadget */ +#define STRING_MANUFACTURER_IDX 0 +#define STRING_PRODUCT_IDX 1 +#define STRING_SERIAL_IDX 2 + +/* ********************************************************** */ +/* THOR protocol definitions */ +/* ********************************************************** */ + +/* + * Attribute Vendor descriptor - necessary to prevent ZLP transmission + * from Windows XP HOST PC + */ +struct usb_cdc_attribute_vendor_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + __u16 DAUType; + __u16 DAULength; + __u8 DAUValue; +} __packed; + +#define VER_PROTOCOL_MAJOR 4 +#define VER_PROTOCOL_MINOR 0 + +enum rqt { + RQT_INFO = 200, + RQT_CMD, + RQT_DL, + RQT_UL, +}; + +enum rqt_data { + /* RQT_INFO */ + RQT_INFO_VER_PROTOCOL = 1, + RQT_INIT_VER_HW, + RQT_INIT_VER_BOOT, + RQT_INIT_VER_KERNEL, + RQT_INIT_VER_PLATFORM, + RQT_INIT_VER_CSC, + + /* RQT_CMD */ + RQT_CMD_REBOOT = 1, + RQT_CMD_POWEROFF, + RQT_CMD_EFSCLEAR, + + /* RQT_DL */ + RQT_DL_INIT = 1, + RQT_DL_FILE_INFO, + RQT_DL_FILE_START, + RQT_DL_FILE_END, + RQT_DL_EXIT, + + /* RQT_UL */ + RQT_UL_INIT = 1, + RQT_UL_START, + RQT_UL_END, + RQT_UL_EXIT, +}; + +struct rqt_box { /* total: 256B */ + s32 rqt; /* request id */ + s32 rqt_data; /* request data id */ + s32 int_data[14]; /* int data */ + char str_data[5][32]; /* string data */ + char md5[32]; /* md5 checksum */ +} __packed; + +struct rsp_box { /* total: 128B */ + s32 rsp; /* response id (= request id) */ + s32 rsp_data; /* response data id */ + s32 ack; /* ack */ + s32 int_data[5]; /* int data */ + char str_data[3][32]; /* string data */ +} __packed; + +struct data_rsp_box { /* total: 8B */ + s32 ack; /* response id (= request id) */ + s32 count; /* response data id */ +} __packed; + +enum { + FILE_TYPE_NORMAL, + FILE_TYPE_PIT, +}; + +struct thor_dev { + struct usb_gadget *gadget; + struct usb_request *req; /* EP0 -> control responses */ + + /* IN/OUT EP's and correspoinding requests */ + struct usb_ep *in_ep, *out_ep, *int_ep; + struct usb_request *in_req, *out_req; + + /* Control flow variables */ + unsigned char configuration_done; + unsigned char rxdata; + unsigned char txdata; +}; + +struct f_thor { + struct usb_function usb_function; + struct thor_dev *dev; +}; + +#define F_NAME_BUF_SIZE 32 +#define THOR_PACKET_SIZE SZ_1M /* 1 MiB */ +#define THOR_STORE_UNIT_SIZE SZ_32M /* 32 MiB */ +#endif /* _USB_THOR_H_ */ diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c index 6e19db15fa..3acf6a1f41 100644 --- a/drivers/usb/gadget/fotg210.c +++ b/drivers/usb/gadget/fotg210.c @@ -245,6 +245,7 @@ static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req) if (ep->id == 0) { /* Wait until cx/ep0 fifo empty */ fotg210_cxwait(chip, CXFIFO_CXFIFOE); + udelay(1); writel(DMAFIFO_CX, ®s->dma_fifo); } else { /* Wait until epx fifo empty */ @@ -847,6 +848,13 @@ int usb_gadget_handle_interrupts(void) /* CX interrupts */ if (gisr & GISR_GRP0) { st = readl(®s->gisr0); + /* + * Write 1 and then 0 works for both W1C & RW. + * + * HW v1.11.0+: It's a W1C register (write 1 clear) + * HW v1.10.0-: It's a R/W register (write 0 clear) + */ + writel(st & GISR0_CXABORT, ®s->gisr0); writel(0, ®s->gisr0); if (st & GISR0_CXERR) @@ -873,6 +881,13 @@ int usb_gadget_handle_interrupts(void) /* Device Status Interrupts */ if (gisr & GISR_GRP2) { st = readl(®s->gisr2); + /* + * Write 1 and then 0 works for both W1C & RW. + * + * HW v1.11.0+: It's a W1C register (write 1 clear) + * HW v1.10.0-: It's a R/W register (write 0 clear) + */ + writel(st, ®s->gisr2); writel(0, ®s->gisr2); if (st & GISR2_RESET) diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index cbfcb2d074..ee52a29467 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -7,7 +7,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include @@ -15,11 +14,12 @@ #include #include -#include "f_dfu.h" +#include +#include +#include #include "gadget_chips.h" #include "composite.c" -#include "f_mass_storage.c" /* * One needs to define the following: @@ -31,15 +31,27 @@ #define STRING_MANUFACTURER 25 #define STRING_PRODUCT 2 +/* Index of String Descriptor describing this configuration */ #define STRING_USBDOWN 2 -#define CONFIG_USBDOWNLOADER 2 +/* Index of String serial */ +#define STRING_SERIAL 3 +#define MAX_STRING_SERIAL 32 +/* Number of supported configurations */ +#define CONFIGURATION_NUMBER 1 #define DRIVER_VERSION "usb_dnl 2.0" -static const char shortname[] = "usb_dnl_"; static const char product[] = "USB download gadget"; +static char g_dnl_serial[MAX_STRING_SERIAL]; static const char manufacturer[] = CONFIG_G_DNL_MANUFACTURER; +void g_dnl_set_serialnumber(char *s) +{ + memset(g_dnl_serial, 0, MAX_STRING_SERIAL); + if (strlen(s) < MAX_STRING_SERIAL) + strncpy(g_dnl_serial, s, strlen(s)); +} + static struct usb_device_descriptor device_desc = { .bLength = sizeof device_desc, .bDescriptorType = USB_DT_DEVICE, @@ -51,14 +63,19 @@ static struct usb_device_descriptor device_desc = { .idVendor = __constant_cpu_to_le16(CONFIG_G_DNL_VENDOR_NUM), .idProduct = __constant_cpu_to_le16(CONFIG_G_DNL_PRODUCT_NUM), .iProduct = STRING_PRODUCT, + .iSerialNumber = STRING_SERIAL, .bNumConfigurations = 1, }; -/* static strings, in UTF-8 */ +/* + * static strings, in UTF-8 + * IDs for those strings are assigned dynamically at g_dnl_bind() + */ static struct usb_string g_dnl_string_defs[] = { - { 0, manufacturer, }, - { 1, product, }, - { } /* end of list */ + {.s = manufacturer}, + {.s = product}, + {.s = g_dnl_serial}, + { } /* end of list */ }; static struct usb_gadget_strings g_dnl_string_tab = { @@ -75,50 +92,106 @@ static int g_dnl_unbind(struct usb_composite_dev *cdev) { struct usb_gadget *gadget = cdev->gadget; + free(cdev->config); + cdev->config = NULL; debug("%s: calling usb_gadget_disconnect for " - "controller '%s'\n", shortname, gadget->name); + "controller '%s'\n", __func__, gadget->name); usb_gadget_disconnect(gadget); return 0; } +static inline struct g_dnl_bind_callback *g_dnl_bind_callback_first(void) +{ + return ll_entry_start(struct g_dnl_bind_callback, + g_dnl_bind_callbacks); +} + +static inline struct g_dnl_bind_callback *g_dnl_bind_callback_end(void) +{ + return ll_entry_end(struct g_dnl_bind_callback, + g_dnl_bind_callbacks); +} + static int g_dnl_do_config(struct usb_configuration *c) { const char *s = c->cdev->driver->name; - int ret = -1; + struct g_dnl_bind_callback *callback = g_dnl_bind_callback_first(); debug("%s: configuration: 0x%p composite dev: 0x%p\n", __func__, c, c->cdev); - printf("GADGET DRIVER: %s\n", s); - if (!strcmp(s, "usb_dnl_dfu")) - ret = dfu_add(c); - else if (!strcmp(s, "usb_dnl_ums")) - ret = fsg_add(c); - - return ret; + for (; callback != g_dnl_bind_callback_end(); callback++) + if (!strcmp(s, callback->usb_function_name)) + return callback->fptr(c); + return -ENODEV; } static int g_dnl_config_register(struct usb_composite_dev *cdev) { - static struct usb_configuration config = { - .label = "usb_dnload", - .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, - .bConfigurationValue = CONFIG_USBDOWNLOADER, - .iConfiguration = STRING_USBDOWN, + struct usb_configuration *config; + const char *name = "usb_dnload"; + + config = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*config)); + if (!config) + return -ENOMEM; - .bind = g_dnl_do_config, - }; + memset(config, 0, sizeof(*config)); - return usb_add_config(cdev, &config); + config->label = name; + config->bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER; + config->bConfigurationValue = CONFIGURATION_NUMBER; + config->iConfiguration = STRING_USBDOWN; + config->bind = g_dnl_do_config; + + return usb_add_config(cdev, config); } __weak -int g_dnl_bind_fixup(struct usb_device_descriptor *dev) +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { return 0; } +__weak int g_dnl_get_board_bcd_device_number(int gcnum) +{ + return gcnum; +} + +__weak int g_dnl_board_usb_cable_connected(void) +{ + return -EOPNOTSUPP; +} + +static bool g_dnl_detach_request; + +bool g_dnl_detach(void) +{ + return g_dnl_detach_request; +} + +void g_dnl_trigger_detach(void) +{ + g_dnl_detach_request = true; +} + +void g_dnl_clear_detach(void) +{ + g_dnl_detach_request = false; +} + +static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev) +{ + struct usb_gadget *gadget = cdev->gadget; + int gcnum; + + gcnum = usb_gadget_controller_number(gadget); + if (gcnum > 0) + gcnum += 0x200; + + return g_dnl_get_board_bcd_device_number(gcnum); +} + static int g_dnl_bind(struct usb_composite_dev *cdev) { struct usb_gadget *gadget = cdev->gadget; @@ -141,24 +214,29 @@ static int g_dnl_bind(struct usb_composite_dev *cdev) g_dnl_string_defs[1].id = id; device_desc.iProduct = id; - g_dnl_bind_fixup(&device_desc); + id = usb_string_id(cdev); + if (id < 0) + return id; + + g_dnl_string_defs[2].id = id; + device_desc.iSerialNumber = id; + + g_dnl_bind_fixup(&device_desc, cdev->driver->name); ret = g_dnl_config_register(cdev); if (ret) goto error; - gcnum = usb_gadget_controller_number(gadget); - - debug("gcnum: %d\n", gcnum); + gcnum = g_dnl_get_bcd_device_number(cdev); if (gcnum >= 0) - device_desc.bcdDevice = cpu_to_le16(0x0200 + gcnum); + device_desc.bcdDevice = cpu_to_le16(gcnum); else { debug("%s: controller '%s' not recognized\n", - shortname, gadget->name); + __func__, gadget->name); device_desc.bcdDevice = __constant_cpu_to_le16(0x9999); } debug("%s: calling usb_gadget_connect for " - "controller '%s'\n", shortname, gadget->name); + "controller '%s'\n", __func__, gadget->name); usb_gadget_connect(gadget); return 0; @@ -177,33 +255,23 @@ static struct usb_composite_driver g_dnl_driver = { .unbind = g_dnl_unbind, }; -int g_dnl_register(const char *type) +/* + * NOTICE: + * Registering via USB function name won't be necessary after rewriting + * g_dnl to support multiple USB functions. + */ +int g_dnl_register(const char *name) { - /* We only allow "dfu" atm, so 3 should be enough */ - static char name[sizeof(shortname) + 3]; int ret; - if (!strcmp(type, "dfu")) { - strcpy(name, shortname); - strcat(name, type); - } else if (!strcmp(type, "ums")) { - strcpy(name, shortname); - strcat(name, type); - } else { - printf("%s: unknown command: %s\n", __func__, type); - return -EINVAL; - } - + debug("%s: g_dnl_driver.name = %s\n", __func__, name); g_dnl_driver.name = name; - debug("%s: g_dnl_driver.name: %s\n", __func__, g_dnl_driver.name); ret = usb_composite_register(&g_dnl_driver); - if (ret) { printf("%s: failed!, error: %d\n", __func__, ret); return ret; } - return 0; } diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index aa54b8547e..cc94771e32 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -144,10 +144,10 @@ #define gadget_is_m66592(g) 0 #endif -#ifdef CONFIG_MV_UDC -#define gadget_is_mv(g) (!strcmp("mv_udc", (g)->name)) +#ifdef CONFIG_CI_UDC +#define gadget_is_ci(g) (!strcmp("ci_udc", (g)->name)) #else -#define gadget_is_mv(g) 0 +#define gadget_is_ci(g) 0 #endif #ifdef CONFIG_USB_GADGET_FOTG210 @@ -219,7 +219,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x19; else if (gadget_is_m66592(gadget)) return 0x20; - else if (gadget_is_mv(gadget)) + else if (gadget_is_ci(gadget)) return 0x21; else if (gadget_is_fotg210(gadget)) return 0x22; diff --git a/drivers/usb/gadget/mpc8xx_udc.c b/drivers/usb/gadget/mpc8xx_udc.c index 0207d391a8..b3e178abef 100644 --- a/drivers/usb/gadget/mpc8xx_udc.c +++ b/drivers/usb/gadget/mpc8xx_udc.c @@ -47,6 +47,7 @@ #include #include #include +#include #include "ep0.h" @@ -896,7 +897,7 @@ static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) pkt_len = urb->actual_length - epi->sent; if (pkt_len > epi->tx_packetSize || pkt_len > EP_MAX_PKT) { - pkt_len = MIN (epi->tx_packetSize, EP_MAX_PKT); + pkt_len = min(epi->tx_packetSize, EP_MAX_PKT); } for (x = 0; x < pkt_len; x++) { @@ -941,7 +942,7 @@ static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) /* TX ACK : USB 2.0 8.7.2, Toggle PID, Advance TX */ epi->sent += pkt_len; - epi->last = MIN (urb->actual_length - epi->sent, epi->tx_packetSize); + epi->last = min(urb->actual_length - epi->sent, epi->tx_packetSize); TOGGLE_TX_PID (ep_ref[ep].pid); if (epi->sent >= epi->tx_urb->actual_length) { diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c deleted file mode 100644 index 7574e31a8f..0000000000 --- a/drivers/usb/gadget/mv_udc.c +++ /dev/null @@ -1,716 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Back ported to the 8xx platform (from the 8260 platform) by - * Murray.Jensen@cmst.csiro.au, 27-Jan-01. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#if CONFIG_USB_MAX_CONTROLLER_COUNT > 1 -#error This driver only supports one single controller. -#endif - -/* - * Check if the system has too long cachelines. If the cachelines are - * longer then 128b, the driver will not be able flush/invalidate data - * cache over separate QH entries. We use 128b because one QH entry is - * 64b long and there are always two QH list entries for each endpoint. - */ -#if ARCH_DMA_MINALIGN > 128 -#error This driver can not work on systems with caches longer than 128b -#endif - -#ifndef DEBUG -#define DBG(x...) do {} while (0) -#else -#define DBG(x...) printf(x) -static const char *reqname(unsigned r) -{ - switch (r) { - case USB_REQ_GET_STATUS: return "GET_STATUS"; - case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE"; - case USB_REQ_SET_FEATURE: return "SET_FEATURE"; - case USB_REQ_SET_ADDRESS: return "SET_ADDRESS"; - case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR"; - case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR"; - case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION"; - case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION"; - case USB_REQ_GET_INTERFACE: return "GET_INTERFACE"; - case USB_REQ_SET_INTERFACE: return "SET_INTERFACE"; - default: return "*UNKNOWN*"; - } -} -#endif - -static struct usb_endpoint_descriptor ep0_out_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static struct usb_endpoint_descriptor ep0_in_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_DIR_IN, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static int mv_pullup(struct usb_gadget *gadget, int is_on); -static int mv_ep_enable(struct usb_ep *ep, - const struct usb_endpoint_descriptor *desc); -static int mv_ep_disable(struct usb_ep *ep); -static int mv_ep_queue(struct usb_ep *ep, - struct usb_request *req, gfp_t gfp_flags); -static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req); - -static struct usb_gadget_ops mv_udc_ops = { - .pullup = mv_pullup, -}; - -static struct usb_ep_ops mv_ep_ops = { - .enable = mv_ep_enable, - .disable = mv_ep_disable, - .queue = mv_ep_queue, - .alloc_request = mv_ep_alloc_request, - .free_request = mv_ep_free_request, -}; - -/* Init values for USB endpoints. */ -static const struct usb_ep mv_ep_init[2] = { - [0] = { /* EP 0 */ - .maxpacket = 64, - .name = "ep0", - .ops = &mv_ep_ops, - }, - [1] = { /* EP 1..n */ - .maxpacket = 512, - .name = "ep-", - .ops = &mv_ep_ops, - }, -}; - -static struct mv_drv controller = { - .gadget = { - .name = "mv_udc", - .ops = &mv_udc_ops, - }, -}; - -/** - * mv_get_qh() - return queue head for endpoint - * @ep_num: Endpoint number - * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) - * - * This function returns the QH associated with particular endpoint - * and it's direction. - */ -static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in) -{ - return &controller.epts[(ep_num * 2) + dir_in]; -} - -/** - * mv_get_qtd() - return queue item for endpoint - * @ep_num: Endpoint number - * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) - * - * This function returns the QH associated with particular endpoint - * and it's direction. - */ -static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in) -{ - return controller.items[(ep_num * 2) + dir_in]; -} - -/** - * mv_flush_qh - flush cache over queue head - * @ep_num: Endpoint number - * - * This function flushes cache over QH for particular endpoint. - */ -static void mv_flush_qh(int ep_num) -{ - struct ept_queue_head *head = mv_get_qh(ep_num, 0); - const uint32_t start = (uint32_t)head; - const uint32_t end = start + 2 * sizeof(*head); - - flush_dcache_range(start, end); -} - -/** - * mv_invalidate_qh - invalidate cache over queue head - * @ep_num: Endpoint number - * - * This function invalidates cache over QH for particular endpoint. - */ -static void mv_invalidate_qh(int ep_num) -{ - struct ept_queue_head *head = mv_get_qh(ep_num, 0); - uint32_t start = (uint32_t)head; - uint32_t end = start + 2 * sizeof(*head); - - invalidate_dcache_range(start, end); -} - -/** - * mv_flush_qtd - flush cache over queue item - * @ep_num: Endpoint number - * - * This function flushes cache over qTD pair for particular endpoint. - */ -static void mv_flush_qtd(int ep_num) -{ - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); - const uint32_t start = (uint32_t)item; - const uint32_t end_raw = start + 2 * sizeof(*item); - const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); - - flush_dcache_range(start, end); -} - -/** - * mv_invalidate_qtd - invalidate cache over queue item - * @ep_num: Endpoint number - * - * This function invalidates cache over qTD pair for particular endpoint. - */ -static void mv_invalidate_qtd(int ep_num) -{ - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); - const uint32_t start = (uint32_t)item; - const uint32_t end_raw = start + 2 * sizeof(*item); - const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); - - invalidate_dcache_range(start, end); -} - -static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - return &mv_ep->req; -} - -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req) -{ - return; -} - -static void ep_enable(int num, int in) -{ - struct ept_queue_head *head; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - unsigned n; - head = mv_get_qh(num, in); - - n = readl(&udc->epctrl[num]); - if (in) - n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK); - else - n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); - - if (num != 0) { - head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) | CONFIG_ZLT; - mv_flush_qh(num); - } - writel(n, &udc->epctrl[num]); -} - -static int mv_ep_enable(struct usb_ep *ep, - const struct usb_endpoint_descriptor *desc) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - int num, in; - num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (desc->bEndpointAddress & USB_DIR_IN) != 0; - ep_enable(num, in); - mv_ep->desc = desc; - return 0; -} - -static int mv_ep_disable(struct usb_ep *ep) -{ - return 0; -} - -static int mv_bounce(struct mv_ep *ep) -{ - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba; - - /* Input buffer address is not aligned. */ - if (addr & (ARCH_DMA_MINALIGN - 1)) - goto align; - - /* Input buffer length is not aligned. */ - if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) - goto align; - - /* The buffer is well aligned, only flush cache. */ - ep->b_len = ep->req.length; - ep->b_buf = ep->req.buf; - goto flush; - -align: - /* Use internal buffer for small payloads. */ - if (ep->req.length <= 64) { - ep->b_len = 64; - ep->b_buf = ep->b_fast; - } else { - ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN); - ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len); - if (!ep->b_buf) - return -ENOMEM; - } - - memcpy(ep->b_buf, ep->req.buf, ep->req.length); - -flush: - ba = (uint32_t)ep->b_buf; - flush_dcache_range(ba, ba + ep->b_len); - - return 0; -} - -static void mv_debounce(struct mv_ep *ep) -{ - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba = (uint32_t)ep->b_buf; - - invalidate_dcache_range(ba, ba + ep->b_len); - - /* Input buffer address is not aligned. */ - if (addr & (ARCH_DMA_MINALIGN - 1)) - goto copy; - - /* Input buffer length is not aligned. */ - if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) - goto copy; - - /* The buffer is well aligned, only invalidate cache. */ - return; - -copy: - memcpy(ep->req.buf, ep->b_buf, ep->req.length); - - /* Large payloads use allocated buffer, free it. */ - if (ep->req.length > 64) - free(ep->b_buf); -} - -static int mv_ep_queue(struct usb_ep *ep, - struct usb_request *req, gfp_t gfp_flags) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - struct ept_queue_item *item; - struct ept_queue_head *head; - int bit, num, len, in, ret; - num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - item = mv_get_qtd(num, in); - head = mv_get_qh(num, in); - len = req->length; - - ret = mv_bounce(mv_ep); - if (ret) - return ret; - - item->next = TERMINATE; - item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; - item->page0 = (uint32_t)mv_ep->b_buf; - item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000; - - head->next = (unsigned) item; - head->info = 0; - - DBG("ept%d %s queue len %x, buffer %p\n", - num, in ? "in" : "out", len, mv_ep->b_buf); - - if (in) - bit = EPT_TX(num); - else - bit = EPT_RX(num); - - mv_flush_qh(num); - mv_flush_qtd(num); - - writel(bit, &udc->epprime); - - return 0; -} - -static void handle_ep_complete(struct mv_ep *ep) -{ - struct ept_queue_item *item; - int num, in, len; - num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - if (num == 0) - ep->desc = &ep0_out_desc; - item = mv_get_qtd(num, in); - mv_invalidate_qtd(num); - - if (item->info & 0xff) - printf("EP%d/%s FAIL nfo=%x pg0=%x\n", - num, in ? "in" : "out", item->info, item->page0); - - len = (item->info >> 16) & 0x7fff; - - mv_debounce(ep); - - ep->req.length -= len; - DBG("ept%d %s complete %x\n", - num, in ? "in" : "out", len); - ep->req.complete(&ep->ep, &ep->req); - if (num == 0) { - ep->req.length = 0; - usb_ep_queue(&ep->ep, &ep->req, 0); - ep->desc = &ep0_in_desc; - } -} - -#define SETUP(type, request) (((type) << 8) | (request)) - -static void handle_setup(void) -{ - struct usb_request *req = &controller.ep[0].req; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - struct ept_queue_head *head; - struct usb_ctrlrequest r; - int status = 0; - int num, in, _num, _in, i; - char *buf; - head = mv_get_qh(0, 0); /* EP0 OUT */ - - mv_invalidate_qh(0); - memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); - writel(EPT_RX(0), &udc->epstat); - DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), - r.bRequestType, r.bRequest, r.wIndex, r.wValue); - - switch (SETUP(r.bRequestType, r.bRequest)) { - case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): - _num = r.wIndex & 15; - _in = !!(r.wIndex & 0x80); - - if ((r.wValue == 0) && (r.wLength == 0)) { - req->length = 0; - for (i = 0; i < NUM_ENDPOINTS; i++) { - if (!controller.ep[i].desc) - continue; - num = controller.ep[i].desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (controller.ep[i].desc->bEndpointAddress - & USB_DIR_IN) != 0; - if ((num == _num) && (in == _in)) { - ep_enable(num, in); - usb_ep_queue(controller.gadget.ep0, - req, 0); - break; - } - } - } - return; - - case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): - /* - * write address delayed (will take effect - * after the next IN txn) - */ - writel((r.wValue << 25) | (1 << 24), &udc->devaddr); - req->length = 0; - usb_ep_queue(controller.gadget.ep0, req, 0); - return; - - case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS): - req->length = 2; - buf = (char *)req->buf; - buf[0] = 1 << USB_DEVICE_SELF_POWERED; - buf[1] = 0; - usb_ep_queue(controller.gadget.ep0, req, 0); - return; - } - /* pass request up to the gadget driver */ - if (controller.driver) - status = controller.driver->setup(&controller.gadget, &r); - else - status = -ENODEV; - - if (!status) - return; - DBG("STALL reqname %s type %x value %x, index %x\n", - reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); - writel((1<<16) | (1 << 0), &udc->epctrl[0]); -} - -static void stop_activity(void) -{ - int i, num, in; - struct ept_queue_head *head; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - writel(readl(&udc->epcomp), &udc->epcomp); - writel(readl(&udc->epstat), &udc->epstat); - writel(0xffffffff, &udc->epflush); - - /* error out any pending reqs */ - for (i = 0; i < NUM_ENDPOINTS; i++) { - if (i != 0) - writel(0, &udc->epctrl[i]); - if (controller.ep[i].desc) { - num = controller.ep[i].desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (controller.ep[i].desc->bEndpointAddress - & USB_DIR_IN) != 0; - head = mv_get_qh(num, in); - head->info = INFO_ACTIVE; - mv_flush_qh(num); - } - } -} - -void udc_irq(void) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - unsigned n = readl(&udc->usbsts); - writel(n, &udc->usbsts); - int bit, i, num, in; - - n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); - if (n == 0) - return; - - if (n & STS_URI) { - DBG("-- reset --\n"); - stop_activity(); - } - if (n & STS_SLI) - DBG("-- suspend --\n"); - - if (n & STS_PCI) { - DBG("-- portchange --\n"); - bit = (readl(&udc->portsc) >> 26) & 3; - if (bit == 2) { - controller.gadget.speed = USB_SPEED_HIGH; - for (i = 1; i < NUM_ENDPOINTS && n; i++) - if (controller.ep[i].desc) - controller.ep[i].ep.maxpacket = 512; - } else { - controller.gadget.speed = USB_SPEED_FULL; - } - } - - if (n & STS_UEI) - printf("\n", readl(&udc->epcomp)); - - if ((n & STS_UI) || (n & STS_UEI)) { - n = readl(&udc->epstat); - if (n & EPT_RX(0)) - handle_setup(); - - n = readl(&udc->epcomp); - if (n != 0) - writel(n, &udc->epcomp); - - for (i = 0; i < NUM_ENDPOINTS && n; i++) { - if (controller.ep[i].desc) { - num = controller.ep[i].desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (controller.ep[i].desc->bEndpointAddress - & USB_DIR_IN) != 0; - bit = (in) ? EPT_TX(num) : EPT_RX(num); - if (n & bit) - handle_ep_complete(&controller.ep[i]); - } - } - } -} - -int usb_gadget_handle_interrupts(void) -{ - u32 value; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - - value = readl(&udc->usbsts); - if (value) - udc_irq(); - - return value; -} - -static int mv_pullup(struct usb_gadget *gadget, int is_on) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - if (is_on) { - /* RESET */ - writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); - udelay(200); - - writel((unsigned)controller.epts, &udc->epinitaddr); - - /* select DEVICE mode */ - writel(USBMODE_DEVICE, &udc->usbmode); - - writel(0xffffffff, &udc->epflush); - - /* Turn on the USB connection by enabling the pullup resistor */ - writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); - } else { - stop_activity(); - writel(USBCMD_FS2, &udc->usbcmd); - udelay(800); - if (controller.driver) - controller.driver->disconnect(gadget); - } - - return 0; -} - -void udc_disconnect(void) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - /* disable pullup */ - stop_activity(); - writel(USBCMD_FS2, &udc->usbcmd); - udelay(800); - if (controller.driver) - controller.driver->disconnect(&controller.gadget); -} - -static int mvudc_probe(void) -{ - struct ept_queue_head *head; - uint8_t *imem; - int i; - - const int num = 2 * NUM_ENDPOINTS; - - const int eplist_min_align = 4096; - const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); - const int eplist_raw_sz = num * sizeof(struct ept_queue_head); - const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); - - const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32); - const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item); - const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN); - const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz; - - /* The QH list must be aligned to 4096 bytes. */ - controller.epts = memalign(eplist_align, eplist_sz); - if (!controller.epts) - return -ENOMEM; - memset(controller.epts, 0, eplist_sz); - - /* - * Each qTD item must be 32-byte aligned, each qTD touple must be - * cacheline aligned. There are two qTD items for each endpoint and - * only one of them is used for the endpoint at time, so we can group - * them together. - */ - controller.items_mem = memalign(ilist_align, ilist_sz); - if (!controller.items_mem) { - free(controller.epts); - return -ENOMEM; - } - - for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { - /* - * Configure QH for each endpoint. The structure of the QH list - * is such that each two subsequent fields, N and N+1 where N is - * even, in the QH list represent QH for one endpoint. The Nth - * entry represents OUT configuration and the N+1th entry does - * represent IN configuration of the endpoint. - */ - head = controller.epts + i; - if (i < 2) - head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) - | CONFIG_ZLT | CONFIG_IOS; - else - head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) - | CONFIG_ZLT; - head->next = TERMINATE; - head->info = 0; - - imem = controller.items_mem + ((i >> 1) * ilist_ent_sz); - if (i & 1) - imem += sizeof(struct ept_queue_item); - - controller.items[i] = (struct ept_queue_item *)imem; - - if (i & 1) { - mv_flush_qh(i - 1); - mv_flush_qtd(i - 1); - } - } - - INIT_LIST_HEAD(&controller.gadget.ep_list); - - /* Init EP 0 */ - memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init)); - controller.ep[0].desc = &ep0_in_desc; - controller.gadget.ep0 = &controller.ep[0].ep; - INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); - - /* Init EP 1..n */ - for (i = 1; i < NUM_ENDPOINTS; i++) { - memcpy(&controller.ep[i].ep, &mv_ep_init[1], - sizeof(*mv_ep_init)); - list_add_tail(&controller.ep[i].ep.ep_list, - &controller.gadget.ep_list); - } - - return 0; -} - -int usb_gadget_register_driver(struct usb_gadget_driver *driver) -{ - struct mv_udc *udc; - int ret; - - if (!driver) - return -EINVAL; - if (!driver->bind || !driver->setup || !driver->disconnect) - return -EINVAL; - if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) - return -EINVAL; - - ret = usb_lowlevel_init(0, (void **)&controller.ctrl); - if (ret) - return ret; - - ret = mvudc_probe(); - if (!ret) { - udc = (struct mv_udc *)controller.ctrl->hcor; - - /* select ULPI phy */ - writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); - } - - ret = driver->bind(&controller.gadget); - if (ret) { - DBG("driver->bind() returned %d\n", ret); - return ret; - } - controller.driver = driver; - - return 0; -} - -int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -{ - return 0; -} diff --git a/drivers/usb/gadget/omap1510_udc.c b/drivers/usb/gadget/omap1510_udc.c deleted file mode 100644 index 8553fe5396..0000000000 --- a/drivers/usb/gadget/omap1510_udc.c +++ /dev/null @@ -1,1554 +0,0 @@ -/* - * (C) Copyright 2003 - * Gerry Hamel, geh@ti.com, Texas Instruments - * - * Based on - * linux/drivers/usb/device/bi/omap.c - * TI OMAP1510 USB bus interface driver - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * (C) Copyright 2002 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#ifdef CONFIG_OMAP_SX1 -#include -#endif -#include -#include - -#include "ep0.h" - - -#define UDC_INIT_MDELAY 80 /* Device settle delay */ -#define UDC_MAX_ENDPOINTS 31 /* Number of endpoints on this UDC */ - -/* Some kind of debugging output... */ -#if 1 -#define UDCDBG(str) -#define UDCDBGA(fmt,args...) -#else /* The bugs still exists... */ -#define UDCDBG(str) serial_printf("[%s] %s:%d: " str "\n", __FILE__,__FUNCTION__,__LINE__) -#define UDCDBGA(fmt,args...) serial_printf("[%s] %s:%d: " fmt "\n", __FILE__,__FUNCTION__,__LINE__, ##args) -#endif - -#if 1 -#define UDCREG(name) -#define UDCREGL(name) -#else /* The bugs still exists... */ -#define UDCREG(name) serial_printf("%s():%d: %s[%08x]=%.4x\n",__FUNCTION__,__LINE__, (#name), name, inw(name)) /* For 16-bit regs */ -#define UDCREGL(name) serial_printf("%s():%d: %s[%08x]=%.8x\n",__FUNCTION__,__LINE__, (#name), name, inl(name)) /* For 32-bit regs */ -#endif - - -static struct urb *ep0_urb = NULL; - -static struct usb_device_instance *udc_device; /* Used in interrupt handler */ -static u16 udc_devstat = 0; /* UDC status (DEVSTAT) */ -static u32 udc_interrupts = 0; - -static void udc_stall_ep (unsigned int ep_addr); - - -static struct usb_endpoint_instance *omap1510_find_ep (int ep) -{ - int i; - - for (i = 0; i < udc_device->bus->max_endpoints; i++) { - if (udc_device->bus->endpoint_array[i].endpoint_address == ep) - return &udc_device->bus->endpoint_array[i]; - } - return NULL; -} - -/* ************************************************************************** */ -/* IO - */ - -/* - * omap1510_prepare_endpoint_for_rx - * - * This function implements TRM Figure 14-11. - * - * The endpoint to prepare for transfer is specified as a physical endpoint - * number. For OUT (rx) endpoints 1 through 15, the corresponding endpoint - * configuration register is checked to see if the endpoint is ISO or not. - * If the OUT endpoint is valid and is non-ISO then its FIFO is enabled. - * No action is taken for endpoint 0 or for IN (tx) endpoints 16 through 30. - */ -static void omap1510_prepare_endpoint_for_rx (int ep_addr) -{ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("omap1510_prepare_endpoint %x", ep_addr); - if (((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT)) { - if ((inw (UDC_EP_RX (ep_num)) & - (UDC_EPn_RX_Valid | UDC_EPn_RX_Iso)) == - UDC_EPn_RX_Valid) { - /* rx endpoint is valid, non-ISO, so enable its FIFO */ - outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); - outw (UDC_Set_FIFO_En, UDC_CTRL); - outw (0, UDC_EP_NUM); - } - } -} - -/* omap1510_configure_endpoints - * - * This function implements TRM Figure 14-10. - */ -static void omap1510_configure_endpoints (struct usb_device_instance *device) -{ - int ep; - struct usb_bus_instance *bus; - struct usb_endpoint_instance *endpoint; - unsigned short ep_ptr; - unsigned short ep_size; - unsigned short ep_isoc; - unsigned short ep_doublebuffer; - int ep_addr; - int packet_size; - int buffer_size; - int attributes; - - bus = device->bus; - - /* There is a dedicated 2048 byte buffer for USB packets that may be - * arbitrarily partitioned among the endpoints on 8-byte boundaries. - * The first 8 bytes are reserved for receiving setup packets on - * endpoint 0. - */ - ep_ptr = 8; /* reserve the first 8 bytes for the setup fifo */ - - for (ep = 0; ep < bus->max_endpoints; ep++) { - endpoint = bus->endpoint_array + ep; - ep_addr = endpoint->endpoint_address; - if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* IN endpoint */ - packet_size = endpoint->tx_packetSize; - attributes = endpoint->tx_attributes; - } else { - /* OUT endpoint */ - packet_size = endpoint->rcv_packetSize; - attributes = endpoint->rcv_attributes; - } - - switch (packet_size) { - case 0: - ep_size = 0; - break; - case 8: - ep_size = 0; - break; - case 16: - ep_size = 1; - break; - case 32: - ep_size = 2; - break; - case 64: - ep_size = 3; - break; - case 128: - ep_size = 4; - break; - case 256: - ep_size = 5; - break; - case 512: - ep_size = 6; - break; - default: - UDCDBGA ("ep 0x%02x has bad packet size %d", - ep_addr, packet_size); - packet_size = 0; - ep_size = 0; - break; - } - - switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { - case USB_ENDPOINT_XFER_CONTROL: - case USB_ENDPOINT_XFER_BULK: - case USB_ENDPOINT_XFER_INT: - default: - /* A non-isochronous endpoint may optionally be - * double-buffered. For now we disable - * double-buffering. - */ - ep_doublebuffer = 0; - ep_isoc = 0; - if (packet_size > 64) - packet_size = 0; - if (!ep || !ep_doublebuffer) - buffer_size = packet_size; - else - buffer_size = packet_size * 2; - break; - case USB_ENDPOINT_XFER_ISOC: - /* Isochronous endpoints are always double- - * buffered, but the double-buffering bit - * in the endpoint configuration register - * becomes the msb of the endpoint size so we - * set the double-buffering flag to zero. - */ - ep_doublebuffer = 0; - ep_isoc = 1; - buffer_size = packet_size * 2; - break; - } - - /* check to see if our packet buffer RAM is exhausted */ - if ((ep_ptr + buffer_size) > 2048) { - UDCDBGA ("out of packet RAM for ep 0x%02x buf size %d", ep_addr, buffer_size); - buffer_size = packet_size = 0; - } - - /* force a default configuration for endpoint 0 since it is - * always enabled - */ - if (!ep && ((packet_size < 8) || (packet_size > 64))) { - buffer_size = packet_size = 64; - ep_size = 3; - } - - if (!ep) { - /* configure endpoint 0 */ - outw ((ep_size << 12) | (ep_ptr >> 3), UDC_EP0); - /*UDCDBGA("ep 0 buffer offset 0x%03x packet size 0x%03x", */ - /* ep_ptr, packet_size); */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* IN endpoint */ - if (packet_size) { - outw ((1 << 15) | (ep_doublebuffer << 14) | - (ep_size << 12) | (ep_isoc << 11) | - (ep_ptr >> 3), - UDC_EP_TX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - UDCDBGA ("IN ep %d buffer offset 0x%03x" - " packet size 0x%03x", - ep_addr & USB_ENDPOINT_NUMBER_MASK, - ep_ptr, packet_size); - } else { - outw (0, - UDC_EP_TX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - } - } else { - /* OUT endpoint */ - if (packet_size) { - outw ((1 << 15) | (ep_doublebuffer << 14) | - (ep_size << 12) | (ep_isoc << 11) | - (ep_ptr >> 3), - UDC_EP_RX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - UDCDBGA ("OUT ep %d buffer offset 0x%03x" - " packet size 0x%03x", - ep_addr & USB_ENDPOINT_NUMBER_MASK, - ep_ptr, packet_size); - } else { - outw (0, - UDC_EP_RX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - } - } - ep_ptr += buffer_size; - } -} - -/* omap1510_deconfigure_device - * - * This function balances omap1510_configure_device. - */ -static void omap1510_deconfigure_device (void) -{ - int epnum; - - UDCDBG ("clear Cfg_Lock"); - outw (inw (UDC_SYSCON1) & ~UDC_Cfg_Lock, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); - - /* deconfigure all endpoints */ - for (epnum = 1; epnum <= 15; epnum++) { - outw (0, UDC_EP_RX (epnum)); - outw (0, UDC_EP_TX (epnum)); - } -} - -/* omap1510_configure_device - * - * This function implements TRM Figure 14-9. - */ -static void omap1510_configure_device (struct usb_device_instance *device) -{ - omap1510_configure_endpoints (device); - - - /* Figure 14-9 indicates we should enable interrupts here, but we have - * other routines (udc_all_interrupts, udc_suspended_interrupts) to - * do that. - */ - - UDCDBG ("set Cfg_Lock"); - outw (inw (UDC_SYSCON1) | UDC_Cfg_Lock, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); -} - -/* omap1510_write_noniso_tx_fifo - * - * This function implements TRM Figure 14-30. - * - * If the endpoint has an active tx_urb, then the next packet of data from the - * URB is written to the tx FIFO. The total amount of data in the urb is given - * by urb->actual_length. The maximum amount of data that can be sent in any - * one packet is given by endpoint->tx_packetSize. The number of data bytes - * from this URB that have already been transmitted is given by endpoint->sent. - * endpoint->last is updated by this routine with the number of data bytes - * transmitted in this packet. - * - * In accordance with Figure 14-30, the EP_NUM register must already have been - * written with the value to select the appropriate tx FIFO before this routine - * is called. - */ -static void omap1510_write_noniso_tx_fifo (struct usb_endpoint_instance - *endpoint) -{ - struct urb *urb = endpoint->tx_urb; - - if (urb) { - unsigned int last, i; - - UDCDBGA ("urb->buffer %p, buffer_length %d, actual_length %d", - urb->buffer, urb->buffer_length, urb->actual_length); - if ((last = - MIN (urb->actual_length - endpoint->sent, - endpoint->tx_packetSize))) { - u8 *cp = urb->buffer + endpoint->sent; - - UDCDBGA ("endpoint->sent %d, tx_packetSize %d, last %d", endpoint->sent, endpoint->tx_packetSize, last); - - if (((u32) cp & 1) == 0) { /* word aligned? */ - outsw (UDC_DATA, cp, last >> 1); - } else { /* byte aligned. */ - for (i = 0; i < (last >> 1); i++) { - u16 w = ((u16) cp[2 * i + 1] << 8) | - (u16) cp[2 * i]; - outw (w, UDC_DATA); - } - } - if (last & 1) { - outb (*(cp + last - 1), UDC_DATA); - } - } - endpoint->last = last; - } -} - -/* omap1510_read_noniso_rx_fifo - * - * This function implements TRM Figure 14-28. - * - * If the endpoint has an active rcv_urb, then the next packet of data is read - * from the rcv FIFO and written to rcv_urb->buffer at offset - * rcv_urb->actual_length to append the packet data to the data from any - * previous packets for this transfer. We assume that there is sufficient room - * left in the buffer to hold an entire packet of data. - * - * The return value is the number of bytes read from the FIFO for this packet. - * - * In accordance with Figure 14-28, the EP_NUM register must already have been - * written with the value to select the appropriate rcv FIFO before this routine - * is called. - */ -static int omap1510_read_noniso_rx_fifo (struct usb_endpoint_instance - *endpoint) -{ - struct urb *urb = endpoint->rcv_urb; - int len = 0; - - if (urb) { - len = inw (UDC_RXFSTAT); - - if (len) { - unsigned char *cp = urb->buffer + urb->actual_length; - - insw (UDC_DATA, cp, len >> 1); - if (len & 1) - *(cp + len - 1) = inb (UDC_DATA); - } - } - return len; -} - -/* omap1510_prepare_for_control_write_status - * - * This function implements TRM Figure 14-17. - * - * We have to deal here with non-autodecoded control writes that haven't already - * been dealt with by ep0_recv_setup. The non-autodecoded standard control - * write requests are: set/clear endpoint feature, set configuration, set - * interface, and set descriptor. ep0_recv_setup handles set/clear requests for - * ENDPOINT_HALT by halting the endpoint for a set request and resetting the - * endpoint for a clear request. ep0_recv_setup returns an error for - * SET_DESCRIPTOR requests which causes them to be terminated with a stall by - * the setup handler. A SET_INTERFACE request is handled by ep0_recv_setup by - * generating a DEVICE_SET_INTERFACE event. This leaves only the - * SET_CONFIGURATION event for us to deal with here. - * - */ -static void omap1510_prepare_for_control_write_status (struct urb *urb) -{ - struct usb_device_request *request = &urb->device_request;; - - /* check for a SET_CONFIGURATION request */ - if (request->bRequest == USB_REQ_SET_CONFIGURATION) { - int configuration = le16_to_cpu (request->wValue) & 0xff; - unsigned short devstat = inw (UDC_DEVSTAT); - - if ((devstat & (UDC_ADD | UDC_CFG)) == UDC_ADD) { - /* device is currently in ADDRESSED state */ - if (configuration) { - /* Assume the specified non-zero configuration - * value is valid and switch to the CONFIGURED - * state. - */ - outw (UDC_Dev_Cfg, UDC_SYSCON2); - } - } else if ((devstat & UDC_CFG) == UDC_CFG) { - /* device is currently in CONFIGURED state */ - if (!configuration) { - /* Switch to ADDRESSED state. */ - outw (UDC_Clr_Cfg, UDC_SYSCON2); - } - } - } - - /* select EP0 tx FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - /* clear endpoint (no data bytes in status stage) */ - outw (UDC_Clr_EP, UDC_CTRL); - /* enable the EP0 tx FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the endpoint */ - outw (UDC_EP_Dir, UDC_EP_NUM); -} - -/* udc_state_transition_up - * udc_state_transition_down - * - * Helper functions to implement device state changes. The device states and - * the events that transition between them are: - * - * STATE_ATTACHED - * || /\ - * \/ || - * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET - * || /\ - * \/ || - * STATE_POWERED - * || /\ - * \/ || - * DEVICE_RESET DEVICE_POWER_INTERRUPTION - * || /\ - * \/ || - * STATE_DEFAULT - * || /\ - * \/ || - * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET - * || /\ - * \/ || - * STATE_ADDRESSED - * || /\ - * \/ || - * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED - * || /\ - * \/ || - * STATE_CONFIGURED - * - * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED - * to STATE_CONFIGURED) from the specified initial state to the specified final - * state, passing through each intermediate state on the way. If the initial - * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then - * no state transitions will take place. - * - * udc_state_transition_down transitions down (in the direction from - * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the - * specified final state, passing through each intermediate state on the way. - * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final - * state, then no state transitions will take place. - * - * These functions must only be called with interrupts disabled. - */ -static void udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial < final) { - switch (initial) { - case STATE_ATTACHED: - usbd_device_event_irq (udc_device, - DEVICE_HUB_CONFIGURED, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_ADDRESS_ASSIGNED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, - 0); - case STATE_CONFIGURED: - break; - default: - break; - } - } -} - -static void udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial > final) { - switch (initial) { - case STATE_CONFIGURED: - usbd_device_event_irq (udc_device, DEVICE_DE_CONFIGURED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, DEVICE_POWER_INTERRUPTION, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, 0); - case STATE_ATTACHED: - break; - default: - break; - } - } -} - -/* Handle all device state changes. - * This function implements TRM Figure 14-21. - */ -static void omap1510_udc_state_changed (void) -{ - u16 bits; - u16 devstat = inw (UDC_DEVSTAT); - - UDCDBGA ("state changed, devstat %x, old %x", devstat, udc_devstat); - - bits = devstat ^ udc_devstat; - if (bits) { - if (bits & UDC_ATT) { - if (devstat & UDC_ATT) { - UDCDBG ("device attached and powered"); - udc_state_transition_up (udc_device->device_state, STATE_POWERED); - } else { - UDCDBG ("device detached or unpowered"); - udc_state_transition_down (udc_device->device_state, STATE_ATTACHED); - } - } - if (bits & UDC_USB_Reset) { - if (devstat & UDC_USB_Reset) { - UDCDBG ("device reset in progess"); - udc_state_transition_down (udc_device->device_state, STATE_POWERED); - } else { - UDCDBG ("device reset completed"); - } - } - if (bits & UDC_DEF) { - if (devstat & UDC_DEF) { - UDCDBG ("device entering default state"); - udc_state_transition_up (udc_device->device_state, STATE_DEFAULT); - } else { - UDCDBG ("device leaving default state"); - udc_state_transition_down (udc_device->device_state, STATE_POWERED); - } - } - if (bits & UDC_SUS) { - if (devstat & UDC_SUS) { - UDCDBG ("entering suspended state"); - usbd_device_event_irq (udc_device, DEVICE_BUS_INACTIVE, 0); - } else { - UDCDBG ("leaving suspended state"); - usbd_device_event_irq (udc_device, DEVICE_BUS_ACTIVITY, 0); - } - } - if (bits & UDC_R_WK_OK) { - UDCDBGA ("remote wakeup %s", (devstat & UDC_R_WK_OK) - ? "enabled" : "disabled"); - } - if (bits & UDC_ADD) { - if (devstat & UDC_ADD) { - UDCDBG ("default -> addressed"); - udc_state_transition_up (udc_device->device_state, STATE_ADDRESSED); - } else { - UDCDBG ("addressed -> default"); - udc_state_transition_down (udc_device->device_state, STATE_DEFAULT); - } - } - if (bits & UDC_CFG) { - if (devstat & UDC_CFG) { - UDCDBG ("device configured"); - /* The ep0_recv_setup function generates the - * DEVICE_CONFIGURED event when a - * USB_REQ_SET_CONFIGURATION setup packet is - * received, so we should already be in the - * state STATE_CONFIGURED. - */ - udc_state_transition_up (udc_device->device_state, STATE_CONFIGURED); - } else { - UDCDBG ("device deconfigured"); - udc_state_transition_down (udc_device->device_state, STATE_ADDRESSED); - } - } - } - - /* Clear interrupt source */ - outw (UDC_DS_Chg, UDC_IRQ_SRC); - - /* Save current DEVSTAT */ - udc_devstat = devstat; -} - -/* Handle SETUP USB interrupt. - * This function implements TRM Figure 14-14. - */ -static void omap1510_udc_setup (struct usb_endpoint_instance *endpoint) -{ - UDCDBG ("-> Entering device setup"); - - do { - const int setup_pktsize = 8; - unsigned char *datap = - (unsigned char *) &ep0_urb->device_request; - - /* Gain access to EP 0 setup FIFO */ - outw (UDC_Setup_Sel, UDC_EP_NUM); - - /* Read control request data */ - insb (UDC_DATA, datap, setup_pktsize); - - UDCDBGA ("EP0 setup read [%x %x %x %x %x %x %x %x]", - *(datap + 0), *(datap + 1), *(datap + 2), - *(datap + 3), *(datap + 4), *(datap + 5), - *(datap + 6), *(datap + 7)); - - /* Reset EP0 setup FIFO */ - outw (0, UDC_EP_NUM); - } while (inw (UDC_IRQ_SRC) & UDC_Setup); - - /* Try to process setup packet */ - if (ep0_recv_setup (ep0_urb)) { - /* Not a setup packet, stall next EP0 transaction */ - udc_stall_ep (0); - UDCDBG ("can't parse setup packet, still waiting for setup"); - return; - } - - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - UDCDBG ("control write on EP0"); - if (le16_to_cpu (ep0_urb->device_request.wLength)) { - /* We don't support control write data stages. - * The only standard control write request with a data - * stage is SET_DESCRIPTOR, and ep0_recv_setup doesn't - * support that so we just stall those requests. A - * function driver might support a non-standard - * write request with a data stage, but it isn't - * obvious what we would do with the data if we read it - * so we'll just stall it. It seems like the API isn't - * quite right here. - */ -#if 0 - /* Here is what we would do if we did support control - * write data stages. - */ - ep0_urb->actual_length = 0; - outw (0, UDC_EP_NUM); - /* enable the EP0 rx FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); -#else - /* Stall this request */ - UDCDBG ("Stalling unsupported EP0 control write data " - "stage."); - udc_stall_ep (0); -#endif - } else { - omap1510_prepare_for_control_write_status (ep0_urb); - } - } else { - UDCDBG ("control read on EP0"); - /* The ep0_recv_setup function has already placed our response - * packet data in ep0_urb->buffer and the packet length in - * ep0_urb->actual_length. - */ - endpoint->tx_urb = ep0_urb; - endpoint->sent = 0; - /* select the EP0 tx FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - /* Write packet data to the FIFO. omap1510_write_noniso_tx_fifo - * will update endpoint->last with the number of bytes written - * to the FIFO. - */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable the FIFO to start the packet transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the EP0 tx FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } - - UDCDBG ("<- Leaving device setup"); -} - -/* Handle endpoint 0 RX interrupt - * This routine implements TRM Figure 14-16. - */ -static void omap1510_udc_ep0_rx (struct usb_endpoint_instance *endpoint) -{ - unsigned short status; - - UDCDBG ("RX on EP0"); - /* select EP0 rx FIFO */ - outw (UDC_EP_Sel, UDC_EP_NUM); - - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType - & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { - /* This rx interrupt must be for a control write data - * stage packet. - * - * We don't support control write data stages. - * We should never end up here. - */ - - /* clear the EP0 rx FIFO */ - outw (UDC_Clr_EP, UDC_CTRL); - - /* deselect the EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - - UDCDBG ("Stalling unexpected EP0 control write " - "data stage packet"); - udc_stall_ep (0); - } else { - /* This rx interrupt must be for a control read status - * stage packet. - */ - UDCDBG ("ACK on EP0 control read status stage packet"); - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } - } else if (status & UDC_STALL) { - UDCDBG ("EP0 stall during RX"); - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } else { - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } -} - -/* Handle endpoint 0 TX interrupt - * This routine implements TRM Figure 14-18. - */ -static void omap1510_udc_ep0_tx (struct usb_endpoint_instance *endpoint) -{ - unsigned short status; - struct usb_device_request *request = &ep0_urb->device_request; - - UDCDBG ("TX on EP0"); - /* select EP0 TX FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - - status = inw (UDC_STAT_FLG); - if (status & UDC_ACK) { - /* Check direction */ - if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == - USB_REQ_HOST2DEVICE) { - /* This tx interrupt must be for a control write status - * stage packet. - */ - UDCDBG ("ACK on EP0 control write status stage packet"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } else { - /* This tx interrupt must be for a control read data - * stage packet. - */ - int wLength = le16_to_cpu (request->wLength); - - /* Update our count of bytes sent so far in this - * transfer. - */ - endpoint->sent += endpoint->last; - - /* We are finished with this transfer if we have sent - * all of the bytes in our tx urb (urb->actual_length) - * unless we need a zero-length terminating packet. We - * need a zero-length terminating packet if we returned - * fewer bytes than were requested (wLength) by the host, - * and the number of bytes we returned is an exact - * multiple of the packet size endpoint->tx_packetSize. - */ - if ((endpoint->sent == ep0_urb->actual_length) - && ((ep0_urb->actual_length == wLength) - || (endpoint->last != - endpoint->tx_packetSize))) { - /* Done with control read data stage. */ - UDCDBG ("control read data stage complete"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - /* select EP0 RX FIFO to prepare for control - * read status stage. - */ - outw (UDC_EP_Sel, UDC_EP_NUM); - /* clear the EP0 RX FIFO */ - outw (UDC_Clr_EP, UDC_CTRL); - /* enable the EP0 RX FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the EP0 RX FIFO */ - outw (0, UDC_EP_NUM); - } else { - /* We still have another packet of data to send - * in this control read data stage or else we - * need a zero-length terminating packet. - */ - UDCDBG ("ACK control read data stage packet"); - omap1510_write_noniso_tx_fifo (endpoint); - /* enable the EP0 tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } - } - } else if (status & UDC_STALL) { - UDCDBG ("EP0 stall during TX"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } else { - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } -} - -/* Handle RX transaction on non-ISO endpoint. - * This function implements TRM Figure 14-27. - * The ep argument is a physical endpoint number for a non-ISO OUT endpoint - * in the range 1 to 15. - */ -static void omap1510_udc_epn_rx (int ep) -{ - unsigned short status; - - /* Check endpoint status */ - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - int nbytes; - struct usb_endpoint_instance *endpoint = - omap1510_find_ep (ep); - - nbytes = omap1510_read_noniso_rx_fifo (endpoint); - usbd_rcv_complete (endpoint, nbytes, 0); - - /* enable rx FIFO to prepare for next packet */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } else if (status & UDC_STALL) { - UDCDBGA ("STALL on RX endpoint %d", ep); - } else if (status & UDC_NAK) { - UDCDBGA ("NAK on RX ep %d", ep); - } else { - serial_printf ("omap-bi: RX on ep %d with status %x", ep, - status); - } -} - -/* Handle TX transaction on non-ISO endpoint. - * This function implements TRM Figure 14-29. - * The ep argument is a physical endpoint number for a non-ISO IN endpoint - * in the range 16 to 30. - */ -static void omap1510_udc_epn_tx (int ep) -{ - unsigned short status; - - /*serial_printf("omap1510_udc_epn_tx( %x )\n",ep); */ - - /* Check endpoint status */ - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - struct usb_endpoint_instance *endpoint = - omap1510_find_ep (ep); - - /* We need to transmit a terminating zero-length packet now if - * we have sent all of the data in this URB and the transfer - * size was an exact multiple of the packet size. - */ - if (endpoint->tx_urb - && (endpoint->last == endpoint->tx_packetSize) - && (endpoint->tx_urb->actual_length - endpoint->sent - - endpoint->last == 0)) { - /* Prepare to transmit a zero-length packet. */ - endpoint->sent += endpoint->last; - /* write 0 bytes of data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } else if (endpoint->tx_urb - && endpoint->tx_urb->actual_length) { - /* retire the data that was just sent */ - usbd_tx_complete (endpoint); - /* Check to see if we have more data ready to transmit - * now. - */ - if (endpoint->tx_urb - && endpoint->tx_urb->actual_length) { - /* write data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } - } - } else if (status & UDC_STALL) { - UDCDBGA ("STALL on TX endpoint %d", ep); - } else if (status & UDC_NAK) { - UDCDBGA ("NAK on TX endpoint %d", ep); - } else { - /*serial_printf("omap-bi: TX on ep %d with status %x\n", ep, status); */ - } -} - - -/* -------------------------------------------------------------------------------- -*/ - -/* Handle general USB interrupts and dispatch according to type. - * This function implements TRM Figure 14-13. - */ -void omap1510_udc_irq (void) -{ - u16 irq_src = inw (UDC_IRQ_SRC); - int valid_irq = 0; - - if (!(irq_src & ~UDC_SOF_Flg)) /* ignore SOF interrupts ) */ - return; - - UDCDBGA ("< IRQ #%d start >- %x", udc_interrupts, irq_src); - /*serial_printf("< IRQ #%d start >- %x\n", udc_interrupts, irq_src); */ - - if (irq_src & UDC_DS_Chg) { - /* Device status changed */ - omap1510_udc_state_changed (); - valid_irq++; - } - if (irq_src & UDC_EP0_RX) { - /* Endpoint 0 receive */ - outw (UDC_EP0_RX, UDC_IRQ_SRC); /* ack interrupt */ - omap1510_udc_ep0_rx (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - if (irq_src & UDC_EP0_TX) { - /* Endpoint 0 transmit */ - outw (UDC_EP0_TX, UDC_IRQ_SRC); /* ack interrupt */ - omap1510_udc_ep0_tx (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - if (irq_src & UDC_Setup) { - /* Device setup */ - omap1510_udc_setup (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - /*if (!valid_irq) */ - /* serial_printf("unknown interrupt, IRQ_SRC %.4x\n", irq_src); */ - UDCDBGA ("< IRQ #%d end >", udc_interrupts); - udc_interrupts++; -} - -/* This function implements TRM Figure 14-26. */ -void omap1510_udc_noniso_irq (void) -{ - unsigned short epnum; - unsigned short irq_src = inw (UDC_IRQ_SRC); - int valid_irq = 0; - - if (!(irq_src & (UDC_EPn_RX | UDC_EPn_TX))) - return; - - UDCDBGA ("non-ISO IRQ, IRQ_SRC %x", inw (UDC_IRQ_SRC)); - - if (irq_src & UDC_EPn_RX) { /* Endpoint N OUT transaction */ - /* Determine the endpoint number for this interrupt */ - epnum = (inw (UDC_EPN_STAT) & 0x0f00) >> 8; - UDCDBGA ("RX on ep %x", epnum); - - /* acknowledge interrupt */ - outw (UDC_EPn_RX, UDC_IRQ_SRC); - - if (epnum) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | epnum, UDC_EP_NUM); - - omap1510_udc_epn_rx (epnum); - - /* deselect the endpoint FIFO */ - outw (epnum, UDC_EP_NUM); - } - valid_irq++; - } - if (irq_src & UDC_EPn_TX) { /* Endpoint N IN transaction */ - /* Determine the endpoint number for this interrupt */ - epnum = (inw (UDC_EPN_STAT) & 0x000f) | USB_DIR_IN; - UDCDBGA ("TX on ep %x", epnum); - - /* acknowledge interrupt */ - outw (UDC_EPn_TX, UDC_IRQ_SRC); - - if (epnum) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); - - omap1510_udc_epn_tx (epnum); - - /* deselect the endpoint FIFO */ - outw (UDC_EP_Dir | epnum, UDC_EP_NUM); - } - valid_irq++; - } - if (!valid_irq) - serial_printf (": unknown non-ISO interrupt, IRQ_SRC %.4x\n", - irq_src); -} - -/* -------------------------------------------------------------------------------- -*/ - - -/* - * Start of public functions. - */ - -/* Called to start packet transmission. */ -int udc_endpoint_write (struct usb_endpoint_instance *endpoint) -{ - unsigned short epnum = - endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("Starting transmit on ep %x", epnum); - - if (endpoint->tx_urb) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); - /* write data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the endpoint FIFO */ - outw (UDC_EP_Dir | epnum, UDC_EP_NUM); - } - - return 0; -} - -/* Start to initialize h/w stuff */ -int udc_init (void) -{ - u16 udc_rev; - uchar value; - ulong gpio; - int i; - - /* Let the device settle down before we start */ - for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000); - - udc_device = NULL; - - UDCDBG ("starting"); - - /* Check peripheral reset. Must be 1 to make sure - MPU TIPB peripheral reset is inactive */ - UDCREG (ARM_RSTCT2); - - /* Set and check clock control. - * We might ought to be using the clock control API to do - * this instead of fiddling with the clock registers directly - * here. - */ - outw ((1 << 4) | (1 << 5), CLOCK_CTRL); - UDCREG (CLOCK_CTRL); - -#ifdef CONFIG_OMAP1510 - /* This code was originally implemented for OMAP1510 and - * therefore is only applicable for OMAP1510 boards. For - * OMAP5912 or OMAP16xx the register APLL_CTRL does not - * exist and DPLL_CTRL is already configured. - */ - - /* Set and check APLL */ - outw (0x0008, APLL_CTRL); - UDCREG (APLL_CTRL); - /* Set and check DPLL */ - outw (0x2210, DPLL_CTRL); - UDCREG (DPLL_CTRL); -#endif - /* Set and check SOFT - * The below line of code has been changed to perform a - * read-modify-write instead of a simple write for - * configuring the SOFT_REQ register. This allows the code - * to be compatible with OMAP5912 and OMAP16xx devices - */ - outw ((1 << 4) | (1 << 3) | 1 | (inw(SOFT_REQ)), SOFT_REQ); - - /* Short delay to wait for DPLL */ - udelay (1000); - - /* Print banner with device revision */ - udc_rev = inw (UDC_REV) & 0xff; -#ifdef CONFIG_OMAP1510 - printf ("USB: TI OMAP1510 USB function module rev %d.%d\n", - udc_rev >> 4, udc_rev & 0xf); -#endif - -#ifdef CONFIG_OMAP1610 - printf ("USB: TI OMAP5912 USB function module rev %d.%d\n", - udc_rev >> 4, udc_rev & 0xf); -#endif - -#ifdef CONFIG_OMAP_SX1 - i2c_read (0x32, 0x04, 1, &value, 1); - value |= 0x04; - i2c_write (0x32, 0x04, 1, &value, 1); - - i2c_read (0x32, 0x03, 1, &value, 1); - value |= 0x01; - i2c_write (0x32, 0x03, 1, &value, 1); - - gpio = inl(GPIO_PIN_CONTROL_REG); - gpio |= 0x0002; /* A_IRDA_OFF */ - gpio |= 0x0800; /* A_SWITCH */ - gpio |= 0x8000; /* A_USB_ON */ - outl (gpio, GPIO_PIN_CONTROL_REG); - - gpio = inl(GPIO_DIR_CONTROL_REG); - gpio &= ~0x0002; /* A_IRDA_OFF */ - gpio &= ~0x0800; /* A_SWITCH */ - gpio &= ~0x8000; /* A_USB_ON */ - outl (gpio, GPIO_DIR_CONTROL_REG); - - gpio = inl(GPIO_DATA_OUTPUT_REG); - gpio |= 0x0002; /* A_IRDA_OFF */ - gpio &= ~0x0800; /* A_SWITCH */ - gpio &= ~0x8000; /* A_USB_ON */ - outl (gpio, GPIO_DATA_OUTPUT_REG); -#endif - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); - outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - /* - * At this point, device is ready for configuration... - */ - - UDCDBG ("disable USB interrupts"); - outw (0, UDC_IRQ_EN); - UDCREG (UDC_IRQ_EN); - - UDCDBG ("disable USB DMA"); - outw (0, UDC_DMA_IRQ_EN); - UDCREG (UDC_DMA_IRQ_EN); - - UDCDBG ("initialize SYSCON1"); - outw (UDC_Self_Pwr | UDC_Pullup_En, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); - - return 0; -} - -/* Stall endpoint */ -static void udc_stall_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("stall ep_addr %d", ep_addr); - - /* REVISIT? - * The OMAP TRM section 14.2.4.2 says we must check that the FIFO - * is empty before halting the endpoint. The current implementation - * doesn't check that the FIFO is empty. - */ - - if (!ep_num) { - outw (UDC_Stall_Cmd, UDC_SYSCON2); - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { - if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { - /* we have a valid rx endpoint, so halt it */ - outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); - outw (UDC_Set_Halt, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - } - } else { - if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { - /* we have a valid tx endpoint, so halt it */ - outw (UDC_EP_Sel | UDC_EP_Dir | ep_num, UDC_EP_NUM); - outw (UDC_Set_Halt, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - } - } -} - -/* Reset endpoint */ -#if 0 -static void udc_reset_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("reset ep_addr %d", ep_addr); - - if (!ep_num) { - /* control endpoint 0 can't be reset */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { - UDCDBGA ("UDC_EP_RX(%d) = 0x%04x", ep_num, - inw (UDC_EP_RX (ep_num))); - if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { - /* we have a valid rx endpoint, so reset it */ - outw (ep_num | UDC_EP_Sel, UDC_EP_NUM); - outw (UDC_Reset_EP, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - UDCDBGA ("OUT endpoint %d reset", ep_num); - } - } else { - UDCDBGA ("UDC_EP_TX(%d) = 0x%04x", ep_num, - inw (UDC_EP_TX (ep_num))); - /* Resetting of tx endpoints seems to be causing the USB function - * module to fail, which causes problems when the driver is - * uninstalled. We'll skip resetting tx endpoints for now until - * we figure out what the problem is. - */ -#if 0 - if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { - /* we have a valid tx endpoint, so reset it */ - outw (ep_num | UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - outw (UDC_Reset_EP, UDC_CTRL); - outw (ep_num | UDC_EP_Dir, UDC_EP_NUM); - UDCDBGA ("IN endpoint %d reset", ep_num); - } -#endif - } -} -#endif - -/* ************************************************************************** */ - -/** - * udc_check_ep - check logical endpoint - * - * Return physical endpoint number to use for this logical endpoint or zero if not valid. - */ -#if 0 -int udc_check_ep (int logical_endpoint, int packetsize) -{ - if ((logical_endpoint == 0x80) || - ((logical_endpoint & 0x8f) != logical_endpoint)) { - return 0; - } - - switch (packetsize) { - case 8: - case 16: - case 32: - case 64: - case 128: - case 256: - case 512: - break; - default: - return 0; - } - - return EP_ADDR_TO_PHYS_EP (logical_endpoint); -} -#endif - -/* - * udc_setup_ep - setup endpoint - * - * Associate a physical endpoint with endpoint_instance - */ -void udc_setup_ep (struct usb_device_instance *device, - unsigned int ep, struct usb_endpoint_instance *endpoint) -{ - UDCDBGA ("setting up endpoint addr %x", endpoint->endpoint_address); - - /* This routine gets called by bi_modinit for endpoint 0 and from - * bi_config for all of the other endpoints. bi_config gets called - * during the DEVICE_CREATE, DEVICE_CONFIGURED, and - * DEVICE_SET_INTERFACE events. We need to reconfigure the OMAP packet - * RAM after bi_config scans the selected device configuration and - * initializes the endpoint structures, but before this routine enables - * the OUT endpoint FIFOs. Since bi_config calls this routine in a - * loop for endpoints 1 through UDC_MAX_ENDPOINTS, we reconfigure our - * packet RAM here when ep==1. - * I really hate to do this here, but it seems like the API exported - * by the USB bus interface controller driver to the usbd-bi module - * isn't quite right so there is no good place to do this. - */ - if (ep == 1) { - omap1510_deconfigure_device (); - omap1510_configure_device (device); - } - - if (endpoint && (ep < UDC_MAX_ENDPOINTS)) { - int ep_addr = endpoint->endpoint_address; - - if (!ep_addr) { - /* nothing to do for endpoint 0 */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* nothing to do for IN (tx) endpoints */ - } else { /* OUT (rx) endpoint */ - if (endpoint->rcv_packetSize) { - /*struct urb* urb = &(urb_out_array[ep&0xFF]); */ - /*urb->endpoint = endpoint; */ - /*urb->device = device; */ - /*urb->buffer_length = sizeof(urb->buffer); */ - - /*endpoint->rcv_urb = urb; */ - omap1510_prepare_endpoint_for_rx (ep_addr); - } - } - } -} - -/** - * udc_disable_ep - disable endpoint - * @ep: - * - * Disable specified endpoint - */ -#if 0 -void udc_disable_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - struct usb_endpoint_instance *endpoint = omap1510_find_ep (ep_addr); /*udc_device->bus->endpoint_array + ep; */ - - UDCDBGA ("disable ep_addr %d", ep_addr); - - if (!ep_num) { - /* nothing to do for endpoint 0 */ ; - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - if (endpoint->tx_packetSize) { - /* we have a valid tx endpoint */ - /*usbd_flush_tx(endpoint); */ - endpoint->tx_urb = NULL; - } - } else { - if (endpoint->rcv_packetSize) { - /* we have a valid rx endpoint */ - /*usbd_flush_rcv(endpoint); */ - endpoint->rcv_urb = NULL; - } - } -} -#endif - -/* ************************************************************************** */ - -/** - * udc_connected - is the USB cable connected - * - * Return non-zero if cable is connected. - */ -#if 0 -int udc_connected (void) -{ - return ((inw (UDC_DEVSTAT) & UDC_ATT) == UDC_ATT); -} -#endif - -/* Turn on the USB connection by enabling the pullup resistor */ -void udc_connect (void) -{ - UDCDBG ("connect, enable Pullup"); - outl (0x00000018, FUNC_MUX_CTRL_D); -} - -/* Turn off the USB connection by disabling the pullup resistor */ -void udc_disconnect (void) -{ - UDCDBG ("disconnect, disable Pullup"); - outl (0x00000000, FUNC_MUX_CTRL_D); -} - -/* ************************************************************************** */ - - -/* - * udc_disable_interrupts - disable interrupts - * switch off interrupts - */ -#if 0 -void udc_disable_interrupts (struct usb_device_instance *device) -{ - UDCDBG ("disabling all interrupts"); - outw (0, UDC_IRQ_EN); -} -#endif - -/* ************************************************************************** */ - -/** - * udc_ep0_packetsize - return ep0 packetsize - */ -#if 0 -int udc_ep0_packetsize (void) -{ - return EP0_PACKETSIZE; -} -#endif - -/* Switch on the UDC */ -void udc_enable (struct usb_device_instance *device) -{ - UDCDBGA ("enable device %p, status %d", device, device->status); - - /* initialize driver state variables */ - udc_devstat = 0; - - /* Save the device structure pointer */ - udc_device = device; - - /* Setup ep0 urb */ - if (!ep0_urb) { - ep0_urb = - usbd_alloc_urb (udc_device, - udc_device->bus->endpoint_array); - } else { - serial_printf ("udc_enable: ep0_urb already allocated %p\n", - ep0_urb); - } - - UDCDBG ("Check clock status"); - UDCREG (STATUS_REQ); - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_CTRL | UDC_VBUS_MODE, - FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - omap1510_configure_device (device); -} - -/* Switch off the UDC */ -void udc_disable (void) -{ - UDCDBG ("disable UDC"); - - omap1510_deconfigure_device (); - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); - outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - /* Free ep0 URB */ - if (ep0_urb) { - /*usbd_dealloc_urb(ep0_urb); */ - ep0_urb = NULL; - } - - /* Reset device pointer. - * We ought to do this here to balance the initialization of udc_device - * in udc_enable, but some of our other exported functions get called - * by the bus interface driver after udc_disable, so we have to hang on - * to the device pointer to avoid a null pointer dereference. */ - /* udc_device = NULL; */ -} - -/** - * udc_startup - allow udc code to do any additional startup - */ -void udc_startup_events (struct usb_device_instance *device) -{ - /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ - usbd_device_event_irq (device, DEVICE_INIT, 0); - - /* The DEVICE_CREATE event puts the USB device in the state - * STATE_ATTACHED. - */ - usbd_device_event_irq (device, DEVICE_CREATE, 0); - - /* Some USB controller driver implementations signal - * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. - * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, - * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. - * The OMAP USB client controller has the capability to detect when the - * USB cable is connected to a powered USB bus via the ATT bit in the - * DEVSTAT register, so we will defer the DEVICE_HUB_CONFIGURED and - * DEVICE_RESET events until later. - */ - - udc_enable (device); -} - -/** - * udc_irq - do pseudo interrupts - */ -void udc_irq(void) -{ - /* Loop while we have interrupts. - * If we don't do this, the input chain - * polling delay is likely to miss - * host requests. - */ - while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) { - /* Handle any new IRQs */ - omap1510_udc_irq (); - omap1510_udc_noniso_irq (); - } -} - -/* Flow control */ -void udc_set_nak(int epid) -{ - /* TODO: implement this functionality in omap1510 */ -} - -void udc_unset_nak (int epid) -{ - /* TODO: implement this functionality in omap1510 */ -} diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c index 8945c5b665..d4460b2dc7 100644 --- a/drivers/usb/gadget/pxa25x_udc.c +++ b/drivers/usb/gadget/pxa25x_udc.c @@ -1950,11 +1950,11 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */ dev->watchdog.function = udc_watchdog; + dev->mach = &mach_info; + udc_disable(dev); udc_reinit(dev); - dev->mach = &mach_info; - dev->gadget.name = "pxa2xx_udc"; retval = driver->bind(&dev->gadget); if (retval) { diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index 05d1b56667..9423555280 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "ep0.h" @@ -64,7 +65,8 @@ static int udc_write_urb(struct usb_endpoint_instance *endpoint) if (!urb || !urb->actual_length) return -1; - n = MIN(urb->actual_length - endpoint->sent, endpoint->tx_packetSize); + n = min_t(unsigned int, urb->actual_length - endpoint->sent, + endpoint->tx_packetSize); if (n <= 0) return -1; diff --git a/drivers/usb/gadget/regs-otg.h b/drivers/usb/gadget/regs-otg.h index 84bfcc5a01..ac5d11213d 100644 --- a/drivers/usb/gadget/regs-otg.h +++ b/drivers/usb/gadget/regs-otg.h @@ -226,6 +226,11 @@ struct s3c_usbotg_reg { #define CLK_SEL_12MHZ (0x2 << 0) #define CLK_SEL_48MHZ (0x0 << 0) +#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3) +#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4) +#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0) +#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0) + /* Device Configuration Register DCFG */ #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0) #define DEV_SPEED_FULL_SPEED_20 (0x1 << 0) diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index 7e2020915e..7653f03949 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -31,7 +31,6 @@ #include #include -#include #include "regs-otg.h" #include @@ -105,7 +104,7 @@ static void stop_activity(struct s3c_udc *dev, struct usb_gadget_driver *driver); static int udc_enable(struct s3c_udc *dev); static void udc_set_address(struct s3c_udc *dev, unsigned char address); -static void reconfig_usbd(void); +static void reconfig_usbd(struct s3c_udc *dev); static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed); static void nuke(struct s3c_ep *ep, int status); static int s3c_udc_set_halt(struct usb_ep *_ep, int value); @@ -146,58 +145,14 @@ static struct usb_ep_ops s3c_ep_ops = { void __iomem *regs_otg; struct s3c_usbotg_reg *reg; -struct s3c_usbotg_phy *phy; -static unsigned int usb_phy_ctrl; -void otg_phy_init(struct s3c_udc *dev) +bool dfu_usb_get_reset(void) { - dev->pdata->phy_control(1); - - /*USB PHY0 Enable */ - printf("USB PHY0 Enable\n"); - - /* Enable PHY */ - writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); - - if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */ - writel((readl(&phy->phypwr) - &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN) - &~FORCE_SUSPEND_0), &phy->phypwr); - else /* C110 GONI */ - writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) - &~FORCE_SUSPEND_0), &phy->phypwr); - - writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) | - CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ - - writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) - | PHY_SW_RST0, &phy->rstcon); - udelay(10); - writel(readl(&phy->rstcon) - &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon); - udelay(10); + return !!(readl(®->gintsts) & INT_RESET); } -void otg_phy_off(struct s3c_udc *dev) -{ - /* reset controller just in case */ - writel(PHY_SW_RST0, &phy->rstcon); - udelay(20); - writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); - udelay(20); - - writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN - | FORCE_SUSPEND_0, &phy->phypwr); - - writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); - - writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)), - &phy->phyclk); - - udelay(10000); - - dev->pdata->phy_control(0); -} +__weak void otg_phy_init(struct s3c_udc *dev) {} +__weak void otg_phy_off(struct s3c_udc *dev) {} /***********************************************************/ @@ -260,7 +215,7 @@ static int udc_enable(struct s3c_udc *dev) debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); otg_phy_init(dev); - reconfig_usbd(); + reconfig_usbd(dev); debug_cond(DEBUG_SETUP != 0, "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n", @@ -278,7 +233,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) { struct s3c_udc *dev = the_controller; int retval = 0; - unsigned long flags; + unsigned long flags = 0; debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name"); @@ -326,7 +281,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) { struct s3c_udc *dev = the_controller; - unsigned long flags; + unsigned long flags = 0; if (!dev) return -ENODEV; @@ -441,15 +396,17 @@ static void stop_activity(struct s3c_udc *dev, udc_reinit(dev); } -static void reconfig_usbd(void) +static void reconfig_usbd(struct s3c_udc *dev) { /* 2. Soft-reset OTG Core and then unreset again. */ int i; unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl); + uint32_t dflt_gusbcfg; debug("Reseting OTG controller\n"); - writel(0<<15 /* PHY Low Power Clock sel*/ + dflt_gusbcfg = + 0<<15 /* PHY Low Power Clock sel*/ |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/ |0x5<<10 /* Turnaround time*/ |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/ @@ -458,8 +415,12 @@ static void reconfig_usbd(void) |0<<6 /* 0: high speed utmi+, 1: full speed serial*/ |0<<4 /* 0: utmi+, 1:ulpi*/ |1<<3 /* phy i/f 0:8bit, 1:16bit*/ - |0x7<<0, /* HS/FS Timeout**/ - ®->gusbcfg); + |0x7<<0; /* HS/FS Timeout**/ + + if (dev->pdata->usb_gusbcfg) + dflt_gusbcfg = dev->pdata->usb_gusbcfg; + + writel(dflt_gusbcfg, ®->gusbcfg); /* 3. Put the OTG device core in the disconnected state.*/ uTemp = readl(®->dctl); @@ -570,7 +531,7 @@ static int s3c_ep_enable(struct usb_ep *_ep, { struct s3c_ep *ep; struct s3c_udc *dev; - unsigned long flags; + unsigned long flags = 0; debug("%s: %p\n", __func__, _ep); @@ -634,7 +595,7 @@ static int s3c_ep_enable(struct usb_ep *_ep, static int s3c_ep_disable(struct usb_ep *_ep) { struct s3c_ep *ep; - unsigned long flags; + unsigned long flags = 0; debug("%s: %p\n", __func__, _ep); @@ -692,7 +653,7 @@ static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct s3c_ep *ep; struct s3c_request *req; - unsigned long flags; + unsigned long flags = 0; debug("%s: %p\n", __func__, _ep); @@ -838,15 +799,13 @@ static struct s3c_udc memory = { int s3c_udc_probe(struct s3c_plat_otg_data *pdata) { struct s3c_udc *dev = &memory; - int retval = 0, i; + int retval = 0; debug("%s: %p\n", __func__, pdata); dev->pdata = pdata; - phy = (struct s3c_usbotg_phy *)pdata->regs_phy; reg = (struct s3c_usbotg_reg *)pdata->regs_otg; - usb_phy_ctrl = pdata->usb_phy_ctrl; /* regs_otg = (void *)pdata->regs_otg; */ @@ -859,16 +818,15 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata) the_controller = dev; - for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) { - dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE, - DMA_BUFFER_SIZE); - dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i]; - invalidate_dcache_range((unsigned long) dev->dma_buf[i], - (unsigned long) (dev->dma_buf[i] - + DMA_BUFFER_SIZE)); + usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE, + ROUND(sizeof(struct usb_ctrlrequest), + CONFIG_SYS_CACHELINE_SIZE)); + if (!usb_ctrl) { + error("No memory available for UDC!\n"); + return -ENOMEM; } - usb_ctrl = dev->dma_buf[0]; - usb_ctrl_dma_addr = dev->dma_addr[0]; + + usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl; udc_reinit(dev); diff --git a/drivers/usb/gadget/s3c_udc_otg_phy.c b/drivers/usb/gadget/s3c_udc_otg_phy.c new file mode 100644 index 0000000000..f13cb8910a --- /dev/null +++ b/drivers/usb/gadget/s3c_udc_otg_phy.c @@ -0,0 +1,101 @@ +/* + * drivers/usb/gadget/s3c_udc_otg.c + * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers + * + * Copyright (C) 2008 for Samsung Electronics + * + * BSP Support for Samsung's UDC driver + * available at: + * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git + * + * State machine bugfixes: + * Marek Szyprowski + * + * Ported to u-boot: + * Marek Szyprowski + * Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include "regs-otg.h" +#include + +#include + +void otg_phy_init(struct s3c_udc *dev) +{ + unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl; + struct s3c_usbotg_phy *phy = + (struct s3c_usbotg_phy *)dev->pdata->regs_phy; + + dev->pdata->phy_control(1); + + /* USB PHY0 Enable */ + printf("USB PHY0 Enable\n"); + + /* Enable PHY */ + writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); + + if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */ + writel((readl(&phy->phypwr) + &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN) + &~FORCE_SUSPEND_0), &phy->phypwr); + else /* C110 GONI */ + writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) + &~FORCE_SUSPEND_0), &phy->phypwr); + + if (s5p_cpu_id == 0x4412) + writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | + EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ, + &phy->phyclk); /* PLL 24Mhz */ + else + writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | + CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ + + writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) + | PHY_SW_RST0, &phy->rstcon); + udelay(10); + writel(readl(&phy->rstcon) + &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon); + udelay(10); +} + +void otg_phy_off(struct s3c_udc *dev) +{ + unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl; + struct s3c_usbotg_phy *phy = + (struct s3c_usbotg_phy *)dev->pdata->regs_phy; + + /* reset controller just in case */ + writel(PHY_SW_RST0, &phy->rstcon); + udelay(20); + writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); + udelay(20); + + writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN + | FORCE_SUSPEND_0, &phy->phypwr); + + writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); + + writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)), + &phy->phyclk); + + udelay(10000); + + dev->pdata->phy_control(0); +} diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index d7af5e9034..7e7a2c2d90 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -29,10 +29,6 @@ static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev) { u32 ep_ctrl; - flush_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz); @@ -52,10 +48,6 @@ void s3c_udc_pre_setup(void) debug_cond(DEBUG_IN_EP, "%s : Prepare Setup packets.\n", __func__); - invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); @@ -82,10 +74,6 @@ static inline void s3c_ep0_complete_out(void) debug_cond(DEBUG_IN_EP, "%s : Prepare Complete Out packet.\n", __func__); - invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); @@ -109,26 +97,20 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) u32 ep_num = ep_index(ep); buf = req->req.buf + req->req.actual; - - length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket); + length = min_t(u32, req->req.length - req->req.actual, + ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); ep->len = length; ep->dma_buf = buf; - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num], - (unsigned long) ep->dev->dma_buf[ep_num] - + DMA_BUFFER_SIZE); - - if (length == 0) + if (ep_num == EP0_CON || length == 0) pktcnt = 1; else pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; - pktcnt = 1; ctrl = readl(®->out_endp[ep_num].doepctl); - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->out_endp[ep_num].doepdma); + writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz); writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); @@ -151,7 +133,6 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) u32 *buf, ctrl = 0; u32 length, pktcnt; u32 ep_num = ep_index(ep); - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; buf = req->req.buf + req->req.actual; length = req->req.length - req->req.actual; @@ -161,10 +142,10 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) ep->len = length; ep->dma_buf = buf; - memcpy(p, ep->dma_buf, length); - flush_dcache_range((unsigned long) p , - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); if (length == 0) pktcnt = 1; @@ -177,8 +158,7 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) while (readl(®->grstctl) & TX_FIFO_FLUSH) ; - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->in_endp[ep_num].diepdma); + writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), ®->in_endp[ep_num].dieptsiz); @@ -211,7 +191,6 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) struct s3c_ep *ep = &dev->ep[ep_num]; struct s3c_request *req = NULL; u32 ep_tsr = 0, xfer_size = 0, is_short = 0; - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; if (list_empty(&ep->queue)) { debug_cond(DEBUG_OUT_EP != 0, @@ -231,10 +210,23 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) xfer_size = ep->len - xfer_size; - invalidate_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); - - memcpy(ep->dma_buf, p, ep->len); + /* + * NOTE: + * + * Please be careful with proper buffer allocation for USB request, + * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only + * with starting address, but also its size shall be a cache line + * multiplication. + * + * This will prevent from corruption of data allocated immediatelly + * before or after the buffer. + * + * For armv7, the cache_v7.c provides proper code to emit "ERROR" + * message to warn users. + */ + invalidate_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE)); req->req.actual += min(xfer_size, req->req.length - req->req.actual); is_short = (xfer_size < ep->ep.maxpacket); @@ -474,7 +466,7 @@ static int s3c_udc_irq(int irq, void *_dev) struct s3c_udc *dev = _dev; u32 intr_status; u32 usb_status, gintmsk; - unsigned long flags; + unsigned long flags = 0; spin_lock_irqsave(&dev->lock, flags); @@ -559,7 +551,7 @@ static int s3c_udc_irq(int irq, void *_dev) debug_cond(DEBUG_ISR, "\t\tOTG core got reset (%d)!!\n", reset_available); - reconfig_usbd(); + reconfig_usbd(dev); dev->ep0state = WAIT_FOR_SETUP; reset_available = 0; s3c_udc_pre_setup(); @@ -593,7 +585,7 @@ static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req, struct s3c_request *req; struct s3c_ep *ep; struct s3c_udc *dev; - unsigned long flags; + unsigned long flags = 0; u32 ep_num, gintsts; req = container_of(_req, struct s3c_request, req); @@ -728,19 +720,14 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) { - u32 bytes; - - bytes = sizeof(struct usb_ctrlrequest); - - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)], - (unsigned long) ep->dev->dma_buf[ep_index(ep)] - + DMA_BUFFER_SIZE); + invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + + ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); debug_cond(DEBUG_EP0 != 0, - "%s: bytes=%d, ep_index=%d %p\n", __func__, - bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]); + "%s: bytes=%d, ep_index=%d 0x%p\n", __func__, + max, ep_index(ep), cp); - return bytes; + return max; } /** @@ -872,14 +859,12 @@ static int s3c_ep0_write(struct s3c_udc *dev) return 1; } -u16 g_status; - int s3c_udc_get_status(struct s3c_udc *dev, struct usb_ctrlrequest *crq) { u8 ep_num = crq->wIndex & 0x7F; + u16 g_status = 0; u32 ep_ctrl; - u32 *p = the_controller->dma_buf[1]; debug_cond(DEBUG_SETUP != 0, "%s: *** USB_REQ_GET_STATUS\n", __func__); @@ -917,12 +902,13 @@ int s3c_udc_get_status(struct s3c_udc *dev, return 1; } - memcpy(p, &g_status, sizeof(g_status)); + memcpy(usb_ctrl, &g_status, sizeof(g_status)); - flush_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) usb_ctrl, + (unsigned long) usb_ctrl + + ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); - writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma); + writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), ®->in_endp[EP0_CON].dieptsiz); @@ -1047,7 +1033,7 @@ static int s3c_udc_set_halt(struct usb_ep *_ep, int value) { struct s3c_ep *ep; struct s3c_udc *dev; - unsigned long flags; + unsigned long flags = 0; u8 ep_num; ep = container_of(_ep, struct s3c_ep, ep); diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c index 866e7c7b8a..b55e40bbda 100644 --- a/drivers/usb/gadget/storage_common.c +++ b/drivers/usb/gadget/storage_common.c @@ -267,15 +267,9 @@ struct interrupt_data { #define ASCQ(x) ((u8) (x)) struct device_attribute { int i; }; -struct rw_semaphore { int i; }; -#define down_write(...) do { } while (0) -#define up_write(...) do { } while (0) -#define down_read(...) do { } while (0) -#define up_read(...) do { } while (0) #define ETOOSMALL 525 #include -extern struct ums_board_info *ums_info; /*-------------------------------------------------------------------------*/ @@ -573,36 +567,16 @@ static struct usb_gadget_strings fsg_stringtab = { static int fsg_lun_open(struct fsg_lun *curlun, const char *filename) { int ro; - int rc = -EINVAL; - loff_t size; - loff_t num_sectors; - loff_t min_sectors; /* R/W if we can, R/O if we must */ ro = curlun->initially_ro; - ums_info->get_capacity(&(ums_info->ums_dev), &size); - if (size < 0) { - printf("unable to find file size: %s\n", filename); - rc = (int) size; - goto out; - } - num_sectors = size >> 9; /* File size in 512-byte blocks */ - min_sectors = 1; - if (num_sectors < min_sectors) { - printf("file too small: %s\n", filename); - rc = -ETOOSMALL; - goto out; - } - curlun->ro = ro; - curlun->file_length = size; - curlun->num_sectors = num_sectors; + curlun->file_length = ums->num_sectors << 9; + curlun->num_sectors = ums->num_sectors; debug("open backing file: %s\n", filename); - rc = 0; -out: - return rc; + return 0; } static void fsg_lun_close(struct fsg_lun *curlun) diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c index de5fa3f648..8c3ff64fe3 100644 --- a/drivers/usb/gadget/usbstring.c +++ b/drivers/usb/gadget/usbstring.c @@ -108,6 +108,9 @@ usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf) struct usb_string *s; int len; + if (!table) + return -EINVAL; + /* descriptor 0 has the language id */ if (id == 0) { buf[0] = 4; diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig new file mode 100644 index 0000000000..30d1457638 --- /dev/null +++ b/drivers/usb/host/Kconfig @@ -0,0 +1,56 @@ +# +# USB Host Controller Drivers +# +comment "USB Host Controller Drivers" + +config USB_XHCI_HCD + bool "xHCI HCD (USB 3.0) support" + ---help--- + The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 + "SuperSpeed" host controller hardware. + +config USB_XHCI + bool + default USB_XHCI_HCD + ---help--- + TODO: rename after most boards switch to Kconfig + +if USB_XHCI_HCD + +endif + +config USB_EHCI_HCD + bool "EHCI HCD (USB 2.0) support" + ---help--- + The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 + "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. + If your USB host controller supports USB 2.0, you will likely want to + configure this Host Controller Driver. + + EHCI controllers are packaged with "companion" host controllers (OHCI + or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports + will connect to EHCI if the device is high speed, otherwise they + connect to a companion controller. If you configure EHCI, you should + probably configure the OHCI (for NEC and some other vendors) USB Host + Controller Driver or UHCI (for Via motherboards) Host Controller + Driver too. + + You may want to read . + +config USB_EHCI + bool + default USB_EHCI_HCD + ---help--- + TODO: rename after most boards switch to Kconfig + +if USB_EHCI_HCD + +config USB_EHCI_UNIPHIER + bool "Support for Panasonic UniPhier on-chip EHCI USB controller" + depends on ARCH_UNIPHIER + default y + ---help--- + Enables support for the on-chip EHCI controller on Panasonic + UniPhier SoCs. + +endif diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index ff6c80e66f..c11b551620 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -5,57 +5,48 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libusb_host.o - # ohci -COBJS-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o -COBJS-$(CONFIG_USB_ATMEL) += ohci-at91.o -COBJS-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o -COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o -COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o -COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o -COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o +obj-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o +obj-$(CONFIG_USB_ATMEL) += ohci-at91.o +obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o +obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o +obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o +obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o +obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o +obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o # echi -COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o -COBJS-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o -COBJS-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o +obj-$(CONFIG_USB_EHCI) += ehci-hcd.o +obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o +obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o ifdef CONFIG_MPC512X -COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o +obj-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o else -COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o +obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif -COBJS-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o -COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o -COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o -COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o -COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o -COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o -COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o -COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o -COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o -COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o -COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o -COBJS-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o -COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o -COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o +obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o +obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o +obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o +obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o +obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o +obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o +obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o +obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o +obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o +obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o +obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o +obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o +obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o +obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o +obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o +obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o + +# xhci +obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o +obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o +obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o +obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o + +# designware +obj-$(CONFIG_USB_DWC2) += dwc2.o diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c new file mode 100644 index 0000000000..e8142ac092 --- /dev/null +++ b/drivers/usb/host/dwc2.c @@ -0,0 +1,1053 @@ +/* + * Copyright (C) 2012 Oleksandr Tymoshenko + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "dwc2.h" + +/* Use only HC channel 0. */ +#define DWC2_HC_CHANNEL 0 + +#define DWC2_STATUS_BUF_SIZE 64 +#define DWC2_DATA_BUF_SIZE (64 * 1024) + +/* We need doubleword-aligned buffers for DMA transfers */ +DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8); +DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8); + +#define MAX_DEVICE 16 +#define MAX_ENDPOINT 16 +static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; +static int control_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; + +static int root_hub_devnum; + +static struct dwc2_core_regs *regs = + (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; + +/* + * DWC2 IP interface + */ +static int wait_for_bit(void *reg, const uint32_t mask, bool set) +{ + unsigned int timeout = 1000000; + uint32_t val; + + while (--timeout) { + val = readl(reg); + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + udelay(1); + } + + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", + __func__, reg, mask, set); + + return -ETIMEDOUT; +} + +/* + * Initializes the FSLSPClkSel field of the HCFG register + * depending on the PHY type. + */ +static void init_fslspclksel(struct dwc2_core_regs *regs) +{ + uint32_t phyclk; + +#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) + phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ +#else + /* High speed PHY running at full speed or high speed */ + phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; +#endif + +#ifdef CONFIG_DWC2_ULPI_FS_LS + uint32_t hwcfg2 = readl(®s->ghwcfg2); + uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> + DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; + uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> + DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; + + if (hval == 2 && fval == 1) + phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ +#endif + + clrsetbits_le32(®s->host_regs.hcfg, + DWC2_HCFG_FSLSPCLKSEL_MASK, + phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); +} + +/* + * Flush a Tx FIFO. + * + * @param regs Programming view of DWC_otg controller. + * @param num Tx FIFO to flush. + */ +static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) +{ + int ret; + + writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), + ®s->grstctl); + ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0); + if (ret) + printf("%s: Timeout!\n", __func__); + + /* Wait for 3 PHY Clocks */ + udelay(1); +} + +/* + * Flush Rx FIFO. + * + * @param regs Programming view of DWC_otg controller. + */ +static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) +{ + int ret; + + writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); + ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0); + if (ret) + printf("%s: Timeout!\n", __func__); + + /* Wait for 3 PHY Clocks */ + udelay(1); +} + +/* + * Do core a soft reset of the core. Be careful with this because it + * resets all the internal state machines of the core. + */ +static void dwc_otg_core_reset(struct dwc2_core_regs *regs) +{ + int ret; + + /* Wait for AHB master IDLE state. */ + ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1); + if (ret) + printf("%s: Timeout!\n", __func__); + + /* Core Soft Reset */ + writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); + ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0); + if (ret) + printf("%s: Timeout!\n", __func__); + + /* + * Wait for core to come out of reset. + * NOTE: This long sleep is _very_ important, otherwise the core will + * not stay in host mode after a connector ID change! + */ + mdelay(100); +} + +/* + * This function initializes the DWC_otg controller registers for + * host mode. + * + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the + * request queues. Host channels are reset to ensure that they are ready for + * performing transfers. + * + * @param regs Programming view of DWC_otg controller + * + */ +static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) +{ + uint32_t nptxfifosize = 0; + uint32_t ptxfifosize = 0; + uint32_t hprt0 = 0; + int i, ret, num_channels; + + /* Restart the Phy Clock */ + writel(0, ®s->pcgcctl); + + /* Initialize Host Configuration Register */ + init_fslspclksel(regs); +#ifdef CONFIG_DWC2_DFLT_SPEED_FULL + setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); +#endif + + /* Configure data FIFO sizes */ +#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO + if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { + /* Rx FIFO */ + writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); + + /* Non-periodic Tx FIFO */ + nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << + DWC2_FIFOSIZE_DEPTH_OFFSET; + nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << + DWC2_FIFOSIZE_STARTADDR_OFFSET; + writel(nptxfifosize, ®s->gnptxfsiz); + + /* Periodic Tx FIFO */ + ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << + DWC2_FIFOSIZE_DEPTH_OFFSET; + ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + + CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << + DWC2_FIFOSIZE_STARTADDR_OFFSET; + writel(ptxfifosize, ®s->hptxfsiz); + } +#endif + + /* Clear Host Set HNP Enable in the OTG Control Register */ + clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); + + /* Make sure the FIFOs are flushed. */ + dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ + dwc_otg_flush_rx_fifo(regs); + + /* Flush out any leftover queued requests. */ + num_channels = readl(®s->ghwcfg2); + num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; + num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; + num_channels += 1; + + for (i = 0; i < num_channels; i++) + clrsetbits_le32(®s->hc_regs[i].hcchar, + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, + DWC2_HCCHAR_CHDIS); + + /* Halt all channels to put them into a known state. */ + for (i = 0; i < num_channels; i++) { + clrsetbits_le32(®s->hc_regs[i].hcchar, + DWC2_HCCHAR_EPDIR, + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); + ret = wait_for_bit(®s->hc_regs[i].hcchar, + DWC2_HCCHAR_CHEN, 0); + if (ret) + printf("%s: Timeout!\n", __func__); + } + + /* Turn on the vbus power. */ + if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { + hprt0 = readl(®s->hprt0); + hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); + hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); + if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { + hprt0 |= DWC2_HPRT0_PRTPWR; + writel(hprt0, ®s->hprt0); + } + } +} + +/* + * This function initializes the DWC_otg controller registers and + * prepares the core for device mode or host mode operation. + * + * @param regs Programming view of the DWC_otg controller + */ +static void dwc_otg_core_init(struct dwc2_core_regs *regs) +{ + uint32_t ahbcfg = 0; + uint32_t usbcfg = 0; + uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; + + /* Common Initialization */ + usbcfg = readl(®s->gusbcfg); + + /* Program the ULPI External VBUS bit if needed */ +#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS + usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; +#else + usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; +#endif + + /* Set external TS Dline pulsing */ +#ifdef CONFIG_DWC2_TS_DLINE + usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; +#else + usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; +#endif + writel(usbcfg, ®s->gusbcfg); + + /* Reset the Controller */ + dwc_otg_core_reset(regs); + + /* + * This programming sequence needs to happen in FS mode before + * any other programming occurs + */ +#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ + (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) + /* If FS mode with FS PHY */ + setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); + + /* Reset after a PHY select */ + dwc_otg_core_reset(regs); + + /* + * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. + * Also do this on HNP Dev/Host mode switches (done in dev_init + * and host_init). + */ + if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) + init_fslspclksel(regs); + +#ifdef CONFIG_DWC2_I2C_ENABLE + /* Program GUSBCFG.OtgUtmifsSel to I2C */ + setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); + + /* Program GI2CCTL.I2CEn */ + clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | + DWC2_GI2CCTL_I2CDEVADDR_MASK, + 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); + setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); +#endif + +#else + /* High speed PHY. */ + + /* + * HS PHY parameters. These parameters are preserved during + * soft reset so only program the first time. Do a soft reset + * immediately after setting phyif. + */ + usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); + usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; + + if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ +#ifdef CONFIG_DWC2_PHY_ULPI_DDR + usbcfg |= DWC2_GUSBCFG_DDRSEL; +#else + usbcfg &= ~DWC2_GUSBCFG_DDRSEL; +#endif + } else { /* UTMI+ interface */ +#if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) + usbcfg |= DWC2_GUSBCFG_PHYIF; +#endif + } + + writel(usbcfg, ®s->gusbcfg); + + /* Reset after setting the PHY parameters */ + dwc_otg_core_reset(regs); +#endif + + usbcfg = readl(®s->gusbcfg); + usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); +#ifdef CONFIG_DWC2_ULPI_FS_LS + uint32_t hwcfg2 = readl(®s->ghwcfg2); + uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> + DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; + uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> + DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; + if (hval == 2 && fval == 1) { + usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; + usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; + } +#endif + writel(usbcfg, ®s->gusbcfg); + + /* Program the GAHBCFG Register. */ + switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { + case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: + break; + case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: + while (brst_sz > 1) { + ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); + ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; + brst_sz >>= 1; + } + +#ifdef CONFIG_DWC2_DMA_ENABLE + ahbcfg |= DWC2_GAHBCFG_DMAENABLE; +#endif + break; + + case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: + ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; +#ifdef CONFIG_DWC2_DMA_ENABLE + ahbcfg |= DWC2_GAHBCFG_DMAENABLE; +#endif + break; + } + + writel(ahbcfg, ®s->gahbcfg); + + /* Program the GUSBCFG register for HNP/SRP. */ + setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP); + +#ifdef CONFIG_DWC2_IC_USB_CAP + setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP); +#endif +} + +/* + * Prepares a host channel for transferring packets to/from a specific + * endpoint. The HCCHARn register is set up with the characteristics specified + * in _hc. Host channel interrupts that may need to be serviced while this + * transfer is in progress are enabled. + * + * @param regs Programming view of DWC_otg controller + * @param hc Information needed to initialize the host channel + */ +static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, + uint8_t dev_addr, uint8_t ep_num, uint8_t ep_is_in, + uint8_t ep_type, uint16_t max_packet) +{ + struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; + const uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | + (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | + (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | + (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | + (max_packet << DWC2_HCCHAR_MPS_OFFSET); + + /* Clear old interrupt conditions for this host channel. */ + writel(0x3fff, &hc_regs->hcint); + + /* + * Program the HCCHARn register with the endpoint characteristics + * for the current transfer. + */ + writel(hcchar, &hc_regs->hcchar); + + /* Program the HCSPLIT register for SPLITs */ + writel(0, &hc_regs->hcsplt); +} + +/* + * DWC2 to USB API interface + */ +/* Direction: In ; Request: Status */ +static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer, + int txlen, struct devrequest *cmd) +{ + uint32_t hprt0 = 0; + uint32_t port_status = 0; + uint32_t port_change = 0; + int len = 0; + int stat = 0; + + switch (cmd->requesttype & ~USB_DIR_IN) { + case 0: + *(uint16_t *)buffer = cpu_to_le16(1); + len = 2; + break; + case USB_RECIP_INTERFACE: + case USB_RECIP_ENDPOINT: + *(uint16_t *)buffer = cpu_to_le16(0); + len = 2; + break; + case USB_TYPE_CLASS: + *(uint32_t *)buffer = cpu_to_le32(0); + len = 4; + break; + case USB_RECIP_OTHER | USB_TYPE_CLASS: + hprt0 = readl(®s->hprt0); + if (hprt0 & DWC2_HPRT0_PRTCONNSTS) + port_status |= USB_PORT_STAT_CONNECTION; + if (hprt0 & DWC2_HPRT0_PRTENA) + port_status |= USB_PORT_STAT_ENABLE; + if (hprt0 & DWC2_HPRT0_PRTSUSP) + port_status |= USB_PORT_STAT_SUSPEND; + if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) + port_status |= USB_PORT_STAT_OVERCURRENT; + if (hprt0 & DWC2_HPRT0_PRTRST) + port_status |= USB_PORT_STAT_RESET; + if (hprt0 & DWC2_HPRT0_PRTPWR) + port_status |= USB_PORT_STAT_POWER; + + port_status |= USB_PORT_STAT_HIGH_SPEED; + + if (hprt0 & DWC2_HPRT0_PRTENCHNG) + port_change |= USB_PORT_STAT_C_ENABLE; + if (hprt0 & DWC2_HPRT0_PRTCONNDET) + port_change |= USB_PORT_STAT_C_CONNECTION; + if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) + port_change |= USB_PORT_STAT_C_OVERCURRENT; + + *(uint32_t *)buffer = cpu_to_le32(port_status | + (port_change << 16)); + len = 4; + break; + default: + puts("unsupported root hub command\n"); + stat = USB_ST_STALLED; + } + + dev->act_len = min(len, txlen); + dev->status = stat; + + return stat; +} + +/* Direction: In ; Request: Descriptor */ +static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, + void *buffer, int txlen, + struct devrequest *cmd) +{ + unsigned char data[32]; + uint32_t dsc; + int len = 0; + int stat = 0; + uint16_t wValue = cpu_to_le16(cmd->value); + uint16_t wLength = cpu_to_le16(cmd->length); + + switch (cmd->requesttype & ~USB_DIR_IN) { + case 0: + switch (wValue & 0xff00) { + case 0x0100: /* device descriptor */ + len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); + memcpy(buffer, root_hub_dev_des, len); + break; + case 0x0200: /* configuration descriptor */ + len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); + memcpy(buffer, root_hub_config_des, len); + break; + case 0x0300: /* string descriptors */ + switch (wValue & 0xff) { + case 0x00: + len = min3(txlen, (int)sizeof(root_hub_str_index0), + (int)wLength); + memcpy(buffer, root_hub_str_index0, len); + break; + case 0x01: + len = min3(txlen, (int)sizeof(root_hub_str_index1), + (int)wLength); + memcpy(buffer, root_hub_str_index1, len); + break; + } + break; + default: + stat = USB_ST_STALLED; + } + break; + + case USB_TYPE_CLASS: + /* Root port config, set 1 port and nothing else. */ + dsc = 0x00000001; + + data[0] = 9; /* min length; */ + data[1] = 0x29; + data[2] = dsc & RH_A_NDP; + data[3] = 0; + if (dsc & RH_A_PSM) + data[3] |= 0x1; + if (dsc & RH_A_NOCP) + data[3] |= 0x10; + else if (dsc & RH_A_OCPM) + data[3] |= 0x8; + + /* corresponds to data[4-7] */ + data[5] = (dsc & RH_A_POTPGT) >> 24; + data[7] = dsc & RH_B_DR; + if (data[2] < 7) { + data[8] = 0xff; + } else { + data[0] += 2; + data[8] = (dsc & RH_B_DR) >> 8; + data[9] = 0xff; + data[10] = data[9]; + } + + len = min3(txlen, (int)data[0], (int)wLength); + memcpy(buffer, data, len); + break; + default: + puts("unsupported root hub command\n"); + stat = USB_ST_STALLED; + } + + dev->act_len = min(len, txlen); + dev->status = stat; + + return stat; +} + +/* Direction: In ; Request: Configuration */ +static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, + void *buffer, int txlen, + struct devrequest *cmd) +{ + int len = 0; + int stat = 0; + + switch (cmd->requesttype & ~USB_DIR_IN) { + case 0: + *(uint8_t *)buffer = 0x01; + len = 1; + break; + default: + puts("unsupported root hub command\n"); + stat = USB_ST_STALLED; + } + + dev->act_len = min(len, txlen); + dev->status = stat; + + return stat; +} + +/* Direction: In */ +static int dwc_otg_submit_rh_msg_in(struct usb_device *dev, + void *buffer, int txlen, + struct devrequest *cmd) +{ + switch (cmd->request) { + case USB_REQ_GET_STATUS: + return dwc_otg_submit_rh_msg_in_status(dev, buffer, + txlen, cmd); + case USB_REQ_GET_DESCRIPTOR: + return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, + txlen, cmd); + case USB_REQ_GET_CONFIGURATION: + return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, + txlen, cmd); + default: + puts("unsupported root hub command\n"); + return USB_ST_STALLED; + } +} + +/* Direction: Out */ +static int dwc_otg_submit_rh_msg_out(struct usb_device *dev, + void *buffer, int txlen, + struct devrequest *cmd) +{ + int len = 0; + int stat = 0; + uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); + uint16_t wValue = cpu_to_le16(cmd->value); + + switch (bmrtype_breq & ~USB_DIR_IN) { + case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: + case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: + break; + + case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: + switch (wValue) { + case USB_PORT_FEAT_C_CONNECTION: + setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); + break; + } + break; + + case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: + switch (wValue) { + case USB_PORT_FEAT_SUSPEND: + break; + + case USB_PORT_FEAT_RESET: + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | + DWC2_HPRT0_PRTCONNDET | + DWC2_HPRT0_PRTENCHNG | + DWC2_HPRT0_PRTOVRCURRCHNG, + DWC2_HPRT0_PRTRST); + mdelay(50); + clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); + break; + + case USB_PORT_FEAT_POWER: + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | + DWC2_HPRT0_PRTCONNDET | + DWC2_HPRT0_PRTENCHNG | + DWC2_HPRT0_PRTOVRCURRCHNG, + DWC2_HPRT0_PRTRST); + break; + + case USB_PORT_FEAT_ENABLE: + break; + } + break; + case (USB_REQ_SET_ADDRESS << 8): + root_hub_devnum = wValue; + break; + case (USB_REQ_SET_CONFIGURATION << 8): + break; + default: + puts("unsupported root hub command\n"); + stat = USB_ST_STALLED; + } + + len = min(len, txlen); + + dev->act_len = len; + dev->status = stat; + + return stat; +} + +static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int txlen, + struct devrequest *cmd) +{ + int stat = 0; + + if (usb_pipeint(pipe)) { + puts("Root-Hub submit IRQ: NOT implemented\n"); + return 0; + } + + if (cmd->requesttype & USB_DIR_IN) + stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd); + else + stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd); + + mdelay(1); + + return stat; +} + +/* U-Boot USB transmission interface */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len) +{ + int devnum = usb_pipedevice(pipe); + int ep = usb_pipeendpoint(pipe); + int max = usb_maxpacket(dev, pipe); + int done = 0; + uint32_t hctsiz, sub, tmp; + struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; + uint32_t hcint; + uint32_t xfer_len; + uint32_t num_packets; + int stop_transfer = 0; + unsigned int timeout = 1000000; + + if (devnum == root_hub_devnum) { + dev->status = 0; + return -EINVAL; + } + + if (len > DWC2_DATA_BUF_SIZE) { + printf("%s: %d is more then available buffer size (%d)\n", + __func__, len, DWC2_DATA_BUF_SIZE); + dev->status = 0; + dev->act_len = 0; + return -EINVAL; + } + + while ((done < len) && !stop_transfer) { + /* Initialize channel */ + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, + usb_pipein(pipe), DWC2_HCCHAR_EPTYPE_BULK, max); + + xfer_len = len - done; + /* Make sure that xfer_len is a multiple of max packet size. */ + if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) + xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1; + + if (xfer_len > 0) { + num_packets = (xfer_len + max - 1) / max; + if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) { + num_packets = CONFIG_DWC2_MAX_PACKET_COUNT; + xfer_len = num_packets * max; + } + } else { + num_packets = 1; + } + + if (usb_pipein(pipe)) + xfer_len = num_packets * max; + + writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | + (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | + (bulk_data_toggle[devnum][ep] << + DWC2_HCTSIZ_PID_OFFSET), + &hc_regs->hctsiz); + + memcpy(aligned_buffer, (char *)buffer + done, len - done); + writel((uint32_t)aligned_buffer, &hc_regs->hcdma); + + /* Set host channel enable after all other setup is complete. */ + clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS, + (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | + DWC2_HCCHAR_CHEN); + + while (1) { + hcint = readl(&hc_regs->hcint); + + if (!(hcint & DWC2_HCINT_CHHLTD)) + continue; + + if (hcint & DWC2_HCINT_XFERCOMP) { + hctsiz = readl(&hc_regs->hctsiz); + done += xfer_len; + + sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK; + sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET; + + if (usb_pipein(pipe)) { + done -= sub; + if (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) + stop_transfer = 1; + } + + tmp = hctsiz & DWC2_HCTSIZ_PID_MASK; + tmp >>= DWC2_HCTSIZ_PID_OFFSET; + if (tmp == DWC2_HC_PID_DATA1) { + bulk_data_toggle[devnum][ep] = + DWC2_HC_PID_DATA1; + } else { + bulk_data_toggle[devnum][ep] = + DWC2_HC_PID_DATA0; + } + break; + } + + if (hcint & DWC2_HCINT_STALL) { + puts("DWC OTG: Channel halted\n"); + bulk_data_toggle[devnum][ep] = + DWC2_HC_PID_DATA0; + + stop_transfer = 1; + break; + } + + if (!--timeout) { + printf("%s: Timeout!\n", __func__); + break; + } + } + } + + if (done && usb_pipein(pipe)) + memcpy(buffer, aligned_buffer, done); + + writel(0, &hc_regs->hcintmsk); + writel(0xFFFFFFFF, &hc_regs->hcint); + + dev->status = 0; + dev->act_len = done; + + return 0; +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, struct devrequest *setup) +{ + struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; + int done = 0; + int devnum = usb_pipedevice(pipe); + int ep = usb_pipeendpoint(pipe); + int max = usb_maxpacket(dev, pipe); + uint32_t hctsiz = 0, sub, tmp, ret; + uint32_t hcint; + const uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | + DWC2_HCINT_CHHLTD | DWC2_HCINT_ACK; + unsigned int timeout = 1000000; + + /* For CONTROL endpoint pid should start with DATA1 */ + int status_direction; + + if (devnum == root_hub_devnum) { + dev->status = 0; + dev->speed = USB_SPEED_HIGH; + return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup); + } + + if (len > DWC2_DATA_BUF_SIZE) { + printf("%s: %d is more then available buffer size(%d)\n", + __func__, len, DWC2_DATA_BUF_SIZE); + dev->status = 0; + dev->act_len = 0; + return -EINVAL; + } + + /* Initialize channel, OUT for setup buffer */ + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, 0, + DWC2_HCCHAR_EPTYPE_CONTROL, max); + + /* SETUP stage */ + writel((8 << DWC2_HCTSIZ_XFERSIZE_OFFSET) | + (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) | + (DWC2_HC_PID_SETUP << DWC2_HCTSIZ_PID_OFFSET), + &hc_regs->hctsiz); + + writel((uint32_t)setup, &hc_regs->hcdma); + + /* Set host channel enable after all other setup is complete. */ + clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS, + (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN); + + ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, 1); + if (ret) + printf("%s: Timeout!\n", __func__); + + hcint = readl(&hc_regs->hcint); + + if (!(hcint & DWC2_HCINT_CHHLTD) || !(hcint & DWC2_HCINT_XFERCOMP)) { + printf("%s: Error (HCINT=%08x)\n", __func__, hcint); + dev->status = 0; + dev->act_len = 0; + return -EINVAL; + } + + /* Clear interrupts */ + writel(0, &hc_regs->hcintmsk); + writel(0xFFFFFFFF, &hc_regs->hcint); + + if (buffer) { + /* DATA stage */ + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, + usb_pipein(pipe), + DWC2_HCCHAR_EPTYPE_CONTROL, max); + + /* TODO: check if len < 64 */ + control_data_toggle[devnum][ep] = DWC2_HC_PID_DATA1; + writel((len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | + (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) | + (control_data_toggle[devnum][ep] << + DWC2_HCTSIZ_PID_OFFSET), + &hc_regs->hctsiz); + + writel((uint32_t)buffer, &hc_regs->hcdma); + + /* Set host channel enable after all other setup is complete */ + clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS, + (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | + DWC2_HCCHAR_CHEN); + + while (1) { + hcint = readl(&hc_regs->hcint); + if (!(hcint & DWC2_HCINT_CHHLTD)) + continue; + + if (hcint & DWC2_HCINT_XFERCOMP) { + hctsiz = readl(&hc_regs->hctsiz); + done = len; + + sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK; + sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET; + + if (usb_pipein(pipe)) + done -= sub; + } + + if (hcint & DWC2_HCINT_ACK) { + tmp = hctsiz & DWC2_HCTSIZ_PID_MASK; + tmp >>= DWC2_HCTSIZ_PID_OFFSET; + if (tmp == DWC2_HC_PID_DATA0) { + control_data_toggle[devnum][ep] = + DWC2_HC_PID_DATA0; + } else { + control_data_toggle[devnum][ep] = + DWC2_HC_PID_DATA1; + } + } + + if (hcint != hcint_comp_hlt_ack) { + printf("%s: Error (HCINT=%08x)\n", + __func__, hcint); + goto out; + } + + if (!--timeout) { + printf("%s: Timeout!\n", __func__); + goto out; + } + + break; + } + } /* End of DATA stage */ + + /* STATUS stage */ + if ((len == 0) || usb_pipeout(pipe)) + status_direction = 1; + else + status_direction = 0; + + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, + status_direction, DWC2_HCCHAR_EPTYPE_CONTROL, max); + + writel((1 << DWC2_HCTSIZ_PKTCNT_OFFSET) | + (DWC2_HC_PID_DATA1 << DWC2_HCTSIZ_PID_OFFSET), + &hc_regs->hctsiz); + + writel((uint32_t)status_buffer, &hc_regs->hcdma); + + /* Set host channel enable after all other setup is complete. */ + clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS, + (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN); + + while (1) { + hcint = readl(&hc_regs->hcint); + if (hcint & DWC2_HCINT_CHHLTD) + break; + } + + if (hcint != hcint_comp_hlt_ack) + printf("%s: Error (HCINT=%08x)\n", __func__, hcint); + +out: + dev->act_len = done; + dev->status = 0; + + return done; +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, int interval) +{ + printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n", + dev, pipe, buffer, len, interval); + return -ENOSYS; +} + +/* U-Boot USB control interface */ +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) +{ + uint32_t snpsid; + int i, j; + + root_hub_devnum = 0; + + snpsid = readl(®s->gsnpsid); + printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff); + + if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) { + printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); + return -ENODEV; + } + + dwc_otg_core_init(regs); + dwc_otg_core_host_init(regs); + + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | + DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | + DWC2_HPRT0_PRTOVRCURRCHNG, + DWC2_HPRT0_PRTRST); + mdelay(50); + clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | + DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | + DWC2_HPRT0_PRTRST); + + for (i = 0; i < MAX_DEVICE; i++) { + for (j = 0; j < MAX_ENDPOINT; j++) { + control_data_toggle[i][j] = DWC2_HC_PID_DATA1; + bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0; + } + } + + return 0; +} + +int usb_lowlevel_stop(int index) +{ + /* Put everything in reset. */ + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | + DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | + DWC2_HPRT0_PRTOVRCURRCHNG, + DWC2_HPRT0_PRTRST); + return 0; +} diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h new file mode 100644 index 0000000000..ba08fd554f --- /dev/null +++ b/drivers/usb/host/dwc2.h @@ -0,0 +1,782 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DWC2_H__ +#define __DWC2_H__ + +struct dwc2_hc_regs { + u32 hcchar; /* 0x00 */ + u32 hcsplt; + u32 hcint; + u32 hcintmsk; + u32 hctsiz; /* 0x10 */ + u32 hcdma; + u32 reserved; + u32 hcdmab; +}; + +struct dwc2_host_regs { + u32 hcfg; /* 0x00 */ + u32 hfir; + u32 hfnum; + u32 _pad_0x40c; + u32 hptxsts; /* 0x10 */ + u32 haint; + u32 haintmsk; + u32 hflbaddr; +}; + +struct dwc2_core_regs { + u32 gotgctl; /* 0x000 */ + u32 gotgint; + u32 gahbcfg; + u32 gusbcfg; + u32 grstctl; /* 0x010 */ + u32 gintsts; + u32 gintmsk; + u32 grxstsr; + u32 grxstsp; /* 0x020 */ + u32 grxfsiz; + u32 gnptxfsiz; + u32 gnptxsts; + u32 gi2cctl; /* 0x030 */ + u32 gpvndctl; + u32 ggpio; + u32 guid; + u32 gsnpsid; /* 0x040 */ + u32 ghwcfg1; + u32 ghwcfg2; + u32 ghwcfg3; + u32 ghwcfg4; /* 0x050 */ + u32 glpmcfg; + u32 _pad_0x58_0x9c[42]; + u32 hptxfsiz; /* 0x100 */ + u32 dptxfsiz_dieptxf[15]; + u32 _pad_0x140_0x3fc[176]; + struct dwc2_host_regs host_regs; /* 0x400 */ + u32 _pad_0x420_0x43c[8]; + u32 hprt0; /* 0x440 */ + u32 _pad_0x444_0x4fc[47]; + struct dwc2_hc_regs hc_regs[16]; /* 0x500 */ + u32 _pad_0x700_0xe00[448]; + u32 pcgcctl; /* 0xe00 */ +}; + +#define DWC2_GOTGCTL_SESREQSCS (1 << 0) +#define DWC2_GOTGCTL_SESREQSCS_OFFSET 0 +#define DWC2_GOTGCTL_SESREQ (1 << 1) +#define DWC2_GOTGCTL_SESREQ_OFFSET 1 +#define DWC2_GOTGCTL_HSTNEGSCS (1 << 8) +#define DWC2_GOTGCTL_HSTNEGSCS_OFFSET 8 +#define DWC2_GOTGCTL_HNPREQ (1 << 9) +#define DWC2_GOTGCTL_HNPREQ_OFFSET 9 +#define DWC2_GOTGCTL_HSTSETHNPEN (1 << 10) +#define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET 10 +#define DWC2_GOTGCTL_DEVHNPEN (1 << 11) +#define DWC2_GOTGCTL_DEVHNPEN_OFFSET 11 +#define DWC2_GOTGCTL_CONIDSTS (1 << 16) +#define DWC2_GOTGCTL_CONIDSTS_OFFSET 16 +#define DWC2_GOTGCTL_DBNCTIME (1 << 17) +#define DWC2_GOTGCTL_DBNCTIME_OFFSET 17 +#define DWC2_GOTGCTL_ASESVLD (1 << 18) +#define DWC2_GOTGCTL_ASESVLD_OFFSET 18 +#define DWC2_GOTGCTL_BSESVLD (1 << 19) +#define DWC2_GOTGCTL_BSESVLD_OFFSET 19 +#define DWC2_GOTGCTL_OTGVER (1 << 20) +#define DWC2_GOTGCTL_OTGVER_OFFSET 20 +#define DWC2_GOTGINT_SESENDDET (1 << 2) +#define DWC2_GOTGINT_SESENDDET_OFFSET 2 +#define DWC2_GOTGINT_SESREQSUCSTSCHNG (1 << 8) +#define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET 8 +#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG (1 << 9) +#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 9 +#define DWC2_GOTGINT_RESERVER10_16_MASK (0x7F << 10) +#define DWC2_GOTGINT_RESERVER10_16_OFFSET 10 +#define DWC2_GOTGINT_HSTNEGDET (1 << 17) +#define DWC2_GOTGINT_HSTNEGDET_OFFSET 17 +#define DWC2_GOTGINT_ADEVTOUTCHNG (1 << 18) +#define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET 18 +#define DWC2_GOTGINT_DEBDONE (1 << 19) +#define DWC2_GOTGINT_DEBDONE_OFFSET 19 +#define DWC2_GAHBCFG_GLBLINTRMSK (1 << 0) +#define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET 0 +#define DWC2_GAHBCFG_HBURSTLEN_SINGLE (0 << 1) +#define DWC2_GAHBCFG_HBURSTLEN_INCR (1 << 1) +#define DWC2_GAHBCFG_HBURSTLEN_INCR4 (3 << 1) +#define DWC2_GAHBCFG_HBURSTLEN_INCR8 (5 << 1) +#define DWC2_GAHBCFG_HBURSTLEN_INCR16 (7 << 1) +#define DWC2_GAHBCFG_HBURSTLEN_MASK (0xF << 1) +#define DWC2_GAHBCFG_HBURSTLEN_OFFSET 1 +#define DWC2_GAHBCFG_DMAENABLE (1 << 5) +#define DWC2_GAHBCFG_DMAENABLE_OFFSET 5 +#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL (1 << 7) +#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET 7 +#define DWC2_GAHBCFG_PTXFEMPLVL (1 << 8) +#define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET 8 +#define DWC2_GUSBCFG_TOUTCAL_MASK (0x7 << 0) +#define DWC2_GUSBCFG_TOUTCAL_OFFSET 0 +#define DWC2_GUSBCFG_PHYIF (1 << 3) +#define DWC2_GUSBCFG_PHYIF_OFFSET 3 +#define DWC2_GUSBCFG_ULPI_UTMI_SEL (1 << 4) +#define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET 4 +#define DWC2_GUSBCFG_FSINTF (1 << 5) +#define DWC2_GUSBCFG_FSINTF_OFFSET 5 +#define DWC2_GUSBCFG_PHYSEL (1 << 6) +#define DWC2_GUSBCFG_PHYSEL_OFFSET 6 +#define DWC2_GUSBCFG_DDRSEL (1 << 7) +#define DWC2_GUSBCFG_DDRSEL_OFFSET 7 +#define DWC2_GUSBCFG_SRPCAP (1 << 8) +#define DWC2_GUSBCFG_SRPCAP_OFFSET 8 +#define DWC2_GUSBCFG_HNPCAP (1 << 9) +#define DWC2_GUSBCFG_HNPCAP_OFFSET 9 +#define DWC2_GUSBCFG_USBTRDTIM_MASK (0xF << 10) +#define DWC2_GUSBCFG_USBTRDTIM_OFFSET 10 +#define DWC2_GUSBCFG_NPTXFRWNDEN (1 << 14) +#define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET 14 +#define DWC2_GUSBCFG_PHYLPWRCLKSEL (1 << 15) +#define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET 15 +#define DWC2_GUSBCFG_OTGUTMIFSSEL (1 << 16) +#define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET 16 +#define DWC2_GUSBCFG_ULPI_FSLS (1 << 17) +#define DWC2_GUSBCFG_ULPI_FSLS_OFFSET 17 +#define DWC2_GUSBCFG_ULPI_AUTO_RES (1 << 18) +#define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET 18 +#define DWC2_GUSBCFG_ULPI_CLK_SUS_M (1 << 19) +#define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET 19 +#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20) +#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET 20 +#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR (1 << 21) +#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET 21 +#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE (1 << 22) +#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET 22 +#define DWC2_GUSBCFG_IC_USB_CAP (1 << 26) +#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET 26 +#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE (1 << 27) +#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET 27 +#define DWC2_GUSBCFG_TX_END_DELAY (1 << 28) +#define DWC2_GUSBCFG_TX_END_DELAY_OFFSET 28 +#define DWC2_GUSBCFG_FORCEHOSTMODE (1 << 29) +#define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET 29 +#define DWC2_GUSBCFG_FORCEDEVMODE (1 << 30) +#define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET 30 +#define DWC2_GLPMCTL_LPM_CAP_EN (1 << 0) +#define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET 0 +#define DWC2_GLPMCTL_APPL_RESP (1 << 1) +#define DWC2_GLPMCTL_APPL_RESP_OFFSET 1 +#define DWC2_GLPMCTL_HIRD_MASK (0xF << 2) +#define DWC2_GLPMCTL_HIRD_OFFSET 2 +#define DWC2_GLPMCTL_REM_WKUP_EN (1 << 6) +#define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET 6 +#define DWC2_GLPMCTL_EN_UTMI_SLEEP (1 << 7) +#define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET 7 +#define DWC2_GLPMCTL_HIRD_THRES_MASK (0x1F << 8) +#define DWC2_GLPMCTL_HIRD_THRES_OFFSET 8 +#define DWC2_GLPMCTL_LPM_RESP_MASK (0x3 << 13) +#define DWC2_GLPMCTL_LPM_RESP_OFFSET 13 +#define DWC2_GLPMCTL_PRT_SLEEP_STS (1 << 15) +#define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET 15 +#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK (1 << 16) +#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET 16 +#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK (0xF << 17) +#define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET 17 +#define DWC2_GLPMCTL_RETRY_COUNT_MASK (0x7 << 21) +#define DWC2_GLPMCTL_RETRY_COUNT_OFFSET 21 +#define DWC2_GLPMCTL_SEND_LPM (1 << 24) +#define DWC2_GLPMCTL_SEND_LPM_OFFSET 24 +#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK (0x7 << 25) +#define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET 25 +#define DWC2_GLPMCTL_HSIC_CONNECT (1 << 30) +#define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET 30 +#define DWC2_GLPMCTL_INV_SEL_HSIC (1 << 31) +#define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET 31 +#define DWC2_GRSTCTL_CSFTRST (1 << 0) +#define DWC2_GRSTCTL_CSFTRST_OFFSET 0 +#define DWC2_GRSTCTL_HSFTRST (1 << 1) +#define DWC2_GRSTCTL_HSFTRST_OFFSET 1 +#define DWC2_GRSTCTL_HSTFRM (1 << 2) +#define DWC2_GRSTCTL_HSTFRM_OFFSET 2 +#define DWC2_GRSTCTL_INTKNQFLSH (1 << 3) +#define DWC2_GRSTCTL_INTKNQFLSH_OFFSET 3 +#define DWC2_GRSTCTL_RXFFLSH (1 << 4) +#define DWC2_GRSTCTL_RXFFLSH_OFFSET 4 +#define DWC2_GRSTCTL_TXFFLSH (1 << 5) +#define DWC2_GRSTCTL_TXFFLSH_OFFSET 5 +#define DWC2_GRSTCTL_TXFNUM_MASK (0x1F << 6) +#define DWC2_GRSTCTL_TXFNUM_OFFSET 6 +#define DWC2_GRSTCTL_DMAREQ (1 << 30) +#define DWC2_GRSTCTL_DMAREQ_OFFSET 30 +#define DWC2_GRSTCTL_AHBIDLE (1 << 31) +#define DWC2_GRSTCTL_AHBIDLE_OFFSET 31 +#define DWC2_GINTMSK_MODEMISMATCH (1 << 1) +#define DWC2_GINTMSK_MODEMISMATCH_OFFSET 1 +#define DWC2_GINTMSK_OTGINTR (1 << 2) +#define DWC2_GINTMSK_OTGINTR_OFFSET 2 +#define DWC2_GINTMSK_SOFINTR (1 << 3) +#define DWC2_GINTMSK_SOFINTR_OFFSET 3 +#define DWC2_GINTMSK_RXSTSQLVL (1 << 4) +#define DWC2_GINTMSK_RXSTSQLVL_OFFSET 4 +#define DWC2_GINTMSK_NPTXFEMPTY (1 << 5) +#define DWC2_GINTMSK_NPTXFEMPTY_OFFSET 5 +#define DWC2_GINTMSK_GINNAKEFF (1 << 6) +#define DWC2_GINTMSK_GINNAKEFF_OFFSET 6 +#define DWC2_GINTMSK_GOUTNAKEFF (1 << 7) +#define DWC2_GINTMSK_GOUTNAKEFF_OFFSET 7 +#define DWC2_GINTMSK_I2CINTR (1 << 9) +#define DWC2_GINTMSK_I2CINTR_OFFSET 9 +#define DWC2_GINTMSK_ERLYSUSPEND (1 << 10) +#define DWC2_GINTMSK_ERLYSUSPEND_OFFSET 10 +#define DWC2_GINTMSK_USBSUSPEND (1 << 11) +#define DWC2_GINTMSK_USBSUSPEND_OFFSET 11 +#define DWC2_GINTMSK_USBRESET (1 << 12) +#define DWC2_GINTMSK_USBRESET_OFFSET 12 +#define DWC2_GINTMSK_ENUMDONE (1 << 13) +#define DWC2_GINTMSK_ENUMDONE_OFFSET 13 +#define DWC2_GINTMSK_ISOOUTDROP (1 << 14) +#define DWC2_GINTMSK_ISOOUTDROP_OFFSET 14 +#define DWC2_GINTMSK_EOPFRAME (1 << 15) +#define DWC2_GINTMSK_EOPFRAME_OFFSET 15 +#define DWC2_GINTMSK_EPMISMATCH (1 << 17) +#define DWC2_GINTMSK_EPMISMATCH_OFFSET 17 +#define DWC2_GINTMSK_INEPINTR (1 << 18) +#define DWC2_GINTMSK_INEPINTR_OFFSET 18 +#define DWC2_GINTMSK_OUTEPINTR (1 << 19) +#define DWC2_GINTMSK_OUTEPINTR_OFFSET 19 +#define DWC2_GINTMSK_INCOMPLISOIN (1 << 20) +#define DWC2_GINTMSK_INCOMPLISOIN_OFFSET 20 +#define DWC2_GINTMSK_INCOMPLISOOUT (1 << 21) +#define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET 21 +#define DWC2_GINTMSK_PORTINTR (1 << 24) +#define DWC2_GINTMSK_PORTINTR_OFFSET 24 +#define DWC2_GINTMSK_HCINTR (1 << 25) +#define DWC2_GINTMSK_HCINTR_OFFSET 25 +#define DWC2_GINTMSK_PTXFEMPTY (1 << 26) +#define DWC2_GINTMSK_PTXFEMPTY_OFFSET 26 +#define DWC2_GINTMSK_LPMTRANRCVD (1 << 27) +#define DWC2_GINTMSK_LPMTRANRCVD_OFFSET 27 +#define DWC2_GINTMSK_CONIDSTSCHNG (1 << 28) +#define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET 28 +#define DWC2_GINTMSK_DISCONNECT (1 << 29) +#define DWC2_GINTMSK_DISCONNECT_OFFSET 29 +#define DWC2_GINTMSK_SESSREQINTR (1 << 30) +#define DWC2_GINTMSK_SESSREQINTR_OFFSET 30 +#define DWC2_GINTMSK_WKUPINTR (1 << 31) +#define DWC2_GINTMSK_WKUPINTR_OFFSET 31 +#define DWC2_GINTSTS_CURMODE_DEVICE (0 << 0) +#define DWC2_GINTSTS_CURMODE_HOST (1 << 0) +#define DWC2_GINTSTS_CURMODE (1 << 0) +#define DWC2_GINTSTS_CURMODE_OFFSET 0 +#define DWC2_GINTSTS_MODEMISMATCH (1 << 1) +#define DWC2_GINTSTS_MODEMISMATCH_OFFSET 1 +#define DWC2_GINTSTS_OTGINTR (1 << 2) +#define DWC2_GINTSTS_OTGINTR_OFFSET 2 +#define DWC2_GINTSTS_SOFINTR (1 << 3) +#define DWC2_GINTSTS_SOFINTR_OFFSET 3 +#define DWC2_GINTSTS_RXSTSQLVL (1 << 4) +#define DWC2_GINTSTS_RXSTSQLVL_OFFSET 4 +#define DWC2_GINTSTS_NPTXFEMPTY (1 << 5) +#define DWC2_GINTSTS_NPTXFEMPTY_OFFSET 5 +#define DWC2_GINTSTS_GINNAKEFF (1 << 6) +#define DWC2_GINTSTS_GINNAKEFF_OFFSET 6 +#define DWC2_GINTSTS_GOUTNAKEFF (1 << 7) +#define DWC2_GINTSTS_GOUTNAKEFF_OFFSET 7 +#define DWC2_GINTSTS_I2CINTR (1 << 9) +#define DWC2_GINTSTS_I2CINTR_OFFSET 9 +#define DWC2_GINTSTS_ERLYSUSPEND (1 << 10) +#define DWC2_GINTSTS_ERLYSUSPEND_OFFSET 10 +#define DWC2_GINTSTS_USBSUSPEND (1 << 11) +#define DWC2_GINTSTS_USBSUSPEND_OFFSET 11 +#define DWC2_GINTSTS_USBRESET (1 << 12) +#define DWC2_GINTSTS_USBRESET_OFFSET 12 +#define DWC2_GINTSTS_ENUMDONE (1 << 13) +#define DWC2_GINTSTS_ENUMDONE_OFFSET 13 +#define DWC2_GINTSTS_ISOOUTDROP (1 << 14) +#define DWC2_GINTSTS_ISOOUTDROP_OFFSET 14 +#define DWC2_GINTSTS_EOPFRAME (1 << 15) +#define DWC2_GINTSTS_EOPFRAME_OFFSET 15 +#define DWC2_GINTSTS_INTOKENRX (1 << 16) +#define DWC2_GINTSTS_INTOKENRX_OFFSET 16 +#define DWC2_GINTSTS_EPMISMATCH (1 << 17) +#define DWC2_GINTSTS_EPMISMATCH_OFFSET 17 +#define DWC2_GINTSTS_INEPINT (1 << 18) +#define DWC2_GINTSTS_INEPINT_OFFSET 18 +#define DWC2_GINTSTS_OUTEPINTR (1 << 19) +#define DWC2_GINTSTS_OUTEPINTR_OFFSET 19 +#define DWC2_GINTSTS_INCOMPLISOIN (1 << 20) +#define DWC2_GINTSTS_INCOMPLISOIN_OFFSET 20 +#define DWC2_GINTSTS_INCOMPLISOOUT (1 << 21) +#define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET 21 +#define DWC2_GINTSTS_PORTINTR (1 << 24) +#define DWC2_GINTSTS_PORTINTR_OFFSET 24 +#define DWC2_GINTSTS_HCINTR (1 << 25) +#define DWC2_GINTSTS_HCINTR_OFFSET 25 +#define DWC2_GINTSTS_PTXFEMPTY (1 << 26) +#define DWC2_GINTSTS_PTXFEMPTY_OFFSET 26 +#define DWC2_GINTSTS_LPMTRANRCVD (1 << 27) +#define DWC2_GINTSTS_LPMTRANRCVD_OFFSET 27 +#define DWC2_GINTSTS_CONIDSTSCHNG (1 << 28) +#define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET 28 +#define DWC2_GINTSTS_DISCONNECT (1 << 29) +#define DWC2_GINTSTS_DISCONNECT_OFFSET 29 +#define DWC2_GINTSTS_SESSREQINTR (1 << 30) +#define DWC2_GINTSTS_SESSREQINTR_OFFSET 30 +#define DWC2_GINTSTS_WKUPINTR (1 << 31) +#define DWC2_GINTSTS_WKUPINTR_OFFSET 31 +#define DWC2_GRXSTS_EPNUM_MASK (0xF << 0) +#define DWC2_GRXSTS_EPNUM_OFFSET 0 +#define DWC2_GRXSTS_BCNT_MASK (0x7FF << 4) +#define DWC2_GRXSTS_BCNT_OFFSET 4 +#define DWC2_GRXSTS_DPID_MASK (0x3 << 15) +#define DWC2_GRXSTS_DPID_OFFSET 15 +#define DWC2_GRXSTS_PKTSTS_MASK (0xF << 17) +#define DWC2_GRXSTS_PKTSTS_OFFSET 17 +#define DWC2_GRXSTS_FN_MASK (0xF << 21) +#define DWC2_GRXSTS_FN_OFFSET 21 +#define DWC2_FIFOSIZE_STARTADDR_MASK (0xFFFF << 0) +#define DWC2_FIFOSIZE_STARTADDR_OFFSET 0 +#define DWC2_FIFOSIZE_DEPTH_MASK (0xFFFF << 16) +#define DWC2_FIFOSIZE_DEPTH_OFFSET 16 +#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK (0xFFFF << 0) +#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET 0 +#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK (0xFF << 16) +#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET 16 +#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE (1 << 24) +#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET 24 +#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK (0x3 << 25) +#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET 25 +#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK (0xF << 27) +#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET 27 +#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK (0xFFFF << 0) +#define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET 0 +#define DWC2_GI2CCTL_RWDATA_MASK (0xFF << 0) +#define DWC2_GI2CCTL_RWDATA_OFFSET 0 +#define DWC2_GI2CCTL_REGADDR_MASK (0xFF << 8) +#define DWC2_GI2CCTL_REGADDR_OFFSET 8 +#define DWC2_GI2CCTL_ADDR_MASK (0x7F << 16) +#define DWC2_GI2CCTL_ADDR_OFFSET 16 +#define DWC2_GI2CCTL_I2CEN (1 << 23) +#define DWC2_GI2CCTL_I2CEN_OFFSET 23 +#define DWC2_GI2CCTL_ACK (1 << 24) +#define DWC2_GI2CCTL_ACK_OFFSET 24 +#define DWC2_GI2CCTL_I2CSUSPCTL (1 << 25) +#define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET 25 +#define DWC2_GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) +#define DWC2_GI2CCTL_I2CDEVADDR_OFFSET 26 +#define DWC2_GI2CCTL_RW (1 << 30) +#define DWC2_GI2CCTL_RW_OFFSET 30 +#define DWC2_GI2CCTL_BSYDNE (1 << 31) +#define DWC2_GI2CCTL_BSYDNE_OFFSET 31 +#define DWC2_HWCFG1_EP_DIR0_MASK (0x3 << 0) +#define DWC2_HWCFG1_EP_DIR0_OFFSET 0 +#define DWC2_HWCFG1_EP_DIR1_MASK (0x3 << 2) +#define DWC2_HWCFG1_EP_DIR1_OFFSET 2 +#define DWC2_HWCFG1_EP_DIR2_MASK (0x3 << 4) +#define DWC2_HWCFG1_EP_DIR2_OFFSET 4 +#define DWC2_HWCFG1_EP_DIR3_MASK (0x3 << 6) +#define DWC2_HWCFG1_EP_DIR3_OFFSET 6 +#define DWC2_HWCFG1_EP_DIR4_MASK (0x3 << 8) +#define DWC2_HWCFG1_EP_DIR4_OFFSET 8 +#define DWC2_HWCFG1_EP_DIR5_MASK (0x3 << 10) +#define DWC2_HWCFG1_EP_DIR5_OFFSET 10 +#define DWC2_HWCFG1_EP_DIR6_MASK (0x3 << 12) +#define DWC2_HWCFG1_EP_DIR6_OFFSET 12 +#define DWC2_HWCFG1_EP_DIR7_MASK (0x3 << 14) +#define DWC2_HWCFG1_EP_DIR7_OFFSET 14 +#define DWC2_HWCFG1_EP_DIR8_MASK (0x3 << 16) +#define DWC2_HWCFG1_EP_DIR8_OFFSET 16 +#define DWC2_HWCFG1_EP_DIR9_MASK (0x3 << 18) +#define DWC2_HWCFG1_EP_DIR9_OFFSET 18 +#define DWC2_HWCFG1_EP_DIR10_MASK (0x3 << 20) +#define DWC2_HWCFG1_EP_DIR10_OFFSET 20 +#define DWC2_HWCFG1_EP_DIR11_MASK (0x3 << 22) +#define DWC2_HWCFG1_EP_DIR11_OFFSET 22 +#define DWC2_HWCFG1_EP_DIR12_MASK (0x3 << 24) +#define DWC2_HWCFG1_EP_DIR12_OFFSET 24 +#define DWC2_HWCFG1_EP_DIR13_MASK (0x3 << 26) +#define DWC2_HWCFG1_EP_DIR13_OFFSET 26 +#define DWC2_HWCFG1_EP_DIR14_MASK (0x3 << 28) +#define DWC2_HWCFG1_EP_DIR14_OFFSET 28 +#define DWC2_HWCFG1_EP_DIR15_MASK (0x3 << 30) +#define DWC2_HWCFG1_EP_DIR15_OFFSET 30 +#define DWC2_HWCFG2_OP_MODE_MASK (0x7 << 0) +#define DWC2_HWCFG2_OP_MODE_OFFSET 0 +#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY (0x0 << 3) +#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA (0x1 << 3) +#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA (0x2 << 3) +#define DWC2_HWCFG2_ARCHITECTURE_MASK (0x3 << 3) +#define DWC2_HWCFG2_ARCHITECTURE_OFFSET 3 +#define DWC2_HWCFG2_POINT2POINT (1 << 5) +#define DWC2_HWCFG2_POINT2POINT_OFFSET 5 +#define DWC2_HWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) +#define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET 6 +#define DWC2_HWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) +#define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET 8 +#define DWC2_HWCFG2_NUM_DEV_EP_MASK (0xF << 10) +#define DWC2_HWCFG2_NUM_DEV_EP_OFFSET 10 +#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK (0xF << 14) +#define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET 14 +#define DWC2_HWCFG2_PERIO_EP_SUPPORTED (1 << 18) +#define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET 18 +#define DWC2_HWCFG2_DYNAMIC_FIFO (1 << 19) +#define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET 19 +#define DWC2_HWCFG2_MULTI_PROC_INT (1 << 20) +#define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET 20 +#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) +#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET 22 +#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) +#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET 24 +#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1F << 26) +#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET 26 +#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xF << 0) +#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET 0 +#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) +#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET 4 +#define DWC2_HWCFG3_OTG_FUNC (1 << 7) +#define DWC2_HWCFG3_OTG_FUNC_OFFSET 7 +#define DWC2_HWCFG3_I2C (1 << 8) +#define DWC2_HWCFG3_I2C_OFFSET 8 +#define DWC2_HWCFG3_VENDOR_CTRL_IF (1 << 9) +#define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET 9 +#define DWC2_HWCFG3_OPTIONAL_FEATURES (1 << 10) +#define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET 10 +#define DWC2_HWCFG3_SYNCH_RESET_TYPE (1 << 11) +#define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET 11 +#define DWC2_HWCFG3_OTG_ENABLE_IC_USB (1 << 12) +#define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET 12 +#define DWC2_HWCFG3_OTG_ENABLE_HSIC (1 << 13) +#define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET 13 +#define DWC2_HWCFG3_OTG_LPM_EN (1 << 15) +#define DWC2_HWCFG3_OTG_LPM_EN_OFFSET 15 +#define DWC2_HWCFG3_DFIFO_DEPTH_MASK (0xFFFF << 16) +#define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET 16 +#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xF << 0) +#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET 0 +#define DWC2_HWCFG4_POWER_OPTIMIZ (1 << 4) +#define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET 4 +#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK (0x1FF << 5) +#define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET 5 +#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) +#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET 14 +#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xF << 16) +#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET 16 +#define DWC2_HWCFG4_IDDIG_FILT_EN (1 << 20) +#define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET 20 +#define DWC2_HWCFG4_VBUS_VALID_FILT_EN (1 << 21) +#define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET 21 +#define DWC2_HWCFG4_A_VALID_FILT_EN (1 << 22) +#define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET 22 +#define DWC2_HWCFG4_B_VALID_FILT_EN (1 << 23) +#define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET 23 +#define DWC2_HWCFG4_SESSION_END_FILT_EN (1 << 24) +#define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET 24 +#define DWC2_HWCFG4_DED_FIFO_EN (1 << 25) +#define DWC2_HWCFG4_DED_FIFO_EN_OFFSET 25 +#define DWC2_HWCFG4_NUM_IN_EPS_MASK (0xF << 26) +#define DWC2_HWCFG4_NUM_IN_EPS_OFFSET 26 +#define DWC2_HWCFG4_DESC_DMA (1 << 30) +#define DWC2_HWCFG4_DESC_DMA_OFFSET 30 +#define DWC2_HWCFG4_DESC_DMA_DYN (1 << 31) +#define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET 31 +#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ 0 +#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ 1 +#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ 2 +#define DWC2_HCFG_FSLSPCLKSEL_MASK (0x3 << 0) +#define DWC2_HCFG_FSLSPCLKSEL_OFFSET 0 +#define DWC2_HCFG_FSLSSUPP (1 << 2) +#define DWC2_HCFG_FSLSSUPP_OFFSET 2 +#define DWC2_HCFG_DESCDMA (1 << 23) +#define DWC2_HCFG_DESCDMA_OFFSET 23 +#define DWC2_HCFG_FRLISTEN_MASK (0x3 << 24) +#define DWC2_HCFG_FRLISTEN_OFFSET 24 +#define DWC2_HCFG_PERSCHEDENA (1 << 26) +#define DWC2_HCFG_PERSCHEDENA_OFFSET 26 +#define DWC2_HCFG_PERSCHEDSTAT (1 << 27) +#define DWC2_HCFG_PERSCHEDSTAT_OFFSET 27 +#define DWC2_HFIR_FRINT_MASK (0xFFFF << 0) +#define DWC2_HFIR_FRINT_OFFSET 0 +#define DWC2_HFNUM_FRNUM_MASK (0xFFFF << 0) +#define DWC2_HFNUM_FRNUM_OFFSET 0 +#define DWC2_HFNUM_FRREM_MASK (0xFFFF << 16) +#define DWC2_HFNUM_FRREM_OFFSET 16 +#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF << 0) +#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0 +#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16) +#define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET 16 +#define DWC2_HPTXSTS_PTXQTOP_TERMINATE (1 << 24) +#define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET 24 +#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK (0x3 << 25) +#define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET 25 +#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK (0xF << 27) +#define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET 27 +#define DWC2_HPTXSTS_PTXQTOP_ODD (1 << 31) +#define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET 31 +#define DWC2_HPRT0_PRTCONNSTS (1 << 0) +#define DWC2_HPRT0_PRTCONNSTS_OFFSET 0 +#define DWC2_HPRT0_PRTCONNDET (1 << 1) +#define DWC2_HPRT0_PRTCONNDET_OFFSET 1 +#define DWC2_HPRT0_PRTENA (1 << 2) +#define DWC2_HPRT0_PRTENA_OFFSET 2 +#define DWC2_HPRT0_PRTENCHNG (1 << 3) +#define DWC2_HPRT0_PRTENCHNG_OFFSET 3 +#define DWC2_HPRT0_PRTOVRCURRACT (1 << 4) +#define DWC2_HPRT0_PRTOVRCURRACT_OFFSET 4 +#define DWC2_HPRT0_PRTOVRCURRCHNG (1 << 5) +#define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET 5 +#define DWC2_HPRT0_PRTRES (1 << 6) +#define DWC2_HPRT0_PRTRES_OFFSET 6 +#define DWC2_HPRT0_PRTSUSP (1 << 7) +#define DWC2_HPRT0_PRTSUSP_OFFSET 7 +#define DWC2_HPRT0_PRTRST (1 << 8) +#define DWC2_HPRT0_PRTRST_OFFSET 8 +#define DWC2_HPRT0_PRTLNSTS_MASK (0x3 << 10) +#define DWC2_HPRT0_PRTLNSTS_OFFSET 10 +#define DWC2_HPRT0_PRTPWR (1 << 12) +#define DWC2_HPRT0_PRTPWR_OFFSET 12 +#define DWC2_HPRT0_PRTTSTCTL_MASK (0xF << 13) +#define DWC2_HPRT0_PRTTSTCTL_OFFSET 13 +#define DWC2_HPRT0_PRTSPD_MASK (0x3 << 17) +#define DWC2_HPRT0_PRTSPD_OFFSET 17 +#define DWC2_HAINT_CH0 (1 << 0) +#define DWC2_HAINT_CH0_OFFSET 0 +#define DWC2_HAINT_CH1 (1 << 1) +#define DWC2_HAINT_CH1_OFFSET 1 +#define DWC2_HAINT_CH2 (1 << 2) +#define DWC2_HAINT_CH2_OFFSET 2 +#define DWC2_HAINT_CH3 (1 << 3) +#define DWC2_HAINT_CH3_OFFSET 3 +#define DWC2_HAINT_CH4 (1 << 4) +#define DWC2_HAINT_CH4_OFFSET 4 +#define DWC2_HAINT_CH5 (1 << 5) +#define DWC2_HAINT_CH5_OFFSET 5 +#define DWC2_HAINT_CH6 (1 << 6) +#define DWC2_HAINT_CH6_OFFSET 6 +#define DWC2_HAINT_CH7 (1 << 7) +#define DWC2_HAINT_CH7_OFFSET 7 +#define DWC2_HAINT_CH8 (1 << 8) +#define DWC2_HAINT_CH8_OFFSET 8 +#define DWC2_HAINT_CH9 (1 << 9) +#define DWC2_HAINT_CH9_OFFSET 9 +#define DWC2_HAINT_CH10 (1 << 10) +#define DWC2_HAINT_CH10_OFFSET 10 +#define DWC2_HAINT_CH11 (1 << 11) +#define DWC2_HAINT_CH11_OFFSET 11 +#define DWC2_HAINT_CH12 (1 << 12) +#define DWC2_HAINT_CH12_OFFSET 12 +#define DWC2_HAINT_CH13 (1 << 13) +#define DWC2_HAINT_CH13_OFFSET 13 +#define DWC2_HAINT_CH14 (1 << 14) +#define DWC2_HAINT_CH14_OFFSET 14 +#define DWC2_HAINT_CH15 (1 << 15) +#define DWC2_HAINT_CH15_OFFSET 15 +#define DWC2_HAINT_CHINT_MASK 0xffff +#define DWC2_HAINT_CHINT_OFFSET 0 +#define DWC2_HAINTMSK_CH0 (1 << 0) +#define DWC2_HAINTMSK_CH0_OFFSET 0 +#define DWC2_HAINTMSK_CH1 (1 << 1) +#define DWC2_HAINTMSK_CH1_OFFSET 1 +#define DWC2_HAINTMSK_CH2 (1 << 2) +#define DWC2_HAINTMSK_CH2_OFFSET 2 +#define DWC2_HAINTMSK_CH3 (1 << 3) +#define DWC2_HAINTMSK_CH3_OFFSET 3 +#define DWC2_HAINTMSK_CH4 (1 << 4) +#define DWC2_HAINTMSK_CH4_OFFSET 4 +#define DWC2_HAINTMSK_CH5 (1 << 5) +#define DWC2_HAINTMSK_CH5_OFFSET 5 +#define DWC2_HAINTMSK_CH6 (1 << 6) +#define DWC2_HAINTMSK_CH6_OFFSET 6 +#define DWC2_HAINTMSK_CH7 (1 << 7) +#define DWC2_HAINTMSK_CH7_OFFSET 7 +#define DWC2_HAINTMSK_CH8 (1 << 8) +#define DWC2_HAINTMSK_CH8_OFFSET 8 +#define DWC2_HAINTMSK_CH9 (1 << 9) +#define DWC2_HAINTMSK_CH9_OFFSET 9 +#define DWC2_HAINTMSK_CH10 (1 << 10) +#define DWC2_HAINTMSK_CH10_OFFSET 10 +#define DWC2_HAINTMSK_CH11 (1 << 11) +#define DWC2_HAINTMSK_CH11_OFFSET 11 +#define DWC2_HAINTMSK_CH12 (1 << 12) +#define DWC2_HAINTMSK_CH12_OFFSET 12 +#define DWC2_HAINTMSK_CH13 (1 << 13) +#define DWC2_HAINTMSK_CH13_OFFSET 13 +#define DWC2_HAINTMSK_CH14 (1 << 14) +#define DWC2_HAINTMSK_CH14_OFFSET 14 +#define DWC2_HAINTMSK_CH15 (1 << 15) +#define DWC2_HAINTMSK_CH15_OFFSET 15 +#define DWC2_HAINTMSK_CHINT_MASK 0xffff +#define DWC2_HAINTMSK_CHINT_OFFSET 0 +#define DWC2_HCCHAR_MPS_MASK (0x7FF << 0) +#define DWC2_HCCHAR_MPS_OFFSET 0 +#define DWC2_HCCHAR_EPNUM_MASK (0xF << 11) +#define DWC2_HCCHAR_EPNUM_OFFSET 11 +#define DWC2_HCCHAR_EPDIR (1 << 15) +#define DWC2_HCCHAR_EPDIR_OFFSET 15 +#define DWC2_HCCHAR_LSPDDEV (1 << 17) +#define DWC2_HCCHAR_LSPDDEV_OFFSET 17 +#define DWC2_HCCHAR_EPTYPE_CONTROL 0 +#define DWC2_HCCHAR_EPTYPE_ISOC 1 +#define DWC2_HCCHAR_EPTYPE_BULK 2 +#define DWC2_HCCHAR_EPTYPE_INTR 3 +#define DWC2_HCCHAR_EPTYPE_MASK (0x3 << 18) +#define DWC2_HCCHAR_EPTYPE_OFFSET 18 +#define DWC2_HCCHAR_MULTICNT_MASK (0x3 << 20) +#define DWC2_HCCHAR_MULTICNT_OFFSET 20 +#define DWC2_HCCHAR_DEVADDR_MASK (0x7F << 22) +#define DWC2_HCCHAR_DEVADDR_OFFSET 22 +#define DWC2_HCCHAR_ODDFRM (1 << 29) +#define DWC2_HCCHAR_ODDFRM_OFFSET 29 +#define DWC2_HCCHAR_CHDIS (1 << 30) +#define DWC2_HCCHAR_CHDIS_OFFSET 30 +#define DWC2_HCCHAR_CHEN (1 << 31) +#define DWC2_HCCHAR_CHEN_OFFSET 31 +#define DWC2_HCSPLT_PRTADDR_MASK (0x7F << 0) +#define DWC2_HCSPLT_PRTADDR_OFFSET 0 +#define DWC2_HCSPLT_HUBADDR_MASK (0x7F << 7) +#define DWC2_HCSPLT_HUBADDR_OFFSET 7 +#define DWC2_HCSPLT_XACTPOS_MASK (0x3 << 14) +#define DWC2_HCSPLT_XACTPOS_OFFSET 14 +#define DWC2_HCSPLT_COMPSPLT (1 << 16) +#define DWC2_HCSPLT_COMPSPLT_OFFSET 16 +#define DWC2_HCSPLT_SPLTENA (1 << 31) +#define DWC2_HCSPLT_SPLTENA_OFFSET 31 +#define DWC2_HCINT_XFERCOMP (1 << 0) +#define DWC2_HCINT_XFERCOMP_OFFSET 0 +#define DWC2_HCINT_CHHLTD (1 << 1) +#define DWC2_HCINT_CHHLTD_OFFSET 1 +#define DWC2_HCINT_AHBERR (1 << 2) +#define DWC2_HCINT_AHBERR_OFFSET 2 +#define DWC2_HCINT_STALL (1 << 3) +#define DWC2_HCINT_STALL_OFFSET 3 +#define DWC2_HCINT_NAK (1 << 4) +#define DWC2_HCINT_NAK_OFFSET 4 +#define DWC2_HCINT_ACK (1 << 5) +#define DWC2_HCINT_ACK_OFFSET 5 +#define DWC2_HCINT_NYET (1 << 6) +#define DWC2_HCINT_NYET_OFFSET 6 +#define DWC2_HCINT_XACTERR (1 << 7) +#define DWC2_HCINT_XACTERR_OFFSET 7 +#define DWC2_HCINT_BBLERR (1 << 8) +#define DWC2_HCINT_BBLERR_OFFSET 8 +#define DWC2_HCINT_FRMOVRUN (1 << 9) +#define DWC2_HCINT_FRMOVRUN_OFFSET 9 +#define DWC2_HCINT_DATATGLERR (1 << 10) +#define DWC2_HCINT_DATATGLERR_OFFSET 10 +#define DWC2_HCINT_BNA (1 << 11) +#define DWC2_HCINT_BNA_OFFSET 11 +#define DWC2_HCINT_XCS_XACT (1 << 12) +#define DWC2_HCINT_XCS_XACT_OFFSET 12 +#define DWC2_HCINT_FRM_LIST_ROLL (1 << 13) +#define DWC2_HCINT_FRM_LIST_ROLL_OFFSET 13 +#define DWC2_HCINTMSK_XFERCOMPL (1 << 0) +#define DWC2_HCINTMSK_XFERCOMPL_OFFSET 0 +#define DWC2_HCINTMSK_CHHLTD (1 << 1) +#define DWC2_HCINTMSK_CHHLTD_OFFSET 1 +#define DWC2_HCINTMSK_AHBERR (1 << 2) +#define DWC2_HCINTMSK_AHBERR_OFFSET 2 +#define DWC2_HCINTMSK_STALL (1 << 3) +#define DWC2_HCINTMSK_STALL_OFFSET 3 +#define DWC2_HCINTMSK_NAK (1 << 4) +#define DWC2_HCINTMSK_NAK_OFFSET 4 +#define DWC2_HCINTMSK_ACK (1 << 5) +#define DWC2_HCINTMSK_ACK_OFFSET 5 +#define DWC2_HCINTMSK_NYET (1 << 6) +#define DWC2_HCINTMSK_NYET_OFFSET 6 +#define DWC2_HCINTMSK_XACTERR (1 << 7) +#define DWC2_HCINTMSK_XACTERR_OFFSET 7 +#define DWC2_HCINTMSK_BBLERR (1 << 8) +#define DWC2_HCINTMSK_BBLERR_OFFSET 8 +#define DWC2_HCINTMSK_FRMOVRUN (1 << 9) +#define DWC2_HCINTMSK_FRMOVRUN_OFFSET 9 +#define DWC2_HCINTMSK_DATATGLERR (1 << 10) +#define DWC2_HCINTMSK_DATATGLERR_OFFSET 10 +#define DWC2_HCINTMSK_BNA (1 << 11) +#define DWC2_HCINTMSK_BNA_OFFSET 11 +#define DWC2_HCINTMSK_XCS_XACT (1 << 12) +#define DWC2_HCINTMSK_XCS_XACT_OFFSET 12 +#define DWC2_HCINTMSK_FRM_LIST_ROLL (1 << 13) +#define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET 13 +#define DWC2_HCTSIZ_XFERSIZE_MASK 0x7ffff +#define DWC2_HCTSIZ_XFERSIZE_OFFSET 0 +#define DWC2_HCTSIZ_SCHINFO_MASK 0xff +#define DWC2_HCTSIZ_SCHINFO_OFFSET 0 +#define DWC2_HCTSIZ_NTD_MASK (0xff << 8) +#define DWC2_HCTSIZ_NTD_OFFSET 8 +#define DWC2_HCTSIZ_PKTCNT_MASK (0x3ff << 19) +#define DWC2_HCTSIZ_PKTCNT_OFFSET 19 +#define DWC2_HCTSIZ_PID_MASK (0x3 << 29) +#define DWC2_HCTSIZ_PID_OFFSET 29 +#define DWC2_HCTSIZ_DOPNG (1 << 31) +#define DWC2_HCTSIZ_DOPNG_OFFSET 31 +#define DWC2_HCDMA_CTD_MASK (0xFF << 3) +#define DWC2_HCDMA_CTD_OFFSET 3 +#define DWC2_HCDMA_DMA_ADDR_MASK (0x1FFFFF << 11) +#define DWC2_HCDMA_DMA_ADDR_OFFSET 11 +#define DWC2_PCGCCTL_STOPPCLK (1 << 0) +#define DWC2_PCGCCTL_STOPPCLK_OFFSET 0 +#define DWC2_PCGCCTL_GATEHCLK (1 << 1) +#define DWC2_PCGCCTL_GATEHCLK_OFFSET 1 +#define DWC2_PCGCCTL_PWRCLMP (1 << 2) +#define DWC2_PCGCCTL_PWRCLMP_OFFSET 2 +#define DWC2_PCGCCTL_RSTPDWNMODULE (1 << 3) +#define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET 3 +#define DWC2_PCGCCTL_PHYSUSPENDED (1 << 4) +#define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET 4 +#define DWC2_PCGCCTL_ENBL_SLEEP_GATING (1 << 5) +#define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET 5 +#define DWC2_PCGCCTL_PHY_IN_SLEEP (1 << 6) +#define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET 6 +#define DWC2_PCGCCTL_DEEP_SLEEP (1 << 7) +#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7 +#define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12) +#define DWC2_SNPSID_DEVID_MASK (0xfffff << 12) +#define DWC2_SNPSID_DEVID_OFFSET 12 + +/* Host controller specific */ +#define DWC2_HC_PID_DATA0 0 +#define DWC2_HC_PID_DATA2 1 +#define DWC2_HC_PID_DATA1 2 +#define DWC2_HC_PID_MDATA 3 +#define DWC2_HC_PID_SETUP 3 + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* Default driver configuration */ +#define CONFIG_DWC2_DMA_ENABLE +#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ +#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ +#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ +#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */ +#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS) +#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ +#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ +#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535 +#define CONFIG_DWC2_MAX_PACKET_COUNT 511 + +#define DWC2_PHY_TYPE_FS 0 +#define DWC2_PHY_TYPE_UTMI 1 +#define DWC2_PHY_TYPE_ULPI 2 +#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ +#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ + +#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ +#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ +#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */ +#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */ +#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */ +#undef CONFIG_DWC2_THR_CTL /* Threshold control */ +#define CONFIG_DWC2_TX_THR_LENGTH 64 +#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */ + +#endif /* __DWC2_H__ */ diff --git a/drivers/usb/host/ehci-armada100.c b/drivers/usb/host/ehci-armada100.c index 636b6e5da0..012eb3a1a4 100644 --- a/drivers/usb/host/ehci-armada100.c +++ b/drivers/usb/host/ehci-armada100.c @@ -22,7 +22,8 @@ /* * EHCI host controller init */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { if (utmi_init() < 0) return -1; diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 67444b26ef..9a8f004ece 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -21,7 +21,8 @@ */ #define EN_UPLL_TIMEOUT 500UL -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; ulong start_time, tmp_time; @@ -39,7 +40,11 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) } /* Enable USB Host clock */ +#ifdef CPU_HAS_PCR + at91_periph_clk_enable(ATMEL_ID_UHPHS); +#else writel(1 << ATMEL_ID_UHPHS, &pmc->pcer); +#endif *hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI; *hcor = (struct ehci_hcor *)((uint32_t)*hccr + @@ -54,7 +59,11 @@ int ehci_hcd_stop(int index) ulong start_time, tmp_time; /* Disable USB Host Clock */ +#ifdef CPU_HAS_PCR + at91_periph_clk_disable(ATMEL_ID_UHPHS); +#else writel(1 << ATMEL_ID_UHPHS, &pmc->pcdr); +#endif start_time = get_timer(0); /* Disable UTMI PLL */ diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 155677e0d9..f3c077d82e 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include "ehci.h" @@ -30,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; struct exynos_ehci { struct exynos_usb_phy *usb; struct ehci_hccr *hcd; + struct gpio_desc vbus_gpio; }; static struct exynos_ehci exynos; @@ -58,6 +60,10 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) exynos->hcd = (struct ehci_hccr *)addr; + /* Vbus gpio */ + gpio_request_by_name_nodev(blob, node, "samsung,vbus-gpio", 0, + &exynos->vbus_gpio, GPIOD_IS_OUT); + depth = 0; node = fdtdec_next_compatible_subnode(blob, node, COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth); @@ -80,12 +86,9 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) } #endif -/* Setup the EHCI host controller. */ -static void setup_usb_phy(struct exynos_usb_phy *usb) +static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb) { - set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); - - set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); + u32 hsic_ctrl; clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | @@ -107,6 +110,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); + + /* HSIC Phy Setting */ + hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ); + + clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + + hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK) + << HSIC_CTRL_REFCLKDIV_SHIFT) + | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK) + << HSIC_CTRL_REFCLKSEL_SHIFT) + | HSIC_CTRL_UTMISWRST); + + setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + + udelay(10); + + clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST | + HSIC_CTRL_UTMISWRST); + + clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST | + HSIC_CTRL_UTMISWRST); + udelay(20); /* EHCI Ctrl setting */ @@ -117,9 +146,37 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) EHCICTRL_ENAINCR16); } -/* Reset the EHCI host controller. */ -static void reset_usb_phy(struct exynos_usb_phy *usb) +static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb) +{ + writel(CLK_24MHZ, &usb->usbphyclk); + + clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | + PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 | + PHYPWR_NORMAL_MASK_PHY0)); + + setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); + udelay(10); + clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); +} + +static void setup_usb_phy(struct exynos_usb_phy *usb) { + set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); + + set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); + + if (cpu_is_exynos5()) + exynos5_setup_usb_phy(usb); + else if (cpu_is_exynos4()) + if (proid_is_exynos4412()) + exynos4412_setup_usb_phy((struct exynos4412_usb_phy *) + usb); +} + +static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb) +{ + u32 hsic_ctrl; + /* HOST_PHY reset */ setbits_le32(&usb->usbphyctrl0, HOST_CTRL0_PHYSWRST | @@ -128,6 +185,33 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + /* HSIC Phy reset */ + hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ | + HSIC_CTRL_PHYSWRST); + + setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); +} + +static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb) +{ + setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | + PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 | + PHYPWR_NORMAL_MASK_PHY0)); +} + +/* Reset the EHCI host controller. */ +static void reset_usb_phy(struct exynos_usb_phy *usb) +{ + if (cpu_is_exynos5()) + exynos5_reset_usb_phy(usb); + else if (cpu_is_exynos4()) + if (proid_is_exynos4412()) + exynos4412_reset_usb_phy((struct exynos4412_usb_phy *) + usb); + set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } @@ -136,7 +220,8 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct exynos_ehci *ctx = &exynos; @@ -150,8 +235,16 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci(); #endif +#ifdef CONFIG_OF_CONTROL + /* setup the Vbus gpio here */ + if (dm_gpio_is_valid(&ctx->vbus_gpio)) + dm_gpio_set_value(&ctx->vbus_gpio, 1); +#endif + setup_usb_phy(ctx->usb); + board_usb_init(index, init); + *hccr = ctx->hcd; *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); diff --git a/drivers/usb/host/ehci-faraday.c b/drivers/usb/host/ehci-faraday.c index 4a36acdaec..3b761bc326 100644 --- a/drivers/usb/host/ehci-faraday.c +++ b/drivers/usb/host/ehci-faraday.c @@ -33,8 +33,8 @@ static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs) * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr, - struct ehci_hcor **ret_hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor) { struct ehci_hccr *hccr; struct ehci_hcor *hcor; diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 0ef6f238d5..5d4288d38f 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -14,9 +14,17 @@ #include #include #include +#include +#include #include "ehci.h" +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +static void set_txfifothresh(struct usb_ehci *, u32); + /* Check USB PHY clock valid */ static int usb_phy_clk_valid(struct usb_ehci *ehci) { @@ -35,18 +43,42 @@ static int usb_phy_clk_valid(struct usb_ehci *ehci) * * Excerpts from linux ehci fsl driver. */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - struct usb_ehci *ehci; + struct usb_ehci *ehci = NULL; const char *phy_type = NULL; size_t len; + char current_usb_controller[5]; #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY char usb_phy[5]; usb_phy[0] = '\0'; #endif + if (has_erratum_a007075()) { + /* + * A 5ms delay is needed after applying soft-reset to the + * controller to let external ULPI phy come out of reset. + * This delay needs to be added before re-initializing + * the controller after soft-resetting completes + */ + mdelay(5); + } + memset(current_usb_controller, '\0', 5); + snprintf(current_usb_controller, 4, "usb%d", index+1); + + switch (index) { + case 0: + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; + break; + case 1: + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; + break; + default: + printf("ERROR: wrong controller index!!\n"); + break; + }; - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); @@ -58,8 +90,9 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ - if (hwconfig_sub("usb1", "phy_type")) - phy_type = hwconfig_subarg("usb1", "phy_type", &len); + if (hwconfig_sub(current_usb_controller, "phy_type")) + phy_type = hwconfig_subarg(current_usb_controller, + "phy_type", &len); else phy_type = getenv("usb_phy_type"); @@ -74,17 +107,22 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) #endif } - if (!strcmp(phy_type, "utmi")) { + if (!strncmp(phy_type, "utmi", 4)) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) - setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); - setbits_be32(&ehci->control, UTMI_PHY_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + PHY_CLK_SEL_UTMI); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */ #endif out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); - setbits_be32(&ehci->control, USB_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + USB_EN); } else { - setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); - clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + PHY_CLK_SEL_ULPI); + clrsetbits_be32(&ehci->control, UTMI_PHY_EN | + CONTROL_REGISTER_W1C_MASK, USB_EN); udelay(1000); /* delay required for PHY Clk to appear */ if (!usb_phy_clk_valid(ehci)) return -EINVAL; @@ -97,6 +135,9 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) in_le32(&ehci->usbmode); + if (has_erratum_a007798()) + set_txfifothresh(ehci, TXFIFOTHRESH); + return 0; } @@ -108,3 +149,198 @@ int ehci_hcd_stop(int index) { return 0; } + +/* + * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register + * to counter DDR latencies in writing data into Tx buffer. + * This prevents Tx buffer from getting underrun + */ +static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) +{ + u32 cmd; + cmd = ehci_readl(&ehci->txfilltuning); + cmd &= ~TXFIFO_THRESH_MASK; + cmd |= TXFIFO_THRESH(txfifo_thresh); + ehci_writel(&ehci->txfilltuning, cmd); +} + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, + const char *phy_type, int start_offset) +{ + const char *compat_dr = "fsl-usb2-dr"; + const char *compat_mph = "fsl-usb2-mph"; + const char *prop_mode = "dr_mode"; + const char *prop_type = "phy_type"; + const char *node_type = NULL; + int node_offset; + int err; + + node_offset = fdt_node_offset_by_compatible(blob, + start_offset, compat_mph); + if (node_offset < 0) { + node_offset = fdt_node_offset_by_compatible(blob, + start_offset, + compat_dr); + if (node_offset < 0) { + printf("WARNING: could not find compatible node: %s", + fdt_strerror(node_offset)); + return -1; + } + node_type = compat_dr; + } else { + node_type = compat_mph; + } + + if (mode) { + err = fdt_setprop(blob, node_offset, prop_mode, mode, + strlen(mode) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_mode, node_type, fdt_strerror(err)); + } + + if (phy_type) { + err = fdt_setprop(blob, node_offset, prop_type, phy_type, + strlen(phy_type) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_type, node_type, fdt_strerror(err)); + } + + return node_offset; +} + +static const char *fdt_usb_get_node_type(void *blob, int start_offset, + int *node_offset) +{ + const char *compat_dr = "fsl-usb2-dr"; + const char *compat_mph = "fsl-usb2-mph"; + const char *node_type = NULL; + + *node_offset = fdt_node_offset_by_compatible(blob, start_offset, + compat_mph); + if (*node_offset < 0) { + *node_offset = fdt_node_offset_by_compatible(blob, + start_offset, + compat_dr); + if (*node_offset < 0) { + printf("ERROR: could not find compatible node: %s\n", + fdt_strerror(*node_offset)); + } else { + node_type = compat_dr; + } + } else { + node_type = compat_mph; + } + + return node_type; +} + +static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum, + int start_offset) +{ + int node_offset, err; + const char *node_type = NULL; + + node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset); + if (!node_type) + return -1; + + err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0); + if (err < 0) { + printf("ERROR: could not set %s for %s: %s.\n", + prop_erratum, node_type, fdt_strerror(err)); + } + + return node_offset; +} + +void fdt_fixup_dr_usb(void *blob, bd_t *bd) +{ + static const char * const modes[] = { "host", "peripheral", "otg" }; + static const char * const phys[] = { "ulpi", "utmi" }; + int usb_erratum_a006261_off = -1; + int usb_erratum_a007075_off = -1; + int usb_erratum_a007792_off = -1; + int usb_mode_off = -1; + int usb_phy_off = -1; + char str[5]; + int i, j; + + for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { + const char *dr_mode_type = NULL; + const char *dr_phy_type = NULL; + int mode_idx = -1, phy_idx = -1; + + snprintf(str, 5, "%s%d", "usb", i); + if (hwconfig(str)) { + for (j = 0; j < ARRAY_SIZE(modes); j++) { + if (hwconfig_subarg_cmp(str, "dr_mode", + modes[j])) { + mode_idx = j; + break; + } + } + + for (j = 0; j < ARRAY_SIZE(phys); j++) { + if (hwconfig_subarg_cmp(str, "phy_type", + phys[j])) { + phy_idx = j; + break; + } + } + + if (mode_idx < 0 && phy_idx < 0) { + printf("WARNING: invalid phy or mode\n"); + return; + } + + if (mode_idx > -1) + dr_mode_type = modes[mode_idx]; + + if (phy_idx > -1) + dr_phy_type = phys[phy_idx]; + } + + usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, + dr_mode_type, NULL, + usb_mode_off); + + if (usb_mode_off < 0) + return; + + usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, + NULL, dr_phy_type, + usb_phy_off); + + if (usb_phy_off < 0) + return; + + if (has_erratum_a006261()) { + usb_erratum_a006261_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a006261", + usb_erratum_a006261_off); + if (usb_erratum_a006261_off < 0) + return; + } + if (has_erratum_a007075()) { + usb_erratum_a007075_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a007075", + usb_erratum_a007075_off); + if (usb_erratum_a007075_off < 0) + return; + } + if (has_erratum_a007792()) { + usb_erratum_a007792_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a007792", + usb_erratum_a007792_off); + if (usb_erratum_a007792_off < 0) + return; + } + } +} +#endif diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index fdad739724..f1fb190132 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -36,6 +36,12 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif +/* + * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. + * Let's time out after 8 to have a little safety margin on top of that. + */ +#define HCHALT_TIMEOUT (8 * 1000) + static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; #define ALIGN_END_ADDR(type, ptr, size) \ @@ -113,15 +119,12 @@ static struct descriptor { #define ehci_is_TDI() (0) #endif -int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) +__weak int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) { return PORTSC_PSPD(reg); } -int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) - __attribute__((weak, alias("__ehci_get_port_speed"))); - -void __ehci_set_usbmode(int index) +__weak void ehci_set_usbmode(int index) { uint32_t tmp; uint32_t *reg_ptr; @@ -135,17 +138,11 @@ void __ehci_set_usbmode(int index) ehci_writel(reg_ptr, tmp); } -void ehci_set_usbmode(int index) - __attribute__((weak, alias("__ehci_set_usbmode"))); - -void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) +__weak void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) { mdelay(50); } -void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) - __attribute__((weak, alias("__ehci_powerup_fixup"))); - static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) { uint32_t result; @@ -190,6 +187,39 @@ out: return ret; } +static int ehci_shutdown(struct ehci_ctrl *ctrl) +{ + int i, ret = 0; + uint32_t cmd, reg; + + if (!ctrl || !ctrl->hcor) + return -EINVAL; + + cmd = ehci_readl(&ctrl->hcor->or_usbcmd); + cmd &= ~(CMD_PSE | CMD_ASE); + ehci_writel(&ctrl->hcor->or_usbcmd, cmd); + ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0, + 100 * 1000); + + if (!ret) { + for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) { + reg = ehci_readl(&ctrl->hcor->or_portsc[i]); + reg |= EHCI_PS_SUSP; + ehci_writel(&ctrl->hcor->or_portsc[i], reg); + } + + cmd &= ~CMD_RUN; + ehci_writel(&ctrl->hcor->or_usbcmd, cmd); + ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT, + HCHALT_TIMEOUT); + } + + if (ret) + puts("EHCI failed to shut down host controller.\n"); + + return ret; +} + static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) { uint32_t delta, next; @@ -234,6 +264,29 @@ static inline u8 ehci_encode_speed(enum usb_device_speed speed) return QH_FULL_SPEED; } +static void ehci_update_endpt2_dev_n_port(struct usb_device *dev, + struct QH *qh) +{ + struct usb_device *ttdev; + + if (dev->speed != USB_SPEED_LOW && dev->speed != USB_SPEED_FULL) + return; + + /* + * For full / low speed devices we need to get the devnum and portnr of + * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs + * in the tree before that one! + */ + ttdev = dev; + while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH) + ttdev = ttdev->parent; + if (!ttdev->parent) + return; + + qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) | + QH_ENDPT2_HUBADDR(ttdev->parent->devnum)); +} + static int ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) @@ -351,11 +404,11 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); qh->qh_endpt1 = cpu_to_hc32(endpt); - endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) | - QH_ENDPT2_HUBADDR(dev->parent->devnum) | - QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); + endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); qh->qh_endpt2 = cpu_to_hc32(endpt); + ehci_update_endpt2_dev_n_port(dev, qh); qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); tdp = &qh->qh_overlay.qt_next; @@ -808,6 +861,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, } break; case USB_PORT_FEAT_TEST: + ehci_shutdown(ctrl); reg &= ~(0xf << 16); reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16; ehci_writel(status_reg, reg); @@ -856,7 +910,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, } mdelay(1); - len = min3(srclen, le16_to_cpu(req->length), length); + len = min3(srclen, (int)le16_to_cpu(req->length), length); if (srcptr != NULL && len > 0) memcpy(buffer, srcptr, len); else @@ -878,31 +932,37 @@ unknown: int usb_lowlevel_stop(int index) { + ehci_shutdown(&ehcic[index]); return ehci_hcd_stop(index); } -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { uint32_t reg; uint32_t cmd; struct QH *qh_list; struct QH *periodic; int i; + int rc; - if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor)) - return -1; + rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor); + if (rc) + return rc; + if (init == USB_INIT_DEVICE) + goto done; /* EHCI spec section 4.1 */ if (ehci_reset(index)) return -1; #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) - if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor)) - return -1; + rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor); + if (rc) + return rc; #endif /* Set the high address word (aka segment) for 64-bit controller */ if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1) - ehci_writel(ehcic[index].hcor->or_ctrldssegment, 0); + ehci_writel(&ehcic[index].hcor->or_ctrldssegment, 0); qh_list = &ehcic[index].qh_list; @@ -911,7 +971,6 @@ int usb_lowlevel_init(int index, void **controller) qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | QH_ENDPT1_EPS(USB_SPEED_HIGH)); - qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); qh_list->qh_overlay.qt_token = @@ -927,6 +986,7 @@ int usb_lowlevel_init(int index, void **controller) * Set up periodic list * Step 1: Parent QH for all periodic transfers. */ + ehcic[index].periodic_schedules = 0; periodic = &ehcic[index].periodic_queue; memset(periodic, 0, sizeof(*periodic)); periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); @@ -951,8 +1011,8 @@ int usb_lowlevel_init(int index, void **controller) if (!ehcic[index].periodic_list) return -ENOMEM; for (i = 0; i < 1024; i++) { - ehcic[index].periodic_list[i] = (uint32_t)periodic - | QH_LINK_TYPE_QH; + ehcic[index].periodic_list[i] = cpu_to_hc32((uint32_t)periodic + | QH_LINK_TYPE_QH); } flush_dcache_range((uint32_t)ehcic[index].periodic_list, @@ -999,7 +1059,7 @@ int usb_lowlevel_init(int index, void **controller) printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); ehcic[index].rootdev = 0; - +done: *controller = &ehcic[index]; return 0; } @@ -1036,13 +1096,14 @@ submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } struct int_queue { + int elementsize; struct QH *first; struct QH *current; struct QH *last; struct qTD *tds; }; -#define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f) +#define NEXT_QH(qh) (struct QH *)(hc32_to_cpu((qh)->qh_link) & ~0x1f) static int enable_periodic(struct ehci_ctrl *ctrl) @@ -1085,16 +1146,31 @@ disable_periodic(struct ehci_ctrl *ctrl) return 0; } -static int periodic_schedules; - struct int_queue * create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, - int elementsize, void *buffer) + int elementsize, void *buffer, int interval) { struct ehci_ctrl *ctrl = dev->controller; struct int_queue *result = NULL; int i; + /* + * Interrupt transfers requiring several transactions are not supported + * because bInterval is ignored. + * + * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 + * <= PKT_ALIGN if several qTDs are required, while the USB + * specification does not constrain this for interrupt transfers. That + * means that ehci_submit_async() would support interrupt transfers + * requiring several transactions only as long as the transfer size does + * not require more than a single qTD. + */ + if (elementsize > usb_maxpacket(dev, pipe)) { + printf("%s: xfers requiring several transactions are not supported.\n", + __func__); + return NULL; + } + debug("Enter create_int_queue\n"); if (usb_pipetype(pipe) != PIPE_INTERRUPT) { debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); @@ -1115,14 +1191,17 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, debug("ehci intr queue: out of memory\n"); goto fail1; } - result->first = memalign(32, sizeof(struct QH) * queuesize); + result->elementsize = elementsize; + result->first = memalign(USB_DMA_MINALIGN, + sizeof(struct QH) * queuesize); if (!result->first) { debug("ehci intr queue: out of memory\n"); goto fail2; } result->current = result->first; result->last = result->first + queuesize - 1; - result->tds = memalign(32, sizeof(struct qTD) * queuesize); + result->tds = memalign(USB_DMA_MINALIGN, + sizeof(struct qTD) * queuesize); if (!result->tds) { debug("ehci intr queue: out of memory\n"); goto fail3; @@ -1135,40 +1214,45 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, struct qTD *td = result->tds + i; void **buf = &qh->buffer; - qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH; + qh->qh_link = cpu_to_hc32((uint32_t)(qh+1) | QH_LINK_TYPE_QH); if (i == queuesize - 1) - qh->qh_link = QH_LINK_TERMINATE; + qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); - qh->qh_overlay.qt_next = (uint32_t)td; - qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */ + qh->qh_overlay.qt_next = cpu_to_hc32((uint32_t)td); + qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + qh->qh_endpt1 = + cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ (usb_maxpacket(dev, pipe) << 16) | /* MPS */ (1 << 14) | QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ - (usb_pipedevice(pipe) << 0); - qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */ - (1 << 0); /* S-mask: microframe 0 */ + (usb_pipedevice(pipe) << 0)); + qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */ + (1 << 0)); /* S-mask: microframe 0 */ if (dev->speed == USB_SPEED_LOW || dev->speed == USB_SPEED_FULL) { - debug("TT: port: %d, hub address: %d\n", - dev->portnr, dev->parent->devnum); - qh->qh_endpt2 |= (dev->portnr << 23) | - (dev->parent->devnum << 16) | - (0x1c << 8); /* C-mask: microframes 2-4 */ + /* C-mask: microframes 2-4 */ + qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8)); } + ehci_update_endpt2_dev_n_port(dev, qh); - td->qt_next = QT_NEXT_TERMINATE; - td->qt_altnext = QT_NEXT_TERMINATE; + td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); debug("communication direction is '%s'\n", usb_pipein(pipe) ? "in" : "out"); - td->qt_token = (elementsize << 16) | + td->qt_token = cpu_to_hc32((elementsize << 16) | ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ - 0x80; /* active */ - td->qt_buffer[0] = (uint32_t)buffer + i * elementsize; - td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff; - td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff; - td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff; - td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff; + 0x80); /* active */ + td->qt_buffer[0] = + cpu_to_hc32((uint32_t)buffer + i * elementsize); + td->qt_buffer[1] = + cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff); + td->qt_buffer[2] = + cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff); + td->qt_buffer[3] = + cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff); + td->qt_buffer[4] = + cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); *buf = buffer + i * elementsize; } @@ -1183,15 +1267,17 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, ALIGN_END_ADDR(struct qTD, result->tds, queuesize)); - if (disable_periodic(ctrl) < 0) { - debug("FATAL: periodic should never fail, but did"); - goto fail3; + if (ctrl->periodic_schedules > 0) { + if (disable_periodic(ctrl) < 0) { + debug("FATAL: periodic should never fail, but did"); + goto fail3; + } } /* hook up to periodic list */ struct QH *list = &ctrl->periodic_queue; result->last->qh_link = list->qh_link; - list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH; + list->qh_link = cpu_to_hc32((uint32_t)result->first | QH_LINK_TYPE_QH); flush_dcache_range((uint32_t)result->last, ALIGN_END_ADDR(struct QH, result->last, 1)); @@ -1202,7 +1288,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, debug("FATAL: periodic should never fail, but did"); goto fail3; } - periodic_schedules++; + ctrl->periodic_schedules++; debug("Exit create_int_queue\n"); return result; @@ -1221,6 +1307,7 @@ fail1: void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) { struct QH *cur = queue->current; + struct qTD *cur_td; /* depleted queue */ if (cur == NULL) { @@ -1228,20 +1315,26 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) return NULL; } /* still active */ - invalidate_dcache_range((uint32_t)cur, - ALIGN_END_ADDR(struct QH, cur, 1)); - if (cur->qh_overlay.qt_token & 0x80) { - debug("Exit poll_int_queue with no completed intr transfer. " - "token is %x\n", cur->qh_overlay.qt_token); + cur_td = &queue->tds[queue->current - queue->first]; + invalidate_dcache_range((uint32_t)cur_td, + ALIGN_END_ADDR(struct qTD, cur_td, 1)); + if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) & + QT_TOKEN_STATUS_ACTIVE) { + debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", + hc32_to_cpu(cur_td->qt_token)); return NULL; } if (!(cur->qh_link & QH_LINK_TERMINATE)) queue->current++; else queue->current = NULL; - debug("Exit poll_int_queue with completed intr transfer. " - "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token, - &cur->qh_overlay.qt_token, queue->first); + + invalidate_dcache_range((uint32_t)cur->buffer, + ALIGN_END_ADDR(char, cur->buffer, + queue->elementsize)); + + debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n", + hc32_to_cpu(cur_td->qt_token), cur, queue->first); return cur->buffer; } @@ -1257,15 +1350,17 @@ destroy_int_queue(struct usb_device *dev, struct int_queue *queue) debug("FATAL: periodic should never fail, but did"); goto out; } - periodic_schedules--; + ctrl->periodic_schedules--; struct QH *cur = &ctrl->periodic_queue; timeout = get_timer(0) + 500; /* abort after 500ms */ - while (!(cur->qh_link & QH_LINK_TERMINATE)) { + while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { debug("considering %p, with qh_link %x\n", cur, cur->qh_link); if (NEXT_QH(cur) == queue->first) { debug("found candidate. removing from chain\n"); cur->qh_link = queue->last->qh_link; + flush_dcache_range((uint32_t)cur, + ALIGN_END_ADDR(struct QH, cur, 1)); result = 0; break; } @@ -1277,7 +1372,7 @@ destroy_int_queue(struct usb_device *dev, struct int_queue *queue) } } - if (periodic_schedules > 0) { + if (ctrl->periodic_schedules > 0) { result = enable_periodic(ctrl); if (result < 0) debug("FATAL: periodic should never fail, but did"); @@ -1303,24 +1398,9 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", dev, pipe, buffer, length, interval); - /* - * Interrupt transfers requiring several transactions are not supported - * because bInterval is ignored. - * - * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 - * <= PKT_ALIGN if several qTDs are required, while the USB - * specification does not constrain this for interrupt transfers. That - * means that ehci_submit_async() would support interrupt transfers - * requiring several transactions only as long as the transfer size does - * not require more than a single qTD. - */ - if (length > usb_maxpacket(dev, pipe)) { - printf("%s: Interrupt transfers requiring several " - "transactions are not supported.\n", __func__); + queue = create_int_queue(dev, pipe, 1, length, buffer, interval); + if (!queue) return -1; - } - - queue = create_int_queue(dev, pipe, 1, length, buffer); timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); while ((backbuffer = poll_int_queue(dev, queue)) == NULL) @@ -1336,9 +1416,6 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, return -EINVAL; } - invalidate_dcache_range((uint32_t)buffer, - ALIGN_END_ADDR(char, buffer, length)); - ret = destroy_int_queue(dev, queue); if (ret < 0) return ret; diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c deleted file mode 100644 index 56ef7e6c13..0000000000 --- a/drivers/usb/host/ehci-ixp4xx.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2008, Michael Trimarchi - * - * Author: Michael Trimarchi - * This code is based on ehci freescale driver - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include - -#include "ehci.h" -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - *hccr = (struct ehci_hccr *)(0xcd000100); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - printf("IXP4XX init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index ee97fd2745..1a5fd6eefc 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -13,7 +13,7 @@ #include #if defined(CONFIG_KIRKWOOD) -#include +#include #elif defined(CONFIG_ORION5X) #include #endif @@ -74,7 +74,8 @@ static void usb_brg_adrdec_setup(void) * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { usb_brg_adrdec_setup(); diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c index bb6e7ac97f..b320c4a4e2 100644 --- a/drivers/usb/host/ehci-mpc512x.c +++ b/drivers/usb/host/ehci-mpc512x.c @@ -32,12 +32,13 @@ static void usb_platform_dr_init(volatile struct usb_ehci *ehci); * This code is derived from EHCI FSL USB Linux driver for MPC5121 * */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { volatile struct usb_ehci *ehci; /* Hook the memory mapped registers for EHCI-Controller */ - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; *hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength)); *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); @@ -81,7 +82,7 @@ int ehci_hcd_stop(int index) int exit_status = 0; /* Reset the USB controller */ - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; exit_status = reset_usb_controller(ehci); return exit_status; diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 3548620eca..838f23fee8 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -101,7 +101,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) else /* OC/USBPWR is not used */ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; else @@ -111,13 +111,13 @@ int mxc_set_usbcontrol(int port, unsigned int flags) MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_OTG_UCTRL_OPM_BIT; else v |= MXC_OTG_UCTRL_OPM_BIT; #endif -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) v |= MXC_OTG_UCTRL_O_PWR_POL_BIT; else @@ -127,7 +127,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) } break; case 1: /* Host 1 ULPI */ -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 /* The clock for the USBH1 ULPI port will come externally from the PHY. */ v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); @@ -136,13 +136,13 @@ int mxc_set_usbcontrol(int port, unsigned int flags) #endif v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ else v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ #endif -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) v |= MXC_H1_UCTRL_H1_PWR_POL_BIT; else @@ -164,13 +164,13 @@ int mxc_set_usbcontrol(int port, unsigned int flags) break; case 2: /* Host 2 ULPI */ v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); -#ifdef CONFIG_MX51 +#ifdef CONFIG_SOC_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ else v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ #endif -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) v |= MXC_H2_UCTRL_H2_OC_POL_BIT; else @@ -186,7 +186,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) #endif __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); break; -#ifdef CONFIG_MX53 +#ifdef CONFIG_SOC_MX53 case 3: /* Host 3 ULPI */ v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) @@ -218,24 +218,16 @@ void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) { } -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct usb_ehci *ehci; -#ifdef CONFIG_MX53 - struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR; - u32 reg; - - reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26); - /* derive USB PHY clock multiplexer from PLL3 */ - reg |= 1 << 26; - __raw_writel(reg, &sc_regs->cscmr1); -#endif set_usboh3_clk(); - enable_usboh3_clk(1); + enable_usboh3_clk(true); set_usb_phy_clk(); - enable_usb_phy1_clk(1); - enable_usb_phy2_clk(1); + enable_usb_phy1_clk(true); + enable_usb_phy2_clk(true); mdelay(1); /* Do board specific initialization */ diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index eb24af5974..154be8cb7c 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -35,66 +35,99 @@ #define USBPHY_CTRL_CLKGATE 0x40000000 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 +#define USBPHY_CTRL_OTG_ID 0x08000000 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 -#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 -#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 -#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 -#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 +#define ANADIG_USB_PLL_480_CTRL_BYPASS 0x00010000 +#define ANADIG_USB_PLL_480_CTRL_ENABLE 0x00002000 +#define ANADIG_USB_PLL_480_CTRL_POWER 0x00001000 +#define ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS 0x00000040 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ /* USBCMD */ -#define UH1_USBCMD_OFFSET 0x140 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ #define UCMD_RESET (1 << 1) /* controller reset */ -static void usbh1_internal_phy_clock_gate(int on) +static const unsigned phy_bases[] = { + USB_PHY0_BASE_ADDR, + USB_PHY1_BASE_ADDR, +}; + +static void usb_internal_phy_clock_gate(int index, int on) { - void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR; + void __iomem *phy_reg; + + if (index >= ARRAY_SIZE(phy_bases)) + return; + phy_reg = (void __iomem *)phy_bases[index]; phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg); } -static void usbh1_power_config(void) +static void usb_power_config(int index) { struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + void __iomem *chrg_detect; + void __iomem *pll_480_ctrl_clr; + void __iomem *pll_480_ctrl_set; + + switch (index) { + case 0: + chrg_detect = &anatop->usb1_chrg_detect; + pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; + pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; + break; + case 1: + chrg_detect = &anatop->usb2_chrg_detect; + pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; + pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; + break; + default: + return; + } /* - * Some phy and power's special controls for host1 + * Some phy and power's special controls * 1. The external charger detector needs to be disabled * or the signal at DP will be poor - * 2. The PLL's power and output to usb for host 1 + * 2. The PLL's power and output to usb * is totally controlled by IC, so the Software only needs * to enable them at initializtion. */ __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B | ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, - &anatop->usb2_chrg_detect); + chrg_detect); - __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, - &anatop->usb2_pll_480_ctrl_clr); + __raw_writel(ANADIG_USB_PLL_480_CTRL_BYPASS, + pll_480_ctrl_clr); - __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | - ANADIG_USB2_PLL_480_CTRL_POWER | - ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, - &anatop->usb2_pll_480_ctrl_set); + __raw_writel(ANADIG_USB_PLL_480_CTRL_ENABLE | + ANADIG_USB_PLL_480_CTRL_POWER | + ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS, + pll_480_ctrl_set); } -static int usbh1_phy_enable(void) +/* Return 0 : host node, <>0 : device mode */ +static int usb_phy_enable(int index, struct usb_ehci *ehci) { - void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR; - void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); - void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR + - USB_H1REGS_OFFSET + - UH1_USBCMD_OFFSET); + void __iomem *phy_reg; + void __iomem *phy_ctrl; + void __iomem *usb_cmd; u32 val; + if (index >= ARRAY_SIZE(phy_bases)) + return 0; + + phy_reg = (void __iomem *)phy_bases[index]; + phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); + usb_cmd = (void __iomem *)&ehci->usbcmd; + /* Stop then Reset */ val = __raw_readl(usb_cmd); val &= ~UCMD_RUN_STOP; @@ -123,31 +156,63 @@ static int usbh1_phy_enable(void) /* Power up the PHY */ __raw_writel(0, phy_reg + USBPHY_PWD); /* enable FS/LS device */ - val = __raw_readl(phy_reg + USBPHY_CTRL); + val = __raw_readl(phy_ctrl); val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3); - __raw_writel(val, phy_reg + USBPHY_CTRL); + __raw_writel(val, phy_ctrl); return 0; } -static void usbh1_oc_config(void) +/* Base address for this IP block is 0x02184800 */ +struct usbnc_regs { + u32 ctrl[4]; /* otg/host1-3 */ + u32 uh2_hsic_ctrl; + u32 uh3_hsic_ctrl; + u32 otg_phy_ctrl_0; + u32 uh1_phy_ctrl_0; +}; + +static void usb_oc_config(int index) { - void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR; - void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET; + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + USB_OTHERREGS_OFFSET); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); u32 val; - val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET); + val = __raw_readl(ctrl); #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 /* mx6qarm2 seems to required a different setting*/ val &= ~UCTRL_OVER_CUR_POL; #else val |= UCTRL_OVER_CUR_POL; #endif - __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET); + __raw_writel(val, ctrl); - val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET); + val = __raw_readl(ctrl); val |= UCTRL_OVER_CUR_DIS; - __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET); + __raw_writel(val, ctrl); +} + +int usb_phy_mode(int port) +{ + void __iomem *phy_reg; + void __iomem *phy_ctrl; + u32 val; + + phy_reg = (void __iomem *)phy_bases[port]; + phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); + + val = __raw_readl(phy_ctrl); + + if (val & USBPHY_CTRL_OTG_ID) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; +} + +int __weak board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); } int __weak board_ehci_hcd_init(int port) @@ -155,33 +220,43 @@ int __weak board_ehci_hcd_init(int port) return 0; } -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int __weak board_ehci_power(int port, int on) { - struct usb_ehci *ehci; + return 0; +} +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + enum usb_init_type type; + struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + + (0x200 * index)); + + if (index > 3) + return -EINVAL; enable_usboh3_clk(1); mdelay(1); /* Do board specific initialization */ - board_ehci_hcd_init(CONFIG_MXC_USB_PORT); - -#if CONFIG_MXC_USB_PORT == 1 - /* USB Host 1 */ - usbh1_power_config(); - usbh1_oc_config(); - usbh1_internal_phy_clock_gate(1); - usbh1_phy_enable(); -#else -#error "MXC USB port not yet supported" -#endif + board_ehci_hcd_init(index); + + usb_power_config(index); + usb_oc_config(index); + usb_internal_phy_clock_gate(index, 1); + usb_phy_enable(index, ehci); + type = board_usb_phy_mode(index); - ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR + - (0x200 * CONFIG_MXC_USB_PORT)); *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - setbits_le32(&ehci->usbmode, CM_HOST); + if ((type == init) || (type == USB_INIT_DEVICE)) + board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); + if (type != init) + return -ENODEV; + if (type == USB_INIT_DEVICE) + return 0; + setbits_le32(&ehci->usbmode, CM_HOST); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index a3048d105a..ded991fa34 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -67,7 +67,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) unsigned int v; v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); -#if defined(CONFIG_MX25) +#if defined(CONFIG_SOC_MX25) switch (port) { case 0: /* OTG port */ v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | @@ -116,7 +116,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) default: return -EINVAL; } -#elif defined(CONFIG_MX31) +#elif defined(CONFIG_SOC_MX31) switch (port) { case 0: /* OTG port */ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); @@ -151,7 +151,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) default: return -EINVAL; } -#elif defined(CONFIG_MX35) +#elif defined(CONFIG_SOC_MX35) switch (port) { case 0: /* OTG port */ v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | @@ -208,10 +208,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) return 0; } -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct usb_ehci *ehci; -#ifdef CONFIG_MX31 +#ifdef CONFIG_SOC_MX31 struct clock_control_regs *sc_regs = (struct clock_control_regs *)CCM_BASE; @@ -229,7 +230,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) setbits_le32(&ehci->usbmode, CM_HOST); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); -#ifdef CONFIG_MX35 +#ifdef CONFIG_SOC_MX35 /* Workaround for ENGcm11601 */ __raw_writel(0, &ehci->sbuscfg); #endif diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 286a380de2..6b8d969bb0 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -77,7 +77,18 @@ static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable) return 0; } -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int __weak board_ehci_hcd_init(int port) +{ + return 0; +} + +int __weak board_ehci_hcd_exit(int port) +{ + return 0; +} + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { int ret; @@ -89,6 +100,10 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) return -EINVAL; } + ret = board_ehci_hcd_init(index); + if (ret) + return ret; + port = &mxs_port[index]; /* Reset the PHY block */ @@ -153,5 +168,7 @@ int ehci_hcd_stop(int index) /* Disable USB clock */ ret = ehci_mxs_toggle_clock(port, 0); + board_ehci_hcd_exit(index); + return ret; } diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 032d5e5ec2..1b215c25f6 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -28,21 +28,48 @@ static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE; static int omap_uhh_reset(void) { -/* - * Soft resetting the UHH module causes instability issues on - * all OMAPs so we just avoid it. - * - * See OMAP36xx Errata - * i571: USB host EHCI may stall when entering smart-standby mode - * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * - * On OMAP4/5, soft-resetting the UHH module will put it into - * Smart-Idle mode and lead to a deadlock. - * - * On OMAP3, this doesn't seem to be the case but still instabilities - * are observed on beagle (3530 ES1.0) if soft-reset is used. - * e.g. NFS root failures with Linux kernel. - */ + int timeout = 0; + u32 rev; + + rev = readl(&uhh->rev); + + /* Soft RESET */ + writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc); + + switch (rev) { + case OMAP_USBHS_REV1: + /* Wait for soft RESET to complete */ + while (!(readl(&uhh->syss) & 0x1)) { + if (timeout > 100) { + printf("%s: RESET timeout\n", __func__); + return -1; + } + udelay(10); + timeout++; + } + + /* Set No-Idle, No-Standby */ + writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); + break; + + default: /* Rev. 2 onwards */ + + udelay(2); /* Need to wait before accessing SYSCONFIG back */ + + /* Wait for soft RESET to complete */ + while ((readl(&uhh->sysc) & 0x1)) { + if (timeout > 100) { + printf("%s: RESET timeout\n", __func__); + return -1; + } + udelay(10); + timeout++; + } + + writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); + break; + } + return 0; } @@ -79,6 +106,7 @@ static void omap_usbhs_hsic_init(int port) writel(reg, &usbtll->channel_conf + port); } +#ifdef CONFIG_USB_ULPI static void omap_ehci_soft_phy_reset(int port) { struct ulpi_viewport ulpi_vp; @@ -88,15 +116,16 @@ static void omap_ehci_soft_phy_reset(int port) ulpi_reset(&ulpi_vp); } - -inline int __board_usb_init(void) +#else +static void omap_ehci_soft_phy_reset(int port) { - return 0; + return; } -int board_usb_init(void) __attribute__((weak, alias("__board_usb_init"))); +#endif #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \ - defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) + defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \ + defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO) /* controls PHY(s) reset signal(s) */ static inline void omap_ehci_phy_reset(int on, int delay) { @@ -115,6 +144,10 @@ static inline void omap_ehci_phy_reset(int on, int delay) gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset"); gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on); #endif +#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO + gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset"); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on); +#endif /* Hold the PHY in RESET for enough time till DIR is high */ /* Refer: ISSUE1 */ @@ -145,15 +178,15 @@ int omap_ehci_hcd_stop(void) * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1 * See there for additional Copyrights. */ -int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { int ret; unsigned int i, reg = 0, rev = 0; debug("Initializing OMAP EHCI\n"); - ret = board_usb_init(); + ret = board_usb_init(index, USB_INIT_HOST); if (ret < 0) return ret; @@ -198,10 +231,27 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, else setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); } else if (rev == OMAP_USBHS_REV2) { + clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR), OMAP4_UHH_HOSTCONFIG_APP_START_CLK); - /* Clear port mode fields for PHY mode*/ + /* Clear port mode fields for PHY mode */ + + if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) + setbits_le32(®, OMAP_P1_MODE_HSIC); + + if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) + setbits_le32(®, OMAP_P2_MODE_HSIC); + + } else if (rev == OMAP_USBHS_REV2_1) { + + clrsetbits_le32(®, + (OMAP_P1_MODE_CLEAR | + OMAP_P2_MODE_CLEAR | + OMAP_P3_MODE_CLEAR), + OMAP4_UHH_HOSTCONFIG_APP_START_CLK); + + /* Clear port mode fields for PHY mode */ if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) setbits_le32(®, OMAP_P1_MODE_HSIC); diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 90d7a6feb5..991b19998b 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -54,9 +54,31 @@ static pci_dev_t ehci_find_class(int index) bdf += PCI_BDF(0, 0, 1)) { pci_read_config_dword(bdf, PCI_CLASS_REVISION, &class); - if ((class >> 8 == PCI_CLASS_SERIAL_USB_EHCI) - && !index--) - return bdf; + class >>= 8; + /* + * Here be dragons! In case we have multiple + * PCI EHCI controllers, this function will + * be called multiple times as well. This + * function will scan the PCI busses, always + * starting from bus 0, device 0, function 0, + * until it finds an USB controller. The USB + * stack gives us an 'index' of a controller + * that is currently being registered, which + * is a number, starting from 0 and growing + * in ascending order as controllers are added. + * To avoid probing the same controller in tne + * subsequent runs of this function, we will + * skip 'index - 1' detected controllers and + * report the index'th controller. + */ + if (class != PCI_CLASS_SERIAL_USB_EHCI) + continue; + if (index) { + index--; + continue; + } + /* Return index'th controller. */ + return bdf; } } } @@ -69,8 +91,8 @@ static pci_dev_t ehci_find_class(int index) * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr, - struct ehci_hcor **ret_hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor) { pci_dev_t pdev; uint32_t cmd; diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c index 462fcfbe4f..9aee3ff786 100644 --- a/drivers/usb/host/ehci-ppc4xx.c +++ b/drivers/usb/host/ehci-ppc4xx.c @@ -15,7 +15,8 @@ * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { *hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR); *hcor = (struct ehci_hcor *)((uint32_t) *hccr + diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c new file mode 100644 index 0000000000..7fe79efc17 --- /dev/null +++ b/drivers/usb/host/ehci-rmobile.c @@ -0,0 +1,129 @@ +/* + * EHCI HCD (Host Controller Driver) for USB. + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2014 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include "ehci.h" + +#if defined(CONFIG_R8A7740) +static u32 usb_base_address[] = { + 0xC6700000 +}; +#elif defined(CONFIG_R8A7790) +static u32 usb_base_address[] = { + 0xEE080000, /* USB0 (EHCI) */ + 0xEE0A0000, /* USB1 */ + 0xEE0C0000, /* USB2 */ +}; +#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ + defined(CONFIG_R8A7794) +static u32 usb_base_address[] = { + 0xEE080000, /* USB0 (EHCI) */ + 0xEE0C0000, /* USB1 */ +}; +#else +#error rmobile EHCI USB driver not supported on this platform +#endif + +int ehci_hcd_stop(int index) +{ + int i; + u32 base; + struct ahbcom_pci_bridge *ahbcom_pci; + + base = usb_base_address[index]; + ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); + writel(0, &ahbcom_pci->ahb_bus_ctr); + + /* reset ehci */ + setbits_le32(base + EHCI_USBCMD, CMD_RESET); + for (i = 100; i > 0; i--) { + if (!(readl(base + EHCI_USBCMD) & CMD_RESET)) + break; + udelay(100); + } + + if (!i) + printf("error : ehci(%d) reset failed.\n", index); + + if (index == (ARRAY_SIZE(usb_base_address) - 1)) + setbits_le32(SMSTPCR7, SMSTPCR703); + + return 0; +} + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + u32 base; + u32 phys_base; + struct rmobile_ehci_reg *rehci; + struct ahbcom_pci_bridge *ahbcom_pci; + struct ahbconf_pci_bridge *ahbconf_pci; + struct ahb_pciconf *ahb_pciconf_ohci; + struct ahb_pciconf *ahb_pciconf_ehci; + uint32_t cap_base; + + base = usb_base_address[index]; + phys_base = base; + if (index == 0) + clrbits_le32(SMSTPCR7, SMSTPCR703); + + rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET); + ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); + ahbconf_pci = + (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET); + ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET); + ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET); + + /* Clock & Reset & Direct Power Down */ + clrsetbits_le32(&ahbcom_pci->usbctr, + (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB); + clrbits_le32(&ahbcom_pci->usbctr, PLL_RST); + + /* AHB-PCI Bridge Communication Registers */ + writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); + writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, + &ahbcom_pci->pciahb_win1_ctr); + writel(0xf0000000 | PCIAHB_WIN_PREFETCH, + &ahbcom_pci->pciahb_win2_ctr); + writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr); + + setbits_le32(&ahbcom_pci->pci_arbiter_ctr, + PCIBP_MODE | PCIREQ1 | PCIREQ0); + + /* PCI Configuration Registers for AHBPCI */ + writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, + &ahbcom_pci->ahbpci_win1_ctr); + writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); + writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); + writel(0xf0000000, &ahbconf_pci->win2_basead); + writel(SERREN | PERREN | MASTEREN | MEMEN, + &ahbconf_pci->cmnd_sts); + + /* PCI Configuration Registers for EHCI */ + writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr); + writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead); + writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead); + writel(SERREN | PERREN | MASTEREN | MEMEN, + &ahb_pciconf_ohci->cmnd_sts); + writel(SERREN | PERREN | MASTEREN | MEMEN, + &ahb_pciconf_ehci->cmnd_sts); + + /* Enable PCI interrupt */ + setbits_le32(&ahbcom_pci->pci_int_enable, + USBH_PMEEN | USBH_INTBEN | USBH_INTAEN); + + *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion); + cap_base = ehci_readl(&(*hccr)->cr_capbase); + *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base)); + + return 0; +} diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c index 6758316f7f..210ee9e88e 100644 --- a/drivers/usb/host/ehci-spear.c +++ b/drivers/usb/host/ehci-spear.c @@ -20,7 +20,8 @@ * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { *hccr = (struct ehci_hccr *)(CONFIG_SYS_UHC0_EHCI_BASE + 0x100); *hcor = (struct ehci_hcor *)((uint32_t)*hccr diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c new file mode 100644 index 0000000000..eda9f698d9 --- /dev/null +++ b/drivers/usb/host/ehci-sunxi.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2014 Roman Byshko + * + * Roman Byshko + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "ehci.h" + +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + int err; + + err = sunxi_usbc_request_resources(index + 1); + if (err) + return err; + + sunxi_usbc_enable(index + 1); + sunxi_usbc_vbus_enable(index + 1); + + *hccr = sunxi_usbc_get_io_base(index + 1); + + *hcor = (struct ehci_hcor *)((uint32_t) *hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)*hccr, (uint32_t)*hcor, + (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + return 0; +} + +int ehci_hcd_stop(int index) +{ + sunxi_usbc_vbus_disable(index + 1); + sunxi_usbc_disable(index + 1); + + return sunxi_usbc_free_resources(index + 1); +} diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index c6da449e4b..b5ad1e35e5 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -70,10 +69,11 @@ struct fdt_usb { unsigned enabled:1; /* 1 to enable, 0 to disable */ unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ unsigned initialized:1; /* has this port already been initialized? */ + enum usb_init_type init_type; enum dr_mode dr_mode; /* dual role mode */ enum periph_id periph_id;/* peripheral id */ - struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ - struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */ + struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ + struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ }; static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ @@ -238,29 +238,28 @@ int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) return PORTSC_PSPD(reg); } -/* Put the port into host mode */ -static void set_host_mode(struct fdt_usb *config) +/* Set up VBUS for host/device mode */ +static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) { /* - * If we are an OTG port, check if remote host is driving VBus and - * bail out in this case. + * If we are an OTG port initializing in host mode, + * check if remote host is driving VBus and bail out in this case. */ - if (config->dr_mode == DR_MODE_OTG && - (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) + if (init == USB_INIT_HOST && + config->dr_mode == DR_MODE_OTG && + (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { + printf("tegrausb: VBUS input active; not enabling as host\n"); return; + } - /* - * If not driving, we set the GPIO to enable VBUS. We assume - * that the pinmux is set up correctly for this. - */ - if (fdt_gpio_isvalid(&config->vbus_gpio)) { - fdtdec_setup_gpio(&config->vbus_gpio); - gpio_direction_output(config->vbus_gpio.gpio, - (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? - 0 : 1); - debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, - (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? - "low" : "high"); + if (dm_gpio_is_valid(&config->vbus_gpio)) { + int vbus_value; + + vbus_value = (init == USB_INIT_HOST); + dm_gpio_set_value(&config->vbus_gpio, vbus_value); + + debug("set_up_vbus: GPIO %d %d\n", + gpio_get_number(&config->vbus_gpio), vbus_value); } } @@ -294,10 +293,44 @@ static const unsigned *get_pll_timing(void) return timing; } +/* select the PHY to use with a USB controller */ +static void init_phy_mux(struct fdt_usb *config, uint pts, + enum usb_init_type init) +{ + struct usb_ctlr *usbctlr = config->reg; + +#if defined(CONFIG_TEGRA20) + if (config->periph_id == PERIPH_ID_USBD) { + clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, + pts << PTS1_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS1); + } else { + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + pts << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + } +#else + /* Set to Host mode (if applicable) after Controller Reset was done */ + clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, + (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); + /* + * Select PHY interface after setting host mode. + * For device mode, the ordering requirement is not an issue, since + * only the first USB controller supports device mode, and that USB + * controller can only talk to a UTMI PHY, so the PHY selection is + * already made at reset time, so this write is a no-op. + */ + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, + pts << PTS_SHIFT); + clrbits_le32(&usbctlr->hostpc1_devlc, STS); +#endif +} + /* set up the UTMI USB controller with the parameters provided */ -static int init_utmi_usb_controller(struct fdt_usb *config) +static int init_utmi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { - u32 val; + u32 b_sess_valid_mask, val; int loop_count; const unsigned *timing; struct usb_ctlr *usbctlr = config->reg; @@ -315,12 +348,16 @@ static int init_utmi_usb_controller(struct fdt_usb *config) /* Follow the crystal clock disable by >100ns delay */ udelay(1); + b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); + clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, + (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); + /* * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP * mux must be switched to actually use a_sess_vld threshold. */ if (config->dr_mode == DR_MODE_OTG && - fdt_gpio_isvalid(&config->vbus_gpio)) + dm_gpio_is_valid(&config->vbus_gpio)) clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, VBUS_SENSE_CTL_MASK, VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); @@ -461,6 +498,9 @@ static int init_utmi_usb_controller(struct fdt_usb *config) if (config->periph_id == PERIPH_ID_USBD) clrbits_le32(&clkrst->crc_utmip_pll_cfg2, UTMIP_FORCE_PD_SAMP_A_POWERDOWN); + if (config->periph_id == PERIPH_ID_USB2) + clrbits_le32(&clkrst->crc_utmip_pll_cfg2, + UTMIP_FORCE_PD_SAMP_B_POWERDOWN); if (config->periph_id == PERIPH_ID_USB3) clrbits_le32(&clkrst->crc_utmip_pll_cfg2, UTMIP_FORCE_PD_SAMP_C_POWERDOWN); @@ -483,9 +523,7 @@ static int init_utmi_usb_controller(struct fdt_usb *config) clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); /* Select UTMI parallel interface */ - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32(&usbctlr->port_sc1, STS); + init_phy_mux(config, PTS_UTMI, init); /* Deassert power down state */ clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | @@ -515,7 +553,8 @@ static int init_utmi_usb_controller(struct fdt_usb *config) #endif /* set up the ULPI USB controller with the parameters provided */ -static int init_ulpi_usb_controller(struct fdt_usb *config) +static int init_ulpi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { u32 val; int loop_count; @@ -527,11 +566,10 @@ static int init_ulpi_usb_controller(struct fdt_usb *config) clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); /* reset ULPI phy */ - if (fdt_gpio_isvalid(&config->phy_reset_gpio)) { - fdtdec_setup_gpio(&config->phy_reset_gpio); - gpio_direction_output(config->phy_reset_gpio.gpio, 0); + if (dm_gpio_is_valid(&config->phy_reset_gpio)) { + dm_gpio_set_value(&config->phy_reset_gpio, 0); mdelay(5); - gpio_set_value(config->phy_reset_gpio.gpio, 1); + dm_gpio_set_value(&config->phy_reset_gpio, 1); } /* Reset the usb controller */ @@ -543,7 +581,7 @@ static int init_ulpi_usb_controller(struct fdt_usb *config) ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); /* Select ULPI parallel interface */ - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); + init_phy_mux(config, PTS_ULPI, init); /* enable ULPI transceiver */ setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); @@ -592,7 +630,8 @@ static int init_ulpi_usb_controller(struct fdt_usb *config) return 0; } #else -static int init_ulpi_usb_controller(struct fdt_usb *config) +static int init_ulpi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { printf("No code to set up ULPI controller, please enable" "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); @@ -642,14 +681,16 @@ static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) debug("%s: Missing/invalid peripheral ID\n", __func__); return -FDT_ERR_NOTFOUND; } - fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); - fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio", - &config->phy_reset_gpio); + gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, + &config->vbus_gpio, GPIOD_IS_OUT); + gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, + &config->phy_reset_gpio, GPIOD_IS_OUT); debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " "vbus=%d, phy_reset=%d, dr_mode=%d\n", config->enabled, config->has_legacy_mode, config->utmi, - config->ulpi, config->periph_id, config->vbus_gpio.gpio, - config->phy_reset_gpio.gpio, config->dr_mode); + config->ulpi, config->periph_id, + gpio_get_number(&config->vbus_gpio), + gpio_get_number(&config->phy_reset_gpio), config->dr_mode); return 0; } @@ -699,7 +740,7 @@ static int process_usb_nodes(const void *blob, int node_list[], int count) return 0; } -int board_usb_init(const void *blob) +int usb_process_devicetree(const void *blob) { int node_list[USB_PORTS_MAX]; int count, err = 0; @@ -734,7 +775,8 @@ int board_usb_init(const void *blob) * @param hcor returns start address of EHCI HCOR registers * @return 0 if ok, -1 on error (generally invalid port number) */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct fdt_usb *config; struct usb_ctlr *usbctlr; @@ -744,42 +786,66 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) config = &port[index]; + switch (init) { + case USB_INIT_HOST: + switch (config->dr_mode) { + case DR_MODE_HOST: + case DR_MODE_OTG: + break; + default: + printf("tegrausb: Invalid dr_mode %d for host mode\n", + config->dr_mode); + return -1; + } + break; + case USB_INIT_DEVICE: + if (config->periph_id != PERIPH_ID_USBD) { + printf("tegrausb: Device mode only supported on first USB controller\n"); + return -1; + } + if (!config->utmi) { + printf("tegrausb: Device mode only supported with UTMI PHY\n"); + return -1; + } + switch (config->dr_mode) { + case DR_MODE_DEVICE: + case DR_MODE_OTG: + break; + default: + printf("tegrausb: Invalid dr_mode %d for device mode\n", + config->dr_mode); + return -1; + } + break; + default: + printf("tegrausb: Unknown USB_INIT_* %d\n", init); + return -1; + } + /* skip init, if the port is already initialized */ - if (config->initialized) + if (config->initialized && config->init_type == init) goto success; - if (config->utmi && init_utmi_usb_controller(config)) { + if (config->utmi && init_utmi_usb_controller(config, init)) { printf("tegrausb: Cannot init port %d\n", index); return -1; } - if (config->ulpi && init_ulpi_usb_controller(config)) { + if (config->ulpi && init_ulpi_usb_controller(config, init)) { printf("tegrausb: Cannot init port %d\n", index); return -1; } - set_host_mode(config); + set_up_vbus(config, init); config->initialized = 1; + config->init_type = init; success: usbctlr = config->reg; *hccr = (struct ehci_hccr *)&usbctlr->cap_length; *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; - if (controller->has_hostpc) { - /* Set to Host mode after Controller Reset was done */ - clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, - USBMODE_CM_HC); - /* Select UTMI parallel interface after setting host mode */ - if (config->utmi) { - clrsetbits_le32((char *)&usbctlr->usb_cmd + - HOSTPC1_DEVLC, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32((char *)&usbctlr->usb_cmd + - HOSTPC1_DEVLC, STS); - } - } return 0; } diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c new file mode 100644 index 0000000000..32a4375279 --- /dev/null +++ b/drivers/usb/host/ehci-uniphier.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "ehci.h" + +#ifdef CONFIG_OF_CONTROL +#include +DECLARE_GLOBAL_DATA_PTR; + +#define FDT gd->fdt_blob +#define COMPAT "panasonic,uniphier-ehci" + +static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) +{ + int offset; + + for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT); + offset >= 0; + offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) { + if (index == 0) { + *base = (struct ehci_hccr *) + fdtdec_get_addr(FDT, offset, "reg"); + return 0; + } + index--; + } + + return -ENODEV; /* not found */ +} +#else +static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) +{ + *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base; + return 0; +} +#endif + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + int ret; + struct ehci_hccr *cr; + struct ehci_hcor *or; + + uniphier_ehci_reset(index, 0); + + ret = get_uniphier_ehci_base(index, &cr); + if (ret < 0) + return ret; + or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase)); + + *hccr = cr; + *hcor = or; + + return 0; +} + +int ehci_hcd_stop(int index) +{ + uniphier_ehci_reset(index, 1); + + return 0; +} diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c index 4252c272cf..512ad3fb78 100644 --- a/drivers/usb/host/ehci-vct.c +++ b/drivers/usb/host/ehci-vct.c @@ -15,7 +15,8 @@ int vct_ehci_hcd_init(u32 *hccr, u32 *hcor); * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { int ret; u32 vct_hccr; diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c new file mode 100644 index 0000000000..7770d05646 --- /dev/null +++ b/drivers/usb/host/ehci-zynq.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2014, Xilinx, Inc + * + * USB Low level initialization(Specific to zynq) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ehci.h" + +#define ZYNQ_USB_USBCMD_RST 0x0000002 +#define ZYNQ_USB_USBCMD_STOP 0x0000000 +#define ZYNQ_USB_NUM_MIO 12 + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + struct usb_ehci *ehci; + struct ulpi_viewport ulpi_vp; + int ret, mio_usb; + /* Used for writing the ULPI data address */ + struct ulpi_regs *ulpi = (struct ulpi_regs *)0; + + if (!index) { + mio_usb = zynq_slcr_get_mio_pin_status("usb0"); + if (mio_usb != ZYNQ_USB_NUM_MIO) { + printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb, + index); + return -1; + } + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; + } else { + mio_usb = zynq_slcr_get_mio_pin_status("usb1"); + if (mio_usb != ZYNQ_USB_NUM_MIO) { + printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb, + index); + return -1; + } + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + } + + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uint32_t) *hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; + ulpi_vp.port_num = 0; + + ret = ulpi_init(&ulpi_vp); + if (ret) { + puts("zynq ULPI viewport init failed\n"); + return -1; + } + + /* ULPI set flags */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl, + ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN | + ULPI_OTG_EXTVBUSIND); + ulpi_write(&ulpi_vp, &ulpi->function_ctrl, + ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL | + ULPI_FC_SUSPENDM); + ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0); + + /* Set VBus */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(int index) +{ + struct usb_ehci *ehci; + + if (!index) + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; + else + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + + /* Stop controller */ + writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd); + udelay(1000); + + /* Initiate controller reset */ + writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd); + + return 0; +} diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index bd52afe262..79aecd414e 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -28,22 +28,6 @@ #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 #endif -/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */ -#define DeviceRequest \ - ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) - -#define DeviceOutRequest \ - ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) - -#define InterfaceRequest \ - ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) - -#define EndpointRequest \ - ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) - -#define EndpointOutRequest \ - ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) - /* * Register Space. */ @@ -63,9 +47,9 @@ struct ehci_hcor { uint32_t or_usbcmd; #define CMD_PARK (1 << 11) /* enable "park" */ #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ -#define CMD_ASE (1 << 5) /* async schedule enable */ #define CMD_LRESET (1 << 7) /* partial reset */ -#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */ +#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */ +#define CMD_ASE (1 << 5) /* async schedule enable */ #define CMD_PSE (1 << 4) /* periodic schedule enable */ #define CMD_RESET (1 << 1) /* reset HC not bus */ #define CMD_RUN (1 << 0) /* start/stop HC */ @@ -262,11 +246,13 @@ struct ehci_ctrl { struct QH qh_list __aligned(USB_DMA_MINALIGN); struct QH periodic_queue __aligned(USB_DMA_MINALIGN); uint32_t *periodic_list; + int periodic_schedules; int ntds; }; /* Low level init functions */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor); +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor); int ehci_hcd_stop(int index); #endif /* USB_EHCI_H */ diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c index 934550ad88..0556f328e4 100644 --- a/drivers/usb/host/isp116x-hcd.c +++ b/drivers/usb/host/isp116x-hcd.c @@ -103,12 +103,6 @@ static int rh_devnum; /* address of Root Hub endpoint */ /* ------------------------------------------------------------------------- */ -#define ALIGN(x,a) (((x)+(a)-1UL)&~((a)-1UL)) -#define min_t(type,x,y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) - -/* ------------------------------------------------------------------------- */ - static int isp116x_reset(struct isp116x *isp116x); /* --- Debugging functions ------------------------------------------------- */ @@ -254,105 +248,7 @@ static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type) /* --- Virtual Root Hub ---------------------------------------------------- */ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x02, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = { - 0x22, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'S', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'P', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '1', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '1', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '6', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'x', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* * Hub class-specific descriptor is constructed dynamically @@ -1377,7 +1273,7 @@ int isp116x_check_id(struct isp116x *isp116x) return 0; } -int usb_lowlevel_init(int index, void **controller)) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)) { struct isp116x *isp116x = &isp116x_dev; diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 9e90d59087..820e2e56ef 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -18,15 +18,15 @@ int usb_cpu_init(void) { at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ - defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ - defined(CONFIG_AT91SAM9261) +#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB /* Enable PLLB */ writel(get_pllb_init(), &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ - defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3) +#ifdef CONFIG_AT91SAM9N12 + writel(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2, &pmc->usb); +#endif +#elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL) /* Enable UPLL */ writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); @@ -38,8 +38,8 @@ int usb_cpu_init(void) #endif /* Enable USB host clock. */ -#ifdef CONFIG_SAMA5D3 - writel(1 << (ATMEL_ID_UHP - 32), &pmc->pcer1); +#ifdef CPU_HAS_PCR + at91_periph_clk_enable(ATMEL_ID_UHP); #else writel(1 << ATMEL_ID_UHP, &pmc->pcer); #endif @@ -58,8 +58,8 @@ int usb_cpu_stop(void) at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; /* Disable USB host clock. */ -#ifdef CONFIG_SAMA5D3 - writel(1 << (ATMEL_ID_UHP - 32), &pmc->pcdr1); +#ifdef CPU_HAS_PCR + at91_periph_clk_disable(ATMEL_ID_UHP); #else writel(1 << ATMEL_ID_UHP, &pmc->pcdr); #endif @@ -70,14 +70,15 @@ int usb_cpu_stop(void) writel(ATMEL_PMC_UHP, &pmc->scdr); #endif -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ - defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) +#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB +#ifdef CONFIG_AT91SAM9N12 + writel(0, &pmc->usb); +#endif /* Disable PLLB */ writel(0, &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ - defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3) +#elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL) /* Disable UPLL */ writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr); while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) diff --git a/drivers/usb/host/ohci-ep93xx.c b/drivers/usb/host/ohci-ep93xx.c new file mode 100644 index 0000000000..8fb4ababec --- /dev/null +++ b/drivers/usb/host/ohci-ep93xx.c @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2013 + * Sergey Kostanbaev < sergey.kostanbaev fairwaves.ru > + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) +#include +#include + +int usb_cpu_init(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + unsigned long pwr = readl(&syscon->pwrcnt); + writel(pwr | SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt); + + return 0; +} + +int usb_cpu_stop(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + unsigned long pwr = readl(&syscon->pwrcnt); + writel(pwr & ~SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt); + + return 0; +} + +int usb_cpu_init_fail(void) +{ + return usb_cpu_stop(); +} + +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index c33c487ee5..97a7edeb53 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -47,7 +47,7 @@ #include /* needed for AT91_USB_HOST_BASE */ #endif -#if defined(CONFIG_ARM920T) || \ +#if defined(CONFIG_CPU_ARM920T) || \ defined(CONFIG_S3C24X0) || \ defined(CONFIG_440EP) || \ defined(CONFIG_PCI_OHCI) || \ @@ -65,9 +65,6 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ @@ -1094,103 +1091,7 @@ static int dl_done_list(ohci_t *ohci) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ @@ -1548,7 +1449,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } dev->status = stat; - dev->act_len = transfer_len; + dev->act_len = urb->actual_length; #ifdef DEBUG pkt_print(urb, dev, pipe, buffer, transfer_len, @@ -1847,7 +1748,7 @@ static void hc_release_ohci(ohci_t *ohci) */ static char ohci_inited = 0; -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { #ifdef CONFIG_PCI_OHCI pci_dev_t pdev; @@ -1861,7 +1762,7 @@ int usb_lowlevel_init(int index, void **controller) #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT /* board dependant init */ - if (usb_board_init()) + if (board_usb_init(index, USB_INIT_HOST)) return -1; #endif memset(&gohci, 0, sizeof(ohci_t)); @@ -1918,7 +1819,7 @@ int usb_lowlevel_init(int index, void **controller) err ("can't reset usb-%s", gohci.slot_name); #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT /* board dependant cleanup */ - usb_board_init_fail(); + board_usb_cleanup(index, USB_INIT_HOST); #endif #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c index 879ac16624..8bb2275c09 100644 --- a/drivers/usb/host/ohci-s3c24xx.c +++ b/drivers/usb/host/ohci-s3c24xx.c @@ -35,9 +35,6 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) - #undef DEBUG #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) @@ -873,100 +870,7 @@ static int dl_done_list(struct ohci *ohci, struct td *td_list) * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, - 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = { - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include /* Hub class-specific descriptor is constructed dynamically */ @@ -1642,7 +1546,7 @@ static void hc_release_ohci(struct ohci *ohci) */ static char ohci_inited = 0; -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index d977e8ff3c..9a4a2c2475 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -19,14 +19,11 @@ #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ /* functions for doing board or CPU specific setup/cleanup */ -extern int usb_board_init(void); -extern int usb_board_stop(void); -extern int usb_board_init_fail(void); - -extern int usb_cpu_init(void); -extern int usb_cpu_stop(void); -extern int usb_cpu_init_fail(void); +int usb_board_stop(void); +int usb_cpu_init(void); +int usb_cpu_stop(void); +int usb_cpu_init_fail(void); static int cc_to_error[16] = { diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index b503b356ce..6f33456c90 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -164,8 +164,8 @@ static int enable_controller(struct r8a66597 *r8a66597) r8a66597_bset(r8a66597, INTL, SOFCFG); r8a66597_write(r8a66597, 0, INTENB0); - r8a66597_write(r8a66597, 0, INTENB1); - r8a66597_write(r8a66597, 0, INTENB2); + for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) + r8a66597_write(r8a66597, 0, get_intenb_reg(port)); r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, CFIFOSEL); r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, D0FIFOSEL); @@ -550,116 +550,11 @@ static int check_usb_device_connecting(struct r8a66597 *r8a66597) return -1; /* fail */ } -/* based on usb_ohci.c */ -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) /*-------------------------------------------------------------------------* * Virtual Root Hub *-------------------------------------------------------------------------*/ -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; */ - - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 34, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '8', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'A', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '6', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '6', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '5', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '9', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - '7', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; +#include static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, struct devrequest *cmd) @@ -903,13 +798,13 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, return 0; } -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { struct r8a66597 *r8a66597 = &gr8a66597; R8A66597_DPRINT("%s\n", __func__); - memset(r8a66597, 0, sizeof(r8a66597)); + memset(r8a66597, 0, sizeof(*r8a66597)); r8a66597->reg = CONFIG_R8A66597_BASE_ADDR; disable_controller(r8a66597); diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c index cead25dc5e..b29c67e189 100644 --- a/drivers/usb/host/sl811-hcd.c +++ b/drivers/usb/host/sl811-hcd.c @@ -16,7 +16,7 @@ * 2.Original SL811 driver (hc_sl811.o) by Pei Liu * 3.Rewrited as sl811.o by Yin Aihua * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -194,7 +194,7 @@ static int sl811_hc_reset(void) return 1; } -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { root_hub_devnum = 0; sl811_hc_reset(); diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c new file mode 100644 index 0000000000..a77c8bc919 --- /dev/null +++ b/drivers/usb/host/xhci-exynos5.c @@ -0,0 +1,328 @@ +/* + * SAMSUNG EXYNOS5 USB HOST XHCI Controller + * + * Copyright (C) 2012 Samsung Electronics Co.Ltd + * Vivek Gautam + * Vikas Sajjan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file is a conglomeration for DWC3-init sequence and further + * exynos5 specific PHY-init sequence. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xhci.h" + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +/** + * Contains pointers to register base addresses + * for the usb controller. + */ +struct exynos_xhci { + struct exynos_usb3_phy *usb3_phy; + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; + struct gpio_desc vbus_gpio; +}; + +static struct exynos_xhci exynos; + +#ifdef CONFIG_OF_CONTROL +static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos) +{ + fdt_addr_t addr; + unsigned int node; + int depth; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI); + if (node <= 0) { + debug("XHCI: Can't get device node for xhci\n"); + return -ENODEV; + } + + /* + * Get the base address for XHCI controller from the device node + */ + addr = fdtdec_get_addr(blob, node, "reg"); + if (addr == FDT_ADDR_T_NONE) { + debug("Can't get the XHCI register base address\n"); + return -ENXIO; + } + exynos->hcd = (struct xhci_hccr *)addr; + + /* Vbus gpio */ + gpio_request_by_name_nodev(blob, node, "samsung,vbus-gpio", 0, + &exynos->vbus_gpio, GPIOD_IS_OUT); + + depth = 0; + node = fdtdec_next_compatible_subnode(blob, node, + COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth); + if (node <= 0) { + debug("XHCI: Can't get device node for usb3-phy controller\n"); + return -ENODEV; + } + + /* + * Get the base address for usbphy from the device node + */ + exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node, + "reg"); + if (exynos->usb3_phy == NULL) { + debug("Can't get the usbphy register address\n"); + return -ENXIO; + } + + return 0; +} +#endif + +static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) +{ + u32 reg; + + /* enabling usb_drd phy */ + set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); + + /* Reset USB 3.0 PHY */ + writel(0x0, &phy->phy_reg0); + + clrbits_le32(&phy->phy_param0, + /* Select PHY CLK source */ + PHYPARAM0_REF_USE_PAD | + /* Set Loss-of-Signal Detector sensitivity */ + PHYPARAM0_REF_LOSLEVEL_MASK); + setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); + + writel(0x0, &phy->phy_resume); + + /* + * Setting the Frame length Adj value[6:1] to default 0x20 + * See xHCI 1.0 spec, 5.2.4 + */ + setbits_le32(&phy->link_system, + LINKSYSTEM_XHCI_VERSION_CONTROL | + LINKSYSTEM_FLADJ(0x20)); + + /* Set Tx De-Emphasis level */ + clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); + setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); + + setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); + + /* PHYTEST POWERDOWN Control */ + clrbits_le32(&phy->phy_test, + PHYTEST_POWERDOWN_SSP | + PHYTEST_POWERDOWN_HSP); + + /* UTMI Power Control */ + writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi); + + /* Use core clock from main PLL */ + reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK | + /* Default 24Mhz crystal clock */ + PHYCLKRST_FSEL(FSEL_CLKSEL_24M) | + PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | + PHYCLKRST_SSC_REFCLKSEL(0x88) | + /* Force PortReset of PHY */ + PHYCLKRST_PORTRESET | + /* Digital power supply in normal operating mode */ + PHYCLKRST_RETENABLEN | + /* Enable ref clock for SS function */ + PHYCLKRST_REF_SSP_EN | + /* Enable spread spectrum */ + PHYCLKRST_SSC_EN | + /* Power down HS Bias and PLL blocks in suspend mode */ + PHYCLKRST_COMMONONN; + + writel(reg, &phy->phy_clk_rst); + + /* giving time to Phy clock to settle before resetting */ + udelay(10); + + reg &= ~PHYCLKRST_PORTRESET; + writel(reg, &phy->phy_clk_rst); +} + +static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy) +{ + setbits_le32(&phy->phy_utmi, + PHYUTMI_OTGDISABLE | + PHYUTMI_FORCESUSPEND | + PHYUTMI_FORCESLEEP); + + clrbits_le32(&phy->phy_clk_rst, + PHYCLKRST_REF_SSP_EN | + PHYCLKRST_SSC_EN | + PHYCLKRST_COMMONONN); + + /* PHYTEST POWERDOWN Control to remove leakage current */ + setbits_le32(&phy->phy_test, + PHYTEST_POWERDOWN_SSP | + PHYTEST_POWERDOWN_HSP); + + /* disabling usb_drd phy */ + set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE); +} + +void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) +{ + clrsetbits_le32(&dwc3_reg->g_ctl, + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), + DWC3_GCTL_PRTCAPDIR(mode)); +} + +static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) +{ + /* Before Resetting PHY, put Core in Reset */ + setbits_le32(&dwc3_reg->g_ctl, + DWC3_GCTL_CORESOFTRESET); + + /* Assert USB3 PHY reset */ + setbits_le32(&dwc3_reg->g_usb3pipectl[0], + DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Assert USB2 PHY reset */ + setbits_le32(&dwc3_reg->g_usb2phycfg, + DWC3_GUSB2PHYCFG_PHYSOFTRST); + + mdelay(100); + + /* Clear USB3 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], + DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Clear USB2 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb2phycfg, + DWC3_GUSB2PHYCFG_PHYSOFTRST); + + /* After PHYs are stable we can take Core out of reset state */ + clrbits_le32(&dwc3_reg->g_ctl, + DWC3_GCTL_CORESOFTRESET); +} + +static int dwc3_core_init(struct dwc3 *dwc3_reg) +{ + u32 reg; + u32 revision; + unsigned int dwc3_hwparams1; + + revision = readl(&dwc3_reg->g_snpsid); + /* This should read as U3 followed by revision number */ + if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { + puts("this is not a DesignWare USB3 DRD Core\n"); + return -EINVAL; + } + + dwc3_core_soft_reset(dwc3_reg); + + dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); + + reg = readl(&dwc3_reg->g_ctl); + reg &= ~DWC3_GCTL_SCALEDOWN_MASK; + reg &= ~DWC3_GCTL_DISSCRAMBLE; + switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { + case DWC3_GHWPARAMS1_EN_PWROPT_CLK: + reg &= ~DWC3_GCTL_DSBLCLKGTNG; + break; + default: + debug("No power optimization available\n"); + } + + /* + * WORKAROUND: DWC3 revisions <1.90a have a bug + * where the device can fail to connect at SuperSpeed + * and falls back to high-speed mode which causes + * the device to enter a Connect/Disconnect loop + */ + if ((revision & DWC3_REVISION_MASK) < 0x190a) + reg |= DWC3_GCTL_U2RSTECN; + + writel(reg, &dwc3_reg->g_ctl); + + return 0; +} + +static int exynos_xhci_core_init(struct exynos_xhci *exynos) +{ + int ret; + + exynos5_usb3_phy_init(exynos->usb3_phy); + + ret = dwc3_core_init(exynos->dwc3_reg); + if (ret) { + debug("failed to initialize core\n"); + return -EINVAL; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return 0; +} + +static void exynos_xhci_core_exit(struct exynos_xhci *exynos) +{ + exynos5_usb3_phy_exit(exynos->usb3_phy); +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct exynos_xhci *ctx = &exynos; + int ret; + +#ifdef CONFIG_OF_CONTROL + exynos_usb3_parse_dt(gd->fdt_blob, ctx); +#else + ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy(); + ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci(); +#endif + + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + +#ifdef CONFIG_OF_CONTROL + /* setup the Vbus gpio here */ + if (dm_gpio_is_valid(&ctx->vbus_gpio)) + dm_gpio_set_value(&ctx->vbus_gpio, 1); +#endif + + ret = exynos_xhci_core_init(ctx); + if (ret) { + puts("XHCI: failed to initialize controller\n"); + return -EINVAL; + } + + *hccr = (ctx->hcd); + *hcor = (struct xhci_hcor *)((uint32_t) *hccr + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)*hccr, (uint32_t)*hcor, + (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + return 0; +} + +void xhci_hcd_stop(int index) +{ + struct exynos_xhci *ctx = &exynos; + + exynos_xhci_core_exit(ctx); +} diff --git a/drivers/usb/host/xhci-keystone.c b/drivers/usb/host/xhci-keystone.c new file mode 100644 index 0000000000..05d338f261 --- /dev/null +++ b/drivers/usb/host/xhci-keystone.c @@ -0,0 +1,329 @@ +/* + * USB 3.0 DRD Controller + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "xhci.h" + +struct kdwc3_irq_regs { + u32 revision; /* 0x000 */ + u32 rsvd0[3]; + u32 sysconfig; /* 0x010 */ + u32 rsvd1[1]; + u32 irq_eoi; + u32 rsvd2[1]; + struct { + u32 raw_status; + u32 status; + u32 enable_set; + u32 enable_clr; + } irqs[16]; +}; + +struct keystone_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; + struct xhci_hcor *hcor; + struct kdwc3_irq_regs *usbss; + struct keystone_xhci_phy *phy; +}; + +struct keystone_xhci keystone; + +static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy) +{ + u32 val; + + /* + * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't. + * It should always be cleared because our USB PHY has an onchip VBUS + * analog comparator. + */ + val = readl(&phy->phy_clock); + /* quit selecting the vbusvldextsel by default! */ + val &= ~USB3_PHY_OTG_VBUSVLDECTSEL; + writel(val, &phy->phy_clock); +} + +static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy) +{ + u32 val; + + /* Disable the PHY REFCLK clock gate */ + val = readl(&phy->phy_clock); + val &= ~USB3_PHY_REF_SSP_EN; + writel(val, &phy->phy_clock); +} + +static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) +{ + clrsetbits_le32(&dwc3_reg->g_ctl, + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), + DWC3_GCTL_PRTCAPDIR(mode)); +} + +static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) +{ + /* Before Resetting PHY, put Core in Reset */ + setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); + + /* Assert USB3 PHY reset */ + setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Assert USB2 PHY reset */ + setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST); + + mdelay(100); + + /* Clear USB3 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Clear USB2 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST); + + /* After PHYs are stable we can take Core out of reset state */ + clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); +} + +static int dwc3_core_init(struct dwc3 *dwc3_reg) +{ + u32 revision, val; + unsigned long t_rst; + unsigned int dwc3_hwparams1; + + revision = readl(&dwc3_reg->g_snpsid); + /* This should read as U3 followed by revision number */ + if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { + puts("this is not a DesignWare USB3 DRD Core\n"); + return -EINVAL; + } + + /* issue device SoftReset too */ + writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl); + + t_rst = get_timer(0); + do { + val = readl(&dwc3_reg->d_ctl); + if (!(val & DWC3_DCTL_CSFTRST)) + break; + WATCHDOG_RESET(); + } while (get_timer(t_rst) < 500); + + if (val & DWC3_DCTL_CSFTRST) { + debug("Reset timed out\n"); + return -2; + } + + dwc3_core_soft_reset(dwc3_reg); + + dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); + + val = readl(&dwc3_reg->g_ctl); + val &= ~DWC3_GCTL_SCALEDOWN_MASK; + val &= ~DWC3_GCTL_DISSCRAMBLE; + switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { + case DWC3_GHWPARAMS1_EN_PWROPT_CLK: + val &= ~DWC3_GCTL_DSBLCLKGTNG; + break; + default: + printf("No power optimization available\n"); + } + + /* + * WORKAROUND: DWC3 revisions <1.90a have a bug + * where the device can fail to connect at SuperSpeed + * and falls back to high-speed mode which causes + * the device to enter a Connect/Disconnect loop + */ + if ((revision & DWC3_REVISION_MASK) < 0x190a) + val |= DWC3_GCTL_U2RSTECN; + + writel(val, &dwc3_reg->g_ctl); + + return 0; +} + +static int keystone_xhci_core_init(struct dwc3 *dwc3_reg) +{ + int ret; + + ret = dwc3_core_init(dwc3_reg); + if (ret) { + debug("failed to initialize core\n"); + return -EINVAL; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return 0; +} + +int xhci_hcd_init(int index, + struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor) +{ + u32 val; + int ret; + struct xhci_hccr *hcd; + struct xhci_hcor *hcor; + struct kdwc3_irq_regs *usbss; + struct keystone_xhci_phy *phy; + + usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE; + phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE; + + /* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */ + val = readl(&(phy->phy_clock)); + val |= USB3_PHY_REF_SSP_EN; + writel(val, &phy->phy_clock); + + mdelay(100); + + /* Release USB from reset */ + ret = psc_enable_module(KS2_LPSC_USB); + if (ret) { + puts("Cannot enable USB module"); + return -1; + } + + mdelay(100); + + /* Initialize usb phy */ + keystone_xhci_phy_set(phy); + + /* soft reset usbss */ + writel(1, &usbss->sysconfig); + while (readl(&usbss->sysconfig) & 1) + ; + + val = readl(&usbss->revision); + debug("usbss revision %x\n", val); + + /* Initialize usb core */ + hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE; + keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE + + DWC3_REG_OFFSET); + + keystone_xhci_core_init(keystone.dwc3_reg); + + /* set register addresses */ + hcor = (struct xhci_hcor *)((uint32_t)hcd + + HC_LENGTH(readl(&hcd->cr_capbase))); + + debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n", + (u32)hcd, (u32)hcor, + (u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase))); + + keystone.usbss = usbss; + keystone.phy = phy; + keystone.hcd = hcd; + keystone.hcor = hcor; + + *ret_hccr = hcd; + *ret_hcor = hcor; + + return 0; +} + +static int keystone_xhci_phy_suspend(void) +{ + int loop_cnt = 0; + struct xhci_hcor *hcor; + uint32_t *portsc_1 = NULL; + uint32_t *portsc_2 = NULL; + u32 val, usb2_pls, usb3_pls, event_q; + struct dwc3 *dwc3_reg = keystone.dwc3_reg; + + /* set register addresses */ + hcor = keystone.hcor; + + /* Bypass Scrambling and Set Shorter Training sequence for simulation */ + val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2); + writel(val, &dwc3_reg->g_ctl); + + /* GUSB2PHYCFG */ + val = readl(&dwc3_reg->g_usb2phycfg[0]); + + /* assert bit 6 (SusPhy) */ + val |= DWC3_GUSB2PHYCFG_SUSPHY; + writel(val, &dwc3_reg->g_usb2phycfg[0]); + + /* GUSB3PIPECTL */ + val = readl(&dwc3_reg->g_usb3pipectl[0]); + + /* + * assert bit 29 to allow PHY to go to suspend when idle + * and cause the USB3 SS PHY to enter suspend mode + */ + val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY); + writel(val, &dwc3_reg->g_usb3pipectl[0]); + + /* + * Steps necessary to allow controller to suspend even when + * VBUS is HIGH: + * - Init DCFG[2:0] (DevSpd) to: 1=FS + * - Init GEVNTADR0 to point to an eventQ + * - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ + * - Init DCTL::Run_nStop = 1 + */ + writel(0x00020001, &dwc3_reg->d_cfg); + /* TODO: local2global( (Uint32) eventQ )? */ + writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo); + writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi); + writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz); + /* Run */ + writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl); + + mdelay(100); + + /* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */ + portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc); + portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc); + usb2_pls = 0; + usb3_pls = 0; + do { + ++loop_cnt; + usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5; + usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5; + } while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000); + + if (usb2_pls != 0x4 || usb3_pls != 0x4) { + debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n", + usb2_pls, usb3_pls); + return -1; + } + + debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt); + return 0; +} + +void xhci_hcd_stop(int index) +{ + /* Disable USB */ + if (keystone_xhci_phy_suspend()) + return; + + if (psc_disable_module(KS2_LPSC_USB)) { + debug("PSC disable module USB failed!\n"); + return; + } + + /* Disable PHY */ + keystone_xhci_phy_unset(keystone.phy); + +/* memset(&keystone, 0, sizeof(struct keystone_xhci)); */ + debug("xhci_hcd_stop OK.\n"); +} diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c new file mode 100644 index 0000000000..89908e8a80 --- /dev/null +++ b/drivers/usb/host/xhci-mem.c @@ -0,0 +1,720 @@ +/* + * USB HOST XHCI Controller stack + * + * Based on xHCI host controller driver in linux-kernel + * by Sarah Sharp. + * + * Copyright (C) 2008 Intel Corp. + * Author: Sarah Sharp + * + * Copyright (C) 2013 Samsung Electronics Co.Ltd + * Authors: Vivek Gautam + * Vikas Sajjan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "xhci.h" + +#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE +/** + * flushes the address passed till the length + * + * @param addr pointer to memory region to be flushed + * @param len the length of the cache line to be flushed + * @return none + */ +void xhci_flush_cache(uint32_t addr, u32 len) +{ + BUG_ON((void *)addr == NULL || len == 0); + + flush_dcache_range(addr & ~(CACHELINE_SIZE - 1), + ALIGN(addr + len, CACHELINE_SIZE)); +} + +/** + * invalidates the address passed till the length + * + * @param addr pointer to memory region to be invalidates + * @param len the length of the cache line to be invalidated + * @return none + */ +void xhci_inval_cache(uint32_t addr, u32 len) +{ + BUG_ON((void *)addr == NULL || len == 0); + + invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1), + ALIGN(addr + len, CACHELINE_SIZE)); +} + + +/** + * frees the "segment" pointer passed + * + * @param ptr pointer to "segement" to be freed + * @return none + */ +static void xhci_segment_free(struct xhci_segment *seg) +{ + free(seg->trbs); + seg->trbs = NULL; + + free(seg); +} + +/** + * frees the "ring" pointer passed + * + * @param ptr pointer to "ring" to be freed + * @return none + */ +static void xhci_ring_free(struct xhci_ring *ring) +{ + struct xhci_segment *seg; + struct xhci_segment *first_seg; + + BUG_ON(!ring); + + first_seg = ring->first_seg; + seg = first_seg->next; + while (seg != first_seg) { + struct xhci_segment *next = seg->next; + xhci_segment_free(seg); + seg = next; + } + xhci_segment_free(first_seg); + + free(ring); +} + +/** + * frees the "xhci_container_ctx" pointer passed + * + * @param ptr pointer to "xhci_container_ctx" to be freed + * @return none + */ +static void xhci_free_container_ctx(struct xhci_container_ctx *ctx) +{ + free(ctx->bytes); + free(ctx); +} + +/** + * frees the virtual devices for "xhci_ctrl" pointer passed + * + * @param ptr pointer to "xhci_ctrl" whose virtual devices are to be freed + * @return none + */ +static void xhci_free_virt_devices(struct xhci_ctrl *ctrl) +{ + int i; + int slot_id; + struct xhci_virt_device *virt_dev; + + /* + * refactored here to loop through all virt_dev + * Slot ID 0 is reserved + */ + for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) { + virt_dev = ctrl->devs[slot_id]; + if (!virt_dev) + continue; + + ctrl->dcbaa->dev_context_ptrs[slot_id] = 0; + + for (i = 0; i < 31; ++i) + if (virt_dev->eps[i].ring) + xhci_ring_free(virt_dev->eps[i].ring); + + if (virt_dev->in_ctx) + xhci_free_container_ctx(virt_dev->in_ctx); + if (virt_dev->out_ctx) + xhci_free_container_ctx(virt_dev->out_ctx); + + free(virt_dev); + /* make sure we are pointing to NULL */ + ctrl->devs[slot_id] = NULL; + } +} + +/** + * frees all the memory allocated + * + * @param ptr pointer to "xhci_ctrl" to be cleaned up + * @return none + */ +void xhci_cleanup(struct xhci_ctrl *ctrl) +{ + xhci_ring_free(ctrl->event_ring); + xhci_ring_free(ctrl->cmd_ring); + xhci_free_virt_devices(ctrl); + free(ctrl->erst.entries); + free(ctrl->dcbaa); + memset(ctrl, '\0', sizeof(struct xhci_ctrl)); +} + +/** + * Malloc the aligned memory + * + * @param size size of memory to be allocated + * @return allocates the memory and returns the aligned pointer + */ +static void *xhci_malloc(unsigned int size) +{ + void *ptr; + size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE); + + ptr = memalign(cacheline_size, ALIGN(size, cacheline_size)); + BUG_ON(!ptr); + memset(ptr, '\0', size); + + xhci_flush_cache((uint32_t)ptr, size); + + return ptr; +} + +/** + * Make the prev segment point to the next segment. + * Change the last TRB in the prev segment to be a Link TRB which points to the + * address of the next segment. The caller needs to set any Link TRB + * related flags, such as End TRB, Toggle Cycle, and no snoop. + * + * @param prev pointer to the previous segment + * @param next pointer to the next segment + * @param link_trbs flag to indicate whether to link the trbs or NOT + * @return none + */ +static void xhci_link_segments(struct xhci_segment *prev, + struct xhci_segment *next, bool link_trbs) +{ + u32 val; + u64 val_64 = 0; + + if (!prev || !next) + return; + prev->next = next; + if (link_trbs) { + val_64 = (uintptr_t)next->trbs; + prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = val_64; + + /* + * Set the last TRB in the segment to + * have a TRB type ID of Link TRB + */ + val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); + val &= ~TRB_TYPE_BITMASK; + val |= (TRB_LINK << TRB_TYPE_SHIFT); + + prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); + } +} + +/** + * Initialises the Ring's enqueue,dequeue,enq_seg pointers + * + * @param ring pointer to the RING to be intialised + * @return none + */ +static void xhci_initialize_ring_info(struct xhci_ring *ring) +{ + /* + * The ring is empty, so the enqueue pointer == dequeue pointer + */ + ring->enqueue = ring->first_seg->trbs; + ring->enq_seg = ring->first_seg; + ring->dequeue = ring->enqueue; + ring->deq_seg = ring->first_seg; + + /* + * The ring is initialized to 0. The producer must write 1 to the + * cycle bit to handover ownership of the TRB, so PCS = 1. + * The consumer must compare CCS to the cycle bit to + * check ownership, so CCS = 1. + */ + ring->cycle_state = 1; +} + +/** + * Allocates a generic ring segment from the ring pool, sets the dma address, + * initializes the segment to zero, and sets the private next pointer to NULL. + * Section 4.11.1.1: + * "All components of all Command and Transfer TRBs shall be initialized to '0'" + * + * @param none + * @return pointer to the newly allocated SEGMENT + */ +static struct xhci_segment *xhci_segment_alloc(void) +{ + struct xhci_segment *seg; + + seg = (struct xhci_segment *)malloc(sizeof(struct xhci_segment)); + BUG_ON(!seg); + + seg->trbs = (union xhci_trb *)xhci_malloc(SEGMENT_SIZE); + + seg->next = NULL; + + return seg; +} + +/** + * Create a new ring with zero or more segments. + * TODO: current code only uses one-time-allocated single-segment rings + * of 1KB anyway, so we might as well get rid of all the segment and + * linking code (and maybe increase the size a bit, e.g. 4KB). + * + * + * Link each segment together into a ring. + * Set the end flag and the cycle toggle bit on the last segment. + * See section 4.9.2 and figures 15 and 16 of XHCI spec rev1.0. + * + * @param num_segs number of segments in the ring + * @param link_trbs flag to indicate whether to link the trbs or NOT + * @return pointer to the newly created RING + */ +struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs) +{ + struct xhci_ring *ring; + struct xhci_segment *prev; + + ring = (struct xhci_ring *)malloc(sizeof(struct xhci_ring)); + BUG_ON(!ring); + + if (num_segs == 0) + return ring; + + ring->first_seg = xhci_segment_alloc(); + BUG_ON(!ring->first_seg); + + num_segs--; + + prev = ring->first_seg; + while (num_segs > 0) { + struct xhci_segment *next; + + next = xhci_segment_alloc(); + BUG_ON(!next); + + xhci_link_segments(prev, next, link_trbs); + + prev = next; + num_segs--; + } + xhci_link_segments(prev, ring->first_seg, link_trbs); + if (link_trbs) { + /* See section 4.9.2.1 and 6.4.4.1 */ + prev->trbs[TRBS_PER_SEGMENT-1].link.control |= + cpu_to_le32(LINK_TOGGLE); + } + xhci_initialize_ring_info(ring); + + return ring; +} + +/** + * Allocates the Container context + * + * @param ctrl Host controller data structure + * @param type type of XHCI Container Context + * @return NULL if failed else pointer to the context on success + */ +static struct xhci_container_ctx + *xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type) +{ + struct xhci_container_ctx *ctx; + + ctx = (struct xhci_container_ctx *) + malloc(sizeof(struct xhci_container_ctx)); + BUG_ON(!ctx); + + BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)); + ctx->type = type; + ctx->size = (MAX_EP_CTX_NUM + 1) * + CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)); + if (type == XHCI_CTX_TYPE_INPUT) + ctx->size += CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)); + + ctx->bytes = (u8 *)xhci_malloc(ctx->size); + + return ctx; +} + +/** + * Allocating virtual device + * + * @param udev pointer to USB deivce structure + * @return 0 on success else -1 on failure + */ +int xhci_alloc_virt_device(struct usb_device *udev) +{ + u64 byte_64 = 0; + unsigned int slot_id = udev->slot_id; + struct xhci_virt_device *virt_dev; + struct xhci_ctrl *ctrl = udev->controller; + + /* Slot ID 0 is reserved */ + if (ctrl->devs[slot_id]) { + printf("Virt dev for slot[%d] already allocated\n", slot_id); + return -EEXIST; + } + + ctrl->devs[slot_id] = (struct xhci_virt_device *) + malloc(sizeof(struct xhci_virt_device)); + + if (!ctrl->devs[slot_id]) { + puts("Failed to allocate virtual device\n"); + return -ENOMEM; + } + + memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device)); + virt_dev = ctrl->devs[slot_id]; + + /* Allocate the (output) device context that will be used in the HC. */ + virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl, + XHCI_CTX_TYPE_DEVICE); + if (!virt_dev->out_ctx) { + puts("Failed to allocate out context for virt dev\n"); + return -ENOMEM; + } + + /* Allocate the (input) device context for address device command */ + virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl, + XHCI_CTX_TYPE_INPUT); + if (!virt_dev->in_ctx) { + puts("Failed to allocate in context for virt dev\n"); + return -ENOMEM; + } + + /* Allocate endpoint 0 ring */ + virt_dev->eps[0].ring = xhci_ring_alloc(1, true); + + byte_64 = (uintptr_t)(virt_dev->out_ctx->bytes); + + /* Point to output device context in dcbaa. */ + ctrl->dcbaa->dev_context_ptrs[slot_id] = byte_64; + + xhci_flush_cache((uint32_t)&ctrl->dcbaa->dev_context_ptrs[slot_id], + sizeof(__le64)); + return 0; +} + +/** + * Allocates the necessary data structures + * for XHCI host controller + * + * @param ctrl Host controller data structure + * @param hccr pointer to HOST Controller Control Registers + * @param hcor pointer to HOST Controller Operational Registers + * @return 0 if successful else -1 on failure + */ +int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr, + struct xhci_hcor *hcor) +{ + uint64_t val_64; + uint64_t trb_64; + uint32_t val; + unsigned long deq; + int i; + struct xhci_segment *seg; + + /* DCBAA initialization */ + ctrl->dcbaa = (struct xhci_device_context_array *) + xhci_malloc(sizeof(struct xhci_device_context_array)); + if (ctrl->dcbaa == NULL) { + puts("unable to allocate DCBA\n"); + return -ENOMEM; + } + + val_64 = (uintptr_t)ctrl->dcbaa; + /* Set the pointer in DCBAA register */ + xhci_writeq(&hcor->or_dcbaap, val_64); + + /* Command ring control pointer register initialization */ + ctrl->cmd_ring = xhci_ring_alloc(1, true); + + /* Set the address in the Command Ring Control register */ + trb_64 = (uintptr_t)ctrl->cmd_ring->first_seg->trbs; + val_64 = xhci_readq(&hcor->or_crcr); + val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | + (trb_64 & (u64) ~CMD_RING_RSVD_BITS) | + ctrl->cmd_ring->cycle_state; + xhci_writeq(&hcor->or_crcr, val_64); + + /* write the address of db register */ + val = xhci_readl(&hccr->cr_dboff); + val &= DBOFF_MASK; + ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val); + + /* write the address of runtime register */ + val = xhci_readl(&hccr->cr_rtsoff); + val &= RTSOFF_MASK; + ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val); + + /* writting the address of ir_set structure */ + ctrl->ir_set = &ctrl->run_regs->ir_set[0]; + + /* Event ring does not maintain link TRB */ + ctrl->event_ring = xhci_ring_alloc(ERST_NUM_SEGS, false); + ctrl->erst.entries = (struct xhci_erst_entry *) + xhci_malloc(sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS); + + ctrl->erst.num_entries = ERST_NUM_SEGS; + + for (val = 0, seg = ctrl->event_ring->first_seg; + val < ERST_NUM_SEGS; + val++) { + trb_64 = 0; + trb_64 = (uintptr_t)seg->trbs; + struct xhci_erst_entry *entry = &ctrl->erst.entries[val]; + xhci_writeq(&entry->seg_addr, trb_64); + entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); + entry->rsvd = 0; + seg = seg->next; + } + xhci_flush_cache((uint32_t)ctrl->erst.entries, + ERST_NUM_SEGS * sizeof(struct xhci_erst_entry)); + + deq = (unsigned long)ctrl->event_ring->dequeue; + + /* Update HC event ring dequeue pointer */ + xhci_writeq(&ctrl->ir_set->erst_dequeue, + (u64)deq & (u64)~ERST_PTR_MASK); + + /* set ERST count with the number of entries in the segment table */ + val = xhci_readl(&ctrl->ir_set->erst_size); + val &= ERST_SIZE_MASK; + val |= ERST_NUM_SEGS; + xhci_writel(&ctrl->ir_set->erst_size, val); + + /* this is the event ring segment table pointer */ + val_64 = xhci_readq(&ctrl->ir_set->erst_base); + val_64 &= ERST_PTR_MASK; + val_64 |= ((u32)(ctrl->erst.entries) & ~ERST_PTR_MASK); + + xhci_writeq(&ctrl->ir_set->erst_base, val_64); + + /* initializing the virtual devices to NULL */ + for (i = 0; i < MAX_HC_SLOTS; ++i) + ctrl->devs[i] = NULL; + + /* + * Just Zero'ing this register completely, + * or some spurious Device Notification Events + * might screw things here. + */ + xhci_writel(&hcor->or_dnctrl, 0x0); + + return 0; +} + +/** + * Give the input control context for the passed container context + * + * @param ctx pointer to the context + * @return pointer to the Input control context data + */ +struct xhci_input_control_ctx + *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx) +{ + BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT); + return (struct xhci_input_control_ctx *)ctx->bytes; +} + +/** + * Give the slot context for the passed container context + * + * @param ctrl Host controller data structure + * @param ctx pointer to the context + * @return pointer to the slot control context data + */ +struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *ctx) +{ + if (ctx->type == XHCI_CTX_TYPE_DEVICE) + return (struct xhci_slot_ctx *)ctx->bytes; + + return (struct xhci_slot_ctx *) + (ctx->bytes + CTX_SIZE(readl(&ctrl->hccr->cr_hccparams))); +} + +/** + * Gets the EP context from based on the ep_index + * + * @param ctrl Host controller data structure + * @param ctx context container + * @param ep_index index of the endpoint + * @return pointer to the End point context + */ +struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *ctx, + unsigned int ep_index) +{ + /* increment ep index by offset of start of ep ctx array */ + ep_index++; + if (ctx->type == XHCI_CTX_TYPE_INPUT) + ep_index++; + + return (struct xhci_ep_ctx *) + (ctx->bytes + + (ep_index * CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)))); +} + +/** + * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. + * Useful when you want to change one particular aspect of the endpoint + * and then issue a configure endpoint command. + * + * @param ctrl Host controller data structure + * @param in_ctx contains the input context + * @param out_ctx contains the input context + * @param ep_index index of the end point + * @return none + */ +void xhci_endpoint_copy(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *in_ctx, + struct xhci_container_ctx *out_ctx, + unsigned int ep_index) +{ + struct xhci_ep_ctx *out_ep_ctx; + struct xhci_ep_ctx *in_ep_ctx; + + out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index); + in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); + + in_ep_ctx->ep_info = out_ep_ctx->ep_info; + in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; + in_ep_ctx->deq = out_ep_ctx->deq; + in_ep_ctx->tx_info = out_ep_ctx->tx_info; +} + +/** + * Copy output xhci_slot_ctx to the input xhci_slot_ctx. + * Useful when you want to change one particular aspect of the endpoint + * and then issue a configure endpoint command. + * Only the context entries field matters, but + * we'll copy the whole thing anyway. + * + * @param ctrl Host controller data structure + * @param in_ctx contains the inpout context + * @param out_ctx contains the inpout context + * @return none + */ +void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx, + struct xhci_container_ctx *out_ctx) +{ + struct xhci_slot_ctx *in_slot_ctx; + struct xhci_slot_ctx *out_slot_ctx; + + in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); + out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx); + + in_slot_ctx->dev_info = out_slot_ctx->dev_info; + in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; + in_slot_ctx->tt_info = out_slot_ctx->tt_info; + in_slot_ctx->dev_state = out_slot_ctx->dev_state; +} + +/** + * Setup an xHCI virtual device for a Set Address command + * + * @param udev pointer to the Device Data Structure + * @return returns negative value on failure else 0 on success + */ +void xhci_setup_addressable_virt_dev(struct usb_device *udev) +{ + struct usb_device *hop = udev; + struct xhci_virt_device *virt_dev; + struct xhci_ep_ctx *ep0_ctx; + struct xhci_slot_ctx *slot_ctx; + u32 port_num = 0; + u64 trb_64 = 0; + struct xhci_ctrl *ctrl = udev->controller; + + virt_dev = ctrl->devs[udev->slot_id]; + + BUG_ON(!virt_dev); + + /* Extract the EP0 and Slot Ctrl */ + ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0); + slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx); + + /* Only the control endpoint is valid - one endpoint context */ + slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | 0); + + switch (udev->speed) { + case USB_SPEED_SUPER: + slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); + break; + case USB_SPEED_HIGH: + slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); + break; + case USB_SPEED_FULL: + slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); + break; + case USB_SPEED_LOW: + slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); + break; + default: + /* Speed was set earlier, this shouldn't happen. */ + BUG(); + } + + /* Extract the root hub port number */ + if (hop->parent) + while (hop->parent->parent) + hop = hop->parent; + port_num = hop->portnr; + debug("port_num = %d\n", port_num); + + slot_ctx->dev_info2 |= + cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) << + ROOT_HUB_PORT_SHIFT)); + + /* Step 4 - ring already allocated */ + /* Step 5 */ + ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT); + debug("SPEED = %d\n", udev->speed); + + switch (udev->speed) { + case USB_SPEED_SUPER: + ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) << + MAX_PACKET_SHIFT)); + debug("Setting Packet size = 512bytes\n"); + break; + case USB_SPEED_HIGH: + /* USB core guesses at a 64-byte max packet first for FS devices */ + case USB_SPEED_FULL: + ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) << + MAX_PACKET_SHIFT)); + debug("Setting Packet size = 64bytes\n"); + break; + case USB_SPEED_LOW: + ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) << + MAX_PACKET_SHIFT)); + debug("Setting Packet size = 8bytes\n"); + break; + default: + /* New speed? */ + BUG(); + } + + /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ + ep0_ctx->ep_info2 |= + cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) | + ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT)); + + trb_64 = (uintptr_t)virt_dev->eps[0].ring->first_seg->trbs; + ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state); + + /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ + + xhci_flush_cache((uint32_t)ep0_ctx, sizeof(struct xhci_ep_ctx)); + xhci_flush_cache((uint32_t)slot_ctx, sizeof(struct xhci_slot_ctx)); +} diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c new file mode 100644 index 0000000000..912b2bd8d5 --- /dev/null +++ b/drivers/usb/host/xhci-omap.c @@ -0,0 +1,159 @@ +/* + * OMAP USB HOST xHCI Controller + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Author: Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "xhci.h" + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +static struct omap_xhci omap; + +inline int __board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} +int board_usb_init(int index, enum usb_init_type init) + __attribute__((weak, alias("__board_usb_init"))); + +static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) +{ + clrsetbits_le32(&dwc3_reg->g_ctl, + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), + DWC3_GCTL_PRTCAPDIR(mode)); +} + +static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) +{ + /* Before Resetting PHY, put Core in Reset */ + setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); + + omap_reset_usb_phy(dwc3_reg); + + /* After PHYs are stable we can take Core out of reset state */ + clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); +} + +static int dwc3_core_init(struct dwc3 *dwc3_reg) +{ + u32 reg; + u32 revision; + unsigned int dwc3_hwparams1; + + revision = readl(&dwc3_reg->g_snpsid); + /* This should read as U3 followed by revision number */ + if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { + puts("this is not a DesignWare USB3 DRD Core\n"); + return -1; + } + + dwc3_core_soft_reset(dwc3_reg); + + dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); + + reg = readl(&dwc3_reg->g_ctl); + reg &= ~DWC3_GCTL_SCALEDOWN_MASK; + reg &= ~DWC3_GCTL_DISSCRAMBLE; + switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { + case DWC3_GHWPARAMS1_EN_PWROPT_CLK: + reg &= ~DWC3_GCTL_DSBLCLKGTNG; + break; + default: + debug("No power optimization available\n"); + } + + /* + * WORKAROUND: DWC3 revisions <1.90a have a bug + * where the device can fail to connect at SuperSpeed + * and falls back to high-speed mode which causes + * the device to enter a Connect/Disconnect loop + */ + if ((revision & DWC3_REVISION_MASK) < 0x190a) + reg |= DWC3_GCTL_U2RSTECN; + + writel(reg, &dwc3_reg->g_ctl); + + return 0; +} + +static int omap_xhci_core_init(struct omap_xhci *omap) +{ + int ret = 0; + + usb_phy_power(1); + omap_enable_phy(omap); + + ret = dwc3_core_init(omap->dwc3_reg); + if (ret) { + debug("%s:failed to initialize core\n", __func__); + return ret; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return ret; +} + +static void omap_xhci_core_exit(struct omap_xhci *omap) +{ + usb_phy_power(0); +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct omap_xhci *ctx = &omap; + int ret = 0; + + ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE; + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE; + ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE; + + ret = board_usb_init(index, USB_INIT_HOST); + if (ret != 0) { + puts("Failed to initialize board for USB\n"); + return ret; + } + + ret = omap_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize xhci\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE); + *hcor = (struct xhci_hcor *)((uint32_t) *hccr + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)*hccr, (uint32_t)*hcor, + (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + return ret; +} + +void xhci_hcd_stop(int index) +{ + struct omap_xhci *ctx = &omap; + + omap_xhci_core_exit(ctx); +} diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c new file mode 100644 index 0000000000..b5aade988d --- /dev/null +++ b/drivers/usb/host/xhci-ring.c @@ -0,0 +1,939 @@ +/* + * USB HOST XHCI Controller stack + * + * Based on xHCI host controller driver in linux-kernel + * by Sarah Sharp. + * + * Copyright (C) 2008 Intel Corp. + * Author: Sarah Sharp + * + * Copyright (C) 2013 Samsung Electronics Co.Ltd + * Authors: Vivek Gautam + * Vikas Sajjan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include "xhci.h" + +/** + * Is this TRB a link TRB or was the last TRB the last TRB in this event ring + * segment? I.e. would the updated event TRB pointer step off the end of the + * event seg ? + * + * @param ctrl Host controller data structure + * @param ring pointer to the ring + * @param seg poniter to the segment to which TRB belongs + * @param trb poniter to the ring trb + * @return 1 if this TRB a link TRB else 0 + */ +static int last_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring, + struct xhci_segment *seg, union xhci_trb *trb) +{ + if (ring == ctrl->event_ring) + return trb == &seg->trbs[TRBS_PER_SEGMENT]; + else + return TRB_TYPE_LINK_LE32(trb->link.control); +} + +/** + * Does this link TRB point to the first segment in a ring, + * or was the previous TRB the last TRB on the last segment in the ERST? + * + * @param ctrl Host controller data structure + * @param ring pointer to the ring + * @param seg poniter to the segment to which TRB belongs + * @param trb poniter to the ring trb + * @return 1 if this TRB is the last TRB on the last segment else 0 + */ +static bool last_trb_on_last_seg(struct xhci_ctrl *ctrl, + struct xhci_ring *ring, + struct xhci_segment *seg, + union xhci_trb *trb) +{ + if (ring == ctrl->event_ring) + return ((trb == &seg->trbs[TRBS_PER_SEGMENT]) && + (seg->next == ring->first_seg)); + else + return le32_to_cpu(trb->link.control) & LINK_TOGGLE; +} + +/** + * See Cycle bit rules. SW is the consumer for the event ring only. + * Don't make a ring full of link TRBs. That would be dumb and this would loop. + * + * If we've just enqueued a TRB that is in the middle of a TD (meaning the + * chain bit is set), then set the chain bit in all the following link TRBs. + * If we've enqueued the last TRB in a TD, make sure the following link TRBs + * have their chain bit cleared (so that each Link TRB is a separate TD). + * + * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit + * set, but other sections talk about dealing with the chain bit set. This was + * fixed in the 0.96 specification errata, but we have to assume that all 0.95 + * xHCI hardware can't handle the chain bit being cleared on a link TRB. + * + * @param ctrl Host controller data structure + * @param ring pointer to the ring + * @param more_trbs_coming flag to indicate whether more trbs + * are expected or NOT. + * Will you enqueue more TRBs before calling + * prepare_ring()? + * @return none + */ +static void inc_enq(struct xhci_ctrl *ctrl, struct xhci_ring *ring, + bool more_trbs_coming) +{ + u32 chain; + union xhci_trb *next; + + chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; + next = ++(ring->enqueue); + + /* + * Update the dequeue pointer further if that was a link TRB or we're at + * the end of an event ring segment (which doesn't have link TRBS) + */ + while (last_trb(ctrl, ring, ring->enq_seg, next)) { + if (ring != ctrl->event_ring) { + /* + * If the caller doesn't plan on enqueueing more + * TDs before ringing the doorbell, then we + * don't want to give the link TRB to the + * hardware just yet. We'll give the link TRB + * back in prepare_ring() just before we enqueue + * the TD at the top of the ring. + */ + if (!chain && !more_trbs_coming) + break; + + /* + * If we're not dealing with 0.95 hardware or + * isoc rings on AMD 0.96 host, + * carry over the chain bit of the previous TRB + * (which may mean the chain bit is cleared). + */ + next->link.control &= cpu_to_le32(~TRB_CHAIN); + next->link.control |= cpu_to_le32(chain); + + next->link.control ^= cpu_to_le32(TRB_CYCLE); + xhci_flush_cache((uint32_t)next, + sizeof(union xhci_trb)); + } + /* Toggle the cycle bit after the last ring segment. */ + if (last_trb_on_last_seg(ctrl, ring, + ring->enq_seg, next)) + ring->cycle_state = (ring->cycle_state ? 0 : 1); + + ring->enq_seg = ring->enq_seg->next; + ring->enqueue = ring->enq_seg->trbs; + next = ring->enqueue; + } +} + +/** + * See Cycle bit rules. SW is the consumer for the event ring only. + * Don't make a ring full of link TRBs. That would be dumb and this would loop. + * + * @param ctrl Host controller data structure + * @param ring Ring whose Dequeue TRB pointer needs to be incremented. + * return none + */ +static void inc_deq(struct xhci_ctrl *ctrl, struct xhci_ring *ring) +{ + do { + /* + * Update the dequeue pointer further if that was a link TRB or + * we're at the end of an event ring segment (which doesn't have + * link TRBS) + */ + if (last_trb(ctrl, ring, ring->deq_seg, ring->dequeue)) { + if (ring == ctrl->event_ring && + last_trb_on_last_seg(ctrl, ring, + ring->deq_seg, ring->dequeue)) { + ring->cycle_state = (ring->cycle_state ? 0 : 1); + } + ring->deq_seg = ring->deq_seg->next; + ring->dequeue = ring->deq_seg->trbs; + } else { + ring->dequeue++; + } + } while (last_trb(ctrl, ring, ring->deq_seg, ring->dequeue)); +} + +/** + * Generic function for queueing a TRB on a ring. + * The caller must have checked to make sure there's room on the ring. + * + * @param more_trbs_coming: Will you enqueue more TRBs before calling + * prepare_ring()? + * @param ctrl Host controller data structure + * @param ring pointer to the ring + * @param more_trbs_coming flag to indicate whether more trbs + * @param trb_fields pointer to trb field array containing TRB contents + * @return pointer to the enqueued trb + */ +static struct xhci_generic_trb *queue_trb(struct xhci_ctrl *ctrl, + struct xhci_ring *ring, + bool more_trbs_coming, + unsigned int *trb_fields) +{ + struct xhci_generic_trb *trb; + int i; + + trb = &ring->enqueue->generic; + + for (i = 0; i < 4; i++) + trb->field[i] = cpu_to_le32(trb_fields[i]); + + xhci_flush_cache((uint32_t)trb, sizeof(struct xhci_generic_trb)); + + inc_enq(ctrl, ring, more_trbs_coming); + + return trb; +} + +/** + * Does various checks on the endpoint ring, and makes it ready + * to queue num_trbs. + * + * @param ctrl Host controller data structure + * @param ep_ring pointer to the EP Transfer Ring + * @param ep_state State of the End Point + * @return error code in case of invalid ep_state, 0 on success + */ +static int prepare_ring(struct xhci_ctrl *ctrl, struct xhci_ring *ep_ring, + u32 ep_state) +{ + union xhci_trb *next = ep_ring->enqueue; + + /* Make sure the endpoint has been added to xHC schedule */ + switch (ep_state) { + case EP_STATE_DISABLED: + /* + * USB core changed config/interfaces without notifying us, + * or hardware is reporting the wrong state. + */ + puts("WARN urb submitted to disabled ep\n"); + return -ENOENT; + case EP_STATE_ERROR: + puts("WARN waiting for error on ep to be cleared\n"); + return -EINVAL; + case EP_STATE_HALTED: + puts("WARN halted endpoint, queueing URB anyway.\n"); + case EP_STATE_STOPPED: + case EP_STATE_RUNNING: + debug("EP STATE RUNNING.\n"); + break; + default: + puts("ERROR unknown endpoint state for ep\n"); + return -EINVAL; + } + + while (last_trb(ctrl, ep_ring, ep_ring->enq_seg, next)) { + /* + * If we're not dealing with 0.95 hardware or isoc rings + * on AMD 0.96 host, clear the chain bit. + */ + next->link.control &= cpu_to_le32(~TRB_CHAIN); + + next->link.control ^= cpu_to_le32(TRB_CYCLE); + + xhci_flush_cache((uint32_t)next, sizeof(union xhci_trb)); + + /* Toggle the cycle bit after the last ring segment. */ + if (last_trb_on_last_seg(ctrl, ep_ring, + ep_ring->enq_seg, next)) + ep_ring->cycle_state = (ep_ring->cycle_state ? 0 : 1); + ep_ring->enq_seg = ep_ring->enq_seg->next; + ep_ring->enqueue = ep_ring->enq_seg->trbs; + next = ep_ring->enqueue; + } + + return 0; +} + +/** + * Generic function for queueing a command TRB on the command ring. + * Check to make sure there's room on the command ring for one command TRB. + * + * @param ctrl Host controller data structure + * @param ptr Pointer address to write in the first two fields (opt.) + * @param slot_id Slot ID to encode in the flags field (opt.) + * @param ep_index Endpoint index to encode in the flags field (opt.) + * @param cmd Command type to enqueue + * @return none + */ +void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, u32 slot_id, + u32 ep_index, trb_type cmd) +{ + u32 fields[4]; + u64 val_64 = (uintptr_t)ptr; + + BUG_ON(prepare_ring(ctrl, ctrl->cmd_ring, EP_STATE_RUNNING)); + + fields[0] = lower_32_bits(val_64); + fields[1] = upper_32_bits(val_64); + fields[2] = 0; + fields[3] = TRB_TYPE(cmd) | EP_ID_FOR_TRB(ep_index) | + SLOT_ID_FOR_TRB(slot_id) | ctrl->cmd_ring->cycle_state; + + queue_trb(ctrl, ctrl->cmd_ring, false, fields); + + /* Ring the command ring doorbell */ + xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST); +} + +/** + * The TD size is the number of bytes remaining in the TD (including this TRB), + * right shifted by 10. + * It must fit in bits 21:17, so it can't be bigger than 31. + * + * @param remainder remaining packets to be sent + * @return remainder if remainder is less than max else max + */ +static u32 xhci_td_remainder(unsigned int remainder) +{ + u32 max = (1 << (21 - 17 + 1)) - 1; + + if ((remainder >> 10) >= max) + return max << 17; + else + return (remainder >> 10) << 17; +} + +/** + * Finds out the remanining packets to be sent + * + * @param running_total total size sent so far + * @param trb_buff_len length of the TRB Buffer + * @param total_packet_count total packet count + * @param maxpacketsize max packet size of current pipe + * @param num_trbs_left number of TRBs left to be processed + * @return 0 if running_total or trb_buff_len is 0, else remainder + */ +static u32 xhci_v1_0_td_remainder(int running_total, + int trb_buff_len, + unsigned int total_packet_count, + int maxpacketsize, + unsigned int num_trbs_left) +{ + int packets_transferred; + + /* One TRB with a zero-length data packet. */ + if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0)) + return 0; + + /* + * All the TRB queueing functions don't count the current TRB in + * running_total. + */ + packets_transferred = (running_total + trb_buff_len) / maxpacketsize; + + if ((total_packet_count - packets_transferred) > 31) + return 31 << 17; + return (total_packet_count - packets_transferred) << 17; +} + +/** + * Ring the doorbell of the End Point + * + * @param udev pointer to the USB device structure + * @param ep_index index of the endpoint + * @param start_cycle cycle flag of the first TRB + * @param start_trb pionter to the first TRB + * @return none + */ +static void giveback_first_trb(struct usb_device *udev, int ep_index, + int start_cycle, + struct xhci_generic_trb *start_trb) +{ + struct xhci_ctrl *ctrl = udev->controller; + + /* + * Pass all the TRBs to the hardware at once and make sure this write + * isn't reordered. + */ + if (start_cycle) + start_trb->field[3] |= cpu_to_le32(start_cycle); + else + start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); + + xhci_flush_cache((uint32_t)start_trb, sizeof(struct xhci_generic_trb)); + + /* Ringing EP doorbell here */ + xhci_writel(&ctrl->dba->doorbell[udev->slot_id], + DB_VALUE(ep_index, 0)); + + return; +} + +/**** POLLING mechanism for XHCI ****/ + +/** + * Finalizes a handled event TRB by advancing our dequeue pointer and giving + * the TRB back to the hardware for recycling. Must call this exactly once at + * the end of each event handler, and not touch the TRB again afterwards. + * + * @param ctrl Host controller data structure + * @return none + */ +void xhci_acknowledge_event(struct xhci_ctrl *ctrl) +{ + /* Advance our dequeue pointer to the next event */ + inc_deq(ctrl, ctrl->event_ring); + + /* Inform the hardware */ + xhci_writeq(&ctrl->ir_set->erst_dequeue, + (uintptr_t)ctrl->event_ring->dequeue | ERST_EHB); +} + +/** + * Checks if there is a new event to handle on the event ring. + * + * @param ctrl Host controller data structure + * @return 0 if failure else 1 on success + */ +static int event_ready(struct xhci_ctrl *ctrl) +{ + union xhci_trb *event; + + xhci_inval_cache((uint32_t)ctrl->event_ring->dequeue, + sizeof(union xhci_trb)); + + event = ctrl->event_ring->dequeue; + + /* Does the HC or OS own the TRB? */ + if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != + ctrl->event_ring->cycle_state) + return 0; + + return 1; +} + +/** + * Waits for a specific type of event and returns it. Discards unexpected + * events. Caller *must* call xhci_acknowledge_event() after it is finished + * processing the event, and must not access the returned pointer afterwards. + * + * @param ctrl Host controller data structure + * @param expected TRB type expected from Event TRB + * @return pointer to event trb + */ +union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected) +{ + trb_type type; + unsigned long ts = get_timer(0); + + do { + union xhci_trb *event = ctrl->event_ring->dequeue; + + if (!event_ready(ctrl)) + continue; + + type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags)); + if (type == expected) + return event; + + if (type == TRB_PORT_STATUS) + /* TODO: remove this once enumeration has been reworked */ + /* + * Port status change events always have a + * successful completion code + */ + BUG_ON(GET_COMP_CODE( + le32_to_cpu(event->generic.field[2])) != + COMP_SUCCESS); + else + printf("Unexpected XHCI event TRB, skipping... " + "(%08x %08x %08x %08x)\n", + le32_to_cpu(event->generic.field[0]), + le32_to_cpu(event->generic.field[1]), + le32_to_cpu(event->generic.field[2]), + le32_to_cpu(event->generic.field[3])); + + xhci_acknowledge_event(ctrl); + } while (get_timer(ts) < XHCI_TIMEOUT); + + if (expected == TRB_TRANSFER) + return NULL; + + printf("XHCI timeout on event type %d... cannot recover.\n", expected); + BUG(); +} + +/* + * Stops transfer processing for an endpoint and throws away all unprocessed + * TRBs by setting the xHC's dequeue pointer to our enqueue pointer. The next + * xhci_bulk_tx/xhci_ctrl_tx on this enpoint will add new transfers there and + * ring the doorbell, causing this endpoint to start working again. + * (Careful: This will BUG() when there was no transfer in progress. Shouldn't + * happen in practice for current uses and is too complicated to fix right now.) + */ +static void abort_td(struct usb_device *udev, int ep_index) +{ + struct xhci_ctrl *ctrl = udev->controller; + struct xhci_ring *ring = ctrl->devs[udev->slot_id]->eps[ep_index].ring; + union xhci_trb *event; + u32 field; + + xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING); + + event = xhci_wait_for_event(ctrl, TRB_TRANSFER); + field = le32_to_cpu(event->trans_event.flags); + BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id); + BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); + BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len + != COMP_STOP))); + xhci_acknowledge_event(ctrl); + + event = xhci_wait_for_event(ctrl, TRB_COMPLETION); + BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) + != udev->slot_id || GET_COMP_CODE(le32_to_cpu( + event->event_cmd.status)) != COMP_SUCCESS); + xhci_acknowledge_event(ctrl); + + xhci_queue_command(ctrl, (void *)((uintptr_t)ring->enqueue | + ring->cycle_state), udev->slot_id, ep_index, TRB_SET_DEQ); + event = xhci_wait_for_event(ctrl, TRB_COMPLETION); + BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) + != udev->slot_id || GET_COMP_CODE(le32_to_cpu( + event->event_cmd.status)) != COMP_SUCCESS); + xhci_acknowledge_event(ctrl); +} + +static void record_transfer_result(struct usb_device *udev, + union xhci_trb *event, int length) +{ + udev->act_len = min(length, length - + (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len))); + + switch (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))) { + case COMP_SUCCESS: + BUG_ON(udev->act_len != length); + /* fallthrough */ + case COMP_SHORT_TX: + udev->status = 0; + break; + case COMP_STALL: + udev->status = USB_ST_STALLED; + break; + case COMP_DB_ERR: + case COMP_TRB_ERR: + udev->status = USB_ST_BUF_ERR; + break; + case COMP_BABBLE: + udev->status = USB_ST_BABBLE_DET; + break; + default: + udev->status = 0x80; /* USB_ST_TOO_LAZY_TO_MAKE_A_NEW_MACRO */ + } +} + +/**** Bulk and Control transfer methods ****/ +/** + * Queues up the BULK Request + * + * @param udev pointer to the USB device structure + * @param pipe contains the DIR_IN or OUT , devnum + * @param length length of the buffer + * @param buffer buffer to be read/written based on the request + * @return returns 0 if successful else -1 on failure + */ +int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, + int length, void *buffer) +{ + int num_trbs = 0; + struct xhci_generic_trb *start_trb; + bool first_trb = 0; + int start_cycle; + u32 field = 0; + u32 length_field = 0; + struct xhci_ctrl *ctrl = udev->controller; + int slot_id = udev->slot_id; + int ep_index; + struct xhci_virt_device *virt_dev; + struct xhci_ep_ctx *ep_ctx; + struct xhci_ring *ring; /* EP transfer ring */ + union xhci_trb *event; + + int running_total, trb_buff_len; + unsigned int total_packet_count; + int maxpacketsize; + u64 addr; + int ret; + u32 trb_fields[4]; + u64 val_64 = (uintptr_t)buffer; + + debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n", + udev, pipe, buffer, length); + + ep_index = usb_pipe_ep_index(pipe); + virt_dev = ctrl->devs[slot_id]; + + xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes, + virt_dev->out_ctx->size); + + ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index); + + ring = virt_dev->eps[ep_index].ring; + /* + * How much data is (potentially) left before the 64KB boundary? + * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec) + * that the buffer should not span 64KB boundary. if so + * we send request in more than 1 TRB by chaining them. + */ + running_total = TRB_MAX_BUFF_SIZE - + (lower_32_bits(val_64) & (TRB_MAX_BUFF_SIZE - 1)); + trb_buff_len = running_total; + running_total &= TRB_MAX_BUFF_SIZE - 1; + + /* + * If there's some data on this 64KB chunk, or we have to send a + * zero-length transfer, we need at least one TRB + */ + if (running_total != 0 || length == 0) + num_trbs++; + + /* How many more 64KB chunks to transfer, how many more TRBs? */ + while (running_total < length) { + num_trbs++; + running_total += TRB_MAX_BUFF_SIZE; + } + + /* + * XXX: Calling routine prepare_ring() called in place of + * prepare_trasfer() as there in 'Linux' since we are not + * maintaining multiple TDs/transfer at the same time. + */ + ret = prepare_ring(ctrl, ring, + le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK); + if (ret < 0) + return ret; + + /* + * Don't give the first TRB to the hardware (by toggling the cycle bit) + * until we've finished creating all the other TRBs. The ring's cycle + * state may change as we enqueue the other TRBs, so save it too. + */ + start_trb = &ring->enqueue->generic; + start_cycle = ring->cycle_state; + + running_total = 0; + maxpacketsize = usb_maxpacket(udev, pipe); + + total_packet_count = DIV_ROUND_UP(length, maxpacketsize); + + /* How much data is in the first TRB? */ + /* + * How much data is (potentially) left before the 64KB boundary? + * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec) + * that the buffer should not span 64KB boundary. if so + * we send request in more than 1 TRB by chaining them. + */ + addr = val_64; + + if (trb_buff_len > length) + trb_buff_len = length; + + first_trb = true; + + /* flush the buffer before use */ + xhci_flush_cache((uint32_t)buffer, length); + + /* Queue the first TRB, even if it's zero-length */ + do { + u32 remainder = 0; + field = 0; + /* Don't change the cycle bit of the first TRB until later */ + if (first_trb) { + first_trb = false; + if (start_cycle == 0) + field |= TRB_CYCLE; + } else { + field |= ring->cycle_state; + } + + /* + * Chain all the TRBs together; clear the chain bit in the last + * TRB to indicate it's the last TRB in the chain. + */ + if (num_trbs > 1) + field |= TRB_CHAIN; + else + field |= TRB_IOC; + + /* Only set interrupt on short packet for IN endpoints */ + if (usb_pipein(pipe)) + field |= TRB_ISP; + + /* Set the TRB length, TD size, and interrupter fields. */ + if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100) + remainder = xhci_td_remainder(length - running_total); + else + remainder = xhci_v1_0_td_remainder(running_total, + trb_buff_len, + total_packet_count, + maxpacketsize, + num_trbs - 1); + + length_field = ((trb_buff_len & TRB_LEN_MASK) | + remainder | + ((0 & TRB_INTR_TARGET_MASK) << + TRB_INTR_TARGET_SHIFT)); + + trb_fields[0] = lower_32_bits(addr); + trb_fields[1] = upper_32_bits(addr); + trb_fields[2] = length_field; + trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT); + + queue_trb(ctrl, ring, (num_trbs > 1), trb_fields); + + --num_trbs; + + running_total += trb_buff_len; + + /* Calculate length for next transfer */ + addr += trb_buff_len; + trb_buff_len = min((length - running_total), TRB_MAX_BUFF_SIZE); + } while (running_total < length); + + giveback_first_trb(udev, ep_index, start_cycle, start_trb); + + event = xhci_wait_for_event(ctrl, TRB_TRANSFER); + if (!event) { + debug("XHCI bulk transfer timed out, aborting...\n"); + abort_td(udev, ep_index); + udev->status = USB_ST_NAK_REC; /* closest thing to a timeout */ + udev->act_len = 0; + return -ETIMEDOUT; + } + field = le32_to_cpu(event->trans_event.flags); + + BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); + BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); + BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) - + buffer > (size_t)length); + + record_transfer_result(udev, event, length); + xhci_acknowledge_event(ctrl); + xhci_inval_cache((uint32_t)buffer, length); + + return (udev->status != USB_ST_NOT_PROC) ? 0 : -1; +} + +/** + * Queues up the Control Transfer Request + * + * @param udev pointer to the USB device structure + * @param pipe contains the DIR_IN or OUT , devnum + * @param req request type + * @param length length of the buffer + * @param buffer buffer to be read/written based on the request + * @return returns 0 if successful else error code on failure + */ +int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, + struct devrequest *req, int length, + void *buffer) +{ + int ret; + int start_cycle; + int num_trbs; + u32 field; + u32 length_field; + u64 buf_64 = 0; + struct xhci_generic_trb *start_trb; + struct xhci_ctrl *ctrl = udev->controller; + int slot_id = udev->slot_id; + int ep_index; + u32 trb_fields[4]; + struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; + struct xhci_ring *ep_ring; + union xhci_trb *event; + + debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", + req->request, req->request, + req->requesttype, req->requesttype, + le16_to_cpu(req->value), le16_to_cpu(req->value), + le16_to_cpu(req->index)); + + ep_index = usb_pipe_ep_index(pipe); + + ep_ring = virt_dev->eps[ep_index].ring; + + /* + * Check to see if the max packet size for the default control + * endpoint changed during FS device enumeration + */ + if (udev->speed == USB_SPEED_FULL) { + ret = xhci_check_maxpacket(udev); + if (ret < 0) + return ret; + } + + xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes, + virt_dev->out_ctx->size); + + struct xhci_ep_ctx *ep_ctx = NULL; + ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index); + + /* 1 TRB for setup, 1 for status */ + num_trbs = 2; + /* + * Don't need to check if we need additional event data and normal TRBs, + * since data in control transfers will never get bigger than 16MB + * XXX: can we get a buffer that crosses 64KB boundaries? + */ + + if (length > 0) + num_trbs++; + /* + * XXX: Calling routine prepare_ring() called in place of + * prepare_trasfer() as there in 'Linux' since we are not + * maintaining multiple TDs/transfer at the same time. + */ + ret = prepare_ring(ctrl, ep_ring, + le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK); + + if (ret < 0) + return ret; + + /* + * Don't give the first TRB to the hardware (by toggling the cycle bit) + * until we've finished creating all the other TRBs. The ring's cycle + * state may change as we enqueue the other TRBs, so save it too. + */ + start_trb = &ep_ring->enqueue->generic; + start_cycle = ep_ring->cycle_state; + + debug("start_trb %p, start_cycle %d\n", start_trb, start_cycle); + + /* Queue setup TRB - see section 6.4.1.2.1 */ + /* FIXME better way to translate setup_packet into two u32 fields? */ + field = 0; + field |= TRB_IDT | (TRB_SETUP << TRB_TYPE_SHIFT); + if (start_cycle == 0) + field |= 0x1; + + /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ + if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) == 0x100) { + if (length > 0) { + if (req->requesttype & USB_DIR_IN) + field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT); + else + field |= (TRB_DATA_OUT << TRB_TX_TYPE_SHIFT); + } + } + + debug("req->requesttype = %d, req->request = %d," + "le16_to_cpu(req->value) = %d," + "le16_to_cpu(req->index) = %d," + "le16_to_cpu(req->length) = %d\n", + req->requesttype, req->request, le16_to_cpu(req->value), + le16_to_cpu(req->index), le16_to_cpu(req->length)); + + trb_fields[0] = req->requesttype | req->request << 8 | + le16_to_cpu(req->value) << 16; + trb_fields[1] = le16_to_cpu(req->index) | + le16_to_cpu(req->length) << 16; + /* TRB_LEN | (TRB_INTR_TARGET) */ + trb_fields[2] = (8 | ((0 & TRB_INTR_TARGET_MASK) << + TRB_INTR_TARGET_SHIFT)); + /* Immediate data in pointer */ + trb_fields[3] = field; + queue_trb(ctrl, ep_ring, true, trb_fields); + + /* Re-initializing field to zero */ + field = 0; + /* If there's data, queue data TRBs */ + /* Only set interrupt on short packet for IN endpoints */ + if (usb_pipein(pipe)) + field = TRB_ISP | (TRB_DATA << TRB_TYPE_SHIFT); + else + field = (TRB_DATA << TRB_TYPE_SHIFT); + + length_field = (length & TRB_LEN_MASK) | xhci_td_remainder(length) | + ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); + debug("length_field = %d, length = %d," + "xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n", + length_field, (length & TRB_LEN_MASK), + xhci_td_remainder(length), 0); + + if (length > 0) { + if (req->requesttype & USB_DIR_IN) + field |= TRB_DIR_IN; + buf_64 = (uintptr_t)buffer; + + trb_fields[0] = lower_32_bits(buf_64); + trb_fields[1] = upper_32_bits(buf_64); + trb_fields[2] = length_field; + trb_fields[3] = field | ep_ring->cycle_state; + + xhci_flush_cache((uint32_t)buffer, length); + queue_trb(ctrl, ep_ring, true, trb_fields); + } + + /* + * Queue status TRB - + * see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 + */ + + /* If the device sent data, the status stage is an OUT transfer */ + field = 0; + if (length > 0 && req->requesttype & USB_DIR_IN) + field = 0; + else + field = TRB_DIR_IN; + + trb_fields[0] = 0; + trb_fields[1] = 0; + trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); + /* Event on completion */ + trb_fields[3] = field | TRB_IOC | + (TRB_STATUS << TRB_TYPE_SHIFT) | + ep_ring->cycle_state; + + queue_trb(ctrl, ep_ring, false, trb_fields); + + giveback_first_trb(udev, ep_index, start_cycle, start_trb); + + event = xhci_wait_for_event(ctrl, TRB_TRANSFER); + if (!event) + goto abort; + field = le32_to_cpu(event->trans_event.flags); + + BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); + BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); + + record_transfer_result(udev, event, length); + xhci_acknowledge_event(ctrl); + + /* Invalidate buffer to make it available to usb-core */ + if (length > 0) + xhci_inval_cache((uint32_t)buffer, length); + + if (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len)) + == COMP_SHORT_TX) { + /* Short data stage, clear up additional status stage event */ + event = xhci_wait_for_event(ctrl, TRB_TRANSFER); + if (!event) + goto abort; + BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); + BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); + xhci_acknowledge_event(ctrl); + } + + return (udev->status != USB_ST_NOT_PROC) ? 0 : -1; + +abort: + debug("XHCI control transfer timed out, aborting...\n"); + abort_td(udev, ep_index); + udev->status = USB_ST_NAK_REC; + udev->act_len = 0; + return -ETIMEDOUT; +} diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c new file mode 100644 index 0000000000..87f2972cb2 --- /dev/null +++ b/drivers/usb/host/xhci.c @@ -0,0 +1,1030 @@ +/* + * USB HOST XHCI Controller stack + * + * Based on xHCI host controller driver in linux-kernel + * by Sarah Sharp. + * + * Copyright (C) 2008 Intel Corp. + * Author: Sarah Sharp + * + * Copyright (C) 2013 Samsung Electronics Co.Ltd + * Authors: Vivek Gautam + * Vikas Sajjan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/** + * This file gives the xhci stack for usb3.0 looking into + * xhci specification Rev1.0 (5/21/10). + * The quirk devices support hasn't been given yet. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "xhci.h" + +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +static struct descriptor { + struct usb_hub_descriptor hub; + struct usb_device_descriptor device; + struct usb_config_descriptor config; + struct usb_interface_descriptor interface; + struct usb_endpoint_descriptor endpoint; + struct usb_ss_ep_comp_descriptor ep_companion; +} __attribute__ ((packed)) descriptor = { + { + 0xc, /* bDescLength */ + 0x2a, /* bDescriptorType: hub descriptor */ + 2, /* bNrPorts -- runtime modified */ + cpu_to_le16(0x8), /* wHubCharacteristics */ + 10, /* bPwrOn2PwrGood */ + 0, /* bHubCntrCurrent */ + {}, /* Device removable */ + {} /* at most 7 ports! XXX */ + }, + { + 0x12, /* bLength */ + 1, /* bDescriptorType: UDESC_DEVICE */ + cpu_to_le16(0x0300), /* bcdUSB: v3.0 */ + 9, /* bDeviceClass: UDCLASS_HUB */ + 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ + 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */ + 9, /* bMaxPacketSize: 512 bytes 2^9 */ + 0x0000, /* idVendor */ + 0x0000, /* idProduct */ + cpu_to_le16(0x0100), /* bcdDevice */ + 1, /* iManufacturer */ + 2, /* iProduct */ + 0, /* iSerialNumber */ + 1 /* bNumConfigurations: 1 */ + }, + { + 0x9, + 2, /* bDescriptorType: UDESC_CONFIG */ + cpu_to_le16(0x1f), /* includes SS endpoint descriptor */ + 1, /* bNumInterface */ + 1, /* bConfigurationValue */ + 0, /* iConfiguration */ + 0x40, /* bmAttributes: UC_SELF_POWER */ + 0 /* bMaxPower */ + }, + { + 0x9, /* bLength */ + 4, /* bDescriptorType: UDESC_INTERFACE */ + 0, /* bInterfaceNumber */ + 0, /* bAlternateSetting */ + 1, /* bNumEndpoints */ + 9, /* bInterfaceClass: UICLASS_HUB */ + 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ + 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ + 0 /* iInterface */ + }, + { + 0x7, /* bLength */ + 5, /* bDescriptorType: UDESC_ENDPOINT */ + 0x81, /* bEndpointAddress: IN endpoint 1 */ + 3, /* bmAttributes: UE_INTERRUPT */ + 8, /* wMaxPacketSize */ + 255 /* bInterval */ + }, + { + 0x06, /* ss_bLength */ + 0x30, /* ss_bDescriptorType: SS EP Companion */ + 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */ + /* ss_bmAttributes: 1 packet per service interval */ + 0x00, + /* ss_wBytesPerInterval: 15 bits for max 15 ports */ + cpu_to_le16(0x02), + }, +}; + +static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; + +/** + * Waits for as per specified amount of time + * for the "result" to match with "done" + * + * @param ptr pointer to the register to be read + * @param mask mask for the value read + * @param done value to be campared with result + * @param usec time to wait till + * @return 0 if handshake is success else < 0 on failure + */ +static int handshake(uint32_t volatile *ptr, uint32_t mask, + uint32_t done, int usec) +{ + uint32_t result; + + do { + result = xhci_readl(ptr); + if (result == ~(uint32_t)0) + return -ENODEV; + result &= mask; + if (result == done) + return 0; + usec--; + udelay(1); + } while (usec > 0); + + return -ETIMEDOUT; +} + +/** + * Set the run bit and wait for the host to be running. + * + * @param hcor pointer to host controller operation registers + * @return status of the Handshake + */ +static int xhci_start(struct xhci_hcor *hcor) +{ + u32 temp; + int ret; + + puts("Starting the controller\n"); + temp = xhci_readl(&hcor->or_usbcmd); + temp |= (CMD_RUN); + xhci_writel(&hcor->or_usbcmd, temp); + + /* + * Wait for the HCHalted Status bit to be 0 to indicate the host is + * running. + */ + ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC); + if (ret) + debug("Host took too long to start, " + "waited %u microseconds.\n", + XHCI_MAX_HALT_USEC); + return ret; +} + +/** + * Resets the XHCI Controller + * + * @param hcor pointer to host controller operation registers + * @return -EBUSY if XHCI Controller is not halted else status of handshake + */ +int xhci_reset(struct xhci_hcor *hcor) +{ + u32 cmd; + u32 state; + int ret; + + /* Halting the Host first */ + debug("// Halt the HC\n"); + state = xhci_readl(&hcor->or_usbsts) & STS_HALT; + if (!state) { + cmd = xhci_readl(&hcor->or_usbcmd); + cmd &= ~CMD_RUN; + xhci_writel(&hcor->or_usbcmd, cmd); + } + + ret = handshake(&hcor->or_usbsts, + STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); + if (ret) { + printf("Host not halted after %u microseconds.\n", + XHCI_MAX_HALT_USEC); + return -EBUSY; + } + + debug("// Reset the HC\n"); + cmd = xhci_readl(&hcor->or_usbcmd); + cmd |= CMD_RESET; + xhci_writel(&hcor->or_usbcmd, cmd); + + ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC); + if (ret) + return ret; + + /* + * xHCI cannot write to any doorbells or operational registers other + * than status until the "Controller Not Ready" flag is cleared. + */ + return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC); +} + +/** + * Used for passing endpoint bitmasks between the core and HCDs. + * Find the index for an endpoint given its descriptor. + * Use the return value to right shift 1 for the bitmask. + * + * Index = (epnum * 2) + direction - 1, + * where direction = 0 for OUT, 1 for IN. + * For control endpoints, the IN index is used (OUT index is unused), so + * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) + * + * @param desc USB enpdoint Descriptor + * @return index of the Endpoint + */ +static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc) +{ + unsigned int index; + + if (usb_endpoint_xfer_control(desc)) + index = (unsigned int)(usb_endpoint_num(desc) * 2); + else + index = (unsigned int)((usb_endpoint_num(desc) * 2) - + (usb_endpoint_dir_in(desc) ? 0 : 1)); + + return index; +} + +/** + * Issue a configure endpoint command or evaluate context command + * and wait for it to finish. + * + * @param udev pointer to the Device Data Structure + * @param ctx_change flag to indicate the Context has changed or NOT + * @return 0 on success, -1 on failure + */ +static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change) +{ + struct xhci_container_ctx *in_ctx; + struct xhci_virt_device *virt_dev; + struct xhci_ctrl *ctrl = udev->controller; + union xhci_trb *event; + + virt_dev = ctrl->devs[udev->slot_id]; + in_ctx = virt_dev->in_ctx; + + xhci_flush_cache((uint32_t)in_ctx->bytes, in_ctx->size); + xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0, + ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP); + event = xhci_wait_for_event(ctrl, TRB_COMPLETION); + BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) + != udev->slot_id); + + switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) { + case COMP_SUCCESS: + debug("Successful %s command\n", + ctx_change ? "Evaluate Context" : "Configure Endpoint"); + break; + default: + printf("ERROR: %s command returned completion code %d.\n", + ctx_change ? "Evaluate Context" : "Configure Endpoint", + GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))); + return -EINVAL; + } + + xhci_acknowledge_event(ctrl); + + return 0; +} + +/** + * Configure the endpoint, programming the device contexts. + * + * @param udev pointer to the USB device structure + * @return returns the status of the xhci_configure_endpoints + */ +static int xhci_set_configuration(struct usb_device *udev) +{ + struct xhci_container_ctx *in_ctx; + struct xhci_container_ctx *out_ctx; + struct xhci_input_control_ctx *ctrl_ctx; + struct xhci_slot_ctx *slot_ctx; + struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM]; + int cur_ep; + int max_ep_flag = 0; + int ep_index; + unsigned int dir; + unsigned int ep_type; + struct xhci_ctrl *ctrl = udev->controller; + int num_of_ep; + int ep_flag = 0; + u64 trb_64 = 0; + int slot_id = udev->slot_id; + struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; + struct usb_interface *ifdesc; + + out_ctx = virt_dev->out_ctx; + in_ctx = virt_dev->in_ctx; + + num_of_ep = udev->config.if_desc[0].no_of_ep; + ifdesc = &udev->config.if_desc[0]; + + ctrl_ctx = xhci_get_input_control_ctx(in_ctx); + /* Zero the input context control */ + ctrl_ctx->add_flags = 0; + ctrl_ctx->drop_flags = 0; + + /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */ + for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { + ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]); + ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1)); + if (max_ep_flag < ep_flag) + max_ep_flag = ep_flag; + } + + xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size); + + /* slot context */ + xhci_slot_copy(ctrl, in_ctx, out_ctx); + slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); + slot_ctx->dev_info &= ~(LAST_CTX_MASK); + slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0); + + xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0); + + /* filling up ep contexts */ + for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { + struct usb_endpoint_descriptor *endpt_desc = NULL; + + endpt_desc = &ifdesc->ep_desc[cur_ep]; + trb_64 = 0; + + ep_index = xhci_get_ep_index(endpt_desc); + ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); + + /* Allocate the ep rings */ + virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true); + if (!virt_dev->eps[ep_index].ring) + return -ENOMEM; + + /*NOTE: ep_desc[0] actually represents EP1 and so on */ + dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7); + ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2)); + ep_ctx[ep_index]->ep_info2 = + cpu_to_le32(ep_type << EP_TYPE_SHIFT); + ep_ctx[ep_index]->ep_info2 |= + cpu_to_le32(MAX_PACKET + (get_unaligned(&endpt_desc->wMaxPacketSize))); + + ep_ctx[ep_index]->ep_info2 |= + cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) | + ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT)); + + trb_64 = (uintptr_t) + virt_dev->eps[ep_index].ring->enqueue; + ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 | + virt_dev->eps[ep_index].ring->cycle_state); + } + + return xhci_configure_endpoints(udev, false); +} + +/** + * Issue an Address Device command (which will issue a SetAddress request to + * the device). + * + * @param udev pointer to the Device Data Structure + * @return 0 if successful else error code on failure + */ +static int xhci_address_device(struct usb_device *udev) +{ + int ret = 0; + struct xhci_ctrl *ctrl = udev->controller; + struct xhci_slot_ctx *slot_ctx; + struct xhci_input_control_ctx *ctrl_ctx; + struct xhci_virt_device *virt_dev; + int slot_id = udev->slot_id; + union xhci_trb *event; + + virt_dev = ctrl->devs[slot_id]; + + /* + * This is the first Set Address since device plug-in + * so setting up the slot context. + */ + debug("Setting up addressable devices\n"); + xhci_setup_addressable_virt_dev(udev); + + ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); + ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); + ctrl_ctx->drop_flags = 0; + + xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV); + event = xhci_wait_for_event(ctrl, TRB_COMPLETION); + BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id); + + switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) { + case COMP_CTX_STATE: + case COMP_EBADSLT: + printf("Setup ERROR: address device command for slot %d.\n", + slot_id); + ret = -EINVAL; + break; + case COMP_TX_ERR: + puts("Device not responding to set address.\n"); + ret = -EPROTO; + break; + case COMP_DEV_ERR: + puts("ERROR: Incompatible device" + "for address device command.\n"); + ret = -ENODEV; + break; + case COMP_SUCCESS: + debug("Successful Address Device command\n"); + udev->status = 0; + break; + default: + printf("ERROR: unexpected command completion code 0x%x.\n", + GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))); + ret = -EINVAL; + break; + } + + xhci_acknowledge_event(ctrl); + + if (ret < 0) + /* + * TODO: Unsuccessful Address Device command shall leave the + * slot in default state. So, issue Disable Slot command now. + */ + return ret; + + xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes, + virt_dev->out_ctx->size); + slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx); + + debug("xHC internal address is: %d\n", + le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); + + return 0; +} + +/** + * Issue Enable slot command to the controller to allocate + * device slot and assign the slot id. It fails if the xHC + * ran out of device slots, the Enable Slot command timed out, + * or allocating memory failed. + * + * @param udev pointer to the Device Data Structure + * @return Returns 0 on succes else return error code on failure + */ +int usb_alloc_device(struct usb_device *udev) +{ + union xhci_trb *event; + struct xhci_ctrl *ctrl = udev->controller; + int ret; + + /* + * Root hub will be first device to be initailized. + * If this device is root-hub, don't do any xHC related + * stuff. + */ + if (ctrl->rootdev == 0) { + udev->speed = USB_SPEED_SUPER; + return 0; + } + + xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT); + event = xhci_wait_for_event(ctrl, TRB_COMPLETION); + BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)) + != COMP_SUCCESS); + + udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)); + + xhci_acknowledge_event(ctrl); + + ret = xhci_alloc_virt_device(udev); + if (ret < 0) { + /* + * TODO: Unsuccessful Address Device command shall leave + * the slot in default. So, issue Disable Slot command now. + */ + puts("Could not allocate xHCI USB device data structures\n"); + return ret; + } + + return 0; +} + +/* + * Full speed devices may have a max packet size greater than 8 bytes, but the + * USB core doesn't know that until it reads the first 8 bytes of the + * descriptor. If the usb_device's max packet size changes after that point, + * we need to issue an evaluate context command and wait on it. + * + * @param udev pointer to the Device Data Structure + * @return returns the status of the xhci_configure_endpoints + */ +int xhci_check_maxpacket(struct usb_device *udev) +{ + struct xhci_ctrl *ctrl = udev->controller; + unsigned int slot_id = udev->slot_id; + int ep_index = 0; /* control endpoint */ + struct xhci_container_ctx *in_ctx; + struct xhci_container_ctx *out_ctx; + struct xhci_input_control_ctx *ctrl_ctx; + struct xhci_ep_ctx *ep_ctx; + int max_packet_size; + int hw_max_packet_size; + int ret = 0; + struct usb_interface *ifdesc; + + ifdesc = &udev->config.if_desc[0]; + + out_ctx = ctrl->devs[slot_id]->out_ctx; + xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size); + + ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index); + hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); + max_packet_size = usb_endpoint_maxp(&ifdesc->ep_desc[0]); + if (hw_max_packet_size != max_packet_size) { + debug("Max Packet Size for ep 0 changed.\n"); + debug("Max packet size in usb_device = %d\n", max_packet_size); + debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size); + debug("Issuing evaluate context command.\n"); + + /* Set up the modified control endpoint 0 */ + xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx, + ctrl->devs[slot_id]->out_ctx, ep_index); + in_ctx = ctrl->devs[slot_id]->in_ctx; + ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); + ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); + ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); + + /* + * Set up the input context flags for the command + * FIXME: This won't work if a non-default control endpoint + * changes max packet sizes. + */ + ctrl_ctx = xhci_get_input_control_ctx(in_ctx); + ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); + ctrl_ctx->drop_flags = 0; + + ret = xhci_configure_endpoints(udev, true); + } + return ret; +} + +/** + * Clears the Change bits of the Port Status Register + * + * @param wValue request value + * @param wIndex request index + * @param addr address of posrt status register + * @param port_status state of port status register + * @return none + */ +static void xhci_clear_port_change_bit(u16 wValue, + u16 wIndex, volatile uint32_t *addr, u32 port_status) +{ + char *port_change_bit; + u32 status; + + switch (wValue) { + case USB_PORT_FEAT_C_RESET: + status = PORT_RC; + port_change_bit = "reset"; + break; + case USB_PORT_FEAT_C_CONNECTION: + status = PORT_CSC; + port_change_bit = "connect"; + break; + case USB_PORT_FEAT_C_OVER_CURRENT: + status = PORT_OCC; + port_change_bit = "over-current"; + break; + case USB_PORT_FEAT_C_ENABLE: + status = PORT_PEC; + port_change_bit = "enable/disable"; + break; + case USB_PORT_FEAT_C_SUSPEND: + status = PORT_PLC; + port_change_bit = "suspend/resume"; + break; + default: + /* Should never happen */ + return; + } + + /* Change bits are all write 1 to clear */ + xhci_writel(addr, port_status | status); + + port_status = xhci_readl(addr); + debug("clear port %s change, actual port %d status = 0x%x\n", + port_change_bit, wIndex, port_status); +} + +/** + * Save Read Only (RO) bits and save read/write bits where + * writing a 0 clears the bit and writing a 1 sets the bit (RWS). + * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. + * + * @param state state of the Port Status and Control Regsiter + * @return a value that would result in the port being in the + * same state, if the value was written to the port + * status control register. + */ +static u32 xhci_port_state_to_neutral(u32 state) +{ + /* Save read-only status and port state */ + return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); +} + +/** + * Submits the Requests to the XHCI Host Controller + * + * @param udev pointer to the USB device structure + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @return returns 0 if successful else -1 on failure + */ +static int xhci_submit_root(struct usb_device *udev, unsigned long pipe, + void *buffer, struct devrequest *req) +{ + uint8_t tmpbuf[4]; + u16 typeReq; + void *srcptr = NULL; + int len, srclen; + uint32_t reg; + volatile uint32_t *status_reg; + struct xhci_ctrl *ctrl = udev->controller; + struct xhci_hcor *hcor = ctrl->hcor; + + if ((req->requesttype & USB_RT_PORT) && + le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) { + printf("The request port(%d) is not configured\n", + le16_to_cpu(req->index) - 1); + return -EINVAL; + } + + status_reg = (volatile uint32_t *) + (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc); + srclen = 0; + + typeReq = req->request | req->requesttype << 8; + + switch (typeReq) { + case DeviceRequest | USB_REQ_GET_DESCRIPTOR: + switch (le16_to_cpu(req->value) >> 8) { + case USB_DT_DEVICE: + debug("USB_DT_DEVICE request\n"); + srcptr = &descriptor.device; + srclen = 0x12; + break; + case USB_DT_CONFIG: + debug("USB_DT_CONFIG config\n"); + srcptr = &descriptor.config; + srclen = 0x19; + break; + case USB_DT_STRING: + debug("USB_DT_STRING config\n"); + switch (le16_to_cpu(req->value) & 0xff) { + case 0: /* Language */ + srcptr = "\4\3\11\4"; + srclen = 4; + break; + case 1: /* Vendor String */ + srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; + srclen = 14; + break; + case 2: /* Product Name */ + srcptr = "\52\3X\0H\0C\0I\0 " + "\0H\0o\0s\0t\0 " + "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; + srclen = 42; + break; + default: + printf("unknown value DT_STRING %x\n", + le16_to_cpu(req->value)); + goto unknown; + } + break; + default: + printf("unknown value %x\n", le16_to_cpu(req->value)); + goto unknown; + } + break; + case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): + switch (le16_to_cpu(req->value) >> 8) { + case USB_DT_HUB: + debug("USB_DT_HUB config\n"); + srcptr = &descriptor.hub; + srclen = 0x8; + break; + default: + printf("unknown value %x\n", le16_to_cpu(req->value)); + goto unknown; + } + break; + case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): + debug("USB_REQ_SET_ADDRESS\n"); + ctrl->rootdev = le16_to_cpu(req->value); + break; + case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: + /* Do nothing */ + break; + case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): + tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ + tmpbuf[1] = 0; + srcptr = tmpbuf; + srclen = 2; + break; + case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): + memset(tmpbuf, 0, 4); + reg = xhci_readl(status_reg); + if (reg & PORT_CONNECT) { + tmpbuf[0] |= USB_PORT_STAT_CONNECTION; + switch (reg & DEV_SPEED_MASK) { + case XDEV_FS: + debug("SPEED = FULLSPEED\n"); + break; + case XDEV_LS: + debug("SPEED = LOWSPEED\n"); + tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; + break; + case XDEV_HS: + debug("SPEED = HIGHSPEED\n"); + tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; + break; + case XDEV_SS: + debug("SPEED = SUPERSPEED\n"); + tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8; + break; + } + } + if (reg & PORT_PE) + tmpbuf[0] |= USB_PORT_STAT_ENABLE; + if ((reg & PORT_PLS_MASK) == XDEV_U3) + tmpbuf[0] |= USB_PORT_STAT_SUSPEND; + if (reg & PORT_OC) + tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; + if (reg & PORT_RESET) + tmpbuf[0] |= USB_PORT_STAT_RESET; + if (reg & PORT_POWER) + /* + * XXX: This Port power bit (for USB 3.0 hub) + * we are faking in USB 2.0 hub port status; + * since there's a change in bit positions in + * two: + * USB 2.0 port status PP is at position[8] + * USB 3.0 port status PP is at position[9] + * So, we are still keeping it at position [8] + */ + tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; + if (reg & PORT_CSC) + tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; + if (reg & PORT_PEC) + tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; + if (reg & PORT_OCC) + tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; + if (reg & PORT_RC) + tmpbuf[2] |= USB_PORT_STAT_C_RESET; + + srcptr = tmpbuf; + srclen = 4; + break; + case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): + reg = xhci_readl(status_reg); + reg = xhci_port_state_to_neutral(reg); + switch (le16_to_cpu(req->value)) { + case USB_PORT_FEAT_ENABLE: + reg |= PORT_PE; + xhci_writel(status_reg, reg); + break; + case USB_PORT_FEAT_POWER: + reg |= PORT_POWER; + xhci_writel(status_reg, reg); + break; + case USB_PORT_FEAT_RESET: + reg |= PORT_RESET; + xhci_writel(status_reg, reg); + break; + default: + printf("unknown feature %x\n", le16_to_cpu(req->value)); + goto unknown; + } + break; + case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): + reg = xhci_readl(status_reg); + reg = xhci_port_state_to_neutral(reg); + switch (le16_to_cpu(req->value)) { + case USB_PORT_FEAT_ENABLE: + reg &= ~PORT_PE; + break; + case USB_PORT_FEAT_POWER: + reg &= ~PORT_POWER; + break; + case USB_PORT_FEAT_C_RESET: + case USB_PORT_FEAT_C_CONNECTION: + case USB_PORT_FEAT_C_OVER_CURRENT: + case USB_PORT_FEAT_C_ENABLE: + xhci_clear_port_change_bit((le16_to_cpu(req->value)), + le16_to_cpu(req->index), + status_reg, reg); + break; + default: + printf("unknown feature %x\n", le16_to_cpu(req->value)); + goto unknown; + } + xhci_writel(status_reg, reg); + break; + default: + puts("Unknown request\n"); + goto unknown; + } + + debug("scrlen = %d\n req->length = %d\n", + srclen, le16_to_cpu(req->length)); + + len = min(srclen, (int)le16_to_cpu(req->length)); + + if (srcptr != NULL && len > 0) + memcpy(buffer, srcptr, len); + else + debug("Len is 0\n"); + + udev->act_len = len; + udev->status = 0; + + return 0; + +unknown: + udev->act_len = 0; + udev->status = USB_ST_STALLED; + + return -ENODEV; +} + +/** + * Submits the INT request to XHCI Host cotroller + * + * @param udev pointer to the USB device + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @param interval interval of the interrupt + * @return 0 + */ +int +submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer, + int length, int interval) +{ + /* + * TODO: Not addressing any interrupt type transfer requests + * Add support for it later. + */ + return -EINVAL; +} + +/** + * submit the BULK type of request to the USB Device + * + * @param udev pointer to the USB device + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @return returns 0 if successful else -1 on failure + */ +int +submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer, + int length) +{ + if (usb_pipetype(pipe) != PIPE_BULK) { + printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); + return -EINVAL; + } + + return xhci_bulk_tx(udev, pipe, length, buffer); +} + +/** + * submit the control type of request to the Root hub/Device based on the devnum + * + * @param udev pointer to the USB device + * @param pipe contains the DIR_IN or OUT , devnum + * @param buffer buffer to be read/written based on the request + * @param length length of the buffer + * @param setup Request type + * @return returns 0 if successful else -1 on failure + */ +int +submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer, + int length, struct devrequest *setup) +{ + struct xhci_ctrl *ctrl = udev->controller; + int ret = 0; + + if (usb_pipetype(pipe) != PIPE_CONTROL) { + printf("non-control pipe (type=%lu)", usb_pipetype(pipe)); + return -EINVAL; + } + + if (usb_pipedevice(pipe) == ctrl->rootdev) + return xhci_submit_root(udev, pipe, buffer, setup); + + if (setup->request == USB_REQ_SET_ADDRESS) + return xhci_address_device(udev); + + if (setup->request == USB_REQ_SET_CONFIGURATION) { + ret = xhci_set_configuration(udev); + if (ret) { + puts("Failed to configure xHCI endpoint\n"); + return ret; + } + } + + return xhci_ctrl_tx(udev, pipe, setup, length, buffer); +} + +/** + * Intialises the XHCI host controller + * and allocates the necessary data structures + * + * @param index index to the host controller data structure + * @return pointer to the intialised controller + */ +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) +{ + uint32_t val; + uint32_t val2; + uint32_t reg; + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + struct xhci_ctrl *ctrl; + + if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0) + return -ENODEV; + + if (xhci_reset(hcor) != 0) + return -ENODEV; + + ctrl = &xhcic[index]; + + ctrl->hccr = hccr; + ctrl->hcor = hcor; + + /* + * Program the Number of Device Slots Enabled field in the CONFIG + * register with the max value of slots the HC can handle. + */ + val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK); + val2 = xhci_readl(&hcor->or_config); + val |= (val2 & ~HCS_SLOTS_MASK); + xhci_writel(&hcor->or_config, val); + + /* initializing xhci data structures */ + if (xhci_mem_init(ctrl, hccr, hcor) < 0) + return -ENOMEM; + + reg = xhci_readl(&hccr->cr_hcsparams1); + descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >> + HCS_MAX_PORTS_SHIFT); + printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); + + /* Port Indicators */ + reg = xhci_readl(&hccr->cr_hccparams); + if (HCS_INDICATOR(reg)) + put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) + | 0x80, &descriptor.hub.wHubCharacteristics); + + /* Port Power Control */ + if (HCC_PPC(reg)) + put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) + | 0x01, &descriptor.hub.wHubCharacteristics); + + if (xhci_start(hcor)) { + xhci_reset(hcor); + return -ENODEV; + } + + /* Zero'ing IRQ control register and IRQ pending register */ + xhci_writel(&ctrl->ir_set->irq_control, 0x0); + xhci_writel(&ctrl->ir_set->irq_pending, 0x0); + + reg = HC_VERSION(xhci_readl(&hccr->cr_capbase)); + printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff); + + *controller = &xhcic[index]; + + return 0; +} + +/** + * Stops the XHCI host controller + * and cleans up all the related data structures + * + * @param index index to the host controller data structure + * @return none + */ +int usb_lowlevel_stop(int index) +{ + struct xhci_ctrl *ctrl = (xhcic + index); + u32 temp; + + xhci_reset(ctrl->hcor); + + debug("// Disabling event ring interrupts\n"); + temp = xhci_readl(&ctrl->hcor->or_usbsts); + xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT); + temp = xhci_readl(&ctrl->ir_set->irq_pending); + xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp)); + + xhci_hcd_stop(index); + + xhci_cleanup(ctrl); + + return 0; +} diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h new file mode 100644 index 0000000000..6685ed23de --- /dev/null +++ b/drivers/usb/host/xhci.h @@ -0,0 +1,1253 @@ +/* + * USB HOST XHCI Controller + * + * Based on xHCI host controller driver in linux-kernel + * by Sarah Sharp. + * + * Copyright (C) 2008 Intel Corp. + * Author: Sarah Sharp + * + * Copyright (C) 2013 Samsung Electronics Co.Ltd + * Authors: Vivek Gautam + * Vikas Sajjan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef HOST_XHCI_H_ +#define HOST_XHCI_H_ + +#include +#include +#include +#include + +#define MAX_EP_CTX_NUM 31 +#define XHCI_ALIGNMENT 64 +/* Generic timeout for XHCI events */ +#define XHCI_TIMEOUT 5000 +/* Max number of USB devices for any host controller - limit in section 6.1 */ +#define MAX_HC_SLOTS 256 +/* Section 5.3.3 - MaxPorts */ +#define MAX_HC_PORTS 127 + +/* Up to 16 ms to halt an HC */ +#define XHCI_MAX_HALT_USEC (16*1000) + +#define XHCI_MAX_RESET_USEC (250*1000) + +/* + * These bits are Read Only (RO) and should be saved and written to the + * registers: 0, 3, 10:13, 30 + * connect status, over-current status, port speed, and device removable. + * connect status and port speed are also sticky - meaning they're in + * the AUX well and they aren't changed by a hot, warm, or cold reset. + */ +#define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30)) +/* + * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: + * bits 5:8, 9, 14:15, 25:27 + * link state, port power, port indicator state, "wake on" enable state + */ +#define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25)) +/* + * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: + * bit 4 (port reset) + */ +#define XHCI_PORT_RW1S ((1 << 4)) +/* + * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: + * bits 1, 17, 18, 19, 20, 21, 22, 23 + * port enable/disable, and + * change bits: connect, PED, + * warm port reset changed (reserved zero for USB 2.0 ports), + * over-current, reset, link state, and L1 change + */ +#define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17)) +/* + * Bit 16 is RW, and writing a '1' to it causes the link state control to be + * latched in + */ +#define XHCI_PORT_RW ((1 << 16)) +/* + * These bits are Reserved Zero (RsvdZ) and zero should be written to them: + * bits 2, 24, 28:31 + */ +#define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28)) + +/* + * XHCI Register Space. + */ +struct xhci_hccr { + uint32_t cr_capbase; + uint32_t cr_hcsparams1; + uint32_t cr_hcsparams2; + uint32_t cr_hcsparams3; + uint32_t cr_hccparams; + uint32_t cr_dboff; + uint32_t cr_rtsoff; + +/* hc_capbase bitmasks */ +/* bits 7:0 - how long is the Capabilities register */ +#define HC_LENGTH(p) XHCI_HC_LENGTH(p) +/* bits 31:16 */ +#define HC_VERSION(p) (((p) >> 16) & 0xffff) + +/* HCSPARAMS1 - hcs_params1 - bitmasks */ +/* bits 0:7, Max Device Slots */ +#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) +#define HCS_SLOTS_MASK 0xff +/* bits 8:18, Max Interrupters */ +#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) +/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ +#define HCS_MAX_PORTS_SHIFT 24 +#define HCS_MAX_PORTS_MASK (0x7f << HCS_MAX_PORTS_SHIFT) +#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) + +/* HCSPARAMS2 - hcs_params2 - bitmasks */ +/* bits 0:3, frames or uframes that SW needs to queue transactions + * ahead of the HW to meet periodic deadlines */ +#define HCS_IST(p) (((p) >> 0) & 0xf) +/* bits 4:7, max number of Event Ring segments */ +#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) +/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ +/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ +#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) + +/* HCSPARAMS3 - hcs_params3 - bitmasks */ +/* bits 0:7, Max U1 to U0 latency for the roothub ports */ +#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) +/* bits 16:31, Max U2 to U0 latency for the roothub ports */ +#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) + +/* HCCPARAMS - hcc_params - bitmasks */ +/* true: HC can use 64-bit address pointers */ +#define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) +/* true: HC can do bandwidth negotiation */ +#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) +/* true: HC uses 64-byte Device Context structures + * FIXME 64-byte context structures aren't supported yet. + */ +#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) +/* true: HC has port power switches */ +#define HCC_PPC(p) ((p) & (1 << 3)) +/* true: HC has port indicators */ +#define HCS_INDICATOR(p) ((p) & (1 << 4)) +/* true: HC has Light HC Reset Capability */ +#define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) +/* true: HC supports latency tolerance messaging */ +#define HCC_LTC(p) ((p) & (1 << 6)) +/* true: no secondary Stream ID Support */ +#define HCC_NSS(p) ((p) & (1 << 7)) +/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ +#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) +/* Extended Capabilities pointer from PCI base - section 5.3.6 */ +#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) + +/* db_off bitmask - bits 0:1 reserved */ +#define DBOFF_MASK (~0x3) + +/* run_regs_off bitmask - bits 0:4 reserved */ +#define RTSOFF_MASK (~0x1f) + +}; + +struct xhci_hcor_port_regs { + volatile uint32_t or_portsc; + volatile uint32_t or_portpmsc; + volatile uint32_t or_portli; + volatile uint32_t reserved_3; +}; + +struct xhci_hcor { + volatile uint32_t or_usbcmd; + volatile uint32_t or_usbsts; + volatile uint32_t or_pagesize; + volatile uint32_t reserved_0[2]; + volatile uint32_t or_dnctrl; + volatile uint64_t or_crcr; + volatile uint32_t reserved_1[4]; + volatile uint64_t or_dcbaap; + volatile uint32_t or_config; + volatile uint32_t reserved_2[241]; + struct xhci_hcor_port_regs portregs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS]; + + uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS * 254]; +}; + +/* USBCMD - USB command - command bitmasks */ +/* start/stop HC execution - do not write unless HC is halted*/ +#define CMD_RUN XHCI_CMD_RUN +/* Reset HC - resets internal HC state machine and all registers (except + * PCI config regs). HC does NOT drive a USB reset on the downstream ports. + * The xHCI driver must reinitialize the xHC after setting this bit. + */ +#define CMD_RESET (1 << 1) +/* Event Interrupt Enable - a '1' allows interrupts from the host controller */ +#define CMD_EIE XHCI_CMD_EIE +/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ +#define CMD_HSEIE XHCI_CMD_HSEIE +/* bits 4:6 are reserved (and should be preserved on writes). */ +/* light reset (port status stays unchanged) - reset completed when this is 0 */ +#define CMD_LRESET (1 << 7) +/* host controller save/restore state. */ +#define CMD_CSS (1 << 8) +#define CMD_CRS (1 << 9) +/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ +#define CMD_EWE XHCI_CMD_EWE +/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root + * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. + * '0' means the xHC can power it off if all ports are in the disconnect, + * disabled, or powered-off state. + */ +#define CMD_PM_INDEX (1 << 11) +/* bits 12:31 are reserved (and should be preserved on writes). */ + +/* USBSTS - USB status - status bitmasks */ +/* HC not running - set to 1 when run/stop bit is cleared. */ +#define STS_HALT XHCI_STS_HALT +/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ +#define STS_FATAL (1 << 2) +/* event interrupt - clear this prior to clearing any IP flags in IR set*/ +#define STS_EINT (1 << 3) +/* port change detect */ +#define STS_PORT (1 << 4) +/* bits 5:7 reserved and zeroed */ +/* save state status - '1' means xHC is saving state */ +#define STS_SAVE (1 << 8) +/* restore state status - '1' means xHC is restoring state */ +#define STS_RESTORE (1 << 9) +/* true: save or restore error */ +#define STS_SRE (1 << 10) +/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ +#define STS_CNR XHCI_STS_CNR +/* true: internal Host Controller Error - SW needs to reset and reinitialize */ +#define STS_HCE (1 << 12) +/* bits 13:31 reserved and should be preserved */ + +/* + * DNCTRL - Device Notification Control Register - dev_notification bitmasks + * Generate a device notification event when the HC sees a transaction with a + * notification type that matches a bit set in this bit field. + */ +#define DEV_NOTE_MASK (0xffff) +#define ENABLE_DEV_NOTE(x) (1 << (x)) +/* Most of the device notification types should only be used for debug. + * SW does need to pay attention to function wake notifications. + */ +#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) + +/* CRCR - Command Ring Control Register - cmd_ring bitmasks */ +/* bit 0 is the command ring cycle state */ +/* stop ring operation after completion of the currently executing command */ +#define CMD_RING_PAUSE (1 << 1) +/* stop ring immediately - abort the currently executing command */ +#define CMD_RING_ABORT (1 << 2) +/* true: command ring is running */ +#define CMD_RING_RUNNING (1 << 3) +/* bits 4:5 reserved and should be preserved */ +/* Command Ring pointer - bit mask for the lower 32 bits. */ +#define CMD_RING_RSVD_BITS (0x3f) + +/* CONFIG - Configure Register - config_reg bitmasks */ +/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ +#define MAX_DEVS(p) ((p) & 0xff) +/* bits 8:31 - reserved and should be preserved */ + +/* PORTSC - Port Status and Control Register - port_status_base bitmasks */ +/* true: device connected */ +#define PORT_CONNECT (1 << 0) +/* true: port enabled */ +#define PORT_PE (1 << 1) +/* bit 2 reserved and zeroed */ +/* true: port has an over-current condition */ +#define PORT_OC (1 << 3) +/* true: port reset signaling asserted */ +#define PORT_RESET (1 << 4) +/* Port Link State - bits 5:8 + * A read gives the current link PM state of the port, + * a write with Link State Write Strobe set sets the link state. + */ +#define PORT_PLS_MASK (0xf << 5) +#define XDEV_U0 (0x0 << 5) +#define XDEV_U2 (0x2 << 5) +#define XDEV_U3 (0x3 << 5) +#define XDEV_RESUME (0xf << 5) +/* true: port has power (see HCC_PPC) */ +#define PORT_POWER (1 << 9) +/* bits 10:13 indicate device speed: + * 0 - undefined speed - port hasn't be initialized by a reset yet + * 1 - full speed + * 2 - low speed + * 3 - high speed + * 4 - super speed + * 5-15 reserved + */ +#define DEV_SPEED_MASK (0xf << 10) +#define XDEV_FS (0x1 << 10) +#define XDEV_LS (0x2 << 10) +#define XDEV_HS (0x3 << 10) +#define XDEV_SS (0x4 << 10) +#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) +#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) +#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) +#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) +#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) +/* Bits 20:23 in the Slot Context are the speed for the device */ +#define SLOT_SPEED_FS (XDEV_FS << 10) +#define SLOT_SPEED_LS (XDEV_LS << 10) +#define SLOT_SPEED_HS (XDEV_HS << 10) +#define SLOT_SPEED_SS (XDEV_SS << 10) +/* Port Indicator Control */ +#define PORT_LED_OFF (0 << 14) +#define PORT_LED_AMBER (1 << 14) +#define PORT_LED_GREEN (2 << 14) +#define PORT_LED_MASK (3 << 14) +/* Port Link State Write Strobe - set this when changing link state */ +#define PORT_LINK_STROBE (1 << 16) +/* true: connect status change */ +#define PORT_CSC (1 << 17) +/* true: port enable change */ +#define PORT_PEC (1 << 18) +/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port + * into an enabled state, and the device into the default state. A "warm" reset + * also resets the link, forcing the device through the link training sequence. + * SW can also look at the Port Reset register to see when warm reset is done. + */ +#define PORT_WRC (1 << 19) +/* true: over-current change */ +#define PORT_OCC (1 << 20) +/* true: reset change - 1 to 0 transition of PORT_RESET */ +#define PORT_RC (1 << 21) +/* port link status change - set on some port link state transitions: + * Transition Reason + * -------------------------------------------------------------------------- + * - U3 to Resume Wakeup signaling from a device + * - Resume to Recovery to U0 USB 3.0 device resume + * - Resume to U0 USB 2.0 device resume + * - U3 to Recovery to U0 Software resume of USB 3.0 device complete + * - U3 to U0 Software resume of USB 2.0 device complete + * - U2 to U0 L1 resume of USB 2.1 device complete + * - U0 to U0 (???) L1 entry rejection by USB 2.1 device + * - U0 to disabled L1 entry error with USB 2.1 device + * - Any state to inactive Error on USB 3.0 port + */ +#define PORT_PLC (1 << 22) +/* port configure error change - port failed to configure its link partner */ +#define PORT_CEC (1 << 23) +/* bit 24 reserved */ +/* wake on connect (enable) */ +#define PORT_WKCONN_E (1 << 25) +/* wake on disconnect (enable) */ +#define PORT_WKDISC_E (1 << 26) +/* wake on over-current (enable) */ +#define PORT_WKOC_E (1 << 27) +/* bits 28:29 reserved */ +/* true: device is removable - for USB 3.0 roothub emulation */ +#define PORT_DEV_REMOVE (1 << 30) +/* Initiate a warm port reset - complete when PORT_WRC is '1' */ +#define PORT_WR (1 << 31) + +/* We mark duplicate entries with -1 */ +#define DUPLICATE_ENTRY ((u8)(-1)) + +/* Port Power Management Status and Control - port_power_base bitmasks */ +/* Inactivity timer value for transitions into U1, in microseconds. + * Timeout can be up to 127us. 0xFF means an infinite timeout. + */ +#define PORT_U1_TIMEOUT(p) ((p) & 0xff) +/* Inactivity timer value for transitions into U2 */ +#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) +/* Bits 24:31 for port testing */ + +/* USB2 Protocol PORTSPMSC */ +#define PORT_L1S_MASK 7 +#define PORT_L1S_SUCCESS 1 +#define PORT_RWE (1 << 3) +#define PORT_HIRD(p) (((p) & 0xf) << 4) +#define PORT_HIRD_MASK (0xf << 4) +#define PORT_L1DS(p) (((p) & 0xff) << 8) +#define PORT_HLE (1 << 16) + +/** +* struct xhci_intr_reg - Interrupt Register Set +* @irq_pending: IMAN - Interrupt Management Register. Used to enable +* interrupts and check for pending interrupts. +* @irq_control: IMOD - Interrupt Moderation Register. +* Used to throttle interrupts. +* @erst_size: Number of segments in the + Event Ring Segment Table (ERST). +* @erst_base: ERST base address. +* @erst_dequeue: Event ring dequeue pointer. +* +* Each interrupter (defined by a MSI-X vector) has an event ring and an Event +* Ring Segment Table (ERST) associated with it. +* The event ring is comprised of multiple segments of the same size. +* The HC places events on the ring and "updates the Cycle bit in the TRBs to +* indicate to software the current position of the Enqueue Pointer." +* The HCD (Linux) processes those events and updates the dequeue pointer. +*/ +struct xhci_intr_reg { + volatile __le32 irq_pending; + volatile __le32 irq_control; + volatile __le32 erst_size; + volatile __le32 rsvd; + volatile __le64 erst_base; + volatile __le64 erst_dequeue; +}; + +/* irq_pending bitmasks */ +#define ER_IRQ_PENDING(p) ((p) & 0x1) +/* bits 2:31 need to be preserved */ +/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ +#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) +#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) +#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) + +/* irq_control bitmasks */ +/* Minimum interval between interrupts (in 250ns intervals). The interval + * between interrupts will be longer if there are no events on the event ring. + * Default is 4000 (1 ms). + */ +#define ER_IRQ_INTERVAL_MASK (0xffff) +/* Counter used to count down the time to the next interrupt - HW use only */ +#define ER_IRQ_COUNTER_MASK (0xffff << 16) + +/* erst_size bitmasks */ +/* Preserve bits 16:31 of erst_size */ +#define ERST_SIZE_MASK (0xffff << 16) + +/* erst_dequeue bitmasks */ +/* Dequeue ERST Segment Index (DESI) - Segment number (or alias) + * where the current dequeue pointer lies. This is an optional HW hint. + */ +#define ERST_DESI_MASK (0x7) +/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by + * a work queue (or delayed service routine)? + */ +#define ERST_EHB (1 << 3) +#define ERST_PTR_MASK (0xf) + +/** + * struct xhci_run_regs + * @microframe_index: MFINDEX - current microframe number + * + * Section 5.5 Host Controller Runtime Registers: + * "Software should read and write these registers using only Dword (32 bit) + * or larger accesses" + */ +struct xhci_run_regs { + __le32 microframe_index; + __le32 rsvd[7]; + struct xhci_intr_reg ir_set[128]; +}; + +/** + * struct doorbell_array + * + * Bits 0 - 7: Endpoint target + * Bits 8 - 15: RsvdZ + * Bits 16 - 31: Stream ID + * + * Section 5.6 + */ +struct xhci_doorbell_array { + volatile __le32 doorbell[256]; +}; + +#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) +#define DB_VALUE_HOST 0x00000000 + +/** + * struct xhci_protocol_caps + * @revision: major revision, minor revision, capability ID, + * and next capability pointer. + * @name_string: Four ASCII characters to say which spec this xHC + * follows, typically "USB ". + * @port_info: Port offset, count, and protocol-defined information. + */ +struct xhci_protocol_caps { + u32 revision; + u32 name_string; + u32 port_info; +}; + +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) +#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) + +/** + * struct xhci_container_ctx + * @type: Type of context. Used to calculated offsets to contained contexts. + * @size: Size of the context data + * @bytes: The raw context data given to HW + * @dma: dma address of the bytes + * + * Represents either a Device or Input context. Holds a pointer to the raw + * memory used for the context (bytes) and dma address of it (dma). + */ +struct xhci_container_ctx { + unsigned type; +#define XHCI_CTX_TYPE_DEVICE 0x1 +#define XHCI_CTX_TYPE_INPUT 0x2 + + int size; + u8 *bytes; +}; + +/** + * struct xhci_slot_ctx + * @dev_info: Route string, device speed, hub info, and last valid endpoint + * @dev_info2: Max exit latency for device number, root hub port number + * @tt_info: tt_info is used to construct split transaction tokens + * @dev_state: slot state and device address + * + * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context + * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes + * reserved at the end of the slot context for HC internal use. + */ +struct xhci_slot_ctx { + __le32 dev_info; + __le32 dev_info2; + __le32 tt_info; + __le32 dev_state; + /* offset 0x10 to 0x1f reserved for HC internal use */ + __le32 reserved[4]; +}; + +/* dev_info bitmasks */ +/* Route String - 0:19 */ +#define ROUTE_STRING_MASK (0xfffff) +/* Device speed - values defined by PORTSC Device Speed field - 20:23 */ +#define DEV_SPEED (0xf << 20) +/* bit 24 reserved */ +/* Is this LS/FS device connected through a HS hub? - bit 25 */ +#define DEV_MTT (0x1 << 25) +/* Set if the device is a hub - bit 26 */ +#define DEV_HUB (0x1 << 26) +/* Index of the last valid endpoint context in this device context - 27:31 */ +#define LAST_CTX_MASK (0x1f << 27) +#define LAST_CTX(p) ((p) << 27) +#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) +#define SLOT_FLAG (1 << 0) +#define EP0_FLAG (1 << 1) + +/* dev_info2 bitmasks */ +/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ +#define MAX_EXIT (0xffff) +/* Root hub port number that is needed to access the USB device */ +#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) +#define ROOT_HUB_PORT_MASK (0xff) +#define ROOT_HUB_PORT_SHIFT (16) +#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) +/* Maximum number of ports under a hub device */ +#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) + +/* tt_info bitmasks */ +/* + * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub + * The Slot ID of the hub that isolates the high speed signaling from + * this low or full-speed device. '0' if attached to root hub port. + */ +#define TT_SLOT (0xff) +/* + * The number of the downstream facing port of the high-speed hub + * '0' if the device is not low or full speed. + */ +#define TT_PORT (0xff << 8) +#define TT_THINK_TIME(p) (((p) & 0x3) << 16) + +/* dev_state bitmasks */ +/* USB device address - assigned by the HC */ +#define DEV_ADDR_MASK (0xff) +/* bits 8:26 reserved */ +/* Slot state */ +#define SLOT_STATE (0x1f << 27) +#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) + +#define SLOT_STATE_DISABLED 0 +#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED +#define SLOT_STATE_DEFAULT 1 +#define SLOT_STATE_ADDRESSED 2 +#define SLOT_STATE_CONFIGURED 3 + +/** + * struct xhci_ep_ctx + * @ep_info: endpoint state, streams, mult, and interval information. + * @ep_info2: information on endpoint type, max packet size, max burst size, + * error count, and whether the HC will force an event for all + * transactions. + * @deq: 64-bit ring dequeue pointer address. If the endpoint only + * defines one stream, this points to the endpoint transfer ring. + * Otherwise, it points to a stream context array, which has a + * ring pointer for each flow. + * @tx_info: + * Average TRB lengths for the endpoint ring and + * max payload within an Endpoint Service Interval Time (ESIT). + * + * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context + * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes + * reserved at the end of the endpoint context for HC internal use. + */ +struct xhci_ep_ctx { + __le32 ep_info; + __le32 ep_info2; + __le64 deq; + __le32 tx_info; + /* offset 0x14 - 0x1f reserved for HC internal use */ + __le32 reserved[3]; +}; + +/* ep_info bitmasks */ +/* + * Endpoint State - bits 0:2 + * 0 - disabled + * 1 - running + * 2 - halted due to halt condition - ok to manipulate endpoint ring + * 3 - stopped + * 4 - TRB error + * 5-7 - reserved + */ +#define EP_STATE_MASK (0xf) +#define EP_STATE_DISABLED 0 +#define EP_STATE_RUNNING 1 +#define EP_STATE_HALTED 2 +#define EP_STATE_STOPPED 3 +#define EP_STATE_ERROR 4 +/* Mult - Max number of burtst within an interval, in EP companion desc. */ +#define EP_MULT(p) (((p) & 0x3) << 8) +#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) +/* bits 10:14 are Max Primary Streams */ +/* bit 15 is Linear Stream Array */ +/* Interval - period between requests to an endpoint - 125u increments. */ +#define EP_INTERVAL(p) (((p) & 0xff) << 16) +#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) +#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) +#define EP_MAXPSTREAMS_MASK (0x1f << 10) +#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) +/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ +#define EP_HAS_LSA (1 << 15) + +/* ep_info2 bitmasks */ +/* + * Force Event - generate transfer events for all TRBs for this endpoint + * This will tell the HC to ignore the IOC and ISP flags (for debugging only). + */ +#define FORCE_EVENT (0x1) +#define ERROR_COUNT(p) (((p) & 0x3) << 1) +#define ERROR_COUNT_SHIFT (1) +#define ERROR_COUNT_MASK (0x3) +#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) +#define EP_TYPE(p) ((p) << 3) +#define EP_TYPE_SHIFT (3) +#define ISOC_OUT_EP 1 +#define BULK_OUT_EP 2 +#define INT_OUT_EP 3 +#define CTRL_EP 4 +#define ISOC_IN_EP 5 +#define BULK_IN_EP 6 +#define INT_IN_EP 7 +/* bit 6 reserved */ +/* bit 7 is Host Initiate Disable - for disabling stream selection */ +#define MAX_BURST(p) (((p)&0xff) << 8) +#define MAX_BURST_MASK (0xff) +#define MAX_BURST_SHIFT (8) +#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) +#define MAX_PACKET(p) (((p)&0xffff) << 16) +#define MAX_PACKET_MASK (0xffff) +#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) +#define MAX_PACKET_SHIFT (16) + +/* Get max packet size from ep desc. Bit 10..0 specify the max packet size. + * USB2.0 spec 9.6.6. + */ +#define GET_MAX_PACKET(p) ((p) & 0x7ff) + +/* tx_info bitmasks */ +#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) +#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) +#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) + +/* deq bitmasks */ +#define EP_CTX_CYCLE_MASK (1 << 0) + + +/** + * struct xhci_input_control_context + * Input control context; see section 6.2.5. + * + * @drop_context: set the bit of the endpoint context you want to disable + * @add_context: set the bit of the endpoint context you want to enable + */ +struct xhci_input_control_ctx { + volatile __le32 drop_flags; + volatile __le32 add_flags; + __le32 rsvd2[6]; +}; + + +/** + * struct xhci_device_context_array + * @dev_context_ptr array of 64-bit DMA addresses for device contexts + */ +struct xhci_device_context_array { + /* 64-bit device addresses; we only write 32-bit addresses */ + __le64 dev_context_ptrs[MAX_HC_SLOTS]; +}; +/* TODO: write function to set the 64-bit device DMA address */ +/* + * TODO: change this to be dynamically sized at HC mem init time since the HC + * might not be able to handle the maximum number of devices possible. + */ + + +struct xhci_transfer_event { + /* 64-bit buffer address, or immediate data */ + __le64 buffer; + __le32 transfer_len; + /* This field is interpreted differently based on the type of TRB */ + volatile __le32 flags; +}; + +/* Transfer event TRB length bit mask */ +/* bits 0:23 */ +#define EVENT_TRB_LEN(p) ((p) & 0xffffff) + +/** Transfer Event bit fields **/ +#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) + +/* Completion Code - only applicable for some types of TRBs */ +#define COMP_CODE_MASK (0xff << 24) +#define COMP_CODE_SHIFT (24) +#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) + +typedef enum { + COMP_SUCCESS = 1, + /* Data Buffer Error */ + COMP_DB_ERR, /* 2 */ + /* Babble Detected Error */ + COMP_BABBLE, /* 3 */ + /* USB Transaction Error */ + COMP_TX_ERR, /* 4 */ + /* TRB Error - some TRB field is invalid */ + COMP_TRB_ERR, /* 5 */ + /* Stall Error - USB device is stalled */ + COMP_STALL, /* 6 */ + /* Resource Error - HC doesn't have memory for that device configuration */ + COMP_ENOMEM, /* 7 */ + /* Bandwidth Error - not enough room in schedule for this dev config */ + COMP_BW_ERR, /* 8 */ + /* No Slots Available Error - HC ran out of device slots */ + COMP_ENOSLOTS, /* 9 */ + /* Invalid Stream Type Error */ + COMP_STREAM_ERR, /* 10 */ + /* Slot Not Enabled Error - doorbell rung for disabled device slot */ + COMP_EBADSLT, /* 11 */ + /* Endpoint Not Enabled Error */ + COMP_EBADEP,/* 12 */ + /* Short Packet */ + COMP_SHORT_TX, /* 13 */ + /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ + COMP_UNDERRUN, /* 14 */ + /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ + COMP_OVERRUN, /* 15 */ + /* Virtual Function Event Ring Full Error */ + COMP_VF_FULL, /* 16 */ + /* Parameter Error - Context parameter is invalid */ + COMP_EINVAL, /* 17 */ + /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ + COMP_BW_OVER,/* 18 */ + /* Context State Error - illegal context state transition requested */ + COMP_CTX_STATE,/* 19 */ + /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ + COMP_PING_ERR,/* 20 */ + /* Event Ring is full */ + COMP_ER_FULL,/* 21 */ + /* Incompatible Device Error */ + COMP_DEV_ERR,/* 22 */ + /* Missed Service Error - HC couldn't service an isoc ep within interval */ + COMP_MISSED_INT,/* 23 */ + /* Successfully stopped command ring */ + COMP_CMD_STOP, /* 24 */ + /* Successfully aborted current command and stopped command ring */ + COMP_CMD_ABORT, /* 25 */ + /* Stopped - transfer was terminated by a stop endpoint command */ + COMP_STOP,/* 26 */ + /* Same as COMP_EP_STOPPED, but the transferred length in the event + * is invalid */ + COMP_STOP_INVAL, /* 27*/ + /* Control Abort Error - Debug Capability - control pipe aborted */ + COMP_DBG_ABORT, /* 28 */ + /* Max Exit Latency Too Large Error */ + COMP_MEL_ERR,/* 29 */ + /* TRB type 30 reserved */ + /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ + COMP_BUFF_OVER = 31, + /* Event Lost Error - xHC has an "internal event overrun condition" */ + COMP_ISSUES, /* 32 */ + /* Undefined Error - reported when other error codes don't apply */ + COMP_UNKNOWN, /* 33 */ + /* Invalid Stream ID Error */ + COMP_STRID_ERR, /* 34 */ + /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ + COMP_2ND_BW_ERR, /* 35 */ + /* Split Transaction Error */ + COMP_SPLIT_ERR /* 36 */ + +} xhci_comp_code; + +struct xhci_link_trb { + /* 64-bit segment pointer*/ + volatile __le64 segment_ptr; + volatile __le32 intr_target; + volatile __le32 control; +}; + +/* control bitfields */ +#define LINK_TOGGLE (0x1 << 1) + +/* Command completion event TRB */ +struct xhci_event_cmd { + /* Pointer to command TRB, or the value passed by the event data trb */ + volatile __le64 cmd_trb; + volatile __le32 status; + volatile __le32 flags; +}; + +/* flags bitmasks */ +/* bits 16:23 are the virtual function ID */ +/* bits 24:31 are the slot ID */ +#define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24) +#define TRB_TO_SLOT_ID_SHIFT (24) +#define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT) +#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) +#define SLOT_ID_FOR_TRB_MASK (0xff) +#define SLOT_ID_FOR_TRB_SHIFT (24) + +/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ +#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) +#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) + +#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) +#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) +#define LAST_EP_INDEX 30 + +/* Set TR Dequeue Pointer command TRB fields */ +#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) +#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) + + +/* Port Status Change Event TRB fields */ +/* Port ID - bits 31:24 */ +#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) +#define PORT_ID_SHIFT (24) +#define PORT_ID_MASK (0xff << PORT_ID_SHIFT) + +/* Normal TRB fields */ +/* transfer_len bitmasks - bits 0:16 */ +#define TRB_LEN(p) ((p) & 0x1ffff) +#define TRB_LEN_MASK (0x1ffff) +/* Interrupter Target - which MSI-X vector to target the completion event at */ +#define TRB_INTR_TARGET_SHIFT (22) +#define TRB_INTR_TARGET_MASK (0x3ff) +#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) +#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) +#define TRB_TBC(p) (((p) & 0x3) << 7) +#define TRB_TLBPC(p) (((p) & 0xf) << 16) + +/* Cycle bit - indicates TRB ownership by HC or HCD */ +#define TRB_CYCLE (1<<0) +/* + * Force next event data TRB to be evaluated before task switch. + * Used to pass OS data back after a TD completes. + */ +#define TRB_ENT (1<<1) +/* Interrupt on short packet */ +#define TRB_ISP (1<<2) +/* Set PCIe no snoop attribute */ +#define TRB_NO_SNOOP (1<<3) +/* Chain multiple TRBs into a TD */ +#define TRB_CHAIN (1<<4) +/* Interrupt on completion */ +#define TRB_IOC (1<<5) +/* The buffer pointer contains immediate data */ +#define TRB_IDT (1<<6) + +/* Block Event Interrupt */ +#define TRB_BEI (1<<9) + +/* Control transfer TRB specific fields */ +#define TRB_DIR_IN (1<<16) +#define TRB_TX_TYPE(p) ((p) << 16) +#define TRB_TX_TYPE_SHIFT (16) +#define TRB_DATA_OUT 2 +#define TRB_DATA_IN 3 + +/* Isochronous TRB specific fields */ +#define TRB_SIA (1 << 31) + +struct xhci_generic_trb { + volatile __le32 field[4]; +}; + +union xhci_trb { + struct xhci_link_trb link; + struct xhci_transfer_event trans_event; + struct xhci_event_cmd event_cmd; + struct xhci_generic_trb generic; +}; + +/* TRB bit mask */ +#define TRB_TYPE_BITMASK (0xfc00) +#define TRB_TYPE(p) ((p) << 10) +#define TRB_TYPE_SHIFT (10) +#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) + +/* TRB type IDs */ +typedef enum { + /* bulk, interrupt, isoc scatter/gather, and control data stage */ + TRB_NORMAL = 1, + /* setup stage for control transfers */ + TRB_SETUP, /* 2 */ + /* data stage for control transfers */ + TRB_DATA, /* 3 */ + /* status stage for control transfers */ + TRB_STATUS, /* 4 */ + /* isoc transfers */ + TRB_ISOC, /* 5 */ + /* TRB for linking ring segments */ + TRB_LINK, /* 6 */ + /* TRB for EVENT DATA */ + TRB_EVENT_DATA, /* 7 */ + /* Transfer Ring No-op (not for the command ring) */ + TRB_TR_NOOP, /* 8 */ + /* Command TRBs */ + /* Enable Slot Command */ + TRB_ENABLE_SLOT, /* 9 */ + /* Disable Slot Command */ + TRB_DISABLE_SLOT, /* 10 */ + /* Address Device Command */ + TRB_ADDR_DEV, /* 11 */ + /* Configure Endpoint Command */ + TRB_CONFIG_EP, /* 12 */ + /* Evaluate Context Command */ + TRB_EVAL_CONTEXT, /* 13 */ + /* Reset Endpoint Command */ + TRB_RESET_EP, /* 14 */ + /* Stop Transfer Ring Command */ + TRB_STOP_RING, /* 15 */ + /* Set Transfer Ring Dequeue Pointer Command */ + TRB_SET_DEQ, /* 16 */ + /* Reset Device Command */ + TRB_RESET_DEV, /* 17 */ + /* Force Event Command (opt) */ + TRB_FORCE_EVENT, /* 18 */ + /* Negotiate Bandwidth Command (opt) */ + TRB_NEG_BANDWIDTH, /* 19 */ + /* Set Latency Tolerance Value Command (opt) */ + TRB_SET_LT, /* 20 */ + /* Get port bandwidth Command */ + TRB_GET_BW, /* 21 */ + /* Force Header Command - generate a transaction or link management packet */ + TRB_FORCE_HEADER, /* 22 */ + /* No-op Command - not for transfer rings */ + TRB_CMD_NOOP, /* 23 */ + /* TRB IDs 24-31 reserved */ + /* Event TRBS */ + /* Transfer Event */ + TRB_TRANSFER = 32, + /* Command Completion Event */ + TRB_COMPLETION, /* 33 */ + /* Port Status Change Event */ + TRB_PORT_STATUS, /* 34 */ + /* Bandwidth Request Event (opt) */ + TRB_BANDWIDTH_EVENT, /* 35 */ + /* Doorbell Event (opt) */ + TRB_DOORBELL, /* 36 */ + /* Host Controller Event */ + TRB_HC_EVENT, /* 37 */ + /* Device Notification Event - device sent function wake notification */ + TRB_DEV_NOTE, /* 38 */ + /* MFINDEX Wrap Event - microframe counter wrapped */ + TRB_MFINDEX_WRAP, /* 39 */ + /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ + /* Nec vendor-specific command completion event. */ + TRB_NEC_CMD_COMP = 48, /* 48 */ + /* Get NEC firmware revision. */ + TRB_NEC_GET_FW, /* 49 */ +} trb_type; + +#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) +/* Above, but for __le32 types -- can avoid work by swapping constants: */ +#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ + cpu_to_le32(TRB_TYPE(TRB_LINK))) +#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ + cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) + +/* + * TRBS_PER_SEGMENT must be a multiple of 4, + * since the command ring is 64-byte aligned. + * It must also be greater than 16. + */ +#define TRBS_PER_SEGMENT 64 +/* Allow two commands + a link TRB, along with any reserved command TRBs */ +#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) +#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) +/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). + * Change this if you change TRBS_PER_SEGMENT! + */ +#define SEGMENT_SHIFT 10 +/* TRB buffer pointers can't cross 64KB boundaries */ +#define TRB_MAX_BUFF_SHIFT 16 +#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) + +struct xhci_segment { + union xhci_trb *trbs; + /* private to HCD */ + struct xhci_segment *next; +}; + +struct xhci_ring { + struct xhci_segment *first_seg; + union xhci_trb *enqueue; + struct xhci_segment *enq_seg; + union xhci_trb *dequeue; + struct xhci_segment *deq_seg; + /* + * Write the cycle state into the TRB cycle field to give ownership of + * the TRB to the host controller (if we are the producer), or to check + * if we own the TRB (if we are the consumer). See section 4.9.1. + */ + volatile u32 cycle_state; + unsigned int num_segs; +}; + +struct xhci_erst_entry { + /* 64-bit event ring segment address */ + __le64 seg_addr; + __le32 seg_size; + /* Set to zero */ + __le32 rsvd; +}; + +struct xhci_erst { + struct xhci_erst_entry *entries; + unsigned int num_entries; + /* Num entries the ERST can contain */ + unsigned int erst_size; +}; + +/* + * Each segment table entry is 4*32bits long. 1K seems like an ok size: + * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, + * meaning 64 ring segments. + * Initial allocated size of the ERST, in number of entries */ +#define ERST_NUM_SEGS 3 +/* Initial number of event segment rings allocated */ +#define ERST_ENTRIES 3 +/* Initial allocated size of the ERST, in number of entries */ +#define ERST_SIZE 64 +/* Poll every 60 seconds */ +#define POLL_TIMEOUT 60 +/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ +#define XHCI_STOP_EP_CMD_TIMEOUT 5 +/* XXX: Make these module parameters */ + +struct xhci_virt_ep { + struct xhci_ring *ring; + unsigned int ep_state; +#define SET_DEQ_PENDING (1 << 0) +#define EP_HALTED (1 << 1) /* For stall handling */ +#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ +/* Transitioning the endpoint to using streams, don't enqueue URBs */ +#define EP_GETTING_STREAMS (1 << 3) +#define EP_HAS_STREAMS (1 << 4) +/* Transitioning the endpoint to not using streams, don't enqueue URBs */ +#define EP_GETTING_NO_STREAMS (1 << 5) +}; + +#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) + +struct xhci_virt_device { + struct usb_device *udev; + /* + * Commands to the hardware are passed an "input context" that + * tells the hardware what to change in its data structures. + * The hardware will return changes in an "output context" that + * software must allocate for the hardware. We need to keep + * track of input and output contexts separately because + * these commands might fail and we don't trust the hardware. + */ + struct xhci_container_ctx *out_ctx; + /* Used for addressing devices and configuration changes */ + struct xhci_container_ctx *in_ctx; + /* Rings saved to ensure old alt settings can be re-instated */ +#define XHCI_MAX_RINGS_CACHED 31 + struct xhci_virt_ep eps[31]; +}; + +/* TODO: copied from ehci.h - can be refactored? */ +/* xHCI spec says all registers are little endian */ +static inline unsigned int xhci_readl(uint32_t volatile *regs) +{ + return readl(regs); +} + +static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) +{ + writel(val, regs); +} + +/* + * Registers should always be accessed with double word or quad word accesses. + * Some xHCI implementations may support 64-bit address pointers. Registers + * with 64-bit address pointers should be written to with dword accesses by + * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. + * xHCI implementations that do not support 64-bit address pointers will ignore + * the high dword, and write order is irrelevant. + */ +static inline u64 xhci_readq(__le64 volatile *regs) +{ + __u32 *ptr = (__u32 *)regs; + u64 val_lo = readl(ptr); + u64 val_hi = readl(ptr + 1); + return val_lo + (val_hi << 32); +} + +static inline void xhci_writeq(__le64 volatile *regs, const u64 val) +{ + __u32 *ptr = (__u32 *)regs; + u32 val_lo = lower_32_bits(val); + /* FIXME */ + u32 val_hi = upper_32_bits(val); + writel(val_lo, ptr); + writel(val_hi, ptr + 1); +} + +int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, + struct xhci_hcor **ret_hcor); +void xhci_hcd_stop(int index); + + +/************************************************************* + EXTENDED CAPABILITY DEFINITIONS +*************************************************************/ +/* Up to 16 ms to halt an HC */ +#define XHCI_MAX_HALT_USEC (16*1000) +/* HC not running - set to 1 when run/stop bit is cleared. */ +#define XHCI_STS_HALT (1 << 0) + +/* HCCPARAMS offset from PCI base address */ +#define XHCI_HCC_PARAMS_OFFSET 0x10 +/* HCCPARAMS contains the first extended capability pointer */ +#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) + +/* Command and Status registers offset from the Operational Registers address */ +#define XHCI_CMD_OFFSET 0x00 +#define XHCI_STS_OFFSET 0x04 + +#define XHCI_MAX_EXT_CAPS 50 + +/* Capability Register */ +/* bits 7:0 - how long is the Capabilities register */ +#define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff) + +/* Extended capability register fields */ +#define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff) +#define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff) +#define XHCI_EXT_CAPS_VAL(p) ((p) >> 16) +/* Extended capability IDs - ID 0 reserved */ +#define XHCI_EXT_CAPS_LEGACY 1 +#define XHCI_EXT_CAPS_PROTOCOL 2 +#define XHCI_EXT_CAPS_PM 3 +#define XHCI_EXT_CAPS_VIRT 4 +#define XHCI_EXT_CAPS_ROUTE 5 +/* IDs 6-9 reserved */ +#define XHCI_EXT_CAPS_DEBUG 10 +/* USB Legacy Support Capability - section 7.1.1 */ +#define XHCI_HC_BIOS_OWNED (1 << 16) +#define XHCI_HC_OS_OWNED (1 << 24) + +/* USB Legacy Support Capability - section 7.1.1 */ +/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ +#define XHCI_LEGACY_SUPPORT_OFFSET (0x00) + +/* USB Legacy Support Control and Status Register - section 7.1.2 */ +/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ +#define XHCI_LEGACY_CONTROL_OFFSET (0x04) +/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ +#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) + +/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ +#define XHCI_L1C (1 << 16) + +/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ +#define XHCI_HLC (1 << 19) + +/* command register values to disable interrupts and halt the HC */ +/* start/stop HC execution - do not write unless HC is halted*/ +#define XHCI_CMD_RUN (1 << 0) +/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ +#define XHCI_CMD_EIE (1 << 2) +/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ +#define XHCI_CMD_HSEIE (1 << 3) +/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ +#define XHCI_CMD_EWE (1 << 10) + +#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) + +/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ +#define XHCI_STS_CNR (1 << 11) + +struct xhci_ctrl { + struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ + struct xhci_hcor *hcor; + struct xhci_doorbell_array *dba; + struct xhci_run_regs *run_regs; + struct xhci_device_context_array *dcbaa \ + __attribute__ ((aligned(ARCH_DMA_MINALIGN))); + struct xhci_ring *event_ring; + struct xhci_ring *cmd_ring; + struct xhci_ring *transfer_ring; + struct xhci_segment *seg; + struct xhci_intr_reg *ir_set; + struct xhci_erst erst; + struct xhci_erst_entry entry[ERST_NUM_SEGS]; + struct xhci_virt_device *devs[MAX_HC_SLOTS]; + int rootdev; +}; + +unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); +struct xhci_input_control_ctx + *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); +struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *ctx); +struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *ctx, + unsigned int ep_index); +void xhci_endpoint_copy(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *in_ctx, + struct xhci_container_ctx *out_ctx, + unsigned int ep_index); +void xhci_slot_copy(struct xhci_ctrl *ctrl, + struct xhci_container_ctx *in_ctx, + struct xhci_container_ctx *out_ctx); +void xhci_setup_addressable_virt_dev(struct usb_device *udev); +void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, + u32 slot_id, u32 ep_index, trb_type cmd); +void xhci_acknowledge_event(struct xhci_ctrl *ctrl); +union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected); +int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, + int length, void *buffer); +int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, + struct devrequest *req, int length, void *buffer); +int xhci_check_maxpacket(struct usb_device *udev); +void xhci_flush_cache(uint32_t addr, u32 type_len); +void xhci_inval_cache(uint32_t addr, u32 type_len); +void xhci_cleanup(struct xhci_ctrl *ctrl); +struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs); +int xhci_alloc_virt_device(struct usb_device *udev); +int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr, + struct xhci_hcor *hcor); + +#endif /* HOST_XHCI_H_ */ diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile index c23bef1cc2..9edeece381 100644 --- a/drivers/usb/musb-new/Makefile +++ b/drivers/usb/musb-new/Makefile @@ -2,38 +2,14 @@ # for USB OTG silicon based on Mentor Graphics INVENTRA designs # -include $(TOPDIR)/config.mk - -LIB := $(obj)libusb_musb-new.o - -COBJS-$(CONFIG_MUSB_GADGET) += musb_gadget.o musb_gadget_ep0.o musb_core.o -COBJS-$(CONFIG_MUSB_GADGET) += musb_uboot.o -COBJS-$(CONFIG_MUSB_HOST) += musb_host.o musb_core.o musb_uboot.o -COBJS-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o -COBJS-$(CONFIG_USB_MUSB_AM35X) += am35x.o -COBJS-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o - -CFLAGS_NO_WARN := $(call cc-option,-Wno-unused-variable) \ - $(call cc-option,-Wno-unused-but-set-variable) \ - $(call cc-option,-Wno-unused-label) -CFLAGS += $(CFLAGS_NO_WARN) - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -#$(LIB): $(OBJS) -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### - +obj-$(CONFIG_MUSB_GADGET) += musb_gadget.o musb_gadget_ep0.o musb_core.o +obj-$(CONFIG_MUSB_GADGET) += musb_uboot.o +obj-$(CONFIG_MUSB_HOST) += musb_host.o musb_core.o musb_uboot.o +obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o +obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o +obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o +obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o + +ccflags-y := $(call cc-option,-Wno-unused-variable) \ + $(call cc-option,-Wno-unused-but-set-variable) \ + $(call cc-option,-Wno-unused-label) diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c index 57c9bd393b..857d7eb0cc 100644 --- a/drivers/usb/musb-new/am35x.c +++ b/drivers/usb/musb-new/am35x.c @@ -26,7 +26,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h index 72c8c2bad1..46f83d9b36 100644 --- a/drivers/usb/musb-new/linux-compat.h +++ b/drivers/usb/musb-new/linux-compat.h @@ -5,49 +5,7 @@ #include #include -#define __init -#define __devinit -#define __devinitdata -#define __devinitconst -#define __iomem -#define __deprecated - -struct unused {}; -typedef struct unused unused_t; - -typedef int irqreturn_t; -typedef unused_t spinlock_t; - -struct work_struct {}; - -struct timer_list {}; -struct notifier_block {}; - -typedef unsigned long dmaaddr_t; - -#define spin_lock_init(lock) do {} while (0) -#define spin_lock(lock) do {} while (0) -#define spin_unlock(lock) do {} while (0) -#define spin_lock_irqsave(lock, flags) do {} while (0) -#define spin_unlock_irqrestore(lock, flags) do {} while (0) - -#define setup_timer(timer, func, data) do {} while (0) -#define del_timer_sync(timer) do {} while (0) -#define schedule_work(work) do {} while (0) -#define INIT_WORK(work, fun) do {} while (0) - -#define cpu_relax() do {} while (0) - #define pr_debug(fmt, args...) debug(fmt, ##args) -#define dev_dbg(dev, fmt, args...) \ - debug(fmt, ##args) -#define dev_vdbg(dev, fmt, args...) \ - debug(fmt, ##args) -#define dev_info(dev, fmt, args...) \ - printf(fmt, ##args) -#define dev_err(dev, fmt, args...) \ - printf(fmt, ##args) -#define printk printf #define WARN(condition, fmt, args...) ({ \ int ret_warn = !!condition; \ @@ -55,28 +13,6 @@ typedef unsigned long dmaaddr_t; printf(fmt, ##args); \ ret_warn; }) -#define KERN_DEBUG -#define KERN_NOTICE -#define KERN_WARNING -#define KERN_ERR - -#define kfree(ptr) free(ptr) - -#define pm_runtime_get_sync(dev) do {} while (0) -#define pm_runtime_put(dev) do {} while (0) -#define pm_runtime_put_sync(dev) do {} while (0) -#define pm_runtime_use_autosuspend(dev) do {} while (0) -#define pm_runtime_set_autosuspend_delay(dev, delay) do {} while (0) -#define pm_runtime_enable(dev) do {} while (0) - -#define MODULE_DESCRIPTION(desc) -#define MODULE_AUTHOR(author) -#define MODULE_LICENSE(license) -#define MODULE_ALIAS(alias) -#define module_param(name, type, perm) -#define MODULE_PARM_DESC(name, desc) -#define EXPORT_SYMBOL_GPL(name) - #define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s) #define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s) #define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s) @@ -84,16 +20,6 @@ typedef unsigned long dmaaddr_t; #define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s) #define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s) -#define IRQ_NONE 0 -#define IRQ_HANDLED 0 - -#define dev_set_drvdata(dev, data) do {} while (0) - -#define disable_irq_wake(irq) do {} while (0) -#define enable_irq_wake(irq) -EINVAL -#define free_irq(irq, data) do {} while (0) -#define request_irq(nr, f, flags, nm, data) 0 - #define device_init_wakeup(dev, a) do {} while (0) #define platform_data device_data diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index da9357149b..242cc30b1c 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -89,7 +89,6 @@ * Most of the conditional compilation will (someday) vanish. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include @@ -943,9 +942,7 @@ void musb_start(struct musb *musb) /* put into basic highspeed mode and start session */ musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE -#ifdef CONFIG_USB_GADGET_DUALSPEED | MUSB_POWER_HSENAB -#endif /* ENSUSPEND wedges tusb */ /* | MUSB_POWER_ENSUSPEND */ ); @@ -1311,9 +1308,7 @@ static int __devinit ep_config_from_table(struct musb *musb) break; } - printk(KERN_DEBUG "%s: setup fifo_mode %d\n", - musb_driver_name, fifo_mode); - + pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); done: offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); @@ -1341,10 +1336,9 @@ done: musb->nr_endpoints = max(epn, musb->nr_endpoints); } - printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", - musb_driver_name, - n + 1, musb->config->num_eps * 2 - 1, - offset, (1 << (musb->config->ram_bits + 2))); + pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1, + musb->config->num_eps * 2 - 1, offset, + (1 << (musb->config->ram_bits + 2))); if (!musb->bulk_ep) { pr_debug("%s: missing bulk\n", musb_driver_name); @@ -1447,8 +1441,7 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb) if (reg & MUSB_CONFIGDATA_SOFTCONE) strcat(aInfo, ", SoftConn"); - printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", - musb_driver_name, reg, aInfo); + pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); aDate[0] = 0; if (MUSB_CONTROLLER_MHDRC == musb_type) { @@ -1469,8 +1462,8 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb) snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), MUSB_HWVERS_MINOR(musb->hwvers), (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); - printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", - musb_driver_name, type, aRevision, aDate); + pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type, + aRevision, aDate); /* configure ep0 */ musb_configure_ep0(musb); @@ -2122,7 +2115,7 @@ musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev, pm_runtime_put(musb->controller); - dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", + pr_debug("USB %s mode controller at %p using %s, IRQ %d\n", ({char *s; switch (musb->board_mode) { case MUSB_HOST: s = "Host"; break; diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c index 9a03917e87..17ed224488 100644 --- a/drivers/usb/musb-new/musb_dsps.c +++ b/drivers/usb/musb-new/musb_dsps.c @@ -29,7 +29,6 @@ * da8xx.c would be merged to this file after testing. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index d2cb91a898..97acf93d31 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -33,7 +33,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c index 6599d386dc..5a715013a2 100644 --- a/drivers/usb/musb-new/musb_gadget_ep0.c +++ b/drivers/usb/musb-new/musb_gadget_ep0.c @@ -33,7 +33,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include @@ -576,6 +575,10 @@ static void ep0_txstate(struct musb *musb) } else request = NULL; + /* send it out, triggering a "txpktrdy cleared" irq */ + musb_ep_select(musb->mregs, 0); + musb_writew(regs, MUSB_CSR0, csr); + /* report completions as soon as the fifo's loaded; there's no * win in waiting till this last packet gets acked. (other than * very precise fault reporting, needed by USB TMC; possible with @@ -588,10 +591,6 @@ static void ep0_txstate(struct musb *musb) return; musb->ackpend = 0; } - - /* send it out, triggering a "txpktrdy cleared" irq */ - musb_ep_select(musb->mregs, 0); - musb_writew(regs, MUSB_CSR0, csr); } /* diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c index 9a2cf59d92..437309ceb4 100644 --- a/drivers/usb/musb-new/musb_host.c +++ b/drivers/usb/musb-new/musb_host.c @@ -33,7 +33,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include @@ -2131,8 +2130,6 @@ done: return ret; } - -#ifndef __UBOOT__ /* * abort a transfer that's at the head of a hardware queue. * called with controller locked, irqs blocked @@ -2196,7 +2193,14 @@ static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) return status; } -static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) +#ifndef __UBOOT__ +static int musb_urb_dequeue( +#else +int musb_urb_dequeue( +#endif + struct usb_hcd *hcd, + struct urb *urb, + int status) { struct musb *musb = hcd_to_musb(hcd); struct musb_qh *qh; @@ -2254,6 +2258,7 @@ done: return ret; } +#ifndef __UBOOT__ /* disable an endpoint */ static void musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) diff --git a/drivers/usb/musb-new/musb_host.h b/drivers/usb/musb-new/musb_host.h index ebebe0c02a..546b4a2715 100644 --- a/drivers/usb/musb-new/musb_host.h +++ b/drivers/usb/musb-new/musb_host.h @@ -110,5 +110,6 @@ static inline struct urb *next_urb(struct musb_qh *qh) #ifdef __UBOOT__ int musb_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); +int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); #endif #endif /* _MUSB_HOST_H */ diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index 03f2655af2..27e4ed4ec6 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -216,6 +216,9 @@ #ifndef CONFIG_BLACKFIN +/* SUNXI has different reg addresses, but identical r/w functions */ +#ifndef CONFIG_ARCH_SUNXI + /* * Common USB registers */ @@ -318,6 +321,85 @@ #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ (0x80 + (8*(_epnum)) + (_offset)) +#else /* CONFIG_ARCH_SUNXI */ + +/* + * Common USB registers + */ + +#define MUSB_FADDR 0x0098 +#define MUSB_POWER 0x0040 + +#define MUSB_INTRTX 0x0044 +#define MUSB_INTRRX 0x0046 +#define MUSB_INTRTXE 0x0048 +#define MUSB_INTRRXE 0x004A +#define MUSB_INTRUSB 0x004C +#define MUSB_INTRUSBE 0x0050 +#define MUSB_FRAME 0x0054 +#define MUSB_INDEX 0x0042 +#define MUSB_TESTMODE 0x007C + +/* Get offset for a given FIFO from musb->mregs */ +#define MUSB_FIFO_OFFSET(epnum) (0x00 + ((epnum) * 4)) + +/* + * Additional Control Registers + */ + +#define MUSB_DEVCTL 0x0041 + +/* These are always controlled through the INDEX register */ +#define MUSB_TXFIFOSZ 0x0090 +#define MUSB_RXFIFOSZ 0x0094 +#define MUSB_TXFIFOADD 0x0092 +#define MUSB_RXFIFOADD 0x0096 + +#define MUSB_EPINFO 0x0078 +#define MUSB_RAMINFO 0x0079 +#define MUSB_LINKINFO 0x007A +#define MUSB_VPLEN 0x007B +#define MUSB_HS_EOF1 0x007C +#define MUSB_FS_EOF1 0x007D +#define MUSB_LS_EOF1 0x007E + +/* Offsets to endpoint registers */ +#define MUSB_TXMAXP 0x0080 +#define MUSB_TXCSR 0x0082 +#define MUSB_CSR0 0x0082 +#define MUSB_RXMAXP 0x0084 +#define MUSB_RXCSR 0x0086 +#define MUSB_RXCOUNT 0x0088 +#define MUSB_COUNT0 0x0088 +#define MUSB_TXTYPE 0x008C +#define MUSB_TYPE0 0x008C +#define MUSB_TXINTERVAL 0x008D +#define MUSB_NAKLIMIT0 0x008D +#define MUSB_RXTYPE 0x008E +#define MUSB_RXINTERVAL 0x008F + +#define MUSB_CONFIGDATA 0x00b0 /* musb_read_configdata adds 0x10 ! */ +#define MUSB_FIFOSIZE 0x0090 + +/* Offsets to endpoint registers in indexed model (using INDEX register) */ +#define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset) + +#define MUSB_TXCSR_MODE 0x2000 + +/* "bus control"/target registers, for host side multipoint (external hubs) */ +#define MUSB_TXFUNCADDR 0x0098 +#define MUSB_TXHUBADDR 0x009A +#define MUSB_TXHUBPORT 0x009B + +#define MUSB_RXFUNCADDR 0x009C +#define MUSB_RXHUBADDR 0x009E +#define MUSB_RXHUBPORT 0x009F + +/* Endpoint is selected with MUSB_INDEX. */ +#define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset) + +#endif /* CONFIG_ARCH_SUNXI */ + static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size) { musb_writeb(mbase, MUSB_TXFIFOSZ, c_size); @@ -340,7 +422,9 @@ static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off) static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val) { +#ifndef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */ musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val); +#endif } static inline u8 musb_read_txfifosz(void __iomem *mbase) @@ -365,7 +449,11 @@ static inline u16 musb_read_rxfifoadd(void __iomem *mbase) static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) { +#ifdef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */ + return 0; +#else return musb_readb(mbase, MUSB_ULPI_BUSCONTROL); +#endif } static inline u8 musb_read_configdata(void __iomem *mbase) @@ -376,7 +464,11 @@ static inline u8 musb_read_configdata(void __iomem *mbase) static inline u16 musb_read_hwvers(void __iomem *mbase) { +#ifdef CONFIG_ARCH_SUNXI + return 0; /* Unknown version */ +#else return musb_readw(mbase, MUSB_HWVERS); +#endif } static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase) diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index c2400328a3..6e58ddf02c 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -4,7 +4,6 @@ #include #include -#define __UBOOT__ #include #include "linux-compat.h" #include "usb-compat.h" @@ -13,6 +12,11 @@ #include "musb_gadget.h" #ifdef CONFIG_MUSB_HOST +struct int_queue { + struct usb_host_endpoint hep; + struct urb urb; +}; + static struct musb *host; static struct usb_hcd hcd; static enum usb_device_speed host_speed; @@ -26,45 +30,42 @@ static void musb_host_complete_urb(struct urb *urb) static struct usb_host_endpoint hep; static struct urb urb; -static struct urb *construct_urb(struct usb_device *dev, int endpoint_type, - unsigned long pipe, void *buffer, int len, - struct devrequest *setup, int interval) +static void construct_urb(struct urb *urb, struct usb_host_endpoint *hep, + struct usb_device *dev, int endpoint_type, + unsigned long pipe, void *buffer, int len, + struct devrequest *setup, int interval) { int epnum = usb_pipeendpoint(pipe); int is_in = usb_pipein(pipe); - memset(&urb, 0, sizeof(struct urb)); - memset(&hep, 0, sizeof(struct usb_host_endpoint)); - INIT_LIST_HEAD(&hep.urb_list); - INIT_LIST_HEAD(&urb.urb_list); - urb.ep = &hep; - urb.complete = musb_host_complete_urb; - urb.status = -EINPROGRESS; - urb.dev = dev; - urb.pipe = pipe; - urb.transfer_buffer = buffer; - urb.transfer_dma = (unsigned long)buffer; - urb.transfer_buffer_length = len; - urb.setup_packet = (unsigned char *)setup; - - urb.ep->desc.wMaxPacketSize = + memset(urb, 0, sizeof(struct urb)); + memset(hep, 0, sizeof(struct usb_host_endpoint)); + INIT_LIST_HEAD(&hep->urb_list); + INIT_LIST_HEAD(&urb->urb_list); + urb->ep = hep; + urb->complete = musb_host_complete_urb; + urb->status = -EINPROGRESS; + urb->dev = dev; + urb->pipe = pipe; + urb->transfer_buffer = buffer; + urb->transfer_dma = (unsigned long)buffer; + urb->transfer_buffer_length = len; + urb->setup_packet = (unsigned char *)setup; + + urb->ep->desc.wMaxPacketSize = __cpu_to_le16(is_in ? dev->epmaxpacketin[epnum] : dev->epmaxpacketout[epnum]); - urb.ep->desc.bmAttributes = endpoint_type; - urb.ep->desc.bEndpointAddress = + urb->ep->desc.bmAttributes = endpoint_type; + urb->ep->desc.bEndpointAddress = (is_in ? USB_DIR_IN : USB_DIR_OUT) | epnum; - urb.ep->desc.bInterval = interval; - - return &urb; + urb->ep->desc.bInterval = interval; } -#define MUSB_HOST_TIMEOUT 0x3ffffff - static int submit_urb(struct usb_hcd *hcd, struct urb *urb) { struct musb *host = hcd->hcd_priv; int ret; - int timeout; + unsigned long timeout; ret = musb_urb_enqueue(hcd, urb, 0); if (ret < 0) { @@ -72,12 +73,16 @@ static int submit_urb(struct usb_hcd *hcd, struct urb *urb) return ret; } - timeout = MUSB_HOST_TIMEOUT; + timeout = get_timer(0) + USB_TIMEOUT_MS(urb->pipe); do { if (ctrlc()) return -EIO; host->isr(0, host); - } while ((urb->dev->status & USB_ST_NOT_PROC) && --timeout); + } while (urb->status == -EINPROGRESS && + get_timer(0) < timeout); + + if (urb->status == -EINPROGRESS) + musb_urb_dequeue(hcd, urb, -ETIME); return urb->status; } @@ -85,38 +90,117 @@ static int submit_urb(struct usb_hcd *hcd, struct urb *urb) int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int len, struct devrequest *setup) { - struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_CONTROL, pipe, - buffer, len, setup, 0); + construct_urb(&urb, &hep, dev, USB_ENDPOINT_XFER_CONTROL, pipe, + buffer, len, setup, 0); /* Fix speed for non hub-attached devices */ if (!dev->parent) dev->speed = host_speed; - return submit_urb(&hcd, urb); + return submit_urb(&hcd, &urb); } int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int len) { - struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_BULK, pipe, - buffer, len, NULL, 0); - return submit_urb(&hcd, urb); + construct_urb(&urb, &hep, dev, USB_ENDPOINT_XFER_BULK, pipe, + buffer, len, NULL, 0); + return submit_urb(&hcd, &urb); } int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int len, int interval) { - struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_INT, pipe, - buffer, len, NULL, interval); - return submit_urb(&hcd, urb); + construct_urb(&urb, &hep, dev, USB_ENDPOINT_XFER_INT, pipe, + buffer, len, NULL, interval); + return submit_urb(&hcd, &urb); } -int usb_lowlevel_init(int index, void **controller) +struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe, + int queuesize, int elementsize, void *buffer, int interval) { + struct int_queue *queue; + int ret, index = usb_pipein(pipe) * 16 + usb_pipeendpoint(pipe); + + if (queuesize != 1) { + printf("ERROR musb int-queues only support queuesize 1\n"); + return NULL; + } + + if (dev->int_pending & (1 << index)) { + printf("ERROR int-urb is already pending on pipe %lx\n", pipe); + return NULL; + } + + queue = malloc(sizeof(*queue)); + if (!queue) + return NULL; + + construct_urb(&queue->urb, &queue->hep, dev, USB_ENDPOINT_XFER_INT, + pipe, buffer, elementsize, NULL, interval); + + ret = musb_urb_enqueue(&hcd, &queue->urb, 0); + if (ret < 0) { + printf("Failed to enqueue URB to controller\n"); + free(queue); + return NULL; + } + + dev->int_pending |= 1 << index; + return queue; +} + +int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) +{ + int index = usb_pipein(queue->urb.pipe) * 16 + + usb_pipeendpoint(queue->urb.pipe); + + if (queue->urb.status == -EINPROGRESS) + musb_urb_dequeue(&hcd, &queue->urb, -ETIME); + + dev->int_pending &= ~(1 << index); + free(queue); + return 0; +} + +void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) +{ + if (queue->urb.status != -EINPROGRESS) + return NULL; /* URB has already completed in a prev. poll */ + + host->isr(0, host); + + if (queue->urb.status != -EINPROGRESS) + return queue->urb.transfer_buffer; /* Done */ + + return NULL; /* URB still pending */ +} + +void usb_reset_root_port(void) +{ + void *mbase = host->mregs; u8 power; + + power = musb_readb(mbase, MUSB_POWER); + power &= 0xf0; + musb_writeb(mbase, MUSB_POWER, MUSB_POWER_RESET | power); + mdelay(50); + power = musb_readb(mbase, MUSB_POWER); + musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power); + host->isr(0, host); + host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ? + USB_SPEED_HIGH : + (musb_readb(mbase, MUSB_DEVCTL) & MUSB_DEVCTL_FSDEV) ? + USB_SPEED_FULL : USB_SPEED_LOW; + mdelay((host_speed == USB_SPEED_LOW) ? 200 : 50); +} + +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) +{ void *mbase; - int timeout = MUSB_HOST_TIMEOUT; + /* USB spec says it may take up to 1 second for a device to connect */ + unsigned long timeout = get_timer(0) + 1000; if (!host) { printf("MUSB host is not registered\n"); @@ -128,20 +212,11 @@ int usb_lowlevel_init(int index, void **controller) do { if (musb_readb(mbase, MUSB_DEVCTL) & MUSB_DEVCTL_HM) break; - } while (--timeout); - if (!timeout) + } while (get_timer(0) < timeout); + if (get_timer(0) >= timeout) return -ENODEV; - power = musb_readb(mbase, MUSB_POWER); - musb_writeb(mbase, MUSB_POWER, MUSB_POWER_RESET | power); - udelay(30000); - power = musb_readb(mbase, MUSB_POWER); - musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power); - host->isr(0, host); - host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ? - USB_SPEED_HIGH : - (musb_readb(mbase, MUSB_DEVCTL) & MUSB_DEVCTL_FSDEV) ? - USB_SPEED_FULL : USB_SPEED_LOW; + usb_reset_root_port(); host->is_active = 1; hcd.hcd_priv = host; @@ -204,7 +279,10 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) { - /* TODO: implement me */ + if (driver->disconnect) + driver->disconnect(&gadget->g); + if (driver->unbind) + driver->unbind(&gadget->g); return 0; } #endif /* CONFIG_MUSB_GADGET */ diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index b1c4dc7828..98f4830912 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -24,7 +24,6 @@ * Suite 330, Boston, MA 02111-1307 USA * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c new file mode 100644 index 0000000000..778916df00 --- /dev/null +++ b/drivers/usb/musb-new/sunxi.c @@ -0,0 +1,279 @@ +/* + * Allwinner SUNXI "glue layer" + * + * Copyright © 2015 Hans de Goede + * Copyright © 2013 Jussi Kivilinna + * + * Based on the sw_usb "Allwinner OTG Dual Role Controller" code. + * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd. + * javen + * + * Based on the DA8xx "glue layer" code. + * Copyright (c) 2008-2009 MontaVista Software, Inc. + * Copyright (C) 2005-2006 by Texas Instruments + * + * This file is part of the Inventra Controller Driver for Linux. + * + * The Inventra Controller Driver for Linux is free software; you + * can redistribute it and/or modify it under the terms of the GNU + * General Public License version 2 as published by the Free Software + * Foundation. + * + */ +#include +#include +#include +#include "linux-compat.h" +#include "musb_core.h" + +/****************************************************************************** + ****************************************************************************** + * From the Allwinner driver + ****************************************************************************** + ******************************************************************************/ + +/****************************************************************************** + * From include/sunxi_usb_bsp.h + ******************************************************************************/ + +/* reg offsets */ +#define USBC_REG_o_ISCR 0x0400 +#define USBC_REG_o_PHYCTL 0x0404 +#define USBC_REG_o_PHYBIST 0x0408 +#define USBC_REG_o_PHYTUNE 0x040c + +#define USBC_REG_o_VEND0 0x0043 + +/* Interface Status and Control */ +#define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30 +#define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29 +#define USBC_BP_ISCR_EXT_ID_STATUS 28 +#define USBC_BP_ISCR_EXT_DM_STATUS 27 +#define USBC_BP_ISCR_EXT_DP_STATUS 26 +#define USBC_BP_ISCR_MERGED_VBUS_STATUS 25 +#define USBC_BP_ISCR_MERGED_ID_STATUS 24 + +#define USBC_BP_ISCR_ID_PULLUP_EN 17 +#define USBC_BP_ISCR_DPDM_PULLUP_EN 16 +#define USBC_BP_ISCR_FORCE_ID 14 +#define USBC_BP_ISCR_FORCE_VBUS_VALID 12 +#define USBC_BP_ISCR_VBUS_VALID_SRC 10 + +#define USBC_BP_ISCR_HOSC_EN 7 +#define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6 +#define USBC_BP_ISCR_ID_CHANGE_DETECT 5 +#define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4 +#define USBC_BP_ISCR_IRQ_ENABLE 3 +#define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2 +#define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1 +#define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0 + +/****************************************************************************** + * From usbc/usbc.c + ******************************************************************************/ + +static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val) +{ + u32 temp = reg_val; + + temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT); + temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT); + temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT); + + return temp; +} + +static void USBC_EnableIdPullUp(__iomem void *base) +{ + u32 reg_val; + + reg_val = musb_readl(base, USBC_REG_o_ISCR); + reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN); + reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); + musb_writel(base, USBC_REG_o_ISCR, reg_val); +} + +static void USBC_DisableIdPullUp(__iomem void *base) +{ + u32 reg_val; + + reg_val = musb_readl(base, USBC_REG_o_ISCR); + reg_val &= ~(1 << USBC_BP_ISCR_ID_PULLUP_EN); + reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); + musb_writel(base, USBC_REG_o_ISCR, reg_val); +} + +static void USBC_EnableDpDmPullUp(__iomem void *base) +{ + u32 reg_val; + + reg_val = musb_readl(base, USBC_REG_o_ISCR); + reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN); + reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); + musb_writel(base, USBC_REG_o_ISCR, reg_val); +} + +static void USBC_DisableDpDmPullUp(__iomem void *base) +{ + u32 reg_val; + + reg_val = musb_readl(base, USBC_REG_o_ISCR); + reg_val &= ~(1 << USBC_BP_ISCR_DPDM_PULLUP_EN); + reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); + musb_writel(base, USBC_REG_o_ISCR, reg_val); +} + +static void USBC_ForceIdToLow(__iomem void *base) +{ + u32 reg_val; + + reg_val = musb_readl(base, USBC_REG_o_ISCR); + reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID); + reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID); + reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); + musb_writel(base, USBC_REG_o_ISCR, reg_val); +} + +static void USBC_ForceIdToHigh(__iomem void *base) +{ + u32 reg_val; + + reg_val = musb_readl(base, USBC_REG_o_ISCR); + reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID); + reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID); + reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); + musb_writel(base, USBC_REG_o_ISCR, reg_val); +} + +static void USBC_ForceVbusValidDisable(__iomem void *base) +{ + u32 reg_val; + + reg_val = musb_readl(base, USBC_REG_o_ISCR); + reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID); + reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); + musb_writel(base, USBC_REG_o_ISCR, reg_val); +} + +static void USBC_ForceVbusValidToHigh(__iomem void *base) +{ + u32 reg_val; + + reg_val = musb_readl(base, USBC_REG_o_ISCR); + reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID); + reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID); + reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); + musb_writel(base, USBC_REG_o_ISCR, reg_val); +} + +static void USBC_ConfigFIFO_Base(void) +{ + u32 reg_value; + + /* config usb fifo, 8kb mode */ + reg_value = readl(SUNXI_SRAMC_BASE + 0x04); + reg_value &= ~(0x03 << 0); + reg_value |= (1 << 0); + writel(reg_value, SUNXI_SRAMC_BASE + 0x04); +} + +/****************************************************************************** + * MUSB Glue code + ******************************************************************************/ + +static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) +{ + struct musb *musb = __hci; + irqreturn_t retval = IRQ_NONE; + + /* read and flush interrupts */ + musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); + if (musb->int_usb) + musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); + musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); + if (musb->int_tx) + musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx); + musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); + if (musb->int_rx) + musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx); + + if (musb->int_usb || musb->int_tx || musb->int_rx) + retval |= musb_interrupt(musb); + + return retval; +} + +static void sunxi_musb_enable(struct musb *musb) +{ + pr_debug("%s():\n", __func__); + + /* select PIO mode */ + musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0); + + if (is_host_enabled(musb)) { + /* port power on */ + sunxi_usbc_vbus_enable(0); + } +} + +static void sunxi_musb_disable(struct musb *musb) +{ + pr_debug("%s():\n", __func__); + + /* Put the controller back in a pristane state for "usb reset" */ + if (musb->is_active) { + sunxi_usbc_disable(0); + sunxi_usbc_enable(0); + musb->is_active = 0; + } +} + +static int sunxi_musb_init(struct musb *musb) +{ + int err; + + pr_debug("%s():\n", __func__); + + err = sunxi_usbc_request_resources(0); + if (err) + return err; + + musb->isr = sunxi_musb_interrupt; + sunxi_usbc_enable(0); + + USBC_ConfigFIFO_Base(); + USBC_EnableDpDmPullUp(musb->mregs); + USBC_EnableIdPullUp(musb->mregs); + + if (is_host_enabled(musb)) { + /* Host mode */ + USBC_ForceIdToLow(musb->mregs); + USBC_ForceVbusValidToHigh(musb->mregs); + } else { + /* Peripheral mode */ + USBC_ForceIdToHigh(musb->mregs); + USBC_ForceVbusValidDisable(musb->mregs); + } + + return 0; +} + +static int sunxi_musb_exit(struct musb *musb) +{ + pr_debug("%s():\n", __func__); + + USBC_DisableDpDmPullUp(musb->mregs); + USBC_DisableIdPullUp(musb->mregs); + sunxi_usbc_vbus_disable(0); + sunxi_usbc_disable(0); + + return sunxi_usbc_free_resources(0); +} + +const struct musb_platform_ops sunxi_musb_ops = { + .init = sunxi_musb_init, + .exit = sunxi_musb_exit, + + .enable = sunxi_musb_enable, + .disable = sunxi_musb_disable, +}; diff --git a/drivers/usb/musb-new/usb-compat.h b/drivers/usb/musb-new/usb-compat.h index 27f656f0ce..50bad378c5 100644 --- a/drivers/usb/musb-new/usb-compat.h +++ b/drivers/usb/musb-new/usb-compat.h @@ -48,6 +48,7 @@ struct urb { list_add_tail(&urb->urb_list, &urb->ep->urb_list); \ ret; }) #define usb_hcd_unlink_urb_from_ep(hcd, urb) list_del_init(&urb->urb_list) +#define usb_hcd_check_unlink_urb(hdc, urb, status) 0 static inline void usb_hcd_giveback_urb(struct usb_hcd *hcd, struct urb *urb, diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile index aa2126dcb0..3c9ed98bc0 100644 --- a/drivers/usb/musb/Makefile +++ b/drivers/usb/musb/Makefile @@ -5,32 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libusb_musb.o - -COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o -COBJS-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o -COBJS-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o -COBJS-$(CONFIG_USB_DAVINCI) += davinci.o -COBJS-$(CONFIG_USB_OMAP3) += omap3.o -COBJS-$(CONFIG_USB_DA8XX) += da8xx.o -COBJS-$(CONFIG_USB_AM35X) += am35x.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o +obj-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o +obj-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o +obj-$(CONFIG_USB_DAVINCI) += davinci.o +obj-$(CONFIG_USB_OMAP3) += omap3.o +obj-$(CONFIG_USB_DA8XX) += da8xx.o +obj-$(CONFIG_USB_AM35X) += am35x.o diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c index 35268ba58e..65fff887d3 100644 --- a/drivers/usb/musb/blackfin_usb.c +++ b/drivers/usb/musb/blackfin_usb.c @@ -11,6 +11,7 @@ #include #include +#include #include #include "musb_core.h" diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index 3dc5d6a558..f0ba8aaaa3 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -28,99 +28,8 @@ static const struct musb_epinfo epinfo[3] = { static int rh_devnum; static u32 port_status; -/* Device descriptor */ -static const u8 root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.1 */ - 0x02, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static const u8 root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x02, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static const unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; +#include -static const unsigned char root_hub_str_index1[] = { - 0x1c, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'M', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'S', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'B', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; #endif /* @@ -267,7 +176,7 @@ static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) /* * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. */ -static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) +static int wait_until_txep_ready(struct usb_device *dev, u8 ep) { u16 csr; int timeout = CONFIG_MUSB_TIMEOUT; @@ -299,7 +208,7 @@ static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) /* * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. */ -static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) +static int wait_until_rxep_ready(struct usb_device *dev, u8 ep) { u16 csr; int timeout = CONFIG_MUSB_TIMEOUT; @@ -417,8 +326,12 @@ static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) /* Set TXPKTRDY bit */ csr = readw(&musbr->txcsr); - writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY, - &musbr->txcsr); + + csr |= MUSB_CSR0_TXPKTRDY; +#if !defined(CONFIG_SOC_DM365) + csr |= MUSB_CSR0_H_DIS_PING; +#endif + writew(csr, &musbr->txcsr); result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); if (result < 0) break; @@ -439,8 +352,10 @@ static int ctrlreq_out_status_phase(struct usb_device *dev) /* Set the StatusPkt bit */ csr = readw(&musbr->txcsr); - csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY | - MUSB_CSR0_H_STATUSPKT); + csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); +#if !defined(CONFIG_SOC_DM365) + csr |= MUSB_CSR0_H_DIS_PING; +#endif writew(csr, &musbr->txcsr); /* Wait until TXPKTRDY bit is cleared */ @@ -457,7 +372,10 @@ static int ctrlreq_in_status_phase(struct usb_device *dev) int result; /* Set the StatusPkt bit and ReqPkt bit */ - csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; + csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; +#if !defined(CONFIG_SOC_DM365) + csr |= MUSB_CSR0_H_DIS_PING; +#endif writew(csr, &musbr->txcsr); result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); @@ -1009,7 +927,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); /* Wait until the TxPktRdy bit is cleared */ - if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { + if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) { readw(&musbr->txcsr); usb_settoggle(dev, ep, dir_out, (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); @@ -1044,7 +962,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); /* Wait until the RxPktRdy bit is set */ - if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { + if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) { csr = readw(&musbr->rxcsr); usb_settoggle(dev, ep, dir_out, (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); @@ -1080,7 +998,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, /* * This function initializes the usb controller module. */ -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { u8 power; u32 timeout; @@ -1217,7 +1135,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); /* Wait until the RxPktRdy bit is set */ - if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) { + if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) { csr = readw(&musbr->rxcsr); usb_settoggle(dev, ep, dir_out, (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); diff --git a/drivers/usb/musb/musb_hcd.h b/drivers/usb/musb/musb_hcd.h index 02b9adcbe4..0c8e75d46c 100644 --- a/drivers/usb/musb/musb_hcd.h +++ b/drivers/usb/musb/musb_hcd.h @@ -37,9 +37,6 @@ extern unsigned char new[]; ((readb(&musbr->power) & MUSB_POWER_HSMODE) \ >> MUSB_POWER_HSMODE_SHIFT) -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) - /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ /* destination of request */ diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c index 3e3e05ecfd..87640f4e32 100644 --- a/drivers/usb/musb/musb_udc.c +++ b/drivers/usb/musb/musb_udc.c @@ -39,7 +39,8 @@ */ #include -#include +#include +#include #include "../gadget/ep0.h" #include "musb_core.h" #if defined(CONFIG_USB_OMAP3) diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index f93121a3aa..93d147e26f 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -5,26 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libusb_phy.o - -COBJS-$(CONFIG_TWL4030_USB) += twl4030.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_TWL4030_USB) += twl4030.o +obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c new file mode 100644 index 0000000000..52a3664b99 --- /dev/null +++ b/drivers/usb/phy/omap_usb_phy.c @@ -0,0 +1,274 @@ +/* + * OMAP USB PHY Support + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Author: Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../host/xhci.h" + +#ifdef CONFIG_OMAP_USB3PHY1_HOST +struct usb_dpll_params { + u16 m; + u8 n; + u8 freq:3; + u8 sd; + u32 mf; +}; + +#define NUM_USB_CLKS 6 + +static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = { + {1250, 5, 4, 20, 0}, /* 12 MHz */ + {3125, 20, 4, 20, 0}, /* 16.8 MHz */ + {1172, 8, 4, 20, 65537}, /* 19.2 MHz */ + {1250, 12, 4, 20, 0}, /* 26 MHz */ + {3125, 47, 4, 20, 92843}, /* 38.4 MHz */ + {1000, 7, 4, 10, 0}, /* 20 MHz */ +}; + +static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs) +{ + u32 val; + + writel(SET_PLL_GO, &phy_regs->pll_go); + do { + val = readl(&phy_regs->pll_status); + if (val & PLL_LOCK) + break; + } while (1); +} + +static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs) +{ + u32 clk_index = get_sys_clk_index(); + u32 val; + + val = readl(&phy_regs->pll_config_1); + val &= ~PLL_REGN_MASK; + val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT; + writel(val, &phy_regs->pll_config_1); + + val = readl(&phy_regs->pll_config_2); + val &= ~PLL_SELFREQDCO_MASK; + val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT; + writel(val, &phy_regs->pll_config_2); + + val = readl(&phy_regs->pll_config_1); + val &= ~PLL_REGM_MASK; + val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT; + writel(val, &phy_regs->pll_config_1); + + val = readl(&phy_regs->pll_config_4); + val &= ~PLL_REGM_F_MASK; + val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT; + writel(val, &phy_regs->pll_config_4); + + val = readl(&phy_regs->pll_config_3); + val &= ~PLL_SD_MASK; + val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT; + writel(val, &phy_regs->pll_config_3); + + omap_usb_dpll_relock(phy_regs); +} + +static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs) +{ + u32 rate = get_sys_clk_freq()/1000000; + u32 val; + + val = readl((*ctrl)->control_phy_power_usb); + val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK); + val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON); + val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT; + + writel(val, (*ctrl)->control_phy_power_usb); +} + +void usb_phy_power(int on) +{ + u32 val; + + val = readl((*ctrl)->control_phy_power_usb); + if (on) { + val &= ~USB3_PWRCTL_CLK_CMD_MASK; + val |= USB3_PHY_TX_RX_POWERON; + } else { + val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON); + } + + writel(val, (*ctrl)->control_phy_power_usb); +} + +void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) +{ + omap_usb_dpll_lock(phy_regs); + usb3_phy_partial_powerup(phy_regs); + /* + * Give enough time for the PHY to partially power-up before + * powering it up completely. delay value suggested by the HW + * team. + */ + mdelay(100); +} + +static void omap_enable_usb3_phy(struct omap_xhci *omap) +{ + u32 val; + + /* Setting OCP2SCP1 register */ + setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl, + OCP2SCP1_CLKCTRL_MODULEMODE_HW); + + /* Turn on 32K AON clk */ + setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */ + writel(0x0, (*prcm)->cm_l3init_clkstctrl); + + val = (USBOTGSS_DMADISABLE | + USBOTGSS_STANDBYMODE_SMRT_WKUP | + USBOTGSS_IDLEMODE_NOIDLE); + writel(val, &omap->otg_wrapper->sysconfig); + + /* Clear the utmi OTG status */ + val = readl(&omap->otg_wrapper->utmi_otg_status); + writel(val, &omap->otg_wrapper->utmi_otg_status); + + /* Enable interrupts */ + writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0); + val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN | + USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN | + USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN | + USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN | + USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN | + USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN | + USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN | + USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN | + USBOTGSS_IRQ_SET_1_OEVT_EN); + writel(val, &omap->otg_wrapper->irqenable_set_1); + + /* Clear the IRQ status */ + val = readl(&omap->otg_wrapper->irqstatus_1); + writel(val, &omap->otg_wrapper->irqstatus_1); + val = readl(&omap->otg_wrapper->irqstatus_0); + writel(val, &omap->otg_wrapper->irqstatus_0); + + /* Enable the USB OTG Super speed clocks */ + val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW); + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val); + +}; +#endif /* CONFIG_OMAP_USB3PHY1_HOST */ + +#ifdef CONFIG_OMAP_USB2PHY2_HOST +static void omap_enable_usb2_phy2(struct omap_xhci *omap) +{ + u32 reg, val; + + val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET); + writel(val, (*ctrl)->control_srcomp_north_side); + + setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, + (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K | + OTG_SS_CLKCTRL_MODULEMODE_HW)); + + /* This is an undocumented Reserved register */ + reg = 0x4a0086c0; + val = readl(reg); + val |= 0x100; + setbits_le32(reg, val); +} + +void usb_phy_power(int on) +{ + return; +} +#endif /* CONFIG_OMAP_USB2PHY2_HOST */ + +#ifdef CONFIG_AM437X_USB2PHY2_HOST +static void am437x_enable_usb2_phy2(struct omap_xhci *omap) +{ + const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN | + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); + + writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL); + writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL); + + writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL); + writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL); +} + +void usb_phy_power(int on) +{ + u32 val; + + /* USB1_CTRL */ + val = readl(USB1_CTRL); + if (on) { + /* + * these bits are re-used on AM437x to power up/down the USB + * CM and OTG PHYs, if we don't toggle them, USB will not be + * functional on newer silicon revisions + */ + val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN); + } else { + val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN; + } + + writel(val, USB1_CTRL); +} +#endif /* CONFIG_AM437X_USB2PHY2_HOST */ + +void omap_reset_usb_phy(struct dwc3 *dwc3_reg) +{ + /* Assert USB3 PHY reset */ + setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Assert USB2 PHY reset */ + setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + + mdelay(100); + + /* Clear USB3 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Clear USB2 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + +} + +void omap_enable_phy(struct omap_xhci *omap) +{ +#ifdef CONFIG_OMAP_USB2PHY2_HOST + omap_enable_usb2_phy2(omap); +#endif + +#ifdef CONFIG_AM437X_USB2PHY2_HOST + am437x_enable_usb2_phy2(omap); +#endif + +#ifdef CONFIG_OMAP_USB3PHY1_HOST + omap_enable_usb3_phy(omap); + omap_usb3_phy_init(omap->usb3_phy); +#endif +} diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c index 8f5d700aa6..6dcb336bbf 100644 --- a/drivers/usb/phy/twl4030.c +++ b/drivers/usb/phy/twl4030.c @@ -21,7 +21,7 @@ * * ------------------------------------------------------------------------ * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/drivers/usb/ulpi/Makefile b/drivers/usb/ulpi/Makefile index ba5a1ab5bf..a21fe2c936 100644 --- a/drivers/usb/ulpi/Makefile +++ b/drivers/usb/ulpi/Makefile @@ -4,28 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libusb_ulpi.o - -COBJS-$(CONFIG_USB_ULPI) += ulpi.o -COBJS-$(CONFIG_USB_ULPI_VIEWPORT) += ulpi-viewport.o -COBJS-$(CONFIG_USB_ULPI_VIEWPORT_OMAP) += omap-ulpi-viewport.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_USB_ULPI) += ulpi.o +obj-$(CONFIG_USB_ULPI_VIEWPORT) += ulpi-viewport.o +obj-$(CONFIG_USB_ULPI_VIEWPORT_OMAP) += omap-ulpi-viewport.o diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig new file mode 100644 index 0000000000..51728b366f --- /dev/null +++ b/drivers/video/Kconfig @@ -0,0 +1,90 @@ +config VIDEO_VESA + bool "Enable VESA video driver support" + depends on X86 + default n + help + Turn on this option to enable a very simple driver which uses vesa + to discover the video mode and then provides a frame buffer for use + by U-Boot. This can in principle be used with any platform that + supports PCI and video cards that support VESA BIOS Extension (VBE). + +config VIDEO_LCD_SSD2828 + bool "SSD2828 bridge chip" + default n + ---help--- + Support for the SSD2828 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fly into MIPI DSI + interface for driving a MIPI compatible LCD panel. It uses SPI for + configuration. + +config VIDEO_LCD_SSD2828_TX_CLK + int "SSD2828 TX_CLK frequency (in MHz)" + depends on VIDEO_LCD_SSD2828 + default 0 + ---help--- + The frequency of the crystal, which is clocking SSD2828. It may be + anything in the 8MHz-30MHz range and the exact value should be + retrieved from the board schematics. Or in the case of Allwinner + hardware, it can be usually found as 'lcd_xtal_freq' variable in + FEX files. It can be also set to 0 for selecting PCLK from the + parallel LCD interface instead of TX_CLK as the PLL clock source. + +config VIDEO_LCD_SSD2828_RESET + string "RESET pin of SSD2828" + depends on VIDEO_LCD_SSD2828 + default "" + ---help--- + The reset pin of SSD2828 chip. This takes a string in the format + understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_HITACHI_TX18D42VM + bool "Hitachi tx18d42vm LVDS LCD panel support" + depends on VIDEO + default n + ---help--- + Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a + lcd controller which needs to be initialized over SPI, once that is + done they work like a regular LVDS panel. + +config VIDEO_LCD_SPI_CS + string "SPI CS pin for LCD related config job" + depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM + default "" + ---help--- + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_SPI_SCLK + string "SPI SCLK pin for LCD related config job" + depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM + default "" + ---help--- + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_SPI_MOSI + string "SPI MOSI pin for LCD related config job" + depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM + default "" + ---help--- + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_SPI_MISO + string "SPI MISO pin for LCD related config job (optional)" + depends on VIDEO_LCD_SSD2828 + default "" + ---help--- + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. If wired up, this pin may provide additional + useful functionality. Such as bi-directional communication with the + hardware and LCD panel id retrieval (if the panel can report it). The + option takes a string in the format understood by 'name_to_gpio' + function, e.g. PH1 for pin 1 of port H. diff --git a/drivers/video/Makefile b/drivers/video/Makefile index f5c4911b20..af2d47bd75 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -5,56 +5,46 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libvideo.o - -COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o -COBJS-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o -COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o -COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o -COBJS-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o -COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o -COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ +obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o +obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o +obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o +obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o +obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o +obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o +obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o -COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o -COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o -COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o -COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o -COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o -COBJS-$(CONFIG_S6E63D6) += s6e63d6.o -COBJS-$(CONFIG_LD9040) += ld9040.o -COBJS-$(CONFIG_SED156X) += sed156x.o -COBJS-$(CONFIG_VIDEO_BCM2835) += bcm2835.o -COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o -COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o -COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o -COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o -COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o -COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o -COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o -COBJS-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o -COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o -COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o -COBJS-$(CONFIG_VIDEO_SM501) += sm501.o -COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o -COBJS-$(CONFIG_VIDEO_TEGRA) += tegra.o -COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o +obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o +obj-$(CONFIG_L5F31188) += l5f31188.o +obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o +obj-$(CONFIG_PXA_LCD) += pxa_lcd.o +obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o +obj-$(CONFIG_S6E8AX0) += s6e8ax0.o +obj-$(CONFIG_S6E63D6) += s6e63d6.o +obj-$(CONFIG_LD9040) += ld9040.o +obj-$(CONFIG_SED156X) += sed156x.o +obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o +obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o +obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o +obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o +obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o +obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o +obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o +obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o +obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o +obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o +obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o +obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o +obj-$(CONFIG_VIDEO_SED13806) += sed13806.o +obj-$(CONFIG_VIDEO_SM501) += sm501.o +obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o +obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o +obj-$(CONFIG_VIDEO_TEGRA) += tegra.o +obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o +obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o +obj-$(CONFIG_FORMIKE) += formike.o +obj-$(CONFIG_AM335X_LCD) += am335x-fb.o +obj-$(CONFIG_VIDEO_PARADE) += parade.o diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c new file mode 100644 index 0000000000..ab9894102d --- /dev/null +++ b/drivers/video/am335x-fb.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2013 Hannes Petermaier + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * minimal framebuffer driver for TI's AM335x SoC to be compatible with + * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c) + * + * - supporting only 24bit RGB/TFT raster Mode (not using palette) + * - sets up LCD controller as in 'am335x_lcdpanel' struct given + * - starts output DMA from gd->fb_base buffer + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include "am335x-fb.h" + +#if !defined(LCD_CNTL_BASE) +#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!" +#endif + + +/* LCD Control Register */ +#define LCD_CLK_DIVISOR(x) ((x) << 8) +#define LCD_RASTER_MODE 0x01 +/* LCD Clock Enable Register */ +#define LCD_CORECLKEN (0x01 << 0) +#define LCD_LIDDCLKEN (0x01 << 1) +#define LCD_DMACLKEN (0x01 << 2) +/* LCD DMA Control Register */ +#define LCD_DMA_BURST_SIZE(x) ((x) << 4) +#define LCD_DMA_BURST_1 0x0 +#define LCD_DMA_BURST_2 0x1 +#define LCD_DMA_BURST_4 0x2 +#define LCD_DMA_BURST_8 0x3 +#define LCD_DMA_BURST_16 0x4 +/* LCD Timing_0 Register */ +#define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24) +#define LCD_HFPLSB(x) ((((x)-1) & 0xFF) << 16) +#define LCD_HSWLSB(x) ((((x)-1) & 0x3F) << 10) +#define LCD_HORLSB(x) (((((x) >> 4)-1) & 0x3F) << 4) +#define LCD_HORMSB(x) (((((x) >> 4)-1) & 0x40) >> 4) +/* LCD Timing_1 Register */ +#define LCD_VBP(x) ((x) << 24) +#define LCD_VFP(x) ((x) << 16) +#define LCD_VSW(x) (((x)-1) << 10) +#define LCD_VERLSB(x) (((x)-1) & 0x3FF) +/* LCD Timing_2 Register */ +#define LCD_HSWMSB(x) ((((x)-1) & 0x3C0) << 21) +#define LCD_VERMSB(x) ((((x)-1) & 0x400) << 16) +#define LCD_HBPMSB(x) ((((x)-1) & 0x300) >> 4) +#define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8) +#define LCD_INVMASK(x) ((x) & 0x3F00000) +/* LCD Raster Ctrl Register */ +#define LCD_TFT_24BPP_MODE (1 << 25) +#define LCD_TFT_24BPP_UNPACK (1 << 26) +#define LCD_PALMODE_RAWDATA (0x10 << 20) +#define LCD_TFT_MODE (0x01 << 7) +#define LCD_RASTER_ENABLE (0x01 << 0) + + +/* Macro definitions */ +#define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3) + +struct am335x_lcdhw { + unsigned int pid; /* 0x00 */ + unsigned int ctrl; /* 0x04 */ + unsigned int gap0; /* 0x08 */ + unsigned int lidd_ctrl; /* 0x0C */ + unsigned int lidd_cs0_conf; /* 0x10 */ + unsigned int lidd_cs0_addr; /* 0x14 */ + unsigned int lidd_cs0_data; /* 0x18 */ + unsigned int lidd_cs1_conf; /* 0x1C */ + unsigned int lidd_cs1_addr; /* 0x20 */ + unsigned int lidd_cs1_data; /* 0x24 */ + unsigned int raster_ctrl; /* 0x28 */ + unsigned int raster_timing0; /* 0x2C */ + unsigned int raster_timing1; /* 0x30 */ + unsigned int raster_timing2; /* 0x34 */ + unsigned int raster_subpanel; /* 0x38 */ + unsigned int raster_subpanel2; /* 0x3C */ + unsigned int lcddma_ctrl; /* 0x40 */ + unsigned int lcddma_fb0_base; /* 0x44 */ + unsigned int lcddma_fb0_ceiling; /* 0x48 */ + unsigned int lcddma_fb1_base; /* 0x4C */ + unsigned int lcddma_fb1_ceiling; /* 0x50 */ + unsigned int sysconfig; /* 0x54 */ + unsigned int irqstatus_raw; /* 0x58 */ + unsigned int irqstatus; /* 0x5C */ + unsigned int irqenable_set; /* 0x60 */ + unsigned int irqenable_clear; /* 0x64 */ + unsigned int gap1; /* 0x68 */ + unsigned int clkc_enable; /* 0x6C */ + unsigned int clkc_reset; /* 0x70 */ +}; + +static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE; +DECLARE_GLOBAL_DATA_PTR; + +int lcd_get_size(int *line_length) +{ + *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; + return *line_length * panel_info.vl_row + 0x20; +} + +int am335xfb_init(struct am335x_lcdpanel *panel) +{ + if (0 == gd->fb_base) { + printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n"); + return -1; + } + if (0 == panel) { + printf("ERROR: missing ptr to am335x_lcdpanel!\n"); + return -1; + } + + debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ", + panel->hactive, panel->vactive, panel->bpp, + panel->hfp, panel->hbp, panel->hsw); + debug("vfp=%d,vbp=%d,vsw=%d / clk-div=%d)\n", + panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk_div); + debug("using frambuffer at 0x%08x with size %d.\n", + (unsigned int)gd->fb_base, FBSIZE(panel)); + + /* palette default entry */ + memset((void *)gd->fb_base, 0, 0x20); + *(unsigned int *)gd->fb_base = 0x4000; + + lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN; + lcdhw->raster_ctrl = 0; + lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE; + lcdhw->lcddma_fb0_base = gd->fb_base; + lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel) + 0x20; + lcdhw->lcddma_fb1_base = gd->fb_base; + lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel) + 0x20; + lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); + + lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) | + LCD_HORMSB(panel->hactive) | + LCD_HFPLSB(panel->hfp) | + LCD_HBPLSB(panel->hbp) | + LCD_HSWLSB(panel->hsw); + lcdhw->raster_timing1 = LCD_VBP(panel->vbp) | + LCD_VFP(panel->vfp) | + LCD_VSW(panel->vsw) | + LCD_VERLSB(panel->vactive); + lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) | + LCD_VERMSB(panel->vactive) | + LCD_INVMASK(panel->pol) | + LCD_HBPMSB(panel->hbp) | + LCD_HFPMSB(panel->hfp) | + 0x0000FF00; /* clk cycles for ac-bias */ + lcdhw->raster_ctrl = LCD_TFT_24BPP_MODE | + LCD_TFT_24BPP_UNPACK | + LCD_PALMODE_RAWDATA | + LCD_TFT_MODE | + LCD_RASTER_ENABLE; + + gd->fb_base += 0x20; /* point fb behind palette */ + + /* turn ON display through powercontrol function if accessible */ + if (0 != panel->panel_power_ctrl) { + mdelay(panel->pon_delay); + panel->panel_power_ctrl(1); + } + + return 0; +} diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h new file mode 100644 index 0000000000..8a0b131495 --- /dev/null +++ b/drivers/video/am335x-fb.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef AM335X_FB_H +#define AM335X_FB_H + +#define HSVS_CONTROL (0x01 << 25) /* + * 0 = lcd_lp and lcd_fp are driven on + * opposite edges of pixel clock than + * the lcd_pixel_o + * 1 = lcd_lp and lcd_fp are driven + * according to bit 24 Note that this + * bit MUST be set to '0' for Passive + * Matrix displays the edge timing is + * fixed + */ +#define HSVS_RISEFALL (0x01 << 24) /* + * 0 = lcd_lp and lcd_fp are driven on + * the rising edge of pixel clock (bit + * 25 must be set to 1) + * 1 = lcd_lp and lcd_fp are driven on + * the falling edge of pixel clock (bit + * 25 must be set to 1) + */ +#define DE_INVERT (0x01 << 23) /* + * 0 = DE is low-active + * 1 = DE is high-active + */ +#define PXCLK_INVERT (0x01 << 22) /* + * 0 = pix-clk is high-active + * 1 = pic-clk is low-active + */ +#define HSYNC_INVERT (0x01 << 21) /* + * 0 = HSYNC is active high + * 1 = HSYNC is avtive low + */ +#define VSYNC_INVERT (0x01 << 20) /* + * 0 = VSYNC is active high + * 1 = VSYNC is active low + */ + +struct am335x_lcdpanel { + unsigned int hactive; /* Horizontal active area */ + unsigned int vactive; /* Vertical active area */ + unsigned int bpp; /* bits per pixel */ + unsigned int hfp; /* Horizontal front porch */ + unsigned int hbp; /* Horizontal back porch */ + unsigned int hsw; /* Horizontal Sync Pulse Width */ + unsigned int vfp; /* Vertical front porch */ + unsigned int vbp; /* Vertical back porch */ + unsigned int vsw; /* Vertical Sync Pulse Width */ + unsigned int pxl_clk_div; /* Pixel clock divider*/ + unsigned int pol; /* polarity of sync, clock signals */ + unsigned int pon_delay; /* + * time in ms for turning on lcd after + * initializing lcd-controller + */ + void (*panel_power_ctrl)(int); /* fp for power on/off display */ +}; + +int am335xfb_init(struct am335x_lcdpanel *panel); + +#endif /* AM335X_FB_H */ diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c index 38d2eb107e..574895155d 100644 --- a/drivers/video/ati_radeon_fb.c +++ b/drivers/video/ati_radeon_fb.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -39,11 +40,6 @@ #define DPRINT(x...) do{}while(0) #endif -#ifndef min_t -#define min_t(type,x,y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) -#endif - #define MAX_MAPPED_VRAM (2048*2048*4) #define MIN_MAPPED_VRAM (1024*768*1) @@ -549,7 +545,6 @@ void radeon_setmode_9200(int vesa_idx, int bpp) } #include "../bios_emulator/include/biosemu.h" -extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp); int radeon_probe(struct radeonfb_info *rinfo) { diff --git a/drivers/video/ati_radeon_fb.h b/drivers/video/ati_radeon_fb.h index 065904555f..9dd638bb9e 100644 --- a/drivers/video/ati_radeon_fb.h +++ b/drivers/video/ati_radeon_fb.h @@ -92,7 +92,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) /* initiate flush */ OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, - ~RB2D_DC_FLUSH_ALL); + ~RB2D_DC_FLUSH_ALL); for (i=0; i < 2000000; i++) { if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index a3f7265df1..361c7da92d 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -3,7 +3,7 @@ * * Copyright (C) 2012 Atmel Corporation * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -31,10 +31,10 @@ */ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) { - lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) - | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) - | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk), - panel_info.mmio + ATMEL_LCDC_LUT(regno)); + lcdc_writel(panel_info.mmio + ATMEL_LCDC_LUT(regno), + ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) | + ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) | + ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk)); } void lcd_ctrl_init(void *lcdbase) @@ -42,11 +42,13 @@ void lcd_ctrl_init(void *lcdbase) unsigned long value; struct lcd_dma_desc *desc; struct atmel_hlcd_regs *regs; + u32 clk_pol; if (!has_lcdc()) return; /* No lcdc */ - regs = (struct atmel_hlcd_regs *)panel_info.mmio; + regs = panel_info.mmio; + clk_pol = panel_info.vl_clk_pol ? LCDC_LCDCFG0_CLKPOL : 0; /* Disable DISP signal */ lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); @@ -78,8 +80,8 @@ void lcd_ctrl_init(void *lcdbase) | LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISBASE - | panel_info.vl_clk_pol - | LCDC_LCDCFG0_CLKSEL); + | LCDC_LCDCFG0_CLKSEL + | clk_pol); } else { lcdc_writel(®s->lcdc_lcdcfg0, @@ -88,7 +90,7 @@ void lcd_ctrl_init(void *lcdbase) | LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISBASE - | panel_info.vl_clk_pol); + | clk_pol); } /* Initialize control register 5 */ @@ -128,12 +130,12 @@ void lcd_ctrl_init(void *lcdbase) value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); lcdc_writel(®s->lcdc_lcdcfg1, value); - value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); - value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); + value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin); + value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1); lcdc_writel(®s->lcdc_lcdcfg2, value); - value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); - value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); + value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1); + value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1); lcdc_writel(®s->lcdc_lcdcfg3, value); /* Display size */ @@ -171,6 +173,9 @@ void lcd_ctrl_init(void *lcdbase) | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; desc->next = (u32)desc; + /* Flush the DMA descriptor if we enabled dcache */ + flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc)); + lcdc_writel(®s->lcdc_baseaddr, desc->address); lcdc_writel(®s->lcdc_basectrl, desc->control); lcdc_writel(®s->lcdc_basenext, desc->next); @@ -194,4 +199,7 @@ void lcd_ctrl_init(void *lcdbase) lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) udelay(1); + + /* Enable flushing if we enabled dcache */ + lcd_set_flush_dcache(1); } diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 4bc0f195fe..3cf008ce6b 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -3,7 +3,7 @@ * * Copyright (C) 2007 Atmel Corporation * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 58a616317a..1f18231ac6 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -14,6 +14,8 @@ DECLARE_GLOBAL_DATA_PTR; /* Global variables that lcd.c expects to exist */ vidinfo_t panel_info; +static u32 bcm2835_pitch; + struct msg_query { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_physical_w_h physical_w_h; @@ -30,6 +32,7 @@ struct msg_setup { struct bcm2835_mbox_tag_virtual_offset virtual_offset; struct bcm2835_mbox_tag_overscan overscan; struct bcm2835_mbox_tag_allocate_buffer allocate_buffer; + struct bcm2835_mbox_tag_pitch pitch; u32 end_tag; }; @@ -80,6 +83,7 @@ void lcd_ctrl_init(void *lcdbase) msg_setup->overscan.body.req.right = 0; BCM2835_MBOX_INIT_TAG(&msg_setup->allocate_buffer, ALLOCATE_BUFFER); msg_setup->allocate_buffer.body.req.alignment = 0x100; + BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_setup->pitch, GET_PITCH); ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_setup->hdr); if (ret) { @@ -90,6 +94,7 @@ void lcd_ctrl_init(void *lcdbase) w = msg_setup->physical_w_h.body.resp.width; h = msg_setup->physical_w_h.body.resp.height; + bcm2835_pitch = msg_setup->pitch.body.resp.pitch; debug("bcm2835: Final resolution is %d x %d\n", w, h); @@ -103,3 +108,9 @@ void lcd_ctrl_init(void *lcdbase) void lcd_enable(void) { } + +int lcd_get_size(int *line_length) +{ + *line_length = bcm2835_pitch; + return *line_length * panel_info.vl_row; +} diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c index 0138bca05e..60a5cc5b71 100644 --- a/drivers/video/bus_vcxk.c +++ b/drivers/video/bus_vcxk.c @@ -20,7 +20,6 @@ vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE)); #ifndef VCBITMASK #define VCBITMASK(bitno) (0x0001 << (bitno % 16)) #endif -#ifndef CONFIG_AT91_LEGACY at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ do { \ @@ -37,20 +36,6 @@ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; #define VCXK_ACKNOWLEDGE \ (!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \ CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) -#else - #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ - ((AT91PS_PIO) PORT)->PIO_PER = PIN; \ - ((AT91PS_PIO) PORT)->DDR = PIN; \ - ((AT91PS_PIO) PORT)->PIO_MDDR = PIN; \ - if (!I0O1) ((AT91PS_PIO) PORT)->PIO_PPUER = PIN; - - #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN; - #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN; - - #define VCXK_ACKNOWLEDGE \ - (!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\ - PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) -#endif #elif defined(CONFIG_MCF52x2) #include #ifndef VCBITMASK diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 96ef8f9c26..a81affa333 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -2,7 +2,7 @@ * (C) Copyright 2002 ELTEC Elektronik AG * Frank Gottschling * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -117,24 +117,11 @@ * Defines for the SED13806 driver */ #ifdef CONFIG_VIDEO_SED13806 - -#ifndef CONFIG_TOTAL5200 #define VIDEO_FB_LITTLE_ENDIAN -#endif #define VIDEO_HW_RECTFILL #define VIDEO_HW_BITBLT #endif -/* - * Defines for the SED13806 driver - */ -#ifdef CONFIG_VIDEO_SM501 - -#ifdef CONFIG_HH405 -#define VIDEO_FB_LITTLE_ENDIAN -#endif -#endif - #ifdef CONFIG_VIDEO_MXS #define VIDEO_FB_16BPP_WORD_SWAP #endif @@ -197,7 +184,6 @@ #include #include #include -#include #if defined(CONFIG_CMD_DATE) #include @@ -313,7 +299,11 @@ void console_cursor(int state); #define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) #define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) #define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) -#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) + +/* By default we scroll by a single line */ +#ifndef CONFIG_CONSOLE_SCROLL_LINES +#define CONFIG_CONSOLE_SCROLL_LINES 1 +#endif /* Macros */ #ifdef VIDEO_FB_LITTLE_ENDIAN @@ -431,6 +421,16 @@ static const int video_font_draw_table32[16][4] = { {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff} }; +/* + * Implement a weak default function for boards that optionally + * need to skip the cfb initialization. + */ +__weak int board_cfb_skip(void) +{ + /* As default, don't skip cfb init */ + return 0; +} + static void video_drawchars(int xx, int yy, unsigned char *s, int count) { u8 *cdat, *dest, *dest0; @@ -452,6 +452,10 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) ((u32 *) dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx; + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx; @@ -477,6 +481,10 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) SHORTSWAP32((video_font_draw_table15 [bits >> 4 & 3] & eorx) ^ bgx); + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[2] = SHORTSWAP32((video_font_draw_table15 [bits >> 2 & 3] & eorx) ^ @@ -507,6 +515,10 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) SHORTSWAP32((video_font_draw_table16 [bits >> 4 & 3] & eorx) ^ bgx); + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[2] = SHORTSWAP32((video_font_draw_table16 [bits >> 2 & 3] & eorx) ^ @@ -541,6 +553,11 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) ((u32 *) dest)[3] = SWAP32((video_font_draw_table32 [bits >> 4][3] & eorx) ^ bgx); + + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[4] = SWAP32((video_font_draw_table32 [bits & 15][0] & eorx) ^ bgx); @@ -576,6 +593,10 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) ((u32 *) dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx; + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx; @@ -723,26 +744,33 @@ static void console_clear_line(int line, int begin, int end) static void console_scrollup(void) { + const int rows = CONFIG_CONSOLE_SCROLL_LINES; + int i; + /* copy up rows ignoring the first one */ #ifdef VIDEO_HW_BITBLT video_hw_bitblt(VIDEO_PIXEL_SIZE, /* bytes per pixel */ 0, /* source pos x */ video_logo_height + - VIDEO_FONT_HEIGHT, /* source pos y */ + VIDEO_FONT_HEIGHT * rows, /* source pos y */ 0, /* dest pos x */ video_logo_height, /* dest pos y */ VIDEO_VISIBLE_COLS, /* frame width */ VIDEO_VISIBLE_ROWS - video_logo_height - - VIDEO_FONT_HEIGHT /* frame height */ + - VIDEO_FONT_HEIGHT * rows /* frame height */ ); #else - memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, - CONSOLE_SCROLL_SIZE >> 2); + memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_FIRST + rows * CONSOLE_ROW_SIZE, + (CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows) >> 2); #endif /* clear the last one */ - console_clear_line(CONSOLE_ROWS - 1, 0, CONSOLE_COLS - 1); + for (i = 1; i <= rows; i++) + console_clear_line(CONSOLE_ROWS - i, 0, CONSOLE_COLS - 1); + + /* Decrement row number */ + console_row -= rows; } static void console_back(void) @@ -854,9 +882,6 @@ static void console_newline(int n) if (console_row >= CONSOLE_ROWS) { /* Scroll everything up */ console_scrollup(); - - /* Decrement row number */ - console_row = CONSOLE_ROWS - 1; } } @@ -914,7 +939,7 @@ static void parse_putc(const char c) CURSOR_SET; } -void video_putc(const char c) +static void video_putc(struct stdio_dev *dev, const char c) { #ifdef CONFIG_CFB_CONSOLE_ANSI int i; @@ -1128,12 +1153,21 @@ void video_putc(const char c) flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); } -void video_puts(const char *s) +static void video_puts(struct stdio_dev *dev, const char *s) { + int flush = cfb_do_flush_cache; int count = strlen(s); + /* temporarily disable cache flush */ + cfb_do_flush_cache = 0; + while (count--) - video_putc(*s++); + video_putc(dev, *s++); + + if (flush) { + cfb_do_flush_cache = flush; + flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); + } } /* @@ -1141,14 +1175,11 @@ void video_puts(const char *s) * video_set_lut() if they do not support 8 bpp format. * Implement weak default function instead. */ -void __video_set_lut(unsigned int index, unsigned char r, +__weak void video_set_lut(unsigned int index, unsigned char r, unsigned char g, unsigned char b) { } -void video_set_lut(unsigned int, unsigned char, unsigned char, unsigned char) - __attribute__ ((weak, alias("__video_set_lut"))); - #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) #define FILL_8BIT_332RGB(r,g,b) { \ @@ -1443,7 +1474,11 @@ int video_display_bitmap(ulong bmp_image, int x, int y) printf("Error: malloc in gunzip failed!\n"); return 1; } - if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, + /* + * NB: we need to force offset of +2 + * See doc/README.displaying-bmps + */ + if (gunzip(dst+2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE-2, (uchar *) bmp_image, &len) != 0) { printf("Error: no valid bmp or bmp.gz image at %lx\n", @@ -1459,7 +1494,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y) /* * Set addr to decompressed image */ - bmp = (bmp_image_t *) dst; + bmp = (bmp_image_t *)(dst+2); if (!((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M'))) { @@ -1501,14 +1536,14 @@ int video_display_bitmap(ulong bmp_image, int x, int y) #ifdef CONFIG_SPLASH_SCREEN_ALIGN if (x == BMP_ALIGN_CENTER) - x = max(0, (VIDEO_VISIBLE_COLS - width) / 2); + x = max(0, (int)(VIDEO_VISIBLE_COLS - width) / 2); else if (x < 0) - x = max(0, VIDEO_VISIBLE_COLS - width + x + 1); + x = max(0, (int)(VIDEO_VISIBLE_COLS - width + x + 1)); if (y == BMP_ALIGN_CENTER) - y = max(0, (VIDEO_VISIBLE_ROWS - height) / 2); + y = max(0, (int)(VIDEO_VISIBLE_ROWS - height) / 2); else if (y < 0) - y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1); + y = max(0, (int)(VIDEO_VISIBLE_ROWS - height + y + 1)); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ /* @@ -1834,14 +1869,14 @@ static void plot_logo_or_black(void *screen, int width, int x, int y, int black) #ifdef CONFIG_SPLASH_SCREEN_ALIGN if (x == BMP_ALIGN_CENTER) - x = max(0, (VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2); + x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2); else if (x < 0) - x = max(0, VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1); + x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1)); if (y == BMP_ALIGN_CENTER) - y = max(0, (VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2); + y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2); else if (y < 0) - y = max(0, VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1); + y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1)); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE; @@ -1988,7 +2023,7 @@ static void *video_logo(void) * we need to adjust the logo height */ if (video_logo_ypos == BMP_ALIGN_CENTER) - video_logo_height += max(0, (VIDEO_VISIBLE_ROWS - \ + video_logo_height += max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2); else if (video_logo_ypos > 0) video_logo_height += video_logo_ypos; @@ -1996,6 +2031,8 @@ static void *video_logo(void) return video_fb_address + video_logo_height * VIDEO_LINE_LEN; } #endif + if (board_cfb_skip()) + return 0; sprintf(info, " %s", version_string); @@ -2076,6 +2113,24 @@ defined(CONFIG_SANDBOX) || defined(CONFIG_X86) return 0; } +void video_clear(void) +{ + if (!video_fb_address) + return; +#ifdef VIDEO_HW_RECTFILL + video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* dest pos x */ + 0, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS, /* frame height */ + bgx /* fill color */ + ); +#else + memsetl(video_fb_address, + (VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), bgx); +#endif +} + static int video_init(void) { unsigned char color8; @@ -2162,6 +2217,8 @@ static int video_init(void) } eorx = fgx ^ bgx; + video_clear(); + #ifdef CONFIG_VIDEO_LOGO /* Plot the logo and get start point of console */ debug("Video: Drawing the logo ...\n"); @@ -2184,15 +2241,12 @@ static int video_init(void) * Implement a weak default function for boards that optionally * need to skip the video initialization. */ -int __board_video_skip(void) +__weak int board_video_skip(void) { /* As default, don't skip test */ return 0; } -int board_video_skip(void) - __attribute__ ((weak, alias("__board_video_skip"))); - int drv_video_init(void) { int skip_dev_init; @@ -2205,6 +2259,9 @@ int drv_video_init(void) /* Init video chip - returns with framebuffer cleared */ skip_dev_init = (video_init() == -1); + if (board_cfb_skip()) + return 0; + #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) debug("KBD: Keyboard init ...\n"); skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1); @@ -2220,8 +2277,6 @@ int drv_video_init(void) console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; console_dev.putc = video_putc; /* 'putc' function */ console_dev.puts = video_puts; /* 'puts' function */ - console_dev.tstc = NULL; /* 'tstc' function */ - console_dev.getc = NULL; /* 'getc' function */ #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) /* Also init console device */ @@ -2262,21 +2317,3 @@ int video_get_screen_columns(void) { return CONSOLE_COLS; } - -void video_clear(void) -{ - if (!video_fb_address) - return; -#ifdef VIDEO_HW_RECTFILL - video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ - 0, /* dest pos x */ - 0, /* dest pos y */ - VIDEO_VISIBLE_COLS, /* frame width */ - VIDEO_VISIBLE_ROWS, /* frame height */ - bgx /* fill color */ - ); -#else - memsetl(video_fb_address, - (VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), bgx); -#endif -} diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index 8915bcf388..3a5f325cd3 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -18,41 +18,44 @@ #include #include #include -#include #include #include -#include +#include #include "videomodes.h" -#include +#include "da8xx-fb.h" + +#if !defined(DA8XX_LCD_CNTL_BASE) +#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE +#endif #define DRIVER_NAME "da8xx_lcdc" #define LCD_VERSION_1 1 #define LCD_VERSION_2 2 -#define BIT(x) (1 << (x)) - /* LCD Status Register */ -#define LCD_END_OF_FRAME1 BIT(9) -#define LCD_END_OF_FRAME0 BIT(8) -#define LCD_PL_LOAD_DONE BIT(6) -#define LCD_FIFO_UNDERFLOW BIT(5) -#define LCD_SYNC_LOST BIT(2) +#define LCD_END_OF_FRAME1 (1 << 9) +#define LCD_END_OF_FRAME0 (1 << 8) +#define LCD_PL_LOAD_DONE (1 << 6) +#define LCD_FIFO_UNDERFLOW (1 << 5) +#define LCD_SYNC_LOST (1 << 2) /* LCD DMA Control Register */ #define LCD_DMA_BURST_SIZE(x) ((x) << 4) -#define LCD_DMA_BURST_SIZE_MASK (0x7 << 4) #define LCD_DMA_BURST_1 0x0 #define LCD_DMA_BURST_2 0x1 #define LCD_DMA_BURST_4 0x2 #define LCD_DMA_BURST_8 0x3 #define LCD_DMA_BURST_16 0x4 -#define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) -#define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) -#define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) -#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) +#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2) +#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8) +#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9) +#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0) + +#define LCD_V2_TFT_24BPP_MODE (1 << 25) +#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) /* LCD Control Register */ #define LCD_CLK_DIVISOR(x) ((x) << 8) @@ -64,67 +67,67 @@ #define PALETTE_ONLY 0x01 #define DATA_ONLY 0x02 -#define LCD_MONO_8BIT_MODE BIT(9) -#define LCD_RASTER_ORDER BIT(8) -#define LCD_TFT_MODE BIT(7) -#define LCD_V1_UNDERFLOW_INT_ENA BIT(6) -#define LCD_V2_UNDERFLOW_INT_ENA BIT(5) -#define LCD_V1_PL_INT_ENA BIT(4) -#define LCD_V2_PL_INT_ENA BIT(6) -#define LCD_MONOCHROME_MODE BIT(1) -#define LCD_RASTER_ENABLE BIT(0) -#define LCD_TFT_ALT_ENABLE BIT(23) -#define LCD_STN_565_ENABLE BIT(24) -#define LCD_TFT24 BIT(25) -#define LCD_TFT24_UNPACKED BIT(26) -#define LCD_V2_DMA_CLK_EN BIT(2) -#define LCD_V2_LIDD_CLK_EN BIT(1) -#define LCD_V2_CORE_CLK_EN BIT(0) +#define LCD_MONO_8BIT_MODE (1 << 9) +#define LCD_RASTER_ORDER (1 << 8) +#define LCD_TFT_MODE (1 << 7) +#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6) +#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5) +#define LCD_V1_PL_INT_ENA (1 << 4) +#define LCD_V2_PL_INT_ENA (1 << 6) +#define LCD_MONOCHROME_MODE (1 << 1) +#define LCD_RASTER_ENABLE (1 << 0) +#define LCD_TFT_ALT_ENABLE (1 << 23) +#define LCD_STN_565_ENABLE (1 << 24) +#define LCD_V2_DMA_CLK_EN (1 << 2) +#define LCD_V2_LIDD_CLK_EN (1 << 1) +#define LCD_V2_CORE_CLK_EN (1 << 0) #define LCD_V2_LPP_B10 26 +#define LCD_V2_TFT_24BPP_MODE (1 << 25) +#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) /* LCD Raster Timing 2 Register */ #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) -#define LCD_SYNC_CTRL BIT(25) -#define LCD_SYNC_EDGE BIT(24) -#define LCD_INVERT_PIXEL_CLOCK BIT(22) -#define LCD_INVERT_LINE_CLOCK BIT(21) -#define LCD_INVERT_FRAME_CLOCK BIT(20) - -/* Clock reset register */ -#define LCD_CLK_MAIN_RESET BIT(3) - +#define LCD_SYNC_CTRL (1 << 25) +#define LCD_SYNC_EDGE (1 << 24) +#define LCD_INVERT_PIXEL_CLOCK (1 << 22) +#define LCD_INVERT_LINE_CLOCK (1 << 21) +#define LCD_INVERT_FRAME_CLOCK (1 << 20) + +/* Clock registers available only on Version 2 */ +#define LCD_CLK_MAIN_RESET (1 << 3) /* LCD Block */ struct da8xx_lcd_regs { - u32 revid; /* 0x00 */ - u32 ctrl; /* 0x04 */ - u32 stat; /* 0x08 */ - u32 lidd_ctrl; /* 0x0c */ - u32 lidd_cs0_conf; /* 0x10 */ - u32 lidd_cs0_addr; /* 0x14 */ - u32 lidd_cs0_data; /* 0x18 */ - u32 lidd_cs1_conf; /* 0x1c */ - u32 lidd_cs1_addr; /* 0x20 */ - u32 lidd_cs1_data; /* 0x24 */ - u32 raster_ctrl; /* 0x28 */ - u32 raster_timing_0; /* 0x2c */ - u32 raster_timing_1; /* 0x30 */ - u32 raster_timing_2; /* 0x34 */ - u32 raster_subpanel; /* 0x38 */ - u32 reserved; /* 0x3c */ - u32 dma_ctrl; /* 0x40 */ - u32 dma_frm_buf_base_addr_0; /* 0x44 */ - u32 dma_frm_buf_ceiling_addr_0; /* 0x48 */ - u32 dma_frm_buf_base_addr_1; /* 0x4c */ - u32 dma_frm_buf_ceiling_addr_1; /* 0x50 */ - u32 rsrvd1; /* 0x54 */ - u32 raw_stat; /* 0x58 */ - u32 masked_stat; /* 0x5c */ - u32 int_enable_set; /* 0x60 */ - u32 int_enable_clr; /* 0x64 */ - u32 end_of_int_ind; /* 0x68 */ - u32 clk_enable; /* 0x6c */ - u32 clk_reset; /* 0x70 */ + u32 revid; + u32 ctrl; + u32 stat; + u32 lidd_ctrl; + u32 lidd_cs0_conf; + u32 lidd_cs0_addr; + u32 lidd_cs0_data; + u32 lidd_cs1_conf; + u32 lidd_cs1_addr; + u32 lidd_cs1_data; + u32 raster_ctrl; + u32 raster_timing_0; + u32 raster_timing_1; + u32 raster_timing_2; + u32 raster_subpanel; + u32 reserved; + u32 dma_ctrl; + u32 dma_frm_buf_base_addr_0; + u32 dma_frm_buf_ceiling_addr_0; + u32 dma_frm_buf_base_addr_1; + u32 dma_frm_buf_ceiling_addr_1; + u32 resv1; + u32 raw_stat; + u32 masked_stat; + u32 int_ena_set; + u32 int_ena_clr; + u32 end_of_int_ind; + /* Clock registers available only on Version 2 */ + u32 clk_ena; + u32 clk_reset; }; #define LCD_NUM_BUFFERS 1 @@ -135,22 +138,26 @@ struct da8xx_lcd_regs { #define RIGHT_MARGIN 64 #define UPPER_MARGIN 32 #define LOWER_MARGIN 32 +#define WAIT_FOR_FRAME_DONE true +#define NO_WAIT_FOR_FRAME_DONE false -DECLARE_GLOBAL_DATA_PTR; +#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP) static struct da8xx_lcd_regs *da8xx_fb_reg_base; -static unsigned int lcd_revision; + +DECLARE_GLOBAL_DATA_PTR; /* graphics setup */ static GraphicDevice gpanel; static const struct da8xx_panel *lcd_panel; static struct fb_info *da8xx_fb_info; static int bits_x_pixel; -static u32 (*lcdc_irq_handler)(void); +static unsigned int lcd_revision; +const struct lcd_ctrl_config *da8xx_lcd_cfg; static inline unsigned int lcdc_read(u32 *addr) { - return readl(addr); + return (unsigned int)readl(addr); } static inline void lcdc_write(unsigned int val, u32 *addr) @@ -159,8 +166,8 @@ static inline void lcdc_write(unsigned int val, u32 *addr) } struct da8xx_fb_par { - unsigned long p_palette_base; - void *v_palette_base; + u32 p_palette_base; + unsigned char *v_palette_base; dma_addr_t vram_phys; unsigned long vram_size; void *vram_virt; @@ -176,6 +183,7 @@ struct da8xx_fb_par { int vsync_timeout; }; + /* Variable Screen Information */ static struct fb_var_screeninfo da8xx_fb_var = { .xoffset = 0, @@ -206,38 +214,23 @@ static struct fb_fix_screeninfo da8xx_fb_fix = { .accel = FB_ACCEL_NONE }; -static const struct display_panel disp_panel = { - .panel_type = QVGA, - .max_bpp = 24, - .min_bpp = 16, - .panel_shade = COLOR_ACTIVE, -}; - -static const struct lcd_ctrl_config lcd_cfg = { - &disp_panel, - .ac_bias = 255, - .ac_bias_intrpt = 0, - .dma_burst_sz = 16, - .bpp = 1 << LCD_BPP, - .fdd = 255, - .tft_alt_mode = 0, - .stn_565_mode = 0, - .mono_8bit_mode = 0, - .invert_line_clock = 1, - .invert_frm_clock = 1, - .sync_edge = 0, - .sync_ctrl = 1, - .raster_order = 0, -}; - /* Enable the Raster Engine of the LCD Controller */ static inline void lcd_enable_raster(void) { u32 reg; + /* Put LCDC in reset for several cycles */ + if (lcd_revision == LCD_VERSION_2) + lcdc_write(LCD_CLK_MAIN_RESET, + &da8xx_fb_reg_base->clk_reset); + + udelay(1000); /* Bring LCDC out of reset */ if (lcd_revision == LCD_VERSION_2) - lcdc_write(0, &da8xx_fb_reg_base->clk_reset); + lcdc_write(0, + &da8xx_fb_reg_base->clk_reset); + + udelay(1000); reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); if (!(reg & LCD_RASTER_ENABLE)) @@ -246,17 +239,40 @@ static inline void lcd_enable_raster(void) } /* Disable the Raster Engine of the LCD Controller */ -static inline void lcd_disable_raster(void) +static inline void lcd_disable_raster(bool wait_for_frame_done) { u32 reg; + u32 loop_cnt = 0; + u32 stat; + u32 i = 0; + + if (wait_for_frame_done) + loop_cnt = 5000; reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); if (reg & LCD_RASTER_ENABLE) lcdc_write(reg & ~LCD_RASTER_ENABLE, &da8xx_fb_reg_base->raster_ctrl); - if (lcd_revision == LCD_VERSION_2) - /* Write 1 to reset LCDC */ - lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); + + /* Wait for the current frame to complete */ + do { + if (lcd_revision == LCD_VERSION_1) + stat = lcdc_read(&da8xx_fb_reg_base->stat); + else + stat = lcdc_read(&da8xx_fb_reg_base->raw_stat); + + mdelay(1); + } while (!(stat & 0x01) && (i++ < loop_cnt)); + + if (lcd_revision == LCD_VERSION_1) + lcdc_write(stat, &da8xx_fb_reg_base->stat); + else + lcdc_write(stat, &da8xx_fb_reg_base->raw_stat); + + if ((loop_cnt != 0) && (i >= loop_cnt)) { + printf("LCD Controller timed out\n"); + return; + } } static void lcd_blit(int load_mode, struct da8xx_fb_par *par) @@ -281,12 +297,13 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par) if (lcd_revision == LCD_VERSION_1) { reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; } else { - reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) | + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | LCD_V2_END_OF_FRAME0_INT_ENA | - LCD_V2_END_OF_FRAME1_INT_ENA; - lcdc_write(reg_int, - &da8xx_fb_reg_base->int_enable_set); + LCD_V2_END_OF_FRAME1_INT_ENA | + LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST; + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); } + #if (LCD_NUM_BUFFERS == 2) reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); @@ -300,19 +317,20 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par) lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); #endif + } else if (load_mode == LOAD_PALETTE) { start = par->p_palette_base; end = start + par->palette_sz - 1; reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); - if (lcd_revision == LCD_VERSION_1) { reg_ras |= LCD_V1_PL_INT_ENA; } else { - reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) | + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | LCD_V2_PL_INT_ENA; - lcdc_write(reg_int, &da8xx_fb_reg_base->int_enable_set); + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); } + lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); } @@ -332,8 +350,7 @@ static int lcd_cfg_dma(int burst_size) { u32 reg; - reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl); - reg &= ~LCD_DMA_BURST_SIZE_MASK; + reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001; switch (burst_size) { case 1: reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); @@ -400,9 +417,7 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | LCD_MONO_8BIT_MODE | - LCD_MONOCHROME_MODE | - LCD_TFT24 | - LCD_TFT24_UNPACKED); + LCD_MONOCHROME_MODE); switch (cfg->p_disp_panel->panel_shade) { case MONOCHROME: @@ -429,13 +444,9 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) if (lcd_revision == LCD_VERSION_1) { reg |= LCD_V1_UNDERFLOW_INT_ENA; } else { - if (bits_x_pixel >= 24) - reg |= LCD_TFT24; - if (cfg->bpp == 32) - reg |= LCD_TFT24_UNPACKED; - reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) | + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | LCD_V2_UNDERFLOW_INT_ENA; - lcdc_write(reg_int, &da8xx_fb_reg_base->int_enable_set); + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); } lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); @@ -474,11 +485,10 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, /* Set the Panel Width */ /* Pixels per line = (PPL + 1)*16 */ - /* Pixels per line = (PPL + 1)*16 */ if (lcd_revision == LCD_VERSION_1) { /* - * 0x3F in bits 4..9 gives max horizontal resolution = 1024 - * pixels. + * 0x3F in bits 4..9 gives max horisontal resolution = 1024 + * pixels */ width &= 0x3f0; } else { @@ -488,7 +498,6 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, */ width &= 0x7f0; } - reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); reg &= 0xfffffc00; if (lcd_revision == LCD_VERSION_1) { @@ -516,6 +525,13 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); if (raster_order) reg |= LCD_RASTER_ORDER; + + if (bpp == 24) + reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE); + else if (bpp == 32) + reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE + | LCD_V2_TFT_24BPP_UNPACK); + lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); switch (bpp) { @@ -524,6 +540,7 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, case 4: case 16: case 24: + case 32: par->palette_sz = 16 * 2; break; @@ -543,7 +560,7 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, struct fb_info *info) { struct da8xx_fb_par *par = info->par; - unsigned short *palette = par->v_palette_base; + unsigned short *palette = (unsigned short *) par->v_palette_base; u_short pal; int update_hw = 0; @@ -566,7 +583,7 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, update_hw = 1; palette[regno] = pal; } - } else if ((info->var.bits_per_pixel >= 16) && regno < 16) { + } else if ((info->var.bits_per_pixel == 16) && regno < 16) { red >>= (16 - info->var.red.length); red <<= info->var.red.offset; @@ -578,6 +595,23 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, par->pseudo_palette[regno] = red | green | blue; + if (palette[0] != 0x4000) { + update_hw = 1; + palette[0] = 0x4000; + } + } else if (((info->var.bits_per_pixel == 32) && regno < 32) || + ((info->var.bits_per_pixel == 24) && regno < 24)) { + red >>= (24 - info->var.red.length); + red <<= info->var.red.offset; + + green >>= (24 - info->var.green.length); + green <<= info->var.green.offset; + + blue >>= (24 - info->var.blue.length); + blue <<= info->var.blue.offset; + + par->pseudo_palette[regno] = red | green | blue; + if (palette[0] != 0x4000) { update_hw = 1; palette[0] = 0x4000; @@ -594,14 +628,14 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, static void lcd_reset(struct da8xx_fb_par *par) { /* Disable the Raster if previously Enabled */ - lcd_disable_raster(); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); /* DMA has to be disabled */ lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); if (lcd_revision == LCD_VERSION_2) { - lcdc_write(0, &da8xx_fb_reg_base->int_enable_set); + lcdc_write(0, &da8xx_fb_reg_base->int_ena_set); /* Write 1 to reset */ lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); lcdc_write(0, &da8xx_fb_reg_base->clk_reset); @@ -612,32 +646,21 @@ static void lcd_calc_clk_divider(struct da8xx_fb_par *par) { unsigned int lcd_clk, div; -#ifndef CONFIG_AM33XX /* Get clock from sysclk2 */ lcd_clk = clk_get(2); -#else - lcd_clk = lcdc_clk_rate(); -#endif - /* calculate divisor so that the resulting clock is rounded down */ - div = (lcd_clk + par->pxl_clk - 1)/ par->pxl_clk; - if (div > 255) - div = 255; - if (div < 2) - div = 2; - - debug("LCD Clock: %u.%03uMHz Divider: 0x%08x PixClk requested: %u.%03uMHz actual: %u.%03uMHz\n", - lcd_clk / 1000000, lcd_clk / 1000 % 1000, div, - par->pxl_clk / 1000000, par->pxl_clk / 1000 % 1000, - lcd_clk / div / 1000000, lcd_clk / div / 1000 % 1000); + + div = lcd_clk / par->pxl_clk; + debug("LCD Clock: %d Divider: %d PixClk: %d\n", + lcd_clk, div, par->pxl_clk); /* Configure the LCD clock divisor. */ - lcdc_write(LCD_CLK_DIVISOR(div) | LCD_RASTER_MODE, - &da8xx_fb_reg_base->ctrl); + lcdc_write(LCD_CLK_DIVISOR(div) | + (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); if (lcd_revision == LCD_VERSION_2) lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | - LCD_V2_CORE_CLK_EN, &da8xx_fb_reg_base->clk_enable); - + LCD_V2_CORE_CLK_EN, + &da8xx_fb_reg_base->clk_ena); } static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, @@ -672,12 +695,13 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); - /* Configure for display */ + /* Configure for disply */ ret = lcd_cfg_display(cfg); if (ret < 0) return ret; - if (QVGA != cfg->p_disp_panel->panel_type) + if ((QVGA != cfg->p_disp_panel->panel_type) && + (WVGA != cfg->p_disp_panel->panel_type)) return -EINVAL; if (cfg->bpp <= cfg->p_disp_panel->max_bpp && @@ -713,21 +737,18 @@ static void lcdc_dma_start(void) &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); } -/* IRQ handler for version 2 of LCDC */ -static u32 lcdc_irq_handler_rev02(void) +static u32 lcdc_irq_handler_rev01(void) { - u32 ret = 0; struct da8xx_fb_par *par = da8xx_fb_info->par; - u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat); - - debug("%s: stat=%08x\n", __func__, stat); + u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); + u32 reg_ras; if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { debug("LCD_SYNC_LOST\n"); - lcd_disable_raster(); - lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + lcdc_write(stat, &da8xx_fb_reg_base->stat); lcd_enable_raster(); - ret = LCD_SYNC_LOST; + return LCD_SYNC_LOST; } else if (stat & LCD_PL_LOAD_DONE) { debug("LCD_PL_LOAD_DONE\n"); /* @@ -736,55 +757,46 @@ static u32 lcdc_irq_handler_rev02(void) * interrupt via the following write to the status register. If * this is done after then one gets multiple PL done interrupts. */ - lcd_disable_raster(); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); - lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + lcdc_write(stat, &da8xx_fb_reg_base->stat); /* Disable PL completion inerrupt */ - lcdc_write(LCD_V2_PL_INT_ENA, - &da8xx_fb_reg_base->int_enable_clr); + reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); + reg_ras &= ~LCD_V1_PL_INT_ENA; + lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); /* Setup and start data loading mode */ lcd_blit(LOAD_DATA, par); - ret = LCD_PL_LOAD_DONE; - } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) { - par->vsync_flag = 1; - lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + return LCD_PL_LOAD_DONE; + } else { + lcdc_write(stat, &da8xx_fb_reg_base->stat); - if (stat & LCD_END_OF_FRAME0) { + if (stat & LCD_END_OF_FRAME0) debug("LCD_END_OF_FRAME0\n"); - lcdc_write(par->dma_start, - &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); - lcdc_write(par->dma_end, - &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); - } - if (stat & LCD_END_OF_FRAME1) { - debug("LCD_END_OF_FRAME1\n"); - lcdc_write(par->dma_start, - &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); - lcdc_write(par->dma_end, - &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); - par->vsync_flag = 1; - } - ret = (stat & LCD_END_OF_FRAME0) ? - LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1; + lcdc_write(par->dma_start, + &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(par->dma_end, + &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + par->vsync_flag = 1; + return LCD_END_OF_FRAME0; } - lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); - return ret; + return stat; } -static u32 lcdc_irq_handler_rev01(void) +static u32 lcdc_irq_handler_rev02(void) { struct da8xx_fb_par *par = da8xx_fb_info->par; - u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); - u32 reg_ras; + u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat); + u32 reg_int; if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { debug("LCD_SYNC_LOST\n"); - lcd_disable_raster(); - lcdc_write(stat, &da8xx_fb_reg_base->stat); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); lcd_enable_raster(); + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); return LCD_SYNC_LOST; } else if (stat & LCD_PL_LOAD_DONE) { debug("LCD_PL_LOAD_DONE\n"); @@ -794,56 +806,54 @@ static u32 lcdc_irq_handler_rev01(void) * interrupt via the following write to the status register. If * this is done after then one gets multiple PL done interrupts. */ - lcd_disable_raster(); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); - lcdc_write(stat, &da8xx_fb_reg_base->stat); + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); /* Disable PL completion inerrupt */ - reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); - reg_ras &= ~LCD_V1_PL_INT_ENA; - lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) | + (LCD_V2_PL_INT_ENA); + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); /* Setup and start data loading mode */ lcd_blit(LOAD_DATA, par); + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); return LCD_PL_LOAD_DONE; - } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) { - par->vsync_flag = 1; - lcdc_write(stat, &da8xx_fb_reg_base->stat); + } else { + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); - if (stat & LCD_END_OF_FRAME0) { + if (stat & LCD_END_OF_FRAME0) debug("LCD_END_OF_FRAME0\n"); - lcdc_write(par->dma_start, - &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); - lcdc_write(par->dma_end, - &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); - } - - if (stat & LCD_END_OF_FRAME1) { - debug("LCD_END_OF_FRAME1\n"); - lcdc_write(par->dma_start, - &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); - lcdc_write(par->dma_end, - &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); - } - - return (stat & LCD_END_OF_FRAME0) ? - LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1; + lcdc_write(par->dma_start, + &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(par->dma_end, + &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + par->vsync_flag = 1; + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return LCD_END_OF_FRAME0; } + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); return stat; } +static u32 lcdc_irq_handler(void) +{ + if (lcd_revision == LCD_VERSION_1) + return lcdc_irq_handler_rev01(); + else + return lcdc_irq_handler_rev02(); +} + static u32 wait_for_event(u32 event) { - int timeout = 100; + u32 timeout = 50000; u32 ret; do { ret = lcdc_irq_handler(); - if (ret & event) - break; udelay(1000); - } while (--timeout > 0); + } while (!(ret & event)); if (timeout <= 0) { printf("%s: event %d not hit\n", __func__, event); @@ -858,19 +868,23 @@ void *video_hw_init(void) { struct da8xx_fb_par *par; u32 size; + u32 rev; char *p; if (!lcd_panel) { printf("Display not initialized\n"); return NULL; } - gpanel.winSizeX = lcd_panel->width; gpanel.winSizeY = lcd_panel->height; gpanel.plnSizeX = lcd_panel->width; gpanel.plnSizeY = lcd_panel->height; switch (bits_x_pixel) { + case 32: + gpanel.gdfBytesPP = 4; + gpanel.gdfIndex = GDF_32BIT_X888RGB; + break; case 24: gpanel.gdfBytesPP = 4; gpanel.gdfIndex = GDF_32BIT_X888RGB; @@ -882,36 +896,36 @@ void *video_hw_init(void) default: gpanel.gdfBytesPP = 1; gpanel.gdfIndex = GDF__8BIT_INDEX; + break; } - da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE; + da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE; /* Determine LCD IP Version */ - - lcd_revision = lcdc_read(&da8xx_fb_reg_base->revid); - switch (lcd_revision & 0xfff00000) { - case 0x4C100000: + rev = lcdc_read(&da8xx_fb_reg_base->revid); + switch (rev) { + case 0x4C100102: lcd_revision = LCD_VERSION_1; break; - - case 0x4F200000: + case 0x4F200800: + case 0x4F201000: lcd_revision = LCD_VERSION_2; break; - default: - printf("Unknown PID Reg value 0x%08x, defaulting to LCD revision 1\n", - lcd_revision); + printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n", + rev); lcd_revision = LCD_VERSION_1; + break; } - debug("Resolution: %dx%d %d\n", - gpanel.winSizeX, - gpanel.winSizeY, - lcd_cfg.bpp); + debug("rev: 0x%x Resolution: %dx%d %d\n", rev, + gpanel.winSizeX, + gpanel.winSizeY, + da8xx_lcd_cfg->bpp); size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par); da8xx_fb_info = malloc(size); - debug("da8xx_fb_info at %p\n", da8xx_fb_info); + debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info); if (!da8xx_fb_info) { printf("Memory allocation failed for fb_info\n"); @@ -925,36 +939,34 @@ void *video_hw_init(void) par = da8xx_fb_info->par; par->pxl_clk = lcd_panel->pxl_clk; - if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) { + if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) { printf("lcd_init failed\n"); goto err_release_fb; } /* allocate frame buffer */ - par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp; + par->vram_size = lcd_panel->width * lcd_panel->height * + da8xx_lcd_cfg->bpp; par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8; -#ifdef CONFIG_LCD - par->vram_virt = (void *)gd->fb_base; -#else par->vram_virt = malloc(par->vram_size); -#endif + par->vram_phys = (dma_addr_t) par->vram_virt; - debug("Requesting 0x%lx bytes for framebuffer at 0x%p\n", - par->vram_size, par->vram_virt); + debug("Requesting 0x%x bytes for framebuffer at 0x%x\n", + (unsigned int)par->vram_size, + (unsigned int)par->vram_virt); if (!par->vram_virt) { printf("GLCD: malloc for frame buffer failed\n"); goto err_release_fb; } + gd->fb_base = (int)par->vram_virt; gpanel.frameAdrs = (unsigned int)par->vram_virt; - da8xx_fb_info->screen_base = par->vram_virt; + da8xx_fb_info->screen_base = (char *) par->vram_virt; da8xx_fb_fix.smem_start = gpanel.frameAdrs; da8xx_fb_fix.smem_len = par->vram_size; - da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8; - debug("%s: vram_virt: %p size %ux%u=%lu bpp %u\n", __func__, - par->vram_virt, lcd_panel->width, lcd_panel->height, - par->vram_size, lcd_cfg.bpp); + da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8; + par->dma_start = par->vram_phys; par->dma_end = par->dma_start + lcd_panel->height * da8xx_fb_fix.line_length - 1; @@ -966,9 +978,11 @@ void *video_hw_init(void) goto err_release_fb_mem; } memset(par->v_palette_base, 0, PALETTE_SIZE); - par->p_palette_base = (unsigned long)par->v_palette_base; + par->p_palette_base = (unsigned int)par->v_palette_base; + + /* Initialize par */ + da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp; - /* Initialize var */ da8xx_fb_var.xres = lcd_panel->width; da8xx_fb_var.xres_virtual = lcd_panel->width; @@ -976,8 +990,8 @@ void *video_hw_init(void) da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS; da8xx_fb_var.grayscale = - lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; - da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp; + da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; + da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp; da8xx_fb_var.hsync_len = lcd_panel->hsw; da8xx_fb_var.vsync_len = lcd_panel->vsw; @@ -990,16 +1004,14 @@ void *video_hw_init(void) da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; + /* Clear interrupt */ + memset((void *)par->vram_virt, 0, par->vram_size); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); if (lcd_revision == LCD_VERSION_1) - lcdc_irq_handler = lcdc_irq_handler_rev01; + lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); else - lcdc_irq_handler = lcdc_irq_handler_rev02; - - /* Clear interrupt */ - memset(par->vram_virt, 0, par->vram_size); - lcd_disable_raster(); - lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); - debug("Palette at 0x%08lx size %u\n", par->p_palette_base, + lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat); + debug("Palette at 0x%x size %d\n", par->p_palette_base, par->palette_sz); lcdc_dma_start(); @@ -1012,12 +1024,10 @@ void *video_hw_init(void) /* Wait until DMA is working */ wait_for_event(LCD_END_OF_FRAME0); - return &gpanel; + return (void *)&gpanel; err_release_fb_mem: -#ifndef CONFIG_LCD free(par->vram_virt); -#endif err_release_fb: free(da8xx_fb_info); @@ -1025,21 +1035,20 @@ err_release_fb: return NULL; } -void da8xx_fb_disable(void) -{ - lcd_reset(da8xx_fb_info->par); -} - void video_set_lut(unsigned int index, /* color number */ unsigned char r, /* red */ unsigned char g, /* green */ unsigned char b /* blue */ ) { + + return; } -void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel) +void da8xx_video_init(const struct da8xx_panel *panel, + const struct lcd_ctrl_config *lcd_cfg, int bits_pixel) { lcd_panel = panel; + da8xx_lcd_cfg = lcd_cfg; bits_x_pixel = bits_pixel; } diff --git a/arch/arm/include/asm/arch-davinci/da8xx-fb.h b/drivers/video/da8xx-fb.h similarity index 94% rename from arch/arm/include/asm/arch-davinci/da8xx-fb.h rename to drivers/video/da8xx-fb.h index c115034f06..6447a4047d 100644 --- a/arch/arm/include/asm/arch-davinci/da8xx-fb.h +++ b/drivers/video/da8xx-fb.h @@ -17,7 +17,8 @@ #define DA8XX_FB_H enum panel_type { - QVGA = 0 + QVGA = 0, + WVGA }; enum panel_shade { @@ -108,6 +109,8 @@ struct lcd_sync_arg { int pulse_width; }; -void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel); +void da8xx_video_init(const struct da8xx_panel *panel, + const struct lcd_ctrl_config *lcd_cfg, + int bits_pixel); #endif /* ifndef DA8XX_FB_H */ diff --git a/drivers/video/exynos_dp.c b/drivers/video/exynos_dp.c index f5c34a980d..f60b060ec1 100644 --- a/drivers/video/exynos_dp.c +++ b/drivers/video/exynos_dp.c @@ -3,12 +3,13 @@ * * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#include #include #include #include diff --git a/drivers/video/exynos_dp_lowlevel.c b/drivers/video/exynos_dp_lowlevel.c index ef11b466f6..bf0ea108e8 100644 --- a/drivers/video/exynos_dp_lowlevel.c +++ b/drivers/video/exynos_dp_lowlevel.c @@ -3,7 +3,7 @@ * * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/drivers/video/exynos_dp_lowlevel.h b/drivers/video/exynos_dp_lowlevel.h index ae2bcd646e..8651681520 100644 --- a/drivers/video/exynos_dp_lowlevel.h +++ b/drivers/video/exynos_dp_lowlevel.h @@ -3,7 +3,7 @@ * * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _EXYNOS_EDP_LOWLEVEL_H diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 5c7ec9199b..be35b982ac 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -27,17 +27,13 @@ DECLARE_GLOBAL_DATA_PTR; static unsigned int panel_width, panel_height; -/* - * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs - * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve - * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt() - * is called. So, we are forced to statically assign it. - */ #ifdef CONFIG_OF_CONTROL vidinfo_t panel_info = { - .vl_col = LCD_XRES, - .vl_row = LCD_YRES, - .vl_bpix = LCD_COLOR16, + /* + * Insert a value here so that we don't end up in the BSS + * Reference: drivers/video/tegra.c + */ + .vl_col = -1, }; #endif @@ -62,72 +58,38 @@ static void exynos_lcd_init(vidinfo_t *vid) lcd_set_flush_dcache(1); } -#ifdef CONFIG_CMD_BMP -static void draw_logo(void) +__weak void exynos_cfg_lcd_gpio(void) { - int x, y; - ulong addr; - - if (panel_width >= panel_info.logo_width) { - x = ((panel_width - panel_info.logo_width) >> 1); - } else { - x = 0; - printf("Warning: image width is bigger than display width\n"); - } - - if (panel_height >= panel_info.logo_height) { - y = ((panel_height - panel_info.logo_height) >> 1) - 4; - } else { - y = 0; - printf("Warning: image height is bigger than display height\n"); - } - - addr = panel_info.logo_addr; - bmp_display(addr, x, y); } -#endif -void __exynos_cfg_lcd_gpio(void) +__weak void exynos_backlight_on(unsigned int onoff) { } -void exynos_cfg_lcd_gpio(void) - __attribute__((weak, alias("__exynos_cfg_lcd_gpio"))); -void __exynos_backlight_on(unsigned int onoff) +__weak void exynos_reset_lcd(void) { } -void exynos_backlight_on(unsigned int onoff) - __attribute__((weak, alias("__exynos_cfg_lcd_gpio"))); -void __exynos_reset_lcd(void) +__weak void exynos_lcd_power_on(void) { } -void exynos_reset_lcd(void) - __attribute__((weak, alias("__exynos_reset_lcd"))); -void __exynos_lcd_power_on(void) +__weak void exynos_cfg_ldo(void) { } -void exynos_lcd_power_on(void) - __attribute__((weak, alias("__exynos_lcd_power_on"))); -void __exynos_cfg_ldo(void) +__weak void exynos_enable_ldo(unsigned int onoff) { } -void exynos_cfg_ldo(void) - __attribute__((weak, alias("__exynos_cfg_ldo"))); -void __exynos_enable_ldo(unsigned int onoff) +__weak void exynos_backlight_reset(void) { } -void exynos_enable_ldo(unsigned int onoff) - __attribute__((weak, alias("__exynos_enable_ldo"))); -void __exynos_backlight_reset(void) +__weak int exynos_lcd_misc_init(vidinfo_t *vid) { + return 0; } -void exynos_backlight_reset(void) - __attribute__((weak, alias("__exynos_backlight_reset"))); static void lcd_panel_on(vidinfo_t *vid) { @@ -159,7 +121,7 @@ static void lcd_panel_on(vidinfo_t *vid) } #ifdef CONFIG_OF_CONTROL -int exynos_fimd_parse_dt(const void *blob) +int exynos_lcd_early_init(const void *blob) { unsigned int node; node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); @@ -304,12 +266,15 @@ void lcd_ctrl_init(void *lcdbase) set_lcd_clk(); #ifdef CONFIG_OF_CONTROL - if (exynos_fimd_parse_dt(gd->fdt_blob)) - debug("Can't get proper panel info\n"); +#ifdef CONFIG_EXYNOS_MIPI_DSIM + exynos_init_dsim_platform_data(&panel_info); +#endif + exynos_lcd_misc_init(&panel_info); #else /* initialize parameters which is specific to panel. */ init_panel_info(&panel_info); #endif + panel_width = panel_info.vl_width; panel_height = panel_info.vl_height; @@ -323,9 +288,6 @@ void lcd_enable(void) if (panel_info.logo_on) { memset((void *) gd->fb_base, 0, panel_width * panel_height * (NBITS(panel_info.vl_bpix) >> 3)); -#ifdef CONFIG_CMD_BMP - draw_logo(); -#endif } lcd_panel_on(&panel_info); diff --git a/drivers/video/exynos_fb.h b/drivers/video/exynos_fb.h index 00cf60c45f..2c2f94bd03 100644 --- a/drivers/video/exynos_fb.h +++ b/drivers/video/exynos_fb.h @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _EXYNOS_FB_H_ diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index 8c2de4ed29..f67fa817ed 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -73,18 +73,19 @@ static void exynos_fimd_set_par(unsigned int win_id) /* DATAPATH is DMA */ cfg |= EXYNOS_WINCON_DATAPATH_DMA; - if (pvid->logo_on) /* To get proprietary LOGO */ - cfg |= EXYNOS_WINCON_WSWP_ENABLE; - else /* To get output console on LCD */ - cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; + cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; /* dma burst is 16 */ cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; - if (pvid->logo_on) /* To get proprietary LOGO */ - cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; - else /* To get output console on LCD */ + switch (pvid->vl_bpix) { + case 4: cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; + break; + default: + cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; + break; + } writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + EXYNOS_WINCON(win_id)); @@ -250,6 +251,45 @@ void exynos_fimd_window_off(unsigned int win_id) writel(cfg, &fimd_ctrl->winshmap); } +#ifdef CONFIG_OF_CONTROL +/* +* The reset value for FIMD SYSMMU register MMU_CTRL is 3 +* on Exynos5420 and newer versions. +* This means FIMD SYSMMU is on by default on Exynos5420 +* and newer versions. +* Since in u-boot we don't use SYSMMU, we should disable +* those FIMD SYSMMU. +* Note that there are 2 SYSMMU for FIMD: m0 and m1. +* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3. +* We disable both of them here. +*/ +void exynos_fimd_disable_sysmmu(void) +{ + u32 *sysmmufimd; + unsigned int node; + int node_list[2]; + int count; + int i; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd", + COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2); + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) { + debug("Can't get device node for fimd sysmmu\n"); + return; + } + + sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); + if (!sysmmufimd) { + debug("Can't get base address for sysmmu fimdm0"); + return; + } + + writel(0x0, sysmmufimd); + } +} +#endif void exynos_fimd_lcd_init(vidinfo_t *vid) { @@ -267,6 +307,10 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) node, "reg"); if (fimd_ctrl == NULL) debug("Can't get the FIMD base address\n"); + + if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu")) + exynos_fimd_disable_sysmmu(); + #else fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd(); #endif diff --git a/drivers/video/exynos_mipi_dsi.c b/drivers/video/exynos_mipi_dsi.c index 3e7158d30e..c68ebd6f7b 100644 --- a/drivers/video/exynos_mipi_dsi.c +++ b/drivers/video/exynos_mipi_dsi.c @@ -4,11 +4,14 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include +#include +#include #include #include #include @@ -22,7 +25,14 @@ #define master_to_driver(a) (a->dsim_lcd_drv) #define master_to_device(a) (a->dsim_lcd_dev) +DECLARE_GLOBAL_DATA_PTR; + static struct exynos_platform_mipi_dsim *dsim_pd; +#ifdef CONFIG_OF_CONTROL +static struct mipi_dsim_config dsim_config_dt; +static struct exynos_platform_mipi_dsim dsim_platform_data_dt; +static struct mipi_dsim_lcd_device mipi_lcd_device_dt; +#endif struct mipi_dsim_ddi { int bus_id; @@ -238,3 +248,90 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd) dsim_pd = pd; } + +#ifdef CONFIG_OF_CONTROL +int exynos_dsim_config_parse_dt(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI); + if (node <= 0) { + printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n"); + return -ENODEV; + } + + dsim_config_dt.e_interface = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-interface", 0); + + dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-virtual-ch", 0); + + dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-pixel-format", 0); + + dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-burst-mode", 0); + + dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-no-data-lane", 0); + + dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-byte-clk", 0); + + dsim_config_dt.hfp = fdtdec_get_int(blob, node, + "samsung,dsim-config-hfp", 0); + + dsim_config_dt.p = fdtdec_get_int(blob, node, + "samsung,dsim-config-p", 0); + dsim_config_dt.m = fdtdec_get_int(blob, node, + "samsung,dsim-config-m", 0); + dsim_config_dt.s = fdtdec_get_int(blob, node, + "samsung,dsim-config-s", 0); + + dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node, + "samsung,dsim-config-pll-stable-time", 0); + + dsim_config_dt.esc_clk = fdtdec_get_int(blob, node, + "samsung,dsim-config-esc-clk", 0); + + dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node, + "samsung,dsim-config-stop-holding-cnt", 0); + + dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-bta-timeout", 0); + + dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-rx-timeout", 0); + + mipi_lcd_device_dt.name = fdtdec_get_config_string(blob, + "samsung,dsim-device-name"); + + mipi_lcd_device_dt.id = fdtdec_get_int(blob, node, + "samsung,dsim-device-id", 0); + + mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node, + "samsung,dsim-device-bus_id", 0); + + mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node, + "samsung,dsim-device-reverse-panel", 0); + + return 0; +} + +void exynos_init_dsim_platform_data(vidinfo_t *vid) +{ + if (exynos_dsim_config_parse_dt(gd->fdt_blob)) + debug("Can't get proper dsim config.\n"); + + strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name); + dsim_platform_data_dt.dsim_config = &dsim_config_dt; + dsim_platform_data_dt.mipi_power = mipi_power; + dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl; + dsim_platform_data_dt.lcd_panel_info = (void *)vid; + + mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt; + exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt); + + dsim_pd = &dsim_platform_data_dt; +} +#endif diff --git a/drivers/video/exynos_mipi_dsi_common.c b/drivers/video/exynos_mipi_dsi_common.c index 2cc847f6e1..925d51500a 100644 --- a/drivers/video/exynos_mipi_dsi_common.c +++ b/drivers/video/exynos_mipi_dsi_common.c @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -50,7 +50,7 @@ static unsigned int dpll_table[15] = { }; static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim, - unsigned int data0, unsigned int data1) + const unsigned char *data0, unsigned int data1) { unsigned int data_cnt = 0, payload = 0; @@ -62,42 +62,40 @@ static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim, */ if ((data1 - data_cnt) < 4) { if ((data1 - data_cnt) == 3) { - payload = *(u8 *)(data0 + data_cnt) | - (*(u8 *)(data0 + (data_cnt + 1))) << 8 | - (*(u8 *)(data0 + (data_cnt + 2))) << 16; + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8 | + data0[data_cnt + 2] << 16; debug("count = 3 payload = %x, %x %x %x\n", - payload, *(u8 *)(data0 + data_cnt), - *(u8 *)(data0 + (data_cnt + 1)), - *(u8 *)(data0 + (data_cnt + 2))); + payload, data0[data_cnt], + data0[data_cnt + 1], + data0[data_cnt + 2]); } else if ((data1 - data_cnt) == 2) { - payload = *(u8 *)(data0 + data_cnt) | - (*(u8 *)(data0 + (data_cnt + 1))) << 8; + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8; debug("count = 2 payload = %x, %x %x\n", payload, - *(u8 *)(data0 + data_cnt), - *(u8 *)(data0 + (data_cnt + 1))); + data0[data_cnt], data0[data_cnt + 1]); } else if ((data1 - data_cnt) == 1) { - payload = *(u8 *)(data0 + data_cnt); + payload = data0[data_cnt]; } } else { /* send 4bytes per one time. */ - payload = *(u8 *)(data0 + data_cnt) | - (*(u8 *)(data0 + (data_cnt + 1))) << 8 | - (*(u8 *)(data0 + (data_cnt + 2))) << 16 | - (*(u8 *)(data0 + (data_cnt + 3))) << 24; + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8 | + data0[data_cnt + 2] << 16 | + data0[data_cnt + 3] << 24; debug("count = 4 payload = %x, %x %x %x %x\n", payload, *(u8 *)(data0 + data_cnt), - *(u8 *)(data0 + (data_cnt + 1)), - *(u8 *)(data0 + (data_cnt + 2)), - *(u8 *)(data0 + (data_cnt + 3))); - + data0[data_cnt + 1], + data0[data_cnt + 2], + data0[data_cnt + 3]); } exynos_mipi_dsi_wr_tx_data(dsim, payload); } } int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, - unsigned int data0, unsigned int data1) + const unsigned char *data0, unsigned int data1) { unsigned int timeout = TRY_GET_FIFO_TIMEOUT; unsigned long delay_val, delay; @@ -136,8 +134,8 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, case MIPI_DSI_DCS_SHORT_WRITE_PARAM: case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: debug("data0 = %x data1 = %x\n", - data0, data1); - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1); + data0[0], data0[1]); + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); if (check_rx_ack) { /* process response func should be implemented */ return 0; @@ -150,7 +148,7 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, case MIPI_DSI_COLOR_MODE_ON: case MIPI_DSI_SHUTDOWN_PERIPHERAL: case MIPI_DSI_TURN_ON_PERIPHERAL: - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1); + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); if (check_rx_ack) { /* process response func should be implemented. */ return 0; @@ -172,7 +170,7 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: case MIPI_DSI_DCS_READ: exynos_mipi_dsi_clear_all_interrupt(dsim); - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1); + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); /* process response func should be implemented. */ return 0; @@ -183,21 +181,19 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, case MIPI_DSI_GENERIC_LONG_WRITE: case MIPI_DSI_DCS_LONG_WRITE: { - unsigned int data_cnt = 0, payload = 0; + unsigned int payload = 0; /* if data count is less then 4, then send 3bytes data. */ if (data1 < 4) { - payload = *(u8 *)(data0) | - *(u8 *)(data0 + 1) << 8 | - *(u8 *)(data0 + 2) << 16; + payload = data0[0] | + data0[1] << 8 | + data0[2] << 16; exynos_mipi_dsi_wr_tx_data(dsim, payload); debug("count = %d payload = %x,%x %x %x\n", - data1, payload, - *(u8 *)(data0 + data_cnt), - *(u8 *)(data0 + (data_cnt + 1)), - *(u8 *)(data0 + (data_cnt + 2))); + data1, payload, data0[0], + data0[1], data0[2]); } else { /* in case that data count is more then 4 */ exynos_mipi_dsi_long_data_wr(dsim, data0, data1); diff --git a/drivers/video/exynos_mipi_dsi_common.h b/drivers/video/exynos_mipi_dsi_common.h index 318c7ecec3..98eb78e5f0 100644 --- a/drivers/video/exynos_mipi_dsi_common.h +++ b/drivers/video/exynos_mipi_dsi_common.h @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -13,7 +13,7 @@ #define _EXYNOS_MIPI_DSI_COMMON_H int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, - unsigned int data0, unsigned int data1); + const unsigned char *data0, unsigned int data1); int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable); unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim, unsigned int pre_divider, unsigned int main_divider, diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos_mipi_dsi_lowlevel.c index b47eee45de..fcfdc8d120 100644 --- a/drivers/video/exynos_mipi_dsi_lowlevel.c +++ b/drivers/video/exynos_mipi_dsi_lowlevel.c @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -600,7 +600,7 @@ unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim) } void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, - unsigned int di, unsigned int data0, unsigned int data1) + unsigned int di, const unsigned char data0, const unsigned char data1) { struct exynos_mipi_dsim *mipi_dsim = (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.h b/drivers/video/exynos_mipi_dsi_lowlevel.h index 8a45954e9e..0bede25e4d 100644 --- a/drivers/video/exynos_mipi_dsi_lowlevel.h +++ b/drivers/video/exynos_mipi_dsi_lowlevel.h @@ -4,7 +4,7 @@ * Author: InKi Dae * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _EXYNOS_MIPI_DSI_LOWLEVEL_H @@ -91,7 +91,7 @@ unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim); void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim); void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, - unsigned int di, unsigned int data0, unsigned int data1); + unsigned int di, const unsigned char data0, const unsigned char data1); void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, unsigned int tx_data); diff --git a/drivers/video/formike.c b/drivers/video/formike.c new file mode 100644 index 0000000000..138315843f --- /dev/null +++ b/drivers/video/formike.c @@ -0,0 +1,512 @@ +/* + * LCD: Formike, TFT 4.3", 480x800, RGB24, KWH043ST20-F01, DriverIC NT35510-16 + * LCD initialization via SPI + * + * SPDX-License-Identifier: GPL-2.0 + * Based on: + * + */ +#include +#include +#include + +#define TAG_READ 0x80 +#define TAG_WRITE 0x00 + +#define TAG_DATA 0x40 +#define TAG_COMMAND 0x00 + +#define TAG_ADDR_H 0x20 +#define TAG_ADDR_L 0x00 + +static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag, + unsigned char val) +{ + unsigned long flags = SPI_XFER_BEGIN; + u8 buf[2]; + int ret; + + buf[0] = tag; + ret = spi_xfer(spi, 8, buf, NULL, flags); + buf[0] = val; + flags = SPI_XFER_END; + ret = spi_xfer(spi, 8, buf, NULL, flags); + +#ifdef KWH043ST20_F01_SPI_DEBUG + printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n", + tag, val, ret); +#endif /* KWH043ST20_F01_SPI_DEBUG */ + if (ret) + debug("%s: Failed to send: %d\n", __func__, ret); + + return ret; +} + +static void spi_write_dat(struct spi_slave *spi, unsigned int val) +{ + spi_write_tag_val(spi, TAG_WRITE|TAG_DATA, val); +} + +static void spi_write_com(struct spi_slave *spi, unsigned int addr) +{ + spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_H, + (addr & 0xff00) >> 8); + spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_L, + (addr & 0x00ff) >> 0); +} + +int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + int ret; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + debug("%s: Failed to set up slave\n", __func__); + return -1; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("%s: Failed to claim SPI bus: %d\n", __func__, ret); + goto err_claim_bus; + } + + + /* LV2 Page 1 enable */ + spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); + spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); + spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); + spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x01); + + /* AVDD Set AVDD 5.2V */ + spi_write_com(spi, 0xB000); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB001); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB002); spi_write_dat(spi, 0x0D); + + /* AVDD ratio */ + spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB601); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB602); spi_write_dat(spi, 0x34); + + /* AVEE -5.2V */ + spi_write_com(spi, 0xB100); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB102); spi_write_dat(spi, 0x0D); + + /* AVEE ratio */ + spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x35); + spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x35); + spi_write_com(spi, 0xB702); spi_write_dat(spi, 0x35); + + /* VCL -2.5V */ + spi_write_com(spi, 0xB200); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xB201); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xB202); spi_write_dat(spi, 0x00); + + /* VCL ratio */ + spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x24); + + /* VGH 15V */ + spi_write_com(spi, 0xBF00); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xB300); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xB301); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xB302); spi_write_dat(spi, 0x08); + + /* VGH ratio */ + spi_write_com(spi, 0xB900); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB901); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB902); spi_write_dat(spi, 0x34); + + /* VGLX ratio */ + spi_write_com(spi, 0xBA00); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xBA01); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xBA02); spi_write_dat(spi, 0x24); + + /* VGMP/VGSP 4.7V/0V */ + spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x88); + spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); + + /* VGMN/VGSN -4.7V/0V */ + spi_write_com(spi, 0xBD00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBD01); spi_write_dat(spi, 0x88); + spi_write_com(spi, 0xBD02); spi_write_dat(spi, 0x00); + + /* VCOM 1.525V */ + spi_write_com(spi, 0xBE00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBE01); spi_write_dat(spi, 0x7A); + + /* Gamma Setting */ + spi_write_com(spi, 0xD100); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD101); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD102); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD103); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD104); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD105); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD106); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD107); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD108); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD109); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD10A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD10C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD10E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD110); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD111); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD112); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD113); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD114); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD115); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD116); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD117); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD118); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD119); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD11A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD11B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD11C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD11D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD11E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD11F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD120); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD121); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD122); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD123); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD124); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD125); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD126); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD127); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD128); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD129); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD12A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD12C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD12E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD130); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD131); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD132); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD133); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD200); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD201); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD202); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD203); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD204); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD205); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD206); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD207); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD208); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD209); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD20A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD20C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD20E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD210); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD211); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD212); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD213); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD214); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD215); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD216); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD217); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD218); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD219); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD21A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD21B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD21C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD21D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD21E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD21F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD220); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD221); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD222); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD223); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD224); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD225); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD226); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD227); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD228); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD229); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD22A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD22C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD22E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD230); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD231); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD232); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD233); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD300); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD301); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD302); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD303); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD304); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD305); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD306); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD307); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD308); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD309); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD30A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD30C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD30E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD310); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD311); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD312); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD313); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD314); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD315); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD316); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD317); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD318); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD319); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD31A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD31B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD31C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD31D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD31E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD31F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD320); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD321); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD322); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD323); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD324); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD325); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD326); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD327); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD328); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD329); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD32A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD32C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD32E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD330); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD331); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD332); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD333); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD400); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD401); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD402); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD403); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD404); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD405); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD406); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD407); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD408); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD409); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD40A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD40C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD40E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD410); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD411); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD412); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD413); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD414); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD415); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD416); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD417); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD418); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD419); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD41A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD41B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD41C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD41D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD41E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD41F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD420); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD421); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD422); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD423); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD424); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD425); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD426); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD427); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD428); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD429); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD42A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD42C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD42E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD430); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD431); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD432); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD433); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD500); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD501); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD502); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD503); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD504); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD505); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD506); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD507); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD508); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD509); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD50A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD50C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD50E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD510); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD511); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD512); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD513); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD514); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD515); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD516); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD517); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD518); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD519); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD51A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD51B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD51C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD51D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD51E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD51F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD520); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD521); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD522); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD523); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD524); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD525); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD526); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD527); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD528); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD529); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD52A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD52C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD52E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD530); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD531); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD532); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD533); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD600); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD601); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD602); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD603); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD604); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD605); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD606); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD607); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD608); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD609); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD60A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD60C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD60E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD610); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD611); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD612); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD613); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD614); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD615); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD616); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD617); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD618); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD619); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD61A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD61B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD61C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD61D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD61E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD61F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD620); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD621); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD622); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD623); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD624); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD625); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD626); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD627); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD628); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD629); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD62A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD62C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD62E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD630); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD631); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD632); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD633); spi_write_dat(spi, 0xFF); + + /* LV2 Page 0 enable */ + spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); + spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); + spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); + spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x00); + + /* Display control */ + spi_write_com(spi, 0xB100); spi_write_dat(spi, 0xFC); + spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x00); + + /* Source hold time */ + spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x05); + + /* Gate EQ control */ + spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x70); + spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x70); + + /* Source EQ control (Mode 2) */ + spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xB803); spi_write_dat(spi, 0x05); + + /* Inversion mode (Column) */ + spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); + + /* Timing control 8phase dual side/4H/4delay/RST_EN */ + spi_write_com(spi, 0xC900); spi_write_dat(spi, 0xD0); + spi_write_com(spi, 0xC901); spi_write_dat(spi, 0x82); + spi_write_com(spi, 0xC902); spi_write_dat(spi, 0x50); + spi_write_com(spi, 0xC903); spi_write_dat(spi, 0x50); + spi_write_com(spi, 0xC904); spi_write_dat(spi, 0x50); + + spi_write_com(spi, 0x3A00); spi_write_dat(spi, 0x55); + mdelay(120); + spi_write_com(spi, 0x1100); + mdelay(120); + spi_write_com(spi, 0x2900); + mdelay(120); + /* spi_write_com(spi, 0x2100); spi_write_dat(spi, 0x00); */ + spi_write_com(spi, 0x2C00); + + return 0; +err_claim_bus: + spi_free_slave(spi); + return -1; +} diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c new file mode 100644 index 0000000000..d4cd382776 --- /dev/null +++ b/drivers/video/fsl_dcu_fb.c @@ -0,0 +1,365 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "videomodes.h" + +/* Convert the X,Y resolution pair into a single number */ +#define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) + +#ifdef CONFIG_SYS_FSL_DCU_LE +#define dcu_read32 in_le32 +#define dcu_write32 out_le32 +#elif defined(CONFIG_SYS_FSL_DCU_BE) +#define dcu_read32 in_be32 +#define dcu_write32 out_be32 +#endif + +#define DCU_MODE_BLEND_ITER(x) ((x) << 20) +#define DCU_MODE_RASTER_EN (1 << 14) +#define DCU_MODE_NORMAL 1 +#define DCU_MODE_COLORBAR 3 +#define DCU_BGND_R(x) ((x) << 16) +#define DCU_BGND_G(x) ((x) << 8) +#define DCU_BGND_B(x) (x) +#define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) +#define DCU_DISP_SIZE_DELTA_X(x) (x) +#define DCU_HSYN_PARA_BP(x) ((x) << 22) +#define DCU_HSYN_PARA_PW(x) ((x) << 11) +#define DCU_HSYN_PARA_FP(x) (x) +#define DCU_VSYN_PARA_BP(x) ((x) << 22) +#define DCU_VSYN_PARA_PW(x) ((x) << 11) +#define DCU_VSYN_PARA_FP(x) (x) +#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) +#define DCU_SYN_POL_NEG_REMAIN (0 << 5) +#define DCU_SYN_POL_INV_VS_LOW (1 << 1) +#define DCU_SYN_POL_INV_HS_LOW (1) +#define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) +#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) +#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) +#define DCU_UPDATE_MODE_MODE (1 << 31) +#define DCU_UPDATE_MODE_READREG (1 << 30) + +#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16) +#define DCU_CTRLDESCLN_1_WIDTH(x) (x) +#define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16) +#define DCU_CTRLDESCLN_2_POSX(x) (x) +#define DCU_CTRLDESCLN_4_EN (1 << 31) +#define DCU_CTRLDESCLN_4_TILE_EN (1 << 30) +#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29) +#define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28) +#define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20) +#define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16) +#define DCU_CTRLDESCLN_4_RLE_EN (1 << 15) +#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4) +#define DCU_CTRLDESCLN_4_BB_ON (1 << 2) +#define DCU_CTRLDESCLN_4_AB(x) (x) +#define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16) +#define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8) +#define DCU_CTRLDESCLN_5_CKMAX_B(x) (x) +#define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16) +#define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8) +#define DCU_CTRLDESCLN_6_CKMIN_B(x) (x) +#define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16) +#define DCU_CTRLDESCLN_7_TILE_HOR(x) (x) +#define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x) +#define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x) + +#define BPP_16_RGB565 4 +#define BPP_24_RGB888 5 +#define BPP_32_ARGB8888 6 + +/* + * This setting is used for the TWR_LCD_RGB card + */ +static struct fb_videomode fsl_dcu_mode_480_272 = { + .name = "480x272-60", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = 91996, + .left_margin = 2, + .right_margin = 2, + .upper_margin = 1, + .lower_margin = 1, + .hsync_len = 41, + .vsync_len = 2, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +/* + * This setting is used for Siliconimage SiI9022A HDMI + */ +static struct fb_videomode fsl_dcu_mode_640_480 = { + .name = "640x480-60", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39722, + .left_margin = 48, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, +}; + +/* + * DCU register map + */ +struct dcu_reg { + u32 desc_cursor[4]; + u32 mode; + u32 bgnd; + u32 disp_size; + u32 hsyn_para; + u32 vsyn_para; + u32 synpol; + u32 threshold; + u32 int_status; + u32 int_mask; + u32 colbar[8]; + u32 div_ratio; + u32 sign_calc[2]; + u32 crc_val; + u8 res_064[0x6c-0x64]; + u32 parr_err_status1; + u8 res_070[0x7c-0x70]; + u32 parr_err_status3; + u32 mparr_err_status1; + u8 res_084[0x90-0x84]; + u32 mparr_err_status3; + u32 threshold_inp_buf[2]; + u8 res_09c[0xa0-0x9c]; + u32 luma_comp; + u32 chroma_red; + u32 chroma_green; + u32 chroma_blue; + u32 crc_pos; + u32 lyr_intpol_en; + u32 lyr_luma_comp; + u32 lyr_chrm_red; + u32 lyr_chrm_grn; + u32 lyr_chrm_blue; + u8 res_0c4[0xcc-0xc8]; + u32 update_mode; + u32 underrun; + u8 res_0d4[0x100-0xd4]; + u32 gpr; + u32 slr_l[2]; + u32 slr_disp_size; + u32 slr_hvsync_para; + u32 slr_pol; + u32 slr_l_transp[2]; + u8 res_120[0x200-0x120]; + u32 ctrldescl[DCU_LAYER_MAX_NUM][16]; +}; + +static struct fb_info info; + +static void reset_total_layers(void) +{ + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + int i; + + for (i = 0; i < DCU_LAYER_MAX_NUM; i++) { + dcu_write32(®s->ctrldescl[i][0], 0); + dcu_write32(®s->ctrldescl[i][1], 0); + dcu_write32(®s->ctrldescl[i][2], 0); + dcu_write32(®s->ctrldescl[i][3], 0); + dcu_write32(®s->ctrldescl[i][4], 0); + dcu_write32(®s->ctrldescl[i][5], 0); + dcu_write32(®s->ctrldescl[i][6], 0); + dcu_write32(®s->ctrldescl[i][7], 0); + dcu_write32(®s->ctrldescl[i][8], 0); + dcu_write32(®s->ctrldescl[i][9], 0); + dcu_write32(®s->ctrldescl[i][10], 0); + } + + dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); +} + +static int layer_ctrldesc_init(int index, u32 pixel_format) +{ + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + unsigned int bpp = BPP_24_RGB888; + + dcu_write32(®s->ctrldescl[index][0], + DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) | + DCU_CTRLDESCLN_1_WIDTH(info.var.xres)); + + dcu_write32(®s->ctrldescl[index][1], + DCU_CTRLDESCLN_2_POSY(0) | + DCU_CTRLDESCLN_2_POSX(0)); + + dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base); + + switch (pixel_format) { + case 16: + bpp = BPP_16_RGB565; + break; + case 24: + bpp = BPP_24_RGB888; + break; + case 32: + bpp = BPP_32_ARGB8888; + break; + default: + printf("unsupported color depth: %u\n", pixel_format); + } + + dcu_write32(®s->ctrldescl[index][3], + DCU_CTRLDESCLN_4_EN | + DCU_CTRLDESCLN_4_TRANS(0xff) | + DCU_CTRLDESCLN_4_BPP(bpp) | + DCU_CTRLDESCLN_4_AB(0)); + + dcu_write32(®s->ctrldescl[index][4], + DCU_CTRLDESCLN_5_CKMAX_R(0xff) | + DCU_CTRLDESCLN_5_CKMAX_G(0xff) | + DCU_CTRLDESCLN_5_CKMAX_B(0xff)); + dcu_write32(®s->ctrldescl[index][5], + DCU_CTRLDESCLN_6_CKMIN_R(0) | + DCU_CTRLDESCLN_6_CKMIN_G(0) | + DCU_CTRLDESCLN_6_CKMIN_B(0)); + + dcu_write32(®s->ctrldescl[index][6], + DCU_CTRLDESCLN_7_TILE_VER(0) | + DCU_CTRLDESCLN_7_TILE_HOR(0)); + + dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); + dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); + + dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); + + return 0; +} + +int fsl_dcu_init(unsigned int xres, unsigned int yres, + unsigned int pixel_format) +{ + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + unsigned int div, mode; + + /* Memory allocation for framebuffer */ + info.screen_size = + info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); + info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN, + roundup(info.screen_size, ARCH_DMA_MINALIGN)); + memset(info.screen_base, 0, info.screen_size); + + reset_total_layers(); + div = dcu_set_pixel_clock(info.var.pixclock); + dcu_write32(®s->div_ratio, (div - 1)); + + dcu_write32(®s->disp_size, + DCU_DISP_SIZE_DELTA_Y(info.var.yres) | + DCU_DISP_SIZE_DELTA_X(info.var.xres / 16)); + + dcu_write32(®s->hsyn_para, + DCU_HSYN_PARA_BP(info.var.left_margin) | + DCU_HSYN_PARA_PW(info.var.hsync_len) | + DCU_HSYN_PARA_FP(info.var.right_margin)); + + dcu_write32(®s->vsyn_para, + DCU_VSYN_PARA_BP(info.var.upper_margin) | + DCU_VSYN_PARA_PW(info.var.vsync_len) | + DCU_VSYN_PARA_FP(info.var.lower_margin)); + + dcu_write32(®s->synpol, + DCU_SYN_POL_INV_PXCK_FALL | + DCU_SYN_POL_NEG_REMAIN | + DCU_SYN_POL_INV_VS_LOW | + DCU_SYN_POL_INV_HS_LOW); + + dcu_write32(®s->bgnd, + DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); + + dcu_write32(®s->mode, + DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) | + DCU_MODE_RASTER_EN); + + dcu_write32(®s->threshold, + DCU_THRESHOLD_LS_BF_VS(0x3) | + DCU_THRESHOLD_OUT_BUF_HIGH(0x78) | + DCU_THRESHOLD_OUT_BUF_LOW(0)); + + mode = dcu_read32(®s->mode); + dcu_write32(®s->mode, mode | DCU_MODE_NORMAL); + + layer_ctrldesc_init(0, pixel_format); + + return 0; +} + +void *video_hw_init(void) +{ + static GraphicDevice ctfb; + const char *options; + unsigned int depth = 0, freq = 0; + struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272; + + if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, + &options)) + return NULL; + + /* Find the monitor port, which is a required option */ + if (!options) + return NULL; + if (strncmp(options, "monitor=", 8) != 0) + return NULL; + + switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) { + case RESOLUTION(480, 272): + fsl_dcu_mode_db = &fsl_dcu_mode_480_272; + break; + case RESOLUTION(640, 480): + fsl_dcu_mode_db = &fsl_dcu_mode_640_480; + break; + default: + printf("unsupported resolution %ux%u\n", + ctfb.winSizeX, ctfb.winSizeY); + } + + info.var.xres = fsl_dcu_mode_db->xres; + info.var.yres = fsl_dcu_mode_db->yres; + info.var.bits_per_pixel = 32; + info.var.pixclock = fsl_dcu_mode_db->pixclock; + info.var.left_margin = fsl_dcu_mode_db->left_margin; + info.var.right_margin = fsl_dcu_mode_db->right_margin; + info.var.upper_margin = fsl_dcu_mode_db->upper_margin; + info.var.lower_margin = fsl_dcu_mode_db->lower_margin; + info.var.hsync_len = fsl_dcu_mode_db->hsync_len; + info.var.vsync_len = fsl_dcu_mode_db->vsync_len; + info.var.sync = fsl_dcu_mode_db->sync; + info.var.vmode = fsl_dcu_mode_db->vmode; + info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; + + if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY, + options + 8, fsl_dcu_mode_db) < 0) + return NULL; + + ctfb.frameAdrs = (unsigned int)info.screen_base; + ctfb.plnSizeX = ctfb.winSizeX; + ctfb.plnSizeY = ctfb.winSizeY; + + ctfb.gdfBytesPP = 4; + ctfb.gdfIndex = GDF_32BIT_X888RGB; + + ctfb.memSize = info.screen_size; + + return &ctfb; +} diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c new file mode 100644 index 0000000000..1ce4a8c93e --- /dev/null +++ b/drivers/video/hitachi_tx18d42vm_lcd.c @@ -0,0 +1,81 @@ +/* + * Hitachi tx18d42vm LVDS LCD panel driver + * + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include + +/* + * Very simple write only SPI support, this does not use the generic SPI infra + * because that assumes R/W SPI, requiring a MISO pin. Also the necessary glue + * code alone would be larger then this minimal version. + */ +static void lcd_panel_spi_write(int cs, int clk, int mosi, + unsigned int data, int bits) +{ + int i, offset; + + gpio_direction_output(cs, 0); + for (i = 0; i < bits; i++) { + gpio_direction_output(clk, 0); + offset = (bits - 1) - i; + gpio_direction_output(mosi, (data >> offset) & 1); + udelay(2); + gpio_direction_output(clk, 1); + udelay(2); + } + gpio_direction_output(cs, 1); + udelay(2); +} + +int hitachi_tx18d42vm_init(void) +{ + const u16 init_data[] = { + 0x0029, /* reset */ + 0x0025, /* standby */ + 0x0840, /* enable normally black */ + 0x0430, /* enable FRC/dither */ + 0x385f, /* enter test mode(1) */ + 0x3ca4, /* enter test mode(2) */ + 0x3409, /* enable SDRRS, enlarge OE width */ + 0x4041, /* adopt 2 line / 1 dot */ + }; + int i, cs, clk, mosi, ret = 0; + + cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); + clk = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK); + mosi = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI); + + if (cs == -1 || clk == -1 || mosi == 1) { + printf("Error tx18d42vm spi gpio config is invalid\n"); + return -EINVAL; + } + + if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 || + gpio_request(clk, "tx18d42vm-spi-clk") != 0 || + gpio_request(mosi, "tx18d42vm-spi-mosi") != 0) { + printf("Error cannot request tx18d42vm spi gpios\n"); + ret = -EBUSY; + goto out; + } + + for (i = 0; i < ARRAY_SIZE(init_data); i++) + lcd_panel_spi_write(cs, clk, mosi, init_data[i], 16); + + mdelay(50); /* All the tx18d42vm drivers have a delay here ? */ + + lcd_panel_spi_write(cs, clk, mosi, 0x00ad, 16); /* display on */ + +out: + gpio_free(mosi); + gpio_free(clk); + gpio_free(cs); + + return ret; +} diff --git a/drivers/video/hitachi_tx18d42vm_lcd.h b/drivers/video/hitachi_tx18d42vm_lcd.h new file mode 100644 index 0000000000..1b728005f6 --- /dev/null +++ b/drivers/video/hitachi_tx18d42vm_lcd.h @@ -0,0 +1,9 @@ +/* + * Hitachi tx18d42vm LVDS LCD panel driver + * + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void hitachi_tx18d42vm_init(void); diff --git a/drivers/video/imx25lcdc.c b/drivers/video/imx25lcdc.c new file mode 100644 index 0000000000..ef5767baed --- /dev/null +++ b/drivers/video/imx25lcdc.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser + * + * SPDX-License-Identifier: GPL-2.0+ + * + * imx25lcdc.c - Graphic interface for i.MX25 lcd controller + */ + +#include + +#include +#include +#include +#include +#include "videomodes.h" + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ + +/* + * Graphic Device + */ +static GraphicDevice imx25fb; + +void *video_hw_init(void) +{ + struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE; + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + GraphicDevice *pGD = &imx25fb; + char *s; + u32 *videomem; + + memset(pGD, 0, sizeof(GraphicDevice)); + + pGD->gdfIndex = GDF_16BIT_565RGB; + pGD->gdfBytesPP = 2; + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + + videomem = (u32 *)pGD->frameAdrs; + + s = getenv("videomode"); + if (s != NULL) { + struct ctfb_res_modes var_mode; + u32 lsr, lpcr, lhcr, lvcr; + unsigned long div; + int bpp; + + /* Disable all clocks of the LCDC */ + writel(readl(&ccm->cgr0) & ~((1<<7) | (1<<24)), &ccm->cgr0); + writel(readl(&ccm->cgr1) & ~(1<<29), &ccm->cgr1); + + bpp = video_get_params(&var_mode, s); + + if (bpp == 0) { + var_mode.xres = 320; + var_mode.yres = 240; + var_mode.pixclock = 154000; + var_mode.left_margin = 68; + var_mode.right_margin = 20; + var_mode.upper_margin = 4; + var_mode.lower_margin = 18; + var_mode.hsync_len = 40; + var_mode.vsync_len = 6; + var_mode.sync = 0; + var_mode.vmode = 0; + } + + /* Fill memory with white */ + memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); + + imx25fb.winSizeX = var_mode.xres; + imx25fb.winSizeY = var_mode.yres; + + /* LCD base clock is 66.6MHZ. We do calculations in kHz */ + div = 66000 / (1000000000L / var_mode.pixclock); + if (div > 63) + div = 63; + if (0 == div) + div = 1; + + lsr = ((var_mode.xres / 16) << 20) | + var_mode.yres; + lpcr = (1 << 31) | + (1 << 30) | + (5 << 25) | + (1 << 23) | + (1 << 22) | + (1 << 19) | + (1 << 7) | + div; + lhcr = (var_mode.right_margin << 0) | + (var_mode.left_margin << 8) | + (var_mode.hsync_len << 26); + + lvcr = (var_mode.lower_margin << 0) | + (var_mode.upper_margin << 8) | + (var_mode.vsync_len << 26); + + writel((uint32_t)videomem, &lcdc->lssar); + writel(lsr, &lcdc->lsr); + writel(var_mode.xres * 2 / 4, &lcdc->lvpwr); + writel(lpcr, &lcdc->lpcr); + writel(lhcr, &lcdc->lhcr); + writel(lvcr, &lcdc->lvcr); + writel(0x00040060, &lcdc->ldcr); + + writel(0xA90300, &lcdc->lpccr); + + /* Ensable all clocks of the LCDC */ + writel(readl(&ccm->cgr0) | ((1<<7) | (1<<24)), &ccm->cgr0); + writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1); + } + + return pGD; +} diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index cf935f577e..ee9c2110ed 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -332,7 +332,7 @@ static struct clk di_clk[] = { /* * This function resets IPU */ -void ipu_reset(void) +static void ipu_reset(void) { u32 *reg; u32 value; @@ -366,7 +366,7 @@ int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val) int ret; void *ipu_base; unsigned long start; -#if defined CONFIG_MX51 +#if defined CONFIG_SOC_MX51 u32 temp; u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800); diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index ff1e34b0ac..b5490b7980 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -33,7 +33,7 @@ enum csc_type_t { struct dp_csc_param_t { int mode; - void *coeff; + const int (*coeff)[5][3]; }; #define SYNC_WAVE 0 @@ -369,7 +369,7 @@ static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = { static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE; static int color_key_4rgb = 1; -void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param, +static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param, unsigned char srm_mode_update) { u32 reg; @@ -597,17 +597,6 @@ void ipu_dc_uninit(int dc_chan) } } -int ipu_chan_is_interlaced(ipu_channel_t channel) -{ - if (channel == MEM_DC_SYNC) - return !!(__raw_readl(DC_WR_CH_CONF_1) & - DC_WR_CH_CONF_FIELD_MODE); - else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC)) - return !!(__raw_readl(DC_WR_CH_CONF_5) & - DC_WR_CH_CONF_FIELD_MODE); - return 0; -} - void ipu_dp_dc_enable(ipu_channel_t channel) { int di; @@ -658,13 +647,16 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) uint32_t csc; uint32_t dc_chan = 0; int timeout = 50; + int irq = 0; dc_swap = swap; if (channel == MEM_DC_SYNC) { dc_chan = 1; + irq = IPU_IRQ_DC_FC_1; } else if (channel == MEM_BG_SYNC) { dc_chan = 5; + irq = IPU_IRQ_DP_SF_END; } else if (channel == MEM_FG_SYNC) { /* Disable FG channel */ dc_chan = 5; @@ -715,25 +707,11 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) reg ^= DC_WR_CH_CONF_PROG_DI_ID; __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); } else { - timeout = 50; - - /* Wait for DC triple buffer to empty */ - if (g_dc_di_assignment[dc_chan] == 0) - while ((__raw_readl(DC_STAT) & 0x00000002) - != 0x00000002) { - udelay(2000); - timeout -= 2; - if (timeout <= 0) - break; - } - else if (g_dc_di_assignment[dc_chan] == 1) - while ((__raw_readl(DC_STAT) & 0x00000020) - != 0x00000020) { - udelay(2000); - timeout -= 2; - if (timeout <= 0) - break; - } + /* Make sure that we leave at the irq starting edge */ + __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); + do { + reg = __raw_readl(IPUIRQ_2_STATREG(irq)); + } while (!(reg & IPUIRQ_2_MASK(irq))); reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; @@ -785,7 +763,7 @@ void ipu_init_dc_mappings(void) ipu_dc_map_config(4, 2, 17, 0xFC); } -int ipu_pixfmt_to_map(uint32_t fmt) +static int ipu_pixfmt_to_map(uint32_t fmt) { switch (fmt) { case IPU_PIX_FMT_GENERIC: @@ -805,28 +783,6 @@ int ipu_pixfmt_to_map(uint32_t fmt) return -EINVAL; } -/* - * This function is called to adapt synchronous LCD panel to IPU restriction. - */ -void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk, - uint16_t width, uint16_t height, - uint16_t h_start_width, - uint16_t h_end_width, - uint16_t v_start_width, - uint16_t *v_end_width) -{ - if (*v_end_width < 2) { - uint16_t total_width = width + h_start_width + h_end_width; - uint16_t total_height_old = height + v_start_width + - (*v_end_width); - uint16_t total_height_new = height + v_start_width + 2; - *v_end_width = 2; - *pixel_clk = (*pixel_clk) * total_width * total_height_new / - (total_width * total_height_old); - printf("WARNING: adapt panel end blank lines\n"); - } -} - /* * This function is called to initialize a synchronous LCD panel. * @@ -884,14 +840,17 @@ int ipu_init_sync_panel(int disp, uint32_t pixel_clk, if ((v_sync_width == 0) || (h_sync_width == 0)) return -EINVAL; - adapt_panel_to_ipu_restricitions(&pixel_clk, width, height, - h_start_width, h_end_width, - v_start_width, &v_end_width); + /* adapt panel to ipu restricitions */ + if (v_end_width < 2) { + v_end_width = 2; + puts("WARNING: v_end_width (lower_margin) must be >= 2, adjusted\n"); + } + h_total = width + h_sync_width + h_start_width + h_end_width; v_total = height + v_sync_width + v_start_width + v_end_width; /* Init clocking */ - debug("pixel clk = %d\n", pixel_clk); + debug("pixel clk = %dHz\n", pixel_clk); if (sig.ext_clk) { if (!(g_di1_tvout && (disp == 1))) { /* don't round div for tvout */ @@ -1198,7 +1157,7 @@ int ipu_init_sync_panel(int disp, uint32_t pixel_clk, if (sig.Vsync_pol) di_gen |= DI_GEN_POLARITY_3; - if (sig.clk_pol) + if (!sig.clk_pol) di_gen |= DI_GEN_POL_CLK; /* Set the clock to stop at counter 6. */ diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 07626941df..ea0cf4141b 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -192,7 +192,7 @@ struct ipu_cm { u32 gpr; u32 reserved0[26]; u32 ch_db_mode_sel[2]; - u32 reserved1[16]; + u32 reserved1[4]; u32 alt_ch_db_mode_sel[2]; u32 reserved2[2]; u32 ch_trb_mode_sel[2]; @@ -209,7 +209,7 @@ struct ipu_idmac { u32 sub_addr[5]; u32 bndm_en[2]; u32 sc_cord[2]; - u32 reserved[45]; + u32 reserved[44]; u32 ch_busy[2]; }; @@ -335,9 +335,12 @@ struct ipu_dmfc { #define IPU_STAT ((struct ipu_stat *)(IPU_DISP_REG_BASE_ADDR + \ IPU_STAT_REG_BASE)) +#define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1]) #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[(ch) / 32]) #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[(ch) / 32]) #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[(ch) / 32]) +#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32)) +#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F)) #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) diff --git a/drivers/video/l5f31188.c b/drivers/video/l5f31188.c new file mode 100644 index 0000000000..3312dcfb31 --- /dev/null +++ b/drivers/video/l5f31188.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved. + * Hyungwon Hwang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define SCAN_FROM_LEFT_TO_RIGHT 0 +#define SCAN_FROM_RIGHT_TO_LEFT 1 +#define SCAN_FROM_TOP_TO_BOTTOM 0 +#define SCAN_FROM_BOTTOM_TO_TOP 1 + +static void l5f31188_sleep_in(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x10, 0x00); +} + +static void l5f31188_sleep_out(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00); +} + +static void l5f31188_set_gamma(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x26, 0x00); +} + +static void l5f31188_display_off(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x28, 0x00); +} + +static void l5f31188_display_on(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00); +} + +static void l5f31188_ctl_memory_access(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, + int h_direction, int v_direction) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x36, + (((h_direction & 0x1) << 1) | (v_direction & 0x1))); +} + +static void l5f31188_set_pixel_format(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x3A, 0x70); +} + +static void l5f31188_write_disbv(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, unsigned int brightness) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x51, brightness); +} + +static void l5f31188_write_ctrld(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x53, 0x2C); +} + +static void l5f31188_write_cabc(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, + unsigned int wm_mode) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x55, wm_mode); +} + +static void l5f31188_write_cabcmb(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, unsigned int min_brightness) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x5E, + min_brightness); +} + +static void l5f31188_set_extension(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xB9, 0xFF, 0x83, 0x94 + }; + + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_dgc_lut(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xC1, 0x01, 0x00, 0x04, 0x0E, 0x18, 0x1E, 0x26, + 0x2F, 0x36, 0x3E, 0x47, 0x4E, 0x56, 0x5D, 0x65, + 0x6D, 0x75, 0x7D, 0x84, 0x8C, 0x94, 0x9C, 0xA4, + 0xAD, 0xB5, 0xBD, 0xC5, 0xCC, 0xD4, 0xDE, 0xE5, + 0xEE, 0xF7, 0xFF, 0x3F, 0x9A, 0xCE, 0xD4, 0x21, + 0xA1, 0x26, 0x54, 0x00, 0x00, 0x04, 0x0E, 0x19, + 0x1F, 0x27, 0x30, 0x37, 0x40, 0x48, 0x50, 0x58, + 0x60, 0x67, 0x6F, 0x77, 0x7F, 0x87, 0x8F, 0x97, + 0x9F, 0xA7, 0xB0, 0xB8, 0xC0, 0xC8, 0xCE, 0xD8, + 0xE0, 0xE7, 0xF0, 0xF7, 0xFF, 0x3C, 0xEB, 0xFD, + 0x2F, 0x66, 0xA8, 0x2C, 0x46, 0x00, 0x00, 0x04, + 0x0E, 0x18, 0x1E, 0x26, 0x30, 0x38, 0x41, 0x4A, + 0x52, 0x5A, 0x62, 0x6B, 0x73, 0x7B, 0x83, 0x8C, + 0x94, 0x9C, 0xA5, 0xAD, 0xB6, 0xBD, 0xC5, 0xCC, + 0xD4, 0xDD, 0xE3, 0xEB, 0xF2, 0xF9, 0xFF, 0x3F, + 0xA4, 0x8A, 0x8F, 0xC7, 0x33, 0xF5, 0xE9, 0x00 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_tcon(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xC7, 0x00, 0x20 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_ptba(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xBF, 0x06, 0x10 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_eco(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xC6, 0x0C); +} + +static int l5f31188_panel_init(struct mipi_dsim_device *dev) +{ + struct mipi_dsim_master_ops *ops = dev->master_ops; + + l5f31188_set_extension(dev, ops); + l5f31188_set_dgc_lut(dev, ops); + + l5f31188_set_eco(dev, ops); + l5f31188_set_tcon(dev, ops); + l5f31188_set_ptba(dev, ops); + l5f31188_set_gamma(dev, ops); + l5f31188_ctl_memory_access(dev, ops, + SCAN_FROM_LEFT_TO_RIGHT, SCAN_FROM_TOP_TO_BOTTOM); + l5f31188_set_pixel_format(dev, ops); + l5f31188_write_disbv(dev, ops, 0xFF); + l5f31188_write_ctrld(dev, ops); + l5f31188_write_cabc(dev, ops, 0x0); + l5f31188_write_cabcmb(dev, ops, 0x0); + + l5f31188_sleep_out(dev, ops); + + /* 120 msec */ + udelay(120 * 1000); + + return 0; +} + +static void l5f31188_display_enable(struct mipi_dsim_device *dev) +{ + struct mipi_dsim_master_ops *ops = dev->master_ops; + l5f31188_display_on(dev, ops); +} + +static struct mipi_dsim_lcd_driver l5f31188_dsim_ddi_driver = { + .name = "l5f31188", + .id = -1, + + .mipi_panel_init = l5f31188_panel_init, + .mipi_display_on = l5f31188_display_enable, +}; + +void l5f31188_init(void) +{ + exynos_mipi_dsi_register_lcd_driver(&l5f31188_dsim_ddi_driver); +} diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c index f54b4834ff..add7215992 100644 --- a/drivers/video/mpc8xx_lcd.c +++ b/drivers/video/mpc8xx_lcd.c @@ -2,7 +2,7 @@ * (C) Copyright 2001-2002 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************/ @@ -34,11 +34,6 @@ #define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ #endif -#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10) -#undef CONFIG_LCD_LOGO -#undef CONFIG_LCD_INFO -#endif - /*----------------------------------------------------------------------*/ #ifdef CONFIG_KYOCERA_KCS057QV1AJ /* @@ -224,20 +219,6 @@ vidinfo_t panel_info = { }; #endif /* CONFIG_OPTREX_BW */ -/*-----------------------------------------------------------------*/ -#ifdef CONFIG_EDT32F10 -/* - * Emerging Display Technologies 320x240. Passive, monochrome, single scan. - */ -#define LCD_BPP LCD_MONOCHROME -#define LCD_DF 10 - -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, - LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 -}; -#endif - /************************************************************************/ /* ----------------- chipset specific functions ----------------------- */ /************************************************************************/ @@ -268,11 +249,6 @@ void lcd_ctrl_init (void *lcdbase) * the controller. */ -#ifdef CONFIG_RPXLITE - /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ - panel_info.vl_dp = CONFIG_SYS_LOW; -#endif - lccrtmp = LCDBIT (LCCR_BNUM_BIT, (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); @@ -297,9 +273,6 @@ void lcd_ctrl_init (void *lcdbase) /* Initialize LCD controller bus priorities. */ -#ifdef CONFIG_RBC823 - immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */ -#else immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ /* set SHFT/CLOCK division factor 4 @@ -313,21 +286,6 @@ void lcd_ctrl_init (void *lcdbase) immr->im_clkrst.car_sccr &= ~0x1F; immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ -#endif /* CONFIG_RBC823 */ - -#if defined(CONFIG_RBC823) - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pddat &= 0x0300; - immr->im_ioport.iop_pdpar |= 0x1CFF; - immr->im_ioport.iop_pddir |= 0x1CFF; - - /* Configure LCD_ON, VEE_ON, CCFL_ON on port B. - */ - immr->im_cpm.cp_pbdat &= ~0x00005001; - immr->im_cpm.cp_pbpar &= ~0x00005001; - immr->im_cpm.cp_pbdir |= 0x00005001; -#elif !defined(CONFIG_EDT32F10) /* Enable LCD on port D. */ immr->im_ioport.iop_pdpar |= 0x1FFF; @@ -337,14 +295,6 @@ void lcd_ctrl_init (void *lcdbase) */ immr->im_cpm.cp_pbpar |= 0x00005001; immr->im_cpm.cp_pbdir |= 0x00005001; -#else - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pdpar |= 0x1DFF; - immr->im_ioport.iop_pdpar &= ~0x0200; - immr->im_ioport.iop_pddir |= 0x1FFF; - immr->im_ioport.iop_pddat |= 0x0200; -#endif /* Load the physical address of the linear frame buffer * into the LCD controller. @@ -395,9 +345,7 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) colreg = ((red & 0x0F) << 8) | ((green & 0x0F) << 4) | (blue & 0x0F) ; -#ifdef CONFIG_SYS_INVERT_COLORS - colreg ^= 0x0FFF; -#endif + *cmap_ptr = colreg; debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", @@ -409,139 +357,15 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) /*----------------------------------------------------------------------*/ -#if LCD_BPP == LCD_MONOCHROME -static -void lcd_initcolregs (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - ushort regno; - - for (regno = 0; regno < 16; regno++) { - cp->lcd_cmap[regno * 2] = 0; - cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f; - } -} -#endif - -/*----------------------------------------------------------------------*/ - void lcd_enable (void) { volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile lcd823_t *lcdp = &immr->im_lcd; /* Enable the LCD panel */ -#ifndef CONFIG_RBC823 immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ -#endif lcdp->lcd_lccr |= LCCR_PON; - -#ifdef CONFIG_V37 - /* Turn on display backlight */ - immr->im_cpm.cp_pbpar |= 0x00008000; - immr->im_cpm.cp_pbdir |= 0x00008000; -#elif defined(CONFIG_RBC823) - /* Turn on display backlight */ - immr->im_cpm.cp_pbdat |= 0x00004000; -#endif - -#if defined(CONFIG_LWMON) - { uchar c = pic_read (0x60); -#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON) - /* Enable LCD later in sysmon test, only if temperature is OK */ -#else - c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ -#endif - pic_write (0x60, c); - } -#endif /* CONFIG_LWMON */ - -#if defined(CONFIG_R360MPI) - { - extern void r360_i2c_lcd_write (uchar data0, uchar data1); - unsigned long bgi, ctr; - char *p; - - if ((p = getenv("lcdbgi")) != NULL) { - bgi = simple_strtoul (p, 0, 10) & 0xFFF; - } else { - bgi = 0xFFF; - } - - if ((p = getenv("lcdctr")) != NULL) { - ctr = simple_strtoul (p, 0, 10) & 0xFFF; - } else { - ctr=0x7FF; - } - - r360_i2c_lcd_write(0x10, 0x01); - r360_i2c_lcd_write(0x20, 0x01); - r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF); - r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); - } -#endif /* CONFIG_R360MPI */ -#ifdef CONFIG_RBC823 - udelay(200000); /* wait 200ms */ - /* Turn VEE_ON first */ - immr->im_cpm.cp_pbdat |= 0x00000001; - udelay(200000); /* wait 200ms */ - /* Now turn on LCD_ON */ - immr->im_cpm.cp_pbdat |= 0x00001000; -#endif -#ifdef CONFIG_RRVISION - debug ("PC4->Output(1): enable LVDS\n"); - debug ("PC5->Output(0): disable PAL clock\n"); - immr->im_ioport.iop_pddir |= 0x1000; - immr->im_ioport.iop_pcpar &= ~(0x0C00); - immr->im_ioport.iop_pcdir |= 0x0C00 ; - immr->im_ioport.iop_pcdat |= 0x0800 ; - immr->im_ioport.iop_pcdat &= ~(0x0400); - debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", - immr->im_ioport.iop_pdpar, - immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); - debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", - immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, - immr->im_ioport.iop_pcdat); -#endif -} - -/*----------------------------------------------------------------------*/ - -#if defined (CONFIG_RBC823) -void lcd_disable (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - -#if defined(CONFIG_LWMON) - { uchar c = pic_read (0x60); - c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */ - pic_write (0x60, c); - } -#elif defined(CONFIG_R360MPI) - { - extern void r360_i2c_lcd_write (uchar data0, uchar data1); - - r360_i2c_lcd_write(0x10, 0x00); - r360_i2c_lcd_write(0x20, 0x00); - r360_i2c_lcd_write(0x30, 0x00); - r360_i2c_lcd_write(0x40, 0x00); - } -#endif /* CONFIG_LWMON */ - /* Disable the LCD panel */ - lcdp->lcd_lccr &= ~LCCR_PON; -#ifdef CONFIG_RBC823 - /* Turn off display backlight, VEE and LCD_ON */ - immr->im_cpm.cp_pbdat &= ~0x00005001; -#else - immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */ -#endif /* CONFIG_RBC823 */ } -#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */ - /************************************************************************/ diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c index 017f6220d1..cd95abab83 100644 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/mxc_ipuv3_fb.c @@ -14,6 +14,7 @@ /* #define DEBUG */ #include #include +#include #include #include #include @@ -410,10 +411,13 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length; } + + fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN); if (gd->fb_base) fbi->screen_base = (void *)gd->fb_base; else - fbi->screen_base = malloc(fbi->fix.smem_len); + fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN, + fbi->fix.smem_len); if (fbi->screen_base == NULL) { puts("Unable to allocate framebuffer memory\n"); fbi->fix.smem_len = 0; @@ -426,6 +430,8 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->screen_size = fbi->fix.smem_len; + gd->fb_base = fbi->fix.smem_start; + return 0; } @@ -486,7 +492,7 @@ static struct fb_info *mxcfb_init_fbinfo(void) /* * Probe routine for the framebuffer driver. It is called during the - * driver binding process. The following functions are performed in + * driver binding process. The following functions are performed in * this routine: Framebuffer initialization, Memory allocation and * mapping, Framebuffer registration, IPU initialization. * diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index f7b5827388..68293d2b75 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -16,6 +16,8 @@ #include #include +#include + #include "videomodes.h" #define PS2KHZ(ps) (1000000000UL / (ps)) @@ -23,6 +25,18 @@ DECLARE_GLOBAL_DATA_PTR; static GraphicDevice panel; +struct mxs_dma_desc desc; + +/** + * mxsfb_system_setup() - Fine-tune LCDIF configuration + * + * This function is used to adjust the LCDIF configuration. This is usually + * needed when driving the controller in System-Mode to operate an 8080 or + * 6800 connected SmartLCD. + */ +__weak void mxsfb_system_setup(void) +{ +} /* * DENX M28EVK: @@ -82,6 +96,9 @@ static void mxs_lcd_init(GraphicDevice *panel, writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET, ®s->hw_lcdif_ctrl1); + + mxsfb_system_setup(); + writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres, ®s->hw_lcdif_transfer_count); @@ -121,8 +138,10 @@ static void mxs_lcd_init(GraphicDevice *panel, /* Flush FIFO first */ writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set); +#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM /* Sync signals ON */ setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON); +#endif /* FIFO cleared */ writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr); @@ -185,5 +204,28 @@ void *video_hw_init(void) /* Start framebuffer */ mxs_lcd_init(&panel, &mode, bpp); - return &panel; +#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM + /* + * If the LCD runs in system mode, the LCD refresh has to be triggered + * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid + * having to set this bit manually after every single change in the + * framebuffer memory, we set up specially crafted circular DMA, which + * sets the RUN bit, then waits until it gets cleared and repeats this + * infinitelly. This way, we get smooth continuous updates of the LCD. + */ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + + memset(&desc, 0, sizeof(struct mxs_dma_desc)); + desc.address = (dma_addr_t)&desc; + desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | + MXS_DMA_DESC_WAIT4END | + (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); + desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN; + desc.cmd.next = (uint32_t)&desc.cmd; + + /* Execute the DMA chain. */ + mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc); +#endif + + return (void *)&panel; } diff --git a/drivers/video/parade.c b/drivers/video/parade.c new file mode 100644 index 0000000000..0f543f653c --- /dev/null +++ b/drivers/video/parade.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file is a driver for Parade dP<->LVDS bridges. The original submission + * is for the ps8625 chip. + */ +#include +#include +#include +#include + +/* + * Initialization of the chip is a process of writing certaing values into + * certain registers over i2c bus. The chip in fact responds to a range of + * addresses on the i2c bus, so for each written value three parameters are + * required: i2c address, register address and the actual value. + * + * The base address is derived from the device tree, only address offset is + * stored in the table below. + */ +/** + * struct reg_data() - data for a parade register write + * + * @addr_off offset from the i2c base address for parade + * @reg_addr register address to write + * @value value to be written + */ +struct reg_data { + uint8_t addr_off; + uint8_t reg; + uint8_t value; +} _packed; + +#define END_OF_TABLE 0xff /* Ficticious offset */ + +static const struct reg_data parade_values[] = { + {0x02, 0xa1, 0x01}, /* HPD low */ + /* + * SW setting + * [1:0] SW output 1.2V voltage is lower to 96% + */ + {0x04, 0x14, 0x01}, + /* + * RCO SS setting + * [5:4] = b01 0.5%, b10 1%, b11 1.5% + */ + {0x04, 0xe3, 0x20}, + {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */ + /* + * RPHY Setting + * [3:2] CDR tune wait cycle before + * measure for fine tune b00: 1us, + * 01: 0.5us, 10:2us, 11:4us. + */ + {0x04, 0x8a, 0x0c}, + {0x04, 0x89, 0x08}, /* [3] RFD always on */ + /* + * CTN lock in/out: + * 20000ppm/80000ppm. Lock out 2 + * times. + */ + {0x04, 0x71, 0x2d}, + /* + * 2.7G CDR settings + * NOF=40LSB for HBR CDR setting + */ + {0x04, 0x7d, 0x07}, + {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */ + {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */ + /* + * 1.62G CDR settings + * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 + */ + {0x04, 0xc0, 0x12}, + {0x04, 0xc1, 0x92}, /* Gitune=-37% */ + {0x04, 0xc2, 0x1c}, /* Fbstep=100% */ + {0x04, 0x32, 0x80}, /* [7] LOS signal disable */ + /* + * RPIO Setting + * [7:4] LVDS driver bias current : + * 75% (250mV swing) + */ + {0x04, 0x00, 0xb0}, + /* + * [7:6] Right-bar GPIO output strength is 8mA + */ + {0x04, 0x15, 0x40}, + /* EQ Training State Machine Setting */ + {0x04, 0x54, 0x10}, /* RCO calibration start */ + /* [4:0] MAX_LANE_COUNT set to one lane */ + {0x01, 0x02, 0x81}, + /* [4:0] LANE_COUNT_SET set to one lane */ + {0x01, 0x21, 0x81}, + {0x00, 0x52, 0x20}, + {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */ + {0x00, 0x62, 0x41}, + /* Counter number, add 1ms counter delay */ + {0x00, 0xf6, 0x01}, + /* + * [6]PWM function control by + * DPCD0040f[7], default is PWM + * block always works. + */ + {0x00, 0x77, 0x06}, + /* + * 04h Adjust VTotal tolerance to + * fix the 30Hz no display issue + */ + {0x00, 0x4c, 0x04}, + /* DPCD00400='h00, Parade OUI = 'h001cf8 */ + {0x01, 0xc0, 0x00}, + {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */ + {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */ + /* + * DPCD403~408 = ASCII code + * D2SLV5='h4432534c5635 + */ + {0x01, 0xc3, 0x44}, + {0x01, 0xc4, 0x32}, /* DPCD404 */ + {0x01, 0xc5, 0x53}, /* DPCD405 */ + {0x01, 0xc6, 0x4c}, /* DPCD406 */ + {0x01, 0xc7, 0x56}, /* DPCD407 */ + {0x01, 0xc8, 0x35}, /* DPCD408 */ + /* + * DPCD40A, Initial Code major revision + * '01' + */ + {0x01, 0xca, 0x01}, + /* DPCD40B, Initial Code minor revision '05' */ + {0x01, 0xcb, 0x05}, + /* DPCD720, Select internal PWM */ + {0x01, 0xa5, 0xa0}, + /* + * FFh for 100% PWM of brightness, 0h for 0% + * brightness + */ + {0x01, 0xa7, 0xff}, + /* + * Set LVDS output as 6bit-VESA mapping, + * single LVDS channel + */ + {0x01, 0xcc, 0x13}, + /* Enable SSC set by register */ + {0x02, 0xb1, 0x20}, + /* + * Set SSC enabled and +/-1% central + * spreading + */ + {0x04, 0x10, 0x16}, + /* MPU Clock source: LC => RCO */ + {0x04, 0x59, 0x60}, + {0x04, 0x54, 0x14}, /* LC -> RCO */ + {0x02, 0xa1, 0x91}, /* HPD high */ + {END_OF_TABLE} +}; + +/** + * Write values table into the Parade eDP bridge + * + * @return 0 on success, non-0 on failure + */ + +static int parade_write_regs(int base_addr, const struct reg_data *table) +{ + int ret = 0; + + while (!ret && (table->addr_off != END_OF_TABLE)) { + ret = i2c_write(base_addr + table->addr_off, + table->reg, 1, + (uint8_t *)&table->value, + sizeof(table->value)); + table++; + } + return ret; +} + +int parade_init(const void *blob) +{ + int bus, old_bus; + int parent; + int node; + int addr; + int ret; + + node = fdtdec_next_compatible(blob, 0, COMPAT_PARADE_PS8625); + if (node < 0) + return 0; + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("%s: Could not find parent i2c node\n", __func__); + return -1; + } + addr = fdtdec_get_int(blob, node, "reg", -1); + if (addr < 0) { + debug("%s: Could not find i2c address\n", __func__); + return -1; + } + + bus = i2c_get_bus_num_fdt(parent); + old_bus = i2c_get_bus_num(); + + debug("%s: Using i2c bus %d\n", __func__, bus); + + /* + * TODO(sjg@chromium.org): Hmmm we seem to need some sort of delay + * here. + */ + mdelay(40); + i2c_set_bus_num(bus); + ret = parade_write_regs(addr, parade_values); + + i2c_set_bus_num(old_bus); + + return ret; +} diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c index 8ed52c0202..f66f615df5 100644 --- a/drivers/video/pxa_lcd.c +++ b/drivers/video/pxa_lcd.c @@ -4,7 +4,7 @@ * (C) Copyright 2001-2002 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************/ @@ -378,21 +378,6 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) } #endif /* LCD_COLOR8 */ -/*----------------------------------------------------------------------*/ -#if LCD_BPP == LCD_MONOCHROME -void lcd_initcolregs (void) -{ - struct pxafb_info *fbi = &panel_info.pxa; - cmap = (ushort *)fbi->palette; - ushort regno; - - for (regno = 0; regno < 16; regno++) { - cmap[regno * 2] = 0; - cmap[(regno * 2) + 1] = regno & 0x0f; - } -} -#endif /* LCD_MONOCHROME */ - /*----------------------------------------------------------------------*/ __weak void lcd_enable(void) { diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c index fc092522b2..84948177e2 100644 --- a/drivers/video/s6e8ax0.c +++ b/drivers/video/s6e8ax0.c @@ -3,7 +3,7 @@ * * Author: Donghwa Lee * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -34,11 +34,11 @@ static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev) if (reverse) { ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send_reverse, + data_to_send_reverse, ARRAY_SIZE(data_to_send_reverse)); } else { ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } } @@ -50,8 +50,7 @@ static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) @@ -65,15 +64,18 @@ static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev) { struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xf7, 0x03 + }; - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xf7, 0x3); + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, + ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) @@ -84,8 +86,7 @@ static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) @@ -97,8 +98,7 @@ static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) @@ -109,8 +109,7 @@ static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) @@ -121,8 +120,7 @@ static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) @@ -133,14 +131,18 @@ static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev) { struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xe3, 0x40 + }; - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xe3, 0x40); + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, + ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) @@ -151,7 +153,7 @@ static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) @@ -162,24 +164,29 @@ static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev) { struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0x29, 0x00 + }; - ops->cmd_write(dsim_dev, - MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00); + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, + ARRAY_SIZE(data_to_send)); } static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev) { struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0x11, 0x00 + }; - ops->cmd_write(dsim_dev, - MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00); + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, + ARRAY_SIZE(data_to_send)); } static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) @@ -190,7 +197,7 @@ static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) @@ -201,7 +208,7 @@ static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev) diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c new file mode 100644 index 0000000000..ba4578e9d1 --- /dev/null +++ b/drivers/video/sandbox_sdl.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + /* Maximum LCD size we support */ + LCD_MAX_WIDTH = 1366, + LCD_MAX_HEIGHT = 768, + LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ +}; + +vidinfo_t panel_info; + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_ctrl_init(void *lcdbase) +{ + /* + * Allocate memory to keep BMP color conversion map. This is required + * for 8 bit BMPs only (hence 256 colors). If malloc fails - keep + * going, it is not even clear if displyaing the bitmap will be + * required on the way up. + */ + panel_info.cmap = malloc(256 * NBITS(panel_info.vl_bpix) / 8); +} + +void lcd_enable(void) +{ + if (sandbox_sdl_init_display(panel_info.vl_col, panel_info.vl_row, + panel_info.vl_bpix)) + puts("LCD init failed\n"); +} + +int sandbox_lcd_sdl_early_init(void) +{ + const void *blob = gd->fdt_blob; + int xres = LCD_MAX_WIDTH, yres = LCD_MAX_HEIGHT; + int node; + int ret = 0; + + /* + * The code in common/lcd.c does not cope with not being able to + * set up a frame buffer. It will just happily keep writing to + * invalid memory. So here we make sure that at least some buffer + * is available even if it actually won't be displayed. + */ + node = fdtdec_next_compatible(blob, 0, COMPAT_SANDBOX_LCD_SDL); + if (node >= 0) { + xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH); + yres = fdtdec_get_int(blob, node, "yres", LCD_MAX_HEIGHT); + if (xres < 0 || xres > LCD_MAX_WIDTH) { + xres = LCD_MAX_WIDTH; + ret = -EINVAL; + } + if (yres < 0 || yres > LCD_MAX_HEIGHT) { + yres = LCD_MAX_HEIGHT; + ret = -EINVAL; + } + } + + panel_info.vl_col = xres; + panel_info.vl_row = yres; + panel_info.vl_bpix = LCD_COLOR16; + + return ret; +} diff --git a/drivers/video/scf0403_lcd.c b/drivers/video/scf0403_lcd.c new file mode 100644 index 0000000000..2bc8bcae8a --- /dev/null +++ b/drivers/video/scf0403_lcd.c @@ -0,0 +1,296 @@ +/* + * scf0403.c -- support for DataImage SCF0403 LCD + * + * Copyright (c) 2013 Adapted from Linux driver: + * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved. + * Copyright (c) 2012 CompuLab, Ltd + * Dmitry Lifshitz + * Ilya Ledvich + * Inspired by Alberto Panizzo & + * Marek Vasut work in l4f00242t03.c + * + * U-Boot port: Nikita Kiryanov + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct scf0403_cmd { + u16 cmd; + u16 *params; + int count; +}; + +struct scf0403_initseq_entry { + struct scf0403_cmd cmd; + int delay_ms; +}; + +struct scf0403_priv { + struct spi_slave *spi; + unsigned int reset_gpio; + u32 rddid; + struct scf0403_initseq_entry *init_seq; + int seq_size; +}; + +struct scf0403_priv priv; + +#define SCF0403852GGU04_ID 0x000080 + +/* SCF0403526GGU20 model commands parameters */ +static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06}; +static u16 spiinttype_params_sn20[] = {0x60}; +static u16 bc_params_sn20[] = { + 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B, + 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01, + 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40, +}; +static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67}; +static u16 be_params_sn20[] = { + 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22, +}; +static u16 vcom_params_sn20[] = {0x74}; +static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00}; +static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00}; +static u16 lvglvolt_params_sn20[] = {0x08}; +static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20}; +static u16 dispfunc_params_sn20[] = {0xa0}; +static u16 dvddvolt_params_sn20[] = {0x74}; +static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00}; +static u16 panelres_params_sn20[] = {0x82}; +static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13}; +static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28}; +static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20}; +static u16 memaccess_params_sn20[] = {0x00}; +static u16 pixfmt_params_sn20[] = {0x66}; +static u16 pgamma_params_sn20[] = { + 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04, + 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10, +}; +static u16 ngamma_params_sn20[] = { + 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03, + 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00, +}; +static u16 tearing_params_sn20[] = {0x00}; + +/* SCF0403852GGU04 model commands parameters */ +static u16 memaccess_params_sn04[] = {0x08}; +static u16 pixfmt_params_sn04[] = {0x66}; +static u16 modectl_params_sn04[] = {0x01}; +static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04}; +static u16 vcom_params_sn04[] = {0x00, 0x6A}; +static u16 pgamma_params_sn04[] = { + 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c, + 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f, +}; +static u16 ngamma_params_sn04[] = { + 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05, + 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00, +}; +static u16 dispinv_params_sn04[] = {0x02}; + +/* Common commands */ +static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0}; +static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0}; + +/* SCF0403852GGU04 init sequence */ +static struct scf0403_initseq_entry scf0403_initseq_sn04[] = { + {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0}, + {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0}, + {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0}, + {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0}, + {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0}, + {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20}, + {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0}, + {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100}, +}; + +/* SCF0403526GGU20 init sequence */ +static struct scf0403_initseq_entry scf0403_initseq_sn20[] = { + {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0}, + {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0}, + {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0}, + {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0}, + {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0}, + {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0}, + {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0}, + {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0}, + {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0}, + {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0}, + {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0}, + {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0}, + {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0}, + {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0}, + {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0}, + {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0}, + {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0}, + {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0}, + {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0}, + {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0}, + {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0}, + {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0}, +}; + +static void scf0403_gpio_reset(unsigned int gpio) +{ + if (!gpio_is_valid(gpio)) + return; + + gpio_set_value(gpio, 1); + mdelay(100); + gpio_set_value(gpio, 0); + mdelay(40); + gpio_set_value(gpio, 1); + mdelay(100); +} + +static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid) +{ + int error = 0; + u8 ids_buf = 0x00; + u16 dummy_buf = 0x00; + u16 cmd = 0x04; + + error = spi_set_wordlen(spi, 9); + if (error) + return error; + + /* Here 9 bits required to transmit a command */ + error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE); + if (error) + return error; + + /* + * Here 8 + 1 bits required to arrange extra clock cycle + * before the first data bit. + * According to the datasheet - first parameter is the dummy data. + */ + error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE); + if (error) + return error; + + error = spi_set_wordlen(spi, 8); + if (error) + return error; + + /* Read rest of the data */ + error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE); + if (error) + return error; + + *rddid = ids_buf; + + return 0; +} + +static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd) +{ + int i, error; + u32 command = cmd->cmd; + u32 msg; + + error = spi_set_wordlen(spi, 9); + if (error) + return error; + + error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE); + if (error) + return error; + + for (i = 0; i < cmd->count; i++) { + msg = (cmd->params[i] | 0x100); + error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE); + if (error) + return error; + } + + return 0; +} + +static void scf0403_lcd_init(struct scf0403_priv *priv) +{ + int i; + + /* reset LCD */ + scf0403_gpio_reset(priv->reset_gpio); + + for (i = 0; i < priv->seq_size; i++) { + if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0) + puts("SPI transfer failed\n"); + + mdelay(priv->init_seq[i].delay_ms); + } +} + +static int scf0403_request_reset_gpio(unsigned gpio) +{ + int err = gpio_request(gpio, "lcd reset"); + + if (err) + return err; + + err = gpio_direction_output(gpio, 0); + if (err) + gpio_free(gpio); + + return err; +} + +int scf0403_init(int reset_gpio) +{ + int error; + + if (gpio_is_valid(reset_gpio)) { + error = scf0403_request_reset_gpio(reset_gpio); + if (error) { + printf("Failed requesting reset GPIO%d: %d\n", + reset_gpio, error); + return error; + } + } + + priv.reset_gpio = reset_gpio; + priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0); + error = spi_claim_bus(priv.spi); + if (error) + goto bus_claim_fail; + + /* reset LCD */ + scf0403_gpio_reset(reset_gpio); + + error = scf0403_spi_read_rddid(priv.spi, &priv.rddid); + if (error) { + puts("IDs read failed\n"); + goto readid_fail; + } + + if (priv.rddid == SCF0403852GGU04_ID) { + priv.init_seq = scf0403_initseq_sn04; + priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04); + } else { + priv.init_seq = scf0403_initseq_sn20; + priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20); + } + + scf0403_lcd_init(&priv); + + /* Start operation */ + scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison); + mdelay(100); + scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout); + spi_release_bus(priv.spi); + + return 0; + +readid_fail: + spi_release_bus(priv.spi); +bus_claim_fail: + if (gpio_is_valid(priv.reset_gpio)) + gpio_free(priv.reset_gpio); + + return error; +} diff --git a/drivers/video/sed13806.c b/drivers/video/sed13806.c index da653c0f51..cd7fac6f97 100644 --- a/drivers/video/sed13806.c +++ b/drivers/video/sed13806.c @@ -18,13 +18,8 @@ #define writeByte(ptrReg,value) \ *(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value -#ifdef CONFIG_TOTAL5200 -#define writeWord(ptrReg,value) \ - (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = value) -#else #define writeWord(ptrReg,value) \ (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00)) -#endif GraphicDevice sed13806; diff --git a/drivers/video/sed156x.c b/drivers/video/sed156x.c index d8b0d7f5d6..2c906ecf1e 100644 --- a/drivers/video/sed156x.c +++ b/drivers/video/sed156x.c @@ -4,7 +4,7 @@ * Pantelis Antoniou * Intracom S.A. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -25,7 +25,6 @@ /* include the font data */ #include -#include #if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16 #error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16 diff --git a/drivers/video/smiLynxEM.c b/drivers/video/smiLynxEM.c index 614bcb3c92..1880cccac2 100644 --- a/drivers/video/smiLynxEM.c +++ b/drivers/video/smiLynxEM.c @@ -131,9 +131,6 @@ static char SMI_PCR [] = { }; static char SMI_MCR[] = { 0x60, 0x01, 0x61, 0x00, -#ifdef CONFIG_HMI1001 - 0x62, 0x74, /* Memory type is not configured by pins on HMI1001 */ -#endif }; static char SMI_HCR[] = { diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c new file mode 100644 index 0000000000..8b09082254 --- /dev/null +++ b/drivers/video/ssd2828.c @@ -0,0 +1,436 @@ +/* + * (C) 2015 Siarhei Siamashka + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Support for the SSD2828 bridge chip, which can take pixel data coming + * from a parallel LCD interface and translate it on the flight into MIPI DSI + * interface for driving a MIPI compatible TFT display. + */ + +#include +#include +#include +#include + +#include "videomodes.h" +#include "ssd2828.h" + +#define SSD2828_DIR 0xB0 +#define SSD2828_VICR1 0xB1 +#define SSD2828_VICR2 0xB2 +#define SSD2828_VICR3 0xB3 +#define SSD2828_VICR4 0xB4 +#define SSD2828_VICR5 0xB5 +#define SSD2828_VICR6 0xB6 +#define SSD2828_CFGR 0xB7 +#define SSD2828_VCR 0xB8 +#define SSD2828_PCR 0xB9 +#define SSD2828_PLCR 0xBA +#define SSD2828_CCR 0xBB +#define SSD2828_PSCR1 0xBC +#define SSD2828_PSCR2 0xBD +#define SSD2828_PSCR3 0xBE +#define SSD2828_PDR 0xBF +#define SSD2828_OCR 0xC0 +#define SSD2828_MRSR 0xC1 +#define SSD2828_RDCR 0xC2 +#define SSD2828_ARSR 0xC3 +#define SSD2828_LCR 0xC4 +#define SSD2828_ICR 0xC5 +#define SSD2828_ISR 0xC6 +#define SSD2828_ESR 0xC7 +#define SSD2828_DAR1 0xC9 +#define SSD2828_DAR2 0xCA +#define SSD2828_DAR3 0xCB +#define SSD2828_DAR4 0xCC +#define SSD2828_DAR5 0xCD +#define SSD2828_DAR6 0xCE +#define SSD2828_HTTR1 0xCF +#define SSD2828_HTTR2 0xD0 +#define SSD2828_LRTR1 0xD1 +#define SSD2828_LRTR2 0xD2 +#define SSD2828_TSR 0xD3 +#define SSD2828_LRR 0xD4 +#define SSD2828_PLLR 0xD5 +#define SSD2828_TR 0xD6 +#define SSD2828_TECR 0xD7 +#define SSD2828_ACR1 0xD8 +#define SSD2828_ACR2 0xD9 +#define SSD2828_ACR3 0xDA +#define SSD2828_ACR4 0xDB +#define SSD2828_IOCR 0xDC +#define SSD2828_VICR7 0xDD +#define SSD2828_LCFR 0xDE +#define SSD2828_DAR7 0xDF +#define SSD2828_PUCR1 0xE0 +#define SSD2828_PUCR2 0xE1 +#define SSD2828_PUCR3 0xE2 +#define SSD2828_CBCR1 0xE9 +#define SSD2828_CBCR2 0xEA +#define SSD2828_CBSR 0xEB +#define SSD2828_ECR 0xEC +#define SSD2828_VSDR 0xED +#define SSD2828_TMR 0xEE +#define SSD2828_GPIO1 0xEF +#define SSD2828_GPIO2 0xF0 +#define SSD2828_DLYA01 0xF1 +#define SSD2828_DLYA23 0xF2 +#define SSD2828_DLYB01 0xF3 +#define SSD2828_DLYB23 0xF4 +#define SSD2828_DLYC01 0xF5 +#define SSD2828_DLYC23 0xF6 +#define SSD2828_ACR5 0xF7 +#define SSD2828_RR 0xFF + +#define SSD2828_CFGR_HS (1 << 0) +#define SSD2828_CFGR_CKE (1 << 1) +#define SSD2828_CFGR_SLP (1 << 2) +#define SSD2828_CFGR_VEN (1 << 3) +#define SSD2828_CFGR_HCLK (1 << 4) +#define SSD2828_CFGR_CSS (1 << 5) +#define SSD2828_CFGR_DCS (1 << 6) +#define SSD2828_CFGR_REN (1 << 7) +#define SSD2828_CFGR_ECD (1 << 8) +#define SSD2828_CFGR_EOT (1 << 9) +#define SSD2828_CFGR_LPE (1 << 10) +#define SSD2828_CFGR_TXD (1 << 11) + +#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2) +#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2) +#define SSD2828_VIDEO_MODE_BURST (2 << 2) + +#define SSD2828_VIDEO_PIXEL_FORMAT_16BPP 0 +#define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED 1 +#define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED 2 +#define SSD2828_VIDEO_PIXEL_FORMAT_24BPP 3 + +#define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F) + +/* + * SPI transfer, using the "24-bit 3 wire" mode (that's how it is called in + * the SSD2828 documentation). The 'dout' input parameter specifies 24-bits + * of data to be written to SSD2828. Returns the lowest 16-bits of data, + * that is received back. + */ +static u32 soft_spi_xfer_24bit_3wire(const struct ssd2828_config *drv, u32 dout) +{ + int j, bitlen = 24; + u32 tmpdin = 0; + /* + * According to the "24 Bit 3 Wire SPI Interface Timing Characteristics" + * and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet, + * the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs + * at 1/8 of that after reset. So using 1 microsecond delays is safe in + * the main loop. But the delays around chip select pin manipulations + * need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in + * the worst case). + */ + const int spi_delay_us = 1; + const int spi_cs_delay_us = 2; + + gpio_set_value(drv->csx_pin, 0); + udelay(spi_cs_delay_us); + for (j = bitlen - 1; j >= 0; j--) { + gpio_set_value(drv->sck_pin, 0); + gpio_set_value(drv->sdi_pin, (dout & (1 << j)) != 0); + udelay(spi_delay_us); + if (drv->sdo_pin != -1) + tmpdin = (tmpdin << 1) | gpio_get_value(drv->sdo_pin); + gpio_set_value(drv->sck_pin, 1); + udelay(spi_delay_us); + } + udelay(spi_cs_delay_us); + gpio_set_value(drv->csx_pin, 1); + udelay(spi_cs_delay_us); + return tmpdin & 0xFFFF; +} + +/* + * Read from a SSD2828 hardware register (regnum >= 0xB0) + */ +static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum) +{ + soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); + return soft_spi_xfer_24bit_3wire(cfg, 0x730000); +} + +/* + * Write to a SSD2828 hardware register (regnum >= 0xB0) + */ +static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum, + u16 val) +{ + soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); + soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val); +} + +/* + * Send MIPI command to the LCD panel (cmdnum < 0xB0) + */ +static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum) +{ + /* Set packet size to 1 (a single command with no parameters) */ + write_hw_register(cfg, SSD2828_PSCR1, 1); + /* Send the command */ + write_hw_register(cfg, SSD2828_PDR, cmdnum); +} + +/* + * Reset SSD2828 + */ +static void ssd2828_reset(const struct ssd2828_config *cfg) +{ + /* RESET needs 10 milliseconds according to the datasheet */ + gpio_set_value(cfg->reset_pin, 0); + mdelay(10); + gpio_set_value(cfg->reset_pin, 1); + mdelay(10); +} + +static int ssd2828_enable_gpio(const struct ssd2828_config *cfg) +{ + if (gpio_request(cfg->csx_pin, "ssd2828_csx")) { + printf("SSD2828: request for 'ssd2828_csx' pin failed\n"); + return 1; + } + if (gpio_request(cfg->sck_pin, "ssd2828_sck")) { + gpio_free(cfg->csx_pin); + printf("SSD2828: request for 'ssd2828_sck' pin failed\n"); + return 1; + } + if (gpio_request(cfg->sdi_pin, "ssd2828_sdi")) { + gpio_free(cfg->csx_pin); + gpio_free(cfg->sck_pin); + printf("SSD2828: request for 'ssd2828_sdi' pin failed\n"); + return 1; + } + if (gpio_request(cfg->reset_pin, "ssd2828_reset")) { + gpio_free(cfg->csx_pin); + gpio_free(cfg->sck_pin); + gpio_free(cfg->sdi_pin); + printf("SSD2828: request for 'ssd2828_reset' pin failed\n"); + return 1; + } + if (cfg->sdo_pin != -1 && gpio_request(cfg->sdo_pin, "ssd2828_sdo")) { + gpio_free(cfg->csx_pin); + gpio_free(cfg->sck_pin); + gpio_free(cfg->sdi_pin); + gpio_free(cfg->reset_pin); + printf("SSD2828: request for 'ssd2828_sdo' pin failed\n"); + return 1; + } + gpio_direction_output(cfg->reset_pin, 0); + gpio_direction_output(cfg->csx_pin, 1); + gpio_direction_output(cfg->sck_pin, 1); + gpio_direction_output(cfg->sdi_pin, 1); + if (cfg->sdo_pin != -1) + gpio_direction_input(cfg->sdo_pin); + + return 0; +} + +static int ssd2828_free_gpio(const struct ssd2828_config *cfg) +{ + gpio_free(cfg->csx_pin); + gpio_free(cfg->sck_pin); + gpio_free(cfg->sdi_pin); + gpio_free(cfg->reset_pin); + if (cfg->sdo_pin != -1) + gpio_free(cfg->sdo_pin); + return 1; +} + +/* + * PLL configuration register settings. + * + * See the "PLL Configuration Register Description" in the SSD2828 datasheet. + */ +static u32 construct_pll_config(u32 desired_pll_freq_kbps, + u32 reference_freq_khz) +{ + u32 div_factor = 1, mul_factor, fr = 0; + u32 output_freq_kbps; + + /* The intermediate clock after division can't be less than 5MHz */ + while (reference_freq_khz / (div_factor + 1) >= 5000) + div_factor++; + if (div_factor > 31) + div_factor = 31; + + mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor, + reference_freq_khz); + + output_freq_kbps = reference_freq_khz * mul_factor / div_factor; + + if (output_freq_kbps >= 501000) + fr = 3; + else if (output_freq_kbps >= 251000) + fr = 2; + else if (output_freq_kbps >= 126000) + fr = 1; + + return (fr << 14) | (div_factor << 8) | mul_factor; +} + +static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz) +{ + u32 mul_factor = pll_config & 0xFF; + u32 div_factor = (pll_config >> 8) & 0x1F; + if (mul_factor == 0) + mul_factor = 1; + if (div_factor == 0) + div_factor = 1; + return reference_freq_khz * mul_factor / div_factor; +} + +static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg, + const struct ctfb_res_modes *mode) +{ + u32 val; + + /* RGB Interface Control Register 1 */ + write_hw_register(cfg, SSD2828_VICR1, (mode->vsync_len << 8) | + (mode->hsync_len)); + + /* RGB Interface Control Register 2 */ + u32 vbp = mode->vsync_len + mode->upper_margin; + u32 hbp = mode->hsync_len + mode->left_margin; + write_hw_register(cfg, SSD2828_VICR2, (vbp << 8) | hbp); + + /* RGB Interface Control Register 3 */ + write_hw_register(cfg, SSD2828_VICR3, (mode->lower_margin << 8) | + (mode->right_margin)); + + /* RGB Interface Control Register 4 */ + write_hw_register(cfg, SSD2828_VICR4, mode->xres); + + /* RGB Interface Control Register 5 */ + write_hw_register(cfg, SSD2828_VICR5, mode->yres); + + /* RGB Interface Control Register 6 */ + val = SSD2828_VIDEO_MODE_BURST; + switch (cfg->ssd2828_color_depth) { + case 16: + val |= SSD2828_VIDEO_PIXEL_FORMAT_16BPP; + break; + case 18: + val |= cfg->mipi_dsi_loosely_packed_pixel_format ? + SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED : + SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED; + break; + case 24: + val |= SSD2828_VIDEO_PIXEL_FORMAT_24BPP; + break; + default: + printf("SSD2828: unsupported color depth\n"); + return 1; + } + write_hw_register(cfg, SSD2828_VICR6, val); + + /* Lane Configuration Register */ + write_hw_register(cfg, SSD2828_LCFR, + cfg->mipi_dsi_number_of_data_lanes - 1); + + return 0; +} + +int ssd2828_init(const struct ssd2828_config *cfg, + const struct ctfb_res_modes *mode) +{ + u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config; + /* The LP clock speed is limited by 10MHz */ + const u32 mipi_dsi_low_power_clk_khz = 10000; + /* + * This is just the reset default value of CFGR register (0x301). + * Because we are not always able to read back from SPI, have + * it initialized here. + */ + u32 cfgr_reg = SSD2828_CFGR_EOT | /* EOT Packet Enable */ + SSD2828_CFGR_ECD | /* Disable ECC and CRC */ + SSD2828_CFGR_HS; /* Data lanes are in HS mode */ + + /* Initialize the pins */ + if (ssd2828_enable_gpio(cfg) != 0) + return 1; + + /* Reset the chip */ + ssd2828_reset(cfg); + + /* + * If there is a pin to read data back from SPI, then we are lucky. Try + * to check if SPI is configured correctly and SSD2828 is actually able + * to talk back. + */ + if (cfg->sdo_pin != -1) { + if (read_hw_register(cfg, SSD2828_DIR) != 0x2828 || + read_hw_register(cfg, SSD2828_CFGR) != cfgr_reg) { + printf("SSD2828: SPI communication failed.\n"); + ssd2828_free_gpio(cfg); + return 1; + } + } + + /* + * Pick the reference clock for PLL. If we know the exact 'tx_clk' + * clock speed, then everything is good. If not, then we can fallback + * to 'pclk' (pixel clock from the parallel LCD interface). In the + * case of using this fallback, it is necessary to have parallel LCD + * already initialized and running at this point. + */ + reference_freq_khz = cfg->ssd2828_tx_clk_khz; + if (reference_freq_khz == 0) { + reference_freq_khz = mode->pixclock_khz; + /* Use 'pclk' as the reference clock for PLL */ + cfgr_reg |= SSD2828_CFGR_CSS; + } + + /* + * Setup the parallel LCD timings in the appropriate registers. + */ + if (ssd2828_configure_video_interface(cfg, mode) != 0) { + ssd2828_free_gpio(cfg); + return 1; + } + + /* Configuration Register */ + cfgr_reg &= ~SSD2828_CFGR_HS; /* Data lanes are in LP mode */ + cfgr_reg |= SSD2828_CFGR_CKE; /* Clock lane is in HS mode */ + cfgr_reg |= SSD2828_CFGR_DCS; /* Only use DCS packets */ + write_hw_register(cfg, SSD2828_CFGR, cfgr_reg); + + /* PLL Configuration Register */ + pll_config = construct_pll_config( + cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000, + reference_freq_khz); + write_hw_register(cfg, SSD2828_PLCR, pll_config); + + pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz); + lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8); + + /* VC Control Register */ + write_hw_register(cfg, SSD2828_VCR, 0); + + /* Clock Control Register */ + write_hw_register(cfg, SSD2828_CCR, SSD2828_LP_CLOCK_DIVIDER(lp_div)); + + /* PLL Control Register */ + write_hw_register(cfg, SSD2828_PCR, 1); /* Enable PLL */ + + /* Wait for PLL lock */ + udelay(500); + + send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE); + mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms); + + send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON); + mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms); + + cfgr_reg |= SSD2828_CFGR_HS; /* Enable HS mode for data lanes */ + cfgr_reg |= SSD2828_CFGR_VEN; /* Enable video pipeline */ + write_hw_register(cfg, SSD2828_CFGR, cfgr_reg); + + return 0; +} diff --git a/drivers/video/ssd2828.h b/drivers/video/ssd2828.h new file mode 100644 index 0000000000..1af6fa4023 --- /dev/null +++ b/drivers/video/ssd2828.h @@ -0,0 +1,128 @@ +/* + * (C) 2015 Siarhei Siamashka + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Support for the SSD2828 bridge chip, which can take pixel data coming + * from a parallel LCD interface and translate it on the flight into MIPI DSI + * interface for driving a MIPI compatible TFT display. + * + * Implemented as a utility function. To be used from display drivers, which are + * responsible for driving parallel LCD hardware in front of the video pipeline. + */ + +#ifndef _SSD2828_H +#define _SSD2828_H + +struct ctfb_res_modes; + +struct ssd2828_config { + /*********************************************************************/ + /* SSD2828 configuration */ + /*********************************************************************/ + + /* + * The pins, which are used for SPI communication. This is only used + * for configuring SSD2828, so the performance is irrelevant (only + * around a hundred of bytes is moved). Also these can be any arbitrary + * GPIO pins (not necessarily the pins having hardware SPI function). + * Moreover, the 'sdo' pin may be even not wired up in some devices. + * + * These configuration variables need to be set as pin numbers for + * the standard u-boot GPIO interface (gpio_get_value/gpio_set_value + * functions). Note that -1 value can be used for the pins, which are + * not really wired up. + */ + int csx_pin; + int sck_pin; + int sdi_pin; + int sdo_pin; + /* SSD2828 reset pin (shared with LCD panel reset) */ + int reset_pin; + + /* + * The SSD2828 has its own dedicated clock source 'tx_clk' (connected + * to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for + * clocking SPI after reset. The exact clock speed is not strictly, + * defined, but the datasheet says that it must be somewhere in the + * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also + * used as a reference clock for PLL. If the exact clock frequency + * is known, then it can be specified here. If it is unknown, or the + * information is not trustworthy, then it can be set to 0. + * + * If unsure, set to 0. + */ + int ssd2828_tx_clk_khz; + + /* + * This is not a property of the used LCD panel, but more like a + * property of the SSD2828 wiring. See the "SSD2828QN4 RGB data + * arrangement" table in the datasheet. The SSD2828 pins are arranged + * in such a way that 18bpp and 24bpp configurations are completely + * incompatible with each other. + * + * Depending on the color depth, this must be set to 16, 18 or 24. + */ + int ssd2828_color_depth; + + /*********************************************************************/ + /* LCD panel configuration */ + /*********************************************************************/ + + /* + * The number of lanes in the MIPI DSI interface. May vary from 1 to 4. + * + * This information can be found in the LCD panel datasheet. + */ + int mipi_dsi_number_of_data_lanes; + + /* + * Data transfer bit rate per lane. Please note that it is expected + * to be higher than the pixel clock rate of the used video mode when + * multiplied by the number of lanes. This is perfectly normal because + * MIPI DSI handles data transfers in periodic bursts, and uses the + * idle time between bursts for sending configuration information and + * commands. Or just for saving power. + * + * The necessary Mbps/lane information can be found in the LCD panel + * datasheet. Note that the transfer rate can't be always set precisely + * and it may be rounded *up* (introducing no more than 10Mbps error). + */ + int mipi_dsi_bitrate_per_data_lane_mbps; + + /* + * Setting this to 1 enforces packing of 18bpp pixel data in 24bpp + * envelope when sending it over the MIPI DSI link. + * + * If unsure, set to 0. + */ + int mipi_dsi_loosely_packed_pixel_format; + + /* + * According to the "Example for system sleep in and out" section in + * the SSD2828 datasheet, some LCD panel specific delays are necessary + * after MIPI DCS commands EXIT_SLEEP_MODE and SET_DISPLAY_ON. + * + * For example, Allwinner uses 100 milliseconds delay after + * EXIT_SLEEP_MODE and 200 milliseconds delay after SET_DISPLAY_ON. + */ + int mipi_dsi_delay_after_exit_sleep_mode_ms; + int mipi_dsi_delay_after_set_display_on_ms; +}; + +/* + * Initialize the SSD2828 chip. It needs the 'ssd2828_config' structure + * and also the video mode timings. + * + * The right place to insert this function call is after the parallel LCD + * interface is initialized and before turning on the backlight. This is + * advised in the "Example for system sleep in and out" section of the + * SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source + * for PLL, which means that the input signal must be already there. + */ +int ssd2828_init(const struct ssd2828_config *cfg, + const struct ctfb_res_modes *mode); + +#endif diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c new file mode 100644 index 0000000000..f5f24fc020 --- /dev/null +++ b/drivers/video/sunxi_display.c @@ -0,0 +1,1249 @@ +/* + * Display driver for Allwinner SoCs. + * + * (C) Copyright 2013-2014 Luc Verhaegen + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "videomodes.h" +#include "hitachi_tx18d42vm_lcd.h" +#include "ssd2828.h" + +#ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW +#define PWM_ON 0 +#define PWM_OFF 1 +#else +#define PWM_ON 1 +#define PWM_OFF 0 +#endif + +DECLARE_GLOBAL_DATA_PTR; + +enum sunxi_monitor { + sunxi_monitor_none, + sunxi_monitor_dvi, + sunxi_monitor_hdmi, + sunxi_monitor_lcd, + sunxi_monitor_vga, +}; +#define SUNXI_MONITOR_LAST sunxi_monitor_vga + +struct sunxi_display { + GraphicDevice graphic_device; + enum sunxi_monitor monitor; + unsigned int depth; +} sunxi_display; + +#ifdef CONFIG_VIDEO_HDMI + +/* + * Wait up to 200ms for value to be set in given part of reg. + */ +static int await_completion(u32 *reg, u32 mask, u32 val) +{ + unsigned long tmo = timer_get_us() + 200000; + + while ((readl(reg) & mask) != val) { + if (timer_get_us() > tmo) { + printf("DDC: timeout reading EDID\n"); + return -ETIME; + } + } + return 0; +} + +static int sunxi_hdmi_hpd_detect(int hpd_delay) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + unsigned long tmo = timer_get_us() + hpd_delay * 1000; + + /* Set pll3 to 300MHz */ + clock_set_pll3(300000000); + + /* Set hdmi parent to pll3 */ + clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, + CCM_HDMI_CTRL_PLL3); + + /* Set ahb gating to pass */ +#ifdef CONFIG_MACH_SUN6I + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); +#endif + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); + + /* Clock on */ + setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); + + writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl); + writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0); + + while (timer_get_us() < tmo) { + if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT) + return 1; + } + + return 0; +} + +static void sunxi_hdmi_shutdown(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + + clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE); + clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); + clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); +#ifdef CONFIG_MACH_SUN6I + clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); +#endif + clock_set_pll3(0); +} + +static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n) +{ + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + + setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR); + writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) | + SUNXI_HMDI_DDC_ADDR_EDDC_ADDR | + SUNXI_HMDI_DDC_ADDR_OFFSET(offset) | + SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr); +#ifndef CONFIG_MACH_SUN6I + writel(n, &hdmi->ddc_byte_count); + writel(cmnd, &hdmi->ddc_cmnd); +#else + writel(n << 16 | cmnd, &hdmi->ddc_cmnd); +#endif + setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START); + + return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0); +} + +static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count) +{ + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + int i, n; + + while (count > 0) { + if (count > 16) + n = 16; + else + n = count; + + if (sunxi_hdmi_ddc_do_command( + SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ, + offset, n)) + return -ETIME; + + for (i = 0; i < n; i++) + *buf++ = readb(&hdmi->ddc_fifo_data); + + offset += n; + count -= n; + } + + return 0; +} + +static int sunxi_hdmi_edid_get_block(int block, u8 *buf) +{ + int r, retries = 2; + + do { + r = sunxi_hdmi_ddc_read(block * 128, buf, 128); + if (r) + continue; + r = edid_check_checksum(buf); + if (r) { + printf("EDID block %d: checksum error%s\n", + block, retries ? ", retrying" : ""); + } + } while (r && retries--); + + return r; +} + +static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode) +{ + struct edid1_info edid1; + struct edid_cea861_info cea681[4]; + struct edid_detailed_timing *t = + (struct edid_detailed_timing *)edid1.monitor_details.timing; + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int i, r, ext_blocks = 0; + + /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */ + writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE, + &hdmi->pad_ctrl1); + writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15), + &hdmi->pll_ctrl); + writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); + + /* Reset i2c controller */ + setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); + writel(SUNXI_HMDI_DDC_CTRL_ENABLE | + SUNXI_HMDI_DDC_CTRL_SDA_ENABLE | + SUNXI_HMDI_DDC_CTRL_SCL_ENABLE | + SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl); + if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0)) + return -EIO; + + writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock); +#ifndef CONFIG_MACH_SUN6I + writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE | + SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl); +#endif + + r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1); + if (r == 0) { + r = edid_check_info(&edid1); + if (r) { + printf("EDID: invalid EDID data\n"); + r = -EINVAL; + } + } + if (r == 0) { + ext_blocks = edid1.extension_flag; + if (ext_blocks > 4) + ext_blocks = 4; + for (i = 0; i < ext_blocks; i++) { + if (sunxi_hdmi_edid_get_block(1 + i, + (u8 *)&cea681[i]) != 0) { + ext_blocks = i; + break; + } + } + } + + /* Disable DDC engine, no longer needed */ + clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE); + clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); + + if (r) + return r; + + /* We want version 1.3 or 1.2 with detailed timing info */ + if (edid1.version != 1 || (edid1.revision < 3 && + !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) { + printf("EDID: unsupported version %d.%d\n", + edid1.version, edid1.revision); + return -EINVAL; + } + + /* Take the first usable detailed timing */ + for (i = 0; i < 4; i++, t++) { + r = video_edid_dtd_to_ctfb_res_modes(t, mode); + if (r == 0) + break; + } + if (i == 4) { + printf("EDID: no usable detailed timing found\n"); + return -ENOENT; + } + + /* Check for basic audio support, if found enable hdmi output */ + sunxi_display.monitor = sunxi_monitor_dvi; + for (i = 0; i < ext_blocks; i++) { + if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG || + cea681[i].revision < 2) + continue; + + if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i])) + sunxi_display.monitor = sunxi_monitor_hdmi; + } + + return 0; +} + +#endif /* CONFIG_VIDEO_HDMI */ + +#ifdef CONFIG_MACH_SUN4I +/* + * Testing has shown that on sun4i the display backend engine does not have + * deep enough fifo-s causing flickering / tearing in full-hd mode due to + * fifo underruns. So on sun4i we use the display frontend engine to do the + * dma from memory, as the frontend does have deep enough fifo-s. + */ + +static const u32 sun4i_vert_coef[32] = { + 0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd, + 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb, + 0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb, + 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc, + 0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd, + 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff, + 0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff, + 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100, +}; + +static const u32 sun4i_horz_coef[64] = { + 0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03, + 0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06, + 0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09, + 0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f, + 0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12, + 0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18, + 0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e, + 0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23, + 0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29, + 0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e, + 0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33, + 0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37, + 0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b, + 0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e, + 0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40, + 0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42, +}; + +static void sunxi_frontend_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_de_fe_reg * const de_fe = + (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE; + int i; + + /* Clocks on */ + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0); + setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0); + clock_set_de_mod_clock(&ccm->fe0_clk_cfg, 300000000); + + setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN); + + for (i = 0; i < 32; i++) { + writel(sun4i_horz_coef[2 * i], &de_fe->ch0_horzcoef0[i]); + writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch0_horzcoef1[i]); + writel(sun4i_vert_coef[i], &de_fe->ch0_vertcoef[i]); + writel(sun4i_horz_coef[2 * i], &de_fe->ch1_horzcoef0[i]); + writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch1_horzcoef1[i]); + writel(sun4i_vert_coef[i], &de_fe->ch1_vertcoef[i]); + } + + setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY); +} + +static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode, + unsigned int address) +{ + struct sunxi_de_fe_reg * const de_fe = + (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE; + + setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS); + writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr); + writel(mode->xres * 4, &de_fe->ch0_stride); + writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt); + writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt); + + writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres), + &de_fe->ch0_insize); + writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres), + &de_fe->ch0_outsize); + writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_horzfact); + writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_vertfact); + + writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres), + &de_fe->ch1_insize); + writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres), + &de_fe->ch1_outsize); + writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_horzfact); + writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_vertfact); + + setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_REG_RDY); +} + +static void sunxi_frontend_enable(void) +{ + struct sunxi_de_fe_reg * const de_fe = + (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE; + + setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_FRM_START); +} +#else +static void sunxi_frontend_init(void) {} +static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode, + unsigned int address) {} +static void sunxi_frontend_enable(void) {} +#endif + +/* + * This is the entity that mixes and matches the different layers and inputs. + * Allwinner calls it the back-end, but i like composer better. + */ +static void sunxi_composer_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_de_be_reg * const de_be = + (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE; + int i; + + sunxi_frontend_init(); + +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + /* Reset off */ + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0); +#endif + + /* Clocks on */ + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0); +#ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */ + setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0); +#endif + clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000); + + /* Engine bug, clear registers after reset */ + for (i = 0x0800; i < 0x1000; i += 4) + writel(0, SUNXI_DE_BE0_BASE + i); + + setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE); +} + +static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode, + unsigned int address) +{ + struct sunxi_de_be_reg * const de_be = + (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE; + + sunxi_frontend_mode_set(mode, address); + + writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres), + &de_be->disp_size); + writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres), + &de_be->layer0_size); +#ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */ + writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride); + writel(address << 3, &de_be->layer0_addr_low32b); + writel(address >> 29, &de_be->layer0_addr_high4b); +#else + writel(SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0, &de_be->layer0_attr0_ctrl); +#endif + writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl); + + setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE); +} + +static void sunxi_composer_enable(void) +{ + struct sunxi_de_be_reg * const de_be = + (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE; + + sunxi_frontend_enable(); + + setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS); + setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START); +} + +/* + * LCDC, what allwinner calls a CRTC, so timing controller and serializer. + */ +static void sunxi_lcdc_pll_set(int tcon, int dotclock, + int *clk_div, int *clk_double) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int value, n, m, min_m, max_m, diff; + int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; + int best_double = 0; + + if (tcon == 0) { +#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL + min_m = 6; + max_m = 127; +#endif +#ifdef CONFIG_VIDEO_LCD_IF_LVDS + min_m = max_m = 7; +#endif + } else { + min_m = 1; + max_m = 15; + } + + /* + * Find the lowest divider resulting in a matching clock, if there + * is no match, pick the closest lower clock, as monitors tend to + * not sync to higher frequencies. + */ + for (m = min_m; m <= max_m; m++) { + n = (m * dotclock) / 3000; + + if ((n >= 9) && (n <= 127)) { + value = (3000 * n) / m; + diff = dotclock - value; + if (diff < best_diff) { + best_diff = diff; + best_m = m; + best_n = n; + best_double = 0; + } + } + + /* These are just duplicates */ + if (!(m & 1)) + continue; + + n = (m * dotclock) / 6000; + if ((n >= 9) && (n <= 127)) { + value = (6000 * n) / m; + diff = dotclock - value; + if (diff < best_diff) { + best_diff = diff; + best_m = m; + best_n = n; + best_double = 1; + } + } + } + + debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n", + dotclock, (best_double + 1) * 3000 * best_n / best_m, + best_double + 1, best_n, best_m); + + clock_set_pll3(best_n * 3000000); + + if (tcon == 0) { + writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | + (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X : + CCM_LCD_CH0_CTRL_PLL3), + &ccm->lcd0_ch0_clk_cfg); + } else { + writel(CCM_LCD_CH1_CTRL_GATE | + (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : + CCM_LCD_CH1_CTRL_PLL3) | + CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg); + } + + *clk_div = best_m; + *clk_double = best_double; +} + +static void sunxi_lcdc_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_lcdc_reg * const lcdc = + (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; + + /* Reset off */ +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); +#else + setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST); +#endif + + /* Clock on */ + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); +#ifdef CONFIG_VIDEO_LCD_IF_LVDS + setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST); +#endif + + /* Init lcdc */ + writel(0, &lcdc->ctrl); /* Disable tcon */ + writel(0, &lcdc->int0); /* Disable all interrupts */ + + /* Disable tcon0 dot clock */ + clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE); + + /* Set all io lines to tristate */ + writel(0xffffffff, &lcdc->tcon0_io_tristate); + writel(0xffffffff, &lcdc->tcon1_io_tristate); +} + +static void sunxi_lcdc_enable(void) +{ + struct sunxi_lcdc_reg * const lcdc = + (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; + + setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); +#ifdef CONFIG_VIDEO_LCD_IF_LVDS + setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE); + setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); + setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); + udelay(2); /* delay at least 1200 ns */ + setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); + udelay(1); /* delay at least 120 ns */ + setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); + setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); +#endif +} + +static void sunxi_lcdc_panel_enable(void) +{ + int pin; + + /* + * Start with backlight disabled to avoid the screen flashing to + * white while the lcd inits. + */ + pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN); + if (pin != -1) { + gpio_request(pin, "lcd_backlight_enable"); + gpio_direction_output(pin, 0); + } + + pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM); + if (pin != -1) { + gpio_request(pin, "lcd_backlight_pwm"); + gpio_direction_output(pin, PWM_OFF); + } + + /* Give the backlight some time to turn off and power up the panel. */ + mdelay(40); + pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER); + if (pin != -1) { + gpio_request(pin, "lcd_power"); + gpio_direction_output(pin, 1); + } +} + +static void sunxi_lcdc_backlight_enable(void) +{ + int pin; + + /* + * We want to have scanned out at least one frame before enabling the + * backlight to avoid the screen flashing to white when we enable it. + */ + mdelay(40); + + pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN); + if (pin != -1) + gpio_direction_output(pin, 1); + + pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM); + if (pin != -1) + gpio_direction_output(pin, PWM_ON); +} + +static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode) +{ + int delay; + + delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2; + return (delay > 30) ? 30 : delay; +} + +static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode, + bool for_ext_vga_dac) +{ + struct sunxi_lcdc_reg * const lcdc = + (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; + int bp, clk_delay, clk_div, clk_double, pin, total, val; + + for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) +#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL + sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0); +#endif +#ifdef CONFIG_VIDEO_LCD_IF_LVDS + sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LVDS0); +#endif + + sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double); + + /* Use tcon0 */ + clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, + SUNXI_LCDC_CTRL_IO_MAP_TCON0); + + clk_delay = sunxi_lcdc_get_clk_delay(mode); + writel(SUNXI_LCDC_TCON0_CTRL_ENABLE | + SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl); + + writel(SUNXI_LCDC_TCON0_DCLK_ENABLE | + SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk); + + writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres), + &lcdc->tcon0_timing_active); + + bp = mode->hsync_len + mode->left_margin; + total = mode->xres + mode->right_margin + bp; + writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) | + SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h); + + bp = mode->vsync_len + mode->upper_margin; + total = mode->yres + mode->lower_margin + bp; + writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) | + SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v); + +#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL + writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len), + &lcdc->tcon0_timing_sync); + + writel(0, &lcdc->tcon0_hv_intf); + writel(0, &lcdc->tcon0_cpu_intf); +#endif +#ifdef CONFIG_VIDEO_LCD_IF_LVDS + val = (sunxi_display.depth == 18) ? 1 : 0; + writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val), &lcdc->tcon0_lvds_intf); +#endif + + if (sunxi_display.depth == 18 || sunxi_display.depth == 16) { + writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]); + writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]); + writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]); + writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]); + writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]); + writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]); + writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]); + writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]); + writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]); + writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]); + writel(((sunxi_display.depth == 18) ? + SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 : + SUNXI_LCDC_TCON0_FRM_CTRL_RGB565), + &lcdc->tcon0_frm_ctrl); + } + + val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE); + if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) + val |= SUNXI_LCDC_TCON_HSYNC_MASK; + if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) + val |= SUNXI_LCDC_TCON_VSYNC_MASK; + +#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH + if (for_ext_vga_dac) + val = 0; +#endif + writel(val, &lcdc->tcon0_io_polarity); + + writel(0, &lcdc->tcon0_io_tristate); +} + +#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA +static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode, + int *clk_div, int *clk_double, + bool use_portd_hvsync) +{ + struct sunxi_lcdc_reg * const lcdc = + (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; + int bp, clk_delay, total, val; + + /* Use tcon1 */ + clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, + SUNXI_LCDC_CTRL_IO_MAP_TCON1); + + clk_delay = sunxi_lcdc_get_clk_delay(mode); + writel(SUNXI_LCDC_TCON1_CTRL_ENABLE | + SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl); + + writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres), + &lcdc->tcon1_timing_source); + writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres), + &lcdc->tcon1_timing_scale); + writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres), + &lcdc->tcon1_timing_out); + + bp = mode->hsync_len + mode->left_margin; + total = mode->xres + mode->right_margin + bp; + writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) | + SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h); + + bp = mode->vsync_len + mode->upper_margin; + total = mode->yres + mode->lower_margin + bp; + writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) | + SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v); + + writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len), + &lcdc->tcon1_timing_sync); + + if (use_portd_hvsync) { + sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0); + sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0); + + val = 0; + if (mode->sync & FB_SYNC_HOR_HIGH_ACT) + val |= SUNXI_LCDC_TCON_HSYNC_MASK; + if (mode->sync & FB_SYNC_VERT_HIGH_ACT) + val |= SUNXI_LCDC_TCON_VSYNC_MASK; + writel(val, &lcdc->tcon1_io_polarity); + + clrbits_le32(&lcdc->tcon1_io_tristate, + SUNXI_LCDC_TCON_VSYNC_MASK | + SUNXI_LCDC_TCON_HSYNC_MASK); + } + sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double); +} +#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA */ + +#ifdef CONFIG_VIDEO_HDMI + +static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode) +{ + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + u8 checksum = 0; + u8 avi_info_frame[17] = { + 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + u8 vendor_info_frame[19] = { + 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00 + }; + int i; + + if (mode->pixclock_khz <= 27000) + avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */ + else + avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */ + + if (mode->xres * 100 / mode->yres < 156) + avi_info_frame[5] |= 0x18; /* 4 : 3 */ + else + avi_info_frame[5] |= 0x28; /* 16 : 9 */ + + for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++) + checksum += avi_info_frame[i]; + + avi_info_frame[3] = 0x100 - checksum; + + for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++) + writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]); + + writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0); + writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1); + + for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++) + writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]); + + writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0); + writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1); + + setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI); +} + +static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode, + int clk_div, int clk_double) +{ + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + int x, y; + + /* Write clear interrupt status bits */ + writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq); + + if (sunxi_display.monitor == sunxi_monitor_hdmi) + sunxi_hdmi_setup_info_frames(mode); + + /* Set input sync enable */ + writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown); + + /* Init various registers, select pll3 as clock source */ + writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity); + writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0); + writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1); + writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl); + writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); + + /* Setup clk div and doubler */ + clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK, + SUNXI_HDMI_PLL_CTRL_DIV(clk_div)); + if (!clk_double) + setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE); + + /* Setup timing registers */ + writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres), + &hdmi->video_size); + + x = mode->hsync_len + mode->left_margin; + y = mode->vsync_len + mode->upper_margin; + writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp); + + x = mode->right_margin; + y = mode->lower_margin; + writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp); + + x = mode->hsync_len; + y = mode->vsync_len; + writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw); + + if (mode->sync & FB_SYNC_HOR_HIGH_ACT) + setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR); + + if (mode->sync & FB_SYNC_VERT_HIGH_ACT) + setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER); +} + +static void sunxi_hdmi_enable(void) +{ + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + + udelay(100); + setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE); +} + +#endif /* CONFIG_VIDEO_HDMI */ + +#ifdef CONFIG_VIDEO_VGA + +static void sunxi_vga_mode_set(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_tve_reg * const tve = + (struct sunxi_tve_reg *)SUNXI_TVE0_BASE; + + /* Clock on */ + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0); + + /* Set TVE in VGA mode */ + writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | + SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) | + SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl); + writel(SUNXI_TVE_GCTRL_CFG0_VGA, &tve->cfg0); + writel(SUNXI_TVE_GCTRL_DAC_CFG0_VGA, &tve->dac_cfg0); + writel(SUNXI_TVE_GCTRL_UNKNOWN1_VGA, &tve->unknown1); +} + +static void sunxi_vga_enable(void) +{ + struct sunxi_tve_reg * const tve = + (struct sunxi_tve_reg *)SUNXI_TVE0_BASE; + + setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE); +} + +#endif /* CONFIG_VIDEO_VGA */ + +static void sunxi_drc_init(void) +{ +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* On sun6i the drc must be clocked even when in pass-through mode */ + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0); + clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000); +#endif +} + +#ifdef CONFIG_VIDEO_VGA_VIA_LCD +static void sunxi_vga_external_dac_enable(void) +{ + int pin; + + pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN); + if (pin != -1) { + gpio_request(pin, "vga_enable"); + gpio_direction_output(pin, 1); + } +} +#endif /* CONFIG_VIDEO_VGA_VIA_LCD */ + +#ifdef CONFIG_VIDEO_LCD_SSD2828 +static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode) +{ + struct ssd2828_config cfg = { + .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS), + .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK), + .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI), + .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO), + .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET), + .ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000, + .ssd2828_color_depth = 24, +#ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 + .mipi_dsi_number_of_data_lanes = 4, + .mipi_dsi_bitrate_per_data_lane_mbps = 513, + .mipi_dsi_delay_after_exit_sleep_mode_ms = 100, + .mipi_dsi_delay_after_set_display_on_ms = 200 +#else +#error MIPI LCD panel needs configuration parameters +#endif + }; + + if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) { + printf("SSD2828: SPI pins are not properly configured\n"); + return 1; + } + if (cfg.reset_pin == -1) { + printf("SSD2828: Reset pin is not properly configured\n"); + return 1; + } + + return ssd2828_init(&cfg, mode); +} +#endif /* CONFIG_VIDEO_LCD_SSD2828 */ + +static void sunxi_engines_init(void) +{ + sunxi_composer_init(); + sunxi_lcdc_init(); + sunxi_drc_init(); +} + +static void sunxi_mode_set(const struct ctfb_res_modes *mode, + unsigned int address) +{ + int __maybe_unused clk_div, clk_double; + + switch (sunxi_display.monitor) { + case sunxi_monitor_none: + break; + case sunxi_monitor_dvi: + case sunxi_monitor_hdmi: +#ifdef CONFIG_VIDEO_HDMI + sunxi_composer_mode_set(mode, address); + sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0); + sunxi_hdmi_mode_set(mode, clk_div, clk_double); + sunxi_composer_enable(); + sunxi_lcdc_enable(); + sunxi_hdmi_enable(); +#endif + break; + case sunxi_monitor_lcd: + sunxi_lcdc_panel_enable(); + if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) { + mdelay(50); /* Wait for lcd controller power on */ + hitachi_tx18d42vm_init(); + } + sunxi_composer_mode_set(mode, address); + sunxi_lcdc_tcon0_mode_set(mode, false); + sunxi_composer_enable(); + sunxi_lcdc_enable(); +#ifdef CONFIG_VIDEO_LCD_SSD2828 + sunxi_ssd2828_init(mode); +#endif + sunxi_lcdc_backlight_enable(); + break; + case sunxi_monitor_vga: +#ifdef CONFIG_VIDEO_VGA + sunxi_composer_mode_set(mode, address); + sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1); + sunxi_vga_mode_set(); + sunxi_composer_enable(); + sunxi_lcdc_enable(); + sunxi_vga_enable(); +#elif defined CONFIG_VIDEO_VGA_VIA_LCD + sunxi_composer_mode_set(mode, address); + sunxi_lcdc_tcon0_mode_set(mode, true); + sunxi_composer_enable(); + sunxi_lcdc_enable(); + sunxi_vga_external_dac_enable(); +#endif + break; + } +} + +static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor) +{ + switch (monitor) { + case sunxi_monitor_none: return "none"; + case sunxi_monitor_dvi: return "dvi"; + case sunxi_monitor_hdmi: return "hdmi"; + case sunxi_monitor_lcd: return "lcd"; + case sunxi_monitor_vga: return "vga"; + } + return NULL; /* never reached */ +} + +void *video_hw_init(void) +{ + static GraphicDevice *graphic_device = &sunxi_display.graphic_device; + const struct ctfb_res_modes *mode; + struct ctfb_res_modes custom; + const char *options; +#ifdef CONFIG_VIDEO_HDMI + int ret, hpd, hpd_delay, edid; +#endif + char mon[16]; + char *lcd_mode = CONFIG_VIDEO_LCD_MODE; + int i; + + memset(&sunxi_display, 0, sizeof(struct sunxi_display)); + + printf("Reserved %dkB of RAM for Framebuffer.\n", + CONFIG_SUNXI_FB_SIZE >> 10); + gd->fb_base = gd->ram_top; + + video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, + &sunxi_display.depth, &options); +#ifdef CONFIG_VIDEO_HDMI + hpd = video_get_option_int(options, "hpd", 1); + hpd_delay = video_get_option_int(options, "hpd_delay", 500); + edid = video_get_option_int(options, "edid", 1); + sunxi_display.monitor = sunxi_monitor_dvi; +#elif defined CONFIG_VIDEO_VGA_VIA_LCD + sunxi_display.monitor = sunxi_monitor_vga; +#else + sunxi_display.monitor = sunxi_monitor_lcd; +#endif + video_get_option_string(options, "monitor", mon, sizeof(mon), + sunxi_get_mon_desc(sunxi_display.monitor)); + for (i = 0; i <= SUNXI_MONITOR_LAST; i++) { + if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) { + sunxi_display.monitor = i; + break; + } + } + if (i > SUNXI_MONITOR_LAST) + printf("Unknown monitor: '%s', falling back to '%s'\n", + mon, sunxi_get_mon_desc(sunxi_display.monitor)); + +#ifdef CONFIG_VIDEO_HDMI + /* If HDMI/DVI is selected do HPD & EDID, and handle fallback */ + if (sunxi_display.monitor == sunxi_monitor_dvi || + sunxi_display.monitor == sunxi_monitor_hdmi) { + /* Always call hdp_detect, as it also enables clocks, etc. */ + ret = sunxi_hdmi_hpd_detect(hpd_delay); + if (ret) { + printf("HDMI connected: "); + if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0) + mode = &custom; + } else if (hpd) { + sunxi_hdmi_shutdown(); + /* Fallback to lcd / vga / none */ + if (lcd_mode[0]) { + sunxi_display.monitor = sunxi_monitor_lcd; + } else { +#if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA + sunxi_display.monitor = sunxi_monitor_vga; +#else + sunxi_display.monitor = sunxi_monitor_none; +#endif + } + } /* else continue with hdmi/dvi without a cable connected */ + } +#endif + + switch (sunxi_display.monitor) { + case sunxi_monitor_none: + return NULL; + case sunxi_monitor_dvi: + case sunxi_monitor_hdmi: +#ifdef CONFIG_VIDEO_HDMI + break; +#else + printf("HDMI/DVI not supported on this board\n"); + sunxi_display.monitor = sunxi_monitor_none; + return NULL; +#endif + case sunxi_monitor_lcd: + if (lcd_mode[0]) { + sunxi_display.depth = video_get_params(&custom, lcd_mode); + mode = &custom; + break; + } + printf("LCD not supported on this board\n"); + sunxi_display.monitor = sunxi_monitor_none; + return NULL; + case sunxi_monitor_vga: +#if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA + sunxi_display.depth = 18; + break; +#else + printf("VGA not supported on this board\n"); + sunxi_display.monitor = sunxi_monitor_none; + return NULL; +#endif + } + + if (mode->vmode != FB_VMODE_NONINTERLACED) { + printf("Only non-interlaced modes supported, falling back to 1024x768\n"); + mode = &res_mode_init[RES_MODE_1024x768]; + } else { + printf("Setting up a %dx%d %s console\n", mode->xres, + mode->yres, sunxi_get_mon_desc(sunxi_display.monitor)); + } + + sunxi_engines_init(); + sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE); + + /* + * These are the only members of this structure that are used. All the + * others are driver specific. There is nothing to decribe pitch or + * stride, but we are lucky with our hw. + */ + graphic_device->frameAdrs = gd->fb_base; + graphic_device->gdfIndex = GDF_32BIT_X888RGB; + graphic_device->gdfBytesPP = 4; + graphic_device->winSizeX = mode->xres; + graphic_device->winSizeY = mode->yres; + + return graphic_device; +} + +/* + * Simplefb support. + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB) +int sunxi_simplefb_setup(void *blob) +{ + static GraphicDevice *graphic_device = &sunxi_display.graphic_device; + int offset, ret; + const char *pipeline = NULL; + +#ifdef CONFIG_MACH_SUN4I +#define PIPELINE_PREFIX "de_fe0-" +#else +#define PIPELINE_PREFIX +#endif + + switch (sunxi_display.monitor) { + case sunxi_monitor_none: + return 0; + case sunxi_monitor_dvi: + case sunxi_monitor_hdmi: + pipeline = PIPELINE_PREFIX "de_be0-lcd0-hdmi"; + break; + case sunxi_monitor_lcd: + pipeline = PIPELINE_PREFIX "de_be0-lcd0"; + break; + case sunxi_monitor_vga: +#ifdef CONFIG_VIDEO_VGA + pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0"; +#elif defined CONFIG_VIDEO_VGA_VIA_LCD + pipeline = PIPELINE_PREFIX "de_be0-lcd0"; +#endif + break; + } + + /* Find a prefilled simpefb node, matching out pipeline config */ + offset = fdt_node_offset_by_compatible(blob, -1, + "allwinner,simple-framebuffer"); + while (offset >= 0) { + ret = fdt_find_string(blob, offset, "allwinner,pipeline", + pipeline); + if (ret == 0) + break; + offset = fdt_node_offset_by_compatible(blob, offset, + "allwinner,simple-framebuffer"); + } + if (offset < 0) { + eprintf("Cannot setup simplefb: node not found\n"); + return 0; /* Keep older kernels working */ + } + + ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base, + graphic_device->winSizeX, graphic_device->winSizeY, + graphic_device->winSizeX * graphic_device->gdfBytesPP, + "x8r8g8b8"); + if (ret) + eprintf("Cannot setup simplefb: Error setting properties\n"); + + return ret; +} +#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */ diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index c047e6e785..b8f3431f24 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -149,14 +149,18 @@ static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config) FDT_LCD_CACHE_WRITE_BACK_FLUSH); /* These GPIOs are all optional */ - fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-enable-gpios", - &config->backlight_en); - fdtdec_decode_gpio(blob, display_node, "nvidia,lvds-shutdown-gpios", - &config->lvds_shutdown); - fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-vdd-gpios", - &config->backlight_vdd); - fdtdec_decode_gpio(blob, display_node, "nvidia,panel-vdd-gpios", - &config->panel_vdd); + gpio_request_by_name_nodev(blob, display_node, + "nvidia,backlight-enable-gpios", 0, + &config->backlight_en, GPIOD_IS_OUT); + gpio_request_by_name_nodev(blob, display_node, + "nvidia,lvds-shutdown-gpios", 0, + &config->lvds_shutdown, GPIOD_IS_OUT); + gpio_request_by_name_nodev(blob, display_node, + "nvidia,backlight-vdd-gpios", 0, + &config->backlight_vdd, GPIOD_IS_OUT); + gpio_request_by_name_nodev(blob, display_node, + "nvidia,panel-vdd-gpios", 0, + &config->panel_vdd, GPIOD_IS_OUT); return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings", config->panel_timings, FDT_LCD_TIMINGS); @@ -196,47 +200,29 @@ static int handle_stage(const void *blob) */ funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); - - fdtdec_setup_gpio(&config.panel_vdd); - fdtdec_setup_gpio(&config.lvds_shutdown); - fdtdec_setup_gpio(&config.backlight_vdd); - fdtdec_setup_gpio(&config.backlight_en); - - /* - * TODO: If fdt includes output flag we can omit this code - * since fdtdec_setup_gpio will do it for us. - */ - if (fdt_gpio_isvalid(&config.panel_vdd)) - gpio_direction_output(config.panel_vdd.gpio, 0); - if (fdt_gpio_isvalid(&config.lvds_shutdown)) - gpio_direction_output(config.lvds_shutdown.gpio, 0); - if (fdt_gpio_isvalid(&config.backlight_vdd)) - gpio_direction_output(config.backlight_vdd.gpio, 0); - if (fdt_gpio_isvalid(&config.backlight_en)) - gpio_direction_output(config.backlight_en.gpio, 0); break; case STAGE_PANEL_VDD: - if (fdt_gpio_isvalid(&config.panel_vdd)) - gpio_direction_output(config.panel_vdd.gpio, 1); + if (dm_gpio_is_valid(&config.panel_vdd)) + dm_gpio_set_value(&config.panel_vdd, 1); break; case STAGE_LVDS: - if (fdt_gpio_isvalid(&config.lvds_shutdown)) - gpio_set_value(config.lvds_shutdown.gpio, 1); + if (dm_gpio_is_valid(&config.lvds_shutdown)) + dm_gpio_set_value(&config.lvds_shutdown, 1); break; case STAGE_BACKLIGHT_VDD: - if (fdt_gpio_isvalid(&config.backlight_vdd)) - gpio_set_value(config.backlight_vdd.gpio, 1); + if (dm_gpio_is_valid(&config.backlight_vdd)) + dm_gpio_set_value(&config.backlight_vdd, 1); break; case STAGE_PWM: /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */ - pinmux_set_func(PINGRP_GPU, PMUX_FUNC_PWM); - pinmux_tristate_disable(PINGRP_GPU); + pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_GPU); pwm_enable(config.pwm_channel, 32768, 0xdf, 1); break; case STAGE_BACKLIGHT_EN: - if (fdt_gpio_isvalid(&config.backlight_en)) - gpio_set_value(config.backlight_en.gpio, 1); + if (dm_gpio_is_valid(&config.backlight_en)) + dm_gpio_set_value(&config.backlight_en, 1); break; case STAGE_DONE: break; diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c new file mode 100644 index 0000000000..3dacafd6bf --- /dev/null +++ b/drivers/video/vesa_fb.c @@ -0,0 +1,64 @@ +/* + * + * Vesa frame buffer driver for x86 + * + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +/* Devices to allow - only the last one works fully */ +struct pci_device_id vesa_video_ids[] = { + { .vendor = 0x102b, .device = 0x0525 }, + { .vendor = 0x1002, .device = 0x5159 }, + { .vendor = 0x1002, .device = 0x4752 }, + { .vendor = 0x1002, .device = 0x5452 }, + {}, +}; + +void *video_hw_init(void) +{ + GraphicDevice *gdev = &ctfb; + int bits_per_pixel; + pci_dev_t dev; + int ret; + + printf("Video: "); + if (vbe_get_video_info(gdev)) { + /* TODO: Should we look these up by class? */ + dev = pci_find_devices(vesa_video_ids, 0); + if (dev == -1) { + printf("no card detected\n"); + return NULL; + } + printf("bdf %x\n", dev); + ret = pci_run_vga_bios(dev, NULL, true); + if (ret) { + printf("failed to run video BIOS: %d\n", ret); + return NULL; + } + } + + if (vbe_get_video_info(gdev)) { + printf("No video mode configured\n"); + return NULL; + } + + bits_per_pixel = gdev->gdfBytesPP * 8; + sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, + bits_per_pixel); + printf("%s\n", gdev->modeIdent); + debug("Framex buffer at %x\n", gdev->pciBase); + + return (void *)gdev; +} diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c index d459ef07e9..cf71ad120e 100644 --- a/drivers/video/videomodes.c +++ b/drivers/video/videomodes.c @@ -3,7 +3,7 @@ * Pierre Aubert, Staubli Faverges , * Copyright 2011 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -58,6 +58,8 @@ ****************************************************************************/ #include +#include +#include #include #include "videomodes.h" @@ -84,13 +86,26 @@ const struct ctfb_vesa_modes vesa_modes[VESA_MODES_COUNT] = { {0x31B, RES_MODE_1280x1024, 24}, }; const struct ctfb_res_modes res_mode_init[RES_MODES_COUNT] = { - /* x y pixclk le ri up lo hs vs s vmode */ - {640, 480, 39721, 40, 24, 32, 11, 96, 2, 0, FB_VMODE_NONINTERLACED}, - {800, 600, 27778, 64, 24, 22, 1, 72, 2, 0, FB_VMODE_NONINTERLACED}, - {1024, 768, 15384, 168, 8, 29, 3, 144, 4, 0, FB_VMODE_NONINTERLACED}, - {960, 720, 13100, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED}, - {1152, 864, 12004, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED}, - {1280, 1024, 9090, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED}, + /* x y hz pixclk ps/kHz le ri up lo hs vs s vmode */ +#ifndef CONFIG_VIDEO_STD_TIMINGS + { 640, 480, 60, 39721, 25180, 40, 24, 32, 11, 96, 2, 0, FB_VMODE_NONINTERLACED}, + { 800, 600, 60, 27778, 36000, 64, 24, 22, 1, 72, 2, 0, FB_VMODE_NONINTERLACED}, + {1024, 768, 60, 15384, 65000, 168, 8, 29, 3, 144, 4, 0, FB_VMODE_NONINTERLACED}, + { 960, 720, 80, 13100, 76335, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED}, + {1152, 864, 60, 12004, 83300, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED}, + {1280, 1024, 60, 9090, 110000, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED}, +#else + { 640, 480, 60, 39683, 25200, 48, 16, 33, 10, 96, 2, 0, FB_VMODE_NONINTERLACED}, + { 800, 600, 60, 25000, 40000, 88, 40, 23, 1, 128, 4, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED}, + {1024, 768, 60, 15384, 65000, 160, 24, 29, 3, 136, 6, 0, FB_VMODE_NONINTERLACED}, + { 960, 720, 75, 13468, 74250, 176, 72, 27, 1, 112, 2, 0, FB_VMODE_NONINTERLACED}, + {1152, 864, 75, 9259, 108000, 256, 64, 32, 1, 128, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED}, + {1280, 1024, 60, 9259, 108000, 248, 48, 38, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED}, +#endif + {1280, 720, 60, 13468, 74250, 220, 110, 20, 5, 40, 5, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED}, + {1360, 768, 60, 11696, 85500, 256, 64, 17, 3, 112, 7, 0, FB_VMODE_NONINTERLACED}, + {1920, 1080, 60, 6734, 148500, 148, 88, 36, 4, 44, 5, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED}, + {1920, 1200, 60, 6494, 154000, 80, 48, 26, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED}, }; /************************************************************************ @@ -100,7 +115,7 @@ const struct ctfb_res_modes res_mode_init[RES_MODES_COUNT] = { * returns the length to the next seperator */ static int -video_get_param_len (char *start, char sep) +video_get_param_len(const char *start, char sep) { int i = 0; while ((*start != 0) && (*start != sep)) { @@ -183,6 +198,7 @@ int video_get_params (struct ctfb_res_modes *pPar, char *penv) while ((i = video_get_param_len (p, ',')) != 0) { GET_OPTION ("x:", pPar->xres) GET_OPTION ("y:", pPar->yres) + GET_OPTION ("refresh:", pPar->refresh) GET_OPTION ("le:", pPar->left_margin) GET_OPTION ("ri:", pPar->right_margin) GET_OPTION ("up:", pPar->upper_margin) @@ -192,6 +208,7 @@ int video_get_params (struct ctfb_res_modes *pPar, char *penv) GET_OPTION ("sync:", pPar->sync) GET_OPTION ("vmode:", pPar->vmode) GET_OPTION ("pclk:", pPar->pixclock) + GET_OPTION ("pclk_khz:", pPar->pixclock_khz) GET_OPTION ("depth:", bpp) p += i; if (*p != 0) @@ -260,3 +277,171 @@ int video_get_video_mode(unsigned int *xres, unsigned int *yres, return 1; } + +/* + * Parse the 'video-mode' environment variable using video_get_video_mode() + * and lookup the matching ctfb_res_modes in res_mode_init. + * + * @default_mode: RES_MODE_##x## define for the mode to store in mode_ret + * when 'video-mode' is not set or does not contain a valid mode + * @default_depth: depth to set when 'video-mode' is not set + * @mode_ret: pointer where the mode will be stored + * @depth_ret: pointer where the depth will be stored + * @options: pointer to any remaining options, or NULL + */ +void video_get_ctfb_res_modes(int default_mode, unsigned int default_depth, + const struct ctfb_res_modes **mode_ret, + unsigned int *depth_ret, + const char **options) +{ + unsigned int i, xres, yres, depth, refresh; + + *mode_ret = &res_mode_init[default_mode]; + *depth_ret = default_depth; + *options = NULL; + + if (!video_get_video_mode(&xres, &yres, &depth, &refresh, options)) + return; + + for (i = 0; i < RES_MODES_COUNT; i++) { + if (res_mode_init[i].xres == xres && + res_mode_init[i].yres == yres && + res_mode_init[i].refresh == refresh) { + *mode_ret = &res_mode_init[i]; + *depth_ret = depth; + return; + } + } + + printf("video-mode %dx%d-%d@%d not available, falling back to %dx%d-%d@%d\n", + xres, yres, depth, refresh, (*mode_ret)->xres, + (*mode_ret)->yres, *depth_ret, (*mode_ret)->refresh); +} + +/* + * Find the named string option within the ',' separated options string, and + * store its value in dest. + * + * @options: ',' separated options string + * @name: name of the option to look for + * @dest: destination buffer to store the value of the option in + * @dest_len: length of dest + * @def: value to store in dest if the option is not present in options + */ +void video_get_option_string(const char *options, const char *name, + char *dest, int dest_len, const char *def) +{ + const char *p = options; + const int name_len = strlen(name); + int i, len; + + while (p && (i = video_get_param_len(p, ',')) != 0) { + if (strncmp(p, name, name_len) == 0 && p[name_len] == '=') { + len = i - (name_len + 1); + if (len >= dest_len) + len = dest_len - 1; + memcpy(dest, &p[name_len + 1], len); + dest[len] = 0; + return; + } + p += i; + if (*p != 0) + p++; /* skip ',' */ + } + strcpy(dest, def); +} + +/* + * Find the named integer option within the ',' separated options string, and + * return its value. + * + * @options: ',' separated options string + * @name: name of the option to look for + * @def: value to return if the option is not present in options + */ +int video_get_option_int(const char *options, const char *name, int def) +{ + const char *p = options; + const int name_len = strlen(name); + int i; + + while (p && (i = video_get_param_len(p, ',')) != 0) { + if (strncmp(p, name, name_len) == 0 && p[name_len] == '=') + return simple_strtoul(&p[name_len + 1], NULL, 10); + + p += i; + if (*p != 0) + p++; /* skip ',' */ + } + return def; +} + +/** + * Convert an EDID detailed timing to a struct ctfb_res_modes + * + * @param t The EDID detailed timing to be converted + * @param mode Returns the converted timing + * + * @return 0 on success, or a negative errno on error + */ +int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t, + struct ctfb_res_modes *mode) +{ + int margin, h_total, v_total; + + /* Check all timings are non 0 */ + if (EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) == 0 || + EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*t) == 0 || + EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*t) == 0 || + EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*t) == 0 || + EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 || + EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 || + EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*t) == 0 || + EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 || + EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*t) == 0 || + /* 3d formats are not supported*/ + EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0) + return -EINVAL; + + mode->xres = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*t); + mode->yres = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*t); + + h_total = mode->xres + EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*t); + v_total = mode->yres + EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t); + mode->refresh = EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) / + (h_total * v_total); + + mode->pixclock_khz = EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) / 1000; + mode->pixclock = 1000000000L / mode->pixclock_khz; + + mode->right_margin = EDID_DETAILED_TIMING_HSYNC_OFFSET(*t); + mode->hsync_len = EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*t); + margin = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*t) - + (mode->right_margin + mode->hsync_len); + if (margin <= 0) + return -EINVAL; + + mode->left_margin = margin; + + mode->lower_margin = EDID_DETAILED_TIMING_VSYNC_OFFSET(*t); + mode->vsync_len = EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*t); + margin = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) - + (mode->lower_margin + mode->vsync_len); + if (margin <= 0) + return -EINVAL; + + mode->upper_margin = margin; + + mode->sync = 0; + if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) + mode->sync |= FB_SYNC_HOR_HIGH_ACT; + if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) + mode->sync |= FB_SYNC_VERT_HIGH_ACT; + + if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) + mode->vmode = FB_VMODE_INTERLACED; + else + mode->vmode = FB_VMODE_NONINTERLACED; + + return 0; +} diff --git a/drivers/video/videomodes.h b/drivers/video/videomodes.h index 9fbe50b0f8..82190a2aec 100644 --- a/drivers/video/videomodes.h +++ b/drivers/video/videomodes.h @@ -2,9 +2,10 @@ * (C) Copyright 2004 * Pierre Aubert, Staubli Faverges , * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ +#include #ifndef CONFIG_SYS_DEFAULT_VIDEO_MODE #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x301 @@ -35,8 +36,10 @@ struct ctfb_res_modes { int xres; /* visible resolution */ int yres; + int refresh; /* vertical refresh rate in hz */ /* Timing: All values in pixclocks, except pixclock (of course) */ int pixclock; /* pixel clock in ps (pico seconds) */ + int pixclock_khz; /* pixel clock in kHz */ int left_margin; /* time from sync to picture */ int right_margin; /* time from picture to sync */ int upper_margin; /* time from sync to picture */ @@ -62,7 +65,11 @@ struct ctfb_vesa_modes { #define RES_MODE_960_720 3 #define RES_MODE_1152x864 4 #define RES_MODE_1280x1024 5 -#define RES_MODES_COUNT 6 +#define RES_MODE_1280x720 6 +#define RES_MODE_1360x768 7 +#define RES_MODE_1920x1080 8 +#define RES_MODE_1920x1200 9 +#define RES_MODES_COUNT 10 #define VESA_MODES_COUNT 19 @@ -73,3 +80,16 @@ int video_get_params (struct ctfb_res_modes *pPar, char *penv); int video_get_video_mode(unsigned int *xres, unsigned int *yres, unsigned int *depth, unsigned int *freq, const char **options); + +void video_get_ctfb_res_modes(int default_mode, unsigned int default_depth, + const struct ctfb_res_modes **mode_ret, + unsigned int *depth_ret, + const char **options); + +void video_get_option_string(const char *options, const char *name, + char *dest, int dest_len, const char *def); + +int video_get_option_int(const char *options, const char *name, int def); + +int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t, + struct ctfb_res_modes *mode); diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig new file mode 100644 index 0000000000..83bdddc28d --- /dev/null +++ b/drivers/watchdog/Kconfig @@ -0,0 +1,7 @@ +config HW_WATCHDOG + bool "Generic SoC specific watchdog support" + depends on !SOC_MX6 + +config IMX_WATCHDOG + bool "Freescale i.MX watchdog support" + depends on SOC_MX31 || SOC_MX35 || SOC_MX5 || SOC_MX6 || SOC_VF610 || SOC_LS102XA diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 7e255ce8ae..efad1432d6 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -5,34 +5,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB := $(obj)libwatchdog.o - -COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o -COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610)) -COBJS-y += imx_watchdog.o -endif -COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o -COBJS-$(CONFIG_S5P) += s5p_wdt.o -COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o -COBJS-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o +obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o +obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o +obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o +obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o +obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o +obj-$(CONFIG_S5P) += s5p_wdt.o +obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o +obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 7a6756b2e5..6a8db59fdf 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -9,6 +9,7 @@ #include #include #include +#include #include void hw_watchdog_reset(void) diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c new file mode 100644 index 0000000000..e788e1b65d --- /dev/null +++ b/drivers/watchdog/designware_wdt.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define DW_WDT_CR 0x00 +#define DW_WDT_TORR 0x04 +#define DW_WDT_CRR 0x0C + +#define DW_WDT_CR_EN_OFFSET 0x00 +#define DW_WDT_CR_RMOD_OFFSET 0x01 +#define DW_WDT_CR_RMOD_VAL 0x00 +#define DW_WDT_CRR_RESTART_VAL 0x76 + +/* + * Set the watchdog time interval. + * Counter is 32 bit. + */ +static int designware_wdt_settimeout(unsigned int timeout) +{ + signed int i; + + /* calculate the timeout range value */ + i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16; + if (i > 15) + i = 15; + if (i < 0) + i = 0; + + writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR)); + return 0; +} + +static void designware_wdt_enable(void) +{ + writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | + (0x1 << DW_WDT_CR_EN_OFFSET)), + (CONFIG_DW_WDT_BASE + DW_WDT_CR)); +} + +static unsigned int designware_wdt_is_enabled(void) +{ + unsigned long val; + val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR)); + return val & 0x1; +} + +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + if (designware_wdt_is_enabled()) + /* restart the watchdog counter */ + writel(DW_WDT_CRR_RESTART_VAL, + (CONFIG_DW_WDT_BASE + DW_WDT_CRR)); +} + +void hw_watchdog_init(void) +{ + /* reset to disable the watchdog */ + hw_watchdog_reset(); + /* set timer in miliseconds */ + designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS); + /* enable the watchdog */ + designware_wdt_enable(); + /* reset the watchdog */ + hw_watchdog_reset(); +} +#endif diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index ee53a58251..3f6e5593ed 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -19,6 +19,7 @@ struct watchdog_regs { #define WCR_WDBG 0x02 #define WCR_WDE 0x04 /* WDOG enable */ #define WCR_WDT 0x08 +#define WCR_SRS 0x10 #define WCR_WDW 0x80 #define SET_WCR_WT(x) (x << 8) @@ -45,7 +46,7 @@ void hw_watchdog_init(void) #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; - writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | + writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); hw_watchdog_reset(); } diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c new file mode 100644 index 0000000000..7ea4b604cd --- /dev/null +++ b/drivers/watchdog/omap_wdt.c @@ -0,0 +1,121 @@ +/* + * omap_wdt.c + * + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * SPDX-License-Identifier: GPL-2.0 + * + * Based on: + * + * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog + * + * commit 2d991a164a61858012651e13c59521975504e260 + * Author: Bill Pemberton + * Date: Mon Nov 19 13:21:41 2012 -0500 + * + * watchdog: remove use of __devinit + * + * CONFIG_HOTPLUG is going away as an option so __devinit is no longer + * needed. + * + * Author: MontaVista Software, Inc. + * or + * + * History: + * + * 20030527: George G. Davis + * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c + * (c) Copyright 2000 Oleg Drokin + * Based on SoftDog driver by Alan Cox + * + * Copyright (c) 2004 Texas Instruments. + * 1. Modified to support OMAP1610 32-KHz watchdog timer + * 2. Ported to 2.6 kernel + * + * Copyright (c) 2005 David Brownell + * Use the driver model and standard identifiers; handle bigger timeouts. + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware timeout in seconds */ +#define WDT_HW_TIMEOUT 60 + +static unsigned int wdt_trgr_pattern = 0x1234; + +void hw_watchdog_reset(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* wait for posted write to complete */ + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) + ; + + wdt_trgr_pattern = ~wdt_trgr_pattern; + writel(wdt_trgr_pattern, &wdt->wdtwtgr); + + /* wait for posted write to complete */ + while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR)) + ; +} + +static int omap_wdt_set_timeout(unsigned int timeout) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + u32 pre_margin = GET_WLDR_VAL(timeout); + + /* just count up at 32 KHz */ + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) + ; + + writel(pre_margin, &wdt->wdtwldr); + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) + ; + + return 0; +} + +void hw_watchdog_init(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* initialize prescaler */ + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) + ; + + writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr); + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) + ; + + omap_wdt_set_timeout(WDT_HW_TIMEOUT); + + /* Sequence to enable the watchdog */ + writel(0xBBBB, &wdt->wdtwspr); + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) + ; + + writel(0x4444, &wdt->wdtwspr); + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) + ; +} + +void hw_watchdog_disable(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* + * Disable watchdog + */ + writel(0xAAAA, &wdt->wdtwspr); + while (readl(&wdt->wdtwwps) != 0x0) + ; + writel(0x5555, &wdt->wdtwspr); + while (readl(&wdt->wdtwwps) != 0x0) + ; +} diff --git a/drivers/watchdog/s5p_wdt.c b/drivers/watchdog/s5p_wdt.c index b3b5834bb6..a6e54d9f77 100644 --- a/drivers/watchdog/s5p_wdt.c +++ b/drivers/watchdog/s5p_wdt.c @@ -2,7 +2,7 @@ * Copyright (C) 2012 Samsung Electronics * Minkyu Kang * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c index 4e46e4cef7..6336c94883 100644 --- a/drivers/watchdog/xilinx_tb_wdt.c +++ b/drivers/watchdog/xilinx_tb_wdt.c @@ -54,7 +54,7 @@ static void hw_watchdog_isr(void *arg) hw_watchdog_reset(); } -int hw_watchdog_init(void) +void hw_watchdog_init(void) { int ret; @@ -65,7 +65,5 @@ int hw_watchdog_init(void) ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ, hw_watchdog_isr, NULL); if (ret) - return 1; - - return 0; + puts("Watchdog IRQ registration failed."); } diff --git a/dts/.gitignore b/dts/.gitignore new file mode 100644 index 0000000000..1b3718065c --- /dev/null +++ b/dts/.gitignore @@ -0,0 +1,2 @@ +*.dtb +*.dtb.S diff --git a/dts/Kconfig b/dts/Kconfig new file mode 100644 index 0000000000..3a180d5b6f --- /dev/null +++ b/dts/Kconfig @@ -0,0 +1,59 @@ +# +# Device Tree Control +# +# TODO: +# This feature is not currently supported for SPL, +# but this restriction should be removed in the future. + +config SUPPORT_OF_CONTROL + bool + +menu "Device Tree Control" + depends on !SPL_BUILD + depends on SUPPORT_OF_CONTROL + +config OF_CONTROL + bool "Run-time configuration via Device Tree" + help + This feature provides for run-time configuration of U-Boot + via a flattened device tree. + +choice + prompt "Provider of DTB for DT control" + depends on OF_CONTROL + +config OF_SEPARATE + bool "Separate DTB for DT control" + depends on !SANDBOX + help + If this option is enabled, the device tree will be built and + placed as a separate u-boot.dtb file alongside the U-Boot image. + +config OF_EMBED + bool "Embedded DTB for DT control" + help + If this option is enabled, the device tree will be picked up and + built into the U-Boot image. + +config OF_HOSTFILE + bool "Host filed DTB for DT control" + depends on SANDBOX + help + If this option is enabled, DTB will be read from a file on startup. + This is only useful for Sandbox. Use the -d flag to U-Boot to + specify the file to read. + +endchoice + +config DEFAULT_DEVICE_TREE + string "Default Device Tree for DT control" + help + This option specifies the default Device Tree used for DT control. + It can be overridden from the command line: + $ make DEVICE_TREE= + +config FDT_FIXUP_PARTITIONS + bool + depends on MTD_PARTITIONS && OF_LIBFDT + +endmenu diff --git a/dts/Makefile b/dts/Makefile index f106317850..d3122aa3b9 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -7,86 +7,42 @@ # This Makefile builds the internal U-Boot fdt if CONFIG_OF_CONTROL is # enabled. See doc/README.fdt-control for more details. -include $(TOPDIR)/config.mk - -LIB = $(obj)libdts.o - +DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%) ifeq ($(DEVICE_TREE),) -$(if $(CONFIG_DEFAULT_DEVICE_TREE),,\ -$(error Please define CONFIG_DEFAULT_DEVICE_TREE in your board header file)) -DEVICE_TREE = $(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE)) +DEVICE_TREE := unset endif -DTS_INCDIRS = $(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts -DTS_INCDIRS += $(SRCTREE)/board/$(VENDOR)/dts -DTS_INCDIRS += $(SRCTREE)/arch/$(ARCH)/dts - -DTS_CPPFLAGS := -x assembler-with-cpp -undef -D__DTS__ \ - -nostdinc $(addprefix -I,$(DTS_INCDIRS)) - -DTC_FLAGS := -R 4 -p 0x1000 \ - $(addprefix -i ,$(DTS_INCDIRS)) - -all: $(obj).depend $(LIB) - -# Use a constant name for this so we can access it from C code. -# objcopy doesn't seem to allow us to set the symbol name independently of -# the filename. -DT_BIN := $(obj)dt.dtb - -$(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts - $(CPP) $(DTS_CPPFLAGS) $< -o $(DT_BIN).dts.tmp - $(DTC) $(DTC_FLAGS) -O dtb -o ${DT_BIN} $(DT_BIN).dts.tmp - -process_lds = \ - $(1) | sed -r -n 's/^OUTPUT_$(2)[ ("]*([^")]*).*/\1/p' - -# Run the compiler and get the link script from the linker -GET_LDS = $(CC) $(CFLAGS) $(LDFLAGS) -Wl,--verbose 2>&1 - -$(obj)dt.o: $(DT_BIN) - # We want the output format and arch. - # We also hope to win a prize for ugliest Makefile / shell interaction - # We look in the LDSCRIPT first. - # Then try the linker which should give us the answer. - # Then check it worked. - [ -n "$(LDSCRIPT)" ] && \ - oformat=`$(call process_lds,cat $(LDSCRIPT),FORMAT)` && \ - oarch=`$(call process_lds,cat $(LDSCRIPT),ARCH)` ;\ - \ - [ -z "$${oformat}" ] && \ - oformat=`$(call process_lds,$(GET_LDS),FORMAT)` ;\ - [ -z "$${oarch}" ] && \ - oarch=`$(call process_lds,$(GET_LDS),ARCH)` ;\ - \ - [ -z "$${oformat}" ] && \ - echo "Cannot read OUTPUT_FORMAT from lds file $(LDSCRIPT)" && \ - exit 1 || true ;\ - [ -z "$${oarch}" ] && \ - echo "Cannot read OUTPUT_ARCH from lds file $(LDSCRIPT)" && \ - exit 1 || true ;\ - \ - cd $(dir ${DT_BIN}) && \ - $(OBJCOPY) -I binary -O $${oformat} -B $${oarch} \ - $(notdir ${DT_BIN}) $@ - rm $(DT_BIN) +ifneq ($(EXT_DTB),) +DTB := $(EXT_DTB) +else +DTB := arch/$(ARCH)/dts/$(DEVICE_TREE).dtb +endif -OBJS-$(CONFIG_OF_EMBED) := dt.o +$(obj)/dt.dtb: $(DTB) FORCE + $(call if_changed,shipped) -COBJS := $(OBJS-y) +targets += dt.dtb -OBJS := $(addprefix $(obj),$(COBJS)) +$(DTB): arch-dtbs + $(Q)test -e $@ || ( \ + echo >&2; \ + echo >&2 "Device Tree Source is not correctly specified."; \ + echo >&2 "Please define 'CONFIG_DEFAULT_DEVICE_TREE'"; \ + echo >&2 "or build with 'DEVICE_TREE=' argument"; \ + echo >&2; \ + /bin/false) -binary: $(DT_BIN) +arch-dtbs: + $(Q)$(MAKE) $(build)=arch/$(ARCH)/dts dtbs -$(LIB): $(OBJS) $(DTB) - $(call cmd_link_o_target, $(OBJS)) +.SECONDARY: $(obj)/dt.dtb.S -######################################################################### +obj-$(CONFIG_OF_EMBED) := dt.dtb.o -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +dtbs: $(obj)/dt.dtb + @: -sinclude $(obj).depend +clean-files := dt.dtb.S -######################################################################### +# Let clean descend into dts directories +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts diff --git a/examples/Makefile b/examples/Makefile new file mode 100644 index 0000000000..18d008e7b5 --- /dev/null +++ b/examples/Makefile @@ -0,0 +1,9 @@ +ifndef CONFIG_SANDBOX + +ifdef FTRACE +subdir-ccflags-y += -finstrument-functions -DFTRACE +endif + +subdir-y += standalone +subdir-$(CONFIG_API) += api +endif diff --git a/examples/api/Makefile b/examples/api/Makefile index 4d683400e1..6cf23d10ac 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -11,64 +11,47 @@ ifeq ($(ARCH),arm) LOAD_ADDR = 0x1000000 endif -include $(TOPDIR)/config.mk - # Resulting ELF and binary exectuables will be named demo and demo.bin -OUTPUT-$(CONFIG_API) = $(obj)demo -OUTPUT = $(OUTPUT-y) +extra-y = demo # Source files located in the examples/api directory -SOBJ_FILES-$(CONFIG_API) += crt0.o -COBJ_FILES-$(CONFIG_API) += demo.o -COBJ_FILES-$(CONFIG_API) += glue.o -COBJ_FILES-$(CONFIG_API) += libgenwrap.o +OBJ-y += crt0.o +OBJ-y += demo.o +OBJ-y += glue.o +OBJ-y += libgenwrap.o # Source files which exist outside the examples/api directory -EXT_COBJ_FILES-$(CONFIG_API) += lib/crc32.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/ctype.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/div64.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/string.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/time.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/vsprintf.o -ifeq ($(ARCH),powerpc) -EXT_SOBJ_FILES-$(CONFIG_API) += arch/powerpc/lib/ppcstring.o -endif - -# Create a list of source files so their dependencies can be auto-generated -SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/,$(EXT_SOBJ_FILES-y:.o=.S)) -SRCS += $(addprefix $(SRCTREE)/examples/api/,$(COBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/examples/api/,$(SOBJ_FILES-y:.o=.S)) +EXT_COBJ-y += lib/crc32.o +EXT_COBJ-y += lib/ctype.o +EXT_COBJ-y += lib/div64.o +EXT_COBJ-y += lib/string.o +EXT_COBJ-y += lib/time.o +EXT_COBJ-y += lib/vsprintf.o +EXT_SOBJ-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o # Create a list of object files to be compiled -OBJS += $(addprefix $(obj),$(SOBJ_FILES-y)) -OBJS += $(addprefix $(obj),$(COBJ_FILES-y)) -OBJS += $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y))) -OBJS += $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y))) +OBJS := $(OBJ-y) $(notdir $(EXT_COBJ-y) $(EXT_SOBJ-y)) +targets += $(OBJS) +OBJS := $(addprefix $(obj)/,$(OBJS)) -CPPFLAGS += -I.. +######################################################################### -all: $(obj).depend $(OUTPUT) +quiet_cmd_link_demo = LD $@ +cmd_link_demo = $(LD) --gc-sections -Ttext $(LOAD_ADDR) -o $@ $(filter-out $(PHONY), $^) $(PLATFORM_LIBS) -######################################################################### +$(obj)/demo: $(OBJS) FORCE + $(call if_changed,link_demo) -$(OUTPUT): $(OBJS) - $(LD) -Ttext $(LOAD_ADDR) -o $@ $^ $(PLATFORM_LIBS) - $(OBJCOPY) -O binary $@ $(OUTPUT).bin 2>/dev/null +# demo.bin is never genrated. Is this necessary? +OBJCOPYFLAGS_demo.bin := -O binary +$(obj)/demo.bin: $(obj)/demo FORCE + $(call if_changed,objcopy) # Rule to build generic library C files -$(obj)%.o: $(SRCTREE)/lib/%.c - $(CC) -g $(CFLAGS) -c -o $@ $< +$(addprefix $(obj)/,$(notdir $(EXT_COBJ-y))): $(obj)/%.o: lib/%.c FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) # Rule to build architecture-specific library assembly files -$(obj)%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S - $(CC) -g $(CFLAGS) -c -o $@ $< - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +$(addprefix $(obj)/,$(notdir $(EXT_SOBJ-y))): $(obj)/%.o: arch/powerpc/lib/%.S FORCE + $(call if_changed_dep,as_o_S) diff --git a/examples/standalone/.gitignore b/examples/standalone/.gitignore index 4d9ce66402..6d3a6166d2 100644 --- a/examples/standalone/.gitignore +++ b/examples/standalone/.gitignore @@ -1,6 +1,4 @@ -/82559_eeprom /atmel_df_pow2 -/eepro100_eeprom /hello_world /interrupt /mem_to_mem_idma2intr diff --git a/examples/standalone/82559_eeprom.c b/examples/standalone/82559_eeprom.c deleted file mode 100644 index 8dd7079ae7..0000000000 --- a/examples/standalone/82559_eeprom.c +++ /dev/null @@ -1,357 +0,0 @@ - -/* - * Copyright 1998-2001 by Donald Becker. - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL), incorporated herein by reference. - * Contact the author for use under other terms. - * - * This program must be compiled with "-O"! - * See the bottom of this file for the suggested compile-command. - * - * The author may be reached as becker@scyld.com, or C/O - * Scyld Computing Corporation - * 410 Severn Ave., Suite 210 - * Annapolis MD 21403 - * - * Common-sense licensing statement: Using any portion of this program in - * your own program means that you must give credit to the original author - * and release the resulting code under the GPL. - */ - -#define _PPC_STRING_H_ /* avoid unnecessary str/mem functions */ - -#include -#include -#include - - -/* Default EEPROM for i82559 */ -static unsigned short default_eeprom[64] = { - 0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff -}; - -static unsigned short eeprom[256]; - -static int eeprom_size = 64; -static int eeprom_addr_size = 6; - -static int debug = 0; - -static inline unsigned short swap16(unsigned short x) -{ - return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); -} - - -void * memcpy(void * dest,const void *src,size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} - - -/* The EEPROM commands include the alway-set leading bit. */ -#define EE_WRITE_CMD (5) -#define EE_READ_CMD (6) -#define EE_ERASE_CMD (7) - -/* Serial EEPROM section. */ -#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ -#define EE_CS 0x02 /* EEPROM chip select. */ -#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ -#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ -#define EE_ENB (0x4800 | EE_CS) -#define EE_WRITE_0 0x4802 -#define EE_WRITE_1 0x4806 -#define EE_OFFSET 14 - -/* Delay between EEPROM clock transitions. */ -#define eeprom_delay(ee_addr) inw(ee_addr) - -/* Wait for the EEPROM to finish the previous operation. */ -static int eeprom_busy_poll(long ee_ioaddr) -{ - int i; - outw(EE_ENB, ee_ioaddr); - for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ - if (inw(ee_ioaddr) & EE_DATA_READ) - break; - return i; -} - -/* This executes a generic EEPROM command, typically a write or write enable. - It returns the data output from the EEPROM, and thus may also be used for - reads. */ -static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len) -{ - unsigned retval = 0; - long ee_addr = ioaddr + EE_OFFSET; - - if (debug > 1) - printf(" EEPROM op 0x%x: ", cmd); - - outw(EE_ENB | EE_SHIFT_CLK, ee_addr); - - /* Shift the command bits out. */ - do { - short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; - outw(dataval, ee_addr); - eeprom_delay(ee_addr); - if (debug > 2) - printf("%X", inw(ee_addr) & 15); - outw(dataval | EE_SHIFT_CLK, ee_addr); - eeprom_delay(ee_addr); - retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0); - } while (--cmd_len >= 0); -#if 0 - outw(EE_ENB, ee_addr); -#endif - /* Terminate the EEPROM access. */ - outw(EE_ENB & ~EE_CS, ee_addr); - if (debug > 1) - printf(" EEPROM result is 0x%5.5x.\n", retval); - return retval; -} - -static int read_eeprom(long ioaddr, int location, int addr_len) -{ - return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location) - << 16 , 3 + addr_len + 16) & 0xffff; -} - -static void write_eeprom(long ioaddr, int index, int value, int addr_len) -{ - long ee_ioaddr = ioaddr + EE_OFFSET; - int i; - - /* Poll for previous op finished. */ - eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */ - /* Enable programming modes. */ - do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len); - /* Do the actual write. */ - do_eeprom_cmd(ioaddr, - (((EE_WRITE_CMD</dev/null +$(LIB): $(LIBOBJS) FORCE + $(call if_changed,link_lib) -$(BIN): -$(obj)%.bin: $(obj)% - $(OBJCOPY) -O binary $< $@ 2>/dev/null +quiet_cmd_link_elf = LD $@ + cmd_link_elf = $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ + -o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) $(PLATFORM_LIBGCC) -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +$(ELF): $(obj)/%: $(obj)/%.o $(LIB) FORCE + $(call if_changed,link_elf) -sinclude $(obj).depend +$(obj)/%.srec: OBJCOPYFLAGS := -O srec +$(obj)/%.srec: $(obj)/% FORCE + $(call if_changed,objcopy) -######################################################################### +$(obj)/%.bin: OBJCOPYFLAGS := -O binary +$(obj)/%.bin: $(obj)/% FORCE + $(call if_changed,objcopy) diff --git a/examples/standalone/README.smc91111_eeprom b/examples/standalone/README.smc91111_eeprom index 28e7e69788..a2d52e7770 100644 --- a/examples/standalone/README.smc91111_eeprom +++ b/examples/standalone/README.smc91111_eeprom @@ -154,10 +154,10 @@ The MAC address can be stored in four locations: -Boot environmental variable in Flash <- can not change, without re-flashing U-boot. -U-Boot environental variable <- can not change, without +U-Boot environmental variable <- can not change, without resetting board/U-Boot -LAN91C111 Registers <- volitle -LAN91C111 EEPROM <- Non Volitle +LAN91C111 Registers <- volatile +LAN91C111 EEPROM <- Non-volatile If you have not activated the network, and do not have a hardcoded or pre-assigned MAC address in U-boot, the environmental variables diff --git a/examples/standalone/eepro100_eeprom.c b/examples/standalone/eepro100_eeprom.c deleted file mode 100644 index 3c7f380977..0000000000 --- a/examples/standalone/eepro100_eeprom.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 1998-2001 by Donald Becker. - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL), incorporated herein by reference. - * Contact the author for use under other terms. - * - * This program must be compiled with "-O"! - * See the bottom of this file for the suggested compile-command. - * - * The author may be reached as becker@scyld.com, or C/O - * Scyld Computing Corporation - * 410 Severn Ave., Suite 210 - * Annapolis MD 21403 - * - * Common-sense licensing statement: Using any portion of this program in - * your own program means that you must give credit to the original author - * and release the resulting code under the GPL. - */ - -/* avoid unnecessary memcpy function */ -#define _PPC_STRING_H_ - -#include -#include - -static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr); - -int eepro100_eeprom(int argc, char * const argv[]) -{ - int ret = 0; - - unsigned char hwaddr1[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x05 }; - unsigned char hwaddr2[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x06 }; - - app_startup(argv); - -#if defined(CONFIG_OXC) - ret |= reset_eeprom(0x80000000, hwaddr1); - ret |= reset_eeprom(0x81000000, hwaddr2); -#endif - - return ret; -} - -/* Default EEPROM for i82559 */ -static unsigned short default_eeprom[64] = { - 0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff -}; - -static unsigned short eeprom[256]; - -static int eeprom_size = 64; -static int eeprom_addr_size = 6; - -static int debug = 0; - -static inline unsigned short swap16(unsigned short x) -{ - return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); -} - -static inline void outw(short data, long addr) -{ - *(volatile short *)(addr) = swap16(data); -} - -static inline short inw(long addr) -{ - return swap16(*(volatile short *)(addr)); -} - -void *memcpy(void *dst, const void *src, unsigned int len) -{ - char *ret = dst; - while (len-- > 0) { - *ret++ = *((char *)src); - src++; - } - return (void *)ret; -} - -/* The EEPROM commands include the alway-set leading bit. */ -#define EE_WRITE_CMD (5) -#define EE_READ_CMD (6) -#define EE_ERASE_CMD (7) - -/* Serial EEPROM section. */ -#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ -#define EE_CS 0x02 /* EEPROM chip select. */ -#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ -#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ -#define EE_ENB (0x4800 | EE_CS) -#define EE_WRITE_0 0x4802 -#define EE_WRITE_1 0x4806 -#define EE_OFFSET 14 - -/* Delay between EEPROM clock transitions. */ -#define eeprom_delay(ee_addr) inw(ee_addr) - -/* Wait for the EEPROM to finish the previous operation. */ -static int eeprom_busy_poll(long ee_ioaddr) -{ - int i; - outw(EE_ENB, ee_ioaddr); - for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ - if (inw(ee_ioaddr) & EE_DATA_READ) - break; - return i; -} - -/* This executes a generic EEPROM command, typically a write or write enable. - It returns the data output from the EEPROM, and thus may also be used for - reads. */ -static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len) -{ - unsigned retval = 0; - long ee_addr = ioaddr + EE_OFFSET; - - if (debug > 1) - printf(" EEPROM op 0x%x: ", cmd); - - outw(EE_ENB | EE_SHIFT_CLK, ee_addr); - - /* Shift the command bits out. */ - do { - short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; - outw(dataval, ee_addr); - eeprom_delay(ee_addr); - if (debug > 2) - printf("%X", inw(ee_addr) & 15); - outw(dataval | EE_SHIFT_CLK, ee_addr); - eeprom_delay(ee_addr); - retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0); - } while (--cmd_len >= 0); -#if 0 - outw(EE_ENB, ee_addr); -#endif - /* Terminate the EEPROM access. */ - outw(EE_ENB & ~EE_CS, ee_addr); - if (debug > 1) - printf(" EEPROM result is 0x%5.5x.\n", retval); - return retval; -} - -static int read_eeprom(long ioaddr, int location, int addr_len) -{ - return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location) - << 16 , 3 + addr_len + 16) & 0xffff; -} - -static void write_eeprom(long ioaddr, int index, int value, int addr_len) -{ - long ee_ioaddr = ioaddr + EE_OFFSET; - int i; - - /* Poll for previous op finished. */ - eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */ - /* Enable programming modes. */ - do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len); - /* Do the actual write. */ - do_eeprom_cmd(ioaddr, - (((EE_WRITE_CMD< #include +#include -#ifndef GCC_VERSION -#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) -#endif /* GCC_VERSION */ +#define FO(x) offsetof(struct jt_funcs, x) #if defined(CONFIG_X86) /* @@ -13,23 +12,23 @@ * from flash memory. The global_data address is passed as argv[-1] * to the application program. */ -static void **jt; +static struct jt_funcs *jt; gd_t *global_data; -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " movl %0, %%eax\n" \ " movl jt, %%ecx\n" \ " jmp *(%%ecx, %%eax)\n" \ - : : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx"); + : : "i"(FO(x)) : "eax", "ecx"); #elif defined(CONFIG_PPC) /* * r2 holds the pointer to the global_data, r11 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ @@ -37,19 +36,34 @@ gd_t *global_data; " lwz %%r11, %1(%%r11)\n" \ " mtctr %%r11\n" \ " bctr\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r11"); #elif defined(CONFIG_ARM) +#ifdef CONFIG_ARM64 +/* + * x18 holds the pointer to the global_data, x9 is a call-clobbered + * register + */ +#define EXPORT_FUNC(f, a, x, ...) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" ldr x9, [x18, %0]\n" \ +" ldr x9, [x9, %1]\n" \ +" br x9\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "x9"); +#else /* - * r8 holds the pointer to the global_data, ip is a call-clobbered + * r9 holds the pointer to the global_data, ip is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ -" ldr ip, [r8, %0]\n" \ +" ldr ip, [r9, %0]\n" \ " ldr pc, [ip, %1]\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "ip"); +#endif #elif defined(CONFIG_MIPS) /* * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call- @@ -58,19 +72,19 @@ gd_t *global_data; * it; however, GCC/mips generates an additional `nop' after each asm * statement */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " lw $25, %0($26)\n" \ " lw $25, %1($25)\n" \ " jr $25\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "t9"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9"); #elif defined(CONFIG_NIOS2) /* * gp holds the pointer to the global_data, r8 is call-clobbered */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ @@ -80,13 +94,13 @@ gd_t *global_data; " ldw r8, 0(r8)\n" \ " ldw r8, %1(r8)\n" \ " jmp r8\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "gp"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "gp"); #elif defined(CONFIG_M68K) /* * d7 holds the pointer to the global_data, a0 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ @@ -96,50 +110,50 @@ gd_t *global_data; " adda.l %1, %%a0\n" \ " move.l (%%a0), %%a0\n" \ " jmp (%%a0)\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "a0"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "a0"); #elif defined(CONFIG_MICROBLAZE) /* * r31 holds the pointer to the global_data. r5 is a call-clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " lwi r5, r31, %0\n" \ " lwi r5, r5, %1\n" \ " bra r5\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r5"); #elif defined(CONFIG_BLACKFIN) /* * P3 holds the pointer to the global_data, P0 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl _" #x "\n_" \ #x ":\n" \ " P0 = [P3 + %0]\n" \ " P0 = [P0 + %1]\n" \ " JUMP (P0)\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "P0"); #elif defined(CONFIG_AVR32) /* * r6 holds the pointer to the global_data. r8 is call clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile( \ " .globl\t" #x "\n" \ #x ":\n" \ " ld.w r8, r6[%0]\n" \ " ld.w pc, r8[%1]\n" \ : \ - : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \ + : "i"(offsetof(gd_t, jt)), "i"(FO(x)) \ : "r8"); #elif defined(CONFIG_SH) /* * r13 holds the pointer to the global_data. r1 is a call clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .align 2\n" \ " .globl " #x "\n" \ @@ -152,12 +166,12 @@ gd_t *global_data; " jmp @r1\n" \ " nop\n" \ " nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1", "r2"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r1", "r2"); #elif defined(CONFIG_SPARC) /* * g7 holds the pointer to the global_data. g1 is call clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile( \ " .globl\t" #x "\n" \ #x ":\n" \ @@ -167,26 +181,26 @@ gd_t *global_data; " ld [%%g1 + %1], %%g1\n" \ " jmp %%g1\n" \ " nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" ); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "g1"); #elif defined(CONFIG_NDS32) /* * r16 holds the pointer to the global_data. gp is call clobbered. * not support reduced register (16 GPR). */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " lwi $r16, [$gp + (%0)]\n" \ " lwi $r16, [$r16 + (%1)]\n" \ " jr $r16\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16"); #elif defined(CONFIG_OPENRISC) /* * r10 holds the pointer to the global_data, r13 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ @@ -194,7 +208,20 @@ gd_t *global_data; " l.lwz r13, %1(r13)\n" \ " l.jr r13\n" \ " l.nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r13"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r13"); +#elif defined(CONFIG_ARC) +/* + * r25 holds the pointer to the global_data. r10 is call clobbered. + */ +#define EXPORT_FUNC(f, a, x, ...) \ + asm volatile( \ +" .align 4\n" \ +" .globl " #x "\n" \ +#x ":\n" \ +" ld r10, [r25, %0]\n" \ +" ld r10, [r10, %1]\n" \ +" j [r10]\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r10"); #else /*" addi $sp, $sp, -24\n" \ " br $r16\n" \*/ @@ -209,7 +236,7 @@ gd_t *global_data; * implementation. On the other hand, asm() statements with * arguments can be used only inside the functions (gcc limitation) */ -#if GCC_VERSION < 3004 +#if GCC_VERSION < 30400 static #endif /* GCC_VERSION */ void __attribute__((unused)) dummy(void) diff --git a/examples/standalone/test_burst.c b/examples/standalone/test_burst.c index 4a16ffb22d..f2fdbf19dc 100644 --- a/examples/standalone/test_burst.c +++ b/examples/standalone/test_burst.c @@ -31,25 +31,6 @@ */ #define TEST_FLASH_ADDR 0x40100000 -/* Define GPIO ports to signal start of burst transfers and errors */ -#ifdef CONFIG_LWMON -/* Use PD.8 to signal start of burst transfers */ -#define GPIO1_DAT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) -#define GPIO1_BIT 0x0080 -/* Configure PD.8 as general purpose output */ -#define GPIO1_INIT \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar &= ~GPIO1_BIT; \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir |= GPIO1_BIT; -/* Use PD.9 to signal error */ -#define GPIO2_DAT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) -#define GPIO2_BIT 0x0040 -/* Configure PD.9 as general purpose output */ -#define GPIO2_INIT \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar &= ~GPIO2_BIT; \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir |= GPIO2_BIT; -#endif /* CONFIG_LWMON */ - - static void test_prepare (void); static int test_burst_start (unsigned long size, unsigned long pattern); static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached); diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c deleted file mode 100644 index 1e16ec7e0e..0000000000 --- a/examples/standalone/x86-testapp.c +++ /dev/null @@ -1,100 +0,0 @@ -#include -#include -#include - -void *func[8], **pfunc; - -typedef struct xxx xxx_t; -struct xxx { - int dummy; - void **pfunc; -} q; - -#define XF_strcpy 3 -#define XF_printf 4 - -#define LABEL(x) \ -asm volatile ( \ - -#if defined(__i386__) -#define EXPORT_FUNC(x) \ -asm volatile ( \ -" .globl mon_" #x "\n" \ -"mon_" #x ":\n" \ -" movl %0, %%eax\n" \ -" movl pfunc, %%ecx\n" \ -" jmp *(%%ecx,%%eax)\n" \ - : : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx"); -#elif defined(__powerpc__) -#define EXPORT_FUNC(x) \ -asm volatile ( \ -" .globl mon_" #x "\n" \ -"mon_" #x ":\n" \ -" lwz %%r11, %0(%%r2)\n" \ -" lwz %%r11, %1(%%r11)\n" \ -" mtctr %%r11\n" \ -" bctr\n" \ - : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r2"); -#elif defined(__arm__) -#define EXPORT_FUNC(x) \ -asm volatile ( \ -" .globl mon_" #x "\n" \ -"mon_" #x ":\n" \ -" ldr ip, [r8, %0]\n" \ -" ldr pc, [ip, %1]\n" \ - : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "ip"); -#elif defined(__mips__) -#define EXPORT_FUNC(x) \ -asm volatile ( \ -" .globl mon_" #x "\n" \ -"mon_" #x ":\n" \ -" lw $25, %0($26)\n" \ -" lw $25, %1($25)\n" \ -" jr $25\n" \ - : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9"); -#elif defined(__nds32__) -#define EXPORT_FUNC(x) \ -asm volatile ( \ -" .globl mon_" #x "\n" \ -"mon_" #x ":\n" \ -" lwi $r16, [$gp + (%0)]\n" \ -" lwi $r16, [$r16 + (%1)]\n" \ -" jr $r16\n" \ -: : "i"(offsetof(xxx_t, pfunc)), \ -"i"(XF_ ## x * sizeof(void *)) : "$r16"); - -#else -#error [No stub code for this arch] -#endif - -void dummy(void) -{ -EXPORT_FUNC(printf) -EXPORT_FUNC(strcpy) -} - -int main(void) -{ -#if defined(__i386__) - xxx_t *pq; -#elif defined(__powerpc__) - register volatile xxx_t *pq asm("r2"); -#elif defined(__arm__) - register volatile xxx_t *pq asm("r8"); -#elif defined(__mips__) - register volatile xxx_t *pq asm("k0"); -#elif defined(__nds32__) - register volatile xxx_t *pq asm("$r16"); -#endif - char buf[32]; - - func[XF_strcpy] = strcpy; - func[XF_printf] = printf; - pq = &q; - pq->pfunc = pfunc = func; - - mon_strcpy(buf, "test"); - mon_printf("hi %s %d z\n", buf, 444); - - return 0; -} diff --git a/fs/Kconfig b/fs/Kconfig new file mode 100644 index 0000000000..41bb0b9f3a --- /dev/null +++ b/fs/Kconfig @@ -0,0 +1,19 @@ +# +# File system configuration +# + +menu "File systems" + +source "fs/ext4/Kconfig" + +source "fs/reiserfs/Kconfig" + +source "fs/fat/Kconfig" + +source "fs/jffs2/Kconfig" + +source "fs/ubifs/Kconfig" + +source "fs/cramfs/Kconfig" + +endmenu diff --git a/fs/Makefile b/fs/Makefile index 7e753e9dd2..51d06fccb6 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -6,26 +6,20 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libfs.o - -COBJS-y += fs.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/ +obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/ +else +obj-y += fs.o + +obj-$(CONFIG_CMD_CBFS) += cbfs/ +obj-$(CONFIG_CMD_CRAMFS) += cramfs/ +obj-$(CONFIG_FS_EXT4) += ext4/ +obj-y += fat/ +obj-$(CONFIG_CMD_JFFS2) += jffs2/ +obj-$(CONFIG_CMD_REISER) += reiserfs/ +obj-$(CONFIG_SANDBOX) += sandbox/ +obj-$(CONFIG_CMD_UBIFS) += ubifs/ +obj-$(CONFIG_YAFFS2) += yaffs2/ +obj-$(CONFIG_CMD_ZFS) += zfs/ +endif diff --git a/fs/cbfs/Makefile b/fs/cbfs/Makefile index 190fd8e561..a106e05dd8 100644 --- a/fs/cbfs/Makefile +++ b/fs/cbfs/Makefile @@ -3,26 +3,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libcbfs.o - -COBJS-$(CONFIG_CMD_CBFS) := cbfs.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cbfs.o diff --git a/fs/cramfs/Kconfig b/fs/cramfs/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/fs/cramfs/Makefile b/fs/cramfs/Makefile index 9b1a3d78a3..12d73a375e 100644 --- a/fs/cramfs/Makefile +++ b/fs/cramfs/Makefile @@ -5,30 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libcramfs.o - -AOBJS = -COBJS-$(CONFIG_CMD_CRAMFS) := cramfs.o -COBJS-$(CONFIG_CMD_CRAMFS) += uncompress.o - -SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) - -#CPPFLAGS += - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := cramfs.o +obj-y += uncompress.o diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c index e578a1e8bc..fd8e4ef31e 100644 --- a/fs/cramfs/cramfs.c +++ b/fs/cramfs/cramfs.c @@ -43,9 +43,10 @@ struct cramfs_super super; * device address space offset, so we need to shift it by a device start address. */ #if !defined(CONFIG_SYS_NO_FLASH) extern flash_info_t flash_info[]; -#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0]) +#define PART_OFFSET(x) ((ulong)x->offset + \ + flash_info[x->dev->id->num].start[0]) #else -#define PART_OFFSET(x) (x->offset) +#define PART_OFFSET(x) ((ulong)x->offset) #endif static int cramfs_read_super (struct part_info *info) diff --git a/fs/ext4/Kconfig b/fs/ext4/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/fs/ext4/Makefile b/fs/ext4/Makefile index f45bb324ec..8d15bdad67 100644 --- a/fs/ext4/Makefile +++ b/fs/ext4/Makefile @@ -9,28 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libext4fs.o - -AOBJS = -COBJS-$(CONFIG_FS_EXT4) := ext4fs.o ext4_common.o dev.o -COBJS-$(CONFIG_EXT4_WRITE) += ext4_write.o ext4_journal.o crc16.o - -SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) - - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ext4fs.o ext4_common.o dev.o +obj-$(CONFIG_EXT4_WRITE) += ext4_write.o ext4_journal.o crc16.o diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c index 787e04133a..c77c02cdfc 100644 --- a/fs/ext4/dev.c +++ b/fs/ext4/dev.c @@ -41,7 +41,7 @@ void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info) get_fs()->dev_desc = rbdd; part_info = info; part_offset = info->start; - get_fs()->total_sect = (info->size * info->blksz) >> + get_fs()->total_sect = ((uint64_t)info->size * info->blksz) >> get_fs()->dev_desc->log2blksz; } @@ -73,6 +73,7 @@ int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf) debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len); if (byte_offset != 0) { + int readlen; /* read first part which isn't aligned with start of sector */ if (ext4fs_block_dev_desc-> block_read(ext4fs_block_dev_desc->dev, @@ -81,13 +82,11 @@ int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf) printf(" ** ext2fs_devread() read error **\n"); return 0; } - memcpy(buf, sec_buf + byte_offset, - min(ext4fs_block_dev_desc->blksz - - byte_offset, byte_len)); - buf += min(ext4fs_block_dev_desc->blksz - - byte_offset, byte_len); - byte_len -= min(ext4fs_block_dev_desc->blksz - - byte_offset, byte_len); + readlen = min((int)ext4fs_block_dev_desc->blksz - byte_offset, + byte_len); + memcpy(buf, sec_buf + byte_offset, readlen); + buf += readlen; + byte_len -= readlen; sector++; } diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 352943ec51..cab5465b9d 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -73,7 +74,7 @@ void put_ext4(uint64_t off, void *buf, uint32_t size) if ((startblock + (size >> log2blksz)) > (part_offset + fs->total_sect)) { printf("part_offset is " LBAFU "\n", part_offset); - printf("total_sector is %llu\n", fs->total_sect); + printf("total_sector is %" PRIu64 "\n", fs->total_sect); printf("error: overflow occurs\n"); return; } @@ -445,9 +446,9 @@ restart: goto fail; } put_ext4(((uint64_t) - (g_parent_inode->b. + ((uint64_t)g_parent_inode->b. blocks.dir_blocks[direct_blk_idx] * - fs->blksz)), zero_buffer, fs->blksz); + (uint64_t)fs->blksz)), zero_buffer, fs->blksz); g_parent_inode->size = g_parent_inode->size + fs->blksz; g_parent_inode->blockcnt = @@ -864,8 +865,8 @@ long int ext4fs_get_new_blk_no(void) for (i = 0; i < fs->no_blkgrp; i++) { if (bgd[i].free_blocks) { if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) { - put_ext4(((uint64_t) (bgd[i].block_id * - fs->blksz)), + put_ext4(((uint64_t) ((uint64_t)bgd[i].block_id * + (uint64_t)fs->blksz)), zero_buffer, fs->blksz); bgd[i].bg_flags = bgd[i]. @@ -904,10 +905,8 @@ long int ext4fs_get_new_blk_no(void) restart: fs->curr_blkno++; /* get the blockbitmap index respective to blockno */ - if (fs->blksz != 1024) { - bg_idx = fs->curr_blkno / blk_per_grp; - } else { - bg_idx = fs->curr_blkno / blk_per_grp; + bg_idx = fs->curr_blkno / blk_per_grp; + if (fs->blksz == 1024) { remainder = fs->curr_blkno % blk_per_grp; if (!remainder) bg_idx--; @@ -929,8 +928,8 @@ restart: if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) { memset(zero_buffer, '\0', fs->blksz); - put_ext4(((uint64_t) (bgd[bg_idx].block_id * - fs->blksz)), zero_buffer, fs->blksz); + put_ext4(((uint64_t) ((uint64_t)bgd[bg_idx].block_id * + (uint64_t)fs->blksz)), zero_buffer, fs->blksz); memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz); bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags & ~EXT4_BG_BLOCK_UNINIT; @@ -996,8 +995,8 @@ int ext4fs_get_new_inode_no(void) bgd[i].free_inodes; if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) { put_ext4(((uint64_t) - (bgd[i].inode_id * - fs->blksz)), + ((uint64_t)bgd[i].inode_id * + (uint64_t)fs->blksz)), zero_buffer, fs->blksz); bgd[i].bg_flags = bgd[i].bg_flags & ~EXT4_BG_INODE_UNINIT; @@ -1037,8 +1036,8 @@ restart: ibmap_idx = fs->curr_inode_no / inodes_per_grp; if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) { memset(zero_buffer, '\0', fs->blksz); - put_ext4(((uint64_t) (bgd[ibmap_idx].inode_id * - fs->blksz)), zero_buffer, + put_ext4(((uint64_t) ((uint64_t)bgd[ibmap_idx].inode_id * + (uint64_t)fs->blksz)), zero_buffer, fs->blksz); bgd[ibmap_idx].bg_flags = bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT; @@ -1143,7 +1142,7 @@ static void alloc_single_indirect_block(struct ext2_inode *file_inode, } /* write the block to disk */ - put_ext4(((uint64_t) (si_blockno * fs->blksz)), + put_ext4(((uint64_t) ((uint64_t)si_blockno * (uint64_t)fs->blksz)), si_start_addr, fs->blksz); file_inode->b.blocks.indir_block = si_blockno; } @@ -1242,7 +1241,7 @@ static void alloc_double_indirect_block(struct ext2_inode *file_inode, break; } /* write the block table */ - put_ext4(((uint64_t) (di_blockno_child * fs->blksz)), + put_ext4(((uint64_t) ((uint64_t)di_blockno_child * (uint64_t)fs->blksz)), di_child_buff_start, fs->blksz); free(di_child_buff_start); di_child_buff_start = NULL; @@ -1250,7 +1249,7 @@ static void alloc_double_indirect_block(struct ext2_inode *file_inode, if (*total_remaining_blocks == 0) break; } - put_ext4(((uint64_t) (di_blockno_parent * fs->blksz)), + put_ext4(((uint64_t) ((uint64_t)di_blockno_parent * (uint64_t)fs->blksz)), di_block_start_addr, fs->blksz); file_inode->b.blocks.double_indir_block = di_blockno_parent; } @@ -1348,8 +1347,8 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, break; } /* write the child block */ - put_ext4(((uint64_t) (ti_child_blockno * - fs->blksz)), + put_ext4(((uint64_t) ((uint64_t)ti_child_blockno * + (uint64_t)fs->blksz)), ti_cbuff_start_addr, fs->blksz); free(ti_cbuff_start_addr); @@ -1357,7 +1356,7 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, break; } /* write the parent block */ - put_ext4(((uint64_t) (ti_parent_blockno * fs->blksz)), + put_ext4(((uint64_t) ((uint64_t)ti_parent_blockno * (uint64_t)fs->blksz)), ti_pbuff_start_addr, fs->blksz); free(ti_pbuff_start_addr); @@ -1365,7 +1364,7 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode, break; } /* write the grand parent block */ - put_ext4(((uint64_t) (ti_gp_blockno * fs->blksz)), + put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)), ti_gp_buff_start_addr, fs->blksz); file_inode->b.blocks.triple_indir_block = ti_gp_blockno; } @@ -1382,7 +1381,7 @@ void ext4fs_allocate_blocks(struct ext2_inode *file_inode, unsigned int no_blks_reqd = 0; /* allocation of direct blocks */ - for (i = 0; i < INDIRECT_BLOCKS; i++) { + for (i = 0; total_remaining_blocks && i < INDIRECT_BLOCKS; i++) { direct_blockno = ext4fs_get_new_blk_no(); if (direct_blockno == -1) { printf("no block left to assign\n"); @@ -1392,8 +1391,6 @@ void ext4fs_allocate_blocks(struct ext2_inode *file_inode, debug("DB %ld: %u\n", direct_blockno, total_remaining_blocks); total_remaining_blocks--; - if (total_remaining_blocks == 0) - break; } alloc_single_indirect_block(file_inode, &total_remaining_blocks, @@ -1414,7 +1411,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block { struct ext4_extent_idx *index; unsigned long long block; - struct ext_filesystem *fs = get_fs(); + int blksz = EXT2_BLOCK_SIZE(data); int i; while (1) { @@ -1430,7 +1427,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block i++; if (i >= le16_to_cpu(ext_block->eh_entries)) break; - } while (fileblock > le32_to_cpu(index[i].ei_block)); + } while (fileblock >= le32_to_cpu(index[i].ei_block)); if (--i < 0) return 0; @@ -1438,7 +1435,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block block = le16_to_cpu(index[i].ei_leaf_hi); block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo); - if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, fs->blksz, + if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, blksz, buf)) ext_block = (struct ext4_extent_header *)buf; else @@ -1843,16 +1840,20 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) return blknr; } -void ext4fs_close(void) +/** + * ext4fs_reinit_global() - Reinitialize values of ext4 write implementation's + * global pointers + * + * This function assures that for a file with the same name but different size + * the sequential store on the ext4 filesystem will be correct. + * + * In this function the global data, responsible for internal representation + * of the ext4 data are initialized to the reset state. Without this, during + * replacement of the smaller file with the bigger truncation of new file was + * performed. + */ +void ext4fs_reinit_global(void) { - if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) { - ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen); - ext4fs_file = NULL; - } - if (ext4fs_root != NULL) { - free(ext4fs_root); - ext4fs_root = NULL; - } if (ext4fs_indir1_block != NULL) { free(ext4fs_indir1_block); ext4fs_indir1_block = NULL; @@ -1872,12 +1873,26 @@ void ext4fs_close(void) ext4fs_indir3_blkno = -1; } } +void ext4fs_close(void) +{ + if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) { + ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen); + ext4fs_file = NULL; + } + if (ext4fs_root != NULL) { + free(ext4fs_root); + ext4fs_root = NULL; + } + + ext4fs_reinit_global(); +} int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, struct ext2fs_node **fnode, int *ftype) { unsigned int fpos = 0; int status; + loff_t actread; struct ext2fs_node *diro = (struct ext2fs_node *) dir; #ifdef DEBUG @@ -1895,8 +1910,8 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, status = ext4fs_read_file(diro, fpos, sizeof(struct ext2_dirent), - (char *) &dirent); - if (status < 1) + (char *)&dirent, &actread); + if (status < 0) return 0; if (dirent.namelen != 0) { @@ -1907,8 +1922,9 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, status = ext4fs_read_file(diro, fpos + sizeof(struct ext2_dirent), - dirent.namelen, filename); - if (status < 1) + dirent.namelen, filename, + &actread); + if (status < 0) return 0; fdiro = zalloc(sizeof(struct ext2fs_node)); @@ -1990,8 +2006,8 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, printf("< ? > "); break; } - printf("%10d %s\n", - __le32_to_cpu(fdiro->inode.size), + printf("%10u %s\n", + __le32_to_cpu(fdiro->inode.size), filename); } free(fdiro); @@ -2006,6 +2022,7 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node) char *symlink; struct ext2fs_node *diro = node; int status; + loff_t actread; if (!diro->inode_read) { status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode); @@ -2022,7 +2039,7 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node) } else { status = ext4fs_read_file(diro, 0, __le32_to_cpu(diro->inode.size), - symlink); + symlink, &actread); if (status == 0) { free(symlink); return 0; @@ -2156,11 +2173,10 @@ int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode, return 1; } -int ext4fs_open(const char *filename) +int ext4fs_open(const char *filename, loff_t *len) { struct ext2fs_node *fdiro = NULL; int status; - int len; if (ext4fs_root == NULL) return -1; @@ -2177,10 +2193,10 @@ int ext4fs_open(const char *filename) if (status == 0) goto fail; } - len = __le32_to_cpu(fdiro->inode.size); + *len = __le32_to_cpu(fdiro->inode.size); ext4fs_file = fdiro; - return len; + return 0; fail: ext4fs_free_node(fdiro, &ext4fs_root->diropen); diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h index 5fa1719f2e..48fd2ac51d 100644 --- a/fs/ext4/ext4_common.h +++ b/fs/ext4/ext4_common.h @@ -50,8 +50,8 @@ static inline void *zalloc(size_t size) int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode); -int ext4fs_read_file(struct ext2fs_node *node, int pos, - unsigned int len, char *buf); +int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, loff_t len, + char *buf, loff_t *actread); int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode, struct ext2fs_node **foundnode, int expecttype); int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c index d4a46ed8b6..3f613351a4 100644 --- a/fs/ext4/ext4_journal.c +++ b/fs/ext4/ext4_journal.c @@ -371,7 +371,7 @@ void recover_transaction(int prev_desc_logical_no) blknr = read_allocated_block(&inode_journal, i); ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz, metadata_buff); - put_ext4((uint64_t)(be32_to_cpu(tag->block) * fs->blksz), + put_ext4((uint64_t)((uint64_t)be32_to_cpu(tag->block) * (uint64_t)fs->blksz), metadata_buff, (uint32_t) fs->blksz); } while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG)); fail: @@ -531,7 +531,7 @@ end: blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK); - put_ext4((uint64_t) (blknr * fs->blksz), + put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), (struct journal_superblock_t *)temp_buff, (uint32_t) fs->blksz); ext4fs_free_revoke_blks(); @@ -590,7 +590,7 @@ static void update_descriptor_block(long int blknr) tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_LAST_TAG); memcpy(temp - sizeof(struct ext3_journal_block_tag), &tag, sizeof(struct ext3_journal_block_tag)); - put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz); + put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz); free(temp_buff); free(buf); @@ -625,7 +625,7 @@ static void update_commit_block(long int blknr) return; } memcpy(buf, &jdb, sizeof(struct journal_header_t)); - put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz); + put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz); free(temp_buff); free(buf); diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index 1e1924c806..f7c52cc4cc 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -40,18 +40,18 @@ static void ext4fs_update(void) /* update block groups */ for (i = 0; i < fs->no_blkgrp; i++) { fs->bgd[i].bg_checksum = ext4fs_checksum_update(i); - put_ext4((uint64_t)(fs->bgd[i].block_id * fs->blksz), + put_ext4((uint64_t)((uint64_t)fs->bgd[i].block_id * (uint64_t)fs->blksz), fs->blk_bmaps[i], fs->blksz); } /* update inode table groups */ for (i = 0; i < fs->no_blkgrp; i++) { - put_ext4((uint64_t) (fs->bgd[i].inode_id * fs->blksz), + put_ext4((uint64_t) ((uint64_t)fs->bgd[i].inode_id * (uint64_t)fs->blksz), fs->inode_bmaps[i], fs->blksz); } /* update the block group descriptor table */ - put_ext4((uint64_t)(fs->gdtable_blkno * fs->blksz), + put_ext4((uint64_t)((uint64_t)fs->gdtable_blkno * (uint64_t)fs->blksz), (struct ext2_block_group *)fs->gdtable, (fs->blksz * fs->no_blk_pergdt)); @@ -116,10 +116,8 @@ static void delete_single_indirect_block(struct ext2_inode *inode) if (inode->b.blocks.indir_block != 0) { debug("SIPB releasing %u\n", inode->b.blocks.indir_block); blknr = inode->b.blocks.indir_block; - if (fs->blksz != 1024) { - bg_idx = blknr / blk_per_grp; - } else { - bg_idx = blknr / blk_per_grp; + bg_idx = blknr / blk_per_grp; + if (fs->blksz == 1024) { remainder = blknr % blk_per_grp; if (!remainder) bg_idx--; @@ -181,11 +179,9 @@ static void delete_double_indirect_block(struct ext2_inode *inode) break; debug("DICB releasing %u\n", *di_buffer); - if (fs->blksz != 1024) { - bg_idx = (*di_buffer) / blk_per_grp; - } else { - bg_idx = (*di_buffer) / blk_per_grp; - remainder = (*di_buffer) % blk_per_grp; + bg_idx = *di_buffer / blk_per_grp; + if (fs->blksz == 1024) { + remainder = *di_buffer % blk_per_grp; if (!remainder) bg_idx--; } @@ -213,10 +209,8 @@ static void delete_double_indirect_block(struct ext2_inode *inode) /* removing the parent double indirect block */ blknr = inode->b.blocks.double_indir_block; - if (fs->blksz != 1024) { - bg_idx = blknr / blk_per_grp; - } else { - bg_idx = blknr / blk_per_grp; + bg_idx = blknr / blk_per_grp; + if (fs->blksz == 1024) { remainder = blknr % blk_per_grp; if (!remainder) bg_idx--; @@ -293,12 +287,9 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) for (j = 0; j < fs->blksz / sizeof(int); j++) { if (*tip_buffer == 0) break; - if (fs->blksz != 1024) { - bg_idx = (*tip_buffer) / blk_per_grp; - } else { - bg_idx = (*tip_buffer) / blk_per_grp; - - remainder = (*tip_buffer) % blk_per_grp; + bg_idx = *tip_buffer / blk_per_grp; + if (fs->blksz == 1024) { + remainder = *tip_buffer % blk_per_grp; if (!remainder) bg_idx--; } @@ -336,12 +327,9 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) * removing the grand parent blocks * which is connected to inode */ - if (fs->blksz != 1024) { - bg_idx = (*tigp_buffer) / blk_per_grp; - } else { - bg_idx = (*tigp_buffer) / blk_per_grp; - - remainder = (*tigp_buffer) % blk_per_grp; + bg_idx = *tigp_buffer / blk_per_grp; + if (fs->blksz == 1024) { + remainder = *tigp_buffer % blk_per_grp; if (!remainder) bg_idx--; } @@ -371,10 +359,8 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) /* removing the grand parent triple indirect block */ blknr = inode->b.blocks.triple_indir_block; - if (fs->blksz != 1024) { - bg_idx = blknr / blk_per_grp; - } else { - bg_idx = blknr / blk_per_grp; + bg_idx = blknr / blk_per_grp; + if (fs->blksz == 1024) { remainder = blknr % blk_per_grp; if (!remainder) bg_idx--; @@ -452,10 +438,8 @@ static int ext4fs_delete_file(int inodeno) for (i = 0; i < no_blocks; i++) { blknr = read_allocated_block(&(node_inode->inode), i); - if (fs->blksz != 1024) { - bg_idx = blknr / blk_per_grp; - } else { - bg_idx = blknr / blk_per_grp; + bg_idx = blknr / blk_per_grp; + if (fs->blksz == 1024) { remainder = blknr % blk_per_grp; if (!remainder) bg_idx--; @@ -499,10 +483,8 @@ static int ext4fs_delete_file(int inodeno) no_blocks++; for (i = 0; i < no_blocks; i++) { blknr = read_allocated_block(&inode, i); - if (fs->blksz != 1024) { - bg_idx = blknr / blk_per_grp; - } else { - bg_idx = blknr / blk_per_grp; + bg_idx = blknr / blk_per_grp; + if (fs->blksz == 1024) { remainder = blknr % blk_per_grp; if (!remainder) bg_idx--; @@ -580,6 +562,7 @@ static int ext4fs_delete_file(int inodeno) ext4fs_update(); ext4fs_deinit(); + ext4fs_reinit_global(); if (ext4fs_init() != 0) { printf("error in File System init\n"); @@ -709,7 +692,7 @@ void ext4fs_deinit(void) temp_buff); jsb = (struct journal_superblock_t *)temp_buff; jsb->s_start = cpu_to_be32(0); - put_ext4((uint64_t) (blknr * fs->blksz), + put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), (struct journal_superblock_t *)temp_buff, fs->blksz); free(temp_buff); } @@ -793,7 +776,7 @@ static int ext4fs_write_file(struct ext2_inode *file_inode, delayed_next += blockend >> log2blksz; } else { /* spill */ put_ext4((uint64_t) - (delayed_start << log2blksz), + ((uint64_t)delayed_start << log2blksz), delayed_buf, (uint32_t) delayed_extent); previous_block_number = blknr; @@ -814,7 +797,7 @@ static int ext4fs_write_file(struct ext2_inode *file_inode, } else { if (previous_block_number != -1) { /* spill */ - put_ext4((uint64_t) (delayed_start << + put_ext4((uint64_t) ((uint64_t)delayed_start << log2blksz), delayed_buf, (uint32_t) delayed_extent); @@ -826,7 +809,7 @@ static int ext4fs_write_file(struct ext2_inode *file_inode, } if (previous_block_number != -1) { /* spill */ - put_ext4((uint64_t) (delayed_start << log2blksz), + put_ext4((uint64_t) ((uint64_t)delayed_start << log2blksz), delayed_buf, (uint32_t) delayed_extent); previous_block_number = -1; } @@ -857,7 +840,7 @@ int ext4fs_write(const char *fname, unsigned char *buffer, unsigned int ibmap_idx; struct ext_filesystem *fs = get_fs(); ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256); - memset(filename, 0x00, sizeof(filename)); + memset(filename, 0x00, 256); g_parent_inode = zalloc(sizeof(struct ext2_inode)); if (!g_parent_inode) @@ -992,3 +975,35 @@ fail: return -1; } + +int ext4_write_file(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite) +{ + int ret; + + if (offset != 0) { + printf("** Cannot support non-zero offset **\n"); + return -1; + } + + /* mount the filesystem */ + if (!ext4fs_mount(0)) { + printf("** Error Bad ext4 partition **\n"); + goto fail; + } + + ret = ext4fs_write(filename, buf, len); + + if (ret) { + printf("** Error ext4fs_write() **\n"); + goto fail; + } + ext4fs_close(); + + return 0; + +fail: + ext4fs_close(); + + return -1; +} diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 735b256417..258b93791b 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -25,6 +25,7 @@ #include #include #include "ext4_common.h" +#include int ext4fs_symlinknest; struct ext_filesystem ext_fs; @@ -45,8 +46,8 @@ void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot) * Optimized read file API : collects and defers contiguous sector * reads into one potentially more efficient larger sequential read action */ -int ext4fs_read_file(struct ext2fs_node *node, int pos, - unsigned int len, char *buf) +int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, + loff_t len, char *buf, loff_t *actread) { struct ext_filesystem *fs = get_fs(); int i; @@ -67,11 +68,11 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos, if (len > filesize) len = filesize; - blockcnt = ((len + pos) + blocksize - 1) / blocksize; + blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize); - for (i = pos / blocksize; i < blockcnt; i++) { + for (i = lldiv(pos, blocksize); i < blockcnt; i++) { lbaint_t blknr; - int blockoff = pos % blocksize; + int blockoff = pos - (blocksize * i); int blockend = blocksize; int skipfirst = 0; blknr = read_allocated_block(&(node->inode), i); @@ -82,7 +83,7 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos, /* Last block. */ if (i == blockcnt - 1) { - blockend = (len + pos) % blocksize; + blockend = (len + pos) - (blocksize * i); /* The last portion is exactly blocksize. */ if (!blockend) @@ -90,7 +91,7 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos, } /* First block. */ - if (i == pos / blocksize) { + if (i == lldiv(pos, blocksize)) { skipfirst = blockoff; blockend -= skipfirst; } @@ -150,7 +151,8 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos, previous_block_number = -1; } - return len; + *actread = len; + return 0; } int ext4fs_ls(const char *dirname) @@ -174,12 +176,26 @@ int ext4fs_ls(const char *dirname) return 0; } -int ext4fs_read(char *buf, unsigned len) +int ext4fs_exists(const char *filename) +{ + loff_t file_len; + int ret; + + ret = ext4fs_open(filename, &file_len); + return ret == 0; +} + +int ext4fs_size(const char *filename, loff_t *size) +{ + return ext4fs_open(filename, size); +} + +int ext4fs_read(char *buf, loff_t len, loff_t *actread) { if (ext4fs_root == NULL || ext4fs_file == NULL) return 0; - return ext4fs_read_file(ext4fs_file, 0, len, buf); + return ext4fs_read_file(ext4fs_file, 0, len, buf, actread); } int ext4fs_probe(block_dev_desc_t *fs_dev_desc, @@ -195,18 +211,19 @@ int ext4fs_probe(block_dev_desc_t *fs_dev_desc, return 0; } -int ext4_read_file(const char *filename, void *buf, int offset, int len) +int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *len_read) { - int file_len; - int len_read; + loff_t file_len; + int ret; if (offset != 0) { printf("** Cannot support non-zero offset **\n"); return -1; } - file_len = ext4fs_open(filename); - if (file_len < 0) { + ret = ext4fs_open(filename, &file_len); + if (ret < 0) { printf("** File not found %s **\n", filename); return -1; } @@ -214,7 +231,20 @@ int ext4_read_file(const char *filename, void *buf, int offset, int len) if (len == 0) len = file_len; - len_read = ext4fs_read(buf, len); + return ext4fs_read(buf, len, len_read); +} - return len_read; +int ext4fs_uuid(char *uuid_str) +{ + if (ext4fs_root == NULL) + return -1; + +#ifdef CONFIG_LIB_UUID + uuid_bin_to_str((unsigned char *)ext4fs_root->sblock.unique_id, + uuid_str, UUID_STR_FORMAT_STD); + + return 0; +#else + return -ENOSYS; +#endif } diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/fs/fat/Makefile b/fs/fat/Makefile index c00681f31b..b60e8486c4 100644 --- a/fs/fat/Makefile +++ b/fs/fat/Makefile @@ -3,34 +3,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libfat.o - -AOBJS = -COBJS-$(CONFIG_FS_FAT) := fat.o -COBJS-$(CONFIG_FAT_WRITE):= fat_write.o +obj-$(CONFIG_FS_FAT) := fat.o +obj-$(CONFIG_FAT_WRITE):= fat_write.o ifndef CONFIG_SPL_BUILD -COBJS-$(CONFIG_FS_FAT) += file.o +obj-$(CONFIG_FS_FAT) += file.o endif - -SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -# SEE README.arm-unaligned-accesses -$(obj)file.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/fs/fat/fat.c b/fs/fat/fat.c index b41d62e3c3..bccc3e3ed8 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -317,32 +317,32 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) /* * Read at most 'maxsize' bytes from 'pos' in the file associated with 'dentptr' * into 'buffer'. - * Return the number of bytes read or -1 on fatal errors. + * Update the number of bytes read in *gotsize or return -1 on fatal errors. */ __u8 get_contents_vfatname_block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN); -static long -get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, - __u8 *buffer, unsigned long maxsize) +static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, + __u8 *buffer, loff_t maxsize, loff_t *gotsize) { - unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; + loff_t filesize = FAT2CPU32(dentptr->size); unsigned int bytesperclust = mydata->clust_size * mydata->sect_size; __u32 curclust = START(dentptr); __u32 endclust, newclust; - unsigned long actsize; + loff_t actsize; - debug("Filesize: %ld bytes\n", filesize); + *gotsize = 0; + debug("Filesize: %llu bytes\n", filesize); if (pos >= filesize) { - debug("Read position past EOF: %lu\n", pos); - return gotsize; + debug("Read position past EOF: %llu\n", pos); + return 0; } if (maxsize > 0 && filesize > pos + maxsize) filesize = pos + maxsize; - debug("%ld bytes\n", filesize); + debug("%llu bytes\n", filesize); actsize = bytesperclust; @@ -352,7 +352,7 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } actsize += bytesperclust; } @@ -364,7 +364,7 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, /* align to beginning of next cluster if any */ if (pos) { - actsize = min(filesize, bytesperclust); + actsize = min(filesize, (loff_t)bytesperclust); if (get_cluster(mydata, curclust, get_contents_vfatname_block, (int)actsize) != 0) { printf("Error reading cluster\n"); @@ -373,16 +373,16 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, filesize -= actsize; actsize -= pos; memcpy(buffer, get_contents_vfatname_block + pos, actsize); - gotsize += actsize; + *gotsize += actsize; if (!filesize) - return gotsize; + return 0; buffer += actsize; curclust = get_fatent(mydata, curclust); if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } } @@ -398,7 +398,7 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, if (CHECK_CLUST(newclust, mydata->fatsize)) { debug("curclust: 0x%x\n", newclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } endclust = newclust; actsize += bytesperclust; @@ -410,14 +410,14 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, printf("Error reading cluster\n"); return -1; } - gotsize += actsize; - return gotsize; + *gotsize += actsize; + return 0; getit: if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { printf("Error reading cluster\n"); return -1; } - gotsize += (int)actsize; + *gotsize += (int)actsize; filesize -= actsize; buffer += actsize; @@ -425,7 +425,7 @@ getit: if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); printf("Invalid FAT entry\n"); - return gotsize; + return 0; } actsize = bytesperclust; endclust = curclust; @@ -633,8 +633,8 @@ static dir_entry *get_dentfromdir(fsdata *mydata, int startsect, } if (doit) { if (dirc == ' ') { - printf(" %8ld %s%c\n", - (long)FAT2CPU32(dentptr->size), + printf(" %8u %s%c\n", + FAT2CPU32(dentptr->size), l_name, dirc); } else { @@ -690,8 +690,8 @@ static dir_entry *get_dentfromdir(fsdata *mydata, int startsect, if (doit) { if (dirc == ' ') { - printf(" %8ld %s%c\n", - (long)FAT2CPU32(dentptr->size), + printf(" %8u %s%c\n", + FAT2CPU32(dentptr->size), s_name, dirc); } else { printf(" %s%c\n", @@ -806,9 +806,8 @@ exit: __u8 do_fat_read_at_block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN); -long -do_fat_read_at(const char *filename, unsigned long pos, void *buffer, - unsigned long maxsize, int dols) +int do_fat_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, int dols, int dogetsize, loff_t *size) { char fnamecopy[2048]; boot_sector bs; @@ -821,11 +820,14 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, __u32 cursect; int idx, isdir = 0; int files = 0, dirs = 0; - long ret = -1; + int ret = -1; int firsttime; __u32 root_cluster = 0; + __u32 read_blk; int rootdir_size = 0; - int j; + int buffer_blk_cnt; + int do_read; + __u8 *dir_ptr; if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) { debug("Error: reading boot sector\n"); @@ -910,24 +912,54 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, isdir = 1; } - j = 0; + buffer_blk_cnt = 0; + firsttime = 1; while (1) { int i; - if (j == 0) { - debug("FAT read sect=%d, clust_size=%d, DIRENTSPERBLOCK=%zd\n", - cursect, mydata->clust_size, DIRENTSPERBLOCK); + if (mydata->fatsize == 32 || firsttime) { + dir_ptr = do_fat_read_at_block; + firsttime = 0; + } else { + /** + * FAT16 sector buffer modification: + * Each loop, the second buffered block is moved to + * the buffer begin, and two next sectors are read + * next to the previously moved one. So the sector + * buffer keeps always 3 sectors for fat16. + * And the current sector is the buffer second sector + * beside the "firsttime" read, when it is the first one. + * + * PREFETCH_BLOCKS is 2 for FAT16 == loop[0:1] + * n = computed root dir sector + * loop | cursect-1 | cursect | cursect+1 | + * 0 | sector n+0 | sector n+1 | none | + * 1 | none | sector n+0 | sector n+1 | + * 0 | sector n+1 | sector n+2 | sector n+3 | + * 1 | sector n+3 | ... + */ + dir_ptr = (do_fat_read_at_block + mydata->sect_size); + memcpy(do_fat_read_at_block, dir_ptr, mydata->sect_size); + } + + do_read = 1; - if (disk_read(cursect, - (mydata->fatsize == 32) ? - (mydata->clust_size) : - PREFETCH_BLOCKS, - do_fat_read_at_block) < 0) { + if (mydata->fatsize == 32 && buffer_blk_cnt) + do_read = 0; + + if (do_read) { + read_blk = (mydata->fatsize == 32) ? + mydata->clust_size : PREFETCH_BLOCKS; + + debug("FAT read(sect=%d, cnt:%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n", + cursect, read_blk, mydata->clust_size, DIRENTSPERBLOCK); + + if (disk_read(cursect, read_blk, dir_ptr) < 0) { debug("Error: reading rootdir block\n"); goto exit; } - dentptr = (dir_entry *) do_fat_read_at_block; + dentptr = (dir_entry *)dir_ptr; } for (i = 0; i < DIRENTSPERBLOCK; i++) { @@ -952,7 +984,7 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, get_vfatname(mydata, root_cluster, - do_fat_read_at_block, + dir_ptr, dentptr, l_name); if (dols == LS_ROOT) { @@ -974,8 +1006,8 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, } if (doit) { if (dirc == ' ') { - printf(" %8ld %s%c\n", - (long)FAT2CPU32(dentptr->size), + printf(" %8u %s%c\n", + FAT2CPU32(dentptr->size), l_name, dirc); } else { @@ -1032,8 +1064,8 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, } if (doit) { if (dirc == ' ') { - printf(" %8ld %s%c\n", - (long)FAT2CPU32(dentptr->size), + printf(" %8u %s%c\n", + FAT2CPU32(dentptr->size), s_name, dirc); } else { printf(" %s%c\n", @@ -1063,7 +1095,7 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, goto rootdir_done; /* We got a match */ } - debug("END LOOP: j=%d clust_size=%d\n", j, + debug("END LOOP: buffer_blk_cnt=%d clust_size=%d\n", buffer_blk_cnt, mydata->clust_size); /* @@ -1071,10 +1103,10 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, * root directory clusters when a cluster has been * completely processed. */ - ++j; + ++buffer_blk_cnt; int rootdir_end = 0; if (mydata->fatsize == 32) { - if (j == mydata->clust_size) { + if (buffer_blk_cnt == mydata->clust_size) { int nxtsect = 0; int nxt_clust = 0; @@ -1087,11 +1119,11 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, root_cluster = nxt_clust; cursect = nxtsect; - j = 0; + buffer_blk_cnt = 0; } } else { - if (j == PREFETCH_BLOCKS) - j = 0; + if (buffer_blk_cnt == PREFETCH_BLOCKS) + buffer_blk_cnt = 0; rootdir_end = (++cursect - mydata->rootdir_sect >= rootdir_size); @@ -1102,7 +1134,7 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, if (dols == LS_ROOT) { printf("\n%d file(s), %d dir(s)\n\n", files, dirs); - ret = 0; + *size = 0; } goto exit; } @@ -1141,7 +1173,7 @@ rootdir_done: if (get_dentfromdir(mydata, startsect, subname, dentptr, isdir ? 0 : dols) == NULL) { if (dols && !isdir) - ret = 0; + *size = 0; goto exit; } @@ -1152,18 +1184,23 @@ rootdir_done: subname = nextname; } - ret = get_contents(mydata, dentptr, pos, buffer, maxsize); - debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret); + if (dogetsize) { + *size = FAT2CPU32(dentptr->size); + ret = 0; + } else { + ret = get_contents(mydata, dentptr, pos, buffer, maxsize, size); + } + debug("Size: %u, got: %llu\n", FAT2CPU32(dentptr->size), *size); exit: free(mydata->fatbuf); return ret; } -long -do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols) +int do_fat_read(const char *filename, void *buffer, loff_t maxsize, int dols, + loff_t *actread) { - return do_fat_read_at(filename, 0, buffer, maxsize, dols); + return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0, actread); } int file_fat_detectfs(void) @@ -1230,32 +1267,55 @@ int file_fat_detectfs(void) int file_fat_ls(const char *dir) { - return do_fat_read(dir, NULL, 0, LS_YES); + loff_t size; + + return do_fat_read(dir, NULL, 0, LS_YES, &size); +} + +int fat_exists(const char *filename) +{ + int ret; + loff_t size; + + ret = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, &size); + return ret == 0; +} + +int fat_size(const char *filename, loff_t *size) +{ + return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, size); } -long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, - unsigned long maxsize) +int file_fat_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread) { printf("reading %s\n", filename); - return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO); + return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0, + actread); } -long file_fat_read(const char *filename, void *buffer, unsigned long maxsize) +int file_fat_read(const char *filename, void *buffer, int maxsize) { - return file_fat_read_at(filename, 0, buffer, maxsize); + loff_t actread; + int ret; + + ret = file_fat_read_at(filename, 0, buffer, maxsize, &actread); + if (ret) + return ret; + else + return actread; } -int fat_read_file(const char *filename, void *buf, int offset, int len) +int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread) { - int len_read; + int ret; - len_read = file_fat_read_at(filename, offset, buf, len); - if (len_read == -1) { + ret = file_fat_read_at(filename, offset, buf, len, actread); + if (ret) printf("** Unable to read file %s **\n", filename); - return -1; - } - return len_read; + return ret; } void fat_close(void) diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index b78026a81f..98b88add83 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include "fat.c" static void uppercase(char *str, int len) @@ -57,7 +59,7 @@ static void set_name(dir_entry *dirent, const char *filename) if (len == 0) return; - memcpy(s_name, filename, len); + strcpy(s_name, filename); uppercase(s_name, len); period = strchr(s_name, '.'); @@ -139,6 +141,11 @@ static __u32 get_fatent_value(fsdata *mydata, __u32 entry) __u32 ret = 0x00; __u16 val1, val2; + if (CHECK_CLUST(entry, mydata->fatsize)) { + printf("Error: Invalid FAT entry: 0x%08x\n", entry); + return ret; + } + switch (mydata->fatsize) { case 32: bufnum = entry / FAT32BUFSIZE; @@ -552,9 +559,11 @@ set_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, debug("clustnum: %d, startsect: %d\n", clustnum, startsect); - if (disk_write(startsect, size / mydata->sect_size, buffer) < 0) { - debug("Error writing data\n"); - return -1; + if ((size / mydata->sect_size) > 0) { + if (disk_write(startsect, size / mydata->sect_size, buffer) < 0) { + debug("Error writing data\n"); + return -1; + } } if (size % mydata->sect_size) { @@ -653,24 +662,26 @@ static int clear_fatent(fsdata *mydata, __u32 entry) /* * Write at most 'maxsize' bytes from 'buffer' into * the file associated with 'dentptr' - * Return the number of bytes read or -1 on fatal errors. + * Update the number of bytes written in *gotsize and return 0 + * or return -1 on fatal errors. */ static int set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, - unsigned long maxsize) + loff_t maxsize, loff_t *gotsize) { - unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; + loff_t filesize = FAT2CPU32(dentptr->size); unsigned int bytesperclust = mydata->clust_size * mydata->sect_size; __u32 curclust = START(dentptr); __u32 endclust = 0, newclust = 0; - unsigned long actsize; + loff_t actsize; - debug("Filesize: %ld bytes\n", filesize); + *gotsize = 0; + debug("Filesize: %llu bytes\n", filesize); if (maxsize > 0 && filesize > maxsize) filesize = maxsize; - debug("%ld bytes\n", filesize); + debug("%llu bytes\n", filesize); actsize = bytesperclust; endclust = curclust; @@ -685,7 +696,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, if (CHECK_CLUST(newclust, mydata->fatsize)) { debug("curclust: 0x%x\n", newclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } endclust = newclust; actsize += bytesperclust; @@ -699,7 +710,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, } /* set remaining bytes */ - gotsize += (int)actsize; + *gotsize += actsize; filesize -= actsize; buffer += actsize; actsize = filesize; @@ -708,7 +719,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, debug("error: writing cluster\n"); return -1; } - gotsize += actsize; + *gotsize += actsize; /* Mark end of file in FAT */ if (mydata->fatsize == 16) @@ -717,20 +728,20 @@ set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, newclust = 0xfffffff; set_fatent_value(mydata, endclust, newclust); - return gotsize; + return 0; getit: if (set_cluster(mydata, curclust, buffer, (int)actsize) != 0) { debug("error: writing cluster\n"); return -1; } - gotsize += (int)actsize; + *gotsize += actsize; filesize -= actsize; buffer += actsize; if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } actsize = bytesperclust; curclust = endclust = newclust; @@ -759,9 +770,9 @@ static void fill_dentry(fsdata *mydata, dir_entry *dentptr, * exceed the size of the block device * Return -1 when overflow occurs, otherwise return 0 */ -static int check_overflow(fsdata *mydata, __u32 clustnum, unsigned long size) +static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size) { - __u32 startsect, sect_num; + __u32 startsect, sect_num, offset; if (clustnum > 0) { startsect = mydata->data_begin + @@ -770,13 +781,13 @@ static int check_overflow(fsdata *mydata, __u32 clustnum, unsigned long size) startsect = mydata->rootdir_sect; } - sect_num = size / mydata->sect_size; - if (size % mydata->sect_size) + sect_num = div_u64_rem(size, mydata->sect_size, &offset); + + if (offset != 0) sect_num++; if (startsect + sect_num > cur_part_info.start + total_sector) return -1; - return 0; } @@ -879,8 +890,30 @@ static dir_entry *find_directory_entry(fsdata *mydata, int startsect, return dentptr; } + /* + * In FAT16/12, the root dir is locate before data area, shows + * in following: + * ------------------------------------------------------------- + * | Boot | FAT1 & 2 | Root dir | Data (start from cluster #2) | + * ------------------------------------------------------------- + * + * As a result if curclust is in Root dir, it is a negative + * number or 0, 1. + * + */ + if (mydata->fatsize != 32 && (int)curclust <= 1) { + /* Current clust is in root dir, set to next clust */ + curclust++; + if ((int)curclust <= 1) + continue; /* continue to find */ + + /* Reach the end of root dir */ + empty_dentptr = dentptr; + return NULL; + } + curclust = get_fatent_value(mydata, dir_curclust); - if ((curclust >= 0xffffff8) || (curclust >= 0xfff8)) { + if (IS_LAST_CLUST(curclust, mydata->fatsize)) { empty_dentptr = dentptr; return NULL; } @@ -894,8 +927,8 @@ static dir_entry *find_directory_entry(fsdata *mydata, int startsect, return NULL; } -static int do_fat_write(const char *filename, void *buffer, - unsigned long size) +static int do_fat_write(const char *filename, void *buffer, loff_t size, + loff_t *actwrite) { dir_entry *dentptr, *retdent; __u32 startsect; @@ -907,8 +940,8 @@ static int do_fat_write(const char *filename, void *buffer, int cursect; int ret = -1, name_len; char l_filename[VFAT_MAXLEN_BYTES]; - int write_size = size; + *actwrite = size; dir_curclust = 0; if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) { @@ -918,7 +951,7 @@ static int do_fat_write(const char *filename, void *buffer, total_sector = bs.total_sect; if (total_sector == 0) - total_sector = cur_part_info.size; + total_sector = (int)cur_part_info.size; /* cast of lbaint_t */ if (mydata->fatsize == 32) mydata->fatlength = bs.fat32_length; @@ -950,7 +983,7 @@ static int do_fat_write(const char *filename, void *buffer, } mydata->fatbufnum = -1; - mydata->fatbuf = malloc(FATBUFSIZE); + mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE); if (mydata->fatbuf == NULL) { debug("Error: allocating memory\n"); return -1; @@ -986,7 +1019,7 @@ static int do_fat_write(const char *filename, void *buffer, ret = check_overflow(mydata, start_cluster, size); if (ret) { - printf("Error: %ld overflow\n", size); + printf("Error: %llu overflow\n", size); goto exit; } @@ -996,13 +1029,12 @@ static int do_fat_write(const char *filename, void *buffer, goto exit; } - ret = set_contents(mydata, retdent, buffer, size); + ret = set_contents(mydata, retdent, buffer, size, actwrite); if (ret < 0) { printf("Error: writing contents\n"); goto exit; } - write_size = ret; - debug("attempt to write 0x%x bytes\n", write_size); + debug("attempt to write 0x%llx bytes\n", *actwrite); /* Flush fat buffer */ ret = flush_fat_buffer(mydata); @@ -1032,7 +1064,7 @@ static int do_fat_write(const char *filename, void *buffer, ret = check_overflow(mydata, start_cluster, size); if (ret) { - printf("Error: %ld overflow\n", size); + printf("Error: %llu overflow\n", size); goto exit; } @@ -1040,13 +1072,13 @@ static int do_fat_write(const char *filename, void *buffer, fill_dentry(mydata, empty_dentptr, filename, start_cluster, size, 0x20); - ret = set_contents(mydata, empty_dentptr, buffer, size); + ret = set_contents(mydata, empty_dentptr, buffer, size, + actwrite); if (ret < 0) { printf("Error: writing contents\n"); goto exit; } - write_size = ret; - debug("attempt to write 0x%x bytes\n", write_size); + debug("attempt to write 0x%llx bytes\n", *actwrite); /* Flush fat buffer */ ret = flush_fat_buffer(mydata); @@ -1067,11 +1099,17 @@ static int do_fat_write(const char *filename, void *buffer, exit: free(mydata->fatbuf); - return ret < 0 ? ret : write_size; + return ret; } -int file_fat_write(const char *filename, void *buffer, unsigned long maxsize) +int file_fat_write(const char *filename, void *buffer, loff_t offset, + loff_t maxsize, loff_t *actwrite) { + if (offset != 0) { + printf("Error: non zero offset is currently not suported.\n"); + return -1; + } + printf("writing %s\n", filename); - return do_fat_write(filename, buffer, maxsize); + return do_fat_write(filename, buffer, maxsize, actwrite); } diff --git a/fs/fat/file.c b/fs/fat/file.c index d910c46ddb..89706117b9 100644 --- a/fs/fat/file.c +++ b/fs/fat/file.c @@ -162,8 +162,7 @@ file_ls(const char *dir) return filesystems[current_filesystem].ls(arg); } -long -file_read(const char *filename, void *buffer, unsigned long maxsize) +int file_read(const char *filename, void *buffer, int maxsize) { char fullpath[1024]; const char *arg; diff --git a/fs/fdos/Makefile b/fs/fdos/Makefile deleted file mode 100644 index 867c5cadfa..0000000000 --- a/fs/fdos/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Stäubli Faverges - -# Pierre AUBERT p.aubert@staubli.com -# -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)libfdos.o - -AOBJS = -COBJS-$(CONFIG_CMD_FDOS) := fat.o vfat.o dev.o fdos.o fs.o subdir.o - -SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) - -#CPPFLAGS += - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/fs/fdos/dev.c b/fs/fdos/dev.c deleted file mode 100644 index 4c48663e09..0000000000 --- a/fs/fdos/dev.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include "dos.h" -#include "fdos.h" - -#define NB_HEADS 2 -#define NB_TRACKS 80 -#define NB_SECTORS 18 - - -static int lastwhere; - -/*----------------------------------------------------------------------------- - * dev_open -- - *----------------------------------------------------------------------------- - */ -int dev_open (void) -{ - lastwhere = 0; - return (0); -} - -/*----------------------------------------------------------------------------- - * dev_read -- len and where are sectors number - *----------------------------------------------------------------------------- - */ -int dev_read (void *buffer, int where, int len) -{ - PRINTF ("dev_read (len = %d, where = %d)\n", len, where); - - /* Si on ne desire pas lire a la position courante, il faut un seek */ - if (where != lastwhere) { - if (!fdc_fdos_seek (where)) { - PRINTF ("seek error in dev_read"); - lastwhere = -1; - return (-1); - } - } - - if (!fdc_fdos_read (buffer, len)) { - PRINTF ("read error\n"); - lastwhere = -1; - return (-1); - } - lastwhere = where + len; - return (0); -} -/*----------------------------------------------------------------------------- - * check_dev -- verify the diskette format - *----------------------------------------------------------------------------- - */ -int check_dev (BootSector_t *boot, Fs_t *fs) -{ - unsigned int heads, sectors, tracks; - int BootP, Infp0, InfpX, InfTm; - int sect_per_track; - - /* Display Boot header */ - PRINTF ("Jump to boot code 0x%02x 0x%02x 0x%02x\n", - boot -> jump [0], boot -> jump [1], boot -> jump[2]); - PRINTF ("OEM name & version '%*.*s'\n", - BANNER_LG, BANNER_LG, boot -> banner ); - PRINTF ("Bytes per sector hopefully 512 %d\n", - __le16_to_cpu (boot -> secsiz)); - PRINTF ("Cluster size in sectors %d\n", - boot -> clsiz); - PRINTF ("Number of reserved (boot) sectors %d\n", - __le16_to_cpu (boot -> nrsvsect)); - PRINTF ("Number of FAT tables hopefully 2 %d\n", - boot -> nfat); - PRINTF ("Number of directory slots %d\n", - __le16_to_cpu (boot -> dirents)); - PRINTF ("Total sectors on disk %d\n", - __le16_to_cpu (boot -> psect)); - PRINTF ("Media descriptor=first byte of FAT %d\n", - boot -> descr); - PRINTF ("Sectors in FAT %d\n", - __le16_to_cpu (boot -> fatlen)); - PRINTF ("Sectors/track %d\n", - __le16_to_cpu (boot -> nsect)); - PRINTF ("Heads %d\n", - __le16_to_cpu (boot -> nheads)); - PRINTF ("number of hidden sectors %d\n", - __le32_to_cpu (boot -> nhs)); - PRINTF ("big total sectors %d\n", - __le32_to_cpu (boot -> bigsect)); - PRINTF ("physical drive ? %d\n", - boot -> physdrive); - PRINTF ("reserved %d\n", - boot -> reserved); - PRINTF ("dos > 4.0 diskette %d\n", - boot -> dos4); - PRINTF ("serial number %d\n", - __le32_to_cpu (boot -> serial)); - PRINTF ("disk label %*.*s\n", - LABEL_LG, LABEL_LG, boot -> label); - PRINTF ("FAT type %8.8s\n", - boot -> fat_type); - PRINTF ("reserved by 2M %d\n", - boot -> res_2m); - PRINTF ("2M checksum (not used) %d\n", - boot -> CheckSum); - PRINTF ("2MF format version %d\n", - boot -> fmt_2mf); - PRINTF ("1 if write track after format %d\n", - boot -> wt); - PRINTF ("data transfer rate on track 0 %d\n", - boot -> rate_0); - PRINTF ("data transfer rate on track<>0 %d\n", - boot -> rate_any); - PRINTF ("offset to boot program %d\n", - __le16_to_cpu (boot -> BootP)); - PRINTF ("T1: information for track 0 %d\n", - __le16_to_cpu (boot -> Infp0)); - PRINTF ("T2: information for track<>0 %d\n", - __le16_to_cpu (boot -> InfpX)); - PRINTF ("T3: track sectors size table %d\n", - __le16_to_cpu (boot -> InfTm)); - PRINTF ("Format date 0x%04x\n", - __le16_to_cpu (boot -> DateF)); - PRINTF ("Format time 0x%04x\n", - __le16_to_cpu (boot -> TimeF)); - - - /* information is extracted from boot sector */ - heads = __le16_to_cpu (boot -> nheads); - sectors = __le16_to_cpu (boot -> nsect); - fs -> tot_sectors = __le32_to_cpu (boot -> bigsect); - if (__le16_to_cpu (boot -> psect) != 0) { - fs -> tot_sectors = __le16_to_cpu (boot -> psect); - } - - sect_per_track = heads * sectors; - tracks = (fs -> tot_sectors + sect_per_track - 1) / sect_per_track; - - BootP = __le16_to_cpu (boot -> BootP); - Infp0 = __le16_to_cpu (boot -> Infp0); - InfpX = __le16_to_cpu (boot -> InfpX); - InfTm = __le16_to_cpu (boot -> InfTm); - - if (boot -> dos4 == EXTENDED_BOOT && - strncmp( boot->banner,"2M", 2 ) == 0 && - BootP < SZ_STD_SECTOR && - Infp0 < SZ_STD_SECTOR && - InfpX < SZ_STD_SECTOR && - InfTm < SZ_STD_SECTOR && - BootP >= InfTm + 2 && - InfTm >= InfpX && - InfpX >= Infp0 && - Infp0 >= 76 ) { - - return (-1); - } - - if (heads != NB_HEADS || - tracks != NB_TRACKS || - sectors != NB_SECTORS || - __le16_to_cpu (boot -> secsiz) != SZ_STD_SECTOR || - fs -> tot_sectors == 0 || - (fs -> tot_sectors % sectors) != 0) { - return (-1); - } - - return (0); -} diff --git a/fs/fdos/dos.h b/fs/fdos/dos.h deleted file mode 100644 index b0b7d2aa06..0000000000 --- a/fs/fdos/dos.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DOS_H_ -#define _DOS_H_ - -/* Definitions for Dos diskettes */ - -/* General definitions */ -#define SZ_STD_SECTOR 512 /* Standard sector size */ -#define MDIR_SIZE 32 /* Direntry size */ -#define FAT_BITS 12 /* Diskette use 12 bits fat */ - -#define MAX_PATH 128 /* Max size of the MSDOS PATH */ -#define MAX_DIR_SECS 64 /* Taille max d'un repertoire (en */ - /* secteurs) */ -/* Misc. definitions */ -#define DELMARK '\xe5' -#define EXTENDED_BOOT (0x29) -#define MEDIA_STD (0xf0) -#define JUMP_0_1 (0xe9) -#define JUMP_0_2 (0xeb) - -/* Boot size is 256 bytes, but we need to read almost a sector, then - assume bootsize is 512 */ -#define BOOTSIZE 512 - -/* Fat definitions for 12 bits fat */ -#define FAT12_MAX_NB 4086 -#define FAT12_LAST 0x0ff6 -#define FAT12_END 0x0fff - -/* file attributes */ -#define ATTR_READONLY 0x01 -#define ATTR_HIDDEN 0x02 -#define ATTR_SYSTEM 0x04 -#define ATTR_VOLUME 0x08 -#define ATTR_DIRECTORY 0x10 -#define ATTR_ARCHIVE 0x20 -#define ATTR_VSE 0x0f - -/* Name format */ -#define EXTCASE 0x10 -#define BASECASE 0x8 - -/* Definition of the boot sector */ -#define BANNER_LG 8 -#define LABEL_LG 11 - -typedef struct bootsector -{ - unsigned char jump [3]; /* 0 Jump to boot code */ - char banner [BANNER_LG]; /* 3 OEM name & version */ - unsigned short secsiz; /* 11 Bytes per sector hopefully 512 */ - unsigned char clsiz; /* 13 Cluster size in sectors */ - unsigned short nrsvsect; /* 14 Number of reserved (boot) sectors */ - unsigned char nfat; /* 16 Number of FAT tables hopefully 2 */ - unsigned short dirents; /* 17 Number of directory slots */ - unsigned short psect; /* 19 Total sectors on disk */ - unsigned char descr; /* 21 Media descriptor=first byte of FAT */ - unsigned short fatlen; /* 22 Sectors in FAT */ - unsigned short nsect; /* 24 Sectors/track */ - unsigned short nheads; /* 26 Heads */ - unsigned int nhs; /* 28 number of hidden sectors */ - unsigned int bigsect; /* 32 big total sectors */ - unsigned char physdrive; /* 36 physical drive ? */ - unsigned char reserved; /* 37 reserved */ - unsigned char dos4; /* 38 dos > 4.0 diskette */ - unsigned int serial; /* 39 serial number */ - char label [LABEL_LG]; /* 43 disk label */ - char fat_type [8]; /* 54 FAT type */ - unsigned char res_2m; /* 62 reserved by 2M */ - unsigned char CheckSum; /* 63 2M checksum (not used) */ - unsigned char fmt_2mf; /* 64 2MF format version */ - unsigned char wt; /* 65 1 if write track after format */ - unsigned char rate_0; /* 66 data transfer rate on track 0 */ - unsigned char rate_any; /* 67 data transfer rate on track<>0 */ - unsigned short BootP; /* 68 offset to boot program */ - unsigned short Infp0; /* 70 T1: information for track 0 */ - unsigned short InfpX; /* 72 T2: information for track<>0 */ - unsigned short InfTm; /* 74 T3: track sectors size table */ - unsigned short DateF; /* 76 Format date */ - unsigned short TimeF; /* 78 Format time */ - unsigned char junk [BOOTSIZE - 80]; /* 80 remaining data */ -} __attribute__ ((packed)) BootSector_t; - -/* Structure d'une entree de repertoire */ -typedef struct directory { - char name [8]; /* file name */ - char ext [3]; /* file extension */ - unsigned char attr; /* attribute byte */ - unsigned char Case; /* case of short filename */ - unsigned char reserved [9]; /* ?? */ - unsigned char time [2]; /* time stamp */ - unsigned char date [2]; /* date stamp */ - unsigned short start; /* starting cluster number */ - unsigned int size; /* size of the file */ -} __attribute__ ((packed)) Directory_t; - - -#define MAX_VFAT_SUBENTRIES 20 -#define VSE_NAMELEN 13 - -#define VSE1SIZE 5 -#define VSE2SIZE 6 -#define VSE3SIZE 2 - -#define VBUFSIZE ((MAX_VFAT_SUBENTRIES * VSE_NAMELEN) + 1) - -#define MAX_VNAMELEN (255) - -#define VSE_PRESENT 0x01 -#define VSE_LAST 0x40 -#define VSE_MASK 0x1f - -/* Flag used by vfat_lookup */ -#define DO_OPEN 1 -#define ACCEPT_PLAIN 0x20 -#define ACCEPT_DIR 0x10 -#define ACCEPT_LABEL 0x08 -#define SINGLE 2 -#define MATCH_ANY 0x40 - -struct vfat_subentry { - unsigned char id; /* VSE_LAST pour la fin, VSE_MASK */ - /* pour un VSE */ - char text1 [VSE1SIZE * 2]; /* Caracteres encodes sur 16 bits */ - unsigned char attribute; /* 0x0f pour les VFAT */ - unsigned char hash1; /* toujours 0 */ - unsigned char sum; /* Checksum du nom court */ - char text2 [VSE2SIZE * 2]; /* Caracteres encodes sur 16 bits */ - unsigned char sector_l; /* 0 pour les VFAT */ - unsigned char sector_u; /* 0 pour les VFAT */ - char text3 [VSE3SIZE * 2]; /* Caracteres encodes sur 16 bits */ -} __attribute__ ((packed)) ; - -struct vfat_state { - char name [VBUFSIZE]; - int status; /* is now a bit map of 32 bits */ - int subentries; - unsigned char sum; /* no need to remember the sum for each */ - /* entry, it is the same anyways */ -} __attribute__ ((packed)) ; - -/* Conversion macros */ -#define DOS_YEAR(dir) (((dir)->date[1] >> 1) + 1980) -#define DOS_MONTH(dir) (((((dir)->date[1]&0x1) << 3) + ((dir)->date[0] >> 5))) -#define DOS_DAY(dir) ((dir)->date[0] & 0x1f) -#define DOS_HOUR(dir) ((dir)->time[1] >> 3) -#define DOS_MINUTE(dir) (((((dir)->time[1]&0x7) << 3) + ((dir)->time[0] >> 5))) -#define DOS_SEC(dir) (((dir)->time[0] & 0x1f) * 2) - - -#endif diff --git a/fs/fdos/fat.c b/fs/fdos/fat.c deleted file mode 100644 index 408fec7600..0000000000 --- a/fs/fdos/fat.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -/*----------------------------------------------------------------------------- - * fat_decode -- - *----------------------------------------------------------------------------- - */ -unsigned int fat_decode (Fs_t *fs, unsigned int num) -{ - unsigned int start = num * 3 / 2; - unsigned char *address = fs -> fat_buf + start; - - if (num < 2 || start + 1 > (fs -> fat_len * SZ_STD_SECTOR)) - return 1; - - if (num & 1) - return ((address [1] & 0xff) << 4) | ((address [0] & 0xf0 ) >> 4); - else - return ((address [1] & 0xf) << 8) | (address [0] & 0xff ); -} -/*----------------------------------------------------------------------------- - * check_fat -- - *----------------------------------------------------------------------------- - */ -static int check_fat (Fs_t *fs) -{ - int i, f; - - /* Cluster verification */ - for (i = 3 ; i < fs -> num_clus; i++){ - f = fat_decode (fs, i); - if (f < FAT12_LAST && f > fs -> num_clus){ - /* Wrong cluster number detected */ - return (-1); - } - } - return (0); -} -/*----------------------------------------------------------------------------- - * read_one_fat -- - *----------------------------------------------------------------------------- - */ -static int read_one_fat (BootSector_t *boot, Fs_t *fs, int nfat) -{ - if (dev_read (fs -> fat_buf, - (fs -> fat_start + nfat * fs -> fat_len), - fs -> fat_len) < 0) { - return (-1); - } - - if (fs -> fat_buf [0] || fs -> fat_buf [1] || fs -> fat_buf [2]) { - if ((fs -> fat_buf [0] != boot -> descr && - (fs -> fat_buf [0] != 0xf9 || boot -> descr != MEDIA_STD)) || - fs -> fat_buf [0] < MEDIA_STD){ - /* Unknown Media */ - return (-1); - } - if (fs -> fat_buf [1] != 0xff || fs -> fat_buf [2] != 0xff){ - /* FAT doesn't start with good values */ - return (-1); - } - } - - if (fs -> num_clus >= FAT12_MAX_NB) { - /* Too much clusters */ - return (-1); - } - - return check_fat (fs); -} -/*----------------------------------------------------------------------------- - * read_fat -- - *----------------------------------------------------------------------------- - */ -int read_fat (BootSector_t *boot, Fs_t *fs) -{ - unsigned int buflen; - int i; - - /* Allocate Fat Buffer */ - buflen = fs -> fat_len * SZ_STD_SECTOR; - if (fs -> fat_buf) { - free (fs -> fat_buf); - } - - if ((fs -> fat_buf = malloc (buflen)) == NULL) { - return (-1); - } - - /* Try to read each Fat */ - for (i = 0; i< fs -> nb_fat; i++){ - if (read_one_fat (boot, fs, i) == 0) { - /* Fat is OK */ - fs -> num_fat = i; - break; - } - } - - if (i == fs -> nb_fat){ - return (-1); - } - - if (fs -> fat_len > (((fs -> num_clus + 2) * - (FAT_BITS / 4) -1 ) / 2 / - SZ_STD_SECTOR + 1)) { - return (-1); - } - return (0); -} diff --git a/fs/fdos/fdos.c b/fs/fdos/fdos.c deleted file mode 100644 index 4e2f479191..0000000000 --- a/fs/fdos/fdos.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -const char *month [] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"}; - -Fs_t fs; -File_t file; - -/*----------------------------------------------------------------------------- - * dos_open -- - *----------------------------------------------------------------------------- - */ -int dos_open(char *name) -{ - int lg; - int entry; - char *fname; - - /* We need to suppress the " char around the name */ - if (name [0] == '"') { - name ++; - } - lg = strlen (name); - if (name [lg - 1] == '"') { - name [lg - 1] = '\0'; - } - - /* Open file system */ - if (fs_init (&fs) < 0) { - return -1; - } - - /* Init the file descriptor */ - file.name = name; - file.fs = &fs; - - /* find the subdirectory containing the file */ - if (open_subdir (&file) < 0) { - return (-1); - } - - fname = basename (name); - - /* if we try to open root directory */ - if (*fname == '\0') { - file.file = file.subdir; - return (0); - } - - /* find the file in the subdir */ - entry = 0; - if (vfat_lookup (&file.subdir, - file.fs, - &file.file.dir, - &entry, - 0, - fname, - ACCEPT_DIR | ACCEPT_PLAIN | SINGLE | DO_OPEN, - 0, - &file.file) != 0) { - /* File not found */ - printf ("File not found\n"); - return (-1); - } - - return 0; -} - -/*----------------------------------------------------------------------------- - * dos_read -- - *----------------------------------------------------------------------------- - */ -int dos_read (ulong addr) -{ - int read = 0, nb; - - /* Try to boot a directory ? */ - if (file.file.dir.attr & (ATTR_DIRECTORY | ATTR_VOLUME)) { - printf ("Unable to boot %s !!\n", file.name); - return (-1); - } - while (read < file.file.FileSize) { - PRINTF ("read_file (%ld)\n", (file.file.FileSize - read)); - nb = read_file (&fs, - &file.file, - (char *)addr + read, - read, - (file.file.FileSize - read)); - PRINTF ("read_file -> %d\n", nb); - if (nb < 0) { - printf ("read error\n"); - return (-1); - } - read += nb; - } - return (read); -} -/*----------------------------------------------------------------------------- - * dos_dir -- - *----------------------------------------------------------------------------- - */ -int dos_dir (void) -{ - int entry; - Directory_t dir; - char *name; - - - if ((file.file.dir.attr & ATTR_DIRECTORY) == 0) { - printf ("%s: not a directory !!\n", file.name); - return (1); - } - entry = 0; - if ((name = malloc (MAX_VNAMELEN + 1)) == NULL) { - PRINTF ("Allcation error\n"); - return (1); - } - - while (vfat_lookup (&file.file, - file.fs, - &dir, - &entry, - 0, - NULL, - ACCEPT_DIR | ACCEPT_PLAIN | MATCH_ANY, - name, - NULL) == 0) { - /* Display file info */ - printf ("%3.3s %9d %s %02d %04d %02d:%02d:%02d %s\n", - (dir.attr & ATTR_DIRECTORY) ? "dir" : " ", - __le32_to_cpu (dir.size), - month [DOS_MONTH (&dir) - 1], - DOS_DAY (&dir), - DOS_YEAR (&dir), - DOS_HOUR (&dir), - DOS_MINUTE (&dir), - DOS_SEC (&dir), - name); - - } - free (name); - return (0); -} diff --git a/fs/fdos/fdos.h b/fs/fdos/fdos.h deleted file mode 100644 index 2d8fe9d13d..0000000000 --- a/fs/fdos/fdos.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FDOS_H_ -#define _FDOS_H_ - - -#undef FDOS_DEBUG - -#ifdef FDOS_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* Data structure describing media */ -typedef struct fs -{ - unsigned long tot_sectors; - - int cluster_size; - int num_clus; - - int fat_start; - int fat_len; - int nb_fat; - int num_fat; - - int dir_start; - int dir_len; - - unsigned char *fat_buf; - -} Fs_t; - -/* Data structure describing one file system slot */ -typedef struct slot { - int (*map) (struct fs *fs, - struct slot *file, - int where, - int *len); - unsigned long FileSize; - - unsigned short int FirstAbsCluNr; - unsigned short int PreviousAbsCluNr; - unsigned short int PreviousRelCluNr; - - Directory_t dir; -} Slot_t; - -typedef struct file { - char *name; - int Case; - Fs_t *fs; - Slot_t subdir; - Slot_t file; -} File_t; - - -/* dev.c */ -int dev_read (void *buffer, int where, int len); -int dev_open (void); -int check_dev (BootSector_t *boot, Fs_t *fs); - -/* fat.c */ -unsigned int fat_decode (Fs_t *fs, unsigned int num); -int read_fat (BootSector_t *boot, Fs_t *fs); - -/* vfat.c */ -int vfat_lookup (Slot_t *dir, - Fs_t *fs, - Directory_t *dirent, - int *entry, - int *vfat_start, - char *filename, - int flags, - char *outname, - Slot_t *file); - -/* subdir.c */ -char *basename (char *name); -int open_subdir (File_t *desc); -int open_file (Slot_t *file, Directory_t *dir); -int read_file (Fs_t *fs, - Slot_t *file, - char *buf, - int where, - int len); -void init_subdir (void); - -/* fs.c */ -int fs_init (Fs_t *fs); - - -#endif diff --git a/fs/fdos/fs.c b/fs/fdos/fs.c deleted file mode 100644 index 39d3eae20d..0000000000 --- a/fs/fdos/fs.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - - -/*----------------------------------------------------------------------------- - * fill_fs -- Read info on file system - *----------------------------------------------------------------------------- - */ -static int fill_fs (BootSector_t *boot, Fs_t *fs) -{ - - fs -> fat_start = __le16_to_cpu (boot -> nrsvsect); - fs -> fat_len = __le16_to_cpu (boot -> fatlen); - fs -> nb_fat = boot -> nfat; - - fs -> dir_start = fs -> fat_start + fs -> nb_fat * fs -> fat_len; - fs -> dir_len = __le16_to_cpu (boot -> dirents) * MDIR_SIZE / SZ_STD_SECTOR; - fs -> cluster_size = boot -> clsiz; - fs -> num_clus = (fs -> tot_sectors - fs -> dir_start - fs -> dir_len) / fs -> cluster_size; - - return (0); -} - -/*----------------------------------------------------------------------------- - * fs_init -- - *----------------------------------------------------------------------------- - */ -int fs_init (Fs_t *fs) -{ - BootSector_t *boot; - - /* Initialize physical device */ - if (dev_open () < 0) { - PRINTF ("Unable to initialize the fdc\n"); - return (-1); - } - init_subdir (); - - /* Allocate space for read the boot sector */ - if ((boot = (BootSector_t *)malloc (sizeof (BootSector_t))) == NULL) { - PRINTF ("Unable to allocate space for boot sector\n"); - return (-1); - } - - /* read boot sector */ - if (dev_read (boot, 0, 1)){ - PRINTF ("Error during boot sector read\n"); - free (boot); - return (-1); - } - - /* we verify it'a a DOS diskette */ - if (boot -> jump [0] != JUMP_0_1 && boot -> jump [0] != JUMP_0_2) { - PRINTF ("Not a DOS diskette\n"); - free (boot); - return (-1); - } - - if (boot -> descr < MEDIA_STD) { - /* We handle only recent medias (type F0) */ - PRINTF ("unrecognized diskette type\n"); - free (boot); - return (-1); - } - - if (check_dev (boot, fs) < 0) { - PRINTF ("Bad diskette\n"); - free (boot); - return (-1); - } - - if (fill_fs (boot, fs) < 0) { - free (boot); - - return (-1); - } - - /* Read FAT */ - if (read_fat (boot, fs) < 0) { - free (boot); - return (-1); - } - - free (boot); - return (0); -} diff --git a/fs/fdos/subdir.c b/fs/fdos/subdir.c deleted file mode 100644 index 97f6fb7102..0000000000 --- a/fs/fdos/subdir.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - -static int cache_sect; -static unsigned char cache [SZ_STD_SECTOR]; - - -#define min(x,y) ((x)<(y)?(x):(y)) - -static int descend (Slot_t *parent, - Fs_t *fs, - char *path); - -/*----------------------------------------------------------------------------- - * init_subdir -- - *----------------------------------------------------------------------------- - */ -void init_subdir (void) -{ - cache_sect = -1; -} -/*----------------------------------------------------------------------------- - * basename -- - *----------------------------------------------------------------------------- - */ -char *basename (char *name) -{ - register char *cptr; - - if (!name || !*name) { - return (""); - } - - for (cptr= name; *cptr++; ); - while (--cptr >= name) { - if (*cptr == '/') { - return (cptr + 1); - } - } - return(name); -} -/*----------------------------------------------------------------------------- - * root_map -- - *----------------------------------------------------------------------------- - */ -static int root_map (Fs_t *fs, Slot_t *file, int where, int *len) -{ - *len = min (*len, fs -> dir_len * SZ_STD_SECTOR - where); - if (*len < 0 ) { - *len = 0; - return (-1); - } - return fs -> dir_start * SZ_STD_SECTOR + where; -} -/*----------------------------------------------------------------------------- - * normal_map -- - *----------------------------------------------------------------------------- - */ -static int normal_map (Fs_t *fs, Slot_t *file, int where, int *len) -{ - int offset; - int NrClu; - unsigned short RelCluNr; - unsigned short CurCluNr; - unsigned short NewCluNr; - unsigned short AbsCluNr; - int clus_size; - - clus_size = fs -> cluster_size * SZ_STD_SECTOR; - offset = where % clus_size; - - *len = min (*len, file -> FileSize - where); - - if (*len < 0 ) { - *len = 0; - return (0); - } - - if (file -> FirstAbsCluNr < 2){ - *len = 0; - return (0); - } - - RelCluNr = where / clus_size; - - if (RelCluNr >= file -> PreviousRelCluNr){ - CurCluNr = file -> PreviousRelCluNr; - AbsCluNr = file -> PreviousAbsCluNr; - } else { - CurCluNr = 0; - AbsCluNr = file -> FirstAbsCluNr; - } - - - NrClu = (offset + *len - 1) / clus_size; - while (CurCluNr <= RelCluNr + NrClu) { - if (CurCluNr == RelCluNr){ - /* we have reached the beginning of our zone. Save - * coordinates */ - file -> PreviousRelCluNr = RelCluNr; - file -> PreviousAbsCluNr = AbsCluNr; - } - NewCluNr = fat_decode (fs, AbsCluNr); - if (NewCluNr == 1 || NewCluNr == 0) { - PRINTF("Fat problem while decoding %d %x\n", - AbsCluNr, NewCluNr); - return (-1); - } - if (CurCluNr == RelCluNr + NrClu) { - break; - } - - if (CurCluNr < RelCluNr && NewCluNr == FAT12_END) { - *len = 0; - return 0; - } - - if (CurCluNr >= RelCluNr && NewCluNr != AbsCluNr + 1) - break; - CurCluNr++; - AbsCluNr = NewCluNr; - } - - *len = min (*len, (1 + CurCluNr - RelCluNr) * clus_size - offset); - - return (((file -> PreviousAbsCluNr - 2) * fs -> cluster_size + - fs -> dir_start + fs -> dir_len) * - SZ_STD_SECTOR + offset); -} -/*----------------------------------------------------------------------------- - * open_subdir -- open the subdir containing the file - *----------------------------------------------------------------------------- - */ -int open_subdir (File_t *desc) -{ - char *pathname; - char *tmp, *s, *path; - char terminator; - - if ((pathname = (char *)malloc (MAX_PATH)) == NULL) { - return (-1); - } - - strcpy (pathname, desc -> name); - - /* Suppress file name */ - tmp = basename (pathname); - *tmp = '\0'; - - /* root directory init */ - desc -> subdir.FirstAbsCluNr = 0; - desc -> subdir.FileSize = -1; - desc -> subdir.map = root_map; - desc -> subdir.dir.attr = ATTR_DIRECTORY; - - tmp = pathname; - for (s = tmp; ; ++s) { - if (*s == '/' || *s == '\0') { - path = tmp; - terminator = *s; - *s = '\0'; - if (s != tmp && strcmp (path,".")) { - if (descend (&desc -> subdir, desc -> fs, path) < 0) { - free (pathname); - return (-1); - } - } - if (terminator == 0) { - break; - } - tmp = s + 1; - } - } - free (pathname); - return (0); -} -/*----------------------------------------------------------------------------- - * descend -- - *----------------------------------------------------------------------------- - */ -static int descend (Slot_t *parent, - Fs_t *fs, - char *path) -{ - int entry; - Slot_t SubDir; - - if(path[0] == '\0' || strcmp (path, ".") == 0) { - return (0); - } - - - entry = 0; - if (vfat_lookup (parent, - fs, - &(SubDir.dir), - &entry, - 0, - path, - ACCEPT_DIR | SINGLE | DO_OPEN, - 0, - &SubDir) == 0) { - *parent = SubDir; - return (0); - } - - if (strcmp(path, "..") == 0) { - parent -> FileSize = -1; - parent -> FirstAbsCluNr = 0; - parent -> map = root_map; - return (0); - } - return (-1); -} -/*----------------------------------------------------------------------------- - * open_file -- - *----------------------------------------------------------------------------- - */ -int open_file (Slot_t *file, Directory_t *dir) -{ - int first; - unsigned long size; - - first = __le16_to_cpu (dir -> start); - - if(first == 0 && - (dir -> attr & ATTR_DIRECTORY) != 0) { - file -> FirstAbsCluNr = 0; - file -> FileSize = -1; - file -> map = root_map; - return (0); - } - - if ((dir -> attr & ATTR_DIRECTORY) != 0) { - size = (1UL << 31) - 1; - } - else { - size = __le32_to_cpu (dir -> size); - } - - file -> map = normal_map; - file -> FirstAbsCluNr = first; - file -> PreviousRelCluNr = 0xffff; - file -> FileSize = size; - return (0); -} -/*----------------------------------------------------------------------------- - * read_file -- - *----------------------------------------------------------------------------- - */ -int read_file (Fs_t *fs, - Slot_t *file, - char *buf, - int where, - int len) -{ - int pos; - int read, nb, sect, offset; - - pos = file -> map (fs, file, where, &len); - if (pos < 0) { - return -1; - } - if (len == 0) { - return (0); - } - - /* Compute sector number */ - sect = pos / SZ_STD_SECTOR; - offset = pos % SZ_STD_SECTOR; - read = 0; - - if (offset) { - /* Read doesn't start at the sector beginning. We need to use our */ - /* cache */ - if (sect != cache_sect) { - if (dev_read (cache, sect, 1) < 0) { - return (-1); - } - cache_sect = sect; - } - nb = min (len, SZ_STD_SECTOR - offset); - - memcpy (buf, cache + offset, nb); - read += nb; - len -= nb; - sect += 1; - } - - if (len > SZ_STD_SECTOR) { - nb = (len - 1) / SZ_STD_SECTOR; - if (dev_read (buf + read, sect, nb) < 0) { - return ((read) ? read : -1); - } - /* update sector position */ - sect += nb; - - /* Update byte position */ - nb *= SZ_STD_SECTOR; - read += nb; - len -= nb; - } - - if (len) { - if (sect != cache_sect) { - if (dev_read (cache, sect, 1) < 0) { - return ((read) ? read : -1); - cache_sect = -1; - } - cache_sect = sect; - } - - memcpy (buf + read, cache, len); - read += len; - } - return (read); -} diff --git a/fs/fdos/vfat.c b/fs/fdos/vfat.c deleted file mode 100644 index 2b87d0f5a7..0000000000 --- a/fs/fdos/vfat.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "dos.h" -#include "fdos.h" - -static int dir_read (Fs_t *fs, - Slot_t *dir, - Directory_t *dirent, - int num, - struct vfat_state *v); - -static int unicode_read (char *in, char *out, int num); -static int match (const char *s, const char *p); -static unsigned char sum_shortname (char *name); -static int check_vfat (struct vfat_state *v, Directory_t *dir); -static char *conv_name (char *name, char *ext, char Case, char *ans); - - -/*----------------------------------------------------------------------------- - * clear_vfat -- - *----------------------------------------------------------------------------- - */ -static void clear_vfat (struct vfat_state *v) -{ - v -> subentries = 0; - v -> status = 0; -} - -/*----------------------------------------------------------------------------- - * vfat_lookup -- - *----------------------------------------------------------------------------- - */ -int vfat_lookup (Slot_t *dir, - Fs_t *fs, - Directory_t *dirent, - int *entry, - int *vfat_start, - char *filename, - int flags, - char *outname, - Slot_t *file) -{ - int found; - struct vfat_state vfat; - char newfile [VSE_NAMELEN]; - int vfat_present = 0; - - if (*entry == -1) { - return -1; - } - - found = 0; - clear_vfat (&vfat); - while (1) { - if (dir_read (fs, dir, dirent, *entry, &vfat) < 0) { - if (vfat_start) { - *vfat_start = *entry; - } - break; - } - (*entry)++; - - /* Empty slot */ - if (dirent -> name[0] == '\0'){ - if (vfat_start == 0) { - break; - } - continue; - } - - if (dirent -> attr == ATTR_VSE) { - /* VSE entry, continue */ - continue; - } - if ( (dirent -> name [0] == DELMARK) || - ((dirent -> attr & ATTR_DIRECTORY) != 0 && - (flags & ACCEPT_DIR) == 0) || - ((dirent -> attr & ATTR_VOLUME) != 0 && - (flags & ACCEPT_LABEL) == 0) || - (((dirent -> attr & (ATTR_DIRECTORY | ATTR_VOLUME)) == 0) && - (flags & ACCEPT_PLAIN) == 0)) { - clear_vfat (&vfat); - continue; - } - - vfat_present = check_vfat (&vfat, dirent); - if (vfat_start) { - *vfat_start = *entry - 1; - if (vfat_present) { - *vfat_start -= vfat.subentries; - } - } - - if (dirent -> attr & ATTR_VOLUME) { - strncpy (newfile, dirent -> name, 8); - newfile [8] = '\0'; - strncat (newfile, dirent -> ext, 3); - newfile [11] = '\0'; - } - else { - conv_name (dirent -> name, dirent -> ext, dirent -> Case, newfile); - } - - if (flags & MATCH_ANY) { - found = 1; - break; - } - - if ((vfat_present && match (vfat.name, filename)) || - (match (newfile, filename))) { - found = 1; - break; - } - clear_vfat (&vfat); - } - - if (found) { - if ((flags & DO_OPEN) && file) { - if (open_file (file, dirent) < 0) { - return (-1); - } - } - if (outname) { - if (vfat_present) { - strcpy (outname, vfat.name); - } - else { - strcpy (outname, newfile); - } - } - return (0); /* File found */ - } else { - *entry = -1; - return -1; /* File not found */ - } -} - -/*----------------------------------------------------------------------------- - * dir_read -- Read one directory entry - *----------------------------------------------------------------------------- - */ -static int dir_read (Fs_t *fs, - Slot_t *dir, - Directory_t *dirent, - int num, - struct vfat_state *v) -{ - - /* read the directory entry */ - if (read_file (fs, - dir, - (char *)dirent, - num * MDIR_SIZE, - MDIR_SIZE) != MDIR_SIZE) { - return (-1); - } - - if (v && (dirent -> attr == ATTR_VSE)) { - struct vfat_subentry *vse; - unsigned char id, last_flag; - char *c; - - vse = (struct vfat_subentry *) dirent; - id = vse -> id & VSE_MASK; - last_flag = (vse -> id & VSE_LAST); - if (id > MAX_VFAT_SUBENTRIES) { - /* Invalid VSE entry */ - return (-1); - } - - - /* Decode VSE */ - if(v -> sum != vse -> sum) { - clear_vfat (v); - v -> sum = vse -> sum; - } - - - v -> status |= 1 << (id - 1); - if (last_flag) { - v -> subentries = id; - } - - c = &(v -> name [VSE_NAMELEN * (id - 1)]); - c += unicode_read (vse->text1, c, VSE1SIZE); - c += unicode_read (vse->text2, c, VSE2SIZE); - c += unicode_read (vse->text3, c, VSE3SIZE); - - if (last_flag) { - *c = '\0'; /* Null terminate long name */ - } - - } - return (0); -} - -/*----------------------------------------------------------------------------- - * unicode_read -- - *----------------------------------------------------------------------------- - */ -static int unicode_read (char *in, char *out, int num) -{ - int j; - - for (j = 0; j < num; ++j) { - if (in [1]) - *out = '_'; - else - *out = in [0]; - out ++; - in += 2; - } - return num; -} - -/*----------------------------------------------------------------------------- - * match -- - *----------------------------------------------------------------------------- - */ -static int match (const char *s, const char *p) -{ - - for (; *p != '\0'; ) { - if (toupper (*s) != toupper (*p)) { - return (0); - } - p++; - s++; - } - - if (*s != '\0') { - return (0); - } - else { - return (1); - } -} -/*----------------------------------------------------------------------------- - * sum_shortname -- - *----------------------------------------------------------------------------- - */ -static unsigned char sum_shortname (char *name) -{ - unsigned char sum; - int j; - - for (j = sum = 0; j < 11; ++j) { - sum = ((sum & 1) ? 0x80 : 0) + (sum >> 1) + - (name [j] ? name [j] : ' '); - } - return (sum); -} -/*----------------------------------------------------------------------------- - * check_vfat -- - * Return 1 if long name is valid, 0 else - *----------------------------------------------------------------------------- - */ -static int check_vfat (struct vfat_state *v, Directory_t *dir) -{ - char name[12]; - - if (v -> subentries == 0) { - return 0; - } - - strncpy (name, dir -> name, 8); - strncpy (name + 8, dir -> ext, 3); - name [11] = '\0'; - - if (v -> sum != sum_shortname (name)) { - return 0; - } - - if( (v -> status & ((1 << v -> subentries) - 1)) != - (1 << v -> subentries) - 1) { - return 0; - } - v->name [VSE_NAMELEN * v -> subentries] = 0; - - return 1; -} -/*----------------------------------------------------------------------------- - * conv_name -- - *----------------------------------------------------------------------------- - */ -static char *conv_name (char *name, char *ext, char Case, char *ans) -{ - char tname [9], text [4]; - int i; - - i = 0; - while (i < 8 && name [i] != ' ' && name [i] != '\0') { - tname [i] = name [i]; - i++; - } - tname [i] = '\0'; - - if (Case & BASECASE) { - for (i = 0; i < 8 && tname [i]; i++) { - tname [i] = tolower (tname [i]); - } - } - - i = 0; - while (i < 3 && ext [i] != ' ' && ext [i] != '\0') { - text [i] = ext [i]; - i++; - } - text [i] = '\0'; - - if (Case & EXTCASE){ - for (i = 0; i < 3 && text [i]; i++) { - text [i] = tolower (text [i]); - } - } - - if (*text) { - strcpy (ans, tname); - strcat (ans, "."); - strcat (ans, text); - } - else { - strcpy(ans, tname); - } - return (ans); -} diff --git a/fs/fs.c b/fs/fs.c index 99e516a44d..483273fe20 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -22,6 +23,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -41,14 +44,26 @@ static inline int fs_ls_unsupported(const char *dirname) return -1; } +static inline int fs_exists_unsupported(const char *filename) +{ + return 0; +} + +static inline int fs_size_unsupported(const char *filename, loff_t *size) +{ + return -1; +} + static inline int fs_read_unsupported(const char *filename, void *buf, - int offset, int len) + loff_t offset, loff_t len, + loff_t *actread) { return -1; } static inline int fs_write_unsupported(const char *filename, void *buf, - int offset, int len) + loff_t offset, loff_t len, + loff_t *actwrite) { return -1; } @@ -57,52 +72,102 @@ static inline void fs_close_unsupported(void) { } +static inline int fs_uuid_unsupported(char *uuid_str) +{ + return -1; +} + struct fstype_info { int fstype; + char *name; + /* + * Is it legal to pass NULL as .probe()'s fs_dev_desc parameter? This + * should be false in most cases. For "virtual" filesystems which + * aren't based on a U-Boot block device (e.g. sandbox), this can be + * set to true. This should also be true for the dumm entry at the end + * of fstypes[], since that is essentially a "virtual" (non-existent) + * filesystem. + */ + bool null_dev_desc_ok; int (*probe)(block_dev_desc_t *fs_dev_desc, disk_partition_t *fs_partition); int (*ls)(const char *dirname); - int (*read)(const char *filename, void *buf, int offset, int len); - int (*write)(const char *filename, void *buf, int offset, int len); + int (*exists)(const char *filename); + int (*size)(const char *filename, loff_t *size); + int (*read)(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actread); + int (*write)(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite); void (*close)(void); + int (*uuid)(char *uuid_str); }; static struct fstype_info fstypes[] = { #ifdef CONFIG_FS_FAT { .fstype = FS_TYPE_FAT, + .name = "fat", + .null_dev_desc_ok = false, .probe = fat_set_blk_dev, .close = fat_close, .ls = file_fat_ls, + .exists = fat_exists, + .size = fat_size, .read = fat_read_file, +#ifdef CONFIG_FAT_WRITE + .write = file_fat_write, +#else + .write = fs_write_unsupported, +#endif + .uuid = fs_uuid_unsupported, }, #endif #ifdef CONFIG_FS_EXT4 { .fstype = FS_TYPE_EXT, + .name = "ext4", + .null_dev_desc_ok = false, .probe = ext4fs_probe, .close = ext4fs_close, .ls = ext4fs_ls, + .exists = ext4fs_exists, + .size = ext4fs_size, .read = ext4_read_file, +#ifdef CONFIG_CMD_EXT4_WRITE + .write = ext4_write_file, +#else + .write = fs_write_unsupported, +#endif + .uuid = ext4fs_uuid, }, #endif #ifdef CONFIG_SANDBOX { .fstype = FS_TYPE_SANDBOX, + .name = "sandbox", + .null_dev_desc_ok = true, .probe = sandbox_fs_set_blk_dev, .close = sandbox_fs_close, .ls = sandbox_fs_ls, + .exists = sandbox_fs_exists, + .size = sandbox_fs_size, .read = fs_read_sandbox, .write = fs_write_sandbox, + .uuid = fs_uuid_unsupported, }, #endif { .fstype = FS_TYPE_ANY, + .name = "unsupported", + .null_dev_desc_ok = true, .probe = fs_probe_unsupported, .close = fs_close_unsupported, .ls = fs_ls_unsupported, + .exists = fs_exists_unsupported, + .size = fs_size_unsupported, .read = fs_read_unsupported, .write = fs_write_unsupported, + .uuid = fs_uuid_unsupported, }, }; @@ -130,6 +195,7 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) if (!relocated) { for (i = 0, info = fstypes; i < ARRAY_SIZE(fstypes); i++, info++) { + info->name += gd->reloc_off; info->probe += gd->reloc_off; info->close += gd->reloc_off; info->ls += gd->reloc_off; @@ -150,6 +216,9 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) fstype != info->fstype) continue; + if (!fs_dev_desc && !info->null_dev_desc_ok) + continue; + if (!info->probe(fs_dev_desc, &fs_partition)) { fs_type = info->fstype; return 0; @@ -168,6 +237,13 @@ static void fs_close(void) fs_type = FS_TYPE_ANY; } +int fs_uuid(char *uuid_str) +{ + struct fstype_info *info = fs_get_info(fs_type); + + return info->uuid(uuid_str); +} + int fs_ls(const char *dirname) { int ret; @@ -182,7 +258,34 @@ int fs_ls(const char *dirname) return ret; } -int fs_read(const char *filename, ulong addr, int offset, int len) +int fs_exists(const char *filename) +{ + int ret; + + struct fstype_info *info = fs_get_info(fs_type); + + ret = info->exists(filename); + + fs_close(); + + return ret; +} + +int fs_size(const char *filename, loff_t *size) +{ + int ret; + + struct fstype_info *info = fs_get_info(fs_type); + + ret = info->size(filename, size); + + fs_close(); + + return ret; +} + +int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actread) { struct fstype_info *info = fs_get_info(fs_type); void *buf; @@ -193,11 +296,11 @@ int fs_read(const char *filename, ulong addr, int offset, int len) * means read the whole file. */ buf = map_sysmem(addr, len); - ret = info->read(filename, buf, offset, len); + ret = info->read(filename, buf, offset, len, actread); unmap_sysmem(buf); /* If we requested a specific number of bytes, check we got it */ - if (ret >= 0 && len && ret != len) { + if (ret == 0 && len && *actread != len) { printf("** Unable to read file %s **\n", filename); ret = -1; } @@ -206,22 +309,18 @@ int fs_read(const char *filename, ulong addr, int offset, int len) return ret; } -int fs_write(const char *filename, ulong addr, int offset, int len) +int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actwrite) { struct fstype_info *info = fs_get_info(fs_type); void *buf; int ret; - /* - * We don't actually know how many bytes are being read, since len==0 - * means read the whole file. - */ buf = map_sysmem(addr, len); - ret = info->write(filename, buf, offset, len); + ret = info->write(filename, buf, offset, len, actwrite); unmap_sysmem(buf); - /* If we requested a specific number of bytes, check we got it */ - if (ret >= 0 && len && ret != len) { + if (ret < 0 && len != *actwrite) { printf("** Unable to write file %s **\n", filename); ret = -1; } @@ -230,16 +329,37 @@ int fs_write(const char *filename, ulong addr, int offset, int len) return ret; } +int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype) +{ + loff_t size; + + if (argc != 4) + return CMD_RET_USAGE; + + if (fs_set_blk_dev(argv[1], argv[2], fstype)) + return 1; + + if (fs_size(argv[3], &size) < 0) + return CMD_RET_FAILURE; + + setenv_hex("filesize", size); + + return 0; +} + int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - int fstype, int cmdline_base) + int fstype) { unsigned long addr; const char *addr_str; const char *filename; - unsigned long bytes; - unsigned long pos; - int len_read; + loff_t bytes; + loff_t pos; + loff_t len_read; + int ret; unsigned long time; + char *ep; if (argc < 2) return CMD_RET_USAGE; @@ -250,7 +370,9 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], return 1; if (argc >= 4) { - addr = simple_strtoul(argv[3], NULL, cmdline_base); + addr = simple_strtoul(argv[3], &ep, 16); + if (ep == argv[3] || *ep != '\0') + return CMD_RET_USAGE; } else { addr_str = getenv("loadaddr"); if (addr_str != NULL) @@ -268,24 +390,24 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], } } if (argc >= 6) - bytes = simple_strtoul(argv[5], NULL, cmdline_base); + bytes = simple_strtoul(argv[5], NULL, 16); else bytes = 0; if (argc >= 7) - pos = simple_strtoul(argv[6], NULL, cmdline_base); + pos = simple_strtoul(argv[6], NULL, 16); else pos = 0; time = get_timer(0); - len_read = fs_read(filename, addr, pos, bytes); + ret = fs_read(filename, addr, pos, bytes, &len_read); time = get_timer(time); - if (len_read <= 0) + if (ret < 0) return 1; - printf("%d bytes read in %lu ms", len_read, time); + printf("%llu bytes read in %lu ms", len_read, time); if (time > 0) { puts(" ("); - print_size(len_read / time * 1000, "/s"); + print_size(div_u64(len_read, time) * 1000, "/s"); puts(")"); } puts("\n"); @@ -312,14 +434,24 @@ int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], return 0; } +int file_exists(const char *dev_type, const char *dev_part, const char *file, + int fstype) +{ + if (fs_set_blk_dev(dev_type, dev_part, fstype)) + return 0; + + return fs_exists(file); +} + int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - int fstype, int cmdline_base) + int fstype) { unsigned long addr; const char *filename; - unsigned long bytes; - unsigned long pos; - int len; + loff_t bytes; + loff_t pos; + loff_t len; + int ret; unsigned long time; if (argc < 6 || argc > 7) @@ -328,27 +460,73 @@ int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], if (fs_set_blk_dev(argv[1], argv[2], fstype)) return 1; - filename = argv[3]; - addr = simple_strtoul(argv[4], NULL, cmdline_base); - bytes = simple_strtoul(argv[5], NULL, cmdline_base); + addr = simple_strtoul(argv[3], NULL, 16); + filename = argv[4]; + bytes = simple_strtoul(argv[5], NULL, 16); if (argc >= 7) - pos = simple_strtoul(argv[6], NULL, cmdline_base); + pos = simple_strtoul(argv[6], NULL, 16); else pos = 0; time = get_timer(0); - len = fs_write(filename, addr, pos, bytes); + ret = fs_write(filename, addr, pos, bytes, &len); time = get_timer(time); - if (len <= 0) + if (ret < 0) return 1; - printf("%d bytes written in %lu ms", len, time); + printf("%llu bytes written in %lu ms", len, time); if (time > 0) { puts(" ("); - print_size(len / time * 1000, "/s"); + print_size(div_u64(len, time) * 1000, "/s"); puts(")"); } puts("\n"); return 0; } + +int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype) +{ + int ret; + char uuid[37]; + memset(uuid, 0, sizeof(uuid)); + + if (argc < 3 || argc > 4) + return CMD_RET_USAGE; + + if (fs_set_blk_dev(argv[1], argv[2], fstype)) + return 1; + + ret = fs_uuid(uuid); + if (ret) + return CMD_RET_FAILURE; + + if (argc == 4) + setenv(argv[3], uuid); + else + printf("%s\n", uuid); + + return CMD_RET_SUCCESS; +} + +int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fstype_info *info; + + if (argc < 3 || argc > 4) + return CMD_RET_USAGE; + + if (fs_set_blk_dev(argv[1], argv[2], FS_TYPE_ANY)) + return 1; + + info = fs_get_info(fs_type); + + if (argc == 4) + setenv(argv[3], info->name); + else + printf("%s\n", info->name); + + return CMD_RET_SUCCESS; +} + diff --git a/fs/jffs2/Kconfig b/fs/jffs2/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile index a11ca32e81..4cb0600cf9 100644 --- a/fs/jffs2/Makefile +++ b/fs/jffs2/Makefile @@ -5,37 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libjffs2.o - -AOBJS = -ifdef CONFIG_CMD_JFFS2 -COBJS-$(CONFIG_JFFS2_LZO) += compr_lzo.o -COBJS-y += compr_rtime.o -COBJS-y += compr_rubin.o -COBJS-y += compr_zlib.o -COBJS-y += jffs2_1pass.o -COBJS-y += mini_inflate.o -endif - -COBJS := $(COBJS-y) -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) - -#CPPFLAGS += - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_JFFS2_LZO) += compr_lzo.o +obj-y += compr_rtime.o +obj-y += compr_rubin.o +obj-y += compr_zlib.o +obj-y += jffs2_1pass.o +obj-y += mini_inflate.o diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index c856983ef4..b1d6470219 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -114,6 +114,7 @@ #include #include #include +#include #include #include #include @@ -723,7 +724,7 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest) for (b = pL->frag.listHead; b != NULL; b = b->next) { jNode = (struct jffs2_raw_inode *) get_node_mem(b->offset, pL->readbuf); - if ((inode == jNode->ino)) { + if (inode == jNode->ino) { #if 0 putLabeledWord("\r\n\r\nread_inode: totlen = ", jNode->totlen); putLabeledWord("read_inode: inode = ", jNode->ino); @@ -1438,7 +1439,7 @@ jffs2_1pass_build_lists(struct part_info * part) { struct b_lists *pL; struct jffs2_unknown_node *node; - u32 nr_sectors = part->size/part->sector_size; + u32 nr_sectors; u32 i; u32 counter4 = 0; u32 counterF = 0; @@ -1447,6 +1448,7 @@ jffs2_1pass_build_lists(struct part_info * part) u32 buf_size = DEFAULT_EMPTY_SCAN_SIZE; char *buf; + nr_sectors = lldiv(part->size, part->sector_size); /* turn off the lcd. Refreshing the lcd adds 50% overhead to the */ /* jffs2 list building enterprise nope. in newer versions the overhead is */ /* only about 5 %. not enough to inconvenience people for. */ diff --git a/fs/reiserfs/Kconfig b/fs/reiserfs/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/fs/reiserfs/Makefile b/fs/reiserfs/Makefile index d81d71d392..5a692f0ee7 100644 --- a/fs/reiserfs/Makefile +++ b/fs/reiserfs/Makefile @@ -9,28 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libreiserfs.o - -AOBJS = -COBJS-$(CONFIG_CMD_REISER) := reiserfs.o dev.o mode_string.o - -SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) - -#CPPFLAGS += - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := reiserfs.o dev.o mode_string.o diff --git a/fs/sandbox/Makefile b/fs/sandbox/Makefile index df2fc32414..ca238f6d7d 100644 --- a/fs/sandbox/Makefile +++ b/fs/sandbox/Makefile @@ -10,25 +10,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libsandboxfs.o - -COBJS-$(CONFIG_SANDBOX) := sandboxfs.o - -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := sandboxfs.o diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c index dd028da8e3..a920bc0877 100644 --- a/fs/sandbox/sandboxfs.c +++ b/fs/sandbox/sandboxfs.c @@ -13,10 +13,10 @@ int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info) return 0; } -long sandbox_fs_read_at(const char *filename, unsigned long pos, - void *buffer, unsigned long maxsize) +int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread) { - ssize_t size; + loff_t size; int fd, ret; fd = os_open(filename, OS_O_RDONLY); @@ -27,16 +27,31 @@ long sandbox_fs_read_at(const char *filename, unsigned long pos, os_close(fd); return ret; } - if (!maxsize) - maxsize = os_get_filesize(filename); + if (!maxsize) { + ret = os_get_filesize(filename, &size); + if (ret) { + os_close(fd); + return ret; + } + + maxsize = size; + } + size = os_read(fd, buffer, maxsize); os_close(fd); - return size; + if (size < 0) { + ret = -1; + } else { + ret = 0; + *actread = size; + } + + return ret; } -long sandbox_fs_write_at(const char *filename, unsigned long pos, - void *buffer, unsigned long towrite) +int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer, + loff_t towrite, loff_t *actwrite) { ssize_t size; int fd, ret; @@ -52,7 +67,14 @@ long sandbox_fs_write_at(const char *filename, unsigned long pos, size = os_write(fd, buffer, towrite); os_close(fd); - return size; + if (size == -1) { + ret = -1; + } else { + ret = 0; + *actwrite = size; + } + + return ret; } int sandbox_fs_ls(const char *dirname) @@ -72,32 +94,44 @@ int sandbox_fs_ls(const char *dirname) return 0; } +int sandbox_fs_exists(const char *filename) +{ + loff_t size; + int ret; + + ret = os_get_filesize(filename, &size); + return ret == 0; +} + +int sandbox_fs_size(const char *filename, loff_t *size) +{ + return os_get_filesize(filename, size); +} + void sandbox_fs_close(void) { } -int fs_read_sandbox(const char *filename, void *buf, int offset, int len) +int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread) { - int len_read; + int ret; - len_read = sandbox_fs_read_at(filename, offset, buf, len); - if (len_read == -1) { + ret = sandbox_fs_read_at(filename, offset, buf, len, actread); + if (ret) printf("** Unable to read file %s **\n", filename); - return -1; - } - return len_read; + return ret; } -int fs_write_sandbox(const char *filename, void *buf, int offset, int len) +int fs_write_sandbox(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite) { - int len_written; + int ret; - len_written = sandbox_fs_write_at(filename, offset, buf, len); - if (len_written == -1) { + ret = sandbox_fs_write_at(filename, offset, buf, len, actwrite); + if (ret) printf("** Unable to write file %s **\n", filename); - return -1; - } - return len_written; + return ret; } diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile index 47949c14be..8c8c6ac683 100644 --- a/fs/ubifs/Makefile +++ b/fs/ubifs/Makefile @@ -9,31 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libubifs.o - -COBJS-$(CONFIG_CMD_UBIFS) := ubifs.o io.o super.o sb.o master.o lpt.o -COBJS-$(CONFIG_CMD_UBIFS) += lpt_commit.o scan.o lprops.o -COBJS-$(CONFIG_CMD_UBIFS) += tnc.o tnc_misc.o debug.o crc16.o budget.o -COBJS-$(CONFIG_CMD_UBIFS) += log.o orphan.o recovery.o replay.o - -SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -# SEE README.arm-unaligned-accesses -$(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := ubifs.o io.o super.o sb.o master.o lpt.o +obj-y += lpt_commit.o scan.o lprops.o +obj-y += tnc.o tnc_misc.o debug.o crc16.o budget.o +obj-y += log.o orphan.o recovery.o replay.o diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c index 85377ea2a6..c626cbf484 100644 --- a/fs/ubifs/budget.c +++ b/fs/ubifs/budget.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Adrian Hunter * Artem Bityutskiy (Битюцкий Артём) @@ -31,32 +20,170 @@ */ #include "ubifs.h" +#ifndef __UBOOT__ +#include +#else +#include +#endif #include +/* + * When pessimistic budget calculations say that there is no enough space, + * UBIFS starts writing back dirty inodes and pages, doing garbage collection, + * or committing. The below constant defines maximum number of times UBIFS + * repeats the operations. + */ +#define MAX_MKSPC_RETRIES 3 + +/* + * The below constant defines amount of dirty pages which should be written + * back at when trying to shrink the liability. + */ +#define NR_TO_WRITE 16 + +#ifndef __UBOOT__ +/** + * shrink_liability - write-back some dirty pages/inodes. + * @c: UBIFS file-system description object + * @nr_to_write: how many dirty pages to write-back + * + * This function shrinks UBIFS liability by means of writing back some amount + * of dirty inodes and their pages. + * + * Note, this function synchronizes even VFS inodes which are locked + * (@i_mutex) by the caller of the budgeting function, because write-back does + * not touch @i_mutex. + */ +static void shrink_liability(struct ubifs_info *c, int nr_to_write) +{ + down_read(&c->vfs_sb->s_umount); + writeback_inodes_sb(c->vfs_sb, WB_REASON_FS_FREE_SPACE); + up_read(&c->vfs_sb->s_umount); +} + +/** + * run_gc - run garbage collector. + * @c: UBIFS file-system description object + * + * This function runs garbage collector to make some more free space. Returns + * zero if a free LEB has been produced, %-EAGAIN if commit is required, and a + * negative error code in case of failure. + */ +static int run_gc(struct ubifs_info *c) +{ + int err, lnum; + + /* Make some free space by garbage-collecting dirty space */ + down_read(&c->commit_sem); + lnum = ubifs_garbage_collect(c, 1); + up_read(&c->commit_sem); + if (lnum < 0) + return lnum; + + /* GC freed one LEB, return it to lprops */ + dbg_budg("GC freed LEB %d", lnum); + err = ubifs_return_leb(c, lnum); + if (err) + return err; + return 0; +} + /** - * ubifs_calc_min_idx_lebs - calculate amount of eraseblocks for the index. + * get_liability - calculate current liability. * @c: UBIFS file-system description object * - * This function calculates and returns the number of eraseblocks which should - * be kept for index usage. + * This function calculates and returns current UBIFS liability, i.e. the + * amount of bytes UBIFS has "promised" to write to the media. + */ +static long long get_liability(struct ubifs_info *c) +{ + long long liab; + + spin_lock(&c->space_lock); + liab = c->bi.idx_growth + c->bi.data_growth + c->bi.dd_growth; + spin_unlock(&c->space_lock); + return liab; +} + +/** + * make_free_space - make more free space on the file-system. + * @c: UBIFS file-system description object + * + * This function is called when an operation cannot be budgeted because there + * is supposedly no free space. But in most cases there is some free space: + * o budgeting is pessimistic, so it always budgets more than it is actually + * needed, so shrinking the liability is one way to make free space - the + * cached data will take less space then it was budgeted for; + * o GC may turn some dark space into free space (budgeting treats dark space + * as not available); + * o commit may free some LEB, i.e., turn freeable LEBs into free LEBs. + * + * So this function tries to do the above. Returns %-EAGAIN if some free space + * was presumably made and the caller has to re-try budgeting the operation. + * Returns %-ENOSPC if it couldn't do more free space, and other negative error + * codes on failures. + */ +static int make_free_space(struct ubifs_info *c) +{ + int err, retries = 0; + long long liab1, liab2; + + do { + liab1 = get_liability(c); + /* + * We probably have some dirty pages or inodes (liability), try + * to write them back. + */ + dbg_budg("liability %lld, run write-back", liab1); + shrink_liability(c, NR_TO_WRITE); + + liab2 = get_liability(c); + if (liab2 < liab1) + return -EAGAIN; + + dbg_budg("new liability %lld (not shrunk)", liab2); + + /* Liability did not shrink again, try GC */ + dbg_budg("Run GC"); + err = run_gc(c); + if (!err) + return -EAGAIN; + + if (err != -EAGAIN && err != -ENOSPC) + /* Some real error happened */ + return err; + + dbg_budg("Run commit (retries %d)", retries); + err = ubifs_run_commit(c); + if (err) + return err; + } while (retries++ < MAX_MKSPC_RETRIES); + + return -ENOSPC; +} +#endif + +/** + * ubifs_calc_min_idx_lebs - calculate amount of LEBs for the index. + * @c: UBIFS file-system description object + * + * This function calculates and returns the number of LEBs which should be kept + * for index usage. */ int ubifs_calc_min_idx_lebs(struct ubifs_info *c) { - int idx_lebs, eff_leb_size = c->leb_size - c->max_idx_node_sz; + int idx_lebs; long long idx_size; - idx_size = c->old_idx_sz + c->budg_idx_growth + c->budg_uncommitted_idx; - + idx_size = c->bi.old_idx_sz + c->bi.idx_growth + c->bi.uncommitted_idx; /* And make sure we have thrice the index size of space reserved */ - idx_size = idx_size + (idx_size << 1); - + idx_size += idx_size << 1; /* * We do not maintain 'old_idx_size' as 'old_idx_lebs'/'old_idx_bytes' * pair, nor similarly the two variables for the new index size, so we * have to do this costly 64-bit division on fast-path. */ - idx_size += eff_leb_size - 1; - idx_lebs = div_u64(idx_size, eff_leb_size); + idx_lebs = div_u64(idx_size + c->idx_leb_size - 1, c->idx_leb_size); /* * The index head is not available for the in-the-gaps method, so add an * extra LEB to compensate. @@ -67,6 +194,424 @@ int ubifs_calc_min_idx_lebs(struct ubifs_info *c) return idx_lebs; } +#ifndef __UBOOT__ +/** + * ubifs_calc_available - calculate available FS space. + * @c: UBIFS file-system description object + * @min_idx_lebs: minimum number of LEBs reserved for the index + * + * This function calculates and returns amount of FS space available for use. + */ +long long ubifs_calc_available(const struct ubifs_info *c, int min_idx_lebs) +{ + int subtract_lebs; + long long available; + + available = c->main_bytes - c->lst.total_used; + + /* + * Now 'available' contains theoretically available flash space + * assuming there is no index, so we have to subtract the space which + * is reserved for the index. + */ + subtract_lebs = min_idx_lebs; + + /* Take into account that GC reserves one LEB for its own needs */ + subtract_lebs += 1; + + /* + * The GC journal head LEB is not really accessible. And since + * different write types go to different heads, we may count only on + * one head's space. + */ + subtract_lebs += c->jhead_cnt - 1; + + /* We also reserve one LEB for deletions, which bypass budgeting */ + subtract_lebs += 1; + + available -= (long long)subtract_lebs * c->leb_size; + + /* Subtract the dead space which is not available for use */ + available -= c->lst.total_dead; + + /* + * Subtract dark space, which might or might not be usable - it depends + * on the data which we have on the media and which will be written. If + * this is a lot of uncompressed or not-compressible data, the dark + * space cannot be used. + */ + available -= c->lst.total_dark; + + /* + * However, there is more dark space. The index may be bigger than + * @min_idx_lebs. Those extra LEBs are assumed to be available, but + * their dark space is not included in total_dark, so it is subtracted + * here. + */ + if (c->lst.idx_lebs > min_idx_lebs) { + subtract_lebs = c->lst.idx_lebs - min_idx_lebs; + available -= subtract_lebs * c->dark_wm; + } + + /* The calculations are rough and may end up with a negative number */ + return available > 0 ? available : 0; +} + +/** + * can_use_rp - check whether the user is allowed to use reserved pool. + * @c: UBIFS file-system description object + * + * UBIFS has so-called "reserved pool" which is flash space reserved + * for the superuser and for uses whose UID/GID is recorded in UBIFS superblock. + * This function checks whether current user is allowed to use reserved pool. + * Returns %1 current user is allowed to use reserved pool and %0 otherwise. + */ +static int can_use_rp(struct ubifs_info *c) +{ + if (uid_eq(current_fsuid(), c->rp_uid) || capable(CAP_SYS_RESOURCE) || + (!gid_eq(c->rp_gid, GLOBAL_ROOT_GID) && in_group_p(c->rp_gid))) + return 1; + return 0; +} + +/** + * do_budget_space - reserve flash space for index and data growth. + * @c: UBIFS file-system description object + * + * This function makes sure UBIFS has enough free LEBs for index growth and + * data. + * + * When budgeting index space, UBIFS reserves thrice as many LEBs as the index + * would take if it was consolidated and written to the flash. This guarantees + * that the "in-the-gaps" commit method always succeeds and UBIFS will always + * be able to commit dirty index. So this function basically adds amount of + * budgeted index space to the size of the current index, multiplies this by 3, + * and makes sure this does not exceed the amount of free LEBs. + * + * Notes about @c->bi.min_idx_lebs and @c->lst.idx_lebs variables: + * o @c->lst.idx_lebs is the number of LEBs the index currently uses. It might + * be large, because UBIFS does not do any index consolidation as long as + * there is free space. IOW, the index may take a lot of LEBs, but the LEBs + * will contain a lot of dirt. + * o @c->bi.min_idx_lebs is the number of LEBS the index presumably takes. IOW, + * the index may be consolidated to take up to @c->bi.min_idx_lebs LEBs. + * + * This function returns zero in case of success, and %-ENOSPC in case of + * failure. + */ +static int do_budget_space(struct ubifs_info *c) +{ + long long outstanding, available; + int lebs, rsvd_idx_lebs, min_idx_lebs; + + /* First budget index space */ + min_idx_lebs = ubifs_calc_min_idx_lebs(c); + + /* Now 'min_idx_lebs' contains number of LEBs to reserve */ + if (min_idx_lebs > c->lst.idx_lebs) + rsvd_idx_lebs = min_idx_lebs - c->lst.idx_lebs; + else + rsvd_idx_lebs = 0; + + /* + * The number of LEBs that are available to be used by the index is: + * + * @c->lst.empty_lebs + @c->freeable_cnt + @c->idx_gc_cnt - + * @c->lst.taken_empty_lebs + * + * @c->lst.empty_lebs are available because they are empty. + * @c->freeable_cnt are available because they contain only free and + * dirty space, @c->idx_gc_cnt are available because they are index + * LEBs that have been garbage collected and are awaiting the commit + * before they can be used. And the in-the-gaps method will grab these + * if it needs them. @c->lst.taken_empty_lebs are empty LEBs that have + * already been allocated for some purpose. + * + * Note, @c->idx_gc_cnt is included to both @c->lst.empty_lebs (because + * these LEBs are empty) and to @c->lst.taken_empty_lebs (because they + * are taken until after the commit). + * + * Note, @c->lst.taken_empty_lebs may temporarily be higher by one + * because of the way we serialize LEB allocations and budgeting. See a + * comment in 'ubifs_find_free_space()'. + */ + lebs = c->lst.empty_lebs + c->freeable_cnt + c->idx_gc_cnt - + c->lst.taken_empty_lebs; + if (unlikely(rsvd_idx_lebs > lebs)) { + dbg_budg("out of indexing space: min_idx_lebs %d (old %d), rsvd_idx_lebs %d", + min_idx_lebs, c->bi.min_idx_lebs, rsvd_idx_lebs); + return -ENOSPC; + } + + available = ubifs_calc_available(c, min_idx_lebs); + outstanding = c->bi.data_growth + c->bi.dd_growth; + + if (unlikely(available < outstanding)) { + dbg_budg("out of data space: available %lld, outstanding %lld", + available, outstanding); + return -ENOSPC; + } + + if (available - outstanding <= c->rp_size && !can_use_rp(c)) + return -ENOSPC; + + c->bi.min_idx_lebs = min_idx_lebs; + return 0; +} + +/** + * calc_idx_growth - calculate approximate index growth from budgeting request. + * @c: UBIFS file-system description object + * @req: budgeting request + * + * For now we assume each new node adds one znode. But this is rather poor + * approximation, though. + */ +static int calc_idx_growth(const struct ubifs_info *c, + const struct ubifs_budget_req *req) +{ + int znodes; + + znodes = req->new_ino + (req->new_page << UBIFS_BLOCKS_PER_PAGE_SHIFT) + + req->new_dent; + return znodes * c->max_idx_node_sz; +} + +/** + * calc_data_growth - calculate approximate amount of new data from budgeting + * request. + * @c: UBIFS file-system description object + * @req: budgeting request + */ +static int calc_data_growth(const struct ubifs_info *c, + const struct ubifs_budget_req *req) +{ + int data_growth; + + data_growth = req->new_ino ? c->bi.inode_budget : 0; + if (req->new_page) + data_growth += c->bi.page_budget; + if (req->new_dent) + data_growth += c->bi.dent_budget; + data_growth += req->new_ino_d; + return data_growth; +} + +/** + * calc_dd_growth - calculate approximate amount of data which makes other data + * dirty from budgeting request. + * @c: UBIFS file-system description object + * @req: budgeting request + */ +static int calc_dd_growth(const struct ubifs_info *c, + const struct ubifs_budget_req *req) +{ + int dd_growth; + + dd_growth = req->dirtied_page ? c->bi.page_budget : 0; + + if (req->dirtied_ino) + dd_growth += c->bi.inode_budget << (req->dirtied_ino - 1); + if (req->mod_dent) + dd_growth += c->bi.dent_budget; + dd_growth += req->dirtied_ino_d; + return dd_growth; +} + +/** + * ubifs_budget_space - ensure there is enough space to complete an operation. + * @c: UBIFS file-system description object + * @req: budget request + * + * This function allocates budget for an operation. It uses pessimistic + * approximation of how much flash space the operation needs. The goal of this + * function is to make sure UBIFS always has flash space to flush all dirty + * pages, dirty inodes, and dirty znodes (liability). This function may force + * commit, garbage-collection or write-back. Returns zero in case of success, + * %-ENOSPC if there is no free space and other negative error codes in case of + * failures. + */ +int ubifs_budget_space(struct ubifs_info *c, struct ubifs_budget_req *req) +{ + int uninitialized_var(cmt_retries), uninitialized_var(wb_retries); + int err, idx_growth, data_growth, dd_growth, retried = 0; + + ubifs_assert(req->new_page <= 1); + ubifs_assert(req->dirtied_page <= 1); + ubifs_assert(req->new_dent <= 1); + ubifs_assert(req->mod_dent <= 1); + ubifs_assert(req->new_ino <= 1); + ubifs_assert(req->new_ino_d <= UBIFS_MAX_INO_DATA); + ubifs_assert(req->dirtied_ino <= 4); + ubifs_assert(req->dirtied_ino_d <= UBIFS_MAX_INO_DATA * 4); + ubifs_assert(!(req->new_ino_d & 7)); + ubifs_assert(!(req->dirtied_ino_d & 7)); + + data_growth = calc_data_growth(c, req); + dd_growth = calc_dd_growth(c, req); + if (!data_growth && !dd_growth) + return 0; + idx_growth = calc_idx_growth(c, req); + +again: + spin_lock(&c->space_lock); + ubifs_assert(c->bi.idx_growth >= 0); + ubifs_assert(c->bi.data_growth >= 0); + ubifs_assert(c->bi.dd_growth >= 0); + + if (unlikely(c->bi.nospace) && (c->bi.nospace_rp || !can_use_rp(c))) { + dbg_budg("no space"); + spin_unlock(&c->space_lock); + return -ENOSPC; + } + + c->bi.idx_growth += idx_growth; + c->bi.data_growth += data_growth; + c->bi.dd_growth += dd_growth; + + err = do_budget_space(c); + if (likely(!err)) { + req->idx_growth = idx_growth; + req->data_growth = data_growth; + req->dd_growth = dd_growth; + spin_unlock(&c->space_lock); + return 0; + } + + /* Restore the old values */ + c->bi.idx_growth -= idx_growth; + c->bi.data_growth -= data_growth; + c->bi.dd_growth -= dd_growth; + spin_unlock(&c->space_lock); + + if (req->fast) { + dbg_budg("no space for fast budgeting"); + return err; + } + + err = make_free_space(c); + cond_resched(); + if (err == -EAGAIN) { + dbg_budg("try again"); + goto again; + } else if (err == -ENOSPC) { + if (!retried) { + retried = 1; + dbg_budg("-ENOSPC, but anyway try once again"); + goto again; + } + dbg_budg("FS is full, -ENOSPC"); + c->bi.nospace = 1; + if (can_use_rp(c) || c->rp_size == 0) + c->bi.nospace_rp = 1; + smp_wmb(); + } else + ubifs_err("cannot budget space, error %d", err); + return err; +} + +/** + * ubifs_release_budget - release budgeted free space. + * @c: UBIFS file-system description object + * @req: budget request + * + * This function releases the space budgeted by 'ubifs_budget_space()'. Note, + * since the index changes (which were budgeted for in @req->idx_growth) will + * only be written to the media on commit, this function moves the index budget + * from @c->bi.idx_growth to @c->bi.uncommitted_idx. The latter will be zeroed + * by the commit operation. + */ +void ubifs_release_budget(struct ubifs_info *c, struct ubifs_budget_req *req) +{ + ubifs_assert(req->new_page <= 1); + ubifs_assert(req->dirtied_page <= 1); + ubifs_assert(req->new_dent <= 1); + ubifs_assert(req->mod_dent <= 1); + ubifs_assert(req->new_ino <= 1); + ubifs_assert(req->new_ino_d <= UBIFS_MAX_INO_DATA); + ubifs_assert(req->dirtied_ino <= 4); + ubifs_assert(req->dirtied_ino_d <= UBIFS_MAX_INO_DATA * 4); + ubifs_assert(!(req->new_ino_d & 7)); + ubifs_assert(!(req->dirtied_ino_d & 7)); + if (!req->recalculate) { + ubifs_assert(req->idx_growth >= 0); + ubifs_assert(req->data_growth >= 0); + ubifs_assert(req->dd_growth >= 0); + } + + if (req->recalculate) { + req->data_growth = calc_data_growth(c, req); + req->dd_growth = calc_dd_growth(c, req); + req->idx_growth = calc_idx_growth(c, req); + } + + if (!req->data_growth && !req->dd_growth) + return; + + c->bi.nospace = c->bi.nospace_rp = 0; + smp_wmb(); + + spin_lock(&c->space_lock); + c->bi.idx_growth -= req->idx_growth; + c->bi.uncommitted_idx += req->idx_growth; + c->bi.data_growth -= req->data_growth; + c->bi.dd_growth -= req->dd_growth; + c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c); + + ubifs_assert(c->bi.idx_growth >= 0); + ubifs_assert(c->bi.data_growth >= 0); + ubifs_assert(c->bi.dd_growth >= 0); + ubifs_assert(c->bi.min_idx_lebs < c->main_lebs); + ubifs_assert(!(c->bi.idx_growth & 7)); + ubifs_assert(!(c->bi.data_growth & 7)); + ubifs_assert(!(c->bi.dd_growth & 7)); + spin_unlock(&c->space_lock); +} + +/** + * ubifs_convert_page_budget - convert budget of a new page. + * @c: UBIFS file-system description object + * + * This function converts budget which was allocated for a new page of data to + * the budget of changing an existing page of data. The latter is smaller than + * the former, so this function only does simple re-calculation and does not + * involve any write-back. + */ +void ubifs_convert_page_budget(struct ubifs_info *c) +{ + spin_lock(&c->space_lock); + /* Release the index growth reservation */ + c->bi.idx_growth -= c->max_idx_node_sz << UBIFS_BLOCKS_PER_PAGE_SHIFT; + /* Release the data growth reservation */ + c->bi.data_growth -= c->bi.page_budget; + /* Increase the dirty data growth reservation instead */ + c->bi.dd_growth += c->bi.page_budget; + /* And re-calculate the indexing space reservation */ + c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c); + spin_unlock(&c->space_lock); +} + +/** + * ubifs_release_dirty_inode_budget - release dirty inode budget. + * @c: UBIFS file-system description object + * @ui: UBIFS inode to release the budget for + * + * This function releases budget corresponding to a dirty inode. It is usually + * called when after the inode has been written to the media and marked as + * clean. It also causes the "no space" flags to be cleared. + */ +void ubifs_release_dirty_inode_budget(struct ubifs_info *c, + struct ubifs_inode *ui) +{ + struct ubifs_budget_req req; + + memset(&req, 0, sizeof(struct ubifs_budget_req)); + /* The "no space" flags will be cleared because dd_growth is > 0 */ + req.dd_growth = c->bi.inode_budget + ALIGN(ui->data_len, 8); + ubifs_release_budget(c, &req); +} +#endif + /** * ubifs_reported_space - calculate reported free space. * @c: the UBIFS file-system description object @@ -111,3 +656,75 @@ long long ubifs_reported_space(const struct ubifs_info *c, long long free) free *= factor; return div_u64(free, divisor); } + +#ifndef __UBOOT__ +/** + * ubifs_get_free_space_nolock - return amount of free space. + * @c: UBIFS file-system description object + * + * This function calculates amount of free space to report to user-space. + * + * Because UBIFS may introduce substantial overhead (the index, node headers, + * alignment, wastage at the end of LEBs, etc), it cannot report real amount of + * free flash space it has (well, because not all dirty space is reclaimable, + * UBIFS does not actually know the real amount). If UBIFS did so, it would + * bread user expectations about what free space is. Users seem to accustomed + * to assume that if the file-system reports N bytes of free space, they would + * be able to fit a file of N bytes to the FS. This almost works for + * traditional file-systems, because they have way less overhead than UBIFS. + * So, to keep users happy, UBIFS tries to take the overhead into account. + */ +long long ubifs_get_free_space_nolock(struct ubifs_info *c) +{ + int rsvd_idx_lebs, lebs; + long long available, outstanding, free; + + ubifs_assert(c->bi.min_idx_lebs == ubifs_calc_min_idx_lebs(c)); + outstanding = c->bi.data_growth + c->bi.dd_growth; + available = ubifs_calc_available(c, c->bi.min_idx_lebs); + + /* + * When reporting free space to user-space, UBIFS guarantees that it is + * possible to write a file of free space size. This means that for + * empty LEBs we may use more precise calculations than + * 'ubifs_calc_available()' is using. Namely, we know that in empty + * LEBs we would waste only @c->leb_overhead bytes, not @c->dark_wm. + * Thus, amend the available space. + * + * Note, the calculations below are similar to what we have in + * 'do_budget_space()', so refer there for comments. + */ + if (c->bi.min_idx_lebs > c->lst.idx_lebs) + rsvd_idx_lebs = c->bi.min_idx_lebs - c->lst.idx_lebs; + else + rsvd_idx_lebs = 0; + lebs = c->lst.empty_lebs + c->freeable_cnt + c->idx_gc_cnt - + c->lst.taken_empty_lebs; + lebs -= rsvd_idx_lebs; + available += lebs * (c->dark_wm - c->leb_overhead); + + if (available > outstanding) + free = ubifs_reported_space(c, available - outstanding); + else + free = 0; + return free; +} + +/** + * ubifs_get_free_space - return amount of free space. + * @c: UBIFS file-system description object + * + * This function calculates and returns amount of free space to report to + * user-space. + */ +long long ubifs_get_free_space(struct ubifs_info *c) +{ + long long free; + + spin_lock(&c->space_lock); + free = ubifs_get_free_space_nolock(c); + spin_unlock(&c->space_lock); + + return free; +} +#endif diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c index 6afb8835a5..6e6f018b2f 100644 --- a/fs/ubifs/debug.c +++ b/fs/ubifs/debug.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -27,28 +16,43 @@ * various local functions of those subsystems. */ -#define UBIFS_DBG_PRESERVE_UBI - +#ifndef __UBOOT__ +#include +#include +#include +#include +#include +#else +#include +#include +#endif #include "ubifs.h" -#ifdef CONFIG_UBIFS_FS_DEBUG - -DEFINE_SPINLOCK(dbg_lock); +#ifndef __UBOOT__ +static DEFINE_SPINLOCK(dbg_lock); +#endif -static char dbg_key_buf0[128]; -static char dbg_key_buf1[128]; - -unsigned int ubifs_msg_flags = UBIFS_MSG_FLAGS_DEFAULT; -unsigned int ubifs_chk_flags = UBIFS_CHK_FLAGS_DEFAULT; -unsigned int ubifs_tst_flags; - -module_param_named(debug_msgs, ubifs_msg_flags, uint, S_IRUGO | S_IWUSR); -module_param_named(debug_chks, ubifs_chk_flags, uint, S_IRUGO | S_IWUSR); -module_param_named(debug_tsts, ubifs_tst_flags, uint, S_IRUGO | S_IWUSR); +static const char *get_key_fmt(int fmt) +{ + switch (fmt) { + case UBIFS_SIMPLE_KEY_FMT: + return "simple"; + default: + return "unknown/invalid format"; + } +} -MODULE_PARM_DESC(debug_msgs, "Debug message type flags"); -MODULE_PARM_DESC(debug_chks, "Debug check flags"); -MODULE_PARM_DESC(debug_tsts, "Debug special test flags"); +static const char *get_key_hash(int hash) +{ + switch (hash) { + case UBIFS_KEY_HASH_R5: + return "R5"; + case UBIFS_KEY_HASH_TEST: + return "test"; + default: + return "unknown/invalid name hash"; + } +} static const char *get_key_type(int type) { @@ -68,8 +72,32 @@ static const char *get_key_type(int type) } } -static void sprintf_key(const struct ubifs_info *c, const union ubifs_key *key, - char *buffer) +#ifndef __UBOOT__ +static const char *get_dent_type(int type) +{ + switch (type) { + case UBIFS_ITYPE_REG: + return "file"; + case UBIFS_ITYPE_DIR: + return "dir"; + case UBIFS_ITYPE_LNK: + return "symlink"; + case UBIFS_ITYPE_BLK: + return "blkdev"; + case UBIFS_ITYPE_CHR: + return "char dev"; + case UBIFS_ITYPE_FIFO: + return "fifo"; + case UBIFS_ITYPE_SOCK: + return "socket"; + default: + return "unknown/invalid type"; + } +} +#endif + +const char *dbg_snprintf_key(const struct ubifs_info *c, + const union ubifs_key *key, char *buffer, int len) { char *p = buffer; int type = key_type(c, key); @@ -77,80 +105,3038 @@ static void sprintf_key(const struct ubifs_info *c, const union ubifs_key *key, if (c->key_fmt == UBIFS_SIMPLE_KEY_FMT) { switch (type) { case UBIFS_INO_KEY: - sprintf(p, "(%lu, %s)", (unsigned long)key_inum(c, key), - get_key_type(type)); + len -= snprintf(p, len, "(%lu, %s)", + (unsigned long)key_inum(c, key), + get_key_type(type)); break; case UBIFS_DENT_KEY: case UBIFS_XENT_KEY: - sprintf(p, "(%lu, %s, %#08x)", - (unsigned long)key_inum(c, key), - get_key_type(type), key_hash(c, key)); + len -= snprintf(p, len, "(%lu, %s, %#08x)", + (unsigned long)key_inum(c, key), + get_key_type(type), key_hash(c, key)); break; case UBIFS_DATA_KEY: - sprintf(p, "(%lu, %s, %u)", - (unsigned long)key_inum(c, key), - get_key_type(type), key_block(c, key)); + len -= snprintf(p, len, "(%lu, %s, %u)", + (unsigned long)key_inum(c, key), + get_key_type(type), key_block(c, key)); break; case UBIFS_TRUN_KEY: - sprintf(p, "(%lu, %s)", - (unsigned long)key_inum(c, key), - get_key_type(type)); + len -= snprintf(p, len, "(%lu, %s)", + (unsigned long)key_inum(c, key), + get_key_type(type)); break; default: - sprintf(p, "(bad key type: %#08x, %#08x)", - key->u32[0], key->u32[1]); + len -= snprintf(p, len, "(bad key type: %#08x, %#08x)", + key->u32[0], key->u32[1]); } } else - sprintf(p, "bad key format %d", c->key_fmt); + len -= snprintf(p, len, "bad key format %d", c->key_fmt); + ubifs_assert(len > 0); + return p; +} + +const char *dbg_ntype(int type) +{ + switch (type) { + case UBIFS_PAD_NODE: + return "padding node"; + case UBIFS_SB_NODE: + return "superblock node"; + case UBIFS_MST_NODE: + return "master node"; + case UBIFS_REF_NODE: + return "reference node"; + case UBIFS_INO_NODE: + return "inode node"; + case UBIFS_DENT_NODE: + return "direntry node"; + case UBIFS_XENT_NODE: + return "xentry node"; + case UBIFS_DATA_NODE: + return "data node"; + case UBIFS_TRUN_NODE: + return "truncate node"; + case UBIFS_IDX_NODE: + return "indexing node"; + case UBIFS_CS_NODE: + return "commit start node"; + case UBIFS_ORPH_NODE: + return "orphan node"; + default: + return "unknown node"; + } +} + +static const char *dbg_gtype(int type) +{ + switch (type) { + case UBIFS_NO_NODE_GROUP: + return "no node group"; + case UBIFS_IN_NODE_GROUP: + return "in node group"; + case UBIFS_LAST_OF_NODE_GROUP: + return "last of node group"; + default: + return "unknown"; + } +} + +const char *dbg_cstate(int cmt_state) +{ + switch (cmt_state) { + case COMMIT_RESTING: + return "commit resting"; + case COMMIT_BACKGROUND: + return "background commit requested"; + case COMMIT_REQUIRED: + return "commit required"; + case COMMIT_RUNNING_BACKGROUND: + return "BACKGROUND commit running"; + case COMMIT_RUNNING_REQUIRED: + return "commit running and required"; + case COMMIT_BROKEN: + return "broken commit"; + default: + return "unknown commit state"; + } +} + +const char *dbg_jhead(int jhead) +{ + switch (jhead) { + case GCHD: + return "0 (GC)"; + case BASEHD: + return "1 (base)"; + case DATAHD: + return "2 (data)"; + default: + return "unknown journal head"; + } +} + +static void dump_ch(const struct ubifs_ch *ch) +{ + pr_err("\tmagic %#x\n", le32_to_cpu(ch->magic)); + pr_err("\tcrc %#x\n", le32_to_cpu(ch->crc)); + pr_err("\tnode_type %d (%s)\n", ch->node_type, + dbg_ntype(ch->node_type)); + pr_err("\tgroup_type %d (%s)\n", ch->group_type, + dbg_gtype(ch->group_type)); + pr_err("\tsqnum %llu\n", + (unsigned long long)le64_to_cpu(ch->sqnum)); + pr_err("\tlen %u\n", le32_to_cpu(ch->len)); +} + +void ubifs_dump_inode(struct ubifs_info *c, const struct inode *inode) +{ +#ifndef __UBOOT__ + const struct ubifs_inode *ui = ubifs_inode(inode); + struct qstr nm = { .name = NULL }; + union ubifs_key key; + struct ubifs_dent_node *dent, *pdent = NULL; + int count = 2; + + pr_err("Dump in-memory inode:"); + pr_err("\tinode %lu\n", inode->i_ino); + pr_err("\tsize %llu\n", + (unsigned long long)i_size_read(inode)); + pr_err("\tnlink %u\n", inode->i_nlink); + pr_err("\tuid %u\n", (unsigned int)i_uid_read(inode)); + pr_err("\tgid %u\n", (unsigned int)i_gid_read(inode)); + pr_err("\tatime %u.%u\n", + (unsigned int)inode->i_atime.tv_sec, + (unsigned int)inode->i_atime.tv_nsec); + pr_err("\tmtime %u.%u\n", + (unsigned int)inode->i_mtime.tv_sec, + (unsigned int)inode->i_mtime.tv_nsec); + pr_err("\tctime %u.%u\n", + (unsigned int)inode->i_ctime.tv_sec, + (unsigned int)inode->i_ctime.tv_nsec); + pr_err("\tcreat_sqnum %llu\n", ui->creat_sqnum); + pr_err("\txattr_size %u\n", ui->xattr_size); + pr_err("\txattr_cnt %u\n", ui->xattr_cnt); + pr_err("\txattr_names %u\n", ui->xattr_names); + pr_err("\tdirty %u\n", ui->dirty); + pr_err("\txattr %u\n", ui->xattr); + pr_err("\tbulk_read %u\n", ui->xattr); + pr_err("\tsynced_i_size %llu\n", + (unsigned long long)ui->synced_i_size); + pr_err("\tui_size %llu\n", + (unsigned long long)ui->ui_size); + pr_err("\tflags %d\n", ui->flags); + pr_err("\tcompr_type %d\n", ui->compr_type); + pr_err("\tlast_page_read %lu\n", ui->last_page_read); + pr_err("\tread_in_a_row %lu\n", ui->read_in_a_row); + pr_err("\tdata_len %d\n", ui->data_len); + + if (!S_ISDIR(inode->i_mode)) + return; + + pr_err("List of directory entries:\n"); + ubifs_assert(!mutex_is_locked(&c->tnc_mutex)); + + lowest_dent_key(c, &key, inode->i_ino); + while (1) { + dent = ubifs_tnc_next_ent(c, &key, &nm); + if (IS_ERR(dent)) { + if (PTR_ERR(dent) != -ENOENT) + pr_err("error %ld\n", PTR_ERR(dent)); + break; + } + + pr_err("\t%d: %s (%s)\n", + count++, dent->name, get_dent_type(dent->type)); + + nm.name = dent->name; + nm.len = le16_to_cpu(dent->nlen); + kfree(pdent); + pdent = dent; + key_read(c, &dent->key, &key); + } + kfree(pdent); +#endif +} + +void ubifs_dump_node(const struct ubifs_info *c, const void *node) +{ + int i, n; + union ubifs_key key; + const struct ubifs_ch *ch = node; + char key_buf[DBG_KEY_BUF_LEN]; + + /* If the magic is incorrect, just hexdump the first bytes */ + if (le32_to_cpu(ch->magic) != UBIFS_NODE_MAGIC) { + pr_err("Not a node, first %zu bytes:", UBIFS_CH_SZ); + print_hex_dump(KERN_ERR, "", DUMP_PREFIX_OFFSET, 32, 1, + (void *)node, UBIFS_CH_SZ, 1); + return; + } + + spin_lock(&dbg_lock); + dump_ch(node); + + switch (ch->node_type) { + case UBIFS_PAD_NODE: + { + const struct ubifs_pad_node *pad = node; + + pr_err("\tpad_len %u\n", le32_to_cpu(pad->pad_len)); + break; + } + case UBIFS_SB_NODE: + { + const struct ubifs_sb_node *sup = node; + unsigned int sup_flags = le32_to_cpu(sup->flags); + + pr_err("\tkey_hash %d (%s)\n", + (int)sup->key_hash, get_key_hash(sup->key_hash)); + pr_err("\tkey_fmt %d (%s)\n", + (int)sup->key_fmt, get_key_fmt(sup->key_fmt)); + pr_err("\tflags %#x\n", sup_flags); + pr_err("\t big_lpt %u\n", + !!(sup_flags & UBIFS_FLG_BIGLPT)); + pr_err("\t space_fixup %u\n", + !!(sup_flags & UBIFS_FLG_SPACE_FIXUP)); + pr_err("\tmin_io_size %u\n", le32_to_cpu(sup->min_io_size)); + pr_err("\tleb_size %u\n", le32_to_cpu(sup->leb_size)); + pr_err("\tleb_cnt %u\n", le32_to_cpu(sup->leb_cnt)); + pr_err("\tmax_leb_cnt %u\n", le32_to_cpu(sup->max_leb_cnt)); + pr_err("\tmax_bud_bytes %llu\n", + (unsigned long long)le64_to_cpu(sup->max_bud_bytes)); + pr_err("\tlog_lebs %u\n", le32_to_cpu(sup->log_lebs)); + pr_err("\tlpt_lebs %u\n", le32_to_cpu(sup->lpt_lebs)); + pr_err("\torph_lebs %u\n", le32_to_cpu(sup->orph_lebs)); + pr_err("\tjhead_cnt %u\n", le32_to_cpu(sup->jhead_cnt)); + pr_err("\tfanout %u\n", le32_to_cpu(sup->fanout)); + pr_err("\tlsave_cnt %u\n", le32_to_cpu(sup->lsave_cnt)); + pr_err("\tdefault_compr %u\n", + (int)le16_to_cpu(sup->default_compr)); + pr_err("\trp_size %llu\n", + (unsigned long long)le64_to_cpu(sup->rp_size)); + pr_err("\trp_uid %u\n", le32_to_cpu(sup->rp_uid)); + pr_err("\trp_gid %u\n", le32_to_cpu(sup->rp_gid)); + pr_err("\tfmt_version %u\n", le32_to_cpu(sup->fmt_version)); + pr_err("\ttime_gran %u\n", le32_to_cpu(sup->time_gran)); + pr_err("\tUUID %pUB\n", sup->uuid); + break; + } + case UBIFS_MST_NODE: + { + const struct ubifs_mst_node *mst = node; + + pr_err("\thighest_inum %llu\n", + (unsigned long long)le64_to_cpu(mst->highest_inum)); + pr_err("\tcommit number %llu\n", + (unsigned long long)le64_to_cpu(mst->cmt_no)); + pr_err("\tflags %#x\n", le32_to_cpu(mst->flags)); + pr_err("\tlog_lnum %u\n", le32_to_cpu(mst->log_lnum)); + pr_err("\troot_lnum %u\n", le32_to_cpu(mst->root_lnum)); + pr_err("\troot_offs %u\n", le32_to_cpu(mst->root_offs)); + pr_err("\troot_len %u\n", le32_to_cpu(mst->root_len)); + pr_err("\tgc_lnum %u\n", le32_to_cpu(mst->gc_lnum)); + pr_err("\tihead_lnum %u\n", le32_to_cpu(mst->ihead_lnum)); + pr_err("\tihead_offs %u\n", le32_to_cpu(mst->ihead_offs)); + pr_err("\tindex_size %llu\n", + (unsigned long long)le64_to_cpu(mst->index_size)); + pr_err("\tlpt_lnum %u\n", le32_to_cpu(mst->lpt_lnum)); + pr_err("\tlpt_offs %u\n", le32_to_cpu(mst->lpt_offs)); + pr_err("\tnhead_lnum %u\n", le32_to_cpu(mst->nhead_lnum)); + pr_err("\tnhead_offs %u\n", le32_to_cpu(mst->nhead_offs)); + pr_err("\tltab_lnum %u\n", le32_to_cpu(mst->ltab_lnum)); + pr_err("\tltab_offs %u\n", le32_to_cpu(mst->ltab_offs)); + pr_err("\tlsave_lnum %u\n", le32_to_cpu(mst->lsave_lnum)); + pr_err("\tlsave_offs %u\n", le32_to_cpu(mst->lsave_offs)); + pr_err("\tlscan_lnum %u\n", le32_to_cpu(mst->lscan_lnum)); + pr_err("\tleb_cnt %u\n", le32_to_cpu(mst->leb_cnt)); + pr_err("\tempty_lebs %u\n", le32_to_cpu(mst->empty_lebs)); + pr_err("\tidx_lebs %u\n", le32_to_cpu(mst->idx_lebs)); + pr_err("\ttotal_free %llu\n", + (unsigned long long)le64_to_cpu(mst->total_free)); + pr_err("\ttotal_dirty %llu\n", + (unsigned long long)le64_to_cpu(mst->total_dirty)); + pr_err("\ttotal_used %llu\n", + (unsigned long long)le64_to_cpu(mst->total_used)); + pr_err("\ttotal_dead %llu\n", + (unsigned long long)le64_to_cpu(mst->total_dead)); + pr_err("\ttotal_dark %llu\n", + (unsigned long long)le64_to_cpu(mst->total_dark)); + break; + } + case UBIFS_REF_NODE: + { + const struct ubifs_ref_node *ref = node; + + pr_err("\tlnum %u\n", le32_to_cpu(ref->lnum)); + pr_err("\toffs %u\n", le32_to_cpu(ref->offs)); + pr_err("\tjhead %u\n", le32_to_cpu(ref->jhead)); + break; + } + case UBIFS_INO_NODE: + { + const struct ubifs_ino_node *ino = node; + + key_read(c, &ino->key, &key); + pr_err("\tkey %s\n", + dbg_snprintf_key(c, &key, key_buf, DBG_KEY_BUF_LEN)); + pr_err("\tcreat_sqnum %llu\n", + (unsigned long long)le64_to_cpu(ino->creat_sqnum)); + pr_err("\tsize %llu\n", + (unsigned long long)le64_to_cpu(ino->size)); + pr_err("\tnlink %u\n", le32_to_cpu(ino->nlink)); + pr_err("\tatime %lld.%u\n", + (long long)le64_to_cpu(ino->atime_sec), + le32_to_cpu(ino->atime_nsec)); + pr_err("\tmtime %lld.%u\n", + (long long)le64_to_cpu(ino->mtime_sec), + le32_to_cpu(ino->mtime_nsec)); + pr_err("\tctime %lld.%u\n", + (long long)le64_to_cpu(ino->ctime_sec), + le32_to_cpu(ino->ctime_nsec)); + pr_err("\tuid %u\n", le32_to_cpu(ino->uid)); + pr_err("\tgid %u\n", le32_to_cpu(ino->gid)); + pr_err("\tmode %u\n", le32_to_cpu(ino->mode)); + pr_err("\tflags %#x\n", le32_to_cpu(ino->flags)); + pr_err("\txattr_cnt %u\n", le32_to_cpu(ino->xattr_cnt)); + pr_err("\txattr_size %u\n", le32_to_cpu(ino->xattr_size)); + pr_err("\txattr_names %u\n", le32_to_cpu(ino->xattr_names)); + pr_err("\tcompr_type %#x\n", + (int)le16_to_cpu(ino->compr_type)); + pr_err("\tdata len %u\n", le32_to_cpu(ino->data_len)); + break; + } + case UBIFS_DENT_NODE: + case UBIFS_XENT_NODE: + { + const struct ubifs_dent_node *dent = node; + int nlen = le16_to_cpu(dent->nlen); + + key_read(c, &dent->key, &key); + pr_err("\tkey %s\n", + dbg_snprintf_key(c, &key, key_buf, DBG_KEY_BUF_LEN)); + pr_err("\tinum %llu\n", + (unsigned long long)le64_to_cpu(dent->inum)); + pr_err("\ttype %d\n", (int)dent->type); + pr_err("\tnlen %d\n", nlen); + pr_err("\tname "); + + if (nlen > UBIFS_MAX_NLEN) + pr_err("(bad name length, not printing, bad or corrupted node)"); + else { + for (i = 0; i < nlen && dent->name[i]; i++) + pr_cont("%c", dent->name[i]); + } + pr_cont("\n"); + + break; + } + case UBIFS_DATA_NODE: + { + const struct ubifs_data_node *dn = node; + int dlen = le32_to_cpu(ch->len) - UBIFS_DATA_NODE_SZ; + + key_read(c, &dn->key, &key); + pr_err("\tkey %s\n", + dbg_snprintf_key(c, &key, key_buf, DBG_KEY_BUF_LEN)); + pr_err("\tsize %u\n", le32_to_cpu(dn->size)); + pr_err("\tcompr_typ %d\n", + (int)le16_to_cpu(dn->compr_type)); + pr_err("\tdata size %d\n", dlen); + pr_err("\tdata:\n"); + print_hex_dump(KERN_ERR, "\t", DUMP_PREFIX_OFFSET, 32, 1, + (void *)&dn->data, dlen, 0); + break; + } + case UBIFS_TRUN_NODE: + { + const struct ubifs_trun_node *trun = node; + + pr_err("\tinum %u\n", le32_to_cpu(trun->inum)); + pr_err("\told_size %llu\n", + (unsigned long long)le64_to_cpu(trun->old_size)); + pr_err("\tnew_size %llu\n", + (unsigned long long)le64_to_cpu(trun->new_size)); + break; + } + case UBIFS_IDX_NODE: + { + const struct ubifs_idx_node *idx = node; + + n = le16_to_cpu(idx->child_cnt); + pr_err("\tchild_cnt %d\n", n); + pr_err("\tlevel %d\n", (int)le16_to_cpu(idx->level)); + pr_err("\tBranches:\n"); + + for (i = 0; i < n && i < c->fanout - 1; i++) { + const struct ubifs_branch *br; + + br = ubifs_idx_branch(c, idx, i); + key_read(c, &br->key, &key); + pr_err("\t%d: LEB %d:%d len %d key %s\n", + i, le32_to_cpu(br->lnum), le32_to_cpu(br->offs), + le32_to_cpu(br->len), + dbg_snprintf_key(c, &key, key_buf, + DBG_KEY_BUF_LEN)); + } + break; + } + case UBIFS_CS_NODE: + break; + case UBIFS_ORPH_NODE: + { + const struct ubifs_orph_node *orph = node; + + pr_err("\tcommit number %llu\n", + (unsigned long long) + le64_to_cpu(orph->cmt_no) & LLONG_MAX); + pr_err("\tlast node flag %llu\n", + (unsigned long long)(le64_to_cpu(orph->cmt_no)) >> 63); + n = (le32_to_cpu(ch->len) - UBIFS_ORPH_NODE_SZ) >> 3; + pr_err("\t%d orphan inode numbers:\n", n); + for (i = 0; i < n; i++) + pr_err("\t ino %llu\n", + (unsigned long long)le64_to_cpu(orph->inos[i])); + break; + } + default: + pr_err("node type %d was not recognized\n", + (int)ch->node_type); + } + spin_unlock(&dbg_lock); +} + +void ubifs_dump_budget_req(const struct ubifs_budget_req *req) +{ + spin_lock(&dbg_lock); + pr_err("Budgeting request: new_ino %d, dirtied_ino %d\n", + req->new_ino, req->dirtied_ino); + pr_err("\tnew_ino_d %d, dirtied_ino_d %d\n", + req->new_ino_d, req->dirtied_ino_d); + pr_err("\tnew_page %d, dirtied_page %d\n", + req->new_page, req->dirtied_page); + pr_err("\tnew_dent %d, mod_dent %d\n", + req->new_dent, req->mod_dent); + pr_err("\tidx_growth %d\n", req->idx_growth); + pr_err("\tdata_growth %d dd_growth %d\n", + req->data_growth, req->dd_growth); + spin_unlock(&dbg_lock); +} + +void ubifs_dump_lstats(const struct ubifs_lp_stats *lst) +{ + spin_lock(&dbg_lock); + pr_err("(pid %d) Lprops statistics: empty_lebs %d, idx_lebs %d\n", + current->pid, lst->empty_lebs, lst->idx_lebs); + pr_err("\ttaken_empty_lebs %d, total_free %lld, total_dirty %lld\n", + lst->taken_empty_lebs, lst->total_free, lst->total_dirty); + pr_err("\ttotal_used %lld, total_dark %lld, total_dead %lld\n", + lst->total_used, lst->total_dark, lst->total_dead); + spin_unlock(&dbg_lock); +} + +#ifndef __UBOOT__ +void ubifs_dump_budg(struct ubifs_info *c, const struct ubifs_budg_info *bi) +{ + int i; + struct rb_node *rb; + struct ubifs_bud *bud; + struct ubifs_gced_idx_leb *idx_gc; + long long available, outstanding, free; + + spin_lock(&c->space_lock); + spin_lock(&dbg_lock); + pr_err("(pid %d) Budgeting info: data budget sum %lld, total budget sum %lld\n", + current->pid, bi->data_growth + bi->dd_growth, + bi->data_growth + bi->dd_growth + bi->idx_growth); + pr_err("\tbudg_data_growth %lld, budg_dd_growth %lld, budg_idx_growth %lld\n", + bi->data_growth, bi->dd_growth, bi->idx_growth); + pr_err("\tmin_idx_lebs %d, old_idx_sz %llu, uncommitted_idx %lld\n", + bi->min_idx_lebs, bi->old_idx_sz, bi->uncommitted_idx); + pr_err("\tpage_budget %d, inode_budget %d, dent_budget %d\n", + bi->page_budget, bi->inode_budget, bi->dent_budget); + pr_err("\tnospace %u, nospace_rp %u\n", bi->nospace, bi->nospace_rp); + pr_err("\tdark_wm %d, dead_wm %d, max_idx_node_sz %d\n", + c->dark_wm, c->dead_wm, c->max_idx_node_sz); + + if (bi != &c->bi) + /* + * If we are dumping saved budgeting data, do not print + * additional information which is about the current state, not + * the old one which corresponded to the saved budgeting data. + */ + goto out_unlock; + + pr_err("\tfreeable_cnt %d, calc_idx_sz %lld, idx_gc_cnt %d\n", + c->freeable_cnt, c->calc_idx_sz, c->idx_gc_cnt); + pr_err("\tdirty_pg_cnt %ld, dirty_zn_cnt %ld, clean_zn_cnt %ld\n", + atomic_long_read(&c->dirty_pg_cnt), + atomic_long_read(&c->dirty_zn_cnt), + atomic_long_read(&c->clean_zn_cnt)); + pr_err("\tgc_lnum %d, ihead_lnum %d\n", c->gc_lnum, c->ihead_lnum); + + /* If we are in R/O mode, journal heads do not exist */ + if (c->jheads) + for (i = 0; i < c->jhead_cnt; i++) + pr_err("\tjhead %s\t LEB %d\n", + dbg_jhead(c->jheads[i].wbuf.jhead), + c->jheads[i].wbuf.lnum); + for (rb = rb_first(&c->buds); rb; rb = rb_next(rb)) { + bud = rb_entry(rb, struct ubifs_bud, rb); + pr_err("\tbud LEB %d\n", bud->lnum); + } + list_for_each_entry(bud, &c->old_buds, list) + pr_err("\told bud LEB %d\n", bud->lnum); + list_for_each_entry(idx_gc, &c->idx_gc, list) + pr_err("\tGC'ed idx LEB %d unmap %d\n", + idx_gc->lnum, idx_gc->unmap); + pr_err("\tcommit state %d\n", c->cmt_state); + + /* Print budgeting predictions */ + available = ubifs_calc_available(c, c->bi.min_idx_lebs); + outstanding = c->bi.data_growth + c->bi.dd_growth; + free = ubifs_get_free_space_nolock(c); + pr_err("Budgeting predictions:\n"); + pr_err("\tavailable: %lld, outstanding %lld, free %lld\n", + available, outstanding, free); +out_unlock: + spin_unlock(&dbg_lock); + spin_unlock(&c->space_lock); +} +#else +void ubifs_dump_budg(struct ubifs_info *c, const struct ubifs_budg_info *bi) +{ +} +#endif + +void ubifs_dump_lprop(const struct ubifs_info *c, const struct ubifs_lprops *lp) +{ + int i, spc, dark = 0, dead = 0; + struct rb_node *rb; + struct ubifs_bud *bud; + + spc = lp->free + lp->dirty; + if (spc < c->dead_wm) + dead = spc; + else + dark = ubifs_calc_dark(c, spc); + + if (lp->flags & LPROPS_INDEX) + pr_err("LEB %-7d free %-8d dirty %-8d used %-8d free + dirty %-8d flags %#x (", + lp->lnum, lp->free, lp->dirty, c->leb_size - spc, spc, + lp->flags); + else + pr_err("LEB %-7d free %-8d dirty %-8d used %-8d free + dirty %-8d dark %-4d dead %-4d nodes fit %-3d flags %#-4x (", + lp->lnum, lp->free, lp->dirty, c->leb_size - spc, spc, + dark, dead, (int)(spc / UBIFS_MAX_NODE_SZ), lp->flags); + + if (lp->flags & LPROPS_TAKEN) { + if (lp->flags & LPROPS_INDEX) + pr_cont("index, taken"); + else + pr_cont("taken"); + } else { + const char *s; + + if (lp->flags & LPROPS_INDEX) { + switch (lp->flags & LPROPS_CAT_MASK) { + case LPROPS_DIRTY_IDX: + s = "dirty index"; + break; + case LPROPS_FRDI_IDX: + s = "freeable index"; + break; + default: + s = "index"; + } + } else { + switch (lp->flags & LPROPS_CAT_MASK) { + case LPROPS_UNCAT: + s = "not categorized"; + break; + case LPROPS_DIRTY: + s = "dirty"; + break; + case LPROPS_FREE: + s = "free"; + break; + case LPROPS_EMPTY: + s = "empty"; + break; + case LPROPS_FREEABLE: + s = "freeable"; + break; + default: + s = NULL; + break; + } + } + pr_cont("%s", s); + } + + for (rb = rb_first((struct rb_root *)&c->buds); rb; rb = rb_next(rb)) { + bud = rb_entry(rb, struct ubifs_bud, rb); + if (bud->lnum == lp->lnum) { + int head = 0; + for (i = 0; i < c->jhead_cnt; i++) { + /* + * Note, if we are in R/O mode or in the middle + * of mounting/re-mounting, the write-buffers do + * not exist. + */ + if (c->jheads && + lp->lnum == c->jheads[i].wbuf.lnum) { + pr_cont(", jhead %s", dbg_jhead(i)); + head = 1; + } + } + if (!head) + pr_cont(", bud of jhead %s", + dbg_jhead(bud->jhead)); + } + } + if (lp->lnum == c->gc_lnum) + pr_cont(", GC LEB"); + pr_cont(")\n"); +} + +void ubifs_dump_lprops(struct ubifs_info *c) +{ + int lnum, err; + struct ubifs_lprops lp; + struct ubifs_lp_stats lst; + + pr_err("(pid %d) start dumping LEB properties\n", current->pid); + ubifs_get_lp_stats(c, &lst); + ubifs_dump_lstats(&lst); + + for (lnum = c->main_first; lnum < c->leb_cnt; lnum++) { + err = ubifs_read_one_lp(c, lnum, &lp); + if (err) + ubifs_err("cannot read lprops for LEB %d", lnum); + + ubifs_dump_lprop(c, &lp); + } + pr_err("(pid %d) finish dumping LEB properties\n", current->pid); } -const char *dbg_key_str0(const struct ubifs_info *c, const union ubifs_key *key) +void ubifs_dump_lpt_info(struct ubifs_info *c) { - /* dbg_lock must be held */ - sprintf_key(c, key, dbg_key_buf0); - return dbg_key_buf0; + int i; + + spin_lock(&dbg_lock); + pr_err("(pid %d) dumping LPT information\n", current->pid); + pr_err("\tlpt_sz: %lld\n", c->lpt_sz); + pr_err("\tpnode_sz: %d\n", c->pnode_sz); + pr_err("\tnnode_sz: %d\n", c->nnode_sz); + pr_err("\tltab_sz: %d\n", c->ltab_sz); + pr_err("\tlsave_sz: %d\n", c->lsave_sz); + pr_err("\tbig_lpt: %d\n", c->big_lpt); + pr_err("\tlpt_hght: %d\n", c->lpt_hght); + pr_err("\tpnode_cnt: %d\n", c->pnode_cnt); + pr_err("\tnnode_cnt: %d\n", c->nnode_cnt); + pr_err("\tdirty_pn_cnt: %d\n", c->dirty_pn_cnt); + pr_err("\tdirty_nn_cnt: %d\n", c->dirty_nn_cnt); + pr_err("\tlsave_cnt: %d\n", c->lsave_cnt); + pr_err("\tspace_bits: %d\n", c->space_bits); + pr_err("\tlpt_lnum_bits: %d\n", c->lpt_lnum_bits); + pr_err("\tlpt_offs_bits: %d\n", c->lpt_offs_bits); + pr_err("\tlpt_spc_bits: %d\n", c->lpt_spc_bits); + pr_err("\tpcnt_bits: %d\n", c->pcnt_bits); + pr_err("\tlnum_bits: %d\n", c->lnum_bits); + pr_err("\tLPT root is at %d:%d\n", c->lpt_lnum, c->lpt_offs); + pr_err("\tLPT head is at %d:%d\n", + c->nhead_lnum, c->nhead_offs); + pr_err("\tLPT ltab is at %d:%d\n", c->ltab_lnum, c->ltab_offs); + if (c->big_lpt) + pr_err("\tLPT lsave is at %d:%d\n", + c->lsave_lnum, c->lsave_offs); + for (i = 0; i < c->lpt_lebs; i++) + pr_err("\tLPT LEB %d free %d dirty %d tgc %d cmt %d\n", + i + c->lpt_first, c->ltab[i].free, c->ltab[i].dirty, + c->ltab[i].tgc, c->ltab[i].cmt); + spin_unlock(&dbg_lock); +} + +void ubifs_dump_sleb(const struct ubifs_info *c, + const struct ubifs_scan_leb *sleb, int offs) +{ + struct ubifs_scan_node *snod; + + pr_err("(pid %d) start dumping scanned data from LEB %d:%d\n", + current->pid, sleb->lnum, offs); + + list_for_each_entry(snod, &sleb->nodes, list) { + cond_resched(); + pr_err("Dumping node at LEB %d:%d len %d\n", + sleb->lnum, snod->offs, snod->len); + ubifs_dump_node(c, snod->node); + } +} + +void ubifs_dump_leb(const struct ubifs_info *c, int lnum) +{ + struct ubifs_scan_leb *sleb; + struct ubifs_scan_node *snod; + void *buf; + + pr_err("(pid %d) start dumping LEB %d\n", current->pid, lnum); + + buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); + if (!buf) { + ubifs_err("cannot allocate memory for dumping LEB %d", lnum); + return; + } + + sleb = ubifs_scan(c, lnum, 0, buf, 0); + if (IS_ERR(sleb)) { + ubifs_err("scan error %d", (int)PTR_ERR(sleb)); + goto out; + } + + pr_err("LEB %d has %d nodes ending at %d\n", lnum, + sleb->nodes_cnt, sleb->endpt); + + list_for_each_entry(snod, &sleb->nodes, list) { + cond_resched(); + pr_err("Dumping node at LEB %d:%d len %d\n", lnum, + snod->offs, snod->len); + ubifs_dump_node(c, snod->node); + } + + pr_err("(pid %d) finish dumping LEB %d\n", current->pid, lnum); + ubifs_scan_destroy(sleb); + +out: + vfree(buf); + return; +} + +void ubifs_dump_znode(const struct ubifs_info *c, + const struct ubifs_znode *znode) +{ + int n; + const struct ubifs_zbranch *zbr; + char key_buf[DBG_KEY_BUF_LEN]; + + spin_lock(&dbg_lock); + if (znode->parent) + zbr = &znode->parent->zbranch[znode->iip]; + else + zbr = &c->zroot; + + pr_err("znode %p, LEB %d:%d len %d parent %p iip %d level %d child_cnt %d flags %lx\n", + znode, zbr->lnum, zbr->offs, zbr->len, znode->parent, znode->iip, + znode->level, znode->child_cnt, znode->flags); + + if (znode->child_cnt <= 0 || znode->child_cnt > c->fanout) { + spin_unlock(&dbg_lock); + return; + } + + pr_err("zbranches:\n"); + for (n = 0; n < znode->child_cnt; n++) { + zbr = &znode->zbranch[n]; + if (znode->level > 0) + pr_err("\t%d: znode %p LEB %d:%d len %d key %s\n", + n, zbr->znode, zbr->lnum, zbr->offs, zbr->len, + dbg_snprintf_key(c, &zbr->key, key_buf, + DBG_KEY_BUF_LEN)); + else + pr_err("\t%d: LNC %p LEB %d:%d len %d key %s\n", + n, zbr->znode, zbr->lnum, zbr->offs, zbr->len, + dbg_snprintf_key(c, &zbr->key, key_buf, + DBG_KEY_BUF_LEN)); + } + spin_unlock(&dbg_lock); +} + +void ubifs_dump_heap(struct ubifs_info *c, struct ubifs_lpt_heap *heap, int cat) +{ + int i; + + pr_err("(pid %d) start dumping heap cat %d (%d elements)\n", + current->pid, cat, heap->cnt); + for (i = 0; i < heap->cnt; i++) { + struct ubifs_lprops *lprops = heap->arr[i]; + + pr_err("\t%d. LEB %d hpos %d free %d dirty %d flags %d\n", + i, lprops->lnum, lprops->hpos, lprops->free, + lprops->dirty, lprops->flags); + } + pr_err("(pid %d) finish dumping heap\n", current->pid); +} + +void ubifs_dump_pnode(struct ubifs_info *c, struct ubifs_pnode *pnode, + struct ubifs_nnode *parent, int iip) +{ + int i; + + pr_err("(pid %d) dumping pnode:\n", current->pid); + pr_err("\taddress %zx parent %zx cnext %zx\n", + (size_t)pnode, (size_t)parent, (size_t)pnode->cnext); + pr_err("\tflags %lu iip %d level %d num %d\n", + pnode->flags, iip, pnode->level, pnode->num); + for (i = 0; i < UBIFS_LPT_FANOUT; i++) { + struct ubifs_lprops *lp = &pnode->lprops[i]; + + pr_err("\t%d: free %d dirty %d flags %d lnum %d\n", + i, lp->free, lp->dirty, lp->flags, lp->lnum); + } +} + +void ubifs_dump_tnc(struct ubifs_info *c) +{ + struct ubifs_znode *znode; + int level; + + pr_err("\n"); + pr_err("(pid %d) start dumping TNC tree\n", current->pid); + znode = ubifs_tnc_levelorder_next(c->zroot.znode, NULL); + level = znode->level; + pr_err("== Level %d ==\n", level); + while (znode) { + if (level != znode->level) { + level = znode->level; + pr_err("== Level %d ==\n", level); + } + ubifs_dump_znode(c, znode); + znode = ubifs_tnc_levelorder_next(c->zroot.znode, znode); + } + pr_err("(pid %d) finish dumping TNC tree\n", current->pid); } -const char *dbg_key_str1(const struct ubifs_info *c, const union ubifs_key *key) +static int dump_znode(struct ubifs_info *c, struct ubifs_znode *znode, + void *priv) { - /* dbg_lock must be held */ - sprintf_key(c, key, dbg_key_buf1); - return dbg_key_buf1; + ubifs_dump_znode(c, znode); + return 0; } /** - * ubifs_debugging_init - initialize UBIFS debugging. + * ubifs_dump_index - dump the on-flash index. * @c: UBIFS file-system description object * - * This function initializes debugging-related data for the file system. - * Returns zero in case of success and a negative error code in case of - * failure. + * This function dumps whole UBIFS indexing B-tree, unlike 'ubifs_dump_tnc()' + * which dumps only in-memory znodes and does not read znodes which from flash. */ -int ubifs_debugging_init(struct ubifs_info *c) +void ubifs_dump_index(struct ubifs_info *c) { - c->dbg = kzalloc(sizeof(struct ubifs_debug_info), GFP_KERNEL); - if (!c->dbg) - return -ENOMEM; + dbg_walk_index(c, NULL, dump_znode, NULL); +} + +#ifndef __UBOOT__ +/** + * dbg_save_space_info - save information about flash space. + * @c: UBIFS file-system description object + * + * This function saves information about UBIFS free space, dirty space, etc, in + * order to check it later. + */ +void dbg_save_space_info(struct ubifs_info *c) +{ + struct ubifs_debug_info *d = c->dbg; + int freeable_cnt; + + spin_lock(&c->space_lock); + memcpy(&d->saved_lst, &c->lst, sizeof(struct ubifs_lp_stats)); + memcpy(&d->saved_bi, &c->bi, sizeof(struct ubifs_budg_info)); + d->saved_idx_gc_cnt = c->idx_gc_cnt; + + /* + * We use a dirty hack here and zero out @c->freeable_cnt, because it + * affects the free space calculations, and UBIFS might not know about + * all freeable eraseblocks. Indeed, we know about freeable eraseblocks + * only when we read their lprops, and we do this only lazily, upon the + * need. So at any given point of time @c->freeable_cnt might be not + * exactly accurate. + * + * Just one example about the issue we hit when we did not zero + * @c->freeable_cnt. + * 1. The file-system is mounted R/O, c->freeable_cnt is %0. We save the + * amount of free space in @d->saved_free + * 2. We re-mount R/W, which makes UBIFS to read the "lsave" + * information from flash, where we cache LEBs from various + * categories ('ubifs_remount_fs()' -> 'ubifs_lpt_init()' + * -> 'lpt_init_wr()' -> 'read_lsave()' -> 'ubifs_lpt_lookup()' + * -> 'ubifs_get_pnode()' -> 'update_cats()' + * -> 'ubifs_add_to_cat()'). + * 3. Lsave contains a freeable eraseblock, and @c->freeable_cnt + * becomes %1. + * 4. We calculate the amount of free space when the re-mount is + * finished in 'dbg_check_space_info()' and it does not match + * @d->saved_free. + */ + freeable_cnt = c->freeable_cnt; + c->freeable_cnt = 0; + d->saved_free = ubifs_get_free_space_nolock(c); + c->freeable_cnt = freeable_cnt; + spin_unlock(&c->space_lock); +} + +/** + * dbg_check_space_info - check flash space information. + * @c: UBIFS file-system description object + * + * This function compares current flash space information with the information + * which was saved when the 'dbg_save_space_info()' function was called. + * Returns zero if the information has not changed, and %-EINVAL it it has + * changed. + */ +int dbg_check_space_info(struct ubifs_info *c) +{ + struct ubifs_debug_info *d = c->dbg; + struct ubifs_lp_stats lst; + long long free; + int freeable_cnt; - c->dbg->buf = vmalloc(c->leb_size); - if (!c->dbg->buf) + spin_lock(&c->space_lock); + freeable_cnt = c->freeable_cnt; + c->freeable_cnt = 0; + free = ubifs_get_free_space_nolock(c); + c->freeable_cnt = freeable_cnt; + spin_unlock(&c->space_lock); + + if (free != d->saved_free) { + ubifs_err("free space changed from %lld to %lld", + d->saved_free, free); goto out; + } return 0; out: - kfree(c->dbg); - return -ENOMEM; + ubifs_msg("saved lprops statistics dump"); + ubifs_dump_lstats(&d->saved_lst); + ubifs_msg("saved budgeting info dump"); + ubifs_dump_budg(c, &d->saved_bi); + ubifs_msg("saved idx_gc_cnt %d", d->saved_idx_gc_cnt); + ubifs_msg("current lprops statistics dump"); + ubifs_get_lp_stats(c, &lst); + ubifs_dump_lstats(&lst); + ubifs_msg("current budgeting info dump"); + ubifs_dump_budg(c, &c->bi); + dump_stack(); + return -EINVAL; } /** - * ubifs_debugging_exit - free debugging data. + * dbg_check_synced_i_size - check synchronized inode size. * @c: UBIFS file-system description object + * @inode: inode to check + * + * If inode is clean, synchronized inode size has to be equivalent to current + * inode size. This function has to be called only for locked inodes (@i_mutex + * has to be locked). Returns %0 if synchronized inode size if correct, and + * %-EINVAL if not. */ -void ubifs_debugging_exit(struct ubifs_info *c) +int dbg_check_synced_i_size(const struct ubifs_info *c, struct inode *inode) { - vfree(c->dbg->buf); - kfree(c->dbg); + int err = 0; + struct ubifs_inode *ui = ubifs_inode(inode); + + if (!dbg_is_chk_gen(c)) + return 0; + if (!S_ISREG(inode->i_mode)) + return 0; + + mutex_lock(&ui->ui_mutex); + spin_lock(&ui->ui_lock); + if (ui->ui_size != ui->synced_i_size && !ui->dirty) { + ubifs_err("ui_size is %lld, synced_i_size is %lld, but inode is clean", + ui->ui_size, ui->synced_i_size); + ubifs_err("i_ino %lu, i_mode %#x, i_size %lld", inode->i_ino, + inode->i_mode, i_size_read(inode)); + dump_stack(); + err = -EINVAL; + } + spin_unlock(&ui->ui_lock); + mutex_unlock(&ui->ui_mutex); + return err; +} + +/* + * dbg_check_dir - check directory inode size and link count. + * @c: UBIFS file-system description object + * @dir: the directory to calculate size for + * @size: the result is returned here + * + * This function makes sure that directory size and link count are correct. + * Returns zero in case of success and a negative error code in case of + * failure. + * + * Note, it is good idea to make sure the @dir->i_mutex is locked before + * calling this function. + */ +int dbg_check_dir(struct ubifs_info *c, const struct inode *dir) +{ + unsigned int nlink = 2; + union ubifs_key key; + struct ubifs_dent_node *dent, *pdent = NULL; + struct qstr nm = { .name = NULL }; + loff_t size = UBIFS_INO_NODE_SZ; + + if (!dbg_is_chk_gen(c)) + return 0; + + if (!S_ISDIR(dir->i_mode)) + return 0; + + lowest_dent_key(c, &key, dir->i_ino); + while (1) { + int err; + + dent = ubifs_tnc_next_ent(c, &key, &nm); + if (IS_ERR(dent)) { + err = PTR_ERR(dent); + if (err == -ENOENT) + break; + return err; + } + + nm.name = dent->name; + nm.len = le16_to_cpu(dent->nlen); + size += CALC_DENT_SIZE(nm.len); + if (dent->type == UBIFS_ITYPE_DIR) + nlink += 1; + kfree(pdent); + pdent = dent; + key_read(c, &dent->key, &key); + } + kfree(pdent); + + if (i_size_read(dir) != size) { + ubifs_err("directory inode %lu has size %llu, but calculated size is %llu", + dir->i_ino, (unsigned long long)i_size_read(dir), + (unsigned long long)size); + ubifs_dump_inode(c, dir); + dump_stack(); + return -EINVAL; + } + if (dir->i_nlink != nlink) { + ubifs_err("directory inode %lu has nlink %u, but calculated nlink is %u", + dir->i_ino, dir->i_nlink, nlink); + ubifs_dump_inode(c, dir); + dump_stack(); + return -EINVAL; + } + + return 0; +} + +/** + * dbg_check_key_order - make sure that colliding keys are properly ordered. + * @c: UBIFS file-system description object + * @zbr1: first zbranch + * @zbr2: following zbranch + * + * In UBIFS indexing B-tree colliding keys has to be sorted in binary order of + * names of the direntries/xentries which are referred by the keys. This + * function reads direntries/xentries referred by @zbr1 and @zbr2 and makes + * sure the name of direntry/xentry referred by @zbr1 is less than + * direntry/xentry referred by @zbr2. Returns zero if this is true, %1 if not, + * and a negative error code in case of failure. + */ +static int dbg_check_key_order(struct ubifs_info *c, struct ubifs_zbranch *zbr1, + struct ubifs_zbranch *zbr2) +{ + int err, nlen1, nlen2, cmp; + struct ubifs_dent_node *dent1, *dent2; + union ubifs_key key; + char key_buf[DBG_KEY_BUF_LEN]; + + ubifs_assert(!keys_cmp(c, &zbr1->key, &zbr2->key)); + dent1 = kmalloc(UBIFS_MAX_DENT_NODE_SZ, GFP_NOFS); + if (!dent1) + return -ENOMEM; + dent2 = kmalloc(UBIFS_MAX_DENT_NODE_SZ, GFP_NOFS); + if (!dent2) { + err = -ENOMEM; + goto out_free; + } + + err = ubifs_tnc_read_node(c, zbr1, dent1); + if (err) + goto out_free; + err = ubifs_validate_entry(c, dent1); + if (err) + goto out_free; + + err = ubifs_tnc_read_node(c, zbr2, dent2); + if (err) + goto out_free; + err = ubifs_validate_entry(c, dent2); + if (err) + goto out_free; + + /* Make sure node keys are the same as in zbranch */ + err = 1; + key_read(c, &dent1->key, &key); + if (keys_cmp(c, &zbr1->key, &key)) { + ubifs_err("1st entry at %d:%d has key %s", zbr1->lnum, + zbr1->offs, dbg_snprintf_key(c, &key, key_buf, + DBG_KEY_BUF_LEN)); + ubifs_err("but it should have key %s according to tnc", + dbg_snprintf_key(c, &zbr1->key, key_buf, + DBG_KEY_BUF_LEN)); + ubifs_dump_node(c, dent1); + goto out_free; + } + + key_read(c, &dent2->key, &key); + if (keys_cmp(c, &zbr2->key, &key)) { + ubifs_err("2nd entry at %d:%d has key %s", zbr1->lnum, + zbr1->offs, dbg_snprintf_key(c, &key, key_buf, + DBG_KEY_BUF_LEN)); + ubifs_err("but it should have key %s according to tnc", + dbg_snprintf_key(c, &zbr2->key, key_buf, + DBG_KEY_BUF_LEN)); + ubifs_dump_node(c, dent2); + goto out_free; + } + + nlen1 = le16_to_cpu(dent1->nlen); + nlen2 = le16_to_cpu(dent2->nlen); + + cmp = memcmp(dent1->name, dent2->name, min_t(int, nlen1, nlen2)); + if (cmp < 0 || (cmp == 0 && nlen1 < nlen2)) { + err = 0; + goto out_free; + } + if (cmp == 0 && nlen1 == nlen2) + ubifs_err("2 xent/dent nodes with the same name"); + else + ubifs_err("bad order of colliding key %s", + dbg_snprintf_key(c, &key, key_buf, DBG_KEY_BUF_LEN)); + + ubifs_msg("first node at %d:%d\n", zbr1->lnum, zbr1->offs); + ubifs_dump_node(c, dent1); + ubifs_msg("second node at %d:%d\n", zbr2->lnum, zbr2->offs); + ubifs_dump_node(c, dent2); + +out_free: + kfree(dent2); + kfree(dent1); + return err; } -#endif /* CONFIG_UBIFS_FS_DEBUG */ +/** + * dbg_check_znode - check if znode is all right. + * @c: UBIFS file-system description object + * @zbr: zbranch which points to this znode + * + * This function makes sure that znode referred to by @zbr is all right. + * Returns zero if it is, and %-EINVAL if it is not. + */ +static int dbg_check_znode(struct ubifs_info *c, struct ubifs_zbranch *zbr) +{ + struct ubifs_znode *znode = zbr->znode; + struct ubifs_znode *zp = znode->parent; + int n, err, cmp; + + if (znode->child_cnt <= 0 || znode->child_cnt > c->fanout) { + err = 1; + goto out; + } + if (znode->level < 0) { + err = 2; + goto out; + } + if (znode->iip < 0 || znode->iip >= c->fanout) { + err = 3; + goto out; + } + + if (zbr->len == 0) + /* Only dirty zbranch may have no on-flash nodes */ + if (!ubifs_zn_dirty(znode)) { + err = 4; + goto out; + } + + if (ubifs_zn_dirty(znode)) { + /* + * If znode is dirty, its parent has to be dirty as well. The + * order of the operation is important, so we have to have + * memory barriers. + */ + smp_mb(); + if (zp && !ubifs_zn_dirty(zp)) { + /* + * The dirty flag is atomic and is cleared outside the + * TNC mutex, so znode's dirty flag may now have + * been cleared. The child is always cleared before the + * parent, so we just need to check again. + */ + smp_mb(); + if (ubifs_zn_dirty(znode)) { + err = 5; + goto out; + } + } + } + + if (zp) { + const union ubifs_key *min, *max; + + if (znode->level != zp->level - 1) { + err = 6; + goto out; + } + + /* Make sure the 'parent' pointer in our znode is correct */ + err = ubifs_search_zbranch(c, zp, &zbr->key, &n); + if (!err) { + /* This zbranch does not exist in the parent */ + err = 7; + goto out; + } + + if (znode->iip >= zp->child_cnt) { + err = 8; + goto out; + } + + if (znode->iip != n) { + /* This may happen only in case of collisions */ + if (keys_cmp(c, &zp->zbranch[n].key, + &zp->zbranch[znode->iip].key)) { + err = 9; + goto out; + } + n = znode->iip; + } + + /* + * Make sure that the first key in our znode is greater than or + * equal to the key in the pointing zbranch. + */ + min = &zbr->key; + cmp = keys_cmp(c, min, &znode->zbranch[0].key); + if (cmp == 1) { + err = 10; + goto out; + } + + if (n + 1 < zp->child_cnt) { + max = &zp->zbranch[n + 1].key; + + /* + * Make sure the last key in our znode is less or + * equivalent than the key in the zbranch which goes + * after our pointing zbranch. + */ + cmp = keys_cmp(c, max, + &znode->zbranch[znode->child_cnt - 1].key); + if (cmp == -1) { + err = 11; + goto out; + } + } + } else { + /* This may only be root znode */ + if (zbr != &c->zroot) { + err = 12; + goto out; + } + } + + /* + * Make sure that next key is greater or equivalent then the previous + * one. + */ + for (n = 1; n < znode->child_cnt; n++) { + cmp = keys_cmp(c, &znode->zbranch[n - 1].key, + &znode->zbranch[n].key); + if (cmp > 0) { + err = 13; + goto out; + } + if (cmp == 0) { + /* This can only be keys with colliding hash */ + if (!is_hash_key(c, &znode->zbranch[n].key)) { + err = 14; + goto out; + } + + if (znode->level != 0 || c->replaying) + continue; + + /* + * Colliding keys should follow binary order of + * corresponding xentry/dentry names. + */ + err = dbg_check_key_order(c, &znode->zbranch[n - 1], + &znode->zbranch[n]); + if (err < 0) + return err; + if (err) { + err = 15; + goto out; + } + } + } + + for (n = 0; n < znode->child_cnt; n++) { + if (!znode->zbranch[n].znode && + (znode->zbranch[n].lnum == 0 || + znode->zbranch[n].len == 0)) { + err = 16; + goto out; + } + + if (znode->zbranch[n].lnum != 0 && + znode->zbranch[n].len == 0) { + err = 17; + goto out; + } + + if (znode->zbranch[n].lnum == 0 && + znode->zbranch[n].len != 0) { + err = 18; + goto out; + } + + if (znode->zbranch[n].lnum == 0 && + znode->zbranch[n].offs != 0) { + err = 19; + goto out; + } + + if (znode->level != 0 && znode->zbranch[n].znode) + if (znode->zbranch[n].znode->parent != znode) { + err = 20; + goto out; + } + } + + return 0; + +out: + ubifs_err("failed, error %d", err); + ubifs_msg("dump of the znode"); + ubifs_dump_znode(c, znode); + if (zp) { + ubifs_msg("dump of the parent znode"); + ubifs_dump_znode(c, zp); + } + dump_stack(); + return -EINVAL; +} +#else + +int dbg_check_dir(struct ubifs_info *c, const struct inode *dir) +{ + return 0; +} + +void dbg_debugfs_exit_fs(struct ubifs_info *c) +{ + return; +} + +int ubifs_debugging_init(struct ubifs_info *c) +{ + return 0; +} +void ubifs_debugging_exit(struct ubifs_info *c) +{ +} +int dbg_check_filesystem(struct ubifs_info *c) +{ + return 0; +} +int dbg_debugfs_init_fs(struct ubifs_info *c) +{ + return 0; +} +#endif + +#ifndef __UBOOT__ +/** + * dbg_check_tnc - check TNC tree. + * @c: UBIFS file-system description object + * @extra: do extra checks that are possible at start commit + * + * This function traverses whole TNC tree and checks every znode. Returns zero + * if everything is all right and %-EINVAL if something is wrong with TNC. + */ +int dbg_check_tnc(struct ubifs_info *c, int extra) +{ + struct ubifs_znode *znode; + long clean_cnt = 0, dirty_cnt = 0; + int err, last; + + if (!dbg_is_chk_index(c)) + return 0; + + ubifs_assert(mutex_is_locked(&c->tnc_mutex)); + if (!c->zroot.znode) + return 0; + + znode = ubifs_tnc_postorder_first(c->zroot.znode); + while (1) { + struct ubifs_znode *prev; + struct ubifs_zbranch *zbr; + + if (!znode->parent) + zbr = &c->zroot; + else + zbr = &znode->parent->zbranch[znode->iip]; + + err = dbg_check_znode(c, zbr); + if (err) + return err; + + if (extra) { + if (ubifs_zn_dirty(znode)) + dirty_cnt += 1; + else + clean_cnt += 1; + } + + prev = znode; + znode = ubifs_tnc_postorder_next(znode); + if (!znode) + break; + + /* + * If the last key of this znode is equivalent to the first key + * of the next znode (collision), then check order of the keys. + */ + last = prev->child_cnt - 1; + if (prev->level == 0 && znode->level == 0 && !c->replaying && + !keys_cmp(c, &prev->zbranch[last].key, + &znode->zbranch[0].key)) { + err = dbg_check_key_order(c, &prev->zbranch[last], + &znode->zbranch[0]); + if (err < 0) + return err; + if (err) { + ubifs_msg("first znode"); + ubifs_dump_znode(c, prev); + ubifs_msg("second znode"); + ubifs_dump_znode(c, znode); + return -EINVAL; + } + } + } + + if (extra) { + if (clean_cnt != atomic_long_read(&c->clean_zn_cnt)) { + ubifs_err("incorrect clean_zn_cnt %ld, calculated %ld", + atomic_long_read(&c->clean_zn_cnt), + clean_cnt); + return -EINVAL; + } + if (dirty_cnt != atomic_long_read(&c->dirty_zn_cnt)) { + ubifs_err("incorrect dirty_zn_cnt %ld, calculated %ld", + atomic_long_read(&c->dirty_zn_cnt), + dirty_cnt); + return -EINVAL; + } + } + + return 0; +} +#else +int dbg_check_tnc(struct ubifs_info *c, int extra) +{ + return 0; +} +#endif + +/** + * dbg_walk_index - walk the on-flash index. + * @c: UBIFS file-system description object + * @leaf_cb: called for each leaf node + * @znode_cb: called for each indexing node + * @priv: private data which is passed to callbacks + * + * This function walks the UBIFS index and calls the @leaf_cb for each leaf + * node and @znode_cb for each indexing node. Returns zero in case of success + * and a negative error code in case of failure. + * + * It would be better if this function removed every znode it pulled to into + * the TNC, so that the behavior more closely matched the non-debugging + * behavior. + */ +int dbg_walk_index(struct ubifs_info *c, dbg_leaf_callback leaf_cb, + dbg_znode_callback znode_cb, void *priv) +{ + int err; + struct ubifs_zbranch *zbr; + struct ubifs_znode *znode, *child; + + mutex_lock(&c->tnc_mutex); + /* If the root indexing node is not in TNC - pull it */ + if (!c->zroot.znode) { + c->zroot.znode = ubifs_load_znode(c, &c->zroot, NULL, 0); + if (IS_ERR(c->zroot.znode)) { + err = PTR_ERR(c->zroot.znode); + c->zroot.znode = NULL; + goto out_unlock; + } + } + + /* + * We are going to traverse the indexing tree in the postorder manner. + * Go down and find the leftmost indexing node where we are going to + * start from. + */ + znode = c->zroot.znode; + while (znode->level > 0) { + zbr = &znode->zbranch[0]; + child = zbr->znode; + if (!child) { + child = ubifs_load_znode(c, zbr, znode, 0); + if (IS_ERR(child)) { + err = PTR_ERR(child); + goto out_unlock; + } + zbr->znode = child; + } + + znode = child; + } + + /* Iterate over all indexing nodes */ + while (1) { + int idx; + + cond_resched(); + + if (znode_cb) { + err = znode_cb(c, znode, priv); + if (err) { + ubifs_err("znode checking function returned error %d", + err); + ubifs_dump_znode(c, znode); + goto out_dump; + } + } + if (leaf_cb && znode->level == 0) { + for (idx = 0; idx < znode->child_cnt; idx++) { + zbr = &znode->zbranch[idx]; + err = leaf_cb(c, zbr, priv); + if (err) { + ubifs_err("leaf checking function returned error %d, for leaf at LEB %d:%d", + err, zbr->lnum, zbr->offs); + goto out_dump; + } + } + } + + if (!znode->parent) + break; + + idx = znode->iip + 1; + znode = znode->parent; + if (idx < znode->child_cnt) { + /* Switch to the next index in the parent */ + zbr = &znode->zbranch[idx]; + child = zbr->znode; + if (!child) { + child = ubifs_load_znode(c, zbr, znode, idx); + if (IS_ERR(child)) { + err = PTR_ERR(child); + goto out_unlock; + } + zbr->znode = child; + } + znode = child; + } else + /* + * This is the last child, switch to the parent and + * continue. + */ + continue; + + /* Go to the lowest leftmost znode in the new sub-tree */ + while (znode->level > 0) { + zbr = &znode->zbranch[0]; + child = zbr->znode; + if (!child) { + child = ubifs_load_znode(c, zbr, znode, 0); + if (IS_ERR(child)) { + err = PTR_ERR(child); + goto out_unlock; + } + zbr->znode = child; + } + znode = child; + } + } + + mutex_unlock(&c->tnc_mutex); + return 0; + +out_dump: + if (znode->parent) + zbr = &znode->parent->zbranch[znode->iip]; + else + zbr = &c->zroot; + ubifs_msg("dump of znode at LEB %d:%d", zbr->lnum, zbr->offs); + ubifs_dump_znode(c, znode); +out_unlock: + mutex_unlock(&c->tnc_mutex); + return err; +} + +/** + * add_size - add znode size to partially calculated index size. + * @c: UBIFS file-system description object + * @znode: znode to add size for + * @priv: partially calculated index size + * + * This is a helper function for 'dbg_check_idx_size()' which is called for + * every indexing node and adds its size to the 'long long' variable pointed to + * by @priv. + */ +static int add_size(struct ubifs_info *c, struct ubifs_znode *znode, void *priv) +{ + long long *idx_size = priv; + int add; + + add = ubifs_idx_node_sz(c, znode->child_cnt); + add = ALIGN(add, 8); + *idx_size += add; + return 0; +} + +/** + * dbg_check_idx_size - check index size. + * @c: UBIFS file-system description object + * @idx_size: size to check + * + * This function walks the UBIFS index, calculates its size and checks that the + * size is equivalent to @idx_size. Returns zero in case of success and a + * negative error code in case of failure. + */ +int dbg_check_idx_size(struct ubifs_info *c, long long idx_size) +{ + int err; + long long calc = 0; + + if (!dbg_is_chk_index(c)) + return 0; + + err = dbg_walk_index(c, NULL, add_size, &calc); + if (err) { + ubifs_err("error %d while walking the index", err); + return err; + } + + if (calc != idx_size) { + ubifs_err("index size check failed: calculated size is %lld, should be %lld", + calc, idx_size); + dump_stack(); + return -EINVAL; + } + + return 0; +} + +#ifndef __UBOOT__ +/** + * struct fsck_inode - information about an inode used when checking the file-system. + * @rb: link in the RB-tree of inodes + * @inum: inode number + * @mode: inode type, permissions, etc + * @nlink: inode link count + * @xattr_cnt: count of extended attributes + * @references: how many directory/xattr entries refer this inode (calculated + * while walking the index) + * @calc_cnt: for directory inode count of child directories + * @size: inode size (read from on-flash inode) + * @xattr_sz: summary size of all extended attributes (read from on-flash + * inode) + * @calc_sz: for directories calculated directory size + * @calc_xcnt: count of extended attributes + * @calc_xsz: calculated summary size of all extended attributes + * @xattr_nms: sum of lengths of all extended attribute names belonging to this + * inode (read from on-flash inode) + * @calc_xnms: calculated sum of lengths of all extended attribute names + */ +struct fsck_inode { + struct rb_node rb; + ino_t inum; + umode_t mode; + unsigned int nlink; + unsigned int xattr_cnt; + int references; + int calc_cnt; + long long size; + unsigned int xattr_sz; + long long calc_sz; + long long calc_xcnt; + long long calc_xsz; + unsigned int xattr_nms; + long long calc_xnms; +}; + +/** + * struct fsck_data - private FS checking information. + * @inodes: RB-tree of all inodes (contains @struct fsck_inode objects) + */ +struct fsck_data { + struct rb_root inodes; +}; + +/** + * add_inode - add inode information to RB-tree of inodes. + * @c: UBIFS file-system description object + * @fsckd: FS checking information + * @ino: raw UBIFS inode to add + * + * This is a helper function for 'check_leaf()' which adds information about + * inode @ino to the RB-tree of inodes. Returns inode information pointer in + * case of success and a negative error code in case of failure. + */ +static struct fsck_inode *add_inode(struct ubifs_info *c, + struct fsck_data *fsckd, + struct ubifs_ino_node *ino) +{ + struct rb_node **p, *parent = NULL; + struct fsck_inode *fscki; + ino_t inum = key_inum_flash(c, &ino->key); + struct inode *inode; + struct ubifs_inode *ui; + + p = &fsckd->inodes.rb_node; + while (*p) { + parent = *p; + fscki = rb_entry(parent, struct fsck_inode, rb); + if (inum < fscki->inum) + p = &(*p)->rb_left; + else if (inum > fscki->inum) + p = &(*p)->rb_right; + else + return fscki; + } + + if (inum > c->highest_inum) { + ubifs_err("too high inode number, max. is %lu", + (unsigned long)c->highest_inum); + return ERR_PTR(-EINVAL); + } + + fscki = kzalloc(sizeof(struct fsck_inode), GFP_NOFS); + if (!fscki) + return ERR_PTR(-ENOMEM); + + inode = ilookup(c->vfs_sb, inum); + + fscki->inum = inum; + /* + * If the inode is present in the VFS inode cache, use it instead of + * the on-flash inode which might be out-of-date. E.g., the size might + * be out-of-date. If we do not do this, the following may happen, for + * example: + * 1. A power cut happens + * 2. We mount the file-system R/O, the replay process fixes up the + * inode size in the VFS cache, but on on-flash. + * 3. 'check_leaf()' fails because it hits a data node beyond inode + * size. + */ + if (!inode) { + fscki->nlink = le32_to_cpu(ino->nlink); + fscki->size = le64_to_cpu(ino->size); + fscki->xattr_cnt = le32_to_cpu(ino->xattr_cnt); + fscki->xattr_sz = le32_to_cpu(ino->xattr_size); + fscki->xattr_nms = le32_to_cpu(ino->xattr_names); + fscki->mode = le32_to_cpu(ino->mode); + } else { + ui = ubifs_inode(inode); + fscki->nlink = inode->i_nlink; + fscki->size = inode->i_size; + fscki->xattr_cnt = ui->xattr_cnt; + fscki->xattr_sz = ui->xattr_size; + fscki->xattr_nms = ui->xattr_names; + fscki->mode = inode->i_mode; + iput(inode); + } + + if (S_ISDIR(fscki->mode)) { + fscki->calc_sz = UBIFS_INO_NODE_SZ; + fscki->calc_cnt = 2; + } + + rb_link_node(&fscki->rb, parent, p); + rb_insert_color(&fscki->rb, &fsckd->inodes); + + return fscki; +} + +/** + * search_inode - search inode in the RB-tree of inodes. + * @fsckd: FS checking information + * @inum: inode number to search + * + * This is a helper function for 'check_leaf()' which searches inode @inum in + * the RB-tree of inodes and returns an inode information pointer or %NULL if + * the inode was not found. + */ +static struct fsck_inode *search_inode(struct fsck_data *fsckd, ino_t inum) +{ + struct rb_node *p; + struct fsck_inode *fscki; + + p = fsckd->inodes.rb_node; + while (p) { + fscki = rb_entry(p, struct fsck_inode, rb); + if (inum < fscki->inum) + p = p->rb_left; + else if (inum > fscki->inum) + p = p->rb_right; + else + return fscki; + } + return NULL; +} + +/** + * read_add_inode - read inode node and add it to RB-tree of inodes. + * @c: UBIFS file-system description object + * @fsckd: FS checking information + * @inum: inode number to read + * + * This is a helper function for 'check_leaf()' which finds inode node @inum in + * the index, reads it, and adds it to the RB-tree of inodes. Returns inode + * information pointer in case of success and a negative error code in case of + * failure. + */ +static struct fsck_inode *read_add_inode(struct ubifs_info *c, + struct fsck_data *fsckd, ino_t inum) +{ + int n, err; + union ubifs_key key; + struct ubifs_znode *znode; + struct ubifs_zbranch *zbr; + struct ubifs_ino_node *ino; + struct fsck_inode *fscki; + + fscki = search_inode(fsckd, inum); + if (fscki) + return fscki; + + ino_key_init(c, &key, inum); + err = ubifs_lookup_level0(c, &key, &znode, &n); + if (!err) { + ubifs_err("inode %lu not found in index", (unsigned long)inum); + return ERR_PTR(-ENOENT); + } else if (err < 0) { + ubifs_err("error %d while looking up inode %lu", + err, (unsigned long)inum); + return ERR_PTR(err); + } + + zbr = &znode->zbranch[n]; + if (zbr->len < UBIFS_INO_NODE_SZ) { + ubifs_err("bad node %lu node length %d", + (unsigned long)inum, zbr->len); + return ERR_PTR(-EINVAL); + } + + ino = kmalloc(zbr->len, GFP_NOFS); + if (!ino) + return ERR_PTR(-ENOMEM); + + err = ubifs_tnc_read_node(c, zbr, ino); + if (err) { + ubifs_err("cannot read inode node at LEB %d:%d, error %d", + zbr->lnum, zbr->offs, err); + kfree(ino); + return ERR_PTR(err); + } + + fscki = add_inode(c, fsckd, ino); + kfree(ino); + if (IS_ERR(fscki)) { + ubifs_err("error %ld while adding inode %lu node", + PTR_ERR(fscki), (unsigned long)inum); + return fscki; + } + + return fscki; +} + +/** + * check_leaf - check leaf node. + * @c: UBIFS file-system description object + * @zbr: zbranch of the leaf node to check + * @priv: FS checking information + * + * This is a helper function for 'dbg_check_filesystem()' which is called for + * every single leaf node while walking the indexing tree. It checks that the + * leaf node referred from the indexing tree exists, has correct CRC, and does + * some other basic validation. This function is also responsible for building + * an RB-tree of inodes - it adds all inodes into the RB-tree. It also + * calculates reference count, size, etc for each inode in order to later + * compare them to the information stored inside the inodes and detect possible + * inconsistencies. Returns zero in case of success and a negative error code + * in case of failure. + */ +static int check_leaf(struct ubifs_info *c, struct ubifs_zbranch *zbr, + void *priv) +{ + ino_t inum; + void *node; + struct ubifs_ch *ch; + int err, type = key_type(c, &zbr->key); + struct fsck_inode *fscki; + + if (zbr->len < UBIFS_CH_SZ) { + ubifs_err("bad leaf length %d (LEB %d:%d)", + zbr->len, zbr->lnum, zbr->offs); + return -EINVAL; + } + + node = kmalloc(zbr->len, GFP_NOFS); + if (!node) + return -ENOMEM; + + err = ubifs_tnc_read_node(c, zbr, node); + if (err) { + ubifs_err("cannot read leaf node at LEB %d:%d, error %d", + zbr->lnum, zbr->offs, err); + goto out_free; + } + + /* If this is an inode node, add it to RB-tree of inodes */ + if (type == UBIFS_INO_KEY) { + fscki = add_inode(c, priv, node); + if (IS_ERR(fscki)) { + err = PTR_ERR(fscki); + ubifs_err("error %d while adding inode node", err); + goto out_dump; + } + goto out; + } + + if (type != UBIFS_DENT_KEY && type != UBIFS_XENT_KEY && + type != UBIFS_DATA_KEY) { + ubifs_err("unexpected node type %d at LEB %d:%d", + type, zbr->lnum, zbr->offs); + err = -EINVAL; + goto out_free; + } + + ch = node; + if (le64_to_cpu(ch->sqnum) > c->max_sqnum) { + ubifs_err("too high sequence number, max. is %llu", + c->max_sqnum); + err = -EINVAL; + goto out_dump; + } + + if (type == UBIFS_DATA_KEY) { + long long blk_offs; + struct ubifs_data_node *dn = node; + + /* + * Search the inode node this data node belongs to and insert + * it to the RB-tree of inodes. + */ + inum = key_inum_flash(c, &dn->key); + fscki = read_add_inode(c, priv, inum); + if (IS_ERR(fscki)) { + err = PTR_ERR(fscki); + ubifs_err("error %d while processing data node and trying to find inode node %lu", + err, (unsigned long)inum); + goto out_dump; + } + + /* Make sure the data node is within inode size */ + blk_offs = key_block_flash(c, &dn->key); + blk_offs <<= UBIFS_BLOCK_SHIFT; + blk_offs += le32_to_cpu(dn->size); + if (blk_offs > fscki->size) { + ubifs_err("data node at LEB %d:%d is not within inode size %lld", + zbr->lnum, zbr->offs, fscki->size); + err = -EINVAL; + goto out_dump; + } + } else { + int nlen; + struct ubifs_dent_node *dent = node; + struct fsck_inode *fscki1; + + err = ubifs_validate_entry(c, dent); + if (err) + goto out_dump; + + /* + * Search the inode node this entry refers to and the parent + * inode node and insert them to the RB-tree of inodes. + */ + inum = le64_to_cpu(dent->inum); + fscki = read_add_inode(c, priv, inum); + if (IS_ERR(fscki)) { + err = PTR_ERR(fscki); + ubifs_err("error %d while processing entry node and trying to find inode node %lu", + err, (unsigned long)inum); + goto out_dump; + } + + /* Count how many direntries or xentries refers this inode */ + fscki->references += 1; + + inum = key_inum_flash(c, &dent->key); + fscki1 = read_add_inode(c, priv, inum); + if (IS_ERR(fscki1)) { + err = PTR_ERR(fscki1); + ubifs_err("error %d while processing entry node and trying to find parent inode node %lu", + err, (unsigned long)inum); + goto out_dump; + } + + nlen = le16_to_cpu(dent->nlen); + if (type == UBIFS_XENT_KEY) { + fscki1->calc_xcnt += 1; + fscki1->calc_xsz += CALC_DENT_SIZE(nlen); + fscki1->calc_xsz += CALC_XATTR_BYTES(fscki->size); + fscki1->calc_xnms += nlen; + } else { + fscki1->calc_sz += CALC_DENT_SIZE(nlen); + if (dent->type == UBIFS_ITYPE_DIR) + fscki1->calc_cnt += 1; + } + } + +out: + kfree(node); + return 0; + +out_dump: + ubifs_msg("dump of node at LEB %d:%d", zbr->lnum, zbr->offs); + ubifs_dump_node(c, node); +out_free: + kfree(node); + return err; +} + +/** + * free_inodes - free RB-tree of inodes. + * @fsckd: FS checking information + */ +static void free_inodes(struct fsck_data *fsckd) +{ + struct fsck_inode *fscki, *n; + + rbtree_postorder_for_each_entry_safe(fscki, n, &fsckd->inodes, rb) + kfree(fscki); +} + +/** + * check_inodes - checks all inodes. + * @c: UBIFS file-system description object + * @fsckd: FS checking information + * + * This is a helper function for 'dbg_check_filesystem()' which walks the + * RB-tree of inodes after the index scan has been finished, and checks that + * inode nlink, size, etc are correct. Returns zero if inodes are fine, + * %-EINVAL if not, and a negative error code in case of failure. + */ +static int check_inodes(struct ubifs_info *c, struct fsck_data *fsckd) +{ + int n, err; + union ubifs_key key; + struct ubifs_znode *znode; + struct ubifs_zbranch *zbr; + struct ubifs_ino_node *ino; + struct fsck_inode *fscki; + struct rb_node *this = rb_first(&fsckd->inodes); + + while (this) { + fscki = rb_entry(this, struct fsck_inode, rb); + this = rb_next(this); + + if (S_ISDIR(fscki->mode)) { + /* + * Directories have to have exactly one reference (they + * cannot have hardlinks), although root inode is an + * exception. + */ + if (fscki->inum != UBIFS_ROOT_INO && + fscki->references != 1) { + ubifs_err("directory inode %lu has %d direntries which refer it, but should be 1", + (unsigned long)fscki->inum, + fscki->references); + goto out_dump; + } + if (fscki->inum == UBIFS_ROOT_INO && + fscki->references != 0) { + ubifs_err("root inode %lu has non-zero (%d) direntries which refer it", + (unsigned long)fscki->inum, + fscki->references); + goto out_dump; + } + if (fscki->calc_sz != fscki->size) { + ubifs_err("directory inode %lu size is %lld, but calculated size is %lld", + (unsigned long)fscki->inum, + fscki->size, fscki->calc_sz); + goto out_dump; + } + if (fscki->calc_cnt != fscki->nlink) { + ubifs_err("directory inode %lu nlink is %d, but calculated nlink is %d", + (unsigned long)fscki->inum, + fscki->nlink, fscki->calc_cnt); + goto out_dump; + } + } else { + if (fscki->references != fscki->nlink) { + ubifs_err("inode %lu nlink is %d, but calculated nlink is %d", + (unsigned long)fscki->inum, + fscki->nlink, fscki->references); + goto out_dump; + } + } + if (fscki->xattr_sz != fscki->calc_xsz) { + ubifs_err("inode %lu has xattr size %u, but calculated size is %lld", + (unsigned long)fscki->inum, fscki->xattr_sz, + fscki->calc_xsz); + goto out_dump; + } + if (fscki->xattr_cnt != fscki->calc_xcnt) { + ubifs_err("inode %lu has %u xattrs, but calculated count is %lld", + (unsigned long)fscki->inum, + fscki->xattr_cnt, fscki->calc_xcnt); + goto out_dump; + } + if (fscki->xattr_nms != fscki->calc_xnms) { + ubifs_err("inode %lu has xattr names' size %u, but calculated names' size is %lld", + (unsigned long)fscki->inum, fscki->xattr_nms, + fscki->calc_xnms); + goto out_dump; + } + } + + return 0; + +out_dump: + /* Read the bad inode and dump it */ + ino_key_init(c, &key, fscki->inum); + err = ubifs_lookup_level0(c, &key, &znode, &n); + if (!err) { + ubifs_err("inode %lu not found in index", + (unsigned long)fscki->inum); + return -ENOENT; + } else if (err < 0) { + ubifs_err("error %d while looking up inode %lu", + err, (unsigned long)fscki->inum); + return err; + } + + zbr = &znode->zbranch[n]; + ino = kmalloc(zbr->len, GFP_NOFS); + if (!ino) + return -ENOMEM; + + err = ubifs_tnc_read_node(c, zbr, ino); + if (err) { + ubifs_err("cannot read inode node at LEB %d:%d, error %d", + zbr->lnum, zbr->offs, err); + kfree(ino); + return err; + } + + ubifs_msg("dump of the inode %lu sitting in LEB %d:%d", + (unsigned long)fscki->inum, zbr->lnum, zbr->offs); + ubifs_dump_node(c, ino); + kfree(ino); + return -EINVAL; +} + +/** + * dbg_check_filesystem - check the file-system. + * @c: UBIFS file-system description object + * + * This function checks the file system, namely: + * o makes sure that all leaf nodes exist and their CRCs are correct; + * o makes sure inode nlink, size, xattr size/count are correct (for all + * inodes). + * + * The function reads whole indexing tree and all nodes, so it is pretty + * heavy-weight. Returns zero if the file-system is consistent, %-EINVAL if + * not, and a negative error code in case of failure. + */ +int dbg_check_filesystem(struct ubifs_info *c) +{ + int err; + struct fsck_data fsckd; + + if (!dbg_is_chk_fs(c)) + return 0; + + fsckd.inodes = RB_ROOT; + err = dbg_walk_index(c, check_leaf, NULL, &fsckd); + if (err) + goto out_free; + + err = check_inodes(c, &fsckd); + if (err) + goto out_free; + + free_inodes(&fsckd); + return 0; + +out_free: + ubifs_err("file-system check failed with error %d", err); + dump_stack(); + free_inodes(&fsckd); + return err; +} + +/** + * dbg_check_data_nodes_order - check that list of data nodes is sorted. + * @c: UBIFS file-system description object + * @head: the list of nodes ('struct ubifs_scan_node' objects) + * + * This function returns zero if the list of data nodes is sorted correctly, + * and %-EINVAL if not. + */ +int dbg_check_data_nodes_order(struct ubifs_info *c, struct list_head *head) +{ + struct list_head *cur; + struct ubifs_scan_node *sa, *sb; + + if (!dbg_is_chk_gen(c)) + return 0; + + for (cur = head->next; cur->next != head; cur = cur->next) { + ino_t inuma, inumb; + uint32_t blka, blkb; + + cond_resched(); + sa = container_of(cur, struct ubifs_scan_node, list); + sb = container_of(cur->next, struct ubifs_scan_node, list); + + if (sa->type != UBIFS_DATA_NODE) { + ubifs_err("bad node type %d", sa->type); + ubifs_dump_node(c, sa->node); + return -EINVAL; + } + if (sb->type != UBIFS_DATA_NODE) { + ubifs_err("bad node type %d", sb->type); + ubifs_dump_node(c, sb->node); + return -EINVAL; + } + + inuma = key_inum(c, &sa->key); + inumb = key_inum(c, &sb->key); + + if (inuma < inumb) + continue; + if (inuma > inumb) { + ubifs_err("larger inum %lu goes before inum %lu", + (unsigned long)inuma, (unsigned long)inumb); + goto error_dump; + } + + blka = key_block(c, &sa->key); + blkb = key_block(c, &sb->key); + + if (blka > blkb) { + ubifs_err("larger block %u goes before %u", blka, blkb); + goto error_dump; + } + if (blka == blkb) { + ubifs_err("two data nodes for the same block"); + goto error_dump; + } + } + + return 0; + +error_dump: + ubifs_dump_node(c, sa->node); + ubifs_dump_node(c, sb->node); + return -EINVAL; +} + +/** + * dbg_check_nondata_nodes_order - check that list of data nodes is sorted. + * @c: UBIFS file-system description object + * @head: the list of nodes ('struct ubifs_scan_node' objects) + * + * This function returns zero if the list of non-data nodes is sorted correctly, + * and %-EINVAL if not. + */ +int dbg_check_nondata_nodes_order(struct ubifs_info *c, struct list_head *head) +{ + struct list_head *cur; + struct ubifs_scan_node *sa, *sb; + + if (!dbg_is_chk_gen(c)) + return 0; + + for (cur = head->next; cur->next != head; cur = cur->next) { + ino_t inuma, inumb; + uint32_t hasha, hashb; + + cond_resched(); + sa = container_of(cur, struct ubifs_scan_node, list); + sb = container_of(cur->next, struct ubifs_scan_node, list); + + if (sa->type != UBIFS_INO_NODE && sa->type != UBIFS_DENT_NODE && + sa->type != UBIFS_XENT_NODE) { + ubifs_err("bad node type %d", sa->type); + ubifs_dump_node(c, sa->node); + return -EINVAL; + } + if (sa->type != UBIFS_INO_NODE && sa->type != UBIFS_DENT_NODE && + sa->type != UBIFS_XENT_NODE) { + ubifs_err("bad node type %d", sb->type); + ubifs_dump_node(c, sb->node); + return -EINVAL; + } + + if (sa->type != UBIFS_INO_NODE && sb->type == UBIFS_INO_NODE) { + ubifs_err("non-inode node goes before inode node"); + goto error_dump; + } + + if (sa->type == UBIFS_INO_NODE && sb->type != UBIFS_INO_NODE) + continue; + + if (sa->type == UBIFS_INO_NODE && sb->type == UBIFS_INO_NODE) { + /* Inode nodes are sorted in descending size order */ + if (sa->len < sb->len) { + ubifs_err("smaller inode node goes first"); + goto error_dump; + } + continue; + } + + /* + * This is either a dentry or xentry, which should be sorted in + * ascending (parent ino, hash) order. + */ + inuma = key_inum(c, &sa->key); + inumb = key_inum(c, &sb->key); + + if (inuma < inumb) + continue; + if (inuma > inumb) { + ubifs_err("larger inum %lu goes before inum %lu", + (unsigned long)inuma, (unsigned long)inumb); + goto error_dump; + } + + hasha = key_block(c, &sa->key); + hashb = key_block(c, &sb->key); + + if (hasha > hashb) { + ubifs_err("larger hash %u goes before %u", + hasha, hashb); + goto error_dump; + } + } + + return 0; + +error_dump: + ubifs_msg("dumping first node"); + ubifs_dump_node(c, sa->node); + ubifs_msg("dumping second node"); + ubifs_dump_node(c, sb->node); + return -EINVAL; + return 0; +} + +static inline int chance(unsigned int n, unsigned int out_of) +{ + return !!((prandom_u32() % out_of) + 1 <= n); + +} + +static int power_cut_emulated(struct ubifs_info *c, int lnum, int write) +{ + struct ubifs_debug_info *d = c->dbg; + + ubifs_assert(dbg_is_tst_rcvry(c)); + + if (!d->pc_cnt) { + /* First call - decide delay to the power cut */ + if (chance(1, 2)) { + unsigned long delay; + + if (chance(1, 2)) { + d->pc_delay = 1; + /* Fail withing 1 minute */ + delay = prandom_u32() % 60000; + d->pc_timeout = jiffies; + d->pc_timeout += msecs_to_jiffies(delay); + ubifs_warn("failing after %lums", delay); + } else { + d->pc_delay = 2; + delay = prandom_u32() % 10000; + /* Fail within 10000 operations */ + d->pc_cnt_max = delay; + ubifs_warn("failing after %lu calls", delay); + } + } + + d->pc_cnt += 1; + } + + /* Determine if failure delay has expired */ + if (d->pc_delay == 1 && time_before(jiffies, d->pc_timeout)) + return 0; + if (d->pc_delay == 2 && d->pc_cnt++ < d->pc_cnt_max) + return 0; + + if (lnum == UBIFS_SB_LNUM) { + if (write && chance(1, 2)) + return 0; + if (chance(19, 20)) + return 0; + ubifs_warn("failing in super block LEB %d", lnum); + } else if (lnum == UBIFS_MST_LNUM || lnum == UBIFS_MST_LNUM + 1) { + if (chance(19, 20)) + return 0; + ubifs_warn("failing in master LEB %d", lnum); + } else if (lnum >= UBIFS_LOG_LNUM && lnum <= c->log_last) { + if (write && chance(99, 100)) + return 0; + if (chance(399, 400)) + return 0; + ubifs_warn("failing in log LEB %d", lnum); + } else if (lnum >= c->lpt_first && lnum <= c->lpt_last) { + if (write && chance(7, 8)) + return 0; + if (chance(19, 20)) + return 0; + ubifs_warn("failing in LPT LEB %d", lnum); + } else if (lnum >= c->orph_first && lnum <= c->orph_last) { + if (write && chance(1, 2)) + return 0; + if (chance(9, 10)) + return 0; + ubifs_warn("failing in orphan LEB %d", lnum); + } else if (lnum == c->ihead_lnum) { + if (chance(99, 100)) + return 0; + ubifs_warn("failing in index head LEB %d", lnum); + } else if (c->jheads && lnum == c->jheads[GCHD].wbuf.lnum) { + if (chance(9, 10)) + return 0; + ubifs_warn("failing in GC head LEB %d", lnum); + } else if (write && !RB_EMPTY_ROOT(&c->buds) && + !ubifs_search_bud(c, lnum)) { + if (chance(19, 20)) + return 0; + ubifs_warn("failing in non-bud LEB %d", lnum); + } else if (c->cmt_state == COMMIT_RUNNING_BACKGROUND || + c->cmt_state == COMMIT_RUNNING_REQUIRED) { + if (chance(999, 1000)) + return 0; + ubifs_warn("failing in bud LEB %d commit running", lnum); + } else { + if (chance(9999, 10000)) + return 0; + ubifs_warn("failing in bud LEB %d commit not running", lnum); + } + + d->pc_happened = 1; + ubifs_warn("========== Power cut emulated =========="); + dump_stack(); + return 1; +} + +static int corrupt_data(const struct ubifs_info *c, const void *buf, + unsigned int len) +{ + unsigned int from, to, ffs = chance(1, 2); + unsigned char *p = (void *)buf; + + from = prandom_u32() % len; + /* Corruption span max to end of write unit */ + to = min(len, ALIGN(from + 1, c->max_write_size)); + + ubifs_warn("filled bytes %u-%u with %s", from, to - 1, + ffs ? "0xFFs" : "random data"); + + if (ffs) + memset(p + from, 0xFF, to - from); + else + prandom_bytes(p + from, to - from); + + return to; +} + +int dbg_leb_write(struct ubifs_info *c, int lnum, const void *buf, + int offs, int len) +{ + int err, failing; + + if (c->dbg->pc_happened) + return -EROFS; + + failing = power_cut_emulated(c, lnum, 1); + if (failing) { + len = corrupt_data(c, buf, len); + ubifs_warn("actually write %d bytes to LEB %d:%d (the buffer was corrupted)", + len, lnum, offs); + } + err = ubi_leb_write(c->ubi, lnum, buf, offs, len); + if (err) + return err; + if (failing) + return -EROFS; + return 0; +} + +int dbg_leb_change(struct ubifs_info *c, int lnum, const void *buf, + int len) +{ + int err; + + if (c->dbg->pc_happened) + return -EROFS; + if (power_cut_emulated(c, lnum, 1)) + return -EROFS; + err = ubi_leb_change(c->ubi, lnum, buf, len); + if (err) + return err; + if (power_cut_emulated(c, lnum, 1)) + return -EROFS; + return 0; +} + +int dbg_leb_unmap(struct ubifs_info *c, int lnum) +{ + int err; + + if (c->dbg->pc_happened) + return -EROFS; + if (power_cut_emulated(c, lnum, 0)) + return -EROFS; + err = ubi_leb_unmap(c->ubi, lnum); + if (err) + return err; + if (power_cut_emulated(c, lnum, 0)) + return -EROFS; + return 0; +} + +int dbg_leb_map(struct ubifs_info *c, int lnum) +{ + int err; + + if (c->dbg->pc_happened) + return -EROFS; + if (power_cut_emulated(c, lnum, 0)) + return -EROFS; + err = ubi_leb_map(c->ubi, lnum); + if (err) + return err; + if (power_cut_emulated(c, lnum, 0)) + return -EROFS; + return 0; +} + +/* + * Root directory for UBIFS stuff in debugfs. Contains sub-directories which + * contain the stuff specific to particular file-system mounts. + */ +static struct dentry *dfs_rootdir; + +static int dfs_file_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return nonseekable_open(inode, file); +} + +/** + * provide_user_output - provide output to the user reading a debugfs file. + * @val: boolean value for the answer + * @u: the buffer to store the answer at + * @count: size of the buffer + * @ppos: position in the @u output buffer + * + * This is a simple helper function which stores @val boolean value in the user + * buffer when the user reads one of UBIFS debugfs files. Returns amount of + * bytes written to @u in case of success and a negative error code in case of + * failure. + */ +static int provide_user_output(int val, char __user *u, size_t count, + loff_t *ppos) +{ + char buf[3]; + + if (val) + buf[0] = '1'; + else + buf[0] = '0'; + buf[1] = '\n'; + buf[2] = 0x00; + + return simple_read_from_buffer(u, count, ppos, buf, 2); +} + +static ssize_t dfs_file_read(struct file *file, char __user *u, size_t count, + loff_t *ppos) +{ + struct dentry *dent = file->f_path.dentry; + struct ubifs_info *c = file->private_data; + struct ubifs_debug_info *d = c->dbg; + int val; + + if (dent == d->dfs_chk_gen) + val = d->chk_gen; + else if (dent == d->dfs_chk_index) + val = d->chk_index; + else if (dent == d->dfs_chk_orph) + val = d->chk_orph; + else if (dent == d->dfs_chk_lprops) + val = d->chk_lprops; + else if (dent == d->dfs_chk_fs) + val = d->chk_fs; + else if (dent == d->dfs_tst_rcvry) + val = d->tst_rcvry; + else if (dent == d->dfs_ro_error) + val = c->ro_error; + else + return -EINVAL; + + return provide_user_output(val, u, count, ppos); +} + +/** + * interpret_user_input - interpret user debugfs file input. + * @u: user-provided buffer with the input + * @count: buffer size + * + * This is a helper function which interpret user input to a boolean UBIFS + * debugfs file. Returns %0 or %1 in case of success and a negative error code + * in case of failure. + */ +static int interpret_user_input(const char __user *u, size_t count) +{ + size_t buf_size; + char buf[8]; + + buf_size = min_t(size_t, count, (sizeof(buf) - 1)); + if (copy_from_user(buf, u, buf_size)) + return -EFAULT; + + if (buf[0] == '1') + return 1; + else if (buf[0] == '0') + return 0; + + return -EINVAL; +} + +static ssize_t dfs_file_write(struct file *file, const char __user *u, + size_t count, loff_t *ppos) +{ + struct ubifs_info *c = file->private_data; + struct ubifs_debug_info *d = c->dbg; + struct dentry *dent = file->f_path.dentry; + int val; + + /* + * TODO: this is racy - the file-system might have already been + * unmounted and we'd oops in this case. The plan is to fix it with + * help of 'iterate_supers_type()' which we should have in v3.0: when + * a debugfs opened, we rember FS's UUID in file->private_data. Then + * whenever we access the FS via a debugfs file, we iterate all UBIFS + * superblocks and fine the one with the same UUID, and take the + * locking right. + * + * The other way to go suggested by Al Viro is to create a separate + * 'ubifs-debug' file-system instead. + */ + if (file->f_path.dentry == d->dfs_dump_lprops) { + ubifs_dump_lprops(c); + return count; + } + if (file->f_path.dentry == d->dfs_dump_budg) { + ubifs_dump_budg(c, &c->bi); + return count; + } + if (file->f_path.dentry == d->dfs_dump_tnc) { + mutex_lock(&c->tnc_mutex); + ubifs_dump_tnc(c); + mutex_unlock(&c->tnc_mutex); + return count; + } + + val = interpret_user_input(u, count); + if (val < 0) + return val; + + if (dent == d->dfs_chk_gen) + d->chk_gen = val; + else if (dent == d->dfs_chk_index) + d->chk_index = val; + else if (dent == d->dfs_chk_orph) + d->chk_orph = val; + else if (dent == d->dfs_chk_lprops) + d->chk_lprops = val; + else if (dent == d->dfs_chk_fs) + d->chk_fs = val; + else if (dent == d->dfs_tst_rcvry) + d->tst_rcvry = val; + else if (dent == d->dfs_ro_error) + c->ro_error = !!val; + else + return -EINVAL; + + return count; +} + +static const struct file_operations dfs_fops = { + .open = dfs_file_open, + .read = dfs_file_read, + .write = dfs_file_write, + .owner = THIS_MODULE, + .llseek = no_llseek, +}; + +/** + * dbg_debugfs_init_fs - initialize debugfs for UBIFS instance. + * @c: UBIFS file-system description object + * + * This function creates all debugfs files for this instance of UBIFS. Returns + * zero in case of success and a negative error code in case of failure. + * + * Note, the only reason we have not merged this function with the + * 'ubifs_debugging_init()' function is because it is better to initialize + * debugfs interfaces at the very end of the mount process, and remove them at + * the very beginning of the mount process. + */ +int dbg_debugfs_init_fs(struct ubifs_info *c) +{ + int err, n; + const char *fname; + struct dentry *dent; + struct ubifs_debug_info *d = c->dbg; + + if (!IS_ENABLED(CONFIG_DEBUG_FS)) + return 0; + + n = snprintf(d->dfs_dir_name, UBIFS_DFS_DIR_LEN + 1, UBIFS_DFS_DIR_NAME, + c->vi.ubi_num, c->vi.vol_id); + if (n == UBIFS_DFS_DIR_LEN) { + /* The array size is too small */ + fname = UBIFS_DFS_DIR_NAME; + dent = ERR_PTR(-EINVAL); + goto out; + } + + fname = d->dfs_dir_name; + dent = debugfs_create_dir(fname, dfs_rootdir); + if (IS_ERR_OR_NULL(dent)) + goto out; + d->dfs_dir = dent; + + fname = "dump_lprops"; + dent = debugfs_create_file(fname, S_IWUSR, d->dfs_dir, c, &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_dump_lprops = dent; + + fname = "dump_budg"; + dent = debugfs_create_file(fname, S_IWUSR, d->dfs_dir, c, &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_dump_budg = dent; + + fname = "dump_tnc"; + dent = debugfs_create_file(fname, S_IWUSR, d->dfs_dir, c, &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_dump_tnc = dent; + + fname = "chk_general"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, d->dfs_dir, c, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_chk_gen = dent; + + fname = "chk_index"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, d->dfs_dir, c, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_chk_index = dent; + + fname = "chk_orphans"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, d->dfs_dir, c, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_chk_orph = dent; + + fname = "chk_lprops"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, d->dfs_dir, c, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_chk_lprops = dent; + + fname = "chk_fs"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, d->dfs_dir, c, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_chk_fs = dent; + + fname = "tst_recovery"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, d->dfs_dir, c, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_tst_rcvry = dent; + + fname = "ro_error"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, d->dfs_dir, c, + &dfs_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + d->dfs_ro_error = dent; + + return 0; + +out_remove: + debugfs_remove_recursive(d->dfs_dir); +out: + err = dent ? PTR_ERR(dent) : -ENODEV; + ubifs_err("cannot create \"%s\" debugfs file or directory, error %d\n", + fname, err); + return err; +} + +/** + * dbg_debugfs_exit_fs - remove all debugfs files. + * @c: UBIFS file-system description object + */ +void dbg_debugfs_exit_fs(struct ubifs_info *c) +{ + if (IS_ENABLED(CONFIG_DEBUG_FS)) + debugfs_remove_recursive(c->dbg->dfs_dir); +} + +struct ubifs_global_debug_info ubifs_dbg; + +static struct dentry *dfs_chk_gen; +static struct dentry *dfs_chk_index; +static struct dentry *dfs_chk_orph; +static struct dentry *dfs_chk_lprops; +static struct dentry *dfs_chk_fs; +static struct dentry *dfs_tst_rcvry; + +static ssize_t dfs_global_file_read(struct file *file, char __user *u, + size_t count, loff_t *ppos) +{ + struct dentry *dent = file->f_path.dentry; + int val; + + if (dent == dfs_chk_gen) + val = ubifs_dbg.chk_gen; + else if (dent == dfs_chk_index) + val = ubifs_dbg.chk_index; + else if (dent == dfs_chk_orph) + val = ubifs_dbg.chk_orph; + else if (dent == dfs_chk_lprops) + val = ubifs_dbg.chk_lprops; + else if (dent == dfs_chk_fs) + val = ubifs_dbg.chk_fs; + else if (dent == dfs_tst_rcvry) + val = ubifs_dbg.tst_rcvry; + else + return -EINVAL; + + return provide_user_output(val, u, count, ppos); +} + +static ssize_t dfs_global_file_write(struct file *file, const char __user *u, + size_t count, loff_t *ppos) +{ + struct dentry *dent = file->f_path.dentry; + int val; + + val = interpret_user_input(u, count); + if (val < 0) + return val; + + if (dent == dfs_chk_gen) + ubifs_dbg.chk_gen = val; + else if (dent == dfs_chk_index) + ubifs_dbg.chk_index = val; + else if (dent == dfs_chk_orph) + ubifs_dbg.chk_orph = val; + else if (dent == dfs_chk_lprops) + ubifs_dbg.chk_lprops = val; + else if (dent == dfs_chk_fs) + ubifs_dbg.chk_fs = val; + else if (dent == dfs_tst_rcvry) + ubifs_dbg.tst_rcvry = val; + else + return -EINVAL; + + return count; +} + +static const struct file_operations dfs_global_fops = { + .read = dfs_global_file_read, + .write = dfs_global_file_write, + .owner = THIS_MODULE, + .llseek = no_llseek, +}; + +/** + * dbg_debugfs_init - initialize debugfs file-system. + * + * UBIFS uses debugfs file-system to expose various debugging knobs to + * user-space. This function creates "ubifs" directory in the debugfs + * file-system. Returns zero in case of success and a negative error code in + * case of failure. + */ +int dbg_debugfs_init(void) +{ + int err; + const char *fname; + struct dentry *dent; + + if (!IS_ENABLED(CONFIG_DEBUG_FS)) + return 0; + + fname = "ubifs"; + dent = debugfs_create_dir(fname, NULL); + if (IS_ERR_OR_NULL(dent)) + goto out; + dfs_rootdir = dent; + + fname = "chk_general"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, dfs_rootdir, NULL, + &dfs_global_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + dfs_chk_gen = dent; + + fname = "chk_index"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, dfs_rootdir, NULL, + &dfs_global_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + dfs_chk_index = dent; + + fname = "chk_orphans"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, dfs_rootdir, NULL, + &dfs_global_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + dfs_chk_orph = dent; + + fname = "chk_lprops"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, dfs_rootdir, NULL, + &dfs_global_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + dfs_chk_lprops = dent; + + fname = "chk_fs"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, dfs_rootdir, NULL, + &dfs_global_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + dfs_chk_fs = dent; + + fname = "tst_recovery"; + dent = debugfs_create_file(fname, S_IRUSR | S_IWUSR, dfs_rootdir, NULL, + &dfs_global_fops); + if (IS_ERR_OR_NULL(dent)) + goto out_remove; + dfs_tst_rcvry = dent; + + return 0; + +out_remove: + debugfs_remove_recursive(dfs_rootdir); +out: + err = dent ? PTR_ERR(dent) : -ENODEV; + ubifs_err("cannot create \"%s\" debugfs file or directory, error %d\n", + fname, err); + return err; +} + +/** + * dbg_debugfs_exit - remove the "ubifs" directory from debugfs file-system. + */ +void dbg_debugfs_exit(void) +{ + if (IS_ENABLED(CONFIG_DEBUG_FS)) + debugfs_remove_recursive(dfs_rootdir); +} + +/** + * ubifs_debugging_init - initialize UBIFS debugging. + * @c: UBIFS file-system description object + * + * This function initializes debugging-related data for the file system. + * Returns zero in case of success and a negative error code in case of + * failure. + */ +int ubifs_debugging_init(struct ubifs_info *c) +{ + c->dbg = kzalloc(sizeof(struct ubifs_debug_info), GFP_KERNEL); + if (!c->dbg) + return -ENOMEM; + + return 0; +} + +/** + * ubifs_debugging_exit - free debugging data. + * @c: UBIFS file-system description object + */ +void ubifs_debugging_exit(struct ubifs_info *c) +{ + kfree(c->dbg); +} +#endif diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h index 62617b6927..807ce1b733 100644 --- a/fs/ubifs/debug.h +++ b/fs/ubifs/debug.h @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -23,19 +12,31 @@ #ifndef __UBIFS_DEBUG_H__ #define __UBIFS_DEBUG_H__ -#ifdef CONFIG_UBIFS_FS_DEBUG +/* Checking helper functions */ +typedef int (*dbg_leaf_callback)(struct ubifs_info *c, + struct ubifs_zbranch *zbr, void *priv); +typedef int (*dbg_znode_callback)(struct ubifs_info *c, + struct ubifs_znode *znode, void *priv); + +/* + * The UBIFS debugfs directory name pattern and maximum name length (3 for "ubi" + * + 1 for "_" and plus 2x2 for 2 UBI numbers and 1 for the trailing zero byte. + */ +#define UBIFS_DFS_DIR_NAME "ubi%d_%d" +#define UBIFS_DFS_DIR_LEN (3 + 1 + 2*2 + 1) /** * ubifs_debug_info - per-FS debugging information. - * @buf: a buffer of LEB size, used for various purposes * @old_zroot: old index root - used by 'dbg_check_old_index()' * @old_zroot_level: old index root level - used by 'dbg_check_old_index()' * @old_zroot_sqnum: old index root sqnum - used by 'dbg_check_old_index()' - * @failure_mode: failure mode for recovery testing - * @fail_delay: 0=>don't delay, 1=>delay a time, 2=>delay a number of calls - * @fail_timeout: time in jiffies when delay of failure mode expires - * @fail_cnt: current number of calls to failure mode I/O functions - * @fail_cnt_max: number of calls by which to delay failure mode + * + * @pc_happened: non-zero if an emulated power cut happened + * @pc_delay: 0=>don't delay, 1=>delay a time, 2=>delay a number of calls + * @pc_timeout: time in jiffies when delay of failure mode expires + * @pc_cnt: current number of calls to failure mode I/O functions + * @pc_cnt_max: number of calls by which to delay failure mode + * * @chk_lpt_sz: used by LPT tree size checker * @chk_lpt_sz2: used by LPT tree size checker * @chk_lpt_wastage: used by LPT tree size checker @@ -45,24 +46,44 @@ * @new_ihead_offs: used by debugging to check @c->ihead_offs * * @saved_lst: saved lprops statistics (used by 'dbg_save_space_info()') - * @saved_free: saved free space (used by 'dbg_save_space_info()') + * @saved_bi: saved budgeting information + * @saved_free: saved amount of free space + * @saved_idx_gc_cnt: saved value of @c->idx_gc_cnt + * + * @chk_gen: if general extra checks are enabled + * @chk_index: if index xtra checks are enabled + * @chk_orph: if orphans extra checks are enabled + * @chk_lprops: if lprops extra checks are enabled + * @chk_fs: if UBIFS contents extra checks are enabled + * @tst_rcvry: if UBIFS recovery testing mode enabled * - * dfs_dir_name: name of debugfs directory containing this file-system's files - * dfs_dir: direntry object of the file-system debugfs directory - * dfs_dump_lprops: "dump lprops" debugfs knob - * dfs_dump_budg: "dump budgeting information" debugfs knob - * dfs_dump_tnc: "dump TNC" debugfs knob + * @dfs_dir_name: name of debugfs directory containing this file-system's files + * @dfs_dir: direntry object of the file-system debugfs directory + * @dfs_dump_lprops: "dump lprops" debugfs knob + * @dfs_dump_budg: "dump budgeting information" debugfs knob + * @dfs_dump_tnc: "dump TNC" debugfs knob + * @dfs_chk_gen: debugfs knob to enable UBIFS general extra checks + * @dfs_chk_index: debugfs knob to enable UBIFS index extra checks + * @dfs_chk_orph: debugfs knob to enable UBIFS orphans extra checks + * @dfs_chk_lprops: debugfs knob to enable UBIFS LEP properties extra checks + * @dfs_chk_fs: debugfs knob to enable UBIFS contents extra checks + * @dfs_tst_rcvry: debugfs knob to enable UBIFS recovery testing + * @dfs_ro_error: debugfs knob to switch UBIFS to R/O mode (different to + * re-mounting to R/O mode because it does not flush any buffers + * and UBIFS just starts returning -EROFS on all write + * operations) */ struct ubifs_debug_info { - void *buf; struct ubifs_zbranch old_zroot; int old_zroot_level; unsigned long long old_zroot_sqnum; - int failure_mode; - int fail_delay; - unsigned long fail_timeout; - unsigned int fail_cnt; - unsigned int fail_cnt_max; + + int pc_happened; + int pc_delay; + unsigned long pc_timeout; + unsigned int pc_cnt; + unsigned int pc_cnt_max; + long long chk_lpt_sz; long long chk_lpt_sz2; long long chk_lpt_wastage; @@ -72,321 +93,285 @@ struct ubifs_debug_info { int new_ihead_offs; struct ubifs_lp_stats saved_lst; + struct ubifs_budg_info saved_bi; long long saved_free; + int saved_idx_gc_cnt; + + unsigned int chk_gen:1; + unsigned int chk_index:1; + unsigned int chk_orph:1; + unsigned int chk_lprops:1; + unsigned int chk_fs:1; + unsigned int tst_rcvry:1; - char dfs_dir_name[100]; + char dfs_dir_name[UBIFS_DFS_DIR_LEN + 1]; struct dentry *dfs_dir; struct dentry *dfs_dump_lprops; struct dentry *dfs_dump_budg; struct dentry *dfs_dump_tnc; + struct dentry *dfs_chk_gen; + struct dentry *dfs_chk_index; + struct dentry *dfs_chk_orph; + struct dentry *dfs_chk_lprops; + struct dentry *dfs_chk_fs; + struct dentry *dfs_tst_rcvry; + struct dentry *dfs_ro_error; }; -#define UBIFS_DBG(op) op +/** + * ubifs_global_debug_info - global (not per-FS) UBIFS debugging information. + * + * @chk_gen: if general extra checks are enabled + * @chk_index: if index xtra checks are enabled + * @chk_orph: if orphans extra checks are enabled + * @chk_lprops: if lprops extra checks are enabled + * @chk_fs: if UBIFS contents extra checks are enabled + * @tst_rcvry: if UBIFS recovery testing mode enabled + */ +struct ubifs_global_debug_info { + unsigned int chk_gen:1; + unsigned int chk_index:1; + unsigned int chk_orph:1; + unsigned int chk_lprops:1; + unsigned int chk_fs:1; + unsigned int tst_rcvry:1; +}; +#ifndef __UBOOT__ #define ubifs_assert(expr) do { \ if (unlikely(!(expr))) { \ - printk(KERN_CRIT "UBIFS assert failed in %s at %u (pid %d)\n", \ - __func__, __LINE__, 0); \ - dbg_dump_stack(); \ + pr_crit("UBIFS assert failed in %s at %u (pid %d)\n", \ + __func__, __LINE__, current->pid); \ + dump_stack(); \ } \ } while (0) #define ubifs_assert_cmt_locked(c) do { \ if (unlikely(down_write_trylock(&(c)->commit_sem))) { \ up_write(&(c)->commit_sem); \ - printk(KERN_CRIT "commit lock is not locked!\n"); \ + pr_crit("commit lock is not locked!\n"); \ ubifs_assert(0); \ } \ } while (0) -#define dbg_dump_stack() do { \ - if (!dbg_failure_mode) \ +#define ubifs_dbg_msg(type, fmt, ...) \ + pr_debug("UBIFS DBG " type " (pid %d): " fmt "\n", current->pid, \ + ##__VA_ARGS__) + +#define DBG_KEY_BUF_LEN 48 +#define ubifs_dbg_msg_key(type, key, fmt, ...) do { \ + char __tmp_key_buf[DBG_KEY_BUF_LEN]; \ + pr_debug("UBIFS DBG " type " (pid %d): " fmt "%s\n", current->pid, \ + ##__VA_ARGS__, \ + dbg_snprintf_key(c, key, __tmp_key_buf, DBG_KEY_BUF_LEN)); \ +} while (0) +#else +#define ubifs_assert(expr) do { \ + if (unlikely(!(expr))) { \ + pr_crit("UBIFS assert failed in %s at %u\n", \ + __func__, __LINE__); \ dump_stack(); \ + } \ } while (0) -/* Generic debugging messages */ -#define dbg_msg(fmt, ...) do { \ - spin_lock(&dbg_lock); \ - printk(KERN_DEBUG "UBIFS DBG (pid %d): %s: " fmt "\n", 0, \ - __func__, ##__VA_ARGS__); \ - spin_unlock(&dbg_lock); \ +#define ubifs_assert_cmt_locked(c) do { \ + if (unlikely(down_write_trylock(&(c)->commit_sem))) { \ + up_write(&(c)->commit_sem); \ + pr_crit("commit lock is not locked!\n"); \ + ubifs_assert(0); \ + } \ } while (0) -#define dbg_do_msg(typ, fmt, ...) do { \ - if (ubifs_msg_flags & typ) \ - dbg_msg(fmt, ##__VA_ARGS__); \ +#define ubifs_dbg_msg(type, fmt, ...) \ + pr_debug("UBIFS DBG " type ": " fmt "\n", \ + ##__VA_ARGS__) + +#define DBG_KEY_BUF_LEN 48 +#if defined CONFIG_MTD_DEBUG +#define ubifs_dbg_msg_key(type, key, fmt, ...) do { \ + char __tmp_key_buf[DBG_KEY_BUF_LEN]; \ + pr_debug("UBIFS DBG " type ": " fmt "%s\n", \ + ##__VA_ARGS__, \ + dbg_snprintf_key(c, key, __tmp_key_buf, DBG_KEY_BUF_LEN)); \ } while (0) - -#define dbg_err(fmt, ...) do { \ - spin_lock(&dbg_lock); \ - ubifs_err(fmt, ##__VA_ARGS__); \ - spin_unlock(&dbg_lock); \ +#else +#define ubifs_dbg_msg_key(type, key, fmt, ...) do { \ + pr_debug("UBIFS DBG\n"); \ } while (0) -const char *dbg_key_str0(const struct ubifs_info *c, - const union ubifs_key *key); -const char *dbg_key_str1(const struct ubifs_info *c, - const union ubifs_key *key); +#endif -/* - * DBGKEY macros require @dbg_lock to be held, which it is in the dbg message - * macros. - */ -#define DBGKEY(key) dbg_key_str0(c, (key)) -#define DBGKEY1(key) dbg_key_str1(c, (key)) +#endif /* General messages */ -#define dbg_gen(fmt, ...) dbg_do_msg(UBIFS_MSG_GEN, fmt, ##__VA_ARGS__) - +#define dbg_gen(fmt, ...) ubifs_dbg_msg("gen", fmt, ##__VA_ARGS__) /* Additional journal messages */ -#define dbg_jnl(fmt, ...) dbg_do_msg(UBIFS_MSG_JNL, fmt, ##__VA_ARGS__) - +#define dbg_jnl(fmt, ...) ubifs_dbg_msg("jnl", fmt, ##__VA_ARGS__) +#define dbg_jnlk(key, fmt, ...) \ + ubifs_dbg_msg_key("jnl", key, fmt, ##__VA_ARGS__) /* Additional TNC messages */ -#define dbg_tnc(fmt, ...) dbg_do_msg(UBIFS_MSG_TNC, fmt, ##__VA_ARGS__) - +#define dbg_tnc(fmt, ...) ubifs_dbg_msg("tnc", fmt, ##__VA_ARGS__) +#define dbg_tnck(key, fmt, ...) \ + ubifs_dbg_msg_key("tnc", key, fmt, ##__VA_ARGS__) /* Additional lprops messages */ -#define dbg_lp(fmt, ...) dbg_do_msg(UBIFS_MSG_LP, fmt, ##__VA_ARGS__) - +#define dbg_lp(fmt, ...) ubifs_dbg_msg("lp", fmt, ##__VA_ARGS__) /* Additional LEB find messages */ -#define dbg_find(fmt, ...) dbg_do_msg(UBIFS_MSG_FIND, fmt, ##__VA_ARGS__) - +#define dbg_find(fmt, ...) ubifs_dbg_msg("find", fmt, ##__VA_ARGS__) /* Additional mount messages */ -#define dbg_mnt(fmt, ...) dbg_do_msg(UBIFS_MSG_MNT, fmt, ##__VA_ARGS__) - +#define dbg_mnt(fmt, ...) ubifs_dbg_msg("mnt", fmt, ##__VA_ARGS__) +#define dbg_mntk(key, fmt, ...) \ + ubifs_dbg_msg_key("mnt", key, fmt, ##__VA_ARGS__) /* Additional I/O messages */ -#define dbg_io(fmt, ...) dbg_do_msg(UBIFS_MSG_IO, fmt, ##__VA_ARGS__) - +#define dbg_io(fmt, ...) ubifs_dbg_msg("io", fmt, ##__VA_ARGS__) /* Additional commit messages */ -#define dbg_cmt(fmt, ...) dbg_do_msg(UBIFS_MSG_CMT, fmt, ##__VA_ARGS__) - +#define dbg_cmt(fmt, ...) ubifs_dbg_msg("cmt", fmt, ##__VA_ARGS__) /* Additional budgeting messages */ -#define dbg_budg(fmt, ...) dbg_do_msg(UBIFS_MSG_BUDG, fmt, ##__VA_ARGS__) - +#define dbg_budg(fmt, ...) ubifs_dbg_msg("budg", fmt, ##__VA_ARGS__) /* Additional log messages */ -#define dbg_log(fmt, ...) dbg_do_msg(UBIFS_MSG_LOG, fmt, ##__VA_ARGS__) - +#define dbg_log(fmt, ...) ubifs_dbg_msg("log", fmt, ##__VA_ARGS__) /* Additional gc messages */ -#define dbg_gc(fmt, ...) dbg_do_msg(UBIFS_MSG_GC, fmt, ##__VA_ARGS__) - +#define dbg_gc(fmt, ...) ubifs_dbg_msg("gc", fmt, ##__VA_ARGS__) /* Additional scan messages */ -#define dbg_scan(fmt, ...) dbg_do_msg(UBIFS_MSG_SCAN, fmt, ##__VA_ARGS__) - +#define dbg_scan(fmt, ...) ubifs_dbg_msg("scan", fmt, ##__VA_ARGS__) /* Additional recovery messages */ -#define dbg_rcvry(fmt, ...) dbg_do_msg(UBIFS_MSG_RCVRY, fmt, ##__VA_ARGS__) +#define dbg_rcvry(fmt, ...) ubifs_dbg_msg("rcvry", fmt, ##__VA_ARGS__) + +#ifndef __UBOOT__ +extern struct ubifs_global_debug_info ubifs_dbg; + +static inline int dbg_is_chk_gen(const struct ubifs_info *c) +{ + return !!(ubifs_dbg.chk_gen || c->dbg->chk_gen); +} +static inline int dbg_is_chk_index(const struct ubifs_info *c) +{ + return !!(ubifs_dbg.chk_index || c->dbg->chk_index); +} +static inline int dbg_is_chk_orph(const struct ubifs_info *c) +{ + return !!(ubifs_dbg.chk_orph || c->dbg->chk_orph); +} +static inline int dbg_is_chk_lprops(const struct ubifs_info *c) +{ + return !!(ubifs_dbg.chk_lprops || c->dbg->chk_lprops); +} +static inline int dbg_is_chk_fs(const struct ubifs_info *c) +{ + return !!(ubifs_dbg.chk_fs || c->dbg->chk_fs); +} +static inline int dbg_is_tst_rcvry(const struct ubifs_info *c) +{ + return !!(ubifs_dbg.tst_rcvry || c->dbg->tst_rcvry); +} +static inline int dbg_is_power_cut(const struct ubifs_info *c) +{ + return !!c->dbg->pc_happened; +} -/* - * Debugging message type flags (must match msg_type_names in debug.c). - * - * UBIFS_MSG_GEN: general messages - * UBIFS_MSG_JNL: journal messages - * UBIFS_MSG_MNT: mount messages - * UBIFS_MSG_CMT: commit messages - * UBIFS_MSG_FIND: LEB find messages - * UBIFS_MSG_BUDG: budgeting messages - * UBIFS_MSG_GC: garbage collection messages - * UBIFS_MSG_TNC: TNC messages - * UBIFS_MSG_LP: lprops messages - * UBIFS_MSG_IO: I/O messages - * UBIFS_MSG_LOG: log messages - * UBIFS_MSG_SCAN: scan messages - * UBIFS_MSG_RCVRY: recovery messages - */ -enum { - UBIFS_MSG_GEN = 0x1, - UBIFS_MSG_JNL = 0x2, - UBIFS_MSG_MNT = 0x4, - UBIFS_MSG_CMT = 0x8, - UBIFS_MSG_FIND = 0x10, - UBIFS_MSG_BUDG = 0x20, - UBIFS_MSG_GC = 0x40, - UBIFS_MSG_TNC = 0x80, - UBIFS_MSG_LP = 0x100, - UBIFS_MSG_IO = 0x200, - UBIFS_MSG_LOG = 0x400, - UBIFS_MSG_SCAN = 0x800, - UBIFS_MSG_RCVRY = 0x1000, -}; - -/* Debugging message type flags for each default debug message level */ -#define UBIFS_MSG_LVL_0 0 -#define UBIFS_MSG_LVL_1 0x1 -#define UBIFS_MSG_LVL_2 0x7f -#define UBIFS_MSG_LVL_3 0xffff - -/* - * Debugging check flags (must match chk_names in debug.c). - * - * UBIFS_CHK_GEN: general checks - * UBIFS_CHK_TNC: check TNC - * UBIFS_CHK_IDX_SZ: check index size - * UBIFS_CHK_ORPH: check orphans - * UBIFS_CHK_OLD_IDX: check the old index - * UBIFS_CHK_LPROPS: check lprops - * UBIFS_CHK_FS: check the file-system - */ -enum { - UBIFS_CHK_GEN = 0x1, - UBIFS_CHK_TNC = 0x2, - UBIFS_CHK_IDX_SZ = 0x4, - UBIFS_CHK_ORPH = 0x8, - UBIFS_CHK_OLD_IDX = 0x10, - UBIFS_CHK_LPROPS = 0x20, - UBIFS_CHK_FS = 0x40, -}; - -/* - * Special testing flags (must match tst_names in debug.c). - * - * UBIFS_TST_FORCE_IN_THE_GAPS: force the use of in-the-gaps method - * UBIFS_TST_RCVRY: failure mode for recovery testing - */ -enum { - UBIFS_TST_FORCE_IN_THE_GAPS = 0x2, - UBIFS_TST_RCVRY = 0x4, -}; - -#if CONFIG_UBIFS_FS_DEBUG_MSG_LVL == 1 -#define UBIFS_MSG_FLAGS_DEFAULT UBIFS_MSG_LVL_1 -#elif CONFIG_UBIFS_FS_DEBUG_MSG_LVL == 2 -#define UBIFS_MSG_FLAGS_DEFAULT UBIFS_MSG_LVL_2 -#elif CONFIG_UBIFS_FS_DEBUG_MSG_LVL == 3 -#define UBIFS_MSG_FLAGS_DEFAULT UBIFS_MSG_LVL_3 -#else -#define UBIFS_MSG_FLAGS_DEFAULT UBIFS_MSG_LVL_0 -#endif - -#ifdef CONFIG_UBIFS_FS_DEBUG_CHKS -#define UBIFS_CHK_FLAGS_DEFAULT 0xffffffff +int ubifs_debugging_init(struct ubifs_info *c); +void ubifs_debugging_exit(struct ubifs_info *c); #else -#define UBIFS_CHK_FLAGS_DEFAULT 0 -#endif - -#define dbg_ntype(type) "" -#define dbg_cstate(cmt_state) "" -#define dbg_get_key_dump(c, key) ({}) -#define dbg_dump_inode(c, inode) ({}) -#define dbg_dump_node(c, node) ({}) -#define dbg_dump_budget_req(req) ({}) -#define dbg_dump_lstats(lst) ({}) -#define dbg_dump_budg(c) ({}) -#define dbg_dump_lprop(c, lp) ({}) -#define dbg_dump_lprops(c) ({}) -#define dbg_dump_lpt_info(c) ({}) -#define dbg_dump_leb(c, lnum) ({}) -#define dbg_dump_znode(c, znode) ({}) -#define dbg_dump_heap(c, heap, cat) ({}) -#define dbg_dump_pnode(c, pnode, parent, iip) ({}) -#define dbg_dump_tnc(c) ({}) -#define dbg_dump_index(c) ({}) - -#define dbg_walk_index(c, leaf_cb, znode_cb, priv) 0 -#define dbg_old_index_check_init(c, zroot) 0 -#define dbg_check_old_index(c, zroot) 0 -#define dbg_check_cats(c) 0 -#define dbg_check_ltab(c) 0 -#define dbg_chk_lpt_free_spc(c) 0 -#define dbg_chk_lpt_sz(c, action, len) 0 -#define dbg_check_synced_i_size(inode) 0 -#define dbg_check_dir_size(c, dir) 0 -#define dbg_check_tnc(c, x) 0 -#define dbg_check_idx_size(c, idx_size) 0 -#define dbg_check_filesystem(c) 0 -#define dbg_check_heap(c, heap, cat, add_pos) ({}) -#define dbg_check_lprops(c) 0 -#define dbg_check_lpt_nodes(c, cnode, row, col) 0 -#define dbg_force_in_the_gaps_enabled 0 -#define dbg_force_in_the_gaps() 0 -#define dbg_failure_mode 0 -#define dbg_failure_mode_registration(c) ({}) -#define dbg_failure_mode_deregistration(c) ({}) +static inline int dbg_is_chk_gen(const struct ubifs_info *c) +{ + return 0; +} +static inline int dbg_is_chk_index(const struct ubifs_info *c) +{ + return 0; +} +static inline int dbg_is_chk_orph(const struct ubifs_info *c) +{ + return 0; +} +static inline int dbg_is_chk_lprops(const struct ubifs_info *c) +{ + return 0; +} +static inline int dbg_is_chk_fs(const struct ubifs_info *c) +{ + return 0; +} +static inline int dbg_is_tst_rcvry(const struct ubifs_info *c) +{ + return 0; +} +static inline int dbg_is_power_cut(const struct ubifs_info *c) +{ + return 0; +} int ubifs_debugging_init(struct ubifs_info *c); void ubifs_debugging_exit(struct ubifs_info *c); -#else /* !CONFIG_UBIFS_FS_DEBUG */ - -#define UBIFS_DBG(op) - -/* Use "if (0)" to make compiler check arguments even if debugging is off */ -#define ubifs_assert(expr) do { \ - if (0 && (expr)) \ - printk(KERN_CRIT "UBIFS assert failed in %s at %u (pid %d)\n", \ - __func__, __LINE__, 0); \ -} while (0) - -#define dbg_err(fmt, ...) do { \ - if (0) \ - ubifs_err(fmt, ##__VA_ARGS__); \ -} while (0) - -#define dbg_msg(fmt, ...) do { \ - if (0) \ - printk(KERN_DEBUG "UBIFS DBG (pid %d): %s: " fmt "\n", \ - 0, __func__, ##__VA_ARGS__); \ -} while (0) - -#define dbg_dump_stack() -#define ubifs_assert_cmt_locked(c) - -#define dbg_gen(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_jnl(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_tnc(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_lp(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_find(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_mnt(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_io(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_cmt(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_budg(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_log(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_gc(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_scan(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) -#define dbg_rcvry(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) - -#define DBGKEY(key) ((char *)(key)) -#define DBGKEY1(key) ((char *)(key)) - -#define ubifs_debugging_init(c) 0 -#define ubifs_debugging_exit(c) ({}) - -#define dbg_ntype(type) "" -#define dbg_cstate(cmt_state) "" -#define dbg_get_key_dump(c, key) ({}) -#define dbg_dump_inode(c, inode) ({}) -#define dbg_dump_node(c, node) ({}) -#define dbg_dump_budget_req(req) ({}) -#define dbg_dump_lstats(lst) ({}) -#define dbg_dump_budg(c) ({}) -#define dbg_dump_lprop(c, lp) ({}) -#define dbg_dump_lprops(c) ({}) -#define dbg_dump_lpt_info(c) ({}) -#define dbg_dump_leb(c, lnum) ({}) -#define dbg_dump_znode(c, znode) ({}) -#define dbg_dump_heap(c, heap, cat) ({}) -#define dbg_dump_pnode(c, pnode, parent, iip) ({}) -#define dbg_dump_tnc(c) ({}) -#define dbg_dump_index(c) ({}) - -#define dbg_walk_index(c, leaf_cb, znode_cb, priv) 0 -#define dbg_old_index_check_init(c, zroot) 0 -#define dbg_check_old_index(c, zroot) 0 -#define dbg_check_cats(c) 0 -#define dbg_check_ltab(c) 0 -#define dbg_chk_lpt_free_spc(c) 0 -#define dbg_chk_lpt_sz(c, action, len) 0 -#define dbg_check_synced_i_size(inode) 0 -#define dbg_check_dir_size(c, dir) 0 -#define dbg_check_tnc(c, x) 0 -#define dbg_check_idx_size(c, idx_size) 0 -#define dbg_check_filesystem(c) 0 -#define dbg_check_heap(c, heap, cat, add_pos) ({}) -#define dbg_check_lprops(c) 0 -#define dbg_check_lpt_nodes(c, cnode, row, col) 0 -#define dbg_force_in_the_gaps_enabled 0 -#define dbg_force_in_the_gaps() 0 -#define dbg_failure_mode 0 -#define dbg_failure_mode_registration(c) ({}) -#define dbg_failure_mode_deregistration(c) ({}) +#endif -#endif /* !CONFIG_UBIFS_FS_DEBUG */ +/* Dump functions */ +const char *dbg_ntype(int type); +const char *dbg_cstate(int cmt_state); +const char *dbg_jhead(int jhead); +const char *dbg_get_key_dump(const struct ubifs_info *c, + const union ubifs_key *key); +const char *dbg_snprintf_key(const struct ubifs_info *c, + const union ubifs_key *key, char *buffer, int len); +void ubifs_dump_inode(struct ubifs_info *c, const struct inode *inode); +void ubifs_dump_node(const struct ubifs_info *c, const void *node); +void ubifs_dump_budget_req(const struct ubifs_budget_req *req); +void ubifs_dump_lstats(const struct ubifs_lp_stats *lst); +void ubifs_dump_budg(struct ubifs_info *c, const struct ubifs_budg_info *bi); +void ubifs_dump_lprop(const struct ubifs_info *c, + const struct ubifs_lprops *lp); +void ubifs_dump_lprops(struct ubifs_info *c); +void ubifs_dump_lpt_info(struct ubifs_info *c); +void ubifs_dump_leb(const struct ubifs_info *c, int lnum); +void ubifs_dump_sleb(const struct ubifs_info *c, + const struct ubifs_scan_leb *sleb, int offs); +void ubifs_dump_znode(const struct ubifs_info *c, + const struct ubifs_znode *znode); +void ubifs_dump_heap(struct ubifs_info *c, struct ubifs_lpt_heap *heap, + int cat); +void ubifs_dump_pnode(struct ubifs_info *c, struct ubifs_pnode *pnode, + struct ubifs_nnode *parent, int iip); +void ubifs_dump_tnc(struct ubifs_info *c); +void ubifs_dump_index(struct ubifs_info *c); +void ubifs_dump_lpt_lebs(const struct ubifs_info *c); + +int dbg_walk_index(struct ubifs_info *c, dbg_leaf_callback leaf_cb, + dbg_znode_callback znode_cb, void *priv); + +/* Checking functions */ +void dbg_save_space_info(struct ubifs_info *c); +int dbg_check_space_info(struct ubifs_info *c); +int dbg_check_lprops(struct ubifs_info *c); +int dbg_old_index_check_init(struct ubifs_info *c, struct ubifs_zbranch *zroot); +int dbg_check_old_index(struct ubifs_info *c, struct ubifs_zbranch *zroot); +int dbg_check_cats(struct ubifs_info *c); +int dbg_check_ltab(struct ubifs_info *c); +int dbg_chk_lpt_free_spc(struct ubifs_info *c); +int dbg_chk_lpt_sz(struct ubifs_info *c, int action, int len); +int dbg_check_synced_i_size(const struct ubifs_info *c, struct inode *inode); +int dbg_check_dir(struct ubifs_info *c, const struct inode *dir); +int dbg_check_tnc(struct ubifs_info *c, int extra); +int dbg_check_idx_size(struct ubifs_info *c, long long idx_size); +int dbg_check_filesystem(struct ubifs_info *c); +void dbg_check_heap(struct ubifs_info *c, struct ubifs_lpt_heap *heap, int cat, + int add_pos); +int dbg_check_lpt_nodes(struct ubifs_info *c, struct ubifs_cnode *cnode, + int row, int col); +int dbg_check_inode_size(struct ubifs_info *c, const struct inode *inode, + loff_t size); +int dbg_check_data_nodes_order(struct ubifs_info *c, struct list_head *head); +int dbg_check_nondata_nodes_order(struct ubifs_info *c, struct list_head *head); + +int dbg_leb_write(struct ubifs_info *c, int lnum, const void *buf, int offs, + int len); +int dbg_leb_change(struct ubifs_info *c, int lnum, const void *buf, int len); +int dbg_leb_unmap(struct ubifs_info *c, int lnum); +int dbg_leb_map(struct ubifs_info *c, int lnum); + +/* Debugfs-related stuff */ +int dbg_debugfs_init(void); +void dbg_debugfs_exit(void); +int dbg_debugfs_init_fs(struct ubifs_info *c); +void dbg_debugfs_exit_fs(struct ubifs_info *c); #endif /* !__UBIFS_DEBUG_H__ */ diff --git a/fs/ubifs/io.c b/fs/ubifs/io.c index aae5c65eae..bdccdc45e1 100644 --- a/fs/ubifs/io.c +++ b/fs/ubifs/io.c @@ -4,18 +4,7 @@ * Copyright (C) 2006-2008 Nokia Corporation. * Copyright (C) 2006, 2007 University of Szeged, Hungary * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -31,6 +20,26 @@ * buffer is full or when it is not used for some time (by timer). This is * similar to the mechanism is used by JFFS2. * + * UBIFS distinguishes between minimum write size (@c->min_io_size) and maximum + * write size (@c->max_write_size). The latter is the maximum amount of bytes + * the underlying flash is able to program at a time, and writing in + * @c->max_write_size units should presumably be faster. Obviously, + * @c->min_io_size <= @c->max_write_size. Write-buffers are of + * @c->max_write_size bytes in size for maximum performance. However, when a + * write-buffer is flushed, only the portion of it (aligned to @c->min_io_size + * boundary) which contains data is written, not the whole write-buffer, + * because this is more space-efficient. + * + * This optimization adds few complications to the code. Indeed, on the one + * hand, we want to write in optimal @c->max_write_size bytes chunks, which + * also means aligning writes at the @c->max_write_size bytes offsets. On the + * other hand, we do not want to waste space when synchronizing the write + * buffer, so during synchronization we writes in smaller chunks. And this makes + * the next write offset to be not aligned to @c->max_write_size bytes. So the + * have to make sure that the write-buffer offset (@wbuf->offs) becomes aligned + * to @c->max_write_size bytes again. We do this by temporarily shrinking + * write-buffer size (@wbuf->size). + * * Write-buffers are defined by 'struct ubifs_wbuf' objects and protected by * mutexes defined inside these objects. Since sometimes upper-level code * has to lock the write-buffer (e.g. journal space reservation code), many @@ -46,10 +55,17 @@ * UBIFS uses padding when it pads to the next min. I/O unit. In this case it * uses padding nodes or padding bytes, if the padding node does not fit. * - * All UBIFS nodes are protected by CRC checksums and UBIFS checks all nodes - * every time they are read from the flash media. + * All UBIFS nodes are protected by CRC checksums and UBIFS checks CRC when + * they are read from the flash media. */ +#ifndef __UBOOT__ +#include +#include +#else +#include +#include +#endif #include "ubifs.h" /** @@ -59,12 +75,129 @@ */ void ubifs_ro_mode(struct ubifs_info *c, int err) { - if (!c->ro_media) { - c->ro_media = 1; + if (!c->ro_error) { + c->ro_error = 1; c->no_chk_data_crc = 0; + c->vfs_sb->s_flags |= MS_RDONLY; ubifs_warn("switched to read-only mode, error %d", err); - dbg_dump_stack(); + dump_stack(); + } +} + +/* + * Below are simple wrappers over UBI I/O functions which include some + * additional checks and UBIFS debugging stuff. See corresponding UBI function + * for more information. + */ + +int ubifs_leb_read(const struct ubifs_info *c, int lnum, void *buf, int offs, + int len, int even_ebadmsg) +{ + int err; + + err = ubi_read(c->ubi, lnum, buf, offs, len); + /* + * In case of %-EBADMSG print the error message only if the + * @even_ebadmsg is true. + */ + if (err && (err != -EBADMSG || even_ebadmsg)) { + ubifs_err("reading %d bytes from LEB %d:%d failed, error %d", + len, lnum, offs, err); + dump_stack(); + } + return err; +} + +int ubifs_leb_write(struct ubifs_info *c, int lnum, const void *buf, int offs, + int len) +{ + int err; + + ubifs_assert(!c->ro_media && !c->ro_mount); + if (c->ro_error) + return -EROFS; + if (!dbg_is_tst_rcvry(c)) + err = ubi_leb_write(c->ubi, lnum, buf, offs, len); + else + err = dbg_leb_write(c, lnum, buf, offs, len); + if (err) { + ubifs_err("writing %d bytes to LEB %d:%d failed, error %d", + len, lnum, offs, err); + ubifs_ro_mode(c, err); + dump_stack(); + } + return err; +} + +int ubifs_leb_change(struct ubifs_info *c, int lnum, const void *buf, int len) +{ + int err; + + ubifs_assert(!c->ro_media && !c->ro_mount); + if (c->ro_error) + return -EROFS; + if (!dbg_is_tst_rcvry(c)) + err = ubi_leb_change(c->ubi, lnum, buf, len); + else + err = dbg_leb_change(c, lnum, buf, len); + if (err) { + ubifs_err("changing %d bytes in LEB %d failed, error %d", + len, lnum, err); + ubifs_ro_mode(c, err); + dump_stack(); } + return err; +} + +int ubifs_leb_unmap(struct ubifs_info *c, int lnum) +{ + int err; + + ubifs_assert(!c->ro_media && !c->ro_mount); + if (c->ro_error) + return -EROFS; + if (!dbg_is_tst_rcvry(c)) + err = ubi_leb_unmap(c->ubi, lnum); + else + err = dbg_leb_unmap(c, lnum); + if (err) { + ubifs_err("unmap LEB %d failed, error %d", lnum, err); + ubifs_ro_mode(c, err); + dump_stack(); + } + return err; +} + +int ubifs_leb_map(struct ubifs_info *c, int lnum) +{ + int err; + + ubifs_assert(!c->ro_media && !c->ro_mount); + if (c->ro_error) + return -EROFS; + if (!dbg_is_tst_rcvry(c)) + err = ubi_leb_map(c->ubi, lnum); + else + err = dbg_leb_map(c, lnum); + if (err) { + ubifs_err("mapping LEB %d failed, error %d", lnum, err); + ubifs_ro_mode(c, err); + dump_stack(); + } + return err; +} + +int ubifs_is_mapped(const struct ubifs_info *c, int lnum) +{ + int err; + + err = ubi_is_mapped(c->ubi, lnum); + if (err < 0) { + ubifs_err("ubi_is_mapped failed for LEB %d, error %d", + lnum, err); + dump_stack(); + } + return err; } /** @@ -85,8 +218,12 @@ void ubifs_ro_mode(struct ubifs_info *c, int err) * This function may skip data nodes CRC checking if @c->no_chk_data_crc is * true, which is controlled by corresponding UBIFS mount option. However, if * @must_chk_crc is true, then @c->no_chk_data_crc is ignored and CRC is - * checked. Similarly, if @c->always_chk_crc is true, @c->no_chk_data_crc is - * ignored and CRC is checked. + * checked. Similarly, if @c->mounting or @c->remounting_rw is true (we are + * mounting or re-mounting to R/W mode), @c->no_chk_data_crc is ignored and CRC + * is checked. This is because during mounting or re-mounting from R/O mode to + * R/W mode we may read journal nodes (when replying the journal or doing the + * recovery) and the journal nodes may potentially be corrupted, so checking is + * required. * * This function returns zero in case of success and %-EUCLEAN in case of bad * CRC or magic. @@ -128,8 +265,8 @@ int ubifs_check_node(const struct ubifs_info *c, const void *buf, int lnum, node_len > c->ranges[type].max_len) goto out_len; - if (!must_chk_crc && type == UBIFS_DATA_NODE && !c->always_chk_crc && - c->no_chk_data_crc) + if (!must_chk_crc && type == UBIFS_DATA_NODE && !c->mounting && + !c->remounting_rw && c->no_chk_data_crc) return 0; crc = crc32(UBIFS_CRC32_INIT, buf + 8, node_len - 8); @@ -150,8 +287,8 @@ out_len: out: if (!quiet) { ubifs_err("bad node at LEB %d:%d", lnum, offs); - dbg_dump_node(c, buf); - dbg_dump_stack(); + ubifs_dump_node(c, buf); + dump_stack(); } return err; } @@ -256,6 +393,571 @@ void ubifs_prepare_node(struct ubifs_info *c, void *node, int len, int pad) } } +/** + * ubifs_prep_grp_node - prepare node of a group to be written to flash. + * @c: UBIFS file-system description object + * @node: the node to pad + * @len: node length + * @last: indicates the last node of the group + * + * This function prepares node at @node to be written to the media - it + * calculates node CRC and fills the common header. + */ +void ubifs_prep_grp_node(struct ubifs_info *c, void *node, int len, int last) +{ + uint32_t crc; + struct ubifs_ch *ch = node; + unsigned long long sqnum = next_sqnum(c); + + ubifs_assert(len >= UBIFS_CH_SZ); + + ch->magic = cpu_to_le32(UBIFS_NODE_MAGIC); + ch->len = cpu_to_le32(len); + if (last) + ch->group_type = UBIFS_LAST_OF_NODE_GROUP; + else + ch->group_type = UBIFS_IN_NODE_GROUP; + ch->sqnum = cpu_to_le64(sqnum); + ch->padding[0] = ch->padding[1] = 0; + crc = crc32(UBIFS_CRC32_INIT, node + 8, len - 8); + ch->crc = cpu_to_le32(crc); +} + +#ifndef __UBOOT__ +/** + * wbuf_timer_callback - write-buffer timer callback function. + * @data: timer data (write-buffer descriptor) + * + * This function is called when the write-buffer timer expires. + */ +static enum hrtimer_restart wbuf_timer_callback_nolock(struct hrtimer *timer) +{ + struct ubifs_wbuf *wbuf = container_of(timer, struct ubifs_wbuf, timer); + + dbg_io("jhead %s", dbg_jhead(wbuf->jhead)); + wbuf->need_sync = 1; + wbuf->c->need_wbuf_sync = 1; + ubifs_wake_up_bgt(wbuf->c); + return HRTIMER_NORESTART; +} + +/** + * new_wbuf_timer - start new write-buffer timer. + * @wbuf: write-buffer descriptor + */ +static void new_wbuf_timer_nolock(struct ubifs_wbuf *wbuf) +{ + ubifs_assert(!hrtimer_active(&wbuf->timer)); + + if (wbuf->no_timer) + return; + dbg_io("set timer for jhead %s, %llu-%llu millisecs", + dbg_jhead(wbuf->jhead), + div_u64(ktime_to_ns(wbuf->softlimit), USEC_PER_SEC), + div_u64(ktime_to_ns(wbuf->softlimit) + wbuf->delta, + USEC_PER_SEC)); + hrtimer_start_range_ns(&wbuf->timer, wbuf->softlimit, wbuf->delta, + HRTIMER_MODE_REL); +} +#endif + +/** + * cancel_wbuf_timer - cancel write-buffer timer. + * @wbuf: write-buffer descriptor + */ +static void cancel_wbuf_timer_nolock(struct ubifs_wbuf *wbuf) +{ + if (wbuf->no_timer) + return; + wbuf->need_sync = 0; +#ifndef __UBOOT__ + hrtimer_cancel(&wbuf->timer); +#endif +} + +/** + * ubifs_wbuf_sync_nolock - synchronize write-buffer. + * @wbuf: write-buffer to synchronize + * + * This function synchronizes write-buffer @buf and returns zero in case of + * success or a negative error code in case of failure. + * + * Note, although write-buffers are of @c->max_write_size, this function does + * not necessarily writes all @c->max_write_size bytes to the flash. Instead, + * if the write-buffer is only partially filled with data, only the used part + * of the write-buffer (aligned on @c->min_io_size boundary) is synchronized. + * This way we waste less space. + */ +int ubifs_wbuf_sync_nolock(struct ubifs_wbuf *wbuf) +{ + struct ubifs_info *c = wbuf->c; + int err, dirt, sync_len; + + cancel_wbuf_timer_nolock(wbuf); + if (!wbuf->used || wbuf->lnum == -1) + /* Write-buffer is empty or not seeked */ + return 0; + + dbg_io("LEB %d:%d, %d bytes, jhead %s", + wbuf->lnum, wbuf->offs, wbuf->used, dbg_jhead(wbuf->jhead)); + ubifs_assert(!(wbuf->avail & 7)); + ubifs_assert(wbuf->offs + wbuf->size <= c->leb_size); + ubifs_assert(wbuf->size >= c->min_io_size); + ubifs_assert(wbuf->size <= c->max_write_size); + ubifs_assert(wbuf->size % c->min_io_size == 0); + ubifs_assert(!c->ro_media && !c->ro_mount); + if (c->leb_size - wbuf->offs >= c->max_write_size) + ubifs_assert(!((wbuf->offs + wbuf->size) % c->max_write_size)); + + if (c->ro_error) + return -EROFS; + + /* + * Do not write whole write buffer but write only the minimum necessary + * amount of min. I/O units. + */ + sync_len = ALIGN(wbuf->used, c->min_io_size); + dirt = sync_len - wbuf->used; + if (dirt) + ubifs_pad(c, wbuf->buf + wbuf->used, dirt); + err = ubifs_leb_write(c, wbuf->lnum, wbuf->buf, wbuf->offs, sync_len); + if (err) + return err; + + spin_lock(&wbuf->lock); + wbuf->offs += sync_len; + /* + * Now @wbuf->offs is not necessarily aligned to @c->max_write_size. + * But our goal is to optimize writes and make sure we write in + * @c->max_write_size chunks and to @c->max_write_size-aligned offset. + * Thus, if @wbuf->offs is not aligned to @c->max_write_size now, make + * sure that @wbuf->offs + @wbuf->size is aligned to + * @c->max_write_size. This way we make sure that after next + * write-buffer flush we are again at the optimal offset (aligned to + * @c->max_write_size). + */ + if (c->leb_size - wbuf->offs < c->max_write_size) + wbuf->size = c->leb_size - wbuf->offs; + else if (wbuf->offs & (c->max_write_size - 1)) + wbuf->size = ALIGN(wbuf->offs, c->max_write_size) - wbuf->offs; + else + wbuf->size = c->max_write_size; + wbuf->avail = wbuf->size; + wbuf->used = 0; + wbuf->next_ino = 0; + spin_unlock(&wbuf->lock); + + if (wbuf->sync_callback) + err = wbuf->sync_callback(c, wbuf->lnum, + c->leb_size - wbuf->offs, dirt); + return err; +} + +/** + * ubifs_wbuf_seek_nolock - seek write-buffer. + * @wbuf: write-buffer + * @lnum: logical eraseblock number to seek to + * @offs: logical eraseblock offset to seek to + * + * This function targets the write-buffer to logical eraseblock @lnum:@offs. + * The write-buffer has to be empty. Returns zero in case of success and a + * negative error code in case of failure. + */ +int ubifs_wbuf_seek_nolock(struct ubifs_wbuf *wbuf, int lnum, int offs) +{ + const struct ubifs_info *c = wbuf->c; + + dbg_io("LEB %d:%d, jhead %s", lnum, offs, dbg_jhead(wbuf->jhead)); + ubifs_assert(lnum >= 0 && lnum < c->leb_cnt); + ubifs_assert(offs >= 0 && offs <= c->leb_size); + ubifs_assert(offs % c->min_io_size == 0 && !(offs & 7)); + ubifs_assert(lnum != wbuf->lnum); + ubifs_assert(wbuf->used == 0); + + spin_lock(&wbuf->lock); + wbuf->lnum = lnum; + wbuf->offs = offs; + if (c->leb_size - wbuf->offs < c->max_write_size) + wbuf->size = c->leb_size - wbuf->offs; + else if (wbuf->offs & (c->max_write_size - 1)) + wbuf->size = ALIGN(wbuf->offs, c->max_write_size) - wbuf->offs; + else + wbuf->size = c->max_write_size; + wbuf->avail = wbuf->size; + wbuf->used = 0; + spin_unlock(&wbuf->lock); + + return 0; +} + +#ifndef __UBOOT__ +/** + * ubifs_bg_wbufs_sync - synchronize write-buffers. + * @c: UBIFS file-system description object + * + * This function is called by background thread to synchronize write-buffers. + * Returns zero in case of success and a negative error code in case of + * failure. + */ +int ubifs_bg_wbufs_sync(struct ubifs_info *c) +{ + int err, i; + + ubifs_assert(!c->ro_media && !c->ro_mount); + if (!c->need_wbuf_sync) + return 0; + c->need_wbuf_sync = 0; + + if (c->ro_error) { + err = -EROFS; + goto out_timers; + } + + dbg_io("synchronize"); + for (i = 0; i < c->jhead_cnt; i++) { + struct ubifs_wbuf *wbuf = &c->jheads[i].wbuf; + + cond_resched(); + + /* + * If the mutex is locked then wbuf is being changed, so + * synchronization is not necessary. + */ + if (mutex_is_locked(&wbuf->io_mutex)) + continue; + + mutex_lock_nested(&wbuf->io_mutex, wbuf->jhead); + if (!wbuf->need_sync) { + mutex_unlock(&wbuf->io_mutex); + continue; + } + + err = ubifs_wbuf_sync_nolock(wbuf); + mutex_unlock(&wbuf->io_mutex); + if (err) { + ubifs_err("cannot sync write-buffer, error %d", err); + ubifs_ro_mode(c, err); + goto out_timers; + } + } + + return 0; + +out_timers: + /* Cancel all timers to prevent repeated errors */ + for (i = 0; i < c->jhead_cnt; i++) { + struct ubifs_wbuf *wbuf = &c->jheads[i].wbuf; + + mutex_lock_nested(&wbuf->io_mutex, wbuf->jhead); + cancel_wbuf_timer_nolock(wbuf); + mutex_unlock(&wbuf->io_mutex); + } + return err; +} + +/** + * ubifs_wbuf_write_nolock - write data to flash via write-buffer. + * @wbuf: write-buffer + * @buf: node to write + * @len: node length + * + * This function writes data to flash via write-buffer @wbuf. This means that + * the last piece of the node won't reach the flash media immediately if it + * does not take whole max. write unit (@c->max_write_size). Instead, the node + * will sit in RAM until the write-buffer is synchronized (e.g., by timer, or + * because more data are appended to the write-buffer). + * + * This function returns zero in case of success and a negative error code in + * case of failure. If the node cannot be written because there is no more + * space in this logical eraseblock, %-ENOSPC is returned. + */ +int ubifs_wbuf_write_nolock(struct ubifs_wbuf *wbuf, void *buf, int len) +{ + struct ubifs_info *c = wbuf->c; + int err, written, n, aligned_len = ALIGN(len, 8); + + dbg_io("%d bytes (%s) to jhead %s wbuf at LEB %d:%d", len, + dbg_ntype(((struct ubifs_ch *)buf)->node_type), + dbg_jhead(wbuf->jhead), wbuf->lnum, wbuf->offs + wbuf->used); + ubifs_assert(len > 0 && wbuf->lnum >= 0 && wbuf->lnum < c->leb_cnt); + ubifs_assert(wbuf->offs >= 0 && wbuf->offs % c->min_io_size == 0); + ubifs_assert(!(wbuf->offs & 7) && wbuf->offs <= c->leb_size); + ubifs_assert(wbuf->avail > 0 && wbuf->avail <= wbuf->size); + ubifs_assert(wbuf->size >= c->min_io_size); + ubifs_assert(wbuf->size <= c->max_write_size); + ubifs_assert(wbuf->size % c->min_io_size == 0); + ubifs_assert(mutex_is_locked(&wbuf->io_mutex)); + ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(!c->space_fixup); + if (c->leb_size - wbuf->offs >= c->max_write_size) + ubifs_assert(!((wbuf->offs + wbuf->size) % c->max_write_size)); + + if (c->leb_size - wbuf->offs - wbuf->used < aligned_len) { + err = -ENOSPC; + goto out; + } + + cancel_wbuf_timer_nolock(wbuf); + + if (c->ro_error) + return -EROFS; + + if (aligned_len <= wbuf->avail) { + /* + * The node is not very large and fits entirely within + * write-buffer. + */ + memcpy(wbuf->buf + wbuf->used, buf, len); + + if (aligned_len == wbuf->avail) { + dbg_io("flush jhead %s wbuf to LEB %d:%d", + dbg_jhead(wbuf->jhead), wbuf->lnum, wbuf->offs); + err = ubifs_leb_write(c, wbuf->lnum, wbuf->buf, + wbuf->offs, wbuf->size); + if (err) + goto out; + + spin_lock(&wbuf->lock); + wbuf->offs += wbuf->size; + if (c->leb_size - wbuf->offs >= c->max_write_size) + wbuf->size = c->max_write_size; + else + wbuf->size = c->leb_size - wbuf->offs; + wbuf->avail = wbuf->size; + wbuf->used = 0; + wbuf->next_ino = 0; + spin_unlock(&wbuf->lock); + } else { + spin_lock(&wbuf->lock); + wbuf->avail -= aligned_len; + wbuf->used += aligned_len; + spin_unlock(&wbuf->lock); + } + + goto exit; + } + + written = 0; + + if (wbuf->used) { + /* + * The node is large enough and does not fit entirely within + * current available space. We have to fill and flush + * write-buffer and switch to the next max. write unit. + */ + dbg_io("flush jhead %s wbuf to LEB %d:%d", + dbg_jhead(wbuf->jhead), wbuf->lnum, wbuf->offs); + memcpy(wbuf->buf + wbuf->used, buf, wbuf->avail); + err = ubifs_leb_write(c, wbuf->lnum, wbuf->buf, wbuf->offs, + wbuf->size); + if (err) + goto out; + + wbuf->offs += wbuf->size; + len -= wbuf->avail; + aligned_len -= wbuf->avail; + written += wbuf->avail; + } else if (wbuf->offs & (c->max_write_size - 1)) { + /* + * The write-buffer offset is not aligned to + * @c->max_write_size and @wbuf->size is less than + * @c->max_write_size. Write @wbuf->size bytes to make sure the + * following writes are done in optimal @c->max_write_size + * chunks. + */ + dbg_io("write %d bytes to LEB %d:%d", + wbuf->size, wbuf->lnum, wbuf->offs); + err = ubifs_leb_write(c, wbuf->lnum, buf, wbuf->offs, + wbuf->size); + if (err) + goto out; + + wbuf->offs += wbuf->size; + len -= wbuf->size; + aligned_len -= wbuf->size; + written += wbuf->size; + } + + /* + * The remaining data may take more whole max. write units, so write the + * remains multiple to max. write unit size directly to the flash media. + * We align node length to 8-byte boundary because we anyway flash wbuf + * if the remaining space is less than 8 bytes. + */ + n = aligned_len >> c->max_write_shift; + if (n) { + n <<= c->max_write_shift; + dbg_io("write %d bytes to LEB %d:%d", n, wbuf->lnum, + wbuf->offs); + err = ubifs_leb_write(c, wbuf->lnum, buf + written, + wbuf->offs, n); + if (err) + goto out; + wbuf->offs += n; + aligned_len -= n; + len -= n; + written += n; + } + + spin_lock(&wbuf->lock); + if (aligned_len) + /* + * And now we have what's left and what does not take whole + * max. write unit, so write it to the write-buffer and we are + * done. + */ + memcpy(wbuf->buf, buf + written, len); + + if (c->leb_size - wbuf->offs >= c->max_write_size) + wbuf->size = c->max_write_size; + else + wbuf->size = c->leb_size - wbuf->offs; + wbuf->avail = wbuf->size - aligned_len; + wbuf->used = aligned_len; + wbuf->next_ino = 0; + spin_unlock(&wbuf->lock); + +exit: + if (wbuf->sync_callback) { + int free = c->leb_size - wbuf->offs - wbuf->used; + + err = wbuf->sync_callback(c, wbuf->lnum, free, 0); + if (err) + goto out; + } + + if (wbuf->used) + new_wbuf_timer_nolock(wbuf); + + return 0; + +out: + ubifs_err("cannot write %d bytes to LEB %d:%d, error %d", + len, wbuf->lnum, wbuf->offs, err); + ubifs_dump_node(c, buf); + dump_stack(); + ubifs_dump_leb(c, wbuf->lnum); + return err; +} + +/** + * ubifs_write_node - write node to the media. + * @c: UBIFS file-system description object + * @buf: the node to write + * @len: node length + * @lnum: logical eraseblock number + * @offs: offset within the logical eraseblock + * + * This function automatically fills node magic number, assigns sequence + * number, and calculates node CRC checksum. The length of the @buf buffer has + * to be aligned to the minimal I/O unit size. This function automatically + * appends padding node and padding bytes if needed. Returns zero in case of + * success and a negative error code in case of failure. + */ +int ubifs_write_node(struct ubifs_info *c, void *buf, int len, int lnum, + int offs) +{ + int err, buf_len = ALIGN(len, c->min_io_size); + + dbg_io("LEB %d:%d, %s, length %d (aligned %d)", + lnum, offs, dbg_ntype(((struct ubifs_ch *)buf)->node_type), len, + buf_len); + ubifs_assert(lnum >= 0 && lnum < c->leb_cnt && offs >= 0); + ubifs_assert(offs % c->min_io_size == 0 && offs < c->leb_size); + ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(!c->space_fixup); + + if (c->ro_error) + return -EROFS; + + ubifs_prepare_node(c, buf, len, 1); + err = ubifs_leb_write(c, lnum, buf, offs, buf_len); + if (err) + ubifs_dump_node(c, buf); + + return err; +} +#endif + +/** + * ubifs_read_node_wbuf - read node from the media or write-buffer. + * @wbuf: wbuf to check for un-written data + * @buf: buffer to read to + * @type: node type + * @len: node length + * @lnum: logical eraseblock number + * @offs: offset within the logical eraseblock + * + * This function reads a node of known type and length, checks it and stores + * in @buf. If the node partially or fully sits in the write-buffer, this + * function takes data from the buffer, otherwise it reads the flash media. + * Returns zero in case of success, %-EUCLEAN if CRC mismatched and a negative + * error code in case of failure. + */ +int ubifs_read_node_wbuf(struct ubifs_wbuf *wbuf, void *buf, int type, int len, + int lnum, int offs) +{ + const struct ubifs_info *c = wbuf->c; + int err, rlen, overlap; + struct ubifs_ch *ch = buf; + + dbg_io("LEB %d:%d, %s, length %d, jhead %s", lnum, offs, + dbg_ntype(type), len, dbg_jhead(wbuf->jhead)); + ubifs_assert(wbuf && lnum >= 0 && lnum < c->leb_cnt && offs >= 0); + ubifs_assert(!(offs & 7) && offs < c->leb_size); + ubifs_assert(type >= 0 && type < UBIFS_NODE_TYPES_CNT); + + spin_lock(&wbuf->lock); + overlap = (lnum == wbuf->lnum && offs + len > wbuf->offs); + if (!overlap) { + /* We may safely unlock the write-buffer and read the data */ + spin_unlock(&wbuf->lock); + return ubifs_read_node(c, buf, type, len, lnum, offs); + } + + /* Don't read under wbuf */ + rlen = wbuf->offs - offs; + if (rlen < 0) + rlen = 0; + + /* Copy the rest from the write-buffer */ + memcpy(buf + rlen, wbuf->buf + offs + rlen - wbuf->offs, len - rlen); + spin_unlock(&wbuf->lock); + + if (rlen > 0) { + /* Read everything that goes before write-buffer */ + err = ubifs_leb_read(c, lnum, buf, offs, rlen, 0); + if (err && err != -EBADMSG) + return err; + } + + if (type != ch->node_type) { + ubifs_err("bad node type (%d but expected %d)", + ch->node_type, type); + goto out; + } + + err = ubifs_check_node(c, buf, lnum, offs, 0, 0); + if (err) { + ubifs_err("expected node type %d", type); + return err; + } + + rlen = le32_to_cpu(ch->len); + if (rlen != len) { + ubifs_err("bad node length %d, expected %d", rlen, len); + goto out; + } + + return 0; + +out: + ubifs_err("bad node at LEB %d:%d", lnum, offs); + ubifs_dump_node(c, buf); + dump_stack(); + return -EINVAL; +} + /** * ubifs_read_node - read node. * @c: UBIFS file-system description object @@ -281,12 +983,9 @@ int ubifs_read_node(const struct ubifs_info *c, void *buf, int type, int len, ubifs_assert(!(offs & 7) && offs < c->leb_size); ubifs_assert(type >= 0 && type < UBIFS_NODE_TYPES_CNT); - err = ubi_read(c->ubi, lnum, buf, offs, len); - if (err && err != -EBADMSG) { - ubifs_err("cannot read node %d from LEB %d:%d, error %d", - type, lnum, offs, err); + err = ubifs_leb_read(c, lnum, buf, offs, len, 0); + if (err && err != -EBADMSG) return err; - } if (type != ch->node_type) { ubifs_err("bad node type (%d but expected %d)", @@ -309,8 +1008,143 @@ int ubifs_read_node(const struct ubifs_info *c, void *buf, int type, int len, return 0; out: - ubifs_err("bad node at LEB %d:%d", lnum, offs); - dbg_dump_node(c, buf); - dbg_dump_stack(); + ubifs_err("bad node at LEB %d:%d, LEB mapping status %d", lnum, offs, + ubi_is_mapped(c->ubi, lnum)); + ubifs_dump_node(c, buf); + dump_stack(); return -EINVAL; } + +/** + * ubifs_wbuf_init - initialize write-buffer. + * @c: UBIFS file-system description object + * @wbuf: write-buffer to initialize + * + * This function initializes write-buffer. Returns zero in case of success + * %-ENOMEM in case of failure. + */ +int ubifs_wbuf_init(struct ubifs_info *c, struct ubifs_wbuf *wbuf) +{ + size_t size; + + wbuf->buf = kmalloc(c->max_write_size, GFP_KERNEL); + if (!wbuf->buf) + return -ENOMEM; + + size = (c->max_write_size / UBIFS_CH_SZ + 1) * sizeof(ino_t); + wbuf->inodes = kmalloc(size, GFP_KERNEL); + if (!wbuf->inodes) { + kfree(wbuf->buf); + wbuf->buf = NULL; + return -ENOMEM; + } + + wbuf->used = 0; + wbuf->lnum = wbuf->offs = -1; + /* + * If the LEB starts at the max. write size aligned address, then + * write-buffer size has to be set to @c->max_write_size. Otherwise, + * set it to something smaller so that it ends at the closest max. + * write size boundary. + */ + size = c->max_write_size - (c->leb_start % c->max_write_size); + wbuf->avail = wbuf->size = size; + wbuf->sync_callback = NULL; + mutex_init(&wbuf->io_mutex); + spin_lock_init(&wbuf->lock); + wbuf->c = c; + wbuf->next_ino = 0; + +#ifndef __UBOOT__ + hrtimer_init(&wbuf->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + wbuf->timer.function = wbuf_timer_callback_nolock; + wbuf->softlimit = ktime_set(WBUF_TIMEOUT_SOFTLIMIT, 0); + wbuf->delta = WBUF_TIMEOUT_HARDLIMIT - WBUF_TIMEOUT_SOFTLIMIT; + wbuf->delta *= 1000000000ULL; + ubifs_assert(wbuf->delta <= ULONG_MAX); +#endif + return 0; +} + +/** + * ubifs_wbuf_add_ino_nolock - add an inode number into the wbuf inode array. + * @wbuf: the write-buffer where to add + * @inum: the inode number + * + * This function adds an inode number to the inode array of the write-buffer. + */ +void ubifs_wbuf_add_ino_nolock(struct ubifs_wbuf *wbuf, ino_t inum) +{ + if (!wbuf->buf) + /* NOR flash or something similar */ + return; + + spin_lock(&wbuf->lock); + if (wbuf->used) + wbuf->inodes[wbuf->next_ino++] = inum; + spin_unlock(&wbuf->lock); +} + +/** + * wbuf_has_ino - returns if the wbuf contains data from the inode. + * @wbuf: the write-buffer + * @inum: the inode number + * + * This function returns with %1 if the write-buffer contains some data from the + * given inode otherwise it returns with %0. + */ +static int wbuf_has_ino(struct ubifs_wbuf *wbuf, ino_t inum) +{ + int i, ret = 0; + + spin_lock(&wbuf->lock); + for (i = 0; i < wbuf->next_ino; i++) + if (inum == wbuf->inodes[i]) { + ret = 1; + break; + } + spin_unlock(&wbuf->lock); + + return ret; +} + +/** + * ubifs_sync_wbufs_by_inode - synchronize write-buffers for an inode. + * @c: UBIFS file-system description object + * @inode: inode to synchronize + * + * This function synchronizes write-buffers which contain nodes belonging to + * @inode. Returns zero in case of success and a negative error code in case of + * failure. + */ +int ubifs_sync_wbufs_by_inode(struct ubifs_info *c, struct inode *inode) +{ + int i, err = 0; + + for (i = 0; i < c->jhead_cnt; i++) { + struct ubifs_wbuf *wbuf = &c->jheads[i].wbuf; + + if (i == GCHD) + /* + * GC head is special, do not look at it. Even if the + * head contains something related to this inode, it is + * a _copy_ of corresponding on-flash node which sits + * somewhere else. + */ + continue; + + if (!wbuf_has_ino(wbuf, inode->i_ino)) + continue; + + mutex_lock_nested(&wbuf->io_mutex, wbuf->jhead); + if (wbuf_has_ino(wbuf, inode->i_ino)) + err = ubifs_wbuf_sync_nolock(wbuf); + mutex_unlock(&wbuf->io_mutex); + + if (err) { + ubifs_ro_mode(c, err); + return err; + } + } + return 0; +} diff --git a/fs/ubifs/key.h b/fs/ubifs/key.h index efb3430a25..b5c4884e30 100644 --- a/fs/ubifs/key.h +++ b/fs/ubifs/key.h @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -228,23 +217,6 @@ static inline void xent_key_init(const struct ubifs_info *c, key->u32[1] = hash | (UBIFS_XENT_KEY << UBIFS_S_KEY_HASH_BITS); } -/** - * xent_key_init_hash - initialize extended attribute entry key without - * re-calculating hash function. - * @c: UBIFS file-system description object - * @key: key to initialize - * @inum: host inode number - * @hash: extended attribute entry name hash - */ -static inline void xent_key_init_hash(const struct ubifs_info *c, - union ubifs_key *key, ino_t inum, - uint32_t hash) -{ - ubifs_assert(!(hash & ~UBIFS_S_KEY_HASH_MASK)); - key->u32[0] = inum; - key->u32[1] = hash | (UBIFS_XENT_KEY << UBIFS_S_KEY_HASH_BITS); -} - /** * xent_key_init_flash - initialize on-flash extended attribute entry key. * @c: UBIFS file-system description object @@ -295,22 +267,15 @@ static inline void data_key_init(const struct ubifs_info *c, } /** - * data_key_init_flash - initialize on-flash data key. + * highest_data_key - get the highest possible data key for an inode. * @c: UBIFS file-system description object - * @k: key to initialize + * @key: key to initialize * @inum: inode number - * @block: block number */ -static inline void data_key_init_flash(const struct ubifs_info *c, void *k, - ino_t inum, unsigned int block) +static inline void highest_data_key(const struct ubifs_info *c, + union ubifs_key *key, ino_t inum) { - union ubifs_key *key = k; - - ubifs_assert(!(block & ~UBIFS_S_KEY_BLOCK_MASK)); - key->j32[0] = cpu_to_le32(inum); - key->j32[1] = cpu_to_le32(block | - (UBIFS_DATA_KEY << UBIFS_S_KEY_BLOCK_BITS)); - memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8); + data_key_init(c, key, inum, UBIFS_S_KEY_BLOCK_MASK); } /** @@ -329,6 +294,20 @@ static inline void trun_key_init(const struct ubifs_info *c, key->u32[1] = UBIFS_TRUN_KEY << UBIFS_S_KEY_BLOCK_BITS; } +/** + * invalid_key_init - initialize invalid node key. + * @c: UBIFS file-system description object + * @key: key to initialize + * + * This is a helper function which marks a @key object as invalid. + */ +static inline void invalid_key_init(const struct ubifs_info *c, + union ubifs_key *key) +{ + key->u32[0] = 0xDEADBEAF; + key->u32[1] = UBIFS_INVALID_KEY; +} + /** * key_type - get key type. * @c: UBIFS file-system description object @@ -381,8 +360,8 @@ static inline ino_t key_inum_flash(const struct ubifs_info *c, const void *k) * @c: UBIFS file-system description object * @key: the key to get hash from */ -static inline int key_hash(const struct ubifs_info *c, - const union ubifs_key *key) +static inline uint32_t key_hash(const struct ubifs_info *c, + const union ubifs_key *key) { return key->u32[1] & UBIFS_S_KEY_HASH_MASK; } @@ -392,7 +371,7 @@ static inline int key_hash(const struct ubifs_info *c, * @c: UBIFS file-system description object * @k: the key to get hash from */ -static inline int key_hash_flash(const struct ubifs_info *c, const void *k) +static inline uint32_t key_hash_flash(const struct ubifs_info *c, const void *k) { const union ubifs_key *key = k; @@ -554,4 +533,5 @@ static inline unsigned long long key_max_inode_size(const struct ubifs_info *c) return 0; } } + #endif /* !__UBIFS_KEY_H__ */ diff --git a/fs/ubifs/log.c b/fs/ubifs/log.c index 68a9bd98f8..0355fe2b04 100644 --- a/fs/ubifs/log.c +++ b/fs/ubifs/log.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -27,8 +16,13 @@ * journal. */ +#ifdef __UBOOT__ +#include +#endif #include "ubifs.h" +static int dbg_check_bud_bytes(struct ubifs_info *c); + /** * ubifs_search_bud - search bud LEB. * @c: UBIFS file-system description object @@ -59,6 +53,57 @@ struct ubifs_bud *ubifs_search_bud(struct ubifs_info *c, int lnum) return NULL; } +/** + * ubifs_get_wbuf - get the wbuf associated with a LEB, if there is one. + * @c: UBIFS file-system description object + * @lnum: logical eraseblock number to search + * + * This functions returns the wbuf for @lnum or %NULL if there is not one. + */ +struct ubifs_wbuf *ubifs_get_wbuf(struct ubifs_info *c, int lnum) +{ + struct rb_node *p; + struct ubifs_bud *bud; + int jhead; + + if (!c->jheads) + return NULL; + + spin_lock(&c->buds_lock); + p = c->buds.rb_node; + while (p) { + bud = rb_entry(p, struct ubifs_bud, rb); + if (lnum < bud->lnum) + p = p->rb_left; + else if (lnum > bud->lnum) + p = p->rb_right; + else { + jhead = bud->jhead; + spin_unlock(&c->buds_lock); + return &c->jheads[jhead].wbuf; + } + } + spin_unlock(&c->buds_lock); + return NULL; +} + +/** + * empty_log_bytes - calculate amount of empty space in the log. + * @c: UBIFS file-system description object + */ +static inline long long empty_log_bytes(const struct ubifs_info *c) +{ + long long h, t; + + h = (long long)c->lhead_lnum * c->leb_size + c->lhead_offs; + t = (long long)c->ltail_lnum * c->leb_size; + + if (h >= t) + return c->log_bytes - h + t; + else + return t - h; +} + /** * ubifs_add_bud - add bud LEB to the tree of buds and its journal head list. * @c: UBIFS file-system description object @@ -88,7 +133,7 @@ void ubifs_add_bud(struct ubifs_info *c, struct ubifs_bud *bud) jhead = &c->jheads[bud->jhead]; list_add_tail(&bud->list, &jhead->buds_list); } else - ubifs_assert(c->replaying && (c->vfs_sb->s_flags & MS_RDONLY)); + ubifs_assert(c->replaying && c->ro_mount); /* * Note, although this is a new bud, we anyway account this space now, @@ -98,7 +143,594 @@ void ubifs_add_bud(struct ubifs_info *c, struct ubifs_bud *bud) */ c->bud_bytes += c->leb_size - bud->start; - dbg_log("LEB %d:%d, jhead %d, bud_bytes %lld", bud->lnum, - bud->start, bud->jhead, c->bud_bytes); + dbg_log("LEB %d:%d, jhead %s, bud_bytes %lld", bud->lnum, + bud->start, dbg_jhead(bud->jhead), c->bud_bytes); + spin_unlock(&c->buds_lock); +} + +/** + * ubifs_add_bud_to_log - add a new bud to the log. + * @c: UBIFS file-system description object + * @jhead: journal head the bud belongs to + * @lnum: LEB number of the bud + * @offs: starting offset of the bud + * + * This function writes reference node for the new bud LEB @lnum it to the log, + * and adds it to the buds tress. It also makes sure that log size does not + * exceed the 'c->max_bud_bytes' limit. Returns zero in case of success, + * %-EAGAIN if commit is required, and a negative error codes in case of + * failure. + */ +int ubifs_add_bud_to_log(struct ubifs_info *c, int jhead, int lnum, int offs) +{ + int err; + struct ubifs_bud *bud; + struct ubifs_ref_node *ref; + + bud = kmalloc(sizeof(struct ubifs_bud), GFP_NOFS); + if (!bud) + return -ENOMEM; + ref = kzalloc(c->ref_node_alsz, GFP_NOFS); + if (!ref) { + kfree(bud); + return -ENOMEM; + } + + mutex_lock(&c->log_mutex); + ubifs_assert(!c->ro_media && !c->ro_mount); + if (c->ro_error) { + err = -EROFS; + goto out_unlock; + } + + /* Make sure we have enough space in the log */ + if (empty_log_bytes(c) - c->ref_node_alsz < c->min_log_bytes) { + dbg_log("not enough log space - %lld, required %d", + empty_log_bytes(c), c->min_log_bytes); + ubifs_commit_required(c); + err = -EAGAIN; + goto out_unlock; + } + + /* + * Make sure the amount of space in buds will not exceed the + * 'c->max_bud_bytes' limit, because we want to guarantee mount time + * limits. + * + * It is not necessary to hold @c->buds_lock when reading @c->bud_bytes + * because we are holding @c->log_mutex. All @c->bud_bytes take place + * when both @c->log_mutex and @c->bud_bytes are locked. + */ + if (c->bud_bytes + c->leb_size - offs > c->max_bud_bytes) { + dbg_log("bud bytes %lld (%lld max), require commit", + c->bud_bytes, c->max_bud_bytes); + ubifs_commit_required(c); + err = -EAGAIN; + goto out_unlock; + } + + /* + * If the journal is full enough - start background commit. Note, it is + * OK to read 'c->cmt_state' without spinlock because integer reads + * are atomic in the kernel. + */ + if (c->bud_bytes >= c->bg_bud_bytes && + c->cmt_state == COMMIT_RESTING) { + dbg_log("bud bytes %lld (%lld max), initiate BG commit", + c->bud_bytes, c->max_bud_bytes); + ubifs_request_bg_commit(c); + } + + bud->lnum = lnum; + bud->start = offs; + bud->jhead = jhead; + + ref->ch.node_type = UBIFS_REF_NODE; + ref->lnum = cpu_to_le32(bud->lnum); + ref->offs = cpu_to_le32(bud->start); + ref->jhead = cpu_to_le32(jhead); + + if (c->lhead_offs > c->leb_size - c->ref_node_alsz) { + c->lhead_lnum = ubifs_next_log_lnum(c, c->lhead_lnum); + c->lhead_offs = 0; + } + + if (c->lhead_offs == 0) { + /* Must ensure next log LEB has been unmapped */ + err = ubifs_leb_unmap(c, c->lhead_lnum); + if (err) + goto out_unlock; + } + + if (bud->start == 0) { + /* + * Before writing the LEB reference which refers an empty LEB + * to the log, we have to make sure it is mapped, because + * otherwise we'd risk to refer an LEB with garbage in case of + * an unclean reboot, because the target LEB might have been + * unmapped, but not yet physically erased. + */ + err = ubifs_leb_map(c, bud->lnum); + if (err) + goto out_unlock; + } + + dbg_log("write ref LEB %d:%d", + c->lhead_lnum, c->lhead_offs); + err = ubifs_write_node(c, ref, UBIFS_REF_NODE_SZ, c->lhead_lnum, + c->lhead_offs); + if (err) + goto out_unlock; + + c->lhead_offs += c->ref_node_alsz; + + ubifs_add_bud(c, bud); + + mutex_unlock(&c->log_mutex); + kfree(ref); + return 0; + +out_unlock: + mutex_unlock(&c->log_mutex); + kfree(ref); + kfree(bud); + return err; +} + +/** + * remove_buds - remove used buds. + * @c: UBIFS file-system description object + * + * This function removes use buds from the buds tree. It does not remove the + * buds which are pointed to by journal heads. + */ +static void remove_buds(struct ubifs_info *c) +{ + struct rb_node *p; + + ubifs_assert(list_empty(&c->old_buds)); + c->cmt_bud_bytes = 0; + spin_lock(&c->buds_lock); + p = rb_first(&c->buds); + while (p) { + struct rb_node *p1 = p; + struct ubifs_bud *bud; + struct ubifs_wbuf *wbuf; + + p = rb_next(p); + bud = rb_entry(p1, struct ubifs_bud, rb); + wbuf = &c->jheads[bud->jhead].wbuf; + + if (wbuf->lnum == bud->lnum) { + /* + * Do not remove buds which are pointed to by journal + * heads (non-closed buds). + */ + c->cmt_bud_bytes += wbuf->offs - bud->start; + dbg_log("preserve %d:%d, jhead %s, bud bytes %d, cmt_bud_bytes %lld", + bud->lnum, bud->start, dbg_jhead(bud->jhead), + wbuf->offs - bud->start, c->cmt_bud_bytes); + bud->start = wbuf->offs; + } else { + c->cmt_bud_bytes += c->leb_size - bud->start; + dbg_log("remove %d:%d, jhead %s, bud bytes %d, cmt_bud_bytes %lld", + bud->lnum, bud->start, dbg_jhead(bud->jhead), + c->leb_size - bud->start, c->cmt_bud_bytes); + rb_erase(p1, &c->buds); + /* + * If the commit does not finish, the recovery will need + * to replay the journal, in which case the old buds + * must be unchanged. Do not release them until post + * commit i.e. do not allow them to be garbage + * collected. + */ + list_move(&bud->list, &c->old_buds); + } + } + spin_unlock(&c->buds_lock); +} + +/** + * ubifs_log_start_commit - start commit. + * @c: UBIFS file-system description object + * @ltail_lnum: return new log tail LEB number + * + * The commit operation starts with writing "commit start" node to the log and + * reference nodes for all journal heads which will define new journal after + * the commit has been finished. The commit start and reference nodes are + * written in one go to the nearest empty log LEB (hence, when commit is + * finished UBIFS may safely unmap all the previous log LEBs). This function + * returns zero in case of success and a negative error code in case of + * failure. + */ +int ubifs_log_start_commit(struct ubifs_info *c, int *ltail_lnum) +{ + void *buf; + struct ubifs_cs_node *cs; + struct ubifs_ref_node *ref; + int err, i, max_len, len; + + err = dbg_check_bud_bytes(c); + if (err) + return err; + + max_len = UBIFS_CS_NODE_SZ + c->jhead_cnt * UBIFS_REF_NODE_SZ; + max_len = ALIGN(max_len, c->min_io_size); + buf = cs = kmalloc(max_len, GFP_NOFS); + if (!buf) + return -ENOMEM; + + cs->ch.node_type = UBIFS_CS_NODE; + cs->cmt_no = cpu_to_le64(c->cmt_no); + ubifs_prepare_node(c, cs, UBIFS_CS_NODE_SZ, 0); + + /* + * Note, we do not lock 'c->log_mutex' because this is the commit start + * phase and we are exclusively using the log. And we do not lock + * write-buffer because nobody can write to the file-system at this + * phase. + */ + + len = UBIFS_CS_NODE_SZ; + for (i = 0; i < c->jhead_cnt; i++) { + int lnum = c->jheads[i].wbuf.lnum; + int offs = c->jheads[i].wbuf.offs; + + if (lnum == -1 || offs == c->leb_size) + continue; + + dbg_log("add ref to LEB %d:%d for jhead %s", + lnum, offs, dbg_jhead(i)); + ref = buf + len; + ref->ch.node_type = UBIFS_REF_NODE; + ref->lnum = cpu_to_le32(lnum); + ref->offs = cpu_to_le32(offs); + ref->jhead = cpu_to_le32(i); + + ubifs_prepare_node(c, ref, UBIFS_REF_NODE_SZ, 0); + len += UBIFS_REF_NODE_SZ; + } + + ubifs_pad(c, buf + len, ALIGN(len, c->min_io_size) - len); + + /* Switch to the next log LEB */ + if (c->lhead_offs) { + c->lhead_lnum = ubifs_next_log_lnum(c, c->lhead_lnum); + c->lhead_offs = 0; + } + + if (c->lhead_offs == 0) { + /* Must ensure next LEB has been unmapped */ + err = ubifs_leb_unmap(c, c->lhead_lnum); + if (err) + goto out; + } + + len = ALIGN(len, c->min_io_size); + dbg_log("writing commit start at LEB %d:0, len %d", c->lhead_lnum, len); + err = ubifs_leb_write(c, c->lhead_lnum, cs, 0, len); + if (err) + goto out; + + *ltail_lnum = c->lhead_lnum; + + c->lhead_offs += len; + if (c->lhead_offs == c->leb_size) { + c->lhead_lnum = ubifs_next_log_lnum(c, c->lhead_lnum); + c->lhead_offs = 0; + } + + remove_buds(c); + + /* + * We have started the commit and now users may use the rest of the log + * for new writes. + */ + c->min_log_bytes = 0; + +out: + kfree(buf); + return err; +} + +/** + * ubifs_log_end_commit - end commit. + * @c: UBIFS file-system description object + * @ltail_lnum: new log tail LEB number + * + * This function is called on when the commit operation was finished. It + * moves log tail to new position and unmaps LEBs which contain obsolete data. + * Returns zero in case of success and a negative error code in case of + * failure. + */ +int ubifs_log_end_commit(struct ubifs_info *c, int ltail_lnum) +{ + int err; + + /* + * At this phase we have to lock 'c->log_mutex' because UBIFS allows FS + * writes during commit. Its only short "commit" start phase when + * writers are blocked. + */ + mutex_lock(&c->log_mutex); + + dbg_log("old tail was LEB %d:0, new tail is LEB %d:0", + c->ltail_lnum, ltail_lnum); + + c->ltail_lnum = ltail_lnum; + /* + * The commit is finished and from now on it must be guaranteed that + * there is always enough space for the next commit. + */ + c->min_log_bytes = c->leb_size; + + spin_lock(&c->buds_lock); + c->bud_bytes -= c->cmt_bud_bytes; + spin_unlock(&c->buds_lock); + + err = dbg_check_bud_bytes(c); + + mutex_unlock(&c->log_mutex); + return err; +} + +/** + * ubifs_log_post_commit - things to do after commit is completed. + * @c: UBIFS file-system description object + * @old_ltail_lnum: old log tail LEB number + * + * Release buds only after commit is completed, because they must be unchanged + * if recovery is needed. + * + * Unmap log LEBs only after commit is completed, because they may be needed for + * recovery. + * + * This function returns %0 on success and a negative error code on failure. + */ +int ubifs_log_post_commit(struct ubifs_info *c, int old_ltail_lnum) +{ + int lnum, err = 0; + + while (!list_empty(&c->old_buds)) { + struct ubifs_bud *bud; + + bud = list_entry(c->old_buds.next, struct ubifs_bud, list); + err = ubifs_return_leb(c, bud->lnum); + if (err) + return err; + list_del(&bud->list); + kfree(bud); + } + mutex_lock(&c->log_mutex); + for (lnum = old_ltail_lnum; lnum != c->ltail_lnum; + lnum = ubifs_next_log_lnum(c, lnum)) { + dbg_log("unmap log LEB %d", lnum); + err = ubifs_leb_unmap(c, lnum); + if (err) + goto out; + } +out: + mutex_unlock(&c->log_mutex); + return err; +} + +/** + * struct done_ref - references that have been done. + * @rb: rb-tree node + * @lnum: LEB number + */ +struct done_ref { + struct rb_node rb; + int lnum; +}; + +/** + * done_already - determine if a reference has been done already. + * @done_tree: rb-tree to store references that have been done + * @lnum: LEB number of reference + * + * This function returns %1 if the reference has been done, %0 if not, otherwise + * a negative error code is returned. + */ +static int done_already(struct rb_root *done_tree, int lnum) +{ + struct rb_node **p = &done_tree->rb_node, *parent = NULL; + struct done_ref *dr; + + while (*p) { + parent = *p; + dr = rb_entry(parent, struct done_ref, rb); + if (lnum < dr->lnum) + p = &(*p)->rb_left; + else if (lnum > dr->lnum) + p = &(*p)->rb_right; + else + return 1; + } + + dr = kzalloc(sizeof(struct done_ref), GFP_NOFS); + if (!dr) + return -ENOMEM; + + dr->lnum = lnum; + + rb_link_node(&dr->rb, parent, p); + rb_insert_color(&dr->rb, done_tree); + + return 0; +} + +/** + * destroy_done_tree - destroy the done tree. + * @done_tree: done tree to destroy + */ +static void destroy_done_tree(struct rb_root *done_tree) +{ + struct done_ref *dr, *n; + + rbtree_postorder_for_each_entry_safe(dr, n, done_tree, rb) + kfree(dr); +} + +/** + * add_node - add a node to the consolidated log. + * @c: UBIFS file-system description object + * @buf: buffer to which to add + * @lnum: LEB number to which to write is passed and returned here + * @offs: offset to where to write is passed and returned here + * @node: node to add + * + * This function returns %0 on success and a negative error code on failure. + */ +static int add_node(struct ubifs_info *c, void *buf, int *lnum, int *offs, + void *node) +{ + struct ubifs_ch *ch = node; + int len = le32_to_cpu(ch->len), remains = c->leb_size - *offs; + + if (len > remains) { + int sz = ALIGN(*offs, c->min_io_size), err; + + ubifs_pad(c, buf + *offs, sz - *offs); + err = ubifs_leb_change(c, *lnum, buf, sz); + if (err) + return err; + *lnum = ubifs_next_log_lnum(c, *lnum); + *offs = 0; + } + memcpy(buf + *offs, node, len); + *offs += ALIGN(len, 8); + return 0; +} + +/** + * ubifs_consolidate_log - consolidate the log. + * @c: UBIFS file-system description object + * + * Repeated failed commits could cause the log to be full, but at least 1 LEB is + * needed for commit. This function rewrites the reference nodes in the log + * omitting duplicates, and failed CS nodes, and leaving no gaps. + * + * This function returns %0 on success and a negative error code on failure. + */ +int ubifs_consolidate_log(struct ubifs_info *c) +{ + struct ubifs_scan_leb *sleb; + struct ubifs_scan_node *snod; + struct rb_root done_tree = RB_ROOT; + int lnum, err, first = 1, write_lnum, offs = 0; + void *buf; + + dbg_rcvry("log tail LEB %d, log head LEB %d", c->ltail_lnum, + c->lhead_lnum); + buf = vmalloc(c->leb_size); + if (!buf) + return -ENOMEM; + lnum = c->ltail_lnum; + write_lnum = lnum; + while (1) { + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 0); + if (IS_ERR(sleb)) { + err = PTR_ERR(sleb); + goto out_free; + } + list_for_each_entry(snod, &sleb->nodes, list) { + switch (snod->type) { + case UBIFS_REF_NODE: { + struct ubifs_ref_node *ref = snod->node; + int ref_lnum = le32_to_cpu(ref->lnum); + + err = done_already(&done_tree, ref_lnum); + if (err < 0) + goto out_scan; + if (err != 1) { + err = add_node(c, buf, &write_lnum, + &offs, snod->node); + if (err) + goto out_scan; + } + break; + } + case UBIFS_CS_NODE: + if (!first) + break; + err = add_node(c, buf, &write_lnum, &offs, + snod->node); + if (err) + goto out_scan; + first = 0; + break; + } + } + ubifs_scan_destroy(sleb); + if (lnum == c->lhead_lnum) + break; + lnum = ubifs_next_log_lnum(c, lnum); + } + if (offs) { + int sz = ALIGN(offs, c->min_io_size); + + ubifs_pad(c, buf + offs, sz - offs); + err = ubifs_leb_change(c, write_lnum, buf, sz); + if (err) + goto out_free; + offs = ALIGN(offs, c->min_io_size); + } + destroy_done_tree(&done_tree); + vfree(buf); + if (write_lnum == c->lhead_lnum) { + ubifs_err("log is too full"); + return -EINVAL; + } + /* Unmap remaining LEBs */ + lnum = write_lnum; + do { + lnum = ubifs_next_log_lnum(c, lnum); + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + } while (lnum != c->lhead_lnum); + c->lhead_lnum = write_lnum; + c->lhead_offs = offs; + dbg_rcvry("new log head at %d:%d", c->lhead_lnum, c->lhead_offs); + return 0; + +out_scan: + ubifs_scan_destroy(sleb); +out_free: + destroy_done_tree(&done_tree); + vfree(buf); + return err; +} + +/** + * dbg_check_bud_bytes - make sure bud bytes calculation are all right. + * @c: UBIFS file-system description object + * + * This function makes sure the amount of flash space used by closed buds + * ('c->bud_bytes' is correct). Returns zero in case of success and %-EINVAL in + * case of failure. + */ +static int dbg_check_bud_bytes(struct ubifs_info *c) +{ + int i, err = 0; + struct ubifs_bud *bud; + long long bud_bytes = 0; + + if (!dbg_is_chk_gen(c)) + return 0; + + spin_lock(&c->buds_lock); + for (i = 0; i < c->jhead_cnt; i++) + list_for_each_entry(bud, &c->jheads[i].buds_list, list) + bud_bytes += c->leb_size - bud->start; + + if (c->bud_bytes != bud_bytes) { + ubifs_err("bad bud_bytes %lld, calculated %lld", + c->bud_bytes, bud_bytes); + err = -EINVAL; + } spin_unlock(&c->buds_lock); + + return err; } diff --git a/fs/ubifs/lprops.c b/fs/ubifs/lprops.c index 8ce4949fcf..a1a814f779 100644 --- a/fs/ubifs/lprops.c +++ b/fs/ubifs/lprops.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Adrian Hunter * Artem Bityutskiy (Битюцкий Артём) @@ -28,6 +17,9 @@ * an empty LEB for the journal, or a very dirty LEB for garbage collection. */ +#ifdef __UBOOT__ +#include +#endif #include "ubifs.h" /** @@ -281,7 +273,7 @@ void ubifs_add_to_cat(struct ubifs_info *c, struct ubifs_lprops *lprops, case LPROPS_FREE: if (add_to_lpt_heap(c, lprops, cat)) break; - /* No more room on heap so make it uncategorized */ + /* No more room on heap so make it un-categorized */ cat = LPROPS_UNCAT; /* Fall through */ case LPROPS_UNCAT: @@ -300,8 +292,11 @@ void ubifs_add_to_cat(struct ubifs_info *c, struct ubifs_lprops *lprops, default: ubifs_assert(0); } + lprops->flags &= ~LPROPS_CAT_MASK; lprops->flags |= cat; + c->in_a_category_cnt += 1; + ubifs_assert(c->in_a_category_cnt <= c->main_lebs); } /** @@ -334,6 +329,9 @@ static void ubifs_remove_from_cat(struct ubifs_info *c, default: ubifs_assert(0); } + + c->in_a_category_cnt -= 1; + ubifs_assert(c->in_a_category_cnt >= 0); } /** @@ -375,8 +373,8 @@ void ubifs_replace_cat(struct ubifs_info *c, struct ubifs_lprops *old_lprops, * @lprops: LEB properties * * A LEB may have fallen off of the bottom of a heap, and ended up as - * uncategorized even though it has enough space for us now. If that is the case - * this function will put the LEB back onto a heap. + * un-categorized even though it has enough space for us now. If that is the + * case this function will put the LEB back onto a heap. */ void ubifs_ensure_cat(struct ubifs_info *c, struct ubifs_lprops *lprops) { @@ -436,10 +434,10 @@ int ubifs_categorize_lprops(const struct ubifs_info *c, /** * change_category - change LEB properties category. * @c: UBIFS file-system description object - * @lprops: LEB properties to recategorize + * @lprops: LEB properties to re-categorize * * LEB properties are categorized to enable fast find operations. When the LEB - * properties change they must be recategorized. + * properties change they must be re-categorized. */ static void change_category(struct ubifs_info *c, struct ubifs_lprops *lprops) { @@ -447,7 +445,7 @@ static void change_category(struct ubifs_info *c, struct ubifs_lprops *lprops) int new_cat = ubifs_categorize_lprops(c, lprops); if (old_cat == new_cat) { - struct ubifs_lpt_heap *heap = &c->lpt_heap[new_cat - 1]; + struct ubifs_lpt_heap *heap; /* lprops on a heap now must be moved up or down */ if (new_cat < 1 || new_cat > LPROPS_HEAP_CNT) @@ -461,21 +459,18 @@ static void change_category(struct ubifs_info *c, struct ubifs_lprops *lprops) } /** - * calc_dark - calculate LEB dark space size. + * ubifs_calc_dark - calculate LEB dark space size. * @c: the UBIFS file-system description object * @spc: amount of free and dirty space in the LEB * - * This function calculates amount of dark space in an LEB which has @spc bytes - * of free and dirty space. Returns the calculations result. + * This function calculates and returns amount of dark space in an LEB which + * has @spc bytes of free and dirty space. * - * Dark space is the space which is not always usable - it depends on which - * nodes are written in which order. E.g., if an LEB has only 512 free bytes, - * it is dark space, because it cannot fit a large data node. So UBIFS cannot - * count on this LEB and treat these 512 bytes as usable because it is not true - * if, for example, only big chunks of uncompressible data will be written to - * the FS. + * UBIFS is trying to account the space which might not be usable, and this + * space is called "dark space". For example, if an LEB has only %512 free + * bytes, it is dark space, because it cannot fit a large data node. */ -static int calc_dark(struct ubifs_info *c, int spc) +int ubifs_calc_dark(const struct ubifs_info *c, int spc) { ubifs_assert(!(spc & 7)); @@ -507,7 +502,7 @@ static int is_lprops_dirty(struct ubifs_info *c, struct ubifs_lprops *lprops) pnode = (struct ubifs_pnode *)container_of(lprops - pos, struct ubifs_pnode, lprops[0]); - return !test_bit(COW_ZNODE, &pnode->flags) && + return !test_bit(COW_CNODE, &pnode->flags) && test_bit(DIRTY_CNODE, &pnode->flags); } @@ -518,7 +513,7 @@ static int is_lprops_dirty(struct ubifs_info *c, struct ubifs_lprops *lprops) * @free: new free space amount * @dirty: new dirty space amount * @flags: new flags - * @idx_gc_cnt: change to the count of idx_gc list + * @idx_gc_cnt: change to the count of @idx_gc list * * This function changes LEB properties (@free, @dirty or @flag). However, the * property which has the %LPROPS_NC value is not changed. Returns a pointer to @@ -535,7 +530,7 @@ const struct ubifs_lprops *ubifs_change_lp(struct ubifs_info *c, { /* * This is the only function that is allowed to change lprops, so we - * discard the const qualifier. + * discard the "const" qualifier. */ struct ubifs_lprops *lprops = (struct ubifs_lprops *)lp; @@ -575,7 +570,7 @@ const struct ubifs_lprops *ubifs_change_lp(struct ubifs_info *c, if (old_spc < c->dead_wm) c->lst.total_dead -= old_spc; else - c->lst.total_dark -= calc_dark(c, old_spc); + c->lst.total_dark -= ubifs_calc_dark(c, old_spc); c->lst.total_used -= c->leb_size - old_spc; } @@ -616,7 +611,7 @@ const struct ubifs_lprops *ubifs_change_lp(struct ubifs_info *c, if (new_spc < c->dead_wm) c->lst.total_dead += new_spc; else - c->lst.total_dark += calc_dark(c, new_spc); + c->lst.total_dark += ubifs_calc_dark(c, new_spc); c->lst.total_used += c->leb_size - new_spc; } @@ -678,6 +673,9 @@ int ubifs_change_one_lp(struct ubifs_info *c, int lnum, int free, int dirty, out: ubifs_release_lprops(c); + if (err) + ubifs_err("cannot change properties of LEB %d, error %d", + lnum, err); return err; } @@ -714,6 +712,9 @@ int ubifs_update_one_lp(struct ubifs_info *c, int lnum, int free, int dirty, out: ubifs_release_lprops(c); + if (err) + ubifs_err("cannot update properties of LEB %d, error %d", + lnum, err); return err; } @@ -737,6 +738,8 @@ int ubifs_read_one_lp(struct ubifs_info *c, int lnum, struct ubifs_lprops *lp) lpp = ubifs_lpt_lookup(c, lnum); if (IS_ERR(lpp)) { err = PTR_ERR(lpp); + ubifs_err("cannot read properties of LEB %d, error %d", + lnum, err); goto out; } @@ -840,3 +843,471 @@ const struct ubifs_lprops *ubifs_fast_find_frdi_idx(struct ubifs_info *c) ubifs_assert(lprops->free + lprops->dirty == c->leb_size); return lprops; } + +/* + * Everything below is related to debugging. + */ + +/** + * dbg_check_cats - check category heaps and lists. + * @c: UBIFS file-system description object + * + * This function returns %0 on success and a negative error code on failure. + */ +int dbg_check_cats(struct ubifs_info *c) +{ + struct ubifs_lprops *lprops; + struct list_head *pos; + int i, cat; + + if (!dbg_is_chk_gen(c) && !dbg_is_chk_lprops(c)) + return 0; + + list_for_each_entry(lprops, &c->empty_list, list) { + if (lprops->free != c->leb_size) { + ubifs_err("non-empty LEB %d on empty list (free %d dirty %d flags %d)", + lprops->lnum, lprops->free, lprops->dirty, + lprops->flags); + return -EINVAL; + } + if (lprops->flags & LPROPS_TAKEN) { + ubifs_err("taken LEB %d on empty list (free %d dirty %d flags %d)", + lprops->lnum, lprops->free, lprops->dirty, + lprops->flags); + return -EINVAL; + } + } + + i = 0; + list_for_each_entry(lprops, &c->freeable_list, list) { + if (lprops->free + lprops->dirty != c->leb_size) { + ubifs_err("non-freeable LEB %d on freeable list (free %d dirty %d flags %d)", + lprops->lnum, lprops->free, lprops->dirty, + lprops->flags); + return -EINVAL; + } + if (lprops->flags & LPROPS_TAKEN) { + ubifs_err("taken LEB %d on freeable list (free %d dirty %d flags %d)", + lprops->lnum, lprops->free, lprops->dirty, + lprops->flags); + return -EINVAL; + } + i += 1; + } + if (i != c->freeable_cnt) { + ubifs_err("freeable list count %d expected %d", i, + c->freeable_cnt); + return -EINVAL; + } + + i = 0; + list_for_each(pos, &c->idx_gc) + i += 1; + if (i != c->idx_gc_cnt) { + ubifs_err("idx_gc list count %d expected %d", i, + c->idx_gc_cnt); + return -EINVAL; + } + + list_for_each_entry(lprops, &c->frdi_idx_list, list) { + if (lprops->free + lprops->dirty != c->leb_size) { + ubifs_err("non-freeable LEB %d on frdi_idx list (free %d dirty %d flags %d)", + lprops->lnum, lprops->free, lprops->dirty, + lprops->flags); + return -EINVAL; + } + if (lprops->flags & LPROPS_TAKEN) { + ubifs_err("taken LEB %d on frdi_idx list (free %d dirty %d flags %d)", + lprops->lnum, lprops->free, lprops->dirty, + lprops->flags); + return -EINVAL; + } + if (!(lprops->flags & LPROPS_INDEX)) { + ubifs_err("non-index LEB %d on frdi_idx list (free %d dirty %d flags %d)", + lprops->lnum, lprops->free, lprops->dirty, + lprops->flags); + return -EINVAL; + } + } + + for (cat = 1; cat <= LPROPS_HEAP_CNT; cat++) { + struct ubifs_lpt_heap *heap = &c->lpt_heap[cat - 1]; + + for (i = 0; i < heap->cnt; i++) { + lprops = heap->arr[i]; + if (!lprops) { + ubifs_err("null ptr in LPT heap cat %d", cat); + return -EINVAL; + } + if (lprops->hpos != i) { + ubifs_err("bad ptr in LPT heap cat %d", cat); + return -EINVAL; + } + if (lprops->flags & LPROPS_TAKEN) { + ubifs_err("taken LEB in LPT heap cat %d", cat); + return -EINVAL; + } + } + } + + return 0; +} + +void dbg_check_heap(struct ubifs_info *c, struct ubifs_lpt_heap *heap, int cat, + int add_pos) +{ + int i = 0, j, err = 0; + + if (!dbg_is_chk_gen(c) && !dbg_is_chk_lprops(c)) + return; + + for (i = 0; i < heap->cnt; i++) { + struct ubifs_lprops *lprops = heap->arr[i]; + struct ubifs_lprops *lp; + + if (i != add_pos) + if ((lprops->flags & LPROPS_CAT_MASK) != cat) { + err = 1; + goto out; + } + if (lprops->hpos != i) { + err = 2; + goto out; + } + lp = ubifs_lpt_lookup(c, lprops->lnum); + if (IS_ERR(lp)) { + err = 3; + goto out; + } + if (lprops != lp) { + ubifs_err("lprops %zx lp %zx lprops->lnum %d lp->lnum %d", + (size_t)lprops, (size_t)lp, lprops->lnum, + lp->lnum); + err = 4; + goto out; + } + for (j = 0; j < i; j++) { + lp = heap->arr[j]; + if (lp == lprops) { + err = 5; + goto out; + } + if (lp->lnum == lprops->lnum) { + err = 6; + goto out; + } + } + } +out: + if (err) { + ubifs_err("failed cat %d hpos %d err %d", cat, i, err); + dump_stack(); + ubifs_dump_heap(c, heap, cat); + } +} + +/** + * scan_check_cb - scan callback. + * @c: the UBIFS file-system description object + * @lp: LEB properties to scan + * @in_tree: whether the LEB properties are in main memory + * @lst: lprops statistics to update + * + * This function returns a code that indicates whether the scan should continue + * (%LPT_SCAN_CONTINUE), whether the LEB properties should be added to the tree + * in main memory (%LPT_SCAN_ADD), or whether the scan should stop + * (%LPT_SCAN_STOP). + */ +static int scan_check_cb(struct ubifs_info *c, + const struct ubifs_lprops *lp, int in_tree, + struct ubifs_lp_stats *lst) +{ + struct ubifs_scan_leb *sleb; + struct ubifs_scan_node *snod; + int cat, lnum = lp->lnum, is_idx = 0, used = 0, freef, dirty, ret; + void *buf = NULL; + + cat = lp->flags & LPROPS_CAT_MASK; + if (cat != LPROPS_UNCAT) { + cat = ubifs_categorize_lprops(c, lp); + if (cat != (lp->flags & LPROPS_CAT_MASK)) { + ubifs_err("bad LEB category %d expected %d", + (lp->flags & LPROPS_CAT_MASK), cat); + return -EINVAL; + } + } + + /* Check lp is on its category list (if it has one) */ + if (in_tree) { + struct list_head *list = NULL; + + switch (cat) { + case LPROPS_EMPTY: + list = &c->empty_list; + break; + case LPROPS_FREEABLE: + list = &c->freeable_list; + break; + case LPROPS_FRDI_IDX: + list = &c->frdi_idx_list; + break; + case LPROPS_UNCAT: + list = &c->uncat_list; + break; + } + if (list) { + struct ubifs_lprops *lprops; + int found = 0; + + list_for_each_entry(lprops, list, list) { + if (lprops == lp) { + found = 1; + break; + } + } + if (!found) { + ubifs_err("bad LPT list (category %d)", cat); + return -EINVAL; + } + } + } + + /* Check lp is on its category heap (if it has one) */ + if (in_tree && cat > 0 && cat <= LPROPS_HEAP_CNT) { + struct ubifs_lpt_heap *heap = &c->lpt_heap[cat - 1]; + + if ((lp->hpos != -1 && heap->arr[lp->hpos]->lnum != lnum) || + lp != heap->arr[lp->hpos]) { + ubifs_err("bad LPT heap (category %d)", cat); + return -EINVAL; + } + } + + buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); + if (!buf) + return -ENOMEM; + + /* + * After an unclean unmount, empty and freeable LEBs + * may contain garbage - do not scan them. + */ + if (lp->free == c->leb_size) { + lst->empty_lebs += 1; + lst->total_free += c->leb_size; + lst->total_dark += ubifs_calc_dark(c, c->leb_size); + return LPT_SCAN_CONTINUE; + } + if (lp->free + lp->dirty == c->leb_size && + !(lp->flags & LPROPS_INDEX)) { + lst->total_free += lp->free; + lst->total_dirty += lp->dirty; + lst->total_dark += ubifs_calc_dark(c, c->leb_size); + return LPT_SCAN_CONTINUE; + } + + sleb = ubifs_scan(c, lnum, 0, buf, 0); + if (IS_ERR(sleb)) { + ret = PTR_ERR(sleb); + if (ret == -EUCLEAN) { + ubifs_dump_lprops(c); + ubifs_dump_budg(c, &c->bi); + } + goto out; + } + + is_idx = -1; + list_for_each_entry(snod, &sleb->nodes, list) { + int found, level = 0; + + cond_resched(); + + if (is_idx == -1) + is_idx = (snod->type == UBIFS_IDX_NODE) ? 1 : 0; + + if (is_idx && snod->type != UBIFS_IDX_NODE) { + ubifs_err("indexing node in data LEB %d:%d", + lnum, snod->offs); + goto out_destroy; + } + + if (snod->type == UBIFS_IDX_NODE) { + struct ubifs_idx_node *idx = snod->node; + + key_read(c, ubifs_idx_key(c, idx), &snod->key); + level = le16_to_cpu(idx->level); + } + + found = ubifs_tnc_has_node(c, &snod->key, level, lnum, + snod->offs, is_idx); + if (found) { + if (found < 0) + goto out_destroy; + used += ALIGN(snod->len, 8); + } + } + + freef = c->leb_size - sleb->endpt; + dirty = sleb->endpt - used; + + if (freef > c->leb_size || freef < 0 || dirty > c->leb_size || + dirty < 0) { + ubifs_err("bad calculated accounting for LEB %d: free %d, dirty %d", + lnum, freef, dirty); + goto out_destroy; + } + + if (lp->free + lp->dirty == c->leb_size && + freef + dirty == c->leb_size) + if ((is_idx && !(lp->flags & LPROPS_INDEX)) || + (!is_idx && freef == c->leb_size) || + lp->free == c->leb_size) { + /* + * Empty or freeable LEBs could contain index + * nodes from an uncompleted commit due to an + * unclean unmount. Or they could be empty for + * the same reason. Or it may simply not have been + * unmapped. + */ + freef = lp->free; + dirty = lp->dirty; + is_idx = 0; + } + + if (is_idx && lp->free + lp->dirty == freef + dirty && + lnum != c->ihead_lnum) { + /* + * After an unclean unmount, an index LEB could have a different + * amount of free space than the value recorded by lprops. That + * is because the in-the-gaps method may use free space or + * create free space (as a side-effect of using ubi_leb_change + * and not writing the whole LEB). The incorrect free space + * value is not a problem because the index is only ever + * allocated empty LEBs, so there will never be an attempt to + * write to the free space at the end of an index LEB - except + * by the in-the-gaps method for which it is not a problem. + */ + freef = lp->free; + dirty = lp->dirty; + } + + if (lp->free != freef || lp->dirty != dirty) + goto out_print; + + if (is_idx && !(lp->flags & LPROPS_INDEX)) { + if (freef == c->leb_size) + /* Free but not unmapped LEB, it's fine */ + is_idx = 0; + else { + ubifs_err("indexing node without indexing flag"); + goto out_print; + } + } + + if (!is_idx && (lp->flags & LPROPS_INDEX)) { + ubifs_err("data node with indexing flag"); + goto out_print; + } + + if (freef == c->leb_size) + lst->empty_lebs += 1; + + if (is_idx) + lst->idx_lebs += 1; + + if (!(lp->flags & LPROPS_INDEX)) + lst->total_used += c->leb_size - freef - dirty; + lst->total_free += freef; + lst->total_dirty += dirty; + + if (!(lp->flags & LPROPS_INDEX)) { + int spc = freef + dirty; + + if (spc < c->dead_wm) + lst->total_dead += spc; + else + lst->total_dark += ubifs_calc_dark(c, spc); + } + + ubifs_scan_destroy(sleb); + vfree(buf); + return LPT_SCAN_CONTINUE; + +out_print: + ubifs_err("bad accounting of LEB %d: free %d, dirty %d flags %#x, should be free %d, dirty %d", + lnum, lp->free, lp->dirty, lp->flags, freef, dirty); + ubifs_dump_leb(c, lnum); +out_destroy: + ubifs_scan_destroy(sleb); + ret = -EINVAL; +out: + vfree(buf); + return ret; +} + +/** + * dbg_check_lprops - check all LEB properties. + * @c: UBIFS file-system description object + * + * This function checks all LEB properties and makes sure they are all correct. + * It returns zero if everything is fine, %-EINVAL if there is an inconsistency + * and other negative error codes in case of other errors. This function is + * called while the file system is locked (because of commit start), so no + * additional locking is required. Note that locking the LPT mutex would cause + * a circular lock dependency with the TNC mutex. + */ +int dbg_check_lprops(struct ubifs_info *c) +{ + int i, err; + struct ubifs_lp_stats lst; + + if (!dbg_is_chk_lprops(c)) + return 0; + + /* + * As we are going to scan the media, the write buffers have to be + * synchronized. + */ + for (i = 0; i < c->jhead_cnt; i++) { + err = ubifs_wbuf_sync(&c->jheads[i].wbuf); + if (err) + return err; + } + + memset(&lst, 0, sizeof(struct ubifs_lp_stats)); + err = ubifs_lpt_scan_nolock(c, c->main_first, c->leb_cnt - 1, + (ubifs_lpt_scan_callback)scan_check_cb, + &lst); + if (err && err != -ENOSPC) + goto out; + + if (lst.empty_lebs != c->lst.empty_lebs || + lst.idx_lebs != c->lst.idx_lebs || + lst.total_free != c->lst.total_free || + lst.total_dirty != c->lst.total_dirty || + lst.total_used != c->lst.total_used) { + ubifs_err("bad overall accounting"); + ubifs_err("calculated: empty_lebs %d, idx_lebs %d, total_free %lld, total_dirty %lld, total_used %lld", + lst.empty_lebs, lst.idx_lebs, lst.total_free, + lst.total_dirty, lst.total_used); + ubifs_err("read from lprops: empty_lebs %d, idx_lebs %d, total_free %lld, total_dirty %lld, total_used %lld", + c->lst.empty_lebs, c->lst.idx_lebs, c->lst.total_free, + c->lst.total_dirty, c->lst.total_used); + err = -EINVAL; + goto out; + } + + if (lst.total_dead != c->lst.total_dead || + lst.total_dark != c->lst.total_dark) { + ubifs_err("bad dead/dark space accounting"); + ubifs_err("calculated: total_dead %lld, total_dark %lld", + lst.total_dead, lst.total_dark); + ubifs_err("read from lprops: total_dead %lld, total_dark %lld", + c->lst.total_dead, c->lst.total_dark); + err = -EINVAL; + goto out; + } + + err = dbg_check_cats(c); +out: + return err; +} diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c index 1a50d4cc27..8489e90e4a 100644 --- a/fs/ubifs/lpt.c +++ b/fs/ubifs/lpt.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Adrian Hunter * Artem Bityutskiy (Битюцкий Артём) @@ -44,8 +33,16 @@ */ #include "ubifs.h" -#include "crc16.h" +#ifndef __UBOOT__ +#include #include +#include +#else +#include +#include +#include +#include "crc16.h" +#endif /** * do_calc_lpt_geom - calculate sizes for the LPT area. @@ -158,6 +155,119 @@ int ubifs_calc_lpt_geom(struct ubifs_info *c) return 0; } +/** + * calc_dflt_lpt_geom - calculate default LPT geometry. + * @c: the UBIFS file-system description object + * @main_lebs: number of main area LEBs is passed and returned here + * @big_lpt: whether the LPT area is "big" is returned here + * + * The size of the LPT area depends on parameters that themselves are dependent + * on the size of the LPT area. This function, successively recalculates the LPT + * area geometry until the parameters and resultant geometry are consistent. + * + * This function returns %0 on success and a negative error code on failure. + */ +static int calc_dflt_lpt_geom(struct ubifs_info *c, int *main_lebs, + int *big_lpt) +{ + int i, lebs_needed; + long long sz; + + /* Start by assuming the minimum number of LPT LEBs */ + c->lpt_lebs = UBIFS_MIN_LPT_LEBS; + c->main_lebs = *main_lebs - c->lpt_lebs; + if (c->main_lebs <= 0) + return -EINVAL; + + /* And assume we will use the small LPT model */ + c->big_lpt = 0; + + /* + * Calculate the geometry based on assumptions above and then see if it + * makes sense + */ + do_calc_lpt_geom(c); + + /* Small LPT model must have lpt_sz < leb_size */ + if (c->lpt_sz > c->leb_size) { + /* Nope, so try again using big LPT model */ + c->big_lpt = 1; + do_calc_lpt_geom(c); + } + + /* Now check there are enough LPT LEBs */ + for (i = 0; i < 64 ; i++) { + sz = c->lpt_sz * 4; /* Allow 4 times the size */ + lebs_needed = div_u64(sz + c->leb_size - 1, c->leb_size); + if (lebs_needed > c->lpt_lebs) { + /* Not enough LPT LEBs so try again with more */ + c->lpt_lebs = lebs_needed; + c->main_lebs = *main_lebs - c->lpt_lebs; + if (c->main_lebs <= 0) + return -EINVAL; + do_calc_lpt_geom(c); + continue; + } + if (c->ltab_sz > c->leb_size) { + ubifs_err("LPT ltab too big"); + return -EINVAL; + } + *main_lebs = c->main_lebs; + *big_lpt = c->big_lpt; + return 0; + } + return -EINVAL; +} + +/** + * pack_bits - pack bit fields end-to-end. + * @addr: address at which to pack (passed and next address returned) + * @pos: bit position at which to pack (passed and next position returned) + * @val: value to pack + * @nrbits: number of bits of value to pack (1-32) + */ +static void pack_bits(uint8_t **addr, int *pos, uint32_t val, int nrbits) +{ + uint8_t *p = *addr; + int b = *pos; + + ubifs_assert(nrbits > 0); + ubifs_assert(nrbits <= 32); + ubifs_assert(*pos >= 0); + ubifs_assert(*pos < 8); + ubifs_assert((val >> nrbits) == 0 || nrbits == 32); + if (b) { + *p |= ((uint8_t)val) << b; + nrbits += b; + if (nrbits > 8) { + *++p = (uint8_t)(val >>= (8 - b)); + if (nrbits > 16) { + *++p = (uint8_t)(val >>= 8); + if (nrbits > 24) { + *++p = (uint8_t)(val >>= 8); + if (nrbits > 32) + *++p = (uint8_t)(val >>= 8); + } + } + } + } else { + *p = (uint8_t)val; + if (nrbits > 8) { + *++p = (uint8_t)(val >>= 8); + if (nrbits > 16) { + *++p = (uint8_t)(val >>= 8); + if (nrbits > 24) + *++p = (uint8_t)(val >>= 8); + } + } + } + b = nrbits & 7; + if (b == 0) + p++; + *addr = p; + *pos = b; +} + /** * ubifs_unpack_bits - unpack bit fields. * @addr: address at which to unpack (passed and next address returned) @@ -227,6 +337,118 @@ uint32_t ubifs_unpack_bits(uint8_t **addr, int *pos, int nrbits) return val; } +/** + * ubifs_pack_pnode - pack all the bit fields of a pnode. + * @c: UBIFS file-system description object + * @buf: buffer into which to pack + * @pnode: pnode to pack + */ +void ubifs_pack_pnode(struct ubifs_info *c, void *buf, + struct ubifs_pnode *pnode) +{ + uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES; + int i, pos = 0; + uint16_t crc; + + pack_bits(&addr, &pos, UBIFS_LPT_PNODE, UBIFS_LPT_TYPE_BITS); + if (c->big_lpt) + pack_bits(&addr, &pos, pnode->num, c->pcnt_bits); + for (i = 0; i < UBIFS_LPT_FANOUT; i++) { + pack_bits(&addr, &pos, pnode->lprops[i].free >> 3, + c->space_bits); + pack_bits(&addr, &pos, pnode->lprops[i].dirty >> 3, + c->space_bits); + if (pnode->lprops[i].flags & LPROPS_INDEX) + pack_bits(&addr, &pos, 1, 1); + else + pack_bits(&addr, &pos, 0, 1); + } + crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, + c->pnode_sz - UBIFS_LPT_CRC_BYTES); + addr = buf; + pos = 0; + pack_bits(&addr, &pos, crc, UBIFS_LPT_CRC_BITS); +} + +/** + * ubifs_pack_nnode - pack all the bit fields of a nnode. + * @c: UBIFS file-system description object + * @buf: buffer into which to pack + * @nnode: nnode to pack + */ +void ubifs_pack_nnode(struct ubifs_info *c, void *buf, + struct ubifs_nnode *nnode) +{ + uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES; + int i, pos = 0; + uint16_t crc; + + pack_bits(&addr, &pos, UBIFS_LPT_NNODE, UBIFS_LPT_TYPE_BITS); + if (c->big_lpt) + pack_bits(&addr, &pos, nnode->num, c->pcnt_bits); + for (i = 0; i < UBIFS_LPT_FANOUT; i++) { + int lnum = nnode->nbranch[i].lnum; + + if (lnum == 0) + lnum = c->lpt_last + 1; + pack_bits(&addr, &pos, lnum - c->lpt_first, c->lpt_lnum_bits); + pack_bits(&addr, &pos, nnode->nbranch[i].offs, + c->lpt_offs_bits); + } + crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, + c->nnode_sz - UBIFS_LPT_CRC_BYTES); + addr = buf; + pos = 0; + pack_bits(&addr, &pos, crc, UBIFS_LPT_CRC_BITS); +} + +/** + * ubifs_pack_ltab - pack the LPT's own lprops table. + * @c: UBIFS file-system description object + * @buf: buffer into which to pack + * @ltab: LPT's own lprops table to pack + */ +void ubifs_pack_ltab(struct ubifs_info *c, void *buf, + struct ubifs_lpt_lprops *ltab) +{ + uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES; + int i, pos = 0; + uint16_t crc; + + pack_bits(&addr, &pos, UBIFS_LPT_LTAB, UBIFS_LPT_TYPE_BITS); + for (i = 0; i < c->lpt_lebs; i++) { + pack_bits(&addr, &pos, ltab[i].free, c->lpt_spc_bits); + pack_bits(&addr, &pos, ltab[i].dirty, c->lpt_spc_bits); + } + crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, + c->ltab_sz - UBIFS_LPT_CRC_BYTES); + addr = buf; + pos = 0; + pack_bits(&addr, &pos, crc, UBIFS_LPT_CRC_BITS); +} + +/** + * ubifs_pack_lsave - pack the LPT's save table. + * @c: UBIFS file-system description object + * @buf: buffer into which to pack + * @lsave: LPT's save table to pack + */ +void ubifs_pack_lsave(struct ubifs_info *c, void *buf, int *lsave) +{ + uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES; + int i, pos = 0; + uint16_t crc; + + pack_bits(&addr, &pos, UBIFS_LPT_LSAVE, UBIFS_LPT_TYPE_BITS); + for (i = 0; i < c->lsave_cnt; i++) + pack_bits(&addr, &pos, lsave[i], c->lnum_bits); + crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, + c->lsave_sz - UBIFS_LPT_CRC_BYTES); + addr = buf; + pos = 0; + pack_bits(&addr, &pos, crc, UBIFS_LPT_CRC_BITS); +} + /** * ubifs_add_lpt_dirt - add dirty space to LPT LEB properties. * @c: UBIFS file-system description object @@ -243,6 +465,23 @@ void ubifs_add_lpt_dirt(struct ubifs_info *c, int lnum, int dirty) c->ltab[lnum - c->lpt_first].dirty += dirty; } +/** + * set_ltab - set LPT LEB properties. + * @c: UBIFS file-system description object + * @lnum: LEB number + * @free: amount of free space + * @dirty: amount of dirty space + */ +static void set_ltab(struct ubifs_info *c, int lnum, int free, int dirty) +{ + dbg_lp("LEB %d free %d dirty %d to %d %d", + lnum, c->ltab[lnum - c->lpt_first].free, + c->ltab[lnum - c->lpt_first].dirty, free, dirty); + ubifs_assert(lnum >= c->lpt_first && lnum <= c->lpt_last); + c->ltab[lnum - c->lpt_first].free = free; + c->ltab[lnum - c->lpt_first].dirty = dirty; +} + /** * ubifs_add_nnode_dirt - add dirty space to LPT LEB properties. * @c: UBIFS file-system description object @@ -275,6 +514,31 @@ static void add_pnode_dirt(struct ubifs_info *c, struct ubifs_pnode *pnode) c->pnode_sz); } +/** + * calc_nnode_num - calculate nnode number. + * @row: the row in the tree (root is zero) + * @col: the column in the row (leftmost is zero) + * + * The nnode number is a number that uniquely identifies a nnode and can be used + * easily to traverse the tree from the root to that nnode. + * + * This function calculates and returns the nnode number for the nnode at @row + * and @col. + */ +static int calc_nnode_num(int row, int col) +{ + int num, bits; + + num = 1; + while (row--) { + bits = (col & (UBIFS_LPT_FANOUT - 1)); + col >>= UBIFS_LPT_FANOUT_SHIFT; + num <<= UBIFS_LPT_FANOUT_SHIFT; + num |= bits; + } + return num; +} + /** * calc_nnode_num_from_parent - calculate nnode number. * @c: UBIFS file-system description object @@ -327,6 +591,269 @@ static int calc_pnode_num_from_parent(const struct ubifs_info *c, return num; } +/** + * ubifs_create_dflt_lpt - create default LPT. + * @c: UBIFS file-system description object + * @main_lebs: number of main area LEBs is passed and returned here + * @lpt_first: LEB number of first LPT LEB + * @lpt_lebs: number of LEBs for LPT is passed and returned here + * @big_lpt: use big LPT model is passed and returned here + * + * This function returns %0 on success and a negative error code on failure. + */ +int ubifs_create_dflt_lpt(struct ubifs_info *c, int *main_lebs, int lpt_first, + int *lpt_lebs, int *big_lpt) +{ + int lnum, err = 0, node_sz, iopos, i, j, cnt, len, alen, row; + int blnum, boffs, bsz, bcnt; + struct ubifs_pnode *pnode = NULL; + struct ubifs_nnode *nnode = NULL; + void *buf = NULL, *p; + struct ubifs_lpt_lprops *ltab = NULL; + int *lsave = NULL; + + err = calc_dflt_lpt_geom(c, main_lebs, big_lpt); + if (err) + return err; + *lpt_lebs = c->lpt_lebs; + + /* Needed by 'ubifs_pack_nnode()' and 'set_ltab()' */ + c->lpt_first = lpt_first; + /* Needed by 'set_ltab()' */ + c->lpt_last = lpt_first + c->lpt_lebs - 1; + /* Needed by 'ubifs_pack_lsave()' */ + c->main_first = c->leb_cnt - *main_lebs; + + lsave = kmalloc(sizeof(int) * c->lsave_cnt, GFP_KERNEL); + pnode = kzalloc(sizeof(struct ubifs_pnode), GFP_KERNEL); + nnode = kzalloc(sizeof(struct ubifs_nnode), GFP_KERNEL); + buf = vmalloc(c->leb_size); + ltab = vmalloc(sizeof(struct ubifs_lpt_lprops) * c->lpt_lebs); + if (!pnode || !nnode || !buf || !ltab || !lsave) { + err = -ENOMEM; + goto out; + } + + ubifs_assert(!c->ltab); + c->ltab = ltab; /* Needed by set_ltab */ + + /* Initialize LPT's own lprops */ + for (i = 0; i < c->lpt_lebs; i++) { + ltab[i].free = c->leb_size; + ltab[i].dirty = 0; + ltab[i].tgc = 0; + ltab[i].cmt = 0; + } + + lnum = lpt_first; + p = buf; + /* Number of leaf nodes (pnodes) */ + cnt = c->pnode_cnt; + + /* + * The first pnode contains the LEB properties for the LEBs that contain + * the root inode node and the root index node of the index tree. + */ + node_sz = ALIGN(ubifs_idx_node_sz(c, 1), 8); + iopos = ALIGN(node_sz, c->min_io_size); + pnode->lprops[0].free = c->leb_size - iopos; + pnode->lprops[0].dirty = iopos - node_sz; + pnode->lprops[0].flags = LPROPS_INDEX; + + node_sz = UBIFS_INO_NODE_SZ; + iopos = ALIGN(node_sz, c->min_io_size); + pnode->lprops[1].free = c->leb_size - iopos; + pnode->lprops[1].dirty = iopos - node_sz; + + for (i = 2; i < UBIFS_LPT_FANOUT; i++) + pnode->lprops[i].free = c->leb_size; + + /* Add first pnode */ + ubifs_pack_pnode(c, p, pnode); + p += c->pnode_sz; + len = c->pnode_sz; + pnode->num += 1; + + /* Reset pnode values for remaining pnodes */ + pnode->lprops[0].free = c->leb_size; + pnode->lprops[0].dirty = 0; + pnode->lprops[0].flags = 0; + + pnode->lprops[1].free = c->leb_size; + pnode->lprops[1].dirty = 0; + + /* + * To calculate the internal node branches, we keep information about + * the level below. + */ + blnum = lnum; /* LEB number of level below */ + boffs = 0; /* Offset of level below */ + bcnt = cnt; /* Number of nodes in level below */ + bsz = c->pnode_sz; /* Size of nodes in level below */ + + /* Add all remaining pnodes */ + for (i = 1; i < cnt; i++) { + if (len + c->pnode_sz > c->leb_size) { + alen = ALIGN(len, c->min_io_size); + set_ltab(c, lnum, c->leb_size - alen, alen - len); + memset(p, 0xff, alen - len); + err = ubifs_leb_change(c, lnum++, buf, alen); + if (err) + goto out; + p = buf; + len = 0; + } + ubifs_pack_pnode(c, p, pnode); + p += c->pnode_sz; + len += c->pnode_sz; + /* + * pnodes are simply numbered left to right starting at zero, + * which means the pnode number can be used easily to traverse + * down the tree to the corresponding pnode. + */ + pnode->num += 1; + } + + row = 0; + for (i = UBIFS_LPT_FANOUT; cnt > i; i <<= UBIFS_LPT_FANOUT_SHIFT) + row += 1; + /* Add all nnodes, one level at a time */ + while (1) { + /* Number of internal nodes (nnodes) at next level */ + cnt = DIV_ROUND_UP(cnt, UBIFS_LPT_FANOUT); + for (i = 0; i < cnt; i++) { + if (len + c->nnode_sz > c->leb_size) { + alen = ALIGN(len, c->min_io_size); + set_ltab(c, lnum, c->leb_size - alen, + alen - len); + memset(p, 0xff, alen - len); + err = ubifs_leb_change(c, lnum++, buf, alen); + if (err) + goto out; + p = buf; + len = 0; + } + /* Only 1 nnode at this level, so it is the root */ + if (cnt == 1) { + c->lpt_lnum = lnum; + c->lpt_offs = len; + } + /* Set branches to the level below */ + for (j = 0; j < UBIFS_LPT_FANOUT; j++) { + if (bcnt) { + if (boffs + bsz > c->leb_size) { + blnum += 1; + boffs = 0; + } + nnode->nbranch[j].lnum = blnum; + nnode->nbranch[j].offs = boffs; + boffs += bsz; + bcnt--; + } else { + nnode->nbranch[j].lnum = 0; + nnode->nbranch[j].offs = 0; + } + } + nnode->num = calc_nnode_num(row, i); + ubifs_pack_nnode(c, p, nnode); + p += c->nnode_sz; + len += c->nnode_sz; + } + /* Only 1 nnode at this level, so it is the root */ + if (cnt == 1) + break; + /* Update the information about the level below */ + bcnt = cnt; + bsz = c->nnode_sz; + row -= 1; + } + + if (*big_lpt) { + /* Need to add LPT's save table */ + if (len + c->lsave_sz > c->leb_size) { + alen = ALIGN(len, c->min_io_size); + set_ltab(c, lnum, c->leb_size - alen, alen - len); + memset(p, 0xff, alen - len); + err = ubifs_leb_change(c, lnum++, buf, alen); + if (err) + goto out; + p = buf; + len = 0; + } + + c->lsave_lnum = lnum; + c->lsave_offs = len; + + for (i = 0; i < c->lsave_cnt && i < *main_lebs; i++) + lsave[i] = c->main_first + i; + for (; i < c->lsave_cnt; i++) + lsave[i] = c->main_first; + + ubifs_pack_lsave(c, p, lsave); + p += c->lsave_sz; + len += c->lsave_sz; + } + + /* Need to add LPT's own LEB properties table */ + if (len + c->ltab_sz > c->leb_size) { + alen = ALIGN(len, c->min_io_size); + set_ltab(c, lnum, c->leb_size - alen, alen - len); + memset(p, 0xff, alen - len); + err = ubifs_leb_change(c, lnum++, buf, alen); + if (err) + goto out; + p = buf; + len = 0; + } + + c->ltab_lnum = lnum; + c->ltab_offs = len; + + /* Update ltab before packing it */ + len += c->ltab_sz; + alen = ALIGN(len, c->min_io_size); + set_ltab(c, lnum, c->leb_size - alen, alen - len); + + ubifs_pack_ltab(c, p, ltab); + p += c->ltab_sz; + + /* Write remaining buffer */ + memset(p, 0xff, alen - len); + err = ubifs_leb_change(c, lnum, buf, alen); + if (err) + goto out; + + c->nhead_lnum = lnum; + c->nhead_offs = ALIGN(len, c->min_io_size); + + dbg_lp("space_bits %d", c->space_bits); + dbg_lp("lpt_lnum_bits %d", c->lpt_lnum_bits); + dbg_lp("lpt_offs_bits %d", c->lpt_offs_bits); + dbg_lp("lpt_spc_bits %d", c->lpt_spc_bits); + dbg_lp("pcnt_bits %d", c->pcnt_bits); + dbg_lp("lnum_bits %d", c->lnum_bits); + dbg_lp("pnode_sz %d", c->pnode_sz); + dbg_lp("nnode_sz %d", c->nnode_sz); + dbg_lp("ltab_sz %d", c->ltab_sz); + dbg_lp("lsave_sz %d", c->lsave_sz); + dbg_lp("lsave_cnt %d", c->lsave_cnt); + dbg_lp("lpt_hght %d", c->lpt_hght); + dbg_lp("big_lpt %d", c->big_lpt); + dbg_lp("LPT root is at %d:%d", c->lpt_lnum, c->lpt_offs); + dbg_lp("LPT head is at %d:%d", c->nhead_lnum, c->nhead_offs); + dbg_lp("LPT ltab is at %d:%d", c->ltab_lnum, c->ltab_offs); + if (c->big_lpt) + dbg_lp("LPT lsave is at %d:%d", c->lsave_lnum, c->lsave_offs); +out: + c->ltab = NULL; + kfree(lsave); + vfree(ltab); + vfree(buf); + kfree(nnode); + kfree(pnode); + return err; +} + /** * update_cats - add LEB properties of a pnode to LEB category lists and heaps. * @c: UBIFS file-system description object @@ -392,7 +919,7 @@ static int check_lpt_crc(void *buf, int len) if (crc != calc_crc) { ubifs_err("invalid crc in LPT node: crc %hx calc %hx", crc, calc_crc); - dbg_dump_stack(); + dump_stack(); return -EINVAL; } return 0; @@ -415,7 +942,7 @@ static int check_lpt_type(uint8_t **addr, int *pos, int type) if (node_type != type) { ubifs_err("invalid type (%d) in LPT node type %d", node_type, type); - dbg_dump_stack(); + dump_stack(); return -EINVAL; } return 0; @@ -524,6 +1051,34 @@ static int unpack_ltab(const struct ubifs_info *c, void *buf) return err; } +#ifndef __UBOOT__ +/** + * unpack_lsave - unpack the LPT's save table. + * @c: UBIFS file-system description object + * @buf: buffer from which to unpack + * + * This function returns %0 on success and a negative error code on failure. + */ +static int unpack_lsave(const struct ubifs_info *c, void *buf) +{ + uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES; + int i, pos = 0, err; + + err = check_lpt_type(&addr, &pos, UBIFS_LPT_LSAVE); + if (err) + return err; + for (i = 0; i < c->lsave_cnt; i++) { + int lnum = ubifs_unpack_bits(&addr, &pos, c->lnum_bits); + + if (lnum < c->main_first || lnum >= c->leb_cnt) + return -EINVAL; + c->lsave[i] = lnum; + } + err = check_lpt_crc(buf, c->lsave_sz); + return err; +} +#endif + /** * validate_nnode - validate a nnode. * @c: UBIFS file-system description object @@ -662,7 +1217,7 @@ int ubifs_read_nnode(struct ubifs_info *c, struct ubifs_nnode *parent, int iip) if (c->big_lpt) nnode->num = calc_nnode_num_from_parent(c, parent, iip); } else { - err = ubi_read(c->ubi, lnum, buf, offs, c->nnode_sz); + err = ubifs_leb_read(c, lnum, buf, offs, c->nnode_sz, 1); if (err) goto out; err = ubifs_unpack_nnode(c, buf, nnode); @@ -687,6 +1242,7 @@ int ubifs_read_nnode(struct ubifs_info *c, struct ubifs_nnode *parent, int iip) out: ubifs_err("error %d reading nnode at %d:%d", err, lnum, offs); + dump_stack(); kfree(nnode); return err; } @@ -710,10 +1266,9 @@ static int read_pnode(struct ubifs_info *c, struct ubifs_nnode *parent, int iip) lnum = branch->lnum; offs = branch->offs; pnode = kzalloc(sizeof(struct ubifs_pnode), GFP_NOFS); - if (!pnode) { - err = -ENOMEM; - goto out; - } + if (!pnode) + return -ENOMEM; + if (lnum == 0) { /* * This pnode was not written which just means that the LEB @@ -731,7 +1286,7 @@ static int read_pnode(struct ubifs_info *c, struct ubifs_nnode *parent, int iip) lprops->flags = ubifs_categorize_lprops(c, lprops); } } else { - err = ubi_read(c->ubi, lnum, buf, offs, c->pnode_sz); + err = ubifs_leb_read(c, lnum, buf, offs, c->pnode_sz, 1); if (err) goto out; err = unpack_pnode(c, buf, pnode); @@ -752,8 +1307,9 @@ static int read_pnode(struct ubifs_info *c, struct ubifs_nnode *parent, int iip) out: ubifs_err("error %d reading pnode at %d:%d", err, lnum, offs); - dbg_dump_pnode(c, pnode, parent, iip); - dbg_msg("calc num: %d", calc_pnode_num_from_parent(c, parent, iip)); + ubifs_dump_pnode(c, pnode, parent, iip); + dump_stack(); + ubifs_err("calc num: %d", calc_pnode_num_from_parent(c, parent, iip)); kfree(pnode); return err; } @@ -772,7 +1328,7 @@ static int read_ltab(struct ubifs_info *c) buf = vmalloc(c->ltab_sz); if (!buf) return -ENOMEM; - err = ubi_read(c->ubi, c->ltab_lnum, buf, c->ltab_offs, c->ltab_sz); + err = ubifs_leb_read(c, c->ltab_lnum, buf, c->ltab_offs, c->ltab_sz, 1); if (err) goto out; err = unpack_ltab(c, buf); @@ -781,6 +1337,50 @@ out: return err; } +#ifndef __UBOOT__ +/** + * read_lsave - read LPT's save table. + * @c: UBIFS file-system description object + * + * This function returns %0 on success and a negative error code on failure. + */ +static int read_lsave(struct ubifs_info *c) +{ + int err, i; + void *buf; + + buf = vmalloc(c->lsave_sz); + if (!buf) + return -ENOMEM; + err = ubifs_leb_read(c, c->lsave_lnum, buf, c->lsave_offs, + c->lsave_sz, 1); + if (err) + goto out; + err = unpack_lsave(c, buf); + if (err) + goto out; + for (i = 0; i < c->lsave_cnt; i++) { + int lnum = c->lsave[i]; + struct ubifs_lprops *lprops; + + /* + * Due to automatic resizing, the values in the lsave table + * could be beyond the volume size - just ignore them. + */ + if (lnum >= c->leb_cnt) + continue; + lprops = ubifs_lpt_lookup(c, lnum); + if (IS_ERR(lprops)) { + err = PTR_ERR(lprops); + goto out; + } + } +out: + vfree(buf); + return err; +} +#endif + /** * ubifs_get_nnode - get a nnode. * @c: UBIFS file-system description object @@ -861,13 +1461,13 @@ struct ubifs_lprops *ubifs_lpt_lookup(struct ubifs_info *c, int lnum) shft -= UBIFS_LPT_FANOUT_SHIFT; nnode = ubifs_get_nnode(c, nnode, iip); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); } iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); shft -= UBIFS_LPT_FANOUT_SHIFT; pnode = ubifs_get_pnode(c, nnode, iip); if (IS_ERR(pnode)) - return ERR_PTR(PTR_ERR(pnode)); + return ERR_CAST(pnode); iip = (i & (UBIFS_LPT_FANOUT - 1)); dbg_lp("LEB %d, free %d, dirty %d, flags %d", lnum, pnode->lprops[iip].free, pnode->lprops[iip].dirty, @@ -990,7 +1590,7 @@ struct ubifs_lprops *ubifs_lpt_lookup_dirty(struct ubifs_info *c, int lnum) nnode = c->nroot; nnode = dirty_cow_nnode(c, nnode); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); i = lnum - c->main_first; shft = c->lpt_hght * UBIFS_LPT_FANOUT_SHIFT; for (h = 1; h < c->lpt_hght; h++) { @@ -998,19 +1598,19 @@ struct ubifs_lprops *ubifs_lpt_lookup_dirty(struct ubifs_info *c, int lnum) shft -= UBIFS_LPT_FANOUT_SHIFT; nnode = ubifs_get_nnode(c, nnode, iip); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); nnode = dirty_cow_nnode(c, nnode); if (IS_ERR(nnode)) - return ERR_PTR(PTR_ERR(nnode)); + return ERR_CAST(nnode); } iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); shft -= UBIFS_LPT_FANOUT_SHIFT; pnode = ubifs_get_pnode(c, nnode, iip); if (IS_ERR(pnode)) - return ERR_PTR(PTR_ERR(pnode)); + return ERR_CAST(pnode); pnode = dirty_cow_pnode(c, pnode); if (IS_ERR(pnode)) - return ERR_PTR(PTR_ERR(pnode)); + return ERR_CAST(pnode); iip = (i & (UBIFS_LPT_FANOUT - 1)); dbg_lp("LEB %d, free %d, dirty %d, flags %d", lnum, pnode->lprops[iip].free, pnode->lprops[iip].dirty, @@ -1079,6 +1679,47 @@ static int lpt_init_rd(struct ubifs_info *c) return 0; } +#ifndef __UBOOT__ +/** + * lpt_init_wr - initialize the LPT for writing. + * @c: UBIFS file-system description object + * + * 'lpt_init_rd()' must have been called already. + * + * This function returns %0 on success and a negative error code on failure. + */ +static int lpt_init_wr(struct ubifs_info *c) +{ + int err, i; + + c->ltab_cmt = vmalloc(sizeof(struct ubifs_lpt_lprops) * c->lpt_lebs); + if (!c->ltab_cmt) + return -ENOMEM; + + c->lpt_buf = vmalloc(c->leb_size); + if (!c->lpt_buf) + return -ENOMEM; + + if (c->big_lpt) { + c->lsave = kmalloc(sizeof(int) * c->lsave_cnt, GFP_NOFS); + if (!c->lsave) + return -ENOMEM; + err = read_lsave(c); + if (err) + return err; + } + + for (i = 0; i < c->lpt_lebs; i++) + if (c->ltab[i].free == c->leb_size) { + err = ubifs_leb_unmap(c, i + c->lpt_first); + if (err) + return err; + } + + return 0; +} +#endif + /** * ubifs_lpt_init - initialize the LPT. * @c: UBIFS file-system description object @@ -1097,9 +1738,547 @@ int ubifs_lpt_init(struct ubifs_info *c, int rd, int wr) if (rd) { err = lpt_init_rd(c); + if (err) + goto out_err; + } + +#ifndef __UBOOT__ + if (wr) { + err = lpt_init_wr(c); + if (err) + goto out_err; + } +#endif + + return 0; + +out_err: +#ifndef __UBOOT__ + if (wr) + ubifs_lpt_free(c, 1); +#endif + if (rd) + ubifs_lpt_free(c, 0); + return err; +} + +/** + * struct lpt_scan_node - somewhere to put nodes while we scan LPT. + * @nnode: where to keep a nnode + * @pnode: where to keep a pnode + * @cnode: where to keep a cnode + * @in_tree: is the node in the tree in memory + * @ptr.nnode: pointer to the nnode (if it is an nnode) which may be here or in + * the tree + * @ptr.pnode: ditto for pnode + * @ptr.cnode: ditto for cnode + */ +struct lpt_scan_node { + union { + struct ubifs_nnode nnode; + struct ubifs_pnode pnode; + struct ubifs_cnode cnode; + }; + int in_tree; + union { + struct ubifs_nnode *nnode; + struct ubifs_pnode *pnode; + struct ubifs_cnode *cnode; + } ptr; +}; + +/** + * scan_get_nnode - for the scan, get a nnode from either the tree or flash. + * @c: the UBIFS file-system description object + * @path: where to put the nnode + * @parent: parent of the nnode + * @iip: index in parent of the nnode + * + * This function returns a pointer to the nnode on success or a negative error + * code on failure. + */ +static struct ubifs_nnode *scan_get_nnode(struct ubifs_info *c, + struct lpt_scan_node *path, + struct ubifs_nnode *parent, int iip) +{ + struct ubifs_nbranch *branch; + struct ubifs_nnode *nnode; + void *buf = c->lpt_nod_buf; + int err; + + branch = &parent->nbranch[iip]; + nnode = branch->nnode; + if (nnode) { + path->in_tree = 1; + path->ptr.nnode = nnode; + return nnode; + } + nnode = &path->nnode; + path->in_tree = 0; + path->ptr.nnode = nnode; + memset(nnode, 0, sizeof(struct ubifs_nnode)); + if (branch->lnum == 0) { + /* + * This nnode was not written which just means that the LEB + * properties in the subtree below it describe empty LEBs. We + * make the nnode as though we had read it, which in fact means + * doing almost nothing. + */ + if (c->big_lpt) + nnode->num = calc_nnode_num_from_parent(c, parent, iip); + } else { + err = ubifs_leb_read(c, branch->lnum, buf, branch->offs, + c->nnode_sz, 1); + if (err) + return ERR_PTR(err); + err = ubifs_unpack_nnode(c, buf, nnode); + if (err) + return ERR_PTR(err); + } + err = validate_nnode(c, nnode, parent, iip); + if (err) + return ERR_PTR(err); + if (!c->big_lpt) + nnode->num = calc_nnode_num_from_parent(c, parent, iip); + nnode->level = parent->level - 1; + nnode->parent = parent; + nnode->iip = iip; + return nnode; +} + +/** + * scan_get_pnode - for the scan, get a pnode from either the tree or flash. + * @c: the UBIFS file-system description object + * @path: where to put the pnode + * @parent: parent of the pnode + * @iip: index in parent of the pnode + * + * This function returns a pointer to the pnode on success or a negative error + * code on failure. + */ +static struct ubifs_pnode *scan_get_pnode(struct ubifs_info *c, + struct lpt_scan_node *path, + struct ubifs_nnode *parent, int iip) +{ + struct ubifs_nbranch *branch; + struct ubifs_pnode *pnode; + void *buf = c->lpt_nod_buf; + int err; + + branch = &parent->nbranch[iip]; + pnode = branch->pnode; + if (pnode) { + path->in_tree = 1; + path->ptr.pnode = pnode; + return pnode; + } + pnode = &path->pnode; + path->in_tree = 0; + path->ptr.pnode = pnode; + memset(pnode, 0, sizeof(struct ubifs_pnode)); + if (branch->lnum == 0) { + /* + * This pnode was not written which just means that the LEB + * properties in it describe empty LEBs. We make the pnode as + * though we had read it. + */ + int i; + + if (c->big_lpt) + pnode->num = calc_pnode_num_from_parent(c, parent, iip); + for (i = 0; i < UBIFS_LPT_FANOUT; i++) { + struct ubifs_lprops * const lprops = &pnode->lprops[i]; + + lprops->free = c->leb_size; + lprops->flags = ubifs_categorize_lprops(c, lprops); + } + } else { + ubifs_assert(branch->lnum >= c->lpt_first && + branch->lnum <= c->lpt_last); + ubifs_assert(branch->offs >= 0 && branch->offs < c->leb_size); + err = ubifs_leb_read(c, branch->lnum, buf, branch->offs, + c->pnode_sz, 1); + if (err) + return ERR_PTR(err); + err = unpack_pnode(c, buf, pnode); + if (err) + return ERR_PTR(err); + } + err = validate_pnode(c, pnode, parent, iip); + if (err) + return ERR_PTR(err); + if (!c->big_lpt) + pnode->num = calc_pnode_num_from_parent(c, parent, iip); + pnode->parent = parent; + pnode->iip = iip; + set_pnode_lnum(c, pnode); + return pnode; +} + +/** + * ubifs_lpt_scan_nolock - scan the LPT. + * @c: the UBIFS file-system description object + * @start_lnum: LEB number from which to start scanning + * @end_lnum: LEB number at which to stop scanning + * @scan_cb: callback function called for each lprops + * @data: data to be passed to the callback function + * + * This function returns %0 on success and a negative error code on failure. + */ +int ubifs_lpt_scan_nolock(struct ubifs_info *c, int start_lnum, int end_lnum, + ubifs_lpt_scan_callback scan_cb, void *data) +{ + int err = 0, i, h, iip, shft; + struct ubifs_nnode *nnode; + struct ubifs_pnode *pnode; + struct lpt_scan_node *path; + + if (start_lnum == -1) { + start_lnum = end_lnum + 1; + if (start_lnum >= c->leb_cnt) + start_lnum = c->main_first; + } + + ubifs_assert(start_lnum >= c->main_first && start_lnum < c->leb_cnt); + ubifs_assert(end_lnum >= c->main_first && end_lnum < c->leb_cnt); + + if (!c->nroot) { + err = ubifs_read_nnode(c, NULL, 0); if (err) return err; } + path = kmalloc(sizeof(struct lpt_scan_node) * (c->lpt_hght + 1), + GFP_NOFS); + if (!path) + return -ENOMEM; + + path[0].ptr.nnode = c->nroot; + path[0].in_tree = 1; +again: + /* Descend to the pnode containing start_lnum */ + nnode = c->nroot; + i = start_lnum - c->main_first; + shft = c->lpt_hght * UBIFS_LPT_FANOUT_SHIFT; + for (h = 1; h < c->lpt_hght; h++) { + iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); + shft -= UBIFS_LPT_FANOUT_SHIFT; + nnode = scan_get_nnode(c, path + h, nnode, iip); + if (IS_ERR(nnode)) { + err = PTR_ERR(nnode); + goto out; + } + } + iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); + shft -= UBIFS_LPT_FANOUT_SHIFT; + pnode = scan_get_pnode(c, path + h, nnode, iip); + if (IS_ERR(pnode)) { + err = PTR_ERR(pnode); + goto out; + } + iip = (i & (UBIFS_LPT_FANOUT - 1)); + + /* Loop for each lprops */ + while (1) { + struct ubifs_lprops *lprops = &pnode->lprops[iip]; + int ret, lnum = lprops->lnum; + + ret = scan_cb(c, lprops, path[h].in_tree, data); + if (ret < 0) { + err = ret; + goto out; + } + if (ret & LPT_SCAN_ADD) { + /* Add all the nodes in path to the tree in memory */ + for (h = 1; h < c->lpt_hght; h++) { + const size_t sz = sizeof(struct ubifs_nnode); + struct ubifs_nnode *parent; + + if (path[h].in_tree) + continue; + nnode = kmemdup(&path[h].nnode, sz, GFP_NOFS); + if (!nnode) { + err = -ENOMEM; + goto out; + } + parent = nnode->parent; + parent->nbranch[nnode->iip].nnode = nnode; + path[h].ptr.nnode = nnode; + path[h].in_tree = 1; + path[h + 1].cnode.parent = nnode; + } + if (path[h].in_tree) + ubifs_ensure_cat(c, lprops); + else { + const size_t sz = sizeof(struct ubifs_pnode); + struct ubifs_nnode *parent; + + pnode = kmemdup(&path[h].pnode, sz, GFP_NOFS); + if (!pnode) { + err = -ENOMEM; + goto out; + } + parent = pnode->parent; + parent->nbranch[pnode->iip].pnode = pnode; + path[h].ptr.pnode = pnode; + path[h].in_tree = 1; + update_cats(c, pnode); + c->pnodes_have += 1; + } + err = dbg_check_lpt_nodes(c, (struct ubifs_cnode *) + c->nroot, 0, 0); + if (err) + goto out; + err = dbg_check_cats(c); + if (err) + goto out; + } + if (ret & LPT_SCAN_STOP) { + err = 0; + break; + } + /* Get the next lprops */ + if (lnum == end_lnum) { + /* + * We got to the end without finding what we were + * looking for + */ + err = -ENOSPC; + goto out; + } + if (lnum + 1 >= c->leb_cnt) { + /* Wrap-around to the beginning */ + start_lnum = c->main_first; + goto again; + } + if (iip + 1 < UBIFS_LPT_FANOUT) { + /* Next lprops is in the same pnode */ + iip += 1; + continue; + } + /* We need to get the next pnode. Go up until we can go right */ + iip = pnode->iip; + while (1) { + h -= 1; + ubifs_assert(h >= 0); + nnode = path[h].ptr.nnode; + if (iip + 1 < UBIFS_LPT_FANOUT) + break; + iip = nnode->iip; + } + /* Go right */ + iip += 1; + /* Descend to the pnode */ + h += 1; + for (; h < c->lpt_hght; h++) { + nnode = scan_get_nnode(c, path + h, nnode, iip); + if (IS_ERR(nnode)) { + err = PTR_ERR(nnode); + goto out; + } + iip = 0; + } + pnode = scan_get_pnode(c, path + h, nnode, iip); + if (IS_ERR(pnode)) { + err = PTR_ERR(pnode); + goto out; + } + iip = 0; + } +out: + kfree(path); + return err; +} + +/** + * dbg_chk_pnode - check a pnode. + * @c: the UBIFS file-system description object + * @pnode: pnode to check + * @col: pnode column + * + * This function returns %0 on success and a negative error code on failure. + */ +static int dbg_chk_pnode(struct ubifs_info *c, struct ubifs_pnode *pnode, + int col) +{ + int i; + + if (pnode->num != col) { + ubifs_err("pnode num %d expected %d parent num %d iip %d", + pnode->num, col, pnode->parent->num, pnode->iip); + return -EINVAL; + } + for (i = 0; i < UBIFS_LPT_FANOUT; i++) { + struct ubifs_lprops *lp, *lprops = &pnode->lprops[i]; + int lnum = (pnode->num << UBIFS_LPT_FANOUT_SHIFT) + i + + c->main_first; + int found, cat = lprops->flags & LPROPS_CAT_MASK; + struct ubifs_lpt_heap *heap; + struct list_head *list = NULL; + + if (lnum >= c->leb_cnt) + continue; + if (lprops->lnum != lnum) { + ubifs_err("bad LEB number %d expected %d", + lprops->lnum, lnum); + return -EINVAL; + } + if (lprops->flags & LPROPS_TAKEN) { + if (cat != LPROPS_UNCAT) { + ubifs_err("LEB %d taken but not uncat %d", + lprops->lnum, cat); + return -EINVAL; + } + continue; + } + if (lprops->flags & LPROPS_INDEX) { + switch (cat) { + case LPROPS_UNCAT: + case LPROPS_DIRTY_IDX: + case LPROPS_FRDI_IDX: + break; + default: + ubifs_err("LEB %d index but cat %d", + lprops->lnum, cat); + return -EINVAL; + } + } else { + switch (cat) { + case LPROPS_UNCAT: + case LPROPS_DIRTY: + case LPROPS_FREE: + case LPROPS_EMPTY: + case LPROPS_FREEABLE: + break; + default: + ubifs_err("LEB %d not index but cat %d", + lprops->lnum, cat); + return -EINVAL; + } + } + switch (cat) { + case LPROPS_UNCAT: + list = &c->uncat_list; + break; + case LPROPS_EMPTY: + list = &c->empty_list; + break; + case LPROPS_FREEABLE: + list = &c->freeable_list; + break; + case LPROPS_FRDI_IDX: + list = &c->frdi_idx_list; + break; + } + found = 0; + switch (cat) { + case LPROPS_DIRTY: + case LPROPS_DIRTY_IDX: + case LPROPS_FREE: + heap = &c->lpt_heap[cat - 1]; + if (lprops->hpos < heap->cnt && + heap->arr[lprops->hpos] == lprops) + found = 1; + break; + case LPROPS_UNCAT: + case LPROPS_EMPTY: + case LPROPS_FREEABLE: + case LPROPS_FRDI_IDX: + list_for_each_entry(lp, list, list) + if (lprops == lp) { + found = 1; + break; + } + break; + } + if (!found) { + ubifs_err("LEB %d cat %d not found in cat heap/list", + lprops->lnum, cat); + return -EINVAL; + } + switch (cat) { + case LPROPS_EMPTY: + if (lprops->free != c->leb_size) { + ubifs_err("LEB %d cat %d free %d dirty %d", + lprops->lnum, cat, lprops->free, + lprops->dirty); + return -EINVAL; + } + case LPROPS_FREEABLE: + case LPROPS_FRDI_IDX: + if (lprops->free + lprops->dirty != c->leb_size) { + ubifs_err("LEB %d cat %d free %d dirty %d", + lprops->lnum, cat, lprops->free, + lprops->dirty); + return -EINVAL; + } + } + } + return 0; +} + +/** + * dbg_check_lpt_nodes - check nnodes and pnodes. + * @c: the UBIFS file-system description object + * @cnode: next cnode (nnode or pnode) to check + * @row: row of cnode (root is zero) + * @col: column of cnode (leftmost is zero) + * + * This function returns %0 on success and a negative error code on failure. + */ +int dbg_check_lpt_nodes(struct ubifs_info *c, struct ubifs_cnode *cnode, + int row, int col) +{ + struct ubifs_nnode *nnode, *nn; + struct ubifs_cnode *cn; + int num, iip = 0, err; + + if (!dbg_is_chk_lprops(c)) + return 0; + + while (cnode) { + ubifs_assert(row >= 0); + nnode = cnode->parent; + if (cnode->level) { + /* cnode is a nnode */ + num = calc_nnode_num(row, col); + if (cnode->num != num) { + ubifs_err("nnode num %d expected %d parent num %d iip %d", + cnode->num, num, + (nnode ? nnode->num : 0), cnode->iip); + return -EINVAL; + } + nn = (struct ubifs_nnode *)cnode; + while (iip < UBIFS_LPT_FANOUT) { + cn = nn->nbranch[iip].cnode; + if (cn) { + /* Go down */ + row += 1; + col <<= UBIFS_LPT_FANOUT_SHIFT; + col += iip; + iip = 0; + cnode = cn; + break; + } + /* Go right */ + iip += 1; + } + if (iip < UBIFS_LPT_FANOUT) + continue; + } else { + struct ubifs_pnode *pnode; + + /* cnode is a pnode */ + pnode = (struct ubifs_pnode *)cnode; + err = dbg_chk_pnode(c, pnode, col); + if (err) + return err; + } + /* Go up and to the right */ + row -= 1; + col >>= UBIFS_LPT_FANOUT_SHIFT; + iip = cnode->iip + 1; + cnode = (struct ubifs_cnode *)nnode; + } return 0; } diff --git a/fs/ubifs/lpt_commit.c b/fs/ubifs/lpt_commit.c index c0af8187ac..c818d4ca5a 100644 --- a/fs/ubifs/lpt_commit.c +++ b/fs/ubifs/lpt_commit.c @@ -3,30 +3,1293 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0+ * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * Authors: Adrian Hunter + * Artem Bityutskiy (Битюцкий Артём) + */ + +/* + * This file implements commit-related functionality of the LEB properties + * subsystem. + */ + +#ifndef __UBOOT__ +#include +#include +#include +#else +#include +#include +#include "crc16.h" +#endif +#include "ubifs.h" + +#ifndef __UBOOT__ +static int dbg_populate_lsave(struct ubifs_info *c); +#endif + +/** + * first_dirty_cnode - find first dirty cnode. + * @c: UBIFS file-system description object + * @nnode: nnode at which to start + * + * This function returns the first dirty cnode or %NULL if there is not one. + */ +static struct ubifs_cnode *first_dirty_cnode(struct ubifs_nnode *nnode) +{ + ubifs_assert(nnode); + while (1) { + int i, cont = 0; + + for (i = 0; i < UBIFS_LPT_FANOUT; i++) { + struct ubifs_cnode *cnode; + + cnode = nnode->nbranch[i].cnode; + if (cnode && + test_bit(DIRTY_CNODE, &cnode->flags)) { + if (cnode->level == 0) + return cnode; + nnode = (struct ubifs_nnode *)cnode; + cont = 1; + break; + } + } + if (!cont) + return (struct ubifs_cnode *)nnode; + } +} + +/** + * next_dirty_cnode - find next dirty cnode. + * @cnode: cnode from which to begin searching + * + * This function returns the next dirty cnode or %NULL if there is not one. + */ +static struct ubifs_cnode *next_dirty_cnode(struct ubifs_cnode *cnode) +{ + struct ubifs_nnode *nnode; + int i; + + ubifs_assert(cnode); + nnode = cnode->parent; + if (!nnode) + return NULL; + for (i = cnode->iip + 1; i < UBIFS_LPT_FANOUT; i++) { + cnode = nnode->nbranch[i].cnode; + if (cnode && test_bit(DIRTY_CNODE, &cnode->flags)) { + if (cnode->level == 0) + return cnode; /* cnode is a pnode */ + /* cnode is a nnode */ + return first_dirty_cnode((struct ubifs_nnode *)cnode); + } + } + return (struct ubifs_cnode *)nnode; +} + +/** + * get_cnodes_to_commit - create list of dirty cnodes to commit. + * @c: UBIFS file-system description object + * + * This function returns the number of cnodes to commit. + */ +static int get_cnodes_to_commit(struct ubifs_info *c) +{ + struct ubifs_cnode *cnode, *cnext; + int cnt = 0; + + if (!c->nroot) + return 0; + + if (!test_bit(DIRTY_CNODE, &c->nroot->flags)) + return 0; + + c->lpt_cnext = first_dirty_cnode(c->nroot); + cnode = c->lpt_cnext; + if (!cnode) + return 0; + cnt += 1; + while (1) { + ubifs_assert(!test_bit(COW_CNODE, &cnode->flags)); + __set_bit(COW_CNODE, &cnode->flags); + cnext = next_dirty_cnode(cnode); + if (!cnext) { + cnode->cnext = c->lpt_cnext; + break; + } + cnode->cnext = cnext; + cnode = cnext; + cnt += 1; + } + dbg_cmt("committing %d cnodes", cnt); + dbg_lp("committing %d cnodes", cnt); + ubifs_assert(cnt == c->dirty_nn_cnt + c->dirty_pn_cnt); + return cnt; +} + +/** + * upd_ltab - update LPT LEB properties. + * @c: UBIFS file-system description object + * @lnum: LEB number + * @free: amount of free space + * @dirty: amount of dirty space to add + */ +static void upd_ltab(struct ubifs_info *c, int lnum, int free, int dirty) +{ + dbg_lp("LEB %d free %d dirty %d to %d +%d", + lnum, c->ltab[lnum - c->lpt_first].free, + c->ltab[lnum - c->lpt_first].dirty, free, dirty); + ubifs_assert(lnum >= c->lpt_first && lnum <= c->lpt_last); + c->ltab[lnum - c->lpt_first].free = free; + c->ltab[lnum - c->lpt_first].dirty += dirty; +} + +/** + * alloc_lpt_leb - allocate an LPT LEB that is empty. + * @c: UBIFS file-system description object + * @lnum: LEB number is passed and returned here + * + * This function finds the next empty LEB in the ltab starting from @lnum. If a + * an empty LEB is found it is returned in @lnum and the function returns %0. + * Otherwise the function returns -ENOSPC. Note however, that LPT is designed + * never to run out of space. + */ +static int alloc_lpt_leb(struct ubifs_info *c, int *lnum) +{ + int i, n; + + n = *lnum - c->lpt_first + 1; + for (i = n; i < c->lpt_lebs; i++) { + if (c->ltab[i].tgc || c->ltab[i].cmt) + continue; + if (c->ltab[i].free == c->leb_size) { + c->ltab[i].cmt = 1; + *lnum = i + c->lpt_first; + return 0; + } + } + + for (i = 0; i < n; i++) { + if (c->ltab[i].tgc || c->ltab[i].cmt) + continue; + if (c->ltab[i].free == c->leb_size) { + c->ltab[i].cmt = 1; + *lnum = i + c->lpt_first; + return 0; + } + } + return -ENOSPC; +} + +/** + * layout_cnodes - layout cnodes for commit. + * @c: UBIFS file-system description object + * + * This function returns %0 on success and a negative error code on failure. + */ +static int layout_cnodes(struct ubifs_info *c) +{ + int lnum, offs, len, alen, done_lsave, done_ltab, err; + struct ubifs_cnode *cnode; + + err = dbg_chk_lpt_sz(c, 0, 0); + if (err) + return err; + cnode = c->lpt_cnext; + if (!cnode) + return 0; + lnum = c->nhead_lnum; + offs = c->nhead_offs; + /* Try to place lsave and ltab nicely */ + done_lsave = !c->big_lpt; + done_ltab = 0; + if (!done_lsave && offs + c->lsave_sz <= c->leb_size) { + done_lsave = 1; + c->lsave_lnum = lnum; + c->lsave_offs = offs; + offs += c->lsave_sz; + dbg_chk_lpt_sz(c, 1, c->lsave_sz); + } + + if (offs + c->ltab_sz <= c->leb_size) { + done_ltab = 1; + c->ltab_lnum = lnum; + c->ltab_offs = offs; + offs += c->ltab_sz; + dbg_chk_lpt_sz(c, 1, c->ltab_sz); + } + + do { + if (cnode->level) { + len = c->nnode_sz; + c->dirty_nn_cnt -= 1; + } else { + len = c->pnode_sz; + c->dirty_pn_cnt -= 1; + } + while (offs + len > c->leb_size) { + alen = ALIGN(offs, c->min_io_size); + upd_ltab(c, lnum, c->leb_size - alen, alen - offs); + dbg_chk_lpt_sz(c, 2, c->leb_size - offs); + err = alloc_lpt_leb(c, &lnum); + if (err) + goto no_space; + offs = 0; + ubifs_assert(lnum >= c->lpt_first && + lnum <= c->lpt_last); + /* Try to place lsave and ltab nicely */ + if (!done_lsave) { + done_lsave = 1; + c->lsave_lnum = lnum; + c->lsave_offs = offs; + offs += c->lsave_sz; + dbg_chk_lpt_sz(c, 1, c->lsave_sz); + continue; + } + if (!done_ltab) { + done_ltab = 1; + c->ltab_lnum = lnum; + c->ltab_offs = offs; + offs += c->ltab_sz; + dbg_chk_lpt_sz(c, 1, c->ltab_sz); + continue; + } + break; + } + if (cnode->parent) { + cnode->parent->nbranch[cnode->iip].lnum = lnum; + cnode->parent->nbranch[cnode->iip].offs = offs; + } else { + c->lpt_lnum = lnum; + c->lpt_offs = offs; + } + offs += len; + dbg_chk_lpt_sz(c, 1, len); + cnode = cnode->cnext; + } while (cnode && cnode != c->lpt_cnext); + + /* Make sure to place LPT's save table */ + if (!done_lsave) { + if (offs + c->lsave_sz > c->leb_size) { + alen = ALIGN(offs, c->min_io_size); + upd_ltab(c, lnum, c->leb_size - alen, alen - offs); + dbg_chk_lpt_sz(c, 2, c->leb_size - offs); + err = alloc_lpt_leb(c, &lnum); + if (err) + goto no_space; + offs = 0; + ubifs_assert(lnum >= c->lpt_first && + lnum <= c->lpt_last); + } + done_lsave = 1; + c->lsave_lnum = lnum; + c->lsave_offs = offs; + offs += c->lsave_sz; + dbg_chk_lpt_sz(c, 1, c->lsave_sz); + } + + /* Make sure to place LPT's own lprops table */ + if (!done_ltab) { + if (offs + c->ltab_sz > c->leb_size) { + alen = ALIGN(offs, c->min_io_size); + upd_ltab(c, lnum, c->leb_size - alen, alen - offs); + dbg_chk_lpt_sz(c, 2, c->leb_size - offs); + err = alloc_lpt_leb(c, &lnum); + if (err) + goto no_space; + offs = 0; + ubifs_assert(lnum >= c->lpt_first && + lnum <= c->lpt_last); + } + done_ltab = 1; + c->ltab_lnum = lnum; + c->ltab_offs = offs; + offs += c->ltab_sz; + dbg_chk_lpt_sz(c, 1, c->ltab_sz); + } + + alen = ALIGN(offs, c->min_io_size); + upd_ltab(c, lnum, c->leb_size - alen, alen - offs); + dbg_chk_lpt_sz(c, 4, alen - offs); + err = dbg_chk_lpt_sz(c, 3, alen); + if (err) + return err; + return 0; + +no_space: + ubifs_err("LPT out of space at LEB %d:%d needing %d, done_ltab %d, done_lsave %d", + lnum, offs, len, done_ltab, done_lsave); + ubifs_dump_lpt_info(c); + ubifs_dump_lpt_lebs(c); + dump_stack(); + return err; +} + +#ifndef __UBOOT__ +/** + * realloc_lpt_leb - allocate an LPT LEB that is empty. + * @c: UBIFS file-system description object + * @lnum: LEB number is passed and returned here + * + * This function duplicates exactly the results of the function alloc_lpt_leb. + * It is used during end commit to reallocate the same LEB numbers that were + * allocated by alloc_lpt_leb during start commit. + * + * This function finds the next LEB that was allocated by the alloc_lpt_leb + * function starting from @lnum. If a LEB is found it is returned in @lnum and + * the function returns %0. Otherwise the function returns -ENOSPC. + * Note however, that LPT is designed never to run out of space. + */ +static int realloc_lpt_leb(struct ubifs_info *c, int *lnum) +{ + int i, n; + + n = *lnum - c->lpt_first + 1; + for (i = n; i < c->lpt_lebs; i++) + if (c->ltab[i].cmt) { + c->ltab[i].cmt = 0; + *lnum = i + c->lpt_first; + return 0; + } + + for (i = 0; i < n; i++) + if (c->ltab[i].cmt) { + c->ltab[i].cmt = 0; + *lnum = i + c->lpt_first; + return 0; + } + return -ENOSPC; +} + +/** + * write_cnodes - write cnodes for commit. + * @c: UBIFS file-system description object + * + * This function returns %0 on success and a negative error code on failure. + */ +static int write_cnodes(struct ubifs_info *c) +{ + int lnum, offs, len, from, err, wlen, alen, done_ltab, done_lsave; + struct ubifs_cnode *cnode; + void *buf = c->lpt_buf; + + cnode = c->lpt_cnext; + if (!cnode) + return 0; + lnum = c->nhead_lnum; + offs = c->nhead_offs; + from = offs; + /* Ensure empty LEB is unmapped */ + if (offs == 0) { + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + } + /* Try to place lsave and ltab nicely */ + done_lsave = !c->big_lpt; + done_ltab = 0; + if (!done_lsave && offs + c->lsave_sz <= c->leb_size) { + done_lsave = 1; + ubifs_pack_lsave(c, buf + offs, c->lsave); + offs += c->lsave_sz; + dbg_chk_lpt_sz(c, 1, c->lsave_sz); + } + + if (offs + c->ltab_sz <= c->leb_size) { + done_ltab = 1; + ubifs_pack_ltab(c, buf + offs, c->ltab_cmt); + offs += c->ltab_sz; + dbg_chk_lpt_sz(c, 1, c->ltab_sz); + } + + /* Loop for each cnode */ + do { + if (cnode->level) + len = c->nnode_sz; + else + len = c->pnode_sz; + while (offs + len > c->leb_size) { + wlen = offs - from; + if (wlen) { + alen = ALIGN(wlen, c->min_io_size); + memset(buf + offs, 0xff, alen - wlen); + err = ubifs_leb_write(c, lnum, buf + from, from, + alen); + if (err) + return err; + } + dbg_chk_lpt_sz(c, 2, c->leb_size - offs); + err = realloc_lpt_leb(c, &lnum); + if (err) + goto no_space; + offs = from = 0; + ubifs_assert(lnum >= c->lpt_first && + lnum <= c->lpt_last); + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + /* Try to place lsave and ltab nicely */ + if (!done_lsave) { + done_lsave = 1; + ubifs_pack_lsave(c, buf + offs, c->lsave); + offs += c->lsave_sz; + dbg_chk_lpt_sz(c, 1, c->lsave_sz); + continue; + } + if (!done_ltab) { + done_ltab = 1; + ubifs_pack_ltab(c, buf + offs, c->ltab_cmt); + offs += c->ltab_sz; + dbg_chk_lpt_sz(c, 1, c->ltab_sz); + continue; + } + break; + } + if (cnode->level) + ubifs_pack_nnode(c, buf + offs, + (struct ubifs_nnode *)cnode); + else + ubifs_pack_pnode(c, buf + offs, + (struct ubifs_pnode *)cnode); + /* + * The reason for the barriers is the same as in case of TNC. + * See comment in 'write_index()'. 'dirty_cow_nnode()' and + * 'dirty_cow_pnode()' are the functions for which this is + * important. + */ + clear_bit(DIRTY_CNODE, &cnode->flags); + smp_mb__before_clear_bit(); + clear_bit(COW_CNODE, &cnode->flags); + smp_mb__after_clear_bit(); + offs += len; + dbg_chk_lpt_sz(c, 1, len); + cnode = cnode->cnext; + } while (cnode && cnode != c->lpt_cnext); + + /* Make sure to place LPT's save table */ + if (!done_lsave) { + if (offs + c->lsave_sz > c->leb_size) { + wlen = offs - from; + alen = ALIGN(wlen, c->min_io_size); + memset(buf + offs, 0xff, alen - wlen); + err = ubifs_leb_write(c, lnum, buf + from, from, alen); + if (err) + return err; + dbg_chk_lpt_sz(c, 2, c->leb_size - offs); + err = realloc_lpt_leb(c, &lnum); + if (err) + goto no_space; + offs = from = 0; + ubifs_assert(lnum >= c->lpt_first && + lnum <= c->lpt_last); + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + } + done_lsave = 1; + ubifs_pack_lsave(c, buf + offs, c->lsave); + offs += c->lsave_sz; + dbg_chk_lpt_sz(c, 1, c->lsave_sz); + } + + /* Make sure to place LPT's own lprops table */ + if (!done_ltab) { + if (offs + c->ltab_sz > c->leb_size) { + wlen = offs - from; + alen = ALIGN(wlen, c->min_io_size); + memset(buf + offs, 0xff, alen - wlen); + err = ubifs_leb_write(c, lnum, buf + from, from, alen); + if (err) + return err; + dbg_chk_lpt_sz(c, 2, c->leb_size - offs); + err = realloc_lpt_leb(c, &lnum); + if (err) + goto no_space; + offs = from = 0; + ubifs_assert(lnum >= c->lpt_first && + lnum <= c->lpt_last); + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + } + done_ltab = 1; + ubifs_pack_ltab(c, buf + offs, c->ltab_cmt); + offs += c->ltab_sz; + dbg_chk_lpt_sz(c, 1, c->ltab_sz); + } + + /* Write remaining data in buffer */ + wlen = offs - from; + alen = ALIGN(wlen, c->min_io_size); + memset(buf + offs, 0xff, alen - wlen); + err = ubifs_leb_write(c, lnum, buf + from, from, alen); + if (err) + return err; + + dbg_chk_lpt_sz(c, 4, alen - wlen); + err = dbg_chk_lpt_sz(c, 3, ALIGN(offs, c->min_io_size)); + if (err) + return err; + + c->nhead_lnum = lnum; + c->nhead_offs = ALIGN(offs, c->min_io_size); + + dbg_lp("LPT root is at %d:%d", c->lpt_lnum, c->lpt_offs); + dbg_lp("LPT head is at %d:%d", c->nhead_lnum, c->nhead_offs); + dbg_lp("LPT ltab is at %d:%d", c->ltab_lnum, c->ltab_offs); + if (c->big_lpt) + dbg_lp("LPT lsave is at %d:%d", c->lsave_lnum, c->lsave_offs); + + return 0; + +no_space: + ubifs_err("LPT out of space mismatch at LEB %d:%d needing %d, done_ltab %d, done_lsave %d", + lnum, offs, len, done_ltab, done_lsave); + ubifs_dump_lpt_info(c); + ubifs_dump_lpt_lebs(c); + dump_stack(); + return err; +} +#endif + +/** + * next_pnode_to_dirty - find next pnode to dirty. + * @c: UBIFS file-system description object + * @pnode: pnode + * + * This function returns the next pnode to dirty or %NULL if there are no more + * pnodes. Note that pnodes that have never been written (lnum == 0) are + * skipped. + */ +static struct ubifs_pnode *next_pnode_to_dirty(struct ubifs_info *c, + struct ubifs_pnode *pnode) +{ + struct ubifs_nnode *nnode; + int iip; + + /* Try to go right */ + nnode = pnode->parent; + for (iip = pnode->iip + 1; iip < UBIFS_LPT_FANOUT; iip++) { + if (nnode->nbranch[iip].lnum) + return ubifs_get_pnode(c, nnode, iip); + } + + /* Go up while can't go right */ + do { + iip = nnode->iip + 1; + nnode = nnode->parent; + if (!nnode) + return NULL; + for (; iip < UBIFS_LPT_FANOUT; iip++) { + if (nnode->nbranch[iip].lnum) + break; + } + } while (iip >= UBIFS_LPT_FANOUT); + + /* Go right */ + nnode = ubifs_get_nnode(c, nnode, iip); + if (IS_ERR(nnode)) + return (void *)nnode; + + /* Go down to level 1 */ + while (nnode->level > 1) { + for (iip = 0; iip < UBIFS_LPT_FANOUT; iip++) { + if (nnode->nbranch[iip].lnum) + break; + } + if (iip >= UBIFS_LPT_FANOUT) { + /* + * Should not happen, but we need to keep going + * if it does. + */ + iip = 0; + } + nnode = ubifs_get_nnode(c, nnode, iip); + if (IS_ERR(nnode)) + return (void *)nnode; + } + + for (iip = 0; iip < UBIFS_LPT_FANOUT; iip++) + if (nnode->nbranch[iip].lnum) + break; + if (iip >= UBIFS_LPT_FANOUT) + /* Should not happen, but we need to keep going if it does */ + iip = 0; + return ubifs_get_pnode(c, nnode, iip); +} + +/** + * pnode_lookup - lookup a pnode in the LPT. + * @c: UBIFS file-system description object + * @i: pnode number (0 to main_lebs - 1) + * + * This function returns a pointer to the pnode on success or a negative + * error code on failure. + */ +static struct ubifs_pnode *pnode_lookup(struct ubifs_info *c, int i) +{ + int err, h, iip, shft; + struct ubifs_nnode *nnode; + + if (!c->nroot) { + err = ubifs_read_nnode(c, NULL, 0); + if (err) + return ERR_PTR(err); + } + i <<= UBIFS_LPT_FANOUT_SHIFT; + nnode = c->nroot; + shft = c->lpt_hght * UBIFS_LPT_FANOUT_SHIFT; + for (h = 1; h < c->lpt_hght; h++) { + iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); + shft -= UBIFS_LPT_FANOUT_SHIFT; + nnode = ubifs_get_nnode(c, nnode, iip); + if (IS_ERR(nnode)) + return ERR_CAST(nnode); + } + iip = ((i >> shft) & (UBIFS_LPT_FANOUT - 1)); + return ubifs_get_pnode(c, nnode, iip); +} + +/** + * add_pnode_dirt - add dirty space to LPT LEB properties. + * @c: UBIFS file-system description object + * @pnode: pnode for which to add dirt + */ +static void add_pnode_dirt(struct ubifs_info *c, struct ubifs_pnode *pnode) +{ + ubifs_add_lpt_dirt(c, pnode->parent->nbranch[pnode->iip].lnum, + c->pnode_sz); +} + +/** + * do_make_pnode_dirty - mark a pnode dirty. + * @c: UBIFS file-system description object + * @pnode: pnode to mark dirty + */ +static void do_make_pnode_dirty(struct ubifs_info *c, struct ubifs_pnode *pnode) +{ + /* Assumes cnext list is empty i.e. not called during commit */ + if (!test_and_set_bit(DIRTY_CNODE, &pnode->flags)) { + struct ubifs_nnode *nnode; + + c->dirty_pn_cnt += 1; + add_pnode_dirt(c, pnode); + /* Mark parent and ancestors dirty too */ + nnode = pnode->parent; + while (nnode) { + if (!test_and_set_bit(DIRTY_CNODE, &nnode->flags)) { + c->dirty_nn_cnt += 1; + ubifs_add_nnode_dirt(c, nnode); + nnode = nnode->parent; + } else + break; + } + } +} + +/** + * make_tree_dirty - mark the entire LEB properties tree dirty. + * @c: UBIFS file-system description object + * + * This function is used by the "small" LPT model to cause the entire LEB + * properties tree to be written. The "small" LPT model does not use LPT + * garbage collection because it is more efficient to write the entire tree + * (because it is small). + * + * This function returns %0 on success and a negative error code on failure. + */ +static int make_tree_dirty(struct ubifs_info *c) +{ + struct ubifs_pnode *pnode; + + pnode = pnode_lookup(c, 0); + if (IS_ERR(pnode)) + return PTR_ERR(pnode); + + while (pnode) { + do_make_pnode_dirty(c, pnode); + pnode = next_pnode_to_dirty(c, pnode); + if (IS_ERR(pnode)) + return PTR_ERR(pnode); + } + return 0; +} + +/** + * need_write_all - determine if the LPT area is running out of free space. + * @c: UBIFS file-system description object + * + * This function returns %1 if the LPT area is running out of free space and %0 + * if it is not. + */ +static int need_write_all(struct ubifs_info *c) +{ + long long free = 0; + int i; + + for (i = 0; i < c->lpt_lebs; i++) { + if (i + c->lpt_first == c->nhead_lnum) + free += c->leb_size - c->nhead_offs; + else if (c->ltab[i].free == c->leb_size) + free += c->leb_size; + else if (c->ltab[i].free + c->ltab[i].dirty == c->leb_size) + free += c->leb_size; + } + /* Less than twice the size left */ + if (free <= c->lpt_sz * 2) + return 1; + return 0; +} + +/** + * lpt_tgc_start - start trivial garbage collection of LPT LEBs. + * @c: UBIFS file-system description object + * + * LPT trivial garbage collection is where a LPT LEB contains only dirty and + * free space and so may be reused as soon as the next commit is completed. + * This function is called during start commit to mark LPT LEBs for trivial GC. + */ +static void lpt_tgc_start(struct ubifs_info *c) +{ + int i; + + for (i = 0; i < c->lpt_lebs; i++) { + if (i + c->lpt_first == c->nhead_lnum) + continue; + if (c->ltab[i].dirty > 0 && + c->ltab[i].free + c->ltab[i].dirty == c->leb_size) { + c->ltab[i].tgc = 1; + c->ltab[i].free = c->leb_size; + c->ltab[i].dirty = 0; + dbg_lp("LEB %d", i + c->lpt_first); + } + } +} + +/** + * lpt_tgc_end - end trivial garbage collection of LPT LEBs. + * @c: UBIFS file-system description object + * + * LPT trivial garbage collection is where a LPT LEB contains only dirty and + * free space and so may be reused as soon as the next commit is completed. + * This function is called after the commit is completed (master node has been + * written) and un-maps LPT LEBs that were marked for trivial GC. + */ +static int lpt_tgc_end(struct ubifs_info *c) +{ + int i, err; + + for (i = 0; i < c->lpt_lebs; i++) + if (c->ltab[i].tgc) { + err = ubifs_leb_unmap(c, i + c->lpt_first); + if (err) + return err; + c->ltab[i].tgc = 0; + dbg_lp("LEB %d", i + c->lpt_first); + } + return 0; +} + +/** + * populate_lsave - fill the lsave array with important LEB numbers. + * @c: the UBIFS file-system description object + * + * This function is only called for the "big" model. It records a small number + * of LEB numbers of important LEBs. Important LEBs are ones that are (from + * most important to least important): empty, freeable, freeable index, dirty + * index, dirty or free. Upon mount, we read this list of LEB numbers and bring + * their pnodes into memory. That will stop us from having to scan the LPT + * straight away. For the "small" model we assume that scanning the LPT is no + * big deal. + */ +static void populate_lsave(struct ubifs_info *c) +{ + struct ubifs_lprops *lprops; + struct ubifs_lpt_heap *heap; + int i, cnt = 0; + + ubifs_assert(c->big_lpt); + if (!(c->lpt_drty_flgs & LSAVE_DIRTY)) { + c->lpt_drty_flgs |= LSAVE_DIRTY; + ubifs_add_lpt_dirt(c, c->lsave_lnum, c->lsave_sz); + } + +#ifndef __UBOOT__ + if (dbg_populate_lsave(c)) + return; +#endif + + list_for_each_entry(lprops, &c->empty_list, list) { + c->lsave[cnt++] = lprops->lnum; + if (cnt >= c->lsave_cnt) + return; + } + list_for_each_entry(lprops, &c->freeable_list, list) { + c->lsave[cnt++] = lprops->lnum; + if (cnt >= c->lsave_cnt) + return; + } + list_for_each_entry(lprops, &c->frdi_idx_list, list) { + c->lsave[cnt++] = lprops->lnum; + if (cnt >= c->lsave_cnt) + return; + } + heap = &c->lpt_heap[LPROPS_DIRTY_IDX - 1]; + for (i = 0; i < heap->cnt; i++) { + c->lsave[cnt++] = heap->arr[i]->lnum; + if (cnt >= c->lsave_cnt) + return; + } + heap = &c->lpt_heap[LPROPS_DIRTY - 1]; + for (i = 0; i < heap->cnt; i++) { + c->lsave[cnt++] = heap->arr[i]->lnum; + if (cnt >= c->lsave_cnt) + return; + } + heap = &c->lpt_heap[LPROPS_FREE - 1]; + for (i = 0; i < heap->cnt; i++) { + c->lsave[cnt++] = heap->arr[i]->lnum; + if (cnt >= c->lsave_cnt) + return; + } + /* Fill it up completely */ + while (cnt < c->lsave_cnt) + c->lsave[cnt++] = c->main_first; +} + +/** + * nnode_lookup - lookup a nnode in the LPT. + * @c: UBIFS file-system description object + * @i: nnode number + * + * This function returns a pointer to the nnode on success or a negative + * error code on failure. + */ +static struct ubifs_nnode *nnode_lookup(struct ubifs_info *c, int i) +{ + int err, iip; + struct ubifs_nnode *nnode; + + if (!c->nroot) { + err = ubifs_read_nnode(c, NULL, 0); + if (err) + return ERR_PTR(err); + } + nnode = c->nroot; + while (1) { + iip = i & (UBIFS_LPT_FANOUT - 1); + i >>= UBIFS_LPT_FANOUT_SHIFT; + if (!i) + break; + nnode = ubifs_get_nnode(c, nnode, iip); + if (IS_ERR(nnode)) + return nnode; + } + return nnode; +} + +/** + * make_nnode_dirty - find a nnode and, if found, make it dirty. + * @c: UBIFS file-system description object + * @node_num: nnode number of nnode to make dirty + * @lnum: LEB number where nnode was written + * @offs: offset where nnode was written + * + * This function is used by LPT garbage collection. LPT garbage collection is + * used only for the "big" LPT model (c->big_lpt == 1). Garbage collection + * simply involves marking all the nodes in the LEB being garbage-collected as + * dirty. The dirty nodes are written next commit, after which the LEB is free + * to be reused. + * + * This function returns %0 on success and a negative error code on failure. + */ +static int make_nnode_dirty(struct ubifs_info *c, int node_num, int lnum, + int offs) +{ + struct ubifs_nnode *nnode; + + nnode = nnode_lookup(c, node_num); + if (IS_ERR(nnode)) + return PTR_ERR(nnode); + if (nnode->parent) { + struct ubifs_nbranch *branch; + + branch = &nnode->parent->nbranch[nnode->iip]; + if (branch->lnum != lnum || branch->offs != offs) + return 0; /* nnode is obsolete */ + } else if (c->lpt_lnum != lnum || c->lpt_offs != offs) + return 0; /* nnode is obsolete */ + /* Assumes cnext list is empty i.e. not called during commit */ + if (!test_and_set_bit(DIRTY_CNODE, &nnode->flags)) { + c->dirty_nn_cnt += 1; + ubifs_add_nnode_dirt(c, nnode); + /* Mark parent and ancestors dirty too */ + nnode = nnode->parent; + while (nnode) { + if (!test_and_set_bit(DIRTY_CNODE, &nnode->flags)) { + c->dirty_nn_cnt += 1; + ubifs_add_nnode_dirt(c, nnode); + nnode = nnode->parent; + } else + break; + } + } + return 0; +} + +/** + * make_pnode_dirty - find a pnode and, if found, make it dirty. + * @c: UBIFS file-system description object + * @node_num: pnode number of pnode to make dirty + * @lnum: LEB number where pnode was written + * @offs: offset where pnode was written + * + * This function is used by LPT garbage collection. LPT garbage collection is + * used only for the "big" LPT model (c->big_lpt == 1). Garbage collection + * simply involves marking all the nodes in the LEB being garbage-collected as + * dirty. The dirty nodes are written next commit, after which the LEB is free + * to be reused. + * + * This function returns %0 on success and a negative error code on failure. + */ +static int make_pnode_dirty(struct ubifs_info *c, int node_num, int lnum, + int offs) +{ + struct ubifs_pnode *pnode; + struct ubifs_nbranch *branch; + + pnode = pnode_lookup(c, node_num); + if (IS_ERR(pnode)) + return PTR_ERR(pnode); + branch = &pnode->parent->nbranch[pnode->iip]; + if (branch->lnum != lnum || branch->offs != offs) + return 0; + do_make_pnode_dirty(c, pnode); + return 0; +} + +/** + * make_ltab_dirty - make ltab node dirty. + * @c: UBIFS file-system description object + * @lnum: LEB number where ltab was written + * @offs: offset where ltab was written + * + * This function is used by LPT garbage collection. LPT garbage collection is + * used only for the "big" LPT model (c->big_lpt == 1). Garbage collection + * simply involves marking all the nodes in the LEB being garbage-collected as + * dirty. The dirty nodes are written next commit, after which the LEB is free + * to be reused. + * + * This function returns %0 on success and a negative error code on failure. + */ +static int make_ltab_dirty(struct ubifs_info *c, int lnum, int offs) +{ + if (lnum != c->ltab_lnum || offs != c->ltab_offs) + return 0; /* This ltab node is obsolete */ + if (!(c->lpt_drty_flgs & LTAB_DIRTY)) { + c->lpt_drty_flgs |= LTAB_DIRTY; + ubifs_add_lpt_dirt(c, c->ltab_lnum, c->ltab_sz); + } + return 0; +} + +/** + * make_lsave_dirty - make lsave node dirty. + * @c: UBIFS file-system description object + * @lnum: LEB number where lsave was written + * @offs: offset where lsave was written + * + * This function is used by LPT garbage collection. LPT garbage collection is + * used only for the "big" LPT model (c->big_lpt == 1). Garbage collection + * simply involves marking all the nodes in the LEB being garbage-collected as + * dirty. The dirty nodes are written next commit, after which the LEB is free + * to be reused. + * + * This function returns %0 on success and a negative error code on failure. + */ +static int make_lsave_dirty(struct ubifs_info *c, int lnum, int offs) +{ + if (lnum != c->lsave_lnum || offs != c->lsave_offs) + return 0; /* This lsave node is obsolete */ + if (!(c->lpt_drty_flgs & LSAVE_DIRTY)) { + c->lpt_drty_flgs |= LSAVE_DIRTY; + ubifs_add_lpt_dirt(c, c->lsave_lnum, c->lsave_sz); + } + return 0; +} + +/** + * make_node_dirty - make node dirty. + * @c: UBIFS file-system description object + * @node_type: LPT node type + * @node_num: node number + * @lnum: LEB number where node was written + * @offs: offset where node was written + * + * This function is used by LPT garbage collection. LPT garbage collection is + * used only for the "big" LPT model (c->big_lpt == 1). Garbage collection + * simply involves marking all the nodes in the LEB being garbage-collected as + * dirty. The dirty nodes are written next commit, after which the LEB is free + * to be reused. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * This function returns %0 on success and a negative error code on failure. + */ +static int make_node_dirty(struct ubifs_info *c, int node_type, int node_num, + int lnum, int offs) +{ + switch (node_type) { + case UBIFS_LPT_NNODE: + return make_nnode_dirty(c, node_num, lnum, offs); + case UBIFS_LPT_PNODE: + return make_pnode_dirty(c, node_num, lnum, offs); + case UBIFS_LPT_LTAB: + return make_ltab_dirty(c, lnum, offs); + case UBIFS_LPT_LSAVE: + return make_lsave_dirty(c, lnum, offs); + } + return -EINVAL; +} + +/** + * get_lpt_node_len - return the length of a node based on its type. + * @c: UBIFS file-system description object + * @node_type: LPT node type + */ +static int get_lpt_node_len(const struct ubifs_info *c, int node_type) +{ + switch (node_type) { + case UBIFS_LPT_NNODE: + return c->nnode_sz; + case UBIFS_LPT_PNODE: + return c->pnode_sz; + case UBIFS_LPT_LTAB: + return c->ltab_sz; + case UBIFS_LPT_LSAVE: + return c->lsave_sz; + } + return 0; +} + +/** + * get_pad_len - return the length of padding in a buffer. + * @c: UBIFS file-system description object + * @buf: buffer + * @len: length of buffer + */ +static int get_pad_len(const struct ubifs_info *c, uint8_t *buf, int len) +{ + int offs, pad_len; + + if (c->min_io_size == 1) + return 0; + offs = c->leb_size - len; + pad_len = ALIGN(offs, c->min_io_size) - offs; + return pad_len; +} + +/** + * get_lpt_node_type - return type (and node number) of a node in a buffer. + * @c: UBIFS file-system description object + * @buf: buffer + * @node_num: node number is returned here + */ +static int get_lpt_node_type(const struct ubifs_info *c, uint8_t *buf, + int *node_num) +{ + uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES; + int pos = 0, node_type; + + node_type = ubifs_unpack_bits(&addr, &pos, UBIFS_LPT_TYPE_BITS); + *node_num = ubifs_unpack_bits(&addr, &pos, c->pcnt_bits); + return node_type; +} + +/** + * is_a_node - determine if a buffer contains a node. + * @c: UBIFS file-system description object + * @buf: buffer + * @len: length of buffer * - * Authors: Adrian Hunter - * Artem Bityutskiy (Битюцкий Артём) + * This function returns %1 if the buffer contains a node or %0 if it does not. */ +static int is_a_node(const struct ubifs_info *c, uint8_t *buf, int len) +{ + uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES; + int pos = 0, node_type, node_len; + uint16_t crc, calc_crc; -/* - * This file implements commit-related functionality of the LEB properties - * subsystem. + if (len < UBIFS_LPT_CRC_BYTES + (UBIFS_LPT_TYPE_BITS + 7) / 8) + return 0; + node_type = ubifs_unpack_bits(&addr, &pos, UBIFS_LPT_TYPE_BITS); + if (node_type == UBIFS_LPT_NOT_A_NODE) + return 0; + node_len = get_lpt_node_len(c, node_type); + if (!node_len || node_len > len) + return 0; + pos = 0; + addr = buf; + crc = ubifs_unpack_bits(&addr, &pos, UBIFS_LPT_CRC_BITS); + calc_crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, + node_len - UBIFS_LPT_CRC_BYTES); + if (crc != calc_crc) + return 0; + return 1; +} + +/** + * lpt_gc_lnum - garbage collect a LPT LEB. + * @c: UBIFS file-system description object + * @lnum: LEB number to garbage collect + * + * LPT garbage collection is used only for the "big" LPT model + * (c->big_lpt == 1). Garbage collection simply involves marking all the nodes + * in the LEB being garbage-collected as dirty. The dirty nodes are written + * next commit, after which the LEB is free to be reused. + * + * This function returns %0 on success and a negative error code on failure. */ +static int lpt_gc_lnum(struct ubifs_info *c, int lnum) +{ + int err, len = c->leb_size, node_type, node_num, node_len, offs; + void *buf = c->lpt_buf; -#include "crc16.h" -#include "ubifs.h" + dbg_lp("LEB %d", lnum); + + err = ubifs_leb_read(c, lnum, buf, 0, c->leb_size, 1); + if (err) + return err; + + while (1) { + if (!is_a_node(c, buf, len)) { + int pad_len; + + pad_len = get_pad_len(c, buf, len); + if (pad_len) { + buf += pad_len; + len -= pad_len; + continue; + } + return 0; + } + node_type = get_lpt_node_type(c, buf, &node_num); + node_len = get_lpt_node_len(c, node_type); + offs = c->leb_size - len; + ubifs_assert(node_len != 0); + mutex_lock(&c->lp_mutex); + err = make_node_dirty(c, node_type, node_num, lnum, offs); + mutex_unlock(&c->lp_mutex); + if (err) + return err; + buf += node_len; + len -= node_len; + } + return 0; +} + +/** + * lpt_gc - LPT garbage collection. + * @c: UBIFS file-system description object + * + * Select a LPT LEB for LPT garbage collection and call 'lpt_gc_lnum()'. + * Returns %0 on success and a negative error code on failure. + */ +static int lpt_gc(struct ubifs_info *c) +{ + int i, lnum = -1, dirty = 0; + + mutex_lock(&c->lp_mutex); + for (i = 0; i < c->lpt_lebs; i++) { + ubifs_assert(!c->ltab[i].tgc); + if (i + c->lpt_first == c->nhead_lnum || + c->ltab[i].free + c->ltab[i].dirty == c->leb_size) + continue; + if (c->ltab[i].dirty > dirty) { + dirty = c->ltab[i].dirty; + lnum = i + c->lpt_first; + } + } + mutex_unlock(&c->lp_mutex); + if (lnum == -1) + return -ENOSPC; + return lpt_gc_lnum(c, lnum); +} + +/** + * ubifs_lpt_start_commit - UBIFS commit starts. + * @c: the UBIFS file-system description object + * + * This function has to be called when UBIFS starts the commit operation. + * This function "freezes" all currently dirty LEB properties and does not + * change them anymore. Further changes are saved and tracked separately + * because they are not part of this commit. This function returns zero in case + * of success and a negative error code in case of failure. + */ +int ubifs_lpt_start_commit(struct ubifs_info *c) +{ + int err, cnt; + + dbg_lp(""); + + mutex_lock(&c->lp_mutex); + err = dbg_chk_lpt_free_spc(c); + if (err) + goto out; + err = dbg_check_ltab(c); + if (err) + goto out; + + if (c->check_lpt_free) { + /* + * We ensure there is enough free space in + * ubifs_lpt_post_commit() by marking nodes dirty. That + * information is lost when we unmount, so we also need + * to check free space once after mounting also. + */ + c->check_lpt_free = 0; + while (need_write_all(c)) { + mutex_unlock(&c->lp_mutex); + err = lpt_gc(c); + if (err) + return err; + mutex_lock(&c->lp_mutex); + } + } + + lpt_tgc_start(c); + + if (!c->dirty_pn_cnt) { + dbg_cmt("no cnodes to commit"); + err = 0; + goto out; + } + + if (!c->big_lpt && need_write_all(c)) { + /* If needed, write everything */ + err = make_tree_dirty(c); + if (err) + goto out; + lpt_tgc_start(c); + } + + if (c->big_lpt) + populate_lsave(c); + + cnt = get_cnodes_to_commit(c); + ubifs_assert(cnt != 0); + + err = layout_cnodes(c); + if (err) + goto out; + + /* Copy the LPT's own lprops for end commit to write */ + memcpy(c->ltab_cmt, c->ltab, + sizeof(struct ubifs_lpt_lprops) * c->lpt_lebs); + c->lpt_drty_flgs &= ~(LTAB_DIRTY | LSAVE_DIRTY); + +out: + mutex_unlock(&c->lp_mutex); + return err; +} /** * free_obsolete_cnodes - free obsolete cnodes for commit end. @@ -50,6 +1313,65 @@ static void free_obsolete_cnodes(struct ubifs_info *c) c->lpt_cnext = NULL; } +#ifndef __UBOOT__ +/** + * ubifs_lpt_end_commit - finish the commit operation. + * @c: the UBIFS file-system description object + * + * This function has to be called when the commit operation finishes. It + * flushes the changes which were "frozen" by 'ubifs_lprops_start_commit()' to + * the media. Returns zero in case of success and a negative error code in case + * of failure. + */ +int ubifs_lpt_end_commit(struct ubifs_info *c) +{ + int err; + + dbg_lp(""); + + if (!c->lpt_cnext) + return 0; + + err = write_cnodes(c); + if (err) + return err; + + mutex_lock(&c->lp_mutex); + free_obsolete_cnodes(c); + mutex_unlock(&c->lp_mutex); + + return 0; +} +#endif + +/** + * ubifs_lpt_post_commit - post commit LPT trivial GC and LPT GC. + * @c: UBIFS file-system description object + * + * LPT trivial GC is completed after a commit. Also LPT GC is done after a + * commit for the "big" LPT model. + */ +int ubifs_lpt_post_commit(struct ubifs_info *c) +{ + int err; + + mutex_lock(&c->lp_mutex); + err = lpt_tgc_end(c); + if (err) + goto out; + if (c->big_lpt) + while (need_write_all(c)) { + mutex_unlock(&c->lp_mutex); + err = lpt_gc(c); + if (err) + return err; + mutex_lock(&c->lp_mutex); + } +out: + mutex_unlock(&c->lp_mutex); + return err; +} + /** * first_nnode - find the first nnode in memory. * @c: UBIFS file-system description object @@ -169,3 +1491,549 @@ void ubifs_lpt_free(struct ubifs_info *c, int wr_only) vfree(c->ltab); kfree(c->lpt_nod_buf); } + +#ifndef __UBOOT__ +/* + * Everything below is related to debugging. + */ + +/** + * dbg_is_all_ff - determine if a buffer contains only 0xFF bytes. + * @buf: buffer + * @len: buffer length + */ +static int dbg_is_all_ff(uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + if (buf[i] != 0xff) + return 0; + return 1; +} + +/** + * dbg_is_nnode_dirty - determine if a nnode is dirty. + * @c: the UBIFS file-system description object + * @lnum: LEB number where nnode was written + * @offs: offset where nnode was written + */ +static int dbg_is_nnode_dirty(struct ubifs_info *c, int lnum, int offs) +{ + struct ubifs_nnode *nnode; + int hght; + + /* Entire tree is in memory so first_nnode / next_nnode are OK */ + nnode = first_nnode(c, &hght); + for (; nnode; nnode = next_nnode(c, nnode, &hght)) { + struct ubifs_nbranch *branch; + + cond_resched(); + if (nnode->parent) { + branch = &nnode->parent->nbranch[nnode->iip]; + if (branch->lnum != lnum || branch->offs != offs) + continue; + if (test_bit(DIRTY_CNODE, &nnode->flags)) + return 1; + return 0; + } else { + if (c->lpt_lnum != lnum || c->lpt_offs != offs) + continue; + if (test_bit(DIRTY_CNODE, &nnode->flags)) + return 1; + return 0; + } + } + return 1; +} + +/** + * dbg_is_pnode_dirty - determine if a pnode is dirty. + * @c: the UBIFS file-system description object + * @lnum: LEB number where pnode was written + * @offs: offset where pnode was written + */ +static int dbg_is_pnode_dirty(struct ubifs_info *c, int lnum, int offs) +{ + int i, cnt; + + cnt = DIV_ROUND_UP(c->main_lebs, UBIFS_LPT_FANOUT); + for (i = 0; i < cnt; i++) { + struct ubifs_pnode *pnode; + struct ubifs_nbranch *branch; + + cond_resched(); + pnode = pnode_lookup(c, i); + if (IS_ERR(pnode)) + return PTR_ERR(pnode); + branch = &pnode->parent->nbranch[pnode->iip]; + if (branch->lnum != lnum || branch->offs != offs) + continue; + if (test_bit(DIRTY_CNODE, &pnode->flags)) + return 1; + return 0; + } + return 1; +} + +/** + * dbg_is_ltab_dirty - determine if a ltab node is dirty. + * @c: the UBIFS file-system description object + * @lnum: LEB number where ltab node was written + * @offs: offset where ltab node was written + */ +static int dbg_is_ltab_dirty(struct ubifs_info *c, int lnum, int offs) +{ + if (lnum != c->ltab_lnum || offs != c->ltab_offs) + return 1; + return (c->lpt_drty_flgs & LTAB_DIRTY) != 0; +} + +/** + * dbg_is_lsave_dirty - determine if a lsave node is dirty. + * @c: the UBIFS file-system description object + * @lnum: LEB number where lsave node was written + * @offs: offset where lsave node was written + */ +static int dbg_is_lsave_dirty(struct ubifs_info *c, int lnum, int offs) +{ + if (lnum != c->lsave_lnum || offs != c->lsave_offs) + return 1; + return (c->lpt_drty_flgs & LSAVE_DIRTY) != 0; +} + +/** + * dbg_is_node_dirty - determine if a node is dirty. + * @c: the UBIFS file-system description object + * @node_type: node type + * @lnum: LEB number where node was written + * @offs: offset where node was written + */ +static int dbg_is_node_dirty(struct ubifs_info *c, int node_type, int lnum, + int offs) +{ + switch (node_type) { + case UBIFS_LPT_NNODE: + return dbg_is_nnode_dirty(c, lnum, offs); + case UBIFS_LPT_PNODE: + return dbg_is_pnode_dirty(c, lnum, offs); + case UBIFS_LPT_LTAB: + return dbg_is_ltab_dirty(c, lnum, offs); + case UBIFS_LPT_LSAVE: + return dbg_is_lsave_dirty(c, lnum, offs); + } + return 1; +} + +/** + * dbg_check_ltab_lnum - check the ltab for a LPT LEB number. + * @c: the UBIFS file-system description object + * @lnum: LEB number where node was written + * @offs: offset where node was written + * + * This function returns %0 on success and a negative error code on failure. + */ +static int dbg_check_ltab_lnum(struct ubifs_info *c, int lnum) +{ + int err, len = c->leb_size, dirty = 0, node_type, node_num, node_len; + int ret; + void *buf, *p; + + if (!dbg_is_chk_lprops(c)) + return 0; + + buf = p = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); + if (!buf) { + ubifs_err("cannot allocate memory for ltab checking"); + return 0; + } + + dbg_lp("LEB %d", lnum); + + err = ubifs_leb_read(c, lnum, buf, 0, c->leb_size, 1); + if (err) + goto out; + + while (1) { + if (!is_a_node(c, p, len)) { + int i, pad_len; + + pad_len = get_pad_len(c, p, len); + if (pad_len) { + p += pad_len; + len -= pad_len; + dirty += pad_len; + continue; + } + if (!dbg_is_all_ff(p, len)) { + ubifs_err("invalid empty space in LEB %d at %d", + lnum, c->leb_size - len); + err = -EINVAL; + } + i = lnum - c->lpt_first; + if (len != c->ltab[i].free) { + ubifs_err("invalid free space in LEB %d (free %d, expected %d)", + lnum, len, c->ltab[i].free); + err = -EINVAL; + } + if (dirty != c->ltab[i].dirty) { + ubifs_err("invalid dirty space in LEB %d (dirty %d, expected %d)", + lnum, dirty, c->ltab[i].dirty); + err = -EINVAL; + } + goto out; + } + node_type = get_lpt_node_type(c, p, &node_num); + node_len = get_lpt_node_len(c, node_type); + ret = dbg_is_node_dirty(c, node_type, lnum, c->leb_size - len); + if (ret == 1) + dirty += node_len; + p += node_len; + len -= node_len; + } + + err = 0; +out: + vfree(buf); + return err; +} + +/** + * dbg_check_ltab - check the free and dirty space in the ltab. + * @c: the UBIFS file-system description object + * + * This function returns %0 on success and a negative error code on failure. + */ +int dbg_check_ltab(struct ubifs_info *c) +{ + int lnum, err, i, cnt; + + if (!dbg_is_chk_lprops(c)) + return 0; + + /* Bring the entire tree into memory */ + cnt = DIV_ROUND_UP(c->main_lebs, UBIFS_LPT_FANOUT); + for (i = 0; i < cnt; i++) { + struct ubifs_pnode *pnode; + + pnode = pnode_lookup(c, i); + if (IS_ERR(pnode)) + return PTR_ERR(pnode); + cond_resched(); + } + + /* Check nodes */ + err = dbg_check_lpt_nodes(c, (struct ubifs_cnode *)c->nroot, 0, 0); + if (err) + return err; + + /* Check each LEB */ + for (lnum = c->lpt_first; lnum <= c->lpt_last; lnum++) { + err = dbg_check_ltab_lnum(c, lnum); + if (err) { + ubifs_err("failed at LEB %d", lnum); + return err; + } + } + + dbg_lp("succeeded"); + return 0; +} + +/** + * dbg_chk_lpt_free_spc - check LPT free space is enough to write entire LPT. + * @c: the UBIFS file-system description object + * + * This function returns %0 on success and a negative error code on failure. + */ +int dbg_chk_lpt_free_spc(struct ubifs_info *c) +{ + long long free = 0; + int i; + + if (!dbg_is_chk_lprops(c)) + return 0; + + for (i = 0; i < c->lpt_lebs; i++) { + if (c->ltab[i].tgc || c->ltab[i].cmt) + continue; + if (i + c->lpt_first == c->nhead_lnum) + free += c->leb_size - c->nhead_offs; + else if (c->ltab[i].free == c->leb_size) + free += c->leb_size; + } + if (free < c->lpt_sz) { + ubifs_err("LPT space error: free %lld lpt_sz %lld", + free, c->lpt_sz); + ubifs_dump_lpt_info(c); + ubifs_dump_lpt_lebs(c); + dump_stack(); + return -EINVAL; + } + return 0; +} + +/** + * dbg_chk_lpt_sz - check LPT does not write more than LPT size. + * @c: the UBIFS file-system description object + * @action: what to do + * @len: length written + * + * This function returns %0 on success and a negative error code on failure. + * The @action argument may be one of: + * o %0 - LPT debugging checking starts, initialize debugging variables; + * o %1 - wrote an LPT node, increase LPT size by @len bytes; + * o %2 - switched to a different LEB and wasted @len bytes; + * o %3 - check that we've written the right number of bytes. + * o %4 - wasted @len bytes; + */ +int dbg_chk_lpt_sz(struct ubifs_info *c, int action, int len) +{ + struct ubifs_debug_info *d = c->dbg; + long long chk_lpt_sz, lpt_sz; + int err = 0; + + if (!dbg_is_chk_lprops(c)) + return 0; + + switch (action) { + case 0: + d->chk_lpt_sz = 0; + d->chk_lpt_sz2 = 0; + d->chk_lpt_lebs = 0; + d->chk_lpt_wastage = 0; + if (c->dirty_pn_cnt > c->pnode_cnt) { + ubifs_err("dirty pnodes %d exceed max %d", + c->dirty_pn_cnt, c->pnode_cnt); + err = -EINVAL; + } + if (c->dirty_nn_cnt > c->nnode_cnt) { + ubifs_err("dirty nnodes %d exceed max %d", + c->dirty_nn_cnt, c->nnode_cnt); + err = -EINVAL; + } + return err; + case 1: + d->chk_lpt_sz += len; + return 0; + case 2: + d->chk_lpt_sz += len; + d->chk_lpt_wastage += len; + d->chk_lpt_lebs += 1; + return 0; + case 3: + chk_lpt_sz = c->leb_size; + chk_lpt_sz *= d->chk_lpt_lebs; + chk_lpt_sz += len - c->nhead_offs; + if (d->chk_lpt_sz != chk_lpt_sz) { + ubifs_err("LPT wrote %lld but space used was %lld", + d->chk_lpt_sz, chk_lpt_sz); + err = -EINVAL; + } + if (d->chk_lpt_sz > c->lpt_sz) { + ubifs_err("LPT wrote %lld but lpt_sz is %lld", + d->chk_lpt_sz, c->lpt_sz); + err = -EINVAL; + } + if (d->chk_lpt_sz2 && d->chk_lpt_sz != d->chk_lpt_sz2) { + ubifs_err("LPT layout size %lld but wrote %lld", + d->chk_lpt_sz, d->chk_lpt_sz2); + err = -EINVAL; + } + if (d->chk_lpt_sz2 && d->new_nhead_offs != len) { + ubifs_err("LPT new nhead offs: expected %d was %d", + d->new_nhead_offs, len); + err = -EINVAL; + } + lpt_sz = (long long)c->pnode_cnt * c->pnode_sz; + lpt_sz += (long long)c->nnode_cnt * c->nnode_sz; + lpt_sz += c->ltab_sz; + if (c->big_lpt) + lpt_sz += c->lsave_sz; + if (d->chk_lpt_sz - d->chk_lpt_wastage > lpt_sz) { + ubifs_err("LPT chk_lpt_sz %lld + waste %lld exceeds %lld", + d->chk_lpt_sz, d->chk_lpt_wastage, lpt_sz); + err = -EINVAL; + } + if (err) { + ubifs_dump_lpt_info(c); + ubifs_dump_lpt_lebs(c); + dump_stack(); + } + d->chk_lpt_sz2 = d->chk_lpt_sz; + d->chk_lpt_sz = 0; + d->chk_lpt_wastage = 0; + d->chk_lpt_lebs = 0; + d->new_nhead_offs = len; + return err; + case 4: + d->chk_lpt_sz += len; + d->chk_lpt_wastage += len; + return 0; + default: + return -EINVAL; + } +} + +/** + * ubifs_dump_lpt_leb - dump an LPT LEB. + * @c: UBIFS file-system description object + * @lnum: LEB number to dump + * + * This function dumps an LEB from LPT area. Nodes in this area are very + * different to nodes in the main area (e.g., they do not have common headers, + * they do not have 8-byte alignments, etc), so we have a separate function to + * dump LPT area LEBs. Note, LPT has to be locked by the caller. + */ +static void dump_lpt_leb(const struct ubifs_info *c, int lnum) +{ + int err, len = c->leb_size, node_type, node_num, node_len, offs; + void *buf, *p; + + pr_err("(pid %d) start dumping LEB %d\n", current->pid, lnum); + buf = p = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); + if (!buf) { + ubifs_err("cannot allocate memory to dump LPT"); + return; + } + + err = ubifs_leb_read(c, lnum, buf, 0, c->leb_size, 1); + if (err) + goto out; + + while (1) { + offs = c->leb_size - len; + if (!is_a_node(c, p, len)) { + int pad_len; + + pad_len = get_pad_len(c, p, len); + if (pad_len) { + pr_err("LEB %d:%d, pad %d bytes\n", + lnum, offs, pad_len); + p += pad_len; + len -= pad_len; + continue; + } + if (len) + pr_err("LEB %d:%d, free %d bytes\n", + lnum, offs, len); + break; + } + + node_type = get_lpt_node_type(c, p, &node_num); + switch (node_type) { + case UBIFS_LPT_PNODE: + { + node_len = c->pnode_sz; + if (c->big_lpt) + pr_err("LEB %d:%d, pnode num %d\n", + lnum, offs, node_num); + else + pr_err("LEB %d:%d, pnode\n", lnum, offs); + break; + } + case UBIFS_LPT_NNODE: + { + int i; + struct ubifs_nnode nnode; + + node_len = c->nnode_sz; + if (c->big_lpt) + pr_err("LEB %d:%d, nnode num %d, ", + lnum, offs, node_num); + else + pr_err("LEB %d:%d, nnode, ", + lnum, offs); + err = ubifs_unpack_nnode(c, p, &nnode); + for (i = 0; i < UBIFS_LPT_FANOUT; i++) { + pr_cont("%d:%d", nnode.nbranch[i].lnum, + nnode.nbranch[i].offs); + if (i != UBIFS_LPT_FANOUT - 1) + pr_cont(", "); + } + pr_cont("\n"); + break; + } + case UBIFS_LPT_LTAB: + node_len = c->ltab_sz; + pr_err("LEB %d:%d, ltab\n", lnum, offs); + break; + case UBIFS_LPT_LSAVE: + node_len = c->lsave_sz; + pr_err("LEB %d:%d, lsave len\n", lnum, offs); + break; + default: + ubifs_err("LPT node type %d not recognized", node_type); + goto out; + } + + p += node_len; + len -= node_len; + } + + pr_err("(pid %d) finish dumping LEB %d\n", current->pid, lnum); +out: + vfree(buf); + return; +} + +/** + * ubifs_dump_lpt_lebs - dump LPT lebs. + * @c: UBIFS file-system description object + * + * This function dumps all LPT LEBs. The caller has to make sure the LPT is + * locked. + */ +void ubifs_dump_lpt_lebs(const struct ubifs_info *c) +{ + int i; + + pr_err("(pid %d) start dumping all LPT LEBs\n", current->pid); + for (i = 0; i < c->lpt_lebs; i++) + dump_lpt_leb(c, i + c->lpt_first); + pr_err("(pid %d) finish dumping all LPT LEBs\n", current->pid); +} + +/** + * dbg_populate_lsave - debugging version of 'populate_lsave()' + * @c: UBIFS file-system description object + * + * This is a debugging version for 'populate_lsave()' which populates lsave + * with random LEBs instead of useful LEBs, which is good for test coverage. + * Returns zero if lsave has not been populated (this debugging feature is + * disabled) an non-zero if lsave has been populated. + */ +static int dbg_populate_lsave(struct ubifs_info *c) +{ + struct ubifs_lprops *lprops; + struct ubifs_lpt_heap *heap; + int i; + + if (!dbg_is_chk_gen(c)) + return 0; + if (prandom_u32() & 3) + return 0; + + for (i = 0; i < c->lsave_cnt; i++) + c->lsave[i] = c->main_first; + + list_for_each_entry(lprops, &c->empty_list, list) + c->lsave[prandom_u32() % c->lsave_cnt] = lprops->lnum; + list_for_each_entry(lprops, &c->freeable_list, list) + c->lsave[prandom_u32() % c->lsave_cnt] = lprops->lnum; + list_for_each_entry(lprops, &c->frdi_idx_list, list) + c->lsave[prandom_u32() % c->lsave_cnt] = lprops->lnum; + + heap = &c->lpt_heap[LPROPS_DIRTY_IDX - 1]; + for (i = 0; i < heap->cnt; i++) + c->lsave[prandom_u32() % c->lsave_cnt] = heap->arr[i]->lnum; + heap = &c->lpt_heap[LPROPS_DIRTY - 1]; + for (i = 0; i < heap->cnt; i++) + c->lsave[prandom_u32() % c->lsave_cnt] = heap->arr[i]->lnum; + heap = &c->lpt_heap[LPROPS_FREE - 1]; + for (i = 0; i < heap->cnt; i++) + c->lsave[prandom_u32() % c->lsave_cnt] = heap->arr[i]->lnum; + + return 1; +} +#endif diff --git a/fs/ubifs/master.c b/fs/ubifs/master.c index 3f2926e870..761e0704e4 100644 --- a/fs/ubifs/master.c +++ b/fs/ubifs/master.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -23,13 +12,19 @@ /* This file implements reading and writing the master node */ #include "ubifs.h" +#ifdef __UBOOT__ +#include +#include +#include +#endif /** * scan_for_master - search the valid master node. * @c: UBIFS file-system description object * * This function scans the master node LEBs and search for the latest master - * node. Returns zero in case of success and a negative error code in case of + * node. Returns zero in case of success, %-EUCLEAN if there master area is + * corrupted and requires recovery, and a negative error code in case of * failure. */ static int scan_for_master(struct ubifs_info *c) @@ -40,7 +35,7 @@ static int scan_for_master(struct ubifs_info *c) lnum = UBIFS_MST_LNUM; - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) return PTR_ERR(sleb); nodes_cnt = sleb->nodes_cnt; @@ -48,7 +43,7 @@ static int scan_for_master(struct ubifs_info *c) snod = list_entry(sleb->nodes.prev, struct ubifs_scan_node, list); if (snod->type != UBIFS_MST_NODE) - goto out; + goto out_dump; memcpy(c->mst_node, snod->node, snod->len); offs = snod->offs; } @@ -56,7 +51,7 @@ static int scan_for_master(struct ubifs_info *c) lnum += 1; - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) return PTR_ERR(sleb); if (sleb->nodes_cnt != nodes_cnt) @@ -65,7 +60,7 @@ static int scan_for_master(struct ubifs_info *c) goto out; snod = list_entry(sleb->nodes.prev, struct ubifs_scan_node, list); if (snod->type != UBIFS_MST_NODE) - goto out; + goto out_dump; if (snod->offs != offs) goto out; if (memcmp((void *)c->mst_node + UBIFS_CH_SZ, @@ -78,6 +73,12 @@ static int scan_for_master(struct ubifs_info *c) out: ubifs_scan_destroy(sleb); + return -EUCLEAN; + +out_dump: + ubifs_err("unexpected node type %d master LEB %d:%d", + snod->type, lnum, snod->offs); + ubifs_scan_destroy(sleb); return -EINVAL; } @@ -141,7 +142,7 @@ static int validate_master(const struct ubifs_info *c) } main_sz = (long long)c->main_lebs * c->leb_size; - if (c->old_idx_sz & 7 || c->old_idx_sz >= main_sz) { + if (c->bi.old_idx_sz & 7 || c->bi.old_idx_sz >= main_sz) { err = 9; goto out; } @@ -211,7 +212,7 @@ static int validate_master(const struct ubifs_info *c) } if (c->lst.total_dead + c->lst.total_dark + - c->lst.total_used + c->old_idx_sz > main_sz) { + c->lst.total_used + c->bi.old_idx_sz > main_sz) { err = 21; goto out; } @@ -234,7 +235,7 @@ static int validate_master(const struct ubifs_info *c) out: ubifs_err("bad master node at offset %d error %d", c->mst_offs, err); - dbg_dump_node(c, c->mst_node); + ubifs_dump_node(c, c->mst_node); return -EINVAL; } @@ -256,7 +257,8 @@ int ubifs_read_master(struct ubifs_info *c) err = scan_for_master(c); if (err) { - err = ubifs_recover_master_node(c); + if (err == -EUCLEAN) + err = ubifs_recover_master_node(c); if (err) /* * Note, we do not free 'c->mst_node' here because the @@ -278,7 +280,7 @@ int ubifs_read_master(struct ubifs_info *c) c->gc_lnum = le32_to_cpu(c->mst_node->gc_lnum); c->ihead_lnum = le32_to_cpu(c->mst_node->ihead_lnum); c->ihead_offs = le32_to_cpu(c->mst_node->ihead_offs); - c->old_idx_sz = le64_to_cpu(c->mst_node->index_size); + c->bi.old_idx_sz = le64_to_cpu(c->mst_node->index_size); c->lpt_lnum = le32_to_cpu(c->mst_node->lpt_lnum); c->lpt_offs = le32_to_cpu(c->mst_node->lpt_offs); c->nhead_lnum = le32_to_cpu(c->mst_node->nhead_lnum); @@ -297,7 +299,7 @@ int ubifs_read_master(struct ubifs_info *c) c->lst.total_dead = le64_to_cpu(c->mst_node->total_dead); c->lst.total_dark = le64_to_cpu(c->mst_node->total_dark); - c->calc_idx_sz = c->old_idx_sz; + c->calc_idx_sz = c->bi.old_idx_sz; if (c->mst_node->flags & cpu_to_le32(UBIFS_MST_NO_ORPHS)) c->no_orphs = 1; @@ -309,7 +311,7 @@ int ubifs_read_master(struct ubifs_info *c) if (c->leb_cnt < old_leb_cnt || c->leb_cnt < UBIFS_MIN_LEB_CNT) { ubifs_err("bad leb_cnt on master node"); - dbg_dump_node(c, c->mst_node); + ubifs_dump_node(c, c->mst_node); return -EINVAL; } @@ -335,7 +337,58 @@ int ubifs_read_master(struct ubifs_info *c) if (err) return err; +#ifndef __UBOOT__ err = dbg_old_index_check_init(c, &c->zroot); +#endif + + return err; +} + +#ifndef __UBOOT__ +/** + * ubifs_write_master - write master node. + * @c: UBIFS file-system description object + * + * This function writes the master node. The caller has to take the + * @c->mst_mutex lock before calling this function. Returns zero in case of + * success and a negative error code in case of failure. The master node is + * written twice to enable recovery. + */ +int ubifs_write_master(struct ubifs_info *c) +{ + int err, lnum, offs, len; + + ubifs_assert(!c->ro_media && !c->ro_mount); + if (c->ro_error) + return -EROFS; + + lnum = UBIFS_MST_LNUM; + offs = c->mst_offs + c->mst_node_alsz; + len = UBIFS_MST_NODE_SZ; + + if (offs + UBIFS_MST_NODE_SZ > c->leb_size) { + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + offs = 0; + } + + c->mst_offs = offs; + c->mst_node->highest_inum = cpu_to_le64(c->highest_inum); + + err = ubifs_write_node(c, c->mst_node, len, lnum, offs); + if (err) + return err; + + lnum += 1; + + if (offs == 0) { + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + } + err = ubifs_write_node(c, c->mst_node, len, lnum, offs); return err; } +#endif diff --git a/fs/ubifs/misc.h b/fs/ubifs/misc.h index 609232e931..7cad2bed1b 100644 --- a/fs/ubifs/misc.h +++ b/fs/ubifs/misc.h @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -38,6 +27,29 @@ static inline int ubifs_zn_dirty(const struct ubifs_znode *znode) return !!test_bit(DIRTY_ZNODE, &znode->flags); } +/** + * ubifs_zn_obsolete - check if znode is obsolete. + * @znode: znode to check + * + * This helper function returns %1 if @znode is obsolete and %0 otherwise. + */ +static inline int ubifs_zn_obsolete(const struct ubifs_znode *znode) +{ + return !!test_bit(OBSOLETE_ZNODE, &znode->flags); +} + +/** + * ubifs_zn_cow - check if znode has to be copied on write. + * @znode: znode to check + * + * This helper function returns %1 if @znode is has COW flag set and %0 + * otherwise. + */ +static inline int ubifs_zn_cow(const struct ubifs_znode *znode) +{ + return !!test_bit(COW_ZNODE, &znode->flags); +} + /** * ubifs_wake_up_bgt - wake up background thread. * @c: UBIFS file-system description object @@ -121,82 +133,27 @@ static inline int ubifs_wbuf_sync(struct ubifs_wbuf *wbuf) return err; } +#ifndef __UBOOT__ /** - * ubifs_leb_unmap - unmap an LEB. - * @c: UBIFS file-system description object - * @lnum: LEB number to unmap - * - * This function returns %0 on success and a negative error code on failure. - */ -static inline int ubifs_leb_unmap(const struct ubifs_info *c, int lnum) -{ - int err; - - if (c->ro_media) - return -EROFS; - err = ubi_leb_unmap(c->ubi, lnum); - if (err) { - ubifs_err("unmap LEB %d failed, error %d", lnum, err); - return err; - } - - return 0; -} - -/** - * ubifs_leb_write - write to a LEB. - * @c: UBIFS file-system description object - * @lnum: LEB number to write - * @buf: buffer to write from - * @offs: offset within LEB to write to - * @len: length to write - * @dtype: data type - * - * This function returns %0 on success and a negative error code on failure. - */ -static inline int ubifs_leb_write(const struct ubifs_info *c, int lnum, - const void *buf, int offs, int len, int dtype) -{ - int err; - - if (c->ro_media) - return -EROFS; - err = ubi_leb_write(c->ubi, lnum, buf, offs, len, dtype); - if (err) { - ubifs_err("writing %d bytes at %d:%d, error %d", - len, lnum, offs, err); - return err; - } - - return 0; -} - -/** - * ubifs_leb_change - atomic LEB change. - * @c: UBIFS file-system description object - * @lnum: LEB number to write - * @buf: buffer to write from - * @len: length to write - * @dtype: data type + * ubifs_encode_dev - encode device node IDs. + * @dev: UBIFS device node information + * @rdev: device IDs to encode * - * This function returns %0 on success and a negative error code on failure. + * This is a helper function which encodes major/minor numbers of a device node + * into UBIFS device node description. We use standard Linux "new" and "huge" + * encodings. */ -static inline int ubifs_leb_change(const struct ubifs_info *c, int lnum, - const void *buf, int len, int dtype) +static inline int ubifs_encode_dev(union ubifs_dev_desc *dev, dev_t rdev) { - int err; - - if (c->ro_media) - return -EROFS; - err = ubi_leb_change(c->ubi, lnum, buf, len, dtype); - if (err) { - ubifs_err("changing %d bytes in LEB %d, error %d", - len, lnum, err); - return err; + if (new_valid_dev(rdev)) { + dev->new = cpu_to_le32(new_encode_dev(rdev)); + return sizeof(dev->new); + } else { + dev->huge = cpu_to_le64(huge_encode_dev(rdev)); + return sizeof(dev->huge); } - - return 0; } +#endif /** * ubifs_add_dirt - add dirty space to LEB properties. @@ -260,8 +217,24 @@ struct ubifs_branch *ubifs_idx_branch(const struct ubifs_info *c, static inline void *ubifs_idx_key(const struct ubifs_info *c, const struct ubifs_idx_node *idx) { - const __u8 *branch = idx->branches; - return (void *)((struct ubifs_branch *)branch)->key; +#ifndef __UBOOT__ + return (void *)((struct ubifs_branch *)idx->branches)->key; +#else + struct ubifs_branch *tmp; + + tmp = (struct ubifs_branch *)idx->branches; + return (void *)tmp->key; +#endif +} + +/** + * ubifs_current_time - round current time to time granularity. + * @inode: inode + */ +static inline struct timespec ubifs_current_time(struct inode *inode) +{ + return (inode->i_sb->s_time_gran < NSEC_PER_SEC) ? + current_fs_time(inode->i_sb) : CURRENT_TIME_SEC; } /** @@ -308,4 +281,21 @@ static inline void ubifs_release_lprops(struct ubifs_info *c) mutex_unlock(&c->lp_mutex); } +/** + * ubifs_next_log_lnum - switch to the next log LEB. + * @c: UBIFS file-system description object + * @lnum: current log LEB + * + * This helper function returns the log LEB number which goes next after LEB + * 'lnum'. + */ +static inline int ubifs_next_log_lnum(const struct ubifs_info *c, int lnum) +{ + lnum += 1; + if (lnum > c->log_last) + lnum = UBIFS_LOG_LNUM; + + return lnum; +} + #endif /* __UBIFS_MISC_H__ */ diff --git a/fs/ubifs/orphan.c b/fs/ubifs/orphan.c index d091031b8b..4e42879b5d 100644 --- a/fs/ubifs/orphan.c +++ b/fs/ubifs/orphan.c @@ -3,22 +3,12 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Author: Adrian Hunter */ +#include #include "ubifs.h" /* @@ -52,6 +42,166 @@ * than the maximum number of orphans allowed. */ +static int dbg_check_orphans(struct ubifs_info *c); + +/** + * ubifs_add_orphan - add an orphan. + * @c: UBIFS file-system description object + * @inum: orphan inode number + * + * Add an orphan. This function is called when an inodes link count drops to + * zero. + */ +int ubifs_add_orphan(struct ubifs_info *c, ino_t inum) +{ + struct ubifs_orphan *orphan, *o; + struct rb_node **p, *parent = NULL; + + orphan = kzalloc(sizeof(struct ubifs_orphan), GFP_NOFS); + if (!orphan) + return -ENOMEM; + orphan->inum = inum; + orphan->new = 1; + + spin_lock(&c->orphan_lock); + if (c->tot_orphans >= c->max_orphans) { + spin_unlock(&c->orphan_lock); + kfree(orphan); + return -ENFILE; + } + p = &c->orph_tree.rb_node; + while (*p) { + parent = *p; + o = rb_entry(parent, struct ubifs_orphan, rb); + if (inum < o->inum) + p = &(*p)->rb_left; + else if (inum > o->inum) + p = &(*p)->rb_right; + else { + ubifs_err("orphaned twice"); + spin_unlock(&c->orphan_lock); + kfree(orphan); + return 0; + } + } + c->tot_orphans += 1; + c->new_orphans += 1; + rb_link_node(&orphan->rb, parent, p); + rb_insert_color(&orphan->rb, &c->orph_tree); + list_add_tail(&orphan->list, &c->orph_list); + list_add_tail(&orphan->new_list, &c->orph_new); + spin_unlock(&c->orphan_lock); + dbg_gen("ino %lu", (unsigned long)inum); + return 0; +} + +/** + * ubifs_delete_orphan - delete an orphan. + * @c: UBIFS file-system description object + * @inum: orphan inode number + * + * Delete an orphan. This function is called when an inode is deleted. + */ +void ubifs_delete_orphan(struct ubifs_info *c, ino_t inum) +{ + struct ubifs_orphan *o; + struct rb_node *p; + + spin_lock(&c->orphan_lock); + p = c->orph_tree.rb_node; + while (p) { + o = rb_entry(p, struct ubifs_orphan, rb); + if (inum < o->inum) + p = p->rb_left; + else if (inum > o->inum) + p = p->rb_right; + else { + if (o->del) { + spin_unlock(&c->orphan_lock); + dbg_gen("deleted twice ino %lu", + (unsigned long)inum); + return; + } + if (o->cmt) { + o->del = 1; + o->dnext = c->orph_dnext; + c->orph_dnext = o; + spin_unlock(&c->orphan_lock); + dbg_gen("delete later ino %lu", + (unsigned long)inum); + return; + } + rb_erase(p, &c->orph_tree); + list_del(&o->list); + c->tot_orphans -= 1; + if (o->new) { + list_del(&o->new_list); + c->new_orphans -= 1; + } + spin_unlock(&c->orphan_lock); + kfree(o); + dbg_gen("inum %lu", (unsigned long)inum); + return; + } + } + spin_unlock(&c->orphan_lock); + ubifs_err("missing orphan ino %lu", (unsigned long)inum); + dump_stack(); +} + +/** + * ubifs_orphan_start_commit - start commit of orphans. + * @c: UBIFS file-system description object + * + * Start commit of orphans. + */ +int ubifs_orphan_start_commit(struct ubifs_info *c) +{ + struct ubifs_orphan *orphan, **last; + + spin_lock(&c->orphan_lock); + last = &c->orph_cnext; + list_for_each_entry(orphan, &c->orph_new, new_list) { + ubifs_assert(orphan->new); + ubifs_assert(!orphan->cmt); + orphan->new = 0; + orphan->cmt = 1; + *last = orphan; + last = &orphan->cnext; + } + *last = NULL; + c->cmt_orphans = c->new_orphans; + c->new_orphans = 0; + dbg_cmt("%d orphans to commit", c->cmt_orphans); + INIT_LIST_HEAD(&c->orph_new); + if (c->tot_orphans == 0) + c->no_orphs = 1; + else + c->no_orphs = 0; + spin_unlock(&c->orphan_lock); + return 0; +} + +/** + * avail_orphs - calculate available space. + * @c: UBIFS file-system description object + * + * This function returns the number of orphans that can be written in the + * available space. + */ +static int avail_orphs(struct ubifs_info *c) +{ + int avail_lebs, avail, gap; + + avail_lebs = c->orph_lebs - (c->ohead_lnum - c->orph_first) - 1; + avail = avail_lebs * + ((c->leb_size - UBIFS_ORPH_NODE_SZ) / sizeof(__le64)); + gap = c->leb_size - c->ohead_offs; + if (gap >= UBIFS_ORPH_NODE_SZ + sizeof(__le64)) + avail += (gap - UBIFS_ORPH_NODE_SZ) / sizeof(__le64); + return avail; +} + /** * tot_avail_orphs - calculate total space. * @c: UBIFS file-system description object @@ -69,6 +219,256 @@ static int tot_avail_orphs(struct ubifs_info *c) return avail / 2; } +/** + * do_write_orph_node - write a node to the orphan head. + * @c: UBIFS file-system description object + * @len: length of node + * @atomic: write atomically + * + * This function writes a node to the orphan head from the orphan buffer. If + * %atomic is not zero, then the write is done atomically. On success, %0 is + * returned, otherwise a negative error code is returned. + */ +static int do_write_orph_node(struct ubifs_info *c, int len, int atomic) +{ + int err = 0; + + if (atomic) { + ubifs_assert(c->ohead_offs == 0); + ubifs_prepare_node(c, c->orph_buf, len, 1); + len = ALIGN(len, c->min_io_size); + err = ubifs_leb_change(c, c->ohead_lnum, c->orph_buf, len); + } else { + if (c->ohead_offs == 0) { + /* Ensure LEB has been unmapped */ + err = ubifs_leb_unmap(c, c->ohead_lnum); + if (err) + return err; + } + err = ubifs_write_node(c, c->orph_buf, len, c->ohead_lnum, + c->ohead_offs); + } + return err; +} + +/** + * write_orph_node - write an orphan node. + * @c: UBIFS file-system description object + * @atomic: write atomically + * + * This function builds an orphan node from the cnext list and writes it to the + * orphan head. On success, %0 is returned, otherwise a negative error code + * is returned. + */ +static int write_orph_node(struct ubifs_info *c, int atomic) +{ + struct ubifs_orphan *orphan, *cnext; + struct ubifs_orph_node *orph; + int gap, err, len, cnt, i; + + ubifs_assert(c->cmt_orphans > 0); + gap = c->leb_size - c->ohead_offs; + if (gap < UBIFS_ORPH_NODE_SZ + sizeof(__le64)) { + c->ohead_lnum += 1; + c->ohead_offs = 0; + gap = c->leb_size; + if (c->ohead_lnum > c->orph_last) { + /* + * We limit the number of orphans so that this should + * never happen. + */ + ubifs_err("out of space in orphan area"); + return -EINVAL; + } + } + cnt = (gap - UBIFS_ORPH_NODE_SZ) / sizeof(__le64); + if (cnt > c->cmt_orphans) + cnt = c->cmt_orphans; + len = UBIFS_ORPH_NODE_SZ + cnt * sizeof(__le64); + ubifs_assert(c->orph_buf); + orph = c->orph_buf; + orph->ch.node_type = UBIFS_ORPH_NODE; + spin_lock(&c->orphan_lock); + cnext = c->orph_cnext; + for (i = 0; i < cnt; i++) { + orphan = cnext; + ubifs_assert(orphan->cmt); + orph->inos[i] = cpu_to_le64(orphan->inum); + orphan->cmt = 0; + cnext = orphan->cnext; + orphan->cnext = NULL; + } + c->orph_cnext = cnext; + c->cmt_orphans -= cnt; + spin_unlock(&c->orphan_lock); + if (c->cmt_orphans) + orph->cmt_no = cpu_to_le64(c->cmt_no); + else + /* Mark the last node of the commit */ + orph->cmt_no = cpu_to_le64((c->cmt_no) | (1ULL << 63)); + ubifs_assert(c->ohead_offs + len <= c->leb_size); + ubifs_assert(c->ohead_lnum >= c->orph_first); + ubifs_assert(c->ohead_lnum <= c->orph_last); + err = do_write_orph_node(c, len, atomic); + c->ohead_offs += ALIGN(len, c->min_io_size); + c->ohead_offs = ALIGN(c->ohead_offs, 8); + return err; +} + +/** + * write_orph_nodes - write orphan nodes until there are no more to commit. + * @c: UBIFS file-system description object + * @atomic: write atomically + * + * This function writes orphan nodes for all the orphans to commit. On success, + * %0 is returned, otherwise a negative error code is returned. + */ +static int write_orph_nodes(struct ubifs_info *c, int atomic) +{ + int err; + + while (c->cmt_orphans > 0) { + err = write_orph_node(c, atomic); + if (err) + return err; + } + if (atomic) { + int lnum; + + /* Unmap any unused LEBs after consolidation */ + lnum = c->ohead_lnum + 1; + for (lnum = c->ohead_lnum + 1; lnum <= c->orph_last; lnum++) { + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + } + } + return 0; +} + +/** + * consolidate - consolidate the orphan area. + * @c: UBIFS file-system description object + * + * This function enables consolidation by putting all the orphans into the list + * to commit. The list is in the order that the orphans were added, and the + * LEBs are written atomically in order, so at no time can orphans be lost by + * an unclean unmount. + * + * This function returns %0 on success and a negative error code on failure. + */ +static int consolidate(struct ubifs_info *c) +{ + int tot_avail = tot_avail_orphs(c), err = 0; + + spin_lock(&c->orphan_lock); + dbg_cmt("there is space for %d orphans and there are %d", + tot_avail, c->tot_orphans); + if (c->tot_orphans - c->new_orphans <= tot_avail) { + struct ubifs_orphan *orphan, **last; + int cnt = 0; + + /* Change the cnext list to include all non-new orphans */ + last = &c->orph_cnext; + list_for_each_entry(orphan, &c->orph_list, list) { + if (orphan->new) + continue; + orphan->cmt = 1; + *last = orphan; + last = &orphan->cnext; + cnt += 1; + } + *last = NULL; + ubifs_assert(cnt == c->tot_orphans - c->new_orphans); + c->cmt_orphans = cnt; + c->ohead_lnum = c->orph_first; + c->ohead_offs = 0; + } else { + /* + * We limit the number of orphans so that this should + * never happen. + */ + ubifs_err("out of space in orphan area"); + err = -EINVAL; + } + spin_unlock(&c->orphan_lock); + return err; +} + +/** + * commit_orphans - commit orphans. + * @c: UBIFS file-system description object + * + * This function commits orphans to flash. On success, %0 is returned, + * otherwise a negative error code is returned. + */ +static int commit_orphans(struct ubifs_info *c) +{ + int avail, atomic = 0, err; + + ubifs_assert(c->cmt_orphans > 0); + avail = avail_orphs(c); + if (avail < c->cmt_orphans) { + /* Not enough space to write new orphans, so consolidate */ + err = consolidate(c); + if (err) + return err; + atomic = 1; + } + err = write_orph_nodes(c, atomic); + return err; +} + +/** + * erase_deleted - erase the orphans marked for deletion. + * @c: UBIFS file-system description object + * + * During commit, the orphans being committed cannot be deleted, so they are + * marked for deletion and deleted by this function. Also, the recovery + * adds killed orphans to the deletion list, and therefore they are deleted + * here too. + */ +static void erase_deleted(struct ubifs_info *c) +{ + struct ubifs_orphan *orphan, *dnext; + + spin_lock(&c->orphan_lock); + dnext = c->orph_dnext; + while (dnext) { + orphan = dnext; + dnext = orphan->dnext; + ubifs_assert(!orphan->new); + ubifs_assert(orphan->del); + rb_erase(&orphan->rb, &c->orph_tree); + list_del(&orphan->list); + c->tot_orphans -= 1; + dbg_gen("deleting orphan ino %lu", (unsigned long)orphan->inum); + kfree(orphan); + } + c->orph_dnext = NULL; + spin_unlock(&c->orphan_lock); +} + +/** + * ubifs_orphan_end_commit - end commit of orphans. + * @c: UBIFS file-system description object + * + * End commit of orphans. + */ +int ubifs_orphan_end_commit(struct ubifs_info *c) +{ + int err; + + if (c->cmt_orphans != 0) { + err = commit_orphans(c); + if (err) + return err; + } + erase_deleted(c); + err = dbg_check_orphans(c); + return err; +} + /** * ubifs_clear_orphans - erase all LEBs used for orphans. * @c: UBIFS file-system description object @@ -128,6 +528,7 @@ static int insert_dead_orphan(struct ubifs_info *c, ino_t inum) rb_link_node(&orphan->rb, parent, p); rb_insert_color(&orphan->rb, &c->orph_tree); list_add_tail(&orphan->list, &c->orph_list); + orphan->del = 1; orphan->dnext = c->orph_dnext; c->orph_dnext = orphan; dbg_mnt("ino %lu, new %d, tot %d", (unsigned long)inum, @@ -159,9 +560,9 @@ static int do_kill_orphans(struct ubifs_info *c, struct ubifs_scan_leb *sleb, list_for_each_entry(snod, &sleb->nodes, list) { if (snod->type != UBIFS_ORPH_NODE) { - ubifs_err("invalid node type %d in orphan area at " - "%d:%d", snod->type, sleb->lnum, snod->offs); - dbg_dump_node(c, snod->node); + ubifs_err("invalid node type %d in orphan area at %d:%d", + snod->type, sleb->lnum, snod->offs); + ubifs_dump_node(c, snod->node); return -EINVAL; } @@ -186,10 +587,9 @@ static int do_kill_orphans(struct ubifs_info *c, struct ubifs_scan_leb *sleb, * number. That makes this orphan node, out of date. */ if (!first) { - ubifs_err("out of order commit number %llu in " - "orphan node at %d:%d", + ubifs_err("out of order commit number %llu in orphan node at %d:%d", cmt_no, sleb->lnum, snod->offs); - dbg_dump_node(c, snod->node); + ubifs_dump_node(c, snod->node); return -EINVAL; } dbg_rcvry("out of date LEB %d", sleb->lnum); @@ -262,9 +662,11 @@ static int kill_orphans(struct ubifs_info *c) struct ubifs_scan_leb *sleb; dbg_rcvry("LEB %d", lnum); - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) { - sleb = ubifs_recover_leb(c, lnum, 0, c->sbuf, 0); + if (PTR_ERR(sleb) == -EUCLEAN) + sleb = ubifs_recover_leb(c, lnum, 0, + c->sbuf, -1); if (IS_ERR(sleb)) { err = PTR_ERR(sleb); break; @@ -314,3 +716,232 @@ int ubifs_mount_orphans(struct ubifs_info *c, int unclean, int read_only) return err; } + +/* + * Everything below is related to debugging. + */ + +struct check_orphan { + struct rb_node rb; + ino_t inum; +}; + +struct check_info { + unsigned long last_ino; + unsigned long tot_inos; + unsigned long missing; + unsigned long long leaf_cnt; + struct ubifs_ino_node *node; + struct rb_root root; +}; + +static int dbg_find_orphan(struct ubifs_info *c, ino_t inum) +{ + struct ubifs_orphan *o; + struct rb_node *p; + + spin_lock(&c->orphan_lock); + p = c->orph_tree.rb_node; + while (p) { + o = rb_entry(p, struct ubifs_orphan, rb); + if (inum < o->inum) + p = p->rb_left; + else if (inum > o->inum) + p = p->rb_right; + else { + spin_unlock(&c->orphan_lock); + return 1; + } + } + spin_unlock(&c->orphan_lock); + return 0; +} + +static int dbg_ins_check_orphan(struct rb_root *root, ino_t inum) +{ + struct check_orphan *orphan, *o; + struct rb_node **p, *parent = NULL; + + orphan = kzalloc(sizeof(struct check_orphan), GFP_NOFS); + if (!orphan) + return -ENOMEM; + orphan->inum = inum; + + p = &root->rb_node; + while (*p) { + parent = *p; + o = rb_entry(parent, struct check_orphan, rb); + if (inum < o->inum) + p = &(*p)->rb_left; + else if (inum > o->inum) + p = &(*p)->rb_right; + else { + kfree(orphan); + return 0; + } + } + rb_link_node(&orphan->rb, parent, p); + rb_insert_color(&orphan->rb, root); + return 0; +} + +static int dbg_find_check_orphan(struct rb_root *root, ino_t inum) +{ + struct check_orphan *o; + struct rb_node *p; + + p = root->rb_node; + while (p) { + o = rb_entry(p, struct check_orphan, rb); + if (inum < o->inum) + p = p->rb_left; + else if (inum > o->inum) + p = p->rb_right; + else + return 1; + } + return 0; +} + +static void dbg_free_check_tree(struct rb_root *root) +{ + struct check_orphan *o, *n; + + rbtree_postorder_for_each_entry_safe(o, n, root, rb) + kfree(o); +} + +static int dbg_orphan_check(struct ubifs_info *c, struct ubifs_zbranch *zbr, + void *priv) +{ + struct check_info *ci = priv; + ino_t inum; + int err; + + inum = key_inum(c, &zbr->key); + if (inum != ci->last_ino) { + /* Lowest node type is the inode node, so it comes first */ + if (key_type(c, &zbr->key) != UBIFS_INO_KEY) + ubifs_err("found orphan node ino %lu, type %d", + (unsigned long)inum, key_type(c, &zbr->key)); + ci->last_ino = inum; + ci->tot_inos += 1; + err = ubifs_tnc_read_node(c, zbr, ci->node); + if (err) { + ubifs_err("node read failed, error %d", err); + return err; + } + if (ci->node->nlink == 0) + /* Must be recorded as an orphan */ + if (!dbg_find_check_orphan(&ci->root, inum) && + !dbg_find_orphan(c, inum)) { + ubifs_err("missing orphan, ino %lu", + (unsigned long)inum); + ci->missing += 1; + } + } + ci->leaf_cnt += 1; + return 0; +} + +static int dbg_read_orphans(struct check_info *ci, struct ubifs_scan_leb *sleb) +{ + struct ubifs_scan_node *snod; + struct ubifs_orph_node *orph; + ino_t inum; + int i, n, err; + + list_for_each_entry(snod, &sleb->nodes, list) { + cond_resched(); + if (snod->type != UBIFS_ORPH_NODE) + continue; + orph = snod->node; + n = (le32_to_cpu(orph->ch.len) - UBIFS_ORPH_NODE_SZ) >> 3; + for (i = 0; i < n; i++) { + inum = le64_to_cpu(orph->inos[i]); + err = dbg_ins_check_orphan(&ci->root, inum); + if (err) + return err; + } + } + return 0; +} + +static int dbg_scan_orphans(struct ubifs_info *c, struct check_info *ci) +{ + int lnum, err = 0; + void *buf; + + /* Check no-orphans flag and skip this if no orphans */ + if (c->no_orphs) + return 0; + + buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); + if (!buf) { + ubifs_err("cannot allocate memory to check orphans"); + return 0; + } + + for (lnum = c->orph_first; lnum <= c->orph_last; lnum++) { + struct ubifs_scan_leb *sleb; + + sleb = ubifs_scan(c, lnum, 0, buf, 0); + if (IS_ERR(sleb)) { + err = PTR_ERR(sleb); + break; + } + + err = dbg_read_orphans(ci, sleb); + ubifs_scan_destroy(sleb); + if (err) + break; + } + + vfree(buf); + return err; +} + +static int dbg_check_orphans(struct ubifs_info *c) +{ + struct check_info ci; + int err; + + if (!dbg_is_chk_orph(c)) + return 0; + + ci.last_ino = 0; + ci.tot_inos = 0; + ci.missing = 0; + ci.leaf_cnt = 0; + ci.root = RB_ROOT; + ci.node = kmalloc(UBIFS_MAX_INO_NODE_SZ, GFP_NOFS); + if (!ci.node) { + ubifs_err("out of memory"); + return -ENOMEM; + } + + err = dbg_scan_orphans(c, &ci); + if (err) + goto out; + + err = dbg_walk_index(c, &dbg_orphan_check, NULL, &ci); + if (err) { + ubifs_err("cannot scan TNC, error %d", err); + goto out; + } + + if (ci.missing) { + ubifs_err("%lu missing orphan(s)", ci.missing); + err = -EINVAL; + goto out; + } + + dbg_cmt("last inode number is %lu", ci.last_ino); + dbg_cmt("total number of inodes is %lu", ci.tot_inos); + dbg_cmt("total number of leaf nodes is %llu", ci.leaf_cnt); + +out: + dbg_free_check_tree(&ci.root); + kfree(ci.node); + return err; +} diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index 744465005c..763770738b 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Adrian Hunter * Artem Bityutskiy (Битюцкий Артём) @@ -23,13 +12,36 @@ /* * This file implements functions needed to recover from unclean un-mounts. * When UBIFS is mounted, it checks a flag on the master node to determine if - * an un-mount was completed sucessfully. If not, the process of mounting - * incorparates additional checking and fixing of on-flash data structures. + * an un-mount was completed successfully. If not, the process of mounting + * incorporates additional checking and fixing of on-flash data structures. * UBIFS always cleans away all remnants of an unclean un-mount, so that * errors do not accumulate. However UBIFS defers recovery if it is mounted * read-only, and the flash is not modified in that case. + * + * The general UBIFS approach to the recovery is that it recovers from + * corruptions which could be caused by power cuts, but it refuses to recover + * from corruption caused by other reasons. And UBIFS tries to distinguish + * between these 2 reasons of corruptions and silently recover in the former + * case and loudly complain in the latter case. + * + * UBIFS writes only to erased LEBs, so it writes only to the flash space + * containing only 0xFFs. UBIFS also always writes strictly from the beginning + * of the LEB to the end. And UBIFS assumes that the underlying flash media + * writes in @c->max_write_size bytes at a time. + * + * Hence, if UBIFS finds a corrupted node at offset X, it expects only the min. + * I/O unit corresponding to offset X to contain corrupted data, all the + * following min. I/O units have to contain empty space (all 0xFFs). If this is + * not true, the corruption cannot be the result of a power cut, and UBIFS + * refuses to mount. */ +#ifndef __UBOOT__ +#include +#include +#else +#include +#endif #include "ubifs.h" /** @@ -51,6 +63,25 @@ static int is_empty(void *buf, int len) return 1; } +/** + * first_non_ff - find offset of the first non-0xff byte. + * @buf: buffer to search in + * @len: length of buffer + * + * This function returns offset of the first non-0xff byte in @buf or %-1 if + * the buffer contains only 0xff bytes. + */ +static int first_non_ff(void *buf, int len) +{ + uint8_t *p = buf; + int i; + + for (i = 0; i < len; i++) + if (*p++ != 0xff) + return i; + return -1; +} + /** * get_master_node - get the last valid master node allowing for corruption. * @c: UBIFS file-system description object @@ -79,7 +110,7 @@ static int get_master_node(const struct ubifs_info *c, int lnum, void **pbuf, if (!sbuf) return -ENOMEM; - err = ubi_read(c->ubi, lnum, sbuf, 0, c->leb_size); + err = ubifs_leb_read(c, lnum, sbuf, 0, c->leb_size, 0); if (err && err != -EBADMSG) goto out_free; @@ -175,10 +206,10 @@ static int write_rcvrd_mst_node(struct ubifs_info *c, mst->flags |= cpu_to_le32(UBIFS_MST_RCVRY); ubifs_prepare_node(c, mst, UBIFS_MST_NODE_SZ, 1); - err = ubi_leb_change(c->ubi, lnum, mst, sz, UBI_SHORTTERM); + err = ubifs_leb_change(c, lnum, mst, sz); if (err) goto out; - err = ubi_leb_change(c->ubi, lnum + 1, mst, sz, UBI_SHORTTERM); + err = ubifs_leb_change(c, lnum + 1, mst, sz); if (err) goto out; out: @@ -236,7 +267,8 @@ int ubifs_recover_master_node(struct ubifs_info *c) if (cor1) goto out_err; mst = mst1; - } else if (offs1 == 0 && offs2 + sz >= c->leb_size) { + } else if (offs1 == 0 && + c->leb_size - offs2 - sz < sz) { /* 1st LEB was unmapped and written, 2nd not */ if (cor1) goto out_err; @@ -266,12 +298,12 @@ int ubifs_recover_master_node(struct ubifs_info *c) mst = mst2; } - dbg_rcvry("recovered master node from LEB %d", + ubifs_msg("recovered master node from LEB %d", (mst == mst1 ? UBIFS_MST_LNUM : UBIFS_MST_LNUM + 1)); memcpy(c->mst_node, mst, UBIFS_MST_NODE_SZ); - if ((c->vfs_sb->s_flags & MS_RDONLY)) { + if (c->ro_mount) { /* Read-only mode. Keep a copy for switching to rw mode */ c->rcvrd_mst_node = kmalloc(sz, GFP_KERNEL); if (!c->rcvrd_mst_node) { @@ -279,6 +311,40 @@ int ubifs_recover_master_node(struct ubifs_info *c) goto out_free; } memcpy(c->rcvrd_mst_node, c->mst_node, UBIFS_MST_NODE_SZ); + + /* + * We had to recover the master node, which means there was an + * unclean reboot. However, it is possible that the master node + * is clean at this point, i.e., %UBIFS_MST_DIRTY is not set. + * E.g., consider the following chain of events: + * + * 1. UBIFS was cleanly unmounted, so the master node is clean + * 2. UBIFS is being mounted R/W and starts changing the master + * node in the first (%UBIFS_MST_LNUM). A power cut happens, + * so this LEB ends up with some amount of garbage at the + * end. + * 3. UBIFS is being mounted R/O. We reach this place and + * recover the master node from the second LEB + * (%UBIFS_MST_LNUM + 1). But we cannot update the media + * because we are being mounted R/O. We have to defer the + * operation. + * 4. However, this master node (@c->mst_node) is marked as + * clean (since the step 1). And if we just return, the + * mount code will be confused and won't recover the master + * node when it is re-mounter R/W later. + * + * Thus, to force the recovery by marking the master node as + * dirty. + */ + c->mst_node->flags |= cpu_to_le32(UBIFS_MST_DIRTY); +#ifndef __UBOOT__ + } else { + /* Write the recovered master node */ + c->max_sqnum = le64_to_cpu(mst->ch.sqnum) - 1; + err = write_rcvrd_mst_node(c, c->mst_node); + if (err) + goto out_free; +#endif } vfree(buf2); @@ -291,12 +357,12 @@ out_err: out_free: ubifs_err("failed to recover master node"); if (mst1) { - dbg_err("dumping first master node"); - dbg_dump_node(c, mst1); + ubifs_err("dumping first master node"); + ubifs_dump_node(c, mst1); } if (mst2) { - dbg_err("dumping second master node"); - dbg_dump_node(c, mst2); + ubifs_err("dumping second master node"); + ubifs_dump_node(c, mst2); } vfree(buf2); vfree(buf1); @@ -335,44 +401,23 @@ int ubifs_write_rcvrd_mst_node(struct ubifs_info *c) * @offs: offset to check * * This function returns %1 if @offs was in the last write to the LEB whose data - * is in @buf, otherwise %0 is returned. The determination is made by checking - * for subsequent empty space starting from the next min_io_size boundary (or a - * bit less than the common header size if min_io_size is one). + * is in @buf, otherwise %0 is returned. The determination is made by checking + * for subsequent empty space starting from the next @c->max_write_size + * boundary. */ static int is_last_write(const struct ubifs_info *c, void *buf, int offs) { - int empty_offs; - int check_len; + int empty_offs, check_len; uint8_t *p; - if (c->min_io_size == 1) { - check_len = c->leb_size - offs; - p = buf + check_len; - for (; check_len > 0; check_len--) - if (*--p != 0xff) - break; - /* - * 'check_len' is the size of the corruption which cannot be - * more than the size of 1 node if it was caused by an unclean - * unmount. - */ - if (check_len > UBIFS_MAX_NODE_SZ) - return 0; - return 1; - } - /* - * Round up to the next c->min_io_size boundary i.e. 'offs' is in the - * last wbuf written. After that should be empty space. + * Round up to the next @c->max_write_size boundary i.e. @offs is in + * the last wbuf written. After that should be empty space. */ - empty_offs = ALIGN(offs + 1, c->min_io_size); + empty_offs = ALIGN(offs + 1, c->max_write_size); check_len = c->leb_size - empty_offs; p = buf + empty_offs - offs; - - for (; check_len > 0; check_len--) - if (*p++ != 0xff) - return 0; - return 1; + return is_empty(p, check_len); } /** @@ -385,7 +430,7 @@ static int is_last_write(const struct ubifs_info *c, void *buf, int offs) * * This function pads up to the next min_io_size boundary (if there is one) and * sets empty space to all 0xff. @buf, @offs and @len are updated to the next - * min_io_size boundary (if there is one). + * @c->min_io_size boundary. */ static void clean_buf(const struct ubifs_info *c, void **buf, int lnum, int *offs, int *len) @@ -395,11 +440,6 @@ static void clean_buf(const struct ubifs_info *c, void **buf, int lnum, lnum = lnum; dbg_rcvry("cleaning corruption at %d:%d", lnum, *offs); - if (c->min_io_size == 1) { - memset(*buf, 0xff, c->leb_size - *offs); - return; - } - ubifs_assert(!(*offs & 7)); empty_offs = ALIGN(*offs, c->min_io_size); pad_len = empty_offs - *offs; @@ -429,7 +469,7 @@ static int no_more_nodes(const struct ubifs_info *c, void *buf, int len, int skip, dlen = le32_to_cpu(ch->len); /* Check for empty space after the corrupt node's common header */ - skip = ALIGN(offs + UBIFS_CH_SZ, c->min_io_size) - offs; + skip = ALIGN(offs + UBIFS_CH_SZ, c->max_write_size) - offs; if (is_empty(buf + skip, len - skip)) return 1; /* @@ -441,7 +481,7 @@ static int no_more_nodes(const struct ubifs_info *c, void *buf, int len, return 0; } /* Now we know the corrupt node's length we can skip over it */ - skip = ALIGN(offs + dlen, c->min_io_size) - offs; + skip = ALIGN(offs + dlen, c->max_write_size) - offs; /* After which there should be empty space */ if (is_empty(buf + skip, len - skip)) return 1; @@ -469,7 +509,7 @@ static int fix_unclean_leb(struct ubifs_info *c, struct ubifs_scan_leb *sleb, endpt = snod->offs + snod->len; } - if ((c->vfs_sb->s_flags & MS_RDONLY) && !c->remounting_rw) { + if (c->ro_mount && !c->remounting_rw) { /* Add to recovery list */ struct ubifs_unclean_leb *ucleb; @@ -481,21 +521,55 @@ static int fix_unclean_leb(struct ubifs_info *c, struct ubifs_scan_leb *sleb, ucleb->lnum = lnum; ucleb->endpt = endpt; list_add_tail(&ucleb->list, &c->unclean_leb_list); +#ifndef __UBOOT__ + } else { + /* Write the fixed LEB back to flash */ + int err; + + dbg_rcvry("fixing LEB %d start %d endpt %d", + lnum, start, sleb->endpt); + if (endpt == 0) { + err = ubifs_leb_unmap(c, lnum); + if (err) + return err; + } else { + int len = ALIGN(endpt, c->min_io_size); + + if (start) { + err = ubifs_leb_read(c, lnum, sleb->buf, 0, + start, 1); + if (err) + return err; + } + /* Pad to min_io_size */ + if (len > endpt) { + int pad_len = len - ALIGN(endpt, 8); + + if (pad_len > 0) { + void *buf = sleb->buf + len - pad_len; + + ubifs_pad(c, buf, pad_len); + } + } + err = ubifs_leb_change(c, lnum, sleb->buf, len); + if (err) + return err; + } +#endif } return 0; } /** - * drop_incomplete_group - drop nodes from an incomplete group. + * drop_last_group - drop the last group of nodes. * @sleb: scanned LEB information * @offs: offset of dropped nodes is returned here * - * This function returns %1 if nodes are dropped and %0 otherwise. + * This is a helper function for 'ubifs_recover_leb()' which drops the last + * group of nodes of the scanned LEB. */ -static int drop_incomplete_group(struct ubifs_scan_leb *sleb, int *offs) +static void drop_last_group(struct ubifs_scan_leb *sleb, int *offs) { - int dropped = 0; - while (!list_empty(&sleb->nodes)) { struct ubifs_scan_node *snod; struct ubifs_ch *ch; @@ -504,15 +578,41 @@ static int drop_incomplete_group(struct ubifs_scan_leb *sleb, int *offs) list); ch = snod->node; if (ch->group_type != UBIFS_IN_NODE_GROUP) - return dropped; - dbg_rcvry("dropping node at %d:%d", sleb->lnum, snod->offs); + break; + + dbg_rcvry("dropping grouped node at %d:%d", + sleb->lnum, snod->offs); + *offs = snod->offs; + list_del(&snod->list); + kfree(snod); + sleb->nodes_cnt -= 1; + } +} + +/** + * drop_last_node - drop the last node. + * @sleb: scanned LEB information + * @offs: offset of dropped nodes is returned here + * @grouped: non-zero if whole group of nodes have to be dropped + * + * This is a helper function for 'ubifs_recover_leb()' which drops the last + * node of the scanned LEB. + */ +static void drop_last_node(struct ubifs_scan_leb *sleb, int *offs) +{ + struct ubifs_scan_node *snod; + + if (!list_empty(&sleb->nodes)) { + snod = list_entry(sleb->nodes.prev, struct ubifs_scan_node, + list); + + dbg_rcvry("dropping last node at %d:%d", + sleb->lnum, snod->offs); *offs = snod->offs; list_del(&snod->list); kfree(snod); sleb->nodes_cnt -= 1; - dropped = 1; } - return dropped; } /** @@ -521,33 +621,30 @@ static int drop_incomplete_group(struct ubifs_scan_leb *sleb, int *offs) * @lnum: LEB number * @offs: offset * @sbuf: LEB-sized buffer to use - * @grouped: nodes may be grouped for recovery + * @jhead: journal head number this LEB belongs to (%-1 if the LEB does not + * belong to any journal head) * * This function does a scan of a LEB, but caters for errors that might have * been caused by the unclean unmount from which we are attempting to recover. - * - * This function returns %0 on success and a negative error code on failure. + * Returns %0 in case of success, %-EUCLEAN if an unrecoverable corruption is + * found, and a negative error code in case of failure. */ struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum, - int offs, void *sbuf, int grouped) + int offs, void *sbuf, int jhead) { - int err, len = c->leb_size - offs, need_clean = 0, quiet = 1; - int empty_chkd = 0, start = offs; + int ret = 0, err, len = c->leb_size - offs, start = offs, min_io_unit; + int grouped = jhead == -1 ? 0 : c->jheads[jhead].grouped; struct ubifs_scan_leb *sleb; void *buf = sbuf + offs; - dbg_rcvry("%d:%d", lnum, offs); + dbg_rcvry("%d:%d, jhead %d, grouped %d", lnum, offs, jhead, grouped); sleb = ubifs_start_scan(c, lnum, offs, sbuf); if (IS_ERR(sleb)) return sleb; - if (sleb->ecc) - need_clean = 1; - + ubifs_assert(len >= 8); while (len >= 8) { - int ret; - dbg_scan("look at LEB %d:%d (%d bytes left)", lnum, offs, len); @@ -557,8 +654,7 @@ struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum, * Scan quietly until there is an error from which we cannot * recover */ - ret = ubifs_scan_a_node(c, buf, len, lnum, offs, quiet); - + ret = ubifs_scan_a_node(c, buf, len, lnum, offs, 1); if (ret == SCANNED_A_NODE) { /* A valid node, and not a padding node */ struct ubifs_ch *ch = buf; @@ -571,98 +667,127 @@ struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum, offs += node_len; buf += node_len; len -= node_len; - continue; - } - - if (ret > 0) { + } else if (ret > 0) { /* Padding bytes or a valid padding node */ offs += ret; buf += ret; len -= ret; - continue; - } - - if (ret == SCANNED_EMPTY_SPACE) { - if (!is_empty(buf, len)) { - if (!is_last_write(c, buf, offs)) - break; - clean_buf(c, &buf, lnum, &offs, &len); - need_clean = 1; - } - empty_chkd = 1; + } else if (ret == SCANNED_EMPTY_SPACE || + ret == SCANNED_GARBAGE || + ret == SCANNED_A_BAD_PAD_NODE || + ret == SCANNED_A_CORRUPT_NODE) { + dbg_rcvry("found corruption (%d) at %d:%d", + ret, lnum, offs); break; + } else { + ubifs_err("unexpected return value %d", ret); + err = -EINVAL; + goto error; } + } - if (ret == SCANNED_GARBAGE || ret == SCANNED_A_BAD_PAD_NODE) - if (is_last_write(c, buf, offs)) { - clean_buf(c, &buf, lnum, &offs, &len); - need_clean = 1; - empty_chkd = 1; - break; - } - - if (ret == SCANNED_A_CORRUPT_NODE) - if (no_more_nodes(c, buf, len, lnum, offs)) { - clean_buf(c, &buf, lnum, &offs, &len); - need_clean = 1; - empty_chkd = 1; - break; - } - - if (quiet) { - /* Redo the last scan but noisily */ - quiet = 0; - continue; - } + if (ret == SCANNED_GARBAGE || ret == SCANNED_A_BAD_PAD_NODE) { + if (!is_last_write(c, buf, offs)) + goto corrupted_rescan; + } else if (ret == SCANNED_A_CORRUPT_NODE) { + if (!no_more_nodes(c, buf, len, lnum, offs)) + goto corrupted_rescan; + } else if (!is_empty(buf, len)) { + if (!is_last_write(c, buf, offs)) { + int corruption = first_non_ff(buf, len); - switch (ret) { - case SCANNED_GARBAGE: - dbg_err("garbage"); - goto corrupted; - case SCANNED_A_CORRUPT_NODE: - case SCANNED_A_BAD_PAD_NODE: - dbg_err("bad node"); - goto corrupted; - default: - dbg_err("unknown"); + /* + * See header comment for this file for more + * explanations about the reasons we have this check. + */ + ubifs_err("corrupt empty space LEB %d:%d, corruption starts at %d", + lnum, offs, corruption); + /* Make sure we dump interesting non-0xFF data */ + offs += corruption; + buf += corruption; goto corrupted; } } - if (!empty_chkd && !is_empty(buf, len)) { - if (is_last_write(c, buf, offs)) { - clean_buf(c, &buf, lnum, &offs, &len); - need_clean = 1; - } else { - ubifs_err("corrupt empty space at LEB %d:%d", - lnum, offs); - goto corrupted; - } - } + min_io_unit = round_down(offs, c->min_io_size); + if (grouped) + /* + * If nodes are grouped, always drop the incomplete group at + * the end. + */ + drop_last_group(sleb, &offs); - /* Drop nodes from incomplete group */ - if (grouped && drop_incomplete_group(sleb, &offs)) { - buf = sbuf + offs; - len = c->leb_size - offs; - clean_buf(c, &buf, lnum, &offs, &len); - need_clean = 1; + if (jhead == GCHD) { + /* + * If this LEB belongs to the GC head then while we are in the + * middle of the same min. I/O unit keep dropping nodes. So + * basically, what we want is to make sure that the last min. + * I/O unit where we saw the corruption is dropped completely + * with all the uncorrupted nodes which may possibly sit there. + * + * In other words, let's name the min. I/O unit where the + * corruption starts B, and the previous min. I/O unit A. The + * below code tries to deal with a situation when half of B + * contains valid nodes or the end of a valid node, and the + * second half of B contains corrupted data or garbage. This + * means that UBIFS had been writing to B just before the power + * cut happened. I do not know how realistic is this scenario + * that half of the min. I/O unit had been written successfully + * and the other half not, but this is possible in our 'failure + * mode emulation' infrastructure at least. + * + * So what is the problem, why we need to drop those nodes? Why + * can't we just clean-up the second half of B by putting a + * padding node there? We can, and this works fine with one + * exception which was reproduced with power cut emulation + * testing and happens extremely rarely. + * + * Imagine the file-system is full, we run GC which starts + * moving valid nodes from LEB X to LEB Y (obviously, LEB Y is + * the current GC head LEB). The @c->gc_lnum is -1, which means + * that GC will retain LEB X and will try to continue. Imagine + * that LEB X is currently the dirtiest LEB, and the amount of + * used space in LEB Y is exactly the same as amount of free + * space in LEB X. + * + * And a power cut happens when nodes are moved from LEB X to + * LEB Y. We are here trying to recover LEB Y which is the GC + * head LEB. We find the min. I/O unit B as described above. + * Then we clean-up LEB Y by padding min. I/O unit. And later + * 'ubifs_rcvry_gc_commit()' function fails, because it cannot + * find a dirty LEB which could be GC'd into LEB Y! Even LEB X + * does not match because the amount of valid nodes there does + * not fit the free space in LEB Y any more! And this is + * because of the padding node which we added to LEB Y. The + * user-visible effect of this which I once observed and + * analysed is that we cannot mount the file-system with + * -ENOSPC error. + * + * So obviously, to make sure that situation does not happen we + * should free min. I/O unit B in LEB Y completely and the last + * used min. I/O unit in LEB Y should be A. This is basically + * what the below code tries to do. + */ + while (offs > min_io_unit) + drop_last_node(sleb, &offs); } - if (offs % c->min_io_size) { - clean_buf(c, &buf, lnum, &offs, &len); - need_clean = 1; - } + buf = sbuf + offs; + len = c->leb_size - offs; + clean_buf(c, &buf, lnum, &offs, &len); ubifs_end_scan(c, sleb, lnum, offs); - if (need_clean) { - err = fix_unclean_leb(c, sleb, start); - if (err) - goto error; - } + err = fix_unclean_leb(c, sleb, start); + if (err) + goto error; return sleb; +corrupted_rescan: + /* Re-scan the corrupted data with verbose messages */ + ubifs_err("corruption %d", ret); + ubifs_scan_a_node(c, buf, len, lnum, offs, 1); corrupted: ubifs_scanned_corruption(c, lnum, offs, buf); err = -EUCLEAN; @@ -693,22 +818,23 @@ static int get_cs_sqnum(struct ubifs_info *c, int lnum, int offs, return -ENOMEM; if (c->leb_size - offs < UBIFS_CS_NODE_SZ) goto out_err; - err = ubi_read(c->ubi, lnum, (void *)cs_node, offs, UBIFS_CS_NODE_SZ); + err = ubifs_leb_read(c, lnum, (void *)cs_node, offs, + UBIFS_CS_NODE_SZ, 0); if (err && err != -EBADMSG) goto out_free; ret = ubifs_scan_a_node(c, cs_node, UBIFS_CS_NODE_SZ, lnum, offs, 0); if (ret != SCANNED_A_NODE) { - dbg_err("Not a valid node"); + ubifs_err("Not a valid node"); goto out_err; } if (cs_node->ch.node_type != UBIFS_CS_NODE) { - dbg_err("Node a CS node, type is %d", cs_node->ch.node_type); + ubifs_err("Node a CS node, type is %d", cs_node->ch.node_type); goto out_err; } if (le64_to_cpu(cs_node->cmt_no) != c->cmt_no) { - dbg_err("CS node cmt_no %llu != current cmt_no %llu", - (unsigned long long)le64_to_cpu(cs_node->cmt_no), - c->cmt_no); + ubifs_err("CS node cmt_no %llu != current cmt_no %llu", + (unsigned long long)le64_to_cpu(cs_node->cmt_no), + c->cmt_no); goto out_err; } *cs_sqnum = le64_to_cpu(cs_node->ch.sqnum); @@ -732,7 +858,8 @@ out_free: * @sbuf: LEB-sized buffer to use * * This function does a scan of a LEB, but caters for errors that might have - * been caused by the unclean unmount from which we are attempting to recover. + * been caused by unclean reboots from which we are attempting to recover + * (assume that only the last log LEB can be corrupted by an unclean reboot). * * This function returns %0 on success and a negative error code on failure. */ @@ -751,7 +878,7 @@ struct ubifs_scan_leb *ubifs_recover_log_leb(struct ubifs_info *c, int lnum, * We can only recover at the end of the log, so check that the * next log LEB is empty or out of date. */ - sleb = ubifs_scan(c, next_lnum, 0, sbuf); + sleb = ubifs_scan(c, next_lnum, 0, sbuf, 0); if (IS_ERR(sleb)) return sleb; if (sleb->nodes_cnt) { @@ -770,15 +897,15 @@ struct ubifs_scan_leb *ubifs_recover_log_leb(struct ubifs_info *c, int lnum, } } if (snod->sqnum > cs_sqnum) { - ubifs_err("unrecoverable log corruption " - "in LEB %d", lnum); + ubifs_err("unrecoverable log corruption in LEB %d", + lnum); ubifs_scan_destroy(sleb); return ERR_PTR(-EUCLEAN); } } ubifs_scan_destroy(sleb); } - return ubifs_recover_leb(c, lnum, offs, sbuf, 0); + return ubifs_recover_leb(c, lnum, offs, sbuf, -1); } /** @@ -792,15 +919,10 @@ struct ubifs_scan_leb *ubifs_recover_log_leb(struct ubifs_info *c, int lnum, * * This function returns %0 on success and a negative error code on failure. */ -static int recover_head(const struct ubifs_info *c, int lnum, int offs, - void *sbuf) +static int recover_head(struct ubifs_info *c, int lnum, int offs, void *sbuf) { - int len, err, need_clean = 0; + int len = c->max_write_size, err; - if (c->min_io_size > 1) - len = c->min_io_size; - else - len = 512; if (offs + len > c->leb_size) len = c->leb_size - offs; @@ -808,27 +930,15 @@ static int recover_head(const struct ubifs_info *c, int lnum, int offs, return 0; /* Read at the head location and check it is empty flash */ - err = ubi_read(c->ubi, lnum, sbuf, offs, len); - if (err) - need_clean = 1; - else { - uint8_t *p = sbuf; - - while (len--) - if (*p++ != 0xff) { - need_clean = 1; - break; - } - } - - if (need_clean) { + err = ubifs_leb_read(c, lnum, sbuf, offs, len, 1); + if (err || !is_empty(sbuf, len)) { dbg_rcvry("cleaning head at %d:%d", lnum, offs); if (offs == 0) return ubifs_leb_unmap(c, lnum); - err = ubi_read(c->ubi, lnum, sbuf, 0, offs); + err = ubifs_leb_read(c, lnum, sbuf, 0, offs, 1); if (err) return err; - return ubi_leb_change(c->ubi, lnum, sbuf, offs, UBI_UNKNOWN); + return ubifs_leb_change(c, lnum, sbuf, offs); } return 0; @@ -851,11 +961,11 @@ static int recover_head(const struct ubifs_info *c, int lnum, int offs, * * This function returns %0 on success and a negative error code on failure. */ -int ubifs_recover_inl_heads(const struct ubifs_info *c, void *sbuf) +int ubifs_recover_inl_heads(struct ubifs_info *c, void *sbuf) { int err; - ubifs_assert(!(c->vfs_sb->s_flags & MS_RDONLY) || c->remounting_rw); + ubifs_assert(!c->ro_mount || c->remounting_rw); dbg_rcvry("checking index head at %d:%d", c->ihead_lnum, c->ihead_offs); err = recover_head(c, c->ihead_lnum, c->ihead_offs, sbuf); @@ -871,7 +981,7 @@ int ubifs_recover_inl_heads(const struct ubifs_info *c, void *sbuf) } /** - * clean_an_unclean_leb - read and write a LEB to remove corruption. + * clean_an_unclean_leb - read and write a LEB to remove corruption. * @c: UBIFS file-system description object * @ucleb: unclean LEB information * @sbuf: LEB-sized buffer to use @@ -882,7 +992,7 @@ int ubifs_recover_inl_heads(const struct ubifs_info *c, void *sbuf) * * This function returns %0 on success and a negative error code on failure. */ -static int clean_an_unclean_leb(const struct ubifs_info *c, +static int clean_an_unclean_leb(struct ubifs_info *c, struct ubifs_unclean_leb *ucleb, void *sbuf) { int err, lnum = ucleb->lnum, offs = 0, len = ucleb->endpt, quiet = 1; @@ -898,7 +1008,7 @@ static int clean_an_unclean_leb(const struct ubifs_info *c, return 0; } - err = ubi_read(c->ubi, lnum, buf, offs, len); + err = ubifs_leb_read(c, lnum, buf, offs, len, 0); if (err && err != -EBADMSG) return err; @@ -958,7 +1068,7 @@ static int clean_an_unclean_leb(const struct ubifs_info *c, } /* Write back the LEB atomically */ - err = ubi_leb_change(c->ubi, lnum, sbuf, len, UBI_UNKNOWN); + err = ubifs_leb_change(c, lnum, sbuf, len); if (err) return err; @@ -978,7 +1088,7 @@ static int clean_an_unclean_leb(const struct ubifs_info *c, * * This function returns %0 on success and a negative error code on failure. */ -int ubifs_clean_lebs(const struct ubifs_info *c, void *sbuf) +int ubifs_clean_lebs(struct ubifs_info *c, void *sbuf) { dbg_rcvry("recovery"); while (!list_empty(&c->unclean_leb_list)) { @@ -996,6 +1106,140 @@ int ubifs_clean_lebs(const struct ubifs_info *c, void *sbuf) return 0; } +#ifndef __UBOOT__ +/** + * grab_empty_leb - grab an empty LEB to use as GC LEB and run commit. + * @c: UBIFS file-system description object + * + * This is a helper function for 'ubifs_rcvry_gc_commit()' which grabs an empty + * LEB to be used as GC LEB (@c->gc_lnum), and then runs the commit. Returns + * zero in case of success and a negative error code in case of failure. + */ +static int grab_empty_leb(struct ubifs_info *c) +{ + int lnum, err; + + /* + * Note, it is very important to first search for an empty LEB and then + * run the commit, not vice-versa. The reason is that there might be + * only one empty LEB at the moment, the one which has been the + * @c->gc_lnum just before the power cut happened. During the regular + * UBIFS operation (not now) @c->gc_lnum is marked as "taken", so no + * one but GC can grab it. But at this moment this single empty LEB is + * not marked as taken, so if we run commit - what happens? Right, the + * commit will grab it and write the index there. Remember that the + * index always expands as long as there is free space, and it only + * starts consolidating when we run out of space. + * + * IOW, if we run commit now, we might not be able to find a free LEB + * after this. + */ + lnum = ubifs_find_free_leb_for_idx(c); + if (lnum < 0) { + ubifs_err("could not find an empty LEB"); + ubifs_dump_lprops(c); + ubifs_dump_budg(c, &c->bi); + return lnum; + } + + /* Reset the index flag */ + err = ubifs_change_one_lp(c, lnum, LPROPS_NC, LPROPS_NC, 0, + LPROPS_INDEX, 0); + if (err) + return err; + + c->gc_lnum = lnum; + dbg_rcvry("found empty LEB %d, run commit", lnum); + + return ubifs_run_commit(c); +} + +/** + * ubifs_rcvry_gc_commit - recover the GC LEB number and run the commit. + * @c: UBIFS file-system description object + * + * Out-of-place garbage collection requires always one empty LEB with which to + * start garbage collection. The LEB number is recorded in c->gc_lnum and is + * written to the master node on unmounting. In the case of an unclean unmount + * the value of gc_lnum recorded in the master node is out of date and cannot + * be used. Instead, recovery must allocate an empty LEB for this purpose. + * However, there may not be enough empty space, in which case it must be + * possible to GC the dirtiest LEB into the GC head LEB. + * + * This function also runs the commit which causes the TNC updates from + * size-recovery and orphans to be written to the flash. That is important to + * ensure correct replay order for subsequent mounts. + * + * This function returns %0 on success and a negative error code on failure. + */ +int ubifs_rcvry_gc_commit(struct ubifs_info *c) +{ + struct ubifs_wbuf *wbuf = &c->jheads[GCHD].wbuf; + struct ubifs_lprops lp; + int err; + + dbg_rcvry("GC head LEB %d, offs %d", wbuf->lnum, wbuf->offs); + + c->gc_lnum = -1; + if (wbuf->lnum == -1 || wbuf->offs == c->leb_size) + return grab_empty_leb(c); + + err = ubifs_find_dirty_leb(c, &lp, wbuf->offs, 2); + if (err) { + if (err != -ENOSPC) + return err; + + dbg_rcvry("could not find a dirty LEB"); + return grab_empty_leb(c); + } + + ubifs_assert(!(lp.flags & LPROPS_INDEX)); + ubifs_assert(lp.free + lp.dirty >= wbuf->offs); + + /* + * We run the commit before garbage collection otherwise subsequent + * mounts will see the GC and orphan deletion in a different order. + */ + dbg_rcvry("committing"); + err = ubifs_run_commit(c); + if (err) + return err; + + dbg_rcvry("GC'ing LEB %d", lp.lnum); + mutex_lock_nested(&wbuf->io_mutex, wbuf->jhead); + err = ubifs_garbage_collect_leb(c, &lp); + if (err >= 0) { + int err2 = ubifs_wbuf_sync_nolock(wbuf); + + if (err2) + err = err2; + } + mutex_unlock(&wbuf->io_mutex); + if (err < 0) { + ubifs_err("GC failed, error %d", err); + if (err == -EAGAIN) + err = -EINVAL; + return err; + } + + ubifs_assert(err == LEB_RETAINED); + if (err != LEB_RETAINED) + return -EINVAL; + + err = ubifs_leb_unmap(c, c->gc_lnum); + if (err) + return err; + + dbg_rcvry("allocated LEB %d for GC", lp.lnum); + return 0; +} +#else +int ubifs_rcvry_gc_commit(struct ubifs_info *c) +{ + return 0; +} +#endif + /** * struct size_entry - inode size information for recovery. * @rb: link in the RB-tree of sizes @@ -1089,6 +1333,23 @@ static void remove_ino(struct ubifs_info *c, ino_t inum) kfree(e); } +/** + * ubifs_destroy_size_tree - free resources related to the size tree. + * @c: UBIFS file-system description object + */ +void ubifs_destroy_size_tree(struct ubifs_info *c) +{ + struct size_entry *e, *n; + + rbtree_postorder_for_each_entry_safe(e, n, &c->size_tree, rb) { + if (e->inode) + iput(e->inode); + kfree(e); + } + + c->size_tree = RB_ROOT; +} + /** * ubifs_recover_size_accum - accumulate inode sizes for recovery. * @c: UBIFS file-system description object @@ -1157,6 +1418,64 @@ int ubifs_recover_size_accum(struct ubifs_info *c, union ubifs_key *key, return 0; } +#ifndef __UBOOT__ +/** + * fix_size_in_place - fix inode size in place on flash. + * @c: UBIFS file-system description object + * @e: inode size information for recovery + */ +static int fix_size_in_place(struct ubifs_info *c, struct size_entry *e) +{ + struct ubifs_ino_node *ino = c->sbuf; + unsigned char *p; + union ubifs_key key; + int err, lnum, offs, len; + loff_t i_size; + uint32_t crc; + + /* Locate the inode node LEB number and offset */ + ino_key_init(c, &key, e->inum); + err = ubifs_tnc_locate(c, &key, ino, &lnum, &offs); + if (err) + goto out; + /* + * If the size recorded on the inode node is greater than the size that + * was calculated from nodes in the journal then don't change the inode. + */ + i_size = le64_to_cpu(ino->size); + if (i_size >= e->d_size) + return 0; + /* Read the LEB */ + err = ubifs_leb_read(c, lnum, c->sbuf, 0, c->leb_size, 1); + if (err) + goto out; + /* Change the size field and recalculate the CRC */ + ino = c->sbuf + offs; + ino->size = cpu_to_le64(e->d_size); + len = le32_to_cpu(ino->ch.len); + crc = crc32(UBIFS_CRC32_INIT, (void *)ino + 8, len - 8); + ino->ch.crc = cpu_to_le32(crc); + /* Work out where data in the LEB ends and free space begins */ + p = c->sbuf; + len = c->leb_size - 1; + while (p[len] == 0xff) + len -= 1; + len = ALIGN(len + 1, c->min_io_size); + /* Atomically write the fixed LEB back again */ + err = ubifs_leb_change(c, lnum, c->sbuf, len); + if (err) + goto out; + dbg_rcvry("inode %lu at %d:%d size %lld -> %lld", + (unsigned long)e->inum, lnum, offs, i_size, e->d_size); + return 0; + +out: + ubifs_warn("inode %lu failed to fix size %lld -> %lld error %d", + (unsigned long)e->inum, e->i_size, e->d_size, err); + return err; +} +#endif + /** * ubifs_recover_size - recover inode size. * @c: UBIFS file-system description object @@ -1196,30 +1515,48 @@ int ubifs_recover_size(struct ubifs_info *c) e->i_size = le64_to_cpu(ino->size); } } + if (e->exists && e->i_size < e->d_size) { - if (!e->inode && (c->vfs_sb->s_flags & MS_RDONLY)) { + if (c->ro_mount) { /* Fix the inode size and pin it in memory */ struct inode *inode; + struct ubifs_inode *ui; + + ubifs_assert(!e->inode); inode = ubifs_iget(c->vfs_sb, e->inum); if (IS_ERR(inode)) return PTR_ERR(inode); + + ui = ubifs_inode(inode); if (inode->i_size < e->d_size) { dbg_rcvry("ino %lu size %lld -> %lld", (unsigned long)e->inum, - e->d_size, inode->i_size); + inode->i_size, e->d_size); inode->i_size = e->d_size; - ubifs_inode(inode)->ui_size = e->d_size; + ui->ui_size = e->d_size; + ui->synced_i_size = e->d_size; e->inode = inode; this = rb_next(this); continue; } iput(inode); +#ifndef __UBOOT__ + } else { + /* Fix the size in place */ + err = fix_size_in_place(c, e); + if (err) + return err; + if (e->inode) + iput(e->inode); +#endif } } + this = rb_next(this); rb_erase(&e->rb, &c->size_tree); kfree(e); } + return 0; } diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c index da33a14ab6..7268b37a49 100644 --- a/fs/ubifs/replay.c +++ b/fs/ubifs/replay.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Adrian Hunter * Artem Bityutskiy (Битюцкий Артём) @@ -32,44 +21,37 @@ * larger is the journal, the more memory its index may consume. */ +#ifdef __UBOOT__ +#include +#include +#endif #include "ubifs.h" - -/* - * Replay flags. - * - * REPLAY_DELETION: node was deleted - * REPLAY_REF: node is a reference node - */ -enum { - REPLAY_DELETION = 1, - REPLAY_REF = 2, -}; +#include /** - * struct replay_entry - replay tree entry. + * struct replay_entry - replay list entry. * @lnum: logical eraseblock number of the node * @offs: node offset * @len: node length + * @deletion: non-zero if this entry corresponds to a node deletion * @sqnum: node sequence number - * @flags: replay flags - * @rb: links the replay tree + * @list: links the replay list * @key: node key * @nm: directory entry name * @old_size: truncation old size * @new_size: truncation new size - * @free: amount of free space in a bud - * @dirty: amount of dirty space in a bud from padding and deletion nodes * - * UBIFS journal replay must compare node sequence numbers, which means it must - * build a tree of node information to insert into the TNC. + * The replay process first scans all buds and builds the replay list, then + * sorts the replay list in nodes sequence number order, and then inserts all + * the replay entries to the TNC. */ struct replay_entry { int lnum; int offs; int len; + unsigned int deletion:1; unsigned long long sqnum; - int flags; - struct rb_node rb; + struct list_head list; union ubifs_key key; union { struct qstr nm; @@ -77,10 +59,6 @@ struct replay_entry { loff_t old_size; loff_t new_size; }; - struct { - int free; - int dirty; - }; }; }; @@ -88,82 +66,116 @@ struct replay_entry { * struct bud_entry - entry in the list of buds to replay. * @list: next bud in the list * @bud: bud description object - * @free: free bytes in the bud * @sqnum: reference node sequence number + * @free: free bytes in the bud + * @dirty: dirty bytes in the bud */ struct bud_entry { struct list_head list; struct ubifs_bud *bud; - int free; unsigned long long sqnum; + int free; + int dirty; }; +#ifndef __UBOOT__ /** * set_bud_lprops - set free and dirty space used by a bud. * @c: UBIFS file-system description object - * @r: replay entry of bud + * @b: bud entry which describes the bud + * + * This function makes sure the LEB properties of bud @b are set correctly + * after the replay. Returns zero in case of success and a negative error code + * in case of failure. */ -static int set_bud_lprops(struct ubifs_info *c, struct replay_entry *r) +static int set_bud_lprops(struct ubifs_info *c, struct bud_entry *b) { const struct ubifs_lprops *lp; int err = 0, dirty; ubifs_get_lprops(c); - lp = ubifs_lpt_lookup_dirty(c, r->lnum); + lp = ubifs_lpt_lookup_dirty(c, b->bud->lnum); if (IS_ERR(lp)) { err = PTR_ERR(lp); goto out; } dirty = lp->dirty; - if (r->offs == 0 && (lp->free != c->leb_size || lp->dirty != 0)) { + if (b->bud->start == 0 && (lp->free != c->leb_size || lp->dirty != 0)) { /* * The LEB was added to the journal with a starting offset of * zero which means the LEB must have been empty. The LEB - * property values should be lp->free == c->leb_size and - * lp->dirty == 0, but that is not the case. The reason is that - * the LEB was garbage collected. The garbage collector resets - * the free and dirty space without recording it anywhere except - * lprops, so if there is not a commit then lprops does not have - * that information next time the file system is mounted. + * property values should be @lp->free == @c->leb_size and + * @lp->dirty == 0, but that is not the case. The reason is that + * the LEB had been garbage collected before it became the bud, + * and there was not commit inbetween. The garbage collector + * resets the free and dirty space without recording it + * anywhere except lprops, so if there was no commit then + * lprops does not have that information. * * We do not need to adjust free space because the scan has told * us the exact value which is recorded in the replay entry as - * r->free. + * @b->free. * * However we do need to subtract from the dirty space the * amount of space that the garbage collector reclaimed, which * is the whole LEB minus the amount of space that was free. */ - dbg_mnt("bud LEB %d was GC'd (%d free, %d dirty)", r->lnum, + dbg_mnt("bud LEB %d was GC'd (%d free, %d dirty)", b->bud->lnum, lp->free, lp->dirty); - dbg_gc("bud LEB %d was GC'd (%d free, %d dirty)", r->lnum, + dbg_gc("bud LEB %d was GC'd (%d free, %d dirty)", b->bud->lnum, lp->free, lp->dirty); dirty -= c->leb_size - lp->free; /* * If the replay order was perfect the dirty space would now be - * zero. The order is not perfect because the the journal heads + * zero. The order is not perfect because the journal heads * race with each other. This is not a problem but is does mean * that the dirty space may temporarily exceed c->leb_size * during the replay. */ if (dirty != 0) - dbg_msg("LEB %d lp: %d free %d dirty " - "replay: %d free %d dirty", r->lnum, lp->free, - lp->dirty, r->free, r->dirty); + dbg_mnt("LEB %d lp: %d free %d dirty replay: %d free %d dirty", + b->bud->lnum, lp->free, lp->dirty, b->free, + b->dirty); } - lp = ubifs_change_lp(c, lp, r->free, dirty + r->dirty, + lp = ubifs_change_lp(c, lp, b->free, dirty + b->dirty, lp->flags | LPROPS_TAKEN, 0); if (IS_ERR(lp)) { err = PTR_ERR(lp); goto out; } + + /* Make sure the journal head points to the latest bud */ + err = ubifs_wbuf_seek_nolock(&c->jheads[b->bud->jhead].wbuf, + b->bud->lnum, c->leb_size - b->free); + out: ubifs_release_lprops(c); return err; } +/** + * set_buds_lprops - set free and dirty space for all replayed buds. + * @c: UBIFS file-system description object + * + * This function sets LEB properties for all replayed buds. Returns zero in + * case of success and a negative error code in case of failure. + */ +static int set_buds_lprops(struct ubifs_info *c) +{ + struct bud_entry *b; + int err; + + list_for_each_entry(b, &c->replay_buds, list) { + err = set_bud_lprops(c, b); + if (err) + return err; + } + + return 0; +} + /** * trun_remove_range - apply a replay entry for a truncation to the TNC. * @c: UBIFS file-system description object @@ -200,24 +212,22 @@ static int trun_remove_range(struct ubifs_info *c, struct replay_entry *r) */ static int apply_replay_entry(struct ubifs_info *c, struct replay_entry *r) { - int err, deletion = ((r->flags & REPLAY_DELETION) != 0); + int err; - dbg_mnt("LEB %d:%d len %d flgs %d sqnum %llu %s", r->lnum, - r->offs, r->len, r->flags, r->sqnum, DBGKEY(&r->key)); + dbg_mntk(&r->key, "LEB %d:%d len %d deletion %d sqnum %llu key ", + r->lnum, r->offs, r->len, r->deletion, r->sqnum); /* Set c->replay_sqnum to help deal with dangling branches. */ c->replay_sqnum = r->sqnum; - if (r->flags & REPLAY_REF) - err = set_bud_lprops(c, r); - else if (is_hash_key(c, &r->key)) { - if (deletion) + if (is_hash_key(c, &r->key)) { + if (r->deletion) err = ubifs_tnc_remove_nm(c, &r->key, &r->nm); else err = ubifs_tnc_add_nm(c, &r->key, r->lnum, r->offs, r->len, &r->nm); } else { - if (deletion) + if (r->deletion) switch (key_type(c, &r->key)) { case UBIFS_INO_KEY: { @@ -240,7 +250,7 @@ static int apply_replay_entry(struct ubifs_info *c, struct replay_entry *r) return err; if (c->need_recovery) - err = ubifs_recover_size_accum(c, &r->key, deletion, + err = ubifs_recover_size_accum(c, &r->key, r->deletion, r->new_size); } @@ -248,68 +258,77 @@ static int apply_replay_entry(struct ubifs_info *c, struct replay_entry *r) } /** - * destroy_replay_tree - destroy the replay. - * @c: UBIFS file-system description object + * replay_entries_cmp - compare 2 replay entries. + * @priv: UBIFS file-system description object + * @a: first replay entry + * @a: second replay entry * - * Destroy the replay tree. + * This is a comparios function for 'list_sort()' which compares 2 replay + * entries @a and @b by comparing their sequence numer. Returns %1 if @a has + * greater sequence number and %-1 otherwise. */ -static void destroy_replay_tree(struct ubifs_info *c) +static int replay_entries_cmp(void *priv, struct list_head *a, + struct list_head *b) { - struct rb_node *this = c->replay_tree.rb_node; - struct replay_entry *r; - - while (this) { - if (this->rb_left) { - this = this->rb_left; - continue; - } else if (this->rb_right) { - this = this->rb_right; - continue; - } - r = rb_entry(this, struct replay_entry, rb); - this = rb_parent(this); - if (this) { - if (this->rb_left == &r->rb) - this->rb_left = NULL; - else - this->rb_right = NULL; - } - if (is_hash_key(c, &r->key)) - kfree((void *)r->nm.name); - kfree(r); - } - c->replay_tree = RB_ROOT; + struct replay_entry *ra, *rb; + + cond_resched(); + if (a == b) + return 0; + + ra = list_entry(a, struct replay_entry, list); + rb = list_entry(b, struct replay_entry, list); + ubifs_assert(ra->sqnum != rb->sqnum); + if (ra->sqnum > rb->sqnum) + return 1; + return -1; } /** - * apply_replay_tree - apply the replay tree to the TNC. + * apply_replay_list - apply the replay list to the TNC. * @c: UBIFS file-system description object * - * Apply the replay tree. - * Returns zero in case of success and a negative error code in case of - * failure. + * Apply all entries in the replay list to the TNC. Returns zero in case of + * success and a negative error code in case of failure. */ -static int apply_replay_tree(struct ubifs_info *c) +static int apply_replay_list(struct ubifs_info *c) { - struct rb_node *this = rb_first(&c->replay_tree); + struct replay_entry *r; + int err; - while (this) { - struct replay_entry *r; - int err; + list_sort(c, &c->replay_list, &replay_entries_cmp); + list_for_each_entry(r, &c->replay_list, list) { cond_resched(); - r = rb_entry(this, struct replay_entry, rb); err = apply_replay_entry(c, r); if (err) return err; - this = rb_next(this); } + return 0; } /** - * insert_node - insert a node to the replay tree. + * destroy_replay_list - destroy the replay. + * @c: UBIFS file-system description object + * + * Destroy the replay list. + */ +static void destroy_replay_list(struct ubifs_info *c) +{ + struct replay_entry *r, *tmp; + + list_for_each_entry_safe(r, tmp, &c->replay_list, list) { + if (is_hash_key(c, &r->key)) + kfree(r->nm.name); + list_del(&r->list); + kfree(r); + } +} + +/** + * insert_node - insert a node to the replay list * @c: UBIFS file-system description object * @lnum: node logical eraseblock number * @offs: node offset @@ -321,39 +340,25 @@ static int apply_replay_tree(struct ubifs_info *c) * @old_size: truncation old size * @new_size: truncation new size * - * This function inserts a scanned non-direntry node to the replay tree. The - * replay tree is an RB-tree containing @struct replay_entry elements which are - * indexed by the sequence number. The replay tree is applied at the very end - * of the replay process. Since the tree is sorted in sequence number order, - * the older modifications are applied first. This function returns zero in - * case of success and a negative error code in case of failure. + * This function inserts a scanned non-direntry node to the replay list. The + * replay list contains @struct replay_entry elements, and we sort this list in + * sequence number order before applying it. The replay list is applied at the + * very end of the replay process. Since the list is sorted in sequence number + * order, the older modifications are applied first. This function returns zero + * in case of success and a negative error code in case of failure. */ static int insert_node(struct ubifs_info *c, int lnum, int offs, int len, union ubifs_key *key, unsigned long long sqnum, int deletion, int *used, loff_t old_size, loff_t new_size) { - struct rb_node **p = &c->replay_tree.rb_node, *parent = NULL; struct replay_entry *r; + dbg_mntk(key, "add LEB %d:%d, key ", lnum, offs); + if (key_inum(c, key) >= c->highest_inum) c->highest_inum = key_inum(c, key); - dbg_mnt("add LEB %d:%d, key %s", lnum, offs, DBGKEY(key)); - while (*p) { - parent = *p; - r = rb_entry(parent, struct replay_entry, rb); - if (sqnum < r->sqnum) { - p = &(*p)->rb_left; - continue; - } else if (sqnum > r->sqnum) { - p = &(*p)->rb_right; - continue; - } - ubifs_err("duplicate sqnum in replay"); - return -EINVAL; - } - r = kzalloc(sizeof(struct replay_entry), GFP_KERNEL); if (!r) return -ENOMEM; @@ -363,19 +368,18 @@ static int insert_node(struct ubifs_info *c, int lnum, int offs, int len, r->lnum = lnum; r->offs = offs; r->len = len; + r->deletion = !!deletion; r->sqnum = sqnum; - r->flags = (deletion ? REPLAY_DELETION : 0); + key_copy(c, key, &r->key); r->old_size = old_size; r->new_size = new_size; - key_copy(c, key, &r->key); - rb_link_node(&r->rb, parent, p); - rb_insert_color(&r->rb, &c->replay_tree); + list_add_tail(&r->list, &c->replay_list); return 0; } /** - * insert_dent - insert a directory entry node into the replay tree. + * insert_dent - insert a directory entry node into the replay list. * @c: UBIFS file-system description object * @lnum: node logical eraseblock number * @offs: node offset @@ -387,43 +391,25 @@ static int insert_node(struct ubifs_info *c, int lnum, int offs, int len, * @deletion: non-zero if this is a deletion * @used: number of bytes in use in a LEB * - * This function inserts a scanned directory entry node to the replay tree. - * Returns zero in case of success and a negative error code in case of - * failure. - * - * This function is also used for extended attribute entries because they are - * implemented as directory entry nodes. + * This function inserts a scanned directory entry node or an extended + * attribute entry to the replay list. Returns zero in case of success and a + * negative error code in case of failure. */ static int insert_dent(struct ubifs_info *c, int lnum, int offs, int len, union ubifs_key *key, const char *name, int nlen, unsigned long long sqnum, int deletion, int *used) { - struct rb_node **p = &c->replay_tree.rb_node, *parent = NULL; struct replay_entry *r; char *nbuf; + dbg_mntk(key, "add LEB %d:%d, key ", lnum, offs); if (key_inum(c, key) >= c->highest_inum) c->highest_inum = key_inum(c, key); - dbg_mnt("add LEB %d:%d, key %s", lnum, offs, DBGKEY(key)); - while (*p) { - parent = *p; - r = rb_entry(parent, struct replay_entry, rb); - if (sqnum < r->sqnum) { - p = &(*p)->rb_left; - continue; - } - if (sqnum > r->sqnum) { - p = &(*p)->rb_right; - continue; - } - ubifs_err("duplicate sqnum in replay"); - return -EINVAL; - } - r = kzalloc(sizeof(struct replay_entry), GFP_KERNEL); if (!r) return -ENOMEM; + nbuf = kmalloc(nlen + 1, GFP_KERNEL); if (!nbuf) { kfree(r); @@ -435,19 +421,18 @@ static int insert_dent(struct ubifs_info *c, int lnum, int offs, int len, r->lnum = lnum; r->offs = offs; r->len = len; + r->deletion = !!deletion; r->sqnum = sqnum; + key_copy(c, key, &r->key); r->nm.len = nlen; memcpy(nbuf, name, nlen); nbuf[nlen] = '\0'; r->nm.name = nbuf; - r->flags = (deletion ? REPLAY_DELETION : 0); - key_copy(c, key, &r->key); - ubifs_assert(!*p); - rb_link_node(&r->rb, parent, p); - rb_insert_color(&r->rb, &c->replay_tree); + list_add_tail(&r->list, &c->replay_list); return 0; } +#endif /** * ubifs_validate_entry - validate directory or extended attribute entry node. @@ -466,7 +451,7 @@ int ubifs_validate_entry(struct ubifs_info *c, if (le32_to_cpu(dent->ch.len) != nlen + UBIFS_DENT_NODE_SZ + 1 || dent->type >= UBIFS_ITYPES_CNT || nlen > UBIFS_MAX_NLEN || dent->name[nlen] != 0 || - strnlen((char *)dent->name, nlen) != nlen || + strnlen(dent->name, nlen) != nlen || le64_to_cpu(dent->inum) > MAX_INUM) { ubifs_err("bad %s node", key_type == UBIFS_DENT_KEY ? "directory entry" : "extended attribute entry"); @@ -481,32 +466,94 @@ int ubifs_validate_entry(struct ubifs_info *c, return 0; } +#ifndef __UBOOT__ +/** + * is_last_bud - check if the bud is the last in the journal head. + * @c: UBIFS file-system description object + * @bud: bud description object + * + * This function checks if bud @bud is the last bud in its journal head. This + * information is then used by 'replay_bud()' to decide whether the bud can + * have corruptions or not. Indeed, only last buds can be corrupted by power + * cuts. Returns %1 if this is the last bud, and %0 if not. + */ +static int is_last_bud(struct ubifs_info *c, struct ubifs_bud *bud) +{ + struct ubifs_jhead *jh = &c->jheads[bud->jhead]; + struct ubifs_bud *next; + uint32_t data; + int err; + + if (list_is_last(&bud->list, &jh->buds_list)) + return 1; + + /* + * The following is a quirk to make sure we work correctly with UBIFS + * images used with older UBIFS. + * + * Normally, the last bud will be the last in the journal head's list + * of bud. However, there is one exception if the UBIFS image belongs + * to older UBIFS. This is fairly unlikely: one would need to use old + * UBIFS, then have a power cut exactly at the right point, and then + * try to mount this image with new UBIFS. + * + * The exception is: it is possible to have 2 buds A and B, A goes + * before B, and B is the last, bud B is contains no data, and bud A is + * corrupted at the end. The reason is that in older versions when the + * journal code switched the next bud (from A to B), it first added a + * log reference node for the new bud (B), and only after this it + * synchronized the write-buffer of current bud (A). But later this was + * changed and UBIFS started to always synchronize the write-buffer of + * the bud (A) before writing the log reference for the new bud (B). + * + * But because older UBIFS always synchronized A's write-buffer before + * writing to B, we can recognize this exceptional situation but + * checking the contents of bud B - if it is empty, then A can be + * treated as the last and we can recover it. + * + * TODO: remove this piece of code in a couple of years (today it is + * 16.05.2011). + */ + next = list_entry(bud->list.next, struct ubifs_bud, list); + if (!list_is_last(&next->list, &jh->buds_list)) + return 0; + + err = ubifs_leb_read(c, next->lnum, (char *)&data, next->start, 4, 1); + if (err) + return 0; + + return data == 0xFFFFFFFF; +} + /** * replay_bud - replay a bud logical eraseblock. * @c: UBIFS file-system description object - * @lnum: bud logical eraseblock number to replay - * @offs: bud start offset - * @jhead: journal head to which this bud belongs - * @free: amount of free space in the bud is returned here - * @dirty: amount of dirty space from padding and deletion nodes is returned - * here + * @b: bud entry which describes the bud * - * This function returns zero in case of success and a negative error code in - * case of failure. + * This function replays bud @bud, recovers it if needed, and adds all nodes + * from this bud to the replay list. Returns zero in case of success and a + * negative error code in case of failure. */ -static int replay_bud(struct ubifs_info *c, int lnum, int offs, int jhead, - int *free, int *dirty) +static int replay_bud(struct ubifs_info *c, struct bud_entry *b) { - int err = 0, used = 0; + int is_last = is_last_bud(c, b->bud); + int err = 0, used = 0, lnum = b->bud->lnum, offs = b->bud->start; struct ubifs_scan_leb *sleb; struct ubifs_scan_node *snod; - struct ubifs_bud *bud; - dbg_mnt("replay bud LEB %d, head %d", lnum, jhead); - if (c->need_recovery) - sleb = ubifs_recover_leb(c, lnum, offs, c->sbuf, jhead != GCHD); + dbg_mnt("replay bud LEB %d, head %d, offs %d, is_last %d", + lnum, b->bud->jhead, offs, is_last); + + if (c->need_recovery && is_last) + /* + * Recover only last LEBs in the journal heads, because power + * cuts may cause corruptions only in these LEBs, because only + * these LEBs could possibly be written to at the power cut + * time. + */ + sleb = ubifs_recover_leb(c, lnum, offs, c->sbuf, b->bud->jhead); else - sleb = ubifs_scan(c, lnum, offs, c->sbuf); + sleb = ubifs_scan(c, lnum, offs, c->sbuf, 0); if (IS_ERR(sleb)) return PTR_ERR(sleb); @@ -580,7 +627,7 @@ static int replay_bud(struct ubifs_info *c, int lnum, int offs, int jhead, goto out_dump; err = insert_dent(c, lnum, snod->offs, snod->len, - &snod->key, (char *)dent->name, + &snod->key, dent->name, le16_to_cpu(dent->nlen), snod->sqnum, !le64_to_cpu(dent->inum), &used); break; @@ -620,15 +667,14 @@ static int replay_bud(struct ubifs_info *c, int lnum, int offs, int jhead, goto out; } - bud = ubifs_search_bud(c, lnum); - if (!bud) - BUG(); - + ubifs_assert(ubifs_search_bud(c, lnum)); ubifs_assert(sleb->endpt - offs >= used); ubifs_assert(sleb->endpt % c->min_io_size == 0); - *dirty = sleb->endpt - offs - used; - *free = c->leb_size - sleb->endpt; + b->dirty = sleb->endpt - offs - used; + b->free = c->leb_size - sleb->endpt; + dbg_mnt("bud LEB %d replied: dirty %d, free %d", + lnum, b->dirty, b->free); out: ubifs_scan_destroy(sleb); @@ -636,60 +682,11 @@ out: out_dump: ubifs_err("bad node is at LEB %d:%d", lnum, snod->offs); - dbg_dump_node(c, snod->node); + ubifs_dump_node(c, snod->node); ubifs_scan_destroy(sleb); return -EINVAL; } -/** - * insert_ref_node - insert a reference node to the replay tree. - * @c: UBIFS file-system description object - * @lnum: node logical eraseblock number - * @offs: node offset - * @sqnum: sequence number - * @free: amount of free space in bud - * @dirty: amount of dirty space from padding and deletion nodes - * - * This function inserts a reference node to the replay tree and returns zero - * in case of success or a negative error code in case of failure. - */ -static int insert_ref_node(struct ubifs_info *c, int lnum, int offs, - unsigned long long sqnum, int free, int dirty) -{ - struct rb_node **p = &c->replay_tree.rb_node, *parent = NULL; - struct replay_entry *r; - - dbg_mnt("add ref LEB %d:%d", lnum, offs); - while (*p) { - parent = *p; - r = rb_entry(parent, struct replay_entry, rb); - if (sqnum < r->sqnum) { - p = &(*p)->rb_left; - continue; - } else if (sqnum > r->sqnum) { - p = &(*p)->rb_right; - continue; - } - ubifs_err("duplicate sqnum in replay tree"); - return -EINVAL; - } - - r = kzalloc(sizeof(struct replay_entry), GFP_KERNEL); - if (!r) - return -ENOMEM; - - r->lnum = lnum; - r->offs = offs; - r->sqnum = sqnum; - r->flags = REPLAY_REF; - r->free = free; - r->dirty = dirty; - - rb_link_node(&r->rb, parent, p); - rb_insert_color(&r->rb, &c->replay_tree); - return 0; -} - /** * replay_buds - replay all buds. * @c: UBIFS file-system description object @@ -700,17 +697,16 @@ static int insert_ref_node(struct ubifs_info *c, int lnum, int offs, static int replay_buds(struct ubifs_info *c) { struct bud_entry *b; - int err, uninitialized_var(free), uninitialized_var(dirty); + int err; + unsigned long long prev_sqnum = 0; list_for_each_entry(b, &c->replay_buds, list) { - err = replay_bud(c, b->bud->lnum, b->bud->start, b->bud->jhead, - &free, &dirty); - if (err) - return err; - err = insert_ref_node(c, b->bud->lnum, b->bud->start, b->sqnum, - free, dirty); + err = replay_bud(c, b); if (err) return err; + + ubifs_assert(b->sqnum > prev_sqnum); + prev_sqnum = b->sqnum; } return 0; @@ -831,10 +827,16 @@ static int replay_log_leb(struct ubifs_info *c, int lnum, int offs, void *sbuf) const struct ubifs_cs_node *node; dbg_mnt("replay log LEB %d:%d", lnum, offs); - sleb = ubifs_scan(c, lnum, offs, sbuf); + sleb = ubifs_scan(c, lnum, offs, sbuf, c->need_recovery); if (IS_ERR(sleb)) { - if (c->need_recovery) - sleb = ubifs_recover_log_leb(c, lnum, offs, sbuf); + if (PTR_ERR(sleb) != -EUCLEAN || !c->need_recovery) + return PTR_ERR(sleb); + /* + * Note, the below function will recover this log LEB only if + * it is the last, because unclean reboots can possibly corrupt + * only the tail of the log. + */ + sleb = ubifs_recover_log_leb(c, lnum, offs, sbuf); if (IS_ERR(sleb)) return PTR_ERR(sleb); } @@ -845,7 +847,6 @@ static int replay_log_leb(struct ubifs_info *c, int lnum, int offs, void *sbuf) } node = sleb->buf; - snod = list_entry(sleb->nodes.next, struct ubifs_scan_node, list); if (c->cs_sqnum == 0) { /* @@ -856,16 +857,15 @@ static int replay_log_leb(struct ubifs_info *c, int lnum, int offs, void *sbuf) * numbers. */ if (snod->type != UBIFS_CS_NODE) { - dbg_err("first log node at LEB %d:%d is not CS node", - lnum, offs); + ubifs_err("first log node at LEB %d:%d is not CS node", + lnum, offs); goto out_dump; } if (le64_to_cpu(node->cmt_no) != c->cmt_no) { - dbg_err("first CS node at LEB %d:%d has wrong " - "commit number %llu expected %llu", - lnum, offs, - (unsigned long long)le64_to_cpu(node->cmt_no), - c->cmt_no); + ubifs_err("first CS node at LEB %d:%d has wrong commit number %llu expected %llu", + lnum, offs, + (unsigned long long)le64_to_cpu(node->cmt_no), + c->cmt_no); goto out_dump; } @@ -887,12 +887,11 @@ static int replay_log_leb(struct ubifs_info *c, int lnum, int offs, void *sbuf) /* Make sure the first node sits at offset zero of the LEB */ if (snod->offs != 0) { - dbg_err("first node is not at zero offset"); + ubifs_err("first node is not at zero offset"); goto out_dump; } list_for_each_entry(snod, &sleb->nodes, list) { - cond_resched(); if (snod->sqnum >= SQNUM_WATERMARK) { @@ -901,8 +900,8 @@ static int replay_log_leb(struct ubifs_info *c, int lnum, int offs, void *sbuf) } if (snod->sqnum < c->cs_sqnum) { - dbg_err("bad sqnum %llu, commit sqnum %llu", - snod->sqnum, c->cs_sqnum); + ubifs_err("bad sqnum %llu, commit sqnum %llu", + snod->sqnum, c->cs_sqnum); goto out_dump; } @@ -952,9 +951,9 @@ out: return err; out_dump: - ubifs_err("log error detected while replying the log at LEB %d:%d", + ubifs_err("log error detected while replaying the log at LEB %d:%d", lnum, offs + snod->offs); - dbg_dump_node(c, snod->node); + ubifs_dump_node(c, snod->node); ubifs_scan_destroy(sleb); return -EINVAL; } @@ -1004,67 +1003,64 @@ out: */ int ubifs_replay_journal(struct ubifs_info *c) { - int err, i, lnum, offs, _free; - void *sbuf = NULL; + int err, lnum, free; BUILD_BUG_ON(UBIFS_TRUN_KEY > 5); /* Update the status of the index head in lprops to 'taken' */ - _free = take_ihead(c); - if (_free < 0) - return _free; /* Error code */ + free = take_ihead(c); + if (free < 0) + return free; /* Error code */ - if (c->ihead_offs != c->leb_size - _free) { + if (c->ihead_offs != c->leb_size - free) { ubifs_err("bad index head LEB %d:%d", c->ihead_lnum, c->ihead_offs); return -EINVAL; } - sbuf = vmalloc(c->leb_size); - if (!sbuf) - return -ENOMEM; - dbg_mnt("start replaying the journal"); - c->replaying = 1; - lnum = c->ltail_lnum = c->lhead_lnum; - offs = c->lhead_offs; - for (i = 0; i < c->log_lebs; i++, lnum++) { - if (lnum >= UBIFS_LOG_LNUM + c->log_lebs) { - /* - * The log is logically circular, we reached the last - * LEB, switch to the first one. - */ - lnum = UBIFS_LOG_LNUM; - offs = 0; - } - err = replay_log_leb(c, lnum, offs, sbuf); + do { + err = replay_log_leb(c, lnum, 0, c->sbuf); if (err == 1) /* We hit the end of the log */ break; if (err) goto out; - offs = 0; - } + lnum = ubifs_next_log_lnum(c, lnum); + } while (lnum != c->ltail_lnum); err = replay_buds(c); if (err) goto out; - err = apply_replay_tree(c); + err = apply_replay_list(c); if (err) goto out; + err = set_buds_lprops(c); + if (err) + goto out; + + /* + * UBIFS budgeting calculations use @c->bi.uncommitted_idx variable + * to roughly estimate index growth. Things like @c->bi.min_idx_lebs + * depend on it. This means we have to initialize it to make sure + * budgeting works properly. + */ + c->bi.uncommitted_idx = atomic_long_read(&c->dirty_zn_cnt); + c->bi.uncommitted_idx *= c->max_idx_node_sz; + ubifs_assert(c->bud_bytes <= c->max_bud_bytes || c->need_recovery); - dbg_mnt("finished, log head LEB %d:%d, max_sqnum %llu, " - "highest_inum %lu", c->lhead_lnum, c->lhead_offs, c->max_sqnum, + dbg_mnt("finished, log head LEB %d:%d, max_sqnum %llu, highest_inum %lu", + c->lhead_lnum, c->lhead_offs, c->max_sqnum, (unsigned long)c->highest_inum); out: - destroy_replay_tree(c); + destroy_replay_list(c); destroy_bud_list(c); - vfree(sbuf); c->replaying = 0; return err; } +#endif diff --git a/fs/ubifs/sb.c b/fs/ubifs/sb.c index 00c9cd31a0..4983bf6289 100644 --- a/fs/ubifs/sb.c +++ b/fs/ubifs/sb.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -27,6 +16,17 @@ */ #include "ubifs.h" +#ifndef __UBOOT__ +#include +#include +#include +#else + +#include +#include +#include +#include +#endif /* * Default journal size in logical eraseblocks as a percent of total @@ -60,6 +60,282 @@ /* Default time granularity in nanoseconds */ #define DEFAULT_TIME_GRAN 1000000000 +#ifndef __UBOOT__ +/** + * create_default_filesystem - format empty UBI volume. + * @c: UBIFS file-system description object + * + * This function creates default empty file-system. Returns zero in case of + * success and a negative error code in case of failure. + */ +static int create_default_filesystem(struct ubifs_info *c) +{ + struct ubifs_sb_node *sup; + struct ubifs_mst_node *mst; + struct ubifs_idx_node *idx; + struct ubifs_branch *br; + struct ubifs_ino_node *ino; + struct ubifs_cs_node *cs; + union ubifs_key key; + int err, tmp, jnl_lebs, log_lebs, max_buds, main_lebs, main_first; + int lpt_lebs, lpt_first, orph_lebs, big_lpt, ino_waste, sup_flags = 0; + int min_leb_cnt = UBIFS_MIN_LEB_CNT; + long long tmp64, main_bytes; + __le64 tmp_le64; + + /* Some functions called from here depend on the @c->key_len filed */ + c->key_len = UBIFS_SK_LEN; + + /* + * First of all, we have to calculate default file-system geometry - + * log size, journal size, etc. + */ + if (c->leb_cnt < 0x7FFFFFFF / DEFAULT_JNL_PERCENT) + /* We can first multiply then divide and have no overflow */ + jnl_lebs = c->leb_cnt * DEFAULT_JNL_PERCENT / 100; + else + jnl_lebs = (c->leb_cnt / 100) * DEFAULT_JNL_PERCENT; + + if (jnl_lebs < UBIFS_MIN_JNL_LEBS) + jnl_lebs = UBIFS_MIN_JNL_LEBS; + if (jnl_lebs * c->leb_size > DEFAULT_MAX_JNL) + jnl_lebs = DEFAULT_MAX_JNL / c->leb_size; + + /* + * The log should be large enough to fit reference nodes for all bud + * LEBs. Because buds do not have to start from the beginning of LEBs + * (half of the LEB may contain committed data), the log should + * generally be larger, make it twice as large. + */ + tmp = 2 * (c->ref_node_alsz * jnl_lebs) + c->leb_size - 1; + log_lebs = tmp / c->leb_size; + /* Plus one LEB reserved for commit */ + log_lebs += 1; + if (c->leb_cnt - min_leb_cnt > 8) { + /* And some extra space to allow writes while committing */ + log_lebs += 1; + min_leb_cnt += 1; + } + + max_buds = jnl_lebs - log_lebs; + if (max_buds < UBIFS_MIN_BUD_LEBS) + max_buds = UBIFS_MIN_BUD_LEBS; + + /* + * Orphan nodes are stored in a separate area. One node can store a lot + * of orphan inode numbers, but when new orphan comes we just add a new + * orphan node. At some point the nodes are consolidated into one + * orphan node. + */ + orph_lebs = UBIFS_MIN_ORPH_LEBS; + if (c->leb_cnt - min_leb_cnt > 1) + /* + * For debugging purposes it is better to have at least 2 + * orphan LEBs, because the orphan subsystem would need to do + * consolidations and would be stressed more. + */ + orph_lebs += 1; + + main_lebs = c->leb_cnt - UBIFS_SB_LEBS - UBIFS_MST_LEBS - log_lebs; + main_lebs -= orph_lebs; + + lpt_first = UBIFS_LOG_LNUM + log_lebs; + c->lsave_cnt = DEFAULT_LSAVE_CNT; + c->max_leb_cnt = c->leb_cnt; + err = ubifs_create_dflt_lpt(c, &main_lebs, lpt_first, &lpt_lebs, + &big_lpt); + if (err) + return err; + + dbg_gen("LEB Properties Tree created (LEBs %d-%d)", lpt_first, + lpt_first + lpt_lebs - 1); + + main_first = c->leb_cnt - main_lebs; + + /* Create default superblock */ + tmp = ALIGN(UBIFS_SB_NODE_SZ, c->min_io_size); + sup = kzalloc(tmp, GFP_KERNEL); + if (!sup) + return -ENOMEM; + + tmp64 = (long long)max_buds * c->leb_size; + if (big_lpt) + sup_flags |= UBIFS_FLG_BIGLPT; + + sup->ch.node_type = UBIFS_SB_NODE; + sup->key_hash = UBIFS_KEY_HASH_R5; + sup->flags = cpu_to_le32(sup_flags); + sup->min_io_size = cpu_to_le32(c->min_io_size); + sup->leb_size = cpu_to_le32(c->leb_size); + sup->leb_cnt = cpu_to_le32(c->leb_cnt); + sup->max_leb_cnt = cpu_to_le32(c->max_leb_cnt); + sup->max_bud_bytes = cpu_to_le64(tmp64); + sup->log_lebs = cpu_to_le32(log_lebs); + sup->lpt_lebs = cpu_to_le32(lpt_lebs); + sup->orph_lebs = cpu_to_le32(orph_lebs); + sup->jhead_cnt = cpu_to_le32(DEFAULT_JHEADS_CNT); + sup->fanout = cpu_to_le32(DEFAULT_FANOUT); + sup->lsave_cnt = cpu_to_le32(c->lsave_cnt); + sup->fmt_version = cpu_to_le32(UBIFS_FORMAT_VERSION); + sup->time_gran = cpu_to_le32(DEFAULT_TIME_GRAN); + if (c->mount_opts.override_compr) + sup->default_compr = cpu_to_le16(c->mount_opts.compr_type); + else + sup->default_compr = cpu_to_le16(UBIFS_COMPR_LZO); + + generate_random_uuid(sup->uuid); + + main_bytes = (long long)main_lebs * c->leb_size; + tmp64 = div_u64(main_bytes * DEFAULT_RP_PERCENT, 100); + if (tmp64 > DEFAULT_MAX_RP_SIZE) + tmp64 = DEFAULT_MAX_RP_SIZE; + sup->rp_size = cpu_to_le64(tmp64); + sup->ro_compat_version = cpu_to_le32(UBIFS_RO_COMPAT_VERSION); + + err = ubifs_write_node(c, sup, UBIFS_SB_NODE_SZ, 0, 0); + kfree(sup); + if (err) + return err; + + dbg_gen("default superblock created at LEB 0:0"); + + /* Create default master node */ + mst = kzalloc(c->mst_node_alsz, GFP_KERNEL); + if (!mst) + return -ENOMEM; + + mst->ch.node_type = UBIFS_MST_NODE; + mst->log_lnum = cpu_to_le32(UBIFS_LOG_LNUM); + mst->highest_inum = cpu_to_le64(UBIFS_FIRST_INO); + mst->cmt_no = 0; + mst->root_lnum = cpu_to_le32(main_first + DEFAULT_IDX_LEB); + mst->root_offs = 0; + tmp = ubifs_idx_node_sz(c, 1); + mst->root_len = cpu_to_le32(tmp); + mst->gc_lnum = cpu_to_le32(main_first + DEFAULT_GC_LEB); + mst->ihead_lnum = cpu_to_le32(main_first + DEFAULT_IDX_LEB); + mst->ihead_offs = cpu_to_le32(ALIGN(tmp, c->min_io_size)); + mst->index_size = cpu_to_le64(ALIGN(tmp, 8)); + mst->lpt_lnum = cpu_to_le32(c->lpt_lnum); + mst->lpt_offs = cpu_to_le32(c->lpt_offs); + mst->nhead_lnum = cpu_to_le32(c->nhead_lnum); + mst->nhead_offs = cpu_to_le32(c->nhead_offs); + mst->ltab_lnum = cpu_to_le32(c->ltab_lnum); + mst->ltab_offs = cpu_to_le32(c->ltab_offs); + mst->lsave_lnum = cpu_to_le32(c->lsave_lnum); + mst->lsave_offs = cpu_to_le32(c->lsave_offs); + mst->lscan_lnum = cpu_to_le32(main_first); + mst->empty_lebs = cpu_to_le32(main_lebs - 2); + mst->idx_lebs = cpu_to_le32(1); + mst->leb_cnt = cpu_to_le32(c->leb_cnt); + + /* Calculate lprops statistics */ + tmp64 = main_bytes; + tmp64 -= ALIGN(ubifs_idx_node_sz(c, 1), c->min_io_size); + tmp64 -= ALIGN(UBIFS_INO_NODE_SZ, c->min_io_size); + mst->total_free = cpu_to_le64(tmp64); + + tmp64 = ALIGN(ubifs_idx_node_sz(c, 1), c->min_io_size); + ino_waste = ALIGN(UBIFS_INO_NODE_SZ, c->min_io_size) - + UBIFS_INO_NODE_SZ; + tmp64 += ino_waste; + tmp64 -= ALIGN(ubifs_idx_node_sz(c, 1), 8); + mst->total_dirty = cpu_to_le64(tmp64); + + /* The indexing LEB does not contribute to dark space */ + tmp64 = ((long long)(c->main_lebs - 1) * c->dark_wm); + mst->total_dark = cpu_to_le64(tmp64); + + mst->total_used = cpu_to_le64(UBIFS_INO_NODE_SZ); + + err = ubifs_write_node(c, mst, UBIFS_MST_NODE_SZ, UBIFS_MST_LNUM, 0); + if (err) { + kfree(mst); + return err; + } + err = ubifs_write_node(c, mst, UBIFS_MST_NODE_SZ, UBIFS_MST_LNUM + 1, + 0); + kfree(mst); + if (err) + return err; + + dbg_gen("default master node created at LEB %d:0", UBIFS_MST_LNUM); + + /* Create the root indexing node */ + tmp = ubifs_idx_node_sz(c, 1); + idx = kzalloc(ALIGN(tmp, c->min_io_size), GFP_KERNEL); + if (!idx) + return -ENOMEM; + + c->key_fmt = UBIFS_SIMPLE_KEY_FMT; + c->key_hash = key_r5_hash; + + idx->ch.node_type = UBIFS_IDX_NODE; + idx->child_cnt = cpu_to_le16(1); + ino_key_init(c, &key, UBIFS_ROOT_INO); + br = ubifs_idx_branch(c, idx, 0); + key_write_idx(c, &key, &br->key); + br->lnum = cpu_to_le32(main_first + DEFAULT_DATA_LEB); + br->len = cpu_to_le32(UBIFS_INO_NODE_SZ); + err = ubifs_write_node(c, idx, tmp, main_first + DEFAULT_IDX_LEB, 0); + kfree(idx); + if (err) + return err; + + dbg_gen("default root indexing node created LEB %d:0", + main_first + DEFAULT_IDX_LEB); + + /* Create default root inode */ + tmp = ALIGN(UBIFS_INO_NODE_SZ, c->min_io_size); + ino = kzalloc(tmp, GFP_KERNEL); + if (!ino) + return -ENOMEM; + + ino_key_init_flash(c, &ino->key, UBIFS_ROOT_INO); + ino->ch.node_type = UBIFS_INO_NODE; + ino->creat_sqnum = cpu_to_le64(++c->max_sqnum); + ino->nlink = cpu_to_le32(2); + tmp_le64 = cpu_to_le64(CURRENT_TIME_SEC.tv_sec); + ino->atime_sec = tmp_le64; + ino->ctime_sec = tmp_le64; + ino->mtime_sec = tmp_le64; + ino->atime_nsec = 0; + ino->ctime_nsec = 0; + ino->mtime_nsec = 0; + ino->mode = cpu_to_le32(S_IFDIR | S_IRUGO | S_IWUSR | S_IXUGO); + ino->size = cpu_to_le64(UBIFS_INO_NODE_SZ); + + /* Set compression enabled by default */ + ino->flags = cpu_to_le32(UBIFS_COMPR_FL); + + err = ubifs_write_node(c, ino, UBIFS_INO_NODE_SZ, + main_first + DEFAULT_DATA_LEB, 0); + kfree(ino); + if (err) + return err; + + dbg_gen("root inode created at LEB %d:0", + main_first + DEFAULT_DATA_LEB); + + /* + * The first node in the log has to be the commit start node. This is + * always the case during normal file-system operation. Write a fake + * commit start node to the log. + */ + tmp = ALIGN(UBIFS_CS_NODE_SZ, c->min_io_size); + cs = kzalloc(tmp, GFP_KERNEL); + if (!cs) + return -ENOMEM; + + cs->ch.node_type = UBIFS_CS_NODE; + err = ubifs_write_node(c, cs, UBIFS_CS_NODE_SZ, UBIFS_LOG_LNUM, 0); + kfree(cs); + + ubifs_msg("default file-system created"); + return 0; +} +#endif + /** * validate_sb - validate superblock node. * @c: UBIFS file-system description object @@ -114,9 +390,8 @@ static int validate_sb(struct ubifs_info *c, struct ubifs_sb_node *sup) min_leb_cnt += c->lpt_lebs + c->orph_lebs + c->jhead_cnt + 6; if (c->leb_cnt < min_leb_cnt || c->leb_cnt > c->vi.size) { - ubifs_err("bad LEB count: %d in superblock, %d on UBI volume, " - "%d minimum required", c->leb_cnt, c->vi.size, - min_leb_cnt); + ubifs_err("bad LEB count: %d in superblock, %d on UBI volume, %d minimum required", + c->leb_cnt, c->vi.size, min_leb_cnt); goto failed; } @@ -127,13 +402,22 @@ static int validate_sb(struct ubifs_info *c, struct ubifs_sb_node *sup) } if (c->main_lebs < UBIFS_MIN_MAIN_LEBS) { - err = 7; + ubifs_err("too few main LEBs count %d, must be at least %d", + c->main_lebs, UBIFS_MIN_MAIN_LEBS); + goto failed; + } + + max_bytes = (long long)c->leb_size * UBIFS_MIN_BUD_LEBS; + if (c->max_bud_bytes < max_bytes) { + ubifs_err("too small journal (%lld bytes), must be at least %lld bytes", + c->max_bud_bytes, max_bytes); goto failed; } - if (c->max_bud_bytes < (long long)c->leb_size * UBIFS_MIN_BUD_LEBS || - c->max_bud_bytes > (long long)c->leb_size * c->main_lebs) { - err = 8; + max_bytes = (long long)c->leb_size * c->main_lebs; + if (c->max_bud_bytes > max_bytes) { + ubifs_err("too large journal size (%lld bytes), only %lld bytes available in the main area", + c->max_bud_bytes, max_bytes); goto failed; } @@ -167,7 +451,6 @@ static int validate_sb(struct ubifs_info *c, struct ubifs_sb_node *sup) goto failed; } - max_bytes = c->main_lebs * (long long)c->leb_size; if (c->rp_size < 0 || max_bytes < c->rp_size) { err = 14; goto failed; @@ -183,7 +466,7 @@ static int validate_sb(struct ubifs_info *c, struct ubifs_sb_node *sup) failed: ubifs_err("bad superblock, error %d", err); - dbg_dump_node(c, sup); + ubifs_dump_node(c, sup); return -EINVAL; } @@ -192,7 +475,8 @@ failed: * @c: UBIFS file-system description object * * This function returns a pointer to the superblock node or a negative error - * code. + * code. Note, the user of this function is responsible of kfree()'ing the + * returned superblock buffer. */ struct ubifs_sb_node *ubifs_read_sb_node(struct ubifs_info *c) { @@ -213,6 +497,21 @@ struct ubifs_sb_node *ubifs_read_sb_node(struct ubifs_info *c) return sup; } +/** + * ubifs_write_sb_node - write superblock node. + * @c: UBIFS file-system description object + * @sup: superblock node read with 'ubifs_read_sb_node()' + * + * This function returns %0 on success and a negative error code on failure. + */ +int ubifs_write_sb_node(struct ubifs_info *c, struct ubifs_sb_node *sup) +{ + int len = ALIGN(UBIFS_SB_NODE_SZ, c->min_io_size); + + ubifs_prepare_node(c, sup, UBIFS_SB_NODE_SZ, 1); + return ubifs_leb_change(c, UBIFS_SB_LNUM, sup, len); +} + /** * ubifs_read_superblock - read superblock. * @c: UBIFS file-system description object @@ -227,8 +526,14 @@ int ubifs_read_superblock(struct ubifs_info *c) struct ubifs_sb_node *sup; if (c->empty) { +#ifndef __UBOOT__ + err = create_default_filesystem(c); + if (err) + return err; +#else printf("No UBIFS filesystem found!\n"); return -1; +#endif } sup = ubifs_read_sb_node(c); @@ -243,16 +548,12 @@ int ubifs_read_superblock(struct ubifs_info *c) * due to the unavailability of time-travelling equipment. */ if (c->fmt_version > UBIFS_FORMAT_VERSION) { - struct super_block *sb = c->vfs_sb; - int mounting_ro = sb->s_flags & MS_RDONLY; - - ubifs_assert(!c->ro_media || mounting_ro); - if (!mounting_ro || + ubifs_assert(!c->ro_media || c->ro_mount); + if (!c->ro_mount || c->ro_compat_version > UBIFS_RO_COMPAT_VERSION) { - ubifs_err("on-flash format version is w%d/r%d, but " - "software only supports up to version " - "w%d/r%d", c->fmt_version, - c->ro_compat_version, UBIFS_FORMAT_VERSION, + ubifs_err("on-flash format version is w%d/r%d, but software only supports up to version w%d/r%d", + c->fmt_version, c->ro_compat_version, + UBIFS_FORMAT_VERSION, UBIFS_RO_COMPAT_VERSION); if (c->ro_compat_version <= UBIFS_RO_COMPAT_VERSION) { ubifs_msg("only R/O mounting is possible"); @@ -310,22 +611,41 @@ int ubifs_read_superblock(struct ubifs_info *c) c->jhead_cnt = le32_to_cpu(sup->jhead_cnt) + NONDATA_JHEADS_CNT; c->fanout = le32_to_cpu(sup->fanout); c->lsave_cnt = le32_to_cpu(sup->lsave_cnt); - c->default_compr = le16_to_cpu(sup->default_compr); c->rp_size = le64_to_cpu(sup->rp_size); - c->rp_uid = le32_to_cpu(sup->rp_uid); - c->rp_gid = le32_to_cpu(sup->rp_gid); +#ifndef __UBOOT__ + c->rp_uid = make_kuid(&init_user_ns, le32_to_cpu(sup->rp_uid)); + c->rp_gid = make_kgid(&init_user_ns, le32_to_cpu(sup->rp_gid)); +#else + c->rp_uid.val = le32_to_cpu(sup->rp_uid); + c->rp_gid.val = le32_to_cpu(sup->rp_gid); +#endif sup_flags = le32_to_cpu(sup->flags); + if (!c->mount_opts.override_compr) + c->default_compr = le16_to_cpu(sup->default_compr); c->vfs_sb->s_time_gran = le32_to_cpu(sup->time_gran); memcpy(&c->uuid, &sup->uuid, 16); c->big_lpt = !!(sup_flags & UBIFS_FLG_BIGLPT); + c->space_fixup = !!(sup_flags & UBIFS_FLG_SPACE_FIXUP); /* Automatically increase file system size to the maximum size */ c->old_leb_cnt = c->leb_cnt; if (c->leb_cnt < c->vi.size && c->leb_cnt < c->max_leb_cnt) { c->leb_cnt = min_t(int, c->max_leb_cnt, c->vi.size); - dbg_mnt("Auto resizing (ro) from %d LEBs to %d LEBs", - c->old_leb_cnt, c->leb_cnt); + if (c->ro_mount) + dbg_mnt("Auto resizing (ro) from %d LEBs to %d LEBs", + c->old_leb_cnt, c->leb_cnt); +#ifndef __UBOOT__ + else { + dbg_mnt("Auto resizing (sb) from %d LEBs to %d LEBs", + c->old_leb_cnt, c->leb_cnt); + sup->leb_cnt = cpu_to_le32(c->leb_cnt); + err = ubifs_write_sb_node(c, sup); + if (err) + goto out; + c->old_leb_cnt = c->leb_cnt; + } +#endif } c->log_bytes = (long long)c->log_lebs * c->leb_size; @@ -337,10 +657,162 @@ int ubifs_read_superblock(struct ubifs_info *c) c->main_lebs = c->leb_cnt - UBIFS_SB_LEBS - UBIFS_MST_LEBS; c->main_lebs -= c->log_lebs + c->lpt_lebs + c->orph_lebs; c->main_first = c->leb_cnt - c->main_lebs; - c->report_rp_size = ubifs_reported_space(c, c->rp_size); err = validate_sb(c, sup); out: kfree(sup); return err; } + +/** + * fixup_leb - fixup/unmap an LEB containing free space. + * @c: UBIFS file-system description object + * @lnum: the LEB number to fix up + * @len: number of used bytes in LEB (starting at offset 0) + * + * This function reads the contents of the given LEB number @lnum, then fixes + * it up, so that empty min. I/O units in the end of LEB are actually erased on + * flash (rather than being just all-0xff real data). If the LEB is completely + * empty, it is simply unmapped. + */ +static int fixup_leb(struct ubifs_info *c, int lnum, int len) +{ + int err; + + ubifs_assert(len >= 0); + ubifs_assert(len % c->min_io_size == 0); + ubifs_assert(len < c->leb_size); + + if (len == 0) { + dbg_mnt("unmap empty LEB %d", lnum); + return ubifs_leb_unmap(c, lnum); + } + + dbg_mnt("fixup LEB %d, data len %d", lnum, len); + err = ubifs_leb_read(c, lnum, c->sbuf, 0, len, 1); + if (err) + return err; + + return ubifs_leb_change(c, lnum, c->sbuf, len); +} + +/** + * fixup_free_space - find & remap all LEBs containing free space. + * @c: UBIFS file-system description object + * + * This function walks through all LEBs in the filesystem and fiexes up those + * containing free/empty space. + */ +static int fixup_free_space(struct ubifs_info *c) +{ + int lnum, err = 0; + struct ubifs_lprops *lprops; + + ubifs_get_lprops(c); + + /* Fixup LEBs in the master area */ + for (lnum = UBIFS_MST_LNUM; lnum < UBIFS_LOG_LNUM; lnum++) { + err = fixup_leb(c, lnum, c->mst_offs + c->mst_node_alsz); + if (err) + goto out; + } + + /* Unmap unused log LEBs */ + lnum = ubifs_next_log_lnum(c, c->lhead_lnum); + while (lnum != c->ltail_lnum) { + err = fixup_leb(c, lnum, 0); + if (err) + goto out; + lnum = ubifs_next_log_lnum(c, lnum); + } + + /* + * Fixup the log head which contains the only a CS node at the + * beginning. + */ + err = fixup_leb(c, c->lhead_lnum, + ALIGN(UBIFS_CS_NODE_SZ, c->min_io_size)); + if (err) + goto out; + + /* Fixup LEBs in the LPT area */ + for (lnum = c->lpt_first; lnum <= c->lpt_last; lnum++) { + int free = c->ltab[lnum - c->lpt_first].free; + + if (free > 0) { + err = fixup_leb(c, lnum, c->leb_size - free); + if (err) + goto out; + } + } + + /* Unmap LEBs in the orphans area */ + for (lnum = c->orph_first; lnum <= c->orph_last; lnum++) { + err = fixup_leb(c, lnum, 0); + if (err) + goto out; + } + + /* Fixup LEBs in the main area */ + for (lnum = c->main_first; lnum < c->leb_cnt; lnum++) { + lprops = ubifs_lpt_lookup(c, lnum); + if (IS_ERR(lprops)) { + err = PTR_ERR(lprops); + goto out; + } + + if (lprops->free > 0) { + err = fixup_leb(c, lnum, c->leb_size - lprops->free); + if (err) + goto out; + } + } + +out: + ubifs_release_lprops(c); + return err; +} + +/** + * ubifs_fixup_free_space - find & fix all LEBs with free space. + * @c: UBIFS file-system description object + * + * This function fixes up LEBs containing free space on first mount, if the + * appropriate flag was set when the FS was created. Each LEB with one or more + * empty min. I/O unit (i.e. free-space-count > 0) is re-written, to make sure + * the free space is actually erased. E.g., this is necessary for some NAND + * chips, since the free space may have been programmed like real "0xff" data + * (generating a non-0xff ECC), causing future writes to the not-really-erased + * NAND pages to behave badly. After the space is fixed up, the superblock flag + * is cleared, so that this is skipped for all future mounts. + */ +int ubifs_fixup_free_space(struct ubifs_info *c) +{ + int err; + struct ubifs_sb_node *sup; + + ubifs_assert(c->space_fixup); + ubifs_assert(!c->ro_mount); + + ubifs_msg("start fixing up free space"); + + err = fixup_free_space(c); + if (err) + return err; + + sup = ubifs_read_sb_node(c); + if (IS_ERR(sup)) + return PTR_ERR(sup); + + /* Free-space fixup is no longer required */ + c->space_fixup = 0; + sup->flags &= cpu_to_le32(~UBIFS_FLG_SPACE_FIXUP); + + err = ubifs_write_sb_node(c, sup); + kfree(sup); + if (err) + return err; + + ubifs_msg("free space fixup complete"); + return err; +} diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c index 0ed82479b4..6fc464bb48 100644 --- a/fs/ubifs/scan.c +++ b/fs/ubifs/scan.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Adrian Hunter * Artem Bityutskiy (Битюцкий Артём) @@ -27,6 +16,9 @@ * debugging functions. */ +#ifdef __UBOOT__ +#include +#endif #include "ubifs.h" /** @@ -75,7 +67,7 @@ int ubifs_scan_a_node(const struct ubifs_info *c, void *buf, int len, int lnum, magic = le32_to_cpu(ch->magic); if (magic == 0xFFFFFFFF) { - dbg_scan("hit empty space"); + dbg_scan("hit empty space at LEB %d:%d", lnum, offs); return SCANNED_EMPTY_SPACE; } @@ -85,7 +77,8 @@ int ubifs_scan_a_node(const struct ubifs_info *c, void *buf, int len, int lnum, if (len < UBIFS_CH_SZ) return SCANNED_GARBAGE; - dbg_scan("scanning %s", dbg_ntype(ch->node_type)); + dbg_scan("scanning %s at LEB %d:%d", + dbg_ntype(ch->node_type), lnum, offs); if (ubifs_check_node(c, buf, lnum, offs, quiet, 1)) return SCANNED_A_CORRUPT_NODE; @@ -101,22 +94,21 @@ int ubifs_scan_a_node(const struct ubifs_info *c, void *buf, int len, int lnum, if (!quiet) { ubifs_err("bad pad node at LEB %d:%d", lnum, offs); - dbg_dump_node(c, pad); + ubifs_dump_node(c, pad); } return SCANNED_A_BAD_PAD_NODE; } /* Make the node pads to 8-byte boundary */ if ((node_len + pad_len) & 7) { - if (!quiet) { - dbg_err("bad padding length %d - %d", - offs, offs + node_len + pad_len); - } + if (!quiet) + ubifs_err("bad padding length %d - %d", + offs, offs + node_len + pad_len); return SCANNED_A_BAD_PAD_NODE; } - dbg_scan("%d bytes padded, offset now %d", - pad_len, ALIGN(offs + node_len + pad_len, 8)); + dbg_scan("%d bytes padded at LEB %d:%d, offset now %d", pad_len, + lnum, offs, ALIGN(offs + node_len + pad_len, 8)); return node_len + pad_len; } @@ -149,10 +141,10 @@ struct ubifs_scan_leb *ubifs_start_scan(const struct ubifs_info *c, int lnum, INIT_LIST_HEAD(&sleb->nodes); sleb->buf = sbuf; - err = ubi_read(c->ubi, lnum, sbuf + offs, offs, c->leb_size - offs); + err = ubifs_leb_read(c, lnum, sbuf + offs, offs, c->leb_size - offs, 0); if (err && err != -EBADMSG) { - ubifs_err("cannot read %d bytes from LEB %d:%d," - " error %d", c->leb_size - offs, lnum, offs, err); + ubifs_err("cannot read %d bytes from LEB %d:%d, error %d", + c->leb_size - offs, lnum, offs, err); kfree(sleb); return ERR_PTR(err); } @@ -198,7 +190,7 @@ int ubifs_add_snod(const struct ubifs_info *c, struct ubifs_scan_leb *sleb, struct ubifs_ino_node *ino = buf; struct ubifs_scan_node *snod; - snod = kzalloc(sizeof(struct ubifs_scan_node), GFP_NOFS); + snod = kmalloc(sizeof(struct ubifs_scan_node), GFP_NOFS); if (!snod) return -ENOMEM; @@ -213,13 +205,15 @@ int ubifs_add_snod(const struct ubifs_info *c, struct ubifs_scan_leb *sleb, case UBIFS_DENT_NODE: case UBIFS_XENT_NODE: case UBIFS_DATA_NODE: - case UBIFS_TRUN_NODE: /* * The key is in the same place in all keyed * nodes. */ key_read(c, &ino->key, &snod->key); break; + default: + invalid_key_init(c, &snod->key); + break; } list_add_tail(&snod->list, &sleb->nodes); sleb->nodes_cnt += 1; @@ -238,13 +232,11 @@ void ubifs_scanned_corruption(const struct ubifs_info *c, int lnum, int offs, { int len; - ubifs_err("corrupted data at LEB %d:%d", lnum, offs); - if (dbg_failure_mode) - return; + ubifs_err("corruption at LEB %d:%d", lnum, offs); len = c->leb_size - offs; - if (len > 4096) - len = 4096; - dbg_err("first %d bytes from LEB %d:%d", len, lnum, offs); + if (len > 8192) + len = 8192; + ubifs_err("first %d bytes from LEB %d:%d", len, lnum, offs); print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 4, buf, len, 1); } @@ -253,13 +245,19 @@ void ubifs_scanned_corruption(const struct ubifs_info *c, int lnum, int offs, * @c: UBIFS file-system description object * @lnum: logical eraseblock number * @offs: offset to start at (usually zero) - * @sbuf: scan buffer (must be c->leb_size) + * @sbuf: scan buffer (must be of @c->leb_size bytes in size) + * @quiet: print no messages * * This function scans LEB number @lnum and returns complete information about - * its contents. Returns an error code in case of failure. + * its contents. Returns the scaned information in case of success and, + * %-EUCLEAN if the LEB neads recovery, and other negative error codes in case + * of failure. + * + * If @quiet is non-zero, this function does not print large and scary + * error messages and flash dumps in case of errors. */ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, - int offs, void *sbuf) + int offs, void *sbuf, int quiet) { void *buf = sbuf + offs; int err, len = c->leb_size - offs; @@ -278,8 +276,7 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, cond_resched(); - ret = ubifs_scan_a_node(c, buf, len, lnum, offs, 0); - + ret = ubifs_scan_a_node(c, buf, len, lnum, offs, quiet); if (ret > 0) { /* Padding bytes or a valid padding node */ offs += ret; @@ -294,17 +291,18 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, switch (ret) { case SCANNED_GARBAGE: - dbg_err("garbage"); + ubifs_err("garbage"); goto corrupted; case SCANNED_A_NODE: break; case SCANNED_A_CORRUPT_NODE: case SCANNED_A_BAD_PAD_NODE: - dbg_err("bad node"); + ubifs_err("bad node"); goto corrupted; default: - dbg_err("unknown"); - goto corrupted; + ubifs_err("unknown"); + err = -EINVAL; + goto error; } err = ubifs_add_snod(c, sleb, buf, offs); @@ -317,8 +315,12 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, len -= node_len; } - if (offs % c->min_io_size) + if (offs % c->min_io_size) { + if (!quiet) + ubifs_err("empty space starts at non-aligned offset %d", + offs); goto corrupted; + } ubifs_end_scan(c, sleb, lnum, offs); @@ -327,18 +329,25 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, break; for (; len; offs++, buf++, len--) if (*(uint8_t *)buf != 0xff) { - ubifs_err("corrupt empty space at LEB %d:%d", - lnum, offs); + if (!quiet) + ubifs_err("corrupt empty space at LEB %d:%d", + lnum, offs); goto corrupted; } return sleb; corrupted: - ubifs_scanned_corruption(c, lnum, offs, buf); + if (!quiet) { + ubifs_scanned_corruption(c, lnum, offs, buf); + ubifs_err("LEB %d scanning failed", lnum); + } err = -EUCLEAN; + ubifs_scan_destroy(sleb); + return ERR_PTR(err); + error: - ubifs_err("LEB %d scanning failed", lnum); + ubifs_err("LEB %d scanning failed, error %d", lnum, err); ubifs_scan_destroy(sleb); return ERR_PTR(err); } diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 9acf243eef..01d449a7af 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -26,103 +15,44 @@ * corresponding subsystems, but most of it is here. */ -#include "ubifs.h" +#ifndef __UBOOT__ +#include +#include +#include +#include +#include +#include +#include +#include #include +#include +#else -#define INODE_LOCKED_MAX 64 +#include +#include +#include +#include "ubifs.h" +#include +#include -struct super_block *ubifs_sb; -static struct inode *inodes_locked_down[INODE_LOCKED_MAX]; +struct dentry; +struct file; +struct iattr; +struct kstat; +struct vfsmount; -/* shrinker.c */ +#define INODE_LOCKED_MAX 64 -/* List of all UBIFS file-system instances */ -struct list_head ubifs_infos; +struct super_block *ubifs_sb; +LIST_HEAD(super_blocks); -/* linux/fs/super.c */ +static struct inode *inodes_locked_down[INODE_LOCKED_MAX]; -static int sb_set(struct super_block *sb, void *data) +int set_anon_super(struct super_block *s, void *data) { - dev_t *dev = data; - - sb->s_dev = *dev; return 0; } -/** - * sget - find or create a superblock - * @type: filesystem type superblock should belong to - * @test: comparison callback - * @set: setup callback - * @data: argument to each of them - */ -struct super_block *sget(struct file_system_type *type, - int (*test)(struct super_block *,void *), - int (*set)(struct super_block *,void *), - void *data) -{ - struct super_block *s = NULL; - int err; - - s = kzalloc(sizeof(struct super_block), GFP_USER); - if (!s) { - err = -ENOMEM; - return ERR_PTR(err); - } - - INIT_LIST_HEAD(&s->s_instances); - INIT_LIST_HEAD(&s->s_inodes); - s->s_time_gran = 1000000000; - - err = set(s, data); - if (err) { - return ERR_PTR(err); - } - s->s_type = type; - strncpy(s->s_id, type->name, sizeof(s->s_id)); - list_add(&s->s_instances, &type->fs_supers); - return s; -} - -/** - * validate_inode - validate inode. - * @c: UBIFS file-system description object - * @inode: the inode to validate - * - * This is a helper function for 'ubifs_iget()' which validates various fields - * of a newly built inode to make sure they contain sane values and prevent - * possible vulnerabilities. Returns zero if the inode is all right and - * a non-zero error code if not. - */ -static int validate_inode(struct ubifs_info *c, const struct inode *inode) -{ - int err; - const struct ubifs_inode *ui = ubifs_inode(inode); - - if (inode->i_size > c->max_inode_sz) { - ubifs_err("inode is too large (%lld)", - (long long)inode->i_size); - return 1; - } - - if (ui->compr_type < 0 || ui->compr_type >= UBIFS_COMPR_TYPES_CNT) { - ubifs_err("unknown compression type %d", ui->compr_type); - return 2; - } - - if (ui->data_len < 0 || ui->data_len > UBIFS_MAX_INO_DATA) - return 4; - - if (!ubifs_compr_present(ui->compr_type)) { - ubifs_warn("inode %lu uses '%s' compression, but it was not " - "compiled in", inode->i_ino, - ubifs_compr_name(ui->compr_type)); - } - - err = dbg_check_dir_size(c, inode); - return err; -} - struct inode *iget_locked(struct super_block *sb, unsigned long ino) { struct inode *inode; @@ -138,6 +68,10 @@ struct inode *iget_locked(struct super_block *sb, unsigned long ino) return inode; } +void iget_failed(struct inode *inode) +{ +} + int ubifs_iput(struct inode *inode) { list_del_init(&inode->i_sb_list); @@ -179,6 +113,125 @@ void iput(struct inode *inode) inodes_locked_down[i] = ino; } +/* from fs/inode.c */ +/** + * clear_nlink - directly zero an inode's link count + * @inode: inode + * + * This is a low-level filesystem helper to replace any + * direct filesystem manipulation of i_nlink. See + * drop_nlink() for why we care about i_nlink hitting zero. + */ +void clear_nlink(struct inode *inode) +{ + if (inode->i_nlink) { + inode->__i_nlink = 0; + atomic_long_inc(&inode->i_sb->s_remove_count); + } +} +EXPORT_SYMBOL(clear_nlink); + +/** + * set_nlink - directly set an inode's link count + * @inode: inode + * @nlink: new nlink (should be non-zero) + * + * This is a low-level filesystem helper to replace any + * direct filesystem manipulation of i_nlink. + */ +void set_nlink(struct inode *inode, unsigned int nlink) +{ + if (!nlink) { + clear_nlink(inode); + } else { + /* Yes, some filesystems do change nlink from zero to one */ + if (inode->i_nlink == 0) + atomic_long_dec(&inode->i_sb->s_remove_count); + + inode->__i_nlink = nlink; + } +} +EXPORT_SYMBOL(set_nlink); + +/* from include/linux/fs.h */ +static inline void i_uid_write(struct inode *inode, uid_t uid) +{ + inode->i_uid.val = uid; +} + +static inline void i_gid_write(struct inode *inode, gid_t gid) +{ + inode->i_gid.val = gid; +} + +void unlock_new_inode(struct inode *inode) +{ + return; +} +#endif + +/* + * Maximum amount of memory we may 'kmalloc()' without worrying that we are + * allocating too much. + */ +#define UBIFS_KMALLOC_OK (128*1024) + +/* Slab cache for UBIFS inodes */ +struct kmem_cache *ubifs_inode_slab; + +#ifndef __UBOOT__ +/* UBIFS TNC shrinker description */ +static struct shrinker ubifs_shrinker_info = { + .scan_objects = ubifs_shrink_scan, + .count_objects = ubifs_shrink_count, + .seeks = DEFAULT_SEEKS, +}; +#endif + +/** + * validate_inode - validate inode. + * @c: UBIFS file-system description object + * @inode: the inode to validate + * + * This is a helper function for 'ubifs_iget()' which validates various fields + * of a newly built inode to make sure they contain sane values and prevent + * possible vulnerabilities. Returns zero if the inode is all right and + * a non-zero error code if not. + */ +static int validate_inode(struct ubifs_info *c, const struct inode *inode) +{ + int err; + const struct ubifs_inode *ui = ubifs_inode(inode); + + if (inode->i_size > c->max_inode_sz) { + ubifs_err("inode is too large (%lld)", + (long long)inode->i_size); + return 1; + } + + if (ui->compr_type < 0 || ui->compr_type >= UBIFS_COMPR_TYPES_CNT) { + ubifs_err("unknown compression type %d", ui->compr_type); + return 2; + } + + if (ui->xattr_names + ui->xattr_cnt > XATTR_LIST_MAX) + return 3; + + if (ui->data_len < 0 || ui->data_len > UBIFS_MAX_INO_DATA) + return 4; + + if (ui->xattr && !S_ISREG(inode->i_mode)) + return 5; + + if (!ubifs_compr_present(ui->compr_type)) { + ubifs_warn("inode %lu uses '%s' compression, but it was not compiled in", + inode->i_ino, ubifs_compr_name(ui->compr_type)); + } + + err = dbg_check_dir(c, inode); + return err; +} + struct inode *ubifs_iget(struct super_block *sb, unsigned long inum) { int err; @@ -187,10 +240,13 @@ struct inode *ubifs_iget(struct super_block *sb, unsigned long inum) struct ubifs_info *c = sb->s_fs_info; struct inode *inode; struct ubifs_inode *ui; +#ifdef __UBOOT__ int i; +#endif dbg_gen("inode %lu", inum); +#ifdef __UBOOT__ /* * U-Boot special handling of locked down inodes via recovery * e.g. ubifs_recover_size() @@ -211,6 +267,7 @@ struct inode *ubifs_iget(struct super_block *sb, unsigned long inum) return inodes_locked_down[i]; } } +#endif inode = iget_locked(sb, inum); if (!inode) @@ -232,9 +289,9 @@ struct inode *ubifs_iget(struct super_block *sb, unsigned long inum) goto out_ino; inode->i_flags |= (S_NOCMTIME | S_NOATIME); - inode->i_nlink = le32_to_cpu(ino->nlink); - inode->i_uid = le32_to_cpu(ino->uid); - inode->i_gid = le32_to_cpu(ino->gid); + set_nlink(inode, le32_to_cpu(ino->nlink)); + i_uid_write(inode, le32_to_cpu(ino->uid)); + i_gid_write(inode, le32_to_cpu(ino->gid)); inode->i_atime.tv_sec = (int64_t)le64_to_cpu(ino->atime_sec); inode->i_atime.tv_nsec = le32_to_cpu(ino->atime_nsec); inode->i_mtime.tv_sec = (int64_t)le64_to_cpu(ino->mtime_sec); @@ -248,12 +305,101 @@ struct inode *ubifs_iget(struct super_block *sb, unsigned long inum) ui->flags = le32_to_cpu(ino->flags); ui->compr_type = le16_to_cpu(ino->compr_type); ui->creat_sqnum = le64_to_cpu(ino->creat_sqnum); + ui->xattr_cnt = le32_to_cpu(ino->xattr_cnt); + ui->xattr_size = le32_to_cpu(ino->xattr_size); + ui->xattr_names = le32_to_cpu(ino->xattr_names); ui->synced_i_size = ui->ui_size = inode->i_size; + ui->xattr = (ui->flags & UBIFS_XATTR_FL) ? 1 : 0; + err = validate_inode(c, inode); if (err) goto out_invalid; +#ifndef __UBOOT__ + /* Disable read-ahead */ + inode->i_mapping->backing_dev_info = &c->bdi; + + switch (inode->i_mode & S_IFMT) { + case S_IFREG: + inode->i_mapping->a_ops = &ubifs_file_address_operations; + inode->i_op = &ubifs_file_inode_operations; + inode->i_fop = &ubifs_file_operations; + if (ui->xattr) { + ui->data = kmalloc(ui->data_len + 1, GFP_NOFS); + if (!ui->data) { + err = -ENOMEM; + goto out_ino; + } + memcpy(ui->data, ino->data, ui->data_len); + ((char *)ui->data)[ui->data_len] = '\0'; + } else if (ui->data_len != 0) { + err = 10; + goto out_invalid; + } + break; + case S_IFDIR: + inode->i_op = &ubifs_dir_inode_operations; + inode->i_fop = &ubifs_dir_operations; + if (ui->data_len != 0) { + err = 11; + goto out_invalid; + } + break; + case S_IFLNK: + inode->i_op = &ubifs_symlink_inode_operations; + if (ui->data_len <= 0 || ui->data_len > UBIFS_MAX_INO_DATA) { + err = 12; + goto out_invalid; + } + ui->data = kmalloc(ui->data_len + 1, GFP_NOFS); + if (!ui->data) { + err = -ENOMEM; + goto out_ino; + } + memcpy(ui->data, ino->data, ui->data_len); + ((char *)ui->data)[ui->data_len] = '\0'; + break; + case S_IFBLK: + case S_IFCHR: + { + dev_t rdev; + union ubifs_dev_desc *dev; + + ui->data = kmalloc(sizeof(union ubifs_dev_desc), GFP_NOFS); + if (!ui->data) { + err = -ENOMEM; + goto out_ino; + } + + dev = (union ubifs_dev_desc *)ino->data; + if (ui->data_len == sizeof(dev->new)) + rdev = new_decode_dev(le32_to_cpu(dev->new)); + else if (ui->data_len == sizeof(dev->huge)) + rdev = huge_decode_dev(le64_to_cpu(dev->huge)); + else { + err = 13; + goto out_invalid; + } + memcpy(ui->data, ino->data, ui->data_len); + inode->i_op = &ubifs_file_inode_operations; + init_special_inode(inode, inode->i_mode, rdev); + break; + } + case S_IFSOCK: + case S_IFIFO: + inode->i_op = &ubifs_file_inode_operations; + init_special_inode(inode, inode->i_mode, 0); + if (ui->data_len != 0) { + err = 14; + goto out_invalid; + } + break; + default: + err = 15; + goto out_invalid; + } +#else if ((inode->i_mode & S_IFMT) == S_IFLNK) { if (ui->data_len <= 0 || ui->data_len > UBIFS_MAX_INO_DATA) { err = 12; @@ -267,23 +413,258 @@ struct inode *ubifs_iget(struct super_block *sb, unsigned long inum) memcpy(ui->data, ino->data, ui->data_len); ((char *)ui->data)[ui->data_len] = '\0'; } +#endif kfree(ino); - inode->i_state &= ~(I_LOCK | I_NEW); +#ifndef __UBOOT__ + ubifs_set_inode_flags(inode); +#endif + unlock_new_inode(inode); return inode; out_invalid: ubifs_err("inode %lu validation failed, error %d", inode->i_ino, err); - dbg_dump_node(c, ino); - dbg_dump_inode(c, inode); + ubifs_dump_node(c, ino); + ubifs_dump_inode(c, inode); err = -EINVAL; out_ino: kfree(ino); out: ubifs_err("failed to read inode %lu, error %d", inode->i_ino, err); + iget_failed(inode); return ERR_PTR(err); } +static struct inode *ubifs_alloc_inode(struct super_block *sb) +{ + struct ubifs_inode *ui; + + ui = kmem_cache_alloc(ubifs_inode_slab, GFP_NOFS); + if (!ui) + return NULL; + + memset((void *)ui + sizeof(struct inode), 0, + sizeof(struct ubifs_inode) - sizeof(struct inode)); + mutex_init(&ui->ui_mutex); + spin_lock_init(&ui->ui_lock); + return &ui->vfs_inode; +}; + +#ifndef __UBOOT__ +static void ubifs_i_callback(struct rcu_head *head) +{ + struct inode *inode = container_of(head, struct inode, i_rcu); + struct ubifs_inode *ui = ubifs_inode(inode); + kmem_cache_free(ubifs_inode_slab, ui); +} + +static void ubifs_destroy_inode(struct inode *inode) +{ + struct ubifs_inode *ui = ubifs_inode(inode); + + kfree(ui->data); + call_rcu(&inode->i_rcu, ubifs_i_callback); +} + +/* + * Note, Linux write-back code calls this without 'i_mutex'. + */ +static int ubifs_write_inode(struct inode *inode, struct writeback_control *wbc) +{ + int err = 0; + struct ubifs_info *c = inode->i_sb->s_fs_info; + struct ubifs_inode *ui = ubifs_inode(inode); + + ubifs_assert(!ui->xattr); + if (is_bad_inode(inode)) + return 0; + + mutex_lock(&ui->ui_mutex); + /* + * Due to races between write-back forced by budgeting + * (see 'sync_some_inodes()') and background write-back, the inode may + * have already been synchronized, do not do this again. This might + * also happen if it was synchronized in an VFS operation, e.g. + * 'ubifs_link()'. + */ + if (!ui->dirty) { + mutex_unlock(&ui->ui_mutex); + return 0; + } + + /* + * As an optimization, do not write orphan inodes to the media just + * because this is not needed. + */ + dbg_gen("inode %lu, mode %#x, nlink %u", + inode->i_ino, (int)inode->i_mode, inode->i_nlink); + if (inode->i_nlink) { + err = ubifs_jnl_write_inode(c, inode); + if (err) + ubifs_err("can't write inode %lu, error %d", + inode->i_ino, err); + else + err = dbg_check_inode_size(c, inode, ui->ui_size); + } + + ui->dirty = 0; + mutex_unlock(&ui->ui_mutex); + ubifs_release_dirty_inode_budget(c, ui); + return err; +} + +static void ubifs_evict_inode(struct inode *inode) +{ + int err; + struct ubifs_info *c = inode->i_sb->s_fs_info; + struct ubifs_inode *ui = ubifs_inode(inode); + + if (ui->xattr) + /* + * Extended attribute inode deletions are fully handled in + * 'ubifs_removexattr()'. These inodes are special and have + * limited usage, so there is nothing to do here. + */ + goto out; + + dbg_gen("inode %lu, mode %#x", inode->i_ino, (int)inode->i_mode); + ubifs_assert(!atomic_read(&inode->i_count)); + + truncate_inode_pages_final(&inode->i_data); + + if (inode->i_nlink) + goto done; + + if (is_bad_inode(inode)) + goto out; + + ui->ui_size = inode->i_size = 0; + err = ubifs_jnl_delete_inode(c, inode); + if (err) + /* + * Worst case we have a lost orphan inode wasting space, so a + * simple error message is OK here. + */ + ubifs_err("can't delete inode %lu, error %d", + inode->i_ino, err); + +out: + if (ui->dirty) + ubifs_release_dirty_inode_budget(c, ui); + else { + /* We've deleted something - clean the "no space" flags */ + c->bi.nospace = c->bi.nospace_rp = 0; + smp_wmb(); + } +done: + clear_inode(inode); +} +#endif + +static void ubifs_dirty_inode(struct inode *inode, int flags) +{ + struct ubifs_inode *ui = ubifs_inode(inode); + + ubifs_assert(mutex_is_locked(&ui->ui_mutex)); + if (!ui->dirty) { + ui->dirty = 1; + dbg_gen("inode %lu", inode->i_ino); + } +} + +#ifndef __UBOOT__ +static int ubifs_statfs(struct dentry *dentry, struct kstatfs *buf) +{ + struct ubifs_info *c = dentry->d_sb->s_fs_info; + unsigned long long free; + __le32 *uuid = (__le32 *)c->uuid; + + free = ubifs_get_free_space(c); + dbg_gen("free space %lld bytes (%lld blocks)", + free, free >> UBIFS_BLOCK_SHIFT); + + buf->f_type = UBIFS_SUPER_MAGIC; + buf->f_bsize = UBIFS_BLOCK_SIZE; + buf->f_blocks = c->block_cnt; + buf->f_bfree = free >> UBIFS_BLOCK_SHIFT; + if (free > c->report_rp_size) + buf->f_bavail = (free - c->report_rp_size) >> UBIFS_BLOCK_SHIFT; + else + buf->f_bavail = 0; + buf->f_files = 0; + buf->f_ffree = 0; + buf->f_namelen = UBIFS_MAX_NLEN; + buf->f_fsid.val[0] = le32_to_cpu(uuid[0]) ^ le32_to_cpu(uuid[2]); + buf->f_fsid.val[1] = le32_to_cpu(uuid[1]) ^ le32_to_cpu(uuid[3]); + ubifs_assert(buf->f_bfree <= c->block_cnt); + return 0; +} + +static int ubifs_show_options(struct seq_file *s, struct dentry *root) +{ + struct ubifs_info *c = root->d_sb->s_fs_info; + + if (c->mount_opts.unmount_mode == 2) + seq_printf(s, ",fast_unmount"); + else if (c->mount_opts.unmount_mode == 1) + seq_printf(s, ",norm_unmount"); + + if (c->mount_opts.bulk_read == 2) + seq_printf(s, ",bulk_read"); + else if (c->mount_opts.bulk_read == 1) + seq_printf(s, ",no_bulk_read"); + + if (c->mount_opts.chk_data_crc == 2) + seq_printf(s, ",chk_data_crc"); + else if (c->mount_opts.chk_data_crc == 1) + seq_printf(s, ",no_chk_data_crc"); + + if (c->mount_opts.override_compr) { + seq_printf(s, ",compr=%s", + ubifs_compr_name(c->mount_opts.compr_type)); + } + + return 0; +} + +static int ubifs_sync_fs(struct super_block *sb, int wait) +{ + int i, err; + struct ubifs_info *c = sb->s_fs_info; + + /* + * Zero @wait is just an advisory thing to help the file system shove + * lots of data into the queues, and there will be the second + * '->sync_fs()' call, with non-zero @wait. + */ + if (!wait) + return 0; + + /* + * Synchronize write buffers, because 'ubifs_run_commit()' does not + * do this if it waits for an already running commit. + */ + for (i = 0; i < c->jhead_cnt; i++) { + err = ubifs_wbuf_sync(&c->jheads[i].wbuf); + if (err) + return err; + } + + /* + * Strictly speaking, it is not necessary to commit the journal here, + * synchronizing write-buffers would be enough. But committing makes + * UBIFS free space predictions much more accurate, so we want to let + * the user be able to get more accurate results of 'statfs()' after + * they synchronize the file system. + */ + err = ubifs_run_commit(c); + if (err) + return err; + + return ubi_sync(c->vi.ubi_num); +} +#endif + /** * init_constants_early - initialize UBIFS constants. * @c: UBIFS file-system description object @@ -312,9 +693,12 @@ static int init_constants_early(struct ubifs_info *c) c->leb_cnt = c->vi.size; c->leb_size = c->vi.usable_leb_size; + c->leb_start = c->di.leb_start; c->half_leb_size = c->leb_size / 2; c->min_io_size = c->di.min_io_size; c->min_io_shift = fls(c->min_io_size) - 1; + c->max_write_size = c->di.max_write_size; + c->max_write_shift = fls(c->max_write_size) - 1; if (c->leb_size < UBIFS_MIN_LEB_SZ) { ubifs_err("too small LEBs (%d bytes), min. is %d bytes", @@ -333,6 +717,18 @@ static int init_constants_early(struct ubifs_info *c) return -EINVAL; } + /* + * Maximum write size has to be greater or equivalent to min. I/O + * size, and be multiple of min. I/O size. + */ + if (c->max_write_size < c->min_io_size || + c->max_write_size % c->min_io_size || + !is_power_of_2(c->max_write_size)) { + ubifs_err("bad write buffer size %d for %d min. I/O unit", + c->max_write_size, c->min_io_size); + return -EINVAL; + } + /* * UBIFS aligns all node to 8-byte boundary, so to make function in * io.c simpler, assume minimum I/O unit size to be 8 bytes if it is @@ -341,6 +737,10 @@ static int init_constants_early(struct ubifs_info *c) if (c->min_io_size < 8) { c->min_io_size = 8; c->min_io_shift = 3; + if (c->max_write_size < c->min_io_size) { + c->max_write_size = c->min_io_size; + c->max_write_shift = c->min_io_shift; + } } c->ref_node_alsz = ALIGN(UBIFS_REF_NODE_SZ, c->min_io_size); @@ -393,9 +793,33 @@ static int init_constants_early(struct ubifs_info *c) */ c->leb_overhead = c->leb_size % UBIFS_MAX_DATA_NODE_SZ; + /* Buffer size for bulk-reads */ + c->max_bu_buf_len = UBIFS_MAX_BULK_READ * UBIFS_MAX_DATA_NODE_SZ; + if (c->max_bu_buf_len > c->leb_size) + c->max_bu_buf_len = c->leb_size; return 0; } +/** + * bud_wbuf_callback - bud LEB write-buffer synchronization call-back. + * @c: UBIFS file-system description object + * @lnum: LEB the write-buffer was synchronized to + * @free: how many free bytes left in this LEB + * @pad: how many bytes were padded + * + * This is a callback function which is called by the I/O unit when the + * write-buffer is synchronized. We need this to correctly maintain space + * accounting in bud logical eraseblocks. This function returns zero in case of + * success and a negative error code in case of failure. + * + * This function actually belongs to the journal, but we keep it here because + * we want to keep it static. + */ +static int bud_wbuf_callback(struct ubifs_info *c, int lnum, int free, int pad) +{ + return ubifs_update_one_lp(c, lnum, free, pad, 0, 0); +} + /* * init_constants_sb - initialize UBIFS constants. * @c: UBIFS file-system description object @@ -426,8 +850,8 @@ static int init_constants_sb(struct ubifs_info *c) tmp = UBIFS_CS_NODE_SZ + UBIFS_REF_NODE_SZ * c->jhead_cnt; tmp = ALIGN(tmp, c->min_io_size); if (tmp > c->leb_size) { - dbg_err("too small LEB size %d, at least %d needed", - c->leb_size, tmp); + ubifs_err("too small LEB size %d, at least %d needed", + c->leb_size, tmp); return -EINVAL; } @@ -441,8 +865,8 @@ static int init_constants_sb(struct ubifs_info *c) tmp /= c->leb_size; tmp += 1; if (c->log_lebs < tmp) { - dbg_err("too small log %d LEBs, required min. %d LEBs", - c->log_lebs, tmp); + ubifs_err("too small log %d LEBs, required min. %d LEBs", + c->log_lebs, tmp); return -EINVAL; } @@ -451,11 +875,11 @@ static int init_constants_sb(struct ubifs_info *c) * be compressed and direntries are of the maximum size. * * Note, data, which may be stored in inodes is budgeted separately, so - * it is not included into 'c->inode_budget'. + * it is not included into 'c->bi.inode_budget'. */ - c->page_budget = UBIFS_MAX_DATA_NODE_SZ * UBIFS_BLOCKS_PER_PAGE; - c->inode_budget = UBIFS_INO_NODE_SZ; - c->dent_budget = UBIFS_MAX_DENT_NODE_SZ; + c->bi.page_budget = UBIFS_MAX_DATA_NODE_SZ * UBIFS_BLOCKS_PER_PAGE; + c->bi.inode_budget = UBIFS_INO_NODE_SZ; + c->bi.dent_budget = UBIFS_MAX_DENT_NODE_SZ; /* * When the amount of flash space used by buds becomes @@ -482,6 +906,8 @@ static int init_constants_sb(struct ubifs_info *c) if (err) return err; + /* Initialize effective LEB size used in budgeting calculations */ + c->idx_leb_size = c->leb_size - c->max_idx_node_sz; return 0; } @@ -497,7 +923,8 @@ static void init_constants_master(struct ubifs_info *c) { long long tmp64; - c->min_idx_lebs = ubifs_calc_min_idx_lebs(c); + c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c); + c->report_rp_size = ubifs_reported_space(c, c->rp_size); /* * Calculate total amount of FS blocks. This number is not used @@ -514,6 +941,88 @@ static void init_constants_master(struct ubifs_info *c) c->block_cnt = tmp64 >> UBIFS_BLOCK_SHIFT; } +/** + * take_gc_lnum - reserve GC LEB. + * @c: UBIFS file-system description object + * + * This function ensures that the LEB reserved for garbage collection is marked + * as "taken" in lprops. We also have to set free space to LEB size and dirty + * space to zero, because lprops may contain out-of-date information if the + * file-system was un-mounted before it has been committed. This function + * returns zero in case of success and a negative error code in case of + * failure. + */ +static int take_gc_lnum(struct ubifs_info *c) +{ + int err; + + if (c->gc_lnum == -1) { + ubifs_err("no LEB for GC"); + return -EINVAL; + } + + /* And we have to tell lprops that this LEB is taken */ + err = ubifs_change_one_lp(c, c->gc_lnum, c->leb_size, 0, + LPROPS_TAKEN, 0, 0); + return err; +} + +/** + * alloc_wbufs - allocate write-buffers. + * @c: UBIFS file-system description object + * + * This helper function allocates and initializes UBIFS write-buffers. Returns + * zero in case of success and %-ENOMEM in case of failure. + */ +static int alloc_wbufs(struct ubifs_info *c) +{ + int i, err; + + c->jheads = kzalloc(c->jhead_cnt * sizeof(struct ubifs_jhead), + GFP_KERNEL); + if (!c->jheads) + return -ENOMEM; + + /* Initialize journal heads */ + for (i = 0; i < c->jhead_cnt; i++) { + INIT_LIST_HEAD(&c->jheads[i].buds_list); + err = ubifs_wbuf_init(c, &c->jheads[i].wbuf); + if (err) + return err; + + c->jheads[i].wbuf.sync_callback = &bud_wbuf_callback; + c->jheads[i].wbuf.jhead = i; + c->jheads[i].grouped = 1; + } + + /* + * Garbage Collector head does not need to be synchronized by timer. + * Also GC head nodes are not grouped. + */ + c->jheads[GCHD].wbuf.no_timer = 1; + c->jheads[GCHD].grouped = 0; + + return 0; +} + +/** + * free_wbufs - free write-buffers. + * @c: UBIFS file-system description object + */ +static void free_wbufs(struct ubifs_info *c) +{ + int i; + + if (c->jheads) { + for (i = 0; i < c->jhead_cnt; i++) { + kfree(c->jheads[i].wbuf.buf); + kfree(c->jheads[i].wbuf.inodes); + } + kfree(c->jheads); + c->jheads = NULL; + } +} + /** * free_orphans - free orphans. * @c: UBIFS file-system description object @@ -533,13 +1042,27 @@ static void free_orphans(struct ubifs_info *c) orph = list_entry(c->orph_list.next, struct ubifs_orphan, list); list_del(&orph->list); kfree(orph); - dbg_err("orphan list not empty at unmount"); + ubifs_err("orphan list not empty at unmount"); } vfree(c->orph_buf); c->orph_buf = NULL; } +#ifndef __UBOOT__ +/** + * free_buds - free per-bud objects. + * @c: UBIFS file-system description object + */ +static void free_buds(struct ubifs_info *c) +{ + struct ubifs_bud *bud, *n; + + rbtree_postorder_for_each_entry_safe(bud, n, &c->buds, rb) + kfree(bud); +} +#endif + /** * check_volume_empty - check if the UBI volume is empty. * @c: UBIFS file-system description object @@ -555,7 +1078,7 @@ static int check_volume_empty(struct ubifs_info *c) c->empty = 1; for (lnum = 0; lnum < c->leb_cnt; lnum++) { - err = ubi_is_mapped(c->ubi, lnum); + err = ubifs_is_mapped(c, lnum); if (unlikely(err < 0)) return err; if (err == 1) { @@ -569,23 +1092,258 @@ static int check_volume_empty(struct ubifs_info *c) return 0; } +/* + * UBIFS mount options. + * + * Opt_fast_unmount: do not run a journal commit before un-mounting + * Opt_norm_unmount: run a journal commit before un-mounting + * Opt_bulk_read: enable bulk-reads + * Opt_no_bulk_read: disable bulk-reads + * Opt_chk_data_crc: check CRCs when reading data nodes + * Opt_no_chk_data_crc: do not check CRCs when reading data nodes + * Opt_override_compr: override default compressor + * Opt_err: just end of array marker + */ +enum { + Opt_fast_unmount, + Opt_norm_unmount, + Opt_bulk_read, + Opt_no_bulk_read, + Opt_chk_data_crc, + Opt_no_chk_data_crc, + Opt_override_compr, + Opt_err, +}; + +#ifndef __UBOOT__ +static const match_table_t tokens = { + {Opt_fast_unmount, "fast_unmount"}, + {Opt_norm_unmount, "norm_unmount"}, + {Opt_bulk_read, "bulk_read"}, + {Opt_no_bulk_read, "no_bulk_read"}, + {Opt_chk_data_crc, "chk_data_crc"}, + {Opt_no_chk_data_crc, "no_chk_data_crc"}, + {Opt_override_compr, "compr=%s"}, + {Opt_err, NULL}, +}; + +/** + * parse_standard_option - parse a standard mount option. + * @option: the option to parse + * + * Normally, standard mount options like "sync" are passed to file-systems as + * flags. However, when a "rootflags=" kernel boot parameter is used, they may + * be present in the options string. This function tries to deal with this + * situation and parse standard options. Returns 0 if the option was not + * recognized, and the corresponding integer flag if it was. + * + * UBIFS is only interested in the "sync" option, so do not check for anything + * else. + */ +static int parse_standard_option(const char *option) +{ + ubifs_msg("parse %s", option); + if (!strcmp(option, "sync")) + return MS_SYNCHRONOUS; + return 0; +} + +/** + * ubifs_parse_options - parse mount parameters. + * @c: UBIFS file-system description object + * @options: parameters to parse + * @is_remount: non-zero if this is FS re-mount + * + * This function parses UBIFS mount options and returns zero in case success + * and a negative error code in case of failure. + */ +static int ubifs_parse_options(struct ubifs_info *c, char *options, + int is_remount) +{ + char *p; + substring_t args[MAX_OPT_ARGS]; + + if (!options) + return 0; + + while ((p = strsep(&options, ","))) { + int token; + + if (!*p) + continue; + + token = match_token(p, tokens, args); + switch (token) { + /* + * %Opt_fast_unmount and %Opt_norm_unmount options are ignored. + * We accept them in order to be backward-compatible. But this + * should be removed at some point. + */ + case Opt_fast_unmount: + c->mount_opts.unmount_mode = 2; + break; + case Opt_norm_unmount: + c->mount_opts.unmount_mode = 1; + break; + case Opt_bulk_read: + c->mount_opts.bulk_read = 2; + c->bulk_read = 1; + break; + case Opt_no_bulk_read: + c->mount_opts.bulk_read = 1; + c->bulk_read = 0; + break; + case Opt_chk_data_crc: + c->mount_opts.chk_data_crc = 2; + c->no_chk_data_crc = 0; + break; + case Opt_no_chk_data_crc: + c->mount_opts.chk_data_crc = 1; + c->no_chk_data_crc = 1; + break; + case Opt_override_compr: + { + char *name = match_strdup(&args[0]); + + if (!name) + return -ENOMEM; + if (!strcmp(name, "none")) + c->mount_opts.compr_type = UBIFS_COMPR_NONE; + else if (!strcmp(name, "lzo")) + c->mount_opts.compr_type = UBIFS_COMPR_LZO; + else if (!strcmp(name, "zlib")) + c->mount_opts.compr_type = UBIFS_COMPR_ZLIB; + else { + ubifs_err("unknown compressor \"%s\"", name); + kfree(name); + return -EINVAL; + } + kfree(name); + c->mount_opts.override_compr = 1; + c->default_compr = c->mount_opts.compr_type; + break; + } + default: + { + unsigned long flag; + struct super_block *sb = c->vfs_sb; + + flag = parse_standard_option(p); + if (!flag) { + ubifs_err("unrecognized mount option \"%s\" or missing value", + p); + return -EINVAL; + } + sb->s_flags |= flag; + break; + } + } + } + + return 0; +} + +/** + * destroy_journal - destroy journal data structures. + * @c: UBIFS file-system description object + * + * This function destroys journal data structures including those that may have + * been created by recovery functions. + */ +static void destroy_journal(struct ubifs_info *c) +{ + while (!list_empty(&c->unclean_leb_list)) { + struct ubifs_unclean_leb *ucleb; + + ucleb = list_entry(c->unclean_leb_list.next, + struct ubifs_unclean_leb, list); + list_del(&ucleb->list); + kfree(ucleb); + } + while (!list_empty(&c->old_buds)) { + struct ubifs_bud *bud; + + bud = list_entry(c->old_buds.next, struct ubifs_bud, list); + list_del(&bud->list); + kfree(bud); + } + ubifs_destroy_idx_gc(c); + ubifs_destroy_size_tree(c); + ubifs_tnc_close(c); + free_buds(c); +} +#endif + +/** + * bu_init - initialize bulk-read information. + * @c: UBIFS file-system description object + */ +static void bu_init(struct ubifs_info *c) +{ + ubifs_assert(c->bulk_read == 1); + + if (c->bu.buf) + return; /* Already initialized */ + +again: + c->bu.buf = kmalloc(c->max_bu_buf_len, GFP_KERNEL | __GFP_NOWARN); + if (!c->bu.buf) { + if (c->max_bu_buf_len > UBIFS_KMALLOC_OK) { + c->max_bu_buf_len = UBIFS_KMALLOC_OK; + goto again; + } + + /* Just disable bulk-read */ + ubifs_warn("cannot allocate %d bytes of memory for bulk-read, disabling it", + c->max_bu_buf_len); + c->mount_opts.bulk_read = 1; + c->bulk_read = 0; + return; + } +} + +#ifndef __UBOOT__ +/** + * check_free_space - check if there is enough free space to mount. + * @c: UBIFS file-system description object + * + * This function makes sure UBIFS has enough free space to be mounted in + * read/write mode. UBIFS must always have some free space to allow deletions. + */ +static int check_free_space(struct ubifs_info *c) +{ + ubifs_assert(c->dark_wm > 0); + if (c->lst.total_free + c->lst.total_dirty < c->dark_wm) { + ubifs_err("insufficient free space to mount in R/W mode"); + ubifs_dump_budg(c, &c->bi); + ubifs_dump_lprops(c); + return -ENOSPC; + } + return 0; +} +#endif + /** * mount_ubifs - mount UBIFS file-system. * @c: UBIFS file-system description object * * This function mounts UBIFS file system. Returns zero in case of success and * a negative error code in case of failure. - * - * Note, the function does not de-allocate resources it it fails half way - * through, and the caller has to do this instead. */ static int mount_ubifs(struct ubifs_info *c) { - struct super_block *sb = c->vfs_sb; - int err, mounted_read_only = (sb->s_flags & MS_RDONLY); - long long x; + int err; + long long x, y; size_t sz; + c->ro_mount = !!(c->vfs_sb->s_flags & MS_RDONLY); +#ifdef __UBOOT__ + if (!c->ro_mount) { + printf("UBIFS: only ro mode in U-Boot allowed.\n"); + return -EACCES; + } +#endif + err = init_constants_early(c); if (err) return err; @@ -598,7 +1356,7 @@ static int mount_ubifs(struct ubifs_info *c) if (err) goto out_free; - if (c->empty && (mounted_read_only || c->ro_media)) { + if (c->empty && (c->ro_mount || c->ro_media)) { /* * This UBI volume is empty, and read-only, or the file system * is mounted read-only - we cannot format it. @@ -609,7 +1367,7 @@ static int mount_ubifs(struct ubifs_info *c) goto out_free; } - if (c->ro_media && !mounted_read_only) { + if (c->ro_media && !c->ro_mount) { ubifs_err("cannot mount read-write - read-only media"); err = -EROFS; goto out_free; @@ -629,11 +1387,27 @@ static int mount_ubifs(struct ubifs_info *c) if (!c->sbuf) goto out_free; - /* - * We have to check all CRCs, even for data nodes, when we mount the FS - * (specifically, when we are replaying). - */ - c->always_chk_crc = 1; +#ifndef __UBOOT__ + if (!c->ro_mount) { + c->ileb_buf = vmalloc(c->leb_size); + if (!c->ileb_buf) + goto out_free; + } +#endif + + if (c->bulk_read == 1) + bu_init(c); + +#ifndef __UBOOT__ + if (!c->ro_mount) { + c->write_reserve_buf = kmalloc(COMPRESSED_DATA_NODE_BUF_SZ, + GFP_KERNEL); + if (!c->write_reserve_buf) + goto out_free; + } +#endif + + c->mounting = 1; err = ubifs_read_superblock(c); if (err) @@ -646,11 +1420,10 @@ static int mount_ubifs(struct ubifs_info *c) if (!ubifs_compr_present(c->default_compr)) { ubifs_err("'compressor \"%s\" is not compiled in", ubifs_compr_name(c->default_compr)); + err = -ENOTSUPP; goto out_free; } - dbg_failure_mode_registration(c); - err = init_constants_sb(c); if (err) goto out_free; @@ -663,7 +1436,25 @@ static int mount_ubifs(struct ubifs_info *c) goto out_free; } + err = alloc_wbufs(c); + if (err) + goto out_cbuf; + sprintf(c->bgt_name, BGT_NAME_PATTERN, c->vi.ubi_num, c->vi.vol_id); +#ifndef __UBOOT__ + if (!c->ro_mount) { + /* Create background thread */ + c->bgt = kthread_create(ubifs_bg_thread, c, "%s", c->bgt_name); + if (IS_ERR(c->bgt)) { + err = PTR_ERR(c->bgt); + c->bgt = NULL; + ubifs_err("cannot spawn \"%s\", error %d", + c->bgt_name, err); + goto out_wbufs; + } + wake_up_process(c->bgt); + } +#endif err = ubifs_read_master(c); if (err) @@ -676,205 +1467,695 @@ static int mount_ubifs(struct ubifs_info *c) c->need_recovery = 1; } - err = ubifs_lpt_init(c, 1, !mounted_read_only); +#ifndef __UBOOT__ + if (c->need_recovery && !c->ro_mount) { + err = ubifs_recover_inl_heads(c, c->sbuf); + if (err) + goto out_master; + } +#endif + + err = ubifs_lpt_init(c, 1, !c->ro_mount); if (err) - goto out_lpt; + goto out_master; + +#ifndef __UBOOT__ + if (!c->ro_mount && c->space_fixup) { + err = ubifs_fixup_free_space(c); + if (err) + goto out_lpt; + } + + if (!c->ro_mount) { + /* + * Set the "dirty" flag so that if we reboot uncleanly we + * will notice this immediately on the next mount. + */ + c->mst_node->flags |= cpu_to_le32(UBIFS_MST_DIRTY); + err = ubifs_write_master(c); + if (err) + goto out_lpt; + } +#endif - err = dbg_check_idx_size(c, c->old_idx_sz); + err = dbg_check_idx_size(c, c->bi.old_idx_sz); if (err) goto out_lpt; +#ifndef __UBOOT__ err = ubifs_replay_journal(c); if (err) goto out_journal; +#endif + + /* Calculate 'min_idx_lebs' after journal replay */ + c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c); - err = ubifs_mount_orphans(c, c->need_recovery, mounted_read_only); + err = ubifs_mount_orphans(c, c->need_recovery, c->ro_mount); if (err) goto out_orphans; - if (c->need_recovery) { + if (!c->ro_mount) { +#ifndef __UBOOT__ + int lnum; + + err = check_free_space(c); + if (err) + goto out_orphans; + + /* Check for enough log space */ + lnum = c->lhead_lnum + 1; + if (lnum >= UBIFS_LOG_LNUM + c->log_lebs) + lnum = UBIFS_LOG_LNUM; + if (lnum == c->ltail_lnum) { + err = ubifs_consolidate_log(c); + if (err) + goto out_orphans; + } + + if (c->need_recovery) { + err = ubifs_recover_size(c); + if (err) + goto out_orphans; + err = ubifs_rcvry_gc_commit(c); + if (err) + goto out_orphans; + } else { + err = take_gc_lnum(c); + if (err) + goto out_orphans; + + /* + * GC LEB may contain garbage if there was an unclean + * reboot, and it should be un-mapped. + */ + err = ubifs_leb_unmap(c, c->gc_lnum); + if (err) + goto out_orphans; + } + + err = dbg_check_lprops(c); + if (err) + goto out_orphans; +#endif + } else if (c->need_recovery) { err = ubifs_recover_size(c); if (err) goto out_orphans; + } else { + /* + * Even if we mount read-only, we have to set space in GC LEB + * to proper value because this affects UBIFS free space + * reporting. We do not want to have a situation when + * re-mounting from R/O to R/W changes amount of free space. + */ + err = take_gc_lnum(c); + if (err) + goto out_orphans; } +#ifndef __UBOOT__ spin_lock(&ubifs_infos_lock); list_add_tail(&c->infos_list, &ubifs_infos); spin_unlock(&ubifs_infos_lock); +#endif if (c->need_recovery) { - if (mounted_read_only) + if (c->ro_mount) ubifs_msg("recovery deferred"); else { c->need_recovery = 0; ubifs_msg("recovery completed"); + /* + * GC LEB has to be empty and taken at this point. But + * the journal head LEBs may also be accounted as + * "empty taken" if they are empty. + */ + ubifs_assert(c->lst.taken_empty_lebs > 0); } - } + } else + ubifs_assert(c->lst.taken_empty_lebs > 0); err = dbg_check_filesystem(c); if (err) goto out_infos; - c->always_chk_crc = 0; + err = dbg_debugfs_init_fs(c); + if (err) + goto out_infos; + + c->mounting = 0; - ubifs_msg("mounted UBI device %d, volume %d, name \"%s\"", - c->vi.ubi_num, c->vi.vol_id, c->vi.name); - if (mounted_read_only) - ubifs_msg("mounted read-only"); + ubifs_msg("mounted UBI device %d, volume %d, name \"%s\"%s", + c->vi.ubi_num, c->vi.vol_id, c->vi.name, + c->ro_mount ? ", R/O mode" : ""); x = (long long)c->main_lebs * c->leb_size; - ubifs_msg("file system size: %lld bytes (%lld KiB, %lld MiB, %d " - "LEBs)", x, x >> 10, x >> 20, c->main_lebs); - x = (long long)c->log_lebs * c->leb_size + c->max_bud_bytes; - ubifs_msg("journal size: %lld bytes (%lld KiB, %lld MiB, %d " - "LEBs)", x, x >> 10, x >> 20, c->log_lebs + c->max_bud_cnt); - ubifs_msg("media format: w%d/r%d (latest is w%d/r%d)", + y = (long long)c->log_lebs * c->leb_size + c->max_bud_bytes; + ubifs_msg("LEB size: %d bytes (%d KiB), min./max. I/O unit sizes: %d bytes/%d bytes", + c->leb_size, c->leb_size >> 10, c->min_io_size, + c->max_write_size); + ubifs_msg("FS size: %lld bytes (%lld MiB, %d LEBs), journal size %lld bytes (%lld MiB, %d LEBs)", + x, x >> 20, c->main_lebs, + y, y >> 20, c->log_lebs + c->max_bud_cnt); + ubifs_msg("reserved for root: %llu bytes (%llu KiB)", + c->report_rp_size, c->report_rp_size >> 10); + ubifs_msg("media format: w%d/r%d (latest is w%d/r%d), UUID %pUB%s", c->fmt_version, c->ro_compat_version, - UBIFS_FORMAT_VERSION, UBIFS_RO_COMPAT_VERSION); - ubifs_msg("default compressor: %s", ubifs_compr_name(c->default_compr)); - ubifs_msg("reserved for root: %llu bytes (%llu KiB)", - c->report_rp_size, c->report_rp_size >> 10); - - dbg_msg("compiled on: " __DATE__ " at " __TIME__); - dbg_msg("min. I/O unit size: %d bytes", c->min_io_size); - dbg_msg("LEB size: %d bytes (%d KiB)", - c->leb_size, c->leb_size >> 10); - dbg_msg("data journal heads: %d", + UBIFS_FORMAT_VERSION, UBIFS_RO_COMPAT_VERSION, c->uuid, + c->big_lpt ? ", big LPT model" : ", small LPT model"); + + dbg_gen("default compressor: %s", ubifs_compr_name(c->default_compr)); + dbg_gen("data journal heads: %d", c->jhead_cnt - NONDATA_JHEADS_CNT); - dbg_msg("UUID: %02X%02X%02X%02X-%02X%02X" - "-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X", - c->uuid[0], c->uuid[1], c->uuid[2], c->uuid[3], - c->uuid[4], c->uuid[5], c->uuid[6], c->uuid[7], - c->uuid[8], c->uuid[9], c->uuid[10], c->uuid[11], - c->uuid[12], c->uuid[13], c->uuid[14], c->uuid[15]); - dbg_msg("big_lpt %d", c->big_lpt); - dbg_msg("log LEBs: %d (%d - %d)", + dbg_gen("log LEBs: %d (%d - %d)", c->log_lebs, UBIFS_LOG_LNUM, c->log_last); - dbg_msg("LPT area LEBs: %d (%d - %d)", + dbg_gen("LPT area LEBs: %d (%d - %d)", c->lpt_lebs, c->lpt_first, c->lpt_last); - dbg_msg("orphan area LEBs: %d (%d - %d)", + dbg_gen("orphan area LEBs: %d (%d - %d)", c->orph_lebs, c->orph_first, c->orph_last); - dbg_msg("main area LEBs: %d (%d - %d)", + dbg_gen("main area LEBs: %d (%d - %d)", c->main_lebs, c->main_first, c->leb_cnt - 1); - dbg_msg("index LEBs: %d", c->lst.idx_lebs); - dbg_msg("total index bytes: %lld (%lld KiB, %lld MiB)", - c->old_idx_sz, c->old_idx_sz >> 10, c->old_idx_sz >> 20); - dbg_msg("key hash type: %d", c->key_hash_type); - dbg_msg("tree fanout: %d", c->fanout); - dbg_msg("reserved GC LEB: %d", c->gc_lnum); - dbg_msg("first main LEB: %d", c->main_first); - dbg_msg("max. znode size %d", c->max_znode_sz); - dbg_msg("max. index node size %d", c->max_idx_node_sz); - dbg_msg("node sizes: data %zu, inode %zu, dentry %zu", + dbg_gen("index LEBs: %d", c->lst.idx_lebs); + dbg_gen("total index bytes: %lld (%lld KiB, %lld MiB)", + c->bi.old_idx_sz, c->bi.old_idx_sz >> 10, + c->bi.old_idx_sz >> 20); + dbg_gen("key hash type: %d", c->key_hash_type); + dbg_gen("tree fanout: %d", c->fanout); + dbg_gen("reserved GC LEB: %d", c->gc_lnum); + dbg_gen("max. znode size %d", c->max_znode_sz); + dbg_gen("max. index node size %d", c->max_idx_node_sz); + dbg_gen("node sizes: data %zu, inode %zu, dentry %zu", UBIFS_DATA_NODE_SZ, UBIFS_INO_NODE_SZ, UBIFS_DENT_NODE_SZ); - dbg_msg("node sizes: trun %zu, sb %zu, master %zu", + dbg_gen("node sizes: trun %zu, sb %zu, master %zu", UBIFS_TRUN_NODE_SZ, UBIFS_SB_NODE_SZ, UBIFS_MST_NODE_SZ); - dbg_msg("node sizes: ref %zu, cmt. start %zu, orph %zu", + dbg_gen("node sizes: ref %zu, cmt. start %zu, orph %zu", UBIFS_REF_NODE_SZ, UBIFS_CS_NODE_SZ, UBIFS_ORPH_NODE_SZ); - dbg_msg("max. node sizes: data %zu, inode %zu dentry %zu", - UBIFS_MAX_DATA_NODE_SZ, UBIFS_MAX_INO_NODE_SZ, - UBIFS_MAX_DENT_NODE_SZ); - dbg_msg("dead watermark: %d", c->dead_wm); - dbg_msg("dark watermark: %d", c->dark_wm); - dbg_msg("LEB overhead: %d", c->leb_overhead); + dbg_gen("max. node sizes: data %zu, inode %zu dentry %zu, idx %d", + UBIFS_MAX_DATA_NODE_SZ, UBIFS_MAX_INO_NODE_SZ, + UBIFS_MAX_DENT_NODE_SZ, ubifs_idx_node_sz(c, c->fanout)); + dbg_gen("dead watermark: %d", c->dead_wm); + dbg_gen("dark watermark: %d", c->dark_wm); + dbg_gen("LEB overhead: %d", c->leb_overhead); x = (long long)c->main_lebs * c->dark_wm; - dbg_msg("max. dark space: %lld (%lld KiB, %lld MiB)", + dbg_gen("max. dark space: %lld (%lld KiB, %lld MiB)", x, x >> 10, x >> 20); - dbg_msg("maximum bud bytes: %lld (%lld KiB, %lld MiB)", + dbg_gen("maximum bud bytes: %lld (%lld KiB, %lld MiB)", c->max_bud_bytes, c->max_bud_bytes >> 10, c->max_bud_bytes >> 20); - dbg_msg("BG commit bud bytes: %lld (%lld KiB, %lld MiB)", + dbg_gen("BG commit bud bytes: %lld (%lld KiB, %lld MiB)", c->bg_bud_bytes, c->bg_bud_bytes >> 10, c->bg_bud_bytes >> 20); - dbg_msg("current bud bytes %lld (%lld KiB, %lld MiB)", + dbg_gen("current bud bytes %lld (%lld KiB, %lld MiB)", c->bud_bytes, c->bud_bytes >> 10, c->bud_bytes >> 20); - dbg_msg("max. seq. number: %llu", c->max_sqnum); - dbg_msg("commit number: %llu", c->cmt_no); + dbg_gen("max. seq. number: %llu", c->max_sqnum); + dbg_gen("commit number: %llu", c->cmt_no); + + return 0; + +out_infos: + spin_lock(&ubifs_infos_lock); + list_del(&c->infos_list); + spin_unlock(&ubifs_infos_lock); +out_orphans: + free_orphans(c); +#ifndef __UBOOT__ +out_journal: + destroy_journal(c); +#endif +out_lpt: + ubifs_lpt_free(c, 0); +out_master: + kfree(c->mst_node); + kfree(c->rcvrd_mst_node); + if (c->bgt) + kthread_stop(c->bgt); +#ifndef __UBOOT__ +out_wbufs: +#endif + free_wbufs(c); +out_cbuf: + kfree(c->cbuf); +out_free: + kfree(c->write_reserve_buf); + kfree(c->bu.buf); + vfree(c->ileb_buf); + vfree(c->sbuf); + kfree(c->bottom_up_buf); + ubifs_debugging_exit(c); + return err; +} + +/** + * ubifs_umount - un-mount UBIFS file-system. + * @c: UBIFS file-system description object + * + * Note, this function is called to free allocated resourced when un-mounting, + * as well as free resources when an error occurred while we were half way + * through mounting (error path cleanup function). So it has to make sure the + * resource was actually allocated before freeing it. + */ +#ifndef __UBOOT__ +static void ubifs_umount(struct ubifs_info *c) +#else +void ubifs_umount(struct ubifs_info *c) +#endif +{ + dbg_gen("un-mounting UBI device %d, volume %d", c->vi.ubi_num, + c->vi.vol_id); + + dbg_debugfs_exit_fs(c); + spin_lock(&ubifs_infos_lock); + list_del(&c->infos_list); + spin_unlock(&ubifs_infos_lock); + +#ifndef __UBOOT__ + if (c->bgt) + kthread_stop(c->bgt); + + destroy_journal(c); +#endif + free_wbufs(c); + free_orphans(c); + ubifs_lpt_free(c, 0); + + kfree(c->cbuf); + kfree(c->rcvrd_mst_node); + kfree(c->mst_node); + kfree(c->write_reserve_buf); + kfree(c->bu.buf); + vfree(c->ileb_buf); + vfree(c->sbuf); + kfree(c->bottom_up_buf); + ubifs_debugging_exit(c); +#ifdef __UBOOT__ + /* Finally free U-Boot's global copy of superblock */ + if (ubifs_sb != NULL) { + free(ubifs_sb->s_fs_info); + free(ubifs_sb); + } +#endif +} + +#ifndef __UBOOT__ +/** + * ubifs_remount_rw - re-mount in read-write mode. + * @c: UBIFS file-system description object + * + * UBIFS avoids allocating many unnecessary resources when mounted in read-only + * mode. This function allocates the needed resources and re-mounts UBIFS in + * read-write mode. + */ +static int ubifs_remount_rw(struct ubifs_info *c) +{ + int err, lnum; + + if (c->rw_incompat) { + ubifs_err("the file-system is not R/W-compatible"); + ubifs_msg("on-flash format version is w%d/r%d, but software only supports up to version w%d/r%d", + c->fmt_version, c->ro_compat_version, + UBIFS_FORMAT_VERSION, UBIFS_RO_COMPAT_VERSION); + return -EROFS; + } + + mutex_lock(&c->umount_mutex); + dbg_save_space_info(c); + c->remounting_rw = 1; + c->ro_mount = 0; + + if (c->space_fixup) { + err = ubifs_fixup_free_space(c); + if (err) + goto out; + } + + err = check_free_space(c); + if (err) + goto out; + + if (c->old_leb_cnt != c->leb_cnt) { + struct ubifs_sb_node *sup; + + sup = ubifs_read_sb_node(c); + if (IS_ERR(sup)) { + err = PTR_ERR(sup); + goto out; + } + sup->leb_cnt = cpu_to_le32(c->leb_cnt); + err = ubifs_write_sb_node(c, sup); + kfree(sup); + if (err) + goto out; + } + + if (c->need_recovery) { + ubifs_msg("completing deferred recovery"); + err = ubifs_write_rcvrd_mst_node(c); + if (err) + goto out; + err = ubifs_recover_size(c); + if (err) + goto out; + err = ubifs_clean_lebs(c, c->sbuf); + if (err) + goto out; + err = ubifs_recover_inl_heads(c, c->sbuf); + if (err) + goto out; + } else { + /* A readonly mount is not allowed to have orphans */ + ubifs_assert(c->tot_orphans == 0); + err = ubifs_clear_orphans(c); + if (err) + goto out; + } + + if (!(c->mst_node->flags & cpu_to_le32(UBIFS_MST_DIRTY))) { + c->mst_node->flags |= cpu_to_le32(UBIFS_MST_DIRTY); + err = ubifs_write_master(c); + if (err) + goto out; + } + + c->ileb_buf = vmalloc(c->leb_size); + if (!c->ileb_buf) { + err = -ENOMEM; + goto out; + } + + c->write_reserve_buf = kmalloc(COMPRESSED_DATA_NODE_BUF_SZ, GFP_KERNEL); + if (!c->write_reserve_buf) { + err = -ENOMEM; + goto out; + } + + err = ubifs_lpt_init(c, 0, 1); + if (err) + goto out; + + /* Create background thread */ + c->bgt = kthread_create(ubifs_bg_thread, c, "%s", c->bgt_name); + if (IS_ERR(c->bgt)) { + err = PTR_ERR(c->bgt); + c->bgt = NULL; + ubifs_err("cannot spawn \"%s\", error %d", + c->bgt_name, err); + goto out; + } + wake_up_process(c->bgt); + + c->orph_buf = vmalloc(c->leb_size); + if (!c->orph_buf) { + err = -ENOMEM; + goto out; + } - return 0; + /* Check for enough log space */ + lnum = c->lhead_lnum + 1; + if (lnum >= UBIFS_LOG_LNUM + c->log_lebs) + lnum = UBIFS_LOG_LNUM; + if (lnum == c->ltail_lnum) { + err = ubifs_consolidate_log(c); + if (err) + goto out; + } -out_infos: - spin_lock(&ubifs_infos_lock); - list_del(&c->infos_list); - spin_unlock(&ubifs_infos_lock); -out_orphans: - free_orphans(c); -out_journal: -out_lpt: - ubifs_lpt_free(c, 0); -out_master: - kfree(c->mst_node); - kfree(c->rcvrd_mst_node); - if (c->bgt) + if (c->need_recovery) + err = ubifs_rcvry_gc_commit(c); + else + err = ubifs_leb_unmap(c, c->gc_lnum); + if (err) + goto out; + + dbg_gen("re-mounted read-write"); + c->remounting_rw = 0; + + if (c->need_recovery) { + c->need_recovery = 0; + ubifs_msg("deferred recovery completed"); + } else { + /* + * Do not run the debugging space check if the were doing + * recovery, because when we saved the information we had the + * file-system in a state where the TNC and lprops has been + * modified in memory, but all the I/O operations (including a + * commit) were deferred. So the file-system was in + * "non-committed" state. Now the file-system is in committed + * state, and of course the amount of free space will change + * because, for example, the old index size was imprecise. + */ + err = dbg_check_space_info(c); + } + + mutex_unlock(&c->umount_mutex); + return err; + +out: + c->ro_mount = 1; + vfree(c->orph_buf); + c->orph_buf = NULL; + if (c->bgt) { kthread_stop(c->bgt); - kfree(c->cbuf); -out_free: + c->bgt = NULL; + } + free_wbufs(c); + kfree(c->write_reserve_buf); + c->write_reserve_buf = NULL; vfree(c->ileb_buf); - vfree(c->sbuf); - kfree(c->bottom_up_buf); - ubifs_debugging_exit(c); + c->ileb_buf = NULL; + ubifs_lpt_free(c, 1); + c->remounting_rw = 0; + mutex_unlock(&c->umount_mutex); return err; } /** - * ubifs_umount - un-mount UBIFS file-system. + * ubifs_remount_ro - re-mount in read-only mode. * @c: UBIFS file-system description object * - * Note, this function is called to free allocated resourced when un-mounting, - * as well as free resources when an error occurred while we were half way - * through mounting (error path cleanup function). So it has to make sure the - * resource was actually allocated before freeing it. + * We assume VFS has stopped writing. Possibly the background thread could be + * running a commit, however kthread_stop will wait in that case. */ -void ubifs_umount(struct ubifs_info *c) +static void ubifs_remount_ro(struct ubifs_info *c) { - dbg_gen("un-mounting UBI device %d, volume %d", c->vi.ubi_num, - c->vi.vol_id); + int i, err; - spin_lock(&ubifs_infos_lock); - list_del(&c->infos_list); - spin_unlock(&ubifs_infos_lock); + ubifs_assert(!c->need_recovery); + ubifs_assert(!c->ro_mount); - if (c->bgt) + mutex_lock(&c->umount_mutex); + if (c->bgt) { kthread_stop(c->bgt); + c->bgt = NULL; + } - free_orphans(c); - ubifs_lpt_free(c, 0); + dbg_save_space_info(c); - kfree(c->cbuf); - kfree(c->rcvrd_mst_node); - kfree(c->mst_node); + for (i = 0; i < c->jhead_cnt; i++) + ubifs_wbuf_sync(&c->jheads[i].wbuf); + + c->mst_node->flags &= ~cpu_to_le32(UBIFS_MST_DIRTY); + c->mst_node->flags |= cpu_to_le32(UBIFS_MST_NO_ORPHS); + c->mst_node->gc_lnum = cpu_to_le32(c->gc_lnum); + err = ubifs_write_master(c); + if (err) + ubifs_ro_mode(c, err); + + vfree(c->orph_buf); + c->orph_buf = NULL; + kfree(c->write_reserve_buf); + c->write_reserve_buf = NULL; vfree(c->ileb_buf); - vfree(c->sbuf); - kfree(c->bottom_up_buf); - ubifs_debugging_exit(c); + c->ileb_buf = NULL; + ubifs_lpt_free(c, 1); + c->ro_mount = 1; + err = dbg_check_space_info(c); + if (err) + ubifs_ro_mode(c, err); + mutex_unlock(&c->umount_mutex); +} - /* Finally free U-Boot's global copy of superblock */ - if (ubifs_sb != NULL) { - free(ubifs_sb->s_fs_info); - free(ubifs_sb); +static void ubifs_put_super(struct super_block *sb) +{ + int i; + struct ubifs_info *c = sb->s_fs_info; + + ubifs_msg("un-mount UBI device %d, volume %d", c->vi.ubi_num, + c->vi.vol_id); + + /* + * The following asserts are only valid if there has not been a failure + * of the media. For example, there will be dirty inodes if we failed + * to write them back because of I/O errors. + */ + if (!c->ro_error) { + ubifs_assert(c->bi.idx_growth == 0); + ubifs_assert(c->bi.dd_growth == 0); + ubifs_assert(c->bi.data_growth == 0); + } + + /* + * The 'c->umount_lock' prevents races between UBIFS memory shrinker + * and file system un-mount. Namely, it prevents the shrinker from + * picking this superblock for shrinking - it will be just skipped if + * the mutex is locked. + */ + mutex_lock(&c->umount_mutex); + if (!c->ro_mount) { + /* + * First of all kill the background thread to make sure it does + * not interfere with un-mounting and freeing resources. + */ + if (c->bgt) { + kthread_stop(c->bgt); + c->bgt = NULL; + } + + /* + * On fatal errors c->ro_error is set to 1, in which case we do + * not write the master node. + */ + if (!c->ro_error) { + int err; + + /* Synchronize write-buffers */ + for (i = 0; i < c->jhead_cnt; i++) + ubifs_wbuf_sync(&c->jheads[i].wbuf); + + /* + * We are being cleanly unmounted which means the + * orphans were killed - indicate this in the master + * node. Also save the reserved GC LEB number. + */ + c->mst_node->flags &= ~cpu_to_le32(UBIFS_MST_DIRTY); + c->mst_node->flags |= cpu_to_le32(UBIFS_MST_NO_ORPHS); + c->mst_node->gc_lnum = cpu_to_le32(c->gc_lnum); + err = ubifs_write_master(c); + if (err) + /* + * Recovery will attempt to fix the master area + * next mount, so we just print a message and + * continue to unmount normally. + */ + ubifs_err("failed to write master node, error %d", + err); + } else { +#ifndef __UBOOT__ + for (i = 0; i < c->jhead_cnt; i++) + /* Make sure write-buffer timers are canceled */ + hrtimer_cancel(&c->jheads[i].wbuf.timer); +#endif + } } + + ubifs_umount(c); +#ifndef __UBOOT__ + bdi_destroy(&c->bdi); +#endif + ubi_close_volume(c->ubi); + mutex_unlock(&c->umount_mutex); +} +#endif + +#ifndef __UBOOT__ +static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) +{ + int err; + struct ubifs_info *c = sb->s_fs_info; + + sync_filesystem(sb); + dbg_gen("old flags %#lx, new flags %#x", sb->s_flags, *flags); + + err = ubifs_parse_options(c, data, 1); + if (err) { + ubifs_err("invalid or unknown remount parameter"); + return err; + } + + if (c->ro_mount && !(*flags & MS_RDONLY)) { + if (c->ro_error) { + ubifs_msg("cannot re-mount R/W due to prior errors"); + return -EROFS; + } + if (c->ro_media) { + ubifs_msg("cannot re-mount R/W - UBI volume is R/O"); + return -EROFS; + } + err = ubifs_remount_rw(c); + if (err) + return err; + } else if (!c->ro_mount && (*flags & MS_RDONLY)) { + if (c->ro_error) { + ubifs_msg("cannot re-mount R/O due to prior errors"); + return -EROFS; + } + ubifs_remount_ro(c); + } + + if (c->bulk_read == 1) + bu_init(c); + else { + dbg_gen("disable bulk-read"); + kfree(c->bu.buf); + c->bu.buf = NULL; + } + + ubifs_assert(c->lst.taken_empty_lebs > 0); + return 0; } +#endif + +const struct super_operations ubifs_super_operations = { + .alloc_inode = ubifs_alloc_inode, +#ifndef __UBOOT__ + .destroy_inode = ubifs_destroy_inode, + .put_super = ubifs_put_super, + .write_inode = ubifs_write_inode, + .evict_inode = ubifs_evict_inode, + .statfs = ubifs_statfs, +#endif + .dirty_inode = ubifs_dirty_inode, +#ifndef __UBOOT__ + .remount_fs = ubifs_remount_fs, + .show_options = ubifs_show_options, + .sync_fs = ubifs_sync_fs, +#endif +}; /** * open_ubi - parse UBI device name string and open the UBI device. * @name: UBI volume name * @mode: UBI volume open mode * - * There are several ways to specify UBI volumes when mounting UBIFS: - * o ubiX_Y - UBI device number X, volume Y; - * o ubiY - UBI device number 0, volume Y; + * The primary method of mounting UBIFS is by specifying the UBI volume + * character device node path. However, UBIFS may also be mounted withoug any + * character device node using one of the following methods: + * + * o ubiX_Y - mount UBI device number X, volume Y; + * o ubiY - mount UBI device number 0, volume Y; * o ubiX:NAME - mount UBI device X, volume with name NAME; * o ubi:NAME - mount UBI device 0, volume with name NAME. * * Alternative '!' separator may be used instead of ':' (because some shells * like busybox may interpret ':' as an NFS host name separator). This function - * returns ubi volume object in case of success and a negative error code in - * case of failure. + * returns UBI volume description object in case of success and a negative + * error code in case of failure. */ static struct ubi_volume_desc *open_ubi(const char *name, int mode) { +#ifndef __UBOOT__ + struct ubi_volume_desc *ubi; +#endif int dev, vol; char *endptr; +#ifndef __UBOOT__ + /* First, try to open using the device node path method */ + ubi = ubi_open_volume_path(name, mode); + if (!IS_ERR(ubi)) + return ubi; +#endif + + /* Try the "nodev" method */ if (name[0] != 'u' || name[1] != 'b' || name[2] != 'i') return ERR_PTR(-EINVAL); @@ -906,78 +2187,106 @@ static struct ubi_volume_desc *open_ubi(const char *name, int mode) return ERR_PTR(-EINVAL); } -static int ubifs_fill_super(struct super_block *sb, void *data, int silent) +static struct ubifs_info *alloc_ubifs_info(struct ubi_volume_desc *ubi) { - struct ubi_volume_desc *ubi = sb->s_fs_info; struct ubifs_info *c; - struct inode *root; - int err; c = kzalloc(sizeof(struct ubifs_info), GFP_KERNEL); - if (!c) - return -ENOMEM; + if (c) { + spin_lock_init(&c->cnt_lock); + spin_lock_init(&c->cs_lock); + spin_lock_init(&c->buds_lock); + spin_lock_init(&c->space_lock); + spin_lock_init(&c->orphan_lock); + init_rwsem(&c->commit_sem); + mutex_init(&c->lp_mutex); + mutex_init(&c->tnc_mutex); + mutex_init(&c->log_mutex); + mutex_init(&c->mst_mutex); + mutex_init(&c->umount_mutex); + mutex_init(&c->bu_mutex); + mutex_init(&c->write_reserve_mutex); + init_waitqueue_head(&c->cmt_wq); + c->buds = RB_ROOT; + c->old_idx = RB_ROOT; + c->size_tree = RB_ROOT; + c->orph_tree = RB_ROOT; + INIT_LIST_HEAD(&c->infos_list); + INIT_LIST_HEAD(&c->idx_gc); + INIT_LIST_HEAD(&c->replay_list); + INIT_LIST_HEAD(&c->replay_buds); + INIT_LIST_HEAD(&c->uncat_list); + INIT_LIST_HEAD(&c->empty_list); + INIT_LIST_HEAD(&c->freeable_list); + INIT_LIST_HEAD(&c->frdi_idx_list); + INIT_LIST_HEAD(&c->unclean_leb_list); + INIT_LIST_HEAD(&c->old_buds); + INIT_LIST_HEAD(&c->orph_list); + INIT_LIST_HEAD(&c->orph_new); + c->no_chk_data_crc = 1; + + c->highest_inum = UBIFS_FIRST_INO; + c->lhead_lnum = c->ltail_lnum = UBIFS_LOG_LNUM; + + ubi_get_volume_info(ubi, &c->vi); + ubi_get_device_info(c->vi.ubi_num, &c->di); + } + return c; +} - spin_lock_init(&c->cnt_lock); - spin_lock_init(&c->cs_lock); - spin_lock_init(&c->buds_lock); - spin_lock_init(&c->space_lock); - spin_lock_init(&c->orphan_lock); - init_rwsem(&c->commit_sem); - mutex_init(&c->lp_mutex); - mutex_init(&c->tnc_mutex); - mutex_init(&c->log_mutex); - mutex_init(&c->mst_mutex); - mutex_init(&c->umount_mutex); - init_waitqueue_head(&c->cmt_wq); - c->buds = RB_ROOT; - c->old_idx = RB_ROOT; - c->size_tree = RB_ROOT; - c->orph_tree = RB_ROOT; - INIT_LIST_HEAD(&c->infos_list); - INIT_LIST_HEAD(&c->idx_gc); - INIT_LIST_HEAD(&c->replay_list); - INIT_LIST_HEAD(&c->replay_buds); - INIT_LIST_HEAD(&c->uncat_list); - INIT_LIST_HEAD(&c->empty_list); - INIT_LIST_HEAD(&c->freeable_list); - INIT_LIST_HEAD(&c->frdi_idx_list); - INIT_LIST_HEAD(&c->unclean_leb_list); - INIT_LIST_HEAD(&c->old_buds); - INIT_LIST_HEAD(&c->orph_list); - INIT_LIST_HEAD(&c->orph_new); - - c->highest_inum = UBIFS_FIRST_INO; - c->lhead_lnum = c->ltail_lnum = UBIFS_LOG_LNUM; - - ubi_get_volume_info(ubi, &c->vi); - ubi_get_device_info(c->vi.ubi_num, &c->di); +static int ubifs_fill_super(struct super_block *sb, void *data, int silent) +{ + struct ubifs_info *c = sb->s_fs_info; + struct inode *root; + int err; + c->vfs_sb = sb; +#ifndef __UBOOT__ /* Re-open the UBI device in read-write mode */ + c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READWRITE); +#else + /* U-Boot read only mode */ c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY); +#endif + if (IS_ERR(c->ubi)) { err = PTR_ERR(c->ubi); - goto out_free; + goto out; } - c->vfs_sb = sb; +#ifndef __UBOOT__ + /* + * UBIFS provides 'backing_dev_info' in order to disable read-ahead. For + * UBIFS, I/O is not deferred, it is done immediately in readpage, + * which means the user would have to wait not just for their own I/O + * but the read-ahead I/O as well i.e. completely pointless. + * + * Read-ahead will be disabled because @c->bdi.ra_pages is 0. + */ + co>bdi.name = "ubifs", + c->bdi.capabilities = BDI_CAP_MAP_COPY; + err = bdi_init(&c->bdi); + if (err) + goto out_close; + err = bdi_register(&c->bdi, NULL, "ubifs_%d_%d", + c->vi.ubi_num, c->vi.vol_id); + if (err) + goto out_bdi; + err = ubifs_parse_options(c, data, 0); + if (err) + goto out_bdi; + + sb->s_bdi = &c->bdi; +#endif sb->s_fs_info = c; sb->s_magic = UBIFS_SUPER_MAGIC; sb->s_blocksize = UBIFS_BLOCK_SIZE; sb->s_blocksize_bits = UBIFS_BLOCK_SHIFT; - sb->s_dev = c->vi.cdev; sb->s_maxbytes = c->max_inode_sz = key_max_inode_size(c); if (c->max_inode_sz > MAX_LFS_FILESIZE) sb->s_maxbytes = c->max_inode_sz = MAX_LFS_FILESIZE; - - if (c->rw_incompat) { - ubifs_err("the file-system is not R/W-compatible"); - ubifs_msg("on-flash format version is w%d/r%d, but software " - "only supports up to version w%d/r%d", c->fmt_version, - c->ro_compat_version, UBIFS_FORMAT_VERSION, - UBIFS_RO_COMPAT_VERSION); - return -EROFS; - } + sb->s_op = &ubifs_super_operations; mutex_lock(&c->umount_mutex); err = mount_ubifs(c); @@ -993,7 +2302,15 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) goto out_umount; } +#ifndef __UBOOT__ + sb->s_root = d_make_root(root); + if (!sb->s_root) { + err = -ENOMEM; + goto out_umount; + } +#else sb->s_root = NULL; +#endif mutex_unlock(&c->umount_mutex); return 0; @@ -1002,24 +2319,130 @@ out_umount: ubifs_umount(c); out_unlock: mutex_unlock(&c->umount_mutex); +#ifndef __UBOOT__ +out_bdi: + bdi_destroy(&c->bdi); +out_close: +#endif ubi_close_volume(c->ubi); -out_free: - kfree(c); +out: return err; } static int sb_test(struct super_block *sb, void *data) { - dev_t *dev = data; + struct ubifs_info *c1 = data; + struct ubifs_info *c = sb->s_fs_info; + + return c->vi.cdev == c1->vi.cdev; +} + +static int sb_set(struct super_block *sb, void *data) +{ + sb->s_fs_info = data; + return set_anon_super(sb, NULL); +} + +static struct super_block *alloc_super(struct file_system_type *type, int flags) +{ + struct super_block *s; + int err; + + s = kzalloc(sizeof(struct super_block), GFP_USER); + if (!s) { + err = -ENOMEM; + return ERR_PTR(err); + } + + INIT_HLIST_NODE(&s->s_instances); + INIT_LIST_HEAD(&s->s_inodes); + s->s_time_gran = 1000000000; + s->s_flags = flags; + + return s; +} + +/** + * sget - find or create a superblock + * @type: filesystem type superblock should belong to + * @test: comparison callback + * @set: setup callback + * @flags: mount flags + * @data: argument to each of them + */ +struct super_block *sget(struct file_system_type *type, + int (*test)(struct super_block *,void *), + int (*set)(struct super_block *,void *), + int flags, + void *data) +{ + struct super_block *s = NULL; +#ifndef __UBOOT__ + struct super_block *old; +#endif + int err; - return sb->s_dev == *dev; +#ifndef __UBOOT__ +retry: + spin_lock(&sb_lock); + if (test) { + hlist_for_each_entry(old, &type->fs_supers, s_instances) { + if (!test(old, data)) + continue; + if (!grab_super(old)) + goto retry; + if (s) { + up_write(&s->s_umount); + destroy_super(s); + s = NULL; + } + return old; + } + } +#endif + if (!s) { + spin_unlock(&sb_lock); + s = alloc_super(type, flags); + if (!s) + return ERR_PTR(-ENOMEM); +#ifndef __UBOOT__ + goto retry; +#endif + } + + err = set(s, data); + if (err) { +#ifndef __UBOOT__ + spin_unlock(&sb_lock); + up_write(&s->s_umount); + destroy_super(s); +#endif + return ERR_PTR(err); + } + s->s_type = type; +#ifndef __UBOOT__ + strlcpy(s->s_id, type->name, sizeof(s->s_id)); +#else + strncpy(s->s_id, type->name, sizeof(s->s_id)); +#endif + list_add_tail(&s->s_list, &super_blocks); + hlist_add_head(&s->s_instances, &type->fs_supers); +#ifndef __UBOOT__ + spin_unlock(&sb_lock); + get_filesystem(type); + register_shrinker(&s->s_shrink); +#endif + return s; } -static int ubifs_get_sb(struct file_system_type *fs_type, int flags, - const char *name, void *data, struct vfsmount *mnt) +EXPORT_SYMBOL(sget); + + +static struct dentry *ubifs_mount(struct file_system_type *fs_type, int flags, + const char *name, void *data) { struct ubi_volume_desc *ubi; - struct ubi_volume_info vi; + struct ubifs_info *c; struct super_block *sb; int err; @@ -1034,32 +2457,34 @@ static int ubifs_get_sb(struct file_system_type *fs_type, int flags, if (IS_ERR(ubi)) { ubifs_err("cannot open \"%s\", error %d", name, (int)PTR_ERR(ubi)); - return PTR_ERR(ubi); + return ERR_CAST(ubi); + } + + c = alloc_ubifs_info(ubi); + if (!c) { + err = -ENOMEM; + goto out_close; } - ubi_get_volume_info(ubi, &vi); - dbg_gen("opened ubi%d_%d", vi.ubi_num, vi.vol_id); + dbg_gen("opened ubi%d_%d", c->vi.ubi_num, c->vi.vol_id); - sb = sget(fs_type, &sb_test, &sb_set, &vi.cdev); + sb = sget(fs_type, sb_test, sb_set, flags, c); if (IS_ERR(sb)) { err = PTR_ERR(sb); + kfree(c); goto out_close; } if (sb->s_root) { + struct ubifs_info *c1 = sb->s_fs_info; + kfree(c); /* A new mount point for already mounted UBIFS */ dbg_gen("this ubi volume is already mounted"); - if ((flags ^ sb->s_flags) & MS_RDONLY) { + if (!!(flags & MS_RDONLY) != c1->ro_mount) { err = -EBUSY; goto out_deact; } } else { - sb->s_flags = flags; - /* - * Pass 'ubi' to 'fill_super()' in sb->s_fs_info where it is - * replaced by 'c'. - */ - sb->s_fs_info = ubi; err = ubifs_fill_super(sb, data, flags & MS_SILENT ? 1 : 0); if (err) goto out_deact; @@ -1070,17 +2495,53 @@ static int ubifs_get_sb(struct file_system_type *fs_type, int flags, /* 'fill_super()' opens ubi again so we must close it here */ ubi_close_volume(ubi); +#ifdef __UBOOT__ ubifs_sb = sb; return 0; +#else + return dget(sb->s_root); +#endif out_deact: - up_write(&sb->s_umount); +#ifndef __UBOOT__ + deactivate_locked_super(sb); +#endif out_close: ubi_close_volume(ubi); - return err; + return ERR_PTR(err); +} + +static void kill_ubifs_super(struct super_block *s) +{ + struct ubifs_info *c = s->s_fs_info; +#ifndef __UBOOT__ + kill_anon_super(s); +#endif + kfree(c); +} + +static struct file_system_type ubifs_fs_type = { + .name = "ubifs", + .owner = THIS_MODULE, + .mount = ubifs_mount, + .kill_sb = kill_ubifs_super, +}; +#ifndef __UBOOT__ +MODULE_ALIAS_FS("ubifs"); + +/* + * Inode slab cache constructor. + */ +static void inode_slab_ctor(void *obj) +{ + struct ubifs_inode *ui = obj; + inode_init_once(&ui->vfs_inode); } -int __init ubifs_init(void) +static int __init ubifs_init(void) +#else +int ubifs_init(void) +#endif { int err; @@ -1136,41 +2597,84 @@ int __init ubifs_init(void) * UBIFS_BLOCK_SIZE. It is assumed that both are powers of 2. */ if (PAGE_CACHE_SIZE < UBIFS_BLOCK_SIZE) { - ubifs_err("VFS page cache size is %u bytes, but UBIFS requires" - " at least 4096 bytes", + ubifs_err("VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes", (unsigned int)PAGE_CACHE_SIZE); return -EINVAL; } - err = -ENOMEM; +#ifndef __UBOOT__ + ubifs_inode_slab = kmem_cache_create("ubifs_inode_slab", + sizeof(struct ubifs_inode), 0, + SLAB_MEM_SPREAD | SLAB_RECLAIM_ACCOUNT, + &inode_slab_ctor); + if (!ubifs_inode_slab) + return -ENOMEM; + + register_shrinker(&ubifs_shrinker_info); +#endif err = ubifs_compressors_init(); if (err) goto out_shrinker; +#ifndef __UBOOT__ + err = dbg_debugfs_init(); + if (err) + goto out_compr; + + err = register_filesystem(&ubifs_fs_type); + if (err) { + ubifs_err("cannot register file system, error %d", err); + goto out_dbg; + } +#endif return 0; +#ifndef __UBOOT__ +out_dbg: + dbg_debugfs_exit(); +out_compr: + ubifs_compressors_exit(); +#endif out_shrinker: +#ifndef __UBOOT__ + unregister_shrinker(&ubifs_shrinker_info); +#endif + kmem_cache_destroy(ubifs_inode_slab); return err; } +/* late_initcall to let compressors initialize first */ +late_initcall(ubifs_init); -/* - * ubifsmount... - */ +#ifndef __UBOOT__ +static void __exit ubifs_exit(void) +{ + ubifs_assert(list_empty(&ubifs_infos)); + ubifs_assert(atomic_long_read(&ubifs_clean_zn_cnt) == 0); -static struct file_system_type ubifs_fs_type = { - .name = "ubifs", - .owner = THIS_MODULE, - .get_sb = ubifs_get_sb, -}; + dbg_debugfs_exit(); + ubifs_compressors_exit(); + unregister_shrinker(&ubifs_shrinker_info); -int ubifs_mount(char *name) + /* + * Make sure all delayed rcu free inodes are flushed before we + * destroy cache. + */ + rcu_barrier(); + kmem_cache_destroy(ubifs_inode_slab); + unregister_filesystem(&ubifs_fs_type); +} +module_exit(ubifs_exit); + +MODULE_LICENSE("GPL"); +MODULE_VERSION(__stringify(UBIFS_VERSION)); +MODULE_AUTHOR("Artem Bityutskiy, Adrian Hunter"); +MODULE_DESCRIPTION("UBIFS - UBI File System"); +#else +int uboot_ubifs_mount(char *vol_name) { + struct dentry *ret; int flags; - void *data; - struct vfsmount *mnt; - int ret; - struct ubifs_info *c; /* * First unmount if allready mounted @@ -1178,23 +2682,17 @@ int ubifs_mount(char *name) if (ubifs_sb) ubifs_umount(ubifs_sb->s_fs_info); - INIT_LIST_HEAD(&ubifs_infos); - INIT_LIST_HEAD(&ubifs_fs_type.fs_supers); - /* * Mount in read-only mode */ flags = MS_RDONLY; - data = NULL; - mnt = NULL; - ret = ubifs_get_sb(&ubifs_fs_type, flags, name, data, mnt); - if (ret) { - ubifs_err("Error reading superblock on volume '%s' errno=%d!\n", name, ret); + ret = ubifs_mount(&ubifs_fs_type, flags, vol_name, NULL); + if (IS_ERR(ret)) { + printf("Error reading superblock on volume '%s' " \ + "errno=%d!\n", vol_name, (int)PTR_ERR(ret)); return -1; } - c = ubifs_sb->s_fs_info; - ubi_close_volume(c->ubi); - return 0; } +#endif diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index ccda9387bc..95cae548bf 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Adrian Hunter * Artem Bityutskiy (Битюцкий Артём) @@ -30,6 +19,14 @@ * the mutex locked. */ +#ifndef __UBOOT__ +#include +#include +#else +#include +#include +#include +#endif #include "ubifs.h" /* @@ -176,27 +173,11 @@ static int ins_clr_old_idx_znode(struct ubifs_info *c, */ void destroy_old_idx(struct ubifs_info *c) { - struct rb_node *this = c->old_idx.rb_node; - struct ubifs_old_idx *old_idx; + struct ubifs_old_idx *old_idx, *n; - while (this) { - if (this->rb_left) { - this = this->rb_left; - continue; - } else if (this->rb_right) { - this = this->rb_right; - continue; - } - old_idx = rb_entry(this, struct ubifs_old_idx, rb); - this = rb_parent(this); - if (this) { - if (this->rb_left == &old_idx->rb) - this->rb_left = NULL; - else - this->rb_right = NULL; - } + rbtree_postorder_for_each_entry_safe(old_idx, n, &c->old_idx, rb) kfree(old_idx); - } + c->old_idx = RB_ROOT; } @@ -221,7 +202,7 @@ static struct ubifs_znode *copy_znode(struct ubifs_info *c, __set_bit(DIRTY_ZNODE, &zn->flags); __clear_bit(COW_ZNODE, &zn->flags); - ubifs_assert(!test_bit(OBSOLETE_ZNODE, &znode->flags)); + ubifs_assert(!ubifs_zn_obsolete(znode)); __set_bit(OBSOLETE_ZNODE, &znode->flags); if (znode->level != 0) { @@ -269,7 +250,7 @@ static struct ubifs_znode *dirty_cow_znode(struct ubifs_info *c, struct ubifs_znode *zn; int err; - if (!test_bit(COW_ZNODE, &znode->flags)) { + if (!ubifs_zn_cow(znode)) { /* znode is not being committed */ if (!test_and_set_bit(DIRTY_ZNODE, &znode->flags)) { atomic_long_inc(&c->dirty_zn_cnt); @@ -337,17 +318,16 @@ static int lnc_add(struct ubifs_info *c, struct ubifs_zbranch *zbr, err = ubifs_validate_entry(c, dent); if (err) { - dbg_dump_stack(); - dbg_dump_node(c, dent); + dump_stack(); + ubifs_dump_node(c, dent); return err; } - lnc_node = kmalloc(zbr->len, GFP_NOFS); + lnc_node = kmemdup(node, zbr->len, GFP_NOFS); if (!lnc_node) /* We don't have to have the cache, so no error */ return 0; - memcpy(lnc_node, node, zbr->len); zbr->leaf = lnc_node; return 0; } @@ -371,8 +351,8 @@ static int lnc_add_directly(struct ubifs_info *c, struct ubifs_zbranch *zbr, err = ubifs_validate_entry(c, node); if (err) { - dbg_dump_stack(); - dbg_dump_node(c, node); + dump_stack(); + ubifs_dump_node(c, node); return err; } @@ -445,8 +425,11 @@ static int tnc_read_node_nm(struct ubifs_info *c, struct ubifs_zbranch *zbr, * * Note, this function does not check CRC of data nodes if @c->no_chk_data_crc * is true (it is controlled by corresponding mount option). However, if - * @c->always_chk_crc is true, @c->no_chk_data_crc is ignored and CRC is always - * checked. + * @c->mounting or @c->remounting_rw is true (we are mounting or re-mounting to + * R/W mode), @c->no_chk_data_crc is ignored and CRC is checked. This is + * because during mounting or re-mounting from R/O mode to R/W mode we may read + * journal nodes (when replying the journal or doing the recovery) and the + * journal nodes may potentially be corrupted, so checking is required. */ static int try_read_node(const struct ubifs_info *c, void *buf, int type, int len, int lnum, int offs) @@ -457,7 +440,7 @@ static int try_read_node(const struct ubifs_info *c, void *buf, int type, dbg_io("LEB %d:%d, %s, length %d", lnum, offs, dbg_ntype(type), len); - err = ubi_read(c->ubi, lnum, buf, offs, len); + err = ubifs_leb_read(c, lnum, buf, offs, len, 1); if (err) { ubifs_err("cannot read node type %d from LEB %d:%d, error %d", type, lnum, offs, err); @@ -474,7 +457,8 @@ static int try_read_node(const struct ubifs_info *c, void *buf, int type, if (node_len != len) return 0; - if (type == UBIFS_DATA_NODE && !c->always_chk_crc && c->no_chk_data_crc) + if (type == UBIFS_DATA_NODE && c->no_chk_data_crc && !c->mounting && + !c->remounting_rw) return 1; crc = crc32(UBIFS_CRC32_INIT, buf + 8, node_len - 8); @@ -500,7 +484,7 @@ static int fallible_read_node(struct ubifs_info *c, const union ubifs_key *key, { int ret; - dbg_tnc("LEB %d:%d, key %s", zbr->lnum, zbr->offs, DBGKEY(key)); + dbg_tnck(key, "LEB %d:%d, key ", zbr->lnum, zbr->offs); ret = try_read_node(c, node, key_type(c, key), zbr->len, zbr->lnum, zbr->offs); @@ -514,8 +498,8 @@ static int fallible_read_node(struct ubifs_info *c, const union ubifs_key *key, ret = 0; } if (ret == 0 && c->replaying) - dbg_mnt("dangling branch LEB %d:%d len %d, key %s", - zbr->lnum, zbr->offs, zbr->len, DBGKEY(key)); + dbg_mntk(key, "dangling branch LEB %d:%d len %d, key ", + zbr->lnum, zbr->offs, zbr->len); return ret; } @@ -990,9 +974,9 @@ static int fallible_resolve_collision(struct ubifs_info *c, if (adding || !o_znode) return 0; - dbg_mnt("dangling match LEB %d:%d len %d %s", + dbg_mntk(key, "dangling match LEB %d:%d len %d key ", o_znode->zbranch[o_n].lnum, o_znode->zbranch[o_n].offs, - o_znode->zbranch[o_n].len, DBGKEY(key)); + o_znode->zbranch[o_n].len); *zn = o_znode; *n = o_n; return 1; @@ -1158,8 +1142,8 @@ static struct ubifs_znode *dirty_cow_bottom_up(struct ubifs_info *c, * o exact match, i.e. the found zero-level znode contains key @key, then %1 * is returned and slot number of the matched branch is stored in @n; * o not exact match, which means that zero-level znode does not contain - * @key, then %0 is returned and slot number of the closed branch is stored - * in @n; + * @key, then %0 is returned and slot number of the closest branch is stored + * in @n; * o @key is so small that it is even less than the lowest key of the * leftmost zero-level node, then %0 is returned and %0 is stored in @n. * @@ -1174,7 +1158,8 @@ int ubifs_lookup_level0(struct ubifs_info *c, const union ubifs_key *key, struct ubifs_znode *znode; unsigned long time = get_seconds(); - dbg_tnc("search key %s", DBGKEY(key)); + dbg_tnck(key, "search key "); + ubifs_assert(key_type(c, key) < UBIFS_INVALID_KEY); znode = c->zroot.znode; if (unlikely(!znode)) { @@ -1251,7 +1236,7 @@ int ubifs_lookup_level0(struct ubifs_info *c, const union ubifs_key *key, * splitting in the middle of the colliding sequence. Also, when * removing the leftmost key, we would have to correct the key of the * parent node, which would introduce additional complications. Namely, - * if we changed the the leftmost key of the parent znode, the garbage + * if we changed the leftmost key of the parent znode, the garbage * collector would be unable to find it (GC is doing this when GC'ing * indexing LEBs). Although we already have an additional RB-tree where * we save such changed znodes (see 'ins_clr_old_idx_znode()') until @@ -1309,7 +1294,7 @@ static int lookup_level0_dirty(struct ubifs_info *c, const union ubifs_key *key, struct ubifs_znode *znode; unsigned long time = get_seconds(); - dbg_tnc("search and dirty key %s", DBGKEY(key)); + dbg_tnck(key, "search and dirty key "); znode = c->zroot.znode; if (unlikely(!znode)) { @@ -1400,9 +1385,31 @@ static int lookup_level0_dirty(struct ubifs_info *c, const union ubifs_key *key, */ static int maybe_leb_gced(struct ubifs_info *c, int lnum, int gc_seq1) { +#ifndef __UBOOT__ + int gc_seq2, gced_lnum; + + gced_lnum = c->gced_lnum; + smp_rmb(); + gc_seq2 = c->gc_seq; + /* Same seq means no GC */ + if (gc_seq1 == gc_seq2) + return 0; + /* Different by more than 1 means we don't know */ + if (gc_seq1 + 1 != gc_seq2) + return 1; /* - * No garbage collection in the read-only U-Boot implementation + * We have seen the sequence number has increased by 1. Now we need to + * be sure we read the right LEB number, so read it again. */ + smp_rmb(); + if (gced_lnum != c->gced_lnum) + return 1; + /* Finally we can check lnum */ + if (gced_lnum == lnum) + return 1; +#else + /* No garbage collection in the read-only U-Boot implementation */ +#endif return 0; } @@ -1414,7 +1421,7 @@ static int maybe_leb_gced(struct ubifs_info *c, int lnum, int gc_seq1) * @lnum: LEB number is returned here * @offs: offset is returned here * - * This function look up and reads node with key @key. The caller has to make + * This function looks up and reads node with key @key. The caller has to make * sure the @node buffer is large enough to fit the node. Returns zero in case * of success, %-ENOENT if the node was not found, and a negative error code in * case of failure. The node location can be returned in @lnum and @offs. @@ -1458,6 +1465,12 @@ again: gc_seq1 = c->gc_seq; mutex_unlock(&c->tnc_mutex); + if (ubifs_get_wbuf(c, zbr.lnum)) { + /* We do not GC journal heads */ + err = ubifs_tnc_read_node(c, &zbr, node); + return err; + } + err = fallible_read_node(c, key, &zbr, node); if (err <= 0 || maybe_leb_gced(c, zbr.lnum, gc_seq1)) { /* @@ -1609,6 +1622,51 @@ out: return 0; } +/** + * read_wbuf - bulk-read from a LEB with a wbuf. + * @wbuf: wbuf that may overlap the read + * @buf: buffer into which to read + * @len: read length + * @lnum: LEB number from which to read + * @offs: offset from which to read + * + * This functions returns %0 on success or a negative error code on failure. + */ +static int read_wbuf(struct ubifs_wbuf *wbuf, void *buf, int len, int lnum, + int offs) +{ + const struct ubifs_info *c = wbuf->c; + int rlen, overlap; + + dbg_io("LEB %d:%d, length %d", lnum, offs, len); + ubifs_assert(wbuf && lnum >= 0 && lnum < c->leb_cnt && offs >= 0); + ubifs_assert(!(offs & 7) && offs < c->leb_size); + ubifs_assert(offs + len <= c->leb_size); + + spin_lock(&wbuf->lock); + overlap = (lnum == wbuf->lnum && offs + len > wbuf->offs); + if (!overlap) { + /* We may safely unlock the write-buffer and read the data */ + spin_unlock(&wbuf->lock); + return ubifs_leb_read(c, lnum, buf, offs, len, 0); + } + + /* Don't read under wbuf */ + rlen = wbuf->offs - offs; + if (rlen < 0) + rlen = 0; + + /* Copy the rest from the write-buffer */ + memcpy(buf + rlen, wbuf->buf + offs + rlen - wbuf->offs, len - rlen); + spin_unlock(&wbuf->lock); + + if (rlen > 0) + /* Read everything that goes before write-buffer */ + return ubifs_leb_read(c, lnum, buf, offs, rlen, 0); + + return 0; +} + /** * validate_data_node - validate data nodes for bulk-read. * @c: UBIFS file-system description object @@ -1647,8 +1705,8 @@ static int validate_data_node(struct ubifs_info *c, void *buf, if (!keys_eq(c, &zbr->key, &key1)) { ubifs_err("bad key in node at LEB %d:%d", zbr->lnum, zbr->offs); - dbg_tnc("looked for key %s found node's key %s", - DBGKEY(&zbr->key), DBGKEY1(&key1)); + dbg_tnck(&zbr->key, "looked for key "); + dbg_tnck(&key1, "found node's key "); goto out_err; } @@ -1658,8 +1716,8 @@ out_err: err = -EINVAL; out: ubifs_err("bad node at LEB %d:%d", zbr->lnum, zbr->offs); - dbg_dump_node(c, buf); - dbg_dump_stack(); + ubifs_dump_node(c, buf); + dump_stack(); return err; } @@ -1676,6 +1734,7 @@ out: int ubifs_tnc_bulk_read(struct ubifs_info *c, struct bu_info *bu) { int lnum = bu->zbranch[0].lnum, offs = bu->zbranch[0].offs, len, err, i; + struct ubifs_wbuf *wbuf; void *buf; len = bu->zbranch[bu->cnt - 1].offs; @@ -1686,7 +1745,11 @@ int ubifs_tnc_bulk_read(struct ubifs_info *c, struct bu_info *bu) } /* Do the read */ - err = ubi_read(c->ubi, lnum, bu->buf, offs, len); + wbuf = ubifs_get_wbuf(c, lnum); + if (wbuf) + err = read_wbuf(wbuf, bu->buf, len, lnum, offs); + else + err = ubifs_leb_read(c, lnum, bu->buf, offs, len, 0); /* Check for a race with GC */ if (maybe_leb_gced(c, lnum, bu->gc_seq)) @@ -1695,8 +1758,8 @@ int ubifs_tnc_bulk_read(struct ubifs_info *c, struct bu_info *bu) if (err && err != -EBADMSG) { ubifs_err("failed to read from LEB %d:%d, error %d", lnum, offs, err); - dbg_dump_stack(); - dbg_tnc("key %s", DBGKEY(&bu->key)); + dump_stack(); + dbg_tnck(&bu->key, "key "); return err; } @@ -1731,7 +1794,7 @@ static int do_lookup_nm(struct ubifs_info *c, const union ubifs_key *key, int found, n, err; struct ubifs_znode *znode; - dbg_tnc("name '%.*s' key %s", nm->len, nm->name, DBGKEY(key)); + dbg_tnck(key, "name '%.*s' key ", nm->len, nm->name); mutex_lock(&c->tnc_mutex); found = ubifs_lookup_level0(c, key, &znode, &n); if (!found) { @@ -1905,8 +1968,7 @@ again: zp = znode->parent; if (znode->child_cnt < c->fanout) { ubifs_assert(n != c->fanout); - dbg_tnc("inserted at %d level %d, key %s", n, znode->level, - DBGKEY(key)); + dbg_tnck(key, "inserted at %d level %d, key ", n, znode->level); insert_zbranch(znode, zbr, n); @@ -1921,7 +1983,7 @@ again: * Unfortunately, @znode does not have more empty slots and we have to * split it. */ - dbg_tnc("splitting level %d, key %s", znode->level, DBGKEY(key)); + dbg_tnck(key, "splitting level %d, key ", znode->level); if (znode->alt) /* @@ -2015,7 +2077,7 @@ do_split: } /* Insert new key and branch */ - dbg_tnc("inserting at %d level %d, key %s", n, zn->level, DBGKEY(key)); + dbg_tnck(key, "inserting at %d level %d, key ", n, zn->level); insert_zbranch(zi, zbr, n); @@ -2091,7 +2153,7 @@ int ubifs_tnc_add(struct ubifs_info *c, const union ubifs_key *key, int lnum, struct ubifs_znode *znode; mutex_lock(&c->tnc_mutex); - dbg_tnc("%d:%d, len %d, key %s", lnum, offs, len, DBGKEY(key)); + dbg_tnck(key, "%d:%d, len %d, key ", lnum, offs, len); found = lookup_level0_dirty(c, key, &znode, &n); if (!found) { struct ubifs_zbranch zbr; @@ -2140,8 +2202,8 @@ int ubifs_tnc_replace(struct ubifs_info *c, const union ubifs_key *key, struct ubifs_znode *znode; mutex_lock(&c->tnc_mutex); - dbg_tnc("old LEB %d:%d, new LEB %d:%d, len %d, key %s", old_lnum, - old_offs, lnum, offs, len, DBGKEY(key)); + dbg_tnck(key, "old LEB %d:%d, new LEB %d:%d, len %d, key ", old_lnum, + old_offs, lnum, offs, len); found = lookup_level0_dirty(c, key, &znode, &n); if (found < 0) { err = found; @@ -2223,8 +2285,8 @@ int ubifs_tnc_add_nm(struct ubifs_info *c, const union ubifs_key *key, struct ubifs_znode *znode; mutex_lock(&c->tnc_mutex); - dbg_tnc("LEB %d:%d, name '%.*s', key %s", lnum, offs, nm->len, nm->name, - DBGKEY(key)); + dbg_tnck(key, "LEB %d:%d, name '%.*s', key ", + lnum, offs, nm->len, nm->name); found = lookup_level0_dirty(c, key, &znode, &n); if (found < 0) { err = found; @@ -2282,7 +2344,7 @@ int ubifs_tnc_add_nm(struct ubifs_info *c, const union ubifs_key *key, * by passing 'ubifs_tnc_remove_nm()' the same key but * an unmatchable name. */ - struct qstr noname = { .len = 0, .name = "" }; + struct qstr noname = { .name = "" }; err = dbg_check_tnc(c, 0); mutex_unlock(&c->tnc_mutex); @@ -2317,14 +2379,14 @@ static int tnc_delete(struct ubifs_info *c, struct ubifs_znode *znode, int n) /* Delete without merge for now */ ubifs_assert(znode->level == 0); ubifs_assert(n >= 0 && n < c->fanout); - dbg_tnc("deleting %s", DBGKEY(&znode->zbranch[n].key)); + dbg_tnck(&znode->zbranch[n].key, "deleting key "); zbr = &znode->zbranch[n]; lnc_free(zbr); err = ubifs_add_dirt(c, zbr->lnum, zbr->len); if (err) { - dbg_dump_znode(c, znode); + ubifs_dump_znode(c, znode); return err; } @@ -2342,7 +2404,7 @@ static int tnc_delete(struct ubifs_info *c, struct ubifs_znode *znode, int n) */ do { - ubifs_assert(!test_bit(OBSOLETE_ZNODE, &znode->flags)); + ubifs_assert(!ubifs_zn_obsolete(znode)); ubifs_assert(ubifs_zn_dirty(znode)); zp = znode->parent; @@ -2398,9 +2460,8 @@ static int tnc_delete(struct ubifs_info *c, struct ubifs_znode *znode, int n) c->zroot.offs = zbr->offs; c->zroot.len = zbr->len; c->zroot.znode = znode; - ubifs_assert(!test_bit(OBSOLETE_ZNODE, - &zp->flags)); - ubifs_assert(test_bit(DIRTY_ZNODE, &zp->flags)); + ubifs_assert(!ubifs_zn_obsolete(zp)); + ubifs_assert(ubifs_zn_dirty(zp)); atomic_long_dec(&c->dirty_zn_cnt); if (zp->cnext) { @@ -2428,7 +2489,7 @@ int ubifs_tnc_remove(struct ubifs_info *c, const union ubifs_key *key) struct ubifs_znode *znode; mutex_lock(&c->tnc_mutex); - dbg_tnc("key %s", DBGKEY(key)); + dbg_tnck(key, "key "); found = lookup_level0_dirty(c, key, &znode, &n); if (found < 0) { err = found; @@ -2459,7 +2520,7 @@ int ubifs_tnc_remove_nm(struct ubifs_info *c, const union ubifs_key *key, struct ubifs_znode *znode; mutex_lock(&c->tnc_mutex); - dbg_tnc("%.*s, key %s", nm->len, nm->name, DBGKEY(key)); + dbg_tnck(key, "%.*s, key ", nm->len, nm->name); err = lookup_level0_dirty(c, key, &znode, &n); if (err < 0) goto out_unlock; @@ -2476,11 +2537,11 @@ int ubifs_tnc_remove_nm(struct ubifs_info *c, const union ubifs_key *key, if (err) { /* Ensure the znode is dirtied */ if (znode->cnext || !ubifs_zn_dirty(znode)) { - znode = dirty_cow_bottom_up(c, znode); - if (IS_ERR(znode)) { - err = PTR_ERR(znode); - goto out_unlock; - } + znode = dirty_cow_bottom_up(c, znode); + if (IS_ERR(znode)) { + err = PTR_ERR(znode); + goto out_unlock; + } } err = tnc_delete(c, znode, n); } @@ -2571,10 +2632,10 @@ int ubifs_tnc_remove_range(struct ubifs_info *c, union ubifs_key *from_key, err = ubifs_add_dirt(c, znode->zbranch[i].lnum, znode->zbranch[i].len); if (err) { - dbg_dump_znode(c, znode); + ubifs_dump_znode(c, znode); goto out_unlock; } - dbg_tnc("removing %s", DBGKEY(key)); + dbg_tnck(key, "removing key "); } if (k) { for (i = n + 1 + k; i < znode->child_cnt; i++) @@ -2633,7 +2694,7 @@ int ubifs_tnc_remove_ino(struct ubifs_info *c, ino_t inum) dbg_tnc("xent '%s', ino %lu", xent->name, (unsigned long)xattr_inum); - nm.name = (char *)xent->name; + nm.name = xent->name; nm.len = le16_to_cpu(xent->nlen); err = ubifs_tnc_remove_nm(c, &key1, &nm); if (err) { @@ -2694,7 +2755,7 @@ struct ubifs_dent_node *ubifs_tnc_next_ent(struct ubifs_info *c, struct ubifs_zbranch *zbr; union ubifs_key *dkey; - dbg_tnc("%s %s", nm->name ? (char *)nm->name : "(lowest)", DBGKEY(key)); + dbg_tnck(key, "%s ", nm->name ? (char *)nm->name : "(lowest)"); ubifs_assert(is_hash_key(c, key)); mutex_lock(&c->tnc_mutex); @@ -2765,3 +2826,503 @@ out_unlock: mutex_unlock(&c->tnc_mutex); return ERR_PTR(err); } + +#ifndef __UBOOT__ +/** + * tnc_destroy_cnext - destroy left-over obsolete znodes from a failed commit. + * @c: UBIFS file-system description object + * + * Destroy left-over obsolete znodes from a failed commit. + */ +static void tnc_destroy_cnext(struct ubifs_info *c) +{ + struct ubifs_znode *cnext; + + if (!c->cnext) + return; + ubifs_assert(c->cmt_state == COMMIT_BROKEN); + cnext = c->cnext; + do { + struct ubifs_znode *znode = cnext; + + cnext = cnext->cnext; + if (ubifs_zn_obsolete(znode)) + kfree(znode); + } while (cnext && cnext != c->cnext); +} + +/** + * ubifs_tnc_close - close TNC subsystem and free all related resources. + * @c: UBIFS file-system description object + */ +void ubifs_tnc_close(struct ubifs_info *c) +{ + tnc_destroy_cnext(c); + if (c->zroot.znode) { + long n; + + ubifs_destroy_tnc_subtree(c->zroot.znode); + n = atomic_long_read(&c->clean_zn_cnt); + atomic_long_sub(n, &ubifs_clean_zn_cnt); + } + kfree(c->gap_lebs); + kfree(c->ilebs); + destroy_old_idx(c); +} +#endif + +/** + * left_znode - get the znode to the left. + * @c: UBIFS file-system description object + * @znode: znode + * + * This function returns a pointer to the znode to the left of @znode or NULL if + * there is not one. A negative error code is returned on failure. + */ +static struct ubifs_znode *left_znode(struct ubifs_info *c, + struct ubifs_znode *znode) +{ + int level = znode->level; + + while (1) { + int n = znode->iip - 1; + + /* Go up until we can go left */ + znode = znode->parent; + if (!znode) + return NULL; + if (n >= 0) { + /* Now go down the rightmost branch to 'level' */ + znode = get_znode(c, znode, n); + if (IS_ERR(znode)) + return znode; + while (znode->level != level) { + n = znode->child_cnt - 1; + znode = get_znode(c, znode, n); + if (IS_ERR(znode)) + return znode; + } + break; + } + } + return znode; +} + +/** + * right_znode - get the znode to the right. + * @c: UBIFS file-system description object + * @znode: znode + * + * This function returns a pointer to the znode to the right of @znode or NULL + * if there is not one. A negative error code is returned on failure. + */ +static struct ubifs_znode *right_znode(struct ubifs_info *c, + struct ubifs_znode *znode) +{ + int level = znode->level; + + while (1) { + int n = znode->iip + 1; + + /* Go up until we can go right */ + znode = znode->parent; + if (!znode) + return NULL; + if (n < znode->child_cnt) { + /* Now go down the leftmost branch to 'level' */ + znode = get_znode(c, znode, n); + if (IS_ERR(znode)) + return znode; + while (znode->level != level) { + znode = get_znode(c, znode, 0); + if (IS_ERR(znode)) + return znode; + } + break; + } + } + return znode; +} + +/** + * lookup_znode - find a particular indexing node from TNC. + * @c: UBIFS file-system description object + * @key: index node key to lookup + * @level: index node level + * @lnum: index node LEB number + * @offs: index node offset + * + * This function searches an indexing node by its first key @key and its + * address @lnum:@offs. It looks up the indexing tree by pulling all indexing + * nodes it traverses to TNC. This function is called for indexing nodes which + * were found on the media by scanning, for example when garbage-collecting or + * when doing in-the-gaps commit. This means that the indexing node which is + * looked for does not have to have exactly the same leftmost key @key, because + * the leftmost key may have been changed, in which case TNC will contain a + * dirty znode which still refers the same @lnum:@offs. This function is clever + * enough to recognize such indexing nodes. + * + * Note, if a znode was deleted or changed too much, then this function will + * not find it. For situations like this UBIFS has the old index RB-tree + * (indexed by @lnum:@offs). + * + * This function returns a pointer to the znode found or %NULL if it is not + * found. A negative error code is returned on failure. + */ +static struct ubifs_znode *lookup_znode(struct ubifs_info *c, + union ubifs_key *key, int level, + int lnum, int offs) +{ + struct ubifs_znode *znode, *zn; + int n, nn; + + ubifs_assert(key_type(c, key) < UBIFS_INVALID_KEY); + + /* + * The arguments have probably been read off flash, so don't assume + * they are valid. + */ + if (level < 0) + return ERR_PTR(-EINVAL); + + /* Get the root znode */ + znode = c->zroot.znode; + if (!znode) { + znode = ubifs_load_znode(c, &c->zroot, NULL, 0); + if (IS_ERR(znode)) + return znode; + } + /* Check if it is the one we are looking for */ + if (c->zroot.lnum == lnum && c->zroot.offs == offs) + return znode; + /* Descend to the parent level i.e. (level + 1) */ + if (level >= znode->level) + return NULL; + while (1) { + ubifs_search_zbranch(c, znode, key, &n); + if (n < 0) { + /* + * We reached a znode where the leftmost key is greater + * than the key we are searching for. This is the same + * situation as the one described in a huge comment at + * the end of the 'ubifs_lookup_level0()' function. And + * for exactly the same reasons we have to try to look + * left before giving up. + */ + znode = left_znode(c, znode); + if (!znode) + return NULL; + if (IS_ERR(znode)) + return znode; + ubifs_search_zbranch(c, znode, key, &n); + ubifs_assert(n >= 0); + } + if (znode->level == level + 1) + break; + znode = get_znode(c, znode, n); + if (IS_ERR(znode)) + return znode; + } + /* Check if the child is the one we are looking for */ + if (znode->zbranch[n].lnum == lnum && znode->zbranch[n].offs == offs) + return get_znode(c, znode, n); + /* If the key is unique, there is nowhere else to look */ + if (!is_hash_key(c, key)) + return NULL; + /* + * The key is not unique and so may be also in the znodes to either + * side. + */ + zn = znode; + nn = n; + /* Look left */ + while (1) { + /* Move one branch to the left */ + if (n) + n -= 1; + else { + znode = left_znode(c, znode); + if (!znode) + break; + if (IS_ERR(znode)) + return znode; + n = znode->child_cnt - 1; + } + /* Check it */ + if (znode->zbranch[n].lnum == lnum && + znode->zbranch[n].offs == offs) + return get_znode(c, znode, n); + /* Stop if the key is less than the one we are looking for */ + if (keys_cmp(c, &znode->zbranch[n].key, key) < 0) + break; + } + /* Back to the middle */ + znode = zn; + n = nn; + /* Look right */ + while (1) { + /* Move one branch to the right */ + if (++n >= znode->child_cnt) { + znode = right_znode(c, znode); + if (!znode) + break; + if (IS_ERR(znode)) + return znode; + n = 0; + } + /* Check it */ + if (znode->zbranch[n].lnum == lnum && + znode->zbranch[n].offs == offs) + return get_znode(c, znode, n); + /* Stop if the key is greater than the one we are looking for */ + if (keys_cmp(c, &znode->zbranch[n].key, key) > 0) + break; + } + return NULL; +} + +/** + * is_idx_node_in_tnc - determine if an index node is in the TNC. + * @c: UBIFS file-system description object + * @key: key of index node + * @level: index node level + * @lnum: LEB number of index node + * @offs: offset of index node + * + * This function returns %0 if the index node is not referred to in the TNC, %1 + * if the index node is referred to in the TNC and the corresponding znode is + * dirty, %2 if an index node is referred to in the TNC and the corresponding + * znode is clean, and a negative error code in case of failure. + * + * Note, the @key argument has to be the key of the first child. Also note, + * this function relies on the fact that 0:0 is never a valid LEB number and + * offset for a main-area node. + */ +int is_idx_node_in_tnc(struct ubifs_info *c, union ubifs_key *key, int level, + int lnum, int offs) +{ + struct ubifs_znode *znode; + + znode = lookup_znode(c, key, level, lnum, offs); + if (!znode) + return 0; + if (IS_ERR(znode)) + return PTR_ERR(znode); + + return ubifs_zn_dirty(znode) ? 1 : 2; +} + +/** + * is_leaf_node_in_tnc - determine if a non-indexing not is in the TNC. + * @c: UBIFS file-system description object + * @key: node key + * @lnum: node LEB number + * @offs: node offset + * + * This function returns %1 if the node is referred to in the TNC, %0 if it is + * not, and a negative error code in case of failure. + * + * Note, this function relies on the fact that 0:0 is never a valid LEB number + * and offset for a main-area node. + */ +static int is_leaf_node_in_tnc(struct ubifs_info *c, union ubifs_key *key, + int lnum, int offs) +{ + struct ubifs_zbranch *zbr; + struct ubifs_znode *znode, *zn; + int n, found, err, nn; + const int unique = !is_hash_key(c, key); + + found = ubifs_lookup_level0(c, key, &znode, &n); + if (found < 0) + return found; /* Error code */ + if (!found) + return 0; + zbr = &znode->zbranch[n]; + if (lnum == zbr->lnum && offs == zbr->offs) + return 1; /* Found it */ + if (unique) + return 0; + /* + * Because the key is not unique, we have to look left + * and right as well + */ + zn = znode; + nn = n; + /* Look left */ + while (1) { + err = tnc_prev(c, &znode, &n); + if (err == -ENOENT) + break; + if (err) + return err; + if (keys_cmp(c, key, &znode->zbranch[n].key)) + break; + zbr = &znode->zbranch[n]; + if (lnum == zbr->lnum && offs == zbr->offs) + return 1; /* Found it */ + } + /* Look right */ + znode = zn; + n = nn; + while (1) { + err = tnc_next(c, &znode, &n); + if (err) { + if (err == -ENOENT) + return 0; + return err; + } + if (keys_cmp(c, key, &znode->zbranch[n].key)) + break; + zbr = &znode->zbranch[n]; + if (lnum == zbr->lnum && offs == zbr->offs) + return 1; /* Found it */ + } + return 0; +} + +/** + * ubifs_tnc_has_node - determine whether a node is in the TNC. + * @c: UBIFS file-system description object + * @key: node key + * @level: index node level (if it is an index node) + * @lnum: node LEB number + * @offs: node offset + * @is_idx: non-zero if the node is an index node + * + * This function returns %1 if the node is in the TNC, %0 if it is not, and a + * negative error code in case of failure. For index nodes, @key has to be the + * key of the first child. An index node is considered to be in the TNC only if + * the corresponding znode is clean or has not been loaded. + */ +int ubifs_tnc_has_node(struct ubifs_info *c, union ubifs_key *key, int level, + int lnum, int offs, int is_idx) +{ + int err; + + mutex_lock(&c->tnc_mutex); + if (is_idx) { + err = is_idx_node_in_tnc(c, key, level, lnum, offs); + if (err < 0) + goto out_unlock; + if (err == 1) + /* The index node was found but it was dirty */ + err = 0; + else if (err == 2) + /* The index node was found and it was clean */ + err = 1; + else + BUG_ON(err != 0); + } else + err = is_leaf_node_in_tnc(c, key, lnum, offs); + +out_unlock: + mutex_unlock(&c->tnc_mutex); + return err; +} + +/** + * ubifs_dirty_idx_node - dirty an index node. + * @c: UBIFS file-system description object + * @key: index node key + * @level: index node level + * @lnum: index node LEB number + * @offs: index node offset + * + * This function loads and dirties an index node so that it can be garbage + * collected. The @key argument has to be the key of the first child. This + * function relies on the fact that 0:0 is never a valid LEB number and offset + * for a main-area node. Returns %0 on success and a negative error code on + * failure. + */ +int ubifs_dirty_idx_node(struct ubifs_info *c, union ubifs_key *key, int level, + int lnum, int offs) +{ + struct ubifs_znode *znode; + int err = 0; + + mutex_lock(&c->tnc_mutex); + znode = lookup_znode(c, key, level, lnum, offs); + if (!znode) + goto out_unlock; + if (IS_ERR(znode)) { + err = PTR_ERR(znode); + goto out_unlock; + } + znode = dirty_cow_bottom_up(c, znode); + if (IS_ERR(znode)) { + err = PTR_ERR(znode); + goto out_unlock; + } + +out_unlock: + mutex_unlock(&c->tnc_mutex); + return err; +} + +/** + * dbg_check_inode_size - check if inode size is correct. + * @c: UBIFS file-system description object + * @inum: inode number + * @size: inode size + * + * This function makes sure that the inode size (@size) is correct and it does + * not have any pages beyond @size. Returns zero if the inode is OK, %-EINVAL + * if it has a data page beyond @size, and other negative error code in case of + * other errors. + */ +int dbg_check_inode_size(struct ubifs_info *c, const struct inode *inode, + loff_t size) +{ + int err, n; + union ubifs_key from_key, to_key, *key; + struct ubifs_znode *znode; + unsigned int block; + + if (!S_ISREG(inode->i_mode)) + return 0; + if (!dbg_is_chk_gen(c)) + return 0; + + block = (size + UBIFS_BLOCK_SIZE - 1) >> UBIFS_BLOCK_SHIFT; + data_key_init(c, &from_key, inode->i_ino, block); + highest_data_key(c, &to_key, inode->i_ino); + + mutex_lock(&c->tnc_mutex); + err = ubifs_lookup_level0(c, &from_key, &znode, &n); + if (err < 0) + goto out_unlock; + + if (err) { + err = -EINVAL; + key = &from_key; + goto out_dump; + } + + err = tnc_next(c, &znode, &n); + if (err == -ENOENT) { + err = 0; + goto out_unlock; + } + if (err < 0) + goto out_unlock; + + ubifs_assert(err == 0); + key = &znode->zbranch[n].key; + if (!key_in_range(c, key, &from_key, &to_key)) + goto out_unlock; + +out_dump: + block = key_block(c, key); + ubifs_err("inode %lu has size %lld, but there are data at offset %lld", + (unsigned long)inode->i_ino, size, + ((loff_t)block) << UBIFS_BLOCK_SHIFT); + mutex_unlock(&c->tnc_mutex); + ubifs_dump_inode(c, inode); + dump_stack(); + return -EINVAL; + +out_unlock: + mutex_unlock(&c->tnc_mutex); + return err; +} diff --git a/fs/ubifs/tnc_misc.c b/fs/ubifs/tnc_misc.c index 955219fa01..f808e0bc2f 100644 --- a/fs/ubifs/tnc_misc.c +++ b/fs/ubifs/tnc_misc.c @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Adrian Hunter * Artem Bityutskiy (Битюцкий Артём) @@ -27,6 +16,9 @@ * putting it all in one file would make that file too big and unreadable. */ +#ifdef __UBOOT__ +#include +#endif #include "ubifs.h" /** @@ -218,6 +210,44 @@ struct ubifs_znode *ubifs_tnc_postorder_next(struct ubifs_znode *znode) return ubifs_tnc_postorder_first(zn); } +/** + * ubifs_destroy_tnc_subtree - destroy all znodes connected to a subtree. + * @znode: znode defining subtree to destroy + * + * This function destroys subtree of the TNC tree. Returns number of clean + * znodes in the subtree. + */ +long ubifs_destroy_tnc_subtree(struct ubifs_znode *znode) +{ + struct ubifs_znode *zn = ubifs_tnc_postorder_first(znode); + long clean_freed = 0; + int n; + + ubifs_assert(zn); + while (1) { + for (n = 0; n < zn->child_cnt; n++) { + if (!zn->zbranch[n].znode) + continue; + + if (zn->level > 0 && + !ubifs_zn_dirty(zn->zbranch[n].znode)) + clean_freed += 1; + + cond_resched(); + kfree(zn->zbranch[n].znode); + } + + if (zn == znode) { + if (!ubifs_zn_dirty(zn)) + clean_freed += 1; + kfree(zn); + return clean_freed; + } + + zn = ubifs_tnc_postorder_next(zn); + } +} + /** * read_znode - read an indexing node from flash and fill znode. * @c: UBIFS file-system description object @@ -255,10 +285,10 @@ static int read_znode(struct ubifs_info *c, int lnum, int offs, int len, lnum, offs, znode->level, znode->child_cnt); if (znode->child_cnt > c->fanout || znode->level > UBIFS_MAX_LEVELS) { - dbg_err("current fanout %d, branch count %d", - c->fanout, znode->child_cnt); - dbg_err("max levels %d, znode level %d", - UBIFS_MAX_LEVELS, znode->level); + ubifs_err("current fanout %d, branch count %d", + c->fanout, znode->child_cnt); + ubifs_err("max levels %d, znode level %d", + UBIFS_MAX_LEVELS, znode->level); err = 1; goto out_dump; } @@ -278,7 +308,7 @@ static int read_znode(struct ubifs_info *c, int lnum, int offs, int len, if (zbr->lnum < c->main_first || zbr->lnum >= c->leb_cnt || zbr->offs < 0 || zbr->offs + zbr->len > c->leb_size || zbr->offs & 7) { - dbg_err("bad branch %d", i); + ubifs_err("bad branch %d", i); err = 2; goto out_dump; } @@ -290,8 +320,8 @@ static int read_znode(struct ubifs_info *c, int lnum, int offs, int len, case UBIFS_XENT_KEY: break; default: - dbg_msg("bad key type at slot %d: %s", i, - DBGKEY(&zbr->key)); + ubifs_err("bad key type at slot %d: %d", + i, key_type(c, &zbr->key)); err = 3; goto out_dump; } @@ -302,19 +332,19 @@ static int read_znode(struct ubifs_info *c, int lnum, int offs, int len, type = key_type(c, &zbr->key); if (c->ranges[type].max_len == 0) { if (zbr->len != c->ranges[type].len) { - dbg_err("bad target node (type %d) length (%d)", - type, zbr->len); - dbg_err("have to be %d", c->ranges[type].len); + ubifs_err("bad target node (type %d) length (%d)", + type, zbr->len); + ubifs_err("have to be %d", c->ranges[type].len); err = 4; goto out_dump; } } else if (zbr->len < c->ranges[type].min_len || zbr->len > c->ranges[type].max_len) { - dbg_err("bad target node (type %d) length (%d)", - type, zbr->len); - dbg_err("have to be in range of %d-%d", - c->ranges[type].min_len, - c->ranges[type].max_len); + ubifs_err("bad target node (type %d) length (%d)", + type, zbr->len); + ubifs_err("have to be in range of %d-%d", + c->ranges[type].min_len, + c->ranges[type].max_len); err = 5; goto out_dump; } @@ -332,13 +362,13 @@ static int read_znode(struct ubifs_info *c, int lnum, int offs, int len, cmp = keys_cmp(c, key1, key2); if (cmp > 0) { - dbg_err("bad key order (keys %d and %d)", i, i + 1); + ubifs_err("bad key order (keys %d and %d)", i, i + 1); err = 6; goto out_dump; } else if (cmp == 0 && !is_hash_key(c, key1)) { /* These can only be keys with colliding hash */ - dbg_err("keys %d and %d are not hashed but equivalent", - i, i + 1); + ubifs_err("keys %d and %d are not hashed but equivalent", + i, i + 1); err = 7; goto out_dump; } @@ -349,7 +379,7 @@ static int read_znode(struct ubifs_info *c, int lnum, int offs, int len, out_dump: ubifs_err("bad indexing node at LEB %d:%d, error %d", lnum, offs, err); - dbg_dump_node(c, idx); + ubifs_dump_node(c, idx); kfree(idx); return -EINVAL; } @@ -385,6 +415,16 @@ struct ubifs_znode *ubifs_load_znode(struct ubifs_info *c, if (err) goto out; + atomic_long_inc(&c->clean_zn_cnt); + + /* + * Increment the global clean znode counter as well. It is OK that + * global and per-FS clean znode counters may be inconsistent for some + * short time (because we might be preempted at this point), the global + * one is only used in shrinker. + */ + atomic_long_inc(&ubifs_clean_zn_cnt); + zbr->znode = znode; znode->parent = parent; znode->time = get_seconds(); @@ -412,11 +452,22 @@ int ubifs_tnc_read_node(struct ubifs_info *c, struct ubifs_zbranch *zbr, { union ubifs_key key1, *key = &zbr->key; int err, type = key_type(c, key); + struct ubifs_wbuf *wbuf; - err = ubifs_read_node(c, node, type, zbr->len, zbr->lnum, zbr->offs); + /* + * 'zbr' has to point to on-flash node. The node may sit in a bud and + * may even be in a write buffer, so we have to take care about this. + */ + wbuf = ubifs_get_wbuf(c, zbr->lnum); + if (wbuf) + err = ubifs_read_node_wbuf(wbuf, node, type, zbr->len, + zbr->lnum, zbr->offs); + else + err = ubifs_read_node(c, node, type, zbr->len, zbr->lnum, + zbr->offs); if (err) { - dbg_tnc("key %s", DBGKEY(key)); + dbg_tnck(key, "key "); return err; } @@ -425,9 +476,9 @@ int ubifs_tnc_read_node(struct ubifs_info *c, struct ubifs_zbranch *zbr, if (!keys_eq(c, key, &key1)) { ubifs_err("bad key in node at LEB %d:%d", zbr->lnum, zbr->offs); - dbg_tnc("looked for key %s found node's key %s", - DBGKEY(key), DBGKEY1(&key1)); - dbg_dump_node(c, node); + dbg_tnck(key, "looked for key "); + dbg_tnck(&key1, "but found node's key "); + ubifs_dump_node(c, node); return -EINVAL; } diff --git a/fs/ubifs/ubifs-media.h b/fs/ubifs/ubifs-media.h index 3eee07e0c4..90b8ffacfb 100644 --- a/fs/ubifs/ubifs-media.h +++ b/fs/ubifs/ubifs-media.h @@ -3,18 +3,7 @@ * * Copyright (C) 2006-2008 Nokia Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -135,6 +124,13 @@ /* The key is always at the same position in all keyed nodes */ #define UBIFS_KEY_OFFSET offsetof(struct ubifs_ino_node, key) +/* Garbage collector journal head number */ +#define UBIFS_GC_HEAD 0 +/* Base journal head number */ +#define UBIFS_BASE_HEAD 1 +/* Data journal head number */ +#define UBIFS_DATA_HEAD 2 + /* * LEB Properties Tree node types. * @@ -401,9 +397,11 @@ enum { * Superblock flags. * * UBIFS_FLG_BIGLPT: if "big" LPT model is used if set + * UBIFS_FLG_SPACE_FIXUP: first-mount "fixup" of free space within LEBs needed */ enum { UBIFS_FLG_BIGLPT = 0x02, + UBIFS_FLG_SPACE_FIXUP = 0x04, }; /** @@ -427,7 +425,7 @@ struct ubifs_ch { __u8 node_type; __u8 group_type; __u8 padding[2]; -} __attribute__ ((packed)); +} __packed; /** * union ubifs_dev_desc - device node descriptor. @@ -441,7 +439,7 @@ struct ubifs_ch { union ubifs_dev_desc { __le32 new; __le64 huge; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_ino_node - inode node. @@ -502,7 +500,7 @@ struct ubifs_ino_node { __le16 compr_type; __u8 padding2[26]; /* Watch 'zero_ino_node_unused()' if changing! */ __u8 data[]; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_dent_node - directory entry node. @@ -526,8 +524,12 @@ struct ubifs_dent_node { __u8 type; __le16 nlen; __u8 padding2[4]; /* Watch 'zero_dent_node_unused()' if changing! */ +#ifndef __UBOOT__ __u8 name[]; -} __attribute__ ((packed)); +#else + char name[]; +#endif +} __packed; /** * struct ubifs_data_node - data node. @@ -548,7 +550,7 @@ struct ubifs_data_node { __le16 compr_type; __u8 padding[2]; /* Watch 'zero_data_node_unused()' if changing! */ __u8 data[]; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_trun_node - truncation node. @@ -568,7 +570,7 @@ struct ubifs_trun_node { __u8 padding[12]; /* Watch 'zero_trun_node_unused()' if changing! */ __le64 old_size; __le64 new_size; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_pad_node - padding node. @@ -579,7 +581,7 @@ struct ubifs_trun_node { struct ubifs_pad_node { struct ubifs_ch ch; __le32 pad_len; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_sb_node - superblock node. @@ -637,7 +639,7 @@ struct ubifs_sb_node { __u8 uuid[16]; __le32 ro_compat_version; __u8 padding2[3968]; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_mst_node - master node. @@ -704,7 +706,7 @@ struct ubifs_mst_node { __le32 idx_lebs; __le32 leb_cnt; __u8 padding[344]; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_ref_node - logical eraseblock reference node. @@ -720,7 +722,7 @@ struct ubifs_ref_node { __le32 offs; __le32 jhead; __u8 padding[28]; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_branch - key/reference/length branch @@ -733,8 +735,12 @@ struct ubifs_branch { __le32 lnum; __le32 offs; __le32 len; +#ifndef __UBOOT__ __u8 key[]; -} __attribute__ ((packed)); +#else + char key[]; +#endif +} __packed; /** * struct ubifs_idx_node - indexing node. @@ -747,8 +753,12 @@ struct ubifs_idx_node { struct ubifs_ch ch; __le16 child_cnt; __le16 level; +#ifndef __UBOOT__ __u8 branches[]; -} __attribute__ ((packed)); +#else + char branches[]; +#endif +} __packed; /** * struct ubifs_cs_node - commit start node. @@ -758,7 +768,7 @@ struct ubifs_idx_node { struct ubifs_cs_node { struct ubifs_ch ch; __le64 cmt_no; -} __attribute__ ((packed)); +} __packed; /** * struct ubifs_orph_node - orphan node. @@ -770,6 +780,6 @@ struct ubifs_orph_node { struct ubifs_ch ch; __le64 cmt_no; __le64 inos[]; -} __attribute__ ((packed)); +} __packed; #endif /* __UBIFS_MEDIA_H__ */ diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 273c0a9638..49e6f469ca 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -26,6 +26,9 @@ #include "ubifs.h" #include +#include +#include + DECLARE_GLOBAL_DATA_PTR; /* compress.c */ @@ -44,20 +47,27 @@ static int gzip_decompress(const unsigned char *in, size_t in_len, /* Fake description object for the "none" compressor */ static struct ubifs_compressor none_compr = { .compr_type = UBIFS_COMPR_NONE, - .name = "no compression", + .name = "none", .capi_name = "", .decompress = NULL, }; static struct ubifs_compressor lzo_compr = { .compr_type = UBIFS_COMPR_LZO, - .name = "LZO", +#ifndef __UBOOT__ + .comp_mutex = &lzo_mutex, +#endif + .name = "lzo", .capi_name = "lzo", .decompress = lzo1x_decompress_safe, }; static struct ubifs_compressor zlib_compr = { .compr_type = UBIFS_COMPR_ZLIB, +#ifndef __UBOOT__ + .comp_mutex = &deflate_mutex, + .decomp_mutex = &inflate_mutex, +#endif .name = "zlib", .capi_name = "deflate", .decompress = gzip_decompress, @@ -66,6 +76,82 @@ static struct ubifs_compressor zlib_compr = { /* All UBIFS compressors */ struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT]; + +#ifdef __UBOOT__ +/* from mm/util.c */ + +/** + * kmemdup - duplicate region of memory + * + * @src: memory region to duplicate + * @len: memory region length + * @gfp: GFP mask to use + */ +void *kmemdup(const void *src, size_t len, gfp_t gfp) +{ + void *p; + + p = kmalloc(len, gfp); + if (p) + memcpy(p, src, len); + return p; +} + +struct crypto_comp { + int compressor; +}; + +static inline struct crypto_comp *crypto_alloc_comp(const char *alg_name, + u32 type, u32 mask) +{ + struct ubifs_compressor *comp; + struct crypto_comp *ptr; + int i = 0; + + ptr = malloc(sizeof(struct crypto_comp)); + while (i < UBIFS_COMPR_TYPES_CNT) { + comp = ubifs_compressors[i]; + if (!comp) { + i++; + continue; + } + if (strncmp(alg_name, comp->capi_name, strlen(alg_name)) == 0) { + ptr->compressor = i; + return ptr; + } + i++; + } + if (i >= UBIFS_COMPR_TYPES_CNT) { + ubifs_err("invalid compression type %s", alg_name); + free (ptr); + return NULL; + } + return ptr; +} +static inline int crypto_comp_decompress(struct crypto_comp *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen) +{ + struct ubifs_compressor *compr = ubifs_compressors[tfm->compressor]; + int err; + + if (compr->compr_type == UBIFS_COMPR_NONE) { + memcpy(dst, src, slen); + *dlen = slen; + return 0; + } + + err = compr->decompress(src, slen, dst, (size_t *)dlen); + if (err) + ubifs_err("cannot decompress %d bytes, compressor %s, " + "error %d", slen, compr->name, err); + + return err; + + return 0; +} +#endif + /** * ubifs_decompress - decompress data. * @in_buf: data to decompress @@ -102,10 +188,15 @@ int ubifs_decompress(const void *in_buf, int in_len, void *out_buf, return 0; } - err = compr->decompress(in_buf, in_len, out_buf, (size_t *)out_len); + if (compr->decomp_mutex) + mutex_lock(compr->decomp_mutex); + err = crypto_comp_decompress(compr->cc, in_buf, in_len, out_buf, + (unsigned int *)out_len); + if (compr->decomp_mutex) + mutex_unlock(compr->decomp_mutex); if (err) - ubifs_err("cannot decompress %d bytes, compressor %s, " - "error %d", in_len, compr->name, err); + ubifs_err("cannot decompress %d bytes, compressor %s, error %d", + in_len, compr->name, err); return err; } @@ -127,6 +218,15 @@ static int __init compr_init(struct ubifs_compressor *compr) ubifs_compressors[compr->compr_type]->decompress += gd->reloc_off; #endif + if (compr->capi_name) { + compr->cc = crypto_alloc_comp(compr->capi_name, 0, 0); + if (IS_ERR(compr->cc)) { + ubifs_err("cannot initialize compressor %s, error %ld", + compr->name, PTR_ERR(compr->cc)); + return PTR_ERR(compr->cc); + } + } + return 0; } @@ -188,7 +288,9 @@ static int filldir(struct ubifs_info *c, const char *name, int namlen, } ctime_r((time_t *)&inode->i_mtime, filetime); printf("%9lld %24.24s ", inode->i_size, filetime); +#ifndef __UBOOT__ ubifs_iput(inode); +#endif printf("%s\n", name); @@ -562,7 +664,7 @@ static int read_block(struct inode *inode, void *addr, unsigned int block, dump: ubifs_err("bad data node (block %u, inode %lu)", block, inode->i_ino); - dbg_dump_node(c, dn); + ubifs_dump_node(c, dn); return -EINVAL; } diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 633631e4d4..c12026147f 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -6,18 +6,7 @@ * (C) Copyright 2008-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ * * Authors: Artem Bityutskiy (Битюцкий Артём) * Adrian Hunter @@ -26,12 +15,24 @@ #ifndef __UBIFS_H__ #define __UBIFS_H__ -#if 0 /* Enable for debugging output */ -#define CONFIG_UBIFS_FS_DEBUG -#define CONFIG_UBIFS_FS_DEBUG_MSG_LVL 3 -#endif - +#ifndef __UBOOT__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ubifs-media.h" +#else #include + #include #include #include @@ -70,13 +71,26 @@ void iput(struct inode *inode); #define atomic_long_dec(a) #define atomic_long_sub(a, b) +typedef unsigned long atomic_long_t; + /* linux/include/time.h */ +#define NSEC_PER_SEC 1000000000L +#define get_seconds() 0 +#define CURRENT_TIME_SEC ((struct timespec) { get_seconds(), 0 }) struct timespec { time_t tv_sec; /* seconds */ long tv_nsec; /* nanoseconds */ }; +static struct timespec current_fs_time(struct super_block *sb) +{ + struct timespec now; + now.tv_sec = 0; + now.tv_nsec = 0; + return now; +}; + /* linux/include/dcache.h */ /* @@ -89,111 +103,245 @@ struct timespec { struct qstr { unsigned int hash; unsigned int len; +#ifndef __UBOOT__ const char *name; +#else + char *name; +#endif +}; + +/* include/linux/fs.h */ + +/* Possible states of 'frozen' field */ +enum { + SB_UNFROZEN = 0, /* FS is unfrozen */ + SB_FREEZE_WRITE = 1, /* Writes, dir ops, ioctls frozen */ + SB_FREEZE_PAGEFAULT = 2, /* Page faults stopped as well */ + SB_FREEZE_FS = 3, /* For internal FS use (e.g. to stop + * internal threads if needed) */ + SB_FREEZE_COMPLETE = 4, /* ->freeze_fs finished successfully */ +}; + +#define SB_FREEZE_LEVELS (SB_FREEZE_COMPLETE - 1) + +struct sb_writers { +#ifndef __UBOOT__ + /* Counters for counting writers at each level */ + struct percpu_counter counter[SB_FREEZE_LEVELS]; +#endif + wait_queue_head_t wait; /* queue for waiting for + writers / faults to finish */ + int frozen; /* Is sb frozen? */ + wait_queue_head_t wait_unfrozen; /* queue for waiting for + sb to be thawed */ +#ifdef CONFIG_DEBUG_LOCK_ALLOC + struct lockdep_map lock_map[SB_FREEZE_LEVELS]; +#endif }; +struct address_space { + struct inode *host; /* owner: inode, block_device */ +#ifndef __UBOOT__ + struct radix_tree_root page_tree; /* radix tree of all pages */ +#endif + spinlock_t tree_lock; /* and lock protecting it */ + unsigned int i_mmap_writable;/* count VM_SHARED mappings */ + struct rb_root i_mmap; /* tree of private and shared mappings */ + struct list_head i_mmap_nonlinear;/*list VM_NONLINEAR mappings */ + struct mutex i_mmap_mutex; /* protect tree, count, list */ + /* Protected by tree_lock together with the radix tree */ + unsigned long nrpages; /* number of total pages */ + pgoff_t writeback_index;/* writeback starts here */ + const struct address_space_operations *a_ops; /* methods */ + unsigned long flags; /* error bits/gfp mask */ +#ifndef __UBOOT__ + struct backing_dev_info *backing_dev_info; /* device readahead, etc */ +#endif + spinlock_t private_lock; /* for use by the address_space */ + struct list_head private_list; /* ditto */ + void *private_data; /* ditto */ +} __attribute__((aligned(sizeof(long)))); + +/* + * Keep mostly read-only and often accessed (especially for + * the RCU path lookup and 'stat' data) fields at the beginning + * of the 'struct inode' + */ struct inode { - struct hlist_node i_hash; - struct list_head i_list; - struct list_head i_sb_list; - struct list_head i_dentry; + umode_t i_mode; + unsigned short i_opflags; + kuid_t i_uid; + kgid_t i_gid; + unsigned int i_flags; + +#ifdef CONFIG_FS_POSIX_ACL + struct posix_acl *i_acl; + struct posix_acl *i_default_acl; +#endif + + const struct inode_operations *i_op; + struct super_block *i_sb; + struct address_space *i_mapping; + +#ifdef CONFIG_SECURITY + void *i_security; +#endif + + /* Stat data, not accessed from path walking */ unsigned long i_ino; - unsigned int i_nlink; - uid_t i_uid; - gid_t i_gid; + /* + * Filesystems may only read i_nlink directly. They shall use the + * following functions for modification: + * + * (set|clear|inc|drop)_nlink + * inode_(inc|dec)_link_count + */ + union { + const unsigned int i_nlink; + unsigned int __i_nlink; + }; dev_t i_rdev; - u64 i_version; loff_t i_size; -#ifdef __NEED_I_SIZE_ORDERED - seqcount_t i_size_seqcount; -#endif struct timespec i_atime; struct timespec i_mtime; struct timespec i_ctime; - unsigned int i_blkbits; - unsigned short i_bytes; - umode_t i_mode; spinlock_t i_lock; /* i_blocks, i_bytes, maybe i_size */ + unsigned short i_bytes; + unsigned int i_blkbits; + blkcnt_t i_blocks; + +#ifdef __NEED_I_SIZE_ORDERED + seqcount_t i_size_seqcount; +#endif + + /* Misc */ + unsigned long i_state; struct mutex i_mutex; - struct rw_semaphore i_alloc_sem; - const struct inode_operations *i_op; + + unsigned long dirtied_when; /* jiffies of first dirtying */ + + struct hlist_node i_hash; + struct list_head i_wb_list; /* backing dev IO list */ + struct list_head i_lru; /* inode LRU list */ + struct list_head i_sb_list; + union { + struct hlist_head i_dentry; + struct rcu_head i_rcu; + }; + u64 i_version; + atomic_t i_count; + atomic_t i_dio_count; + atomic_t i_writecount; const struct file_operations *i_fop; /* former ->i_op->default_file_ops */ - struct super_block *i_sb; struct file_lock *i_flock; + struct address_space i_data; #ifdef CONFIG_QUOTA struct dquot *i_dquot[MAXQUOTAS]; #endif struct list_head i_devices; - int i_cindex; + union { + struct pipe_inode_info *i_pipe; + struct block_device *i_bdev; + struct cdev *i_cdev; + }; __u32 i_generation; -#ifdef CONFIG_DNOTIFY - unsigned long i_dnotify_mask; /* Directory notify events */ - struct dnotify_struct *i_dnotify; /* for directory notifications */ +#ifdef CONFIG_FSNOTIFY + __u32 i_fsnotify_mask; /* all events this inode cares about */ + struct hlist_head i_fsnotify_marks; #endif -#ifdef CONFIG_INOTIFY - struct list_head inotify_watches; /* watches on this inode */ - struct mutex inotify_mutex; /* protects the watches list */ +#ifdef CONFIG_IMA + atomic_t i_readcount; /* struct files open RO */ #endif + void *i_private; /* fs or device private pointer */ +}; - unsigned long i_state; - unsigned long dirtied_when; /* jiffies of first dirtying */ - - unsigned int i_flags; - -#ifdef CONFIG_SECURITY - void *i_security; +struct super_operations { + struct inode *(*alloc_inode)(struct super_block *sb); + void (*destroy_inode)(struct inode *); + + void (*dirty_inode) (struct inode *, int flags); + int (*write_inode) (struct inode *, struct writeback_control *wbc); + int (*drop_inode) (struct inode *); + void (*evict_inode) (struct inode *); + void (*put_super) (struct super_block *); + int (*sync_fs)(struct super_block *sb, int wait); + int (*freeze_fs) (struct super_block *); + int (*unfreeze_fs) (struct super_block *); +#ifndef __UBOOT__ + int (*statfs) (struct dentry *, struct kstatfs *); #endif - void *i_private; /* fs or device private pointer */ + int (*remount_fs) (struct super_block *, int *, char *); + void (*umount_begin) (struct super_block *); + +#ifndef __UBOOT__ + int (*show_options)(struct seq_file *, struct dentry *); + int (*show_devname)(struct seq_file *, struct dentry *); + int (*show_path)(struct seq_file *, struct dentry *); + int (*show_stats)(struct seq_file *, struct dentry *); +#endif +#ifdef CONFIG_QUOTA + ssize_t (*quota_read)(struct super_block *, int, char *, size_t, loff_t); + ssize_t (*quota_write)(struct super_block *, int, const char *, size_t, loff_t); +#endif + int (*bdev_try_to_free_page)(struct super_block*, struct page*, gfp_t); + long (*nr_cached_objects)(struct super_block *, int); + long (*free_cached_objects)(struct super_block *, long, int); }; struct super_block { struct list_head s_list; /* Keep this first */ dev_t s_dev; /* search index; _not_ kdev_t */ - unsigned long s_blocksize; unsigned char s_blocksize_bits; - unsigned char s_dirt; - unsigned long long s_maxbytes; /* Max file size */ + unsigned long s_blocksize; + loff_t s_maxbytes; /* Max file size */ struct file_system_type *s_type; const struct super_operations *s_op; - struct dquot_operations *dq_op; - struct quotactl_ops *s_qcop; + const struct dquot_operations *dq_op; + const struct quotactl_ops *s_qcop; const struct export_operations *s_export_op; unsigned long s_flags; unsigned long s_magic; struct dentry *s_root; struct rw_semaphore s_umount; - struct mutex s_lock; int s_count; - int s_syncing; - int s_need_sync_fs; + atomic_t s_active; #ifdef CONFIG_SECURITY void *s_security; #endif - struct xattr_handler **s_xattr; + const struct xattr_handler **s_xattr; struct list_head s_inodes; /* all inodes */ - struct list_head s_dirty; /* dirty inodes */ - struct list_head s_io; /* parked for writeback */ - struct list_head s_more_io; /* parked for more writeback */ - struct hlist_head s_anon; /* anonymous dentries for (nfs) exporting */ - struct list_head s_files; - /* s_dentry_lru and s_nr_dentry_unused are protected by dcache_lock */ - struct list_head s_dentry_lru; /* unused dentry lru */ - int s_nr_dentry_unused; /* # of dentry on lru */ - +#ifndef __UBOOT__ + struct hlist_bl_head s_anon; /* anonymous dentries for (nfs) exporting */ +#endif + struct list_head s_mounts; /* list of mounts; _not_ for fs use */ struct block_device *s_bdev; +#ifndef __UBOOT__ + struct backing_dev_info *s_bdi; +#endif struct mtd_info *s_mtd; - struct list_head s_instances; + struct hlist_node s_instances; +#ifndef __UBOOT__ + struct quota_info s_dquot; /* Diskquota specific options */ +#endif - int s_frozen; - wait_queue_head_t s_wait_unfrozen; + struct sb_writers s_writers; char s_id[32]; /* Informational name */ + u8 s_uuid[16]; /* UUID */ void *s_fs_info; /* Filesystem private info */ + unsigned int s_max_links; +#ifndef __UBOOT__ + fmode_t s_mode; +#endif + + /* Granularity of c/m/atime in ns. + Cannot be worse than a second */ + u32 s_time_gran; /* * The next field is for VFS *only*. No filesystems have any business @@ -201,66 +349,83 @@ struct super_block { */ struct mutex s_vfs_rename_mutex; /* Kludge */ - /* Granularity of c/m/atime in ns. - Cannot be worse than a second */ - u32 s_time_gran; - /* * Filesystem subtype. If non-empty the filesystem type field * in /proc/mounts will be "type.subtype" */ char *s_subtype; +#ifndef __UBOOT__ /* * Saved mount options for lazy filesystems using * generic_show_options() */ - char *s_options; + char __rcu *s_options; +#endif + const struct dentry_operations *s_d_op; /* default d_op for dentries */ + + /* + * Saved pool identifier for cleancache (-1 means none) + */ + int cleancache_poolid; + +#ifndef __UBOOT__ + struct shrinker s_shrink; /* per-sb shrinker handle */ +#endif + + /* Number of inodes with nlink == 0 but still referenced */ + atomic_long_t s_remove_count; + + /* Being remounted read-only */ + int s_readonly_remount; + + /* AIO completions deferred from interrupt context */ + struct workqueue_struct *s_dio_done_wq; + +#ifndef __UBOOT__ + /* + * Keep the lru lists last in the structure so they always sit on their + * own individual cachelines. + */ + struct list_lru s_dentry_lru ____cacheline_aligned_in_smp; + struct list_lru s_inode_lru ____cacheline_aligned_in_smp; +#endif + struct rcu_head rcu; }; struct file_system_type { const char *name; int fs_flags; - int (*get_sb) (struct file_system_type *, int, - const char *, void *, struct vfsmount *); +#define FS_REQUIRES_DEV 1 +#define FS_BINARY_MOUNTDATA 2 +#define FS_HAS_SUBTYPE 4 +#define FS_USERNS_MOUNT 8 /* Can be mounted by userns root */ +#define FS_USERNS_DEV_MOUNT 16 /* A userns mount does not imply MNT_NODEV */ +#define FS_RENAME_DOES_D_MOVE 32768 /* FS will handle d_move() during rename() internally. */ + struct dentry *(*mount) (struct file_system_type *, int, + const char *, void *); void (*kill_sb) (struct super_block *); struct module *owner; struct file_system_type * next; - struct list_head fs_supers; + struct hlist_head fs_supers; + +#ifndef __UBOOT__ + struct lock_class_key s_lock_key; + struct lock_class_key s_umount_key; + struct lock_class_key s_vfs_rename_key; + struct lock_class_key s_writers_key[SB_FREEZE_LEVELS]; + + struct lock_class_key i_lock_key; + struct lock_class_key i_mutex_key; + struct lock_class_key i_mutex_dir_key; +#endif }; +/* include/linux/mount.h */ struct vfsmount { - struct list_head mnt_hash; - struct vfsmount *mnt_parent; /* fs we are mounted on */ - struct dentry *mnt_mountpoint; /* dentry of mountpoint */ struct dentry *mnt_root; /* root of the mounted tree */ struct super_block *mnt_sb; /* pointer to superblock */ - struct list_head mnt_mounts; /* list of children, anchored here */ - struct list_head mnt_child; /* and going through their mnt_child */ int mnt_flags; - /* 4 bytes hole on 64bits arches */ - const char *mnt_devname; /* Name of device e.g. /dev/dsk/hda1 */ - struct list_head mnt_list; - struct list_head mnt_expire; /* link in fs-specific expiry list */ - struct list_head mnt_share; /* circular list of shared mounts */ - struct list_head mnt_slave_list;/* list of slave mounts */ - struct list_head mnt_slave; /* slave list entry */ - struct vfsmount *mnt_master; /* slave is on master->mnt_slave_list */ - struct mnt_namespace *mnt_ns; /* containing namespace */ - int mnt_id; /* mount identifier */ - int mnt_group_id; /* peer group identifier */ - /* - * We put mnt_count & mnt_expiry_mark at the end of struct vfsmount - * to let these frequently modified fields in a separate cache line - * (so that reads of mnt_flags wont ping-pong on SMP machines) - */ - int mnt_expiry_mark; /* true if marked for expiry */ - int mnt_pinned; - int mnt_ghosts; - /* - * This value is not stable unless all of the mnt_writers[] spinlocks - * are held, and all mnt_writer[]s on this mount have 0 as their ->count - */ }; struct path { @@ -311,10 +476,6 @@ struct file { #define MAX_LFS_FILESIZE 0x7fffffffffffffffUL #endif -#define INT_MAX ((int)(~0U>>1)) -#define INT_MIN (-INT_MAX - 1) -#define LLONG_MAX ((long long)(~0ULL>>1)) - /* * These are the fs-independent mount-flags: up to 32 flags are supported */ @@ -451,32 +612,35 @@ static inline ino_t parent_ino(struct dentry *dentry) /* debug.c */ -#define DEFINE_SPINLOCK(...) #define module_param_named(...) /* misc.h */ #define mutex_lock_nested(...) #define mutex_unlock_nested(...) #define mutex_is_locked(...) 0 +#endif /* Version of this UBIFS implementation */ #define UBIFS_VERSION 1 /* Normal UBIFS messages */ -#ifdef CONFIG_UBIFS_SILENCE_MSG -#define ubifs_msg(fmt, ...) -#else -#define ubifs_msg(fmt, ...) \ - printk(KERN_NOTICE "UBIFS: " fmt "\n", ##__VA_ARGS__) -#endif +#define ubifs_msg(fmt, ...) pr_notice("UBIFS: " fmt "\n", ##__VA_ARGS__) /* UBIFS error messages */ -#define ubifs_err(fmt, ...) \ - printk(KERN_ERR "UBIFS error (pid %d): %s: " fmt "\n", 0, \ +#ifndef __UBOOT__ +#define ubifs_err(fmt, ...) \ + pr_err("UBIFS error (pid %d): %s: " fmt "\n", current->pid, \ __func__, ##__VA_ARGS__) /* UBIFS warning messages */ -#define ubifs_warn(fmt, ...) \ - printk(KERN_WARNING "UBIFS warning (pid %d): %s: " fmt "\n", \ - 0, __func__, ##__VA_ARGS__) +#define ubifs_warn(fmt, ...) \ + pr_warn("UBIFS warning (pid %d): %s: " fmt "\n", \ + current->pid, __func__, ##__VA_ARGS__) +#else +#define ubifs_err(fmt, ...) \ + pr_err("UBIFS error: %s: " fmt "\n", __func__, ##__VA_ARGS__) +/* UBIFS warning messages */ +#define ubifs_warn(fmt, ...) \ + pr_warn("UBIFS warning: %s: " fmt "\n", __func__, ##__VA_ARGS__) +#endif /* UBIFS file system VFS magic number */ #define UBIFS_SUPER_MAGIC 0x24051905 @@ -509,9 +673,6 @@ static inline ino_t parent_ino(struct dentry *dentry) #define INUM_WARN_WATERMARK 0xFFF00000 #define INUM_WATERMARK 0xFFFFFF00 -/* Largest key size supported in this implementation */ -#define CUR_MAX_KEY_LEN UBIFS_SK_LEN - /* Maximum number of entries in each LPT (LEB category) heap */ #define LPT_HEAP_SZ 256 @@ -521,8 +682,9 @@ static inline ino_t parent_ino(struct dentry *dentry) */ #define BGT_NAME_PATTERN "ubifs_bgt%d_%d" -/* Default write-buffer synchronization timeout (5 secs) */ -#define DEFAULT_WBUF_TIMEOUT (5 * HZ) +/* Write-buffer synchronization timeout interval in seconds */ +#define WBUF_TIMEOUT_SOFTLIMIT 3 +#define WBUF_TIMEOUT_HARDLIMIT 5 /* Maximum possible inode number (only 32-bit inodes are supported now) */ #define MAX_INUM 0xFFFFFFFF @@ -530,12 +692,10 @@ static inline ino_t parent_ino(struct dentry *dentry) /* Number of non-data journal heads */ #define NONDATA_JHEADS_CNT 2 -/* Garbage collector head */ -#define GCHD 0 -/* Base journal head number */ -#define BASEHD 1 -/* First "general purpose" journal head */ -#define DATAHD 2 +/* Shorter names for journal head numbers for internal usage */ +#define GCHD UBIFS_GC_HEAD +#define BASEHD UBIFS_BASE_HEAD +#define DATAHD UBIFS_DATA_HEAD /* 'No change' value for 'ubifs_change_lp()' */ #define LPROPS_NC 0x80000001 @@ -545,8 +705,12 @@ static inline ino_t parent_ino(struct dentry *dentry) * in TNC. However, when replaying, it is handy to introduce fake "truncation" * keys for truncation nodes because the code becomes simpler. So we define * %UBIFS_TRUN_KEY type. + * + * But otherwise, out of the journal reply scope, the truncation keys are + * invalid. */ -#define UBIFS_TRUN_KEY UBIFS_KEY_TYPES_CNT +#define UBIFS_TRUN_KEY UBIFS_KEY_TYPES_CNT +#define UBIFS_INVALID_KEY UBIFS_KEY_TYPES_CNT /* * How much a directory entry/extended attribute entry adds to the parent/host @@ -573,6 +737,12 @@ static inline ino_t parent_ino(struct dentry *dentry) */ #define WORST_COMPR_FACTOR 2 +/* + * How much memory is needed for a buffer where we comress a data node. + */ +#define COMPRESSED_DATA_NODE_BUF_SZ \ + (UBIFS_DATA_NODE_SZ + UBIFS_BLOCK_SIZE * WORST_COMPR_FACTOR) + /* Maximum expected tree height for use by bottom_up_buf */ #define BOTTOM_UP_HEIGHT 64 @@ -646,14 +816,14 @@ enum { * LPT cnode flag bits. * * DIRTY_CNODE: cnode is dirty - * COW_CNODE: cnode is being committed and must be copied before writing * OBSOLETE_CNODE: cnode is being committed and has been copied (or deleted), - * so it can (and must) be freed when the commit is finished + * so it can (and must) be freed when the commit is finished + * COW_CNODE: cnode is being committed and must be copied before writing */ enum { DIRTY_CNODE = 0, - COW_CNODE = 1, - OBSOLETE_CNODE = 2, + OBSOLETE_CNODE = 1, + COW_CNODE = 2, }; /* @@ -693,10 +863,10 @@ struct ubifs_old_idx { /* The below union makes it easier to deal with keys */ union ubifs_key { - uint8_t u8[CUR_MAX_KEY_LEN]; - uint32_t u32[CUR_MAX_KEY_LEN/4]; - uint64_t u64[CUR_MAX_KEY_LEN/8]; - __le32 j32[CUR_MAX_KEY_LEN/4]; + uint8_t u8[UBIFS_SK_LEN]; + uint32_t u32[UBIFS_SK_LEN/4]; + uint64_t u64[UBIFS_SK_LEN/8]; + __le32 j32[UBIFS_SK_LEN/4]; }; /** @@ -805,9 +975,9 @@ struct ubifs_gced_idx_leb { * The @ui_size is a "shadow" variable for @inode->i_size and UBIFS uses * @ui_size instead of @inode->i_size. The reason for this is that UBIFS cannot * make sure @inode->i_size is always changed under @ui_mutex, because it - * cannot call 'vmtruncate()' with @ui_mutex locked, because it would deadlock - * with 'ubifs_writepage()' (see file.c). All the other inode fields are - * changed under @ui_mutex, so they do not need "shadow" fields. Note, one + * cannot call 'truncate_setsize()' with @ui_mutex locked, because it would + * deadlock with 'ubifs_writepage()' (see file.c). All the other inode fields + * are changed under @ui_mutex, so they do not need "shadow" fields. Note, one * could consider to rework locking and base it on "shadow" fields. */ struct ubifs_inode { @@ -1068,17 +1238,19 @@ typedef int (*ubifs_lpt_scan_callback)(struct ubifs_info *c, * @offs: write-buffer offset in this logical eraseblock * @avail: number of bytes available in the write-buffer * @used: number of used bytes in the write-buffer - * @dtype: type of data stored in this LEB (%UBI_LONGTERM, %UBI_SHORTTERM, - * %UBI_UNKNOWN) + * @size: write-buffer size (in [@c->min_io_size, @c->max_write_size] range) * @jhead: journal head the mutex belongs to (note, needed only to shut lockdep * up by 'mutex_lock_nested()). * @sync_callback: write-buffer synchronization callback * @io_mutex: serializes write-buffer I/O * @lock: serializes @buf, @lnum, @offs, @avail, @used, @next_ino and @inodes * fields + * @softlimit: soft write-buffer timeout interval + * @delta: hard and soft timeouts delta (the timer expire inteval is @softlimit + * and @softlimit + @delta) * @timer: write-buffer timer - * @timeout: timer expire interval in jiffies - * @need_sync: it is set if its timer expired and needs sync + * @no_timer: non-zero if this write-buffer does not have a timer + * @need_sync: non-zero if the timer expired and the wbuf needs sync'ing * @next_ino: points to the next position of the following inode number * @inodes: stores the inode numbers of the nodes which are in wbuf * @@ -1099,13 +1271,16 @@ struct ubifs_wbuf { int offs; int avail; int used; - int dtype; + int size; int jhead; int (*sync_callback)(struct ubifs_info *c, int lnum, int free, int pad); struct mutex io_mutex; spinlock_t lock; - int timeout; - int need_sync; +// ktime_t softlimit; +// unsigned long long delta; +// struct hrtimer timer; + unsigned int no_timer:1; + unsigned int need_sync:1; int next_ino; ino_t *inodes; }; @@ -1130,12 +1305,14 @@ struct ubifs_bud { * struct ubifs_jhead - journal head. * @wbuf: head's write-buffer * @buds_list: list of bud LEBs belonging to this journal head + * @grouped: non-zero if UBIFS groups nodes when writing to this journal head * * Note, the @buds list is protected by the @c->buds_lock. */ struct ubifs_jhead { struct ubifs_wbuf wbuf; struct list_head buds_list; + unsigned int grouped:1; }; /** @@ -1171,6 +1348,9 @@ struct ubifs_zbranch { * @offs: offset of the corresponding indexing node * @len: length of the corresponding indexing node * @zbranch: array of znode branches (@c->fanout elements) + * + * Note! The @lnum, @offs, and @len fields are not really needed - we have them + * only for internal consistency check. They could be removed to save some RAM. */ struct ubifs_znode { struct ubifs_znode *parent; @@ -1181,9 +1361,9 @@ struct ubifs_znode { int child_cnt; int iip; int alt; -#ifdef CONFIG_UBIFS_FS_DEBUG - int lnum, offs, len; -#endif + int lnum; + int offs; + int len; struct ubifs_zbranch zbranch[]; }; @@ -1236,10 +1416,15 @@ struct ubifs_node_range { */ struct ubifs_compressor { int compr_type; - char *name; - char *capi_name; + struct crypto_comp *cc; + struct mutex *comp_mutex; + struct mutex *decomp_mutex; + const char *name; + const char *capi_name; +#ifdef __UBOOT__ int (*decompress)(const unsigned char *in, size_t in_len, unsigned char *out, size_t *out_len); +#endif }; /** @@ -1313,6 +1498,8 @@ struct ubifs_budget_req { * @dnext: next orphan to delete * @inum: inode number * @new: %1 => added since the last commit, otherwise %0 + * @cmt: %1 => commit pending, otherwise %0 + * @del: %1 => delete pending, otherwise %0 */ struct ubifs_orphan { struct rb_node rb; @@ -1321,7 +1508,9 @@ struct ubifs_orphan { struct ubifs_orphan *cnext; struct ubifs_orphan *dnext; ino_t inum; - int new; + unsigned new:1; + unsigned cmt:1; + unsigned del:1; }; /** @@ -1344,6 +1533,40 @@ struct ubifs_mount_opts { unsigned int compr_type:2; }; +/** + * struct ubifs_budg_info - UBIFS budgeting information. + * @idx_growth: amount of bytes budgeted for index growth + * @data_growth: amount of bytes budgeted for cached data + * @dd_growth: amount of bytes budgeted for cached data that will make + * other data dirty + * @uncommitted_idx: amount of bytes were budgeted for growth of the index, but + * which still have to be taken into account because the index + * has not been committed so far + * @old_idx_sz: size of index on flash + * @min_idx_lebs: minimum number of LEBs required for the index + * @nospace: non-zero if the file-system does not have flash space (used as + * optimization) + * @nospace_rp: the same as @nospace, but additionally means that even reserved + * pool is full + * @page_budget: budget for a page (constant, nenver changed after mount) + * @inode_budget: budget for an inode (constant, nenver changed after mount) + * @dent_budget: budget for a directory entry (constant, nenver changed after + * mount) + */ +struct ubifs_budg_info { + long long idx_growth; + long long data_growth; + long long dd_growth; + long long uncommitted_idx; + unsigned long long old_idx_sz; + int min_idx_lebs; + unsigned int nospace:1; + unsigned int nospace_rp:1; + int page_budget; + int inode_budget; + int dent_budget; +}; + struct ubifs_debug_info; /** @@ -1387,6 +1610,7 @@ struct ubifs_debug_info; * @cmt_wq: wait queue to sleep on if the log is full and a commit is running * * @big_lpt: flag that LPT is too big to write whole during commit + * @space_fixup: flag indicating that free space in LEBs needs to be cleaned up * @no_chk_data_crc: do not check CRCs when reading data nodes (except during * recovery) * @bulk_read: enable bulk-reads @@ -1418,6 +1642,11 @@ struct ubifs_debug_info; * @bu_mutex: protects the pre-allocated bulk-read buffer and @c->bu * @bu: pre-allocated bulk-read information * + * @write_reserve_mutex: protects @write_reserve_buf + * @write_reserve_buf: on the write path we allocate memory, which might + * sometimes be unavailable, in which case we use this + * write reserve buffer + * * @log_lebs: number of logical eraseblocks in the log * @log_bytes: log size in bytes * @log_last: last LEB of the log @@ -1439,43 +1668,34 @@ struct ubifs_debug_info; * * @min_io_size: minimal input/output unit size * @min_io_shift: number of bits in @min_io_size minus one + * @max_write_size: maximum amount of bytes the underlying flash can write at a + * time (MTD write buffer size) + * @max_write_shift: number of bits in @max_write_size minus one * @leb_size: logical eraseblock size in bytes + * @leb_start: starting offset of logical eraseblocks within physical + * eraseblocks * @half_leb_size: half LEB size + * @idx_leb_size: how many bytes of an LEB are effectively available when it is + * used to store indexing nodes (@leb_size - @max_idx_node_sz) * @leb_cnt: count of logical eraseblocks * @max_leb_cnt: maximum count of logical eraseblocks * @old_leb_cnt: count of logical eraseblocks before re-size * @ro_media: the underlying UBI volume is read-only + * @ro_mount: the file-system was mounted as read-only + * @ro_error: UBIFS switched to R/O mode because an error happened * * @dirty_pg_cnt: number of dirty pages (not used) * @dirty_zn_cnt: number of dirty znodes * @clean_zn_cnt: number of clean znodes * - * @budg_idx_growth: amount of bytes budgeted for index growth - * @budg_data_growth: amount of bytes budgeted for cached data - * @budg_dd_growth: amount of bytes budgeted for cached data that will make - * other data dirty - * @budg_uncommitted_idx: amount of bytes were budgeted for growth of the index, - * but which still have to be taken into account because - * the index has not been committed so far - * @space_lock: protects @budg_idx_growth, @budg_data_growth, @budg_dd_growth, - * @budg_uncommited_idx, @min_idx_lebs, @old_idx_sz, @lst, - * @nospace, and @nospace_rp; - * @min_idx_lebs: minimum number of LEBs required for the index - * @old_idx_sz: size of index on flash + * @space_lock: protects @bi and @lst + * @lst: lprops statistics + * @bi: budgeting information * @calc_idx_sz: temporary variable which is used to calculate new index size * (contains accurate new index size at end of TNC commit start) - * @lst: lprops statistics - * @nospace: non-zero if the file-system does not have flash space (used as - * optimization) - * @nospace_rp: the same as @nospace, but additionally means that even reserved - * pool is full - * - * @page_budget: budget for a page - * @inode_budget: budget for an inode - * @dent_budget: budget for a directory entry * * @ref_node_alsz: size of the LEB reference node aligned to the min. flash - * I/O unit + * I/O unit * @mst_node_alsz: master node aligned size * @min_idx_node_sz: minimum indexing node aligned on 8-bytes boundary * @max_idx_node_sz: maximum indexing node aligned on 8-bytes boundary @@ -1558,9 +1778,11 @@ struct ubifs_debug_info; * previous commit start * @uncat_list: list of un-categorized LEBs * @empty_list: list of empty LEBs - * @freeable_list: list of freeable non-index LEBs (free + dirty == leb_size) - * @frdi_idx_list: list of freeable index LEBs (free + dirty == leb_size) + * @freeable_list: list of freeable non-index LEBs (free + dirty == @leb_size) + * @frdi_idx_list: list of freeable index LEBs (free + dirty == @leb_size) * @freeable_cnt: number of freeable LEBs in @freeable_list + * @in_a_category_cnt: count of lprops which are in a certain category, which + * basically meants that they were loaded from the flash * * @ltab_lnum: LEB number of LPT's own lprops table * @ltab_offs: offset of LPT's own lprops table @@ -1577,25 +1799,29 @@ struct ubifs_debug_info; * @rp_uid: reserved pool user ID * @rp_gid: reserved pool group ID * - * @empty: if the UBI device is empty - * @replay_tree: temporary tree used during journal replay + * @empty: %1 if the UBI device is empty + * @need_recovery: %1 if the file-system needs recovery + * @replaying: %1 during journal replay + * @mounting: %1 while mounting + * @remounting_rw: %1 while re-mounting from R/O mode to R/W mode * @replay_list: temporary list used during journal replay * @replay_buds: list of buds to replay * @cs_sqnum: sequence number of first node in the log (commit start node) * @replay_sqnum: sequence number of node currently being replayed - * @need_recovery: file-system needs recovery - * @replaying: set to %1 during journal replay - * @unclean_leb_list: LEBs to recover when mounting ro to rw - * @rcvrd_mst_node: recovered master node to write when mounting ro to rw + * @unclean_leb_list: LEBs to recover when re-mounting R/O mounted FS to R/W + * mode + * @rcvrd_mst_node: recovered master node to write when re-mounting R/O mounted + * FS to R/W mode * @size_tree: inode size information for recovery - * @remounting_rw: set while remounting from ro to rw (sb flags have MS_RDONLY) - * @always_chk_crc: always check CRCs (while mounting and remounting rw) * @mount_opts: UBIFS-specific mount options * * @dbg: debugging-related information */ struct ubifs_info { struct super_block *vfs_sb; +#ifndef __UBOOT__ + struct backing_dev_info bdi; +#endif ino_t highest_inum; unsigned long long max_sqnum; @@ -1628,6 +1854,7 @@ struct ubifs_info { wait_queue_head_t cmt_wq; unsigned int big_lpt:1; + unsigned int space_fixup:1; unsigned int no_chk_data_crc:1; unsigned int bulk_read:1; unsigned int default_compr:2; @@ -1657,6 +1884,9 @@ struct ubifs_info { struct mutex bu_mutex; struct bu_info bu; + struct mutex write_reserve_mutex; + void *write_reserve_buf; + int log_lebs; long long log_bytes; int log_last; @@ -1678,28 +1908,27 @@ struct ubifs_info { int min_io_size; int min_io_shift; + int max_write_size; + int max_write_shift; int leb_size; + int leb_start; int half_leb_size; + int idx_leb_size; int leb_cnt; int max_leb_cnt; int old_leb_cnt; - int ro_media; + unsigned int ro_media:1; + unsigned int ro_mount:1; + unsigned int ro_error:1; + + atomic_long_t dirty_pg_cnt; + atomic_long_t dirty_zn_cnt; + atomic_long_t clean_zn_cnt; - long long budg_idx_growth; - long long budg_data_growth; - long long budg_dd_growth; - long long budg_uncommitted_idx; spinlock_t space_lock; - int min_idx_lebs; - unsigned long long old_idx_sz; - unsigned long long calc_idx_sz; struct ubifs_lp_stats lst; - unsigned int nospace:1; - unsigned int nospace_rp:1; - - int page_budget; - int inode_budget; - int dent_budget; + struct ubifs_budg_info bi; + unsigned long long calc_idx_sz; int ref_node_alsz; int mst_node_alsz; @@ -1785,6 +2014,7 @@ struct ubifs_info { struct list_head freeable_list; struct list_head frdi_idx_list; int freeable_cnt; + int in_a_category_cnt; int ltab_lnum; int ltab_offs; @@ -1798,31 +2028,32 @@ struct ubifs_info { long long rp_size; long long report_rp_size; - uid_t rp_uid; - gid_t rp_gid; + kuid_t rp_uid; + kgid_t rp_gid; /* The below fields are used only during mounting and re-mounting */ - int empty; - struct rb_root replay_tree; + unsigned int empty:1; + unsigned int need_recovery:1; + unsigned int replaying:1; + unsigned int mounting:1; + unsigned int remounting_rw:1; struct list_head replay_list; struct list_head replay_buds; unsigned long long cs_sqnum; unsigned long long replay_sqnum; - int need_recovery; - int replaying; struct list_head unclean_leb_list; struct ubifs_mst_node *rcvrd_mst_node; struct rb_root size_tree; - int remounting_rw; - int always_chk_crc; struct ubifs_mount_opts mount_opts; -#ifdef CONFIG_UBIFS_FS_DEBUG +#ifndef __UBOOT__ struct ubifs_debug_info *dbg; #endif }; +extern struct list_head ubifs_infos; extern spinlock_t ubifs_infos_lock; +extern atomic_long_t ubifs_clean_zn_cnt; extern struct kmem_cache *ubifs_inode_slab; extern const struct super_operations ubifs_super_operations; extern const struct address_space_operations ubifs_file_address_operations; @@ -1836,16 +2067,23 @@ extern struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT]; /* io.c */ void ubifs_ro_mode(struct ubifs_info *c, int err); +int ubifs_leb_read(const struct ubifs_info *c, int lnum, void *buf, int offs, + int len, int even_ebadmsg); +int ubifs_leb_write(struct ubifs_info *c, int lnum, const void *buf, int offs, + int len); +int ubifs_leb_change(struct ubifs_info *c, int lnum, const void *buf, int len); +int ubifs_leb_unmap(struct ubifs_info *c, int lnum); +int ubifs_leb_map(struct ubifs_info *c, int lnum); +int ubifs_is_mapped(const struct ubifs_info *c, int lnum); int ubifs_wbuf_write_nolock(struct ubifs_wbuf *wbuf, void *buf, int len); -int ubifs_wbuf_seek_nolock(struct ubifs_wbuf *wbuf, int lnum, int offs, - int dtype); +int ubifs_wbuf_seek_nolock(struct ubifs_wbuf *wbuf, int lnum, int offs); int ubifs_wbuf_init(struct ubifs_info *c, struct ubifs_wbuf *wbuf); int ubifs_read_node(const struct ubifs_info *c, void *buf, int type, int len, int lnum, int offs); int ubifs_read_node_wbuf(struct ubifs_wbuf *wbuf, void *buf, int type, int len, int lnum, int offs); int ubifs_write_node(struct ubifs_info *c, void *node, int len, int lnum, - int offs, int dtype); + int offs); int ubifs_check_node(const struct ubifs_info *c, const void *buf, int lnum, int offs, int quiet, int must_chk_crc); void ubifs_prepare_node(struct ubifs_info *c, void *buf, int len, int pad); @@ -1859,7 +2097,7 @@ int ubifs_sync_wbufs_by_inode(struct ubifs_info *c, struct inode *inode); /* scan.c */ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, - int offs, void *sbuf); + int offs, void *sbuf, int quiet); void ubifs_scan_destroy(struct ubifs_scan_leb *sleb); int ubifs_scan_a_node(const struct ubifs_info *c, void *buf, int len, int lnum, int offs, int quiet); @@ -1921,7 +2159,7 @@ long long ubifs_reported_space(const struct ubifs_info *c, long long free); long long ubifs_calc_available(const struct ubifs_info *c, int min_idx_lebs); /* find.c */ -int ubifs_find_free_space(struct ubifs_info *c, int min_space, int *free, +int ubifs_find_free_space(struct ubifs_info *c, int min_space, int *offs, int squeeze); int ubifs_find_free_leb_for_idx(struct ubifs_info *c); int ubifs_find_dirty_leb(struct ubifs_info *c, struct ubifs_lprops *ret_lp, @@ -1983,8 +2221,13 @@ int ubifs_tnc_read_node(struct ubifs_info *c, struct ubifs_zbranch *zbr, int ubifs_tnc_start_commit(struct ubifs_info *c, struct ubifs_zbranch *zroot); int ubifs_tnc_end_commit(struct ubifs_info *c); +#ifndef __UBOOT__ /* shrinker.c */ -int ubifs_shrinker(int nr_to_scan, gfp_t gfp_mask); +unsigned long ubifs_shrink_scan(struct shrinker *shrink, + struct shrink_control *sc); +unsigned long ubifs_shrink_count(struct shrinker *shrink, + struct shrink_control *sc); +#endif /* commit.c */ int ubifs_bg_thread(void *info); @@ -2003,6 +2246,7 @@ int ubifs_write_master(struct ubifs_info *c); int ubifs_read_superblock(struct ubifs_info *c); struct ubifs_sb_node *ubifs_read_sb_node(struct ubifs_info *c); int ubifs_write_sb_node(struct ubifs_info *c, struct ubifs_sb_node *sup); +int ubifs_fixup_free_space(struct ubifs_info *c); /* replay.c */ int ubifs_validate_entry(struct ubifs_info *c, @@ -2084,14 +2328,15 @@ const struct ubifs_lprops *ubifs_fast_find_free(struct ubifs_info *c); const struct ubifs_lprops *ubifs_fast_find_empty(struct ubifs_info *c); const struct ubifs_lprops *ubifs_fast_find_freeable(struct ubifs_info *c); const struct ubifs_lprops *ubifs_fast_find_frdi_idx(struct ubifs_info *c); +int ubifs_calc_dark(const struct ubifs_info *c, int spc); /* file.c */ -int ubifs_fsync(struct file *file, struct dentry *dentry, int datasync); +int ubifs_fsync(struct file *file, loff_t start, loff_t end, int datasync); int ubifs_setattr(struct dentry *dentry, struct iattr *attr); /* dir.c */ struct inode *ubifs_new_inode(struct ubifs_info *c, const struct inode *dir, - int mode); + umode_t mode); int ubifs_getattr(struct vfsmount *mnt, struct dentry *dentry, struct kstat *stat); @@ -2111,11 +2356,11 @@ int ubifs_iput(struct inode *inode); int ubifs_recover_master_node(struct ubifs_info *c); int ubifs_write_rcvrd_mst_node(struct ubifs_info *c); struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum, - int offs, void *sbuf, int grouped); + int offs, void *sbuf, int jhead); struct ubifs_scan_leb *ubifs_recover_log_leb(struct ubifs_info *c, int lnum, int offs, void *sbuf); -int ubifs_recover_inl_heads(const struct ubifs_info *c, void *sbuf); -int ubifs_clean_lebs(const struct ubifs_info *c, void *sbuf); +int ubifs_recover_inl_heads(struct ubifs_info *c, void *sbuf); +int ubifs_clean_lebs(struct ubifs_info *c, void *sbuf); int ubifs_rcvry_gc_commit(struct ubifs_info *c); int ubifs_recover_size_accum(struct ubifs_info *c, union ubifs_key *key, int deletion, loff_t new_size); @@ -2131,7 +2376,7 @@ long ubifs_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg); /* compressor.c */ int __init ubifs_compressors_init(void); -void __exit ubifs_compressors_exit(void); +void ubifs_compressors_exit(void); void ubifs_compress(const void *in_buf, int in_len, void *out_buf, int *out_len, int *compr_type); int ubifs_decompress(const void *buf, int len, void *out, int *out_len, @@ -2141,7 +2386,12 @@ int ubifs_decompress(const void *buf, int len, void *out, int *out_len, #include "misc.h" #include "key.h" -/* todo: Move these to a common U-Boot header */ -int lzo1x_decompress_safe(const unsigned char *in, size_t in_len, - unsigned char *out, size_t *out_len); +#ifdef __UBOOT__ +/* these are used in cmd_ubifs.c */ +int ubifs_init(void); +int uboot_ubifs_mount(char *vol_name); +void ubifs_umount(struct ubifs_info *c); +int ubifs_ls(char *dir_name); +int ubifs_load(char *filename, u32 addr, u32 size); +#endif #endif /* !__UBIFS_H__ */ diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile index 9b29d225a5..45ff7458c6 100644 --- a/fs/yaffs2/Makefile +++ b/fs/yaffs2/Makefile @@ -16,11 +16,7 @@ # # $Id: Makefile,v 1.15 2007/07/18 19:40:38 charles Exp $ -include $(TOPDIR)/config.mk - -LIB = $(obj)libyaffs2.o - -COBJS-$(CONFIG_YAFFS2) := \ +obj-y := \ yaffs_allocator.o yaffs_attribs.o yaffs_bitmap.o yaffs_uboot_glue.o\ yaffs_checkptrw.o yaffs_ecc.o yaffs_error.o \ yaffsfs.o yaffs_guts.o yaffs_nameval.o yaffs_nand.o\ @@ -28,36 +24,6 @@ COBJS-$(CONFIG_YAFFS2) := \ yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \ yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o -SRCS := $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) - -YCFLAGS = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM -YCFLAGS += -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE -YCFLAGS += -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES - -CFLAGS += $(YCFLAGS) -CPPFLAGS += $(YCFLAGS) - -all: $(LIB) - -$(obj)libyaffs2.a: $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -$(obj)libyaffs2.o: $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -.PHONY: clean distclean -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +ccflags-y = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM \ + -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \ + -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c index 21441fd991..32e6ff2a04 100644 --- a/fs/yaffs2/yaffs_guts.c +++ b/fs/yaffs2/yaffs_guts.c @@ -219,18 +219,11 @@ static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk, const u8 *data, const struct yaffs_ext_tags *tags) { - dev = dev; - nand_chunk = nand_chunk; - data = data; - tags = tags; } static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk, const struct yaffs_ext_tags *tags) { - dev = dev; - nand_chunk = nand_chunk; - tags = tags; } void yaffs_handle_chunk_error(struct yaffs_dev *dev, @@ -814,8 +807,6 @@ struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, int required_depth; int level = file_struct->top_level; - dev = dev; - /* Check sane level and chunk Id */ if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL) return NULL; @@ -3212,20 +3203,18 @@ static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR *name, } else { yaffs_strncpy(name, oh_name + 1, buff_size - 1); } - } else { -#else - dev = dev; - { -#endif - yaffs_strncpy(name, oh_name, buff_size - 1); + + return; } +#endif + + yaffs_strncpy(name, oh_name, buff_size - 1); } static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR *oh_name, const YCHAR *name) { #ifdef CONFIG_YAFFS_AUTO_UNICODE - int is_ascii; YCHAR *w; @@ -3256,13 +3245,12 @@ static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR *oh_name, *oh_name = 0; yaffs_strncpy(oh_name + 1, name, YAFFS_MAX_NAME_LENGTH - 2); } - } else { -#else - dev = dev; - { -#endif - yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1); + + return; } +#endif + + yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1); } /* UpdateObjectHeader updates the header on NAND for an object. diff --git a/fs/yaffs2/yaffs_list.h b/fs/yaffs2/yaffs_list.h deleted file mode 100644 index a7afaea27b..0000000000 --- a/fs/yaffs2/yaffs_list.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * YAFFS: Yet another Flash File System . A NAND-flash specific file system. - * - * Copyright (C) 2002-2011 Aleph One Ltd. - * for Toby Churchill Ltd and Brightstar Engineering - * - * Created by Charles Manning - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License version 2.1 as - * published by the Free Software Foundation. - * - * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. - */ - -/* - * This file is just holds extra declarations of macros that would normally - * be providesd in the Linux kernel. These macros have been written from - * scratch but are functionally equivalent to the Linux ones. - * - */ - -#ifndef __YAFFS_LIST_H__ -#define __YAFFS_LIST_H__ - - -/* - * This is a simple doubly linked list implementation that matches the - * way the Linux kernel doubly linked list implementation works. - */ - -struct list_head { - struct list_head *next; /* next in chain */ - struct list_head *prev; /* previous in chain */ -}; - - -/* Initialise a static list */ -#define LIST_HEAD(name) \ -struct list_head name = { &(name), &(name)} - - - -/* Initialise a list head to an empty list */ -#define INIT_LIST_HEAD(p) \ -do { \ - (p)->next = (p);\ - (p)->prev = (p); \ -} while (0) - - -/* Add an element to a list */ -static inline void list_add(struct list_head *new_entry, - struct list_head *list) -{ - struct list_head *list_next = list->next; - - list->next = new_entry; - new_entry->prev = list; - new_entry->next = list_next; - list_next->prev = new_entry; - -} - -static inline void list_add_tail(struct list_head *new_entry, - struct list_head *list) -{ - struct list_head *list_prev = list->prev; - - list->prev = new_entry; - new_entry->next = list; - new_entry->prev = list_prev; - list_prev->next = new_entry; - -} - - -/* Take an element out of its current list, with or without - * reinitialising the links.of the entry*/ -static inline void list_del(struct list_head *entry) -{ - struct list_head *list_next = entry->next; - struct list_head *list_prev = entry->prev; - - list_next->prev = list_prev; - list_prev->next = list_next; - -} - -static inline void list_del_init(struct list_head *entry) -{ - list_del(entry); - entry->next = entry->prev = entry; -} - - -/* Test if the list is empty */ -static inline int list_empty(struct list_head *entry) -{ - return (entry->next == entry); -} - - -/* list_entry takes a pointer to a list entry and offsets it to that - * we can find a pointer to the object it is embedded in. - */ - - -#define list_entry(entry, type, member) \ - ((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member))) - - -/* list_for_each and list_for_each_safe iterate over lists. - * list_for_each_safe uses temporary storage to make the list delete safe - */ - -#define list_for_each(itervar, list) \ - for (itervar = (list)->next; itervar != (list); itervar = itervar->next) - -#define list_for_each_safe(itervar, save_var, list) \ - for (itervar = (list)->next, save_var = (list)->next->next; \ - itervar != (list); \ - itervar = save_var, save_var = save_var->next) - - -#endif diff --git a/fs/yaffs2/yaffs_qsort.c b/fs/yaffs2/yaffs_qsort.c index afd1ffa799..1ca5895740 100644 --- a/fs/yaffs2/yaffs_qsort.c +++ b/fs/yaffs2/yaffs_qsort.c @@ -2,29 +2,7 @@ * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "yportenv.h" diff --git a/fs/yaffs2/yaffs_summary.c b/fs/yaffs2/yaffs_summary.c index 46e42f6d7d..e9e1b5d857 100644 --- a/fs/yaffs2/yaffs_summary.c +++ b/fs/yaffs2/yaffs_summary.c @@ -232,7 +232,6 @@ int yaffs_summary_read(struct yaffs_dev *dev, if (result == YAFFS_OK) { /* Verify header */ if (hdr.version != YAFFS_SUMMARY_VERSION || - hdr.block != blk || hdr.seq != bi->seq_number || hdr.sum != yaffs_summary_sum(dev)) result = YAFFS_FAIL; diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c index e113e4039e..50000a135b 100644 --- a/fs/yaffs2/yaffs_uboot_glue.c +++ b/fs/yaffs2/yaffs_uboot_glue.c @@ -20,6 +20,7 @@ */ #include +#include #include #include "nand.h" @@ -184,7 +185,7 @@ void cmd_yaffs_devconfig(char *_mp, int flash_dev, } if (end_block == 0) - end_block = mtd->size / mtd->erasesize - 1; + end_block = lldiv(mtd->size, mtd->erasesize - 1); if (end_block < start_block) { printf("Bad start/end\n"); diff --git a/fs/yaffs2/yaffs_verify.c b/fs/yaffs2/yaffs_verify.c index 97734a9e29..3fef28bdcb 100644 --- a/fs/yaffs2/yaffs_verify.c +++ b/fs/yaffs2/yaffs_verify.c @@ -19,20 +19,17 @@ int yaffs_skip_verification(struct yaffs_dev *dev) { - dev = dev; return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL)); } static int yaffs_skip_full_verification(struct yaffs_dev *dev) { - dev = dev; return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_FULL)); } static int yaffs_skip_nand_verification(struct yaffs_dev *dev) { - dev = dev; return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_NAND)); } @@ -521,6 +518,5 @@ void yaffs_verify_free_chunks(struct yaffs_dev *dev) int yaffs_verify_file_sane(struct yaffs_obj *in) { - in = in; return YAFFS_OK; } diff --git a/fs/yaffs2/yaffsfs.c b/fs/yaffs2/yaffsfs.c index ac4a010bdf..41e5f0108c 100644 --- a/fs/yaffs2/yaffsfs.c +++ b/fs/yaffs2/yaffsfs.c @@ -11,6 +11,7 @@ * published by the Free Software Foundation. */ +#include #include "yaffsfs.h" #include "yaffs_guts.h" #include "yaffscfg.h" @@ -1603,8 +1604,8 @@ static int yaffsfs_DoStat(struct yaffs_obj *obj, struct yaffs_stat *buf) buf->st_rdev = obj->yst_rdev; buf->st_size = yaffs_get_obj_length(obj); buf->st_blksize = obj->my_dev->data_bytes_per_chunk; - buf->st_blocks = (buf->st_size + buf->st_blksize - 1) / - buf->st_blksize; + buf->st_blocks = lldiv(buf->st_size + buf->st_blksize - 1, + buf->st_blksize); #if CONFIG_YAFFS_WINCE buf->yst_wince_atime[0] = obj->win_atime[0]; buf->yst_wince_atime[1] = obj->win_atime[1]; @@ -3135,10 +3136,6 @@ int yaffs_link(const YCHAR *oldpath, const YCHAR *linkpath) int yaffs_mknod(const YCHAR *pathname, mode_t mode, dev_t dev) { - pathname = pathname; - mode = mode; - dev = dev; - yaffsfs_SetError(-EINVAL); return -1; } @@ -3186,9 +3183,7 @@ int yaffs_set_error(int error) int yaffs_dump_dev(const YCHAR *path) { -#if 1 - path = path; -#else +#if 0 YCHAR *rest; struct yaffs_obj *obj = yaffsfs_FindRoot(path, &rest); diff --git a/fs/yaffs2/ydirectenv.h b/fs/yaffs2/ydirectenv.h index c2ffbfd56d..2b3e84fd38 100644 --- a/fs/yaffs2/ydirectenv.h +++ b/fs/yaffs2/ydirectenv.h @@ -58,8 +58,6 @@ void yaffs_qsort(void *aa, size_t n, size_t es, #define inline #endif -#define cond_resched() do {} while (0) - #define yaffs_trace(msk, fmt, ...) do { \ if (yaffs_trace_mask & (msk)) \ printf("yaffs: " fmt "\n", ##__VA_ARGS__); \ @@ -77,7 +75,7 @@ void yaffs_qsort(void *aa, size_t n, size_t es, #define YAFFS_ROOT_MODE 0666 #define YAFFS_LOSTNFOUND_MODE 0666 -#include "yaffs_list.h" +#include "linux/list.h" #include "yaffsfs.h" diff --git a/fs/zfs/Makefile b/fs/zfs/Makefile index 32070de58d..fa58b7fcde 100644 --- a/fs/zfs/Makefile +++ b/fs/zfs/Makefile @@ -5,27 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libzfs.o - -AOBJS = -COBJS-$(CONFIG_CMD_ZFS) := dev.o zfs.o zfs_fletcher.o zfs_sha256.o zfs_lzjb.o - -SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) - - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y := dev.o zfs.o zfs_fletcher.o zfs_sha256.o zfs_lzjb.o diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c index 099d51718b..fb2b3ee089 100644 --- a/fs/zfs/zfs.c +++ b/fs/zfs/zfs.c @@ -736,7 +736,7 @@ zap_hash(uint64_t salt, const char *name) uint64_t crc = salt; if (table[128] == 0) { - uint64_t *ct; + uint64_t *ct = NULL; int i, j; for (i = 0; i < 256; i++) { for (ct = table + i, *ct = i, j = 8; j > 0; j--) @@ -772,7 +772,7 @@ zap_leaf_array_equal(zap_leaf_phys_t *l, zfs_endian_t endian, while (bseen < array_len) { struct zap_leaf_array *la = &ZAP_LEAF_CHUNK(l, blksft, chunk).l_array; - int toread = MIN(array_len - bseen, ZAP_LEAF_ARRAY_BYTES); + int toread = min(array_len - bseen, ZAP_LEAF_ARRAY_BYTES); if (chunk >= ZAP_LEAF_NUMCHUNKS(blksft)) return 0; @@ -794,7 +794,7 @@ zap_leaf_array_get(zap_leaf_phys_t *l, zfs_endian_t endian, int blksft, while (bseen < array_len) { struct zap_leaf_array *la = &ZAP_LEAF_CHUNK(l, blksft, chunk).l_array; - int toread = MIN(array_len - bseen, ZAP_LEAF_ARRAY_BYTES); + int toread = min(array_len - bseen, ZAP_LEAF_ARRAY_BYTES); if (chunk >= ZAP_LEAF_NUMCHUNKS(blksft)) /* Don't use errno because this error is to be ignored. */ @@ -1060,6 +1060,7 @@ zap_lookup(dnode_end_t *zap_dnode, char *name, uint64_t *val, } printf("unknown ZAP type\n"); + free(zapbuf); return ZFS_ERR_BAD_FS; } @@ -1094,6 +1095,7 @@ zap_iterate(dnode_end_t *zap_dnode, return ret; } printf("unknown ZAP type\n"); + free(zapbuf); return 0; } @@ -1865,6 +1867,7 @@ zfs_mount(device_t dev) ubbest = malloc(sizeof(*ubbest)); if (!ubbest) { + free(ub_array); zfs_unmount(data); return 0; } @@ -1953,6 +1956,7 @@ zfs_mount(device_t dev) if (err) { printf("couldn't zio_read object directory\n"); zfs_unmount(data); + free(osp); free(ubbest); return 0; } @@ -2052,6 +2056,9 @@ zfs_open(struct zfs_file *file, const char *fsfilename) hdrsize = SA_HDR_SIZE(((sa_hdr_phys_t *) sahdrp)); file->size = *(uint64_t *) ((char *) sahdrp + hdrsize + SA_SIZE_OFFSET); + if ((data->dnode.dn.dn_bonuslen == 0) && + (data->dnode.dn.dn_flags & DNODE_FLAG_SPILL_BLKPTR)) + free(sahdrp); } else { file->size = zfs_to_cpu64(((znode_phys_t *) DN_BONUS(&data->dnode.dn))->zp_size, data->dnode.endian); } @@ -2118,7 +2125,7 @@ zfs_read(zfs_file_t file, char *buf, uint64_t len) data->file_start = blkid * blksz; data->file_end = data->file_start + blksz; - movesize = MIN(length, data->file_end - (int) file->offset - red); + movesize = min(length, data->file_end - (int)file->offset - red); memmove(buf, data->file_buf + file->offset + red - data->file_start, movesize); diff --git a/include/.gitignore b/include/.gitignore index 7cd3e90700..8e41a9511d 100644 --- a/include/.gitignore +++ b/include/.gitignore @@ -1,6 +1,4 @@ /autoconf.mk* -/asm /bmp_logo.h /bmp_logo_data.h /config.h -/config.mk diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h deleted file mode 100644 index 3deeeeaa5a..0000000000 --- a/include/74xx_7xx.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * 74xx_7xx.h - * - * 74xx/7xx specific definitions - */ - -#ifndef __MPC74XX_H__ -#define __MPC74XX_H__ - -/*---------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/*---------------------------------------------------------------- - * l2cr values - */ -#define l2cr 1017 - -#define L2CR_L2E 0x80000000 /* bit 0 - enable */ -#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ -#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */ -#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */ -#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */ -#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */ -#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */ -#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */ -#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */ -#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */ -#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */ -#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */ -#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */ -#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */ -#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */ -#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ -#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ -#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */ -#define L2CR_TS 0x00040000 /* bit 13 - test support on */ -#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */ -#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */ -#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */ -#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */ -#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ - -#ifndef __ASSEMBLY__ -/* cpu ids we detect */ -typedef enum __cpu_t { - CPU_740, CPU_750, - CPU_740P, CPU_750P, - CPU_745, CPU_755, - CPU_750CX, CPU_750FX, CPU_750GX, - CPU_7400, - CPU_7410, - CPU_7447A, CPU_7448, - CPU_7450, CPU_7455, CPU_7457, - CPU_UNKNOWN} cpu_t; - -extern cpu_t get_cpu_type(void); - -#define l1icache_enable icache_enable - -void l2cache_enable(void); -void l1dcache_enable(void); - -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -static __inline__ unsigned long get_hid0 (void) -{ - unsigned long hid0; - asm volatile("mfspr %0, 1008" : "=r" (hid0) :); - return hid0; -} - -static __inline__ unsigned long get_hid1 (void) -{ - unsigned long hid1; - asm volatile("mfspr %0, 1009" : "=r" (hid1) :); - return hid1; -} - -static __inline__ void set_hid0 (unsigned long hid0) -{ - asm volatile("mtspr 1008, %0" : : "r" (hid0)); -} - -static __inline__ void set_hid1 (unsigned long hid1) -{ - asm volatile("mtspr 1009, %0" : : "r" (hid1)); -} - -#endif /* __ASSEMBLY__ */ -#endif /* __MPC74XX_H__ */ diff --git a/include/_exports.h b/include/_exports.h index 349a3c5522..594470328e 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -1,32 +1,73 @@ /* - * You do not need to use #ifdef around functions that may not exist + * You need to use #ifdef around functions that may not exist * in the final configuration (such as i2c). + * use a dummyfunction as first parameter to EXPORT_FUNC. + * As an example see the CONFIG_CMD_I2C section below */ -EXPORT_FUNC(get_version) -EXPORT_FUNC(getc) -EXPORT_FUNC(tstc) -EXPORT_FUNC(putc) -EXPORT_FUNC(puts) -EXPORT_FUNC(printf) -EXPORT_FUNC(install_hdlr) -EXPORT_FUNC(free_hdlr) -EXPORT_FUNC(malloc) -EXPORT_FUNC(free) -EXPORT_FUNC(udelay) -EXPORT_FUNC(get_timer) -EXPORT_FUNC(vprintf) -EXPORT_FUNC(do_reset) -EXPORT_FUNC(getenv) -EXPORT_FUNC(setenv) -EXPORT_FUNC(simple_strtoul) -EXPORT_FUNC(strict_strtoul) -EXPORT_FUNC(simple_strtol) -EXPORT_FUNC(strcmp) -EXPORT_FUNC(i2c_write) -EXPORT_FUNC(i2c_read) -EXPORT_FUNC(spi_init) -EXPORT_FUNC(spi_setup_slave) -EXPORT_FUNC(spi_free_slave) -EXPORT_FUNC(spi_claim_bus) -EXPORT_FUNC(spi_release_bus) -EXPORT_FUNC(spi_xfer) +#ifndef EXPORT_FUNC +#define EXPORT_FUNC(a, b, c, ...) +#endif + EXPORT_FUNC(get_version, unsigned long, get_version, void) + EXPORT_FUNC(getc, int, getc, void) + EXPORT_FUNC(tstc, int, tstc, void) + EXPORT_FUNC(putc, void, putc, const char) + EXPORT_FUNC(puts, void, puts, const char *) + EXPORT_FUNC(printf, int, printf, const char*, ...) +#if defined(CONFIG_X86) || defined(CONFIG_PPC) + EXPORT_FUNC(irq_install_handler, void, install_hdlr, + int, interrupt_handler_t, void*) + + EXPORT_FUNC(irq_free_handler, void, free_hdlr, int) +#else + EXPORT_FUNC(dummy, void, install_hdlr, void) + EXPORT_FUNC(dummy, void, free_hdlr, void) +#endif + EXPORT_FUNC(malloc, void *, malloc, size_t) + EXPORT_FUNC(free, void, free, void *) + EXPORT_FUNC(udelay, void, udelay, unsigned long) + EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long) + EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list) + EXPORT_FUNC(do_reset, int, do_reset, cmd_tbl_t *, + int , int , char * const []) + EXPORT_FUNC(getenv, char *, getenv, const char*) + EXPORT_FUNC(setenv, int, setenv, const char *, const char *) + EXPORT_FUNC(simple_strtoul, unsigned long, simple_strtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(strict_strtoul, int, strict_strtoul, + const char *, unsigned int , unsigned long *) + EXPORT_FUNC(simple_strtol, long, simple_strtol, + const char *, char **, unsigned int) + EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct) +#if defined(CONFIG_CMD_I2C) && \ + (!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT)) + EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int) + EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) +#else + EXPORT_FUNC(dummy, void, i2c_write, void) + EXPORT_FUNC(dummy, void, i2c_read, void) +#endif + +#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI) + EXPORT_FUNC(dummy, void, spi_init, void) + EXPORT_FUNC(dummy, void, spi_setup_slave, void) + EXPORT_FUNC(dummy, void, spi_free_slave, void) +#else + EXPORT_FUNC(spi_init, void, spi_init, void) + EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave, + unsigned int, unsigned int, unsigned int, unsigned int) + EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *) +#endif +#ifndef CONFIG_CMD_SPI + EXPORT_FUNC(dummy, void, spi_claim_bus, void) + EXPORT_FUNC(dummy, void, spi_release_bus, void) + EXPORT_FUNC(dummy, void, spi_xfer, void) +#else + EXPORT_FUNC(spi_claim_bus, int, spi_claim_bus, struct spi_slave *) + EXPORT_FUNC(spi_release_bus, void, spi_release_bus, struct spi_slave *) + EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *, + unsigned int, const void *, void *, unsigned long) +#endif + EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull, + const char *, char **, unsigned int) diff --git a/include/aboot.h b/include/aboot.h new file mode 100644 index 0000000000..30e4d36df8 --- /dev/null +++ b/include/aboot.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define ROUNDUP(x, y) (((x) + ((y) - 1)) & ~((y) - 1)) + +void fastboot_fail(const char *s); +void fastboot_okay(const char *s); + +static inline int is_sparse_image(void *buf) +{ + sparse_header_t *s_header = (sparse_header_t *)buf; + + if ((le32_to_cpu(s_header->magic) == SPARSE_HEADER_MAGIC) && + (le16_to_cpu(s_header->major_version) == 1)) + return 1; + + return 0; +} + +void write_sparse_image(block_dev_desc_t *dev_desc, + disk_partition_t *info, const char *part_name, + void *data, unsigned sz); diff --git a/include/aes.h b/include/aes.h index ea06308279..6315c02aa9 100644 --- a/include/aes.h +++ b/include/aes.h @@ -8,6 +8,13 @@ #ifndef _AES_REF_H_ #define _AES_REF_H_ +#ifdef USE_HOSTCC +/* Define compat stuff for use in fw_* tools. */ +typedef unsigned char u8; +typedef unsigned int u32; +#define debug(...) do {} while (0) +#endif + /* * AES encryption library, with small code size, supporting only 128-bit AES * @@ -25,30 +32,63 @@ enum { }; /** + * aes_expand_key() - Expand the AES key + * * Expand a key into a key schedule, which is then used for the other * operations. * - * \param key Key, of length AES_KEY_LENGTH bytes - * \param expkey Buffer to place expanded key, AES_EXPAND_KEY_LENGTH + * @key Key, of length AES_KEY_LENGTH bytes + * @expkey Buffer to place expanded key, AES_EXPAND_KEY_LENGTH */ void aes_expand_key(u8 *key, u8 *expkey); /** - * Encrypt a single block of data + * aes_encrypt() - Encrypt single block of data with AES 128 * - * in Input data - * expkey Expanded key to use for encryption (from aes_expand_key()) - * out Output data + * @in Input data + * @expkey Expanded key to use for encryption (from aes_expand_key()) + * @out Output data */ void aes_encrypt(u8 *in, u8 *expkey, u8 *out); /** - * Decrypt a single block of data + * aes_decrypt() - Decrypt single block of data with AES 128 * - * in Input data - * expkey Expanded key to use for decryption (from aes_expand_key()) - * out Output data + * @in Input data + * @expkey Expanded key to use for decryption (from aes_expand_key()) + * @out Output data */ void aes_decrypt(u8 *in, u8 *expkey, u8 *out); +/** + * Apply chain data to the destination using EOR + * + * Each array is of length AES_KEY_LENGTH. + * + * @cbc_chain_data Chain data + * @src Source data + * @dst Destination data, which is modified here + */ +void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst); + +/** + * aes_cbc_encrypt_blocks() - Encrypt multiple blocks of data with AES CBC. + * + * @key_exp Expanded key to use + * @src Source data to encrypt + * @dst Destination buffer + * @num_aes_blocks Number of AES blocks to encrypt + */ +void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * Decrypt multiple blocks of data with AES CBC. + * + * @key_exp Expanded key to use + * @src Source data to decrypt + * @dst Destination buffer + * @num_aes_blocks Number of AES blocks to decrypt + */ +void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks); + #endif /* _AES_REF_H_ */ diff --git a/include/ahci.h b/include/ahci.h index 1940eea630..2cfd6cfbd7 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -62,6 +62,10 @@ #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ +#ifdef CONFIG_SUNXI_AHCI +#define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */ +#endif + /* PORT_IRQ_{STAT,MASK} bits */ #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ @@ -91,6 +95,11 @@ | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ | PORT_IRQ_D2H_REG_FIS +/* PORT_SCR_STAT bits */ +#define PORT_SCR_STAT_DET_MASK 0x3 +#define PORT_SCR_STAT_DET_COMINIT 0x1 +#define PORT_SCR_STAT_DET_PHYRDY 0x3 + /* PORT_CMD bits */ #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ @@ -107,29 +116,6 @@ #define AHCI_MAX_PORTS 32 -/* SETFEATURES stuff */ -#define SETFEATURES_XFER 0x03 -#define XFER_UDMA_7 0x47 -#define XFER_UDMA_6 0x46 -#define XFER_UDMA_5 0x45 -#define XFER_UDMA_4 0x44 -#define XFER_UDMA_3 0x43 -#define XFER_UDMA_2 0x42 -#define XFER_UDMA_1 0x41 -#define XFER_UDMA_0 0x40 -#define XFER_MW_DMA_2 0x22 -#define XFER_MW_DMA_1 0x21 -#define XFER_MW_DMA_0 0x20 -#define XFER_SW_DMA_2 0x12 -#define XFER_SW_DMA_1 0x11 -#define XFER_SW_DMA_0 0x10 -#define XFER_PIO_4 0x0C -#define XFER_PIO_3 0x0B -#define XFER_PIO_2 0x0A -#define XFER_PIO_1 0x09 -#define XFER_PIO_0 0x08 -#define XFER_PIO_SLOW 0x00 - #define ATA_FLAG_SATA (1 << 3) #define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ #define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ @@ -179,5 +165,6 @@ struct ahci_probe_ent { }; int ahci_init(u32 base); +int ahci_reset(u32 base); #endif diff --git a/include/altera.h b/include/altera.h index 0327a1b82a..c2991ad800 100644 --- a/include/altera.h +++ b/include/altera.h @@ -10,35 +10,59 @@ #ifndef _ALTERA_H_ #define _ALTERA_H_ -typedef enum { /* typedef Altera_iface */ - min_altera_iface_type, /* insert all new types after this */ - passive_serial, /* serial data and external clock */ - passive_parallel_synchronous, /* parallel data */ - passive_parallel_asynchronous, /* parallel data */ - passive_serial_asynchronous, /* serial data w/ internal clock (not used) */ - altera_jtag_mode, /* jtag/tap serial (not used ) */ - fast_passive_parallel, /* fast passive parallel (FPP) */ - fast_passive_parallel_security, /* fast passive parallel with security (FPPS) */ - max_altera_iface_type /* insert all new types before this */ -} Altera_iface; /* end, typedef Altera_iface */ +enum altera_iface { + /* insert all new types after this */ + min_altera_iface_type, + /* serial data and external clock */ + passive_serial, + /* parallel data */ + passive_parallel_synchronous, + /* parallel data */ + passive_parallel_asynchronous, + /* serial data w/ internal clock (not used) */ + passive_serial_asynchronous, + /* jtag/tap serial (not used ) */ + altera_jtag_mode, + /* fast passive parallel (FPP) */ + fast_passive_parallel, + /* fast passive parallel with security (FPPS) */ + fast_passive_parallel_security, + /* insert all new types before this */ + max_altera_iface_type, +}; -typedef enum { /* typedef Altera_Family */ - min_altera_type, /* insert all new types after this */ - Altera_ACEX1K, /* ACEX1K Family */ - Altera_CYC2, /* CYCLONII Family */ - Altera_StratixII, /* StratixII Familiy */ -/* Add new models here */ - max_altera_type /* insert all new types before this */ -} Altera_Family; /* end, typedef Altera_Family */ +enum altera_family { + /* insert all new types after this */ + min_altera_type, + /* ACEX1K Family */ + Altera_ACEX1K, + /* CYCLONII Family */ + Altera_CYC2, + /* StratixII Family */ + Altera_StratixII, + /* SoCFPGA Family */ + Altera_SoCFPGA, -typedef struct { /* typedef Altera_desc */ - Altera_Family family; /* part type */ - Altera_iface iface; /* interface type */ - size_t size; /* bytes of data part can accept */ - void * iface_fns;/* interface function table */ - void * base; /* base interface address */ - int cookie; /* implementation specific cookie */ -} Altera_desc; /* end, typedef Altera_desc */ + /* Add new models here */ + + /* insert all new types before this */ + max_altera_type, +}; + +typedef struct { + /* part type */ + enum altera_family family; + /* interface type */ + enum altera_iface iface; + /* bytes of data part can accept */ + size_t size; + /* interface function table */ + void *iface_fns; + /* base interface address */ + void *base; + /* implementation specific cookie */ + int cookie; +} Altera_desc; /* Generic Altera Functions *********************************************************************/ @@ -69,4 +93,8 @@ typedef struct { Altera_post_fn post; } altera_board_specific_func; +#ifdef CONFIG_FPGA_SOCFPGA +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif + #endif /* _ALTERA_H_ */ diff --git a/include/amba_clcd.h b/include/amba_clcd.h deleted file mode 100644 index db80517e53..0000000000 --- a/include/amba_clcd.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Register definitions for the AMBA CLCD logic cell. - * - * derived from David A Rusling, although rearranged as a C structure - * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel. - * - * Copyright (C) 2001 ARM Limited - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * CLCD Controller Internal Register addresses - */ -struct clcd_registers { - u32 tim0; /* 0x00 */ - u32 tim1; - u32 tim2; - u32 tim3; - u32 ubas; /* 0x10 */ - u32 lbas; -#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW) - u32 ienb; - u32 cntl; -#else /* Someone rearranged these two registers on the Versatile */ - u32 cntl; - u32 ienb; -#endif - u32 stat; /* 0x20 */ - u32 intr; - u32 ucur; - u32 lcur; - u32 unused[0x74]; /* 0x030..0x1ff */ - u32 palette[0x80]; /* 0x200..0x3ff */ -}; - -/* Bit definition for TIM2 */ -#define TIM2_CLKSEL (1 << 5) -#define TIM2_IVS (1 << 11) -#define TIM2_IHS (1 << 12) -#define TIM2_IPC (1 << 13) -#define TIM2_IOE (1 << 14) -#define TIM2_BCD (1 << 26) - -/* Bit definitions for control register */ -#define CNTL_LCDEN (1 << 0) -#define CNTL_LCDBPP1 (0 << 1) -#define CNTL_LCDBPP2 (1 << 1) -#define CNTL_LCDBPP4 (2 << 1) -#define CNTL_LCDBPP8 (3 << 1) -#define CNTL_LCDBPP16 (4 << 1) -#define CNTL_LCDBPP16_565 (6 << 1) -#define CNTL_LCDBPP24 (5 << 1) -#define CNTL_LCDBW (1 << 4) -#define CNTL_LCDTFT (1 << 5) -#define CNTL_LCDMONO8 (1 << 6) -#define CNTL_LCDDUAL (1 << 7) -#define CNTL_BGR (1 << 8) -#define CNTL_BEBO (1 << 9) -#define CNTL_BEPO (1 << 10) -#define CNTL_LCDPWR (1 << 11) -#define CNTL_LCDVCOMP(x) ((x) << 12) -#define CNTL_LDMAFIFOTIME (1 << 15) -#define CNTL_WATERMARK (1 << 16) - -/* u-boot specific: information passed by the board file */ -struct clcd_config { - struct clcd_registers *address; - u32 tim0; - u32 tim1; - u32 tim2; - u32 tim3; - u32 cntl; - unsigned long pixclock; -}; diff --git a/include/android_image.h b/include/android_image.h new file mode 100644 index 0000000000..094d60afe8 --- /dev/null +++ b/include/android_image.h @@ -0,0 +1,69 @@ +/* + * This is from the Android Project, + * Repository: https://android.googlesource.com/platform/bootable/bootloader/legacy + * File: include/boot/bootimg.h + * Commit: 4205b865141ff2e255fe1d3bd16de18e217ef06a + * + * Copyright (C) 2008 The Android Open Source Project + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef _ANDROID_IMAGE_H_ +#define _ANDROID_IMAGE_H_ + +#define ANDR_BOOT_MAGIC "ANDROID!" +#define ANDR_BOOT_MAGIC_SIZE 8 +#define ANDR_BOOT_NAME_SIZE 16 +#define ANDR_BOOT_ARGS_SIZE 512 + +struct andr_img_hdr { + char magic[ANDR_BOOT_MAGIC_SIZE]; + + u32 kernel_size; /* size in bytes */ + u32 kernel_addr; /* physical load addr */ + + u32 ramdisk_size; /* size in bytes */ + u32 ramdisk_addr; /* physical load addr */ + + u32 second_size; /* size in bytes */ + u32 second_addr; /* physical load addr */ + + u32 tags_addr; /* physical addr for kernel tags */ + u32 page_size; /* flash page size we assume */ + u32 unused[2]; /* future expansion: should be 0 */ + + char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */ + + char cmdline[ANDR_BOOT_ARGS_SIZE]; + + u32 id[8]; /* timestamp / checksum / sha1 / etc */ +}; + +/* + * +-----------------+ + * | boot header | 1 page + * +-----------------+ + * | kernel | n pages + * +-----------------+ + * | ramdisk | m pages + * +-----------------+ + * | second stage | o pages + * +-----------------+ + * + * n = (kernel_size + page_size - 1) / page_size + * m = (ramdisk_size + page_size - 1) / page_size + * o = (second_size + page_size - 1) / page_size + * + * 0. all entities are page_size aligned in flash + * 1. kernel and ramdisk are required (size != 0) + * 2. second is optional (second_size == 0 -> no second) + * 3. load each element (kernel, ramdisk, second) at + * the specified physical address (kernel_addr, etc) + * 4. prepare tags at tag_addr. kernel_args[] is + * appended to the kernel commandline in the tags. + * 5. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr + * 6. if second_size != 0: jump to second_addr + * else: jump to kernel_addr + */ +#endif diff --git a/include/api_public.h b/include/api_public.h index 4420c990b4..f5c89f3f13 100644 --- a/include/api_public.h +++ b/include/api_public.h @@ -3,50 +3,7 @@ * * Written by: Rafal Jaworowski * - * This file is dual licensed; you can use it under the terms of - * either the GPL, or the BSD license, at your option. - * - * I. GPL: - * - * This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Alternatively, - * - * II. BSD license: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #ifndef _API_PUBLIC_H_ diff --git a/include/arm925t.h b/include/arm925t.h deleted file mode 100644 index 3d767b35c0..0000000000 --- a/include/arm925t.h +++ /dev/null @@ -1,11 +0,0 @@ -/************************************************ - * NAME : arm925t.h - * Version : 23 June 2003 * - ************************************************/ - -#ifndef __ARM925T_H__ -#define __ARM925T_H__ - -void archflashwp(void *archdata, int wp); - -#endif /*__ARM925T_H__*/ diff --git a/include/armcoremodule.h b/include/armcoremodule.h index b8ba36be50..cc6f2b4d3b 100644 --- a/include/armcoremodule.h +++ b/include/armcoremodule.h @@ -6,7 +6,7 @@ * No standalonw port yet available * - this file is included by both integratorap.h & integratorcp.h * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ARMCOREMODULE_H diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 77e06fb4fe..6747619b1c 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -21,6 +21,8 @@ */ #ifndef __ASSEMBLY__ +#include + typedef struct global_data { bd_t *bd; unsigned long flags; @@ -61,10 +63,17 @@ typedef struct global_data { unsigned long start_addr_sp; /* start_addr_stackpointer */ unsigned long reloc_off; struct global_data *new_gd; /* relocated global data */ + +#ifdef CONFIG_DM + struct udevice *dm_root; /* Root instance for Driver Model */ + struct udevice *dm_root_f; /* Pre-relocation root instance */ + struct list_head uclass_root; /* Head of core tree */ +#endif + const void *fdt_blob; /* Our device tree, NULL if none */ void *new_fdt; /* Relocated FDT */ unsigned long fdt_size; /* Space reserved for relocated FDT */ - void **jt; /* jump table */ + struct jt_funcs *jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ #ifdef CONFIG_TRACE void *trace_buff; /* The trace buffer */ @@ -72,6 +81,23 @@ typedef struct global_data { #if defined(CONFIG_SYS_I2C) int cur_i2c_bus; /* current used i2c bus */ #endif +#ifdef CONFIG_SYS_I2C_MXC + void *srdata[10]; +#endif + unsigned long timebase_h; + unsigned long timebase_l; +#ifdef CONFIG_SYS_MALLOC_F_LEN + unsigned long malloc_base; /* base address of early malloc() */ + unsigned long malloc_limit; /* limit address */ + unsigned long malloc_ptr; /* current address */ +#endif +#ifdef CONFIG_PCI + struct pci_controller *hose; /* PCI hose for early use */ +#endif +#ifdef CONFIG_PCI_BOOTDELAY + int pcidelay_done; +#endif + struct udevice *cur_serial_dev; /* current serial device */ struct arch_global_data arch; /* architecture-specific data */ } gd_t; #endif @@ -87,5 +113,7 @@ typedef struct global_data { #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */ +#define GD_FLG_SERIAL_READY 0x00100 /* Pre-reloc serial console ready */ +#define GD_FLG_FULL_MALLOC_INIT 0x00200 /* Full malloc() is ready */ #endif /* __ASM_GENERIC_GBL_DATA_H */ diff --git a/include/asm-generic/global_data_flags.h b/include/asm-generic/global_data_flags.h deleted file mode 100644 index bb57fb6c4a..0000000000 --- a/include/asm-generic/global_data_flags.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * transitional header until we merge global_data.h - * - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_GENERIC_GLOBAL_DATA_FLAGS_H -#define __ASM_GENERIC_GLOBAL_DATA_FLAGS_H - -/* - * Global Data Flags - * - * Note: The low 16 bits are expected for common code. If your arch - * really needs to add your own, use the high 16bits. - */ -#define GD_FLG_RELOC 0x0001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x0002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x0004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x0008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x0010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x0020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x0040 /* Disable console (in & out) */ -#define GD_FLG_ENV_READY 0x0080 /* Environment imported into hash table */ - -#endif diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 0106d0af65..e728c1e776 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -10,6 +10,15 @@ /* * Generic GPIO API for U-Boot * + * -- + * NB: This is deprecated. Please use the driver model functions instead: + * + * - gpio_request_by_name() + * - dm_gpio_get_value() etc. + * + * For now we need a dm_ prefix on some functions to avoid name collision. + * -- + * * GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined * by the SOC/architecture. * @@ -26,9 +35,9 @@ */ enum gpio_flags { - GPIOF_INPUT, - GPIOF_OUTPUT_INIT_LOW, - GPIOF_OUTPUT_INIT_HIGH, + GPIOFLAG_INPUT, + GPIOFLAG_OUTPUT_INIT_LOW, + GPIOFLAG_OUTPUT_INIT_HIGH, }; struct gpio { @@ -38,8 +47,12 @@ struct gpio { }; /** - * Request a gpio. This should be called before any of the other functions - * are used on this gpio. + * @deprecated Please use driver model instead + * Request a GPIO. This should be called before any of the other functions + * are used on this GPIO. + * + * Note: With driver model, the label is allocated so there is no need for + * the caller to preserve it. * * @param gp GPIO number * @param label User label for this GPIO @@ -48,6 +61,7 @@ struct gpio { int gpio_request(unsigned gpio, const char *label); /** + * @deprecated Please use driver model instead * Stop using the GPIO. This function should not alter pin configuration. * * @param gpio GPIO number @@ -56,6 +70,7 @@ int gpio_request(unsigned gpio, const char *label); int gpio_free(unsigned gpio); /** + * @deprecated Please use driver model instead * Make a GPIO an input. * * @param gpio GPIO number @@ -64,6 +79,7 @@ int gpio_free(unsigned gpio); int gpio_direction_input(unsigned gpio); /** + * @deprecated Please use driver model instead * Make a GPIO an output, and set its value. * * @param gpio GPIO number @@ -73,6 +89,7 @@ int gpio_direction_input(unsigned gpio); int gpio_direction_output(unsigned gpio, int value); /** + * @deprecated Please use driver model instead * Get a GPIO's value. This will work whether the GPIO is an input * or an output. * @@ -82,6 +99,7 @@ int gpio_direction_output(unsigned gpio, int value); int gpio_get_value(unsigned gpio); /** + * @deprecated Please use driver model instead * Set an output GPIO's value. The GPIO must already be an output or * this function may have no effect. * @@ -91,25 +109,509 @@ int gpio_get_value(unsigned gpio); */ int gpio_set_value(unsigned gpio, int value); +/* State of a GPIO, as reported by get_function() */ +enum gpio_func_t { + GPIOF_INPUT = 0, + GPIOF_OUTPUT, + GPIOF_UNUSED, /* Not claimed */ + GPIOF_UNKNOWN, /* Not known */ + GPIOF_FUNC, /* Not used as a GPIO */ + + GPIOF_COUNT, +}; + +struct udevice; + +struct gpio_desc { + struct udevice *dev; /* Device, NULL for invalid GPIO */ + unsigned long flags; +#define GPIOD_REQUESTED (1 << 0) /* Requested/claimed */ +#define GPIOD_IS_OUT (1 << 1) /* GPIO is an output */ +#define GPIOD_IS_IN (1 << 2) /* GPIO is an output */ +#define GPIOD_ACTIVE_LOW (1 << 3) /* value has active low */ +#define GPIOD_IS_OUT_ACTIVE (1 << 4) /* set output active */ + + uint offset; /* GPIO offset within the device */ + /* + * We could consider adding the GPIO label in here. Possibly we could + * use this structure for internal GPIO information. + */ +}; + +/** + * dm_gpio_is_valid() - Check if a GPIO is gpio_is_valie + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return true if valid, false if not + */ +static inline bool dm_gpio_is_valid(struct gpio_desc *desc) +{ + return desc->dev != NULL; +} + /** + * gpio_get_status() - get the current GPIO status as a string + * + * Obtain the current GPIO status as a string which can be presented to the + * user. A typical string is: + * + * "b4: in: 1 [x] sdmmc_cd" + * + * which means this is GPIO bank b, offset 4, currently set to input, current + * value 1, [x] means that it is requested and the owner is 'sdmmc_cd' + * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * + * @dev: Device to check + * @offset: Offset of device GPIO to check + * @buf: Place to put string + * @buffsize: Size of string including \0 + */ +int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize); + +/** + * gpio_get_function() - get the current function for a GPIO pin + * + * Note this returns GPIOF_UNUSED if the GPIO is not requested. + * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * + * @dev: Device to check + * @offset: Offset of device GPIO to check + * @namep: If non-NULL, this is set to the nane given when the GPIO + * was requested, or -1 if it has not been requested + * @return -ENODATA if the driver returned an unknown function, + * -ENODEV if the device is not active, -EINVAL if the offset is invalid. + * GPIOF_UNUSED if the GPIO has not been requested. Otherwise returns the + * function from enum gpio_func_t. + */ +int gpio_get_function(struct udevice *dev, int offset, const char **namep); + +/** + * gpio_get_raw_function() - get the current raw function for a GPIO pin + * + * Note this does not return GPIOF_UNUSED - it will always return the GPIO + * driver's view of a pin function, even if it is not correctly set up. + * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * + * @dev: Device to check + * @offset: Offset of device GPIO to check + * @namep: If non-NULL, this is set to the nane given when the GPIO + * was requested, or -1 if it has not been requested + * @return -ENODATA if the driver returned an unknown function, + * -ENODEV if the device is not active, -EINVAL if the offset is invalid. + * Otherwise returns the function from enum gpio_func_t. + */ +int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep); + +/** + * gpio_requestf() - request a GPIO using a format string for the owner + * + * This is a helper function for gpio_request(). It allows you to provide + * a printf()-format string for the GPIO owner. It calls gpio_request() with + * the string that is created + */ +int gpio_requestf(unsigned gpio, const char *fmt, ...) + __attribute__ ((format (__printf__, 2, 3))); + +struct fdtdec_phandle_args; + +/** + * struct struct dm_gpio_ops - Driver model GPIO operations + * + * Refer to functions above for description. These function largely copy + * the old API. + * + * This is trying to be close to Linux GPIO API. Once the U-Boot uses the + * new DM GPIO API, this should be really easy to flip over to the Linux + * GPIO API-alike interface. + * + * Also it would be useful to standardise additional functions like + * pullup, slew rate and drive strength. + * + * gpio_request)( and gpio_free() are optional - if NULL then they will + * not be called. + * + * Note that @offset is the offset from the base GPIO of the device. So + * offset 0 is the device's first GPIO and offset o-1 is the last GPIO, + * where o is the number of GPIO lines controlled by the device. A device + * is typically used to control a single bank of GPIOs. Within complex + * SoCs there may be many banks and therefore many devices all referring + * to the different IO addresses within the SoC. + * + * The uclass combines all GPIO devices together to provide a consistent + * numbering from 0 to n-1, where n is the number of GPIOs in total across + * all devices. Be careful not to confuse offset with gpio in the parameters. + */ +struct dm_gpio_ops { + int (*request)(struct udevice *dev, unsigned offset, const char *label); + int (*free)(struct udevice *dev, unsigned offset); + int (*direction_input)(struct udevice *dev, unsigned offset); + int (*direction_output)(struct udevice *dev, unsigned offset, + int value); + int (*get_value)(struct udevice *dev, unsigned offset); + int (*set_value)(struct udevice *dev, unsigned offset, int value); + /** + * get_function() Get the GPIO function + * + * @dev: Device to check + * @offset: GPIO offset within that device + * @return current function - GPIOF_... + */ + int (*get_function)(struct udevice *dev, unsigned offset); + + /** + * xlate() - Translate phandle arguments into a GPIO description + * + * This function should set up the fields in desc according to the + * information in the arguments. The uclass will have set up: + * + * @desc->dev to @dev + * @desc->flags to 0 + * @desc->offset to the value of the first argument in args, if any, + * otherwise -1 (which is invalid) + * + * This method is optional so if the above defaults suit it can be + * omitted. Typical behaviour is to set up the GPIOD_ACTIVE_LOW flag + * in desc->flags. + * + * Note that @dev is passed in as a parameter to follow driver model + * uclass conventions, even though it is already available as + * desc->dev. + * + * @dev: GPIO device + * @desc: Place to put GPIO description + * @args: Arguments provided in descripion + * @return 0 if OK, -ve on error + */ + int (*xlate)(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args); +}; + +/** + * struct gpio_dev_priv - information about a device used by the uclass + * + * The uclass combines all active GPIO devices into a unified numbering + * scheme. To do this it maintains some private information about each + * device. + * + * To implement driver model support in your GPIO driver, add a probe + * handler, and set @gpio_count and @bank_name correctly in that handler. + * This tells the uclass the name of the GPIO bank and the number of GPIOs + * it contains. + * + * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called + * 'A0', 'A1', etc. + * @gpio_count: Number of GPIOs in this device + * @gpio_base: Base GPIO number for this device. For the first active device + * this will be 0; the numbering for others will follow sequentially so that + * @gpio_base for device 1 will equal the number of GPIOs in device 0. + * @name: Array of pointers to the name for each GPIO in this bank. The + * value of the pointer will be NULL if the GPIO has not been claimed. + */ +struct gpio_dev_priv { + const char *bank_name; + unsigned gpio_count; + unsigned gpio_base; + char **name; +}; + +/* Access the GPIO operations for a device */ +#define gpio_get_ops(dev) ((struct dm_gpio_ops *)(dev)->driver->ops) + +/** + * gpio_get_bank_info - Return information about a GPIO bank/device + * + * This looks up a device and returns both its GPIO base name and the number + * of GPIOs it controls. + * + * @dev: Device to look up + * @offset_count: Returns number of GPIOs within this bank + * @return bank name of this device + */ +const char *gpio_get_bank_info(struct udevice *dev, int *offset_count); + +/** + * gpio_lookup_name - Look up a GPIO name and return its details + * + * This is used to convert a named GPIO into a device, offset and GPIO + * number. + * + * @name: GPIO name to look up + * @devp: Returns pointer to device which contains this GPIO + * @offsetp: Returns the offset number within this device + * @gpiop: Returns the absolute GPIO number, numbered from 0 + */ +int gpio_lookup_name(const char *name, struct udevice **devp, + unsigned int *offsetp, unsigned int *gpiop); + +/** + * get_gpios() - Turn the values of a list of GPIOs into an integer + * + * This puts the value of the first GPIO into bit 0, the second into bit 1, + * etc. then returns the resulting integer. + * + * @gpio_list: List of GPIOs to collect + * @return resulting integer value + */ +unsigned gpio_get_values_as_int(const int *gpio_list); + +/** + * gpio_request_by_name() - Locate and request a GPIO by name + * + * This operates by looking up the given list name in the device (device + * tree property) and requesting the GPIO for use. The property must exist + * in @dev's node. + * + * Use @flags to specify whether the GPIO should be an input or output. In + * principle this can also come from the device tree binding but most + * bindings don't provide this information. Specifically, when the GPIO uclass + * calls the xlate() method, it can return default flags, which are then + * ORed with this @flags. + * + * If we find that requesting the GPIO is not always needed we could add a + * new function or a new GPIOD_NO_REQUEST flag. + * + * At present driver model has no reference counting so if one device + * requests a GPIO which subsequently is unbound, the @desc->dev pointer + * will be invalid. However this will only happen if the GPIO device is + * unbound, not if it is removed, so this seems like a reasonable limitation + * for now. There is no real use case for unbinding drivers in normal + * operation. + * + * The device tree binding is doc/device-tree-bindings/gpio/gpio.txt in + * generate terms and each specific device may add additional details in + * a binding file in the same directory. + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @index: Index number of the GPIO in that list use request (0=first) + * @desc: Returns GPIO description information. If there is no such + * GPIO, dev->dev will be NULL. + * @flags: Indicates the GPIO input/output settings (GPIOD_...) + * @return 0 if OK, -ENOENT if the GPIO does not exist, -EINVAL if there is + * something wrong with the list, or other -ve for another error (e.g. + * -EBUSY if a GPIO was already requested) + */ +int gpio_request_by_name(struct udevice *dev, const char *list_name, + int index, struct gpio_desc *desc, int flags); + +/** + * gpio_request_list_by_name() - Request a list of GPIOs + * + * Reads all the GPIOs from a list and requetss them. See + * gpio_request_by_name() for additional details. Lists should not be + * misused to hold unrelated or optional GPIOs. They should only be used + * for things like parallel data lines. A zero phandle terminates the list + * the list. + * + * This function will either succeed, and request all GPIOs in the list, or + * fail and request none (it will free already-requested GPIOs in case of + * an error part-way through). + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @desc_list: Returns a list of GPIO description information + * @max_count: Maximum number of GPIOs to return (@desc_list must be at least + * this big) + * @flags: Indicates the GPIO input/output settings (GPIOD_...) + * @return number of GPIOs requested, or -ve on error + */ +int gpio_request_list_by_name(struct udevice *dev, const char *list_name, + struct gpio_desc *desc_list, int max_count, + int flags); + +/** + * gpio_get_list_count() - Returns the number of GPIOs in a list + * + * Counts the GPIOs in a list. See gpio_request_by_name() for additional + * details. + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @return number of GPIOs (0 for an empty property) or -ENOENT if the list + * does not exist + */ +int gpio_get_list_count(struct udevice *dev, const char *list_name); + +/** + * gpio_request_by_name_nodev() - request GPIOs without a device + * + * This is a version of gpio_request_list_by_name() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_request_by_name_nodev(const void *blob, int node, + const char *list_name, + int index, struct gpio_desc *desc, int flags); + +/** + * gpio_request_list_by_name_nodev() - request GPIOs without a device + * + * This is a version of gpio_request_list_by_name() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_request_list_by_name_nodev(const void *blob, int node, + const char *list_name, + struct gpio_desc *desc_list, int max_count, + int flags); + +/** + * dm_gpio_free() - Free a single GPIO + * + * This frees a single GPIOs previously returned from gpio_request_by_name(). + * + * @dev: Device which requested the GPIO + * @desc: GPIO to free + * @return 0 if OK, -ve on error + */ +int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc); + +/** + * gpio_free_list() - Free a list of GPIOs + * + * This frees a list of GPIOs previously returned from + * gpio_request_list_by_name(). + * + * @dev: Device which requested the GPIOs + * @desc: List of GPIOs to free + * @count: Number of GPIOs in the list + * @return 0 if OK, -ve on error + */ +int gpio_free_list(struct udevice *dev, struct gpio_desc *desc, int count); + +/** + * gpio_free_list_nodev() - free GPIOs without a device + * + * This is a version of gpio_free_list() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_free_list_nodev(struct gpio_desc *desc, int count); + +/** + * dm_gpio_get_value() - Get the value of a GPIO + * + * This is the driver model version of the existing gpio_get_value() function + * and should be used instead of that. + * + * For now, these functions have a dm_ prefix since they conflict with + * existing names. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return GPIO value (0 for inactive, 1 for active) or -ve on error + */ +int dm_gpio_get_value(struct gpio_desc *desc); + +int dm_gpio_set_value(struct gpio_desc *desc, int value); + +/** + * dm_gpio_set_dir() - Set the direction for a GPIO + * + * This sets up the direction according tot the provided flags. It will do + * nothing unless the direction is actually specified. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return 0 if OK, -ve on error + */ +int dm_gpio_set_dir(struct gpio_desc *desc); + +/** + * dm_gpio_set_dir_flags() - Set direction using specific flags + * + * This is like dm_gpio_set_dir() except that the flags value is provided + * instead of being used from desc->flags. This is needed because in many + * cases the GPIO description does not include direction information. + * Note that desc->flags is updated by this function. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @flags: New flags to use + * @return 0 if OK, -ve on error, in which case desc->flags is not updated + */ +int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); + +/** + * gpio_get_number() - Get the global GPIO number of a GPIO + * + * This should only be used for debugging or interest. It returns the nummber + * that should be used for gpio_get_value() etc. to access this GPIO. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return GPIO number, or -ve if not found + */ +int gpio_get_number(struct gpio_desc *desc); + +/** + * @deprecated Please use driver model instead * Request a GPIO and configure it * @param gpios pointer to array of gpio defs * @param count number of GPIOs to set up */ -int gpio_request_one(unsigned gpio, enum gpio_flags flags, const char *label); +static inline int gpio_request_one(unsigned int gpio, enum gpio_flags flags, + const char *label) +{ + int ret; + + ret = gpio_request(gpio, label); + if (ret) + return ret; + + if (flags == GPIOFLAG_INPUT) + gpio_direction_input(gpio); + else if (flags == GPIOFLAG_OUTPUT_INIT_LOW) + gpio_direction_output(gpio, 0); + else if (flags == GPIOFLAG_OUTPUT_INIT_HIGH) + gpio_direction_output(gpio, 1); + + return ret; +} /** * Request a set of GPIOs and configure them * @param gpios pointer to array of gpio defs * @param count number of GPIOs to set up */ -int gpio_request_array(const struct gpio *gpios, int count); +static inline int gpio_request_array(const struct gpio *gpios, int count) +{ + int ret; + int i; + + for (i = 0; i < count; i++) { + ret = gpio_request_one(gpios[i].gpio, gpios[i].flags, + gpios[i].label); + if (ret) { + printf("Failed to request GPIO%d (%u of %u): %d\n", + gpios[i].gpio, i, count, ret); + goto error; + } + } + return 0; + +error: + while (--i >= 0) + gpio_free(gpios[i].gpio); + + return ret; +} /** + * @deprecated Please use driver model instead * Release a set of GPIOs * @param gpios pointer to array of gpio defs * @param count number of GPIOs to set up */ -int gpio_free_array(const struct gpio *gpios, int count); +static inline int gpio_free_array(const struct gpio *gpios, int count) +{ + int ret = 0; + int i; + + for (i = 0; i < count; i++) + ret |= gpio_free(gpios[i].gpio); + return ret; +} #endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 7e1eb4bf5e..458952fb58 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -63,28 +63,16 @@ extern char __image_copy_end[]; extern void _start(void); /* - * ARM needs to use offsets for symbols, since the values of some symbols - * are not resolved prior to relocation (and are just 0). Maybe this can be - * resolved, or maybe other architectures are similar, iwc this should be - * promoted to an architecture option. + * ARM defines its symbols as char[]. Other arches define them as ulongs. */ #ifdef CONFIG_ARM -#define CONFIG_SYS_SYM_OFFSETS -#endif - -#ifdef CONFIG_SYS_SYM_OFFSETS -/* Start/end of the relocation entries, as an offset from _start */ -extern ulong _rel_dyn_start_ofs; -extern ulong _rel_dyn_end_ofs; - -/* End of the region to be relocated, as an offset form _start */ -extern ulong _image_copy_end_ofs; -extern ulong _bss_start_ofs; /* BSS start relative to _start */ -extern ulong _bss_end_ofs; /* BSS end relative to _start */ -extern ulong _end_ofs; /* end of image relative to _start */ - -extern ulong _TEXT_BASE; /* code start */ +extern char __bss_start[]; +extern char __bss_end[]; +extern char __image_copy_start[]; +extern char __image_copy_end[]; +extern char __rel_dyn_start[]; +extern char __rel_dyn_end[]; #else /* don't use offsets: */ diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 29e0438ba4..aef39d7884 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -37,7 +37,7 @@ typedef struct bd_info { unsigned long bi_dsp_freq; /* dsp core frequency */ unsigned long bi_ddr_freq; /* ddr frequency */ #endif -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif @@ -66,10 +66,8 @@ typedef struct bd_info { unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ - defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || \ @@ -81,9 +79,6 @@ typedef struct bd_info { unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ #endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif #ifdef CONFIG_HAS_ETH1 unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ @@ -109,9 +104,6 @@ typedef struct bd_info { unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif -#if defined(CONFIG_NX823) - unsigned char bi_sernum[8]; -#endif #if defined(CONFIG_4xx) #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) diff --git a/include/at45.h b/include/at45.h deleted file mode 100644 index e7e3711e3b..0000000000 --- a/include/at45.h +++ /dev/null @@ -1,69 +0,0 @@ - -#ifndef _AT45_H_ -#define _AT45_H_ -#ifdef CONFIG_DATAFLASH_MMC_SELECT -extern void AT91F_SelectMMC(void); -extern void AT91F_SelectSPI(void); -extern int AT91F_GetMuxStatus(void); -#endif -extern void AT91F_SpiInit(void); -extern void AT91F_SpiEnable(int cs); -extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ); -extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress); -extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus ( - AT91PS_DataflashDesc pDesc); -extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady ( - AT91PS_DataflashDesc pDataFlashDesc, - unsigned int timeout); -extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ); -extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite); -extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page); -extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ); -extern AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page); -extern AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block); -extern AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ); -extern AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size); -extern AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ); -extern int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer); -extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc); - -#endif diff --git a/include/at91rm9200_i2c.h b/include/at91rm9200_i2c.h deleted file mode 100644 index 486660638c..0000000000 --- a/include/at91rm9200_i2c.h +++ /dev/null @@ -1,114 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* ATMEL Microcontroller Software Support - ROUSSET - */ -/* ---------------------------------------------------------------------------- */ -/* The software is delivered "AS IS" without warranty or condition of any */ -/* kind, either express, implied or statutory. This includes without */ -/* limitation any warranty or condition with respect to merchantability or */ -/* fitness for any particular purpose, or against the infringements of */ -/* intellectual property rights of others. */ -/* ---------------------------------------------------------------------------- */ -/* File Name : at91rm9200_i2c.h */ -/* Object : AT91RM9200 / TWI definitions */ -/* Generated : AT91 SW Application Group 12/03/2002 (10:48:02) */ -/* */ -/* ---------------------------------------------------------------------------- */ - -#ifndef AT91RM9200_TWI_H -#define AT91RM9200_TWI_H - -/* ******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ******************************************************************************/ -#ifndef __ASSEMBLY__ - -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; /* Control Register */ - AT91_REG TWI_MMR; /* Master Mode Register */ - AT91_REG TWI_SMR; /* Slave Mode Register */ - AT91_REG TWI_IADR; /* Internal Address Register */ - AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ - AT91_REG Reserved0[3]; - AT91_REG TWI_SR; /* Status Register */ - AT91_REG TWI_IER; /* Interrupt Enable Register */ - AT91_REG TWI_IDR; /* Interrupt Disable Register */ - AT91_REG TWI_IMR; /* Interrupt Mask Register */ - AT91_REG TWI_RHR; /* Receive Holding Register */ - AT91_REG TWI_THR; /* Transmit Holding Register */ - AT91_REG Reserved1[50]; - AT91_REG TWI_RPR; /* Receive Pointer Register */ - AT91_REG TWI_RCR; /* Receive Counter Register */ - AT91_REG TWI_TPR; /* Transmit Pointer Register */ - AT91_REG TWI_TCR; /* Transmit Counter Register */ - AT91_REG TWI_RNPR; /* Receive Next Pointer Register */ - AT91_REG TWI_RNCR; /* Receive Next Counter Register */ - AT91_REG TWI_TNPR; /* Transmit Next Pointer Register */ - AT91_REG TWI_TNCR; /* Transmit Next Counter Register */ - AT91_REG TWI_PTCR; /* PDC Transfer Control Register */ - AT91_REG TWI_PTSR; /* PDC Transfer Status Register */ -} AT91S_TWI, *AT91PS_TWI; - -#endif - -/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ -#define AT91C_TWI_START (0x1 << 0) /* (TWI) Send a START Condition */ -#define AT91C_TWI_STOP (0x1 << 1) /* (TWI) Send a STOP Condition */ -#define AT91C_TWI_MSEN (0x1 << 2) /* (TWI) TWI Master Transfer Enabled */ -#define AT91C_TWI_MSDIS (0x1 << 3) /* (TWI) TWI Master Transfer Disabled */ -#define AT91C_TWI_SVEN (0x1 << 4) /* (TWI) TWI Slave Transfer Enabled */ -#define AT91C_TWI_SVDIS (0x1 << 5) /* (TWI) TWI Slave Transfer Disabled */ -#define AT91C_TWI_SWRST (0x1 << 7) /* (TWI) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ -#define AT91C_TWI_IADRSZ (0x3 << 8) /* (TWI) Internal Device Address Size */ -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) /* (TWI) No internal device address */ -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) /* (TWI) One-byte internal device address */ -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) /* (TWI) Two-byte internal device address */ -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) /* (TWI) Three-byte internal device address */ -#define AT91C_TWI_MREAD (0x1 << 12) /* (TWI) Master Read Direction */ -#define AT91C_TWI_DADR (0x7F << 6) /* (TWI) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */ -#define AT91C_TWI_SADR (0x7F << 16) /* (TWI) Slave Device Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ -#define AT91C_TWI_CLDIV (0xFF << 0) /* (TWI) Clock Low Divider */ -#define AT91C_TWI_CHDIV (0xFF << 8) /* (TWI) Clock High Divider */ -#define AT91C_TWI_CKDIV (0x7 << 16) /* (TWI) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ -#define AT91C_TWI_TXCOMP (0x1 << 0) /* (TWI) Transmission Completed */ -#define AT91C_TWI_RXRDY (0x1 << 1) /* (TWI) Receive holding register ReaDY */ -#define AT91C_TWI_TXRDY (0x1 << 2) /* (TWI) Transmit holding register ReaDY*/ -#define AT91C_TWI_SVREAD (0x1 << 3) /* (TWI) Slave Read */ -#define AT91C_TWI_SVACC (0x1 << 4) /* (TWI) Slave Access */ -#define AT91C_TWI_GCACC (0x1 << 5) /* (TWI) General Call Access */ -#define AT91C_TWI_OVRE (0x1 << 6) /* (TWI) Overrun Error */ -#define AT91C_TWI_UNRE (0x1 << 7) /* (TWI) Underrun Error */ -#define AT91C_TWI_NACK (0x1 << 8) /* (TWI) Not Acknowledged */ -#define AT91C_TWI_ARBLST (0x1 << 9) /* (TWI) Arbitration Lost */ -/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ -/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */ -/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ - -/* - i2c Support for Atmel's AT91RM9200 Two-Wire Interface - - (c) Rick Bronson - - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef AT91_I2C_H -#define AT91_I2C_H - -#define AT91C_TWI_CLOCK 100000 -#define AT91C_TWI_SCLOCK (10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK) -#define AT91C_TWI_CKDIV1 (2 << 16) /* TWI clock divider. NOTE: see Errata #22 */ - -#if (AT91C_TWI_SCLOCK % 10) >= 5 -#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5) -#else -#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6) -#endif -#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2) - -#define AT91C_EEPROM_I2C_ADDRESS (0x50 << 16) - -#endif /* __ASSEMBLY__ */ -#endif /* AT91RM9200_TWI_H */ diff --git a/include/at91rm9200_net.h b/include/at91rm9200_net.h deleted file mode 100644 index 831cb1e260..0000000000 --- a/include/at91rm9200_net.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Ethernet: An implementation of the Ethernet Device Driver suite for the - * uClinux 2.0.38 operating system. This Driver has been developed - * for AT75C220 board. - * - * NOTE: The driver is implemented for one MAC - * - * Version: @(#)at91rm9200_net.h 1.0.0 01/10/2001 - * - * Authors: Lineo Inc - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91RM9200_ETHERNET -#define AT91RM9200_ETHERNET - -#include -#include -#include - -#define ETHERNET_ADDRESS_SIZE 6 - -typedef unsigned char UCHAR; - -/* Interface to drive the physical layer */ -typedef struct _AT91S_PhyOps -{ - unsigned char (*Init)(AT91S_EMAC *pmac); - unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac); - unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac); - unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *); - -} AT91S_PhyOps,*AT91PS_PhyOps; - - -#define EMAC_DESC_DONE 0x00000001 /* ownership bit */ -#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ - -/****************** function prototypes **********************/ - -/* MII functions */ -void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac); -void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac); -UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput); -UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput); -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops); - -#endif /* AT91RM9200_ETHERNET */ diff --git a/include/atmel_mci.h b/include/atmel_mci.h index 090574d8c2..de2414806b 100644 --- a/include/atmel_mci.h +++ b/include/atmel_mci.h @@ -36,7 +36,9 @@ typedef struct atmel_mci { u32 ier; /* 0x44 */ u32 idr; /* 0x48 */ u32 imr; /* 0x4c */ - u32 reserved[43]; + u32 dma; /* 0x50 */ + u32 cfg; /* 0x54 */ + u32 reserved[41]; u32 version; } atmel_mci_t; @@ -67,6 +69,10 @@ typedef struct atmel_mci { #define MMCI_PDCPADV_SIZE 1 #define MMCI_PDCMODE_OFFSET 15 #define MMCI_PDCMODE_SIZE 1 +/* MCI IP version >= 0x500, MR bit 16 used for CLKODD */ +#define MMCI_CLKODD_OFFSET 16 +#define MMCI_CLKODD_SIZE 1 +/* MCI IP version < 0x200, MR higher 16bits for BLKLEN */ #define MMCI_BLKLEN_OFFSET 16 #define MMCI_BLKLEN_SIZE 16 @@ -185,6 +191,16 @@ typedef struct atmel_mci { #define MMCI_TRTYP_MULTI_BLOCK 1 #define MMCI_TRTYP_STREAM 2 +/* Bitfields in CFG */ +#define MMCI_FIFOMODE_OFFSET 0 +#define MMCI_FIFOMODE_SIZE 1 +#define MMCI_FERRCTRL_OFFSET 4 +#define MMCI_FERRCTRL_SIZE 1 +#define MMCI_HSMODE_OFFSET 8 +#define MMCI_HSMODE_SIZE 1 +#define MMCI_LSYNC_OFFSET 12 +#define MMCI_LSYNC_SIZE 1 + /* Bit manipulation macros */ #define MMCI_BIT(name) \ (1 << MMCI_##name##_OFFSET) diff --git a/include/autoboot.h b/include/autoboot.h new file mode 100644 index 0000000000..3a9059a0b9 --- /dev/null +++ b/include/autoboot.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AUTOBOOT_H +#define __AUTOBOOT_H + +#ifdef CONFIG_BOOTDELAY +/** + * bootdelay_process() - process the bootd delay + * + * Process the boot delay, boot limit, then get the value of either + * bootcmd, failbootcmd or altbootcmd depending on the current state. + * Return this command so it can be executed. + * + * @return command to executed + */ +const char *bootdelay_process(void); + +/** + * autoboot_command() - run the autoboot command + * + * If enabled, run the autoboot command returned from bootdelay_process(). + * Also do the CONFIG_MENUKEY processing if enabled. + * + * @cmd: Command to run + */ +void autoboot_command(const char *cmd); +#else +static inline const char *bootdelay_process(void) +{ + return NULL; +} + +static inline void autoboot_command(const char *s) +{ +} +#endif + +#endif diff --git a/include/axp152.h b/include/axp152.h new file mode 100644 index 0000000000..3e5ccbd0d8 --- /dev/null +++ b/include/axp152.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ +int axp152_set_dcdc2(int mvolt); +int axp152_set_dcdc3(int mvolt); +int axp152_set_dcdc4(int mvolt); +int axp152_set_ldo2(int mvolt); +int axp152_init(void); diff --git a/include/axp209.h b/include/axp209.h new file mode 100644 index 0000000000..043624953a --- /dev/null +++ b/include/axp209.h @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define AXP_GPIO + +extern int axp209_set_dcdc2(int mvolt); +extern int axp209_set_dcdc3(int mvolt); +extern int axp209_set_ldo2(int mvolt); +extern int axp209_set_ldo3(int mvolt); +extern int axp209_set_ldo4(int mvolt); +extern int axp209_init(void); +extern int axp209_poweron_by_dc(void); +extern int axp209_power_button(void); + +extern int axp_gpio_direction_input(unsigned int pin); +extern int axp_gpio_direction_output(unsigned int pin, unsigned int val); +extern int axp_gpio_get_value(unsigned int pin); +extern int axp_gpio_set_value(unsigned int pin, unsigned int val); diff --git a/include/axp221.h b/include/axp221.h new file mode 100644 index 0000000000..a20e25c2f8 --- /dev/null +++ b/include/axp221.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2013 Oliver Schinagl + * + * X-Powers AXP221 Power Management IC driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define AXP221_CHIP_ADDR 0x68 +#define AXP221_CTRL_ADDR 0x3e +#define AXP221_INIT_DATA 0x3e + +#define AXP223_DEVICE_ADDR 0x3a3 +#define AXP223_RUNTIME_ADDR 0x2d + +/* Page 0 addresses */ +#define AXP221_CHIP_ID 0x03 +#define AXP221_OUTPUT_CTRL1 0x10 +#define AXP221_OUTPUT_CTRL1_DCDC0_EN (1 << 0) +#define AXP221_OUTPUT_CTRL1_DCDC1_EN (1 << 1) +#define AXP221_OUTPUT_CTRL1_DCDC2_EN (1 << 2) +#define AXP221_OUTPUT_CTRL1_DCDC3_EN (1 << 3) +#define AXP221_OUTPUT_CTRL1_DCDC4_EN (1 << 4) +#define AXP221_OUTPUT_CTRL1_DCDC5_EN (1 << 5) +#define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6) +#define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7) +#define AXP221_OUTPUT_CTRL2 0x12 +#define AXP221_OUTPUT_CTRL2_ELDO1_EN (1 << 0) +#define AXP221_OUTPUT_CTRL2_ELDO2_EN (1 << 1) +#define AXP221_OUTPUT_CTRL2_ELDO3_EN (1 << 2) +#define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3) +#define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4) +#define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5) +#define AXP221_OUTPUT_CTRL2_DLDO4_EN (1 << 6) +#define AXP221_OUTPUT_CTRL2_DCDC1SW_EN (1 << 7) +#define AXP221_OUTPUT_CTRL3 0x13 +#define AXP221_OUTPUT_CTRL3_ALDO3_EN (1 << 7) +#define AXP221_DLDO1_CTRL 0x15 +#define AXP221_DLDO2_CTRL 0x16 +#define AXP221_DLDO3_CTRL 0x17 +#define AXP221_DLDO4_CTRL 0x18 +#define AXP221_ELDO1_CTRL 0x19 +#define AXP221_ELDO2_CTRL 0x1a +#define AXP221_ELDO3_CTRL 0x1b +#define AXP221_DCDC1_CTRL 0x21 +#define AXP221_DCDC2_CTRL 0x22 +#define AXP221_DCDC3_CTRL 0x23 +#define AXP221_DCDC4_CTRL 0x24 +#define AXP221_DCDC5_CTRL 0x25 +#define AXP221_ALDO1_CTRL 0x28 +#define AXP221_ALDO2_CTRL 0x29 +#define AXP221_ALDO3_CTRL 0x2a +#define AXP221_VBUS_IPSOUT 0x30 +#define AXP221_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP221_MISC_CTRL 0x8f +#define AXP221_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +#define AXP221_PAGE 0xff + +/* Page 1 addresses */ +#define AXP221_SID 0x20 + +/* We support drivebus control */ +#define AXP_DRIVEBUS + +int axp221_set_dcdc1(unsigned int mvolt); +int axp221_set_dcdc2(unsigned int mvolt); +int axp221_set_dcdc3(unsigned int mvolt); +int axp221_set_dcdc4(unsigned int mvolt); +int axp221_set_dcdc5(unsigned int mvolt); +int axp221_set_dldo1(unsigned int mvolt); +int axp221_set_dldo2(unsigned int mvolt); +int axp221_set_dldo3(unsigned int mvolt); +int axp221_set_dldo4(unsigned int mvolt); +int axp221_set_aldo1(unsigned int mvolt); +int axp221_set_aldo2(unsigned int mvolt); +int axp221_set_aldo3(unsigned int mvolt); +int axp221_set_eldo(int eldo_num, unsigned int mvolt); +int axp221_init(void); +int axp221_get_sid(unsigned int *sid); +int axp_drivebus_enable(void); +int axp_drivebus_disable(void); diff --git a/include/bcm5221.h b/include/bcm5221.h deleted file mode 100644 index 4719389cfd..0000000000 --- a/include/bcm5221.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Broadcom BCM5221 Ethernet PHY - * - * (C) Copyright 2005 REA Elektronik GmbH - * Anders Larsen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define BCM5221_BMCR 0 /* Basic Mode Control Register */ -#define BCM5221_BMSR 1 /* Basic Mode Status Register */ -#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */ -#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */ -#define BCM5221_ANAR 4 /* Auto-negotiation Advertisement Register */ -#define BCM5221_ANLPAR 5 /* Auto-negotiation Link Partner Ability Register */ -#define BCM5221_ANER 6 /* Auto-negotiation Expansion Register */ -#define BCM5221_ACSR 24 /* Auxiliary Control/Status Register */ -#define BCM5221_INTR 26 /* Interrupt Register */ - -/* --Bit definitions: BCM5221_BMCR */ -#define BCM5221_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ -#define BCM5221_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */ -#define BCM5221_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */ -#define BCM5221_AUTONEG (1 << 12) -#define BCM5221_POWER_DOWN (1 << 11) -#define BCM5221_ISOLATE (1 << 10) -#define BCM5221_RESTART_AUTONEG (1 << 9) -#define BCM5221_DUPLEX_MODE (1 << 8) -#define BCM5221_COLLISION_TEST (1 << 7) - -/*--Bit definitions: BCM5221_BMSR */ -#define BCM5221_100BASE_T4 (1 << 15) -#define BCM5221_100BASE_TX_FD (1 << 14) -#define BCM5221_100BASE_TX_HD (1 << 13) -#define BCM5221_10BASE_T_FD (1 << 12) -#define BCM5221_10BASE_T_HD (1 << 11) -#define BCM5221_MF_PREAMB_SUPPR (1 << 6) -#define BCM5221_AUTONEG_COMP (1 << 5) -#define BCM5221_REMOTE_FAULT (1 << 4) -#define BCM5221_AUTONEG_ABILITY (1 << 3) -#define BCM5221_LINK_STATUS (1 << 2) -#define BCM5221_JABBER_DETECT (1 << 1) -#define BCM5221_EXTEND_CAPAB (1 << 0) - -/*--definitions: BCM5221_PHYID1 */ -#define BCM5221_PHYID1_OUI 0x1018 -#define BCM5221_LSB_MASK 0x3F - -/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */ -#define BCM5221_NP (1 << 15) -#define BCM5221_ACK (1 << 14) -#define BCM5221_RF (1 << 13) -#define BCM5221_FCS (1 << 10) -#define BCM5221_T4 (1 << 9) -#define BCM5221_TX_FDX (1 << 8) -#define BCM5221_TX_HDX (1 << 7) -#define BCM5221_10_FDX (1 << 6) -#define BCM5221_10_HDX (1 << 5) -#define BCM5221_AN_IEEE_802_3 0x0001 - -/*--Bit definitions: BCM5221_ANER */ -#define BCM5221_PDF (1 << 4) -#define BCM5221_LP_NP_ABLE (1 << 3) -#define BCM5221_NP_ABLE (1 << 2) -#define BCM5221_PAGE_RX (1 << 1) -#define BCM5221_LP_AN_ABLE (1 << 0) - -/*--Bit definitions: BCM5221_ACSR */ -#define BCM5221_100 (1 << 1) -#define BCM5221_FDX (1 << 0) - -/*--Bit definitions: BCM5221_INTR */ -#define BCM5221_FDX_LED (1 << 15) -#define BCM5221_INTR_ENABLE (1 << 14) -#define BCM5221_FDX_MASK (1 << 11) -#define BCM5221_SPD_MASK (1 << 10) -#define BCM5221_LINK_MASK (1 << 9) -#define BCM5221_INTR_MASK (1 << 8) -#define BCM5221_FDX_CHG (1 << 3) -#define BCM5221_SPD_CHG (1 << 2) -#define BCM5221_LINK_CHG (1 << 1) -#define BCM5221_INTR_STATUS (1 << 0) - -/****************** function prototypes **********************/ -unsigned int bcm5221_IsPhyConnected(AT91PS_EMAC p_mac); -unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac); -unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status); -unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac); diff --git a/include/bios_emul.h b/include/bios_emul.h new file mode 100644 index 0000000000..3643b82b3a --- /dev/null +++ b/include/bios_emul.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 1996-1999 SciTech Software, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _BIOS_EMUL_H +#define _BIOS_EMUL_H + +/* Include the register header directly here */ +#include "../drivers/bios_emulator/include/x86emu/regs.h" +#include + +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +vgaInfo - VGA BIOS information structure +biosmem_base - Base of the BIOS image +biosmem_limit - Limit of the BIOS image +busmem_base - Base of the VGA bus memory +****************************************************************************/ +typedef struct { + int function; + int device; + int bus; + u32 VendorID; + u32 DeviceID; + pci_dev_t pcidev; + void *BIOSImage; + u32 BIOSImageLen; + u8 LowMem[1536]; +} BE_VGAInfo; + +struct vbe_mode_info; + +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp); + +/* Run a BIOS ROM natively (only supported on x86 machines) */ +void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode, + struct vbe_mode_info *mode_info); + +/** + * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS + * + * This installs an interrupt handler that the BIOS will call when needed. + * + * @intnum: Interrupt number to install a handler for + * @int_handler_func: Function to call to handle interrupt + */ +void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void)); + +void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)); + +int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo); + +int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info); + +#endif diff --git a/include/bitfield.h b/include/bitfield.h new file mode 100644 index 0000000000..ec4815c8e0 --- /dev/null +++ b/include/bitfield.h @@ -0,0 +1,58 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Bitfield operations + * + * These are generic bitfield operations which allow manipulation of variable + * width bitfields within a word. One use of this would be to use data tables + * to determine how to reprogram fields within R/W hardware registers. + * + * Example: + * + * old_reg_val + * +--------+----+---+--+-----+----------+ + * | | | | | old | | + * +--------+----+---+--+-----+----------+ + * + * new_reg_val + * +--------+----+---+--+-----+----------+ + * | | | | | new | | + * +--------+----+---+--+-----+----------+ + * + * mask = bitfield_mask(10, 5); + * old = bitfield_extract(old_reg_val, 10, 5); + * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new); + * + * The numbers 10 and 5 could for example come from data + * tables which describe all bitfields in all registers. + */ + +#include + +/* Produces a mask of set bits covering a range of a uint value */ +static inline uint bitfield_mask(uint shift, uint width) +{ + return ((1 << width) - 1) << shift; +} + +/* Extract the value of a bitfield found within a given register value */ +static inline uint bitfield_extract(uint reg_val, uint shift, uint width) +{ + return (reg_val & bitfield_mask(shift, width)) >> shift; +} + +/* + * Replace the value of a bitfield found within a given register value + * Returns the newly modified uint value with the replaced field. + */ +static inline uint bitfield_replace(uint reg_val, uint shift, uint width, + uint bitfield_val) +{ + uint mask = bitfield_mask(shift, width); + + return (reg_val & ~mask) | (bitfield_val << shift); +} diff --git a/include/bootm.h b/include/bootm.h new file mode 100644 index 0000000000..6181488769 --- /dev/null +++ b/include/bootm.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOOTM_H +#define _BOOTM_H + +#include +#include + +#define BOOTM_ERR_RESET (-1) +#define BOOTM_ERR_OVERLAP (-2) +#define BOOTM_ERR_UNIMPLEMENTED (-3) + +/* + * Continue booting an OS image; caller already has: + * - copied image header to global variable `header' + * - checked header magic number, checksums (both header & image), + * - verified image architecture (PPC) and type (KERNEL or MULTI), + * - loaded (first part of) image to header load address, + * - disabled interrupts. + * + * @flag: Flags indicating what to do (BOOTM_STATE_...) + * @argc: Number of arguments. Note that the arguments are shifted down + * so that 0 is the first argument not processed by U-Boot, and + * argc is adjusted accordingly. This avoids confusion as to how + * many arguments are available for the OS. + * @images: Pointers to os/initrd/fdt + * @return 1 on error. On success the OS boots so this function does + * not return. + */ +typedef int boot_os_fn(int flag, int argc, char * const argv[], + bootm_headers_t *images); + +extern boot_os_fn do_bootm_linux; +int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +void lynxkdi_boot(image_header_t *hdr); + +boot_os_fn *bootm_os_get_boot_func(int os); + +int bootm_host_load_images(const void *fit, int cfg_noffset); + +int boot_selected_os(int argc, char * const argv[], int state, + bootm_headers_t *images, boot_os_fn *boot_fn); + +ulong bootm_disable_interrupts(void); + +/* This is a special function used by booti/bootz */ +int bootm_find_ramdisk_fdt(int flag, int argc, char * const argv[]); + +int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int states, bootm_headers_t *images, int boot_progress); + +void arch_preboot_os(void); + +/** + * bootm_decomp_image() - decompress the operating system + * + * @comp: Compression algorithm that is used (IH_COMP_...) + * @load: Destination load address in U-Boot memory + * @image_start Image start address (where we are decompressing from) + * @type: OS type (IH_OS_...) + * @load_bug: Place to decompress to + * @image_buf: Address to decompress from + * @image_len: Number of bytes in @image_buf to decompress + * @unc_len: Available space for decompression + * @return 0 if OK, -ve on error (BOOTM_ERR_...) + */ +int bootm_decomp_image(int comp, ulong load, ulong image_start, int type, + void *load_buf, void *image_buf, ulong image_len, + uint unc_len, ulong *load_end); + +#endif diff --git a/include/bootretry.h b/include/bootretry.h new file mode 100644 index 0000000000..2ecd7a48b0 --- /dev/null +++ b/include/bootretry.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOOTRETRY_H +#define __BOOTRETRY_H + +#ifdef CONFIG_BOOT_RETRY_TIME +/** + * bootretry_tstc_timeout() - ensure we get a keypress before timeout + * + * Check for a keypress repeatedly, resetting the watchdog each time. If a + * keypress is not received within the command timeout, return an error. + * + * @return 0 if a key is received in time, -ETIMEDOUT if not + */ +int bootretry_tstc_timeout(void); + +/** + * bootretry_init_cmd_timeout() - set up command timeout + * + * Get the required command timeout from the environment. + */ +void bootretry_init_cmd_timeout(void); + +/** + * bootretry_reset_cmd_timeout() - reset command timeout + * + * Reset the command timeout so that the user has a fresh start. This is + * typically used when input is received from the user. + */ +void bootretry_reset_cmd_timeout(void); + +/** bootretry_dont_retry() - Indicate that we should not retry the boot */ +void bootretry_dont_retry(void); +#else +static inline int bootretry_tstc_timeout(void) +{ + return 0; +} + +static inline void bootretry_init_cmd_timeout(void) +{ +} + +static inline void bootretry_reset_cmd_timeout(void) +{ +} + +static inline void bootretry_dont_retry(void) +{ +} + +#endif + +#endif diff --git a/include/bootstage.h b/include/bootstage.h index 25b4e07c7e..df13ab2f63 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -159,6 +159,9 @@ enum bootstage_id { /* Next 10 IDs used by BOOTSTAGE_SUB_... */ BOOTSTAGE_ID_FIT_RD_START = 120, /* Ramdisk stages */ + /* Next 10 IDs used by BOOTSTAGE_SUB_... */ + BOOTSTAGE_ID_FIT_SETUP_START = 130, /* x86 setup stages */ + BOOTSTAGE_ID_IDE_FIT_READ = 140, BOOTSTAGE_ID_IDE_FIT_READ_OK, @@ -353,6 +356,7 @@ static inline ulong bootstage_error(enum bootstage_id id) static inline ulong bootstage_mark_name(enum bootstage_id id, const char *name) { + show_boot_progress(id); return 0; } diff --git a/include/cli.h b/include/cli.h new file mode 100644 index 0000000000..6da7a4afdb --- /dev/null +++ b/include/cli.h @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2014 Google, Inc + * Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CLI_H +#define __CLI_H + +/** + * Go into the command loop + * + * This will return if we get a timeout waiting for a command. See + * CONFIG_BOOT_RETRY_TIME. + */ +void cli_simple_loop(void); + +/** + * cli_simple_run_command() - Execute a command with the simple CLI + * + * @cmd: String containing the command to execute + * @flag Flag value - see CMD_FLAG_... + * @return 1 - command executed, repeatable + * 0 - command executed but not repeatable, interrupted commands are + * always considered not repeatable + * -1 - not executed (unrecognized, bootd recursion or too many args) + * (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is + * considered unrecognized) + */ +int cli_simple_run_command(const char *cmd, int flag); + +/** + * cli_simple_process_macros() - Expand $() and ${} format env. variables + * + * @param input Input string possible containing $() / ${} vars + * @param output Output string with $() / ${} vars expanded + */ +void cli_simple_process_macros(const char *input, char *output); + +/** + * cli_simple_run_command_list() - Execute a list of command + * + * The commands should be separated by ; or \n and will be executed + * by the built-in parser. + * + * This function cannot take a const char * for the command, since if it + * finds newlines in the string, it replaces them with \0. + * + * @param cmd String containing list of commands + * @param flag Execution flags (CMD_FLAG_...) + * @return 0 on success, or != 0 on error. + */ +int cli_simple_run_command_list(char *cmd, int flag); + +/** + * cli_readline() - read a line into the console_buffer + * + * This is a convenience function which calls cli_readline_into_buffer(). + * + * @prompt: Prompt to display + * @return command line length excluding terminator, or -ve on error + */ +int cli_readline(const char *const prompt); + +/** + * readline_into_buffer() - read a line into a buffer + * + * Display the prompt, then read a command line into @buffer. The + * maximum line length is CONFIG_SYS_CBSIZE including a \0 terminator, which + * will always be added. + * + * The command is echoed as it is typed. Command editing is supported if + * CONFIG_CMDLINE_EDITING is defined. Tab auto-complete is supported if + * CONFIG_AUTO_COMPLETE is defined. If CONFIG_BOOT_RETRY_TIME is defined, + * then a timeout will be applied. + * + * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0, + * time out when time goes past endtime (timebase time in ticks). + * + * @prompt: Prompt to display + * @buffer: Place to put the line that is entered + * @timeout: Timeout in milliseconds, 0 if none + * @return command line length excluding terminator, or -ve on error: of the + * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout + * parameter), then -2 is returned. If a break is detected (Ctrl-C) then + * -1 is returned. + */ +int cli_readline_into_buffer(const char *const prompt, char *buffer, + int timeout); + +/** + * parse_line() - split a command line down into separate arguments + * + * The argv[] array is filled with pointers into @line, and each argument + * is terminated by \0 (i.e. @line is changed in the process unless there + * is only one argument). + * + * #argv is terminated by a NULL after the last argument pointer. + * + * At most CONFIG_SYS_MAXARGS arguments are permited - if there are more + * than that then an error is printed, and this function returns + * CONFIG_SYS_MAXARGS, with argv[] set up to that point. + * + * @line: Command line to parse + * @args: Array to hold arguments + * @return number of arguments + */ +int cli_simple_parse_line(char *line, char *argv[]); + +#ifdef CONFIG_OF_CONTROL +/** + * cli_process_fdt() - process the boot command from the FDT + * + * If bootcmmd is defined in the /config node of the FDT, we use that + * as the boot command. Further, if bootsecure is set to 1 (in the same + * node) then we return true, indicating that the command should be executed + * as securely as possible, avoiding the CLI parser. + * + * @cmdp: On entry, the command that will be executed if the FDT does + * not have a command. Returns the command to execute after + * checking the FDT. + * @return true to execute securely, else false + */ +bool cli_process_fdt(const char **cmdp); + +/** cli_secure_boot_cmd() - execute a command as securely as possible + * + * This avoids using the parser, thus executing the command with the + * smallest amount of code. Parameters are not supported. + */ +void cli_secure_boot_cmd(const char *cmd); +#else +static inline bool cli_process_fdt(const char **cmdp) +{ + return false; +} + +static inline void cli_secure_boot_cmd(const char *cmd) +{ +} +#endif /* CONFIG_OF_CONTROL */ + +/** + * Go into the command loop + * + * This will return if we get a timeout waiting for a command, but only for + * the simple parser (not hush). See CONFIG_BOOT_RETRY_TIME. + */ +void cli_loop(void); + +/** Set up the command line interpreter ready for action */ +void cli_init(void); + +#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk()) + +#endif diff --git a/include/cli_hush.h b/include/cli_hush.h new file mode 100644 index 0000000000..57c870dfe9 --- /dev/null +++ b/include/cli_hush.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLI_HUSH_H_ +#define _CLI_HUSH_H_ + +#define FLAG_EXIT_FROM_LOOP 1 +#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ +#define FLAG_REPARSING (1 << 2) /* >=2nd pass */ +#define FLAG_CONT_ON_NEWLINE (1 << 3) /* continue when we see \n */ + +extern int u_boot_hush_start(void); +extern int parse_string_outer(const char *, int); +extern int parse_file_outer(void); + +int set_local_var(const char *s, int flg_export); +void unset_local_var(const char *name); +char *get_local_var(const char *s); + +#if defined(CONFIG_HUSH_INIT_VAR) +extern int hush_init_var (void); +#endif +#endif diff --git a/include/clk.h b/include/clk.h new file mode 100644 index 0000000000..df4570c6f5 --- /dev/null +++ b/include/clk.h @@ -0,0 +1,6 @@ +#ifndef _CLK_H_ +#define _CLK_H_ + +int soc_clk_dump(void); + +#endif /* _CLK_H_ */ diff --git a/include/command.h b/include/command.h index f782779d8b..bd3fc049ec 100644 --- a/include/command.h +++ b/include/command.h @@ -11,7 +11,6 @@ #ifndef __COMMAND_H #define __COMMAND_H -#include #include #ifndef NULL @@ -64,6 +63,15 @@ extern int var_complete(int argc, char * const argv[], char last_char, int maxv, extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); #endif +/** + * cmd_process_error() - report and process a possible error + * + * @cmdtp: Command which caused the error + * @err: Error code (0 if none, -ve for error, like -EIO) + * @return 0 if there is not error, 1 (CMD_RET_FAILURE) if an error is found + */ +int cmd_process_error(cmd_tbl_t *cmdtp, int err); + /* * Monitor Command * @@ -139,6 +147,7 @@ int cmd_process(int flag, int argc, char * const argv[], */ #define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ #define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ +#define CMD_FLAG_ENV 0x0004 /* command is from the environment */ #ifdef CONFIG_AUTO_COMPLETE # define _CMD_COMPLETE(x) x, diff --git a/include/common.h b/include/common.h index 5d502c1b54..97c8f79fc7 100644 --- a/include/common.h +++ b/include/common.h @@ -2,15 +2,12 @@ * (C) Copyright 2000-2009 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __COMMON_H_ #define __COMMON_H_ 1 -#undef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #ifndef __ASSEMBLY__ /* put C only stuff in this section */ typedef unsigned char uchar; @@ -26,21 +23,17 @@ typedef volatile unsigned char vu_char; #include #include #include +#include #if defined(CONFIG_PCI) && defined(CONFIG_4xx) #include #endif #if defined(CONFIG_8xx) #include -#if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \ - defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ - defined(CONFIG_MPC859DSL) || \ - defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \ +#if defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ + defined(CONFIG_MPC866) || \ defined(CONFIG_MPC866P) # define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC870) \ - || defined(CONFIG_MPC875) \ - || defined(CONFIG_MPC880) \ - || defined(CONFIG_MPC885) +#elif defined(CONFIG_MPC885) # define CONFIG_MPC885_FAMILY 1 #endif #if defined(CONFIG_MPC860) \ @@ -55,16 +48,11 @@ typedef volatile unsigned char vu_char; #include #elif defined(CONFIG_MPC512X) #include -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #if defined(CONFIG_MPC8247) \ - || defined(CONFIG_MPC8248) \ - || defined(CONFIG_MPC8271) \ || defined(CONFIG_MPC8272) #define CONFIG_MPC8272_FAMILY 1 #endif -#if defined(CONFIG_MPC8272_FAMILY) -#define CONFIG_MPC8260 1 -#endif #include #endif #ifdef CONFIG_MPC86xx @@ -82,12 +70,6 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_4xx #include #endif -#ifdef CONFIG_HYMOD -#include -#endif -#ifdef CONFIG_ARM -#define asmlinkage /* nothing */ -#endif #ifdef CONFIG_BLACKFIN #include #endif @@ -99,21 +81,32 @@ typedef volatile unsigned char vu_char; #include #include +/* Bring in printf format macros if inttypes.h is included */ +#define __STDC_FORMAT_MACROS + +#ifdef __LP64__ +#define CONFIG_SYS_SUPPORT_64BIT_DATA +#endif + #ifdef DEBUG #define _DEBUG 1 #else #define _DEBUG 0 #endif +#ifndef pr_fmt +#define pr_fmt(fmt) fmt +#endif + /* * Output a debug text when condition "cond" is met. The "cond" should be * computed by a preprocessor in the best case, allowing for the best * optimization. */ -#define debug_cond(cond, fmt, args...) \ - do { \ - if (cond) \ - printf(fmt, ##args); \ +#define debug_cond(cond, fmt, args...) \ + do { \ + if (cond) \ + printf(pr_fmt(fmt), ##args); \ } while (0) #define debug(fmt, args...) \ @@ -135,7 +128,7 @@ void __assert_fail(const char *assertion, const char *file, unsigned line, __assert_fail(#x, __FILE__, __LINE__, __func__); }) #define error(fmt, args...) do { \ - printf("ERROR: " fmt "\nat %s:%d/%s()\n", \ + printf("ERROR: " pr_fmt(fmt) "\nat %s:%d/%s()\n", \ ##args, __FILE__, __LINE__, __func__); \ } while (0) @@ -177,64 +170,6 @@ typedef void (interrupt_handler_t)(void *); # endif #endif -/* - * General Purpose Utilities - */ -#define min(X, Y) \ - ({ typeof(X) __x = (X); \ - typeof(Y) __y = (Y); \ - (__x < __y) ? __x : __y; }) - -#define max(X, Y) \ - ({ typeof(X) __x = (X); \ - typeof(Y) __y = (Y); \ - (__x > __y) ? __x : __y; }) - -#define MIN(x, y) min(x, y) -#define MAX(x, y) max(x, y) - -#define min3(X, Y, Z) \ - ({ typeof(X) __x = (X); \ - typeof(Y) __y = (Y); \ - typeof(Z) __z = (Z); \ - __x < __y ? (__x < __z ? __x : __z) : \ - (__y < __z ? __y : __z); }) - -#define max3(X, Y, Z) \ - ({ typeof(X) __x = (X); \ - typeof(Y) __y = (Y); \ - typeof(Z) __z = (Z); \ - __x > __y ? (__x > __z ? __x : __z) : \ - (__y > __z ? __y : __z); }) - -#define MIN3(x, y, z) min3(x, y, z) -#define MAX3(x, y, z) max3(x, y, z) - -/* - * Return the absolute value of a number. - * - * This handles unsigned and signed longs, ints, shorts and chars. For all - * input types abs() returns a signed long. - * - * For 64-bit types, use abs64() - */ -#define abs(x) ({ \ - long ret; \ - if (sizeof(x) == sizeof(long)) { \ - long __x = (x); \ - ret = (__x < 0) ? -__x : __x; \ - } else { \ - int __x = (x); \ - ret = (__x < 0) ? -__x : __x; \ - } \ - ret; \ - }) - -#define abs64(x) ({ \ - s64 __x = (x); \ - (__x < 0) ? -__x : __x; \ - }) - #if defined(CONFIG_ENV_IS_EMBEDDED) #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ @@ -245,17 +180,6 @@ typedef void (interrupt_handler_t)(void *); #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #endif -/** - * container_of - cast a member of a structure out to the containing structure - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - * - */ -#define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - /* * Function Prototypes */ @@ -268,13 +192,26 @@ int cpu_init(void); /* */ phys_size_t initdram (int); int display_options (void); -void print_size(unsigned long long, const char *); + +/** + * print_size() - Print a size with a suffic + * + * print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB", + * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string + * (like "\n") + * + * @size: Size to print + * @suffix String to print after the size + */ +void print_size(uint64_t size, const char *suffix); + int print_buffer(ulong addr, const void *data, uint width, uint count, uint linelen); /* common/main.c */ void main_loop (void); int run_command(const char *cmd, int flag); +int run_command_repeatable(const char *cmd, int flag); /** * Run a list of commands separated by ; or even \0 @@ -288,27 +225,31 @@ int run_command(const char *cmd, int flag); * @return 0 on success, or != 0 on error. */ int run_command_list(const char *cmd, int len, int flag); -int readline (const char *const prompt); -int readline_into_buffer(const char *const prompt, char *buffer, - int timeout); -int parse_line (char *, char *[]); -void init_cmd_timeout(void); -void reset_cmd_timeout(void); extern char console_buffer[]; /* arch/$(ARCH)/lib/board.c */ -void board_init_f(ulong); -void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); -int checkboard (void); -int checkflash (void); -int checkdram (void); -int last_stage_init(void); +void board_init_f(ulong); +void board_init_r(gd_t *, ulong) __attribute__ ((noreturn)); +int checkboard(void); +int show_board_info(void); +int checkflash(void); +int checkdram(void); +int last_stage_init(void); extern ulong monitor_flash_len; int mac_read_from_eeprom(void); -extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */ +extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ int set_cpu_clk_info(void); +int mdm_init(void); +#if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void); +#else +static inline int print_cpuinfo(void) +{ + return 0; +} +#endif int update_flash_size(int flash_size); +int arch_early_init_r(void); /** * Show the DRAM size in a board-specific way @@ -320,14 +261,14 @@ int update_flash_size(int flash_size); void board_show_dram(ulong size); /** - * arch_fixup_memory_node() - Write arch-specific memory information to fdt + * arch_fixup_fdt() - Write arch-specific information to fdt * - * Defined in arch/$(ARCH)/lib/bootm.c + * Defined in arch/$(ARCH)/lib/bootm-fdt.c * * @blob: FDT blob to write to * @return 0 if ok, or -ve FDT_ERR_... on failure */ -int arch_fixup_memory_node(void *blob); +int arch_fixup_fdt(void *blob); /* common/flash.c */ void flash_perror (int); @@ -355,6 +296,11 @@ int do_ext2load(cmd_tbl_t *, int, int, char * const []); int env_init (void); void env_relocate (void); int envmatch (uchar *, int); + +/* Avoid unfortunate conflict with libc's getenv() */ +#ifdef CONFIG_SANDBOX +#define getenv uboot_getenv +#endif char *getenv (const char *); int getenv_f (const char *name, char *buf, unsigned len); ulong getenv_ulong(const char *name, int base, ulong default_val); @@ -383,7 +329,7 @@ int setenv_hex(const char *varname, ulong value); /** * setenv_addr - Set an environment variable to an address in hex * - * @varname: Environmet variable to set + * @varname: Environment variable to set * @addr: Value to set it to * @return 0 if ok, 1 on error */ @@ -411,6 +357,9 @@ static inline int setenv_addr(const char *varname, const void *addr) #ifdef CONFIG_MIPS # include #endif /* CONFIG_MIPS */ +#ifdef CONFIG_ARC +# include +#endif /* CONFIG_ARC */ #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); @@ -454,6 +403,7 @@ void api_init (void); /* common/memsize.c */ long get_ram_size (long *, long); +phys_size_t get_effective_memsize(void); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); @@ -466,10 +416,6 @@ int eeprom_probe (unsigned dev_addr, unsigned offset); #endif int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); -#ifdef CONFIG_LWMON -extern uchar pic_read (uchar reg); -extern void pic_write (uchar reg, uchar val); -#endif /* * Set this up regardless of board @@ -490,31 +436,6 @@ extern ssize_t spi_read (uchar *, int, uchar *, int); extern ssize_t spi_write (uchar *, int, uchar *, int); #endif -#ifdef CONFIG_RPXCLASSIC -void rpxclassic_init (void); -#endif - -void rpxlite_init (void); - -#ifdef CONFIG_MBX -/* $(BOARD)/mbx8xx.c */ -void mbx_init (void); -void board_serial_init (void); -void board_ether_init (void); -#endif - -#ifdef CONFIG_HERMES -/* $(BOARD)/hermes.c */ -void hermes_start_lxt980 (int speed); -#endif - -#ifdef CONFIG_EVB64260 -void evb64260_init(void); -void debug_led(int, int); -void display_mem_map(void); -void perform_soft_reset(void); -#endif - /* $(BOARD)/$(BOARD).c */ int board_early_init_f (void); int board_late_init (void); @@ -559,10 +480,6 @@ ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \ defined (CONFIG_MPC5xxx) || \ - defined (CONFIG_74xx_7xx) || \ - defined (CONFIG_74x) || \ - defined (CONFIG_75x) || \ - defined (CONFIG_74xx) || \ defined (CONFIG_MPC85xx) || \ defined (CONFIG_MPC86xx) || \ defined (CONFIG_MPC83xx) @@ -596,6 +513,12 @@ void ddr_enable_ecc(unsigned int dram_size); #endif #endif +/* + * Return the current value of a monotonically increasing microsecond timer. + * Granularity may be larger than 1us if hardware does not support this. + */ +ulong timer_get_us(void); + /* $(CPU)/cpu.c */ static inline int cpumask_next(int cpu, unsigned int mask) { @@ -619,6 +542,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +void reset_misc (void); void reset_cpu (ulong addr); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd); @@ -627,6 +551,8 @@ void ft_pci_setup(void *blob, bd_t *bd); #endif #endif +void smp_set_core_boot_addr(unsigned long addr, int corenr); +void smp_kick_all_cpus(void); /* $(CPU)/serial.c */ int serial_init (void); @@ -637,19 +563,17 @@ void serial_puts (const char *); int serial_getc (void); int serial_tstc (void); -void _serial_setbrg (const int); -void _serial_putc (const char, const int); -void _serial_putc_raw(const char, const int); -void _serial_puts (const char *, const int); -int _serial_getc (const int); -int _serial_tstc (const int); +/* These versions take a stdio_dev pointer */ +struct stdio_dev; +int serial_stub_getc(struct stdio_dev *sdev); +int serial_stub_tstc(struct stdio_dev *sdev); /* $(CPU)/speed.c */ int get_clocks (void); int get_clocks_866 (void); int sdram_adjust_866 (void); int adjust_sdram_tbs_8xx (void); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) int prt_8260_clks (void); #elif defined(CONFIG_MPC5xxx) int prt_mpc5xxx_clks (void); @@ -669,9 +593,6 @@ ulong get_UCLK (void); #if defined(CONFIG_LH7A40X) ulong get_PLLCLK (void); #endif -#if defined CONFIG_INCA_IP -uint incaip_get_cpuclk (void); -#endif #if defined(CONFIG_IMX) ulong get_systemPLLCLK(void); ulong get_FCLK(void); @@ -684,12 +605,13 @@ ulong get_PERCLK3(void); ulong get_bus_freq (ulong); int get_serial_clock(void); -#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) -ulong get_ddr_freq(ulong); -#endif #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); +# if defined(CONFIG_OF_LIBFDT) + void ft_fixup_cpu(void *, u64); + void ft_fixup_num_cores(void *); +# endif #endif #if defined(CONFIG_MPC86xx) typedef MPC86xx_SYS_INFO sys_info_t; @@ -698,6 +620,8 @@ static inline ulong get_ddr_freq(ulong dummy) { return get_bus_freq(dummy); } +#else +ulong get_ddr_freq(ulong); #endif #if defined(CONFIG_4xx) @@ -713,15 +637,18 @@ void get_sys_info ( sys_info_t * ); #endif /* $(CPU)/cpu_init.c */ -#if defined(CONFIG_8xx) || defined(CONFIG_8260) +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx) void cpu_init_f (void); #endif +#ifdef CONFIG_MPC85xx +ulong cpu_init_f(void); +#endif int cpu_init_r (void); -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) int prt_8260_rsr (void); #elif defined(CONFIG_MPC83xx) int prt_83xx_rsr (void); @@ -771,7 +698,7 @@ void invalidate_dcache_all(void); void invalidate_icache_all(void); /* arch/$(ARCH)/lib/ticks.S */ -unsigned long long get_ticks(void); +uint64_t get_ticks(void); void wait_ticks (unsigned long); /* arch/$(ARCH)/lib/time.c */ @@ -795,8 +722,7 @@ void udelay (unsigned long); void mdelay(unsigned long); /* lib/uuid.c */ -void uuid_str_to_bin(const char *uuid, unsigned char *out); -int uuid_str_valid(const char *uuid); +#include /* lib/vsprintf.c */ #include @@ -808,15 +734,10 @@ char * strmhz(char *buf, unsigned long hz); #include /* lib/rand.c */ -#if defined(CONFIG_RANDOM_MACADDR) || \ - defined(CONFIG_BOOTP_RANDOM_DELAY) || \ - defined(CONFIG_BOOTP_RANDOM_ID) || \ - defined(CONFIG_CMD_LINK_LOCAL) #define RAND_MAX -1U void srand(unsigned int seed); unsigned int rand(void); unsigned int rand_r(unsigned int *seedp); -#endif /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ @@ -826,7 +747,7 @@ int ctrlc (void); int had_ctrlc (void); /* have we had a Control-C since last clear? */ void clear_ctrlc (void); /* clear the Control-C condition */ int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ - +int confirm_yesno(void); /* 1 if input is "y", "Y", "yes" or "YES" */ /* * STDIO based functions (can always be used) */ @@ -916,7 +837,7 @@ static inline void unmap_sysmem(const void *vaddr) { } -static inline phys_addr_t map_to_sysmem(void *ptr) +static inline phys_addr_t map_to_sysmem(const void *ptr) { return (phys_addr_t)(uintptr_t)ptr; } @@ -946,15 +867,7 @@ static inline phys_addr_t map_to_sysmem(void *ptr) #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. #endif -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - #define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) -#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d)) -#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) - -#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) /* * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It @@ -1016,10 +929,10 @@ static inline phys_addr_t map_to_sysmem(void *ptr) * of a function scoped static buffer. It can not be used to create a cache * line aligned global buffer. */ -#define PAD_COUNT(s, pad) ((s - 1) / pad + 1) +#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) #define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) #define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ - char __##name[ROUND(PAD_SIZE(size * sizeof(type), pad), align) \ + char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ + (align - 1)]; \ \ type *name = (type *) ALIGN((uintptr_t)__##name, align) @@ -1036,7 +949,7 @@ static inline phys_addr_t map_to_sysmem(void *ptr) * Usage of this macro shall be avoided or used with extreme care! */ #define DEFINE_ALIGN_BUFFER(type, name, size, align) \ - static char __##name[roundup(size * sizeof(type), align)] \ + static char __##name[ALIGN(size * sizeof(type), align)] \ __aligned(align); \ \ static type *name = (type *)__##name diff --git a/include/common_timing_params.h b/include/common_timing_params.h new file mode 100644 index 0000000000..821de21de7 --- /dev/null +++ b/include/common_timing_params.h @@ -0,0 +1,70 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef COMMON_TIMING_PARAMS_H +#define COMMON_TIMING_PARAMS_H + +typedef struct { + /* parameters to constrict */ + + unsigned int tckmin_x_ps; + unsigned int tckmax_ps; + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + unsigned int taamin_ps; +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int trfc1_ps; + unsigned int trfc2_ps; + unsigned int trfc4_ps; + unsigned int trrds_ps; + unsigned int trrdl_ps; + unsigned int tccdl_ps; +#else + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns + = 511750 ps */ + + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ +#endif + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + unsigned int refresh_rate_ps; + unsigned int extended_op_srt; + +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ +#endif + + unsigned int ndimms_present; + unsigned int lowest_common_spd_caslat; + unsigned int highest_common_derated_caslat; + unsigned int additive_latency; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + unsigned int all_dimms_ecc_capable; + + unsigned long long total_mem; + unsigned long long base_address; + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ +} common_timing_params_t; + +#endif diff --git a/include/commproc.h b/include/commproc.h index 6959905efe..9582746153 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -12,15 +12,10 @@ * CPM capabilities. I (or someone else) will add definitions as they * are needed. -- Dan * - * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 - * bytes of the DP RAM and relocates the I2C parameter area to the - * IDMA1 space. The remaining DP RAM is available for buffer descriptors - * or other use. */ #ifndef __CPM_8XX__ #define __CPM_8XX__ -#include #include /* CPM Command register. @@ -136,7 +131,6 @@ typedef struct cpm_buf_desc { #define PROFF_SMC2 ((uint)0x0380) /* Define enough so I can at least use the serial port as a UART. - * The MBX uses SMC1 as the host serial port. */ typedef struct smc_uart { ushort smc_rbase; /* Rx Buffer descriptor base address */ @@ -435,38 +429,6 @@ typedef struct scc_enet { * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. **********************************************************************/ - -/*** ADS *************************************************************/ - -#if defined(CONFIG_MPC860) && defined(CONFIG_ADS) -/* This ENET stuff is for the MPC860ADS with ethernet on SCC1. - */ - -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 - -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) - -#define PB_ENET_TENA ((uint)0x00001000) - -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002c) - -/* 68160 PHY control */ - -#define PC_ENET_ETHLOOP ((ushort)0x0800) -#define PC_ENET_TPFLDL ((ushort)0x0400) -#define PC_ENET_TPSQEL ((ushort)0x0200) - -#endif /* MPC860ADS */ - /*** BSEIP **********************************************************/ #ifdef CONFIG_BSEIP @@ -494,455 +456,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002c00) #endif /* CONFIG_BSEIP */ -/*** BSEIP **********************************************************/ - -#ifdef CONFIG_FLAGADM -/* Enet configuration for the FLAGADM */ -/* Enet on SCC2 */ - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0400) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003400) -#endif /* CONFIG_FLAGADM */ - -/*** ELPT860 *********************************************************/ - -#ifdef CONFIG_ELPT860 -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -# define PROFF_ENET PROFF_SCC1 -# define CPM_CR_ENET CPM_CR_CH_SCC1 -# define SCC_ENET 0 - -# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ - -# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -# define SICR_ENET_MASK ((uint)0x000000FF) -# define SICR_ENET_CLKRT ((uint)0x00000025) -#endif /* CONFIG_ELPT860 */ - -/*** ESTEEM 192E **************************************************/ -#ifdef CONFIG_ESTEEM192E -/* ESTEEM192E - * This ENET stuff is for the MPC850 with ethernet on SCC2. This - * is very similar to the RPX-Lite configuration. - * Note TENA , LOOPBACK , FDPLEX_DIS on Port B. - */ - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 - -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) - -#define PB_ENET_LOOPBACK ((uint)0x00004000) -#define PB_ENET_FDPLEX_DIS ((uint)0x00008000) - -#endif - -/*** FADS823 ********************************************************/ - -#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS) -/* This ENET stuff is for the MPC823FADS with ethernet on SCC2. - */ -#ifdef CONFIG_SCC2_ENET -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define CPMVEC_ENET CPMVEC_SCC2 -#endif - -#ifdef CONFIG_SCC1_ENET -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define CPMVEC_ENET CPMVEC_SCC1 -#endif - -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0200) - -#define PB_ENET_TENA ((uint)0x00002000) - -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) - -#endif /* CONFIG_FADS823FADS */ - -/*** FADS850SAR ********************************************************/ - -#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS) -/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of - * this may be unique to the FADS850SAR configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ -#endif /* CONFIG_FADS850SAR */ - -/*** FADS860T********************************************************/ - -#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) -/* - * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. - */ -#ifdef CONFIG_SCC1_ENET - -#define SCC_ENET 0 - -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 - -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) - -#define PB_ENET_TENA ((uint)0x00001000) - -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002c) - -#endif /* CONFIG_SCC1_ETHERNET */ - -/* - * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS - * with ethernet on FEC. - */ - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* Use FEC for Ethernet */ -#endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_FADS && CONFIG_MPC86x */ - -/*** FPS850L, FPS860L ************************************************/ - -#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_FPS850L, CONFIG_FPS860L */ - -/*** GEN860T **********************************************************/ -#if defined(CONFIG_GEN860T) -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ -#endif /* CONFIG_GEN860T */ - -/*** GENIETV ********************************************************/ - -#if defined(CONFIG_GENIETV) -/* Ethernet is only on SCC2 */ - -#define CONFIG_SCC2_ENET -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define CPMVEC_ENET CPMVEC_SCC2 - -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) - -#endif /* CONFIG_GENIETV */ - -/*** HERMES-PRO ******************************************************/ - -/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ - -#ifdef CONFIG_HERMES - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_HERMES */ - -/*** ICU862 **********************************************************/ - -#if defined(CONFIG_ICU862) - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for EThernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -#endif /* CONFIG_ICU862 */ - -/*** IP860 **********************************************************/ - -#if defined(CONFIG_IP860) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */ -#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */ - -/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002C) -#endif /* CONFIG_IP860 */ - -/*** IVMS8 **********************************************************/ - -/* The IVMS8 uses the FEC on a MPC860T for Ethernet */ - -#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - -#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ - -#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_IVMS8, CONFIG_IVML24 */ - -/*** KUP4K, KUP4X ****************************************************/ -/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ - -#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - -#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ - -#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_KUP4K */ - -/*** LWMON **********************************************************/ - -#if defined(CONFIG_LWMON) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003E00) -#endif /* CONFIG_LWMON */ - -/*** NX823 ***********************************************/ - -#if defined(CONFIG_NX823) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) - -#endif /* CONFIG_NX823 */ - -/*** MBX ************************************************************/ - -#ifdef CONFIG_MBX -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. The TCLK and RCLK seem unique - * to the MBX860 board. Any two of the four available clocks could be - * used, and the MPC860 cookbook manual has an example using different - * clock pins. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PC_ENET_TENA ((ushort)0x0001) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) -#endif /* CONFIG_MBX */ - /*** KM8XX *********************************************************/ /* The KM8XX Service Module uses SCC3 for Ethernet */ @@ -968,309 +481,19 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00250000) #endif /* CONFIG_KM8XX */ - -/*** MHPC ********************************************************/ - -#if defined(CONFIG_MHPC) -/* This ENET stuff is for the MHPC with ethernet on SCC2. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ -#endif /* CONFIG_MHPC */ - -/*** NETVIA *******************************************************/ - -/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ -#if ( defined CONFIG_SVM_SC8xx ) -# ifndef CONFIG_FEC_ENET - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 - - /* Bits in parallel I/O port registers that have to be set/cleared - * * * * to configure the pins for SCC2 use. - * * * */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - * * * */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003700) - -# else /* Use FEC for Fast Ethernet */ - -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_SVM_SC8xx */ - - -#if defined(CONFIG_NETVIA) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 -# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ -#elif CONFIG_NETVIA_VERSION >= 2 -# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ -#endif - -#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) - -#endif /* CONFIG_NETVIA */ - -/*** QS850/QS823 ***************************************************/ - -#if defined(CONFIG_QS850) || defined(CONFIG_QS823) -#undef FEC_ENET /* Don't use FEC for EThernet */ - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 - -#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */ -#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */ -#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */ -#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */ -#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */ -#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */ -#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */ -#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */ -#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */ -#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */ - -/* SCC2 TXCLK from CLK2 - * SCC2 RXCLK from CLK4 - * SCC2 Connected to NMSI */ -#define SICR_ENET_MASK ((uint)0x00007F00) -#define SICR_ENET_CLKRT ((uint)0x00003D00) - -#endif /* CONFIG_QS850/QS823 */ - -/*** QS860T ***************************************************/ - -#ifdef CONFIG_QS860T -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for EThernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -/* This ENET stuff is for GTH 10 Mbit ( SCC ) */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 - -#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */ -#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ - -#define SICR_ENET_MASK ((uint)0x000000ff) -/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */ -#define SICR_ENET_CLKRT ((uint)0x0000003D) - -#endif /* CONFIG_QS860T */ - -/*** RPXCLASSIC *****************************************************/ - -#ifdef CONFIG_RPXCLASSIC - -#ifdef CONFIG_FEC_ENET - -# define FEC_ENET /* use FEC for EThernet */ -# undef SCC_ENET - -#else /* ! CONFIG_FEC_ENET */ - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) - -#endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_RPXCLASSIC */ - -/*** RPXLITE ********************************************************/ - -#ifdef CONFIG_RPXLITE -/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of - * this may be unique to the RPX-Lite configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#if defined(CONFIG_RMU) -#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */ -#else -#define PB_ENET_TENA ((uint)0x00002000) -#endif -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) -#endif /* CONFIG_RPXLITE */ - -/*** SM850 *********************************************************/ - -/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ - -#ifdef CONFIG_SM850 -#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ -#define CPM_CR_ENET CPM_CR_CH_SCC3 -#define SCC_ENET 2 -#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ -#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ -#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00260000) -#endif /* CONFIG_SM850 */ - -/*** SPD823TS ******************************************************/ - -#ifdef CONFIG_SPD823TS -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */ -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ -#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002E00) -#endif /* CONFIG_SPD823TS */ - -/*** SXNI855T ******************************************************/ - -#if defined(CONFIG_SXNI855T) - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for Ethernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -#endif /* CONFIG_SXNI855T */ - /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ - defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ - defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \ + defined(CONFIG_TQM823L) || \ defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \ - defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2) + defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. */ #define PROFF_ENET PROFF_SCC2 #define CPM_CR_ENET CPM_CR_CH_SCC2 -#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ #define SCC_ENET 1 -#endif #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ @@ -1280,9 +503,6 @@ typedef struct scc_enet { #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -#if defined(CONFIG_R360MPI) -#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ -#endif /* CONFIG_R360MPI */ /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. @@ -1351,29 +571,6 @@ typedef struct scc_enet { # endif /* CONFIG_FEC_ENET */ #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ -/*** V37 **********************************************************/ - -#ifdef CONFIG_V37 -/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of - * this may be unique to the Marel V37 configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) -#endif /* CONFIG_V37 */ - - /*********************************************************************/ /* SCC Event register as used by Ethernet. diff --git a/include/compiler.h b/include/compiler.h index 0734ed4942..47c296e202 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -48,6 +48,11 @@ # include typedef unsigned long ulong; #endif +#ifdef __FreeBSD__ +# include /* htole32 and friends */ +#endif + +#include typedef uint8_t __u8; typedef uint16_t __u16; @@ -107,6 +112,14 @@ typedef unsigned int uint; #else /* !USE_HOSTCC */ +#ifdef CONFIG_USE_STDINT +/* Provided by gcc. */ +#include +#else +/* Type for `void *' pointers. */ +typedef unsigned long int uintptr_t; +#endif + #include #include #include @@ -123,14 +136,8 @@ typedef unsigned int uint; #define __WORDSIZE 32 #endif -/* Type for `void *' pointers. */ -typedef unsigned long int uintptr_t; - #endif /* USE_HOSTCC */ -/* compiler options */ -#define uninitialized_var(x) x = x - #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d84706969d..2c2a05bce1 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_BSP /* Board Specific functions */ #define CONFIG_CMD_CACHE /* icache, dcache */ #define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ +#define CONFIG_CMD_CLK /* Clock support */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ #define CONFIG_CMD_DHCP /* DHCP Support */ @@ -37,7 +38,6 @@ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ -#define CONFIG_CMD_FDOS /* Floppy DOS support */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_FUSE /* Device fuse support */ diff --git a/include/config_cmd_defaults.h b/include/config_cmd_defaults.h deleted file mode 100644 index a55b268b9b..0000000000 --- a/include/config_cmd_defaults.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * config_cmd_defaults.h - sane defaults for everyone - * - * Copyright (c) 2010-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CONFIG_CMD_DEFAULTS_H_ -#define _CONFIG_CMD_DEFAULTS_H_ - -#define CONFIG_CMD_BOOTM 1 -#define CONFIG_CMD_CRC32 1 -#define CONFIG_CMD_EXPORTENV 1 -#define CONFIG_CMD_GO 1 -#define CONFIG_CMD_IMPORTENV 1 - -#endif diff --git a/include/config_defaults.h b/include/config_defaults.h index 567b46c87a..4d49315044 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -14,9 +14,16 @@ #define CONFIG_BOOTM_NETBSD 1 #define CONFIG_BOOTM_PLAN9 1 #define CONFIG_BOOTM_RTEMS 1 +#define CONFIG_BOOTM_VXWORKS 1 #define CONFIG_GZIP 1 #define CONFIG_ZLIB 1 #define CONFIG_PARTITIONS 1 +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_WARN +#define CONFIG_DM_DEVICE_REMOVE +#define CONFIG_DM_STDIO +#endif + #endif diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h new file mode 100644 index 0000000000..49674f4537 --- /dev/null +++ b/include/config_distro_bootcmd.h @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * Copyright 2014 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H +#define _CONFIG_CMD_DISTRO_BOOTCMD_H + +#define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \ + "if " #devtypel " dev ${devnum}; then " \ + "setenv devtype " #devtypel "; " \ + "run scan_dev_for_boot_part; " \ + "fi\0" + +#define BOOTENV_SHARED_BLKDEV(devtypel) \ + #devtypel "_boot=" \ + BOOTENV_SHARED_BLKDEV_BODY(devtypel) + +#define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv devnum " #instance "; " \ + "run " #devtypel "_boot\0" + +#define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#ifdef CONFIG_CMD_MMC +#define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc) +#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_MMC +#define BOOTENV_DEV_MMC \ + BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC +#define BOOTENV_DEV_NAME_MMC \ + BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC +#endif + +#ifdef CONFIG_CMD_SATA +#define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata) +#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_SATA +#define BOOTENV_DEV_SATA \ + BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA +#define BOOTENV_DEV_NAME_SATA \ + BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA +#endif + +#ifdef CONFIG_CMD_SCSI +#define BOOTENV_RUN_SCSI_INIT "run scsi_init; " +#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; " +#define BOOTENV_SHARED_SCSI \ + "scsi_init=" \ + "if ${scsi_need_init}; then " \ + "setenv scsi_need_init false; " \ + "scsi scan; " \ + "fi\0" \ + \ + "scsi_boot=" \ + BOOTENV_RUN_SCSI_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(scsi) +#define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_SCSI BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_RUN_SCSI_INIT +#define BOOTENV_SET_SCSI_NEED_INIT +#define BOOTENV_SHARED_SCSI +#define BOOTENV_DEV_SCSI \ + BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI +#define BOOTENV_DEV_NAME_SCSI \ + BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI +#endif + +#ifdef CONFIG_CMD_IDE +#define BOOTENV_SHARED_IDE BOOTENV_SHARED_BLKDEV(ide) +#define BOOTENV_DEV_IDE BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_IDE BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_IDE +#define BOOTENV_DEV_IDE \ + BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE +#define BOOTENV_DEV_NAME_IDE \ + BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE +#endif + +#ifdef CONFIG_CMD_USB +#define BOOTENV_RUN_USB_INIT "usb start; " +#define BOOTENV_SHARED_USB \ + "usb_boot=" \ + BOOTENV_RUN_USB_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(usb) +#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_RUN_USB_INIT +#define BOOTENV_SHARED_USB +#define BOOTENV_DEV_USB \ + BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB +#define BOOTENV_DEV_NAME_USB \ + BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB +#endif + +#if defined(CONFIG_CMD_DHCP) +#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ + "bootcmd_dhcp=" \ + BOOTENV_RUN_USB_INIT \ + "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ + "source ${scriptaddr}; " \ + "fi\0" +#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \ + "dhcp " +#else +#define BOOTENV_DEV_DHCP \ + BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP +#define BOOTENV_DEV_NAME_DHCP \ + BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP +#endif + +#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE) +#define BOOTENV_DEV_PXE(devtypeu, devtypel, instance) \ + "bootcmd_pxe=" \ + BOOTENV_RUN_USB_INIT \ + "dhcp; " \ + "if pxe get; then " \ + "pxe boot; " \ + "fi\0" +#define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \ + "pxe " +#else +#define BOOTENV_DEV_PXE \ + BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE +#define BOOTENV_DEV_NAME_PXE \ + BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE +#endif + +#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \ + BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV_BOOT_TARGETS \ + "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0" + +#define BOOTENV_DEV(devtypeu, devtypel, instance) \ + BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV \ + BOOTENV_SHARED_MMC \ + BOOTENV_SHARED_USB \ + BOOTENV_SHARED_SATA \ + BOOTENV_SHARED_SCSI \ + BOOTENV_SHARED_IDE \ + "boot_prefixes=/ /boot/\0" \ + "boot_scripts=boot.scr.uimg boot.scr\0" \ + "boot_script_dhcp=boot.scr.uimg\0" \ + BOOTENV_BOOT_TARGETS \ + \ + "boot_extlinux=" \ + "sysboot ${devtype} ${devnum}:${bootpart} any " \ + "${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \ + \ + "scan_dev_for_extlinux=" \ + "if test -e ${devtype} ${devnum}:${bootpart} " \ + "${prefix}extlinux/extlinux.conf; then " \ + "echo Found ${prefix}extlinux/extlinux.conf; " \ + "run boot_extlinux; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi\0" \ + \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "source ${scriptaddr}\0" \ + \ + "scan_dev_for_scripts=" \ + "for script in ${boot_scripts}; do " \ + "if test -e ${devtype} ${devnum}:${bootpart} " \ + "${prefix}${script}; then " \ + "echo Found U-Boot script " \ + "${prefix}${script}; " \ + "run boot_a_script; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi; " \ + "done\0" \ + \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} ${devnum}:${bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_extlinux; " \ + "run scan_dev_for_scripts; " \ + "done\0" \ + \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "for bootpart in ${devplist}; do " \ + "if fstype ${devtype} ${devnum}:${bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + \ + BOOT_TARGET_DEVICES(BOOTENV_DEV) \ + \ + "distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \ + "for target in ${boot_targets}; do " \ + "run bootcmd_${target}; " \ + "done\0" + +#ifndef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd" +#endif + +#endif /* _CONFIG_CMD_DISTRO_BOOTCMD_H */ diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h new file mode 100644 index 0000000000..1ecc0bb0a9 --- /dev/null +++ b/include/config_distro_defaults.h @@ -0,0 +1,56 @@ +/* + * Copyright 2013-2014 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H +#define _CONFIG_CMD_DISTRO_DEFAULTS_H + +/* + * List of all commands and options that when defined enables support for + * features required by distros to support boards in a standardised and + * consistent manner. + */ + +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_SUBNETMASK + +#if defined(__arm__) +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 +#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7" +#else +#define CONFIG_BOOTP_VCI_STRING "U-boot.arm" +#endif +#endif + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_PXE + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_BOOTDELAY 2 +#define CONFIG_SYS_LONGHELP +#define CONFIG_MENU +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_SYS_HUSH_PARSER + +#endif /* _CONFIG_CMD_DISTRO_DEFAULTS_H */ diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index e59ee963f7..ddfe0450d2 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -48,9 +48,53 @@ defined(CONFIG_CMD_SCSI) || \ defined(CONFIG_CMD_USB) || \ defined(CONFIG_CMD_PART) || \ + defined(CONFIG_CMD_GPT) || \ defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) + defined(CONFIG_SYSTEMACE) || \ + defined(CONFIG_SANDBOX) #define HAVE_BLOCK_DEVICE #endif +#if (defined(CONFIG_PARTITION_UUIDS) || \ + defined(CONFIG_EFI_PARTITION) || \ + defined(CONFIG_RANDOM_UUID) || \ + defined(CONFIG_CMD_UUID) || \ + defined(CONFIG_BOOTP_PXE)) && \ + !defined(CONFIG_LIB_UUID) +#define CONFIG_LIB_UUID +#endif + +#if (defined(CONFIG_RANDOM_UUID) || \ + defined(CONFIG_CMD_UUID)) && \ + (!defined(CONFIG_LIB_RAND) && \ + !defined(CONFIG_LIB_HW_RAND)) +#define CONFIG_LIB_RAND +#endif + +#if defined(CONFIG_API) && defined(CONFIG_LCD) +#define CONFIG_CMD_BMP +#endif + +#ifndef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "=> " +#endif + +#ifndef CONFIG_SYS_PBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 128) +#endif + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_IMAGE_FORMAT_LEGACY +#endif + +#ifdef CONFIG_DISABLE_IMAGE_LEGACY +#undef CONFIG_IMAGE_FORMAT_LEGACY +#endif + +#ifdef CONFIG_DM_I2C +# ifdef CONFIG_SYS_I2C +# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" +# endif +#endif + #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/configs/A3000.h b/include/configs/A3000.h deleted file mode 100644 index 90a21768e9..0000000000 --- a/include/configs/A3000.h +++ /dev/null @@ -1,295 +0,0 @@ -/* - * (C) Copyright 2001, 2002, 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ -/* - * Configuration settings for the A-3000 board (Artis Microsystems Inc.). - * http://artismicro.com - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_A3000 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - - -/* #define CONFIG_TULIP */ -/* #define CONFIG_EEPRO100 */ -#define CONFIG_NATSEMI - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 -#define PCI_ENET2_IOADDR 0x82000000 -#define PCI_ENET2_MEMADDR 0x82000000 -#define PCI_ENET3_IOADDR 0x83000000 -#define PCI_ENET3_MEMADDR 0x83000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ -#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM -#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM } - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_SYS_HZ 1000 - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 7 -#define CONFIG_SYS_ROMFAL 11 -#define CONFIG_SYS_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 121 - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFFE0000 -#define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h deleted file mode 100644 index 82ea172d7a..0000000000 --- a/include/configs/ADS860.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860 ADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board type */ -#define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */ - -/* Processor type */ -#define CONFIG_MPC860 1 - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* Console baudrate */ - -#if 0 -#define CONFIG_SYS_8XX_FACT 1526 /* 32.768 kHz crystal on XTAL/EXTAL */ -#else -#define CONFIG_SYS_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ -#endif - -#define CONFIG_SYS_PLPRCR (((CONFIG_SYS_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -#define CONFIG_DRAM_50MHZ 1 - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - -/* This is picked up again in fads.h */ -#define FADS_COMMANDS_ALREADY_DEFINED - -#include "../../board/fads/fads.h" - -#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h deleted file mode 100644 index 37bcac32c7..0000000000 --- a/include/configs/APC405.h +++ /dev/null @@ -1,428 +0,0 @@ -/* - * (C) Copyright 2005-2008 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_APCG405 1 /* ...on a APC405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_BOARD_EARLY_INIT_R 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */ -#define CONFIG_BOOTCOUNT_LIMIT 1 - -#undef CONFIG_BOOTARGS - -#define CONFIG_SYS_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \ - "fatload usb 0 300000 pImage.initrd" -#define CONFIG_SYS_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \ - "run ramargs addip addcon usbargs;" \ - "bootm 200000 300000" -#define CONFIG_SYS_USB_ARGS "setenv bootargs $(bootargs) usbboot=1" -#define CONFIG_SYS_BOOTLIMIT "3" -#define CONFIG_SYS_ALT_BOOTCOMMAND "run usb_self;reset" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=abg405\0" \ - "bd_type=abg405\0" \ - "serial#=AA0000\0" \ - "kernel_addr=fe000000\0" \ - "ramdisk_addr=fe100000\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname)::off panic=1\0" \ - "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \ - " $(optargs)\0" \ - "flash_self=run ramargs addip addcon;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \ - "bootm\0" \ - "rootpath=/tftpboot/abg405/target_root\0" \ - "img=/tftpboot/abg405/pImage\0" \ - "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000\0" \ - "ipaddr=10.0.111.111\0" \ - "netmask=255.255.0.0\0" \ - "serverip=10.0.0.190\0" \ - "splashimage=ffe80000\0" \ - "usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0" \ - "usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0" \ - "usbargs="CONFIG_SYS_USB_ARGS"\0" \ - "bootlimit="CONFIG_SYS_BOOTLIMIT"\0" \ - "altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self;reset" - -#define CONFIG_ETHADDR 00:02:27:8e:00:00 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_USB - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/* Only interrupt boot if space is pressed */ -/* If a long serial cable is connected but */ -/* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/* - * PCI stuff - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_SKIP_HOST_BRIDGE 1 -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE/ATA stuff - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0xFFF80000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */ - -/* - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 -#define CONFIG_SYS_FLASH_QUIET_TEST 1 -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \ - {0xfe000000, 0x500000}, \ - {0xffe80000, 0x180000} \ - } -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_BANKS_LIST { \ - CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \ - } -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the */ - /* beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/* - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */ -#define FLASH1_BA CONFIG_SYS_FLASH_BASE /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define PS2_BA 0xF0000600 /* PS/2 Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ -#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ -#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ -#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ -#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ - -#define CONFIG_SYS_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ -#define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP -#define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (PCMCIA Slot 1) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 5 (Epson VGA) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ -#define CONFIG_SYS_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 6 (PCMCIA Slot 2) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/ - -/* - * FPGA stuff - */ - -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_CTRL 0x008 -#define CONFIG_SYS_FPGA_CTRL2 0x00a - -/* FPGA Control Reg */ -#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 -#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/* - * LCD Setup - */ -#define CONFIG_SYS_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */ -#define CONFIG_SYS_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */ - -#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ - -/* Image information... */ -#define CONFIG_LCD_USED CONFIG_LCD_BIG - -#define CONFIG_SYS_LCD_MEM CONFIG_SYS_LCD_BIG_MEM -#define CONFIG_SYS_LCD_REG CONFIG_SYS_LCD_BIG_REG - -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20) - -/* - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* reserve some memory for BOOT limit info */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16) - -#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ -#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8) -#endif - -/* - * PCI OHCI controller - */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_PCI_OHCI 1 -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_USB_STORAGE 1 -#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/AR405.h b/include/configs/AR405.h deleted file mode 100644 index 11051798b6..0000000000 --- a/include/configs/AR405.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_AR405 1 /* ...on a AR405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -#if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ - "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" -#else -#define CONFIG_BOOTARGS "root=/dev/hda1 " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" - -#endif - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#undef CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xfff00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xfff00001 /* 1MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */ -#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Expension Bus) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16552) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */ -#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (FPGA regs) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */ -#define CONFIG_SYS_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */ - -/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x92015480 -#define CONFIG_SYS_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h deleted file mode 100644 index 54de966741..0000000000 --- a/include/configs/ASH405.h +++ /dev/null @@ -1,353 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_ASH405 1 /* ...on a ASH405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define DUART2_BA 0xF0000410 /* DUART Base Address */ -#define DUART3_BA 0xF0000418 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 - -#define CONFIG_SYS_DUART_RST (0x80000000 >> 14) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/Adder.h b/include/configs/Adder.h deleted file mode 100644 index 1a159ad4ab..0000000000 --- a/include/configs/Adder.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (C) 2004-2005 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Analogue&Micro Adder boards family. - * Tested on AdderII and Adder87x. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) -#define CONFIG_MPC875 -#endif - -#define CONFIG_ADDER /* Analogue&Micro Adder board */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_ETHER_ON_FEC1 -#define CONFIG_ETHER_ON_FEC2 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#define FEC_ENET -#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 -#ifdef CONFIG_MPC852T -#define CONFIG_SYS_8xx_CPUCLK_MAX 50000000 -#else -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 -#endif /* CONFIG_MPC852T */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* #undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */ - -#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ - -#define CONFIG_SYS_MAMR 0x00002114 - -/* - * 4096 Up to 4096 SDRAM rows - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ - -#define CONFIG_SYS_RESET_ADDRESS 0x09900000 - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_OR0_PRELIM 0xFF000774 -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/*----------------------------------------------------------------------- - * Internal Memory Map Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Configuration registers - */ -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ - SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) - -/* TBSCR - Time Base Status and Control Register */ -#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE) - -/* PISCR - Periodic Interrupt Status and Control */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/* PLPRCR - PLL, Low-Power, and Reset Control Register */ -/* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */ - -/* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR SCCR_RTSEL - -#define CONFIG_SYS_DER 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/AdderUSB.h b/include/configs/AdderUSB.h deleted file mode 100644 index b2435810b4..0000000000 --- a/include/configs/AdderUSB.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2006 CodeHermit. - * Bryan O'Donoghue - * - * Provides support for USB console on the Analogue & Micro Adder87x - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ADDERUSB__ -#define __ADDERUSB__ - -/* Include the board port */ -#include "Adder.h" - -#define CONFIG_USB_DEVICE /* Include UDC driver */ -#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */ -#define CONFIG_SYS_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */ -#define CONFIG_SYS_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Console is in env */ - -/* If you have a USB-IF assigned VendorID then you may wish to define - * your own vendor specific values either in BoardName.h or directly in - * usbd_vendor_info.h - */ - -/* -#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie" -#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot" -#define CONFIG_USBD_VENDORID 0xFFFF -#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF -#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE -*/ - -#endif /* __ADDERUSB_H__ */ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 09043435b4..838a0b18c3 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -7,6 +7,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * B4860 QDS board configuration file */ @@ -14,8 +17,42 @@ #define CONFIG_PHYS_64BIT #ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg +#ifndef CONFIG_NAND #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#else +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif +#endif #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -32,12 +69,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -47,6 +82,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ @@ -75,6 +111,24 @@ #define VSC3308_TX_ADDRESS 0x02 #define VSC3308_RX_ADDRESS 0x03 +/* IDT clock synthesizers */ +#define CONFIG_IDT8T49N222A +#define I2C_CH_IDT 0x9 + +#define IDT_SERDES1_ADDRESS 0x6E +#define IDT_SERDES2_ADDRESS 0x6C + +/* Voltage monitor on channel 2*/ +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_ZM7300 +#define I2C_MUX_CH_DPM 0xa +#define I2C_DPM_ADDR 0x28 + #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH @@ -106,8 +160,8 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -157,7 +211,16 @@ unsigned long get_board_ddr_clk(void); /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_NAND +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 @@ -165,6 +228,7 @@ unsigned long get_board_ddr_clk(void); #endif /* EEPROM */ +#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 @@ -185,8 +249,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 +#ifndef CONFIG_SPL_BUILD #define CONFIG_FSL_DDR_INTERACTIVE +#endif #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x51 @@ -275,12 +341,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 /* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 #define CONFIG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) @@ -372,7 +440,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -405,7 +477,7 @@ unsigned long get_board_ddr_clk(void); GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 @@ -426,7 +498,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif /* Use the HUSH parser */ @@ -488,15 +562,15 @@ unsigned long get_board_ddr_clk(void); * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ @@ -567,6 +641,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT @@ -575,9 +657,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_RMAN + /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SPIFLASH) /* @@ -585,7 +677,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -593,10 +685,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -606,10 +698,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -637,8 +729,8 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_PCI */ #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 -#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 +#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 +#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ @@ -655,6 +747,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif +#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR + /* * Environment */ @@ -684,6 +778,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * USB */ @@ -708,7 +808,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -717,7 +816,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data @@ -729,7 +827,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -748,9 +845,16 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE ulpi +#ifdef CONFIG_PPC_B4860 +#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ + "bank_intlv=cs0_cs1;" \ + "en_cpc:cpc2;" +#else +#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=null," \ - "bank_intlv=cs0_cs1;" \ + HWCONFIG \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ @@ -766,8 +870,7 @@ unsigned long get_board_ddr_clk(void); "ramdiskfile=b4860qds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ "fdtfile=b4860qds/b4860qds.dtb\0" \ - "bdev=sda3\0" \ - "c=ffe\0" + "bdev=sda3\0" /* For emulation this causes u-boot to jump to the start of the proof point app code automatically */ @@ -833,8 +936,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 0c5091957f..802e9cce1f 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -13,7 +13,7 @@ * History: * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -22,8 +22,7 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on a TQM5200 module */ #define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */ @@ -427,7 +426,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -445,8 +443,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ - #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if defined(CONFIG_CMD_KGDB) # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 948394eddd..6aaaaa43f0 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -11,6 +11,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_BSC9131RDB #define CONFIG_BSC9131 #define CONFIG_NAND_FSL_IFC @@ -21,15 +24,14 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_NAND -#define CONFIG_SPL #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -38,7 +40,7 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 @@ -55,8 +57,8 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_TSEC_ENET @@ -80,7 +82,7 @@ #define CONFIG_SYS_MEMTEST_END 0x01ffffff /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_SYS_DDR_RAW_TIMING #undef CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -181,18 +183,18 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ - | FTIM0_NAND_TWP(0x06) \ - | FTIM0_NAND_TWCHT(0x03) \ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ + | FTIM0_NAND_TWP(0x05) \ + | FTIM0_NAND_TWCHT(0x02) \ | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ - | FTIM1_NAND_TWBE(0x23) \ - | FTIM1_NAND_TRR(0x08) \ +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ + | FTIM1_NAND_TWBE(0x1E) \ + | FTIM1_NAND_TRR(0x07) \ | FTIM1_NAND_TRP(0x05)) #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x3f)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) + | FTIM2_NAND_TWHRE(0x11)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -221,7 +223,7 @@ extern unsigned long get_sdram_size(void); - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ /* Serial Port */ @@ -326,7 +328,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_IS_IN_NAND #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ @@ -361,7 +363,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -372,7 +373,6 @@ extern unsigned long get_sdram_size(void); /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -384,7 +384,12 @@ extern unsigned long get_sdram_size(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL #endif #define CONFIG_USB_EHCI @@ -397,6 +402,23 @@ extern unsigned long get_sdram_size(void); #define CONFIG_HAS_FSL_DR_USB #endif +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=ff800000.flash," +#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \ + "8m(kernel),512k(dtb),-(fs)" +/* + * Override partitions in device tree using info + * in "mtdparts" environment variable + */ +#ifdef CONFIG_CMD_MTDPARTS +#define CONFIG_FDT_FIXUP_PARTITIONS +#endif + /* * Environment Configuration */ @@ -411,6 +433,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 1ab6891585..59a8d1b5d1 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -11,6 +11,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_BSC9132QDS #define CONFIG_BSC9132 #endif @@ -22,7 +25,7 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 #ifdef CONFIG_SPIFLASH @@ -30,15 +33,21 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#endif +#ifdef CONFIG_NAND_SECBOOT +#define CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_NAND -#define CONFIG_SPL #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -47,7 +56,7 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 @@ -55,7 +64,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x8ff80000 +#define CONFIG_SYS_TEXT_BASE 0x8ff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -71,8 +80,8 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #define CONFIG_PCI /* Enable PCI/PCIE */ @@ -134,7 +143,7 @@ #define CONFIG_SYS_MEMTEST_END 0x01ffffff /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ @@ -224,6 +233,10 @@ combinations. this should be removed later #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +/* DSP CCSRBAR */ +#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT +#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT + /* * IFC Definitions */ @@ -344,13 +357,13 @@ combinations. this should be removed later #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 #endif /* Set up IFC registers for boot location NOR/NAND */ -#if defined(CONFIG_NAND) +#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR @@ -393,7 +406,7 @@ combinations. this should be removed later - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ /* Serial Port */ @@ -536,6 +549,7 @@ combinations. this should be removed later */ #if defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_RAMBOOT_SPIFLASH) @@ -547,10 +561,10 @@ combinations. this should be removed later #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_NAND) +#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ @@ -558,13 +572,9 @@ combinations. this should be removed later #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#define CONFIG_ENV_SECT_SIZE 0x20000 #endif #define CONFIG_LOADS_ECHO /* echo on for serial download */ @@ -592,6 +602,12 @@ combinations. this should be removed later #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -599,7 +615,6 @@ combinations. this should be removed later #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -610,7 +625,6 @@ combinations. this should be removed later /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq:1ms ticks */ /* @@ -623,7 +637,27 @@ combinations. this should be removed later #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," +#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ + "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ + "8m(kernel),512k(dtb),-(fs)" +#endif +/* + * Override partitions in device tree using info + * in "mtdparts" environment variable + */ +#ifdef CONFIG_CMD_MTDPARTS +#define CONFIG_FDT_FIXUP_PARTITIONS #endif /* @@ -641,6 +675,7 @@ combinations. this should be removed later #define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #ifdef CONFIG_SDCARD #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" @@ -699,4 +734,10 @@ combinations. this should be removed later #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h new file mode 100644 index 0000000000..e24b923368 --- /dev/null +++ b/include/configs/C29XPCIE.h @@ -0,0 +1,586 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * C29XPCIE board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + +#ifdef CONFIG_C29XPCIE +#define CONFIG_PPC_C29X +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#endif + +#ifdef CONFIG_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 8192 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ +#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#ifdef CONFIG_PCI +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI + +#define CONFIG_E1000 + +/* + * PCI Windows + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 1" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_TSEC_ENET +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_SYS_CLK_FREQ 66666666 + +#define CONFIG_HWCONFIG + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_PANIC_HANG + +/* DDR Setup */ +#define CONFIG_SYS_FSL_DDR3 +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x50 +#define CONFIG_SYS_DDR_RAW_TIMING + +/* DDR ECC Setup*/ +#define CONFIG_DDR_ECC +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + +#define CONFIG_SYS_SDRAM_SIZE 512 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* Platform SRAM setting */ +#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 +#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ + (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) +#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NO_FLASH +#endif + +/* + * IFC Definitions + */ +/* NOR Flash on IFC */ +#define CONFIG_SYS_FLASH_BASE 0xec000000 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ + +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ + +/* 16Bit NOR Flash - S29GL512S10TFI01 */ +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +/* CFI for NOR Flash */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) + +/* 8Bit NAND Flash - K9F1G08U0B */ +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ + | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ + | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ + FTIM0_NAND_TWP(0x0c) | \ + FTIM0_NAND_TWCHT(0x08) | \ + FTIM0_NAND_TWH(0x06)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ + FTIM1_NAND_TWBE(0x1d) | \ + FTIM1_NAND_TRR(0x08) | \ + FTIM1_NAND_TRP(0x0c)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x18)) +#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* Set up IFC registers for boot location NOR/NAND */ +#ifdef CONFIG_NAND +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +/* CPLD on IFC, selected by CS2 */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ + | CONFIG_SYS_CPLD_BASE) + +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#endif + +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) + +/* + * Config the L2 Cache as L2 SRAM + */ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#endif +#endif + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 + +/* I2C EEPROM */ +/* enable read and write access to EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_CMD_I2C + +/* eSPI - Enhanced SPI */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_EON +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_NET_MULTI +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +/* Default mode is RGMII mode */ +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#endif +#elif defined(CONFIG_NAND) +#define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE +#endif +#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#endif + +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "loadaddr=1000000\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=name/of/device-tree.dtb\0" \ + "othbootargs=ramdisk_size=600000\0" \ + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h deleted file mode 100644 index 40471b78a1..0000000000 --- a/include/configs/CANBT.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * (C) Copyright 2001 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405CR 1 /* This is a PPC405CR CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CANBT 1 /* ...on a CANBT board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \ - "bootm ffe00000 ffe80000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - -#define CONFIG_PHY_ADDR 0 /* PHY address */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use FLASH for environment variables */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ - -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (CAN/USB) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */ -#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Misc-IO/LEDs) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CAN Features) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in RAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h deleted file mode 100644 index 3906863f05..0000000000 --- a/include/configs/CATcenter.h +++ /dev/null @@ -1,754 +0,0 @@ -/* - * ueberarbeitet durch Christoph Seyfert - * - * (C) Copyright 2004-2005 DENX Software Engineering, - * Wolfgang Grandegger - * (C) Copyright 2003 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Credits: Stefan Roese, Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ -#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ -#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ -#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL -#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA -#endif - -/* Only one of the following two symbols must be defined (default is 25 MHz) - * CONFIG_PPCHAMELEON_CLK_25 - * CONFIG_PPCHAMELEON_CLK_33 - */ -#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_PPCHAMELEON_CLK_25 -#endif - -#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) -#error "* Two external frequencies (SysClk) are defined! *" -#endif - -#undef CONFIG_PPCHAMELEON_SMI712 - -/* - * Debug stuff - */ -#undef __DEBUG_START_FROM_SRAM__ -#define __DISABLE_MACHINE_EXCEPTION__ - -#ifdef __DEBUG_START_FROM_SRAM__ -#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#else -# error "* External frequency (SysClk) not defined! *" -#endif - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_VERSION_VARIABLE 1 /* add version variable */ -#define CONFIG_IDENT_STRING "1" - -#undef CONFIG_BOOTARGS - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -#define CONFIG_PPC4xx_EMAC -#undef CONFIG_EXT_PHY - -#define CONFIG_MII 1 /* MII PHY management */ -#ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */ -#else -#define CONFIG_PHY_ADDR 2 /* PHY address */ -#endif -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND0_BASE 0xFF400000 -#define CONFIG_SYS_NAND1_BASE 0xFF000000 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } -#define NAND_BIG_DELAY_US 25 - -/* For CATcenter there is only NAND on the module */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_NO_RB - -#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ -#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ -#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ -#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ - - -#define MACRO_NAND_DISABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_ENABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ - switch((unsigned long)nandptr) { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -/* TBD */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#if 0 /* No PCI on CATcenter */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ - -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#endif /* No PCI */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ -#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ -#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000 -#define CONFIG_ENV_SIZE_REDUND 0x2000 - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (External SRAM) initialization */ -/* Since this must replace NOR Flash, we use the same settings for CS0 */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x92015480 -#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x92015480 -#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ - -#ifdef CONFIG_PPCHAMELEON_SMI712 -/* - * Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -/*#define CONFIG_VIDEO_BMP_LOGO*/ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ -#define CONFIG_SYS_ISA_IO 0xE8000000 -/* see also drivers/video/videomodes.c */ -#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303 -#endif - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30] - EMAC0 input - * GPIO0[31] - EMAC1 reject packet as output - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 - -#define CONFIG_NO_SERIAL_EEPROM - -/*--------------------------------------------------------------------*/ - -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!----------------------------------------------------------------------- -! Defines for entry options. -! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that -! are plugged in the board will be utilized as non-ECC DIMMs. -!----------------------------------------------------------------------- -*/ -#undef AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) - -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#else -#error "* External frequency (SysClk) not defined! *" -#endif - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -/* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 -#define CONFIG_SYS_OPB_FREQ 55555555 -/* Model ME */ -#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 -#define CONFIG_SYS_OPB_FREQ 66666666 -#else -/* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 -#define CONFIG_SYS_OPB_FREQ 66666666 -#endif - -#endif /* CONFIG_NO_SERIAL_EEPROM */ - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nand" -#define CONFIG_JFFS2_PART_SIZE 0x00200000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support - * - * Note: fake mtd_id used, no linux mtd map file - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nand0=catcenter" -#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h deleted file mode 100644 index 323eac3fb4..0000000000 --- a/include/configs/CMS700.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2005 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CMS700.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_VOM405 1 /* ...on a VOM405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC8000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#undef CONFIG_HAS_ETH1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#undef CONFIG_PRAM /* no "protected RAM" */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * RTC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) - -#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CONFIG_SYS_RAMBOOT 1 -#else -# undef CONFIG_SYS_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_EEPROM_WREN 1 - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define CONFIG_SYS_PLD_BASE 0xf0000000 -#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ -/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ -/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ -/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ - -#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ -#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h deleted file mode 100644 index 9a083b7204..0000000000 --- a/include/configs/CPC45.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the CPC45 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_CPC45 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#define CONFIG_BOOTDELAY 5 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#if 1 -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#endif - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#else -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#endif - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) -#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CONFIG_SYS_HZ 1000 - - -/* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 0 -#define CONFIG_SYS_ROMFAL 8 - -#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ -#define CONFIG_SYS_BANK1_ROW 0 -#define CONFIG_SYS_BANK2_ROW 0 -#define CONFIG_SYS_BANK3_ROW 0 -#define CONFIG_SYS_BANK4_ROW 0 -#define CONFIG_SYS_BANK5_ROW 0 -#define CONFIG_SYS_BANK6_ROW 0 -#define CONFIG_SYS_BANK7_ROW 0 - -/* Bit-field values for MCCR2. - */ - -#define CONFIG_SYS_REFINT 0x2ec - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 160 - -/* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */ - -/* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 2 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 0 -#define CONFIG_SYS_REGDIMM 0 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ -#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - /* Warining: environment is not EMBEDDED in the ppcboot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000) -#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------*/ -/* CPC45 Memory Map */ -/*----------------------------------------------------------------------*/ -#define SRAM_BASE 0x80000000 /* SRAM base address */ -#define SRAM_END 0x801FFFFF -#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ -#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ -#define BCSR_BASE 0x80600000 /* board control / status registers */ -#define DISPLAY_BASE 0x80600040 /* DISPLAY base */ -#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */ -#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ - -#define CONFIG_SYS_SRAM_BASE SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1) - -/*---------------------------------------------------------------------*/ -/* CPC45 Control/Status Registers */ -/*---------------------------------------------------------------------*/ -#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00)) -#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01)) -#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02)) -#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03)) -#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04)) -#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05)) -#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06)) -#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06)) -#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06)) -#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07)) - -/* IRQ_ENA_1 bit definitions */ -#define I_ENA_1_IERA 0x80 /* INTA enable */ -#define I_ENA_1_IERB 0x40 /* INTB enable */ -#define I_ENA_1_IERC 0x20 /* INTC enable */ -#define I_ENA_1_IERD 0x10 /* INTD enable */ - -/* IRQ_STAT_1 bit definitions */ -#define I_STAT_1_INTA 0x80 /* INTA status */ -#define I_STAT_1_INTB 0x40 /* INTB status */ -#define I_STAT_1_INTC 0x20 /* INTC status */ -#define I_STAT_1_INTD 0x10 /* INTD status */ - -/* IRQ_ENA_2 bit definitions */ -#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */ -#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */ -#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */ -#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */ -#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */ -#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */ -#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */ -#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */ - -/* IRQ_STAT_2 bit definitions */ -#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */ -#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */ -#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */ -#define I_STAT_2_RTC 0x10 /* RTC IRQ status */ -#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */ -#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */ -#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */ -#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */ - -/* BOARD_CTRL bit definitions */ -#define USER_LEDS 2 /* 2 user LEDs */ - -#if (USER_LEDS == 4) -#define B_CTRL_WRSE 0x80 -#define B_CTRL_KRSE 0x40 -#define B_CTRL_FWRE 0x20 /* Flash write enable */ -#define B_CTRL_FWPT 0x10 /* Flash write protect */ -#define B_CTRL_LED3 0x08 /* LED 3 control */ -#define B_CTRL_LED2 0x04 /* LED 2 control */ -#define B_CTRL_LED1 0x02 /* LED 1 control */ -#define B_CTRL_LED0 0x01 /* LED 0 control */ -#else -#define B_CTRL_WRSE 0x80 -#define B_CTRL_KRSE 0x40 -#define B_CTRL_FWRE_1 0x20 /* Flash write enable */ -#define B_CTRL_FWPT_1 0x10 /* Flash write protect */ -#define B_CTRL_LED1 0x08 /* LED 1 control */ -#define B_CTRL_LED0 0x04 /* LED 0 control */ -#define B_CTRL_FWRE_0 0x02 /* Flash write enable */ -#define B_CTRL_FWPT_0 0x01 /* Flash write protect */ -#endif - -/* BOARD_STAT bit definitions */ -#define B_STAT_WDGE 0x80 -#define B_STAT_WDGS 0x40 -#define B_STAT_WRST 0x20 -#define B_STAT_KRST 0x10 -#define B_STAT_CSW3 0x08 /* sitch bit 3 status */ -#define B_STAT_CSW2 0x04 /* sitch bit 2 status */ -#define B_STAT_CSW1 0x02 /* sitch bit 1 status */ -#define B_STAT_CSW0 0x01 /* sitch bit 0 status */ - -/*---------------------------------------------------------------------*/ -/* Display addresses */ -/*---------------------------------------------------------------------*/ -#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */ -#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */ -#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */ - -#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */ -#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */ - -#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */ -#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */ -#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */ -#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */ -#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */ -#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */ -#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */ -#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_EARLY_PCI_INIT -#undef CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x82000000 -#define PCI_ENET0_MEMADDR 0x82000000 -#define PCI_PLX9030_IOADDR 0x82100000 -#define PCI_PLX9030_MEMADDR 0x82100000 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ - -#define CONFIG_I82365 - -#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000 - -#define CONFIG_PCMCIA_SLOT_A - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_RESET /* reset for IDE not supported */ -#define CONFIG_IDE_LED /* LED for IDE is supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400) - -#define CONFIG_DOS_PARTITION - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index bd9fd6ee7b..845ed81a46 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -2,7 +2,7 @@ * (C) Copyright 2005 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,9 +18,10 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ @@ -72,7 +73,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ @@ -111,8 +111,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h deleted file mode 100644 index 94ef16e06c..0000000000 --- a/include/configs/CPCI405.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#undef CONFIG_HAS_ETH1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ - -#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (Quart) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#if 1 /* test-only */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 8383c19359..ceddd7accc 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -2,7 +2,7 @@ * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,12 +18,13 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ #undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -94,7 +95,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ @@ -133,8 +133,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h deleted file mode 100644 index ec9f5aec4a..0000000000 --- a/include/configs/CPCI405AB.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ -#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ -#define CONFIG_CPCI405AB 1 /* ...and special AB version */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#undef CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING /* add command line history */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ - -#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -#define CONFIG_PRAM 0 /* use pram variable to overwrite */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC32) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC32 is 4096 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_LED_ADDR 0xF0000380 - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM/RTC) initialization */ -/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ -#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (optional Quart) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 6 (FPGA internal) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 -#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ -#define CONFIG_SYS_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */ -#define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR 0x0200 -#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400 -#define CONFIG_SYS_FPGA_MODE_1WIRE 0x1000 -#define CONFIG_SYS_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */ -#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL 0x4000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_1WIRE 0x1000 -#define CONFIG_SYS_FPGA_STATUS_SIM_OK 0x2000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h deleted file mode 100644 index ba926abdc0..0000000000 --- a/include/configs/CPCI405DT.h +++ /dev/null @@ -1,380 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ -#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/* Only interrupt boot if special string is typed */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ -#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ - -#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ -#endif - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_LED_ADDR 0xF0000380 - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM/RTC) initialization */ -/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ -#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (optional Quart) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 6 (FPGA internal) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 -#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h deleted file mode 100644 index cd2fa9514f..0000000000 --- a/include/configs/CPCI750.h +++ /dev/null @@ -1,611 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2004 esd gmbh Hannover - * - * - * from db64360.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - ************************************************************************/ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#ifndef __ASSEMBLY__ -#include <../board/Marvell/include/core.h> -#endif -/*-----------------------------------------------------*/ - -#include "../board/esd/cpci750/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_750FX /* we have a 750FX (override local.h) */ - -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ - -#define CONFIG_MV64360_ECC /* enable ECC support */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_PRE_INIT -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CONFIG_SYS_BOARD_NAME "CPCI750" -#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" - -/*#define CONFIG_SYS_HUSH_PARSER*/ -#define CONFIG_SYS_HUSH_PARSER - - -#define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ - -/* Define which ETH port will be used for connecting the network */ -#define CONFIG_SYS_ETH_PORT ETH_0 - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 1 -#define CONFIG_ETHER_PORT 0 - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#define CONFIG_BOOTDELAY 5 /* autoboot disabled */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS - -/* ----------------------------------------------------------------------------- - * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus - */ - -#define CONFIG_IPADDR "192.168.0.185" - -#define CONFIG_SERIAL "AA000001" -#define CONFIG_SERVERIP "10.0.0.79" -#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* ----------------------------------------------------------------------------- */ - - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - - -#define CONFIG_DOS_PARTITION - -#define CONFIG_USE_CPCIDVI - -#ifdef CONFIG_USE_CPCIDVI -#define CONFIG_VIDEO -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VIDEO_LOGO -#define CONFIG_I8042_KBD -#define CONFIG_SYS_ISA_IO 0 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */ - -#define CONFIG_PRAM 0 - -#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_TCLK 133000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - - /* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CONFIG_SYS_INIT_RAM_LOCK -/* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ -/* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR -/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/ -#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE 0xfff00000 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \ - CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \ - CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the cpci750 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ - -#undef MARVEL_STANDARD_CFG -#ifndef MARVEL_STANDARD_CFG -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -/*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ -#define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ - -#define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ -#define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ -#define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ -#define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ -#define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ - -#define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */ -#define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */ -#define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#endif - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */ -#define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* MPP Control MV64360 Appendix P P. 632*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */ -#define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */ -#define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */ -#define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */ -/* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */ - - -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ - -/* setup new config_value for MV64360 DDR-RAM To_do !! */ -/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ -/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ - /* GB has high prio. - idma has low prio - MPSC has low prio - pci has low prio 1 and 2 - cpu has high prio - Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices - ECC disable - non registered DRAM */ - /* 31:26 25:22 21:20 19 18 17 16 */ - /* 100001 0000 010 0 0 0 0 */ - /* refresh_count=0x400 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 0 1 0x400 */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ -#ifndef __ASSEMBLY__ -int ata_device(int dev); -#endif -#define ATA_DEVICE(dev) ata_device(dev) -#define CONFIG_ATAPI 1 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) - * IBAT4 and DBAT4 - * FIXME: ingo disable BATs for Linux Kernel - */ -/* #undef SETUP_HIGH_BATS_FX750 */ /* don't initialize BATS 4-7 */ -#define SETUP_HIGH_BATS_FX750 /* initialize BATS 4-7 */ - -#ifdef SETUP_HIGH_BATS_FX750 -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#else /* set em out of range for Linux !!!!!!!!!!! */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U - -#endif -/* FIXME: ingo end: disable BATs for Linux Kernel */ - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ - -#if 0 -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ -#endif - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x050 -#define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -/*#define CONFIG_SYS_L2*/ -#undef CONFIG_SYS_L2 - -/* #ifdef CONFIG_750CX*/ -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) -#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) -#define CONFIG_SYS_PLD_VER 0xf0e00000 - -#define CONFIG_OF_LIBFDT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h deleted file mode 100644 index dc4df29455..0000000000 --- a/include/configs/CPCIISER4.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "bootm fff00000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Uart 8bit) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */ -#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Uart 32bit) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ - -/* Memory Bank 3 (FPGA Reset) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h deleted file mode 100644 index a85a418fb1..0000000000 --- a/include/configs/CPU86.h +++ /dev/null @@ -1,633 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_CPU86 1 /* ...on a CPU86 board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#ifdef CONFIG_BOOT_ROM -#define CONFIG_SYS_TEXT_BASE 0xFF800000 -#else -#define CONFIG_SYS_TEXT_BASE 0xFF000000 -#endif - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK12 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 64000000 /* in Hz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT \ - "echo; " \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \ - "echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/*----------------------------------------------------------------------- - * I2C/EEPROM/RTC configuration - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE - -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configuration options - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash configuration - */ - -#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 -#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/*----------------------------------------------------------------------- - * Other areas to be mapped - */ - -/* CS3: Dual ported SRAM */ -#define CONFIG_SYS_DPSRAM_BASE 0x40000000 -#define CONFIG_SYS_DPSRAM_SIZE 0x00020000 - -/* CS4: DiskOnChip */ -#define CONFIG_SYS_DOC_BASE 0xF4000000 -#define CONFIG_SYS_DOC_SIZE 0x00100000 - -/* CS5: FDC37C78 controller */ -#define CONFIG_SYS_FDC37C78_BASE 0xF1000000 -#define CONFIG_SYS_FDC37C78_SIZE 0x00100000 - -/* CS6: Board configuration registers */ -#define CONFIG_SYS_BCRS_BASE 0xF2000000 -#define CONFIG_SYS_BCRS_SIZE 0x00010000 - -/* CS7: VME Extended Access Range */ -#define CONFIG_SYS_VMEEAR_BASE 0x80000000 -#define CONFIG_SYS_VMEEAR_SIZE 0x01000000 - -/* CS8: VME Standard Access Range */ -#define CONFIG_SYS_VMESAR_BASE 0xFE000000 -#define CONFIG_SYS_VMESAR_SIZE 0x01000000 - -/* CS9: VME Short I/O Access Range */ -#define CONFIG_SYS_VMESIOAR_BASE 0xFD000000 -#define CONFIG_SYS_VMESIOAR_SIZE 0x01000000 - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ - HRCW_BPS01 | HRCW_CS10PC01) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#if 0 -/* environment is in Flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_BOOT_ROM -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000) -# define CONFIG_ENV_SIZE 0x10000 -# define CONFIG_ENV_SECT_SIZE 0x10000 -#endif -#else -/* environment is in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_ENV_OFFSET 512 -#define CONFIG_ENV_SIZE (2048 - 512) -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ - SIUMCR_CS10PC01|SIUMCR_BCTLC10) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MPTPR 0x1F00 - -/*----------------------------------------------------------------------- - * PSRT - Refresh Timer Register 10-16 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PSRT 0x0f - -/*----------------------------------------------------------------------- - * PSRT - SDRAM Mode Register 10-10 - *----------------------------------------------------------------------- - */ - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit Boot ROM - * 1 60x GPCM 64 bit FLASH - * 2 60x SDRAM 64 bit SDRAM - * - */ - -#define CONFIG_SYS_MRS_OFFS 0x00000000 - -#ifdef CONFIG_BOOT_ROM -/* Bank 0 - Boot ROM - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 1 - FLASH - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - -#else /* CONFIG_BOOT_ROM */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 1 - Boot ROM - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - -#endif /* CONFIG_BOOT_ROM */ - - -/* Bank 2 - 60x bus SDRAM - */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL - -#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL -#endif /* CONFIG_SYS_RAMBOOT */ - -/* Bank 3 - Dual Ported SRAM - */ -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) - -/* Bank 4 - DiskOnChip - */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 5 - FDC37C78 controller - */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_8_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 6 - Board control registers - */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\ - ORxG_CSNT |\ - ORxG_SCY_5_CLK) - -/* Bank 7 - VME Extended Access Range - */ -#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) - -/* Bank 8 - VME Standard Access Range - */ -#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) - -/* Bank 9 - VME Short I/O Access Range - */ -#define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h deleted file mode 100644 index 7bbcb77af7..0000000000 --- a/include/configs/CPU87.h +++ /dev/null @@ -1,680 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_CPU87 1 /* ...on a CPU87 board */ -#define CONFIG_PCI -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#ifdef CONFIG_BOOT_ROM -#define CONFIG_SYS_TEXT_BASE 0xFF800000 -#else -#define CONFIG_SYS_TEXT_BASE 0xFF000000 -#endif - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ - -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK12 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT \ - "echo; " \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \ - "echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/*----------------------------------------------------------------------- - * I2C/EEPROM/RTC configuration - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE - -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - * Miscellaneous configuration options - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - #define CONFIG_CMD_PCI -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */ - -#define CONFIG_LOOPW - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash configuration - */ - -#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 -#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/*----------------------------------------------------------------------- - * Other areas to be mapped - */ - -/* CS3: Dual ported SRAM */ -#define CONFIG_SYS_DPSRAM_BASE 0x40000000 -#define CONFIG_SYS_DPSRAM_SIZE 0x00100000 - -/* CS4: DiskOnChip */ -#define CONFIG_SYS_DOC_BASE 0xF4000000 -#define CONFIG_SYS_DOC_SIZE 0x00100000 - -/* CS5: FDC37C78 controller */ -#define CONFIG_SYS_FDC37C78_BASE 0xF1000000 -#define CONFIG_SYS_FDC37C78_SIZE 0x00100000 - -/* CS6: Board configuration registers */ -#define CONFIG_SYS_BCRS_BASE 0xF2000000 -#define CONFIG_SYS_BCRS_SIZE 0x00010000 - -/* CS7: VME Extended Access Range */ -#define CONFIG_SYS_VMEEAR_BASE 0x60000000 -#define CONFIG_SYS_VMEEAR_SIZE 0x01000000 - -/* CS8: VME Standard Access Range */ -#define CONFIG_SYS_VMESAR_BASE 0xFE000000 -#define CONFIG_SYS_VMESAR_SIZE 0x01000000 - -/* CS9: VME Short I/O Access Range */ -#define CONFIG_SYS_VMESIOAR_BASE 0xFD000000 -#define CONFIG_SYS_VMESIOAR_SIZE 0x01000000 - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ - HRCW_BPS01 | HRCW_CS10PC01) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif - -#if 0 -/* environment is in Flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_BOOT_ROM -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000) -# define CONFIG_ENV_SIZE 0x10000 -# define CONFIG_ENV_SECT_SIZE 0x10000 -#endif -#else -/* environment is in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_ENV_OFFSET 512 -#define CONFIG_ENV_SIZE (2048 - 512) -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ - SIUMCR_CS10PC01|SIUMCR_BCTLC10) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 - -/* - * we use the same values for 32 MB, 128 MB and 256 MB SDRAM - * refresh rate = 7.68 uS (100 MHz Bus Clock) - */ - -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MPTPR 0x2000 - -/*----------------------------------------------------------------------- - * PSRT - Refresh Timer Register 10-16 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PSRT 0x16 - -/*----------------------------------------------------------------------- - * PSRT - SDRAM Mode Register 10-10 - *----------------------------------------------------------------------- - */ - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 10-column chips - */ -#define CONFIG_SYS_OR2_10COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A4 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ - PSDMR_SDAM_A17_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A6 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit Boot ROM - * 1 60x GPCM 64 bit FLASH - * 2 60x SDRAM 64 bit SDRAM - * - */ - -#define CONFIG_SYS_MRS_OFFS 0x00000000 - -#ifdef CONFIG_BOOT_ROM -/* Bank 0 - Boot ROM - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 1 - FLASH - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -#else /* CONFIG_BOOT_ROM */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 1 - Boot ROM - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -#endif /* CONFIG_BOOT_ROM */ - - -/* Bank 2 - 60x bus SDRAM - */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL - -#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL -#endif /* CONFIG_SYS_RAMBOOT */ - -/* Bank 3 - Dual Ported SRAM - */ -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_7_CLK |\ - ORxG_SETA) - -/* Bank 4 - DiskOnChip - */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_9_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 5 - FDC37C78 controller - */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_10_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 6 - Board control registers - */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\ - ORxG_CSNT |\ - ORxG_SCY_7_CLK) - -/* Bank 7 - VME Extended Access Range - */ -#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_7_CLK |\ - ORxG_SETA) - -/* Bank 8 - VME Standard Access Range - */ -#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_7_CLK |\ - ORxG_SETA) - -/* Bank 9 - VME Short I/O Access Range - */ -#define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_7_CLK |\ - ORxG_SETA) - -#endif /* __CONFIG_H */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h deleted file mode 100644 index fa3efabea4..0000000000 --- a/include/configs/CRAYL1.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite.. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_CRAYL1 -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ - -/* - * Note: I make an "image" from U-Boot itself, which prefixes 0x40 - * bytes of header info, hence start address is thus shifted. - */ -#define CONFIG_SYS_TEXT_BASE 0xFFFD0040 - -#define CONFIG_SYS_CLK_FREQ 25000000 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */ -#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to - * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) - #define CONFIG_PRAM 16 - */ -#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */ -#undef CONFIG_BOOTARGS - -/* Bootcmd is overridden by the bootscript in board/cray/L1 - */ -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_BOOTCOMMAND "dhcp" - -/* - * ..during experiments.. - #define CONFIG_SERVERIP 10.0.0.1 - #define CONFIG_ETHADDR 00:40:a6:80:14:5 - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SDRAM_BANK0 1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_IDENT_STRING "Cray L1" -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SOURCE 1 - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * how many time to fail & restart a net-TFTP before giving up & resetting - * the board hoping that a reset of net interface might help.. - */ -#define CONFIG_NET_RESET 5 - -/* - * bauds. Just to make it compile; in our case, I read the base_baud - * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn - * drives the system clock. - */ -#define CONFIG_SYS_BASE_BAUD 403225 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_DRAM_TEST 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ -#define CONFIG_ENV_OFFSET 0x3c8000 -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at - * 32meg-(128k+some_malloc_space+copy-of-ENV sector).. - */ -#define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */ -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */ -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE) -/* END ENVIRONNEMENT FLASH */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in OnChipMem ) - */ -#if 1 -/* On Chip Memory location */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#endif - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - */ -#define EEPROM_WRITE_ADDRESS 0xA0 -#define EEPROM_READ_ADDRESS 0xA1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/CU824.h b/include/configs/CU824.h deleted file mode 100644 index f6f05a45ac..0000000000 --- a/include/configs/CU824.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the CU824 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_CU824 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#if 1 -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#endif - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 4 - -#define CONFIG_SYS_NS16550_CLK (14745600 / 2) - -#define CONFIG_SYS_NS16550_COM1 0xFE800080 -#define CONFIG_SYS_NS16550_COM2 0xFE8000C0 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CONFIG_SYS_HZ 1000 - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 0 -#define CONFIG_SYS_ROMFAL 7 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_REFINT 430 /* Refresh interval */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 192 - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 2 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if 0 -#define CONFIG_ENV_ADDR 0xFF008000 -#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ -#else -#define CONFIG_ENV_ADDR 0xFFFC0000 -#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP -#define CONFIG_TULIP_USE_IO - -#define CONFIG_SYS_ETH_DEV_FN 0x7800 -#define CONFIG_SYS_ETH_IOBASE 0x00104000 - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define PCI_ENET0_IOADDR 0x00104000 -#define PCI_ENET0_MEMADDR 0x80000000 -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h deleted file mode 100644 index 2000a88805..0000000000 --- a/include/configs/DB64360.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2002 Datentechnik AG - Project: Dino - * - * - * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $ - * - ************************************************************************/ - -/************************************************************************* - * - * History: - * - * $Log: DB64360.h,v $ - * Revision 1.3 2003/04/26 04:58:13 brad - * Cosmetic changes and compiler warning cleanups - * - * Revision 1.2 2003/04/23 15:48:15 ingo - * mem. map output added - * - * Revision 1.1 2003/04/17 09:31:42 ias - * keymile changes 17_04_2003 - * - * Revision 1.10 2003/03/06 12:25:04 ias - * 750 FX CPU HID settings updated - * - * Revision 1.9 2003/03/03 16:14:36 ias - * cleanup compiler warnings of printf fuctions - * - * Revision 1.8 2003/03/03 15:11:44 ias - * Marvell MPSC-UART is working - * - * Revision 1.7 2003/02/26 12:15:45 ssu - * adapted default parameters to new board flash address - * - * Revision 1.6 2003/02/25 14:55:42 ssu - * changed default environment parameters - * - * Revision 1.5 2003/02/21 17:14:23 ias - * added extended SPD handling - * - * Revision 1.4 2003/01/14 09:16:08 ias - * PPCBoot for Marvel Beta 0.9 - * - * Revision 1.3 2002/12/03 13:56:26 ias - * Environment in flash support added - * - * Revision 1.2 2002/11/29 16:53:29 ias - * Flash support for STM added - * - * Revision 1.1 2002/11/29 13:36:31 ias - * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board - * - working DDRRAM (only 32MByte of 128MB Modul) - * - working I2C Driver for SPD EEPROM read - * - working DUART 16650 for Serial Console - * - working "console" - * - * - * - ************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64360/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -/* first ethernet */ -#define CONFIG_ETHADDR 64:36:00:00:00:01 - /* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:36:00:00:00:02 -/* in the atlantis 64360 we have only 2 ETH port on the board, -if we use PCI it has its own MAC addr */ - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64360_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_BOARD_NAME "DB64360" -#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 2 - -/* #undef CONFIG_ETHER_PORT_MII */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64360:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=db64360-1" -#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" -*/ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64360 core) */ -#define CONFIG_SYS_TCLK 133000000 - - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_750FX_HID0 0x8000c084 -#define CONFIG_SYS_750FX_HID1 0x54800000 -#define CONFIG_SYS_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64360 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ -#define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64360*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 -#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 -#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 - -/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64360 DDR-RAM !! */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#define CONFIG_SYS_INIT_CHAN1 -#define CONFIG_SYS_INIT_CHAN2 - -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h deleted file mode 100644 index e0f7e46728..0000000000 --- a/include/configs/DB64460.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64460/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -#define CONFIG_ETHADDR 64:46:00:00:00:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:46:00:00:00:02 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 64:46:00:00:00:03 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64460_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_BOARD_NAME "DB64460" -#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)" - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 3 - -/* #undef CONFIG_ETHER_PORT_MII */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64460:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=db64460-1" -#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" -*/ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64460 core) */ -#define CONFIG_SYS_TCLK 133000000 - - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_750FX_HID0 0x8000c084 -#define CONFIG_SYS_750FX_HID1 0x54800000 -#define CONFIG_SYS_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64460 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CONFIG_SYS_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */ -#define CONFIG_SYS_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64460*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 -#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 -#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 - -/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64460 DDR-RAM !! */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#define CONFIG_SYS_INIT_CHAN1 -#define CONFIG_SYS_INIT_CHAN2 - -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h deleted file mode 100644 index 872a2b4408..0000000000 --- a/include/configs/DP405.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_DP405 1 /* ...on a DP405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) - -#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CONFIG_SYS_RAMBOOT 1 -#else -# undef CONFIG_SYS_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ -/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ -/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ -/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h deleted file mode 100644 index 5b9e0d2f41..0000000000 --- a/include/configs/DU405.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_DU405 1 /* ...on a DU405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "bootm fff00000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ -#undef CONFIG_HAS_ETH1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_EDITENV -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_IDE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART_BA 0xF0300000 /* DUART Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ -#define SRAM_BA 0xF0200000 /* SRAM Base Address */ -#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */ -#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */ - -#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (DUART) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (CompactFlash IDE) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 5 (SRAM) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 6 (DURAG Bus IO Space) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/ - -/* Memory Bank 7 (DURAG Bus Mem Space) initialization */ -#define CONFIG_SYS_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */ - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/DU440.h b/include/configs/DU440.h deleted file mode 100644 index 08271132dc..0000000000 --- a/include/configs/DU440.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - * (C) Copyright 2008 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com - * - * based on the Sequoia board configuration by - * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - ********************************************************************** - * DU440.h - configuration for esd's DU440 board (Power PC440EPx) - ********************************************************************** - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_DU440 1 /* Board is esd DU440 */ -#define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 -#endif - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */ - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */ - -#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */ -#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */ -#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -#define CONFIG_SYS_PCI_IOBASE 0xe8000000 -#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH -#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */ - -#define CONFIG_SYS_USB2D0_BASE 0xe0000100 -#define CONFIG_SYS_USB_DEVICE 0xe0000000 -#define CONFIG_SYS_USB_HOST 0xe0000400 - -/* - * Initial RAM & stack pointer - */ -/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ - -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#undef CONFIG_SYS_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/* - * Video Port - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */ -#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ - -/* - * FLASH related - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0 /* environment starts at */ - /* the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ -#endif - -/* - * DDR SDRAM - */ -#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */ -#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ - /* 440EPx errata CHIP 11 */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define CONFIG_DDR_ECC /* Use ECC when available */ -#define SPD_EEPROM_ADDRESS {0x50} -#define CONFIG_PROG_SDRAM_TLB - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_PPC4XX_CH1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define IIC1_MCP3021_ADDR 0x4d -#define IIC1_USB2507_ADDR 0x2c -#define CONFIG_SYS_I2C_NOPROBES { {1, IIC1_USB2507_ADDR} } - -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 - -#define CONFIG_SYS_EEPROM_WREN 1 -#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52 - -/* - * standard dtt sensor configuration - bottom bit will determine local or - * remote sensor of the TMP401 - */ -#define CONFIG_DTT_SENSORS { 0, 1 } - -/* - * The PMC440 uses a TI TMP401 temperature sensor. This part - * is basically compatible to the ADM1021 that is supported - * by U-Boot. - * - * - i2c addr 0x4c - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT ouput disabled - * - local temp sensor enabled, min set to 0 deg, max set to 70 deg - * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg - */ -#define CONFIG_DTT_ADM1021 -#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } - -/* - * RTC stuff - */ -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ethrotate=no\0" \ - "hostname=du440\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_self=run ramargs addip addtty optargs;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \ - "bootm\0" \ - "rootpath=/tftpboot/du440/target_root_du440\0" \ - "img=/tftpboot/du440/uImage\0" \ - "kernel_addr=FFC00000\0" \ - "ramdisk_addr=FFE00000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 100000 FFFA0000 60000\0" \ - "" - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#ifndef __ASSEMBLY__ -int du440_phy_addr(int devnum); -#endif - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */ - -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#undef CONFIG_PHY_GIGE /* no GbE detection */ - -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_RX_ETH_BUFFER 128 - -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY1_ADDR du440_phy_addr(1) - -/* - * USB - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#define CONFIG_SYS_OHCI_BE_CONTROLLER - -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* Comment this out to enable USB 1.1 device */ -#define USB_2_0_DEVICE - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BMP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_USB - -#define CONFIG_SUPPORT_VFAT - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT -#define CONFIG_SYS_PCI_MASTER_INIT - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * External Bus Controller (EBC) Setup - */ -#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_CPLD_BASE 0xC0000000 -#define CONFIG_SYS_CPLD_RANGE 0x00000010 -#define CONFIG_SYS_DUMEM_BASE 0xC0100000 -#define CONFIG_SYS_DUMEM_RANGE 0x00100000 -#define CONFIG_SYS_DUIO_BASE 0xC0200000 -#define CONFIG_SYS_DUIO_RANGE 0x00010000 - -#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */ -#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */ -/* Memory Bank 0 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x04017200 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000) - -/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */ -#define CONFIG_SYS_EBC_PB1AP 0x018003c0 -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000) - -/* Memory Bank 2 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x018003c0 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000) - -/* Memory Bank 3 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x018003c0 -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000) - -/* Memory Bank 4 (DUMEM, 1MB) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x018053c0 -#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000) - -/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */ -#define CONFIG_SYS_EBC_PB5AP 0x018053c0 -#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000) - -/* - * NAND FLASH - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \ - CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS} - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#define CONFIG_SOURCE 1 - -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -#endif /* __CONFIG_H */ diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h deleted file mode 100644 index fb2f3befd6..0000000000 --- a/include/configs/ELPPC.h +++ /dev/null @@ -1,340 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define GTREGREAD(x) 0xffffffff /* needed for debug */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#define CONFIG_IPADDR 192.168.0.105 -#define CONFIG_SERVERIP 192.168.0.100 - -#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate */ - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp 1000000; " \ - "setenv bootargs root=ramfs console=ttyS00,9600 " \ - "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ - "${netmask}:${hostname}:eth0:none; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_JFFS2 - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -/* - * choose between COM1 and COM2 as serial console - */ -#define CONFIG_CONS_INDEX 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* dec. freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CONFIG_SYS_BOARD_ASM_INIT -#define CONFIG_MISC_INIT_R - -/* - * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP) - */ -#undef CONFIG_SYS_ADDRESS_MAP_A - -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000 - -#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000 - -#define CONFIG_SYS_ISA_MEM_BUS 0x00000000 -#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000 -#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000 - -#define CONFIG_SYS_PCI_IO_BUS 0x00800000 -#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000 -#define CONFIG_SYS_PCI_IO_SIZE 0x00400000 - -#define CONFIG_SYS_ISA_IO_BUS 0x00000000 -#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000 -#define CONFIG_SYS_ISA_IO_SIZE 0x00800000 - -/* driver defines FDC,IDE,... */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_USR_LED_BASE 0x78000000 -#define CONFIG_SYS_NVRAM_BASE 0xff000000 -#define CONFIG_SYS_UART_BASE 0xff400000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define MPC107_EUMB_ADDR 0xfce00000 -#define MPC107_EUMB_PI 0xfce41090 -#define MPC107_EUMB_GCR 0xfce41020 -#define MPC107_EUMB_IACKR 0xfce600a0 -#define MPC107_I2C_ADDR 0xfce03000 - -/* - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Flash mapping/organization on the MPC10x. - */ -#define FLASH_BASE0_PRELIM 0xff800000 -#define FLASH_BASE1_PRELIM 0xffc00000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1" -#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)" -*/ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ -#undef CONFIG_SYS_MEMTEST - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */ -#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ -#define CONFIG_ENV_ADDR 0x0 -#define CONFIG_ENV_MAP_ADRS 0xff000000 -#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */ -#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ - -/* - * Serial devices - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 24000000 -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8) - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO -#undef CONFIG_PCI_SCAN_SHOW - -/* - * Optional Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10)) -#define VIDEO_TSTC_FCT serial_tstc -#define VIDEO_GETC_FCT serial_getc - -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO - -/* - * Initial BATs - */ -#if 1 - -#define CONFIG_SYS_IBAT0L 0 -#define CONFIG_SYS_IBAT0U 0 -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U - -#define CONFIG_SYS_IBAT1L 0 -#define CONFIG_SYS_IBAT1U 0 -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -#define CONFIG_SYS_IBAT2L 0 -#define CONFIG_SYS_IBAT2U 0 -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -#define CONFIG_SYS_IBAT3L 0 -#define CONFIG_SYS_IBAT3U 0 -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#else - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U - -/* address range for flashes */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* ISA IO space */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* ISA memory space */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#endif - -/* - * Speed settings are board specific - */ -#define CONFIG_SYS_BUS_CLK 100000000 -#define CONFIG_SYS_CPU_CLK 400000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#if 1 -#define L2_INIT 0 /* cpu 750 CXe*/ -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#endif /* __CONFIG_H */ diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h deleted file mode 100644 index 69f44b1e62..0000000000 --- a/include/configs/ELPT860.h +++ /dev/null @@ -1,376 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** - * SPDX-License-Identifier: GPL-2.0+ -** -**===================================================================== -*/ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */ -#define CONFIG_MPC860T 1 -#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */ - -#define CONFIG_SYS_TEXT_BASE 0x02000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */ -#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* BOOT arguments */ -#define CONFIG_PREBOOT \ - "echo;" \ - "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootargs=setenv rootpath /tftp/${ipaddr}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:eth0:off panic=1\0" \ - "ramboot=tftp 400000 /home/paugaml/pMulti;" \ - "run ramargs;bootm\0" \ - "nfsboot=tftp 400000 /home/paugaml/uImage;" \ - "run rootargs;run nfsargs;run addip;bootm\0" \ - "" -#define CONFIG_BOOTCOMMAND "run ramboot" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */ -#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Environment Variables and Storages - */ -#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */ - -#undef CONFIG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */ -#undef CONFIG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */ - -#define CONFIG_ETHADDR 00:01:77:00:60:40 -#define CONFIG_IPADDR 192.168.0.30 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_GATEWAYIP 192.168.0.1 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x02000000 -#define CONFIG_SYS_NVRAM_BASE 0x03000000 - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# if defined(DEBUG) -# define CONFIG_SYS_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */ -# else -# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -# endif -#else -# if defined(DEBUG) -# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -# else -# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -# endif -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -# define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */ -#define CONFIG_SYS_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */ - /* 8 top NVRAM locations */ - -#if defined(CONFIG_ENV_IS_IN_NVRAM) -# define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */ -# define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC - * enabled - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler - *----------------------------------------------------------------------- - * - */ -#ifdef DEBUG -# define CONFIG_SYS_DER 0xFFE7400F /* Debug Enable Register */ -#else -# define CONFIG_SYS_DER 0 -#endif - -/* - * Init Memory Controller: - * ~~~~~~~~~~~~~~~~~~~~~~ - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE1_PRELIM CONFIG_SYS_SDRAM_BASE /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */ - -/* SDRAM timing: */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000000 - -#define CONFIG_SYS_OR1_PRELIM ((2 * CONFIG_SYS_PRELIM_OR_AM) | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2 and OR2 (NVRAM) - * - */ -#define NVRAM_BASE1_PRELIM CONFIG_SYS_NVRAM_BASE /* NVRAM bank #0 */ -#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */ - -#define CONFIG_SYS_OR2_PRELIM 0xFFF80160 -#define CONFIG_SYS_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h deleted file mode 100644 index 1d9d0df5a9..0000000000 --- a/include/configs/EP88x.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (C) 2005 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Embedded Planet EP88x boards. - * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC885 - -#define CONFIG_EP88X /* Embedded Planet EP88x board */ - -#define CONFIG_SYS_TEXT_BASE 0xFC000000 - -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */ -#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#define FEC_ENET -#endif /* CONFIG_FEC_ENET */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 100000000 -#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* #undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */ - -#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */ - -#define CONFIG_SYS_MAMR 0x00805000 - -/* - * 4096 Up to 4096 SDRAM rows - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ - -#define CONFIG_SYS_RESET_ADDRESS 0x09900000 - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CONFIG_SYS_FLASH_BASE 0xFC000000 -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_SYS_OR0_PRELIM 0xFC000160 -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V) - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/*----------------------------------------------------------------------- - * BCSR - */ -#define CONFIG_SYS_OR3_PRELIM 0xFF0005B0 -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V) - -#define CONFIG_SYS_BCSR 0xFA400000 - -/*----------------------------------------------------------------------- - * Internal Memory Map Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Configuration registers - */ -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ - SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) - -/* TBSCR - Time Base Status and Control Register */ -#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE) - -/* PISCR - Periodic Interrupt Status and Control */ -#define CONFIG_SYS_PISCR PISCR_PS - -/* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR SCCR_RTSEL - -#define CONFIG_SYS_DER 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h deleted file mode 100644 index 7d2fb47d80..0000000000 --- a/include/configs/ESTEEM192E.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */ -#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20) -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */ - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BAUDRATE 9600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \ - "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 " -/* - * Miscellaneous configurable options - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "BOOT: " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - - /*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) - -/*----------------------------------------------------------------------- - * SUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */ - - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 -/*#define CONFIG_SYS_DER 0x02002000 */ - - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH 0x00000160 - /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) */ - -#define CONFIG_SYS_OR0_REMAP 0x80000160 /*(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)*/ -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM 0xFC000E00 -#define CONFIG_SYS_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081) - -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL 0x18803112 -#define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h deleted file mode 100644 index fc8b921efc..0000000000 --- a/include/configs/EVB64260.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -#include -#endif - -#include "../board/evb64260/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 -#define CONFIG_SYS_LDSCRIPT "board/evb64260/u-boot.lds" - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ - -#undef CONFIG_ECC /* enable ECC support */ -/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#ifndef CONFIG_EVB64260_750CX -#define CONFIG_SYS_BOARD_NAME "EVB64260" -#else -#define CONFIG_SYS_BOARD_NAME "EVB64260-750CX" -#endif - -#define CONFIG_SYS_HUSH_PARSER - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp && " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none; && " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_CLK 100000000 /* 100 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_EVB64260_750CX -#define CONFIG_750CX -#define CONFIG_SYS_BROKEN_CL2 -#endif - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CONFIG_SYS_GT_REGS 0xf8000000 -#define CONFIG_SYS_DEV_BASE 0xfc000000 - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) - -#define CONFIG_SYS_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */ -#define CONFIG_SYS_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */ - -#define CONFIG_SYS_DEV0_PAR 0x20205093 -#define CONFIG_SYS_DEV1_PAR 0xcfcfffff -#define CONFIG_SYS_DEV2_PAR 0xc0059bd4 -#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c -#define CONFIG_SYS_32BIT_BOOT_PAR 0xc4a8241c - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ - /* DMAAck[1:0] GNT0[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ - /* REQ0[1:0] GNT0[1:0] */ -#endif -#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ - /* DMAReq[4] DMAAck[4] WDNMI WDE */ -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ - /* DMAAck[1:0] GNT1[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ - /* GPP[22] (RS232IntB or PCI1Int) */ - /* GPP[21] (RS323IntA) */ - /* BClkIn */ - /* REQ1[1:0] GNT1[1:0] */ -#endif - -#if 0 /* Wrong?? NTL */ -# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ - /* GPP[27:26] Int[1:0] */ -#else -# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ -#endif - -# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - -#if 0 /* Wrong?? - NTL */ -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6 -#else -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ - /* gpp[27:26] */ - /* gpp[22:21] */ - -# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 0 - pci use buffer 1,1 - cpu use buffer 0 - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 110110 00 111 0 0 00 1 */ - /* refresh_count=0x200 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ -#endif - -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#define CONFIG_SYS_INIT_CHAN1 -#define CONFIG_SYS_INIT_CHAN2 - -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 - -#define CONFIG_SYS_NS16550_REG_SIZE -4 - -#define CONFIG_SYS_NS16550_CLK 3686400 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_DUART_IO + 0) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_DUART_IO + 0x20) - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C speed and slave address (for compatability) defaults */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* I2C addresses for the two DIMM SPD chips */ -#ifndef CONFIG_EVB64260_750CX -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 -#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ -#define DIMM0_I2C_ADDR 0x54 -#define DIMM1_I2C_ADDR 0x54 -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#ifdef CONFIG_750CX -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h deleted file mode 100644 index d1b9f97b2e..0000000000 --- a/include/configs/EXBITGEN.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -/* I2C configuration */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ - -/* environment is in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#undef CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_IN_NVRAM - -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 /* 1010110 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */ -#define CONFIG_ENV_OFFSET 4 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 350 /* that is 350 bytes only! */ -#endif - -#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ -/* Explanation: - autbooting is altogether disabled and cannot be - enabled if CONFIG_BOOTDELAY is negative. - If you want shorter bootdelay, then - - "setenv bootdelay " to the proper value -*/ - -#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000" - -#define CONFIG_BOOTARGS "root=/dev/ram " \ - "ramdisk_size=32768 " \ - "console=ttyS0,115200 " \ - "ram=128M debug" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_PPC4xx_EMAC -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* UART configuration */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* Default baud rate */ -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_PCI /* no pci support */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 -#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH0_BASE 0xFFF80000 -#define CONFIG_SYS_FLASH0_SIZE 0x00080000 -#define CONFIG_SYS_FLASH1_BASE 0x20000000 -#define CONFIG_SYS_FLASH1_SIZE 0x02000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_RAMSTART -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 5 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */ -#endif - -/* On Chip Memory location/size */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/* Global info and initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h deleted file mode 100644 index 35c0c7eed1..0000000000 --- a/include/configs/FADS823.h +++ /dev/null @@ -1,474 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia io remapping - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot - * ff000000 -> ff00ffff : IMAP internal in the cpu - * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia - * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot - * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot -*/ - -#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 -#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x02800000 -#define BCSR_ADDR ((uint) 0xff010000) -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ -#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ - -#define CONFIG_VIDEO 1 /* To enable video controller support */ -#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */ - -/* Video related */ - -#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ -#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */ -#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */ -#define CONFIG_VIDEO_SIZE (2*1024*1024) -/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */ - -/* Wireless 56Khz 4PPM keyboard on SMCx */ - -/*#define CONFIG_KEYBOARD 1 */ -#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 -#define CONFIG_MPC823FADS 1 -#define CONFIG_FADS 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 - -/* Set the CPU speed to 50Mhz on the FADS */ - -#if 0 -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#else -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#define CONFIG_SYS_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */ -#endif -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTCOMMAND \ -"bootp ;" \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ -"bootm" -#else -#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13a01114 - -/* values according to the manual */ - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 -#define CONFIG_SCC2_ENET 1 -#undef CONFIG_FEC_ENET -#undef CONFIG_CPM_IIC -#undef CONFIG_UCODE_PATCH - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 1 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CONFIG_SYS_DAUGHTERBOARD - -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h deleted file mode 100644 index 559a83f527..0000000000 --- a/include/configs/FADS850SAR.h +++ /dev/null @@ -1,417 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom - * ff000000 -> ff00ffff : IMAP internal in the cpu - * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom - * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC850 1 -#define CONFIG_MPC850SAR 1 -#define CONFIG_FADS 1 - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - -#if 0 -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 50000000 /* 50 MHz in */ -#else -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#endif -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */ -#define CONFIG_BOOTARGS " " - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ -#define CONFIG_SYS_FLASH_BASE 0x02800000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << 20) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - - -#define BCSR_ADDR ((uint) 0x02100000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13a01114 - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 2 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CONFIG_SYS_DAUGHTERBOARD - -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h deleted file mode 100644 index ed7484bd1c..0000000000 --- a/include/configs/FADS860T.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* board type */ -#define CONFIG_FADS 1 /* old/new FADS + new ADS */ - -/* processor type */ -#define CONFIG_MPC860T 1 /* 860T */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#if 0 /* old FADS */ -# define CONFIG_SYS_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ -#else /* new FADS */ -# define CONFIG_SYS_8XX_FACT 10 /* 5 MHz oscillator on EXTCLK */ -#endif - -#define CONFIG_SYS_PLPRCR (((CONFIG_SYS_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -#include "../../board/fads/fads.h" - -#ifdef USE_REAL_FLASH_VALUES -/* - * These values fit our FADS860T ... - * The "default" behaviour with 1Mbyte initial doesn't work for us! - */ -#undef CONFIG_SYS_OR0_PRELIM -#undef CONFIG_SYS_BR0_PRELIM -#define CONFIG_SYS_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ -#define CONFIG_SYS_BR0_PRELIM 0x02800001 /* Real values for the board */ -#endif - -#define CONFIG_SYS_DAUGHTERBOARD /* FADS has processor-specific daughterboard */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h deleted file mode 100644 index a5d1a9c9d3..0000000000 --- a/include/configs/FLAGADM.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ -#define CONFIG_8xx_CONS_SMC2 1 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#undef CONFIG_CLOCKS_IN_MHZ - -#if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram ip=off panic=1;" \ - "bootm 40040000 400e0000" -#else -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1" -#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000" -#endif /* 0|1*/ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_IMI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "EEG> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x40040000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This is a litlebit wasteful, but one sector is 128kb and we have to - * assigne a whole sector for the environment, so that we can safely - * erase and write it without disturbing the boot sector - */ -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif -#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before - * running in RAM. - */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \ - SIUMCR_MLRC01 | SIUMCR_GB5E) -#define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit miltiplier of 0x00b i.e. operation clock is - * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz - */ -#define CONFIG_SYS_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -#define CONFIG_SYS_DER 0 - -/* - * In the Flaga DM we have: - * Flash on BR0/OR0/CS0a at 0x40000000 - * Display on BR1/OR1/CS1 at 0x20000000 - * SDRAM on BR2/OR2/CS2 at 0x00000000 - * Free BR3/OR3/CS3 - * DSP1 on BR4/OR4/CS4 at 0x80000000 - * DSP2 on BR5/OR5/CS5 at 0xa0000000 - * - * For now we just configure the Flash and the SDRAM and leave the others - * untouched. -*/ - -#define CONFIG_SYS_FLASH_PROTECTION 0 - -#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_OR_AM 0xff000000 /* OR addr mask */ -#define CONFIG_SYS_OR_ATM 0x00006000 - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \ - OR_SCY_3_CLK | OR_TRLX | OR_EHTR ) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR2 and OR2 (SDRAM) - * - */ -#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM ( 0x00000800 ) - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CONFIG_SYS_BR2 CONFIG_SYS_BR2_PRELIM -#define CONFIG_SYS_OR2 CONFIG_SYS_OR2_PRELIM - -/* - * MAMR settings for SDRAM - */ -#define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \ - | MAMR_G0CLA_A11) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 0x0F000000 - -/* - * BR4 and OR4 (DSP1) - * - * We do not wan't preliminary setup of the DSP, anyway we need the - * UPMB setup correctly before we can access the DSP. - * -*/ -#define DSP_BASE 0x80000000 - -#define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS) -#define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V ) - -#endif /* __CONFIG_H */ diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h deleted file mode 100644 index 002a80413e..0000000000 --- a/include/configs/FPS850L.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=FPS850L\0" \ - "bootfile=FPS850L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=FPS850L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h deleted file mode 100644 index 5eaf2f862f..0000000000 --- a/include/configs/FPS860L.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=FPS860L\0" \ - "bootfile=FPS860L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=FPS860L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h deleted file mode 100644 index 5a74abcd41..0000000000 --- a/include/configs/G2000.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_G2000 1 /* ...on a PLU405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#if 0 /* test-only */ -#define CONFIG_BAUDRATE 115200 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_PREBOOT - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "flash_nfs=run nfsargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addmisc;bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/g2000/pImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff900000\0" \ - "pciconfighost=yes\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY1_ADDR 1 /* PHY address */ - -#if 0 /* test-only */ -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if 0 /* test-only */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------------*/ -/* adding Ethernet setting: FTS OUI 00:11:0B */ -/*----------------------------------------------------------------------------*/ -#define CONFIG_ETHADDR 00:11:0B:00:00:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:11:0B:00:00:02 -#define CONFIG_IPADDR 10.48.8.178 -#define CONFIG_IP1ADDR 10.48.8.188 -#define CONFIG_NETMASK 255.255.255.128 -#define CONFIG_SERVERIP 10.48.8.138 - -/*----------------------------------------------------------------------- - * RTC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -#if 0 /* test-only */ -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#if 0 /* APC405 */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* test-only...*/ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */ -#else /* G2000 */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* test-only...*/ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */ -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#if 1 /* test-only */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#else /* DEFAULT: environment in flash, using redundand flash sectors */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_ADDR 0xFFFA0000 /* environment starts before u-boot */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k bytes may be used for env vars*/ - -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -/* CAT24WC08/16... */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Intel Strata Flash) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFF87A000 /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 1 ( Power TAU) initialization */ -/* #define CONFIG_SYS_EBC_PB1AP 0x04041000 */ -/* #define CONFIG_SYS_EBC_PB1CR 0xF0018000 */ /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_EBC_PB1AP 0x00000000 -#define CONFIG_SYS_EBC_PB1CR 0x00000000 - -/* Memory Bank 2 (Intel Flash) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x00000000 -#define CONFIG_SYS_EBC_PB2CR 0x00000000 - -/* Memory Bank 3 (NAND) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x92015480 -#define CONFIG_SYS_EBC_PB3CR 0xF40B8000 /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */ - -/* Memory Bank 4 (FPGA regs) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x00000000 -#define CONFIG_SYS_EBC_PB4CR 0x00000000 /* leave it blank */ - -#define CONFIG_SYS_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - * - * following GPIO setting changed for G20000, 080304 - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40005555 -#define CONFIG_SYS_GPIO0_OSRH 0x40000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 1 -#define PLLMR0_DEFAULT PLLMR0_266_66_33_33 -#define PLLMR1_DEFAULT PLLMR1_266_66_33_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h deleted file mode 100644 index 06c0e50c96..0000000000 --- a/include/configs/GEN860T.h +++ /dev/null @@ -1,716 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config_GEN860T.h - board specific configuration options - */ - -#ifndef __CONFIG_GEN860T_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC860 -#define CONFIG_GEN860T - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* - * Identify the board - */ -#if !defined(CONFIG_SC) -#define CONFIG_IDENT_STRING " B2" -#else -#define CONFIG_IDENT_STRING " SC" -#endif - -/* - * Don't depend on the RTC clock to determine clock frequency - - * the 860's internal rtc uses a 32.768 KHz clock which is - * generated by the DS1337 - and the DS1337 clock can be turned off. - */ -#if !defined(CONFIG_SC) -#define CONFIG_8xx_GCLK_FREQ 66600000 -#else -#define CONFIG_8xx_GCLK_FREQ 48000000 -#endif - -/* - * The RS-232 console port is on SMC1 - */ -#define CONFIG_8xx_CONS_SMC1 -#define CONFIG_BAUDRATE 38400 - -/* - * Print console information - */ -#undef CONFIG_SYS_CONSOLE_INFO_QUIET - -/* - * Set the autoboot delay in seconds. A delay of -1 disables autoboot - */ -#define CONFIG_BOOTDELAY 5 - -/* - * Pass the clock frequency to the Linux kernel in units of MHz - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_PREBOOT \ - "echo;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* - * Turn off echo for serial download by default. Allow baud rate to be changed - * for downloads - */ -#undef CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Turn off the watchdog timer - */ -#undef CONFIG_WATCHDOG - -/* - * Do not reboot if a panic occurs - */ -#define CONFIG_PANIC_HANG - -/* - * Enable the status LED - */ -#define CONFIG_STATUS_LED - -/* - * Reset address. We pick an address such that when an instruction - * is executed at that address, a machine check exception occurs - */ -#define CONFIG_SYS_RESET_ADDRESS ((ulong) -1) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * The GEN860T network interface uses the on-chip 10/100 FEC with - * an Intel LXT971A PHY connected to the 860T's MII. The PHY's - * MII address is hardwired on the board to zero. - */ -#define CONFIG_FEC_ENET -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII -#define CONFIG_MII_INIT 1 -#define CONFIG_PHY_ADDR 0 - -/* - * Set default IP stuff just to get bootstrap entries into the - * environment so that we can source the full default environment. - */ -#define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.201 -#define CONFIG_IPADDR 10.0.4.111 - -/* - * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to - * the MPC860T I2C interface. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ -#define CONFIG_ENV_EEPROM_SIZE (32 * 1024) - -/* - * Enable I2C and select the hardware/software driver - */ -#define CONFIG_HARD_I2C 1 /* CPM based I2C */ -#undef CONFIG_SYS_I2C_SOFT /* Bit-banged I2C */ - -#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */ -#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */ -#endif - -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SDA; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SCL; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -/* - * Allow environment overwrites by anyone - */ -#define CONFIG_ENV_OVERWRITE - -#if !defined(CONFIG_SC) -/* - * The MPC860's internal RTC is horribly broken in rev D masks. Three - * internal MPC860T circuit nodes were inadvertently left floating; this - * causes KAPWR current in power down mode to be three orders of magnitude - * higher than specified in the datasheet (from 10 uA to 10 mA). No - * reasonable battery can keep that kind RTC running during powerdown for any - * length of time, so we use an external RTC on the I2C bus instead. - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -#else -/* - * No external RTC on SC variant, so we're stuck with the internal one. - */ -#define CONFIG_RTC_MPC8xx -#endif - -/* - * Power On Self Test support - */ -#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_SPR ) - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_MII -#define CONFIG_CMD_BEDBUG - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - -/* - * There is no IDE/PCMCIA hardware support on the board. - */ -#undef CONFIG_IDE_PCMCIA -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -/* - * Enable the call to misc_init_r() for miscellaneous platform - * dependent initialization. - */ -#define CONFIG_MISC_INIT_R - -/* - * Enable call to last_stage_init() so we can twiddle some LEDS :) - */ -#define CONFIG_LAST_STAGE_INIT - -/* - * Virtex2 FPGA configuration support - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_VIRTEX2 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK - -/* - * Verbose help from command monitor. - */ -#define CONFIG_SYS_LONGHELP -#if !defined(CONFIG_SC) -#define CONFIG_SYS_PROMPT "B2> " -#else -#define CONFIG_SYS_PROMPT "SC> " -#endif - - -/* - * Use the "hush" command parser - */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Set buffer size for console I/O - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif - -/* - * Print buffer size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * Maximum number of arguments that a command can accept - */ -#define CONFIG_SYS_MAXARGS 16 - -/* - * Boot argument buffer size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Default memory test range - */ -#define CONFIG_SYS_MEMTEST_START 0x0100000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (128 * 1024)) - -/* - * Select the more full-featured memory test - */ -#define CONFIG_SYS_ALT_MEMTEST - -/* - * Default load address - */ -#define CONFIG_SYS_LOAD_ADDR 0x01000000 - -/* - * Set decrementer frequency (1 ms ticks) - */ -#define CONFIG_SYS_HZ 1000 - -/* - * Device memory map (after SDRAM remap to 0x0): - * - * CS Device Base Addr Size - * ---------------------------------------------------- - * CS0* Flash 0x40000000 64 M - * CS1* SDRAM 0x00000000 16 M - * CS2* Disk-On-Chip 0x50000000 32 K - * CS3* FPGA 0x60000000 64 M - * CS4* SelectMap 0x70000000 32 K - * CS5* Mil-Std 1553 I/F 0x80000000 32 K - * CS6* Unused - * CS7* Unused - * IMMR 860T Registers 0xfff00000 - */ - -/* - * Base addresses and block sizes - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -#define SDRAM_BASE 0x00000000 -#define SDRAM_SIZE (64 * 1024 * 1024) - -#define FLASH_BASE 0x40000000 -#define FLASH_SIZE (16 * 1024 * 1024) - -#define DOC_BASE 0x50000000 -#define DOC_SIZE (32 * 1024) - -#define FPGA_BASE 0x60000000 -#define FPGA_SIZE (64 * 1024 * 1024) - -#define SELECTMAP_BASE 0x70000000 -#define SELECTMAP_SIZE (32 * 1024) - -#define M1553_BASE 0x80000000 -#define M1553_SIZE (64 * 1024) - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE SDRAM_BASE - -/* - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE FLASH_SIZE -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* - * The timeout values are for an entire chip and are in milliseconds. - * Yes I know that the write timeout is huge. Accroding to the - * datasheet a single byte takes 630 uS (round to 1 ms) max at worst - * case VCC and temp after 100K programming cycles. It works out - * to 280 minutes (might as well be forever). - */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 5000) -#define CONFIG_SYS_FLASH_WRITE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1) - -/* - * Allow direct writes to FLASH from tftp transfers (** dangerous **) - */ -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/* - * Reserve memory for U-Boot. - */ -#define CONFIG_SYS_MAX_UBOOT_SECTS 4 -#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -/* - * Select environment placement. NOTE that u-boot.lds must - * be edited if this is changed! - */ -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_IS_IN_EEPROM - -#if defined(CONFIG_ENV_IS_IN_EEPROM) -#define CONFIG_ENV_SIZE (2 * 1024) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_EEPROM_SIZE - (8 * 1024)) -#else -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE - -/* - * This ultimately gets passed right into the linker script, so we have to - * use a number :( - */ -#define CONFIG_ENV_OFFSET 0x060000 -#endif - -/* - * Reserve memory for malloc() - */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of above value */ -#endif - -/*------------------------------------------------------------------------ - * SYPCR - System Protection Control UM 11-9 - * ----------------------------------------------------------------------- - * SYPCR can only be written once after reset! - * - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWE | \ - SYPCR_SWRI | \ - SYPCR_SWP \ - ) -#else -#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWP \ - ) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration UM 11-6 - *----------------------------------------------------------------------- - * Set debug pin mux, enable SPKROUT and GPLB5*. - */ -#define CONFIG_SYS_SIUMCR ( SIUMCR_DBGC11 | \ - SIUMCR_DBPC11 | \ - SIUMCR_MLRC11 | \ - SIUMCR_GB5E \ - ) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control UM 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freeze enabled - */ -#define CONFIG_SYS_TBSCR ( TBSCR_REFA | \ - TBSCR_REFB | \ - TBSCR_TBF \ - ) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register UM 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC ( RTCSC_SEC | \ - RTCSC_ALR | \ - RTCSC_RTF | \ - RTCSC_RTE \ - ) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control UM 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR ( PISCR_PS | \ - PISCR_PITF \ - ) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit. Set MF for 1:2:1 mode. - */ -#define CONFIG_SYS_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \ - PLPRCR_SPLSS | \ - PLPRCR_TEXPS | \ - PLPRCR_TMIST \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register UM 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - -#if !defined(CONFIG_SC) -#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ - SCCR_DFNL000 | \ - SCCR_DFNH000 \ - ) -#else -#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ - SCCR_DFNL000 | \ - SCCR_DFNH000 | \ - SCCR_RTDIV | \ - SCCR_RTSEL \ - ) -#endif - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register UM 37-46 - *----------------------------------------------------------------------- - * Mask all events that can cause entry into debug mode - */ -#define CONFIG_SYS_DER 0 - -/* - * Initialize Memory Controller: - * - * BR0 and OR0 (FLASH memory) - */ -#define FLASH_BASE0_PRELIM FLASH_BASE - -/* - * Flash address mask - */ -#define CONFIG_SYS_PRELIM_OR_AM 0xfe000000 - -/* - * FLASH timing: - * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 - */ -#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_2_CLK | \ - OR_TRLX | \ - OR_EHTR \ - ) - -#define CONFIG_SYS_OR0_PRELIM ( CONFIG_SYS_PRELIM_OR_AM | \ - CONFIG_SYS_OR_TIMING_FLASH \ - ) - -#define CONFIG_SYS_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ - BR_MS_GPCM | \ - BR_PS_8 | \ - BR_V \ - ) - -/* - * SDRAM configuration - */ -#define CONFIG_SYS_OR1_AM 0xfc000000 -#define CONFIG_SYS_OR1 ( (CONFIG_SYS_OR1_AM & OR_AM_MSK) | \ - OR_CSNT_SAM \ - ) - -#define CONFIG_SYS_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_32 | \ - BR_V \ - ) - -/* - * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank - * of 256 MBit SDRAM - */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 - -/* - * Periodic timer for refresh @ 33 MHz system clock - */ -#define CONFIG_SYS_MAMR_PTA 64 - -/* - * MAMR settings for SDRAM - */ -#define CONFIG_SYS_MAMR_8COL ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | \ - MAMR_DSA_1_CYCL | \ - MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | \ - MAMR_WLFA_1X | \ - MAMR_TLFA_4X \ - ) - -/* - * CS2* configuration for Disk On Chip: - * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, - * no burst. - */ -#define CONFIG_SYS_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_CSNT_SAM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_2_CLK | \ - OR_TRLX | \ - OR_EHTR \ - ) - -#define CONFIG_SYS_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V \ - ) - -/* - * CS3* configuration for FPGA: - * 33 MHz bus with SCY=15, no burst. - * The FPGA uses TA and TEA to terminate bus cycles, but we - * clear SETA and set the cycle length to a large number so that - * the cycle will still complete even if there is a configuration - * error that prevents TA from asserting on FPGA accesss. - */ -#define CONFIG_SYS_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ - OR_SCY_15_CLK | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ - BR_PS_32 | \ - BR_MS_GPCM | \ - BR_V \ - ) -/* - * CS4* configuration for FPGA SelectMap configuration interface. - * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge - * of GCLK1_50 - */ -#define CONFIG_SYS_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_G5LS | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ - BR_PS_8 | \ - BR_MS_UPMB | \ - BR_V \ - ) - -/* - * CS5* configuration for Mil-Std 1553 databus interface. - * 33 MHz bus, GPCM, no burst. - * The 1553 interface uses TA and TEA to terminate bus cycles, - * but we clear SETA and set the cycle length to a large number so that - * the cycle will still complete even if there is a configuration - * error that prevents TA from asserting on FPGA accesss. - */ -#define CONFIG_SYS_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_SCY_15_CLK | \ - OR_EHTR | \ - OR_TRLX | \ - OR_CSNT_SAM | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V \ - ) - -/* - * FEC interrupt assignment - */ -#define FEC_INTERRUPT SIU_LEVEL1 - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_GEN860T_H */ diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h deleted file mode 100644 index c5ca279d7d..0000000000 --- a/include/configs/GENIETV.h +++ /dev/null @@ -1,356 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 30000000 -> 300fffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - Lon (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ -#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ - -#define CONFIG_SYS_ALLOC_DPRAM /* Use dynamic DPRAM allocation */ - -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ - -/*#define CONFIG_VIDEO 1 / To enable the video initialization */ -/*#define CONFIG_VIDEO_ADDR 0x00200000 */ -/*#define CONFIG_HARD_I2C 1 / I2C with hardware support */ -/*#define CONFIG_PCMCIA 1 / To enable the PCMCIA initialization */ - -/*#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 */ -/*#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 */ -/*#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 */ -/*#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 */ - -/* Video related */ - -/*#define CONFIG_VIDEO_LOGO 1 / Show the logo */ -/*#define CONFIG_VIDEO_ENCODER_AD7177 1 / Enable this encoder */ -/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 / ALSB to ground */ - -/* Wireless 56Khz 4PPM keyboard on SMCx */ - -/*#define CONFIG_KEYBOARD 0 */ -/*#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 / SMC to use (0 indexed) */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#include - -#define CONFIG_GENIETV 1 -#define CONFIG_MPC823 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 5000000 /* 4 MHz clock */ - -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) -#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20) -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY 1 /* autoboot after 2 seconds */ -#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTCOMMAND \ -"bootp; tftp; " \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ -"bootm " -#else -#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x02800000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/ - -/* values according to the manual */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - * -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - * - * #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0(FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */ - -/* FLASH timing */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX ) - -/*#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) */ -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 0xfff80ff4 */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */ - -/* - * BR1/2 and OR1/2 (SDRAM) -*/ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define SDRAM_MAX_SIZE 0x04000000 /* 64Mb bank */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* First bank */ -#define SDRAM_BASE2_PRELIM 0x10000000 /* Second bank */ - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MBMR_PTB 0x5d /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 -/* - * MBMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \ - | MAMR_TLFA_4X) /* 0x5d802114 */ - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 1 -#define PCMCIA_SLOT_B 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h deleted file mode 100644 index d20ca77870..0000000000 --- a/include/configs/HH405.h +++ /dev/null @@ -1,483 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_HH405 1 /* ...on a HH405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT "autoupd" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "pciconfighost=1\0" \ - "" - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#undef CONFIG_HAS_ETH1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -/* - * Video console - */ -#define CONFIG_VIDEO /* for sm501 video support */ - -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#if 0 -#define CONFIG_VIDEO_SM501_32BPP -#else -#define CONFIG_VIDEO_SM501_16BPP -#endif -#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ - -#endif /* CONFIG_VIDEO */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - -#ifdef CONFIG_VIDEO -#define CONFIG_CMD_BMP -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ - -#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * RTC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF80000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ - -#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CONFIG_SYS_RAMBOOT 1 -#else -# undef CONFIG_SYS_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#if 0 /* test-only */ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#else -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#endif -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#define CONFIG_SYS_EEPROM_WREN 1 - -#if 1 /* test-only */ -/* CAT24WC08/16... */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define LCD_BA 0xF1000000 /* Epson LCD Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ -#define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (Epson LCD) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ -#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * LCD Setup - */ - -#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ -#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ -#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ - -/*----------------------------------------------------------------------- - * Universal Interrupt Controller (UIC) Setup - */ - -/* - * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high - */ -#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6)) - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ - -#define LCD_CLK_OFF 0x0000 /* Off */ -#define LCD_CLK_02083 0x1000 /* 2.083 MHz */ -#define LCD_CLK_03135 0x2000 /* 3.135 MHz */ -#define LCD_CLK_04165 0x3000 /* 4.165 MHz */ -#define LCD_CLK_06250 0x4000 /* 6.250 MHz */ -#define LCD_CLK_08330 0x5000 /* 8.330 MHz */ -#define LCD_CLK_12500 0x6000 /* 12.50 MHz */ -#define LCD_CLK_25000 0x7000 /* 25.00 MHz */ - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555440 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017 - -#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) -#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ -#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ -#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) -#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h deleted file mode 100644 index ddeccb0868..0000000000 --- a/include/configs/HIDDEN_DRAGON.h +++ /dev/null @@ -1,374 +0,0 @@ -/* - * (C) Copyright 2004 - * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com - * - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_HIDDEN_DRAGON 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - -#define CONFIG_RTL8139 - -/* Make sure the ethaddr can be overwritten - TODO: Remove this on final product -*/ -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE 0x00090000 -#define CONFIG_SYS_RAMBOOT 1 -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 -#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_ISA_MEM 0xFD000000 -#define CONFIG_SYS_ISA_IO 0xFE000000 - -#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */ -#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000 -#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#ifdef CONFIG_SYS_I2C_SOFT -#error "Soft I2C is not configured properly. Please review!" -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ -#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* TODO: Change this to VIA686A */ - -/* - * NS87308 Configuration - */ -#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CONFIG_SYS_NS87308_BADDR_10 1 - -#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ - CONFIG_SYS_NS87308_UART2 | \ - CONFIG_SYS_NS87308_POWRMAN | \ - CONFIG_SYS_NS87308_RTC_APC ) - -#undef CONFIG_SYS_NS87308_PS2MOD - -#define CONFIG_SYS_NS87308_CS0_BASE 0x0076 -#define CONFIG_SYS_NS87308_CS0_CONF 0x30 -#define CONFIG_SYS_NS87308_CS1_BASE 0x0075 -#define CONFIG_SYS_NS87308_CS1_CONF 0x30 -#define CONFIG_SYS_NS87308_CS2_BASE 0x0074 -#define CONFIG_SYS_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX > 2) -#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 -#else -#define CONFIG_SYS_NS16550_CLK 1843200 -#endif - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ - -#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#if 0 -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ -#endif - -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h deleted file mode 100644 index cf796bf2d9..0000000000 --- a/include/configs/HUB405.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_HUB405 1 /* ...on a HUB405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#undef CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: UART) initialization */ -#if 0 -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#else -#define CONFIG_SYS_EBC_PB2AP 0x92015480 -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#endif - -#define DUART0_BA 0xF0000000 /* DUART Base Address */ -#define DUART1_BA 0xF0000008 /* DUART Base Address */ -#define DUART2_BA 0xF0000010 /* DUART Base Address */ -#define DUART3_BA 0xF0000018 /* DUART Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 - -#define CONFIG_SYS_DUART_RST (0x80000000 >> 14) -#define CONFIG_SYS_UART2_RS232 (0x80000000 >> 5) -#define CONFIG_SYS_UART3_RS232 (0x80000000 >> 6) -#define CONFIG_SYS_UART4_RS232 (0x80000000 >> 7) -#define CONFIG_SYS_UART5_RS232 (0x80000000 >> 8) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h deleted file mode 100644 index 5aaa9767e9..0000000000 --- a/include/configs/HWW1U1A.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * HardwareWall HWW-1U-1A airborne unit configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High-level system configuration options */ -#define CONFIG_BOOKE /* Power/PowerPC Book-E */ -#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 family */ -#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */ -#define CONFIG_FSL_LAW /* FreeScale Local Access Window */ -#define CONFIG_P2020 /* FreeScale P2020 */ -#define CONFIG_HWW1U1A /* eXMeritus HardwareWall HWW-1U-1A */ -#define CONFIG_MP /* Multiprocessing support */ -#define CONFIG_HWCONFIG /* Use hwconfig from environment */ - -#define CONFIG_L2_CACHE /* L2 cache enabled */ -#define CONFIG_BTB /* Branch predition enabled */ - -#define CONFIG_PANIC_HANG /* No board reset on panic */ -#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r() */ -#define CONFIG_CMD_REGINFO /* Dump various CPU regs */ - -/* - * Allow the use of 36-bit physical addresses. Device-trees with 64-bit - * addresses have known compatibility issues with some existing kernels. - */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */ - -/* Reserve plenty of RAM for malloc (we have 2GB+) */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* How much L2 cache do we map so we can use it as RAM */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -/* This is our temporary global data area just above the stack */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* The stack grows down from the global data area */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Enable IRQs and watchdog with a 1000Hz system decrementer */ -#define CONFIG_CMD_IRQ -#define CONFIG_SYS_HZ 1000 - - -/* -------------------------------------------------------------------- */ - -/* - * Clock crystal configuration: - * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR) - * (2) CCB: Multiplier from SYS_CLK - * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock) - */ -#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/ -#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/ - - -/* -------------------------------------------------------------------- */ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM - * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1 - * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused) - * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3 - * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH - * 0xe800_0000 0xefff_ffff 128M Spansion FLASH - * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0) - * 0xffe0_0000 0xffef_ffff 1M CCSR - * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller - */ - -/* Virtual Memory Map */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */ - -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* Physical Memory Map */ -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf /* for ASM code */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000 /* for ASM code */ -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf /* for ASM code */ -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000 /* for ASM code */ - - -/* -------------------------------------------------------------------- */ - -/* U-Boot image (MONITOR_BASE == TEXT_BASE) */ -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc /* Top address in flash */ -#define CONFIG_SYS_TEXT_BASE 0xeff80000 /* Start of U-Boot image */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN 0x80000 /* 512kB (4 flash sectors) */ - -/* - * U-Boot Environment Image: The two sectors immediately below U-Boot - * form the U-Boot environment (regular and redundant). - */ -#define CONFIG_ENV_IS_IN_FLASH /* The environment image is stored in FLASH */ -#define CONFIG_ENV_OVERWRITE /* Allow "protected" variables to be erased */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (1 flash sector) */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) - -/* Only use 8kB of each environment sector for data */ -#define CONFIG_ENV_SIZE 0x2000 /* 8kB */ -#define CONFIG_ENV_SIZE_REDUND 0x2000 /* 8kB */ - - -/* -------------------------------------------------------------------- */ - -/* Serial Console Configuration */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Echo back characters received during a serial download */ -#define CONFIG_LOADS_ECHO - -/* Allow a serial-download to temporarily change baud */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - - -/* -------------------------------------------------------------------- */ - -/* PCI and PCI-Express Support */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCI_PNP /* Scan PCI busses */ -#define CONFIG_CMD_PCI /* Enable the "pci" command */ -#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */ -#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */ -#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */ - -/* Enable 2 of the 3 PCI-E controllers */ -#define CONFIG_PCIE3 -#undef CONFIG_PCIE2 -#define CONFIG_PCIE1 - -/* Display human-readable names when initializing */ -#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB" -#define CONFIG_SYS_PCIE2_NAME "Unused" -#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531" - -/* - * PCI bus addresses - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 - - -/* -------------------------------------------------------------------- */ - -/* Generic FreeScale hardware I2C support */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#define CONFIG_CMD_I2C - -/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */ -#define CONFIG_CMD_DATE -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 0 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* Turn off RTC square-wave output to save battery */ -#define CONFIG_SYS_RTC_DS1337_NOOSC - -/* - * AT24C128N EEPROM at I2C0-0x53. - * - * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages - * of 64 bytes per page. The chip uses 2-byte addresses and has a max write - * cycle time of 20ms according to the datasheet. - * - * NOTE: Our environment is stored on regular direct-attached FLASH, this - * chip is only used as a write-protected backup for certain key settings - * such as the serial# and macaddr values. (EG: "env import") - */ -#define CONFIG_CMD_EEPROM -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21 - -/* - * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554). You - * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command - * will not be able to access the chip. - */ -#define CONFIG_PCA953X -#define CONFIG_CMD_PCA953X -#define CONFIG_CMD_PCA953X_INFO -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f - - -/* -------------------------------------------------------------------- */ - -/* FreeScale DDR2/3 SDRAM Controller */ -#define CONFIG_FSL_DDR2 /* Our SDRAM slot is DDR2 */ -#define CONFIG_DDR_ECC /* Enable ECC by default */ -#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */ -#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */ -#define CONFIG_VERY_BIG_RAM /* Allow 2GB+ of RAM */ -#define CONFIG_CMD_SDRAM - -/* Standard P2020 DDR controller parameters */ -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* Make sure to tell the DDR controller to preinitialze all of RAM */ -#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER - - -/* -------------------------------------------------------------------- */ - -/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -/* Flash banks (2x 128MB) */ -#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull) -#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS } - -/* - * Flash access modes and timings (values are the defaults after a RESET). - * - * NOTE: These could probably be optimized but are more than sufficient for - * this particular system for the moment. - */ -#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V) -#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -/* Configure both flash banks */ -#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS)) -#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS)) -#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB) -#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB) - -/* Flash timeouts (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */ - -/* Quiet flash testing */ -#define CONFIG_SYS_FLASH_QUIET_TEST - -/* Make program/erase count down from 45/5 (9....8....7....) */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - - -/* -------------------------------------------------------------------- */ - -/* Ethernet Device Support */ -#define CONFIG_MII /* Enable MII PHY code */ -#define CONFIG_MII_DEFAULT_TSEC /* ??? Copied from P2020DS */ -#define CONFIG_PHY_GIGE /* Support Gigabit PHYs */ -#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */ - -/* Turn on various helpful networking commands */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING - -/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */ -#define CONFIG_TSEC_ENET -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 -#define CONFIG_TSEC3 -#define CONFIG_TSEC1_NAME "owt0" -#define CONFIG_TSEC2_NAME "owt1" -#define CONFIG_TSEC3_NAME "peer" -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 -#define TSEC3_PHY_ADDR 4 -#define TSEC3_PHY_ADDR_CPUA 4 -#define TSEC3_PHY_ADDR_CPUB 5 - -/* PCI-E dual-port E1000 (external ethernet ports) */ -#define CONFIG_E1000 -#define CONFIG_E1000_SPI -#define CONFIG_E1000_SPI_GENERIC -#define CONFIG_CMD_E1000 - -/* We need the SPI infrastructure to poke the E1000's EEPROM */ -#define CONFIG_SPI -#define CONFIG_SPI_X -#define CONFIG_CMD_SPI -#define MAX_SPI_BYTES 32 - - -/* -------------------------------------------------------------------- */ - -/* USB Thumbdrive Device Support */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_USB - -/* Partition and Filesystem support */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - - -/* -------------------------------------------------------------------- */ - -/* Command line configuration. */ -#define CONFIG_CMDLINE_EDITING /* Enable command editing */ -#define CONFIG_COMMAND_HISTORY /* Enable command history */ -#define CONFIG_AUTO_COMPLETE /* Enable command completion */ -#define CONFIG_SYS_LONGHELP /* Enable detailed command help */ -#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */ -#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */ -#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */ -#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */ -#define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */ - -/* A little extra magic here for the prompt */ -#define CONFIG_SYS_PROMPT hww1u1a_get_ps1() -#ifndef __ASSEMBLY__ -const char *hww1u1a_get_ps1(void); -#endif - -/* Include a bunch of default commands we probably want */ -#include - -/* Other helpful shell-like commands */ -#define CONFIG_MD5 -#define CONFIG_SHA1 -#define CONFIG_CMD_MD5SUM -#define CONFIG_CMD_SHA1SUM -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SETEXPR - - -/* -------------------------------------------------------------------- */ - -/* Image manipulation and booting */ - -/* We use the OpenFirmware-esque "Flattened Device Tree" */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMD_ELF -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB */ - -/* This is the default address for commands with an optional address arg */ -#define CONFIG_LOADADDR 100000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 - -/* Test memory starting from the default load address to just below 2GB */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_END 0x7f000000 - -#define CONFIG_BOOTDELAY 20 -#define CONFIG_BOOTCOMMAND "echo Not yet flashed" -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1" - -/* Extra environment parameters */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethprime=e1000#0\0" \ - "ethrotate=no\0" \ - "setbootargs=setenv bootargs " \ - "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \ - "perf_mode=performance\0" \ - "hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=ulpi\0" \ - "flkernel=0xe8000000\0" \ - "flinitramfs=0xe8800000\0" \ - "fldevicetree=0xeff20000\0" \ - "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \ - "flboot=run preboot; run flbootm\0" \ - "restore_eeprom=i2c dev 0 && " \ - "eeprom read $loadaddr 0x0000 0x2000 && " \ - "env import -c $loadaddr 0x2000\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h deleted file mode 100644 index 40d0d7cab9..0000000000 --- a/include/configs/ICU862.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_ICU862 1 -#define CONFIG_MPC862 1 - -#define CONFIG_SYS_TEXT_BASE 0x40F00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#ifdef CONFIG_100MHz -#define MPC8XX_FACT 24 /* Multiply by 24 */ -#define MPC8XX_XIN 4165000 /* 4.165 MHz in */ -#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) - /* define if cant' use get_gclk_freq */ -#else -#if 1 /* for 50MHz version of processor */ -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */ -#else /* for 80MHz version of processor */ -#define MPC8XX_FACT 20 /* Multiply by 20 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */ -#endif -#endif - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 -#if 1 -#define CONFIG_SYS_DISCOVER_PHY 1 -#else -#undef CONFIG_SYS_DISCOVER_PHY -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if 0 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00F40000 - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */ -#define SCCR_MASK 0 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01) -#else /* up to 50 MHz we use a 1:1 clock */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 ) -#endif /* CONFIG_100MHz */ - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ -#define CONFIG_SYS_RCCR 0x0020 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * PCMCIA Power Switch - * - * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to - * control the voltages on the PCMCIA slot which is connected to Port B - *----------------------------------------------------------------------- - */ - /* Output pins */ -#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */ -#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */ -#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */ -#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */ -#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */ -#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \ - TPS2205_VPP_PGM | TPS2205_VPP_VCC | \ - TPS2205_SHDN) - - /* Input pins */ -#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */ -#define TPS2205_INPUTS ( TPS2205_OC ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */ -#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */ - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */ - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13a01114 - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h deleted file mode 100644 index 590abc30df..0000000000 --- a/include/configs/IDS8247.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_IDS8247 1 -#define CPU_ID_STR "MPC8247" -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=ttyS0,115200\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/IDS8247/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ffa00000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000080) -#define I2C_TRISTATE (iop->pdir &= ~0x00000080) -#define I2C_READ ((iop->pdat & 0x00000080) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ - else iop->pdat &= ~0x00000080 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ - else iop->pdat &= ~0x00000100 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#if 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X -#endif - -/* - * select serial console configuration - * use the extern UART for the console - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 14745600 - -#define CONFIG_SYS_UART_BASE 0xE0000000 -#define CONFIG_SYS_UART_SIZE 0x10000 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000) - - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" - - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#define CONFIG_ETHER_ON_FCC1 -#define FCC_ENET - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK9 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH0_SIZE 8 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Environment in flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND0_BASE 0xE1000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -#endif /* CONFIG_CMD_NAND */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ - -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) -#define CONFIG_SYS_HID0_FINAL 0 -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR 0 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 16 bit FLASH - * 1 60x GPCM 8 bit NAND - * 2 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit UART - * - */ - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ - -#define CONFIG_SYS_MPTPR 0x6600 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_SCY_6_CLK ) - -#if defined(CONFIG_CMD_NAND) -/* Bank 1 - NAND Flash -*/ -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE -#define CONFIG_SYS_NAND_SIZE 0x8000 - -#define CONFIG_SYS_OR_TIMING_NAND 0x000036 - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND ) -#endif - -/* Bank 2 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 - -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2 - - -/* SDRAM initialization values -*/ -#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_2C |\ - PSDMR_WRC_3C |\ - PSDMR_CL_3) - -/* Bank 3 - UART -*/ - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) - -#endif /* __CONFIG_H */ diff --git a/include/configs/IP860.h b/include/configs/IP860.h deleted file mode 100644 index c852ca998b..0000000000 --- a/include/configs/IP860.h +++ /dev/null @@ -1,441 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_IP860 1 /* ...on a IP860 board */ - -#define CONFIG_SYS_TEXT_BASE 0x10000000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \ -"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF1000000 /* Non-standard value!! */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -#if 0 /* need more space for I2C tests */ -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#endif -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#undef CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_IN_NVRAM -#undef CONFIG_ENV_IS_IN_NVRAM -#undef DEBUG_I2C -#define CONFIG_ENV_IS_IN_EEPROM - -#ifdef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_ADDR 0x20000000 /* use SRAM */ -#define CONFIG_ENV_SIZE (16<<10) /* use 16 kB */ -#endif /* CONFIG_ENV_IS_IN_NVRAM */ - -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */ -#define CONFIG_ENV_SIZE 1536 /* Use remaining space */ -#endif /* CONFIG_ENV_IS_IN_EEPROM */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif -#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before - * running in RAM. - */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - * +0x0004 - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * +0x0000 => 0x80600800 - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \ - SIUMCR_DBGC11 | SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * Clock Setting - get clock frequency from Board Revision Register - *----------------------------------------------------------------------- - */ -#ifndef __ASSEMBLY__ -extern unsigned long ip860_get_clk_freq (void); -#endif -#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq() - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - * +0x0200 => 0x00C2 - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - * +0x0240 => 0x0082 - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* +0x0286 => was: 0x0000D000 */ -#define CONFIG_SYS_PLPRCR \ - ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* +0x0220 => 0x00C3 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => TIMEP=1 */ -#define CONFIG_SYS_RCCR 0x0100 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * DER - Debug Event Register - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - */ - -/* - * MAMR settings for SDRAM - 16-14 - * => 0xC3804114 - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 0xC3 - -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* - * BR1 and OR1 (FLASH) - */ -#define FLASH_BASE 0x10000000 /* FLASH bank #0 */ - -/* used to re-map FLASH - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* allow for max 8 MB of Flash */ -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR0_PRELIM - -/* - * BR2/OR2 - SDRAM - */ -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CONFIG_SYS_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR3/OR3 - SRAM (16 bit) - */ -#define SRAM_BASE 0x20000000 -#define CONFIG_SYS_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */ -#define CONFIG_SYS_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK))) -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */ -#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */ -#define CONFIG_SYS_SRAM_BASE SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE SRAM_SIZE - -/* - * BR4/OR4 - Board Control & Status (8 bit) - */ -#define BCSR_BASE 0xFC000000 -#define CONFIG_SYS_OR4 0xFFFF0120 /* BI (internal) */ -#define CONFIG_SYS_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) - -/* - * BR5/OR5 - IP Slot A/B (16 bit) - */ -#define IP_SLOT_BASE 0x40000000 -#define CONFIG_SYS_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */ -#define CONFIG_SYS_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) - -/* - * BR6/OR6 - VME STD (16 bit) - */ -#define VME_STD_BASE 0xFE000000 -#define CONFIG_SYS_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */ -#define CONFIG_SYS_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) - -/* - * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit) - */ -#define VME_SHORT_BASE 0xFF000000 -#define CONFIG_SYS_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */ -#define CONFIG_SYS_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) - -/*----------------------------------------------------------------------- - * Board Control and Status Region: - *----------------------------------------------------------------------- - */ -#ifndef __ASSEMBLY__ -typedef struct ip860_bcsr_s { - unsigned char shmem_addr; /* +00 shared memory address register */ - unsigned char reserved0; - unsigned char mbox_addr; /* +02 mailbox address register */ - unsigned char reserved1; - unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */ - unsigned char reserved2; - unsigned char vme_int_pend; /* +06 VME interrupt pending register */ - unsigned char reserved3; - unsigned char bd_int_mask; /* +08 board interrupt mask register */ - unsigned char reserved4; - unsigned char bd_int_pend; /* +0A board interrupt pending register */ - unsigned char reserved5; - unsigned char bd_ctrl; /* +0C board control register */ - unsigned char reserved6; - unsigned char bd_status; /* +0E board status register */ - unsigned char reserved7; - unsigned char vme_irq; /* +10 VME interrupt request register */ - unsigned char reserved8; - unsigned char vme_ivec; /* +12 VME interrupt vector register */ - unsigned char reserved9; - unsigned char cli_mbox; /* +14 clear mailbox irq */ - unsigned char reservedA; - unsigned char rtc; /* +16 RTC control register */ - unsigned char reservedB; - unsigned char mbox_data; /* +18 mailbox read/write register */ - unsigned char reservedC; - unsigned char wd_trigger; /* +1A Watchdog trigger register */ - unsigned char reservedD; - unsigned char rmw_req; /* +1C RMW request register */ - unsigned char reservedE; - unsigned char bd_rev; /* +1E Board Revision register */ -} ip860_bcsr_t; -#endif /* __ASSEMBLY__ */ - -/*----------------------------------------------------------------------- - * Board Control Register: bd_ctrl (Offset 0x0C) - *----------------------------------------------------------------------- - */ -#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */ -#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */ -#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */ -#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h deleted file mode 100644 index cbc8b5bbc1..0000000000 --- a/include/configs/IPHASE4539.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * This file is based on similar values for other boards found in - * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */ - -#define CONFIG_SYS_TEXT_BASE 0xffb00000 - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/*----------------------------------------------------------------------- - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -/*----------------------------------------------------------------------- - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 3 /* which channel for ether */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) - -/*----------------------------------------------------------------------- - * - Rx-CLK is CLK14 - * - Tx-CLK is CLK16 - * - Select bus for bd/buffers (see 28-13) - * - Half duplex - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* other options */ - -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#define CONFIG_BAUDRATE 19200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -/* - * Command line configuration. - */ -#include - - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ - /* for versions < 2.4.5-pre5 */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0x04400000 - -#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */ - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration (Setup by the - * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF800000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_SIZE (CONFIG_SYS_MAX_FLASH_SECT * 0x10000) /* 4 MB */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Environment in FLASH, there is little space left in Serial EEPROM */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */ - - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\ - ( HRCW_L2CPC10 | HRCW_ISB110 ) |\ - ( HRCW_MMR11 | HRCW_APPC10 ) |\ - ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ - ) /* 0x14863245 */ - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 /* We keep original value */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR 0xA01C0000 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR 0X4205C000 - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined (CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/*----------------------------------------------------------------------- - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - */ - -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801) -#define CONFIG_SYS_OR0_PRELIM 0xFF800882 -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041) -#define CONFIG_SYS_OR1_PRELIM 0xF8002CD0 - -#define CONFIG_SYS_PSDMR 0x404A241A -#define CONFIG_SYS_MPTPR 0x00007400 -#define CONFIG_SYS_PSRT 0x00000007 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h deleted file mode 100644 index b0287e2117..0000000000 --- a/include/configs/ISPAN.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Interphase iSPAN Communications Controllers - * (453x and others). Tested on 4532. - * - * Derived from iSPAN 4539 port (iphase4539) by - * Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8260 /* This is an MPC8260 CPU */ -#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xFE7A0000 - -/*----------------------------------------------------------------------- - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * If CONFIG_CONS_NONE is defined, then the serial console routines must be - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* Define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */ -#undef CONFIG_CONS_NONE /* Define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */ - -/*----------------------------------------------------------------------- - * Select Ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC). - * - * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must - * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */ -#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */ - -#ifdef CONFIG_ETHER_ON_FCC - -#if CONFIG_ETHER_INDEX == 3 - -#define CONFIG_SYS_PHY_ADDR 0 -#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) -#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) - -#endif /* CONFIG_ETHER_INDEX == 3 */ - -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 3 /* Port D */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - - -#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */ -#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */ - -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#define CONFIG_8260_CLKIN 65536000 /* in Hz */ -#define CONFIG_BAUDRATE 38400 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO - - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* #undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */ - -#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0x09900000 - -#define CONFIG_MISC_INIT_R /* We need misc_init_r() */ - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */ - -/* Environment is in flash, there is little space left in Serial EEPROM */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * If you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -/* 0x1686B245 */ -#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_ISB110 |\ - HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\ - HRCW_CS10PC01 | HRCW_MODCK_H0101 \ - ) -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0F00000 -#ifdef CONFIG_SYS_REV_B -#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000 -#endif /* CONFIG_SYS_REV_B */ -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR 0xA01C0000 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined (CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/*----------------------------------------------------------------------- - * Init Memory Controller: - * - * Bank Bus Machine PortSize Device - * ---- --- ------- ----------------------------- ------ - * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - */ -#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory - controller, rely on initialisation - performed by the Interphase boot firmware. - */ - -#define CONFIG_SYS_OR0_PRELIM 0xFE000882 -#ifdef CONFIG_SYS_REV_B -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V) -#else /* Rev. D */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V) -#endif /* CONFIG_SYS_REV_B */ - -#define CONFIG_SYS_MPTPR 0x7F00 - -/* Please note that 60x SDRAM MUST start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_60x_BR 0x00000041 -#define CONFIG_SYS_60x_OR 0xF0002CD0 -#define CONFIG_SYS_PSDMR 0x0049929A -#define CONFIG_SYS_PSRT 0x07 - -#define CONFIG_SYS_LSDRAM_BASE 0xF7000000 -#define CONFIG_SYS_LOC_BR 0x00001861 -#define CONFIG_SYS_LOC_OR 0xFF803280 -#define CONFIG_SYS_LSDMR 0x8285A552 -#define CONFIG_SYS_LSRT 0x07 - -#endif /* __CONFIG_H */ diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h deleted file mode 100644 index 53b51f3d5d..0000000000 --- a/include/configs/IVML24.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_IVML24 1 /* ...on a IVML24 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -#if defined (CONFIG_IVML24_16M) -# define CONFIG_IDENT_STRING " IVML24" -#elif defined (CONFIG_IVML24_32M) -# define CONFIG_IDENT_STRING " IVML24_128" -#elif defined (CONFIG_IVML24_64M) -# define CONFIG_IDENT_STRING " IVML24_256" -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ 50331648 - -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */ -#define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */ -#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ -#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */ - -#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ -#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR - -#if defined (CONFIG_IVML24_16M) -# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#elif defined (CONFIG_IVML24_32M) -# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#elif defined (CONFIG_IVML24_64M) -# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) - -# if defined (CONFIG_IVML24_16M) -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -# elif defined (CONFIG_IVML24_32M) -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -# elif defined (CONFIG_IVML24_64M) -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -# endif - -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* EARB, DBGC and DBPC are initialised by the HCW */ -/* => 0x000000C0 */ -#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00B0C0C0 */ -#define CONFIG_SYS_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800014 */ -#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD101 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* 0x00C3 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* TIMEP=2 */ -#define CONFIG_SYS_RCCR 0x0200 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */ - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* EPROMs are 512kb */ -#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \ - CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \ - CONFIG_SYS_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 - */ -#define ELIC_SACCO_BASE 0xFE000000 -#define ELIC_SACCO_OR_AM 0xFFFF8000 -#define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) - -#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - ELIC_SACCO_TIMING) -#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 - */ -#define ELIC_EPIC_BASE 0xFE008000 -#define ELIC_EPIC_OR_AM 0xFFFF8000 -#define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) - -#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - ELIC_EPIC_TIMING) -#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3/OR3: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) - -/* - * BR4/OR4 - HDLC Address - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0 - */ -#define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */ -#define HDLC_ADDR_OR_AM 0xFFFF8000 -#define HDLC_ADDR_TIMING OR_SCY_1_CLK - -#define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING) -#define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V ) - -/* - * BR5/OR5: SHARC ADSP-2165L - * - * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 - */ -#define SHARC_BASE 0xFE400000 -#define SHARC_OR_AM 0xFFC00000 -#define SHARC_TIMING OR_SCY_0_CLK - -#define CONFIG_SYS_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING ) -#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MBMR_PTB 204 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ - -#if defined (CONFIG_IVML24_16M) -# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ -#elif defined (CONFIG_IVML24_32M) -# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ -#elif defined (CONFIG_IVML24_64M) -# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ -#endif - - -/* - * MBMR settings for SDRAM - */ - -#if defined (CONFIG_IVML24_16M) - /* 8 column SDRAM */ -# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#elif defined (CONFIG_IVML24_32M) -/* 128 MBit SDRAM */ -# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#elif defined (CONFIG_IVML24_64M) -/* 128 MBit SDRAM */ -# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h deleted file mode 100644 index 70e201a352..0000000000 --- a/include/configs/IVMS8.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -#if defined (CONFIG_IVMS8_16M) -# define CONFIG_IDENT_STRING " IVMS8" -#elif defined (CONFIG_IVMS8_32M) -# define CONFIG_IDENT_STRING " IVMS8_128" -#elif defined (CONFIG_IVMS8_64M) -# define CONFIG_IDENT_STRING " IVMS8_256" -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ 50331648 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ -#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */ - -#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ -#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#if defined (CONFIG_IVMS8_16M) -# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#elif defined (CONFIG_IVMS8_32M) -# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#elif defined (CONFIG_IVMS8_64M) -# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -# if defined (CONFIG_IVMS8_16M) -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -# elif defined (CONFIG_IVMS8_32M) -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -# elif defined (CONFIG_IVMS8_64M) -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -# endif -#else -# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* EARB, DBGC and DBPC are initialised by the HCW */ -/* => 0x000000C0 */ -#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00B0C0C0 */ -#define CONFIG_SYS_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800014 */ -#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD101 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* 0x00C3 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* TIMEP=2 */ -#define CONFIG_SYS_RCCR 0x0200 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */ - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* EPROMs are 512kb */ -#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 - */ -#define ELIC_SACCO_BASE 0xFE000000 -#define ELIC_SACCO_OR_AM 0xFFFF8000 -#define ELIC_SACCO_TIMING 0x00000F26 - -#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING) -#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 - */ -#define ELIC_EPIC_BASE 0xFE008000 -#define ELIC_EPIC_OR_AM 0xFFFF8000 -#define ELIC_EPIC_TIMING 0x00000F26 - -#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING) -#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3/OR3: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) - -/* - * BR4/OR4: not used - */ - -/* - * BR5/OR5: SHARC ADSP-2165L - * - * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 - */ -#define SHARC_BASE 0xFE400000 -#define SHARC_OR_AM 0xFFC00000 -#define SHARC_TIMING 0x00000700 - -#define CONFIG_SYS_OR5 (SHARC_OR_AM | SHARC_TIMING ) -#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MBMR_PTB 204 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#if defined (CONFIG_IVMS8_16M) - #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ -#elif defined (CONFIG_IVMS8_32M) -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ -#elif defined (CONFIG_IVMS8_64M) -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ -#endif - - -/* - * MBMR settings for SDRAM - */ - -#if defined (CONFIG_IVMS8_16M) - /* 8 column SDRAM */ -# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#elif defined (CONFIG_IVMS8_32M) -/* 128 MBit SDRAM */ -#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#elif defined (CONFIG_IVMS8_64M) -/* 128 MBit SDRAM */ -#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h deleted file mode 100644 index df29c7d3f4..0000000000 --- a/include/configs/IceCube.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFF000000 boot low for 16 MiB boards - * 0xFF800000 boot low for 8 MiB boards - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI - -#if defined(CONFIG_PCI) -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_SYS_XLB_PIPELINING 1 - -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#define CONFIG_SYS_OHCI_BE_CONTROLLER -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#endif -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -#if defined(CONFIG_LITE5200B) -# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B -#else -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT08 1 -#endif -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#if defined(CONFIG_LITE5200B) -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#else -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * Flash configuration - */ -#if defined(CONFIG_LITE5200B) -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#if defined(CONFIG_SYS_LOWBOOT08) -# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B -#endif -#if defined(CONFIG_SYS_LOWBOOT16) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000) -#endif -#endif /* CONFIG_SYS_LOWBOOT */ -#else /* !CONFIG_LITE5200B (IceCube)*/ -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#if defined(CONFIG_SYS_LOWBOOT08) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000) -#endif -#if defined(CONFIG_SYS_LOWBOOT16) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#endif -#endif /* CONFIG_SYS_LOWBOOT */ -#endif /* CONFIG_LITE5200B */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ - -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ - -#if defined(CONFIG_LITE5200B) -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START} -#endif - - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#if defined(CONFIG_LITE5200B) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#else -#define CONFIG_ENV_SECT_SIZE 0x10000 -#endif -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#ifdef CONFIG_MPC5200_DDR -#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004 -#else -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#if defined(CONFIG_LITE5200B) -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_CFG 0x00047800 -#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#else /* IceCube aka Lite5200 */ -#ifdef CONFIG_MPC5200_DDR - -#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE) -#define CONFIG_SYS_BOOTCS_SIZE 0x00800000 -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS1_SIZE 0x00800000 -#define CONFIG_SYS_CS1_CFG 0x00047800 - -#else /* !CONFIG_MPC5200_DDR */ - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#endif /* CONFIG_MPC5200_DDR */ -#endif /*CONFIG_LITE5200B */ - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 6439d99bf8..5cc25576ae 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -2,7 +2,7 @@ * (C) Copyright 2003 Picture Elements, Inc. * Stephen Williams * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -20,8 +20,6 @@ #define CONFIG_JSE 1 /* JSE has a PPC405GPr */ #define CONFIG_405GP 1 - /* ... which is a 4xxx series */ -#define CONFIG_4x 1 /* ... with a 33MHz OSC. connected to the SysCLK input */ #define CONFIG_SYS_CLK_FREQ 33333333 /* ... with on-chip memory here (4KBytes) */ @@ -156,7 +154,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ @@ -192,8 +189,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_PPC4XX #define CONFIG_SYS_I2C_PPC4XX_CH0 @@ -277,6 +272,5 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif #endif /* __CONFIG_H */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h deleted file mode 100644 index 2cbb6eeb9c..0000000000 --- a/include/configs/KAREF.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference - * design. - ***********************************************************************/ - -/* - * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $ - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000) -#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000) -#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000) -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) - -/* Here for completeness */ -#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_PPC4XX_CH1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */ -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_PING -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT - - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */ - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */ - -#define CONFIG_SYS_HZ 100 /* decr freq: 1 ms ticks */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h deleted file mode 100644 index ef51e35df6..0000000000 --- a/include/configs/KUP4K.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - * Derived from ../tqm8xx/tqm8xx.c - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_KUP4K 1 /* ...on a KUP4K module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \ - "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \ -"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \ - "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \ -"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \ -"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \ - bootm 400000 \0" \ -"panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \ -"ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \ - ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \ - hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \ -"console=ttyCPM0,115200\0" \ -"netdev=eth0\0" \ -"contrast=20\0" \ -"silent=1\0" \ -"mtdparts=" MTDPARTS_DEFAULT "\0" \ -"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ -"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \ - "cp.b 200000 40050000 14000\0" - -#define CONFIG_BOOTCOMMAND \ - "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot" - -#define CONFIG_PREBOOT "setenv preboot; saveenv" - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MISC_INIT_F 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * enable I2C and select the hardware/software driver - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE - -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -/*----------------------------------------------------------------------- - * I2C Configuration - */ - -#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ - -/* List of I2C addresses to be verified by POST */ - -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \ - CONFIG_SYS_I2C_RTC_ADDR, \ - } - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_FAT -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_POST - #define CONFIG_CMD_DIAG -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST 1 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \ - "64k(env)," \ - "128k(splash)," \ - "512k(etc)," \ - "64k(hw-info)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#define CONFIG_SYS_PLPRCR ( (5-1)< ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#if defined(CONFIG_80MHz) -#define CONFIG_SYS_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CONFIG_SYS_MAMR_PTA 129 -#else /* 50 MHz */ -#define CONFIG_SYS_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR 0x400 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL 0x68802114 -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL 0x68904114 - -/* - * Chip Selects - */ -#define CONFIG_SYS_OR0 -#define CONFIG_SYS_BR0 - -#define CONFIG_SYS_OR1_8COL 0xFF000A00 -#define CONFIG_SYS_BR1_8COL 0x00000081 -#define CONFIG_SYS_OR2_8COL 0xFE000A00 -#define CONFIG_SYS_BR2_8COL 0x01000081 -#define CONFIG_SYS_OR3_8COL 0xFC000A00 -#define CONFIG_SYS_BR3_8COL 0x02000081 - -#define CONFIG_SYS_OR1_9COL 0xFE000A00 -#define CONFIG_SYS_BR1_9COL 0x00000081 -#define CONFIG_SYS_OR2_9COL 0xFE000A00 -#define CONFIG_SYS_BR2_9COL 0x02000081 -#define CONFIG_SYS_OR3_9COL 0xFE000A00 -#define CONFIG_SYS_BR3_9COL 0x04000081 - -#define CONFIG_SYS_OR4 0xFFFF8926 -#define CONFIG_SYS_BR4 0x90000401 - -#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */ -#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */ - -#define LATCH_ADDR 0x90000200 - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR "." -#define CONFIG_SILENT_CONSOLE 1 -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ -#define CONFIG_VERSION_VARIABLE 1 - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h deleted file mode 100644 index 6da07e7d06..0000000000 --- a/include/configs/KUP4X.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - * Derived from ../tqm8xx/tqm8xx.c - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ -#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ - -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */ -#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */ - - -#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT)) - -/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ -/* in general, we always know this for FADS+new ADS anyway */ -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - - -#undef CONFIG_BOOTARGS - - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw;diskboot 200000 0:1;bootm 200000\0" \ -"usb_boot=setenv bootargs root=/dev/sda2 ip=off; \ - run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1; \ - usb stop; bootm 200000\0" \ -"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \ -"panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ -"ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ - ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ -"netdev=eth0\0" \ -"silent=1\0" \ -"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \ -"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \ - "cp.b 200000 40040000 14000\0" - -#define CONFIG_BOOTCOMMAND \ - "run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot" - - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MISC_INIT_F 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * enable I2C and select the hardware/software driver - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ - -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE - -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - - -/*----------------------------------------------------------------------- - * I2C Configuration - */ - -#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ - - -/* List of I2C addresses to be verified by POST */ - -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \ - CONFIG_SYS_I2C_RTC_ADDR, \ - } - - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII - -#undef CONFIG_KUP4K_LOGO - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_I2C) - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#ifdef CONFIG_POST - #define CONFIG_CMD_DIAG -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/* Address and size of Redundant Environment Sector */ -#if 0 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#if 1 -#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P' */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR ((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS) - - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ - -/* KUP4K use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 - -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define PCMCIA_SOCKETS_NO 1 -#define PCMCIA_MEM_WIN_NO 8 -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 2 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP \ - (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM \ - (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM \ - ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - - -#define CONFIG_SYS_MPTPR 0x400 - -/* - * MAMR settings for SDRAM - */ -#define CONFIG_SYS_MAMR 0x80802114 - - -/* - * Chip Selects - */ - -#define CONFIG_SYS_OR4 0xFFFF8926 -#define CONFIG_SYS_BR4 0x90000401 - -#define LATCH_ADDR 0x90000200 - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ - -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 - -#define CONFIG_USB_STORAGE 1 -#define CONFIG_USB_SL811HS 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index fe901ce6c2..66303773c3 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _M5208EVBE_H @@ -113,7 +113,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ #define CONFIG_SYS_LOAD_ADDR 0x40010000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ #define CONFIG_SYS_PLL_ODR 0x36 #define CONFIG_SYS_PLL_FDR 0x7D diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 1d10f7f2a0..cde7305954 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -176,8 +176,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_MBAR 0xFC000000 /* diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index aaaaa41a15..0f6e2f72cf 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -133,7 +133,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 75000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 2a1a904bb5..ae4fe45fce 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -4,7 +4,7 @@ * (C) Copyright 2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -46,7 +46,6 @@ #define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) @@ -69,8 +68,6 @@ #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 -#define CONFIG_SYS_HZ 1000 - /* * Clock configuration: enable only one of the following options */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 83122cf59f..3a1cbcae93 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -1,7 +1,7 @@ -TABILITY or FITNESS FO04-2007 Freescale Semiconductor, Inc. +/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _M5253DEMO_H @@ -107,7 +107,6 @@ TABILITY or FITNESS FO04-2007 Freescale Semiconductor, Inc. #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) #define CONFIG_SYS_I2C_PINMUX_SET (0) -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) @@ -124,8 +123,6 @@ TABILITY or FITNESS FO04-2007 Freescale Semiconductor, Inc. #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 -#define CONFIG_SYS_HZ 1000 - #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ #define CONFIG_SYS_FAST_CLK #ifdef CONFIG_SYS_FAST_CLK diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index 109b1c0284..fabfdb93db 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -2,7 +2,7 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _M5253EVBE_H @@ -76,7 +76,6 @@ #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) @@ -93,8 +92,6 @@ #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 -#define CONFIG_SYS_HZ 1000 - #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ #define CONFIG_SYS_FAST_CLK #ifdef CONFIG_SYS_FAST_CLK diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h deleted file mode 100644 index a77cb24975..0000000000 --- a/include/configs/M5271EVB.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Configuation settings for the Freescale M5271EVB - * - * Based on MC5272C3 and r5200 board configs - * (C) Copyright 2006 Lab X Technologies - * (C) Copyright 2003 Josef Baumgartner - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5271EVB_H -#define _M5271EVB_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5271 /* define processor type */ -#define CONFIG_M5271EVB /* define board type */ - -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 - -#undef CONFIG_WATCHDOG /* disable watchdog */ - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_OFFSET 0x4000 -#else -#define CONFIG_ENV_ADDR 0xffe04000 -#endif -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_PING -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC - -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */ -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ -#define CONFIG_BOOTFILE "u-boot.bin" -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_RETRY_COUNT 5 -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME M5271EVB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp $loadaddr $uboot\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b $loadaddr ffe00000 $filesize;" \ - "save\0" \ - "" - -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#define CONFIG_SYS_HZ 1000000 - -/* Clock configuration - * The external oscillator is a 25.000 MHz - * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk) - * bus_clk = (cpu_clk/2) (fixed ratio) - * - * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to - * match the new clock speed. Max cpu_clk is 150 MHz. - */ -#define CONFIG_SYS_CLK 100000000 -#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */ - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_SIZE 0x200000 - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/* Chip Select 0 : Boot Flash */ -#define CONFIG_SYS_CS0_BASE 0xFFE00000 -#define CONFIG_SYS_CS0_MASK 0x001F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001980 - -/* Chip Select 1 : External SRAM */ -#define CONFIG_SYS_CS1_BASE 0x30000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001900 - -#endif /* _M5271EVB_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 434c839c73..4c84126559 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -3,7 +3,7 @@ * * (C) Copyright 2003 Josef Baumgartner * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -129,7 +129,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x20000 #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 66000000 /* diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index bacee0a8fa..4dddab7c1d 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -7,7 +7,7 @@ * Based off of M5272C3 board code by Josef Baumgartner * * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -139,7 +139,6 @@ "save\0" \ "" -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 150000000 /* diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index d22018f127..fd970d0787 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -117,7 +117,6 @@ #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 64000000 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 0ced196489..a100d9f316 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -133,7 +133,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ #define CONFIG_SYS_LOAD_ADDR 0x40010000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 86b06f4f16..78ea384375 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -126,7 +126,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR 0x40010000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index cca76097dc..849c26562a 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -126,7 +126,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR 0x40010000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index bc264276d4..3d7dc1fb2d 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -4,7 +4,7 @@ * Copyright 2010-2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -77,7 +77,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_SELECT_DEVICE -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Network configuration */ @@ -253,8 +252,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_MBAR 0xFC000000 /* @@ -270,10 +267,8 @@ /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 256 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_GBL_DATA_SIZE) - 32) + GENERATED_GBL_DATA_SIZE) - 32) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 72ad8366fb..0f4b726f3a 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -187,8 +187,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_MBAR 0xFC000000 /* diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 3dc87d6f61..7a55d3c619 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -177,7 +177,7 @@ #define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 80000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSLI2C_OFFSET 0x58000 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ @@ -246,8 +246,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_MBAR 0xFC000000 /* diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index dc38219c1d..e88a6bd8d3 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -172,7 +172,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 0307f19ad2..e4128062a9 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -158,7 +158,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 diff --git a/include/configs/MBX.h b/include/configs/MBX.h deleted file mode 100644 index b3cd12df90..0000000000 --- a/include/configs/MBX.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the MBX8xx board. - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * Changed 2002-10-01 - * Added PCMCIA defines mostly taken from other U-Boot boards that - * have PCMCIA already working. If you find any bugs, incorrect assumptions - * feel free to fix them yourself and submit a patch. - * Rod Boyce " /* Monitor Command Prompt */ -#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map as defined by the MBX PGM - */ -#define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ -#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ -#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ -#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ -#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ -#define CONFIG_SYS_PCIMEM_OR 0xA0000108 -#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ -#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Offset in DPMEM where we keep the VPD data - */ -#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfe000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * NVRAM Configuration - * - * Note: the MBX is special because there is already a firmware on this - * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we - * access the NVRAM at the offset 0x1000. - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) -#define CONFIG_ENV_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) -#define CONFIG_SYS_SCCR SCCR_TBS - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 - -#define CONFIG_PCMCIA_SLOT_A 1 - - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h deleted file mode 100644 index 8d1ca48233..0000000000 --- a/include/configs/MBX860T.h +++ /dev/null @@ -1,397 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T MBX board. - * Copied from the FADS stuff, which was originally copied from the MBX stuff! - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * Rob Taylor coverted it back to MBX - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MBX 1 - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_8xx_CPUCLOCK 40 -#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK) -#define TARGET_SYSTEM_FREQUENCY 40 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_BAUDRATE 9600 - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 40000000 /* 50 MHz in */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */ -#define CONFIG_8xx_TFTP_MODE -#else -#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */ -#undef CONFIG_8xx_TFTP_MODE -#endif - -#define CONFIG_MISC_INIT_R - -#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */ -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#define CONFIG_BOOTARGS " " -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFA00000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) -#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ -#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ -#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ -#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ -#define CONFIG_SYS_PCIMEM_OR 0xA0000108 -#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ -#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Offset in DPMEM where we keep the VPD data - */ -#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -/*0xFE000000*/ -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_HWINFO_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN) -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * NVRAM Configuration - * - * Note: the MBX is special because there is already a firmware on this - * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we - * access the NVRAM at the offset 0x1000. - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) -#define CONFIG_ENV_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) -#define CONFIG_SYS_SCCR SCCR_TBS - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - - -#define BCSR_ADDR ((uint) 0xFF010000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4 -#define CONFIG_SYS_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13821000 - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#define BCSR4_USB_SPEED ((uint)0x04000000) -#define BCSR4_VCCO ((uint)0x02000000) -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) - -#define CONFIG_DRAM_40MHZ 1 - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#define CONFIG_CMD_NET -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 -#define CONFIG_SCC1_ENET 1 -#define CONFIG_FEC_ENET 1 -#undef CONFIG_CPM_IIC -#undef CONFIG_UCODE_PATCH - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 2 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h deleted file mode 100644 index ad9c77e1c8..0000000000 --- a/include/configs/MERGERBOX.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 -#define CONFIG_MPC837x 1 -#define CONFIG_MPC8377 1 - -#define CONFIG_SYS_TEXT_BASE 0xFC000000 - -#define CONFIG_PCI 1 -#define CONFIG_PCI_INDIRECT_BRIDGE 1 - -#define CONFIG_MASK_AER_AO -#define CONFIG_DISPLAY_AER_FULL - -#define CONFIG_MISC_INIT_R - -/* - * On-board devices - */ -#define CONFIG_TSEC_ENET - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#define CONFIG_PCIE -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - -/* - * Hardware Reset Configuration Word stored in EEPROM. - */ -#define CONFIG_SYS_HRCW_LOW 0 -#define CONFIG_SYS_HRCW_HIGH 0 - -/* Arbiter Configuration Register */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 -#define CONFIG_SYS_ACR_RPTCNT 3 - -/* System Priority Control Regsiter */ -#define CONFIG_SYS_SPCR_TSECEP 3 - -/* System Clock Configuration Register */ -#define CONFIG_SYS_SCCR_TSEC1CM 3 -#define CONFIG_SYS_SCCR_TSEC2CM 0 -#define CONFIG_SYS_SCCR_SDHCCM 3 -#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */ -#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 3 -#define CONFIG_SYS_SCCR_PCIEXP2CM 3 -#define CONFIG_SYS_SCCR_PCICM 1 -#define CONFIG_SYS_SCCR_SATACM 0xFF - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x087c0000 -#define CONFIG_SYS_SICRL 0x40000000 - -/* - * Output Buffer Impedance - */ -#define CONFIG_SYS_OBIR 0x30000000 - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\ - DDRCDR_NZ_HIZ | DDRCDR_ODT |\ - DDRCDR_Q_DRN) - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_MODE_WEAK -#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2 -#define CONFIG_SYS_DDR_CPO 0x1f - -/* SPD table located at offset 0x20 in extended adressing ROM - * used for HRCW fetch after power-on reset - */ -#define CONFIG_SPD_EEPROM -#define SPD_EEPROM_ADDRESS 0x50 -#define SPD_EEPROM_OFFSET 0x20 -#define SPD_EEPROM_ADDR_LEN 2 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512*1024) -#define CONFIG_SYS_MALLOC_LEN (512*1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ - CONFIG_SYS_GBL_DATA_SIZE) - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_FSL_ELBC 1 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 64 - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\ - BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\ - OR_GPCM_XACS | OR_GPCM_SCY_15 |\ - OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\ - OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 - -#define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\ - BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\ - OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\ - OR_FCM_TRLX | OR_FCM_EHTR) - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#define CONFIG_CONSOLE ttyS0 -#define CONFIG_BAUDRATE 115200 - -/* SERDES */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20) -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE (1 << 20) - -#ifdef CONFIG_PCIE -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20) -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20) - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20) -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20) -#endif - -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -/* - * TSEC - */ -#define CONFIG_GMII /* MII PHY management */ -#define CONFIG_SYS_VSC8601_SKEWFIX -#define CONFIG_SYS_VSC8601_SKEW_TX 3 -#define CONFIG_SYS_VSC8601_SKEW_RX 3 - -#define CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x10 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 - -#define CONFIG_ETHPRIME "TSEC0" -#define CONFIG_HAS_ETH0 - -/* - * SATA - */ -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_USB -#define CONFIG_CMD_SPI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_SATA - -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 - -#define CONFIG_RBTREE -#define CONFIG_LZO - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS - -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND" -#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)" - -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 - -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR 0x2000000 -#define CONFIG_LOADADDR 0x4000000 -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 256 - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_SYS_MEMTEST_START (60<<20) -#define CONFIG_SYS_MEMTEST_END (70<<20) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ -#define CONFIG_HIGH_BATS 1 - -/* DDR: cache cacheable */ -#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* unused */ -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* unused */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * I2C EEPROM settings - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x4000 - -/* - * Environment Configuration - */ -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFD00000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - -/* - * Video - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501_PCI -#define VIDEO_FB_LITTLE_ENDIAN -#define CONFIG_CMD_BMP -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) - -/* - * SPI - */ -#define CONFIG_MPC8XXX_SPI - -/* - * USB - */ -#define CONFIG_SYS_USB_HOST -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_USB_STORAGE -#define CONFIG_USB_KEYBOARD -/* - * - */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define MV_CI "MergerBox" -#define MV_VCI "MergerBox" -#define MV_FPGA_DATA 0xfc100000 -#define MV_FPGA_SIZE 0x00200000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x02800000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 -#define MV_FITADDR 0xfc300000 -#define MV_SPLAH_ADDR 0xffe00000 - -#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\ - "then; run fitboot;else;run ubiboot;fi;" -#define CONFIG_BOOTARGS "console=ttyS0,115200n8" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0"\ - "stdin=serial\0"\ - "stdout=serial\0"\ - "stderr=serial\0"\ - "boot_sqfs=1\0"\ - "usb_dr_mode=host\0"\ - "bootfile=MergerBox.fit\0"\ - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\ - "fpga=0\0"\ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\ - "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\ - "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\ - "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\ - "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\ - "fitaddr=" __stringify(MV_FITADDR) "\0"\ - "mv_version=" U_BOOT_VERSION "\0"\ - "mtdids=" MTDIDS_DEFAULT "\0"\ - "mtdparts=" MTDPARTS_DEFAULT "\0"\ - "dhcp_client_id=" MV_CI "\0"\ - "dhcp_vendor-class-identifier=" MV_VCI "\0"\ - "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\ - "protect off all;erase $uboota +0xC0000;"\ - "cp.b $loadaddr $uboota $filesize\0"\ - "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\ - "cp.b $loadaddr $fpgadata $filesize\0"\ - "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\ - "cp.b $loadaddr $fitaddr $filesize\0"\ - "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\ - "rootfstype=squashfs\0"\ - "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\ - "rootfstype=ubifs\0"\ - "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\ - "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\ - "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\ - "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\ - "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\ - "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\ - "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\ - "imxtract $fitaddr ramdisk $mv_initrd_ram;"\ - "imxtract $fitaddr fdt $mv_dtb_ram\0"\ - "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\ - "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\ - "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\ - "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\ - "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\ - "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\ - "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\ - "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\ - "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\ - "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\ - "" - -/* - * FPGA - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 - -#endif diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h deleted file mode 100644 index 1e50032414..0000000000 --- a/include/configs/METROBOX.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * METROBOX.h - configuration Sandburst MetroBox - ***********************************************************************/ - -/* - * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $ - * - * - * $Log: METROBOX.h,v $ - * Revision 1.21 2005/06/03 15:05:25 tsawyer - * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB - * - * Revision 1.20 2005/04/11 20:51:11 tsawyer - * fix ethernet - * - * Revision 1.19 2005/04/06 15:13:36 tsawyer - * Update appropriate files to coincide with u-boot 1.1.3 - * - * Revision 1.18 2005/03/10 14:16:02 tsawyer - * add def'n for cis8201 short etch option. - * - * Revision 1.17 2005/03/09 19:49:51 tsawyer - * Remove KGDB to allow use of 2nd serial port - * - * Revision 1.16 2004/12/02 19:00:23 tsawyer - * Add misc_init_f to turn on i2c-1 and all four fans before sdram init - * - * Revision 1.15 2004/09/15 18:04:12 tsawyer - * add multiple serial port support - * - * Revision 1.14 2004/09/03 15:27:51 tsawyer - * All metrobox boards are at 66.66 sys clock - * - * Revision 1.13 2004/08/05 20:27:46 tsawyer - * Remove system ace definitions, add net console support - * - * Revision 1.12 2004/07/29 20:00:13 tsawyer - * Add i2c bus 1 - * - * Revision 1.11 2004/07/21 13:44:18 tsawyer - * SystemACE is out, CF direct to local bus is in - * - * Revision 1.10 2004/06/29 19:08:55 tsawyer - * Add CONFIG_MISC_INIT_R - * - * Revision 1.9 2004/06/28 21:30:53 tsawyer - * Fix default BOOTARGS - * - * Revision 1.8 2004/06/17 15:51:08 tsawyer - * auto complete - * - * Revision 1.7 2004/06/17 15:08:49 tsawyer - * Add autocomplete - * - * Revision 1.6 2004/06/15 12:33:57 tsawyer - * debugging checkpoint - * - * Revision 1.5 2004/06/12 19:48:28 tsawyer - * Debugging checkpoint - * - * Revision 1.4 2004/06/02 13:03:06 tsawyer - * Fix eth addrs - * - * Revision 1.3 2004/05/18 19:56:10 tsawyer - * Change default bootcommand to pImage.metrobox - * - * Revision 1.2 2004/05/18 14:13:44 tsawyer - * Add bringup values for bootargs and bootcommand. - * Remove definition of ipaddress and serverip addresses. - * - * Revision 1.1 2004/04/16 15:08:54 tsawyer - * Initial Revision - * - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_METROBOX 1 /* Board is Metrobox */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Metrobox" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000) -#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000) -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_PPC4XX_CH1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */ -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none " -#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000" -#define CONFIG_BOOTDELAY 5 /* disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_PING -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT - - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "MetroBox=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */ - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */ - -#define CONFIG_SYS_HZ 100 /* decr freq: 1 ms ticks */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h deleted file mode 100644 index 75eef20e58..0000000000 --- a/include/configs/MHPC.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - * (C) Copyright 2001 - * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Configuation settings for the miniHiPerCam. - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_MHPC 1 /* on a miniHiPerCam */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */ -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#undef CONFIG_UCODE_PATCH - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE) -#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */ -#define LCD_VIDEO_COLS 640 -#define LCD_VIDEO_ROWS 480 -#define LCD_VIDEO_FG 255 -#define LCD_VIDEO_BG 0 - -#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */ -#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */ -#define CONFIG_VIDEO_LOGO - -#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */ -#define VIDEO_TSTC_FCT serial_tstc -#define VIDEO_GETC_FCT serial_getc - -#define CONFIG_BR0_WORKAROUND 1 - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_REGINFO - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfe000000 - -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=mhpc-0" -#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)" -*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */ -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 12-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define MPC8XX_SPEED 50000000L -#define MPC8XX_XIN 5000000L /* ref clk */ -#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */ -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001) - - -/*----------------------------------------------------------------------- - * MAMR settings for SDRAM - 16-14 - * => 0xC080200F - *----------------------------------------------------------------------- - * periodic timer for refresh - */ -#define CONFIG_SYS_MAMR_PTA 0xC0 -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK) - -/* - * BR0 and OR0 (FLASH) used to re-map FLASH - */ - -/* allow for max 8 MB of Flash */ -#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/ -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/ -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/ - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V ) - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ -#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */ - -/* SDRAM timing: drive GPL5 high on first cycle */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS) - -#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2/OR2 - DIMM - */ -#define CONFIG_SYS_OR2 (OR_ACS_DIV4) -#define CONFIG_SYS_BR2 (BR_MS_UPMA) - -/* - * BR3/OR3 - DIMM - */ -#define CONFIG_SYS_OR3 (OR_ACS_DIV4) -#define CONFIG_SYS_BR3 (BR_MS_UPMA) - -/* - * BR4/OR4 - */ -#define CONFIG_SYS_OR4 0 -#define CONFIG_SYS_BR4 0 - -/* - * BR5/OR5 - */ -#define CONFIG_SYS_OR5 0 -#define CONFIG_SYS_BR5 0 - -/* - * BR6/OR6 - */ -#define CONFIG_SYS_OR6 0 -#define CONFIG_SYS_BR6 0 - -/* - * BR7/OR7 - */ -#define CONFIG_SYS_OR7 0 -#define CONFIG_SYS_BR7 0 - - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index c535dbeaae..147f122967 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -2,7 +2,7 @@ * (C) Copyright 2001, 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -17,11 +17,12 @@ * (easy to change) ***********************************************************/ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_MIP405 1 /* ...on a MIP405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_SYS_GENERIC_BOARD + /*********************************************************** * Note that it may also be a MIP405T board which is a subset of the * MIP405 @@ -150,7 +151,6 @@ * Miscellaneous configurable options **********************************************************/ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -180,8 +180,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -399,7 +397,6 @@ ************************************************************/ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /************************************************************ diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h deleted file mode 100644 index f9fc8ff7e1..0000000000 --- a/include/configs/MOUSSE.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James F. Dougherty (jfd@cs.stanford.edu) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the MOUSSE board. - * See also: http://www.vooha.com/ - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_MOUSSE 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/mousse/u-boot.lds" - -#define CONFIG_SYS_ADDR_MAP_B 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#if 1 -#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */ -#else -#define CONFIG_BOOTCOMMAND "bootm ffe10000" -#endif -#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138" -#define CONFIG_BOOTDELAY 3 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE - - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ETH_ADDR "00:10:18:10:00:06" - -#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */ - -#include "../board/mousse/mousse.h" - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_SDRAM_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#endif - -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (4 << 20) /* lots of mem ... */ -#else -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */ -#endif -#define CONFIG_SYS_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_ISA_MEM 0xFD000000 -#define CONFIG_SYS_ISA_IO 0xFE000000 - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(512 * 1024)) -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/ -#define FLASH_BASE0_SIZE 0x80000 /* 512K */ -#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB - 1MB - 64K FLASH0 SEG =960K - (size=0xf0000)*/ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 18432000 - -#define CONFIG_SYS_NS16550_COM1 0xFFE08080 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_ETH_DEV_FN 0x00 -#define CONFIG_SYS_ETH_IOBASE 0x00104000 - - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 8 -#define CONFIG_SYS_ROMFAL 8 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_REFINT 0xf5 /* Refresh interval */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 0x79 - -#ifdef INCLUDE_ECC -#define USE_ECC 1 -#else /* INCLUDE_ECC */ -#define USE_ECC 0 -#endif /* INCLUDE_ECC */ - - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT (4+USE_ECC) /* Data latancy from read command */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 2 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC) - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ -#define CONFIG_SYS_RAM_SIZE 0x04000000 /* 64MB */ - - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0x7f - - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory - see 8240 book for details*/ -#define PCI_MEM_SPACE1_START 0x80000000 -#define PCI_MEM_SPACE2_START 0xfd000000 - -/* IBAT/DBAT Configuration */ -/* Ram: 64MB, starts at address-0, r/w instruction/data */ -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L - -/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */ -#define CONFIG_SYS_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP) -#if 0 -#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\ - BATL_WRITETHROUGH | BATL_CACHEINHIBIT) -#else -#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT) -#endif -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L - -/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */ -#define CONFIG_SYS_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L - -/* PCI Memory region 2: PCI Devices in 0xFD space */ -#define CONFIG_SYS_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L - - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment Sector */ -#else -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/ -#define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR -#define CONFIG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -/* Localizations */ -#if 0 -#define CONFIG_ETHADDR 0:0:0:0:1:d -#define CONFIG_IPADDR 172.16.40.113 -#define CONFIG_SERVERIP 172.16.40.111 -#else -#define CONFIG_ETHADDR 0:0:0:0:1:d -#define CONFIG_IPADDR 209.128.93.138 -#define CONFIG_SERVERIP 209.128.93.133 -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h deleted file mode 100644 index 0f6ca94262..0000000000 --- a/include/configs/MPC8260ADS.h +++ /dev/null @@ -1,554 +0,0 @@ -/* - * (C) Copyright 2001 - * Stuart Hughes - * This file is based on similar values for other boards found in other - * U-Boot config files, and some that I found in the mpc8260ads manual. - * - * Note: my board is a PILOT rev. - * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. - * - * (C) Copyright 2003-2004 Arabella Software Ltd. - * Yuli Barcohen - * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. - * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. - * Ported to MPC8272ADS board. - * - * Copyright (c) 2005 MontaVista Software, Inc. - * Vitaly Bordug - * Added support for PCI bridge on MPC8272ADS - * - * Copyright (C) Freescale Semiconductor, Inc. 2006-2009. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ -#endif - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * Figure out if we are booting low via flash HRCW or high via the BCSR. - */ -#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* ADS flavours */ -#define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */ -#define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */ -#define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */ -#define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */ - -#ifndef CONFIG_ADSTYPE -#define CONFIG_ADSTYPE CONFIG_SYS_8260ADS -#endif /* CONFIG_ADSTYPE */ - -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS -#define CONFIG_MPC8272 1 -#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS -/* - * Actually MPC8275, but the code is littered with ifdefs that - * apply to both, or which use this ifdef to assume board-specific - * details. :-( - */ -#define CONFIG_MPC8272 1 -#else -#define CONFIG_MPC8260 1 -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* allow serial and ethaddr to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if CONFIG_ETHER_INDEX == 1 - -# define CONFIG_SYS_PHY_ADDR 0 -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) - -#elif CONFIG_ETHER_INDEX == 2 - -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */ -# define CONFIG_SYS_PHY_ADDR 3 -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) -#else /* RxCLK is CLK13, TxCLK is CLK14 */ -# define CONFIG_SYS_PHY_ADDR 0 -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ - -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */ -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS -#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */ -#define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */ -#else -#define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */ -#define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */ -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ - -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS -#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */ -#else -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) -#define CONFIG_SPD_ADDR 0x50 -#endif -#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */ - -/*PCI*/ -#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#define CONFIG_PCI_BOOTDELAY 0 -#define CONFIG_PCI_SCAN_SHOW -#endif - -#ifndef CONFIG_SDRAM_PBI -#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ -#endif - -#ifndef CONFIG_8260_CLKIN -#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#if defined(CONFIG_OF_LIBFDT) -#define OF_TBCLK (bd->bi_busfreq / 4) -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM - -#undef CONFIG_CMD_XIMG - -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - #undef CONFIG_CMD_SDRAM - #undef CONFIG_CMD_I2C - -#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS - #undef CONFIG_CMD_SDRAM - #undef CONFIG_CMD_I2C - -#else - #undef CONFIG_CMD_PCI - -#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */ - - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2" - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_FLASH_BASE 0xff800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -/* - * JFFS2 partitions - * - * Note: fake mtd_id used, no linux mtd map file - */ -#define MTDIDS_DEFAULT "nor0=mpc8260ads-0" -#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)" -#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS - -/* this is stuff came out of the Motorola docs */ -#ifndef CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 -#endif - -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_BCSR 0xF4500000 -#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS -#define CONFIG_SYS_PCI_INT 0xF8200000 -#endif -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_LSDRAM_BASE 0xFD000000 - -#define RS232EN_1 0x02000002 -#define RS232EN_2 0x01000001 -#define FETHIEN1 0x08000008 -#define FETH1_RST 0x04000004 -#define FETHIEN2 0x10000000 -#define FETH2_RST 0x08000000 -#define BCSR_PCI_MODE 0x01000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#ifdef CONFIG_SYS_LOWBOOT -/* PQ2FADS flash HRCW = 0x0EB4B645 */ -#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ - ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\ - ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ - ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ - ) -#else -/* PQ2FADS BCSR HRCW = 0x0CB23645 */ -#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ - ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ - ( HRCW_BMS | HRCW_APPC10 ) |\ - ( HRCW_MODCK_H0101 ) \ - ) -#endif -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 -# define CONFIG_ENV_SECT_SIZE 0x40000 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE) -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SYPCR 0xFFFFFFC3 -#define CONFIG_SYS_BCR 0x100C0000 -#define CONFIG_SYS_SIUMCR 0x0A200000 -#define CONFIG_SYS_SCCR SCCR_DFBRG01 -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801) -#define CONFIG_SYS_OR0_PRELIM 0xFF800876 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801) -#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010 - -/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ - -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8010 -#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS -#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ -#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010 -#endif - -#define CONFIG_SYS_RMR RMR_CSRE -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CONFIG_SYS_RCCR 0 - -#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS) -#undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */ -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */ - -#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS -#define CONFIG_SYS_OR2 0xFE002EC0 -#define CONFIG_SYS_PSDMR 0x824B36A3 -#define CONFIG_SYS_PSRT 0x13 -#define CONFIG_SYS_LSDMR 0x828737A3 -#define CONFIG_SYS_LSRT 0x13 -#define CONFIG_SYS_MPTPR 0x2800 -#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS -#define CONFIG_SYS_OR2 0xFC002CC0 -#define CONFIG_SYS_PSDMR 0x834E24A3 -#define CONFIG_SYS_PSRT 0x13 -#define CONFIG_SYS_MPTPR 0x2800 -#else -#define CONFIG_SYS_OR2 0xFF000CA0 -#define CONFIG_SYS_PSDMR 0x016EB452 -#define CONFIG_SYS_PSRT 0x21 -#define CONFIG_SYS_LSDMR 0x0086A522 -#define CONFIG_SYS_LSRT 0x21 -#define CONFIG_SYS_MPTPR 0x1900 -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ - -#define CONFIG_SYS_RESET_ADDRESS 0x04400000 - -#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS - -/* PCI Memory map (if different from default map */ -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ -#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ -#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) - - -/* PCIBR0 - for PCI IO*/ -#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */ -#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ -/* PCIBR1 - prefetch and non-prefetch regions joined together */ -#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL -#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U) - -#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ - -#define CONFIG_HAS_ETH0 - -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_NETDEV eth0 -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" __stringify(CONFIG_NETDEV) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=400000\0" \ - "console=ttyCPM0\0" \ - "setbootargs=setenv bootargs " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv rootdev /dev/nfs;" \ - "run setipargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv rootdev /dev/ram;" \ - "run setbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h deleted file mode 100644 index 5a101cf612..0000000000 --- a/include/configs/MPC8266ADS.h +++ /dev/null @@ -1,567 +0,0 @@ -/* - * (C) Copyright 2001 - * Stuart Hughes - * This file is based on similar values for other boards found in other - * U-Boot config files, and some that I found in the mpc8260ads manual. - * - * Note: my board is a PILOT rev. - * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm - */ - -/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - !! !! - !! This configuration requires JP3 to be in position 1-2 to work !! - !! To make it work for the default, the CONFIG_SYS_TEXT_BASE define in !! - !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !! - !! 0xfff00000 !! - !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !! - !! !! - !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* allow serial and ethaddr to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#if (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Half duplex - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -/* other options */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* PCI */ -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#define CONFIG_PCI_BOOTDELAY 0 -#undef CONFIG_PCI_SCAN_SHOW - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include - -/* Commands we want, that are not part of default set */ -#define CONFIG_CMD_ASKENV /* ask for env variable */ -#define CONFIG_CMD_CACHE /* icache, dcache */ -#define CONFIG_CMD_DHCP /* DHCP Support */ -#define CONFIG_CMD_DIAG /* Diagnostics */ -#define CONFIG_CMD_IMMAP /* IMMR dump support */ -#define CONFIG_CMD_IRQ /* irqinfo */ -#define CONFIG_CMD_MII /* MII support */ -#define CONFIG_CMD_PCI /* pciinfo */ -#define CONFIG_CMD_PING /* ping support */ -#define CONFIG_CMD_PORTIO /* Port I/O */ -#define CONFIG_CMD_REGINFO /* Register dump */ -#define CONFIG_CMD_SAVES /* save S record dump */ -#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ - -/* Commands from default set we don't need */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - /* for versions < 2.4.5-pre5 */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define FLASH_BASE 0xFE000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* this is stuff came out of the Motorola docs */ -/* Only change this if you also change the Hardware configuration Word */ -#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 - -/* Set IMMR to 0xF0000000 or above to boot Linux */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_BCSR 0xF8000000 -#define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */ - -/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes - */ -/*#define CONFIG_VERY_BIG_RAM 1*/ - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? This will normally auto-configure via the SPD. -*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 - -#define SDRAM_SPD_ADDR 0x50 - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2,3 - SDRAM DIMM - */ - -/* The BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM_SIZE == 64) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) -#elif (CONFIG_SYS_SDRAM_SIZE == 16) -#define CONFIG_SYS_OR2_PRELIM (0xFF000C80) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -#if (CONFIG_SYS_SDRAM_SIZE == 64) -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#elif (CONFIG_SYS_SDRAM_SIZE == 16) -/* With a 16 MB DIMM, the PSDMR is configured as follows: - * - * configuration parameters found in Motorola documentation - */ -#define CONFIG_SYS_PSDMR (0x016EB452) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -#define RS232EN_1 0x02000002 -#define RS232EN_2 0x01000001 -#define FETHIEN 0x08000008 -#define FETH_RST 0x04000004 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */ -/* 0x0EB2B645 */ -#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\ - ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\ - ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ - ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ - ) - -/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */ -/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */ - -/* This value should actually be situated in the first 256 bytes of the FLASH - which on the standard MPC8266ADS board is at address 0xFF800000 - The linker script places it at 0xFFF00000 instead. - - It still works, however, as long as the ADS board jumper JP3 is set to - position 2-3 so the board is using the BCSR as Hardware Configuration Word - - If you want to use the one defined here instead, ust copy the first 256 bytes from - 0xfff00000 to 0xff800000 (for 8MB flash) - - - Rune - -*/ - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -/*#define CONFIG_SYS_HID0_INIT 0 */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SYPCR 0xFFFFFFC3 -#define CONFIG_SYS_BCR 0x004C0000 -#define CONFIG_SYS_SIUMCR 0x4E64C000 -#define CONFIG_SYS_SCCR 0x00000000 - -/* local bus memory map - * - * 0x00000000-0x03FFFFFF 64MB SDRAM - * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window - * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window - * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory - * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window - * 0xF8000000-0xF8007FFF 32KB BCSR - * 0xF8100000-0xF8107FFF 32KB ATM UNI - * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller - * 0xF8300000-0xF8307FFF 32KB EEPROM - * 0xFE000000-0xFFFFFFFF 32MB flash - */ -#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */ -#define CONFIG_SYS_OR0_PRELIM 0xFE000836 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010 -#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846 -#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */ -#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36 -#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ -#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010 - -#define CONFIG_SYS_RMR 0x0001 -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CONFIG_SYS_RCCR 0 -#define CONFIG_SYS_MPTPR 0x00001900 -#define CONFIG_SYS_PSRT 0x00000021 - -/* This address must not exist */ -#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00 - -/* PCI Memory map (if different from default map */ -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* PCIBR0 */ -#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */ -#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */ -/* PCIBR1 */ -#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ -#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */ - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ -#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the third set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ -#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index d315729b8b..bf974fd461 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ @@ -462,7 +461,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -471,7 +469,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 6c6ce58fb8..dd8122965a 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -1,7 +1,7 @@ /* * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* * mpc8313epb board configuration file @@ -14,17 +14,14 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 #define CONFIG_MPC8313ERDB 1 #ifdef CONFIG_NAND -#define CONFIG_SPL #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND @@ -512,7 +509,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print Buffer Size */ @@ -521,7 +517,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index fef19d4b5f..98e907245a 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -15,14 +15,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#ifdef CONFIG_NAND_U_BOOT -#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ -#endif /* CONFIG_NAND_SPL */ -#endif /* CONFIG_NAND_U_BOOT */ - #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFE000000 #endif @@ -35,7 +27,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC831x 1 /* MPC831x CPU family */ #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ @@ -94,10 +85,6 @@ */ #define CONFIG_SYS_IMMR 0xE0000000 -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR -#endif - /* * Arbiter Setup */ @@ -282,17 +269,10 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */ -#ifdef CONFIG_NAND_U_BOOT -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#else #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM -#endif #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) @@ -460,16 +440,7 @@ /* * Environment */ -#if defined(CONFIG_NAND_U_BOOT) - #define CONFIG_ENV_IS_IN_NAND 1 - #define CONFIG_ENV_OFFSET (512 * 1024) - #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) - #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_RANGE) -#elif !defined(CONFIG_SYS_RAMBOOT) +#if !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR \ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) @@ -504,7 +475,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_PCI -#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) +#if defined(CONFIG_SYS_RAMBOOT) #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -519,7 +490,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -532,7 +502,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -636,7 +605,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index d5db65df11..65a63e2b7f 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -14,7 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_SYS_TEXT_BASE 0xFE000000 @@ -355,7 +354,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -368,7 +366,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -483,7 +480,6 @@ #if (CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 32e05af8ab..1735b3c521 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -12,7 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ @@ -441,7 +440,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -454,7 +452,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -576,7 +573,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 432db72daa..6b7d648944 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -2,7 +2,7 @@ * (C) Copyright 2006-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ @@ -62,11 +61,12 @@ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ /* - * define CONFIG_FSL_DDR2 to use unified DDR driver + * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver * undefine it to use old spd_sdram.c */ -#define CONFIG_FSL_DDR2 -#ifdef CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 +#ifdef CONFIG_SYS_FSL_DDR2 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x51 @@ -507,7 +507,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -520,7 +519,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -738,7 +736,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index c3a577f40a..398918a940 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -1,7 +1,7 @@ /* * Copyright (C) Freescale Semiconductor, Inc. 2006. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -47,7 +47,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC83xx 1 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */ @@ -562,7 +561,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -731,7 +729,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h deleted file mode 100644 index 7c4f3ef8f1..0000000000 --- a/include/configs/MPC8360EMDS.h +++ /dev/null @@ -1,739 +0,0 @@ -/* - * Copyright (C) 2006,2011 Freescale Semiconductor, Inc. - * - * Dave Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ -#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ -#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ - -/* - * System Clock Setup - */ -#ifdef CONFIG_CLKIN_33MHZ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 33330000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 33330000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33330000 -#endif - -#elif defined(CONFIG_CLKIN_66MHZ) -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif -#else -#error Unknown oscillator frequency. -#endif - -/* - * Hardware Reset Configuration Word - */ -#ifdef CONFIG_CLKIN_33MHZ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_8X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CE_PLL_VCO_DIV_4 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X15 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif defined(CONFIG_CLKIN_66MHZ) -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CE_PLL_VCO_DIV_4 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X6 |\ - HRCWL_CORE_TO_CSB_2X1) -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCICKDRV_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCICKDRV_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT) -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x40000000 - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE - /* + 256M */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x47d00432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#else -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_9) -#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ -#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ -#endif -#endif - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * The reserved memory - */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * BCSR on the Local Bus - */ -#define CONFIG_SYS_BCSR 0xF8000000 - /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFFE9F7 */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CONFIG_SYS_LB_SDRAM -#define CONFIG_SYS_LBLAWBAR2 0 -#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB) - -/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * - * For BR2, need: - * Base address = BR[0:16] = dynamic - * port size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861 - */ - -/* Port size=32bit, MSEL=DRAM */ -#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */ - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -#endif - -/* - * Windows to access Platform I/O Boards (PIB) via local bus - */ -#define CONFIG_SYS_PIB_BASE 0xF8008000 -#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) - -/* [RFC] This LBLAW only covers the 2nd window (CS5) */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM \ - CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -/* - * CS4 on Local Bus, to PIB - */ - /* CS4 base address at 0xf8008000 */ -#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8008801 */ -#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffffe9f7 */ - -/* - * CS5 on Local Bus, to PIB - */ - /* CS5 base address at 0xf8010000 */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \ - CONFIG_SYS_PIB_WINDOW_SIZE) \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8010801 */ -#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffffe9f7 */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_83XX_PCI_STREAMING - -#undef CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - - -#define CONFIG_HWCONFIG 1 - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" -#define CONFIG_PHY_MODE_NEED_CHANGE - -#define CONFIG_UEC_ETH1 /* GETH1 */ - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 -#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 -#endif - -#define CONFIG_UEC_ETH2 /* GETH2 */ - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 -#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x20000 - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SDRAM - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - - /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ -#define CONFIG_BAT_RW - -/* DDR/LBC SDRAM: cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_4M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* DDR/LBC SDRAM next 256M: cacheable */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc836x_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h deleted file mode 100644 index 1973447a23..0000000000 --- a/include/configs/MPC8360ERDK.h +++ /dev/null @@ -1,624 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ -#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xFF800000 - -/* - * System Clock Setup - */ -#ifdef CONFIG_CLKIN_33MHZ -#define CONFIG_83XX_CLKIN 33333333 -#define CONFIG_SYS_CLK_FREQ 33333333 -#define CONFIG_PCI_33M 1 -#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 -#else -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_PCI_66M 1 -#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1 -#endif /* CONFIG_CLKIN_33MHZ */ - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\ - HRCWL_CORE_TO_CSB_2X1 |\ - HRCWL_CE_TO_PLL_1X15) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCICKDRV_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_SECONDARY_DDR_DISABLE |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_EARLY) - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x40000000 - -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x80080001 */ - -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10 \ - | CSCONFIG_ODT_WR_ONLY_CURRENT) -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_ECC_EN) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \ - | (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_MODE 0x47800432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (10 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (0 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */ - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * NAND flash on the local bus - */ -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_CMD_NAND 1 -#define CONFIG_NAND_FSL_UPM 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -/* - * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB - * ... What's correct? - */ -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -/* Port size 8 bit, UPMA */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_PS_8 \ - | BR_MS_UPMA \ - | BR_V) - /* 0x60000881 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD) - /* 0xFC000001 */ - -/* - * Fujitsu MB86277 (MINT) graphics controller - */ -#define CONFIG_SYS_VIDEO_BASE 0x70000000 - -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - -/* Port size 32 bit, UPMB */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \ - | BR_PS_32 \ - | BR_MS_UPMB \ - | BR_V) - /* 0x000018a1 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD) - /* 0xFC000001 */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_PCI - -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 -#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 2 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 -#endif - -#define CONFIG_UEC_ETH2 /* GETH2 */ - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 -#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x20000 -#else /* CONFIG_SYS_RAMBOOT */ -#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CONFIG_SYS_RAMBOOT */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_LOADS -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - - /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_4M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \ - | BATU_BL_64M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \ - | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \ - | BATU_BL_64M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else /* CONFIG_PCI */ -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADADDR a00000 -#define CONFIG_HOSTNAME mpc8360erdk -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_ROOTPATH "/nfsroot/" - -#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "loadaddr=a00000\0" \ - "fdtaddr=900000\0" \ - "fdtfile=mpc836x_rdk.dtb\0" \ - "fsfile=fs\0" \ - "ubootfile=u-boot.bin\0" \ - "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\ - "-(rootfs)\0" \ - "setbootargs=setenv bootargs console=$consoledev,$baudrate " \ - "$mtdparts panic=1\0" \ - "adddhcpargs=setenv bootargs $bootargs ip=on\0" \ - "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \ - "$gatewayip:$netmask:$hostname:$netdev:off " \ - "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ - "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \ - "rootfstype=jffs2 rw\0" \ - "tftp_get_uboot=tftp 100000 $ubootfile\0" \ - "tftp_get_kernel=tftp $loadaddr $bootfile\0" \ - "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \ - "tftp_get_fs=tftp c00000 $fsfile\0" \ - "nand_erase_kernel=nand erase 0 400000\0" \ - "nand_erase_dtb=nand erase 400000 20000\0" \ - "nand_erase_fs=nand erase 420000 3be0000\0" \ - "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \ - "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \ - "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \ - "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \ - "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \ - "nor_reflash=protect off ff800000 ff87ffff ; " \ - "erase ff800000 ff87ffff ; " \ - "cp.b 100000 ff800000 $filesize\0" \ - "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \ - "nand_write_kernel\0" \ - "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ - "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \ - "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \ - "nand_reflash_fs\0" \ - "boot_m=bootm $loadaddr - $fdtaddr\0" \ - "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\ - "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ - "boot_m\0" \ - "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ - "boot_m\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run dhcpboot" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 51688a76bf..832c10f5c0 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ @@ -388,6 +387,11 @@ extern int board_pci_host_broken(void); #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -523,7 +527,6 @@ extern int board_pci_host_broken(void); */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -536,7 +539,6 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -664,7 +666,6 @@ extern int board_pci_host_broken(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a5fe220b14..19e0e30eef 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -13,9 +13,10 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0xFE000000 @@ -538,7 +539,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -551,7 +551,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -680,7 +679,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -689,6 +687,11 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HAS_FSL_DR_USB +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_NETDEV "eth1" diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8ff2c3a4fa..27221648e4 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -11,38 +11,28 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT 1 #endif -#ifdef CONFIG_NAND -#define CONFIG_NAND_U_BOOT 1 -#define CONFIG_RAMBOOT_NAND 1 -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ -#else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -#define CONFIG_SYS_TEXT_BASE 0xf8f82000 -#endif /* CONFIG_NAND_SPL */ -#endif - #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -56,7 +46,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8536 1 #define CONFIG_MPC8536DS 1 @@ -122,7 +111,7 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -221,8 +210,7 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ - defined(CONFIG_RAMBOOT_SPIFLASH) +#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #else @@ -327,7 +315,7 @@ /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) #define CONFIG_SYS_NAND_U_BOOT_START \ (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) @@ -351,17 +339,10 @@ | OR_FCM_TRLX \ | OR_FCM_EHTR) -#ifdef CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#endif #define CONFIG_SYS_BR4_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ @@ -624,12 +605,7 @@ */ #if defined(CONFIG_SYS_RAMBOOT) -#if defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#if defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 @@ -650,11 +626,7 @@ #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 - #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 - #define CONFIG_ENV_ADDR 0xfff80000 - #else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif @@ -720,7 +692,6 @@ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -730,7 +701,6 @@ + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -742,7 +712,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index acd37a01aa..37c2b9415a 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -3,7 +3,7 @@ * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -21,7 +21,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_MPC8540 1 /* MPC8540 specific */ #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ @@ -78,7 +77,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE @@ -376,7 +375,6 @@ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -387,7 +385,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -399,7 +396,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 61775d2c28..5d229a0d20 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -1,7 +1,7 @@ /* * Copyright 2004, 2011 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -16,7 +16,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8541 1 /* MPC8541 specific */ #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ @@ -51,7 +50,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE @@ -391,7 +390,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -400,7 +398,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -412,7 +409,6 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 2a5e5d4ed9..dade6d3b89 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -14,7 +14,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8544 1 #define CONFIG_MPC8544DS 1 @@ -63,7 +62,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -318,6 +317,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 @@ -421,7 +421,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -430,7 +429,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -442,7 +440,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 8deb241c39..190c668303 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -20,7 +20,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ @@ -75,7 +74,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD @@ -516,7 +515,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -525,7 +523,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -537,7 +534,6 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 1ec3797e7c..5263ffcc8d 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -1,7 +1,7 @@ /* * Copyright 2004, 2011 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -16,7 +16,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8555 1 /* MPC8555 specific */ #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ @@ -51,7 +50,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE @@ -389,7 +388,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -398,7 +396,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -410,7 +407,6 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 49f6a35332..ac78d481d6 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -3,7 +3,7 @@ * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -21,7 +21,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ #define CONFIG_MPC8560 1 @@ -75,7 +74,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE @@ -417,7 +416,6 @@ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -428,7 +426,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -440,7 +437,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 2d5e8c0b7b..02a5acf38e 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -1,7 +1,7 @@ /* * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -13,7 +13,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ @@ -60,7 +59,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD @@ -411,7 +410,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -420,7 +418,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -432,7 +429,6 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index c35fd2bdbc..4da247c51a 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -1,7 +1,7 @@ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -13,7 +13,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ #define CONFIG_MPC8569 1 /* MPC8569 specific */ #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ @@ -50,18 +49,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#ifdef CONFIG_NAND -#define CONFIG_NAND_U_BOOT 1 -#define CONFIG_RAMBOOT_NAND 1 -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ -#else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -#define CONFIG_SYS_TEXT_BASE 0xf8f82000 -#endif -#endif - #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 #endif @@ -98,7 +85,7 @@ extern unsigned long get_clock_freq(void); #endif /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD @@ -181,12 +168,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#else #undef CONFIG_SYS_RAMBOOT -#endif #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -229,17 +211,10 @@ extern unsigned long get_clock_freq(void); | OR_FCM_TRLX \ | OR_FCM_EHTR) -#ifdef CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */ -#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#endif #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ @@ -477,11 +452,6 @@ extern unsigned long get_clock_freq(void); * Environment */ #if defined(CONFIG_SYS_RAMBOOT) -#if defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#endif #else #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -494,7 +464,7 @@ extern unsigned long get_clock_freq(void); /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 +#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 /* * BOOTP options @@ -545,7 +515,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ #else @@ -556,7 +525,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -568,7 +536,6 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 05d8870500..0b07876e78 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -11,26 +11,17 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif -#ifdef CONFIG_NAND -#define CONFIG_NAND_U_BOOT -#define CONFIG_RAMBOOT_NAND -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ -#else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -#define CONFIG_SYS_TEXT_BASE 0xf8f82000 -#endif /* CONFIG_NAND_SPL */ -#endif - #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -44,7 +35,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8572 1 #define CONFIG_MPC8572DS 1 #define CONFIG_MP 1 /* support multiple processors */ @@ -106,7 +96,7 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -206,12 +196,7 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#else #undef CONFIG_SYS_RAMBOOT -#endif #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -322,6 +307,8 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_MAX_OOBFREE 5 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 @@ -349,17 +336,10 @@ | OR_FCM_TRLX \ | OR_FCM_EHTR) -#ifdef CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#endif #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ | (2< " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -669,7 +643,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -681,7 +654,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1553a746c8..e6d570a6af 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -14,7 +14,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ @@ -92,7 +91,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ #define CONFIG_DDR_SPD @@ -326,6 +325,7 @@ #define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 @@ -496,7 +496,6 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -507,7 +506,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -518,7 +516,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 6ca6f6b807..a0d7d52627 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -3,7 +3,7 @@ * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -16,8 +16,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_MP 1 /* support multiple processors */ @@ -108,7 +110,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -412,6 +414,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 @@ -649,7 +652,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -660,7 +662,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -671,7 +672,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h deleted file mode 100644 index beada7ee2a..0000000000 --- a/include/configs/MPC86xADS.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola MPC8xxADS board. Copied from the FADS config. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* board type */ -#define CONFIG_MPC86xADS 1 /* new ADS */ -#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ - -/* CPU type - pick one of these */ -#define CONFIG_MPC866T 1 -#undef CONFIG_MPC866P -#undef CONFIG_MPC859T -#undef CONFIG_MPC859DSL -#undef CONFIG_MPC852T - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 -#define CONFIG_SYS_8xx_CPUCLK_MAX 80000000 - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -#include "../../board/fads/fads.h" - -#define CONFIG_SYS_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V) - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h deleted file mode 100644 index eeb2355b9f..0000000000 --- a/include/configs/MPC885ADS.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola MPC885ADS board. Values common to all FADS family boards - * are in board/fads/fads.h - * - * Copyright (C) 2003-2004 Arabella Software Ltd. - * Yuli Barcohen - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC885ADS 1 /* MPC885ADS board */ -#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ - -#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 - -#define CONFIG_SDRAM_50MHZ 1 - -#include "../../board/fads/fads.h" - -#define CONFIG_SYS_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V) - -#define CONFIG_HAS_ETH1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h deleted file mode 100644 index 96efc63d7a..0000000000 --- a/include/configs/MUSENKI.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the MUSENKI board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_MUSENKI 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ -#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_SYS_HZ 1000 - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 7 -#define CONFIG_SYS_ROMFAL 11 -#define CONFIG_SYS_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 121 - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFFF0000 -#define CONFIG_ENV_SIZE 0x00010000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h deleted file mode 100644 index b7bc920f00..0000000000 --- a/include/configs/MVBC_P.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2008 - * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_MPC5xxx 1 -#define CONFIG_MPC5200 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFF800000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_PSC_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#undef CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 -#define CONFIG_HIGH_BATS 1 - -#define MV_CI mvBlueCOUGAR-P -#define MV_VCI mvBlueCOUGAR-P -#define MV_FPGA_DATA 0xff860000 -#define MV_FPGA_SIZE 0 -#define MV_KERNEL_ADDR 0xffd00000 -#define MV_INITRD_ADDR 0xff900000 -#define MV_INITRD_LENGTH 0x00400000 -#define MV_SCRATCH_ADDR 0x00000000 -#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH -#define MV_SCRIPT_ADDR 0xff840000 -#define MV_SCRIPT_ADDR2 0xff850000 -#define MV_DTB_ADDR 0xfffc0000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define MV_DTB_NAME mvbc-p.dtb -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * Supported commands - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_I2C - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME - -/* - * Autoboot - */ -#define CONFIG_BOOTDELAY 2 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ - then source ${script_addr}; \ - else source ${script_addr2}; \ - fi;" - -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "console=yes\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \ - "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \ - "dtb_name=" __stringify(MV_DTB_NAME) "\0" \ - "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \ - "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" __stringify(MV_CI) "\0" \ - "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.90.10\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvbc-p-rfs\0" \ - "zcip=no\0" \ - "netboot=yes\0" \ - "mvtest=Ff\0" \ - "tried_bootfromflash=no\0" \ - "tried_bootfromnet=no\0" \ - "use_dhcp=yes\0" \ - "gev_start=yes\0" \ - "mvbcdma_debug=0\0" \ - "mvbcia_debug=0\0" \ - "propdev_debug=0\0" \ - "gevss_debug=0\0" \ - "watchdog=1\0" \ - "sensor_cnt=1\0" \ - "" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 - -/* - * Flash configuration - */ -#undef CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_FLASH_PROTECTION - -#define CONFIG_ENV_ADDR 0xFFFE0000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (512 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 86000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Ethernet configuration - */ -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_E1000 -#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 } -#undef CONFIG_MPC5xxx_FEC -#undef CONFIG_PHY_ADDR -#define CONFIG_NETDEV eth0 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#undef CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x02f00000 - -#define CONFIG_SYS_HZ 1000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x02000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x00200000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004 - -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x000000f0 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 - -#define CONFIG_SYS_RESET_ADDRESS 0x00000100 - -#undef FPGA_DEBUG -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA 1 -#define CONFIG_FPGA_CYCLON2 1 -#define CONFIG_FPGA_COUNT 1 - -#endif diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h deleted file mode 100644 index 044a1bc2c8..0000000000 --- a/include/configs/MVBLM7.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright (C) Matrix Vision GmbH 2008 - * - * Matrix Vision mvBlueLYNX-M7 configuration file - * based on Freescale's MPC8349ITX. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 -#define CONFIG_MPC834x 1 -#define CONFIG_MPC8343 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_SYS_IMMR 0xE0000000 - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_SKIP_HOST_BRIDGE -#define CONFIG_TSEC_ENET -#define CONFIG_MPC8XXX_SPI -#define CONFIG_HARD_SPI -#define MVBLM7_MMC_CS 0x04000000 -#define CONFIG_MISC_INIT_R - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* - * DDR Setup - */ -#undef CONFIG_SPD_EEPROM - -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_83XX_DDR_USES_CS0 1 -#define CONFIG_SYS_MEMTEST_START (60<<20) -#define CONFIG_SYS_MEMTEST_END (70<<20) -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \ - | DDRCDR_NZ_HIZ \ - | DDRCDR_Q_DRN) - /* 0x22000001 */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_SIZE 512 - -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f - -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 -#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_INTERVAL 0x02000100 - -#define CONFIG_SYS_DDR_MODE 0x04040242 -#define CONFIG_SYS_DDR_MODE2 0x00800000 - -/* Flash */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - -/* - * U-Boot memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#undef CONFIG_SYS_RAMBOOT - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 -/* LB refresh timer prescal, 266MHz/32*/ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_CONSOLE ttyS0 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 -#define MV_DTB_NAME "mvblm7.dtb" - -/* - * PCI - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCI1_MMIO_BASE \ - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 - -#define CONFIG_NET_RETRY_COUNT 3 - -#define CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66666667 -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW - -/* TSEC */ -#define CONFIG_GMII -#define CONFIG_SYS_VSC8601_SKEWFIX -#define CONFIG_SYS_VSC8601_SKEW_TX 3 -#define CONFIG_SYS_VSC8601_SKEW_RX 3 - -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 - -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_FEC1_PHY_NORXERR -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define TSEC1_PHY_ADDR 0x10 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) - -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_FEC2_PHY_NORXERR -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) -#define TSEC2_PHY_ADDR 0x11 -#define TSEC2_PHYIDX 0 -#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) - -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME - -/* USB */ -#define CONFIG_SYS_USB_HOST -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -/* - * Environment - */ -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFF800000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_I2C -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_USB -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_HUSH_PARSER - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x200000 - -#define CONFIG_SYS_PROMPT "mvBL-M7> " -#define CONFIG_SYS_CBSIZE 256 - -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_SYS_HRCW_LOW 0x0 -#define CONFIG_SYS_HRCW_HIGH 0x0 - -/* - * System performance - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ - -/* clocking */ -#define CONFIG_SYS_SCCR_ENCCM 0 -#define CONFIG_SYS_SCCR_USBMPHCM 0 -#define CONFIG_SYS_SCCR_USBDRCM 2 -#define CONFIG_SYS_SCCR_TSEC1CM 1 -#define CONFIG_SYS_SCCR_TSEC2CM 1 - -#define CONFIG_SYS_SICRH 0x1fef0003 -#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 - -/* DDR */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* no PCI2 */ -#define CONFIG_SYS_IBAT3L 0 -#define CONFIG_SYS_IBAT3U 0 -#define CONFIG_SYS_IBAT4L 0 -#define CONFIG_SYS_IBAT4U 0 - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT7L 0 -#define CONFIG_SYS_IBAT7U 0 - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NETDEV eth0 - -/* Default path and filenames */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define MV_CI "mvBL-M7" -#define MV_VCI "mvBL-M7" -#define MV_FPGA_DATA 0xfff40000 -#define MV_FPGA_SIZE 0 -#define MV_KERNEL_ADDR 0xff810000 -#define MV_INITRD_ADDR 0xffb00000 -#define MV_SCRIPT_ADDR 0xff804000 -#define MV_SCRIPT_ADDR2 0xff806000 -#define MV_DTB_ADDR 0xff808000 -#define MV_INITRD_LENGTH 0x00400000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 - -#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \ - "then source ${script_addr}; " \ - "else source ${script_addr2}; " \ - "fi;" -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \ - "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \ - "dtb_name=" __stringify(MV_DTB_NAME) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" MV_CI "\0" \ - "dhcp_vendor-class-identifier=" MV_VCI "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.90.10\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvBL-M7-rfs\0" \ - "zcip=no\0" \ - "netboot=yes\0" \ - "mvtest=Ff\0" \ - "tried_bootfromflash=no\0" \ - "tried_bootfromnet=no\0" \ - "bootfile=mvblm72625.boot\0" \ - "use_dhcp=yes\0" \ - "gev_start=yes\0" \ - "mvbcdma_debug=0\0" \ - "mvbcia_debug=0\0" \ - "propdev_debug=0\0" \ - "gevss_debug=0\0" \ - "watchdog=0\0" \ - "usb_dr_mode=host\0" \ - "sensor_cnt=2\0" \ - "" - -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 - -#endif diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h deleted file mode 100644 index 0968b86778..0000000000 --- a/include/configs/MVBLUE.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define MV_VERSION "v0.2.0" - -/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */ -#define ERR_NONE 0 -#define ERR_ENV 1 -#define ERR_BOOTM_BADMAGIC 2 -#define ERR_BOOTM_BADCRC 3 -#define ERR_BOOTM_GUNZIP 4 -#define ERR_BOOTP_TIMEOUT 5 -#define ERR_DHCP 6 -#define ERR_TFTP 7 -#define ERR_NOLAN 8 -#define ERR_LANDRV 9 - -#define CONFIG_BOARD_TYPES 1 -#define MVBLUE_BOARD_BOX 1 -#define MVBLUE_BOARD_LYNX 2 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/mvblue/u-boot.lds" - -#if 0 -#define ERR_LED(code) do { if (code) \ - *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ - else \ - *(volatile char *)(0xff000003) = ( 1 ); \ -} while(0) -#else -#define ERR_LED(code) -#endif - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_MVBLUE 1 - -#define CONFIG_CLOCKS_IN_MHZ 1 - -#define CONFIG_BOARD_TYPES 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOT_RETRY_TIME -1 - -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "autoboot in %d seconds (stop with 's')...\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 60 - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_RUN - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -#define CONFIG_BOOTCOMMAND "run nfsboot" -#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2" - -#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "dhcp_client_id=mvBOX-XP\0" \ - "dhcp_vendor-class-identifier=mvBOX\0" \ - "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \ - "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \ - "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \ - "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ - "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \ - "mv_version=" MV_VERSION "\0" \ - "bootretry=30\0" - -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW - -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_TULIP -#define CONFIG_TULIP_FIX_DAVICOM 1 -#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 - -#define CONFIG_HW_WATCHDOG - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_LEN 0x00100000 -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ - -/* Maximum amount of RAM. */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_ISA_IO 0xFE000000 - -/* - * serial configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CONFIG_SYS_HZ 10000 - -/* Bit-field values for MCCR1. */ -#define CONFIG_SYS_ROMNAL 7 -#define CONFIG_SYS_ROMFAL 11 - -/* Bit-field values for MCCR2. */ -#define CONFIG_SYS_TSWAIT 0x5 -#define CONFIG_SYS_REFINT 430 - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CONFIG_SYS_BSTOPRE 121 - -/* Bit-field values for MCCR3. */ -#define CONFIG_SYS_REFREC 8 - -/* Bit-field values for MCCR4. */ -#define CONFIG_SYS_PRETOACT 3 -#define CONFIG_SYS_ACTTOPRE 5 -#define CONFIG_SYS_ACTORW 3 -#define CONFIG_SYS_SDMODE_CAS_LAT 3 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 -#define CONFIG_SYS_DBUS_SIZE2 1 -#define CONFIG_SYS_SDMODE_WRAP 0 - -#define CONFIG_SYS_PGMAX 0x32 -#define CONFIG_SYS_SDRAM_DSCD 0x20 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 63 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - - -#define CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_ENV_OFFSET 0x00010000 -#define CONFIG_ENV_SIZE 0x00010000 -#define CONFIG_ENV_SECT_SIZE 0x00010000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h deleted file mode 100644 index 2ddca10af4..0000000000 --- a/include/configs/MVS1.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_MVS 1 /* ...on a MVsensor module */ -#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */ -#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo To mount root over NFS use \"run bootnet\";" \ - "echo To mount root from FLASH use \"run bootflash\";" \ - "echo" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG /* watchdog disabled/enabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_VENDOREX - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_IMI -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_RUN - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 - -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */ -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */ -#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */ -#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */ - - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#undef FLASH_BASE1_PRELIM - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - - -/* - * FLASH timing: - */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -/* -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) -*/ - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#ifdef CONFIG_MVS_16BIT_FLASH -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#else -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) -#endif - -#undef CONFIG_SYS_OR1_REMAP -#undef CONFIG_SYS_OR1_PRELIM -#undef CONFIG_SYS_BR1_PRELIM -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#undef SDRAM_BASE3_PRELIM -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#undef CONFIG_SYS_OR3_PRELIM -#undef CONFIG_SYS_BR3_PRELIM - - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#define CONFIG_SYS_MAMR_PTA 98 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h deleted file mode 100644 index 47f5c32d64..0000000000 --- a/include/configs/MVSMR.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2010 - * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_MPC5xxx 1 -#define CONFIG_MPC5200 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFF800000 -#endif -#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds" - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_PSC_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\ - 230400} - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#undef CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 -#define CONFIG_HIGH_BATS 1 - -#define MV_CI mvSMR -#define MV_VCI mvSMR -#define MV_FPGA_DATA 0xff840000 -#define MV_FPGA_SIZE 0x1ff88 -#define MV_KERNEL_ADDR 0xfff00000 -#define MV_SCRIPT_ADDR 0xff806000 -#define MV_INITRD_ADDR 0xff880000 -#define MV_INITRD_LENGTH 0x00240000 -#define MV_SCRATCH_ADDR 0xffcc0000 -#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_INITRD_ADDR_RAM 0x00400000 - -/* - * Supported commands - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_VENDOREX - -/* - * Autoboot - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "abcdefg" -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_BOOTCOMMAND "source ${script_addr}" -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \ - " allocate=6M" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "console=no\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \ - "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" __stringify(MV_CI) "\0" \ - "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.0.101\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvsmr-rfs\0" \ - "zcip=yes\0" \ - "netboot=no\0" \ - "" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK - -/* - * Flash configuration - */ -#undef CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 - -/* used by linker script to wrap code around */ -#define CONFIG_SCRIPT_OFFSET 0x6000 -#define CONFIG_SCRIPT_SECT_SIZE 0x2000 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (512 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 86000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Ethernet configuration - */ -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_MPC5xxx_FEC -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_NETDEV eth0 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#undef CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x02f00000 - -#define CONFIG_SYS_HZ 1000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x02000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x00200000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044 - -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x000000f0 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 - -#define CONFIG_SYS_RESET_ADDRESS 0x00000100 - -#undef FPGA_DEBUG -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX 1 -#define CONFIG_FPGA_SPARTAN2 1 -#define CONFIG_FPGA_COUNT 1 - -#endif diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index dc4a7681be..88df94f112 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -10,8 +10,6 @@ #define __MIGO_R_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4 1 #define CONFIG_CPU_SH7722 1 #define CONFIG_MIGO_R 1 @@ -43,7 +41,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -123,7 +120,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ -#define CONFIG_SYS_HZ 1000 #endif /* __MIGO_R_H */ diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h deleted file mode 100644 index dbf2efc69e..0000000000 --- a/include/configs/NETPHONE.h +++ /dev/null @@ -1,704 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2 -#error Unsupported CONFIG_NETPHONE version -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ -#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -/* #define CONFIG_XIN 10000000 */ -#define CONFIG_XIN 50000000 -/* #define MPC8XX_HZ 120000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_SOURCE -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 -#define CONFIG_RMII 1 /* use RMII interface */ - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ -#define CONFIG_FEC1_PHY_NORXERR 1 - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 4 -#define CONFIG_FEC2_PHY_NORXERR 1 - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_CDP - - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#if CONFIG_NETPHONE_VERSION == 2 -#define CONFIG_SYS_FLASH_BASE4 0x40080000 -#endif - -#define CONFIG_SYS_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#if CONFIG_NETPHONE_VERSION == 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#elif CONFIG_NETPHONE_VERSION == 2 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#endif -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 120000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 50000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 25000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 40000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 75000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif - -#elif CONFIG_XIN == 50000000 - -#if MPC8XX_HZ == 120000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 50MHz -#endif - -#else - -#error unsupported XIN freq -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#if CONFIG_NETPHONE_VERSION == 2 - -#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ - -#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#endif - -/* - * BR3 and OR3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define DSP_SIZE 0x00010000 /* 64K */ -#define NAND_SIZE 0x00010000 /* 64K */ - -#define DSP_BASE 0xF1000000 -#define NAND_BASE 0xF1010000 - -/*****************************************************************************/ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/*****************************************************************************/ - -#if CONFIG_NETPHONE_VERSION == 1 -#define STATUS_LED_BIT 0x00000008 /* bit 28 */ -#elif CONFIG_NETPHONE_VERSION == 2 -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ -#endif - -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \ - else \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/*********************************************************************************************************** - - ---------------------------------------------------------------------------------------------- - - (V1) version 1 of the board - (V2) version 2 of the board - - ---------------------------------------------------------------------------------------------- - - Pin definitions: - - +------+----------------+--------+------------------------------------------------------------ - | # | Name | Type | Comment - +------+----------------+--------+------------------------------------------------------------ - | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select - | PA7 | DSP_INT | Output | DSP interrupt - | PA10 | DSP_RESET | Output | DSP reset - | PA14 | USBOE | Output | USB (1) - | PA15 | USBRXD | Output | USB (1) - | PB19 | BT_RTS | Output | Bluetooth (0) - | PB23 | BT_CTS | Output | Bluetooth (0) - | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select - | PB27 | SPICS_DISP | Output | Display chip select - | PB28 | SPI_RXD_3V | Input | SPI Data Rx - | PB29 | SPI_TXD | Output | SPI Data Tx - | PB30 | SPI_CLK | Output | SPI Clock - | PC10 | DISPA0 | Output | Display A0 - | PC11 | BACKLIGHT | Output | Display backlit - | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD - | | IO_RESET | Output | (V2) General I/O reset - | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) - | | HOOK | Input | (V2) Hook input interrupt - | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK - | | F_RY_BY | Input | (V2) NAND F_RY_BY - | PE17 | F_ALE | Output | NAND F_ALE - | PE18 | F_CLE | Output | NAND F_CLE - | PE20 | F_CE | Output | NAND F_CE - | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select - | | LED | Output | (V2) LED - | PE27 | SPICS_ER | Output | External serial register CS - | PE28 | LEDIO1 | Output | (V1) LED - | | BKBR1 | Input | (V2) Keyboard input scan - | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) - | | BKBR2 | Input | (V2) Keyboard input scan - | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) - | | BKBR3 | Input | (V2) Keyboard input scan - | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY - | | BKBR4 | Input | (V2) Keyboard input scan - +------+----------------+--------+--------------------------------------------------- - - ---------------------------------------------------------------------------------------------- - - Serial register input: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | 0 | BKBR1 | (V1) Keyboard input scan - | 1 | BKBR3 | (V1) Keyboard input scan - | 2 | BKBR4 | (V1) Keyboard input scan - | 3 | BKBR2 | (V1) Keyboard input scan - | 4 | HOOK | (V1) Hook switch - | 5 | BT_LINK | (V1) Bluetooth link status - | 6 | HOST_WAKE | (V1) Bluetooth host wake up - | 7 | OK_ETH | (V1) Cisco inline power OK status - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Serial register output: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | 0 | KEY1 | Keyboard output scan - | 1 | KEY2 | Keyboard output scan - | 2 | KEY3 | Keyboard output scan - | 3 | KEY4 | Keyboard output scan - | 4 | KEY5 | Keyboard output scan - | 5 | KEY6 | Keyboard output scan - | 6 | KEY7 | Keyboard output scan - | 7 | BT_WAKE | Bluetooth wake up - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Chip selects: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | CS0 | CS0 | Boot flash - | CS1 | CS_FLASH | NAND flash - | CS2 | CS_DSP | DSP - | CS3 | DCS_DRAM | DRAM - | CS4 | CS_FLASH2 | (V2) 2nd flash - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Interrupts: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IRQ1 | IRQ_DSP | DSP interrupt - | IRQ3 | S_INTER | DUSLIC ??? - | IRQ4 | F_RY_BY | NAND - | IRQ7 | IRQ_MAX | MAX 3100 interrupt - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Interrupts on PCMCIA pins: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface - | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface - | IP_A2| RMII1_MDINT | PHY interrupt for #1 - | IP_A3| RMII2_MDINT | PHY interrupt for #2 - | IP_A5| HOST_WAKE | (V2) Bluetooth host wake - | IP_A6| OK_ETH | (V2) Cisco inline power OK - +------+----------------+------------------------------------------------------------ - -*************************************************************************************************/ - -#define CONFIG_SED156X 1 /* use SED156X */ -#define CONFIG_SED156X_PG12864Q 1 /* type of display used */ - -/* serial interfacing macros */ - -#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define SED156X_SPI_RXD_MASK 0x00000008 - -#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define SED156X_SPI_TXD_MASK 0x00000004 - -#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define SED156X_SPI_CLK_MASK 0x00000002 - -#define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define SED156X_CS_MASK 0x00000010 - -#define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define SED156X_A0_MASK 0x0020 - -/*************************************************************************************************/ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 - -/*************************************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_SHOW_ACTIVITY - -/*************************************************************************************************/ - -/* phone console configuration */ - -#define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */ - -/*************************************************************************************************/ - -#define CONFIG_CDP_DEVICE_ID 20 -#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ -#define CONFIG_CDP_PORT_ID "eth%d" -#define CONFIG_CDP_CAPABILITIES 0x00000010 -#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME -#define CONFIG_CDP_PLATFORM "Intracom NetPhone" -#define CONFIG_CDP_TRIGGER 0x20020001 -#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ -#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ - -/*************************************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 - -/*************************************************************************************************/ - -#define CONFIG_CRC32_VERIFY 1 - -/*************************************************************************************************/ - -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*************************************************************************************************/ -#endif /* __CONFIG_H */ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h deleted file mode 100644 index 53b0f13687..0000000000 --- a/include/configs/NETTA.h +++ /dev/null @@ -1,669 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_NETTA 1 /* ...on a NetTA board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -/* #define CONFIG_XIN 10000000 */ -#define CONFIG_XIN 50000000 -#define MPC8XX_HZ 120000000 -/* #define MPC8XX_HZ 100000000 */ -/* #define MPC8XX_HZ 50000000 */ -/* #define MPC8XX_HZ 80000000 */ - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */ -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 -#define CONFIG_RMII 1 /* use RMII interface */ - -#if defined(CONFIG_NETTA_ISDN) -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ -#define CONFIG_FEC1_PHY_NORXERR 1 -#undef CONFIG_ETHER_ON_FEC2 -#else -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ -#define CONFIG_FEC1_PHY_NORXERR 1 -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ -#define CONFIG_FEC2_PHY_NORXERR 1 -#endif - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CODEC | \ - CONFIG_SYS_POST_DSP ) - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 120000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 50000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 25000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 40000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 75000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif - -#elif CONFIG_XIN == 50000000 - -#if MPC8XX_HZ == 120000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 80000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 50000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 50MHz -#endif - -#else - -#error unsupported XIN freq -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3 and OR3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#if MPC8XX_HZ == 120000000 -#define CONFIG_SYS_MAMR_PTA 234 -#elif MPC8XX_HZ == 100000000 -#define CONFIG_SYS_MAMR_PTA 195 -#elif MPC8XX_HZ == 80000000 -#define CONFIG_SYS_MAMR_PTA 156 -#elif MPC8XX_HZ == 50000000 -#define CONFIG_SYS_MAMR_PTA 98 -#else -#error Unknown frequency -#endif - - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/*********************************************************************************************************** - - Pin definitions: - - +------+----------------+--------+------------------------------------------------------------ - | # | Name | Type | Comment - +------+----------------+--------+------------------------------------------------------------ - | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK - | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK) - | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA - | PA7 | DCL1_3V | Periph | IDL1 PCM clock - | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx - | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx - | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA - | PA12 | P_SHDN | Output | TPS2211A PCMCIA - | PA13 | ETH_LOOP | Output | CISCO Loopback remote power - | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL) - | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA - | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA - | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board - | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only) - | PB16 | DREQ1 | Output | D channel request for S-interface chip 1. - | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC - | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC - | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only) - | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom - | PB21 | LEDIO | Output | Led mode indication for PHY - | PB22 | UART_CTS | Input | UART CTS - | PB23 | UART_RTS | Output | UART RTS - | PB24 | UART_RX | Periph | UART Data Rx - | PB25 | UART_TX | Periph | UART Data Tx - | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock) - | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data) - | PB28 | SPI_RXD_3V | Input | SPI Data Rx - | PB29 | SPI_TXD | Output | SPI Data Tx - | PB30 | SPI_CLK | Output | SPI Clock - | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1 - | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt) - | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt) - | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt) - | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt) - | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK) - | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt) - | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt) - | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt) - | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt) - | PC13 | F_RY_BY | Input | NAND ready signal (interrupt) - | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK) - | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request. - | PD3 | F_ALE | Output | NAND - | PD4 | F_CLE | Output | NAND - | PD5 | F_CE | Output | NAND - | PD6 | DSP_INT | Output | DSP debug interrupt - | PD7 | DSP_RESET | Output | DSP reset - | PD8 | RMII_MDC | Periph | MII mgt clock - | PD9 | SPIEN_C1 | Output | SPI CS for codec #1 - | PD10 | SPIEN_C2 | Output | SPI CS for codec #2 - | PD11 | SPIEN_C3 | Output | SPI CS for codec #3 - | PD12 | FSC2 | Periph | IDL2 frame sync - | PD13 | DGRANT2 | Input | D channel grant from S #2 - | PD14 | SPIEN_C4 | Output | SPI CS for codec #4 - | PD15 | TP700 | Output | Testpoint for software debugging - | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data - | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data - | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for - | | DCL2 | Periph | NetRoute: PCM clock #2 - | PE17 | TP703 | Output | Testpoint for software debugging - | PE18 | DGRANT1 | Input | D channel grant from S #1 - | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable - | | PCM2OUT | Periph | NetRoute: Tx data for IDL2 - | PE20 | FSC1 | Periph | IDL1 frame sync - | PE21 | RMII2-RXD0 | Periph | FEC2 receive data - | PE22 | RMII2-RXD1 | Periph | FEC2 receive data - | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC - | PE24 | U-N1 | Output | Select user/network for S #1 (0=user) - | PE25 | U-N2 | Output | Select user/network for S #2 (0=user) - | PE26 | RMII2-RXDV | Periph | FEC2 valid - | PE27 | DREQ2 | Output | D channel request for S #2. - | PE28 | FPGA_DONE | Input | FPGA done signal - | PE29 | FPGA_INIT | Output | FPGA init signal - | PE30 | UDOUT2_3V | Input | IDL2 PCM input - | PE31 | | | Free - +------+----------------+--------+--------------------------------------------------- - - Chip selects: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | CS0 | CS0 | Boot flash - | CS1 | CS_FLASH | NAND flash - | CS2 | CS_DSP | DSP - | CS3 | DCS_DRAM | DRAM - | CS4 | CS_ER1 | External output register - +------+----------------+------------------------------------------------------------ - - Interrupts: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IRQ1 | UINTER_3V | S interrupt chips interrupt (common) - | IRQ3 | IRQ_DSP | DSP interrupt - | IRQ4 | IRQ_DSP1 | Extra DSP interrupt - +------+----------------+------------------------------------------------------------ - -*************************************************************************************************/ - -#define DSP_SIZE 0x00010000 /* 64K */ -#define NAND_SIZE 0x00010000 /* 64K */ -#define ER_SIZE 0x00010000 /* 64K */ -#define DUMMY_SIZE 0x00010000 /* 64K */ - -#define DSP_BASE 0xF1000000 -#define NAND_BASE 0xF1010000 -#define ER_BASE 0xF1020000 -#define DUMMY_BASE 0xF1FF0000 - -/*****************************************************************************/ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP -#define CONFIG_SYS_DIRECT_NAND_TFTP - -/*****************************************************************************/ - -#if 1 -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#endif - -/*************************************************************************************************/ - -#define CONFIG_CDP_DEVICE_ID 20 -#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */ -#define CONFIG_CDP_PORT_ID "eth%d" -#define CONFIG_CDP_CAPABILITIES 0x00000010 -#define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME -#define CONFIG_CDP_PLATFORM "Intracom NetTA" -#define CONFIG_CDP_TRIGGER 0x20020001 -#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ -#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */ - -/*************************************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 - -/*************************************************************************************************/ - -#define CONFIG_CRC32_VERIFY 1 - -/*************************************************************************************************/ - -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*************************************************************************************************/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h deleted file mode 100644 index 18ab2cca15..0000000000 --- a/include/configs/NETTA2.h +++ /dev/null @@ -1,657 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2 -#error Unsupported CONFIG_NETTA2 version -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ -#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -/* #define CONFIG_XIN 10000000 */ -#define CONFIG_XIN 50000000 -/* #define MPC8XX_HZ 120000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_SOURCE -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 -#define CONFIG_RMII 1 /* use RMII interface */ - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ -#define CONFIG_FEC1_PHY_NORXERR 1 - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 4 -#define CONFIG_FEC2_PHY_NORXERR 1 - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_CDP - - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#if CONFIG_NETTA2_VERSION == 2 -#define CONFIG_SYS_FLASH_BASE4 0x40080000 -#endif - -#define CONFIG_SYS_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#if CONFIG_NETTA2_VERSION == 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#elif CONFIG_NETTA2_VERSION == 2 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#endif -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) -#define CONFIG_ENV_OFFSET_REDUND 0 -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 120000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 50000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 25000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 40000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 75000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif - -#elif CONFIG_XIN == 50000000 - -#if MPC8XX_HZ == 120000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 50MHz -#endif - -#else - -#error unsupported XIN freq -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#if CONFIG_NETTA2_VERSION == 2 - -#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ - -#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#endif - -/* - * BR3 and OR3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define DSP_SIZE 0x00010000 /* 64K */ -#define NAND_SIZE 0x00010000 /* 64K */ - -#define DSP_BASE 0xF1000000 -#define NAND_BASE 0xF1010000 - -/*****************************************************************************/ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/*****************************************************************************/ - -#if CONFIG_NETTA2_VERSION == 1 -#define STATUS_LED_BIT 0x00000008 /* bit 28 */ -#elif CONFIG_NETTA2_VERSION == 2 -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ -#endif - -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \ - else \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/*********************************************************************************************************** - - ---------------------------------------------------------------------------------------------- - - (V1) version 1 of the board - (V2) version 2 of the board - - ---------------------------------------------------------------------------------------------- - - Pin definitions: - - +------+----------------+--------+------------------------------------------------------------ - | # | Name | Type | Comment - +------+----------------+--------+------------------------------------------------------------ - | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select - | PA7 | DSP_INT | Output | DSP interrupt - | PA10 | DSP_RESET | Output | DSP reset - | PA14 | USBOE | Output | USB (1) - | PA15 | USBRXD | Output | USB (1) - | PB19 | BT_RTS | Output | Bluetooth (0) - | PB23 | BT_CTS | Output | Bluetooth (0) - | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select - | PB27 | SPICS_DISP | Output | Display chip select - | PB28 | SPI_RXD_3V | Input | SPI Data Rx - | PB29 | SPI_TXD | Output | SPI Data Tx - | PB30 | SPI_CLK | Output | SPI Clock - | PC10 | DISPA0 | Output | Display A0 - | PC11 | BACKLIGHT | Output | Display backlit - | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD - | | IO_RESET | Output | (V2) General I/O reset - | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) - | | HOOK | Input | (V2) Hook input interrupt - | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK - | | F_RY_BY | Input | (V2) NAND F_RY_BY - | PE17 | F_ALE | Output | NAND F_ALE - | PE18 | F_CLE | Output | NAND F_CLE - | PE20 | F_CE | Output | NAND F_CE - | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select - | | LED | Output | (V2) LED - | PE27 | SPICS_ER | Output | External serial register CS - | PE28 | LEDIO1 | Output | (V1) LED - | | BKBR1 | Input | (V2) Keyboard input scan - | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) - | | BKBR2 | Input | (V2) Keyboard input scan - | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) - | | BKBR3 | Input | (V2) Keyboard input scan - | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY - | | BKBR4 | Input | (V2) Keyboard input scan - +------+----------------+--------+--------------------------------------------------- - - ---------------------------------------------------------------------------------------------- - - Serial register input: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | 4 | HOOK | Hook switch - | 5 | BT_LINK | Bluetooth link status - | 6 | HOST_WAKE | Bluetooth host wake up - | 7 | OK_ETH | Cisco inline power OK status - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Chip selects: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | CS0 | CS0 | Boot flash - | CS1 | CS_FLASH | NAND flash - | CS2 | CS_DSP | DSP - | CS3 | DCS_DRAM | DRAM - | CS4 | CS_FLASH2 | (V2) 2nd flash - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Interrupts: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IRQ1 | IRQ_DSP | DSP interrupt - | IRQ3 | S_INTER | DUSLIC ??? - | IRQ4 | F_RY_BY | NAND - | IRQ7 | IRQ_MAX | MAX 3100 interrupt - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Interrupts on PCMCIA pins: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface - | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface - | IP_A2| RMII1_MDINT | PHY interrupt for #1 - | IP_A3| RMII2_MDINT | PHY interrupt for #2 - | IP_A5| HOST_WAKE | (V2) Bluetooth host wake - | IP_A6| OK_ETH | (V2) Cisco inline power OK - +------+----------------+------------------------------------------------------------ - -**************************************************************************************************/ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 - -/*************************************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG - -/*************************************************************************************************/ - -#define CONFIG_CDP_DEVICE_ID 20 -#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */ -#define CONFIG_CDP_PORT_ID "eth%d" -#define CONFIG_CDP_CAPABILITIES 0x00000010 -#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME -#define CONFIG_CDP_PLATFORM "Intracom NetTA2" -#define CONFIG_CDP_TRIGGER 0x20020001 -#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ -#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */ - -/*************************************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 - -/*************************************************************************************************/ - -#define CONFIG_CRC32_VERIFY 1 - -/*************************************************************************************************/ - -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*************************************************************************************************/ -#endif /* __CONFIG_H */ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h deleted file mode 100644 index 0fd635dc27..0000000000 --- a/include/configs/NETVIA.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetVia board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_NETVIA 1 /* ...on a NetVia board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#else -#define CONFIG_8xx_CONS_NONE -#define CONFIG_MAX3100_SERIAL -#endif - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_XIN 10000000 -#define CONFIG_8xx_GCLK_FREQ 80000000 - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ -#endif - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -/* #define CONFIG_CMD_NAND */ /* disabled */ -#endif - - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -#define SCCR_MASK SCCR_EBDF11 - -#if CONFIG_8xx_GCLK_FREQ == 50000000 - -#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -#elif CONFIG_8xx_GCLK_FREQ == 80000000 - -#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) - -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3 and OR3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 208 - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* Ethernet at SCC2 */ -#define CONFIG_SCC2_ENET - -/****************************************************************/ - -#define DSP_SIZE 0x00010000 /* 64K */ -#define FPGA_SIZE 0x00010000 /* 64K */ - -#define DSP0_BASE 0xF1000000 -#define DSP1_BASE (DSP0_BASE + DSP_SIZE) -#define FPGA_BASE (DSP1_BASE + DSP_SIZE) - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -#define ER_SIZE 0x00010000 /* 64K */ -#define ER_BASE (FPGA_BASE + FPGA_SIZE) - -#define NAND_SIZE 0x00010000 /* 64K */ -#define NAND_BASE (ER_BASE + ER_SIZE) - -#endif - -/****************************************************************/ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -#define STATUS_LED_BIT 0x00000001 /* bit 31 */ -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_BIT1 0x00000002 /* bit 30 */ -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE1 STATUS_LED_OFF - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#endif - - -/*****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -/* LEDs */ - -/* last value written to the external register; we cannot read back */ -extern unsigned int last_er_val; - -/* led_id_t is unsigned long mask */ -typedef unsigned int led_id_t; - -static inline void __led_init(led_id_t mask, int state) -{ - unsigned int new_er_val; - - if (state) - new_er_val = last_er_val & ~mask; - else - new_er_val = last_er_val | mask; - - *(volatile unsigned int *)ER_BASE = new_er_val; - last_er_val = new_er_val; -} - -static inline void __led_toggle(led_id_t mask) -{ - unsigned int new_er_val; - - new_er_val = last_er_val ^ mask; - *(volatile unsigned int *)ER_BASE = new_er_val; - last_er_val = new_er_val; -} - -static inline void __led_set(led_id_t mask, int state) -{ - unsigned int new_er_val; - - if (state) - new_er_val = last_er_val & ~mask; - else - new_er_val = last_er_val | mask; - - *(volatile unsigned int *)ER_BASE = new_er_val; - last_er_val = new_er_val; -} - -/* MAX3100 console */ -#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define MAX3100_SPI_RXD_BIT 0x00000008 - -#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define MAX3100_SPI_TXD_BIT 0x00000004 - -#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define MAX3100_SPI_CLK_BIT 0x00000002 - -#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) -#define MAX3100_CS_BIT 0x0010 - -#endif - -#endif - -/*************************************************************************************************/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h deleted file mode 100644 index 46faa5d6e9..0000000000 --- a/include/configs/NSCU.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ -#define CONFIG_NSCU 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=NSCU\0" \ - "bootfile=${hostname}/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "u-boot=${hostname}/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history -*/ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -/* NSCU use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 - -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ -#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ -#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE buses */ -#define CONFIG_SYS_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */ - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -#ifdef CONFIG_ISP1362_USB -#define CONFIG_SYS_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ -#define CONFIG_SYS_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR5_ISP1362 (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \ - OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) -#define CONFIG_SYS_BR5_ISP1362 ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \ - BR_PS_16 | BR_MS_GPCM | BR_V ) -#endif /* CONFIG_ISP1362_USB */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#undef CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/NX823.h b/include/configs/NX823.h deleted file mode 100644 index 635f9ce1ed..0000000000 --- a/include/configs/NX823.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/*#define CONFIG_VIDEO 1 */ - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#define CONFIG_BOOTARGS "ramdisk_size=8000 "\ - "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\ - "nfsaddrs=10.77.77.20:10.77.77.250" -#define CONFIG_BOOTCOMMAND "bootm 400e0000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled, for now */ -#define CONFIG_SOURCE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_SOURCE - - -/* call various generic functions */ -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define xEMBED -#ifdef EMBED -#define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */ -#define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE -#else -#define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */ -#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ -#endif - -#define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */ -#define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */ -#define CONFIG_SYS_FLASH_SN_BYTES 8 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 12-30 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 12-16 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 12-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 12-23 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define MPC8XX_SPEED 66666666L -#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */ -#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) -#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) -#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 5-3 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_8_CLK ) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR1/2 and OR1/2 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM) - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* IO and memory mapped stuff */ -#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */ -#define NX823_IO_BASE 0xFF000000 /* start of IO */ -#define GPOUT_OFFSET (3<<16) -#define QUART_OFFSET (4<<16) -#define VIDAC_OFFSET (5<<16) -#define CPLD_OFFSET (6<<16) -#define SED1386_OFFSET (7<<16) - -/* - * BR3 and OR3 (general purpose output latches) - */ -#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET) -#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI) -#define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING) -#define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V) - -/* - * BR4 and OR4 (QUART) - */ -#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET) -#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX) -#define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI) -#define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V) - -/* - * BR5 and OR5 (Video DAC) - */ -#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET) -#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) -#define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI) -#define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V) - -/* - * BR6 and OR6 (CPLD) - * FIXME timing not verified for CPLD - */ -#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET) -#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) -#define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI) -#define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V ) - -/* - * BR7 and OR7 (SED1386) - * FIXME timing not verified for SED controller - */ -#define SED1386_BASE 0xF7000000 -#define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA) -#define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */ -#define CONFIG_ETHADDR 00:10:20:30:40:50 -#define CONFIG_IPADDR 10.77.77.20 -#define CONFIG_SERVERIP 10.77.77.250 - -#endif /* __CONFIG_H */ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h deleted file mode 100644 index c919613519..0000000000 --- a/include/configs/OCRTC.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_OCRTC 1 /* ...on a OCRTC board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "go fff00100" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ -#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (PLD - FPGA-boot) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (PLD - OSL) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (Spartan2 1) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 5 (Spartan2 2) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 6 (Virtex 1) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 7 (Virtex 2) initialization */ -#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ - - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h deleted file mode 100644 index 56d251cea5..0000000000 --- a/include/configs/ORSG.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_ORSG 1 /* ...on a ORSG board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "go fff00100" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ -#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (PLD - FPGA-boot) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (PLD - OSL) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (Spartan2 1) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 5 (Spartan2 2) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 6 (Virtex 1) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 7 (Virtex 2) initialization */ -#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ - - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ba3f7c2821..cd6a39c657 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -14,6 +14,8 @@ #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_P1010 #define CONFIG_E500 /* BOOKE e500 family */ @@ -21,23 +23,76 @@ #define CONFIG_NAND_FSL_IFC #ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #ifdef CONFIG_SPIFLASH +#ifdef CONFIG_SECURE_BOOT #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#else +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif +#endif #endif #ifdef CONFIG_NAND -#define CONFIG_SPL +#ifdef CONFIG_SECURE_BOOT #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -46,22 +101,61 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#else +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xD0001000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 8192 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#endif #endif - #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ #define CONFIG_RAMBOOT_NAND #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -77,8 +171,8 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #define CONFIG_PCI /* Enable PCI/PCIE */ @@ -120,7 +214,11 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#if defined(CONFIG_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" +#elif defined(CONFIG_P1010RDB_PB) +#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" +#endif #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 @@ -152,10 +250,7 @@ #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ -#ifndef CONFIG_SDCARD #define CONFIG_MISC_INIT_R -#endif - #define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. @@ -172,12 +267,12 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 @@ -203,25 +298,24 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 #define CONFIG_SYS_DDR_RCW_1 0x00000000 #define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401010 +#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644 +#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x40461520 -#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 /* settings for DDR3 at 667MT/s */ #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 @@ -256,10 +350,6 @@ extern unsigned long get_sdram_size(void); * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable */ -/* In case of SD card boot, IFC interface is not available because of muxing */ -#ifdef CONFIG_SDCARD -#define CONFIG_SYS_NO_FLASH -#else /* * IFC Definitions */ @@ -317,11 +407,20 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITION +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=ff800000.flash" +#define MTDPARTS_DEFAULT \ + "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" + #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#if defined(CONFIG_P1010RDB_PA) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -329,13 +428,26 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + +#elif defined(CONFIG_P1010RDB_PB) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) +#if defined(CONFIG_P1010RDB_PA) /* NAND Flash Timing Params */ #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ @@ -350,6 +462,23 @@ extern unsigned long get_sdram_size(void); FTIM2_NAND_TWHRE(0x0f) #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) +#elif defined(CONFIG_P1010RDB_PB) +/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 +#endif + #define CONFIG_SYS_NAND_DDR_LAW 11 /* Set up IFC registers for boot location NOR/NAND */ @@ -407,12 +536,12 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#endif /* CONFIG_SDCARD */ -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) +#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ + defined(CONFIG_RAMBOOT_NAND) #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #else @@ -420,8 +549,7 @@ extern unsigned long get_sdram_size(void); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ - && !defined(CONFIG_SECURE_BOOT) +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_A003399_NOR_WORKAROUND #endif #endif @@ -437,9 +565,46 @@ extern unsigned long get_sdram_size(void); - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ +/* + * Config the L2 Cache as L2 SRAM + */ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#endif +#endif + /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO @@ -447,7 +612,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -482,9 +647,21 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define I2C_PCA9557_ADDR1 0x18 +#define I2C_PCA9557_ADDR2 0x19 +#define I2C_PCA9557_BUS_NUM 0 /* I2C EEPROM */ -#undef CONFIG_ID_EEPROM +#if defined(CONFIG_P1010RDB_PB) +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ +#endif /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_MULTI_EEPROMS @@ -567,12 +744,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_LBA48 #endif /* #ifdef CONFIG_FSL_SATA */ -/* SD interface will only be available in case of SD boot */ -#ifdef CONFIG_SDCARD #define CONFIG_MMC -#define CONFIG_DEF_HWCONFIG esdhc -#endif - #ifdef CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION @@ -597,12 +769,12 @@ extern unsigned long get_sdram_size(void); /* * Environment */ -#if defined(CONFIG_RAMBOOT_SDCARD) +#if defined(CONFIG_SDCARD) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#elif defined(CONFIG_SPIFLASH) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 @@ -613,20 +785,26 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else +#if defined(CONFIG_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ +#elif defined(CONFIG_P1010RDB_PB) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ +#endif +#endif +#define CONFIG_ENV_OFFSET (1024 * 1024) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif @@ -657,6 +835,12 @@ extern unsigned long get_sdram_size(void); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -664,7 +848,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -675,7 +858,6 @@ extern unsigned long get_sdram_size(void); /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ /* * Internal Definitions @@ -695,7 +877,6 @@ extern unsigned long get_sdram_size(void); #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -708,7 +889,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_HAS_ETH2 #endif -#define CONFIG_HOSTNAME P1010RDB #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ @@ -747,7 +927,31 @@ extern unsigned long get_sdram_size(void); "ext2load usb 0:4 $loadaddr $bootfile;" \ "ext2load usb 0:4 $fdtaddr $fdtfile;" \ "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + CONFIG_BOOTMODE + +#if defined(CONFIG_P1010RDB_PA) +#define CONFIG_BOOTMODE \ + "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ + "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ + "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" + +#elif defined(CONFIG_P1010RDB_PB) +#define CONFIG_BOOTMODE \ + "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ + "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ + "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ + "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ + "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ + "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ + "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ + "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ + "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ + "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" +#endif #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ @@ -759,8 +963,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index d1ce9fdc8d..437111070d 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -11,59 +11,122 @@ #include "../board/freescale/common/ics307_clk.h" +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif #ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #define CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 +#define CONFIG_SYS_NAND_MAX_OOBFREE 5 #ifdef CONFIG_NAND -#define CONFIG_SPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SYS_TEXT_BASE 0x00201000 -#define CONFIG_SPL_TEXT_BASE 0xfffff000 -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 4096 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ #define CONFIG_P1022 #define CONFIG_P1022DS #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -114,7 +177,7 @@ /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER @@ -225,11 +288,11 @@ #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE /* NAND flash config */ @@ -288,9 +351,46 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +/* + * Config the L2 Cache as L2 SRAM +*/ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#endif +#endif + /* * Serial Port */ @@ -299,7 +399,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -518,10 +618,29 @@ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fe8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=e8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" +#endif + /* * Environment */ -#ifdef CONFIG_RAMBOOT_SPIFLASH +#ifdef CONFIG_SPIFLASH #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 @@ -530,14 +649,20 @@ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_RAMBOOT_SDCARD) +#elif defined(CONFIG_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_NAND) -#define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (1024 * 1024) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ @@ -545,11 +670,7 @@ #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif @@ -599,7 +720,6 @@ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -609,7 +729,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* * For booting Linux, the board info and command line data @@ -621,7 +740,6 @@ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index cd6d20c729..a8b7817a8e 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -10,8 +10,11 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_SYS_MONITOR_BASE @@ -25,7 +28,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_P1023 #define CONFIG_MP /* support multiple processors */ @@ -74,7 +76,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -126,7 +128,7 @@ extern unsigned long get_clock_freq(void); GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ #define CONFIG_SYS_NAND_BASE 0xffa00000 @@ -260,11 +262,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ @@ -312,7 +310,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -323,7 +320,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -351,9 +347,25 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 /* For FM */ #define CONFIG_SYS_DPAA_FMAN @@ -367,7 +379,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -381,6 +393,49 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "loadaddr=1000000\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off $ubootaddr +$filesize; " \ + "erase $ubootaddr +$filesize; " \ + "cp.b $loadaddr $ubootaddr $filesize; " \ + "protect on $ubootaddr +$filesize; " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p1023rdb.dtb\0" \ + "othbootargs=ramdisk_size=600000\0" \ + "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + #endif /* __CONFIG_H */ diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h deleted file mode 100644 index a8202c67fd..0000000000 --- a/include/configs/P1023RDS.h +++ /dev/null @@ -1,532 +0,0 @@ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * - * Authors: Roy Zang - * Chunhe Lan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * p1023rds board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_NAND -#define CONFIG_NAND_U_BOOT -#define CONFIG_RAMBOOT_NAND -#endif - -#ifdef CONFIG_NAND_U_BOOT -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 -#define CONFIG_SYS_TEXT_BASE 0x11001000 - -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ -#else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif /* CONFIG_NAND_SPL */ -#endif - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx -#define CONFIG_P1023 -#define CONFIG_P1023RDS -#define CONFIG_MP /* support multiple processors */ - -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif - -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_HWCONFIG - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */ -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of - addresses in the LBC */ - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */ - -/* Default settings for "stable" mode */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x40110104 -#define CONFIG_SYS_DDR_TIMING_1 0x5C59E544 -#define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA -#define CONFIG_SYS_DDR_MODE_1 0x00441210 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x0A280100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x01800000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x01401400 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */ -#define CONFIG_SYS_DDR_CONTROL2 0x24401010 -#define CONFIG_SYS_DDR_CDR1 0x00000000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00000000 - -/* Settings that differ for "performance" mode */ -#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ -#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ -#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302 -#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544 -#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA -/* Type = DDR3: cs0-cs1 interleaving */ -#define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008 -#define CONFIG_SYS_DDR_CDR_1 0x00000000 -#define CONFIG_SYS_DDR_CDR_2 0x00000000 - - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe003_ffff BCSR 256K BCSR - * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash - * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M - * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */ -#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE - -#ifndef CONFIG_NAND -#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */ - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#else -#define CONFIG_SYS_NO_FLASH -#endif - -#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ - -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#else -#define CONFIG_SYS_NAND_BASE 0xfff00000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ - -#define CONFIG_BAUDRATE 115200 - -/* Qman/Bman */ -#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ -#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 - -/* For FM */ -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET -#define CONFIG_PHY_MARVELL -#endif - -#ifndef CONFIG_NAND -/* Default address of microcode for the Linux Fman driver */ -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 -#else -#define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7 - -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h deleted file mode 100644 index adaed564f7..0000000000 --- a/include/configs/P1_P2_RDB.h +++ /dev/null @@ -1,719 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * P1 P2 RDB board configuration file - * This file is intended to address a set of Low End and Ultra Low End - * Freescale SOCs of QorIQ series(RDB platforms). - * Currently only P2020RDB - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - -#ifdef CONFIG_P1011RDB -#define CONFIG_P1011 -#endif -#ifdef CONFIG_P1020RDB -#define CONFIG_P1020 -#endif -#ifdef CONFIG_P2010RDB -#define CONFIG_P2010 -#endif -#ifdef CONFIG_P2020RDB -#define CONFIG_P2020 -#endif - -#ifdef CONFIG_NAND -#define CONFIG_NAND_U_BOOT 1 -#define CONFIG_RAMBOOT_NAND 1 -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ -#else -#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -#define CONFIG_SYS_TEXT_BASE 0xf8f82000 -#endif /* CONFIG_NAND_SPL */ -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#endif - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ -#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ - -#define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif /* #if defined(CONFIG_PCI) */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_PCI) -#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ -#endif - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */ -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */ - -#if defined(CONFIG_P2020) || defined(CONFIG_P1020) -#define CONFIG_MP -#endif - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - - /* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -#if defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_FSL_DDR2 -#undef CONFIG_FSL_DDR_INTERACTIVE -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00FF0000 - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xff000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ - defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_MISC_INIT_R -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#else -#define CONFIG_SYS_NAND_BASE 0xfff00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#endif - -#define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< 0xfff80000 - #define CONFIG_ENV_ADDR 0xfff80000 - #else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #endif - #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_MMC 1 - -#ifdef CONFIG_MMC -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_FSL_ESDHC -#define CONFIG_GENERIC_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#ifdef CONFIG_P2020 -#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/ -#endif -#endif - -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#endif -#endif - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_HOSTNAME P2020RDB -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=p2020rdb.dtb\0" \ - "bdev=sda1\0" \ - "jffs2nor=mtdblock3\0" \ - "norbootaddr=ef080000\0" \ - "norfdtaddr=ef040000\0" \ - "jffs2nand=mtdblock9\0" \ - "nandbootaddr=100000\0" \ - "nandfdtaddr=80000\0" \ - "nandimgsize=400000\0" \ - "nandfdtsize=80000\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ - "vscfw_addr=ef000000\0" \ - "othbootargs=ramdisk_size=600000\0" \ - "usbfatboot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "fatload usb 0:2 $loadaddr $bootfile;" \ - "fatload usb 0:2 $fdtaddr $fdtfile;" \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "norboot=setenv bootargs root=/dev/$jffs2nor rw " \ - "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ - "bootm $norbootaddr - $norfdtaddr\0" \ - "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "nand read 2000000 $nandbootaddr $nandimgsize;" \ - "nand read 3000000 $nandfdtaddr $nandfdtsize;" \ - "bootm 2000000 - 3000000;\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h deleted file mode 100644 index 08d1c25914..0000000000 --- a/include/configs/P2020COME.h +++ /dev/null @@ -1,551 +0,0 @@ -/* - * Copyright 2009-2010,2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* The P2020COME board is only booted via the Freescale On-Chip ROM */ -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC - -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD 1 -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH 1 -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ -#define CONFIG_P2020 1 -#define CONFIG_P2020COME 1 -#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ -#define CONFIG_MP - -#define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */ - -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif /* #if defined(CONFIG_PCI) */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_PCI) -#define CONFIG_E1000 1 /* E1000 pci Ethernet card */ -#endif - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_ddr_clk(unsigned long dummy); -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif - -/* - * For P2020COME DDRCLK and SYSCLK are from the same oscillator - * For DA phase the SYSCLK is 66MHz - * For EA phase the SYSCLK is 100MHz - */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch prediction */ - -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - - /* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \ - + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_FSL_DDR3 -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - -#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00ff0000 - -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS 0x53 - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable - * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable - * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable - * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable - * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable - * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable - * - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ - -/* There is no NOR Flash on P2020COME */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* the assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Pass open firmware flat tree - */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* new uImage format support */ -#define CONFIG_FIT 1 -#define CONFIG_FIT_VERBOSE 1 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } - -/* - * I2C2 EEPROM - */ -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#if defined(CONFIG_PCI) - -/* controller 3, Slot 3, tgtid 3, Base address 8000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP -#undef CONFIG_RTL8139 - -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 2 -#define TSEC3_PHY_ADDR 1 - -#undef CONFIG_VSC7385_ENET - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#if defined(CONFIG_RAMBOOT_SDCARD) - #define CONFIG_ENV_IS_IN_MMC 1 - #define CONFIG_FSL_FIXED_MMC_LOCATION - #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_RAMBOOT_SPIFLASH) - #define CONFIG_ENV_IS_IN_SPI_FLASH - #define CONFIG_ENV_SPI_BUS 0 - #define CONFIG_ENV_SPI_CS 0 - #define CONFIG_ENV_SPI_MAX_HZ 10000000 - #define CONFIG_ENV_SPI_MODE 0 - #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ - #define CONFIG_ENV_SECT_SIZE 0x10000 - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_MMC 1 - -#ifdef CONFIG_MMC -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_FSL_ESDHC -#define CONFIG_GENERIC_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#endif /* CONFIG_MMC */ - -#define CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#endif -#endif - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* Misc Extra Settings */ -#define CONFIG_CMD_DHCP 1 - -#define CONFIG_CMD_DATE 1 -#define CONFIG_RTC_M41T62 1 -#define CONFIG_SYS_RTC_BUS_NUM 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ecc=on\0" \ - "bootcmd=run sdboot\0" \ - "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \ - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ - "$othbootargs; mmcinfo; " \ - "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \ - "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \ - "bootm $loadaddr - $fdtaddr\0" \ - "sdfatboot=setenv bootargs root=/dev/ram rw " \ - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ - "$othbootargs; mmcinfo; " \ - "fatload mmc 0:1 $loadaddr $bootfile; " \ - "fatload mmc 0:1 $fdtaddr $fdtfile; " \ - "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "usbboot=setenv bootargs root=/dev/sda1 rw " \ - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ - "$othbootargs; " \ - "usb start; " \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \ - "bootm $loadaddr - $fdtaddr\0" \ - "usbfatboot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start; " \ - "fatload usb 0:2 $loadaddr $bootfile; " \ - "fatload usb 0:2 $fdtaddr $fdtfile; " \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start; " \ - "ext2load usb 0:4 $loadaddr $bootfile; " \ - "ext2load usb 0:4 $fdtaddr $fdtfile; " \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "upgradespi=sf probe 0; " \ - "setenv startaddr 0; " \ - "setenv erasesize a0000; " \ - "tftp 1000000 $tftppath/$uboot_spi; " \ - "sf erase $startaddr $erasesize; " \ - "sf write 1000000 $startaddr $filesize; " \ - "sf erase 100000 120000\0" \ - "clearspienv=sf probe 0;sf erase 100000 20000\0" \ - "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \ - "netdev=eth0\0" \ - "rootdelaysecond=15\0" \ - "uboot_nor=u-boot-nor.bin\0" \ - "uboot_spi=u-boot-p2020.spi\0" \ - "uboot_sd=u-boot-p2020.bin\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs-dev.ext2.img\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=uImage-2.6.32-p2020.dtb\0" \ - "tftppath=p2020\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $tftppath/$bootfile;" \ - "tftp $fdtaddr $tftppath/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \ - "tftp $loadaddr $tftppath/$bootfile;" \ - "tftp $fdtaddr $tftppath/$fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h deleted file mode 100644 index b5078cdb52..0000000000 --- a/include/configs/P2020DS.h +++ /dev/null @@ -1,758 +0,0 @@ -/* - * Copyright 2007-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * p2020ds board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ -#define CONFIG_P2020 1 -#define CONFIG_P2020DS 1 -#define CONFIG_MP 1 /* support multiple processors */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - -#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ -#define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - -/* - * Config the L2 Cache - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM -#ifdef CONFIG_DDR2 -#define CONFIG_FSL_DDR2 -#else -#define CONFIG_FSL_DDR3 1 -#endif - -/* ECC will be enabled based on perf_mode environment variable */ -/* #define CONFIG_DDR_ECC */ - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ - -/* Default settings for "stable" mode */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330804 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 -#define CONFIG_SYS_DDR_MODE_1 0x00421422 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x61800100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 -#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ -#define CONFIG_SYS_DDR_CONTROL2 0x24400011 -#define CONFIG_SYS_DDR_CDR1 0x00040000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 - -/* Settings that differ for "performance" mode */ -#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ -#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ -#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 -#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 -#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce -#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ - -/* - * The following set of values were tested for DDR2 - * with a DDR3 to DDR2 interposer - * -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 -#define CONFIG_SYS_DDR_MODE_1 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x06180100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3008000 -#define CONFIG_SYS_DDR_CONTROL2 0x04400010 - * - */ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ - -#define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#ifdef CONFIG_FSL_NGPIXIS -#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ -#ifdef CONFIG_PHYS_64BIT -#define PIXIS_BASE_PHYS 0xfffdf0000ull -#else -#define PIXIS_BASE_PHYS PIXIS_BASE -#endif - -#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ - -#define PIXIS_LBMAP_SWITCH 7 -#define PIXIS_LBMAP_MASK 0xf0 -#define PIXIS_LBMAP_SHIFT 4 -#define PIXIS_LBMAP_ALTBANK 0x20 -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ - CONFIG_SYS_NAND_BASE + 0x40000, \ - CONFIG_SYS_NAND_BASE + 0x80000,\ - CONFIG_SYS_NAND_BASE + 0xC0000} -#define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET -#define CONFIG_CMD_SCSI -#define CONFIG_CMD_EXT2 -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -/* - * SDHC/MMC - */ -#define CONFIG_MMC - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#endif - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_IPADDR 192.168.1.254 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"perf_mode=performance\0" \ - "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=ulpi\0" \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ -"satabootcmd=setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=p2020ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ -"othbootargs=cache-sram-size=0x10000\0" \ -"fdtfile=p2020ds/p2020ds.dtb\0" \ -"bdev=sda3\0" \ -"partition=scsi 0:0\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load $partition $loadaddr $bootfile;" \ - "ext2load $partition $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 9814ca2012..d8d30bb280 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -13,13 +13,15 @@ #define CONFIG_P2041RDB #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_PPC_P2041 #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -36,12 +38,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -51,6 +51,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ @@ -94,12 +95,12 @@ #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_OFFSET (512 * 1097) + #define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -176,7 +177,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 @@ -317,7 +318,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Serial Port - controlled on board with jumper J8 @@ -355,10 +356,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 /* * RapidIO @@ -383,15 +384,15 @@ unsigned long get_board_sys_clk(unsigned long dummy); * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ @@ -490,6 +491,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 #ifdef CONFIG_PHYS_64BIT @@ -498,6 +507,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME @@ -508,18 +525,18 @@ unsigned long get_board_sys_clk(unsigned long dummy); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -529,10 +546,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -649,6 +666,12 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -656,7 +679,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -668,7 +690,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -680,7 +701,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -718,8 +738,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ "fdtfile=p2041rdb/p2041rdb.dtb\0" \ - "bdev=sda3\0" \ - "c=ffe\0" + "bdev=sda3\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ @@ -747,8 +766,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h deleted file mode 100644 index 6328ba9bf4..0000000000 --- a/include/configs/P3G4.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -#include -#endif - -#include "../board/evb64260/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_P3G4 1 /* this is a P3G4 board */ -#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ - -#undef CONFIG_ECC /* enable ECC support */ -/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CONFIG_SYS_BOARD_NAME "P3G4" - -#undef CONFIG_SYS_HUSH_PARSER - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3g4\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_74xx\0" \ - "bootfile=/tftpboot/p3g4/uImage\0" \ - "kernel_addr=ff000000\0" \ - "ramdisk_addr=ff010000\0" \ - "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_UNIVERSE -#define CONFIG_CMD_BSP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 1 -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CONFIG_SYS_GT_REGS 0xf8000000 -#define CONFIG_SYS_DEV_BASE 0xff000000 - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) - -#define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */ -#define CONFIG_SYS_DEV1_SIZE 0 /* unused */ -#define CONFIG_SYS_DEV2_SIZE 0 /* unused */ -#define CONFIG_SYS_DEV3_SIZE 0 /* unused */ - -#define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c -#define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR - -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ - /* DMAAck[1:0] GNT0[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ - /* REQ0[1:0] GNT0[1:0] */ -#endif -#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ - /* DMAReq[4] DMAAck[4] WDNMI WDE */ -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ - /* DMAAck[1:0] GNT1[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ - /* GPP[22] (RS232IntB or PCI1Int) */ - /* GPP[21] (RS323IntA) */ - /* BClkIn */ - /* REQ1[1:0] GNT1[1:0] */ -#endif - -#if 0 /* Wrong?? NTL */ -# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ - /* GPP[27:26] Int[1:0] */ -#else -# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ -#endif - -#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ - -#if 0 /* Wrong?? - NTL */ -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6 -#else -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ - /* gpp[27:26] */ - /* gpp[22:21] */ - -# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 0 - pci use buffer 1,1 - cpu use buffer 0 - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 110110 00 111 0 0 00 1 */ - /* refresh_count=0x200 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ -#endif - -#if 0 -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#endif -#undef CONFIG_SYS_INIT_CHAN1 -#undef CONFIG_SYS_INIT_CHAN2 -#if 0 -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ -#endif - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) - -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C speed and slave address (for compatability) defaults */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* I2C addresses for the two DIMM SPD chips */ -#ifndef CONFIG_EVB64260_750CX -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 -#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ -#define DIMM0_I2C_ADDR 0x54 -#define DIMM1_I2C_ADDR 0x54 -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR 0xFFFE0000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index b0cd7d5c21..2f8900834d 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -17,6 +17,12 @@ #define CONFIG_MMC #define CONFIG_PCIE3 +#define CONFIG_CMD_SATA +#define CONFIG_SATA_SIL +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LIBATA +#define CONFIG_LBA48 + #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index 371485fec0..e4a031aefa 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -17,6 +17,7 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC #define CONFIG_PCIE3 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 732fe64d4e..3ca204e1e2 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 +#define CONFIG_SYS_GENERIC_BOARD + /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 #undef CONFIG_5xx_CONS_SCI2 @@ -94,10 +96,9 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ - #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } +#define CONFIG_BOARD_EARLY_INIT_F /*********************************************************************** * Last Stage Init diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h deleted file mode 100644 index a71a5219cf..0000000000 --- a/include/configs/PCI405.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com - * - * (C) Copyright 2001-2004 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PCI405 1 /* ...on a PCI405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mem_linux=14336k\0" \ - "optargs=panic=0\0" \ - "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ - "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ - "" -#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci" - -#define CONFIG_PREBOOT /* enable preboot variable */ - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_ITEST -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ - -#define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */ -#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ - /* total size of a CAT24WC08 is 1024 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -/*#define CONFIG_SYS_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (FPGA internal) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */ -#define CONFIG_SYS_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h deleted file mode 100644 index 84ef49c9c5..0000000000 --- a/include/configs/PCI5441.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_PCI5441 1 /* PCI-5441 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x00920828 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128k */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ -#define CONFIG_SYS_LOW_RES_TIMER -#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 2251ca6116..9a1b2acac3 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -17,11 +17,12 @@ * (easy to change) ***********************************************************/ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PIP405 1 /* ...on a PIP405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_SYS_GENERIC_BOARD + /*********************************************************** * Clock ***********************************************************/ @@ -143,7 +144,6 @@ * Miscellaneous configurable options **********************************************************/ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -173,8 +173,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -356,7 +354,6 @@ ************************************************************/ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /************************************************************ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h deleted file mode 100644 index 115c89a36b..0000000000 --- a/include/configs/PK1C20.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_PK1C20 1 /* PK1C20 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for - * epcs device access is enabled. The base address is the epcs - * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. - * The register base is currently at offset 0x600 from the memory base. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ -#define CONFIG_SYS_LOW_RES_TIMER -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- leds are, after all, - * board-specific, no? - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ -#define CONFIG_BOARD_SPECIFIC_LED - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - - -/*------------------------------------------------------------------------ - * COMPACT FLASH - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_IDE) -#define CONFIG_IDE_PREINIT /* Implement id_preinit */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */ -#define CONFIG_DOS_PARTITION - -/* Board-specific cf regs */ -#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base */ -#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO base*/ -#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ - -#endif - -/*------------------------------------------------------------------------ - * JFFS2 - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_JFFS2) -#define CONFIG_SYS_JFFS_CUSTOM_PART /* board defined part */ -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#define CONFIG_SYS_HUSH_PARSER - -#endif /* __CONFIG_H */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 3c31cfb01a..a236e117a0 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -2,7 +2,7 @@ * (C) Copyright 2001-2003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,10 +18,11 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PLU405 1 /* ...on a PLU405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -95,7 +96,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ @@ -134,8 +134,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ diff --git a/include/configs/PM520.h b/include/configs/PM520.h deleted file mode 100644 index 7ab1d84773..0000000000 --- a/include/configs/PM520.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_PM520 1 /* ... on PM520 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#undef CONFIG_NS8382X - - -/* Partitions */ -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 1 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#define CONFIG_CMD_PCI - - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=pm520\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk30/ppc_82xx\0" \ - "bootfile=/tftpboot/PM520/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -#define CONFIG_SYS_DOC_BASE 0xE0000000 -#define CONFIG_SYS_DOC_SIZE 0x00100000 - -#if defined(CONFIG_BOOT_ROM) -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFA000000 for 64 MB - * 0xFC000000 for 32 MB - * 0xFD000000 for 16 MB - * 0xFD800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0xFA000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 -#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000 -#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 -#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000) -#else -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0xFC000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 -#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000) -#endif -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ - -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */ - - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_CFG 0x0004FF00 -#else -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE -#define CONFIG_SYS_CS1_CFG 0x00047800 -#endif - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#undef CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM826.h b/include/configs/PM826.h deleted file mode 100644 index b466513ea3..0000000000 --- a/include/configs/PM826.h +++ /dev/null @@ -1,538 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CONFIG_SYS_RAMBOOT - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_PM826 1 /* ...on a PM8260 module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */ -#endif - -#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if CONFIG_ETHER_ON_SCC is selected, then - * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) - * - * if CONFIG_ETHER_ON_FCC is selected, then - * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK10 - */ -#define CONFIG_ETHER_ON_FCC1 -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -#ifndef CONFIG_DB_CR826_J30x_ON -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) -#else -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -#endif -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - */ -#define CONFIG_ETHER_ON_FCC2 -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -/* - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 64000000 /* in Hz */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_CMD_PCI -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash and Boot ROM mapping - */ -#ifdef CONFIG_FLASH_32MB -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 0x02000000 -#else -#define CONFIG_SYS_FLASH0_BASE 0xFF000000 -#define CONFIG_SYS_FLASH0_SIZE 0x00800000 -#endif -#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 -#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 -#define CONFIG_SYS_DOC_BASE 0xFF800000 -#define CONFIG_SYS_DOC_SIZE 0x00100000 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#ifdef CONFIG_FLASH_32MB -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ -#else -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#endif -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_ENV_OFFSET 512 -#define CONFIG_ENV_SIZE (2048 - 512) -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ - -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG00) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 - -/* - * we use the same values for 32 MB and 128 MB SDRAM - * refresh rate = 7.73 uS (64 MHz Bus Clock) - */ -#define CONFIG_SYS_MPTPR 0x2000 -#define CONFIG_SYS_PSRT 0x0E - -#define CONFIG_SYS_MRS_OFFS 0x00000000 - - -#if defined(CONFIG_BOOT_ROM) -/* - * Bank 0 - Boot ROM (8 bit wide) - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Flash (64 bit wide) - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#else /* ! CONFIG_BOOT_ROM */ - -/* - * Bank 0 - Flash (64 bit wide) - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Disk-On-Chip - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#endif /* CONFIG_BOOT_ROM */ - -/* Bank 2 - SDRAM - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL -#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h deleted file mode 100644 index cb68c41bab..0000000000 --- a/include/configs/PM828.h +++ /dev/null @@ -1,532 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CONFIG_SYS_RAMBOOT - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_PM828 1 /* ...on a PM828 module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x40000000 /* Standard: boot 64-bit flash */ -#endif - -#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if CONFIG_ETHER_ON_SCC is selected, then - * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) - * - * if CONFIG_ETHER_ON_FCC is selected, then - * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK10 - */ -#define CONFIG_ETHER_ON_FCC1 -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -#ifndef CONFIG_DB_CR826_J30x_ON -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) -#else -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -#endif -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - */ -#define CONFIG_ETHER_ON_FCC2 -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -/* - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_CMD_PCI -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash and Boot ROM mapping - */ - -#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 -#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 0x02000000 -#define CONFIG_SYS_DOC_BASE 0xFF800000 -#define CONFIG_SYS_DOC_SIZE 0x00100000 - - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_ENV_OFFSET 512 -#define CONFIG_ENV_SIZE (2048 - 512) -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ - -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG00) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 - -/* - * we use the same values for 32 MB and 128 MB SDRAM - * refresh rate = 7.68 uS (100 MHz Bus Clock) - */ -#define CONFIG_SYS_MPTPR 0x2000 -#define CONFIG_SYS_PSRT 0x16 - -#define CONFIG_SYS_MRS_OFFS 0x00000000 - - -#if defined(CONFIG_BOOT_ROM) -/* - * Bank 0 - Boot ROM (8 bit wide) - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Flash (64 bit wide) - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#else /* ! CONFIG_BOOT_ROM */ - -/* - * Bank 0 - Flash (64 bit wide) - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Disk-On-Chip - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#endif /* CONFIG_BOOT_ROM */ - -/* Bank 2 - SDRAM - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL -#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h deleted file mode 100644 index 67a96d29d4..0000000000 --- a/include/configs/PMC405.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PMC405 1 /* ...on a PMC405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -/* Only interrupt boot if space is pressed. */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_UNIVERSE -#define CONFIG_CMD_EEPROM - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */ -#define CONFIG_SYS_BASE_BAUD 806400 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 - -/* - * PCI stuff - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() - -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */ - -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */ -#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */ - -#define CONFIG_PRAM 0 /* use pram variable to overwrite */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}} -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT} -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */ - -/* - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ - -/* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_OFFSET 0x000 -#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/* - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Addres */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ -#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000) - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ -#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000) - -/* Memory Bank 2 (CAN0, 1, RTC) initialization */ -/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CONFIG_SYS_EBC_PB2AP 0x03000440 -/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000) - -/* Memory Bank 3 -> unused */ - -/* Memory Bank 4 (NVRAM) initialization */ -/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CONFIG_SYS_EBC_PB4AP 0x03000440 -/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000) - -/* - * FPGA stuff - */ -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */ - -/* pass Ethernet MAC to VxWorks */ -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 - -/* - * GPIOs - */ -#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */ -#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */ -#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */ -#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ -#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */ -#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */ - -/* - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory (OCM) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR - -/* End of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -#endif /* __CONFIG_H */ diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 531e95612a..f7d28e39dd 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -2,17 +2,18 @@ * (C) Copyright 2009 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -79,7 +80,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) @@ -104,8 +104,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index a54c099ce4..c29429d368 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -24,12 +24,14 @@ *----------------------------------------------------------------------*/ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF90000 #endif +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_SYS_CLK_FREQ 33333400 #if 0 /* temporary disabled because OS/9 does not like dcache on startup */ @@ -96,12 +98,7 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * RTC @@ -139,73 +136,15 @@ #endif #ifdef CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_I2C_ENV_EEPROM_BUS 0 #define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */ #define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ #endif -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#if defined (CONFIG_NAND_U_BOOT) -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} -#endif - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ -#endif #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ /* 440EPx errata CHIP 11 */ @@ -372,7 +311,6 @@ * Miscellaneous configurable options *----------------------------------------------------------------------*/ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -388,8 +326,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ @@ -452,7 +388,6 @@ /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ @@ -462,16 +397,6 @@ /* Memory Bank 2 (NAND-FLASH) initialization */ #define CONFIG_SYS_EBC_PB2AP 0x018003c0 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000) -#else -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 2 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x03017200 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000) - -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) -#endif /* Memory Bank 1 (RESET) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */ @@ -495,7 +420,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* pass open firmware flat tree */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h deleted file mode 100644 index fbf8a996ce..0000000000 --- a/include/configs/PN62.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_PN62 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_BSP - -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_SOURCE - - -#define CONFIG_BAUDRATE 19200 /* console baudrate */ - -#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_SERVERIP 10.0.0.201 -#define CONFIG_IPADDR 10.0.0.200 -#define CONFIG_ROOTPATH "/opt/eldk/ppc_82xx" -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_BOOTARGS -#if 0 -/* Boot Linux with NFS root filesystem */ -#define CONFIG_BOOTCOMMAND \ - "setenv verify y;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ - "loadp 100000; bootm" - /* "tftpboot 100000 uImage; bootm" */ -#else -/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ -#define CONFIG_BOOTCOMMAND \ - "setenv verify n;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/ram rw " \ - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ - "loadp 200000; bootm" -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */ - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* we need Plug 'n Play */ -#if 0 -#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */ -#endif - -/* - * Networking stuff - */ - -#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ -#define CONFIG_PCNET_79C973 - -#define _IO_BASE 0xfe000000 /* points to PCI I/O space */ - - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */ - -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */ - -/* - * Serial port configuration - */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 1843200 - -#define CONFIG_SYS_NS16550_COM1 0xff800008 -#define CONFIG_SYS_NS16550_COM2 0xff800000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 - -#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 - -/* MCCR1 */ -#define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */ - -/* MCCR2 */ -#define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */ -#define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */ -#define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */ - -/* MCCR3 */ -#define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 3 /* data latency from read command */ - -/* MCCR4 */ -#define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings: - * - * only bits 20-29 are actually used from these vales to set the - * start/qend address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x00000000 -#define CONFIG_SYS_BANK1_END 0x00000000 -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x00000000 -#define CONFIG_SYS_BANK2_END 0x00000000 -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x00000000 -#define CONFIG_SYS_BANK3_END 0x00000000 -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 - -/* - * Memory bank enable bitmask, specifying which of the banks defined above - * are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory space */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h deleted file mode 100644 index cd9eb4b10b..0000000000 --- a/include/configs/PPChameleonEVB.h +++ /dev/null @@ -1,781 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2003 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Credits: Stefan Roese, Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ -#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ -#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ -#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL -#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA -#endif - - -/* Only one of the following two symbols must be defined (default is 25 MHz) - * CONFIG_PPCHAMELEON_CLK_25 - * CONFIG_PPCHAMELEON_CLK_33 - */ -#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_PPCHAMELEON_CLK_25 -#endif - -#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) -#error "* Two external frequencies (SysClk) are defined! *" -#endif - -#undef CONFIG_PPCHAMELEON_SMI712 - -/* - * Debug stuff - */ -#undef __DEBUG_START_FROM_SRAM__ -#define __DISABLE_MACHINE_EXCEPTION__ - -#ifdef __DEBUG_START_FROM_SRAM__ -#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#else -# error "* External frequency (SysClk) not defined! *" -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_BOOTARGS - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:c2:1e:af:fe -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_EXT_PHY - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ -#else -#define CONFIG_PHY_ADDR 2 /* PHY address */ -#endif -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 - -/* - * SDRAM configuration (please see cpu/ppc/sdram.[ch]) - */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* SDRAM timings used in datasheet */ -#define CONFIG_SYS_SDRAM_CL 2 -#define CONFIG_SYS_SDRAM_tRP 20 -#define CONFIG_SYS_SDRAM_tRC 65 -#define CONFIG_SYS_SDRAM_tRCD 20 -#undef CONFIG_SYS_SDRAM_tRFC - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ - -/* - * nand device 1 on dave (PPChameleonEVB) needs more time, - * so we just introduce additional wait in nand_wait(), - * effectively for both devices. - */ -#define PPCHAMELON_NAND_TIMER_HACK - -#define CONFIG_SYS_NAND0_BASE 0xFF400000 -#define CONFIG_SYS_NAND1_BASE 0xFF000000 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE } -#define NAND_BIG_DELAY_US 25 -#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ -#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ -#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ - -#define MACRO_NAND_DISABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_ENABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ - switch((unsigned long)nandptr) { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \ - break; \ - } \ -} while(0) - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ - -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* Reserve 256 kB for Monitor */ -/* -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -*/ - -/* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_FLASH_BASE 0xFFFB0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) - -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#ifdef ENVIRONMENT_IN_EEPROM - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/ - -#else /* DEFAULT: environment in flash, using redundand flash sectors */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ -#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ -#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000 -#define CONFIG_ENV_SIZE_REDUND 0x2000 - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#endif /* ENVIRONMENT_IN_EEPROM */ - - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (External SRAM) initialization */ -/* Since this must replace NOR Flash, we use the same settings for CS0 */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x92015480 -#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x92015480 -#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ - -#ifdef CONFIG_PPCHAMELEON_SMI712 -/* - * Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -/*#define CONFIG_VIDEO_BMP_LOGO*/ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ -#define CONFIG_SYS_ISA_IO 0xE8000000 -/* see also drivers/video/videomodes.c */ -#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303 -#endif - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30] - EMAC0 input - * GPIO0[31] - EMAC1 reject packet as output - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 - -#define CONFIG_NO_SERIAL_EEPROM - -/*--------------------------------------------------------------------*/ - -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!----------------------------------------------------------------------- -! Defines for entry options. -! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that -! are plugged in the board will be utilized as non-ECC DIMMs. -!----------------------------------------------------------------------- -*/ -#undef AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) - -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#else -#error "* External frequency (SysClk) not defined! *" -#endif - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -/* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 -#define CONFIG_SYS_OPB_FREQ 55555555 -/* Model ME */ -#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 -#define CONFIG_SYS_OPB_FREQ 66666666 -#else -/* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 -#define CONFIG_SYS_OPB_FREQ 66666666 -#endif - -#endif /* CONFIG_NO_SERIAL_EEPROM */ - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand" -*/ - -/* 256 kB U-boot image */ -/* -#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ - "1792k(user),256k(u-boot);" \ - "ppchameleonevb-nand:-(nand)" -*/ - -/* 320 kB U-boot image */ -/* -#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ - "1728k(user),320k(u-boot);" \ - "ppchameleonevb-nand:-(nand)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/QS823.h b/include/configs/QS823.h deleted file mode 100644 index d712828245..0000000000 --- a/include/configs/QS823.h +++ /dev/null @@ -1,554 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* various debug settings */ -#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ -#undef CONFIG_SILENT_CONSOLE /* silent console */ -#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ -#undef DEBUG_FLASH /* debug flash code */ -#undef FLASH_DEBUG /* debug fash code */ -#undef DEBUG_ENV /* debug environment code */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_QS823 1 /* ...on a QS823 module */ -#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* Select the target clock speed */ -#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ -#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ -#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ -#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ -#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ - -#ifdef CONFIG_CLOCK_16MHZ -#define CONFIG_CLOCK_MULT 512 -#endif - -#ifdef CONFIG_CLOCK_33MHZ -#define CONFIG_CLOCK_MULT 1024 -#endif - -#ifdef CONFIG_CLOCK_50MHZ -#define CONFIG_CLOCK_MULT 1525 -#endif - -#ifdef CONFIG_CLOCK_66MHZ -#define CONFIG_CLOCK_MULT 2048 -#endif - -#ifdef CONFIG_CLOCK_80MHZ -#define CONFIG_CLOCK_MULT 2441 -#endif - -/* choose flash size, 4Mb or 8Mb */ -#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ -#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ - -#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - -/* Define default IP addresses */ -#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ -#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ - -/* message to say directly after booting */ -#define CONFIG_PREBOOT "echo '';" \ - "echo 'type:';" \ - "echo 'run boot_nfs to boot to NFS';" \ - "echo 'run boot_flash to boot to flash';" \ - "echo '';" \ - "echo 'run flash_rootfs to install a new rootfs';" \ - "echo 'run flash_env to clear the env sector';" \ - "echo 'run flash_rw to clear the rw fs';" \ - "echo 'run flash_uboot to install a new u-boot';" \ - "echo 'run flash_kernel to install a new kernel';" - -/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND "run boot_nfs" - -#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ - -/* Our flash filesystem looks like this - * - * 4Mb board: - * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - * 8Mb board: - * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - */ - -/* environment for 4Mb board */ -#ifdef CONFIG_FLASH_4MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS823\0" \ - "hostname=qs823\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_4MB */ - -/* environment for 8Mb board */ -#ifdef CONFIG_FLASH_8MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS823\0" \ - "hostname=qs823\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_8MB */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_STATUS_LED /* Status LED disabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_RUN - - -/*----------------------------------------------------------------------- - * Environment variable storage is in FLASH, one sector before U-boot - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ -#define CONFIG_ENV_SIZE 0x2000 /* 8kb */ -#define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ - -#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ -#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * TODO flash parameters - * FLASH organization for Intel Strataflash - */ -#undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ - -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - */ - -/* MF (Multiplication Factor of SPLL) */ -/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */ -#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) -#define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) -#define CONFIG_SYS_BRGCLK_PRESCALE 1 -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) -#define CONFIG_SYS_BRGCLK_PRESCALE 4 -#endif - -#if defined(CONFIG_CLOCK_80MHZ) -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) -#define CONFIG_SYS_BRGCLK_PRESCALE 4 -#endif - -#define SCCR_MASK CONFIG_SYS_SCCR - -/*----------------------------------------------------------------------- - * Debug Enable Register - * 0x73E67C0F - All interrupts handled by BDM - * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM - *----------------------------------------------------------------------- -#define CONFIG_SYS_DER 0x73E67C0F -#define CONFIG_SYS_DER 0x0082400F - - #------------------------------------------------------------------------- - # Program the Debug Enable Register (DER). This register provides the user - # with the reason for entering into the debug mode. We want all conditions - # to end up as an exception. We don't want to enter into debug mode for - # any condition. See the back of of the Development Support section of the - # MPC860 User Manual for a description of this register. - #------------------------------------------------------------------------- -*/ -#define CONFIG_SYS_DER 0 - -/*----------------------------------------------------------------------- - * Memory Controller Initialization Constants - *----------------------------------------------------------------------- - */ - -/* - * BR0 and OR0 (AMD dual FLASH devices) - * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) - */ -#define CONFIG_SYS_PRELIM_OR_AM -#define CONFIG_SYS_OR_TIMING_FLASH - -/* - *----------------------------------------------------------------------- - * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) - * flash that resides on the QS823. - *----------------------------------------------------------------------- - */ - -/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ -/* represents a minumum 32K block size. */ -#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) -#define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V) - -/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ -/* which defines a 8 Mbyte memory block. */ -#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) - -#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* 0101 = Add a 5 clock cycle wait state */ -#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) -/* 0011 = Add a 3 clock cycle wait state */ -/* 29.8ns clock * (3 + 2) = 149ns cycle time */ -#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -/* 0010 = Add a 2 clock cycle wait state */ -#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) -#endif - -/* - * BR1 and OR1 (SDRAM) - * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) - * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) - * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) - * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) - */ - -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ - -/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which - * represents a 128 Mbyte block the DRAM in - * this address base. - */ -#define vOR1_AM ((0xF800 << 16) + (0 << 15)) -#define vBR1_BA ((0x0000 << 16) + (0 << 15)) -#define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) -#define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) - -/* Machine A Mode Register */ - -/* PTA Periodic Timer A */ - -#if defined(CONFIG_CLOCK_80MHZ) -#define vMAMR_PTA (19 << 24) -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define vMAMR_PTA (16 << 24) -#endif - -#if defined(CONFIG_CLOCK_50MHZ) -#define vMAMR_PTA (195 << 24) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) -#define vMAMR_PTA (131 << 24) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -#define vMAMR_PTA (65 << 24) -#endif - -/* For boards with 16M of SDRAM */ -#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* For boards with 32M of SDRAM */ -#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* Memory Periodic Timer Prescaler Register */ - -#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* Divide by 32 */ -#define CONFIG_SYS_MPTPR 0x02 -#endif - -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -/* Divide by 16 */ -#define CONFIG_SYS_MPTPR 0x04 -#endif - -/* - * BR2 and OR2 (Unused) - * Base address = 0xF020_0000 - 0xF020_0FFF - * - */ -#define CONFIG_SYS_OR2_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR2_PRELIM 0xF0200000 - -/* - * BR3 and OR3 (External Bus CS3) - * Base address = 0xF030_0000 - 0xF030_0FFF - * - */ -#define CONFIG_SYS_OR3_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR3_PRELIM 0xF0300000 - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF040_0000 - 0xF040_0FFF - * - */ -#define CONFIG_SYS_OR4_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR4_PRELIM 0xF0400000 - - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF050_0000 - 0xF050_0FFF - * - */ -#define CONFIG_SYS_OR5_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR5_PRELIM 0xF0500000 - -/* - * BR6 and OR6 (Unused) - * Base address = 0xF060_0000 - 0xF060_0FFF - * - */ -#define CONFIG_SYS_OR6_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR6_PRELIM 0xF0600000 - -/* - * BR7 and OR7 (Unused) - * Base address = 0xF070_0000 - 0xF070_0FFF - * - */ -#define CONFIG_SYS_OR7_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR7_PRELIM 0xF0700000 - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/QS850.h b/include/configs/QS850.h deleted file mode 100644 index 3229095ddf..0000000000 --- a/include/configs/QS850.h +++ /dev/null @@ -1,554 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* various debug settings */ -#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ -#undef CONFIG_SILENT_CONSOLE /* silent console */ -#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ -#undef DEBUG_FLASH /* debug flash code */ -#undef FLASH_DEBUG /* debug fash code */ -#undef DEBUG_ENV /* debug environment code */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_QS850 1 /* ...on a QS850 module */ -#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* Select the target clock speed */ -#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ -#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ -#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ -#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ -#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ - -#ifdef CONFIG_CLOCK_16MHZ -#define CONFIG_CLOCK_MULT 512 -#endif - -#ifdef CONFIG_CLOCK_33MHZ -#define CONFIG_CLOCK_MULT 1024 -#endif - -#ifdef CONFIG_CLOCK_50MHZ -#define CONFIG_CLOCK_MULT 1525 -#endif - -#ifdef CONFIG_CLOCK_66MHZ -#define CONFIG_CLOCK_MULT 2048 -#endif - -#ifdef CONFIG_CLOCK_80MHZ -#define CONFIG_CLOCK_MULT 2441 -#endif - -/* choose flash size, 4Mb or 8Mb */ -#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ -#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ - -#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - -/* Define default IP addresses */ -#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ -#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ - -/* message to say directly after booting */ -#define CONFIG_PREBOOT "echo '';" \ - "echo 'type:';" \ - "echo 'run boot_nfs to boot to NFS';" \ - "echo 'run boot_flash to boot to flash';" \ - "echo '';" \ - "echo 'run flash_rootfs to install a new rootfs';" \ - "echo 'run flash_env to clear the env sector';" \ - "echo 'run flash_rw to clear the rw fs';" \ - "echo 'run flash_uboot to install a new u-boot';" \ - "echo 'run flash_kernel to install a new kernel';" - -/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND "run boot_nfs" - -#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ - -/* Our flash filesystem looks like this - * - * 4Mb board: - * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - * 8Mb board: - * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - */ - -/* environment for 4Mb board */ -#ifdef CONFIG_FLASH_4MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS850\0" \ - "hostname=qs850\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_4MB */ - -/* environment for 8Mb board */ -#ifdef CONFIG_FLASH_8MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS850\0" \ - "hostname=qs850\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_8MB */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_STATUS_LED /* Status LED disabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_RUN - - -/*----------------------------------------------------------------------- - * Environment variable storage is in FLASH, one sector before U-boot - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ -#define CONFIG_ENV_SIZE 0x2000 /* 8kb */ -#define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ - -#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ -#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * TODO flash parameters - * FLASH organization for Intel Strataflash - */ -#undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ - -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - */ - -/* MF (Multiplication Factor of SPLL) */ -/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */ -#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) -#define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) -#define CONFIG_SYS_BRGCLK_PRESCALE 1 -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) -#define CONFIG_SYS_BRGCLK_PRESCALE 4 -#endif - -#if defined(CONFIG_CLOCK_80MHZ) -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) -#define CONFIG_SYS_BRGCLK_PRESCALE 4 -#endif - -#define SCCR_MASK CONFIG_SYS_SCCR - -/*----------------------------------------------------------------------- - * Debug Enable Register - * 0x73E67C0F - All interrupts handled by BDM - * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM - *----------------------------------------------------------------------- -#define CONFIG_SYS_DER 0x73E67C0F -#define CONFIG_SYS_DER 0x0082400F - - #------------------------------------------------------------------------- - # Program the Debug Enable Register (DER). This register provides the user - # with the reason for entering into the debug mode. We want all conditions - # to end up as an exception. We don't want to enter into debug mode for - # any condition. See the back of of the Development Support section of the - # MPC860 User Manual for a description of this register. - #------------------------------------------------------------------------- -*/ -#define CONFIG_SYS_DER 0 - -/*----------------------------------------------------------------------- - * Memory Controller Initialization Constants - *----------------------------------------------------------------------- - */ - -/* - * BR0 and OR0 (AMD dual FLASH devices) - * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) - */ -#define CONFIG_SYS_PRELIM_OR_AM -#define CONFIG_SYS_OR_TIMING_FLASH - -/* - *----------------------------------------------------------------------- - * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) - * flash that resides on the QS850. - *----------------------------------------------------------------------- - */ - -/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ -/* represents a minumum 32K block size. */ -#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) -#define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V) - -/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ -/* which defines a 8 Mbyte memory block. */ -#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) - -#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* 0101 = Add a 5 clock cycle wait state */ -#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) -/* 0011 = Add a 3 clock cycle wait state */ -/* 29.8ns clock * (3 + 2) = 149ns cycle time */ -#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -/* 0010 = Add a 2 clock cycle wait state */ -#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) -#endif - -/* - * BR1 and OR1 (SDRAM) - * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) - * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) - * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) - * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) - */ - -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ - -/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which - * represents a 128 Mbyte block the DRAM in - * this address base. - */ -#define vOR1_AM ((0xF800 << 16) + (0 << 15)) -#define vBR1_BA ((0x0000 << 16) + (0 << 15)) -#define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) -#define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) - -/* Machine A Mode Register */ - -/* PTA Periodic Timer A */ - -#if defined(CONFIG_CLOCK_80MHZ) -#define vMAMR_PTA (19 << 24) -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define vMAMR_PTA (16 << 24) -#endif - -#if defined(CONFIG_CLOCK_50MHZ) -#define vMAMR_PTA (195 << 24) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) -#define vMAMR_PTA (131 << 24) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -#define vMAMR_PTA (65 << 24) -#endif - -/* For boards with 16M of SDRAM */ -#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* For boards with 32M of SDRAM */ -#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* Memory Periodic Timer Prescaler Register */ - -#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* Divide by 32 */ -#define CONFIG_SYS_MPTPR 0x02 -#endif - -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -/* Divide by 16 */ -#define CONFIG_SYS_MPTPR 0x04 -#endif - -/* - * BR2 and OR2 (Unused) - * Base address = 0xF020_0000 - 0xF020_0FFF - * - */ -#define CONFIG_SYS_OR2_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR2_PRELIM 0xF0200000 - -/* - * BR3 and OR3 (External Bus CS3) - * Base address = 0xF030_0000 - 0xF030_0FFF - * - */ -#define CONFIG_SYS_OR3_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR3_PRELIM 0xF0300000 - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF040_0000 - 0xF040_0FFF - * - */ -#define CONFIG_SYS_OR4_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR4_PRELIM 0xF0400000 - - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF050_0000 - 0xF050_0FFF - * - */ -#define CONFIG_SYS_OR5_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR5_PRELIM 0xF0500000 - -/* - * BR6 and OR6 (Unused) - * Base address = 0xF060_0000 - 0xF060_0FFF - * - */ -#define CONFIG_SYS_OR6_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR6_PRELIM 0xF0600000 - -/* - * BR7 and OR7 (Unused) - * Base address = 0xF070_0000 - 0xF070_0FFF - * - */ -#define CONFIG_SYS_OR7_PRELIM 0xFFF00000 -#define CONFIG_SYS_BR7_PRELIM 0xF0700000 - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h deleted file mode 100644 index 7c77c6b854..0000000000 --- a/include/configs/QS860T.h +++ /dev/null @@ -1,393 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* various debug settings */ -#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ -#undef CONFIG_SILENT_CONSOLE /* silent console */ -#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ -#undef DEBUG_FLASH /* debug flash code */ -#undef FLASH_DEBUG /* debug fash code */ -#undef DEBUG_ENV /* debug environment code */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ - - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_QS860T 1 /* ...on a QS860T module */ - -/* Start address of 512K Socketed Flash */ -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */ -#define CONFIG_MII -#define FEC_INTERRUPT SIU_LEVEL1 -#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */ -#define CONFIG_SYS_DISCOVER_PHY - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */ -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* Pass clocks to Linux 2.4.18 in Hz */ -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;" \ - "echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \ - "echo" - -#undef CONFIG_BOOTARGS -/* TODO compare against CADM860 */ -#define CONFIG_BOOTCOMMAND "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - - -/* TODO */ -#if 0 -/* Look at these */ -CONFIG_IPADDR -CONFIG_SERVERIP -CONFIG_I2C -CONFIG_SPI -#endif - -/* - * Environment variable storage is in NVRAM - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */ -#define CONFIG_ENV_ADDR 0xD100E000 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* TODO - size? */ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* TODO flash parameters */ -/*----------------------------------------------------------------------- - * FLASH organization for Intel Strataflash - */ -#define CONFIG_SYS_FLASH_16BIT 1 /* 16-bit wide flash memory */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#undef CONFIG_ENV_IS_IN_FLASH - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI) -#else -#define CONFIG_SYS_SYPCR 0xFFFFFF88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR 0x00620000 - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_TBSCR 0x00C3 - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PISCR 0x0082 - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PLPRCR 0x0090D000 - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR 0x02000000 - - -/*----------------------------------------------------------------------- - * Debug Enable Register - * 0x73E67C0F - All interrupts handled by BDM - * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM - *----------------------------------------------------------------------- -#define CONFIG_SYS_DER 0x73E67C0F -*/ -#define CONFIG_SYS_DER 0x0082400F - - -/*----------------------------------------------------------------------- - * Memory Controller Initialization Constants - *----------------------------------------------------------------------- - */ - -/* - * BR0 and OR0 (AMD 512K Socketed FLASH) - * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) - */ -#define CONFIG_SYS_PRELIM_OR_AM -#define CONFIG_SYS_OR_TIMING_FLASH - -#define FLASH_BASE0_PRELIM 0xFFF00001 -#define CONFIG_SYS_OR0_PRELIM 0xFFF80D42 -#define CONFIG_SYS_BR0_PRELIM 0xFFF00401 - - -/* - * BR1 and OR1 (Intel 8M StrataFLASH) - * Base address = 0xD000_0000 - 0xD07F_FFFF - */ - -#define FLASH_BASE1_PRELIM 0xD0000000 -#define CONFIG_SYS_OR1_PRELIM 0xFF800D42 -#define CONFIG_SYS_BR1_PRELIM 0xD0000801 -/* #define CONFIG_SYS_OR1 0xFF800D42 */ -/* #define CONFIG_SYS_BR1 0xD0000801 */ - - -/* - * BR2 and OR2 (SDRAM) - * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) - * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) - * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) - * - */ -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ - -/* SDRAM timing */ -#define SDRAM_TIMING 0x00000A00 - -/* For boards with 16M of SDRAM */ -#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CONFIG_SYS_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */ - -/* For boards with 64M of SDRAM */ -#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */ -/* TODO - determine real value */ -#define CONFIG_SYS_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */ - -#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING) -#define CONFIG_SYS_BR2 (SDRAM_BASE | 0x000000C1) - - -/* - * BR3 and OR3 (NVRAM, Sipex, NAND Flash) - * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM) - * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register) - * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register) - * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register) - * - */ - -#define CONFIG_SYS_OR3_PRELIM 0xFFC00DF6 -#define CONFIG_SYS_BR3_PRELIM 0xD1000401 -/* #define CONFIG_SYS_OR3 0xFFC00DF6 */ -/* #define CONFIG_SYS_BR3 0xD1000401 */ - - -/* - * BR4 and OR4 (Unused) - * Base address = 0xE000_0000 - 0xE3FF_FFFF - * - */ - -#define CONFIG_SYS_OR4_PRELIM 0xFF000000 -#define CONFIG_SYS_BR4_PRELIM 0xE0000000 -/* #define CONFIG_SYS_OR4 0xFF000000 */ -/* #define CONFIG_SYS_BR4 0xE0000000 */ - - -/* - * BR5 and OR5 (Expansion bus) - * Base address = 0xE400_0000 - 0xE7FF_FFFF - * - */ - -#define CONFIG_SYS_OR5_PRELIM 0xFF000000 -#define CONFIG_SYS_BR5_PRELIM 0xE4000000 -/* #define CONFIG_SYS_OR5 0xFF000000 */ -/* #define CONFIG_SYS_BR5 0xE4000000 */ - - -/* - * BR6 and OR6 (Expansion bus) - * Base address = 0xE800_0000 - 0xEBFF_FFFF - * - */ - -#define CONFIG_SYS_OR6_PRELIM 0xFF000000 -#define CONFIG_SYS_BR6_PRELIM 0xE8000000 -/* #define CONFIG_SYS_OR6 0xFF000000 */ -/* #define CONFIG_SYS_BR6 0xE8000000 */ - - -/* - * BR7 and OR7 (Expansion bus) - * Base address = 0xEC00_0000 - 0xEFFF_FFFF - * - */ - -#define CONFIG_SYS_OR7_PRELIM 0xFF000000 -#define CONFIG_SYS_BR7_PRELIM 0xE8000000 -/* #define CONFIG_SYS_OR7 0xFF000000 */ -/* #define CONFIG_SYS_BR7 0xE8000000 */ - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h deleted file mode 100644 index efe699538c..0000000000 --- a/include/configs/R360MPI.h +++ /dev/null @@ -1,467 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_R360MPI 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_LCD -#define CONFIG_MPC8XX_LCD -#undef CONFIG_EDT32F10 -#define CONFIG_SHARP_LQ057Q3DC02 - -#define CONFIG_SPLASH_SCREEN - -#define MPC8XX_FACT 1 /* Multiply by 1 */ -#define MPC8XX_XIN 50000000 /* 50 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */ -#if 0 -#define CONFIG_BOOTDELAY 0 /* immediate boot */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#undef CONFIG_SCC1_ENET -#define CONFIG_SCC2_ENET - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ -#undef CONFIG_SYS_I2C_SOFT /* To I2C with software support */ -#define CONFIG_SYS_I2C_SPEED 4700 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#if defined(CONFIG_SYS_I2C_SOFT) -#define CONFIG_SYS_SYS_I2C_SOFT_SPEED 4700 /* I2C speed and slave address */ -#define CONFIG_SYS_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(50) -#endif /* #define(CONFIG_SYS_I2C_SOFT) */ - -#define CONFIG_SYS_I2C_LCD_ADDR 0x8 /* LCD Control */ -#define CONFIG_SYS_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */ -#define CONFIG_SYS_I2C_TEM_ADDR 0x49 /* Temperature Sensors */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BMP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* we need the null device */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* must set console from env */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * JFFS2 partitions - */ -/* No command line, one static partition - * use all the space starting at offset 3MB*/ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00300000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=r360-0" -#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)" -*/ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CONFIG_SYS_PLPRCR \ - ( (5-1)< ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#if defined(CONFIG_80MHz) -#define CONFIG_SYS_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CONFIG_SYS_MAMR_PTA 129 -#else /* 50 MHz */ -#define CONFIG_SYS_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h deleted file mode 100644 index 3970dc36f1..0000000000 --- a/include/configs/RBC823.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Udi Finkelstein udif@udif.com - * For the RBC823 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_RBC823 1 /* ...on a RBC823 module */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#if 0 -#define DEBUG 1 -#define CONFIG_LAST_STAGE_INIT -#endif -#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */ -#define CONFIG_LCD 1 /* use LCD controller ... */ -#define CONFIG_MPC8XX_LCD -#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */ - -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_SMC1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ 48000000L - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#undef CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */ - -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 40000 -#define CONFIG_SYS_I2C_SLAVE 0xfe -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_BMP -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM - -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -/* -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -*/ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -/* - * for 48 MHz, we use a 4 MHz clock * 12 - */ -#define CONFIG_SYS_PLPRCR \ - ( (12-1)< - -#define CONFIG_CMD_ELF - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_RESET_ADDRESS 0x80000000 -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------------- - * I2C Configuration - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0x34 - - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ - -#if defined(CONFIG_SYS_I2C_SOFT) -#define CONFIG_SYS_I2C 1 -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00000010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x34 -#endif - -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE 0xFF000000 -/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#else -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR 0xfa000100 -#define CONFIG_ENV_SIZE 0x1000 -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/* #define CONFIG_SYS_DER 0x2002000F */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CONFIG_SYS_OR3_PRELIM 0xff7f8970 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFF80970 - -/* ECCX CS settings */ -#define SED13806_OR 0xFFC00108 /* - 4 Mo - - Burst inhibit - - external TA */ -#define SED13806_REG_ADDR 0xa0000000 -#define SED13806_ACCES 0x801 /* 16 bit access */ - - -/* Global definitions for the ECCX board */ -#define ECCX_CSR_ADDR (0xfac00000) -#define ECCX_CSR8_OFFSET (0x8) -#define ECCX_CSR11_OFFSET (0xB) -#define ECCX_CSR12_OFFSET (0xC) - -#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET) -#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET) -#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET) - - -#define REG_GPIO_CTRL 0x008 - -/* Definitions for CSR8 */ -#define ECCX_ENEPSON 0x80 /* Bit 0: - 0= disable and reset SED1386 - 1= enable SED1386 */ -/* Bit 1: 0= SED1386 in Big Endian mode */ -/* 1= SED1386 in little endian mode */ -#define ECCX_LE 0x40 -#define ECCX_BE 0x00 - -/* Bit 2,3: Selection */ -/* 00 = Disabled */ -/* 01 = CS2 is used for the SED1386 */ -/* 10 = CS5 is used for the SED1386 */ -/* 11 = reserved */ -#define ECCX_CS2 0x10 -#define ECCX_CS5 0x20 - -/* Definitions for CSR12 */ -#define ECCX_ID 0x02 -#define ECCX_860 0x01 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 58 - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_MIIRST 0x80 -#define BCSR2_MIIPWRDWN 0x40 -#define BCSR2_MIICTL 0x08 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - - -/* - * Environment setting - */ - -/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */ -/* #define CONFIG_IPADDR 10.10.106.1 */ -/* #define CONFIG_SERVERIP 10.10.104.11 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h deleted file mode 100644 index ada7e145c0..0000000000 --- a/include/configs/RPXlite.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define RPXLite_50MHz - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 40000 /* 40 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* Software (bit-bang) I2C driver configuration */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SDA; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SCL; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -/* M41T11 Serial Access Timekeeper(R) SRAM */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* play along with the linux driver */ -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_RESET_ADDRESS 0x09900000 - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 58 - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -#endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h deleted file mode 100644 index ffc84d2901..0000000000 --- a/include/configs/RPXlite_DW.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-BOOT port on RPXlite board - */ - -/* - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * U-BOOT port on RPXlite DW version board--RPXlite_DW - * June 8 ,2004 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* #define DEBUG 1 */ -/* #define DEPLOYMENT 1 */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ -#define CONFIG_RPXLITE 1 /* RPXlite DW version board */ - -#define CONFIG_SYS_TEXT_BASE 0xff000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ - -#ifdef DEPLOYMENT -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "autoboot in %d seconds (stop with 'st')...\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR "st" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1 -#define CONFIG_BOOT_RETRY_MIN 1 -#endif /* DEPLOYMENT */ -#endif /* DEBUG */ - -/* pre-boot commands */ -#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "gatewayip=172.16.115.254\0" \ - "netmask=255.255.255.0\0" \ - "kernel_addr=ff040000\0" \ - "ramdisk_addr=ff200000\0" \ - "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \ - "${filesize};md ${kernel_addr};" \ - "echo kernel updating finished\0" \ - "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ - "${filesize};md ff000000;" \ - "echo u-boot updating finished\0" \ - "eu=protect off 1:6;era 1:6;reset\0" \ - "lcd=setenv stdout lcd;setenv stdin lcd\0" \ - "ser=setenv stdout serial;setenv stdin serial\0" \ - "verify=no" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you - don't want the advanced function */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DHCP - -#ifdef CONFIG_SPLASH_SCREEN -#define CONFIG_CMD_BMP -#endif - - -/* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ - -#define CONFIG_NETCONSOLE - -#endif /* 1 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "u-boot>" /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#if defined(DEBUG) || defined(CONFIG_CMD_IDE) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif - -#define CONFIG_SYS_MONITOR_BASE 0xFF000000 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_ADDR 0xFA000100 -#define CONFIG_ENV_SIZE 0x1000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#endif /* CONFIG_ENV_IS_IN_NVRAM */ - -#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 32-bit 12-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /* We can get SYPCR: 0xFFFF0689. */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 32-bit 12-30 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */ - -/*--------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 16-bit 12-16 - *--------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) -/* TBSCR: 0x00C3 [SAM] */ - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18 - *----------------------------------------------------------------------- - * [RTC enabled but not stopped on FRZ] - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 16-bit 12-23 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - * [Periodic timer enabled,Periodic timer interrupt disable. ] - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -/* up to 64 MHz we use a 1:2 clock */ -#if defined(RPXlite_64MHz) -#define CONFIG_SYS_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */ -#else -#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 5-3 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */ -#if defined(RPXlite_64MHz) -#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ -#else -#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ -#endif - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ -#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 -#define CONFIG_SYS_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK)) -#define CONFIG_SYS_OR1_PRELIM ( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXlite mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CONFIG_SYS_OR3_PRELIM 0xFF7F8900 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0040 - -/* - * Memory Periodic Timer Prescaler - */ -/* periodic timer for refresh */ -#if defined(RPXlite_64MHz) -#define CONFIG_SYS_MAMR_PTA 32 -#else -#define CONFIG_SYS_MAMR_PTA 20 -#endif - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10) -/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */ - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* - * BCSRx - * - * Board Status and Control Registers - * - */ -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */ -#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */ - -#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */ -#define BCSR2_ENBRG1 0x04 /* Added by SAM. */ - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */ -#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */ -#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */ - -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -/* - * Environment setting - */ -#define CONFIG_ETHADDR 00:10:EC:00:37:5B -#define CONFIG_IPADDR 172.16.115.7 -#define CONFIG_SERVERIP 172.16.115.6 -#define CONFIG_ROOTPATH "/workspace/myfilesystem/target/" -#define CONFIG_BOOTFILE "uImage.rpxusb" -#define CONFIG_HOSTNAME LITE_H1_DW - -#endif /* __CONFIG_H */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h deleted file mode 100644 index d4d3d5738d..0000000000 --- a/include/configs/RPXsuper.h +++ /dev/null @@ -1,504 +0,0 @@ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x80F00000 - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ -/* for the AY-Revision which does not use the HRCW */ -#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/* How is switch S2 set? We really only want the MODCK[1-3] bits, so - * only the 3 least significant bits are important. -*/ -#define CONFIG_SYS_SBC_S2 0x04 - -/* What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core - * 0x2 0x2 33 133 133 - * 0x2 0x4 33 133 200 - * 0x5 0x5 66 133 133 - * 0x5 0x7 66 133 200 - */ -#define CONFIG_SYS_SBC_MODCK_H 0x06 - -#define CONFIG_SYS_SBC_BOOT_LOW 1 /* only for HRCW */ -#undef CONFIG_SYS_SBC_BOOT_LOW - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE. - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CONFIG_SYS_FLASH0_BASE 0x80000000 -#define CONFIG_SYS_FLASH0_SIZE 16 - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. U-Boot expects this to be the on board FLASH. If you don't - * want it enabled, don't define these constants. - */ -#define CONFIG_SYS_FLASH1_BASE 0 -#define CONFIG_SYS_FLASH1_SIZE 0 -#undef CONFIG_SYS_FLASH1_BASE -#undef CONFIG_SYS_FLASH1_SIZE - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM1_BASE 0x04000000 -#define CONFIG_SYS_SDRAM1_SIZE 32 - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CONFIG_SYS_LED_BASE 0x00000000 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ - -#if ( CONFIG_ETHER_INDEX == 3 ) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Half Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -/*#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ -# define CONFIG_SYS_FCC_PSMR 0 - -#else /* CONFIG_ETHER_INDEX */ -# error "on RPX Super ethernet must be FCC3" -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 115200 - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 08:00:22:50:70:63 - -#define CONFIG_IPADDR 192.168.1.99 -#define CONFIG_SERVERIP 192.168.1.3 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY -1 - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#undef CONFIG_CMD_KGDB - - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/* Where do the on board registers (CS4) live? */ -#define CONFIG_SYS_REGS_BASE 0xFA000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 |\ - HRCW_DPPC11 |\ - CONFIG_SYS_SBC_HRCW_IMMR |\ - HRCW_MMR00 |\ - HRCW_LBPC11 |\ - HRCW_APPC10 |\ - HRCW_CS10PC00 |\ - (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH0_BASE + 0x00F00000) - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 - -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (/*HID0_ICE |*/\ - /*HID0_DCE |*/\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_EBM |\ - BCR_PLDP |\ - BCR_EAV |\ - BCR_NPQM0) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC01) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90) - * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60) - * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60) - * 3 unused - * 4 60x GPCM 8 bit Board Regs, LEDs, switches - * 5 unused - * 6 unused - * 7 unused - * 8 PCMCIA - * 9 unused - * 10 unused - * 11 unused -*/ - -/* Bank 0 - FLASH - * - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_6_CLK |\ - ORxG_EHTR) - -/* Bank 1 - SDRAM - * - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12 |\ - ORxS_IBID) - -#define CONFIG_SYS_PSDMR 0x014DA412 -#define CONFIG_SYS_PSRT 0x79 - - -/* Bank 2 - SDRAM - * - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_LSDMR 0x0169A512 -#define CONFIG_SYS_LSRT 0x79 - -#define CONFIG_SYS_MPTPR (0x0800 & MPTPR_PTP_MSK) - -/* Bank 4 - On board registers - * - */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -#endif /* __CONFIG_H */ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h deleted file mode 100644 index 06273a2ae1..0000000000 --- a/include/configs/RRvision.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_RRVISION 1 /* ...on a RRvision board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_GCLK_FREQ 64000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "setenv stdout serial" - -#undef CONFIG_BOOTARGS -#define CONFIG_ETHADDR 00:50:C2:00:E0:70 -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_IPADDR 10.0.0.5 -#define CONFIG_SERVERIP 10.0.0.2 -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_ROOTPATH "/opt/eldk/ppc_8xx" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \ - ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "load=tftp 100000 /tftpboot/u-boot.bin\0" \ - "update=protect off 1:0-8;era 1:0-8;" \ - "cp.b 100000 40000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "kernel_img=/tftpboot/uImage\0" \ - "kernel_load=tftp 200000 ${kernel_img}\0" \ - "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \ - "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" - - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* disturbs display */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -#ifdef CONFIG_LCD -#define CONFIG_MPC8XX_LCD -#else -#define CONFIG_VIDEO 1 /* To enable the video initialization */ - -/* Video related */ -#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ -#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */ -#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */ -#endif - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE - -#undef CONFIG_CMD_PCMCIA -#undef CONFIG_CMD_IDE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -/* timeout values are in ticks = ms */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (120*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (1 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ - -/* for 64 MHz, we use a 16 MHz clock * 4 */ -#define CONFIG_SYS_PLPRCR ( (4-1)< ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#define CONFIG_SYS_MAMR_PTA 129 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -#endif /* __CONFIG_H */ diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h deleted file mode 100644 index 1404634991..0000000000 --- a/include/configs/Rattler.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * U-Boot configuration for Analogue&Micro Rattler boards. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_MPC8248 -#define CPU_ID_STR "MPC8248" -#else -#define CONFIG_MPC8260 -#define CPU_ID_STR "MPC8250" -#endif /* CONFIG_MPC8248 */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_RATTLER /* Analogue&Micro Rattler board */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 1) - -/* - Rx clock is CLK11 - * - Tx clock is CLK10 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - Rx clock is CLK15 - * - Tx clock is CLK14 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \ - else iop->pdat &= ~0x00800000 - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)" - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#if defined(CONFIG_CMD_JFFS2) -#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00100000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=rattler-0" -#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)" -*/ -#endif /* CONFIG_CMD_JFFS2 */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -#define CONFIG_SYS_DEFAULT_IMMR 0xFF010000 - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 32 -#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041) -#define CONFIG_SYS_SDRAM_OR 0xFE002EC0 - -#define CONFIG_SYS_BCSR 0xFC000000 - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x0E04C000 -#define CONFIG_SYS_SYPCR 0xFFFFFFC3 -#define CONFIG_SYS_BCR 0x00000000 -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -#define CONFIG_SYS_RMR RMR_CSRE -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CONFIG_SYS_RCCR 0 - -#define CONFIG_SYS_PSDMR 0x8249A452 -#define CONFIG_SYS_PSRT 0x1F -#define CONFIG_SYS_MPTPR 0x2000 - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001) -#define CONFIG_SYS_OR0_PRELIM 0xFF001ED6 -#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801) -#define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6 - -#define CONFIG_SYS_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h deleted file mode 100644 index 3448ef35a8..0000000000 --- a/include/configs/SIMPC8313.h +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright (C) Sheldon Instruments, Inc. 2008 - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * simpc8313 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_NAND_U_BOOT - -#define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1 - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) - -#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 - -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_ELBC 1 - -#define CONFIG_MISC_INIT_R - -/* - * On-board devices - * - * TSEC1 is Marvell PHY 88E1118 - */ - -#define CONFIG_SYS_33MHZ - -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ - -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - -#define CONFIG_SYS_IMMR 0xE0000000 - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - -/* - * Device configurations - */ -#define CONFIG_TSEC1 - -/* - * DDR Setup - */ - /* DDR is system memory*/ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED (512 << 20) - -#define CONFIG_SYS_DDRCDR (DDRCDR_EN \ - | DDRCDR_PZ_NOMZ \ - | DDRCDR_NZ_NOMZ \ - | DDRCDR_M_ODR) - /* 0x73000002 TODO ODR & DRN ? */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_NO_FLASH - -#if !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 -#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ - | (0xFF << LBCR_BMT_SHIFT) \ - | 0xF) /* 0x0004ff0f */ - - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* drivers/mtd/nand/nand.c */ -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xFFF00000 -#else -#define CONFIG_SYS_NAND_BASE 0xE2800000 -#endif -#define CONFIG_SYS_FPGA_BASE 0xFF000000 - -#define CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_NAND_FSL_ELBC 1 - -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit Port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ - -#ifdef CONFIG_NAND_SP -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ - /* NAND chip block size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) -#define NAND_CACHE_PAGES 32 -#elif defined(CONFIG_NAND_LP) -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \ - | OR_FCM_PGS \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */ - /* NAND chip block size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) -#define NAND_CACHE_PAGES 64 -#else -#error Page size of NAND not defined. -#endif /* CONFIG_NAND_SP */ - -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE - -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \ - | BR_PS_16 \ - | BR_MS_UPMA \ - | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \ - | OR_UPM_BCTLD) - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB) - -/* - * JFFS2 configuration - */ -#define CONFIG_JFFS2_NAND -#define CONFIG_JFFS2_DEV "nand0" - -/* mtdparts command line support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nand0=nand0" -#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#ifdef CONFIG_NAND_SPL -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -/* - * TSEC - */ -#define CONFIG_TSEC_ENET /* TSEC ethernet support */ - -#define CONFIG_GMII /* MII PHY management */ - -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define TSEC2_PHY_ADDR 4 -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC2_PHYIDX 0 -#endif - - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC1" - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Environment - */ -#if defined(CONFIG_NAND_U_BOOT) - #define CONFIG_ENV_IS_IN_NAND 1 - #define CONFIG_ENV_OFFSET (768 * 1024) - #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) - #define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) -#elif !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#else - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_FLASH - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_JFFS2 - -#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) \ - + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -#define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \ - | 0x20000000 /* reserved */ \ - | HRCWL_DDR_TO_SCB_CLK_2X1 \ - | HRCWL_CSB_TO_CLKIN_4X1 \ - | HRCWL_CORE_TO_CSB_2_5X1) - -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4) - -#define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \ - | HRCWH_PCI1_ARBITER_ENABLE \ - | HRCWH_CORE_ENABLE \ - | HRCWH_BOOTSEQ_DISABLE \ - | HRCWH_SW_WATCHDOG_DISABLE \ - | HRCWH_TSEC1M_IN_RGMII \ - | HRCWH_TSEC2M_IN_RGMII \ - | HRCWH_BIG_ENDIAN \ - | HRCWH_LALE_NORMAL) - -#ifdef CONFIG_NAND_LP -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \ - | HRCWH_FROM_0XFFF00100 \ - | HRCWH_ROM_LOC_NAND_LP_8BIT \ - | HRCWH_RL_EXT_NAND) -#else -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \ - | HRCWH_FROM_0XFFF00100 \ - | HRCWH_ROM_LOC_NAND_SP_8BIT \ - | HRCWH_RL_EXT_NAND) -#endif - -/* System IO Config */ -#define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \ - | SICRH_ETSEC2_C \ - | SICRH_ETSEC2_D \ - | SICRH_ETSEC2_E \ - | SICRH_ETSEC2_F \ - | SICRH_ETSEC2_G \ - | SICRH_TSOBI1 \ - | SICRH_TSOBI2) -#define CONFIG_SYS_SICRL (SICRL_LBC \ - | SICRL_USBDR_10 \ - | SICRL_ETSEC2_A) - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE \ - | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) - -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \ - | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI2 not supported on 8313 */ -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NETDEV "eth1" - -#define CONFIG_HOSTNAME simpc8313 -#define CONFIG_ROOTPATH "/tftpboot/" -#define CONFIG_BOOTFILE "/tftpboot/uImage" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot-nand.bin" -#define CONFIG_FDTFILE "simpc8313.dtb" - - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 500000 -#define CONFIG_BOOTDELAY 5 /* 5 second delay */ -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" CONFIG_NETDEV "\0" \ - "ethprime=TSEC1\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=ae0000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" \ - "console=ttyS0\0" \ - "setbootargs=setenv bootargs " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ - "load_uboot=tftp 100000 u-boot-nand.bin\0" \ - "burn_uboot=nand erase u-boot 80000; " \ - "nand write 100000 u-boot $filesize\0" \ - "update_uboot=run load_uboot;run burn_uboot\0" \ - "mtdids=nand0=nand0\0" \ - "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \ - "console=ttyS0,115200\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv rootdev /dev/nfs;" \ - "run setbootargs;" \ - "run setipargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv rootdev /dev/ram;" \ - "run setbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif /* __CONFIG_H */ diff --git a/include/configs/SM850.h b/include/configs/SM850.h deleted file mode 100644 index 5d48f8f8c4..0000000000 --- a/include/configs/SM850.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_SM850 1 /*...on a MPC850 Service Module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED not enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CONFIG_SYS_PLPRCR \ - ( (5-1)< - -#define CONFIG_CMD_IDE - -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_FLASH - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/*----------------------------------------------------------------------*/ -#define CONFIG_ETHADDR 00:D0:93:00:01:CB -#define CONFIG_IPADDR 10.0.0.98 -#define CONFIG_SERVERIP 10.0.0.1 -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000" -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* 0x00000040 */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00b0c0c0 */ -#define CONFIG_SYS_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800014 */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD101 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register - *----------------------------------------------------------------------- - */ -/* 0x00C3 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register - *----------------------------------------------------------------------- - */ -/* TIMEP=2 */ -#define CONFIG_SYS_RCCR 0x0200 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * SDSR - SDMA Status Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SDSR ((u_char)0x83) - -/*----------------------------------------------------------------------- - * SDMR - SDMA Mask Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SDMR ((u_char)0x00) - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* EPROMs are 512kb */ -#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -/* 16 bit, bank valid */ -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) - * - */ -#define SRAM_BASE 0xFE200000 /* SRAM bank */ -#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ - -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define PER8_BASE 0xFE000000 /* PER8 bank */ -#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ - -#define SHARC_BASE 0xFE400000 /* SHARC bank */ -#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ - -/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ -#define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM ) -#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ -#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) - -#define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ -#define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 ) -#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ -#define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC ) -#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MBMR_PTB 204 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MBMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h deleted file mode 100644 index e2b05de381..0000000000 --- a/include/configs/SXNI855T.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * U-Boot configuration for SIXNET SXNI855T CPU board. - * This board is based (loosely) on the Motorola FADS board, so this - * file is based (loosely) on config_FADS860T.h, see it for additional - * credits. - * - * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include - -#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */ - -/* The 855T is just a stripped 860T and needs code for 860, so for now - * at least define 860, 860T and 855T - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC855T 1 - -#define CONFIG_SYS_TEXT_BASE 0xF8000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_SCC1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_HAS_ETH1 - -/*----------------------------------------------------------------------- - * Definitions for status LED - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */ -# define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifdef DEV /* development (debug) settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF -#else /* production settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_ON -#endif - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram ip=off" - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 - -#define CONFIG_SYS_DISCOVER_PHY - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_DATE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save a little memory */ -#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SRAM_BASE 0xF4000000 -#define CONFIG_SYS_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */ - -#define CONFIG_SYS_FLASH_BASE 0xF8000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CONFIG_SYS_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */ -#define CONFIG_SYS_DFLASH_SIZE 0x00010000 - -#define CONFIG_SYS_FPGA_BASE 0xFF100000 /* Xilinx FPGA */ -#define CONFIG_SYS_FPGA_PROG 0xFF130000 /* Programming address */ -#define CONFIG_SYS_FPGA_SIZE 0x00040000 /* 256KiB usable */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks. - * AMD 29LV641 has 128 64K sectors in 8MB - */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the - * entire address space, we have to set the memory controller - * differently. Normally, you write the option register - * first, and then enable the chip select by writing the - * base register. For CS0, you must write the base register - * first, followed by the option register. - */ - -/* - * Init Memory Controller: - * - ********************************************************** - * BR0 and OR0 (FLASH) - */ - -#define CONFIG_SYS_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_FLASH_16BIT -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) -#define CONFIG_SYS_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */ - -/********************************************************** - * BR1 and OR1 (FPGA) - * These preliminary values are also the final values. - */ -#define CONFIG_SYS_OR_TIMING_FPGA \ - (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX) -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR1_PRELIM (((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA) - -/********************************************************** - * BR4 and OR4 (data flash) - * These preliminary values are also the final values. - */ -#define CONFIG_SYS_OR_TIMING_DFLASH \ - (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX) -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH) - -/********************************************************** - * BR5/6 and OR5/6 (Dual UART) - */ -#define CONFIG_SYS_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */ -#define CONFIG_SYS_DUARTA_BASE 0xff010000 -#define CONFIG_SYS_DUARTB_BASE 0xff018000 - -#define DUART_MBMR 0 -#define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI) -#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V) -#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE) -#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE) - -#define CONFIG_RESET_ON_PANIC /* reset if system panic() */ - -#define CONFIG_ENV_IS_IN_FLASH -#ifdef CONFIG_ENV_IS_IN_FLASH - /* environment is in FLASH */ - #define CONFIG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */ - #define CONFIG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */ - #define CONFIG_ENV_SECT_SIZE 0x00010000 - #define CONFIG_ENV_SIZE 0x00002000 -#else - /* environment is in EEPROM */ - #define CONFIG_ENV_IS_IN_EEPROM 1 - #define CONFIG_ENV_OFFSET 0 /* at beginning of EEPROM */ - #define CONFIG_ENV_SIZE 1024 /* Use only a part of it*/ -#endif - -#if 1 -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "delayabit" -#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h deleted file mode 100644 index ed8a32f7df..0000000000 --- a/include/configs/Sandpoint8240.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_SANDPOINT 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "net_self=tftp ${kernel_addr} ${bootfile};" \ - "tftp ${ramdisk_addr} ${ramdisk};" \ - "run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp ${kernel_addr} ${bootfile};" \ - "run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/SP8240/uImage\0" \ - "ramdisk=/tftpboot/SP8240/uRamdisk\0" \ - "kernel_addr=200000\0" \ - "ramdisk_addr=400000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - - -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE 0x00090000 -#define CONFIG_SYS_RAMBOOT 1 -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#if 0 -#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ -#else -#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ -#endif -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_ISA_MEM 0xFD000000 -#define CONFIG_SYS_ISA_IO 0xFE000000 - -#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SPEED 400000 - -#ifdef CONFIG_SYS_I2C_SOFT -#error "Soft I2C is not configured properly. Please review!" -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* write page size */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ - - -#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ -#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* - * NS87308 Configuration - */ -#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CONFIG_SYS_NS87308_BADDR_10 1 - -#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ - CONFIG_SYS_NS87308_UART2 | \ - CONFIG_SYS_NS87308_POWRMAN | \ - CONFIG_SYS_NS87308_RTC_APC ) - -#undef CONFIG_SYS_NS87308_PS2MOD - -#define CONFIG_SYS_NS87308_CS0_BASE 0x0076 -#define CONFIG_SYS_NS87308_CS0_CONF 0x30 -#define CONFIG_SYS_NS87308_CS1_BASE 0x0075 -#define CONFIG_SYS_NS87308_CS1_CONF 0x30 -#define CONFIG_SYS_NS87308_CS2_BASE 0x0074 -#define CONFIG_SYS_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 1843200 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1 - -#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ - -#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ - -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h deleted file mode 100644 index 97e8968243..0000000000 --- a/include/configs/Sandpoint8245.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_SANDPOINT 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NATSEMI -#define CONFIG_NS8382X - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE 0x00090000 -#define CONFIG_SYS_RAMBOOT 1 -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#if 0 -#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ -#else -#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ -#endif -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_ISA_MEM 0xFD000000 -#define CONFIG_SYS_ISA_IO 0xFE000000 - -#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#ifdef CONFIG_SYS_I2C_SOFT -#error "Soft I2C is not configured properly. Please review!" -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ -#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* - * NS87308 Configuration - */ -#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CONFIG_SYS_NS87308_BADDR_10 1 - -#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ - CONFIG_SYS_NS87308_UART2 | \ - CONFIG_SYS_NS87308_POWRMAN | \ - CONFIG_SYS_NS87308_RTC_APC ) - -#undef CONFIG_SYS_NS87308_PS2MOD - -#define CONFIG_SYS_NS87308_CS0_BASE 0x0076 -#define CONFIG_SYS_NS87308_CS0_CONF 0x30 -#define CONFIG_SYS_NS87308_CS1_BASE 0x0075 -#define CONFIG_SYS_NS87308_CS1_CONF 0x30 -#define CONFIG_SYS_NS87308_CS2_BASE 0x0074 -#define CONFIG_SYS_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX > 2) -#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 -#else -#define CONFIG_SYS_NS16550_CLK 1843200 -#endif - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ - -#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#if 0 -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ -#endif - -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h new file mode 100644 index 0000000000..3f02cede32 --- /dev/null +++ b/include/configs/T102xQDS.h @@ -0,0 +1,958 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T1024/T1023 QDS board configuration file + */ + +#ifndef __T1024QDS_H +#define __T1024QDS_H + +/* High Level Configuration Options */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_PHYS_64BIT +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +/* PCIe Boot - Master */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#endif +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#endif +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* PCIe Boot - Slave */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +/* Set 1M boot space for PCIe boot */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (256 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 +#endif + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#ifdef CONFIG_PHYS_64BIT +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) +#else +#define QIXIS_BASE_PHYS QIXIS_BASE +#endif +#define QIXIS_LBMAP_SWITCH 0x06 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Video */ +#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ +#define CONFIG_FSL_DIU_FB +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO +#endif +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 + +#define I2C_MUX_PCA_ADDR 0x77 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_DIU 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH7 0xF + +/* LDI/DVI Encoder for display */ +#define CONFIG_SYS_I2C_LDI_ADDR 0x38 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS3231 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#endif +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCIe + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_PCI_INDIRECT_BRIDGE + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* + *SATA + */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif + +/* + * SDHC + */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN + +#define CONFIG_QE +#define CONFIG_U_QE +/* Default address of microcode for the Linux FMan driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_QE_FW_ADDR 0x130000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_TERANETICS +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 +#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 +#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);"\ + "fff800000.flash:2m(uboot),9m(kernel),"\ + "128k(dtb),96m(fs),-(user);spife110000.0:" \ + "2m(uboot),9m(kernel),128k(dtb),-(user)" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ +#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 +#define __USB_PHY_TYPE utmi + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ + "ramdiskfile=t1024qds/ramdisk.uboot\0" \ + "fdtfile=t1024qds/t1024qds.dtb\0" \ + "netdev=eth0\0" \ + "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "fdtaddr=d00000\0" \ + "bdev=sda3\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#endif + +#endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h new file mode 100644 index 0000000000..bd40d6ac93 --- /dev/null +++ b/include/configs/T102xRDB.h @@ -0,0 +1,917 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T1024/T1023 RDB board configuration file + */ + +#ifndef __T1024RDB_H +#define __T1024RDB_H + +/* High Level Configuration Options */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_PHYS_64BIT +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +/* support deep sleep */ +#define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +/* PCIe Boot - Master */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#endif +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#endif +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* PCIe Boot - Slave */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +/* Set 1M boot space for PCIe boot */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 66660000 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (256 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 + +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Video */ +#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 + +#define I2C_MUX_PCA_ADDR 0x77 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ + + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCIe + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#ifdef CONFIG_PPC_T1040 +#define CONFIG_PCIE4 /* PCIE controler 4 */ +#endif +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_PCI_INDIRECT_BRIDGE + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000, to be removed */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#else +#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 +#endif +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif + +/* + * SDHC + */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN + +#define CONFIG_QE +#define CONFIG_U_QE +/* Default address of microcode for the Linux FMan driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_QE_FW_ADDR 0x130000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_AQUANTIA +#define RGMII_PHY1_ADDR 0x2 +#define RGMII_PHY2_ADDR 0x6 +#define SGMII_PHY1_ADDR 0x2 +#define FM1_10GEC1_PHY_ADDR 0x1 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.1" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ + "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ + "1m(uboot),5m(kernel),128k(dtb),-(user)" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_BDI + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ +#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 +#define __USB_PHY_TYPE utmi + +#ifdef CONFIG_PPC_T1024 +#define CONFIG_BOARDNAME "t1024rdb" +#else +#define CONFIG_BOARDNAME "t1023rdb" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ + "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ + __stringify(CONFIG_BOARDNAME) ".dtb\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ + "netdev=eth0\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "fdtaddr=c00000\0" \ + "bdev=sda3\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#endif + +#endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h new file mode 100644 index 0000000000..92f5f56718 --- /dev/null +++ b/include/configs/T1040QDS.h @@ -0,0 +1,856 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * T1040 QDS board configuration file + */ +#define CONFIG_T1040QDS +#define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + +/* support deep sleep */ +#define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ + +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1658) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif +#else /* CONFIG_SYS_NO_FLASH */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 +#endif +#define CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* + * TDM Definition + */ +#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) +#define QIXIS_LBMAP_SWITCH 0x06 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Video */ +#define CONFIG_FSL_DIU_FB +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 +#define CONFIG_SYS_FSL_I2C3_SPEED 50000 +#define CONFIG_SYS_FSL_I2C4_SPEED 50000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 + +#define I2C_MUX_PCA_ADDR 0x77 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ + + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_DIU 0xC + +/* LDI/DVI Encoder for display */ +#define CONFIG_SYS_I2C_LDI_ADDR 0x38 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS3231 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000 */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* +* USB +*/ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +#define CONFIG_QE +#define CONFIG_U_QE +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_TERANETICS +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x10 +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x11 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 + +#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* Enable VSC9953 L2 Switch driver */ +#define CONFIG_VSC9953 +#define CONFIG_VSC9953_CMD +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);"\ + "fff800000.flash:2m(uboot),9m(kernel),"\ + "128k(dtb),96m(fs),-(user);spife110000.0:" \ + "2m(uboot),9m(kernel),128k(dtb),-(user)" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t1040qds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t1040qds/t1040qds.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#define CONFIG_CMD_BLOB +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h new file mode 100644 index 0000000000..d47f1be685 --- /dev/null +++ b/include/configs/T104xRDB.h @@ -0,0 +1,914 @@ +/* ++ * Copyright 2014 Freescale Semiconductor, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * T104x RDB board configuration file + */ +#define CONFIG_T104xRDB +#define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_E500 /* BOOKE e500 family */ +#include + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#ifdef CONFIG_T1040RDB +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg +#endif +#ifdef CONFIG_T1042RDB_PI +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg +#endif +#ifdef CONFIG_T1042RDB +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg +#endif + +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + +/* support deep sleep */ +#define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SILENT_CONSOLE +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ + +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* + * TDM Definition + */ +#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#ifdef CONFIG_T1042RDB_PI +#define CPLD_DIU_SEL_DFP 0x80 +#endif + +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008044 +#if defined(CONFIG_NAND) +#define CONFIG_A008044_WORKAROUND +#endif +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#ifdef CONFIG_T1042RDB_PI +/* Video */ +#define CONFIG_FSL_DIU_FB + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_CFB_CONSOLE_ANSI +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR 0x70 +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#define I2C_MUX_CH_DEFAULT 0x8 +#endif + +#ifdef CONFIG_T1042RDB_PI +/* LDI/DVI Encoder for display */ +#define CONFIG_SYS_I2C_LDI_ADDR 0x38 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/*DVI encoder*/ +#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 +#endif + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000 */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* +* USB +*/ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#define CONFIG_QE +#define CONFIG_U_QE +#endif + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif + +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_QE_FW_ADDR 0x130000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 +#endif +#endif + + +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#endif + +#ifdef CONFIG_FMAN_ENET +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#endif +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 + +/* Enable VSC9953 L2 Switch driver on T1040 SoC */ +#ifdef CONFIG_T1040RDB +#define CONFIG_VSC9953 +#define CONFIG_VSC9953_CMD +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#endif + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#ifdef CONFIG_T1042RDB_PI +#define CONFIG_CMD_DATE +#endif +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);"\ + "fff800000.flash:2m(uboot),9m(kernel),"\ + "128k(dtb),96m(fs),-(user);spife110000.0:" \ + "2m(uboot),9m(kernel),128k(dtb),-(user)" +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi +#define RAMDISKFILE "t104xrdb/ramdisk.uboot" + +#ifdef CONFIG_T1040RDB +#define FDTFILE "t1040rdb/t1040rdb.dtb" +#elif defined(CONFIG_T1042RDB_PI) +#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" +#elif defined(CONFIG_T1042RDB) +#define FDTFILE "t1042rdb/t1042rdb.dtb" +#endif + +#ifdef CONFIG_FSL_DIU_FB +#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" +#else +#define DIU_ENVIRONMENT +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=" __stringify(FDTFILE) "\0" \ + "bdev=sda3\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#define CONFIG_CMD_BLOB +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h new file mode 100644 index 0000000000..ff6d2c1d37 --- /dev/null +++ b/include/configs/T208xQDS.h @@ -0,0 +1,955 @@ +/* + * Copyright 2011-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T2080/T2081 QDS board configuration file + */ + +#ifndef __T208xQDS_H +#define __T208xQDS_H + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CONFIG_MMC +#define CONFIG_SPI_FLASH +#define CONFIG_USB_EHCI +#if defined(CONFIG_PPC_T2080) +#define CONFIG_T2080QDS +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_T2081QDS +#endif + +/* High Level Configuration Options */ +#define CONFIG_PHYS_64BIT +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg +#if defined(CONFIG_PPC_T2080) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg +#endif + +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 +#define CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CTRL_INTLV_PREFERED cacheline + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RST_FORCE_MEM 0x1 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */\ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ +#define I2C_MUX_CH_DEFAULT 0x8 + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_IR36021_READ +/* The lowest and highest voltage allowed for T208xQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* + * eSPI - Enhanced SPI + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH_STMICRO +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#endif + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_NET_MULTI +#define CONFIG_E1000 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 18 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_TERANETICS +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define FM1_10GEC1_PHY_ADDR 0x3 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * SATA + */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* + * USB + */ +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ + "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ + "1m(uboot),5m(kernel),128k(dtb),-(user)" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_BDI + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t2080qds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t2080qds/t2080qds.dtb\0" \ + "bdev=sda3\0" + +/* + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#define CONFIG_CMD_BLOB +#undef CONFIG_CMD_USB +#endif + +#endif /* __T208xQDS_H */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h new file mode 100644 index 0000000000..db6b42ea0f --- /dev/null +++ b/include/configs/T208xRDB.h @@ -0,0 +1,897 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T2080 RDB/PCIe board configuration file + */ + +#ifndef __T2080RDB_H +#define __T2080RDB_H + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_T2080RDB +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CONFIG_MMC +#define CONFIG_SPI_FLASH +#define CONFIG_USB_EHCI +#define CONFIG_FSL_SATA_V2 + +/* High Level Configuration Options */ +#define CONFIG_PHYS_64BIT +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg + +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 66660000 +#define CONFIG_DDR_CLK_FREQ 133330000 + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CTRL_INTLV_PREFERED cacheline + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 + +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */\ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ +#define I2C_MUX_CH_DEFAULT 0x8 + + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* + * eSPI - Enhanced SPI + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ +#define CONFIG_NET_MULTI +#define CONFIG_E1000 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 18 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#define CONFIG_CORTINA_FW_ADDR 0x120000 + +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_CORTINA_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) + +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_CORTINA_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_CORTINA_FW_IN_REMOTE +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_CORTINA_FW_ADDR 0xFFE10000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_CORTINA_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_CORTINA_FW_ADDR 0xEFE00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_CORTINA +#define CONFIG_PHY_AQ1202 +#define CONFIG_PHY_REALTEK +#define CONFIG_CORTINA_FW_LENGTH 0x40000 +#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ +#define RGMII_PHY2_ADDR 0x02 +#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ +#define CORTINA_PHY_ADDR2 0x0d +#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ +#define FM1_10GEC4_PHY_ADDR 0x01 +#endif + + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * SATA + */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* + * USB + */ +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.1" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ + "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ + "1m(uboot),5m(kernel),128k(dtb),-(user)" +#endif + +/* + * Environment + */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_MII +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_BDI + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t2080rdb/t2080rdb.dtb\0" \ + "bdev=sda3\0" + +/* + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#define CONFIG_CMD_BLOB +#undef CONFIG_CMD_USB +#endif + +#endif /* __T2080RDB_H */ diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h new file mode 100644 index 0000000000..e8ba5d6b26 --- /dev/null +++ b/include/configs/T4240EMU.h @@ -0,0 +1,181 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T4240 EMU board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_T4240EMU +#define CONFIG_PHYS_64BIT + +#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_FSL_DDR_EMU 1 +#define CONFIG_SYS_FSL_NO_QIXIS 1 +#define CONFIG_SYS_FSL_NO_SERDES 1 + +#include "t4qds.h" + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_CACHE_FLUSH + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 +#define CONFIG_FSL_TBCLK_EXTRA_DIV 100 + +/* + * DDR Setup + */ +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_32 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x1)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ + FTIM2_NOR_TCH(0x0) | \ + FTIM2_NOR_TWP(0x1)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* I2C */ +#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */ +#define CONFIG_SYS_FSL_I2C2_SPEED 4000000 + +/* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 50 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_INTERLAKEN + +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +#define CONFIG_BOOTDELAY 0 + +/* + * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way + * interleaving. It can be cacheline, page, bank, superbank. + * See doc/README.fsl-ddr for details. + */ +#ifdef CONFIG_PPC_T4240 +#define CTRL_INTLV_PREFERED 3way_4KB +#else +#define CTRL_INTLV_PREFERED cacheline +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t4240emu/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t4240emu/t4240emu.dtb\0" \ + "bdev=sda3\0" + +/* + * For emulation this causes u-boot to jump to the start of the proof point + * app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_LINUX \ + "errata;" \ + "setenv othbootargs ignore_loglevel;" \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#endif /* __CONFIG_H */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 9ac7f69922..dd7d52f293 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -7,12 +7,649 @@ /* * T4240 QDS board configuration file */ +#ifndef __CONFIG_H +#define __CONFIG_H + #define CONFIG_T4240QDS #define CONFIG_PHYS_64BIT #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg +#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#else +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#endif +#endif /* CONFIG_RAMBOOT_PBL */ + +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#define CONFIG_DDR_ECC + #include "t4qds.h" + +#ifdef CONFIG_SYS_NO_FLASH +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_ENV_IS_NOWHERE +#endif +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RST_FORCE_MEM 0x1 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BRDCFG5 0x55 +#define QIXIS_MUX_SDHC 2 +#define QIXIS_MUX_SDHC_WIDTH8 1 +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + + +/* I2C */ +#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ + +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_MUX_CH_VSC3316_FS 0xc +#define I2C_MUX_CH_VSC3316_BS 0xd + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +/* VSC Crossbar switches */ +#define CONFIG_VSC_CROSSBAR +#define VSC3316_FSM_TX_ADDR 0x70 +#define VSC3316_FSM_RX_ADDR 0x71 + +/* + * RapidIO + */ + +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 50 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_TERANETICS +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#define FM1_10GEC1_PHY_ADDR 0x0 +#define FM1_10GEC2_PHY_ADDR 0x1 +#define FM2_10GEC1_PHY_ADDR 0x2 +#define FM2_10GEC2_PHY_ADDR 0x3 +#endif + + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_ESDHC_DETECT_QUIRK \ + (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ + IS_SVR_REV(get_svr(), 1, 0)) +#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ + (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) +#endif + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define __USB_PHY_TYPE utmi + +/* + * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way + * interleaving. It can be cacheline, page, bank, superbank. + * See doc/README.fsl-ddr for details. + */ +#ifdef CONFIG_PPC_T4240 +#define CTRL_INTLV_PREFERED 3way_4KB +#else +#define CTRL_INTLV_PREFERED cacheline +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t4240qds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t4240qds/t4240qds.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h new file mode 100644 index 0000000000..b644a6ce8b --- /dev/null +++ b/include/configs/T4240RDB.h @@ -0,0 +1,806 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T4240 RDB board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_T4240RDB +#define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg +#endif + +#define CONFIG_DDR_ECC + +#define CONFIG_CMD_REGINFO + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 + + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_IS_NOWHERE +#endif +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1658) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ 133333333 + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x54 +#define SPD_EEPROM_ADDRESS3 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 + +/* CPLD Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + + +/* I2C */ +#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ + +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_MUX_CH_VSC3316_FS 0xc +#define I2C_MUX_CH_VSC3316_BS 0xd + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 50 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_CORTINA +#define CONFIG_CORTINA_FW_ADDR 0xefe00000 +#define CONFIG_CORTINA_FW_LENGTH 0x40000 +#define CONFIG_PHY_TERANETICS +#define SGMII_PHY_ADDR1 0x0 +#define SGMII_PHY_ADDR2 0x1 +#define SGMII_PHY_ADDR3 0x2 +#define SGMII_PHY_ADDR4 0x3 +#define SGMII_PHY_ADDR5 0x4 +#define SGMII_PHY_ADDR6 0x5 +#define SGMII_PHY_ADDR7 0x6 +#define SGMII_PHY_ADDR8 0x7 +#define FM1_10GEC1_PHY_ADDR 0x10 +#define FM1_10GEC2_PHY_ADDR 0x11 +#define FM2_10GEC1_PHY_ADDR 0x12 +#define FM2_10GEC2_PHY_ADDR 0x13 +#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR +#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR +#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR +#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR +#endif + + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define __USB_PHY_TYPE utmi + +/* + * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way + * interleaving. It can be cacheline, page, bank, superbank. + * See doc/README.fsl-ddr for details. + */ +#ifdef CONFIG_PPC_T4240 +#define CTRL_INTLV_PREFERED 3way_4KB +#else +#define CTRL_INTLV_PREFERED cacheline +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t4240rdb/t4240rdb.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#ifdef CONFIG_SECURE_BOOT +/* Secure Boot target was not getting build for T4240 because of + * increased binary size. So the size is being reduced by removing USB + * which is anyways not used in Secure Environment. + */ +#undef CONFIG_CMD_USB +#define CONFIG_CMD_BLOB +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h deleted file mode 100644 index bce4176f9d..0000000000 --- a/include/configs/TASREG.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Configuation settings for the esd TASREG board. - * - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _TASREG_H -#define _TASREG_H - -#ifndef __ASSEMBLY__ -#include -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5249 /* define processor type */ - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 - -#undef CONFIG_WATCHDOG - -#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET - - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#define CONFIG_SYS_HZ 1000 - -/* - * Clock configuration: enable only one of the following options - */ - -#if 0 /* this setting will run the cpu at 11MHz */ -#define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */ -#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */ -#define CONFIG_SYS_CLK 11289600 /* PLL bypass */ -#endif - -#if 0 /* this setting will run the cpu at 70MHz */ -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */ -#define CONFIG_SYS_CLK 72185018 /* The next lower speed */ -#endif - -#if 1 /* this setting will run the cpu at 140MHz */ -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ -#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ -#endif - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 - -/*----------------------------------------------------------------------- - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -#if 0 /* push-pull */ -#define SDA 0x00800000 -#define SCL 0x00000008 -#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN)) -#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN)) -#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT)) -#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT)) -#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ)) -#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ)) -#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;} -#define I2C_READ ((IN1&SDA)?1:0) -#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;} -#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;} -#define I2C_DELAY {udelay(5);} -#define I2C_ACTIVE {DIR1|=SDA;} -#define I2C_TRISTATE {DIR1&=~SDA;} -#else /* open-collector */ -#define SDA 0x00800000 -#define SCL 0x00000008 -#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN)) -#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN)) -#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT)) -#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT)) -#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ)) -#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ)) -#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;} -#define I2C_READ ((IN1&SDA)?1:0) -#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;} -#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;} -#define I2C_DELAY {udelay(5);} -#define I2C_ACTIVE {DIR1|=SDA;} -#define I2C_TRISTATE {DIR1&=~SDA;} -#endif - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -/* - * The Catalyst CAT24WC32 has 32 byte page write mode using - * last 5 bits of the address - */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -#if 0 /* test-only */ -#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ -#endif - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ - CF_CACR_DBWE) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ - -/* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE 0xffc00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ -/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ - -/* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CS1_BASE 0xe0000000 -#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ - -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */ - -#endif /* _TASREG_H */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 1fa4714884..b4daedceea 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -5,7 +5,7 @@ * (C) Copyright 2004-2006 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,8 +16,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #define CONFIG_TB5200 1 /* ... on a TB5200 base board */ @@ -386,7 +385,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -410,8 +408,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Enable loopw command. */ diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h deleted file mode 100644 index 7f2b842993..0000000000 --- a/include/configs/TK885D.h +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ -#define CONFIG_TK885D 1 /* ...in a TK885D base board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethprime=FEC\0" \ - "ethact=FEC\0" \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/tk885d/uImage\0" \ - "u-boot=/tftpboot/tk885d/u-boot.bin\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -# define CONFIG_RTC_DS1337 1 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive - memory test.*/ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_6_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 128 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Network configuration - */ -#define CONFIG_FEC_ENET /* enable ethernet on FEC */ -#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ - -#define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */ - -/* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */ -#if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2)) -#define CONFIG_SYS_DISCOVER_PHY -#endif - -#ifndef CONFIG_SYS_DISCOVER_PHY -/* PHY addresses - hard wired in hardware */ -#define CONFIG_FEC1_PHY 1 -#define CONFIG_FEC2_PHY 2 -#endif - -#define CONFIG_MII_INIT 1 - -#define CONFIG_NET_RETRY_COUNT 3 -#define CONFIG_ETHPRIME "FEC" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h deleted file mode 100644 index 00056a33d4..0000000000 --- a/include/configs/TOP5200.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de - * - * TOP5200 differences from IceCube: - * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks - * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins - * 1 SDRAM/DDRAM Bank up to 256 MB - * local VPD I2C Bus is software driven and uses - * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL - * FLASH is re-located at 0xff000000 - * Internal regs are at 0xf0000000 - * Reset jumps to 0x00000100 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ -#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ - -/* - * allowed and functional CONFIG_SYS_TEXT_BASE values: - * 0xff000000 low boot at 0x00000100 (default board setting) - * 0xfff00000 high boot at 0xfff00100 (board needs modification) - * 0x00100000 RAM load and test - */ -#define CONFIG_SYS_TEXT_BASE 0xff000000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -# define CONFIG_PCI 1 -# define CONFIG_PCI_PNP 1 -# define CONFIG_PCI_SCAN_SHOW 1 -# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -# define CONFIG_PCI_MEM_BUS 0x40000000 -# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -# define CONFIG_PCI_MEM_SIZE 0x10000000 - -# define CONFIG_PCI_IO_BUS 0x50000000 -# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -# define CONFIG_PCI_IO_SIZE 0x01000000 - -#endif - -/* USB */ -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) - -# define CONFIG_USB_OHCI -# define CONFIG_USB_CLOCK 0x0001bbbb -# if defined (CONFIG_EVAL5200) -# define CONFIG_USB_CONFIG 0x00005100 -# else -# define CONFIG_USB_CONFIG 0x00001000 -# endif -# define CONFIG_DOS_PARTITION -# define CONFIG_USB_STORAGE - -#endif - -/* IDE */ -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -# define CONFIG_DOS_PARTITION -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_REGINFO - -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_USB -#define CONFIG_CMD_PCI -#endif - - -/* - * MUST be low boot - HIGHBOOT is not supported anymore - */ -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#else -# error "CONFIG_SYS_TEXT_BASE must be 0xff000000" -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -/* - * EEPROM configuration - */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x2000 - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ - -#if defined(CONFIG_SYS_I2C_SOFT) -# define CONFIG_SYS_I2C -# define CONFIG_SYS_I2C_SOFT_SPEED 100000 -# define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/**/ -# define SDA0 0x40 -# define SCL0 0x80 -# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00)) -# define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08)) -# define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c)) -# define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20)) -# define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04)) -# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);} -# define I2C_READ ((DVI0&SDA0)?1:0) -# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;} -# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;} -# define I2C_DELAY {udelay(5);} -# define I2C_ACTIVE {DDR0|=SDA0;} -# define I2C_TRISTATE {DDR0&=~SDA0;} - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_FACT_ADDR 0x57 -#endif - -#if defined (CONFIG_HARD_I2C) -# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -# define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_FACT_ADDR 0x54 -#endif - -/* - * Flash configuration, expect one 16 Megabyte Bank at most - */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0) - -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ - -/* - * DRAM configuration - will be read from VPD later... TODO! - */ -#if 0 -/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */ -#define CONFIG_SYS_DRAM_DDR 0 -#define CONFIG_SYS_DRAM_EMODE 0 -#define CONFIG_SYS_DRAM_MODE 0x008D -#define CONFIG_SYS_DRAM_CONTROL 0x514F0000 -#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00 -#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004 -#define CONFIG_SYS_DRAM_TAP_DEL 0x08 -#define CONFIG_SYS_DRAM_RAM_SIZE 0x19 -#endif -#if 1 -/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */ -#define CONFIG_SYS_DRAM_DDR 0 -#define CONFIG_SYS_DRAM_EMODE 0 -#define CONFIG_SYS_DRAM_MODE 0x00CD -#define CONFIG_SYS_DRAM_CONTROL 0x514F0000 -#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00 -#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004 -#define CONFIG_SYS_DRAM_TAP_DEL 0x08 -#define CONFIG_SYS_DRAM_RAM_SIZE 0x19 -#endif - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ -#define CONFIG_ENV_OFFSET 0x1000 -#define CONFIG_ENV_SIZE 0x0700 - -/* - * VPD settings - */ -#define CONFIG_SYS_FACT_OFFSET 0x1800 -#define CONFIG_SYS_FACT_SIZE 0x0800 - -/* - * Memory map - * - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 - */ -#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x1f -#define CONFIG_PHY_TYPE 0x79c874 -/* - * GPIO configuration: - * PSC1,2,3 predefined as UART - * PCI disabled - * Ethernet 100 with MD - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ - #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ - #define RTC(reg) (0xf0010000+reg) - /* setup CS2 for M48T08. Must MAP 64kB */ - #define CONFIG_SYS_CS2_START RTC(0) - #define CONFIG_SYS_CS2_SIZE 0x10000 - /* setup CS2 configuration register: */ - /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */ - /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */ - #define CONFIG_SYS_CS2_CFG 0x00047800 -#else - #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0x7f000000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET 1 -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h deleted file mode 100644 index 5c5ce84ff1..0000000000 --- a/include/configs/TOP860.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * (C) Copyright 2003 - * EMK Elektronik GmbH - * Reinhard Meyer - * - * Configuation settings for the TOP860 board. - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * TOP860 is a simple module: - * 16-bit wide FLASH on CS0 (2MB or more) - * 32-bit wide DRAM on CS2 (either 4MB or 16MB) - * FEC with Am79C874 100-Base-T and Fiber Optic - * Ports available, but we choose SMC1 for Console - * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set - * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock - * - * This config has been copied from MBX.h / MBX860T.h - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/*----------------------------------------------------------------------- - * CPU and BOARD type - */ -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_MPC860T 1 /* even better... an FEC! */ -#define CONFIG_TOP860 1 /* ...on a TOP860 module */ - -#define CONFIG_SYS_TEXT_BASE 0x80000000 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_IDENT_STRING " EMK TOP860" - -/*----------------------------------------------------------------------- - * CLOCK settings - */ -#define CONFIG_SYSCLK 49152000 -#define CONFIG_SYS_XTAL 32768 -#define CONFIG_EBDF 1 -#define CONFIG_COM 3 -#define CONFIG_RTC_MPC8xx - -/*----------------------------------------------------------------------- - * Physical memory map as defined by EMK - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */ -#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */ -#define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */ -#define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */ -#define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */ - -/*----------------------------------------------------------------------- - * derived values - */ -#define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL) -#define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK -#define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK -#define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF) -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_CFI - -/*----------------------------------------------------------------------- - * Command interpreter - */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_BAUDRATE 9600 - -/* - * Allow partial commands to be matched to uniqueness. - */ -#define CONFIG_SYS_MATCH_PARTIAL_CMD - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_BEDBUG - - -#define CONFIG_SOURCE 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 -#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ - - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */ - - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test Command - */ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Environment handler - * only the first 6k in EEPROM are available for user. Of that we use 256b - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ -#define CONFIG_ENV_OFFSET 0x1000 -#define CONFIG_ENV_SIZE 0x0700 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_FACT_OFFSET 0x1800 -#define CONFIG_SYS_FACT_SIZE 0x0800 -#define CONFIG_SYS_I2C_FACT_ADDR 0x57 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x2000 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/**/ -#define SDA 0x00010 -#define SCL 0x00020 -#define __I2C_DIR immr->im_cpm.cp_pbdir -#define __I2C_DAT immr->im_cpm.cp_pbdat -#define __I2C_PAR immr->im_cpm.cp_pbpar -#define __I2C_ODR immr->im_cpm.cp_pbodr -#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ - __I2C_ODR &= ~(SDA|SCL); \ - __I2C_DAT |= (SDA|SCL); \ - __I2C_DIR|=(SDA|SCL); } -#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) -#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } -#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } -#define I2C_DELAY { udelay(5); } -#define I2C_ACTIVE { __I2C_DIR |= SDA; } -#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/*----------------------------------------------------------------------- - * defines we need to get FEC running - */ -#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#define CONFIG_SYS_DISCOVER_PHY 1 -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 -#define CONFIG_PHY_ADDR 31 - -/*----------------------------------------------------------------------- - * adresses - */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x80000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -/*----------------------------------------------------------------------- - * Debug Enable Register - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 /* used in start.S */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set up PLPRCR (PLL, Low-Power, and Reset Control Register) - * 12 MF calculated Multiplication factor - * 4 0 0000 - * 1 SPLSS 0 System PLL lock status sticky - * 1 TEXPS 1 Timer expired status - * 1 0 0 - * 1 TMIST 0 Timers interrupt status - * 1 0 0 - * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL) - * 2 LPM 00 Low-power modes - * 1 CSR 0 Checkstop reset enable - * 1 LOLRE 0 Loss-of-lock reset enable - * 1 FIOPD 0 Force I/O pull down - * 5 0 00000 - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20)) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * set up SYPCR: - * 16 SWTC 0xffff Software watchdog timer count - * 8 BMT 0xff Bus monitor timing - * 1 BME 1 Bus monitor enable - * 3 0 000 - * 1 SWF 1 Software watchdog freeze - * 1 SWE 0/1 Software watchdog enable - * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET) - * 1 SWP 0/1 Software watchdog prescale (1=/2048) - */ -#if defined (CONFIG_WATCHDOG) - #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else - #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * set up SIUMCR - * 1 EARB 0 External arbitration - * 3 EARP 000 External arbitration request priority - * 4 0 0000 - * 1 DSHW 0 Data show cycles - * 2 DBGC 00 Debug pin configuration - * 2 DBPC 00 Debug port pins configuration - * 1 0 0 - * 1 FRC 0 FRZ pin configuration - * 1 DLK 0 Debug register lock - * 1 OPAR 0 Odd parity - * 1 PNCS 0 Parity enable for non memory controller regions - * 1 DPC 0 Data parity pins configuration - * 1 MPRE 0 Multiprocessor reservation enable - * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT) - * 1 AEME 0 Async external master enable - * 1 SEME 0 Sync external master enable - * 1 BSC 0 Byte strobe configuration - * 1 GB5E 0 GPL_B5 enable - * 1 B2DD 0 Bank 2 double drive - * 1 B3DD 0 Bank 3 double drive - * 4 0 0000 - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * set up SCCR (System Clock and Reset Control Register) - * 1 0 0 - * 2 COM 11 Clock output module (00=full, 01=half, 11=off) - * 3 0 000 - * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2) - * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512) - * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK) - * 1 CRQEN 0 CPM request enable - * 1 PRQEN 0 Power management request enable - * 2 0 00 - * 2 EBDF xx External bus division factor - * 2 0 00 - * 2 DFSYNC 00 Division factor for SYNCLK - * 2 DFBRG 00 Division factor for BRGCLK - * 3 DFNL 000 Division factor low frequency - * 3 DFNH 000 Division factor high frequency - * 5 0 00000 - */ -#define SCCR_MASK 0 -#ifdef CONFIG_EBDF - #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01) -#else - #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS) -#endif - -/*----------------------------------------------------------------------- - * Chip Select 0 - FLASH - *----------------------------------------------------------------------- - * Preliminary Values - */ -/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR) -#define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V ) - -/*----------------------------------------------------------------------- - * misc - *----------------------------------------------------------------------- - * - */ -/* - * Set the autoboot delay in seconds. A delay of -1 disables autoboot - */ -#define CONFIG_BOOTDELAY 5 - -/* - * Pass the clock frequency to the Linux kernel in units of MHz - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_PREBOOT \ - "echo;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Set default IP stuff just to get bootstrap entries into the - * environment so that we can source the full default environment. - */ -#define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.200 -#define CONFIG_IPADDR 10.0.4.111 - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 8a4dd358d8..cdccbef1f6 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -1,11 +1,11 @@ /* - * (C) Copyright 2003-2005 + * (C) Copyright 2003-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004-2006 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,10 +16,11 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: @@ -605,7 +606,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ @@ -632,8 +632,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Enable loopw command. */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 0221d16a44..0d5a2b96f1 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -127,7 +129,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -146,8 +147,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 514bbecd54..e765a03cfb 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -122,7 +124,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -141,8 +142,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h deleted file mode 100644 index 1b02cbbca7..0000000000 --- a/include/configs/TQM8260.h +++ /dev/null @@ -1,624 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Imported from global configuration: - * CONFIG_MPC8255 - * CONFIG_MPC8265 - * CONFIG_200MHz - * CONFIG_266MHz - * CONFIG_300MHz - * CONFIG_L2_CACHE - * CONFIG_BUSMODE_60x - */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ - -#if 0 -#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ -#else -#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ -#endif - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=tqm8260/uImage\0" \ - "kernel_addr=400C0000\0" \ - "ramdisk_addr=40240000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ -#if (CONFIG_TQM8260 <= 100) - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00020000) -#define I2C_TRISTATE (iop->pdir &= ~0x00020000) -#define I2C_READ ((iop->pdat & 0x00020000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#else - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ -# ifndef CONFIG_300MHz -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -# else -# define CONFIG_8260_CLKIN 83333000 /* in Hz */ -# endif -#endif /* CONFIG_MPC8255 */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH0_SIZE 32 -#define CONFIG_SYS_FLASH1_SIZE 32 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x08000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else /* ! MPC8255 && !MPC8265 */ -# if defined(CONFIG_266MHz) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -# elif defined(CONFIG_300MHz) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) -# else -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__) -# endif -#endif /* CONFIG_MPC8255 */ - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_BUSMODE_60x -#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ - BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ -#else -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - - /* SDRAM on TQM8260 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - -/* Bank 2 - Local bus SDRAM - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL - -#define SDRAM_BASE2_PRELIM 0x80000000 - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h deleted file mode 100644 index 3f586fbbc1..0000000000 --- a/include/configs/TQM8272.h +++ /dev/null @@ -1,739 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_TQM8272 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ -#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ - -#define STK82xx_150 1 /* on a STK82xx.150 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyCPM0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "hostname=tqm8272\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=$(consdev),$(baudrate)\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 300000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/tqm8272/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ - "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ - "cp.b 300000 40000000 40000;" \ - "setenv filesize;saveenv\0" \ - "cphwib=cp.b 4003fc00 33fc00 400\0" \ - "upd=run load cphwib update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_I2C 1 - -#if CONFIG_I2C -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_I2C_X - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -#else -#undef CONFIG_SYS_I2C -#undef CONFIG_HARD_I2C -#undef CONFIG_SYS_I2C_SOFT -#endif - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#define CONFIG_SYS_FCC_ETHERNET - -#if defined(CONFIG_SYS_FCC_ETHERNET) -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#else -#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#if STK82xx_150 -#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */ -#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */ -#endif - -#if STK82xx_100 -#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */ -#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */ -#endif - -#if 1 -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN -#else -#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;} - -#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;} -#endif - -#define MIIDELAY udelay(1) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#if CONFIG_I2C - #define CONFIG_CMD_I2C - #define CONFIG_CMD_DATE - #define CONFIG_CMD_DTT - #define CONFIG_CMD_EEPROM -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * CAN stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CAN_BASE 0x51000000 -#define CONFIG_SYS_CAN_SIZE 1 -#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMC |\ - BRx_V) - -#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI) - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */ - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_SYS_UPDATE_FLASH_SIZE - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND 0x20000 - -/* Where is the Hardwareinformation Block (from Monitor Sources) */ -#define MON_RES_LENGTH (0x0003FC00) -#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH) -#define HWIB_INFO_LEN 512 -#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) -#define CIB_INFO_LEN 512 - -#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND_CS_DIST 0x80 -#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20 -#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40 - -#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMB |\ - BRx_V) - -#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_8IDLE) - -#define CONFIG_SYS_NAND_SIZE 1 -#define CONFIG_SYS_NAND0_BASE 0x50000000 -#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) - -#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ - CONFIG_SYS_NAND2_BASE, \ - CONFIG_SYS_NAND3_BASE, \ - } - -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) -#define WRITE_NAND_UPM(d, adr, off) do \ -{ \ - volatile unsigned char *addr = (unsigned char *) (adr + off); \ - WRITE_NAND(d, addr); \ -} while(0) - -#endif /* CONFIG_CMD_NAND */ - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_PCI_SCAN_SHOW -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if 0 -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00) -#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00) -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 60x UPMB 8 bit NAND - * 3 60x UPMC 8 bit CAN - * - */ - -/* Initialize SDRAM - */ -#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ - -#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_8_CLK |\ - ORxG_TRLX) - -/* SDRAM on TQM8272 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 /* Low Value */ -/* #define CONFIG_SYS_PSRT 0x10 Fast Value */ -#define CONFIG_SYS_LSRT 0x20 /* Local Bus */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - -/* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - - -/* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A4 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ - PSDMR_SDAM_A17_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A4 |\ - PSDMR_RFRC_6_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ -#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ -#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ -#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ -#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ -#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ - -#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ -#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ -#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ -#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ -#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ -#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ - -#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ -#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ -#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ -#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ -#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ -#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ - -#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ -#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ -#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ -#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ -#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ -#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 07b5acb977..6762e3a57e 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -2,7 +2,7 @@ * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -16,7 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x specific */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_TQM834X 1 /* TQM834X board specific */ @@ -316,7 +315,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ @@ -334,7 +332,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -497,7 +494,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index fc854d9916..bbdc3f81fc 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -111,7 +113,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -130,8 +131,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 7bf685da05..5fc87f2138 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -112,7 +114,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -131,8 +132,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index f8bf75b713..589d168eba 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -115,7 +117,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -134,8 +135,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 37e3541d68..60acb564e8 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -145,7 +147,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -164,8 +165,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index a6e36b3de3..ebc5571632 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -114,7 +116,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -133,8 +134,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 78ecb47692..f4ce07f20e 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -115,7 +117,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -134,8 +135,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 379698a55f..97db519d53 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -20,6 +20,8 @@ #define CONFIG_MPC860 1 #define CONFIG_MPC860T 1 #define CONFIG_MPC862 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ @@ -118,7 +120,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -137,8 +138,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index ca7dd35fc0..25d60a74ef 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -20,6 +20,8 @@ #define CONFIG_MPC860 1 #define CONFIG_MPC860T 1 #define CONFIG_MPC862 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ @@ -118,7 +120,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -137,8 +138,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 9cf263cff6..928b879609 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -1,8 +1,8 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -19,6 +19,8 @@ #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -158,7 +160,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -177,8 +178,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 1f52efcf5b..598020c867 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -1,11 +1,11 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2006 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -22,6 +22,8 @@ #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 @@ -152,7 +154,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -173,8 +174,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Enable loopw command. */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h deleted file mode 100644 index 9d8819977e..0000000000 --- a/include/configs/Total5200.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Check valid setting of revision define. - * Total5100 and Total5200 Rev.1 are identical except for the processor. - */ -#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) -#error CONFIG_TOTAL5200_REV must be 1 or 2 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ -#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFE000000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Video console - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SED13806 -#define CONFIG_VIDEO_SED13806_16BPP - -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -/* #define CONFIG_VIDEO_BMP_LOGO */ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN - - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI - -#define CONFIG_CMD_BMP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB - - -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT \ - "setenv stdout serial;setenv stderr serial;" \ - "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if CONFIG_TOTAL5200_REV==2 -# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START } -#else -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#endif -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#if CONFIG_TOTAL5200_REV==1 -# define CONFIG_SYS_FLASH_BASE 0xFE000000 -# define CONFIG_SYS_FLASH_SIZE 0x02000000 -#elif CONFIG_TOTAL5200_REV==2 -# define CONFIG_SYS_FLASH_BASE 0xFA000000 -# define CONFIG_SYS_FLASH_SIZE 0x06000000 -#endif /* CONFIG_TOTAL5200_REV */ - -#if defined(CONFIG_SYS_LOWBOOT) -# define CONFIG_ENV_ADDR 0xFE040000 -#else /* CONFIG_SYS_LOWBOOT */ -# define CONFIG_ENV_ADDR 0xFFF40000 -#endif /* CONFIG_SYS_LOWBOOT */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */ -#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */ -#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */ -#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */ - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_SEVENWIRE -/* dummy, 7-wire FEC does not have phy address */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 - * Reserved 0 - * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 - * CS7: Interrupt GPIO on PSC3_5 0 - * CS8: Interrupt GPIO on PSC3_4 0 - * ATA: reset default, changed in ATA driver 00 - * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 - * IRDA: reset default, changed in IrDA driver 000 - * ETHER: reset default, changed in Ethernet driver 0000 - * PCI_DIS: reset default, changed in PCI driver 0 - * USB_SE: reset default, changed in USB driver 0 - * USB: reset default, changed in USB driver 00 - * PSC3: SPI and UART functionality without CD 1100 - * Reserved 0 - * PSC2: CAN1/2 001 - * Reserved 0 - * PSC1: reset default, changed in AC'97 driver 000 - * - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#if CONFIG_TOTAL5200_REV==1 -# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ -# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */ -#else -# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE) -# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ -# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE) -# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */ -# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */ -# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -#endif - -#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE -#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */ -#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ - -#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE -#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */ -#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ - -#if CONFIG_TOTAL5200_REV==1 -# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE -# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ -# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ -#else -# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE -# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ -# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ -#endif - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_ATA_CS_ON_I2C2 -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 20344937bd..94078f5481 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -20,14 +20,15 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ #define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ #define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* input clock of PLL (VCMA9 has 12MHz input clock) */ @@ -73,12 +74,12 @@ * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ +#define CONFIG_SYS_I2C /* we use the built-in I2C controller */ -#define CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */ +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 @@ -138,8 +139,6 @@ #if defined(CONFIG_CMD_KGDB) /* speed to run kgdb serial port */ #define CONFIG_KGDB_BAUDRATE 115200 -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* Miscellaneous configurable options */ @@ -162,7 +161,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x30800000 /* we configure PWM Timer 4 to 1ms 1000Hz */ -#define CONFIG_SYS_HZ 1000 /* support additional compression methods */ #define CONFIG_BZIP2 @@ -217,7 +215,6 @@ /* File system */ #define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_CMD_JFFS2 diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h deleted file mode 100644 index a1dad2b5bb..0000000000 --- a/include/configs/VOH405.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_VOH405 1 /* ...on a VOH405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF80000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */ - -#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CONFIG_SYS_RAMBOOT 1 -#else -# undef CONFIG_SYS_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#define CONFIG_SYS_EEPROM_WREN 1 - -/* CAT24WC32/64... */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (Epson VGA) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ -#define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * LCD Setup - */ - -#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ -#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ -#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ - -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20) - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ - -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_CTRL 0x000 - -/* FPGA Control Reg */ -#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 -#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO - */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555440 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0x777E0017 - -#define CONFIG_SYS_DUART_RST (0x80000000 >> 14) -#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) -#define CONFIG_SYS_IIC_ON (0x80000000 >> 8) -#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) -#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) -#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 1 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 5daf175863..e229256730 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -2,7 +2,7 @@ * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -16,10 +16,11 @@ * (easy to change) */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_VOM405 1 /* ...on a VOM405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -82,7 +83,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ @@ -119,8 +119,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h deleted file mode 100644 index c4f680bec7..0000000000 --- a/include/configs/VoVPN-GW.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* define cpu used */ -#define CONFIG_MPC8272 1 - -/* define busmode: 8260 */ -#undef CONFIG_BUSMODE_60x - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifdef CONFIG_CLKIN_66MHz -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ -#endif - -/* call board_early_init_f */ -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/* have misc_init_r() function */ -#define CONFIG_MISC_INIT_R 1 - -/* have reset_phy_r() function */ -#define CONFIG_RESET_PHY_R 1 - -/* have special reset function */ -#define CONFIG_HAVE_OWN_RESET 1 - -/* allow serial and ethaddr to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* watchdog disabled */ -#undef CONFIG_WATCHDOG - -/* include support for bzip2 compressed images */ -#undef CONFIG_BZIP2 - -/* status led */ -#undef CONFIG_STATUS_LED /* XXX jse */ - -/* vendor parameter protection */ -#define CONFIG_ENV_OVERWRITE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC -#undef CONFIG_CONS_ON_SCC -#undef CONFIG_CONS_NONE -#define CONFIG_CONS_INDEX 1 - -/* serial port default baudrate */ -#define CONFIG_BAUDRATE 115200 - -/* echo on for serial download */ -#define CONFIG_LOADS_ECHO 1 - -/* don't allow baudrate change */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE - -#ifdef CONFIG_ETHER_ON_FCC - -/* which SCC/FCC channel for ethernet */ -#define CONFIG_ETHER_INDEX 1 - -/* Marvell Switch SMI base addr */ -#define CONFIG_SYS_PHY_ADDR 0x10 - -/* FCC1 RMII REFCLK is CLK10 */ -#define CONFIG_SYS_CMXFCR_VALUE CMXFCR_TF1CS_CLK10 -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK) - -/* BDs and buffers on 60x bus */ -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 - -/* Local Protect, Full duplex, Flowcontrol, RMII */ -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\ - FCC_PSMR_FCE|FCC_PSMR_RMII) - -/* bit-bang MII PHY management */ -#define CONFIG_BITBANGMII - -#define MDIO_PORT 1 /* Port B */ - -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */ -#define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */ -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN -#define MIIDELAY udelay(1) - -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMLS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SOURCE - - -/* - * boot options & environment - */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "run flash_self" -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ -"clean_nv=erase fff20000 ffffffff\0" \ -"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \ -"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \ -"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \ -"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \ -"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ -"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \ -"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \ -"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \ -"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \ -"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \ -"fstype=cramfs\0" \ -"rootpath=/root_fs\0" \ -"uboot=PPC/u-boot.bin\0" \ -"kernel=PPC/uImage\0" \ -"kernel_addr=ffe00000\0" \ -"fs=PPC/root_fs\0" \ -"console=ttyS0\0" \ -"netdev=eth0\0" \ -"rootdev=31:3\0" \ -"ethaddr=00:09:4f:01:02:03\0" \ -"ipaddr=10.0.0.201\0" \ -"netmask=255.255.255.0\0" \ -"serverip=10.0.0.136\0" \ -"gatewayip=10.0.0.10\0" \ -"hostname=bastard\0" \ -"" - - -/* - * miscellaneous configurable options - */ - -/* undef to save memory */ -#define CONFIG_SYS_LONGHELP - -/* monitor command prompt */ -#define CONFIG_SYS_PROMPT "=> " - -/* console i/o buffer size */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif - -/* print buffer size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - -/* boot argument buffer size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 -/* 1 ... 15 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 -/* full featured memtest */ -#define CONFIG_SYS_ALT_MEMTEST - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* decrementer freq: 1 ms ticks */ -#define CONFIG_SYS_HZ 1000 - -/* configure flash */ -#define CONFIG_SYS_FLASH_BASE 0xff800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 64 -#define CONFIG_SYS_FLASH_SIZE 8 -#undef CONFIG_SYS_FLASH_16BIT -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 -#define CONFIG_SYS_FLASH_PROTECTION - -/* monitor in flash */ -#define CONFIG_SYS_MONITOR_OFFSET 0x00700000 - -/* environment in flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00020000) -#define CONFIG_ENV_SIZE 0x00020000 -#define CONFIG_ENV_SECT_SIZE 0x00020000 - -/* - * Initial memory map for linux - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* hard reset configuration words */ -#ifdef CONFIG_CLKIN_66MHz -#define CONFIG_SYS_HRCW_MASTER 0x04643050 -#else -#error NO HRCW FOR 100MHZ SPECIFIED !!! -#endif -#define CONFIG_SYS_HRCW_SLAVE1 0x00000000 -#define CONFIG_SYS_HRCW_SLAVE2 0x00000000 -#define CONFIG_SYS_HRCW_SLAVE3 0x00000000 -#define CONFIG_SYS_HRCW_SLAVE4 0x00000000 -#define CONFIG_SYS_HRCW_SLAVE5 0x00000000 -#define CONFIG_SYS_HRCW_SLAVE6 0x00000000 -#define CONFIG_SYS_HRCW_SLAVE7 0x00000000 - -/* internal memory mapped register */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/* definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE (32*1024*1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_FLASH (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET) -#define CONFIG_SYS_MONITOR_LEN 0x00020000 -#define CONFIG_SYS_MALLOC_LEN 0x00020000 - -/* cache configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* for MPC8260 */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of above */ -#endif - -/* - * HIDx - Hardware Implementation-dependent Registers - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|\ - HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/* RMR - reset mode register - turn on checkstop reset enable */ -#define CONFIG_SYS_RMR RMR_CSRE - -/* BCR - bus configuration */ -#define CONFIG_SYS_BCR 0x00000000 - -/* SIUMCR - siu module configuration */ -#define CONFIG_SYS_SIUMCR 0x4905c000 - -/* SYPCR - system protection control */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR 0xffffff87 -#else -#define CONFIG_SYS_SYPCR 0xffffff83 -#endif - -/* TMCNTSC - time counter status and control */ -/* clear interrupts XXX jse */ -/*#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\ - TMCNTSC_TCF|TMCNTSC_TCE) - -/* PISCR - periodic interrupt status and control */ -/* clear interrupts XXX jse */ -/*#define CONFIG_SYS_PISCR (PISCR_PS) */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/* SCCR - system clock control */ -#define CONFIG_SYS_SCCR 0x000001a9 - -/* RCCR - risc controller configuration */ -#define CONFIG_SYS_RCCR 0 - -/* - * MEMORY MAP - * ---------- - * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) - * CS1 - SDRAM 32MB/64Bit base=0x00000000 - * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000 - * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000 - * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000 - * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000 - * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored) - * x - IMMR 384KB base=0xf0000000 - */ -/* XXX jse 100MHz TODO */ -#define CONFIG_SYS_BR0_PRELIM 0xff800801 -#define CONFIG_SYS_OR0_PRELIM 0xff801e44 -#define CONFIG_SYS_BR1_PRELIM 0x00000041 -#define CONFIG_SYS_OR1_PRELIM 0xfe002ec0 -#if 1 -#define CONFIG_SYS_BR2_PRELIM 0xf0101001 -#define CONFIG_SYS_OR2_PRELIM 0xfff00ef4 -#define CONFIG_SYS_BR3_PRELIM 0xf0201001 -#define CONFIG_SYS_OR3_PRELIM 0xfff00ef4 -#define CONFIG_SYS_BR4_PRELIM 0xf0301001 -#define CONFIG_SYS_OR4_PRELIM 0xfff00ef4 -#define CONFIG_SYS_BR5_PRELIM 0xf0401001 -#define CONFIG_SYS_OR5_PRELIM 0xfff00ef4 -#else -#define CONFIG_SYS_BR2_PRELIM 0xf0101081 -#define CONFIG_SYS_OR2_PRELIM 0xfff00104 -#define CONFIG_SYS_BR3_PRELIM 0xf0201081 -#define CONFIG_SYS_OR3_PRELIM 0xfff00104 -#define CONFIG_SYS_BR4_PRELIM 0xf0301081 -#define CONFIG_SYS_OR4_PRELIM 0xfff00104 -#define CONFIG_SYS_BR5_PRELIM 0xf0401081 -#define CONFIG_SYS_OR5_PRELIM 0xfff00104 -#endif -#define CONFIG_SYS_BR7_PRELIM 0xf0500881 -#define CONFIG_SYS_OR7_PRELIM 0xffff8104 -#define CONFIG_SYS_MPTPR 0x2700 -#define CONFIG_SYS_PSDMR 0x822a2452 /* optimal */ -/*#define CONFIG_SYS_PSDMR 0x822a48a3 */ /* relaxed */ -#define CONFIG_SYS_PSRT 0x1a - -/* "bad" address */ -#define CONFIG_SYS_RESET_ADDRESS 0x40000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 51cfcf6e21..895ad4611b 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ #define CONFIG_W7OLMC 1 /* ...specifically an LMC */ @@ -126,8 +125,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -303,7 +300,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 6769c0d806..2a38116dd1 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ #define CONFIG_W7OLMG 1 /* ...specifically an LMG */ @@ -134,8 +133,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -306,7 +303,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h deleted file mode 100644 index f38d90ee3f..0000000000 --- a/include/configs/WUH405.h +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IDENT_STRING " $Name: $" - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_WUH405 1 /* ...on a WUH405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define DUART2_BA 0xF0000410 /* DUART Base Address */ -#define DUART3_BA 0xF0000418 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 - -#define CONFIG_SYS_DUART_RST (0x80000000 >> 14) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h deleted file mode 100644 index 2160694df2..0000000000 --- a/include/configs/ZPC1900.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (C) 2003-2005 Arabella Software Ltd. - * Yuli Barcohen - * - * U-Boot configuration for Zephyr Engineering ZPC.1900 board. - * This port was developed and tested on Revision C board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CPU_ID_STR "MPC8265" -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 2) -/* - * - Rx clock is CLK13 - * - Tx clock is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Full duplex - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp" - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 64 - -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_LSDRAM_BASE 0xFC000000 -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_BCSR 0xFEA00000 -#define CONFIG_SYS_EEPROM 0xFEB00000 -#define CONFIG_SYS_FLSIMM_BASE 0xFF000000 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE } - -#define BCSR_PCI_MODE 0x01 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\ - HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\ - HRCW_MODCK_H0111 \ - ) /* 0x16848207 */ -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM) -#define CONFIG_ENV_IS_IN_NVRAM 1 -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH -# define CONFIG_ENV_SECT_SIZE 0x10000 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#else -# define CONFIG_ENV_ADDR (CONFIG_SYS_EEPROM + 0x400) -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_SYS_NVRAM_ACCESS_ROUTINE -#endif - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT (HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x42200000 -#define CONFIG_SYS_SYPCR 0xFFFFFFC3 -#define CONFIG_SYS_BCR 0x90000000 -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -#define CONFIG_SYS_RMR RMR_CSRE -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CONFIG_SYS_RCCR 0 - -#define CONFIG_SYS_PSDMR /* 0x834DA43B */0x014DA43A -#define CONFIG_SYS_PSRT 0x0F/* 0x0C */ -#define CONFIG_SYS_LSDMR 0x0085A562 -#define CONFIG_SYS_LSRT 0x0F -#define CONFIG_SYS_MPTPR 0x4000 - -#define CONFIG_SYS_PSDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041) -#define CONFIG_SYS_PSDRAM_OR 0xFC0028C0 -#define CONFIG_SYS_LSDRAM_BR (CONFIG_SYS_LSDRAM_BASE | 0x00001861) -#define CONFIG_SYS_LSDRAM_OR 0xFF803480 - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00000801) -#define CONFIG_SYS_OR0_PRELIM 0xFFE00856 -#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_EEPROM | 0x00000801) -#define CONFIG_SYS_OR5_PRELIM 0xFFFF03F6 -#define CONFIG_SYS_BR6_PRELIM (CONFIG_SYS_FLSIMM_BASE | 0x00001801) -#define CONFIG_SYS_OR6_PRELIM 0xFF000856 -#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801) -#define CONFIG_SYS_OR7_PRELIM 0xFFFF83F6 - -#define CONFIG_SYS_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h deleted file mode 100644 index ec86023974..0000000000 --- a/include/configs/ZUMA.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_ETHER_PORT_MII /* use two MII ports */ -#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */ - -#ifndef __ASSEMBLY__ -#include -#endif - -#include "../board/evb64260/local.h" - -#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */ - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ - -#define CONFIG_ECC /* enable ECC support */ - -#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SYS_BOARD_ASM_INIT - -#define CONFIG_SYS_BOARD_NAME "Zuma APv2" - -#define CONFIG_SYS_HUSH_PARSER - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC - -#define CONFIG_MPSC_PORT 0 - - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND \ - "tftpboot && " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none panic=5 && bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MII /* enable MII commands */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" -#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" -*/ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ - -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CONFIG_SYS_GT_REGS 0xf8000000 /* later mapped GT_REGS */ -#define CONFIG_SYS_DEV_BASE 0xf0000000 -#define CONFIG_SYS_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ -#define CONFIG_SYS_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */ -#define CONFIG_SYS_DEV2_SIZE _8M /* unused */ -#define CONFIG_SYS_DEV3_SIZE _8M /* unused */ - -#define CONFIG_SYS_DEV0_PAR 0xc498243c - /* c 4 9 8 2 4 3 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */ - /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */ - -#define CONFIG_SYS_DEV1_PAR 0xc01b6ac5 - /* c 0 1 b 6 a c 5 */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */ - /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ - - -#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c - -#define CONFIG_SYS_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ -#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ -#define CONFIG_SYS_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ -#define CONFIG_SYS_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */ - /* GPP[27:24] (27 is int4, rest are GPP) */ - -#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */ - -#define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 1 - pci use buffer 0,0 (pci1->0 pci0->0) - cpu use buffer 1 (R*18) - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 111001 00 111 0 0 00 1 */ - - /* refresh count=0x200 - phy interleave disable (by default, - set later by dram config..) - virt interleave enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) - -/*----------------------------------------------------------------------- - * PCI stuff - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -#define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#ifdef CONFIG_750CX -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*------------------------------------------------------------------------ - * Real time clock - */ -#define CONFIG_RTC_DS1302 - - -/*------------------------------------------------------------------------ - * Galileo I2C driver - */ -#define CONFIG_GT_I2C - -#endif /* __CONFIG_H */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index bcb7ab47ba..0d3cf369b6 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -37,7 +37,6 @@ /* * Timer */ -#define CONFIG_SYS_HZ 1000 /* timer ticks per second */ /* * Real Time Clock diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index b18a3fa643..d23d2c4cc5 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -13,8 +13,9 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_A3M071 /* ... on A3M071 board */ +#define CONFIG_A3M071 /* A3M071 board */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ @@ -31,6 +32,8 @@ #define CONFIG_HOSTNAME a3m071 #endif +#define CONFIG_BOOTCOUNT_LIMIT + /* * Serial console configuration */ @@ -57,6 +60,7 @@ #define CONFIG_BOOTP_SERVERIP #define CONFIG_NET_RETRY_COUNT 3 #define CONFIG_CMD_LINK_LOCAL +#define CONFIG_LIB_RAND #define CONFIG_NETCONSOLE #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_CMD_PING @@ -65,7 +69,8 @@ #define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=fc000000.flash" #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \ - "256k(env)," \ + "128k(env1)," \ + "128k(env2)," \ "128k(hwinfo)," \ "1M(nvramsim)," \ "128k(dtb)," \ @@ -73,7 +78,9 @@ "128k(sysinfo)," \ "7552k(root)," \ "4M(app)," \ - "13568k(data)" + "5376k(data)," \ + "8M(install)" + #define CONFIG_LZO /* needed for UBI */ #define CONFIG_RBTREE /* needed for UBI */ #define CONFIG_CMD_MTDPARTS @@ -240,7 +247,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER @@ -260,7 +266,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00100000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_LOOPW #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ @@ -367,7 +372,7 @@ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock7 " \ + "mtdargs=setenv bootargs root=/dev/mtdblock8 " \ "rootfstype=squashfs,jffs2\0" \ "addhost=setenv bootargs ${bootargs} " \ "hostname=${hostname}\0" \ @@ -376,22 +381,32 @@ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} " \ "console=${consoledev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty addhost;" \ + "flash_nfs=run nfsargs addip addtty addmtd addhost;" \ "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_mtd=run mtdargs addip addtty addhost;" \ + "flash_mtd=run mtdargs addip addtty addmtd addhost;" \ "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty addhost;" \ + "flash_self=run ramargs addip addtty addmtd addhost;" \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty addhost;" \ + "run nfsargs addip addtty addmtd addhost;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ "/u-boot-img.bin\0" \ - "update=protect off fc000000 fc07ffff; " \ + "update=protect off fc000000 fc07ffff;" \ "era fc000000 fc07ffff;" \ "cp.b ${loadaddr} fc000000 ${filesize}\0" \ "upd=run load;run update\0" \ + "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \ + "run mtdargs addip addtty addmtd addhost;" \ + "fdt addr 1800000;fdt boardsetup;fdt chosen;" \ + "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \ + "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \ + "erase fc200000 fc6fffff;" \ + "cp.b 1000000 fc200000 ${filesize}" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_mtd" @@ -399,13 +414,10 @@ /* * SPL related defines */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NOR_SUPPORT #define CONFIG_SPL_TEXT_BASE 0xfc000000 -#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx" -#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ #define CONFIG_SPL_SERIAL_SUPPORT diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index d243bc12c0..3c6765560e 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -5,7 +5,7 @@ * (C) Copyright 2010 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,10 +16,11 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_A4M072 1 /* ... on A4M072 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0xFE000000 @@ -271,7 +272,6 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -286,8 +286,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if defined(CONFIG_CMD_KGDB) # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index a2090dac86..54b7028c56 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_AC14XX 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the ifm AC14xx board: * @@ -27,7 +30,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 @@ -290,9 +292,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE @@ -440,9 +441,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* decrementer freq: 1ms ticks */ -#define CONFIG_SYS_HZ 1000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -474,7 +472,6 @@ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/acadia.h b/include/configs/acadia.h index f79706e1d2..4dd5720d2f 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -16,7 +16,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_ACADIA 1 /* Board is Acadia */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EZ 1 /* Specifc 405EZ support*/ #ifndef CONFIG_SYS_TEXT_BASE @@ -83,17 +82,11 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -107,16 +100,6 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#else -/* - * No NOR-flash on Acadia when NAND-booting. We need to undef the - * NOR device-tree fixup code as well, since flash_info is not defined - * in this case. - */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE -#endif - #ifdef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) @@ -127,61 +110,6 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * RAM (CRAM) *----------------------------------------------------------------------*/ @@ -220,7 +148,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ "kozio=bootm ffc60000\0" \ @@ -243,14 +170,6 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_USB -/* - * No NOR on Acadia when NAND-booting - */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#endif - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -261,7 +180,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_NAND_CS 3 /* Memory Bank 0 (Flash) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x03337200 @@ -279,24 +197,6 @@ /* Memory Bank 2 (CRAM) initialization */ #define CONFIG_SYS_EBC_PB2AP 0x030400c0 #define CONFIG_SYS_EBC_PB2CR 0x020bc000 -#else -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) - -/* - * When NAND-booting the CRAM EBC setup must be done in sync mode, since the - * NAND-SPL already initialized the CRAM and EBC to sync mode. - */ -/* Memory Bank 1 (CRAM) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x9C0201C0 -#define CONFIG_SYS_EBC_PB1CR 0x000bc000 - -/* Memory Bank 2 (CRAM) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x9C0201C0 -#define CONFIG_SYS_EBC_PB2CR 0x020bc000 -#endif /* Memory Bank 4 (CPLD) initialization */ #define CONFIG_SYS_EBC_PB4AP 0x04006000 diff --git a/include/configs/actux1.h b/include/configs/actux1.h deleted file mode 100644 index 33669c2e83..0000000000 --- a/include/configs/actux1.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-1 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX1 1 - -#define CONFIG_MACH_TYPE 1479 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -/* which serial port to use */ -# define CONFIG_KGDB_SER_INDEX 1 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 -#define CONFIG_SYS_HZ 1000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113842 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#ifdef CONFIG_RAM_32MB -# define CONFIG_SYS_SDR_CONFIG 0x18 -# define PHYS_SDRAM_1_SIZE 0x02000000 -# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -# define CONFIG_SYS_DRAM_SIZE 0x02000000 -#else /* 16MB SDRAM */ -# define CONFIG_SYS_SDR_CONFIG 0x3A -# define PHYS_SDRAM_1_SIZE 0x01000000 -# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -# define CONFIG_SYS_DRAM_SIZE 0x01000000 -#endif - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#ifdef CONFIG_FLASH2X2 -# define CONFIG_SYS_MAX_FLASH_BANKS 2 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 40 -# define PHYS_FLASH_1 0x50000000 -# define PHYS_FLASH_2 0x50200000 -# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } -#endif -#ifdef CONFIG_FLASH1X8 -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 140 -# define PHYS_FLASH_1 0x50000000 -# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#endif - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0 -/* NPE1 PHY address (HW Release E only) */ -#define CONFIG_PHY1_ADDR 1 -/* MII PHY management */ -#define CONFIG_MII 1 -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 - -#define CONFIG_HAS_ETH1 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux1/uImage\0" \ - "rootfile=actux1/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux1/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/actux2.h b/include/configs/actux2.h deleted file mode 100644 index 533f46976a..0000000000 --- a/include/configs/actux2.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX2 1 - -#define CONFIG_MACH_TYPE 1480 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#undef CONFIG_CMD_PCI -#undef CONFIG_PCI - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -/* which serial port to use */ -# define CONFIG_KGDB_SER_INDEX 1 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 -#define CONFIG_SYS_HZ 1000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113042 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 16MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x3A -#define PHYS_SDRAM_1_SIZE 0x01000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x01000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x00 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux2/uImage\0" \ - "rootfile=actux2/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux2/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/actux3.h b/include/configs/actux3.h deleted file mode 100644 index 76b5efd8a1..0000000000 --- a/include/configs/actux3.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-3 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX3 1 - -#define CONFIG_MACH_TYPE 1481 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -/* which serial port to use */ -# define CONFIG_KGDB_SER_INDEX 1 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 -#define CONFIG_SYS_HZ 1000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113442 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 16MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x3A -#define PHYS_SDRAM_1_SIZE 0x01000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x01000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x10 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux3/uImage\0" \ - "rootfile=actux3/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux3/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/actux4.h b/include/configs/actux4.h deleted file mode 100644 index 1df0a7caab..0000000000 --- a/include/configs/actux4.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the AcTux-4 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX4 1 - -#define CONFIG_MACH_TYPE 1532 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration */ -#include - -#define CONFIG_CMD_ELF - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -/* which serial port to use */ -# define CONFIG_KGDB_SER_INDEX 1 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66000000 -#define CONFIG_SYS_HZ 1000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113003 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 32MB SDRAM */ -#define CONFIG_SYS_SDR_CONFIG 0x18 -#define PHYS_SDRAM_1_SIZE 0x02000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE 0x02000000 - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -/* max # of sectors per chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 70 -#define PHYS_FLASH_1 0x50000000 -#define PHYS_FLASH_2 0x51000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (252 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 258048 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* board provides its own flash_init code */ -#define CONFIG_FLASH_CFI_LEGACY 1 -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* SST 39VF020 etc. support */ -#define CONFIG_SYS_FLASH_LEGACY_256Kx8 1 - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0x1C -/* MII PHY management */ -#define CONFIG_MII 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* environment organization: one complete 4k flash sector */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=51000000\0" \ - "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \ - "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \ - "kerneladdr=51020000\0" \ - "kernelfile=actux4/uImage\0" \ - "rootfile=actux4/rootfs\0" \ - "rootaddr=51160000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux4/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 5003efff;" \ - " erase 50000000 +${filesize}\0" \ - "writeboot=cp.b 10000 50000000 ${filesize}\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h index 81f71b9b72..e318c7543f 100644 --- a/include/configs/adp-ag101.h +++ b/include/configs/adp-ag101.h @@ -40,12 +40,6 @@ /* * Timer */ - -/* - * According to the discussion in u-boot mailing list before, - * CONFIG_SYS_HZ at 1000 is mandatory. - */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK_FREQ 48000000 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ @@ -144,11 +138,6 @@ /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ #define CONFIG_SYS_MALLOC_LEN (512 << 10) -/* - * size in bytes reserved for initial data - */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 48afbf4467..24904b0b7c 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -40,12 +40,6 @@ /* * Timer */ - -/* - * According to the discussion in u-boot mailing list before, - * CONFIG_SYS_HZ at 1000 is mandatory. - */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK_FREQ 39062500 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ @@ -144,11 +138,6 @@ /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ #define CONFIG_SYS_MALLOC_LEN (512 << 10) -/* - * size in bytes reserved for initial data - */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h index 681dfa251c..39f7a3cd46 100644 --- a/include/configs/adp-ag102.h +++ b/include/configs/adp-ag102.h @@ -32,12 +32,6 @@ /* * Timer */ - -/* - * According to the discussion in u-boot mailing list before, - * CONFIG_SYS_HZ at 1000 is mandatory. - */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK_FREQ (66000000 * 2) #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ @@ -209,11 +203,6 @@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -/* - * size in bytes reserved for initial data -*/ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - /* * AHB Controller configuration */ diff --git a/include/configs/aev.h b/include/configs/aev.h index 6c0b034dcc..2dffcfbed3 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -5,7 +5,7 @@ * (C) Copyright 2004-2005 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,8 +16,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ @@ -320,7 +319,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -338,8 +336,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if defined(CONFIG_CMD_KGDB) # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index be2f207055..932a3090b4 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -17,7 +17,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_HZ 1000 #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO @@ -78,7 +77,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ @@ -107,11 +105,12 @@ /* Ethernet */ #define CONFIG_MACB #define CONFIG_RESET_PHY_R - +#define CONFIG_AT91_WANTS_COMMON_PHY #define CONFIG_NET_RETRY_COUNT 20 /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 5431b098c5..2782e559f5 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -2,7 +2,7 @@ * (C) Copyright 2006-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -14,7 +14,6 @@ #define CONFIG_ALPR 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ @@ -148,7 +147,7 @@ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ + "bootm\0" \ "net_nfs_fdt=tftp 200000 ${bootfile};" \ "tftp ${fdt_addr} ${fdt_file};" \ "run nfsargs addip addtty;" \ @@ -223,6 +222,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_I2C #undef CONFIG_CMD_LOADB #undef CONFIG_CMD_LOADS @@ -238,7 +238,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -255,8 +254,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ @@ -327,6 +324,8 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \ CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 } #define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup @@ -350,7 +349,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* pass open firmware flat tree */ diff --git a/include/configs/alt.h b/include/configs/alt.h new file mode 100644 index 0000000000..58eac31358 --- /dev/null +++ b/include/configs/alt.h @@ -0,0 +1,117 @@ +/* + * include/configs/alt.h + * This file is alt board configuration. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ALT_H +#define __ALT_H + +#undef DEBUG +#define CONFIG_R8A7794 +#define CONFIG_RMOBILE_BOARD_STRING "Alt" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF2 +#define CONFIG_SCIF_USE_EXT_CLK + +/* FLASH */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* MMCIF */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_SH_MMCIF +#define CONFIG_SH_MMCIF_ADDR 0xee200000 +#define CONFIG_SH_MMCIF_CLK 48000000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF2 */ +#define CONFIG_SMSTP7_ENA 0x00080000 + +#endif /* __ALT_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c5a6d4b315..f1c270c939 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -16,80 +16,83 @@ #ifndef __CONFIG_AM335X_EVM_H #define __CONFIG_AM335X_EVM_H -#define CONFIG_AM33XX -#define CONFIG_OMAP +#include -#include +#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_FIT +# define CONFIG_FIT +#endif +# define CONFIG_TIMESTAMP +# define CONFIG_LZO +#endif -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) +#define CONFIG_SYS_BOOTM_LEN (16 << 20) -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot# " -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_SYS_NO_FLASH #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM +#define CONFIG_BOARD_LATE_INIT -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) -#define CONFIG_SYS_CACHELINE_SIZE 64 +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/ti/am335x/u-boot.lds" -/* commands to include */ -#include +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_CMD_ASKENV -#define CONFIG_VERSION_VARIABLE +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} u-boot-spl-os; " \ + "nand read ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#else +#define NANDARGS "" +#endif -/* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "fdt_high=0xffffffff\0" \ - "rdaddr=0x81000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ + "boot_fdt=try\0" \ + "bootpart=0:2\0" \ "bootdir=/boot\0" \ - "bootfile=uImage\0" \ + "bootfile=zImage\0" \ "fdtfile=undefined\0" \ "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ "optargs=\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "dfu_alt_info_mmc=" DFU_ALT_INFO_MMC "\0" \ - "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ - "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ - "bootpart=0:2\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandsrcaddr=0x280000\0" \ - "nandimgsize=0x500000\0" \ "rootpath=/export/rootfs\0" \ "nfsopts=nolock\0" \ "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ "::off\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ "spiroot=/dev/mtdblock4 rw\0" \ "spirootfstype=jffs2\0" \ "spisrcaddr=0xe0000\0" \ @@ -105,38 +108,67 @@ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ "ip=dhcp\0" \ "bootenv=uEnv.txt\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ + "env import -t -r $loadaddr $filesize\0" \ "ramargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${ramroot} " \ "rootfstype=${ramrootfstype}\0" \ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ - "bootm ${loadaddr}\0" \ + "mmcloados=run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootscript; then " \ + "run bootscript;" \ + "else " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run mmcloados;" \ + "fi;" \ + "fi ;" \ + "fi;\0" \ "spiboot=echo Booting from spi ...; " \ "run spiargs; " \ "sf probe ${spibusno}:0; " \ "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr}\0" \ "netboot=echo Booting from network ...; " \ "setenv autoload no; " \ "dhcp; " \ "tftp ${loadaddr} ${bootfile}; " \ "tftp ${fdtaddr} ${fdtfile}; " \ "run netargs; " \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ - "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ "findfdt="\ "if test $board_name = A335BONE; then " \ "setenv fdtfile am335x-bone.dtb; fi; " \ @@ -147,239 +179,66 @@ "if test $board_name = A335X_SK; then " \ "setenv fdtfile am335x-evmsk.dtb; fi; " \ "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" + "echo WARNING: Could not determine device tree to use; fi; \0" \ + NANDARGS \ + DFUARGS #endif #define CONFIG_BOOTCOMMAND \ "run findfdt; " \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run loadfdt;" \ - "run mmcboot;" \ - "fi;" \ - "else " \ - "run nandboot;" \ - "fi;" \ - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_CMD_ECHO - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * memtest works on 8 MB in DRAM after skipping 32MB from - * start addr of ram disk - */ -#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + (8 * 1024 * 1024)) - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_FS_GENERIC - -#define CONFIG_SPI -#define CONFIG_OMAP3_SPI -#define CONFIG_MTD_DEVICE -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED (24000000) - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USB_GADGET -#define CONFIG_USBDOWNLOAD_GADGET - -/* USB TI's IDs */ -#define CONFIG_USBD_HS -#define CONFIG_G_DNL_VENDOR_NUM 0x0403 -#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 -#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" - -/* USB Device Firmware Update support */ -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC -#define CONFIG_DFU_NAND -#define CONFIG_CMD_DFU -#define DFU_ALT_INFO_MMC \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "MLO fat 0 1;" \ - "MLO.raw mmc 100 100;" \ - "u-boot.img.raw mmc 300 3C0;" \ - "u-boot.img fat 0 1;" \ - "uEnv.txt fat 0 1" -#define DFU_ALT_INFO_NAND \ - "SPL part 0 1;" \ - "SPL.backup1 part 0 2;" \ - "SPL.backup2 part 0 3;" \ - "SPL.backup3 part 0 4;" \ - "u-boot part 0 5;" \ - "kernel part 0 7;" \ - "rootfs part 0 8" - - /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - /* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "run mmcboot;" \ + "run nandboot;" /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 -/* I2C Configuration */ -#define CONFIG_I2C -#define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_OMAP_GPIO - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ -4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -#define CONFIG_ENV_IS_NOWHERE - -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -/* - * Place the image at the start of the ROM defined image space. - * We limit our size to the ROM-defined downloaded image area, and use the - * rest of the space for stack. - */ -#define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR - -#define CONFIG_SPL_OS_BOOT - -#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +/* PMIC support */ +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#ifdef CONFIG_SPL_OS_BOOT -/* fat */ -#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" -#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_DRAM_1 + 0x100) - -/* raw mmc */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ - -/* nand */ -#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_CMD_SPL_WRITE_SIZE 0x1000 - -/* spl export command */ -#define CONFIG_CMD_SPL -#endif +/* SPL */ +#ifndef CONFIG_NOR_BOOT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT +/* Bootcount using the RTC block */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_AM33XX +#define CONFIG_SYS_BOOTCOUNT_BE -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_YMODEM_SUPPORT -#define CONFIG_SPL_NET_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" -#define CONFIG_SPL_ETH_SUPPORT -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 +/* USB gadget RNDIS */ #define CONFIG_SPL_MUSB_NEW_SUPPORT + #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#endif -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_NAND_AM33XX_BCH -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC +#ifdef CONFIG_NAND +/* NAND: device related configs */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +/* NAND: driver related configs */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_GPMC_PREFETCH +#define CONFIG_NAND_OMAP_ELM #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ @@ -391,36 +250,59 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define MTDIDS_DEFAULT "nand0=nand.0" +#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ + "128k(NAND.SPL)," \ + "128k(NAND.SPL.backup1)," \ + "128k(NAND.SPL.backup2)," \ + "128k(NAND.SPL.backup3)," \ + "256k(NAND.u-boot-spl-os)," \ + "1m(NAND.u-boot)," \ + "128k(NAND.u-boot-env)," \ + "128k(NAND.u-boot-env.backup1)," \ + "8m(NAND.kernel)," \ + "-(NAND.rootfs)" +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x001c0000 +#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +/* NAND: SPL related configs */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_AM33XX_BCH +#endif +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif +#endif /* !CONFIG_NAND */ /* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80800000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -/* Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. + * For NOR boot, we must set this to the start of where NOR is mapped + * in memory. */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_TEXT_BASE 0x08000000 #endif /* - * USB configuration + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. */ #define CONFIG_USB_MUSB_DSPS #define CONFIG_ARCH_MISC_INIT #define CONFIG_MUSB_GADGET #define CONFIG_MUSB_PIO_ONLY #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_MUSB_HOST @@ -429,6 +311,18 @@ #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST +#ifndef CONFIG_SPL_USBETH_SUPPORT +/* Fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 + +/* To support eMMC booting */ +#define CONFIG_STORAGE_EMMC +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#endif + #ifdef CONFIG_MUSB_HOST #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE @@ -438,83 +332,160 @@ #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" + +/* USB TI's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0451 +#define CONFIG_G_DNL_PRODUCT_NUM 0xD022 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" #endif /* CONFIG_MUSB_GADGET */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) /* disable host part of MUSB in SPL */ #undef CONFIG_MUSB_HOST -/* - * Disable CPSW SPL support so we fit within the 101KiB limit. - */ -#undef CONFIG_SPL_ETH_SUPPORT +/* disable EFI partitions and partition UUID support */ +#undef CONFIG_PARTITION_UUIDS +#undef CONFIG_EFI_PARTITION +/* General network SPL */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" +#endif + +/* USB Device Firmware Update support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_CMD_DFU +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw raw 0x100 0x100;" \ + "u-boot.img.raw raw 0x300 0x400;" \ + "spl-os-args.raw raw 0x80 0x80;" \ + "spl-os-image.raw raw 0x900 0x2000;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1\0" +#ifdef CONFIG_NAND +#define CONFIG_DFU_NAND +#define DFU_ALT_INFO_NAND \ + "dfu_alt_info_nand=" \ + "SPL part 0 1;" \ + "SPL.backup1 part 0 2;" \ + "SPL.backup2 part 0 3;" \ + "SPL.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot-spl-os part 0 6;" \ + "kernel part 0 8;" \ + "rootfs part 0 9\0" +#else +#define DFU_ALT_INFO_NAND "" +#endif +#define CONFIG_DFU_RAM +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "kernel ram 0x80200000 0xD80000;" \ + "fdt ram 0x80F80000 0x80000;" \ + "ramdisk ram 0x81000000 0x4000000\0" +#define DFUARGS \ + "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_NAND #endif /* - * Default to using SPI for environment, etc. We have multiple copies - * of SPL as the ROM will check these locations. - * 0x0 - 0x20000 : First copy of SPL - * 0x20000 - 0x40000 : Second copy of SPL - * 0x40000 - 0x60000 : Third copy of SPL - * 0x60000 - 0x80000 : Fourth copy of SPL - * 0x80000 - 0xDF000 : U-Boot - * 0xDF000 - 0xE0000 : U-Boot Environment - * 0xE0000 - 0x442000 : Linux Kernel + * Default to using SPI for environment, etc. + * 0x000000 - 0x020000 : SPL (128KiB) + * 0x020000 - 0x0A0000 : U-Boot (512KiB) + * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) + * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) + * 0x0E0000 - 0x442000 : Linux Kernel * 0x442000 - 0x800000 : Userland */ #if defined(CONFIG_SPI_BOOT) -# undef CONFIG_ENV_IS_NOWHERE -# define CONFIG_ENV_IS_IN_SPI_FLASH -# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ -# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ -#endif /* SPI support */ - -/* Unsupported features */ -#undef CONFIG_USE_IRQ - -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI +/* SPL related */ +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ +#define MTDIDS_DEFAULT "nor0=m25p80-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ + "512k(u-boot),128k(u-boot-env1)," \ + "128k(u-boot-env2),3464k(kernel)," \ + "-(rootfs)" +#elif defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif + +/* SPI flash. */ +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_SPEED 24000000 + +/* Network. */ #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC -#define CONFIG_NAND -/* NAND support */ -#ifdef CONFIG_NAND -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ - "128k(SPL.backup1)," \ - "128k(SPL.backup2)," \ - "128k(SPL.backup3),1792k(u-boot)," \ - "128k(u-boot-spl-os)," \ - "128k(u-boot-env),5m(kernel),-(rootfs)" -#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND - devices */ -#if !defined(CONFIG_SPI_BOOT) -#undef CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#endif +/* + * NOR Size = 16 MiB + * Number of Sectors/Blocks = 128 + * Sector Size = 128 KiB + * Word length = 16 bits + * Default layout: + * 0x000000 - 0x07FFFF : U-Boot (512 KiB) + * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB) + * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB) + * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB) + * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) + */ +#if defined(CONFIG_NOR) +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +/* Reduce SPL size by removing unlikey targets */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ +#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ + "512k(u-boot)," \ + "128k(u-boot-env1)," \ + "128k(u-boot-env2)," \ + "4m(kernel),-(rootfs)" #endif +#endif /* NOR support */ #endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h new file mode 100644 index 0000000000..a14310a8ed --- /dev/null +++ b/include/configs/am335x_igep0033.h @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_IGEP0033_H +#define __CONFIG_IGEP0033_H + +#define CONFIG_NAND +#include + +/* Mach type */ +#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033 + +/* Clock defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + +/* Make the verbose messages from UBI stop printing */ +#define CONFIG_UBI_SILENCE_MSG +#define CONFIG_UBIFS_SILENCE_MSG + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "dtbfile=am335x-base0033.dtb\0" \ + "console=ttyO0,115200n8\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ + "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${dtbfile}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmcload; then " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr};" \ + "fi;" \ + "fi;\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandroot=ubi0:filesystem rw ubi.mtd=3,2048\0" \ + "nandrootfstype=ubifs rootwait\0" \ + "nandload=ubi part filesystem 2048; ubifsmount ubi0; " \ + "ubifsload ${loadaddr} ${bootdir}/${bootfile}; " \ + "ubifsload ${fdtaddr} ${bootdir}/${dtbfile} \0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} \0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "run nandload; " \ + "bootz ${loadaddr} - ${fdtaddr} \0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot;" \ + "run nandboot;" + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Ethernet support */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +/* NAND support */ +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_ONFI_DETECTION 1 +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x180000 /* environment starts here */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO + +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(spl),"\ + "1m(uboot),256k(environment),"\ + "-(filesystem)" + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +/* SPL */ +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#endif /* ! __CONFIG_IGEP0033_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 9bf283aba3..09ee10c059 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -17,8 +17,8 @@ * High Level Configuration Options */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ +#define CONFIG_OMAP_COMMON #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ @@ -141,10 +141,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS @@ -238,7 +238,6 @@ */ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -252,23 +251,17 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ /* on one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -299,7 +292,6 @@ GENERATED_GBL_DATA_SIZE) /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE @@ -312,8 +304,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT @@ -330,6 +322,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -340,6 +333,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 5c6169771c..190ef0e71b 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -17,8 +17,8 @@ * High Level Configuration Options */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ +#define CONFIG_OMAP_COMMON #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ @@ -56,6 +56,11 @@ * Hardware drivers */ +/* + * OMAP GPIO configuration + */ +#define CONFIG_OMAP_GPIO + /* * NS16550 Configuration */ @@ -135,13 +140,23 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX + +/* + * Ethernet + */ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS /* * Board NAND Info. */ @@ -230,7 +245,6 @@ */ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -244,25 +258,19 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ /* on one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -293,7 +301,6 @@ GENERATED_GBL_DATA_SIZE) /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE @@ -306,8 +313,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT @@ -334,6 +341,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h new file mode 100644 index 0000000000..7ccbf36b0b --- /dev/null +++ b/include/configs/am43xx_evm.h @@ -0,0 +1,340 @@ +/* + * am43xx_evm.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_AM43XX_EVM_H +#define __CONFIG_AM43XX_EVM_H + +#define CONFIG_AM43XX + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_SAVEENV + +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 + +/* I2C Configuration */ +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* Power */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65218 +#define CONFIG_POWER_TPS62362 + +/* SPL defines. */ +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) +#define CONFIG_BOARD_EARLY_INIT_F +#endif + +/* Now bring in the rest of the common code. */ +#include + +/* Always 64 KiB env size */ +#define CONFIG_ENV_SIZE (64 << 10) + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ + +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* SPL USB Support */ +#define CONFIG_SPL_USB_SUPPORT +#define CONFIG_SPL_USB_HOST_SUPPORT +#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 + +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_AM437X_USB2PHY2_HOST + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x30000000 +#undef CONFIG_ENV_IS_IN_FAT +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ +#define CONFIG_ENV_OFFSET 0x110000 +#define CONFIG_ENV_OFFSET_REDUND 0x120000 +#ifdef MTDIDS_DEFAULT +#undef MTDIDS_DEFAULT +#endif +#ifdef MTDPARTS_DEFAULT +#undef MTDPARTS_DEFAULT +#endif +#define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \ + "512k(QSPI.u-boot.backup)," \ + "512k(QSPI.u-boot-spl-os)," \ + "64k(QSPI.u-boot-env)," \ + "64k(QSPI.u-boot-env.backup)," \ + "8m(QSPI.kernel)," \ + "-(QSPI.file-system)" +#endif + +/* SPI */ +#undef CONFIG_OMAP3_SPI +#define CONFIG_TI_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_TI_SPI_MMAP +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_QSPI_SEL_GPIO 48 +#define CONFIG_SF_DEFAULT_SPEED 48000000 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "usbroot=/dev/sda2 rw\0" \ + "usbrootfstype=ext4 rootwait\0" \ + "usbdev=0\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "usbargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${usbroot} " \ + "rootfstype=${usbrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load ${devtype} ${devnum} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "setenv devnum ${mmcdev}; " \ + "setenv devtype mmc; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${devnum};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi;\0" \ + "usbboot=" \ + "setenv devnum ${usbdev}; " \ + "setenv devtype usb; " \ + "usb start ${usbdev}; " \ + "if usb dev ${usbdev}; then " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from usb ${usbdev}...; " \ + "run usbargs;" \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi\0" \ + "findfdt="\ + "if test $board_name = AM43EPOS; then " \ + "setenv fdtfile am43x-epos-evm.dtb; fi; " \ + "if test $board_name = AM43__GP; then " \ + "setenv fdtfile am437x-gp-evm.dtb; fi; " \ + "if test $board_name = AM43__SK; then " \ + "setenv fdtfile am437x-sk-evm.dtb; fi; " \ + "if test $board_name = AM43_IDK; then " \ + "setenv fdtfile am437x-idk-evm.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree; fi; \0" + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" \ + "run usbboot;" + +#endif + +/* CPSW Ethernet */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB + +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL" + +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SYS_RX_ETH_BUFFER 64 + +/* NAND support */ +#ifdef CONFIG_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +/* NAND: driver related configs */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ + 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ + 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ + 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ + 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ + 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ + 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ + } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 26 +#define MTDIDS_DEFAULT "nand0=nand.0" +#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ + "256k(NAND.SPL)," \ + "256k(NAND.SPL.backup1)," \ + "256k(NAND.SPL.backup2)," \ + "256k(NAND.SPL.backup3)," \ + "512k(NAND.u-boot-spl-os)," \ + "1m(NAND.u-boot)," \ + "256k(NAND.u-boot-env)," \ + "256k(NAND.u-boot-env.backup1)," \ + "7m(NAND.kernel)," \ + "-(NAND.rootfs)" +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 +/* NAND: SPL related configs */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_AM33XX_BCH +#endif +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#endif +#endif /* !CONFIG_NAND */ + +#endif /* __CONFIG_AM43XX_EVM_H */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 580d079ed1..2aea89937a 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -74,7 +74,6 @@ */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -90,8 +89,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING /* add command line history */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_LOOPW /* enable loopw command */ @@ -128,7 +125,6 @@ */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -257,10 +253,4 @@ "cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ -#define CONFIG_AMCC_DEF_ENV_NAND_UPD \ - "u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\ - "nload=tftp 200000 ${u-boot-nand}\0" \ - "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \ - "nupd=run nload nupdate\0" - #endif /* __AMCC_COMMON_H */ diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index af3a4277e2..462b2e2910 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -11,8 +11,6 @@ #define __AP325RXA_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4 1 #define CONFIG_CPU_SH7723 1 #define CONFIG_AP325RXA 1 @@ -51,7 +49,6 @@ /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " /* Buffer size for input from the Console */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for Console output */ @@ -155,7 +152,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ -#define CONFIG_SYS_HZ 1000 #endif /* __AP325RXA_H */ diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index b9112910e7..4282d70266 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -10,9 +10,6 @@ #define __AP_SH4A_4A_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4 1 -#define CONFIG_SH4A 1 #define CONFIG_CPU_SH7734 1 #define CONFIG_AP_SH4A_4A 1 #define CONFIG_400MHZ_MODE 1 @@ -67,7 +64,6 @@ /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " /* Buffer size for input from the Console */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for Console output */ @@ -138,8 +134,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ @@ -158,7 +152,8 @@ #else #define CONFIG_SYS_CLK_FREQ 44444444 #endif +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __AP_SH4A_4A_H */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h new file mode 100644 index 0000000000..61809fcdbe --- /dev/null +++ b/include/configs/apalis_t30.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2014 Marcel Ziswiler + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra30-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Apalis T30 # " +#define CONFIG_TEGRA_BOARD_STRING "Toradex Apalis T30" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30 + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* PCI host support */ +#undef CONFIG_PCI /* just define once Tegra PCIe support got merged */ +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_E1000 +#undef CONFIG_E1000_NO_NVM /* just define once E1000 driver got fixed */ + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h new file mode 100644 index 0000000000..c8cbd5009e --- /dev/null +++ b/include/configs/apf27.h @@ -0,0 +1,381 @@ +/* + * + * Configuration settings for the Armadeus Project motherboard APF27 + * + * Copyright (C) 2008-2013 Eric Jarrige + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_ENV_VERSION 10 +#define CONFIG_IDENT_STRING " apf27 patch 3.10" +#define CONFIG_BOARD_NAME apf27 + +/* + * SoC configurations + */ +#define CONFIG_MACH_TYPE 1698 /* APF27 */ +#define CONFIG_SYS_GENERIC_BOARD + +/* + * Enable the call to miscellaneous platform dependent initialization. + */ +#define CONFIG_SYS_NO_FLASH /* to be define before */ + +/* + * Board display option + */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO + +/* + * SPL + */ +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_TEXT_BASE 0xA0000000 + +/* NAND boot config */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 + +#define CONFIG_HOSTNAME CONFIG_BOARD_NAME +#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" + +/* + * U-Boot Commands + */ +#include + +#define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_BSP /* Board Specific functions */ +#define CONFIG_CMD_CACHE /* icache, dcache */ +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_DNS +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII /* MII support */ +#define CONFIG_CMD_MMC +#define CONFIG_CMD_MTDPARTS /* MTD partition support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING /* ping support */ +#define CONFIG_CMD_SETEXPR /* setexpr support */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_POPULATED 1 +#define CONFIG_NR_DRAM_BANKS 2 + +#define ACFG_SDRAM_MBYTE_SYZE 64 + +#define PHYS_SDRAM_1 0xA0000000 +#define PHYS_SDRAM_2 0xB0000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) +#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ +#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ + + PHYS_SDRAM_1_SIZE - 0x0100000) + +#define CONFIG_SYS_TEXT_BASE 0xA0000800 + +/* + * FLASH organization + */ +#define ACFG_MONITOR_OFFSET 0x00000000 +#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ +#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ +#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ +#define CONFIG_FIRMWARE_OFFSET 0x00200000 +#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ +#define CONFIG_KERNEL_OFFSET 0x00300000 +#define CONFIG_ROOTFS_OFFSET 0x00800000 + +#define CONFIG_MTDMAP "mxc_nand.0" +#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP +#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \ + ":1M(u-boot)ro," \ + "512K(env)," \ + "512K(env2)," \ + "512K(firmware)," \ + "512K(dtb)," \ + "5M(kernel)," \ + "-(rootfs)" + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */ +#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 16 /* max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_PREBOOT "run check_flash check_env;" + + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG /* send initrd params */ + +#define CONFIG_OF_LIBFDT + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" +#define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \ + __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \ + " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " + +#define ACFG_CONSOLE_DEV ttySMX0 +#define CONFIG_BOOTCOMMAND "run ubifsboot" +#define CONFIG_SYS_AUTOLOAD "no" +/* + * Default load address for user programs and kernel + */ +#define CONFIG_LOADADDR 0xA0000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ + "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,6\0" \ + "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ + "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ + "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ + "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ + "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ + "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ + "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ + "kernel_addr_r=A0000000\0" \ + "check_env=if test -n ${flash_env_version}; " \ + "then env default env_version; " \ + "else env set flash_env_version ${env_version}; env save; "\ + "fi; " \ + "if itest ${flash_env_version} < ${env_version}; then " \ + "echo \"*** Warning - Environment version" \ + " change suggests: run flash_reset_env; reset\"; "\ + "env default flash_reset_env; "\ + "fi; \0" \ + "check_flash=nand lock; nand unlock ${env_addr}; \0" \ + "flash_reset_env=env default -f -a; saveenv; run update_env;" \ + "echo Flash environment variables erased!\0" \ + "download_uboot=tftpboot ${loadaddr} ${board_name}" \ + "-u-boot-with-spl.bin\0" \ + "flash_uboot=nand unlock ${u-boot_addr} ;" \ + "nand erase.part u-boot;" \ + "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ + "then nand lock; nand unlock ${env_addr};" \ + "echo Flashing of uboot succeed;" \ + "else echo Flashing of uboot failed;" \ + "fi; \0" \ + "update_uboot=run download_uboot flash_uboot\0" \ + "download_env=tftpboot ${loadaddr} ${board_name}" \ + "-u-boot-env.txt\0" \ + "flash_env=env import -t ${loadaddr}; env save; \0" \ + "update_env=run download_env flash_env\0" \ + "update_all=run update_env update_uboot\0" \ + "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ + +/* + * Serial Driver + */ +#define CONFIG_MXC_UART +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* + * GPIO + */ +#define CONFIG_MXC_GPIO + +/* + * NOR + */ + +/* + * NAND + */ +#define CONFIG_NAND_MXC + +#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 +#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 +#define NAND_MAX_CHIPS 1 + +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_NAND_QUIET 1 + +/* + * Partitions & Filsystems + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + +/* + * UBIFS + */ +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* + * Ethernet (on SOC imx FEC) + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII /* MII PHY management */ + +/* + * FPGA + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_FPGA +#endif +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_CHECK_CTRLC +#define CONFIG_SYS_FPGA_CHECK_ERROR + +/* + * Fuses - IIM + */ +#ifdef CONFIG_CMD_IMX_FUSE +#define IIM_MAC_BANK 0 +#define IIM_MAC_ROW 5 +#define IIM0_SCC_KEY 11 +#define IIM1_SUID 1 +#endif + +/* + * I2C + */ + +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F +#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES { } + +#ifdef CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ +#endif /* CONFIG_CMD_EEPROM */ +#endif /* CONFIG_CMD_I2C */ + +/* + * SD/MMC + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 +#endif + +/* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1374 +#define CONFIG_SYS_RTC_BUS_NUM 0 +#endif /* CONFIG_CMD_DATE */ + +/* + * PLL + * + * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 + * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| + */ +#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ + +#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ +/* micron 64MB */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ +#endif + +#if (ACFG_SDRAM_MBYTE_SYZE == 128) +/* micron 128MB */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#endif + +#if (ACFG_SDRAM_MBYTE_SYZE == 256) +/* micron 256MB */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ +#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index 8561a248c4..9536e85be5 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -11,34 +11,15 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SoC configurations */ -#define CONFIG_MX28 /* i.MX28 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#ifndef __CONFIGS_APX4DEVKIT_H__ +#define __CONFIGS_APX4DEVKIT_H__ +/* System configurations */ #define MACH_TYPE_APX4DEVKIT 3712 #define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT -#include - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_ARCH_MISC_INIT - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - /* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -58,78 +39,26 @@ #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_USB -/* Memory configurations */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +/* Environment */ #define CONFIG_ENV_OVERWRITE - -/* U-Boot general configurations */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-Boot version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc. */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_OF_LIBFDT #define CONFIG_ENV_IS_IN_NAND -/* Serial Driver */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* DMA */ -#define CONFIG_APBH_DMA - -/* MMC Driver */ -#ifdef CONFIG_ENV_IS_IN_MMC +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_ENV_OFFSET (256 * 1024) #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 #endif -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_MXS_MMC -#endif - -/* NAND Driver */ -#ifdef CONFIG_ENV_IS_IN_NAND +/* Environment is in NAND */ +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE (128 * 1024) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE @@ -139,12 +68,8 @@ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) #endif +/* UBI and NAND partitioning */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_CMD_MTDPARTS @@ -159,43 +84,30 @@ #define MTDPARTS_DEFAULT "" #endif -/* Ethernet on SOC (FEC) */ +/* FEC Ethernet on SoC */ #ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC #define CONFIG_NET_MULTI #define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC #define CONFIG_FEC_MXC_PHYADDR 0 #define IMX_FEC_BASE MXS_ENET0_BASE -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII #endif /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MXS -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#endif /* RTC */ -#if defined(CONFIG_CMD_DATE) +#ifdef CONFIG_CMD_DATE #define CONFIG_RTC_PCF8563 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 #endif /* Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTCOMMAND "run bootcmd_nand" @@ -225,4 +137,7 @@ "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \ "" -#endif /* __CONFIG_H */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_APX4DEVKIT_H__ */ diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h new file mode 100644 index 0000000000..76163ab2a0 --- /dev/null +++ b/include/configs/arcangel4-be.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_SYS_BIG_ENDIAN +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h new file mode 100644 index 0000000000..81934a45a8 --- /dev/null +++ b/include/configs/arcangel4.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/aria.h b/include/configs/aria.h index 68f25ea388..2f9677c332 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -2,7 +2,7 @@ * (C) Copyright 2009 Wolfgang Denk * (C) Copyright 2009, DAVE Srl * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_ARIA 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the ARIA board: * @@ -31,7 +34,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 @@ -469,7 +471,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -485,8 +486,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 - /* * For booting Linux, the board info and command line data * have to be in the first 256 MB of memory, since this is @@ -510,7 +509,6 @@ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h new file mode 100644 index 0000000000..78deeab6e0 --- /dev/null +++ b/include/configs/aristainetos.h @@ -0,0 +1,324 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6Q SabreSD board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ARISTAINETOS_CONFIG_H +#define __ARISTAINETOS_CONFIG_H + + +#include "mx6_common.h" +#include + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#include +#include + +#define CONFIG_MACH_TYPE 4501 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" +#define CONFIG_DEFAULT_FDT_FILE "aristainetos.dtb" +#define CONFIG_HOSTNAME aristainetos +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART5_BASE +#define CONFIG_CONSOLE_DEV "ttymxc4" + +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MTD +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 3 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_SETEXPR +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "uimage=uImage\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr_r=0x11000000\0" \ + "kernel_addr_r=0x12000000\0" \ + "kernel_file=uImage\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "mmcpart=1\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} " \ + "${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} " \ + "${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs;run loadimage loadfdt fdt_setup;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r};\0" \ + "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-sato-sdk\0" \ + "nfsopts=nfsvers=3 nolock rw\0" \ + "netdev=eth0\0" \ + "fdt_setup=fdt addr ${fdt_addr_r};fdt resize;fdt chosen;fdt board\0"\ + "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ + "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "get_env=mw ${loadaddr} 0x00000000 0x20000;" \ + "tftp ${loadaddr} /tftpboot/aristainetos/env.txt;" \ + "env import -t ${loadaddr}\0" \ + "addmisc=setenv bootargs ${bootargs} maxcpus=1 loglevel=8\0" \ + "bootargs_defaults=setenv bootargs ${console} ${mtdoops} " \ + "${optargs}\0" \ + "net_args=run bootargs_defaults;setenv bootargs ${bootargs} " \ + "root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}:${netdev}:off\0" \ + "net_nfs=run load_kernel load_fdt;run net_args addmtd addmisc;" \ + "run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "uboot=/tftpboot/aristainetos/u-boot.imx\0" \ + "load_uboot=tftp ${loadaddr} ${uboot}\0" \ + "uboot_sz=c0000\0" \ + "upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ + "mw.b 10200000 0x00 ${uboot_sz};" \ + "run load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ + "sf write ${loadaddr} 400 ${filesize};" \ + "sf read 10200000 400 ${uboot_sz};" \ + "cmp.b ${loadaddr} 10200000 bc000\0" \ + "ubi_prep=ubi part ubi 2048;ubifsmount ubi:kernel\0" \ + "load_kernel_ubi=ubifsload ${kernel_addr_r} uImage\0" \ + "load_fdt_ubi=ubifsload ${fdt_addr_r} aristainetos.dtb\0" \ + "ubi_nfs=run ubiprep load_kernel_ubi load_fdt_ubi;" \ + "run net_args addmtd addmisc;run fdt_setup;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "rootfsname=rootfs\0" \ + "ubi_args=run bootargs_defaults;setenv bootargs ${bootargs} " \ + "ubi.mtd=0,2048 root=ubi0:${rootfsname} rootfstype=ubifs " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}:${netdev}:off\0" \ + "ubi_ubi=run ubi_prep load_kernel_ubi load_fdt_ubi;" \ + "run bootargs_defaults ubi_args addmtd addmisc;" \ + "run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "ubirootfs_file=/tftpboot/aristainetos/rootfs-minimal.ubifs\0" \ + "upd_ubirootfs=run ubi_prep;tftp ${loadaddr} ${ubirootfs_file};" \ + "ubi write ${loadaddr} rootfs ${filesize}\0" \ + "ksz=800000\0" \ + "rootsz=2000000\0" \ + "usersz=8000000\0" \ + "ubi_make=run ubi_prep;ubi create kernel ${ksz};" \ + "ubi create rootfs ${rootsz};ubi create userfs ${usersz}\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "run mmcboot;" \ + "else run ubi_ubi; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (12 * 1024) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SECT_SIZE (0x010000) +#define CONFIG_ENV_OFFSET (0x0c0000) +#define CONFIG_ENV_OFFSET_REDUND (0x0d0000) + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMD_CACHE + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } + +#define CONFIG_CMD_GPIO +#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) + +/* NAND stuff */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_RTC_BUS_NUM 2 +#define CONFIG_RTC_M41T11 +#define CONFIG_CMD_DATE + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) +#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31) + +/* UBI support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:-(ubi)" + +#define CONFIG_MTD_UBI_FASTMAP +#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1 + +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG + +#define CONFIG_FIT + +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +/* check this console not needed, after test remove it */ +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 198000000 +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_CMD_BMP + +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#endif /* __ARISTAINETOS_CONFIG_H */ diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 9f357eadb2..72469f35b2 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -10,9 +10,7 @@ #define __ARMADILLO_800EVA_H #undef DEBUG -#define CONFIG_ARMV7 #define CONFIG_R8A7740 -#define CONFIG_RMOBILE #define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n" #define CONFIG_SH_GPIO_PFC @@ -48,6 +46,7 @@ #define CONFIG_USE_ARCH_MEMCPY #define CONFIG_TMU_TIMER #define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_GENERIC_BOARD /* STACK */ #define CONFIG_SYS_INIT_SP_ADDR 0xE8083000 @@ -60,7 +59,6 @@ #define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024) #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_MAXARGS 16 @@ -95,7 +93,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #define CONFIG_SYS_TEXT_BASE 0xE80C0000 @@ -138,7 +135,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 50000000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __ARMADILLO_800EVA_H */ diff --git a/include/configs/arndale.h b/include/configs/arndale.h new file mode 100644 index 0000000000..3ad4a9ba91 --- /dev/null +++ b/include/configs/arndale.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Configuration settings for the SAMSUNG Arndale board. + */ + +#ifndef __CONFIG_ARNDALE_H +#define __CONFIG_ARNDALE_H + +#define EXYNOS_FDTFILE_SETTING \ + "fdtfile=exynos5250-arndale.dtb\0" + +#include "exynos5250-common.h" + +/* SD/MMC configuration */ +#define CONFIG_SUPPORT_EMMC_BOOT + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS + +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_ASIX88179 + +/* MMC SPL */ +#define CONFIG_EXYNOS_SPL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "ARNDALE # " +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#define CONFIG_IDENT_STRING " for ARNDALE" + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) + +#define CONFIG_IRAM_STACK 0x02050000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK + +/* PMIC */ +#define CONFIG_PMIC +#define CONFIG_POWER_I2C + +#define CONFIG_PREBOOT + +#define CONFIG_S5P_PA_SYSRAM 0x02020000 +#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM + +/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index ed9400e4c0..fa64a688a4 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -3,7 +3,7 @@ * * (C) Copyright 2003 Josef Baumgartner * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -88,6 +88,7 @@ #define CONFIG_CMD_LOADS #define CONFIG_CMD_LOADB #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER @@ -110,10 +111,8 @@ /* * Defines processor clock - important for correct timings concerning serial * interface etc. - * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index e158b0dd2d..735c82aa8d 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -14,7 +14,7 @@ #ifndef __AT91RM9200EK_CONFIG_H__ #define __AT91RM9200EK_CONFIG_H__ -#include +#include /* * set some initial configurations depending on configure target @@ -43,7 +43,6 @@ #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) -#define CONFIG_SYS_HZ 1000 /* CPU configuration */ #define CONFIG_AT91RM9200 @@ -62,6 +61,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory Configuration */ @@ -154,6 +155,7 @@ * USB Config */ #define CONFIG_USB_ATMEL 1 +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_USB_KEYBOARD 1 #define CONFIG_USB_STORAGE 1 diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index d7fd6b089c..a6a80de88a 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -28,7 +28,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ -#define CONFIG_SYS_HZ 1000 /* Define actual evaluation board type from used processor type */ #ifdef CONFIG_AT91SAM9G20 @@ -49,6 +48,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO @@ -136,7 +137,6 @@ #ifndef CONFIG_AT91SAM9G20EK_2MMC #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ @@ -182,9 +182,11 @@ #define CONFIG_RMII 1 #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R 1 +#define CONFIG_AT91_WANTS_COMMON_PHY /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index af56604396..407a53e555 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -14,7 +14,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 #ifdef CONFIG_AT91SAM9G10 #define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/ @@ -34,6 +33,8 @@ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_ATMEL_LEGACY #define CONFIG_SYS_TEXT_BASE 0x21f00000 @@ -108,7 +109,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ @@ -146,6 +146,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 40e167c10a..fa19e8bcc8 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -26,7 +26,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_HZ 1000 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ @@ -49,6 +48,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* * Hardware drivers */ @@ -104,6 +105,7 @@ #define CONFIG_CMD_PING 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_MMC #define CONFIG_CMD_USB 1 /* SDRAM */ @@ -117,13 +119,24 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 #define DATAFLASH_TCSS (0x1a << 16) #define DATAFLASH_TCHS (0x1 << 24) +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* FAT */ +#ifdef CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH #define CONFIG_SYS_FLASH_CFI 1 @@ -276,9 +289,11 @@ #define CONFIG_RMII 1 #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R 1 +#define CONFIG_AT91_WANTS_COMMON_PHY /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 2aea55567d..db5d5ea846 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -13,16 +13,15 @@ #include -#define CONFIG_AT91_LEGACY +#define CONFIG_SYS_TEXT_BASE 0x73f00000 + #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_AT91SAM9M10G45EK -#define CONFIG_AT91FAMILY #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS @@ -34,6 +33,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO @@ -76,6 +77,10 @@ /* * Command line configuration. */ + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + #include #undef CONFIG_CMD_BDI #undef CONFIG_CMD_FPGA @@ -96,9 +101,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -/* No NOR flash */ -#define CONFIG_SYS_NO_FLASH - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL @@ -114,17 +116,31 @@ #endif +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* Ethernet */ #define CONFIG_MACB #define CONFIG_RMII #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R +#define CONFIG_AT91_WANTS_COMMON_PHY /* USB */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 -#define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ @@ -132,6 +148,7 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 +#ifdef CONFIG_SYS_USE_NANDFLASH /* bootstrap + u-boot + env in nandflash */ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0xc0000 @@ -147,6 +164,28 @@ "256k(env),256k(env_redundant),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "root=/dev/mtdblock7 rw rootfstype=jffs2" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env + linux in mmc */ +#define FAT_ENV_INTERFACE "mmc" +/* + * We don't specify the part number, if device 0 has partition table, it means + * the first partition; it no partition table, then take whole device as a + * FAT file system. + */ +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "mtdparts=atmel_nand:" \ + "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ + "root=/dev/mmcblk0p2 rw rootwait" +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ + "fatload mmc 0:1 0x72000000 zImage; " \ + "bootz 0x72000000 - 0x71000000" +#endif #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index be8a28c327..f02fce95b3 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -18,13 +18,9 @@ #define CONFIG_SYS_TEXT_BASE 0x26f00000 -#define CONFIG_ARM926EJS -#define CONFIG_AT91FAMILY - /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ -#define CONFIG_SYS_HZ 1000 /* Misc CPU related */ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ @@ -35,6 +31,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD /* general purpose I/O */ #define CONFIG_AT91_GPIO @@ -83,6 +80,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_MMC #define CONFIG_CMD_FAT +#define CONFIG_CMD_USB #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x20000000 @@ -113,8 +111,8 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 5 +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) /* PMECC & PMERRLOC */ #define CONFIG_ATMEL_NAND_HWECC @@ -122,6 +120,9 @@ #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 #define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 + +#define CONFIG_CMD_NAND_TRIMFFS + #endif #define CONFIG_MTD_PARTITIONS @@ -160,6 +161,18 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x26e00000 +/* USB host */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_STORAGE +#endif + #ifdef CONFIG_SYS_USE_SPIFLASH /* bootstrap + u-boot + env + linux in dataflash on CS0 */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index b08848ef73..d5f0197466 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -18,7 +18,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_AT91SAM9RLEK 1 /* It's an AT91SAM9RLEK Board */ @@ -35,6 +34,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_ATMEL_LEGACY #define CONFIG_AT91_GPIO 1 #define CONFIG_AT91_GPIO_PULLUP 1 @@ -99,7 +100,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 2b1533c85a..b1d4baaff9 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -11,13 +11,13 @@ #include +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_AT91SAM9X5EK -#define CONFIG_AT91FAMILY #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS @@ -29,6 +29,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO @@ -43,7 +45,6 @@ #define LCD_BPP LCD_COLOR16 #define LCD_OUTPUT_BPP 24 #define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_WHITE_ON_BLACK @@ -61,14 +62,15 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH + /* * Command line configuration. */ #include #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP @@ -100,9 +102,6 @@ #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif -/* no NOR flash */ -#define CONFIG_SYS_NO_FLASH - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL @@ -121,7 +120,8 @@ #define CONFIG_ATMEL_NAND_HW_PMECC 1 #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 + +#define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_MTD_DEVICE #define CONFIG_CMD_MTDPARTS @@ -156,13 +156,14 @@ #define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 #else +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 #endif -#define CONFIG_USB_ATMEL #define CONFIG_USB_STORAGE #endif @@ -241,8 +242,4 @@ */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - #endif diff --git a/include/configs/atc.h b/include/configs/atc.h deleted file mode 100644 index b661e95e04..0000000000 --- a/include/configs/atc.h +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_ATC 1 /* ...on a ATC board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 115200 - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_ON_FCC2 - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#define CONFIG_ETHER_ON_FCC3 - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the local Bus (see 28-13) - * - Enable Half Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 64000000 /* in Hz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ - -#define CONFIG_PREBOOT \ - "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\ - "echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ - "bootm" - -/*----------------------------------------------------------------------- - * Miscellaneous configuration options - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_DATE -#define CONFIG_CMD_IDE - - -#define CONFIG_DOS_PARTITION - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */ - -#define CONFIG_SYS_ALLOC_DPRAM - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SPI - -#define CONFIG_RTC_DS12887 - -#define RTC_BASE_ADDR 0xF5000000 -#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 -#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 - -#define CONFIG_MISC_INIT_R - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash configuration - */ - -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_16BIT - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ - HRCW_BPS10 |\ - HRCW_APPC10) - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ - -#if 1 -/* environment is in Flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000) -# define CONFIG_ENV_SIZE 0x10000 -# define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 2048 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\ - SIUMCR_CS10PC00|SIUMCR_BCTLC10) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MPTPR 0x1F00 - -/*----------------------------------------------------------------------- - * PSRT - Refresh Timer Register 10-16 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PSRT 0x0f - -/*----------------------------------------------------------------------- - * PSRT - SDRAM Mode Register 10-10 - *----------------------------------------------------------------------- - */ - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI1_A6 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit Boot ROM - * 1 60x GPCM 64 bit FLASH - * 2 60x SDRAM 64 bit SDRAM - * - */ - -#define CONFIG_SYS_MRS_OFFS 0x00000000 - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - - -/* Bank 2 - 60x bus SDRAM - */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL - -#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL -#endif /* CONFIG_SYS_RAMBOOT */ - -#define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_I82365 - -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000 -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000 - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x100 - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x100 - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x108 - -#endif /* __CONFIG_H */ diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index c87e4147cd..9c81e3199f 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -10,13 +10,10 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100 -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 8e4ad073cd..7b4f9cf206 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -12,17 +12,10 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100MKII -/* - * Timer clock frequency. We're using the CPU-internal COUNT register - * for this, so this is equivalent to the CPU core clock frequency - */ -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency @@ -158,6 +151,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 5be563ce0d..8f3fd0bb00 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -10,18 +10,11 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_ATSTK1002 #define CONFIG_ATSTK1000 -/* - * Timer clock frequency. We're using the CPU-internal COUNT register - * for this, so this is equivalent to the CPU core clock frequency - */ -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index a49d0add82..63704b1987 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -10,18 +10,11 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7001 #define CONFIG_ATSTK1003 #define CONFIG_ATSTK1000 -/* - * Timer clock frequency. We're using the CPU-internal COUNT register - * for this, so this is equivalent to the CPU core clock frequency - */ -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 7f3976c54f..331a60d76a 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -10,18 +10,11 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7002 #define CONFIG_ATSTK1004 #define CONFIG_ATSTK1000 -/* - * Timer clock frequency. We're using the CPU-internal COUNT register - * for this, so this is equivalent to the CPU core clock frequency - */ -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 97470dfad8..bbe0aea861 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -10,17 +10,11 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_ATSTK1006 #define CONFIG_ATSTK1000 -/* - * Timer clock frequency. We're using the CPU-internal COUNT register - * for this, so this is equivalent to the CPU core clock frequency - */ -#define CONFIG_SYS_HZ 1000 /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL diff --git a/include/configs/axs101.h b/include/configs/axs101.h new file mode 100644 index 0000000000..c61ddd6fb7 --- /dev/null +++ b/include/configs/axs101.h @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_AXS101_H_ +#define _CONFIG_AXS101_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* NAND controller DMA doesn't work correctly with D$ enabled */ +#define CONFIG_SYS_DCACHE_OFF + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 +#define ARC_APB_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) +#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * NAND Flash configuration + */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* + * UART configuration + * + * CONFIG_CONS_INDEX = 1 - Debug UART + * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB + */ +#define CONFIG_CONS_INDEX 4 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#if (CONFIG_CONS_INDEX == 1) + /* Debug UART */ +# define CONFIG_SYS_NS16550_CLK 33333000 +#else + /* FPGA UARTs use different clock */ +# define CONFIG_SYS_NS16550_CLK 33333333 +#endif +#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000) +#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000) +#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000) +#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000) +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_BAUDRATE 115200 +/* + * I2C configuration + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW +#define CONFIG_I2C_ENV_EEPROM_BUS 2 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SPEED1 100000 +#define CONFIG_SYS_I2C_SPEED2 100000 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_SLAVE1 0 +#define CONFIG_SYS_I2C_SLAVE2 0 +#define CONFIG_SYS_I2C_BASE 0xE001D000 +#define CONFIG_SYS_I2C_BASE1 0xE001E000 +#define CONFIG_SYS_I2C_BASE2 0xE001F000 +#define CONFIG_SYS_I2C_BUS_MAX 3 +#define IC_CLK 50 + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64 + +/* + * SD/MMC configuration + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_DOS_PARTITION + +/* + * Ethernet PHY configuration + */ +#define CONFIG_PHYLIB +#define CONFIG_MII +#define CONFIG_PHY_GIGE + +/* + * Ethernet configuration + */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_AUTONEG +#define CONFIG_NET_MULTI + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_RARP + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS3,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "AXS# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Misc utility configuration + */ +#define CONFIG_BOUNCE_BUFFER + +#endif /* _CONFIG_AXS101_H_ */ diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index cbf2853549..2f5a6609b8 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -54,6 +54,7 @@ #undef CONFIG_CMD_IMLS #define CONFIG_CMD_USB #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #undef CONFIG_LCD /* @@ -61,7 +62,6 @@ */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -73,7 +73,6 @@ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " #endif #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE \ @@ -86,7 +85,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ /* @@ -129,10 +127,10 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_ENV_IS_IN_FLASH #else diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 5336f69103..6ba4aaf8cb 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -2,7 +2,7 @@ * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -17,7 +17,6 @@ #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #ifndef CONFIG_SYS_TEXT_BASE @@ -87,12 +86,7 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * FLASH related @@ -121,61 +115,6 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -183,15 +122,7 @@ #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ - -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_NAND_CS 1 -#else -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) -#endif /*----------------------------------------------------------------------- * DDR SDRAM @@ -227,7 +158,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ "" diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h new file mode 100644 index 0000000000..104577995e --- /dev/null +++ b/include/configs/bcm28155_ap.h @@ -0,0 +1,140 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BCM28155_AP_H +#define __BCM28155_AP_H + +#include +#include + +/* CPU, chip, mach, etc */ +#define CONFIG_KONA +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_GENERIC_BOARD + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0xae000000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ +#define CONFIG_STACKSIZE SZ_256K + +/* GPIO Driver */ +#define CONFIG_KONA_GPIO + +/* MMC/SD Driver */ +#define CONFIG_SDHCI +#define CONFIG_MMC_SDMA +#define CONFIG_KONA_SDHCI +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC + +#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR +#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR +#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 +#define CONFIG_SYS_SDIO0 "sdio1" +#define CONFIG_SYS_SDIO1 "sdio2" +#define CONFIG_SYS_SDIO2 "sdio3" +#define CONFIG_SYS_SDIO3 "sdio4" + +/* I2C Driver */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_KONA +#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR +#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR +#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR +#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR + +/* Timer Driver */ +#define CONFIG_SYS_TIMER_RATE 32000 +#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ + +/* Init functions */ +#define CONFIG_MISC_INIT_R /* board's misc_init_r function */ + +/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +/* No mtest functions as recommended */ +#undef CONFIG_CMD_MEMORY + +/* + * This is the initial SP which is used only briefly for relocating the u-boot + * image to the top of SDRAM. After relocation u-boot moves the stack to the + * proper place. + */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +/* Serial Info */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +/* Post pad 3 bytes after each reg addr */ +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 13000000 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 0x3e000000 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_NO_FLASH /* Not using NAND/NOR unmanaged flash */ + +/* console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) /* Printbuffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * One partition type must be defined for part.c + * This is necessary for the fatls command to work on an SD card + * for example. + */ +#define CONFIG_DOS_PARTITION + +/* version string, parser, etc */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* Initial upstream - boot to cmd prompt only */ +#define CONFIG_BOOTCOMMAND "" + +/* Commands */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_BOOTZ +#define CONFIG_FAT_WRITE + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#endif /* __BCM28155_AP_H */ diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h new file mode 100644 index 0000000000..fb85c7263b --- /dev/null +++ b/include/configs/bcm_ep_board.h @@ -0,0 +1,113 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BCM_EP_BOARD_H +#define __BCM_EP_BOARD_H + +#include + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_GENERIC_BOARD + +/* + * Memory configuration + * (these must be defined elsewhere) + */ +#ifndef CONFIG_SYS_TEXT_BASE +#error CONFIG_SYS_TEXT_BASE must be defined! +#endif +#ifndef CONFIG_SYS_SDRAM_BASE +#error CONFIG_SYS_SDRAM_BASE must be defined! +#endif +#ifndef CONFIG_SYS_SDRAM_SIZE +#error CONFIG_SYS_SDRAM_SIZE must be defined! +#endif + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_STACKSIZE (256 * 1024) + +/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +/* No mtest functions as recommended */ +#undef CONFIG_CMD_MEMORY + +/* + * This is the initial SP which is used only briefly for relocating the u-boot + * image to the top of SDRAM. After relocation u-boot moves the stack to the + * proper place. + */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Serial Info */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_NO_FLASH /* Not using NAND/NOR unmanaged flash */ + +/* console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) /* Printbuffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * One partition type must be defined for part.c + * This is necessary for the fatls command to work on an SD card + * for example. + */ +#define CONFIG_DOS_PARTITION + +/* version string, parser, etc */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_SYS_LONGHELP + +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* Commands */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +/* SHA hashing */ +#define CONFIG_CMD_HASH +#define CONFIG_HASH_VERIFY +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +/* Enable Time Command */ +#define CONFIG_CMD_TIME + +#define CONFIG_CMD_BOOTZ + +/* Misc utility code */ +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CRC32_VERIFY + +#endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index ce09c2e138..2e0e9224cf 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -75,6 +75,7 @@ #define CONFIG_ROOTPATH "/romfs/brettl2" /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ +#define CONFIG_LIB_RAND #endif @@ -96,7 +97,7 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x12000 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED @@ -111,8 +112,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif @@ -121,8 +122,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -137,7 +138,6 @@ #define CONFIG_MTD_PARTITIONS #define CONFIG_SYS_HUSH_PARSER - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h new file mode 100644 index 0000000000..c7719f389a --- /dev/null +++ b/include/configs/beagle_x15.h @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated. + * Felipe Balbi + * + * Configuration settings for the TI Beagle x15 board. + * See ti_omap5_common.h for omap5 common settings. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BEAGLE_X15_H +#define __CONFIG_BEAGLE_X15_H + +#define CONFIG_AM57XX + +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" + +#define CONFIG_CMD_SAVEENV + +#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_OMAP_ABE_SYSCK + +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + +#include + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +/* CPSW Ethernet */ +#define CONFIG_CMD_NFS +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB + +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#endif /* __CONFIG_BEAGLE_X5_H */ diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 801caca24f..5df460c96b 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -17,14 +17,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra30-common.h" -/* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra30-beaver -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE +/* VDD core PMIC */ +#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 /* High-level configuration options */ #define V_PROMPT "Tegra30 (Beaver) # " @@ -42,10 +40,7 @@ /* I2C */ #define CONFIG_SYS_I2C_TEGRA -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C /* SD/MMC */ #define CONFIG_MMC @@ -73,6 +68,7 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB @@ -80,10 +76,21 @@ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_RTL8169 + /* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +#include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h index 77b6735a70..0b66cdbc01 100644 --- a/include/configs/bf506f-ezkit.h +++ b/include/configs/bf506f-ezkit.h @@ -56,6 +56,7 @@ /* * Flash Settings */ +/* #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_BASE 0x20000000 #define CONFIG_SYS_FLASH_CFI @@ -63,7 +64,8 @@ #define CONFIG_SYS_MAX_FLASH_SECT 71 #define CONFIG_CMD_FLASH #define CONFIG_MONITOR_IS_IN_RAM - +*/ +#define CONFIG_SYS_NO_FLASH /* * SPI Settings @@ -71,19 +73,18 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 +/* #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_CMD_SF #define CONFIG_CMD_SPI - +*/ /* * Env Storage Settings */ #define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 0x400 -#undef CONFIG_CMD_EXPORTENV -#undef CONFIG_CMD_IMPORTENV /* @@ -94,11 +95,11 @@ #define CONFIG_DCACHE_OFF #define CONFIG_UART_CONSOLE 0 #define CONFIG_BAUDRATE 115200 +#define CONFIG_BFIN_SERIAL #define CONFIG_CMD_MEMORY #undef CONFIG_GZIP #undef CONFIG_ZLIB -#undef CONFIG_CMD_BOOTM #undef CONFIG_BOOTM_RTEMS #undef CONFIG_BOOTM_LINUX diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index a97972b81c..50e85ca93c 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -89,7 +89,7 @@ #define CONFIG_PHY_ADDR 3 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -134,8 +134,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -156,7 +156,6 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h index 1f65130f6c..008f4b5ec8 100644 --- a/include/configs/bf525-ucr2.h +++ b/include/configs/bf525-ucr2.h @@ -85,6 +85,7 @@ #define CONFIG_UART_CONSOLE 0 #define CONFIG_BAUDRATE 115200 +#define CONFIG_BFIN_SERIAL #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" #define CONFIG_BOOTCOMMAND "run sfboot" #define CONFIG_BOOTDELAY 5 diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 003109329a..7fc882a133 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -87,7 +87,7 @@ #define CONFIG_HOSTNAME bf526-ezbrd /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -131,8 +131,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h index fa05103e5a..c2958e834e 100644 --- a/include/configs/bf527-ad7160-eval.h +++ b/include/configs/bf527-ad7160-eval.h @@ -119,8 +119,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -137,7 +137,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_UART_CONSOLE 0 - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index db1b6136f3..79e440a0be 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -85,7 +85,7 @@ #define CONFIG_HOSTNAME bf527-ezkit /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -134,8 +134,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -180,7 +180,6 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h index c0e8b5adc8..b374ab5772 100644 --- a/include/configs/bf527-sdp.h +++ b/include/configs/bf527-sdp.h @@ -103,8 +103,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -113,7 +113,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_UART_CONSOLE 0 - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index beab1271a4..0fda967ac2 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -111,7 +111,6 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 7144c6319f..ae4d83a8f1 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -80,33 +80,8 @@ /* * Software (bit-bang) I2C driver configuration */ -#define PF_SCL PF3 -#define PF_SDA PF2 -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); \ - *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); \ - *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); \ - asm("ssync;") -#define I2C_SDA(bit) if (bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if (bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - +#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 +#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 /* * Flash Settings @@ -123,10 +98,11 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 +/* #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_ALL - +*/ /* * Env Storage Settings @@ -155,8 +131,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index feb9d7344a..6df89af402 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -89,6 +89,7 @@ /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */ +#define CONFIG_LIB_RAND /* * Flash Settings @@ -120,8 +121,8 @@ /* * I2C settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_SYS_I2C_SLAVE 0 @@ -136,6 +137,7 @@ #define CONFIG_BAUDRATE 57600 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BFIN_SERIAL #define CONFIG_PANIC_HANG 1 #define CONFIG_RTC_BFIN 1 diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 62bd3bf085..4f2b2cbf29 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -67,7 +67,7 @@ #define CONFIG_HOSTNAME bf537-pnav /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -111,8 +111,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif @@ -142,8 +142,8 @@ /* * I2C settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 1de8ffe2df..d01d88f3b4 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -88,7 +88,7 @@ #define CONFIG_ROOTPATH "/romfs" /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -120,8 +120,8 @@ /* * I2C settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_SYS_I2C_SLAVE 0 @@ -136,6 +136,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BFIN_SERIAL #define CONFIG_PANIC_HANG 1 #define CONFIG_RTC_BFIN 1 diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 25cebf880f..7b5a5a7f71 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -67,7 +67,7 @@ #define CONFIG_HOSTNAME bf537-stamp /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -118,8 +118,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif @@ -128,8 +128,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 77822e792f..e60558e1b6 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -83,10 +83,11 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 +/* #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_ALL - +*/ /* * Env Storage Settings @@ -115,8 +116,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif @@ -125,8 +126,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -135,7 +136,6 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index da5f029435..e71e6d324c 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -134,8 +134,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index ee585c0ffd..6871d8c422 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -53,7 +53,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 #define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) @@ -161,7 +161,6 @@ #define CONFIG_BAUDRATE 57600 #define CONFIG_SYS_PROMPT "Acvilon> " - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 404039ac23..fb6f94873a 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -90,6 +90,7 @@ */ #define CONFIG_SYS_I2C_SOFT #ifdef CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 1a43e1b433..878009ff66 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -72,16 +72,17 @@ #define CONFIG_NET_MULTI #define CONFIG_HOSTNAME "bf609-ezkit" #define CONFIG_DESIGNWARE_ETH +#define CONFIG_PHY_ADDR 1 #define CONFIG_DW_PORTS 1 -#define CONFIG_DW_AUTONEG #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_MII +#define CONFIG_PHYLIB /* i2c Settings */ -#define CONFIG_BFIN_TWI_I2C -#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* * Flash Settings diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 08ccce0b9a..143d3ddd2d 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -17,6 +17,7 @@ # define CONFIG_BOOTP_DNS # define CONFIG_BOOTP_NTPSERVER # define CONFIG_BOOTP_RANDOM_DELAY +# define CONFIG_LIB_RAND # define CONFIG_KEEP_SERVERADDR # define CONFIG_CMD_DNS # define CONFIG_CMD_PING @@ -38,6 +39,7 @@ # define CONFIG_CMD_FAT # define CONFIG_CMD_MMC # define CONFIG_DOS_PARTITION +# define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 # endif # ifdef CONFIG_MMC_SPI # define CONFIG_CMD_MMC_SPI @@ -71,7 +73,7 @@ # ifdef CONFIG_SPI_FLASH # define CONFIG_CMD_SF # endif -# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) +# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT) # define CONFIG_CMD_I2C # define CONFIG_SOFT_I2C_READ_REPEATED_START # endif @@ -299,7 +301,7 @@ /* * I2C Settings */ -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT) # ifndef CONFIG_SYS_I2C_SPEED # define CONFIG_SYS_I2C_SPEED 50000 # endif diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h new file mode 100644 index 0000000000..3b93ff600e --- /dev/null +++ b/include/configs/bg0900.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_BG0900_H__ +#define __CONFIGS_BG0900_H__ + +/* System configurations */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_NOWHERE + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_NET_MULTI +#endif + +/* SPI */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_DEFAULT_SPI_BUS 2 +#define CONFIG_DEFAULT_SPI_CS 0 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 + +/* SPI FLASH */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define CONFIG_ENV_SPI_BUS 2 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 40000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#endif + +#endif + +/* Boot Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200" +#define CONFIG_BOOTCOMMAND "bootm" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_spi_firmware_filename=u-boot.sb\0" \ + "update_spi_firmware_maxsz=0x80000\0" \ + "update_spi_firmware=" /* Update the SPI flash firmware */ \ + "if sf probe 2:0 ; then " \ + "if tftp ${update_spi_firmware_filename} ; then " \ + "sf erase 0x0 +${filesize} ; " \ + "sf write ${loadaddr} 0x0 ${filesize} ; " \ + "fi ; " \ + "fi\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_BG0900_H__ */ diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 5b3aac7954..7de425349f 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -195,6 +195,7 @@ #define CONFIG_BAUDRATE 57600 #define CONFIG_LOADS_ECHO 1 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BFIN_SERIAL /* * I2C settings diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index cd37f9adb9..6e5774c6ba 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -177,6 +177,7 @@ #define CONFIG_BAUDRATE 57600 #define CONFIG_LOADS_ECHO 1 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BFIN_SERIAL /* * U-Boot environment variables. Use "printenv" to examine. diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h deleted file mode 100644 index 33e04963e6..0000000000 --- a/include/configs/bluestone.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * bluestone.h - configuration for Bluestone (APM821XX) - * - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_APM821XX 1 /* APM821XX series */ -#define CONFIG_HOSTNAME bluestone - -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_440 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 -#endif - -/* - * Include common defines/options for all AMCC eval boards - */ -#include "amcc-common.h" -#define CONFIG_SYS_CLK_FREQ 50000000 - -#define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -/* EBC stuff */ -/* later mapped to this addr */ -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */ - -/* EBC Boot Space: 0xFF000000 */ -#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ -#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ - -#define CONFIG_SYS_SRAM_SIZE (256 << 10) -/* - * Initial RAM & stack pointer (placed in OCM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Environment - */ -/* - * Define here the location of the environment variables (FLASH). - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/* - * FLASH related - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 80 -/* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 -/* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -/* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/* SDRAM */ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ -#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ -#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ -#define CONFIG_DDR_ECC 1 /* with ECC support */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ - -/* - * I2C - */ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ - -/* I2C bootstrap EEPROM */ -#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 -#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 -#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 - -/* - * Ethernet - */ -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII -#define CONFIG_HAS_ETH0 -/* PHY address, See schematics */ -#define CONFIG_PHY_ADDR 0x1f -/* reset phy upon startup */ -#define CONFIG_PHY_RESET 1 -/* Include GbE speed/duplex detection */ -#define CONFIG_PHY_GIGE 1 -#define CONFIG_PHY_DYNAMIC_ANEG 1 - -/* - * External Bus Controller (EBC) Setup - **/ -#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ - EBC_CFG_PTD_ENABLE | \ - EBC_CFG_RTC_2048PERCLK | \ - EBC_CFG_ATC_HI | \ - EBC_CFG_DTC_HI | \ - EBC_CFG_CTC_HI | \ - EBC_CFG_OEO_PREVIOUS) -/* NOR Flash */ -#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(64) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(1) | \ - EBC_BXAP_OEN_ENCODE(2) | \ - EBC_BXAP_WBN_ENCODE(2) | \ - EBC_BXAP_WBF_ENCODE(2) | \ - EBC_BXAP_TH_ENCODE(7) | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED) -/* Peripheral Bank Configuration Register - EBC_BxCR */ -#define CONFIG_SYS_EBC_PB0CR \ - (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ - EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_8BIT) - - -#endif /* __CONFIG_H */ diff --git a/include/configs/br4.h b/include/configs/br4.h index ef3752dcd5..48cf184826 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -102,8 +102,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C -#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -136,7 +136,6 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_LOADADDR 0x2000000 - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 9301fccbdc..ea7b104729 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -2,7 +2,7 @@ * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h new file mode 100644 index 0000000000..e9d5d01620 --- /dev/null +++ b/include/configs/bur_am335x_common.h @@ -0,0 +1,196 @@ +/* + * bur_am335x_common.h + * + * common parts used by B&R AM335x based boards + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BUR_AM335X_COMMON_H__ +#define __BUR_AM335X_COMMON_H__ +/* ------------------------------------------------------------------------- */ +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_AM33XX +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* Timer information */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_POWER_TPS65217 + +#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */ + +#include + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_BAUDRATE 115200 + +/* Network defines */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 4 +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_PHYLIB +#define CONFIG_PHY_NATSEMI +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif /* !CONFIG_SPL_BUILD, ... */ +/* + * Our DDR memory always starts at 0x80000000 and U-Boot shall have + * relocated itself to higher in memory by the time this value is used. + */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +/* + * ---------------------------------------------------------------------------- + * DDR information. We say (for simplicity) that we have 1 bank, + * always, even when we have more. We always start at 0x80000000, + * and we place the initial stack pointer in our SRAM. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX +#define CONFIG_CMD_I2C +/* GPIO */ +#define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO +/* + * ---------------------------------------------------------------------------- + * The following are general good-enough settings for U-Boot. We set a + * large malloc pool as we generally have a lot of DDR, and we opt for + * function over binary size in the main portion of U-Boot as this is + * generally easily constrained later if needed. We enable the config + * options that give us information in the environment about what board + * we are on so we do not need to rely on the command prompt. We set a + * console baudrate of 115200 and use the default baud rate table. + */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# " +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* + * For commands to use, we take the default list and add a few other + * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH + * prior to this include, in order to skip a few commands. When we do + * have flash, if we expect these commands they must be enabled in that + * config. If desired, a specific list of desired commands can be used + * instead. + */ +#include +/* undefine commands, which we do not need */ +#undef CONFIG_CMD_EDITENV +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG +/* define command we need always */ +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE + +/* + * Our platforms make use of SPL to initalize the hardware (primarily + * memory) enough for full U-Boot to be loaded. We also support Falcon + * Mode so that the Linux kernel can be booted directly from SPL + * instead, if desired. We make use of the general SPL framework found + * under common/spl/. Given our generally common memory map, we set a + * number of related defaults and sizes here. + */ +#define CONFIG_SPL_FRAMEWORK +/* + * Place the image at the start of the ROM defined image space. + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. We load U-Boot itself into memory at + * 0x80800000 for legacy reasons (to not conflict with older SPLs). We + * have our BSS be placed 1MiB after this, to allow for the default + * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. + * We have the SPL malloc pool at the end of the BSS area. + * + * ---------------------------------------------------------------------------- + */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#undef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SPL_BSS_START_ADDR 0x80A00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN + +/* General parts of the framework, required. */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* ! __BUR_AM335X_COMMON_H__ */ diff --git a/include/configs/calimain.h b/include/configs/calimain.h index c76bc2cbe6..656dda6aee 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 OMICRON electronics GmbH + * Copyright (C) 2011-2014 OMICRON electronics GmbH * * Based on da850evm.h. Original Copyrights follow: * @@ -18,20 +18,17 @@ #define CONFIG_DRIVER_TI_EMAC #define MACH_TYPE_CALIMAIN 3528 #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN +#define CONFIG_SYS_GENERIC_BOARD /* * SoC Configuration */ #define CONFIG_MACH_DAVINCI_CALIMAIN -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0x60000000 #define CONFIG_DA850_LOWLEVEL #define CONFIG_SYS_DA850_PLL_INIT @@ -185,7 +182,6 @@ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 0f3f61a0d5..ae0abc7c74 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -4,7 +4,7 @@ * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -14,11 +14,8 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM365 #define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM @@ -49,7 +46,6 @@ #define CONFIG_EMAC_MDIO_PHY_NUM 0 #define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */ #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME @@ -59,10 +55,10 @@ #define CONFIG_RESET_PHY_R /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI @@ -201,7 +197,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBGENERIC_SUPPORT @@ -217,6 +212,8 @@ #define CONFIG_SPL_STACK (0x00010000 + 0x7f00) #define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/ +/* Provide at least 16MB spacing between us and the Linux Kernel image */ +#define CONFIG_SPL_PAD_TO 12320 #define CONFIG_SPL_MAX_FOOTPRINT 12288 #ifndef CONFIG_SPL_BUILD @@ -236,6 +233,8 @@ #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_ECCSIZE 0x200 #define CONFIG_SYS_NAND_ECCBYTES 10 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 7b90dcb5ac..c90179380f 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -2,7 +2,7 @@ * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -13,8 +13,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ /* @@ -174,7 +173,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -189,8 +187,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index f6faeec06c..8eeb15c0e1 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -33,7 +33,6 @@ #endif #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF80000 @@ -126,78 +125,9 @@ /* * Define here the location of the environment variables (FLASH). */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */ -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif - -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - * - * This is the first official implementation of booting from 2k page sized - * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8) - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */ - /* this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE) - /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif /*----------------------------------------------------------------------- * FLASH related @@ -236,7 +166,6 @@ /*------------------------------------------------------------------------------ * DDR SDRAM *----------------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) #if !defined(CONFIG_ARCHES) /* * NAND booting U-Boot version uses a fixed initialization, since the whole @@ -309,7 +238,6 @@ #define CONFIG_SYS_SDRAM0_MMODE 0x00000432 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000004 #endif /* !defined(CONFIG_ARCHES) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) */ #define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */ @@ -422,7 +350,6 @@ CONFIG_AMCC_DEF_ENV \ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ @@ -557,15 +484,6 @@ * 0xfe00.0000 -> 4.ce00.0000 */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -/* Memory Bank 3 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x10055e00 -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) - -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ -#else /* Memory Bank 0 (NOR-FLASH) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x10055e00 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) @@ -575,7 +493,6 @@ #define CONFIG_SYS_EBC_PB3AP 0x018003c0 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ #endif -#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ #if !defined(CONFIG_ARCHES) /* Memory Bank 2 (CPLD) initialization */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 4abb03ea56..5e13b655c2 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -17,19 +17,21 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra30-common.h" -/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE +/* VDD core PMIC */ +#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 /* High-level configuration options */ #define V_PROMPT "Tegra30 (Cardhu) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" +#define BOARD_EXTRA_ENV_SETTINGS \ + "board_name=cardhu-a04\0" \ + "fdtfile=tegra30-cardhu-a04.dtb\0" + /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA @@ -41,12 +43,7 @@ /* I2C */ #define CONFIG_SYS_I2C_TEGRA -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C /* SD/MMC */ #define CONFIG_MMC @@ -81,6 +78,16 @@ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_RTL8169 + /* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 5cf456a78e..6ee2dd403b 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -13,7 +13,6 @@ #ifndef __CONFIG_CGTQMX6EVAL_H #define __CONFIG_CGTQMX6EVAL_H -#define CONFIG_MX6 #include "mx6_common.h" @@ -75,13 +74,13 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "boot_dir=/boot\0" \ "console=ttymxc1\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x11000000\0" \ + "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "mmcdev=1\0" \ "mmcpart=1\0" \ @@ -92,24 +91,24 @@ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${boot_dir}/${uimage}\0" \ + "loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${boot_dir}/${image}\0" \ "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \ "${boot_dir}/${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -118,7 +117,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else "\ "echo ERR: Fail to boot from mmc; " \ @@ -143,7 +142,6 @@ #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/charon.h b/include/configs/charon.h index 88ac4ad327..2f537e0d4b 100644 --- a/include/configs/charon.h +++ b/include/configs/charon.h @@ -8,7 +8,7 @@ * (C) Copyright 2010 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_CHARON_H diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h new file mode 100644 index 0000000000..7b460e83c4 --- /dev/null +++ b/include/configs/chromebook_link.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_X86_MRC_ADDR 0xfffa0000 +#define CONFIG_CACHE_MRC_SIZE_KB 512 + +#define CONFIG_X86_SERIAL + +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} + +#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 + +#define CONFIG_PCI_MEM_BUS 0xe0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x1000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xefff + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_BIOSEMU +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC +#define CONFIG_ARCH_EARLY_INIT_R + +#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x003f8000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index b15a1eb7a2..643c8379aa 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -85,7 +85,7 @@ #define CONFIG_HOSTNAME cm-bf527 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -113,8 +113,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -129,7 +129,6 @@ "flashboot=flread 20040000 1000000 300000;" \ "bootm 0x1000000\0" - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index e2b954c063..485f01a01c 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -98,7 +98,6 @@ #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 77f47d9457..e05956846c 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -55,7 +55,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) @@ -73,7 +73,7 @@ #define CONFIG_HOSTNAME cm-bf537e /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -112,8 +112,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif @@ -122,8 +122,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -145,7 +145,7 @@ #define FLASHBOOT_ENV_SETTINGS \ "flashboot=flread 20040000 1000000 3c0000;" \ "bootm 0x1000000\0" - +#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 55e61d674f..1f26457a95 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -54,7 +54,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) @@ -71,7 +71,7 @@ #define CONFIG_HOSTNAME cm-bf537u /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -110,8 +110,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif @@ -120,8 +120,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -142,7 +142,7 @@ #define FLASHBOOT_ENV_SETTINGS \ "flashboot=flread 20040000 1000000 300000;" \ "bootm 0x1000000\0" - +#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index 3c9eeb58a3..72eafc5699 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -104,8 +104,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -118,6 +118,8 @@ #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" +#define CONFIG_ADI_GPIO2 + #ifndef __ADSPBF542__ /* Don't waste time transferring a logo over the UART */ # if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 93e3c8677e..96910a7afd 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -100,7 +100,6 @@ #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h index b40199566e..1cb54b3225 100644 --- a/include/configs/cm4008.h +++ b/include/configs/cm4008.h @@ -3,7 +3,7 @@ * Greg Ungerer . * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H @@ -75,8 +75,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ -#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */ - /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h index d792240e95..adebd4b7b0 100644 --- a/include/configs/cm41xx.h +++ b/include/configs/cm41xx.h @@ -3,7 +3,7 @@ * Greg Ungerer . * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H @@ -75,8 +75,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ -#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */ - /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index cfd63ad831..93938642fa 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -2,17 +2,21 @@ * (C) Copyright 2003-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + + /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ #define CONFIG_SYS_TEXT_BASE 0xfc000000 @@ -283,7 +287,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -296,7 +299,6 @@ #define CONFIG_LOOPW 1 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* * Various low-level settings diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h new file mode 100644 index 0000000000..42be7fcafd --- /dev/null +++ b/include/configs/cm_fx6.h @@ -0,0 +1,298 @@ +/* + * Config file for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_CM_FX6_H +#define __CONFIG_CM_FX6_H + +#include +#include +#include "mx6_common.h" + +/* Machine config */ +#define CONFIG_SYS_LITTLE_ENDIAN +#define CONFIG_MACH_TYPE 4273 + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM +#define CONFIG_CMD_DM + +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO + +#define CONFIG_DM_SERIAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#endif + +/* Display information on boot */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_TIMESTAMP + +/* CMD */ +#include +#define CONFIG_CMD_GREPENV +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMLS + +/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* RAM */ +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Serial console */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Shell */ +#define CONFIG_SYS_PROMPT "CM-FX6 # " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* SPI flash */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + +/* Environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (768 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel=uImage-cm-fx6\0" \ + "autoload=no\0" \ + "loadaddr=0x10800000\0" \ + "fdtaddr=0x11000000\0" \ + "console=ttymxc3,115200\0" \ + "ethprime=FEC0\0" \ + "bootscr=boot.scr\0" \ + "bootm_low=18000000\0" \ + "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ + "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ + "fdtfile=cm-fx6.dtb\0" \ + "doboot=bootm ${loadaddr}\0" \ + "loadfdt=false\0" \ + "setboottypez=setenv kernel zImage-cm-fx6;" \ + "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ + "setenv loadfdt true;\0" \ + "setboottypem=setenv kernel uImage-cm-fx6;" \ + "setenv doboot bootm ${loadaddr};" \ + "setenv loadfdt false;\0"\ + "run_eboot=echo Starting EBOOT ...; "\ + "mmc dev ${mmcdev} && " \ + "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ + "mmcdev=2\0" \ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \ + "mmcbootscript=echo Running bootscript from mmc ...; "\ + "source ${loadaddr}\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} " \ + "${video}\0" \ + "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ + "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "run doboot\0" \ + "satadev=0\0" \ + "sataroot=/dev/sda2 rw rootwait\0" \ + "sataargs=setenv bootargs console=${console} " \ + "root=${sataroot} " \ + "${video}\0" \ + "loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \ + "satabootscript=echo Running bootscript from sata ...; " \ + "source ${loadaddr}\0" \ + "sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \ + "sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \ + "sataboot=echo Booting from sata ...; "\ + "run sataargs; " \ + "run doboot\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=ubifs\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} " \ + "${video}\0" \ + "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 0 780000; " \ + "if ${loadfdt}; then " \ + "run nandloadfdt;" \ + "fi; " \ + "run doboot\0" \ + "boot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "if run loadmmcbootscript; then " \ + "run mmcbootscript;" \ + "else " \ + "if run mmcloadkernel; then " \ + "if ${loadfdt}; then " \ + "run mmcloadfdt;" \ + "fi;" \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "if sata init; then " \ + "if run loadsatabootscript; then " \ + "run satabootscript;" \ + "else "\ + "if run sataloadkernel; then " \ + "if ${loadfdt}; then " \ + "run sataloadfdt; " \ + "fi;" \ + "run sataboot;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "run nandboot\0" + +#define CONFIG_BOOTCOMMAND \ + "run setboottypem; run boot" + +/* SPI */ +#define CONFIG_SPI +#define CONFIG_MXC_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_WINBOND + +/* NAND */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_MXS +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* APBH DMA is required for NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RGMII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_ARP_TIMEOUT 200UL +#define CONFIG_NET_RETRY_COUNT 5 + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 2 + +/* SATA */ +#define CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_LIBATA +#define CONFIG_LBA48 +#define CONFIG_DWC_AHSATA +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + +/* GPIO */ +#define CONFIG_MXC_GPIO + +/* Boot */ +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* misc */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_STACKSIZE (128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_OF_BOARD_SETUP + +/* SPL */ +#include "imx6_spl.h" +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */ +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024) +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) +#define CONFIG_SPL_SPI_LOAD + +#endif /* __CONFIG_CM_FX6_H */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h new file mode 100644 index 0000000000..767ef3a266 --- /dev/null +++ b/include/configs/cm_t335.h @@ -0,0 +1,186 @@ +/* + * Config file for Compulab CM-T335 board + * + * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ + * + * Author: Ilya Ledvich + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_CM_T335_H +#define __CONFIG_CM_T335_H + +#define CONFIG_CM_T335 +#define CONFIG_NAND + +#include + +#undef CONFIG_BOARD_LATE_INIT +#undef CONFIG_SPI +#undef CONFIG_OMAP3_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_SPL_OS_BOOT +#undef CONFIG_BOOTCOUNT_LIMIT +#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC + +#undef CONFIG_MAX_RAM_BANK_SIZE +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "CM-T335 # " + +#define CONFIG_OMAP_COMMON + +#define MACH_TYPE_CM_T335 4586 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 + +/* Clock Defines */ +#define V_OSCK 25000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ + +#ifndef CONFIG_SPL_BUILD +#define MMCARGS \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "mmcrootfstype=ext4\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" + +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandroot=ubi0:rootfs rw\0" \ + "nandrootfstype=ubifs\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} " \ + "ubi.mtd=${rootfs_name}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nboot ${loadaddr} nand0 900000; " \ + "bootm ${loadaddr}\0" + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=82000000\0" \ + "console=ttyO0,115200n8\0" \ + "rootfs_name=rootfs\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + MMCARGS \ + NANDARGS + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_TIMESTAMP +#define CONFIG_SYS_AUTOLOAD "no" + +/* Serial console configuration */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SERIAL1 1 /* UART0 */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_BAUDRATE 115200 + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 + +/* SPL */ +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +/* Network. */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* NAND support */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#undef CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +#define CONFIG_CMD_NAND +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \ + "1m(u-boot),1m(u-boot-env)," \ + "1m(dtb),4m(splash)," \ + "6m(kernel),-(rootfs)" +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x400000 /* un-assigned: (using dtb) */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif + +/* GPIO pin + bank to pin ID mapping */ +#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) + +/* Status LED */ +#define CONFIG_STATUS_LED +#define CONFIG_GPIO_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define STATUS_LED_BIT GPIO_PIN(2, 0) +/* Status LED polarity is inversed, so init it in the "off" state */ +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BOOT 0 + +#ifndef CONFIG_SPL_BUILD +/* + * Enable PCA9555 at I2C0-0x26. + * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. + */ +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } +#endif /* CONFIG_SPL_BUILD */ + +#endif /* __CONFIG_CM_T335_H */ + diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 39a216e835..9767512a5c 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -21,11 +21,11 @@ * High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ - -#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SDRC /* The chip has SDRC controller */ @@ -45,13 +45,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT 1 -/* - * The early kernel mapping on ARM currently only maps from the base of DRAM - * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. - * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, - * so that leaves DRAM base to DRAM base + 0x4000 available. - */ -#define CONFIG_SYS_BOOTMAPSZ 0x4000 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS @@ -102,8 +95,6 @@ #define CONFIG_USB_OMAP3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT_OMAP #define CONFIG_USB_STORAGE #define CONFIG_MUSB_UDC #define CONFIG_TWL4030_USB @@ -139,12 +130,13 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 #define CONFIG_I2C_MULTI_BUS /* @@ -163,18 +155,17 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ + /* Environment information */ -#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "mpurate=500\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ @@ -188,7 +179,6 @@ "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ @@ -196,7 +186,6 @@ "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ @@ -212,6 +201,7 @@ "nand read ${loadaddr} 2a0000 400000; " \ "bootm ${loadaddr}\0" \ +#define CONFIG_CMD_BOOTZ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -257,7 +247,6 @@ */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -270,9 +259,6 @@ */ /* **** PISMO SUPPORT *** */ -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ @@ -301,12 +287,13 @@ /* Status LED */ #define CONFIG_STATUS_LED /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED -#define STATUS_LED_GREEN 0 -#define STATUS_LED_BIT STATUS_LED_GREEN +#define CONFIG_GPIO_LED +#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ +#define GREEN_LED_DEV 0 +#define STATUS_LED_BIT GREEN_LED_GPIO #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_BOOT STATUS_LED_BIT -#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ +#define STATUS_LED_BOOT GREEN_LED_DEV #define CONFIG_SPLASHIMAGE_GUARD @@ -317,6 +304,7 @@ /* Display Configuration */ #define CONFIG_OMAP3_GPIO_2 +#define CONFIG_OMAP3_GPIO_5 #define CONFIG_VIDEO_OMAP3 #define LCD_BPP LCD_COLOR16 @@ -324,5 +312,70 @@ #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP +#define CONFIG_SCF0403_LCD + +#define CONFIG_OMAP3_SPI + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +/* + * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: + * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT + */ +#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12 } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* + * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the + * older x-loader implementations. And move the BSS area so that it + * doesn't overlap with TEXT_BASE. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #endif /* __CONFIG_H */ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h new file mode 100644 index 0000000000..918032bd75 --- /dev/null +++ b/include/configs/cm_t3517.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2013 CompuLab, Ltd. + * Author: Igor Grinberg + * + * Configuration settings for the CompuLab CM-T3517 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_CM_T3517 /* working with CM-T3517 */ +#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * This is needed for the DMA stuff. + * Although the default iss 64, we still define it + * to be on the safe side once the default is changed. + */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include /* get chip and board defs */ +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT +/* + * The early kernel mapping on ARM currently only maps from the base of DRAM + * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. + * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, + * so that leaves DRAM base to DRAM base + 0x4000 available. + */ +#define CONFIG_SYS_BOOTMAPSZ 0x4000 + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +#define CONFIG_OMAP_GPIO + +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_USB_MUSB_AM35X + +#ifndef CONFIG_USB_MUSB_AM35X +#define CONFIG_USB_OMAP3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 +#else /* !CONFIG_USB_MUSB_AM35X */ +#define CONFIG_MUSB_HOST +#define CONFIG_MUSB_PIO_ONLY +#endif /* CONFIG_USB_MUSB_AM35X */ + +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* commands to include */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),256k(u-boot-env),"\ + "4m(kernel),-(fs)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_GPIO + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 400000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 +#define CONFIG_I2C_MULTI_BUS + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "baudrate=115200\0" \ + "console=ttyO2,115200n8\0" \ + "mpurate=auto\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "mmcrootfstype=ext4\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 2a0000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_CMD_BOOTZ +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_TIMESTAMP +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "CM-T3517 # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define CONFIG_SYS_CS0_SIZE (256 << 20) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) +#endif /* CONFIG_CMD_NET */ + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Status LED */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_GPIO_LED +#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ +#define GREEN_LED_DEV 0 +#define STATUS_LED_BIT GREEN_LED_GPIO +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BOOT GREEN_LED_DEV + +/* GPIO banks */ +#ifdef CONFIG_STATUS_LED +#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ +#endif + +/* Display Configuration */ +#define CONFIG_OMAP3_GPIO_2 +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_VIDEO_OMAP3 +#define LCD_BPP LCD_COLOR16 + +#define CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASHIMAGE_GUARD +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_SCF0403_LCD + +#define CONFIG_OMAP3_SPI + +#endif /* __CONFIG_H */ diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h new file mode 100644 index 0000000000..0cd4aec7e2 --- /dev/null +++ b/include/configs/cm_t54.h @@ -0,0 +1,165 @@ +/* + * Config file for Compulab CM-T54 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Dmitry Lifshitz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_CM_T54_H +#define __CONFIG_CM_T54_H + +#define CONFIG_CM_T54 +#define CONFIG_DRAM_2G + +#include + +#undef CONFIG_SPL_OS_BOOT + +/* Enable Generic board */ +#define CONFIG_SYS_GENERIC_BOARD + +/* Device Tree defines */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* EEPROM related defines */ +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 + +/* Enable SD/MMC CD and WP GPIOs */ +#define OMAP_HSMMC_USE_GPIO + +/* UART setup */ +#define CONFIG_CONS_INDEX 4 +#define CONFIG_SYS_NS16550_COM4 UART4_BASE +#define CONFIG_BAUDRATE 115200 + +/* SD/MMC RAW boot */ +#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR +#undef CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* 0x40000 - 256 KB */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 /* 384 KB */ + +/* MMC ENV related defines */ +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_SIZE + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_OFFSET 0xc0000 /* (in bytes) 768 KB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_CMD_SAVEENV + +/* Enhance our eMMC support / experience. */ +#define CONFIG_HSMMC2_8BIT +#define CONFIG_SUPPORT_EMMC_BOOT + +/* SATA Boot related defines */ +#define CONFIG_SPL_SATA_SUPPORT +#define CONFIG_SPL_SATA_BOOT_DEVICE 0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 + +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +/* USB UHH support options */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 76 /* HSIC2 HUB #RESET */ +#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 83 /* HSIC3 ETH #RESET */ + +/* Enabled commands */ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_PING + +/* USB Networking options */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 + +/* Max time to hold reset on this board, see doc/README.omap-reset-time */ +#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 + +/* + * Miscellaneous configurable options + */ +#undef CONFIG_SYS_AUTOLOAD +#undef CONFIG_SYS_PROMPT +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_BOOTDELAY + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_SYS_PROMPT "CM-T54 # " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "baudrate=115200\0" \ + "bootdelay=3\0" \ + "autoload=no\0" \ + "bootscr=bootscr.img\0" \ + "fdtfile=omap5-sbc-t54.dtb\0" \ + "kernel=zImage-cm-t54\0" \ + "ramdisk=ramdisk-cm-t54.img\0" \ + "console=ttyO3\0" \ + "ramdisksize=16384\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk1p2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} rw rootwait\0" \ + "ramroot=/dev/ram0\0" \ + "ramargs=setenv bootargs console=${console} " \ + "root=${ramroot} ramdisk_size=${ramdisksize} rw\0" \ + "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ + "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "mmcloadramdisk=load mmc ${mmcdev} ${rdaddr} ${ramdisk}\0" \ + "mmcloadbootscript=load mmc ${mmcdev} ${loadaddr} ${bootsrc}\0" \ + "mmcbootscript=echo Running bootscript from mmc${mmcdev}...; " \ + "source ${loadaddr}\0" \ + "mmcbootlinux=echo Booting from mmc${mmcdev} ...; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "mmcboot=if mmc dev ${mmcdev} && mmc rescan; then " \ + "if run mmcloadbootscript; " \ + "then run mmcbootscript; " \ + "fi; " \ + "if run mmcloadkernel; then " \ + "if run mmcloadfdt; then " \ + "if run mmcloadramdisk; then " \ + "run ramargs; " \ + "run mmcbootlinux; " \ + "fi; " \ + "run mmcargs; " \ + "setenv rdaddr - ; " \ + "run mmcbootlinux; " \ + "fi; " \ + "fi; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "bootcmd=run mmcboot || setenv mmcdev 1; setenv mmcroot /dev/mmcblk0p2; run mmcboot;" + +#endif /* __CONFIG_CM_T54_H */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index 417c873574..32cecbdc9c 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -82,7 +82,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -97,8 +96,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ - #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 885dfd4761..464436930d 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -3,7 +3,7 @@ * * (C) Copyright 2003 Josef Baumgartner * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* --- @@ -37,11 +37,9 @@ /* --- * Defines processor clock - important for correct timings concerning serial * interface etc. - * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms * --- */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 66000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ diff --git a/include/configs/cogent_common.h b/include/configs/cogent_common.h deleted file mode 100644 index 1b5d6a5656..0000000000 --- a/include/configs/cogent_common.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen, CSIRO-MST - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_COGENT_COMMON_H -#define _CONFIG_COGENT_COMMON_H - -/* - * Cogent Motherboard Capabilities - */ -#define CMA_MB_CAP_SERPAR 0x0001 /* has dual serial+parallel (16C552) */ -#define CMA_MB_CAP_LCD 0x0002 /* has LCD display (HD44780) */ -#define CMA_MB_CAP_FLASH 0x0004 /* has flash (E28F800B or AM29F800BB) */ -#define CMA_MB_CAP_RTC 0x0008 /* has RTC+NVRAM (MK48T02) */ -#define CMA_MB_CAP_ETHER 0x0010 /* has Ethernet (MB86964) */ -#define CMA_MB_CAP_SLOT1 0x0020 /* has CMABus slot 1 */ -#define CMA_MB_CAP_SLOT2 0x0040 /* has CMABus slot 2 */ -#define CMA_MB_CAP_SLOT3 0x0080 /* has CMABus slot 3 */ -#define CMA_MB_CAP_KBM 0x0100 /* has PS/2 keyboard+mouse (HT6542B) */ -#define CMA_MB_CAP_SER2 0x0200 /* has 2nd dual serial (16C2552) */ -#define CMA_MB_CAP_PCI 0x0400 /* has pci bridge (V360EPC) */ -#define CMA_MB_CAP_PCI_EXT 0x0800 /* can access extended pci space */ -#define CMA_MB_CAP_PCI_ETHER 0x1000 /* has 10/100 ether on PCI (GD82559) */ -#define CMA_MB_CAP_PCI_VIDEO 0x2000 /* has video int'face on PCI (B69000) */ -#define CMA_MB_CAP_PCI_CARDBUS 0x4000 /* has Cardbus Ctlr on PCI (PD6832) */ - -/* - * Cogent option sanity checking - */ - -#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \ - defined(CONFIG_MPC850) || defined(CONFIG_MPC860) - -/* - * check a PowerPC 8xx cpu module has been selected - */ - -# if defined(CONFIG_CMA286_21) - -# define COGENT_CPU_MODULE "CMA286-21" - -# elif defined(CONFIG_CMA286_60_OLD) - -# define COGENT_CPU_MODULE "CMA286-60 (old)" - -# elif defined(CONFIG_CMA286_60) - -# define COGENT_CPU_MODULE "CMA286-60" - -# elif defined(CONFIG_CMA286_60P) - -# define COGENT_CPU_MODULE "CMA286-60P" - -# elif defined(CONFIG_CMA287_21) - -# define COGENT_CPU_MODULE "CMA287-21" - -# elif defined(CONFIG_CMA287_50) - -# define COGENT_CPU_MODULE "CMA287-50" - -# else - -# error Cogent CPU Module must be a PowerPC MPC8xx module - -# endif - -#elif defined(CONFIG_MPC8260) - -/* - * check a PowerPC 8260 cpu module has been selected - */ - -# if defined(CONFIG_CMA282) - -# define COGENT_CPU_MODULE "CMA282" - -# else - -# error Cogent CPU Module must be a PowerPC MPC8260 module - -# endif - -#else - -# error CPU type must be PowerPC 8xx or 8260 - -#endif - -/* - * check a motherboard has been selected - * define the motherboard capabilities while we're at it - */ - -#if defined(CONFIG_CMA101) - -# define COGENT_MOTHERBOARD "CMA101" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \ - CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \ - CMA_MB_CAP_SLOT3) -# define CMA_MB_NSLOTS 3 - -#elif defined(CONFIG_CMA102) - -# define COGENT_MOTHERBOARD "CMA102" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \ - CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3) -# define CMA_MB_NSLOTS 3 - -#elif defined(CONFIG_CMA110) - -# define COGENT_MOTHERBOARD "CMA110" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ - CMA_MB_CAP_KBM | CMA_MB_CAP_PCI) -# define CMA_MB_NSLOTS 0 - -#elif defined(CONFIG_CMA111) - -# define COGENT_MOTHERBOARD "CMA111" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ - CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \ - CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \ - CMA_MB_CAP_PCI_ETHER) -# define CMA_MB_NSLOTS 1 - -#elif defined(CONFIG_CMA120) - -# define COGENT_MOTHERBOARD "CMA120" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ - CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \ - CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \ - CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \ - CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS) -# define CMA_MB_NSLOTS 1 - -#elif defined(CONFIG_CMA150) - -# define COGENT_MOTHERBOARD "CMA150" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ - CMA_MB_CAP_KBM) -# define CMA_MB_NSLOTS 0 - -#else - -# error Cogent Motherboard either unsupported or undefined - -#endif - -/* - * check a flash i/o module has been selected if no flash on m/b - */ - -#if defined(CONFIG_CMA302) - -# define COGENT_FLASH_MODULE "CMA302" - -#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0 - -# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard - -#endif - -/* - * some further sanity checks - */ - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) -#error Cogent Sanity Check: Both Slot2 and PCI are defined -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI) -#error Extended PCI capability defined without PCI capability -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI) -#error Motherboard ethernet capability defined without PCI capability -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR) -#error 2nd dual serial capability defined without serial/parallel capability -#endif -#include "../board/cogent/mb.h" -#endif /* _CONFIG_COGENT_COMMON_H */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h deleted file mode 100644 index 4a8e5830e1..0000000000 --- a/include/configs/cogent_mpc8260.h +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for Cogent platform using an MPC8xx CPU module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_MISC_INIT_R /* Use misc_init_r() */ - -/* Cogent Modular Architecture options */ -#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */ -#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#define CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_KGDB - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ - -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ -#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ -# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */ -# else -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -# endif -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Low Level Cogent settings - * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not. - * also, make sure CONFIG_CONS_INDEX is still defined - the index will be - * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B - * (second 2 for CMA120 only) - */ -#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */ - -#include - -#ifdef CONFIG_CONS_NONE -#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ -#endif -#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ -#define CONFIG_SHOW_ACTIVITY - -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -/* - * flash exists on the motherboard - * set these four according to TOP dipsw: - * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) - * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) - */ -#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE -#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE -#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE -#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE -#endif -#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE -#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\ - HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101) -/* no slaves so just duplicate the master hrcw */ -#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE -#ifdef CONFIG_CMA302 -#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ -#else -#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */ -#ifdef CONFIG_CMA302 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ -#else -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR BCR_EBM - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -#if defined(CONFIG_CMA282) - -/* - * Init Memory Controller: - * - * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM - * and CS2 for (optional) local bus RAM on the CPU module. - * - * Note the motherboard address space (256 Mbyte in size) is connected - * to the 60x Bus and is located starting at address 0. The Hard Reset - * Configuration Word should put the 60x Bus into External Bus Mode, since - * we dont set up any memory controller maps for it (see BCR[EBM], 4-26). - * - * (the *_SIZE vars must be a power of 2) - */ - -#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */ -#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20) -#if 0 -#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */ -#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20) -#endif - -/* - * CS0 maps the EPROM on the cpu module - * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M - * - * Note: We must have already transferred control to the final location - * of the EPROM before these are used, because when BR0/OR0 are set, the - * mirror of the eprom at any other addresses will disappear. - */ - -/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V) -/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */ -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\ - ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) - -/* - * CS2 enables the Local Bus SDRAM on the CPU Module - * - * Will leave this unset for the moment, because a) my CPU module has no - * SDRAM installed (it is optional); and b) it will require programming - * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right - * if you can't test it. - */ - -#if 0 -/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V) -/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */ -#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/) -#endif - -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h deleted file mode 100644 index c57d70279f..0000000000 --- a/include/configs/cogent_mpc8xx.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Murray Jensen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for Cogent platform using an MPC8xx CPU module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is an MPC860 CPU */ -#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_MISC_INIT_R /* Use misc_init_r() */ - -/* Cogent Modular Architecture options */ -#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */ -#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */ -#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */ - -/* serial console configuration */ -#undef CONFIG_8xx_CONS_SMC1 -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */ - -#if defined(CONFIG_CMA286_60_OLD) -#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */ -#endif - -#define CONFIG_BAUDRATE 230400 - -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ - -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#define CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_ALLOC_DPRAM - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Low Level Cogent settings - * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not. - * also, make sure CONFIG_CONS_INDEX is still defined - the index will be - * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B - * (second 2 for CMA120 only) - */ -#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */ - -#include - -#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ -#define CONFIG_SHOW_ACTIVITY -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -/* - * flash exists on the motherboard - * set these four according to TOP dipsw: - * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) - * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) - */ -#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE -#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE -#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE -#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE -#endif -#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE -#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE -#ifdef CONFIG_CMA302 -#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ -#else -#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */ -#ifdef CONFIG_CMA302 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ -#else -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -#if defined(CONFIG_CMA286_60_OLD) - -/* - * Init Memory Controller: - * - * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings, - * they are actually the final settings for this cpu/board, because the - * flash and RAM are on the motherboard, accessed via the CMAbus, and the - * mappings are pretty much fixed. - * - * (the *_SIZE vars must be a power of 2) - */ - -#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */ -#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20) -#define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */ -#define CONFIG_SYS_CMA_CS1_SIZE (64 << 20) -#define CONFIG_SYS_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */ -#define CONFIG_SYS_CMA_CS2_SIZE (64 << 20) -#define CONFIG_SYS_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */ -#define CONFIG_SYS_CMA_CS3_SIZE (32 << 20) - -/* - * CS0 maps the EPROM on the cpu module - * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M - * - * Note: We must have already transferred control to the final location - * of the EPROM before these are used, because when BR0/OR0 are set, the - * mirror of the eprom at any other addresses will disappear. - */ - -/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V) -/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK) - -/* - * CS1 maps motherboard DRAM and motherboard I/O slot 1 - * (each 32Mbyte in size) - */ - -/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V) -/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */ -#define CONFIG_SYS_OR1_PRELIM ((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA) - -/* - * CS2 maps motherboard I/O slots 2 and 3 - * (each 32Mbyte in size) - */ - -/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V) -/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */ -#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA) - -/* - * CS3 maps motherboard I/O - * (32Mbyte in size) - */ - -/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */ -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V) -/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */ -#define CONFIG_SYS_OR3_PRELIM ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA) - -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 290a08d044..08bd276b44 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -3,7 +3,7 @@ * * Copyright (C) 2010 Marek Vasut * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -86,7 +86,6 @@ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " #endif #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE \ @@ -101,7 +100,6 @@ /* * Clock Configuration */ -#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ /* diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20_iris.h index 6f9e08cac0..2b876fede1 100644 --- a/include/configs/colibri_t20_iris.h +++ b/include/configs/colibri_t20_iris.h @@ -9,11 +9,6 @@ #include "tegra20-common.h" -/* Enable FDT support */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-colibri_t20_iris -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (Colibri) # " #define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris" diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h new file mode 100644 index 0000000000..ce6f23b8c4 --- /dev/null +++ b/include/configs/colibri_t30.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2013-2014 Stefan Agner + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra30-common.h" + +#define V_PROMPT "Colibri T30 # " +#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30" + +/* Board-specific config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30 + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index c6aad01dba..bfcfa0c8c9 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -41,11 +41,12 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ #define CONFIG_P1022 #define CONFIG_CONTROLCENTERD #define CONFIG_MP /* support multiple processors */ +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_NO_FLASH #define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_FSL_LAW /* Use common FSL init code */ @@ -138,7 +139,7 @@ #define CONFIG_SYS_SDRAM_SIZE 1024 #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) @@ -200,9 +201,10 @@ #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -/* Probing DP501 I2C-Bridge will hang */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \ - {0, 0x3b}, {0, 0x50} } + +#ifndef CONFIG_TRAILBLAZER +#define CONFIG_CMD_I2C +#endif #define CONFIG_PCA9698 /* NXP PCA9698 */ @@ -383,7 +385,6 @@ #endif /* CONFIG_TRAILBLAZER */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -433,14 +434,12 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_LAST_STAGE_INIT -#undef CONFIG_CMD_BOOTM #endif /* CONFIG_TRAILBLAZER */ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_HW_WATCHDOG #define CONFIG_LOADS_ECHO #define CONFIG_SYS_LOADS_BAUD_CHANGE diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h deleted file mode 100644 index c2dcef89c6..0000000000 --- a/include/configs/coreboot.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SYS_COREBOOT -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_LAST_STAGE_INIT -#define CONFIG_SYS_VSNPRINTF -#define CONFIG_ZBOOT_32 -#define CONFIG_PHYSMEM -#define CONFIG_SYS_EARLY_PCI_INIT - -#define CONFIG_LMB -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE -#define CONFIG_DEFAULT_DEVICE_TREE link - -#define CONFIG_BOOTSTAGE -#define CONFIG_BOOTSTAGE_REPORT -#define CONFIG_BOOTSTAGE_FDT -#define CONFIG_CMD_BOOTSTAGE -/* Place to stash bootstage data from first-stage U-Boot */ -#define CONFIG_BOOTSTAGE_STASH 0x0110f000 -#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc -#define CONFIG_BOOTSTAGE_USER_COUNT 60 - -#define CONFIG_LZO -#undef CONFIG_ZLIB -#undef CONFIG_GZIP - -/*----------------------------------------------------------------------- - * Watchdog Configuration - */ -#undef CONFIG_WATCHDOG -#undef CONFIG_HW_WATCHDOG - -/* SATA AHCI storage */ - -#define CONFIG_SCSI_AHCI - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_SATA_INTEL 1 -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#endif - -/* Generic TPM interfaced through LPC bus */ -#define CONFIG_TPM -#define CONFIG_TPM_TIS_LPC -#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 - -/*----------------------------------------------------------------------- - * Real Time Clock Configuration - */ -#define CONFIG_RTC_MC146818 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS - -/*----------------------------------------------------------------------- - * Serial Configuration - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 1843200 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ - 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_PORT_MAPPED - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,eserial0\0" \ - "stdout=vga,eserial0,cbmem\0" \ - "stderr=vga,eserial0,cbmem\0" - -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_STDIO_DEREGISTER -#define CONFIG_CBMEM_CONSOLE - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTOCOMPLETE - -#define CONFIG_SUPPORT_VFAT -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_EFI_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - -#define CONFIG_CMD_PART -#define CONFIG_CMD_CBFS -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_PARTITION_UUIDS - -/*----------------------------------------------------------------------- - * Video Configuration - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_COREBOOT -#define CONFIG_VIDEO_SW_CURSOR -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_I8042_KBD -#define CONFIG_CFB_CONSOLE -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* x86 GPIOs are accessed through a PCI device */ -#define CONFIG_INTEL_ICH6_GPIO - -/*----------------------------------------------------------------------- - * Command line configuration. - */ -#include - -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x01400000 - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO -#undef CONFIG_CMD_FLASH -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#define CONFIG_CMD_IO -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_GETTIME -#define CONFIG_CMD_XIMG -#define CONFIG_CMD_SCSI - -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -#define CONFIG_CMD_ZBOOT - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS \ - "root=/dev/sdb3 init=/sbin/init rootwait ro" -#define CONFIG_BOOTCOMMAND \ - "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" - - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 -#define CONFIG_KGDB_SER_INDEX 2 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "boot > " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + \ - 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * SDRAM Configuration - */ -#define CONFIG_NR_DRAM_BANKS 4 - -/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ -#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY -#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T - -/*----------------------------------------------------------------------- - * CPU Features - */ - -#define CONFIG_SYS_X86_TSC_TIMER -#define CONFIG_SYS_PCAT_INTERRUPTS -#define CONFIG_SYS_PCAT_TIMER -#define CONFIG_SYS_NUM_IRQS 16 - -/*----------------------------------------------------------------------- - * Memory organization: - * 32kB Stack - * 16kB Cache-As-RAM @ 0x19200000 - * 256kB Monitor - * (128kB + Environment Sector Size) malloc pool - */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) -#define CONFIG_SYS_CAR_ADDR 0x19200000 -#define CONFIG_SYS_CAR_SIZE (16 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024) - - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * FLASH configuration - */ -#define CONFIG_ICH_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_CMD_SF -#define CONFIG_CMD_SF_TEST -#define CONFIG_CMD_SPI -#define CONFIG_SPI - -/*----------------------------------------------------------------------- - * Environment configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x01000 - -/*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI - -/*----------------------------------------------------------------------- - * USB configuration - */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_PCI -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_USB_STORAGE -#define CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL - -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_SMSC95XX - -#define CONFIG_CMD_USB - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_STD_DEVICES_SETTINGS - -#endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c0591c5277..225ffdd0a5 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -10,20 +10,23 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg #if defined(CONFIG_P3041DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg #elif defined(CONFIG_P4080DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg #elif defined(CONFIG_P5020DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg #elif defined(CONFIG_P5040DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif @@ -41,12 +44,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -56,6 +57,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ @@ -92,12 +94,12 @@ #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1097) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -174,7 +176,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 @@ -312,7 +314,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port - controlled on board with jumper J8 @@ -378,15 +380,15 @@ * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ @@ -493,6 +495,14 @@ #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 #ifdef CONFIG_PHYS_64BIT @@ -501,6 +511,14 @@ #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME @@ -511,18 +529,18 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -532,10 +550,10 @@ * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -647,6 +665,12 @@ #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -654,7 +678,6 @@ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -663,7 +686,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -675,7 +697,6 @@ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -701,8 +722,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "bank_intlv=cs0_cs1;" \ - "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ @@ -717,8 +738,7 @@ "ramdiskfile=p4080ds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ "fdtfile=p4080ds/p4080ds.dtb\0" \ - "bdev=sda3\0" \ - "c=ffe\0" + "bdev=sda3\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ @@ -746,8 +766,10 @@ #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h new file mode 100644 index 0000000000..ace511f765 --- /dev/null +++ b/include/configs/corvus.h @@ -0,0 +1,209 @@ +/* + * Common board functions for siemens AT91SAM9G45 based boards + * (C) Copyright 2013 Siemens AG + * + * Based on: + * U-Boot file: include/configs/at91sam9m10g45ek.h + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define MACH_TYPE_CORVUS 2066 + +#define CONFIG_MACH_TYPE MACH_TYPE_CORVUS +#define CONFIG_SYS_GENERIC_BOARD +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ + +#define CONFIG_SYS_TEXT_BASE 0x72000000 + +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* LED */ +#define CONFIG_AT91_LED +#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ +#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#define CONFIG_DOS_PARTITION +#define CONFIG_USB_STORAGE + +#define CONFIG_SYS_LOAD_ADDR 0x72000000 /* load address */ + +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET_REDUND 0x180000 +#define CONFIG_ENV_SIZE 0x20000 + +#define CONFIG_BOOTCOMMAND \ + "nand read 0x70000000 0x200000 0x300000;" \ + "bootm 0x70000000" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256k(env),256k(env_redundant),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "root=/dev/mtdblock7 rw rootfstype=jffs2" + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ + 128*1024, 0x1000) +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE (12 * 1024) +#define CONFIG_SPL_STACK (16 * 1024) + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (2 * 1024) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0 + +#endif diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h deleted file mode 100644 index 05529c8fce..0000000000 --- a/include/configs/cpci5200.h +++ /dev/null @@ -1,394 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - - */ - -/************************************************************************* - * (c) 2005 esd gmbh Hannover - * - * - * from IceCube.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - *************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ -#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#if 1 -#define CONFIG_PCI 1 -#if 1 -#define CONFIG_PCI_PNP 1 -#endif -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_MII -#if 0 /* test-only !!! */ -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 0 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_DATE - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#endif -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to esd CPU CPCI/5200;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ - "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ - "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ - "loadaddr=01000000\0" \ - "serverip=192.168.2.99\0" \ - "gatewayip=10.0.0.79\0" \ - "user=mu\0" \ - "target=cpci5200.esd\0" \ - "script=cpci5200.bat\0" \ - "image=/tftpboot/vxWorks_cpci5200\0" \ - "ipaddr=10.0.13.196\0" \ - "netmask=255.255.0.0\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_vxworks0" - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000 -#define CONFIG_SYS_NVRAM_SIZE 32*1024 - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 -/* - * Flash configuration - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#if 1 /* test-only */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 -#else -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ - /* total size of a CAT24WC32 is 8192 bytes */ -#define CONFIG_ENV_OVERWRITE 1 -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_UDP_CHECKSUM 1 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00 - -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS1_START 0xfd000000 -#define CONFIG_SYS_CS1_SIZE 0x00010000 -#define CONFIG_SYS_CS1_CFG 0x10101410 - -#define CONFIG_SYS_CS3_START 0xfd010000 -#define CONFIG_SYS_CS3_SIZE 0x00010000 -#define CONFIG_SYS_CS3_CFG 0x10109410 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -/*----------------------------------------------------------------------- - * CPLD stuff - */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* CPLD program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ - -#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ -#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ - -#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00) -#define JTAG_GPIO_CFG_SET 0x00000000 -#define JTAG_GPIO_CFG_RESET 0x00F00000 - -#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04) -#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TMS_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C) -#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00) -#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TCK_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08) -#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00) -#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDI_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08) -#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ -#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04) -#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDO_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C) -#define JTAG_GPIO_TDO_DDR_SET 0x00000000 -#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 5b79ace5fa..1feaefd14e 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -20,7 +20,6 @@ #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #if defined(CONFIG_CPU9G20) @@ -33,7 +32,6 @@ #include -#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOARD_EARLY_INIT_F @@ -281,8 +279,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13 -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13) +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) @@ -311,6 +309,7 @@ #define CONFIG_RMII #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_MACB_SEARCH_PHY +#define CONFIG_AT91_WANTS_COMMON_PHY /* LEDS */ /* Status LED */ @@ -346,6 +345,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index c56fdd7517..8c7d97a18e 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -4,13 +4,13 @@ * * Configuration settings for the CPUAT91 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CONFIG_CPUAT91_H #define _CONFIG_CPUAT91_H -#include +#include #ifdef CONFIG_RAMBOOT #define CONFIG_SKIP_LOWLEVEL_INIT @@ -25,9 +25,7 @@ #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) -#define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM920T #define CONFIG_AT91RM9200 #define CONFIG_CPUAT91 #define USE_920T_MMU @@ -160,6 +158,7 @@ #if defined(CONFIG_CMD_USB) #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h new file mode 100644 index 0000000000..b927b1c9f5 --- /dev/null +++ b/include/configs/crownbay.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_X86_SERIAL +#define CONFIG_SMSC_LPC47M + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x80000000 + +#define CONFIG_PCI_PREF_BUS 0xc0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x20000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP +#define CONFIG_E1000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA} + +#define CONFIG_SPI_FLASH_SST + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + +/* Video is not supported */ +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE + +#endif /* __CONFIG_H */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 49a144fd33..a5c6f8474b 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -2,7 +2,7 @@ * (C) Copyright 2004 * Tolunay Orkun, Nextio Inc., torkun@nextio.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ #define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ @@ -99,7 +98,6 @@ */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -109,7 +107,6 @@ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -121,8 +118,6 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 7705a5dda8..6aa98efd4e 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -2,7 +2,7 @@ * (C) Copyright 2004 * Tolunay Orkun, Nextio Inc., torkun@nextio.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ #define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ @@ -98,7 +97,6 @@ */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -108,7 +106,6 @@ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -121,7 +118,6 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 9407eaf74b..a07ac38de7 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -21,14 +21,10 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_DA830_EVM -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA830 /* TI DA830 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 @@ -56,10 +52,10 @@ /* * I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* * I2C EEPROM definitions for catalyst 24W256 EEPROM chip @@ -74,7 +70,6 @@ */ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 3c0aacdd56..4b821f7031 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -25,15 +25,11 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_DA850_EVM -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_DA850_PLL_INIT #define CONFIG_SYS_DA850_DDR_INIT @@ -147,6 +143,7 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_CMD_SF #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) @@ -157,19 +154,17 @@ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #endif /* * I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 25000 -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 /* @@ -227,7 +222,6 @@ */ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME @@ -255,7 +249,7 @@ #undef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_OFFSET (256 << 10) +#define CONFIG_ENV_OFFSET (512 << 10) #define CONFIG_ENV_SECT_SIZE (64 << 10) #define CONFIG_SYS_NO_FLASH #endif @@ -263,6 +257,7 @@ /* * U-Boot general configuration */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOOTFILE "uImage" /* Boot file name */ @@ -279,6 +274,7 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC +#define CONFIG_OF_LIBFDT /* * Linux Information @@ -335,7 +331,6 @@ #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_FLASH #define CONFIG_CMD_SPI -#define CONFIG_CMD_SF #define CONFIG_CMD_SAVEENV #endif @@ -370,7 +365,6 @@ #ifndef CONFIG_DIRECT_NOR_BOOT /* defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ @@ -379,8 +373,6 @@ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0 #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT @@ -388,6 +380,7 @@ #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_TEXT_BASE 0x80000000 #define CONFIG_SPL_MAX_FOOTPRINT 32768 +#define CONFIG_SPL_PAD_TO 32768 #endif /* Load U-Boot Image From MMC */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 145e7ac926..0b04ee67b3 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -17,18 +17,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra114-common.h" -/* Must be off for Dalmore to boot !?!? FIXME */ -#define CONFIG_SYS_DCACHE_OFF - -/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra114 (Dalmore) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore" @@ -44,12 +36,7 @@ /* I2C */ #define CONFIG_SYS_I2C_TEGRA -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C /* SD/MMC */ #define CONFIG_MMC diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index 96d35c5718..6a2187266f 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2009 David Brownell * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -15,11 +15,8 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM355 /* Memory Info */ #define CONFIG_NR_DRAM_BANKS 1 @@ -42,10 +39,10 @@ #define DM9000_DATA (CONFIG_DM9000_BASE + 2) /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h index f7adbd86ce..52803ae909 100644 --- a/include/configs/davinci_dm355leopard.h +++ b/include/configs/davinci_dm355leopard.h @@ -14,11 +14,8 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM355 /* DM355 based board */ /* Memory Info */ #define CONFIG_NR_DRAM_BANKS 1 @@ -41,10 +38,10 @@ #define DM9000_DATA (CONFIG_DM9000_BASE + 16) /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x10 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* NAND */ #define CONFIG_NAND_DAVINCI diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index e3084d3754..d75b43df41 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2009 Texas Instruments Incorporated * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -15,11 +15,8 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM365 /* Memory Info */ #define CONFIG_NR_DRAM_BANKS 1 @@ -44,17 +41,16 @@ /* Network Configuration */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index 3c430ae0e0..a3fcd868d2 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -15,7 +15,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ /* Clock rates detection */ #ifndef __ASSEMBLY__ @@ -27,8 +26,6 @@ extern unsigned int davinci_arm_clk_get(void); /* Timer Input clock freq */ #define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2) #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM646X /* EEPROM definitions for EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 @@ -61,15 +58,14 @@ extern unsigned int davinci_arm_clk_get(void); #define CONFIG_BAUDRATE 115200 /* I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 10 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Network & Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME @@ -80,6 +76,8 @@ extern unsigned int davinci_arm_clk_get(void); #define CONFIG_SYS_NO_FLASH #ifdef CONFIG_SYS_USE_NAND #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_MASK_CLE 0x80000 +#define CONFIG_SYS_NAND_MASK_ALE 0x40000 #define CONFIG_SYS_NAND_CS 2 #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_IS_IN_NAND diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 6526478a96..e7710cb3f6 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2007 Sergey Kubushyn * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -41,11 +41,8 @@ /*===================*/ /* SoC Configuration */ /*===================*/ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM644X /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ @@ -78,16 +75,15 @@ /*===================*/ /* I2C Configuration */ /*===================*/ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /*==================================*/ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 29b10dd167..8776b4a206 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2007 Sergey Kubushyn * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -19,11 +19,8 @@ /*===================*/ /* SoC Configuration */ /*===================*/ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM644X /*=============*/ /* Memory Info */ /*=============*/ @@ -47,16 +44,15 @@ /*===================*/ /* I2C Configuration */ /*===================*/ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /*==================================*/ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 34a64b301a..dba7adeb73 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -16,11 +16,8 @@ #define CONFIG_SYS_USE_NAND #define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */ /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM644X /* EEPROM definitions for Atmel 24LC64 EEPROM chip */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 @@ -43,14 +40,13 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ /* I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* Network & Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index d35aea7ee5..fc20547162 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2007 Sergey Kubushyn * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -43,11 +43,8 @@ /*===================*/ /* SoC Configuration */ /*===================*/ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM644X /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ @@ -79,16 +76,15 @@ /*===================*/ /* I2C Configuration */ /*===================*/ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /*==================================*/ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h new file mode 100644 index 0000000000..cb03e33b6e --- /dev/null +++ b/include/configs/db-mv784mp-gp.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_DB_MV7846MP_GP_H +#define _CONFIG_DB_MV7846MP_GP_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TEXT_BASE 0x04000000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_STMICRO + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define CONFIG_PHY_BASE_ADDR 0x10 +#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ +#define CONFIG_RESET_PHY_R + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 07c60abec4..5bbd4431d1 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -12,23 +12,20 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_DBAU1X00 1 -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ -#define CONFIG_SOC_AU1000 1 #else #ifdef CONFIG_DBAU1100 -#define CONFIG_SOC_AU1100 1 #else #ifdef CONFIG_DBAU1500 -#define CONFIG_SOC_AU1500 1 #else #ifdef CONFIG_DBAU1550 /* Cabernet */ -#define CONFIG_SOC_AU1550 1 #else #error "No valid board set" #endif @@ -133,8 +130,6 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ diff --git a/include/configs/debris.h b/include/configs/debris.h deleted file mode 100644 index c9fb8d78cb..0000000000 --- a/include/configs/debris.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Sangmoon Kim, Etin Systems, dogoil@etinsys.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* Environments */ - -/* bootargs */ -#define CONFIG_BOOTARGS \ - "console=ttyS0,9600 init=/linuxrc " \ - "root=/dev/nfs rw nfsroot=192.168.0.1:" \ - "/tftpboot/target " \ - "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \ - "255.255.255.0:debris:eth0:none " \ - "mtdparts=phys:12m(root),-(kernel)" - -/* bootcmd */ -#define CONFIG_BOOTCOMMAND \ - "tftp 800000 pImage; " \ - "setenv bootargs console=ttyS0,9600 init=/linuxrc " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:eth0:none " \ - "mtdparts=phys:12m(root),-(kernel); " \ - "bootm 800000" - -/* bootdelay */ -#define CONFIG_BOOTDELAY 5 /* autoboot 5s */ - -/* baudrate */ -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ - -/* loads_echo */ -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ - -/* ethaddr */ -#undef CONFIG_ETHADDR - -/* eth2addr */ -#undef CONFIG_ETH2ADDR - -/* eth3addr */ -#undef CONFIG_ETH3ADDR - -/* ipaddr */ -#define CONFIG_IPADDR 192.168.0.2 - -/* serverip */ -#define CONFIG_SERVERIP 192.168.0.1 - -/* autoload */ -#undef CONFIG_SYS_AUTOLOAD - -/* rootpath */ -#define CONFIG_ROOTPATH "/tftpboot/target" - -/* gatewayip */ -#define CONFIG_GATEWAYIP 192.168.0.1 - -/* netmask */ -#define CONFIG_NETMASK 255.255.255.0 - -/* hostname */ -#define CONFIG_HOSTNAME debris - -/* bootfile */ -#define CONFIG_BOOTFILE "pImage" - -/* loadaddr */ -#define CONFIG_LOADADDR 800000 - -/* preboot */ -#undef CONFIG_PREBOOT - -/* clocks_in_mhz */ -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_DEBRIS 1 - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CONFIG_SYS_MONITOR_LEN 0x00040000 -#define CONFIG_SYS_MONITOR_BASE 0x00090000 -#define CONFIG_SYS_RAMBOOT 1 -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00040000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#endif - -#define CONFIG_SYS_FLASH_BASE 0x7C000000 -#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=debris-0" -#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)" -*/ - -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1 -#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */ -#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000 - -/* - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS = - * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET - */ -#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#ifdef CONFIG_SYS_I2C_SOFT -#error "Soft I2C is not configured properly. Please review!" -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 7372800 - -#define CONFIG_SYS_NS16550_COM1 0xFF080000 -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 - -#define CONFIG_SYS_DLL_EXTEND 0x00 -#define CONFIG_SYS_PCI_HOLD_DEL 0x20 - -#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */ - -#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */ - -#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ - -/* the following are for SDRAM only*/ -#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#if 0 -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ -#endif - -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (0x4000000 - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x04000000 -#define CONFIG_SYS_BANK1_END (0x8000000 - 1) -#define CONFIG_SYS_BANK1_ENABLE 1 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index ed8ba1abc4..bd96a7d3f4 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -10,7 +10,7 @@ #define __CONFIG_DEVKIT3250_H__ /* SoC and board defines */ -#include +#include #include /* @@ -29,7 +29,6 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MALLOC_LEN SZ_1M -#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M #define CONFIG_SYS_TEXT_BASE 0x83FA0000 @@ -61,7 +60,6 @@ * U-Boot General Configurations */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 513121ae64..1c69551d16 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -9,18 +9,15 @@ * * Configuration settings for the DevKit8000 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 -#define CONFIG_OMAP_GPIO /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM @@ -30,31 +27,31 @@ */ #define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ + +#define CONFIG_NAND + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#include /* get chip and board defs */ -#include +#include /* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT 1 - /* Size of malloc() pool */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ +#undef CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* Hardware drivers */ @@ -68,39 +65,18 @@ #define CONFIG_DM9000_NO_SROM 1 #undef CONFIG_DM9000_DEBUG -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -/* select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* MMC */ -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 +/* SPI */ +#undef CONFIG_SPI +#undef CONFIG_OMAP3_SPI /* I2C */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#undef CONFIG_SYS_I2C_OMAP24XX +#define CONFIG_SYS_I2C_OMAP34XX /* TWL4030 */ -#define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 /* Board NAND Info */ -#define CONFIG_SYS_NO_FLASH /* no NOR flash */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:" \ "512k(x-loader)," \ @@ -109,16 +85,8 @@ "4m(kernel)," \ "-(fs)" -#define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" @@ -128,20 +96,20 @@ /* partition */ /* commands to include */ -#include - #define CONFIG_CMD_DHCP /* DHCP support */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_GPIO +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_BOOTZ +#undef CONFIG_SUPPORT_RAW_INITRD +#undef CONFIG_FAT_WRITE +#undef CONFIG_CMD_EXT4 +#undef CONFIG_CMD_FS_GENERIC /* BOOTP/DHCP options */ #define CONFIG_BOOTP_SUBNETMASK @@ -158,10 +126,6 @@ #undef CONFIG_BOOTP_VENDOREX /* Environment information */ -#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ - -#define CONFIG_BOOTDELAY 3 - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ @@ -229,93 +193,31 @@ #define CONFIG_BOOTCOMMAND "run autoboot" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 128 /* max number of command args */ - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 0x01000000) /* 16MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - /* NAND and environment organization */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - /* SRAM config */ #define CONFIG_SYS_SRAM_START 0x40200000 #define CONFIG_SYS_SRAM_SIZE 0x10000 /* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NAND_SIMPLE - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#undef CONFIG_SPL_MTD_SUPPORT +#undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#undef CONFIG_SPL_STACK #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -327,31 +229,25 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - /* SPL OS boot options */ -#define CONFIG_SPL_OS_BOOT - -#define CONFIG_CMD_SPL #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 0x400000) #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" - +#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR +#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR +#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ +#undef CONFIG_SYS_SPL_ARGS_ADDR #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) #endif /* __CONFIG_H */ diff --git a/include/configs/dig297.h b/include/configs/dig297.h index bf91625079..c8739ed294 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -10,7 +10,7 @@ * * Configuration settings for the Comelit DIG297 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -28,8 +28,8 @@ * High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SYS_TEXT_BASE 0x80008000 @@ -122,10 +122,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 @@ -137,13 +137,12 @@ * Board NAND Info. */ #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ #if defined(CONFIG_CMD_NET) @@ -238,7 +237,6 @@ */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -252,10 +250,6 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index a5215db298..76ec168c20 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -20,9 +20,10 @@ * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD /* * Valid values for CONFIG_SYS_TEXT_BASE are: @@ -393,7 +394,6 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_AUTO_COMPLETE 1 #define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_HUSH_PARSER #define CONFIG_AUTOBOOT_KEYED @@ -416,8 +416,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00100000 -#define CONFIG_SYS_HZ 1000 - /* * Various low-level settings */ diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index a03c46295e..d9bd564880 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -2,14 +2,13 @@ * (C) Copyright 2010 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -18,13 +17,14 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME dlvsion-10g -#define CONFIG_IDENT_STRING " dlvision-10g 0.04" +#define CONFIG_IDENT_STRING " dlvision-10g 0.06" #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -41,6 +41,7 @@ /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ @@ -65,9 +66,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) @@ -98,9 +104,23 @@ /* * I2C stuff */ +#define CONFIG_SYS_I2C_PPC4XX +#define CONFIG_SYS_I2C_PPC4XX_CH0 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F + +#define CONFIG_SYS_I2C_IHS +#define CONFIG_SYS_I2C_IHS_CH0 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_CH1 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F + +#define CONFIG_SYS_SPD_BUS_NUM 2 /* Temp sensor/hwmon/dtt */ +#define CONFIG_SYS_DTT_BUS_NUM 2 #define CONFIG_DTT_LM63 1 /* National LM63 */ #define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */ #define CONFIG_DTT_PWM_LOOKUPTABLE \ @@ -108,6 +128,9 @@ { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } } #define CONFIG_DTT_TACH_LIMIT 0xa10 +#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1} +#define CONFIG_SYS_SIL1178_I2C {0, 1} + /* EBC peripherals */ #define CONFIG_SYS_FLASH_BASE 0xFC000000 @@ -131,7 +154,7 @@ #define CONFIG_SYS_LATCH0_RESET 0xffff #define CONFIG_SYS_LATCH0_BOOT 0xffff -#define CONFIG_SYS_LATCH1_RESET 0xffcf +#define CONFIG_SYS_LATCH1_RESET 0xffbf #define CONFIG_SYS_LATCH1_BOOT 0xffff #define CONFIG_SYS_FPGA_NO_RFL_HI @@ -218,9 +241,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* @@ -308,9 +330,7 @@ /* * OSD Setup */ -#define CONFIG_SYS_ICS8N3QV01 #define CONFIG_SYS_MPC92469AC -#define CONFIG_SYS_SIL1178 #define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT #endif /* __CONFIG_H */ diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index 2f8d6b4c90..a9cfc10d0c 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -2,14 +2,13 @@ * (C) Copyright 2009 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_DLVISION 1 /* on a Neo board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -23,6 +22,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ #define CONFIG_MISC_INIT_R /* call misc_init_r */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -35,6 +35,7 @@ /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ @@ -59,8 +60,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h index f2f41028eb..3f1f9f3846 100644 --- a/include/configs/dnp5370.h +++ b/include/configs/dnp5370.h @@ -55,6 +55,8 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING + +#define CONFIG_LIB_RAND #endif /* @@ -85,8 +87,8 @@ #define ENV_IS_EMBEDDED #define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); @@ -103,6 +105,7 @@ #define CONFIG_DNP5370_EXT_WD_DISABLE 1 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BFIN_SERIAL #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTCOMMAND "bootm 0x20030000" #define CONFIG_BOOTARGS "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2" diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 0f0dd21c23..379e6c79b8 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2011 - * Stefan Herbrechtsmeier + * Stefan Herbrechtsmeier * * Based on Kirkwood support: * (C) Copyright 2009 @@ -24,9 +24,9 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_GENERIC_BOARD /* * Commands configuration @@ -52,7 +52,6 @@ /* Remove or override few declarations from mv-common.h */ #undef CONFIG_SYS_PROMPT -#define CONFIG_SYS_PROMPT "=> " /* * Ethernet Driver configuration diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index d66bd2ab34..ec7f721ff3 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -12,6 +12,8 @@ #ifndef _CONFIG_DOCKSTAR_H #define _CONFIG_DOCKSTAR_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -21,7 +23,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_DOCKSTAR /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 70b204f645..dee2b11056 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -4,28 +4,229 @@ * Lokesh Vutla * * Configuration settings for the TI DRA7XX board. - * See omap5_common.h for omap5 common settings. + * See ti_omap5_common.h for omap5 common settings. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H -/* High Level Configuration Options */ -#define CONFIG_DRA7XX /* in a TI DRA7XX core */ -#define CONFIG_ENV_IS_NOWHERE /* For now. */ +#define CONFIG_DRA7XX +#define CONFIG_BOARD_EARLY_INIT_F -#include +#ifndef CONFIG_QSPI_BOOT +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif +#define CONFIG_CMD_SAVEENV -#define CONFIG_SYS_PROMPT "DRA752 EVM # " - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 UART1_BASE +#if (CONFIG_CONS_INDEX == 1) +#define CONSOLEDEV "ttyO0" +#elif (CONFIG_CONS_INDEX == 3) +#define CONSOLEDEV "ttyO2" +#endif +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_OMAP_ABE_SYSCK -#define CONSOLEDEV "ttyO0" +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + +#include + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_HSMMC2_8BIT + +/* CPSW Ethernet */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB + +/* SPI */ +#undef CONFIG_OMAP3_SPI +#define CONFIG_TI_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_TI_SPI_MMAP +#define CONFIG_SF_DEFAULT_SPEED 48000000 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 + +/* + * Default to using SPI for environment, etc. + * 0x000000 - 0x010000 : QSPI.SPL (64KiB) + * 0x010000 - 0x020000 : QSPI.SPL.backup1 (64KiB) + * 0x020000 - 0x030000 : QSPI.SPL.backup2 (64KiB) + * 0x030000 - 0x040000 : QSPI.SPL.backup3 (64KiB) + * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) + * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) + * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) + * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) + * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) + * 0x9E0000 - 0x2000000 : USERLAND + */ +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#if defined(CONFIG_QSPI_BOOT) +/* In SPL, use the environment and discard MMC support for space. */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SPL_MMC_SUPPORT +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE (64 << 10) /* 64 KiB */ +#endif +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ +#define CONFIG_ENV_OFFSET 0x1C0000 +#define CONFIG_ENV_OFFSET_REDUND 0x1D0000 +#endif + +/* SPI SPL */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 + +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB2PHY2_HOST + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* NAND support */ +#ifdef CONFIG_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +/* NAND: driver related configs */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define MTDIDS_DEFAULT "nand0=nand.0" +#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ + "128k(NAND.SPL)," \ + "128k(NAND.SPL.backup1)," \ + "128k(NAND.SPL.backup2)," \ + "128k(NAND.SPL.backup3)," \ + "256k(NAND.u-boot-spl-os)," \ + "1m(NAND.u-boot)," \ + "128k(NAND.u-boot-env)," \ + "128k(NAND.u-boot-env.backup1)," \ + "8m(NAND.kernel)," \ + "-(NAND.rootfs)" +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +/* NAND: SPL related configs */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_AM33XX_BCH +#endif +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif +#endif /* !CONFIG_NAND */ + +/* Parallel NOR Support */ +#if defined(CONFIG_NOR) +/* NOR: device related configs */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ +/* #define CONFIG_INIT_IGNORE_ERROR */ +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +/* Reduce SPL size by removing unlikey targets */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ + "128k(NOR.SPL)," \ + "128k(NOR.SPL.backup1)," \ + "128k(NOR.SPL.backup2)," \ + "128k(NOR.SPL.backup3)," \ + "256k(NOR.u-boot-spl-os)," \ + "1m(NOR.u-boot)," \ + "128k(NOR.u-boot-env)," \ + "128k(NOR.u-boot-env.backup1)," \ + "8m(NOR.kernel)," \ + "-(NOR.rootfs)" +#define CONFIG_ENV_OFFSET 0x001c0000 +#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 +#endif +#endif /* NOR support */ #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/draco.h b/include/configs/draco.h new file mode 100644 index 0000000000..a2438d883e --- /dev/null +++ b/include/configs/draco.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_DRACO_H +#define __CONFIG_DRACO_H + +#define CONFIG_SIEMENS_DRACO +#define MACH_TYPE_DRACO 4314 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 275 +#define DDR_PLL_FREQ 303 +#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC + +#define BOARD_DFU_BUTTON_GPIO 27 +#define BOARD_DFU_BUTTON_LED 64 /* red LED */ +#define BOARD_STATUS_LED 103 /* green LED */ +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ + +#undef CONFIG_DOS_PARTITION +#undef CONFIG_CMD_FAT + + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#undef CONFIG_MII +#undef CONFIG_PHY_GIGE +#define CONFIG_PHY_SMSC + +#define CONFIG_FACTORYSET + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nand_img_size=0x400000\0" \ + "optargs=\0" \ + CONFIG_COMMON_ENV_SETTINGS + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"run nand_boot;" \ +"reset;" + + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index b1ca859250..981233a070 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -34,7 +34,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/duovero.h b/include/configs/duovero.h new file mode 100644 index 0000000000..e68f415c20 --- /dev/null +++ b/include/configs/duovero.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright: 2013 + * Gumstix, Inc - http://www.gumstix.com + * Maintainer: Ash Charles + * + * Configuration settings for the Gumstix DuoVero board. + * See omap4_common.h for OMAP4 common part + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_DUOVERO_H +#define __CONFIG_DUOVERO_H + +/* + * High Level Configuration Options + */ +#define CONFIG_DUOVERO +#define MACH_TYPE_OMAP4_DUOVERO 4097 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP4_DUOVERO + +#include + +#undef CONFIG_SPL_OS_BOOT + +#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "duovero # " + +/* USB UHH support options */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 + +#define CONFIG_SYS_ENABLE_PADS_ALL + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET + +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +/* GPIO */ +#define CONFIG_CMD_GPIO + +/* ENV related config options */ +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#endif /* __CONFIG_DUOVERO_H */ diff --git a/include/configs/dvlhost.h b/include/configs/dvlhost.h deleted file mode 100644 index 141879540f..0000000000 --- a/include/configs/dvlhost.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (C) Copyright 2009 - * Michael Schwingen, michael@schwingen.org - * - * Configuration settings for the - * dLAN200 AV Wireless G ("dvlhost") board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_DVLHOST 1 - -#define CONFIG_MACH_TYPE 1343 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/dvlhost/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -/* which serial port to use */ -# define CONFIG_KGDB_SER_INDEX 1 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x01D80000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 -#define CONFIG_SYS_HZ 1000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113442 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* 32MB SDRAM: 2* 8Mx16, CL3 */ -#define CONFIG_SYS_SDR_CONFIG 0x18 -#define PHYS_SDRAM_1_SIZE 0x02000000 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x800 -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE - -/* FLASH organization: one Spansion S29AL032D-04 Flash */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 -#define PHYS_FLASH_1 0x50000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 - -/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */ -#define CONFIG_PHY_ADDR 0x18 -/* NPE1 PHY: MII IP175 switch, port 5 is host port */ -#define CONFIG_PHY1_ADDR 0x05 -/* MII PHY management */ -#define CONFIG_MII 1 -/* fixed-speed powerline modem without standard PHY registers on MII */ -#define CONFIG_MII_NPE0_FIXEDLINK 1 -#define CONFIG_MII_NPE0_SPEED 100 -#define CONFIG_MII_NPE0_FULLDUPLEX 1 -/* fixed-speed switch without standard PHY registers on MII */ -#define CONFIG_MII_NPE1_FIXEDLINK 1 -#define CONFIG_MII_NPE1_SPEED 100 -#define CONFIG_MII_NPE1_FULLDUPLEX 1 - -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 -/* ethernet switch connected to MII port */ -#define CONFIG_MII_ETHSWITCH 1 -#define CONFIG_HAS_ETH1 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "ethprime=NPE1\0" \ - "ethrotate=no\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=dvlhost/uImage\0" \ - "rootfile=dvlhost/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} dvlhost/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h new file mode 100644 index 0000000000..76e6cac77c --- /dev/null +++ b/include/configs/dxr2.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_DXR2_H +#define __CONFIG_DXR2_H + +#define CONFIG_SIEMENS_DXR2 +#define MACH_TYPE_DXR2 4315 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DXR2 + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 275 +#define DDR_PLL_FREQ 303 +#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC + +#define BOARD_DFU_BUTTON_GPIO 27 +#define BOARD_DFU_BUTTON_LED 64 /* red LED */ +#define BOARD_STATUS_LED 103 /* green LED */ +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ + +#undef CONFIG_DOS_PARTITION +#undef CONFIG_CMD_FAT + + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#undef CONFIG_MII +#undef CONFIG_PHY_GIGE +#define CONFIG_PHY_SMSC + +#define CONFIG_FACTORYSET + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=dxr2\0" \ + "nand_img_size=0x400000\0" \ + "optargs=\0" \ + CONFIG_COMMON_ENV_SETTINGS + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"run nand_boot;" \ +"reset;" + + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_DXR2_H */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h deleted file mode 100644 index c2d04a21c7..0000000000 --- a/include/configs/eXalion.h +++ /dev/null @@ -1,436 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -/* #define CONFIG_MPC8240 1 */ -#define CONFIG_MPC8245 1 -#define CONFIG_EXALION 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#if defined (CONFIG_MPC8240) - /* #warning ---------- eXalion with MPC8240 --------------- */ -#elif defined (CONFIG_MPC8245) - /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */ -#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245) -#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245) -#else -#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -/* older kernels need clock in MHz newer in Hz */ - /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */ -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_BOOTDELAY 10 - - - /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_PCI - - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_MISC_INIT_R 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */ - /* return real value. */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_DATA_SIZE 128 - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - - -#if defined (CONFIG_MPC8240) -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 -#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */ -#elif defined (CONFIG_MPC8245) -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */ -#define CONFIG_ENV_ADDR 0xFFFC0000 -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -/* #define CONFIG_SYS_ISA_MEM 0xFD000000 */ -#define CONFIG_SYS_ISA_IO 0xFE000000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE -#define FLASH_BASE1_PRELIM 0 - - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI 1 /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_EEPRO100 1 - -#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */ -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */ -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */ -#define PCI_ENET2_IOADDR 0x82000000 -#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */ -#define PCI_ENET3_IOADDR 0x83000000 - -/*----------------------------------------------------------------------- - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_NS16550_SERIAL 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX == 1) -#define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */ -#else -#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); }) -#endif - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */ - - /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */ - -#if defined (CONFIG_MPC8245) -/* Bit-field values for PMCR2. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */ -#define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */ -#endif - -/* Bit-field values for MIOCR1. */ -#if !defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */ -#endif -/* Bit-field values for MIOCR2. */ -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */ - /* - note bottom 3 bits MUST be 0 */ -#endif - -/* Bit-field values for MCCR1. */ -#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ - -/* Bit-field values for MCCR2. */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */ -#else /* refresh cycles */ -#define CONFIG_SYS_REFINT 750 -#endif - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_BSTOPRE 1023 -#else -#define CONFIG_SYS_BSTOPRE 250 -#endif - -/* Bit-field values for MCCR3. */ -/* the following are for SDRAM only */ - -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */ -#else -#define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */ -#endif -#if defined (CONFIG_MPC8240) -#define CONFIG_SYS_RDLAT 2 /* data latency from read command */ -#endif - -/* Bit-field values for MCCR4. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 5 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#else -#if 0 -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ -#endif -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#endif -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CONFIG_SYS_REGDIMM 0 -#if defined (CONFIG_MPC8240) -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0 -#elif defined (CONFIG_MPC8245) -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 0 -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - - -/*----------------------------------------------------------------------- - memory bank settings - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 - -/*----------------------------------------------------------------------- - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#if defined (CONFIG_MPC8240) -#define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#elif defined (CONFIG_MPC8245) -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */ -#else -#define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */ -#endif -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/*----------------------------------------------------------------------- - * Block Address Translation (BAT) register settings. - */ -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#define CONFIG_ATAPI - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide supported... */ -#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ - -/*----------------------------------------------------------------------- - * DISK Partition support - */ -#define CONFIG_DOS_PARTITION - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 14a8db3bb8..1e616730eb 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -28,14 +28,10 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_DA850_EVM -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 #define CONFIG_DA8XX_GPIO @@ -79,9 +75,10 @@ /* * I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* * Network & Ethernet Configuration @@ -89,7 +86,6 @@ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_EMAC_MDIO_PHY_NUM 0 #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 08ba883f4c..bdca705874 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -98,7 +98,6 @@ /*----------------------------------------------------------------------* * Clock and PLL Configuration * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ @@ -153,7 +152,7 @@ #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index 247e37b6dd..f7e70aa573 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -36,13 +36,10 @@ #define CONFIG_SYS_TEXT_BASE 0x00000000 #else #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x21f00000 +#define CONFIG_SYS_TEXT_BASE 0x21800000 #endif #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 -#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ +#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000 #define CONFIG_BOOT_RETRY_TIME 30 #define CONFIG_CMDLINE_EDITING @@ -59,7 +56,6 @@ #define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */ #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ @@ -82,7 +78,7 @@ * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* * sdram @@ -123,45 +119,46 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_PING -#define CONFIG_I2C_CMD_NO_FLAT #define CONFIG_I2C_CMD_TREE #define CONFIG_CMD_USB #define CONFIG_CMD_FAT +#define CONFIG_CMD_UBI +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_UBIFS #define CONFIG_SYS_LONGHELP /* - * Filesystems + * MTD defines */ -#define CONFIG_JFFS2_NAND 1 +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO -#ifndef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_OFFSET 0 -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#else -#define MTDIDS_DEFAULT "nor0=0,nand0=1" +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" #define MTDPARTS_DEFAULT "mtdparts=" \ - "0:" \ - "384k(U-Boot)," \ - "128k(Env)," \ - "128k(Splash)," \ - "4M(Kernel)," \ - "-(FS)" \ + "physmap-flash.0:" \ + "512k(U-Boot)," \ + "128k(Env)," \ + "128k(Splash)," \ + "4M(Kernel)," \ + "384k(MiniFS)," \ + "-(FS)" \ ";" \ - "1:" \ - "-(jffs2)" -#endif /* CONFIG_JFFS2_CMDLINE */ - + "atmel_nand:" \ + "1M(emergency)," \ + "-(data)" /* * Hardware drivers */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_AT91C_PQFP_UHPBUG #define CONFIG_USB_STORAGE @@ -328,7 +325,7 @@ #define CONFIG_BOOTDELAY 5 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000) #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ #define CONFIG_BAUDRATE 115200 @@ -347,12 +344,14 @@ "displayheight=512\0" \ "displaybsteps=1023\0" \ "ubootaddr=10000000\0" \ - "splashimage=10080000\0" \ - "kerneladdr=100A0000\0" \ + "splashimage=100A0000\0" \ + "kerneladdr=100C0000\0" \ "kernelsize=00400000\0" \ - "rootfsaddr=104A0000\0" \ + "rootfsaddr=10520000\0" \ "copy_addr=21200000\0" \ - "rootfssize=00B60000\0" \ + "rootfssize=00AE0000\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ "bootargsdefaults=set bootargs " \ "console=ttyS0,115200 " \ "video=vcxk_fb:xres:${displaywidth}," \ @@ -373,15 +372,15 @@ "erase $(rootfsaddr) +$(rootfssize);" \ "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ "\0" \ - "update_uboot=protect off 10000000 1005FFFF;" \ + "update_uboot=protect off 10000000 1007FFFF;" \ "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \ - "erase 10000000 1005FFFF;" \ + "erase 10000000 1007FFFF;" \ "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ - "protect on 10000000 1005FFFF;reset\0" \ + "protect on 10000000 1007FFFF;reset\0" \ "update_splash=protect off $(splashimage) +20000;" \ "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \ "erase $(splashimage) +20000;" \ - "cp.b $(fileaddr) 10080000 $(filesize);" \ + "cp.b $(fileaddr) $(splashimage) $(filesize);" \ "protect on $(splashimage) +20000;reset\0" \ "emergency=run bootargsdefaults;" \ "set bootargs $(bootargs) root=initramfs boot=emergency " \ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 47014f9e30..3f0ad69738 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -17,7 +17,6 @@ #define CONFIG_EBONY 1 /* Board is ebony */ #define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 2c9594be03..e26591c14f 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -23,9 +23,6 @@ */ #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4 1 -#define CONFIG_SH4A 1 #define CONFIG_CPU_SH7724 1 #define CONFIG_BOARD_LATE_INIT 1 #define CONFIG_ECOVEC 1 @@ -58,18 +55,17 @@ /* I2C */ #define CONFIG_CMD_I2C -#define CONFIG_SH_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_SYS_MAX_I2C_BUS 2 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH #define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2 +#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000 +#define CONFIG_SYS_I2C_SH_SPEED0 100000 +#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000 +#define CONFIG_SYS_I2C_SH_SPEED1 100000 #define CONFIG_SH_I2C_DATA_HIGH 4 #define CONFIG_SH_I2C_DATA_LOW 5 #define CONFIG_SH_I2C_CLOCK 41666666 -#define CONFIG_SH_I2C_BASE0 0xA4470000 -#define CONFIG_SH_I2C_BASE1 0xA4750000 /* Ether */ #define CONFIG_SH_ETHER 1 @@ -92,7 +88,6 @@ /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " /* Buffer size for input from the Console */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for Console output */ @@ -163,8 +158,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ @@ -179,7 +172,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 41666666 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __ECOVEC_H */ diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h new file mode 100644 index 0000000000..a82e8bcadc --- /dev/null +++ b/include/configs/edb93xx.h @@ -0,0 +1,290 @@ +/* + * U-boot - Configuration file for Cirrus Logic EDB93xx boards + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_MK_edb9301 +#define CONFIG_EDB9301 +#elif defined(CONFIG_MK_edb9302) +#define CONFIG_EDB9302 +#elif defined(CONFIG_MK_edb9302a) +#define CONFIG_EDB9302A +#elif defined(CONFIG_MK_edb9307) +#define CONFIG_EDB9307 +#elif defined(CONFIG_MK_edb9307a) +#define CONFIG_EDB9307A +#elif defined(CONFIG_MK_edb9312) +#define CONFIG_EDB9312 +#elif defined(CONFIG_MK_edb9315) +#define CONFIG_EDB9315 +#elif defined(CONFIG_MK_edb9315a) +#define CONFIG_EDB9315A +#else +#error "no board defined" +#endif + +/* Initial environment and monitor configuration options. */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp" +#define CONFIG_BOOTFILE "edb93xx.img" + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + + +#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds" + + +#ifdef CONFIG_EDB9301 +#define CONFIG_EP9301 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 +#define CONFIG_SYS_PROMPT "EDB9301> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 +#define CONFIG_SYS_PROMPT "EDB9302> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302A) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A +#define CONFIG_SYS_PROMPT "EDB9302A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9307) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 +#define CONFIG_SYS_PROMPT "EDB9307> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9307A) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A +#define CONFIG_SYS_PROMPT "EDB9307A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9312) +#define CONFIG_EP9312 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 +#define CONFIG_SYS_PROMPT "EDB9312> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 +#define CONFIG_SYS_PROMPT "EDB9315> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315A) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A +#define CONFIG_SYS_PROMPT "EDB9315A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#else +#error "no board defined" +#endif + +/* High-level configuration options */ +#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */ + +#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ +#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ + +/* Monitor configuration */ +#include +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#undef CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 + +#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +/* Print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* Boot argument buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ + +/* Serial port hardware configuration */ +#define CONFIG_PL010_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \ + 115200, 230400} +#define CONFIG_SYS_SERIAL0 0x808C0000 +#define CONFIG_SYS_SERIAL1 0x808D0000 +/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} */ + +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_GREEN 0 +#define STATUS_LED_RED 1 +/* Green */ +#define STATUS_LED_BIT STATUS_LED_GREEN +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Red */ +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +/* Network hardware configuration */ +#define CONFIG_DRIVER_EP93XX_MAC +#define CONFIG_MII_SUPPRESS_PREAMBLE +#define CONFIG_MII +#define CONFIG_PHY_ADDR 1 +#define CONFIG_NET_MULTI +#undef CONFIG_NETCONSOLE + +/* SDRAM configuration */ +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ + defined(CONFIG_EDB9315) +/* + * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * + * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of + * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of + * 64 MB of SDRAM. + */ + +#define CONFIG_EDB93XX_SDCS3 + +#elif defined(CONFIG_EDB9302A) || \ + defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) +/* + * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * + * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung + * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. + */ +#define CONFIG_EDB93XX_SDCS0 + +#else +#error "no SDCS configuration for this board" +#endif + + +#if defined(CONFIG_EDB93XX_SDCS3) +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */ +#define PHYS_SDRAM_1 0x00000000 +#elif defined(CONFIG_EDB93XX_SDCS0) +#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */ +#define PHYS_SDRAM_1 0xc0000000 +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_NR_DRAM_BANKS 8 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE) + + +/* Must match kernel config */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) + +/* Run-time memory allocatons */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_STACKSIZE (128 * 1024) + +#if defined(CONFIG_USE_IRQ) +#define CONFIG_STACKSIZE_IRQ (4 * 1024) +#define CONFIG_STACKSIZE_FIQ (4 * 1024) +#endif + +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* ----------------------------------------------------------------------------- + * FLASH and environment organization + * + * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at + * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit + * data bus, for a total of 16 MB of CFI-compatible flash. + * + * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at + * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit + * data bus, for a total of 32 MB of CFI-compatible flash. + * + * + * EDB9301/02(a)7a/15a EDB9307/12/15 + * 0x60000000 - 0x0003FFFF u-boot u-boot + * 0x60040000 - 0x0005FFFF environment #1 environment #1 + * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) + * 0x60080000 - 0x0009FFFF unused environment #2 + * 0x600A0000 - 0x000BFFFF unused environment #2 (continued) + * 0x600C0000 - 0x00FFFFFF unused unused + * 0x61000000 - 0x01FFFFFF not present unused + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + + +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT (256+8) + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_ADDR 0x60040000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* Define to enable MMC on SPI support */ +/* #define CONFIG_EP93XX_SPI_MMC */ + +#ifdef CONFIG_EP93XX_SPI_MMC +#define CONFIG_EP93XX_SPI +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SPI_NPOWER_EGPIO 9 +#endif + +#define CONFIG_USB_STORAGE +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_OHCI_EP93XX +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci" +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000 + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_CMD_BOOTZ + +/* Define to disable flash configuration*/ +/* #define CONFIG_EP93XX_NO_FLASH_CFG */ + +/* Define this for indusrial rated chips */ +/* #define CONFIG_EDB93XX_INDUSTRIAL */ + +#endif /* !defined (__CONFIG_H) */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 9c701099ad..70a698ab32 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -23,9 +23,7 @@ */ #define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_FEROCEON 1 /* CPU Core subversion */ -#define CONFIG_ORION5X 1 /* SOC Family Name */ #define CONFIG_88F5182 1 /* SOC Name */ #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ @@ -34,8 +32,6 @@ * CLKs configurations */ -#define CONFIG_SYS_HZ 1000 - /* * Board-specific values for Orion5x MPP low level init: * - MPPs 12 to 15 are SATA LEDs (mode 5) @@ -189,7 +185,8 @@ * I2C related stuff */ #ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h new file mode 100644 index 0000000000..6bc1ac6f3a --- /dev/null +++ b/include/configs/embestmx6boards.h @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2014 Eukréa Electromatique + * Author: Eric Bénard + * + * Configuration settings for the Embest RIoTboard + * + * based on mx6*sabre*.h which are : + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RIOTBOARD_CONFIG_H +#define __RIOTBOARD_CONFIG_H + +#include +#include + +#include "mx6_common.h" +#include + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" +#define CONFIG_MMCROOT "/dev/mmcblk1p2" + +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 4 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include +#undef CONFIG_CMD_FPGA + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR +#undef CONFIG_CMD_IMLS + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#if defined(CONFIG_ENV_IS_IN_MMC) +/* RiOTboard */ +#define CONFIG_FDTFILE "imx6dl-riotboard.dtb" +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +/* MarSBoard */ +#define CONFIG_FDTFILE "imx6q-marsboard.dtb" +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#include + +/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, + * 1M script, 1M pxe and the ramdisk at the end */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x12000000\0" \ + "fdt_addr_r=0x13000000\0" \ + "scriptaddr=0x13100000\0" \ + "pxefile_addr_r=0x13200000\0" \ + "ramdisk_addr_r=0x13300000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" + +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + BOOTENV + +#endif /* __RIOTBOARD_CONFIG_H */ diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index 43cf6bc441..3e62259062 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -25,15 +25,11 @@ /* * SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_HZ 1000 #define CONFIG_DA850_LOWLEVEL #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_DA850_PLL_INIT @@ -74,10 +70,10 @@ /* * I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 #define CONFIG_CMD_I2C @@ -135,7 +131,6 @@ */ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME @@ -229,7 +224,6 @@ * U-Boot general configuration */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h deleted file mode 100644 index 32d5cd65b9..0000000000 --- a/include/configs/ep8248.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * U-Boot configuration for Embedded Planet EP8248 boards. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8248 -#define CPU_ID_STR "MPC8248" - -#define CONFIG_EP8248 /* Embedded Planet EP8248 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -#define CONFIG_SYS_BCSR 0xFA000000 - -/* Pass open firmware flat device tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc/cpm/serial 11a80" - -/* Select ethernet configuration */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#define CONFIG_HAS_ETH0 -#define CONFIG_ETHER_ON_FCC1 1 -/* - Rx clock is CLK10 - * - Tx clock is CLK11 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) - -#define CONFIG_HAS_ETH1 -#define CONFIG_ETHER_ON_FCC2 1 -/* - Rx clock is CLK13 - * - Tx clock is CLK14 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 0 /* Not used - implemented in BCSR */ - -#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB) -#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04) -#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1) - -#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \ - else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE - -#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \ - else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD - -#define MIIDELAY udelay(1) - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro" - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#if defined(CONFIG_CMD_JFFS2) -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 -#define CONFIG_SYS_JFFS2_LAST_SECTOR 62 -#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS -#define CONFIG_SYS_JFFS_CUSTOM_PART -#endif - -#if defined(CONFIG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */ -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x01240200 -#define CONFIG_SYS_SYPCR 0xFFFF0683 -#define CONFIG_SYS_BCR 0x00000000 -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -#define CONFIG_SYS_RMR RMR_CSRE -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CONFIG_SYS_RCCR 0 - -#define CONFIG_SYS_MPTPR 0x1300 -#define CONFIG_SYS_PSDMR 0x82672522 -#define CONFIG_SYS_PSRT 0x4B - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841) -#define CONFIG_SYS_SDRAM_OR 0xFF0030C0 - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801) -#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2 -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801) -#define CONFIG_SYS_OR2_PRELIM 0xFFF00864 - -#define CONFIG_SYS_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h deleted file mode 100644 index aba3392234..0000000000 --- a/include/configs/ep8260.h +++ /dev/null @@ -1,748 +0,0 @@ -/* - * (C) Copyright 2002 - * Frank Panno , Delphin Technology AG - * - * This file is based on similar values for other boards found in other - * U-Boot config files, and some that I found in the EP8260 manual. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - * - * "EP8260 H, V.1.1" - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 16M Flash (4 x AM29DL323DB90WDI) - * - 128k NVRAM with RTC - * - * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2) - * - 300MHz/133MHz/66MHz - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 32M Flash - * - 128k NVRAM with RTC - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Define this to enable support the EP8260 H2 version */ -#define CONFIG_SYS_EP8260_H2 1 -/* #undef CONFIG_SYS_EP8260_H2 */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core - * ------- ---------- --- --- ---- - * 0x2 0x2 33 133 133 - * 0x2 0x3 33 133 166 - * 0x2 0x4 33 133 200 - * 0x2 0x5 33 133 233 - * 0x2 0x6 33 133 266 - * - * 0x5 0x5 66 133 133 - * 0x5 0x6 66 133 166 - * 0x5 0x7 66 133 200 * - * 0x6 0x0 66 133 233 - * 0x6 0x1 66 133 266 - * 0x6 0x2 66 133 300 - */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) -#else -#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) -#endif - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */ -/* #undef CONFIG_SYS_SBC_BOOT_LOW */ - -/* The reset command will not work as expected if the reset address does - * not point to the correct address. - */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_FLASH0_BASE 0xFE000000 -#define CONFIG_SYS_FLASH0_SIZE 32 -#else -#define CONFIG_SYS_FLASH0_BASE 0xFF000000 -#define CONFIG_SYS_FLASH0_SIZE 16 -#endif - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. U-Boot expects this to be the on board FLASH. If you don't - * want it enabled, don't define these constants. - */ -#define CONFIG_SYS_FLASH1_BASE 0 -#define CONFIG_SYS_FLASH1_SIZE 0 -#undef CONFIG_SYS_FLASH1_BASE -#undef CONFIG_SYS_FLASH1_SIZE - -/* What should be the base address of SDRAM DIMM (60x bus) and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the - * local bus (8260 local bus is NOT cacheable!) -*/ -/* #define CONFIG_SYS_LSDRAM */ -#undef CONFIG_SYS_LSDRAM - -#ifdef CONFIG_SYS_LSDRAM -/* What should be the base address of SDRAM DIMM (local bus) and how big is - * it (in Mbytes)? -*/ - #define CONFIG_SYS_SDRAM1_BASE 0x04000000 - #define CONFIG_SYS_SDRAM1_SIZE 32 -#else - #define CONFIG_SYS_SDRAM1_BASE 0 - #define CONFIG_SYS_SDRAM1_SIZE 0 - #undef CONFIG_SYS_SDRAM1_BASE - #undef CONFIG_SYS_SDRAM1_SIZE -#endif /* CONFIG_SYS_LSDRAM */ - -/* What should be the base address of NVRAM and how big is - * it (in Bytes) - */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000 -#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16 - -/* The RTC is a Dallas DS1556 - */ -#define CONFIG_RTC_DS1556 - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CONFIG_SYS_LED_BASE 0x00000000 -#undef CONFIG_SYS_LED_BASE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ - -#if ( CONFIG_ETHER_INDEX == 3 ) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the local Bus (see 28-13) - * - Enable Half Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) - -/* - * - RAM for BD/Buffers is on the local Bus (see 28-13) - */ -#ifdef CONFIG_SYS_LSDRAM - #define CONFIG_SYS_CPMFCR_RAMTYPE 3 -#else /* CONFIG_SYS_LSDRAM */ - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#endif /* CONFIG_SYS_LSDRAM */ - -/* - Enable Half Duplex in FSMR */ -/* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ -# define CONFIG_SYS_FCC_PSMR 0 - -#else /* CONFIG_ETHER_INDEX */ -# error "on EP8260 ethernet must be FCC3" -#endif /* CONFIG_ETHER_INDEX */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* This is for HARD, must go */ - -/* - * Software (bit-bang) I2C driver configuration - */ -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -/* #define CONFIG_RTC_DS174x */ - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_BAUDRATE 9600 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 00:10:EC:00:30:8C - -#define CONFIG_IPADDR 192.168.254.130 -#define CONFIG_SERVERIP 192.168.254.49 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY -1 - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " - -/* Define this variable to enable the "hush" shell (from - Busybox) as command line interpreter, thus enabling - powerful command line syntax like - if...then...else...fi conditionals or `&&' and '||' - constructs ("shell scripts"). - If undefined, you get the old, much simpler behaviour - with a somewhat smapper memory footprint. -*/ -#define CONFIG_SYS_HUSH_PARSER - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_XIMG - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 - -/* Where do the on board registers (CS4) live? */ -#define CONFIG_SYS_REGS_BASE 0xFA000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#ifdef CONFIG_SYS_LSDRAM - #define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */ - #define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ -#else - #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ - #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */ -#endif /* CONFIG_SYS_LSDRAM */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ - -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -#ifdef CONFIG_SYS_EP8260_H2 -/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\ - ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\ - ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\ - HRCW_L2CPC01 |\ - CONFIG_SYS_SBC_HRCW_IMMR |\ - HRCW_APPC10 |\ - HRCW_CS10PC01 |\ - CONFIG_SYS_SBC_MODCK_H |\ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS) -#else -#define CONFIG_SYS_HRCW_MASTER 0x10400245 -#endif - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#else -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#endif - -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#else -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ -#endif - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 - -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) -#ifdef CONFIG_SYS_LSDRAM -/* 8260 local bus is NOT cacheable */ -#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#else /* !CONFIG_SYS_LSDRAM */ -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#endif /* CONFIG_SYS_LSDRAM */ - -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_EBM |\ - BCR_PLDP |\ - BCR_EAV |\ - BCR_NPQM0) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#ifdef CONFIG_SYS_EP8260_H2 -/* TBD: Find out why setting the BMT to 0xff causes the FCC to - * generate TX buffer underrun errors for large packets under - * Linux - */ -#define CONFIG_SYS_SYPCR_BMT 0x00000600 -#else -#define CONFIG_SYS_SYPCR_BMT SYPCR_BMT -#endif - -#ifdef CONFIG_SYS_LSDRAM -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - CONFIG_SYS_SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - CONFIG_SYS_SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) -#else -#define CONFIG_SYS_PISCR 0 -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_SCCR (SCCR_DFBRG00) -#else -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) -#endif - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescale Register 10-32 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI) - * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG) - * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG) - * 3 unused - * 4 60x GPCM 8 bit Board Regs, NVRTC - * 5 unused - * 6 unused - * 7 unused - * 8 PCMCIA - * 9 unused - * 10 unused - * 11 unused -*/ - -/*----------------------------------------------------------------------- - * BRx - Base Register - * Ref: Section 10.3.1 on page 10-14 - * ORx - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0 - FLASH - * - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_8_CLK |\ - ORxG_EHTR) - -/* Bank 1 - SDRAM - * PSDRAM - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_12) - -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_PSDMR 0xC34E246E -#else -#define CONFIG_SYS_PSDMR 0xC34E2462 -#endif - -#define CONFIG_SYS_PSRT 0x64 - -#ifdef CONFIG_SYS_LSDRAM -/* Bank 2 - SDRAM - * LSDRAM - */ - - #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - - #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - - #define CONFIG_SYS_LSDMR 0x416A2562 - #define CONFIG_SYS_LSRT 0x64 -#else - #define CONFIG_SYS_LSRT 0x0 -#endif /* CONFIG_SYS_LSDRAM */ - -/* Bank 4 - On board registers - * NVRTC and BCSR - */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) -/* -#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_10_CLK |\ - ORxG_TRLX) -*/ -#define CONFIG_SYS_OR4_PRELIM 0xfff00854 - -#ifdef _NOT_USED_SINCE_NOT_WORKING_ -/* Bank 8 - On board registers - * PCMCIA (currently not working!) - */ -#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SETA |\ - ORxG_SCY_10_CLK) -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h deleted file mode 100644 index bcf01b6169..0000000000 --- a/include/configs/ep82xxm.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (C) 2006 Embedded Planet, LLC. - * - * U-Boot configuration for Embedded Planet EP82xxM boards. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8260 -#define CPU_ID_STR "MPC8270" - -#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ - /* 256MB SDRAM / 64MB FLASH */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -#define CONFIG_SYS_BCSR 0xFA000000 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - - -#define CONFIG_ETHER_ON_FCC2 -#define CONFIG_ETHER_ON_FCC3 - -#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) -#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 0 /* Not used - implemented in BCSR */ - -#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB) -#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04) -#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1) - -#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \ - else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE - -#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \ - else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD - -#define MIIDELAY udelay(1) - - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_DIAG - - -#define CONFIG_ETHADDR 00:10:EC:00:88:65 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:10:EC:80:88:65 -#define CONFIG_IPADDR 10.0.0.245 -#define CONFIG_HOSTNAME EP82xxM -#define CONFIG_SERVERIP 10.0.0.26 -#define CONFIG_GATEWAYIP 10.0.0.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_ENV_IN_OWN_SECT 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3" - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#if 1 -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#endif - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0xFC000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -/* EEPROM Configuration */ -#define CONFIG_SYS_EEPROM_SIZE 0x1000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CONFIG_ENV_OFFSET 0x0 -#endif /* CONFIG_ENV_IS_IN_EEPROM */ - -/* RTC Configuration */ -#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_M41T11_BASE_YEAR 1900 - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 -#define CONFIG_DTT_SENSORS {0} -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -/*----------------------------------------------------------------------- - * NVRAM Configuration - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000 -#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16 - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_PCI_BOOTDELAY 0 - -/* PCI Memory map (if different from default map */ -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ -#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ -#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) - - -/* PCIBR0 - for PCI IO*/ -#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */ -#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ -/* PCIBR1 - prefetch and non-prefetch regions joined together */ -#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL -#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U) - - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#if defined(CONFIG_CMD_JFFS2) -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 -#define CONFIG_SYS_JFFS2_LAST_SECTOR 62 -#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS -#define CONFIG_SYS_JFFS_CUSTOM_PART -#endif - -#if defined(CONFIG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */ - -#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x02610000 -#define CONFIG_SYS_SYPCR 0xFFFF0689 -#define CONFIG_SYS_BCR 0x8080E000 -#define CONFIG_SYS_SCCR 0x00000001 - -#define CONFIG_SYS_RMR 0 -#define CONFIG_SYS_TMCNTSC 0x000000C3 -#define CONFIG_SYS_PISCR 0x00000083 -#define CONFIG_SYS_RCCR 0 - -#define CONFIG_SYS_MPTPR 0x0A00 -#define CONFIG_SYS_PSDMR 0xC432246E -#define CONFIG_SYS_PSRT 0x32 - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041) -#define CONFIG_SYS_SDRAM_OR 0xF0002900 - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801) -#define CONFIG_SYS_OR0_PRELIM 0xFC000882 -#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_BCSR | 0x00001001) -#define CONFIG_SYS_OR4_PRELIM 0xFFF00050 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#endif /* __CONFIG_H */ diff --git a/include/configs/espt.h b/include/configs/espt.h index e906efbdba..de16be70b2 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -10,8 +10,6 @@ #ifndef __ESPT_H #define __ESPT_H -#define CONFIG_SH 1 -#define CONFIG_SH4 1 #define CONFIG_CPU_SH7763 1 #define CONFIG_ESPT 1 #define __LITTLE_ENDIAN 1 @@ -43,7 +41,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -98,8 +95,9 @@ /* Clock */ #define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 /* Ether */ #define CONFIG_SH_ETHER 1 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index adf14be365..ce61a1621c 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -12,6 +12,8 @@ #include +#define CONFIG_SYS_GENERIC_BOARD + /* The first stage boot loader expects u-boot running at this address. */ #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ @@ -23,15 +25,12 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 /* CPU information */ -#define CONFIG_ARM926EJS -#define CONFIG_AT91FAMILY #define CONFIG_DISPLAY_CPUINFO /* Display at console. */ #define CONFIG_ARCH_CPU_INIT /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 /* 32kB internal SRAM */ #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ @@ -79,7 +78,6 @@ /* SPI */ #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define AT91_SPI_CLK 15000000 /* Serial port */ @@ -150,7 +148,7 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) #endif /* JFFS2 */ @@ -178,6 +176,7 @@ /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h new file mode 100644 index 0000000000..1f3ee55098 --- /dev/null +++ b/include/configs/exynos-common.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Common configuration settings for the SAMSUNG EXYNOS boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EXYNOS_COMMON_H +#define __EXYNOS_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ + +#include /* get chip and board defs */ +#include + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* Keep L2 Cache Disabled */ +#define CONFIG_CMD_CACHE + +/* input clock of PLL: 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_ENV_OVERWRITE + +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_SDHCI +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* PWM */ +#define CONFIG_PWM + +/* Command definition*/ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC + +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h new file mode 100644 index 0000000000..41631c72e9 --- /dev/null +++ b/include/configs/exynos4-common.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS4_COMMON_H +#define __CONFIG_EXYNOS4_COMMON_H + +#define CONFIG_EXYNOS4 /* Exynos4 Family */ + +#include "exynos-common.h" + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_REVISION_TAG + +/* SD/MMC configuration */ +#define CONFIG_MMC_SDMA +#define CONFIG_MMC_DEFAULT_DEV 0 + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_ONENAND +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_DFU +#define CONFIG_CMD_GPT +#define CONFIG_CMD_PMIC +#define CONFIG_CMD_SETEXPR + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET + +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 +#define CONFIG_G_DNL_MANUFACTURER "Samsung" + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE + +#endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h new file mode 100644 index 0000000000..0ba39a23dd --- /dev/null +++ b/include/configs/exynos5-common.h @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5_COMMON_H +#define __CONFIG_EXYNOS5_COMMON_H + +#define CONFIG_EXYNOS5 /* Exynos5 Family */ + +#include "exynos-common.h" + +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_EXYNOS_SPL + +/* Allow tracing to be enabled */ +#define CONFIG_TRACE +#define CONFIG_CMD_TRACE +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) +#define CONFIG_TRACE_EARLY_SIZE (8 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x50000000 + + +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_SHA_HW_ACCEL + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 +#define INFORM2_OFFSET 0x808 +#define INFORM3_OFFSET 0x80c + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 +#define CONFIG_SILENT_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX + +#define CONFIG_CMD_HASH + +/* Thermal Management Unit */ +#define CONFIG_EXYNOS_TMU +#define CONFIG_CMD_DTT +#define CONFIG_TMU_CMD_DTT + +/* TPM */ +#define CONFIG_TPM +#define CONFIG_CMD_TPM +#define CONFIG_TPM_TIS_I2C +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 + +/* MMC SPL */ +#define COPY_BL2_FNPTR_ADDR 0x02020030 +#define CONFIG_SUPPORT_EMMC_BOOT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* specific .lds file */ +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" + +/* Boot Argument Buffer Size */ +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_RD_LVL + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_SECURE_BL1_ONLY + +/* Secure FW size configuration */ +#ifdef CONFIG_SECURE_BL1_ONLY +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ +#else +#define CONFIG_SEC_FW_SIZE 0 +#endif + +/* Configuration of BL1, BL2, ENV Blocks on mmc */ +#define CONFIG_RES_BLOCK_SIZE (512) +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ + +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) + +/* U-boot copy size from boot Media to DRAM.*/ +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) + +#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 +#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) + +/* I2C */ +#define CONFIG_DM_I2C +#define CONFIG_DM_I2C_COMPAT +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 +#define CONFIG_I2C_EDID + +/* SPI */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_EXYNOS_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define EXYNOS5_SPI_NUM_CONTROLLERS 5 +#define CONFIG_OF_SPI +#endif + +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif + +/* Ethernet Controllor Driver */ +#ifdef CONFIG_CMD_NET +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x5000000 +#define CONFIG_SMC911X_16_BIT +#define CONFIG_ENV_SROM_BANK 1 +#endif /*CONFIG_CMD_NET*/ + +/* SHA hashing */ +#define CONFIG_CMD_HASH +#define CONFIG_HASH_VERIFY +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +/* Enable Time Command */ +#define CONFIG_CMD_TIME + +#define CONFIG_CMD_GPIO + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX + +/* USB boot mode */ +#define CONFIG_USB_BOOTING +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 +#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 + +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#ifndef MEM_LAYOUT_ENV_SETTINGS +/* 2GB RAM, bootm size of 256M, load scripts after that */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "ramdisk_addr_r=0x43300000\0" \ + "scriptaddr=0x50000000\0" \ + "pxefile_addr_r=0x51000000\0" +#endif + +#ifndef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#ifndef EXYNOS_FDTFILE_SETTING +#define EXYNOS_FDTFILE_SETTING +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + EXYNOS_FDTFILE_SETTING \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV + +#endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h new file mode 100644 index 0000000000..9cef0b0a38 --- /dev/null +++ b/include/configs/exynos5-dt-common.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * Configuration settings for generic Exynos 5 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5_DT_COMMON_H +#define __CONFIG_EXYNOS5_DT_COMMON_H + +/* Console configuration */ +#undef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +#include "exynos5-common.h" + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65090 + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +#endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h new file mode 100644 index 0000000000..ae0e5ff47b --- /dev/null +++ b/include/configs/exynos5250-common.h @@ -0,0 +1,56 @@ + +/* + * Copyright (C) 2012 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5250 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_5250_H +#define __CONFIG_5250_H + +#include +#define CONFIG_EXYNOS5250 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ +#define MACH_TYPE_SMDK5250 3774 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 + +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + +#define CONFIG_SPL_TEXT_BASE 0x02023400 + +#define CONFIG_IRAM_STACK 0x02050000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK + +/* Sound */ +#define CONFIG_CMD_SOUND +#ifdef CONFIG_CMD_SOUND +#define CONFIG_SOUND +#define CONFIG_I2S_SAMSUNG +#define CONFIG_I2S +#define CONFIG_SOUND_MAX98095 +#define CONFIG_SOUND_WM8994 +#endif + +/* I2C */ +#define CONFIG_MAX_I2C_NUM 8 + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#endif /* __CONFIG_5250_H */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h deleted file mode 100644 index 8f8f85f440..0000000000 --- a/include/configs/exynos5250-dt.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5250 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ -#define CONFIG_SMDK5250 /* which is in a SMDK5250 */ - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* Enable fdt support for Exynos5250 */ -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - -/* Allow tracing to be enabled */ -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF - -/* Enable ACE acceleration for SHA1 and SHA256 */ -#define CONFIG_EXYNOS_ACE_SHA -#define CONFIG_SHA_HW_ACCEL - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 - -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ -#define MACH_TYPE_SMDK5250 3774 -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - -/* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE - -/* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC -#define CONFIG_KEYBOARD - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_SUPPORT_EMMC_BOOT - - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET -#define CONFIG_CMD_HASH - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* Thermal Management Unit */ -#define CONFIG_EXYNOS_TMU -#define CONFIG_CMD_DTT -#define CONFIG_TMU_CMD_DTT - -/* USB */ -#define CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_EXYNOS -#define CONFIG_USB_STORAGE - -/* USB boot mode */ -#define CONFIG_USB_BOOTING -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 - -/* TPM */ -#define CONFIG_TPM -#define CONFIG_CMD_TPM -#define CONFIG_TPM_TIS_I2C -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 - -/* MMC SPL */ -#define CONFIG_SPL -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_SPL_LIBCOMMON_SUPPORT - -/* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -#define CONFIG_SPL_TEXT_BASE 0x02023400 -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "SMDK5250 # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_RD_LVL - -#define CONFIG_NR_DRAM_BANKS 8 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS -#define CONFIG_IDENT_STRING " for SMDK5250" - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) -#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) - -/* U-boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define CONFIG_SPI_BOOTING -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 -#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - - -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK - -/* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_HARD_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ -#define CONFIG_DRIVER_S3C24X0_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_I2C_EDID - -/* PMIC */ -#define CONFIG_PMIC -#define CONFIG_PMIC_I2C -#define CONFIG_PMIC_MAX77686 - -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_MAX77686 - -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif - -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - -/* Sound */ -#define CONFIG_CMD_SOUND -#ifdef CONFIG_CMD_SOUND -#define CONFIG_SOUND -#define CONFIG_I2S -#define CONFIG_SOUND_MAX98095 -#define CONFIG_SOUND_WM8994 -#endif - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -/* SHA hashing */ -#define CONFIG_CMD_HASH -#define CONFIG_HASH_VERIFY -#define CONFIG_SHA1 -#define CONFIG_SHA256 - -/* Display */ -#define CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_XRES 2560 -#define LCD_YRES 1600 -#define LCD_BPP LCD_COLOR16 -#endif - -/* Enable Time Command */ -#define CONFIG_CMD_TIME - -#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h new file mode 100644 index 0000000000..fe72bd0d3b --- /dev/null +++ b/include/configs/exynos5420-common.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5420 SoC + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5420_H +#define __CONFIG_EXYNOS5420_H + +#define CONFIG_EXYNOS5420 +/* A variant of Exynos5420 (Exynos5 Family) */ +#define CONFIG_EXYNOS5800 + +#include + +#define CONFIG_ARCH_EARLY_INIT_R + +#define MACH_TYPE_SMDK5420 8002 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 + +#define CONFIG_VAR_SIZE_SPL + +#ifdef CONFIG_VAR_SIZE_SPL +#define CONFIG_SPL_TEXT_BASE 0x02024410 +#else +#define CONFIG_SPL_TEXT_BASE 0x02024400 +#endif +#define CONFIG_IRAM_TOP 0x02074000 + +#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) + +#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \ + "exynos5420-peach-pit exynos5420-smdk5420" + +#define CONFIG_MAX_I2C_NUM 11 + +#define CONFIG_BOARD_REV_GPIO_COUNT 2 + +#endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index 14f0784817..338d3dc782 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -10,19 +10,12 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_FAVR32_EZKIT #define CONFIG_FAVR32_EZKIT_EXT_FLASH -/* - * Timer clock frequency. We're using the CPU-internal COUNT register - * for this, so this is equivalent to the CPU core clock frequency - */ -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the diff --git a/include/configs/flea3.h b/include/configs/flea3.h index cfcaf1b232..7f10e9b932 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -7,7 +7,7 @@ * * Configuration for the flea3 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,8 +16,6 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX35 #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 32 @@ -50,11 +48,10 @@ /* * Hardware drivers */ -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ +#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO @@ -130,8 +127,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - /* * Physical Memory Map */ diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 984f274512..b555d82ddc 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -11,7 +11,7 @@ * (C) Copyright 2009 * Eric Millbrandt, DEKA Research and Development Corporation * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -23,8 +23,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ /* @@ -352,7 +351,6 @@ #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_DISPLAY_BOARDINFO 1 @@ -360,10 +358,9 @@ #define CONFIG_CRC32_VERIFY 1 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_VERSION_VARIABLE 1 diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index cfb2a72716..12fd75d743 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -6,7 +6,7 @@ * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -21,7 +21,6 @@ #define CONFIG_440GR 1 /* Specific PPC440GR support */ #define CONFIG_HOSTNAME gdppc440etx #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 @@ -33,6 +32,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_SYS_GENERIC_BOARD #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 30a5859c55..836515d178 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -15,6 +15,8 @@ #ifndef _CONFIG_GOFLEXHOME_H #define _CONFIG_GOFLEXHOME_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -24,7 +26,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_GOFLEXHOME /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/gose.h b/include/configs/gose.h new file mode 100644 index 0000000000..44c8a3053a --- /dev/null +++ b/include/configs/gose.h @@ -0,0 +1,104 @@ +/* + * include/configs/gose.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __GOSE_H +#define __GOSE_H + +#undef DEBUG +#define CONFIG_R8A7793 +#define CONFIG_RMOBILE_BOARD_STRING "Gose" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +/* STACK */ +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#endif + +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE 0x40000000 +#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000 + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF0 +#define CONFIG_SCIF_USE_EXT_CLK + +/* FLASH */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SPI +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_SPANSION + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF0 */ +#define CONFIG_SMSTP7_ENA 0x00200000 + +#endif /* __GOSE_H */ diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index 4f286bd941..854807d486 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -8,7 +8,7 @@ * (C) Copyright 2008 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H__ @@ -19,8 +19,6 @@ * (easy to change) */ -#define CONFIG_LEON3 /* This is an LEON3 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ #define CONFIG_CPCI_AX2000 1 /* ... on GR-CPCI-AX2000 board */ #define CONFIG_LEON_RAM_SRAM 1 @@ -289,7 +287,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -304,8 +301,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Various low-level settings */ diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index fac7f1c5f1..ed2dd2a847 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -9,7 +9,7 @@ * (C) Copyright 2008 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H__ @@ -20,8 +20,6 @@ * (easy to change) */ -#define CONFIG_LEON3 /* This is an LEON3 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ /* Altera NIOS Development board, Stratix II board */ #define CONFIG_GR_EP2S60 1 @@ -278,7 +276,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -293,8 +290,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /*----------------------------------------------------------------------- * USB stuff *----------------------------------------------------------------------- diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index 7f0c5be0c9..e3cbb6f596 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -7,7 +7,7 @@ * (C) Copyright 2007 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H__ @@ -18,8 +18,6 @@ * (easy to change) */ -#define CONFIG_LEON3 /* This is an LEON3 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ #define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */ /* CPU / AMBA BUS configuration */ @@ -237,7 +235,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -252,8 +249,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Various low-level settings */ diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index c288b39f2d..73534addfc 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -11,16 +11,9 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 -/* - * Timer clock frequency. We're using the CPU-internal COUNT register - * for this, so this is equivalent to the CPU core clock frequency - */ -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 612451904f..1e089a9bf7 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -7,7 +7,7 @@ * (C) Copyright 2007 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H__ @@ -24,8 +24,6 @@ * */ -#define CONFIG_LEON3 /* This is an LEON3 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ #define CONFIG_GRSIM 0 /* ... not running on GRSIM */ #define CONFIG_TSIM 1 /* ... running on TSIM */ @@ -55,6 +53,7 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_IRQ #define CONFIG_CMD_ITEST /* Integer (and string) test */ #define CONFIG_CMD_LOADB /* loadb */ @@ -264,7 +263,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -279,8 +277,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /***** Gaisler GRLIB IP-Cores Config ********/ /* AMBA Plug & Play info display on startup */ diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 2226f5bbb8..66194a8ff0 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -6,7 +6,7 @@ * (C) Copyright 2007 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H__ @@ -23,8 +23,6 @@ * */ -#define CONFIG_LEON2 /* This is an LEON2 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ #define CONFIG_GRSIM 0 /* ... not running on GRSIM */ #define CONFIG_TSIM 1 /* ... running on TSIM */ @@ -53,6 +51,7 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_IRQ #define CONFIG_CMD_ITEST /* Integer (and string) test */ #define CONFIG_CMD_LOADB /* loadb */ @@ -262,7 +261,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -277,8 +275,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /***** Gaisler GRLIB IP-Cores Config ********/ #define CONFIG_SYS_GRLIB_SDRAM 0 diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index e401e7e9b8..8e53af8c04 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -1,5 +1,6 @@ /* - * (C) Copyright 2009 + * (C) Copyright 2009-2014 + * Gerald Kerma * Marvell Semiconductor * Written-by: Siddarth Gore * @@ -9,6 +10,8 @@ #ifndef _CONFIG_GURUPLUG_H #define _CONFIG_GURUPLUG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -18,23 +21,41 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_GURUPLUG /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ + /* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB -#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT /* * mv-common.h should be defined after CMD configs since it used them @@ -56,24 +77,38 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */ /* * Default environment variables */ -#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ - "${x_bootcmd_ethernet}; setenv ethact egiga1; " \ - "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "x_bootcmd_ethernet=ping 192.168.2.1\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \ - "x_bootargs=console=ttyS0,115200\0" \ - "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "896K(uboot),128K(uboot_env)," \ + "-@1M(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/zImage\0" \ + "fdt=/boot/guruplug-server-plus.dtb\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" + +#define MTDIDS_DEFAULT "nand0=orion_nand" + +#define MTDPARTS_DEFAULT \ + "mtdparts="CONFIG_MTDPARTS /* * Ethernet Driver configuration @@ -90,6 +125,20 @@ #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #endif /*CONFIG_MVSATA_IDE*/ +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + #define CONFIG_SYS_ALT_MEMTEST #endif /* _CONFIG_GURUPLUG_H */ diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h deleted file mode 100644 index 545fa85377..0000000000 --- a/include/configs/gw8260.h +++ /dev/null @@ -1,803 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the board configuartion for the GW8260 board. - * - * MODULE DEPENDENCY: - * None - * - * RESTRICTIONS/LIMITATIONS: - * None - * - * Copyright (c) 2001, Advent Networks, Inc. - */ -/*********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* Enable debug prints */ -#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CONFIG_SYS_SBC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_SBC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE. - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 8 - -/* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot. - * Note: the 'flashchecksum' environment variable must also be set to 'y'. - */ -#define CONFIG_SYS_FLASH_CHECKSUM - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? - */ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* - * GW8260 with 16 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x00F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x00F5 FFB0 Board Info Data - * 0x00F6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 256k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x00FC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - -/* - * GW8260 with 64 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x03F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x03F5 FFB0 Board Info Data - * 0x03F6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 256k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x03FC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ - -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ - -#ifdef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif /* CONFIG_ETHER_ON_SCC */ - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ - -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) -#endif /* CONFIG_ETHER_ON_FCC */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 115200 - -/* Ethernet MAC address - This is set to all zeros to force an - * an error if we use BOOTP without setting - * the MAC address - */ -#define CONFIG_ETHADDR 00:00:00:00:00:00 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds, press \" \" to stop\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII - -#undef CONFIG_CMD_KGDB - - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xf0000000 - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* What is the address of IO controller */ -#define CONFIG_SYS_IO_BASE 0xe0000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_GW8260 1 /* on an GW8260 Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Convert clocks to MHZ when passing board info to kernel. - * This must be defined for eariler 2.4 kernels (~2.4.4). - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - - -/* memtest works from the end of the exception vector table - * to the end of the DRAM less monitor and malloc area - */ -#define CONFIG_SYS_MEMTEST_START 0x2000 - -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ - -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ - - CONFIG_SYS_MEM_END_USAGE ) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \ - HRCW_DPPC11 | \ - CONFIG_SYS_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024)) -# define CONFIG_ENV_SECT_SIZE (256 * 1024) -#else -# define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */ -# define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE) -# define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */ -#endif /* CONFIG_ENV_IN_OWN_SECT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) - * 1 60x GPCM 32 bit unused - * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB) - * 3 60x SDRAM 64 bit unused - * 4 Local GPCM 8 bit IO (on board - 64k) - * 5 60x GPCM 8 bit unused - * 6 60x GPCM 8 bit unused - * 7 60x GPCM 8 bit unused - * - */ - -/*----------------------------------------------------------------------- - * BR0 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0,1 - FLASH SIMM - * - * This expects the FLASH SIMM to be connected to *CS0 - * It consists of 4 AM29F016D parts. - * - * Note: For the 8 MB SIMM, *CS1 is unused. - */ - -/* BR0 is configured as follows: - * - * - Base address of 0x40000000 - * - 32 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 8 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2 - SDRAM DIMM - * - * 16MB DIMM: P/N - * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or - * MT4LSDT864AG-10EB1 (Micron) - * - * Note: *CS3 is unused for this DIMM - */ - -/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 16 MB DIMM, the OR2 is configured as follows: - * - * - 16 MB - * - 2 internal banks per device - * - Row start address bit is A9 with PSDMR[PBI] = 0 - * - 11 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM0_SIZE == 16) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_2 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_11) - -/* With a 16 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A16-A18 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A16_A18 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */ - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM0_SIZE == 64) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) - -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */ - -#define CONFIG_SYS_PSRT 0x0e -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 - - -/*----------------------------------------------------------------------- - * BR4 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR4 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ -/* Bank 4 - Onboard Memory Mapped IO controller - * - * This expects the onboard IO controller to connected to *CS4 and - * the local bus. - * - Base address of 0xe0000000 - * - 8 bit port size (local bus only) - * - Read and write access - * - GPCM local bus - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - * - extended hold time - * - 11 wait states - */ - -#ifdef CONFIG_SYS_IO_BASE -# define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_L |\ - BRx_V) - -# define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_SCY_11_CLK |\ - ORxG_EHTR) -#endif /* CONFIG_SYS_IO_BASE */ -#endif /* __CONFIG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h new file mode 100644 index 0000000000..6e4f1264d9 --- /dev/null +++ b/include/configs/gw_ventana.h @@ -0,0 +1,459 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SPL */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +/* +#define CONFIG_SPL_SATA_SUPPORT +*/ +/* Location in NAND to read U-Boot from */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024) + +#include "imx6_spl.h" /* common IMX6 SPL configuration */ +#include "mx6_common.h" +#define CONFIG_DISPLAY_CPUINFO /* display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO_LATE /* display board info (after reloc) */ + +#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ + +#include +#include + +/* ATAGs */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + +/* Init Functions */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +/* GPIO */ +#define CONFIG_MXC_GPIO + +/* Serial */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +#ifdef CONFIG_SPI_FLASH + +/* SPI */ +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF + #define CONFIG_MXC_SPI + #define CONFIG_SPI_FLASH_MTD + #define CONFIG_SPI_FLASH_BAR + #define CONFIG_SPI_FLASH_WINBOND + #define CONFIG_SF_DEFAULT_BUS 0 + #define CONFIG_SF_DEFAULT_CS 0 + /* GPIO 3-19 (21248) */ + #define CONFIG_SF_DEFAULT_SPEED 30000000 + #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +#else +/* Enable NAND support */ +#define CONFIG_CMD_TIME +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_MXS + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_NAND_5_ADDR_CYCLE + #define CONFIG_SYS_NAND_ONFI_DETECTION + + /* DMA stuff, needed for GPMI/MXS NAND support */ + #define CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_BURST + #define CONFIG_APBH_DMA_BURST8 +#endif + +#endif /* CONFIG_SPI_FLASH */ + +/* Flattened Image Tree Suport */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_I2C_GSC 0 +#define CONFIG_I2C_PMIC 1 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* Filesystem support */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_UBIFS +#define CONFIG_DOS_PARTITION + +/* Network config - Allow larger/faster download for TFTP/NFS */ +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_NFS_READ_SIZE 4096 + +/* + * SATA Configs + */ +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/* + * PCI express + */ +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCI_FIXUP_DEV +#define CONFIG_PCIE_IMX +#endif + +/* + * PMIC + */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CONFIG_POWER_LTC3676 +#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c + +/* Various command support */ +#include +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */ +#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_GSC +#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */ +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_FUSE /* eFUSE read/write support */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + + +/* Ethernet support */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_ARP_TIMEOUT 200UL + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +/* serial console (ttymxc1,115200) */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Ventana > " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_HWCONFIG + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Memory configuration */ +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#define CONFIG_SYS_LOAD_ADDR 0x12000000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH /* no NOR flash */ + +/* + * MTD Command for mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#ifdef CONFIG_SPI_FLASH +#define MTDIDS_DEFAULT "nor0=nor" +#define MTDPARTS_DEFAULT \ + "mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)" +#else +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" +#endif + +/* Persistent Environment Config */ +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#else +#define CONFIG_ENV_IS_IN_NAND +#endif +#if defined(CONFIG_ENV_IS_IN_MMC) + #define CONFIG_ENV_OFFSET (6 * 64 * 1024) + #define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_NAND) + #define CONFIG_ENV_OFFSET (16 << 20) + #define CONFIG_ENV_SECT_SIZE (128 << 10) + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + #define CONFIG_ENV_OFFSET (512 * 1024) + #define CONFIG_ENV_SECT_SIZE (64 * 1024) + #define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS + #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS + #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE + #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* Environment */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.146 +#define HWCONFIG_DEFAULT \ + "hwconfig=rs232;" \ + "dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "console=ttymxc1\0" \ + "bootdevs=usb mmc sata flash\0" \ + HWCONFIG_DEFAULT \ + "video=\0" \ + \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=0x18000000\0" \ + "loadfdt=" \ + "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \ + "echo Loaded DTB from boot/${fdt_file}; " \ + "elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \ + "echo Loaded DTB from boot/${fdt_file1}; " \ + "elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \ + "echo Loaded DTB from boot/${fdt_file2}; " \ + "fi\0" \ + \ + "script=boot/6x_bootscript-ventana\0" \ + "loadscript=" \ + "if ${fsload} ${loadaddr} ${script}; then " \ + "source; " \ + "fi\0" \ + \ + "uimage=boot/uImage\0" \ + "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \ + "mmc_boot=" \ + "setenv fsload 'ext2load mmc 0:1'; " \ + "mmc dev 0 && mmc rescan && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mmcblk0p1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + \ + "sata_boot=" \ + "setenv fsload 'ext2load sata 0:1'; sata init && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + "usb_boot=" \ + "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" + +#ifdef CONFIG_SPI_FLASH + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ + "image_uboot=ventana/u-boot_spi.imx\0" \ + \ + "spi_koffset=0x90000\0" \ + "spi_klen=0x200000\0" \ + \ + "spi_updateuboot=echo Updating uboot from " \ + "${serverip}:${image_uboot}...; " \ + "tftpboot ${loadaddr} ${image_uboot} && " \ + "sf probe && sf erase 0 80000 && " \ + "sf write ${loadaddr} 400 ${filesize}\0" \ + "spi_update=echo Updating OS from ${serverip}:${image_os} " \ + "to ${spi_koffset} ...; " \ + "tftp ${loadaddr} ${image_os} && " \ + "sf probe && " \ + "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ + \ + "flash_boot=" \ + "if sf probe && " \ + "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mtdblock3 " \ + "rootfstype=squashfs,jffs2 " \ + "${video} ${extra}; " \ + "bootm; " \ + "fi\0" +#else + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ + \ + "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ + "tftp ${loadaddr} ${image_rootfs} && " \ + "nand erase.part rootfs && " \ + "nand write ${loadaddr} rootfs ${filesize}\0" \ + \ + "flash_boot=" \ + "setenv fsload 'ubifsload'; " \ + "ubi part rootfs && ubifsmount ubi0:rootfs; " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=ubifs ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "ubifsumount; " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "ubifsumount; bootm; " \ + "fi; " \ + "fi\0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "for btype in ${bootdevs}; do " \ + "echo; echo Attempting ${btype} boot...; " \ + "if run ${btype}_boot; then; fi; " \ + "done" + +/* Device Tree Support */ +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_LIBFDT +#define CONFIG_FDT_FIXUP_PARTITIONS + +#ifndef CONFIG_SYS_DCACHE_OFF + #define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/h2200.h b/include/configs/h2200.h index 19ecc9ad6c..109cee985b 100644 --- a/include/configs/h2200.h +++ b/include/configs/h2200.h @@ -12,13 +12,12 @@ #define MACH_TYPE_H2200 341 #define CONFIG_MACH_TYPE MACH_TYPE_H2200 +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_CPU_PXA25X 1 #define CONFIG_BOARD_H2200 #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_HZ 1000 - #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ @@ -117,13 +116,13 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } -#define CONFIG_CMD_IMPORTENV 1 #define CONFIG_CMD_LOADB #define CONFIG_CMD_SOURCE #define CONFIG_CMD_RUN #define CONFIG_CMD_IMI #define CONFIG_FIT +#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h deleted file mode 100644 index 4ba2c55e98..0000000000 --- a/include/configs/h2_p2_dbg_board.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * TI H2 and P2 Debug Board hardware map - * - * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) - * Author: MPC-Data Limited - * Dave Peverley - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __INCLUDED_H2_P2_DBH_BOARD_H -#define __INCLUDED_H2_P2_DBH_BOARD_H - -#include - -/* - * The Debug board is designed to function with the P2 Sample, H2 - * Sample and 1610 Innovator boards. The main difference AFAICT is - * the chip selects used with each system ; - * - * P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs - * H2 Sample : CS1a is used to select the CPLD registers. - * - */ - -/*************************************************************************** - * CPLD Registers - **************************************************************************/ - -#define H2DBG_CPLD_REVISION 0x04000010 -#define H2DBG_BOARD_REVISION 0x04000012 -#define H2DBG_GPIO_REGISTER 0x04000014 -#define H2DBG_LED_CONTROL 0x04000016 -#define H2DBG_MISC_INPUT 0x04000018 -#define H2DBG_LAN_STATUS 0x0400001A -#define H2DBG_LAN_RESET 0x0400001C -#define H2DBG_ETH_REG_BASE 0x04000300 - -/*************************************************************************** - * Ethernet Control Registers - * These are for the LAN91C96 on the debug board - **************************************************************************/ - -/* Bank 0 in IO space */ - -#define ETH_TCR (H2DBG_ETH_REG_BASE + 0x00) /* Transmit Control Register */ -#define ETH_EPH_STATUS (H2DBG_ETH_REG_BASE + 0x02) /* EPH Status Register */ -#define ETH_RCR (H2DBG_ETH_REG_BASE + 0x04) /* Receive Control Register */ -#define ETH_COUNTER (H2DBG_ETH_REG_BASE + 0x06) /* Counter Register */ -#define ETH_MIR (H2DBG_ETH_REG_BASE + 0x08) /* Memory Information Register */ -#define ETH_MCR (H2DBG_ETH_REG_BASE + 0x0A) /* Memory Configuration Register */ - -/* Bank 1 in IO space */ - -#define ETH_CONFIG (H2DBG_ETH_REG_BASE + 0x00) /* Configuration Register */ -#define ETH_BASE (H2DBG_ETH_REG_BASE + 0x02) /* Base Address Register */ -#define ETH_IA0 (H2DBG_ETH_REG_BASE + 0x04) /* Individual Address Register - 0 */ -#define ETH_IA1 (H2DBG_ETH_REG_BASE + 0x05) /* Individual Address Register - 1 */ -#define ETH_IA2 (H2DBG_ETH_REG_BASE + 0x06) /* Individual Address Register - 2 */ -#define ETH_IA3 (H2DBG_ETH_REG_BASE + 0x07) /* Individual Address Register - 3 */ -#define ETH_IA4 (H2DBG_ETH_REG_BASE + 0x08) /* Individual Address Register - 4 */ -#define ETH_IA5 (H2DBG_ETH_REG_BASE + 0x09) /* Individual Address Register - 5 */ -#define ETH_GEN_PURPOSE (H2DBG_ETH_REG_BASE + 0x0A) /* General Address Registers */ -#define ETH_CONTROL (H2DBG_ETH_REG_BASE + 0x0B) /* Control Register */ - -/* Bank 2 in IO space */ - -#define ETH_MMU (H2DBG_ETH_REG_BASE + 0x00) /* MMU Command Register */ -#define ETH_AUTO_TX_START (H2DBG_ETH_REG_BASE + 0x01) /* Auto Tx Start Register */ -#define ETH_PNR (H2DBG_ETH_REG_BASE + 0x02) /* Packet Number Register */ -#define ETH_ARR (H2DBG_ETH_REG_BASE + 0x03) /* Allocation Result Register */ -#define ETH_FIFO (H2DBG_ETH_REG_BASE + 0x04) /* FIFO Ports Register */ -#define ETH_POINTER (H2DBG_ETH_REG_BASE + 0x06) /* Pointer Register */ -#define ETH_DATA_HIGH (H2DBG_ETH_REG_BASE + 0x08) /* Data High Register */ -#define ETH_DATA_LOW (H2DBG_ETH_REG_BASE + 0x0A) /* Data Low Register */ -#define ETH_INT_STATS (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Status Register - RO */ -#define ETH_INT_ACK (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Acknowledge Register -WO */ -#define ETH_INT_MASK (H2DBG_ETH_REG_BASE + 0x0D) /* Interrupt Mask Register */ - - -#ifndef __ASSEMBLY__ - -/* - * A couple of utility inlines to aid debugging using the LED's on the - * debug board. - */ - -static inline void set_led_state(int state) -{ - static unsigned long hw_led_state = 0; - volatile unsigned short *led_address = (volatile unsigned short *)0x04000016; - - hw_led_state = ((unsigned long)state); - *((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF); -} - - -static inline void spin_up_leds(void) -{ - volatile int i, j, k; - - for (k = 0; k < 2; k++) { - for (i = 0; i < 16; i++) { - for (j = 0; j < 5000; j++) { - set_led_state(1 << i); - } - } - for (i = 15; i >= 0; i--) { - for (j = 0; j < 5000; j++) { - set_led_state(1 << i); - } - } - } -} - -#endif /* ! __ASSEMBLY__ */ - -#endif /* ! __INCLUDED_H2_P2_DBH_BOARD_H */ diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index 38c70aca32..4f0603abc1 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -8,13 +8,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_HAMMERHEAD -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 125 MHz, the CPU to run at the PLL * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d733be9cd5..ff9fbc9965 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -8,14 +8,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" -/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-harmony -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (Harmony) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" @@ -61,8 +56,9 @@ /* USB networking support */ #define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX /* General networking support */ #define CONFIG_CMD_NET diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index 2e478cc63c..669e7f1f7a 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -20,15 +20,11 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_HAWK -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg" @@ -47,7 +43,6 @@ #endif /* Spl */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SUPPORT @@ -97,7 +92,6 @@ */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/hermes.h b/include/configs/hermes.h deleted file mode 100644 index 1af529627e..0000000000 --- a/include/configs/hermes.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ -#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * Command line configuration. - */ -#include - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */ -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - * +0x0004 - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * +0x0000 => 0x000000C0 - */ -#define CONFIG_SYS_SIUMCR 0 - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - * +0x0200 => 0x00C2 - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - * +0x0240 => 0x0082 - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* +0x0286 => 0x00B0D0C0 */ -#define CONFIG_SYS_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* +0x0282 => 0x03800000 */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* +0x0220 => 0x00C3 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => TIMEP=1 */ -#define CONFIG_SYS_RCCR 0x0100 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ - -/* used to re-map FLASH - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* allow for max 4 MB of Flash */ -#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \ - OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -/* 8 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR1/OR1 - SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide - */ -#define HPRO2_BASE 0xE0000000 -#define HPRO2_OR_AM 0xFFFF8000 -#define HPRO2_TIMING 0x00000934 - -#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING) -#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3/OR3: not used - * BR4/OR4: not used - * BR5/OR5: not used - * BR6/OR6: not used - * BR7/OR7: not used - */ - -/* - * MAMR settings for SDRAM - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -#endif /* __CONFIG_H */ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index e7459c179b..da1c837cc7 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -7,16 +7,22 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_L2_OFF +#include + +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_NO_FLASH -#define CFG_HZ 1000 -#define CONFIG_SYS_HZ CFG_HZ +#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP #define CONFIG_FIT #define CONFIG_SYS_BOOTMAPSZ (16 << 20) +#define CONFIG_SYS_TIMER_RATE (150000000/256) +#define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) +#define CONFIG_SYS_TIMER_COUNTS_DOWN + /* * Size of malloc() pool */ @@ -27,7 +33,7 @@ #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_SYS_BOOTCOUNT_SINGLEWORD @@ -35,6 +41,7 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c #define CONFIG_MISC_INIT_R +#define CONFIG_LIBATA #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 @@ -42,46 +49,36 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -#define CONFIG_DOS_PARTITION - #define CONFIG_CALXEDA_XGMAC -/* PXE support */ -#define CONFIG_BOOTP_PXE -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.highbank" - /* * Command line configuration. */ #include #define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_MEMORY #define CONFIG_CMD_LOADS #define CONFIG_CMD_SCSI -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds...\nPress to stop or to delay\n", bootdelay +#define CONFIG_AUTOBOOT_KEYED_CTRLC /* * Miscellaneous configurable options */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PROMPT "Highbank #" /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_LOAD_ADDR 0x800000 +#define CONFIG_SYS_64BIT_LBA + /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h deleted file mode 100644 index 747c43c070..0000000000 --- a/include/configs/hmi1001.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_HMI1001 1 /* HMI1001 board */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_BOARD_EARLY_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_DOS_PARTITION - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_MISC_INIT_R 1 - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 - -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_AMD_RESET - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_DISPLAY_BASE 0x80600000 -#define CONFIG_SYS_STATUS1_BASE 0x80600200 -#define CONFIG_SYS_STATUS2_BASE 0x80600300 - -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM - -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) - -#ifdef CONFIG_POST -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 /* MII PHY management */ - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01051004 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_START 0x80100000 -#define CONFIG_SYS_CS1_SIZE 0x00100000 -#define CONFIG_SYS_CS1_CFG 0x19B00 - -/* FRAM 32Kbyte @0x80700000 */ -#define CONFIG_SYS_CS2_START 0x80700000 -#define CONFIG_SYS_CS2_SIZE 0x00008000 -#define CONFIG_SYS_CS2_CFG 0x19800 - -/* Display H1, Status Inputs, EPLD @0x80600000 */ -#define CONFIG_SYS_CS3_START 0x80600000 -#define CONFIG_SYS_CS3_SIZE 0x00100000 -#define CONFIG_SYS_CS3_CFG 0x00019800 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_IDE_PREINIT 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_LOGO - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS - -/*---------------------------------------------------------------------*/ -/* Display addresses */ -/*---------------------------------------------------------------------*/ - -#define CONFIG_PDSP188x -#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38) -#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30) - -#endif /* __CONFIG_H */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h new file mode 100644 index 0000000000..e7df9ad92a --- /dev/null +++ b/include/configs/hrcon.h @@ -0,0 +1,614 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ +#define CONFIG_HRCON 1 /* HRCON board specific */ + +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + +#define CONFIG_IDENT_STRING " hrcon 0.01" + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 + +#define CONFIG_CMD_FPGAD +#define CONFIG_CMD_IOLOOP + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.66MHz, then + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz + * We choose the A type silicon as default, so the core is 400Mhz. + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CORE_TO_CSB_3X1) +/* + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits + * in 8308's HRCWH according to the manual, but original Freescale's + * code has them and I've expirienced some problems using the board + * with BDI3000 attached when I've tried to set these bits to zero + * (UART doesn't work after the 'reset run' command). + */ +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH (\ + SICRH_ESDHC_A_SD |\ + SICRH_ESDHC_B_SD |\ + SICRH_ESDHC_C_SD |\ + SICRH_GPIO_A_GPIO |\ + SICRH_GPIO_B_GPIO |\ + SICRH_IEEE1588_A_GPIO |\ + SICRH_USB |\ + SICRH_GTM_GPIO |\ + SICRH_IEEE1588_B_GPIO |\ + SICRH_ETSEC2_GPIO |\ + SICRH_GPIOSEL_1 |\ + SICRH_TMROBI_V3P3 |\ + SICRH_TSOBI1_V2P5 |\ + SICRH_TSOBI2_V2P5) /* 0x0037f103 */ +#define CONFIG_SYS_SICRL (\ + SICRL_SPI_PF0 |\ + SICRL_UART_PF0 |\ + SICRL_IRQ_PF0 |\ + SICRL_I2C2_PF0 |\ + SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * SERDES + */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of one chip NT5TU64M16HG from NANYA + */ + +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ + +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_BANK_BIT_3 \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00260802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (7 << TIMING_CFG1_CASLAT_SHIFT) \ + | (9 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x26279222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x021848c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x08240100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_16) + /* 0x43100000 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0242 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=4, AL=0 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 + +/* + * FLASH on the Local Bus + */ +#if 1 +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#else +#define CONFIG_SYS_NO_FLASH +#endif + +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ + +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * FPGA + */ +#define CONFIG_SYS_FPGA0_BASE 0xE0600000 +#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ + +/* Window base at FPGA base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET) + +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_FPGA_DONE(k) 0x0010 + +#define CONFIG_SYS_FPGA_COUNT 1 + +#define CONFIG_SYS_MCLINK_MAX 3 + +#define CONFIG_SYS_FPGA_PTR \ + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + +#define CONFIG_PCA953X /* NXP PCA9554 */ +#define CONFIG_PCA9698 /* NXP PCA9698 */ + +#define CONFIG_SYS_I2C_IHS +#define CONFIG_SYS_I2C_IHS_CH0 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_CH1 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2 +#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F +#define CONFIG_SYS_I2C_IHS_CH3 +#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F +#define I2C_SOFT_DECLARATIONS2 +#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F +#define I2C_SOFT_DECLARATIONS3 +#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F +#define I2C_SOFT_DECLARATIONS4 +#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F + +#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} +#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} +#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} + +#ifndef __ASSEMBLY__ +void fpga_gpio_set(unsigned int bus, int pin); +void fpga_gpio_clear(unsigned int bus, int pin); +int fpga_gpio_get(unsigned int bus, int pin); +#endif + +#define I2C_ACTIVE { } +#define I2C_TRISTATE { } +#define I2C_READ \ + (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \ + else \ + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \ + else \ + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \ + } while (0) +#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ + +/* + * Software (bit-bang) MII driver configuration + */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII_MULTI + +/* + * OSD Setup + */ +#define CONFIG_SYS_OSD_SCREENS 1 +#define CONFIG_SYS_DP501_DIFFERENTIAL +#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 + +#define CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +/* + * Environment + */ +#if 1 +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#else +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define CONFIG_HOSTNAME hrcon +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "kernel_addr=1000000\0" \ + "fdt_addr=C00000\0" \ + "fdtfile=hrcon.dtb\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp ${kernel_addr} $bootfile;" \ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + + +#endif /* __CONFIG_H */ diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h new file mode 100644 index 0000000000..d58eacb1ed --- /dev/null +++ b/include/configs/hummingboard.h @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * Configuration settings for the SolidRun Hummingboard. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#include +#include +#include + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 4773 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_I2C + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_MEMTEST +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Ethernet Configuration */ +#define CONFIG_FEC_MXC +#ifdef CONFIG_FEC_MXC +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-hummingboard.dtb" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H * */ diff --git a/include/configs/hymod.h b/include/configs/hymod.h deleted file mode 100644 index f73de6814d..0000000000 --- a/include/configs/hymod.h +++ /dev/null @@ -1,732 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for Hymod board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_HYMOD 1 /* ...on a Hymod board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ -#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ - -#ifdef CONFIG_ETHER_ON_FCC - -#if (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK11 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ -# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ -# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ - -#elif (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ -# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) -#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) -#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ - else iop->pdat &= ~MDIO_DATA_PINMASK - -#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ - else iop->pdat &= ~MDIO_CLCK_PINMASK - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - - -/* other options */ -#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ -#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifdef DEBUG -#define CONFIG_8260_CLKIN 33333333 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 115200 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* default ip addresses - these will be overridden */ -#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ -#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ - -#define CONFIG_LAST_STAGE_INIT - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_XIMG - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ -#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press to stop\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 -#endif - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ -#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ -# if defined(CONFIG_KGDB_USE_EXTC) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -# else -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -# endif -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Hymod specific configurable options - */ -#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0x7e - -/* these are for the ST M24C02 2kbit serial i2c eeprom */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ - -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ - -/* - * standard dtt sensor configuration - bottom bit will determine local or - * remote sensor of the ADM1021, the rest determines index into - * CONFIG_SYS_DTT_ADM1021 array below. - * - * On HYMOD board, the remote sensor should be connected to the MPC8260 - * temperature diode thingy, but an errata said this didn't work and - * should be disabled - so it isn't connected. - */ -#if 0 -#define CONFIG_DTT_SENSORS { 0, 1 } -#else -#define CONFIG_DTT_SENSORS { 0 } -#endif - -/* - * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). - * there will be one entry in this array for each two (dummy) sensors in - * CONFIG_DTT_SENSORS. - * - * For HYMOD board: - * - only one ADM1021 - * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT ouput disabled - * - local temp sensor enabled, min set to 0 deg, max set to 85 deg - * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) - */ -#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#ifdef DEBUG -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0010) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0101) -#endif -/* no slaves so just duplicate the master hrcw */ -#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FPGA_BASE 0x80000000 -/* - * unfortunately, CONFIG_SYS_MONITOR_LEN must include the - * (very large i.e. 256kB) environment flash sector - */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#ifdef DEBUG -#define CONFIG_SYS_HID0_FINAL 0 -#else -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#endif -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#ifdef DEBUG -#define CONFIG_SYS_RMR 0 -#else -#define CONFIG_SYS_RMR RMR_CSRE -#endif - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ - SIUMCR_APPC10|SIUMCR_MMR11) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) - * 2 60x SDRAM 64 bit SDRAM - * 3 Local UPMC 8 bit Main Xilinx configuration - * 4 Local GPCM 32 bit Main Xilinx register mode - * 5 Local UPMB 32 bit Main Xilinx port mode - * 6 Local UPMC 8 bit Mezz Xilinx configuration - */ - -/* - * Bank 0 - FLASH - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The flash memory is two Intel StrataFlash chips, each configured for - * 16 bit operation and connected to give a 32 bit wide port." - * - * "The chip select logic is configured to respond to both *CS0 and *CS1. - * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. - * It is suggested that bank 0 be read-only and bank 1 be read/write. The - * FLASH will then appear as ROM during boot." - * - * Initially, we are only going to use bank 0 in read/write mode. - */ - -/* 32 bit, read-write, GPCM on 60x bus */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\ - BRx_PS_32|BRx_MS_GPCM_P|BRx_V) -/* up to 32 Mb */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) - -/* - * Bank 2 - SDRAM - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a - * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous - * dynamic random access memory organised as 4 banks by 4096 rows by 512 - * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." - * - * "The locations in SDRAM are accessed using multiplexed address pins to - * specify row and column. The pins also act to specify commands. The state - * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP - * pin may function as a row address or as the AUTO PRECHARGE control line, - * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 - * address lines to be configured to the required multiplexing scheme." - */ - -#define CONFIG_SYS_SDRAM_SIZE 64 - -/* 64 bit, read-write, SDRAM on 60x bus */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\ - BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) -/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\ - ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) - -/* - * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: - * - * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 - * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 - * as bank select, A7 is output on SDA10 during an ACTIVATE command, - * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, - * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE - * command is 2 clocks, earliest timing for PRECHARGE after last data - * was read is 1 clock, earliest timing for PRECHARGE after last data - * was written is 1 clock, CAS Latency is 2. - */ - -#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ - PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ - PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ - PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ - PSDMR_WRC_1C|PSDMR_CL_2) - -/* - * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh - * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register - * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer - * Prescaler, hence the P instead of the R). The refresh timer period is given - * by (note that there was a change in the 8260 UM Errata): - * - * TimerPeriod = (PSRT + 1) / Fmptc - * - * where Fmptc is the BusClock divided by PTP. i.e. - * - * TimerPeriod = (PSRT + 1) / (BusClock / PTP) - * - * or - * - * TImerPeriod = (PTP * (PSRT + 1)) / BusClock - * - * The requirement for the Toshiba TC59SM716FTL-10 is that there must be - * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 - * = 15.625 usecs. - * - * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 - * appear to be reasonable. - */ - -#ifdef DEBUG -#define CONFIG_SYS_PSRT 39 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 -#else -#define CONFIG_SYS_PSRT 31 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#endif - -/* - * Banks 3,4,5 and 6 - FPGA access - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made - * for configuring an optional FPGA on the mezzanine interface. - * - * Access to the FPGAs may be divided into several catagories: - * - * 1. Configuration - * 2. Register mode access - * 3. Port mode access - * - * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be - * configured only (mode 1). Consequently there are four access types. - * - * To improve interface performance and simplify software design, the four - * possible access types are separately mapped to different memory banks. - * - * All are accessed using the local bus." - * - * Device Mode Memory Bank Machine Port Size Access - * - * Main Configuration 3 UPMC 8bit R/W - * Main Register 4 GPCM 32bit R/W - * Main Port 5 UPMB 32bit R/W - * Mezzanine Configuration 6 UPMC 8bit W/O - * - * "Note that mezzanine mode 1 access is write-only." - */ - -/* all the bank sizes must be a power of two, greater or equal to 32768 */ -#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) -#define FPGA_MAIN_CFG_SIZE 32768 -#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) -#define FPGA_MAIN_REG_SIZE 32768 -#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) -#define FPGA_MAIN_PORT_SIZE 32768 -#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) -#define FPGA_MEZZ_CFG_SIZE 32768 - -/* 8 bit, read-write, UPMC */ -#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) - -/* 32 bit, read-write, GPCM */ -#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) -/* up to 32Kbyte */ -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) - -/* 32 bit, read-write, UPMB */ -#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) -/* up to 32Kbyte */ -#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) - -/* 8 bit, write-only, UPMC */ -#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) - -/*----------------------------------------------------------------------- - * MBMR - Machine B Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ - -/*----------------------------------------------------------------------- - * MCMR - Machine C Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ - -/* - * FPGA I/O Port/Bit information - */ - -#define FPGA_MAIN_PROG_PORT IOPIN_PORTA -#define FPGA_MAIN_PROG_PIN 4 /* PA4 */ -#define FPGA_MAIN_INIT_PORT IOPIN_PORTA -#define FPGA_MAIN_INIT_PIN 5 /* PA5 */ -#define FPGA_MAIN_DONE_PORT IOPIN_PORTA -#define FPGA_MAIN_DONE_PIN 6 /* PA6 */ - -#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA -#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ -#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA -#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ -#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA -#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ -#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA -#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ - -/* - * FPGA Interrupt configuration - */ -#define FPGA_MAIN_IRQ SIU_INT_IRQ2 - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 7fa0c5356c..f1ddf21580 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -9,6 +9,8 @@ #ifndef _CONFIG_IB62x0_H #define _CONFIG_IB62x0_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -18,7 +20,6 @@ * High level configuration options */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ @@ -27,6 +28,11 @@ */ #define CONFIG_MACH_TYPE MACH_TYPE_NAS6210 +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + /* * Compression configuration */ @@ -41,6 +47,7 @@ #define CONFIG_SYS_MVFS #include #define CONFIG_CMD_ENV +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_IDE #define CONFIG_CMD_MII #define CONFIG_CMD_NAND @@ -66,7 +73,7 @@ #define CONFIG_ENV_IS_NOWHERE #endif #define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_OFFSET 0xe0000 /* * Default environment variables @@ -74,24 +81,26 @@ #define CONFIG_BOOTCOMMAND \ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ "ubi part root; " \ - "ubifsmount ubi:root; " \ + "ubifsmount ubi:rootfs; " \ "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x1100000 ${initrd}; " \ - "bootm 0x800000 0x1100000" - -#define CONFIG_MTDPARTS \ - "mtdparts=orion_nand:" \ - "0x80000@0x0(uboot)," \ - "0x20000@0x80000(uboot_env)," \ - "-@0xa0000(root)\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0xe0000@0x0(uboot)," \ + "0x20000@0xe0000(uboot_env)," \ + "-@0x100000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "mtdids=nand0=orion_nand\0" \ "mtdparts="CONFIG_MTDPARTS \ - "kernel=/boot/uImage\0" \ - "initrd=/boot/uInitrd\0" \ - "bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0" + "kernel=/boot/zImage\0" \ + "fdt=/boot/ib62x0.dtb\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" /* * Ethernet driver configuration diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 5291755121..2a937c6a22 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -82,7 +82,7 @@ #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x12000 /* Total Size of Environment Sector */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else @@ -95,8 +95,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/icon.h b/include/configs/icon.h index eafcf5aeaf..bbe9b59b53 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -16,7 +16,6 @@ * High Level Configuration Options */ #define CONFIG_ICON 1 /* Board is icon */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index a58f076c21..2baf50cc4e 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -9,6 +9,8 @@ #ifndef _CONFIG_ICONNECT_H #define _CONFIG_ICONNECT_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -18,7 +20,6 @@ * High level configuration options */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/idmr.h b/include/configs/idmr.h deleted file mode 100644 index 55ea567bee..0000000000 --- a/include/configs/idmr.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Configuration settings for the iDMR board - * - * Based on MC5272C3, r5200 and M5271EVB board configs - * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2006 Lab X Technologies - * (C) Copyright 2003 Josef Baumgartner - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _IDMR_H -#define _IDMR_H - - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5271 /* define processor type */ -#define CONFIG_IDMR /* define board type */ - -#undef CONFIG_WATCHDOG /* disable watchdog */ - -/* - * Default environment settings - */ -#define CONFIG_BOOTCOMMAND "run net_nfs" -#define CONFIG_BOOTDELAY 5 -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 -#define CONFIG_ETHADDR 00:06:3b:01:41:55 -#define CONFIG_ETHPRIME -#define CONFIG_IPADDR 192.168.30.1 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_ROOTPATH "" -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_HOSTNAME idmr -#define CONFIG_BOOTFILE "/tftpboot/idmr/uImage" -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root " \ - "filesystem over NFS; echo" - -#define CONFIG_MCFTMR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ethact=FEC\0 " \ - "update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \ - "cp.b 200000 ff800000 $(filesize);" \ - "prot on ff800000 ff81ffff\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "u-boot=/tftpboot/idmr/u-boot.bin\0" \ - "" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NET - -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/* - * Configuration for environment, which occupies third sector in flash. - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_ADDR 0xff820000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH -#else /* CONFIG_MONITOR_IS_IN_RAM */ -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH -#endif /* !CONFIG_MONITOR_IS_IN_RAM */ - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#define CONFIG_SYS_HZ (50000000 / 64) -#define CONFIG_SYS_CLK 100000000 - -#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */ - -/* - * Ethernet - */ -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xff800000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else /* !CONFIG_MONITOR_IS_IN_RAM */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif /* CONFIG_MONITOR_IS_IN_RAM */ - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define CONFIG_SYS_FLASH_SIZE 0x800000 -/* - * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - */ - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/* Port configuration */ -#define CONFIG_SYS_FECI2C 0xF0 - - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=idmr-0" - -#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \ - "64k(env)," \ - "640k(kernel)," \ - "2m(rootfs)," \ - "-(user)"; - -#if defined(CONFIG_CMD_MII) -#error "MII commands don't work on iDMR board and should not be enabled." -#endif - -#endif /* _IDMR_H */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h new file mode 100644 index 0000000000..2384864eb0 --- /dev/null +++ b/include/configs/ids8313.h @@ -0,0 +1,584 @@ +/* + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (c) 2011 IDS GmbH, Germany + * Sergej Stepanov + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC831x +#define CONFIG_MPC8313 +#define CONFIG_IDS8313 + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_FSL_ELBC + +#define CONFIG_MISC_INIT_R + +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY +#define CONFIG_AUTOBOOT_DELAY_STR "ids" +#define CONFIG_BOOT_RETRY_TIME 900 +#define CONFIG_BOOT_RETRY_MIN 30 +#define CONFIG_BOOTDELAY 1 +#define CONFIG_RESET_TO_RETRY + +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_SYS_IMMR 0xF0000000 + +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.000MHz, then + * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz + */ +#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_8BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_MII |\ + HRCWH_TSEC2M_IN_MII |\ + HRCWH_BIG_ENDIAN) + +#define CONFIG_SYS_SICRH 0x00000000 +#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) + +#define CONFIG_HWCONFIG + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) + +#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) + +/* + * Definitions for initial stack pointer and data area (in DCACHE ) + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Local Bus LCRR and LBCR regs + */ +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR (0x00040000 |\ + (0xFF << LBCR_BMT_SHIFT) |\ + 0xF) + +#define CONFIG_SYS_LBC_MRTPR 0x20000000 + +/* + * Internal Definitions + */ +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE + +/* + * Manually set up DDR parameters, + * as this board has not the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ + 0x00010000 |\ + CSCONFIG_ROW_BIT_13 |\ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ + CSCONFIG_BANK_BIT_3) + +#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ +#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ + (3 << TIMING_CFG0_WRT_SHIFT) |\ + (3 << TIMING_CFG0_RRT_SHIFT) |\ + (3 << TIMING_CFG0_WWT_SHIFT) |\ + (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_MRS_CYC_SHIFT)) +#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ + (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ + (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ + (7 << TIMING_CFG1_CASLAT_SHIFT) |\ + (4 << TIMING_CFG1_REFREC_SHIFT) |\ + (4 << TIMING_CFG1_WRREC_SHIFT) |\ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ + (2 << TIMING_CFG1_WRTORD_SHIFT)) +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ + (5 << TIMING_CFG2_CPO_SHIFT) |\ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ + (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ + (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ + (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) + +#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ + (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ + SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ + SDRAM_CFG_DBW_32 |\ + SDRAM_CFG_SDRAM_TYPE_DDR2) + +#define CONFIG_SYS_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ + (0x0242 << SDRAM_MODE_SD_SHIFT)) +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ + DDRCDR_PZ_NOMZ |\ + DDRCDR_NZ_NOMZ |\ + DDRCDR_ODT |\ + DDRCDR_M_ODR |\ + DDRCDR_Q_DRN) + +/* + * on-board devices + */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 +#define CONFIG_TSEC_ENET +#define CONFIG_NET_MULTI +#define CONFIG_HARD_SPI +#define CONFIG_HARD_I2C + +/* + * NOR FLASH setup + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_FLASH_SHOW_PROGRESS 50 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_SYS_FLASH_BASE 0xFF800000 +#define CONFIG_SYS_FLASH_SIZE 8 +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ + BR_PS_8 |\ + BR_MS_GPCM |\ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ + OR_GPCM_SCY_10 |\ + OR_GPCM_EHTR |\ + OR_GPCM_TRLX |\ + OR_GPCM_CSNT |\ + OR_GPCM_EAD) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +/* + * NAND FLASH setup + */ +#define CONFIG_SYS_NAND_BASE 0xE1000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_PAGE_SIZE (2048) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) +#define NAND_CACHE_PAGES 64 + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM + +#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ + (2< + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_JFFS2 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ + + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + + +#define CONFIG_NETDEV eth1 +#define CONFIG_HOSTNAME ids8313 +#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" +#define CONFIG_BOOTFILE "ids8313/uImage" +#define CONFIG_UBOOTPATH "ids8313/u-boot.bin" +#define CONFIG_FDTFILE "ids8313/ids8313.dtb" +#define CONFIG_LOADADDR 0x400000 +#define CONFIG_CMD_ENV_FLAGS +#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" + +#define CONFIG_BAUDRATE 115200 + +/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x00C00000 + +#define CONFIG_SYS_LOAD_ADDR 0x100000 +#define CONFIG_MII +#define CONFIG_LOADS_ECHO +#define CONFIG_TIMESTAMP +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run nfsboot\\\" " \ + "to mount root filesystem over NFS;echo" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND "run boot_cramfs" +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "0" + +/* mtdparts command line support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash" +#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \ + "768k(BOOT-BIN)," \ + "128k(BOOT-ENV),128k(BOOT-REDENV);" \ + "e1000000.flash:-(ubi)" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" __stringify(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +${filesize}; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +${filesize}; " \ + "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ + " ${filesize}; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +${filesize}; " \ + "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ + " ${filesize}\0" \ + "console=ttyS0\0" \ + "fdtaddr=0x780000\0" \ + "kernel_addr=ff800000\0" \ + "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ + "setbootargs=setenv bootargs " \ + "root=${rootdev} rw console=${console}," \ + "${baudrate} ${othbootargs}\0" \ + "setipargs=setenv bootargs root=${rootdev} rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off " \ + "console=${console},${baudrate} ${othbootargs}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setipargs;run addmtd;" \ + "tftp ${loadaddr} ${bootfile};" \ + "tftp ${fdtaddr} ${fdtfile};" \ + "fdt addr ${fdtaddr};" \ + "bootm ${loadaddr} - ${fdtaddr}" + +/* UBI Support */ +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS + +/* bootcount support */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_I2C +#define CONFIG_BOOTCOUNT_ALEN 1 +#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9 + +#define CONFIG_VERSION_VARIABLE + +#define CONFIG_IMAGE_FORMAT_LEGACY +#define CONFIG_CMD_FDT +#define CONFIG_CMD_HASH +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#endif /* __CONFIG_H */ diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h deleted file mode 100644 index 12f28f82a8..0000000000 --- a/include/configs/igep0033.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_IGEP0033_H -#define __CONFIG_IGEP0033_H - -#define CONFIG_AM33XX -#define CONFIG_OMAP - -#include - -/* Mach type */ -#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */ -#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033 - -/* Clock defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* DMA defines */ -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot# " -#define CONFIG_SYS_NO_FLASH - -/* Display cpuinfo */ -#define CONFIG_DISPLAY_CPUINFO - -/* Commands to include */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_MMC -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS - -/* - * Because the issues explained in doc/README.memory-test, the "mtest command - * is considered deprecated. It should not be enabled in most normal ports of - * U-Boot. - */ -#undef CONFIG_CMD_MEMTEST - -#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "rdaddr=0x81000000\0" \ - "bootfile=/boot/uImage\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ - "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot;" \ - "fi;" \ - "fi;" \ - -/* Max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) -/* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ - -#define CONFIG_SERIAL_MULTI -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* MMC support */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - -/* GPIO support */ -#define CONFIG_OMAP_GPIO - -/* Ethernet support */ -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI -#define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 -#define CONFIG_PHY_SMSC - -/* NAND support */ -#define CONFIG_NAND -#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_ONFI_DETECTION 1 -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_RBTREE -#define CONFIG_LZO - -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:512k(SPL),"\ - "1m(U-Boot),128k(U-Boot Env),"\ - "5m(Kernel),-(File System)" - -/* Unsupported features */ -#undef CONFIG_USE_IRQ - -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -/* - * Place the image at the start of the ROM defined image space. - * We limit our size to the ROM-defined downloaded image area, and use the - * rest of the space for stack. - */ -#define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_YMODEM_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_NAND_AM33XX_BCH -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 - -#define CONFIG_SYS_NAND_ECCSTEPS 4 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80800000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#endif /* ! __CONFIG_IGEP0033_H */ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h deleted file mode 100644 index c17267e3ad..0000000000 --- a/include/configs/igep00x0.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Common configuration settings for IGEP technology based boards - * - * (C) Copyright 2012 - * ISEE 2007 SL, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __IGEP00X0_H -#define __IGEP00X0_H - -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP_GPIO - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include -#include -#include - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ - -/* - * NS16550 Configuration - */ - -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* define to enable boot progress via leds */ -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ - (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) -#define CONFIG_SHOW_BOOT_PROGRESS -#endif - -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 - -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "IGEP" - -/* commands to include */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#ifdef CONFIG_BOOT_ONENAND -#define CONFIG_CMD_ONENAND /* ONENAND support */ -#endif -#ifdef CONFIG_BOOT_NAND -#define CONFIG_CMD_NAND -#endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ - (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#endif -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" \ - "loadaddr=0x82000000\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=auto\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=jffs2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from onenand ...; " \ - "run nandargs; " \ - "onenand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot;" \ - "fi;" \ - "fi;" \ - "run nandboot;" \ - -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * Physical Memory Map - * - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ - -#ifdef CONFIG_BOOT_ONENAND -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ - -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ -#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET -#endif - -#ifdef CONFIG_BOOT_NAND -#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_BASE NAND_BASE -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ -#define CONFIG_ENV_ADDR NAND_ENV_OFFSET -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * SMSC911x Ethernet - */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_SMC911X -#define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 -#endif /* (CONFIG_CMD_NET) */ - -/* - * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader - * and older u-boot.bin with the new U-Boot SPL. - */ -#define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -/* move malloc and bss high to prevent clashing with the main image */ -#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -/* MMC boot config */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT - -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -#ifdef CONFIG_BOOT_ONENAND -#define CONFIG_SPL_ONENAND_SUPPORT - -/* OneNAND boot config */ -#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 -#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 -#define CONFIG_SPL_ONENAND_LOAD_SIZE \ - (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) - -#endif - -#ifdef CONFIG_BOOT_NAND -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#endif - -#endif /* __IGEP00X0_H */ diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h index ae6828bd78..b5909962f8 100644 --- a/include/configs/ima3-mx53.h +++ b/include/configs/ima3-mx53.h @@ -12,7 +12,6 @@ #define __CONFIG_H /* SOC type must be included before imx-regs.h */ -#define CONFIG_MX53 #include #define CONFIG_DISPLAY_CPUINFO @@ -111,7 +110,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING /* Physical Memory Map */ diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index cda7e0d92b..b6909a97fc 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -4,7 +4,7 @@ * based on: * Copyright (C) 2009 Ilya Yanok * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __IMX27LITE_COMMON_CONFIG_H @@ -13,10 +13,7 @@ /* * SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_MX27 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_CPUINFO @@ -160,7 +157,6 @@ /* * U-Boot general configuration */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print buffer sz */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h index 805c05d77e..c18c35ef53 100644 --- a/include/configs/imx27lite.h +++ b/include/configs/imx27lite.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2009 Ilya Yanok * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 30c65da539..2b74402007 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -6,7 +6,7 @@ * * Configuration settings for the LogicPD i.MX31 Litekit board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -15,8 +15,6 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 1 /* in a mx31 */ #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO @@ -117,8 +115,6 @@ #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ -#define CONFIG_SYS_HZ 1000 - #define CONFIG_CMDLINE_EDITING 1 /*----------------------------------------------------------------------- diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 720e1bf407..74b0b082c3 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -6,7 +6,7 @@ * * Configuration settings for the phyCORE-i.MX31 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -15,8 +15,6 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 /* in a mx31 */ #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO @@ -35,11 +33,9 @@ * Hardware drivers */ -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE @@ -121,8 +117,6 @@ #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ -#define CONFIG_SYS_HZ 1000 - #define CONFIG_CMDLINE_EDITING /* diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h new file mode 100644 index 0000000000..1b9c2773be --- /dev/null +++ b/include/configs/imx6_spl.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __IMX6_SPL_CONFIG_H +#define __IMX6_SPL_CONFIG_H + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_FRAMEWORK + +/* + * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: + * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF + * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well + * - BOOT ROM stack is at 0x0091FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to + * fit between 0x00907000 and 0x00918000. + * - Additionally the BOOT ROM loads what they consider the firmware image + * which consists of a 4K header in front of us that contains the IVT, DCD + * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 + * or 64KB + */ +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_TEXT_BASE 0x00908000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_STACK 0x0091FFB8 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* NAND support */ +#if defined(CONFIG_SPL_NAND_SUPPORT) +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_DMA_SUPPORT +#endif + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) +#endif + +/* SATA support */ +#if defined(CONFIG_SPL_SATA_SUPPORT) +#define CONFIG_SPL_SATA_BOOT_DEVICE 0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_LIBDISK_SUPPORT +#endif + +#define CONFIG_SPL_BSS_START_ADDR 0x18200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */ +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#endif + +#endif diff --git a/include/configs/incaip.h b/include/configs/incaip.h deleted file mode 100644 index 0ff9a7ff82..0000000000 --- a/include/configs/incaip.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file contains the configuration parameters for the INCA-IP board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ -#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */ - -#define CONFIG_XWAY_SWAP_BYTES - -/* - * Clock for the MIPS core (MHz) - * allowed values: 100000000, 133000000, and 150000000 (default) - */ -#ifndef CONFIG_CPU_CLOCK_RATE -#define CONFIG_CPU_CLOCK_RATE 150000000 -#endif - -#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "ethaddr=${ethaddr} " \ - "panic=1\0" \ - "flash_nfs=run nfsargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 80500000 ${bootfile};" \ - "run nfsargs addip addmisc;bootm\0" \ - "rootpath=/opt/eldk/mips_4KC\0" \ - "bootfile=/tftpboot/INCA/uImage\0" \ - "kernel_addr=B0040000\0" \ - "ramdisk_addr=B0100000\0" \ - "u-boot=/tftpboot/INCA/u-boot.bin\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "update=protect off 1:0-2;era 1:0-2;" \ - "cp.b 80500000 B0000000 ${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "INCA-IP # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ - -#define CONFIG_SYS_MALLOC_LEN 128*1024 - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2) - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#define CONFIG_SYS_LOAD_ADDR 0x80100000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */ - -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xB0030000 -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_INCA_IP_SWITCH -#define CONFIG_INCA_IP_SWITCH_AMDIX - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, use all space on the device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=INCA-IP Bank 0" -#define MTDPARTS_DEFAULT "mtdparts=INCA-IP Bank 0:192k(uboot)," \ - "64k(env)," \ - "768k(linux)," \ - "1m@3m(rootfs)," \ - "768k(linux2)," \ - "3m@5m(rootfs2)" -*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 4096 -#define CONFIG_SYS_ICACHE_SIZE 4096 -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#endif /* __CONFIG_H */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 5cc686f2ff..f321975c47 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -5,7 +5,7 @@ * (C) Copyright 2003-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,9 +16,8 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_INKA4X0 1 /* INKA4x0 board */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_INKA4X0 1 /* INKA4x0 board */ /* * Valid values for CONFIG_SYS_TEXT_BASE are: @@ -325,7 +324,6 @@ static inline void tws_data_config_output(unsigned output) * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -348,8 +346,6 @@ static inline void tws_data_config_output(unsigned output) #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Enable loopw command. */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 910c243175..eac517aeeb 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -4,7 +4,7 @@ * Linus Walleij * Common ARM Integrator configuration settings * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #define CONFIG_INTEGRATOR @@ -12,7 +12,6 @@ #define CONFIG_SYS_TEXT_BASE 0x01000000 #define CONFIG_SYS_MEMTEST_START 0x100000 #define CONFIG_SYS_MEMTEST_END 0x10000000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ #define CONFIG_SYS_LONGHELP @@ -27,6 +26,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_OF_LIBFDT /* enable passing a Device Tree */ #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ +#define CONFIG_SYS_GENERIC_BOARD /* * There are various dependencies on the core module (CM) fitted diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index fb71e3c26a..edea769a92 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -9,7 +9,7 @@ * Philippe Robin, * Configuration for Integrator AP board. *. - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index dcbdd227fe..608719a7ea 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -9,7 +9,7 @@ * Philippe Robin, * Configuration for Compact Integrator board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H diff --git a/include/configs/intip.h b/include/configs/intip.h index d3d7a441b6..928eb5b9db 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -30,7 +30,6 @@ #define CONFIG_IDENT_STRING " intip 0.06" #endif #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 @@ -46,6 +45,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_FIT #define CFG_ALT_MEMTEST diff --git a/include/configs/io.h b/include/configs/io.h index 79ada68ac7..d4ae0adfda 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -2,14 +2,13 @@ * (C) Copyright 2010 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_IO 1 /* on a Io board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -25,6 +24,7 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -41,6 +41,7 @@ /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ @@ -65,9 +66,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) @@ -199,9 +205,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* diff --git a/include/configs/io64.h b/include/configs/io64.h index f110b70602..2a9ff376ef 100644 --- a/include/configs/io64.h +++ b/include/configs/io64.h @@ -6,7 +6,7 @@ * by Stefan Roese, DENX Software Engineering, sr@denx.de. * and Grant Erickson * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -20,7 +20,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_IO64 1 /* Board is Io64 */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ @@ -44,6 +43,7 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT +#define CONFIG_SYS_GENERIC_BOARD #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ diff --git a/include/configs/iocon.h b/include/configs/iocon.h index ec9016a6d1..38d473de42 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -2,14 +2,13 @@ * (C) Copyright 2010 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_IOCON 1 /* on a IoCon board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -18,12 +17,13 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME iocon -#define CONFIG_IDENT_STRING " iocon 0.05" +#define CONFIG_IDENT_STRING " iocon 0.06" #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_LAST_STAGE_INIT +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -40,6 +40,7 @@ /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ @@ -65,6 +66,10 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_FPGAD #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) @@ -100,12 +105,27 @@ #define CONFIG_SYS_I2C_PPC4XX_CH0 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS #define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_SPD_BUS_NUM 4 #define CONFIG_PCA953X /* NXP PCA9554 */ #define CONFIG_PCA9698 /* NXP PCA9698 */ +#define CONFIG_SYS_I2C_IHS_CH0 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_CH1 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2 +#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F +#define CONFIG_SYS_I2C_IHS_CH3 +#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F + /* * Software (bit-bang) I2C driver configuration */ @@ -122,7 +142,9 @@ #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} +#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} +#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} +#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3} #ifndef __ASSEMBLY__ void fpga_gpio_set(unsigned int bus, int pin); @@ -150,12 +172,6 @@ int fpga_gpio_get(unsigned int bus, int pin); } while (0) #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ -/* - * OSD hardware - */ -#define CONFIG_SYS_MPC92469AC -#define CONFIG_SYS_CH7301 - /* * FLASH organization */ @@ -239,9 +255,8 @@ int fpga_gpio_get(unsigned int bus, int pin); #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* @@ -285,8 +300,9 @@ int fpga_gpio_get(unsigned int bus, int pin); * OSD Setup */ #define CONFIG_SYS_MPC92469AC -#define CONFIG_SYS_CH7301 #define CONFIG_SYS_OSD_SCREENS 1 +#define CONFIG_SYS_DP501_DIFFERENTIAL +#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ #define CONFIG_BITBANGMII_MULTI diff --git a/include/configs/ip04.h b/include/configs/ip04.h index d36ae43664..2ee215f706 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -61,7 +61,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 #define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) @@ -77,6 +77,7 @@ #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE + 2) +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h new file mode 100644 index 0000000000..982941c9a9 --- /dev/null +++ b/include/configs/ipam390.h @@ -0,0 +1,335 @@ +/* + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * Based on: + * U-Boot:include/configs/da850evm.h + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_BARIX_IPAM390 + +/* + * SoC Configuration + */ +#define CONFIG_MACH_DAVINCI_DA850_EVM +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT +#define CONFIG_SYS_TEXT_BASE 0xc1080000 + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +/* memtest start addr */ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) + +/* memtest will be run on 16MB */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024) + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ + +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_UART0 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC) + +/* + * PLL configuration + */ +#define CONFIG_SYS_DV_CLKMODE 0 +#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 +#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 + +#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 + +#define CONFIG_SYS_DA850_PLL0_PLLM 24 +#define CONFIG_SYS_DA850_PLL1_PLLM 24 + +/* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT)) +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498 + +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020 + + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (2 << DV_DDR_SDCR_CL_SHIFT) | \ + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ + DAVINCI_ABCR_WSTROBE(2) | \ + DAVINCI_ABCR_WHOLD(0) | \ + DAVINCI_ABCR_RSETUP(1) | \ + DAVINCI_ABCR_RSTROBE(2) | \ + DAVINCI_ABCR_RHOLD(1) | \ + DAVINCI_ABCR_TA(0) | \ + DAVINCI_ABCR_ASIZE_8BIT) + + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ + +/* + * Flash & Environment + */ +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_NAND_MASK_CLE 0x10 +#define CONFIG_SYS_NAND_MASK_ALE 0x8 +#undef CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST +#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000 +#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ + CONFIG_SYS_NAND_U_BOOT_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_NAND_ECCPOS { \ + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_LOAD + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +/* + * U-Boot general configuration + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_HWCONFIG /* enable hwconfig */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 2 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \ + "root=/dev/mtdblock5 rw noinitrd " \ + "rootfstype=jffs2 noinitrd\0" \ + "hwconfig=dsp:wake=yes\0" \ + "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \ + "bootfile=uImage\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "mtddevname=uboot-env\0" \ + "mtddevnum=0\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "u-boot=/tftpboot/ipam390/u-boot.ais\0" \ + "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \ + "nand write c0000000 20000 ${filesize}\0" \ + "setbootparms=nand read c0100000 200000 400000;" \ + "run defbootargs addmtd;" \ + "spl export atags c0100000;" \ + "nand erase.part bootparms;" \ + "nand write c0000100 180000 20000\0" \ + "\0" + +/* + * U-Boot commands + */ +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY + +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_LZO +#define CONFIG_RBTREE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +#define MTDIDS_NAME_STR "davinci_nand.0" +#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ + "128k(u-boot-env)," \ + "1408k(u-boot)," \ + "128k(bootparms)," \ + "384k(factory-info)," \ + "4M(kernel)," \ + "-(rootfs)" + +/* defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" +#define CONFIG_SPL_STACK 0x8001ff00 +#define CONFIG_SPL_TEXT_BASE 0x80000000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_MAX_FOOTPRINT 32768 + +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +/* add FALCON boot mode */ +#define CONFIG_CMD_SPL +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 +#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR +#define CONFIG_CMD_SPL_NAND_OFS 0x00180000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 + +/* GPIO support */ +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_DA8XX_GPIO +#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14) + +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) +#define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) + +#endif /* __CONFIG_H */ diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index 50fd995657..41ced15c48 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -5,7 +5,7 @@ * (C) Copyright 2009 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,9 +16,8 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPX5200 1 /* ... on MPX5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ +#define CONFIG_MPX5200 1 /* MPX5200 board */ +#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ #define CONFIG_IPEK01 /* Motherboard is ipek01 */ #define CONFIG_SYS_TEXT_BASE 0xfc000000 @@ -278,7 +277,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -297,7 +295,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_LOOPW /* diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h index d0609f6250..8175621338 100644 --- a/include/configs/jadecpu.h +++ b/include/configs/jadecpu.h @@ -12,10 +12,8 @@ #define CONFIG_MB86R0x #define CONFIG_MB86R0x_IOCLK get_bus_freq(0) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0x10000000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_USE_ARCH_MEMCPY #define CONFIG_USE_ARCH_MEMSET @@ -88,8 +86,8 @@ #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024) #define VIDEO_FB_16BPP_WORD_SWAP #define VIDEO_KBD_INIT_FCT 0 -#define VIDEO_TSTC_FCT serial_tstc -#define VIDEO_GETC_FCT serial_getc +#define VIDEO_TSTC_FCT serial_stub_tstc +#define VIDEO_GETC_FCT serial_stub_getc /* * BOOTP options diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h new file mode 100644 index 0000000000..0a79c7cfc3 --- /dev/null +++ b/include/configs/jetson-tk1.h @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* enable PMIC */ +#define CONFIG_AS3722_POWER + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Jetson TK1) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_RTL8169 + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/jornada.h b/include/configs/jornada.h index 71f1e72528..7e18d8e7b5 100644 --- a/include/configs/jornada.h +++ b/include/configs/jornada.h @@ -70,7 +70,6 @@ #define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */ #define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 } diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 01c087b0d3..7dfaa221ee 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -13,8 +13,7 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* especially an MPC5200 */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_JUPITER 1 /* ... on Jupiter board */ /* @@ -243,7 +242,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -262,8 +260,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if defined(CONFIG_CMD_KGDB) # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h new file mode 100644 index 0000000000..4992d1d2fe --- /dev/null +++ b/include/configs/k2e_evm.h @@ -0,0 +1,42 @@ +/* + * Configuration header file for TI's k2e-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2E_EVM_H +#define __CONFIG_K2E_EVM_H + +/* Platform type */ +#define CONFIG_K2E_EVM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2E EVM # " + +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c140000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "name_fdt=uImage-k2e-evm.dtb\0" \ + "name_mon=skern-k2e-evm.bin\0" \ + "name_ubi=k2e-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2e-evm.gph\0" \ + "name_fs=arago-console-image-k2e-evm.cpio.gz\0" + +#include + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c100000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 9 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + +#endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h new file mode 100644 index 0000000000..594ba0a010 --- /dev/null +++ b/include/configs/k2hk_evm.h @@ -0,0 +1,41 @@ +/* + * Configuration header file for TI's k2hk-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2HK_EVM_H +#define __CONFIG_K2HK_EVM_H + +/* Platform type */ +#define CONFIG_K2HK_EVM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2HK EVM # " + +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c5f0000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "name_fdt=uImage-k2hk-evm.dtb\0" \ + "name_mon=skern-k2hk-evm.bin\0" \ + "name_ubi=k2hk-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ + "name_fs=arago-console-image-k2hk-evm.cpio.gz\0" + +#include + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c200000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_0 +#define CONFIG_KSNET_CPSW_NUM_PORTS 5 + +#endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h new file mode 100644 index 0000000000..9c08690ff7 --- /dev/null +++ b/include/configs/k2l_evm.h @@ -0,0 +1,42 @@ +/* + * Configuration header file for TI's k2l-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2L_EVM_H +#define __CONFIG_K2L_EVM_H + +/* Platform type */ +#define CONFIG_K2L_EVM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2L EVM # " + +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c140000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" \ + "name_fdt=uImage-k2l-evm.dtb\0" \ + "name_mon=skern-k2l-evm.bin\0" \ + "name_ubi=k2l-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2l-evm.gph\0" \ + "name_fs=arago-console-image-k2l-evm.cpio.gz\0" + +#include + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c100000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_4K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 5 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + +#endif /* __CONFIG_K2L_EVM_H */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index ca0df2d0ce..fa72eb02f3 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -18,7 +18,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_KATMAI 1 /* Board is Katmai */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index bd3bbb79a5..1990b2df15 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -5,7 +5,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -19,7 +19,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_KILAUEA 1 /* Board is Kilauea */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ @@ -119,12 +118,7 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * FLASH related @@ -152,61 +146,6 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 405EX the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from location 0xfffff000...0xffffffff the - * NAND controller cannot be accessed since it is attached to CS0 too. - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -231,11 +170,9 @@ * * DDR Autocalibration Method_B is the default. */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A -#endif #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) @@ -417,7 +354,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "logversion=2\0" \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ @@ -435,16 +371,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_SNTP -/* - * Don't run the memory POST on the NAND-booting version. It will - * overwrite part of the U-Boot image which is already loaded from NAND - * to SDRAM. - */ -#if defined(CONFIG_NAND_U_BOOT) -#define CONFIG_SYS_POST_MEMORY_ON 0 -#else #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY -#endif /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ @@ -495,18 +422,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -/* booting from NAND, so NAND chips select has to be on CS 0 */ -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ - -/* Memory Bank 1 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x05806500 -#define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000) -#else #define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ @@ -516,7 +431,6 @@ /* Memory Bank 1 (NAND-FLASH) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x018003c0 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000) -#endif /* Memory Bank 2 (FPGA) initialization */ #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index a82987d6a0..517f46a3a3 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -2,7 +2,7 @@ * (C) Copyright 2008-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_KEYMILE_H @@ -18,6 +18,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_DEFAULTENV_VARS +#define CONFIG_CMD_GREPENV #define CONFIG_CMD_ECHO #define CONFIG_CMD_IMMAP #define CONFIG_CMD_MII @@ -38,7 +39,6 @@ */ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -54,16 +54,12 @@ #define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */ - #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_LOADS_ECHO #define CONFIG_SYS_LOADS_BAUD_CHANGE -#define CONFIG_SYS_I2C_INIT_BOARD - /* Support the IVM EEprom */ #define CONFIG_SYS_IVM_EEPROM_ADR 0x50 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400 @@ -79,8 +75,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* UBI Support for all Keymile boards */ #define CONFIG_CMD_UBI #define CONFIG_RBTREE @@ -105,11 +99,16 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ +#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS +#define CONFIG_KM_UBI_PART_BOOT_OPTS "" +#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ + #ifndef CONFIG_KM_UBI_PARTITION_NAME_APP /* one flash chip only called boot */ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" #else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ @@ -117,7 +116,8 @@ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ /* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS " " \ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=if test ${boot_bank} -eq 0; then; " \ @@ -141,8 +141,8 @@ * - 'release': for a standalone system kernel/rootfs from flash */ #define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \ - "flashargs add_default addpanic boot\0" \ + "subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh " \ + "cramfsloadkernel flashargs add_default addpanic boot\0"\ "develop=" \ "tftp 200000 scripts/develop-${arch}.txt && " \ "env import -t 200000 ${filesize} && " \ @@ -166,7 +166,7 @@ "add_default=" \ "setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off3" \ + ":${hostname}:${netdev}:off:" \ " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \ " mem=${kernelmem} init=${init}" \ CONFIG_KM_ECC_MODE \ @@ -226,6 +226,7 @@ CONFIG_KM_DEF_ENV_FLASH_BOOT \ CONFIG_KM_DEF_ENV_CONSTANTS \ "altbootcmd=run bootcmd\0" \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ "bootcmd=km_checkbidhwk && " \ "setenv bootcmd \'if km_checktestboot; then; " \ "setenv boot_bank ${test_bank}; else; " \ @@ -235,6 +236,10 @@ "run ${subbootcmds}; reset\' && " \ "saveenv && saveenv && boot\0" \ "bootlimit=3\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0" \ "init=/sbin/init-overlay.sh\0" \ "load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 7ceb5e7eda..eb85a74919 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -2,7 +2,7 @@ * (C) Copyright 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_KEYMILE_POWERPC_H @@ -17,6 +17,9 @@ #define CONFIG_CMD_DTT #define CONFIG_JFFS2_CMDLINE +/* standard km ethernet_present for piggy */ +#define CONFIG_KM_COMMON_ETH_INIT + /* EEprom support 24C08, 24C16, 24C64 */ #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE @@ -32,6 +35,9 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +/* Reserve 4 MB for malloc */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + /****************************************************************************** * (PRAM usage) * ... ------------------------------------------------------- @@ -53,8 +59,9 @@ #define CONFIG_KM_PHRAM 0x100000 /* resereved pram area at the end of memroy [hex] */ #define CONFIG_KM_RESERVED_PRAM 0x0 -/* enable protected RAM */ -#define CONFIG_PRAM 0 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) #define CONFIG_KM_CRAMFS_ADDR 0x800000 #define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */ @@ -64,11 +71,6 @@ #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" #define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "update=" \ "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\ @@ -76,6 +78,7 @@ "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \ " ${filesize} && " \ "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\ + "set_fdthigh=true\0" \ "" #endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index 47355abed9..c8df23b534 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -15,7 +15,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ @@ -28,7 +27,7 @@ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* at end of uboot partition, before env */ -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000 +#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 /* * System IO Config diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 0ff866a896..940000ea71 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_KM83XX_H #define __CONFIG_KM83XX_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* include common defines/options for all Keymile boards */ #include "keymile-common.h" #include "km-powerpc.h" @@ -84,7 +87,6 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) @@ -223,7 +225,6 @@ #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ #define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 #define CONFIG_SYS_DTT_HYSTERESIS 3 #define CONFIG_SYS_DTT_BUS_NUM 1 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index e0368cb894..f780f8b5bb 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -20,6 +20,8 @@ #ifndef _CONFIG_KM_ARM_H #define _CONFIG_KM_ARM_H +#define CONFIG_SYS_GENERIC_BOARD + /* We got removed from Linux mach-types.h */ #define MACH_TYPE_KM_KIRKWOOD 2255 @@ -28,7 +30,6 @@ */ #define CONFIG_MARVELL #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ #define CONFIG_MACH_KM_KIRKWOOD /* Machine type */ @@ -54,6 +55,9 @@ #define CONFIG_ENV_SPI_MODE SPI_MODE_3 #endif +/* Reserve 4 MB for malloc */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + #include "asm/arch/config.h" #define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */ @@ -67,7 +71,8 @@ #define CONFIG_KM_PHRAM 0x17F000 #define CONFIG_KM_CRAMFS_ADDR 0x2400000 -#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ +#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */ +#define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */ /* architecture specific default bootargs */ #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ @@ -75,15 +80,17 @@ " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}" #define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - -\0" \ - "cramfsloadfdt=true\0" \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ CONFIG_KM_UPDATE_UBOOT \ + "set_fdthigh=setenv fdt_high ${kernelmem}\0" \ "" #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_MISC_INIT_R +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT + /* * NS16550 Configuration */ @@ -161,6 +168,7 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */ /* * UBI related stuff @@ -173,10 +181,9 @@ #undef CONFIG_I2C_MVTWSI #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ -#if defined(CONFIG_SYS_I2C_SOFT) - #define CONFIG_SYS_NUM_I2C_BUSES 6 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ @@ -211,7 +218,6 @@ int get_scl(void); #define CONFIG_SYS_I2C_SOFT_SLAVE 0x0 #define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#endif /* EEprom support 24C128, 24C256 valid for environment eeprom */ #define CONFIG_SYS_I2C_MULTI_EEPROMS @@ -287,10 +293,15 @@ int get_scl(void); " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" #endif +#ifndef CONFIG_KM_BOARD_EXTRA_ENV +#define CONFIG_KM_BOARD_EXTRA_ENV "" +#endif + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_BOARD_EXTRA_ENV \ CONFIG_KM_DEF_ENV \ CONFIG_KM_NEW_ENV \ "arch=arm\0" \ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h new file mode 100644 index 0000000000..949b3dadb3 --- /dev/null +++ b/include/configs/km/kmp204x-common.h @@ -0,0 +1,492 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_KMP204X_H +#define _CONFIG_KMP204X_H + +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P2041 + +#define CONFIG_SYS_TEXT_BASE 0xfff40000 + +#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" + +/* an additionnal option is required for UBI as subpage access is + * supported in u-boot */ +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" + +#define CONFIG_NAND_ECC_BCH + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + +/* common KM defines */ +#include "keymile-common.h" + +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_DPAA_RMAN /* RMan */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +/* Environment in SPI Flash */ +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 20000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ +#define CONFIG_ENV_SIZE 0x004000 /* 16K env */ +#define CONFIG_ENV_SECT_SIZE 0x010000 +#define CONFIG_ENV_OFFSET_REDUND 0x110000 +#define CONFIG_ENV_TOTAL_SIZE 0x020000 + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(unsigned long dummy); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 +#define CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* pseudo-non volatile RAM [hex] */ +#define CONFIG_KM_PNVRAM 0x80000 +/* physical RAM MTD size [hex] */ +#define CONFIG_KM_PHRAM 0x100000 +/* reserved pram area at the end of memory [hex] + * u-boot reserves some memory for the MP boot page */ +#define CONFIG_KM_RESERVED_PRAM 0x1000 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) + +#define CONFIG_KM_CRAMFS_ADDR 0x2000000 +#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ +#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ + +/* + * Local Bus Definitions + */ + +/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) + +/* Nand Flash */ +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_BCH + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ + | OR_FCM_BCTLD /* LBCTL not ass */ \ + | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ + | OR_FCM_RST /* 1 clk read setup */ \ + | OR_FCM_PGS /* Large page size */ \ + | OR_FCM_CST) /* 0.25 command setup */ + +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ + +/* QRIO FPGA */ +#define CONFIG_SYS_QRIO_BASE 0xfb000000 +#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull + +#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ + | BR_PS_8 /* Port Size 8 bits */ \ + | BR_DECC_OFF /* no error corr */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ + | OR_GPCM_BCTLD /* no LCTL assert */ \ + | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ + | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ + | OR_GPCM_TRLX /* relaxed tmgs */ \ + | OR_GPCM_EAD) /* extra bus clk cycles */ + +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ + +/* bootcounter in QRIO */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_LAST_STAGE_INIT + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ +#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ + } +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif + +#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +/* Default address of microcode for the Linux Fman driver + * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) + * ucode is stored after env, so we got 0x120000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x120000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ + +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION + +/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_PHYLIB /* recommended PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC5" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Hardware Watchdog + */ +#define CONFIG_WATCHDOG /* enable CPU watchdog */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ + + +/* + * additionnal command line configuration. + */ +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#define CONFIG_CMD_ERRATA + +/* we don't need flash support */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH +#undef CONFIG_FLASH_CFI_MTD +#undef CONFIG_JFFS2_CMDLINE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +#define __USB_PHY_TYPE utmi + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef MTDIDS_DEFAULT +# define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" +#endif /* MTDIDS_DEFAULT */ + +#ifndef MTDPARTS_DEFAULT +# define MTDPARTS_DEFAULT "mtdparts=" \ + "fsl_elbc_nand:" \ + "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" +#endif /* MTDPARTS_DEFAULT */ + +/* architecture specific default bootargs */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" + +/* FIXME: FDT_ADDR is unspecified */ +#define CONFIG_KM_DEF_ENV_CPU \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ + "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ + "update=" \ + "sf probe 0;sf erase 0 +${filesize};" \ + "sf write ${load_addr_r} 0 ${filesize};\0" \ + "set_fdthigh=true\0" \ + "" + +#define CONFIG_HW_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ + "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" + +#define CONFIG_KM_NEW_ENV \ + "newenv=sf probe 0;" \ + "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ + __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" + +/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + CONFIG_KM_NEW_ENV \ + CONFIG_HW_ENV_SETTINGS \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +#endif /* _CONFIG_KMP204X_H */ diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h index b23cb96274..14fd290be1 100644 --- a/include/configs/km82xx.h +++ b/include/configs/km82xx.h @@ -2,7 +2,7 @@ * (C) Copyright 2007-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -29,6 +29,9 @@ #error ("Board unsupported") #endif +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_SYS_TEXT_BASE 0xFE000000 /* include common defines/options for all Keymile boards */ @@ -204,9 +207,6 @@ "" #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif #define CONFIG_SYS_MONITOR_LEN (768 << 10) @@ -227,6 +227,7 @@ /* enable I2C and select the hardware/software driver */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_NUM_I2C_BUSES 3 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 @@ -237,6 +238,7 @@ {0, {{I2C_MUX_PCA9542, 0x70, 1} } } } #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_I2C_ABORT /* * Software (bit-bang) I2C driver configuration @@ -271,7 +273,6 @@ int get_scl(void); #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ #define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 #define CONFIG_SYS_DTT_HYSTERESIS 3 #define CONFIG_SYS_DTT_BUS_NUM 2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 0e6073c642..dc2615533c 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -34,15 +34,33 @@ #define CONFIG_HOSTNAME km_kirkwood_pci #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #define CONFIG_KM_FPGA_CONFIG +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE -/* KM_NUSA */ -#elif defined(CONFIG_KM_NUSA) +/* KM_KIRKWOOD_128M16 */ +#elif defined(CONFIG_KM_KIRKWOOD_128M16) +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood 128M16" +#define CONFIG_HOSTNAME km_kirkwood_128m16 +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_KM_DISABLE_PCIE #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ + +/* KM_NUSA / KM_SUGP1 */ +#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1) +#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ + +# if defined(CONFIG_KM_NUSA) #define CONFIG_IDENT_STRING "\nKeymile NUSA" #define CONFIG_HOSTNAME kmnusa +# elif defined(CONFIG_KM_SUGP1) +#define CONFIG_IDENT_STRING "\nKeymile SUGP1" +#define CONFIG_HOSTNAME kmsugp1 +#define KM_PCIE_RESET_MPP7 +#endif + #undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG \ - $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352 @@ -55,8 +73,7 @@ #define CONFIG_HOSTNAME mgcoge3un #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG \ - $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg #define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 #define CONFIG_KM_DISABLE_PCIE @@ -67,8 +84,7 @@ #define CONFIG_IDENT_STRING "\nKeymile COGE5UN" #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG \ - $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 #define CONFIG_HOSTNAME kmcoge5un @@ -87,9 +103,12 @@ #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #define CONFIG_IDENT_STRING "\nKeymile SUV31" #define CONFIG_HOSTNAME kmsuv31 +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_KM_FPGA_CONFIG - +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE #else #error ("Board unsupported") #endif diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h new file mode 100644 index 0000000000..8bb3571691 --- /dev/null +++ b/include/configs/kmp204x.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* KMLION1 */ +#if defined(CONFIG_KMLION1) +#define CONFIG_HOSTNAME kmlion1 +#define CONFIG_KM_BOARD_NAME "kmlion1" + +/* KMCOGE4 */ +#elif defined(CONFIG_KMCOGE4) +#define CONFIG_HOSTNAME kmcoge4 +#define CONFIG_KM_BOARD_NAME "kmcoge4" + +#else +#error ("Board not supported") +#endif + +#define CONFIG_KMP204X + +#include "km/kmp204x-common.h" + +#if defined(CONFIG_KMLION1) +/* App1 Local bus */ +#define CONFIG_SYS_LBAPP1_BASE 0xD0000000 +#define CONFIG_SYS_LBAPP1_BASE_PHYS 0xFD0000000ull + +#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \ + | BR_PS_8 /* Port Size 8 bits */ \ + | BR_DECC_OFF /* no error corr */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ + | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \ + | OR_GPCM_CSNT /* LCS 1/4 clk before */ \ + | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ + | OR_GPCM_TRLX /* relaxed tmgs */ \ + | OR_GPCM_EAD) /* extra bus clk cycles */ +/* Local bus app1 Base Address */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM +/* Local bus app1 Options */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM +#endif + +/* App2 Local bus */ +#define CONFIG_SYS_LBAPP2_BASE 0xE0000000 +#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull + +#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \ + | BR_PS_8 /* Port Size 8 bits */ \ + | BR_DECC_OFF /* no error corr */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ + | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \ + | OR_GPCM_CSNT /* LCS 1/4 clk before */ \ + | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ + | OR_GPCM_TRLX /* relaxed tmgs */ \ + | OR_GPCM_EAD) /* extra bus clk cycles */ +/* Local bus app2 Base Address */ +#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM +/* Local bus app2 Options */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM + +#endif /* __CONFIG_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h new file mode 100644 index 0000000000..c14889ce30 --- /dev/null +++ b/include/configs/koelsch.h @@ -0,0 +1,106 @@ +/* + * include/configs/koelsch.h + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __KOELSCH_H +#define __KOELSCH_H + +#undef DEBUG +#define CONFIG_R8A7791 +#define CONFIG_RMOBILE_BOARD_STRING "Koelsch" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +/* STACK */ +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC +#endif + +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF0 +#define CONFIG_SCIF_USE_EXT_CLK + +/* FLASH */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SPI +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_SPANSION + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE + + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF*/ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF0 */ +#define CONFIG_SMSTP7_ENA 0x00200000 + +#endif /* __KOELSCH_H */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 7c7a305175..5494a6007d 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -22,7 +22,6 @@ * High Level Configuration Options */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 #ifdef CONFIG_KORAT_PERMANENT @@ -307,7 +306,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -324,8 +322,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ @@ -545,7 +541,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* Pass open firmware flat tree */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h new file mode 100644 index 0000000000..bf7833607a --- /dev/null +++ b/include/configs/ks2_evm.h @@ -0,0 +1,321 @@ +/* + * Common configuration header file for all Keystone II EVM platforms + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_KS2_EVM_H +#define __CONFIG_KS2_EVM_H + + +/* U-Boot Build Configuration */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ +#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_THUMB_BUILD + +/* SoC Configuration */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_TEXT_BASE 0x0c001000 +#define CONFIG_SPL_TARGET "u-boot-spi.gph" +#define CONFIG_SYS_DCACHE_OFF + +/* Memory Configuration */ +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ +#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ + GENERATED_GBL_DATA_SIZE) + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_PAD_TO 65536 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SPL_MAX_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) +#define CONFIG_SPL_STACK_SIZE (8 * 1024) +#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SPL_STACK_SIZE - 4) +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SPL_FRAMEWORK + +/* UART Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE +#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* SPI Configuration */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_DAVINCI_SPI +#define CONFIG_CMD_SPI +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SYS_SPI0 +#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE +#define CONFIG_SYS_SPI0_NUM_CS 4 +#define CONFIG_SYS_SPI1 +#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE +#define CONFIG_SYS_SPI1_NUM_CS 4 +#define CONFIG_SYS_SPI2 +#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE +#define CONFIG_SYS_SPI2_NUM_CS 4 + +/* Network Configuration */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_MARVELL +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 32 +#define CONFIG_NET_MULTI +#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 +#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 +#define CONFIG_SYS_SGMII_RATESCALE 2 + +/* Keyston Navigator Configuration */ +#define CONFIG_TI_KSNAV +#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS +#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE +#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE +#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE +#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE +#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE +#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE +#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE +#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE +#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE +#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE +#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE +#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM +#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM + +/* NETCP pktdma */ +#define CONFIG_KSNAV_PKTDMA_NETCP +#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE +#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE +#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM +#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM +#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM +#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE +#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE +#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE + +/* Keystone net */ +#define CONFIG_DRIVER_TI_KEYSTONE_NET +#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR +#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE +#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE +#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES + +/* SerDes */ +#define CONFIG_TI_KEYSTONE_SERDES + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + +/* I2C Configuration */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ +#define I2C_BUS_MAX 3 + +/* EEPROM definitions */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_ENV_EEPROM_IS_ON_I2C + +/* NAND Configuration */ +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST + +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define MTDIDS_DEFAULT "nand0=davinci_nand.0" +#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro," \ + "-(ubifs)" + +/* USB Configuration */ +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_KEYSTONE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_FS_FAT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE +#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE +#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE +#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE + +/* U-Boot command configuration */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_SF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC + +/* U-Boot general configuration */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE 2048 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_TIMESTAMP + +/* EDMA3 */ +#define CONFIG_TI_EDMA3 + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "boot=ubi\0" \ + "tftp_root=/\0" \ + "nfs_root=/export\0" \ + "mem_lpae=1\0" \ + "mem_reserve=512M\0" \ + "addr_fdt=0x87000000\0" \ + "addr_kern=0x88000000\0" \ + "addr_uboot=0x87000000\0" \ + "addr_fs=0x82000000\0" \ + "addr_ubi=0x82000000\0" \ + "addr_secdb_key=0xc000000\0" \ + "fdt_high=0xffffffff\0" \ + "name_kern=uImage-keystone-evm.bin\0" \ + "run_mon=mon_install ${addr_mon}\0" \ + "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ + "init_net=run args_all args_net\0" \ + "init_ubi=run args_all args_ubi; " \ + "ubi part ubifs; ubifsmount ubi:boot;" \ + "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ + "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ + "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ + "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ + "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ + "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ + "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ + "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ + "sf write ${addr_uboot} 0 ${filesize}\0" \ + "burn_uboot_nand=nand erase 0 0x100000; " \ + "nand write ${addr_uboot} 0 ${filesize}\0" \ + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ + "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ + "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ + "${nfs_options} ip=dhcp\0" \ + "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ + "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ + "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ + "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \ + "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ + "burn_ubi=nand erase.part ubifs; " \ + "nand write ${addr_ubi} ubifs ${filesize}\0" \ + "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ + "args_ramfs=setenv bootargs ${bootargs} " \ + "rdinit=/sbin/init rw root=/dev/ram0 " \ + "initrd=0x802000000,9M\0" \ + "no_post=1\0" \ + "mtdparts=mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" + +#define CONFIG_BOOTCOMMAND \ + "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ + "get_kern_${boot} run_mon run_kern" + +#define CONFIG_BOOTARGS \ + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_SYS_BARGSIZE 1024 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) +#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) + +#define CONFIG_SUPPORT_RAW_INITRD + +/* we may include files below only after all above definitions */ +#include +#include +#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) + +#endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h deleted file mode 100644 index 5485a42fcc..0000000000 --- a/include/configs/kvme080.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2005 - * Sangmoon Kim, dogoil@etinsys.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_KVME080 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_IPADDR 192.168.0.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.0.1 - -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 " \ - "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \ - "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \ - "kvme080:eth0:none " \ - "mtdparts=phys_mapped_flash:12m(root),-(kernel)" - -#define CONFIG_BOOTCOMMAND \ - "tftp 800000 kvme080/uImage; " \ - "bootm 800000" - -#define CONFIG_LOADADDR 800000 - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_MISC_INIT_R - -#define CONFIG_LOADS_ECHO 1 -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#undef CONFIG_WATCHDOG - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_DS164x - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x07C00000 - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x7C000000 -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFF000000 -#define CONFIG_SYS_NS16550_COM1 0xFF080000 -#define CONFIG_SYS_NS16550_COM2 0xFF080010 -#define CONFIG_SYS_NS16550_COM3 0xFF080020 -#define CONFIG_SYS_NS16550_COM4 0xFF080030 -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 -#define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024) -#define CONFIG_SYS_NVRAM_SIZE 0x7FFF8 - -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_SYS_MONITOR_LEN 0x00040000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_PROTECT_CLEAR - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 - -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE -#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR -#define CONFIG_ENV_SIZE 0x400 -#define CONFIG_ENV_OFFSET 0 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 14745600 - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP - -#define CONFIG_EEPRO100 -#define CONFIG_EEPRO100_SROM_WRITE - -#define CONFIG_SYS_RX_ETH_BUFFER 8 - -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_CLK_FREQ 33333333 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_SYS_DLL_EXTEND 0x00 -#define CONFIG_SYS_PCI_HOLD_DEL 0x20 - -#define CONFIG_SYS_ROMNAL 15 -#define CONFIG_SYS_ROMFAL 31 - -#define CONFIG_SYS_REFINT 430 - -#define CONFIG_SYS_DBUS_SIZE2 1 - -#define CONFIG_SYS_BSTOPRE 121 -#define CONFIG_SYS_REFREC 8 -#define CONFIG_SYS_RDLAT 4 -#define CONFIG_SYS_PRETOACT 3 -#define CONFIG_SYS_ACTTOPRE 5 -#define CONFIG_SYS_ACTORW 3 -#define CONFIG_SYS_SDMODE_CAS_LAT 3 -#define CONFIG_SYS_SDMODE_WRAP 0 - -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (0x4000000 - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x04000000 -#define CONFIG_SYS_BANK1_END (0x8000000 - 1) -#define CONFIG_SYS_BANK1_ENABLE 1 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_BANK_ENABLE 0x03 - -#define CONFIG_SYS_ODCR 0x75 -#define CONFIG_SYS_PGMAX 0x32 - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#endif /* __CONFIG_H */ diff --git a/include/configs/kwb.h b/include/configs/kwb.h new file mode 100644 index 0000000000..29b263f301 --- /dev/null +++ b/include/configs/kwb.h @@ -0,0 +1,127 @@ +/* + * kwb.h + * + * specific parts for B&R KWB Motherboard + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_KWB_H__ +#define __CONFIG_KWB_H__ + +#include +/* ------------------------------------------------------------------------- */ +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65217 + +#define CONFIG_MACH_TYPE 3589 +/* I2C IP block */ +#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000 + +/* GPIO */ +#define CONFIG_SPL_GPIO_SUPPORT + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_SUPPORT_EMMC_BOOT +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SPL_MMC_SUPPORT + +#undef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +#endif /* CONFIG_SPL_OS_BOOT */ + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x80100000\0" \ + "bootfile=arimg\0" \ + "usbboot=echo Booting from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 ${loadaddr} ${bootfile}; " \ + "usb stop; " \ + "go ${loadaddr};\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload 0; " \ + "dhcp; " \ + "tftp ${loadaddr} arimg; " \ + "go ${loadaddr}\0" \ + "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 0x80000000 updateubootusb.img; " \ + "source;\0" \ + "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp;" \ + "tftp 0x80000000 updateUBOOT.img;" \ + "source;\0" +#endif /* !CONFIG_SPL_BUILD*/ + +#define CONFIG_BOOTCOMMAND \ + "run usbupdate;" +#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */ + +/* undefine command which we not need here */ +#undef CONFIG_BOOTM_LINUX +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS +#undef CONFIG_GZIP +#undef CONFIG_ZLIB + +/* USB configuration */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +/* attention! not only for gadget, enables also highspeed in hostmode */ +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif /* CONFIG_MUSB_HOST */ + +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC +#endif /* CONFIG_MMC, ... */ + +#endif /* ! __CONFIG_TSERIES_H__ */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 222725cd1f..ac74ae7fb3 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -10,11 +10,11 @@ #undef DEBUG -#define CONFIG_RMOBILE #define CONFIG_SH73A0 #define CONFIG_KZM_A9_GT #define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G +#define CONFIG_SYS_GENERIC_BOARD #include @@ -22,7 +22,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_L2_OFF #define CONFIG_OF_LIBFDT #include @@ -89,7 +88,6 @@ #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #define CONFIG_SYS_TEXT_BASE 0x00000000 @@ -125,9 +123,8 @@ #define CONFIG_GLOBAL_TIMER #define CONFIG_SYS_CLK_FREQ (48000000) #define CONFIG_SYS_CPU_CLK (1196000000) +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ -#define CFG_HZ (1000) -#define CONFIG_SYS_HZ CFG_HZ /* Ether */ #define CONFIG_NET_MULTI @@ -140,21 +137,22 @@ /* I2C */ #define CONFIG_CMD_I2C -#define CONFIG_SH_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 +#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 +#define CONFIG_SYS_I2C_SH_SPEED0 100000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 +#define CONFIG_SYS_I2C_SH_SPEED1 100000 +#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 +#define CONFIG_SYS_I2C_SH_SPEED2 100000 +#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 +#define CONFIG_SYS_I2C_SH_SPEED3 100000 +#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 +#define CONFIG_SYS_I2C_SH_SPEED4 100000 #define CONFIG_SH_I2C_8BIT -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (5) -#define CONFIG_SYS_I2C_MODULE -#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE (0x7F) -#define CONFIG_SH_I2C_DATA_HIGH (4) -#define CONFIG_SH_I2C_DATA_LOW (5) -#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ -#define CONFIG_SH_I2C_BASE0 (0xE6820000) -#define CONFIG_SH_I2C_BASE1 (0xE6822000) -#define CONFIG_SH_I2C_BASE2 (0xE6824000) -#define CONFIG_SH_I2C_BASE3 (0xE6826000) -#define CONFIG_SH_I2C_BASE4 (0xE6828000) +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ #endif /* __KZM9G_H */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index f6e79ba350..9ac5d3319e 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -41,7 +41,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SoC Family Name */ /* SoC name */ #if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) #define CONFIG_KW88F6192 @@ -80,9 +79,9 @@ * from the Network Space v2 */ #if defined(CONFIG_INETSPACE_V2) -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg #elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg #endif /* diff --git a/include/configs/lager.h b/include/configs/lager.h new file mode 100644 index 0000000000..291267f0f0 --- /dev/null +++ b/include/configs/lager.h @@ -0,0 +1,115 @@ +/* + * include/configs/lager.h + * This file is lager board configuration. + * + * Copyright (C) 2013, 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __LAGER_H +#define __LAGER_H + +#undef DEBUG +#define CONFIG_R8A7790 +#define CONFIG_RMOBILE_BOARD_STRING "Lager" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0xB0000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE8080000 +#endif + +/* STACK */ +#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF0 +#define CONFIG_SCIF_USE_EXT_CLK + +/* SPI */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_RCAR +#define CONFIG_SYS_RCAR_I2C0_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C1_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C2_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C3_SPEED 400000 +#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) +#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) +#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_USB_STORAGE + +/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC + +#define CONFIG_SH_MMCIF +#define CONFIG_SH_MMCIF_ADDR 0xEE220000 +#define CONFIG_SH_MMCIF_CLK 97500000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF0 */ +#define CONFIG_SMSTP7_ENA 0x00200000 + +#endif /* __LAGER_H */ diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h deleted file mode 100644 index 2ec776174c..0000000000 --- a/include/configs/linkstation.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Copyright (C) 2006 Mihai Georgian - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * - * Standard configuration - all models - * 0xFFF00000 boot from flash - * - * Test configuration (boot from RAM using uloader.o) - * LinkStation HD-HLAN and KuroBox Standard - * 0x03F00000 boot from RAM - * LinkStation HD-HGLAN and KuroBox HG - * 0x07F00000 boot from RAM - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#if 0 -#define DEBUG -#endif - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/*----------------------------------------------------------------------- - * User configurable settings: - * Mandatory settings: - * CONFIG_IPADDR_LS - the IP address of the LinkStation - * CONFIG_SERVERIP_LS - the address of the server for NFS/TFTP/DHCP/BOOTP - * Optional settins: - * CONFIG_NCIP_LS - the adress of the computer running net console - * if not configured, it will be set to - * CONFIG_SERVERIP_LS - */ - - -#define CONFIG_IPADDR_LS 192.168.11.150 -#define CONFIG_SERVERIP_LS 192.168.11.149 - -#if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS) -#error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined -#endif - -#if !defined(CONFIG_NCIP_LS) -#define CONFIG_NCIP_LS CONFIG_SERVERIP_LS -#endif - -/*---------------------------------------------------------------------- - * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING - *---------------------------------------------------------------------*/ - -#define CONFIG_MPC8245 1 -#define CONFIG_LINKSTATION 1 - -/*--------------------------------------- - * Supported models - * - * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN) - * LinkStation old model (CONFIG_LAN) - totally untested - * LinkStation HGLAN / KuroBox HG (CONFIG_HGLAN) - * - * Models not supported yet - * TeraStatin (CONFIG_HTGL) - */ - -#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) -#define CONFIG_IDENT_STRING " LinkStation / KuroBox" -#elif defined(CONFIG_HGLAN) -#define CONFIG_IDENT_STRING " LinkStation HG / KuroBox HG" -#elif defined(CONFIG_HTGL) -#define CONFIG_IDENT_STRING " TeraStation" -#else -#error No LinkStation model defined -#endif - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_ZERO_BOOTDELAY_CHECK -#undef CONFIG_BOOT_RETRY_TIME - -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Boot in %02d seconds ('s' to stop)...", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR "s" - -#define CONFIG_CMD_IDE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_EXT2 - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL - -#define CONFIG_OF_LIBFDT 1 - -#define OF_STDOUT_PATH "/soc10x/serial@80004600" - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */ - -#define CONFIG_BOOTCOMMAND "run bootcmd1" -#define CONFIG_BOOTARGS "root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug" -#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) -#define UBFILE "share/u-boot/u-boot-hd.flash.bin" -#elif defined(CONFIG_HGLAN) -#define UBFILE "share/u-boot/u-boot-hg.flash.bin" -#elif defined(CONFIG_HTGL) -#define UBFILE "share/u-boot/u-boot-ht.flash.bin" -#else -#error No LinkStation model defined -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "stdin=nc\0" \ - "stdout=nc\0" \ - "stderr=nc\0" \ - "ipaddr="__stringify(CONFIG_IPADDR_LS)"\0" \ - "netmask=255.255.255.0\0" \ - "serverip="__stringify(CONFIG_SERVERIP_LS)"\0" \ - "ncip="__stringify(CONFIG_NCIP_LS)"\0" \ - "netretry=no\0" \ - "nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \ - "ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \ - "ldaddr=800000\0" \ - "hdpart=0:1\0" \ - "hdfile=boot/uImage\0" \ - "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0" \ - "boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0" \ - "hdboot=run hdload;run boothd\0" \ - "flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \ - "emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ - "bootretry=30\0" \ - "bootcmd1=run hdboot;run flboot\0" \ - "bootcmd2=run flboot\0" \ - "bootcmd3=run emboot\0" \ - "writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \ - "writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \ - "ubpart=0:3\0" \ - "ubfile="UBFILE"\0" \ - "ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \ - "ubsaddr=fff00000\0" \ - "ubeaddr=fff2ffff\0" \ - "ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \ - "upgrade=run ubload ubflash\0" - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -/* Verified: CONFIG_PCI_PNP doesn't work */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW - -#ifndef CONFIG_PCI_PNP -/* Keep the following defines in sync with the BAT mappings */ - -#define PCI_ETH_IOADDR 0xbfff00 -#define PCI_ETH_MEMADDR 0xbffffc00 -#define PCI_IDE_IOADDR 0xbffed0 -#define PCI_IDE_MEMADDR 0xbffffb00 -#define PCI_USB0_IOADDR 0 -#define PCI_USB0_MEMADDR 0xbfffe000 -#define PCI_USB1_IOADDR 0 -#define PCI_USB1_MEMADDR 0xbfffd000 -#define PCI_USB2_IOADDR 0 -#define PCI_USB2_MEMADDR 0xbfffcf00 - -#endif - -/*----------------------------------------------------------------------- - * Ethernet stuff - */ - -#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) -#define CONFIG_TULIP -#define CONFIG_TULIP_USE_IO -#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) -#define CONFIG_RTL8169 -#endif - -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_NETCONSOLE - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 -#define CONFIG_SYS_EUMB_ADDR 0x80000000 -#define CONFIG_SYS_PCI_MEM_ADDR 0xB0000000 -#define CONFIG_SYS_MISC_REGION_ADDR 0xFE000000 - -#define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256 kB */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ - -/* Maximum amount of RAM */ -#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) -#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */ -#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) -#define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */ -#else -#error Unknown LinkStation type -#endif - -/*----------------------------------------------------------------------- - * Change CONFIG_SYS_TEXT_BASE in bord/linkstation/config.mk to get a RAM build - * - * RAM based builds are for testing purposes. A Linux module, uloader.o, - * exists to load U-Boot and pass control to it - * - * Always do "make clean" after changing the build type - */ -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#if 1 /* RAM is available when the first C function is called */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 0x1000) -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/*---------------------------------------------------------------------- - * Serial configuration - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 57600 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4600) /* Console port */ -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) /* AVR port */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8245 user's manual. - * - * Unless indicated otherwise, the values are - * taken from the orignal Linkstation boot code - * - * Most of the low level configuration setttings are normally used - * in arch/powerpc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation. - * Low level initialisation is done in board/linkstation/early_init.S - * The values below are included for reference purpose only - */ - -/* FIXME: 32.768 MHz is the crystal frequency but */ -/* the real frequency is lower by about 0.75% */ -#define CONFIG_SYS_CLK_FREQ 32768000 -#define CONFIG_SYS_HZ 1000 - -/* Bit-field values for MCCR1. */ -#define CONFIG_SYS_ROMNAL 0 -#define CONFIG_SYS_ROMFAL 11 - -#define CONFIG_SYS_BANK0_ROW 2 /* Only bank 0 used: 13 x n x 4 */ -#define CONFIG_SYS_BANK1_ROW 0 -#define CONFIG_SYS_BANK2_ROW 0 -#define CONFIG_SYS_BANK3_ROW 0 -#define CONFIG_SYS_BANK4_ROW 0 -#define CONFIG_SYS_BANK5_ROW 0 -#define CONFIG_SYS_BANK6_ROW 0 -#define CONFIG_SYS_BANK7_ROW 0 - -/* Bit-field values for MCCR2. */ -#define CONFIG_SYS_TSWAIT 0 -#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) -#define CONFIG_SYS_REFINT 0x15e0 -#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) -#define CONFIG_SYS_REFINT 0x1580 -#endif - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CONFIG_SYS_BSTOPRE 0x91c - -/* Bit-field values for MCCR3. */ -#define CONFIG_SYS_REFREC 7 - -/* Bit-field values for MCCR4. */ -#define CONFIG_SYS_PRETOACT 2 -#define CONFIG_SYS_ACTTOPRE 2 /* Original value was 2 */ -#define CONFIG_SYS_ACTORW 2 -#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* For 100MHz bus */ -/*#define CONFIG_SYS_SDMODE_BURSTLEN 3*/ -#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* For 133MHz bus */ -/*#define CONFIG_SYS_SDMODE_BURSTLEN 2*/ -#endif -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 /* Original setting but there is no EXTROM */ -#define CONFIG_SYS_REGDIMM 0 -#define CONFIG_SYS_DBUS_SIZE2 1 -#define CONFIG_SYS_SDMODE_WRAP 0 - -#define CONFIG_SYS_PGMAX 0x32 /* All boards use this setting. Original 0x92 */ -#define CONFIG_SYS_SDRAM_DSCD 0x30 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0x15 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITETHROUGH not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* EUMB: 1MB of address space */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT1L (CONFIG_SYS_IBAT1L | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI Mem: 256MB of address space */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_IBAT2L | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* PCI and local ROM/Flash: last 32MB of address space */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_IBAT3L | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - * - * FIXME: This doesn't appear to be true for the newer kernels - * which map more that 8 MB - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 72 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CONFIG_ENV_IS_IN_FLASH -/* - * The original LinkStation flash organisation uses - * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader - * We use the last sector of this area to store the environment - * which leaves max. 384 kB for the U-Boot itself - */ -#define CONFIG_ENV_ADDR 0xFFF60000 -#define CONFIG_ENV_SIZE 0x00010000 -#define CONFIG_ENV_SECT_SIZE 0x00010000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * IDE/ATA definitions - */ -#undef CONFIG_IDE_LED /* No IDE LED */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ -#define CONFIG_LBA48 /* 48 bit LBA supported */ - -#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN) -#define CONFIG_SYS_IDE_MAXBUS 1 /* Scan only 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* Only 1 drive per IDE bus */ -#elif defined(CONFIG_HGTL) -#define CONFIG_SYS_IDE_MAXBUS 2 /* Max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ -#else -#error Config IDE: Unknown LinkStation type -#endif - -#define CONFIG_SYS_ATA_BASE_ADDR 0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0 /* Offset for normal registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Partitions and file system - */ -#define CONFIG_DOS_PARTITION - -#endif /* __CONFIG_H */ diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h index 6df6f2b464..a26937265a 100644 --- a/include/configs/lp8x4x.h +++ b/include/configs/lp8x4x.h @@ -20,18 +20,18 @@ #define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ - "bootm 80000;" + "bootm 80000 - 240000;" #define CONFIG_BOOTARGS \ - "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ - "init=/sbin/init rootfstype=ext3" + "console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ + "init=/sbin/init rootfstype=ext4 rootwait" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_LZMA /* LZMA compression support */ -#undef CONFIG_OF_LIBFDT +#define CONFIG_OF_LIBFDT /* * Serial Console Configuration @@ -93,7 +93,6 @@ */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -101,11 +100,10 @@ */ #define CONFIG_SYS_HUSH_PARSER 1 -#undef CONFIG_SYS_LONGHELP +#define CONFIG_SYS_LONGHELP #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " #endif #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE \ @@ -116,11 +114,6 @@ #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_AUTO_COMPLETE 1 -/* - * Clock Configuration - */ -#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ - /* * DRAM Map */ @@ -150,7 +143,7 @@ #define CONFIG_ENV_SECT_SIZE 0x40000 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER 1 @@ -190,7 +183,7 @@ #define CONFIG_SYS_GAFR1_L_VAL 0x999a955a #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402 +#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402 #define CONFIG_SYS_GAFR3_L_VAL 0x540a950c #define CONFIG_SYS_GAFR3_U_VAL 0x00001599 @@ -238,7 +231,6 @@ */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_BOARD_INIT #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h new file mode 100644 index 0000000000..dc3c6d2294 --- /dev/null +++ b/include/configs/ls1021aqds.h @@ -0,0 +1,636 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_SILENT_CONSOLE +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* + * Generic Timer Definitions + */ +#define GENERIC_TIMER_CLK 12500000 + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_QIXIS_I2C_ACCESS +#else +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#endif + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#define CONFIG_SYS_DDR_RAW_TIMING +#endif +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_HAS_SERDES + +#define CONFIG_FSL_CAAM /* Enable CAAM */ + +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) +#define CONFIG_U_QE +#endif + +/* + * IFC Definitions + */ +#ifndef CONFIG_QSPI_BOOT +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ + FTIM0_GPCM_TEADC(0xe) | \ + FTIM0_GPCM_TEAHC(0xe)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ + FTIM2_GPCM_TCH(0xe) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif + +/* + * Serial Port + */ +#ifdef CONFIG_LPUART +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif + +#define CONFIG_BAUDRATE 115200 + +/* + * I2C + */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC + +/* + * MMC + */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC + +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#endif + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +/* + * Video + */ +#define CONFIG_FSL_DCU_FB + +#ifdef CONFIG_FSL_DCU_FB +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 +#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#endif + +/* + * eTSEC + */ +#define CONFIG_TSEC_ENET + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_MII +#define CONFIG_MII_DEFAULT_TSEC 3 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 +#define TSEC3_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_REALTEK + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 + +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1b + +#ifdef CONFIG_FSL_SGMII_RISER +#define CONFIG_SYS_TBIPA_VALUE 8 +#endif + +#endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING + +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else +#define CONFIG_CMD_IMLS +#endif + +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + +#ifdef CONFIG_LPUART +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ + "fdt_high=0xcfffffff\0" \ + "initrd_high=0xcfffffff\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "fdt_high=0xcfffffff\0" \ + "initrd_high=0xcfffffff\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_ENV_EXISTS +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_CMD_BOOTZ + +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + +#endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h new file mode 100644 index 0000000000..24b1709ad9 --- /dev/null +++ b/include/configs/ls1021atwr.h @@ -0,0 +1,423 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* + * Generic Timer Definitions + */ +#define GENERIC_TIMER_CLK 12500000 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#endif + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_SYS_HAS_SERDES + +#define CONFIG_FSL_CAAM /* Enable CAAM */ + +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) +#define CONFIG_U_QE +#endif + +/* + * IFC Definitions + */ +#ifndef CONFIG_QSPI_BOOT +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWP(0x1c) | \ + FTIM2_NOR_TWPH(0x0e)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA +#endif + +/* CPLD */ + +#define CONFIG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 + +/* + * Serial Port + */ +#ifdef CONFIG_LPUART +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif + +#define CONFIG_BAUDRATE 115200 + +/* + * I2C + */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC + +/* EEPROM */ +#ifndef CONFIG_SD_BOOT +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#endif + +/* + * MMC + */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC + +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#endif + +/* + * Video + */ +#define CONFIG_FSL_DCU_FB + +#ifdef CONFIG_FSL_DCU_FB +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_FSL_DCU_SII9022A +#define CONFIG_SYS_I2C_DVI_BUS_NUM 1 +#define CONFIG_SYS_I2C_DVI_ADDR 0x39 +#endif + +/* + * eTSEC + */ +#define CONFIG_TSEC_ENET + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_MII +#define CONFIG_MII_DEFAULT_TSEC 1 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING + +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else +#define CONFIG_CMD_IMLS +#endif + +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_BOOTDELAY 3 + +#ifdef CONFIG_LPUART +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ + "initrd_high=0xcfffffff\0" \ + "fdt_high=0xcfffffff\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "initrd_high=0xcfffffff\0" \ + "fdt_high=0xcfffffff\0" +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_ENV_EXISTS +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_CMD_BOOTZ + +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + +#endif diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h new file mode 100644 index 0000000000..6fe032c9ff --- /dev/null +++ b/include/configs/ls2085a_common.h @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_COMMON_H +#define __LS2_COMMON_H + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LSCH3 +#define CONFIG_LS2085A +#define CONFIG_GICV3 + +/* Link Definitions */ +#define CONFIG_SYS_TEXT_BASE 0x30001000 + +#ifdef CONFIG_EMU +#define CONFIG_SYS_NO_FLASH +#endif + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#define CONFIG_IDENT_STRING " LS2085A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#define CONFIG_SYS_DDR_RAW_TIMING +#endif +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 + +/* + * SMP Definitinos + */ +#define CPU_RELEASE_ADDR secondary_boot_func + +#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS +#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL +/* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ +#define CONFIG_SYS_DP_DDR_BASE_PHY 0 +#define CONFIG_DP_DDR_CTRL 2 +#define CONFIG_DP_DDR_NUM_CTRLS 1 +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 12000000 /* 12MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 +#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 + +/* Serial Port */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* IFC */ +#define CONFIG_FSL_IFC +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* + * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC + * address 0. But this region is limited to 256MB. To accommodate bigger NOR + * flash and other devices, we will map CS0 to 0x580000000 after relocation. + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting + */ +#define CONFIG_SYS_FLASH_BASE 0x580000000ULL +#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +/* + * NOR Flash Timing Params + */ +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x1)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ + FTIM2_NOR_TCH(0x0) | \ + FTIM2_NOR_TWP(0x1)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#endif + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_BASE 0x520000000 +#define CONFIG_SYS_NAND_BASE_PHYS 0x20000000 + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* MC firmware */ +#define CONFIG_FSL_MC_ENET +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_FW_IN_NOR +#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL +/* TODO Actual FW length needs to be determined at runtime from FW header */ +#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DPL_IN_NOR +#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL +/* TODO Actual DPL max length needs to be confirmed with the MC FW team */ +#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000 + +/* Carve the MC private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size() +#endif + +/* Command line configuration */ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) +#define CONFIG_ARCH_EARLY_INIT_R + +/* Physical Memory Map */ +/* fixme: these need to be checked against the board */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_SYS_CLK_FREQ 133333333 + + +#define CONFIG_NR_DRAM_BANKS 3 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_DISPLAY_CPUINFO + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581200000\0" \ + "kernel_load=0x806f0000\0" \ + "kernel_size=0x1000000\0" \ + "console=ttyAMA0,38400n8\0" + +#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ + "earlyprintk=uart8250-8bit,0x21c0600" +#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load" +#define CONFIG_BOOTDELAY 1 + +/* Store environment at top of flash */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#ifndef __ASSEMBLY__ +unsigned long mc_get_dram_block_size(void); +#endif + +#endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h new file mode 100644 index 0000000000..487cd99c5d --- /dev/null +++ b/include/configs/ls2085a_emu.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_EMU_H +#define __LS2_EMU_H + +#include "ls2085a_common.h" + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ + +#endif /* __LS2_EMU_H */ diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h new file mode 100644 index 0000000000..0f40b787b4 --- /dev/null +++ b/include/configs/ls2085a_simu.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_SIMU_H +#define __LS2_SIMU_H + +#include "ls2085a_common.h" + +/* SMSC 91C111 ethernet configuration */ +#define CONFIG_SMC91111 +#define CONFIG_SMC91111_BASE (0x2210000) + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#endif /* __LS2_SIMU_H */ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 52d8377a1b..a14bfe3a85 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -8,17 +8,19 @@ #ifndef _CONFIG_LSXL_H #define _CONFIG_LSXL_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ #if defined(CONFIG_LSCHLV2) #define CONFIG_IDENT_STRING " LS-CHLv2" -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg #define CONFIG_MACH_TYPE 3006 #define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ #elif defined(CONFIG_LSXHL) #define CONFIG_IDENT_STRING " LS-XHL" -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg #define CONFIG_MACH_TYPE 2663 /* CONFIG_SYS_TCLK is 200000000 by default */ #else @@ -29,7 +31,6 @@ * General configuration options */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ @@ -37,6 +38,7 @@ #define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_RANDOM_MACADDR +#define CONFIG_LIB_RAND #define CONFIG_KIRKWOOD_GPIO #define CONFIG_OF_LIBFDT @@ -65,6 +67,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_CMD_USB +#define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION @@ -85,7 +88,6 @@ #undef CONFIG_SYS_PROMPT -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* @@ -109,20 +111,41 @@ #define CONFIG_LOADADDR 0x00800000 #define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2" + +#if defined(CONFIG_LSXHL) +#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" +#elif defined(CONFIG_LSCHLV2) +#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb" +#else +#error "Unsupported board" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootsource=hdd\0" \ + "bootsource=legacy\0" \ "hdpart=0:1\0" \ - "bootcmd_net=bootp 0x00100000 uImage " \ - "&& tftpboot 0x00800000 uInitrd " \ + "kernel_addr=0x00800000\0" \ + "ramdisk_addr=0x01000000\0" \ + "fdt_addr=0x01ff0000\0" \ + "bootcmd_legacy=ide reset " \ + "&& load ide ${hdpart} 0x00100000 /uImage.buffalo " \ + "&& load ide ${hdpart} 0x00800000 /initrd.buffalo " \ "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_net=bootp ${kernel_addr} uImage " \ + "&& tftpboot ${ramdisk_addr} uInitrd " \ + "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_hdd=ide reset " \ - "&& ext2load ide ${hdpart} 0x00100000 /uImage " \ - "&& ext2load ide ${hdpart} 0x00800000 /uInitrd " \ - "&& bootm 0x00100000 0x00800000\0" \ + "&& load ide ${hdpart} ${kernel_addr} /uImage " \ + "&& load ide ${hdpart} ${ramdisk_addr} /uInitrd " \ + "&& load ide ${hdpart} ${fdt_addr} " \ + "/" CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_usb=usb start " \ - "&& fatload usb 0:1 0x00100000 /uImage " \ - "&& fatload usb 0:1 0x00800000 /uInitrd " \ - "&& bootm 0x00100000 0x00800000\0" \ + "&& load usb 0:1 ${kernel_addr} /uImage " \ + "&& load usb 0:1 ${ramdisk_addr} /uInitrd " \ + "&& load usb 0:1 ${fdt_addr} " \ + "/" CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ "eraseenv=sf probe 0 " \ "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \ @@ -136,7 +159,7 @@ "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ "setenv ncip; setenv gatewayip; setenv ethact; " \ "setenv bootfile; setenv dnsip; " \ - "setenv bootsource hdd; run ser\0" \ + "setenv bootsource legacy; run ser\0" \ "restore_env=run standard_env; saveenv; reset\0" \ "ser=setenv stdin serial; setenv stdout serial; " \ "setenv stderr serial\0" \ @@ -161,6 +184,7 @@ #undef CONFIG_SYS_IDE_MAXDEVICE #define CONFIG_SYS_IDE_MAXDEVICE 1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_64BIT_LBA #endif #endif /* _CONFIG_LSXL_H */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 8ecdf8049d..15e4a7e5c8 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -3,7 +3,7 @@ * Stefan Roese, DENX Software Engineering, sr@denx.de. * John Otken, jotken@softadvances.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -17,7 +17,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_LUAN 1 /* Board is Luan */ #define CONFIG_440SP 1 /* Specific PPC440SP support */ -#define CONFIG_4xx 1 /* PPC4xx family */ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h deleted file mode 100644 index 08d633ba17..0000000000 --- a/include/configs/lubbock.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the LUBBOCK board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ -#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ -#define CONFIG_LCD 1 -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_SHARP_LM8V31 -#endif -#define CONFIG_MMC -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_TEXT_BASE 0x0 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x0C000000 - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ -#define CONFIG_CONS_INDEX 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_FAT - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 80000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG -#define CONFIG_TIMESTAMP - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#ifdef CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -#define FPGA_REGS_BASE_PHYSICAL 0x08000000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00008000 -#define CONFIG_SYS_GPSR1_VAL 0x00FC0382 -#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0x0060A800 -#define CONFIG_SYS_GPDR1_VAL 0x00FF0382 -#define CONFIG_SYS_GPDR2_VAL 0x0001C000 -#define CONFIG_SYS_GAFR0_L_VAL 0x98400000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00002950 -#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558 -#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA -#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 - -#define CONFIG_SYS_PSSR_VAL 0x20 - -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 -#define CONFIG_SYS_CKEN 0x0 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x23F223F2 -#define CONFIG_SYS_MSC1_VAL 0x3FF1A441 -#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1 -#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 -#define CONFIG_SYS_MDREFR_VAL 0x00018018 -#define CONFIG_SYS_MDMRS_VAL 0x00000000 - -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 -#define LED_BLANK 0x08000040 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* NOTE: many default partitioning schemes assume the kernel starts at the - * second sector, not an environment. You have been warned! - */ -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) - - -/* - * FPGA Offsets - */ -#define WHOAMI_OFFSET 0x00 -#define HEXLED_OFFSET 0x10 -#define BLANKLED_OFFSET 0x40 -#define DISCRETELED_OFFSET 0x40 -#define CNFG_SWITCHES_OFFSET 0x50 -#define USER_SWITCHES_OFFSET 0x60 -#define MISC_WR_OFFSET 0x80 -#define MISC_RD_OFFSET 0x90 -#define INT_MASK_OFFSET 0xC0 -#define INT_CLEAR_OFFSET 0xD0 -#define GP_OFFSET 0x100 - -#endif /* __CONFIG_H */ diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h deleted file mode 100644 index 459c047b71..0000000000 --- a/include/configs/lwmon.h +++ /dev/null @@ -1,590 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* External logbuffer support */ -#define CONFIG_LOGBUFFER - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823E CPU */ -#define CONFIG_LWMON 1 /* ...on a LWMON board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* Default Ethernet MAC address */ -#define CONFIG_ETHADDR 00:11:B0:00:00:00 - -/* The default Ethernet MAC address can be overwritten just once */ -#ifdef CONFIG_ETHADDR -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#endif - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ - -#define CONFIG_LCD 1 /* use LCD controller ... */ -#define CONFIG_MPC8XX_LCD -#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ - -#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ -#define CONFIG_LCD_INFO 1 /* ... and some board info */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ - -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */ - -#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */ - -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -/* pre-boot commands */ -#define CONFIG_PREBOOT "setenv bootdelay 15" - -#undef CONFIG_BOOTARGS - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_WATCHDOG | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_SPI | \ - CONFIG_SYS_POST_USB | \ - CONFIG_SYS_POST_SPR | \ - CONFIG_SYS_POST_SYSMON) - -/* - * Keyboard commands: - * # = 0x28 = ENTER : enable bootmessages on LCD - * 2 = 0x3A+0x3C = F1 + F3 : enable update mode - * 3 = 0x3C+0x3F = F3 + F6 : enable test mode - */ - -#define CONFIG_BOOTCOMMAND "source 40040000;saveenv" - -/* "gatewayip=10.8.211.250\0" \ */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40280000\0" \ - "netmask=255.255.192.0\0" \ - "serverip=10.8.2.101\0" \ - "ipaddr=10.8.57.0\0" \ - "magic_keys=#23\0" \ - "key_magic#=28\0" \ - "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \ - "key_magic2=3A+3C\0" \ - "key_cmd2=echo *** Entering Update Mode ***;" \ - "if fatload ide 0:3 10000 update.scr;" \ - "then source 10000;" \ - "else echo *** UPDATE FAILED ***;" \ - "fi\0" \ - "key_magic3=3C+3F\0" \ - "key_cmd3=echo *** Entering Test Mode ***;" \ - "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ - "panic=1\0" \ - "add_wdt=setenv bootargs $bootargs $wdt_args\0" \ - "add_misc=setenv bootargs $bootargs runmode\0" \ - "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip add_wdt addfb add_misc;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \ - "run nfsargs addip add_wdt addfb;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "load=tftp 100000 /tftpboot/u-boot.bin\0" \ - "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \ - "wdt_args=wdt_8xx=off\0" \ - "verify=no" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ -#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 20) - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BMP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * When the watchdog is enabled, output must be fast enough in Linux. - */ -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 57600, 115200 } -#endif - -/*----------------------------------------------------------------------*/ -#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ -#undef CONFIG_MODEM_SUPPORT_DEBUG - -#define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */ -#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ -#if 0 -#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d sec...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ -#endif -/*----------------------------------------------------------------------*/ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) || defined(CONFIG_CMD_IDE) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */ -/* Buffer size. - We have two flash devices connected in parallel. - Each device incorporates a Write Buffer of 32 bytes. - */ -#define CONFIG_SYS_FLASH_BUFFER_SIZE (2*32) - -/* Put environment in flash which is much faster to boot than using the EEPROM */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x40040000 /* Address of Environment Sector */ -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */ - -/*----------------------------------------------------------------------- - * I2C/EEPROM Configuration - */ - -#define CONFIG_SYS_I2C_AUDIO_ADDR 0x28 /* Audio volume control */ -#define CONFIG_SYS_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ -#define CONFIG_SYS_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */ -#define CONFIG_SYS_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */ -#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ -#define CONFIG_SYS_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */ - -#undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */ - -#ifdef CONFIG_USE_FRAM /* use FRAM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#else /* use EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#endif /* CONFIG_USE_FRAM */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 - -/* List of I2C addresses to be verified by POST */ -#ifdef CONFIG_USE_FRAM -#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \ - CONFIG_SYS_I2C_SYSMON_ADDR, \ - CONFIG_SYS_I2C_RTC_ADDR, \ - CONFIG_SYS_I2C_POWER_A_ADDR, \ - CONFIG_SYS_I2C_POWER_B_ADDR, \ - CONFIG_SYS_I2C_KEYBD_ADDR, \ - CONFIG_SYS_I2C_PICIO_ADDR, \ - CONFIG_SYS_I2C_EEPROM_ADDR, \ - } -#else /* Use EEPROM - which show up on 8 consequtive addresses */ -#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \ - CONFIG_SYS_I2C_SYSMON_ADDR, \ - CONFIG_SYS_I2C_RTC_ADDR, \ - CONFIG_SYS_I2C_POWER_A_ADDR, \ - CONFIG_SYS_I2C_POWER_B_ADDR, \ - CONFIG_SYS_I2C_KEYBD_ADDR, \ - CONFIG_SYS_I2C_PICIO_ADDR, \ - CONFIG_SYS_I2C_EEPROM_ADDR+0, \ - CONFIG_SYS_I2C_EEPROM_ADDR+1, \ - CONFIG_SYS_I2C_EEPROM_ADDR+2, \ - CONFIG_SYS_I2C_EEPROM_ADDR+3, \ - CONFIG_SYS_I2C_EEPROM_ADDR+4, \ - CONFIG_SYS_I2C_EEPROM_ADDR+5, \ - CONFIG_SYS_I2C_EEPROM_ADDR+6, \ - CONFIG_SYS_I2C_EEPROM_ADDR+7, \ - } -#endif /* CONFIG_USE_FRAM */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* EARB, DBGC and DBPC are initialised by the HCW */ -/* => 0x000000C0 */ -#define CONFIG_SYS_SIUMCR (SIUMCR_GB5E) -/*#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00405000 */ -#define CONFIG_SYS_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */ -#define CONFIG_SYS_PLPRCR \ - ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ - ) - -#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*13200000) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800000 */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD100 | \ - SCCR_DFALCD01) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* 0x00C3 => 0x0003 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0x0000 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -#define CONFIG_SUPPORT_VFAT /* enable VFAT support */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - second Flash bank optional - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */ - -/* used to re-map FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0xFF000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ - -/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK) - -#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CONFIG_SYS_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) - -/* - * BR3/OR3: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */ -#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */ - -#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR5/OR5: Touch Panel - * - * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 - */ -#define TOUCHPNL_BASE 0x20000000 -#define TOUCHPNL_OR_AM 0xFFFF8000 -#define TOUCHPNL_TIMING OR_SCY_0_CLK - -#define CONFIG_SYS_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - TOUCHPNL_TIMING ) -#define CONFIG_SYS_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) - -#define CONFIG_SYS_MEMORY_75 -#undef CONFIG_SYS_MEMORY_7E -#undef CONFIG_SYS_MEMORY_8E - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MPTPR 0x200 - -/* - * MAMR settings for SDRAM - */ - -#define CONFIG_SYS_MAMR_8COL 0x80802114 -#define CONFIG_SYS_MAMR_9COL 0x80904114 - -/* - * MAR setting for SDRAM - */ -#define CONFIG_SYS_MAR 0x00000088 - -#endif /* __CONFIG_H */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 8f5eb956ae..d43db5288e 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -22,7 +22,6 @@ #define CONFIG_LWMON5 1 /* Board is lwmon5 */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifdef CONFIG_LCD4_LWMON5 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ @@ -463,7 +462,6 @@ #define CONFIG_SUPPORT_VFAT #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -482,8 +480,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ @@ -565,6 +561,7 @@ #define CONFIG_SYS_GPIO_PHY1_RST 12 #define CONFIG_SYS_GPIO_FLASH_WP 14 #define CONFIG_SYS_GPIO_PHY0_RST 22 +#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49 #define CONFIG_SYS_GPIO_DSPIC_READY 51 #define CONFIG_SYS_GPIO_CAN_ENABLE 53 #define CONFIG_SYS_GPIO_LSB_ENABLE 54 @@ -577,6 +574,13 @@ #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 #define CONFIG_SYS_GPIO_WATCHDOG 63 +/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */ +#ifdef CONFIG_LCD4_LWMON5 +#define GPIO49_VAL 0 +#else +#define GPIO49_VAL 1 +#endif + /* * PPC440 GPIO Configuration */ @@ -635,7 +639,7 @@ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ @@ -655,22 +659,18 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* * SPL related defines */ #ifdef CONFIG_LCD4_LWMON5 -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NOR_SUPPORT #define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */ #define CONFIG_SYS_SPL_MAX_LEN (64 << 10) #define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */ -#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx" -#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ #define CONFIG_SPL_SERIAL_SUPPORT diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index fd3ae028dc..c5e795f522 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -2,55 +2,36 @@ * Copyright (C) 2011 Marek Vasut * on behalf of DENX Software Engineering GmbH * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __M28EVK_CONFIG_H__ -#define __M28EVK_CONFIG_H__ +#ifndef __CONFIGS_M28EVK_H__ +#define __CONFIGS_M28EVK_H__ -/* - * SoC configurations - */ -#define CONFIG_MX28 /* i.MX28 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - -/* - * Define M28EVK machine type by hand until it lands in mach-types - */ +/* System configurations */ #define MACH_TYPE_M28EVK 3613 - #define CONFIG_MACH_TYPE MACH_TYPE_M28EVK -#include - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT +#define CONFIG_FIT -/* - * SPL - */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ -/* - * U-Boot Commands - */ +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BMP #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GPIO #define CONFIG_CMD_GREPENV #define CONFIG_CMD_I2C @@ -69,90 +50,22 @@ #define CONFIG_REGEX /* Enable regular expression support */ -/* - * Memory configurations - */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Serial Driver - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_MXS_MMC -#endif - -/* - * APBH DMA - */ -#define CONFIG_APBH_DMA -/* - * NAND - */ +/* Environment */ #define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_ENV_IS_IN_NAND /* Environment is in NAND */ -#define CONFIG_ENV_IS_IN_NAND +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (512 * 1024) -#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET (24 * CONFIG_ENV_SECT_SIZE) /* 3 MiB */ #define CONFIG_ENV_OFFSET_REDUND \ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) @@ -166,51 +79,32 @@ #define MTDIDS_DEFAULT "nand0=gpmi-nand" #define MTDPARTS_DEFAULT \ "mtdparts=gpmi-nand:" \ - "3m(bootloader)ro," \ - "512k(environment)," \ - "512k(redundant-environment)," \ - "4m(kernel)," \ - "128k(fdt)," \ - "8m(ramdisk)," \ - "-(filesystem)" + "3m(u-boot)," \ + "512k(env1)," \ + "512k(env2)," \ + "14m(boot)," \ + "238m(data)," \ + "-@4096k(UBI)" #else #define CONFIG_ENV_IS_NOWHERE #endif -/* - * Ethernet on SOC (FEC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_ETHPRIME "FEC0" +/* FEC Ethernet on SoC */ +#ifdef CONFIG_CMD_NET #define CONFIG_FEC_MXC -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII -#endif - -/* - * I2C - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MXS -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 #endif -/* - * EEPROM - */ -#ifdef CONFIG_CMD_EEPROM +/* EEPROM */ +#ifdef CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #endif -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE +/* RTC */ +#ifdef CONFIG_CMD_DATE /* Use the internal RTC in the MXS chip */ #define CONFIG_RTC_INTERNAL -#ifdef CONFIG_RTC_INTERNAL +#ifdef CONFIG_RTC_INTERNAL #define CONFIG_RTC_MXS #else #define CONFIG_RTC_M41T62 @@ -219,32 +113,22 @@ #endif #endif -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS +/* USB */ +#ifdef CONFIG_CMD_USB #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_EHCI_MXS_PORT1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif -/* - * SPI - */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_HARD_SPI -#define CONFIG_MXS_SPI -#define CONFIG_SPI_HALF_DUPLEX +/* SPI */ +#ifdef CONFIG_CMD_SPI #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_CS 0 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 /* SPI FLASH */ -#ifdef CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SF_DEFAULT_BUS 2 @@ -257,43 +141,45 @@ #define CONFIG_ENV_SPI_MAX_HZ 40000000 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 #endif + #endif -/* - * LCD - */ -#ifdef CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MXS +/* LCD */ +#ifdef CONFIG_VIDEO #define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) #endif -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS +/* Booting Linux */ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " -#define CONFIG_BOOTCOMMAND "run bootcmd_net" +#define CONFIG_BOOTCOMMAND "run mmc_mmc" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT -/* - * Extra Environments - */ +/* Extra Environment */ +#define CONFIG_PREBOOT "run try_bootscript" +#define CONFIG_HOSTNAME m28evk + #define CONFIG_EXTRA_ENV_SETTINGS \ + "consdev=ttyAMA0\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "bootdev=/dev/mmcblk0p2\0" \ + "rootdev=/dev/mmcblk0p3\0" \ + "netdev=eth0\0" \ + "hostname=m28evk\0" \ + "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \ + "kernel_addr_r=0x42000000\0" \ + "videomode=video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066," \ + "le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296," \ + "vmode:0\0" \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ "update_sd_firmware_filename=u-boot.sd\0" \ @@ -309,7 +195,7 @@ "if tftp ${update_nand_full_filename} ; then " \ "run update_nand_get_fcb_size ; " \ "nand scrub -y 0x0 ${filesize} ; " \ - "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ + "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ @@ -331,6 +217,78 @@ "setexpr fw_sz ${fw_sz} + 1 ; " \ "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ "fi ; " \ + "fi\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "adddfltmtd=" \ + "if test \"x${mtdparts}\" == \"x\" ; then " \ + "mtdparts default ; " \ + "fi\0" \ + "addmtd=" \ + "run adddfltmtd ; " \ + "setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addargs=run addcons addmtd addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ + "ubiload=" \ + "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ + "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "ubiargs=" \ + "setenv bootargs ubi.mtd=5 " \ + "root=ubi0:rootfs rootfstype=ubifs\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_ubi=" \ + "run mmcload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_mmc=" \ + "run ubiload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_ubi=" \ + "run ubiload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_nfs=" \ + "run ubiload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_ubi=" \ + "run netload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "try_bootscript=" \ + "mmc rescan;" \ + "if test -e mmc 0:2 ${bootscript} ; then " \ + "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ + "fi ; " \ "fi\0" -#endif /* __M28EVK_CONFIG_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_M28EVK_H__ */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index ccb07e3384..0f894e3fb2 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -2,15 +2,14 @@ * DENX M53 configuration * Copyright (C) 2012-2013 Marek Vasut * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __M53EVK_CONFIG_H__ #define __M53EVK_CONFIG_H__ -#define CONFIG_MX53 +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_MXC_GPIO -#define CONFIG_SYS_HZ 1000 #include @@ -19,17 +18,27 @@ #define CONFIG_REVISION_TAG #define CONFIG_SYS_NO_FLASH +#define CONFIG_FIT + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + /* * U-Boot Commands */ #include #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BMP #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_MMC @@ -37,20 +46,24 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_SATA +#define CONFIG_CMD_SETEXPR #define CONFIG_CMD_USB +#define CONFIG_VIDEO + +#define CONFIG_REGEX /* Enable regular expression support */ /* * Memory configurations */ #define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0xaff00000 +#define CONFIG_SYS_MEMTEST_END 0x8ff00000 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) @@ -67,7 +80,6 @@ * U-Boot general configurations */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) @@ -117,8 +129,8 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (512 * 1024) -#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */ #define CONFIG_ENV_OFFSET_REDUND \ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) @@ -129,16 +141,15 @@ #define CONFIG_LZO #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=mxc-nand" +#define MTDIDS_DEFAULT "nand0=mxc_nand" #define MTDPARTS_DEFAULT \ - "mtdparts=mxc-nand:" \ - "1m(bootloader)ro," \ - "512k(environment)," \ - "512k(redundant-environment)," \ - "4m(kernel)," \ - "128k(fdt)," \ - "8m(ramdisk)," \ - "-(filesystem)" + "mtdparts=mxc_nand:" \ + "1024k(u-boot)," \ + "512k(env1)," \ + "512k(env2)," \ + "14m(boot)," \ + "240m(data)," \ + "-@2048k(UBI)" #else #define CONFIG_ENV_IS_NOWHERE #endif @@ -155,16 +166,16 @@ #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL +#define CONFIG_ETHPRIME "FEC0" #endif /* * I2C */ #ifdef CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ #endif /* @@ -185,6 +196,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) @@ -203,6 +215,25 @@ #define CONFIG_LIBATA #endif +/* + * LCD + */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASHIMAGE_GUARD +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#define CONFIG_IPUV3_CLK 200000000 +#endif + /* * Boot Linux */ @@ -211,16 +242,16 @@ #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "m53evk/uImage" +#define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttymxc1,115200" #define CONFIG_LOADADDR 0x70800000 +#define CONFIG_BOOTCOMMAND "run mmc_mmc" #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_OF_LIBFDT /* * NAND SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" #define CONFIG_SPL_BOARD_INIT @@ -240,4 +271,89 @@ #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +/* + * Extra Environments + */ +#define CONFIG_PREBOOT "run try_bootscript" +#define CONFIG_HOSTNAME m53evk + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "consdev=ttymxc1\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "bootdev=/dev/mmcblk0p1\0" \ + "rootdev=/dev/mmcblk0p2\0" \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \ + "kernel_addr_r=0x72000000\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "adddfltmtd=" \ + "if test \"x${mtdparts}\" == \"x\" ; then " \ + "mtdparts default ; " \ + "fi\0" \ + "addmtd=" \ + "run adddfltmtd ; " \ + "setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addargs=run addcons addmtd addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ + "ubiload=" \ + "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ + "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "ubiargs=" \ + "setenv bootargs ubi.mtd=5 " \ + "root=ubi0:rootfs rootfstype=ubifs\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_ubi=" \ + "run mmcload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_mmc=" \ + "run ubiload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_ubi=" \ + "run ubiload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_nfs=" \ + "run ubiload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_ubi=" \ + "run netload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "try_bootscript=" \ + "mmc rescan;" \ + "if test -e mmc 0:1 ${bootscript} ; then " \ + "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ + "fi ; " \ + "fi\0" + #endif /* __M53EVK_CONFIG_H__ */ diff --git a/include/configs/magnesium.h b/include/configs/magnesium.h index d2da12fd06..3364bde71f 100644 --- a/include/configs/magnesium.h +++ b/include/configs/magnesium.h @@ -4,7 +4,7 @@ * based on: * Copyright (C) 2009 Ilya Yanok * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H diff --git a/include/configs/makalu.h b/include/configs/makalu.h index e7ed917f84..fd4c26eb94 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -5,7 +5,7 @@ * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -19,7 +19,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_MAKALU 1 /* Board is Makalu */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */ diff --git a/include/configs/malta.h b/include/configs/malta.h new file mode 100644 index 0000000000..354672ecf8 --- /dev/null +++ b/include/configs/malta.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MALTA_CONFIG_H +#define _MALTA_CONFIG_H + +#include +#include + +/* + * System configuration + */ +#define CONFIG_MALTA +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MEMSIZE_IN_BYTES + +#define CONFIG_PCI +#define CONFIG_PCI_GT64120 +#define CONFIG_PCI_MSC01 +#define CONFIG_PCI_PNP +#define CONFIG_PCNET +#define CONFIG_PCNET_79C973 +#define PCNET_HAS_PROM + +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 + +/* + * CPU Configuration + */ +#define CONFIG_SYS_MHZ 250 /* arbitrary value */ +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* + * Memory map + */ +#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ +#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80800000 + +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) + +/* + * Console configuration + */ +#if defined(CONFIG_SYS_LITTLE_ENDIAN) +#define CONFIG_SYS_PROMPT "maltael # " +#else +#define CONFIG_SYS_PROMPT "malta # " +#endif + +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +/* + * Serial driver + */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (115200 * 16) +#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE) +#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE) +#define CONFIG_CONS_INDEX 1 + +/* + * Flash configuration + */ +#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE) + +/* + * IDE/ATA + */ +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 + +/* + * Commands + */ +#include + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IDE +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */ + +#endif /* _MALTA_CONFIG_H */ diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h index c316599288..ab4a4710c7 100644 --- a/include/configs/manroland/common.h +++ b/include/configs/manroland/common.h @@ -2,7 +2,7 @@ * (C) Copyright 2009 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MANROLAND_COMMON_H @@ -99,7 +99,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index 29ea3043df..60e8716a79 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -2,7 +2,7 @@ * (C) Copyright 2009 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MANROLAND_MPC52XX__COMMON_H @@ -12,8 +12,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* MPC5200 CPU */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -143,8 +142,6 @@ /*use Hardware WDT */ #define CONFIG_HW_WATCHDOG -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if defined(CONFIG_CMD_KGDB) # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h new file mode 100644 index 0000000000..72217bdb57 --- /dev/null +++ b/include/configs/maxbcm.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_DB_MV7846MP_GP_H +#define _CONFIG_DB_MV7846MP_GP_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TEXT_BASE 0x04000000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_STMICRO + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define CONFIG_PHY_BASE_ADDR 0x0 +#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ +#define CONFIG_RESET_PHY_R + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h deleted file mode 100644 index 487574f6a7..0000000000 --- a/include/configs/mcc200.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MCC200 1 /* ... on MCC200 board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low (standard configuration) - * 0xFFF00000 boot high - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFC000000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - * - * To select console on the one of 8 external UARTs, - * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, - * or as 5, 6, 7, or 8 for the second Quad UART. - * COM11, COM12, COM13, COM14 are located on the second Quad UART. - * - * CONFIG_PSC_CONSOLE must be undefined in this case. - */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#ifdef CONFIG_CONSOLE_COM12 -#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ -#else -#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ -#endif -#else -/* PRS200 configuration: */ -#undef CONFIG_QUART_CONSOLE -#endif /* CONFIG_PRS200 */ -/* - * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 - * and undefine CONFIG_QUART_CONSOLE. - */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ -#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ -#else -/* PRS200 configuration: */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#endif -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_MII 1 - -#define CONFIG_DOS_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -/* automatic software updates (see board/mcc200/auto_update.c) */ -#define CONFIG_AUTO_UPDATE 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_USB - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#ifdef CONFIG_PRS200 -# define CONFIG_SYS__BOARDNAME "prs200" -# define CONFIG_SYS__LINUX_CONSOLE "ttyS0" -#else -# define CONFIG_SYS__BOARDNAME "mcc200" -# define CONFIG_SYS__LINUX_CONSOLE "ttyEU5" -#endif - -/* Network */ -#define CONFIG_ETHADDR 00:17:17:ff:00:00 -#define CONFIG_IPADDR 10.76.9.29 -#define CONFIG_SERVERIP 10.76.9.1 - -#include /* For U-Boot version */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubootver=" U_BOOT_VERSION "\0" \ - "netdev=eth0\0" \ - "hostname=" CONFIG_SYS__BOARDNAME "\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/mtdblock2 " \ - "rootfstype=cramfs\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate} " \ - "ubootver=${ubootver} board=${board}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "console=" CONFIG_SYS__LINUX_CONSOLE "\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \ - "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \ - "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "kernel_addr=0xFC0C0000\0" \ - "update=protect off ${text_base} +${filesize};" \ - "era ${text_base} +${filesize};" \ - "cp.b 200000 ${text_base} ${filesize}\0" \ - "unlock=yes\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -/* #define CONFIG_MPC5xxx_FEC 1 */ -/* #define CONFIG_MPC5xxx_FEC_MII100 */ -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 1 - -/* - * LCD Splash Screen - */ -#if !defined(CONFIG_PRS200) -#define CONFIG_LCD 1 -#define CONFIG_PROGRESSBAR 1 -#endif - -#if defined(CONFIG_LCD) -#define CONFIG_SPLASH_SCREEN 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define LCD_BPP LCD_MONOCHROME -#endif - -/* - * GPIO configuration - */ -/* 0x10000004 = 32MB SDRAM */ -/* 0x90000004 = 64MB SDRAM */ -#if defined(CONFIG_LCD) -/* set PSC2 in UART mode */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044 -#else -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004fb00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ -#define CONFIG_SYS_CS2_START 0x80000000 -#define CONFIG_SYS_CS2_SIZE 0x00001000 -#define CONFIG_SYS_CS2_CFG 0x1d300 - -/* Second Quad UART @0x80010000 */ -#define CONFIG_SYS_CS1_START 0x80010000 -#define CONFIG_SYS_CS1_SIZE 0x00001000 -#define CONFIG_SYS_CS1_CFG 0x1d300 - -/* Leica - build revision resistors */ -/* -#define CONFIG_SYS_CS3_START 0x80020000 -#define CONFIG_SYS_CS3_SIZE 0x00000004 -#define CONFIG_SYS_CS3_CFG 0x1d300 -*/ - -/* - * Select one of quarts as a default - * console. If undefined - PSC console - * wil be default - */ -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * QUART Expanders support - */ -#if defined(CONFIG_QUART_CONSOLE) -/* - * We'll use NS16550 chip routines, - */ -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_NS16550_SERIAL 1 -#define CONFIG_CONS_INDEX 1 -/* - * To achieve necessary offset on SC16C554 - * A0-A2 (register select) pins with NS16550 - * functions (in struct NS16550), REG_SIZE - * should be 4, because A0-A2 pins are connected - * to DA2-DA4 address bus lines. - */ -#define CONFIG_SYS_NS16550_REG_SIZE 4 -/* - * LocalPlus Bus already inited in cpu_init_f(), - * so can work with QUART's chip selects. - * One of four SC16C554 UARTs is selected with - * A3-A4 (DA5-DA6) lines. - */ -#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) -#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) -#else -#error "Wrong QUART expander number." -#endif - -/* - * SC16C554 chip's external crystal oscillator frequency - * is 7.3728 MHz - */ -#define CONFIG_SYS_NS16550_CLK 7372800 -#endif /* CONFIG_QUART_CONSOLE */ -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR "432" -#define CONFIG_SILENT_CONSOLE 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index c2b16316f1..26eb220354 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -13,9 +13,9 @@ * High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_MCX /* working with mcx */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define MACH_TYPE_MCX 3656 #define CONFIG_MACH_TYPE MACH_TYPE_MCX @@ -97,6 +97,7 @@ /* EHCI */ #define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_2 #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP @@ -136,10 +137,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* RTC */ #define CONFIG_RTC_DS1337 @@ -171,9 +172,6 @@ #define CONFIG_BOOTFILE "uImage" -#define xstr(s) str(s) -#define str(s) #s - /* Setup MTD for NAND on the SOM */ #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ @@ -200,13 +198,13 @@ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "baudrate=115200\0" \ "consoledev=ttyO2\0" \ - "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ "loadaddr=0x82000000\0" \ "load=tftp ${loadaddr} ${u-boot}\0" \ "load_k=tftp ${loadaddr} ${bootfile}\0" \ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ "loadmlo=tftp ${loadaddr} ${mlo}\0" \ - "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \ + "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ "mmcargs=root=/dev/mmcblk0p2 rw " \ "rootfstype=ext3 rootwait\0" \ "mmcboot=echo Booting from mmc ...; " \ @@ -220,7 +218,7 @@ "bootm ${loadaddr}\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \ + "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ "uboot_addr=0x80000\0" \ "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ "nand write ${loadaddr} ${uboot_addr} 80000\0" \ @@ -262,10 +260,9 @@ "${mtdparts} " \ "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ "omapdss.def_disp=lcd;" \ - "bootm 0x82000000 0x84000000\0" - -#define CONFIG_BOOTCOMMAND \ - "run nandboot" + "bootm 0x82000000 0x84000000\0" \ + "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ + "then source 82000000;else run nandboot;fi\0" #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING @@ -302,7 +299,6 @@ */ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* * Physical Memory Map @@ -316,12 +312,7 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ @@ -349,11 +340,9 @@ GENERATED_GBL_DATA_SIZE) /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT @@ -380,8 +369,8 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" /* NAND boot config */ #define CONFIG_SYS_NAND_PAGE_COUNT 64 @@ -395,6 +384,8 @@ 56, 57, 58, 59, 60, 61, 62, 63} #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW +#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE @@ -408,7 +399,6 @@ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_DRIVER_TI_EMAC_USE_RMII #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index b48872b267..0b9cbae5ba 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -15,6 +15,9 @@ #define __CONFIG_H #define CONFIG_MECP5123 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the MECP5123 board: * @@ -29,7 +32,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 @@ -327,7 +329,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -343,8 +344,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 - /* * For booting Linux, the board info and command line data * have to be in the first 256 MB of memory, since this is @@ -367,7 +366,6 @@ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h deleted file mode 100644 index 601bb79d1c..0000000000 --- a/include/configs/mecp5200.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -/************************************************************************* - * (c) 2005 esd gmbh Hannover - * - * - * from IceCube.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - *************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ -#define CONFIG_MECP5200 1 /* ... on MECP5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#if 0 /* test-only */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#else -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ -#endif -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_MII -#if 0 /* test-only !!! */ -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 0 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF - - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#endif -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to CBX-CPU5200 (mecp5200);" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ - "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \ - "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \ - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \ - "loadaddr=01000000\0" \ - "serverip=192.168.2.99\0" \ - "gatewayip=10.0.0.79\0" \ - "user=mu\0" \ - "target=mecp5200.esd\0" \ - "script=mecp5200.bat\0" \ - "image=/tftpboot/vxWorks_mecp5200\0" \ - "ipaddr=10.0.13.196\0" \ - "netmask=255.255.0.0\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_vxworks0" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#if 1 /* test-only */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 -#else -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/ - /* total size of a CAT24WC32 is 8192 bytes */ -#define CONFIG_ENV_OVERWRITE 1 -#endif - -#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#if 0 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#endif -#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ - - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_UDP_CHECKSUM 1 - - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00085d00 - -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS1_START 0xfd000000 -#define CONFIG_SYS_CS1_SIZE 0x00010000 -#define CONFIG_SYS_CS1_CFG 0x10101410 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index 40155c3796..ac5208fa0d 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -12,11 +12,6 @@ #include "tegra20-common.h" -/* Enable fdt support for Medcom-Wide. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-medcom-wide -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (Medcom-Wide) # " #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d2ec83cd1f..955d0e278a 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -40,7 +40,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq */ /* Misc CPU related */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -125,7 +124,6 @@ #ifdef CONFIG_SYS_USE_DATAFLASH # define CONFIG_ATMEL_DATAFLASH_SPI # define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) # define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ # define AT91_SPI_CLK 15000000 @@ -144,8 +142,8 @@ # define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -# define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 -# define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 +# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif /* Ethernet */ @@ -157,6 +155,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT @@ -190,7 +189,6 @@ #endif -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 0e3de777b2..bb07060002 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -12,14 +12,8 @@ #include "../board/xilinx/microblaze-generic/xparameters.h" /* MicroBlaze CPU */ -#define CONFIG_MICROBLAZE 1 #define MICROBLAZE_V5 1 -/* Open Firmware DTS */ -#define CONFIG_OF_CONTROL 1 -#define CONFIG_OF_EMBED 1 -#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic - /* linear and spi flash memory */ #ifdef XILINX_FLASH_START #define FLASH @@ -71,7 +65,7 @@ /* ethernet */ #undef CONFIG_SYS_ENET -#if defined(XILINX_EMACLITE_BASEADDR) +#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) # define CONFIG_XILINX_EMACLITE 1 # define CONFIG_SYS_ENET #endif @@ -200,7 +194,8 @@ # define CONFIG_SYS_MAX_FLASH_SECT 512 /* hardware flash protection */ # define CONFIG_SYS_FLASH_PROTECTION - +/* use buffered writes (20x faster) */ +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # ifdef RAMENV # define CONFIG_ENV_IS_NOWHERE 1 # define CONFIG_ENV_SIZE 0x1000 @@ -399,7 +394,6 @@ /* architecture dependent code */ #define CONFIG_SYS_USR_EXCEP /* user exception */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" @@ -447,4 +441,63 @@ # undef CONFIG_PHYLIB #endif +/* SPL part */ +#define CONFIG_CMD_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_NOR_SUPPORT + +/* for booting directly linux */ +#define CONFIG_SPL_OS_BOOT + +#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x60000) +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x40000) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ + 0x1000000) + +/* SP location before relocation, must use scratch RAM */ +/* BRAM start */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +/* BRAM size - will be generated */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100 + +/* + * The main reason to do it in this way is that MALLOC_START + * can't be defined - common/spl/spl.c + */ +#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0) +# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \ + CONFIG_SYS_SPL_MALLOC_SIZE) +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START +#else +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END +#endif + +/* Just for sure that there is a space for stack */ +#define CONFIG_SPL_STACK_SIZE 0x100 + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_INIT_RAM_ADDR - \ + GENERATED_GBL_DATA_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE - \ + CONFIG_SPL_STACK_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index 82f653ed5c..fc7ecfaee4 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -10,15 +10,12 @@ #include -#define CONFIG_AVR32 #define CONFIG_AT32AP #define CONFIG_AT32AP7000 #define CONFIG_MIMC200 #define CONFIG_MIMC200_EXT_FLASH -#define CONFIG_SYS_HZ 1000 - /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h deleted file mode 100644 index 5e9e98d2fc..0000000000 --- a/include/configs/mini2440.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Gary Jennejohn - * David Mueller - * - * (C) Copyright 2009-2010 - * Michel Pollet - * - * (C) Copyright 2012 - * Gabriel Huau - * - * Configuation settings for the MINI2440 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_S3C2440_GPIO - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM920T /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */ -#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */ -#define CONFIG_MINI2440 /* on a MIN2440 Board */ - -#define MACH_TYPE_MINI2440 1999 -#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 - -/* - * We don't use lowlevel_init - */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F - -/* - * input clock of PLL - */ -/* MINI2440 has 12.0000MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_DM9000 -#define CONFIG_DRIVER_DM9000_NO_EEPROM -#define CONFIG_DM9000_BASE 0x20000300 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+4) - -/* - * select serial console configuration - */ -#define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 - -/* - * allow to overwrite serial and ethaddr - */ -#define CONFIG_ENV_OVERWRITE - -/* - * Command definition - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES - -/* - * Miscellaneous configurable options - */ -#define CONFIG_LONGHELP -#define CONFIG_SYS_PROMPT "MINI2440 => " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x30000000 -#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x32000000 - -/* boot parameters address */ -#define CONFIG_BOOT_PARAM_ADDR 0x30000100 - -/* - * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need - * it to wrap 100 times (total 1562500) to get 1 sec. - */ -#define CONFIG_SYS_HZ 1562500 - -/* - * valid baudrates - */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BAUDRATE 115200 - -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 -#define CONFIG_SYS_FLASH_BASE 0x0 - -/* - * Stack should be on the SRAM because - * DRAM is not init - */ -#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) - -/* - * NOR FLASH organization - * Now uses the standard CFI interface - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_MONITOR_BASE 0x0 -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* 512 * 4096 sectors, or 32 * 64k blocks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_FLASH_SHOW_PROGRESS 1 - -/* - * Config for NOR flash - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_MY_ENV_OFFSET 0x40000 -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET) -/* 16k Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 - -/* ATAG configuration */ -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE - -#endif /* __CONFIG_H */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index d7383a62c6..e8b05932a1 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -4,7 +4,7 @@ * * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -15,8 +15,7 @@ */ /* CPU and board */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ +#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ @@ -368,7 +367,6 @@ extern void __led_set(led_id_t id, int state); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -380,8 +378,6 @@ extern void __led_set(led_id_t id, int state); #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default kernel load addr */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Various low-level settings */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 85ae3671f1..41ae0a53f8 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2007-2009 DENX Software Engineering * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -12,6 +12,9 @@ #define __CONFIG_H #define CONFIG_MPC5121ADS 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the MPC5121ADS board: * @@ -29,7 +32,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 @@ -486,7 +488,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -498,7 +499,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -522,7 +522,6 @@ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h deleted file mode 100644 index f8c46278ad..0000000000 --- a/include/configs/mpc7448hpc2.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Copyright (c) 2005 Freescale Semiconductor, Inc. - * - * (C) Copyright 2006 - * Alex Bounine , Tundra Semiconductor Corp. - * Roy Zang , Freescale Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board specific configuration options for Freescale - * MPC7448HPC2 (High-Performance Computing II) (Taiga) board - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board Configuration Definitions */ -/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */ - -#define CONFIG_MPC7448HPC2 - -#define CONFIG_74xx -#define CONFIG_HIGH_BATS /* High BATs supported */ -#define CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -#define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II" -#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" - -#define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */ -#define CONFIG_SYS_BUS_CLK 133000000 - -#define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ - -#undef CONFIG_ECC /* disable ECC support */ - -#ifndef __ASSEMBLY__ -#include -#endif - -/* Board-specific Initialization Functions to be called */ -#define CONFIG_SYS_BOARD_ASM_INIT -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_MISC_INIT_R - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -#define CONFIG_ENV_OVERWRITE - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TSI "tsi108@c0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * If you have hacked a serial cable onto the second DUART channel, - * change the CONFIG_SYS_DUART port from 1 to 0 below. - * - */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08) - -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -/* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ - setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ - ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" -#endif - -#undef CONFIG_EXTRA_ENV_SETTINGS - -#define CONFIG_SERIAL "No. 1" - -/* Networking Configuration */ - -#define CONFIG_TSI108_ETH -#define CONFIG_TSI108_ETH_NUM_PORTS 2 - - -#define CONFIG_BOOTFILE "zImage.initrd.elf" -#define CONFIG_LOADADDR 0x400000 - -/*-------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_DATE - - -/*set date in u-boot*/ -#define CONFIG_RTC_M48T35A -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 -#define CONFIG_SYS_NVRAM_SIZE 0x8000 -/* - * Miscellaneous configurable options - */ -#define CONFIG_VERSION_VARIABLE 1 -#define CONFIG_TSI108_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized - */ -#undef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000/* larger space - we have SDRAM initialized */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ - -#define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ -#define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ - -#define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ - -#define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ - -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */ -#define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ - -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ - -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0x3fffff00 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* u-boot code base */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* Peripheral Device section */ - -/* - * Resources on the Tsi108 - */ - -#define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ -#define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ - -#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ - -#undef DISABLE_PBM - -/* - * PCI stuff - * - */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_TSI108_PCI /* include tsi108 pci support */ - -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ - -/* PCI view of System Memory */ -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000 - -/* PCI Memory Space */ -#define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS) -#define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */ -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ - -/* PCI I/O Space */ -#define CONFIG_SYS_PCI_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ - -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */ - -/* PCI Config Space mapping */ -#define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ -#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */ - -#define CONFIG_SYS_IBAT0U 0xFE0003FF -#define CONFIG_SYS_IBAT0L 0xFE000002 - -#define CONFIG_SYS_IBAT1U 0x00007FFF -#define CONFIG_SYS_IBAT1L 0x00000012 - -#define CONFIG_SYS_IBAT2U 0x80007FFF -#define CONFIG_SYS_IBAT2L 0x80000022 - -#define CONFIG_SYS_IBAT3U 0x00000000 -#define CONFIG_SYS_IBAT3L 0x00000000 - -#define CONFIG_SYS_IBAT4U 0x00000000 -#define CONFIG_SYS_IBAT4L 0x00000000 - -#define CONFIG_SYS_IBAT5U 0x00000000 -#define CONFIG_SYS_IBAT5L 0x00000000 - -#define CONFIG_SYS_IBAT6U 0x00000000 -#define CONFIG_SYS_IBAT6L 0x00000000 - -#define CONFIG_SYS_IBAT7U 0x00000000 -#define CONFIG_SYS_IBAT7L 0x00000000 - -#define CONFIG_SYS_DBAT0U 0xE0003FFF -#define CONFIG_SYS_DBAT0L 0xE000002A - -#define CONFIG_SYS_DBAT1U 0x00007FFF -#define CONFIG_SYS_DBAT1L 0x00000012 - -#define CONFIG_SYS_DBAT2U 0x00000000 -#define CONFIG_SYS_DBAT2L 0x00000000 - -#define CONFIG_SYS_DBAT3U 0xC0000003 -#define CONFIG_SYS_DBAT3L 0xC000002A - -#define CONFIG_SYS_DBAT4U 0x00000000 -#define CONFIG_SYS_DBAT4L 0x00000000 - -#define CONFIG_SYS_DBAT5U 0x00000000 -#define CONFIG_SYS_DBAT5L 0x00000000 - -#define CONFIG_SYS_DBAT6U 0x00000000 -#define CONFIG_SYS_DBAT6L 0x00000000 - -#define CONFIG_SYS_DBAT7U 0x00000000 -#define CONFIG_SYS_DBAT7L 0x00000000 - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ } - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -#define PHYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_SECT (128) - -#define CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_ADDR 0xFC000000 - -#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ -#undef CONFIG_SYS_L2 - -#define L2_INIT 0 -#define L2_ENABLE (L2_INIT | L2CR_L2E) -#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION -#endif /* __CONFIG_H */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 6875cf4c5b..4ae9afd4e5 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ @@ -412,7 +411,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -421,7 +419,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h deleted file mode 100644 index 55d93da598..0000000000 --- a/include/configs/mpq101.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright 2011 Alex Dubov - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Merury Computers MPQ101 board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_36BIT -# define CONFIG_PHYS_64BIT -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ -#define CONFIG_MPC8548 /* MPC8548 specific */ -#define CONFIG_MPQ101 /* MPQ101 board specific */ - -#define CONFIG_SYS_SRIO /* enable serial RapidIO */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_PANIC_HANG - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_ADDR_MAP -# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - - -#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_FSL_DDR2 - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* Fixed 512MB DDR2 parameters */ -#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 -#define CONFIG_SYS_DDR_TIMING_3 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432 -#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322 -#define CONFIG_SYS_DDR_TIMING_2 0x03984cce -#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca -#define CONFIG_SYS_DDR_MODE_1 0x00400442 -#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x08200100 -#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100 -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x04400000 - -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0ffffffc - -/* - * RAM definitions - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ - - -/* - * FLASH on the Local Bus - * One bank, 128M, using the CFI driver. - */ -#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */ - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull -#else -# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -/* 0xf8001801 */ -#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_32 | BR_V) - -/* 0xf8006ff7 */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 | OR_GPCM_TRLX \ - | OR_GPCM_EHTR | OR_GPCM_EAD) - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash. - */ -#define CONFIG_ASSUME_AMD_FLASH - -/* - * Environment parameters - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_USE_PPCENV -#define ENV_IS_EMBEDDED -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ -#define CONFIG_ENV_SIZE 0x800 - -/* Environment at the start of flash sector, before text. */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_TEXT_BASE 0xfffc0800 -#define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds" - -/* - * Cypress CY7C67200 USB controller on the Local Bus. - * Not supported by u-boot at present. - */ -#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull -#else -# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE -#endif - -/* 0xf0001001 */ -#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \ - | BR_PS_16 | BR_V) - -/* fffff002 */ -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \ - | OR_GPCM_BCTLD | OR_GPCM_EHTR) - -/* - * Serial Ports - */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \ - 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C buses and peripherals - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* I2C RTC - M41T81 */ -#define CONFIG_RTC_M41T62 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 - -/* I2C EEPROM - 24C256 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 - -/* - * RapidIO MMU - */ -#ifdef CONFIG_SYS_SRIO -# define CONFIG_SRIO1 -# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 -# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ - -# ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull -# else -# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT -# endif -#endif - -/* - * Ethernet - */ -#ifdef CONFIG_TSEC_ENET - -# define CONFIG_MII /* MII PHY management */ -# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ - -# define CONFIG_TSEC1 -# define CONFIG_TSEC1_NAME "eTSEC0" -# define TSEC1_PHY_ADDR 0x10 -# define TSEC1_PHYIDX 0 -# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -# define CONFIG_TSEC2 -# define CONFIG_TSEC2_NAME "eTSEC1" -# define TSEC2_PHY_ADDR 0x11 -# define TSEC2_PHYIDX 0 -# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -# define CONFIG_TSEC3 -# define CONFIG_TSEC3_NAME "eTSEC2" -# define TSEC3_PHY_ADDR 0x12 -# define TSEC3_PHYIDX 0 -# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -# define CONFIG_TSEC4 -# define CONFIG_TSEC4_NAME "eTSEC3" -# define TSEC4_PHY_ADDR 0x13 -# define TSEC4_PHYIDX 0 -# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -/* Options are: eTSEC[0-3] */ -# define CONFIG_ETHPRIME "eTSEC0" -# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -#endif - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_JFFS2 - -/* - * Miscellaneous configurable options - */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -#define CONFIG_FIT /* new uImage format support */ -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ - -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */ - -/* Console I/O Buffer Size */ -#ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 -#else -# define CONFIG_SYS_CBSIZE 256 -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -# define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Basic Environment Configuration - */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ - -/*default location for tftp and bootm*/ -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#endif /* __CONFIG_H */ diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h index 7e18723723..8ae497c6d5 100644 --- a/include/configs/mpr2.h +++ b/include/configs/mpr2.h @@ -24,14 +24,11 @@ #define CONFIG_VERSION_VARIABLE /* CPU and platform */ -#define CONFIG_SH 1 -#define CONFIG_SH3 1 #define CONFIG_CPU_SH7720 1 #define CONFIG_MPR2 1 /* U-Boot internals */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -67,8 +64,9 @@ /* Clocks */ #define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ -#define CONFIG_SYS_HZ 1000 /* UART */ #define CONFIG_SCIF_CONSOLE 1 diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index bc8bb8d5a7..585d68f208 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -9,8 +9,6 @@ #ifndef __MS7720SE_H #define __MS7720SE_H -#define CONFIG_SH 1 -#define CONFIG_SH3 1 #define CONFIG_CPU_SH7720 1 #define CONFIG_MS7720SE 1 @@ -38,7 +36,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -85,8 +82,9 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ -#define CONFIG_SYS_HZ 1000 /* PCMCIA */ #define CONFIG_IDE_PCMCIA 1 diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index a757737f84..1c8ada6c03 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -9,8 +9,6 @@ #ifndef __MS7722SE_H #define __MS7722SE_H -#define CONFIG_SH 1 -#define CONFIG_SH4 1 #define CONFIG_CPU_SH7722 1 #define CONFIG_MS7722SE 1 @@ -41,7 +39,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -111,7 +108,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ -#define CONFIG_SYS_HZ 1000 #endif /* __MS7722SE_H */ diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index c4c96bfb2d..4cf8efeca0 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -9,8 +9,6 @@ #ifndef __MS7750SE_H #define __MS7750SE_H -#define CONFIG_SH 1 -#define CONFIG_SH4 1 #define CONFIG_CPU_SH7750 1 /* #define CONFIG_CPU_SH7751 1 */ /* #define CONFIG_CPU_TYPE_R 1 */ @@ -39,7 +37,6 @@ #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_MAXARGS 16 @@ -82,7 +79,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __MS7750SE_H */ diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index e7afd07b94..01e395a49d 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -49,6 +49,7 @@ * FPGA */ #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_FPGA #define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h deleted file mode 100644 index 950d71b5ce..0000000000 --- a/include/configs/muas3001.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_8260 1 -#define CONFIG_MPC8260 1 -#define CONFIG_MUAS3001 1 - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* Do boardspecific init */ -#define CONFIG_BOARD_EARLY_INIT_R 1 - -/* enable Watchdog */ -#define CONFIG_WATCHDOG 1 - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#if defined(CONFIG_MUAS_DEV_BOARD) -#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ -#else -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ -#endif - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#define CONFIG_ETHER_INDEX 1 -#define CONFIG_ETHER_ON_FCC1 -#define CONFIG_HAS_ETH0 -#define FCC_ENET - -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK12 - */ -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -/* - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - */ -# define CONFIG_SYS_CPMFCR_RAMTYPE (0) -/* know on local Bus */ -/* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */ -/* - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -# define CONFIG_SYS_PHY_ADDR 1 -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 0 /* Port A */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - - -#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */ -#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */ - -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN - -#define MIIDELAY udelay(1) - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DTT -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "u-boot_addr_r=100000\0" \ - "kernel_addr_r=200000\0" \ - "fdt_addr_r=400000\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "u-boot=muas3001/u-boot.bin\0" \ - "bootfile=muas3001/uImage\0" \ - "fdt_file=muas3001/muas3001.dtb\0" \ - "ramdisk_file=uRamdisk\0" \ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ - "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \ - "prot on ff000000 ff03ffff\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "tftp ${ramdisk_addr} ${ramdisk_file}; " \ - "run ramargs addip; " \ - "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \ - "ramdisk_addr=ff210000\0" \ - "kernel_addr=ff050000\0" \ - "fdt_addr=ff200000\0" \ - "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \ - " ${ramdisk_addr} ${fdt_addr}\0" \ - "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \ - " ${ramdisk_file};" \ - "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \ - "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \ - " ${bootfile};" \ - "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \ - "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \ - "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_SIZE 32 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/* - * I2C Bus - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */ - -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x00200000 -#define CONFIG_SYS_BCR 0x004c0000 -#define CONFIG_SYS_SCCR 0x0 - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 4 60x GPCM 16 bit I/O Ctrl - * - */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (0xff000020) - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ - -#define CONFIG_SYS_MPTPR 0x2800 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 -#define CONFIG_SYS_PSRT 0x13 - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE - -/* SDRAM initialization values -*/ -#define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3 - -#define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A4 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_BIG 0x014f36a3 - -/* IO on CS4 initialization values -*/ -#define CONFIG_SYS_IO_BASE 0xc0000000 -#define CONFIG_SYS_IO_SIZE 1 - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\ - BRx_PS_16 | BRx_MS_GPCM_L | BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (0xfff80020) - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TBCLK (bd->bi_busfreq / 4) -#if defined(CONFIG_MUAS_DEV_BOARD) -#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" -#else -#define OF_STDOUT_PATH "/soc/cpm/serial@11a80" -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h deleted file mode 100644 index d875901d56..0000000000 --- a/include/configs/mucmc52.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MUCMC52 1 /* MUCMC52 board */ -#define CONFIG_HOSTNAME mucmc52 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#include "manroland/common.h" -#include "manroland/mpc5200-common.h" - -#define CONFIG_LAST_STAGE_INIT -/* - * Serial console configuration - */ -#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ - -#define CONFIG_CMD_PCI - -/* - * Flash configuration - */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * Environment settings - */ -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/* - * Memory map - */ -#define CONFIG_SYS_STATUS1_BASE 0x80600200 -#define CONFIG_SYS_STATUS2_BASE 0x80600300 -#define CONFIG_SYS_PMI_UNI_BASE 0x80800000 -#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x00f00000 - -#define CONFIG_SYS_LOAD_ADDR 0x100000 - -#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00 - -/* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_SIZE 0x00100000 -#define CONFIG_SYS_CS1_CFG 0x00019B00 - -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE - -/* FRAM 32Kbyte @0x80700000 */ -#define CONFIG_SYS_CS2_START 0x80700000 -#define CONFIG_SYS_CS2_SIZE 0x00008000 -#define CONFIG_SYS_CS2_CFG 0x00019800 - -/* Display H1, Status Inputs, EPLD @0x80600000 */ -#define CONFIG_SYS_CS3_START 0x80600000 -#define CONFIG_SYS_CS3_SIZE 0x00100000 -#define CONFIG_SYS_CS3_CFG 0x00019800 - -/* PMI Unicast 32Kbyte @0x80800000 */ -#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE -#define CONFIG_SYS_CS6_SIZE 0x00008000 -#define CONFIG_SYS_CS6_CFG 0xFFFFF930 - -/* PMI Broadcast 32Kbyte @0x80810000 */ -#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE -#define CONFIG_SYS_CS7_SIZE 0x00008000 -#define CONFIG_SYS_CS7_CFG 0xFF00F930 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS - -/*---------------------------------------------------------------------*/ -/* Display addresses */ -/*---------------------------------------------------------------------*/ - -#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38) -#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30) - -#endif /* __CONFIG_H */ diff --git a/include/configs/munices.h b/include/configs/munices.h index 7700a1d57d..e65a14af23 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -11,8 +11,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ #define CONFIG_MUNICES 1 /* ... on MUNICes board */ @@ -166,7 +165,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -176,7 +174,6 @@ #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_CMDLINE_EDITING 1 diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index c458dd9734..721b75daee 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -35,7 +35,6 @@ /* * CLKs configurations */ -#define CONFIG_SYS_HZ 1000 /* * NS16550 Configuration diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h index f6c06eea25..311fc0c3c5 100644 --- a/include/configs/mv88f6281gtw_ge.h +++ b/include/configs/mv88f6281gtw_ge.h @@ -18,7 +18,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h deleted file mode 100644 index 4de4324f74..0000000000 --- a/include/configs/mx1ads.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * include/configs/mx1ads.h - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * This is the Configuration setting for Motorola MX1ADS board - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */ -#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ - -/* - * Select serial console configuration - */ -#define CONFIG_IMX_SERIAL -#define CONFIG_IMX_SERIAL1 /* internal uart 1 */ -/* #define _CONFIG_UART2 */ /* internal uart 2 */ -/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */ - -#define CONFIG_BOARD_LATE_INIT -#define USE_920T_MMU 1 - -#if 0 -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#endif - -/* - * Size of malloc() pool - */ - -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * CS8900 Ethernet drivers - */ -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x15000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -/* - * select serial console configuration - */ - -/* #define CONFIG_UART1 */ -/* #define CONFIG_UART2 1 */ - -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_ELF - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" -#define CONFIG_BOOTFILE "mx1ads" -#define CONFIG_BOOTCOMMAND "tftp; bootm" - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ - /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */ -#endif - -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */ -/*#define CONFIG_SYS_HZ 1000 */ -#define CONFIG_SYS_HZ 3686400 -#define CONFIG_SYS_CPUSPEED 0x141 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_TEXT_BASE 0x10000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ -#define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYNCFLASH 1 -#define PHYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_SECT (16) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000) - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x100000 - -/*----------------------------------------------------------------------- - * Enable passing ATAGS - */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -#define CONFIG_SYS_CLK_FREQ 16780000 -#define CONFIG_SYSPLL_CLK_FREQ 16000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 94bedd6d25..564f4ec9af 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -1,42 +1,16 @@ /* * Copyright (C) 2013 Marek Vasut * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __MX23_OLINUXINO_CONFIG_H__ -#define __MX23_OLINUXINO_CONFIG_H__ - -#include - -/* - * SoC configurations - */ -#define CONFIG_MX23 /* i.MX23 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#ifndef __CONFIGS_MX23_OLINUXINO_H__ +#define __CONFIGS_MX23_OLINUXINO_H__ +/* System configurations */ #define CONFIG_MACH_TYPE 4105 -#include - +/* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT - -/* - * SPL - */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - -/* - * U-Boot Commands - */ #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -51,92 +25,36 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_USB -/* - * Memory configurations - */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER +/* Environment */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OVERWRITE -/* - * Serial Driver - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif -/* - * Status LED - */ +/* Status LED */ #define CONFIG_STATUS_LED #define CONFIG_GPIO_LED #define CONFIG_BOARD_SPECIFIC_LED -#define STATUS_LED_BOOT 0 -#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1 +#define STATUS_LED_BOOT 0 +#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1 #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_MXS_MMC -#endif - -/* - * APBH DMA - */ -#define CONFIG_APBH_DMA - /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif @@ -146,31 +64,13 @@ #define CONFIG_USB_ETHER_SMSC95XX #endif -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS +/* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* - * Extra Environments - */ +/* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ @@ -252,4 +152,7 @@ "fi; " \ "else run netboot; fi" -#endif /* __MX23_OLINUXINO_CONFIG_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX23_OLINUXINO_H__ */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 2380649e06..05f5ddb6e3 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -6,33 +6,14 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __MX23EVK_CONFIG_H__ -#define __MX23EVK_CONFIG_H__ - -/* SoC configurations */ -#define CONFIG_MX23 /* i.MX23 SoC */ - -#include - -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#ifndef __CONFIGS_MX23EVK_H__ +#define __CONFIGS_MX23EVK_H__ +/* System configurations */ #define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK -#define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - /* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH #include #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS @@ -49,86 +30,33 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_VIDEO -/* Memory configurations */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +/* Environment */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_MMC -/* U-Boot general configurations */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* Serial Driver */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -/* DMA */ -#define CONFIG_APBH_DMA - -/* MMC Driver */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_MXS_MMC +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 #endif /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif /* Framebuffer support */ #ifdef CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP @@ -138,21 +66,10 @@ #endif /* Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT - -/* Environment */ -#define CONFIG_ENV_IS_IN_MMC -#ifdef CONFIG_ENV_IS_IN_MMC - #define CONFIG_ENV_OFFSET (256 * 1024) - #define CONFIG_ENV_SIZE (16 * 1024) - #define CONFIG_SYS_MMC_ENV_DEV 0 -#endif /* Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -166,7 +83,7 @@ "fi ; " \ "fi\0" \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttyAMA0\0" \ "fdt_file=imx23-evk.dtb\0" \ "fdt_addr=0x41000000\0" \ @@ -180,22 +97,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -203,7 +120,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else " \ "echo ERR: Fail to boot from MMC; " \ @@ -211,4 +128,7 @@ "fi; " \ "else exit; fi" -#endif /* __MX23EVK_CONFIG_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX23EVK_H__ */ diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 543c4159ef..ec4e42f48c 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -11,10 +11,13 @@ /* High Level Configuration Options */ -#define CONFIG_MX25 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0x81200000 #define CONFIG_MXC_GPIO +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_TIMER_RATE 32768 +#define CONFIG_SYS_TIMER_COUNTER \ + (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -59,15 +62,15 @@ /* No NOR flash present */ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* U-Boot general configuration */ -#define CONFIG_SYS_PROMPT "MX25PDK U-Boot > " #define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print buffer sz */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) @@ -97,24 +100,22 @@ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE #define CONFIG_SYS_FSL_ESDHC_NUM 1 /* PMIC Configs */ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC34704 +#define CONFIG_POWER_FSL_MC34704 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54 #define CONFIG_DOS_PARTITION /* I2C Configs */ #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE IMX_I2C_BASE -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC /* RTC */ #define CONFIG_RTC_IMXDI @@ -132,12 +133,104 @@ #define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_DEFAULT_FDT_FILE "imx25-pdk.dtb" + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x82000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "bootcmd=run netargs; dhcp ${uimage}; bootm\0" \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif /* __CONFIG_H */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 885e513f9d..bfd51c5bba 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -8,33 +8,14 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __MX28EVK_CONFIG_H__ -#define __MX28EVK_CONFIG_H__ - -/* SoC configurations */ -#define CONFIG_MX28 /* i.MX28 SoC */ - -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#ifndef __CONFIGS_MX28EVK_H__ +#define __CONFIGS_MX28EVK_H__ +/* System configurations */ #define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK -#include - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - /* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -49,6 +30,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_NFS #define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_SF #define CONFIG_CMD_SPI @@ -58,81 +40,28 @@ #define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_VIDEO -/* Memory configurations */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +/* Environment */ +#ifndef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (16 * 1024) +#else +#define CONFIG_ENV_SIZE (4 * 1024) +#endif #define CONFIG_ENV_OVERWRITE -/* U-Boot general configurations */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER - -/* Serial Driver */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/* DMA */ -#define CONFIG_APBH_DMA - -/* MMC Driver */ -#ifdef CONFIG_ENV_IS_IN_MMC - #define CONFIG_ENV_OFFSET (256 * 1024) - #define CONFIG_ENV_SIZE (16 * 1024) - #define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#define CONFIG_CMD_SAVEENV -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_MXS_MMC +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 #endif -/* NAND Driver */ -#define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - /* Environment is in NAND */ -#ifdef CONFIG_ENV_IS_IN_NAND +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_RANGE (512 * 1024) @@ -141,6 +70,20 @@ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) #endif +/* Environemnt is in SPI flash */ +#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET 0x40000 /* 256K */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_BUS 2 +#define CONFIG_ENV_SPI_MAX_HZ 24000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#endif + +/* UBI and NAND partitioning */ +#ifdef CONFIG_CMD_NAND #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_CMD_MTDPARTS @@ -155,18 +98,15 @@ "512k(environment)," \ "512k(redundant-environment)," \ "4m(kernel)," \ - "128k(fdt)," \ + "512k(fdt)," \ "8m(ramdisk)," \ "-(filesystem)" #endif -/* Ethernet on SOC (FEC) */ +/* FEC Ethernet on SoC */ #ifdef CONFIG_CMD_NET -#define CONFIG_NET_MULTI -#define CONFIG_ETHPRIME "FEC0" #define CONFIG_FEC_MXC -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_NET_MULTI #define CONFIG_MX28_FEC_MAC_IN_OCOTP #endif @@ -177,65 +117,35 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_SMSC95XX #endif -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MXS -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#endif - /* SPI */ #ifdef CONFIG_CMD_SPI -#define CONFIG_HARD_SPI -#define CONFIG_MXS_SPI -#define CONFIG_SPI_HALF_DUPLEX #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 /* SPI Flash */ #ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SF_DEFAULT_BUS 2 -#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 /* this may vary and depends on the installed chip */ #define CONFIG_SPI_FLASH_SST #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 - -/* (redundant) environemnt in SPI flash */ -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ -#define CONFIG_ENV_OFFSET 0x40000 /* 256K */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_BUS 2 -#define CONFIG_ENV_SPI_MAX_HZ 24000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#endif #endif + #endif /* Framebuffer support */ #ifdef CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP @@ -245,19 +155,16 @@ #endif /* Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT -/* Extra Environments */ +/* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "ubifs_file=filesystem.ubifs\0" \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ - "update_sd_firmware_filename=u-boot.sd\0" \ "update_nand_firmware_maxsz=0x100000\0" \ "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ @@ -266,7 +173,7 @@ "nand info ; " \ "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ - "update_nand_full=" /* Update FCB, DBBT and FW */ \ + "update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \ "if tftp ${update_nand_full_filename} ; then " \ "run update_nand_get_fcb_size ; " \ "nand scrub -y 0x0 ${filesize} ; " \ @@ -285,6 +192,55 @@ "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ "fi\0" \ + "update_nand_kernel=" /* Update kernel */ \ + "mtdparts default; " \ + "nand erase.part kernel; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "nand write ${loadaddr} kernel ${filesize}\0" \ + "update_nand_fdt=" /* Update fdt */ \ + "mtdparts default; " \ + "nand erase.part fdt; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${fdt_file}; " \ + "nand write ${loadaddr} fdt ${filesize}\0" \ + "update_nand_filesystem=" /* Update filesystem */ \ + "mtdparts default; " \ + "nand erase.part filesystem; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${ubifs_file}; " \ + "ubi part filesystem; " \ + "ubi create filesystem; " \ + "ubi write ${loadaddr} filesystem ${filesize}\0" \ + "nandargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \ + "nandboot=" /* Boot from NAND */ \ + "mtdparts default; " \ + "run nandargs; " \ + "nand read ${loadaddr} kernel 0x00400000; " \ + "if test ${boot_fdt} = yes; then " \ + "nand read ${fdt_addr} fdt 0x00080000; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = no; then " \ + "bootz; " \ + "else " \ + "echo \"ERROR: Set boot_fdt to yes or no.\"; " \ + "fi; " \ + "fi\0" \ + "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ "if mmc rescan ; then " \ "if tftp ${update_sd_firmware_filename} ; then " \ @@ -294,7 +250,7 @@ "fi ; " \ "fi\0" \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console_fsl=ttyAM0\0" \ "console_mainline=ttyAMA0\0" \ "fdt_file=imx28-evk.dtb\0" \ @@ -310,22 +266,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ "root=/dev/nfs " \ @@ -337,19 +293,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi;" \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -357,11 +313,14 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ "fi; " \ "else run netboot; fi" -#endif /* __MX28EVK_CONFIG_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX28EVK_H__ */ diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index b1b68528a3..f4f2670213 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -3,7 +3,7 @@ * * Configuration settings for the MX31ADS Freescale board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -12,8 +12,6 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 1 /* in a mx31 */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -123,7 +121,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) @@ -135,8 +132,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - #define CONFIG_CMDLINE_EDITING 1 /*----------------------------------------------------------------------- diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 69045da131..974a014571 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -8,7 +8,7 @@ * * Configuration settings for the Freescale i.MX31 PDK board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -17,8 +17,8 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 /* in a mx31 */ + +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -29,7 +29,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS -#define CONFIG_SPL #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_MAX_SIZE 2048 @@ -120,7 +119,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "MX31PDK U-Boot > " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ @@ -137,8 +135,6 @@ /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_SYS_HZ 1000 - #define CONFIG_CMDLINE_EDITING /*----------------------------------------------------------------------- diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 68b225af9c..34eb1cfcd6 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -7,7 +7,7 @@ * * Configuration for the MX35pdk Freescale board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,14 +16,11 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX35 #define CONFIG_DISPLAY_CPUINFO /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA0000000 -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT @@ -41,10 +38,8 @@ /* * Hardware drivers */ -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO @@ -55,7 +50,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 #define CONFIG_RTC_MC13XXX @@ -137,7 +132,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "MX35 U-Boot > " #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ @@ -155,8 +149,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - /* * Physical Memory Map */ diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h index f0c677640e..89c36a56a4 100644 --- a/include/configs/mx51_efikamx.h +++ b/include/configs/mx51_efikamx.h @@ -5,7 +5,7 @@ * * Configuration settings for the MX51EVK Board * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -17,7 +17,6 @@ * High Level Board Configuration Options */ /* An i.MX51 CPU */ -#define CONFIG_MX51 #define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX) #define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB) @@ -29,7 +28,6 @@ #define CONFIG_SYS_TEXT_BASE 0x97800000 -#define CONFIG_L2_OFF #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF @@ -97,11 +95,11 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SST -#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8) +#define CONFIG_SF_DEFAULT_CS 1 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_ENV_SPI_CS (1 | 121 << 8) +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_MAX_HZ 25000000 #define CONFIG_ENV_SPI_MODE (SPI_MODE_0) @@ -227,7 +225,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING /*----------------------------------------------------------------------- diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 04f518a22a..3d4b8396b1 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -13,7 +13,6 @@ /* High Level Configuration Options */ -#define CONFIG_MX51 /* in a mx51 */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -26,6 +25,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_OF_LIBFDT @@ -69,7 +69,7 @@ * MMC Configs * */ #define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_NUM 2 #define CONFIG_MMC @@ -143,7 +143,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=imx51-babbage.dtb\0" \ "fdt_addr=0x91000000\0" \ "boot_fdt=try\0" \ @@ -157,22 +157,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ "root=/dev/nfs " \ @@ -184,20 +184,20 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo ERROR: Cannot load the DT; " \ "exit; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -205,7 +205,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -219,7 +219,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "MX51EVK U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ @@ -232,7 +231,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING /*----------------------------------------------------------------------- diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 122ffd074d..9015d02b0f 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -3,13 +3,12 @@ * * Configuration settings for the MX53ARD Freescale board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX53 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -23,6 +22,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) @@ -44,10 +45,8 @@ /* I2C Configs */ #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC /* MMC Configs */ #define CONFIG_FSL_ESDHC @@ -200,7 +199,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING /* Physical Memory Map */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index d39ce7b664..007b952c7e 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -3,13 +3,12 @@ * * Configuration settings for the MX53-EVK Freescale board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX53 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -23,6 +22,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_OF_LIBFDT /* Size of malloc() pool */ @@ -37,17 +38,15 @@ /* I2C Configs */ #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC /* PMIC Configs */ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_RTC_MC13XXX /* MMC Configs */ @@ -136,7 +135,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "MX53EVK U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ @@ -150,7 +148,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING /* Physical Memory Map */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 7237da5939..c3ffd38de9 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -4,13 +4,12 @@ * * Configuration settings for Freescale MX53 low cost board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX53 #define CONFIG_DISPLAY_BOARDINFO @@ -22,6 +21,8 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) @@ -65,23 +66,22 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* I2C Configs */ -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC /* PMIC Controller */ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_DIALOG_POWER #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 @@ -93,6 +93,7 @@ /* Command definition */ #include #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD #undef CONFIG_CMD_IMLS @@ -105,8 +106,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ - "fdt_file=imx53-qsb.dtb\0" \ + "image=zImage\0" \ "fdt_addr=0x71000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ @@ -118,22 +118,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ "root=/dev/nfs " \ @@ -145,20 +145,20 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo ERROR: Cannot load the DT; " \ "exit; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -166,7 +166,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -178,7 +178,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ @@ -192,16 +191,15 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 7e4e1c9661..1a97c069b7 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -3,13 +3,12 @@ * * Configuration settings for the MX53SMD Freescale board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX53 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -23,6 +22,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) @@ -34,10 +35,8 @@ /* I2C Configs */ #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC /* MMC Configs */ #define CONFIG_FSL_ESDHC @@ -121,7 +120,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "MX53SMD U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ @@ -135,7 +133,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING /* Physical Memory Map */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 674bcd3f6d..e0528ce4b9 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -17,8 +17,18 @@ #ifndef __MX6_COMMON_H #define __MX6_COMMON_H -#define CONFIG_ARM_ERRATA_742230 #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 +#define CONFIG_ARM_ERRATA_794072 +#define CONFIG_ARM_ERRATA_761320 +#define CONFIG_BOARD_POSTCLK_INIT + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#endif + +#define CONFIG_MP +#define CONFIG_MXC_GPT_HCLK #endif diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 1c5c837d3b..906adefa89 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -3,14 +3,12 @@ * * Configuration settings for the Freescale i.MX6Q Armadillo2 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX6 -#define CONFIG_MX6Q #include "mx6_common.h" @@ -23,6 +21,8 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) @@ -35,7 +35,7 @@ /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_MMC @@ -67,34 +67,69 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc3\0" \ + "fdt_file=imx6q-arm2.dtb\0" \ + "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ "mmcdev=1\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm\0" \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ @@ -102,7 +137,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -114,7 +149,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "MX6QARM2 U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 @@ -127,14 +161,12 @@ #define CONFIG_SYS_MEMTEST_END 0x10010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR @@ -156,4 +188,18 @@ #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 5530fc6f2b..0f77e7f041 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -13,6 +13,8 @@ #define CONFIG_MXC_UART_BASE UART4_BASE #define CONFIG_CONSOLE_DEV "ttymxc3" #define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb" +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb" +#endif #define CONFIG_MMCROOT "/dev/mmcblk0p2" #define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) @@ -23,12 +25,26 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX -#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } + #include "mx6sabre_common.h" +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO + #define CONFIG_SYS_FSL_USDHC_NUM 2 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 0 @@ -36,8 +52,30 @@ /* I2C Configs */ #define CONFIG_CMD_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 +/* NAND flash command */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + #endif /* __MX6QSABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h deleted file mode 100644 index 511db73605..0000000000 --- a/include/configs/mx6qsabrelite.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q Sabre Lite board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MX6 -#define CONFIG_MX6Q - -#include "mx6_common.h" - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_MACH_TYPE 3769 - -#include -#include - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R -#define CONFIG_MXC_GPIO - -#define CONFIG_CMD_FUSE -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -#define CONFIG_CMD_SF -#ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_SST -#define CONFIG_MXC_SPI -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) -#define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) -#endif - -/* I2C Configs */ -#define CONFIG_CMD_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC Configs */ -#define CONFIG_FSL_ESDHC -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMD_SATA -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#define CONFIG_LIBATA -#endif - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_MII -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 -#define CONFIG_PHYLIB -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 - -/* USB Configs */ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 -#define CONFIG_USB_STORAGE -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* Miscellaneous commands */ -#define CONFIG_CMD_BMODE - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_IPUV3_CLK 260000000 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Command definition */ -#include - -#undef CONFIG_CMD_IMLS - -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_PREBOOT "" - -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_TEXT_BASE 0x17800000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "console=ttymxc1\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6q-sabrelite.dtb\0" \ - "fdt_addr=0x11000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${uimage}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > " -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_CMDLINE_EDITING - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_ENV_IS_IN_MMC -/* #define CONFIG_ENV_IS_IN_SPI_FLASH */ - -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -#endif - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ - -#ifndef CONFIG_SYS_DCACHE_OFF -#define CONFIG_CMD_CACHE -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index dad8618c0a..da010ebf17 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -9,22 +9,30 @@ #ifndef __MX6QSABRE_COMMON_CONFIG_H #define __MX6QSABRE_COMMON_CONFIG_H -#define CONFIG_MX6 #include "mx6_common.h" +#include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #include +#include #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_DM +#define CONFIG_DM_THERMAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_IMX6_THERMAL + +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT @@ -32,6 +40,11 @@ #define CONFIG_MXC_UART +#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif + /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC @@ -59,6 +72,17 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 @@ -77,11 +101,33 @@ #define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 +#ifdef CONFIG_SUPPORT_EMMC_BOOT +#define EMMC_ENV \ + "emmcdev=2\0" \ + "update_emmc_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "if mmc dev ${emmcdev} && " \ + "mmc open ${emmcdev} 1; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "mmc close ${emmcdev} 1; " \ + "fi; " \ + "fi\0" +#else +#define EMMC_ENV "" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x11000000\0" \ + "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "console=" CONFIG_CONSOLE_DEV "\0" \ @@ -103,28 +149,29 @@ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ "fi; " \ "fi\0" \ + EMMC_ENV \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -136,19 +183,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -157,7 +204,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -170,12 +217,8 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE @@ -184,7 +227,6 @@ #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING #define CONFIG_STACKSIZE (128 * 1024) @@ -210,7 +252,7 @@ #define CONFIG_ENV_IS_IN_MMC #if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_OFFSET (8 * 64 * 1024) #endif #define CONFIG_OF_LIBFDT @@ -219,4 +261,21 @@ #define CONFIG_CMD_CACHE #endif +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 57e1860b1b..d477bb206b 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -9,13 +9,26 @@ #ifndef __MX6QSABRESD_CONFIG_H #define __MX6QSABRESD_CONFIG_H +#include +#include + +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" +#endif + #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0" #define CONFIG_MMCROOT "/dev/mmcblk1p2" #define CONFIG_DEFAULT_FDT_FILE "imx6q-sabresd.dtb" +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabresd.dtb" +#endif #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + #include "mx6sabre_common.h" #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -23,4 +36,40 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ #endif +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) +#endif + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ +#endif + #endif /* __MX6QSABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ca8f2f607d..dd0f90041e 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,9 +10,10 @@ #define __CONFIG_H #include -#include +#include +#include +#include "mx6_common.h" -#define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -24,6 +25,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) @@ -36,7 +39,7 @@ /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_MMC #define CONFIG_CMD_MMC @@ -44,6 +47,20 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 @@ -61,15 +78,15 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=imx6sl-evk.dtb\0" \ - "fdt_addr=0x81000000\0" \ + "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "mmcdev=1\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ @@ -78,22 +95,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -105,19 +122,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -126,7 +143,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -136,7 +153,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 @@ -149,7 +165,6 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING #define CONFIG_STACKSIZE SZ_128K @@ -171,10 +186,20 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K + +#if defined CONFIG_SYS_BOOT_SPINOR +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ @@ -183,4 +208,34 @@ #define CONFIG_CMD_CACHE #endif +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h new file mode 100644 index 0000000000..e1de60d6e3 --- /dev/null +++ b/include/configs/mx6sxsabresd.h @@ -0,0 +1,273 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX Sabresd board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include +#include "mx6_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sx-sdb.dtb\0" \ + "fdt_addr=0x88000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=2\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_1G + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* Network */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + + +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) +#endif + +#define CONFIG_DM +#define CONFIG_DM_THERMAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_IMX6_THERMAL + +#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_CMD_TIME + +#define CONFIG_FSL_QSPI + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define CONFIG_SYS_FSL_QSPI_AHB +#ifdef CONFIG_MX6SX_SABRESD_REVA +#define FSL_QSPI_FLASH_SIZE SZ_16M +#else +#define FSL_QSPI_FLASH_SIZE SZ_32M +#endif +#define FSL_QSPI_FLASH_NUM 2 +#endif + +#define CONFIG_ENV_OFFSET (6 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h new file mode 100644 index 0000000000..70dc50ca34 --- /dev/null +++ b/include/configs/mxs.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2013 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIGS_MXS_H__ +#define __CONFIGS_MXS_H__ + +/* + * Includes + */ + +#if defined(CONFIG_SOC_MX23) && defined(CONFIG_SOC_MX28) +#error Select either CONFIG_SOC_MX23 or CONFIG_SOC_MX28 , never both! +#elif !defined(CONFIG_SOC_MX23) && !defined(CONFIG_SOC_MX28) +#error Select one of CONFIG_SOC_MX23 or CONFIG_SOC_MX28 ! +#endif + +#include + +#if defined(CONFIG_SOC_MX23) +#include +#elif defined(CONFIG_SOC_MX28) +#include +#endif + +/* + * CPU specifics + */ +#define CONFIG_SYS_GENERIC_BOARD + +/* MXS uses FDT */ +#define CONFIG_OF_LIBFDT + +/* Startup hooks */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +/* SPL */ +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* Memory sizes */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ + +/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#if defined(CONFIG_SOC_MX23) +#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) +#elif defined(CONFIG_SOC_MX28) +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) +#endif + +/* Point initial SP in SRAM so SPL can use it too. */ +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * We need to sacrifice first 4 bytes of RAM here to avoid triggering some + * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot + * binary. In case there was more of this mess, 0x100 bytes are skipped. + * + * In case of a HAB boot, we cannot for some weird reason use the first 4KiB + * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST + * blocks, thus U-Boot starts at offset +8 KiB of DRAM start. + * + * As for the SPL, we must avoid the first 4 KiB as well, but we load the + * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. + */ +#define CONFIG_SYS_TEXT_BASE 0x40002000 +#define CONFIG_SPL_TEXT_BASE 0x00001000 + +/* U-Boot general configuration */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Booting Linux */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +/* + * Drivers + */ + +/* APBH DMA */ +#define CONFIG_APBH_DMA + +/* GPIO */ +#define CONFIG_MXS_GPIO + +/* + * DUART Serial Driver. + * Conflicts with AUART driver which can be set by board. + */ +#ifndef CONFIG_MXS_AUART +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +#define CONFIG_CONS_INDEX 0 +#endif +/* Default baudrate can be overriden by board! */ +#ifndef CONFIG_BAUDRATE +#define CONFIG_BAUDRATE 115200 +#endif + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_FEC_MXC +#define CONFIG_MII +#ifndef CONFIG_ETHPRIME +#define CONFIG_ETHPRIME "FEC0" +#endif +#ifndef CONFIG_FEC_XCV_TYPE +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#endif + +/* I2C */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXS +#define CONFIG_HARD_I2C +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 400000 +#endif +#endif + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_MXS_MMC +#endif + +/* NAND */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#endif + +/* OCOTP */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXS_OCOTP +#endif + +/* SPI */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_HARD_SPI +#define CONFIG_MXS_SPI +#define CONFIG_SPI_HALF_DUPLEX +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MXS +#define CONFIG_EHCI_IS_TDI +#endif + +#endif /* __CONFIGS_MXS_H__ */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h new file mode 100644 index 0000000000..cfb85bfe84 --- /dev/null +++ b/include/configs/nas220.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2014 Evgeni Dobrev + * + * based on work from: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_NAS220_H +#define _CONFIG_NAS220_H + +/* + * Machine type definition and ID + */ +#define MACH_TYPE_NAS220 MACH_TYPE_RD88F6192_NAS +#define CONFIG_MACH_TYPE MACH_TYPE_NAS220 +#define CONFIG_IDENT_STRING "\nNAS 220" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ +#define CONFIG_KW88F6192 /* SOC Name */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* power-on led, regulator, sata0, sata1 */ +#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) +#define NAS220_GE_OE_VAL_HIGH (0) +#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))) +#define NAS220_GE_OE_HIGH (~(0)) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_DATE +#define CONFIG_CMD_IDE +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "nas220> " + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OFFSET 0xa0000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=console=ttyS0,115200\0" \ + "mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\ + "0x010000@0xa0000(env),"\ + "0x500000@0xc0000(uimage),"\ + "0x1a40000@0x5c0000(rootfs)\0" \ + "mtdids=nand0=orion_nand\0"\ + "bootdelay=-1\0"\ + "autostart=no\0"\ + "autoload=no\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 8 +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* + * SATA + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif + + +/* + * Device Tree + */ +#define CONFIG_OF_LIBFDT + +/* + * EFI partition + */ +#define CONFIG_EFI_PARTITION + +/* + * Date Time + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +#define CONFIG_KIRKWOOD_GPIO + +#endif /* _CONFIG_NAS220_H */ + diff --git a/include/configs/neo.h b/include/configs/neo.h index ccbb1fa9b1..09300ca8ed 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -2,7 +2,7 @@ * (C) Copyright 2007-2008 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -10,7 +10,6 @@ #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_NEO 1 /* on a Neo board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -26,6 +25,7 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -38,6 +38,7 @@ /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ @@ -62,10 +63,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index 0997f49859..52cde4110c 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -4,7 +4,7 @@ * Configuration settings for the "Nomadik Hardware Kit" NHK-8815, * the evaluation board for the Nomadik 8815 System on Chip. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -12,10 +12,7 @@ #include -#define CONFIG_ARM926EJS -#define CONFIG_NOMADIK #define CONFIG_NOMADIK_8815 /* cpu variant */ -#define CONFIG_NOMADIK_NHK8815 /* board variant */ #define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ @@ -76,7 +73,6 @@ #define CONFIG_BOARD_LATE_INIT /* call board_late_init during start up */ /* timing informazion */ -#define CONFIG_SYS_HZ 1000 /* Mandatory... */ #define CONFIG_SYS_TIMERBASE 0x101E2000 /* serial port (PL011) configuration */ diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index b528f5a622..6247bf1569 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -3,7 +3,7 @@ * Scott McNutt * (C) Copyright 2010, Thomas Chou * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -15,12 +15,14 @@ #include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */ #define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */ #define CONFIG_BOARD_EARLY_INIT_F /* enable early board-spec. init */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_NIOS_SYSID_BASE CONFIG_SYS_SYSID_BASE /* * SERIAL */ -#define CONFIG_ALTERA_UART +#define CONFIG_ALTERA_JTAG_UART #if defined(CONFIG_ALTERA_JTAG_UART) # define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_JTAG_UART_BASE #else @@ -39,7 +41,6 @@ #define CONFIG_SYS_LOW_RES_TIMER #define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_TIMER_BASE #define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_TIMER_IRQ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ #define CONFIG_SYS_NIOS_TMRCNT \ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1) @@ -55,6 +56,9 @@ #define CONFIG_BOARD_SPECIFIC_LED #define CONFIG_GPIO_LED /* Enable GPIO LED driver */ #define CONFIG_GPIO /* Enable GPIO driver */ +#define LED_PIO_BASE USER_LED_PIO_8OUT_BASE +#define LED_PIO_WIDTH 8 +#define LED_PIO_RSTVAL 0xff #define STATUS_LED_BIT 0 /* Bit-0 on GPIO */ #define STATUS_LED_STATE 1 /* Blinking */ @@ -85,6 +89,10 @@ # define CONFIG_CMD_PING #endif +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_LMB + /* * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the @@ -94,7 +102,7 @@ */ #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ #define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \ CONFIG_SYS_MONITOR_LEN) | \ @@ -120,7 +128,6 @@ * MISC */ #define CONFIG_SYS_LONGHELP /* Provide extended help */ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ #define CONFIG_SYS_MAXARGS 16 /* Max command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 4242414266..33b8554058 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX6 +#include "mx6_common.h" #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -23,6 +23,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) @@ -30,6 +31,13 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE #define CONFIG_CMD_FUSE #ifdef CONFIG_CMD_FUSE @@ -45,26 +53,17 @@ #define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 25000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #endif /* I2C Configs */ #define CONFIG_CMD_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#define CONFIG_CMD_IMXOTP -#ifdef CONFIG_CMD_IMXOTP -#define CONFIG_IMX_OTP -#define IMX_OTP_BASE OCOTP_BASE_ADDR -#define IMX_OTP_ADDR_MAX 0x7F -#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA -#define IMX_OTPWRITE_ENABLED -#endif +#define CONFIG_I2C_EDID /* MMC Configs */ #define CONFIG_FSL_ESDHC @@ -77,10 +76,11 @@ #define CONFIG_GENERIC_MMC #define CONFIG_BOUNCE_BUFFER #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION -#ifdef CONFIG_MX6Q #define CONFIG_CMD_SATA #endif @@ -118,10 +118,14 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP /* Miscellaneous commands */ #define CONFIG_CMD_BMODE @@ -137,10 +141,11 @@ #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_CMD_HDMIDETECT #define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -171,41 +176,147 @@ #define CONFIG_DRIVE_MMC #endif -#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC +#ifdef CONFIG_USB_STORAGE +#define CONFIG_DRIVE_USB "usb " +#else +#define CONFIG_DRIVE_USB +#endif + +#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC CONFIG_DRIVE_USB +#define CONFIG_UMSDEVS CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC +#if defined(CONFIG_SABRELITE) #define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc1\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6q-sabrelite.dtb\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdevs=0 1\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "for mmcdev in ${mmcdevs}; do " \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "done; " \ + "run netboot; " +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootdevs=" CONFIG_DRIVE_TYPES "\0" \ + "umsdevs=" CONFIG_UMSDEVS "\0" \ "console=ttymxc1\0" \ "clearenv=if sf probe || sf probe || sf probe 1 ; then " \ "sf erase 0xc0000 0x2000 && " \ "echo restored environment to factory default ; fi\0" \ - "bootcmd=for dtype in " CONFIG_DRIVE_TYPES \ + "bootcmd=for dtype in ${bootdevs}" \ "; do " \ + "if itest.s \"xusb\" == \"x${dtype}\" ; then " \ + "usb start ;" \ + "fi; " \ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ - "for fs in fat ext2 ; do " \ - "${fs}load " \ - "${dtype} ${disk}:1 " \ - "10008000 " \ - "/6x_bootscript" \ - "&& source 10008000 ; " \ - "done ; " \ + "load " \ + "${dtype} ${disk}:1 " \ + "10008000 " \ + "/6x_bootscript" \ + "&& source 10008000 ; " \ "done ; " \ "done; " \ "setenv stdout serial,vga ; " \ "echo ; echo 6x_bootscript not found ; " \ "echo ; echo serial console at 115200, 8N1 ; echo ; " \ "echo details at http://boundarydevices.com/6q_bootscript ; " \ - "setenv stdout serial\0" \ - "upgradeu=for dtype in " CONFIG_DRIVE_TYPES \ + "setenv stdout serial;" \ + "setenv stdin serial,usbkbd;" \ + "for dtype in ${umsdevs} ; do " \ + "if itest.s sata == ${dtype}; then " \ + "initcmd='sata init' ;" \ + "else " \ + "initcmd='mmc rescan' ;" \ + "fi; " \ + "for disk in 0 1 ; do " \ + "if $initcmd && $dtype dev $disk ; then " \ + "setenv stdout serial,vga; " \ + "echo expose ${dtype} ${disk} " \ + "over USB; " \ + "ums 0 $dtype $disk ;" \ + "fi; " \ + " done; " \ + "done ;" \ + "setenv stdout serial,vga; " \ + "echo no block devices found;" \ + "\0" \ + "initrd_high=0xffffffff\0" \ + "upgradeu=for dtype in ${bootdevs}" \ "; do " \ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ - "for fs in fat ext2 ; do " \ - "${fs}load ${dtype} ${disk}:1 10008000 " \ - "/6x_upgrade " \ - "&& source 10008000 ; " \ - "done ; " \ + "load ${dtype} ${disk}:1 10008000 " \ + "/6x_upgrade " \ + "&& source 10008000 ; " \ "done ; " \ "done\0" \ +#endif /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER @@ -215,7 +326,7 @@ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MAXARGS 48 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MEMTEST_START 0x10000000 @@ -223,7 +334,6 @@ #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING @@ -245,8 +355,11 @@ #define CONFIG_ENV_SIZE (8 * 1024) -/* #define CONFIG_ENV_IS_IN_MMC */ +#if defined(CONFIG_SABRELITE) +#define CONFIG_ENV_IS_IN_MMC +#else #define CONFIG_ENV_IS_IN_SPI_FLASH +#endif #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_ENV_OFFSET (6 * 64 * 1024) @@ -270,10 +383,39 @@ #define CONFIG_CMD_BMP #define CONFIG_CMD_TIME +#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_CMD_BOOTZ #define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_CMD_FS_GENERIC +/* + * PCI express + */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#endif + +#define CONFIG_CMD_ELF + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* Netchip IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "Boundary" + +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 + #endif /* __CONFIG_H */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 36c6800c56..46fc91e5e1 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -13,7 +13,7 @@ * * Configuration settings for the Nokia RX-51 aka N900. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -24,10 +24,11 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3430 /* which is in a 3430 */ #define CONFIG_OMAP3_RX51 /* working with RX51 */ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ +#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 @@ -156,10 +157,10 @@ #undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ #define CONFIG_OMAP3_SPI -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 @@ -219,8 +220,6 @@ #ifdef ONENAND_SUPPORT -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS @@ -262,9 +261,10 @@ #define VIDEO_TSTC_FCT rx51_kp_tstc #define VIDEO_GETC_FCT rx51_kp_getc #ifndef __ASSEMBLY__ +struct stdio_dev; int rx51_kp_init(void); -int rx51_kp_tstc(void); -int rx51_kp_getc(void); +int rx51_kp_tstc(struct stdio_dev *sdev); +int rx51_kp_getc(struct stdio_dev *sdev); #endif #ifndef MTDPARTS_DEFAULT @@ -425,7 +425,6 @@ int rx51_kp_getc(void); */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* * Stack sizes diff --git a/include/configs/novena.h b/include/configs/novena.h new file mode 100644 index 0000000000..0eb061138a --- /dev/null +++ b/include/configs/novena.h @@ -0,0 +1,298 @@ +/* + * Configuration settings for the Novena U-boot. + * + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* System configurations */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MISC_INIT_R +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_FIT +#define CONFIG_KEYBOARD +#define CONFIG_MXC_GPIO +#define CONFIG_OF_LIBFDT +#define CONFIG_REGEX +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_NO_FLASH + +#include "configs/mx6_common.h" +#include +#include +#include + +/* U-Boot Commands */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_I2C +#define CONFIG_CMD_FUSE +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SATA +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_TIME +#define CONFIG_CMD_USB +#define CONFIG_VIDEO + +/* U-Boot general configurations */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER + +/* U-Boot environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SIZE (16 * 1024) +/* + * Environment is on MMC, starting at offset 512KiB from start of the card. + * Please place first partition at offset 1MiB from the start of the card + * as recommended by GNU/fdisk. See below for details: + * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET (512 * 1024) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTARGS "console=ttymxc1,115200 " +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_LOADADDR 0x18000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_HOSTNAME novena + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE 0xF0000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + +/* SPL */ +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" /* common IMX6 SPL configuration */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Ethernet Configuration */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0x7 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_ARP_TIMEOUT 200UL +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C EEPROM */ +#ifdef CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_SPD_BUS_NUM 2 +#endif + +/* MMC Configs */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* OCOTP Configs */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* PCI express */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) +#endif + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* SATA Configs */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_INDEX 1 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +/* Gadget part */ +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#endif + +/* Video output */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* Extra U-Boot environment. */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "consdev=ttymxc1\0" \ + "baudrate=115200\0" \ + "bootdev=/dev/mmcblk0p1\0" \ + "rootdev=/dev/mmcblk0p2\0" \ + "netdev=eth0\0" \ + "kernel_addr_r=0x18000000\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "update_sd_spl_filename=SPL\0" \ + "update_sd_uboot_filename=u-boot.img\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if dhcp ${update_sd_spl_filename} ; then " \ + "mmc write ${loadaddr} 2 0x200 ; " \ + "fi ; " \ + "if dhcp ${update_sd_uboot_filename} ; then " \ + "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\ + "fi ; " \ + "fi\0" \ + +#endif /* __CONFIG_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h new file mode 100644 index 0000000000..cf331ab207 --- /dev/null +++ b/include/configs/nyan-big.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Nyan-big) # " +#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/o2d.h b/include/configs/o2d.h index eff1bcef3b..b2905b2697 100644 --- a/include/configs/o2d.h +++ b/include/configs/o2d.h @@ -43,8 +43,8 @@ #define CONFIG_BOARD_NAME "o2d" #define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT xstr(126) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(126) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -56,7 +56,7 @@ "ramtop=fc55ffff\0" \ "jffbot=fc560000\0" \ "jfftop=fcffffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=fc03ffff\0" \ "kernel_addr=0xfc060000\0" \ "ramdisk_addr=0xfc160000\0" \ diff --git a/include/configs/o2d300.h b/include/configs/o2d300.h index 1af53834f7..a8222d9f97 100644 --- a/include/configs/o2d300.h +++ b/include/configs/o2d300.h @@ -44,8 +44,8 @@ #define CONFIG_BOARD_NAME "o2d300" #define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT xstr(126) -#define BOARD_POST_CRC32_END xstr(0x02000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(126) +#define BOARD_POST_CRC32_END __stringify(0x02000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -63,7 +63,7 @@ "ramtop=fc57ffff\0" \ "jffbot=fc580000\0" \ "jfftop=fd39ffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=fc03ffff\0" \ "halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0" \ "halbot=fd3a0000\0" \ diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index 90c45d5c47..18388d150b 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -7,7 +7,7 @@ * (C) Copyright 2012 * DENX Software Engineering, Anatolij Gustschin * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __O2D_CONFIG_H @@ -16,8 +16,9 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ @@ -115,9 +116,6 @@ #undef CONFIG_BOOTARGS -#define xstr(s) str(s) -#define str(s) #s - #if !defined(CONFIG_CONSOLE_DEV) #define CONFIG_CONSOLE_DEV "ttyPSC1" #endif @@ -159,7 +157,7 @@ "kernel_addr_r=600000\0" \ "initrd_high=0x03e00000\0" \ "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \ - "memtest=mtest 0x00100000 "xstr(CONFIG_SYS_MEMTEST_END)" 0 1\0" \ + "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ @@ -183,7 +181,7 @@ "unlock=yes\0" \ "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \ "setenv bootdelay 1;" \ - "crc32 "xstr(CONFIG_SYS_TEXT_BASE)" " \ + "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \ BOARD_POST_CRC32_END";" \ "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0" @@ -276,10 +274,8 @@ #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE #endif -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE @@ -311,7 +307,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER @@ -332,7 +327,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_SYS_HZ 1000 /* * Various low-level settings diff --git a/include/configs/o2dnt2.h b/include/configs/o2dnt2.h index 3636c0e1d4..1b765a7e4e 100644 --- a/include/configs/o2dnt2.h +++ b/include/configs/o2dnt2.h @@ -43,8 +43,8 @@ #define CONFIG_BOARD_NAME "o2dnt2" #define CONFIG_BOARD_BOOTCMD "run flash_self" -#define CONFIG_BOARD_MEM_LIMIT xstr(126) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(126) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -56,7 +56,7 @@ "ramtop=fc55ffff\0" \ "jffbot=fc560000\0" \ "jfftop=fce5ffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=fc03ffff\0" \ "calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \ "calbot=fce60000\0" \ diff --git a/include/configs/o2i.h b/include/configs/o2i.h index 8fe1da58bb..c0fcedaf10 100644 --- a/include/configs/o2i.h +++ b/include/configs/o2i.h @@ -37,8 +37,8 @@ #define CONFIG_BOARD_NAME "o2i" #define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT xstr(62) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(62) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -52,7 +52,7 @@ "jfftop=ffebffff\0" \ "kernel_addr=0xff060000\0" \ "ramdisk_addr=0xff160000\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=ff03ffff\0" \ "autoload=no\0" \ "dhcp_boot=run dhcpcmd; run flash_mtd\0" \ diff --git a/include/configs/o2mnt.h b/include/configs/o2mnt.h index c2164b5efb..eb63cb0c85 100644 --- a/include/configs/o2mnt.h +++ b/include/configs/o2mnt.h @@ -39,8 +39,8 @@ #define CONFIG_BOARD_NAME "o2mnt" #define CONFIG_BOARD_BOOTCMD "${newcmd}" -#define CONFIG_BOARD_MEM_LIMIT xstr(62) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(62) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #ifndef CONFIG_IFM_SENSOR_TYPE #define CONFIG_IFM_SENSOR_TYPE "O2M110" @@ -56,7 +56,7 @@ "ramtop=ffc5ffff\0" \ "jffbot=ffc60000\0" \ "jfftop=ffffffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=ff03ffff\0" \ "kernel_addr=0xff060000\0" \ "ramdisk_addr=0xff260000\0" \ diff --git a/include/configs/o3dnt.h b/include/configs/o3dnt.h index 05cd360815..77907507b3 100644 --- a/include/configs/o3dnt.h +++ b/include/configs/o3dnt.h @@ -44,8 +44,8 @@ #define CONFIG_BOARD_NAME "o3dnt" #define CONFIG_BOARD_BOOTCMD "run flash_self" -#define CONFIG_BOARD_MEM_LIMIT xstr(62) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(62) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -57,7 +57,7 @@ "ramtop=fc55ffff\0" \ "jffbot=fc560000\0" \ "jfftop=fce5ffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=fc03ffff\0" \ "calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \ "calbot=fce60000\0" \ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 60ee8da558..4ff2f05c88 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -4,7 +4,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -26,7 +26,6 @@ #define CONFIG_OCOTEA 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h new file mode 100644 index 0000000000..9d5dbdce36 --- /dev/null +++ b/include/configs/odroid.h @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Sanghee Kim + * Piotr Wilczek + * Przemyslaw Marczak + * + * Configuation settings for the Odroid-U3 (EXYNOS4412) board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ODROID_U3_H +#define __CONFIG_ODROID_U3_H + +#include + +#define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */ + + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x10502000 +#endif + +#define CONFIG_MACH_TYPE 4289 + +#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) +#define CONFIG_SYS_TEXT_BASE 0x43e00000 + +#include + +/* select serial console configuration */ +#define CONFIG_SERIAL1 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_CMD_BOOTZ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (SZ_1M) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ +#define CONFIG_ENV_OVERWRITE + +/* Partitions name */ +#define PARTS_BOOT "boot" +#define PARTS_ROOT "platform" + +#define CONFIG_DFU_ALT \ + "uImage fat 0 1;" \ + "zImage fat 0 1;" \ + "Image.itb fat 0 1;" \ + "uInitrd fat 0 1;" \ + "exynos4412-odroidu3.dtb fat 0 1;" \ + "exynos4412-odroidx2.dtb fat 0 1;" \ + ""PARTS_BOOT" part 0 1;" \ + ""PARTS_ROOT" part 0 2\0" \ + +#define CONFIG_SET_DFU_ALT_INFO +#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) + +#define CONFIG_DFU_ALT_BOOT_EMMC \ + "u-boot raw 0x3e 0x800 mmcpart 1;" \ + "bl1 raw 0x0 0x1e mmcpart 1;" \ + "bl2 raw 0x1e 0x1d mmcpart 1;" \ + "tzsw raw 0x83e 0x138 mmcpart 1\0" + +#define CONFIG_DFU_ALT_BOOT_SD \ + "u-boot raw 0x3f 0x800;" \ + "bl1 raw 0x1 0x1e;" \ + "bl2 raw 0x1f 0x1d;" \ + "tzsw raw 0x83f 0x138\0" + +/* + * Bootable media layout: + * dev: SD eMMC(part boot) + * BL1 1 0 + * BL2 31 30 + * UBOOT 63 62 + * TZSW 2111 2110 + * ENV 2560 2560(part user) + * + * MBR Primary partiions: + * Num Name Size Offset + * 1. BOOT: 100MiB 2MiB + * 2. ROOT: - +*/ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "${kernelname}\0" \ + "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ + "${initrdname}\0" \ + "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "check_ramdisk=" \ + "if run loadinitrd; then " \ + "setenv initrd_addr ${initrdaddr};" \ + "else " \ + "setenv initrd_addr -;" \ + "fi;\0" \ + "check_dtb=" \ + "if run loaddtb; then " \ + "setenv fdt_addr ${fdtaddr};" \ + "else " \ + "setenv fdt_addr;" \ + "fi;\0" \ + "kernel_args=" \ + "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \ + " rootwait ${console} ${opts}\0" \ + "boot_fit=" \ + "setenv kerneladdr 0x42000000;" \ + "setenv kernelname Image.itb;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr}#${boardname}\0" \ + "boot_uimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname uImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "boot_zimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname zImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "autoboot=" \ + "if test -e mmc 0 Image.itb; then; " \ + "run boot_fit;" \ + "elif test -e mmc 0 zImage; then; " \ + "run boot_zimg;" \ + "elif test -e mmc 0 uImage; then; " \ + "run boot_uimg;" \ + "fi;\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "mmcbootdev=0\0" \ + "mmcbootpart=1\0" \ + "mmcrootdev=0\0" \ + "mmcrootpart=2\0" \ + "bootdelay=0\0" \ + "dfu_alt_system="CONFIG_DFU_ALT \ + "dfu_alt_info=Please reset the board\0" \ + "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ + "consoleoff=set console console=ram; save; reset\0" \ + "initrdname=uInitrd\0" \ + "initrdaddr=42000000\0" \ + "fdtaddr=40800000\0" + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_DM_I2C +#define CONFIG_DM_I2C_COMPAT +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 + +/* POWER */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_MAX77686 + +/* GPT */ +#define CONFIG_RANDOM_UUID + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_LIB_HW_RAND + +#define CONFIG_CMD_GPIO + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS +#define CONFIG_USB_STORAGE + +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +/* + * Supported Odroid boards: X3, U3 + * TODO: Add Odroid X support + */ +#define CONFIG_MISC_COMMON +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_BOARD_TYPES +#define CONFIG_MISC_INIT_R + +#undef CONFIG_REVISION_TAG + +#endif /* __CONFIG_H */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000000..9fa86603f6 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Hyungwon Hwang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H + +#include "exynos5420-common.h" + +#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3" + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */ + +#define TZPC_BASE_OFFSET 0x10000 + +#define CONFIG_CMD_MMC + +/* + * FIXME: The number of bank is actually 8. But there is no way to reserve the + * last 16 Mib in the last bank now. So I just excluded the last bank + * temporally. + */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#define CONFIG_ENV_IS_IN_MMC + +#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS + +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h deleted file mode 100644 index a578edd0d8..0000000000 --- a/include/configs/omap1510.h +++ /dev/null @@ -1,772 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * OMAP hardware map - * - * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* - There are 2 sets of general I/O --> - 1. GPIO (shared between ARM & DSP, configured by ARM) - 2. MPUIO which can be used only by the ARM. - - Base address FFFB:5000 is where the ARM accesses the MPUIO control registers - (see 7.2.2 of the TRM for MPUIO reg definitions). - - Base address E101:5000 is reserved for ARM access of the same MPUIO control - regs, but via the DSP I/O map. This address is unavailable on 1510. - - Base address FFFC:E000 is where the ARM accesses the GPIO config registers - directly via its own peripheral bus. - - Base address E101:E000 is where the ARM can access the same GPIO config - registers, but the access takes place through the ARM port interface (called - API or MPUI) via the DSP's peripheral bus (DSP I/O space). - - Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses - instead of the E101:E000 addresses. The DSP has only read access of the pin - control register, so this may explain the inability to write to E101:E018. - Try accessing pin control reg at FFFC:E018. - */ -#define OMAP1510_GPIO_BASE 0xfffce000 -#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE -#define OMAP1510_GPIO_SIZE SZ_4K - -#define OMAP1510_MCBSP1_BASE 0xE1011000 -#define OMAP1510_MCBSP1_SIZE SZ_4K -#define OMAP1510_MCBSP1_START 0xE1011000 - -#define OMAP1510_MCBSP2_BASE 0xFFFB1000 - -#define OMAP1510_MCBSP3_BASE 0xE1017000 -#define OMAP1510_MCBSP3_SIZE SZ_4K -#define OMAP1510_MCBSP3_START 0xE1017000 - -/* - * Where's the flush address (for flushing D and I cache?) - */ -#define FLUSH_BASE 0xdf000000 -#define FLUSH_BASE_PHYS 0x00000000 - -#ifndef __ASSEMBLER__ - -#define PCIO_BASE 0 - -/* - * RAM definitions - */ -#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) -#define KERNTOPHYS(a) ((unsigned long)(&a)) -#define KERNEL_BASE (0x10008000) -#endif - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x)) - -/* ---------------------------------------------------------------------------- - * OMAP1510 system registers - * ---------------------------------------------------------------------------- - */ - -#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ -#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ -#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ -#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ -#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ -#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ -#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ - -/* - * OMAP1510 UART3 Registers - */ - -#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ - -/* UART3 Registers Maping through MPU bus */ - -#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) -#define UART3_THR (OMAP_MPU_UART3_BASE + 0) -#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) -#define UART3_IER (OMAP_MPU_UART3_BASE + 4) -#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) -#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) -#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) -#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) -#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) - -/* - * Configuration Registers - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define GATE_INH_CTRL_0 0xfffe1050 -#define VOLTAGE_CTRL_0 0xfffe1060 -#define TEST_DBG_CTRL_0 0xfffe1070 - -#define MOD_CONF_CTRL_0 0xfffe1080 - -#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ - -#define USB_OTG_CTRL 0xFFFB040C -#define USB_TRANSCEIVER_CTRL 0xFFFE1064 -#define PULL_DWN_CTRL_4 0xFFFE10AC -#define PU_PD_SEL_0 0xFFFE10B4 -#define PU_PD_SEL_1 0xFFFE10B8 -#define PU_PD_SEL_2 0xFFFE10BC -#define PU_PD_SEL_3 0xFFFE10C0 -#define PU_PD_SEL_4 0xFFFE10C4 - -#endif -/* - * Traffic Controller Memory Interface Registers - */ -#define TCMIF_BASE 0xfffecc00 -#define IMIF_PRIO (TCMIF_BASE + 0x00) -#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) -#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) -#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) -#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) -#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) -#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) -#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) -#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) -#define EMIFF_MRS (TCMIF_BASE + 0x24) -#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) -#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) -#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) -#define TC_ENDIANISM (TCMIF_BASE + 0x34) -#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) -#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) - -/* - * LCD Panel - */ -#define TI925_LCD_BASE 0xFFFEC000 -#define TI925_LCD_CONTROL (TI925_LCD_BASE) -#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) -#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) -#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) -#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) -#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) - -#define OMAP_LCD_CONTROL TI925_LCD_CONTROL - -/* I2C Registers */ - -#define I2C_BASE 0xfffb3800 - -#define I2C_REV (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_IV (I2C_BASE + 0x0c) -#define I2C_BUF (I2C_BASE + 0x14) -#define I2C_CNT (I2C_BASE + 0x18) -#define I2C_DATA (I2C_BASE + 0x1c) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_OA (I2C_BASE + 0x28) -#define I2C_SA (I2C_BASE + 0x2c) -#define I2C_PSC (I2C_BASE + 0x30) -#define I2C_SCLL (I2C_BASE + 0x34) -#define I2C_SCLH (I2C_BASE + 0x38) -#define I2C_SYSTEST (I2C_BASE + 0x3c) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ - -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_AD0 (1 << 8) /* Address zero */ -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Vector Register (I2C_IV): */ - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* - * MMC/SD Host Controller Registers - */ - -#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ -#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ -#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ -#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ -#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ -#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ -#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ -#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ -#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ -#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ -#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ -#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ -#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ -#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ -#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ -#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ -#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ -#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ -#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ -#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ -#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ -#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ -#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ -#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ - -/* MMC masks */ - -#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ -#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ -#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ -#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ -#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ -#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ -#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ -#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ -#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ -#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ -#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ -#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ -#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ - -/* 2.9.2 MPUI Interface Registers FFFE:C900 */ - -#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) -#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) -#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) -#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) -#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) -#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) -#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) -#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) - -/* 2.9.6 Traffic Controller Memory Interface Registers: */ -#define OMAP_IMIF_PRIO_REG 0xfffecc00 -#define OMAP_EMIFS_PRIO_REG 0xfffecc04 -#define OMAP_EMIFF_PRIO_REG 0xfffecc08 -#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c -#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 -#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 -#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 -#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c -#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 -#define OMAP_EMIFF_MRS 0xfffecc24 -#define OMAP_TIMEOUT1 0xfffecc28 -#define OMAP_TIMEOUT2 0xfffecc2c -#define OMAP_TIMEOUT3 0xfffecc30 -#define OMAP_ENDIANISM 0xfffecc34 - -/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ -#define OMAP_EMIFS_CONFIG_FR (1 << 4) -#define OMAP_EMIFS_CONFIG_PDE (1 << 3) -#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) -#define OMAP_EMIFS_CONFIG_BM (1 << 1) -#define OMAP_EMIFS_CONFIG_WP (1 << 0) - -/* - * Memory chunk set aside for the Framebuffer in SRAM - */ -#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE - - -/* - * DMA - */ - -#define OMAP1510_DMA_BASE 0xFFFED800 -#define OMAP_DMA_BASE OMAP1510_DMA_BASE - -/* Global Register selection */ -#define NO_GLOBAL_DMA_ACCESS 0 - -/* Channel select field - * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... - */ -#define LCD_CHANNEL 0xc - -/* Register Select Field (LCD) */ -#define DMA_LCD_CTRL 0 -#define DMA_LCD_TOP_F1_L 1 -#define DMA_LCD_TOP_F1_U 2 -#define DMA_LCD_BOT_F1_L 3 -#define DMA_LCD_BOT_F1_U 4 - -#define LCD_FRAME_MODE (1<<0) -#define LCD_FRAME_IT_IE (1<<1) -#define LCD_BUS_ERROR_IT_IE (1<<2) -#define LCD_FRAME_1_IT_COND (1<<3) -#define LCD_FRAME_2_IT_COND (1<<4) -#define LCD_BUS_ERROR_IT_COND (1<<5) -#define LCD_SOURCE_IMIF (1<<6) - -/* - * Real-Time Clock - */ - -#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) -#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) -#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) -#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) -#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) -#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) -#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) - - -/* --------------------------------------------------------------------------- - * OMAP1510 Interrupt Handlers - * --------------------------------------------------------------------------- - * - */ -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 -#define OMAP1510_ITR 0x0 -#define OMAP1510_MASK 0x4 - -#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE -#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR -#define INTERRUPT_MASK_REGISTER OMAP1510_MASK - - -/* --------------------------------------------------------------------------- - * OMAP1510 TIMERS - * --------------------------------------------------------------------------- - * - */ - -#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 - -/* 32k Timer Registers */ -#define TIMER32k_CR 0x08 -#define TIMER32k_TVR 0x00 -#define TIMER32k_TCR 0x04 - -/* 32k Timer Control Register definition */ -#define TIMER32k_TSS (1<<0) -#define TIMER32k_TRB (1<<1) -#define TIMER32k_INT (1<<2) -#define TIMER32k_ARL (1<<3) - -/* MPU Timer base addresses */ -#define OMAP1510_MPUTIMER_BASE 0xfffec500 -#define OMAP1510_MPUTIMER_OFF 0x00000100 - -#define OMAP1510_TIMER1_BASE 0xfffec500 -#define OMAP1510_TIMER2_BASE 0xfffec600 -#define OMAP1510_TIMER3_BASE 0xfffec700 - -/* MPU Timer Registers */ -#define CNTL_TIMER 0 -#define LOAD_TIM 4 -#define READ_TIM 8 - -/* CNTL_TIMER register bits */ -#define MPUTIM_FREE (1<<6) -#define MPUTIM_CLOCK_ENABLE (1<<5) -#define MPUTIM_PTV_MASK (0x7< - * Configuation settings for the TI OMAP Innovator board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ -#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -/* -#define CONFIG_DRIVER_SMC9196 -#define CONFIG_SMC9196_BASE 0x08000300 -#define CONFIG_SMC9196_EXT_PHY -*/ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x08000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define PHYS_SRAM 0x20000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE } - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 7958ca5445..f25a940789 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -6,24 +6,28 @@ * * Configuration settings for the TI OMAP3530 Beagle board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ + /* - * High Level Configuration Options + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. We use this rather than the inherited defines from + * ti_armv7_common.h for backwards compatibility. */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ -#define CONFIG_OMAP_GPIO - -#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#include /* get chip and board defs */ -#include +#include /* * Display CPU and Board information @@ -31,57 +35,10 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ - -/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 /* Status LED */ #define CONFIG_STATUS_LED 1 @@ -109,6 +66,16 @@ #define CONFIG_TWL4030_USB 1 #define CONFIG_USB_ETHER #define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 0 +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_G_DNL_VENDOR_NUM 0x0451 +#define CONFIG_G_DNL_PRODUCT_NUM 0xd022 +#define CONFIG_G_DNL_MANUFACTURER "TI" +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 /* USB EHCI */ #define CONFIG_CMD_USB @@ -117,14 +84,15 @@ #define CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT_OMAP - #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ /* commands to include */ #include @@ -132,45 +100,24 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ + #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ "1920k(u-boot),128k(u-boot-env),"\ "4m(kernel),-(fs)" -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ #define CONFIG_USB_STORAGE /* USB storage support */ #define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_LED /* LED support */ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#define CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP #define CONFIG_CMD_SETEXPR /* Evaluate expressions */ #define CONFIG_CMD_GPIO /* Enable gpio command */ +#define CONFIG_CMD_DHCP -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 #define CONFIG_VIDEO_OMAP3 /* DSS Support */ /* * TWL4030 */ -#define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 /* @@ -178,31 +125,19 @@ */ #define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ - -/* Environment information */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "rdaddr=0x81000000\0" \ + "fdt_high=0xffffffff\0" \ + "fdtaddr=0x80f80000\0" \ "usbtty=cdc_acm\0" \ - "bootfile=uImage.beagle\0" \ + "bootfile=uImage\0" \ + "ramdisk=ramdisk.gz\0" \ + "bootdir=/boot\0" \ + "bootpart=0:2\0" \ "console=ttyO2,115200n8\0" \ "mpurate=auto\0" \ "buddy=none\0" \ @@ -238,10 +173,29 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ + "findfdt=" \ + "if test $beaglerev = AxBx; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = Cx; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = C4; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = xMAB; then " \ + "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \ + "if test $beaglerev = xMC; then " \ + "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ + "validatefdt=" \ + "if test $beaglerev = xMAB; then " \ + "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \ + "setenv fdtfile omap3-beagle-xm.dtb; " \ + "fi; " \ + "fi; \0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ + "env import -t -r $loadaddr $filesize\0" \ "ramargs=setenv bootargs console=${console} " \ "${optargs} " \ "mpurate=${mpurate} " \ @@ -251,12 +205,18 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${ramroot} " \ "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \ + "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ @@ -270,6 +230,7 @@ "userbutton_nonxm=gpio input 7;\0" /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */ #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run userbutton; then " \ "setenv bootenv uEnv.txt;" \ @@ -285,66 +246,35 @@ "echo Running uenvcmd ...;" \ "run uenvcmd;" \ "fi;" \ - "if run loaduimage; then " \ - "run mmcboot;" \ - "fi;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi; " \ "fi;" \ "run nandboot;" \ - -#define CONFIG_AUTO_COMPLETE 1 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_ALT_MEMTEST 1 -#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ - /* defaults */ -#define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */ -#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ + "setenv bootfile zImage;" \ + "if run loadimage; then " \ + "run loadfdt;" \ + "run mmcbootz; " \ + "fi; " \ /* * OMAP3 has 12 GP timers, they can be driven by the system clock * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*----------------------------------------------------------------------- * FLASH and environment organization */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ @@ -352,6 +282,7 @@ #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -359,51 +290,15 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - #define CONFIG_OMAP3_SPI #define CONFIG_SYS_CACHELINE_SIZE 64 /* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -414,17 +309,13 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index fc1ffea55b..8bdc08f586 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -11,7 +11,7 @@ * * Manikandan Pillai * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __OMAP3EVM_CONFIG_H @@ -75,8 +75,8 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" /* Partition tables */ #define CONFIG_EFI_PARTITION @@ -107,6 +107,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 3b3e25ad84..8885e17581 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -13,8 +13,8 @@ * High level configuration options */ #define CONFIG_OMAP /* This is TI OMAP core */ -#define CONFIG_OMAP34XX /* belonging to 34XX family */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ @@ -34,7 +34,6 @@ */ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* Size of environment - 128KB */ #define CONFIG_ENV_SIZE (128 << 10) @@ -87,18 +86,14 @@ /* * I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_OMAP34XX_I2C - -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * PISMO support */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - /* Monitor at start of flash - Reserve 2 sectors */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -121,7 +116,7 @@ /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 - +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Timeout values (in ticks) */ #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) @@ -206,13 +201,12 @@ * NAND / OneNAND */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#define CONFIG_SYS_FLASH_BASE ONENAND_MAP #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #endif @@ -262,7 +256,6 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 50929aaea2..1185f42550 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -87,7 +87,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif /* __OMAP3_EVM_QUICK_MMC_H */ diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 9ecd70d55b..4427e88b7e 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -86,6 +86,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h new file mode 100644 index 0000000000..6295ec505f --- /dev/null +++ b/include/configs/omap3_igep00x0.h @@ -0,0 +1,216 @@ +/* + * Common configuration settings for IGEP technology based boards + * + * (C) Copyright 2012 + * ISEE 2007 SL, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IGEP00X0_H +#define __IGEP00X0_H + +#ifdef CONFIG_BOOT_NAND +#define CONFIG_NAND +#endif + +#define CONFIG_NR_DRAM_BANKS 2 + +#include +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_MISC_INIT_R + +#define CONFIG_REVISION_TAG 1 + +/* Status LED */ +#define CONFIG_STATUS_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_GPIO_LED +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) +#define RED_LED_GPIO 27 +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) +#define RED_LED_GPIO 16 +#endif +#define RED_LED_DEV 0 +#define STATUS_LED_BIT RED_LED_GPIO +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BOOT RED_LED_DEV + +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ + +/* USB */ +#define CONFIG_MUSB_UDC 1 +#define CONFIG_USB_OMAP3 1 +#define CONFIG_TWL4030_USB 1 + +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +/* Change these to suit your needs */ +#define CONFIG_USBD_VENDORID 0x0451 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Texas Instruments" +#define CONFIG_USBD_PRODUCT_NAME "IGEP" + +#define CONFIG_CMD_CACHE +#ifdef CONFIG_BOOT_ONENAND +#define CONFIG_CMD_ONENAND /* ONENAND support */ +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ + (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#endif +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS /* NFS support */ + +/*#undef CONFIG_ENV_IS_NOWHERE*/ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usbtty=cdc_acm\0" \ + "loadaddr=0x82000000\0" \ + "dtbaddr=0x81600000\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ + "console=ttyO2,115200n8\0" \ + "mpurate=auto\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr}\0" \ + "mmcbootfdt=echo Booting with DT from mmc ...; " \ + "bootz ${loadaddr} - ${dtbaddr}\0" \ + "nandboot=echo Booting from onenand ...; " \ + "run nandargs; " \ + "onenand read ${loadaddr} 280000 400000; " \ + "bootz ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadzimage; then " \ + "if test -n $dtbfile; then " \ + "if run loadfdt; then " \ + "run mmcbootfdt;" \ + "fi;" \ + "fi;" \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + "run nandboot;" \ + +/* + * FLASH and environment organization + */ + +#ifdef CONFIG_BOOT_ONENAND +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_ENV_IS_IN_ONENAND 1 +#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ +#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET +#endif + +#ifdef CONFIG_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ +#define CONFIG_ENV_ADDR NAND_ENV_OFFSET +#endif + +/* + * SMSC911x Ethernet + */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 +#endif /* (CONFIG_CMD_NET) */ + +/* OneNAND boot config */ +#ifdef CONFIG_BOOT_ONENAND +#define CONFIG_SPL_ONENAND_SUPPORT +#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 +#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 +#define CONFIG_SPL_ONENAND_LOAD_SIZE \ + (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) + +#endif + +/* NAND boot config */ +#ifdef CONFIG_NAND +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif +#endif + +#endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 3dd6d32965..aeb385f5ff 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -5,7 +5,7 @@ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo * reference boards. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -15,9 +15,9 @@ * High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SYS_TEXT_BASE 0x80400000 @@ -117,12 +117,10 @@ /* * I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_OMAP34XX_I2C - -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 @@ -142,6 +140,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" @@ -264,7 +263,6 @@ */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* * Physical Memory Map @@ -278,16 +276,12 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#define CONFIG_SYS_FLASH_BASE ONENAND_MAP #endif /* Monitor at start of flash */ @@ -297,7 +291,6 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #endif diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 5526b4314f..bf1d34dedb 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -9,7 +9,7 @@ * * Configuration settings for the TI OMAP3530 Beagle board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -18,12 +18,11 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ @@ -126,12 +125,12 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 @@ -235,7 +234,6 @@ */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 3e018c00e8..c58636a541 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -7,137 +7,95 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ -#define CONFIG_OMAP3_OVERO /* working with overo */ -#define CONFIG_OMAP_GPIO - -#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define CONFIG_NAND -#include /* get chip and board defs */ -#include +#include -/* - * Display CPU and Board information - */ +/* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - +/* call misc_init_r */ #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG +/* pass the revision tag */ #define CONFIG_REVISION_TAG -#define CONFIG_OF_LIBFDT +/* override size of malloc() pool */ +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +/* Shift 128 << 15 provides 4 MiB heap to support UBI commands. + * Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15)) -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ +/* I2C Support */ +#define CONFIG_SYS_I2C_OMAP34XX -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +/* TWL4030 LED */ +#define CONFIG_TWL4030_LED -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 +/* USB EHCI */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION +/* Initialize GPIOs by default */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */ +#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */ +#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO Bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */ /* commands to include */ -#include - #define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_USB #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_IMLS /* List all found images */ #undef CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_NAND +#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */ +#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER -#define CONFIG_TWL4030_LED +#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ +#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ -/* - * Board NAND Info. +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ + +/* NAND block size is 128 KiB. Synchronize these values with + * overo_nand_partitions in mach-omap2/board-overo.c in Linux: + * xloader 4 * NAND_BLOCK_SIZE = 512 KiB + * uboot 14 * NAND_BLOCK_SIZE = 1792 KiB + * uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB + * linux 64 * NAND_BLOCK_SIZE = 8 MiB + * rootfs remainder */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "512k(xloader)," \ + "1792k(u-boot)," \ + "256k(environ)," \ + "8m(linux)," \ + "-(rootfs)" +#else /* CONFIG_NAND */ +#define MTDPARTS_DEFAULT +#endif /* CONFIG_NAND */ + +/* Board NAND Info. */ #define CONFIG_SYS_NAND_QUIET_TEST -#define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand */ - /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ - /* Environment information */ -#define CONFIG_BOOTDELAY 5 - #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ "console=ttyO2,115200n8\0" \ - "mpurate=500\0" \ + "mpurate=auto\0" \ "optargs=\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ @@ -147,6 +105,7 @@ "mmcrootfstype=ext3 rootwait\0" \ "nandroot=ubi0:rootfs ubi.mtd=4\0" \ "nandrootfstype=ubifs\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ "mpurate=${mpurate} " \ @@ -163,82 +122,68 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running boot script from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcbootfdt=echo Booting with DT from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ + "if nand read ${loadaddr} linux; then " \ + "bootm ${loadaddr};" \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" + "fi;" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "if run loadzimage; then " \ + "if test -z \"${fdtfile}\"; then " \ + "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ + "fi;" \ + "if run loadfdt; then " \ + "run mmcbootfdt;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "run nandboot; " \ -#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#undef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "Overo # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command */ - /* args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +/* FLASH and environment organization */ +#if defined(CONFIG_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ @@ -253,68 +198,20 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET +/* Configure SMSC9211 ethernet */ #if defined(CONFIG_CMD_NET) -/*---------------------------------------------------------------------------- - * SMSC9211 Ethernet from SMSC9118 family - *---------------------------------------------------------------------------- - */ - #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE 0x2C000000 - #endif /* (CONFIG_CMD_NET) */ -/* - * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader - * and older u-boot.bin with the new U-Boot SPL. - */ -#define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* Initial RAM setup */ #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - #define CONFIG_SYS_CACHELINE_SIZE 64 -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -/* move malloc and bss high to prevent clashing with the main image */ -#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -325,7 +222,14 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 3e8bd67d27..45feeb5773 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -4,7 +4,7 @@ * * Configuration settings for the OMAP3 Pandora. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -14,9 +14,9 @@ * High Level Configuration Options */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ @@ -110,10 +110,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 @@ -130,8 +130,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ @@ -200,7 +198,6 @@ */ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -222,15 +219,10 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 836a3d847d..ac307eb456 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -7,7 +7,7 @@ * * Configuration settings for the 3430 TI SDP3430 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,13 +16,13 @@ /* TODO: REMOVE THE FOLLOWING * Retained the following till size.h is removed in u-boot */ -#include +#include /* * High Level Configuration Options */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ @@ -113,10 +113,10 @@ /* * I2C for power management setup */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* OMITTED: single 1 Gbit MT29F1G NAND flash */ @@ -272,7 +272,6 @@ */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 36870459ef..c5d742c2bd 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -7,7 +7,7 @@ * * Configuration settings for the TI OMAP3430 Zoom MDK board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,14 +16,21 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ +#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SDRC /* The chip has SDRC controller */ - +#define CONFIG_NAND +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #include /* get chip and board defs */ #include +#include + +/* Remove SPL boot option - we do not support that on LDP yet */ +#undef CONFIG_SPL_FRAMEWORK +#undef CONFIG_SPL_OS_BOOT + +/* Generic NAND definition conflicts with debug_base */ +#undef CONFIG_SYS_NAND_BASE /* * Display CPU and Board information @@ -31,57 +38,16 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* * Hardware drivers */ -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 @@ -97,65 +63,59 @@ #define CONFIG_USBD_MANUFACTURER "Texas Instruments" #define CONFIG_USBD_PRODUCT_NAME "Zoom1" -/* commands to include */ -#include - -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ +#if defined(CONFIG_CMD_NAND) +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ +#endif #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP -#define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#undef CONFIG_SYS_I2C_OMAP24XX +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 */ -#define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 /* * Board NAND Info. */ -#define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Environment information */ -#define CONFIG_BOOTDELAY 10 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ + "fdtaddr=0x80f80000\0" \ + "bootfile=uImage\0" \ + "fdtfile=omap3-ldp.dtb\0" \ + "bootdir=/\0" \ + "bootpart=0:1\0" \ "usbtty=cdc_acm\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ "videomode=1024x768@60,vxres=1024,vyres=768\0" \ "videospec=omapfb:vram:2M,vram:4M\0" \ @@ -170,10 +130,15 @@ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "mmczboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ @@ -184,72 +149,29 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ + "else if run loadzimage; then " \ + "run mmczboot; " \ "else run nandboot; " \ - "fi; " \ + "fi; fi;" \ "fi; " \ "else run nandboot; fi" -#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) /* memtest */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_2 + \ 0x01F00000) /* 31MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ @@ -266,4 +188,12 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 +#ifdef CONFIG_CMD_NET +/* Ethernet (LAN9211 from SMSC9118 family) */ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE DEBUG_BASE + +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h deleted file mode 100644 index c57df8edb5..0000000000 --- a/include/configs/omap3_zoom2.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * Nishanth Menon - * Tom Rix - * - * Configuration settings for the TI OMAP3430 Zoom II board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ -#define CONFIG_OMAP_GPIO - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include /* get chip and board defs */ -#include - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - * Zoom2 uses the TL16CP754C on the debug board - */ -/* - * 0 - 1 : first USB with respect to the left edge of the debug board - * 2 - 3 : second USB with respect to the left edge of the debug board - */ -#define ZOOM2_DEFAULT_SERIAL_DEVICE 0 - -#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_REG_SIZE (-2) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200} - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* Status LED */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED 1 -#define STATUS_LED_BLUE 0 -#define STATUS_LED_RED 1 -/* Blue */ -#define STATUS_LED_BIT STATUS_LED_BLUE -#define STATUS_LED_STATE STATUS_LED_ON -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -/* Red */ -#define STATUS_LED_BIT1 STATUS_LED_RED -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -/* Optional value */ -#define STATUS_LED_BOOT STATUS_LED_BIT - -/* GPIO banks */ -#ifdef CONFIG_STATUS_LED -#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */ -#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */ -#endif -#define CONFIG_OMAP3_GPIO_3 /* board revision */ -#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */ - -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "Zoom2" - -/* commands to include */ -#include - -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ -#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#undef CONFIG_CMD_NFS /* NFS support */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 -#define CONFIG_TWL4030_LED 1 - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment information */ -#define CONFIG_BOOTDELAY 10 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" \ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # " -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -/* Memtest from start of memory to 31MB */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) -/* The default load address is the start of memory */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) -/* everything, incl board info, in Hz */ -#undef CONFIG_SYS_CLKS_IN_HZ -/* - * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_IS_IN_NAND 1 -#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h deleted file mode 100644 index 719cb83d9a..0000000000 --- a/include/configs/omap4_common.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments Incorporated. - * Aneesh V - * Steve Sakoman - * - * TI OMAP4 common configuration settings - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_OMAP4_COMMON_H -#define __CONFIG_OMAP4_COMMON_H - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP44XX 1 /* which is a 44XX */ -#define CONFIG_OMAP4430 1 /* which is in a 4430 */ -#define CONFIG_OMAP_GPIO - -/* Get CPU defs */ -#include -#include - -/* Display CPU and Board Info */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_MISC_INIT_R - -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - * Total Size Environment - 128k - * Malloc - add 256k - */ -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) -/* Vector Base */ -#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE - -/* - * Hardware drivers - */ - -/* - * serial port - NS16550 compatible - */ -#define V_NS16550_CLK 48000000 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -/* I2C */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 - -/* TWL6030 */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_TWL6030_POWER 1 -#endif - -/* MMC */ -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - - -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 - -/* Flash */ -#define CONFIG_SYS_NO_FLASH 1 - -/* commands to include */ -#include - -/* Enabled commands */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ - -/* Disabled commands */ -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -/* - * Environment setup - */ - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "fdt_high=0xffffffff\0" \ - "fdtaddr=0x80f80000\0" \ - "fdtfile=undefined\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "mmcboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "findfdt="\ - "if test $board_name = sdp4430; then " \ - "setenv fdtfile omap4-sdp.dtb; fi; " \ - "if test $board_name = panda; then " \ - "setenv fdtfile omap4-panda.dtb; fi;" \ - "if test $board_name = panda-a4; then " \ - "setenv fdtfile omap4-panda-a4.dtb; fi;" \ - "if test $board_name = panda-es; then " \ - "setenv fdtfile omap4-panda-es.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadbootenv; then " \ - "run importbootenv; " \ - "fi;" \ - "if test -n ${uenvcmd}; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "fi;" \ - "if run loadimage; then " \ - "run loadfdt;" \ - "run mmcboot; " \ - "fi; " \ - "fi" - -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 512 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* - * memtest setup - */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * SDRAM Memory Map - * Even though we use two CS all the memory - * is mapped to one contiguous block - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 1 -#define CONFIG_SYS_PL310_BASE 0x48242000 -#endif -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* Defines for SDRAM init */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x40304350 -#define CONFIG_SPL_MAX_SIZE (38 * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_DISPLAY_PRINT - -/* - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 80E7FFC0--0x80E80000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80E80000 - -/* - * BSS and malloc area 64MB into memory to allow enough - * space for the kernel at the beginning of memory - */ -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -#define CONFIG_SYS_THUMB_BUILD - -#endif /* __CONFIG_OMAP4_COMMON_H */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 18800f3cc1..7378acdb21 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -4,9 +4,9 @@ * Steve Sakoman * * Configuration settings for the TI OMAP4 Panda board. - * See omap4_common.h for OMAP4 common part + * See ti_omap4_common.h for OMAP4 common part * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_PANDA_H @@ -36,10 +36,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT_OMAP - -#include +#include #define CONFIG_CMD_NET /* GPIO */ @@ -48,8 +45,6 @@ /* ENV related config options */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_PROMPT "Panda # " - #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #endif /* __CONFIG_PANDA_H */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 3da78b6575..a83797454c 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -5,9 +5,9 @@ * Steve Sakoman * * Configuration settings for the TI SDP4430 board. - * See omap4_common.h for OMAP4 common part + * See ti_omap4_common.h for OMAP4 common part * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_SDP4430_H @@ -17,8 +17,9 @@ * High Level Configuration Options */ #define CONFIG_4430SDP 1 /* working with SDP */ +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP -#include +#include /* Battery Charger */ #ifndef CONFIG_SPL_BUILD @@ -31,6 +32,4 @@ #define CONFIG_ENV_OFFSET 0xE0000 #define CONFIG_CMD_SAVEENV -#define CONFIG_SYS_PROMPT "OMAP4430 SDP # " - #endif /* __CONFIG_SDP4430_H */ diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h deleted file mode 100644 index 75488de761..0000000000 --- a/include/configs/omap5912osk.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */ -#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */ - -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ -#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ - -/* input clock of PLL */ -/* the OMAP5912 OSK has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -/* -*/ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04800300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart - on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ - root=/dev/nfs rw nfsroot=157.87.82.48:\ - /home/mwd/myfs/target ip=dhcp" -#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ -#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ -#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ -#define CONFIG_BOOTFILE "uImage" /* file to load */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ - -#define PHYS_SRAM 0x20000000 - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h deleted file mode 100644 index 7dd56cfa78..0000000000 --- a/include/configs/omap5_common.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2013 - * Texas Instruments Incorporated. - * Sricharan R - * - * Derived from OMAP4 done by: - * Aneesh V - * - * TI OMAP5 AND DRA7XX common configuration settings - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_OMAP5_COMMON_H -#define __CONFIG_OMAP5_COMMON_H - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP54XX /* which is a 54XX */ -#define CONFIG_OMAP_GPIO - -/* Get CPU defs */ -#include -#include - -/* Display CPU and Board Info */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_MISC_INIT_R - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - * Total Size Environment - 128k - * Malloc - add 256k - */ -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) -/* Vector Base */ -#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE - -/* - * Hardware drivers - */ - -/* - * serial port - NS16550 compatible - */ -#define V_NS16550_CLK 48000000 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -/* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C -#define CONFIG_I2C_MULTI_BUS - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Flash */ -#define CONFIG_SYS_NO_FLASH - -/* Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_CACHELINE_SHIFT 6 - -/* commands to include */ -#include - -/* Enabled commands */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ - -/* Disabled commands */ -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -/* - * Environment setup - */ - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 - -#define CONFIG_ENV_OVERWRITE - -#ifndef PARTS_DEFAULT -#define PARTS_DEFAULT -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=" CONSOLEDEV ",115200n8\0" \ - "fdt_high=0xffffffff\0" \ - "fdtaddr=0x80f80000\0" \ - "fdtfile=undefined\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - "partitions=" PARTS_DEFAULT "\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "mmcboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "findfdt="\ - "if test $board_name = omap5_uevm; then " \ - "setenv fdtfile omap5-uevm.dtb; fi; " \ - "if test $board_name = dra7xx; then " \ - "setenv fdtfile dra7-evm.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadbootenv; then " \ - "run importbootenv; " \ - "fi;" \ - "if test -n ${uenvcmd}; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "fi;" \ - "if run loadimage; then " \ - "run loadfdt; " \ - "run mmcboot; " \ - "fi; " \ - "fi" - -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* - * memtest setup - */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * SDRAM Memory Map - * Even though we use two CS all the memory - * is mapped to one contiguous block - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -/* Defines for SDRAM init */ -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PALMAS_POWER -#endif - -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x40300350 -#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_DISPLAY_PRINT - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -/* - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 80E7FFC0--0x80E80000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80E80000 - -/* - * BSS and malloc area 64MB into memory to allow enough - * space for the kernel at the beginning of memory - */ -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SPL_GPIO_SUPPORT - -#endif /* __CONFIG_OMAP5_COMMON_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 9c045d3056..0ca4e82e0f 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -4,9 +4,9 @@ * Sricharan R * * Configuration settings for the TI EVM5430 board. - * See omap5_common.h for omap5 common settings. + * See ti_omap5_common.h for omap5 common settings. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_OMAP5_EVM_H @@ -17,15 +17,17 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" -#include +#include #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_SIZE (128 << 10) #define CONFIG_ENV_OFFSET 0xE0000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT @@ -34,12 +36,48 @@ /* Enhance our eMMC support / experience. */ #define CONFIG_CMD_GPT #define CONFIG_EFI_PARTITION -#define CONFIG_PARTITION_UUIDS -#define CONFIG_CMD_PART +#define CONFIG_HSMMC2_8BIT +#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_SYS_PROMPT "OMAP5432 uEVM # " +/* Required support for the TCA642X GPIO we have on the uEVM */ +#define CONFIG_TCA642X +#define CONFIG_CMD_TCA642X +#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 +#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 + +/* USB UHH support options */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80 +#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79 + +/* Enabled commands */ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ + +/* USB Networking options */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX #define CONSOLEDEV "ttyO2" +/* Max time to hold reset on this board, see doc/README.omap-reset-time */ #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 + +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + #endif /* __CONFIG_OMAP5_EVM_H */ diff --git a/include/configs/omap730.h b/include/configs/omap730.h deleted file mode 100644 index b54e0fb2da..0000000000 --- a/include/configs/omap730.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * OMAP730 hardware map - * - * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) - * Author: MPC-Data Limited - * Dave Peverley - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __INCLUDED_OMAP730_H -#define __INCLUDED_OMAP730_H - -#include - -/*************************************************************************** - * OMAP730 Configuration Registers - **************************************************************************/ - -#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000)) -#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000)) -#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002)) -#define DSP_CONF ((unsigned int)(0xFFFE1004)) -#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008)) -#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008)) -#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C)) -#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010)) -#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010)) -#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012)) -#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014)) -#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014)) -#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016)) -#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018)) -#define SPECCTL ((unsigned int)(0xFFFE101C)) -#define SPARE1 ((unsigned int)(0xFFFE1020)) -#define SPARE2 ((unsigned int)(0xFFFE1024)) -#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028)) -#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030)) -#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060)) -#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070)) -#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074)) -#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078)) -#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C)) -#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080)) -#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084)) -#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088)) -#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C)) -#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090)) -#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094)) -#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098)) -#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C)) -#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0)) -#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4)) -#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4)) -#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8)) -#define BIST_CONTROL ((unsigned int)(0xFFFE10C0)) -#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4)) -#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8)) -#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0)) -#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4)) -#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8)) -#define DEBUG1 ((unsigned int)(0xFFFE10E0)) -#define DEBUG2 ((unsigned int)(0xFFFE10E4)) -#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8)) - -/*************************************************************************** - * OMAP730 EMIFS Registers (TRM 2.5.7) - **************************************************************************/ - -#define TCMIF_BASE 0xFFFECC00 - -#define EMIFS_LRUREG (TCMIF_BASE + 0x04) -#define EMIFS_CONFIG (TCMIF_BASE + 0x0C) -#define FLASH_CFG_0 (TCMIF_BASE + 0x10) -#define FLASH_CFG_1 (TCMIF_BASE + 0x14) -#define FLASH_CFG_2 (TCMIF_BASE + 0x18) -#define FLASH_CFG_3 (TCMIF_BASE + 0x1C) -#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40) -#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28) -#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C) -#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30) -#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44) -#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48) -#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C) -#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50) -#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54) -#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58) -#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C) - -/*************************************************************************** - * OMAP730 Interrupt handlers - **************************************************************************/ - -#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */ -#define OMAP_IH2_BASE 0xfffe0000 - -/*************************************************************************** - * OMAP730 Timers - * - * There are three general purpose OS timers in the 730 that can be - * configured in autoreload or one-shot modes. - **************************************************************************/ - -#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000 - -/* 32k Timer Registers */ -#define TIMER32k_CR 0x08 -#define TIMER32k_TVR 0x00 -#define TIMER32k_TCR 0x04 - -/* 32k Timer Control Register definition */ -#define TIMER32k_TSS (1<<0) -#define TIMER32k_TRB (1<<1) -#define TIMER32k_INT (1<<2) -#define TIMER32k_ARL (1<<3) - -/* MPU Timer base addresses */ -#define OMAP730_MPUTIMER_BASE 0xfffec500 -#define OMAP730_MPUTIMER_OFF 0x00000100 - -#define OMAP730_TIMER1_BASE 0xFFFEC500 -#define OMAP730_TIMER2_BASE 0xFFFEC600 -#define OMAP730_TIMER3_BASE 0xFFFEC700 - -/* MPU Timer Register offsets */ -#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */ -#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */ -#define READ_TIM 0x08 /* MPU_READ_TIMER */ - -/* MPU_CNTL_TIMER register bits */ -#define MPUTIM_FREE (1<<6) -#define MPUTIM_CLOCK_ENABLE (1<<5) -#define MPUTIM_PTV_MASK (0x7< - * - * Configuation settings for the TI OMAP Perseus 2 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP730 1 /* which is in a 730 */ -#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */ - -/* - * Input clock of PLL - * The OMAP730 Perseus 2 has 13MHz input clock - */ - -#define CONFIG_SYS_CLK_FREQ 13000000 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -/* - * Size of malloc() pool - */ - -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (1) -#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart - * on perseus */ - -/* - * select serial console configuration - */ - -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp" - -#define CONFIG_LOADADDR 0x10000000 - -#define CONFIG_ETHADDR -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.23 -#define CONFIG_SERVERIP 192.150.0.100 -#define CONFIG_BOOTFILE "uImage" /* File to load */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The OMAP730 has 3 general purpose MPU timers, they can be driven by - * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a - * local divisor. - */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#if defined(CONFIG_CS0_BOOT) -#define PHYS_FLASH_1 0x0C000000 -#elif defined(CONFIG_CS3_BOOT) -#define PHYS_FLASH_1 0x00000000 -#else -#error Unknown Boot Chip-Select number -#endif - -#define PHYS_SRAM 0x20000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* ! __CONFIG_H */ diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 8fab6e63e3..b6f80af801 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -35,7 +35,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_OPENRD_BASE /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ @@ -49,6 +48,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_MII +#define CONFIG_CMD_MMC #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB @@ -76,6 +76,11 @@ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ #define CONFIG_ENV_ADDR 0x60000 #define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET /* * Default environment variables @@ -123,4 +128,11 @@ #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET #endif /*CONFIG_MVSATA_IDE*/ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MVEBU_MMC +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE +#endif /* CONFIG_CMD_MMC */ + #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h index dfe0258402..d4de3c3550 100644 --- a/include/configs/openrisc-generic.h +++ b/include/configs/openrisc-generic.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2011, Stefan Kristiansson, stefan.kristianssons@saunalahti.fi * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -55,7 +55,6 @@ /* * TIMER */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_OPENRISC_TMR_HZ 100 /* @@ -101,7 +100,6 @@ * MISC */ #define CONFIG_SYS_LONGHELP /* Provide extended help */ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ #define CONFIG_SYS_MAXARGS 16 /* Max command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ diff --git a/include/configs/origen.h b/include/configs/origen.h index da135740e4..8f1e25696e 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -6,119 +6,98 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_ORIGEN_H +#define __CONFIG_ORIGEN_H + +#include + +#define CONFIG_SYS_PROMPT "ORIGEN # " + /* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* SAMSUNG core */ -#define CONFIG_S5P 1 /* S5P Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F - -/* Keep L2 Cache Disabled */ -#define CONFIG_L2_OFF 1 #define CONFIG_SYS_DCACHE_OFF 1 +/* ORIGEN has 4 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* input clock of PLL: ORIGEN has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_TEXT_BASE 0x43E00000 #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - /* select serial console configuration */ -#define CONFIG_SERIAL2 1 /* use SERIAL 2 */ +#define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 -#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000 - -#define CONFIG_SKIP_LOWLEVEL_INIT -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -/* PWM */ -#define CONFIG_PWM 1 +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MONITOR_BASE 0x00000000 -/* Command definition*/ -#include +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 #undef CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* MMC SPL */ -#define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 - #define CONFIG_SPL_TEXT_BASE 0x02021410 -#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x40007000\0" \ + "rdaddr=0x48000000\0" \ + "kerneladdr=0x40007000\0" \ + "ramdiskaddr=0x48000000\0" \ + "console=ttySAC2,115200n8\0" \ + "mmcdev=0\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi;" \ + "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "ORIGEN # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_SYS_HZ 1000 - -/* ORIGEN has 4 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 4 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for ORIGEN" #define CONFIG_CLK_1000_400_200 @@ -126,13 +105,12 @@ /* MIU (Memory Interleaving Unit) */ #define CONFIG_MIU_2BIT_21_7_INTERLEAVED -#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_DOS_PARTITION 1 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) @@ -144,7 +122,4 @@ #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - #endif /* __CONFIG_H */ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h new file mode 100644 index 0000000000..9b902b5cad --- /dev/null +++ b/include/configs/ot1200.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2014 Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#include +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_MXC_GPIO + +/* FUSE Configs */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +/* UART Configs */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* SF Configs */ +#define CONFIG_CMD_SF +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + +/* IO expander */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* OCOTP Configs */ +#define CONFIG_CMD_IMXOTP +#define CONFIG_IMX_OTP +#define IMX_OTP_BASE OCOTP_BASE_ADDR +#define IMX_OTP_ADDR_MAX 0x7F +#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA +#define IMX_OTPWRITE_ENABLED + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_CMD_SATA +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0x5 +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 2 + +#define CONFIG_PREBOOT "" + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ +#define CONFIG_ENV_OFFSET (1024 * 1024) +/* M25P16 has an erase size of 64 KiB */ +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD + +/* FS Configs */ +#define CONFIG_CMD_EXT3 +#define CONFIG_CMD_EXT4 +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_LIB_UUID +#define CONFIG_CMD_FS_UUID + +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTFILE + +#endif /* __CONFIG_H */ diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 543209cb9d..2390bebf91 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -39,7 +39,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq */ /* Misc CPU related */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -175,7 +174,6 @@ #ifdef CONFIG_SYS_USE_DATAFLASH # define CONFIG_ATMEL_DATAFLASH_SPI # define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) # define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ # define AT91_SPI_CLK 15000000 @@ -194,8 +192,8 @@ # define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -# define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 -# define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 +# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif /* Ethernet */ @@ -207,6 +205,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT @@ -242,7 +241,6 @@ #endif -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 1b0be23dd3..5f27c2a41a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif @@ -34,7 +37,7 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020RDB) +#if defined(CONFIG_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1020 @@ -50,6 +53,45 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif +/* + * P1020RDB-PD board has user selectable switches for evaluating different + * frequency and boot options for the P1020 device. The table that + * follow describe the available options. The front six binary number was in + * accordance with SW3[1:6]. + * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off + * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off + * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off + * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off + * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off + * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off + * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off + */ +#if defined(CONFIG_P1020RDB_PD) +#define CONFIG_BOARDNAME "P1020RDB-PD" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_P1020 +#define CONFIG_SPI_FLASH +#define CONFIG_VSC7385_ENET +#define CONFIG_SLIC +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0x64 +#define __SW_BOOT_SPI 0x34 +#define __SW_BOOT_SD 0x24 +#define __SW_BOOT_NAND 0x44 +#define __SW_BOOT_PCIE 0x74 +#define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ + "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" +#endif + #if defined(CONFIG_P1021RDB) #define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC @@ -66,6 +108,24 @@ #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#endif #endif #if defined(CONFIG_P1024RDB) @@ -113,68 +173,124 @@ #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" #endif - -#if CONFIG_SYS_L2_SIZE >= (512 << 10) -/* must be 32-bit */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #ifdef CONFIG_NAND -#define CONFIG_SPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_TEXT_BASE 0xfffff000 +#define CONFIG_SPL_TEXT_BASE 0xff800000 #define CONFIG_SPL_MAX_SIZE 4096 - -#ifdef CONFIG_SYS_INIT_L2_ADDR -/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ -#define CONFIG_SYS_TEXT_BASE 0xf8f82000 -#define CONFIG_SPL_RELOC_TEXT_BASE \ - (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) -#define CONFIG_SPL_RELOC_STACK \ - (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START \ - (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE) -#else -#define CONFIG_SYS_TEXT_BASE 0x00201000 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#endif - -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif /* not CONFIG_TPL_BUILD */ + +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -192,7 +308,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 -#define CONFIG_MPC85xx #define CONFIG_MP @@ -252,14 +367,14 @@ #endif /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #undef CONFIG_FSL_DDR_INTERACTIVE -#ifdef CONFIG_P1020MBG +#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else @@ -330,7 +445,7 @@ /* * Local Bus Definitions */ -#if defined(CONFIG_P1020MBG) +#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 #elif defined(CONFIG_P1020UTM) @@ -381,13 +496,27 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND +#if defined(CONFIG_P1020RDB_PD) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#else #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) +#endif #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2< 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif @@ -757,6 +926,10 @@ #endif #endif +#if defined(CONFIG_P1020RDB_PD) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + #define CONFIG_MMC #ifdef CONFIG_MMC @@ -781,7 +954,6 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -791,7 +963,6 @@ /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ /* * For booting Linux, the board info and command line data @@ -803,7 +974,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h new file mode 100644 index 0000000000..9864c15d83 --- /dev/null +++ b/include/configs/p1_twr.h @@ -0,0 +1,623 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * QorIQ P1 Tower boards configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO +#if defined(CONFIG_TWR_P1025) +#define CONFIG_BOARDNAME "TWR-P1025" +#define CONFIG_P1025 +#define CONFIG_PHY_ATHEROS +#define CONFIG_QE +#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ +#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 + +#define CONFIG_MP + +#define CONFIG_FSL_ELBC +#define CONFIG_PCI +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_CMD_SATA +#define CONFIG_SATA_SIL3114 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LIBATA +#define CONFIG_LBA48 + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ + +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_SYS_FSL_DDR3 + +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* Default settings for DDR3 */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00220004 +#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 +#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 +#define CONFIG_SYS_DDR_MODE_1 0x80461320 +#define CONFIG_SYS_DDR_MODE_2 0x00008000 +#define CONFIG_SYS_DDR_INTERVAL 0x09480000 + +/* + * Memory map + * + * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable + * + * Localbus + * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable + * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable + * + * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable + * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ +#define CONFIG_SYS_FLASH_BASE 0xec000000 + +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ + | BR_PS_16 | BR_V) + +#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 + +#define CONFIG_SYS_SSD_BASE 0xe0000000 +#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE +#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ + BR_PS_16 | BR_V) +#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM +#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 +/* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +/* Size of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ + +/* Serial Port + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 + +/* + * I2C2 EEPROM + */ +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 + +#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 + +/* enable read and write access to EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#if defined(CONFIG_PCI) +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#undef CONFIG_TSEC2 +#undef CONFIG_TSEC2_NAME +#define CONFIG_TSEC3 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#undef CONFIG_HAS_ETH2 +#endif /* CONFIG_TSEC_ENET */ + +#ifdef CONFIG_QE +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#endif /* CONFIG_QE */ + +#ifdef CONFIG_TWR_P1025 +/* + * QE UEC ethernet configuration + */ +#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) + +#undef CONFIG_UEC_ETH +#define CONFIG_PHY_MODE_NEED_CHANGE + +#define CONFIG_UEC_ETH1 /* ETH1 */ +#define CONFIG_HAS_ETH0 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH1 */ + +#define CONFIG_UEC_ETH5 /* ETH5 */ +#define CONFIG_HAS_ETH1 + +#ifdef CONFIG_UEC_ETH5 +#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ +#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ +#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ +#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH5 */ +#endif /* CONFIG_TWR-P1025 */ + +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),5632k(kernel),57856k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" + +/* + * Environment + */ +#ifdef CONFIG_SYS_RAMBOOT +#ifdef CONFIG_RAMBOOT_SDCARD +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif +#endif + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ + || defined(CONFIG_FSL_SATA) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"netdev=eth0\0" \ +"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ +"loadaddr=1000000\0" \ +"bootfile=uImage\0" \ +"dtbfile=twr-p1025twr.dtb\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ +"kernelflash=tftpboot $loadaddr $bootfile; " \ + "protect off 0xefa80000 +$filesize; " \ + "erase 0xefa80000 +$filesize; " \ + "cp.b $loadaddr 0xefa80000 $filesize; " \ + "protect on 0xefa80000 +$filesize; " \ + "cmp.b $loadaddr 0xefa80000 $filesize\0" \ +"dtbflash=tftpboot $loadaddr $dtbfile; " \ + "protect off 0xefe80000 +$filesize; " \ + "erase 0xefe80000 +$filesize; " \ + "cp.b $loadaddr 0xefe80000 $filesize; " \ + "protect on 0xefe80000 +$filesize; " \ + "cmp.b $loadaddr 0xefe80000 $filesize\0" \ +"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ + "protect off 0xeeb80000 +$filesize; " \ + "erase 0xeeb80000 +$filesize; " \ + "cp.b $loadaddr 0xeeb80000 $filesize; " \ + "protect on 0xeeb80000 +$filesize; " \ + "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ +"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ + "protect off 0xefec0000 +$filesize; " \ + "erase 0xefec0000 +$filesize; " \ + "cp.b $loadaddr 0xefec0000 $filesize; " \ + "protect on 0xefec0000 +$filesize; " \ + "cmp.b $loadaddr 0xefec0000 $filesize\0" \ +"consoledev=ttyS0\0" \ +"ramdiskaddr=2000000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"fdtaddr=c00000\0" \ +"bdev=sda1\0" \ +"norbootaddr=ef080000\0" \ +"norfdtaddr=ef040000\0" \ +"ramdisk_size=120000\0" \ +"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ +"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" + +#define CONFIG_NFSBOOTCOMMAND \ +"setenv bootargs root=/dev/nfs rw " \ +"nfsroot=$serverip:$rootpath " \ +"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"tftp $loadaddr $bootfile&&" \ +"tftp $fdtaddr $fdtfile&&" \ +"bootm $loadaddr - $fdtaddr" + +#define CONFIG_HDBOOT \ +"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"usb start;" \ +"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ +"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ +"bootm $loadaddr - $fdtaddr" + +#define CONFIG_USB_FAT_BOOT \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs " \ +"ramdisk_size=$ramdisk_size;" \ +"usb start;" \ +"fatload usb 0:2 $loadaddr $bootfile;" \ +"fatload usb 0:2 $fdtaddr $fdtfile;" \ +"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ +"bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_USB_EXT2_BOOT \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs " \ +"ramdisk_size=$ramdisk_size;" \ +"usb start;" \ +"ext2load usb 0:4 $loadaddr $bootfile;" \ +"ext2load usb 0:4 $fdtaddr $fdtfile;" \ +"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ +"bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_NORBOOT \ +"setenv bootargs root=/dev/mtdblock3 rw " \ +"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ +"bootm $norbootaddr - $norfdtaddr" + +#define CONFIG_RAMBOOTCOMMAND_TFTP \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs " \ +"ramdisk_size=$ramdisk_size;" \ +"tftp $ramdiskaddr $ramdiskfile;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs " \ +"ramdisk_size=$ramdisk_size;" \ +"bootm 0xefa80000 0xeeb80000 0xefe80000" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h deleted file mode 100644 index d1c7a1a2d4..0000000000 --- a/include/configs/p3mx.h +++ /dev/null @@ -1,437 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on original work by - * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards - * - * The defines: - * CONFIG_P3M750 or - * CONFIG_P3M7448 - * are written into include/config.h by the "make xxx_config" command - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_P3Mx /* used for both board versions */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#if defined (CONFIG_P3M750) -#define CONFIG_750FX /* 750GL/GX/FX */ -#define CONFIG_HIGH_BATS /* High BATs supported */ -#define CONFIG_SYS_BOARD_NAME "P3M750" -#define CONFIG_SYS_BUS_CLK 100000000 -#define CONFIG_SYS_TCLK 100000000 -#elif defined (CONFIG_P3M7448) -#define CONFIG_74xx -#define CONFIG_SYS_BOARD_NAME "P3M7448" -#define CONFIG_SYS_BUS_CLK 133333333 -#define CONFIG_SYS_TCLK 133333333 -#endif -#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ - -/* which initialization functions to call for this board */ -#define CONFIG_SYS_BOARD_ASM_INIT 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#ifdef CONFIG_P3M750 -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#if defined (CONFIG_P3M750) -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */ -#define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */ -#elif defined (CONFIG_P3M7448) -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */ -#define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */ -#endif -#define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */ -#define CONFIG_SYS_MONITOR_BASE 0xfff00000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -#define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */ -#define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */ - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ - /* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x42000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_MPSC /* MV64460 Serial */ -#define CONFIG_MPSC_PORT 0 -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Ethernet - *----------------------------------------------------------------------*/ -/* Change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_SYS_ETH_PORT ETH_0 -#define MV_ETH_DEVS 2 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#if defined (CONFIG_P3M750) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */ -#elif defined (CONFIG_P3M7448) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ -#endif -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_MV64460_ECC - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */ - -/* I2C RTC */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#undef CONFIG_PCI /* include pci support */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ -#endif /* CONFIG_PCI */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI_IDSEL 0x30 - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "u-boot=p3mx/u-boot/u-boot.bin\0" \ - "load=tftp 100000 ${u-boot}\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "serverip=11.0.0.152\0" - -#if defined (CONFIG_P3M750) -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "hostname=p3m750\0" \ - "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc180000\0" \ - "vxfile=p3m750/vxWorks\0" \ - "vxuser=ddg\0" \ - "vxpass=ddg\0" \ - "vxtarget=target\0" \ - "vxflags=0x8\0" \ - "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ - "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ - "f=${vxflags}\0" -#elif defined (CONFIG_P3M7448) -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "hostname=p3m7448\0" -#endif - -#if defined (CONFIG_P3M750) -#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx" -#elif defined (CONFIG_P3M7448) -#define CONFIG_BOOTCOMMAND " " -#endif - -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_PCI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_SDRAM - - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * Marvell MV64460 config settings - *----------------------------------------------------------------------*/ -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */ -#if defined (CONFIG_P3M750) -#define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/ -#elif defined (CONFIG_P3M7448) -#define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */ -#endif - -/* - * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) - * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) - * MPP[2] NC - * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) - * MPP[4] PCI Monarch# GPIO IN Connected to P12 - * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) - * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 - * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 - * MPP[8] Reserved Do not use - * MPP[9] Reserved Do not use - * MPP[10] Reserved Do not use - * MPP[11] Reserved Do not use - * MPP[12] Phy 0 Interrupt Int IN - * MPP[13] Phy 1 Interrupt Int IN - * MPP[14] NC - * MPP[15] NC - * MPP[16] PCI Interrupt C Int IN Connected to P11 - * MPP[17] PCI Interrupt D Int IN Connected to P11 - * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] - * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic - * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog - * MPP[21] NC - * MPP[22] GP LED Green GPIO OUT - * MPP[23] GP LED Red GPIO OUT - * MPP[24] Watchdog NMI# Int OUT - * MPP[25] NC - * MPP[26] NC - * MPP[27] PCI Interrupt A Int IN Connected to P11 - * MPP[28] NC - * MPP[29] PCI Interrupt B Int IN Connected to P11 - * MPP[30] Module reset GPIO OUT Board reset - * MPP[31] PCI EReady GPIO IN Connected to P12 - */ -#define CONFIG_SYS_MPP_CONTROL_0 0x00303022 -#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 -#define CONFIG_SYS_MPP_CONTROL_2 0x00004000 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000004 -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* set rest out of range for Linux !!!!!!!!!!! */ - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ -#define CONFIG_SYS_L2 - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#ifndef __ASSEMBLY__ -#include <../board/Marvell/include/core.h> -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index c4c50932c3..225567bd90 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -4,7 +4,7 @@ * * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -20,7 +20,6 @@ #define CONFIG_P3P440 1 /* Board is P3P440 */ #define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -129,7 +128,7 @@ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ + "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/p3p440/uImage\0" \ "kernel_addr=ff800000\0" \ @@ -197,7 +196,6 @@ * Miscellaneous configurable options *----------------------------------------------------------------------*/ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -213,8 +211,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ @@ -306,6 +302,5 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif #endif /* __CONFIG_H */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 03020902bb..9480d8daf2 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -93,7 +93,6 @@ */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -104,8 +103,6 @@ #define CONFIG_SYS_LONGHELP #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " -#else -#define CONFIG_SYS_PROMPT "=> " #endif #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE \ @@ -118,7 +115,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* @@ -161,10 +157,10 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index d838356366..8abce1b425 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -95,7 +95,6 @@ */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -106,8 +105,6 @@ #define CONFIG_SYS_LONGHELP #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " -#else -#define CONFIG_SYS_PROMPT "=> " #endif #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE \ @@ -120,7 +117,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3686400 /* Timer @ 3686400 Hz */ #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ /* @@ -158,10 +154,10 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h index 2ab6fd2e8a..6490be5504 100644 --- a/include/configs/palmtreo680.h +++ b/include/configs/palmtreo680.h @@ -94,7 +94,6 @@ */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -107,7 +106,6 @@ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " #endif #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE \ @@ -120,7 +118,6 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* @@ -208,7 +205,6 @@ /* * SPL */ -#define CONFIG_SPL #define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */ #define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */ #define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 9e2686ac44..45bb47088b 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -17,14 +17,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" -/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-paz00 -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (Paz00) MOD # " #define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index cab9192de3..f920048555 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -12,26 +12,22 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_PB1X00 1 -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_PB1000 -#define CONFIG_SOC_AU1000 1 #else #ifdef CONFIG_PB1100 -#define CONFIG_SOC_AU1100 1 #else #ifdef CONFIG_PB1500 -#define CONFIG_SOC_AU1500 1 #else #error "No valid board set" #endif #endif #endif -#define CONFIG_SYS_LITTLE_ENDIAN - #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ @@ -66,8 +62,6 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ 396000000 -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index a608c872d5..31a93c87de 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -8,7 +8,7 @@ * (C) Copyright 2009 * Jon Smirl * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -20,8 +20,7 @@ High Level Configuration Options (easy to change) -----------------------------------------------------------------------------*/ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ #define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ /* FEC configuration and IDE */ @@ -364,7 +363,6 @@ RTC configuration #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 9b16c47820..c0bb227a33 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -19,37 +19,13 @@ #ifndef __CONFIG_PCM051_H #define __CONFIG_PCM051_H -#define CONFIG_AM33XX -#define CONFIG_OMAP - -#include - -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) +#include #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot# " -#define CONFIG_SYS_NO_FLASH #define MACH_TYPE_PCM051 4144 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_PCM051 -#define CONFIG_OF_LIBFDT -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* commands to include */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_VERSION_VARIABLE - /* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80007fc0\0" \ @@ -69,6 +45,9 @@ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ "bootenv=uEnv.txt\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ @@ -89,83 +68,42 @@ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot;" \ - "fi;" \ + "if run loadbootscript; then " \ + "run bootscript;" \ + "else " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi ;" \ "fi;" \ /* Clock Defines */ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_CMD_ECHO - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* * memtest works on 8 MB in DRAM after skipping 32MB from * start addr of ram disk */ -#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (64 << 20)) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + (8 * 1024 * 1024)) -#define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */ - -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -#define CONFIG_SPI -#define CONFIG_OMAP3_SPI -#define CONFIG_MTD_DEVICE #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 24000000 - /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 19) /* 512MiB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - /* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ - #define CONFIG_CONS_INDEX 1 /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ @@ -174,90 +112,31 @@ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* I2C Configuration */ -#define CONFIG_I2C -#define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_OMAP_GPIO - -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } /* CPU */ -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET - #define CONFIG_ENV_IS_NOWHERE -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -/* - * Place the image at the start of the ROM defined image space. - * We limit our size to the ROM-defined downloaded image area, and use the - * rest of the space for stack. - */ -#define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_YMODEM_SUPPORT #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL" #define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#ifdef CONFIG_SPI_BOOT #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80800000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -/* Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT #endif /* @@ -287,22 +166,9 @@ /* Unsupported features */ #undef CONFIG_USE_IRQ -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC #endif /* ! __CONFIG_PCM051_H */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 5de8e98aca..e6e06f2d2e 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -2,7 +2,7 @@ * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -23,7 +23,6 @@ #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 @@ -157,7 +156,7 @@ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ + "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/pcs440ep/uImage\0" \ "kernel_addr=FFF00000\0" \ @@ -276,7 +275,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -293,8 +291,6 @@ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CONFIG_LYNXKDI 1 /* support kdi files */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -430,7 +426,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 50321199c1..17d7bcab00 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -2,7 +2,7 @@ * (C) Copyright 2009-2010 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -13,6 +13,8 @@ #define __CONFIG_H #define CONFIG_PDM360NG 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD /* * Memory map for the PDM360NG board: @@ -30,7 +32,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ #define CONFIG_SYS_TEXT_BASE 0xF0000000 @@ -402,7 +403,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -417,7 +417,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Decrementer freq: 1ms ticks */ -#define CONFIG_SYS_HZ 1000 /* * For booting Linux, the board info and command line data @@ -443,7 +442,6 @@ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* POST support */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h deleted file mode 100644 index c664010067..0000000000 --- a/include/configs/pdnb3.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Configuation settings for the PDNB3 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ -#define CONFIG_PDNB3 1 /* on an PDNB3 board */ - -#define CONFIG_MACH_TYPE 1002 - -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ -#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ - -/* - * Ethernet - */ -#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ -#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -/* - * Misc configuration options - */ -#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ -#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_IXP_SERIAL -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ELF -#define CONFIG_CMD_PING - -#if !defined(CONFIG_SCPU) -#define CONFIG_CMD_NAND -#endif - - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ - -#define CONFIG_IXP425_TIMER_CLK 66666666 -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*************************************************************** - * Platform/Board specific defines start here. - ***************************************************************/ - -/*----------------------------------------------------------------------- - * Default configuration (environment varibles...) - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=pdnb3\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \ - "mtdparts=${mtdparts}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/buildroot\0" \ - "bootfile=/tftpboot/netbox/uImage\0" \ - "kernel_addr=50080000\0" \ - "ramdisk_addr=50200000\0" \ - "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \ - "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \ - "cp.b 100000 50000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "ipaddr=10.0.0.233\0" \ - "serverip=10.0.0.152\0" \ - "netmask=255.255.0.0\0" \ - "ethaddr=c6:6f:13:36:f3:81\0" \ - "eth1addr=c6:6f:13:36:f3:82\0" \ - "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \ - "4k@508k(renv)\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_FLASH_BASE 0x50000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#if defined(CONFIG_SCPU) -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ -#endif - -/* - * Expansion bus settings - */ -#if defined(CONFIG_SCPU) -#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */ -#else -#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */ -#endif -#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */ - -/* - * SDRAM settings - */ -#define CONFIG_SYS_SDR_CONFIG 0x18 -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a - -/* - * FLASH and environment organization - */ -#if defined(CONFIG_SCPU) -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ -#endif - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#if defined(CONFIG_SCPU) -/* no redundant environment on SCPU */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#else -#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -#if !defined(CONFIG_SCPU) -/* - * NAND-FLASH stuff - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ -#endif - -/* - * GPIO settings - */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/ -#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */ -#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */ -#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */ -#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */ - -/* other GPIO's */ -#define CONFIG_SYS_GPIO_RESTORE_INT 0 -#define CONFIG_SYS_GPIO_RESTART_INT 1 -#define CONFIG_SYS_GPIO_SYS_RUNNING 2 -#define CONFIG_SYS_GPIO_PCI_INTA 3 -#define CONFIG_SYS_GPIO_PCI_INTB 4 -#define CONFIG_SYS_GPIO_I2C_SCL 6 -#define CONFIG_SYS_GPIO_I2C_SDA 7 -#define CONFIG_SYS_GPIO_FPGA_RESET 9 -#define CONFIG_SYS_GPIO_CLK_33M 15 - -/* - * I2C stuff - */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL) -#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA) - -#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL) -#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \ - else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \ - else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL) -#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ - -/* - * I2C RTC - */ -#if 0 /* test-only */ -#define CONFIG_RTC_DS1340 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#else -/* M41T11 Serial Access Timekeeper(R) SRAM */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ -#endif - -/* - * Spartan3 FPGA configuration support - */ -#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */ - -#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/ -#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */ -#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */ -#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */ -#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h new file mode 100644 index 0000000000..a1c980d320 --- /dev/null +++ b/include/configs/peach-pi.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PEACH_PI_H +#define __CONFIG_PEACH_PI_H + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + +#include +#include + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_PROMPT "Peach-Pi # " +#define CONFIG_IDENT_STRING " for Peach-Pi" + +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +#define CONFIG_POWER_TPS65090_EC +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_DM_CROS_EC + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_PEACH_PI_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h new file mode 100644 index 0000000000..6516a72764 --- /dev/null +++ b/include/configs/peach-pit.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PEACH_PIT_H +#define __CONFIG_PEACH_PIT_H + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + +#include +#include + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_PROMPT "Peach-Pit # " +#define CONFIG_IDENT_STRING " for Peach-Pit" + +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +#define CONFIG_POWER_TPS65090_EC +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_DM_CROS_EC + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h new file mode 100644 index 0000000000..4684ad6852 --- /dev/null +++ b/include/configs/pengwyn.h @@ -0,0 +1,212 @@ +/* + * pengwyn.h + * + * Copyright (C) 2013 Lothar Felten + * + * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PENGWYN_H +#define __CONFIG_PENGWYN_H + +#define CONFIG_NAND +#define CONFIG_SERIAL1 +#define CONFIG_CONS_INDEX 1 + +#include + +/* Clock Defines */ +#define V_OSCK 24000000 +#define V_SCLK V_OSCK + +/* set env size */ +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=am335x-pengwyn.dtb\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcloados=run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr};\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt;" \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} u-boot-spl-os; " \ + "nand read ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot;" \ + "run nandboot;" + +/* NS16550 Configuration: primary UART via FDTI */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CONFIG_BAUDRATE 115200 + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* General network SPL */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3),1792k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env),5m(kernel),-(rootfs)" +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* un-assigned */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support. + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#if defined(CONFIG_MUSB_HOST) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_SPL_BUILD) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* Disable CPSW SPL support so we fit within the 101KiB limit. */ +#undef CONFIG_SPL_ETH_SUPPORT +#endif + +/* Network */ +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_NATSEMI + +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* ! __CONFIG_PENGWYN_H */ diff --git a/include/configs/pepper.h b/include/configs/pepper.h new file mode 100644 index 0000000000..cc153abaa9 --- /dev/null +++ b/include/configs/pepper.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PEPPER_H +#define __CONFIG_PEPPER_H + +#define CONFIG_MMC +#include + +#undef CONFIG_BOARD_LATE_INIT +#undef CONFIG_SPL_OS_BOOT + +/* Clock defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "pepper# " + +/* Mach type */ +#define MACH_TYPE_PEPPER 4207 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_IS_NOWHERE +/* Display cpuinfo */ +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=am335x-pepper.dtb\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ + "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \ + "uimageboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "ubiboot=echo Booting from nand (ubifs) ...; " \ + "run ubiargs; run ubiload; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmcload; then " \ + "run mmcboot;" \ + "fi;" \ + "if run loaduimage; then " \ + "run uimageboot;" \ + "fi;" \ + "fi;" \ + +/* Serial console configuration */ +#define CONFIG_CONS_INDEX 1 /* UART0 */ +#define CONFIG_SERIAL1 1 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 + +/* Ethernet support */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_PHY_RESET_DELAY 1000 + +/* SPL */ +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* __CONFIG_PEPPER_H */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h deleted file mode 100644 index 027ddd2d98..0000000000 --- a/include/configs/pf5200.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * (c) 2005 esd gmbh Hannover - * - * - * from IceCube.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - *************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ -#define CONFIG_PF5200 1 /* ... on PF5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#if 0 /* test-only */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#else -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ -#endif -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#if 0 /* test-only !!! */ -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 0 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE - -#define CONFIG_CMD_PCI - - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#endif -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to ParaFinder pf5200;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ - "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ - "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ - "loadaddr=01000000\0" \ - "serverip=192.168.2.99\0" \ - "gatewayip=10.0.0.79\0" \ - "user=mu\0" \ - "target=pf5200.esd\0" \ - "script=pf5200.bat\0" \ - "image=/tftpboot/vxWorks_pf5200\0" \ - "ipaddr=10.0.13.196\0" \ - "netmask=255.255.0.0\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_vxworks0" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#if 1 /* test-only */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 -#else -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ - /* total size of a CAT24WC32 is 8192 bytes */ -#define CONFIG_ENV_OVERWRITE 1 -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_UDP_CHECKSUM 1 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00 - -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS1_START 0xfd000000 -#define CONFIG_SYS_CS1_SIZE 0x00010000 -#define CONFIG_SYS_CS1_CFG 0x10101410 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -/*----------------------------------------------------------------------- - * CPLD stuff - */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* CPLD program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ - -#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ -#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ - -#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00) -#define JTAG_GPIO_CFG_SET 0x00000000 -#define JTAG_GPIO_CFG_RESET 0x00F00000 - -#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04) -#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TMS_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C) -#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00) -#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TCK_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08) -#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00) -#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDI_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08) -#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ -#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04) -#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDO_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C) -#define JTAG_GPIO_TDO_DDR_SET 0x00000000 -#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index a473f232f3..b663b89d2c 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -12,11 +12,6 @@ #include "tegra20-common.h" -/* Enable fdt support for Plutux. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-plutux -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (Plutux) # " #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 67b40b2fcc..10415d31a5 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -20,6 +20,8 @@ #include /* ARM asynchronous clock */ +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_DISPLAY_BOARDINFO #define MASTER_PLL_DIV 15 @@ -28,8 +30,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ #define CONFIG_ARCH_CPU_INIT @@ -52,15 +52,13 @@ #define CONFIG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2 | \ - AT91_PMC_MCKR_PLLADIV_1) + AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2 | \ - AT91_PMC_MCKR_PLLADIV_1) + AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 @@ -168,9 +166,9 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIO_PORTC, 12 -#define CONFIG_GREEN_LED AT91_PIO_PORTC, 13 -#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15 +#define CONFIG_RED_LED GPIO_PIN_PC(12) +#define CONFIG_GREEN_LED GPIO_PIN_PC(13) +#define CONFIG_YELLOW_LED GPIO_PIN_PC(15) #define CONFIG_BOOTDELAY 3 @@ -206,7 +204,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ @@ -223,8 +220,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16 +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) /* NOR flash */ #define CONFIG_SYS_FLASH_CFI 1 @@ -245,6 +242,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 2b4335e78e..f6aebf4e4a 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -18,6 +18,8 @@ */ #include +#define CONFIG_SYS_GENERIC_BOARD + /* ARM asynchronous clock */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -28,8 +30,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ #define CONFIG_ARCH_CPU_INIT @@ -181,8 +181,8 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */ +#define CONFIG_RED_LED GPIO_PIN_PB(7) /* this is the power led */ +#define CONFIG_GREEN_LED GPIO_PIN_PB(8) /* this is the user1 led */ #define CONFIG_BOOTDELAY 3 @@ -218,7 +218,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 @@ -243,8 +242,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30 +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) #endif @@ -272,6 +271,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 7d16bd8b25..a8dc0f0b03 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -22,6 +22,8 @@ */ #include +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" @@ -31,7 +33,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0x73f00000 #define CONFIG_ARCH_CPU_INIT @@ -55,8 +56,8 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIO_PORTD, 31 /* this is the user1 led */ -#define CONFIG_GREEN_LED AT91_PIO_PORTD, 0 /* this is the user2 led */ +#define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */ +#define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */ #define CONFIG_BOOTDELAY 3 @@ -107,8 +108,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3 +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3) #endif @@ -120,6 +121,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index a81d452194..89560ad1c5 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -13,6 +13,8 @@ #ifndef _CONFIG_POGO_E02_H #define _CONFIG_POGO_E02_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Machine type definition and ID */ @@ -24,7 +26,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h deleted file mode 100644 index 3f9fdd444d..0000000000 --- a/include/configs/ppmc7xx.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * ppmc7xx.h - * --------- - * - * Wind River PPMC 7xx/74xx board configuration file. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPMC7XX - - -/*=================================================================== - * - * User configurable settings - Modify to your preference - * - *=================================================================== - */ - -/* - * Debug - * - * DEBUG - Define this is you want extra debug info - * GTREGREAD - Required to build with debug - * do_bdinfo - Required to build with debug - */ - -#ifdef DEBUG -#define GTREGREAD(x) 0xFFFFFFFF -#define do_bdinfo(a,b,c,d) -#endif - -/* - * CPU type - * - * CONFIG_7xx - We have a 750 or 755 CPU - * CONFIG_74xx - We have a 7400 CPU - * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) - * CONFIG_BUS_CLK - System bus clock in Hz - */ - -#define CONFIG_7xx -#undef CONFIG_74xx -#undef CONFIG_ALTIVEC -#define CONFIG_BUS_CLK 66000000 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#ifndef __ASSEMBLY__ -#include -#endif - -/* - * Monitor configuration - * - * List of command sets to include in shell - * - * The following command sets have been tested and known to work: - * - * CMD_CACHE - Cache control commands - * CMD_MEMORY - Memory display, change and test commands - * CMD_FLASH - Erase and program flash - * CMD_ENV - Environment commands - * CMD_RUN - Run commands stored in env vars - * CMD_ELF - Load ELF files - * CMD_NET - Networking/file download commands - * CMD_PIN - ICMP Echo Request command - * CMD_PCI - PCI Bus scanning command - */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_RUN -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_PCI - -#undef CONFIG_CMD_KGDB - - -/* - * Serial configuration - * - * CONFIG_CONS_INDEX - Serial console port number (COM1) - * CONFIG_BAUDRATE - Serial speed - */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - - -/* - * PCI config - * - * CONFIG_PCI - Enable PCI bus - * CONFIG_PCI_PNP - Enable Plug & Play support - * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup - */ - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW - - -/* - * Network config - * - * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller - * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM - */ - -#define CONFIG_EEPRO100 -#define CONFIG_EEPRO100_SROM_WRITE - - -/* - * Enable extra init functions - * - * CONFIG_MISC_INIT_F - Call pre-relocation init functions - * CONFIG_MISC_INIT_R - Call post relocation init functions - */ - -#undef CONFIG_MISC_INIT_F -#define CONFIG_MISC_INIT_R - - -/* - * Boot config - * - * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot - * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) - */ - -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm" -#define CONFIG_BOOTDELAY 5 - - -/*=================================================================== - * - * Board configuration settings - You should not need to modify these - * - *=================================================================== - */ - - -/* - * Memory map - * - * This board runs in a standard CHRP (Map-B) configuration. - * - * Type Start End Size Width Chip Sel - * ----------- ----------- ----------- ------- ------- -------- - * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 - * User LED's 0x78000000 RCS3 - * UART 0x7C000000 RCS2 - * Mailbox 0xFF000000 RCS1 - * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 - * - * Flash sectors are laid out as follows. - * - * Sector Start End Size Comments - * ------- ----------- ----------- ------- ----------- - * 0 0xFFC00000 0xFFC3FFFF 256KB - * 1 0xFFC40000 0xFFC7FFFF 256KB - * 2 0xFFC80000 0xFFCBFFFF 256KB - * 3 0xFFCC0000 0xFFCFFFFF 256KB - * 4 0xFFD00000 0xFFD3FFFF 256KB - * 5 0xFFD40000 0xFFD7FFFF 256KB - * 6 0xFFD80000 0xFFDBFFFF 256KB - * 7 0xFFDC0000 0xFFDFFFFF 256KB - * 8 0xFFE00000 0xFFE3FFFF 256KB - * 9 0xFFE40000 0xFFE7FFFF 256KB - * 10 0xFFE80000 0xFFEBFFFF 256KB - * 11 0xFFEC0000 0xFFEFFFFF 256KB - * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here - * 13 0xFFF40000 0xFFF7FFFF 256KB - * 14 0xFFF80000 0xFFFBFFFF 256KB - * 15 0xFFFC0000 0xFFFDFFFF 128KB - * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here - * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here - * 18 0xFFFF0000 0xFFFFFFFF 64KB - */ - - -/* - * SDRAM config - see memory map details above. - * - * CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! - * CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) - */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - - -/* - * Flash config - see memory map details above. - * - * CONFIG_SYS_FLASH_BASE - Start address of flash memory - * CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem - * CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms - * CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms - * CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board - * CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank - */ - -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 -#define CONFIG_SYS_FLASH_ERASE_TOUT 250000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 5000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - - -/* - * Monitor config - see memory map details above - * - * CONFIG_SYS_MONITOR_BASE - Base address of monitor code - * CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB) - */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x20000 - - -/* - * Command shell settings - * - * CONFIG_SYS_BARGSIZE - Boot Argument buffer size - * CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB) - * CONFIG_SYS_CBSIZE - Console Buffer (input) size - * CONFIG_SYS_LOAD_ADDR - Default load address - * CONFIG_SYS_LONGHELP - Provide more detailed help - * CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands - * CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM - * CONFIG_SYS_MEMTEST_END - End address of RAM test - * CONFIG_SYS_PBSIZE - Print Buffer (output) size - * CONFIG_SYS_PROMPT - Prompt string - */ - -#define CONFIG_SYS_BARGSIZE 1024 -#define CONFIG_SYS_BOOTMAPSZ 0x800000 -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MEMTEST_START 0x00040000 -#define CONFIG_SYS_MEMTEST_END 0x00040100 -#define CONFIG_SYS_PBSIZE 1024 -#define CONFIG_SYS_PROMPT "=> " - - -/* - * Environment config - see memory map details above - * - * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash - * CONFIG_ENV_ADDR - Address of the sector containing env vars - * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB) - * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB) - */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFFE0000 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000 -#define CONFIG_ENV_SIZE_REDUND 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x8000 - - -/* - * Initial RAM config - * - * Since the main system RAM is initialised very early, we place the INIT_RAM - * in the main system RAM just above the exception vectors. The contents are - * copied to top of RAM by the init code. - * - * CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect - * CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM - * GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data - * CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack - */ - -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000) -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/* - * Initial BAT config - * - * BAT0 - System SDRAM - * BAT1 - LED's and Serial Port - * BAT2 - PCI Memory - * BAT3 - PCI I/O including Flash Memory - */ - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - - -/* - * Cache config - * - * CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific) - * CONFIG_SYS_L2 - L2 cache enabled if defined - * L2_INIT - L2 cache init flags - * L2_ENABLE - L2 cache enable flags - */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#undef CONFIG_SYS_L2 -#define L2_INIT 0 -#define L2_ENABLE 0 - - -/* - * Clocks config - * - * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz - * CONFIG_SYS_HZ - Decrementer freq in Hz - */ - -#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK -#define CONFIG_SYS_HZ 1000 - - -/* - * Serial port config - * - * CONFIG_SYS_NS16550 - Include the NS16550 driver - * CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver - * CONFIG_SYS_NS16550_CLK - Frequency of reference clock - * CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port - * CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port - */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 3686400 -#define CONFIG_SYS_NS16550_REG_SIZE -8 -#define CONFIG_SYS_NS16550_COM1 0x7C000000 - - -/* - * PCI Config - Address Map B (CHRP) - */ - -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000 -#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000 -#define CONFIG_SYS_ISA_MEM_BUS 0x00000000 -#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000 -#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000 -#define CONFIG_SYS_PCI_IO_BUS 0x00800000 -#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000 -#define CONFIG_SYS_PCI_IO_SIZE 0x00400000 -#define CONFIG_SYS_ISA_IO_BUS 0x00000000 -#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000 -#define CONFIG_SYS_ISA_IO_SIZE 0x00800000 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS - - -/* - * Extra init functions - * - * CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code - */ - -#define CONFIG_SYS_BOARD_ASM_INIT - -#endif /* __CONFIG_H */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h deleted file mode 100644 index 7cf12ba0f6..0000000000 --- a/include/configs/ppmc8260.h +++ /dev/null @@ -1,989 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * Configuation settings for the WindRiver PPMC8260 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x2 0x2 33 133 133 Close Open Close - * 0x2 0x3 33 133 166 Close Open Open - * 0x2 0x4 33 133 200 Open Close Close - * 0x2 0x5 33 133 233 Open Close Open - * 0x2 0x6 33 133 266 Open Open Close - * - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CONFIG_SYS_PPMC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_PPMC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CONFIG_SYS_FLASH0_BASE 0xFE000000 -#define CONFIG_SYS_FLASH0_SIZE 16 - -/* What should be the base address of the first SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 128 - -/* What should be the base address of the second SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM1_BASE 0x08000000 -#define CONFIG_SYS_SDRAM1_SIZE 128 - -/* What should be the base address of the on board SDRAM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM2_BASE 0x38000000 -#define CONFIG_SYS_SDRAM2_SIZE 16 - -/* What should be the base address of the MAILBOX and how big is it - * (in Bytes) - * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000 - */ -#define CONFIG_SYS_MAILBOX_BASE 0x32000000 -#define CONFIG_SYS_MAILBOX_SIZE 8192 - -/* What is the base address of the I/O select lines and how big is it - * (In Mbytes)? - */ - -#define CONFIG_SYS_IOSELECT_BASE 0xE0000000 -#define CONFIG_SYS_IOSELECT_SIZE 32 - - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CONFIG_SYS_LED_BASE 0xF1000000 - -/* - * PPMC8260 with 256 16 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x0FF5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x0FF5 FFB0 Board Info Data - * 0x0FF6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 256k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x0FFC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x0FFF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - * The console can be on SMC1 or SMC2 - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ - -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT 1 - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 9600 - -/* Ethernet MAC address */ - -#define CONFIG_ETHADDR 00:a0:1e:90:2b:00 - -/* Define this to set the last octet of the ethernet address - * from the DS0-DS7 switch and light the leds with the result - * The DS0-DS7 switch and the leds are backwards with respect - * to each other. DS7 is on the board edge side of both the - * led strip and the DS0-DS7 switch. - */ -#define CONFIG_MISC_INIT_R - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#if 0 -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -# define CONFIG_AUTOBOOT_KEYED -# define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds, press \" \" to stop\n", bootdelay -# define CONFIG_AUTOBOOT_STOP_STR " " -# undef CONFIG_AUTOBOOT_DELAY_STR -# define DEBUG_BOOTKEYS 0 -#endif - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS - - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_MEMTEST -#define CONFIG_CMD_MII -#define CONFIG_CMD_IMMAP - -#undef CONFIG_CMD_KGDB - - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xf0000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ - - CONFIG_SYS_MEM_END_USAGE ) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -/* - * Attention: This is board specific - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\ - CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) -/* - * Attention: this is board-specific - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_PPMC_BOOT_LOW) -# define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PPMC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER ( HRCW_EBM | \ - HRCW_BPS11 | \ - HRCW_L2CPC10 | \ - HRCW_DPPC00 | \ - CONFIG_SYS_PPMC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC00 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \ - CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE 0x0ff80000 -#endif - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - - -#ifndef CONFIG_SYS_RAMBOOT - -# define CONFIG_ENV_IS_IN_FLASH 1 -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ - -#else -# define CONFIG_ENV_IS_IN_FLASH 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_SECT_SIZE 0x40000 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_EBM |\ - 0x30000000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - * Ref Section 4.3.2.6 page 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_ESE |\ - SIUMCR_DPPC00 |\ - SIUMCR_L2CPC10 |\ - SIUMCR_LBPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC00 |\ - SIUMCR_BCTLC00 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) * - * 1 unused - * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB) - * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB) - * 4 Local SDRAM 32 bit SDRAM (on board - 16MB) - * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB) - * 6 60x GPCM 8 bit FLASH (on board - 2MB) * - * 7 60x GPCM 8 bit LEDs, switches - * - * (*) This configuration requires the PPMC8260 be configured - * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to - * the on board FLASH. In other words, JP24 should have - * pins 1 and 2 jumpered and pins 3 and 4 jumpered. - * - */ - -/*----------------------------------------------------------------------- - * BR0,BR1 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0,OR1 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0,1 - FLASH SIMM - * - * This expects the FLASH SIMM to be connected to *CS0 - * It consists of 4 AM29F080B parts. - * - * Note: For the 4 MB SIMM, *CS1 is unused. - */ - -/* BR0 is configured as follows: - * - * - Base address of 0xFE000000 - * - 32 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 32 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 2,3 - 128 MB SDRAM DIMM - */ - -/* With a 128 MB DIMM, the BR2 is configured as follows: - * - * - Base address of 0x00000000/0x08000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 128 MB DIMM, the OR2 is configured as follows: - * - * - 128 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 13 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -/* With a 128 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Normal Operation - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A13-A15 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - External Address Multiplexing enabled - * - CAS Latency is 2. - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - -#define CONFIG_SYS_PSRT 0x0e -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 - - -/*----------------------------------------------------------------------- - * BR4 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR4 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 4 - On board SDRAM - * - */ -/* With 16 MB of onboard SDRAM BR4 is configured as follows - * - * - Base address 0x38000000 - * - 32 bit port size - * - Data error checking disabled - * - Read/Write access - * - SDRAM local bus - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - * - */ - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_DECC_NONE |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -/* - * With 16MB SDRAM, OR4 is configured as follows - * - 4 internal banks per device - * - Row start address bit is A10 with LSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ - -#define CONFIG_SYS_OR4_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A10 |\ - ORxS_NUMR_12) - - -/*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register - * Ref: Section 10.3.4 on page 10-24 - *----------------------------------------------------------------------- - */ - -/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Normal Operation - * - Address Multiplexing where A5 is output on A13 pin - * (A6 on A15, and so on), - * - use address pins A15-A17 as bank select, - * - A11 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 2 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - SDRAM burst length is 8 - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - External Address Multiplexing disabled - * - CAS Latency is 2. - */ -#define CONFIG_SYS_LSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A11 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_LSRT 0x0e - -/*----------------------------------------------------------------------- - * BR5 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR5 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 5 EEProm and Mailbox - * - * The EEPROM and mailbox live on the same chip select. - * the eeprom is selected if the MSb of the address is set and the mailbox is - * selected if the MSb of the address is clear. - * - */ - -/* BR5 is configured as follows: - * - * - Base address of 0x32000000/0xF2000000 - * - 8 bit - * - Data error checking disabled - * - Read/Write access - * - GPCM 60x Bus - * - SDRAM local bus - * - No data pipelining is done - * - Valid - */ - -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) -/* OR5 is configured as follows - * - buffer control enabled - * - chip select negated normally - * - CS output 1/2 clock after address - * - 15 wait states - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ - -#define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR6 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR6 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 6 - I/O select - * - */ - -/* BR6 is configured as follows: - * - * - Base address of 0xE0000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR6 is configured as follows - * - buffer control enabled - * - chip select negated normally - * - CS output 1/2 clock after address - * - 15 wait states - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ - -#define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - - -/*----------------------------------------------------------------------- - * BR7 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR7 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 7 - LEDs and switches - * - * LEDs are at 0x00001 (write only) - * switches are at 0x00001 (read only) - */ -#ifdef CONFIG_SYS_LED_BASE - -/* BR7 is configured as follows: - * - * - Base address of 0xA0000000 - * - 8 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR7 is configured as follows: - * - * - 1 byte - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 15 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* CONFIG_SYS_LED_BASE */ -#endif /* __CONFIG_H */ diff --git a/include/configs/pr1.h b/include/configs/pr1.h index 03d4269584..13fb675a5f 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -102,8 +102,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C -#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -136,7 +136,6 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_LOADADDR 0x2000000 - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h index e5e801508e..f0ecc34587 100644 --- a/include/configs/pxa-common.h +++ b/include/configs/pxa-common.h @@ -3,7 +3,7 @@ * * Copyright (C) 2010 Marek Vasut * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_PXA_COMMON_H__ @@ -16,7 +16,6 @@ */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 -#define CONFIG_KGDB_SER_INDEX 2 #endif /* diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index cd3dd763f7..af7c076df0 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -13,7 +13,7 @@ * Cliff Brake * Configuation settings for the Accelent/Vibren PXA255 IDP * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -199,7 +199,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -211,7 +210,6 @@ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ #else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #endif #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ @@ -224,7 +222,6 @@ #define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ #define RTC 1 /* enable 32KHz osc */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h new file mode 100644 index 0000000000..946b2c85e9 --- /dev/null +++ b/include/configs/pxm2.h @@ -0,0 +1,157 @@ +/* + * siemens pxm2 + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PXM2_H +#define __CONFIG_PXM2_H + +#define CONFIG_SIEMENS_PXM2 +#define MACH_TYPE_PXM2 4309 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2 + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 720 +#define DDR_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 266 + +#define BOARD_DFU_BUTTON_GPIO 59 +#define BOARD_DFU_BUTTON_LED 117 +#define BOARD_LCD_POWER 111 +#define BOARD_BACK_LIGHT 112 +#define BOARD_TOUCH_POWER 57 + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_PHY_ATHEROS + +#define CONFIG_FACTORYSET + +/* UBI Support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=pxm2\0" \ + "nand_img_size=0x500000\0" \ + "optargs=\0" \ + "splashpos=m,m\0" \ + CONFIG_COMMON_ENV_SETTINGS \ + "mmc_dev=0\0" \ + "mmc_root=/dev/mmcblk0p2 rw\0" \ + "mmc_root_fs_type=ext4 rootwait\0" \ + "mmc_load_uimage=" \ + "mmc rescan; " \ + "setenv bootfile uImage;" \ + "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ + "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "mmc_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_root} ${mtdparts}" \ + "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ + "eth=${ethaddr} " \ + "\0" \ + "mmc_boot=run mmc_args; " \ + "run mmc_load_uimage; " \ + "bootm ${kloadaddr}\0" \ + "" + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ + "if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ + "fi; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmc_dev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmc_load_uimage; then " \ + "run mmc_args;" \ + "bootm ${kloadaddr};" \ + "fi;" \ + "fi;" \ + "run nand_boot;" \ + "reset;" + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_VIDEO +#if defined(CONFIG_VIDEO) +#define CONFIG_VIDEO_DA8XX +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_BMP +#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE +#define PWM_TICKS 0x1388 +#define PWM_DUTY 0x200 +#define CONFIG_SYS_CONSOLE_BG_COL 0xff +#define CONFIG_SYS_CONSOLE_FG_COL 0x00 +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_FIT +#endif + +#endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/qemu-malta.h b/include/configs/qemu-malta.h deleted file mode 100644 index 4e7ad33230..0000000000 --- a/include/configs/qemu-malta.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2013 Gabor Juhos - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _QEMU_MALTA_CONFIG_H -#define _QEMU_MALTA_CONFIG_H - -#include -#include - -/* - * System configuration - */ -#define CONFIG_QEMU_MALTA - -#define CONFIG_PCI -#define CONFIG_PCI_GT64120 -#define CONFIG_PCI_PNP -#define CONFIG_PCNET - -/* - * CPU Configuration - */ -#define CONFIG_SYS_MHZ 250 /* arbitrary value */ -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_DCACHE_SIZE 16384 /* arbitrary value */ -#define CONFIG_SYS_ICACHE_SIZE 16384 /* arbitrary value */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* arbitrary value */ - -#define CONFIG_SWAP_IO_SPACE - -/* - * Memory map - */ -#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ -#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) - -/* - * Console configuration - */ -#if defined(CONFIG_SYS_LITTLE_ENDIAN) -#define CONFIG_SYS_PROMPT "qemu-maltael # " -#else -#define CONFIG_SYS_PROMPT "qemu-malta # " -#endif - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 - -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING - -/* - * Serial driver - */ -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 115200 -#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_UART_BASE) -#define CONFIG_CONS_INDEX 1 - -/* - * Environment - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Commands - */ -#include - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NFS - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING - -#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */ - -#endif /* _QEMU_MALTA_CONFIG_H */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index c3a69c5327..1548d3e682 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -12,8 +12,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 /* MIPS32 CPU core */ #define CONFIG_QEMU_MIPS + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ @@ -106,8 +108,6 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_HZ 1000 - /* Cached addr */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 7267a8115e..61cafadd7c 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -12,8 +12,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS64 /* MIPS64 CPU core */ #define CONFIG_QEMU_MIPS + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ @@ -108,8 +110,6 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_HZ 1000 - /* Cached addr */ #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h new file mode 100644 index 0000000000..763a47ac3d --- /dev/null +++ b/include/configs/qemu-ppce500.h @@ -0,0 +1,207 @@ +/* + * Copyright 2011-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Corenet DS style board configuration file + */ +#ifndef __QEMU_PPCE500_H +#define __QEMU_PPCE500_H + +#define CONFIG_CMD_REGINFO + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_QEMU_E500 + +#undef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */ +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_MPC85XX_NO_RESETVEC + +#define CONFIG_SYS_RAMBOOT + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* Needed to fill the ccsrbar pointer */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* Virtual address to CCSRBAR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +/* Physical address should be a function call */ +#ifndef __ASSEMBLY__ +extern unsigned long long get_phys_ccsrbar_addr_early(void); +#endif +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE + +/* Virtual address range for PCI region maps */ +#define CONFIG_SYS_PCI_MAP_START 0x80000000 +#define CONFIG_SYS_PCI_MAP_END 0xe8000000 + +/* Virtual address to a temporary map if we need it (max 128MB) */ +#define CONFIG_SYS_TMPVIRT 0xe8000000 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 0 + +#define CONFIG_SYS_CLK_FREQ 33000000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_HWCONFIG + +#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +#define CONFIG_LBA48 +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 + +/* + * Environment + */ +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ + +#define CONFIG_LAST_STAGE_INIT + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTCOMMAND \ + "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0" + +#endif /* __QEMU_PPCE500_H */ diff --git a/include/configs/qong.h b/include/configs/qong.h index c57fddd672..8faf6a88d9 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -3,7 +3,7 @@ * * Configuration settings for the Dave/DENX QongEVB-LITE board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -12,8 +12,6 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 /* in a mx31 */ #define CONFIG_QONG #define CONFIG_DISPLAY_CPUINFO @@ -174,7 +172,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ @@ -189,8 +186,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h deleted file mode 100644 index a51f2d4faf..0000000000 --- a/include/configs/quad100hd.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * (C) Copyright 2008 - * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * quad100hd.h - configuration for Quad100hd board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_405EP 1 /* Specifc 405EP support*/ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */ -#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */ - -/* the environment is in the EEPROM by default */ -#define CONFIG_ENV_IS_IN_EEPROM -#undef CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_HAS_ETH1 1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0x01 /* PHY address */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ -#define CONFIG_PHY_RESET 1 -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_ASKENV -#undef CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#undef CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#undef CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#undef CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#undef CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * SDRAM - *----------------------------------------------------------------------*/ -/* - * SDRAM configuration (please see cpu/ppc/sdram.[ch]) - */ -#define CONFIG_SDRAM_BANK0 1 - -/* FIX! SDRAM timings used in datasheet */ -#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ -#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ -#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ -#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ -#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ - -/* - * JFFS2 - */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#ifdef CONFIG_SYS_KERNEL_IN_JFFS2 -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */ -#else /* kernel not in JFFS */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */ -#endif -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */ - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_SYS_EEPROM_SIZE 0x2000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -/* the environment is located before u-boot */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) -#endif - -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */ -#define CONFIG_ENV_OFFSET 0x00000000 -#define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */ -#endif - -/* partly from PPCBoot */ -/* NAND */ -#define CONFIG_NAND -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */ -#define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */ -#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */ -#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */ -#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#endif - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory (OCM) for temperary stack until sdram is tested */ -/* see ./arch/powerpc/cpu/ppc4xx/start.S */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - * Taken from PPCBoot board/icecube/icecube.h - */ - -/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ -#define CONFIG_SYS_EBC_PB0AP 0x04002480 -/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */ -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 -#define CONFIG_SYS_EBC_PB1AP 0x04005480 -#define CONFIG_SYS_EBC_PB1CR 0x60018000 -#define CONFIG_SYS_EBC_PB2AP 0x00000000 -#define CONFIG_SYS_EBC_PB2CR 0x00000000 -#define CONFIG_SYS_EBC_PB3AP 0x00000000 -#define CONFIG_SYS_EBC_PB3CR 0x00000000 -#define CONFIG_SYS_EBC_PB4AP 0x00000000 -#define CONFIG_SYS_EBC_PB4CR 0x00000000 - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * Taken in part from PPCBoot board/icecube/icecube.h - */ -/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ -#define CONFIG_SYS_GPIO0_OSRL 0x55555550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097 -#define CONFIG_SYS_GPIO0_ODR 0x00000000 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* ENVIRONMENT VARS */ - -#define CONFIG_IPADDR 192.168.1.67 -#define CONFIG_SERVERIP 192.168.1.50 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 300000 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/quantum.h b/include/configs/quantum.h deleted file mode 100644 index aaf97ebe0c..0000000000 --- a/include/configs/quantum.h +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2003-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - * changes for 16M board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */ -#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -/* default developmenmt environment */ - -#define CONFIG_ETHADDR 00:0B:17:00:00:00 - -#define CONFIG_IPADDR 10.10.69.10 -#define CONFIG_SERVERIP 10.10.69.49 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME QUANTUM -#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx" - -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#define CONFIG_BOOTCOMMAND "bootm ff000000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=12345\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" - -/* - * Select the more full-featured memory test (Barr embedded systems) - */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/ -#define CONFIG_RTC_M48T35A 1 - -#if 0 -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ -#else -#undef CONFIG_WATCHDOG -#endif - -/* NVRAM and RTC */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000 -#define CONFIG_SYS_NVRAM_SIZE 2048 - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d sec...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "system" -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#if 1 - #define CONFIG_FLASH_CFI_DRIVER -#else - #undef CONFIG_FLASH_CFI_DRIVER -#endif - - -#ifdef CONFIG_FLASH_CFI_DRIVER - #define CONFIG_SYS_FLASH_CFI 1 - #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#endif - -/*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || defined(CONFIG_CMD_IDE) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 -/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* FPGA */ -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_FPGA_SPARTAN2 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK - - -/*----------------------------------------------------------------------- - * Reset address - */ -#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 - -#define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */ -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */ -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 - -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 20 - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -#endif /* __CONFIG_H */ diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index 080448090d..a71709bc7c 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -10,9 +10,6 @@ #define __R0P7734_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4 1 -#define CONFIG_SH4A 1 #define CONFIG_CPU_SH7734 1 #define CONFIG_R0P7734 1 #define CONFIG_400MHZ_MODE 1 @@ -73,7 +70,6 @@ /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " /* Buffer size for input from the Console */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for Console output */ @@ -144,8 +140,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -/* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ @@ -164,7 +158,8 @@ #else #define CONFIG_SYS_CLK_FREQ 44444444 #endif +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __R0P7734_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 65dcffb29b..24d0c34db6 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -3,8 +3,6 @@ #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4 1 #define CONFIG_CPU_SH7751 1 #define CONFIG_CPU_SH_TYPE_R 1 #define CONFIG_R2DPLUS 1 @@ -41,7 +39,6 @@ #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_MAXARGS 16 @@ -77,8 +74,9 @@ * SuperH Clock setting */ #define CONFIG_SYS_CLK_FREQ 60000000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ /* diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index dd1caf18bc..8156724f7f 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -11,8 +11,6 @@ #define __R7780RP_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4A 1 #define CONFIG_CPU_SH7780 1 #define CONFIG_R7780MP 1 #define CONFIG_SYS_R7780MP_OLD_FLASH 1 @@ -49,7 +47,6 @@ #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_MAXARGS 16 @@ -102,8 +99,9 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 /* PCI Controller */ #if defined(CONFIG_CMD_PCI) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h new file mode 100644 index 0000000000..c33f1cb880 --- /dev/null +++ b/include/configs/rcar-gen2-common.h @@ -0,0 +1,99 @@ +/* + * include/configs/rcar-gen2-common.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __RCAR_GEN2_COMMON_H +#define __RCAR_GEN2_COMMON_H + +#include + +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_RUN +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_GENERIC_BOARD + +/* Support File sytems */ +#define CONFIG_FAT_WRITE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_EXT4 +#define CONFIG_EXT4_WRITE + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_OF_LIBFDT + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_TMU_TIMER +#define CONFIG_SH_GPIO_PFC + +/* console */ +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } + +#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* ENV setting */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_ADDR 0xC0000 + +/* Common ENV setting */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) + +#endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h index 9856516c1a..e80949e3d6 100644 --- a/include/configs/rd6281a.h +++ b/include/configs/rd6281a.h @@ -18,7 +18,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_RD6281A /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/redwood.h b/include/configs/redwood.h index c8bd02e710..622b7c79e6 100644 --- a/include/configs/redwood.h +++ b/include/configs/redwood.h @@ -12,7 +12,6 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC460 family */ #define CONFIG_460SX 1 /* ... PPC460 family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ @@ -121,7 +120,6 @@ CONFIG_AMCC_DEF_ENV \ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ diff --git a/include/configs/rpi.h b/include/configs/rpi.h new file mode 100644 index 0000000000..c94f411202 --- /dev/null +++ b/include/configs/rpi.h @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* Architecture, CPU, etc.*/ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BCM2835 +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_DCACHE_OFF +/* + * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, + * so 2708 has historically been used rather than a dedicated 2835 ID. + */ +#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 + +/* Enable driver model */ +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL + +/* Memory layout */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_TEXT_BASE 0x00008000 +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE +/* + * The board really has 256M. However, the VC (VideoCore co-processor) shares + * the RAM, and uses a configurable portion at the top. We tell U-Boot that a + * smaller amount of RAM is present in order to avoid stomping on the area + * the VC uses. + */ +#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x00200000 +#define CONFIG_LOADADDR 0x00200000 + +/* Flash */ +#define CONFIG_SYS_NO_FLASH + +/* Devices */ +/* GPIO */ +#define CONFIG_BCM2835_GPIO +/* LCD */ +#define CONFIG_LCD +#define CONFIG_LCD_DT_SIMPLEFB +#define LCD_BPP LCD_COLOR16 +/* + * Prevent allocation of RAM for FB; the real FB address is queried + * dynamically from the VideoCore co-processor, and comes from RAM + * not owned by the ARM CPU. + */ +#define CONFIG_FB_ADDR 0 +#define CONFIG_VIDEO_BCM2835 +#define CONFIG_SYS_WHITE_ON_BLACK + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_MMC_SDHCI_IO_ACCESSORS +#define CONFIG_BCM2835_SDHCI + +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_DWC2_REG_ADDR 0x20980000 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MISC_INIT_R +#endif + +/* Console UART */ +#define CONFIG_PL01X_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Environment */ +#define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_SYS_LOAD_ADDR 0x1000000 +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* Shell */ +#define CONFIG_SYS_MAXARGS 8 +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_COMMAND_HISTORY + +/* Commands */ +#include +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* Device tree support */ +#define CONFIG_OF_BOARD_SETUP +/* ATAGs support for bootm/bootz */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +#include + +/* Some things don't make sense on this HW or yet */ +#undef CONFIG_CMD_FPGA + +/* Environment */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial,lcd\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it low in memory to avoid conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it low in memory to avoid conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "kernel_addr_r=0x01000000\0" \ + "fdt_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_DEVICE_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + +#define CONFIG_BOOTDELAY 2 + +#endif diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h deleted file mode 100644 index 216c6cb70b..0000000000 --- a/include/configs/rpi_b.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* Architecture, CPU, etc.*/ -#define CONFIG_ARM1176 -#define CONFIG_BCM2835 -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_DCACHE_OFF -/* - * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, - * so 2708 has historically been used rather than a dedicated 2835 ID. - */ -#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 - -/* Timer */ -#define CONFIG_SYS_HZ 1000 - -/* Memory layout */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_TEXT_BASE 0x00008000 -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* - * The board really has 256M. However, the VC (VideoCore co-processor) shares - * the RAM, and uses a configurable portion at the top. We tell U-Boot that a - * smaller amount of RAM is present in order to avoid stomping on the area - * the VC uses. - */ -#define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x00200000 -#define CONFIG_LOADADDR 0x00200000 - -/* Flash */ -#define CONFIG_SYS_NO_FLASH - -/* Devices */ -/* GPIO */ -#define CONFIG_BCM2835_GPIO -/* LCD */ -#define CONFIG_LCD -#define CONFIG_LCD_DT_SIMPLEFB -#define LCD_BPP LCD_COLOR16 -/* - * Prevent allocation of RAM for FB; the real FB address is queried - * dynamically from the VideoCore co-processor, and comes from RAM - * not owned by the ARM CPU. - */ -#define CONFIG_FB_ADDR 0 -#define CONFIG_VIDEO_BCM2835 -#define CONFIG_SYS_WHITE_ON_BLACK - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_MMC_SDHCI_IO_ACCESSORS -#define CONFIG_BCM2835_SDHCI - -/* Console UART */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 3000000 -#define CONFIG_PL01x_PORTS { (void *)0x20201000 } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 - -/* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Environment */ -#define CONFIG_ENV_SIZE SZ_16K -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_SYS_LOAD_ADDR 0x1000000 -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it low in memory to avoid conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 16M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for - * the compressed kernel to be up to 16M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stderr=serial,lcd\0" \ - "stdout=serial,lcd\0" \ - "scriptaddr=0x00000000\0" \ - "kernel_addr_r=0x01000000\0" \ - "fdt_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x02100000\0" \ - "boot_targets=mmc0\0" \ - \ - "script_boot=" \ - "if fatload ${devtype} ${devnum}:1 " \ - "${scriptaddr} boot.scr.uimg; then " \ - "source ${scriptaddr}; " \ - "fi;\0" \ - \ - "mmc_boot=" \ - "setenv devtype mmc; " \ - "if mmc dev ${devnum}; then " \ - "run script_boot; " \ - "fi\0" \ - \ - "bootcmd_mmc0=setenv devnum 0; run mmc_boot\0" \ - -#define CONFIG_BOOTCOMMAND \ - "for target in ${boot_targets}; do run bootcmd_${target}; done" - -#define CONFIG_BOOTDELAY 2 - -/* Shell */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE - -/* Commands */ -#include -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_PARTITION_UUIDS -#define CONFIG_CMD_PART -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT -/* Some things don't make sense on this HW or yet */ -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SAVEENV - -/* Device tree support for bootm/bootz */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -/* ATAGs support for bootm/bootz */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -#endif diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h deleted file mode 100644 index 2743c9afe0..0000000000 --- a/include/configs/rsdproto.h +++ /dev/null @@ -1,405 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the R&S Protocol Board board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xff000000 -#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds" - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE (0) -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* enable I2C */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x30 - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 50000000 /* in Hz */ - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_KGDB - - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_RSD_BOOT_LOW 1 - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5a -#define CONFIG_NETMASK 255.255.0.0 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */ -#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */ - -#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ -#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ - -#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ -#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ - -/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ -/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ - -#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ -#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ - -/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ -/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ - -#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */ -#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 - -#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */ -#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */ - -#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */ - -#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ - -#define CONFIG_SYS_IMMR PHYS_IMMR - -/*----------------------------------------------------------------------- - * Reset Address - * - * In order to reset the CPU, U-Boot jumps to a special address which - * causes a machine check exception. The default address for this is - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when - * testing the monitor in RAM using a JTAG debugger. - * - * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to - * cause a bus error on your hardware. - */ -#define CONFIG_SYS_RESET_ADDRESS 0x20000000 - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ - -#if defined(CONFIG_SYS_RSD_BOOT_LOW) -# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \ - HRCW_DPPC11 | \ - CONFIG_SYS_RSD_HRCW_IMMR |\ - HRCW_MMR00 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - HRCW_MODCK_H0000 |\ - CONFIG_SYS_RSD_HRCW_BOOT_FLAGS) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend. - */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH -/*#define CONFIG_SYS_MONITOR_BASE 0x200000 */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_RAMBOOT -#endif -#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */ - -/* turn off NVRAM env feature */ -#undef CONFIG_NVRAM_ENV - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR 0x100c0000 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \ - SIUMCR_CS10PC01 | SIUMCR_BCTLC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \ - SYPCR_SWRI | SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0x00000000 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - */ - -#define CONFIG_SYS_PSDMR 0x494D2452 -#define CONFIG_SYS_LSDMR 0x49492552 - -/* Flash */ -#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V) -#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \ - ORxG_BCTLD | \ - ORxG_SCY_5_CLK) - -/* DPRAM to the PCI BUS on the protocol board */ -#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V) -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \ - ORxG_ACS_DIV4) - -/* 60x Bus SDRAM */ -#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V) -#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \ - ORxS_BPD_4 | \ - ORxS_ROWST_PBI1_A2 | \ - ORxS_NUMR_13 | \ - ORxS_IBID) - -/* Virtex-FPGA - Register */ -#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) -#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ - ORxG_SCY_1_CLK | \ - ORxG_ACS_DIV2 | \ - ORxG_CSNT ) - -/* local bus SDRAM */ -#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) -#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \ - ORxS_BPD_4 | \ - ORxS_ROWST_PBI1_A4 | \ - ORxS_NUMR_13) - -/* DPRAM to the Sharc-Bus on the protocol board */ -#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V) -#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \ - ORxG_ACS_DIV4) - -#endif /* __CONFIG_H */ diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index d7473c3e62..e7f73872ee 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -11,9 +11,6 @@ #define __RSK7203_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH2 1 -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7203 1 #define CONFIG_RSK7203 1 @@ -40,7 +37,6 @@ #define CONFIG_SYS_TEXT_BASE 0x0C7C0000 #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -85,8 +81,10 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) +#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) /* Network interface */ #define CONFIG_SMC911X diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h index 783467af5e..2ecf785082 100644 --- a/include/configs/rsk7264.h +++ b/include/configs/rsk7264.h @@ -12,9 +12,6 @@ #define __RSK7264_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH2 1 -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7264 1 #define CONFIG_RSK7264 1 @@ -28,7 +25,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -65,8 +61,10 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 36000000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) +#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) /* Network interface */ #define CONFIG_SMC911X diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h index 11c2a93c1a..14c1da774d 100644 --- a/include/configs/rsk7269.h +++ b/include/configs/rsk7269.h @@ -11,9 +11,6 @@ #define __RSK7269_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH2 1 -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7269 1 #define CONFIG_RSK7269 1 @@ -27,7 +24,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Boot Argument Buffer Size */ #define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -64,8 +60,10 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 66125000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) +#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) /* Network interface */ #define CONFIG_SMC911X diff --git a/include/configs/rut.h b/include/configs/rut.h new file mode 100644 index 0000000000..0067ea46e0 --- /dev/null +++ b/include/configs/rut.h @@ -0,0 +1,161 @@ +/* + * siemens rut + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RUT_H +#define __CONFIG_RUT_H + +#define CONFIG_SIEMENS_RUT +#define MACH_TYPE_RUT 4316 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 600 +#define RUT_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 303 + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_PHY_NATSEMI + +#define CONFIG_FACTORYSET + +/* UBI Support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +/* Watchdog */ +#define WATCHDOG_TRIGGER_GPIO 14 + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=rut\0" \ + "nand_img_size=0x500000\0" \ + "splashpos=m,m\0" \ + "optargs=fixrtc --no-log consoleblank=0 \0" \ + CONFIG_COMMON_ENV_SETTINGS \ + "mmc_dev=0\0" \ + "mmc_root=/dev/mmcblk0p2 rw\0" \ + "mmc_root_fs_type=ext4 rootwait\0" \ + "mmc_load_uimage=" \ + "mmc rescan; " \ + "setenv bootfile uImage;" \ + "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ + "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "mmc_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_root} ${mtdparts}" \ + "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ + "eth=${ethaddr} " \ + "\0" \ + "mmc_boot=run mmc_args; " \ + "run mmc_load_uimage; " \ + "bootm ${kloadaddr}\0" \ + "" + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmc_dev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmc_load_uimage; then " \ + "run mmc_args;" \ + "bootm ${kloadaddr};" \ + "fi;" \ + "fi;" \ + "run nand_boot;" \ + "reset;" + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif + +#endif /* CONFIG_SPL_BUILD */ + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_HW_WATCHDOG +#endif + +#define CONFIG_VIDEO +#if defined(CONFIG_VIDEO) +#define CONFIG_VIDEO_DA8XX +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_BMP +#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE + +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI + +#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */ +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_FORMIKE +#define DISPL_PLL_SPREAD_SPECTRUM +#define CONFIG_SYS_CONSOLE_BG_COL 0xff +#define CONFIG_SYS_CONSOLE_FG_COL 0x00 +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_FIT +#endif + +#endif /* ! __CONFIG_RUT_H */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index d0fafd7136..dfa2e07948 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -17,6 +17,7 @@ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ #define CONFIG_MACH_GONI 1 /* working with Goni */ +#include #include /* get chip and board defs */ #define CONFIG_ARCH_CPU_INIT @@ -29,16 +30,19 @@ /* DRAM Base */ #define CONFIG_SYS_SDRAM_BASE 0x30000000 +/* Text Base */ +#define CONFIG_SYS_TEXT_BASE 0x34800000 + #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING -/* - * Size of malloc() pool - * 1MB = 0x100000, 0x100000 = 1024 * 1024 - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) + /* * select serial console configuration */ @@ -50,6 +54,7 @@ #define CONFIG_MMC #define CONFIG_SDHCI #define CONFIG_S5P_SDHCI +#define SDHCI_MAX_HOSTS 4 /* PWM */ #define CONFIG_PWM 1 @@ -68,14 +73,29 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_REGINFO #define CONFIG_CMD_ONENAND -#define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_MMC - -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_DFU +#define CONFIG_CMD_GPT + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 +#define CONFIG_G_DNL_MANUFACTURER "Samsung" /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ #define MTDIDS_DEFAULT "onenand0=samsung-onenand" @@ -86,32 +106,58 @@ ",7m(kernel)"\ ",1m(log)"\ ",12m(modem)"\ - ",60m(qboot)"\ - ",-(UBI)\0" + ",60m(qboot)\0" -#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT +#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_BOOTCOMMAND "run ubifsboot" +/* partitions definitions */ +#define PARTS_CSA "csa-mmc" +#define PARTS_BOOTLOADER "u-boot" +#define PARTS_BOOT "boot" +#define PARTS_ROOT "platform" +#define PARTS_DATA "data" +#define PARTS_CSC "csc" +#define PARTS_UMS "ums" + +#define CONFIG_DFU_ALT \ + "u-boot raw 0x80 0x400;" \ + "uImage ext4 0 2;" \ + "exynos3-goni.dtb ext4 0 2;" \ + ""PARTS_ROOT" part 0 5\0" + +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOTLOADER",size=60MiB," \ + "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \ + "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ + +#define CONFIG_BOOTCOMMAND "run mmcboot" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \ +#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \ " ${console} ${meminfo}" #define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}" -#define CONFIG_BOOTARGS "root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \ - " rootfstype=cramfs " CONFIG_COMMON_BOOT +#define CONFIG_BOOTARGS "root=/dev/mtdblock8 rootfstype=ext4 " \ + CONFIG_COMMON_BOOT #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \ " onenand write 0x32008000 0x0 0x100000\0" -#define CONFIG_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6" - -#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc" +#define CONFIG_MISC_COMMON +#define CONFIG_MISC_INIT_R #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_UPDATEB \ "updatek=" \ @@ -121,42 +167,44 @@ "onenand erase 0x01560000 0x1eaa0000;" \ "onenand write 0x32000000 0x1260000 0x8C0000\0" \ "bootk=" \ - "onenand read 0x30007FC0 0xc00000 0x600000;" \ + "run loaduimage;" \ "bootm 0x30007FC0\0" \ "flashboot=" \ "set bootargs root=/dev/mtdblock${bootblock} " \ - "rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \ + "rootfstype=${rootfstype} ${opts} " \ "${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \ "ubifsboot=" \ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ + "${opts} ${lcdinfo} " \ CONFIG_COMMON_BOOT "; run bootk\0" \ "tftpboot=" \ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ - CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \ - "bootm 0x30007FC0\0" \ + "${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \ + "; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \ "ramboot=" \ "set bootargs " CONFIG_RAMDISK_BOOT \ - " initrd=0x33000000,8M ramdisk=8192\0" \ + "initrd=0x33000000,8M ramdisk=8192\0" \ "mmcboot=" \ - "set bootargs root=${mmcblk} rootfstype=${rootfstype}" \ - CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ + "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "rootfstype=${rootfstype} ${opts} ${lcdinfo} " \ CONFIG_COMMON_BOOT "; run bootk\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ "verify=n\0" \ - "rootfstype=cramfs\0" \ + "rootfstype=ext4\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ - "mtdparts=" MTDPARTS_DEFAULT \ "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ - "mmcblk=/dev/mmcblk1p1\0" \ + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \ + "mmcdev=0\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=5\0" \ + "partitions=" PARTS_DEFAULT \ "bootblock=9\0" \ "ubiblock=8\0" \ "ubi=enabled\0" \ - "opts=always_resume=1" + "opts=always_resume=1\0" \ + "dfu_alt_info=" CONFIG_DFU_ALT "\0" -/* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "Goni # " @@ -170,8 +218,6 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) -#define CONFIG_SYS_HZ 1000 - /* Goni has 3 banks of DRAM, but swap the bank */ #define CONFIG_NR_DRAM_BANKS 3 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ @@ -185,9 +231,12 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ /* FLASH and environment organization */ -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB, 0x40000 */ -#define CONFIG_ENV_ADDR (1 << 20) /* 1 MB, 0x100000 */ +#define CONFIG_MMC_DEFAULT_DEV 0 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ +#define CONFIG_ENV_OVERWRITE #define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SAMSUNG_ONENAND 1 @@ -195,6 +244,18 @@ #define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +/* write support for filesystems */ +#define CONFIG_FAT_WRITE +#define CONFIG_EXT4_WRITE + +/* GPT */ +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -207,17 +268,31 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3) -#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL S5PC110_GPIO_J43 +#define CONFIG_SOFT_I2C_GPIO_SDA S5PC110_GPIO_J40 #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ #define CONFIG_SYS_I2C_SOFT_SPEED 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_INIT_BOARD + #define CONFIG_SYS_MAX_I2C_BUS 7 #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE + +#define CONFIG_OF_LIBFDT + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 97a4008e36..e7bace4345 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -7,78 +7,51 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_UNIVERSAL_H +#define __CONFIG_UNIVERSAL_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */ -#define CONFIG_UNIVERSAL 1 /* working with Universal */ -#define CONFIG_TIZEN 1 /* TIZEN lib */ +#include + +#define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */ -#include /* get chip and board defs */ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_TIZEN /* TIZEN lib */ /* Keep L2 Cache Disabled */ #define CONFIG_SYS_L2CACHE_OFF 1 +/* Universal has 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x44800000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 +/* select serial console configuration */ +#define CONFIG_SERIAL2 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) -/* select serial console configuration */ -#define CONFIG_SERIAL2 1 /* use SERIAL 2 */ -#define CONFIG_BAUDRATE 115200 - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI - -/* PWM */ -#define CONFIG_PWM 1 - -/* It should define before config_cmd_default.h */ -#define CONFIG_SYS_NO_FLASH 1 - -/* Command definition */ -#include - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_ONENAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT - -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) + +#define CONFIG_SYS_TEXT_BASE 0x44800000 #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS @@ -106,23 +79,23 @@ ",100M(swap)"\ ",-(UMS)\0" -#define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - #define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7" #define CONFIG_BOOTBLOCK "10" #define CONFIG_UBIBLOCK "9" +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + #define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc " #define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \ "${mtdparts}" #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ @@ -133,12 +106,9 @@ "onenand write 0x41008000 0xc00000 0x500000\0" \ "bootk=" \ "run loaduimage; bootm 0x40007FC0\0" \ - "updatemmc=" \ - "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ "updatebackup=" \ - "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ + "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc dev 0 0\0" \ "updatebootb=" \ "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ "lpj=lpj=3981312\0" \ @@ -184,55 +154,18 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "Universal # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -#define CONFIG_SYS_HZ 1000 - -/* Universal has 2 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SAMSUNG_ONENAND #define CONFIG_SYS_ONENAND_BASE 0x0C000000 -#define CONFIG_ENV_IS_IN_MMC 1 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */ - -#define CONFIG_DOS_PARTITION 1 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) +#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7 +#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6 + +#define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ @@ -248,39 +181,56 @@ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED /* * SPI Settings */ #define CONFIG_SOFT_SPI -#define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1) -#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3) -#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0) -#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3) - -#define SPI_DELAY udelay(1) -#undef SPI_INIT -#define SPI_SCL(bit) universal_spi_scl(bit) -#define SPI_SDA(bit) universal_spi_sda(bit) -#define SPI_READ universal_spi_read() + #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); void universal_spi_sda(int bit); int universal_spi_read(void); #endif +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX8998_PMIC" +#define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 7) +#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 +#define KEY_PWR_INTERRUPT_MASK (1 << 7) + +#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 +#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + /* * LCD Settings */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_LD9040 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h deleted file mode 100644 index d63d0c4f54..0000000000 --- a/include/configs/sacsng.h +++ /dev/null @@ -1,1041 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * Configuration settings for the SACSng 8260 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ - -#undef CONFIG_LOGBUFFER /* External logbuffer support */ - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN 66666600 - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x1 0x5 33 100 133 Open Close Open - * 0x1 0x6 33 100 166 Open Open Close - * 0x1 0x7 33 100 200 Open Open Open - * - * 0x2 0x2 33 133 133 Close Open Close - * 0x2 0x3 33 133 166 Close Open Open - * 0x2 0x4 33 133 200 Open Close Close - * 0x2 0x5 33 133 233 Open Close Open - * 0x2 0x6 33 133 266 Open Open Close - * - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CONFIG_SYS_SBC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_SBC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 2 - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. - */ -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH1_SIZE 2 - -/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes - */ -#define CONFIG_VERY_BIG_RAM 1 - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? This will normally auto-configure via the SPD. -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* - * Memory map example with 64 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x03F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x03F5 FFB0 Board Info Data - * 0x03F6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 16k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x03FC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU) - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ - -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ - -#ifdef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif /* CONFIG_ETHER_ON_SCC */ - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ - -#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x40000000) -#define MDIO_TRISTATE (iop->pdir &= ~0x40000000) -#define MDIO_READ ((iop->pdat & 0x40000000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \ - else iop->pdat &= ~0x40000000 - -#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \ - else iop->pdat &= ~0x80000000 - -#define MIIDELAY udelay(50) -#endif /* CONFIG_ETHER_ON_FCC */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */ - -/* - * Configure for RAM tests. - */ -#undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */ - - -/* - * Status LED for power up status feedback. - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define STATUS_LED_PAR im_ioport.iop_ppara -#define STATUS_LED_DIR im_ioport.iop_pdira -#define STATUS_LED_ODR im_ioport.iop_podra -#define STATUS_LED_DAT im_ioport.iop_pdata - -#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */ -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ) -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */ -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ) -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */ -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2) -#define STATUS_LED_STATE2 STATUS_LED_ON - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - -#define STATUS_LED_YELLOW 0 -#define STATUS_LED_GREEN 1 -#define STATUS_LED_RED 2 -#define STATUS_LED_BOOT 1 - - -/* - * Select SPI support configuration - */ -#define CONFIG_SOFT_SPI /* Enable SPI driver */ -#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */ -#undef DEBUG_SPI /* Disable SPI debugging */ - -/* - * Software (bit-bang) SPI driver configuration - */ -#ifdef CONFIG_SOFT_SPI - -/* - * Software (bit-bang) SPI driver configuration - */ -#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */ -#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */ -#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */ - -#undef SPI_INIT /* no port initialization needed */ -#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) -#define SPI_SDA(bit) do { \ - if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ - else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \ - } while (0) -#define SPI_SCL(bit) do { \ - if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ - else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \ - } while (0) -#define SPI_DELAY /* No delay is needed */ -#endif /* CONFIG_SOFT_SPI */ - - -/* - * select I2C support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */ - -/* Define this to reserve an entire FLASH sector for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT 1 - -/* Define this to contain any number of null terminated strings that - * will be part of the default enviroment compiled into the boot image. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ -"quiet=0\0" \ -"serverip=192.168.123.205\0" \ -"ipaddr=192.168.123.203\0" \ -"checkhostname=VR8500\0" \ -"reprog="\ - "bootp; " \ - "tftpboot 0x140000 /bdi2000/u-boot.bin; " \ - "protect off 60000000 6003FFFF; " \ - "erase 60000000 6003FFFF; " \ - "cp.b 140000 60000000 ${filesize}; " \ - "protect on 60000000 6003FFFF\0" \ -"copyenv="\ - "protect off 60040000 6004FFFF; " \ - "erase 60040000 6004FFFF; " \ - "cp.b 40040000 60040000 10000; " \ - "protect on 60040000 6004FFFF\0" \ -"copyprog="\ - "protect off 60000000 6003FFFF; " \ - "erase 60000000 6003FFFF; " \ - "cp.b 40000000 60000000 40000; " \ - "protect on 60000000 6003FFFF\0" \ -"zapenv="\ - "protect off 40040000 4004FFFF; " \ - "erase 40040000 4004FFFF; " \ - "protect on 40040000 4004FFFF\0" \ -"zapotherenv="\ - "protect off 60040000 6004FFFF; " \ - "erase 60040000 6004FFFF; " \ - "protect on 60040000 6004FFFF\0" \ -"root-on-initrd="\ - "setenv bootcmd "\ - "version\\;" \ - "echo\\;" \ - "bootp\\;" \ - "setenv bootargs root=/dev/ram0 rw quiet " \ - "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ - "run boot-hook\\;" \ - "bootm\0" \ -"root-on-initrd-debug="\ - "setenv bootcmd "\ - "version\\;" \ - "echo\\;" \ - "bootp\\;" \ - "setenv bootargs root=/dev/ram0 rw debug " \ - "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ - "run debug-hook\\;" \ - "run boot-hook\\;" \ - "bootm\0" \ -"root-on-nfs="\ - "setenv bootcmd "\ - "version\\;" \ - "echo\\;" \ - "bootp\\;" \ - "setenv bootargs root=/dev/nfs rw quiet " \ - "nfsroot=\\${serverip}:\\${rootpath} " \ - "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ - "run boot-hook\\;" \ - "bootm\0" \ -"root-on-nfs-debug="\ - "setenv bootcmd "\ - "version\\;" \ - "echo\\;" \ - "bootp\\;" \ - "setenv bootargs root=/dev/nfs rw debug " \ - "nfsroot=\\${serverip}:\\${rootpath} " \ - "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ - "run debug-hook\\;" \ - "run boot-hook\\;" \ - "bootm\0" \ -"debug-checkout="\ - "setenv checkhostname;" \ - "setenv ethaddr 00:09:70:00:00:01;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run debug-hook;" \ - "run boot-hook;" \ - "bootm\0" \ -"debug-hook="\ - "echo ipaddr ${ipaddr};" \ - "echo serverip ${serverip};" \ - "echo gatewayip ${gatewayip};" \ - "echo netmask ${netmask};" \ - "echo hostname ${hostname}\0" \ -"ana=run adc ; run dac\0" \ -"adc=run adc-12 ; run adc-34\0" \ -"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \ -"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \ -"dac=echo ### DAC ; i2c md 11 81 5\0" \ -"boot-hook=echo\0" - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 9600 - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 00:09:70:00:00:00 - -/* The default Ethernet MAC address can be overwritten just once */ -#ifdef CONFIG_ETHADDR -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#endif - -/* - * Define this to do some miscellaneous board-specific initialization. - */ -#define CONFIG_MISC_INIT_R - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n" -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define DEBUG_BOOTKEYS 0 - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw quiet " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "=> " - -#undef CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) - * of an image is printed by image commands like bootm or iminfo. - */ -#define CONFIG_TIMESTAMP - -/* If this variable is defined, an environment variable named "ver" - * is created by U-Boot showing the U-Boot version. - */ -#define CONFIG_VERSION_VARIABLE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING - -#undef CONFIG_CMD_KGDB - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_CMD_MII -#endif - - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xF0000000 - -#undef CONFIG_WATCHDOG /* disable the watchdog */ - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_SACSng 1 /* munged for the SACSng */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */ - /* in the bootm command. */ -#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */ - /* "## " from the bootm cmd */ -#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */ - /* defined, then the hostname param */ - /* validated against checkhostname. */ -#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */ -#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */ - /* (limited to maximum of 1024 msec) */ -#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1 - /* Check for abort key presses */ - /* at least once in dependent of the */ - /* CONFIG_BOOTDELAY value. */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */ - /* state to the fault LED. */ -#define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */ - /* the Ethernet link state. */ -#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */ - /* until the TFTP is successful. */ -#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */ - /* turn off the STATUS LEDs. */ -#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */ - /* incoming data. */ -#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */ - /* to signify that tftp is moving. */ -#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */ - /* flash the status LED. */ -#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */ - /* during the tftp file transfer. */ -#define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */ - /* '#'s from the tftp command. */ -#define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */ - /* issued during the tftp command. */ -#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */ - /* before it gives up. */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */ -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ - - CONFIG_SYS_MEM_END_USAGE ) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \ - HRCW_DPPC11 | \ - CONFIG_SYS_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 - -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -# define CONFIG_ENV_SECT_SIZE 0x10000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ - -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP |\ - SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 16 bit FLASH (primary flash - 2MB) - * 1 60x GPCM -- bit (Unused) - * 2 60x SDRAM 64 bit SDRAM (DIMM) - * 3 60x SDRAM 64 bit SDRAM (DIMM) - * 4 60x GPCM -- bit (Unused) - * 5 60x GPCM -- bit (Unused) - * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB) - */ - -/*----------------------------------------------------------------------- - * BR0,BR1 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0,OR1 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0 - Primary FLASH - */ - -/* BR0 is configured as follows: - * - * - Base address of 0x40000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 4 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2,3 - SDRAM DIMM - */ - -/* The BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM0_SIZE == 64) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -/* Address that the DIMM SPD memory lives at. - */ -#define SDRAM_SPD_ADDR 0x50 - -#if (CONFIG_SYS_SDRAM0_SIZE == 64) -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/* - * Shoot for approximately 1MHz on the prescaler. - */ -#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000)) -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64 -#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000)) -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#else -#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK" -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#endif -#define CONFIG_SYS_PSRT 14 - - -/*----------------------------------------------------------------------- - * BR6 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR6 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 6 - Secondary FLASH - * - * The secondary FLASH is connected to *CS6 - */ -#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) - -/* BR6 is configured as follows: - * - * - Base address of 0x60000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR6 is configured as follows: - * - * - 2 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h new file mode 100644 index 0000000000..9458047c06 --- /dev/null +++ b/include/configs/sama5d3_xplained.h @@ -0,0 +1,253 @@ +/* + * Configuration settings for the SAMA5D3 Xplained board. + * + * Copyright (C) 2014 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_DBGU + +/* + * This needs to be defined for the OHCI code to work but it is defined as + * ATMEL_ID_UHPHS in the CPU specific header files. + */ +#define ATMEL_ID_UHP ATMEL_ID_UHPHS + +/* + * Specify the clock enable bit in the PMC_SCER register. + */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x310000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_PMECC_CAP 4 +#define CONFIG_PMECC_SECTOR_SIZE 512 +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_MTDPARTS + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RGMII +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_ATMEL_MCI_8BIT +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_DOS_PARTITION +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#if CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#endif + +#endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 10697d627a..f2849d794e 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -20,18 +20,21 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT +#endif + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* Device Tree support */ +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_AT91_GPIO @@ -56,7 +59,6 @@ #define LCD_BPP LCD_COLOR16 #define LCD_OUTPUT_BPP 24 #define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_WHITE_ON_BLACK @@ -77,8 +79,19 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME -/* No NOR flash */ +/* NOR flash */ +#define CONFIG_CMD_FLASH + +#ifdef CONFIG_CMD_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MAX_FLASH_SECT 131 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#else #define CONFIG_SYS_NO_FLASH +#endif /* * Command line configuration. @@ -95,8 +108,12 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x310000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif /* SerialFlash */ #define CONFIG_CMD_SF @@ -112,7 +129,6 @@ #define CONFIG_CMD_NAND #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MAX_CHIPS 1 #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 @@ -126,16 +142,19 @@ #define CONFIG_ATMEL_NAND_HW_PMECC #define CONFIG_PMECC_CAP 4 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET ATMEL_PMECC_INDEX_OFFSET_512 #define CONFIG_CMD_NAND_TRIMFFS #endif /* Ethernet Hardware */ #define CONFIG_MACB #define CONFIG_RMII -#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RGMII +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 /* MMC */ #define CONFIG_CMD_MMC @@ -152,6 +171,7 @@ #ifdef CONFIG_CMD_USB #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI @@ -161,6 +181,14 @@ #define CONFIG_USB_STORAGE #endif +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK" + #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) #define CONFIG_CMD_FAT #endif @@ -195,7 +223,7 @@ "bootm 0x22000000 - 0x21000000" #define CONFIG_SYS_MMC_ENV_DEV 0 #else -#define CONIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif #ifdef CONFIG_SYS_USE_MMC @@ -226,4 +254,52 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#elif CONFIG_SYS_USE_SERIALFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 + +#endif + #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h new file mode 100644 index 0000000000..996973d99b --- /dev/null +++ b/include/configs/sama5d4_xplained.h @@ -0,0 +1,224 @@ +/* + * Configuration settings for the SAMA5D4 Xplained ultra board. + * + * Copyright (C) 2014 Atmel + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART3 +#define CONFIG_USART_ID ATMEL_ID_USART3 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ +#define CONFIG_CMD_SF + +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#endif + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ +#ifdef CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_SYS_USE_SERIALFLASH +/* bootstrap + u-boot + env + linux in serial flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0xa0000 0x60000; " \ + "sf read 0x22000000 0x100000 0x300000; " \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +/* + * We don't specify the part number, if device 0 has partition table, it means + * the first partition; it no partition table, then take whole device as a + * FAT file system. + */ +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d4_xplained.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h new file mode 100644 index 0000000000..09ab4d7f25 --- /dev/null +++ b/include/configs/sama5d4ek.h @@ -0,0 +1,222 @@ +/* + * Configuration settings for the SAMA5D4EK board. + * + * Copyright (C) 2014 Atmel + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART3 +#define CONFIG_USART_ID ATMEL_ID_USART3 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ +#define CONFIG_CMD_SF + +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#endif + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +#define CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 18 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#ifdef CONFIG_SYS_USE_SERIALFLASH +/* bootstrap + u-boot + env + linux in serial flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0xa0000 0x60000; " \ + "sf read 0x22000000 0x100000 0x300000; " \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +/* + * We don't specify the part number, if device 0 has partition table, it means + * the first partition; it no partition table, then take whole device as a + * FAT file system. + */ +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 sama5d4ek.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index af3d6ad4e7..e9d3f3226b 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -16,40 +16,63 @@ #endif +#define CONFIG_IO_TRACE +#define CONFIG_CMD_IOTRACE + +#define CONFIG_SYS_TIMER_RATE 1000000 + #define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT +#define CONFIG_CMD_DEMO +#define CONFIG_CMD_DM +#define CONFIG_DM_DEMO +#define CONFIG_DM_DEMO_SIMPLE +#define CONFIG_DM_DEMO_SHAPE +#define CONFIG_DM_GPIO +#define CONFIG_DM_TEST +#define CONFIG_DM_SERIAL +#define CONFIG_DM_CROS_EC + +#define CONFIG_SYS_STDIO_DEREGISTER /* Number of bits in a C 'long' on this architecture */ #define CONFIG_SANDBOX_BITS_PER_LONG 64 -#define CONFIG_OF_CONTROL -#define CONFIG_OF_HOSTFILE #define CONFIG_OF_LIBFDT #define CONFIG_LMB -#define CONFIG_FIT -#define CONFIG_FIT_SIGNATURE -#define CONFIG_RSA #define CONFIG_CMD_FDT +#define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_FS_FAT +#define CONFIG_FAT_WRITE #define CONFIG_FS_EXT4 #define CONFIG_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_PART +#define CONFIG_DOS_PARTITION +#define CONFIG_HOST_MAX_DEVICES 4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_MD5SUM #define CONFIG_SYS_VSNPRINTF #define CONFIG_CMD_GPIO #define CONFIG_SANDBOX_GPIO -#define CONFIG_SANDBOX_GPIO_COUNT 20 +#define CONFIG_SANDBOX_GPIO_COUNT 128 + +#define CONFIG_CMD_GPT +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION /* - * Size of malloc() pool, although we don't actually use this yet. + * Size of malloc() pool, before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_MALLOC_F_ADDR 0x0010000 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ -#define CONFIG_SYS_PROMPT "=>" /* Command Prompt */ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_LONGHELP /* #undef to save memory */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -62,18 +85,42 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY #define CONFIG_AUTO_COMPLETE +#define CONFIG_BOOTDELAY 3 #define CONFIG_ENV_SIZE 8192 #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_HZ 1000 +/* SPI - enable all SPI flash types for testing purposes */ +#define CONFIG_SANDBOX_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SF_TEST +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_SANDBOX +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND + +#define CONFIG_DM_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SANDBOX +#define CONFIG_I2C_EDID +#define CONFIG_I2C_EEPROM /* Memory things - we don't really want a memory test */ #define CONFIG_SYS_LOAD_ADDR 0x00000000 #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000) -#define CONFIG_PHYS_64BIT -#define CONFIG_SYS_FDT_LOAD_ADDR 0x1000000 +#define CONFIG_SYS_FDT_LOAD_ADDR 0x100 + +#define CONFIG_PHYSMEM /* Size of our emulated memory */ #define CONFIG_SYS_SDRAM_BASE 0 @@ -101,12 +148,57 @@ #define CONFIG_SHA1 #define CONFIG_SHA256 +#define CONFIG_TPM_TIS_SANDBOX + #define CONFIG_CMD_SANDBOX #define CONFIG_BOOTARGS "" +#define CONFIG_CROS_EC +#define CONFIG_CMD_CROS_EC +#define CONFIG_CROS_EC_SANDBOX +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SOUND +#define CONFIG_SOUND_SANDBOX +#define CONFIG_CMD_SOUND + +#ifndef SANDBOX_NO_SDL +#define CONFIG_SANDBOX_SDL +#endif + +/* LCD and keyboard require SDL support */ +#ifdef CONFIG_SANDBOX_SDL +#define CONFIG_LCD +#define CONFIG_VIDEO_SANDBOX_SDL +#define CONFIG_CMD_BMP +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define LCD_BPP LCD_COLOR16 +#define CONFIG_LCD_BMP_RLE8 + +#define CONFIG_CROS_EC_KEYB +#define CONFIG_KEYBOARD + +#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" +#else + #define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" +#endif + +#define CONFIG_GZIP_COMPRESSED +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA + +#define CONFIG_TPM_TIS_SANDBOX + +#define CONFIG_CMD_LZMADEC #endif diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h new file mode 100644 index 0000000000..6573ac3c0b --- /dev/null +++ b/include/configs/sansa_fuze_plus.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__ +#define __CONFIGS_SANSA_FUZE_PLUS_H__ + +/* System configurations */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_VIDEO +#define CONFIG_CMD_MEMTEST + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_OVERWRITE + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_FONT_4X6 +#define CONFIG_VIDEO_MXS_MODE_SYSTEM +#define CONFIG_SYS_BLACK_IN_WRITE +#define LCD_BPP LCD_COLOR16 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#endif + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_SANSA_FUZE_PLUS_H__ */ diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index 4ba224252a..e7c35eca39 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -12,7 +12,7 @@ /* SoC type is defined in boards.cfg */ #include -#include +#include #if defined(CONFIG_SYS_USE_NANDFLASH) #define CONFIG_ENV_IS_IN_NAND @@ -26,7 +26,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_ARCH_CPU_INIT @@ -81,7 +80,6 @@ #define CONFIG_SPI #define CONFIG_CMD_SPI #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_CMD_EEPROM #define CONFIG_SPI_M95XXX @@ -116,9 +114,11 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R #define CONFIG_MACB_SEARCH_PHY +#define CONFIG_AT91_WANTS_COMMON_PHY /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 072f97e602..69dc210917 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2001 * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -17,7 +17,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -113,7 +112,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ @@ -146,8 +144,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6f912ed2c3..2516a3e97e 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -5,7 +5,7 @@ * Paul Gortmaker * Based on the MPC8349EMDS config. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -19,7 +19,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ @@ -438,7 +437,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -451,7 +449,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -645,7 +642,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 84be5246b9..aee0d9e273 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -13,6 +13,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Top level Makefile configuration choices */ @@ -38,7 +40,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ @@ -102,7 +103,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_DDR_ECC /* only for ECC DDR module */ /* @@ -557,7 +558,6 @@ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -566,7 +566,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -577,7 +576,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index cf97db94c8..8eb7276618 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -7,7 +7,7 @@ * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -21,7 +21,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ #define CONFIG_MP 1 /* support multiple processors */ @@ -496,7 +495,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -507,7 +505,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -525,7 +522,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/sc3.h b/include/configs/sc3.h index a96ffbcec3..14e033dd80 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -6,7 +6,7 @@ * (C) Copyright 2003 * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -43,7 +43,6 @@ */ #define CONFIG_SC3 1 -#define CONFIG_4xx 1 #define CONFIG_405GP 1 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 @@ -224,8 +223,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - /*----------------------------------------------------------------------- * IIC stuff *----------------------------------------------------------------------- diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index 9c2eb05c04..ff74cb2639 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -4,50 +4,17 @@ * Copyright (C) 2012 Marek Vasut * on behalf of DENX Software Engineering GmbH * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __SC_SPS_1_H__ -#define __SC_SPS_1_H__ +#ifndef __CONFIGS_SC_SPS_1_H__ +#define __CONFIGS_SC_SPS_1_H__ -/* - * SoC configurations - */ -#define CONFIG_MX28 /* i.MX28 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - -/* - * Define SC_SPS_1 machine type by hand until it lands in mach-types - */ +/* System configuration */ #define MACH_TYPE_SC_SPS_1 4172 - #define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1 -#include - +/* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_ARCH_MISC_INIT - -#define CONFIG_ENV_IS_IN_MMC - -#define CONFIG_OF_LIBFDT - -/* - * SPL - */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - -/* - * U-Boot Commands - */ #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -65,119 +32,47 @@ #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_USB -/* - * Memory configurations - */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* - * Serial Driver - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_APBH_DMA -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_MXS_MMC -#endif +/* Environment */ #define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_IS_IN_MMC + +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_ENV_OFFSET (256 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 #else #define CONFIG_ENV_IS_NOWHERE #endif -/* - * Ethernet on SOC (FEC) - */ +/* FEC Ethernet on SoC */ #ifdef CONFIG_CMD_NET -#define CONFIG_ETHPRIME "FEC0" #define CONFIG_FEC_MXC -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC #endif -/* - * USB - */ +/* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS +/* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200" -#define CONFIG_BOOTCOMMAND "bootm " +#define CONFIG_BOOTCOMMAND "bootm" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* - * Extra Environments - */ +/* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ @@ -189,4 +84,7 @@ "fi ; " \ "fi\0" -#endif /* __SC_SPS_1_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_SC_SPS_1_H__ */ diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index a09310c889..f4a40bb932 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -10,8 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ -#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ +#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */ #define CONFIG_SCB9328 1 /* on a scb9328tronix board */ #define CONFIG_IMX_SERIAL @@ -69,7 +68,6 @@ #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ #define CONFIG_SYS_MEMTEST_END 0x08F00000 -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ #define CONFIG_BAUDRATE 115200 @@ -143,8 +141,8 @@ now.*/ #undef CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */ #define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 2a24ef3c64..5f77051d13 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include /* LP0 suspend / resume */ #define CONFIG_TEGRA_LP0 @@ -19,11 +19,6 @@ #include "tegra20-common.h" -/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-seaboard -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (SeaBoard) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" @@ -42,10 +37,7 @@ /* I2C */ #define CONFIG_SYS_I2C_TEGRA -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C /* SD/MMC */ #define CONFIG_MMC diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index d2dedac4ed..b6a5e6a59c 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -27,7 +27,6 @@ #define CONFIG_HOSTNAME rainier #endif #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF80000 @@ -98,10 +97,7 @@ /* * Environment */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */ -#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */ -#elif defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */ #define CONFIG_ENV_SIZE (8 << 10) /* @@ -149,68 +145,11 @@ #endif #endif /* CONFIG_CMD_FLASH */ -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */ - /* this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /* * DDR SDRAM */ #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ - !defined(CONFIG_SYS_RAMBOOT) +#if !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ @@ -248,7 +187,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=FC000000\0" \ "ramdisk_addr=FC180000\0" \ "" @@ -322,7 +260,7 @@ * overwrite part of the U-Boot image which is already loaded from NAND * to SDRAM. */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_POST_MEMORY_ON 0 #else #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY @@ -371,8 +309,7 @@ /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ - !defined(CONFIG_SYS_RAMBOOT) +#if !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x03017200 diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index fb4dc6fde4..2d509a9b9c 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -10,9 +10,6 @@ #define __SH7752EVB_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4A 1 -#define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7752 1 #define CONFIG_SH7752EVB 1 @@ -51,7 +48,6 @@ #define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024) #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_MAXARGS 16 @@ -132,6 +128,7 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 48000000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __SH7752EVB_H */ diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h new file mode 100644 index 0000000000..c31dd7a174 --- /dev/null +++ b/include/configs/sh7753evb.h @@ -0,0 +1,134 @@ +/* + * Configuation settings for the sh7753evb board + * + * Copyright (C) 2012 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SH7753EVB_H +#define __SH7753EVB_H + +#undef DEBUG +#define CONFIG_CPU_SH7753 1 +#define CONFIG_SH7753EVB 1 + +#define CONFIG_SYS_TEXT_BASE 0x5ff80000 +#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7753evb/u-boot.lds" + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SF +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MD5SUM +#define CONFIG_MD5 +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* MEMORY */ +#define SH7753EVB_SDRAM_BASE (0x40000000) +#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF2 1 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + 480 * 1024 * 1024) +#undef CONFIG_SYS_ALT_MEMTEST +#undef CONFIG_SYS_MEMTEST_SCRATCH +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ + 128 * 1024 * 1024) + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SYS_NO_FLASH + +/* Ether */ +#define CONFIG_SH_ETHER 1 +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 18 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 +#define CONFIG_SH_ETHER_USE_GETHER 1 +#define CONFIG_PHYLIB +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII +#define CONFIG_PHY_VITESSE + +#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000 +#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024) +#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI +#define SH7753EVB_ETHERNET_MAC_SIZE 17 +#define SH7753EVB_ETHERNET_NUM_CH 2 +#define CONFIG_BOARD_LATE_INIT + +/* SPI */ +#define CONFIG_SH_SPI 1 +#define CONFIG_SH_SPI_BASE 0xfe002000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO 1 +#define CONFIG_SPI_FLASH_MACRONIX 1 + +/* MMCIF */ +#define CONFIG_MMC 1 +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_SH_MMCIF 1 +#define CONFIG_SH_MMCIF_ADDR 0xffcb0000 +#define CONFIG_SH_MMCIF_CLK 48000000 + +/* ENV setting */ +#define CONFIG_ENV_IS_EMBEDDED +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_ADDR (0x00080000) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netboot=bootp; bootm\0" + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 48000000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_TMU_CLK_DIV 4 +#endif /* __SH7753EVB_H */ diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index af76f49dd2..36afd5f70a 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -10,9 +10,6 @@ #define __SH7757LCR_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4A 1 -#define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7757 1 #define CONFIG_SH7757LCR 1 #define CONFIG_SH7757LCR_DDR_ECC 1 @@ -51,7 +48,6 @@ #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_MAXARGS 16 @@ -140,6 +136,7 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 48000000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __SH7757LCR_H */ diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index c1d33d87ba..2438318fca 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -10,8 +10,6 @@ #ifndef __SH7763RDP_H #define __SH7763RDP_H -#define CONFIG_SH 1 -#define CONFIG_SH4 1 #define CONFIG_CPU_SH7763 1 #define CONFIG_SH7763RDP 1 #define __LITTLE_ENDIAN 1 @@ -43,7 +41,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -98,8 +95,9 @@ /* Clock */ #define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ -#define CONFIG_SYS_HZ 1000 /* Ether */ #define CONFIG_SH_ETHER 1 diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index 04f1d2284e..2723eaf2d3 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -10,8 +10,6 @@ #define __SH7785LCR_H #undef DEBUG -#define CONFIG_SH 1 -#define CONFIG_SH4A 1 #define CONFIG_CPU_SH7785 1 #define CONFIG_SH7785LCR 1 @@ -65,7 +63,6 @@ #endif #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_MAXARGS 16 @@ -172,7 +169,8 @@ /* Board Clock */ /* The SCIF used external clock. system clock only used timer. */ #define CONFIG_SYS_CLK_FREQ 50000000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 #endif /* __SH7785LCR_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index ecc93bc539..21c8bda9f3 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -1,5 +1,6 @@ /* - * (C) Copyright 2009 + * (C) Copyright 2009-2014 + * Gerald Kerma * Marvell Semiconductor * Written-by: Prafulla Wadaskar * @@ -9,6 +10,8 @@ #ifndef _CONFIG_SHEEVAPLUG_H #define _CONFIG_SHEEVAPLUG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -18,19 +21,33 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_SHEEVAPLUG /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ + /* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV +#define CONFIG_CMD_IDE #define CONFIG_CMD_MII +#define CONFIG_CMD_MMC #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB @@ -54,8 +71,8 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_ADDR 0x80000 +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ /* * Default environment variables @@ -64,8 +81,10 @@ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ "${x_bootcmd_usb}; bootm 0x6400000;" -#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \ - "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0" +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:512K(uboot)," \ + "512K(env),1M(script),6M(kernel)," \ + "12M(ramdisk),4M(spare),-(rootfs)" #define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ @@ -73,6 +92,11 @@ "x_bootcmd_usb=usb start\0" \ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" +#define MTDIDS_DEFAULT "nand0=orion_nand" + +#define MTDPARTS_DEFAULT \ + "mtdparts="CONFIG_MTDPARTS + /* * Ethernet Driver configuration */ @@ -81,10 +105,34 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ +/* + * SDIO/MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MVEBU_MMC +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE +#endif /* CONFIG_CMD_MMC */ + +/* + * SATA driver configuration + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +#define CONFIG_MVSATA_IDE_USE_PORT1 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_CMD_IDE */ + /* * File system */ #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_UBI diff --git a/include/configs/shmin.h b/include/configs/shmin.h index 5fb71760f8..4d38f6c554 100644 --- a/include/configs/shmin.h +++ b/include/configs/shmin.h @@ -9,8 +9,6 @@ #ifndef __SHMIN_H #define __SHMIN_H -#define CONFIG_SH 1 -#define CONFIG_SH3 1 #define CONFIG_CPU_SH7706 1 /* T-SH7706LAN */ #define CONFIG_SHMIN 1 @@ -42,7 +40,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8DFB0000 #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ @@ -65,7 +62,6 @@ #define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE) #define CONFIG_SYS_MONITOR_LEN (128 * 1024) #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE 256 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ @@ -103,8 +99,9 @@ #else #define CONFIG_SYS_CLK_FREQ 33333333 #endif /* CONFIG_T_SH7706LSR */ +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -#define CONFIG_SYS_HZ 1000 /* Network device */ #define CONFIG_DRIVER_NE2000 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h new file mode 100644 index 0000000000..21e13e5473 --- /dev/null +++ b/include/configs/siemens-am33x-common.h @@ -0,0 +1,499 @@ +/* + * siemens am33x common board options + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H +#define __CONFIG_SIEMENS_AM33X_COMMON_H + +#define CONFIG_AM33XX +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +#include + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (0x2000) +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_NO_FLASH +#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* commands to include */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CACHE + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#ifndef CONFIG_SPL_BUILD +#define CONFIG_ROOTPATH "/opt/eldk" +#endif + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_AUTOLOAD "yes" + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 32 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * memtest works on 8 MB in DRAM after skipping 32MB from + * start addr of ram disk + */ +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + + (8 * 1024 * 1024)) + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_MTD_DEVICE +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED (75000000) + + /* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CONFIG_SYS_NS16550_COM4 0x481a6000 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SERIAL1 1 +#define CONFIG_CONS_INDEX 1 + +/* I2C Configuration */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (101 * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_FS_FAT +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_NAND_AM33XX_BCH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + +#define CONFIG_SYS_NAND_ECCSTEPS 4 +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#ifndef CONFIG_SPL_BUILD +/* + * USB configuration + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#undef CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST + +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_MUSB_GADGET +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" +#endif /* CONFIG_MUSB_GADGET */ + +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET + +/* USB DRACO ID as default */ +#define CONFIG_USBD_HS +#define CONFIG_G_DNL_VENDOR_NUM 0x0908 +#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2 +#define CONFIG_G_DNL_MANUFACTURER "Siemens AG" + +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_NAND +#define CONFIG_CMD_DFU +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) +#define DFU_MANIFEST_POLL_TIMEOUT 25000 + +#endif /* CONFIG_SPL_BUILD */ + +/* + * Default to using SPI for environment, etc. We have multiple copies + * of SPL as the ROM will check these locations. + * 0x0 - 0x20000 : First copy of SPL + * 0x20000 - 0x40000 : Second copy of SPL + * 0x40000 - 0x60000 : Third copy of SPL + * 0x60000 - 0x80000 : Fourth copy of SPL + * 0x80000 - 0xDF000 : U-Boot + * 0xDF000 - 0xE0000 : U-Boot Environment + * 0xE0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ +#if defined(CONFIG_SPI_BOOT) +# undef CONFIG_ENV_IS_NOWHERE +# define CONFIG_ENV_IS_IN_SPI_FLASH +# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ +# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#endif /* SPI support */ + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_CMD_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI + +#define CONFIG_NAND +/* NAND support */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS + +#define MTDIDS_NAME_STR "omap2-nand.0" +#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ + "128k(spl)," \ + "128k(spl.backup1)," \ + "128k(spl.backup2)," \ + "128k(spl.backup3)," \ + "1920k(u-boot)," \ + "128k(uboot.env)," \ + "5120k(kernel_a)," \ + "5120k(kernel_b)," \ + "8192k(mtdoops)," \ + "-(rootfs)" +/* + * chip-size = 256MiB + *| name | size | address area | + *------------------------------------------------------- + *| spl | 128.000 KiB | 0x 0..0x 1ffff | + *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | + *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | + *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | + *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | + *| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff | + *| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff | + *| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff | + *| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff | + *| rootfs | 235.500 MiB | 0x 1480000..0x fffffff | + *------------------------------------------------------- + */ + +#define DFU_ALT_INFO_NAND \ + "spl part 0 1;" \ + "spl.backup1 part 0 2;" \ + "spl.backup2 part 0 3;" \ + "spl.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot.env part 0 6;" \ + "kernel_a part 0 7;" \ + "kernel_b part 0 8;" \ + "rootfs partubi 0 10" + +#define CONFIG_COMMON_ENV_SETTINGS \ + "verify=no \0" \ + "project_dir=targetdir\0" \ + "upgrade_available=0\0" \ + "altbootcmd=run bootcmd\0" \ + "bootlimit=3\0" \ + "partitionset_active=A\0" \ + "loadaddr=0x82000000\0" \ + "kloadaddr=0x81000000\0" \ + "script_addr=0x81900000\0" \ + "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \ + "nand_active_ubi_vol=rootfs_a\0" \ + "nand_active_ubi_vol_A=rootfs_a\0" \ + "nand_active_ubi_vol_B=rootfs_b\0" \ + "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_src_addr=0x280000\0" \ + "nand_src_addr_A=0x280000\0" \ + "nand_src_addr_B=0x780000\0" \ + "nfsopts=nolock rw mem=128M\0" \ + "ip_method=none\0" \ + "bootenv=uEnv.txt\0" \ + "bootargs_defaults=setenv bootargs " \ + "console=${console} " \ + "${testargs} " \ + "${optargs}\0" \ + "nand_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; then " \ + "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \ + "setenv nand_src_addr ${nand_src_addr_A};" \ + "fi;" \ + "if test -n ${B}; then " \ + "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \ + "setenv nand_src_addr ${nand_src_addr_B};" \ + "fi;" \ + "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ + "ubi.mtd=9,2048;" \ + "setenv bootargs ${bootargs} " \ + "root=${nand_root} noinitrd ${mtdparts} " \ + "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ + "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ + "=mtdoops\0" \ + "dfu_args=run bootargs_defaults;" \ + "setenv bootargs ${bootargs} ;" \ + "mtdparts default; " \ + "led dfu 1;" \ + "led stat 0;" \ + "dfu 0 nand 0;" \ + "led dfu 0;" \ + "led stat 1;\0" \ + "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \ + "net_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootfile ${project_dir}/kernel/uImage;" \ + "setenv rootpath /home/projects/${project_dir}/rootfs;" \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs ${mtdparts} " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "nand_boot=echo Booting from nand; " \ + "if test ${upgrade_available} -eq 1; then " \ + "if test ${bootcount} -gt ${bootlimit}; " \ + "then " \ + "setenv upgrade_available 0;" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; then " \ + "setenv partitionset_active B; " \ + "env delete A; " \ + "fi;" \ + "if test -n ${B}; then " \ + "setenv partitionset_active A; " \ + "env delete B; " \ + "fi;" \ + "saveenv; " \ + "fi;" \ + "fi;" \ + "echo set ${partitionset_active}...;" \ + "run nand_args; " \ + "nand read.i ${kloadaddr} ${nand_src_addr} " \ + "${nand_img_size}; bootm ${kloadaddr}\0" \ + "net_nfs=echo Booting from network ...; " \ + "run net_args; " \ + "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \ + "bootm ${kloadaddr}\0" \ + "flash_self=run nand_boot\0" \ + "flash_self_test=setenv testargs test; " \ + "run nand_boot\0" \ + "dfu_start=echo Preparing for dfu mode ...; " \ + "run dfu_args; \0" \ + "preboot=echo; "\ + "echo Type 'run flash_self' to use kernel and root " \ + "filesystem on memory; echo Type 'run flash_self_test' to " \ + "use kernel and root filesystem on memory, boot in test " \ + "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \ + "from memory and root filesystem over NFS; echo Type " \ + "'run net_nfs' to get Kernel over TFTP and mount root " \ + "filesystem over NFS; " \ + "echo Set partitionset_active variable to 'A' " \ + "or 'B' to select kernel and rootfs partition; " \ + "echo" \ + "\0" + +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ + /* to access nand at */ + /* CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND + devices */ +#if !defined(CONFIG_SPI_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#endif +#endif + +#define CONFIG_OMAP_GPIO + +/* Watchdog */ +#define CONFIG_HW_WATCHDOG + +/* Stop autoboot with ESC ESC key detected */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ + "press \"\" to stop\n", bootdelay + +/* Reboot after 60 sec if bootcmd fails */ +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME 60 + +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_ENV + +/* Enable Device-Tree (FDT) support */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_FDT + +#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index b787270670..71eb81c2f7 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -17,13 +17,14 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */ #define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* input clock of PLL (the SMDK2410 has 12MHz input clock) */ @@ -101,8 +102,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -124,8 +123,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x30800000 -#define CONFIG_SYS_HZ 1000 - /* support additional compression methods */ #define CONFIG_BZIP2 #define CONFIG_LZO diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 183aae726d..3b06d305db 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,9 +9,28 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H -#include +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING -#undef CONFIG_DEFAULT_DEVICE_TREE -#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250 +#include + +/* PMIC */ +#define CONFIG_POWER_MAX77686 + +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "SMDK5250 # " +#define CONFIG_IDENT_STRING " for SMDK5250" + +/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h new file mode 100644 index 0000000000..61f582f375 --- /dev/null +++ b/include/configs/smdk5420.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG SMDK5420 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_SMDK5420_H +#define __CONFIG_SMDK5420_H + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + +#include + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SMDK5420 /* which is in a SMDK5420 */ + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_PROMPT "SMDK5420 # " +#define CONFIG_IDENT_STRING " for SMDK5420" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +/* USB */ +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_SMDK5420_H */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index a572e629da..982d0dcea3 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -34,6 +34,9 @@ /* DRAM Base */ #define CONFIG_SYS_SDRAM_BASE 0x30000000 +/* Text Base */ +#define CONFIG_SYS_TEXT_BASE 0x34800000 + #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG @@ -44,6 +47,10 @@ * 1MB = 0x100000, 0x100000 = 1024 * 1024 */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* Small malloc pool before relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + /* * select serial console configuration */ @@ -163,8 +170,6 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000) #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_HZ 1000 - /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ @@ -216,4 +221,12 @@ #define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ #endif /* CONFIG_CMD_NET */ +#define CONFIG_OF_LIBFDT + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL + #endif /* __CONFIG_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 0496661b20..655025c912 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -9,76 +9,45 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "exynos4-common.h" + +#undef CONFIG_BOARD_COMMON +#undef CONFIG_USB_GADGET +#undef CONFIG_USB_GADGET_S3C_UDC_OTG +#undef CONFIG_USB_GADGET_S3C_UDC_OTG_PHY +#undef CONFIG_CMD_USB_MASS_STORAGE +#undef CONFIG_REVISION_TAG +#undef CONFIG_CMD_THOR_DOWNLOAD +#undef CONFIG_CMD_DFU + /* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* S5P Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F - /* Mach Type */ #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 -/* Keep L2 Cache Disabled */ -#define CONFIG_L2_OFF 1 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000 -/* input clock of PLL: SMDKV310 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 #define S5P_CHECK_LPA 0xABAD0000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - /* select serial console configuration */ #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ -#define CONFIG_BAUDRATE 115200 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI - -/* PWM */ -#define CONFIG_PWM 1 - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* Command definition*/ -#include - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP -#define CONFIG_CMD_MMC #define CONFIG_CMD_NET -#define CONFIG_CMD_FAT - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* MMC SPL */ -#define CONFIG_SPL #define CONFIG_SKIP_LOWLEVEL_INIT #define COPY_BL2_FNPTR_ADDR 0x00002488 @@ -87,22 +56,13 @@ #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "SMDKV310 # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) -#define CONFIG_SYS_HZ 1000 - /* SMDKV310 has 4 bank of DRAM */ #define CONFIG_NR_DRAM_BANKS 4 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ @@ -116,8 +76,6 @@ #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE /* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for SMDKC210/V310" #define CONFIG_CLK_1000_400_200 @@ -131,7 +89,6 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_DOS_PARTITION 1 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) @@ -151,6 +108,4 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 17eb5f2455..9fa644f7c2 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -13,14 +13,19 @@ /* SoC type is defined in boards.cfg */ #include -#include +#include -#define CONFIG_SYS_TEXT_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x21f00000 /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* CPU */ #define CONFIG_ARCH_CPU_INIT @@ -29,7 +34,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_FIT @@ -60,11 +64,13 @@ #define CONFIG_RMII #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R +#define CONFIG_AT91_WANTS_COMMON_PHY #define CONFIG_TFTP_PORT #define CONFIG_TFTP_TSIZE /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT @@ -74,7 +80,6 @@ #define CONFIG_USB_STORAGE /* GPIOs and IO expander */ -#define CONFIG_AT91_LEGACY #define CONFIG_ATMEL_LEGACY #define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 @@ -84,8 +89,10 @@ /* UARTs/Serial console */ #define CONFIG_ATMEL_USART +#ifndef CONFIG_DM_SERIAL #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS +#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_PROMPT "Snapper> " @@ -159,7 +166,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C -#undef CONFIG_CMD_GPIO +#define CONFIG_CMD_GPIO #define CONFIG_CMD_USB #define CONFIG_CMD_MII #define CONFIG_CMD_NAND diff --git a/include/configs/snow.h b/include/configs/snow.h index ed5c0b614f..ce6676eae7 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,9 +9,29 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H -#include +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING -#undef CONFIG_DEFAULT_DEVICE_TREE -#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow +#include +#include + + +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ +#define CONFIG_POWER_TPS65090_I2C +#define CONFIG_DM_CROS_EC + +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "snow # " +#define CONFIG_IDENT_STRING " for snow" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/snowball.h b/include/configs/snowball.h index edc426aa0d..dacb5604cd 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -23,11 +23,9 @@ * (easy to change) */ #define CONFIG_U8500 -#define CONFIG_L2_OFF #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF -#define CONFIG_SYS_HZ 1000 /* must be 1000 */ /*----------------------------------------------------------------------- * Size of environment and malloc() pool @@ -43,8 +41,6 @@ #define CONFIG_ENV_SIZE (8*1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ - #define CONFIG_ENV_IS_IN_MMC #define CONFIG_CMD_ENV #define CONFIG_CMD_SAVEENV diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h new file mode 100644 index 0000000000..17eab01776 --- /dev/null +++ b/include/configs/socfpga_common.h @@ -0,0 +1,307 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* Virtual target or real hardware */ + +#define CONFIG_SYS_THUMB_BUILD + + +/* + * High level configuration + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CLOCKS + +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x0 +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 +#endif + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Cache + */ +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS + +/* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 + */ +#endif + +/* + * Ethernet on SoC (EMAC) + */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_MII +#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) +#define CONFIG_PHYLIB +#define CONFIG_PHY_GIGE +#endif + +/* + * FPGA Driver + */ +#ifdef CONFIG_CMD_FPGA +#define CONFIG_FPGA +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_SOCFPGA +#define CONFIG_FPGA_COUNT 1 +#endif + +/* + * L4 OSC1 Timer 0 + */ +/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#define CONFIG_SYS_TIMER_RATE 2400000 +#else +#define CONFIG_SYS_TIMER_RATE 25000000 +#endif + +/* + * L4 Watchdog + */ +#ifdef CONFIG_HW_WATCHDOG +#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +#define CONFIG_DW_WDT_CLOCK_KHZ 25000 +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 +#endif + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +/* FIXME */ +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ +#endif + +/* + * I2C support + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW +#define CONFIG_SYS_I2C_BUS_MAX 4 +#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS +#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS +#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS +#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS +/* Using standard mode which the speed up to 100Kb/s */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SPEED1 100000 +#define CONFIG_SYS_I2C_SPEED2 100000 +#define CONFIG_SYS_I2C_SPEED3 100000 +/* Address of device when used as slave */ +#define CONFIG_SYS_I2C_SLAVE 0x02 +#define CONFIG_SYS_I2C_SLAVE1 0x02 +#define CONFIG_SYS_I2C_SLAVE2 0x02 +#define CONFIG_SYS_I2C_SLAVE3 0x02 +#ifndef __ASSEMBLY__ +/* Clock supplied to I2C controller in unit of MHz */ +unsigned int cm_get_l4_sp_clk_hz(void); +#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) +#endif +#define CONFIG_CMD_I2C + +/* + * QSPI support + */ +#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ +#define CONFIG_CMD_DM +#define CONFIG_DM +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH +#define CONFIG_CADENCE_QSPI +/* Enable multiple SPI NOR flash manufacturers */ +#define CONFIG_SPI_FLASH /* SPI flash subsystem */ +#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ +#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ +#define CONFIG_SPI_FLASH_MTD +/* QSPI reference clock */ +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif +#define CONFIG_CQSPI_DECODER 0 +#define CONFIG_CMD_SF +#endif + +#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */ +#define CONFIG_CMD_DM +#define CONFIG_DM +#define CONFIG_DM_SPI +#define CONFIG_DESIGNWARE_SPI +#define CONFIG_CMD_SPI +#endif + +/* + * Serial Driver + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550_CLK 1000000 +#else +#define CONFIG_SYS_NS16550_CLK 100000000 +#endif +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_STORAGE +/* + * NOTE: User must define either of the following to select which + * of the two USB controllers available on SoCFPGA to use. + * The DWC2 driver doesn't support multiple USB controllers. + * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS + * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS + */ +#endif + +/* + * USB Gadget (DFU, UMS) + */ +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_MASS_STORAGE + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ +#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ +#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM +#ifndef CONFIG_G_DNL_MANUFACTURER +#define CONFIG_G_DNL_MANUFACTURER "Altera" +#endif +#endif + +/* + * U-Boot environment + */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 4096 + +/* + * SPL + * + * SRAM Memory layout: + * + * 0xFFFF_0000 ...... Start of SRAM + * 0xFFFF_xxxx ...... Top of stack (grows down) + * 0xFFFF_yyyy ...... Malloc area + * 0xFFFF_zzzz ...... Global Data + * 0xFFFF_FF00 ...... End of SRAM + */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) + +#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index b5a7a9addc..755677e14b 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -1,225 +1,94 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2014 Marek Vasut * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H #include +#include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" +#include "../../board/altera/socfpga/pll_config.h" -/* - * High level configuration - */ - -#define CONFIG_ARMV7 -#define CONFIG_L2_OFF -#define CONFIG_SYS_DCACHE_OFF -#undef CONFIG_USE_IRQ - -#define CONFIG_MISC_INIT_R -#define CONFIG_SINGLE_BOOTLOADER -#define CONFIG_SOCFPGA - -#define CONFIG_SYS_TEXT_BASE 0x08000040 -#define V_NS16550_CLK 1000000 -#define CONFIG_BAUDRATE 57600 -#define CONFIG_SYS_HZ 1000 -#define CONFIG_TIMER_CLOCK_KHZ 2400 -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * Display CPU and Board Info - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* - * Enable early stage initialization at C environment - */ -#define CONFIG_BOARD_EARLY_INIT_F - -/* flat device tree */ -#define CONFIG_OF_LIBFDT -/* skip updating the FDT blob */ -#define CONFIG_FDT_BLOB_SKIP_UPDATE -/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ -#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) - -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) - -/* - * Memory allocation (MALLOC) - */ -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE 1024 -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* SP location before relocation, must use scratch RAM */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -/* Reserving 0x100 space at back of scratch RAM for debug info */ -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -/* Stack pointer prior relocation, must situated at on-chip RAM */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - - -/* - * Command line configuration. - */ +/* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH #include -/* FAT file system support */ +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT - - -/* - * Misc - */ -#define CONFIG_DOS_PARTITION 1 - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#define CONFIG_REGEX /* Enable regular expression support */ + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" #endif +#define CONFIG_LOADADDR 0x8000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 -/* - * Environment setup - */ - -/* Delay before automatically booting the default image */ -#define CONFIG_BOOTDELAY 3 -/* Enable auto completion of commands using TAB */ -#define CONFIG_AUTO_COMPLETE -/* use "hush" command parser */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMD_RUN - -#define CONFIG_BOOTCOMMAND "run ramboot" +#endif -/* - * arguments passed to the bootm command. The value of - * CONFIG_BOOTARGS goes into the environment value "bootargs". - * Do note the value will overide also the chosen node in FDT blob. - */ -#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_cyclone5 #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=uImage\0" \ + "bootimage=zImage\0" \ "fdt_addr=100\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ "qspiroot=/dev/mtdblock0\0" \ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ "bootm ${loadaddr} - ${fdt_addr}\0" -/* using environment setting for stdin, stdout, stderr */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* Enable the call to overwrite_console() */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -/* Enable overwrite of previous console environment settings */ -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - - -/* - * Hardware drivers - */ - -/* - * SDRAM Memory Map - */ -/* We have 1 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -/* SDRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x80000000 - -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - -/* - * NS16550 Configuration - */ -#define UART0_BASE SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 UART0_BASE - -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} - -/* - * FLASH - */ -#define CONFIG_SYS_NO_FLASH - -/* - * L4 OSC1 Timer 0 - */ -/* This timer use eosc1 where the clock frequency is fixed - * throughout any condition */ -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS - -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0xFFFFFFFF - -#define CONFIG_ENV_IS_NOWHERE - -/* - * SPL "Second Program Loader" aka Initial Software - */ - -/* Enable building of SPL globally */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK - -/* TEXT_BASE for linking the SPL binary */ -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 - -/* Stack size for SPL */ -#define CONFIG_SPL_STACK_SIZE (4 * 1024) - -/* MALLOC size for SPL */ -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) - -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_BOARD_INIT - -#define CHUNKSZ_CRC32 (1 * 1024) - -#define CONFIG_CRC32_VERIFY - -/* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" - -/* Support for common/libcommon.o in SPL binary */ -#define CONFIG_SPL_LIBCOMMON_SUPPORT -/* Support for lib/libgeneric.o in SPL binary */ -#define CONFIG_SPL_LIBGENERIC_SUPPORT +/* The rest of the configuration is shared */ +#include -#endif /* __CONFIG_H */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index e73f9c174c..9b54ba6866 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -7,7 +7,7 @@ * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -25,9 +25,7 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_MPC8544 1 -#define CONFIG_SOCRATES 1 #define CONFIG_SYS_TEXT_BASE 0xfff80000 @@ -80,7 +78,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -343,7 +341,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -354,7 +351,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -365,7 +361,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h deleted file mode 100644 index 564f3645c9..0000000000 --- a/include/configs/spc1920.h +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de - * - * Configuation settings for the SPC1920 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __H -#define __CONFIG_H - -#define CONFIG_SPC1920 1 /* SPC1920 board */ -#define CONFIG_MPC885 1 /* MPC885 CPU */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_MII -#define CONFIG_MII_INIT 1 -#undef CONFIG_ETHER_ON_FEC1 -#define CONFIG_ETHER_ON_FEC2 -#define FEC_ENET -#define CONFIG_FEC2_PHY 1 - -#define CONFIG_BAUDRATE 19200 - -/* use PLD CLK4 instead of brg */ -#define CONFIG_SYS_SPC1920_SMC1_CLK4 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xC0000000 - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_LAST_STAGE_INIT - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm" - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm fe080000" - -#undef CONFIG_BOOTARGS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ -#define CONFIG_SYS_HUSH_PARSER - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ - -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */ - -/* - * Flash - */ -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -#ifdef CONFIG_CMD_DATE -# define CONFIG_RTC_DS3231 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#endif - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if defined(CONFIG_CMD_I2C) -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_FRC) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* #define CONFIG_SYS_SCCR SCCR_TBS */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register - *----------------------------------------------------------------------- - * Set to zero to prevent the processor from entering debug mode - */ -#define CONFIG_SYS_DER 0 - - -/* Because of the way the 860 starts up and assigns CS0 the entire - * address space, we have to set the memory controller differently. - * Normally, you write the option register first, and then enable the - * chip select by writing the base register. For CS0, you must write - * the base register first, followed by the option register. - */ - - -/* - * Init Memory Controller: - */ - -/* BR0 and OR0 (FLASH) */ -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_6_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - - -/* - * SDRAM CS1 UPMB - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE -#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */ - -#define CONFIG_SYS_PRELIM_OR1_AM 0xF0000000 -/* #define CONFIG_SYS_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */ -#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING) -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V) - -/* #define CONFIG_SYS_OR1_FINAL ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */ -/* #define CONFIG_SYS_BR1_FINAL ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */ - -#define CONFIG_SYS_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64)) -#define CONFIG_SYS_PTA_PER_CLK 195 -#define CONFIG_SYS_MBMR_PTB 195 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16 -#define CONFIG_SYS_MAR 0x88 - -#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | \ - MBMR_G0CLB_A10 | \ - MBMR_DSB_1_CYCL | \ - MBMR_RLFB_1X | \ - MBMR_WLFB_1X | \ - MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ - -#define CONFIG_SYS_MBMR_9COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | \ - MBMR_G0CLB_A10 | \ - MBMR_DSB_1_CYCL | \ - MBMR_RLFB_1X | \ - MBMR_WLFB_1X | \ - MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ - - -/* - * DSP Host Port Interface CS3 - */ -#define CONFIG_SYS_SPC1920_HPI_BASE 0x90000000 -#define CONFIG_SYS_PRELIM_OR3_AM 0xF8000000 - -#define CONFIG_SYS_OR3 (CONFIG_SYS_PRELIM_OR3_AM | \ - OR_G5LS | \ - OR_SCY_0_CLK | \ - OR_BI) - -#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_16 | \ - BR_V) - -#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \ - MAMR_RLFA_5X | \ - MAMR_WLFA_5X) - -#define CONFIG_SPC1920_HPI_TEST - -#ifdef CONFIG_SPC1920_HPI_TEST -#define HPI_REG(x) (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x))) -#define HPI_HPIC_1 HPI_REG(0) -#define HPI_HPIC_2 HPI_REG(2) -#define HPI_HPIA_1 HPI_REG(0x2000008) -#define HPI_HPIA_2 HPI_REG(0x2000008 + 2) -#define HPI_HPID_INC_1 HPI_REG(0x1000004) -#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2) -#define HPI_HPID_NOINC_1 HPI_REG(0x300000c) -#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2) -#endif /* CONFIG_SPC1920_HPI_TEST */ - -/* - * Ramtron FM18L08 FRAM 32KB on CS4 - */ -#define CONFIG_SYS_SPC1920_FRAM_BASE 0x80100000 -#define CONFIG_SYS_PRELIM_OR4_AM 0xffff8000 -#define CONFIG_SYS_OR4 (CONFIG_SYS_PRELIM_OR4_AM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_4_CLK | \ - OR_TRLX) - -#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) - -/* - * PLD CS5 - */ -#define CONFIG_SYS_SPC1920_PLD_BASE 0x80000000 -#define CONFIG_SYS_PRELIM_OR5_AM 0xffff8000 - -#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR5_AM | \ - OR_CSNT_SAM | \ - OR_ACS_DIV1 | \ - OR_BI | \ - OR_SCY_0_CLK | \ - OR_TRLX) - -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) - -#endif /* __CONFIG_H */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index c11c2b4d05..a11f4ed2e1 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,11 +17,9 @@ /* Ethernet driver configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY -#define CONFIG_DW0_PHY 1 #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ /* USBD driver configuration */ @@ -39,15 +37,23 @@ #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" /* I2C driver configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW +#if defined(CONFIG_SPEAR600) +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#elif defined(CONFIG_SPEAR300) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#endif #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 #define CONFIG_I2C_CHIPADDRESS 0x50 /* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ 1000 /* Flash configuration */ #if defined(CONFIG_FLASH_PNOR) diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 7f4dc5801c..28dddcc5b9 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -37,6 +37,9 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE 0xD2000000 +/* Ethernet PHY configuration */ +#define CONFIG_PHY_NATSEMI + /* Environment Settings */ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY diff --git a/include/configs/spieval.h b/include/configs/spieval.h deleted file mode 100644 index e91f5ae47a..0000000000 --- a/include/configs/spieval.h +++ /dev/null @@ -1,497 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_STK52XX -#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_STK52XX */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#ifdef CONFIG_STK52XX -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_STK52XX */ - -/* - * Video console - */ -#if 1 -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#ifdef CONFIG_STK52XX -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_I2C) - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP - -#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) - #define CONFIG_CMD_IDE - #define CONFIG_CMD_FAT - #define CONFIG_CMD_EXT2 -#endif - -#ifdef CONFIG_STK52XX - #define CONFIG_CMD_USB - #define CONFIG_CMD_FAT -#endif - -#ifdef CONFIG_VIDEO - #define CONFIG_CMD_BMP -#endif - -#ifdef CONFIG_PCI - #define CONFIG_CMD_PCI - #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 -#endif - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * HW-Monitor configuration on Mini-FAP - */ -#if defined (CONFIG_MINIFAP) -#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C -#endif - -/* List of I2C addresses to be verified by POST */ -#if defined (CONFIG_MINIFAP) -#undef CONFIG_SYS_POST_I2C_ADDRS -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ - CONFIG_SYS_I2C_HWMON_ADDR, \ - CONFIG_SYS_I2C_SLAVE} -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#if defined (CONFIG_MINIFAP) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004 -# endif -# endif -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 -#endif - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CONFIG_SYS_CS2_START 0xE5000000 -#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ -#define CONFIG_SYS_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CONFIG_SYS_CS1_START (SM501_FB_BASE) -#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CONFIG_SYS_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h index a9973315c2..01085dc5c1 100644 --- a/include/configs/stamp9g20.h +++ b/include/configs/stamp9g20.h @@ -35,7 +35,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ -#define CONFIG_SYS_HZ 1000 /* 1ms resolution */ /* misc settings */ #define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ @@ -141,11 +140,15 @@ * can enable it here if your baseboard features ethernet. */ -/* #define CONFIG_MACB */ +#define CONFIG_MACB +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #ifdef CONFIG_MACB # define CONFIG_RMII /* use reduced MII inteface */ # define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ +#define CONFIG_AT91_WANTS_COMMON_PHY /* BOOTP and DHCP options */ # define CONFIG_BOOTP_BOOTFILESIZE @@ -165,6 +168,7 @@ /* USB configuration */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h new file mode 100644 index 0000000000..fd9bd638c6 --- /dev/null +++ b/include/configs/stv0991.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, STMicroelectronics, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_STV0991_H +#define __CONFIG_STV0991_H +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_CORTEX_R4 + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_NO_FLASH + +/* ram memory-related information */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define PHYS_SDRAM_1_SIZE 0x00198000 + +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR \ + (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) +#define CONFIG_SYS_MALLOC_F_LEN 0x2000 + +#define CONFIG_DM +/* serial port (PL011) configuration */ +#define CONFIG_BAUDRATE 115200 +#ifdef CONFIG_DM +#define CONFIG_DM_SERIAL +#define CONFIG_PL01X_SERIAL +#else +#define CONFIG_SYS_SERIAL0 0x80406000 +#define CONFIG_CONS_INDEX 0 +#define CONFIG_PL011_SERIAL +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} +#define CONFIG_PL011_CLOCK (2700 * 1000) +#endif + +/* user interface */ +#define CONFIG_SYS_PROMPT "STV0991> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) + +/* MISC */ +#define CONFIG_SYS_LOAD_ADDR 0x00000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +/* U-boot Load Address */ +#define CONFIG_SYS_TEXT_BASE 0x00010000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* GMAC related configs */ + +#define CONFIG_MII +#define CONFIG_PHYLIB +#define CONFIG_CMD_NET +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_PHY_MICREL + +/* Command support defines */ +#define CONFIG_CMD_PING +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ + +#include "config_cmd_default.h" +#undef CONFIG_CMD_SAVEENV + +#define CONFIG_SYS_MEMTEST_START 0x0000 +#define CONFIG_SYS_MEMTEST_END 1024*1024 +#define CONFIG_CMD_MEMTEST + +/* Misc configuration */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "go 0x40040000" +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#endif /* __CONFIG_H */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index c7689a7290..5fb40ebf8b 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -7,7 +7,7 @@ * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* mpc8560ads board configuration file */ @@ -22,7 +22,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ #define CONFIG_MPC8560 1 @@ -98,7 +97,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE @@ -331,7 +330,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* * For booting Linux, the board info and command line data @@ -342,7 +340,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /*Note: change below for your network setting!!! */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index f5f7f54348..914d821905 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -7,7 +7,7 @@ * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* mpc8560ads board configuration file */ @@ -22,7 +22,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ #define CONFIG_MPC8560 1 @@ -112,7 +111,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE @@ -366,7 +365,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* * For booting Linux, the board info and command line data @@ -377,7 +375,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /*Note: change below for your network setting!!! */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h deleted file mode 100644 index ead67453b9..0000000000 --- a/include/configs/stxxtc.h +++ /dev/null @@ -1,487 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * U-Boot port on STx XTc 8xx board - * Mostly copied from Panto's NETTA2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC875 1 /* This is a MPC875 CPU */ -#define CONFIG_STXXTC 1 /* ...on a STx XTc board */ - -#define CONFIG_SYS_TEXT_BASE 0x40F00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ - -#define CONFIG_XIN 10000000 /* 10 MHz input xtal */ - -/* Select one of few clock rates defined later in this file. -*/ -/* #define MPC8XX_HZ 50000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_SOURCE -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 -#undef CONFIG_RMII - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ -#undef CONFIG_FEC1_PHY_NORXERR - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 3 -#undef CONFIG_FEC2_PHY_NORXERR - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif - -/* yes this is weird, I know :) */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000) -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000) -#define CONFIG_ENV_OFFSET_REDUND 0 -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 } - -#define CONFIG_SYS_FLASH_PROTECTION - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 50000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif -#else -#error unsupported freq for XIN (must be 10MHz) -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ - -#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 -#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR4 and OR4 (SDRAM) - * - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define NAND_SIZE 0x00010000 /* 64K */ -#define NAND_BASE 0xF1000000 - -/*****************************************************************************/ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/*****************************************************************************/ - -/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, - * CxOE and CxRESET. We use the CxOE. - */ -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ - -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ - else \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/******************************************************************************/ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 - -/******************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG - -/*****************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_CRC32_VERIFY 1 -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*****************************************************************************/ - -/* pass open firmware flattened device tree */ -#define CONFIG_OF_LIBFDT 1 - -#define OF_TBCLK (MPC8XX_HZ / 16) - -#endif /* __CONFIG_H */ diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h new file mode 100644 index 0000000000..87d269b041 --- /dev/null +++ b/include/configs/sun4i.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * + * Configuration settings for the Allwinner A10 (sun4i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A10 specific configuration + */ +#define CONFIG_CLK_FULL_SPEED 1008000000 + +#define CONFIG_MACH_TYPE 4104 + +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SUNXI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h new file mode 100644 index 0000000000..52e3a6ff01 --- /dev/null +++ b/include/configs/sun5i.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * + * Configuration settings for the Allwinner A13 (sun5i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_CLK_FULL_SPEED 1008000000 + +#define CONFIG_MACH_TYPE 4138 + +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SUNXI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h new file mode 100644 index 0000000000..f5e11ddb69 --- /dev/null +++ b/include/configs/sun6i.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * (C) Copyright 2013 Maxime Ripard + * + * Configuration settings for the Allwinner A31 (sun6i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A31 specific configuration + */ +#define CONFIG_CLK_FULL_SPEED 1008000000 + +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SUNXI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h new file mode 100644 index 0000000000..7cd7890341 --- /dev/null +++ b/include/configs/sun7i.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * Configuration settings for the Allwinner A20 (sun7i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A20 specific configuration + */ +#define CONFIG_CLK_FULL_SPEED 912000000 + +#define CONFIG_MACH_TYPE 4283 + +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SUNXI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_ARMV7_PSCI 1 +#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h new file mode 100644 index 0000000000..3bdedb390c --- /dev/null +++ b/include/configs/sun8i.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2014 Chen-Yu Tsai + * + * Configuration settings for the Allwinner A23 (sun8i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A23 specific configuration + */ +#define CONFIG_CLK_FULL_SPEED 1008000000 + +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SUNXI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h new file mode 100644 index 0000000000..6cfd7e1489 --- /dev/null +++ b/include/configs/sunxi-common.h @@ -0,0 +1,368 @@ +/* + * (C) Copyright 2012-2012 Henrik Nordstrom + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Configuration settings for the Allwinner sunxi series of boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_COMMON_CONFIG_H +#define _SUNXI_COMMON_CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SUNXI /* sunxi family */ +#ifdef CONFIG_SPL_BUILD +#ifndef CONFIG_SPL_FEL +#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ +#endif +#endif + +#include /* get chip and board defs */ + +#define CONFIG_SYS_TEXT_BASE 0x4a000000 + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM) +# define CONFIG_CMD_DM +# define CONFIG_DM_GPIO +# define CONFIG_DM_SERIAL +# define CONFIG_DW_SERIAL +# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#endif + +/* + * Display CPU information + */ +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_SYS_PROMPT "sunxi# " + +/* Serial & console */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +/* ns16550 reg in the low bits of cpu reg */ +#define CONFIG_SYS_NS16550_CLK 24000000 +#ifndef CONFIG_DM_SERIAL +# define CONFIG_SYS_NS16550_REG_SIZE -4 +# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE +# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE +# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE +# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE +# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE +#endif + +/* DRAM Base */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ + +#ifdef CONFIG_AHCI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SUNXI_AHCI +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_CMD_SCSI +#endif + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_SETEXPR + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* mmc config */ +#if !defined(CONFIG_UART0_PORT_F) +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SUNXI +#define CONFIG_MMC_SUNXI_SLOT 0 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ +#endif + +/* 4MB of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) + +/* + * Miscellaneous configurable options + */ +#define CONFIG_CMD_ECHO +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_GENERIC_BOARD + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ + +/* standalone support */ +#define CONFIG_STANDALONE_LOAD_ADDR 0x42000000 + +/* baudrate */ +#define CONFIG_BAUDRATE 115200 + +/* The stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ + +/* FLASH and environment organization */ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ +#define CONFIG_IDENT_STRING " Allwinner Technology" + +#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + +#include +#undef CONFIG_CMD_FPGA + +#define CONFIG_FAT_WRITE /* enable write access */ + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#ifdef CONFIG_SPL_FEL + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" +#define CONFIG_SPL_TEXT_BASE 0x2000 +#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ + +#else /* CONFIG_SPL */ + +#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */ + +#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ + +#define CONFIG_SPL_LIBDISK_SUPPORT + +#if !defined(CONFIG_UART0_PORT_F) +#define CONFIG_SPL_MMC_SUPPORT +#endif + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ +#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ + +#endif /* CONFIG_SPL */ + +/* end of 32 KiB in sram */ +#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK +#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ + +/* I2C */ +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER +#define CONFIG_SPL_I2C_SUPPORT +#endif + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_CMD_I2C + +/* PMU */ +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER +#define CONFIG_SPL_POWER_SUPPORT +#endif + +#ifndef CONFIG_CONS_INDEX +#define CONFIG_CONS_INDEX 1 /* UART0 */ +#endif + +/* GPIO */ +#define CONFIG_SUNXI_GPIO +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_CMD_GPIO + +#ifdef CONFIG_VIDEO +/* + * The amount of RAM that is reserved for the FB. This will not show up as + * RAM to the kernel, but will be reclaimed by a KMS driver in future. + */ +#define CONFIG_SUNXI_FB_SIZE (9 << 20) + +/* Do we want to initialize a simple FB? */ +#define CONFIG_VIDEO_DT_SIMPLEFB + +#define CONFIG_VIDEO_SUNXI + +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_STD_TIMINGS +#define CONFIG_I2C_EDID + +/* allow both serial and cfb console. */ +#define CONFIG_CONSOLE_MUX +/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */ +#define CONFIG_VGA_AS_SINGLE_DEVICE + +#define CONFIG_SYS_MEM_TOP_HIDE ((CONFIG_SUNXI_FB_SIZE + 0xFFF) & ~0xFFF) + +/* To be able to hook simplefb into dt */ +#ifdef CONFIG_VIDEO_DT_SIMPLEFB +#define CONFIG_OF_BOARD_SETUP +#endif + +#endif /* CONFIG_VIDEO */ + +/* Ethernet support */ +#ifdef CONFIG_SUNXI_EMAC +#define CONFIG_MII /* MII PHY management */ +#endif + +#ifdef CONFIG_SUNXI_GMAC +#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ +#define CONFIG_DW_AUTONEG +#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_PHYLIB +#endif + +#ifdef CONFIG_USB_EHCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +#endif + +#ifdef CONFIG_USB_MUSB_SUNXI +#define CONFIG_MUSB_HOST +#define CONFIG_MUSB_PIO_ONLY +#endif + +#if defined CONFIG_USB_EHCI || defined CONFIG_USB_MUSB_SUNXI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_CONSOLE_MUX +#define CONFIG_PREBOOT +#define CONFIG_SYS_STDIO_DEREGISTER +#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE +#endif + +#if !defined CONFIG_ENV_IS_IN_MMC && \ + !defined CONFIG_ENV_IS_IN_NAND && \ + !defined CONFIG_ENV_IS_IN_FAT && \ + !defined CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#ifndef CONFIG_SPL_BUILD +#include + +/* Enable pre-console buffer to get complete log on the VGA console */ +#define CONFIG_PRE_CONSOLE_BUFFER +#define CONFIG_PRE_CON_BUF_SZ (1024 * 1024) +/* Use the room between the end of bootm_size and the framebuffer */ +#define CONFIG_PRE_CON_BUF_ADDR 0x4f000000 + +/* + * 240M RAM (256M minimum minus space for the framebuffer), + * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, + * 1M script, 1M pxe and the ramdisk at the end. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0xf000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "scriptaddr=0x43100000\0" \ + "pxefile_addr_r=0x43200000\0" \ + "ramdisk_addr_r=0x43300000\0" + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_AHCI +#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +#define BOOT_TARGET_DEVICES_SCSI(func) +#endif + +#ifdef CONFIG_USB_EHCI +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#ifdef CONFIG_USB_KEYBOARD +#define CONSOLE_STDIN_SETTINGS \ + "preboot=usb start\0" \ + "stdin=serial,usbkbd\0" +#else +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" +#endif + +#ifdef CONFIG_VIDEO +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" +#else +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + "console=ttyS0,115200\0" \ + BOOTENV + +#else /* ifndef CONFIG_SPL_BUILD */ +#define CONFIG_EXTRA_ENV_SETTINGS +#endif + +#endif /* _SUNXI_COMMON_CONFIG_H */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h deleted file mode 100644 index a6c1f9927b..0000000000 --- a/include/configs/svm_sc8xx.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific, - * for SinoVee Microsystems SC8xx series SBC - * http://www.fel.com.cn (Chinese) - * http://www.sinovee.com (English) - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* Custom configuration */ -/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ -/* SC85T,SC860T, FEL8xx-AT(855T/860T) */ -/*#define CONFIG_FEL8xx_AT */ -/*#define CONFIG_LCD */ -/*#define CONFIG_MPC8XX_LCD*/ -/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ -/* #define CONFIG_50MHz */ -/* #define CONFIG_66MHz */ -/* #define CONFIG_75MHz */ -#define CONFIG_80MHz -/*#define CONFIG_100MHz */ -/* #define CONFIG_BUS_DIV2 1 */ -/* for BOOT device port size */ -/* #define CONFIG_BOOT_8B */ -#define CONFIG_BOOT_16B -/* #define CONFIG_BOOT_32B */ -/* #define CONFIG_CAN_DRIVER */ -/* #define DEBUG */ -#define CONFIG_FEC_ENET - -/* #define CONFIG_SDRAM_16M */ -#define CONFIG_SDRAM_32M -/* #define CONFIG_SDRAM_64M */ -#define CONFIG_SYS_RESET_ADDRESS 0xffffffff -/* - * High Level Configuration Options - * (easy to change) - */ - -/* #define CONFIG_MPC823 1 */ -/* #define CONFIG_MPC850 1 */ -#define CONFIG_MPC855 1 -/* #define CONFIG_MPC860 1 */ -/* #define CONFIG_MPC860T 1 */ - -#undef CONFIG_WATCHDOG /* watchdog */ - -#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ - "bootfile=pImage-sc855t\0" \ - "kernel_addr=48000000\0" \ - "ramdisk_addr=48100000\0" \ - "" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -#ifdef CONFIG_LCD -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_BOOT_8B -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#elif defined (CONFIG_BOOT_16B) -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#elif defined (CONFIG_BOOT_32B) -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -/*#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -*/ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR 0xffffff88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -/*#define CONFIG_SYS_SIUMCR 0x00610c00 */ -#define CONFIG_SYS_SIUMCR 0x00000000 -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR 0x0001 - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC 0x00c3 - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR 0x0000 - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#if defined (CONFIG_100MHz) -#define CONFIG_SYS_PLPRCR 0x06301000 -#define CONFIG_8xx_GCLK_FREQ 100000000 -#elif defined (CONFIG_80MHz) -#define CONFIG_SYS_PLPRCR 0x04f01000 -#define CONFIG_8xx_GCLK_FREQ 80000000 -#elif defined(CONFIG_75MHz) -#define CONFIG_SYS_PLPRCR 0x04a00100 -#define CONFIG_8xx_GCLK_FREQ 75000000 -#elif defined(CONFIG_66MHz) -#define CONFIG_SYS_PLPRCR 0x04101000 -#define CONFIG_8xx_GCLK_FREQ 66000000 -#elif defined(CONFIG_50MHz) -#define CONFIG_SYS_PLPRCR 0x03101000 -#define CONFIG_8xx_GCLK_FREQ 50000000 -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_BUS_DIV2 -#define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL -#else /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR 0x02000000 | SCCR_RTSEL -#endif - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ -#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -/*#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O - */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses - */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers - */ -#define CONFIG_ATAPI -#define CONFIG_SYS_PIO_MODE 0 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0x0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#if defined(CONFIG_100MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 -#define CONFIG_SYS_MxMR_PTx 0x61000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_80MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 -#define CONFIG_SYS_MxMR_PTx 0x4e000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_75MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 -#define CONFIG_SYS_MxMR_PTx 0x49000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_66MHz) -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -/*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */ -#define CONFIG_SYS_OR_TIMING_DOC 0x000003f4 -#define CONFIG_SYS_MxMR_PTx 0x40000000 -#define CONFIG_SYS_MPTPR 0x400 - -#else /* 50 MHz */ -#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 -#define CONFIG_SYS_MxMR_PTx 0x30000000 -#define CONFIG_SYS_MPTPR 0x400 -#endif /*CONFIG_??MHz */ - - -#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) -#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) -#else -#error Boot device port size missing. -#endif - -/* - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_DOC_SHORT_TIMEOUT -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM -#define CONFIG_SYS_DOC_BASE 0x80000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 9ab99244cf..502e795976 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -16,7 +16,6 @@ */ #define CONFIG_460GT 1 /* Specific PPC460GT */ #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 1ed53dbbb1..75609b9f61 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -7,25 +7,11 @@ /* * Corenet DS style board configuration file */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg -#endif - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_NO_FLASH -#endif +#ifndef __T4QDS_H +#define __T4QDS_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_CMD_REGINFO /* High Level Configuration Options */ @@ -33,12 +19,10 @@ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -58,70 +42,16 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_SYS_NO_FLASH -#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_ENV_IS_NOWHERE -#endif -#else -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#endif - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1097) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_IS_IN_REMOTE -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - /* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -129,14 +59,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif -#if 0 -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#endif #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST @@ -145,19 +70,19 @@ unsigned long get_board_ddr_clk(void); /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* * DDR Setup @@ -172,199 +97,20 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 -#define SPD_EEPROM_ADDRESS5 0x55 -#define SPD_EEPROM_ADDRESS6 0x56 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CONFIG_SYS_FSL_DDR3 + /* * IFC Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#ifdef CONFIG_PHYS_64BIT -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#else -#define QIXIS_BASE_PHYS QIXIS_BASE -#endif - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ @@ -376,25 +122,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 @@ -431,89 +171,22 @@ unsigned long get_board_ddr_clk(void); /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 100000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ - -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_MUX_CH_VSC3316_FS 0xc -#define I2C_MUX_CH_VSC3316_BS 0xd - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -/* VSC Crossbar switches */ -#define CONFIG_VSC_CROSSBAR -#define VSC3316_FSM_TX_ADDR 0x70 -#define VSC3316_FSM_RX_ADDR 0x71 - /* * RapidIO */ #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 -#endif #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 -#endif #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_SST -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE 0 - /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. @@ -521,59 +194,32 @@ unsigned long get_board_ddr_clk(void); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ @@ -584,84 +230,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_INTERLAKEN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. - */ -#define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_TERANETICS -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#define FM1_10GEC1_PHY_ADDR 0x0 -#define FM1_10GEC2_PHY_ADDR 0x1 -#define FM2_10GEC1_PHY_ADDR 0x2 -#define FM2_10GEC2_PHY_ADDR 0x3 -#endif - #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_NET_MULTI @@ -723,30 +291,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif -/* -* USB -*/ -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_EXT2 -#define CONFIG_HAS_FSL_DR_USB - -#define CONFIG_MMC - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - /* * Miscellaneous configurable options */ @@ -754,7 +298,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -763,7 +306,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data @@ -775,7 +317,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -788,112 +329,11 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 -#define __USB_PHY_TYPE utmi - -/* - * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be - * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to - * cacheline interleaving. It can be cacheline, page, bank, superbank. - * See doc/README.fsl-ddr for details. - */ -#ifdef CONFIG_PPC_T4240 -#define CTRL_INTLV_PREFERED 3way_4KB -#else -#define CTRL_INTLV_PREFERED cacheline -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t4240qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=t4240qds/t4240qds.dtb\0" \ - "bdev=sda3\0" \ - "c=ffe\0" - -/* For emulation this causes u-boot to jump to the start of the proof point - app code automatically */ -#define CONFIG_PROOF_POINTS \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x29000000 - - -;" \ - "cpu 2 release 0x29000000 - - -;" \ - "cpu 3 release 0x29000000 - - -;" \ - "cpu 4 release 0x29000000 - - -;" \ - "cpu 5 release 0x29000000 - - -;" \ - "cpu 6 release 0x29000000 - - -;" \ - "cpu 7 release 0x29000000 - - -;" \ - "go 0x29000000" - #define CONFIG_HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#ifdef CONFIG_SECURE_BOOT -#include -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/taihu.h b/include/configs/taihu.h index e8d191e7f9..5c0ce7a2e4 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -5,7 +5,7 @@ * (C) Copyright 2005-2007 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -13,7 +13,6 @@ #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_TAIHU 1 /* on a taihu board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 3dbfc6ad1d..3d5c351b1a 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -18,7 +18,6 @@ #define CONFIG_TAISHAN 1 /* Board is taishan */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index c297827d80..9fbe68a8a2 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -14,8 +14,9 @@ * High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0x80008000 @@ -116,14 +117,13 @@ #undef CONFIG_CMD_IMLS #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 400000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_DRIVER_OMAP34XX_I2C - /* * Board NAND Info. @@ -168,7 +168,6 @@ */ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* * Physical Memory Map @@ -182,12 +181,8 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - +#define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ @@ -214,14 +209,12 @@ #define CONFIG_DRIVER_TI_EMAC_USE_RMII #define CONFIG_MII #define CONFIG_EMAC_MDIO_PHY_NUM 0 -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_CONSOLE @@ -252,6 +245,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 @@ -263,6 +257,7 @@ 56, 57, 58, 59, 60, 61, 62, 63} #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE @@ -370,7 +365,7 @@ struct tam3517_module_info { #define TAM3517_READ_EEPROM(info, ret) \ do { \ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ (void *)info, sizeof(*info))) \ ret = 1; \ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h new file mode 100644 index 0000000000..7d2c0d2fa7 --- /dev/null +++ b/include/configs/tao3530.h @@ -0,0 +1,363 @@ +/* + * Configuration settings for the TechNexion TAO-3530 SOM + * equipped on Thunder baseboard. + * + * Edward Lin + * Tapani Utriainen + * + * Copyright (C) 2013 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ + +#define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD + +#define MACH_TYPE_OMAP3_TAO3530 2836 + +#define CONFIG_SDRC /* Has an SDRC controller */ + +#include /* get chip and board defs */ +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ +#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ +#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ + +/* commands to include */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 +/* Environment information */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mpurate=600\0" \ + "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ + "tv_mode=omapfb.mode=tv:ntsc\0" \ + "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ + "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ + "extra_options= \0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=ubi0:rootfs ubi.mtd=4\0" \ + "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "${video_mode} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} " \ + "${extra_options}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "${video_mode} " \ + "${network_setting} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} "\ + "${extra_options}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "TAO-3530 # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* turn on command-line edit/hist/auto */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ + /* defaults */ +#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ +#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ +#define CONFIG_SYS_FLASH_BASE NAND_BASE + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_OMAP3_SPI + +/* + * USB + * + * Currently only EHCI is enabled, the MUSB OTG controller + * is not enabled. + */ + +/* USB EHCI */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 + +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_STORAGE +#define CONGIG_CMD_STORAGE + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +/* + * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: + * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT + */ +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13 } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* + * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the + * older x-loader implementations. And move the BSS area so that it + * doesn't overlap with TEXT_BASE. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h new file mode 100644 index 0000000000..65468ad165 --- /dev/null +++ b/include/configs/taurus.h @@ -0,0 +1,242 @@ +/* + * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards + * (C) Copyright 2013 Siemens AG + * + * Based on: + * U-Boot file: include/configs/at91sam9260ek.h + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include + +#define MACH_TYPE_TAURUS 2067 +#define MACH_TYPE_AXM 2068 + +#define CONFIG_SYS_GENERIC_BOARD + +#if defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#endif +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ + + +#define CONFIG_SYS_TEXT_BASE 0x21000000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ + +/* Misc CPU related */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 3 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND + +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +# define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#endif + +/* NOR flash - no real flash on this board */ +#define CONFIG_SYS_NO_FLASH 1 + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* USB */ +#if defined(CONFIG_BOARD_TAURUS) +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#endif + +/* SPI EEPROM */ +#define CONFIG_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_ATMEL_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define TAURUS_SPI_MASK (1 << 4) +#define TAURUS_SPI_CS_PIN AT91_PIN_PA3 + +#if defined(CONFIG_SPL_BUILD) +/* SPL related */ +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +/* load address */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +/* bootstrap in spi flash , u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET_REDUND 0x180000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256k(env),256k(env_redundant),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "root=/dev/mtdblock7 rw rootfstype=jffs2" + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (14 * 1024) +#define CONFIG_SPL_STACK (16 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_USE_NANDFLASH 1 +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_SIZE (256*1024*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x202A3F01 +#define CONFIG_SYS_MCKR 0x1300 +#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) +#define CONFIG_SYS_AT91_PLLB 0x10193F05 +#endif diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h deleted file mode 100644 index a1b7720796..0000000000 --- a/include/configs/tb0229.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * (C) Copyright 2003 - * Masami Komiya - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for TANBAC TB0229 board using an VR4131 CPU module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ -#define CONFIG_TB0229 1 /* on a TB0229 Board */ - -#ifndef CPU_CLOCK_RATE -#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */ -#endif -#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \ - "echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo Type \\\"run flash_local\\\" to mount local root filesystem;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=dhcp;tftp;run netargs; bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \ - "localargs=setenv bootargs root=1F02 ip=dhcp\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "read-only=readonly\0" \ - "netargs=run nfsargs addmisc\0" \ - "flash_nfs=run nfsargs addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_local=run localargs addmisc;" \ - "bootm ${kernel_addr}\0" \ - "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \ - "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\ - "run addmisc;" \ - "bootm 80400000 80600000\0" \ - "rootpath=/export/miniroot-mipsel\0" \ - "autoload=no\0" \ - "kernel_addr=BFC60000\0" \ - "ramdisk_addr=B0100000\0" \ - "u-boot=u-boot.bin\0" \ - "bootfile=uImage\0" \ - "load=dhcp;tftp 80400000 ${u-boot}\0" \ - "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \ - "update_uboot=run load;" \ - "protect off BFC00000 BFC3FFFF;" \ - "erase BFC00000 BFC3FFFF;" \ - "cp.b 80400000 BFC00000 ${filesize}\0" \ - "update_kernel=run load_kernel;" \ - "erase BFC60000 BFD5FFFF;" \ - "cp.b 80400000 BFC60000 ${filesize}\0" \ - "initenv=erase bfc40000 bfc5ffff\0" \ - "" -/*#define CONFIG_BOOTCOMMAND "run flash_local" */ -#define CONFIG_BOOTCOMMAND "run netboot" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ - -#define CONFIG_SYS_MALLOC_LEN 128*1024 - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4) - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */ - -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xBFC40000 -#define CONFIG_ENV_SIZE 0x20000 - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#define CONFIG_NR_DRAM_BANKS 1 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 16 - -/*----------------------------------------------------------------------- - * Serial Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 18432000 -#define CONFIG_SYS_NS16550_COM1 0xaf000800 - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define CONFIG_RTL8139 - -#endif /* __CONFIG_H */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h new file mode 100644 index 0000000000..e9218f7d81 --- /dev/null +++ b/include/configs/tb100.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2011-2014 Pierrick Hascoet, Abilis Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_TB100_H_ +#define _CONFIG_TB100_H_ + +#include + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x84000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_128M + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_128K +#define CONFIG_SYS_BOOTM_LEN SZ_32M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 166666666 +#define CONFIG_SYS_NS16550_COM1 0xFF100000 +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_BAUDRATE 115200 + +/* + * Ethernet PHY configuration + */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_GIGE + +/* + * Even though the board houses Realtek RTL8211E PHY + * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly. + * In particular "parse_status" reports link is down. + * + * Until Realtek PHY driver is fixed fall back to generic PHY driver + * which implements all required functionality and behaves much more stable. + * + * #define CONFIG_PHY_REALTEK + * + */ + +/* + * Ethernet configuration + */ +#define CONFIG_DESIGNWARE_ETH +#define ETH0_BASE_ADDRESS 0xFE100000 +#define ETH1_BASE_ADDRESS 0xFE110000 + +/* + * Command line configuration + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_PING + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE SZ_2K +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "[tb100]:~# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_TB100_H_ */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h new file mode 100644 index 0000000000..ce651baa70 --- /dev/null +++ b/include/configs/tbs2910.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2014 Soeren Moch + * + * Configuration settings for the TBS2910 MatrixARM board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TBS2910_CONFIG_H +#define __TBS2910_CONFIG_H + +#include "mx6_common.h" +#include +#include + +/* General configuration */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_MACH_TYPE 3980 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Matrix U-Boot> " +#define CONFIG_BOOTDELAY 3 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) + +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#define CONFIG_SYS_BOOTMAPSZ 0x6C000000 +#define CONFIG_SYS_LOAD_ADDR 0x10800000 + +/* Serial console */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX +#define CONFIG_CONS_INDEX 1 + +/* *** Command definition *** */ +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_MEMTEST +#define CONFIG_CMD_TIME + +/* Filesystems / image support */ +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_FS_GENERIC + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_FIT + +/* MMC */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 4 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* Framebuffer */ +#define CONFIG_VIDEO +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_CFB_CONSOLE_ANSI +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CMD_HDMIDETECT +#endif + +/* PCI */ +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#endif + +/* SATA */ +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +/* USB */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE +#define CONFIG_SYS_STDIO_DEREGISTER +#define CONFIG_PREBOOT "if hdmidet; then usb start; fi" +#endif /* CONFIG_USB_KEYBOARD */ +#endif /* CONFIG_CMD_USB */ + +/* RTC */ +#define CONFIG_CMD_DATE +#ifdef CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_RTC_DS1307 +#define CONFIG_SYS_RTC_BUS_NUM 2 +#endif + +/* I2C */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_I2C_EDID +#endif + +/* Fuses */ +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* Flash and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 2 +#define CONFIG_SYS_MMC_ENV_PART 1 +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (384 * 1024) +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ + "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ + "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ + "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \ + "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \ + "${bootargs_mmc3}\0" \ + "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ + "rdinit=/sbin/init enable_wait_mode=off\0" \ + "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ + "mmc read 0x10800000 0x800 0x4000; bootm\0" \ + "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ + "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ + "run bootargs_upd; " \ + "bootm 0x10800000 0x10d00000\0" \ + "console=ttymxc0\0" \ + "fan=gpio set 92\0" \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan; " \ + "if run bootcmd_up1; then " \ + "run bootcmd_up2; " \ + "else " \ + "run bootcmd_mmc; " \ + "fi" + +#endif /* __TBS2910_CONFIG_H * */ diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 241f21051e..e96a7427e5 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -68,7 +68,7 @@ #define CONFIG_HOSTNAME tcm-bf518 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -103,8 +103,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -117,7 +117,6 @@ #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - /* * Pull in common ADI header for remaining command/environment setup */ diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 2adb071ddb..42129fb7d8 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -55,7 +55,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) @@ -73,7 +73,7 @@ #define CONFIG_HOSTNAME tcm-bf537 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings @@ -112,8 +112,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif @@ -122,8 +122,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* @@ -144,7 +144,7 @@ #define FLASHBOOT_ENV_SETTINGS \ "flashboot=flread 20040000 1000000 300000;" \ "bootm 0x1000000\0" - +#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h new file mode 100644 index 0000000000..e37b23359b --- /dev/null +++ b/include/configs/tec-ng.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra30-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra30 (TEC-NG) # " +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* SPI */ +#define CONFIG_TEGRA20_SLINK +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +/* Tag support */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +/* support the new (FDT-based) image format */ +#define CONFIG_FIT + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h index 90e7b7ad97..9ea4ff4971 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -12,11 +12,6 @@ #include "tegra20-common.h" -/* Enable fdt support for TEC. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-tec -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (TEC) # " #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index a3242fe612..c3ad8beb90 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -8,99 +8,16 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H -#ifdef CONFIG_BOOTCOMMAND - -#define BOOTCMDS_COMMON "" - -#else - -#ifdef CONFIG_CMD_MMC -#define BOOTCMDS_MMC \ - "mmc_boot=" \ - "setenv devtype mmc; " \ - "if mmc dev ${devnum}; then " \ - "run scan_boot; " \ - "fi\0" \ - "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" \ - "bootcmd_mmc1=setenv devnum 1; run mmc_boot;\0" -#define BOOT_TARGETS_MMC "mmc1 mmc0" +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#include #else -#define BOOTCMDS_MMC "" -#define BOOT_TARGETS_MMC "" -#endif - -#ifdef CONFIG_CMD_USB -#define BOOTCMD_INIT_USB "run usb_init; " -#define BOOTCMDS_USB \ - "usb_init=" \ - "if ${usb_need_init}; then " \ - "set usb_need_init false; " \ - "usb start 0; " \ - "fi\0" \ - \ - "usb_boot=" \ - "setenv devtype usb; " \ - BOOTCMD_INIT_USB \ - "if usb dev ${devnum}; then " \ - "run scan_boot; " \ - "fi\0" \ - \ - "bootcmd_usb0=setenv devnum 0; run usb_boot;\0" -#define BOOT_TARGETS_USB "usb0" -#else -#define BOOTCMD_INIT_USB "" -#define BOOTCMDS_USB "" -#define BOOT_TARGETS_USB "" -#endif - -#ifdef CONFIG_CMD_DHCP -#define BOOTCMDS_DHCP \ - "bootcmd_dhcp=" \ - BOOTCMD_INIT_USB \ - "if dhcp ${scriptaddr} boot.scr.uimg; then "\ - "source ${scriptaddr}; " \ - "fi\0" -#define BOOT_TARGETS_DHCP "dhcp" -#else -#define BOOTCMDS_DHCP "" -#define BOOT_TARGETS_DHCP "" -#endif - -#define BOOTCMDS_COMMON \ - "rootpart=1\0" \ - \ - "script_boot=" \ - "if load ${devtype} ${devnum}:${rootpart} " \ - "${scriptaddr} ${prefix}${script}; then " \ - "echo ${script} found! Executing ...;" \ - "source ${scriptaddr};" \ - "fi;\0" \ - \ - "scan_boot=" \ - "echo Scanning ${devtype} ${devnum}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "for script in ${boot_scripts}; do " \ - "run script_boot; " \ - "done; " \ - "done;\0" \ - \ - "boot_targets=" \ - BOOT_TARGETS_MMC " " \ - BOOT_TARGETS_USB " " \ - BOOT_TARGETS_DHCP " " \ - "\0" \ - \ - "boot_prefixes=/ /boot/\0" \ - \ - "boot_scripts=boot.scr.uimg boot.scr\0" \ - \ - BOOTCMDS_MMC \ - BOOTCMDS_USB \ - BOOTCMDS_DHCP - -#define CONFIG_BOOTCOMMAND \ - "for target in ${boot_targets}; do run bootcmd_${target}; done" - +#define BOOTENV #endif #ifdef CONFIG_TEGRA_KEYBOARD @@ -129,13 +46,20 @@ "stderr=serial" STDOUT_LCD "\0" \ "" +#ifndef BOARD_EXTRA_ENV_SETTINGS +#define BOARD_EXTRA_ENV_SETTINGS +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - BOOTCMDS_COMMON + "fdt_high=ffffffff\0" \ + "initrd_high=ffffffff\0" \ + BOOTENV \ + BOARD_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) -#define CONFIG_FDT_SPI +#define CONFIG_TEGRA_SPI #endif /* overrides for SPL build here */ @@ -143,11 +67,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT -/* remove devicetree support */ -#ifdef CONFIG_OF_CONTROL -#undef CONFIG_OF_CONTROL -#endif - /* remove I2C support */ #ifdef CONFIG_SYS_I2C_TEGRA #undef CONFIG_SYS_I2C_TEGRA diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h new file mode 100644 index 0000000000..287460c132 --- /dev/null +++ b/include/configs/tegra-common-usb-gadget.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA_COMMON_USB_GADGET_H_ +#define _TEGRA_COMMON_USB_GADGET_H_ + +#ifndef CONFIG_SPL_BUILD +/* USB gadget mode support*/ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_CI_UDC +#define CONFIG_CI_UDC_HAS_HOSTPC +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_G_DNL_VENDOR_NUM 0x0955 +#define CONFIG_G_DNL_PRODUCT_NUM 0x701A +#define CONFIG_G_DNL_MANUFACTURER "NVIDIA" +#define CONFIG_USBDOWNLOAD_GADGET +/* USB mass storage protocol */ +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_CMD_USB_MASS_STORAGE +/* DFU protocol */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 * 1024 * 1024) +#define CONFIG_CMD_DFU +#ifdef CONFIG_MMC +#define CONFIG_DFU_MMC +#endif +#ifdef CONFIG_SPI_FLASH +#define CONFIG_DFU_SF +#endif +#endif + +#endif /* _TEGRA_COMMON_USB_GADGET_H_ */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index ccd68a19fd..8f1e370915 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -7,20 +7,30 @@ #ifndef _TEGRA_COMMON_H_ #define _TEGRA_COMMON_H_ -#include +#include #include /* * High Level Configuration Options */ #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ -#define CONFIG_TEGRA /* which is a Tegra generic machine */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include /* get chip and board defs */ +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_SERIAL +#endif +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH +#define CONFIG_DM_I2C + +#define CONFIG_SYS_TIMER_RATE 1000000 +#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE + /* * Display CPU and Board information */ @@ -28,7 +38,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ /* Environment */ #define CONFIG_ENV_VARS_UBOOT_CONFIG @@ -38,14 +47,28 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + +#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#else +#define CONFIG_TEGRA_SERIAL +#endif +#define CONFIG_SYS_NS16550 + +/* + * Common HW configuration. + * If this varies between SoCs later, move to tegraNN-common.h + * Note: This is number of devices, not max device ID. + */ +#define CONFIG_SYS_MMC_MAX_DEVICE 4 /* * select serial console configuration @@ -68,33 +91,20 @@ #undef CONFIG_CMD_NET /* network support */ /* turn on command-line edit/hist/auto */ -#define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE /* turn on commonly used storage-related commands */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION #define CONFIG_PARTITION_UUIDS -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_PART #define CONFIG_SYS_NO_FLASH #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT V_PROMPT /* * Increasing the size of the IO buffer as default nfsargs size is more @@ -111,7 +121,9 @@ #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) -#define CONFIG_SYS_HZ 1000 +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USE_ARCH_MEMCPY +#endif /*----------------------------------------------------------------------- * Physical Memory Map @@ -134,10 +146,8 @@ #define CONFIG_TEGRA_GPIO #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM -#define CONFIG_CMD_BOOTZ /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_BOARD_INIT @@ -157,4 +167,8 @@ #define CONFIG_BOUNCE_BUFFER #define CONFIG_CRC32_VERIFY +#ifndef CONFIG_SPL_BUILD +#include +#endif + #endif /* _TEGRA_COMMON_H_ */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 44e98e5019..9eba5d517d 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -18,16 +18,14 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * NS16550 Configuration */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* - * High Level Configuration Options - */ -#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */ - /* Environment information, boards can override if required */ #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ @@ -48,6 +46,9 @@ * scriptaddr can be pretty much anywhere that doesn't conflict with something * else. Put it above BOOTMAPSZ to eliminate conflicts. * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * * kernel_addr_r must be within the first 128M of RAM in order for the * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will * decompress itself to 0x8000 after the start of RAM, kernel_addr_r @@ -65,6 +66,7 @@ */ #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=0x81000000\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" @@ -74,10 +76,9 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 #define CONFIG_SPL_STACK 0x800ffffc -/* Total I2C ports on Tegra114 */ -#define TEGRA_I2C_NUM_CONTROLLERS 5 - /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h new file mode 100644 index 0000000000..f2b3774da8 --- /dev/null +++ b/include/configs/tegra124-common.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_COMMON_H_ +#define _TEGRA124_COMMON_H_ + +#include "tegra-common.h" + +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* Environment information, boards can override if required */ +#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x8010E000 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 + +#endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index d5e9ee4062..6330281df7 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -9,6 +9,9 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ @@ -21,11 +24,6 @@ */ #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ -/* - * High Level Configuration Options - */ -#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ - /* Environment information, boards can override if required */ #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ @@ -46,6 +44,9 @@ * scriptaddr can be pretty much anywhere that doesn't conflict with something * else. Put it above BOOTMAPSZ to eliminate conflicts. * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * * kernel_addr_r must be within the first 128M of RAM in order for the * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will * decompress itself to 0x8000 after the start of RAM, kernel_addr_r @@ -63,6 +64,7 @@ */ #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x10000000\0" \ + "pxefile_addr_r=0x10100000\0" \ "kernel_addr_r=0x01000000\0" \ "fdt_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x02100000\0" @@ -93,9 +95,7 @@ */ #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 #define CONFIG_EHCI_IS_TDI - -/* Total I2C ports on Tegra20 */ -#define TEGRA_I2C_NUM_CONTROLLERS 4 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 #define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_SYS_NAND_ONFI_DETECTION diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 5ac8816504..bfdbeb70d2 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -9,6 +9,9 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ @@ -20,11 +23,6 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* - * High Level Configuration Options - */ -#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */ - /* Environment information, boards can override if required */ #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ @@ -45,6 +43,9 @@ * scriptaddr can be pretty much anywhere that doesn't conflict with something * else. Put it above BOOTMAPSZ to eliminate conflicts. * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * * kernel_addr_r must be within the first 128M of RAM in order for the * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will * decompress itself to 0x8000 after the start of RAM, kernel_addr_r @@ -62,6 +63,7 @@ */ #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=0x81000000\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" @@ -71,10 +73,9 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 #define CONFIG_SPL_STACK 0x800ffffc -/* Total I2C ports on Tegra30 */ -#define TEGRA_I2C_NUM_CONTROLLERS 5 - /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 #endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index eac5ad0243..deb6bb2b8f 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -20,12 +20,10 @@ #define CONFIG_TI814X #define CONFIG_SYS_NO_FLASH #define CONFIG_OMAP +#define CONFIG_OMAP_COMMON #include -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (1024 << 10) #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -119,12 +117,11 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MEMTEST_START PHYS_DRAM_1 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + PHYS_DRAM_1_SIZE - (8 << 12)) #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ #define CONFIG_OMAP_GPIO #define CONFIG_MMC @@ -139,11 +136,10 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ #define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) @@ -152,7 +148,6 @@ */ #define CONFIG_SYS_TIMERBASE 0x4802E000 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 @@ -173,7 +168,6 @@ #define CONFIG_ENV_IS_NOWHERE /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40300000 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) @@ -184,8 +178,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT @@ -229,7 +223,6 @@ #define CONFIG_CMD_MII #define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME @@ -239,7 +232,6 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_ET1011C #define CONFIG_PHY_ET1011C_TX_CLK_FIX diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h new file mode 100644 index 0000000000..87a4efcd5a --- /dev/null +++ b/include/configs/ti816x_evm.h @@ -0,0 +1,178 @@ +/* + * ti816x_evm.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TI816X_EVM_H +#define __CONFIG_TI816X_EVM_H + +#define CONFIG_TI81XX +#define CONFIG_TI816X +#define CONFIG_SYS_NO_FLASH +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +#define CONFIG_ARCH_CPU_INIT + +#include + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) +#define CONFIG_SYS_LONGHELP /* undef save memory */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "u-boot/ti816x# " +#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* required for ramdisk support */ + +#include /* u-boot default commands */ + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x81000000\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan;" \ + "fatload mmc 0 ${loadaddr} uImage;" \ + "bootm ${loadaddr}" \ + +#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ + +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ + +#define CONFIG_CMD_ASKEN +#define CONFIG_CMD_ECHO +#define CONFIG_OMAP_GPIO +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_FS_FAT + +/* + * Only one of the following two options (DDR3/DDR2) should be enabled + * CONFIG_TI816X_EVM_DDR2 + * CONFIG_TI816X_EVM_DDR3 + */ +#define CONFIG_TI816X_EVM_DDR3 + +/* + * Supported values: 400, 531, 675 or 796 MHz + */ +#define CONFIG_TI816X_DDR_PLL_796 + +#define CONFIG_TI816X_USE_EMIF0 1 +#define CONFIG_TI816X_USE_EMIF1 1 + + +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ +#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ + +#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/** + * Platform/Board specific defs + */ +#define CONFIG_SYS_CLK_FREQ 27000000 +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +#undef CONFIG_NAND_OMAP_GPMC + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ + +#define CONFIG_BAUDRATE 115200 + +/* allow overwriting serial config and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SERIAL1 +#define CONFIG_SERIAL2 +#define CONFIG_SERIAL3 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define CONFIG_ENV_IS_NOWHERE + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40400000 +#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#endif diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h new file mode 100644 index 0000000000..598526bf95 --- /dev/null +++ b/include/configs/ti_am335x_common.h @@ -0,0 +1,107 @@ +/* + * ti_am335x_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/am3359#technicaldocuments + */ + +#ifndef __CONFIG_TI_AM335X_COMMON_H__ +#define __CONFIG_TI_AM335X_COMMON_H__ + +#define CONFIG_AM33XX +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC + +#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_DM +# define CONFIG_DM +#endif +# define CONFIG_CMD_DM +# define CONFIG_DM_GPIO +# define CONFIG_DM_SERIAL +# define CONFIG_OMAP_SERIAL +# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#endif + +#include + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif +#define CONFIG_SYS_NS16550_CLK 48000000 + +/* Network defines. */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ + +/* + * RTC related defines. To use bootcount you must set bootlimit in the + * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT + * in the board config. + */ +#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 + +/* Enable the HW watchdog, since we can use this with bootcount */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_OMAP_WATCHDOG + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +/* Enable the watchdog inside of SPL */ +#define CONFIG_SPL_WATCHDOG_SUPPORT + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) +#define CONFIG_BOARD_EARLY_INIT_F +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + +/* Now bring in the rest of the common code. */ +#include + +#endif /* __CONFIG_TI_AM335X_COMMON_H__ */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h new file mode 100644 index 0000000000..2bd116477c --- /dev/null +++ b/include/configs/ti_armv7_common.h @@ -0,0 +1,279 @@ +/* + * ti_armv7_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The various ARMv7 SoCs from TI all share a number of IP blocks when + * implementing a given feature. Rather than define these in every + * board or even SoC common file, we define a common file to be re-used + * in all cases. While technically true that some of these details are + * configurable at the board design, they are common throughout SoC + * reference platforms as well as custom designs and become de facto + * standards. + */ + +#ifndef __CONFIG_TI_ARMV7_COMMON_H__ +#define __CONFIG_TI_ARMV7_COMMON_H__ + +/* Common define for many platforms. */ +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD + +/* + * We typically do not contain NOR flash. In the cases where we do, we + * undefine this later. + */ +#define CONFIG_SYS_NO_FLASH + +/* Support both device trees and ATAGs. */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Our DDR memory always starts at 0x80000000 and U-Boot shall have + * relocated itself to higher in memory by the time this value is used. + * However, set this to a 32MB offset to allow for easier Linux kernel + * booting as the default is often used as the kernel load address. + */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * We setup defaults based on constraints from the Linux kernel, which should + * also be safe elsewhere. We have the default load at 32MB into DDR (for + * the kernel), FDT above 128MB (the maximum location for the end of the + * kernel), and the ramdisk 512KB above that (allowing for hopefully never + * seen large trees). We say all of this must be within the first 256MB + * as that will normally be within the kernel lowmem and thus visible via + * bootm_size and we only run on platforms with 256MB or more of memory. + */ +#define DEFAULT_LINUX_BOOT_ENV \ + "loadaddr=0x82000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdtaddr=0x88000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "rdaddr=0x88080000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + "bootm_size=0x10000000\0" + +/* + * Default to a quick boot delay. + */ +#define CONFIG_BOOTDELAY 1 + +/* + * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, + * we say (for simplicity) that we have 1 bank, always, even when + * we have more. We always start at 0x80000000, and we place the + * initial stack pointer in our SRAM. Otherwise, we can define + * CONFIG_NR_DRAM_BANKS before including this file. + */ +#ifndef CONFIG_NR_DRAM_BANKS +#define CONFIG_NR_DRAM_BANKS 1 +#endif +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/* Timer information. */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* I2C IP block */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC + +/* McSPI IP block */ +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_CMD_SPI + +/* GPIO block */ +#define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO + +/* + * GPMC NAND block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#ifdef CONFIG_NAND +#define CONFIG_NAND_OMAP_GPMC +#ifndef CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE 0x8000000 +#endif +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_CMD_NAND +#endif + +/* + * The following are general good-enough settings for U-Boot. We set a + * large malloc pool as we generally have a lot of DDR, and we opt for + * function over binary size in the main portion of U-Boot as this is + * generally easily constrained later if needed. We enable the config + * options that give us information in the environment about what board + * we are on so we do not need to rely on the command prompt. We set a + * console baudrate of 115200 and use the default baud rate table. + */ +#define CONFIG_SYS_MALLOC_LEN (16 << 20) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_BAUDRATE 115200 +#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * When we have SPI, NOR or NAND flash we expect to be making use of + * mtdparts, both for ease of use in U-Boot and for passing information + * on to the Linux kernel. + */ +#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) +#define CONFIG_MTD_DEVICE /* Required for mtdparts */ +#define CONFIG_CMD_MTDPARTS +#endif + +/* + * For commands to use, we take the default list and add a few other + * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH + * prior to this include, in order to skip a few commands. When we do + * have flash, if we expect these commands they must be enabled in that + * config. If desired, a specific list of desired commands can be used + * instead. + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD + +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART +#endif + +/* + * Our platforms make use of SPL to initalize the hardware (primarily + * memory) enough for full U-Boot to be loaded. We also support Falcon + * Mode so that the Linux kernel can be booted directly from SPL + * instead, if desired. We make use of the general SPL framework found + * under common/spl/. Given our generally common memory map, we set a + * number of related defaults and sizes here. + */ +#if !defined(CONFIG_NOR_BOOT) && \ + !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_OS_BOOT + +/* + * Place the image at the start of the ROM defined image space (per + * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined + * downloaded image area. We initalize DRAM as soon as we can so that + * we can place stack, malloc and BSS there. We load U-Boot itself into + * memory at 0x80800000 for legacy reasons (to not conflict with older + * SPLs). We have our BSS be placed 2MiB after this, to allow for the + * default Linux kernel address of 0x80008000 to work with most sized + * kernels, in the Falcon Mode case. We have the SPL malloc pool at the + * end of the BSS area. We place our stack at 32MiB after the start of + * DRAM to allow room for all of the above. + */ +#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20)) +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#endif +#ifndef CONFIG_SPL_BSS_START_ADDR +#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#endif +#ifndef CONFIG_SYS_SPL_MALLOC_START +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN +#endif + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#ifdef CONFIG_SPL_OS_BOOT +/* FAT */ +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +/* spl export command */ +#define CONFIG_CMD_SPL +#endif + +#ifdef CONFIG_MMC +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#endif + +/* General parts of the framework, required. */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_MTD_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#endif +#endif /* !CONFIG_NOR_BOOT */ + +#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h new file mode 100644 index 0000000000..3c634ee680 --- /dev/null +++ b/include/configs/ti_omap3_common.h @@ -0,0 +1,89 @@ +/* + * ti_omap3_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap3530 + * http://www.ti.com/product/omap3630 + * http://www.ti.com/product/dm3730 + */ + +#ifndef __CONFIG_TI_OMAP3_COMMON_H__ +#define __CONFIG_TI_OMAP3_COMMON_H__ + + +#include +#include + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_DM +# define CONFIG_CMD_DM +# define CONFIG_DM_GPIO +# define CONFIG_DM_SERIAL +# define CONFIG_OMAP_SERIAL +# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#endif + +/* The chip has SDRC controller */ +#define CONFIG_SDRC + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +/* NS16550 Configuration */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ +#define CONFIG_SYS_NS16550 +#ifdef CONFIG_SPL_BUILD +# define CONFIG_SYS_NS16550_SERIAL +# define CONFIG_SYS_NS16550_REG_SIZE (-4) +# define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#endif +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} + +/* Select serial console configuration */ +#define CONFIG_CONS_INDEX 3 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +/* TWL4030 */ +#define CONFIG_TWL4030_POWER 1 + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (64 << 20)) + + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SYS_NAND_BASE 0x30000000 +#endif + +/* Now bring in the rest of the common code. */ +#include + +#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h new file mode 100644 index 0000000000..1c93aab1a7 --- /dev/null +++ b/include/configs/ti_omap4_common.h @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated. + * Aneesh V + * Steve Sakoman + * + * TI OMAP4 common configuration settings + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TI_OMAP4_COMMON_H +#define __CONFIG_TI_OMAP4_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP4430 1 /* which is in a 4430 */ +#define CONFIG_MISC_INIT_R +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_SYS_THUMB_BUILD + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#endif +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* Get CPU defs */ +#include +#include + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE + +/* + * Total Size Environment - 128k + */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#include + +/* + * Hardware drivers + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE + +/* TWL6030 */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_TWL6030_POWER 1 +#endif + +/* USB */ +#define CONFIG_MUSB_UDC 1 +#define CONFIG_USB_OMAP3 1 + +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +/* Per-Soc commands */ +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Environment setup + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "console=ttyO2,115200n8\0" \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "uimageboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "findfdt="\ + "if test $board_name = sdp4430; then " \ + "setenv fdtfile omap4-sdp.dtb; fi; " \ + "if test $board_name = panda; then " \ + "setenv fdtfile omap4-panda.dtb; fi;" \ + "if test $board_name = panda-a4; then " \ + "setenv fdtfile omap4-panda-a4.dtb; fi;" \ + "if test $board_name = panda-es; then " \ + "setenv fdtfile omap4-panda-es.dtb; fi;" \ + "if test $board_name = duovero; then " \ + "setenv fdtfile omap4-duovero-parlor.dtb; fi;" \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadbootenv; then " \ + "run importbootenv; " \ + "fi;" \ + "if test -n ${uenvcmd}; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt;" \ + "run mmcboot; " \ + "fi; " \ + "if run loaduimage; then " \ + "run uimageboot;" \ + "fi; " \ + "fi" + +/* + * Defines for SPL + * It is known that this will break HS devices. Since the current size of + * SPL is overlapped with public stack and breaking non HS devices to boot. + * So moving TEXT_BASE down to non-HS limit. + */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_DISPLAY_PRINT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +/* SPL: Allow to use an EXT partition */ +#define CONFIG_SPL_EXT_SUPPORT + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + +#ifdef CONFIG_SPL_BUILD +/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ +#undef CONFIG_SYS_I2C +#undef CONFIG_SYS_I2C_OMAP24XX +#endif + +#endif /* __CONFIG_TI_OMAP4_COMMON_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h new file mode 100644 index 0000000000..925cb42dd3 --- /dev/null +++ b/include/configs/ti_omap5_common.h @@ -0,0 +1,166 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Sricharan R + * + * Derived from OMAP4 done by: + * Aneesh V + * + * TI OMAP5 AND DRA7XX common configuration settings + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap5432 + */ + +#ifndef __CONFIG_TI_OMAP5_COMMON_H +#define __CONFIG_TI_OMAP5_COMMON_H + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE + +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + +#include +#include + +#include + +/* + * Hardware drivers + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 + +/* Per-SoC commands */ +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Environment setup + */ +#ifndef PARTS_DEFAULT +#define PARTS_DEFAULT +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "console=" CONSOLEDEV ",115200n8\0" \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "vram=${vram} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi;\0" \ + "netboot=echo Booting from network ...; " \ + "set env autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = omap5_uevm; then " \ + "setenv fdtfile omap5-uevm.dtb; fi; " \ + "if test $board_name = dra7xx; then " \ + "setenv fdtfile dra7-evm.dtb; fi;" \ + "if test $board_name = dra72x; then " \ + "setenv fdtfile dra72-evm.dtb; fi;" \ + "if test $board_name = beagle_x15; then " \ + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "setenv mmcroot /dev/mmcblk0p2 rw; " \ + "run mmcboot;" \ + + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 + * (dra7xx is larger, but we do not need to be larger at this time). We + * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * print some information. + */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_DISPLAY_PRINT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ +#endif + +#endif /* __CONFIG_TI_OMAP5_COMMON_H */ diff --git a/include/configs/titanium.h b/include/configs/titanium.h index 077e25e16e..764fd5d121 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -13,11 +13,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "mx6_common.h" #include #include -#define CONFIG_MX6 -#define CONFIG_MX6Q #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -41,8 +40,8 @@ /* I2C Configs */ #define CONFIG_CMD_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 /* MMC Configs */ @@ -194,7 +193,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/tk71.h b/include/configs/tk71.h index 16e8a7f2b8..a9c6d2e601 100644 --- a/include/configs/tk71.h +++ b/include/configs/tk71.h @@ -17,7 +17,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 27efa69abc..00a1a9e002 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -11,12 +11,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include #include /* Architecture, CPU, etc */ -#define CONFIG_ARM1176 #define CONFIG_TNETV107X #define CONFIG_TNETV107X_EVM #define CONFIG_TNETV107X_WATCHDOG @@ -30,7 +29,6 @@ #define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0) -#define CONFIG_SYS_HZ 1000 #define CONFIG_PLL_SYS_EXT_FREQ 25000000 #define CONFIG_PLL_TDM_EXT_FREQ 19200000 diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index f841ba828b..79c7fc5129 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -40,7 +40,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_ARCH_CPU_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ @@ -86,7 +85,6 @@ #define CONFIG_SPI #define CONFIG_CMD_SPI #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_CMD_EEPROM #define CONFIG_SPI_M95XXX diff --git a/include/configs/top9000.h b/include/configs/top9000.h deleted file mode 100644 index 65dabde54f..0000000000 --- a/include/configs/top9000.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * Configuation settings for the TOP9000 CPU module with AT91SAM9XE. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * top9000 with at91sam9xe256 or at91sam9xe512 - * - * Initial Bootloader is in embedded flash. - * Vital Product Data, U-Boot Environment are in I2C-EEPROM. - * U-Boot is in embedded flash, a backup U-Boot can be in NAND flash. - * kernel and file system are either in NAND flash or on a micro SD card. - * NAND flash is optional. - * I2C EEPROM is never optional. - * SPI FRAM is optional. - * SPI ENC28J60 is optional. - * 16 or 32 bit wide SDRAM. - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SoC must be defined first, before hardware.h is included */ -#define CONFIG_AT91SAM9XE -#include - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires - * adapting the initial boot program. - */ -#define CONFIG_SYS_TEXT_BASE 0x20000000 /* start of SDRAM */ - -/* Command line configuration */ -#include -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG -#define CONFIG_CMD_ASKENV -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_PROMPT "TOP9000> " -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CACHE - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ -#define CONFIG_SYS_HZ 1000 - -/* Misc CPU related */ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_AT91RESET_EXTRST /* assert external reset */ - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 - -/* SD/MMC card */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9 -#define CONFIG_CMD_MMC - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_SYS_PHY_ID 1 -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 - -/* real time clock */ -#define CONFIG_RTC_AT91SAM9_RTT -#define CONFIG_CMD_DATE - -#if defined(CONFIG_AT91SAM9XE) -/* - * NOR flash - use embedded flash of SAM9XE256/512 - * U-Boot will not fit into 128K ! - * 2010.09 will not fit into 256K with all options enabled ! - * - * Layout: - * 16kB 1st Bootloader - * Rest U-Boot - * the first sector (16kB) of EFLASH cannot be unprotected - * with u-boot commands - */ -# define CONFIG_AT91_EFLASH -# define CONFIG_SYS_FLASH_BASE ATMEL_BASE_FLASH -# define CONFIG_SYS_MAX_FLASH_SECT 32 -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -# define CONFIG_SYS_FLASH_PROTECTION -# define CONFIG_EFLASH_PROTSECTORS 1 /* protect first sector */ -#endif - -/* SPI */ -#define CONFIG_ATMEL_SPI -#define CONFIG_CMD_SPI - -/* RAMTRON FRAM */ -#define CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */ -#define FRAM_SPI_BUS 0 -#define FRAM_CS_NUM 0 -#define CONFIG_SPI_FLASH /* RAMTRON FRAM on SPI bus */ -#define CONFIG_SPI_FRAM_RAMTRON -#define CONFIG_SF_DEFAULT_SPEED 1000000 /* be conservative here... */ -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "FM25H20" - -/* Microchip ENC28J60 (second LAN) */ -#if defined(CONFIG_EVAL9000) -# define CONFIG_ENC28J60 -# define CONFIG_ATMEL_SPI1 /* SPI used for ENC28J60 is SPI1 */ -# define ENC_SPI_BUS 1 -# define ENC_CS_NUM 0 -# define ENC_SPI_CLOCK 1000000 -#endif /* CONFIG_EVAL9000 */ - -/* - * SDRAM: 1 bank, min 32, max 128 MB - * Initialized before u-boot gets started. - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01e00000) -#define CONFIG_SYS_LOAD_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x01000000) -/* - * Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE) - -/* - * NAND flash: 256 MB (optional) - * - * Layout: - * 640kB: u-boot (includes space for spare sectors, handled by - * initial loader) - * 2MB: kernel - * rest: file system - */ -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 -#define CONFIG_CMD_NAND - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_USB - -/* I2C support must always be enabled */ -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -#define I2C0_PORT AT91_PIO_PORTA -#define SDA0_PIN 23 -#define SCL0_PIN 24 -#define I2C1_PORT AT91_PIO_PORTB -#define SDA1_PIN 12 -#define SCL1_PIN 13 -#define I2C_SOFT_DECLARATIONS void iic_init(void);\ - int iic_read(void);\ - void iic_sda(int);\ - void iic_scl(int); -#define I2C_ACTIVE -#define I2C_TRISTATE -#define I2C_INIT iic_init() -#define I2C_READ iic_read() -#define I2C_SDA(bit) iic_sda(bit) -#define I2C_SCL(bit) iic_scl(bit) -#define I2C_DELAY udelay(3) -/* EEPROM configuration */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x2000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -/* later: #define CONFIG_I2C_ENV_EEPROM_BUS 0 */ -/* ENV is always in I2C-EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0x1000 -#define CONFIG_ENV_SIZE 0x0f00 -/* VPD settings */ -#define CONFIG_SYS_I2C_FACT_ADDR 0x57 -#define CONFIG_SYS_FACT_OFFSET 0x1F00 -#define CONFIG_SYS_FACT_SIZE 0x0100 -/* later: #define CONFIG_MISC_INIT_R */ -/* define the next only if you want to allow users to enter VPD data */ -#define CONFIG_SYS_FACT_ENTRY -#ifndef __ASSEMBLY__ -extern void read_factory_r(void); -#endif - -/* - * Only interrupt autoboot if is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -/* - * add filesystem commands if we have at least 1 storage - * media with filesystem - */ -#if defined(CONFIG_NAND_ATMEL) \ - || defined(CONFIG_USB_ATMEL) \ - || defined(CONFIG_MMC) -# define CONFIG_DOS_PARTITION -# define CONFIG_CMD_FAT -# define CONFIG_CMD_EXT2 -/* later: #define CONFIG_CMD_JFFS2 */ -#endif - -/* add NET commands if we have at least 1 LAN */ -#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60) -# define CONFIG_CMD_PING -# define CONFIG_CMD_DHCP -# define CONFIG_CMD_MII -/* is this really needed ? */ -# define CONFIG_RESET_PHY_R -/* BOOTP options */ -# define CONFIG_BOOTP_BOOTFILESIZE -# define CONFIG_BOOTP_BOOTPATH -# define CONFIG_BOOTP_GATEWAY -# define CONFIG_BOOTP_HOSTNAME -#endif - -/* linux in NAND flash */ -#define CONFIG_BOOTCOUNT_LIMIT 1 -#define CONFIG_BOOTCOMMAND \ - "nand read 0x21000000 0xA0000 0x200000; bootm" -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 " \ - "root=/dev/mtdblock2 " \ - "mtdparts=atmel_nand:" \ - "640k(uboot)ro," \ - "2M(linux)," \ - "16M(root)," \ - "-(rest) " \ - "rw "\ - "rootfstype=jffs2" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#endif diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h new file mode 100644 index 0000000000..a2422f3f07 --- /dev/null +++ b/include/configs/tqma6.h @@ -0,0 +1,488 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel + * + * Configuration settings for the TQ Systems TQMa6 module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +/* SPL */ +/* #if defined(CONFIG_SPL_BUILD) */ + +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_EXT_SUPPORT + +/* common IMX6 SPL configuration */ +#include "imx6_spl.h" + +/* #endif */ + +#include "mx6_common.h" +#include +#include +#include + +#define PHYS_SDRAM_SIZE (512u * SZ_1M) +#define PHYS_SDRAM_SIZE (1024u * SZ_1M) +#endif + +#if defined(CONFIG_MBA6) + +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb" +#define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb" +#endif + +#endif + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_UART + +/* SPI */ +#define CONFIG_CMD_SPI +#define CONFIG_MXC_SPI + +/* SPI Flash */ +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + +#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 +#if defined(CONFIG_MBA6) +#define CONFIG_DTT_SENSORS { 0, 1 } +#else +#define CONFIG_DTT_SENSORS { 0 } +#endif +#define CONFIG_DTT_MAX_TEMP 70 +#define CONFIG_DTT_MIN_TEMP -30 +#define CONFIG_DTT_HYSTERESIS 3 +#define CONFIG_CMD_DTT + +/* I2C EEPROM (M24C64) */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ +#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_CMD_EEPROM + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define TQMA6_PFUZE100_I2C_BUS 2 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Fuses */ +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_PHYLIB +#define CONFIG_MII + +#if defined(CONFIG_MBA6) + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC_PHYADDR 0x03 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_KSZ9031 + +#else + +#error "define PHY to use for your baseboard" + +#endif + +#define CONFIG_ARP_TIMEOUT 200UL +/* Network config - Allow larger/faster download for TFTP/NFS */ +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_NFS_READ_SIZE 4096 + +#if defined(CONFIG_MBA6) + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" + +#else + +#error "define baseboard specific things (uart, number of SD-card slots)" + +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_SETEXPR +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x12000000 + +/* place code in last 4 MiB of RAM */ +#define CONFIG_SYS_TEXT_BASE 0x2fc00000 +#define CONFIG_SYS_TEXT_BASE 0x4fc00000 +#endif + +#define CONFIG_ENV_SIZE (SZ_8K) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) + +#if defined(CONFIG_TQMA6X_MMC_BOOT) + +#define CONFIG_ENV_IS_IN_MMC +#define TQMA6_UBOOT_OFFSET SZ_1K +#define TQMA6_UBOOT_SECTOR_START 0x2 +#define TQMA6_UBOOT_SECTOR_COUNT 0x7fe + +#define CONFIG_ENV_OFFSET SZ_1M +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define TQMA6_FDT_OFFSET (2 * SZ_1M) +#define TQMA6_FDT_SECTOR_START 0x1000 +#define TQMA6_FDT_SECTOR_COUNT 0x800 + +#define TQMA6_KERNEL_SECTOR_START 0x2000 +#define TQMA6_KERNEL_SECTOR_COUNT 0x2000 + +#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ + "uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0" \ + "uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ + "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ + "fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ + "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ + "kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "loadimage=mmc dev ${mmcdev}; " \ + "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ + "loadfdt=mmc dev ${mmcdev}; " \ + "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ + "update_uboot=if tftp ${uboot}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} / 0x200; " \ + "setexpr blkc ${blkc} + 1; " \ + "if itest ${blkc} <= ${uboot_size}; then " \ + "mmc write ${loadaddr} ${uboot_start} " \ + "${blkc}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize; setenv blkc \0" \ + "update_kernel=run kernel_name; " \ + "if tftp ${kernel}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} / 0x200; " \ + "setexpr blkc ${blkc} + 1; " \ + "if itest ${blkc} <= ${kernel_size}; then " \ + "mmc write ${loadaddr} " \ + "${kernel_start} ${blkc}; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "setenv filesize; setenv blkc \0" \ + "update_fdt=if tftp ${fdt_file}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} / 0x200; " \ + "setexpr blkc ${blkc} + 1; " \ + "if itest ${blkc} <= ${fdt_size}; then " \ + "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize; setenv blkc \0" \ + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot; run netboot; run panicboot" + +#elif defined(CONFIG_TQMA6X_SPI_BOOT) + +#define TQMA6_UBOOT_OFFSET 0x400 +#define TQMA6_UBOOT_SECTOR_START 0x0 +/* max u-boot size: 512k */ +#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE +#define TQMA6_UBOOT_SECTOR_COUNT 0x8 +#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ + TQMA6_UBOOT_SECTOR_COUNT) + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET (TQMA6_UBOOT_SIZE) +#define CONFIG_ENV_SECT_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SPI_BUS (CONFIG_SF_DEFAULT_BUS) +#define CONFIG_ENV_SPI_CS (CONFIG_SF_DEFAULT_CS) +#define CONFIG_ENV_SPI_MAX_HZ (CONFIG_SF_DEFAULT_SPEED) +#define CONFIG_ENV_SPI_MODE (CONFIG_SF_DEFAULT_MODE) + +#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ + CONFIG_ENV_SECT_SIZE) +#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE) + +#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ +#define TQMA6_FDT_SECTOR_COUNT 0x01 + +#define TQMA6_KERNEL_SECTOR_START 0x10 +#define TQMA6_KERNEL_SECTOR_COUNT 0x60 + +#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ + "mmcblkdev=0\0" \ + "uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0" \ + "uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ + "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ + "fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ + "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ + "kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ + "update_uboot=if tftp ${uboot}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr blkc ${filesize} + " \ + __stringify(TQMA6_UBOOT_OFFSET) "; " \ + "setexpr size ${uboot_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "if itest ${blkc} <= ${size}; then " \ + "sf probe; " \ + "sf erase 0 ${size}; " \ + "sf write ${loadaddr} ${uboot_offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv blkc; setenv size \0" \ + "update_kernel=run kernel_name; if tftp ${kernel}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr size ${kernel_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${kernel_start} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "if itest ${filesize} <= ${size}; then " \ + "sf probe; " \ + "sf erase ${offset} ${size}; " \ + "sf write ${loadaddr} ${offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv size ; setenv offset\0" \ + "update_fdt=if tftp ${fdt_file}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr size ${fdt_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${fdt_start} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "if itest ${filesize} <= ${size}; then " \ + "sf probe; " \ + "sf erase ${offset} ${size}; " \ + "sf write ${loadaddr} ${offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv size ; setenv offset\0" \ + "loadimage=sf probe; " \ + "setexpr size ${kernel_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${kernel_start} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "sf read ${loadaddr} ${offset} ${size}; " \ + "setenv size ; setenv offset\0" \ + "loadfdt=sf probe; " \ + "setexpr size ${fdt_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${fdt_start} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "sf read ${${fdt_addr}} ${offset} ${size}; " \ + "setenv size ; setenv offset\0" \ + + +#define CONFIG_BOOTCOMMAND \ + "sf probe; run mmcboot; run netboot; run panicboot" \ + +#else + +#error "need to define boot source" + +#endif + +/* 128 MiB offset as in ARM related docu for linux suggested */ +#define TQMA6_FDT_ADDRESS 0x18000000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board=tqma6\0" \ + "uimage=uImage\0" \ + "zimage=zImage\0" \ + "boot_type=bootz\0" \ + "kernel_name=if test \"${boot_type}\" != bootz; then " \ + "setenv kernel ${uimage}; " \ + "else setenv kernel ${zimage}; fi\0" \ + "uboot=u-boot.imx\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "addfb=setenv bootargs ${bootargs} " \ + "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ + "mmcpart=2\0" \ + "mmcblkdev=0\0" \ + "mmcargs=run addmmc addtty addfb\0" \ + "addmmc=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk${mmcblkdev}p${mmcpart} rw rootwait\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "setenv bootargs; " \ + "run mmcargs; " \ + "run loadimage; " \ + "if run loadfdt; then " \ + "echo boot device tree kernel ...; " \ + "${boot_type} ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "${boot_type}; " \ + "fi;\0" \ + "setenv bootargs \0" \ + "netdev=eth0\0" \ + "rootpath=/srv/nfs/tqma6\0" \ + "ipmode=static\0" \ + "netargs=run addnfs addip addtty addfb\0" \ + "addnfs=setenv bootargs ${bootargs} " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp;\0" \ + "addip_static=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}:${netdev}:off\0" \ + "addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test \"${ipmode}\" != static; then " \ + "run addip_dynamic; else run addip_static; fi\0" \ + "set_getcmd=if test \"${ipmode}\" != static; then " \ + "setenv getcmd dhcp; setenv autoload yes; " \ + "else setenv getcmd tftp; setenv autoload no; fi\0" \ + "netboot=echo Booting from net ...; " \ + "run kernel_name; " \ + "run set_getcmd; " \ + "setenv bootargs; " \ + "run netargs; " \ + "if ${getcmd} ${kernel}; then " \ + "if ${getcmd} ${fdt_addr} ${fdt_file}; then " \ + "${boot_type} ${loadaddr} - ${fdt_addr}; " \ + "fi; " \ + "fi; " \ + "echo ... failed\0" \ + "panicboot=echo No boot device !!! reset\0" \ + TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128u * SZ_1K) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 9b6aac96e6..b21ea2de5f 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -7,145 +7,117 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_TRATS_H +#define __CONFIG_TRATS_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* which is in a S5P Family */ -#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */ -#define CONFIG_TRATS /* working with TRATS */ -#define CONFIG_TIZEN /* TIZEN lib */ +#include + +#define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */ -#include /* get chip and board defs */ +#define CONFIG_TRATS -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_TIZEN /* TIZEN lib */ + +#define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 #endif +/* TRATS has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_TEXT_BASE 0x63300000 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_TEXT_BASE 0x63300000 + +/* select serial console configuration */ +#define CONFIG_SERIAL2 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* MACH_TYPE_TRATS macro will be removed once added to mach-types */ #define MACH_TYPE_TRATS 3928 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (16 << 20)) - -/* select serial console configuration */ -#define CONFIG_SERIAL2 /* use SERIAL 2 */ -#define CONFIG_BAUDRATE 115200 - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI -#define CONFIG_MMC_SDMA - -/* PWM */ -#define CONFIG_PWM - -/* It should define before config_cmd_default.h */ -#define CONFIG_SYS_NO_FLASH - -/* Command definition */ -#include - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE -#undef CONFIG_CMD_ONENAND -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_MMC -#define CONFIG_CMD_DFU -#define CONFIG_CMD_GPT -#define CONFIG_CMD_SETEXPR - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 -#define CONFIG_G_DNL_MANUFACTURER "Samsung" - -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_BOOTARGS "Please use defined boot" #define CONFIG_BOOTCOMMAND "run mmcboot" - #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + #define CONFIG_BOOTBLOCK "10" #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" -#define PARTS_BOOTLOADER "u-boot" #define PARTS_BOOT "boot" +#define PARTS_QBOOT "qboot" +#define PARTS_CSC "csc" #define PARTS_ROOT "platform" #define PARTS_DATA "data" -#define PARTS_CSC "csc" #define PARTS_UMS "ums" #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ - "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ - "name="PARTS_BOOTLOADER",size=60MiB," \ - "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \ - "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ - "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ - "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ #define CONFIG_DFU_ALT \ - "u-boot mmc 80 400;" \ - "uImage ext4 0 2;" \ - "exynos4210-trats.dtb ext4 0 2\0" - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_CONSOLE_IS_IN_ENV + "u-boot raw 0x80 0x400;" \ + "/uImage ext4 0 2;" \ + "/modem.bin ext4 0 2;" \ + "/exynos4210-trats.dtb ext4 0 2;" \ + ""PARTS_CSA" part 0 1;" \ + ""PARTS_BOOT" part 0 2;" \ + ""PARTS_QBOOT" part 0 3;" \ + ""PARTS_CSC" part 0 4;" \ + ""PARTS_ROOT" part 0 5;" \ + ""PARTS_DATA" part 0 6;" \ + ""PARTS_UMS" part 0 7;" \ + "params.bin raw 0x38 0x8\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ - "updatemmc=" \ - "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ "updatebackup=" \ - "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ + "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc dev 0 0\0" \ "updatebootb=" \ "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ "lpj=lpj=3981312\0" \ @@ -162,7 +134,7 @@ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run bootk\0" \ "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ @@ -201,88 +173,35 @@ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ - "fdtfile=exynos4210-trats.dtb\0" - - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "TRATS # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -#define CONFIG_SYS_HZ 1000 -/* TRATS has 4 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 4 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE /* Falcon mode definitions */ #define CONFIG_CMD_SPL -#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100 +#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 /* GPT */ -#define CONFIG_EFI_PARTITION -#define CONFIG_PARTITION_UUIDS +#define CONFIG_RANDOM_UUID -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_CACHELINE_SIZE 32 +/* I2C */ +#include + +#define CONFIG_CMD_I2C #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE +#define CONFIG_MAX_I2C_NUM 8 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ #define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F #define CONFIG_SOFT_I2C_READ_REPEATED_START #define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SOFT_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS 15 - -#include - -/* I2C PMIC */ -#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7) -#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6) /* I2C FG */ -#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1) -#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0) - -#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin() -#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin() -#define I2C_INIT multi_i2c_init() +#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41 +#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40 +/* POWER */ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX8997 @@ -293,28 +212,47 @@ #define CONFIG_POWER_MUIC_MAX8997 #define CONFIG_POWER_BATTERY #define CONFIG_POWER_BATTERY_TRATS -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_LIB_HW_RAND + +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX8997_PMIC" +#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 0) + +#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 +#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12)) - -#define CONFIG_CMD_USB_MASS_STORAGE -#if defined(CONFIG_CMD_USB_MASS_STORAGE) -#define CONFIG_USB_GADGET_MASS_STORAGE -#endif - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h new file mode 100644 index 0000000000..42481ab6e1 --- /dev/null +++ b/include/configs/trats2.h @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Sanghee Kim + * Piotr Wilczek + * + * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TRATS2_H +#define __CONFIG_TRATS2_H + +#include + +#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ + + +#define CONFIG_TIZEN /* TIZEN lib */ + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x10502000 +#endif + +/* TRATS2 has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_SYS_TEXT_BASE 0x43e00000 + +/* select serial console configuration */ +#define CONFIG_SERIAL2 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Tizen - partitions definitions */ +#define PARTS_CSA "csa-mmc" +#define PARTS_BOOT "boot" +#define PARTS_QBOOT "qboot" +#define PARTS_CSC "csc" +#define PARTS_ROOT "platform" +#define PARTS_DATA "data" +#define PARTS_UMS "ums" + +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ + "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ + +#define CONFIG_DFU_ALT \ + "u-boot raw 0x80 0x800;" \ + "/uImage ext4 0 2;" \ + "/modem.bin ext4 0 2;" \ + "/exynos4412-trats2.dtb ext4 0 2;" \ + ""PARTS_CSA" part 0 1;" \ + ""PARTS_BOOT" part 0 2;" \ + ""PARTS_QBOOT" part 0 3;" \ + ""PARTS_CSC" part 0 4;" \ + ""PARTS_ROOT" part 0 5;" \ + ""PARTS_DATA" part 0 6;" \ + ""PARTS_UMS" part 0 7;" \ + "params.bin raw 0x38 0x8\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootk=" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ + "updatebackup=" \ + "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ + " mmc dev 0 0\0" \ + "updatebootb=" \ + "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ + "mmcboot=" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ + "run bootk\0" \ + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "verify=n\0" \ + "rootfstype=ext4\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "kernelname=uImage\0" \ + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ + "${kernelname}\0" \ + "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=5\0" \ + "opts=always_resume=1\0" \ + "partitions=" PARTS_DEFAULT \ + "dfu_alt_info=" CONFIG_DFU_ALT \ + "uartpath=ap\0" \ + "usbpath=ap\0" \ + "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ + "consoleoff=set console console=ram; save; reset\0" \ + "spladdr=0x40000100\0" \ + "splsize=0x200\0" \ + "splfile=falcon.bin\0" \ + "spl_export=" \ + "setexpr spl_imgsize ${splsize} + 8 ;" \ + "setenv spl_imgsize 0x${spl_imgsize};" \ + "setexpr spl_imgaddr ${spladdr} - 8 ;" \ + "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ + "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ + "spl export atags 0x40007FC0;" \ + "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ + "mw.l ${spl_addr_tmp} ${splsize};" \ + "ext4write mmc ${mmcdev}:${mmcbootpart}" \ + " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ + "setenv spl_imgsize;" \ + "setenv spl_imgaddr;" \ + "setenv spl_addr_tmp;\0" \ + "fdtaddr=40800000\0" \ + +/* GPT */ +#define CONFIG_RANDOM_UUID + +/* I2C */ +#include + +#define CONFIG_CMD_I2C + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 +#define CONFIG_MAX_I2C_NUM 8 +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 +#define I2C_SOFT_DECLARATIONS2 +#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00 +#define CONFIG_SOFT_I2C_READ_REPEATED_START +#define CONFIG_SYS_I2C_INIT_BOARD + +#ifndef __ASSEMBLY__ +int get_soft_i2c_scl_pin(void); +int get_soft_i2c_sda_pin(void); +#endif +#define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin() +#define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin() + +/* POWER */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_MAX77686 +#define CONFIG_POWER_PMIC_MAX77693 +#define CONFIG_POWER_MUIC_MAX77693 +#define CONFIG_POWER_FG_MAX77693 +#define CONFIG_POWER_BATTERY_TRATS2 + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_LIB_HW_RAND + +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include + +#define KEY_PWR_PMIC_NAME "MAX77686_PMIC" +#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 1) + +#define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 +#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + +/* LCD */ +#define CONFIG_EXYNOS_FB +#define CONFIG_LCD +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_FB_ADDR 0x52504000 +#define CONFIG_S6E8AX0 +#define CONFIG_EXYNOS_MIPI_DSIM +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) + +#endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 4e2cb65b0a..36621a553c 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -10,7 +10,7 @@ * * Configuration settings for the Tricorder board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -18,7 +18,7 @@ /* High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP_COMMON #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER /* @@ -34,10 +34,15 @@ #include /* get chip and board defs */ #include +#define CONFIG_SYS_GENERIC_BOARD + /* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SILENT_CONSOLE +#define CONFIG_ZERO_BOOTDELAY_CHECK + /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) @@ -52,12 +57,30 @@ #define CONFIG_OF_LIBFDT /* Size of malloc() pool */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ #define CONFIG_SYS_MALLOC_LEN (1024*1024) /* Hardware drivers */ +/* GPIO support */ +#define CONFIG_OMAP_GPIO + +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ + +/* LED support */ +#define CONFIG_STATUS_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_CMD_LED /* LED command */ +#define STATUS_LED_BIT (1 << 0) +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT1 (1 << 1) +#define STATUS_LED_STATE1 STATUS_LED_ON +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT2 (1 << 2) +#define STATUS_LED_STATE2 STATUS_LED_ON +#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) + /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -79,10 +102,17 @@ #define CONFIG_DOS_PARTITION /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX + + +/* EEPROM */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_BUS_NUM 1 /* TWL4030 */ #define CONFIG_TWL4030_POWER @@ -91,13 +121,16 @@ /* Board NAND Info */ #define CONFIG_SYS_NO_FLASH /* no NOR flash */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:" \ - "512k(u-boot-spl)," \ - "1920k(u-boot)," \ - "128k(u-boot-env)," \ - "4m(kernel)," \ - "-(fs)" +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "128k(SPL)," \ + "1m(u-boot)," \ + "384k(u-boot-env1)," \ + "1152k(mtdoops)," \ + "384k(u-boot-env2)," \ + "5m(kernel)," \ + "2m(fdt)," \ + "-(ubi)" #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ @@ -105,12 +138,11 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_NAND_OMAP_BCH8 #define CONFIG_BCH +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 /* commands to include */ #include @@ -137,53 +169,104 @@ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_MTD_PARTITIONS -/* Environment information */ -#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ +/* Environment information (this is the common part) */ -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ +/* hang() the board on panic() */ +#define CONFIG_PANIC_HANG + +/* environment placement (for NAND), is different for FLASHCARD but does not + * harm there */ +#define CONFIG_ENV_OFFSET 0x120000 /* env start */ +#define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ +#define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ +#define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ + +/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend + * value can not be used here! */ +#define CONFIG_LOADADDR 0x82000000 + +#define CONFIG_COMMON_ENV_SETTINGS \ "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ - "vram=12M\0" \ - "lcdmode=800x600\0" \ + "vram=3M\0" \ "defaultdisplay=lcd\0" \ - "kernelopts=rw rootwait\0" \ + "kernelopts=mtdoops.mtddev=3\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ "commonargs=" \ "setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${kernelopts} " \ + "vt.global_cursor_default=0 " \ "vram=${vram} " \ - "omapfb.mode=lcd:${lcdmode} " \ - "omapdss.def_disp=${defaultdisplay}\0" \ + "omapdss.def_disp=${defaultdisplay}\0" + +#define CONFIG_BOOTCOMMAND "run autoboot" + +/* specific environment settings for different use cases + * FLASHCARD: used to run a rdimage from sdcard to program the device + * 'NORMAL': used to boot kernel from sdcard, nand, ... + * + * The main aim for the FLASHCARD skin is to have an embedded environment + * which will not be influenced by any data already on the device. + */ +#ifdef CONFIG_FLASHCARD + +#define CONFIG_ENV_IS_NOWHERE + +/* the rdaddr is 16 MiB before the loadaddr */ +#define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_COMMON_ENV_SETTINGS \ + CONFIG_ENV_RDADDR \ + "autoboot=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ + "rdinit=/sbin/init; " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ + "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ + "bootm ${loadaddr} ${rdaddr}\0" + +#else /* CONFIG_FLASHCARD */ + +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ + +#define CONFIG_ENV_IS_IN_NAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_COMMON_ENV_SETTINGS \ "mmcargs=" \ "run commonargs; " \ "setenv bootargs ${bootargs} " \ "root=/dev/mmcblk0p2 " \ - "${kernelopts}\0" \ + "rootwait " \ + "rw\0" \ "nandargs=" \ "run commonargs; " \ "setenv bootargs ${bootargs} " \ - "omapfb.mode=lcd:${lcdmode} " \ - "omapdss.def_disp=${defaultdisplay} " \ "root=ubi0:root " \ - "ubi.mtd=4 " \ + "ubi.mtd=7 " \ "rootfstype=ubifs " \ - "${kernelopts}\0" \ + "ro\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ - "loaduimage_ubi=mtd default; " \ - "ubi part fs; " \ + "loaduimage_ubi=ubi part ubi; " \ "ubifsmount ubi:root; " \ "ubifsload ${loadaddr} /boot/uImage\0" \ + "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "run loaduimage_ubi; " \ + "run loaduimage_nand; " \ "bootm ${loadaddr}\0" \ "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -196,12 +279,12 @@ "fi; " \ "else run nandboot; fi\0" - -#define CONFIG_BOOTCOMMAND "run autoboot" +#endif /* CONFIG_FLASHCARD */ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_CMDLINE_EDITING /* enable cmdline history */ #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_PROMPT "OMAP3 Tricorder # " #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ @@ -213,9 +296,9 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 0x01000000) /* 16MB */ + 0x07000000) /* 112 MB */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) @@ -226,7 +309,6 @@ */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ @@ -234,13 +316,8 @@ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* NAND and environment organization */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ - #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 @@ -253,11 +330,11 @@ #define CONFIG_SYS_SRAM_SIZE 0x10000 /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT @@ -271,12 +348,12 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */ +#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ @@ -289,21 +366,25 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20,\ - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\ - 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\ - 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\ - 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ + 13, 14, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 30, 31, 32, \ + 33, 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 44, 45, 46, 47, 48, 49, 50, 51, \ + 52, 53, 54, 55, 56} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 #endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 8e03f6f4c4..59f4f6767b 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -8,14 +8,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" -/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-trimslice -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (TrimSlice) # " #define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" @@ -39,10 +34,7 @@ /* I2C */ #define CONFIG_SYS_I2C_TEGRA -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C /* SD/MMC */ #define CONFIG_MMC @@ -68,6 +60,16 @@ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_TEGRA +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM + +/* PCI networking support */ +#define CONFIG_RTL8169 + /* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index c7c6952d2b..b7804d2872 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -14,7 +14,7 @@ * * Configuation settings for the LUBBOCK board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -125,7 +125,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -137,7 +136,6 @@ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ #else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #endif #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ @@ -150,7 +148,6 @@ #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ #ifdef CONFIG_MMC diff --git a/include/configs/tseries.h b/include/configs/tseries.h new file mode 100644 index 0000000000..9a6207048c --- /dev/null +++ b/include/configs/tseries.h @@ -0,0 +1,266 @@ +/* + * tseries.h + * + * specific parts for B&R T-Series Motherboard + * + * Copyright (C) 2013 Hannes Petermaier - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TSERIES_H__ +#define __CONFIG_TSERIES_H__ + +#include +/* ------------------------------------------------------------------------- */ +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65217 + +/* Support both device trees and ATAGs. */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMD_BOOTZ +/*#define CONFIG_MACH_TYPE 3589*/ +#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ + +/* MMC/SD IP block */ +#if defined(CONFIG_EMMC_BOOT) + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_OMAP_HSMMC + #define CONFIG_CMD_MMC + #define CONFIG_SUPPORT_EMMC_BOOT +/* RAW SD card / eMMC locations. */ + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */ + #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + #define CONFIG_SPL_MMC_SUPPORT +#endif /* CONFIG_EMMC_BOOT */ + +/* + * When we have SPI or NAND flash we expect to be making use of mtdparts, + * both for ease of use in U-Boot and for passing information on to + * the Linux kernel. + */ +#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND) +#define CONFIG_MTD_DEVICE /* Required for mtdparts */ +#define CONFIG_CMD_MTDPARTS +#endif /* CONFIG_SPI_BOOT, ... */ + +#undef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +/* NAND */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* CONFIG_NAND */ +#endif /* CONFIG_SPL_OS_BOOT */ + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif /* CONFIG_NAND */ + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandimgsize=0x500000\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} kernel ${nandimgsize}; " \ + "bootz ${loadaddr}\0" +#else +#define NANDARGS "" +#endif /* CONFIG_NAND */ + +#ifdef CONFIG_MMC +#define MMCARGS \ + "silent=1\0" +#else +#define MMCARGS "" +#endif /* CONFIG_MMC */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x80200000\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "rootpath=/tftpboot/tseries/rootfs-small\0" \ + "nfsopts=nolock\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "run netargs; " \ + "bootm ${loadaddr}\0" \ + "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 0x80000000 updateubootusb.img; " \ + "source;\0" \ + "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp;" \ + "tftp 0x80000000 updateUBOOT.img;" \ + "source;\0" \ + NANDARGS \ + MMCARGS +#endif /* !CONFIG_SPL_BUILD*/ + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot1;" +#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */ + +#ifdef CONFIG_NAND +/* + * GPMC block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_CMD_NAND +/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3)," \ + "512k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env)," \ + "5m(kernel),"\ + "-(rootfs)" +#endif /* CONFIG_NAND */ + +/* USB configuration */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +/* attention! not only for gadget, enables also highspeed in hostmode */ +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif /* CONFIG_MUSB_HOST */ + +#if defined(CONFIG_SPI_BOOT) +/* McSPI IP block */ +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_SPEED 24000000 + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ + +#elif defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#elif defined(CONFIG_NAND) +/* No NAND env support in SPL */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_ENV_IS_IN_NAND +#endif +#define CONFIG_ENV_OFFSET 0x120000 /* TODO: Adresse definieren */ +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE +#else +#error "no storage for Environment defined!" +#endif +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC +#endif /* CONFIG_MMC, ... */ + +#endif /* ! __CONFIG_TSERIES_H__ */ diff --git a/include/configs/tt01.h b/include/configs/tt01.h index a755d520d7..0f9d7e0da8 100644 --- a/include/configs/tt01.h +++ b/include/configs/tt01.h @@ -4,7 +4,7 @@ * * Configuration settings for the HALE TT-01 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -13,8 +13,6 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 -#define CONFIG_MX31 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -239,8 +237,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 - #define CONFIG_CMDLINE_EDITING /* MMC boot support */ diff --git a/include/configs/twister.h b/include/configs/twister.h index b6ca59c33c..f24dc136ca 100644 --- a/include/configs/twister.h +++ b/include/configs/twister.h @@ -50,4 +50,7 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_SPL_BOARD_INIT +/* gpio 55 is used as SPL_OS_BOOT_KEY */ +#define CONFIG_OMAP3_GPIO_2 + #endif /* __CONFIG_H */ diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 93dd3c58a8..b43dafb43a 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -2,7 +2,7 @@ * (C) Copyright 2009 DENX Software Engineering * Author: John Rigby * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -13,13 +13,13 @@ /* * KARO TX25 board - SoC Configuration */ -#define CONFIG_MX25 #define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TIMER_RATE CONFIG_MX25_CLK32 +#define CONFIG_SYS_TIMER_COUNTER \ + (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */ -#define CONFIG_SPL #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_MAX_SIZE 2048 @@ -94,14 +94,12 @@ * Flash & Environment */ /* No NOR flash present */ -#define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN #define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) /* NAND */ -#define CONFIG_NAND_MXC #define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (0xBB000000) @@ -110,7 +108,6 @@ #define CONFIG_SYS_NAND_LARGEPAGE /* U-Boot general configuration */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print buffer sz */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ @@ -123,16 +120,10 @@ /* U-Boot commands */ #include -#define CONFIG_CMD_NAND -#define CONFIG_CMD_CACHE /* * Ethernet */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f -#define CONFIG_MII -#define CONFIG_CMD_NET #define CONFIG_BOARD_LATE_INIT #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/tx28.h b/include/configs/tx28.h index ac7f3d94e3..565f7610c3 100644 --- a/include/configs/tx28.h +++ b/include/configs/tx28.h @@ -8,9 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX28 /* must be defined before including regs-base.h */ - -#include +#include #include /* @@ -18,7 +16,7 @@ */ #define CONFIG_MXS_GPIO /* GPIO control */ #define CONFIG_SYS_HZ 1000 /* Ticks per second */ -#define PHYS_SDRAM_1_SIZE CONFIG_SDRAM_SIZE +#define PHYS_SDRAM_1_SIZE CONFIG_SYS_SDRAM_SIZE #ifdef CONFIG_TX28_S #define TX28_MOD_SUFFIX "1" #else @@ -36,15 +34,15 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_LATE_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_GENERIC_BOARD /* LCD Logo and Splash screen support */ -#define CONFIG_LCD #ifdef CONFIG_LCD #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_VIDEO_MXS #define CONFIG_LCD_LOGO -#define LCD_BPP LCD_COLOR24 +#define LCD_BPP LCD_COLOR32 #define CONFIG_CMD_BMP #define CONFIG_VIDEO_BMP_RLE8 #endif /* CONFIG_LCD */ @@ -77,15 +75,11 @@ #define CONFIG_CMDLINE_EDITING /* Command history etc */ #define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_NO_FLASH /* * Flattened Device Tree (FDT) support */ -#define CONFIG_OF_LIBFDT #ifdef CONFIG_OF_LIBFDT -#define CONFIG_FDT_FIXUP_PARTITIONS -#define CONFIG_OF_BOARD_SETUP #endif /* @@ -109,7 +103,7 @@ #else #define CONFIG_LOADADDR 43000000 #endif -#define CONFIG_FDTADDR 41000000 +#define CONFIG_FDTADDR 40800000 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR) #define CONFIG_U_BOOT_IMG_SIZE SZ_1M @@ -162,18 +156,6 @@ #define MTD_NAME "gpmi-nand" #define MTDIDS_DEFAULT "nand0=" MTD_NAME -/* - * U-Boot Commands - */ -#include -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_BOOTCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_MEMTEST - /* * Serial Driver */ @@ -190,63 +172,35 @@ /* * Ethernet Driver */ -#define CONFIG_FEC_MXC #ifdef CONFIG_FEC_MXC /* This is required for the FEC driver to work with cache enabled */ #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH #define CONFIG_SYS_CACHELINE_SIZE 32 -#ifndef CONFIG_TX28_S -#define CONFIG_FEC_MXC_MULTI -#else +#ifdef CONFIG_FEC_MXC_PHYADDR #define IMX_FEC_BASE MXS_ENET0_BASE -#define CONFIG_FEC_MXC_PHYADDR 0x00 #endif -#define CONFIG_PHY_SMSC -#define CONFIG_PHYLIB -#define CONFIG_MII #define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM -#define CONFIG_NET_MULTI -#define CONFIG_CMD_MII -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -/* Add for working with "strict" DHCP server */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_RANDOM_ID #endif #ifndef CONFIG_ENV_IS_NOWHERE /* define one of the following options: -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_MMC */ -#define CONFIG_ENV_IS_IN_NAND #endif #define CONFIG_ENV_OVERWRITE /* * NAND flash driver */ -#ifdef CONFIG_CMD_NAND +#ifdef CONFIG_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K -#define CONFIG_MTD_DEVICE -#define CONFIG_NAND_MXS -#define CONFIG_APBH_DMA -#define CONFIG_APBH_DMA_BURST -#define CONFIG_APBH_DMA_BURST8 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_SYS_MXS_DMA_CHANNEL 4 #define CONFIG_SYS_NAND_MAX_CHIPS 0x1 #define CONFIG_SYS_MAX_NAND_DEVICE 0x1 #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BASE 0x00000000 -#define CONFIG_CMD_ROMUPDATE #else #undef CONFIG_ENV_IS_IN_NAND #endif /* CONFIG_CMD_NAND */ @@ -273,12 +227,8 @@ * MMC Driver */ #ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_MXS_MMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_DOS_PARTITION #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_CMD_EXT2 @@ -314,7 +264,6 @@ GENERATED_GBL_DATA_SIZE) /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -322,7 +271,8 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SYS_SPL_VDDD_VAL 1500 -#define CONFIG_SYS_SPL_BATT_BO_LEVEL 2800 +#define CONFIG_SYS_SPL_BATT_BO_LEVEL 2400 +#define CONFIG_SYS_SPL_VDDA_BO_VAL 100 #define CONFIG_SYS_SPL_VDDMEM_VAL 0 /* VDDMEM is not utilized on TX28 */ #endif /* __CONFIGS_TX28_H */ diff --git a/include/configs/tx48.h b/include/configs/tx48.h index dd7cf74a23..392879410d 100644 --- a/include/configs/tx48.h +++ b/include/configs/tx48.h @@ -15,7 +15,7 @@ #define CONFIG_AM33XX /* must be set before including omap.h */ -#include +#include #include /* @@ -31,16 +31,17 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_GENERIC_BOARD /* LCD Logo and Splash screen support */ -#define CONFIG_LCD #ifdef CONFIG_LCD +#define CONFIG_VIDEO_DA8XX #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_DA8XX +#define CONFIG_AM335X_LCD #define DAVINCI_LCD_CNTL_BASE 0x4830e000 #define CONFIG_LCD_LOGO -#define LCD_BPP LCD_COLOR24 +#define LCD_BPP LCD_COLOR32 #define CONFIG_CMD_BMP #define CONFIG_VIDEO_BMP_RLE8 #endif /* CONFIG_LCD */ @@ -83,13 +84,10 @@ #define CONFIG_CMDLINE_EDITING /* Command history etc */ #define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_NO_FLASH /* * Flattened Device Tree (FDT) support */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP /* * Boot Linux @@ -112,7 +110,6 @@ #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR) #define CONFIG_U_BOOT_IMG_SIZE SZ_1M -#define CONFIG_HW_WATCHDOG /* * Extra Environment Settings @@ -156,19 +153,6 @@ #define MTD_NAME "omap2-nand.0" #define MTDIDS_DEFAULT "nand0=" MTD_NAME -#define CONFIG_FDT_FIXUP_PARTITIONS - -/* - * U-Boot Commands - */ -#include -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_BOOTCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_MEMTEST /* * Serial Driver @@ -195,27 +179,13 @@ */ #ifdef CONFIG_CMD_NET #define CONFIG_DRIVER_TI_CPSW -#define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE -#define CONFIG_PHY_SMSC -#define CONFIG_PHYLIB -#define CONFIG_MII -#define CONFIG_CMD_MII -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -/* Add for working with "strict" DHCP server */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 #endif /* * NAND flash driver */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_MTD_DEVICE -#define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_GPMC_PREFETCH_ENABLE @@ -227,12 +197,10 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_SYS_NAND_MAX_CHIPS 0x1 #define CONFIG_SYS_NAND_MAXBAD 20 /* Max. number of bad blocks guaranteed by manufacturer */ #define CONFIG_SYS_MAX_NAND_DEVICE 0x1 #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_USE_FLASH_BBT #ifdef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) @@ -248,15 +216,9 @@ * MMC Driver */ #ifdef CONFIG_CMD_MMC -#ifndef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_MMC -#endif -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_OMAP_MMC_DEV_1 -#define CONFIG_DOS_PARTITION #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_CMD_EXT2 @@ -274,6 +236,10 @@ #endif /* CONFIG_ENV_IS_IN_MMC */ #endif /* CONFIG_CMD_MMC */ +#ifdef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE SZ_4K +#endif + #ifdef CONFIG_ENV_OFFSET_REDUND #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ "128k(u-boot-spl)," \ @@ -301,7 +267,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* Defines for SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_GPIO_SUPPORT diff --git a/include/configs/tx51.h b/include/configs/tx51.h index 19bb7c4986..55ad3da20d 100644 --- a/include/configs/tx51.h +++ b/include/configs/tx51.h @@ -8,9 +8,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX51 /* must be set before including imx-regs.h */ -#include +#include #include /* @@ -25,6 +24,7 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_LATE_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_GENERIC_BOARD #if CONFIG_SYS_CPU_CLK == 600 #define TX51_MOD_PREFIX "6" @@ -36,14 +36,13 @@ #endif /* LCD Logo and Splash screen support */ -#define CONFIG_LCD #ifdef CONFIG_LCD #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_VIDEO_IPUV3 #define CONFIG_IPUV3_CLK 133000000 #define CONFIG_LCD_LOGO -#define LCD_BPP LCD_COLOR24 +#define LCD_BPP LCD_COLOR32 #define CONFIG_CMD_BMP #define CONFIG_VIDEO_BMP_RLE8 #endif /* CONFIG_LCD */ @@ -81,13 +80,10 @@ #define CONFIG_CMDLINE_EDITING /* Command history etc */ #define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_NO_FLASH /* * Flattened Device Tree (FDT) support */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP /* * Boot Linux @@ -110,7 +106,6 @@ #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR) #define CONFIG_U_BOOT_IMG_SIZE SZ_1M -#define CONFIG_HW_WATCHDOG /* * Extra Environment Settings @@ -154,19 +149,6 @@ #define MTD_NAME "mxc_nand" #define MTDIDS_DEFAULT "nand0=" MTD_NAME -#define CONFIG_FDT_FIXUP_PARTITIONS - -/* - * U-Boot Commands - */ -#include -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_BOOTCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_MEMTEST /* * Serial Driver @@ -181,39 +163,21 @@ /* * Ethernet Driver */ -#define CONFIG_FEC_MXC #ifdef CONFIG_FEC_MXC #define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1f -#define CONFIG_PHYLIB -#define CONFIG_PHY_SMSC -#define CONFIG_MII #define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM -#define CONFIG_CMD_MII -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -/* Add for working with "strict" DHCP server */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS #endif /* * NAND flash driver */ #ifdef CONFIG_CMD_NAND -#define CONFIG_MTD_DEVICE -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_NAND_MXC #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_MXC_NAND_HWECC -#define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_SYS_NAND_MAX_CHIPS 0x1 #define CONFIG_SYS_MAX_NAND_DEVICE 0x1 #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_USE_FLASH_BBT #ifdef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE @@ -221,7 +185,6 @@ #define CONFIG_ENV_RANGE 0x60000 #endif #define CONFIG_SYS_NAND_BASE 0x00000000 -#define CONFIG_CMD_ROMUPDATE #endif /* CONFIG_CMD_NAND */ /* @@ -229,14 +192,9 @@ */ #ifdef CONFIG_CMD_MMC #ifndef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_MMC #endif -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_DOS_PARTITION #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_CMD_EXT2 diff --git a/include/configs/tx53.h b/include/configs/tx53.h index 7502e6726b..1e03ed719c 100644 --- a/include/configs/tx53.h +++ b/include/configs/tx53.h @@ -8,15 +8,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX53 /* must be set before including imx-regs.h */ - -#include +#include #include /* * Ka-Ro TX53 board - SoC configuration */ -#define CONFIG_TX53 /* TX53 SoM */ #define CONFIG_SYS_MX5_IOMUX_V3 #define CONFIG_MXC_GPIO /* GPIO control */ #define CONFIG_SYS_MX5_HCLK 24000000 @@ -26,16 +23,16 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_LATE_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_GENERIC_BOARD /* LCD Logo and Splash screen support */ -#define CONFIG_LCD #ifdef CONFIG_LCD #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_VIDEO_IPUV3 #define CONFIG_IPUV3_CLK 200000000 #define CONFIG_LCD_LOGO -#define LCD_BPP LCD_COLOR24 +#define LCD_BPP LCD_COLOR32 #define CONFIG_CMD_BMP #define CONFIG_VIDEO_BMP_RLE8 #endif /* CONFIG_LCD */ @@ -76,13 +73,10 @@ #define CONFIG_CMDLINE_EDITING /* Command history etc */ #define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_NO_FLASH /* * Flattened Device Tree (FDT) support */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP /* * Boot Linux @@ -105,7 +99,6 @@ #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR) #define CONFIG_U_BOOT_IMG_SIZE SZ_1M -#define CONFIG_HW_WATCHDOG #ifndef CONFIG_SYS_LVDS_IF #define DEFAULT_VIDEO_MODE "VGA" #else @@ -152,20 +145,6 @@ #define MTD_NAME "mxc_nand" #define MTDIDS_DEFAULT "nand0=" MTD_NAME -#define CONFIG_FDT_FIXUP_PARTITIONS - -/* - * U-Boot Commands - */ -#include -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_BOOTCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MEMTEST /* * Serial Driver @@ -184,32 +163,18 @@ /* * Ethernet Driver */ -#define CONFIG_FEC_MXC #ifdef CONFIG_FEC_MXC #define IMX_FEC_BASE FEC_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_PHYLIB -#define CONFIG_PHY_SMSC -#define CONFIG_MII #define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM -#define CONFIG_CMD_MII -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -/* Add for working with "strict" DHCP server */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS #endif /* * I2C Configs */ #ifdef CONFIG_CMD_I2C -#define CONFIG_HARD_I2C #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR -#define CONFIG_SYS_I2C_MX6_PORT1 #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x34 #endif @@ -218,17 +183,12 @@ * NAND flash driver */ #ifdef CONFIG_CMD_NAND -#define CONFIG_MTD_DEVICE -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_NAND_MXC #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_MXC_NAND_HWECC -#define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_SYS_NAND_MAX_CHIPS 0x1 #define CONFIG_SYS_MAX_NAND_DEVICE 0x1 #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_USE_FLASH_BBT #ifdef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE @@ -236,22 +196,14 @@ #define CONFIG_ENV_RANGE 0x60000 #endif #define CONFIG_SYS_NAND_BASE 0x00000000 -#define CONFIG_CMD_ROMUPDATE #endif /* CONFIG_CMD_NAND */ /* * MMC Driver */ -#ifdef CONFIG_CMD_MMC -#ifndef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_MMC -#endif -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_DOS_PARTITION #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_CMD_EXT2 diff --git a/include/configs/tx6.h b/include/configs/tx6.h index fd52fb8861..4e009fed3d 100644 --- a/include/configs/tx6.h +++ b/include/configs/tx6.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 + * Copyright (C) 2012-2015 * * SPDX-License-Identifier: GPL-2.0 * @@ -8,13 +8,13 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include +#include "mx6_common.h" /* * Ka-Ro TX6 board - SoC configuration */ -#define CONFIG_MX6 #define CONFIG_SYS_MX6_HCLK 24000000 #define CONFIG_SYS_MX6_CLK32 32768 #define CONFIG_SYS_HZ 1000 /* Ticks per second */ @@ -23,21 +23,21 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_LATE_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_GENERIC_BOARD -#ifndef CONFIG_MFG +#ifndef CONFIG_TX6_UBOOT_MFG /* LCD Logo and Splash screen support */ -#define CONFIG_LCD #ifdef CONFIG_LCD #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_VIDEO_IPUV3 #define CONFIG_IPUV3_CLK (CONFIG_SYS_SDRAM_CLK * 1000000 / 2) #define CONFIG_LCD_LOGO -#define LCD_BPP LCD_COLOR24 +#define LCD_BPP LCD_COLOR32 #define CONFIG_CMD_BMP #define CONFIG_VIDEO_BMP_RLE8 #endif /* CONFIG_LCD */ -#endif /* CONFIG_MFG */ +#endif /* CONFIG_TX6_UBOOT_MFG */ /* * Memory configuration options @@ -46,16 +46,21 @@ #define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */ #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH #define PHYS_SDRAM_1_WIDTH CONFIG_SYS_SDRAM_BUS_WIDTH +#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32) +#define PHYS_SDRAM_1_WIDTH 32 +#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_16) +#define PHYS_SDRAM_1_WIDTH 16 #else #define PHYS_SDRAM_1_WIDTH 64 #endif #define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH) -#ifdef CONFIG_MX6Q +#ifdef CONFIG_SOC_MX6Q #define CONFIG_SYS_SDRAM_CLK 528 #else #define CONFIG_SYS_SDRAM_CLK 400 #endif #define CONFIG_STACKSIZE SZ_128K +#define CONFIG_SPL_STACK (IRAM_BASE_ADDR + SZ_16K) #define CONFIG_SYS_MALLOC_LEN SZ_8M #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M) @@ -64,11 +69,11 @@ * U-Boot general configurations */ #define CONFIG_SYS_LONGHELP -#if defined(CONFIG_MX6Q) +#if defined(CONFIG_SOC_MX6Q) #define CONFIG_SYS_PROMPT "TX6Q U-Boot > " -#elif defined(CONFIG_MX6DL) +#elif defined(CONFIG_SOC_MX6DL) #define CONFIG_SYS_PROMPT "TX6DL U-Boot > " -#elif defined(CONFIG_MX6S) +#elif defined(CONFIG_SOC_MX6S) #define CONFIG_SYS_PROMPT "TX6S U-Boot > " #else #error Unsupported i.MX6 processor variant @@ -85,17 +90,13 @@ #define CONFIG_CMDLINE_EDITING /* Command history etc */ #define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_NO_FLASH /* * Flattened Device Tree (FDT) support */ -#define CONFIG_OF_LIBFDT #ifdef CONFIG_OF_LIBFDT -#ifndef CONFIG_NO_NAND -#define CONFIG_FDT_FIXUP_PARTITIONS +#ifdef CONFIG_TX6_NAND #endif -#define CONFIG_OF_BOARD_SETUP #endif /* CONFIG_OF_LIBFDT */ /* @@ -109,29 +110,28 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG #define CONFIG_SETUP_MEMORY_TAGS -#ifndef CONFIG_MFG +#ifndef CONFIG_TX6_UBOOT_MFG #define CONFIG_BOOTDELAY 1 #else #define CONFIG_BOOTDELAY 0 #endif #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_SYS_AUTOLOAD "no" +#define DEFAULT_BOOTCMD "run bootcmd_${boot_mode} bootm_cmd" +#ifndef CONFIG_TX6_UBOOT_MFG #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1" -#define DEFAULT_BOOTCMD "run bootcmd_${boot_mode} bootm_cmd" -#ifndef CONFIG_MFG #define CONFIG_BOOTCOMMAND DEFAULT_BOOTCMD #else #define CONFIG_BOOTCOMMAND "set bootcmd '" DEFAULT_BOOTCMD "';" \ "env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg" #define CONFIG_BOOTCMD_MFG_LOADADDR 10500000 #define CONFIG_DELAY_ENVIRONMENT -#endif /* CONFIG_MFG */ +#endif /* CONFIG_TX6_UBOOT_MFG */ #define CONFIG_LOADADDR 18000000 #define CONFIG_FDTADDR 11000000 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR) -#define CONFIG_HW_WATCHDOG #ifndef CONFIG_SYS_LVDS_IF #define DEFAULT_VIDEO_MODE "VGA" #else @@ -141,6 +141,7 @@ /* * Extra Environments */ +#ifndef CONFIG_TX6_UBOOT_MFG #ifdef CONFIG_ENV_IS_NOWHERE #define CONFIG_EXTRA_ENV_SETTINGS \ "autostart=no\0" \ @@ -174,6 +175,8 @@ "cpu_clk=800\0" \ "default_bootargs=set bootargs " CONFIG_BOOTARGS \ " ${append_bootargs}\0" \ + EMMC_BOOT_PART_STR \ + EMMC_BOOT_ACK_STR \ "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \ CONFIG_SYS_FDTSAVE_CMD \ "mtdids=" MTDIDS_DEFAULT "\0" \ @@ -184,9 +187,10 @@ "touchpanel=tsc2007\0" \ "video_mode=" DEFAULT_VIDEO_MODE "\0" #endif /* CONFIG_ENV_IS_NOWHERE */ +#endif /* CONFIG_TX6_UBOOT_MFG */ -#ifndef CONFIG_NO_NAND -#define CONFIG_SYS_DEFAULT_BOOT_MODE "nand" +#ifdef CONFIG_TX6_NAND +#define CONFIG_SYS_DEFAULT_BOOT_MODE "nand" #define CONFIG_SYS_BOOT_CMD_NAND \ "bootcmd_nand=set autostart no;run bootargs_ubifs;nboot linux\0" #define CONFIG_SYS_FDTSAVE_CMD \ @@ -196,36 +200,25 @@ #define MTDIDS_DEFAULT "nand0=" MTD_NAME #define CONFIG_SYS_NAND_ONFI_DETECTION #define MMC_ROOT_STR " root=/dev/mmcblk0p2 rootwait\0" -#define ROOTPART_UUID_STR "" +#define ROOTPART_UUID_STR "" +#define EMMC_BOOT_ACK_STR "" +#define EMMC_BOOT_PART_STR "" #else -#define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc" -#define CONFIG_SYS_BOOT_CMD_NAND "" +#define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_BOOT_CMD_NAND "" #define CONFIG_SYS_FDTSAVE_CMD \ - "fdtsave=mmc open 0 1;mmc write ${fdtaddr} " \ - xstr(CONFIG_SYS_DTB_BLKNO) " 80;mmc close 0 1\0" -#define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0" -#define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0" + "fdtsave=mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} 1" \ + ";mmc write ${fdtaddr} " xstr(CONFIG_SYS_DTB_BLKNO) " 80" \ + ";mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} 0\0" #define MTD_NAME "" #define MTDIDS_DEFAULT "" -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_MMC_BOOT_DEV 0 -#endif - -/* - * U-Boot Commands - */ -#include -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC -#ifndef CONFIG_NO_NAND -#define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#endif -#define CONFIG_CMD_BOOTCE -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_TIME -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MEMTEST +#define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0" +#define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0" +#define EMMC_BOOT_ACK_STR "emmc_boot_ack=1\0" +#define EMMC_BOOT_PART_STR "emmc_boot_part=" \ + xstr(CONFIG_SYS_MMCSD_FS_BOOT_PARTITION) "\0" +#endif /* CONFIG_TX6_NAND */ /* * Serial Driver @@ -244,36 +237,19 @@ /* * Ethernet Driver */ -#define CONFIG_FEC_MXC #ifdef CONFIG_FEC_MXC /* This is required for the FEC driver to work with cache enabled */ #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH -#define CONFIG_SYS_CACHELINE_SIZE 64 #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_PHYLIB -#define CONFIG_PHY_SMSC -#define CONFIG_MII #define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM -#define CONFIG_CMD_MII -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -/* Add for working with "strict" DHCP server */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS #endif /* * I2C Configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC +#ifdef CONFIG_SYS_I2C #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR -#define CONFIG_SYS_I2C_MX6_PORT1 #define CONFIG_SYS_I2C_SPEED 400000 #if defined(CONFIG_TX6_REV) #if CONFIG_TX6_REV == 0x1 @@ -294,45 +270,25 @@ #define CONFIG_RN5T567 /* TX6_REV == 3 */ #endif /* CONFIG_CMD_I2C */ -#ifndef CONFIG_ENV_IS_NOWHERE -/* define one of the following options: -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_MMC -*/ -#define CONFIG_ENV_IS_IN_NAND -#endif #define CONFIG_ENV_OVERWRITE /* * NAND flash driver */ -#ifndef CONFIG_NO_NAND -#define CONFIG_MTD_DEVICE -#if 0 -#define CONFIG_MTD_DEBUG -#define CONFIG_MTD_DEBUG_VERBOSE 4 -#endif -#define CONFIG_NAND_MXS -#define CONFIG_NAND_MXS_NO_BBM_SWAP -#define CONFIG_APBH_DMA -#define CONFIG_APBH_DMA_BURST -#define CONFIG_APBH_DMA_BURST8 -#define CONFIG_CMD_NAND_TRIMFFS +#ifdef CONFIG_TX6_NAND #define CONFIG_SYS_MXS_DMA_CHANNEL 4 #define CONFIG_SYS_MAX_FLASH_BANKS 0x1 #define CONFIG_SYS_NAND_MAX_CHIPS 0x1 #define CONFIG_SYS_MAX_NAND_DEVICE 0x1 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BASE 0x00000000 -#define CONFIG_CMD_ROMUPDATE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) #define CONFIG_ENV_SIZE SZ_128K #define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #undef CONFIG_ENV_IS_IN_NAND -#endif /* CONFIG_NO_NAND */ +#endif /* CONFIG_TX6_NAND */ #ifdef CONFIG_ENV_OFFSET_REDUND #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \ @@ -349,14 +305,10 @@ /* * MMC Driver */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_FSL_USDHC +#ifdef CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_DOS_PARTITION +#endif +#ifdef CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_CMD_EXT2 @@ -378,7 +330,7 @@ #define CONFIG_ENV_SIZE SZ_4K #endif -#ifndef CONFIG_NO_NAND +#ifdef CONFIG_TX6_NAND #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ xstr(CONFIG_SYS_U_BOOT_PART_SIZE) \ "@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) \ diff --git a/include/configs/txa5.h b/include/configs/txa5.h new file mode 100644 index 0000000000..fff51d95ad --- /dev/null +++ b/include/configs/txa5.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2015 + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#define CONFIG_SYS_TEXT_BASE 0x20100000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART0 +#define CONFIG_USART_ID ATMEL_ID_USART0 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define xstr(s) str(s) +#define str(s) #s +#define __pfx(x, s) (x##s) +#define _pfx(x, s) __pfx(x, s) + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "init=/linuxrc console=ttyS0,115200 ro debug panic=1" +#define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd" +#define CONFIG_LOADADDR 22000000 /* load address */ +#define CONFIG_FDTADDR 21000000 +#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) +#define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR) +#define CONFIG_U_BOOT_IMG_SIZE SZ_1M + +/* NAND flash */ +#ifdef CONFIG_TXA5_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 0x1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_SYS_NAND_U_BOOT_OFFS SZ_128K +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_RANGE 0x60000 +#endif /* CONFIG_ENV_IS_IN_NAND */ +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_SIZE SZ_128M +#define NAND_BASE CONFIG_SYS_NAND_BASE +#endif /* CONFIG_CMD_NAND */ + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 + +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ +#ifdef CONFIG_LCD +#ifndef __ASSEMBLY__ +extern int lcd_output_bpp; +#endif +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP lcd_output_bpp +#define CONFIG_LCD_LOGO +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_BMP_RLE8 +#endif + +#ifdef CONFIG_TXA5_NAND +#define CONFIG_SYS_DEFAULT_BOOT_MODE "nand" +#define CONFIG_SYS_BOOT_CMD_NAND \ + "bootcmd_nand=set autostart no;run bootargs_ubifs;nboot linux\0" +#define CONFIG_SYS_FDTSAVE_CMD \ + "fdtsave=fdt resize;nand erase.part dtb" \ + ";nand write ${fdtaddr} dtb ${fdtsize}\0" +#define MTD_NAME "atmel_nand" +#define MTDIDS_DEFAULT "nand0=" MTD_NAME +#ifdef CONFIG_ENV_OFFSET_REDUND +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "128k(u-boot-spl)," \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env2),6m(linux),32m(rootfs),89216k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro" +#else +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "128k(u-boot-spl)," \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env),6m(linux),32m(rootfs),89600k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro" +#endif + +#define MMC_ROOT_STR " root=/dev/mmcblk0p2 rootwait\0" +#define ROOTPART_UUID_STR "" + +#else /* CONFIG_TXA5_NAND */ +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_SYS_FDTSAVE_CMD \ + "fdtsave=mmc open 0 1;mmc write ${fdtaddr} " \ + xstr(CONFIG_SYS_DTB_BLKNO) " 80;mmc close 0 1\0" +#define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0" +#define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0" +#define MTD_NAME "" +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +#define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc" +#define CONFIG_SYS_BOOT_CMD_NAND "" +#define CONFIG_SYS_FDTSAVE_CMD \ + "fdtsave=mmc open 0 1;mmc write ${fdtaddr} " \ + xstr(CONFIG_SYS_DTB_BLKNO) " 80;mmc close 0 1\0" +#define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0" +#define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0" +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0x1 +#define CONFIG_DYNAMIC_MMC_DEVNO +#endif /* CONFIG_ENV_IS_IN_MMC */ +#endif /* CONFIG_TXA5_NAND */ + +/* + * Extra Environment Settings + */ +#ifdef CONFIG_ENV_IS_NOWHERE +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "autoload=no\0" \ + "bootdelay=-1\0" \ + "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "baseboard=stk5-v3\0" \ + "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mtdblock4 rootfstype=jffs2\0" \ + "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ + MMC_ROOT_STR \ + "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \ + " ip=dhcp\0" \ + "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \ + " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \ + "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \ + ";nboot linux\0" \ + "bootcmd_mmc=set autostart no;run bootargs_mmc" \ + ";fatload mmc 0 ${loadaddr} uImage\0" \ + CONFIG_SYS_BOOT_CMD_NAND \ + "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \ + ";dhcp\0" \ + "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \ + "boot_mode=" CONFIG_SYS_DEFAULT_BOOT_MODE "\0" \ + "default_bootargs=set bootargs " CONFIG_BOOTARGS \ + " ${append_bootargs}\0" \ + "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \ + CONFIG_SYS_FDTSAVE_CMD \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nfsroot=/tftpboot/rootfs\0" \ + "otg_mode=device\0" \ + ROOTPART_UUID_STR \ + "touchpanel=tsc2007\0" \ + "video_mode=VGA\0" +#endif /* CONFIG_ENV_IS_NOWHERE */ + + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "TXA5 U-Boot > " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Memtest start address */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M) + +#endif diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h index 0c97ab1894..8d7970a376 100644 --- a/include/configs/u8500_href.h +++ b/include/configs/u8500_href.h @@ -12,11 +12,9 @@ * (easy to change) */ #define CONFIG_U8500 -#define CONFIG_L2_OFF #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF -#define CONFIG_SYS_HZ 1000 /* must be 1000 */ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT @@ -31,7 +29,6 @@ #define CONFIG_ENV_SIZE (128*1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) #endif -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ /* * PL011 Configuration diff --git a/include/configs/uc100.h b/include/configs/uc100.h deleted file mode 100644 index 8bf7353bc1..0000000000 --- a/include/configs/uc100.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 /* enable 862 since the */ -#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */ - -#define CONFIG_UC100 1 /* ...on a UC100 module */ - -#define CONFIG_SYS_TEXT_BASE 0x40700000 - -#define MPC8XX_FACT 4 /* Multiply by 4 */ -#define MPC8XX_XIN 25000000 /* 25.0 MHz in */ -#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) - /* define if cant' use get_gclk_freq */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/uc100/uImage\0" \ - "kernel_addr=40000000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \ - "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \ - "cp.b 100000 40700000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* no status-led */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Power On Self Test support - */ -#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_SPR ) -#undef CONFIG_POST - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CONFIG_SYS_RESET_ADDRESS 0x90000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK 0x00000000 -#define CONFIG_SYS_SCCR (SCCR_EBDF11) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (0x00000d24) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */ -#define CONFIG_SYS_OR1_PRELIM 0xfc000a00 -#define CONFIG_SYS_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */ -#define CONFIG_SYS_OR2_PRELIM 0xfff00d24 -#define CONFIG_SYS_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */ -#define CONFIG_SYS_OR3_PRELIM 0xffff8f44 -#define CONFIG_SYS_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */ -#define CONFIG_SYS_OR4_PRELIM 0xffff0300 -#define CONFIG_SYS_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */ -#define CONFIG_SYS_OR5_PRELIM 0xffff8db0 - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR_VAL 0x30904114 /* for SDRAM */ -#define CONFIG_SYS_MBMR_VAL 0xff001111 /* for Interbus-MPM */ - -/*----------------------------------------------------------------------- - * I2C stuff - */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (24C164) - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define FEC_ENET -#define CONFIG_MII -#define CONFIG_MII_INIT 1 -#define CONFIG_SYS_DISCOVER_PHY 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h deleted file mode 100644 index a11745fdb9..0000000000 --- a/include/configs/uc101.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2003-2009 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_UC101 1 /* UC101 board */ -#define CONFIG_HOSTNAME uc101 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds" - -#include "manroland/common.h" -#include "manroland/mpc5200-common.h" - -/* - * Serial console configuration - */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Flash configuration - */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 - -/* - * Environment settings - */ -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/* - * Memory map - */ -#define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */ -#define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */ - -/* SRAM */ -#define CONFIG_SYS_SRAM_SIZE 0x200000 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044 - -#define CONFIG_SYS_MEMTEST_START 0x00300000 -#define CONFIG_SYS_MEMTEST_END 0x00f00000 - -#define CONFIG_SYS_LOAD_ADDR 0x300000 - -#define CONFIG_SYS_BOOTCS_CFG 0x00045D00 - -/* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_SIZE 0x00200000 -#define CONFIG_SYS_CS1_CFG 0x21D00 - -/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */ -#define CONFIG_SYS_CS3_START CONFIG_SYS_DISPLAY_BASE -#define CONFIG_SYS_CS3_SIZE 0x00000100 -#define CONFIG_SYS_CS3_CFG 0x00081802 - -/* Interbus Master 16 Bit */ -#define CONFIG_SYS_CS6_START CONFIG_SYS_IB_MASTER -#define CONFIG_SYS_CS6_SIZE 0x00010000 -#define CONFIG_SYS_CS6_CFG 0x00FF3500 - -/* Interbus EPLD 8 Bit */ -#define CONFIG_SYS_CS7_START CONFIG_SYS_IB_EPLD -#define CONFIG_SYS_CS7_SIZE 0x00010000 -#define CONFIG_SYS_CS7_CFG 0x00081800 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/ - -/*---------------------------------------------------------------------*/ -/* Display addresses */ -/*---------------------------------------------------------------------*/ -#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38) -#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30) - -#endif /* __CONFIG_H */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h new file mode 100644 index 0000000000..6e054c5ccb --- /dev/null +++ b/include/configs/udoo.h @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for Udoo board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#include +#include +#include + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define MACH_TYPE_UDOO 4800 +#define CONFIG_MACH_TYPE MACH_TYPE_UDOO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* SATA Configs */ + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +/* Network support */ + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc1\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H * */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h new file mode 100644 index 0000000000..9ad47f6933 --- /dev/null +++ b/include/configs/uniphier.h @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* U-boot - Common settings for UniPhier Family */ + +#ifndef __CONFIG_UNIPHIER_COMMON_H__ +#define __CONFIG_UNIPHIER_COMMON_H__ + +#if defined(CONFIG_MACH_PH1_PRO4) +#define CONFIG_DDR_NUM_CH0 2 +#define CONFIG_DDR_NUM_CH1 2 + +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x20000000 +#define CONFIG_SDRAM1_BASE 0xa0000000 +#define CONFIG_SDRAM1_SIZE 0x20000000 +#endif + +#if defined(CONFIG_MACH_PH1_LD4) +#define CONFIG_DDR_NUM_CH0 1 +#define CONFIG_DDR_NUM_CH1 1 + +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x10000000 +#define CONFIG_SDRAM1_BASE 0x90000000 +#define CONFIG_SDRAM1_SIZE 0x10000000 +#endif + +#if defined(CONFIG_MACH_PH1_SLD8) +#define CONFIG_DDR_NUM_CH0 1 +#define CONFIG_DDR_NUM_CH1 1 + +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x10000000 +#define CONFIG_SDRAM1_BASE 0x90000000 +#define CONFIG_SDRAM1_SIZE 0x10000000 +#endif + +#define CONFIG_I2C_EEPROM +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * Support card address map + */ +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) +# define CONFIG_SUPPORT_CARD_BASE 0x03f00000 +# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) +# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) +# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +# define CONFIG_SUPPORT_CARD_BASE 0x08000000 +# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) +# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630) +# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000) +#endif + +#ifdef CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE +#define CONFIG_SYS_NS16550_CLK 12288000 +#define CONFIG_SYS_NS16550_REG_SIZE -2 +#endif + +/* TODO: move to Kconfig and device tree */ +#if 0 +#define CONFIG_SYS_NS16550_SERIAL +#endif + +#define CONFIG_SMC911X + +#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE +#define CONFIG_SMC911X_32_BIT + +#define CONFIG_SYS_MALLOC_F_LEN 0x2000 + +/*----------------------------------------------------------------------- + * MMU and Cache Setting + *----------------------------------------------------------------------*/ + +/* Comment out the following to enable L1 cache */ +/* #define CONFIG_SYS_ICACHE_OFF */ +/* #define CONFIG_SYS_DCACHE_OFF */ + +/* Comment out the following to enable L2 cache */ +#define CONFIG_UNIPHIER_L2CACHE_ON + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#define CONFIG_TIMESTAMP + +/* FLASH related */ +#define CONFIG_MTD_DEVICE + +/* + * uncomment the following to disable FLASH related code. + */ +/* #define CONFIG_SYS_NO_FLASH */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI + +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_FLASH_BASE 0 + +/* + * flash_toggle does not work for out supoort card. + * We need to use flash_status_poll. + */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL + +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 + +/* serial console configuration */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_GENERIC_BOARD + +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_USE_ARCH_MEMSET +#define CONFIG_USE_ARCH_MEMCPY +#endif + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_CONS_INDEX 1 + +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. + */ +/* #define CONFIG_ENV_IS_IN_NAND */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x0 +/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ + +/* Time clock 1MHz */ +#define CONFIG_SYS_TIMER_RATE 1000000 + +/* + * By default, ARP timeout is 5 sec. + * The first ARP request does not seem to work. + * So we need to retry ARP request anyway. + * We want to shrink the interval until the second ARP request. + */ +#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 2 +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_NAND_DENALI_ECC_SIZE 1024 + +#define CONFIG_SYS_NAND_REGS_BASE 0x68100000 +#define CONFIG_SYS_NAND_DATA_BASE 0x68000000 + +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) + +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + +/* USB */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_DM + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * Network Configuration + */ +#define CONFIG_ETHADDR 00:21:83:24:00:00 +#define CONFIG_SERVERIP 192.168.11.1 +#define CONFIG_IPADDR 192.168.11.10 +#define CONFIG_GATEWAYIP 192.168.11.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 0x84000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_BOOTFILE "fit.itb" + +#define CONFIG_CMDLINE_EDITING /* add command line history */ + +#define CONFIG_BOOTCOMMAND "run $bootmode" + +#define CONFIG_ROOTPATH "/nfs/root/path" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs $bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ + "tftpboot; bootm;" + +#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "image_offset=0x00080000\0" \ + "image_size=0x00f00000\0" \ + "verify=n\0" \ + "norboot=run add_default_bootargs;" \ + "bootm $image_offset\0" \ + "nandboot=run add_default_bootargs;" \ + "nand read $loadaddr $image_offset $image_size;" \ + "bootm\0" \ + "add_default_bootargs=setenv bootargs $bootargs" \ + " console=ttyS0,$baudrate\0" \ + +/* Open Firmware flat tree */ +#define CONFIG_OF_LIBFDT + +#define CONFIG_HAVE_ARM_SECURE + +/* Memory Size & Mapping */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE + +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE +/* Thre is no memory hole */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE) +#else +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE) +#endif + +#define CONFIG_SYS_TEXT_BASE 0x84000000 + +#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#define CONFIG_SPL_TEXT_BASE 0x00040000 +#endif +#if defined(CONFIG_MACH_PH1_PRO4) +#define CONFIG_SPL_TEXT_BASE 0x00100000 +#endif + +#define CONFIG_BOARD_POSTCLK_INIT + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000) +#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000) +#else +#define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000) +#endif + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 + +#endif /* __CONFIG_UNIPHIER_COMMON_H__ */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h new file mode 100644 index 0000000000..84571f6e93 --- /dev/null +++ b/include/configs/usb_a9263.h @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2007-2013 + * Stelian Pop + * Lead Tech Design + * Thomas Petazzoni, Free Electrons, + * Mateusz Kulikowski + * + * Settings for Calao USB-A9263 board + * + * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap + * installed on board will not be able to load it properly. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + +#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* + * Hardware drivers + */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define AT91_SPI_CLK 8000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) +#endif + +#define MTDPARTS_DEFAULT \ + "mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)" + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x4000) +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_BOOTCOMMAND "nboot 21000000 0" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=" MTDPARTS_DEFAULT " " \ + "rw rootfstype=jffs2" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_LONGHELP + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +#endif diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h deleted file mode 100644 index bf044456ce..0000000000 --- a/include/configs/utx8245.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the utx8245 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_UTX8245 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define DEBUG 1 - -#define CONFIG_IDENT_STRING " [UTX5] " - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 57600 - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay -#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ -#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ -#define CONFIG_SERVERIP 10.8.17.105 /* Spree */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=FFA00000\0" \ - "ramdisk_addr=FF800000\0" \ - "u-boot_startaddr=FFB00000\0" \ - "u-boot_endaddr=FFB2FFFF\0" \ - "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \ -nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \ - "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \ - "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \ - "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \ - "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \ - "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \ -${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \ -${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\ -protect on ${u-boot_startaddr} ${u-boot_endaddr}" - -#define CONFIG_ENV_OVERWRITE - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_PCI -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_IMI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - - -/*----------------------------------------------------------------------- - * PCI configuration - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#define PCI_ENET0_IOADDR 0xF0000000 -#define PCI_ENET0_MEMADDR 0xF0000000 - -#define PCI_FIREWIRE_IOADDR 0xF1000000 -#define PCI_FIREWIRE_MEMADDR 0xF1000000 -/* -#define PCI_ENET0_IOADDR 0xFE000000 -#define PCI_ENET0_MEMADDR 0x80000000 - -#define PCI_FIREWIRE_IOADDR 0x81000000 -#define PCI_FIREWIRE_MEMADDR 0x81000000 -*/ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 256MB */ -/*#define CONFIG_SYS_VERY_BIG_RAM 1 */ - -/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector - * is actually located at FFF00100. Therefore, U-Boot is - * physically located at 0xFFB0_0000, but is also mirrored at - * 0xFFF0_0000. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*#define CONFIG_SYS_DRAM_TEST 1 */ -#define CONFIG_SYS_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */ -#define CONFIG_SYS_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */ - /* vectors and U-Boot */ - - -/*-------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - *------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_DATA_SIZE 128 /* Size in bytes reserved for */ - /* initial data */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/*-------------------------------------------------------------------- - * NS16550 Configuration - *------------------------------------------------------------------*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2) -# define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#else -# define CONFIG_SYS_NS16550_CLK 33000000 -#endif - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) -#define CONFIG_SYS_NS16550_COM3 0xFF000000 -#define CONFIG_SYS_NS16550_COM4 0xFF000008 - -/*-------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - *------------------------------------------------------------------*/ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CONFIG_SYS_HZ 1000 - -/*#define CONFIG_SYS_ETH_DEV_FN 0x7800 */ -/*#define CONFIG_SYS_ETH_IOBASE 0x00104000 */ - -/*-------------------------------------------------------------------- - * I2C Configuration - *------------------------------------------------------------------*/ -#if 1 -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#endif - -#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */ - /* Philips PCF8563 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ - -/*-------------------------------------------------------------------- - * Memory Control Configuration Register values - * - see sec. 4.12 of MPC8245 UM - *------------------------------------------------------------------*/ - -/**** MCCR1 ****/ -#define CONFIG_SYS_ROMNAL 0 -#define CONFIG_SYS_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2, - mem_freq = 100MHz */ - -#define CONFIG_SYS_BANK7_ROW 0 /* SDRAM bank 7-0 row address */ -#define CONFIG_SYS_BANK6_ROW 0 /* bit count */ -#define CONFIG_SYS_BANK5_ROW 0 -#define CONFIG_SYS_BANK4_ROW 0 -#define CONFIG_SYS_BANK3_ROW 0 -#define CONFIG_SYS_BANK2_ROW 0 -#define CONFIG_SYS_BANK1_ROW 2 -#define CONFIG_SYS_BANK0_ROW 2 - -/**** MCCR2, refresh interval clock cycles ****/ -#define CONFIG_SYS_REFINT 480 /* 33 MHz SDRAM clock was 480 */ - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CONFIG_SYS_BSTOPRE 1023 /* burst to precharge[0..9], */ - /* sets open page interval */ - -/**** MCCR3 ****/ -#define CONFIG_SYS_REFREC 7 /* Refresh to activate interval, trc */ - -/**** MCCR4 ****/ -#define CONFIG_SYS_PRETOACT 2 /* trp */ -#define CONFIG_SYS_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */ -#define CONFIG_SYS_ACTORW 2 /* trcd min */ -#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 0 /* we don't need extended ROM space */ -#define CONFIG_SYS_REGDIMM 0 - -/* calculate according to formula in sec. 6-22 of 8245 UM */ -#define CONFIG_SYS_PGMAX 50 /* how long the 8245 retains the */ - /* currently accessed page in memory */ - /* was 45 */ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */ - /* bits 7,6, and 3-0 MUST be 0 */ - -#if 0 -#define CONFIG_SYS_DLL_MAX_DELAY 0x04 -#else -#define CONFIG_SYS_DLL_MAX_DELAY 0 -#endif -#if 0 /* need for 33MHz SDRAM */ -#define CONFIG_SYS_DLL_EXTEND 0x80 -#else -#define CONFIG_SYS_DLL_EXTEND 0 -#endif -#define CONFIG_SYS_PCI_HOLD_DEL 0x20 - - -/* Memory bank settings. - * Only bits 20-29 are actually used from these values to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8245 user manual. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE/2 - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START CONFIG_SYS_MAX_RAM_SIZE/2 -#define CONFIG_SYS_BANK1_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK1_ENABLE 1 -#define CONFIG_SYS_BANK2_START 0x3ff00000 /* not available in this design */ -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -/*--------------------------------------------------------------------*/ -/* 4.4 - Output Driver Control Register */ -/*--------------------------------------------------------------------*/ -#define CONFIG_SYS_ODCR 0xe5 - -/*--------------------------------------------------------------------*/ -/* 4.8 - Error Handling Registers */ -/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/ -#define CONFIG_SYS_ERRENR1 0x11 /* enable SDRAM refresh overflow error */ - -/* SDRAM 0-256 MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -/*#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */ -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in dcache */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - - -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP) - -/* PCI memory */ -/*#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */ -/*#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */ - -/*Flash, config addrs, etc. */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ - -/* NOTE: environment is not EMBEDDED in the u-boot code. - It's stored in flash in its own separate sector. */ -#define CONFIG_ENV_IS_IN_FLASH 1 - -#if 1 /* AMD AM29LV033C */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ -#define CONFIG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */ -#define CONFIG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */ -#else /* AMD AM29LV116D */ -#define CONFIG_SYS_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ -#define CONFIG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */ -#define CONFIG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */ -#endif /* #if */ - -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Size of the Environment */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/v37.h b/include/configs/v37.h deleted file mode 100644 index 0fa55d6f3a..0000000000 --- a/include/configs/v37.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_V37 1 /* ...on a Marel V37 board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_LCD -#define CONFIG_MPC8XX_LCD -#define CONFIG_SHARP_LQ084V1DG21 -#undef CONFIG_LCD_LOGO - -/*----------------------------------------------------------------------------- - * I2C Configuration - *----------------------------------------------------------------------------- - */ -#define CONFIG_I2C 1 -#define CONFIG_SYS_I2C_SLAVE 0x2 - -#define CONFIG_8xx_CONS_SMC1 1 -#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs console=tty0 " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_DATE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=v37-1" -#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)" -*/ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE0 0x40000000 -#define CONFIG_SYS_FLASH_BASE1 0x60000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE1 - -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR 0x80000000/* Address of Environment */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#define CONFIG_ENV_OFFSET 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR 0xFFFFFF88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) -/* -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) -*/ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -#define CONFIG_SYS_OR_TIMING_FLASH 0xF56 - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V) - -#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V) - -/* - * BR1 and OR1 (Battery backed SRAM) - */ -#define CONFIG_SYS_BR1_PRELIM 0x80000401 -#define CONFIG_SYS_OR1_PRELIM 0xFFC00736 - -/* - * BR2 and OR2 (SDRAM) - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* Marel V37 mem setting */ - -#define CONFIG_SYS_BR3_CAN 0xC0000401 -#define CONFIG_SYS_OR3_CAN 0xFFFF0724 - -/* -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 -*/ - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 501010eb9c..7f6b0c7cb2 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -12,7 +12,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_V38B 1 /* ...on V38B board */ @@ -244,7 +243,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -259,8 +257,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if defined(CONFIG_CMD_KGDB) # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/vct.h b/include/configs/vct.h index 85a6c11137..83e4163e3f 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -25,10 +25,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */ @@ -298,7 +299,6 @@ int vct_gpio_get(int pin); #undef CONFIG_CMD_BEDBUG #undef CONFIG_CMD_CACHE #undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_CRC32 #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_EEPROM #undef CONFIG_CMD_EEPROM diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index a4b4732ce5..00787bbb28 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -4,7 +4,7 @@ * (C) Copyright 2010 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* * ve8313 board configuration file @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 #define CONFIG_VE8313 1 @@ -345,13 +344,11 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ -#define CONFIG_SYS_HZ 1000 /* 1ms ticks */ /* * For booting Linux, the board info and command line data diff --git a/include/configs/venice2.h b/include/configs/venice2.h new file mode 100644 index 0000000000..8880de86c4 --- /dev/null +++ b/include/configs/venice2.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Venice2) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 5c02c968f9..f195f8a6ea 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -8,14 +8,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" -/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-ventana -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (Ventana) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 8d3ff6aab7..900b89c997 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -9,7 +9,7 @@ * Philippe Robin, * Configuration for Versatile PB. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -19,18 +19,16 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ +#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */ #define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ #define CONFIG_SYS_MEMTEST_START 0x100000 #define CONFIG_SYS_MEMTEST_END 0x10000000 -#define CONFIG_SYS_HZ (1000000 / 256) -#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ -#define CONFIG_SYS_TIMER_INTERVAL 10000 -#define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4) -#define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */ +#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ +#define CONFIG_SYS_TIMER_RATE (1000000 / 256) +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#define CONFIG_SYS_TIMER_COUNTS_DOWN /* * control registers @@ -102,7 +100,8 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ - "netdev=25,0,0xf1010000,0xf1010010,eth0" + "netdev=25,0,0xf1010000,0xf1010010,eth0 "\ + "console=ttyAMA0,38400n1" /* * Static configuration when assigning fixed address diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h new file mode 100644 index 0000000000..7fb28a54ba --- /dev/null +++ b/include/configs/vexpress_aemv8a.h @@ -0,0 +1,261 @@ +/* + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VEXPRESS_AEMV8A_H +#define __VEXPRESS_AEMV8A_H + +/* We use generic board for v8 Versatile Express */ +#define CONFIG_SYS_GENERIC_BOARD + +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#ifndef CONFIG_SEMIHOSTING +#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING +#endif +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARMV8_SWITCH_TO_EL1 +#endif + +#define CONFIG_REMAKE_ELF + +#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \ + !defined(CONFIG_TARGET_VEXPRESS64_JUNO) +/* Base FVP and Juno not using GICv3 yet */ +#define CONFIG_GICV3 +#endif + +/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SUPPORT_RAW_INITRD + +/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF + +#define CONFIG_IDENT_STRING " vexpress_aemv8a" +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" + +/* Link Definitions */ +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +/* ATF loads u-boot here for BASE_FVP model */ +#define CONFIG_SYS_TEXT_BASE 0x88000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#elif CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_TEXT_BASE 0xe0000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#else +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#endif + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + + +/* SMP Spin Table Definitions */ +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#else +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#endif + +/* CS register bases for the original memory map. */ +#define V2M_PA_CS0 0x00000000 +#define V2M_PA_CS1 0x14000000 +#define V2M_PA_CS2 0x18000000 +#define V2M_PA_CS3 0x1c000000 +#define V2M_PA_CS4 0x0c000000 +#define V2M_PA_CS5 0x10000000 + +#define V2M_PERIPH_OFFSET(x) (x << 16) +#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) +#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) + +#define V2M_BASE 0x80000000 + +/* + * Physical addresses, offset from V2M_PA_CS0-3 + */ +#define V2M_NOR0 (V2M_PA_CS0) +#define V2M_NOR1 (V2M_PA_CS4) +#define V2M_SRAM (V2M_PA_CS1) + +/* Common peripherals relative to CS7. */ +#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) +#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) +#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) +#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define V2M_UART0 0x7ff80000 +#define V2M_UART1 0x7ff70000 +#else /* Not Juno */ +#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) +#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) +#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) +#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) +#endif + +#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) + +#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) +#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) + +#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) +#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) + +#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) + +#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) + +/* System register offsets. */ +#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) +#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) +#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +/* Generic Interrupt Controller Definitions */ +#ifdef CONFIG_GICV3 +#define GICD_BASE (0x2f000000) +#define GICR_BASE (0x2f100000) +#else + +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#define GICD_BASE (0x2f000000) +#define GICC_BASE (0x2c000000) +#elif CONFIG_TARGET_VEXPRESS64_JUNO +#define GICD_BASE (0x2C010000) +#define GICC_BASE (0x2C02f000) +#else +#define GICD_BASE (0x2C001000) +#define GICC_BASE (0x2C002000) +#endif +#endif + +#define CONFIG_SYS_MEMTEST_START V2M_BASE +#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) + +/* SMSC91C111 Ethernet Configuration */ +#define CONFIG_SMC91111 1 +#define CONFIG_SMC91111_BASE (0x01A000000) + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_PL011_CLOCK 7273800 +#else +#define CONFIG_PL011_CLOCK 24000000 +#endif +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_CONS_INDEX 0 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_SERIAL0 V2M_UART0 +#define CONFIG_SYS_SERIAL1 V2M_UART1 + +/* Command line configuration */ +#define CONFIG_MENU +/*#define CONFIG_MENU_SHOW*/ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTI +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PXE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Initial environment variables */ +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=uImage\0" \ + "kernel_addr_r=0x80000000\0" \ + "initrd_name=ramdisk.img\0" \ + "initrd_addr_r=0x88000000\0" \ + "fdt_name=devtree.dtb\0" \ + "fdt_addr_r=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" + +#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ + "0x1c090000 debug user_debug=31 "\ + "loglevel=9" + +#define CONFIG_BOOTCOMMAND "fdt addr $fdt_addr_r; fdt resize; " \ + "fdt chosen $initrd_addr_r $initrd_end; " \ + "bootm $kernel_addr_r - $fdt_addr_r" + +#define CONFIG_BOOTDELAY 1 + +#else + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x80000000\0" \ + "initrd_addr_r=0x88000000\0" \ + "fdt_addr_r=0x83000000\0" \ + "fdt_high=0xa0000000\0" + +#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0" +#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \ + "$initrd_addr_r:$initrd_size $fdt_addr_r" +#define CONFIG_BOOTDELAY -1 +#endif + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "VExpress64# " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#endif /* __VEXPRESS_AEMV8A_H */ diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index d1431e5c75..b43afa2938 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -5,7 +5,7 @@ * Configuration for Versatile Express. Parts were derived from other ARM * configurations. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __VEXPRESS_CA15X2_TC2_h @@ -15,6 +15,7 @@ #include "vexpress_common.h" #define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca15x2_tc2" -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SYSFLAGS_ADDR 0x1c010030 +#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR #endif diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h index 7926905b22..7719d59e15 100644 --- a/include/configs/vexpress_ca5x2.h +++ b/include/configs/vexpress_ca5x2.h @@ -5,7 +5,7 @@ * Configuration for Versatile Express. Parts were derived from other ARM * configurations. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __VEXPRESS_CA5X2_h diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h index 2c08caaa01..38ac4ed38d 100644 --- a/include/configs/vexpress_ca9x4.h +++ b/include/configs/vexpress_ca9x4.h @@ -5,7 +5,7 @@ * Configuration for Versatile Express. Parts were derived from other ARM * configurations. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __VEXPRESS_CA9X4_H diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 75a45000ec..2dea921045 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -6,7 +6,7 @@ * Configuration for Versatile Express. Parts were derived from other ARM * configurations. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __VEXPRESS_COMMON_H @@ -117,13 +117,12 @@ #define CONFIG_SYS_MEMTEST_START V2M_BASE #define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SYS_L2CACHE_OFF 1 #define CONFIG_INITRD_TAG 1 - +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_OF_LIBFDT 1 /* Size of malloc() pool */ @@ -132,6 +131,10 @@ #define SCTL_BASE V2M_SYSCTL #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) +#define CONFIG_SYS_TIMER_RATE 1000000 +#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) +#define CONFIG_SYS_TIMER_COUNTS_DOWN + /* SMSC9115 Ethernet from SMSC9118 family */ #define CONFIG_SMC911X 1 #define CONFIG_SMC911X_32_BIT 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 5a7a066377..d5d296b9a3 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -12,8 +12,8 @@ #include #include -#define CONFIG_VF610 +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -44,6 +44,38 @@ #undef CONFIG_CMD_IMLS +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_VF610_NFC +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR + +/* UBI */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* Dynamic MTD partition support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=fsl_nfc" +#define MTDPARTS_DEFAULT "mtdparts=fsl_nfc:" \ + "128k(vf-bcb)ro," \ + "1408k(u-boot)ro," \ + "512k(u-boot-env)," \ + "4m(kernel)," \ + "512k(fdt)," \ + "-(rootfs)" +#endif + #define CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -68,21 +100,35 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL +/* QSPI Configs*/ +#define CONFIG_FSL_QSPI + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_LE +#endif + /* I2C Configs */ #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C0_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x82000000 -#define CONFIG_SYS_TEXT_BASE 0x3f008000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_SYS_TEXT_BASE 0x3f408000 +#define CONFIG_BOARD_SIZE_LIMIT 524288 #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttyLP1\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -113,22 +159,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -140,19 +186,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -160,7 +206,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -171,7 +217,6 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "=> " #undef CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE \ @@ -184,7 +229,6 @@ #define CONFIG_SYS_MEMTEST_END 0x87C00000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 /* * Stack sizes @@ -209,11 +253,19 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH +#ifdef CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_OFFSET (12 * 64 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE (64 * 2048) +#define CONFIG_ENV_SECT_SIZE (64 * 2048) +#define CONFIG_ENV_RANGE (512 * 1024) +#define CONFIG_ENV_OFFSET 0x180000 +#endif #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h deleted file mode 100644 index cf88d68ea1..0000000000 --- a/include/configs/virtlab2.h +++ /dev/null @@ -1,472 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */ -#define CONFIG_TQM8xxL 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=virtlab2\0" \ - "bootfile=virtlab2/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=virtlab2/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if defined(CONFIG_LCD) -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#if defined(CONFIG_SPLASH_SCREEN) - #define CONFIG_CMD_BMP -#endif - - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* Map peripheral control registers on CS4 */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000 -#define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK) -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/vision2.h b/include/configs/vision2.h index c24ce9c057..6beef8901a 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -5,14 +5,13 @@ * * Configuration settings for the MX51-3Stack Freescale board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MX51 /* in a mx51 */ #define CONFIG_SYS_TEXT_BASE 0x97800000 #include @@ -57,11 +56,11 @@ * Use gpio 4 pin 25 as chip select for SPI flash * This corresponds to gpio 121 */ -#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8)) +#define CONFIG_SF_DEFAULT_CS 1 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_ENV_SPI_CS (1 | (121 << 8)) +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_MAX_HZ 25000000 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 @@ -157,7 +156,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index e171ae4c40..bef821f337 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -13,8 +13,6 @@ /*--------------------------------------------------------------------------*/ -#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ -#define CONFIG_AT91FAMILY #define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ #define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ #define CONFIG_ARCH_CPU_INIT @@ -116,6 +114,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT @@ -198,7 +197,6 @@ /* clocks */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ #define MHZ180 @@ -320,9 +318,8 @@ #define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0) #endif /* Ethernet */ @@ -330,6 +327,7 @@ #define CONFIG_RMII #define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 5 +#define CONFIG_AT91_WANTS_COMMON_PHY #define CONFIG_OVERWRITE_ETHADDR_ONCE @@ -362,7 +360,6 @@ */ #define CONFIG_SYS_MALLOC_LEN \ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ #ifndef CONFIG_RAMLOAD #define CONFIG_BOOTCOMMAND "run nfsboot" diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index b450ab5e17..175311cad9 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -8,7 +8,7 @@ * reinhard.arlt@esd-electronics.de * Based on the MPC8349EMDS config. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -29,7 +29,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ @@ -386,7 +385,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -397,7 +395,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ -#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -541,7 +538,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index ba92db3de6..2fb91a8f8c 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -17,7 +17,6 @@ #define CONFIG_SYS_TEXT_BASE 0xa0000000 #ifdef CONFIG_ONENAND -#define CONFIG_SPL #define CONFIG_SPL_ONENAND_SUPPORT #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000 #define CONFIG_SPL_ONENAND_LOAD_SIZE \ @@ -124,7 +123,6 @@ */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -136,7 +134,6 @@ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " #endif #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE \ @@ -150,7 +147,6 @@ /* * Clock Configuration */ -#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ #define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ @@ -289,7 +285,7 @@ /* * Memory settings */ -#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa +#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9 #define CONFIG_SYS_MSC1_VAL 0x02ccf974 #define CONFIG_SYS_MSC2_VAL 0x00000000 #ifdef CONFIG_RAM_256M diff --git a/include/configs/walnut.h b/include/configs/walnut.h index b23824bd0a..8b803a2ee0 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -2,7 +2,7 @@ * (C) Copyright 2000-2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ /* ...or on a SYCAMORE board */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 9c23b26200..e513cc642f 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -9,11 +9,11 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "mx6_common.h" #include #include -#include +#include -#define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -25,6 +25,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) @@ -55,6 +57,12 @@ #define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + /* MMC Configuration */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC @@ -69,6 +77,15 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + /* Ethernet Configuration */ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP @@ -97,23 +114,28 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif -#if defined(CONFIG_MX6DL) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb" -#elif defined(CONFIG_MX6Q) #define CONFIG_DEFAULT_FDT_FILE "imx6q-wandboard.dtb" -#elif defined(CONFIG_MX6S) -#define CONFIG_DEFAULT_FDT_FILE "imx6s-wandboard.dtb" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc0\0" \ + "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x11000000\0" \ + "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ @@ -134,27 +156,53 @@ "fi; " \ "fi\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ + "root=${mmcroot}; run videoargs\0" \ + "videoargs=" \ + "setenv nextcon 0; " \ + "if hdmidet; then " \ + "setenv bootargs ${bootargs} " \ + "video=mxcfb${nextcon}:dev=hdmi,1280x720M@60," \ + "if=RGB24; " \ + "setenv fbmen fbmem=28M; " \ + "setexpr nextcon ${nextcon} + 1; " \ + "else " \ + "echo - no HDMI monitor;" \ + "fi; " \ + "i2c dev 1; " \ + "if i2c probe 0x10; then " \ + "setenv bootargs ${bootargs} " \ + "video=mxcfb${nextcon}:dev=lcd,800x480@60," \ + "if=RGB666; " \ + "if test 0 -eq ${nextcon}; then " \ + "setenv fbmem fbmem=10M; " \ + "else " \ + "setenv fbmem ${fbmem},10M; " \ + "fi; " \ + "setexpr nextcon ${nextcon} + 1; " \ + "else " \ + "echo '- no FWBADAPT-7WVGA-LCD-F07A-0102 display';" \ + "fi; " \ + "setenv bootargs ${bootargs} ${fbmem}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -166,19 +214,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -186,7 +234,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ @@ -196,7 +244,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 @@ -206,7 +253,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/whistler.h b/include/configs/whistler.h index d5c7e3bbd6..e083cbd07f 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -8,14 +8,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include #include "tegra20-common.h" -/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra20-whistler -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - /* High-level configuration options */ #define V_PROMPT "Tegra20 (Whistler) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler" @@ -31,10 +26,7 @@ /* I2C */ #define CONFIG_SYS_I2C_TEGRA -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C /* SD/MMC */ #define CONFIG_MMC diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h index 2070a9b1bd..036c1e427e 100644 --- a/include/configs/wireless_space.h +++ b/include/configs/wireless_space.h @@ -21,7 +21,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD /* SoC Family Name */ /* SoC name */ #define CONFIG_KW88F6281 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/woodburn.h b/include/configs/woodburn.h index 3191ff98ae..c14f7d47d0 100644 --- a/include/configs/woodburn.h +++ b/include/configs/woodburn.h @@ -5,7 +5,7 @@ * * Configuration for the woodburn board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 6b7e81f307..fb9929170d 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -5,7 +5,7 @@ * * Configuration for the woodburn board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __WOODBURN_COMMON_CONFIG_H @@ -14,8 +14,6 @@ #include /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX35 #define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_SYS_DCACHE_OFF @@ -45,10 +43,9 @@ /* * Hardware drivers */ -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO @@ -56,7 +53,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 #define CONFIG_RTC_MC13XXX @@ -152,9 +149,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - - /* * Stack sizes * @@ -246,8 +240,6 @@ * Default environment and default scripts * to update uboot and load kernel */ -#define xstr(s) str(s) -#define str(s) #s #define CONFIG_HOSTNAME woodburn #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -267,9 +259,9 @@ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ "loadaddr=80800000\0" \ "kernel_addr_r=80800000\0" \ - "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ - "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ - "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ + "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \ "flash_self=run ramargs addip addtty addmtd addmisc;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ @@ -283,9 +275,9 @@ "run ramargs addip addtty addmtd addmisc;" \ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ "else echo Images not loades;fi\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ + "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ "update=protect off ${uboot_addr} +80000;" \ "erase ${uboot_addr} +80000;" \ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h index c86692da5c..25bfeef036 100644 --- a/include/configs/woodburn_sd.h +++ b/include/configs/woodburn_sd.h @@ -5,7 +5,7 @@ * * Configuration for the woodburn board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -17,12 +17,9 @@ /* Set TEXT in RAM */ #define CONFIG_SYS_TEXT_BASE 0x82000000 -#define CONFIG_BOOT_INTERNAL - /* * SPL */ -#define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/include/configs/x600.h b/include/configs/x600.h index 89cd501644..04187c0a31 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -20,7 +20,6 @@ #include /* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ_CLOCK 8300000 #define CONFIG_SYS_TEXT_BASE 0x00800040 @@ -75,18 +74,18 @@ /* Ethernet config options */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #define CONFIG_SPEAR_GPIO /* I2C config options */ -#define CONFIG_HARD_I2C -#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW +#define CONFIG_SYS_I2C_BASE 0xD0200000 #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 #define CONFIG_I2C_CHIPADDRESS 0x50 @@ -108,6 +107,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_GPIO #define CONFIG_CMD_I2C #define CONFIG_CMD_MEMORY @@ -172,7 +172,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_64BIT_VSPRINTF /* Use last 2 lwords in internal SRAM for bootcounter */ #define CONFIG_BOOTCOUNT_LIMIT @@ -182,26 +181,24 @@ #define CONFIG_UBI_PART ubi0 #define CONFIG_UBIFS_VOLUME rootfs -#define xstr(s) str(s) -#define str(s) #s - #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" #define CONFIG_EXTRA_ENV_SETTINGS \ "u-boot_addr=1000000\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ + "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ - "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ - "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};" \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ " ${filesize};" \ - "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ "upd=run load update\0" \ - "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ - "part=" xstr(CONFIG_UBI_PART) "\0" \ - "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ + "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ + "part=" __stringify(CONFIG_UBI_PART) "\0" \ + "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ " ${filesize}\0" \ @@ -224,11 +221,12 @@ "saveenv;boot\0" \ "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ "root=ubi0:rootfs rootfstype=ubifs\0" \ - "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ "kernel_fs=/boot/uImage \0" \ "kernel_addr=1000000\0" \ - "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ - "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ + __stringify(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ "dtb_addr=1800000\0" \ "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ @@ -275,7 +273,6 @@ /* * SPL related defines */ -#define CONFIG_SPL #define CONFIG_SPL_TEXT_BASE 0xd2800b00 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h new file mode 100644 index 0000000000..ecedfc3ab1 --- /dev/null +++ b/include/configs/x86-common.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifndef __CONFIG_X86_COMMON_H +#define __CONFIG_X86_COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_SYS_VSNPRINTF +#define CONFIG_ZBOOT_32 +#define CONFIG_PHYSMEM +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL + +#define CONFIG_LMB +#define CONFIG_OF_LIBFDT + +#define CONFIG_LZO +#define CONFIG_FIT +#undef CONFIG_ZLIB +#undef CONFIG_GZIP +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/* SATA AHCI storage */ + +#define CONFIG_SCSI_AHCI +#define CONFIG_SATA_INTEL +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA +#define CONFIG_SYS_64BIT_LBA + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* Generic TPM interfaced through LPC bus */ +#define CONFIG_TPM +#define CONFIG_TPM_TIS_LPC +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 + +/*----------------------------------------------------------------------- + * Real Time Clock Configuration + */ +#define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS + +/*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ + 9600, 19200, 38400, 115200} +#define CONFIG_SYS_NS16550_PORT_MAPPED + +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_STDIO_DEREGISTER + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_SUPPORT_VFAT +/************************************************************ + * ATAPI support (experimental) + ************************************************************/ +#define CONFIG_ATAPI + +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_EFI_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ + +#define CONFIG_CMD_PART +#define CONFIG_CMD_CBFS +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_PARTITION_UUIDS + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* x86 GPIOs are accessed through a PCI device */ +#define CONFIG_INTEL_ICH6_GPIO + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ECHO +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_IO +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SETGETDCR +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_TIME +#define CONFIG_CMD_GETTIME +#define CONFIG_CMD_XIMG +#define CONFIG_CMD_SCSI + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_CMD_ZBOOT +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTARGS \ + "root=/dev/sdb3 init=/sbin/init rootwait ro" +#define CONFIG_BOOTCOMMAND \ + "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01000000 +#define CONFIG_SYS_LOAD_ADDR 0x20000000 + +/*----------------------------------------------------------------------- + * Video Configuration + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SW_CURSOR +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_I8042_KBD +#define CONFIG_CFB_CONSOLE +#define CONFIG_CONSOLE_SCROLL_LINES 5 + +/*----------------------------------------------------------------------- + * CPU Features + */ + +#define CONFIG_SYS_X86_TSC_TIMER +#define CONFIG_SYS_PCAT_INTERRUPTS +#define CONFIG_SYS_PCAT_TIMER +#define CONFIG_SYS_NUM_IRQS 16 + +#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN 0x200000 +#define CONFIG_SYS_MALLOC_F_LEN (2 << 10) + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/*----------------------------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_ICH_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_SF +#define CONFIG_CMD_SF_TEST +#define CONFIG_CMD_SPI +#define CONFIG_SPI +#define CONFIG_OF_SPI_FLASH + +/*----------------------------------------------------------------------- + * Environment configuration + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x01000 + +/*----------------------------------------------------------------------- + * PCI configuration + */ +#define CONFIG_PCI + +/*----------------------------------------------------------------------- + * USB configuration + */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_PCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_TFTP_TSIZE +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +#define CONFIG_CMD_USB + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_STD_DEVICES_SETTINGS + +#endif /* __CONFIG_H */ diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 28c84db032..2999d1b0f5 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -14,7 +14,7 @@ * * Configuation settings for the xaeniax board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -84,7 +84,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #endif /* @@ -116,7 +115,6 @@ #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ /* diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h new file mode 100644 index 0000000000..006f5a4d16 --- /dev/null +++ b/include/configs/xfi3.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_XFI3_H__ +#define __CONFIGS_XFI3_H__ + +/* System configurations */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_VIDEO + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_OVERWRITE + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_FONT_4X6 +#define CONFIG_VIDEO_MXS_MODE_SYSTEM +#define CONFIG_SYS_BLACK_IN_WRITE +#define LCD_BPP LCD_COLOR16 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#endif + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_XFI3_H__ */ diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index f4f42c510d..0ccd73a868 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -64,7 +64,6 @@ /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* Extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_CMDLINE_EDITING /* add command line history */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h index 431e331f5c..a0151fe8f4 100644 --- a/include/configs/xilinx-ppc405.h +++ b/include/configs/xilinx-ppc405.h @@ -15,7 +15,6 @@ /* cpu parameter */ #define CONFIG_405 1 -#define CONFIG_4xx 1 #define CONFIG_XILINX_405 1 #include diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h index 2ec3dd18dd..f45700878e 100644 --- a/include/configs/xilinx-ppc440.h +++ b/include/configs/xilinx-ppc440.h @@ -9,7 +9,6 @@ #define __CONFIG_GEN_H /*CPU*/ -#define CONFIG_4xx 1 #define CONFIG_440 1 #define CONFIG_XILINX_440 1 diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index ea270509c1..15c9176521 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2002 Scott McNutt * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,11 +18,12 @@ #define CONFIG_XPEDITE1000 1 #define CONFIG_SYS_BOARD_NAME "XPedite1000" #define CONFIG_SYS_FORM_PMC 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 #define CONFIG_440GX 1 /* 440 GX */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xFFF80000 @@ -209,12 +210,10 @@ extern void out32(unsigned int, unsigned long); */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 97ce3eb542..3414230244 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -14,7 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ #define CONFIG_SYS_BOARD_NAME "XPedite5170" @@ -24,6 +23,8 @@ #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_ALTIVEC 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xfff00000 @@ -40,7 +41,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -556,12 +557,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 372135a89f..f966a8ad5e 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -16,12 +16,13 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 #define CONFIG_XPEDITE5200 1 #define CONFIG_SYS_BOARD_NAME "XPedite5200" #define CONFIG_SYS_FORM_PMC_XMC 1 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 @@ -39,7 +40,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -337,12 +338,10 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 31330eaa30..d6b6143500 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -16,12 +16,13 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8572 1 #define CONFIG_XPEDITE5370 1 #define CONFIG_SYS_BOARD_NAME "XPedite5370" #define CONFIG_SYS_FORM_3U_VPX 1 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 @@ -49,7 +50,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -411,12 +412,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 340d4be4c6..4536b94e91 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -16,13 +16,14 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_P2020 1 #define CONFIG_XPEDITE550X 1 #define CONFIG_SYS_BOARD_NAME "XPedite5500" #define CONFIG_SYS_FORM_PMC_XMC 1 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 @@ -49,7 +50,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -396,12 +397,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 4d3abf08bd..8508a8029e 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -2,7 +2,7 @@ * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -23,7 +23,6 @@ #define CONFIG_HOSTNAME yellowstone #endif #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 5d584fbad4..76717e4579 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -18,7 +18,6 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 386f9deb70..4d7a7fc755 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -15,7 +15,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_ZEUS 1 /* Board is Zeus */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EP 1 /* Specifc 405EP support*/ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 @@ -122,7 +121,6 @@ * Miscellaneous configurable options *----------------------------------------------------------------------*/ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -138,8 +136,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -286,7 +282,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -322,7 +317,7 @@ " ramdisk_size=${ramdisk_size}\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ + ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0," \ "${baudrate}\0" \ "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \ @@ -352,7 +347,7 @@ "file_fs=/zeus/rootfs_ba.img\0" \ "tftp_fs=tftp 100000 ${file_fs}\0" \ "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\ - "cp.b 100000 ff300000 580000\0" \ + "cp.b 100000 ff300000 580000\0" \ "upd_fs=run tftp_fs;run update_fs\0" \ "bootcmd=chkreset;run ramargs addip addtty addmisc;" \ "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index c2dbdcb99f..fe331bc082 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -3,7 +3,7 @@ * * Copyright (C) 2009-2010 Marek Vasut * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -99,7 +99,6 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#undef SPI_INIT #define SPI_DELAY udelay(10) #define SPI_SDA(val) zipitz2_spi_sda(val) @@ -117,7 +116,6 @@ unsigned char zipitz2_spi_read(void); */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -128,8 +126,6 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_LONGHELP /* undef to save memory */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #endif #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ @@ -141,7 +137,6 @@ unsigned char zipitz2_spi_read(void); * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ /* @@ -188,10 +183,10 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 #define CONFIG_SYS_FLASH_PROTECTION /* diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 765b849e25..2ad0b90871 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -10,11 +10,14 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_MX25 -#define CONFIG_SYS_HZ 1000 +#include + #define CONFIG_SYS_TEXT_BASE 0xA0000000 +#define CONFIG_SYS_TIMER_RATE 32768 +#define CONFIG_SYS_TIMER_COUNTER \ + (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) + #define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 /* * Environment settings diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h new file mode 100644 index 0000000000..864528a5ea --- /dev/null +++ b/include/configs/zynq-common.h @@ -0,0 +1,381 @@ +/* + * (C) Copyright 2012 Michal Simek + * (C) Copyright 2013 Xilinx, Inc. + * + * Common configuration options for all Zynq boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_COMMON_H +#define __CONFIG_ZYNQ_COMMON_H + +/* CPU clock */ +#ifndef CONFIG_CPU_FREQ_HZ +# define CONFIG_CPU_FREQ_HZ 800000000 +#endif + +/* Cache options */ +#define CONFIG_CMD_CACHE +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +# define CONFIG_SYS_L2_PL310 +# define CONFIG_SYS_PL310_BASE 0xf8f02000 +#endif + +/* Serial drivers */ +#define CONFIG_BAUDRATE 115200 +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* DCC driver */ +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#else +# define CONFIG_ZYNQ_SERIAL +#endif + +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) +# define CONFIG_NET_MULTI +# define CONFIG_ZYNQ_GEM +# define CONFIG_MII +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_PHYLIB +# define CONFIG_PHY_MARVELL +# define CONFIG_BOOTP_SERVERIP +# define CONFIG_BOOTP_BOOTPATH +# define CONFIG_BOOTP_GATEWAY +# define CONFIG_BOOTP_HOSTNAME +# define CONFIG_BOOTP_MAY_FAIL +# if !defined(CONFIG_ZYNQ_GEM_EMIO0) +# define CONFIG_ZYNQ_GEM_EMIO0 0 +# endif +# if !defined(CONFIG_ZYNQ_GEM_EMIO1) +# define CONFIG_ZYNQ_GEM_EMIO1 0 +# endif +#endif + +/* SPI */ +#ifdef CONFIG_ZYNQ_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SF +#endif + +/* NOR */ +#ifndef CONFIG_SYS_NO_FLASH +# define CONFIG_SYS_FLASH_BASE 0xE2000000 +# define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024) +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_MAX_FLASH_SECT 512 +# define CONFIG_SYS_FLASH_ERASE_TOUT 1000 +# define CONFIG_SYS_FLASH_WRITE_TOUT 5000 +# define CONFIG_FLASH_SHOW_PROGRESS 10 +# define CONFIG_SYS_FLASH_CFI +# undef CONFIG_SYS_FLASH_EMPTY_INFO +# define CONFIG_FLASH_CFI_DRIVER +# undef CONFIG_SYS_FLASH_PROTECTION +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +/* MMC */ +#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# define CONFIG_MMC +# define CONFIG_GENERIC_MMC +# define CONFIG_SDHCI +# define CONFIG_ZYNQ_SDHCI +# define CONFIG_CMD_MMC +#endif + +#ifdef CONFIG_ZYNQ_USB +# define CONFIG_USB_EHCI +# define CONFIG_CMD_USB +# define CONFIG_USB_STORAGE +# define CONFIG_USB_EHCI_ZYNQ +# define CONFIG_USB_ULPI_VIEWPORT +# define CONFIG_USB_ULPI +# define CONFIG_EHCI_IS_TDI +# define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +# define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ +# define CONFIG_USB_GADGET +# define CONFIG_USB_GADGET_DUALSPEED +# define CONFIG_USBDOWNLOAD_GADGET +# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 +# define DFU_DEFAULT_POLL_TIMEOUT 300 +# define CONFIG_DFU_FUNCTION +# define CONFIG_DFU_RAM +# define CONFIG_USB_GADGET_VBUS_DRAW 2 +# define CONFIG_G_DNL_VENDOR_NUM 0x03FD +# define CONFIG_G_DNL_PRODUCT_NUM 0x0300 +# define CONFIG_G_DNL_MANUFACTURER "Xilinx" +# define CONFIG_USB_GADGET +# define CONFIG_USB_CABLE_CHECK +# define CONFIG_CMD_DFU +# define CONFIG_CMD_THOR_DOWNLOAD +# define CONFIG_THOR_FUNCTION +# define DFU_ALT_INFO_RAM \ + "dfu_ram_info=" \ + "set dfu_alt_info " \ + "${kernel_image} ram 0x3000000 0x500000\\\\;" \ + "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \ + "${ramdisk_image} ram 0x2000000 0x600000\0" \ + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" + +# if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# define CONFIG_DFU_MMC +# define DFU_ALT_INFO_MMC \ + "dfu_mmc_info=" \ + "set dfu_alt_info " \ + "${kernel_image} fat 0 1\\\\;" \ + "${devicetree_image} fat 0 1\\\\;" \ + "${ramdisk_image} fat 0 1\0" \ + "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ + "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" + +# define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_MMC +# else +# define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM +# endif +#endif + +#if !defined(DFU_ALT_INFO) +# define DFU_ALT_INFO +#endif + +#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB) +# define CONFIG_SUPPORT_VFAT +# define CONFIG_CMD_FAT +# define CONFIG_CMD_EXT2 +# define CONFIG_FAT_WRITE +# define CONFIG_DOS_PARTITION +# define CONFIG_CMD_EXT4 +# define CONFIG_CMD_EXT4_WRITE +# define CONFIG_CMD_FS_GENERIC +#endif + +#define CONFIG_SYS_I2C_ZYNQ +/* I2C */ +#if defined(CONFIG_SYS_I2C_ZYNQ) +# define CONFIG_CMD_I2C +# define CONFIG_SYS_I2C +# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 +# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0 +#endif + +/* EEPROM */ +#ifdef CONFIG_ZYNQ_EEPROM +# define CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ +#endif + +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Environment */ +#ifndef CONFIG_ENV_IS_NOWHERE +# ifndef CONFIG_SYS_NO_FLASH +# define CONFIG_ENV_IS_IN_FLASH +# elif defined(CONFIG_SYS_NO_FLASH) +# define CONFIG_ENV_IS_NOWHERE +# endif + +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +# define CONFIG_ENV_OFFSET 0xE0000 +# define CONFIG_CMD_SAVEENV +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fit_image=fit.itb\0" \ + "load_addr=0x2000000\0" \ + "fit_size=0x800000\0" \ + "flash_off=0x100000\0" \ + "nor_flash_off=0xE2100000\0" \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" \ + "norboot=echo Copying FIT from NOR flash to RAM... && " \ + "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \ + "bootm ${load_addr}\0" \ + "sdboot=echo Copying FIT from SD to RAM... && " \ + "load mmc 0 ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "jtagboot=echo TFTPing FIT to RAM... && " \ + "tftpboot ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "usbboot=if usb start; then " \ + "echo Copying FIT from USB to RAM... && " \ + "load usb 0 ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "fi\0" \ + DFU_ALT_INFO + +#define CONFIG_BOOTCOMMAND "run $modeboot" +#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "zynq-uboot> " +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_LONGHELP +#define CONFIG_CLOCKS +#define CONFIG_CMD_CLK +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Physical Memory map */ +#define CONFIG_SYS_TEXT_BASE 0x4000000 + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +#define CONFIG_SYS_MALLOC_LEN 0xC00000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Enable the PL to be downloaded */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK +#define CONFIG_CMD_FPGA_LOADP +#define CONFIG_CMD_FPGA_LOADBP +#define CONFIG_CMD_FPGA_LOADFS + +/* Open Firmware flat tree */ +#define CONFIG_OF_LIBFDT + +/* FIT support */ +#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */ + +/* FDT support */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +/* Boot FreeBSD/vxWorks from an ELF image */ +#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) +# define CONFIG_API +# define CONFIG_CMD_ELF +# define CONFIG_SYS_MMC_MAX_DEVICE 1 +#endif + +#define CONFIG_SYS_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot.lds" + +/* Commands */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_TFTPPUT + +/* SPL part */ +#define CONFIG_CMD_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds" + +/* MMC support */ +#ifdef CONFIG_ZYNQ_SDHCI0 +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#endif + +/* Disable dcache for SPL just for sure */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_FPGA +#endif + +/* Address in RAM where the parameters must be copied by SPL. */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000 + +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" + +/* Not using MMC raw mode - just for compilation purpose */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 + +/* qspi mode is working fine */ +#ifdef CONFIG_ZYNQ_QSPI +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#endif + +/* for booting directly linux */ +#define CONFIG_SPL_OS_BOOT + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SPL_TEXT_BASE 0x0 + +/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ +#define CONFIG_SPL_MAX_SIZE 0x30000 + +/* The highest 64k OCM address */ +#define OCM_HIGH_ADDR 0xffff0000 + +/* Just define any reasonable size */ +#define CONFIG_SPL_STACK_SIZE 0x1000 + +/* SPL stack position - and stack goes down */ +#define CONFIG_SPL_STACK (OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE) + +/* On the top of OCM space */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_STACK + \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000 + +/* BSS setup */ +#define CONFIG_SPL_BSS_START_ADDR 0x100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_GENERIC_BOARD + +#endif /* __CONFIG_ZYNQ_COMMON_H */ diff --git a/include/configs/zynq.h b/include/configs/zynq.h deleted file mode 100644 index 79fa5bb53f..0000000000 --- a/include/configs/zynq.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2012 Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_H -#define __CONFIG_ZYNQ_H - -#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ -#define CONFIG_ZYNQ - -/* CPU clock */ -#define CONFIG_CPU_FREQ_HZ 800000000 -#define CONFIG_SYS_HZ 1000 - -/* Ram */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_TEXT_BASE 0 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_BAUDRATE 115200 - -/* XPSS Serial driver */ -#define CONFIG_ZYNQ_SERIAL -#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE -#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 - -/* Ethernet driver */ -#define CONFIG_NET_MULTI -#define CONFIG_ZYNQ_GEM -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 - -#define CONFIG_ZYNQ_SDHCI -#define CONFIG_ZYNQ_SDHCI0 - -/* MMC */ -#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) -# define CONFIG_MMC -# define CONFIG_GENERIC_MMC -# define CONFIG_SDHCI -# define CONFIG_ZYNQ_SDHCI -# define CONFIG_CMD_MMC -# define CONFIG_CMD_FAT -# define CONFIG_SUPPORT_VFAT -# define CONFIG_CMD_EXT2 -# define CONFIG_DOS_PARTITION -#endif - -#define CONFIG_ZYNQ_I2C0 - -/* I2C */ -#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) -# define CONFIG_CMD_I2C -# define CONFIG_ZYNQ_I2C -# define CONFIG_HARD_I2C -# define CONFIG_SYS_I2C_SPEED 100000 -# define CONFIG_SYS_I2C_SLAVE 1 -#endif - -#if defined(CONFIG_ZYNQ_DCC) -# define CONFIG_ARM_DCC -# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ -#endif - -/* Enable the PL to be downloaded */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_ZYNQPL -#define CONFIG_CMD_FPGA - -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_MAY_FAIL - -/* MII and Phylib */ -#define CONFIG_MII -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_PHYLIB -#define CONFIG_PHY_MARVELL - -/* Environment */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_SYS_MALLOC_LEN 0x400000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_LOAD_ADDR 0 -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* OF */ -#define CONFIG_FIT -#define CONFIG_OF_LIBFDT - -/* Commands */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII - -#endif /* __CONFIG_ZYNQ_H */ diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h new file mode 100644 index 0000000000..549a664ef5 --- /dev/null +++ b/include/configs/zynq_microzed.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_MICROZED_H +#define __CONFIG_ZYNQ_MICROZED_H + +#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 + +#include + +#endif /* __CONFIG_ZYNQ_MICROZED_H */ diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h new file mode 100644 index 0000000000..b6590547a9 --- /dev/null +++ b/include/configs/zynq_zc70x.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZC70X_H +#define __CONFIG_ZYNQ_ZC70X_H + +#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_USB +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_EEPROM +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include + +#endif /* __CONFIG_ZYNQ_ZC70X_H */ diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h new file mode 100644 index 0000000000..16b904743f --- /dev/null +++ b/include/configs/zynq_zc770.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration settings for the Xilinx Zynq ZC770 board. + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZC770_H +#define __CONFIG_ZYNQ_ZC770_H + +#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_NO_FLASH + +#if defined(CONFIG_ZC770_XM010) +# define CONFIG_ZYNQ_SERIAL_UART1 +# define CONFIG_ZYNQ_GEM0 +# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 +# define CONFIG_ZYNQ_SDHCI0 +# define CONFIG_ZYNQ_SPI + +#elif defined(CONFIG_ZC770_XM012) +# define CONFIG_ZYNQ_SERIAL_UART1 +# undef CONFIG_SYS_NO_FLASH + +#elif defined(CONFIG_ZC770_XM013) +# define CONFIG_ZYNQ_SERIAL_UART0 +# define CONFIG_ZYNQ_GEM1 +# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7 + +#else +# define CONFIG_ZYNQ_SERIAL_UART0 +#endif + +#include + +#endif /* __CONFIG_ZYNQ_ZC770_H */ diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h new file mode 100644 index 0000000000..946de953e4 --- /dev/null +++ b/include/configs/zynq_zed.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration for Zynq Evaluation and Development Board - ZedBoard + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZED_H +#define __CONFIG_ZYNQ_ZED_H + +#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_USB +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include + +#endif /* __CONFIG_ZYNQ_ZED_H */ diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h new file mode 100644 index 0000000000..191f2a5f30 --- /dev/null +++ b/include/configs/zynq_zybo.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2012 Xilinx + * (C) Copyright 2014 Digilent Inc. + * + * Configuration for Zynq Development Board - ZYBO + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZYBO_H +#define __CONFIG_ZYNQ_ZYBO_H + +#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_BOOT_FREEBSD + +/* Define ZYBO PS Clock Frequency to 50MHz */ +#define CONFIG_ZYNQ_PS_CLK_FREQ 50000000UL + +#include + +#endif /* __CONFIG_ZYNQ_ZYBO_H */ diff --git a/include/cortina.h b/include/cortina.h new file mode 100644 index 0000000000..6cadd28811 --- /dev/null +++ b/include/cortina.h @@ -0,0 +1,75 @@ +/* + * Cortina PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef _CORTINA_H_ +#define _CORTINA_H_ + +#define VILLA_GLOBAL_CHIP_ID_LSB 0x000 +#define VILLA_GLOBAL_CHIP_ID_MSB 0x001 +#define VILLA_GLOBAL_BIST_CONTROL 0x002 +#define VILLA_GLOBAL_BIST_STATUS 0x003 +#define VILLA_GLOBAL_LINE_SOFT_RESET 0x007 +#define VILLA_GLOBAL_HOST_SOFT_RESET 0x008 +#define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A +#define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B +#define VILLA_GLOBAL_MSEQCLKCTRL 0x00E +#define VILLA_MSEQ_OPTIONS 0x1D0 +#define VILLA_MSEQ_PC 0x1D3 +#define VILLA_MSEQ_BANKSELECT 0x1DF +#define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB +#define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E +#define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403 +#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404 +#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405 +#define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369 +#define VILLA_MSEQ_ENABLE_MSB 0x194 +#define VILLA_MSEQ_SPARE21_LSB 0x226 +#define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0 +#define VILLA_MSEQ_SPARE12_MSB 0x215 +#define VILLA_MSEQ_SPARE2_LSB 0x200 +#define VILLA_MSEQ_SPARE7_LSB 0x20A +#define VILLA_MSEQ_SPARE9_LSB 0x20E +#define VILLA_MSEQ_SPARE3_LSB 0x202 +#define VILLA_MSEQ_SPARE3_MSB 0x203 +#define VILLA_MSEQ_SPARE8_LSB 0x20C +#define VILLA_MSEQ_SPARE8_MSB 0x20D +#define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2 +#define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4 +#define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6 +#define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8 +#define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA +#define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC +#define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0 +#define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE +#define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2 +#define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2 +#define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360 +#define VILLA_MSEQ_POWER_DOWN_LSB 0x198 +#define VILLA_MSEQ_POWER_DOWN_MSB 0x199 +#define VILLA_MSEQ_CAL_RX_SLICER 0x1B8 +#define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365 +#define VILLA_MSEQ_COEF_INIT_SEL 0x1AE +#define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A +#define VILLA_MSEQ_SERDES_PARAM_LSB 0x195 +#define VILLA_MSEQ_SPARE25_LSB 0x22E +#define VILLA_MSEQ_SPARE23_LSB 0x22A +#define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA +#define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030 +#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812 +#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813 +#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427 +#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428 + +#define mseq_edc_bist_done (0x1<<0) +#define mseq_edc_bist_fail (0x1<<8) + +struct cortina_reg_config { + unsigned short reg_addr; + unsigned short reg_value; +}; +#endif diff --git a/include/cpsw.h b/include/cpsw.h index 296b0e557f..547b40c57b 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -19,7 +19,7 @@ struct cpsw_slave_data { u32 slave_reg_ofs; u32 sliver_reg_ofs; - int phy_id; + int phy_addr; int phy_if; }; @@ -39,10 +39,12 @@ struct cpsw_platform_data { int ale_entries; /* ale table size */ u32 host_port_reg_ofs; /* cpdma host port registers */ u32 hw_stats_reg_ofs; /* cpsw hw stats counters */ + u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */ u32 mac_control; struct cpsw_slave_data *slave_data; void (*control)(int enabled); u32 host_port_num; + u32 active_slave; u8 version; }; diff --git a/include/cramfs/cramfs_fs_sb.h b/include/cramfs/cramfs_fs_sb.h deleted file mode 100644 index bc23f94b94..0000000000 --- a/include/cramfs/cramfs_fs_sb.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _CRAMFS_FS_SB -#define _CRAMFS_FS_SB - -/* - * cramfs super-block data in memory - */ -struct cramfs_sb_info { - unsigned long magic; - unsigned long size; - unsigned long blocks; - unsigned long files; - unsigned long flags; -#ifdef CONFIG_CRAMFS_LINEAR - unsigned long linear_phys_addr; - char * linear_virt_addr; -#endif -}; - -#endif diff --git a/include/cros_ec.h b/include/cros_ec.h index 1e89f29eea..8457c80c5e 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -13,17 +13,24 @@ #include #include #include +#include +#ifndef CONFIG_DM_CROS_EC /* Which interface is the device on? */ enum cros_ec_interface_t { CROS_EC_IF_NONE, CROS_EC_IF_SPI, CROS_EC_IF_I2C, CROS_EC_IF_LPC, /* Intel Low Pin Count interface */ + CROS_EC_IF_SANDBOX, }; +#endif /* Our configuration information */ struct cros_ec_dev { +#ifdef CONFIG_DM_CROS_EC + struct udevice *dev; /* Transport device */ +#else enum cros_ec_interface_t interface; struct spi_slave *spi; /* Our SPI slave, if using SPI */ int node; /* Our node */ @@ -32,8 +39,9 @@ struct cros_ec_dev { unsigned int addr; /* Device address (for I2C) */ unsigned int bus_num; /* Bus number (for I2C) */ unsigned int max_frequency; /* Maximum interface frequency */ - struct fdt_gpio_state ec_int; /* GPIO used as EC interrupt line */ - int cmd_version_is_supported; /* Device supports command versions */ +#endif + struct gpio_desc ec_int; /* GPIO used as EC interrupt line */ + int protocol_version; /* Protocol version to use */ int optimise_flash_write; /* Don't write erased flash blocks */ /* @@ -63,6 +71,17 @@ struct mbkp_keyscan { uint8_t data[CROS_EC_KEYSCAN_COLS]; }; +/* Holds information about the Chrome EC */ +struct fdt_cros_ec { + struct fmap_entry flash; /* Address and size of EC flash */ + /* + * Byte value of erased flash, or -1 if not known. It is normally + * 0xff but some flash devices use 0 (e.g. STM32Lxxx) + */ + int flash_erase_value; + struct fmap_entry region[EC_FLASH_REGION_COUNT]; +}; + /** * Read the ID of the CROS-EC device * @@ -140,7 +159,7 @@ enum { }; /** - * Set up the Chromium OS matrix keyboard protocol + * Initialise the Chromium OS EC driver * * @param blob Device tree blob containing setup information * @param cros_ecp Returns pointer to the cros_ec device, or NULL if none @@ -157,7 +176,7 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp); * @param info Place to put the info structure */ int cros_ec_info(struct cros_ec_dev *dev, - struct ec_response_cros_ec_info *info); + struct ec_response_mkbp_info *info); /** * Read the host event flags @@ -221,11 +240,28 @@ int cros_ec_flash_update_rw(struct cros_ec_dev *dev, */ struct cros_ec_dev *board_get_cros_ec_dev(void); +#ifdef CONFIG_DM_CROS_EC + +struct dm_cros_ec_ops { + int (*check_version)(struct udevice *dev); + int (*command)(struct udevice *dev, uint8_t cmd, int cmd_version, + const uint8_t *dout, int dout_len, + uint8_t **dinp, int din_len); + int (*packet)(struct udevice *dev, int out_bytes, int in_bytes); +}; + +#define dm_cros_ec_get_ops(dev) \ + ((struct dm_cros_ec_ops *)(dev)->driver->ops) + +int cros_ec_register(struct udevice *dev); + +#else /* !CONFIG_DM_CROS_EC */ /* Internal interfaces */ int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob); int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob); int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob); +int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob); /** * Read information from the fdt for the i2c cros_ec interface @@ -245,12 +281,20 @@ int cros_ec_i2c_decode_fdt(struct cros_ec_dev *dev, const void *blob); */ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob); +/** + * Read information from the fdt for the sandbox cros_ec interface + * + * @param dev CROS-EC device + * @param blob Device tree blob + * @return 0 if ok, -1 if we failed to read all required information + */ +int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob); + /** * Check whether the LPC interface supports new-style commands. * * LPC has its own way of doing this, which involves checking LPC values - * visible to the host. Do this, and update dev->cmd_version_is_supported - * accordingly. + * visible to the host. Do this, and update dev->protocol_version accordingly. * * @param dev CROS-EC device to check */ @@ -301,6 +345,22 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const uint8_t *dout, int dout_len, uint8_t **dinp, int din_len); +/** + * Send a packet to a CROS-EC device and return the response packet. + * + * Expects the request packet to be stored in dev->dout. Stores the response + * packet in dev->din. + * + * @param dev CROS-EC device + * @param out_bytes Size of request packet to output + * @param in_bytes Maximum size of response packet to receive + * @return number of bytes in response packet, or <0 on error + */ +int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes); +int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, + int in_bytes); +#endif + /** * Dump a block of data for a command. * @@ -431,4 +491,54 @@ int cros_ec_set_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t state); * @return 0 if ok, -1 on error */ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state); + +/** + * Initialize the Chrome OS EC at board initialization time. + * + * @return 0 if ok, -ve on error + */ +int cros_ec_board_init(void); + +/** + * Get access to the error reported when cros_ec_board_init() was called + * + * This permits delayed reporting of the EC error if it failed during + * early init. + * + * @return error (0 if there was no error, -ve if there was an error) + */ +int cros_ec_get_error(void); + +/** + * Returns information from the FDT about the Chrome EC flash + * + * @param blob FDT blob to use + * @param node Node offset to read from + * @param config Structure to use to return information + */ +int cros_ec_decode_ec_flash(const void *blob, int node, + struct fdt_cros_ec *config); + +/** + * Check the current keyboard state, in case recovery mode is requested. + * This function is for sandbox only. + * + * @param ec CROS-EC device + */ +void cros_ec_check_keyboard(struct cros_ec_dev *dev); + +/* + * Tunnel an I2C transfer to the EC + * + * @param dev CROS-EC device + * @param chip Chip address (7-bit I2C address) + * @param addr Register address to read/write + * @param alen Length of register address in bytes + * @param buffer Buffer containing data to read/write + * @param len Length of buffer + * @param is_read 1 if this is a read, 0 if this is a write + */ +int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr, + int alen, uchar *buffer, int len, int is_read); + #endif diff --git a/include/cros_ec_message.h b/include/cros_ec_message.h index b1da53db1b..36e2d83ce1 100644 --- a/include/cros_ec_message.h +++ b/include/cros_ec_message.h @@ -23,7 +23,7 @@ enum { MSG_PROTO_BYTES = MSG_HEADER_BYTES + MSG_TRAILER_BYTES, /* Max length of messages */ - MSG_BYTES = EC_HOST_PARAM_SIZE + MSG_PROTO_BYTES, + MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE + MSG_PROTO_BYTES, }; #endif diff --git a/include/da9030.h b/include/da9030.h deleted file mode 100644 index 275d6813b0..0000000000 --- a/include/da9030.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2006 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* DA9030 register definitions */ -#define CID 0x00 -#define EVENT_A 0x01 -#define EVENT_B 0x02 -#define EVENT_C 0x03 -#define STATUS 0x04 -#define IRQ_MASK_A 0x05 -#define IRQ_MASK_B 0x06 -#define IRQ_MASK_C 0x07 -#define SYS_CONTROL_A 0x08 -#define SYS_CONTROL_B 0x09 -#define FAULT_LOG 0x0A -#define LDO_10_11 0x10 -#define LDO_15 0x11 -#define LDO_14_16 0x12 -#define LDO_18_19 0x13 -#define LDO_17_SIMCP0 0x14 -#define BUCK2_DVC1 0x15 -#define BUCK2_DVC2 0x16 -#define REG_CONTROL_1_17 0x17 -#define REG_CONTROL_2_18 0x18 -#define USBPUMP 0x19 -#define SLEEP_CONTROL 0x1A -#define STARTUP_CONTROL 0x1B -#define LED1_CONTROL 0x20 -#define LED2_CONTROL 0x21 -#define LED3_CONTROL 0x22 -#define LED4_CONTROL 0x23 -#define LEDPC_CONTROL 0x24 -#define WLED_CONTROL 0x25 -#define MISC_CONTROLA 0x26 -#define MISC_CONTROLB 0x27 -#define CHARGE_CONTROL 0x28 -#define CCTR_CONTROL 0x29 -#define TCTR_CONTROL 0x2A -#define CHARGE_PULSE 0x2B - -/* ... some missing ...*/ - -#define LDO1 0x90 -#define LDO2_3 0x91 -#define LDO4_5 0x92 -#define LDO6_SIMCP 0x93 -#define LDO7_8 0x94 -#define LDO9_12 0x95 -#define BUCK 0x96 -#define REG_CONTROL_1_97 0x97 -#define REG_CONTROL_2_98 0x98 -#define REG_SLEEP_CONTROL1 0x99 -#define REG_SLEEP_CONTROL2 0x9A -#define REG_SLEEP_CONTROL3 0x9B -#define ADC_MAN_CONTROL 0xA0 -#define ADC_AUTO_CONTROL 0xA1 -#define VBATMON 0xA2 -#define VBATMONTXMON 0xA3 -#define TBATHIGHP 0xA4 -#define TBATHIGHN 0xA5 -#define TBATLOW 0xA6 -#define MAN_RES 0xB0 -#define VBAT_RES 0xB1 -#define VBATMIN_RES 0xB2 -#define VBATMINTXON_RES 0xB3 -#define ICHMAX_RES 0xB4 -#define ICHMIN_RES 0xB5 -#define ICHAVERAGE_RES 0xB6 -#define VCHMAX_RES 0xB7 -#define VCHMIN_RES 0xB8 -#define TBAT_RES 0xB9 -#define ADC_IN4_RES 0xBA - -#define STATUS_ONKEY_N 0x1 /* current ONKEY_N value */ -#define STATUS_PWREN1 (1<<1) /* PWREN1 value */ -#define STATUS_EXTON (1<<2) /* EXTON value */ -#define STATUS_CHDET (1<<3) /* Charger detection status */ -#define STATUS_TBAT (1<<4) /* Battery over/under temperature status */ -#define STATUS_VBATMON (1<<5) /* VBATMON comparison status */ -#define STATUS_VBATMONTXON (1<<6) /* VBATMONTXON comparison status */ -#define STATUS_CHIOVER (1<<7) /* Charge overcurrent */ - -#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE 0x1 -#define SYS_CONTROL_A_SHUT_DOWN (1<<1) -#define SYS_CONTROL_A_HWRES_ENABLE (1<<2) -#define SYS_CONTROL_A_WDOG_ACTION (1<<3) -#define SYS_CONTROL_A_WATCHDOG (1<<7) - -#define MISC_CONTROLB_USB_INT_RISING (1<<2) -#define MISC_CONTROLB_SESSION_VALID_EN (1<<3) - -#define USB_PUMP_USBVE (1<<0) -#define USB_PUMP_USBVEP (1<<1) -#define USB_PUMP_SRP_DETECT (1<<2) -#define USB_PUMP_SESSION_VALID (1<<3) -#define USB_PUMP_VBUS_VALID_4_0 (1<<4) -#define USB_PUMP_VBUS_VALID_4_4 (1<<5) -#define USB_PUMP_EN_USBVE (1<<6) -#define USB_PUMP_EN_USBVEP (1<<7) diff --git a/include/dataflash.h b/include/dataflash.h index 769354914f..142b55546f 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -3,7 +3,7 @@ * Data Flash Atmel Description File * Author : Hamid Ikdoumi (Atmel) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* File Name : dataflash.h */ diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 9e74d8729e..cf2aac6ae4 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -39,7 +39,7 @@ typedef struct ddr1_spd_eeprom_s { unsigned char dev_attr; /* 22 SDRAM Device Attributes */ unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ unsigned char clk_access2; /* 24 SDRAM Access from - Clk @ CL=X-0.5 (tAC) */ + Clk @ CL=X-0.5 (tAC) */ unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ @@ -112,9 +112,9 @@ typedef struct ddr2_spd_eeprom_s { unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ unsigned char data_setup; /* 34 Data Input Setup Time - Before Strobe (tDS) */ + Before Strobe (tDS) */ unsigned char data_hold; /* 35 Data Input Hold Time - After Strobe (tDH) */ + After Strobe (tDH) */ unsigned char twr; /* 36 Write Recovery time tWR */ unsigned char twtr; /* 37 Int write to read delay tWTR */ unsigned char trtp; /* 38 Int read to precharge delay tRTP */ @@ -126,42 +126,42 @@ typedef struct ddr2_spd_eeprom_s { unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ unsigned char pll_relock; /* 46 PLL Relock time */ - unsigned char Tcasemax; /* 47 Tcasemax */ - unsigned char psiTAdram; /* 48 Thermal Resistance of DRAM Package from - Top (Case) to Ambient (Psi T-A DRAM) */ + unsigned char t_casemax; /* 47 Tcasemax */ + unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from + Top (Case) to Ambient (Psi T-A DRAM) */ unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient - due to Activate-Precharge/Mode Bits + due to Activate-Precharge/Mode Bits (DT0/Mode Bits) */ unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient - due to Precharge/Quiet Standby + due to Precharge/Quiet Standby (DT2N/DT2Q) */ unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient - due to Precharge Power-Down (DT2P) */ + due to Precharge Power-Down (DT2P) */ unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient - due to Active Standby (DT3N) */ + due to Active Standby (DT3N) */ unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient - due to Active Power-Down with + due to Active Power-Down with Fast PDN Exit (DT3Pfast) */ unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient - due to Active Power-Down with Slow + due to Active Power-Down with Slow PDN Exit (DT3Pslow) */ unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient - due to Page Open Burst Read/DT4R4W + due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) */ unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient - due to Burst Refresh (DT5B) */ + due to Burst Refresh (DT5B) */ unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient - due to Bank Interleave Reads with + due to Bank Interleave Reads with Auto-Precharge (DT7) */ - unsigned char psiTApll; /* 58 Thermal Resistance of PLL Package form - Top (Case) to Ambient (Psi T-A PLL) */ - unsigned char psiTAreg; /* 59 Thermal Reisitance of Register Package - from Top (Case) to Ambient + unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package form + Top (Case) to Ambient (Psi T-A PLL) */ + unsigned char psi_ta_reg; /* 59 Thermal Reisitance of Register Package + from Top (Case) to Ambient (Psi T-A Register) */ unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient - due to PLL Active (DT PLL Active) */ + due to PLL Active (DT PLL Active) */ unsigned char dtregact; /* 61 Register Case Temperature Rise from - Ambient due to Register Active/Mode Bit + Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) */ unsigned char spd_rev; /* 62 SPD Data Revision Code */ unsigned char cksum; /* 63 Checksum for bytes 0-62 */ @@ -191,41 +191,41 @@ typedef struct ddr3_spd_eeprom_s { Dividend / Divisor */ unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ - unsigned char tCK_min; /* 12 SDRAM Minimum Cycle Time */ + unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */ unsigned char res_13; /* 13 Reserved */ unsigned char caslat_lsb; /* 14 CAS Latencies Supported, Least Significant Byte */ unsigned char caslat_msb; /* 15 CAS Latencies Supported, Most Significant Byte */ - unsigned char tAA_min; /* 16 Min CAS Latency Time */ - unsigned char tWR_min; /* 17 Min Write REcovery Time */ - unsigned char tRCD_min; /* 18 Min RAS# to CAS# Delay Time */ - unsigned char tRRD_min; /* 19 Min Row Active to + unsigned char taa_min; /* 16 Min CAS Latency Time */ + unsigned char twr_min; /* 17 Min Write REcovery Time */ + unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */ + unsigned char trrd_min; /* 19 Min Row Active to Row Active Delay Time */ - unsigned char tRP_min; /* 20 Min Row Precharge Delay Time */ - unsigned char tRAS_tRC_ext; /* 21 Upper Nibbles for tRAS and tRC */ - unsigned char tRAS_min_lsb; /* 22 Min Active to Precharge + unsigned char trp_min; /* 20 Min Row Precharge Delay Time */ + unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ + unsigned char tras_min_lsb; /* 22 Min Active to Precharge Delay Time */ - unsigned char tRC_min_lsb; /* 23 Min Active to Active/Refresh + unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh Delay Time, LSB */ - unsigned char tRFC_min_lsb; /* 24 Min Refresh Recovery Delay Time */ - unsigned char tRFC_min_msb; /* 25 Min Refresh Recovery Delay Time */ - unsigned char tWTR_min; /* 26 Min Internal Write to + unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ + unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ + unsigned char twtr_min; /* 26 Min Internal Write to Read Command Delay Time */ - unsigned char tRTP_min; /* 27 Min Internal Read to Precharge + unsigned char trtp_min; /* 27 Min Internal Read to Precharge Command Delay Time */ - unsigned char tFAW_msb; /* 28 Upper Nibble for tFAW */ - unsigned char tFAW_min; /* 29 Min Four Activate Window + unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */ + unsigned char tfaw_min; /* 29 Min Four Activate Window Delay Time*/ unsigned char opt_features; /* 30 SDRAM Optional Features */ unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ unsigned char therm_sensor; /* 32 Module Thermal Sensor */ unsigned char device_type; /* 33 SDRAM device type */ - int8_t fine_tCK_min; /* 34 Fine offset for tCKmin */ - int8_t fine_tAA_min; /* 35 Fine offset for tAAmin */ - int8_t fine_tRCD_min; /* 36 Fine offset for tRCDmin */ - int8_t fine_tRP_min; /* 37 Fine offset for tRPmin */ - int8_t fine_tRC_min; /* 38 Fine offset for tRCmin */ + int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ + int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ + int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ + int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ + int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ /* Module-Specific Section: Bytes 60-116 */ @@ -290,11 +290,220 @@ typedef struct ddr3_spd_eeprom_s { } ddr3_spd_eeprom_t; +/* From JEEC Standard No. 21-C release 23A */ +struct ddr4_spd_eeprom_s { + /* General Section: Bytes 0-127 */ + uint8_t info_size_crc; /* 0 # bytes */ + uint8_t spd_rev; /* 1 Total # bytes of SPD */ + uint8_t mem_type; /* 2 Key Byte / mem type */ + uint8_t module_type; /* 3 Key Byte / Module Type */ + uint8_t density_banks; /* 4 Density and Banks */ + uint8_t addressing; /* 5 Addressing */ + uint8_t package_type; /* 6 Package type */ + uint8_t opt_feature; /* 7 Optional features */ + uint8_t thermal_ref; /* 8 Thermal and refresh */ + uint8_t oth_opt_features; /* 9 Other optional features */ + uint8_t res_10; /* 10 Reserved */ + uint8_t module_vdd; /* 11 Module nominal voltage */ + uint8_t organization; /* 12 Module Organization */ + uint8_t bus_width; /* 13 Module Memory Bus Width */ + uint8_t therm_sensor; /* 14 Module Thermal Sensor */ + uint8_t ext_type; /* 15 Extended module type */ + uint8_t res_16; + uint8_t timebases; /* 17 MTb and FTB */ + uint8_t tck_min; /* 18 tCKAVGmin */ + uint8_t tck_max; /* 19 TCKAVGmax */ + uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */ + uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */ + uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */ + uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */ + uint8_t taa_min; /* 24 Min CAS Latency Time */ + uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */ + uint8_t trp_min; /* 26 Min Row Precharge Delay Time */ + uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ + uint8_t tras_min_lsb; /* 28 tRASmin, lsb */ + uint8_t trc_min_lsb; /* 29 tRCmin, lsb */ + uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ + uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ + uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ + uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ + uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ + uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ + uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */ + uint8_t tfaw_min; /* 37 tFAW, lsb */ + uint8_t trrds_min; /* 38 tRRD_Smin, MTB */ + uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */ + uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */ + uint8_t res_41[60-41]; /* 41 Rserved */ + uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ + uint8_t res_78[117-78]; /* 78~116, Reserved */ + int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ + int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ + int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ + int8_t fine_trc_min; /* 120 Fine offset for tRCmin */ + int8_t fine_trp_min; /* 121 Fine offset for tRPmin */ + int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */ + int8_t fine_taa_min; /* 123 Fine offset for tAAmin */ + int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */ + int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */ + /* CRC: Bytes 126-127 */ + uint8_t crc[2]; /* 126-127 SPD CRC */ + + /* Module-Specific Section: Bytes 128-255 */ + union { + struct { + /* 128 (Unbuffered) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Unbuffered) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Unbuffered) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 (Unbuffered) Address Mapping from + Edge Connector to DRAM */ + uint8_t addr_mapping; + /* 132~253 (Unbuffered) Reserved */ + uint8_t res_132[254-132]; + /* 254~255 CRC */ + uint8_t crc[2]; + } unbuffered; + struct { + /* 128 (Registered) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Registered) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Registered) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 DIMM Module Attributes */ + uint8_t modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + uint8_t thermal; + /* 133 Register Manufacturer ID Code, LSB */ + uint8_t reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + uint8_t reg_id_hi; + /* 135 Register Revision Number */ + uint8_t reg_rev; + /* 136 Address mapping from register to DRAM */ + uint8_t reg_map; + /* 137~253 Reserved */ + uint8_t res_137[254-137]; + /* 254~255 CRC */ + uint8_t crc[2]; + } registered; + struct { + /* 128 (Loadreduced) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Loadreduced) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Loadreduced) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 DIMM Module Attributes */ + uint8_t modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + uint8_t thermal; + /* 133 Register Manufacturer ID Code, LSB */ + uint8_t reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + uint8_t reg_id_hi; + /* 135 Register Revision Number */ + uint8_t reg_rev; + /* 136 Address mapping from register to DRAM */ + uint8_t reg_map; + /* 137 Register Output Drive Strength for CMD/Add*/ + uint8_t reg_drv; + /* 138 Register Output Drive Strength for CK */ + uint8_t reg_drv_ck; + /* 139 Data Buffer Revision Number */ + uint8_t data_buf_rev; + /* 140 DRAM VrefDQ for Package Rank 0 */ + uint8_t vrefqe_r0; + /* 141 DRAM VrefDQ for Package Rank 1 */ + uint8_t vrefqe_r1; + /* 142 DRAM VrefDQ for Package Rank 2 */ + uint8_t vrefqe_r2; + /* 143 DRAM VrefDQ for Package Rank 3 */ + uint8_t vrefqe_r3; + /* 144 Data Buffer VrefDQ for DRAM Interface */ + uint8_t data_intf; + /* + * 145 Data Buffer MDQ Drive Strength and RTT + * for data rate <= 1866 + */ + uint8_t data_drv_1866; + /* + * 146 Data Buffer MDQ Drive Strength and RTT + * for 1866 < data rate <= 2400 + */ + uint8_t data_drv_2400; + /* + * 147 Data Buffer MDQ Drive Strength and RTT + * for 2400 < data rate <= 3200 + */ + uint8_t data_drv_3200; + /* 148 DRAM Drive Strength */ + uint8_t dram_drv; + /* + * 149 DRAM ODT (RTT_WR, RTT_NOM) + * for data rate <= 1866 + */ + uint8_t dram_odt_1866; + /* + * 150 DRAM ODT (RTT_WR, RTT_NOM) + * for 1866 < data rate <= 2400 + */ + uint8_t dram_odt_2400; + /* + * 151 DRAM ODT (RTT_WR, RTT_NOM) + * for 2400 < data rate <= 3200 + */ + uint8_t dram_odt_3200; + /* + * 152 DRAM ODT (RTT_PARK) + * for data rate <= 1866 + */ + uint8_t dram_odt_park_1866; + /* + * 153 DRAM ODT (RTT_PARK) + * for 1866 < data rate <= 2400 + */ + uint8_t dram_odt_park_2400; + /* + * 154 DRAM ODT (RTT_PARK) + * for 2400 < data rate <= 3200 + */ + uint8_t dram_odt_park_3200; + uint8_t res_155[254-155]; /* Reserved */ + /* 254~255 CRC */ + uint8_t crc[2]; + } loadreduced; + uint8_t uc[128]; /* 128-255 Module-Specific Section */ + } mod_section; + + uint8_t res_256[320-256]; /* 256~319 Reserved */ + + /* Module supplier's data: Byte 320~383 */ + uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */ + uint8_t mmid_msb; /* 321 Module MfgID Code MSB */ + uint8_t mloc; /* 322 Mfg Location */ + uint8_t mdate[2]; /* 323~324 Mfg Date */ + uint8_t sernum[4]; /* 325~328 Module Serial Number */ + uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */ + uint8_t mrev; /* 349 Module Revision Code */ + uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */ + uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */ + uint8_t stepping; /* 352 DRAM stepping */ + uint8_t msd[29]; /* 353~381 Mfg's Specific Data */ + uint8_t res_382[2]; /* 382~383 Reserved */ + + uint8_t user[512-384]; /* 384~511 End User Programmable */ +}; + extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); +unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd); /* * Byte 2 Fundamental Memory Types. @@ -310,6 +519,7 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define SPD_MEMTYPE_DDR2_FBDIMM (0x09) #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) #define SPD_MEMTYPE_DDR3 (0x0B) +#define SPD_MEMTYPE_DDR4 (0x0C) /* DIMM Type for DDR2 SPD (according to v1.3) */ #define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) @@ -338,4 +548,18 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) +/* DIMM Type for DDR4 SPD */ +#define DDR4_SPD_MODULETYPE_MASK (0x0f) +#define DDR4_SPD_MODULETYPE_EXT (0x00) +#define DDR4_SPD_MODULETYPE_RDIMM (0x01) +#define DDR4_SPD_MODULETYPE_UDIMM (0x02) +#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR4_SPD_MODULETYPE_LRDIMM (0x04) +#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06) +#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) +#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) +#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C) +#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D) + #endif /* _DDR_SPD_H_ */ diff --git a/include/dfu.h b/include/dfu.h index 1d4006de8b..c27856cb72 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -14,11 +14,15 @@ #include #include #include +#include +#include enum dfu_device_type { DFU_DEV_MMC = 1, DFU_DEV_ONENAND, DFU_DEV_NAND, + DFU_DEV_RAM, + DFU_DEV_SF, }; enum dfu_layout { @@ -27,14 +31,26 @@ enum dfu_layout { DFU_FS_EXT2, DFU_FS_EXT3, DFU_FS_EXT4, + DFU_RAM_ADDR, +}; + +enum dfu_op { + DFU_OP_READ = 1, + DFU_OP_WRITE, + DFU_OP_SIZE, }; struct mmc_internal_data { + int dev_num; + /* RAW programming */ unsigned int lba_start; unsigned int lba_size; unsigned int lba_blk_size; + /* eMMC HW partition access */ + int hw_partition; + /* FAT/EXT */ unsigned int dev; unsigned int part; @@ -47,12 +63,22 @@ struct nand_internal_data { unsigned int dev; unsigned int part; + /* for nand/ubi use */ + unsigned int ubi; }; -static inline unsigned int get_mmc_blk_size(int dev) -{ - return find_mmc_device(dev)->read_bl_len; -} +struct ram_internal_data { + void *start; + unsigned int size; +}; + +struct sf_internal_data { + struct spi_flash *dev; + + /* RAW programming */ + u64 start; + u64 size; +}; #define DFU_NAME_SIZE 32 #define DFU_CMD_BUF_SIZE 128 @@ -60,22 +86,32 @@ static inline unsigned int get_mmc_blk_size(int dev) #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024*1024*8) /* 8 MiB */ #endif #ifndef CONFIG_SYS_DFU_MAX_FILE_SIZE -#define CONFIG_SYS_DFU_MAX_FILE_SIZE (4 << 20) /* 4 MiB */ +#define CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_SYS_DFU_DATA_BUF_SIZE +#endif +#ifndef DFU_DEFAULT_POLL_TIMEOUT +#define DFU_DEFAULT_POLL_TIMEOUT 0 +#endif +#ifndef DFU_MANIFEST_POLL_TIMEOUT +#define DFU_MANIFEST_POLL_TIMEOUT DFU_DEFAULT_POLL_TIMEOUT #endif struct dfu_entity { char name[DFU_NAME_SIZE]; int alt; void *dev_private; - int dev_num; enum dfu_device_type dev_type; enum dfu_layout layout; + unsigned long max_buf_size; union { struct mmc_internal_data mmc; struct nand_internal_data nand; + struct ram_internal_data ram; + struct sf_internal_data sf; } data; + long (*get_medium_size)(struct dfu_entity *dfu); + int (*read_medium)(struct dfu_entity *dfu, u64 offset, void *buf, long *len); @@ -83,6 +119,9 @@ struct dfu_entity { u64 offset, void *buf, long *len); int (*flush_medium)(struct dfu_entity *dfu); + unsigned int (*poll_timeout)(struct dfu_entity *dfu); + + void (*free_entity)(struct dfu_entity *dfu); struct list_head list; @@ -101,7 +140,7 @@ struct dfu_entity { unsigned int inited:1; }; -int dfu_config_entities(char *s, char *interface, int num); +int dfu_config_entities(char *s, char *interface, char *devstr); void dfu_free_entities(void); void dfu_show_entities(void); int dfu_get_alt_number(void); @@ -110,15 +149,22 @@ const char *dfu_get_layout(enum dfu_layout l); struct dfu_entity *dfu_get_entity(int alt); char *dfu_extract_token(char** e, int *n); void dfu_trigger_reset(void); -bool dfu_reset(void); +int dfu_get_alt(char *name); +int dfu_init_env_entities(char *interface, char *devstr); +unsigned char *dfu_get_buf(struct dfu_entity *dfu); +unsigned char *dfu_free_buf(void); +unsigned long dfu_get_buf_size(void); +bool dfu_usb_get_reset(void); int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num); int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num); +int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num); /* Device specific */ #ifdef CONFIG_DFU_MMC -extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s); +extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s); #else -static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) +static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, + char *s) { puts("MMC support not available!\n"); return -1; @@ -126,13 +172,37 @@ static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) #endif #ifdef CONFIG_DFU_NAND -extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s); +extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s); #else -static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) +static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, + char *s) { puts("NAND support not available!\n"); return -1; } #endif +#ifdef CONFIG_DFU_RAM +extern int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s); +#else +static inline int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("RAM support not available!\n"); + return -1; +} +#endif + +#ifdef CONFIG_DFU_SF +extern int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s); +#else +static inline int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("SF support not available!\n"); + return -1; +} +#endif + +int dfu_add(struct usb_configuration *c); #endif /* __DFU_ENTITY_H_ */ diff --git a/include/dm-demo.h b/include/dm-demo.h new file mode 100644 index 0000000000..03722d0c14 --- /dev/null +++ b/include/dm-demo.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DM_DEMO_H +#define __DM_DEMO_H + +#include + +/** + * struct dm_demo_pdata - configuration data for demo instance + * + * @colour: Color of the demo + * @sides: Numbers of sides + * @default_char: Default ASCII character to output (65 = 'A') + */ +struct dm_demo_pdata { + const char *colour; + int sides; + int default_char; +}; + +struct demo_ops { + int (*hello)(struct udevice *dev, int ch); + int (*status)(struct udevice *dev, int *status); + int (*set_light)(struct udevice *dev, int light); + int (*get_light)(struct udevice *dev); +}; + +int demo_hello(struct udevice *dev, int ch); +int demo_status(struct udevice *dev, int *status); +int demo_set_light(struct udevice *dev, int light); +int demo_get_light(struct udevice *dev); +int demo_list(void); + +int demo_parse_dt(struct udevice *dev); + +#endif diff --git a/include/dm.h b/include/dm.h new file mode 100644 index 0000000000..a179c8a6e3 --- /dev/null +++ b/include/dm.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_H_ +#define _DM_H_ + +#include +#include +#include + +#endif diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h new file mode 100644 index 0000000000..f0cc794750 --- /dev/null +++ b/include/dm/device-internal.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_DEVICE_INTERNAL_H +#define _DM_DEVICE_INTERNAL_H + +struct udevice; + +/** + * device_bind() - Create a device and bind it to a driver + * + * Called to set up a new device attached to a driver. The device will either + * have platdata, or a device tree node which can be used to create the + * platdata. + * + * Once bound a device exists but is not yet active until device_probe() is + * called. + * + * @parent: Pointer to device's parent, under which this driver will exist + * @drv: Device's driver + * @name: Name of device (e.g. device tree node name) + * @platdata: Pointer to data for this device - the structure is device- + * specific but may include the device's I/O address, etc.. This is NULL for + * devices which use device tree. + * @of_offset: Offset of device tree node for this device. This is -1 for + * devices which don't use device tree. + * @devp: Returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind(struct udevice *parent, struct driver *drv, + const char *name, void *platdata, int of_offset, + struct udevice **devp); + +/** + * device_bind_by_name: Create a device and bind it to a driver + * + * This is a helper function used to bind devices which do not use device + * tree. + * + * @parent: Pointer to device's parent + * @pre_reloc_only: If true, bind the driver only if its DM_INIT_F flag is set. + * If false bind the driver always. + * @info: Name and platdata for this device + * @devp: Returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, + const struct driver_info *info, struct udevice **devp); + +/** + * device_probe() - Probe a device, activating it + * + * Activate a device so that it is ready for use. All its parents are probed + * first. + * + * @dev: Pointer to device to probe + * @return 0 if OK, -ve on error + */ +int device_probe(struct udevice *dev); + +/** + * device_probe() - Probe a child device, activating it + * + * Activate a device so that it is ready for use. All its parents are probed + * first. The child is provided with parent data if parent_priv is not NULL. + * + * @dev: Pointer to device to probe + * @parent_priv: Pointer to parent data. If non-NULL then this is provided to + * the child. + * @return 0 if OK, -ve on error + */ +int device_probe_child(struct udevice *dev, void *parent_priv); + +/** + * device_remove() - Remove a device, de-activating it + * + * De-activate a device so that it is no longer ready for use. All its + * children are deactivated first. + * + * @dev: Pointer to device to remove + * @return 0 if OK, -ve on error (an error here is normally a very bad thing) + */ +#ifdef CONFIG_DM_DEVICE_REMOVE +int device_remove(struct udevice *dev); +#else +static inline int device_remove(struct udevice *dev) { return 0; } +#endif + +/** + * device_unbind() - Unbind a device, destroying it + * + * Unbind a device and remove all memory used by it + * + * @dev: Pointer to device to unbind + * @return 0 if OK, -ve on error + */ +int device_unbind(struct udevice *dev); + +#ifdef CONFIG_DM_DEVICE_REMOVE +void device_free(struct udevice *dev); +#else +static inline void device_free(struct udevice *dev) {} +#endif + +/* Cast away any volatile pointer */ +#define DM_ROOT_NON_CONST (((gd_t *)gd)->dm_root) +#define DM_UCLASS_ROOT_NON_CONST (((gd_t *)gd)->uclass_root) + +#endif diff --git a/include/dm/device.h b/include/dm/device.h new file mode 100644 index 0000000000..81afa8c628 --- /dev/null +++ b/include/dm/device.h @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_DEVICE_H +#define _DM_DEVICE_H + +#include +#include +#include + +struct driver_info; + +/* Driver is active (probed). Cleared when it is removed */ +#define DM_FLAG_ACTIVATED (1 << 0) + +/* DM is responsible for allocating and freeing platdata */ +#define DM_FLAG_ALLOC_PDATA (1 << 1) + +/* DM should init this device prior to relocation */ +#define DM_FLAG_PRE_RELOC (1 << 2) + +/* DM is responsible for allocating and freeing parent_platdata */ +#define DM_FLAG_ALLOC_PARENT_PDATA (1 << 3) + +/** + * struct udevice - An instance of a driver + * + * This holds information about a device, which is a driver bound to a + * particular port or peripheral (essentially a driver instance). + * + * A device will come into existence through a 'bind' call, either due to + * a U_BOOT_DEVICE() macro (in which case platdata is non-NULL) or a node + * in the device tree (in which case of_offset is >= 0). In the latter case + * we translate the device tree information into platdata in a function + * implemented by the driver ofdata_to_platdata method (called just before the + * probe method if the device has a device tree node. + * + * All three of platdata, priv and uclass_priv can be allocated by the + * driver, or you can use the auto_alloc_size members of struct driver and + * struct uclass_driver to have driver model do this automatically. + * + * @driver: The driver used by this device + * @name: Name of device, typically the FDT node name + * @platdata: Configuration data for this device + * @parent_platdata: The parent bus's configuration data for this device + * @of_offset: Device tree node offset for this device (- for none) + * @of_id: Pointer to the udevice_id structure which created the device + * @parent: Parent of this device, or NULL for the top level device + * @priv: Private data for this device + * @uclass: Pointer to uclass for this device + * @uclass_priv: The uclass's private data for this device + * @parent_priv: The parent's private data for this device + * @uclass_node: Used by uclass to link its devices + * @child_head: List of children of this device + * @sibling_node: Next device in list of all devices + * @flags: Flags for this device DM_FLAG_... + * @req_seq: Requested sequence number for this device (-1 = any) + * @seq: Allocated sequence number for this device (-1 = none). This is set up + * when the device is probed and will be unique within the device's uclass. + */ +struct udevice { + struct driver *driver; + const char *name; + void *platdata; + void *parent_platdata; + int of_offset; + const struct udevice_id *of_id; + struct udevice *parent; + void *priv; + struct uclass *uclass; + void *uclass_priv; + void *parent_priv; + struct list_head uclass_node; + struct list_head child_head; + struct list_head sibling_node; + uint32_t flags; + int req_seq; + int seq; +}; + +/* Maximum sequence number supported */ +#define DM_MAX_SEQ 999 + +/* Returns the operations for a device */ +#define device_get_ops(dev) (dev->driver->ops) + +/* Returns non-zero if the device is active (probed and not removed) */ +#define device_active(dev) ((dev)->flags & DM_FLAG_ACTIVATED) + +/** + * struct udevice_id - Lists the compatible strings supported by a driver + * @compatible: Compatible string + * @data: Data for this compatible string + */ +struct udevice_id { + const char *compatible; + ulong data; +}; + +#ifdef CONFIG_OF_CONTROL +#define of_match_ptr(_ptr) (_ptr) +#else +#define of_match_ptr(_ptr) NULL +#endif /* CONFIG_OF_CONTROL */ + +/** + * struct driver - A driver for a feature or peripheral + * + * This holds methods for setting up a new device, and also removing it. + * The device needs information to set itself up - this is provided either + * by platdata or a device tree node (which we find by looking up + * matching compatible strings with of_match). + * + * Drivers all belong to a uclass, representing a class of devices of the + * same type. Common elements of the drivers can be implemented in the uclass, + * or the uclass can provide a consistent interface to the drivers within + * it. + * + * @name: Device name + * @id: Identiies the uclass we belong to + * @of_match: List of compatible strings to match, and any identifying data + * for each. + * @bind: Called to bind a device to its driver + * @probe: Called to probe a device, i.e. activate it + * @remove: Called to remove a device, i.e. de-activate it + * @unbind: Called to unbind a device from its driver + * @ofdata_to_platdata: Called before probe to decode device tree data + * @child_post_bind: Called after a new child has been bound + * @child_pre_probe: Called before a child device is probed. The device has + * memory allocated but it has not yet been probed. + * @child_post_remove: Called after a child device is removed. The device + * has memory allocated but its device_remove() method has been called. + * @priv_auto_alloc_size: If non-zero this is the size of the private data + * to be allocated in the device's ->priv pointer. If zero, then the driver + * is responsible for allocating any data required. + * @platdata_auto_alloc_size: If non-zero this is the size of the + * platform data to be allocated in the device's ->platdata pointer. + * This is typically only useful for device-tree-aware drivers (those with + * an of_match), since drivers which use platdata will have the data + * provided in the U_BOOT_DEVICE() instantiation. + * @per_child_auto_alloc_size: Each device can hold private data owned by + * its parent. If required this will be automatically allocated if this + * value is non-zero. + * TODO(sjg@chromium.org): I'm considering dropping this, and just having + * device_probe_child() pass it in. So far the use case for allocating it + * is SPI, but I found that unsatisfactory. Since it is here I will leave it + * until things are clearer. + * @per_child_platdata_auto_alloc_size: A bus likes to store information about + * its children. If non-zero this is the size of this data, to be allocated + * in the child's parent_platdata pointer. + * @ops: Driver-specific operations. This is typically a list of function + * pointers defined by the driver, to implement driver functions required by + * the uclass. + * @flags: driver flags - see DM_FLAGS_... + */ +struct driver { + char *name; + enum uclass_id id; + const struct udevice_id *of_match; + int (*bind)(struct udevice *dev); + int (*probe)(struct udevice *dev); + int (*remove)(struct udevice *dev); + int (*unbind)(struct udevice *dev); + int (*ofdata_to_platdata)(struct udevice *dev); + int (*child_post_bind)(struct udevice *dev); + int (*child_pre_probe)(struct udevice *dev); + int (*child_post_remove)(struct udevice *dev); + int priv_auto_alloc_size; + int platdata_auto_alloc_size; + int per_child_auto_alloc_size; + int per_child_platdata_auto_alloc_size; + const void *ops; /* driver-specific operations */ + uint32_t flags; +}; + +/* Declare a new U-Boot driver */ +#define U_BOOT_DRIVER(__name) \ + ll_entry_declare(struct driver, __name, driver) + +/** + * dev_get_platdata() - Get the platform data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return platform data, or NULL if none + */ +void *dev_get_platdata(struct udevice *dev); + +/** + * dev_get_parent_platdata() - Get the parent platform data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return parent's platform data, or NULL if none + */ +void *dev_get_parent_platdata(struct udevice *dev); + +/** + * dev_get_parentdata() - Get the parent data for a device + * + * The parent data is data stored in the device but owned by the parent. + * For example, a USB device may have parent data which contains information + * about how to talk to the device over USB. + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return parent data, or NULL if none + */ +void *dev_get_parentdata(struct udevice *dev); + +/** + * dev_get_priv() - Get the private data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return private data, or NULL if none + */ +void *dev_get_priv(struct udevice *dev); + +/** + * struct dev_get_parent() - Get the parent of a device + * + * @child: Child to check + * @return parent of child, or NULL if this is the root device + */ +struct udevice *dev_get_parent(struct udevice *child); + +/** + * dev_get_of_data() - get the device tree data used to bind a device + * + * When a device is bound using a device tree node, it matches a + * particular compatible string as in struct udevice_id. This function + * returns the associated data value for that compatible string + */ +ulong dev_get_of_data(struct udevice *dev); + +/* + * device_get_uclass_id() - return the uclass ID of a device + * + * @dev: Device to check + * @return uclass ID for the device + */ +enum uclass_id device_get_uclass_id(struct udevice *dev); + +/** + * device_get_child() - Get the child of a device by index + * + * Returns the numbered child, 0 being the first. This does not use + * sequence numbers, only the natural order. + * + * @dev: Parent device to check + * @index: Child index + * @devp: Returns pointer to device + */ +int device_get_child(struct udevice *parent, int index, struct udevice **devp); + +/** + * device_find_child_by_seq() - Find a child device based on a sequence + * + * This searches for a device with the given seq or req_seq. + * + * For seq, if an active device has this sequence it will be returned. + * If there is no such device then this will return -ENODEV. + * + * For req_seq, if a device (whether activated or not) has this req_seq + * value, that device will be returned. This is a strong indication that + * the device will receive that sequence when activated. + * + * @parent: Parent device + * @seq_or_req_seq: Sequence number to find (0=first) + * @find_req_seq: true to find req_seq, false to find seq + * @devp: Returns pointer to device (there is only one per for each seq). + * Set to NULL if none is found + * @return 0 if OK, -ve on error + */ +int device_find_child_by_seq(struct udevice *parent, int seq_or_req_seq, + bool find_req_seq, struct udevice **devp); + +/** + * device_get_child_by_seq() - Get a child device based on a sequence + * + * If an active device has this sequence it will be returned. If there is no + * such device then this will check for a device that is requesting this + * sequence. + * + * The device is probed to activate it ready for use. + * + * @parent: Parent device + * @seq: Sequence number to find (0=first) + * @devp: Returns pointer to device (there is only one per for each seq) + * Set to NULL if none is found + * @return 0 if OK, -ve on error + */ +int device_get_child_by_seq(struct udevice *parent, int seq, + struct udevice **devp); + +/** + * device_find_child_by_of_offset() - Find a child device based on FDT offset + * + * Locates a child device by its device tree offset. + * + * @parent: Parent device + * @of_offset: Device tree offset to find + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * @return 0 if OK, -ve on error + */ +int device_find_child_by_of_offset(struct udevice *parent, int of_offset, + struct udevice **devp); + +/** + * device_get_child_by_of_offset() - Get a child device based on FDT offset + * + * Locates a child device by its device tree offset. + * + * The device is probed to activate it ready for use. + * + * @parent: Parent device + * @of_offset: Device tree offset to find + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * @return 0 if OK, -ve on error + */ +int device_get_child_by_of_offset(struct udevice *parent, int seq, + struct udevice **devp); + +/** + * device_find_first_child() - Find the first child of a device + * + * @parent: Parent device to search + * @devp: Returns first child device, or NULL if none + * @return 0 + */ +int device_find_first_child(struct udevice *parent, struct udevice **devp); + +/** + * device_find_first_child() - Find the first child of a device + * + * @devp: Pointer to previous child device on entry. Returns pointer to next + * child device, or NULL if none + * @return 0 + */ +int device_find_next_child(struct udevice **devp); + +#endif diff --git a/include/dm/lists.h b/include/dm/lists.h new file mode 100644 index 0000000000..1b50af9f23 --- /dev/null +++ b/include/dm/lists.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_LISTS_H_ +#define _DM_LISTS_H_ + +#include + +/** + * lists_driver_lookup_name() - Return u_boot_driver corresponding to name + * + * This function returns a pointer to a driver given its name. This is used + * for binding a driver given its name and platdata. + * + * @name: Name of driver to look up + * @return pointer to driver, or NULL if not found + */ +struct driver *lists_driver_lookup_name(const char *name); + +/** + * lists_uclass_lookup() - Return uclass_driver based on ID of the class + * id: ID of the class + * + * This function returns the pointer to uclass_driver, which is the class's + * base structure based on the ID of the class. Returns NULL on error. + */ +struct uclass_driver *lists_uclass_lookup(enum uclass_id id); + +/** + * lists_bind_drivers() - search for and bind all drivers to parent + * + * This searches the U_BOOT_DEVICE() structures and creates new devices for + * each one. The devices will have @parent as their parent. + * + * @parent: parent device (root) + * @early_only: If true, bind only drivers with the DM_INIT_F flag. If false + * bind all drivers. + */ +int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only); + +/** + * lists_bind_fdt() - bind a device tree node + * + * This creates a new device bound to the given device tree node, with + * @parent as its parent. + * + * @parent: parent device (root) + * @blob: device tree blob + * @offset: offset of this device tree node + * @devp: if non-NULL, returns a pointer to the bound device + * @return 0 if device was bound, -EINVAL if the device tree is invalid, + * other -ve value on error + */ +int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, + struct udevice **devp); + +/** + * device_bind_driver() - bind a device to a driver + * + * This binds a new device to a driver. + * + * @parent: Parent device + * @drv_name: Name of driver to attach to this parent + * @dev_name: Name of the new device thus created + * @devp: Returns the newly bound device + */ +int device_bind_driver(struct udevice *parent, const char *drv_name, + const char *dev_name, struct udevice **devp); + +#endif diff --git a/include/dm/platdata.h b/include/dm/platdata.h new file mode 100644 index 0000000000..fbc8a6b3ad --- /dev/null +++ b/include/dm/platdata.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_PLATDATA_H +#define _DM_PLATDATA_H + +#include + +/** + * struct driver_info - Information required to instantiate a device + * + * @name: Driver name + * @platdata: Driver-specific platform data + */ +struct driver_info { + const char *name; + const void *platdata; +}; + +#define U_BOOT_DEVICE(__name) \ + ll_entry_declare(struct driver_info, __name, driver_info) + +/* Declare a list of devices. The argument is a driver_info[] array */ +#define U_BOOT_DEVICES(__name) \ + ll_entry_declare_list(struct driver_info, __name, driver_info) + +#endif diff --git a/include/dm/platform_data/serial-uniphier.h b/include/dm/platform_data/serial-uniphier.h new file mode 100644 index 0000000000..52343e34ee --- /dev/null +++ b/include/dm/platform_data/serial-uniphier.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLAT_UNIPHIER_SERIAL_H +#define __PLAT_UNIPHIER_SERIAL_H + +#define DRIVER_NAME "uniphier-uart" + +struct uniphier_serial_platform_data { + unsigned long base; + unsigned int uartclk; +}; + +#endif /* __PLAT_UNIPHIER_SERIAL_H */ diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h new file mode 100644 index 0000000000..7d3ace2f9e --- /dev/null +++ b/include/dm/platform_data/serial_mxc.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2014 Google, Inc + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __serial_mxc_h +#define __serial_mxc_h + +/* Information about a serial port */ +struct mxc_serial_platdata { + struct mxc_uart *reg; /* address of registers in physical memory */ +}; + +#endif diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h new file mode 100644 index 0000000000..5e068f390b --- /dev/null +++ b/include/dm/platform_data/serial_pl01x.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2014 Google, Inc + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __serial_pl01x_h +#define __serial_pl01x_h + +enum pl01x_type { + TYPE_PL010, + TYPE_PL011, +}; + +/* + *Information about a serial port + * + * @base: Register base address + * @type: Port type + * @clock: Input clock rate, used for calculating the baud rate divisor + */ +struct pl01x_serial_platdata { + unsigned long base; + enum pl01x_type type; + unsigned int clock; +}; + +#endif diff --git a/include/dm/root.h b/include/dm/root.h new file mode 100644 index 0000000000..c7f0c1d5ca --- /dev/null +++ b/include/dm/root.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_ROOT_H_ +#define _DM_ROOT_H_ + +struct udevice; + +/** + * dm_root() - Return pointer to the top of the driver tree + * + * This function returns pointer to the root node of the driver tree, + * + * @return pointer to root device, or NULL if not inited yet + */ +struct udevice *dm_root(void); + +/** + * dm_scan_platdata() - Scan all platform data and bind drivers + * + * This scans all available platdata and creates drivers for each + * + * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC + * flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_scan_platdata(bool pre_reloc_only); + +/** + * dm_scan_fdt() - Scan the device tree and bind drivers + * + * This scans the device tree and creates a driver for each node. Only + * the top-level subnodes are examined. + * + * @blob: Pointer to device tree blob + * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC + * flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_scan_fdt(const void *blob, bool pre_reloc_only); + +/** + * dm_scan_fdt_node() - Scan the device tree and bind drivers for a node + * + * This scans the subnodes of a device tree node and and creates a driver + * for each one. + * + * @parent: Parent device for the devices that will be created + * @blob: Pointer to device tree blob + * @offset: Offset of node to scan + * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC + * flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset, + bool pre_reloc_only); + +/** + * dm_scan_other() - Scan for other devices + * + * Some devices may not be visible to Driver Model. This weak function can + * be provided by boards which wish to create their own devices + * programmaticaly. They should do this by calling device_bind() on each + * device. + * + * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC + * flag. If false bind all drivers. + */ +int dm_scan_other(bool pre_reloc_only); + +/** + * dm_init_and_scan() - Initialise Driver Model structures and scan for devices + * + * This function initialises the roots of the driver tree and uclass trees, + * then scans and binds available devices from platform data and the FDT. + * This calls dm_init() to set up Driver Model structures. + * + * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC + * flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_init_and_scan(bool pre_reloc_only); + +/** + * dm_init() - Initialise Driver Model structures + * + * This function will initialize roots of driver tree and class tree. + * This needs to be called before anything uses the DM + * + * @return 0 if OK, -ve on error + */ +int dm_init(void); + +/** + * dm_uninit - Uninitialise Driver Model structures + * + * All devices will be removed and unbound + * @return 0 if OK, -ve on error + */ +int dm_uninit(void); + +#endif diff --git a/include/dm/test.h b/include/dm/test.h new file mode 100644 index 0000000000..707c69e07f --- /dev/null +++ b/include/dm/test.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2013 Google, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DM_TEST_H +#define __DM_TEST_H + +#include +#include + +/** + * struct dm_test_cdata - configuration data for test instance + * + * @ping_add: Amonut to add each time we get a ping + * @base: Base address of this device + */ +struct dm_test_pdata { + int ping_add; + uint32_t base; +}; + +/** + * struct test_ops - Operations supported by the test device + * + * @ping: Ping operation + * @dev: Device to operate on + * @pingval: Value to ping the device with + * @pingret: Returns resulting value from driver + * @return 0 if OK, -ve on error + */ +struct test_ops { + int (*ping)(struct udevice *dev, int pingval, int *pingret); +}; + +/* Operations that our test driver supports */ +enum { + DM_TEST_OP_BIND = 0, + DM_TEST_OP_UNBIND, + DM_TEST_OP_PROBE, + DM_TEST_OP_REMOVE, + + /* For uclass */ + DM_TEST_OP_POST_BIND, + DM_TEST_OP_PRE_UNBIND, + DM_TEST_OP_POST_PROBE, + DM_TEST_OP_PRE_REMOVE, + DM_TEST_OP_INIT, + DM_TEST_OP_DESTROY, + + DM_TEST_OP_COUNT, +}; + +/* Test driver types */ +enum { + DM_TEST_TYPE_FIRST = 0, + DM_TEST_TYPE_SECOND, +}; + +/* The number added to the ping total on each probe */ +#define DM_TEST_START_TOTAL 5 + +/** + * struct dm_test_priv - private data for the test devices + */ +struct dm_test_priv { + int ping_total; + int op_count[DM_TEST_OP_COUNT]; + int uclass_flag; + int uclass_total; +}; + +/** + * struct dm_test_perdev_class_priv - private per-device data for test uclass + */ +struct dm_test_uclass_perdev_priv { + int base_add; +}; + +/** + * struct dm_test_uclass_priv - private data for test uclass + */ +struct dm_test_uclass_priv { + int total_add; +}; + +/** + * struct dm_test_parent_data - parent's information on each child + * + * @sum: Test value used to check parent data works correctly + * @flag: Used to track calling of parent operations + * @uclass_flag: Used to track calling of parent operations by uclass + */ +struct dm_test_parent_data { + int sum; + int flag; +}; + +/* + * Operation counts for the test driver, used to check that each method is + * called correctly + */ +extern int dm_testdrv_op_count[DM_TEST_OP_COUNT]; + +extern struct dm_test_state global_test_state; + +/* + * struct dm_test_state - Entire state of dm test system + * + * This is often abreviated to dms. + * + * @root: Root device + * @testdev: Test device + * @fail_count: Number of tests that failed + * @force_fail_alloc: Force all memory allocs to fail + * @skip_post_probe: Skip uclass post-probe processing + * @removed: Used to keep track of a device that was removed + */ +struct dm_test_state { + struct udevice *root; + struct udevice *testdev; + int fail_count; + int force_fail_alloc; + int skip_post_probe; + struct udevice *removed; + struct mallinfo start; +}; + +/* Test flags for each test */ +enum { + DM_TESTF_SCAN_PDATA = 1 << 0, /* test needs platform data */ + DM_TESTF_PROBE_TEST = 1 << 1, /* probe test uclass */ + DM_TESTF_SCAN_FDT = 1 << 2, /* scan device tree */ +}; + +/** + * struct dm_test - Information about a driver model test + * + * @name: Name of test + * @func: Function to call to perform test + * @flags: Flags indicated pre-conditions for test + */ +struct dm_test { + const char *name; + int (*func)(struct dm_test_state *dms); + int flags; +}; + +/* Declare a new driver model test */ +#define DM_TEST(_name, _flags) \ + ll_entry_declare(struct dm_test, _name, dm_test) = { \ + .name = #_name, \ + .flags = _flags, \ + .func = _name, \ + } + +/* Declare ping methods for the drivers */ +int test_ping(struct udevice *dev, int pingval, int *pingret); +int testfdt_ping(struct udevice *dev, int pingval, int *pingret); + +/** + * dm_check_operations() - Check that we can perform ping operations + * + * This checks that the ping operations work as expected for a device + * + * @dms: Overall test state + * @dev: Device to test + * @base: Base address, used to check ping return value + * @priv: Pointer to private test information + * @return 0 if OK, -ve on error + */ +int dm_check_operations(struct dm_test_state *dms, struct udevice *dev, + uint32_t base, struct dm_test_priv *priv); + +/** + * dm_check_devices() - check the devices respond to operations correctly + * + * @dms: Overall test state + * @num_devices: Number of test devices to check + * @return 0 if OK, -ve on error + */ +int dm_check_devices(struct dm_test_state *dms, int num_devices); + +/** + * dm_leak_check_start() - Prepare to check for a memory leak + * + * Call this before allocating memory to record the amount of memory being + * used. + * + * @dms: Overall test state + */ +void dm_leak_check_start(struct dm_test_state *dms); + +/** + * dm_leak_check_end() - Check that no memory has leaked + * + * Call this after dm_leak_check_start() and after you have hopefuilly freed + * all the memory that was allocated. This function will print an error if + * it sees a different amount of total memory allocated than before. + * + * @dms: Overall test state + */int dm_leak_check_end(struct dm_test_state *dms); + + +/** + * dm_test_main() - Run all the tests + * + * This runs all available driver model tests + * + * @return 0 if OK, -ve on error + */ +int dm_test_main(void); + +#endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h new file mode 100644 index 0000000000..91bb90dcfb --- /dev/null +++ b/include/dm/uclass-id.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_UCLASS_ID_H +#define _DM_UCLASS_ID_H + +/* TODO(sjg@chromium.org): this could be compile-time generated */ +enum uclass_id { + /* These are used internally by driver model */ + UCLASS_ROOT = 0, + UCLASS_DEMO, + UCLASS_TEST, + UCLASS_TEST_FDT, + UCLASS_TEST_BUS, + UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ + UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ + UCLASS_SIMPLE_BUS, + + /* U-Boot uclasses start here */ + UCLASS_GPIO, /* Bank of general-purpose I/O pins */ + UCLASS_SERIAL, /* Serial UART */ + UCLASS_SPI, /* SPI bus */ + UCLASS_SPI_GENERIC, /* Generic SPI flash target */ + UCLASS_SPI_FLASH, /* SPI flash */ + UCLASS_CROS_EC, /* Chrome OS EC */ + UCLASS_THERMAL, /* Thermal sensor */ + UCLASS_I2C, /* I2C bus */ + UCLASS_I2C_GENERIC, /* Generic I2C device */ + UCLASS_I2C_EEPROM, /* I2C EEPROM device */ + UCLASS_MOD_EXP, /* RSA Mod Exp device */ + + UCLASS_COUNT, + UCLASS_INVALID = -1, +}; + +#endif diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h new file mode 100644 index 0000000000..f2f254a825 --- /dev/null +++ b/include/dm/uclass-internal.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_UCLASS_INTERNAL_H +#define _DM_UCLASS_INTERNAL_H + +/** + * uclass_find_device() - Return n-th child of uclass + * @id: Id number of the uclass + * @index: Position of the child in uclass's list + * #devp: Returns pointer to device, or NULL on error + * + * The device is not prepared for use - this is an internal function + * + * @return the uclass pointer of a child at the given index or + * return NULL on error. + */ +int uclass_find_device(enum uclass_id id, int index, struct udevice **devp); + +/** + * uclass_bind_device() - Associate device with a uclass + * + * Connect the device into uclass's list of devices. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_bind_device(struct udevice *dev); + +/** + * uclass_unbind_device() - Deassociate device with a uclass + * + * Disconnect the device from uclass's list of devices. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_unbind_device(struct udevice *dev); + +/** + * uclass_pre_probe_child() - Deal with a child that is about to be probed + * + * Perform any pre-processing that is needed by the uclass before it can be + * probed. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_pre_probe_child(struct udevice *dev); + +/** + * uclass_post_probe_device() - Deal with a device that has just been probed + * + * Perform any post-processing of a probed device that is needed by the + * uclass. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_post_probe_device(struct udevice *dev); + +/** + * uclass_pre_remove_device() - Handle a device which is about to be removed + * + * Perform any pre-processing of a device that is about to be removed. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_pre_remove_device(struct udevice *dev); + +/** + * uclass_find() - Find uclass by its id + * + * @id: Id to serach for + * @return pointer to uclass, or NULL if not found + */ +struct uclass *uclass_find(enum uclass_id key); + +/** + * uclass_destroy() - Destroy a uclass + * + * Destroy a uclass and all its devices + * + * @uc: uclass to destroy + * @return 0 on success, -ve on error + */ +int uclass_destroy(struct uclass *uc); + +/** + * uclass_find_device_by_seq() - Find uclass device based on ID and sequence + * + * This searches for a device with the given seq or req_seq. + * + * For seq, if an active device has this sequence it will be returned. + * If there is no such device then this will return -ENODEV. + * + * For req_seq, if a device (whether activated or not) has this req_seq + * value, that device will be returned. This is a strong indication that + * the device will receive that sequence when activated. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @seq_or_req_seq: Sequence number to find (0=first) + * @find_req_seq: true to find req_seq, false to find seq + * @devp: Returns pointer to device (there is only one per for each seq) + * @return 0 if OK, -ve on error + */ +int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq, + bool find_req_seq, struct udevice **devp); + +#endif diff --git a/include/dm/uclass.h b/include/dm/uclass.h new file mode 100644 index 0000000000..d6c40c60dd --- /dev/null +++ b/include/dm/uclass.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_UCLASS_H +#define _DM_UCLASS_H + +#include +#include +#include + +/** + * struct uclass - a U-Boot drive class, collecting together similar drivers + * + * A uclass provides an interface to a particular function, which is + * implemented by one or more drivers. Every driver belongs to a uclass even + * if it is the only driver in that uclass. An example uclass is GPIO, which + * provides the ability to change read inputs, set and clear outputs, etc. + * There may be drivers for on-chip SoC GPIO banks, I2C GPIO expanders and + * PMIC IO lines, all made available in a unified way through the uclass. + * + * @priv: Private data for this uclass + * @uc_drv: The driver for the uclass itself, not to be confused with a + * 'struct driver' + * @dev_head: List of devices in this uclass (devices are attached to their + * uclass when their bind method is called) + * @sibling_node: Next uclass in the linked list of uclasses + */ +struct uclass { + void *priv; + struct uclass_driver *uc_drv; + struct list_head dev_head; + struct list_head sibling_node; +}; + +struct udevice; + +/* Members of this uclass sequence themselves with aliases */ +#define DM_UC_FLAG_SEQ_ALIAS (1 << 0) + +/** + * struct uclass_driver - Driver for the uclass + * + * A uclass_driver provides a consistent interface to a set of related + * drivers. + * + * @name: Name of uclass driver + * @id: ID number of this uclass + * @post_bind: Called after a new device is bound to this uclass + * @pre_unbind: Called before a device is unbound from this uclass + * @post_probe: Called after a new device is probed + * @pre_remove: Called before a device is removed + * @child_post_bind: Called after a child is bound to a device in this uclass + * @init: Called to set up the uclass + * @destroy: Called to destroy the uclass + * @priv_auto_alloc_size: If non-zero this is the size of the private data + * to be allocated in the uclass's ->priv pointer. If zero, then the uclass + * driver is responsible for allocating any data required. + * @per_device_auto_alloc_size: Each device can hold private data owned + * by the uclass. If required this will be automatically allocated if this + * value is non-zero. + * @per_child_auto_alloc_size: Each child device (of a parent in this + * uclass) can hold parent data for the device/uclass. This value is only + * used as a falback if this member is 0 in the driver. + * @per_child_platdata_auto_alloc_size: A bus likes to store information about + * its children. If non-zero this is the size of this data, to be allocated + * in the child device's parent_platdata pointer. This value is only used as + * a falback if this member is 0 in the driver. + * @ops: Uclass operations, providing the consistent interface to devices + * within the uclass. + * @flags: Flags for this uclass (DM_UC_...) + */ +struct uclass_driver { + const char *name; + enum uclass_id id; + int (*post_bind)(struct udevice *dev); + int (*pre_unbind)(struct udevice *dev); + int (*post_probe)(struct udevice *dev); + int (*pre_remove)(struct udevice *dev); + int (*child_post_bind)(struct udevice *dev); + int (*child_pre_probe)(struct udevice *dev); + int (*init)(struct uclass *class); + int (*destroy)(struct uclass *class); + int priv_auto_alloc_size; + int per_device_auto_alloc_size; + int per_child_auto_alloc_size; + int per_child_platdata_auto_alloc_size; + const void *ops; + uint32_t flags; +}; + +/* Declare a new uclass_driver */ +#define UCLASS_DRIVER(__name) \ + ll_entry_declare(struct uclass_driver, __name, uclass) + +/** + * uclass_get() - Get a uclass based on an ID, creating it if needed + * + * Every uclass is identified by an ID, a number from 0 to n-1 where n is + * the number of uclasses. This function allows looking up a uclass by its + * ID. + * + * @key: ID to look up + * @ucp: Returns pointer to uclass (there is only one per ID) + * @return 0 if OK, -ve on error + */ +int uclass_get(enum uclass_id key, struct uclass **ucp); + +/** + * uclass_get_device() - Get a uclass device based on an ID and index + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @index: Device number within that uclass (0=first) + * @devp: Returns pointer to device (there is only one per for each ID) + * @return 0 if OK, -ve on error + */ +int uclass_get_device(enum uclass_id id, int index, struct udevice **devp); + +/** + * uclass_get_device_by_seq() - Get a uclass device based on an ID and sequence + * + * If an active device has this sequence it will be returned. If there is no + * such device then this will check for a device that is requesting this + * sequence. + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @seq: Sequence number to find (0=first) + * @devp: Returns pointer to device (there is only one for each seq) + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp); + +/** + * uclass_get_device_by_of_offset() - Get a uclass device by device tree node + * + * This searches the devices in the uclass for one attached to the given + * device tree node. + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @node: Device tree offset to search for (if -ve then -ENODEV is returned) + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_of_offset(enum uclass_id id, int node, + struct udevice **devp); + +/** + * uclass_first_device() - Get the first device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * @id: Uclass ID to look up + * @devp: Returns pointer to the first device in that uclass, or NULL if none + * @return 0 if OK (found or not found), -1 on error + */ +int uclass_first_device(enum uclass_id id, struct udevice **devp); + +/** + * uclass_next_device() - Get the next device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next device in the same uclass, or NULL if none + * @return 0 if OK (found or not found), -1 on error + */ +int uclass_next_device(struct udevice **devp); + +/** + * uclass_resolve_seq() - Resolve a device's sequence number + * + * On entry dev->seq is -1, and dev->req_seq may be -1 (to allocate a + * sequence number automatically, or >= 0 to select a particular number. + * If the requested sequence number is in use, then this device will + * be allocated another one. + * + * Note that the device's seq value is not changed by this function. + * + * @dev: Device for which to allocate sequence number + * @return sequence number allocated, or -ve on error + */ +int uclass_resolve_seq(struct udevice *dev); + +/** + * uclass_foreach_dev() - Helper function to iteration through devices + * + * This creates a for() loop which works through the available devices in + * a uclass in order from start to end. + * + * @pos: struct udevice * to hold the current device. Set to NULL when there + * are no more devices. + * @uc: uclass to scan + */ +#define uclass_foreach_dev(pos, uc) \ + for (pos = list_entry((&(uc)->dev_head)->next, typeof(*pos), \ + uclass_node); \ + prefetch(pos->uclass_node.next), \ + &pos->uclass_node != (&(uc)->dev_head); \ + pos = list_entry(pos->uclass_node.next, typeof(*pos), \ + uclass_node)) + +#endif diff --git a/include/dm/ut.h b/include/dm/ut.h new file mode 100644 index 0000000000..ec6146545b --- /dev/null +++ b/include/dm/ut.h @@ -0,0 +1,107 @@ +/* + * Simple unit test library for driver model + * + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DM_UT_H +#define __DM_UT_H + +struct dm_test_state; + +/** + * ut_fail() - Record failure of a unit test + * + * @dms: Test state + * @fname: Filename where the error occured + * @line: Line number where the error occured + * @func: Function name where the error occured + * @cond: The condition that failed + */ +void ut_fail(struct dm_test_state *dms, const char *fname, int line, + const char *func, const char *cond); + +/** + * ut_failf() - Record failure of a unit test + * + * @dms: Test state + * @fname: Filename where the error occured + * @line: Line number where the error occured + * @func: Function name where the error occured + * @cond: The condition that failed + * @fmt: printf() format string for the error, followed by args + */ +void ut_failf(struct dm_test_state *dms, const char *fname, int line, + const char *func, const char *cond, const char *fmt, ...) + __attribute__ ((format (__printf__, 6, 7))); + + +/* Assert that a condition is non-zero */ +#define ut_assert(cond) \ + if (!(cond)) { \ + ut_fail(dms, __FILE__, __LINE__, __func__, #cond); \ + return -1; \ + } + +/* Assert that a condition is non-zero, with printf() string */ +#define ut_assertf(cond, fmt, args...) \ + if (!(cond)) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, #cond, \ + fmt, ##args); \ + return -1; \ + } + +/* Assert that two int expressions are equal */ +#define ut_asserteq(expr1, expr2) { \ + unsigned int val1 = (expr1), val2 = (expr2); \ + \ + if (val1 != val2) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, \ + #expr1 " == " #expr2, \ + "Expected %d, got %d", val1, val2); \ + return -1; \ + } \ +} + +/* Assert that two string expressions are equal */ +#define ut_asserteq_str(expr1, expr2) { \ + const char *val1 = (expr1), *val2 = (expr2); \ + \ + if (strcmp(val1, val2)) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, \ + #expr1 " = " #expr2, \ + "Expected \"%s\", got \"%s\"", val1, val2); \ + return -1; \ + } \ +} + +/* Assert that two pointers are equal */ +#define ut_asserteq_ptr(expr1, expr2) { \ + const void *val1 = (expr1), *val2 = (expr2); \ + \ + if (val1 != val2) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, \ + #expr1 " = " #expr2, \ + "Expected %p, got %p", val1, val2); \ + return -1; \ + } \ +} + +/* Assert that a pointer is not NULL */ +#define ut_assertnonnull(expr) { \ + const void *val = (expr); \ + \ + if (val == NULL) { \ + ut_failf(dms, __FILE__, __LINE__, __func__, \ + #expr " = NULL", \ + "Expected non-null, got NULL"); \ + return -1; \ + } \ +} + +/* Assert that an operation succeeds (returns 0) */ +#define ut_assertok(cond) ut_asserteq(0, cond) + +#endif diff --git a/include/dm/util.h b/include/dm/util.h new file mode 100644 index 0000000000..0cec17b52a --- /dev/null +++ b/include/dm/util.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DM_UTIL_H +#define __DM_UTIL_H + +#ifdef CONFIG_DM_WARN +void dm_warn(const char *fmt, ...); +#else +static inline void dm_warn(const char *fmt, ...) +{ +} +#endif + +#ifdef DEBUG +void dm_dbg(const char *fmt, ...); +#else +static inline void dm_dbg(const char *fmt, ...) +{ +} +#endif + +struct list_head; + +/** + * list_count_items() - Count number of items in a list + * + * @param head: Head of list + * @return number of items, or 0 if empty + */ +int list_count_items(struct list_head *head); + +#endif diff --git a/include/dm9161.h b/include/dm9161.h deleted file mode 100644 index bd85e4287e..0000000000 --- a/include/dm9161.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * NOTE: DAVICOM ethernet Physical layer - * - * Version: @(#)DM9161.h 1.0.0 01/10/2001 - * - * Authors: ATMEL Rousset - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */ - -#define DM9161_BMCR 0 /* Basic Mode Control Register */ -#define DM9161_BMSR 1 /* Basic Mode Status Register */ -#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */ -#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */ -#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */ -#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */ -#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */ -#define DM9161_DSCR 16 /* Specified Configuration Register */ -#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */ -#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */ -#define DM9161_MDINTR 21 /* Specified Interrupt Register */ -#define DM9161_RECR 22 /* Specified Receive Error Counter Register */ -#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */ -#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */ - - -/* --Bit definitions: DM9161_BMCR */ -#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ -#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */ -#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */ -#define DM9161_AUTONEG (1 << 12) -#define DM9161_POWER_DOWN (1 << 11) -#define DM9161_ISOLATE (1 << 10) -#define DM9161_RESTART_AUTONEG (1 << 9) -#define DM9161_DUPLEX_MODE (1 << 8) -#define DM9161_COLLISION_TEST (1 << 7) - -/*--Bit definitions: DM9161_BMSR */ -#define DM9161_100BASE_TX (1 << 15) -#define DM9161_100BASE_TX_FD (1 << 14) -#define DM9161_100BASE_TX_HD (1 << 13) -#define DM9161_10BASE_T_FD (1 << 12) -#define DM9161_10BASE_T_HD (1 << 11) -#define DM9161_MF_PREAMB_SUPPR (1 << 6) -#define DM9161_AUTONEG_COMP (1 << 5) -#define DM9161_REMOTE_FAULT (1 << 4) -#define DM9161_AUTONEG_ABILITY (1 << 3) -#define DM9161_LINK_STATUS (1 << 2) -#define DM9161_JABBER_DETECT (1 << 1) -#define DM9161_EXTEND_CAPAB (1 << 0) - -/*--definitions: DM9161_PHYID1 */ -#define DM9161_PHYID1_OUI 0x606E -#define DM9161_LSB_MASK 0x3F - -/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */ -#define DM9161_NP (1 << 15) -#define DM9161_ACK (1 << 14) -#define DM9161_RF (1 << 13) -#define DM9161_FCS (1 << 10) -#define DM9161_T4 (1 << 9) -#define DM9161_TX_FDX (1 << 8) -#define DM9161_TX_HDX (1 << 7) -#define DM9161_10_FDX (1 << 6) -#define DM9161_10_HDX (1 << 5) -#define DM9161_AN_IEEE_802_3 0x0001 - -/*--Bit definitions: DM9161_ANER */ -#define DM9161_PDF (1 << 4) -#define DM9161_LP_NP_ABLE (1 << 3) -#define DM9161_NP_ABLE (1 << 2) -#define DM9161_PAGE_RX (1 << 1) -#define DM9161_LP_AN_ABLE (1 << 0) - -/*--Bit definitions: DM9161_DSCR */ -#define DM9161_BP4B5B (1 << 15) -#define DM9161_BP_SCR (1 << 14) -#define DM9161_BP_ALIGN (1 << 13) -#define DM9161_BP_ADPOK (1 << 12) -#define DM9161_REPEATER (1 << 11) -#define DM9161_TX (1 << 10) -#define DM9161_RMII_ENABLE (1 << 8) -#define DM9161_F_LINK_100 (1 << 7) -#define DM9161_SPLED_CTL (1 << 6) -#define DM9161_COLLED_CTL (1 << 5) -#define DM9161_RPDCTR_EN (1 << 4) -#define DM9161_SM_RST (1 << 3) -#define DM9161_MFP SC (1 << 2) -#define DM9161_SLEEP (1 << 1) -#define DM9161_RLOUT (1 << 0) - -/*--Bit definitions: DM9161_DSCSR */ -#define DM9161_100FDX (1 << 15) -#define DM9161_100HDX (1 << 14) -#define DM9161_10FDX (1 << 13) -#define DM9161_10HDX (1 << 12) - -/*--Bit definitions: DM9161_10BTCSR */ -#define DM9161_LP_EN (1 << 14) -#define DM9161_HBE (1 << 13) -#define DM9161_SQUELCH (1 << 12) -#define DM9161_JABEN (1 << 11) -#define DM9161_10BT_SER (1 << 10) -#define DM9161_POLR (1 << 0) - - -/*--Bit definitions: DM9161_MDINTR */ -#define DM9161_INTR_PEND (1 << 15) -#define DM9161_FDX_MASK (1 << 11) -#define DM9161_SPD_MASK (1 << 10) -#define DM9161_LINK_MASK (1 << 9) -#define DM9161_INTR_MASK (1 << 8) -#define DM9161_FDX_CHANGE (1 << 4) -#define DM9161_SPD_CHANGE (1 << 3) -#define DM9161_LINK_CHANGE (1 << 2) -#define DM9161_INTR_STATUS (1 << 0) - - -/****************** function prototypes **********************/ -unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac); -unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac); -unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status); -unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac); diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h new file mode 100644 index 0000000000..6d0d8d8ef3 --- /dev/null +++ b/include/dt-bindings/clock/tegra114-car.h @@ -0,0 +1,342 @@ +/* + * This header provides constants for binding nvidia,tegra114-car. + * + * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 160 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 160 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H + +/* 0 */ +/* 1 */ +/* 2 */ +/* 3 */ +#define TEGRA114_CLK_RTC 4 +#define TEGRA114_CLK_TIMER 5 +#define TEGRA114_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA114_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA114_CLK_I2S1 11 +#define TEGRA114_CLK_I2C1 12 +#define TEGRA114_CLK_NDFLASH 13 +#define TEGRA114_CLK_SDMMC1 14 +#define TEGRA114_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA114_CLK_PWM 17 +#define TEGRA114_CLK_I2S2 18 +#define TEGRA114_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA114_CLK_GR2D 21 +#define TEGRA114_CLK_USBD 22 +#define TEGRA114_CLK_ISP 23 +#define TEGRA114_CLK_GR3D 24 +/* 25 */ +#define TEGRA114_CLK_DISP2 26 +#define TEGRA114_CLK_DISP1 27 +#define TEGRA114_CLK_HOST1X 28 +#define TEGRA114_CLK_VCP 29 +#define TEGRA114_CLK_I2S0 30 +/* 31 */ + +/* 32 */ +/* 33 */ +#define TEGRA114_CLK_APBDMA 34 +/* 35 */ +#define TEGRA114_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA114_CLK_KFUSE 40 +#define TEGRA114_CLK_SBC1 41 +#define TEGRA114_CLK_NOR 42 +/* 43 */ +#define TEGRA114_CLK_SBC2 44 +/* 45 */ +#define TEGRA114_CLK_SBC3 46 +#define TEGRA114_CLK_I2C5 47 +#define TEGRA114_CLK_DSIA 48 +/* 49 */ +#define TEGRA114_CLK_MIPI 50 +#define TEGRA114_CLK_HDMI 51 +#define TEGRA114_CLK_CSI 52 +/* 53 */ +#define TEGRA114_CLK_I2C2 54 +#define TEGRA114_CLK_UARTC 55 +#define TEGRA114_CLK_MIPI_CAL 56 +#define TEGRA114_CLK_EMC 57 +#define TEGRA114_CLK_USB2 58 +#define TEGRA114_CLK_USB3 59 +/* 60 */ +#define TEGRA114_CLK_VDE 61 +#define TEGRA114_CLK_BSEA 62 +#define TEGRA114_CLK_BSEV 63 + +/* 64 */ +#define TEGRA114_CLK_UARTD 65 +/* 66 */ +#define TEGRA114_CLK_I2C3 67 +#define TEGRA114_CLK_SBC4 68 +#define TEGRA114_CLK_SDMMC3 69 +/* 70 */ +#define TEGRA114_CLK_OWR 71 +/* 72 */ +#define TEGRA114_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA114_CLK_LA 76 +#define TEGRA114_CLK_TRACE 77 +#define TEGRA114_CLK_SOC_THERM 78 +#define TEGRA114_CLK_DTV 79 +#define TEGRA114_CLK_NDSPEED 80 +#define TEGRA114_CLK_I2CSLOW 81 +#define TEGRA114_CLK_DSIB 82 +#define TEGRA114_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA114_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA114_CLK_MSENC 91 +#define TEGRA114_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA114_CLK_MSELECT 99 +#define TEGRA114_CLK_TSENSOR 100 +#define TEGRA114_CLK_I2S3 101 +#define TEGRA114_CLK_I2S4 102 +#define TEGRA114_CLK_I2C4 103 +#define TEGRA114_CLK_SBC5 104 +#define TEGRA114_CLK_SBC6 105 +#define TEGRA114_CLK_D_AUDIO 106 +#define TEGRA114_CLK_APBIF 107 +#define TEGRA114_CLK_DAM0 108 +#define TEGRA114_CLK_DAM1 109 +#define TEGRA114_CLK_DAM2 110 +#define TEGRA114_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA114_CLK_AUDIO0_2X 113 +#define TEGRA114_CLK_AUDIO1_2X 114 +#define TEGRA114_CLK_AUDIO2_2X 115 +#define TEGRA114_CLK_AUDIO3_2X 116 +#define TEGRA114_CLK_AUDIO4_2X 117 +#define TEGRA114_CLK_SPDIF_2X 118 +#define TEGRA114_CLK_ACTMON 119 +#define TEGRA114_CLK_EXTERN1 120 +#define TEGRA114_CLK_EXTERN2 121 +#define TEGRA114_CLK_EXTERN3 122 +/* 123 */ +/* 124 */ +#define TEGRA114_CLK_HDA 125 +/* 126 */ +#define TEGRA114_CLK_SE 127 + +#define TEGRA114_CLK_HDA2HDMI 128 +/* 129 */ +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA114_CLK_CILAB 144 +#define TEGRA114_CLK_CILCD 145 +#define TEGRA114_CLK_CILE 146 +#define TEGRA114_CLK_DSIALP 147 +#define TEGRA114_CLK_DSIBLP 148 +/* 149 */ +#define TEGRA114_CLK_DDS 150 +/* 151 */ +#define TEGRA114_CLK_DP2 152 +#define TEGRA114_CLK_AMX 153 +#define TEGRA114_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA114_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +/* 166 */ +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +/* 171 */ +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +/* 176 */ +/* 177 */ +/* 178 */ +/* 179 */ +/* 180 */ +/* 181 */ +/* 182 */ +/* 183 */ +/* 184 */ +/* 185 */ +/* 186 */ +/* 187 */ +/* 188 */ +/* 189 */ +/* 190 */ +/* 191 */ + +#define TEGRA114_CLK_UARTB 192 +#define TEGRA114_CLK_VFIR 193 +#define TEGRA114_CLK_SPDIF_IN 194 +#define TEGRA114_CLK_SPDIF_OUT 195 +#define TEGRA114_CLK_VI 196 +#define TEGRA114_CLK_VI_SENSOR 197 +#define TEGRA114_CLK_FUSE 198 +#define TEGRA114_CLK_FUSE_BURN 199 +#define TEGRA114_CLK_CLK_32K 200 +#define TEGRA114_CLK_CLK_M 201 +#define TEGRA114_CLK_CLK_M_DIV2 202 +#define TEGRA114_CLK_CLK_M_DIV4 203 +#define TEGRA114_CLK_PLL_REF 204 +#define TEGRA114_CLK_PLL_C 205 +#define TEGRA114_CLK_PLL_C_OUT1 206 +#define TEGRA114_CLK_PLL_C2 207 +#define TEGRA114_CLK_PLL_C3 208 +#define TEGRA114_CLK_PLL_M 209 +#define TEGRA114_CLK_PLL_M_OUT1 210 +#define TEGRA114_CLK_PLL_P 211 +#define TEGRA114_CLK_PLL_P_OUT1 212 +#define TEGRA114_CLK_PLL_P_OUT2 213 +#define TEGRA114_CLK_PLL_P_OUT3 214 +#define TEGRA114_CLK_PLL_P_OUT4 215 +#define TEGRA114_CLK_PLL_A 216 +#define TEGRA114_CLK_PLL_A_OUT0 217 +#define TEGRA114_CLK_PLL_D 218 +#define TEGRA114_CLK_PLL_D_OUT0 219 +#define TEGRA114_CLK_PLL_D2 220 +#define TEGRA114_CLK_PLL_D2_OUT0 221 +#define TEGRA114_CLK_PLL_U 222 +#define TEGRA114_CLK_PLL_U_480M 223 + +#define TEGRA114_CLK_PLL_U_60M 224 +#define TEGRA114_CLK_PLL_U_48M 225 +#define TEGRA114_CLK_PLL_U_12M 226 +#define TEGRA114_CLK_PLL_X 227 +#define TEGRA114_CLK_PLL_X_OUT0 228 +#define TEGRA114_CLK_PLL_RE_VCO 229 +#define TEGRA114_CLK_PLL_RE_OUT 230 +#define TEGRA114_CLK_PLL_E_OUT0 231 +#define TEGRA114_CLK_SPDIF_IN_SYNC 232 +#define TEGRA114_CLK_I2S0_SYNC 233 +#define TEGRA114_CLK_I2S1_SYNC 234 +#define TEGRA114_CLK_I2S2_SYNC 235 +#define TEGRA114_CLK_I2S3_SYNC 236 +#define TEGRA114_CLK_I2S4_SYNC 237 +#define TEGRA114_CLK_VIMCLK_SYNC 238 +#define TEGRA114_CLK_AUDIO0 239 +#define TEGRA114_CLK_AUDIO1 240 +#define TEGRA114_CLK_AUDIO2 241 +#define TEGRA114_CLK_AUDIO3 242 +#define TEGRA114_CLK_AUDIO4 243 +#define TEGRA114_CLK_SPDIF 244 +#define TEGRA114_CLK_CLK_OUT_1 245 +#define TEGRA114_CLK_CLK_OUT_2 246 +#define TEGRA114_CLK_CLK_OUT_3 247 +#define TEGRA114_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA114_CLK_XUSB_HOST_SRC 252 +#define TEGRA114_CLK_XUSB_FALCON_SRC 253 +#define TEGRA114_CLK_XUSB_FS_SRC 254 +#define TEGRA114_CLK_XUSB_SS_SRC 255 + +#define TEGRA114_CLK_XUSB_DEV_SRC 256 +#define TEGRA114_CLK_XUSB_DEV 257 +#define TEGRA114_CLK_XUSB_HS_SRC 258 +#define TEGRA114_CLK_SCLK 259 +#define TEGRA114_CLK_HCLK 260 +#define TEGRA114_CLK_PCLK 261 +#define TEGRA114_CLK_CCLK_G 262 +#define TEGRA114_CLK_CCLK_LP 263 +#define TEGRA114_CLK_DFLL_REF 264 +#define TEGRA114_CLK_DFLL_SOC 265 +/* 266 */ +/* 267 */ +/* 268 */ +/* 269 */ +/* 270 */ +/* 271 */ +/* 272 */ +/* 273 */ +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA114_CLK_AUDIO0_MUX 300 +#define TEGRA114_CLK_AUDIO1_MUX 301 +#define TEGRA114_CLK_AUDIO2_MUX 302 +#define TEGRA114_CLK_AUDIO3_MUX 303 +#define TEGRA114_CLK_AUDIO4_MUX 304 +#define TEGRA114_CLK_SPDIF_MUX 305 +#define TEGRA114_CLK_CLK_OUT_1_MUX 306 +#define TEGRA114_CLK_CLK_OUT_2_MUX 307 +#define TEGRA114_CLK_CLK_OUT_3_MUX 308 +#define TEGRA114_CLK_DSIA_MUX 309 +#define TEGRA114_CLK_DSIB_MUX 310 +#define TEGRA114_CLK_CLK_MAX 311 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h new file mode 100644 index 0000000000..fd8d62ac7f --- /dev/null +++ b/include/dt-bindings/clock/tegra124-car.h @@ -0,0 +1,342 @@ +/* + * This header provides constants for binding nvidia,tegra124-car. + * + * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 185 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 185 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H + +/* 0 */ +/* 1 */ +/* 2 */ +#define TEGRA124_CLK_ISPB 3 +#define TEGRA124_CLK_RTC 4 +#define TEGRA124_CLK_TIMER 5 +#define TEGRA124_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA124_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA124_CLK_I2S1 11 +#define TEGRA124_CLK_I2C1 12 +#define TEGRA124_CLK_NDFLASH 13 +#define TEGRA124_CLK_SDMMC1 14 +#define TEGRA124_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA124_CLK_PWM 17 +#define TEGRA124_CLK_I2S2 18 +/* 20 (register bit affects vi and vi_sensor) */ +/* 21 */ +#define TEGRA124_CLK_USBD 22 +#define TEGRA124_CLK_ISP 23 +/* 26 */ +/* 25 */ +#define TEGRA124_CLK_DISP2 26 +#define TEGRA124_CLK_DISP1 27 +#define TEGRA124_CLK_HOST1X 28 +#define TEGRA124_CLK_VCP 29 +#define TEGRA124_CLK_I2S0 30 +/* 31 */ + +/* 32 */ +/* 33 */ +#define TEGRA124_CLK_APBDMA 34 +/* 35 */ +#define TEGRA124_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA124_CLK_KFUSE 40 +#define TEGRA124_CLK_SBC1 41 +#define TEGRA124_CLK_NOR 42 +/* 43 */ +#define TEGRA124_CLK_SBC2 44 +/* 45 */ +#define TEGRA124_CLK_SBC3 46 +#define TEGRA124_CLK_I2C5 47 +#define TEGRA124_CLK_DSIA 48 +/* 49 */ +#define TEGRA124_CLK_MIPI 50 +#define TEGRA124_CLK_HDMI 51 +#define TEGRA124_CLK_CSI 52 +/* 53 */ +#define TEGRA124_CLK_I2C2 54 +#define TEGRA124_CLK_UARTC 55 +#define TEGRA124_CLK_MIPI_CAL 56 +#define TEGRA124_CLK_EMC 57 +#define TEGRA124_CLK_USB2 58 +#define TEGRA124_CLK_USB3 59 +/* 60 */ +#define TEGRA124_CLK_VDE 61 +#define TEGRA124_CLK_BSEA 62 +#define TEGRA124_CLK_BSEV 63 + +/* 64 */ +#define TEGRA124_CLK_UARTD 65 +#define TEGRA124_CLK_UARTE 66 +#define TEGRA124_CLK_I2C3 67 +#define TEGRA124_CLK_SBC4 68 +#define TEGRA124_CLK_SDMMC3 69 +#define TEGRA124_CLK_PCIE 70 +#define TEGRA124_CLK_OWR 71 +#define TEGRA124_CLK_AFI 72 +#define TEGRA124_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA124_CLK_LA 76 +#define TEGRA124_CLK_TRACE 77 +#define TEGRA124_CLK_SOC_THERM 78 +#define TEGRA124_CLK_DTV 79 +#define TEGRA124_CLK_NDSPEED 80 +#define TEGRA124_CLK_I2CSLOW 81 +#define TEGRA124_CLK_DSIB 82 +#define TEGRA124_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA124_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA124_CLK_MSENC 91 +#define TEGRA124_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA124_CLK_MSELECT 99 +#define TEGRA124_CLK_TSENSOR 100 +#define TEGRA124_CLK_I2S3 101 +#define TEGRA124_CLK_I2S4 102 +#define TEGRA124_CLK_I2C4 103 +#define TEGRA124_CLK_SBC5 104 +#define TEGRA124_CLK_SBC6 105 +#define TEGRA124_CLK_D_AUDIO 106 +#define TEGRA124_CLK_APBIF 107 +#define TEGRA124_CLK_DAM0 108 +#define TEGRA124_CLK_DAM1 109 +#define TEGRA124_CLK_DAM2 110 +#define TEGRA124_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA124_CLK_AUDIO0_2X 113 +#define TEGRA124_CLK_AUDIO1_2X 114 +#define TEGRA124_CLK_AUDIO2_2X 115 +#define TEGRA124_CLK_AUDIO3_2X 116 +#define TEGRA124_CLK_AUDIO4_2X 117 +#define TEGRA124_CLK_SPDIF_2X 118 +#define TEGRA124_CLK_ACTMON 119 +#define TEGRA124_CLK_EXTERN1 120 +#define TEGRA124_CLK_EXTERN2 121 +#define TEGRA124_CLK_EXTERN3 122 +#define TEGRA124_CLK_SATA_OOB 123 +#define TEGRA124_CLK_SATA 124 +#define TEGRA124_CLK_HDA 125 +/* 126 */ +#define TEGRA124_CLK_SE 127 + +#define TEGRA124_CLK_HDA2HDMI 128 +#define TEGRA124_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA124_CLK_CILAB 144 +#define TEGRA124_CLK_CILCD 145 +#define TEGRA124_CLK_CILE 146 +#define TEGRA124_CLK_DSIALP 147 +#define TEGRA124_CLK_DSIBLP 148 +#define TEGRA124_CLK_ENTROPY 149 +#define TEGRA124_CLK_DDS 150 +/* 151 */ +#define TEGRA124_CLK_DP2 152 +#define TEGRA124_CLK_AMX 153 +#define TEGRA124_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA124_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +#define TEGRA124_CLK_I2C6 166 +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +#define TEGRA124_CLK_VIM2_CLK 171 +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +#define TEGRA124_CLK_HDMI_AUDIO 176 +#define TEGRA124_CLK_CLK72MHZ 177 +#define TEGRA124_CLK_VIC03 178 +/* 179 */ +#define TEGRA124_CLK_ADX1 180 +#define TEGRA124_CLK_DPAUX 181 +#define TEGRA124_CLK_SOR0 182 +/* 183 */ +#define TEGRA124_CLK_GPU 184 +#define TEGRA124_CLK_AMX1 185 +#define TEGRA124_CLK_AFC0 186 +#define TEGRA124_CLK_AFC1 187 +#define TEGRA124_CLK_AFC2 188 +#define TEGRA124_CLK_AFC3 189 +#define TEGRA124_CLK_AFC4 190 +#define TEGRA124_CLK_AFC5 191 +#define TEGRA124_CLK_UARTB 192 +#define TEGRA124_CLK_VFIR 193 +#define TEGRA124_CLK_SPDIF_IN 194 +#define TEGRA124_CLK_SPDIF_OUT 195 +#define TEGRA124_CLK_VI 196 +#define TEGRA124_CLK_VI_SENSOR 197 +#define TEGRA124_CLK_FUSE 198 +#define TEGRA124_CLK_FUSE_BURN 199 +#define TEGRA124_CLK_CLK_32K 200 +#define TEGRA124_CLK_CLK_M 201 +#define TEGRA124_CLK_CLK_M_DIV2 202 +#define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_PLL_REF 204 +#define TEGRA124_CLK_PLL_C 205 +#define TEGRA124_CLK_PLL_C_OUT1 206 +#define TEGRA124_CLK_PLL_C2 207 +#define TEGRA124_CLK_PLL_C3 208 +#define TEGRA124_CLK_PLL_M 209 +#define TEGRA124_CLK_PLL_M_OUT1 210 +#define TEGRA124_CLK_PLL_P 211 +#define TEGRA124_CLK_PLL_P_OUT1 212 +#define TEGRA124_CLK_PLL_P_OUT2 213 +#define TEGRA124_CLK_PLL_P_OUT3 214 +#define TEGRA124_CLK_PLL_P_OUT4 215 +#define TEGRA124_CLK_PLL_A 216 +#define TEGRA124_CLK_PLL_A_OUT0 217 +#define TEGRA124_CLK_PLL_D 218 +#define TEGRA124_CLK_PLL_D_OUT0 219 +#define TEGRA124_CLK_PLL_D2 220 +#define TEGRA124_CLK_PLL_D2_OUT0 221 +#define TEGRA124_CLK_PLL_U 222 +#define TEGRA124_CLK_PLL_U_480M 223 + +#define TEGRA124_CLK_PLL_U_60M 224 +#define TEGRA124_CLK_PLL_U_48M 225 +#define TEGRA124_CLK_PLL_U_12M 226 +#define TEGRA124_CLK_PLL_X 227 +#define TEGRA124_CLK_PLL_X_OUT0 228 +#define TEGRA124_CLK_PLL_RE_VCO 229 +#define TEGRA124_CLK_PLL_RE_OUT 230 +#define TEGRA124_CLK_PLL_E 231 +#define TEGRA124_CLK_SPDIF_IN_SYNC 232 +#define TEGRA124_CLK_I2S0_SYNC 233 +#define TEGRA124_CLK_I2S1_SYNC 234 +#define TEGRA124_CLK_I2S2_SYNC 235 +#define TEGRA124_CLK_I2S3_SYNC 236 +#define TEGRA124_CLK_I2S4_SYNC 237 +#define TEGRA124_CLK_VIMCLK_SYNC 238 +#define TEGRA124_CLK_AUDIO0 239 +#define TEGRA124_CLK_AUDIO1 240 +#define TEGRA124_CLK_AUDIO2 241 +#define TEGRA124_CLK_AUDIO3 242 +#define TEGRA124_CLK_AUDIO4 243 +#define TEGRA124_CLK_SPDIF 244 +#define TEGRA124_CLK_CLK_OUT_1 245 +#define TEGRA124_CLK_CLK_OUT_2 246 +#define TEGRA124_CLK_CLK_OUT_3 247 +#define TEGRA124_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA124_CLK_XUSB_HOST_SRC 252 +#define TEGRA124_CLK_XUSB_FALCON_SRC 253 +#define TEGRA124_CLK_XUSB_FS_SRC 254 +#define TEGRA124_CLK_XUSB_SS_SRC 255 + +#define TEGRA124_CLK_XUSB_DEV_SRC 256 +#define TEGRA124_CLK_XUSB_DEV 257 +#define TEGRA124_CLK_XUSB_HS_SRC 258 +#define TEGRA124_CLK_SCLK 259 +#define TEGRA124_CLK_HCLK 260 +#define TEGRA124_CLK_PCLK 261 +#define TEGRA124_CLK_CCLK_G 262 +#define TEGRA124_CLK_CCLK_LP 263 +#define TEGRA124_CLK_DFLL_REF 264 +#define TEGRA124_CLK_DFLL_SOC 265 +#define TEGRA124_CLK_VI_SENSOR2 266 +#define TEGRA124_CLK_PLL_P_OUT5 267 +#define TEGRA124_CLK_CML0 268 +#define TEGRA124_CLK_CML1 269 +#define TEGRA124_CLK_PLL_C4 270 +#define TEGRA124_CLK_PLL_DP 271 +#define TEGRA124_CLK_PLL_E_MUX 272 +/* 273 */ +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA124_CLK_AUDIO0_MUX 300 +#define TEGRA124_CLK_AUDIO1_MUX 301 +#define TEGRA124_CLK_AUDIO2_MUX 302 +#define TEGRA124_CLK_AUDIO3_MUX 303 +#define TEGRA124_CLK_AUDIO4_MUX 304 +#define TEGRA124_CLK_SPDIF_MUX 305 +#define TEGRA124_CLK_CLK_OUT_1_MUX 306 +#define TEGRA124_CLK_CLK_OUT_2_MUX 307 +#define TEGRA124_CLK_CLK_OUT_3_MUX 308 +#define TEGRA124_CLK_DSIA_MUX 309 +#define TEGRA124_CLK_DSIB_MUX 310 +#define TEGRA124_CLK_SOR0_LVDS 311 +#define TEGRA124_CLK_PLL_M_UD 311 +#define TEGRA124_CLK_CLK_MAX 312 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h new file mode 100644 index 0000000000..a1ae9a8fdd --- /dev/null +++ b/include/dt-bindings/clock/tegra20-car.h @@ -0,0 +1,158 @@ +/* + * This header provides constants for binding nvidia,tegra20-car. + * + * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 95 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 96 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H + +#define TEGRA20_CLK_CPU 0 +/* 1 */ +/* 2 */ +#define TEGRA20_CLK_AC97 3 +#define TEGRA20_CLK_RTC 4 +#define TEGRA20_CLK_TIMER 5 +#define TEGRA20_CLK_UARTA 6 +/* 7 (register bit affects uart2 and vfir) */ +#define TEGRA20_CLK_GPIO 8 +#define TEGRA20_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA20_CLK_I2S1 11 +#define TEGRA20_CLK_I2C1 12 +#define TEGRA20_CLK_NDFLASH 13 +#define TEGRA20_CLK_SDMMC1 14 +#define TEGRA20_CLK_SDMMC4 15 +#define TEGRA20_CLK_TWC 16 +#define TEGRA20_CLK_PWM 17 +#define TEGRA20_CLK_I2S2 18 +#define TEGRA20_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA20_CLK_GR2D 21 +#define TEGRA20_CLK_USBD 22 +#define TEGRA20_CLK_ISP 23 +#define TEGRA20_CLK_GR3D 24 +#define TEGRA20_CLK_IDE 25 +#define TEGRA20_CLK_DISP2 26 +#define TEGRA20_CLK_DISP1 27 +#define TEGRA20_CLK_HOST1X 28 +#define TEGRA20_CLK_VCP 29 +/* 30 */ +#define TEGRA20_CLK_CACHE2 31 + +#define TEGRA20_CLK_MEM 32 +#define TEGRA20_CLK_AHBDMA 33 +#define TEGRA20_CLK_APBDMA 34 +/* 35 */ +#define TEGRA20_CLK_KBC 36 +#define TEGRA20_CLK_STAT_MON 37 +#define TEGRA20_CLK_PMC 38 +#define TEGRA20_CLK_FUSE 39 +#define TEGRA20_CLK_KFUSE 40 +#define TEGRA20_CLK_SBC1 41 +#define TEGRA20_CLK_NOR 42 +#define TEGRA20_CLK_SPI 43 +#define TEGRA20_CLK_SBC2 44 +#define TEGRA20_CLK_XIO 45 +#define TEGRA20_CLK_SBC3 46 +#define TEGRA20_CLK_DVC 47 +#define TEGRA20_CLK_DSI 48 +/* 49 (register bit affects tvo and cve) */ +#define TEGRA20_CLK_MIPI 50 +#define TEGRA20_CLK_HDMI 51 +#define TEGRA20_CLK_CSI 52 +#define TEGRA20_CLK_TVDAC 53 +#define TEGRA20_CLK_I2C2 54 +#define TEGRA20_CLK_UARTC 55 +/* 56 */ +#define TEGRA20_CLK_EMC 57 +#define TEGRA20_CLK_USB2 58 +#define TEGRA20_CLK_USB3 59 +#define TEGRA20_CLK_MPE 60 +#define TEGRA20_CLK_VDE 61 +#define TEGRA20_CLK_BSEA 62 +#define TEGRA20_CLK_BSEV 63 + +#define TEGRA20_CLK_SPEEDO 64 +#define TEGRA20_CLK_UARTD 65 +#define TEGRA20_CLK_UARTE 66 +#define TEGRA20_CLK_I2C3 67 +#define TEGRA20_CLK_SBC4 68 +#define TEGRA20_CLK_SDMMC3 69 +#define TEGRA20_CLK_PEX 70 +#define TEGRA20_CLK_OWR 71 +#define TEGRA20_CLK_AFI 72 +#define TEGRA20_CLK_CSITE 73 +#define TEGRA20_CLK_PCIE_XCLK 74 +#define TEGRA20_CLK_AVPUCQ 75 +#define TEGRA20_CLK_LA 76 +/* 77 */ +/* 78 */ +/* 79 */ +/* 80 */ +/* 81 */ +/* 82 */ +/* 83 */ +#define TEGRA20_CLK_IRAMA 84 +#define TEGRA20_CLK_IRAMB 85 +#define TEGRA20_CLK_IRAMC 86 +#define TEGRA20_CLK_IRAMD 87 +#define TEGRA20_CLK_CRAM2 88 +#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ +#define TEGRA20_CLK_CLK_D 90 +/* 91 */ +#define TEGRA20_CLK_CSUS 92 +#define TEGRA20_CLK_CDEV2 93 +#define TEGRA20_CLK_CDEV1 94 +/* 95 */ + +#define TEGRA20_CLK_UARTB 96 +#define TEGRA20_CLK_VFIR 97 +#define TEGRA20_CLK_SPDIF_IN 98 +#define TEGRA20_CLK_SPDIF_OUT 99 +#define TEGRA20_CLK_VI 100 +#define TEGRA20_CLK_VI_SENSOR 101 +#define TEGRA20_CLK_TVO 102 +#define TEGRA20_CLK_CVE 103 +#define TEGRA20_CLK_OSC 104 +#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ +#define TEGRA20_CLK_CLK_M 106 +#define TEGRA20_CLK_SCLK 107 +#define TEGRA20_CLK_CCLK 108 +#define TEGRA20_CLK_HCLK 109 +#define TEGRA20_CLK_PCLK 110 +#define TEGRA20_CLK_BLINK 111 +#define TEGRA20_CLK_PLL_A 112 +#define TEGRA20_CLK_PLL_A_OUT0 113 +#define TEGRA20_CLK_PLL_C 114 +#define TEGRA20_CLK_PLL_C_OUT1 115 +#define TEGRA20_CLK_PLL_D 116 +#define TEGRA20_CLK_PLL_D_OUT0 117 +#define TEGRA20_CLK_PLL_E 118 +#define TEGRA20_CLK_PLL_M 119 +#define TEGRA20_CLK_PLL_M_OUT1 120 +#define TEGRA20_CLK_PLL_P 121 +#define TEGRA20_CLK_PLL_P_OUT1 122 +#define TEGRA20_CLK_PLL_P_OUT2 123 +#define TEGRA20_CLK_PLL_P_OUT3 124 +#define TEGRA20_CLK_PLL_P_OUT4 125 +#define TEGRA20_CLK_PLL_S 126 +#define TEGRA20_CLK_PLL_U 127 + +#define TEGRA20_CLK_PLL_X 128 +#define TEGRA20_CLK_COP 129 /* a/k/a avp */ +#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ +#define TEGRA20_CLK_PLL_REF 131 +#define TEGRA20_CLK_TWD 132 +#define TEGRA20_CLK_CLK_MAX 133 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h new file mode 100644 index 0000000000..22445820a9 --- /dev/null +++ b/include/dt-bindings/clock/tegra30-car.h @@ -0,0 +1,273 @@ +/* + * This header provides constants for binding nvidia,tegra30-car. + * + * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 160 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 160 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H + +#define TEGRA30_CLK_CPU 0 +/* 1 */ +/* 2 */ +/* 3 */ +#define TEGRA30_CLK_RTC 4 +#define TEGRA30_CLK_TIMER 5 +#define TEGRA30_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +#define TEGRA30_CLK_GPIO 8 +#define TEGRA30_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA30_CLK_I2S1 11 +#define TEGRA30_CLK_I2C1 12 +#define TEGRA30_CLK_NDFLASH 13 +#define TEGRA30_CLK_SDMMC1 14 +#define TEGRA30_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA30_CLK_PWM 17 +#define TEGRA30_CLK_I2S2 18 +#define TEGRA30_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA30_CLK_GR2D 21 +#define TEGRA30_CLK_USBD 22 +#define TEGRA30_CLK_ISP 23 +#define TEGRA30_CLK_GR3D 24 +/* 25 */ +#define TEGRA30_CLK_DISP2 26 +#define TEGRA30_CLK_DISP1 27 +#define TEGRA30_CLK_HOST1X 28 +#define TEGRA30_CLK_VCP 29 +#define TEGRA30_CLK_I2S0 30 +#define TEGRA30_CLK_COP_CACHE 31 + +#define TEGRA30_CLK_MC 32 +#define TEGRA30_CLK_AHBDMA 33 +#define TEGRA30_CLK_APBDMA 34 +/* 35 */ +#define TEGRA30_CLK_KBC 36 +#define TEGRA30_CLK_STATMON 37 +#define TEGRA30_CLK_PMC 38 +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA30_CLK_KFUSE 40 +#define TEGRA30_CLK_SBC1 41 +#define TEGRA30_CLK_NOR 42 +/* 43 */ +#define TEGRA30_CLK_SBC2 44 +/* 45 */ +#define TEGRA30_CLK_SBC3 46 +#define TEGRA30_CLK_I2C5 47 +#define TEGRA30_CLK_DSIA 48 +/* 49 (register bit affects cve and tvo) */ +#define TEGRA30_CLK_MIPI 50 +#define TEGRA30_CLK_HDMI 51 +#define TEGRA30_CLK_CSI 52 +#define TEGRA30_CLK_TVDAC 53 +#define TEGRA30_CLK_I2C2 54 +#define TEGRA30_CLK_UARTC 55 +/* 56 */ +#define TEGRA30_CLK_EMC 57 +#define TEGRA30_CLK_USB2 58 +#define TEGRA30_CLK_USB3 59 +#define TEGRA30_CLK_MPE 60 +#define TEGRA30_CLK_VDE 61 +#define TEGRA30_CLK_BSEA 62 +#define TEGRA30_CLK_BSEV 63 + +#define TEGRA30_CLK_SPEEDO 64 +#define TEGRA30_CLK_UARTD 65 +#define TEGRA30_CLK_UARTE 66 +#define TEGRA30_CLK_I2C3 67 +#define TEGRA30_CLK_SBC4 68 +#define TEGRA30_CLK_SDMMC3 69 +#define TEGRA30_CLK_PCIE 70 +#define TEGRA30_CLK_OWR 71 +#define TEGRA30_CLK_AFI 72 +#define TEGRA30_CLK_CSITE 73 +#define TEGRA30_CLK_PCIEX 74 +#define TEGRA30_CLK_AVPUCQ 75 +#define TEGRA30_CLK_LA 76 +/* 77 */ +/* 78 */ +#define TEGRA30_CLK_DTV 79 +#define TEGRA30_CLK_NDSPEED 80 +#define TEGRA30_CLK_I2CSLOW 81 +#define TEGRA30_CLK_DSIB 82 +/* 83 */ +#define TEGRA30_CLK_IRAMA 84 +#define TEGRA30_CLK_IRAMB 85 +#define TEGRA30_CLK_IRAMC 86 +#define TEGRA30_CLK_IRAMD 87 +#define TEGRA30_CLK_CRAM2 88 +/* 89 */ +#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ +/* 91 */ +#define TEGRA30_CLK_CSUS 92 +#define TEGRA30_CLK_CDEV2 93 +#define TEGRA30_CLK_CDEV1 94 +/* 95 */ + +#define TEGRA30_CLK_CPU_G 96 +#define TEGRA30_CLK_CPU_LP 97 +#define TEGRA30_CLK_GR3D2 98 +#define TEGRA30_CLK_MSELECT 99 +#define TEGRA30_CLK_TSENSOR 100 +#define TEGRA30_CLK_I2S3 101 +#define TEGRA30_CLK_I2S4 102 +#define TEGRA30_CLK_I2C4 103 +#define TEGRA30_CLK_SBC5 104 +#define TEGRA30_CLK_SBC6 105 +#define TEGRA30_CLK_D_AUDIO 106 +#define TEGRA30_CLK_APBIF 107 +#define TEGRA30_CLK_DAM0 108 +#define TEGRA30_CLK_DAM1 109 +#define TEGRA30_CLK_DAM2 110 +#define TEGRA30_CLK_HDA2CODEC_2X 111 +#define TEGRA30_CLK_ATOMICS 112 +#define TEGRA30_CLK_AUDIO0_2X 113 +#define TEGRA30_CLK_AUDIO1_2X 114 +#define TEGRA30_CLK_AUDIO2_2X 115 +#define TEGRA30_CLK_AUDIO3_2X 116 +#define TEGRA30_CLK_AUDIO4_2X 117 +#define TEGRA30_CLK_SPDIF_2X 118 +#define TEGRA30_CLK_ACTMON 119 +#define TEGRA30_CLK_EXTERN1 120 +#define TEGRA30_CLK_EXTERN2 121 +#define TEGRA30_CLK_EXTERN3 122 +#define TEGRA30_CLK_SATA_OOB 123 +#define TEGRA30_CLK_SATA 124 +#define TEGRA30_CLK_HDA 125 +/* 126 */ +#define TEGRA30_CLK_SE 127 + +#define TEGRA30_CLK_HDA2HDMI 128 +#define TEGRA30_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 */ +/* 144 */ +/* 145 */ +/* 146 */ +/* 147 */ +/* 148 */ +/* 149 */ +/* 150 */ +/* 151 */ +/* 152 */ +/* 153 */ +/* 154 */ +/* 155 */ +/* 156 */ +/* 157 */ +/* 158 */ +/* 159 */ + +#define TEGRA30_CLK_UARTB 160 +#define TEGRA30_CLK_VFIR 161 +#define TEGRA30_CLK_SPDIF_IN 162 +#define TEGRA30_CLK_SPDIF_OUT 163 +#define TEGRA30_CLK_VI 164 +#define TEGRA30_CLK_VI_SENSOR 165 +#define TEGRA30_CLK_FUSE 166 +#define TEGRA30_CLK_FUSE_BURN 167 +#define TEGRA30_CLK_CVE 168 +#define TEGRA30_CLK_TVO 169 +#define TEGRA30_CLK_CLK_32K 170 +#define TEGRA30_CLK_CLK_M 171 +#define TEGRA30_CLK_CLK_M_DIV2 172 +#define TEGRA30_CLK_CLK_M_DIV4 173 +#define TEGRA30_CLK_PLL_REF 174 +#define TEGRA30_CLK_PLL_C 175 +#define TEGRA30_CLK_PLL_C_OUT1 176 +#define TEGRA30_CLK_PLL_M 177 +#define TEGRA30_CLK_PLL_M_OUT1 178 +#define TEGRA30_CLK_PLL_P 179 +#define TEGRA30_CLK_PLL_P_OUT1 180 +#define TEGRA30_CLK_PLL_P_OUT2 181 +#define TEGRA30_CLK_PLL_P_OUT3 182 +#define TEGRA30_CLK_PLL_P_OUT4 183 +#define TEGRA30_CLK_PLL_A 184 +#define TEGRA30_CLK_PLL_A_OUT0 185 +#define TEGRA30_CLK_PLL_D 186 +#define TEGRA30_CLK_PLL_D_OUT0 187 +#define TEGRA30_CLK_PLL_D2 188 +#define TEGRA30_CLK_PLL_D2_OUT0 189 +#define TEGRA30_CLK_PLL_U 190 +#define TEGRA30_CLK_PLL_X 191 + +#define TEGRA30_CLK_PLL_X_OUT0 192 +#define TEGRA30_CLK_PLL_E 193 +#define TEGRA30_CLK_SPDIF_IN_SYNC 194 +#define TEGRA30_CLK_I2S0_SYNC 195 +#define TEGRA30_CLK_I2S1_SYNC 196 +#define TEGRA30_CLK_I2S2_SYNC 197 +#define TEGRA30_CLK_I2S3_SYNC 198 +#define TEGRA30_CLK_I2S4_SYNC 199 +#define TEGRA30_CLK_VIMCLK_SYNC 200 +#define TEGRA30_CLK_AUDIO0 201 +#define TEGRA30_CLK_AUDIO1 202 +#define TEGRA30_CLK_AUDIO2 203 +#define TEGRA30_CLK_AUDIO3 204 +#define TEGRA30_CLK_AUDIO4 205 +#define TEGRA30_CLK_SPDIF 206 +#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ +#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ +#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ +#define TEGRA30_CLK_SCLK 210 +#define TEGRA30_CLK_BLINK 211 +#define TEGRA30_CLK_CCLK_G 212 +#define TEGRA30_CLK_CCLK_LP 213 +#define TEGRA30_CLK_TWD 214 +#define TEGRA30_CLK_CML0 215 +#define TEGRA30_CLK_CML1 216 +#define TEGRA30_CLK_HCLK 217 +#define TEGRA30_CLK_PCLK 218 +/* 219 */ +/* 220 */ +/* 221 */ +/* 222 */ +/* 223 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA30_CLK_CLK_OUT_1_MUX 300 +#define TEGRA30_CLK_CLK_OUT_2_MUX 301 +#define TEGRA30_CLK_CLK_OUT_3_MUX 302 +#define TEGRA30_CLK_AUDIO0_MUX 303 +#define TEGRA30_CLK_AUDIO1_MUX 304 +#define TEGRA30_CLK_AUDIO2_MUX 305 +#define TEGRA30_CLK_AUDIO3_MUX 306 +#define TEGRA30_CLK_AUDIO4_MUX 307 +#define TEGRA30_CLK_SPDIF_MUX 308 +#define TEGRA30_CLK_CLK_MAX 309 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h new file mode 100644 index 0000000000..e6b1e0a808 --- /dev/null +++ b/include/dt-bindings/gpio/gpio.h @@ -0,0 +1,15 @@ +/* + * This header provides constants for most GPIO bindings. + * + * Most GPIO bindings include a flags cell as part of the GPIO specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_GPIO_GPIO_H +#define _DT_BINDINGS_GPIO_GPIO_H + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +#endif diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h new file mode 100644 index 0000000000..197dc28b67 --- /dev/null +++ b/include/dt-bindings/gpio/tegra-gpio.h @@ -0,0 +1,51 @@ +/* + * This header provides constants for binding nvidia,tegra*-gpio. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H + +#include + +#define TEGRA_GPIO_BANK_ID_A 0 +#define TEGRA_GPIO_BANK_ID_B 1 +#define TEGRA_GPIO_BANK_ID_C 2 +#define TEGRA_GPIO_BANK_ID_D 3 +#define TEGRA_GPIO_BANK_ID_E 4 +#define TEGRA_GPIO_BANK_ID_F 5 +#define TEGRA_GPIO_BANK_ID_G 6 +#define TEGRA_GPIO_BANK_ID_H 7 +#define TEGRA_GPIO_BANK_ID_I 8 +#define TEGRA_GPIO_BANK_ID_J 9 +#define TEGRA_GPIO_BANK_ID_K 10 +#define TEGRA_GPIO_BANK_ID_L 11 +#define TEGRA_GPIO_BANK_ID_M 12 +#define TEGRA_GPIO_BANK_ID_N 13 +#define TEGRA_GPIO_BANK_ID_O 14 +#define TEGRA_GPIO_BANK_ID_P 15 +#define TEGRA_GPIO_BANK_ID_Q 16 +#define TEGRA_GPIO_BANK_ID_R 17 +#define TEGRA_GPIO_BANK_ID_S 18 +#define TEGRA_GPIO_BANK_ID_T 19 +#define TEGRA_GPIO_BANK_ID_U 20 +#define TEGRA_GPIO_BANK_ID_V 21 +#define TEGRA_GPIO_BANK_ID_W 22 +#define TEGRA_GPIO_BANK_ID_X 23 +#define TEGRA_GPIO_BANK_ID_Y 24 +#define TEGRA_GPIO_BANK_ID_Z 25 +#define TEGRA_GPIO_BANK_ID_AA 26 +#define TEGRA_GPIO_BANK_ID_BB 27 +#define TEGRA_GPIO_BANK_ID_CC 28 +#define TEGRA_GPIO_BANK_ID_DD 29 +#define TEGRA_GPIO_BANK_ID_EE 30 +#define TEGRA_GPIO_BANK_ID_FF 31 + +#define TEGRA_GPIO(bank, offset) \ + ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) + +#endif diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h new file mode 100644 index 0000000000..042e7b3b62 --- /dev/null +++ b/include/dt-bindings/input/input.h @@ -0,0 +1,525 @@ +/* + * This header provides constants for most input bindings. + * + * Most input bindings include key code, matrix key code format. + * In most cases, key code and matrix key code format uses + * the standard values/macro defined in this header. + */ + +#ifndef _DT_BINDINGS_INPUT_INPUT_H +#define _DT_BINDINGS_INPUT_INPUT_H + +#define KEY_RESERVED 0 +#define KEY_ESC 1 +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_0 11 +#define KEY_MINUS 12 +#define KEY_EQUAL 13 +#define KEY_BACKSPACE 14 +#define KEY_TAB 15 +#define KEY_Q 16 +#define KEY_W 17 +#define KEY_E 18 +#define KEY_R 19 +#define KEY_T 20 +#define KEY_Y 21 +#define KEY_U 22 +#define KEY_I 23 +#define KEY_O 24 +#define KEY_P 25 +#define KEY_LEFTBRACE 26 +#define KEY_RIGHTBRACE 27 +#define KEY_ENTER 28 +#define KEY_LEFTCTRL 29 +#define KEY_A 30 +#define KEY_S 31 +#define KEY_D 32 +#define KEY_F 33 +#define KEY_G 34 +#define KEY_H 35 +#define KEY_J 36 +#define KEY_K 37 +#define KEY_L 38 +#define KEY_SEMICOLON 39 +#define KEY_APOSTROPHE 40 +#define KEY_GRAVE 41 +#define KEY_LEFTSHIFT 42 +#define KEY_BACKSLASH 43 +#define KEY_Z 44 +#define KEY_X 45 +#define KEY_C 46 +#define KEY_V 47 +#define KEY_B 48 +#define KEY_N 49 +#define KEY_M 50 +#define KEY_COMMA 51 +#define KEY_DOT 52 +#define KEY_SLASH 53 +#define KEY_RIGHTSHIFT 54 +#define KEY_KPASTERISK 55 +#define KEY_LEFTALT 56 +#define KEY_SPACE 57 +#define KEY_CAPSLOCK 58 +#define KEY_F1 59 +#define KEY_F2 60 +#define KEY_F3 61 +#define KEY_F4 62 +#define KEY_F5 63 +#define KEY_F6 64 +#define KEY_F7 65 +#define KEY_F8 66 +#define KEY_F9 67 +#define KEY_F10 68 +#define KEY_NUMLOCK 69 +#define KEY_SCROLLLOCK 70 +#define KEY_KP7 71 +#define KEY_KP8 72 +#define KEY_KP9 73 +#define KEY_KPMINUS 74 +#define KEY_KP4 75 +#define KEY_KP5 76 +#define KEY_KP6 77 +#define KEY_KPPLUS 78 +#define KEY_KP1 79 +#define KEY_KP2 80 +#define KEY_KP3 81 +#define KEY_KP0 82 +#define KEY_KPDOT 83 + +#define KEY_ZENKAKUHANKAKU 85 +#define KEY_102ND 86 +#define KEY_F11 87 +#define KEY_F12 88 +#define KEY_RO 89 +#define KEY_KATAKANA 90 +#define KEY_HIRAGANA 91 +#define KEY_HENKAN 92 +#define KEY_KATAKANAHIRAGANA 93 +#define KEY_MUHENKAN 94 +#define KEY_KPJPCOMMA 95 +#define KEY_KPENTER 96 +#define KEY_RIGHTCTRL 97 +#define KEY_KPSLASH 98 +#define KEY_SYSRQ 99 +#define KEY_RIGHTALT 100 +#define KEY_LINEFEED 101 +#define KEY_HOME 102 +#define KEY_UP 103 +#define KEY_PAGEUP 104 +#define KEY_LEFT 105 +#define KEY_RIGHT 106 +#define KEY_END 107 +#define KEY_DOWN 108 +#define KEY_PAGEDOWN 109 +#define KEY_INSERT 110 +#define KEY_DELETE 111 +#define KEY_MACRO 112 +#define KEY_MUTE 113 +#define KEY_VOLUMEDOWN 114 +#define KEY_VOLUMEUP 115 +#define KEY_POWER 116 /* SC System Power Down */ +#define KEY_KPEQUAL 117 +#define KEY_KPPLUSMINUS 118 +#define KEY_PAUSE 119 +#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ + +#define KEY_KPCOMMA 121 +#define KEY_HANGEUL 122 +#define KEY_HANGUEL KEY_HANGEUL +#define KEY_HANJA 123 +#define KEY_YEN 124 +#define KEY_LEFTMETA 125 +#define KEY_RIGHTMETA 126 +#define KEY_COMPOSE 127 + +#define KEY_STOP 128 /* AC Stop */ +#define KEY_AGAIN 129 +#define KEY_PROPS 130 /* AC Properties */ +#define KEY_UNDO 131 /* AC Undo */ +#define KEY_FRONT 132 +#define KEY_COPY 133 /* AC Copy */ +#define KEY_OPEN 134 /* AC Open */ +#define KEY_PASTE 135 /* AC Paste */ +#define KEY_FIND 136 /* AC Search */ +#define KEY_CUT 137 /* AC Cut */ +#define KEY_HELP 138 /* AL Integrated Help Center */ +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_CALC 140 /* AL Calculator */ +#define KEY_SETUP 141 +#define KEY_SLEEP 142 /* SC System Sleep */ +#define KEY_WAKEUP 143 /* System Wake Up */ +#define KEY_FILE 144 /* AL Local Machine Browser */ +#define KEY_SENDFILE 145 +#define KEY_DELETEFILE 146 +#define KEY_XFER 147 +#define KEY_PROG1 148 +#define KEY_PROG2 149 +#define KEY_WWW 150 /* AL Internet Browser */ +#define KEY_MSDOS 151 +#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ +#define KEY_SCREENLOCK KEY_COFFEE +#define KEY_DIRECTION 153 +#define KEY_CYCLEWINDOWS 154 +#define KEY_MAIL 155 +#define KEY_BOOKMARKS 156 /* AC Bookmarks */ +#define KEY_COMPUTER 157 +#define KEY_BACK 158 /* AC Back */ +#define KEY_FORWARD 159 /* AC Forward */ +#define KEY_CLOSECD 160 +#define KEY_EJECTCD 161 +#define KEY_EJECTCLOSECD 162 +#define KEY_NEXTSONG 163 +#define KEY_PLAYPAUSE 164 +#define KEY_PREVIOUSSONG 165 +#define KEY_STOPCD 166 +#define KEY_RECORD 167 +#define KEY_REWIND 168 +#define KEY_PHONE 169 /* Media Select Telephone */ +#define KEY_ISO 170 +#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ +#define KEY_HOMEPAGE 172 /* AC Home */ +#define KEY_REFRESH 173 /* AC Refresh */ +#define KEY_EXIT 174 /* AC Exit */ +#define KEY_MOVE 175 +#define KEY_EDIT 176 +#define KEY_SCROLLUP 177 +#define KEY_SCROLLDOWN 178 +#define KEY_KPLEFTPAREN 179 +#define KEY_KPRIGHTPAREN 180 +#define KEY_NEW 181 /* AC New */ +#define KEY_REDO 182 /* AC Redo/Repeat */ + +#define KEY_F13 183 +#define KEY_F14 184 +#define KEY_F15 185 +#define KEY_F16 186 +#define KEY_F17 187 +#define KEY_F18 188 +#define KEY_F19 189 +#define KEY_F20 190 +#define KEY_F21 191 +#define KEY_F22 192 +#define KEY_F23 193 +#define KEY_F24 194 + +#define KEY_PLAYCD 200 +#define KEY_PAUSECD 201 +#define KEY_PROG3 202 +#define KEY_PROG4 203 +#define KEY_DASHBOARD 204 /* AL Dashboard */ +#define KEY_SUSPEND 205 +#define KEY_CLOSE 206 /* AC Close */ +#define KEY_PLAY 207 +#define KEY_FASTFORWARD 208 +#define KEY_BASSBOOST 209 +#define KEY_PRINT 210 /* AC Print */ +#define KEY_HP 211 +#define KEY_CAMERA 212 +#define KEY_SOUND 213 +#define KEY_QUESTION 214 +#define KEY_EMAIL 215 +#define KEY_CHAT 216 +#define KEY_SEARCH 217 +#define KEY_CONNECT 218 +#define KEY_FINANCE 219 /* AL Checkbook/Finance */ +#define KEY_SPORT 220 +#define KEY_SHOP 221 +#define KEY_ALTERASE 222 +#define KEY_CANCEL 223 /* AC Cancel */ +#define KEY_BRIGHTNESSDOWN 224 +#define KEY_BRIGHTNESSUP 225 +#define KEY_MEDIA 226 + +#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video + outputs (Monitor/LCD/TV-out/etc) */ +#define KEY_KBDILLUMTOGGLE 228 +#define KEY_KBDILLUMDOWN 229 +#define KEY_KBDILLUMUP 230 + +#define KEY_SEND 231 /* AC Send */ +#define KEY_REPLY 232 /* AC Reply */ +#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ +#define KEY_SAVE 234 /* AC Save */ +#define KEY_DOCUMENTS 235 + +#define KEY_BATTERY 236 + +#define KEY_BLUETOOTH 237 +#define KEY_WLAN 238 +#define KEY_UWB 239 + +#define KEY_UNKNOWN 240 + +#define KEY_VIDEO_NEXT 241 /* drive next video source */ +#define KEY_VIDEO_PREV 242 /* drive previous video source */ +#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ +#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */ +#define KEY_DISPLAY_OFF 245 /* display device to off state */ + +#define KEY_WIMAX 246 +#define KEY_RFKILL 247 /* Key that controls all radios */ + +#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ + +/* Code 255 is reserved for special needs of AT keyboard driver */ + +#define BTN_MISC 0x100 +#define BTN_0 0x100 +#define BTN_1 0x101 +#define BTN_2 0x102 +#define BTN_3 0x103 +#define BTN_4 0x104 +#define BTN_5 0x105 +#define BTN_6 0x106 +#define BTN_7 0x107 +#define BTN_8 0x108 +#define BTN_9 0x109 + +#define BTN_MOUSE 0x110 +#define BTN_LEFT 0x110 +#define BTN_RIGHT 0x111 +#define BTN_MIDDLE 0x112 +#define BTN_SIDE 0x113 +#define BTN_EXTRA 0x114 +#define BTN_FORWARD 0x115 +#define BTN_BACK 0x116 +#define BTN_TASK 0x117 + +#define BTN_JOYSTICK 0x120 +#define BTN_TRIGGER 0x120 +#define BTN_THUMB 0x121 +#define BTN_THUMB2 0x122 +#define BTN_TOP 0x123 +#define BTN_TOP2 0x124 +#define BTN_PINKIE 0x125 +#define BTN_BASE 0x126 +#define BTN_BASE2 0x127 +#define BTN_BASE3 0x128 +#define BTN_BASE4 0x129 +#define BTN_BASE5 0x12a +#define BTN_BASE6 0x12b +#define BTN_DEAD 0x12f + +#define BTN_GAMEPAD 0x130 +#define BTN_SOUTH 0x130 +#define BTN_A BTN_SOUTH +#define BTN_EAST 0x131 +#define BTN_B BTN_EAST +#define BTN_C 0x132 +#define BTN_NORTH 0x133 +#define BTN_X BTN_NORTH +#define BTN_WEST 0x134 +#define BTN_Y BTN_WEST +#define BTN_Z 0x135 +#define BTN_TL 0x136 +#define BTN_TR 0x137 +#define BTN_TL2 0x138 +#define BTN_TR2 0x139 +#define BTN_SELECT 0x13a +#define BTN_START 0x13b +#define BTN_MODE 0x13c +#define BTN_THUMBL 0x13d +#define BTN_THUMBR 0x13e + +#define BTN_DIGI 0x140 +#define BTN_TOOL_PEN 0x140 +#define BTN_TOOL_RUBBER 0x141 +#define BTN_TOOL_BRUSH 0x142 +#define BTN_TOOL_PENCIL 0x143 +#define BTN_TOOL_AIRBRUSH 0x144 +#define BTN_TOOL_FINGER 0x145 +#define BTN_TOOL_MOUSE 0x146 +#define BTN_TOOL_LENS 0x147 +#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ +#define BTN_TOUCH 0x14a +#define BTN_STYLUS 0x14b +#define BTN_STYLUS2 0x14c +#define BTN_TOOL_DOUBLETAP 0x14d +#define BTN_TOOL_TRIPLETAP 0x14e +#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ + +#define BTN_WHEEL 0x150 +#define BTN_GEAR_DOWN 0x150 +#define BTN_GEAR_UP 0x151 + +#define KEY_OK 0x160 +#define KEY_SELECT 0x161 +#define KEY_GOTO 0x162 +#define KEY_CLEAR 0x163 +#define KEY_POWER2 0x164 +#define KEY_OPTION 0x165 +#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ +#define KEY_TIME 0x167 +#define KEY_VENDOR 0x168 +#define KEY_ARCHIVE 0x169 +#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ +#define KEY_CHANNEL 0x16b +#define KEY_FAVORITES 0x16c +#define KEY_EPG 0x16d +#define KEY_PVR 0x16e /* Media Select Home */ +#define KEY_MHP 0x16f +#define KEY_LANGUAGE 0x170 +#define KEY_TITLE 0x171 +#define KEY_SUBTITLE 0x172 +#define KEY_ANGLE 0x173 +#define KEY_ZOOM 0x174 +#define KEY_MODE 0x175 +#define KEY_KEYBOARD 0x176 +#define KEY_SCREEN 0x177 +#define KEY_PC 0x178 /* Media Select Computer */ +#define KEY_TV 0x179 /* Media Select TV */ +#define KEY_TV2 0x17a /* Media Select Cable */ +#define KEY_VCR 0x17b /* Media Select VCR */ +#define KEY_VCR2 0x17c /* VCR Plus */ +#define KEY_SAT 0x17d /* Media Select Satellite */ +#define KEY_SAT2 0x17e +#define KEY_CD 0x17f /* Media Select CD */ +#define KEY_TAPE 0x180 /* Media Select Tape */ +#define KEY_RADIO 0x181 +#define KEY_TUNER 0x182 /* Media Select Tuner */ +#define KEY_PLAYER 0x183 +#define KEY_TEXT 0x184 +#define KEY_DVD 0x185 /* Media Select DVD */ +#define KEY_AUX 0x186 +#define KEY_MP3 0x187 +#define KEY_AUDIO 0x188 /* AL Audio Browser */ +#define KEY_VIDEO 0x189 /* AL Movie Browser */ +#define KEY_DIRECTORY 0x18a +#define KEY_LIST 0x18b +#define KEY_MEMO 0x18c /* Media Select Messages */ +#define KEY_CALENDAR 0x18d +#define KEY_RED 0x18e +#define KEY_GREEN 0x18f +#define KEY_YELLOW 0x190 +#define KEY_BLUE 0x191 +#define KEY_CHANNELUP 0x192 /* Channel Increment */ +#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ +#define KEY_FIRST 0x194 +#define KEY_LAST 0x195 /* Recall Last */ +#define KEY_AB 0x196 +#define KEY_NEXT 0x197 +#define KEY_RESTART 0x198 +#define KEY_SLOW 0x199 +#define KEY_SHUFFLE 0x19a +#define KEY_BREAK 0x19b +#define KEY_PREVIOUS 0x19c +#define KEY_DIGITS 0x19d +#define KEY_TEEN 0x19e +#define KEY_TWEN 0x19f +#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ +#define KEY_GAMES 0x1a1 /* Media Select Games */ +#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ +#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ +#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ +#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ +#define KEY_EDITOR 0x1a6 /* AL Text Editor */ +#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ +#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ +#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ +#define KEY_DATABASE 0x1aa /* AL Database App */ +#define KEY_NEWS 0x1ab /* AL Newsreader */ +#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ +#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ +#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ +#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ +#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ +#define KEY_LOGOFF 0x1b1 /* AL Logoff */ + +#define KEY_DOLLAR 0x1b2 +#define KEY_EURO 0x1b3 + +#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ +#define KEY_FRAMEFORWARD 0x1b5 +#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ +#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ +#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ +#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ +#define KEY_IMAGES 0x1ba /* AL Image Browser */ + +#define KEY_DEL_EOL 0x1c0 +#define KEY_DEL_EOS 0x1c1 +#define KEY_INS_LINE 0x1c2 +#define KEY_DEL_LINE 0x1c3 + +#define KEY_FN 0x1d0 +#define KEY_FN_ESC 0x1d1 +#define KEY_FN_F1 0x1d2 +#define KEY_FN_F2 0x1d3 +#define KEY_FN_F3 0x1d4 +#define KEY_FN_F4 0x1d5 +#define KEY_FN_F5 0x1d6 +#define KEY_FN_F6 0x1d7 +#define KEY_FN_F7 0x1d8 +#define KEY_FN_F8 0x1d9 +#define KEY_FN_F9 0x1da +#define KEY_FN_F10 0x1db +#define KEY_FN_F11 0x1dc +#define KEY_FN_F12 0x1dd +#define KEY_FN_1 0x1de +#define KEY_FN_2 0x1df +#define KEY_FN_D 0x1e0 +#define KEY_FN_E 0x1e1 +#define KEY_FN_F 0x1e2 +#define KEY_FN_S 0x1e3 +#define KEY_FN_B 0x1e4 + +#define KEY_BRL_DOT1 0x1f1 +#define KEY_BRL_DOT2 0x1f2 +#define KEY_BRL_DOT3 0x1f3 +#define KEY_BRL_DOT4 0x1f4 +#define KEY_BRL_DOT5 0x1f5 +#define KEY_BRL_DOT6 0x1f6 +#define KEY_BRL_DOT7 0x1f7 +#define KEY_BRL_DOT8 0x1f8 +#define KEY_BRL_DOT9 0x1f9 +#define KEY_BRL_DOT10 0x1fa + +#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ +#define KEY_NUMERIC_1 0x201 /* and other keypads */ +#define KEY_NUMERIC_2 0x202 +#define KEY_NUMERIC_3 0x203 +#define KEY_NUMERIC_4 0x204 +#define KEY_NUMERIC_5 0x205 +#define KEY_NUMERIC_6 0x206 +#define KEY_NUMERIC_7 0x207 +#define KEY_NUMERIC_8 0x208 +#define KEY_NUMERIC_9 0x209 +#define KEY_NUMERIC_STAR 0x20a +#define KEY_NUMERIC_POUND 0x20b + +#define KEY_CAMERA_FOCUS 0x210 +#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ + +#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ +#define KEY_TOUCHPAD_ON 0x213 +#define KEY_TOUCHPAD_OFF 0x214 + +#define KEY_CAMERA_ZOOMIN 0x215 +#define KEY_CAMERA_ZOOMOUT 0x216 +#define KEY_CAMERA_UP 0x217 +#define KEY_CAMERA_DOWN 0x218 +#define KEY_CAMERA_LEFT 0x219 +#define KEY_CAMERA_RIGHT 0x21a + +#define KEY_ATTENDANT_ON 0x21b +#define KEY_ATTENDANT_OFF 0x21c +#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ +#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ + +#define BTN_DPAD_UP 0x220 +#define BTN_DPAD_DOWN 0x221 +#define BTN_DPAD_LEFT 0x222 +#define BTN_DPAD_RIGHT 0x223 + +#define MATRIX_KEY(row, col, code) \ + ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) + +#endif /* _DT_BINDINGS_INPUT_INPUT_H */ diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h new file mode 100644 index 0000000000..1ea1b702fe --- /dev/null +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -0,0 +1,22 @@ +/* + * This header provides constants for the ARM GIC. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H + +#include + +/* interrupt specific cell 0 */ + +#define GIC_SPI 0 +#define GIC_PPI 1 + +/* + * Interrupt specifier cell 2. + * The flaggs in irq.h are valid, plus those below. + */ +#define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) + +#endif diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h new file mode 100644 index 0000000000..33a1003c55 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irq.h @@ -0,0 +1,19 @@ +/* + * This header provides constants for most IRQ bindings. + * + * Most IRQ bindings include a flags cell as part of the IRQ specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#endif diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h new file mode 100644 index 0000000000..2fbc804e1a --- /dev/null +++ b/include/dt-bindings/pinctrl/am33xx.h @@ -0,0 +1,42 @@ +/* + * This header provides constants specific to AM33XX pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H +#define _DT_BINDINGS_PINCTRL_AM33XX_H + +#include + +/* am33xx specific mux bit defines */ +#undef PULL_ENA +#undef INPUT_EN + +#define PULL_DISABLE (1 << 3) +#define INPUT_EN (1 << 5) +#define SLEWCTRL_FAST (1 << 6) + +/* update macro depending on INPUT_EN and PULL_ENA */ +#undef PIN_OUTPUT +#undef PIN_OUTPUT_PULLUP +#undef PIN_OUTPUT_PULLDOWN +#undef PIN_INPUT +#undef PIN_INPUT_PULLUP +#undef PIN_INPUT_PULLDOWN + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +/* undef non-existing modes */ +#undef PIN_OFF_NONE +#undef PIN_OFF_OUTPUT_HIGH +#undef PIN_OFF_OUTPUT_LOW +#undef PIN_OFF_INPUT_PULLUP +#undef PIN_OFF_INPUT_PULLDOWN +#undef PIN_OFF_WAKEUPENABLE + +#endif + diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h new file mode 100644 index 0000000000..edbd250809 --- /dev/null +++ b/include/dt-bindings/pinctrl/omap.h @@ -0,0 +1,55 @@ +/* + * This header provides constants for OMAP pinctrl bindings. + * + * Copyright (C) 2009 Nokia + * Copyright (C) 2009-2010 Texas Instruments + */ + +#ifndef _DT_BINDINGS_PINCTRL_OMAP_H +#define _DT_BINDINGS_PINCTRL_OMAP_H + +/* 34xx mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 + +/* 24xx/34xx mux bit defines */ +#define PULL_ENA (1 << 3) +#define PULL_UP (1 << 4) +#define ALTELECTRICALSEL (1 << 5) + +/* 34xx specific mux bit defines */ +#define INPUT_EN (1 << 8) +#define OFF_EN (1 << 9) +#define OFFOUT_EN (1 << 10) +#define OFFOUT_VAL (1 << 11) +#define OFF_PULL_EN (1 << 12) +#define OFF_PULL_UP (1 << 13) +#define WAKEUP_EN (1 << 14) + +/* 44xx specific mux bit defines */ +#define WAKEUP_EVENT (1 << 15) + +/* Active pin states */ +#define PIN_OUTPUT 0 +#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) +#define PIN_INPUT INPUT_EN +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + +/* Off mode states */ +#define PIN_OFF_NONE 0 +#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN + +#endif + diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h new file mode 100644 index 0000000000..914d56da93 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h @@ -0,0 +1,7 @@ +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H +#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 + +#define TEGRA_XUSB_PADCTL_PCIE 0 +#define TEGRA_XUSB_PADCTL_SATA 1 + +#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 0000000000..ebafa498be --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,45 @@ +/* + * This header provides constants for Tegra pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +/* + * Enable/disable for diffeent dt properties. This is applicable for + * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, + * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. + */ +#define TEGRA_PIN_DISABLE 0 +#define TEGRA_PIN_ENABLE 1 + +#define TEGRA_PIN_PULL_NONE 0 +#define TEGRA_PIN_PULL_DOWN 1 +#define TEGRA_PIN_PULL_UP 2 + +/* Low power mode driver */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +/* Rising/Falling slew rate */ +#define TEGRA_PIN_SLEW_RATE_FASTEST 0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 + +#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 0000000000..351d8cdc6f --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif diff --git a/include/dtt.h b/include/dtt.h index 29268f64ea..058bca4d5d 100644 --- a/include/dtt.h +++ b/include/dtt.h @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* diff --git a/include/dwmmc.h b/include/dwmmc.h index 08ced0bf1f..109f7c8ac7 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,12 @@ #define DWMCI_BMOD_IDMAC_FB (1 << 1) #define DWMCI_BMOD_IDMAC_EN (1 << 7) +/* UHS register */ +#define DWMCI_DDR_MODE (1 << 16) + +/* quirks */ +#define DWMCI_QUIRK_DISABLE_SMU (1 << 0) + struct dwmci_host { char *name; void *ioaddr; @@ -131,14 +137,19 @@ struct dwmci_host { unsigned int version; unsigned int clock; unsigned int bus_hz; + unsigned int div; int dev_index; + int dev_id; int buswidth; u32 clksel_val; u32 fifoth_val; struct mmc *mmc; void (*clksel)(struct dwmci_host *host); - unsigned int (*mmc_clk)(int dev_index); + void (*board_init)(struct dwmci_host *host); + unsigned int (*get_mmc_clk)(struct dwmci_host *host); + + struct mmc_config cfg; }; struct dwmci_idmac { @@ -146,7 +157,7 @@ struct dwmci_idmac { u32 cnt; u32 addr; u32 next_addr; -}; +} __aligned(ARCH_DMA_MINALIGN); static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) { diff --git a/include/e500.h b/include/e500.h index 0ff8e89a1e..5884a224d2 100644 --- a/include/e500.h +++ b/include/e500.h @@ -10,19 +10,22 @@ typedef struct { - unsigned long freqProcessor[CONFIG_MAX_CPUS]; - unsigned long freqSystemBus; - unsigned long freqDDRBus; - unsigned long freqLocalBus; - unsigned long freqQE; + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; + unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freqFMan[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN - unsigned long freqQMAN; + unsigned long freq_qman; #endif #ifdef CONFIG_SYS_DPAA_PME - unsigned long freqPME; + unsigned long freq_pme; +#endif +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + unsigned char diff_sysclk; #endif } MPC85xx_SYS_INFO; diff --git a/include/ec_commands.h b/include/ec_commands.h index 12811cc070..78baab1641 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -42,13 +42,19 @@ #define EC_LPC_ADDR_HOST_CMD 0x204 /* I/O addresses for host command args and params */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 -#define EC_LPC_ADDR_HOST_PARAM 0x804 -#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */ - -/* I/O addresses for host command params, old interface */ -#define EC_LPC_ADDR_OLD_PARAM 0x880 -#define EC_OLD_PARAM_SIZE 0x080 /* Size of param area in bytes */ +/* Protocol version 2 */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is + * EC_PROTO2_MAX_PARAM_SIZE */ +/* Protocol version 3 */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ + +/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff + * and they tell the kernel that so we have to think of it as two parts. */ +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 +#define EC_HOST_CMD_REGION_SIZE 0x80 /* EC command register bit functions */ #define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ @@ -122,8 +128,8 @@ #define EC_SWITCH_LID_OPEN 0x01 #define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 -/* Recovery requested via keyboard */ -#define EC_SWITCH_KEYBOARD_RECOVERY 0x08 +/* Was recovery requested via keyboard; now unused. */ +#define EC_SWITCH_IGNORE1 0x08 /* Recovery requested via dedicated signal (from servo board) */ #define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ @@ -132,10 +138,13 @@ /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */ #define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +/* Host command interface supports version 3 protocol */ +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 /* Wireless switch flags */ #define EC_WIRELESS_SWITCH_WLAN 0x01 #define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* * This header file is used in coreboot both in C and ACPI code. The ACPI code @@ -191,6 +200,9 @@ enum ec_status { EC_RES_UNAVAILABLE = 9, /* No response available */ EC_RES_TIMEOUT = 10, /* We got a timeout */ EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */ }; /* @@ -272,6 +284,105 @@ struct ec_lpc_host_args { */ #define EC_HOST_ARGS_FLAG_TO_HOST 0x02 +/*****************************************************************************/ + +/* + * Protocol version 2 for I2C and SPI send a request this way: + * + * 0 EC_CMD_VERSION0 + (command version) + * 1 Command number + * 2 Length of params = N + * 3..N+2 Params, if any + * N+3 8-bit checksum of bytes 0..N+2 + * + * The corresponding response is: + * + * 0 Result code (EC_RES_*) + * 1 Length of params = M + * 2..M+1 Params, if any + * M+2 8-bit checksum of bytes 0..M+1 + */ +#define EC_PROTO2_REQUEST_HEADER_BYTES 3 +#define EC_PROTO2_REQUEST_TRAILER_BYTES 1 +#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ + EC_PROTO2_REQUEST_TRAILER_BYTES) + +#define EC_PROTO2_RESPONSE_HEADER_BYTES 2 +#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 +#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ + EC_PROTO2_RESPONSE_TRAILER_BYTES) + +/* Parameter length was limited by the LPC interface */ +#define EC_PROTO2_MAX_PARAM_SIZE 0xfc + +/* Maximum request and response packet sizes for protocol version 2 */ +#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) + +/*****************************************************************************/ + +/* + * Value written to legacy command port / prefix byte to indicate protocol + * 3+ structs are being used. Usage is bus-dependent. + */ +#define EC_COMMAND_PROTOCOL_3 0xda + +#define EC_HOST_REQUEST_VERSION 3 + +/* Version 3 request from host */ +struct ec_host_request { + /* Struct version (=3) + * + * EC will return EC_RES_INVALID_HEADER if it receives a header with a + * version it doesn't know how to parse. + */ + uint8_t struct_version; + + /* + * Checksum of request and data; sum of all bytes including checksum + * should total to 0. + */ + uint8_t checksum; + + /* Command code */ + uint16_t command; + + /* Command version */ + uint8_t command_version; + + /* Unused byte in current protocol version; set to 0 */ + uint8_t reserved; + + /* Length of data which follows this header */ + uint16_t data_len; +} __packed; + +#define EC_HOST_RESPONSE_VERSION 3 + +/* Version 3 response from EC */ +struct ec_host_response { + /* Struct version (=3) */ + uint8_t struct_version; + + /* + * Checksum of response and data; sum of all bytes including checksum + * should total to 0. + */ + uint8_t checksum; + + /* Result code (EC_RES_*) */ + uint16_t result; + + /* Length of data which follows this header */ + uint16_t data_len; + + /* Unused bytes in current protocol version; set to 0 */ + uint16_t reserved; +} __packed; + +/*****************************************************************************/ /* * Notes on commands: * @@ -411,6 +522,46 @@ struct ec_response_get_comms_status { uint32_t flags; /* Mask of enum ec_comms_status */ } __packed; +/* + * Fake a variety of responses, purely for testing purposes. + * FIXME: Would be nice to force checksum errors. + */ +#define EC_CMD_TEST_PROTOCOL 0x0a + +/* Tell the EC what to send back to us. */ +struct ec_params_test_protocol { + uint32_t ec_result; + uint32_t ret_len; + uint8_t buf[32]; +} __packed; + +/* Here it comes... */ +struct ec_response_test_protocol { + uint8_t buf[32]; +} __packed; + +/* Get prococol information */ +#define EC_CMD_GET_PROTOCOL_INFO 0x0b + +/* Flags for ec_response_get_protocol_info.flags */ +/* EC_RES_IN_PROGRESS may be returned if a command is slow */ +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) + +struct ec_response_get_protocol_info { + /* Fields which exist if at least protocol version 3 supported */ + + /* Bitmask of protocol versions supported (1 << n means version n)*/ + uint32_t protocol_versions; + + /* Maximum request packet size, in bytes */ + uint16_t max_request_packet_size; + + /* Maximum response packet size, in bytes */ + uint16_t max_response_packet_size; + + /* Flags; see EC_PROTOCOL_INFO_* */ + uint32_t flags; +} __packed; /*****************************************************************************/ /* Flash commands */ @@ -452,15 +603,15 @@ struct ec_params_flash_read { /* Write flash */ #define EC_CMD_FLASH_WRITE 0x12 +#define EC_VER_FLASH_WRITE 1 + +/* Version 0 of the flash command supported only 64 bytes of data */ +#define EC_FLASH_WRITE_VER0_SIZE 64 struct ec_params_flash_write { uint32_t offset; /* Byte offset to write */ uint32_t size; /* Size to write in bytes */ - /* - * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to - * use a power of 2 so writes stay aligned. - */ - uint8_t data[64]; + /* Followed by data to write */ } __packed; /* Erase flash */ @@ -536,7 +687,7 @@ struct ec_response_flash_protect { enum ec_flash_region { /* Region which holds read-only EC image */ - EC_FLASH_REGION_RO, + EC_FLASH_REGION_RO = 0, /* Region which holds rewritable EC image */ EC_FLASH_REGION_RW, /* @@ -544,6 +695,8 @@ enum ec_flash_region { * EC_FLASH_REGION_RO) */ EC_FLASH_REGION_WP_RO, + /* Number of regions */ + EC_FLASH_REGION_COUNT, }; struct ec_params_flash_region_info { @@ -726,6 +879,49 @@ enum lightbar_command { LIGHTBAR_NUM_CMDS }; +/*****************************************************************************/ +/* LED control commands */ + +#define EC_CMD_LED_CONTROL 0x29 + +enum ec_led_id { + EC_LED_ID_BATTERY_LED = 0, + EC_LED_ID_POWER_BUTTON_LED, + EC_LED_ID_ADAPTER_LED, +}; + +/* LED control flags */ +#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ + +enum ec_led_colors { + EC_LED_COLOR_RED = 0, + EC_LED_COLOR_GREEN, + EC_LED_COLOR_BLUE, + EC_LED_COLOR_YELLOW, + EC_LED_COLOR_WHITE, + + EC_LED_COLOR_COUNT +}; + +struct ec_params_led_control { + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ + + uint8_t brightness[EC_LED_COLOR_COUNT]; +} __packed; + +struct ec_response_led_control { + /* + * Available brightness value range. + * + * Range 0 means color channel not present. + * Range 1 means on/off control. + * Other values means the LED is control by PWM. + */ + uint8_t brightness_range[EC_LED_COLOR_COUNT]; +} __packed; + /*****************************************************************************/ /* Verified boot commands */ @@ -914,57 +1110,57 @@ struct ec_params_tmp006_set_calibration { } __packed; /*****************************************************************************/ -/* CROS_EC - Matrix KeyBoard Protocol */ +/* MKBP - Matrix KeyBoard Protocol */ /* * Read key state * - * Returns raw data for keyboard cols; see ec_response_cros_ec_info.cols for + * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for * expected response size. */ -#define EC_CMD_CROS_EC_STATE 0x60 +#define EC_CMD_MKBP_STATE 0x60 /* Provide information about the matrix : number of rows and columns */ -#define EC_CMD_CROS_EC_INFO 0x61 +#define EC_CMD_MKBP_INFO 0x61 -struct ec_response_cros_ec_info { +struct ec_response_mkbp_info { uint32_t rows; uint32_t cols; uint8_t switches; } __packed; /* Simulate key press */ -#define EC_CMD_CROS_EC_SIMULATE_KEY 0x62 +#define EC_CMD_MKBP_SIMULATE_KEY 0x62 -struct ec_params_cros_ec_simulate_key { +struct ec_params_mkbp_simulate_key { uint8_t col; uint8_t row; uint8_t pressed; } __packed; /* Configure keyboard scanning */ -#define EC_CMD_CROS_EC_SET_CONFIG 0x64 -#define EC_CMD_CROS_EC_GET_CONFIG 0x65 +#define EC_CMD_MKBP_SET_CONFIG 0x64 +#define EC_CMD_MKBP_GET_CONFIG 0x65 /* flags */ -enum cros_ec_config_flags { - EC_CROS_EC_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ +enum mkbp_config_flags { + EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ }; -enum cros_ec_config_valid { - EC_CROS_EC_VALID_SCAN_PERIOD = 1 << 0, - EC_CROS_EC_VALID_POLL_TIMEOUT = 1 << 1, - EC_CROS_EC_VALID_MIN_POST_SCAN_DELAY = 1 << 3, - EC_CROS_EC_VALID_OUTPUT_SETTLE = 1 << 4, - EC_CROS_EC_VALID_DEBOUNCE_DOWN = 1 << 5, - EC_CROS_EC_VALID_DEBOUNCE_UP = 1 << 6, - EC_CROS_EC_VALID_FIFO_MAX_DEPTH = 1 << 7, +enum mkbp_config_valid { + EC_MKBP_VALID_SCAN_PERIOD = 1 << 0, + EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1, + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3, + EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4, + EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5, + EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6, + EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7, }; /* Configuration for our key scanning algorithm */ -struct ec_cros_ec_config { +struct ec_mkbp_config { uint32_t valid_mask; /* valid fields */ - uint8_t flags; /* some flags (enum cros_ec_config_flags) */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ uint8_t valid_flags; /* which flags are valid */ uint16_t scan_period_us; /* period between start of scans */ /* revert to interrupt mode after no activity for this long */ @@ -983,12 +1179,12 @@ struct ec_cros_ec_config { uint8_t fifo_max_depth; } __packed; -struct ec_params_cros_ec_set_config { - struct ec_cros_ec_config config; +struct ec_params_mkbp_set_config { + struct ec_mkbp_config config; } __packed; -struct ec_response_cros_ec_get_config { - struct ec_cros_ec_config config; +struct ec_response_mkbp_get_config { + struct ec_mkbp_config config; } __packed; /* Run the key scan emulation */ @@ -1144,7 +1340,7 @@ struct ec_response_gpio_get { #define EC_CMD_I2C_READ 0x94 struct ec_params_i2c_read { - uint16_t addr; + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t read_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; @@ -1158,7 +1354,7 @@ struct ec_response_i2c_read { struct ec_params_i2c_write { uint16_t data; - uint16_t addr; + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t write_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; @@ -1241,6 +1437,61 @@ struct ec_response_ldo_get { uint8_t state; } __packed; +/*****************************************************************************/ +/* Power info. */ + +/* + * Get power info. + */ +#define EC_CMD_POWER_INFO 0x9d + +struct ec_response_power_info { + uint32_t usb_dev_type; + uint16_t voltage_ac; + uint16_t voltage_system; + uint16_t current_system; + uint16_t usb_current_limit; +} __packed; + +/*****************************************************************************/ +/* I2C passthru command */ + +#define EC_CMD_I2C_PASSTHRU 0x9e + +/* Slave address is 10 (not 7) bit */ +#define EC_I2C_FLAG_10BIT (1 << 16) + +/* Read data; if not present, message is a write */ +#define EC_I2C_FLAG_READ (1 << 15) + +/* Mask for address */ +#define EC_I2C_ADDR_MASK 0x3ff + +#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ + +/* Any error */ +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) + +struct ec_params_i2c_passthru_msg { + uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ + uint16_t len; /* Number of bytes to read or write */ +} __packed; + +struct ec_params_i2c_passthru { + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ + struct ec_params_i2c_passthru_msg msg[]; + /* Data to write for all messages is concatenated here */ +} __packed; + +struct ec_response_i2c_passthru { + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + uint8_t data[]; /* Data read by messages concatenated here */ +} __packed; + + /*****************************************************************************/ /* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */ @@ -1257,7 +1508,16 @@ struct ec_response_ldo_get { #define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1 struct ec_params_current_limit { - uint32_t limit; + uint32_t limit; /* in mA */ +} __packed; + +/* + * Set maximum external power current. + */ +#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2 + +struct ec_params_ext_power_current_limit { + uint32_t limit; /* in mA */ } __packed; /*****************************************************************************/ diff --git a/include/edid.h b/include/edid.h index f153091f64..18ec1d5ab0 100644 --- a/include/edid.h +++ b/include/edid.h @@ -54,7 +54,7 @@ struct edid_detailed_timing { (_x).vertical_blanking) unsigned char hsync_offset; unsigned char hsync_pulse_width; - unsigned char sync_offset_pulse_width; + unsigned char vsync_offset_pulse_width; unsigned char hsync_vsync_offset_pulse_width_hi; #define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \ ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \ @@ -86,6 +86,10 @@ struct edid_detailed_timing { GET_BITS((_x).flags, 4, 3) #define EDID_DETAILED_TIMING_FLAG_POLARITY(_x) \ GET_BITS((_x).flags, 2, 1) +#define EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(_x) \ + GET_BIT((_x).flags, 2) +#define EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(_x) \ + GET_BIT((_x).flags, 1) #define EDID_DETAILED_TIMING_FLAG_INTERLEAVED(_x) \ GET_BIT((_x).flags, 0) } __attribute__ ((__packed__)); @@ -226,6 +230,25 @@ struct edid1_info { unsigned char checksum; } __attribute__ ((__packed__)); +struct edid_cea861_info { + unsigned char extension_tag; +#define EDID_CEA861_EXTENSION_TAG 0x02 + unsigned char revision; + unsigned char dtd_offset; + unsigned char dtd_count; +#define EDID_CEA861_SUPPORTS_UNDERSCAN(_x) \ + GET_BIT(((_x).dtd_count), 7) +#define EDID_CEA861_SUPPORTS_BASIC_AUDIO(_x) \ + GET_BIT(((_x).dtd_count), 6) +#define EDID_CEA861_SUPPORTS_YUV444(_x) \ + GET_BIT(((_x).dtd_count), 5) +#define EDID_CEA861_SUPPORTS_YUV422(_x) \ + GET_BIT(((_x).dtd_count), 4) +#define EDID_CEA861_DTD_COUNT(_x) \ + GET_BITS(((_x).dtd_count), 3, 0) + unsigned char data[124]; +} __attribute__ ((__packed__)); + /** * Print the EDID info. * @@ -241,6 +264,15 @@ void edid_print_info(struct edid1_info *edid_info); */ int edid_check_info(struct edid1_info *info); +/** + * Check checksum of a 128 bytes EDID data block + * + * @param edid_block EDID block data + * + * @return 0 on success, or a negative errno on error + */ +int edid_check_checksum(u8 *edid_block); + /** * Get the horizontal and vertical rate ranges of the monitor. * diff --git a/include/elf.h b/include/elf.h index 29f276d3f0..63d93416a3 100644 --- a/include/elf.h +++ b/include/elf.h @@ -2,27 +2,7 @@ * Copyright (c) 1995, 1996, 2001, 2002 * Erik Theisen. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ /* @@ -590,4 +570,6 @@ unsigned long elf_hash(const unsigned char *name); that may still be in object files. */ #define R_PPC_TOC16 255 +int valid_elf_image(unsigned long addr); + #endif /* _ELF_H */ diff --git a/include/env_callback.h b/include/env_callback.h index f90a7fa3b6..ab4e115fb0 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -60,7 +60,7 @@ void env_callback_init(ENTRY *var_entry); */ #ifdef CONFIG_SPL_BUILD #define U_BOOT_ENV_CALLBACK(name, callback) \ - static inline void _u_boot_env_noop_##name(void) \ + static inline __maybe_unused void _u_boot_env_noop_##name(void) \ { \ (void)callback; \ } diff --git a/include/env_default.h b/include/env_default.h index a7010269d3..90431beb19 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -5,7 +5,7 @@ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH * Andreas Heppel * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/include/environment.h b/include/environment.h index 46a3554ff9..1fdbdad882 100644 --- a/include/environment.h +++ b/include/environment.h @@ -146,7 +146,12 @@ extern unsigned long nand_env_oob_offset; extern char *env_name_spec; #endif +#ifdef CONFIG_ENV_AES +/* Make sure the payload is multiple of AES block size */ +#define ENV_SIZE ((CONFIG_ENV_SIZE - ENV_HEADER_SIZE) & ~(16 - 1)) +#else #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) +#endif typedef struct environment_s { uint32_t crc; /* CRC32 over data bytes */ @@ -154,7 +159,12 @@ typedef struct environment_s { unsigned char flags; /* active/obsolete flags */ #endif unsigned char data[ENV_SIZE]; /* Environment data */ -} env_t; +} env_t +#ifdef CONFIG_ENV_AES +/* Make sure the env is aligned to block size. */ +__attribute__((aligned(16))) +#endif +; #ifdef ENV_IS_EMBEDDED extern env_t environment; @@ -170,6 +180,15 @@ extern unsigned char env_get_char_spec(int); extern void env_reloc(void); #endif +#ifdef CONFIG_ENV_IS_IN_MMC +#include + +extern int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); +# ifdef CONFIG_SYS_MMC_ENV_PART +extern uint mmc_get_env_part(struct mmc *mmc); +# endif +#endif + #ifndef DO_DEPS_ONLY #include @@ -201,6 +220,9 @@ int set_default_vars(int nvars, char * const vars[]); /* Import from binary representation into hash table */ int env_import(const char *buf, int check); +/* Export from hash table into binary representation */ +int env_export(env_t *env_out); + #endif /* DO_DEPS_ONLY */ #endif /* _ENVIRONMENT_H_ */ diff --git a/include/errno.h b/include/errno.h index e24a33b386..14ac3cb10b 100644 --- a/include/errno.h +++ b/include/errno.h @@ -6,4 +6,7 @@ extern int errno; #define __set_errno(val) do { errno = val; } while (0) +#ifdef CONFIG_ERRNO_STR +const char *errno_str(int errno); +#endif #endif /* _ERRNO_H */ diff --git a/include/exports.h b/include/exports.h index 41d5085e16..205affe72d 100644 --- a/include/exports.h +++ b/include/exports.h @@ -3,6 +3,8 @@ #ifndef __ASSEMBLY__ +struct spi_slave; + /* These are declarations of exported functions available in C code */ unsigned long get_version(void); int getc(void); @@ -10,22 +12,23 @@ int tstc(void); void putc(const char); void puts(const char*); int printf(const char* fmt, ...); -void install_hdlr(int, void (*interrupt_handler_t)(void *), void*); +void install_hdlr(int, interrupt_handler_t, void*); void free_hdlr(int); void *malloc(size_t); void free(void*); void __udelay(unsigned long); unsigned long get_timer(unsigned long); int vprintf(const char *, va_list); -unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); +unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); char *getenv (const char *name); int setenv (const char *varname, const char *varvalue); -long simple_strtol(const char *cp,char **endp,unsigned int base); -int strcmp(const char * cs,const char * ct); +long simple_strtol(const char *cp, char **endp, unsigned int base); +int strcmp(const char *cs, const char *ct); unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); -#if defined(CONFIG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) && \ + (!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT)) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); #endif @@ -34,15 +37,14 @@ void app_startup(char * const *); #endif /* ifndef __ASSEMBLY__ */ -enum { -#define EXPORT_FUNC(x) XF_ ## x , +struct jt_funcs { +#define EXPORT_FUNC(impl, res, func, ...) res(*func)(__VA_ARGS__); #include <_exports.h> #undef EXPORT_FUNC - - XF_MAX }; -#define XF_VERSION 6 + +#define XF_VERSION 7 #if defined(CONFIG_X86) extern gd_t *global_data; diff --git a/include/ext4fs.h b/include/ext4fs.h index 2429380396..6888adc56f 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -125,21 +125,28 @@ int ext4fs_init(void); void ext4fs_deinit(void); int ext4fs_filename_check(char *filename); int ext4fs_write(const char *fname, unsigned char *buffer, - unsigned long sizebytes); + unsigned long sizebytes); +int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actwrite); #endif struct ext_filesystem *get_fs(void); -int ext4fs_open(const char *filename); -int ext4fs_read(char *buf, unsigned len); +int ext4fs_open(const char *filename, loff_t *len); +int ext4fs_read(char *buf, loff_t len, loff_t *actread); int ext4fs_mount(unsigned part_length); void ext4fs_close(void); +void ext4fs_reinit_global(void); int ext4fs_ls(const char *dirname); +int ext4fs_exists(const char *filename); +int ext4fs_size(const char *filename, loff_t *size); void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf); void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); long int read_allocated_block(struct ext2_inode *inode, int fileblock); int ext4fs_probe(block_dev_desc_t *fs_dev_desc, disk_partition_t *fs_partition); -int ext4_read_file(const char *filename, void *buf, int offset, int len); +int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); int ext4_read_superblock(char *buffer); +int ext4fs_uuid(char *uuid_str); #endif diff --git a/include/fat.h b/include/fat.h index 2c951e7d79..3038bd7e4f 100644 --- a/include/fat.h +++ b/include/fat.h @@ -18,7 +18,11 @@ #define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */ #define PREFETCH_BLOCKS 2 -#define MAX_CLUSTSIZE 65536 +#ifndef CONFIG_FS_FAT_MAX_CLUSTSIZE +#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536 +#endif +#define MAX_CLUSTSIZE CONFIG_FS_FAT_MAX_CLUSTSIZE + #define DIRENTSPERBLOCK (mydata->sect_size / sizeof(dir_entry)) #define DIRENTSPERCLUST ((mydata->clust_size * mydata->sect_size) / \ sizeof(dir_entry)) @@ -84,8 +88,13 @@ #define START(dent) (FAT2CPU16((dent)->start) \ + (mydata->fatsize != 32 ? 0 : \ (FAT2CPU16((dent)->starthi) << 16))) +#define IS_LAST_CLUST(x, fatsize) ((x) >= ((fatsize) != 32 ? \ + ((fatsize) != 16 ? 0xff8 : 0xfff8) : \ + 0xffffff8)) #define CHECK_CLUST(x, fatsize) ((x) <= 1 || \ - (x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0)) + (x) >= ((fatsize) != 32 ? \ + ((fatsize) != 16 ? 0xff0 : 0xfff0) : \ + 0xffffff0)) typedef struct boot_sector { __u8 ignored[3]; /* Bootstrap code */ @@ -169,8 +178,8 @@ typedef struct { typedef int (file_detectfs_func)(void); typedef int (file_ls_func)(const char *dir); -typedef long (file_read_func)(const char *filename, void *buffer, - unsigned long maxsize); +typedef int (file_read_func)(const char *filename, void *buffer, + int maxsize); struct filesystem { file_detectfs_func *detect; @@ -188,14 +197,18 @@ file_read_func file_fat_read; int file_cd(const char *path); int file_fat_detectfs(void); int file_fat_ls(const char *dir); -long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, - unsigned long maxsize); -long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); +int fat_exists(const char *filename); +int fat_size(const char *filename, loff_t *size); +int file_fat_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread); +int file_fat_read(const char *filename, void *buffer, int maxsize); const char *file_getfsname(int idx); int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); int fat_register_device(block_dev_desc_t *dev_desc, int part_no); -int file_fat_write(const char *filename, void *buffer, unsigned long maxsize); -int fat_read_file(const char *filename, void *buf, int offset, int len); +int file_fat_write(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actwrite); +int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); void fat_close(void); #endif /* _FAT_H_ */ diff --git a/include/fb_mmc.h b/include/fb_mmc.h new file mode 100644 index 0000000000..1ad1d1327d --- /dev/null +++ b/include/fb_mmc.h @@ -0,0 +1,8 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void fb_mmc_flash_write(const char *cmd, void *download_buffer, + unsigned int download_bytes, char *response); diff --git a/include/fdc.h b/include/fdc.h deleted file mode 100644 index 207b0e2667..0000000000 --- a/include/fdc.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FDC_H_ -#define _FDC_H_ - -/* Functions prototype */ -int fdc_fdos_init (int drive); -int fdc_fdos_seek (int where); -int fdc_fdos_read (void *buffer, int len); - -int dos_open(char *name); -int dos_read (ulong addr); -int dos_dir (void); - -#endif diff --git a/include/fdt_support.h b/include/fdt_support.h index 9871e2f81a..2309f75583 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -12,14 +12,16 @@ #include -u32 fdt_getprop_u32_default(const void *fdt, const char *path, - const char *prop, const u32 dflt); -int fdt_chosen(void *fdt, int force); -int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force); +uint32_t fdt_getprop_u32_default_node(const void *fdt, int off, int cell, + const char *prop, const uint32_t dflt); +uint32_t fdt_getprop_u32_default(const void *fdt, const char *path, + const char *prop, const uint32_t dflt); +int fdt_chosen(void *fdt); +int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end); void do_fixup_by_path(void *fdt, const char *path, const char *prop, const void *val, int len, int create); void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop, - u32 val, int create); + uint32_t val, int create); static inline void do_fixup_by_path_string(void *fdt, const char *path, const char *prop, const char *status) @@ -33,18 +35,19 @@ void do_fixup_by_prop(void *fdt, int create); void do_fixup_by_prop_u32(void *fdt, const char *pname, const void *pval, int plen, - const char *prop, u32 val, int create); + const char *prop, uint32_t val, int create); void do_fixup_by_compat(void *fdt, const char *compat, const char *prop, const void *val, int len, int create); void do_fixup_by_compat_u32(void *fdt, const char *compat, - const char *prop, u32 val, int create); -int fdt_fixup_memory(void *blob, u64 start, u64 size); -int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks); + const char *prop, uint32_t val, int create); +int fdt_fixup_memory(void *blob, uint64_t start, uint64_t size); +int fdt_fixup_memory_banks(void *blob, uint64_t start[], uint64_t size[], int banks); void fdt_fixup_ethernet(void *fdt); int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, const void *val, int len, int create); void fdt_fixup_qe_firmware(void *fdt); +#if defined(__UBOOT__) #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) void fdt_fixup_dr_usb(void *blob, bd_t *bd); #else @@ -62,19 +65,51 @@ static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose); #endif -void ft_board_setup(void *blob, bd_t *bd); +int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * Add board-specific data to the FDT before booting the OS. + * + * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space. + * This function is called if CONFIG_OF_BOARD_SETUP is defined + * + * @param blob FDT blob to update + * @param bd_t Pointer to board data + * @return 0 if ok, or -FDT_ERR_... on error + */ +int ft_board_setup(void *blob, bd_t *bd); + +/* + * The keystone2 SOC requires all 32 bit aliased addresses to be converted + * to their 36 physical format. This has to happen after all fdt nodes + * are added or modified by the image_setup_libfdt(). The ft_board_setup_ex() + * called at the end of the image_setup_libfdt() is to do that convertion. + */ +void ft_board_setup_ex(void *blob, bd_t *bd); void ft_cpu_setup(void *blob, bd_t *bd); void ft_pci_setup(void *blob, bd_t *bd); +/** + * Add system-specific data to the FDT before booting the OS. + * + * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space. + * This function is called if CONFIG_OF_SYSTEM_SETUP is defined + * + * @param blob FDT blob to update + * @param bd_t Pointer to board data + * @return 0 if ok, or -FDT_ERR_... on error + */ +int ft_system_setup(void *blob, bd_t *bd); + void set_working_fdt_addr(void *addr); -int fdt_resize(void *blob); +int fdt_shrink_to_minimum(void *blob); int fdt_increase_size(void *fdt, int add_len); int fdt_fixup_nor_flash_size(void *blob); void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); void fdt_del_node_and_alias(void *blob, const char *alias); -u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr); +uint64_t fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); int fdt_alloc_phandle(void *blob); @@ -83,8 +118,11 @@ unsigned int fdt_create_phandle(void *fdt, int nodeoffset); int fdt_add_edid(void *blob, const char *compat, unsigned char *buf); int fdt_verify_alias_address(void *fdt, int anode, const char *alias, - u64 addr); -u64 fdt_get_base_address(void *fdt, int node); + uint64_t addr); +uint64_t fdt_get_base_address(void *fdt, int node); +int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr, + uint64_t *addr, uint64_t *len); +#endif /* __UBOOT__ */ enum fdt_status { FDT_STATUS_OKAY, @@ -102,17 +140,50 @@ static inline int fdt_status_disabled(void *fdt, int nodeoffset) { return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0); } +static inline int fdt_status_fail(void *fdt, int nodeoffset) +{ + return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_FAIL, 0); +} -int fdt_set_status_by_alias(void *fdt, const char* alias, +int fdt_set_status_by_alias(void *fdt, const char *alias, enum fdt_status status, unsigned int error_code); -static inline int fdt_status_okay_by_alias(void *fdt, const char* alias) +static inline int fdt_status_okay_by_alias(void *fdt, const char *alias) { return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0); } -static inline int fdt_status_disabled_by_alias(void *fdt, const char* alias) +static inline int fdt_status_disabled_by_alias(void *fdt, const char *alias) { return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0); } +static inline int fdt_status_fail_by_alias(void *fdt, const char *alias) +{ + return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_FAIL, 0); +} + +/* Helper to read a big number; size is in cells (not bytes) */ +static inline uint64_t of_read_number(const fdt32_t *cell, int size) +{ + uint64_t r = 0; + + while (size--) { + r = (r << 32) | fdt32_to_cpu(*cell); + cell++; + } + return r; +} + +void of_bus_default_count_cells(void *blob, int parentoffset, + int *addrc, int *sizec); +int ft_verify_fdt(void *fdt); +int arch_fixup_memory_node(void *blob); + +int fdt_setup_simplefb_node(void *fdt, int node, uint64_t base_address, uint32_t width, + uint32_t height, uint32_t stride, const char *format); #endif /* ifdef CONFIG_OF_LIBFDT */ + +#ifdef USE_HOSTCC +int fdtdec_get_int(const void *blob, int node, const char *prop_name, + int default_val); +#endif #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 6bf83bf7c1..231eed7892 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -15,6 +15,7 @@ */ #include +#include /* * A typedef for a physical address. Note that fdt data is always big @@ -40,6 +41,70 @@ struct fdt_memory { fdt_addr_t end; }; +/* + * Information about a resource. start is the first address of the resource + * and end is the last address (inclusive). The length of the resource will + * be equal to: end - start + 1. + */ +struct fdt_resource { + fdt_addr_t start; + fdt_addr_t end; +}; + +enum fdt_pci_space { + FDT_PCI_SPACE_CONFIG = 0, + FDT_PCI_SPACE_IO = 0x01000000, + FDT_PCI_SPACE_MEM32 = 0x02000000, + FDT_PCI_SPACE_MEM64 = 0x03000000, + FDT_PCI_SPACE_MEM32_PREF = 0x42000000, + FDT_PCI_SPACE_MEM64_PREF = 0x43000000, +}; + +#define FDT_PCI_ADDR_CELLS 3 +#define FDT_PCI_SIZE_CELLS 2 +#define FDT_PCI_REG_SIZE \ + ((FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS) * sizeof(u32)) + +/* + * The Open Firmware spec defines PCI physical address as follows: + * + * bits# 31 .... 24 23 .... 16 15 .... 08 07 .... 00 + * + * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr + * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh + * phys.lo cell: llllllll llllllll llllllll llllllll + * + * where: + * + * n: is 0 if the address is relocatable, 1 otherwise + * p: is 1 if addressable region is prefetchable, 0 otherwise + * t: is 1 if the address is aliased (for non-relocatable I/O) below 1MB + * (for Memory), or below 64KB (for relocatable I/O) + * ss: is the space code, denoting the address space + * bbbbbbbb: is the 8-bit Bus Number + * ddddd: is the 5-bit Device Number + * fff: is the 3-bit Function Number + * rrrrrrrr: is the 8-bit Register Number + * hhhhhhhh: is a 32-bit unsigned number + * llllllll: is a 32-bit unsigned number + */ +struct fdt_pci_addr { + u32 phys_hi; + u32 phys_mid; + u32 phys_lo; +}; + +/** + * Compute the size of a resource. + * + * @param res the resource to operate on + * @return the size of the resource + */ +static inline fdt_size_t fdt_resource_size(const struct fdt_resource *res) +{ + return res->end - res->start + 1; +} + /** * Compat types that we know about and for which we might have drivers. * Each is named COMPAT__ where is the directory @@ -50,34 +115,37 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */ COMPAT_NVIDIA_TEGRA30_USB, /* Tegra30 USB port */ COMPAT_NVIDIA_TEGRA114_USB, /* Tegra114 USB port */ - COMPAT_NVIDIA_TEGRA114_I2C, /* Tegra114 I2C w/single clock source */ - COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra20 i2c */ - COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra20 dvc (really just i2c) */ COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */ COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ - COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ - COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */ - COMPAT_NVIDIA_TEGRA114_SPI, /* Tegra 114 SPI controller */ + COMPAT_NVIDIA_TEGRA124_PCIE, /* Tegra 124 PCIe controller */ + COMPAT_NVIDIA_TEGRA30_PCIE, /* Tegra 30 PCIe controller */ + COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */ + COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, + /* Tegra124 XUSB pad controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ - COMPAT_SAMSUNG_EXYNOS_SPI, /* Exynos SPI */ COMPAT_GOOGLE_CROS_EC, /* Google CROS_EC Protocol */ COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */ COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */ + COMPAT_SAMSUNG_EXYNOS5_XHCI, /* Exynos5 XHCI controller */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ + COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */ + COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ - COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */ + COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ + COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ @@ -85,42 +153,76 @@ enum fdt_compat_id { COMPAT_INFINEON_SLB9635_TPM, /* Infineon SLB9635 TPM */ COMPAT_INFINEON_SLB9645_TPM, /* Infineon SLB9645 TPM */ COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ + COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */ + COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ + COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */ + COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ + COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ + COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ + COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ + COMPAT_INTEL_MICROCODE, /* Intel microcode update */ + COMPAT_MEMORY_SPD, /* Memory SPD information */ + COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ + COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */ + COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ + COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ + COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_COUNT, }; -/* GPIOs are numbered from 0 */ -enum { - FDT_GPIO_NONE = -1U, /* an invalid GPIO used to end our list */ - - FDT_GPIO_ACTIVE_LOW = 1 << 0, /* input is active low (else high) */ -}; - -/* This is the state of a GPIO pin as defined by the fdt */ -struct fdt_gpio_state { - const char *name; /* name of the fdt property defining this */ - uint gpio; /* GPIO number, or FDT_GPIO_NONE if none */ - u8 flags; /* FDT_GPIO_... flags */ +#define MAX_PHANDLE_ARGS 16 +struct fdtdec_phandle_args { + int node; + int args_count; + uint32_t args[MAX_PHANDLE_ARGS]; }; -/* This tells us whether a fdt_gpio_state record is valid or not */ -#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE) - /** - * Read the GPIO taking into account the polarity of the pin. + * fdtdec_parse_phandle_with_args() - Find a node pointed by phandle in a list * - * @param gpio pointer to the decoded gpio - * @return value of the gpio if successful, < 0 if unsuccessful - */ -int fdtdec_get_gpio(struct fdt_gpio_state *gpio); - -/** - * Write the GPIO taking into account the polarity of the pin. + * This function is useful to parse lists of phandles and their arguments. + * + * Example: + * + * phandle1: node1 { + * #list-cells = <2>; + * } + * + * phandle2: node2 { + * #list-cells = <1>; + * } + * + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * } + * + * To get a device_node of the `node2' node you may call this: + * fdtdec_parse_phandle_with_args(blob, node3, "list", "#list-cells", 0, 1, + * &args); + * + * (This function is a modified version of __of_parse_phandle_with_args() from + * Linux 3.18) + * + * @blob: Pointer to device tree + * @src_node: Offset of device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies the phandles' arguments count, + * or NULL to use @cells_count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, a phandle was not found, @cells_name + * could not be found, the arguments were truncated or there were too + * many arguments. * - * @param gpio pointer to the decoded gpio - * @return 0 if successful */ -int fdtdec_set_gpio(struct fdt_gpio_state *gpio, int val); +int fdtdec_parse_phandle_with_args(const void *blob, int src_node, + const char *list_name, + const char *cells_name, + int cell_count, int index, + struct fdtdec_phandle_args *out_args); /** * Find the next numbered alias for a peripheral. This is used to enumerate @@ -213,6 +315,60 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node, fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, const char *prop_name, fdt_size_t *sizep); +/** + * Look at an address property in a node and return the pci address which + * corresponds to the given type in the form of fdt_pci_addr. + * The property must hold one fdt_pci_addr with a lengh. + * + * @param blob FDT blob + * @param node node to examine + * @param type pci address type (FDT_PCI_SPACE_xxx) + * @param prop_name name of property to find + * @param addr returns pci address in the form of fdt_pci_addr + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type, + const char *prop_name, struct fdt_pci_addr *addr); + +/** + * Look at the compatible property of a device node that represents a PCI + * device and extract pci vendor id and device id from it. + * + * @param blob FDT blob + * @param node node to examine + * @param vendor vendor id of the pci device + * @param device device id of the pci device + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_vendev(const void *blob, int node, + u16 *vendor, u16 *device); + +/** + * Look at the pci address of a device node that represents a PCI device + * and parse the bus, device and function number from it. + * + * @param blob FDT blob + * @param node node to examine + * @param addr pci address in the form of fdt_pci_addr + * @param bdf returns bus, device, function triplet + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_bdf(const void *blob, int node, + struct fdt_pci_addr *addr, pci_dev_t *bdf); + +/** + * Look at the pci address of a device node that represents a PCI device + * and return base address of the pci device's registers. + * + * @param blob FDT blob + * @param node node to examine + * @param addr pci address in the form of fdt_pci_addr + * @param bar returns base address of the pci device's registers + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_bar32(const void *blob, int node, + struct fdt_pci_addr *addr, u32 *bar); + /** * Look up a 32-bit integer property in a node and return it. The property * must have at least 4 bytes of data. The value of the first cell is @@ -336,6 +492,36 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, int fdtdec_add_aliases_for_id(const void *blob, const char *name, enum fdt_compat_id id, int *node_list, int maxcount); +/** + * Get the alias sequence number of a node + * + * This works out whether a node is pointed to by an alias, and if so, the + * sequence number of that alias. Aliases are of the form where + * is the sequence number. For example spi2 would be sequence number + * 2. + * + * @param blob Device tree blob (if NULL, then error is returned) + * @param base Base name for alias (before the underscore) + * @param node Node to look up + * @param seqp This is set to the sequence number if one is found, + * but otherwise the value is left alone + * @return 0 if a sequence was found, -ve if not + */ +int fdtdec_get_alias_seq(const void *blob, const char *base, int node, + int *seqp); + +/** + * Get the offset of the given chosen node + * + * This looks up a property in /chosen containing the path to another node, + * then finds the offset of that node. + * + * @param blob Device tree blob (if NULL, then error is returned) + * @param name Property name, e.g. "stdout-path" + * @return Node offset referred to by that chosen node, or -ve FDT_ERR_... + */ +int fdtdec_get_chosen_node(const void *blob, const char *name); + /* * Get the name for a compatible ID * @@ -370,6 +556,22 @@ int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name); int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, u32 *array, int count); +/** + * Look up a property in a node and return its contents in an integer + * array of given length. The property must exist but may have less data that + * expected (4*count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return number of array elements if ok, or -FDT_ERR_NOTFOUND if the + * property is not found + */ +int fdtdec_get_int_array_count(const void *blob, int node, + const char *prop_name, u32 *array, int count); + /** * Look up a property in a node and return a pointer to its contents as a * unsigned int array of given length. The property must have at least enough @@ -402,50 +604,6 @@ const u32 *fdtdec_locate_array(const void *blob, int node, */ int fdtdec_get_bool(const void *blob, int node, const char *prop_name); -/** - * Decode a single GPIOs from an FDT. - * - * If the property is not found, then the GPIO structure will still be - * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to - * provide optional GPIOs. - * - * @param blob FDT blob to use - * @param node Node to look at - * @param prop_name Node property name - * @param gpio gpio elements to fill from FDT - * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing. - */ -int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, - struct fdt_gpio_state *gpio); - -/** - * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no - * terminating item. - * - * @param blob FDT blob to use - * @param node Node to look at - * @param prop_name Node property name - * @param gpio Array of gpio elements to fill from FDT. This will be - * untouched if either 0 or an error is returned - * @param max_count Maximum number of elements allowed - * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would - * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing. - */ -int fdtdec_decode_gpios(const void *blob, int node, const char *prop_name, - struct fdt_gpio_state *gpio, int max_count); - -/** - * Set up a GPIO pin according to the provided gpio information. At present this - * just requests the GPIO. - * - * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to - * deal with optional GPIOs. - * - * @param gpio GPIO info to use for set up - * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error - */ -int fdtdec_setup_gpio(struct fdt_gpio_state *gpio); - /** * Look in the FDT for a config item with the given name and return its value * as a 32-bit integer. The property must have at least 4 bytes of data. The @@ -521,10 +679,102 @@ const u8 *fdtdec_locate_byte_array(const void *blob, int node, * @param blob FDT blob * @param node node to examine * @param prop_name name of property to find - * @param ptrp returns pointer to region, or NULL if no address - * @param size returns size of region - * @return 0 if ok, -1 on error (propery not found) + * @param basep Returns base address of region + * @param size Returns size of region + * @return 0 if ok, -1 on error (property not found) */ -int fdtdec_decode_region(const void *blob, int node, - const char *prop_name, void **ptrp, size_t *size); +int fdtdec_decode_region(const void *blob, int node, const char *prop_name, + fdt_addr_t *basep, fdt_size_t *sizep); + +enum fmap_compress_t { + FMAP_COMPRESS_NONE, + FMAP_COMPRESS_LZO, +}; + +enum fmap_hash_t { + FMAP_HASH_NONE, + FMAP_HASH_SHA1, + FMAP_HASH_SHA256, +}; + +/* A flash map entry, containing an offset and length */ +struct fmap_entry { + uint32_t offset; + uint32_t length; + uint32_t used; /* Number of bytes used in region */ + enum fmap_compress_t compress_algo; /* Compression type */ + enum fmap_hash_t hash_algo; /* Hash algorithm */ + const uint8_t *hash; /* Hash value */ + int hash_size; /* Hash size */ +}; + +/** + * Read a flash entry from the fdt + * + * @param blob FDT blob + * @param node Offset of node to read + * @param name Name of node being read + * @param entry Place to put offset and size of this node + * @return 0 if ok, -ve on error + */ +int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, + struct fmap_entry *entry); + +/** + * Obtain an indexed resource from a device property. + * + * @param fdt FDT blob + * @param node node to examine + * @param property name of the property to parse + * @param index index of the resource to retrieve + * @param res returns the resource + * @return 0 if ok, negative on error + */ +int fdt_get_resource(const void *fdt, int node, const char *property, + unsigned int index, struct fdt_resource *res); + +/** + * Obtain a named resource from a device property. + * + * Look up the index of the name in a list of strings and return the resource + * at that index. + * + * @param fdt FDT blob + * @param node node to examine + * @param property name of the property to parse + * @param prop_names name of the property containing the list of names + * @param name the name of the entry to look up + * @param res returns the resource + */ +int fdt_get_named_resource(const void *fdt, int node, const char *property, + const char *prop_names, const char *name, + struct fdt_resource *res); + +/** + * Decode a named region within a memory bank of a given type. + * + * This function handles selection of a memory region. The region is + * specified as an offset/size within a particular type of memory. + * + * The properties used are: + * + * -memory for the name of the memory bank + * -offset for the offset in that bank + * + * The property value must have an offset and a size. The function checks + * that the region is entirely within the memory bank.5 + * + * @param blob FDT blob + * @param node Node containing the properties (-1 for /config) + * @param mem_type Type of memory to use, which is a name, such as + * "u-boot" or "kernel". + * @param suffix String to append to the memory/offset + * property names + * @param basep Returns base of region + * @param sizep Returns size of region + * @return 0 if OK, -ive on error + */ +int fdtdec_decode_memory_region(const void *blob, int node, + const char *mem_type, const char *suffix, + fdt_addr_t *basep, fdt_size_t *sizep); #endif diff --git a/include/flash.h b/include/flash.h index 77f8b7e47a..30aa080b88 100644 --- a/include/flash.h +++ b/include/flash.h @@ -2,7 +2,7 @@ * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _FLASH_H_ @@ -158,6 +158,7 @@ extern flash_info_t *flash_get_info(ulong base); #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ #define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ #define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ +#define EON_ALT_MANU 0x001C001C /* EON manuf. ID in D23..D16, D7..D0 */ /* Manufacturers inside bank 1 have ids like 0x01xx01xx */ #define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ diff --git a/include/fm_eth.h b/include/fm_eth.h index 90562dc9f0..3e1b9f4281 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -8,8 +8,8 @@ #define __FM_ETH_H__ #include +#include #include -#include enum fm_port { FM1_DTSEC1, @@ -22,6 +22,8 @@ enum fm_port { FM1_DTSEC10, FM1_10GEC1, FM1_10GEC2, + FM1_10GEC3, + FM1_10GEC4, FM2_DTSEC1, FM2_DTSEC2, FM2_DTSEC3, @@ -73,6 +75,20 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } +#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1]),\ +} +#else #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -85,6 +101,23 @@ enum fm_eth_type { .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1+8]),\ } +#endif + +#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#define FM_TGEC_INFO_INITIALIZER2(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \ + .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1-2]),\ +} +#endif + #else #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ { \ @@ -149,5 +182,10 @@ void fm_info_set_phy_address(enum fm_port port, int address); int fm_info_get_phy_address(enum fm_port port); void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); void fm_disable_port(enum fm_port port); +void fm_enable_port(enum fm_port port); +void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port, + unsigned int port_num, int phy_base_addr); +int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr, + unsigned int port_num, unsigned regnum); #endif diff --git a/include/fpga.h b/include/fpga.h index 15e603a169..e0d12981b2 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -35,16 +35,33 @@ typedef struct { /* typedef fpga_desc */ void *devdesc; /* real device descriptor */ } fpga_desc; /* end, typedef fpga_desc */ +typedef struct { /* typedef fpga_desc */ + unsigned int blocksize; + char *interface; + char *dev_part; + char *filename; + int fstype; +} fpga_fs_info; + +typedef enum { + BIT_FULL = 0, + BIT_PARTIAL, +} bitstream_type; /* root function definitions */ -extern void fpga_init(void); -extern int fpga_add(fpga_type devtype, void *desc); -extern int fpga_count(void); -extern int fpga_load(int devnum, const void *buf, size_t bsize); -extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size); -extern int fpga_dump(int devnum, const void *buf, size_t bsize); -extern int fpga_info(int devnum); -extern const fpga_desc *const fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn); +void fpga_init(void); +int fpga_add(fpga_type devtype, void *desc); +int fpga_count(void); +const fpga_desc *const fpga_get_desc(int devnum); +int fpga_load(int devnum, const void *buf, size_t bsize, + bitstream_type bstype); +int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo); +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype); +int fpga_dump(int devnum, const void *buf, size_t bsize); +int fpga_info(int devnum); +const fpga_desc *const fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn); #endif /* _FPGA_H_ */ diff --git a/include/fs.h b/include/fs.h index c837bae25c..fd1e4ab1c0 100644 --- a/include/fs.h +++ b/include/fs.h @@ -44,25 +44,75 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype); int fs_ls(const char *dirname); /* - * Read file "filename" from the partition previously set by fs_set_blk_dev(), - * to address "addr", starting at byte offset "offset", and reading "len" - * bytes. "offset" may be 0 to read from the start of the file. "len" may be - * 0 to read the entire file. Note that not all filesystem types support - * either/both offset!=0 or len!=0. + * Determine whether a file exists * - * Returns number of bytes read on success. Returns <= 0 on error. + * Returns 1 if the file exists, 0 if it doesn't exist. */ -int fs_read(const char *filename, ulong addr, int offset, int len); +int fs_exists(const char *filename); + +/* + * fs_size - Determine a file's size + * + * @filename: Name of the file + * @size: Size of file + * @return 0 if ok with valid *size, negative on error + */ +int fs_size(const char *filename, loff_t *size); + +/* + * fs_read - Read file from the partition previously set by fs_set_blk_dev() + * Note that not all filesystem types support either/both offset!=0 or len!=0. + * + * @filename: Name of file to read from + * @addr: The address to read into + * @offset: The offset in file to read from + * @len: The number of bytes to read. Maybe 0 to read entire file + * @actread: Returns the actual number of bytes read + * @return 0 if ok with valid *actread, -1 on error conditions + */ +int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actread); + +/* + * fs_write - Write file to the partition previously set by fs_set_blk_dev() + * Note that not all filesystem types support offset!=0. + * + * @filename: Name of file to read from + * @addr: The address to read into + * @offset: The offset in file to read from. Maybe 0 to write to start of file + * @len: The number of bytes to write + * @actwrite: Returns the actual number of bytes written + * @return 0 if ok with valid *actwrite, -1 on error conditions + */ +int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actwrite); /* * Common implementation for various filesystem commands, optionally limited * to a specific filesystem type via the fstype parameter. */ +int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype); int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - int fstype, int cmdline_base); + int fstype); int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); +int file_exists(const char *dev_type, const char *dev_part, const char *file, + int fstype); int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - int fstype, int cmdline_base); + int fstype); + +/* + * Determine the UUID of the specified filesystem and print it. Optionally it is + * possible to store the UUID directly in env. + */ +int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype); + +/* + * Determine the type of the specified filesystem and print it. Optionally it is + * possible to store the type directly in env. + */ +int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif /* _FS_H */ diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h new file mode 100644 index 0000000000..42632984d3 --- /dev/null +++ b/include/fsl_dcu_fb.h @@ -0,0 +1,16 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + +int fsl_dcu_init(unsigned int xres, unsigned int yres, + unsigned int pixel_format); + +/* Prototypes for external board-specific functions */ +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, struct fb_videomode *dcu_fb_videomode); +unsigned int dcu_set_pixel_clock(unsigned int pixclock); diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h new file mode 100644 index 0000000000..3286c95907 --- /dev/null +++ b/include/fsl_ddr.h @@ -0,0 +1,136 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef FSL_DDR_MAIN_H +#define FSL_DDR_MAIN_H + +#include +#include +#include + +#include + +#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS +/* All controllers are for main memory */ +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS +#endif + +#ifdef CONFIG_SYS_FSL_DDR_LE +#define ddr_in32(a) in_le32(a) +#define ddr_out32(a, v) out_le32(a, v) +#define ddr_setbits32(a, v) setbits_le32(a, v) +#define ddr_clrbits32(a, v) clrbits_le32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) +#else +#define ddr_in32(a) in_be32(a) +#define ddr_out32(a, v) out_be32(a, v) +#define ddr_setbits32(a, v) setbits_be32(a, v) +#define ddr_clrbits32(a, v) clrbits_be32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) +#endif + +#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR + +u32 fsl_ddr_get_version(void); + +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) +/* + * Bind the main DDR setup driver's generic names + * to this specific DDR technology. + */ +static __inline__ int +compute_dimm_parameters(const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); +} +#endif + +/* + * Data Structures + * + * All data structures have to be on the stack + */ +#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR + +typedef struct { + generic_spd_eeprom_t + spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + struct dimm_params_s + dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; + common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; + fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; + unsigned int first_ctrl; + unsigned int num_ctrls; + unsigned long long mem_base; + unsigned int dimm_slots_per_ctrl; + int (*board_need_mem_reset)(void); + void (*board_mem_reset)(void); + void (*board_mem_de_reset)(void); +} fsl_ddr_info_t; + +/* Compute steps */ +#define STEP_GET_SPD (1 << 0) +#define STEP_COMPUTE_DIMM_PARMS (1 << 1) +#define STEP_COMPUTE_COMMON_PARMS (1 << 2) +#define STEP_GATHER_OPTS (1 << 3) +#define STEP_ASSIGN_ADDRESSES (1 << 4) +#define STEP_COMPUTE_REGS (1 << 5) +#define STEP_PROGRAM_REGS (1 << 6) +#define STEP_ALL 0xFFF + +unsigned long long +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only); +const char *step_to_string(unsigned int step); + +unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm, + const dimm_params_t *dimm_parameters, + unsigned int dbw_capacity_adjust, + unsigned int size_only); +unsigned int compute_lowest_common_dimm_parameters( + const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms); +unsigned int populate_memctl_options(int all_dimms_registered, + memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num); +void check_interleaving_options(fsl_ddr_info_t *pinfo); + +unsigned int mclk_to_picos(unsigned int mclk); +unsigned int get_memory_clk_period_ps(void); +unsigned int picos_to_mclk(unsigned int picos); +void fsl_ddr_set_lawbar( + const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); + +int fsl_ddr_interactive_env_var_exists(void); +unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); +void board_add_ram_info(int use_default); + +/* processor specific function */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step); + +/* board specific function */ +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number); +#endif diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h new file mode 100644 index 0000000000..09a67a6802 --- /dev/null +++ b/include/fsl_ddr_dimm_params.h @@ -0,0 +1,120 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef DDR2_DIMM_PARAMS_H +#define DDR2_DIMM_PARAMS_H + +#define EDC_DATA_PARITY 1 +#define EDC_ECC 2 +#define EDC_AC_PARITY 4 + +/* Parameters for a DDR dimm computed from the SPD */ +typedef struct dimm_params_s { + + /* DIMM organization parameters */ + char mpart[19]; /* guaranteed null terminated */ + + unsigned int n_ranks; + unsigned long long rank_density; + unsigned long long capacity; + unsigned int data_width; + unsigned int primary_sdram_width; + unsigned int ec_sdram_width; + unsigned int registered_dimm; + unsigned int device_width; /* x4, x8, x16 components */ + + /* SDRAM device parameters */ + unsigned int n_row_addr; + unsigned int n_col_addr; + unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int bank_addr_bits; + unsigned int bank_group_bits; +#else + unsigned int n_banks_per_sdram_device; +#endif + unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ + unsigned int row_density; + + /* used in computing base address of DIMMs */ + unsigned long long base_address; + /* mirrored DIMMs */ + unsigned int mirrored_dimm; /* only for ddr3 */ + + /* DIMM timing parameters */ + + int mtb_ps; /* medium timebase ps */ + int ftb_10th_ps; /* fine timebase, in 1/10 ps */ + int taa_ps; /* minimum CAS latency time */ + int tfaw_ps; /* four active window delay */ + + /* + * SDRAM clock periods + * The range for these are 1000-10000 so a short should be sufficient + */ + int tckmin_x_ps; + int tckmin_x_minus_1_ps; + int tckmin_x_minus_2_ps; + int tckmax_ps; + + /* SPD-defined CAS latencies */ + unsigned int caslat_x; + unsigned int caslat_x_minus_1; + unsigned int caslat_x_minus_2; + + unsigned int caslat_lowest_derated; /* Derated CAS latency */ + + /* basic timing parameters */ + int trcd_ps; + int trp_ps; + int tras_ps; + +#ifdef CONFIG_SYS_FSL_DDR4 + int trfc1_ps; + int trfc2_ps; + int trfc4_ps; + int trrds_ps; + int trrdl_ps; + int tccdl_ps; +#else + int twr_ps; /* maximum = 63750 ps */ + int trfc_ps; /* max = 255 ns + 256 ns + .75 ns + = 511750 ps */ + int trrd_ps; /* maximum = 63750 ps */ + int twtr_ps; /* maximum = 63750 ps */ + int trtp_ps; /* byte 38, spd->trtp */ +#endif + + int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + int refresh_rate_ps; + int extended_op_srt; + +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + int tis_ps; /* byte 32, spd->ca_setup */ + int tih_ps; /* byte 33, spd->ca_hold */ + int tds_ps; /* byte 34, spd->data_setup */ + int tdh_ps; /* byte 35, spd->data_hold */ + int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + int tqhs_ps; /* byte 45, spd->tqhs */ +#endif + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int dq_mapping[18]; + unsigned int dq_mapping_ors; +#endif +} dimm_params_t; + +extern unsigned int ddr_compute_dimm_parameters( + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number); + +#endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h new file mode 100644 index 0000000000..095b33e29e --- /dev/null +++ b/include/fsl_ddr_sdram.h @@ -0,0 +1,445 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef FSL_DDR_MEMCTL_H +#define FSL_DDR_MEMCTL_H + +/* + * Pick a basic DDR Technology. + */ +#include +#include + +#define SDRAM_TYPE_DDR1 2 +#define SDRAM_TYPE_DDR2 3 +#define SDRAM_TYPE_LPDDR1 6 +#define SDRAM_TYPE_DDR3 7 +#define SDRAM_TYPE_DDR4 5 + +#define DDR_BL4 4 /* burst length 4 */ +#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ +#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ +#define DDR_BL8 8 /* burst length 8 */ + +#define DDR3_RTT_OFF 0 +#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ +#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ +#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ +#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ +#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ + +#define DDR2_RTT_OFF 0 +#define DDR2_RTT_75_OHM 1 +#define DDR2_RTT_150_OHM 2 +#define DDR2_RTT_50_OHM 3 + +#if defined(CONFIG_SYS_FSL_DDR1) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) +typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 +#endif +#elif defined(CONFIG_SYS_FSL_DDR2) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) +typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 +#endif +#elif defined(CONFIG_SYS_FSL_DDR3) +typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 +#endif +#elif defined(CONFIG_SYS_FSL_DDR4) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ +typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4 +#endif +#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ + +#define FSL_DDR_ODT_NEVER 0x0 +#define FSL_DDR_ODT_CS 0x1 +#define FSL_DDR_ODT_ALL_OTHER_CS 0x2 +#define FSL_DDR_ODT_OTHER_DIMM 0x3 +#define FSL_DDR_ODT_ALL 0x4 +#define FSL_DDR_ODT_SAME_DIMM 0x5 +#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 +#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 + +/* define bank(chip select) interleaving mode */ +#define FSL_DDR_CS0_CS1 0x40 +#define FSL_DDR_CS2_CS3 0x20 +#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) +#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) + +/* define memory controller interleaving mode */ +#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 +#define FSL_DDR_PAGE_INTERLEAVING 0x1 +#define FSL_DDR_BANK_INTERLEAVING 0x2 +#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_256B_INTERLEAVING 0x8 +#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA +#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC +#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD +/* placeholder for 4-way interleaving */ +#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A +#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C +#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D + +#define SDRAM_CS_CONFIG_EN 0x80000000 + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_SHIFT 19 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_16_BE 0x00100000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_BI 0x00000001 + +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 +#define SDRAM_CFG2_ODT_NEVER 0 +#define SDRAM_CFG2_ODT_ONLY_WRITE 1 +#define SDRAM_CFG2_ODT_ONLY_READ 2 +#define SDRAM_CFG2_ODT_ALWAYS 3 + +#define TIMING_CFG_2_CPO_MASK 0x0F800000 + +#if defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4) +#define RD_TO_PRE_MASK 0xf +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0xf +#define WR_DATA_DELAY_SHIFT 9 +#else +#define RD_TO_PRE_MASK 0x7 +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0x7 +#define WR_DATA_DELAY_SHIFT 10 +#endif + +/* DDR_MD_CNTL */ +#define MD_CNTL_MD_EN 0x80000000 +#define MD_CNTL_CS_SEL_CS0 0x00000000 +#define MD_CNTL_CS_SEL_CS1 0x10000000 +#define MD_CNTL_CS_SEL_CS2 0x20000000 +#define MD_CNTL_CS_SEL_CS3 0x30000000 +#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 +#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 +#define MD_CNTL_MD_SEL_MR 0x00000000 +#define MD_CNTL_MD_SEL_EMR 0x01000000 +#define MD_CNTL_MD_SEL_EMR2 0x02000000 +#define MD_CNTL_MD_SEL_EMR3 0x03000000 +#define MD_CNTL_SET_REF 0x00800000 +#define MD_CNTL_SET_PRE 0x00400000 +#define MD_CNTL_CKE_CNTL_LOW 0x00100000 +#define MD_CNTL_CKE_CNTL_HIGH 0x00200000 +#define MD_CNTL_WRCW 0x00080000 +#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) + +/* DDR_CDR1 */ +#define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_ODT_SHIFT 17 +#define DDR_CDR1_ODT_MASK 0x6 +#define DDR_CDR2_ODT_MASK 0x1 +#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) +#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) +#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 + +#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#ifdef CONFIG_SYS_FSL_DDR3L +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_200ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x5 +#define DDR_CDR_ODT_46ohm 0x7 +#elif defined(CONFIG_SYS_FSL_DDR4) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_100ohm 0x1 +#define DDR_CDR_ODT_120OHM 0x2 +#define DDR_CDR_ODT_80ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x4 +#define DDR_CDR_ODT_40ohm 0x5 +#define DDR_CDR_ODT_50ohm 0x6 +#define DDR_CDR_ODT_30ohm 0x7 +#else +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_180ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_110ohm 0x4 +#define DDR_CDR_ODT_60hm 0x5 +#define DDR_CDR_ODT_70ohm 0x6 +#define DDR_CDR_ODT_47ohm 0x7 +#endif /* DDR3L */ +#else +#define DDR_CDR_ODT_75ohm 0x0 +#define DDR_CDR_ODT_55ohm 0x1 +#define DDR_CDR_ODT_60ohm 0x2 +#define DDR_CDR_ODT_50ohm 0x3 +#define DDR_CDR_ODT_150ohm 0x4 +#define DDR_CDR_ODT_43ohm 0x5 +#define DDR_CDR_ODT_120ohm 0x6 +#endif + +#define DDR_INIT_ADDR_EXT_UIA (1 << 31) + +/* Record of register values computed */ +typedef struct fsl_ddr_cfg_regs_s { + struct { + unsigned int bnds; + unsigned int config; + unsigned int config_2; + } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; + unsigned int timing_cfg_3; + unsigned int timing_cfg_0; + unsigned int timing_cfg_1; + unsigned int timing_cfg_2; + unsigned int ddr_sdram_cfg; + unsigned int ddr_sdram_cfg_2; + unsigned int ddr_sdram_cfg_3; + unsigned int ddr_sdram_mode; + unsigned int ddr_sdram_mode_2; + unsigned int ddr_sdram_mode_3; + unsigned int ddr_sdram_mode_4; + unsigned int ddr_sdram_mode_5; + unsigned int ddr_sdram_mode_6; + unsigned int ddr_sdram_mode_7; + unsigned int ddr_sdram_mode_8; + unsigned int ddr_sdram_mode_9; + unsigned int ddr_sdram_mode_10; + unsigned int ddr_sdram_mode_11; + unsigned int ddr_sdram_mode_12; + unsigned int ddr_sdram_mode_13; + unsigned int ddr_sdram_mode_14; + unsigned int ddr_sdram_mode_15; + unsigned int ddr_sdram_mode_16; + unsigned int ddr_sdram_md_cntl; + unsigned int ddr_sdram_interval; + unsigned int ddr_data_init; + unsigned int ddr_sdram_clk_cntl; + unsigned int ddr_init_addr; + unsigned int ddr_init_ext_addr; + unsigned int timing_cfg_4; + unsigned int timing_cfg_5; + unsigned int timing_cfg_6; + unsigned int timing_cfg_7; + unsigned int timing_cfg_8; + unsigned int timing_cfg_9; + unsigned int ddr_zq_cntl; + unsigned int ddr_wrlvl_cntl; + unsigned int ddr_wrlvl_cntl_2; + unsigned int ddr_wrlvl_cntl_3; + unsigned int ddr_sr_cntr; + unsigned int ddr_sdram_rcw_1; + unsigned int ddr_sdram_rcw_2; + unsigned int ddr_sdram_rcw_3; + unsigned int ddr_sdram_rcw_4; + unsigned int ddr_sdram_rcw_5; + unsigned int ddr_sdram_rcw_6; + unsigned int dq_map_0; + unsigned int dq_map_1; + unsigned int dq_map_2; + unsigned int dq_map_3; + unsigned int ddr_eor; + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + unsigned int err_disable; + unsigned int err_int_en; + unsigned int debug[32]; +} fsl_ddr_cfg_regs_t; + +typedef struct memctl_options_partial_s { + unsigned int all_dimms_ecc_capable; + unsigned int all_dimms_tckmax_ps; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + /* unsigned int lowest_common_spd_caslat; */ + unsigned int all_dimms_minimum_trcd_ps; +} memctl_options_partial_t; + +#define DDR_DATA_BUS_WIDTH_64 0 +#define DDR_DATA_BUS_WIDTH_32 1 +#define DDR_DATA_BUS_WIDTH_16 2 +#define DDR_CSWL_CS0 0x04000001 +/* + * Generalized parameters for memory controller configuration, + * might be a little specific to the FSL memory controller + */ +typedef struct memctl_options_s { + /* + * Memory organization parameters + * + * if DIMM is present in the system + * where DIMMs are with respect to chip select + * where chip selects are with respect to memory boundaries + */ + unsigned int registered_dimm_en; /* use registered DIMM support */ + + /* Options local to a Chip Select */ + struct cs_local_opts_s { + unsigned int auto_precharge; + unsigned int odt_rd_cfg; + unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; + } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; + + /* Special configurations for chip select */ + unsigned int memctl_interleaving; + unsigned int memctl_interleaving_mode; + unsigned int ba_intlv_ctl; + unsigned int addr_hash; + + /* Operational mode parameters */ + unsigned int ecc_mode; /* Use ECC? */ + /* Initialize ECC using memory controller? */ + unsigned int ecc_init_using_memctl; + unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ + /* SREN - self-refresh during sleep */ + unsigned int self_refresh_in_sleep; + unsigned int dynamic_power; /* DYN_PWR */ + /* memory data width to use (16-bit, 32-bit, 64-bit) */ + unsigned int data_bus_width; + unsigned int burst_length; /* BL4, OTF and BL8 */ + /* On-The-Fly Burst Chop enable */ + unsigned int otf_burst_chop_en; + /* mirrior DIMMs for DDR3 */ + unsigned int mirrored_dimm; + unsigned int quad_rank_present; + unsigned int ap_en; /* address parity enable for RDIMM */ + unsigned int x4_en; /* enable x4 devices */ + + /* Global Timing Parameters */ + unsigned int cas_latency_override; + unsigned int cas_latency_override_value; + unsigned int use_derated_caslat; + unsigned int additive_latency_override; + unsigned int additive_latency_override_value; + + unsigned int clk_adjust; /* */ + unsigned int cpo_override; + unsigned int write_data_delay; /* DQS adjust */ + + unsigned int cswl_override; + unsigned int wrlvl_override; + unsigned int wrlvl_sample; /* Write leveling */ + unsigned int wrlvl_start; + unsigned int wrlvl_ctl_2; + unsigned int wrlvl_ctl_3; + + unsigned int half_strength_driver_enable; + unsigned int twot_en; + unsigned int threet_en; + unsigned int bstopre; + unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + + /* Rtt impedance */ + unsigned int rtt_override; /* rtt_override enable */ + unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ + + /* Automatic self refresh */ + unsigned int auto_self_refresh_en; + unsigned int sr_it; + /* ZQ calibration */ + unsigned int zq_en; + /* Write leveling */ + unsigned int wrlvl_en; + /* RCW override for RDIMM */ + unsigned int rcw_override; + unsigned int rcw_1; + unsigned int rcw_2; + /* control register 1 */ + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + + unsigned int trwt_override; + unsigned int trwt; /* read-to-write turnaround */ +} memctl_options_t; + +phys_size_t fsl_ddr_sdram(void); +phys_size_t fsl_ddr_sdram_size(void); +phys_size_t fsl_other_ddr_sdram(unsigned long long base, + unsigned int first_ctrl, + unsigned int num_ctrls, + unsigned int dimm_slots_per_ctrl, + int (*board_need_reset)(void), + void (*board_reset)(void), + void (*board_de_reset)(void)); +extern int fsl_use_spd(void); +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step); +u32 fsl_ddr_get_intl3r(void); +void print_ddr_info(unsigned int start_ctrl); + +static void __board_assert_mem_reset(void) +{ +} + +static void __board_deassert_mem_reset(void) +{ +} + +void board_assert_mem_reset(void) + __attribute__((weak, alias("__board_assert_mem_reset"))); + +void board_deassert_mem_reset(void) + __attribute__((weak, alias("__board_deassert_mem_reset"))); + +static int __board_need_mem_reset(void) +{ + return 0; +} + +int board_need_mem_reset(void) + __attribute__((weak, alias("__board_need_mem_reset"))); + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void); +bool is_warm_boot(void); +int fsl_dp_resume(void); +#endif + +/* + * The 85xx boards have a common prototype for fixed_sdram so put the + * declaration here. + */ +#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + + +typedef struct fixed_ddr_parm{ + int min_freq; + int max_freq; + fsl_ddr_cfg_regs_t *ddr_settings; +} fixed_ddr_parm_t; +#endif diff --git a/include/fsl_ddrc_version.h b/include/fsl_ddrc_version.h new file mode 100644 index 0000000000..60ba98bf81 --- /dev/null +++ b/include/fsl_ddrc_version.h @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DDRC_VER_H +#define __FSL_DDRC_VER_H + +/* + * Only the versions with distinct features or registers are listed here. + */ +#define FSL_DDR_VER_4_4 44 +#define FSL_DDR_VER_4_6 46 +#define FSL_DDR_VER_4_7 47 +#define FSL_DDR_VER_5_0 50 + +#endif /* __FSL_DDRC_VER_H */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 0da20092f3..29bfe28801 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -14,6 +14,9 @@ #include #include +/* needed for the mmc_cfg definition */ +#include + /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 @@ -156,10 +159,23 @@ struct fsl_esdhc_cfg { void __iomem *esdhc_base; u32 sdhc_clk; u8 max_bus_width; + struct mmc_config cfg; }; /* Select the correct accessors depending on endianess */ -#if __BYTE_ORDER == __LITTLE_ENDIAN +#if defined CONFIG_SYS_FSL_ESDHC_LE +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_ESDHC_BE) +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#elif __BYTE_ORDER == __LITTLE_ENDIAN #define esdhc_read32 in_le32 #define esdhc_write32 out_le32 #define esdhc_clrsetbits32 clrsetbits_le32 @@ -183,5 +199,7 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd); static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {} #endif /* CONFIG_FSL_ESDHC */ +void __noreturn mmc_boot(void); +void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst); #endif /* __FSL_ESDHC_H__ */ diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/include/fsl_ifc.h similarity index 94% rename from arch/powerpc/include/asm/fsl_ifc.h rename to include/fsl_ifc.h index a945e4b2d4..11474b757c 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -5,13 +5,29 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __ASM_PPC_FSL_IFC_H -#define __ASM_PPC_FSL_IFC_H +#ifndef __FSL_IFC_H +#define __FSL_IFC_H #ifdef CONFIG_FSL_IFC #include #include +#define FSL_IFC_V1_1_0 0x01010000 +#define FSL_IFC_V2_0_0 0x02000000 + +#ifdef CONFIG_SYS_FSL_IFC_LE +#define ifc_in32(a) in_le32(a) +#define ifc_out32(a, v) out_le32(a, v) +#define ifc_in16(a) in_le16(a) +#elif defined(CONFIG_SYS_FSL_IFC_BE) +#define ifc_in32(a) in_be32(a) +#define ifc_out32(a, v) out_be32(a, v) +#define ifc_in16(a) in_be16(a) +#else +#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined +#endif + + /* * CSPR - Chip Select Property Register */ @@ -77,6 +93,7 @@ #define CSOR_NAND_PGS_512 0x00000000 #define CSOR_NAND_PGS_2K 0x00080000 #define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 /* Spare region Size */ #define CSOR_NAND_SPRZ_MASK 0x0000E000 #define CSOR_NAND_SPRZ_SHIFT 13 @@ -86,6 +103,7 @@ #define CSOR_NAND_SPRZ_210 0x00006000 #define CSOR_NAND_SPRZ_218 0x00008000 #define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 @@ -351,6 +369,8 @@ */ /* Auto Boot Mode */ #define IFC_NAND_NCFGR_BOOT 0x80000000 +/* SRAM INIT EN */ +#define IFC_NAND_SRAM_INIT_EN 0x20000000 /* Addressing Mode-ROW0+n/COL0 */ #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 /* Addressing Mode-ROW0+n/COL0+n */ @@ -768,23 +788,26 @@ enum ifc_nand_fir_opcodes { extern void print_ifc_regs(void); extern void init_early_memctl_regs(void); +void init_final_memctl_regs(void); #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) -#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) -#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) -#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) -#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) -#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) -#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) - -#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) -#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) -#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) -#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) -#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) +#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) +#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) +#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) +#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) #define set_ifc_ftim(i, j, v) \ - (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) enum ifc_chip_sel { IFC_CS0, @@ -983,4 +1006,4 @@ struct fsl_ifc { #endif /* CONFIG_FSL_IFC */ #endif /* __ASSEMBLY__ */ -#endif /* __ASM_PPC_FSL_IFC_H */ +#endif /* __FSL_IFC_H */ diff --git a/include/fsl_immap.h b/include/fsl_immap.h new file mode 100644 index 0000000000..d63cc19fa1 --- /dev/null +++ b/include/fsl_immap.h @@ -0,0 +1,139 @@ +/* + * Common internal memory map for some Freescale SoCs + * + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_IMMAP_H +#define __FSL_IMMAP_H +/* + * DDR memory controller registers + * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx. + */ +struct ccsr_ddr { + u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ + u8 res_04[4]; + u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ + u8 res_0c[4]; + u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ + u8 res_14[4]; + u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ + u8 res_1c[100]; + u32 cs0_config; /* Chip Select Configuration */ + u32 cs1_config; /* Chip Select Configuration */ + u32 cs2_config; /* Chip Select Configuration */ + u32 cs3_config; /* Chip Select Configuration */ + u8 res_90[48]; + u32 cs0_config_2; /* Chip Select Configuration 2 */ + u32 cs1_config_2; /* Chip Select Configuration 2 */ + u32 cs2_config_2; /* Chip Select Configuration 2 */ + u32 cs3_config_2; /* Chip Select Configuration 2 */ + u8 res_d0[48]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ + u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ + u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ + u32 sdram_data_init; /* SDRAM Data initialization */ + u8 res_12c[4]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res_134[20]; + u32 init_addr; /* training init addr */ + u32 init_ext_addr; /* training init extended addr */ + u8 res_150[16]; + u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ + u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ + u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ + u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ + u32 ddr_zq_cntl; /* ZQ calibration control*/ + u32 ddr_wrlvl_cntl; /* write leveling control*/ + u8 reg_178[4]; + u32 ddr_sr_cntr; /* self refresh counter */ + u32 ddr_sdram_rcw_1; /* Control Words 1 */ + u32 ddr_sdram_rcw_2; /* Control Words 2 */ + u8 reg_188[8]; + u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ + u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ + u8 res_198[0x1a0-0x198]; + u32 ddr_sdram_rcw_3; + u32 ddr_sdram_rcw_4; + u32 ddr_sdram_rcw_5; + u32 ddr_sdram_rcw_6; + u8 res_1b0[0x200-0x1b0]; + u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ + u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ + u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ + u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ + u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ + u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ + u8 res_218[0x220-0x218]; + u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ + u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ + u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ + u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ + u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ + u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ + u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ + u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ + u8 res_240[0x250-0x240]; + u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ + u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ + u8 res_258[0x260-0x258]; + u32 sdram_cfg_3; + u8 res_264[0x2a0-0x264]; + u32 deskew_cntl; + u8 res_2a4[0x400-0x2a4]; + u32 dq_map_0; + u32 dq_map_1; + u32 dq_map_2; + u32 dq_map_3; + u8 res_410[0xb20-0x410]; + u32 ddr_dsr1; /* Debug Status 1 */ + u32 ddr_dsr2; /* Debug Status 2 */ + u32 ddr_cdr1; /* Control Driver 1 */ + u32 ddr_cdr2; /* Control Driver 2 */ + u8 res_b30[200]; + u32 ip_rev1; /* IP Block Revision 1 */ + u32 ip_rev2; /* IP Block Revision 2 */ + u32 eor; /* Enhanced Optimization Register */ + u8 res_c04[252]; + u32 mtcr; /* Memory Test Control Register */ + u8 res_d04[28]; + u32 mtp1; /* Memory Test Pattern 1 */ + u32 mtp2; /* Memory Test Pattern 2 */ + u32 mtp3; /* Memory Test Pattern 3 */ + u32 mtp4; /* Memory Test Pattern 4 */ + u32 mtp5; /* Memory Test Pattern 5 */ + u32 mtp6; /* Memory Test Pattern 6 */ + u32 mtp7; /* Memory Test Pattern 7 */ + u32 mtp8; /* Memory Test Pattern 8 */ + u32 mtp9; /* Memory Test Pattern 9 */ + u32 mtp10; /* Memory Test Pattern 10 */ + u8 res_d48[184]; + u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ + u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ + u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ + u8 res_e0c[20]; + u32 capture_data_hi; /* Data Path Read Capture High */ + u32 capture_data_lo; /* Data Path Read Capture Low */ + u32 capture_ecc; /* Data Path Read Capture ECC */ + u8 res_e2c[20]; + u32 err_detect; /* Error Detect */ + u32 err_disable; /* Error Disable */ + u32 err_int_en; + u32 capture_attributes; /* Error Attrs Capture */ + u32 capture_address; /* Error Addr Capture */ + u32 capture_ext_address; /* Error Extended Addr Capture */ + u32 err_sbe; /* Single-Bit ECC Error Management */ + u8 res_e5c[164]; + u32 debug[32]; /* debug_1 to debug_32 */ + u8 res_f80[128]; +}; +#endif /* __FSL_IMMAP_H */ diff --git a/include/fsl_mc.h b/include/fsl_mc.h new file mode 100644 index 0000000000..b9f089e5f3 --- /dev/null +++ b/include/fsl_mc.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_MC_H__ +#define __FSL_MC_H__ + +#include + +#define MC_CCSR_BASE_ADDR \ + ((struct mc_ccsr_registers __iomem *)0x8340000) + +#define BIT(x) (1 << (x)) +#define GCR1_P1_STOP BIT(31) +#define GCR1_P2_STOP BIT(30) +#define GCR1_P1_DE_RST BIT(23) +#define GCR1_P2_DE_RST BIT(22) +#define GCR1_M1_DE_RST BIT(15) +#define GCR1_M2_DE_RST BIT(14) +#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) +#define GSR_FS_MASK 0x3fffffff +#define MCFAPR_PL_MASK (0x1 << 18) +#define MCFAPR_BMT_MASK (0x1 << 17) +#define MCFAPR_BYPASS_ICID_MASK \ + (MCFAPR_PL_MASK | MCFAPR_BMT_MASK) + +#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) +#define SOC_MC_PORTAL_STRIDE 0x10000 + +#define SOC_MC_PORTAL_ADDR(_portal_id) \ + ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ + (_portal_id) * SOC_MC_PORTAL_STRIDE)) + +struct mc_ccsr_registers { + u32 reg_gcr1; + u32 reserved1; + u32 reg_gsr; + u32 reserved2; + u32 reg_sicbalr; + u32 reg_sicbahr; + u32 reg_sicapr; + u32 reserved3; + u32 reg_mcfbalr; + u32 reg_mcfbahr; + u32 reg_mcfapr; + u32 reserved4[0x2f1]; + u32 reg_psr; + u32 reserved5; + u32 reg_brr[2]; + u32 reserved6[0x80]; + u32 reg_error[]; +}; + +int mc_init(bd_t *bis); + +int get_mc_boot_status(void); +#endif diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index 9c0b762773..2137282df3 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc. * Jun-jie Zhang * Mingkai Hu * @@ -10,7 +10,18 @@ #include #include -#include + +struct tsec_mii_mng { + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u32 ifstat; /* Interface Status Register */ +}; + +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); /* PHY register offsets */ #define PHY_EXT_PAGE_ACCESS 0x1f @@ -31,9 +42,9 @@ #define MIIMIND_BUSY 0x00000001 #define MIIMIND_NOTVALID 0x00000004 -void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, +void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, int dev_addr, int reg, int value); -int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, +int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, int dev_addr, int regnum); int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, @@ -44,7 +55,7 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, int regnum); struct fsl_pq_mdio_info { - struct tsec_mii_mng *regs; + struct tsec_mii_mng __iomem *regs; char *name; }; int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); diff --git a/include/fsl_sec.h b/include/fsl_sec.h new file mode 100644 index 0000000000..aa850a3bf1 --- /dev/null +++ b/include/fsl_sec.h @@ -0,0 +1,181 @@ +/* + * Common internal memory map for some Freescale SoCs + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + */ + +#ifndef __FSL_SEC_H +#define __FSL_SEC_H + +#include +#include + +#ifdef CONFIG_SYS_FSL_SEC_LE +#define sec_in32(a) in_le32(a) +#define sec_out32(a, v) out_le32(a, v) +#define sec_in16(a) in_le16(a) +#define sec_clrbits32 clrbits_le32 +#define sec_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_SEC_BE) +#define sec_in32(a) in_be32(a) +#define sec_out32(a, v) out_be32(a, v) +#define sec_in16(a) in_be16(a) +#define sec_clrbits32 clrbits_be32 +#define sec_setbits32 setbits_be32 +#else +#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined +#endif + +/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +/* RNG4 TRNG test registers */ +struct rng4tst { +#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ + u32 rtmctl; /* misc. control register */ + u32 rtscmisc; /* statistical check misc. register */ + u32 rtpkrrng; /* poker range register */ +#define RTSDCTL_ENT_DLY_MIN 1200 +#define RTSDCTL_ENT_DLY_MAX 12800 + union { + u32 rtpkrmax; /* PRGM=1: poker max. limit register */ + u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ + }; +#define RTSDCTL_ENT_DLY_SHIFT 16 +#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) + u32 rtsdctl; /* seed control register */ + union { + u32 rtsblim; /* PRGM=1: sparse bit limit register */ + u32 rttotsam; /* PRGM=0: total samples register */ + }; + u32 rtfreqmin; /* frequency count min. limit register */ + union { + u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ + u32 rtfreqcnt; /* PRGM=0: freq. count register */ + }; + u32 rsvd1[40]; +#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001 + u32 rdsta; /*RNG DRNG Status Register*/ + u32 rsvd2[15]; +}; + +typedef struct ccsr_sec { + u32 res0; + u32 mcfgr; /* Master CFG Register */ + u8 res1[0x4]; + u32 scfgr; + struct { + u32 ms; /* Job Ring LIODN Register, MS */ + u32 ls; /* Job Ring LIODN Register, LS */ + } jrliodnr[4]; + u8 res2[0x2c]; + u32 jrstartr; /* Job Ring Start Register */ + struct { + u32 ms; /* RTIC LIODN Register, MS */ + u32 ls; /* RTIC LIODN Register, LS */ + } rticliodnr[4]; + u8 res3[0x1c]; + u32 decorr; /* DECO Request Register */ + struct { + u32 ms; /* DECO LIODN Register, MS */ + u32 ls; /* DECO LIODN Register, LS */ + } decoliodnr[8]; + u8 res4[0x40]; + u32 dar; /* DECO Avail Register */ + u32 drr; /* DECO Reset Register */ + u8 res5[0x4d8]; + struct rng4tst rng; /* RNG Registers */ + u8 res11[0x8a0]; + u32 crnr_ms; /* CHA Revision Number Register, MS */ + u32 crnr_ls; /* CHA Revision Number Register, LS */ + u32 ctpr_ms; /* Compile Time Parameters Register, MS */ + u32 ctpr_ls; /* Compile Time Parameters Register, LS */ + u8 res6[0x10]; + u32 far_ms; /* Fault Address Register, MS */ + u32 far_ls; /* Fault Address Register, LS */ + u32 falr; /* Fault Address LIODN Register */ + u32 fadr; /* Fault Address Detail Register */ + u8 res7[0x4]; + u32 csta; /* CAAM Status Register */ + u8 res8[0x8]; + u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ + u32 ccbvid; /* CHA Cluster Block Version ID Register */ + u32 chavid_ms; /* CHA Version ID Register, MS */ + u32 chavid_ls; /* CHA Version ID Register, LS */ + u32 chanum_ms; /* CHA Number Register, MS */ + u32 chanum_ls; /* CHA Number Register, LS */ + u32 secvid_ms; /* SEC Version ID Register, MS */ + u32 secvid_ls; /* SEC Version ID Register, LS */ + u8 res9[0x6020]; + u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ + u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ + u8 res10[0x8fd8]; +} ccsr_sec_t; + +#define SEC_CTPR_MS_AXI_LIODN 0x08000000 +#define SEC_CTPR_MS_QI 0x02000000 +#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001 +#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002 +#define SEC_RVID_MA 0x0f000000 +#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JRNUM_SHIFT 28 +#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 +#define SEC_CHANUM_MS_DECONUM_SHIFT 24 +#define SEC_SECVID_MS_IPID_MASK 0xffff0000 +#define SEC_SECVID_MS_IPID_SHIFT 16 +#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 +#define SEC_SECVID_MS_MAJ_REV_SHIFT 8 +#define SEC_CCBVID_ERA_MASK 0xff000000 +#define SEC_CCBVID_ERA_SHIFT 24 +#define SEC_SCFGR_RDBENABLE 0x00000400 +#define SEC_SCFGR_VIRT_EN 0x00008000 +#define SEC_CHAVID_LS_RNG_SHIFT 16 +#define SEC_CHAVID_RNG_LS_MASK 0x000f0000 + +#define CONFIG_JRSTARTR_JR0 0x00000001 + +struct jr_regs { +#ifdef CONFIG_SYS_FSL_SEC_LE + u32 irba_l; + u32 irba_h; +#else + u32 irba_h; + u32 irba_l; +#endif + u32 rsvd1; + u32 irs; + u32 rsvd2; + u32 irsa; + u32 rsvd3; + u32 irja; +#ifdef CONFIG_SYS_FSL_SEC_LE + u32 orba_l; + u32 orba_h; +#else + u32 orba_h; + u32 orba_l; +#endif + u32 rsvd4; + u32 ors; + u32 rsvd5; + u32 orjr; + u32 rsvd6; + u32 orsf; + u32 rsvd7; + u32 jrsta; + u32 rsvd8; + u32 jrint; + u32 jrcfg0; + u32 jrcfg1; + u32 rsvd9; + u32 irri; + u32 rsvd10; + u32 orwi; + u32 rsvd11; + u32 jrcr; +}; + +int sec_init(void); +#endif + +#endif /* __FSL_SEC_H */ diff --git a/include/fsl_usb.h b/include/fsl_usb.h new file mode 100644 index 0000000000..d251f5d4ce --- /dev/null +++ b/include/fsl_usb.h @@ -0,0 +1,188 @@ +/* + * Freescale USB Controller + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_FSL_USB_H_ +#define _ASM_FSL_USB_H_ + +#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +struct ccsr_usb_port_ctrl { + u32 ctrl; + u32 drvvbuscfg; + u32 pwrfltcfg; + u32 sts; + u8 res_14[0xc]; + u32 bistcfg; + u32 biststs; + u32 abistcfg; + u32 abiststs; + u8 res_30[0x10]; + u32 xcvrprg; + u32 anaprg; + u32 anadrv; + u32 anasts; +}; + +struct ccsr_usb_phy { + u32 id; + struct ccsr_usb_port_ctrl port1; + u8 res_50[0xc]; + u32 tvr; + u32 pllprg[4]; + u8 res_70[0x4]; + u32 anaccfg; + u32 dbg; + u8 res_7c[0x4]; + struct ccsr_usb_port_ctrl port2; + u8 res_dc[0x334]; +}; + +#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) +#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4) +#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16) +#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20) +#endif +#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) +#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) +#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7) +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4) + +#define INC_DCNT_THRESHOLD_25MV (0 << 4) +#define INC_DCNT_THRESHOLD_50MV (1 << 4) +#define DEC_DCNT_THRESHOLD_25MV (2 << 4) +#define DEC_DCNT_THRESHOLD_50MV (3 << 4) +#else +struct ccsr_usb_phy { + u32 config1; + u32 config2; + u32 config3; + u32 config4; + u32 config5; + u32 status1; + u32 usb_enable_override; + u8 res[0xe4]; +}; +#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22) +#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20) +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3 +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 +#endif + +/* USB Erratum Checking code */ +#ifdef CONFIG_PPC +static inline bool has_erratum_a006261(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P2041: + case SVR_P2040: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1); + case SVR_P3041: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || + IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1); + case SVR_P5010: + case SVR_P5020: + case SVR_P5021: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T4240: + case SVR_T4160: + case SVR_T4080: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T1040: + return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0); + case SVR_P5040: + return IS_SVR_REV(svr, 1, 0); + } + + return false; +} + +static inline bool has_erratum_a007075(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + return false; +} + +static inline bool has_erratum_a007798(void) +{ + return SVR_SOC_VER(get_svr()) == SVR_T4240 && + IS_SVR_REV(get_svr(), 2, 0); +} + +static inline bool has_erratum_a007792(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + case SVR_T4160: + return IS_SVR_REV(svr, 2, 0); + case SVR_T1040: + return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + } + return false; +} + +#else +static inline bool has_erratum_a006261(void) +{ + return false; +} + +static inline bool has_erratum_a007075(void) +{ + return false; +} + +static inline bool has_erratum_a007798(void) +{ + return false; +} + +static inline bool has_erratum_a007792(void) +{ + return false; +} +#endif +#endif /*_ASM_FSL_USB_H_ */ diff --git a/include/g_dnl.h b/include/g_dnl.h index 2b2f11a62f..4eeb5e4070 100644 --- a/include/g_dnl.h +++ b/include/g_dnl.h @@ -10,10 +10,37 @@ #include #include -int g_dnl_bind_fixup(struct usb_device_descriptor *); +#include +#include + +/* + * @usb_fname: unescaped USB function name + * @callback_ptr: bind callback, one per function name + */ +#define DECLARE_GADGET_BIND_CALLBACK(usb_fname, callback_ptr) \ + ll_entry_declare(struct g_dnl_bind_callback, \ + __usb_function_name_##usb_fname, \ + g_dnl_bind_callbacks) = { \ + .usb_function_name = #usb_fname, \ + .fptr = callback_ptr \ + } + +typedef int (*g_dnl_bind_callback_f)(struct usb_configuration *); + +/* used in Gadget downloader callback linker list */ +struct g_dnl_bind_callback { + const char *usb_function_name; + g_dnl_bind_callback_f fptr; +}; + +int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *); +int g_dnl_board_usb_cable_connected(void); int g_dnl_register(const char *s); void g_dnl_unregister(void); +void g_dnl_set_serialnumber(char *); + +bool g_dnl_detach(void); +void g_dnl_trigger_detach(void); +void g_dnl_clear_detach(void); -/* USB initialization declaration - board specific */ -void board_usb_init(void); #endif /* __G_DOWNLOAD_H_ */ diff --git a/include/galileo/core.h b/include/galileo/core.h deleted file mode 100644 index 95013fac26..0000000000 --- a/include/galileo/core.h +++ /dev/null @@ -1,217 +0,0 @@ -/* Core.h - Basic core logic functions and definitions */ - -/* Copyright Galileo Technology. */ - -/* -DESCRIPTION -This header file contains simple read/write macros for addressing -the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address -space). The macros take care of Big/Little endian conversions. -*/ - -#ifndef __INCcoreh -#define __INCcoreh - -/* includes */ -#include "gt64260R.h" -#include - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/* - * GT-6426x variants - */ -#define GT_64260 0 /* includes both 64260A and 64260B */ -#define GT_64261 1 - -#if (CONFIG_SYS_GT_6426x == GT_64260) -#ifdef CONFIG_ETHER_PORT_MII -#define GAL_ETH_DEVS 2 -#else -#define GAL_ETH_DEVS 3 -#endif -#elif (CONFIG_SYS_GT_6426x == GT_64261) -#define GAL_ETH_DEVS 2 -#else -#define GAL_ETH_DEVS 3 /* default to a 64260 */ -#endif - -/****************************************/ -/* GENERAL Definitions */ -/****************************************/ - -#define NO_BIT 0x00000000 -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#define _1K 0x00000400 -#define _2K 0x00000800 -#define _4K 0x00001000 -#define _8K 0x00002000 -#define _16K 0x00004000 -#define _32K 0x00008000 -#define _64K 0x00010000 -#define _128K 0x00020000 -#define _256K 0x00040000 -#define _512K 0x00080000 - -#define _1M 0x00100000 -#define _2M 0x00200000 -#define _3M 0x00300000 -#define _4M 0x00400000 -#define _5M 0x00500000 -#define _6M 0x00600000 -#define _7M 0x00700000 -#define _8M 0x00800000 -#define _9M 0x00900000 -#define _10M 0x00a00000 -#define _11M 0x00b00000 -#define _12M 0x00c00000 -#define _13M 0x00d00000 -#define _14M 0x00e00000 -#define _15M 0x00f00000 -#define _16M 0x01000000 - -#define _32M 0x02000000 -#define _64M 0x04000000 -#define _128M 0x08000000 -#define _256M 0x10000000 -#define _512M 0x20000000 - -#define _1G 0x40000000 -#define _2G 0x80000000 - -/* Little to Big endian conversion macros */ - -#ifdef LE /* Little Endian */ -#define SHORT_SWAP(X) (X) -#define WORD_SWAP(X) (X) -#define LONG_SWAP(X) ((l64)(X)) - -#else /* Big Endian */ -#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) - -#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ - (((X)&0xff00)<<8)+ \ - (((X)&0xff0000)>>8)+ \ - (((X)&0xff000000)>>24) - -#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ - (((X)&0xff00ULL)<<40)+ \ - (((X)&0xff0000ULL)<<24)+ \ - (((X)&0xff000000ULL)<<8)+ \ - (((X)&0xff00000000ULL)>>8)+ \ - (((X)&0xff0000000000ULL)>>24)+ \ - (((X)&0xff000000000000ULL)>>40)+ \ - (((X)&0xff00000000000000ULL)>>56)) - -#endif - -#ifndef NULL -#define NULL 0 -#endif - -/* Those two definitions were defined to be compatible with MIPS */ -#define NONE_CACHEABLE 0x00000000 -#define CACHEABLE 0x00000000 - -/* 750 cache line */ -#define CACHE_LINE_SIZE 32 -#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) -#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) - -/* Read/Write to/from GT`s internal registers */ -#define GT_REG_READ(offset, pData) \ -*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ -*pData = WORD_SWAP(*pData) - -#define GTREGREAD(offset) \ - (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) )) - -#define GT_REG_WRITE(offset, data) \ -*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ - WORD_SWAP(data) - -/* Write 32/16/8 bit */ -#define WRITE_CHAR(address, data) \ - *((unsigned char *)(address)) = data -#define WRITE_SHORT(address, data) \ - *((unsigned short *)(address)) = data -#define WRITE_WORD(address, data) \ - *((unsigned int *)(address)) = data - -/* Read 32/16/8 bits - returns data in variable. */ -#define READ_CHAR(address, pData) \ - *pData = *((volatile unsigned char *)(address)) - -#define READ_SHORT(address, pData) \ - *pData = *((volatile unsigned short *)(address)) - -#define READ_WORD(address, pData) \ - *pData = *((volatile unsigned int *)(address)) - -/* Read 32/16/8 bit - returns data direct. */ -#define READCHAR(address) \ - *((volatile unsigned char *)((address) | NONE_CACHEABLE)) - -#define READSHORT(address) \ - *((volatile unsigned short *)((address) | NONE_CACHEABLE)) - -#define READWORD(address) \ - *((volatile unsigned int *)((address) | NONE_CACHEABLE)) - -/* Those two Macros were defined to be compatible with MIPS */ -#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) -#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE) - -/* SET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '1' in the - internal register the bits which given as an input example: - SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '1' in register 0x840 while the other bits stays as is. */ -#define SET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ - regOffset) |= (unsigned int)WORD_SWAP(bits) - -/* RESET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '0' in the - internal register the bits which given as an input example: - RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '0' in register 0x840 while the other bits stays as is. */ -#define RESET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ - | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) - -#endif /* __INCcoreh */ diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h deleted file mode 100644 index b55da9d352..0000000000 --- a/include/galileo/gt64260R.h +++ /dev/null @@ -1,1194 +0,0 @@ -/* gt64260R.h - GT64260 Internal registers definition file */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCgt64260rh -#define __INCgt64260rh - -#ifndef GT64260 -#define GT64260 -#endif - -/* CPU MASTER CONTROL REGISTER */ -#define CPU_CONFIGURATION 0x0 -#define CPU_MASTER_CONTROL 0x160 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* Sdram's BAR'S */ -#define SCS_0_LOW_DECODE_ADDRESS 0x008 -#define SCS_0_HIGH_DECODE_ADDRESS 0x010 -#define SCS_1_LOW_DECODE_ADDRESS 0x208 -#define SCS_1_HIGH_DECODE_ADDRESS 0x210 -#define SCS_2_LOW_DECODE_ADDRESS 0x018 -#define SCS_2_HIGH_DECODE_ADDRESS 0x020 -#define SCS_3_LOW_DECODE_ADDRESS 0x218 -#define SCS_3_HIGH_DECODE_ADDRESS 0x220 -/* Devices BAR'S */ -#define CS_0_LOW_DECODE_ADDRESS 0x028 -#define CS_0_HIGH_DECODE_ADDRESS 0x030 -#define CS_1_LOW_DECODE_ADDRESS 0x228 -#define CS_1_HIGH_DECODE_ADDRESS 0x230 -#define CS_2_LOW_DECODE_ADDRESS 0x248 -#define CS_2_HIGH_DECODE_ADDRESS 0x250 -#define CS_3_LOW_DECODE_ADDRESS 0x038 -#define CS_3_HIGH_DECODE_ADDRESS 0x040 -#define BOOTCS_LOW_DECODE_ADDRESS 0x238 -#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 - -#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 -#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 -#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 -#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 -#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 -#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 -#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 -#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 -#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 -#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 - -#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 -#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 -#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 -#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 -#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 -#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 -#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 -#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 -#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 -#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 - - -#define INTERNAL_SPACE_DECODE 0x068 - -#define CPU_0_LOW_DECODE_ADDRESS 0x290 -#define CPU_0_HIGH_DECODE_ADDRESS 0x298 -#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 -#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 - -#define PCI_0I_O_ADDRESS_REMAP 0x0f0 -#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 -#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 -#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 -#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 -#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 -#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 -#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 -#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 - -#define PCI_1I_O_ADDRESS_REMAP 0x108 -#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 -#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 -#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 -#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 -#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 -#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 -#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 -#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 - - -/****************************************/ -/* CPU Sync Barrier */ -/****************************************/ - -#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0 -#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8 - - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define CPU_LOW_PROTECT_ADDRESS_0 0x180 -#define CPU_HIGH_PROTECT_ADDRESS_0 0x188 -#define CPU_LOW_PROTECT_ADDRESS_1 0x190 -#define CPU_HIGH_PROTECT_ADDRESS_1 0x198 -#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0 -#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8 -#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0 -#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8 -#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0 -#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8 -#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0 -#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8 -#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0 -#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8 -#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0 -#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8 - - -/****************************************/ -/* Snoop Control */ -/****************************************/ - -#define SNOOP_BASE_ADDRESS_0 0x380 -#define SNOOP_TOP_ADDRESS_0 0x388 -#define SNOOP_BASE_ADDRESS_1 0x390 -#define SNOOP_TOP_ADDRESS_1 0x398 -#define SNOOP_BASE_ADDRESS_2 0x3a0 -#define SNOOP_TOP_ADDRESS_2 0x3a8 -#define SNOOP_BASE_ADDRESS_3 0x3b0 -#define SNOOP_TOP_ADDRESS_3 0x3b8 - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define CPU_ERROR_ADDRESS_LOW 0x070 -#define CPU_ERROR_ADDRESS_HIGH 0x078 -#define CPU_ERROR_DATA_LOW 0x128 -#define CPU_ERROR_DATA_HIGH 0x130 -#define CPU_ERROR_PARITY 0x138 -#define CPU_ERROR_CAUSE 0x140 -#define CPU_ERROR_MASK 0x148 - -/****************************************/ -/* Pslave Debug */ -/****************************************/ - -#define X_0_ADDRESS 0x360 -#define X_0_COMMAND_ID 0x368 -#define X_1_ADDRESS 0x370 -#define X_1_COMMAND_ID 0x378 -#define WRITE_DATA_LOW 0x3c0 -#define WRITE_DATA_HIGH 0x3c8 -#define WRITE_BYTE_ENABLE 0x3e0 -#define READ_DATA_LOW 0x3d0 -#define READ_DATA_HIGH 0x3d8 -#define READ_ID 0x3e8 - - -/****************************************/ -/* SDRAM and Device Address Space */ -/****************************************/ - - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - - -#define SDRAM_CONFIGURATION 0x448 -#define SDRAM_OPERATION_MODE 0x474 -#define SDRAM_ADDRESS_DECODE 0x47c -#define SDRAM_UMA_CONTROL 0x4a4 -#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 -#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac -#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 -#define SDRAM_TIMING 0x4b4 - - -/****************************************/ -/* SDRAM Parameters */ -/****************************************/ - -#define SDRAM_BANK0PARAMETERS 0x44C -#define SDRAM_BANK1PARAMETERS 0x450 -#define SDRAM_BANK2PARAMETERS 0x454 -#define SDRAM_BANK3PARAMETERS 0x458 - - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define SDRAM_ERROR_DATA_LOW 0x484 -#define SDRAM_ERROR_DATA_HIGH 0x480 -#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490 -#define SDRAM_RECEIVED_ECC 0x488 -#define SDRAM_CALCULATED_ECC 0x48c -#define SDRAM_ECC_CONTROL 0x494 -#define SDRAM_ECC_ERROR_COUNTER 0x498 - - -/****************************************/ -/* SDunit Debug (for internal use) */ -/****************************************/ - -#define X0_ADDRESS 0x500 -#define X0_COMMAND_AND_ID 0x504 -#define X0_WRITE_DATA_LOW 0x508 -#define X0_WRITE_DATA_HIGH 0x50c -#define X0_WRITE_BYTE_ENABLE 0x518 -#define X0_READ_DATA_LOW 0x510 -#define X0_READ_DATA_HIGH 0x514 -#define X0_READ_ID 0x51c -#define X1_ADDRESS 0x520 -#define X1_COMMAND_AND_ID 0x524 -#define X1_WRITE_DATA_LOW 0x528 -#define X1_WRITE_DATA_HIGH 0x52c -#define X1_WRITE_BYTE_ENABLE 0x538 -#define X1_READ_DATA_LOW 0x530 -#define X1_READ_DATA_HIGH 0x534 -#define X1_READ_ID 0x53c -#define X0_SNOOP_ADDRESS 0x540 -#define X0_SNOOP_COMMAND 0x544 -#define X1_SNOOP_ADDRESS 0x548 -#define X1_SNOOP_COMMAND 0x54c - - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define DEVICE_BANK0PARAMETERS 0x45c -#define DEVICE_BANK1PARAMETERS 0x460 -#define DEVICE_BANK2PARAMETERS 0x464 -#define DEVICE_BANK3PARAMETERS 0x468 -#define DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define DEVICE_CONTROL 0x4c0 -#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 - - -/****************************************/ -/* Device Interrupt */ -/****************************************/ - -#define DEVICE_INTERRUPT_CAUSE 0x4d0 -#define DEVICE_INTERRUPT_MASK 0x4d4 -#define DEVICE_ERROR_ADDRESS 0x4d8 - -/****************************************/ -/* DMA Record */ -/****************************************/ - -#define CHANNEL0_DMA_BYTE_COUNT 0x800 -#define CHANNEL1_DMA_BYTE_COUNT 0x804 -#define CHANNEL2_DMA_BYTE_COUNT 0x808 -#define CHANNEL3_DMA_BYTE_COUNT 0x80C -#define CHANNEL4_DMA_BYTE_COUNT 0x900 -#define CHANNEL5_DMA_BYTE_COUNT 0x904 -#define CHANNEL6_DMA_BYTE_COUNT 0x908 -#define CHANNEL7_DMA_BYTE_COUNT 0x90C -#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 -#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 -#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 -#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C -#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910 -#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914 -#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918 -#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C -#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 -#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 -#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 -#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C -#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920 -#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924 -#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928 -#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C -#define CHANNEL0NEXT_RECORD_POINTER 0x830 -#define CHANNEL1NEXT_RECORD_POINTER 0x834 -#define CHANNEL2NEXT_RECORD_POINTER 0x838 -#define CHANNEL3NEXT_RECORD_POINTER 0x83C -#define CHANNEL4NEXT_RECORD_POINTER 0x930 -#define CHANNEL5NEXT_RECORD_POINTER 0x934 -#define CHANNEL6NEXT_RECORD_POINTER 0x938 -#define CHANNEL7NEXT_RECORD_POINTER 0x93C -#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 -#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 -#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 -#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C -#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970 -#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974 -#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978 -#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C -#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890 -#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894 -#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898 -#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c -#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990 -#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994 -#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998 -#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c -#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0 -#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4 -#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8 -#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac -#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0 -#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4 -#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8 -#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac -#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0 -#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4 -#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8 -#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc -#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0 -#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4 -#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8 -#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define CHANNEL0CONTROL 0x840 -#define CHANNEL0CONTROL_HIGH 0x880 -#define CHANNEL1CONTROL 0x844 -#define CHANNEL1CONTROL_HIGH 0x884 -#define CHANNEL2CONTROL 0x848 -#define CHANNEL2CONTROL_HIGH 0x888 -#define CHANNEL3CONTROL 0x84C -#define CHANNEL3CONTROL_HIGH 0x88C - -#define CHANNEL4CONTROL 0x940 -#define CHANNEL4CONTROL_HIGH 0x980 -#define CHANNEL5CONTROL 0x944 -#define CHANNEL5CONTROL_HIGH 0x984 -#define CHANNEL6CONTROL 0x948 -#define CHANNEL6CONTROL_HIGH 0x988 -#define CHANNEL7CONTROL 0x94C -#define CHANNEL7CONTROL_HIGH 0x98C - - -/****************************************/ -/* DMA Arbiter */ -/****************************************/ - -#define ARBITER_CONTROL_0_3 0x860 -#define ARBITER_CONTROL_4_7 0x960 - - -/****************************************/ -/* DMA Interrupt */ -/****************************************/ - -#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 -#define CHANELS0_3_INTERRUPT_MASK 0x8c4 -#define CHANELS0_3_ERROR_ADDRESS 0x8c8 -#define CHANELS0_3_ERROR_SELECT 0x8cc -#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0 -#define CHANELS4_7_INTERRUPT_MASK 0x9c4 -#define CHANELS4_7_ERROR_ADDRESS 0x9c8 -#define CHANELS4_7_ERROR_SELECT 0x9cc - - -/****************************************/ -/* DMA Debug (for internal use) */ -/****************************************/ - -#define DMA_X0_ADDRESS 0x8e0 -#define DMA_X0_COMMAND_AND_ID 0x8e4 -#define DMA_X0_WRITE_DATA_LOW 0x8e8 -#define DMA_X0_WRITE_DATA_HIGH 0x8ec -#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8 -#define DMA_X0_READ_DATA_LOW 0x8f0 -#define DMA_X0_READ_DATA_HIGH 0x8f4 -#define DMA_X0_READ_ID 0x8fc -#define DMA_X1_ADDRESS 0x9e0 -#define DMA_X1_COMMAND_AND_ID 0x9e4 -#define DMA_X1_WRITE_DATA_LOW 0x9e8 -#define DMA_X1_WRITE_DATA_HIGH 0x9ec -#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8 -#define DMA_X1_READ_DATA_LOW 0x9f0 -#define DMA_X1_READ_DATA_HIGH 0x9f4 -#define DMA_X1_READ_ID 0x9fc - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define TIMER_COUNTER0 0x850 -#define TIMER_COUNTER1 0x854 -#define TIMER_COUNTER2 0x858 -#define TIMER_COUNTER3 0x85C -#define TIMER_COUNTER_0_3_CONTROL 0x864 -#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c -#define TIMER_COUNTER4 0x950 -#define TIMER_COUNTER5 0x954 -#define TIMER_COUNTER6 0x958 -#define TIMER_COUNTER7 0x95C -#define TIMER_COUNTER_4_7_CONTROL 0x964 -#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968 -#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c - -/****************************************/ -/* PCI Slave Address Decoding */ -/****************************************/ - -#define PCI_0SCS_0_BANK_SIZE 0xc08 -#define PCI_1SCS_0_BANK_SIZE 0xc88 -#define PCI_0SCS_1_BANK_SIZE 0xd08 -#define PCI_1SCS_1_BANK_SIZE 0xd88 -#define PCI_0SCS_2_BANK_SIZE 0xc0c -#define PCI_1SCS_2_BANK_SIZE 0xc8c -#define PCI_0SCS_3_BANK_SIZE 0xd0c -#define PCI_1SCS_3_BANK_SIZE 0xd8c -#define PCI_0CS_0_BANK_SIZE 0xc10 -#define PCI_1CS_0_BANK_SIZE 0xc90 -#define PCI_0CS_1_BANK_SIZE 0xd10 -#define PCI_1CS_1_BANK_SIZE 0xd90 -#define PCI_0CS_2_BANK_SIZE 0xd18 -#define PCI_1CS_2_BANK_SIZE 0xd98 -#define PCI_0CS_3_BANK_SIZE 0xc14 -#define PCI_1CS_3_BANK_SIZE 0xc94 -#define PCI_0CS_BOOT_BANK_SIZE 0xd14 -#define PCI_1CS_BOOT_BANK_SIZE 0xd94 -#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c -#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c -#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 -#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 -#define PCI_0P2P_I_O_BAR_SIZE 0xd24 -#define PCI_1P2P_I_O_BAR_SIZE 0xda4 -#define PCI_0CPU_BAR_SIZE 0xd28 -#define PCI_1CPU_BAR_SIZE 0xda8 -#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 -#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 -#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 -#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 -#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 -#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 -#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c -#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c -#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 -#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 -#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 -#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 -#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 -#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 -#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c -#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c -#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 -#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 -#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 -#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 -#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 -#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 -#define PCI_0DAC_CPU_BAR_SIZE 0xe2c -#define PCI_1DAC_CPU_BAR_SIZE 0xeac -#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c -#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac -#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c -#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc -#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 -#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 -#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 -#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 -#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c -#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc -#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c -#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc -#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 -#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 -#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 -#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 -#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 -#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 -#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 -#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 -#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 -#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 -#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c -#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec -#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 -#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 -#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 -#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 -#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 -#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 -#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 -#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 -#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c -#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c -#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 -#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 -#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 -#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 -#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 -#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 -#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c -#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c -#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 -#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 -#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 -#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 -#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 -#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 -#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c -#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc - -/****************************************/ -/* PCI Control */ -/****************************************/ - -#define PCI_0COMMAND 0xc00 -#define PCI_1COMMAND 0xc80 -#define PCI_0MODE 0xd00 -#define PCI_1MODE 0xd80 -#define PCI_0TIMEOUT_RETRY 0xc04 -#define PCI_1TIMEOUT_RETRY 0xc84 -#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 -#define MSI_0TRIGGER_TIMER 0xc38 -#define MSI_1TRIGGER_TIMER 0xcb8 -#define PCI_0ARBITER_CONTROL 0x1d00 -#define PCI_1ARBITER_CONTROL 0x1d80 -/* changing untill here */ -#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c -#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 -#define PCI_0P2P_CONFIGURATION 0x1d14 -#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 -#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 -#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 -#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 -#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 -#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 -#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60 -#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 -#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 -#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70 -#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 -#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 -#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c -#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 -#define PCI_1P2P_CONFIGURATION 0x1d94 -#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 -#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 -#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 -#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 -#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 -#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 -#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0 -#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 -#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 -#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0 -#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 -#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 - -/****************************************/ -/* PCI Snoop Control */ -/****************************************/ - -#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 -#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 -#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 -#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 -#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 -#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 -#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 -#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 -#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 -#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 -#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 -#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 -#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 -#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 -#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 -#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 -#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 -#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 -#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 -#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 -#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 -#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 -#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 -#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 - -/****************************************/ -/* PCI Configuration Address */ -/****************************************/ - -#define PCI_0CONFIGURATION_ADDRESS 0xcf8 -#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc -#define PCI_1CONFIGURATION_ADDRESS 0xc78 -#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c -#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 -#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 - -/****************************************/ -/* PCI Error Report */ -/****************************************/ - -#define PCI_0SERR_MASK 0xc28 -#define PCI_0ERROR_ADDRESS_LOW 0x1d40 -#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 -#define PCI_0ERROR_DATA_LOW 0x1d48 -#define PCI_0ERROR_DATA_HIGH 0x1d4c -#define PCI_0ERROR_COMMAND 0x1d50 -#define PCI_0ERROR_CAUSE 0x1d58 -#define PCI_0ERROR_MASK 0x1d5c -#define PCI_1SERR_MASK 0xca8 -#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 -#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 -#define PCI_1ERROR_DATA_LOW 0x1dc8 -#define PCI_1ERROR_DATA_HIGH 0x1dcc -#define PCI_1ERROR_COMMAND 0x1dd0 -#define PCI_1ERROR_CAUSE 0x1dd8 -#define PCI_1ERROR_MASK 0x1ddc - - -/****************************************/ -/* Lslave Debug (for internal use) */ -/****************************************/ - -#define L_SLAVE_X0_ADDRESS 0x1d20 -#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 -#define L_SLAVE_X1_ADDRESS 0x1d28 -#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c -#define L_SLAVE_WRITE_DATA_LOW 0x1d30 -#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 -#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 -#define L_SLAVE_READ_DATA_LOW 0x1d38 -#define L_SLAVE_READ_DATA_HIGH 0x1d3c -#define L_SLAVE_READ_ID 0x1d64 - -/****************************************/ -/* PCI Configuration Function 0 */ -/****************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/****************************************/ -/* PCI Configuration Function 1 */ -/****************************************/ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/****************************************/ -/* PCI Configuration Function 2 */ -/****************************************/ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 -#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 -#define PCI_CPU_BASE_ADDRESS 0x21c - -/****************************************/ -/* PCI Configuration Function 4 */ -/****************************************/ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/****************************************/ -/* PCI Configuration Function 5 */ -/****************************************/ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/****************************************/ -/* PCI Configuration Function 6 */ -/****************************************/ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/****************************************/ -/* PCI Configuration Function 7 */ -/****************************************/ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 -#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68 -#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c -#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c -#define CPU_SELECT_CAUSE_REGISTER 0xc70 -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24 -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64 -#define PCI_0SELECT_CAUSE 0xc74 -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4 -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4 -#define PCI_1SELECT_CAUSE 0xcf4 -#define CPU_INT_0_MASK 0xe60 -#define CPU_INT_1_MASK 0xe64 -#define CPU_INT_2_MASK 0xe68 -#define CPU_INT_3_MASK 0xe6c - -/****************************************/ -/* I20 Support registers */ -/****************************************/ - -#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C -#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C - -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C - -/****************************************/ -/* Communication Unit Registers */ -/****************************************/ - -#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200 -#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 -#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 -#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c -#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 -#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 -#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 -#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 -#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 -#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 -#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c -#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 -#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 -#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 -#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 -#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 -#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 -#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c -#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 -#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 -#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 -#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 -#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 -#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 -#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c -#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 -#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 -#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0 -#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4 -#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 -#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc -#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 -#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 -#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 -#define SERIAL_INIT_LAST_DATA 0xf324 -#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 -#define COMM_UNIT_ARBITER_CONTROL 0xf300 -#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 -#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 -#define COMM_UNIT_INTERRUPT_MASK 0xf314 -#define COMM_UNIT_ERROR_ADDRESS 0xf314 - -/****************************************/ -/* Cunit Debug (for internal use) */ -/****************************************/ - -#define CUNIT_ADDRESS 0xf340 -#define CUNIT_COMMAND_AND_ID 0xf344 -#define CUNIT_WRITE_DATA_LOW 0xf348 -#define CUNIT_WRITE_DATA_HIGH 0xf34c -#define CUNIT_WRITE_BYTE_ENABLE 0xf358 -#define CUNIT_READ_DATA_LOW 0xf350 -#define CUNIT_READ_DATA_HIGH 0xf354 -#define CUNIT_READ_ID 0xf35c - -/****************************************/ -/* Fast Ethernet Unit Registers */ -/****************************************/ - -/* Ethernet */ - -#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 -#define ETHERNET_SMI_REGISTER 0x2010 - -/* Ethernet 0 */ - -#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 -#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 -#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 -#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 -#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 -#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 -#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 -#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 -#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 -#define ETHERNET0_MIB_COUNTER_BASE 0x2500 - -/* Ethernet 1 */ - -#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 -#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 -#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 -#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 -#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 -#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 -#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 -#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 -#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 -#define ETHERNET1_MIB_COUNTER_BASE 0x2900 - -/* Ethernet 2 */ - -#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 -#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 -#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 -#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 -#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 -#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 -#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 -#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 -#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 -#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 - -/****************************************/ -/* SDMA Registers */ -/****************************************/ - -#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 -#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 -#define CHANNEL0_COMMAND_REGISTER 0x4008 -#define CHANNEL0_RX_CMD_STATUS 0x4800 -#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 -#define CHANNEL0_RX_BUFFER_POINTER 0x4808 -#define CHANNEL0_RX_NEXT_POINTER 0x480c -#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 -#define CHANNEL0_TX_CMD_STATUS 0x4C00 -#define CHANNEL0_TX_PACKET_SIZE 0x4C04 -#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 -#define CHANNEL0_TX_NEXT_POINTER 0x4C0c -#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 -#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 -#define CHANNEL1_CONFIGURATION_REGISTER 0x5000 -#define CHANNEL1_COMMAND_REGISTER 0x5008 -#define CHANNEL1_RX_CMD_STATUS 0x5800 -#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804 -#define CHANNEL1_RX_BUFFER_POINTER 0x5808 -#define CHANNEL1_RX_NEXT_POINTER 0x580c -#define CHANNEL1_TX_CMD_STATUS 0x5C00 -#define CHANNEL1_TX_PACKET_SIZE 0x5C04 -#define CHANNEL1_TX_BUFFER_POINTER 0x5C08 -#define CHANNEL1_TX_NEXT_POINTER 0x5C0c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810 -#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10 -#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14 -#define CHANNEL2_CONFIGURATION_REGISTER 0x6000 -#define CHANNEL2_COMMAND_REGISTER 0x6008 -#define CHANNEL2_RX_CMD_STATUS 0x6800 -#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804 -#define CHANNEL2_RX_BUFFER_POINTER 0x6808 -#define CHANNEL2_RX_NEXT_POINTER 0x680c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_TX_CMD_STATUS 0x6C00 -#define CHANNEL2_TX_PACKET_SIZE 0x6C04 -#define CHANNEL2_TX_BUFFER_POINTER 0x6C08 -#define CHANNEL2_TX_NEXT_POINTER 0x6C0c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 -#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 - -/* SDMA Interrupt */ - -#define SDMA_CAUSE 0xb820 -#define SDMA_MASK 0xb8a0 - - -/****************************************/ -/* Baude Rate Generators Registers */ -/****************************************/ - -/* BRG 0 */ - -#define BRG0_CONFIGURATION_REGISTER 0xb200 -#define BRG0_BAUDE_TUNING_REGISTER 0xb204 - -/* BRG 1 */ - -#define BRG1_CONFIGURATION_REGISTER 0xb208 -#define BRG1_BAUDE_TUNING_REGISTER 0xb20c - -/* BRG 2 */ - -#define BRG2_CONFIGURATION_REGISTER 0xb210 -#define BRG2_BAUDE_TUNING_REGISTER 0xb214 - -/* BRG Interrupts */ - -#define BRG_CAUSE_REGISTER 0xb834 -#define BRG_MASK_REGISTER 0xb8b4 - -/* MISC */ - -#define MAIN_ROUTING_REGISTER 0xb400 -#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 -#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 -#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c -#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 -#define WATCHDOG_VALUE_REGISTER 0xb414 - - -/****************************************/ -/* Flex TDM Registers */ -/****************************************/ - -/* FTDM Port */ - -#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 -#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 -#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 -#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c -#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 -#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 -#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 - -/* FTDM Interrupts */ - -#define FTDM_CAUSE_REGISTER 0xb830 -#define FTDM_MASK_REGISTER 0xb8b0 - - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define GPP_IO_CONTROL 0xf100 -#define GPP_LEVEL_CONTROL 0xf110 -#define GPP_VALUE 0xf104 -#define GPP_INTERRUPT_CAUSE 0xf108 -#define GPP_INTERRUPT_MASK 0xf10c - -#define MPP_CONTROL0 0xf000 -#define MPP_CONTROL1 0xf004 -#define MPP_CONTROL2 0xf008 -#define MPP_CONTROL3 0xf00c -#define DEBUG_PORT_MULTIPLEX 0xf014 -#define SERIAL_PORT_MULTIPLEX 0xf010 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define I2C_SLAVE_ADDRESS 0xc000 -#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 -#define I2C_DATA 0xc004 -#define I2C_CONTROL 0xc008 -#define I2C_STATUS_BAUDE_RATE 0xc00C -#define I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* MPSC Registers */ -/****************************************/ - -/* MPSC0 */ - -#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 -#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 -#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 -#define CHANNEL0_REGISTER1 0x800c -#define CHANNEL0_REGISTER2 0x8010 -#define CHANNEL0_REGISTER3 0x8014 -#define CHANNEL0_REGISTER4 0x8018 -#define CHANNEL0_REGISTER5 0x801c -#define CHANNEL0_REGISTER6 0x8020 -#define CHANNEL0_REGISTER7 0x8024 -#define CHANNEL0_REGISTER8 0x8028 -#define CHANNEL0_REGISTER9 0x802c -#define CHANNEL0_REGISTER10 0x8030 -#define CHANNEL0_REGISTER11 0x8034 - -/* MPSC1 */ - -#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840 -#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844 -#define MPSC1_PROTOCOL_CONFIGURATION 0x8848 -#define CHANNEL1_REGISTER1 0x884c -#define CHANNEL1_REGISTER2 0x8850 -#define CHANNEL1_REGISTER3 0x8854 -#define CHANNEL1_REGISTER4 0x8858 -#define CHANNEL1_REGISTER5 0x885c -#define CHANNEL1_REGISTER6 0x8860 -#define CHANNEL1_REGISTER7 0x8864 -#define CHANNEL1_REGISTER8 0x8868 -#define CHANNEL1_REGISTER9 0x886c -#define CHANNEL1_REGISTER10 0x8870 -#define CHANNEL1_REGISTER11 0x8874 - -/* MPSC2 */ - -#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040 -#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044 -#define MPSC2_PROTOCOL_CONFIGURATION 0x9048 -#define CHANNEL2_REGISTER1 0x904c -#define CHANNEL2_REGISTER2 0x9050 -#define CHANNEL2_REGISTER3 0x9054 -#define CHANNEL2_REGISTER4 0x9058 -#define CHANNEL2_REGISTER5 0x905c -#define CHANNEL2_REGISTER6 0x9060 -#define CHANNEL2_REGISTER7 0x9064 -#define CHANNEL2_REGISTER8 0x9068 -#define CHANNEL2_REGISTER9 0x906c -#define CHANNEL2_REGISTER10 0x9070 -#define CHANNEL2_REGISTER11 0x9074 - -/* MPSCs Interrupts */ - -#define MPSC0_CAUSE 0xb824 -#define MPSC0_MASK 0xb8a4 -#define MPSC1_CAUSE 0xb828 -#define MPSC1_MASK 0xb8a8 -#define MPSC2_CAUSE 0xb82c -#define MPSC2_MASK 0xb8ac - -#endif /* __INCgt64260rh */ diff --git a/include/galileo/memory.h b/include/galileo/memory.h deleted file mode 100644 index 0c46c24d06..0000000000 --- a/include/galileo/memory.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Memory.h - Memory mappings and remapping functions declarations */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCmemoryh -#define __INCmemoryh - -/* includes */ - -#include "core.h" - -/* defines */ - -#define DONT_MODIFY 0xffffffff -#define PARITY_SUPPORT 0x40000000 - -#define _8BIT 0x00000000 -#define _16BIT 0x00100000 -#define _32BIT 0x00200000 -#define _64BIT 0x00300000 - -/* typedefs */ - - typedef struct deviceParam -{ /* boundary values */ - unsigned int turnOff; /* 0x0 - 0xf */ - unsigned int acc2First; /* 0x0 - 0x1f */ - unsigned int acc2Next; /* 0x0 - 0x1f */ - unsigned int ale2Wr; /* 0x0 - 0xf */ - unsigned int wrLow; /* 0x0 - 0xf */ - unsigned int wrHigh; /* 0x0 - 0xf */ - unsigned int deviceWidth; /* in Bytes */ -} DEVICE_PARAM; - -typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; -typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; - -typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \ - MEM_REGION3,MEM_REGION4,MEM_REGION5, \ - MEM_REGION6,MEM_REGION7} \ - MEMORY_PROTECT_REGION; -typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \ - MEMORY_ACCESS; -typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \ - MEMORY_ACCESS_WRITE; -typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \ - MEMORY_CACHE_PROTECT; -typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \ - MEMORY_SNOOP_TYPE; -typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \ - MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ - MEMORY_SNOOP_REGION; - -/* functions */ -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); -unsigned int memoryGetDeviceBaseAddress(DEVICE device); -unsigned int memoryGetBankSize(MEMORY_BANK bank); -unsigned int memoryGetDeviceSize(DEVICE device); -unsigned int memoryGetDeviceWidth(DEVICE device); - -/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ -bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); -bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); - -/* Change the Internal Register Base Address to a new given Address. */ -bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); -/* returns internal Register Space Base Address. */ -unsigned int memoryGetInternalRegistersSpace(void); -/* Configurate the protection feature to a given space. */ -bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memoryAccess, - MEMORY_ACCESS_WRITE memoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength); -/* Configurate the snoop feature to a given space. */ -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); -bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -#endif /* __INCmemoryh */ diff --git a/include/galileo/pci.h b/include/galileo/pci.h deleted file mode 100644 index 6ed8b95df0..0000000000 --- a/include/galileo/pci.h +++ /dev/null @@ -1,113 +0,0 @@ -/* PCI.h - PCI functions header file */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCpcih -#define __INCpcih - -/* includes */ - -#include "core.h" -#include "memory.h" - -/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ -#define PCI_MAX_DEVICES 22 - - -/* Macros */ -#define SELF 32 - -/* Defines for the access regions. */ -#define PREFETCH_ENABLE BIT12 -#define PREFETCH_DISABLE NO_BIT -#define DELAYED_READ_ENABLE BIT13 -/* #define CACHING_ENABLE BIT14 */ -/* aggressive prefetch: PCI slave prefetch two burst in advance*/ -#define AGGRESSIVE_PREFETCH BIT16 -/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_LINE_AGGRESSIVE_PREFETCH BIT17 -/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18 -#define MAX_BURST_4 NO_BIT -#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */ -#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */ -#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ -#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ -#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ -#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ -#define PCI_ACCESS_PROTECT BIT28 -#define PCI_WRITE_PROTECT BIT29 - -/* typedefs */ - -typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, - REGION6,REGION7} PCI_ACCESS_REGIONS; - -typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; -typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; - -typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} - PCI_SNOOP_TYPE; -typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, - PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} - PCI_SNOOP_REGION; - -typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; -typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, - PCI_REGION2,PCI_REGION3, - PCI_IO} - PCI_REGION; - -/* read/write configuration registers on local PCI bus. */ -void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data); -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum); - -/* read/write configuration registers on another PCI bus. */ -void pciOverBridgeWriteConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data); -unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum); - -/* Master`s memory space */ -bool pciMapSpace(PCI_HOST host, PCI_REGION region, - unsigned int remapBase, - unsigned int deviceBase, - unsigned int deviceLength); -unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); -unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); - -/* Slave`s memory space */ -void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, - unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); - -/* PCI region options */ - -bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength); - -void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); - -/* PCI arbiter */ - -bool pciArbiterEnable(PCI_HOST host); -bool pciArbiterDisable(PCI_HOST host); -bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5); -bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -#endif /* __INCpcih */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index f50e0e2733..8a5efe732a 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -2,7 +2,7 @@ * (C) Copyright 2010 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __GDSYS_FPGA_H @@ -43,10 +43,12 @@ struct ihs_gpio { }; struct ihs_i2c { - u16 write_mailbox; + u16 interrupt_status; + u16 interrupt_enable; u16 write_mailbox_ext; - u16 read_mailbox; + u16 write_mailbox; u16 read_mailbox_ext; + u16 read_mailbox; }; struct ihs_osd { @@ -59,6 +61,22 @@ struct ihs_osd { u16 y_pos; }; +struct ihs_mdio { + u16 control; + u16 address_data; + u16 rx_data; +}; + +struct ihs_io_ep { + u16 transmit_data; + u16 rx_tx_control; + u16 receive_data; + u16 rx_tx_status; + u16 reserved; + u16 device_address; + u16 target_address; +}; + #ifdef CONFIG_NEO struct ihs_fpga { u16 reflection_low; /* 0x0000 */ @@ -84,7 +102,6 @@ struct ihs_fpga { #endif #ifdef CONFIG_IO64 - struct ihs_fpga_channel { u16 status_int; u16 config_int; @@ -118,12 +135,50 @@ struct ihs_fpga { u16 versions; /* 0x0002 */ u16 fpga_version; /* 0x0004 */ u16 fpga_features; /* 0x0006 */ - u16 reserved_0[6]; /* 0x0008 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[4]; /* 0x000c */ + struct ihs_gpio gpio; /* 0x0014 */ + u16 mpc3w_control; /* 0x001a */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + struct ihs_i2c i2c; /* 0x0040 */ + u16 reserved_4[10]; /* 0x004c */ + u16 mc_int; /* 0x0060 */ + u16 mc_int_en; /* 0x0062 */ + u16 mc_status; /* 0x0064 */ + u16 mc_control; /* 0x0066 */ + u16 mc_tx_data; /* 0x0068 */ + u16 mc_tx_address; /* 0x006a */ + u16 mc_tx_cmd; /* 0x006c */ + u16 mc_res; /* 0x006e */ + u16 mc_rx_cmd_status; /* 0x0070 */ + u16 mc_rx_data; /* 0x0072 */ + u16 reserved_5[69]; /* 0x0074 */ + u16 reflection_high; /* 0x00fe */ + struct ihs_osd osd; /* 0x0100 */ + u16 reserved_6[889]; /* 0x010e */ + u16 videomem[31736]; /* 0x0800 */ +}; +#endif + +#ifdef CONFIG_HRCON +struct ihs_fpga { + u16 reflection_low; /* 0x0000 */ + u16 versions; /* 0x0002 */ + u16 fpga_version; /* 0x0004 */ + u16 fpga_features; /* 0x0006 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[4]; /* 0x000c */ struct ihs_gpio gpio; /* 0x0014 */ u16 mpc3w_control; /* 0x001a */ - u16 reserved_1[19]; /* 0x001c */ - u16 videocontrol; /* 0x0042 */ - u16 reserved_2[14]; /* 0x0044 */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + struct ihs_i2c i2c; /* 0x0040 */ + u16 reserved_4[10]; /* 0x004c */ u16 mc_int; /* 0x0060 */ u16 mc_int_en; /* 0x0062 */ u16 mc_status; /* 0x0064 */ @@ -134,10 +189,10 @@ struct ihs_fpga { u16 mc_res; /* 0x006e */ u16 mc_rx_cmd_status; /* 0x0070 */ u16 mc_rx_data; /* 0x0072 */ - u16 reserved_3[69]; /* 0x0074 */ + u16 reserved_5[69]; /* 0x0074 */ u16 reflection_high; /* 0x00fe */ struct ihs_osd osd; /* 0x0100 */ - u16 reserved_4[889]; /* 0x010e */ + u16 reserved_6[889]; /* 0x010e */ u16 videomem[31736]; /* 0x0800 */ }; #endif @@ -150,15 +205,13 @@ struct ihs_fpga { u16 fpga_features; /* 0x0006 */ u16 reserved_0[10]; /* 0x0008 */ u16 extended_interrupt; /* 0x001c */ - u16 reserved_1[9]; /* 0x001e */ - struct ihs_i2c i2c; /* 0x0030 */ - u16 reserved_2[16]; /* 0x0038 */ + u16 reserved_1[29]; /* 0x001e */ u16 mpc3w_control; /* 0x0058 */ - u16 reserved_3[34]; /* 0x005a */ - u16 videocontrol; /* 0x009e */ - u16 reserved_4[176]; /* 0x00a0 */ + u16 reserved_2[3]; /* 0x005a */ + struct ihs_i2c i2c; /* 0x0060 */ + u16 reserved_3[205]; /* 0x0066 */ struct ihs_osd osd; /* 0x0200 */ - u16 reserved_5[761]; /* 0x020e */ + u16 reserved_4[761]; /* 0x020e */ u16 videomem[31736]; /* 0x0800 */ }; #endif diff --git a/include/hash.h b/include/hash.h index e92d27218c..f4eb100de0 100644 --- a/include/hash.h +++ b/include/hash.h @@ -6,6 +6,17 @@ #ifndef _HASH_H #define _HASH_H +/* + * Maximum digest size for all algorithms we support. Having this value + * avoids a malloc() or C99 local declaration in common/cmd_hash.c. + */ +#define HASH_MAX_DIGEST_SIZE 32 + +enum { + HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */ + HASH_FLAG_ENV = 1 << 1, /* Allow env vars */ +}; + #if defined(CONFIG_SHA1SUM_VERIFY) || defined(CONFIG_CRC32_VERIFY) #define CONFIG_HASH_VERIFY #endif @@ -27,19 +38,45 @@ struct hash_algo { void (*hash_func_ws)(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz); int chunk_size; /* Watchdog chunk size */ + /* + * hash_init: Create the context for progressive hashing + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -1 on error + */ + int (*hash_init)(struct hash_algo *algo, void **ctxp); + /* + * hash_update: Perform hashing on the given buffer + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -1 on error + */ + int (*hash_update)(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last); + /* + * hash_finish: Write the hash result to the given buffer + * + * The context is freed by this function. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the buffer for the result + * @size: Size of the buffer for the result + * @return 0 if ok, -ENOSPC if size of the result buffer is too small + * or -1 on other errors + */ + int (*hash_finish)(struct hash_algo *algo, void *ctx, void *dest_buf, + int size); }; -/* - * Maximum digest size for all algorithms we support. Having this value - * avoids a malloc() or C99 local declaration in common/cmd_hash.c. - */ -#define HASH_MAX_DIGEST_SIZE 32 - -enum { - HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */ - HASH_FLAG_ENV = 1 << 1, /* Allow env vars */ -}; - +#ifndef USE_HOSTCC /** * hash_command: Process a hash command for a particular algorithm * @@ -77,4 +114,48 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, int hash_block(const char *algo_name, const void *data, unsigned int len, uint8_t *output, int *output_size); +/** + * hash_show() - Print out a hash algorithm and value + * + * You will get a message like this (without a newline at the end): + * + * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257" + * + * @algo: Algorithm used for hash + * @addr: Address of data that was hashed + * @len: Length of data that was hashed + * @output: Hash value to display + */ +void hash_show(struct hash_algo *algo, ulong addr, ulong len, + uint8_t *output); + +#endif /* !USE_HOSTCC */ + +/** + * hash_lookup_algo() - Look up the hash_algo struct for an algorithm + * + * The function returns the pointer to the struct or -EPROTONOSUPPORT if the + * algorithm is not available. + * + * @algo_name: Hash algorithm to look up + * @algop: Pointer to the hash_algo struct if found + * + * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm. + */ +int hash_lookup_algo(const char *algo_name, struct hash_algo **algop); + +/** + * hash_progressive_lookup_algo() - Look up hash_algo for prog. hash support + * + * The function returns the pointer to the struct or -EPROTONOSUPPORT if the + * algorithm is not available with progressive hash support. + * + * @algo_name: Hash algorithm to look up + * @algop: Pointer to the hash_algo struct if found + * + * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm. + */ +int hash_progressive_lookup_algo(const char *algo_name, + struct hash_algo **algop); + #endif diff --git a/include/hush.h b/include/hush.h deleted file mode 100644 index 595303a652..0000000000 --- a/include/hush.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _HUSH_H_ -#define _HUSH_H_ - -#define FLAG_EXIT_FROM_LOOP 1 -#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ -#define FLAG_REPARSING (1 << 2) /* >=2nd pass */ - -extern int u_boot_hush_start(void); -extern int parse_string_outer(const char *, int); -extern int parse_file_outer(void); - -int set_local_var(const char *s, int flg_export); -void unset_local_var(const char *name); -char *get_local_var(const char *s); - -#if defined(CONFIG_HUSH_INIT_VAR) -extern int hush_init_var (void); -#endif -#endif diff --git a/include/i2c.h b/include/i2c.h index d8674efe58..27fe00f173 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -17,6 +17,432 @@ #ifndef _I2C_H_ #define _I2C_H_ +/* + * For now there are essentially two parts to this file - driver model + * here at the top, and the older code below (with CONFIG_SYS_I2C being + * most recent). The plan is to migrate everything to driver model. + * The driver model structures and API are separate as they are different + * enough as to be incompatible for compilation purposes. + */ + +#ifdef CONFIG_DM_I2C + +enum dm_i2c_chip_flags { + DM_I2C_CHIP_10BIT = 1 << 0, /* Use 10-bit addressing */ + DM_I2C_CHIP_RD_ADDRESS = 1 << 1, /* Send address for each read byte */ + DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */ +}; + +/** + * struct dm_i2c_chip - information about an i2c chip + * + * An I2C chip is a device on the I2C bus. It sits at a particular address + * and normally supports 7-bit or 10-bit addressing. + * + * To obtain this structure, use dev_get_parent_platdata(dev) where dev is + * the chip to examine. + * + * @chip_addr: Chip address on bus + * @offset_len: Length of offset in bytes. A single byte offset can + * represent up to 256 bytes. A value larger than 1 may be + * needed for larger devices. + * @flags: Flags for this chip (dm_i2c_chip_flags) + * @emul: Emulator for this chip address (only used for emulation) + */ +struct dm_i2c_chip { + uint chip_addr; + uint offset_len; + uint flags; +#ifdef CONFIG_SANDBOX + struct udevice *emul; +#endif +}; + +/** + * struct dm_i2c_bus- information about an i2c bus + * + * An I2C bus contains 0 or more chips on it, each at its own address. The + * bus can operate at different speeds (measured in Hz, typically 100KHz + * or 400KHz). + * + * To obtain this structure, use bus->uclass_priv where bus is the I2C + * bus udevice. + * + * @speed_hz: Bus speed in hertz (typically 100000) + */ +struct dm_i2c_bus { + int speed_hz; +}; + +/** + * dm_i2c_read() - read bytes from an I2C chip + * + * To obtain an I2C device (called a 'chip') given the I2C bus address you + * can use i2c_get_chip(). To obtain a bus by bus number use + * uclass_get_device_by_seq(UCLASS_I2C, ). + * + * To set the address length of a devce use i2c_set_addr_len(). It + * defaults to 1. + * + * @dev: Chip to read from + * @offset: Offset within chip to start reading + * @buffer: Place to put data + * @len: Number of bytes to read + * + * @return 0 on success, -ve on failure + */ +int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len); + +/** + * dm_i2c_write() - write bytes to an I2C chip + * + * See notes for dm_i2c_read() above. + * + * @dev: Chip to write to + * @offset: Offset within chip to start writing + * @buffer: Buffer containing data to write + * @len: Number of bytes to write + * + * @return 0 on success, -ve on failure + */ +int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, + int len); + +/** + * dm_i2c_probe() - probe a particular chip address + * + * This can be useful to check for the existence of a chip on the bus. + * It is typically implemented by writing the chip address to the bus + * and checking that the chip replies with an ACK. + * + * @bus: Bus to probe + * @chip_addr: 7-bit address to probe (10-bit and others are not supported) + * @chip_flags: Flags for the probe (see enum dm_i2c_chip_flags) + * @devp: Returns the device found, or NULL if none + * @return 0 if a chip was found at that address, -ve if not + */ +int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, + struct udevice **devp); + +/** + * i2c_set_bus_speed() - set the speed of a bus + * + * @bus: Bus to adjust + * @speed: Requested speed in Hz + * @return 0 if OK, -EINVAL for invalid values + */ +int i2c_set_bus_speed(struct udevice *bus, unsigned int speed); + +/** + * i2c_get_bus_speed() - get the speed of a bus + * + * @bus: Bus to check + * @return speed of selected I2C bus in Hz, -ve on error + */ +int i2c_get_bus_speed(struct udevice *bus); + +/** + * i2c_set_chip_flags() - set flags for a chip + * + * Typically addresses are 7 bits, but for 10-bit addresses you should set + * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing. + * + * @dev: Chip to adjust + * @flags: New flags + * @return 0 if OK, -EINVAL if value is unsupported, other -ve value on error + */ +int i2c_set_chip_flags(struct udevice *dev, uint flags); + +/** + * i2c_get_chip_flags() - get flags for a chip + * + * @dev: Chip to check + * @flagsp: Place to put flags + * @return 0 if OK, other -ve value on error + */ +int i2c_get_chip_flags(struct udevice *dev, uint *flagsp); + +/** + * i2c_set_offset_len() - set the offset length for a chip + * + * The offset used to access a chip may be up to 4 bytes long. Typically it + * is only 1 byte, which is enough for chips with 256 bytes of memory or + * registers. The default value is 1, but you can call this function to + * change it. + * + * @offset_len: New offset length value (typically 1 or 2) + */ + +int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len); +/** + * i2c_deblock() - recover a bus that is in an unknown state + * + * See the deblock() method in 'struct dm_i2c_ops' for full information + * + * @bus: Bus to recover + * @return 0 if OK, -ve on error + */ +int i2c_deblock(struct udevice *bus); + +#ifdef CONFIG_DM_I2C_COMPAT +/** + * i2c_probe() - Compatibility function for driver model + * + * Calls dm_i2c_probe() on the current bus + */ +int i2c_probe(uint8_t chip_addr); + +/** + * i2c_read() - Compatibility function for driver model + * + * Calls dm_i2c_read() with the device corresponding to @chip_addr, and offset + * set to @addr. @alen must match the current setting for the device. + */ +int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, + int len); + +/** + * i2c_write() - Compatibility function for driver model + * + * Calls dm_i2c_write() with the device corresponding to @chip_addr, and offset + * set to @addr. @alen must match the current setting for the device. + */ +int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, + int len); + +/** + * i2c_get_bus_num_fdt() - Compatibility function for driver model + * + * @return the bus number associated with the given device tree node + */ +int i2c_get_bus_num_fdt(int node); + +/** + * i2c_get_bus_num() - Compatibility function for driver model + * + * @return the 'current' bus number + */ +unsigned int i2c_get_bus_num(void); + +/** + * i2c_set_bus_num() - Compatibility function for driver model + * + * Sets the 'current' bus + */ +int i2c_set_bus_num(unsigned int bus); + +static inline void I2C_SET_BUS(unsigned int bus) +{ + i2c_set_bus_num(bus); +} + +static inline unsigned int I2C_GET_BUS(void) +{ + return i2c_get_bus_num(); +} + +/** + * i2c_init() - Compatibility function for driver model + * + * This function does nothing. + */ +void i2c_init(int speed, int slaveaddr); + +/** + * board_i2c_init() - Compatibility function for driver model + * + * @param blob Device tree blbo + * @return the number of I2C bus + */ +void board_i2c_init(const void *blob); + +#endif + +/* + * Not all of these flags are implemented in the U-Boot API + */ +enum dm_i2c_msg_flags { + I2C_M_TEN = 0x0010, /* ten-bit chip address */ + I2C_M_RD = 0x0001, /* read data, from slave to master */ + I2C_M_STOP = 0x8000, /* send stop after this message */ + I2C_M_NOSTART = 0x4000, /* no start before this message */ + I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */ + I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */ + I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */ + I2C_M_RECV_LEN = 0x0400, /* length is first received byte */ +}; + +/** + * struct i2c_msg - an I2C message + * + * @addr: Slave address + * @flags: Flags (see enum dm_i2c_msg_flags) + * @len: Length of buffer in bytes, may be 0 for a probe + * @buf: Buffer to send/receive, or NULL if no data + */ +struct i2c_msg { + uint addr; + uint flags; + uint len; + u8 *buf; +}; + +/** + * struct i2c_msg_list - a list of I2C messages + * + * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem + * appropriate in U-Boot. + * + * @msg: Pointer to i2c_msg array + * @nmsgs: Number of elements in the array + */ +struct i2c_msg_list { + struct i2c_msg *msgs; + uint nmsgs; +}; + +/** + * struct dm_i2c_ops - driver operations for I2C uclass + * + * Drivers should support these operations unless otherwise noted. These + * operations are intended to be used by uclass code, not directly from + * other code. + */ +struct dm_i2c_ops { + /** + * xfer() - transfer a list of I2C messages + * + * @bus: Bus to read from + * @msg: List of messages to transfer + * @nmsgs: Number of messages in the list + * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte, + * -ECOMM if the speed cannot be supported, -EPROTO if the chip + * flags cannot be supported, other -ve value on some other error + */ + int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs); + + /** + * probe_chip() - probe for the presense of a chip address + * + * This function is optional. If omitted, the uclass will send a zero + * length message instead. + * + * @bus: Bus to probe + * @chip_addr: Chip address to probe + * @chip_flags: Probe flags (enum dm_i2c_chip_flags) + * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back + * to default probem other -ve value on error + */ + int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags); + + /** + * set_bus_speed() - set the speed of a bus (optional) + * + * The bus speed value will be updated by the uclass if this function + * does not return an error. This method is optional - if it is not + * provided then the driver can read the speed from + * bus->uclass_priv->speed_hz + * + * @bus: Bus to adjust + * @speed: Requested speed in Hz + * @return 0 if OK, -EINVAL for invalid values + */ + int (*set_bus_speed)(struct udevice *bus, unsigned int speed); + + /** + * get_bus_speed() - get the speed of a bus (optional) + * + * Normally this can be provided by the uclass, but if you want your + * driver to check the bus speed by looking at the hardware, you can + * implement that here. This method is optional. This method would + * normally be expected to return bus->uclass_priv->speed_hz. + * + * @bus: Bus to check + * @return speed of selected I2C bus in Hz, -ve on error + */ + int (*get_bus_speed)(struct udevice *bus); + + /** + * set_flags() - set the flags for a chip (optional) + * + * This is generally implemented by the uclass, but drivers can + * check the value to ensure that unsupported options are not used. + * This method is optional. If provided, this method will always be + * called when the flags change. + * + * @dev: Chip to adjust + * @flags: New flags value + * @return 0 if OK, -EINVAL if value is unsupported + */ + int (*set_flags)(struct udevice *dev, uint flags); + + /** + * deblock() - recover a bus that is in an unknown state + * + * I2C is a synchronous protocol and resets of the processor in the + * middle of an access can block the I2C Bus until a powerdown of + * the full unit is done. This is because slaves can be stuck + * waiting for addition bus transitions for a transaction that will + * never complete. Resetting the I2C master does not help. The only + * way is to force the bus through a series of transitions to make + * sure that all slaves are done with the transaction. This method + * performs this 'deblocking' if support by the driver. + * + * This method is optional. + */ + int (*deblock)(struct udevice *bus); +}; + +#define i2c_get_ops(dev) ((struct dm_i2c_ops *)(dev)->driver->ops) + +/** + * i2c_get_chip() - get a device to use to access a chip on a bus + * + * This returns the device for the given chip address. The device can then + * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc. + * + * @bus: Bus to examine + * @chip_addr: Chip address for the new device + * @offset_len: Length of a register offset in bytes (normally 1) + * @devp: Returns pointer to new device if found or -ENODEV if not + * found + */ +int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, + struct udevice **devp); + +/** + * i2c_get_chip() - get a device to use to access a chip on a bus number + * + * This returns the device for the given chip address on a particular bus + * number. + * + * @busnum: Bus number to examine + * @chip_addr: Chip address for the new device + * @offset_len: Length of a register offset in bytes (normally 1) + * @devp: Returns pointer to new device if found or -ENODEV if not + * found + */ +int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, + struct udevice **devp); + +/** + * i2c_chip_ofdata_to_platdata() - Decode standard I2C platform data + * + * This decodes the chip address from a device tree node and puts it into + * its dm_i2c_chip structure. This should be called in your driver's + * ofdata_to_platdata() method. + * + * @blob: Device tree blob + * @node: Node offset to read from + * @spi: Place to put the decoded information + */ +int i2c_chip_ofdata_to_platdata(const void *blob, int node, + struct dm_i2c_chip *chip); + +#endif + +#ifndef CONFIG_DM_I2C + /* * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING * @@ -68,6 +494,7 @@ struct i2c_adapter { uint (*set_bus_speed)(struct i2c_adapter *adap, uint speed); int speed; + int waitdelay; int slaveaddr; int init_done; int hwadapnr; @@ -135,6 +562,8 @@ extern struct i2c_bus_hose i2c_bus[]; #define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"} #define I2C_MUX_PCA9547_ID 4 #define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"} +#define I2C_MUX_PCA9548_ID 5 +#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"} #endif #ifndef I2C_SOFT_DECLARATIONS @@ -145,7 +574,7 @@ extern struct i2c_bus_hose i2c_bus[]; # elif (defined(CONFIG_AT91RM9200) || \ defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ - defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) + defined(CONFIG_AT91SAM9263)) # define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; # else # define I2C_SOFT_DECLARATIONS @@ -390,7 +819,7 @@ unsigned int i2c_get_bus_speed(void); # if !defined(CONFIG_SYS_MAX_I2C_BUS) # define CONFIG_SYS_MAX_I2C_BUS 2 # endif -# define I2C_MULTI_BUS 0 +# define I2C_MULTI_BUS 1 #else # define CONFIG_SYS_MAX_I2C_BUS 1 # define I2C_MULTI_BUS 0 @@ -448,4 +877,7 @@ int i2c_get_bus_num_fdt(int node); * @return 0 if port was reset, -1 if not found */ int i2c_reset_port_fdt(const void *blob, int node); + +#endif /* !CONFIG_DM_I2C */ + #endif /* _I2C_H_ */ diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h new file mode 100644 index 0000000000..ea6c962a39 --- /dev/null +++ b/include/i2c_eeprom.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __I2C_EEPROM +#define __I2C_EEPROM + +struct i2c_eeprom_ops { + int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size); + int (*write)(struct udevice *dev, int offset, const uint8_t *buf, + int size); +}; + +struct i2c_eeprom { +}; + +#endif diff --git a/include/i2s.h b/include/i2s.h index aee52e7f14..8dd2cc388a 100644 --- a/include/i2s.h +++ b/include/i2s.h @@ -85,6 +85,7 @@ struct i2stx_info { unsigned int bitspersample; /* bits per sample */ unsigned int channels; /* audio channels */ unsigned int base_address; /* I2S Register Base */ + unsigned int id; /* I2S controller id */ }; /* diff --git a/include/i8042.h b/include/i8042.h index 963061920c..58c85ec5f0 100644 --- a/include/i8042.h +++ b/include/i8042.h @@ -72,8 +72,10 @@ void i8042_flush(void); */ int i8042_disable(void); +struct stdio_dev; + int i8042_kbd_init(void); -int i8042_tstc(void); -int i8042_getc(void); +int i8042_tstc(struct stdio_dev *dev); +int i8042_getc(struct stdio_dev *dev); #endif /* _I8042_H_ */ diff --git a/include/ide.h b/include/ide.h index 0424d045a1..d5e05e97cb 100644 --- a/include/ide.h +++ b/include/ide.h @@ -23,6 +23,7 @@ extern ulong ide_bus_offset[]; #define LED_IDE2 0x02 #define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */ +void ide_led(uchar led, uchar status); #endif /* CONFIG_IDE_LED */ #ifdef CONFIG_SYS_64BIT_LBA @@ -66,12 +67,16 @@ void ide_write_data(int dev, const ulong *sect_buf, int words); /* * I/O function overrides */ +unsigned char ide_inb(int dev, int port); +void ide_outb(int dev, int port, unsigned char val); void ide_input_swap_data(int dev, ulong *sect_buf, int words); void ide_input_data(int dev, ulong *sect_buf, int words); void ide_output_data(int dev, const ulong *sect_buf, int words); void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts); void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts); +void ide_led(uchar led, uchar status); + /** * board_start_ide() - Start up the board IDE interfac * diff --git a/include/image.h b/include/image.h index f93a39389a..0e6af00c16 100644 --- a/include/image.h +++ b/include/image.h @@ -45,6 +45,7 @@ struct lmb; #endif /* USE_HOSTCC */ #if defined(CONFIG_FIT) +#include #include #include # ifdef CONFIG_SPL_BUILD @@ -57,15 +58,25 @@ struct lmb; # ifdef CONFIG_SPL_SHA1_SUPPORT # define IMAGE_ENABLE_SHA1 1 # endif +# ifdef CONFIG_SPL_SHA256_SUPPORT +# define IMAGE_ENABLE_SHA256 1 +# endif # else # define CONFIG_CRC32 /* FIT images need CRC32 support */ # define CONFIG_MD5 /* and MD5 */ # define CONFIG_SHA1 /* and SHA1 */ +# define CONFIG_SHA256 /* and SHA256 */ # define IMAGE_ENABLE_CRC32 1 # define IMAGE_ENABLE_MD5 1 # define IMAGE_ENABLE_SHA1 1 +# define IMAGE_ENABLE_SHA256 1 # endif +#ifdef CONFIG_FIT_DISABLE_SHA256 +#undef CONFIG_SHA256 +#undef IMAGE_ENABLE_SHA256 +#endif + #ifndef IMAGE_ENABLE_CRC32 #define IMAGE_ENABLE_CRC32 0 #endif @@ -78,6 +89,10 @@ struct lmb; #define IMAGE_ENABLE_SHA1 0 #endif +#ifndef IMAGE_ENABLE_SHA256 +#define IMAGE_ENABLE_SHA256 0 +#endif + #endif /* CONFIG_FIT */ #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH @@ -99,9 +114,15 @@ struct lmb; #endif #ifdef CONFIG_OF_BOARD_SETUP -# define IMAAGE_OF_BOARD_SETUP 1 +# define IMAGE_OF_BOARD_SETUP 1 +#else +# define IMAGE_OF_BOARD_SETUP 0 +#endif + +#ifdef CONFIG_OF_SYSTEM_SETUP +# define IMAGE_OF_SYSTEM_SETUP 1 #else -# define IMAAGE_OF_BOARD_SETUP 0 +# define IMAGE_OF_SYSTEM_SETUP 0 #endif /* @@ -131,6 +152,7 @@ struct lmb; #define IH_OS_INTEGRITY 21 /* INTEGRITY */ #define IH_OS_OSE 22 /* OSE */ #define IH_OS_PLAN9 23 /* Plan 9 */ +#define IH_OS_OPENRTOS 24 /* OpenRTOS */ /* * CPU Architecture Codes (supported by Linux) @@ -156,6 +178,9 @@ struct lmb; #define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */ #define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */ #define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ +#define IH_ARCH_ARM64 22 /* ARM64 */ +#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */ +#define IH_ARCH_X86_64 24 /* AMD x86_64, Intel and Via */ /* * Image Types @@ -212,6 +237,11 @@ struct lmb; #define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */ #define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ #define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ +#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ +#define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ +#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ +#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */ +#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */ /* * Compression Types @@ -252,6 +282,7 @@ typedef struct image_info { ulong image_start, image_len; /* start of image within blob, len of image */ ulong load; /* load addr for the image */ uint8_t comp, type, os; /* compression, type of image, os type */ + uint8_t arch; /* CPU architecture */ } image_info_t; /* @@ -282,6 +313,10 @@ typedef struct bootm_headers { void *fit_hdr_fdt; /* FDT blob FIT image header */ const char *fit_uname_fdt; /* FDT blob subimage node unit name */ int fit_noffset_fdt;/* FDT blob subimage node offset */ + + void *fit_hdr_setup; /* x86 setup FIT image header */ + const char *fit_uname_setup; /* x86 setup subimage node name */ + int fit_noffset_setup;/* x86 setup subimage node offset */ #endif #ifndef USE_HOSTCC @@ -392,21 +427,36 @@ void genimg_print_time(time_t timestamp); enum fit_load_op { FIT_LOAD_IGNORED, /* Ignore load address */ FIT_LOAD_OPTIONAL, /* Can be provided, but optional */ + FIT_LOAD_OPTIONAL_NON_ZERO, /* Optional, a value of 0 is ignored */ FIT_LOAD_REQUIRED, /* Must be provided */ }; +int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start, + ulong *setup_len); + #ifndef USE_HOSTCC /* Image format types, returned by _get_format() routine */ #define IMAGE_FORMAT_INVALID 0x00 +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) #define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ +#endif #define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ +#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */ +ulong genimg_get_kernel_addr_fit(char * const img_addr, + const char **fit_uname_config, + const char **fit_uname_kernel); +ulong genimg_get_kernel_addr(char * const img_addr); int genimg_get_format(const void *img_addr); int genimg_has_config(bootm_headers_t *images); ulong genimg_get_image(ulong img_addr); int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, uint8_t arch, ulong *rd_start, ulong *rd_end); +#endif + +int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch, + ulong *setup_start, ulong *setup_len); /** * fit_image_load() - load an image from a FIT @@ -416,8 +466,9 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, * out progress messages, checking the type/arch/os and optionally copying it * to the right load address. * + * The property to look up is defined by image_type. + * * @param images Boot images structure - * @param prop_name Property name to look up (FIT_..._PROP) * @param addr Address of FIT in memory * @param fit_unamep On entry this is the requested image name * (e.g. "kernel@1") or NULL to use the default. On exit @@ -435,12 +486,14 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, * @param load_op Decribes what to do with the load address * @param datap Returns address of loaded image * @param lenp Returns length of loaded image + * @return node offset of image, or -ve error code on error */ -int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, +int fit_image_load(bootm_headers_t *images, ulong addr, const char **fit_unamep, const char **fit_uname_configp, int arch, int image_type, int bootstage_id, enum fit_load_op load_op, ulong *datap, ulong *lenp); +#ifndef USE_HOSTCC /** * fit_get_node_from_config() - Look up an image a FIT by type * @@ -585,8 +638,8 @@ int image_check_dcrc(const image_header_t *hdr); ulong getenv_bootm_low(void); phys_size_t getenv_bootm_size(void); phys_size_t getenv_bootm_mapsize(void); -void memmove_wd(void *to, void *from, size_t len, ulong chunksz); #endif +void memmove_wd(void *to, void *from, size_t len, ulong chunksz); static inline int image_check_magic(const image_header_t *hdr) { @@ -688,8 +741,9 @@ int bootz_setup(ulong image, ulong *start, ulong *end); #define FIT_RAMDISK_PROP "ramdisk" #define FIT_FDT_PROP "fdt" #define FIT_DEFAULT_PROP "default" +#define FIT_SETUP_PROP "setup" -#define FIT_MAX_HASH_LEN 20 /* max(crc32_len(4), sha1_len(20)) */ +#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE /* cmdline argument format parsing */ int fit_parse_conf(const char *spec, ulong addr_curr, @@ -697,6 +751,7 @@ int fit_parse_conf(const char *spec, ulong addr_curr, int fit_parse_subimage(const char *spec, ulong addr_curr, ulong *addr, const char **image_name); +int fit_get_subimage_count(const void *fit, int images_noffset); void fit_print_contents(const void *fit); void fit_image_print(const void *fit, int noffset, const char *p); @@ -820,7 +875,8 @@ int calculate_hash(const void *data, int data_len, const char *algo, #if defined(CONFIG_FIT_SIGNATURE) # ifdef USE_HOSTCC # define IMAGE_ENABLE_SIGN 1 -# define IMAGE_ENABLE_VERIFY 0 +# define IMAGE_ENABLE_VERIFY 1 +# include #else # define IMAGE_ENABLE_SIGN 0 # define IMAGE_ENABLE_VERIFY 1 @@ -831,7 +887,9 @@ int calculate_hash(const void *data, int data_len, const char *algo, #endif #ifdef USE_HOSTCC -# define gd_fdt_blob() NULL +void *image_get_host_blob(void); +void image_set_host_blob(void *host_blob); +# define gd_fdt_blob() image_get_host_blob() #else # define gd_fdt_blob() (gd->fdt_blob) #endif @@ -860,6 +918,22 @@ struct image_region { int size; }; +#if IMAGE_ENABLE_VERIFY +# include +#endif +struct checksum_algo { + const char *name; + const int checksum_len; + const int pad_len; +#if IMAGE_ENABLE_SIGN + const EVP_MD *(*calculate_sign)(void); +#endif + int (*calculate)(const char *name, + const struct image_region region[], + int region_count, uint8_t *checksum); + const uint8_t *rsa_padding; +}; + struct image_sig_algo { const char *name; /* Name of algorithm */ @@ -910,6 +984,9 @@ struct image_sig_algo { int (*verify)(struct image_sign_info *info, const struct image_region region[], int region_count, uint8_t *sig, uint sig_len); + + /* pointer to checksum algorithm */ + struct checksum_algo *checksum; }; /** @@ -975,7 +1052,11 @@ struct image_region *fit_region_make_list(const void *fit, static inline int fit_image_check_target_arch(const void *fdt, int node) { +#ifndef USE_HOSTCC return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT); +#else + return 0; +#endif } #ifdef CONFIG_FIT_VERBOSE @@ -993,4 +1074,16 @@ static inline int fit_image_check_target_arch(const void *fdt, int node) #endif /* CONFIG_FIT_VERBOSE */ #endif /* CONFIG_FIT */ +#if defined(CONFIG_ANDROID_BOOT_IMAGE) +struct andr_img_hdr; +int android_image_check_header(const struct andr_img_hdr *hdr); +int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, + ulong *os_data, ulong *os_len); +int android_image_get_ramdisk(const struct andr_img_hdr *hdr, + ulong *rd_data, ulong *rd_len); +ulong android_image_get_end(const struct andr_img_hdr *hdr); +ulong android_image_get_kload(const struct andr_img_hdr *hdr); + +#endif /* CONFIG_ANDROID_BOOT_IMAGE */ + #endif /* __IMAGE_H__ */ diff --git a/include/imx_thermal.h b/include/imx_thermal.h new file mode 100644 index 0000000000..be1365288e --- /dev/null +++ b/include/imx_thermal.h @@ -0,0 +1,17 @@ +/* + * + * (C) Copyright 2014 Freescale Semiconductor, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX_THERMAL_H_ +#define _IMX_THERMAL_H_ + +struct imx_thermal_plat { + void *regs; + int fuse_bank; + int fuse_word; +}; + +#endif /* _IMX_THERMAL_H_ */ diff --git a/include/initcall.h b/include/initcall.h index 2378077361..65f67dca83 100644 --- a/include/initcall.h +++ b/include/initcall.h @@ -6,4 +6,4 @@ typedef int (*init_fnc_t)(void); -int initcall_run_list(init_fnc_t init_sequence[]); +int initcall_run_list(const init_fnc_t init_sequence[]); diff --git a/include/inttypes.h b/include/inttypes.h new file mode 100644 index 0000000000..e2e569d0ac --- /dev/null +++ b/include/inttypes.h @@ -0,0 +1,287 @@ +/* + * Copyright (C) 1997-2001, 2004, 2007 Free Software Foundation, Inc. + * + * This file is taken from the GNU C Library v2.15, with the unimplemented + * functions removed and a few style fixes. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * ISO C99: 7.8 Format conversion of integer types + */ + +#ifndef _INTTYPES_H +#define _INTTYPES_H 1 + +#include + +/* Get a definition for wchar_t. But we must not define wchar_t itself. */ +#ifndef ____gwchar_t_defined +# ifdef __cplusplus +# define __gwchar_t wchar_t +# elif defined __WCHAR_TYPE__ +typedef __WCHAR_TYPE__ __gwchar_t; +# else +# define __need_wchar_t +# include +typedef wchar_t __gwchar_t; +# endif +# define ____gwchar_t_defined 1 +#endif + + +/* The ISO C99 standard specifies that these macros must only be + defined if explicitly requested. */ +#if !defined __cplusplus || defined __STDC_FORMAT_MACROS + +#ifdef CONFIG_USE_STDINT +# if __WORDSIZE == 64 +# define __PRI64_PREFIX "l" +# define __PRIPTR_PREFIX "l" +# else +# define __PRI64_PREFIX "ll" +# define __PRIPTR_PREFIX +# endif +#else +/* linux/types.h always uses long long for 64-bit and long for uintptr_t */ +# define __PRI64_PREFIX "ll" +# define __PRIPTR_PREFIX "l" +#endif + +/* Macros for printing format specifiers. */ + +/* Decimal notation. */ +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "d" +# define PRId64 __PRI64_PREFIX "d" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "d" +# define PRIdLEAST64 __PRI64_PREFIX "d" + +# define PRIdFAST8 "d" +# define PRIdFAST16 __PRIPTR_PREFIX "d" +# define PRIdFAST32 __PRIPTR_PREFIX "d" +# define PRIdFAST64 __PRI64_PREFIX "d" + + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "i" +# define PRIi64 __PRI64_PREFIX "i" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "i" +# define PRIiLEAST64 __PRI64_PREFIX "i" + +# define PRIiFAST8 "i" +# define PRIiFAST16 __PRIPTR_PREFIX "i" +# define PRIiFAST32 __PRIPTR_PREFIX "i" +# define PRIiFAST64 __PRI64_PREFIX "i" + +/* Octal notation. */ +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "o" +# define PRIo64 __PRI64_PREFIX "o" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "o" +# define PRIoLEAST64 __PRI64_PREFIX "o" + +# define PRIoFAST8 "o" +# define PRIoFAST16 __PRIPTR_PREFIX "o" +# define PRIoFAST32 __PRIPTR_PREFIX "o" +# define PRIoFAST64 __PRI64_PREFIX "o" + +/* Unsigned integers. */ +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "u" +# define PRIu64 __PRI64_PREFIX "u" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "u" +# define PRIuLEAST64 __PRI64_PREFIX "u" + +# define PRIuFAST8 "u" +# define PRIuFAST16 __PRIPTR_PREFIX "u" +# define PRIuFAST32 __PRIPTR_PREFIX "u" +# define PRIuFAST64 __PRI64_PREFIX "u" + +/* lowercase hexadecimal notation. */ +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "x" +# define PRIx64 __PRI64_PREFIX "x" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "x" +# define PRIxLEAST64 __PRI64_PREFIX "x" + +# define PRIxFAST8 "x" +# define PRIxFAST16 __PRIPTR_PREFIX "x" +# define PRIxFAST32 __PRIPTR_PREFIX "x" +# define PRIxFAST64 __PRI64_PREFIX "x" + +/* UPPERCASE hexadecimal notation. */ +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "X" +# define PRIX64 __PRI64_PREFIX "X" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "X" +# define PRIXLEAST64 __PRI64_PREFIX "X" + +# define PRIXFAST8 "X" +# define PRIXFAST16 __PRIPTR_PREFIX "X" +# define PRIXFAST32 __PRIPTR_PREFIX "X" +# define PRIXFAST64 __PRI64_PREFIX "X" + + +/* Macros for printing `intmax_t' and `uintmax_t'. */ +# define PRIdMAX __PRI64_PREFIX "d" +# define PRIiMAX __PRI64_PREFIX "i" +# define PRIoMAX __PRI64_PREFIX "o" +# define PRIuMAX __PRI64_PREFIX "u" +# define PRIxMAX __PRI64_PREFIX "x" +# define PRIXMAX __PRI64_PREFIX "X" + + +/* Macros for printing `intptr_t' and `uintptr_t'. */ +# define PRIdPTR __PRIPTR_PREFIX "d" +# define PRIiPTR __PRIPTR_PREFIX "i" +# define PRIoPTR __PRIPTR_PREFIX "o" +# define PRIuPTR __PRIPTR_PREFIX "u" +# define PRIxPTR __PRIPTR_PREFIX "x" +# define PRIXPTR __PRIPTR_PREFIX "X" + + +/* Macros for scanning format specifiers. */ + +/* Signed decimal notation. */ +# define SCNd8 "hhd" +# define SCNd16 "hd" +# define SCNd32 "d" +# define SCNd64 __PRI64_PREFIX "d" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "hd" +# define SCNdLEAST32 "d" +# define SCNdLEAST64 __PRI64_PREFIX "d" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 __PRIPTR_PREFIX "d" +# define SCNdFAST32 __PRIPTR_PREFIX "d" +# define SCNdFAST64 __PRI64_PREFIX "d" + +/* Signed decimal notation. */ +# define SCNi8 "hhi" +# define SCNi16 "hi" +# define SCNi32 "i" +# define SCNi64 __PRI64_PREFIX "i" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "hi" +# define SCNiLEAST32 "i" +# define SCNiLEAST64 __PRI64_PREFIX "i" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 __PRIPTR_PREFIX "i" +# define SCNiFAST32 __PRIPTR_PREFIX "i" +# define SCNiFAST64 __PRI64_PREFIX "i" + +/* Unsigned decimal notation. */ +# define SCNu8 "hhu" +# define SCNu16 "hu" +# define SCNu32 "u" +# define SCNu64 __PRI64_PREFIX "u" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "hu" +# define SCNuLEAST32 "u" +# define SCNuLEAST64 __PRI64_PREFIX "u" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 __PRIPTR_PREFIX "u" +# define SCNuFAST32 __PRIPTR_PREFIX "u" +# define SCNuFAST64 __PRI64_PREFIX "u" + +/* Octal notation. */ +# define SCNo8 "hho" +# define SCNo16 "ho" +# define SCNo32 "o" +# define SCNo64 __PRI64_PREFIX "o" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "ho" +# define SCNoLEAST32 "o" +# define SCNoLEAST64 __PRI64_PREFIX "o" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 __PRIPTR_PREFIX "o" +# define SCNoFAST32 __PRIPTR_PREFIX "o" +# define SCNoFAST64 __PRI64_PREFIX "o" + +/* Hexadecimal notation. */ +# define SCNx8 "hhx" +# define SCNx16 "hx" +# define SCNx32 "x" +# define SCNx64 __PRI64_PREFIX "x" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "hx" +# define SCNxLEAST32 "x" +# define SCNxLEAST64 __PRI64_PREFIX "x" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 __PRIPTR_PREFIX "x" +# define SCNxFAST32 __PRIPTR_PREFIX "x" +# define SCNxFAST64 __PRI64_PREFIX "x" + + +/* Macros for scanning `intmax_t' and `uintmax_t'. */ +# define SCNdMAX __PRI64_PREFIX "d" +# define SCNiMAX __PRI64_PREFIX "i" +# define SCNoMAX __PRI64_PREFIX "o" +# define SCNuMAX __PRI64_PREFIX "u" +# define SCNxMAX __PRI64_PREFIX "x" + +/* Macros for scaning `intptr_t' and `uintptr_t'. */ +# define SCNdPTR __PRIPTR_PREFIX "d" +# define SCNiPTR __PRIPTR_PREFIX "i" +# define SCNoPTR __PRIPTR_PREFIX "o" +# define SCNuPTR __PRIPTR_PREFIX "u" +# define SCNxPTR __PRIPTR_PREFIX "x" + +#endif /* C++ && format macros */ + + +#if __WORDSIZE == 64 + +/* We have to define the `uintmax_t' type using `ldiv_t'. */ +typedef struct { + long int quot; /* Quotient. */ + long int rem; /* Remainder. */ +} imaxdiv_t; + +#else + +/* We have to define the `uintmax_t' type using `lldiv_t'. */ +typedef struct { + long long int quot; /* Quotient. */ + long long int rem; /* Remainder. */ +} imaxdiv_t; + +#endif + +#endif /* inttypes.h */ diff --git a/include/iotrace.h b/include/iotrace.h new file mode 100644 index 0000000000..9bd1f167ab --- /dev/null +++ b/include/iotrace.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2014 Google, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IOTRACE_H +#define __IOTRACE_H + +#include + +/* + * This file is designed to be included in arch//include/asm/io.h. + * It redirects all IO access through a tracing/checksumming feature for + * testing purposes. + */ + +#if defined(CONFIG_IO_TRACE) && !defined(IOTRACE_IMPL) && \ + !defined(CONFIG_SPL_BUILD) + +#undef readl +#define readl(addr) iotrace_readl((const void *)(addr)) + +#undef writel +#define writel(val, addr) iotrace_writel(val, (const void *)(addr)) + +#undef readw +#define readw(addr) iotrace_readw((const void *)(addr)) + +#undef writew +#define writew(val, addr) iotrace_writew(val, (const void *)(addr)) + +#undef readb +#define readb(addr) iotrace_readb((const void *)(addr)) + +#undef writeb +#define writeb(val, addr) iotrace_writeb(val, (const void *)(addr)) + +#endif + +/* Tracing functions which mirror their io.h counterparts */ +u32 iotrace_readl(const void *ptr); +void iotrace_writel(ulong value, const void *ptr); +u16 iotrace_readw(const void *ptr); +void iotrace_writew(ulong value, const void *ptr); +u8 iotrace_readb(const void *ptr); +void iotrace_writeb(ulong value, const void *ptr); + +/** + * iotrace_reset_checksum() - Reset the iotrace checksum + */ +void iotrace_reset_checksum(void); + +/** + * iotrace_get_checksum() - Get the current checksum value + * + * @return currect checksum value + */ +u32 iotrace_get_checksum(void); + +/** + * iotrace_set_enabled() - Set whether iotracing is enabled or not + * + * This controls whether the checksum is updated and a trace record added + * for each I/O access. + * + * @enable: true to enable iotracing, false to disable + */ +void iotrace_set_enabled(int enable); + +/** + * iotrace_get_enabled() - Get whether iotracing is enabled or not + * + * @return true if enabled, false if disabled + */ +int iotrace_get_enabled(void); + +/** + * iotrace_set_buffer() - Set position and size of iotrace buffer + * + * Defines where the iotrace buffer goes, and resets the output pointer to + * the start of the buffer. + * + * The buffer can be 0 size in which case the checksum is updated but no + * trace records are writen. If the buffer is exhausted, the offset will + * continue to increase but not new data will be written. + * + * @start: Start address of buffer + * @size: Size of buffer in bytes + */ +void iotrace_set_buffer(ulong start, ulong size); + +/** + * iotrace_get_buffer() - Get buffer information + * + * @start: Returns start address of buffer + * @size: Returns size of buffer in bytes + * @offset: Returns the byte offset where the next output trace record will + * @count: Returns the number of trace records recorded + * be written (or would be if the buffer was large enough) + */ +void iotrace_get_buffer(ulong *start, ulong *size, ulong *offset, ulong *count); + +#endif /* __IOTRACE_H */ diff --git a/include/ipu.h b/include/ipu.h index b8cf52147a..b1143a4270 100644 --- a/include/ipu.h +++ b/include/ipu.h @@ -188,6 +188,14 @@ typedef union { } mem_dp_fg_sync; } ipu_channel_params_t; +/* + * Enumeration of IPU interrupts. + */ +enum ipu_irq_line { + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_DC_FC_1 = 448 + 9, +}; + /* * Bitfield of Display Interface signal polarities. */ diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h index e1943e507c..dd0d23fa52 100644 --- a/include/jffs2/load_kernel.h +++ b/include/jffs2/load_kernel.h @@ -32,8 +32,8 @@ struct part_info { struct list_head link; char *name; /* partition name */ u8 auto_name; /* set to 1 for generated name */ - u32 size; /* total size of the partition */ - u32 offset; /* offset within device */ + u64 size; /* total size of the partition */ + u64 offset; /* offset within device */ void *jffs2_priv; /* used internaly by jffs2 */ u32 mask_flags; /* kernel MTD mask flags */ u32 sector_size; /* size of sector */ @@ -44,7 +44,7 @@ struct mtdids { struct list_head link; u8 type; /* device type */ u8 num; /* device number */ - u32 size; /* device size */ + u64 size; /* device size */ char *mtd_id; /* linux kernel device id */ }; diff --git a/include/ks8721.h b/include/ks8721.h deleted file mode 100644 index 90ed178087..0000000000 --- a/include/ks8721.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * NOTE: MICREL ethernet Physical layer - * - * Version: KS8721.h - * - * Authors: Eric Benard (based on dm9161.h) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* MICREL PHYSICAL LAYER TRANSCEIVER KS8721 */ - -#define KS8721_BMCR 0 -#define KS8721_BMSR 1 -#define KS8721_PHYID1 2 -#define KS8721_PHYID2 3 -#define KS8721_ANAR 4 -#define KS8721_ANLPAR 5 -#define KS8721_ANER 6 -#define KS8721_RECR 15 -#define KS8721_MDINTR 27 -#define KS8721_100BT 31 - -/* --Bit definitions: KS8721_BMCR */ -#define KS8721_RESET (1 << 15) -#define KS8721_LOOPBACK (1 << 14) -#define KS8721_SPEED_SELECT (1 << 13) -#define KS8721_AUTONEG (1 << 12) -#define KS8721_POWER_DOWN (1 << 11) -#define KS8721_ISOLATE (1 << 10) -#define KS8721_RESTART_AUTONEG (1 << 9) -#define KS8721_DUPLEX_MODE (1 << 8) -#define KS8721_COLLISION_TEST (1 << 7) -#define KS8721_DISABLE (1 << 0) - -/*--Bit definitions: KS8721_BMSR */ -#define KS8721_100BASE_T4 (1 << 15) -#define KS8721_100BASE_TX_FD (1 << 14) -#define KS8721_100BASE_T4_HD (1 << 13) -#define KS8721_10BASE_T_FD (1 << 12) -#define KS8721_10BASE_T_HD (1 << 11) -#define KS8721_MF_PREAMB_SUPPR (1 << 6) -#define KS8721_AUTONEG_COMP (1 << 5) -#define KS8721_REMOTE_FAULT (1 << 4) -#define KS8721_AUTONEG_ABILITY (1 << 3) -#define KS8721_LINK_STATUS (1 << 2) -#define KS8721_JABBER_DETECT (1 << 1) -#define KS8721_EXTEND_CAPAB (1 << 0) - -/*--Bit definitions: KS8721_PHYID */ -#define KS8721_PHYID_OUI 0x0885 -#define KS8721_LSB_MASK 0x3F - -#define KS8721BL_MODEL 0x21 -#define KS8721_MODELMASK 0x3F0 -#define KS8721BL_REV 0x9 -#define KS8721_REVMASK 0xF - -/*--Bit definitions: KS8721_ANAR, KS8721_ANLPAR */ -#define KS8721_NP (1 << 15) -#define KS8721_ACK (1 << 14) -#define KS8721_RF (1 << 13) -#define KS8721_PAUSE (1 << 10) -#define KS8721_T4 (1 << 9) -#define KS8721_TX_FDX (1 << 8) -#define KS8721_TX_HDX (1 << 7) -#define KS8721_10_FDX (1 << 6) -#define KS8721_10_HDX (1 << 5) -#define KS8721_AN_IEEE_802_3 0x0001 - -/****************** function prototypes **********************/ -unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac); -unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac); -unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status); -unsigned char ks8721_initphy(AT91PS_EMAC p_mac); diff --git a/include/lcd.h b/include/lcd.h index c167946eb2..187584ca13 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -9,11 +9,12 @@ * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _LCD_H_ #define _LCD_H_ +#include extern char lcd_is_enabled; @@ -28,8 +29,6 @@ void lcd_enable(void); void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); void lcd_initcolregs(void); -int lcd_getfgcolor(void); - /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, void **alloc_addr); @@ -168,7 +167,7 @@ typedef struct vidinfo { u_long vl_upper_margin; /* Time from sync to picture */ u_long vl_lower_margin; /* Time from picture to sync */ - u_long mmio; /* Memory mapped registers */ + void *mmio; /* Memory mapped registers */ } vidinfo_t; #elif defined(CONFIG_EXYNOS_FB) @@ -225,6 +224,8 @@ typedef struct vidinfo { unsigned int logo_on; unsigned int logo_width; unsigned int logo_height; + int logo_x_offset; + int logo_y_offset; unsigned long logo_addr; unsigned int rgb_mode; unsigned int resolution; @@ -252,7 +253,7 @@ typedef struct vidinfo { void *priv; /* Pointer to driver-specific data */ } vidinfo_t; -#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */ +#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */ extern vidinfo_t panel_info; @@ -295,6 +296,20 @@ int lcd_get_screen_rows(void); */ int lcd_get_screen_columns(void); +/** + * Get the background color of the LCD + * + * @return background color value + */ +int lcd_getbgcolor(void); + +/** + * Get the foreground color of the LCD + * + * @return foreground color value + */ +int lcd_getfgcolor(void); + /** * Set the position of the text cursor * @@ -312,6 +327,9 @@ int lcd_get_size(int *line_length); int lcd_dt_simplefb_add_node(void *blob); int lcd_dt_simplefb_enable_existing_node(void *blob); +/* Update the LCD / flush the cache */ +void lcd_sync(void); + /************************************************************************/ /* ** BITMAP DISPLAY SUPPORT */ /************************************************************************/ @@ -333,8 +351,7 @@ int lcd_dt_simplefb_enable_existing_node(void *blob); #define LCD_COLOR4 2 #define LCD_COLOR8 3 #define LCD_COLOR16 4 -#define LCD_COLOR24 5 - +#define LCD_COLOR32 5 /*----------------------------------------------------------------------*/ #if defined(CONFIG_LCD_INFO_BELOW_LOGO) # define LCD_INFO_X 0 @@ -362,15 +379,7 @@ int lcd_dt_simplefb_enable_existing_node(void *blob); /************************************************************************/ /* ** CONSOLE CONSTANTS */ /************************************************************************/ -#if LCD_BPP == LCD_MONOCHROME - -/* - * Simple black/white definitions - */ -# define CONSOLE_COLOR_BLACK 0 -# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ - -#elif LCD_BPP == LCD_COLOR8 +#if LCD_BPP == LCD_COLOR8 /* * 8bpp color definitions @@ -385,6 +394,21 @@ int lcd_dt_simplefb_enable_existing_node(void *blob); # define CONSOLE_COLOR_GREY 14 # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ +#elif LCD_BPP == LCD_COLOR32 +/* + * 32bpp color definitions + */ +# define CONSOLE_COLOR_RED 0x00ff0000 +# define CONSOLE_COLOR_GREEN 0x0000ff00 +# define CONSOLE_COLOR_YELLOW 0x00ffff00 +# define CONSOLE_COLOR_BLUE 0x000000ff +# define CONSOLE_COLOR_MAGENTA 0x00ff00ff +# define CONSOLE_COLOR_CYAN 0x0000ffff +# define CONSOLE_COLOR_GREY 0x00aaaaaa +# define CONSOLE_COLOR_BLACK 0x00000000 +# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest*/ +# define NBYTES(bit_code) (NBITS(bit_code) >> 3) + #elif LCD_BPP == LCD_COLOR16 /* @@ -400,19 +424,6 @@ int lcd_dt_simplefb_enable_existing_node(void *blob); # define CONSOLE_COLOR_GREY 0xcccc # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ -#elif LCD_BPP == LCD_COLOR24 -/* - * 16bpp color definitions - */ -# define CONSOLE_COLOR_BLACK 0x00000000 -# define CONSOLE_COLOR_RED 0x00ff0000 -# define CONSOLE_COLOR_GREEN 0x0000ff00 -# define CONSOLE_COLOR_YELLOW 0x00ffff00 -# define CONSOLE_COLOR_BLUE 0x000000ff -# define CONSOLE_COLOR_MAGENTA 0x00ff00ff -# define CONSOLE_COLOR_CYAN 0x0000ffff -# define CONSOLE_COLOR_GREY 0x00cccccc -# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest */ #else #error Invalid LCD_BPP setting #endif /* color definitions */ diff --git a/include/lcd_console.h b/include/lcd_console.h new file mode 100644 index 0000000000..429214df80 --- /dev/null +++ b/include/lcd_console.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* By default we scroll by a single line */ +#ifndef CONFIG_CONSOLE_SCROLL_LINES +#define CONFIG_CONSOLE_SCROLL_LINES 1 +#endif + +/** + * lcd_init_console() - Initialize lcd console parameters + * + * Setup the address of console base, and the number of rows and columns the + * console has. + * + * @address: Console base address + * @rows: Number of rows in the console + * @cols: Number of columns in the console + */ +void lcd_init_console(void *address, int rows, int cols); + +/** + * lcd_set_col() - Set the number of the current lcd console column + * + * Set the number of the console column where the cursor is. + * + * @col: Column number + */ +void lcd_set_col(short col); + +/** + * lcd_set_row() - Set the number of the current lcd console row + * + * Set the number of the console row where the cursor is. + * + * @row: Row number + */ +void lcd_set_row(short row); + +/** + * lcd_position_cursor() - Position the cursor on the screen + * + * Position the cursor at the given coordinates on the screen. + * + * @col: Column number + * @row: Row number + */ +void lcd_position_cursor(unsigned col, unsigned row); + +/** + * lcd_get_screen_rows() - Get the total number of screen rows + * + * @return: Number of screen rows + */ +int lcd_get_screen_rows(void); + +/** + * lcd_get_screen_columns() - Get the total number of screen columns + * + * @return: Number of screen columns + */ +int lcd_get_screen_columns(void); + +/** + * lcd_putc() - Print to screen a single character at the location of the cursor + * + * @c: The character to print + */ +void lcd_putc(const char c); + +/** + * lcd_puts() - Print to screen a string at the location of the cursor + * + * @s: The string to print + */ +void lcd_puts(const char *s); + +/** + * lcd_printf() - Print to screen a formatted string at location of the cursor + * + * @fmt: The formatted string to print + * @...: The arguments for the formatted string + */ +void lcd_printf(const char *fmt, ...); diff --git a/include/libfdt.h b/include/libfdt.h index 765d84f5e4..f3cbb637be 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -116,7 +116,12 @@ * Should never be returned, if it is, it indicates a bug in * libfdt itself. */ -#define FDT_ERR_MAX 13 +/* Errors in device tree content */ +#define FDT_ERR_BADNCELLS 14 + /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells + * or similar property with a bad format or value */ + +#define FDT_ERR_MAX 14 /**********************************************************************/ /* Low-level functions (you probably don't need these) */ @@ -158,6 +163,31 @@ int fdt_first_subnode(const void *fdt, int offset); */ int fdt_next_subnode(const void *fdt, int offset); +/** + * fdt_for_each_subnode - iterate over all subnodes of a parent + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_subnode(fdt, node, parent) { + * ... + * use node + * ... + * } + * + * Note that this is implemented as a macro and node is used as iterator in + * the loop. It should therefore be a locally allocated variable. The parent + * variable on the other hand is never modified, so it can be constant or + * even a literal. + * + * @fdt: FDT blob (const void *) + * @node: child node (int) + * @parent: parent node (int) + */ +#define fdt_for_each_subnode(fdt, node, parent) \ + for (node = fdt_first_subnode(fdt, parent); \ + node >= 0; \ + node = fdt_next_subnode(fdt, node)) + /**********************************************************************/ /* General functions */ /**********************************************************************/ @@ -731,7 +761,7 @@ int fdt_parent_offset(const void *fdt, int nodeoffset); * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, * propval, proplen); * while (offset != -FDT_ERR_NOTFOUND) { - * ... other code here ... + * // other code here * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, * propval, proplen); * } @@ -816,7 +846,7 @@ int fdt_node_check_compatible(const void *fdt, int nodeoffset, * idiom can be used: * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); * while (offset != -FDT_ERR_NOTFOUND) { - * ... other code here ... + * // other code here * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); * } * @@ -852,6 +882,110 @@ int fdt_node_offset_by_compatible(const void *fdt, int startoffset, */ int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); +/** + * fdt_count_strings - count the number of strings in a string list + * @fdt: pointer to the device tree blob + * @node: offset of the node + * @property: name of the property containing the string list + * @return: the number of strings in the given property + */ +int fdt_count_strings(const void *fdt, int node, const char *property); + +/** + * fdt_find_string - find a string in a string list and return its index + * @fdt: pointer to the device tree blob + * @node: offset of the node + * @property: name of the property containing the string list + * @string: string to look up in the string list + * @return: the index of the string or negative on error + */ +int fdt_find_string(const void *fdt, int node, const char *property, + const char *string); + +/** + * fdt_get_string_index() - obtain the string at a given index in a string list + * @fdt: pointer to the device tree blob + * @node: offset of the node + * @property: name of the property containing the string list + * @index: index of the string to return + * @output: return location for the string + * @return: 0 if the string was found or a negative error code otherwise + */ +int fdt_get_string_index(const void *fdt, int node, const char *property, + int index, const char **output); + +/** + * fdt_get_string() - obtain the string at a given index in a string list + * @fdt: pointer to the device tree blob + * @node: offset of the node + * @property: name of the property containing the string list + * @output: return location for the string + * @return: 0 if the string was found or a negative error code otherwise + * + * This is a shortcut for: + * + * fdt_get_string_index(fdt, node, property, 0, output). + */ +int fdt_get_string(const void *fdt, int node, const char *property, + const char **output); + +/**********************************************************************/ +/* Read-only functions (addressing related) */ +/**********************************************************************/ + +/** + * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells + * + * This is the maximum value for #address-cells, #size-cells and + * similar properties that will be processed by libfdt. IEE1275 + * requires that OF implementations handle values up to 4. + * Implementations may support larger values, but in practice higher + * values aren't used. + */ +#define FDT_MAX_NCELLS 4 + +/** + * fdt_address_cells - retrieve address size for a bus represented in the tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address size for + * + * When the node has a valid #address-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #address-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_address_cells(const void *fdt, int nodeoffset); + +/** + * fdt_size_cells - retrieve address range size for a bus represented in the + * tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address range size for + * + * When the node has a valid #size-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #size-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_size_cells(const void *fdt, int nodeoffset); + + /**********************************************************************/ /* Write-in-place functions */ /**********************************************************************/ @@ -1023,6 +1157,7 @@ int fdt_nop_node(void *fdt, int nodeoffset); /**********************************************************************/ int fdt_create(void *buf, int bufsize); +int fdt_resize(void *fdt, void *buf, int bufsize); int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); int fdt_finish_reservemap(void *fdt); int fdt_begin_node(void *fdt, const char *name); diff --git a/include/linker_lists.h b/include/linker_lists.h index 1eebb95fbb..940c871281 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -8,6 +8,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __LINKER_LISTS_H__ +#define __LINKER_LISTS_H__ + +#include + /* * There is no use in including this from ASM files, but that happens * anyway, e.g. PPC kgdb.S includes command.h which incluse us. @@ -18,23 +23,23 @@ /** * A linker list is constructed by grouping together linker input - * sections, each containning one entry of the list. Each input section + * sections, each containing one entry of the list. Each input section * contains a constant initialized variable which holds the entry's * content. Linker list input sections are constructed from the list * and entry names, plus a prefix which allows grouping all lists * together. Assuming _list and _entry are the list and entry names, * then the corresponding input section name is * - * _u_boot_list + _2_ + @_list + _2_ + @_entry + * .u_boot_list_ + 2_ + @_list + _2_ + @_entry * * and the C variable name is * - * .u_boot_list_ + 2_ + @_list + _2_ + @_entry + * _u_boot_list + _2_ + @_list + _2_ + @_entry * * This ensures uniqueness for both input section and C variable name. * * Note that the names differ only in the first character, "." for the - * setion and "_" for the variable, so that the linker cannot confuse + * section and "_" for the variable, so that the linker cannot confuse * section and symbol names. From now on, both names will be referred * to as * @@ -97,9 +102,6 @@ * %u_boot_list_2_drivers_3 */ -#ifndef __LINKER_LISTS_H__ -#define __LINKER_LISTS_H__ - /** * ll_entry_declare() - Declare linker-generated array entry * @_type: Data type of the entry @@ -140,6 +142,27 @@ __attribute__((unused, \ section(".u_boot_list_2_"#_list"_2_"#_name))) +/** + * ll_entry_declare_list() - Declare a list of link-generated array entries + * @_type: Data type of each entry + * @_name: Name of the entry + * @_list: name of the list. Should contain only characters allowed + * in a C variable name! + * + * This is like ll_entry_declare() but creates multiple entries. It should + * be assigned to an array. + * + * ll_entry_declare_list(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * { .x = 3, .y = 4 }, + * { .x = 8, .y = 2 }, + * { .x = 1, .y = 7 } + * }; + */ +#define ll_entry_declare_list(_type, _name, _list) \ + _type _u_boot_list_2_##_list##_2_##_name[] __aligned(4) \ + __attribute__((unused, \ + section(".u_boot_list_2_"#_list"_2_"#_name))) + /** * We need a 0-byte-size type for iterator symbols, and the compiler * does not allow defining objects of C type 'void'. Using an empty @@ -228,7 +251,7 @@ * and it's name. * * Example: - * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub) = { * .x = 3, * .y = 4, * }; diff --git a/include/linux/compat.h b/include/linux/compat.h index e1338bf489..b40133cb3c 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -1,9 +1,31 @@ #ifndef _LINUX_COMPAT_H_ #define _LINUX_COMPAT_H_ +#include +#include +#include + +struct unused {}; +typedef struct unused unused_t; + +struct p_current{ + int pid; +}; + +extern struct p_current *current; + #define ndelay(x) udelay(1) +#define dev_dbg(dev, fmt, args...) \ + debug(fmt, ##args) +#define dev_vdbg(dev, fmt, args...) \ + debug(fmt, ##args) +#define dev_info(dev, fmt, args...) \ + printf(fmt, ##args) +#define dev_err(dev, fmt, args...) \ + printf(fmt, ##args) #define printk printf +#define printk_once printf #define KERN_EMERG #define KERN_ALERT @@ -14,11 +36,20 @@ #define KERN_INFO #define KERN_DEBUG -#define kmalloc(size, flags) malloc(size) -#define kzalloc(size, flags) calloc(size, 1) -#define vmalloc(size) malloc(size) -#define kfree(ptr) free(ptr) -#define vfree(ptr) free(ptr) +void *kmalloc(size_t size, int flags); +void *kzalloc(size_t size, int flags); +#define vmalloc(size) kmalloc(size, 0) +#define __vmalloc(size, flags, pgsz) kmalloc(size, flags) +#define kfree(ptr) free(ptr) +#define vfree(ptr) free(ptr) + +struct kmem_cache { int sz; }; + +struct kmem_cache *get_mem(int element_sz); +#define kmem_cache_create(a, sz, c, d, e) get_mem(sz) +void *kmem_cache_alloc(struct kmem_cache *obj, int flag); +#define kmem_cache_free(obj, size) free(size) +#define kmem_cache_destroy(obj) free(obj) #define DECLARE_WAITQUEUE(...) do { } while (0) #define add_wait_queue(...) do { } while (0) @@ -26,17 +57,6 @@ #define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -/* - * ..and if you can't take the strict - * types, you can specify one yourself. - * - * Or not use min/max at all, of course. - */ -#define min_t(type,x,y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) -#define max_t(type,x,y) \ - ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; }) - #ifndef BUG #define BUG() do { \ printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \ @@ -49,4 +69,272 @@ , __FILE__, __LINE__); } #define PAGE_SIZE 4096 + +/* drivers/char/random.c */ +#define get_random_bytes(...) + +/* idr.c */ +#define GFP_ATOMIC ((gfp_t) 0) +#define GFP_KERNEL ((gfp_t) 0) +#define GFP_NOFS ((gfp_t) 0) +#define GFP_USER ((gfp_t) 0) +#define __GFP_NOWARN ((gfp_t) 0) + +/* include/linux/leds.h */ +struct led_trigger {}; + +#define DEFINE_LED_TRIGGER(x) static struct led_trigger *x; +enum led_brightness { + LED_OFF = 0, + LED_HALF = 127, + LED_FULL = 255, +}; + +static inline void led_trigger_register_simple(const char *name, + struct led_trigger **trigger) {} +static inline void led_trigger_unregister_simple(struct led_trigger *trigger) {} +static inline void led_trigger_event(struct led_trigger *trigger, + enum led_brightness event) {} + +/* include/linux/log2.h */ +static inline int is_power_of_2(unsigned long n) +{ + return (n != 0 && ((n & (n - 1)) == 0)); +} + +/* uapi/linux/limits.h */ +#define XATTR_LIST_MAX 65536 /* size of extended attribute namelist (64k) */ + +/** + * The type used for indexing onto a disc or disc partition. + * + * Linux always considers sectors to be 512 bytes long independently + * of the devices real block size. + * + * blkcnt_t is the type of the inode's block count. + */ +#ifdef CONFIG_LBDAF +typedef u64 sector_t; +typedef u64 blkcnt_t; +#else +typedef unsigned long sector_t; +typedef unsigned long blkcnt_t; +#endif + +#define ENOTSUPP 524 /* Operation is not supported */ + +/* module */ +#define THIS_MODULE 0 +#define try_module_get(...) 1 +#define module_put(...) do { } while (0) +#define module_init(...) +#define module_exit(...) +#define EXPORT_SYMBOL(...) +#define EXPORT_SYMBOL_GPL(...) +#define module_param(...) +#define module_param_call(...) +#define MODULE_PARM_DESC(...) +#define MODULE_VERSION(...) +#define MODULE_DESCRIPTION(...) +#define MODULE_AUTHOR(...) +#define MODULE_LICENSE(...) +#define MODULE_ALIAS(...) +#define __module_get(...) + +/* character device */ +#define MKDEV(...) 0 +#define MAJOR(dev) 0 +#define MINOR(dev) 0 + +#define alloc_chrdev_region(...) 0 +#define unregister_chrdev_region(...) + +#define class_create(...) __builtin_return_address(0) +#define class_create_file(...) 0 +#define class_remove_file(...) +#define class_destroy(...) +#define misc_register(...) 0 +#define misc_deregister(...) + +#define blocking_notifier_call_chain(...) 0 + +#define __initdata +#define late_initcall(...) + +#define dev_set_name(...) do { } while (0) +#define device_register(...) 0 +#define volume_sysfs_init(...) 0 +#define volume_sysfs_close(...) do { } while (0) + +#define init_waitqueue_head(...) do { } while (0) +#define wait_event_interruptible(...) 0 +#define wake_up_interruptible(...) do { } while (0) +#define print_hex_dump(...) do { } while (0) +#define dump_stack(...) do { } while (0) + +#define task_pid_nr(x) 0 +#define set_freezable(...) do { } while (0) +#define try_to_freeze(...) 0 +#define set_current_state(...) do { } while (0) +#define kthread_should_stop(...) 0 +#define schedule() do { } while (0) + +#define setup_timer(timer, func, data) do {} while (0) +#define del_timer_sync(timer) do {} while (0) +#define schedule_work(work) do {} while (0) +#define INIT_WORK(work, fun) do {} while (0) + +struct work_struct {}; + +unsigned long copy_from_user(void *dest, const void *src, + unsigned long count); + +void *vzalloc(unsigned long size); + +typedef unused_t spinlock_t; +typedef int wait_queue_head_t; + +#define spin_lock_init(lock) do {} while (0) +#define spin_lock(lock) do {} while (0) +#define spin_unlock(lock) do {} while (0) +#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0) +#define spin_unlock_irqrestore(lock, flags) do { flags = 0; } while (0) + +#define DEFINE_MUTEX(...) +#define mutex_init(...) +#define mutex_lock(...) +#define mutex_unlock(...) + +#define init_rwsem(...) do { } while (0) +#define down_read(...) do { } while (0) +#define down_write(...) do { } while (0) +#define down_write_trylock(...) 1 +#define up_read(...) do { } while (0) +#define up_write(...) do { } while (0) + +#define cond_resched() do { } while (0) +#define yield() do { } while (0) + +#define __init +#define __exit +#define __devinit +#define __devinitdata +#define __devinitconst + +#define kthread_create(...) __builtin_return_address(0) +#define kthread_stop(...) do { } while (0) +#define wake_up_process(...) do { } while (0) + +struct rw_semaphore { int i; }; +#define down_write(...) do { } while (0) +#define up_write(...) do { } while (0) +#define down_read(...) do { } while (0) +#define up_read(...) do { } while (0) +struct device { + struct device *parent; + struct class *class; + dev_t devt; /* dev_t, creates the sysfs "dev" */ + void (*release)(struct device *dev); + /* This is used from drivers/usb/musb-new subsystem only */ + void *driver_data; /* data private to the driver */ + void *device_data; /* data private to the device */ +}; +struct mutex { int i; }; +struct kernel_param { int i; }; + +struct cdev { + int owner; + dev_t dev; +}; +#define cdev_init(...) do { } while (0) +#define cdev_add(...) 0 +#define cdev_del(...) do { } while (0) + +#define prandom_u32(...) 0 + +typedef struct { + uid_t val; +} kuid_t; + +typedef struct { + gid_t val; +} kgid_t; + +/* from include/linux/types.h */ + +typedef int atomic_t; +/** + * struct callback_head - callback structure for use with RCU and task_work + * @next: next update requests in a list + * @func: actual update function to call after the grace period. + */ +struct callback_head { + struct callback_head *next; + void (*func)(struct callback_head *head); +}; +#define rcu_head callback_head +enum writeback_sync_modes { + WB_SYNC_NONE, /* Don't wait on anything */ + WB_SYNC_ALL, /* Wait on every mapping */ +}; + +/* from include/linux/writeback.h */ +/* + * A control structure which tells the writeback code what to do. These are + * always on the stack, and hence need no locking. They are always initialised + * in a manner such that unspecified fields are set to zero. + */ +struct writeback_control { + long nr_to_write; /* Write this many pages, and decrement + this for each page written */ + long pages_skipped; /* Pages which were not written */ + + /* + * For a_ops->writepages(): if start or end are non-zero then this is + * a hint that the filesystem need only write out the pages inside that + * byterange. The byte at `end' is included in the writeout request. + */ + loff_t range_start; + loff_t range_end; + + enum writeback_sync_modes sync_mode; + + unsigned for_kupdate:1; /* A kupdate writeback */ + unsigned for_background:1; /* A background writeback */ + unsigned tagged_writepages:1; /* tag-and-write to avoid livelock */ + unsigned for_reclaim:1; /* Invoked from the page allocator */ + unsigned range_cyclic:1; /* range_start is cyclic */ + unsigned for_sync:1; /* sync(2) WB_SYNC_ALL writeback */ +}; + +void *kmemdup(const void *src, size_t len, gfp_t gfp); + +typedef int irqreturn_t; + +struct timer_list {}; +struct notifier_block {}; + +typedef unsigned long dmaaddr_t; + +#define cpu_relax() do {} while (0) + +#define pm_runtime_get_sync(dev) do {} while (0) +#define pm_runtime_put(dev) do {} while (0) +#define pm_runtime_put_sync(dev) do {} while (0) +#define pm_runtime_use_autosuspend(dev) do {} while (0) +#define pm_runtime_set_autosuspend_delay(dev, delay) do {} while (0) +#define pm_runtime_enable(dev) do {} while (0) + +#define IRQ_NONE 0 +#define IRQ_HANDLED 1 + +#define dev_set_drvdata(dev, data) do {} while (0) + +#define enable_irq(...) +#define disable_irq(...) +#define disable_irq_wake(irq) do {} while (0) +#define enable_irq_wake(irq) -EINVAL +#define free_irq(irq, data) do {} while (0) +#define request_irq(nr, f, flags, nm, data) 0 + #endif diff --git a/include/linux/compiler-clang.h b/include/linux/compiler-clang.h new file mode 100644 index 0000000000..d1e49d52b6 --- /dev/null +++ b/include/linux/compiler-clang.h @@ -0,0 +1,12 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include directly, include instead." +#endif + +/* Some compiler specific definitions are overwritten here + * for Clang compiler + */ + +#ifdef uninitialized_var +#undef uninitialized_var +#define uninitialized_var(x) x = *(&(x)) +#endif diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h index 73dcf804bc..e057bd2a84 100644 --- a/include/linux/compiler-gcc.h +++ b/include/linux/compiler-gcc.h @@ -5,6 +5,9 @@ /* * Common definitions for all gcc versions go here. */ +#define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) /* Optimization barrier */ @@ -34,9 +37,15 @@ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \ (typeof(ptr)) (__ptr + (off)); }) +/* Make the optimizer believe the variable can be manipulated arbitrarily. */ +#define OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var)) + +#ifdef __CHECKER__ +#define __must_be_array(arr) 0 +#else /* &a[0] degrades to a pointer: a different type from an array */ -#define __must_be_array(a) \ - BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0]))) +#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) +#endif /* * Force always-inline if the user requests it so via the .config, @@ -44,22 +53,35 @@ */ #if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4) -# define inline inline __attribute__((always_inline)) -# define __inline__ __inline__ __attribute__((always_inline)) -# define __inline __inline __attribute__((always_inline)) +# define inline inline __attribute__((always_inline)) notrace +# define __inline__ __inline__ __attribute__((always_inline)) notrace +# define __inline __inline __attribute__((always_inline)) notrace +#else +/* A lot of inline functions can cause havoc with function tracing */ +# define inline inline notrace +# define __inline__ __inline__ notrace +# define __inline __inline notrace #endif #define __deprecated __attribute__((deprecated)) +#ifndef __packed #define __packed __attribute__((packed)) +#endif +#ifndef __weak #define __weak __attribute__((weak)) +#endif /* * it doesn't make sense on ARM (currently the only user of __naked) to trace * naked functions because then mcount is called without stack and frame pointer * being set up and there is no chance to restore the lr register to the value * before mcount was called. + * + * The asm() bodies of naked functions often depend on standard calling conventions, + * therefore they must be noinline and noclone. GCC 4.[56] currently fail to enforce + * this, so we must do so ourselves. See GCC PR44290. */ -#define __naked __attribute__((naked)) notrace +#define __naked __attribute__((naked)) noinline __noclone notrace #define __noreturn __attribute__((noreturn)) @@ -73,9 +95,14 @@ * would be. * [...] */ +#ifndef __pure #define __pure __attribute__((pure)) +#endif +#ifndef __aligned #define __aligned(x) __attribute__((aligned(x))) -#define __printf(a,b) __attribute__((format(printf,a,b))) +#endif +#define __printf(a, b) __attribute__((format(printf, a, b))) +#define __scanf(a, b) __attribute__((format(scanf, a, b))) #define noinline __attribute__((noinline)) #define __attribute_const__ __attribute__((__const__)) #define __maybe_unused __attribute__((unused)) @@ -85,3 +112,17 @@ #define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h) #define gcc_header(x) _gcc_header(x) #include gcc_header(__GNUC__) + +#if !defined(__noclone) +#define __noclone /* not needed */ +#endif + +/* + * A trick to suppress uninitialized variable warning without generating any + * code + */ +#define uninitialized_var(x) x = x + +#ifndef __always_inline +#define __always_inline inline __attribute__((always_inline)) +#endif diff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h index 2befe6513c..7d89febe4d 100644 --- a/include/linux/compiler-gcc3.h +++ b/include/linux/compiler-gcc3.h @@ -2,20 +2,22 @@ #error "Please don't include directly, include instead." #endif -#if __GNUC_MINOR__ >= 3 +#if GCC_VERSION < 30200 +# error Sorry, your compiler is too old - please upgrade it. +#endif + +#if GCC_VERSION >= 30300 # define __used __attribute__((__used__)) #else # define __used __attribute__((__unused__)) #endif -#if __GNUC_MINOR__ >= 4 +#if GCC_VERSION >= 30400 #define __must_check __attribute__((warn_unused_result)) #endif -/* - * A trick to suppress uninitialized variable warning without generating any - * code - */ -#define uninitialized_var(x) x = x - -#define __always_inline inline __attribute__((always_inline)) +#ifdef CONFIG_GCOV_KERNEL +# if GCC_VERSION < 30400 +# error "GCOV profiling support for gcc versions below 3.4 not included" +# endif /* __GNUC_MINOR__ */ +#endif /* CONFIG_GCOV_KERNEL */ diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h index 94dea3ffbf..2507fd2a1e 100644 --- a/include/linux/compiler-gcc4.h +++ b/include/linux/compiler-gcc4.h @@ -4,7 +4,7 @@ /* GCC 4.1.[01] miscompiles __weak */ #ifdef __KERNEL__ -# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1 +# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101 # error Your version of gcc miscompiles the __weak directive # endif #endif @@ -12,15 +12,12 @@ #define __used __attribute__((__used__)) #define __must_check __attribute__((warn_unused_result)) #define __compiler_offsetof(a,b) __builtin_offsetof(a,b) -#define __always_inline inline __attribute__((always_inline)) -/* - * A trick to suppress uninitialized variable warning without generating any - * code - */ -#define uninitialized_var(x) x = x +#if GCC_VERSION >= 40100 && GCC_VERSION < 40600 +# define __compiletime_object_size(obj) __builtin_object_size(obj, 0) +#endif -#if __GNUC_MINOR__ >= 3 +#if GCC_VERSION >= 40300 /* Mark functions as cold. gcc will assume any path leading to a call to them will be unlikely. This means a lot of manual unlikely()s are unnecessary now for any paths leading to the usual suspects @@ -36,8 +33,15 @@ the kernel context */ #define __cold __attribute__((__cold__)) +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#ifndef __CHECKER__ +# define __compiletime_warning(message) __attribute__((warning(message))) +# define __compiletime_error(message) __attribute__((error(message))) +#endif /* __CHECKER__ */ +#endif /* GCC_VERSION >= 40300 */ -#if __GNUC_MINOR__ >= 5 +#if GCC_VERSION >= 40500 /* * Mark a position in code as unreachable. This can be used to * suppress control flow warnings after asm blocks that transfer @@ -48,14 +52,37 @@ * unreleased. Really, we need to have autoconf for the kernel. */ #define unreachable() __builtin_unreachable() -#endif +/* Mark a function definition as prohibited from being cloned. */ +#define __noclone __attribute__((__noclone__)) + +#endif /* GCC_VERSION >= 40500 */ + +#if GCC_VERSION >= 40600 +/* + * Tell the optimizer that something else uses this function or variable. + */ +#define __visible __attribute__((externally_visible)) #endif -#if __GNUC_MINOR__ > 0 -#define __compiletime_object_size(obj) __builtin_object_size(obj, 0) +/* + * GCC 'asm goto' miscompiles certain code sequences: + * + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 + * + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. + * Fixed in GCC 4.8.2 and later versions. + * + * (asm goto is automatically volatile - the naming reflects this.) + */ +#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) + +#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP +#if GCC_VERSION >= 40400 +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ #endif -#if __GNUC_MINOR__ >= 4 -#define __compiletime_warning(message) __attribute__((warning(message))) -#define __compiletime_error(message) __attribute__((error(message))) +#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600) +#define __HAVE_BUILTIN_BSWAP16__ #endif +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h new file mode 100644 index 0000000000..ba147a1727 --- /dev/null +++ b/include/linux/compiler-intel.h @@ -0,0 +1,40 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include directly, include instead." +#endif + +#ifdef __ECC + +/* Some compiler specific definitions are overwritten here + * for Intel ECC compiler + */ + +#include + +/* Intel ECC compiler doesn't support gcc specific asm stmts. + * It uses intrinsics to do the equivalent things. + */ +#undef RELOC_HIDE +#undef OPTIMIZER_HIDE_VAR + +#define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __ptr = (unsigned long) (ptr); \ + (typeof(ptr)) (__ptr + (off)); }) + +/* This should act as an optimization barrier on var. + * Given that this compiler does not have inline assembly, a compiler barrier + * is the best we can do. + */ +#define OPTIMIZER_HIDE_VAR(var) barrier() + +/* Intel ECC compiler doesn't support __builtin_types_compatible_p() */ +#define __must_be_array(a) 0 + +#endif + +#ifndef __HAVE_BUILTIN_BSWAP16__ +/* icc has this, but it's called _bswap16 */ +#define __HAVE_BUILTIN_BSWAP16__ +#define __builtin_bswap16 _bswap16 +#endif + diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 5be3dab4a6..d5ad7b1118 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -5,16 +5,23 @@ #ifdef __CHECKER__ # define __user __attribute__((noderef, address_space(1))) -# define __kernel /* default address space */ +# define __kernel __attribute__((address_space(0))) # define __safe __attribute__((safe)) # define __force __attribute__((force)) # define __nocast __attribute__((nocast)) # define __iomem __attribute__((noderef, address_space(2))) +# define __must_hold(x) __attribute__((context(x,1,1))) # define __acquires(x) __attribute__((context(x,0,1))) # define __releases(x) __attribute__((context(x,1,0))) # define __acquire(x) __context__(x,1) # define __release(x) __context__(x,-1) # define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) +# define __percpu __attribute__((noderef, address_space(3))) +#ifdef CONFIG_SPARSE_RCU_POINTER +# define __rcu __attribute__((noderef, address_space(4))) +#else +# define __rcu +#endif extern void __chk_user_ptr(const volatile void __user *); extern void __chk_io_ptr(const volatile void __iomem *); #else @@ -27,13 +34,20 @@ extern void __chk_io_ptr(const volatile void __iomem *); # define __chk_user_ptr(x) (void)0 # define __chk_io_ptr(x) (void)0 # define __builtin_warning(x, y...) (1) +# define __must_hold(x) # define __acquires(x) # define __releases(x) # define __acquire(x) (void)0 # define __release(x) (void)0 # define __cond_lock(x,c) (c) +# define __percpu +# define __rcu #endif +/* Indirect macros required for expanded argument pasting, eg. __LINE__. */ +#define ___PASTE(a,b) a##b +#define __PASTE(a,b) ___PASTE(a,b) + #ifdef __KERNEL__ #ifdef __GNUC__ @@ -49,6 +63,13 @@ extern void __chk_io_ptr(const volatile void __iomem *); # include #endif +/* Clang compiler defines __GNUC__. So we will overwrite implementations + * coming from above header files here + */ +#ifdef __clang__ +#include +#endif + /* * Generic compiler-dependent macros required for kernel * build go below this comment. Actual compiler/compiler version @@ -156,6 +177,15 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); (typeof(ptr)) (__ptr + (off)); }) #endif +#ifndef OPTIMIZER_HIDE_VAR +#define OPTIMIZER_HIDE_VAR(var) barrier() +#endif + +/* Not-quite-unique ID. */ +#ifndef __UNIQUE_ID +# define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__) +#endif + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ @@ -228,7 +258,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); /* * Rather then using noinline to prevent stack consumption, use - * noinline_for_stack instead. For documentaiton reasons. + * noinline_for_stack instead. For documentation reasons. */ #define noinline_for_stack noinline @@ -270,11 +300,20 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); # define __section(S) __attribute__ ((__section__(#S))) #endif +#ifndef __visible +#define __visible +#endif + /* Are two types/vars the same type (ignoring qualifiers)? */ #ifndef __same_type # define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) #endif +/* Is this type a native word size -- useful for atomic operations */ +#ifndef __native_word +# define __native_word(t) (sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) +#endif + /* Compile time object size, -1 for unknown */ #ifndef __compiletime_object_size # define __compiletime_object_size(obj) -1 @@ -284,8 +323,49 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); #endif #ifndef __compiletime_error # define __compiletime_error(message) +/* + * Sparse complains of variable sized arrays due to the temporary variable in + * __compiletime_assert. Unfortunately we can't just expand it out to make + * sparse see a constant array size without breaking compiletime_assert on old + * versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether. + */ +# ifndef __CHECKER__ +# define __compiletime_error_fallback(condition) \ + do { ((void)sizeof(char[1 - 2 * condition])); } while (0) +# endif +#endif +#ifndef __compiletime_error_fallback +# define __compiletime_error_fallback(condition) do { } while (0) #endif +#define __compiletime_assert(condition, msg, prefix, suffix) \ + do { \ + bool __cond = !(condition); \ + extern void prefix ## suffix(void) __compiletime_error(msg); \ + if (__cond) \ + prefix ## suffix(); \ + __compiletime_error_fallback(__cond); \ + } while (0) + +#define _compiletime_assert(condition, msg, prefix, suffix) \ + __compiletime_assert(condition, msg, prefix, suffix) + +/** + * compiletime_assert - break build and emit msg if condition is false + * @condition: a compile-time constant condition to check + * @msg: a message to emit if condition is false + * + * In tradition of POSIX assert, this macro will break the build if the + * supplied condition is *false*, emitting the supplied error message if the + * compiler has support to do so. + */ +#define compiletime_assert(condition, msg) \ + _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__) + +#define compiletime_assert_atomic_type(t) \ + compiletime_assert(__native_word(t), \ + "Need native word sized stores/loads for atomicity.") + /* * Prevent the compiler from merging or refetching accesses. The compiler * is also forbidden from reordering successive instances of ACCESS_ONCE(), @@ -300,4 +380,12 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); */ #define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) +/* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */ +#ifdef CONFIG_KPROBES +# define __kprobes __attribute__((__section__(".kprobes.text"))) +# define nokprobe_inline __always_inline +#else +# define __kprobes +# define nokprobe_inline inline +#endif #endif /* __LINUX_COMPILER_H */ diff --git a/include/linux/config.h b/include/linux/config.h deleted file mode 100644 index a0194cb7c7..0000000000 --- a/include/linux/config.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H - -/* #include */ - -#endif diff --git a/include/linux/crc8.h b/include/linux/crc8.h new file mode 100644 index 0000000000..b5fd2ac9d6 --- /dev/null +++ b/include/linux/crc8.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __linux_crc8_h +#define __linux_crc8_h + +/** + * crc8() - Calculate and return CRC-8 of the data + * + * This uses an x^8 + x^2 + x + 1 polynomial. A table-based algorithm would + * be faster, but for only a few bytes it isn't worth the code size + * + * @vptr: Buffer to checksum + * @len: Length of buffer in bytes + * @return CRC8 checksum + */ +unsigned int crc8(const unsigned char *vptr, int len); + +#endif diff --git a/include/linux/err.h b/include/linux/err.h index 96c0c72baa..5b3c8bcf70 100644 --- a/include/linux/err.h +++ b/include/linux/err.h @@ -1,12 +1,8 @@ #ifndef _LINUX_ERR_H #define _LINUX_ERR_H -/* XXX U-BOOT XXX */ -#if 0 #include -#else #include -#endif #include @@ -40,6 +36,19 @@ static inline long IS_ERR(const void *ptr) return IS_ERR_VALUE((unsigned long)ptr); } +/** + * ERR_CAST - Explicitly cast an error-valued pointer to another pointer type + * @ptr: The pointer to cast. + * + * Explicitly cast an error-valued pointer to another pointer type in such a + * way as to make it clear that's what's going on. + */ +static inline void * __must_check ERR_CAST(__force const void *ptr) +{ + /* cast away the const */ + return (void *) ptr; +} + #endif #endif /* _LINUX_ERR_H */ diff --git a/include/linux/fb.h b/include/linux/fb.h index 3858f8f80f..652cf3bab7 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -2,6 +2,7 @@ #define _LINUX_FB_H #include +#include /* Definitions of frame buffers */ @@ -611,6 +612,8 @@ struct fb_videomode { u32 flag; }; +int board_video_skip(void); + #endif /* __KERNEL__ */ #endif /* _LINUX_FB_H */ diff --git a/arch/powerpc/include/asm/immap_qe.h b/include/linux/immap_qe.h similarity index 100% rename from arch/powerpc/include/asm/immap_qe.h rename to include/linux/immap_qe.h diff --git a/include/linux/kbuild.h b/include/linux/kbuild.h index ab7805a3b4..8a9f645e42 100644 --- a/include/linux/kbuild.h +++ b/include/linux/kbuild.h @@ -7,14 +7,14 @@ #define __LINUX_KBUILD_H #define DEFINE(sym, val) \ - asm volatile("\n->" #sym " %0 " #val : : "i" (val)) + asm volatile("\n.ascii \"->" #sym " %0 " #val "\"" : : "i" (val)) -#define BLANK() asm volatile("\n->" : : ) +#define BLANK() asm volatile("\n.ascii \"->\"" : : ) #define OFFSET(sym, str, mem) \ DEFINE(sym, offsetof(struct str, mem)) #define COMMENT(x) \ - asm volatile("\n->#" x) + asm volatile("\n.ascii \"->#" x "\"") #endif diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h new file mode 100644 index 0000000000..be342b94c6 --- /dev/null +++ b/include/linux/kconfig.h @@ -0,0 +1,46 @@ +#ifndef __LINUX_KCONFIG_H +#define __LINUX_KCONFIG_H + +#include + +/* + * Helper macros to use CONFIG_ options in C/CPP expressions. Note that + * these only work with boolean and tristate options. + */ + +/* + * Getting something that works in C and CPP for an arg that may or may + * not be defined is tricky. Here, if we have "#define CONFIG_BOOGER 1" + * we match on the placeholder define, insert the "0," for arg1 and generate + * the triplet (0, 1, 0). Then the last step cherry picks the 2nd arg (a one). + * When CONFIG_BOOGER is not defined, we generate a (... 1, 0) pair, and when + * the last step cherry picks the 2nd arg, we get a zero. + */ +#define __ARG_PLACEHOLDER_1 0, +#define config_enabled(cfg) _config_enabled(cfg) +#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value) +#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0) +#define ___config_enabled(__ignored, val, ...) val + +/* + * IS_ENABLED(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y' or 'm', + * 0 otherwise. + * + */ +#define IS_ENABLED(option) \ + (config_enabled(option) || config_enabled(option##_MODULE)) + +/* + * IS_BUILTIN(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y', 0 + * otherwise. For boolean options, this is equivalent to + * IS_ENABLED(CONFIG_FOO). + */ +#define IS_BUILTIN(option) config_enabled(option) + +/* + * IS_MODULE(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'm', 0 + * otherwise. + */ +#define IS_MODULE(option) config_enabled(option##_MODULE) + +#endif /* __LINUX_KCONFIG_H */ diff --git a/include/linux/kernel.h b/include/linux/kernel.h new file mode 100644 index 0000000000..0b616713cc --- /dev/null +++ b/include/linux/kernel.h @@ -0,0 +1,247 @@ +#ifndef _LINUX_KERNEL_H +#define _LINUX_KERNEL_H + + +#include + +#define USHRT_MAX ((u16)(~0U)) +#define SHRT_MAX ((s16)(USHRT_MAX>>1)) +#define SHRT_MIN ((s16)(-SHRT_MAX - 1)) +#define INT_MAX ((int)(~0U>>1)) +#define INT_MIN (-INT_MAX - 1) +#define UINT_MAX (~0U) +#define LONG_MAX ((long)(~0UL>>1)) +#define LONG_MIN (-LONG_MAX - 1) +#define ULONG_MAX (~0UL) +#define LLONG_MAX ((long long)(~0ULL>>1)) +#define LLONG_MIN (-LLONG_MAX - 1) +#define ULLONG_MAX (~0ULL) +#ifndef SIZE_MAX +#define SIZE_MAX (~(size_t)0) +#endif + +#define U8_MAX ((u8)~0U) +#define S8_MAX ((s8)(U8_MAX>>1)) +#define S8_MIN ((s8)(-S8_MAX - 1)) +#define U16_MAX ((u16)~0U) +#define S16_MAX ((s16)(U16_MAX>>1)) +#define S16_MIN ((s16)(-S16_MAX - 1)) +#define U32_MAX ((u32)~0U) +#define S32_MAX ((s32)(U32_MAX>>1)) +#define S32_MIN ((s32)(-S32_MAX - 1)) +#define U64_MAX ((u64)~0ULL) +#define S64_MAX ((s64)(U64_MAX>>1)) +#define S64_MIN ((s64)(-S64_MAX - 1)) + +#define STACK_MAGIC 0xdeadbeef + +#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) + +#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/* + * This looks more complex than it should be. But we need to + * get the type for the ~ right in round_down (it needs to be + * as wide as the result!), and we want to evaluate the macro + * arguments just once each. + */ +#define __round_mask(x, y) ((__typeof__(x))((y)-1)) +#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) +#define round_down(x, y) ((x) & ~__round_mask(x, y)) + +#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) + +#if BITS_PER_LONG == 32 +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d) +#else +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d) +#endif + +/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ +#define roundup(x, y) ( \ +{ \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ +} \ +) +#define rounddown(x, y) ( \ +{ \ + typeof(x) __x = (x); \ + __x - (__x % (y)); \ +} \ +) + +/* + * Divide positive or negative dividend by positive divisor and round + * to closest integer. Result is undefined for negative divisors and + * for negative dividends if the divisor variable type is unsigned. + */ +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ +} \ +) + +/* + * Multiplies an integer by a fraction, while avoiding unnecessary + * overflow or loss of precision. + */ +#define mult_frac(x, numer, denom)( \ +{ \ + typeof(x) quot = (x) / (denom); \ + typeof(x) rem = (x) % (denom); \ + (quot * (numer)) + ((rem * (numer)) / (denom)); \ +} \ +) + +/** + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) + +/** + * lower_32_bits - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define lower_32_bits(n) ((u32)(n)) + +/* + * abs() handles unsigned and signed longs, ints, shorts and chars. For all + * input types abs() returns a signed long. + * abs() should not be used for 64-bit types (s64, u64, long long) - use abs64() + * for those. + */ +#define abs(x) ({ \ + long ret; \ + if (sizeof(x) == sizeof(long)) { \ + long __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } else { \ + int __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } \ + ret; \ + }) + +#define abs64(x) ({ \ + s64 __x = (x); \ + (__x < 0) ? -__x : __x; \ + }) + +/* + * min()/max()/clamp() macros that also do + * strict type-checking.. See the + * "unnecessary" pointer comparison. + */ +#define min(x, y) ({ \ + typeof(x) _min1 = (x); \ + typeof(y) _min2 = (y); \ + (void) (&_min1 == &_min2); \ + _min1 < _min2 ? _min1 : _min2; }) + +#define max(x, y) ({ \ + typeof(x) _max1 = (x); \ + typeof(y) _max2 = (y); \ + (void) (&_max1 == &_max2); \ + _max1 > _max2 ? _max1 : _max2; }) + +#define min3(x, y, z) min((typeof(x))min(x, y), z) +#define max3(x, y, z) max((typeof(x))max(x, y), z) + +/** + * min_not_zero - return the minimum that is _not_ zero, unless both are zero + * @x: value1 + * @y: value2 + */ +#define min_not_zero(x, y) ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); }) + +/** + * clamp - return a value clamped to a given range with strict typechecking + * @val: current value + * @lo: lowest allowable value + * @hi: highest allowable value + * + * This macro does strict typechecking of lo/hi to make sure they are of the + * same type as val. See the unnecessary pointer comparisons. + */ +#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) + +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max/clamp at all, of course. + */ +#define min_t(type, x, y) ({ \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1: __min2; }) + +#define max_t(type, x, y) ({ \ + type __max1 = (x); \ + type __max2 = (y); \ + __max1 > __max2 ? __max1: __max2; }) + +/** + * clamp_t - return a value clamped to a given range using a given type + * @type: the type of variable to use + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of type + * 'type' to make all the comparisons. + */ +#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi) + +/** + * clamp_val - return a value clamped to a given range using val's type + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of whatever + * type the input argument 'val' is. This is useful when val is an unsigned + * type and min and max are literals that will otherwise be assigned a signed + * integer type. + */ +#define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi) + + +/* + * swap - swap value of @a and @b + */ +#define swap(a, b) \ + do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#endif diff --git a/include/linux/linkage.h b/include/linux/linkage.h index 9ddf830284..5797498adc 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -10,7 +10,6 @@ #define _LINUX_LINKAGE_H #include -#include #ifdef __cplusplus #define CPP_ASMLINKAGE extern "C" @@ -18,7 +17,9 @@ #define CPP_ASMLINKAGE #endif +#ifndef asmlinkage #define asmlinkage CPP_ASMLINKAGE +#endif #define SYMBOL_NAME_STR(X) #X #define SYMBOL_NAME(X) X @@ -49,6 +50,10 @@ .globl SYMBOL_NAME(name); \ LENTRY(name) +#define WEAK(name) \ + .weak SYMBOL_NAME(name); \ + LENTRY(name) + #ifndef END #define END(name) \ .size name, .-name diff --git a/include/linux/list_sort.h b/include/linux/list_sort.h new file mode 100644 index 0000000000..1a2df2efb7 --- /dev/null +++ b/include/linux/list_sort.h @@ -0,0 +1,11 @@ +#ifndef _LINUX_LIST_SORT_H +#define _LINUX_LIST_SORT_H + +#include + +struct list_head; + +void list_sort(void *priv, struct list_head *head, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b)); +#endif diff --git a/include/linux/mbus.h b/include/linux/mbus.h new file mode 100644 index 0000000000..717cbeab37 --- /dev/null +++ b/include/linux/mbus.h @@ -0,0 +1,73 @@ +/* + * Marvell MBUS common definitions. + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __LINUX_MBUS_H +#define __LINUX_MBUS_H + +struct resource; + +struct mbus_dram_target_info { + /* + * The 4-bit MBUS target ID of the DRAM controller. + */ + u8 mbus_dram_target_id; + + /* + * The base address, size, and MBUS attribute ID for each + * of the possible DRAM chip selects. Peripherals are + * required to support at least 4 decode windows. + */ + int num_cs; + struct mbus_dram_window { + u8 cs_index; + u8 mbus_attr; + u32 base; + u32 size; + } cs[4]; +}; + +struct mvebu_mbus_state { + void __iomem *mbuswins_base; + void __iomem *sdramwins_base; + struct dentry *debugfs_root; + struct dentry *debugfs_sdram; + struct dentry *debugfs_devs; + const struct mvebu_mbus_soc_data *soc; + int hw_io_coherency; +}; + +/* Flags for PCI/PCIe address decoding regions */ +#define MVEBU_MBUS_PCI_IO 0x1 +#define MVEBU_MBUS_PCI_MEM 0x2 +#define MVEBU_MBUS_PCI_WA 0x3 + +/* + * Magic value that explicits that we don't need a remapping-capable + * address decoding window. + */ +#define MVEBU_MBUS_NO_REMAP (0xffffffff) + +/* Maximum size of a mbus window name */ +#define MVEBU_MBUS_MAX_WINNAME_SZ 32 + +const struct mbus_dram_target_info *mvebu_mbus_dram_info(void); +void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); +void mvebu_mbus_get_pcie_io_aperture(struct resource *res); +int mvebu_mbus_add_window_remap_by_id(unsigned int target, + unsigned int attribute, + phys_addr_t base, size_t size, + phys_addr_t remap); +int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, + phys_addr_t base, size_t size); +int mvebu_mbus_del_window(phys_addr_t base, size_t size); +int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, + u32 base, u32 size, u8 target, u8 attr); + +#endif /* __LINUX_MBUS_H */ diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h index 94130aa774..be81d3824a 100644 --- a/include/linux/mtd/bbm.h +++ b/include/linux/mtd/bbm.h @@ -11,6 +11,7 @@ * Thomas Gleixner * * SPDX-License-Identifier: GPL-2.0+ + * */ #ifndef __LINUX_MTD_BBM_H #define __LINUX_MTD_BBM_H @@ -80,10 +81,6 @@ struct nand_bbt_descr { * with NAND_BBT_CREATE. */ #define NAND_BBT_CREATE_EMPTY 0x00000400 -/* Search good / bad pattern through all pages of a block */ -#define NAND_BBT_SCANALLPAGES 0x00000800 -/* Scan block empty during good / bad block scan */ -#define NAND_BBT_SCANEMPTY 0x00001000 /* Write bbt if neccecary */ #define NAND_BBT_WRITE 0x00002000 /* Read and write back block contents when writing bbt */ diff --git a/include/linux/mtd/blktrans.h b/include/linux/mtd/blktrans.h deleted file mode 100644 index 32acb6ce9d..0000000000 --- a/include/linux/mtd/blktrans.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) 2003 David Woodhouse - * - * Interface to Linux block layer for MTD 'translation layers'. - * - */ - -#ifndef __MTD_TRANS_H__ -#define __MTD_TRANS_H__ - -/* XXX U-BOOT XXX */ -#if 0 -#include -#else -#include -#endif - -struct hd_geometry; -struct mtd_info; -struct mtd_blktrans_ops; -struct file; -struct inode; - -struct mtd_blktrans_dev { - struct mtd_blktrans_ops *tr; - struct list_head list; - struct mtd_info *mtd; -/* XXX U-BOOT XXX */ -#if 0 - struct mutex lock; -#endif - int devnum; - unsigned long size; - int readonly; - void *blkcore_priv; /* gendisk in 2.5, devfs_handle in 2.4 */ -}; - -struct blkcore_priv; /* Differs for 2.4 and 2.5 kernels; private */ - -struct mtd_blktrans_ops { - char *name; - int major; - int part_bits; - int blksize; - int blkshift; - - /* Access functions */ - int (*readsect)(struct mtd_blktrans_dev *dev, - unsigned long block, char *buffer); - int (*writesect)(struct mtd_blktrans_dev *dev, - unsigned long block, char *buffer); - - /* Block layer ioctls */ - int (*getgeo)(struct mtd_blktrans_dev *dev, struct hd_geometry *geo); - int (*flush)(struct mtd_blktrans_dev *dev); - - /* Called with mtd_table_mutex held; no race with add/remove */ - int (*open)(struct mtd_blktrans_dev *dev); - int (*release)(struct mtd_blktrans_dev *dev); - - /* Called on {de,}registration and on subsequent addition/removal - of devices, with mtd_table_mutex held. */ - void (*add_mtd)(struct mtd_blktrans_ops *tr, struct mtd_info *mtd); - void (*remove_dev)(struct mtd_blktrans_dev *dev); - - struct list_head devs; - struct list_head list; - struct module *owner; - - struct mtd_blkcore_priv *blkcore_priv; -}; - -extern int register_mtd_blktrans(struct mtd_blktrans_ops *tr); -extern int deregister_mtd_blktrans(struct mtd_blktrans_ops *tr); -extern int add_mtd_blktrans_dev(struct mtd_blktrans_dev *dev); -extern int del_mtd_blktrans_dev(struct mtd_blktrans_dev *dev); - - -#endif /* __MTD_TRANS_H__ */ diff --git a/include/linux/mtd/concat.h b/include/linux/mtd/concat.h index c92b4ddc9b..195a4a5426 100644 --- a/include/linux/mtd/concat.h +++ b/include/linux/mtd/concat.h @@ -12,7 +12,11 @@ struct mtd_info *mtd_concat_create( struct mtd_info *subdev[], /* subdevices to concatenate */ int num_devs, /* number of subdevices */ +#ifndef __UBOOT__ const char *name); /* name for the new device */ +#else + char *name); /* name for the new device */ +#endif void mtd_concat_destroy(struct mtd_info *mtd); diff --git a/include/linux/mtd/flashchip.h b/include/linux/mtd/flashchip.h new file mode 100644 index 0000000000..e5c7d1cf0d --- /dev/null +++ b/include/linux/mtd/flashchip.h @@ -0,0 +1,104 @@ +/* + * Copyright © 2000 Red Hat UK Limited + * Copyright © 2000-2010 David Woodhouse + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __MTD_FLASHCHIP_H__ +#define __MTD_FLASHCHIP_H__ + +#ifndef __UBOOT__ +/* For spinlocks. sched.h includes spinlock.h from whichever directory it + * happens to be in - so we don't have to care whether we're on 2.2, which + * has asm/spinlock.h, or 2.4, which has linux/spinlock.h + */ +#include +#include +#endif + +typedef enum { + FL_READY, + FL_STATUS, + FL_CFI_QUERY, + FL_JEDEC_QUERY, + FL_ERASING, + FL_ERASE_SUSPENDING, + FL_ERASE_SUSPENDED, + FL_WRITING, + FL_WRITING_TO_BUFFER, + FL_OTP_WRITE, + FL_WRITE_SUSPENDING, + FL_WRITE_SUSPENDED, + FL_PM_SUSPENDED, + FL_SYNCING, + FL_UNLOADING, + FL_LOCKING, + FL_UNLOCKING, + FL_POINT, + FL_XIP_WHILE_ERASING, + FL_XIP_WHILE_WRITING, + FL_SHUTDOWN, + /* These 2 come from nand_state_t, which has been unified here */ + FL_READING, + FL_CACHEDPRG, + /* These 4 come from onenand_state_t, which has been unified here */ + FL_RESETING, + FL_OTPING, + FL_PREPARING_ERASE, + FL_VERIFYING_ERASE, + + FL_UNKNOWN +} flstate_t; + + + +/* NOTE: confusingly, this can be used to refer to more than one chip at a time, + if they're interleaved. This can even refer to individual partitions on + the same physical chip when present. */ + +struct flchip { + unsigned long start; /* Offset within the map */ + // unsigned long len; + /* We omit len for now, because when we group them together + we insist that they're all of the same size, and the chip size + is held in the next level up. If we get more versatile later, + it'll make it a damn sight harder to find which chip we want from + a given offset, and we'll want to add the per-chip length field + back in. + */ + int ref_point_counter; + flstate_t state; + flstate_t oldstate; + + unsigned int write_suspended:1; + unsigned int erase_suspended:1; + unsigned long in_progress_block_addr; + + struct mutex mutex; +#ifndef __UBOOT__ + wait_queue_head_t wq; /* Wait on here when we're waiting for the chip + to be ready */ +#endif + int word_write_time; + int buffer_write_time; + int erase_time; + + int word_write_time_max; + int buffer_write_time_max; + int erase_time_max; + + void *priv; +}; + +/* This is used to handle contention on write/erase operations + between partitions of the same physical chip. */ +struct flchip_shared { + struct mutex lock; + struct flchip *writing; + struct flchip *erasing; +}; + + +#endif /* __MTD_FLASHCHIP_H__ */ diff --git a/include/linux/mtd/inftl-user.h b/include/linux/mtd/inftl-user.h deleted file mode 100644 index 45220ed76f..0000000000 --- a/include/linux/mtd/inftl-user.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * $Id: inftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $ - * - * Parts of INFTL headers shared with userspace - * - */ - -#ifndef __MTD_INFTL_USER_H__ -#define __MTD_INFTL_USER_H__ - -#define OSAK_VERSION 0x5120 -#define PERCENTUSED 98 - -#define SECTORSIZE 512 - -/* Block Control Information */ - -struct inftl_bci { - uint8_t ECCsig[6]; - uint8_t Status; - uint8_t Status1; -} __attribute__((packed)); - -struct inftl_unithead1 { - uint16_t virtualUnitNo; - uint16_t prevUnitNo; - uint8_t ANAC; - uint8_t NACs; - uint8_t parityPerField; - uint8_t discarded; -} __attribute__((packed)); - -struct inftl_unithead2 { - uint8_t parityPerField; - uint8_t ANAC; - uint16_t prevUnitNo; - uint16_t virtualUnitNo; - uint8_t NACs; - uint8_t discarded; -} __attribute__((packed)); - -struct inftl_unittail { - uint8_t Reserved[4]; - uint16_t EraseMark; - uint16_t EraseMark1; -} __attribute__((packed)); - -union inftl_uci { - struct inftl_unithead1 a; - struct inftl_unithead2 b; - struct inftl_unittail c; -}; - -struct inftl_oob { - struct inftl_bci b; - union inftl_uci u; -}; - - -/* INFTL Media Header */ - -struct INFTLPartition { - __u32 virtualUnits; - __u32 firstUnit; - __u32 lastUnit; - __u32 flags; - __u32 spareUnits; - __u32 Reserved0; - __u32 Reserved1; -} __attribute__((packed)); - -struct INFTLMediaHeader { - char bootRecordID[8]; - __u32 NoOfBootImageBlocks; - __u32 NoOfBinaryPartitions; - __u32 NoOfBDTLPartitions; - __u32 BlockMultiplierBits; - __u32 FormatFlags; - __u32 OsakVersion; - __u32 PercentUsed; - struct INFTLPartition Partitions[4]; -} __attribute__((packed)); - -/* Partition flag types */ -#define INFTL_BINARY 0x20000000 -#define INFTL_BDTL 0x40000000 -#define INFTL_LAST 0x80000000 - -#endif /* __MTD_INFTL_USER_H__ */ diff --git a/include/linux/mtd/jffs2-user.h b/include/linux/mtd/jffs2-user.h deleted file mode 100644 index d508ef0ae0..0000000000 --- a/include/linux/mtd/jffs2-user.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * $Id: jffs2-user.h,v 1.1 2004/05/05 11:57:54 dwmw2 Exp $ - * - * JFFS2 definitions for use in user space only - */ - -#ifndef __JFFS2_USER_H__ -#define __JFFS2_USER_H__ - -/* This file is blessed for inclusion by userspace */ -#include -#include -#include - -#undef cpu_to_je16 -#undef cpu_to_je32 -#undef cpu_to_jemode -#undef je16_to_cpu -#undef je32_to_cpu -#undef jemode_to_cpu - -extern int target_endian; - -#define t16(x) ({ uint16_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_16(__b); }) -#define t32(x) ({ uint32_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_32(__b); }) - -#define cpu_to_je16(x) ((jint16_t){t16(x)}) -#define cpu_to_je32(x) ((jint32_t){t32(x)}) -#define cpu_to_jemode(x) ((jmode_t){t32(x)}) - -#define je16_to_cpu(x) (t16((x).v16)) -#define je32_to_cpu(x) (t32((x).v32)) -#define jemode_to_cpu(x) (t32((x).m)) - -#endif /* __JFFS2_USER_H__ */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 6f44abdc16..8666413275 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -1,48 +1,44 @@ /* - * Copyright (C) 1999-2003 David Woodhouse et al. + * Copyright © 1999-2010 David Woodhouse et al. * * Released under GPL + * */ #ifndef __MTD_MTD_H__ #define __MTD_MTD_H__ +#ifndef __UBOOT__ #include -#include +#include +#include +#include + +#include + +#include +#else +#include #include #include +#include -#define MTD_CHAR_MAJOR 90 -#define MTD_BLOCK_MAJOR 31 #define MAX_MTD_DEVICES 32 +#endif #define MTD_ERASE_PENDING 0x01 #define MTD_ERASING 0x02 #define MTD_ERASE_SUSPEND 0x04 -#define MTD_ERASE_DONE 0x08 -#define MTD_ERASE_FAILED 0x10 +#define MTD_ERASE_DONE 0x08 +#define MTD_ERASE_FAILED 0x10 -#define MTD_FAIL_ADDR_UNKNOWN -1LL +#define MTD_FAIL_ADDR_UNKNOWN -1LL /* - * Enumeration for NAND/OneNAND flash chip state + * If the erase fails, fail_addr might indicate exactly which block failed. If + * fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level + * or was not specific to any particular block. */ -enum { - FL_READY, - FL_READING, - FL_WRITING, - FL_ERASING, - FL_SYNCING, - FL_CACHEDPRG, - FL_RESETING, - FL_UNLOCKING, - FL_LOCKING, - FL_PM_SUSPENDED, -}; - -/* If the erase fails, fail_addr might indicate exactly which block failed. If - fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level or was not - specific to any particular block. */ struct erase_info { struct mtd_info *mtd; uint64_t addr; @@ -50,8 +46,8 @@ struct erase_info { uint64_t fail_addr; u_long time; u_long retries; - u_int dev; - u_int cell; + unsigned dev; + unsigned cell; void (*callback) (struct erase_info *self); u_long priv; u_char state; @@ -60,9 +56,9 @@ struct erase_info { }; struct mtd_erase_region_info { - uint64_t offset; /* At which this region starts, from the beginning of the MTD */ - u_int32_t erasesize; /* For this region */ - u_int32_t numblocks; /* Number of blocks of erasesize in this region */ + uint64_t offset; /* At which this region starts, from the beginning of the MTD */ + uint32_t erasesize; /* For this region */ + uint32_t numblocks; /* Number of blocks of erasesize in this region */ unsigned long *lockmap; /* If keeping bitmap of locks */ }; @@ -81,7 +77,7 @@ struct mtd_erase_region_info { * @datbuf: data buffer - if NULL only oob data are read/written * @oobbuf: oob data buffer * - * Note, it is allowed to read more then one OOB area at one go, but not write. + * Note, it is allowed to read more than one OOB area at one go, but not write. * The interface assumes that the OOB write requests program only one page's * OOB area. */ @@ -96,16 +92,43 @@ struct mtd_oob_ops { uint8_t *oobbuf; }; +#ifdef CONFIG_SYS_NAND_MAX_OOBFREE +#define MTD_MAX_OOBFREE_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_OOBFREE +#else +#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32 +#endif + +#ifdef CONFIG_SYS_NAND_MAX_ECCPOS +#define MTD_MAX_ECCPOS_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_ECCPOS +#else +#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640 +#endif + +/* + * Internal ECC layout control structure. For historical reasons, there is a + * similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained + * for export to user-space via the ECCGETLAYOUT ioctl. + * nand_ecclayout should be expandable in the future simply by the above macros. + */ +struct nand_ecclayout { + __u32 eccbytes; + __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE]; + __u32 oobavail; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE]; +}; + +struct module; /* only needed for owner field in mtd_info */ + struct mtd_info { u_char type; - u_int32_t flags; - uint64_t size; /* Total size of the MTD */ + uint32_t flags; + uint64_t size; // Total size of the MTD /* "Major" erase size for the device. Naïve users may take this * to be the only erase size available, or may use the more detailed * information below if they desire */ - u_int32_t erasesize; + uint32_t erasesize; /* Minimal writable flash unit size. In case of NOR flash it is 1 (even * though individual bits can be cleared), in case of NAND flash it is * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR @@ -113,10 +136,31 @@ struct mtd_info { * Any driver registering a struct mtd_info must ensure a writesize of * 1 or larger. */ - u_int32_t writesize; + uint32_t writesize; + + /* + * Size of the write buffer used by the MTD. MTD devices having a write + * buffer can write multiple writesize chunks at a time. E.g. while + * writing 4 * writesize bytes to a device with 2 * writesize bytes + * buffer the MTD driver can (but doesn't have to) do 2 writesize + * operations, but not 4. Currently, all NANDs have writebufsize + * equivalent to writesize (NAND page size). Some NOR flashes do have + * writebufsize greater than writesize. + */ + uint32_t writebufsize; + + uint32_t oobsize; // Amount of OOB data per block (e.g. 16) + uint32_t oobavail; // Available OOB bytes per block - u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ - u_int32_t oobavail; /* Available OOB bytes per block */ + /* + * If erasesize is a power of 2 then the shift is stored in + * erasesize_shift otherwise erasesize_shift is zero. Ditto writesize. + */ + unsigned int erasesize_shift; + unsigned int writesize_shift; + /* Masks based on erasesize_shift and writesize_shift */ + unsigned int erasesize_mask; + unsigned int writesize_mask; /* * read ops return -EUCLEAN if max number of bitflips corrected on any @@ -127,13 +171,20 @@ struct mtd_info { */ unsigned int bitflip_threshold; - /* Kernel-only stuff starts here. */ + // Kernel-only stuff starts here. +#ifndef __UBOOT__ const char *name; +#else + char *name; +#endif int index; /* ECC layout structure pointer - read only! */ struct nand_ecclayout *ecclayout; + /* the ecc step size. */ + unsigned int ecc_step_size; + /* max number of correctible bit errors per ecc step */ unsigned int ecc_strength; @@ -148,44 +199,51 @@ struct mtd_info { * wrappers instead. */ int (*_erase) (struct mtd_info *mtd, struct erase_info *instr); +#ifndef __UBOOT__ int (*_point) (struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, void **virt, phys_addr_t *phys); - void (*_unpoint) (struct mtd_info *mtd, loff_t from, size_t len); + size_t *retlen, void **virt, resource_size_t *phys); + int (*_unpoint) (struct mtd_info *mtd, loff_t from, size_t len); +#endif + unsigned long (*_get_unmapped_area) (struct mtd_info *mtd, + unsigned long len, + unsigned long offset, + unsigned long flags); int (*_read) (struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf); + size_t *retlen, u_char *buf); int (*_write) (struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf); - - /* In blackbox flight recorder like scenarios we want to make successful - writes in interrupt context. panic_write() is only intended to be - called when its known the kernel is about to panic and we need the - write to succeed. Since the kernel is not going to be running for much - longer, this function can break locks and delay to ensure the write - succeeds (but not sleep). */ - - int (*_panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); - + size_t *retlen, const u_char *buf); + int (*_panic_write) (struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf); int (*_read_oob) (struct mtd_info *mtd, loff_t from, - struct mtd_oob_ops *ops); + struct mtd_oob_ops *ops); int (*_write_oob) (struct mtd_info *mtd, loff_t to, - struct mtd_oob_ops *ops); - int (*_get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf, - size_t len); + struct mtd_oob_ops *ops); + int (*_get_fact_prot_info) (struct mtd_info *mtd, size_t len, + size_t *retlen, struct otp_info *buf); int (*_read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, - size_t len, size_t *retlen, u_char *buf); - int (*_get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf, - size_t len); + size_t len, size_t *retlen, u_char *buf); + int (*_get_user_prot_info) (struct mtd_info *mtd, size_t len, + size_t *retlen, struct otp_info *buf); int (*_read_user_prot_reg) (struct mtd_info *mtd, loff_t from, - size_t len, size_t *retlen, u_char *buf); - int (*_write_user_prot_reg) (struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, u_char *buf); + size_t len, size_t *retlen, u_char *buf); + int (*_write_user_prot_reg) (struct mtd_info *mtd, loff_t to, + size_t len, size_t *retlen, u_char *buf); int (*_lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, - size_t len); + size_t len); +#ifndef __UBOOT__ + int (*_writev) (struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t *retlen); +#endif void (*_sync) (struct mtd_info *mtd); int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); + int (*_is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len); int (*_block_isbad) (struct mtd_info *mtd, loff_t ofs); int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs); +#ifndef __UBOOT__ + int (*_suspend) (struct mtd_info *mtd); + void (*_resume) (struct mtd_info *mtd); +#endif /* * If the driver is something smart, like UBI, it may need to maintain * its own reference counting. The below functions are only for driver. @@ -193,16 +251,12 @@ struct mtd_info { int (*_get_device) (struct mtd_info *mtd); void (*_put_device) (struct mtd_info *mtd); -/* XXX U-BOOT XXX */ -#if 0 - /* kvec-based read/write methods. - NB: The 'count' parameter is the number of _vectors_, each of - which contains an (ofs, len) tuple. - */ - int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen); -#endif -/* XXX U-BOOT XXX */ -#if 0 +#ifndef __UBOOT__ + /* Backing device capabilities for this device + * - provides mmap capabilities + */ + struct backing_dev_info *backing_dev_info; + struct notifier_block reboot_notifier; /* default mode before reboot */ #endif @@ -214,10 +268,20 @@ struct mtd_info { void *priv; struct module *owner; +#ifndef __UBOOT__ + struct device dev; +#endif int usecount; }; int mtd_erase(struct mtd_info *mtd, struct erase_info *instr); +#ifndef __UBOOT__ +int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, + void **virt, resource_size_t *phys); +int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len); +#endif +unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len, + unsigned long offset, unsigned long flags); int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, @@ -238,20 +302,19 @@ static inline int mtd_write_oob(struct mtd_info *mtd, loff_t to, return mtd->_write_oob(mtd, to, ops); } -int mtd_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf, - size_t len); +int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, + struct otp_info *buf); int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); -int mtd_get_user_prot_info(struct mtd_info *mtd, struct otp_info *buf, - size_t len); +int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen, + struct otp_info *buf); int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, u_char *buf); int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len); -/* XXX U-BOOT XXX */ -#if 0 +#ifndef __UBOOT__ int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen); #endif @@ -268,22 +331,59 @@ int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len); int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs); int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs); +#ifndef __UBOOT__ +static inline int mtd_suspend(struct mtd_info *mtd) +{ + return mtd->_suspend ? mtd->_suspend(mtd) : 0; +} + +static inline void mtd_resume(struct mtd_info *mtd) +{ + if (mtd->_resume) + mtd->_resume(mtd); +} +#endif + static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd) { + if (mtd->erasesize_shift) + return sz >> mtd->erasesize_shift; do_div(sz, mtd->erasesize); return sz; } static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd) { + if (mtd->erasesize_shift) + return sz & mtd->erasesize_mask; return do_div(sz, mtd->erasesize); } +static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd) +{ + if (mtd->writesize_shift) + return sz >> mtd->writesize_shift; + do_div(sz, mtd->writesize); + return sz; +} + +static inline uint32_t mtd_mod_by_ws(uint64_t sz, struct mtd_info *mtd) +{ + if (mtd->writesize_shift) + return sz & mtd->writesize_mask; + return do_div(sz, mtd->writesize); +} + static inline int mtd_has_oob(const struct mtd_info *mtd) { return mtd->_read_oob && mtd->_write_oob; } +static inline int mtd_type_is_nand(const struct mtd_info *mtd) +{ + return mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH; +} + static inline int mtd_can_have_bb(const struct mtd_info *mtd) { return !!mtd->_block_isbad; @@ -291,27 +391,36 @@ static inline int mtd_can_have_bb(const struct mtd_info *mtd) /* Kernel-side ioctl definitions */ -extern int add_mtd_device(struct mtd_info *mtd); -extern int del_mtd_device (struct mtd_info *mtd); - +struct mtd_partition; +struct mtd_part_parser_data; + +extern int mtd_device_parse_register(struct mtd_info *mtd, + const char * const *part_probe_types, + struct mtd_part_parser_data *parser_data, + const struct mtd_partition *defparts, + int defnr_parts); +#define mtd_device_register(master, parts, nr_parts) \ + mtd_device_parse_register(master, NULL, NULL, parts, nr_parts) +extern int mtd_device_unregister(struct mtd_info *master); extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); +extern int __get_mtd_device(struct mtd_info *mtd); +extern void __put_mtd_device(struct mtd_info *mtd); extern struct mtd_info *get_mtd_device_nm(const char *name); - extern void put_mtd_device(struct mtd_info *mtd); -extern void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, - const uint64_t length, uint64_t *len_incl_bad, - int *truncated); -/* XXX U-BOOT XXX */ -#if 0 + + +#ifndef __UBOOT__ struct mtd_notifier { void (*add)(struct mtd_info *mtd); void (*remove)(struct mtd_info *mtd); struct list_head list; }; + extern void register_mtd_user (struct mtd_notifier *new); extern int unregister_mtd_user (struct mtd_notifier *old); #endif +void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size); #ifdef CONFIG_MTD_PARTITIONS void mtd_erase_callback(struct erase_info *instr); @@ -323,6 +432,7 @@ static inline void mtd_erase_callback(struct erase_info *instr) } #endif +#ifdef __UBOOT__ /* * Debugging macro and defines */ @@ -349,7 +459,11 @@ static inline void mtd_erase_callback(struct erase_info *instr) #define pr_info(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) #define pr_warn(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) #define pr_err(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) - +#define pr_crit(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) +#define pr_cont(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) +#define pr_notice(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) +#endif + static inline int mtd_is_bitflip(int err) { return err == -EUCLEAN; } @@ -362,4 +476,11 @@ static inline int mtd_is_bitflip_or_eccerr(int err) { return mtd_is_bitflip(err) || mtd_is_eccerr(err); } +#ifdef __UBOOT__ +/* drivers/mtd/mtdcore.h */ +int add_mtd_device(struct mtd_info *mtd); +int del_mtd_device(struct mtd_info *mtd); +int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); +int del_mtd_partitions(struct mtd_info *); +#endif #endif /* __MTD_MTD_H__ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 2055584374..8438490fe4 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -5,9 +5,7 @@ * Steven J. Hill * Thomas Gleixner * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0+ * * Info: * Contains standard defines and IDs for NAND flash devices @@ -18,21 +16,31 @@ #ifndef __LINUX_MTD_NAND_H #define __LINUX_MTD_NAND_H +#ifndef __UBOOT__ +#include +#include +#include +#include +#include +#else #include "config.h" #include "linux/compat.h" #include "linux/mtd/mtd.h" +#include "linux/mtd/flashchip.h" #include "linux/mtd/bbm.h" - +#endif struct mtd_info; struct nand_flash_dev; /* Scan and identify a NAND device */ -extern int nand_scan (struct mtd_info *mtd, int max_chips); -/* Separate phases of nand_scan(), allowing board driver to intervene - * and override command or ECC setup according to flash type */ +extern int nand_scan(struct mtd_info *mtd, int max_chips); +/* + * Separate phases of nand_scan(), allowing board driver to intervene + * and override command or ECC setup according to flash type. + */ extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, - const struct nand_flash_dev *table); + struct nand_flash_dev *table); extern int nand_scan_tail(struct mtd_info *mtd); /* Free resources held by the NAND device */ @@ -41,13 +49,24 @@ extern void nand_release(struct mtd_info *mtd); /* Internal helper for board drivers which need to override command function */ extern void nand_wait_ready(struct mtd_info *mtd); +#ifndef __UBOOT__ +/* locks all blocks present in the device */ +extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); + +/* unlocks specified locked blocks */ +extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); + +/* The maximum number of NAND chips in an array */ +#define NAND_MAX_CHIPS 8 +#else /* * This constant declares the max. oobsize / page, which * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ -#define NAND_MAX_OOBSIZE 640 -#define NAND_MAX_PAGESIZE 8192 +#define NAND_MAX_OOBSIZE 744 +#define NAND_MAX_PAGESIZE 8192 +#endif /* * Constants for hardware specific CLE/ALE/NCE function @@ -76,7 +95,6 @@ extern void nand_wait_ready(struct mtd_info *mtd); #define NAND_CMD_READOOB 0x50 #define NAND_CMD_ERASE1 0x60 #define NAND_CMD_STATUS 0x70 -#define NAND_CMD_STATUS_MULTI 0x71 #define NAND_CMD_SEQIN 0x80 #define NAND_CMD_RNDIN 0x85 #define NAND_CMD_READID 0x90 @@ -87,10 +105,8 @@ extern void nand_wait_ready(struct mtd_info *mtd); #define NAND_CMD_RESET 0xff #define NAND_CMD_LOCK 0x2a -#define NAND_CMD_LOCK_TIGHT 0x2c #define NAND_CMD_UNLOCK1 0x23 #define NAND_CMD_UNLOCK2 0x24 -#define NAND_CMD_LOCK_STATUS 0x7a /* Extended commands for large page devices */ #define NAND_CMD_READSTART 0x30 @@ -164,21 +180,12 @@ typedef enum { /* Chip has copy back function */ #define NAND_COPYBACK 0x00000010 /* - * AND Chip which has 4 banks and a confusing page / block - * assignment. See Renesas datasheet for further information. + * Chip requires ready check on read (for auto-incremented sequential read). + * True only for small page devices; large page devices do not support + * autoincrement. */ -#define NAND_IS_AND 0x00000020 -/* - * Chip has a array of 4 pages which can be read without - * additional ready /busy waits. - */ -#define NAND_4PAGE_ARRAY 0x00000040 -/* - * Chip requires that BBT is periodically rewritten to prevent - * bits from adjacent blocks from 'leaking' in altering data. - * This happens with the Renesas AG-AND chips, possibly others. - */ -#define BBT_AUTO_REFRESH 0x00000080 +#define NAND_NEED_READRDY 0x00000100 + /* Chip does not allow subpage writes */ #define NAND_NO_SUBPAGE_WRITE 0x00000200 @@ -189,16 +196,13 @@ typedef enum { #define NAND_ROM 0x00000800 /* Device supports subpage reads */ -#define NAND_SUBPAGE_READ 0x00001000 +#define NAND_SUBPAGE_READ 0x00001000 /* Options valid for Samsung large page devices */ -#define NAND_SAMSUNG_LP_OPTIONS \ - (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) +#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG /* Macros to identify the above */ -#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) -#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) /* Non chip related options */ @@ -211,6 +215,13 @@ typedef enum { #define NAND_OWN_BUFFERS 0x00020000 /* Chip may not exist, so silence any errors in scan */ #define NAND_SCAN_SILENT_NODEV 0x00040000 +/* + * Autodetect nand buswidth with readid/onfi. + * This suppose the driver will configure the hardware in 8 bits mode + * when calling nand_scan_ident, and update its configuration + * before calling nand_scan_tail. + */ +#define NAND_BUSWIDTH_AUTO 0x00080000 /* Options set by nand scan */ /* bbt has already been read */ @@ -221,10 +232,15 @@ typedef enum { /* Cell info constants */ #define NAND_CI_CHIPNR_MSK 0x03 #define NAND_CI_CELLTYPE_MSK 0x0C +#define NAND_CI_CELLTYPE_SHIFT 2 /* Keep gcc happy */ struct nand_chip; +/* ONFI features */ +#define ONFI_FEATURE_16_BIT_BUS (1 << 0) +#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) + /* ONFI timing mode, used in both asynchronous and synchronous mode */ #define ONFI_TIMING_MODE_0 (1 << 0) #define ONFI_TIMING_MODE_1 (1 << 1) @@ -237,9 +253,15 @@ struct nand_chip; /* ONFI feature address */ #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 +/* Vendor-specific feature address (Micron) */ +#define ONFI_FEATURE_ADDR_READ_RETRY 0x89 + /* ONFI subfeature parameters length */ #define ONFI_SUBFEATURE_PARAM_LEN 4 +/* ONFI optional commands SET/GET FEATURES supported? */ +#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) + struct nand_onfi_params { /* rev info and features block */ /* 'O' 'N' 'F' 'I' */ @@ -247,7 +269,10 @@ struct nand_onfi_params { __le16 revision; __le16 features; __le16 opt_cmd; - u8 reserved[22]; + u8 reserved0[2]; + __le16 ext_param_page_length; /* since ONFI 2.1 */ + u8 num_of_param_pages; /* since ONFI 2.1 */ + u8 reserved1[17]; /* manufacturer information block */ char manufacturer[12]; @@ -291,19 +316,152 @@ struct nand_onfi_params { __le16 io_pin_capacitance_typ; __le16 input_pin_capacitance_typ; u8 input_pin_capacitance_max; - u8 driver_strenght_support; + u8 driver_strength_support; __le16 t_int_r; __le16 t_ald; u8 reserved4[7]; /* vendor */ - u8 reserved5[90]; + __le16 vendor_revision; + u8 vendor[88]; __le16 crc; -} __attribute__((packed)); +} __packed; #define ONFI_CRC_BASE 0x4F4E +/* Extended ECC information Block Definition (since ONFI 2.1) */ +struct onfi_ext_ecc_info { + u8 ecc_bits; + u8 codeword_size; + __le16 bb_per_lun; + __le16 block_endurance; + u8 reserved[2]; +} __packed; + +#define ONFI_SECTION_TYPE_0 0 /* Unused section. */ +#define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ +#define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ +struct onfi_ext_section { + u8 type; + u8 length; +} __packed; + +#define ONFI_EXT_SECTION_MAX 8 + +/* Extended Parameter Page Definition (since ONFI 2.1) */ +struct onfi_ext_param_page { + __le16 crc; + u8 sig[4]; /* 'E' 'P' 'P' 'S' */ + u8 reserved0[10]; + struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; + + /* + * The actual size of the Extended Parameter Page is in + * @ext_param_page_length of nand_onfi_params{}. + * The following are the variable length sections. + * So we do not add any fields below. Please see the ONFI spec. + */ +} __packed; + +struct nand_onfi_vendor_micron { + u8 two_plane_read; + u8 read_cache; + u8 read_unique_id; + u8 dq_imped; + u8 dq_imped_num_settings; + u8 dq_imped_feat_addr; + u8 rb_pulldown_strength; + u8 rb_pulldown_strength_feat_addr; + u8 rb_pulldown_strength_num_settings; + u8 otp_mode; + u8 otp_page_start; + u8 otp_data_prot_addr; + u8 otp_num_pages; + u8 otp_feat_addr; + u8 read_retry_options; + u8 reserved[72]; + u8 param_revision; +} __packed; + +struct jedec_ecc_info { + u8 ecc_bits; + u8 codeword_size; + __le16 bb_per_lun; + __le16 block_endurance; + u8 reserved[2]; +} __packed; + +/* JEDEC features */ +#define JEDEC_FEATURE_16_BIT_BUS (1 << 0) + +struct nand_jedec_params { + /* rev info and features block */ + /* 'J' 'E' 'S' 'D' */ + u8 sig[4]; + __le16 revision; + __le16 features; + u8 opt_cmd[3]; + __le16 sec_cmd; + u8 num_of_param_pages; + u8 reserved0[18]; + + /* manufacturer information block */ + char manufacturer[12]; + char model[20]; + u8 jedec_id[6]; + u8 reserved1[10]; + + /* memory organization block */ + __le32 byte_per_page; + __le16 spare_bytes_per_page; + u8 reserved2[6]; + __le32 pages_per_block; + __le32 blocks_per_lun; + u8 lun_count; + u8 addr_cycles; + u8 bits_per_cell; + u8 programs_per_page; + u8 multi_plane_addr; + u8 multi_plane_op_attr; + u8 reserved3[38]; + + /* electrical parameter block */ + __le16 async_sdr_speed_grade; + __le16 toggle_ddr_speed_grade; + __le16 sync_ddr_speed_grade; + u8 async_sdr_features; + u8 toggle_ddr_features; + u8 sync_ddr_features; + __le16 t_prog; + __le16 t_bers; + __le16 t_r; + __le16 t_r_multi_plane; + __le16 t_ccs; + __le16 io_pin_capacitance_typ; + __le16 input_pin_capacitance_typ; + __le16 clk_pin_capacitance_typ; + u8 driver_strength_support; + __le16 t_ald; + u8 reserved4[36]; + + /* ECC and endurance block */ + u8 guaranteed_good_blocks; + __le16 guaranteed_block_endurance; + struct jedec_ecc_info ecc_info[4]; + u8 reserved5[29]; + + /* reserved */ + u8 reserved6[148]; + + /* vendor */ + __le16 vendor_rev_num; + u8 reserved7[88]; + + /* CRC for Parameter Page */ + __le16 crc; +} __packed; + /** * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices * @lock: protection lock @@ -313,12 +471,11 @@ struct nand_onfi_params { * when a hw controller is available. */ struct nand_hw_control { -/* XXX U-BOOT XXX */ -#if 0 - spinlock_t lock; + spinlock_t lock; + struct nand_chip *active; +#ifndef __UBOOT__ wait_queue_head_t wq; #endif - struct nand_chip *active; }; /** @@ -344,6 +501,7 @@ struct nand_hw_control { * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error * @read_subpage: function to read parts of the page covered by ECC; * returns same as read_page() + * @write_subpage: function to write parts of the page covered by ECC. * @write_page: function to write a page according to the ECC generator * requirements. * @write_oob_raw: function to write chip OOB data without ECC @@ -374,7 +532,10 @@ struct nand_ecc_ctrl { int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, - uint32_t offs, uint32_t len, uint8_t *buf); + uint32_t offs, uint32_t len, uint8_t *buf, int page); + int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, + uint32_t offset, uint32_t data_len, + const uint8_t *data_buf, int oob_required); int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int oob_required); int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, @@ -388,18 +549,24 @@ struct nand_ecc_ctrl { /** * struct nand_buffers - buffer structure for read/write - * @ecccalc: buffer for calculated ECC - * @ecccode: buffer for ECC read from flash - * @databuf: buffer for data - dynamically sized + * @ecccalc: buffer pointer for calculated ECC, size is oobsize. + * @ecccode: buffer pointer for ECC read from flash, size is oobsize. + * @databuf: buffer pointer for data, size is (page size + oobsize). * * Do not change the order of buffers. databuf and oobrbuf must be in * consecutive order. */ struct nand_buffers { +#ifndef __UBOOT__ + uint8_t *ecccalc; + uint8_t *ecccode; + uint8_t *databuf; +#else uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; +#endif }; /** @@ -410,13 +577,13 @@ struct nand_buffers { * flash device. * @read_byte: [REPLACEABLE] read one byte from the chip * @read_word: [REPLACEABLE] read one word from the chip + * @write_byte: [REPLACEABLE] write a single byte to the chip on the + * low 8 I/O lines * @write_buf: [REPLACEABLE] write data from the buffer to the chip * @read_buf: [REPLACEABLE] read data from the chip into the buffer - * @verify_buf: [REPLACEABLE] verify buffer contents against the chip - * data. * @select_chip: [REPLACEABLE] select chip nr - * @block_bad: [REPLACEABLE] check, if the block is bad - * @block_markbad: [REPLACEABLE] mark the block bad + * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers + * @block_markbad: [REPLACEABLE] mark a block bad * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling * ALE/CLE/nCE. Also used to write command and address * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting @@ -431,6 +598,8 @@ struct nand_buffers { * commands to the chip. * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on * ready. + * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for + * setting the read-retry mode. Mostly needed for MLC NAND. * @ecc: [BOARDSPECIFIC] ECC control structure * @buffers: buffer structure for read/write * @hwcontrol: platform-specific hardware control structure @@ -458,20 +627,32 @@ struct nand_buffers { * @badblockbits: [INTERN] minimum number of set bits in a good block's * bad block marker position; i.e., BBM == 11110111b is * not bad when badblockbits == 7 - * @cellinfo: [INTERN] MLC/multichip data from chip ident + * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. + * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. + * Minimum amount of bit errors per @ecc_step_ds guaranteed + * to be correctable. If unknown, set to zero. + * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, + * also from the datasheet. It is the recommended ECC step + * size, if known; if unknown, set to zero. * @numchips: [INTERN] number of physical chips * @chipsize: [INTERN] the size of one chip for multichip arrays * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 * @pagebuf: [INTERN] holds the pagenumber which is currently in * data_buf. + * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is + * currently in data_buf. * @subpagesize: [INTERN] holds the subpagesize * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), * non 0 if ONFI supported. + * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), + * non 0 if JEDEC supported. * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is * supported, 0 otherwise. - * @onfi_set_features [REPLACEABLE] set the features for ONFI nand - * @onfi_get_features [REPLACEABLE] get the features for ONFI nand - * @ecclayout: [REPLACEABLE] the default ECC placement scheme + * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is + * supported, 0 otherwise. + * @read_retries: [INTERN] the number of read retry modes supported + * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand + * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand * @bbt: [INTERN] bad block table pointer * @bbt_td: [REPLACEABLE] bad block table descriptor for flash * lookup. @@ -494,9 +675,14 @@ struct nand_chip { uint8_t (*read_byte)(struct mtd_info *mtd); u16 (*read_word)(struct mtd_info *mtd); + void (*write_byte)(struct mtd_info *mtd, uint8_t byte); void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); - int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); +#ifdef __UBOOT__ +#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) + int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); +#endif +#endif void (*select_chip)(struct mtd_info *mtd, int chip); int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); @@ -512,12 +698,13 @@ struct nand_chip { int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, - const uint8_t *buf, int oob_required, int page, - int cached, int raw); + uint32_t offset, int data_len, const uint8_t *buf, + int oob_required, int page, int cached, int raw); int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, int feature_addr, uint8_t *subfeature_para); int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, int feature_addr, uint8_t *subfeature_para); + int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); int chip_delay; unsigned int options; @@ -531,21 +718,30 @@ struct nand_chip { uint64_t chipsize; int pagemask; int pagebuf; + unsigned int pagebuf_bitflips; int subpagesize; - uint8_t cellinfo; + uint8_t bits_per_cell; + uint16_t ecc_strength_ds; + uint16_t ecc_step_ds; int badblockpos; int badblockbits; int onfi_version; + int jedec_version; #ifdef CONFIG_SYS_NAND_ONFI_DETECTION - struct nand_onfi_params onfi_params; + struct nand_onfi_params onfi_params; #endif + struct nand_jedec_params jedec_params; + + int read_retries; - int state; + flstate_t state; uint8_t *oob_poi; struct nand_hw_control *controller; +#ifdef __UBOOT__ struct nand_ecclayout *ecclayout; +#endif struct nand_ecc_ctrl ecc; struct nand_buffers *buffers; @@ -574,26 +770,83 @@ struct nand_chip { #define NAND_MFR_AMD 0x01 #define NAND_MFR_MACRONIX 0xc2 #define NAND_MFR_EON 0x92 +#define NAND_MFR_SANDISK 0x45 +#define NAND_MFR_INTEL 0x89 + +/* The maximum expected count of bytes in the NAND ID sequence */ +#define NAND_MAX_ID_LEN 8 + +/* + * A helper for defining older NAND chips where the second ID byte fully + * defined the chip, including the geometry (chip size, eraseblock size, page + * size). All these chips have 512 bytes NAND page size. + */ +#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ + { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ + .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } + +/* + * A helper for defining newer chips which report their page size and + * eraseblock size via the extended ID bytes. + * + * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with + * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the + * device ID now only represented a particular total chip size (and voltage, + * buswidth), and the page size, eraseblock size, and OOB size could vary while + * using the same device ID. + */ +#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ + { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ + .options = (opts) } + +#define NAND_ECC_INFO(_strength, _step) \ + { .strength_ds = (_strength), .step_ds = (_step) } +#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) +#define NAND_ECC_STEP(type) ((type)->ecc.step_ds) /** * struct nand_flash_dev - NAND Flash Device ID Structure - * @name: Identify the device type - * @id: device ID code - * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 - * If the pagesize is 0, then the real pagesize - * and the eraseize are determined from the - * extended id bytes in the chip - * @erasesize: Size of an erase block in the flash device. - * @chipsize: Total chipsize in Mega Bytes - * @options: Bitfield to store chip relevant options + * @name: a human-readable name of the NAND chip + * @dev_id: the device ID (the second byte of the full chip ID array) + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: device ID part of the full chip ID array (refers the same memory + * address as @id[1]) + * @id: full device ID array + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @chipsize: total chip size in MiB + * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) + * @options: stores various chip bit options + * @id_len: The valid length of the @id. + * @oobsize: OOB size + * @ecc.strength_ds: The ECC correctability from the datasheet, same as the + * @ecc_strength_ds in nand_chip{}. + * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the + * @ecc_step_ds in nand_chip{}, also from the datasheet. + * For example, the "4bit ECC for each 512Byte" can be set with + * NAND_ECC_INFO(4, 512). */ struct nand_flash_dev { char *name; - int id; - unsigned long pagesize; - unsigned long chipsize; - unsigned long erasesize; - unsigned long options; + union { + struct { + uint8_t mfr_id; + uint8_t dev_id; + }; + uint8_t id[NAND_MAX_ID_LEN]; + }; + unsigned int pagesize; + unsigned int chipsize; + unsigned int erasesize; + unsigned int options; + uint16_t id_len; + uint16_t oobsize; + struct { + uint16_t strength_ds; + uint16_t step_ds; + } ecc; }; /** @@ -606,23 +859,25 @@ struct nand_manufacturers { char *name; }; -extern const struct nand_flash_dev nand_flash_ids[]; -extern const struct nand_manufacturers nand_manuf_ids[]; +extern struct nand_flash_dev nand_flash_ids[]; +extern struct nand_manufacturers nand_manuf_ids[]; extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); -extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); extern int nand_default_bbt(struct mtd_info *mtd); +extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt); extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, uint8_t *buf); +#ifdef __UBOOT__ /* * Constants for oob configuration */ #define NAND_SMALL_BADBLOCK_POS 5 #define NAND_LARGE_BADBLOCK_POS 0 +#endif /** * struct platform_nand_chip - chip level device structure @@ -653,20 +908,29 @@ struct platform_device; /** * struct platform_nand_ctrl - controller level device structure + * @probe: platform specific function to probe/setup hardware + * @remove: platform specific function to remove/teardown hardware * @hwcontrol: platform specific hardware control structure * @dev_ready: platform specific function to read ready/busy pin * @select_chip: platform specific chip select function * @cmd_ctrl: platform specific function for controlling * ALE/CLE/nCE. Also used to write command and address + * @write_buf: platform specific function for write buffer + * @read_buf: platform specific function for read buffer + * @read_byte: platform specific function to read one byte from chip * @priv: private data to transport driver specific settings * * All fields are optional and depend on the hardware driver requirements */ struct platform_nand_ctrl { + int (*probe)(struct platform_device *pdev); + void (*remove)(struct platform_device *pdev); void (*hwcontrol)(struct mtd_info *mtd, int cmd); int (*dev_ready)(struct mtd_info *mtd); void (*select_chip)(struct mtd_info *mtd, int chip); void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); + void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); + void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); unsigned char (*read_byte)(struct mtd_info *mtd); void *priv; }; @@ -690,16 +954,14 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) return chip->priv; } -/* Standard NAND functions from nand_base.c */ -void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); -void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); -void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); -void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); -uint8_t nand_read_byte(struct mtd_info *mtd); +#ifdef CONFIG_SYS_NAND_ONFI_DETECTION +/* return the supported features. */ +static inline int onfi_feature(struct nand_chip *chip) +{ + return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; +} /* return the supported asynchronous timing mode. */ - -#ifdef CONFIG_SYS_NAND_ONFI_DETECTION static inline int onfi_get_async_timing_mode(struct nand_chip *chip) { if (!chip->onfi_version) @@ -716,4 +978,47 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) } #endif +/* + * Check if it is a SLC nand. + * The !nand_is_slc() can be used to check the MLC/TLC nand chips. + * We do not distinguish the MLC and TLC now. + */ +static inline bool nand_is_slc(struct nand_chip *chip) +{ + return chip->bits_per_cell == 1; +} + +/** + * Check if the opcode's address should be sent only on the lower 8 bits + * @command: opcode to check + */ +static inline int nand_opcode_8bits(unsigned int command) +{ + switch (command) { + case NAND_CMD_READID: + case NAND_CMD_PARAM: + case NAND_CMD_GET_FEATURES: + case NAND_CMD_SET_FEATURES: + return 1; + default: + break; + } + return 0; +} + +/* return the supported JEDEC features. */ +static inline int jedec_feature(struct nand_chip *chip) +{ + return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) + : 0; +} + +#ifdef __UBOOT__ +/* Standard NAND functions from nand_base.c */ +void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); +void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); +void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); +void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); +uint8_t nand_read_byte(struct mtd_info *mtd); +#endif #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/linux/mtd/nftl-user.h b/include/linux/mtd/nftl-user.h deleted file mode 100644 index 22b8b707e5..0000000000 --- a/include/linux/mtd/nftl-user.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * $Id: nftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $ - * - * Parts of NFTL headers shared with userspace - * - */ - -#ifndef __MTD_NFTL_USER_H__ -#define __MTD_NFTL_USER_H__ - -/* Block Control Information */ - -struct nftl_bci { - unsigned char ECCSig[6]; - uint8_t Status; - uint8_t Status1; -}__attribute__((packed)); - -/* Unit Control Information */ - -struct nftl_uci0 { - uint16_t VirtUnitNum; - uint16_t ReplUnitNum; - uint16_t SpareVirtUnitNum; - uint16_t SpareReplUnitNum; -} __attribute__((packed)); - -struct nftl_uci1 { - uint32_t WearInfo; - uint16_t EraseMark; - uint16_t EraseMark1; -} __attribute__((packed)); - -struct nftl_uci2 { - uint16_t FoldMark; - uint16_t FoldMark1; - uint32_t unused; -} __attribute__((packed)); - -union nftl_uci { - struct nftl_uci0 a; - struct nftl_uci1 b; - struct nftl_uci2 c; -}; - -struct nftl_oob { - struct nftl_bci b; - union nftl_uci u; -}; - -/* NFTL Media Header */ - -struct NFTLMediaHeader { - char DataOrgID[6]; - uint16_t NumEraseUnits; - uint16_t FirstPhysicalEUN; - uint32_t FormattedSize; - unsigned char UnitSizeFactor; -} __attribute__((packed)); - -#define MAX_ERASE_ZONES (8192 - 512) - -#define ERASE_MARK 0x3c69 -#define SECTOR_FREE 0xff -#define SECTOR_USED 0x55 -#define SECTOR_IGNORE 0x11 -#define SECTOR_DELETED 0x00 - -#define FOLD_MARK_IN_PROGRESS 0x5555 - -#define ZONE_GOOD 0xff -#define ZONE_BAD_ORIGINAL 0 -#define ZONE_BAD_MARKED 7 - - -#endif /* __MTD_NFTL_USER_H__ */ diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h deleted file mode 100644 index fe22e0dceb..0000000000 --- a/include/linux/mtd/nftl.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) 1999-2003 David Woodhouse - */ - -#ifndef __MTD_NFTL_H__ -#define __MTD_NFTL_H__ - -#include -#include - -#include - -/* these info are used in ReplUnitTable */ -#define BLOCK_NIL 0xffff /* last block of a chain */ -#define BLOCK_FREE 0xfffe /* free block */ -#define BLOCK_NOTEXPLORED 0xfffd /* non explored block, only used during mounting */ -#define BLOCK_RESERVED 0xfffc /* bios block or bad block */ - -struct NFTLrecord { - struct mtd_blktrans_dev mbd; - __u16 MediaUnit, SpareMediaUnit; - __u32 EraseSize; - struct NFTLMediaHeader MediaHdr; - int usecount; - unsigned char heads; - unsigned char sectors; - unsigned short cylinders; - __u16 numvunits; - __u16 lastEUN; /* should be suppressed */ - __u16 numfreeEUNs; - __u16 LastFreeEUN; /* To speed up finding a free EUN */ - int head,sect,cyl; - __u16 *EUNtable; /* [numvunits]: First EUN for each virtual unit */ - __u16 *ReplUnitTable; /* [numEUNs]: ReplUnitNumber for each */ - unsigned int nb_blocks; /* number of physical blocks */ - unsigned int nb_boot_blocks; /* number of blocks used by the bios */ - struct erase_info instr; - struct nand_ecclayout oobinfo; -}; - -int NFTL_mount(struct NFTLrecord *s); -int NFTL_formatblock(struct NFTLrecord *s, int block); - -int nftl_read_oob(struct mtd_info *mtd, loff_t offs, size_t len, - size_t *retlen, uint8_t *buf); -int nftl_write_oob(struct mtd_info *mtd, loff_t offs, size_t len, - size_t *retlen, uint8_t *buf); - -#ifndef NFTL_MAJOR -#define NFTL_MAJOR 93 -#endif - -#define MAX_NFTLS 16 -#define MAX_SECTORS_PER_UNIT 64 -#define NFTL_PARTN_BITS 4 - -#endif /* __MTD_NFTL_H__ */ diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h new file mode 100644 index 0000000000..b8096b02e3 --- /dev/null +++ b/include/linux/mtd/omap_elm.h @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, + * Mansoor Ahamed + * + * Derived from work done by Rohit Choraria for omap3 + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_ELM_H +#define __ASM_ARCH_ELM_H +/* + * ELM Module Registers + */ + +/* ELM registers bit fields */ +#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) +#define ELM_SYSCONFIG_SOFTRESET (0x2) +#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) +#define ELM_SYSSTATUS_RESETDONE (0x1) +#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) +#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) +#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) +#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) +#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) +#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) + +#define ELM_MAX_CHANNELS 8 +#define ELM_MAX_ERROR_COUNT 16 + +#ifndef __ASSEMBLY__ + +enum bch_level { + BCH_4_BIT = 0, + BCH_8_BIT, + BCH_16_BIT +}; + + +/* BCH syndrome registers */ +struct syndrome { + u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ + u8 res1[36]; /* 0x41c */ +}; + +/* BCH error status & location register */ +struct location { + u32 location_status; /* 0x800 */ + u8 res1[124]; /* 0x804 */ + u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */ + u8 res2[64]; /* 0x8c0 */ +}; + +/* BCH ELM register map - do not try to allocate memmory for this structure. + * We have used plenty of reserved variables to fill the slots in the ELM + * register memory map. + * Directly initialize the struct pointer to ELM base address. + */ +struct elm { + u32 rev; /* 0x000 */ + u8 res1[12]; /* 0x004 */ + u32 sysconfig; /* 0x010 */ + u32 sysstatus; /* 0x014 */ + u32 irqstatus; /* 0x018 */ + u32 irqenable; /* 0x01c */ + u32 location_config; /* 0x020 */ + u8 res2[92]; /* 0x024 */ + u32 page_ctrl; /* 0x080 */ + u8 res3[892]; /* 0x084 */ + struct syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */ + u8 res4[512]; /* 0x600 */ + struct location error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */ +}; + +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, + u32 *error_locations); +int elm_config(enum bch_level level); +void elm_reset(void); +void elm_init(void); +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_ELM_H */ diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h new file mode 100644 index 0000000000..6cbae45022 --- /dev/null +++ b/include/linux/mtd/omap_gpmc.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2004-2008 Texas Instruments, + * Rohit Choraria + * + * (C) Copyright 2013 Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_OMAP_GPMC_H +#define __ASM_OMAP_GPMC_H + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 +#define GPMC_MAX_SECTORS 8 + +enum omap_ecc { + /* 1-bit ECC calculation by Software, Error detection by Software */ + OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ + /* 1-bit ECC calculation by GPMC, Error detection by Software */ + /* ECC layout compatible to legacy ROMCODE. */ + OMAP_ECC_HAM1_CODE_HW, + /* 4-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, + /* 4-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH4_CODE_HW, + /* 8-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + /* 8-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH8_CODE_HW, + /* 16-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH16_CODE_HW, +}; + +struct gpmc_cs { + u32 config1; /* 0x00 */ + u32 config2; /* 0x04 */ + u32 config3; /* 0x08 */ + u32 config4; /* 0x0C */ + u32 config5; /* 0x10 */ + u32 config6; /* 0x14 */ + u32 config7; /* 0x18 */ + u32 nand_cmd; /* 0x1C */ + u32 nand_adr; /* 0x20 */ + u32 nand_dat; /* 0x24 */ + u8 res[8]; /* blow up to 0x30 byte */ +}; + +struct bch_res_0_3 { + u32 bch_result_x[4]; +}; + +struct bch_res_4_6 { + u32 bch_result_x[3]; +}; + +struct gpmc { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x4]; + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res3[0x20]; + u32 timeout_control; /* 0x40 */ + u8 res4[0xC]; + u32 config; /* 0x50 */ + u32 status; /* 0x54 */ + u8 res5[0x8]; /* 0x58 */ + struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ + u32 prefetch_config1; /* 0x1E0 */ + u32 prefetch_config2; /* 0x1E4 */ + u32 res6; /* 0x1E8 */ + u32 prefetch_control; /* 0x1EC */ + u32 prefetch_status; /* 0x1F0 */ + u32 ecc_config; /* 0x1F4 */ + u32 ecc_control; /* 0x1F8 */ + u32 ecc_size_config; /* 0x1FC */ + u32 ecc1_result; /* 0x200 */ + u32 ecc2_result; /* 0x204 */ + u32 ecc3_result; /* 0x208 */ + u32 ecc4_result; /* 0x20C */ + u32 ecc5_result; /* 0x210 */ + u32 ecc6_result; /* 0x214 */ + u32 ecc7_result; /* 0x218 */ + u32 ecc8_result; /* 0x21C */ + u32 ecc9_result; /* 0x220 */ + u8 res7[12]; /* 0x224 */ + u32 testmomde_ctrl; /* 0x230 */ + u8 res8[12]; /* 0x234 */ + struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */ + u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */ + struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */ +}; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + +#endif /* __ASM_OMAP_GPMC_H */ diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index d1d9a96d58..ce0e8dbee4 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -1,11 +1,9 @@ /* * MTD partitioning layer definitions * - * (C) 2000 Nicolas Pitre + * (C) 2000 Nicolas Pitre * * This code is GPL - * - * $Id: partitions.h,v 1.17 2005/11/07 11:14:55 gleixner Exp $ */ #ifndef MTD_PARTITIONS_H @@ -18,7 +16,7 @@ * Partition definition structure: * * An array of struct partition is passed along with a MTD object to - * add_mtd_partitions() to create them. + * mtd_device_register() to create them. * * For each partition, these fields are available: * name: string that will be used to label the partition's MTD device. @@ -26,7 +24,9 @@ * will extend to the end of the master MTD device. * offset: absolute starting position within the master MTD device; if * defined as MTDPART_OFS_APPEND, the partition will start where the - * previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block. + * previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block; + * if MTDPART_OFS_RETAIN, consume as much as possible, leaving size + * after the end of partition. * mask_flags: contains flags that have to be masked (removed) from the * master MTD flag set for the corresponding MTD partition. * For example, to force a read-only partition, simply adding @@ -37,23 +37,34 @@ */ struct mtd_partition { - char *name; /* identifier string */ + const char *name; /* identifier string */ uint64_t size; /* partition size */ uint64_t offset; /* offset within the master MTD space */ - u_int32_t mask_flags; /* master MTD flags to mask out for this partition */ - struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/ - struct mtd_info **mtdp; /* pointer to store the MTD object */ + uint32_t mask_flags; /* master MTD flags to mask out for this partition */ + struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only) */ }; +#define MTDPART_OFS_RETAIN (-3) #define MTDPART_OFS_NXTBLK (-2) #define MTDPART_OFS_APPEND (-1) #define MTDPART_SIZ_FULL (0) -int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); -int del_mtd_partitions(struct mtd_info *); +struct mtd_info; +struct device_node; + +#ifndef __UBOOT__ +/** + * struct mtd_part_parser_data - used to pass data to MTD partition parsers. + * @origin: for RedBoot, start address of MTD device + * @of_node: for OF parsers, device node containing partitioning information + */ +struct mtd_part_parser_data { + unsigned long origin; + struct device_node *of_node; +}; + -#if 0 /* * Functions dealing with the various ways of partitioning the space */ @@ -62,23 +73,18 @@ struct mtd_part_parser { struct list_head list; struct module *owner; const char *name; - int (*parse_fn)(struct mtd_info *, struct mtd_partition **, unsigned long); + int (*parse_fn)(struct mtd_info *, struct mtd_partition **, + struct mtd_part_parser_data *); }; -extern int register_mtd_parser(struct mtd_part_parser *parser); -extern int deregister_mtd_parser(struct mtd_part_parser *parser); -extern int parse_mtd_partitions(struct mtd_info *master, const char **types, - struct mtd_partition **pparts, unsigned long origin); - -#define put_partition_parser(p) do { module_put((p)->owner); } while(0) - -struct device; -struct device_node; - -int __devinit of_mtd_parse_partitions(struct device *dev, - struct mtd_info *mtd, - struct device_node *node, - struct mtd_partition **pparts); +extern void register_mtd_parser(struct mtd_part_parser *parser); +extern void deregister_mtd_parser(struct mtd_part_parser *parser); #endif +int mtd_is_partition(const struct mtd_info *mtd); +int mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length); +int mtd_del_partition(struct mtd_info *master, int partno); +uint64_t mtd_get_device_size(const struct mtd_info *mtd); + #endif diff --git a/include/linux/mtd/ubi.h b/include/linux/mtd/ubi.h index 4755770c54..05d0ab54c0 100644 --- a/include/linux/mtd/ubi.h +++ b/include/linux/mtd/ubi.h @@ -9,9 +9,14 @@ #ifndef __LINUX_UBI_H__ #define __LINUX_UBI_H__ -/* #include */ #include +#ifndef __UBOOT__ +#include #include +#endif + +/* All voumes/LEBs */ +#define UBI_ALL -1 /* * enum ubi_open_mode - UBI volume open mode constants. @@ -33,13 +38,13 @@ enum { * @size: how many physical eraseblocks are reserved for this volume * @used_bytes: how many bytes of data this volume contains * @used_ebs: how many physical eraseblocks of this volume actually contain any - * data + * data * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME) * @corrupted: non-zero if the volume is corrupted (static volumes only) * @upd_marker: non-zero if the volume has update marker set * @alignment: volume alignment * @usable_leb_size: how many bytes are available in logical eraseblocks of - * this volume + * this volume * @name_len: volume name length * @name: volume name * @cdev: UBI volume character device major and minor numbers @@ -75,7 +80,7 @@ enum { * physical eraseblock size and on how much bytes UBI headers consume. But * because of the volume alignment (@alignment), the usable size of logical * eraseblocks if a volume may be less. The following equation is true: - * @usable_leb_size = LEB size - (LEB size mod @alignment), + * @usable_leb_size = LEB size - (LEB size mod @alignment), * where LEB size is the logical eraseblock size defined by the UBI device. * * The alignment is multiple to the minimal flash input/output unit size or %1 @@ -104,20 +109,79 @@ struct ubi_volume_info { * struct ubi_device_info - UBI device description data structure. * @ubi_num: ubi device number * @leb_size: logical eraseblock size on this UBI device + * @leb_start: starting offset of logical eraseblocks within physical + * eraseblocks * @min_io_size: minimal I/O unit size + * @max_write_size: maximum amount of bytes the underlying flash can write at a + * time (MTD write buffer size) * @ro_mode: if this device is in read-only mode * @cdev: UBI character device major and minor numbers * * Note, @leb_size is the logical eraseblock size offered by the UBI device. * Volumes of this UBI device may have smaller logical eraseblock size if their * alignment is not equivalent to %1. + * + * The @max_write_size field describes flash write maximum write unit. For + * example, NOR flash allows for changing individual bytes, so @min_io_size is + * %1. However, it does not mean than NOR flash has to write data byte-by-byte. + * Instead, CFI NOR flashes have a write-buffer of, e.g., 64 bytes, and when + * writing large chunks of data, they write 64-bytes at a time. Obviously, this + * improves write throughput. + * + * Also, the MTD device may have N interleaved (striped) flash chips + * underneath, in which case @min_io_size can be physical min. I/O size of + * single flash chip, while @max_write_size can be N * @min_io_size. + * + * The @max_write_size field is always greater or equivalent to @min_io_size. + * E.g., some NOR flashes may have (@min_io_size = 1, @max_write_size = 64). In + * contrast, NAND flashes usually have @min_io_size = @max_write_size = NAND + * page size. */ struct ubi_device_info { int ubi_num; int leb_size; + int leb_start; int min_io_size; + int max_write_size; int ro_mode; +#ifndef __UBOOT__ dev_t cdev; +#endif +}; + +/* + * Volume notification types. + * @UBI_VOLUME_ADDED: a volume has been added (an UBI device was attached or a + * volume was created) + * @UBI_VOLUME_REMOVED: a volume has been removed (an UBI device was detached + * or a volume was removed) + * @UBI_VOLUME_RESIZED: a volume has been re-sized + * @UBI_VOLUME_RENAMED: a volume has been re-named + * @UBI_VOLUME_UPDATED: data has been written to a volume + * + * These constants define which type of event has happened when a volume + * notification function is invoked. + */ +enum { + UBI_VOLUME_ADDED, + UBI_VOLUME_REMOVED, + UBI_VOLUME_RESIZED, + UBI_VOLUME_RENAMED, + UBI_VOLUME_UPDATED, +}; + +/* + * struct ubi_notification - UBI notification description structure. + * @di: UBI device description object + * @vi: UBI volume description object + * + * UBI notifiers are called with a pointer to an object of this type. The + * object describes the notification. Namely, it provides a description of the + * UBI device and UBI volume the notification informs about. + */ +struct ubi_notification { + struct ubi_device_info di; + struct ubi_volume_info vi; }; /* UBI descriptor given to users when they open UBI volumes */ @@ -129,17 +193,37 @@ void ubi_get_volume_info(struct ubi_volume_desc *desc, struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode); struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name, int mode); +struct ubi_volume_desc *ubi_open_volume_path(const char *pathname, int mode); + +#ifndef __UBOOT__ +typedef int (*notifier_fn_t)(void *nb, + unsigned long action, void *data); + +struct notifier_block { + notifier_fn_t notifier_call; + struct notifier_block *next; + void *next; + int priority; +}; + +int ubi_register_volume_notifier(struct notifier_block *nb, + int ignore_existing); +int ubi_unregister_volume_notifier(struct notifier_block *nb); +#endif + void ubi_close_volume(struct ubi_volume_desc *desc); int ubi_leb_read(struct ubi_volume_desc *desc, int lnum, char *buf, int offset, int len, int check); int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf, - int offset, int len, int dtype); + int offset, int len); int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf, - int len, int dtype); + int len); int ubi_leb_erase(struct ubi_volume_desc *desc, int lnum); int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum); -int ubi_leb_map(struct ubi_volume_desc *desc, int lnum, int dtype); +int ubi_leb_map(struct ubi_volume_desc *desc, int lnum); int ubi_is_mapped(struct ubi_volume_desc *desc, int lnum); +int ubi_sync(int ubi_num); +int ubi_flush(int ubi_num, int vol_id, int lnum); /* * This function is the same as the 'ubi_leb_read()' function, but it does not @@ -150,25 +234,4 @@ static inline int ubi_read(struct ubi_volume_desc *desc, int lnum, char *buf, { return ubi_leb_read(desc, lnum, buf, offset, len, 0); } - -/* - * This function is the same as the 'ubi_leb_write()' functions, but it does - * not have the data type argument. - */ -static inline int ubi_write(struct ubi_volume_desc *desc, int lnum, - const void *buf, int offset, int len) -{ - return ubi_leb_write(desc, lnum, buf, offset, len, UBI_UNKNOWN); -} - -/* - * This function is the same as the 'ubi_leb_change()' functions, but it does - * not have the data type argument. - */ -static inline int ubi_change(struct ubi_volume_desc *desc, int lnum, - const void *buf, int len) -{ - return ubi_leb_change(desc, lnum, buf, len, UBI_UNKNOWN); -} - #endif /* !__LINUX_UBI_H__ */ diff --git a/include/linux/rbtree.h b/include/linux/rbtree.h index ad892d1cbb..2cc16a3e7d 100644 --- a/include/linux/rbtree.h +++ b/include/linux/rbtree.h @@ -1,7 +1,7 @@ /* Red Black Trees (C) 1999 Andrea Arcangeli - + * SPDX-License-Identifier: GPL-2.0+ linux/include/linux/rbtree.h @@ -11,138 +11,88 @@ I know it's not the cleaner way, but in C (not in C++) to get performances and genericity... - Some example of insert and search follows here. The search is a plain - normal search over an ordered tree. The insert instead must be implemented - int two steps: as first thing the code must insert the element in - order as a red leaf in the tree, then the support library function - rb_insert_color() must be called. Such function will do the - not trivial work to rebalance the rbtree if necessary. - ------------------------------------------------------------------------ -static inline struct page * rb_search_page_cache(struct inode * inode, - unsigned long offset) -{ - struct rb_node * n = inode->i_rb_page_cache.rb_node; - struct page * page; - - while (n) - { - page = rb_entry(n, struct page, rb_page_cache); - - if (offset < page->offset) - n = n->rb_left; - else if (offset > page->offset) - n = n->rb_right; - else - return page; - } - return NULL; -} - -static inline struct page * __rb_insert_page_cache(struct inode * inode, - unsigned long offset, - struct rb_node * node) -{ - struct rb_node ** p = &inode->i_rb_page_cache.rb_node; - struct rb_node * parent = NULL; - struct page * page; - - while (*p) - { - parent = *p; - page = rb_entry(parent, struct page, rb_page_cache); - - if (offset < page->offset) - p = &(*p)->rb_left; - else if (offset > page->offset) - p = &(*p)->rb_right; - else - return page; - } - - rb_link_node(node, parent, p); - - return NULL; -} - -static inline struct page * rb_insert_page_cache(struct inode * inode, - unsigned long offset, - struct rb_node * node) -{ - struct page * ret; - if ((ret = __rb_insert_page_cache(inode, offset, node))) - goto out; - rb_insert_color(node, &inode->i_rb_page_cache); - out: - return ret; -} ------------------------------------------------------------------------ + See Documentation/rbtree.txt for documentation and samples. */ #ifndef _LINUX_RBTREE_H #define _LINUX_RBTREE_H +#ifndef __UBOOT__ +#include +#endif #include -struct rb_node -{ - unsigned long rb_parent_color; -#define RB_RED 0 -#define RB_BLACK 1 +struct rb_node { + unsigned long __rb_parent_color; struct rb_node *rb_right; struct rb_node *rb_left; } __attribute__((aligned(sizeof(long)))); /* The alignment might seem pointless, but allegedly CRIS needs it */ -struct rb_root -{ +struct rb_root { struct rb_node *rb_node; }; -#define rb_parent(r) ((struct rb_node *)((r)->rb_parent_color & ~3)) -#define rb_color(r) ((r)->rb_parent_color & 1) -#define rb_is_red(r) (!rb_color(r)) -#define rb_is_black(r) rb_color(r) -#define rb_set_red(r) do { (r)->rb_parent_color &= ~1; } while (0) -#define rb_set_black(r) do { (r)->rb_parent_color |= 1; } while (0) - -static inline void rb_set_parent(struct rb_node *rb, struct rb_node *p) -{ - rb->rb_parent_color = (rb->rb_parent_color & 3) | (unsigned long)p; -} -static inline void rb_set_color(struct rb_node *rb, int color) -{ - rb->rb_parent_color = (rb->rb_parent_color & ~1) | color; -} +#define rb_parent(r) ((struct rb_node *)((r)->__rb_parent_color & ~3)) #define RB_ROOT (struct rb_root) { NULL, } #define rb_entry(ptr, type, member) container_of(ptr, type, member) -#define RB_EMPTY_ROOT(root) ((root)->rb_node == NULL) -#define RB_EMPTY_NODE(node) (rb_parent(node) == node) -#define RB_CLEAR_NODE(node) (rb_set_parent(node, node)) +#define RB_EMPTY_ROOT(root) ((root)->rb_node == NULL) + +/* 'empty' nodes are nodes that are known not to be inserted in an rbree */ +#define RB_EMPTY_NODE(node) \ + ((node)->__rb_parent_color == (unsigned long)(node)) +#define RB_CLEAR_NODE(node) \ + ((node)->__rb_parent_color = (unsigned long)(node)) + extern void rb_insert_color(struct rb_node *, struct rb_root *); extern void rb_erase(struct rb_node *, struct rb_root *); + /* Find logical next and previous nodes in a tree */ -extern struct rb_node *rb_next(struct rb_node *); -extern struct rb_node *rb_prev(struct rb_node *); -extern struct rb_node *rb_first(struct rb_root *); -extern struct rb_node *rb_last(struct rb_root *); +extern struct rb_node *rb_next(const struct rb_node *); +extern struct rb_node *rb_prev(const struct rb_node *); +extern struct rb_node *rb_first(const struct rb_root *); +extern struct rb_node *rb_last(const struct rb_root *); + +/* Postorder iteration - always visit the parent after its children */ +extern struct rb_node *rb_first_postorder(const struct rb_root *); +extern struct rb_node *rb_next_postorder(const struct rb_node *); /* Fast replacement of a single node without remove/rebalance/add/rebalance */ -extern void rb_replace_node(struct rb_node *victim, struct rb_node *new, +extern void rb_replace_node(struct rb_node *victim, struct rb_node *new, struct rb_root *root); static inline void rb_link_node(struct rb_node * node, struct rb_node * parent, struct rb_node ** rb_link) { - node->rb_parent_color = (unsigned long )parent; + node->__rb_parent_color = (unsigned long)parent; node->rb_left = node->rb_right = NULL; *rb_link = node; } +#define rb_entry_safe(ptr, type, member) \ + ({ typeof(ptr) ____ptr = (ptr); \ + ____ptr ? rb_entry(____ptr, type, member) : NULL; \ + }) + +/** + * rbtree_postorder_for_each_entry_safe - iterate over rb_root in post order of + * given type safe against removal of rb_node entry + * + * @pos: the 'type *' to use as a loop cursor. + * @n: another 'type *' to use as temporary storage + * @root: 'rb_root *' of the rbtree. + * @field: the name of the rb_node field within 'type'. + */ +#define rbtree_postorder_for_each_entry_safe(pos, n, root, field) \ + for (pos = rb_entry_safe(rb_first_postorder(root), typeof(*pos), field); \ + pos && ({ n = rb_entry_safe(rb_next_postorder(&pos->field), \ + typeof(*pos), field); 1; }); \ + pos = n) + #endif /* _LINUX_RBTREE_H */ diff --git a/include/linux/rbtree_augmented.h b/include/linux/rbtree_augmented.h new file mode 100644 index 0000000000..a86797edb6 --- /dev/null +++ b/include/linux/rbtree_augmented.h @@ -0,0 +1,220 @@ +/* + Red Black Trees + (C) 1999 Andrea Arcangeli + (C) 2002 David Woodhouse + (C) 2012 Michel Lespinasse + + * SPDX-License-Identifier: GPL-2.0+ + + linux/include/linux/rbtree_augmented.h +*/ + +#ifndef _LINUX_RBTREE_AUGMENTED_H +#define _LINUX_RBTREE_AUGMENTED_H + +#include +#include + +/* + * Please note - only struct rb_augment_callbacks and the prototypes for + * rb_insert_augmented() and rb_erase_augmented() are intended to be public. + * The rest are implementation details you are not expected to depend on. + * + * See Documentation/rbtree.txt for documentation and samples. + */ + +struct rb_augment_callbacks { + void (*propagate)(struct rb_node *node, struct rb_node *stop); + void (*copy)(struct rb_node *old, struct rb_node *new); + void (*rotate)(struct rb_node *old, struct rb_node *new); +}; + +extern void __rb_insert_augmented(struct rb_node *node, struct rb_root *root, + void (*augment_rotate)(struct rb_node *old, struct rb_node *new)); +static inline void +rb_insert_augmented(struct rb_node *node, struct rb_root *root, + const struct rb_augment_callbacks *augment) +{ + __rb_insert_augmented(node, root, augment->rotate); +} + +#define RB_DECLARE_CALLBACKS(rbstatic, rbname, rbstruct, rbfield, \ + rbtype, rbaugmented, rbcompute) \ +static inline void \ +rbname ## _propagate(struct rb_node *rb, struct rb_node *stop) \ +{ \ + while (rb != stop) { \ + rbstruct *node = rb_entry(rb, rbstruct, rbfield); \ + rbtype augmented = rbcompute(node); \ + if (node->rbaugmented == augmented) \ + break; \ + node->rbaugmented = augmented; \ + rb = rb_parent(&node->rbfield); \ + } \ +} \ +static inline void \ +rbname ## _copy(struct rb_node *rb_old, struct rb_node *rb_new) \ +{ \ + rbstruct *old = rb_entry(rb_old, rbstruct, rbfield); \ + rbstruct *new = rb_entry(rb_new, rbstruct, rbfield); \ + new->rbaugmented = old->rbaugmented; \ +} \ +static void \ +rbname ## _rotate(struct rb_node *rb_old, struct rb_node *rb_new) \ +{ \ + rbstruct *old = rb_entry(rb_old, rbstruct, rbfield); \ + rbstruct *new = rb_entry(rb_new, rbstruct, rbfield); \ + new->rbaugmented = old->rbaugmented; \ + old->rbaugmented = rbcompute(old); \ +} \ +rbstatic const struct rb_augment_callbacks rbname = { \ + rbname ## _propagate, rbname ## _copy, rbname ## _rotate \ +}; + + +#define RB_RED 0 +#define RB_BLACK 1 + +#define __rb_parent(pc) ((struct rb_node *)(pc & ~3)) + +#define __rb_color(pc) ((pc) & 1) +#define __rb_is_black(pc) __rb_color(pc) +#define __rb_is_red(pc) (!__rb_color(pc)) +#define rb_color(rb) __rb_color((rb)->__rb_parent_color) +#define rb_is_red(rb) __rb_is_red((rb)->__rb_parent_color) +#define rb_is_black(rb) __rb_is_black((rb)->__rb_parent_color) + +static inline void rb_set_parent(struct rb_node *rb, struct rb_node *p) +{ + rb->__rb_parent_color = rb_color(rb) | (unsigned long)p; +} + +static inline void rb_set_parent_color(struct rb_node *rb, + struct rb_node *p, int color) +{ + rb->__rb_parent_color = (unsigned long)p | color; +} + +static inline void +__rb_change_child(struct rb_node *old, struct rb_node *new, + struct rb_node *parent, struct rb_root *root) +{ + if (parent) { + if (parent->rb_left == old) + parent->rb_left = new; + else + parent->rb_right = new; + } else + root->rb_node = new; +} + +extern void __rb_erase_color(struct rb_node *parent, struct rb_root *root, + void (*augment_rotate)(struct rb_node *old, struct rb_node *new)); + +static __always_inline struct rb_node * +__rb_erase_augmented(struct rb_node *node, struct rb_root *root, + const struct rb_augment_callbacks *augment) +{ + struct rb_node *child = node->rb_right, *tmp = node->rb_left; + struct rb_node *parent, *rebalance; + unsigned long pc; + + if (!tmp) { + /* + * Case 1: node to erase has no more than 1 child (easy!) + * + * Note that if there is one child it must be red due to 5) + * and node must be black due to 4). We adjust colors locally + * so as to bypass __rb_erase_color() later on. + */ + pc = node->__rb_parent_color; + parent = __rb_parent(pc); + __rb_change_child(node, child, parent, root); + if (child) { + child->__rb_parent_color = pc; + rebalance = NULL; + } else + rebalance = __rb_is_black(pc) ? parent : NULL; + tmp = parent; + } else if (!child) { + /* Still case 1, but this time the child is node->rb_left */ + tmp->__rb_parent_color = pc = node->__rb_parent_color; + parent = __rb_parent(pc); + __rb_change_child(node, tmp, parent, root); + rebalance = NULL; + tmp = parent; + } else { + struct rb_node *successor = child, *child2; + tmp = child->rb_left; + if (!tmp) { + /* + * Case 2: node's successor is its right child + * + * (n) (s) + * / \ / \ + * (x) (s) -> (x) (c) + * \ + * (c) + */ + parent = successor; + child2 = successor->rb_right; + augment->copy(node, successor); + } else { + /* + * Case 3: node's successor is leftmost under + * node's right child subtree + * + * (n) (s) + * / \ / \ + * (x) (y) -> (x) (y) + * / / + * (p) (p) + * / / + * (s) (c) + * \ + * (c) + */ + do { + parent = successor; + successor = tmp; + tmp = tmp->rb_left; + } while (tmp); + parent->rb_left = child2 = successor->rb_right; + successor->rb_right = child; + rb_set_parent(child, successor); + augment->copy(node, successor); + augment->propagate(parent, successor); + } + + successor->rb_left = tmp = node->rb_left; + rb_set_parent(tmp, successor); + + pc = node->__rb_parent_color; + tmp = __rb_parent(pc); + __rb_change_child(node, successor, tmp, root); + if (child2) { + successor->__rb_parent_color = pc; + rb_set_parent_color(child2, parent, RB_BLACK); + rebalance = NULL; + } else { + unsigned long pc2 = successor->__rb_parent_color; + successor->__rb_parent_color = pc; + rebalance = __rb_is_black(pc2) ? parent : NULL; + } + tmp = successor; + } + + augment->propagate(tmp, NULL); + return rebalance; +} + +static __always_inline void +rb_erase_augmented(struct rb_node *node, struct rb_root *root, + const struct rb_augment_callbacks *augment) +{ + struct rb_node *rebalance = __rb_erase_augmented(node, root, augment); + if (rebalance) + __rb_erase_color(rebalance, root, augment->rotate); +} + +#endif /* _LINUX_RBTREE_AUGMENTED_H */ diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h new file mode 100644 index 0000000000..9214b67b11 --- /dev/null +++ b/include/linux/serial_reg.h @@ -0,0 +1,388 @@ +/* + * include/linux/serial_reg.h + * + * Copyright (C) 1992, 1994 by Theodore Ts'o. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * These are the UART port assignments, expressed as offsets from the base + * register. These assignments should hold for any serial port based on + * a 8250, 16450, or 16550(A). + */ + +#ifndef _LINUX_SERIAL_REG_H +#define _LINUX_SERIAL_REG_H + +/* + * DLAB=0 + */ +#define UART_RX 0 /* In: Receive buffer */ +#define UART_TX 0 /* Out: Transmit buffer */ + +#define UART_IER 1 /* Out: Interrupt Enable Register */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ +/* + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 + */ +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ + +#define UART_IIR 2 /* In: Interrupt ID Register */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +#define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ + +#define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ +#define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ +#define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ + +#define UART_FCR 2 /* Out: FIFO Control Register */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +/* + * Note: The FIFO trigger levels are chip specific: + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 + * PC16550D: 1 4 8 14 xx xx xx xx + * TI16C550A: 1 4 8 14 xx xx xx xx + * TI16C550C: 1 4 8 14 xx xx xx xx + * ST16C550: 1 4 8 14 xx xx xx xx + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 + * NS16C552: 1 4 8 14 xx xx xx xx + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 + * TI16C752: 8 16 56 60 8 16 32 56 + * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA + */ +#define UART_FCR_R_TRIG_00 0x00 +#define UART_FCR_R_TRIG_01 0x40 +#define UART_FCR_R_TRIG_10 0x80 +#define UART_FCR_R_TRIG_11 0xc0 +#define UART_FCR_T_TRIG_00 0x00 +#define UART_FCR_T_TRIG_01 0x10 +#define UART_FCR_T_TRIG_10 0x20 +#define UART_FCR_T_TRIG_11 0x30 + +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +/* 16650 definitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ + +#define UART_LCR 3 /* Out: Line Control Register */ +/* + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * Access to some registers depends on register access / configuration + * mode. + */ +#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ +#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ + +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_LSR_FIFOE 0x80 /* Fifo error */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ +#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ + +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +#define UART_SCR 7 /* I/O: Scratch Register */ + +/* + * DLAB=1 + */ +#define UART_DLL 0 /* Out: Divisor Latch Low */ +#define UART_DLM 1 /* Out: Divisor Latch High */ + +/* + * LCR=0xBF (or DLAB=1 for 16C660) + */ +#define UART_EFR 2 /* I/O: Extended Features Register */ +#define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ECB 0x10 /* Enhanced control bit */ +/* + * the low four bits control software flow control + */ + +/* + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 + */ +#define UART_XON1 4 /* I/O: Xon character 1 */ +#define UART_XON2 5 /* I/O: Xon character 2 */ +#define UART_XOFF1 6 /* I/O: Xoff character 1 */ +#define UART_XOFF2 7 /* I/O: Xoff character 2 */ + +/* + * EFR[4]=1 MCR[6]=1, TI16C752 + */ +#define UART_TI752_TCR 6 /* I/O: transmission control register */ +#define UART_TI752_TLR 7 /* I/O: trigger level register */ + +/* + * LCR=0xBF, XR16C85x + */ +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx + * In: Fifo count + * Out: Fifo custom trigger levels */ +/* + * These are the definitions for the Programmable Trigger Register + */ +#define UART_TRG_1 0x01 +#define UART_TRG_4 0x04 +#define UART_TRG_8 0x08 +#define UART_TRG_16 0x10 +#define UART_TRG_32 0x20 +#define UART_TRG_64 0x40 +#define UART_TRG_96 0x60 +#define UART_TRG_120 0x78 +#define UART_TRG_128 0x80 + +#define UART_FCTR 1 /* Feature Control Register */ +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ +#define UART_FCTR_RTS_4DELAY 0x01 +#define UART_FCTR_RTS_6DELAY 0x02 +#define UART_FCTR_RTS_8DELAY 0x03 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ + +/* + * LCR=0xBF, FCTR[6]=1 + */ +#define UART_EMSR 7 /* Extended Mode Select Register */ +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ + +/* + * The Intel XScale on-chip UARTs define these bits + */ +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */ +#define UART_IER_UUE 0x40 /* UART Unit Enable */ +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */ +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ + +#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ + +#define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */ +#define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */ +#define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ +#define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ + +/* + * Intel MID on-chip HSU (High Speed UART) defined bits + */ +#define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */ +#define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */ +#define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */ +#define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */ + +#define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */ +#define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */ +#define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */ +#define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */ + +#define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */ +#define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */ + +#define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */ +#define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */ + +/* + * These register definitions are for the 16C950 + */ +#define UART_ASR 0x01 /* Additional Status Register */ +#define UART_RFL 0x03 /* Receiver FIFO level */ +#define UART_TFL 0x04 /* Transmitter FIFO level */ +#define UART_ICR 0x05 /* Index Control Register */ + +/* The 16950 ICR registers */ +#define UART_ACR 0x00 /* Additional Control Register */ +#define UART_CPR 0x01 /* Clock Prescalar Register */ +#define UART_TCR 0x02 /* Times Clock Register */ +#define UART_CKS 0x03 /* Clock Select Register */ +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ +#define UART_FCL 0x06 /* Flow Control Level Lower */ +#define UART_FCH 0x07 /* Flow Control Level Higher */ +#define UART_ID1 0x08 /* ID #1 */ +#define UART_ID2 0x09 /* ID #2 */ +#define UART_ID3 0x0A /* ID #3 */ +#define UART_REV 0x0B /* Revision */ +#define UART_CSR 0x0C /* Channel Software Reset */ +#define UART_NMR 0x0D /* Nine-bit Mode Register */ +#define UART_CTR 0xFF + +/* + * The 16C950 Additional Control Register + */ +#define UART_ACR_RXDIS 0x01 /* Receiver disable */ +#define UART_ACR_TXDIS 0x02 /* Transmitter disable */ +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */ +#define UART_ACR_ASREN 0x80 /* Additional status enable */ + + + +/* + * These definitions are for the RSA-DV II/S card, from + * + * Kiyokazu SUTO + */ + +#define UART_RSA_BASE (-8) + +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ + +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ + +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ + +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ + +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ + +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ + +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ + +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ + +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ + +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ + +/* + * The RSA DSV/II board has two fixed clock frequencies. One is the + * standard rate, and the other is 8 times faster. + */ +#define SERIAL_RSA_BAUD_BASE (921600) +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) + +/* + * Extra serial register definitions for the internal UARTs + * in TI OMAP processors. + */ +#define UART_OMAP_MDR1 0x08 /* Mode definition register */ +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ +#define UART_OMAP_SCR 0x10 /* Supplementary control register */ +#define UART_OMAP_SSR 0x11 /* Supplementary status register */ +#define UART_OMAP_EBLR 0x12 /* BOF length register */ +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ +#define UART_OMAP_MVER 0x14 /* Module version register */ +#define UART_OMAP_SYSC 0x15 /* System configuration register */ +#define UART_OMAP_SYSS 0x16 /* System status register */ +#define UART_OMAP_WER 0x17 /* Wake-up enable register */ + +/* + * These are the definitions for the MDR1 register + */ +#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ +#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ +#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ +#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ +#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ +#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ +#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ +#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ + +/* + * These are definitions for the Exar XR17V35X and XR17(C|D)15X + */ +#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ +#define UART_EXAR_SLEEP 0x8b /* Sleep mode */ +#define UART_EXAR_DVID 0x8d /* Device identification */ + +#define UART_EXAR_FCTR 0x08 /* Feature Control Register */ +#define UART_FCTR_EXAR_IRDA 0x08 /* IrDa data encode select */ +#define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */ +#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ +#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ +#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ +#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ + +#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ +#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ + +#endif /* _LINUX_SERIAL_REG_H */ + diff --git a/include/linux/sizes.h b/include/linux/sizes.h new file mode 100644 index 0000000000..ce3e8150c1 --- /dev/null +++ b/include/linux/sizes.h @@ -0,0 +1,47 @@ +/* + * include/linux/sizes.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __LINUX_SIZES_H__ +#define __LINUX_SIZES_H__ + +#define SZ_1 0x00000001 +#define SZ_2 0x00000002 +#define SZ_4 0x00000004 +#define SZ_8 0x00000008 +#define SZ_16 0x00000010 +#define SZ_32 0x00000020 +#define SZ_64 0x00000040 +#define SZ_128 0x00000080 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + +#define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __LINUX_SIZES_H__ */ diff --git a/include/linux/string.h b/include/linux/string.h index 8e44855712..c7047ba0bc 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -20,12 +20,19 @@ extern __kernel_size_t strspn(const char *,const char *); */ #include +#ifndef __HAVE_ARCH_BCOPY +char *bcopy(const char *src, char *dest, int count); +#endif + #ifndef __HAVE_ARCH_STRCPY extern char * strcpy(char *,const char *); #endif #ifndef __HAVE_ARCH_STRNCPY extern char * strncpy(char *,const char *, __kernel_size_t); #endif +#ifndef __HAVE_ARCH_STRLCPY +size_t strlcpy(char *, const char *, size_t); +#endif #ifndef __HAVE_ARCH_STRCAT extern char * strcat(char *, const char *); #endif @@ -89,6 +96,9 @@ extern void * memchr(const void *,int,__kernel_size_t); void *memchr_inv(const void *, int, size_t); #endif +unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); +unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); + #ifdef __cplusplus } #endif diff --git a/include/linux/types.h b/include/linux/types.h index f07ba41b72..c9a8d9a8c2 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -1,10 +1,6 @@ #ifndef _LINUX_TYPES_H #define _LINUX_TYPES_H -#ifdef __KERNEL__ -#include -#endif - #include #include #include @@ -108,7 +104,8 @@ typedef __u8 uint8_t; typedef __u16 uint16_t; typedef __u32 uint32_t; -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) && \ + (!defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__)) typedef __u64 uint64_t; typedef __u64 u_int64_t; typedef __s64 int64_t; @@ -116,6 +113,12 @@ typedef __s64 int64_t; #endif /* __KERNEL_STRICT_NAMES */ +#if defined(CONFIG_USE_STDINT) && defined(__INT64_TYPE__) +typedef __UINT64_TYPE__ uint64_t; +typedef __UINT64_TYPE__ u_int64_t; +typedef __INT64_TYPE__ int64_t; +#endif + /* * Below are truly Linux-specific types that should never collide with * any application/library that wants linux/types.h. diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h new file mode 100644 index 0000000000..be29ef0c5c --- /dev/null +++ b/include/linux/usb/atmel_usba_udc.h @@ -0,0 +1,26 @@ +/* + * Platform data definitions for Atmel USBA gadget driver + * [Original from Linux kernel: include/linux/usb/atmel_usba_udc.h] + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __LINUX_USB_USBA_H__ +#define __LINUX_USB_USBA_H__ + +struct usba_ep_data { + char *name; + int index; + int fifo_size; + int nr_banks; + int can_dma; + int can_isoc; +}; + +struct usba_platform_data { + int num_ep; + struct usba_ep_data *ep; +}; + +extern int usba_udc_probe(struct usba_platform_data *pdata); + +#endif /* __LINUX_USB_USBA_H */ diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h new file mode 100644 index 0000000000..7edc760c7b --- /dev/null +++ b/include/linux/usb/dwc3.h @@ -0,0 +1,194 @@ +/* include/linux/usb/dwc3.h + * + * Copyright (c) 2012 Samsung Electronics Co. Ltd + * + * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DWC3_H_ +#define __DWC3_H_ + +/* Global constants */ +#define DWC3_ENDPOINTS_NUM 32 + +#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE +#define DWC3_EVENT_TYPE_MASK 0xfe + +#define DWC3_EVENT_TYPE_DEV 0 +#define DWC3_EVENT_TYPE_CARKIT 3 +#define DWC3_EVENT_TYPE_I2C 4 + +#define DWC3_DEVICE_EVENT_DISCONNECT 0 +#define DWC3_DEVICE_EVENT_RESET 1 +#define DWC3_DEVICE_EVENT_CONNECT_DONE 2 +#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 +#define DWC3_DEVICE_EVENT_WAKEUP 4 +#define DWC3_DEVICE_EVENT_EOPF 6 +#define DWC3_DEVICE_EVENT_SOF 7 +#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 +#define DWC3_DEVICE_EVENT_CMD_CMPL 10 +#define DWC3_DEVICE_EVENT_OVERFLOW 11 + +#define DWC3_GEVNTCOUNT_MASK 0xfffc +#define DWC3_GSNPSID_MASK 0xffff0000 +#define DWC3_GSNPSID_SHIFT 16 +#define DWC3_GSNPSREV_MASK 0xffff + +#define DWC3_REVISION_MASK 0xffff + +#define DWC3_REG_OFFSET 0xC100 + +struct g_event_buffer { + u32 g_evntadrlo; + u32 g_evntadrhi; + u32 g_evntsiz; + u32 g_evntcount; +}; + +struct d_physical_endpoint { + u32 d_depcmdpar2; + u32 d_depcmdpar1; + u32 d_depcmdpar0; + u32 d_depcmd; +}; + +struct dwc3 { /* offset: 0xC100 */ + u32 g_sbuscfg0; + u32 g_sbuscfg1; + u32 g_txthrcfg; + u32 g_rxthrcfg; + u32 g_ctl; + + u32 reserved1; + + u32 g_sts; + + u32 reserved2; + + u32 g_snpsid; + u32 g_gpio; + u32 g_uid; + u32 g_uctl; + u64 g_buserraddr; + u64 g_prtbimap; + + u32 g_hwparams0; + u32 g_hwparams1; + u32 g_hwparams2; + u32 g_hwparams3; + u32 g_hwparams4; + u32 g_hwparams5; + u32 g_hwparams6; + u32 g_hwparams7; + + u32 g_dbgfifospace; + u32 g_dbgltssm; + u32 g_dbglnmcc; + u32 g_dbgbmu; + u32 g_dbglspmux; + u32 g_dbglsp; + u32 g_dbgepinfo0; + u32 g_dbgepinfo1; + + u64 g_prtbimap_hs; + u64 g_prtbimap_fs; + + u32 reserved3[28]; + + u32 g_usb2phycfg[16]; + u32 g_usb2i2cctl[16]; + u32 g_usb2phyacc[16]; + u32 g_usb3pipectl[16]; + + u32 g_txfifosiz[32]; + u32 g_rxfifosiz[32]; + + struct g_event_buffer g_evnt_buf[32]; + + u32 g_hwparams8; + + u32 reserved4[63]; + + u32 d_cfg; + u32 d_ctl; + u32 d_evten; + u32 d_sts; + u32 d_gcmdpar; + u32 d_gcmd; + + u32 reserved5[2]; + + u32 d_alepena; + + u32 reserved6[55]; + + struct d_physical_endpoint d_phy_ep_cmd[32]; + + u32 reserved7[128]; + + u32 o_cfg; + u32 o_ctl; + u32 o_evt; + u32 o_evten; + u32 o_sts; + + u32 reserved8[3]; + + u32 adp_cfg; + u32 adp_ctl; + u32 adp_evt; + u32 adp_evten; + + u32 bc_cfg; + + u32 reserved9; + + u32 bc_evt; + u32 bc_evten; +}; + +/* Global Configuration Register */ +#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) +#define DWC3_GCTL_U2RSTECN (1 << 16) +#define DWC3_GCTL_RAMCLKSEL(x) \ + (((x) & DWC3_GCTL_CLK_MASK) << 6) +#define DWC3_GCTL_CLK_BUS (0) +#define DWC3_GCTL_CLK_PIPE (1) +#define DWC3_GCTL_CLK_PIPEHALF (2) +#define DWC3_GCTL_CLK_MASK (3) +#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_HOST 1 +#define DWC3_GCTL_PRTCAP_DEVICE 2 +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_CORESOFTRESET (1 << 11) +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +/* Global HWPARAMS1 Register */ +#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) +#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) + +/* Global USB3 PIPE Control Register */ +#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) +#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) + +/* Global TX Fifo Size Register */ +#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) +#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) + +/* Device Control Register */ +#define DWC3_DCTL_RUN_STOP (1 << 31) +#define DWC3_DCTL_CSFTRST (1 << 30) +#define DWC3_DCTL_LSFTRST (1 << 29) + +#endif /* __DWC3_H_ */ diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 220d068600..9bccd451af 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -18,6 +18,8 @@ #ifndef __LINUX_USB_GADGET_H #define __LINUX_USB_GADGET_H +#include +#include #include struct usb_ep; @@ -409,11 +411,6 @@ struct usb_gadget_ops { unsigned code, unsigned long param); }; -struct device { - void *driver_data; /* data private to the driver */ - void *device_data; /* data private to the device */ -}; - /** * struct usb_gadget - represents a usb slave device * @ops: Function pointers used to access hardware-specific operations. diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h index 9f65ef96ac..075d222195 100644 --- a/include/linux/usb/musb.h +++ b/include/linux/usb/musb.h @@ -14,6 +14,8 @@ #define __deprecated #endif +#include + /* The USB role is defined by the connector used on the board, so long as * standards are being followed. (Developer boards sometimes won't.) */ diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h new file mode 100644 index 0000000000..cb166e6a6c --- /dev/null +++ b/include/linux/usb/xhci-omap.h @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Inc, + * + * Author: Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_XHCI_OMAP_H_ +#define _ASM_ARCH_XHCI_OMAP_H_ + +#ifdef CONFIG_DRA7XX +#define OMAP_XHCI_BASE 0x488d0000 +#define OMAP_OCP1_SCP_BASE 0x4A081000 +#define OMAP_OTG_WRAPPER_BASE 0x488c0000 +#elif defined CONFIG_AM57XX +#define OMAP_XHCI_BASE 0x48890000 +#define OMAP_OCP1_SCP_BASE 0x4A084c00 +#define OMAP_OTG_WRAPPER_BASE 0x48880000 +#elif defined CONFIG_AM43XX +#define OMAP_XHCI_BASE 0x483d0000 +#define OMAP_OCP1_SCP_BASE 0x483E8000 +#define OMAP_OTG_WRAPPER_BASE 0x483dc100 +#else +/* Default to the OMAP5 XHCI defines */ +#define OMAP_XHCI_BASE 0x4a030000 +#define OMAP_OCP1_SCP_BASE 0x4a084c00 +#define OMAP_OTG_WRAPPER_BASE 0x4A020000 +#endif + +/* Phy register MACRO definitions */ +#define PLL_REGM_MASK 0x001FFE00 +#define PLL_REGM_SHIFT 0x9 +#define PLL_REGM_F_MASK 0x0003FFFF +#define PLL_REGM_F_SHIFT 0x0 +#define PLL_REGN_MASK 0x000001FE +#define PLL_REGN_SHIFT 0x1 +#define PLL_SELFREQDCO_MASK 0x0000000E +#define PLL_SELFREQDCO_SHIFT 0x1 +#define PLL_SD_MASK 0x0003FC00 +#define PLL_SD_SHIFT 0x9 +#define SET_PLL_GO 0x1 +#define PLL_TICOPWDN 0x10000 +#define PLL_LOCK 0x2 +#define PLL_IDLE 0x1 + +#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 +#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC +#define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) +#define USB3_PHY_RX_POWERON (1 << 14) +#define USB3_PHY_TX_POWERON (1 << 15) +#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) +#define USB3_PWRCTL_CLK_CMD_SHIFT 14 +#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 + +/* USBOTGSS_WRAPPER definitions */ +#define USBOTGSS_WRAPRESET (1 << 17) +#define USBOTGSS_DMADISABLE (1 << 16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) +#define USBOTGSS_STANDBYMODE_SMRT (1 << 5) +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) +#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) +#define USBOTGSS_IDLEMODE_SMRT (1 << 3) +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) + +/* USBOTGSS_IRQENABLE_SET_0 bit */ +#define USBOTGSS_COREIRQ_EN (1 << 0) + +/* USBOTGSS_IRQENABLE_SET_1 bits */ +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) + +/* + * USBOTGSS_WRAPPER registers + */ +struct omap_dwc_wrapper { + u32 revision; + + u32 reserve_1[3]; + + u32 sysconfig; /* offset of 0x10 */ + + u32 reserve_2[3]; + u16 reserve_3; + + u32 irqstatus_raw_0; /* offset of 0x24 */ + u32 irqstatus_0; + u32 irqenable_set_0; + u32 irqenable_clr_0; + + u32 irqstatus_raw_1; /* offset of 0x34 */ + u32 irqstatus_1; + u32 irqenable_set_1; + u32 irqenable_clr_1; + + u32 reserve_4[15]; + + u32 utmi_otg_ctrl; /* offset of 0x80 */ + u32 utmi_otg_status; + + u32 reserve_5[30]; + + u32 mram_offset; /* offset of 0x100 */ + u32 fladj; + u32 dbg_config; + u32 dbg_data; + u32 dev_ebc_en; +}; + +/* XHCI PHY register structure */ +struct omap_usb3_phy { + u32 reserve1; + u32 pll_status; + u32 pll_go; + u32 pll_config_1; + u32 pll_config_2; + u32 pll_config_3; + u32 pll_ssc_config_1; + u32 pll_ssc_config_2; + u32 pll_config_4; +}; + +struct omap_xhci { + struct omap_dwc_wrapper *otg_wrapper; + struct omap_usb3_phy *usb3_phy; + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +/* USB PHY functions */ +void omap_enable_phy(struct omap_xhci *omap); +void omap_reset_usb_phy(struct dwc3 *dwc3_reg); +void usb_phy_power(int on); + +#endif /* _ASM_ARCH_XHCI_OMAP_H_ */ diff --git a/include/lynxkdi.h b/include/lynxkdi.h index df214a1798..8e45a81f92 100644 --- a/include/lynxkdi.h +++ b/include/lynxkdi.h @@ -2,7 +2,7 @@ * (C) Copyright 2003 * Orbacom Systems, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __LYNXKDI_H__ diff --git a/include/malloc.h b/include/malloc.h index c33f3b494e..5df634873f 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -872,33 +872,46 @@ extern Void_t* sbrk(); #else -#ifdef USE_DL_PREFIX -#define cALLOc dlcalloc -#define fREe dlfree -#define mALLOc dlmalloc -#define mEMALIGn dlmemalign -#define rEALLOc dlrealloc -#define vALLOc dlvalloc -#define pvALLOc dlpvalloc -#define mALLINFo dlmallinfo -#define mALLOPt dlmallopt -#else /* USE_DL_PREFIX */ -#define cALLOc calloc -#define fREe free -#define mALLOc malloc -#define mEMALIGn memalign -#define rEALLOc realloc -#define vALLOc valloc -#define pvALLOc pvalloc -#define mALLINFo mallinfo -#define mALLOPt mallopt -#endif /* USE_DL_PREFIX */ +#ifdef CONFIG_SYS_MALLOC_SIMPLE +#define malloc malloc_simple +#define realloc realloc_simple +#define memalign memalign_simple +static inline void free(void *ptr) {} +void *calloc(size_t nmemb, size_t size); +void *memalign_simple(size_t alignment, size_t bytes); +void *realloc_simple(void *ptr, size_t size); +#else + +# ifdef USE_DL_PREFIX +# define cALLOc dlcalloc +# define fREe dlfree +# define mALLOc dlmalloc +# define mEMALIGn dlmemalign +# define rEALLOc dlrealloc +# define vALLOc dlvalloc +# define pvALLOc dlpvalloc +# define mALLINFo dlmallinfo +# define mALLOPt dlmallopt +# else /* USE_DL_PREFIX */ +# define cALLOc calloc +# define fREe free +# define mALLOc malloc +# define mEMALIGn memalign +# define rEALLOc realloc +# define vALLOc valloc +# define pvALLOc pvalloc +# define mALLINFo mallinfo +# define mALLOPt mallopt +# endif /* USE_DL_PREFIX */ #endif /* Public routines */ -#if __STD_C +/* Simple versions which can be used when space is tight */ +void *malloc_simple(size_t size); + +# if __STD_C Void_t* mALLOc(size_t); void fREe(Void_t*); @@ -913,7 +926,7 @@ size_t malloc_usable_size(Void_t*); void malloc_stats(void); int mALLOPt(int, int); struct mallinfo mALLINFo(void); -#else +# else Void_t* mALLOc(); void fREe(); Void_t* rEALLOc(); @@ -927,6 +940,7 @@ size_t malloc_usable_size(); void malloc_stats(); int mALLOPt(); struct mallinfo mALLINFo(); +# endif #endif /* diff --git a/include/micrel.h b/include/micrel.h index e1c62d83cb..04c9ecf3bf 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -15,6 +15,11 @@ #define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000 #define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000 +#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4 +#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5 +#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6 +#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8 + struct phy_device; int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val); int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum); diff --git a/include/miiphy.h b/include/miiphy.h index ca5040ed8d..088797e4c6 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -1,27 +1,8 @@ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of the -| GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -| -| Additions (C) Copyright 2009 Industrie Dial Face S.p.A. -+----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + * + * Additions (C) Copyright 2009 Industrie Dial Face S.p.A. + */ /*----------------------------------------------------------------------------+ | | File Name: miiphy.h diff --git a/include/mipi_display.h b/include/mipi_display.h new file mode 100644 index 0000000000..ddcc8ca731 --- /dev/null +++ b/include/mipi_display.h @@ -0,0 +1,130 @@ +/* + * Defines for Mobile Industry Processor Interface (MIPI(R)) + * Display Working Group standards: DSI, DCS, DBI, DPI + * + * Copyright (C) 2010 Guennadi Liakhovetski + * Copyright (C) 2006 Nokia Corporation + * Author: Imre Deak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef MIPI_DISPLAY_H +#define MIPI_DISPLAY_H + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +/* MIPI DCS pixel formats */ +#define MIPI_DCS_PIXEL_FMT_24BIT 7 +#define MIPI_DCS_PIXEL_FMT_18BIT 6 +#define MIPI_DCS_PIXEL_FMT_16BIT 5 +#define MIPI_DCS_PIXEL_FMT_12BIT 3 +#define MIPI_DCS_PIXEL_FMT_8BIT 2 +#define MIPI_DCS_PIXEL_FMT_3BIT 1 + +#endif diff --git a/include/mmc.h b/include/mmc.h index 228d77139d..c0bcfb9076 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -12,6 +12,7 @@ #include #include +#include #define SD_VERSION_SD 0x20000 #define SD_VERSION_3 (SD_VERSION_SD | 0x300) @@ -30,16 +31,15 @@ #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) +#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500) -#define MMC_MODE_HS 0x001 -#define MMC_MODE_HS_52MHz 0x010 -#define MMC_MODE_4BIT 0x100 -#define MMC_MODE_8BIT 0x200 -#define MMC_MODE_SPI 0x400 -#define MMC_MODE_HC 0x800 - -#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) -#define MMC_MODE_WIDTH_BITS_SHIFT 8 +#define MMC_MODE_HS (1 << 0) +#define MMC_MODE_HS_52MHz (1 << 1) +#define MMC_MODE_4BIT (1 << 2) +#define MMC_MODE_8BIT (1 << 3) +#define MMC_MODE_SPI (1 << 4) +#define MMC_MODE_HC (1 << 5) +#define MMC_MODE_DDR_52MHz (1 << 6) #define SD_DATA_4BIT 0x00040000 @@ -53,6 +53,7 @@ #define COMM_ERR -18 /* Communications Error */ #define TIMEOUT -19 #define IN_PROGRESS -20 /* operation is in progress */ +#define SWITCH_ERR -21 /* Card reports failure to switch mode */ #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 @@ -69,6 +70,7 @@ #define MMC_CMD_SET_BLOCKLEN 16 #define MMC_CMD_READ_SINGLE_BLOCK 17 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_SET_BLOCK_COUNT 23 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 #define MMC_CMD_ERASE_GROUP_START 35 @@ -97,9 +99,6 @@ #define SD_HIGHSPEED_BUSY 0x00020000 #define SD_HIGHSPEED_SUPPORTED 0x00020000 -#define MMC_HS_TIMING 0x00000100 -#define MMC_HS_52MHZ 0x2 - #define OCR_BUSY 0x80000000 #define OCR_HCS 0x40000000 #define OCR_VOLTAGE_MASK 0x007FFF80 @@ -108,6 +107,7 @@ #define SECURE_ERASE 0x80000000 #define MMC_STATUS_MASK (~0x0206BF7F) +#define MMC_STATUS_SWITCH_ERROR (1 << 7) #define MMC_STATUS_RDY_FOR_DATA (1 << 8) #define MMC_STATUS_CURR_STATE (0xf << 9) #define MMC_STATUS_ERROR (1 << 19) @@ -147,8 +147,16 @@ /* * EXT_CSD fields */ +#define EXT_CSD_ENH_START_ADDR 136 /* R/W */ +#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ +#define EXT_CSD_PARTITION_SETTING 155 /* R/W */ +#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ +#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ +#define EXT_CSD_WR_REL_PARAM 166 /* R */ +#define EXT_CSD_WR_REL_SET 167 /* R/W */ #define EXT_CSD_RPMB_MULT 168 /* RO */ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ #define EXT_CSD_BOOT_BUS_WIDTH 177 @@ -172,10 +180,16 @@ #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ +#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) @@ -186,6 +200,19 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) +#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) +#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) + +#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) + +#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ +#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ + +#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ + +#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ +#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -210,6 +237,8 @@ #define MMCPART_NOAVAILABLE (0xff) #define PART_ACCESS_MASK (0x7) #define PART_SUPPORT (0x1) +#define ENHNCD_SUPPORT (0x2) +#define PART_ENH_ATTRIB (0x1f) /* Maximum block size for MMC */ #define MMC_MAX_BLOCK_LEN 512 @@ -218,6 +247,7 @@ * boot partitions (2), general purpose partitions (4) in MMC v4.4. */ #define MMC_NUM_BOOT_PARTITION 2 +#define MMC_PART_RPMB 3 /* RPMB partition number */ struct mmc_cid { unsigned long psn; @@ -245,51 +275,96 @@ struct mmc_data { uint blocksize; }; +/* forward decl. */ +struct mmc; + +struct mmc_ops { + int (*send_cmd)(struct mmc *mmc, + struct mmc_cmd *cmd, struct mmc_data *data); + void (*set_ios)(struct mmc *mmc); + int (*init)(struct mmc *mmc); + int (*getcd)(struct mmc *mmc); + int (*getwp)(struct mmc *mmc); +}; + +struct mmc_config { + const char *name; + const struct mmc_ops *ops; + uint host_caps; + uint voltages; + uint f_min; + uint f_max; + uint b_max; + unsigned char part_type; +}; + +/* TODO struct mmc should be in mmc_private but it's hard to fix right now */ struct mmc { struct list_head link; - char name[32]; - void *priv; - uint voltages; + const struct mmc_config *cfg; /* provided configuration */ uint version; + void *priv; uint has_init; - uint f_min; - uint f_max; int high_capacity; uint bus_width; uint clock; uint card_caps; - uint host_caps; uint ocr; + uint dsr; + uint dsr_imp; uint scr[2]; uint csd[4]; uint cid[4]; ushort rca; + u8 part_support; + u8 part_attr; + u8 wr_rel_set; char part_config; char part_num; uint tran_speed; uint read_bl_len; uint write_bl_len; - uint erase_grp_size; + uint erase_grp_size; /* in 512-byte sectors */ + uint hc_wp_grp_size; /* in 512-byte sectors */ u64 capacity; u64 capacity_user; u64 capacity_boot; u64 capacity_rpmb; u64 capacity_gp[4]; + u64 enh_user_start; + u64 enh_user_size; block_dev_desc_t block_dev; - int (*send_cmd)(struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data); - void (*set_ios)(struct mmc *mmc); - int (*init)(struct mmc *mmc); - int (*getcd)(struct mmc *mmc); - int (*getwp)(struct mmc *mmc); - uint b_max; char op_cond_pending; /* 1 if we are waiting on an op_cond command */ char init_in_progress; /* 1 if we have done mmc_start_init() */ char preinit; /* start init as early as possible */ uint op_cond_response; /* the response byte from the last op_cond */ + int ddr_mode; +}; + +struct mmc_hwpart_conf { + struct { + uint enh_start; /* in 512-byte sectors */ + uint enh_size; /* in 512-byte sectors, if 0 no enh area */ + unsigned wr_rel_change : 1; + unsigned wr_rel_set : 1; + } user; + struct { + uint size; /* in 512-byte sectors */ + unsigned enhanced : 1; + unsigned wr_rel_change : 1; + unsigned wr_rel_set : 1; + } gp_part[4]; +}; + +enum mmc_hwpart_conf_mode { + MMC_HWPART_CONF_CHECK, + MMC_HWPART_CONF_SET, + MMC_HWPART_CONF_COMPLETE, }; int mmc_register(struct mmc *mmc); +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); +void mmc_destroy(struct mmc *mmc); int mmc_initialize(bd_t *bis); int mmc_init(struct mmc *mmc); int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); @@ -298,17 +373,31 @@ struct mmc *find_mmc_device(int dev_num); int mmc_set_dev(int dev_num); void print_mmc_devices(char separator); int get_mmc_num(void); -int board_mmc_getcd(struct mmc *mmc); +int get_mmc_dev_count(void); int mmc_switch_part(int dev_num, unsigned int part_num); +int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, + enum mmc_hwpart_conf_mode mode); int mmc_getcd(struct mmc *mmc); +int board_mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); -void spl_mmc_load(void) __noreturn; +int board_mmc_getwp(struct mmc *mmc); +int mmc_set_dsr(struct mmc *mmc, u16 val); /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); -/* Function to send commands to open/close the specified boot partition */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); - +/* Function to modify the PARTITION_CONFIG field of EXT_CSD */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); +/* Function to modify the RST_n_FUNCTION field of EXT_CSD */ +int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); +/* Functions to read / write the RPMB partition */ +int mmc_rpmb_set_key(struct mmc *mmc, void *key); +int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); +int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key); +int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key); /** * Start device initialization and return immediately; it does not block on * polling OCR (operation condition register) status. Then you should call @@ -335,10 +424,24 @@ int mmc_start_init(struct mmc *mmc); void mmc_set_preinit(struct mmc *mmc, int preinit); #ifdef CONFIG_GENERIC_MMC -#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI) +#ifdef CONFIG_MMC_SPI +#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) +#else +#define mmc_host_is_spi(mmc) 0 +#endif struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); #else int mmc_legacy_init(int verbose); #endif +void board_mmc_power_init(void); +int board_mmc_init(bd_t *bis); +int cpu_mmc_init(bd_t *bis); +int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); + +/* Set block count limit because of 16 bit register limit on some hardware*/ +#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 +#endif + #endif /* _MMC_H_ */ diff --git a/include/mpc824x.h b/include/mpc824x.h deleted file mode 100644 index 975a5dd2a7..0000000000 --- a/include/mpc824x.h +++ /dev/null @@ -1,523 +0,0 @@ -/* - * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000. - * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MPC824X_H__ -#define __MPC824X_H__ - -#include - -/* CPU Types */ -#define CPU_TYPE_601 0x01 /* PPC 601 CPU */ -#define CPU_TYPE_602 0x02 /* PPC 602 CPU */ -#define CPU_TYPE_603 0x03 /* PPC 603 CPU */ -#define CPU_TYPE_603E 0x06 /* PPC 603e CPU */ -#define CPU_TYPE_603P 0x07 /* PPC 603p CPU */ -#define CPU_TYPE_604 0x04 /* PPC 604 CPU */ -#define CPU_TYPE_604E 0x09 /* PPC 604e CPU */ -#define CPU_TYPE_604R 0x0a /* PPC 604r CPU */ -#define CPU_TYPE_750 0x08 /* PPC 750 CPU */ -#define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */ -#define CPU_TYPE_8245 0x8081 /* PPC 8245/8241 CPU */ -#define _CACHE_ALIGN_SIZE 32 /* cache line size */ - -/* spr976 - DMISS data tlb miss address register - * spr977 - DCMP data tlb miss compare register - * spr978 - HASH1 PTEG1 address register - * spr980 - HASH2 PTEG2 address register - * IMISS - instruction tlb miss address register - * ICMP - instruction TLB mis compare register - * RPA - real page address register - * HID0 - hardware implemntation register - * HID2 - instruction address breakpoint register - */ - -/* Kahlua/MPC8240 defines */ -#define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */ -#define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */ -#define KAHLUA2_ID 0x00061057 /* 8245 is aka Kahlua-2 */ -#define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */ -#define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */ -#define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */ -#define CHRP_ISA_MEM_PHYS 0xfd000000 -#define CHRP_ISA_MEM_BUS 0x00000000 -#define CHRP_ISA_MEM_SIZE 0x01000000 -#define CHRP_ISA_IO_PHYS 0xfe000000 -#define CHRP_ISA_IO_BUS 0x00000000 -#define CHRP_ISA_IO_SIZE 0x00800000 -#define CHRP_PCI_IO_PHYS 0xfe800000 -#define CHRP_PCI_IO_BUS 0x00800000 -#define CHRP_PCI_IO_SIZE 0x00400000 -#define CHRP_PCI_MEM_PHYS 0x80000000 -#define CHRP_PCI_MEM_BUS 0x80000000 -#define CHRP_PCI_MEM_SIZE 0x7d000000 -#define CHRP_PCI_MEMORY_PHYS 0x00000000 -#define CHRP_PCI_MEMORY_BUS 0x00000000 -#define CHRP_PCI_MEMORY_SIZE 0x40000000 -#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ -#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ -#define PREP_ISA_IO_PHYS 0x80000000 -#define PREP_ISA_IO_BUS 0x00000000 -#define PREP_ISA_IO_SIZE 0x00800000 -#define PREP_PCI_IO_PHYS 0x81000000 -#define PREP_PCI_IO_BUS 0x01000000 -#define PREP_PCI_IO_SIZE 0x3e800000 -#define PREP_PCI_MEM_PHYS 0xc0000000 -#define PREP_PCI_MEM_BUS 0x00000000 -#define PREP_PCI_MEM_SIZE 0x3f000000 -#define PREP_PCI_MEMORY_PHYS 0x00000000 -#define PREP_PCI_MEMORY_BUS 0x80000000 -#define PREP_PCI_MEMORY_SIZE 0x80000000 -#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ -#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ -#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ -#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ -#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ -#define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */ -#define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */ -#define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */ -#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ -#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ -#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ -#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ -#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ -#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ -#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ -#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ -#define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/ -#define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */ -#define MEM_EN_ADR 0x800000a0 /* Memory bank enable */ -#define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */ - -/*----------------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_RESERVED0 0x0000 /* Reserved */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define EXC_OFF_MACH_CHCK 0x0200 /* Machine Check */ -#define EXC_OFF_DATA_STOR 0x0300 /* Data Storage */ -#define EXC_OFF_INS_STOR 0x0400 /* Instruction Storage */ -#define EXC_OFF_EXTERNAL 0x0500 /* External */ -#define EXC_OFF_ALIGN 0x0600 /* Alignment */ -#define EXC_OFF_PROGRAM 0x0700 /* Program */ -#define EXC_OFF_FPUNAVAIL 0x0800 /* Floating-point Unavailable */ -#define EXC_OFF_DECR 0x0900 /* Decrementer */ -#define EXC_OFF_RESERVED1 0x0A00 /* Reserved */ -#define EXC_OFF_RESERVED2 0x0B00 /* Reserved */ -#define EXC_OFF_SYS_CALL 0x0C00 /* System Call */ -#define EXC_OFF_TRACE 0x0D00 /* Trace */ -#define EXC_OFF_FPUNASSIST 0x0E00 /* Floating-point Assist */ - - /* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */ - /* these found in DINK code - may not apply to 8240*/ -#define EXC_OFF_PMI 0x0F00 /* Performance Monitoring Interrupt */ -#define EXC_OFF_VMXUI 0x0F20 /* VMX (AltiVec) Unavailable Interrupt */ - - /* 0x1000 - 0x2FFF are implementation specific */ - /* these found in DINK code - may not apply to 8240 */ -#define EXC_OFF_ITME 0x1000 /* Instruction Translation Miss Exception */ -#define EXC_OFF_DLTME 0x1100 /* Data Load Translation Miss Exception */ -#define EXC_OFF_DSTME 0x1200 /* Data Store Translation Miss Exception */ -#define EXC_OFF_IABE 0x1300 /* Instruction Addr Breakpoint Exception */ -#define EXC_OFF_SMIE 0x1400 /* System Management Interrupt Exception */ -#define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/ -#define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */ - -#define _START_OFFSET EXC_OFF_SYS_RESET - -#define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */ -#define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */ -#define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */ -#define MAP_A_CONFIG_DATA_LOW 0x0CFC /* Lower half of CONFIG_DAT for Map A */ -#define MAP_B_CONFIG_ADDR_HIGH 0xfec0 /* Upper half of CONFIG_ADDR for Map B */ -#define MAP_B_CONFIG_ADDR_LOW 0x0000 /* Lower half of CONFIG_ADDR for Map B */ -#define MAP_B_CONFIG_DATA_HIGH 0xfee0 /* Upper half of CONFIG_DAT for Map B */ -#define MAP_B_CONFIG_DATA_LOW 0x0000 /* Lower half of CONFIG_DAT for Map B */ - - -#if defined(CONFIG_SYS_ADDR_MAP_A) -#define CONFIG_ADDR_HIGH MAP_A_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */ -#define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */ -#define CONFIG_DATA_HIGH MAP_A_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */ -#define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */ -#else /* Assume Map B, default */ -#define CONFIG_ADDR_HIGH MAP_B_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */ -#define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */ -#define CONFIG_DATA_HIGH MAP_B_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */ -#define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */ -#endif - -#define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW) - -#define CONFIG_DATA (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW) - -/* Macros to write to config registers. addr should be a constant in all cases */ - -#define CONFIG_WRITE_BYTE( addr, data ) \ - __asm__ __volatile__( \ - " stwbrx %1, 0, %0\n \ - sync\n \ - stb %3, %4(%2)\n \ - sync " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ - "b" (CONFIG_DATA), "r" (data), \ - "n" ((addr) & 3)); - -#define CONFIG_WRITE_HALFWORD( addr, data ) \ - __asm__ __volatile__( \ - " stwbrx %1, 0, %0\n \ - sync\n \ - sthbrx %3, %4, %2\n \ - sync " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ - "r" (CONFIG_DATA), "r" (data), \ - "b" ((addr) & 3)); - -/* this assumes it's writeing on word boundaries*/ -#define CONFIG_WRITE_WORD( addr, data ) \ - __asm__ __volatile__( \ - " stwbrx %1, 0, %0\n \ - sync\n \ - stwbrx %3, 0, %2\n \ - sync " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" (addr), \ - "r" (CONFIG_DATA), "r" (data)); - -/* Configuration register reads*/ - -#define CONFIG_READ_BYTE( addr, reg ) \ - __asm__ ( \ - " stwbrx %1, 0, %2\n \ - sync\n \ - lbz %0, %4(%3)\n \ - sync " \ - : "=r" (reg) \ - : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ - "b" (CONFIG_DATA), "n" ((addr) & 3)); - - -#define CONFIG_READ_HALFWORD( addr, reg ) \ - __asm__ ( \ - " stwbrx %1, 0, %2\n \ - sync\n \ - lhbrx %0, %4, %3\n \ - sync " \ - : "=r" (reg) \ - : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ - "r" (CONFIG_DATA), \ - "b" ((addr) & 3)); - -/* this assumes it's reading on word boundaries*/ -#define CONFIG_READ_WORD( addr, reg ) \ - __asm__ ( \ - " stwbrx %1, 0, %2\n \ - sync\n \ - lwbrx %0, 0, %3\n \ - sync " \ - : "=r" (reg) \ - : "r" (addr), "r" (CONFIG_ADDR),\ - "r" (CONFIG_DATA)); - -/* - * configuration register 'addresses'. - * These are described in chaper 5 of the 8240 users manual. - * Where the register has an abreviation in the manual, this has - * been usaed here, otherwise a name in keeping with the norm has - * been invented. - * Note that some of these registers aren't documented in the manual. - */ - -#define PCICR 0x80000004 /* PCI Command Register */ -#define PCISR 0x80000006 /* PCI Status Register */ -#define REVID 0x80000008 /* CPU revision id */ -#define PIR 0x80000009 /* PCI Programming Interface Register */ -#define PBCCR 0x8000000b /* PCI Base Class Code Register */ -#define PCLSR 0x8000000c /* Processor Cache Line Size Register */ -#define PLTR 0x8000000d /* PCI Latancy Timer Register */ -#define PHTR 0x8000000e /* PCI Header Type Register */ -#define BISTCTRL 0x8000000f /* BIST Control */ -#define LMBAR 0x80000010 /* Local Base Address Register */ -#define PCSRBAR 0x80000014 /* PCSR Base Address Register */ -#define ILR 0x8000003c /* PCI Interrupt Line Register */ -#define IPR 0x8000003d /* Interrupt Pin Register */ -#define MINGNT 0x8000003e /* MIN GNI */ -#define MAXLAT 0x8000003f /* MAX LAT */ -#define PCIACR 0x80000046 /* PCI Arbiter Control Register */ -#define PMCR1 0x80000070 /* Power management config. 1 */ -#define PMCR2 0x80000072 /* Power management config. 2 */ -#define ODCR 0x80000073 /* Output Driver Control Register */ -#define CLKDCR 0x80000074 /* CLK Driver Control Register */ -#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) -#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */ -#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */ -#endif -#define EUMBBAR 0x80000078 /* Embedded Utilities Memory Block Base Address Register */ -#define EUMBBAR_VAL 0x80500000 /* PCI Relocation offset for EUMB region */ -#define EUMBSIZE 0x00100000 /* Size of EUMB region */ - -#define MSAR1 0x80000080 /* Memory Starting Address Register 1 */ -#define MSAR2 0x80000084 /* Memory Starting Address Register 2 */ -#define EMSAR1 0x80000088 /* Extended Memory Starting Address Register 1*/ -#define EMSAR2 0x8000008c /* Extended Memory Starting Address Register 2*/ -#define MEAR1 0x80000090 /* Memory Ending Address Register 1 */ -#define MEAR2 0x80000094 /* Memory Ending Address Register 2 */ -#define EMEAR1 0x80000098 /* Extended Memory Ending Address Register 1 */ -#define EMEAR2 0x8000009c /* Extended Memory Ending Address Register 2 */ -#define MBER 0x800000a0 /* Memory bank Enable Register*/ -#define MPMR 0x800000a3 /* Memory Page Mode Register (stores PGMAX) */ -#define PICR1 0x800000a8 /* Processor Interface Configuration Register 1 */ -#define PICR2 0x800000ac /* Processor Interface Configuration Register 2 */ -#define ECCSBECR 0x800000b8 /* ECC Single-Bit Error Counter Register */ -#define ECCSBETR 0x800000b8 /* ECC Single-Bit Error Trigger Register */ -#define ERRENR1 0x800000c0 /* Error Enableing Register 1 */ -#define ERRENR2 0x800000c4 /* Error Enableing Register 2 */ -#define ERRDR1 0x800000c1 /* Error Detection Register 1 */ -#define IPBESR 0x800000c3 /* Internal Processor Error Status Register */ -#define ERRDR2 0x800000c5 /* Error Detection Register 2 */ -#define PBESR 0x800000c7 /* PCI Bus Error Status Register */ -#define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */ -#define AMBOR 0x800000e0 /* Address Map B Options Register */ -#define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */ -#define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */ -#define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */ -#define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */ -#define MCCR4 0x800000fc /* Memory Control Configuration Register 4 */ - -/* some values for some of the above */ - -#define PICR1_CF_APARK 0x00000008 -#define PICR1_LE_MODE 0x00000020 -#define PICR1_ST_GATH_EN 0x00000040 -#if defined(CONFIG_MPC8240) -#define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */ -#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) -#define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */ -#define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */ -#define ERCR1 0x800000d0 /* Extended ROM Configuration Register 1 */ -#define ERCR2 0x800000d4 /* Extended ROM Configuration Register 2 */ -#define ERCR3 0x800000d8 /* Extended ROM Configuration Register 3 */ -#define ERCR4 0x800000dc /* Extended ROM Configuration Register 4 */ -#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */ -#define MIOCR1_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */ -#define MIOCR1_SHIFT 2 -#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */ -#define MIOCR2_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */ -#define MIOCR2_SHIFT 3 -#define ODCR_ADR_X 0x80000070 /* Output Driver Control register */ -#define ODCR_SHIFT 3 -#define PMCR2_ADR 0x80000072 /* Power Mgmnt Cfg 2 register */ -#define PMCR2_ADR_X 0x80000070 -#define PMCR2_SHIFT 3 -#define PMCR1_ADR 0x80000070 /* Power Mgmnt Cfg 1 reister */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -#define PICR1_CF_DPARK 0x00000200 -#define PICR1_MCP_EN 0x00000800 -#define PICR1_FLASH_WR_EN 0x00001000 -#ifdef CONFIG_MPC8240 -#define PICR1_ADDRESS_MAP 0x00010000 -#define PIRC1_MSK 0xff000000 -#endif -#define PICR1_PROC_TYPE_MSK 0x00060000 -#define PICR1_PROC_TYPE_603E 0x00040000 -#define PICR1_RCS0 0x00100000 - -#define PICR2_CF_SNOOP_WS_MASK 0x000c0000 -#define PICR2_CF_SNOOP_WS_0WS 0x00000000 -#define PICR2_CF_SNOOP_WS_1WS 0x00040000 -#define PICR2_CF_SNOOP_WS_2WS 0x00080000 -#define PICR2_CF_SNOOP_WS_3WS 0x000c0000 -#define PICR2_CF_APHASE_WS_MASK 0x0000000c -#define PICR2_CF_APHASE_WS_0WS 0x00000000 -#define PICR2_CF_APHASE_WS_1WS 0x00000004 -#define PICR2_CF_APHASE_WS_2WS 0x00000008 -#define PICR2_CF_APHASE_WS_3WS 0x0000000c - -#define MCCR1_ROMNAL_SHIFT 28 -#define MCCR1_ROMNAL_MSK 0xf0000000 -#define MCCR1_ROMFAL_SHIFT 23 -#define MCCR1_ROMFAL_MSK 0x0f800000 -#define MCCR1_DBUS_SIZE0 0x00400000 -#define MCCR1_BURST 0x00100000 -#define MCCR1_MEMGO 0x00080000 -#define MCCR1_SREN 0x00040000 -#if defined(CONFIG_MPC8240) -#define MCCR1_RAM_TYPE 0x00020000 -#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) -#define MCCR1_SDRAM_EN 0x00020000 -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -#define MCCR1_PCKEN 0x00010000 -#define MCCR1_BANK1ROW_SHIFT 2 -#define MCCR1_BANK2ROW_SHIFT 4 -#define MCCR1_BANK3ROW_SHIFT 6 -#define MCCR1_BANK4ROW_SHIFT 8 -#define MCCR1_BANK5ROW_SHIFT 10 -#define MCCR1_BANK6ROW_SHIFT 12 -#define MCCR1_BANK7ROW_SHIFT 14 - -#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000 -#define MCCR2_TS_WAIT_TIMER_SHIFT 29 -#define MCCR2_ASRISE_MSK 0x1e000000 -#define MCCR2_ASRISE_SHIFT 25 -#define MCCR2_ASFALL_MSK 0x01e00000 -#define MCCR2_ASFALL_SHIFT 21 - -#define MCCR2_INLINE_PAR_NOT_ECC 0x00100000 -#define MCCR2_WRITE_PARITY_CHK 0x00080000 -#define MCCR2_INLFRD_PARECC_CHK_EN 0x00040000 -#ifdef CONFIG_MPC8240 -#define MCCR2_ECC_EN 0x00020000 -#define MCCR2_EDO 0x00010000 -#endif -#define MCCR2_REFINT_MSK 0x0000fffc -#define MCCR2_REFINT_SHIFT 2 -#define MCCR2_RSV_PG 0x00000002 -#define MCCR2_PMW_PAR 0x00000001 - -#define MCCR3_BSTOPRE2TO5_MSK 0xf0000000 /*BSTOPRE[2-5]*/ -#define MCCR3_BSTOPRE2TO5_SHIFT 28 -#define MCCR3_REFREC_MSK 0x0f000000 -#define MCCR3_REFREC_SHIFT 24 -#ifdef CONFIG_MPC8240 -#define MCCR3_RDLAT_MSK 0x00f00000 -#define MCCR3_RDLAT_SHIFT 20 -#define MCCR3_CPX 0x00010000 -#define MCCR3_RAS6P_MSK 0x00078000 -#define MCCR3_RAS6P_SHIFT 15 -#define MCCR3_CAS5_MSK 0x00007000 -#define MCCR3_CAS5_SHIFT 12 -#define MCCR3_CP4_MSK 0x00000e00 -#define MCCR3_CP4_SHIFT 9 -#define MCCR3_CAS3_MSK 0x000001c0 -#define MCCR3_CAS3_SHIFT 6 -#define MCCR3_RCD2_MSK 0x00000038 -#define MCCR3_RCD2_SHIFT 3 -#define MCCR3_RP1_MSK 0x00000007 -#define MCCR3_RP1_SHIFT 0 -#endif - -#define MCCR4_PRETOACT_MSK 0xf0000000 -#define MCCR4_PRETOACT_SHIFT 28 -#define MCCR4_ACTTOPRE_MSK 0x0f000000 -#define MCCR4_ACTTOPRE_SHIFT 24 -#define MCCR4_WMODE 0x00800000 -#define MCCR4_INLINE 0x00400000 -#if defined(CONFIG_MPC8240) -#define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/ -#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) -#define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -#define MCCR4_REGISTERED 0x00100000 -#define MCCR4_BSTOPRE0TO1_MSK 0x000c0000 /*BSTOPRE[0-1]*/ -#define MCCR4_BSTOPRE0TO1_SHIFT 18 -#define MCCR4_REGDIMM 0x00008000 -#define MCCR4_SDMODE_MSK 0x00007f00 -#define MCCR4_SDMODE_SHIFT 8 -#define MCCR4_ACTTORW_MSK 0x000000f0 -#define MCCR4_ACTTORW_SHIFT 4 -#define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/ -#define MCCR4_BSTOPRE6TO9_SHIFT 0 -#define MCCR4_DBUS_SIZE2_SHIFT 17 - -#define MICR_ADDR_MASK 0x0ff00000 -#define MICR_ADDR_SHIFT 20 -#define MICR_EADDR_MASK 0x30000000 -#define MICR_EADDR_SHIFT 28 - -/*eumb and epic config*/ - -#define EPIC_FPR 0x00041000 -#define EPIC_GCR 0x00041020 -#define EPIC_EICR 0x00041030 -#define EPIC_EVI 0x00041080 -#define EPIC_PI 0x00041090 -#define EPIC_SVR 0x000410E0 -#define EPIC_TFRR 0x000410F0 - -/* - * Note the information for these is rather mangled in the 8240 manual. - * These are guesses. - */ - -#define EPIC_GTCCR0 0x00041100 -#define EPIC_GTCCR1 0x00041140 -#define EPIC_GTCCR2 0x00041180 -#define EPIC_GTCCR3 0x000411C0 -#define EPIC_GTBCR0 0x00041110 -#define EPIC_GTBCR1 0x00041150 -#define EPIC_GTBCR2 0x00041190 -#define EPIC_GTBCR3 0x000411D0 -#define EPIC_GTVPR0 0x00041120 -#define EPIC_GTVPR1 0x00041160 -#define EPIC_GTVPR2 0x000411a0 -#define EPIC_GTVPR3 0x000411e0 -#define EPIC_GTDR0 0x00041130 -#define EPIC_GTDR1 0x00041170 -#define EPIC_GTDR2 0x000411b0 -#define EPIC_GTDR3 0x000411f0 - -#define EPIC_IVPR0 0x00050200 -#define EPIC_IVPR1 0x00050220 -#define EPIC_IVPR2 0x00050240 -#define EPIC_IVPR3 0x00050260 -#define EPIC_IVPR4 0x00050280 - -#define EPIC_SVPR0 0x00050200 -#define EPIC_SVPR1 0x00050220 -#define EPIC_SVPR2 0x00050240 -#define EPIC_SVPR3 0x00050260 -#define EPIC_SVPR4 0x00050280 -#define EPIC_SVPR5 0x000502A0 -#define EPIC_SVPR6 0x000502C0 -#define EPIC_SVPR7 0x000502E0 -#define EPIC_SVPR8 0x00050300 -#define EPIC_SVPR9 0x00050320 -#define EPIC_SVPRa 0x00050340 -#define EPIC_SVPRb 0x00050360 -#define EPIC_SVPRc 0x00050380 -#define EPIC_SVPRd 0x000503A0 -#define EPIC_SVPRe 0x000503C0 -#define EPIC_SVPRf 0x000503E0 - -/* MPC8240 Byte Swap/PCI Support Macros */ -#define BYTE_SWAP_16_BIT(x) ( (((x) & 0x00ff) << 8) | ( (x) >> 8) ) -#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ - (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) -#define PCISWAP(x) LONGSWAP(x) - -#ifndef __ASSEMBLY__ - -/* - * MPC107 Support - * - */ -unsigned int mpc824x_mpc107_getreg(unsigned int regNum); -void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal); -void mpc824x_mpc107_write8(unsigned int address, unsigned char data); -void mpc824x_mpc107_write16(unsigned int address, unsigned short data); -void mpc824x_mpc107_write32(unsigned int address, unsigned int data); -unsigned char mpc824x_mpc107_read8(unsigned int address); -unsigned short mpc824x_mpc107_read16(unsigned int address); -unsigned int mpc824x_mpc107_read32(unsigned int address); -unsigned int mpc824x_eummbar_read(unsigned int regNum); -void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal); - -#ifdef CONFIG_PCI -struct pci_controller; -void pci_cpm824x_init(struct pci_controller* hose); -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __MPC824X_H__ */ diff --git a/include/mpc8260.h b/include/mpc8260.h index a8ae278799..9980c74b51 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -21,10 +21,6 @@ #if defined(CONFIG_MPC8272_FAMILY) #ifdef CONFIG_MPC8247 #define CPU_ID_STR "MPC8247" -#elif defined CONFIG_MPC8248 -#define CPU_ID_STR "MPC8248" -#elif defined CONFIG_MPC8271 -#define CPU_ID_STR "MPC8271" #else #define CPU_ID_STR "MPC8272" #endif diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 31e83f2cc9..9fe4748032 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -41,9 +41,9 @@ #ifndef __ASSEMBLY__ typedef struct { - unsigned long freqProcessor; - unsigned long freqSystemBus; - unsigned long freqLocalBus; + unsigned long freq_processor; + unsigned long freq_systembus; + unsigned long freq_localbus; } MPC86xx_SYS_INFO; #define l1icache_enable icache_enable diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 3cde26b940..33a2cd8057 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -2,7 +2,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* diff --git a/include/msc01.h b/include/msc01.h new file mode 100644 index 0000000000..37cf963f13 --- /dev/null +++ b/include/msc01.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MSC01_H__ +#define __MSC01_H__ + +/* + * Bus Interface Unit + */ + +#define MSC01_BIU_IP1BAS1L_OFS 0x0208 +#define MSC01_BIU_IP1MSK1L_OFS 0x0218 +#define MSC01_BIU_IP1BAS2L_OFS 0x0248 +#define MSC01_BIU_IP1MSK2L_OFS 0x0258 +#define MSC01_BIU_IP2BAS1L_OFS 0x0288 +#define MSC01_BIU_IP2MSK1L_OFS 0x0298 +#define MSC01_BIU_IP2BAS2L_OFS 0x02c8 +#define MSC01_BIU_IP2MSK2L_OFS 0x02d8 +#define MSC01_BIU_IP3BAS1L_OFS 0x0308 +#define MSC01_BIU_IP3MSK1L_OFS 0x0318 +#define MSC01_BIU_IP3BAS2L_OFS 0x0348 +#define MSC01_BIU_IP3MSK2L_OFS 0x0358 +#define MSC01_BIU_MCBAS1L_OFS 0x0388 +#define MSC01_BIU_MCMSK1L_OFS 0x0398 +#define MSC01_BIU_MCBAS2L_OFS 0x03c8 +#define MSC01_BIU_MCMSK2L_OFS 0x03d8 + +/* + * PCI Bridge + */ + +#define MSC01_PCI_SC2PMBASL_OFS 0x0208 +#define MSC01_PCI_SC2PMMSKL_OFS 0x0218 +#define MSC01_PCI_SC2PMMAPL_OFS 0x0228 +#define MSC01_PCI_SC2PIOBASL_OFS 0x0248 +#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 +#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 +#define MSC01_PCI_P2SCMSKL_OFS 0x0308 +#define MSC01_PCI_P2SCMAPL_OFS 0x0318 +#define MSC01_PCI_INTSTAT_OFS 0x0608 +#define MSC01_PCI_CFGADDR_OFS 0x0610 +#define MSC01_PCI_CFGDATA_OFS 0x0618 +#define MSC01_PCI_HEAD0_OFS 0x2000 +#define MSC01_PCI_HEAD1_OFS 0x2008 +#define MSC01_PCI_HEAD2_OFS 0x2010 +#define MSC01_PCI_HEAD3_OFS 0x2018 +#define MSC01_PCI_HEAD4_OFS 0x2020 +#define MSC01_PCI_HEAD5_OFS 0x2028 +#define MSC01_PCI_HEAD6_OFS 0x2030 +#define MSC01_PCI_HEAD7_OFS 0x2038 +#define MSC01_PCI_HEAD8_OFS 0x2040 +#define MSC01_PCI_HEAD9_OFS 0x2048 +#define MSC01_PCI_HEAD10_OFS 0x2050 +#define MSC01_PCI_HEAD11_OFS 0x2058 +#define MSC01_PCI_HEAD12_OFS 0x2060 +#define MSC01_PCI_HEAD13_OFS 0x2068 +#define MSC01_PCI_HEAD14_OFS 0x2070 +#define MSC01_PCI_HEAD15_OFS 0x2078 +#define MSC01_PCI_BAR0_OFS 0x2220 +#define MSC01_PCI_CFG_OFS 0x2380 +#define MSC01_PCI_SWAP_OFS 0x2388 + +#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 +#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 + +#define MSC01_PCI_INTSTAT_TA_SHF 6 +#define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF) +#define MSC01_PCI_INTSTAT_MA_SHF 7 +#define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF) + +#define MSC01_PCI_CFGADDR_BNUM_SHF 16 +#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF) +#define MSC01_PCI_CFGADDR_DNUM_SHF 11 +#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF) +#define MSC01_PCI_CFGADDR_FNUM_SHF 8 +#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF) +#define MSC01_PCI_CFGADDR_RNUM_SHF 2 +#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF) + +#define MSC01_PCI_HEAD0_VENDORID_SHF 0 +#define MSC01_PCI_HEAD0_DEVICEID_SHF 16 + +#define MSC01_PCI_HEAD2_REV_SHF 0 +#define MSC01_PCI_HEAD2_CLASS_SHF 16 + +#define MSC01_PCI_CFG_EN_SHF 15 +#define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF) +#define MSC01_PCI_CFG_G_SHF 16 +#define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF) +#define MSC01_PCI_CFG_RA_SHF 17 +#define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF) + +#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0 +#define MSC01_PCI_SWAP_IO_BSWAP_SHF 18 + +/* + * Peripheral Bus Controller + */ + +#define MSC01_PBC_CLKCFG_OFS 0x0100 +#define MSC01_PBC_CS0CFG_OFS 0x0400 +#define MSC01_PBC_CS0TIM_OFS 0x0500 +#define MSC01_PBC_CS0RW_OFS 0x0600 + +#define MSC01_PBC_CLKCFG_SHF 0 +#define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF) + +#define MSC01_PBC_CS0CFG_WS_SHF 0 +#define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF) +#define MSC01_PBC_CS0CFG_WSIDLE_SHF 8 +#define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF) +#define MSC01_PBC_CS0CFG_DTYP_SHF 16 +#define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF) +#define MSC01_PBC_CS0CFG_ADM_SHF 20 +#define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF) + +#define MSC01_PBC_CS0TIM_CAT_SHF 0 +#define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF) +#define MSC01_PBC_CS0TIM_CDT_SHF 8 +#define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF) + +#define MSC01_PBC_CS0RW_WAT_SHF 0 +#define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF) +#define MSC01_PBC_CS0RW_WDT_SHF 8 +#define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF) +#define MSC01_PBC_CS0RW_RAT_SHF 16 +#define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF) +#define MSC01_PBC_CS0RW_RDT_SHF 24 +#define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF) + +#endif /* __MSC01_H__ */ diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index d51c1abd18..0ef582aeec 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -1,30 +1,43 @@ /* - * $Id: mtd-abi.h,v 1.13 2005/11/07 11:14:56 gleixner Exp $ + * Copyright © 1999-2010 David Woodhouse et al. + * + * SPDX-License-Identifier: GPL-2.0+ * - * Portions of MTD ABI definition which are shared by kernel and user space */ #ifndef __MTD_ABI_H__ #define __MTD_ABI_H__ -#if 1 +#ifdef __UBOOT__ #include #endif #include struct erase_info_user { - uint32_t start; - uint32_t length; + __u32 start; + __u32 length; +}; + +struct erase_info_user64 { + __u64 start; + __u64 length; }; struct mtd_oob_buf { - uint32_t start; - uint32_t length; + __u32 start; + __u32 length; unsigned char __user *ptr; }; -/* +struct mtd_oob_buf64 { + __u64 start; + __u32 pad; + __u32 length; + __u64 usr_ptr; +}; + +/** * MTD operation modes * * @MTD_OPS_PLACE_OOB: OOB data are placed at the given offset (default) @@ -43,18 +56,45 @@ enum { MTD_OPS_RAW = 2, }; +/** + * struct mtd_write_req - data structure for requesting a write operation + * + * @start: start address + * @len: length of data buffer + * @ooblen: length of OOB buffer + * @usr_data: user-provided data buffer + * @usr_oob: user-provided OOB buffer + * @mode: MTD mode (see "MTD operation modes") + * @padding: reserved, must be set to 0 + * + * This structure supports ioctl(MEMWRITE) operations, allowing data and/or OOB + * writes in various modes. To write to OOB-only, set @usr_data == NULL, and to + * write data-only, set @usr_oob == NULL. However, setting both @usr_data and + * @usr_oob to NULL is not allowed. + */ +struct mtd_write_req { + __u64 start; + __u64 len; + __u64 ooblen; + __u64 usr_data; + __u64 usr_oob; + __u8 mode; + __u8 padding[7]; +}; + #define MTD_ABSENT 0 #define MTD_RAM 1 #define MTD_ROM 2 #define MTD_NORFLASH 3 -#define MTD_NANDFLASH 4 +#define MTD_NANDFLASH 4 /* SLC NAND */ #define MTD_DATAFLASH 6 #define MTD_UBIVOLUME 7 +#define MTD_MLCNANDFLASH 8 /* MLC NAND (including TLC) */ #define MTD_WRITEABLE 0x400 /* Device is writeable */ #define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */ #define MTD_NO_ERASE 0x1000 /* No erase necessary */ -#define MTD_STUPID_LOCK 0x2000 /* Always locked after reset */ +#define MTD_POWERUP_LOCK 0x2000 /* Always locked after reset */ /* Some common devices / combinations of capabilities */ #define MTD_CAP_ROM 0 @@ -62,12 +102,12 @@ enum { #define MTD_CAP_NORFLASH (MTD_WRITEABLE | MTD_BIT_WRITEABLE) #define MTD_CAP_NANDFLASH (MTD_WRITEABLE) -/* ECC byte placement */ -#define MTD_NANDECC_OFF 0 /* Switch off ECC (Not recommended) */ -#define MTD_NANDECC_PLACE 1 /* Use the given placement in the structure (YAFFS1 legacy mode) */ -#define MTD_NANDECC_AUTOPLACE 2 /* Use the default placement scheme */ -#define MTD_NANDECC_PLACEONLY 3 /* Use the given placement in the structure (Do not store ecc result on read) */ -#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */ +/* Obsolete ECC byte placement modes (used with obsolete MEMGETOOBSEL) */ +#define MTD_NANDECC_OFF 0 // Switch off ECC (Not recommended) +#define MTD_NANDECC_PLACE 1 // Use the given placement in the structure (YAFFS1 legacy mode) +#define MTD_NANDECC_AUTOPLACE 2 // Use the default placement scheme +#define MTD_NANDECC_PLACEONLY 3 // Use the given placement in the structure (Do not store ecc result on read) +#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default /* OTP mode selection */ #define MTD_OTP_OFF 0 @@ -75,32 +115,35 @@ enum { #define MTD_OTP_USER 2 struct mtd_info_user { - uint8_t type; - uint32_t flags; - uint32_t size; /* Total size of the MTD */ - uint32_t erasesize; - uint32_t writesize; - uint32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ - /* The below two fields are obsolete and broken, do not use them - * (TODO: remove at some point) */ - uint32_t ecctype; - uint32_t eccsize; + __u8 type; + __u32 flags; + __u32 size; /* Total size of the MTD */ + __u32 erasesize; + __u32 writesize; + __u32 oobsize; /* Amount of OOB data per block (e.g. 16) */ + __u64 padding; /* Old obsolete field; do not use */ }; struct region_info_user { - uint32_t offset; /* At which this region starts, - * from the beginning of the MTD */ - uint32_t erasesize; /* For this region */ - uint32_t numblocks; /* Number of blocks in this region */ - uint32_t regionindex; + __u32 offset; /* At which this region starts, + * from the beginning of the MTD */ + __u32 erasesize; /* For this region */ + __u32 numblocks; /* Number of blocks in this region */ + __u32 regionindex; }; struct otp_info { - uint32_t start; - uint32_t length; - uint32_t locked; + __u32 start; + __u32 length; + __u32 locked; }; +/* + * Note, the following ioctl existed in the past and was removed: + * #define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo) + * Try to avoid adding a new ioctl with the same ioctl number. + */ + /* Get basic MTD characteristics info (better to use sysfs) */ #define MEMGETINFO _IOR('M', 1, struct mtd_info_user) /* Erase segment of MTD */ @@ -118,12 +161,11 @@ struct otp_info { /* Get information about the erase region for a specific index */ #define MEMGETREGIONINFO _IOWR('M', 8, struct region_info_user) /* Get info about OOB modes (e.g., RAW, PLACE, AUTO) - legacy interface */ -#define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo) #define MEMGETOOBSEL _IOR('M', 10, struct nand_oobinfo) /* Check if an eraseblock is bad */ -#define MEMGETBADBLOCK _IOW('M', 11, loff_t) +#define MEMGETBADBLOCK _IOW('M', 11, __kernel_loff_t) /* Mark an eraseblock as bad */ -#define MEMSETBADBLOCK _IOW('M', 12, loff_t) +#define MEMSETBADBLOCK _IOW('M', 12, __kernel_loff_t) /* Set OTP (One-Time Programmable) mode (factory vs. user) */ #define OTPSELECT _IOR('M', 13, int) /* Get number of OTP (One-Time Programmable) regions */ @@ -133,37 +175,56 @@ struct otp_info { /* Lock a given range of user data (must be in mode %MTD_FILE_MODE_OTP_USER) */ #define OTPLOCK _IOR('M', 16, struct otp_info) /* Get ECC layout (deprecated) */ -#define ECCGETLAYOUT _IOR('M', 17, struct nand_ecclayout) +#define ECCGETLAYOUT _IOR('M', 17, struct nand_ecclayout_user) /* Get statistics about corrected/uncorrected errors */ #define ECCGETSTATS _IOR('M', 18, struct mtd_ecc_stats) /* Set MTD mode on a per-file-descriptor basis (see "MTD file modes") */ #define MTDFILEMODE _IO('M', 19) +/* Erase segment of MTD (supports 64-bit address) */ +#define MEMERASE64 _IOW('M', 20, struct erase_info_user64) +/* Write data to OOB (64-bit version) */ +#define MEMWRITEOOB64 _IOWR('M', 21, struct mtd_oob_buf64) +/* Read data from OOB (64-bit version) */ +#define MEMREADOOB64 _IOWR('M', 22, struct mtd_oob_buf64) +/* Check if chip is locked (for MTD that supports it) */ +#define MEMISLOCKED _IOR('M', 23, struct erase_info_user) +/* + * Most generic write interface; can write in-band and/or out-of-band in various + * modes (see "struct mtd_write_req"). This ioctl is not supported for flashes + * without OOB, e.g., NOR flash. + */ +#define MEMWRITE _IOWR('M', 24, struct mtd_write_req) /* * Obsolete legacy interface. Keep it in order not to break userspace * interfaces */ struct nand_oobinfo { - uint32_t useecc; - uint32_t eccbytes; - uint32_t oobfree[8][2]; - uint32_t eccpos[48]; + __u32 useecc; + __u32 eccbytes; + __u32 oobfree[8][2]; + __u32 eccpos[32]; }; struct nand_oobfree { - uint32_t offset; - uint32_t length; + __u32 offset; + __u32 length; }; #define MTD_MAX_OOBFREE_ENTRIES 8 +#define MTD_MAX_ECCPOS_ENTRIES 64 /* - * ECC layout control structure. Exported to userspace for - * diagnosis and to allow creation of raw images + * OBSOLETE: ECC layout control structure. Exported to user-space via ioctl + * ECCGETLAYOUT for backwards compatbility and should not be mistaken as a + * complete set of ECC information. The ioctl truncates the larger internal + * structure to retain binary compatibility with the static declaration of the + * ioctl. Note that the "MTD_MAX_..._ENTRIES" macros represent the max size of + * the user struct, not the MAX size of the internal struct nand_ecclayout. */ -struct nand_ecclayout { - uint32_t eccbytes; - uint32_t eccpos[128]; - uint32_t oobavail; +struct nand_ecclayout_user { + __u32 eccbytes; + __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES]; + __u32 oobavail; struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; }; @@ -176,10 +237,10 @@ struct nand_ecclayout { * @bbtblocks: number of blocks reserved for bad block tables */ struct mtd_ecc_stats { - uint32_t corrected; - uint32_t failed; - uint32_t badblocks; - uint32_t bbtblocks; + __u32 corrected; + __u32 failed; + __u32 badblocks; + __u32 bbtblocks; }; /* @@ -200,10 +261,15 @@ struct mtd_ecc_stats { * used out of necessity (e.g., `write()', ioctl(MEMWRITEOOB64)). */ enum mtd_file_modes { - MTD_MODE_NORMAL = MTD_OTP_OFF, - MTD_MODE_OTP_FACTORY = MTD_OTP_FACTORY, - MTD_MODE_OTP_USER = MTD_OTP_USER, - MTD_MODE_RAW, + MTD_FILE_MODE_NORMAL = MTD_OTP_OFF, + MTD_FILE_MODE_OTP_FACTORY = MTD_OTP_FACTORY, + MTD_FILE_MODE_OTP_USER = MTD_OTP_USER, + MTD_FILE_MODE_RAW, }; +static inline int mtd_type_is_nand_user(const struct mtd_info_user *mtd) +{ + return mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH; +} + #endif /* __MTD_ABI_H__ */ diff --git a/include/mtd/ubi-user.h b/include/mtd/ubi-user.h index 1ccc06ea68..22d90040f8 100644 --- a/include/mtd/ubi-user.h +++ b/include/mtd/ubi-user.h @@ -1,7 +1,7 @@ /* - * Copyright (c) International Business Machines Corp., 2006 + * Copyright © International Business Machines Corp., 2006 * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ * * Author: Artem Bityutskiy (Битюцкий Артём) */ @@ -9,6 +9,8 @@ #ifndef __UBI_USER_H__ #define __UBI_USER_H__ +#include + /* * UBI device creation (the same as MTD device attachment) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -28,30 +30,37 @@ * UBI volume creation * ~~~~~~~~~~~~~~~~~~~ * - * UBI volumes are created via the %UBI_IOCMKVOL IOCTL command of UBI character + * UBI volumes are created via the %UBI_IOCMKVOL ioctl command of UBI character * device. A &struct ubi_mkvol_req object has to be properly filled and a - * pointer to it has to be passed to the IOCTL. + * pointer to it has to be passed to the ioctl. * * UBI volume deletion * ~~~~~~~~~~~~~~~~~~~ * - * To delete a volume, the %UBI_IOCRMVOL IOCTL command of the UBI character + * To delete a volume, the %UBI_IOCRMVOL ioctl command of the UBI character * device should be used. A pointer to the 32-bit volume ID hast to be passed - * to the IOCTL. + * to the ioctl. * * UBI volume re-size * ~~~~~~~~~~~~~~~~~~ * - * To re-size a volume, the %UBI_IOCRSVOL IOCTL command of the UBI character + * To re-size a volume, the %UBI_IOCRSVOL ioctl command of the UBI character * device should be used. A &struct ubi_rsvol_req object has to be properly - * filled and a pointer to it has to be passed to the IOCTL. + * filled and a pointer to it has to be passed to the ioctl. + * + * UBI volumes re-name + * ~~~~~~~~~~~~~~~~~~~ + * + * To re-name several volumes atomically at one go, the %UBI_IOCRNVOL command + * of the UBI character device should be used. A &struct ubi_rnvol_req object + * has to be properly filled and a pointer to it has to be passed to the ioctl. * * UBI volume update * ~~~~~~~~~~~~~~~~~ * - * Volume update should be done via the %UBI_IOCVOLUP IOCTL command of the + * Volume update should be done via the %UBI_IOCVOLUP ioctl command of the * corresponding UBI volume character device. A pointer to a 64-bit update - * size should be passed to the IOCTL. After this, UBI expects user to write + * size should be passed to the ioctl. After this, UBI expects user to write * this number of bytes to the volume character device. The update is finished * when the claimed number of bytes is passed. So, the volume update sequence * is something like: @@ -61,14 +70,68 @@ * write(fd, buf, image_size); * close(fd); * - * Atomic eraseblock change + * Logical eraseblock erase + * ~~~~~~~~~~~~~~~~~~~~~~~~ + * + * To erase a logical eraseblock, the %UBI_IOCEBER ioctl command of the + * corresponding UBI volume character device should be used. This command + * unmaps the requested logical eraseblock, makes sure the corresponding + * physical eraseblock is successfully erased, and returns. + * + * Atomic logical eraseblock change + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * Atomic logical eraseblock change operation is called using the %UBI_IOCEBCH + * ioctl command of the corresponding UBI volume character device. A pointer to + * a &struct ubi_leb_change_req object has to be passed to the ioctl. Then the + * user is expected to write the requested amount of bytes (similarly to what + * should be done in case of the "volume update" ioctl). + * + * Logical eraseblock map + * ~~~~~~~~~~~~~~~~~~~~~ + * + * To map a logical eraseblock to a physical eraseblock, the %UBI_IOCEBMAP + * ioctl command should be used. A pointer to a &struct ubi_map_req object is + * expected to be passed. The ioctl maps the requested logical eraseblock to + * a physical eraseblock and returns. Only non-mapped logical eraseblocks can + * be mapped. If the logical eraseblock specified in the request is already + * mapped to a physical eraseblock, the ioctl fails and returns error. + * + * Logical eraseblock unmap * ~~~~~~~~~~~~~~~~~~~~~~~~ * - * Atomic eraseblock change operation is done via the %UBI_IOCEBCH IOCTL - * command of the corresponding UBI volume character device. A pointer to - * &struct ubi_leb_change_req has to be passed to the IOCTL. Then the user is - * expected to write the requested amount of bytes. This is similar to the - * "volume update" IOCTL. + * To unmap a logical eraseblock to a physical eraseblock, the %UBI_IOCEBUNMAP + * ioctl command should be used. The ioctl unmaps the logical eraseblocks, + * schedules corresponding physical eraseblock for erasure, and returns. Unlike + * the "LEB erase" command, it does not wait for the physical eraseblock being + * erased. Note, the side effect of this is that if an unclean reboot happens + * after the unmap ioctl returns, you may find the LEB mapped again to the same + * physical eraseblock after the UBI is run again. + * + * Check if logical eraseblock is mapped + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * To check if a logical eraseblock is mapped to a physical eraseblock, the + * %UBI_IOCEBISMAP ioctl command should be used. It returns %0 if the LEB is + * not mapped, and %1 if it is mapped. + * + * Set an UBI volume property + * ~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * To set an UBI volume property the %UBI_IOCSETPROP ioctl command should be + * used. A pointer to a &struct ubi_set_vol_prop_req object is expected to be + * passed. The object describes which property should be set, and to which value + * it should be set. + * + * Block devices on UBI volumes + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * To create a R/O block device on top of an UBI volume the %UBI_IOCVOLCRBLK + * should be used. A pointer to a &struct ubi_blkcreate_req object is expected + * to be passed, which is not used and reserved for future usage. + * + * Conversely, to remove a block device the %UBI_IOCVOLRMBLK should be used, + * which takes no arguments. */ /* @@ -82,56 +145,60 @@ /* Maximum volume name length */ #define UBI_MAX_VOLUME_NAME 127 -/* IOCTL commands of UBI character devices */ +/* ioctl commands of UBI character devices */ #define UBI_IOC_MAGIC 'o' /* Create an UBI volume */ #define UBI_IOCMKVOL _IOW(UBI_IOC_MAGIC, 0, struct ubi_mkvol_req) /* Remove an UBI volume */ -#define UBI_IOCRMVOL _IOW(UBI_IOC_MAGIC, 1, int32_t) +#define UBI_IOCRMVOL _IOW(UBI_IOC_MAGIC, 1, __s32) /* Re-size an UBI volume */ #define UBI_IOCRSVOL _IOW(UBI_IOC_MAGIC, 2, struct ubi_rsvol_req) +/* Re-name volumes */ +#define UBI_IOCRNVOL _IOW(UBI_IOC_MAGIC, 3, struct ubi_rnvol_req) -/* IOCTL commands of the UBI control character device */ +/* ioctl commands of the UBI control character device */ #define UBI_CTRL_IOC_MAGIC 'o' /* Attach an MTD device */ #define UBI_IOCATT _IOW(UBI_CTRL_IOC_MAGIC, 64, struct ubi_attach_req) /* Detach an MTD device */ -#define UBI_IOCDET _IOW(UBI_CTRL_IOC_MAGIC, 65, int32_t) +#define UBI_IOCDET _IOW(UBI_CTRL_IOC_MAGIC, 65, __s32) -/* IOCTL commands of UBI volume character devices */ +/* ioctl commands of UBI volume character devices */ #define UBI_VOL_IOC_MAGIC 'O' -/* Start UBI volume update */ -#define UBI_IOCVOLUP _IOW(UBI_VOL_IOC_MAGIC, 0, int64_t) -/* An eraseblock erasure command, used for debugging, disabled by default */ -#define UBI_IOCEBER _IOW(UBI_VOL_IOC_MAGIC, 1, int32_t) -/* An atomic eraseblock change command */ -#define UBI_IOCEBCH _IOW(UBI_VOL_IOC_MAGIC, 2, int32_t) +/* Start UBI volume update + * Note: This actually takes a pointer (__s64*), but we can't change + * that without breaking the ABI on 32bit systems + */ +#define UBI_IOCVOLUP _IOW(UBI_VOL_IOC_MAGIC, 0, __s64) +/* LEB erasure command, used for debugging, disabled by default */ +#define UBI_IOCEBER _IOW(UBI_VOL_IOC_MAGIC, 1, __s32) +/* Atomic LEB change command */ +#define UBI_IOCEBCH _IOW(UBI_VOL_IOC_MAGIC, 2, __s32) +/* Map LEB command */ +#define UBI_IOCEBMAP _IOW(UBI_VOL_IOC_MAGIC, 3, struct ubi_map_req) +/* Unmap LEB command */ +#define UBI_IOCEBUNMAP _IOW(UBI_VOL_IOC_MAGIC, 4, __s32) +/* Check if LEB is mapped command */ +#define UBI_IOCEBISMAP _IOR(UBI_VOL_IOC_MAGIC, 5, __s32) +/* Set an UBI volume property */ +#define UBI_IOCSETVOLPROP _IOW(UBI_VOL_IOC_MAGIC, 6, \ + struct ubi_set_vol_prop_req) +/* Create a R/O block device on top of an UBI volume */ +#define UBI_IOCVOLCRBLK _IOW(UBI_VOL_IOC_MAGIC, 7, struct ubi_blkcreate_req) +/* Remove the R/O block device */ +#define UBI_IOCVOLRMBLK _IO(UBI_VOL_IOC_MAGIC, 8) /* Maximum MTD device name length supported by UBI */ #define MAX_UBI_MTD_NAME_LEN 127 -/* - * UBI data type hint constants. - * - * UBI_LONGTERM: long-term data - * UBI_SHORTTERM: short-term data - * UBI_UNKNOWN: data persistence is unknown - * - * These constants are used when data is written to UBI volumes in order to - * help the UBI wear-leveling unit to find more appropriate physical - * eraseblocks. - */ -enum { - UBI_LONGTERM = 1, - UBI_SHORTTERM = 2, - UBI_UNKNOWN = 3, -}; +/* Maximum amount of UBI volumes that can be re-named at one go */ +#define UBI_MAX_RNVOL 32 /* * UBI volume type constants. @@ -144,11 +211,23 @@ enum { UBI_STATIC_VOLUME = 4, }; +/* + * UBI set volume property ioctl constants. + * + * @UBI_VOL_PROP_DIRECT_WRITE: allow (any non-zero value) or disallow (value 0) + * user to directly write and erase individual + * eraseblocks on dynamic volumes + */ +enum { + UBI_VOL_PROP_DIRECT_WRITE = 1, +}; + /** * struct ubi_attach_req - attach MTD device request. * @ubi_num: UBI device number to create * @mtd_num: MTD device number to attach * @vid_hdr_offset: VID header offset (use defaults if %0) + * @max_beb_per1024: maximum expected number of bad PEB per 1024 PEBs * @padding: reserved for future, not used, has to be zeroed * * This data structure is used to specify MTD device UBI has to attach and the @@ -164,20 +243,33 @@ enum { * it will be 512 in case of a 2KiB page NAND flash with 4 512-byte sub-pages. * * But in rare cases, if this optimizes things, the VID header may be placed to - * a different offset. For example, the boot-loader might do things faster if the - * VID header sits at the end of the first 2KiB NAND page with 4 sub-pages. As - * the boot-loader would not normally need to read EC headers (unless it needs - * UBI in RW mode), it might be faster to calculate ECC. This is weird example, - * but it real-life example. So, in this example, @vid_hdr_offer would be - * 2KiB-64 bytes = 1984. Note, that this position is not even 512-bytes - * aligned, which is OK, as UBI is clever enough to realize this is 4th sub-page - * of the first page and add needed padding. + * a different offset. For example, the boot-loader might do things faster if + * the VID header sits at the end of the first 2KiB NAND page with 4 sub-pages. + * As the boot-loader would not normally need to read EC headers (unless it + * needs UBI in RW mode), it might be faster to calculate ECC. This is weird + * example, but it real-life example. So, in this example, @vid_hdr_offer would + * be 2KiB-64 bytes = 1984. Note, that this position is not even 512-bytes + * aligned, which is OK, as UBI is clever enough to realize this is 4th + * sub-page of the first page and add needed padding. + * + * The @max_beb_per1024 is the maximum amount of bad PEBs UBI expects on the + * UBI device per 1024 eraseblocks. This value is often given in an other form + * in the NAND datasheet (min NVB i.e. minimal number of valid blocks). The + * maximum expected bad eraseblocks per 1024 is then: + * 1024 * (1 - MinNVB / MaxNVB) + * Which gives 20 for most NAND devices. This limit is used in order to derive + * amount of eraseblock UBI reserves for handling new bad blocks. If the device + * has more bad eraseblocks than this limit, UBI does not reserve any physical + * eraseblocks for new bad eraseblocks, but attempts to use available + * eraseblocks (if any). The accepted range is 0-768. If 0 is given, the + * default kernel value of %CONFIG_MTD_UBI_BEB_LIMIT will be used. */ struct ubi_attach_req { - int32_t ubi_num; - int32_t mtd_num; - int32_t vid_hdr_offset; - uint8_t padding[12]; + __s32 ubi_num; + __s32 mtd_num; + __s32 vid_hdr_offset; + __s16 max_beb_per1024; + __s8 padding[10]; }; /** @@ -212,15 +304,15 @@ struct ubi_attach_req { * BLOBs, without caring about how to properly align them. */ struct ubi_mkvol_req { - int32_t vol_id; - int32_t alignment; - int64_t bytes; - int8_t vol_type; - int8_t padding1; - int16_t name_len; - int8_t padding2[4]; + __s32 vol_id; + __s32 alignment; + __s64 bytes; + __s8 vol_type; + __s8 padding1; + __s16 name_len; + __s8 padding2[4]; char name[UBI_MAX_VOLUME_NAME + 1]; -} __attribute__ ((packed)); +} __packed; /** * struct ubi_rsvol_req - a data structure used in volume re-size requests. @@ -229,28 +321,113 @@ struct ubi_mkvol_req { * * Re-sizing is possible for both dynamic and static volumes. But while dynamic * volumes may be re-sized arbitrarily, static volumes cannot be made to be - * smaller then the number of bytes they bear. To arbitrarily shrink a static + * smaller than the number of bytes they bear. To arbitrarily shrink a static * volume, it must be wiped out first (by means of volume update operation with * zero number of bytes). */ struct ubi_rsvol_req { - int64_t bytes; - int32_t vol_id; -} __attribute__ ((packed)); + __s64 bytes; + __s32 vol_id; +} __packed; + +/** + * struct ubi_rnvol_req - volumes re-name request. + * @count: count of volumes to re-name + * @padding1: reserved for future, not used, has to be zeroed + * @vol_id: ID of the volume to re-name + * @name_len: name length + * @padding2: reserved for future, not used, has to be zeroed + * @name: new volume name + * + * UBI allows to re-name up to %32 volumes at one go. The count of volumes to + * re-name is specified in the @count field. The ID of the volumes to re-name + * and the new names are specified in the @vol_id and @name fields. + * + * The UBI volume re-name operation is atomic, which means that should power cut + * happen, the volumes will have either old name or new name. So the possible + * use-cases of this command is atomic upgrade. Indeed, to upgrade, say, volumes + * A and B one may create temporary volumes %A1 and %B1 with the new contents, + * then atomically re-name A1->A and B1->B, in which case old %A and %B will + * be removed. + * + * If it is not desirable to remove old A and B, the re-name request has to + * contain 4 entries: A1->A, A->A1, B1->B, B->B1, in which case old A1 and B1 + * become A and B, and old A and B will become A1 and B1. + * + * It is also OK to request: A1->A, A1->X, B1->B, B->Y, in which case old A1 + * and B1 become A and B, and old A and B become X and Y. + * + * In other words, in case of re-naming into an existing volume name, the + * existing volume is removed, unless it is re-named as well at the same + * re-name request. + */ +struct ubi_rnvol_req { + __s32 count; + __s8 padding1[12]; + struct { + __s32 vol_id; + __s16 name_len; + __s8 padding2[2]; + char name[UBI_MAX_VOLUME_NAME + 1]; + } ents[UBI_MAX_RNVOL]; +} __packed; /** - * struct ubi_leb_change_req - a data structure used in atomic logical - * eraseblock change requests. + * struct ubi_leb_change_req - a data structure used in atomic LEB change + * requests. * @lnum: logical eraseblock number to change * @bytes: how many bytes will be written to the logical eraseblock - * @dtype: data type (%UBI_LONGTERM, %UBI_SHORTTERM, %UBI_UNKNOWN) + * @dtype: pass "3" for better compatibility with old kernels * @padding: reserved for future, not used, has to be zeroed + * + * The @dtype field used to inform UBI about what kind of data will be written + * to the LEB: long term (value 1), short term (value 2), unknown (value 3). + * UBI tried to pick a PEB with lower erase counter for short term data and a + * PEB with higher erase counter for long term data. But this was not really + * used because users usually do not know this and could easily mislead UBI. We + * removed this feature in May 2012. UBI currently just ignores the @dtype + * field. But for better compatibility with older kernels it is recommended to + * set @dtype to 3 (unknown). */ struct ubi_leb_change_req { - int32_t lnum; - int32_t bytes; - uint8_t dtype; - uint8_t padding[7]; -} __attribute__ ((packed)); + __s32 lnum; + __s32 bytes; + __s8 dtype; /* obsolete, do not use! */ + __s8 padding[7]; +} __packed; + +/** + * struct ubi_map_req - a data structure used in map LEB requests. + * @dtype: pass "3" for better compatibility with old kernels + * @lnum: logical eraseblock number to unmap + * @padding: reserved for future, not used, has to be zeroed + */ +struct ubi_map_req { + __s32 lnum; + __s8 dtype; /* obsolete, do not use! */ + __s8 padding[3]; +} __packed; + + +/** + * struct ubi_set_vol_prop_req - a data structure used to set an UBI volume + * property. + * @property: property to set (%UBI_VOL_PROP_DIRECT_WRITE) + * @padding: reserved for future, not used, has to be zeroed + * @value: value to set + */ +struct ubi_set_vol_prop_req { + __u8 property; + __u8 padding[7]; + __u64 value; +} __packed; + +/** + * struct ubi_blkcreate_req - a data structure used in block creation requests. + * @padding: reserved for future, not used, has to be zeroed + */ +struct ubi_blkcreate_req { + __s8 padding[128]; +} __packed; #endif /* __UBI_USER_H__ */ diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h new file mode 100644 index 0000000000..7fb71f7219 --- /dev/null +++ b/include/mvebu_mmc.h @@ -0,0 +1,279 @@ +/* + * Marvell MMC/SD/SDIO driver + * + * (C) Copyright 2012 + * Marvell Semiconductor + * Written-by: Maen Suleiman, Gerald Kerma + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MVEBU_MMC_H__ +#define __MVEBU_MMC_H__ + +/* needed for the mmc_cfg definition */ +#include + +#define MMC_BLOCK_SIZE 512 + +/* + * Clock rates + */ + +#define MVEBU_MMC_CLOCKRATE_MAX 50000000 +#define MVEBU_MMC_BASE_DIV_MAX 0x7ff +#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK +#define MVEBU_MMC_BASE_FAST_CLK_100 100000000 +#define MVEBU_MMC_BASE_FAST_CLK_200 200000000 + +/* SDIO register */ +#define SDIO_SYS_ADDR_LOW 0x000 +#define SDIO_SYS_ADDR_HI 0x004 +#define SDIO_BLK_SIZE 0x008 +#define SDIO_BLK_COUNT 0x00c +#define SDIO_ARG_LOW 0x010 +#define SDIO_ARG_HI 0x014 +#define SDIO_XFER_MODE 0x018 +#define SDIO_CMD 0x01c +#define SDIO_RSP(i) (0x020 + ((i)<<2)) +#define SDIO_RSP0 0x020 +#define SDIO_RSP1 0x024 +#define SDIO_RSP2 0x028 +#define SDIO_RSP3 0x02c +#define SDIO_RSP4 0x030 +#define SDIO_RSP5 0x034 +#define SDIO_RSP6 0x038 +#define SDIO_RSP7 0x03c +#define SDIO_BUF_DATA_PORT 0x040 +#define SDIO_RSVED 0x044 +#define SDIO_HW_STATE 0x048 +#define SDIO_PRESENT_STATE0 0x048 +#define SDIO_PRESENT_STATE1 0x04c +#define SDIO_HOST_CTRL 0x050 +#define SDIO_BLK_GAP_CTRL 0x054 +#define SDIO_CLK_CTRL 0x058 +#define SDIO_SW_RESET 0x05c +#define SDIO_NOR_INTR_STATUS 0x060 +#define SDIO_ERR_INTR_STATUS 0x064 +#define SDIO_NOR_STATUS_EN 0x068 +#define SDIO_ERR_STATUS_EN 0x06c +#define SDIO_NOR_INTR_EN 0x070 +#define SDIO_ERR_INTR_EN 0x074 +#define SDIO_AUTOCMD12_ERR_STATUS 0x078 +#define SDIO_CURR_BYTE_LEFT 0x07c +#define SDIO_CURR_BLK_LEFT 0x080 +#define SDIO_AUTOCMD12_ARG_LOW 0x084 +#define SDIO_AUTOCMD12_ARG_HI 0x088 +#define SDIO_AUTOCMD12_INDEX 0x08c +#define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2)) +#define SDIO_AUTO_RSP0 0x090 +#define SDIO_AUTO_RSP1 0x094 +#define SDIO_AUTO_RSP2 0x098 +#define SDIO_CLK_DIV 0x128 + +#define WINDOW_CTRL(i) (0x108 + ((i) << 3)) +#define WINDOW_BASE(i) (0x10c + ((i) << 3)) + +/* SDIO_PRESENT_STATE */ +#define CARD_BUSY (1 << 1) +#define CMD_INHIBIT (1 << 0) +#define CMD_TXACTIVE (1 << 8) +#define CMD_RXACTIVE (1 << 9) +#define CMD_FIFO_EMPTY (1 << 13) +#define CMD_AUTOCMD12ACTIVE (1 << 14) +#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \ + CMD_RXACTIVE | \ + CMD_TXACTIVE | \ + CMD_INHIBIT | \ + CARD_BUSY) + +/* + * SDIO_CMD + */ + +#define SDIO_CMD_RSP_NONE (0 << 0) +#define SDIO_CMD_RSP_136 (1 << 0) +#define SDIO_CMD_RSP_48 (2 << 0) +#define SDIO_CMD_RSP_48BUSY (3 << 0) + +#define SDIO_CMD_CHECK_DATACRC16 (1 << 2) +#define SDIO_CMD_CHECK_CMDCRC (1 << 3) +#define SDIO_CMD_INDX_CHECK (1 << 4) +#define SDIO_CMD_DATA_PRESENT (1 << 5) +#define SDIO_UNEXPECTED_RESP (1 << 7) + +#define SDIO_CMD_INDEX(x) ((x) << 8) + +/* + * SDIO_XFER_MODE + */ + +#define SDIO_XFER_MODE_STOP_CLK (1 << 5) +#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1) +#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2) +#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3) +#define SDIO_XFER_MODE_TO_HOST (1 << 4) +#define SDIO_XFER_MODE_DMA (0 << 6) + +/* + * SDIO_HOST_CTRL + */ + +#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0) + +#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1) + +#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3) +#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4) +#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9) +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) +#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10) + +#define SDIO_HOST_CTRL_TMOUT_MAX 0xf +#define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11) +#define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11) +#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15) + +/* + * SDIO_SW_RESET + */ + +#define SDIO_SW_RESET_NOW (1 << 8) + +/* + * Normal interrupt status bits + */ + +#define SDIO_NOR_ERROR (1 << 15) +#define SDIO_NOR_UNEXP_RSP (1 << 14) +#define SDIO_NOR_AUTOCMD12_DONE (1 << 13) +#define SDIO_NOR_SUSPEND_ON (1 << 12) +#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11) +#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10) +#define SDIO_NOR_READ_WAIT_ON (1 << 9) +#define SDIO_NOR_CARD_INT (1 << 8) +#define SDIO_NOR_READ_READY (1 << 5) +#define SDIO_NOR_WRITE_READY (1 << 4) +#define SDIO_NOR_DMA_INI (1 << 3) +#define SDIO_NOR_BLK_GAP_EVT (1 << 2) +#define SDIO_NOR_XFER_DONE (1 << 1) +#define SDIO_NOR_CMD_DONE (1 << 0) + +/* + * Error status bits + */ + +#define SDIO_ERR_CRC_STATUS (1 << 14) +#define SDIO_ERR_CRC_STARTBIT (1 << 13) +#define SDIO_ERR_CRC_ENDBIT (1 << 12) +#define SDIO_ERR_RESP_TBIT (1 << 11) +#define SDIO_ERR_XFER_SIZE (1 << 10) +#define SDIO_ERR_CMD_STARTBIT (1 << 9) +#define SDIO_ERR_AUTOCMD12 (1 << 8) +#define SDIO_ERR_DATA_ENDBIT (1 << 6) +#define SDIO_ERR_DATA_CRC (1 << 5) +#define SDIO_ERR_DATA_TIMEOUT (1 << 4) +#define SDIO_ERR_CMD_INDEX (1 << 3) +#define SDIO_ERR_CMD_ENDBIT (1 << 2) +#define SDIO_ERR_CMD_CRC (1 << 1) +#define SDIO_ERR_CMD_TIMEOUT (1 << 0) +/* enable all for polling */ +#define SDIO_POLL_MASK 0xffff + +/* + * CMD12 error status bits + */ + +#define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0) +#define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1) +#define SDIO_AUTOCMD12_ERR_CRC (1 << 2) +#define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3) +#define SDIO_AUTOCMD12_ERR_INDEX (1 << 4) +#define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) +#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) + +#define MMC_RSP_PRESENT (1 << 0) +/* 136 bit response */ +#define MMC_RSP_136 (1 << 1) +/* expect valid crc */ +#define MMC_RSP_CRC (1 << 2) +/* card may send busy */ +#define MMC_RSP_BUSY (1 << 3) +/* response contains opcode */ +#define MMC_RSP_OPCODE (1 << 4) + +#define MMC_BUSMODE_OPENDRAIN 1 +#define MMC_BUSMODE_PUSHPULL 2 + +#define MMC_BUS_WIDTH_1 0 +#define MMC_BUS_WIDTH_4 2 +#define MMC_BUS_WIDTH_8 3 + +/* Can the host do 4 bit transfers */ +#define MMC_CAP_4_BIT_DATA (1 << 0) +/* Can do MMC high-speed timing */ +#define MMC_CAP_MMC_HIGHSPEED (1 << 1) +/* Can do SD high-speed timing */ +#define MMC_CAP_SD_HIGHSPEED (1 << 2) +/* Can signal pending SDIO IRQs */ +#define MMC_CAP_SDIO_IRQ (1 << 3) +/* Talks only SPI protocols */ +#define MMC_CAP_SPI (1 << 4) +/* Needs polling for card-detection */ +#define MMC_CAP_NEEDS_POLL (1 << 5) +/* Can the host do 8 bit transfers */ +#define MMC_CAP_8_BIT_DATA (1 << 6) + +/* Nonremovable e.g. eMMC */ +#define MMC_CAP_NONREMOVABLE (1 << 8) +/* Waits while card is busy */ +#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) +/* Allow erase/trim commands */ +#define MMC_CAP_ERASE (1 << 10) +/* can support DDR mode at 1.8V */ +#define MMC_CAP_1_8V_DDR (1 << 11) +/* can support DDR mode at 1.2V */ +#define MMC_CAP_1_2V_DDR (1 << 12) +/* Can power off after boot */ +#define MMC_CAP_POWER_OFF_CARD (1 << 13) +/* CMD14/CMD19 bus width ok */ +#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) +/* Host supports UHS SDR12 mode */ +#define MMC_CAP_UHS_SDR12 (1 << 15) +/* Host supports UHS SDR25 mode */ +#define MMC_CAP_UHS_SDR25 (1 << 16) +/* Host supports UHS SDR50 mode */ +#define MMC_CAP_UHS_SDR50 (1 << 17) +/* Host supports UHS SDR104 mode */ +#define MMC_CAP_UHS_SDR104 (1 << 18) +/* Host supports UHS DDR50 mode */ +#define MMC_CAP_UHS_DDR50 (1 << 19) +/* Host supports Driver Type A */ +#define MMC_CAP_DRIVER_TYPE_A (1 << 23) +/* Host supports Driver Type C */ +#define MMC_CAP_DRIVER_TYPE_C (1 << 24) +/* Host supports Driver Type D */ +#define MMC_CAP_DRIVER_TYPE_D (1 << 25) +/* CMD23 supported. */ +#define MMC_CAP_CMD23 (1 << 30) +/* Hardware reset */ +#define MMC_CAP_HW_RESET (1 << 31) + +struct mvebu_mmc_cfg { + u32 mvebu_mmc_base; + u32 mvebu_mmc_clk; + u8 max_bus_width; + struct mmc_config cfg; +}; + +/* + * Functions prototypes + */ + +int mvebu_mmc_init(bd_t *bis); + +#endif /* __MVEBU_MMC_H__ */ diff --git a/include/nand.h b/include/nand.h index 2b62ef777e..3c8dea5f87 100644 --- a/include/nand.h +++ b/include/nand.h @@ -16,16 +16,6 @@ #include -/* - * All boards using a given driver must convert to self-init - * at the same time, so do it here. When all drivers are - * converted, this will go away. - */ -#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\ - || defined(CONFIG_NAND_FSL_IFC) || defined(CONFIG_NAND_MXC) -#define CONFIG_SYS_NAND_SELF_INIT -#endif - extern void nand_init(void); #include @@ -161,3 +151,4 @@ __attribute__((noreturn)) void nand_boot(void); #define ENV_OFFSET_SIZE 8 int get_nand_env_oob(nand_info_t *nand, unsigned long *result); #endif +int spl_nand_erase_one(int block, int page); diff --git a/include/net.h b/include/net.h index faa4b50cd6..0b338ff4e6 100644 --- a/include/net.h +++ b/include/net.h @@ -3,7 +3,7 @@ * * Copyright 1994 - 2000 Neil Russell. * (See License) - * + * SPDX-License-Identifier: GPL-2.0 * * History * 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added @@ -81,7 +81,7 @@ enum eth_state_t { struct eth_device { char name[16]; unsigned char enetaddr[6]; - int iobase; + phys_addr_t iobase; int state; int (*init) (struct eth_device *, bd_t *); @@ -89,7 +89,7 @@ struct eth_device { int (*recv) (struct eth_device *); void (*halt) (struct eth_device *); #ifdef CONFIG_MCAST_TFTP - int (*mcast) (struct eth_device *, u32 ip, u8 set); + int (*mcast) (struct eth_device *, const u8 *enetaddr, u8 set); #endif int (*write_hwaddr) (struct eth_device *); struct eth_device *next; @@ -130,23 +130,6 @@ extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr); extern int eth_getenv_enetaddr_by_index(const char *base_name, int index, uchar *enetaddr); -#ifdef CONFIG_RANDOM_MACADDR -/* - * The u-boot policy does not allow hardcoded ethernet addresses. Under the - * following circumstances a random generated address is allowed: - * - in emergency cases, where you need a working network connection to set - * the ethernet address. - * Eg. you want a rescue boot and don't have a serial port to access the - * CLI to set environment variables. - * - * In these cases, we generate a random locally administered ethernet address. - * - * Args: - * enetaddr - returns 6 byte hardware address - */ -extern void eth_random_enetaddr(uchar *enetaddr); -#endif - extern int usb_eth_initialize(bd_t *bi); extern int eth_init(bd_t *bis); /* Initialize the device */ extern int eth_send(void *packet, int length); /* Send a packet */ @@ -357,7 +340,7 @@ struct icmp_hdr { } echo; ulong gateway; struct { - ushort __unused; + ushort unused; ushort mtu; } frag; uchar data[0]; @@ -499,6 +482,36 @@ extern void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source); extern void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport, int sport, int len); +/** + * compute_ip_checksum() - Compute IP checksum + * + * @addr: Address to check (must be 16-bit aligned) + * @nbytes: Number of bytes to check (normally a multiple of 2) + * @return 16-bit IP checksum + */ +unsigned compute_ip_checksum(const void *addr, unsigned nbytes); + +/** + * add_ip_checksums() - add two IP checksums + * + * @offset: Offset of first sum (if odd we do a byte-swap) + * @sum: First checksum + * @new_sum: New checksum to add + * @return updated 16-bit IP checksum + */ +unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new_sum); + +/** + * ip_checksum_ok() - check if a checksum is correct + * + * This works by making sure the checksum sums to 0 + * + * @addr: Address to check (must be 16-bit aligned) + * @nbytes: Number of bytes to check (normally a multiple of 2) + * @return true if the checksum matches, false if not + */ +int ip_checksum_ok(const void *addr, unsigned nbytes); + /* Checksum */ extern int NetCksumOk(uchar *, int); /* Return true if cksum OK */ extern uint NetCksum(uchar *, int); /* Calculate the checksum */ @@ -677,6 +690,25 @@ static inline int is_valid_ether_addr(const u8 *addr) return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr); } +/** + * eth_random_addr - Generate software assigned random Ethernet address + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Generate a random Ethernet address (MAC) that is not multicast + * and has the local assigned bit set. + */ +static inline void eth_random_addr(uchar *addr) +{ + int i; + unsigned int seed = get_timer(0); + + for (i = 0; i < 6; i++) + addr[i] = rand_r(&seed); + + addr[0] &= 0xfe; /* clear multicast bit */ + addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ +} + /* Convert an IP address to a string */ extern void ip_to_string(IPaddr_t x, char *s); diff --git a/include/netdev.h b/include/netdev.h index a2f60b2135..c67b0646e4 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -31,12 +31,13 @@ int altera_tse_initialize(u8 dev_num, int mac_base, int at91emac_register(bd_t *bis, unsigned long iobase); int au1x00_enet_initialize(bd_t*); int ax88180_initialize(bd_t *bis); +int bcm_sf2_eth_register(bd_t *bis, u8 dev_num); int bfin_EMAC_initialize(bd_t *bis); int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface); +int designware_initialize(ulong base_addr, u32 interface); int dm9000_initialize(bd_t *bis); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); @@ -54,7 +55,6 @@ int ftmac100_initialize(bd_t *bits); int ftmac110_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); -int inca_switch_initialize(bd_t *bis); int ks8695_eth_initialize(void); int ks8851_mll_initialize(u8 dev_num, int base_addr); int lan91c96_initialize(u8 dev_num, int base_addr); @@ -65,12 +65,12 @@ int mpc512x_fec_initialize(bd_t *bis); int mpc5xxx_fec_initialize(bd_t *bis); int mpc82xx_scc_enet_initialize(bd_t *bis); int mvgbe_initialize(bd_t *bis); +int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr); int natsemi_initialize(bd_t *bis); int ne2k_register(void); int npe_initialize(bd_t *bis); int ns8382x_initialize(bd_t *bis); int pcnet_initialize(bd_t *bis); -int plb2800_eth_initialize(bd_t *bis); int ppc_4xx_eth_initialize (bd_t *bis); int rtl8139_initialize(bd_t *bis); int rtl8169_initialize(bd_t *bis); @@ -79,18 +79,22 @@ int sh_eth_initialize(bd_t *bis); int skge_initialize(bd_t *bis); int smc91111_initialize(u8 dev_num, int base_addr); int smc911x_initialize(u8 dev_num, int base_addr); -int sunxi_wemac_initialize(bd_t *bis); +int sunxi_emac_initialize(bd_t *bis); +int sunxi_gmac_initialize(bd_t *bis); int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, unsigned long dma_addr); +int xilinx_emaclite_of_init(const void *blob); int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, unsigned long ctrl_addr); -int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio); +int zynq_gem_of_init(const void *blob); +int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, + int phy_addr, u32 emio); /* * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface * exported by a public hader file, we need a global definition at this point. diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h deleted file mode 100644 index 8c8f2385ee..0000000000 --- a/include/nios2-epcs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * Altera Nios-II EPCS Controller Core interfaces - ************************************************************************/ - -#ifndef __NIOS2_EPCS_H__ -#define __NIOS2_EPCS_H__ - -typedef struct epcs_devinfo_t { - const char *name; /* Device name */ - unsigned char id; /* Device silicon id */ - unsigned char size; /* Total size log2(bytes)*/ - unsigned char num_sects; /* Number of sectors */ - unsigned char sz_sect; /* Sector size log2(bytes) */ - unsigned char sz_page; /* Page size log2(bytes) */ - unsigned char prot_mask; /* Protection mask */ -}epcs_devinfo_t; - -/* Resets the epcs controller -- to prevent (potential) soft-reset - * problems when booting from the epcs controller - */ -extern int epcs_reset (void); - -/* Returns the devinfo struct if EPCS device is found; - * NULL otherwise. - */ -extern epcs_devinfo_t *epcs_dev_find (void); - -/* Returns the number of bytes used by config data. - * Negative on error. - */ -extern int epcs_cfgsz (void); - -/* Erase sectors 'start' to 'end' - return zero on success - */ -extern int epcs_erase (unsigned start, unsigned end); - -/* Read 'cnt' bytes from device offset 'off' into buf at 'addr' - * Zero return on success - */ -extern int epcs_read (ulong addr, ulong off, ulong cnt); - -/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'. - * Zero return on success - */ -extern int epcs_write (ulong addr, ulong off, ulong cnt); - -/* Verify 'cnt' bytes at device offset 'off' comparing with buf - * at 'addr'. On failure, write first invalid offset to *err. - * Zero return on success - */ -extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err); - -#endif /* __NIOS2_EPCS_H__ */ diff --git a/include/nios2-io.h b/include/nios2-io.h deleted file mode 100644 index 6f1ae50314..0000000000 --- a/include/nios2-io.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * Altera Nios2 Standard Peripherals - ************************************************************************/ - -#ifndef __NIOS2IO_H__ -#define __NIOS2IO_H__ - -/*------------------------------------------------------------------------ - * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_uart_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned divisor; /* Baud rate divisor reg */ - unsigned endofpacket; /* End-of-packet reg */ -}nios_uart_t; - -/* status register */ -#define NIOS_UART_PE (1 << 0) /* parity error */ -#define NIOS_UART_FE (1 << 1) /* frame error */ -#define NIOS_UART_BRK (1 << 2) /* break detect */ -#define NIOS_UART_ROE (1 << 3) /* rx overrun */ -#define NIOS_UART_TOE (1 << 4) /* tx overrun */ -#define NIOS_UART_TMT (1 << 5) /* tx empty */ -#define NIOS_UART_TRDY (1 << 6) /* tx ready */ -#define NIOS_UART_RRDY (1 << 7) /* rx ready */ -#define NIOS_UART_E (1 << 8) /* exception */ -#define NIOS_UART_DCTS (1 << 10) /* cts change */ -#define NIOS_UART_CTS (1 << 11) /* cts */ -#define NIOS_UART_EOP (1 << 12) /* eop detected */ - -/* control register */ -#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ -#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ -#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ -#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ -#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_UART_IE (1 << 8) /* exception int ena */ -#define NIOS_UART_TBRK (1 << 9) /* transmit break */ -#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ -#define NIOS_UART_RTS (1 << 11) /* rts */ -#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ - - -/*------------------------------------------------------------------------ - * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_timer_t { - unsigned status; /* Timer status reg */ - unsigned control; /* Timer control reg */ - unsigned periodl; /* Timeout period low */ - unsigned periodh; /* Timeout period high */ - unsigned snapl; /* Snapshot low */ - unsigned snaph; /* Snapshot high */ -}nios_timer_t; - -/* status register */ -#define NIOS_TIMER_TO (1 << 0) /* Timeout */ -#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ - -/* control register */ -#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ -#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ -#define NIOS_TIMER_START (1 << 2) /* Start timer */ -#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ - - -/*------------------------------------------------------------------------ - * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_pio_t { - unsigned int data; /* Data value at each PIO in/out */ - unsigned int direction; /* Data direct. for each PIO bit */ - unsigned int interruptmask; /* Per-bit IRQ enable/disable */ - unsigned int edgecapture; /* Per-bit sync. edge detect & hold */ -}nios_pio_t; - -/* direction register */ -#define NIOS_PIO_OUT (1) /* PIO bit is output */ -#define NIOS_PIO_IN (0) /* PIO bit is input */ - - -/*------------------------------------------------------------------------ - * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_spi_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned reserved; /* (master only) */ - unsigned slaveselect; /* SPI slave select mask (master only) */ -}nios_spi_t; - -/* status register */ -#define NIOS_SPI_ROE (1 << 3) /* rx overrun */ -#define NIOS_SPI_TOE (1 << 4) /* tx overrun */ -#define NIOS_SPI_TMT (1 << 5) /* tx empty */ -#define NIOS_SPI_TRDY (1 << 6) /* tx ready */ -#define NIOS_SPI_RRDY (1 << 7) /* rx ready */ -#define NIOS_SPI_E (1 << 8) /* exception */ - -/* control register */ -#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_SPI_IE (1 << 8) /* exception int ena */ -#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ - -/*------------------------------------------------------------------------ - * JTAG UART - *----------------------------------------------------------------------*/ -typedef volatile struct nios_jtag_t { - unsigned data; /* Data register */ - unsigned control; /* Control register */ -}nios_jtag_t; - -/* data register */ -#define NIOS_JTAG_RVALID (1<<15) /* Read valid */ -#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */ -#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ - -/* control register */ -#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ -#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ -#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ -#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ -#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ -#define NIOS_JTAG_RRDY (1 << 12) /* read available */ -#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ - -/*------------------------------------------------------------------------ - * SYSTEM ID - *----------------------------------------------------------------------*/ -typedef volatile struct nios_sysid_t { - unsigned id; /* The system build id*/ - unsigned timestamp; /* Timestamp */ -}nios_sysid_t; - -#endif /* __NIOS2IO_H__ */ diff --git a/include/nios2-yanu.h b/include/nios2-yanu.h deleted file mode 100644 index 6c16f5b454..0000000000 --- a/include/nios2-yanu.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2006, Imagos S.a.s - * Renato Andreola - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * Altera NiosII YANU serial interface by Imagos - * please see http://www.opencores.org/project,yanu for - * information/downloads - ************************************************************************/ - -#ifndef __NIOS2_YANU_H__ -#define __NIOS2_YANU_H__ - -#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ -#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ -#define YANU_FIFO_SIZE (16) -#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) -#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) - -#define YANU_RXFIFO_DLY (10*11) -#define YANU_TXFIFO_THR (10) -#define YANU_DATA_CHAR_MASK (0xFF) - -/* data register */ -#define YANU_DATA_OFFSET (0) /* data register offset */ - -#define YANU_CONTROL_OFFSET (4) /* control register offset */ -/* interrupt enable */ -#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ -#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ -#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ -#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ -#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ -#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ -/* control bits */ -#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ -#define YANU_CONTROL_BITS (1< +#ifdef CONFIG_DM_SERIAL +/* + * For driver model we always use one byte per register, and sort out the + * differences in the driver + */ +#define CONFIG_SYS_NS16550_REG_SIZE (-1) +#endif + #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) #error "Please define NS16550 registers size." #elif defined(CONFIG_SYS_NS16550_MEM32) @@ -37,6 +45,21 @@ unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; #endif +/** + * struct ns16550_platdata - information about a NS16550 port + * + * @base: Base register address + * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @clock: UART base clock speed in Hz + */ +struct ns16550_platdata { + unsigned long base; + int reg_shift; + int clock; +}; + +struct udevice; + struct NS16550 { UART_REG(rbr); /* 0 */ UART_REG(ier); /* 1 */ @@ -64,8 +87,9 @@ struct NS16550 { UART_REG(uasr); /* F */ UART_REG(scr); /* 10*/ UART_REG(ssr); /* 11*/ - UART_REG(reg12); /* 12*/ - UART_REG(osc_12m_sel); /* 13*/ +#endif +#ifdef CONFIG_DM_SERIAL + struct ns16550_platdata *plat; #endif }; @@ -100,6 +124,7 @@ typedef struct NS16550 *NS16550_t; #define UART_MCR_OUT1 0x04 /* Out 1 */ #define UART_MCR_OUT2 0x08 /* Out 2 */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ #define UART_MCR_DMA_EN 0x04 #define UART_MCR_TX_DFR 0x08 @@ -163,11 +188,6 @@ typedef struct NS16550 *NS16550_t; #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -#ifdef CONFIG_OMAP1510 -#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */ -#endif - /* useful defaults for LCR */ #define UART_LCR_8N1 0x03 @@ -176,3 +196,43 @@ void NS16550_putc(NS16550_t com_port, char c); char NS16550_getc(NS16550_t com_port); int NS16550_tstc(NS16550_t com_port); void NS16550_reinit(NS16550_t com_port, int baud_divisor); + +/** + * ns16550_calc_divisor() - calculate the divisor given clock and baud rate + * + * Given the UART input clock and required baudrate, calculate the divisor + * that should be used. + * + * @port: UART port + * @clock: UART input clock speed in Hz + * @baudrate: Required baud rate + * @return baud rate divisor that should be used + */ +int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); + +/** + * ns16550_serial_ofdata_to_platdata() - convert DT to platform data + * + * Decode a device tree node for an ns16550 device. This includes the + * register base address and register shift properties. The caller must set + * up the clock frequency. + * + * @dev: dev to decode platform data for + * @return: 0 if OK, -EINVAL on error + */ +int ns16550_serial_ofdata_to_platdata(struct udevice *dev); + +/** + * ns16550_serial_probe() - probe a serial port + * + * This sets up the serial port ready for use, except for the baud rate + * @return 0, or -ve on error + */ +int ns16550_serial_probe(struct udevice *dev); + +/** + * struct ns16550_serial_ops - ns16550 serial operations + * + * These should be used by the client driver for the driver's 'ops' member + */ +extern const struct dm_serial_ops ns16550_serial_ops; diff --git a/include/os.h b/include/os.h index 8665f70edb..e3645e0116 100644 --- a/include/os.h +++ b/include/os.h @@ -11,6 +11,8 @@ #ifndef __OS_H__ #define __OS_H__ +#include + struct sandbox_state; /** @@ -81,6 +83,14 @@ int os_open(const char *pathname, int flags); */ int os_close(int fd); +/** + * Access to the OS unlink() system call + * + * \param pathname Path of file to delete + * \return 0 for success, other for error + */ +int os_unlink(const char *pathname); + /** * Access to the OS exit() system call * @@ -93,8 +103,12 @@ void os_exit(int exit_code) __attribute__((noreturn)); /** * Put tty into raw mode to mimic serial console better + * + * @param fd File descriptor of stdin (normally 0) + * @param allow_sigs Allow Ctrl-C, Ctrl-Z to generate signals rather than + * be handled by U-Boot */ -void os_tty_raw(int fd); +void os_tty_raw(int fd, bool allow_sigs); /** * Acquires some memory from the underlying os. @@ -104,6 +118,35 @@ void os_tty_raw(int fd); */ void *os_malloc(size_t length); +/** + * Free memory previous allocated with os_malloc()/os_realloc() + * + * This returns the memory to the OS. + * + * \param ptr Pointer to memory block to free + */ +void os_free(void *ptr); + +/** + * Reallocate previously-allocated memory to increase/decrease space + * + * This works in a similar way to the C library realloc() function. If + * length is 0, then ptr is freed. Otherwise the space used by ptr is + * expanded or reduced depending on whether length is larger or smaller + * than before. + * + * If ptr is NULL, then this is similar to calling os_malloc(). + * + * This function may need to move the memory block to make room for any + * extra space, in which case the new pointer is returned. + * + * \param ptr Pointer to memory block to reallocate + * \param length New length for memory block + * \return pointer to new memory block, or NULL on failure or if length + * is 0. + */ +void *os_realloc(void *ptr, size_t length); + /** * Access to the usleep function of the os * @@ -116,7 +159,7 @@ void os_usleep(unsigned long usec); * * \return A monotonic increasing time scaled in nano seconds */ -u64 os_get_nsec(void); +uint64_t os_get_nsec(void); /** * Parse arguments and update sandbox state. @@ -174,8 +217,64 @@ const char *os_dirent_get_typename(enum os_dirent_t type); * Get the size of a file * * @param fname Filename to check - * @return size of file, or -1 if an error ocurred + * @param size size of file is returned if no error + * @return 0 on success or -1 if an error ocurred + */ +int os_get_filesize(const char *fname, loff_t *size); + +/** + * Write a character to the controlling OS terminal + * + * This bypasses the U-Boot console support and writes directly to the OS + * stdout file descriptor. + * + * @param ch Character to write + */ +void os_putc(int ch); + +/** + * Write a string to the controlling OS terminal + * + * This bypasses the U-Boot console support and writes directly to the OS + * stdout file descriptor. + * + * @param str String to write (note that \n is not appended) + */ +void os_puts(const char *str); + +/** + * Write the sandbox RAM buffer to a existing file + * + * @param fname Filename to write memory to (simple binary format) + * @return 0 if OK, -ve on error + */ +int os_write_ram_buf(const char *fname); + +/** + * Read the sandbox RAM buffer from an existing file + * + * @param fname Filename containing memory (simple binary format) + * @return 0 if OK, -ve on error + */ +int os_read_ram_buf(const char *fname); + +/** + * Jump to a new executable image + * + * This uses exec() to run a new executable image, after putting it in a + * temporary file. The same arguments and environment are passed to this + * new image, with the addition of: + * + * -j Specifies the filename the image was written to. The + * calling image may want to delete this at some point. + * -m Specifies the file containing the sandbox memory + * (ram_buf) from this image, so that the new image can + * have access to this. It also means that the original + * memory filename passed to U-Boot will be left intact. + * + * @param dest Buffer containing executable image + * @param size Size of buffer */ -ssize_t os_get_filesize(const char *fname); +int os_jump_to_image(const void *dest, int size); #endif diff --git a/include/palmas.h b/include/palmas.h index f74f08e2d8..cca3f9a9d1 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -24,6 +24,10 @@ #define LDO1_CTRL 0x50 #define LDO1_VOLTAGE 0x51 +/* LDO2 control/voltage */ +#define LDO2_CTRL 0x52 +#define LDO2_VOLTAGE 0x53 + /* LDO9 control/voltage */ #define LDO9_CTRL 0x60 #define LDO9_VOLTAGE 0x61 @@ -31,6 +35,7 @@ /* LDOUSB control/voltage */ #define LDOUSB_CTRL 0x64 #define LDOUSB_VOLTAGE 0x65 +#define LDO_CTRL 0x6a /* Control of 32 kHz audio clock */ #define CLK32KGAUDIO_CTRL 0xd5 @@ -62,6 +67,10 @@ #define SMPS9_CTRL 0x38 #define SMPS9_VOLTAGE 0x3b +/* SMPS10_CTRL */ +#define SMPS10_CTRL 0x3c +#define SMPS10_MODE_ACTIVE_D 0x0d + /* Bit field definitions for SMPSx_CTRL */ #define SMPS_MODE_ACT_AUTO 1 #define SMPS_MODE_ACT_ECO 2 @@ -114,5 +123,6 @@ int palmas_mmc1_poweron_ldo(void); int twl603x_mmc1_set_ldo9(u8 vsel); int twl603x_audio_power(u8 on); int twl603x_enable_bb_charge(u8 bb_fields); +int palmas_enable_ss_ldo(void); #endif /* PALMAS_H */ diff --git a/include/parade.h b/include/parade.h new file mode 100644 index 0000000000..887f56dcf2 --- /dev/null +++ b/include/parade.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * Donghwa Lee + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PARADE_H__ +#define __PARADE_H__ + +/* Initialize the Parade dP<->LVDS bridge if present */ +#ifdef CONFIG_VIDEO_PARADE +int parade_init(const void *blob); +#else +static inline int parade_init(const void *blob) { return -1; } +#endif + +#endif /* __PARADE_H__ */ diff --git a/include/part.h b/include/part.h index ff62407d05..8ea9b3049a 100644 --- a/include/part.h +++ b/include/part.h @@ -2,12 +2,13 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PART_H #define _PART_H #include +#include typedef struct block_dev_desc { int if_type; /* type of the interface */ @@ -58,6 +59,8 @@ typedef struct block_dev_desc { #define IF_TYPE_MMC 6 #define IF_TYPE_SD 7 #define IF_TYPE_SATA 8 +#define IF_TYPE_HOST 9 +#define IF_TYPE_MAX 10 /* Max number of IF_TYPE_* supported */ /* Part types */ #define PART_TYPE_UNKNOWN 0x00 @@ -100,8 +103,11 @@ block_dev_desc_t* sata_get_dev(int dev); block_dev_desc_t* scsi_get_dev(int dev); block_dev_desc_t* usb_stor_get_dev(int dev); block_dev_desc_t* mmc_get_dev(int dev); +int mmc_select_hwpart(int dev_num, int hwpart); block_dev_desc_t* systemace_get_dev(int dev); block_dev_desc_t* mg_disk_get_dev(int dev); +block_dev_desc_t *host_get_dev(int dev); +int host_get_dev_err(int dev, block_dev_desc_t **blk_devp); /* disk/part.c */ int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); @@ -121,8 +127,10 @@ static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; } +static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; } static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; } +static inline block_dev_desc_t *host_get_dev(int dev) { return NULL; } static inline int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info) { return -1; } @@ -172,6 +180,17 @@ int test_part_amiga (block_dev_desc_t *dev_desc); #include /* disk/part_efi.c */ int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +/** + * get_partition_info_efi_by_name() - Find the specified GPT partition table entry + * + * @param dev_desc - block device descriptor + * @param gpt_name - the specified table entry name + * @param info - returns the disk partition info + * + * @return - '0' on match, '-1' on no match, otherwise error + */ +int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc, + const char *name, disk_partition_t *info); void print_part_efi (block_dev_desc_t *dev_desc); int test_part_efi (block_dev_desc_t *dev_desc); @@ -225,6 +244,26 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h, */ int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid, disk_partition_t *partitions, const int parts_count); + +/** + * is_valid_gpt_buf() - Ensure that the Primary GPT information is valid + * + * @param dev_desc - block device descriptor + * @param buf - buffer which contains the MBR and Primary GPT info + * + * @return - '0' on success, otherwise error + */ +int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf); + +/** + * write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT + * + * @param dev_desc - block device descriptor + * @param buf - buffer which contains the MBR and Primary GPT info + * + * @return - '0' on success, otherwise error + */ +int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf); #endif #endif /* _PART_H */ diff --git a/include/part_efi.h b/include/part_efi.h index 33cd3be75c..d68ef3bb37 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -2,7 +2,7 @@ * Copyright (C) 2008 RuggedCom, Inc. * Richard Retanubun * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* diff --git a/include/pci.h b/include/pci.h index 01002a430c..4fbb8f6729 100644 --- a/include/pci.h +++ b/include/pci.h @@ -410,17 +410,15 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ -#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ -#define PCI_LTSSM_L0 0x16 /* L0 state */ +#define PCI_FIND_CAP_TTL 0x48 +#define CAP_START_POS 0x40 /* Include the ID list */ #include +#ifndef __ASSEMBLY__ + #ifdef CONFIG_SYS_PCI_64BIT typedef u64 pci_addr_t; typedef u64 pci_size_t; @@ -625,6 +623,7 @@ extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); +extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); @@ -654,14 +653,58 @@ extern int pci_hose_config_device(struct pci_controller *hose, pci_addr_t mem, unsigned long command); +extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, + int cap); +extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, + u8 hdr_type); +extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, + int cap); + +#ifdef CONFIG_PCI_FIXUP_DEV +extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, + unsigned short vendor, + unsigned short device, + unsigned short class); +#endif + const char * pci_class_str(u8 class); int pci_last_busno(void); -#ifdef CONFIG_MPC824X -extern void pci_mpc824x_init (struct pci_controller *hose); -#endif - #ifdef CONFIG_MPC85xx extern void pci_mpc85xx_init (struct pci_controller *hose); #endif -#endif /* _PCI_H */ + +/** + * pci_write_bar32() - Write the address of a BAR including control bits + * + * This writes a raw address (with control bits) to a bar + * + * @hose: PCI hose to use + * @dev: PCI device to update + * @barnum: BAR number (0-5) + * @addr: BAR address with control bits + */ +void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, + u32 addr_and_ctrl); + +/** + * pci_read_bar32() - read the address of a bar + * + * @hose: PCI hose to use + * @dev: PCI device to inspect + * @barnum: BAR number (0-5) + * @return address of the bar, masking out any control bits + * */ +u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); + +/** + * pciauto_setup_rom() - Set up access to a device ROM + * + * @hose: PCI hose to use + * @dev: PCI device to adjust + * @return 0 if done, -ve on error + */ +int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev); + +#endif /* __ASSEMBLY__ */ +#endif /* _PCI_H */ diff --git a/include/pci_ids.h b/include/pci_ids.h index 2c6dfd4044..26f4748685 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -526,7 +526,19 @@ #define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302 #define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303 #define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304 -#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603 +#define PCI_DEVICE_ID_AMD_15H_M10H_F3 0x1403 +#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d +#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e +#define PCI_DEVICE_ID_AMD_15H_NB_F0 0x1600 +#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 +#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 +#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603 +#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604 +#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605 +#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533 +#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534 +#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583 +#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584 #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 @@ -569,8 +581,9 @@ #define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A #define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081 #define PCI_DEVICE_ID_AMD_LX_AES 0x2082 -#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c #define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800 +#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b +#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 @@ -616,6 +629,8 @@ #define PCI_DEVICE_ID_MATROX_G550 0x2527 #define PCI_DEVICE_ID_MATROX_VIA 0x4536 +#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS 0x14f2 + #define PCI_VENDOR_ID_CT 0x102c #define PCI_DEVICE_ID_CT_69000 0x00c0 #define PCI_DEVICE_ID_CT_65545 0x00d8 @@ -724,6 +739,7 @@ #define PCI_DEVICE_ID_SI_7018 0x7018 #define PCI_VENDOR_ID_HP 0x103c +#define PCI_VENDOR_ID_HP_3PAR 0x1590 #define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005 #define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006 #define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008 @@ -755,6 +771,8 @@ #define PCI_DEVICE_ID_HP_CISSD 0x3238 #define PCI_DEVICE_ID_HP_CISSE 0x323a #define PCI_DEVICE_ID_HP_CISSF 0x323b +#define PCI_DEVICE_ID_HP_CISSH 0x323c +#define PCI_DEVICE_ID_HP_CISSI 0x3239 #define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 #define PCI_VENDOR_ID_PCTECH 0x1042 @@ -779,6 +797,29 @@ #define PCI_DEVICE_ID_ELSA_QS3000 0x3000 #define PCI_VENDOR_ID_STMICRO 0x104A +#define PCI_DEVICE_ID_STMICRO_USB_HOST 0xCC00 +#define PCI_DEVICE_ID_STMICRO_USB_OHCI 0xCC01 +#define PCI_DEVICE_ID_STMICRO_USB_OTG 0xCC02 +#define PCI_DEVICE_ID_STMICRO_UART_HWFC 0xCC03 +#define PCI_DEVICE_ID_STMICRO_UART_NO_HWFC 0xCC04 +#define PCI_DEVICE_ID_STMICRO_SOC_DMA 0xCC05 +#define PCI_DEVICE_ID_STMICRO_SATA 0xCC06 +#define PCI_DEVICE_ID_STMICRO_I2C 0xCC07 +#define PCI_DEVICE_ID_STMICRO_SPI_HS 0xCC08 +#define PCI_DEVICE_ID_STMICRO_MAC 0xCC09 +#define PCI_DEVICE_ID_STMICRO_SDIO_EMMC 0xCC0A +#define PCI_DEVICE_ID_STMICRO_SDIO 0xCC0B +#define PCI_DEVICE_ID_STMICRO_GPIO 0xCC0C +#define PCI_DEVICE_ID_STMICRO_VIP 0xCC0D +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA 0xCC0E +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS 0xCC0F +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS 0xCC10 +#define PCI_DEVICE_ID_STMICRO_CAN 0xCC11 +#define PCI_DEVICE_ID_STMICRO_MLB 0xCC12 +#define PCI_DEVICE_ID_STMICRO_DBP 0xCC13 +#define PCI_DEVICE_ID_STMICRO_SATA_PHY 0xCC14 +#define PCI_DEVICE_ID_STMICRO_ESRAM 0xCC15 +#define PCI_DEVICE_ID_STMICRO_VIC 0xCC16 #define PCI_VENDOR_ID_BUSLOGIC 0x104B #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 @@ -1294,6 +1335,8 @@ #define PCI_VENDOR_ID_TUNDRA 0x10e3 #define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 +#define PCI_VENDOR_ID_AMCC 0x10e8 + #define PCI_VENDOR_ID_INTERG 0x10ea #define PCI_DEVICE_ID_INTERG_1682 0x1682 #define PCI_DEVICE_ID_INTERG_2000 0x2000 @@ -1322,6 +1365,7 @@ #define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041 #define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042 #define PCI_SUBDEVICE_ID_CREATIVE_SB08803 0x0043 +#define PCI_SUBDEVICE_ID_CREATIVE_SB1270 0x0062 #define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX 0x6000 #define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */ @@ -1411,6 +1455,7 @@ #define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581 #define PCI_DEVICE_ID_VIA_VX800 0x8353 #define PCI_DEVICE_ID_VIA_VX855 0x8409 +#define PCI_DEVICE_ID_VIA_VX900 0x8410 #define PCI_DEVICE_ID_VIA_8371_1 0x8391 #define PCI_DEVICE_ID_VIA_82C598_1 0x8598 #define PCI_DEVICE_ID_VIA_838X_1 0xB188 @@ -1551,6 +1596,8 @@ #define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 #define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 #define PCI_DEVICE_ID_RICOH_R5C822 0x0822 +#define PCI_DEVICE_ID_RICOH_R5CE822 0xe822 +#define PCI_DEVICE_ID_RICOH_R5CE823 0xe823 #define PCI_DEVICE_ID_RICOH_R5C832 0x0832 #define PCI_DEVICE_ID_RICOH_R5C843 0x0843 @@ -1586,6 +1633,7 @@ #define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 #define PCI_VENDOR_ID_MARVELL 0x11ab +#define PCI_VENDOR_ID_MARVELL_EXT 0x1b4b #define PCI_DEVICE_ID_MARVELL_GT64111 0x4146 #define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 #define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 @@ -1798,6 +1846,8 @@ #define PCI_VENDOR_ID_ESDGMBH 0x12fe #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111 +#define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */ + #define PCI_VENDOR_ID_SIIG 0x131f #define PCI_SUBVENDOR_ID_SIIG 0x131f #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 @@ -1860,8 +1910,23 @@ #define PCI_VENDOR_ID_QUATECH 0x135C #define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 #define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 +#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 +#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 #define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 #define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 +#define PCI_DEVICE_ID_QUATECH_QSCP100 0x0120 +#define PCI_DEVICE_ID_QUATECH_DSCP100 0x0130 +#define PCI_DEVICE_ID_QUATECH_QSCP200 0x0140 +#define PCI_DEVICE_ID_QUATECH_DSCP200 0x0150 +#define PCI_DEVICE_ID_QUATECH_QSCLP100 0x0170 +#define PCI_DEVICE_ID_QUATECH_DSCLP100 0x0180 +#define PCI_DEVICE_ID_QUATECH_DSC100E 0x0181 +#define PCI_DEVICE_ID_QUATECH_SSCLP100 0x0190 +#define PCI_DEVICE_ID_QUATECH_QSCLP200 0x01A0 +#define PCI_DEVICE_ID_QUATECH_DSCLP200 0x01B0 +#define PCI_DEVICE_ID_QUATECH_DSC200E 0x01B1 +#define PCI_DEVICE_ID_QUATECH_SSCLP200 0x01C0 +#define PCI_DEVICE_ID_QUATECH_ESCLP100 0x01E0 #define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278 #define PCI_VENDOR_ID_SEALEVEL 0x135e @@ -1978,6 +2043,9 @@ #define PCI_DEVICE_ID_EXAR_XR17C152 0x0152 #define PCI_DEVICE_ID_EXAR_XR17C154 0x0154 #define PCI_DEVICE_ID_EXAR_XR17C158 0x0158 +#define PCI_DEVICE_ID_EXAR_XR17V352 0x0352 +#define PCI_DEVICE_ID_EXAR_XR17V354 0x0354 +#define PCI_DEVICE_ID_EXAR_XR17V358 0x0358 #define PCI_VENDOR_ID_MICROGATE 0x13c0 #define PCI_DEVICE_ID_MICROGATE_USC 0x0010 @@ -2002,6 +2070,10 @@ #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 +#define PCI_VENDOR_ID_ADVANTECH 0x13fe + +#define PCI_VENDOR_ID_MEILHAUS 0x1402 + #define PCI_VENDOR_ID_LAVA 0x1407 #define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ #define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ @@ -2047,6 +2119,8 @@ #define PCI_VENDOR_ID_CHELSIO 0x1425 +#define PCI_VENDOR_ID_ADLINK 0x144a + #define PCI_VENDOR_ID_SAMSUNG 0x144d #define PCI_VENDOR_ID_GIGABYTE 0x1458 @@ -2080,6 +2154,8 @@ #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150 +#define PCI_VENDOR_ID_AMPLICON 0x14dc + #define PCI_VENDOR_ID_BCM_GVC 0x14a4 #define PCI_VENDOR_ID_BROADCOM 0x14e4 #define PCI_DEVICE_ID_TIGON3_5752 0x1600 @@ -2100,19 +2176,25 @@ #define PCI_DEVICE_ID_NX2_57711E 0x1650 #define PCI_DEVICE_ID_TIGON3_5705 0x1653 #define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 +#define PCI_DEVICE_ID_TIGON3_5719 0x1657 #define PCI_DEVICE_ID_TIGON3_5721 0x1659 #define PCI_DEVICE_ID_TIGON3_5722 0x165a #define PCI_DEVICE_ID_TIGON3_5723 0x165b #define PCI_DEVICE_ID_TIGON3_5705M 0x165d #define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e +#define PCI_DEVICE_ID_NX2_57712 0x1662 +#define PCI_DEVICE_ID_NX2_57712E 0x1663 +#define PCI_DEVICE_ID_NX2_57712_MF 0x1663 #define PCI_DEVICE_ID_TIGON3_5714 0x1668 #define PCI_DEVICE_ID_TIGON3_5714S 0x1669 #define PCI_DEVICE_ID_TIGON3_5780 0x166a #define PCI_DEVICE_ID_TIGON3_5780S 0x166b #define PCI_DEVICE_ID_TIGON3_5705F 0x166e +#define PCI_DEVICE_ID_NX2_57712_VF 0x166f #define PCI_DEVICE_ID_TIGON3_5754M 0x1672 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673 #define PCI_DEVICE_ID_TIGON3_5756 0x1674 +#define PCI_DEVICE_ID_TIGON3_5750 0x1676 #define PCI_DEVICE_ID_TIGON3_5751 0x1677 #define PCI_DEVICE_ID_TIGON3_5715 0x1678 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679 @@ -2124,6 +2206,9 @@ #define PCI_DEVICE_ID_TIGON3_5761E 0x1680 #define PCI_DEVICE_ID_TIGON3_5761 0x1681 #define PCI_DEVICE_ID_TIGON3_5764 0x1684 +#define PCI_DEVICE_ID_NX2_57800 0x168a +#define PCI_DEVICE_ID_NX2_57840 0x168d +#define PCI_DEVICE_ID_NX2_57810 0x168e #define PCI_DEVICE_ID_TIGON3_5787M 0x1693 #define PCI_DEVICE_ID_TIGON3_5782 0x1696 #define PCI_DEVICE_ID_TIGON3_5784 0x1698 @@ -2131,11 +2216,19 @@ #define PCI_DEVICE_ID_TIGON3_5787 0x169b #define PCI_DEVICE_ID_TIGON3_5788 0x169c #define PCI_DEVICE_ID_TIGON3_5789 0x169d +#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1 +#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2 +#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4 +#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5 #define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 #define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 #define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 +#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9 #define PCI_DEVICE_ID_NX2_5706S 0x16aa #define PCI_DEVICE_ID_NX2_5708S 0x16ac +#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad +#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae +#define PCI_DEVICE_ID_NX2_57810_VF 0x16af #define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 #define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 #define PCI_DEVICE_ID_TIGON3_5781 0x16dd @@ -2170,6 +2263,9 @@ #define PCI_DEVICE_ID_ENE_720 0x1421 #define PCI_DEVICE_ID_ENE_722 0x1422 +#define PCI_VENDOR_ID_MIPS 0x153f +#define PCI_DEVICE_ID_MIPS_MSC01 0x0001 + #define PCI_SUBVENDOR_ID_PERLE 0x155f #define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001 #define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010 @@ -2304,6 +2400,8 @@ #define PCI_VENDOR_ID_TOPSPIN 0x1867 +#define PCI_VENDOR_ID_COMMTECH 0x18f7 + #define PCI_VENDOR_ID_SILAN 0x1904 #define PCI_VENDOR_ID_RENESAS 0x1912 @@ -2313,6 +2411,11 @@ #define PCI_DEVICE_ID_RENESAS_SH7785 0x0007 #define PCI_DEVICE_ID_RENESAS_SH7786 0x0010 +#define PCI_VENDOR_ID_SOLARFLARE 0x1924 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0 0x0703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1 0x6703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B 0x0710 + #define PCI_VENDOR_ID_TDI 0x192E #define PCI_DEVICE_ID_TDI_EHCI 0x0101 @@ -2411,6 +2514,11 @@ #define PCI_VENDOR_ID_AZWAVE 0x1a3b +#define PCI_VENDOR_ID_ASMEDIA 0x1b21 + +#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8 +#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001 + #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 @@ -2460,6 +2568,9 @@ #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 +#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 +#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154 +#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00 #define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 #define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321 #define PCI_DEVICE_ID_INTEL_PXH_0 0x0329 @@ -2482,6 +2593,7 @@ #define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 #define PCI_DEVICE_ID_INTEL_82541ER 0x1078 #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c #define PCI_DEVICE_ID_INTEL_82542 0x1000 @@ -2543,6 +2655,15 @@ #define PCI_DEVICE_ID_INTEL_82441 0x1237 #define PCI_DEVICE_ID_INTEL_82380FB 0x124b #define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED 0x1531 +#define PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED 0x1532 +#define PCI_DEVICE_ID_INTEL_I210_COPPER 0x1533 +#define PCI_DEVICE_ID_INTEL_I210_SERDES 0x1536 +#define PCI_DEVICE_ID_INTEL_I210_1000BASEKX 0x1537 +#define PCI_DEVICE_ID_INTEL_I210_EXTPHY 0x1538 +#define PCI_DEVICE_ID_INTEL_I211_COPPER 0x1539 +#define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS 0x157b +#define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c #define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 #define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 #define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 @@ -2552,13 +2673,50 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA 0x1c20 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68 0x1c44 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67 0x1c46 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67 0x1c47 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65 0x1c49 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67 0x1c4a +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67 0x1c4b +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65 0x1c4c +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67 0x1c4d +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67 0x1c4e +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67 0x1c4f +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65 0x1c50 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202 0x1c52 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204 0x1c54 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206 0x1c56 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61 0x1c5c #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40 +#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40 +#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI 0x1e31 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_B75 0x1e49 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_C216 0x1e53 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_H77 0x1e4A +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM70 0x1e5e +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM75 0x1e5d +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM76 0x1e59 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM77 0x1e57 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MBL_SAMPLE 0x1e42 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_NM70 0x1e5f +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q75 0x1e48 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q77 0x1e47 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QM77 0x1e55 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QS77 0x1e56 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_SFF_SAMPLE 0x1e43 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_UM77 0x1e58 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z75 0x1e46 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z77 0x1e44 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f +#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310 +#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX 0x231f #define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 #define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 #define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 @@ -2771,8 +2929,30 @@ #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e +#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f +#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46 +#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0 +#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1 +#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4 +#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5 +#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41 +#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42 +#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43 +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44 +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45 +#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0 #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 +#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3 #define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 #define PCI_DEVICE_ID_INTEL_5100_22 0x65f6 #define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030 @@ -2811,12 +2991,21 @@ #define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 #define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a +#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186 #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 #define PCI_DEVICE_ID_INTEL_82451NX 0x84ca #define PCI_DEVICE_ID_INTEL_82454NX 0x84cb #define PCI_DEVICE_ID_INTEL_84460GX 0x84ea #define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500 +#define PCI_DEVICE_ID_INTEL_TCF_GBE 0x8802 +#define PCI_DEVICE_ID_INTEL_TCF_SDIO_0 0x8809 +#define PCI_DEVICE_ID_INTEL_TCF_SDIO_1 0x880a +#define PCI_DEVICE_ID_INTEL_TCF_SATA 0x880b +#define PCI_DEVICE_ID_INTEL_TCF_UART_0 0x8811 +#define PCI_DEVICE_ID_INTEL_TCF_UART_1 0x8812 +#define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813 +#define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814 #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 @@ -2893,7 +3082,11 @@ #define PCI_DEVICE_ID_NETMOS_9845 0x9845 #define PCI_DEVICE_ID_NETMOS_9855 0x9855 #define PCI_DEVICE_ID_NETMOS_9865 0x9865 +#define PCI_DEVICE_ID_NETMOS_9900 0x9900 #define PCI_DEVICE_ID_NETMOS_9901 0x9901 +#define PCI_DEVICE_ID_NETMOS_9904 0x9904 +#define PCI_DEVICE_ID_NETMOS_9912 0x9912 +#define PCI_DEVICE_ID_NETMOS_9922 0x9922 #define PCI_VENDOR_ID_3COM_2 0xa727 @@ -2915,3 +3108,5 @@ #define PCI_VENDOR_ID_XEN 0x5853 #define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 + +#define PCI_VENDOR_ID_OCZ 0x1b85 diff --git a/include/pci_msc01.h b/include/pci_msc01.h new file mode 100644 index 0000000000..54945a7a8f --- /dev/null +++ b/include/pci_msc01.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCI_MSC01_H__ +#define __PCI_MSC01_H__ + +extern void msc01_pci_init(void *base, unsigned long sys_bus, + unsigned long sys_phys, unsigned long sys_size, + unsigned long mem_bus, unsigned long mem_phys, + unsigned long mem_size, unsigned long io_bus, + unsigned long io_phys, unsigned long io_size); + +#endif /* __PCI_MSC01_H__ */ diff --git a/include/pci_rom.h b/include/pci_rom.h new file mode 100644 index 0000000000..4ba36eb1b7 --- /dev/null +++ b/include/pci_rom.h @@ -0,0 +1,57 @@ +/* + * From coreboot file of same name + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PCI_ROM_H +#define _PCI_ROM_H + +#define PCI_ROM_HDR 0xaa55 + +struct pci_rom_header { + uint16_t signature; + uint8_t size; + uint8_t init[3]; + uint8_t reserved[0x12]; + uint16_t data; +}; + +struct pci_rom_data { + uint32_t signature; + uint16_t vendor; + uint16_t device; + uint16_t reserved_1; + uint16_t dlen; + uint8_t drevision; + uint8_t class_lo; + uint16_t class_hi; + uint16_t ilen; + uint16_t irevision; + uint8_t type; + uint8_t indicator; + uint16_t reserved_2; +}; + + /** + * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC + * + * @dev: Video device containing the BIOS + * @int15_handler: Function to call to handle int 0x15 + * @emulate: true to use the x86 emulator, false to run native + */ +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate); + +/** + * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects + * + * Some VGA option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + * + * @vendev: Vendor and device for the video device + * @return standard vendor and device expected by the ROM + */ +uint32_t board_map_oprom_vendev(uint32_t vendev); + +#endif diff --git a/include/pcmcia.h b/include/pcmcia.h index ce8c8ed5e9..c8a730c4d0 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -21,35 +21,8 @@ #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) - /* The RPX series use SLOT_B */ -#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) -# define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_ADS) /* The ADS board uses SLOT_A */ -# define CONFIG_PCMCIA_SLOT_A -#elif defined(CONFIG_FADS) /* The FADS series are a mess */ -# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) -# define CONFIG_PCMCIA_SLOT_A -# else -# define CONFIG_PCMCIA_SLOT_B -# endif -#elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx) +#if defined(CONFIG_TQM8xxL) # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ -#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */ -# define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */ -# define CONFIG_PCMCIA_SLOT_A -#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ -# define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */ -# define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */ -# define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ -# define CONFIG_PCMCIA_SLOT_A -#elif defined(CONFIG_NETTA) -# define CONFIG_PCMCIA_SLOT_A -#elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */ -# define CONFIG_PCMCIA_SLOT_B #else # error "PCMCIA Slot not configured" #endif diff --git a/include/pcmcia/cirrus.h b/include/pcmcia/cirrus.h deleted file mode 100644 index cd34dd8560..0000000000 --- a/include/pcmcia/cirrus.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * cirrus.h 1.4 1999/10/25 20:03:34 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * . Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in which - * case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_CIRRUS_H -#define _LINUX_CIRRUS_H - -#ifndef PCI_VENDOR_ID_CIRRUS -#define PCI_VENDOR_ID_CIRRUS 0x1013 -#endif -#ifndef PCI_DEVICE_ID_CIRRUS_6729 -#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 -#endif -#ifndef PCI_DEVICE_ID_CIRRUS_6832 -#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 -#endif - -#define PD67_MISC_CTL_1 0x16 /* Misc control 1 */ -#define PD67_FIFO_CTL 0x17 /* FIFO control */ -#define PD67_MISC_CTL_2 0x1E /* Misc control 2 */ -#define PD67_CHIP_INFO 0x1f /* Chip information */ -#define PD67_ATA_CTL 0x026 /* 6730: ATA control */ -#define PD67_EXT_INDEX 0x2e /* Extension index */ -#define PD67_EXT_DATA 0x2f /* Extension data */ - -/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */ -#define PD67_DATA_MASK0 0x01 /* Data mask 0 */ -#define PD67_DATA_MASK1 0x02 /* Data mask 1 */ -#define PD67_DMA_CTL 0x03 /* DMA control */ - -/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */ -#define PD67_EXT_CTL_1 0x03 /* Extension control 1 */ -#define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */ -#define PD67_EXTERN_DATA 0x0a -#define PD67_MISC_CTL_3 0x25 -#define PD67_SMB_PWR_CTL 0x26 - -/* I/O window address offset */ -#define PD67_IO_OFF(w) (0x36+((w)<<1)) - -/* Timing register sets */ -#define PD67_TIME_SETUP(n) (0x3a + 3*(n)) -#define PD67_TIME_CMD(n) (0x3b + 3*(n)) -#define PD67_TIME_RECOV(n) (0x3c + 3*(n)) - -/* Flags for PD67_MISC_CTL_1 */ -#define PD67_MC1_5V_DET 0x01 /* 5v detect */ -#define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */ -#define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */ -#define PD67_MC1_PULSE_MGMT 0x04 -#define PD67_MC1_PULSE_IRQ 0x08 -#define PD67_MC1_SPKR_ENA 0x10 -#define PD67_MC1_INPACK_ENA 0x80 - -/* Flags for PD67_FIFO_CTL */ -#define PD67_FIFO_EMPTY 0x80 - -/* Flags for PD67_MISC_CTL_2 */ -#define PD67_MC2_FREQ_BYPASS 0x01 -#define PD67_MC2_DYNAMIC_MODE 0x02 -#define PD67_MC2_SUSPEND 0x04 -#define PD67_MC2_5V_CORE 0x08 -#define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */ -#define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */ -#define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */ -#define PD67_MC2_DMA_MODE 0x40 -#define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */ - -/* Flags for PD67_CHIP_INFO */ -#define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */ -#define PD67_INFO_CHIP_ID 0xc0 -#define PD67_INFO_REV 0x1c - -/* Fields in PD67_TIME_* registers */ -#define PD67_TIME_SCALE 0xc0 -#define PD67_TIME_SCALE_1 0x00 -#define PD67_TIME_SCALE_16 0x40 -#define PD67_TIME_SCALE_256 0x80 -#define PD67_TIME_SCALE_4096 0xc0 -#define PD67_TIME_MULT 0x3f - -/* Fields in PD67_DMA_CTL */ -#define PD67_DMA_MODE 0xc0 -#define PD67_DMA_OFF 0x00 -#define PD67_DMA_DREQ_INPACK 0x40 -#define PD67_DMA_DREQ_WP 0x80 -#define PD67_DMA_DREQ_BVD2 0xc0 -#define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */ - -/* Fields in PD67_EXT_CTL_1 */ -#define PD67_EC1_VCC_PWR_LOCK 0x01 -#define PD67_EC1_AUTO_PWR_CLEAR 0x02 -#define PD67_EC1_LED_ENA 0x04 -#define PD67_EC1_INV_CARD_IRQ 0x08 -#define PD67_EC1_INV_MGMT_IRQ 0x10 -#define PD67_EC1_PULLUP_CTL 0x20 - -/* Fields in PD67_MISC_CTL_3 */ -#define PD67_MC3_IRQ_MASK 0x03 -#define PD67_MC3_IRQ_PCPCI 0x00 -#define PD67_MC3_IRQ_EXTERN 0x01 -#define PD67_MC3_IRQ_PCIWAY 0x02 -#define PD67_MC3_IRQ_PCI 0x03 -#define PD67_MC3_PWR_MASK 0x0c -#define PD67_MC3_PWR_SERIAL 0x00 -#define PD67_MC3_PWR_TI2202 0x08 -#define PD67_MC3_PWR_SMB 0x0c - -/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */ - -/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */ -#define PD68_EXT_CTL_2 0x0b -#define PD68_PCI_SPACE 0x22 -#define PD68_PCCARD_SPACE 0x23 -#define PD68_WINDOW_TYPE 0x24 -#define PD68_EXT_CSC 0x2e -#define PD68_MISC_CTL_4 0x2f -#define PD68_MISC_CTL_5 0x30 -#define PD68_MISC_CTL_6 0x31 - -/* Extra flags in PD67_MISC_CTL_3 */ -#define PD68_MC3_HW_SUSP 0x10 -#define PD68_MC3_MM_EXPAND 0x40 -#define PD68_MC3_MM_ARM 0x80 - -/* Bridge Control Register */ -#define PD6832_BCR_MGMT_IRQ_ENA 0x0800 - -/* Socket Number Register */ -#define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */ - - -typedef struct cirrus_state_t { - u_char misc1, misc2; - u_char timer[6]; -} cirrus_state_t; - -/* Cirrus options */ -static int has_dma = -1; -static int has_led = -1; -static int has_ring = -1; -static int dynamic_mode = 0; -static int freq_bypass = -1; -#ifdef CONFIG_CPC45 -static int setup_time = 2; -static int cmd_time = 6; -static int recov_time = 1; -#else -static int setup_time = -1; -static int cmd_time = -1; -static int recov_time = -1; -#endif - - -#endif /* _LINUX_CIRRUS_H */ diff --git a/include/pcmcia/i82365.h b/include/pcmcia/i82365.h deleted file mode 100644 index 0b432a80ba..0000000000 --- a/include/pcmcia/i82365.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * i82365.h 1.21 2001/08/24 12:15:33 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * . Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in - * which case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_I82365_H -#define _LINUX_I82365_H - -/* register definitions for the Intel 82365SL PCMCIA controller */ - -/* Offsets for PCIC registers */ -#define I365_IDENT 0x00 /* Identification and revision */ -#define I365_STATUS 0x01 /* Interface status */ -#define I365_POWER 0x02 /* Power and RESETDRV control */ -#define I365_INTCTL 0x03 /* Interrupt and general control */ -#define I365_CSC 0x04 /* Card status change */ -#define I365_CSCINT 0x05 /* Card status change interrupt control */ -#define I365_ADDRWIN 0x06 /* Address window enable */ -#define I365_IOCTL 0x07 /* I/O control */ -#define I365_GENCTL 0x16 /* Card detect and general control */ -#define I365_GBLCTL 0x1E /* Global control register */ - -/* Offsets for I/O and memory window registers */ -#define I365_IO(map) (0x08+((map)<<2)) -#define I365_MEM(map) (0x10+((map)<<3)) -#define I365_W_START 0 -#define I365_W_STOP 2 -#define I365_W_OFF 4 - -/* Flags for I365_STATUS */ -#define I365_CS_BVD1 0x01 -#define I365_CS_STSCHG 0x01 -#define I365_CS_BVD2 0x02 -#define I365_CS_SPKR 0x02 -#define I365_CS_DETECT 0x0C -#define I365_CS_WRPROT 0x10 -#define I365_CS_READY 0x20 /* Inverted */ -#define I365_CS_POWERON 0x40 -#define I365_CS_GPI 0x80 - -/* Flags for I365_POWER */ -#define I365_PWR_OFF 0x00 /* Turn off the socket */ -#define I365_PWR_OUT 0x80 /* Output enable */ -#define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */ -#define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */ -#define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */ -/* There are different layouts for B-step and DF-step chips: the B - step has independent Vpp1/Vpp2 control, and the DF step has only - Vpp1 control, plus 3V control */ -#define I365_VCC_5V 0x10 /* Vcc = 5.0v */ -#define I365_VCC_3V 0x18 /* Vcc = 3.3v */ -#define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */ -#define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */ -#define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */ -#define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */ -#define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */ -#define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */ - -/* Flags for I365_INTCTL */ -#define I365_RING_ENA 0x80 -#define I365_PC_RESET 0x40 -#define I365_PC_IOCARD 0x20 -#define I365_INTR_ENA 0x10 -#define I365_IRQ_MASK 0x0F - -/* Flags for I365_CSC and I365_CSCINT*/ -#define I365_CSC_BVD1 0x01 -#define I365_CSC_STSCHG 0x01 -#define I365_CSC_BVD2 0x02 -#define I365_CSC_READY 0x04 -#define I365_CSC_DETECT 0x08 -#define I365_CSC_ANY 0x0F -#define I365_CSC_GPI 0x10 - -/* Flags for I365_ADDRWIN */ -#define I365_ADDR_MEMCS16 0x20 -#define I365_ENA_IO(map) (0x40 << (map)) -#define I365_ENA_MEM(map) (0x01 << (map)) - -/* Flags for I365_IOCTL */ -#define I365_IOCTL_MASK(map) (0x0F << (map<<2)) -#define I365_IOCTL_WAIT(map) (0x08 << (map<<2)) -#define I365_IOCTL_0WS(map) (0x04 << (map<<2)) -#define I365_IOCTL_IOCS16(map) (0x02 << (map<<2)) -#define I365_IOCTL_16BIT(map) (0x01 << (map<<2)) - -/* Flags for I365_GENCTL */ -#define I365_CTL_16DELAY 0x01 -#define I365_CTL_RESET 0x02 -#define I365_CTL_GPI_ENA 0x04 -#define I365_CTL_GPI_CTL 0x08 -#define I365_CTL_RESUME 0x10 -#define I365_CTL_SW_IRQ 0x20 - -/* Flags for I365_GBLCTL */ -#define I365_GBL_PWRDOWN 0x01 -#define I365_GBL_CSC_LEV 0x02 -#define I365_GBL_WRBACK 0x04 -#define I365_GBL_IRQ_0_LEV 0x08 -#define I365_GBL_IRQ_1_LEV 0x10 - -/* Flags for memory window registers */ -#define I365_MEM_16BIT 0x8000 /* In memory start high byte */ -#define I365_MEM_0WS 0x4000 -#define I365_MEM_WS1 0x8000 /* In memory stop high byte */ -#define I365_MEM_WS0 0x4000 -#define I365_MEM_WRPROT 0x8000 /* In offset high byte */ -#define I365_MEM_REG 0x4000 - -#define I365_REG(slot, reg) (((slot) << 6) | (reg)) - -/* Default ISA interrupt mask */ -#define I365_ISA_IRQ_MASK 0xdeb8 /* irq's 3-5,7,9-12,14,15 */ - -/* Device ID's for PCI-to-PCMCIA bridges */ - -#ifndef PCI_VENDOR_ID_INTEL -#define PCI_VENDOR_ID_INTEL 0x8086 -#endif -#ifndef PCI_DEVICE_ID_INTEL_82092AA_0 -#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 -#endif -#ifndef PCI_VENDOR_ID_OMEGA -#define PCI_VENDOR_ID_OMEGA 0x119b -#endif -#ifndef PCI_DEVICE_ID_OMEGA_82C092G -#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 -#endif - -#endif /* _LINUX_I82365_H */ diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h deleted file mode 100644 index aafae8a547..0000000000 --- a/include/pcmcia/ss.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * ss.h 1.31 2001/08/24 12:16:13 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * . Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in - * which case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_SS_H -#define _LINUX_SS_H - -/* For RegisterCallback */ -typedef struct ss_callback_t { - void (*handler)(void *info, u_int events); - void *info; -} ss_callback_t; - -/* Definitions for card status flags for GetStatus */ -#define SS_WRPROT 0x0001 -#define SS_CARDLOCK 0x0002 -#define SS_EJECTION 0x0004 -#define SS_INSERTION 0x0008 -#define SS_BATDEAD 0x0010 -#define SS_BATWARN 0x0020 -#define SS_READY 0x0040 -#define SS_DETECT 0x0080 -#define SS_POWERON 0x0100 -#define SS_GPI 0x0200 -#define SS_STSCHG 0x0400 -#define SS_CARDBUS 0x0800 -#define SS_3VCARD 0x1000 -#define SS_XVCARD 0x2000 -#define SS_PENDING 0x4000 - -/* for InquireSocket */ -typedef struct socket_cap_t { - u_int features; - u_int irq_mask; - u_int map_size; - u_char pci_irq; - u_char cardbus; - struct pci_bus *cb_bus; - struct bus_operations *bus; -} socket_cap_t; - -/* InquireSocket capabilities */ -#define SS_CAP_PAGE_REGS 0x0001 -#define SS_CAP_VIRTUAL_BUS 0x0002 -#define SS_CAP_MEM_ALIGN 0x0004 -#define SS_CAP_STATIC_MAP 0x0008 -#define SS_CAP_PCCARD 0x4000 -#define SS_CAP_CARDBUS 0x8000 - -/* for GetSocket, SetSocket */ -typedef struct socket_state_t { - u_int flags; - u_int csc_mask; - u_char Vcc, Vpp; - u_char io_irq; -} socket_state_t; - -/* Socket configuration flags */ -#define SS_PWR_AUTO 0x0010 -#define SS_IOCARD 0x0020 -#define SS_RESET 0x0040 -#define SS_DMA_MODE 0x0080 -#define SS_SPKR_ENA 0x0100 -#define SS_OUTPUT_ENA 0x0200 -#define SS_ZVCARD 0x0400 - -/* Flags for I/O port and memory windows */ -#define MAP_ACTIVE 0x01 -#define MAP_16BIT 0x02 -#define MAP_AUTOSZ 0x04 -#define MAP_0WS 0x08 -#define MAP_WRPROT 0x10 -#define MAP_ATTRIB 0x20 -#define MAP_USE_WAIT 0x40 -#define MAP_PREFETCH 0x80 - -/* Use this just for bridge windows */ -#define MAP_IOSPACE 0x20 - -typedef struct pccard_io_map { - u_char map; - u_char flags; - u_short speed; - u_short start, stop; -} pccard_io_map; - -typedef struct pccard_mem_map { - u_char map; - u_char flags; - u_short speed; - u_long sys_start, sys_stop; - u_int card_start; -} pccard_mem_map; - -typedef struct cb_bridge_map { - u_char map; - u_char flags; - u_int start, stop; -} cb_bridge_map; - -enum ss_service { - SS_RegisterCallback, SS_InquireSocket, - SS_GetStatus, SS_GetSocket, SS_SetSocket, - SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap, - SS_GetBridge, SS_SetBridge, SS_ProcSetup -}; - -#endif /* _LINUX_SS_H */ diff --git a/include/pcmcia/ti113x.h b/include/pcmcia/ti113x.h deleted file mode 100644 index 5453588d0c..0000000000 --- a/include/pcmcia/ti113x.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * ti113x.h 1.31 2002/05/12 18:19:47 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * . Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in - * which case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_TI113X_H -#define _LINUX_TI113X_H - -#ifndef PCI_VENDOR_ID_TI -#define PCI_VENDOR_ID_TI 0x104c -#endif - -#ifndef PCI_DEVICE_ID_TI_1130 -#define PCI_DEVICE_ID_TI_1130 0xac12 -#endif -#ifndef PCI_DEVICE_ID_TI_1031 -#define PCI_DEVICE_ID_TI_1031 0xac13 -#endif -#ifndef PCI_DEVICE_ID_TI_1131 -#define PCI_DEVICE_ID_TI_1131 0xac15 -#endif -#ifndef PCI_DEVICE_ID_TI_1210 -#define PCI_DEVICE_ID_TI_1210 0xac1a -#endif -#ifndef PCI_DEVICE_ID_TI_1211 -#define PCI_DEVICE_ID_TI_1211 0xac1e -#endif -#ifndef PCI_DEVICE_ID_TI_1220 -#define PCI_DEVICE_ID_TI_1220 0xac17 -#endif -#ifndef PCI_DEVICE_ID_TI_1221 -#define PCI_DEVICE_ID_TI_1221 0xac19 -#endif -#ifndef PCI_DEVICE_ID_TI_1250A -#define PCI_DEVICE_ID_TI_1250A 0xac16 -#endif -#ifndef PCI_DEVICE_ID_TI_1225 -#define PCI_DEVICE_ID_TI_1225 0xac1c -#endif -#ifndef PCI_DEVICE_ID_TI_1251A -#define PCI_DEVICE_ID_TI_1251A 0xac1d -#endif -#ifndef PCI_DEVICE_ID_TI_1251B -#define PCI_DEVICE_ID_TI_1251B 0xac1f -#endif -#ifndef PCI_DEVICE_ID_TI_1410 -#define PCI_DEVICE_ID_TI_1410 0xac50 -#endif -#ifndef PCI_DEVICE_ID_TI_1420 -#define PCI_DEVICE_ID_TI_1420 0xac51 -#endif -#ifndef PCI_DEVICE_ID_TI_1450 -#define PCI_DEVICE_ID_TI_1450 0xac1b -#endif -#ifndef PCI_DEVICE_ID_TI_1451 -#define PCI_DEVICE_ID_TI_1451 0xac52 -#endif -#ifndef PCI_DEVICE_ID_TI_1510 -#define PCI_DEVICE_ID_TI_1510 0xac56 -#endif -#ifndef PCI_DEVICE_ID_TI_4410 -#define PCI_DEVICE_ID_TI_4410 0xac41 -#endif -#ifndef PCI_DEVICE_ID_TI_4450 -#define PCI_DEVICE_ID_TI_4450 0xac40 -#endif -#ifndef PCI_DEVICE_ID_TI_4451 -#define PCI_DEVICE_ID_TI_4451 0xac42 -#endif - -/* Register definitions for TI 113X PCI-to-CardBus bridges */ - -/* System Control Register */ -#define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */ -#define TI113X_SCR_SMIROUTE 0x04000000 -#define TI113X_SCR_SMISTATUS 0x02000000 -#define TI113X_SCR_SMIENB 0x01000000 -#define TI113X_SCR_VCCPROT 0x00200000 -#define TI113X_SCR_REDUCEZV 0x00100000 -#define TI113X_SCR_CDREQEN 0x00080000 -#define TI113X_SCR_CDMACHAN 0x00070000 -#define TI113X_SCR_SOCACTIVE 0x00002000 -#define TI113X_SCR_PWRSTREAM 0x00000800 -#define TI113X_SCR_DELAYUP 0x00000400 -#define TI113X_SCR_DELAYDOWN 0x00000200 -#define TI113X_SCR_INTERROGATE 0x00000100 -#define TI113X_SCR_CLKRUN_SEL 0x00000080 -#define TI113X_SCR_PWRSAVINGS 0x00000040 -#define TI113X_SCR_SUBSYSRW 0x00000020 -#define TI113X_SCR_CB_DPAR 0x00000010 -#define TI113X_SCR_CDMA_EN 0x00000008 -#define TI113X_SCR_ASYNC_IRQ 0x00000004 -#define TI113X_SCR_KEEPCLK 0x00000002 -#define TI113X_SCR_CLKRUN_ENA 0x00000001 - -#define TI122X_SCR_SER_STEP 0xc0000000 -#define TI122X_SCR_INTRTIE 0x20000000 -#define TI122X_SCR_P2CCLK 0x08000000 -#define TI122X_SCR_CBRSVD 0x00400000 -#define TI122X_SCR_MRBURSTDN 0x00008000 -#define TI122X_SCR_MRBURSTUP 0x00004000 -#define TI122X_SCR_RIMUX 0x00000001 - -/* Multimedia Control Register */ -#define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */ -#define TI1250_MMC_ZVOUTEN 0x80 -#define TI1250_MMC_PORTSEL 0x40 -#define TI1250_MMC_ZVEN1 0x02 -#define TI1250_MMC_ZVEN0 0x01 - -#define TI1250_GENERAL_STATUS 0x85 /* 8 bit */ -#define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */ -#define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */ -#define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */ -#define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */ -#define TI12XX_IRQMUX 0x8c /* 32 bit */ - -/* Retry Status Register */ -#define TI113X_RETRY_STATUS 0x90 /* 8 bit */ -#define TI113X_RSR_PCIRETRY 0x80 -#define TI113X_RSR_CBRETRY 0x40 -#define TI113X_RSR_TEXP_CBB 0x20 -#define TI113X_RSR_MEXP_CBB 0x10 -#define TI113X_RSR_TEXP_CBA 0x08 -#define TI113X_RSR_MEXP_CBA 0x04 -#define TI113X_RSR_TEXP_PCI 0x02 -#define TI113X_RSR_MEXP_PCI 0x01 - -/* Card Control Register */ -#define TI113X_CARD_CONTROL 0x91 /* 8 bit */ -#define TI113X_CCR_RIENB 0x80 -#define TI113X_CCR_ZVENABLE 0x40 -#define TI113X_CCR_PCI_IRQ_ENA 0x20 -#define TI113X_CCR_PCI_IREQ 0x10 -#define TI113X_CCR_PCI_CSC 0x08 -#define TI113X_CCR_SPKROUTEN 0x02 -#define TI113X_CCR_IFG 0x01 - -#define TI1220_CCR_PORT_SEL 0x20 -#define TI122X_CCR_AUD2MUX 0x04 - -/* Device Control Register */ -#define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */ -#define TI113X_DCR_5V_FORCE 0x40 -#define TI113X_DCR_3V_FORCE 0x20 -#define TI113X_DCR_IMODE_MASK 0x06 -#define TI113X_DCR_IMODE_ISA 0x02 -#define TI113X_DCR_IMODE_SERIAL 0x04 - -#define TI12XX_DCR_IMODE_PCI_ONLY 0x00 -#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06 - -/* Buffer Control Register */ -#define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */ -#define TI113X_BCR_CB_READ_DEPTH 0x08 -#define TI113X_BCR_CB_WRITE_DEPTH 0x04 -#define TI113X_BCR_PCI_READ_DEPTH 0x02 -#define TI113X_BCR_PCI_WRITE_DEPTH 0x01 - -/* Diagnostic Register */ -#define TI1250_DIAGNOSTIC 0x93 /* 8 bit */ -#define TI1250_DIAG_TRUE_VALUE 0x80 -#define TI1250_DIAG_PCI_IREQ 0x40 -#define TI1250_DIAG_PCI_CSC 0x20 -#define TI1250_DIAG_ASYNC_CSC 0x01 - -/* DMA Registers */ -#define TI113X_DMA_0 0x94 /* 32 bit */ -#define TI113X_DMA_1 0x98 /* 32 bit */ - -/* ExCA IO offset registers */ -#define TI113X_IO_OFFSET(map) (0x36+((map)<<1)) - -/* Data structure for tracking vendor-specific state */ -typedef struct ti113x_state_t { - u32 sysctl; /* TI113X_SYSTEM_CONTROL */ - u8 cardctl; /* TI113X_CARD_CONTROL */ - u8 devctl; /* TI113X_DEVICE_CONTROL */ - u8 diag; /* TI1250_DIAGNOSTIC */ - u32 irqmux; /* TI12XX_IRQMUX */ -} ti113x_state_t; - -#define TI_PCIC_ID \ - IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \ - IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \ - IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \ - IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451 - -#define TI_PCIC_INFO \ - { "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \ - { "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \ - { "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \ - { "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \ - { "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \ - { "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \ - { "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \ - { "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \ - { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \ - { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \ - { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \ - { "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \ - { "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \ - { "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \ - { "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \ - { "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \ - { "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \ - { "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \ - { "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) } - -#endif /* _LINUX_TI113X_H */ diff --git a/include/phy.h b/include/phy.h index f0f522a9c2..d117fc1634 100644 --- a/include/phy.h +++ b/include/phy.h @@ -1,6 +1,6 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. - * Andy Fleming + * Andy Fleming * * SPDX-License-Identifier: GPL-2.0+ * @@ -32,13 +32,16 @@ #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ SUPPORTED_10000baseT_Full) +#ifndef PHY_ANEG_TIMEOUT #define PHY_ANEG_TIMEOUT 4000 +#endif typedef enum { PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_SGMII_2500, PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RMII, @@ -55,6 +58,7 @@ static const char *phy_interface_strings[] = { [PHY_INTERFACE_MODE_MII] = "mii", [PHY_INTERFACE_MODE_GMII] = "gmii", [PHY_INTERFACE_MODE_SGMII] = "sgmii", + [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", [PHY_INTERFACE_MODE_TBI] = "tbi", [PHY_INTERFACE_MODE_RMII] = "rmii", @@ -125,6 +129,9 @@ struct phy_driver { /* Called when bringing down the controller */ int (*shutdown)(struct phy_device *phydev); + int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); + int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, + u16 val); struct list_head list; }; @@ -160,6 +167,14 @@ struct phy_device { u32 flags; }; +struct fixed_link { + int phy_id; + int duplex; + int link_speed; + int pause; + int asym_pause; +}; + static inline int phy_read(struct phy_device *phydev, int devad, int regnum) { struct mii_dev *bus = phydev->bus; @@ -210,8 +225,10 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev); +int phy_aquantia_init(void); int phy_atheros_init(void); int phy_broadcom_init(void); +int phy_cortina_init(void); int phy_davicom_init(void); int phy_et1011c_init(void); int phy_lxt_init(void); @@ -223,7 +240,10 @@ int phy_smsc_init(void); int phy_teranetics_init(void); int phy_vitesse_init(void); +int board_phy_config(struct phy_device *phydev); + /* PHY UIDs for various PHYs that are referenced in external code */ +#define PHY_UID_CS4340 0x13e51002 #define PHY_UID_TN2020 0x00a19410 #endif diff --git a/include/post.h b/include/post.h index 24ca728b40..5ebd535823 100644 --- a/include/post.h +++ b/include/post.h @@ -38,7 +38,7 @@ #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) #elif defined(CONFIG_MPC8360) -#include +#include #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) #elif defined (CONFIG_MPC85xx) diff --git a/include/power/as3722.h b/include/power/as3722.h new file mode 100644 index 0000000000..aa966d2cca --- /dev/null +++ b/include/power/as3722.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __POWER_AS3722_H__ +#define __POWER_AS3722_H__ + +#include + +#define AS3722_GPIO_OUTPUT_VDDH (1 << 0) +#define AS3722_GPIO_INVERT (1 << 1) + +struct udevice; + +int as3722_init(struct udevice **devp); +int as3722_sd_enable(struct udevice *pmic, unsigned int sd); +int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value); +int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo); +int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value); +int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio, + unsigned long flags); +int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio, + unsigned int level); + +#endif /* __POWER_AS3722_H__ */ diff --git a/include/power/ltc3676_pmic.h b/include/power/ltc3676_pmic.h new file mode 100644 index 0000000000..dcaa985193 --- /dev/null +++ b/include/power/ltc3676_pmic.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LTC3676_PMIC_H_ +#define __LTC3676_PMIC_H_ + +/* LTC3676 registers */ +enum { + LTC3676_BUCK1 = 0x01, + LTC3676_BUCK2 = 0x02, + LTC3676_BUCK3 = 0x03, + LTC3676_BUCK4 = 0x04, + LTC3676_LDOA = 0x05, + LTC3676_LDOB = 0x06, + LTC3676_SQD1 = 0x07, + LTC3676_SQD2 = 0x08, + LTC3676_CNTRL = 0x09, + LTC3676_DVB1A = 0x0A, + LTC3676_DVB1B = 0x0B, + LTC3676_DVB2A = 0x0C, + LTC3676_DVB2B = 0x0D, + LTC3676_DVB3A = 0x0E, + LTC3676_DVB3B = 0x0F, + LTC3676_DVB4A = 0x10, + LTC3676_DVB4B = 0x11, + LTC3676_MSKIRQ = 0x12, + LTC3676_MSKPG = 0x13, + LTC3676_USER = 0x14, + LTC3676_HRST = 0x1E, + LTC3676_CLIRQ = 0x1F, + LTC3676_IRQSTAT = 0x15, + LTC3676_PGSTATL = 0x16, + LTC3676_PGSTATR = 0x17, + LTC3676_NUM_OF_REGS = 0x20, +}; + +/* + * SW Configuration + */ + +#define LTC3676_DVB_MASK 0x1f +#define LTC3676_PGOOD_MASK (1<<5) +#define LTC3676_REF_SELA (0<<5) +#define LTC3676_REF_SELB (1<<5) + +int power_ltc3676_init(unsigned char bus); +#endif diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index 91b7ba7bdb..b0e42550a2 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -8,6 +8,8 @@ #ifndef __MAX77686_H_ #define __MAX77686_H_ +#include + enum { MAX77686_REG_PMIC_ID = 0x0, MAX77686_REG_PMIC_INTSRC, @@ -36,7 +38,7 @@ enum { MAX77686_REG_PMIC_BUCK2DVS7, MAX77686_REG_PMIC_BUCK2DVS8, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_REG_PMIC_BUCK3DVS1 = 0x1e, MAX77686_REG_PMIC_BUCK3DVS2, MAX77686_REG_PMIC_BUCK3DVS3, MAX77686_REG_PMIC_BUCK3DVS4, @@ -139,6 +141,35 @@ enum { EN_LDO = (0x3 << 6), }; +enum { + OPMODE_OFF = 0, + OPMODE_STANDBY, + OPMODE_LPM, + OPMODE_ON, +}; + +int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV); +int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode); +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV); +int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); + +#define MAX77686_LDO_VOLT_MAX_HEX 0x3f +#define MAX77686_LDO_VOLT_MASK 0x3f +#define MAX77686_LDO_MODE_MASK 0xc0 +#define MAX77686_LDO_MODE_OFF (0x00 << 0x06) +#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06) +#define MAX77686_LDO_MODE_LPM (0x02 << 0x06) +#define MAX77686_LDO_MODE_ON (0x03 << 0x06) +#define MAX77686_BUCK_VOLT_MAX_HEX 0x3f +#define MAX77686_BUCK_VOLT_MASK 0x3f +#define MAX77686_BUCK_MODE_MASK 0x03 +#define MAX77686_BUCK_MODE_SHIFT_1 0x00 +#define MAX77686_BUCK_MODE_SHIFT_2 0x04 +#define MAX77686_BUCK_MODE_OFF 0x00 +#define MAX77686_BUCK_MODE_STANDBY 0x01 +#define MAX77686_BUCK_MODE_LPM 0x02 +#define MAX77686_BUCK_MODE_ON 0x03 + /* Buck1 1 volt value */ #define MAX77686_BUCK1OUT_1V 0x5 /* Buck1 1.05 volt value */ diff --git a/include/power/max77693_fg.h b/include/power/max77693_fg.h new file mode 100644 index 0000000000..42626ed839 --- /dev/null +++ b/include/power/max77693_fg.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Piotr Wilczek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MAX77693_FG_H_ +#define __MAX77693_FG_H_ + +/* MAX 77693 registers */ +enum { + MAX77693_STATUS = 0x00, + MAX77693_SOCREP = 0x06, + MAX77693_VCELL = 0x09, + MAX77693_CURRENT = 0x0A, + MAX77693_AVG_CURRENT = 0x0B, + MAX77693_SOCMIX = 0x0D, + MAX77693_SOCAV = 0x0E, + MAX77693_DESIGN_CAP = 0x18, + MAX77693_AVG_VCELL = 0x19, + MAX77693_CONFIG = 0x1D, + MAX77693_VERSION = 0x21, + MAX77693_LEARNCFG = 0x28, + MAX77693_FILTERCFG = 0x29, + MAX77693_RELAXCFG = 0x2A, + MAX77693_MISCCFG = 0x2B, + MAX77693_CGAIN = 0x2E, + MAX77693_COFF = 0x2F, + MAX77693_RCOMP0 = 0x38, + MAX77693_TEMPCO = 0x39, + MAX77693_FSTAT = 0x3D, + MAX77693_VFOCV = 0xEE, + MAX77693_VFSOC = 0xFF, + + FG_NUM_OF_REGS = 0x100, +}; + +#define MAX77693_POR (1 << 1) + +#define MODEL_UNLOCK1 0x0059 +#define MODEL_UNLOCK2 0x00c4 +#define MODEL_LOCK1 0x0000 +#define MODEL_LOCK2 0x0000 + +#define MAX77693_FUEL_I2C_ADDR (0x6C >> 1) + +int power_fg_init(unsigned char bus); +#endif /* __MAX77693_FG_H_ */ diff --git a/include/power/max77693_muic.h b/include/power/max77693_muic.h new file mode 100644 index 0000000000..a2c29eb6ce --- /dev/null +++ b/include/power/max77693_muic.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Piotr Wilczek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MAX77693_MUIC_H_ +#define __MAX77693_MUIC_H_ + +#include + +/* + * MUIC REGISTER + */ + +#define MAX77693_MUIC_PREFIX "max77693-muic:" + +/* MAX77693_MUIC_STATUS1 */ +#define MAX77693_MUIC_ADC_MASK 0x1F + +/* MAX77693_MUIC_STATUS2 */ +#define MAX77693_MUIC_CHG_NO 0x00 +#define MAX77693_MUIC_CHG_USB 0x01 +#define MAX77693_MUIC_CHG_USB_D 0x02 +#define MAX77693_MUIC_CHG_TA 0x03 +#define MAX77693_MUIC_CHG_TA_500 0x04 +#define MAX77693_MUIC_CHG_TA_1A 0x05 +#define MAX77693_MUIC_CHG_MASK 0x07 + +/* MAX77693_MUIC_CONTROL1 */ +#define MAX77693_MUIC_CTRL1_DN1DP2 ((0x1 << 3) | 0x1) +#define MAX77693_MUIC_CTRL1_UT1UR2 ((0x3 << 3) | 0x3) +#define MAX77693_MUIC_CTRL1_ADN1ADP2 ((0x4 << 3) | 0x4) +#define MAX77693_MUIC_CTRL1_AUT1AUR2 ((0x5 << 3) | 0x5) +#define MAX77693_MUIC_CTRL1_MASK 0xC0 + +#define MUIC_PATH_USB 0 +#define MUIC_PATH_UART 1 + +#define MUIC_PATH_CP 0 +#define MUIC_PATH_AP 1 + +enum muic_path { + MUIC_PATH_USB_CP, + MUIC_PATH_USB_AP, + MUIC_PATH_UART_CP, + MUIC_PATH_UART_AP, +}; + +/* MAX 777693 MUIC registers */ +enum { + MAX77693_MUIC_ID = 0x00, + MAX77693_MUIC_INT1 = 0x01, + MAX77693_MUIC_INT2 = 0x02, + MAX77693_MUIC_INT3 = 0x03, + MAX77693_MUIC_STATUS1 = 0x04, + MAX77693_MUIC_STATUS2 = 0x05, + MAX77693_MUIC_STATUS3 = 0x06, + MAX77693_MUIC_INTMASK1 = 0x07, + MAX77693_MUIC_INTMASK2 = 0x08, + MAX77693_MUIC_INTMASK3 = 0x09, + MAX77693_MUIC_CDETCTRL = 0x0A, + MAX77693_MUIC_CONTROL1 = 0x0C, + MAX77693_MUIC_CONTROL2 = 0x0D, + MAX77693_MUIC_CONTROL3 = 0x0E, + + MUIC_NUM_OF_REGS = 0x0F, +}; + +#define MAX77693_MUIC_I2C_ADDR (0x4A >> 1) + +int power_muic_init(unsigned int bus); +#endif /* __MAX77693_MUIC_H_ */ diff --git a/include/power/max77693_pmic.h b/include/power/max77693_pmic.h new file mode 100644 index 0000000000..3d59e5916e --- /dev/null +++ b/include/power/max77693_pmic.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Piotr Wilczek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MAX77693_PMIC_H_ +#define __MAX77693_PMIC_H_ + +#include + +#define CHARGER_MIN_CURRENT 200 +#define CHARGER_MAX_CURRENT 2000 + +#define MAX77693_CHG_PREFIX "max77693-chg:" + +/* Registers */ + +#define MAX77693_CHG_BASE 0xB0 +#define MAX77693_CHG_INT_OK 0xB2 +#define MAX77693_CHG_CNFG_00 0xB7 +#define MAX77693_CHG_CNFG_02 0xB9 +#define MAX77693_CHG_CNFG_06 0xBD +#define MAX77693_SAFEOUT 0xC6 + +#define PMIC_NUM_OF_REGS 0xC7 + +#define MAX77693_CHG_DETBAT (0x1 << 7) /* MAX77693_CHG_INT_OK */ +#define MAX77693_CHG_MODE_ON 0x05 /* MAX77693_CHG_CNFG_00 */ +#define MAX77693_CHG_CC 0x3F /* MAX77693_CHG_CNFG_02 */ +#define MAX77693_CHG_LOCK (0x0 << 2) /* MAX77693_CHG_CNFG_06 */ +#define MAX77693_CHG_UNLOCK (0x3 << 2) /* MAX77693_CHG_CNFG_06 */ + +#define MAX77693_ENSAFEOUT1 (1 << 6) +#define MAX77693_ENSAFEOUT2 (1 << 7) + +#define MAX77693_PMIC_I2C_ADDR (0xCC >> 1) + +int pmic_init_max77693(unsigned char bus); +#endif /* __MAX77693_PMIC_H_ */ diff --git a/include/power/max8997_pmic.h b/include/power/max8997_pmic.h index 74c5d54387..728d60afa5 100644 --- a/include/power/max8997_pmic.h +++ b/include/power/max8997_pmic.h @@ -170,7 +170,6 @@ enum { #define SAFEOUT_3_30V 0x03 /* Charger */ -enum {CHARGER_ENABLE, CHARGER_DISABLE}; #define DETBAT (1 << 2) #define MBCICHFCSET (1 << 4) #define MBCHOSTEN (1 << 6) diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h new file mode 100644 index 0000000000..11184893bf --- /dev/null +++ b/include/power/pfuze100_pmic.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PFUZE100_PMIC_H_ +#define __PFUZE100_PMIC_H_ + +/* PFUZE100 registers */ +enum { + PFUZE100_DEVICEID = 0x00, + PFUZE100_REVID = 0x03, + PFUZE100_FABID = 0x04, + + PFUZE100_SW1ABVOL = 0x20, + PFUZE100_SW1ABSTBY = 0x21, + PUZE_100_SW1ABCONF = 0x24, + PFUZE100_SW1CVOL = 0x2e, + PFUZE100_SW1CSTBY = 0x2f, + PFUZE100_SW1CCONF = 0x32, + PFUZE100_SW2VOL = 0x35, + PFUZE100_SW3AVOL = 0x3c, + PFUZE100_SW3BVOL = 0x43, + PFUZE100_SW4VOL = 0x4a, + PFUZE100_SWBSTCON1 = 0x66, + PFUZE100_VREFDDRCON = 0x6a, + PFUZE100_VSNVSVOL = 0x6b, + PFUZE100_VGEN1VOL = 0x6c, + PFUZE100_VGEN2VOL = 0x6d, + PFUZE100_VGEN3VOL = 0x6e, + PFUZE100_VGEN4VOL = 0x6f, + PFUZE100_VGEN5VOL = 0x70, + PFUZE100_VGEN6VOL = 0x71, + + PMIC_NUM_OF_REGS = 0x7f, +}; + +/* + * Buck Regulators + */ + +/* SW1A/B/C Output Voltage Configuration */ +#define SW1x_0_300V 0 +#define SW1x_0_325V 1 +#define SW1x_0_350V 2 +#define SW1x_0_375V 3 +#define SW1x_0_400V 4 +#define SW1x_0_425V 5 +#define SW1x_0_450V 6 +#define SW1x_0_475V 7 +#define SW1x_0_500V 8 +#define SW1x_0_525V 9 +#define SW1x_0_550V 10 +#define SW1x_0_575V 11 +#define SW1x_0_600V 12 +#define SW1x_0_625V 13 +#define SW1x_0_650V 14 +#define SW1x_0_675V 15 +#define SW1x_0_700V 16 +#define SW1x_0_725V 17 +#define SW1x_0_750V 18 +#define SW1x_0_775V 19 +#define SW1x_0_800V 20 +#define SW1x_0_825V 21 +#define SW1x_0_850V 22 +#define SW1x_0_875V 23 +#define SW1x_0_900V 24 +#define SW1x_0_925V 25 +#define SW1x_0_950V 26 +#define SW1x_0_975V 27 +#define SW1x_1_000V 28 +#define SW1x_1_025V 29 +#define SW1x_1_050V 30 +#define SW1x_1_075V 31 +#define SW1x_1_100V 32 +#define SW1x_1_125V 33 +#define SW1x_1_150V 34 +#define SW1x_1_175V 35 +#define SW1x_1_200V 36 +#define SW1x_1_225V 37 +#define SW1x_1_250V 38 +#define SW1x_1_275V 39 +#define SW1x_1_300V 40 +#define SW1x_1_325V 41 +#define SW1x_1_350V 42 +#define SW1x_1_375V 43 +#define SW1x_1_400V 44 +#define SW1x_1_425V 45 +#define SW1x_1_450V 46 +#define SW1x_1_475V 47 +#define SW1x_1_500V 48 +#define SW1x_1_525V 49 +#define SW1x_1_550V 50 +#define SW1x_1_575V 51 +#define SW1x_1_600V 52 +#define SW1x_1_625V 53 +#define SW1x_1_650V 54 +#define SW1x_1_675V 55 +#define SW1x_1_700V 56 +#define SW1x_1_725V 57 +#define SW1x_1_750V 58 +#define SW1x_1_775V 59 +#define SW1x_1_800V 60 +#define SW1x_1_825V 61 +#define SW1x_1_850V 62 +#define SW1x_1_875V 63 + +#define SW1x_NORMAL_MASK 0x3f +#define SW1x_STBY_MASK 0x3f +#define SW1x_OFF_MASK 0x3f + +#define SW1xCONF_DVSSPEED_MASK 0xc0 +#define SW1xCONF_DVSSPEED_2US 0x00 +#define SW1xCONF_DVSSPEED_4US 0x40 +#define SW1xCONF_DVSSPEED_8US 0x80 +#define SW1xCONF_DVSSPEED_16US 0xc0 + +/* + * LDO Configuration + */ + +/* VGEN1/2 Voltage Configuration */ +#define LDOA_0_80V 0 +#define LDOA_0_85V 1 +#define LDOA_0_90V 2 +#define LDOA_0_95V 3 +#define LDOA_1_00V 4 +#define LDOA_1_05V 5 +#define LDOA_1_10V 6 +#define LDOA_1_15V 7 +#define LDOA_1_20V 8 +#define LDOA_1_25V 9 +#define LDOA_1_30V 10 +#define LDOA_1_35V 11 +#define LDOA_1_40V 12 +#define LDOA_1_45V 13 +#define LDOA_1_50V 14 +#define LDOA_1_55V 15 + +/* VGEN3/4/5/6 Voltage Configuration */ +#define LDOB_1_80V 0 +#define LDOB_1_90V 1 +#define LDOB_2_00V 2 +#define LDOB_2_10V 3 +#define LDOB_2_20V 4 +#define LDOB_2_30V 5 +#define LDOB_2_40V 6 +#define LDOB_2_50V 7 +#define LDOB_2_60V 8 +#define LDOB_2_70V 9 +#define LDOB_2_80V 10 +#define LDOB_2_90V 11 +#define LDOB_3_00V 12 +#define LDOB_3_10V 13 +#define LDOB_3_20V 14 +#define LDOB_3_30V 15 + +#define LDO_VOL_MASK 0xf +#define LDO_EN 4 + +/* + * Boost Regulator + */ + +/* SWBST Output Voltage */ +#define SWBST_5_00V 0 +#define SWBST_5_05V 1 +#define SWBST_5_10V 2 +#define SWBST_5_15V 3 + +#define SWBST_VOL_MASK 0x3 +#define SWBST_MODE_MASK 0x6 +#define SWBST_MODE_OFF (2 << 0) +#define SWBST_MODE_PFM (2 << 1) +#define SWBST_MODE_AUTO (2 << 2) +#define SWBST_MODE_APS (2 << 3) + +int power_pfuze100_init(unsigned char bus); +#endif diff --git a/include/power/pmic.h b/include/power/pmic.h index 0e7aa31492..afbc5aab7e 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -8,7 +8,6 @@ #ifndef __CORE_PMIC_H_ #define __CORE_PMIC_H_ -#include #include #include #include @@ -18,6 +17,11 @@ enum { I2C_PMIC, I2C_NUM, }; enum { PMIC_READ, PMIC_WRITE, }; enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; +enum { + PMIC_CHARGER_DISABLE, + PMIC_CHARGER_ENABLE, +}; + struct p_i2c { unsigned char addr; unsigned char *buf; @@ -75,6 +79,7 @@ struct pmic { }; int pmic_init(unsigned char bus); +int power_init_board(void); int pmic_dialog_init(unsigned char bus); int check_reg(struct pmic *p, u32 reg); struct pmic *pmic_alloc(void); diff --git a/include/power/tps62362.h b/include/power/tps62362.h new file mode 100644 index 0000000000..720c338722 --- /dev/null +++ b/include/power/tps62362.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com + * Author: Felipe Balbi + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __POWER_TPS62362_H__ +#define __POWER_TPS62362_H__ + +/* I2C chip address */ +#define TPS62362_I2C_ADDR 0x60 + +/* Registers */ +#define TPS62362_SET0 0x00 +#define TPS62362_SET1 0x01 +#define TPS62362_SET2 0x02 +#define TPS62362_SET3 0x03 +#define TPS62362_NUM_REGS 4 + +#define TPS62362_DCDC_VOLT_SEL_0950MV 0x12 +#define TPS62362_DCDC_VOLT_SEL_1100MV 0x21 +#define TPS62362_DCDC_VOLT_SEL_1200MV 0x2b +#define TPS62362_DCDC_VOLT_SEL_1260MV 0x31 +#define TPS62362_DCDC_VOLT_SEL_1330MV 0x38 + +int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel); +int power_tps62362_init(unsigned char bus); +#endif /* __POWER_TPS62362_H__ */ diff --git a/include/power/tps65090_pmic.h b/include/power/tps65090_pmic.h new file mode 100644 index 0000000000..dcf99c956a --- /dev/null +++ b/include/power/tps65090_pmic.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TPS65090_PMIC_H_ +#define __TPS65090_PMIC_H_ + +/* I2C device address for TPS65090 PMU */ +#define TPS65090_I2C_ADDR 0x48 + +enum { + /* Status register fields */ + TPS65090_ST1_OTC = 1 << 0, + TPS65090_ST1_OCC = 1 << 1, + TPS65090_ST1_STATE_SHIFT = 4, + TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, +}; + +/** + * Enable FET + * + * @param fet_id FET ID, value between 1 and 7 + * @return 0 on success, non-0 on failure + */ +int tps65090_fet_enable(unsigned int fet_id); + +/** + * Disable FET + * + * @param fet_id FET ID, value between 1 and 7 + * @return 0 on success, non-0 on failure + */ +int tps65090_fet_disable(unsigned int fet_id); + +/** + * Is FET enabled? + * + * @param fet_id FET ID, value between 1 and 7 + * @return 1 enabled, 0 disabled, negative value on failure + */ +int tps65090_fet_is_enabled(unsigned int fet_id); + +/** + * Enable / disable the battery charger + * + * @param enable 0 to disable charging, non-zero to enable + */ +int tps65090_set_charge_enable(int enable); + +/** + * Check whether we have enabled battery charging + * + * @return 1 if enabled, 0 if disabled + */ +int tps65090_get_charging(void); + +/** + * Return the value of the status register + * + * @return status register value, or -1 on error + */ +int tps65090_get_status(void); + +/** + * Initialize the TPS65090 PMU. + * + * @return 0 on success, non-0 on failure + */ +int tps65090_init(void); + +#endif /* __TPS65090_PMIC_H_ */ diff --git a/include/power/tps65217.h b/include/power/tps65217.h new file mode 100644 index 0000000000..297c4cbd99 --- /dev/null +++ b/include/power/tps65217.h @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the TRM at http://www.ti.com/product/tps65217a + */ + +#ifndef __POWER_TPS65217_H__ +#define __POWER_TPS65217_H__ + +/* I2C chip address */ +#define TPS65217_CHIP_PM 0x24 + +/* Registers */ +enum { + TPS65217_CHIPID = 0x00, + TPS65217_POWER_PATH, + TPS65217_INTERRUPT, + TPS65217_CHGCONFIG0, + TPS65217_CHGCONFIG1, + TPS65217_CHGCONFIG2, + TPS65217_CHGCONFIG3, + TPS65217_WLEDCTRL1, + TPS65217_WLEDCTRL2, + TPS65217_MUXCTRL, + TPS65217_STATUS, + TPS65217_PASSWORD, + TPS65217_PGOOD, + TPS65217_DEFPG, + TPS65217_DEFDCDC1, + TPS65217_DEFDCDC2, + TPS65217_DEFDCDC3, + TPS65217_DEFSLEW, + TPS65217_DEFLDO1, + TPS65217_DEFLDO2, + TPS65217_DEFLS1, + TPS65217_DEFLS2, + TPS65217_ENABLE, + TPS65217_DEFUVLO, + TPS65217_SEQ1, + TPS65217_SEQ2, + TPS65217_SEQ3, + TPS65217_SEQ4, + TPS65217_SEQ5, + TPS65217_SEQ6, + TPS65217_PMIC_NUM_OF_REGS, +}; + +#define TPS65217_PROT_LEVEL_NONE 0x00 +#define TPS65217_PROT_LEVEL_1 0x01 +#define TPS65217_PROT_LEVEL_2 0x02 + +#define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00 +#define TPS65217_PASSWORD_UNLOCK 0x7D + +#define TPS65217_DCDC_GO 0x80 + +#define TPS65217_MASK_ALL_BITS 0xFF + +#define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03 +#define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00 +#define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01 +#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 +#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 + +#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09 +#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F +#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11 + +#define TPS65217_LDO_MASK 0x1F +#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06 +#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F + +#define TPS65217_PWR_SRC_USB_BITMASK 0x4 +#define TPS65217_PWR_SRC_AC_BITMASK 0x8 + +int tps65217_reg_read(uchar src_reg, uchar *src_val); +int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask); +int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +#endif /* __POWER_TPS65217_H__ */ diff --git a/include/power/tps65218.h b/include/power/tps65218.h new file mode 100644 index 0000000000..63fc7b343f --- /dev/null +++ b/include/power/tps65218.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __POWER_TPS65218_H__ +#define __POWER_TPS65218_H__ + +/* I2C chip address */ +#define TPS65218_CHIP_PM 0x24 + +/* Registers */ +enum { + TPS65218_CHIPID = 0x00, + TPS65218_INT1, + TPS65218_INT2, + TPS65218_INT_MASK1, + TPS65218_INT_MASK2, + TPS65218_STATUS, + TPS65218_CONTROL, + TPS65218_FLAG, + TPS65218_PASSWORD = 0x10, + TPS65218_ENABLE1, + TPS65218_ENABLE2, + TPS65218_CONFIG1, + TPS65218_CONFIG2, + TPS65218_CONFIG3, + TPS65218_DCDC1, + TPS65218_DCDC2, + TPS65218_DCDC3, + TPS65218_DCDC4, + TPS65218_SLEW, + TPS65218_LDO1, + TPS65218_SEQ1 = 0x20, + TPS65218_SEQ2, + TPS65218_SEQ3, + TPS65218_SEQ4, + TPS65218_SEQ5, + TPS65218_SEQ6, + TPS65218_SEQ7, + TPS65218_PMIC_NUM_OF_REGS, +}; + +#define TPS65218_PROT_LEVEL_NONE 0x00 +#define TPS65218_PROT_LEVEL_1 0x01 +#define TPS65218_PROT_LEVEL_2 0x02 + +#define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00 +#define TPS65218_PASSWORD_UNLOCK 0x7D + +#define TPS65218_DCDC_GO 0x80 + +#define TPS65218_MASK_ALL_BITS 0xFF + +#define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a +#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 +#define TPS65218_DCDC_VOLT_SEL_1200MV 0x23 +#define TPS65218_DCDC_VOLT_SEL_1260MV 0x29 +#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 + +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask); +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +int power_tps65218_init(unsigned char bus); +#endif /* __POWER_TPS65218_H__ */ diff --git a/include/power/tps65910.h b/include/power/tps65910.h new file mode 100644 index 0000000000..ca8430145b --- /dev/null +++ b/include/power/tps65910.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the TRM at http://www.ti.com/product/tps65910 + */ +#ifndef __POWER_TPS65910_H__ +#define __POWER_TPS65910_H__ + +#define MPU 0 +#define CORE 1 + +#define TPS65910_SR_I2C_ADDR 0x12 +#define TPS65910_CTRL_I2C_ADDR 0x2D + +/* PMIC Register offsets */ +enum { + TPS65910_VDD1_REG = 0x21, + TPS65910_VDD1_OP_REG = 0x22, + TPS65910_VDD2_REG = 0x24, + TPS65910_VDD2_OP_REG = 0x25, + TPS65910_DEVCTRL_REG = 0x3F, +}; + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define TPS65910_VGAIN_SEL_MASK (0x3 << 6) +#define TPS65910_ILMAX_MASK (0x1 << 5) +#define TPS65910_TSTEP_MASK (0x7 << 2) +#define TPS65910_ST_MASK (0x3) + +#define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6) +#define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6) +#define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define TPS65910_REG_ILMAX_1_0_A (0x0 << 5) +#define TPS65910_REG_ILMAX_1_5_A (0x1 << 5) + +#define TPS65910_REG_TSTEP_ (0x0 << 2) +#define TPS65910_REG_TSTEP_12_5 (0x1 << 2) +#define TPS65910_REG_TSTEP_9_4 (0x2 << 2) +#define TPS65910_REG_TSTEP_7_5 (0x3 << 2) +#define TPS65910_REG_TSTEP_6_25 (0x4 << 2) +#define TPS65910_REG_TSTEP_4_7 (0x5 << 2) +#define TPS65910_REG_TSTEP_3_12 (0x6 << 2) +#define TPS65910_REG_TSTEP_2_5 (0x7 << 2) + +#define TPS65910_REG_ST_OFF (0x0) +#define TPS65910_REG_ST_ON_HI_POW (0x1) +#define TPS65910_REG_ST_OFF_1 (0x2) +#define TPS65910_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define TPS65910_OP_REG_SEL (0x7F) + +#define TPS65910_OP_REG_CMD_MASK (0x1 << 7) +#define TPS65910_OP_REG_CMD_OP (0x0 << 7) +#define TPS65910_OP_REG_CMD_SR (0x1 << 7) + +#define TPS65910_OP_REG_SEL_MASK (0x7F) +#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */ +#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */ +#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ +#define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +int tps65910_set_i2c_control(void); +int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel); +#endif /* __POWER_TPS65910_H__ */ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 331b666459..36d5975584 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -80,7 +80,7 @@ #define r31 31 -#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X) +#if defined(CONFIG_8xx) /* Some special registers */ @@ -92,7 +92,7 @@ #define LCTRL2 157 /* Load/Store Support (37-41) */ #define ICTRL 158 -#endif /* CONFIG_8xx, CONFIG_MPC824X */ +#endif /* CONFIG_8xx */ #if defined(CONFIG_5xx) @@ -135,7 +135,7 @@ #define PLPRCR 0x00000284 -#elif defined(CONFIG_8260) +#elif defined(CONFIG_MPC8260) #define HID2 1011 diff --git a/include/rsa.h b/include/rsa.h deleted file mode 100644 index add4c789f3..0000000000 --- a/include/rsa.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2013, Google Inc. - * - * (C) Copyright 2008 Semihalf - * - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _RSA_H -#define _RSA_H - -#include -#include - -#if IMAGE_ENABLE_SIGN -/** - * sign() - calculate and return signature for given input data - * - * @info: Specifies key and FIT information - * @data: Pointer to the input data - * @data_len: Data length - * @sigp: Set to an allocated buffer holding the signature - * @sig_len: Set to length of the calculated hash - * - * This computes input data signature according to selected algorithm. - * Resulting signature value is placed in an allocated buffer, the - * pointer is returned as *sigp. The length of the calculated - * signature is returned via the sig_len pointer argument. The caller - * should free *sigp. - * - * @return: 0, on success, -ve on error - */ -int rsa_sign(struct image_sign_info *info, - const struct image_region region[], - int region_count, uint8_t **sigp, uint *sig_len); - -/** - * add_verify_data() - Add verification information to FDT - * - * Add public key information to the FDT node, suitable for - * verification at run-time. The information added depends on the - * algorithm being used. - * - * @info: Specifies key and FIT information - * @keydest: Destination FDT blob for public key data - * @return: 0, on success, -ve on error -*/ -int rsa_add_verify_data(struct image_sign_info *info, void *keydest); -#else -static inline int rsa_sign(struct image_sign_info *info, - const struct image_region region[], int region_count, - uint8_t **sigp, uint *sig_len) -{ - return -ENXIO; -} - -static inline int rsa_add_verify_data(struct image_sign_info *info, - void *keydest) -{ - return -ENXIO; -} -#endif - -#if IMAGE_ENABLE_VERIFY -/** - * rsa_verify() - Verify a signature against some data - * - * Verify a RSA PKCS1.5 signature against an expected hash. - * - * @info: Specifies key and FIT information - * @data: Pointer to the input data - * @data_len: Data length - * @sig: Signature - * @sig_len: Number of bytes in signature - * @return 0 if verified, -ve on error - */ -int rsa_verify(struct image_sign_info *info, - const struct image_region region[], int region_count, - uint8_t *sig, uint sig_len); -#else -static inline int rsa_verify(struct image_sign_info *info, - const struct image_region region[], int region_count, - uint8_t *sig, uint sig_len) -{ - return -ENXIO; -} -#endif - -#endif diff --git a/include/rtc.h b/include/rtc.h index c0349668bc..54e361ea5e 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -50,4 +50,41 @@ void to_tm (int, struct rtc_time *); unsigned long mktime (unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); +/** + * rtc_read8() - Read an 8-bit register + * + * @reg: Register to read + * @return value read + */ +int rtc_read8(int reg); + +/** + * rtc_write8() - Write an 8-bit register + * + * @reg: Register to write + * @value: Value to write + */ +void rtc_write8(int reg, uchar val); + +/** + * rtc_read32() - Read a 32-bit value from the RTC + * + * @reg: Offset to start reading from + * @return value read + */ +u32 rtc_read32(int reg); + +/** + * rtc_write32() - Write a 32-bit value to the RTC + * + * @reg: Register to start writing to + * @value: Value to write + */ +void rtc_write32(int reg, u32 value); + +/** + * rtc_init() - Set up the real time clock ready for use + */ +void rtc_init(void); + #endif /* _RTC_H_ */ diff --git a/include/samsung/misc.h b/include/samsung/misc.h new file mode 100644 index 0000000000..607e8d4922 --- /dev/null +++ b/include/samsung/misc.h @@ -0,0 +1,41 @@ +#ifndef __SAMSUNG_MISC_COMMON_H__ +#define __SAMSUNG_MISC_COMMON_H__ + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +void set_board_info(void); +#endif + +#ifdef CONFIG_LCD_MENU +enum { + BOOT_MODE_INFO, + BOOT_MODE_THOR, + BOOT_MODE_UMS, + BOOT_MODE_DFU, + BOOT_MODE_GPT, + BOOT_MODE_ENV, + BOOT_MODE_EXIT, +}; + +void keys_init(void); +void check_boot_mode(void); +#endif /* CONFIG_LCD_MENU */ + +#ifdef CONFIG_CMD_BMP +void draw_logo(void); +#endif + +#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(void); +char *get_dfu_alt_boot(void); +void set_dfu_alt_info(void); +#endif +#ifdef CONFIG_BOARD_TYPES +void set_board_type(void); +const char *get_board_type(void); +#endif + +#endif /* __SAMSUNG_MISC_COMMON_H__ */ diff --git a/include/sandboxblockdev.h b/include/sandboxblockdev.h new file mode 100644 index 0000000000..627787aa32 --- /dev/null +++ b/include/sandboxblockdev.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2013, Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SANDBOX_BLOCK_DEV__ +#define __SANDBOX_BLOCK_DEV__ + +struct host_block_dev { + block_dev_desc_t blk_dev; + char *filename; + int fd; +}; + +int host_dev_bind(int dev, char *filename); + +#endif diff --git a/include/sandboxfs.h b/include/sandboxfs.h index 8ea8cb7e2e..4c7745de91 100644 --- a/include/sandboxfs.h +++ b/include/sandboxfs.h @@ -20,12 +20,18 @@ int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); -long sandbox_fs_read_at(const char *filename, unsigned long pos, - void *buffer, unsigned long maxsize); +int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread); +int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actwrite); void sandbox_fs_close(void); int sandbox_fs_ls(const char *dirname); -int fs_read_sandbox(const char *filename, void *buf, int offset, int len); -int fs_write_sandbox(const char *filename, void *buf, int offset, int len); +int sandbox_fs_exists(const char *filename); +int sandbox_fs_size(const char *filename, loff_t *size); +int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); +int fs_write_sandbox(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite); #endif diff --git a/include/sata.h b/include/sata.h index c95dc56e94..fa61da8ddd 100644 --- a/include/sata.h +++ b/include/sata.h @@ -3,12 +3,16 @@ #include int init_sata(int dev); +int reset_sata(int dev); int scan_sata(int dev); ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer); ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer); int sata_initialize(void); int __sata_initialize(void); +int sata_stop(void); +int __sata_stop(void); +int sata_port_status(int dev, int port); extern block_dev_desc_t sata_dev_desc[]; diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h new file mode 100644 index 0000000000..d71896bbda --- /dev/null +++ b/include/scf0403_lcd.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2013, Compulab Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef SCF0403_LCD_H_ +#define SCF0403_LCD_H_ + +int scf0403_init(int reset_gpio); + +#endif diff --git a/include/sdhci.h b/include/sdhci.h index b18b87312b..23893b5740 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -12,6 +12,7 @@ #include #include +#include /* * Controller registers @@ -192,6 +193,8 @@ #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK) + /* * End of controller registers. */ @@ -210,6 +213,7 @@ #define SDHCI_QUIRK_NO_CD (1 << 5) #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7) +#define SDHCI_QUIRK_USE_WIDE8 (1 << 8) /* to make gcc happy */ struct sdhci_host; @@ -241,9 +245,15 @@ struct sdhci_host { const struct sdhci_ops *ops; int index; + int bus_width; + struct gpio_desc pwr_gpio; /* Power GPIO */ + struct gpio_desc cd_gpio; /* Card Detect GPIO */ + void (*set_control_reg)(struct sdhci_host *host); void (*set_clock)(int dev_index, unsigned int div); uint voltages; + + struct mmc_config cfg; }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS diff --git a/include/search.h b/include/search.h index ae3efc43ca..9701efb2df 100644 --- a/include/search.h +++ b/include/search.h @@ -102,7 +102,8 @@ extern ssize_t hexport_r(struct hsearch_data *__htab, */ extern int himport_r(struct hsearch_data *__htab, const char *__env, size_t __size, const char __sep, - int __flag, int nvars, char * const vars[]); + int __flag, int __crlf_is_lf, int nvars, + char * const vars[]); /* Walk the whole table calling the callback on each element */ extern int hwalk_r(struct hsearch_data *__htab, int (*callback)(ENTRY *)); diff --git a/include/serial.h b/include/serial.h index f6bb2b90a1..66ed12c9c2 100644 --- a/include/serial.h +++ b/include/serial.h @@ -26,7 +26,7 @@ extern struct serial_device serial_smc_device; extern struct serial_device serial_scc_device; extern struct serial_device *default_serial_console(void); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ +#if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_440) || \ defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ @@ -72,4 +72,145 @@ extern int write_port(struct stdio_dev *port, char *buf); extern int read_port(struct stdio_dev *port, char *buf, int size); #endif +struct udevice; + +/** + * struct struct dm_serial_ops - Driver model serial operations + * + * The uclass interface is implemented by all serial devices which use + * driver model. + */ +struct dm_serial_ops { + /** + * setbrg() - Set up the baud rate generator + * + * Adjust baud rate divisors to set up a new baud rate for this + * device. Not all devices will support all rates. If the rate + * cannot be supported, the driver is free to select the nearest + * available rate. or return -EINVAL if this is not possible. + * + * @dev: Device pointer + * @baudrate: New baud rate to use + * @return 0 if OK, -ve on error + */ + int (*setbrg)(struct udevice *dev, int baudrate); + /** + * getc() - Read a character and return it + * + * If no character is available, this should return -EAGAIN without + * waiting. + * + * @dev: Device pointer + * @return character (0..255), -ve on error + */ + int (*getc)(struct udevice *dev); + /** + * putc() - Write a character + * + * @dev: Device pointer + * @ch: character to write + * @return 0 if OK, -ve on error + */ + int (*putc)(struct udevice *dev, const char ch); + /** + * pending() - Check if input/output characters are waiting + * + * This can be used to return an indication of the number of waiting + * characters if the driver knows this (e.g. by looking at the FIFO + * level). It is acceptable to return 1 if an indeterminant number + * of characters is waiting. + * + * This method is optional. + * + * @dev: Device pointer + * @input: true to check input characters, false for output + * @return number of waiting characters, 0 for none, -ve on error + */ + int (*pending)(struct udevice *dev, bool input); + /** + * clear() - Clear the serial FIFOs/holding registers + * + * This method is optional. + * + * This quickly clears any input/output characters from the UART. + * If this is not possible, but characters still exist, then it + * is acceptable to return -EAGAIN (try again) or -EINVAL (not + * supported). + * + * @dev: Device pointer + * @return 0 if OK, -ve on error + */ + int (*clear)(struct udevice *dev); +#if CONFIG_POST & CONFIG_SYS_POST_UART + /** + * loop() - Control serial device loopback mode + * + * @dev: Device pointer + * @on: 1 to turn loopback on, 0 to turn if off + */ + int (*loop)(struct udevice *dev, int on); +#endif +}; + +/** + * struct serial_dev_priv - information about a device used by the uclass + * + * @sdev: stdio device attached to this uart + */ +struct serial_dev_priv { + struct stdio_dev *sdev; +}; + +/* Access the serial operations for a device */ +#define serial_get_ops(dev) ((struct dm_serial_ops *)(dev)->driver->ops) + +void altera_jtag_serial_initialize(void); +void altera_serial_initialize(void); +void amirix_serial_initialize(void); +void arc_serial_initialize(void); +void arm_dcc_initialize(void); +void asc_serial_initialize(void); +void atmel_serial_initialize(void); +void au1x00_serial_initialize(void); +void bfin_jtag_initialize(void); +void bfin_serial_initialize(void); +void bmw_serial_initialize(void); +void clps7111_serial_initialize(void); +void cogent_serial_initialize(void); +void cpci750_serial_initialize(void); +void evb64260_serial_initialize(void); +void imx_serial_initialize(void); +void iop480_serial_initialize(void); +void jz_serial_initialize(void); +void ks8695_serial_initialize(void); +void leon2_serial_initialize(void); +void leon3_serial_initialize(void); +void lh7a40x_serial_initialize(void); +void lpc32xx_serial_initialize(void); +void marvell_serial_initialize(void); +void max3100_serial_initialize(void); +void mcf_serial_initialize(void); +void ml2_serial_initialize(void); +void mpc512x_serial_initialize(void); +void mpc5xx_serial_initialize(void); +void mpc8260_scc_serial_initialize(void); +void mpc8260_smc_serial_initialize(void); +void mpc85xx_serial_initialize(void); +void mpc8xx_serial_initialize(void); +void mxc_serial_initialize(void); +void mxs_auart_initialize(void); +void ns16550_serial_initialize(void); +void oc_serial_initialize(void); +void p3mx_serial_initialize(void); +void pl01x_serial_initialize(void); +void pxa_serial_initialize(void); +void s3c24xx_serial_initialize(void); +void s5p_serial_initialize(void); +void sa1100_serial_initialize(void); +void sandbox_serial_initialize(void); +void sconsole_serial_initialize(void); +void sh_serial_initialize(void); +void uartlite_serial_initialize(void); +void zynq_serial_initialize(void); + #endif diff --git a/include/sh_tmu.h b/include/sh_tmu.h index 96c589da50..97d578dd55 100644 --- a/include/sh_tmu.h +++ b/include/sh_tmu.h @@ -25,7 +25,7 @@ #include -#if defined(CONFIG_SH3) +#if defined(CONFIG_CPU_SH3) struct tmu_regs { u8 tocr; u8 reserved0; @@ -45,9 +45,9 @@ struct tmu_regs { u16 reserved4; u32 tcpr2; }; -#endif /* CONFIG_SH3 */ +#endif /* CONFIG_CPU_SH3 */ -#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) || defined(CONFIG_RMOBILE) +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_RMOBILE) struct tmu_regs { u32 reserved; u8 tstr; @@ -65,11 +65,11 @@ struct tmu_regs { u16 tcr2; u16 reserved5; }; -#endif /* CONFIG_SH4 */ +#endif /* CONFIG_CPU_SH4 */ static inline unsigned long get_tmu0_clk_rate(void) { - return CONFIG_SYS_CLK_FREQ; + return CONFIG_SH_TMU_CLK_FREQ; } #endif /* __SH_TMU_H */ diff --git a/include/smiLynxEM.h b/include/smiLynxEM.h deleted file mode 100644 index c020115f86..0000000000 --- a/include/smiLynxEM.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * (C) Copyright 1997-2002 ELTEC Elektronik AG - * Frank Gottschling - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * smiLynxEM.h - * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator - * - * - * modification history - * -------------------- - * 04-18-2002 Rewritten for U-Boot . - */ - -#ifndef _SMI_LYNX_EM_H_ -#define _SMI_LYNX_EM_H_ - -/* - * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external - */ -#define VIDEO_MEM_SIZE 0x400000 - -/* - * Supported video modes for SMI Lynx E/EM/EM+ - */ -#define VIDEO_MODES 7 -#define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */ - /* VGA2:60/120Hz (pitch=1600) */ - /* SMI810:VGA1:75Hz (pitch=1600) */ - /* VGA2:75Hz (pitch=1600) */ -#define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */ -#define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */ -#define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */ -#define SINGLE_1280_1024 4 /* VGA1:75Hz (pitch=1280) */ -#define TV_MODE_CCIR 5 /* VGA1:50Hz (h=720;v=576;pitch=720) */ -#define TV_MODE_EIA 6 /* VGA1:60Hz (h=720;v=484;pitch=720) */ - - -/* - * ISA mapped regs - */ -#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */ -#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */ -#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */ -#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */ -#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */ -#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */ -#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */ -#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */ -#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */ -#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */ -#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/ - - -/* - * Video processor control - */ -typedef struct { - unsigned int control; - unsigned int colorKey; - unsigned int colorKeyMask; - unsigned int start; - unsigned short offset; - unsigned short width; - unsigned int fifoPrio; - unsigned int fifoERL; - unsigned int YUVtoRGB; -} SmiVideoProc; - -/* - * Video window control - */ -typedef struct { - unsigned short top; - unsigned short left; - unsigned short bottom; - unsigned short right; - unsigned int srcStart; - unsigned short width; - unsigned short offset; - unsigned char hStretch; - unsigned char vStretch; -} SmiVideoWin; - -/* - * Capture port control - */ -typedef struct { - unsigned int control; - unsigned short topClip; - unsigned short leftClip; - unsigned short srcHeight; - unsigned short srcWidth; - unsigned int srcBufStart1; - unsigned int srcBufStart2; - unsigned short srcOffset; - unsigned short fifoControl; -} SmiCapturePort; - - -/******************************************************************************/ -/* Export Graphic Driver Control */ -/******************************************************************************/ - -typedef struct { - unsigned int isaBase; - unsigned int pciBase; - unsigned int dprBase; - unsigned int vprBase; - unsigned int cprBase; - unsigned int frameAdrs; - unsigned int memSize; - unsigned int mode; - unsigned int gdfIndex; - unsigned int gdfBytesPP; - unsigned int fg; - unsigned int bg; - unsigned int plnSizeX; - unsigned int plnSizeY; - unsigned int winSizeX; - unsigned int winSizeY; - char modeIdent[80]; -} GraphicDevice; - -extern GraphicDevice smi; - - -/******************************************************************************/ -/* Export Graphic Functions */ -/******************************************************************************/ - -void *video_hw_init (void); /* returns GraphicDevice struct or NULL */ - -void video_hw_bitblt ( - unsigned int bpp, /* bytes per pixel */ - unsigned int src_x, /* source pos x */ - unsigned int src_y, /* source pos y */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y /* frame height */ - ); - -void video_hw_rectfill ( - unsigned int bpp, /* bytes per pixel */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y, /* frame height */ - unsigned int color /* fill color */ - ); - -void video_set_lut ( - unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ); - -#endif /*_SMI_LYNX_EM_H_ */ diff --git a/include/smsc_lpc47m.h b/include/smsc_lpc47m.h new file mode 100644 index 0000000000..bffd622f0f --- /dev/null +++ b/include/smsc_lpc47m.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SMSC_LPC47M_H_ +#define _SMSC_LPC47M_H_ + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @dev: High 8 bits = Super I/O port, low 8 bits = logical device number. + * @iobase: Processor I/O port address to assign to this serial device. + */ +void lpc47m_enable_serial(u16 dev, u16 iobase); + +#endif /* _SMSC_LPC47M_H_ */ diff --git a/include/sound.h b/include/sound.h index a06ab85386..155e1b40e2 100644 --- a/include/sound.h +++ b/include/sound.h @@ -29,6 +29,15 @@ struct sound_codec_info { enum en_sound_codec codec_type; }; +/* + * Generates square wave sound data for 1 second + * + * @param data data buffer pointer + * @param size size of the buffer + * @param freq frequency of the wave + */ +void sound_create_square_wave(unsigned short *data, int size, uint32_t freq); + /* * Initialises audio sub system * @param blob Pointer of device tree node or NULL if none. diff --git a/include/sparse_defs.h b/include/sparse_defs.h new file mode 100644 index 0000000000..d0612c94e5 --- /dev/null +++ b/include/sparse_defs.h @@ -0,0 +1,7 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/include/sparse_format.h b/include/sparse_format.h new file mode 100644 index 0000000000..af67581cde --- /dev/null +++ b/include/sparse_format.h @@ -0,0 +1,49 @@ +/* + * This is from the Android Project, + * Repository: https://android.googlesource.com/platform/system/core + * File: libsparse/sparse_format.h + * Commit: 28fa5bc347390480fe190294c6c385b6a9f0d68b + * Copyright (C) 2010 The Android Open Source Project + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LIBSPARSE_SPARSE_FORMAT_H_ +#define _LIBSPARSE_SPARSE_FORMAT_H_ +#include "sparse_defs.h" + +typedef struct sparse_header { + __le32 magic; /* 0xed26ff3a */ + __le16 major_version; /* (0x1) - reject images with higher major versions */ + __le16 minor_version; /* (0x0) - allow images with higer minor versions */ + __le16 file_hdr_sz; /* 28 bytes for first revision of the file format */ + __le16 chunk_hdr_sz; /* 12 bytes for first revision of the file format */ + __le32 blk_sz; /* block size in bytes, must be a multiple of 4 (4096) */ + __le32 total_blks; /* total blocks in the non-sparse output image */ + __le32 total_chunks; /* total chunks in the sparse input image */ + __le32 image_checksum; /* CRC32 checksum of the original data, counting "don't care" */ + /* as 0. Standard 802.3 polynomial, use a Public Domain */ + /* table implementation */ +} sparse_header_t; + +#define SPARSE_HEADER_MAGIC 0xed26ff3a + +#define CHUNK_TYPE_RAW 0xCAC1 +#define CHUNK_TYPE_FILL 0xCAC2 +#define CHUNK_TYPE_DONT_CARE 0xCAC3 +#define CHUNK_TYPE_CRC32 0xCAC4 + +typedef struct chunk_header { + __le16 chunk_type; /* 0xCAC1 -> raw; 0xCAC2 -> fill; 0xCAC3 -> don't care */ + __le16 reserved1; + __le32 chunk_sz; /* in blocks in output image */ + __le32 total_sz; /* in bytes of chunk input file including chunk header and data */ +} chunk_header_t; + +/* Following a Raw or Fill or CRC32 chunk is data. + * For a Raw chunk, it's the data in chunk_sz * blk_sz. + * For a Fill chunk, it's 4 bytes of the fill data. + * For a CRC32 chunk, it's 4 bytes of CRC32 + */ + +#endif diff --git a/include/spartan2.h b/include/spartan2.h index 087a27d3cc..14606c3031 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -10,37 +10,40 @@ #include -extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Spartan2_info(Xilinx_desc *desc); - /* Slave Parallel Implementation function table */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_init_fn init; - Xilinx_err_fn err; - Xilinx_done_fn done; - Xilinx_clk_fn clk; - Xilinx_cs_fn cs; - Xilinx_wr_fn wr; - Xilinx_rdata_fn rdata; - Xilinx_wdata_fn wdata; - Xilinx_busy_fn busy; - Xilinx_abort_fn abort; - Xilinx_post_fn post; -} Xilinx_Spartan2_Slave_Parallel_fns; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_init_fn init; + xilinx_err_fn err; + xilinx_done_fn done; + xilinx_clk_fn clk; + xilinx_cs_fn cs; + xilinx_wr_fn wr; + xilinx_rdata_fn rdata; + xilinx_wdata_fn wdata; + xilinx_busy_fn busy; + xilinx_abort_fn abort; + xilinx_post_fn post; +} xilinx_spartan2_slave_parallel_fns; /* Slave Serial Implementation function table */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_clk_fn clk; - Xilinx_init_fn init; - Xilinx_done_fn done; - Xilinx_wr_fn wr; - Xilinx_post_fn post; -} Xilinx_Spartan2_Slave_Serial_fns; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_clk_fn clk; + xilinx_init_fn init; + xilinx_done_fn done; + xilinx_wr_fn wr; + xilinx_post_fn post; +} xilinx_spartan2_slave_serial_fns; + +#if defined(CONFIG_FPGA_SPARTAN2) +extern struct xilinx_fpga_op spartan2_op; +# define FPGA_SPARTAN2_OPS &spartan2_op +#else +# define FPGA_SPARTAN2_OPS NULL +#endif /* Device Image Sizes *********************************************************************/ @@ -63,36 +66,47 @@ typedef struct { *********************************************************************/ /* Spartan-II devices */ #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #endif /* _SPARTAN2_H_ */ diff --git a/include/spartan3.h b/include/spartan3.h index 72e7c0ddd0..fcb27b01e4 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -10,39 +10,42 @@ #include -extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Spartan3_info(Xilinx_desc *desc); - /* Slave Parallel Implementation function table */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_init_fn init; - Xilinx_err_fn err; - Xilinx_done_fn done; - Xilinx_clk_fn clk; - Xilinx_cs_fn cs; - Xilinx_wr_fn wr; - Xilinx_rdata_fn rdata; - Xilinx_wdata_fn wdata; - Xilinx_busy_fn busy; - Xilinx_abort_fn abort; - Xilinx_post_fn post; -} Xilinx_Spartan3_Slave_Parallel_fns; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_init_fn init; + xilinx_err_fn err; + xilinx_done_fn done; + xilinx_clk_fn clk; + xilinx_cs_fn cs; + xilinx_wr_fn wr; + xilinx_rdata_fn rdata; + xilinx_wdata_fn wdata; + xilinx_busy_fn busy; + xilinx_abort_fn abort; + xilinx_post_fn post; +} xilinx_spartan3_slave_parallel_fns; /* Slave Serial Implementation function table */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_clk_fn clk; - Xilinx_init_fn init; - Xilinx_done_fn done; - Xilinx_wr_fn wr; - Xilinx_post_fn post; - Xilinx_bwr_fn bwr; /* block write function */ - Xilinx_abort_fn abort; -} Xilinx_Spartan3_Slave_Serial_fns; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_clk_fn clk; + xilinx_init_fn init; + xilinx_done_fn done; + xilinx_wr_fn wr; + xilinx_post_fn post; + xilinx_bwr_fn bwr; /* block write function */ + xilinx_abort_fn abort; +} xilinx_spartan3_slave_serial_fns; + +#if defined(CONFIG_FPGA_SPARTAN3) +extern struct xilinx_fpga_op spartan3_op; +# define FPGA_SPARTAN3_OPS &spartan3_op +#else +# define FPGA_SPARTAN3_OPS NULL +#endif /* Device Image Sizes *********************************************************************/ @@ -73,46 +76,60 @@ typedef struct { *********************************************************************/ /* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } /* Spartan-3E devices */ #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #endif /* _SPARTAN3_H_ */ diff --git a/include/spi.h b/include/spi.h index c0dab578bf..c58e453559 100644 --- a/include/spi.h +++ b/include/spi.h @@ -1,4 +1,6 @@ /* + * Common SPI Interface: Controller-specific definitions + * * (C) Copyright 2001 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. * @@ -8,8 +10,6 @@ #ifndef _SPI_H_ #define _SPI_H_ -/* Controller-specific definitions: */ - /* SPI mode flags */ #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ @@ -25,29 +25,112 @@ #define SPI_PREAMBLE 0x80 /* Skip preamble bytes */ /* SPI transfer flags */ -#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ -#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ +#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ +#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ +#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ +#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ +#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) +#define SPI_XFER_U_PAGE (1 << 5) + +/* SPI TX operation modes */ +#define SPI_OPM_TX_QPP (1 << 0) +#define SPI_OPM_TX_BP (1 << 1) + +/* SPI RX operation modes */ +#define SPI_OPM_RX_AS (1 << 0) +#define SPI_OPM_RX_DOUT (1 << 1) +#define SPI_OPM_RX_DIO (1 << 2) +#define SPI_OPM_RX_QOF (1 << 3) +#define SPI_OPM_RX_QIOF (1 << 4) +#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \ + SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ + SPI_OPM_RX_QIOF) + +/* SPI bus connection options - see enum spi_dual_flash */ +#define SPI_CONN_DUAL_SHARED (1 << 0) +#define SPI_CONN_DUAL_SEPARATED (1 << 1) /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec -/*----------------------------------------------------------------------- - * Representation of a SPI slave, i.e. what we're communicating with. +#define SPI_DEFAULT_WORDLEN 8 + +#ifdef CONFIG_DM_SPI +/* TODO(sjg@chromium.org): Remove this and use max_hz from struct spi_slave */ +struct dm_spi_bus { + uint max_hz; +}; + +/** + * struct dm_spi_platdata - platform data for all SPI slaves + * + * This describes a SPI slave, a child device of the SPI bus. To obtain this + * struct from a spi_slave, use dev_get_parent_platdata(dev) or + * dev_get_parent_platdata(slave->dev). + * + * This data is immuatable. Each time the device is probed, @max_hz and @mode + * will be copied to struct spi_slave. + * + * @cs: Chip select number (0..n-1) + * @max_hz: Maximum bus speed that this slave can tolerate + * @mode: SPI mode to use for this device (see SPI mode flags) + */ +struct dm_spi_slave_platdata { + unsigned int cs; + uint max_hz; + uint mode; +}; + +#endif /* CONFIG_DM_SPI */ + +/** + * struct spi_slave - Representation of a SPI slave + * + * For driver model this is the per-child data used by the SPI bus. It can + * be accessed using dev_get_parentdata() on the slave device. The SPI uclass + * sets uip per_child_auto_alloc_size to sizeof(struct spi_slave), and the + * driver should not override it. Two platform data fields (max_hz and mode) + * are copied into this structure to provide an initial value. This allows + * them to be changed, since we should never change platform data in drivers. * - * Drivers are expected to extend this with controller-specific data. + * If not using driver model, drivers are expected to extend this with + * controller-specific data. * - * bus: ID of the bus that the slave is attached to. - * cs: ID of the chip select connected to the slave. - * max_write_size: If non-zero, the maximum number of bytes which can - * be written at once, excluding command bytes. + * @dev: SPI slave device + * @max_hz: Maximum speed for this slave + * @mode: SPI mode to use for this slave (see SPI mode flags) + * @bus: ID of the bus that the slave is attached to. For + * driver model this is the sequence number of the SPI + * bus (bus->seq) so does not need to be stored + * @cs: ID of the chip select connected to the slave. + * @op_mode_rx: SPI RX operation mode. + * @op_mode_tx: SPI TX operation mode. + * @wordlen: Size of SPI word in number of bits + * @max_write_size: If non-zero, the maximum number of bytes which can + * be written at once, excluding command bytes. + * @memory_map: Address of read-only SPI flash access. + * @option: Varies SPI bus options - separate, shared bus. + * @flags: Indication of SPI flags. */ struct spi_slave { - unsigned int bus; - unsigned int cs; +#ifdef CONFIG_DM_SPI + struct udevice *dev; /* struct spi_slave is dev->parentdata */ + uint max_hz; + uint mode; +#else + unsigned int bus; + unsigned int cs; +#endif + u8 op_mode_rx; + u8 op_mode_tx; + unsigned int wordlen; unsigned int max_write_size; + void *memory_map; + u8 option; + u8 flags; }; -/*----------------------------------------------------------------------- +/** * Initialization, must be called once on start up. * * TODO: I don't think we really need this. @@ -60,10 +143,10 @@ void spi_init(void); * Allocate and zero all fields in the spi slave, and set the bus/chip * select. Use the helper macro spi_alloc_slave() to call this. * - * @offset: Offset of struct spi_slave within slave structure - * @size: Size of slave structure - * @bus: Bus ID of the slave chip. - * @cs: Chip select ID of the slave chip on the specified bus. + * @offset: Offset of struct spi_slave within slave structure. + * @size: Size of slave structure. + * @bus: Bus ID of the slave chip. + * @cs: Chip select ID of the slave chip on the specified bus. */ void *spi_do_alloc_slave(int offset, int size, unsigned int bus, unsigned int cs); @@ -74,10 +157,10 @@ void *spi_do_alloc_slave(int offset, int size, unsigned int bus, * Allocate and zero all fields in the spi slave, and set the bus/chip * select. * - * @_struct: Name of structure to allocate (e.g. struct tegra_spi). This - * structure must contain a member 'struct spi_slave *slave'. - * @bus: Bus ID of the slave chip. - * @cs: Chip select ID of the slave chip on the specified bus. + * @_struct: Name of structure to allocate (e.g. struct tegra_spi). + * This structure must contain a member 'struct spi_slave *slave'. + * @bus: Bus ID of the slave chip. + * @cs: Chip select ID of the slave chip on the specified bus. */ #define spi_alloc_slave(_struct, bus, cs) \ spi_do_alloc_slave(offsetof(_struct, slave), \ @@ -89,13 +172,13 @@ void *spi_do_alloc_slave(int offset, int size, unsigned int bus, * Allocate and zero all fields in the spi slave, and set the bus/chip * select. * - * @bus: Bus ID of the slave chip. - * @cs: Chip select ID of the slave chip on the specified bus. + * @bus: Bus ID of the slave chip. + * @cs: Chip select ID of the slave chip on the specified bus. */ #define spi_alloc_slave_base(bus, cs) \ spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs) -/*----------------------------------------------------------------------- +/** * Set up communications parameters for a SPI slave. * * This must be called once for each slave. Note that this function @@ -103,10 +186,10 @@ void *spi_do_alloc_slave(int offset, int size, unsigned int bus, * contents of spi_slave so that the hardware can be easily * initialized later. * - * bus: Bus ID of the slave chip. - * cs: Chip select ID of the slave chip on the specified bus. - * max_hz: Maximum SCK rate in Hz. - * mode: Clock polarity, clock phase and other parameters. + * @bus: Bus ID of the slave chip. + * @cs: Chip select ID of the slave chip on the specified bus. + * @max_hz: Maximum SCK rate in Hz. + * @mode: Clock polarity, clock phase and other parameters. * * Returns: A spi_slave reference that can be used in subsequent SPI * calls, or NULL if one or more of the parameters are not supported. @@ -114,14 +197,14 @@ void *spi_do_alloc_slave(int offset, int size, unsigned int bus, struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode); -/*----------------------------------------------------------------------- +/** * Free any memory associated with a SPI slave. * - * slave: The SPI slave + * @slave: The SPI slave */ void spi_free_slave(struct spi_slave *slave); -/*----------------------------------------------------------------------- +/** * Claim the bus and prepare it for communication with a given slave. * * This must be called before doing any transfers with a SPI slave. It @@ -130,25 +213,37 @@ void spi_free_slave(struct spi_slave *slave); * allowed to claim the same bus for several slaves without releasing * the bus in between. * - * slave: The SPI slave + * @slave: The SPI slave * * Returns: 0 if the bus was claimed successfully, or a negative value * if it wasn't. */ int spi_claim_bus(struct spi_slave *slave); -/*----------------------------------------------------------------------- +/** * Release the SPI bus * * This must be called once for every call to spi_claim_bus() after * all transfers have finished. It may disable any SPI hardware as * appropriate. * - * slave: The SPI slave + * @slave: The SPI slave */ void spi_release_bus(struct spi_slave *slave); -/*----------------------------------------------------------------------- +/** + * Set the word length for SPI transactions + * + * Set the word length (number of bits per word) for SPI transactions. + * + * @slave: The SPI slave + * @wordlen: The number of bits in a word + * + * Returns: 0 on success, -1 on failure. + */ +int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen); + +/** * SPI transfer * * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks @@ -161,19 +256,19 @@ void spi_release_bus(struct spi_slave *slave); * temporary variables, this is OK). * * spi_xfer() interface: - * slave: The SPI slave which will be sending/receiving the data. - * bitlen: How many bits to write and read. - * dout: Pointer to a string of bits to send out. The bits are + * @slave: The SPI slave which will be sending/receiving the data. + * @bitlen: How many bits to write and read. + * @dout: Pointer to a string of bits to send out. The bits are * held in a byte array and are sent MSB first. - * din: Pointer to a string of bits that will be filled in. - * flags: A bitwise combination of SPI_XFER_* flags. + * @din: Pointer to a string of bits that will be filled in. + * @flags: A bitwise combination of SPI_XFER_* flags. * - * Returns: 0 on success, not 0 on failure + * Returns: 0 on success, not 0 on failure */ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags); -/*----------------------------------------------------------------------- +/** * Determine if a SPI chipselect is valid. * This function is provided by the board if the low-level SPI driver * needs it to determine if a given chipselect is actually valid. @@ -181,9 +276,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, * Returns: 1 if bus:cs identifies a valid chip on this board, 0 * otherwise. */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs); +int spi_cs_is_valid(unsigned int bus, unsigned int cs); -/*----------------------------------------------------------------------- +#ifndef CONFIG_DM_SPI +/** * Activate a SPI chipselect. * This function is provided by the board code when using a driver * that can't control its chipselects automatically (e.g. @@ -192,7 +288,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs); */ void spi_cs_activate(struct spi_slave *slave); -/*----------------------------------------------------------------------- +/** * Deactivate a SPI chipselect. * This function is provided by the board code when using a driver * that can't control its chipselects automatically (e.g. @@ -201,18 +297,19 @@ void spi_cs_activate(struct spi_slave *slave); */ void spi_cs_deactivate(struct spi_slave *slave); -/*----------------------------------------------------------------------- +/** * Set transfer speed. * This sets a new speed to be applied for next spi_xfer(). - * slave: The SPI slave - * hz: The transfer speed + * @slave: The SPI slave + * @hz: The transfer speed */ void spi_set_speed(struct spi_slave *slave, uint hz); +#endif -/*----------------------------------------------------------------------- +/** * Write 8 bits, then read 8 bits. - * slave: The SPI slave we're communicating with - * byte: Byte to be written + * @slave: The SPI slave we're communicating with + * @byte: Byte to be written * * Returns: The value that was read, or a negative value on error. * @@ -237,14 +334,287 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) * This calls spi_setup_slave() with the correct bus number. Call * spi_free_slave() to free it later. * - * @param blob Device tree blob - * @param node SPI peripheral node to use - * @param cs Chip select to use - * @param max_hz Maximum SCK rate in Hz (0 for default) - * @param mode Clock polarity, clock phase and other parameters + * @param blob: Device tree blob + * @param slave_node: Slave node to use + * @param spi_node: SPI peripheral node to use * @return pointer to new spi_slave structure */ -struct spi_slave *spi_setup_slave_fdt(const void *blob, int node, - unsigned int cs, unsigned int max_hz, unsigned int mode); +struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, + int spi_node); + +/** + * spi_base_setup_slave_fdt() - helper function to set up a SPI slace + * + * This decodes SPI properties from the slave node to determine the + * chip select and SPI parameters. + * + * @blob: Device tree blob + * @busnum: Bus number to use + * @node: Device tree node for the SPI bus + */ +struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum, + int node); + +#ifdef CONFIG_DM_SPI + +/** + * struct spi_cs_info - Information about a bus chip select + * + * @dev: Connected device, or NULL if none + */ +struct spi_cs_info { + struct udevice *dev; +}; + +/** + * struct struct dm_spi_ops - Driver model SPI operations + * + * The uclass interface is implemented by all SPI devices which use + * driver model. + */ +struct dm_spi_ops { + /** + * Claim the bus and prepare it for communication. + * + * The device provided is the slave device. It's parent controller + * will be used to provide the communication. + * + * This must be called before doing any transfers with a SPI slave. It + * will enable and initialize any SPI hardware as necessary, and make + * sure that the SCK line is in the correct idle state. It is not + * allowed to claim the same bus for several slaves without releasing + * the bus in between. + * + * @bus: The SPI slave + * + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ + int (*claim_bus)(struct udevice *bus); + + /** + * Release the SPI bus + * + * This must be called once for every call to spi_claim_bus() after + * all transfers have finished. It may disable any SPI hardware as + * appropriate. + * + * @bus: The SPI slave + */ + int (*release_bus)(struct udevice *bus); + + /** + * Set the word length for SPI transactions + * + * Set the word length (number of bits per word) for SPI transactions. + * + * @bus: The SPI slave + * @wordlen: The number of bits in a word + * + * Returns: 0 on success, -ve on failure. + */ + int (*set_wordlen)(struct udevice *bus, unsigned int wordlen); + + /** + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously + * clocks "bitlen" bits in the SPI MISO port. That's just the way SPI + * works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that + * "dout" and "din" can point to the same memory location, in which + * case the input data overwrites the output data (since both are + * buffered by temporary variables, this is OK). + * + * spi_xfer() interface: + * @dev: The slave device to communicate with + * @bitlen: How many bits to write and read. + * @dout: Pointer to a string of bits to send out. The bits are + * held in a byte array and are sent MSB first. + * @din: Pointer to a string of bits that will be filled in. + * @flags: A bitwise combination of SPI_XFER_* flags. + * + * Returns: 0 on success, not -1 on failure + */ + int (*xfer)(struct udevice *dev, unsigned int bitlen, const void *dout, + void *din, unsigned long flags); + + /** + * Set transfer speed. + * This sets a new speed to be applied for next spi_xfer(). + * @bus: The SPI bus + * @hz: The transfer speed + * @return 0 if OK, -ve on error + */ + int (*set_speed)(struct udevice *bus, uint hz); + + /** + * Set the SPI mode/flags + * + * It is unclear if we want to set speed and mode together instead + * of separately. + * + * @bus: The SPI bus + * @mode: Requested SPI mode (SPI_... flags) + * @return 0 if OK, -ve on error + */ + int (*set_mode)(struct udevice *bus, uint mode); + + /** + * Get information on a chip select + * + * This is only called when the SPI uclass does not know about a + * chip select, i.e. it has no attached device. It gives the driver + * a chance to allow activity on that chip select even so. + * + * @bus: The SPI bus + * @cs: The chip select (0..n-1) + * @info: Returns information about the chip select, if valid. + * On entry info->dev is NULL + * @return 0 if OK (and @info is set up), -ENODEV if the chip select + * is invalid, other -ve value on error + */ + int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info); +}; + +struct dm_spi_emul_ops { + /** + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously + * clocks "bitlen" bits in the SPI MISO port. That's just the way SPI + * works. Here the device is a slave. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that + * "dout" and "din" can point to the same memory location, in which + * case the input data overwrites the output data (since both are + * buffered by temporary variables, this is OK). + * + * spi_xfer() interface: + * @slave: The SPI slave which will be sending/receiving the data. + * @bitlen: How many bits to write and read. + * @dout: Pointer to a string of bits sent to the device. The + * bits are held in a byte array and are sent MSB first. + * @din: Pointer to a string of bits that will be sent back to + * the master. + * @flags: A bitwise combination of SPI_XFER_* flags. + * + * Returns: 0 on success, not -1 on failure + */ + int (*xfer)(struct udevice *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags); +}; + +/** + * spi_find_bus_and_cs() - Find bus and slave devices by number + * + * Given a bus number and chip select, this finds the corresponding bus + * device and slave device. Neither device is activated by this function, + * although they may have been activated previously. + * + * @busnum: SPI bus number + * @cs: Chip select to look for + * @busp: Returns bus device + * @devp: Return slave device + * @return 0 if found, -ENODEV on error + */ +int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, + struct udevice **devp); + +/** + * spi_get_bus_and_cs() - Find and activate bus and slave devices by number + * + * Given a bus number and chip select, this finds the corresponding bus + * device and slave device. + * + * If no such slave exists, and drv_name is not NULL, then a new slave device + * is automatically bound on this chip select. + * + * Ths new slave device is probed ready for use with the given speed and mode. + * + * @busnum: SPI bus number + * @cs: Chip select to look for + * @speed: SPI speed to use for this slave + * @mode: SPI mode to use for this slave + * @drv_name: Name of driver to attach to this chip select + * @dev_name: Name of the new device thus created + * @busp: Returns bus device + * @devp: Return slave device + * @return 0 if found, -ve on error + */ +int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, + const char *drv_name, const char *dev_name, + struct udevice **busp, struct spi_slave **devp); + +/** + * spi_chip_select() - Get the chip select for a slave + * + * @return the chip select this slave is attached to + */ +int spi_chip_select(struct udevice *slave); + +/** + * spi_find_chip_select() - Find the slave attached to chip select + * + * @bus: SPI bus to search + * @cs: Chip select to look for + * @devp: Returns the slave device if found + * @return 0 if found, -ENODEV on error + */ +int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp); + +/** + * spi_slave_ofdata_to_platdata() - decode standard SPI platform data + * + * This decodes the speed and mode for a slave from a device tree node + * + * @blob: Device tree blob + * @node: Node offset to read from + * @plat: Place to put the decoded information + */ +int spi_slave_ofdata_to_platdata(const void *blob, int node, + struct dm_spi_slave_platdata *plat); + +/** + * spi_cs_info() - Check information on a chip select + * + * This checks a particular chip select on a bus to see if it has a device + * attached, or is even valid. + * + * @bus: The SPI bus + * @cs: The chip select (0..n-1) + * @info: Returns information about the chip select, if valid + * @return 0 if OK (and @info is set up), -ENODEV if the chip select + * is invalid, other -ve value on error + */ +int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info); + +struct sandbox_state; + +/** + * sandbox_spi_get_emul() - get an emulator for a SPI slave + * + * This provides a way to attach an emulated SPI device to a particular SPI + * slave, so that xfer() operations on the slave will be handled by the + * emulator. If a emulator already exists on that chip select it is returned. + * Otherwise one is created. + * + * @state: Sandbox state + * @bus: SPI bus requesting the emulator + * @slave: SPI slave device requesting the emulator + * @emuip: Returns pointer to emulator + * @return 0 if OK, -ve on error + */ +int sandbox_spi_get_emul(struct sandbox_state *state, + struct udevice *bus, struct udevice *slave, + struct udevice **emulp); + +/* Access the serial operations for a device */ +#define spi_get_ops(dev) ((struct dm_spi_ops *)(dev)->driver->ops) +#define spi_emul_get_ops(dev) ((struct dm_spi_emul_ops *)(dev)->driver->ops) +#endif /* CONFIG_DM_SPI */ #endif /* _SPI_H_ */ diff --git a/include/spi_flash.h b/include/spi_flash.h index bfc59aa701..5913b39e26 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -1,93 +1,177 @@ /* - * Interface to SPI flash + * Common SPI flash Interface * * Copyright (C) 2008 Atmel Corporation + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. + * version 2 as published by the Free Software Foundation. */ + #ifndef _SPI_FLASH_H_ #define _SPI_FLASH_H_ -#include +#include /* Because we dereference struct udevice here */ #include -#include +#ifndef CONFIG_SF_DEFAULT_SPEED +# define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#endif +#ifndef CONFIG_SF_DEFAULT_CS +# define CONFIG_SF_DEFAULT_CS 0 +#endif +#ifndef CONFIG_SF_DEFAULT_BUS +# define CONFIG_SF_DEFAULT_BUS 0 +#endif + +struct spi_slave; + +/** + * struct spi_flash - SPI flash structure + * + * @spi: SPI slave + * @name: Name of SPI flash + * @dual_flash: Indicates dual flash memories - dual stacked, parallel + * @shift: Flash shift useful in dual parallel + * @size: Total flash size + * @page_size: Write (page) size + * @sector_size: Sector size + * @erase_size: Erase size + * @bank_read_cmd: Bank read cmd + * @bank_write_cmd: Bank write cmd + * @bank_curr: Current flash bank + * @poll_cmd: Poll cmd - for flash erase/program + * @erase_cmd: Erase cmd 4K, 32K, 64K + * @read_cmd: Read cmd - Array Fast, Extn read and quad read. + * @write_cmd: Write cmd - page and quad program. + * @dummy_byte: Dummy cycles for read operation. + * @memory_map: Address of read-only SPI flash access + * @read: Flash read ops: Read len bytes at offset into buf + * Supported cmds: Fast Array Read + * @write: Flash write ops: Write len bytes from buf into offset + * Supported cmds: Page Program + * @erase: Flash erase ops: Erase len bytes from offset + * Supported cmds: Sector erase 4K, 32K, 64K + * return 0 - Success, 1 - Failure + */ struct spi_flash { +#ifdef CONFIG_DM_SPI_FLASH struct spi_slave *spi; + struct udevice *dev; +#else + struct spi_slave *spi; +#endif + const char *name; + u8 dual_flash; + u8 shift; - const char *name; - - /* Total flash size */ - u32 size; - /* Write (page) size */ - u32 page_size; - /* Erase (sector) size */ - u32 sector_size; + u32 size; + u32 page_size; + u32 sector_size; + u32 erase_size; #ifdef CONFIG_SPI_FLASH_BAR - /* Bank read cmd */ - u8 bank_read_cmd; - /* Bank write cmd */ - u8 bank_write_cmd; - /* Current flash bank */ - u8 bank_curr; + u8 bank_read_cmd; + u8 bank_write_cmd; + u8 bank_curr; +#endif + u8 poll_cmd; + u8 erase_cmd; + u8 read_cmd; + u8 write_cmd; + u8 dummy_byte; + + void *memory_map; +#ifndef CONFIG_DM_SPI_FLASH + /* + * These are not strictly needed for driver model, but keep them here + * whilt the transition is in progress. + * + * Normally each driver would provide its own operations, but for + * SPI flash most chips use the same algorithms. One approach is + * to create a 'common' SPI flash device which knows how to talk + * to most devices, and then allow other drivers to be used instead + * if requird, perhaps with a way of scanning through the list to + * find the driver that matches the device. + */ + int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); + int (*write)(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); + int (*erase)(struct spi_flash *flash, u32 offset, size_t len); #endif - /* Poll cmd - for flash erase/program */ - u8 poll_cmd; - - void *memory_map; /* Address of read-only SPI flash access */ - int (*read)(struct spi_flash *flash, u32 offset, - size_t len, void *buf); - int (*write)(struct spi_flash *flash, u32 offset, - size_t len, const void *buf); - int (*erase)(struct spi_flash *flash, u32 offset, - size_t len); }; -/** - * spi_flash_do_alloc - Allocate a new spi flash structure - * - * The structure is allocated and cleared with default values for - * read, write and erase, which the caller can modify. The caller must set - * up size, page_size and sector_size. - * - * Use the helper macro spi_flash_alloc() to call this. - * - * @offset: Offset of struct spi_slave within slave structure - * @size: Size of slave structure - * @spi: SPI slave - * @name: Name of SPI flash device - */ -void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, - const char *name); +struct dm_spi_flash_ops { + int (*read)(struct udevice *dev, u32 offset, size_t len, void *buf); + int (*write)(struct udevice *dev, u32 offset, size_t len, + const void *buf); + int (*erase)(struct udevice *dev, u32 offset, size_t len); +}; -/** - * spi_flash_alloc - Allocate a new SPI flash structure - * - * @_struct: Name of structure to allocate (e.g. struct ramtron_spi_fram). This - * structure must contain a member 'struct spi_flash *flash'. - * @spi: SPI slave - * @name: Name of SPI flash device - */ -#define spi_flash_alloc(_struct, spi, name) \ - spi_flash_do_alloc(offsetof(_struct, flash), sizeof(_struct), \ - spi, name) +/* Access the serial operations for a device */ +#define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops) + +#ifdef CONFIG_DM_SPI_FLASH +int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode, + struct udevice **devp); + +/* Compatibility function - this is the old U-Boot API */ +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); + +/* Compatibility function - this is the old U-Boot API */ +void spi_flash_free(struct spi_flash *flash); + +int spi_flash_remove(struct udevice *flash); + +static inline int spi_flash_read(struct spi_flash *flash, u32 offset, + size_t len, void *buf) +{ + return sf_get_ops(flash->dev)->read(flash->dev, offset, len, buf); +} + +static inline int spi_flash_write(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + return sf_get_ops(flash->dev)->write(flash->dev, offset, len, buf); +} + +static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, + size_t len) +{ + return sf_get_ops(flash->dev)->erase(flash->dev, offset, len); +} + +struct sandbox_state; + +int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs, + struct udevice *bus, int of_offset, const char *spec); + +void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs); + +#else +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); /** - * spi_flash_alloc_base - Allocate a new SPI flash structure with no private data + * Set up a new SPI flash from an fdt node * - * @spi: SPI slave - * @name: Name of SPI flash device + * @param blob Device tree blob + * @param slave_node Pointer to this SPI slave node in the device tree + * @param spi_node Cached pointer to the SPI interface this node belongs + * to + * @return 0 if ok, -1 on error */ -#define spi_flash_alloc_base(spi, name) \ - spi_flash_do_alloc(0, sizeof(struct spi_flash), spi, name) +struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node, + int spi_node); -struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int spi_mode); void spi_flash_free(struct spi_flash *flash); static inline int spi_flash_read(struct spi_flash *flash, u32 offset, @@ -107,7 +191,9 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, { return flash->erase(flash, offset, len); } +#endif void spi_boot(void) __noreturn; +void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); #endif /* _SPI_FLASH_H_ */ diff --git a/include/spl.h b/include/spl.h index 625785f022..36e301ade4 100644 --- a/include/spl.h +++ b/include/spl.h @@ -11,10 +11,12 @@ #include #include + /* Boot type */ #define MMCSD_MODE_UNDEFINED 0 #define MMCSD_MODE_RAW 1 -#define MMCSD_MODE_FAT 2 +#define MMCSD_MODE_FS 2 +#define MMCSD_MODE_EMMCBOOT 3 struct spl_image_info { const char *name; @@ -33,6 +35,7 @@ extern struct spl_image_info spl_image; void preloader_console_init(void); u32 spl_boot_device(void); u32 spl_boot_mode(void); +void spl_set_header_raw_uboot(void); void spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); void __noreturn jump_to_image_linux(void *arg); @@ -60,6 +63,22 @@ void spl_spi_load_image(void); /* Ethernet SPL functions */ void spl_net_load_image(const char *device); +/* USB SPL functions */ +void spl_usb_load_image(void); + +/* SATA SPL functions */ +void spl_sata_load_image(void); + +/* SPL FAT image functions */ +int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename); +int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition); + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image); + +/* SPL EXT image functions */ +int spl_load_image_ext(block_dev_desc_t *block_dev, int partition, const char *filename); +int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition); + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif diff --git a/include/status_led.h b/include/status_led.h index ecff60d59f..27f4bdfa87 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -56,107 +56,6 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ -/***** GEN860T *********************************************************/ -#elif defined(CONFIG_GEN860T) - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE STATUS_LED_OFF -# define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */ -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 8) -# define STATUS_LED_STATE1 STATUS_LED_BLINKING -# define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */ -# define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE2 STATUS_LED_OFF -# define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */ -# define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE3 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ -# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */ - -/***** IVMS8 **********************************************************/ -#elif defined(CONFIG_IVMS8) - -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */ -# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ) -# define STATUS_LED_STATE STATUS_LED_OFF -# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */ -# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ) -# define STATUS_LED_STATE1 STATUS_LED_OFF -/* IDE LED usable for other purposes, too */ -# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */ -# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ) -# define STATUS_LED_STATE2 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */ - -# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */ - -# define STATUS_LED_YELLOW 0 -# define STATUS_LED_GREEN 1 -# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */ - -/***** IVML24 *********************************************************/ -#elif defined(CONFIG_IVML24) - -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */ -# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ) -# define STATUS_LED_STATE STATUS_LED_OFF -# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */ -# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ) -# define STATUS_LED_STATE1 STATUS_LED_OFF -/* IDE LED usable for other purposes, too */ -# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */ -# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ) -# define STATUS_LED_STATE2 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */ - -# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */ - -# define STATUS_LED_YELLOW 0 -# define STATUS_LED_GREEN 1 -# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */ - -/***** ICU862 ********************************************************/ -#elif defined(CONFIG_ICU862) - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING -# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */ -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ) -# define STATUS_LED_STATE1 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - /***** Someone else defines these *************************************/ #elif defined(STATUS_LED_PAR) @@ -165,29 +64,6 @@ void status_led_set (int led, int state); * filling this file up with lots of custom board stuff. */ -/***** NetVia ********************************************************/ -#elif defined(CONFIG_NETVIA) - -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 - -#define STATUS_LED_PAR im_ioport.iop_pdpar -#define STATUS_LED_DIR im_ioport.iop_pddir -#undef STATUS_LED_ODR -#define STATUS_LED_DAT im_ioport.iop_pddat - -# define STATUS_LED_BIT 0x0080 /* PD.8 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_BIT1 0x0040 /* PD.9 */ -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE1 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#endif - /***** CMI ********************************************************/ #elif defined(CONFIG_CMI) # define STATUS_LED_DIR im_mios.mios_mpiosm32ddr @@ -201,62 +77,6 @@ void status_led_set (int led, int state); # define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */ # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ -/***** KUP4K, KUP4X ****************************************************/ -#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x00000300 /* green + red PA[8]=yellow, PA[7]=red, PA[6]=green */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#elif defined(CONFIG_SVM_SC8xx) -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_BIT 0x00000001 -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -/***** RBC823 ********************************************************/ -#elif defined(CONFIG_RBC823) - -# define STATUS_LED_PAR im_ioport.iop_pcpar -# define STATUS_LED_DIR im_ioport.iop_pcdir -# undef STATUS_LED_ODR -# define STATUS_LED_DAT im_ioport.iop_pcdat - -# define STATUS_LED_BIT 0x0002 /* LED 0 is on PC.14 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING -# define STATUS_LED_BIT1 0x0004 /* LED 1 is on PC.13 */ -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ) -# define STATUS_LED_STATE1 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -/***** NetPhone ********************************************************/ -#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) -/* XXX empty just to avoid the error */ -/***** STx XTc ********************************************************/ -#elif defined(CONFIG_STXXTC) -/* XXX empty just to avoid the error */ -/************************************************************************/ #elif defined(CONFIG_V38B) # define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ @@ -294,19 +114,21 @@ extern void __led_set (led_id_t mask, int state); # include #endif +#endif /* CONFIG_STATUS_LED */ + /* * Coloured LEDs API */ #ifndef __ASSEMBLY__ -extern void coloured_LED_init (void); -extern void red_led_on(void); -extern void red_led_off(void); -extern void green_led_on(void); -extern void green_led_off(void); -extern void yellow_led_on(void); -extern void yellow_led_off(void); -extern void blue_led_on(void); -extern void blue_led_off(void); +void coloured_LED_init(void); +void red_led_on(void); +void red_led_off(void); +void green_led_on(void); +void green_led_off(void); +void yellow_led_on(void); +void yellow_led_off(void); +void blue_led_on(void); +void blue_led_off(void); #else .extern LED_init .extern red_led_on @@ -319,6 +141,4 @@ extern void blue_led_off(void); .extern blue_led_off #endif -#endif /* CONFIG_STATUS_LED */ - #endif /* _STATUS_LED_H_ */ diff --git a/include/stdio_dev.h b/include/stdio_dev.h index d0b5593e5b..24da23fe50 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -27,18 +27,21 @@ struct stdio_dev { /* GENERAL functions */ - int (*start) (void); /* To start the device */ - int (*stop) (void); /* To stop the device */ + int (*start)(struct stdio_dev *dev); /* To start the device */ + int (*stop)(struct stdio_dev *dev); /* To stop the device */ /* OUTPUT functions */ - void (*putc) (const char c); /* To put a char */ - void (*puts) (const char *s); /* To put a string (accelerator) */ + /* To put a char */ + void (*putc)(struct stdio_dev *dev, const char c); + /* To put a string (accelerator) */ + void (*puts)(struct stdio_dev *dev, const char *s); /* INPUT functions */ - int (*tstc) (void); /* To test if a char is ready... */ - int (*getc) (void); /* To get that char */ + /* To test if a char is ready... */ + int (*tstc)(struct stdio_dev *dev); + int (*getc)(struct stdio_dev *dev); /* To get that char */ /* Other functions */ @@ -74,18 +77,39 @@ extern char *stdio_names[MAX_FILES]; * PROTOTYPES */ int stdio_register (struct stdio_dev * dev); -int stdio_init (void); +int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp); + +/** + * stdio_init_tables() - set up stdio tables ready for devices + * + * This does not add any devices, but just prepares stdio for use. + */ +int stdio_init_tables(void); + +/** + * stdio_add_devices() - Add stdio devices to the table + * + * This makes calls to all the various subsystems that use stdio, to make + * them register with stdio. + */ +int stdio_add_devices(void); + +/** + * stdio_init() - Sets up stdio ready for use + * + * This calls stdio_init_tables() and stdio_add_devices() + */ +int stdio_init(void); + void stdio_print_current_devices(void); #ifdef CONFIG_SYS_STDIO_DEREGISTER -int stdio_deregister(const char *devname); +int stdio_deregister(const char *devname, int force); +int stdio_deregister_dev(struct stdio_dev *dev, int force); #endif struct list_head* stdio_get_list(void); struct stdio_dev* stdio_get_by_name(const char* name); struct stdio_dev* stdio_clone(struct stdio_dev *dev); -#ifdef CONFIG_ARM_DCC -int drv_arm_dcc_init(void); -#endif #ifdef CONFIG_LCD int drv_lcd_init (void); #endif diff --git a/include/stdlib.h b/include/stdlib.h new file mode 100644 index 0000000000..6bc7fbb3c4 --- /dev/null +++ b/include/stdlib.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2013 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STDLIB_H_ +#define __STDLIB_H_ + +#include + +#endif /* __STDLIB_H_ */ diff --git a/include/sx151x.h b/include/sx151x.h new file mode 100644 index 0000000000..be42b0681b --- /dev/null +++ b/include/sx151x.h @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2013 + * Viktar Palstsiuk, Promwad, viktar.palstsiuk@promwad.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SX151X_H_ +#define __SX151X_H_ + +int sx151x_get_value(int chip, int gpio); +int sx151x_set_value(int chip, int gpio, int val); +int sx151x_direction_input(int chip, int gpio); +int sx151x_direction_output(int chip, int gpio); +int sx151x_reset(int chip); + +#endif /* __SX151X_H_ */ diff --git a/include/systemace.h b/include/systemace.h index 73affc42be..3f342d565c 100644 --- a/include/systemace.h +++ b/include/systemace.h @@ -6,7 +6,6 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ident "$Id:$" #ifdef CONFIG_SYSTEMACE diff --git a/include/tca642x.h b/include/tca642x.h new file mode 100644 index 0000000000..bda86c1ed8 --- /dev/null +++ b/include/tca642x.h @@ -0,0 +1,69 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * Author: Dan Murphy + * + * Derived work from the pca953x.c driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TCA642X_H_ +#define __TCA642X_H_ + +#ifdef CONFIG_CMD_TCA642X +enum { + TCA642X_CMD_INFO, + TCA642X_CMD_DEVICE, + TCA642X_CMD_OUTPUT, + TCA642X_CMD_INPUT, + TCA642X_CMD_INVERT, +}; +#endif + +#define TCA642X_OUT_LOW 0 +#define TCA642X_OUT_HIGH 1 +#define TCA642X_POL_NORMAL 0 +#define TCA642X_POL_INVERT 1 +#define TCA642X_DIR_OUT 0 +#define TCA642X_DIR_IN 1 + +/* Default to an address that hopefully won't corrupt other i2c devices */ +#ifndef CONFIG_SYS_I2C_TCA642X_ADDR +#define CONFIG_SYS_I2C_TCA642X_ADDR (~0) +#endif + +/* Default to an address that hopefully won't corrupt other i2c devices */ +#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM +#define CONFIG_SYS_I2C_TCA642X_BUS_NUM (0) +#endif + +struct tca642x_bank_info { + uint8_t input_reg; + uint8_t output_reg; + uint8_t polarity_reg; + uint8_t configuration_reg; +}; + +int tca642x_set_val(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data); +int tca642x_set_pol(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data); +int tca642x_set_dir(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data); +int tca642x_get_val(uchar chip, uint8_t gpio_bank); +int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]); + +#endif /* __TCA642X_H_ */ diff --git a/include/thermal.h b/include/thermal.h new file mode 100644 index 0000000000..5d6101bec6 --- /dev/null +++ b/include/thermal.h @@ -0,0 +1,42 @@ +/* + * + * (C) Copyright 2014 Freescale Semiconductor, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _THERMAL_H_ +#define _THERMAL_H_ + +#include + +int thermal_get_temp(struct udevice *dev, int *temp); + +/** + * struct struct dm_thermal_ops - Driver model Thermal operations + * + * The uclass interface is implemented by all Thermal devices which use + * driver model. + */ +struct dm_thermal_ops { + /** + * Get the current temperature + * + * The device provided is the slave device. It's parent controller + * will be used to provide the communication. + * + * This must be called before doing any transfers with a Thermal slave. + * It will enable and initialize any Thermal hardware as necessary, + * and make sure that the SCK line is in the correct idle state. It is + * not allowed to claim the same bus for several slaves without + * releasing the bus in between. + * + * @dev: The Thermal device + * + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ + int (*get_temp)(struct udevice *dev, int *temp); +}; + +#endif /* _THERMAL_H_ */ diff --git a/include/thor.h b/include/thor.h new file mode 100644 index 0000000000..5051be714b --- /dev/null +++ b/include/thor.h @@ -0,0 +1,19 @@ +/* + * thor.h -- USB THOR Downloader protocol + * + * Copyright (C) 2013 Samsung Electronics + * Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __THOR_H_ +#define __THOR_H_ + +#include + +int thor_handle(void); +int thor_init(void); +int thor_add(struct usb_configuration *c); +#endif /* __THOR_H_ */ diff --git a/include/tps6586x.h b/include/tps6586x.h index 10ca103895..eefc95f22e 100644 --- a/include/tps6586x.h +++ b/include/tps6586x.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __H_ +#ifndef _TPS6586X_H_ #define _TPS6586X_H_ enum { @@ -44,9 +44,9 @@ int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate, * Set up the TPS6586X I2C bus number. This will be used for all operations * on the device. This function must be called before using other functions. * - * @param bus I2C bus number containing the TPS6586X chip + * @param bus I2C bus containing the TPS6586X chip * @return 0 (always succeeds) */ -int tps6586x_init(int bus); +int tps6586x_init(struct udevice *bus); #endif /* _TPS6586X_H_ */ diff --git a/include/trace.h b/include/trace.h index 871327fb35..09a38d782f 100644 --- a/include/trace.h +++ b/include/trace.h @@ -89,14 +89,7 @@ int trace_list_calls(void *buff, int buff_size, unsigned int *needed); */ void trace_set_enabled(int enabled); -#ifdef CONFIG_TRACE_EARLY int trace_early_init(void); -#else -static inline int trace_early_init(void) -{ - return 0; -} -#endif /** * Init the trace system diff --git a/include/tsec.h b/include/tsec.h index f0f3d4d59b..89c9091cff 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007, 2009, 2011 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao@motorola.com) * author Andy Fleming @@ -20,20 +20,37 @@ #include #include #include -#include +#ifdef CONFIG_SOC_LS102XA +#define TSEC_SIZE 0x40000 +#define TSEC_MDIO_OFFSET 0x40000 +#else #define TSEC_SIZE 0x01000 #define TSEC_MDIO_OFFSET 0x01000 +#endif #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) +#define TSEC_GET_REGS(num, offset) \ + (struct tsec __iomem *)\ + (TSEC_BASE_ADDR + (((num) - 1) * (offset))) + +#define TSEC_GET_REGS_BASE(num) \ + TSEC_GET_REGS((num), TSEC_SIZE) + +#define TSEC_GET_MDIO_REGS(num, offset) \ + (struct tsec_mii_mng __iomem *)\ + (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset)) + +#define TSEC_GET_MDIO_REGS_BASE(num) \ + TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET) + #define DEFAULT_MII_NAME "FSL_MDIO" #define STD_TSEC_INFO(num) \ { \ - .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ - .miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \ - + (num - 1) * TSEC_MDIO_OFFSET), \ + .regs = TSEC_GET_REGS_BASE(num), \ + .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \ .devname = CONFIG_TSEC##num##_NAME, \ .phyaddr = TSEC##num##_PHY_ADDR, \ .flags = TSEC##num##_FLAGS, \ @@ -42,9 +59,8 @@ #define SET_STD_TSEC_INFO(x, num) \ { \ - x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ - x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \ - + (num - 1) * TSEC_MDIO_OFFSET); \ + x.regs = TSEC_GET_REGS_BASE(num); \ + x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \ x.devname = CONFIG_TSEC##num##_NAME; \ x.phyaddr = TSEC##num##_PHY_ADDR; \ x.flags = TSEC##num##_FLAGS;\ @@ -113,9 +129,14 @@ #define MINFLR_INIT_SETTINGS 0x00000040 +#ifdef CONFIG_SOC_LS102XA +#define DMACTRL_INIT_SETTINGS 0x00000003 +#else #define DMACTRL_INIT_SETTINGS 0x000000c3 +#endif #define DMACTRL_GRS 0x00000010 #define DMACTRL_GTS 0x00000008 +#define DMACTRL_LE 0x00008000 #define TSTAT_CLEAR_THALT 0x80000000 #define RSTAT_CLEAR_RHALT 0x00800000 @@ -186,195 +207,190 @@ #define RXBD_TRUNCATED 0x0001 #define RXBD_STATS 0x003f -typedef struct txbd8 -{ - ushort status; /* Status Fields */ - ushort length; /* Buffer length */ - uint bufPtr; /* Buffer Pointer */ -} txbd8_t; - -typedef struct rxbd8 -{ - ushort status; /* Status Fields */ - ushort length; /* Buffer Length */ - uint bufPtr; /* Buffer Pointer */ -} rxbd8_t; - -typedef struct rmon_mib -{ +struct txbd8 { + uint16_t status; /* Status Fields */ + uint16_t length; /* Buffer length */ + uint32_t bufptr; /* Buffer Pointer */ +}; + +struct rxbd8 { + uint16_t status; /* Status Fields */ + uint16_t length; /* Buffer Length */ + uint32_t bufptr; /* Buffer Pointer */ +}; + +struct tsec_rmon_mib { /* Transmit and Receive Counters */ - uint tr64; /* Transmit and Receive 64-byte Frame Counter */ - uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ - uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ - uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ - uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ - uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ - uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ + u32 tr64; /* Tx/Rx 64-byte Frame Counter */ + u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */ + u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */ + u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */ + u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */ + u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */ + u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */ /* Receive Counters */ - uint rbyt; /* Receive Byte Counter */ - uint rpkt; /* Receive Packet Counter */ - uint rfcs; /* Receive FCS Error Counter */ - uint rmca; /* Receive Multicast Packet (Counter) */ - uint rbca; /* Receive Broadcast Packet */ - uint rxcf; /* Receive Control Frame Packet */ - uint rxpf; /* Receive Pause Frame Packet */ - uint rxuo; /* Receive Unknown OP Code */ - uint raln; /* Receive Alignment Error */ - uint rflr; /* Receive Frame Length Error */ - uint rcde; /* Receive Code Error */ - uint rcse; /* Receive Carrier Sense Error */ - uint rund; /* Receive Undersize Packet */ - uint rovr; /* Receive Oversize Packet */ - uint rfrg; /* Receive Fragments */ - uint rjbr; /* Receive Jabber */ - uint rdrp; /* Receive Drop */ + u32 rbyt; /* Receive Byte Counter */ + u32 rpkt; /* Receive Packet Counter */ + u32 rfcs; /* Receive FCS Error Counter */ + u32 rmca; /* Receive Multicast Packet (Counter) */ + u32 rbca; /* Receive Broadcast Packet */ + u32 rxcf; /* Receive Control Frame Packet */ + u32 rxpf; /* Receive Pause Frame Packet */ + u32 rxuo; /* Receive Unknown OP Code */ + u32 raln; /* Receive Alignment Error */ + u32 rflr; /* Receive Frame Length Error */ + u32 rcde; /* Receive Code Error */ + u32 rcse; /* Receive Carrier Sense Error */ + u32 rund; /* Receive Undersize Packet */ + u32 rovr; /* Receive Oversize Packet */ + u32 rfrg; /* Receive Fragments */ + u32 rjbr; /* Receive Jabber */ + u32 rdrp; /* Receive Drop */ /* Transmit Counters */ - uint tbyt; /* Transmit Byte Counter */ - uint tpkt; /* Transmit Packet */ - uint tmca; /* Transmit Multicast Packet */ - uint tbca; /* Transmit Broadcast Packet */ - uint txpf; /* Transmit Pause Control Frame */ - uint tdfr; /* Transmit Deferral Packet */ - uint tedf; /* Transmit Excessive Deferral Packet */ - uint tscl; /* Transmit Single Collision Packet */ + u32 tbyt; /* Transmit Byte Counter */ + u32 tpkt; /* Transmit Packet */ + u32 tmca; /* Transmit Multicast Packet */ + u32 tbca; /* Transmit Broadcast Packet */ + u32 txpf; /* Transmit Pause Control Frame */ + u32 tdfr; /* Transmit Deferral Packet */ + u32 tedf; /* Transmit Excessive Deferral Packet */ + u32 tscl; /* Transmit Single Collision Packet */ /* (0x2_n700) */ - uint tmcl; /* Transmit Multiple Collision Packet */ - uint tlcl; /* Transmit Late Collision Packet */ - uint txcl; /* Transmit Excessive Collision Packet */ - uint tncl; /* Transmit Total Collision */ - - uint res2; - - uint tdrp; /* Transmit Drop Frame */ - uint tjbr; /* Transmit Jabber Frame */ - uint tfcs; /* Transmit FCS Error */ - uint txcf; /* Transmit Control Frame */ - uint tovr; /* Transmit Oversize Frame */ - uint tund; /* Transmit Undersize Frame */ - uint tfrg; /* Transmit Fragments Frame */ + u32 tmcl; /* Transmit Multiple Collision Packet */ + u32 tlcl; /* Transmit Late Collision Packet */ + u32 txcl; /* Transmit Excessive Collision Packet */ + u32 tncl; /* Transmit Total Collision */ + + u32 res2; + + u32 tdrp; /* Transmit Drop Frame */ + u32 tjbr; /* Transmit Jabber Frame */ + u32 tfcs; /* Transmit FCS Error */ + u32 txcf; /* Transmit Control Frame */ + u32 tovr; /* Transmit Oversize Frame */ + u32 tund; /* Transmit Undersize Frame */ + u32 tfrg; /* Transmit Fragments Frame */ /* General Registers */ - uint car1; /* Carry Register One */ - uint car2; /* Carry Register Two */ - uint cam1; /* Carry Register One Mask */ - uint cam2; /* Carry Register Two Mask */ -} rmon_mib_t; - -typedef struct tsec_hash_regs -{ - uint iaddr0; /* Individual Address Register 0 */ - uint iaddr1; /* Individual Address Register 1 */ - uint iaddr2; /* Individual Address Register 2 */ - uint iaddr3; /* Individual Address Register 3 */ - uint iaddr4; /* Individual Address Register 4 */ - uint iaddr5; /* Individual Address Register 5 */ - uint iaddr6; /* Individual Address Register 6 */ - uint iaddr7; /* Individual Address Register 7 */ - uint res1[24]; - uint gaddr0; /* Group Address Register 0 */ - uint gaddr1; /* Group Address Register 1 */ - uint gaddr2; /* Group Address Register 2 */ - uint gaddr3; /* Group Address Register 3 */ - uint gaddr4; /* Group Address Register 4 */ - uint gaddr5; /* Group Address Register 5 */ - uint gaddr6; /* Group Address Register 6 */ - uint gaddr7; /* Group Address Register 7 */ - uint res2[24]; -} tsec_hash_t; - -typedef struct tsec -{ + u32 car1; /* Carry Register One */ + u32 car2; /* Carry Register Two */ + u32 cam1; /* Carry Register One Mask */ + u32 cam2; /* Carry Register Two Mask */ +}; + +struct tsec_hash_regs { + u32 iaddr0; /* Individual Address Register 0 */ + u32 iaddr1; /* Individual Address Register 1 */ + u32 iaddr2; /* Individual Address Register 2 */ + u32 iaddr3; /* Individual Address Register 3 */ + u32 iaddr4; /* Individual Address Register 4 */ + u32 iaddr5; /* Individual Address Register 5 */ + u32 iaddr6; /* Individual Address Register 6 */ + u32 iaddr7; /* Individual Address Register 7 */ + u32 res1[24]; + u32 gaddr0; /* Group Address Register 0 */ + u32 gaddr1; /* Group Address Register 1 */ + u32 gaddr2; /* Group Address Register 2 */ + u32 gaddr3; /* Group Address Register 3 */ + u32 gaddr4; /* Group Address Register 4 */ + u32 gaddr5; /* Group Address Register 5 */ + u32 gaddr6; /* Group Address Register 6 */ + u32 gaddr7; /* Group Address Register 7 */ + u32 res2[24]; +}; + +struct tsec { /* General Control and Status Registers (0x2_n000) */ - uint res000[4]; + u32 res000[4]; - uint ievent; /* Interrupt Event */ - uint imask; /* Interrupt Mask */ - uint edis; /* Error Disabled */ - uint res01c; - uint ecntrl; /* Ethernet Control */ - uint minflr; /* Minimum Frame Length */ - uint ptv; /* Pause Time Value */ - uint dmactrl; /* DMA Control */ - uint tbipa; /* TBI PHY Address */ + u32 ievent; /* Interrupt Event */ + u32 imask; /* Interrupt Mask */ + u32 edis; /* Error Disabled */ + u32 res01c; + u32 ecntrl; /* Ethernet Control */ + u32 minflr; /* Minimum Frame Length */ + u32 ptv; /* Pause Time Value */ + u32 dmactrl; /* DMA Control */ + u32 tbipa; /* TBI PHY Address */ - uint res034[3]; - uint res040[48]; + u32 res034[3]; + u32 res040[48]; /* Transmit Control and Status Registers (0x2_n100) */ - uint tctrl; /* Transmit Control */ - uint tstat; /* Transmit Status */ - uint res108; - uint tbdlen; /* Tx BD Data Length */ - uint res110[5]; - uint ctbptr; /* Current TxBD Pointer */ - uint res128[23]; - uint tbptr; /* TxBD Pointer */ - uint res188[30]; + u32 tctrl; /* Transmit Control */ + u32 tstat; /* Transmit Status */ + u32 res108; + u32 tbdlen; /* Tx BD Data Length */ + u32 res110[5]; + u32 ctbptr; /* Current TxBD Pointer */ + u32 res128[23]; + u32 tbptr; /* TxBD Pointer */ + u32 res188[30]; /* (0x2_n200) */ - uint res200; - uint tbase; /* TxBD Base Address */ - uint res208[42]; - uint ostbd; /* Out of Sequence TxBD */ - uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ - uint res2b8[18]; + u32 res200; + u32 tbase; /* TxBD Base Address */ + u32 res208[42]; + u32 ostbd; /* Out of Sequence TxBD */ + u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ + u32 res2b8[18]; /* Receive Control and Status Registers (0x2_n300) */ - uint rctrl; /* Receive Control */ - uint rstat; /* Receive Status */ - uint res308; - uint rbdlen; /* RxBD Data Length */ - uint res310[4]; - uint res320; - uint crbptr; /* Current Receive Buffer Pointer */ - uint res328[6]; - uint mrblr; /* Maximum Receive Buffer Length */ - uint res344[16]; - uint rbptr; /* RxBD Pointer */ - uint res388[30]; + u32 rctrl; /* Receive Control */ + u32 rstat; /* Receive Status */ + u32 res308; + u32 rbdlen; /* RxBD Data Length */ + u32 res310[4]; + u32 res320; + u32 crbptr; /* Current Receive Buffer Pointer */ + u32 res328[6]; + u32 mrblr; /* Maximum Receive Buffer Length */ + u32 res344[16]; + u32 rbptr; /* RxBD Pointer */ + u32 res388[30]; /* (0x2_n400) */ - uint res400; - uint rbase; /* RxBD Base Address */ - uint res408[62]; + u32 res400; + u32 rbase; /* RxBD Base Address */ + u32 res408[62]; /* MAC Registers (0x2_n500) */ - uint maccfg1; /* MAC Configuration #1 */ - uint maccfg2; /* MAC Configuration #2 */ - uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ - uint hafdup; /* Half-duplex */ - uint maxfrm; /* Maximum Frame */ - uint res514; - uint res518; + u32 maccfg1; /* MAC Configuration #1 */ + u32 maccfg2; /* MAC Configuration #2 */ + u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ + u32 hafdup; /* Half-duplex */ + u32 maxfrm; /* Maximum Frame */ + u32 res514; + u32 res518; - uint res51c; + u32 res51c; - uint resmdio[6]; + u32 resmdio[6]; - uint res538; + u32 res538; - uint ifstat; /* Interface Status */ - uint macstnaddr1; /* Station Address, part 1 */ - uint macstnaddr2; /* Station Address, part 2 */ - uint res548[46]; + u32 ifstat; /* Interface Status */ + u32 macstnaddr1; /* Station Address, part 1 */ + u32 macstnaddr2; /* Station Address, part 2 */ + u32 res548[46]; /* (0x2_n600) */ - uint res600[32]; + u32 res600[32]; /* RMON MIB Registers (0x2_n680-0x2_n73c) */ - rmon_mib_t rmon; - uint res740[48]; + struct tsec_rmon_mib rmon; + u32 res740[48]; /* Hash Function Registers (0x2_n800) */ - tsec_hash_t hash; + struct tsec_hash_regs hash; - uint res900[128]; + u32 res900[128]; /* Pattern Registers (0x2_nb00) */ - uint resb00[62]; - uint attr; /* Default Attribute Register */ - uint attreli; /* Default Attribute Extract Length and Index */ + u32 resb00[62]; + u32 attr; /* Default Attribute Register */ + u32 attreli; /* Default Attribute Extract Length and Index */ /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ - uint resc00[256]; -} tsec_t; + u32 resc00[256]; +}; #define TSEC_GIGABIT (1 << 0) @@ -383,8 +399,8 @@ typedef struct tsec #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ struct tsec_private { - tsec_t *regs; - struct tsec_mii_mng *phyregs_sgmii; + struct tsec __iomem *regs; + struct tsec_mii_mng __iomem *phyregs_sgmii; struct phy_device *phydev; phy_interface_t interface; struct mii_dev *bus; @@ -394,8 +410,8 @@ struct tsec_private { }; struct tsec_info_struct { - tsec_t *regs; - struct tsec_mii_mng *miiregs_sgmii; + struct tsec __iomem *regs; + struct tsec_mii_mng __iomem *miiregs_sgmii; char *devname; char *mii_devname; phy_interface_t interface; diff --git a/include/tsi148.h b/include/tsi148.h index a0beba73e4..9b635e150a 100644 --- a/include/tsi148.h +++ b/include/tsi148.h @@ -5,7 +5,7 @@ * * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _tsi148_h diff --git a/include/twl4030.h b/include/twl4030.h index 093c61d6db..50f8da822a 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -390,11 +390,15 @@ /* Voltage Selection in PM Receiver Module */ #define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05 +#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09 +#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01 #define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03 #define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05 #define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03 +#define TWL4030_PM_RECEIVER_VMMC2_VSEL_30 0x0B +#define TWL4030_PM_RECEIVER_VMMC2_VSEL_32 0x0C #define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03 /* Device Selection in PM Receiver Module */ @@ -647,7 +651,7 @@ void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, /* For initializing power device */ void twl4030_power_init(void); /* For initializing mmc power */ -void twl4030_power_mmc_init(void); +void twl4030_power_mmc_init(int dev_index); /* * LED diff --git a/include/twl6030.h b/include/twl6030.h index b4035ba4fe..7898699eac 100644 --- a/include/twl6030.h +++ b/include/twl6030.h @@ -110,9 +110,47 @@ #define CTRL_P2_EOCP2 (1 << 1) #define CTRL_P2_BUSY (1 << 0) +#define TWL6032_CTRL_P1 0x36 +#define CTRL_P1_SP1 (1 << 3) + #define GPCH0_LSB 0x57 #define GPCH0_MSB 0x58 +#define TWL6032_GPCH0_LSB 0x3b + +#define TWL6032_GPSELECT_ISB 0x35 + +#define USB_PRODUCT_ID_LSB 0x02 + +#define TWL6030_GPADC_VBAT_CHNL 0x07 +#define TWL6032_GPADC_VBAT_CHNL 0x12 + +#define TWL6030_GPADC_CTRL 0x2e +#define TWL6032_GPADC_CTRL2 0x2f +#define GPADC_CTRL2_CH18_SCALER_EN (1 << 2) +#define GPADC_CTRL_SCALER_DIV4 (1 << 3) + +#define TWL6030_VBAT_MULT 40 * 1000 +#define TWL6032_VBAT_MULT 25 * 1000 + +#define TWL6030_VBAT_SHIFT (10 + 3) +#define TWL6032_VBAT_SHIFT (12 + 2) + +enum twl603x_chip_type{ + chip_TWL6030, + chip_TWL6032, + chip_TWL603X_cnt +}; + +struct twl6030_data{ + u8 chip_type; + u8 adc_rbase; + u8 adc_ctrl; + u8 adc_enable; + int vbat_mult; + int vbat_shift; +}; + /* Functions to read and write from TWL6030 */ static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) { diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/rsa-checksum.h new file mode 100644 index 0000000000..3c69d85ecb --- /dev/null +++ b/include/u-boot/rsa-checksum.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2013, Andreas Oetken. + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _RSA_CHECKSUM_H +#define _RSA_CHECKSUM_H + +#include +#include +#include +#include + +extern const uint8_t padding_sha256_rsa4096[]; +extern const uint8_t padding_sha256_rsa2048[]; +extern const uint8_t padding_sha1_rsa2048[]; + +/** + * hash_calculate() - Calculate hash over the data + * + * @name: Name of algorithm to be used for hash calculation + * @region: Array having info of regions over which hash needs to be calculated + * @region_count: Number of regions in the region array + * @checksum: Buffer contanining the output hash + * + * @return 0 if OK, < 0 if error + */ +int hash_calculate(const char *name, + const struct image_region region[], int region_count, + uint8_t *checksum); + +#endif diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h new file mode 100644 index 0000000000..fce445a082 --- /dev/null +++ b/include/u-boot/rsa-mod-exp.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2014, Ruchika Gupta. + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _RSA_MOD_EXP_H +#define _RSA_MOD_EXP_H + +#include +#include + +/** + * struct key_prop - holder for a public key properties + * + * The struct has pointers to modulus (Typically called N), + * The inverse, R^2, exponent. These can be typecasted and + * used as byte arrays or converted to the required format + * as per requirement of RSA implementation. + */ +struct key_prop { + const void *rr; /* R^2 can be treated as byte array */ + const void *modulus; /* modulus as byte array */ + const void *public_exponent; /* public exponent as byte array */ + uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */ + int num_bits; /* Key length in bits */ + uint32_t exp_len; /* Exponent length in number of uint8_t */ +}; + +/** + * rsa_mod_exp_sw() - Perform RSA Modular Exponentiation in sw + * + * Operation: out[] = sig ^ exponent % modulus + * + * @sig: RSA PKCS1.5 signature + * @sig_len: Length of signature in number of bytes + * @node: Node with RSA key elements like modulus, exponent, R^2, n0inv + * @out: Result in form of byte array of len equal to sig_len + */ +int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len, + struct key_prop *node, uint8_t *out); + +int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, + struct key_prop *node, uint8_t *out); + +/** + * struct struct mod_exp_ops - Driver model for RSA Modular Exponentiation + * operations + * + * The uclass interface is implemented by all crypto devices which use + * driver model. + */ +struct mod_exp_ops { + /** + * Perform Modular Exponentiation + * + * Operation: out[] = sig ^ exponent % modulus + * + * @dev: RSA Device + * @sig: RSA PKCS1.5 signature + * @sig_len: Length of signature in number of bytes + * @node: Node with RSA key elements like modulus, exponent, + * R^2, n0inv + * @out: Result in form of byte array of len equal to sig_len + * + * This function computes exponentiation over the signature. + * Returns: 0 if exponentiation is successful, or a negative value + * if it wasn't. + */ + int (*mod_exp)(struct udevice *dev, const uint8_t *sig, + uint32_t sig_len, struct key_prop *node, + uint8_t *outp); +}; + +#endif diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h new file mode 100644 index 0000000000..fd08a617fb --- /dev/null +++ b/include/u-boot/rsa.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2013, Google Inc. + * + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RSA_H +#define _RSA_H + +#include +#include + +/** + * struct rsa_public_key - holder for a public key + * + * An RSA public key consists of a modulus (typically called N), the inverse + * and R^2, where R is 2^(# key bits). + */ + +struct rsa_public_key { + uint len; /* len of modulus[] in number of uint32_t */ + uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */ + uint32_t *modulus; /* modulus as little endian array */ + uint32_t *rr; /* R^2 as little endian array */ + uint64_t exponent; /* public exponent */ +}; + +#if IMAGE_ENABLE_SIGN +/** + * sign() - calculate and return signature for given input data + * + * @info: Specifies key and FIT information + * @data: Pointer to the input data + * @data_len: Data length + * @sigp: Set to an allocated buffer holding the signature + * @sig_len: Set to length of the calculated hash + * + * This computes input data signature according to selected algorithm. + * Resulting signature value is placed in an allocated buffer, the + * pointer is returned as *sigp. The length of the calculated + * signature is returned via the sig_len pointer argument. The caller + * should free *sigp. + * + * @return: 0, on success, -ve on error + */ +int rsa_sign(struct image_sign_info *info, + const struct image_region region[], + int region_count, uint8_t **sigp, uint *sig_len); + +/** + * add_verify_data() - Add verification information to FDT + * + * Add public key information to the FDT node, suitable for + * verification at run-time. The information added depends on the + * algorithm being used. + * + * @info: Specifies key and FIT information + * @keydest: Destination FDT blob for public key data + * @return: 0, on success, -ENOSPC if the keydest FDT blob ran out of space, + other -ve value on error +*/ +int rsa_add_verify_data(struct image_sign_info *info, void *keydest); +#else +static inline int rsa_sign(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t **sigp, uint *sig_len) +{ + return -ENXIO; +} + +static inline int rsa_add_verify_data(struct image_sign_info *info, + void *keydest) +{ + return -ENXIO; +} +#endif + +#if IMAGE_ENABLE_VERIFY +/** + * rsa_verify() - Verify a signature against some data + * + * Verify a RSA PKCS1.5 signature against an expected hash. + * + * @info: Specifies key and FIT information + * @data: Pointer to the input data + * @data_len: Data length + * @sig: Signature + * @sig_len: Number of bytes in signature + * @return 0 if verified, -ve on error + */ +int rsa_verify(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t *sig, uint sig_len); +#else +static inline int rsa_verify(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t *sig, uint sig_len) +{ + return -ENXIO; +} +#endif + +#define RSA2048_BYTES (2048 / 8) +#define RSA4096_BYTES (4096 / 8) + +/* This is the minimum/maximum key size we support, in bits */ +#define RSA_MIN_KEY_BITS 2048 +#define RSA_MAX_KEY_BITS 4096 + +/* This is the maximum signature length that we support, in bits */ +#define RSA_MAX_SIG_BITS 4096 + +#endif diff --git a/include/sha1.h b/include/u-boot/sha1.h similarity index 100% rename from include/sha1.h rename to include/u-boot/sha1.h diff --git a/include/sha256.h b/include/u-boot/sha256.h similarity index 100% rename from include/sha256.h rename to include/u-boot/sha256.h diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 7f720229a6..324fe72016 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -16,8 +16,10 @@ #include #include +#include #include #include +#include #include #include #include @@ -32,15 +34,11 @@ #include -#define DPRINTK(format, args...) \ -do { \ - printf("%s[%d]: " format "\n", __func__, __LINE__, ##args); \ -} while (0) - /* configurable */ +#if !defined(CONFIG_MTD_UBI_WL_THRESHOLD) #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 +#endif #define CONFIG_MTD_UBI_BEB_RESERVE 1 -#define UBI_IO_DEBUG 0 /* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */ #undef CONFIG_MTD_UBI_DEBUG @@ -50,161 +48,26 @@ do { \ #undef CONFIG_MTD_UBI_DEBUG_MSG_WL #undef CONFIG_MTD_UBI_DEBUG_MSG_IO #undef CONFIG_MTD_UBI_DEBUG_MSG_BLD -#define CONFIG_MTD_UBI_DEBUG_DISABLE_BGT + +#undef CONFIG_MTD_UBI_BLOCK + +/* ubi_init() disables returning error codes when built into the Linux + * kernel so that it doesn't hang the Linux kernel boot process. Since + * the U-Boot driver code depends on getting valid error codes from this + * function we just tell the UBI layer that we are building as a module + * (which only enables the additional error reporting). + */ +#define CONFIG_MTD_UBI_MODULE + +#if !defined(CONFIG_MTD_UBI_BEB_LIMIT) +#define CONFIG_MTD_UBI_BEB_LIMIT 20 +#endif /* build.c */ #define get_device(...) #define put_device(...) #define ubi_sysfs_init(...) 0 #define ubi_sysfs_close(...) do { } while (0) -static inline int is_power_of_2(unsigned long n) -{ - return (n != 0 && ((n & (n - 1)) == 0)); -} - -/* FIXME */ -#define MKDEV(...) 0 -#define MAJOR(dev) 0 -#define MINOR(dev) 0 - -#define alloc_chrdev_region(...) 0 -#define unregister_chrdev_region(...) - -#define class_create(...) __builtin_return_address(0) -#define class_create_file(...) 0 -#define class_remove_file(...) -#define class_destroy(...) -#define misc_register(...) 0 -#define misc_deregister(...) - -/* vmt.c */ -#define device_register(...) 0 -#define volume_sysfs_init(...) 0 -#define volume_sysfs_close(...) do { } while (0) - -/* kapi.c */ - -/* eba.c */ - -/* io.c */ -#define init_waitqueue_head(...) do { } while (0) -#define wait_event_interruptible(...) 0 -#define wake_up_interruptible(...) do { } while (0) -#define print_hex_dump(...) do { } while (0) -#define dump_stack(...) do { } while (0) - -/* wl.c */ -#define task_pid_nr(x) 0 -#define set_freezable(...) do { } while (0) -#define try_to_freeze(...) 0 -#define set_current_state(...) do { } while (0) -#define kthread_should_stop(...) 0 -#define schedule() do { } while (0) - -/* upd.c */ -static inline unsigned long copy_from_user(void *dest, const void *src, - unsigned long count) -{ - memcpy((void *)dest, (void *)src, count); - return 0; -} - -/* common */ -typedef int spinlock_t; -typedef int wait_queue_head_t; -#define spin_lock_init(...) -#define spin_lock(...) -#define spin_unlock(...) - -#define mutex_init(...) -#define mutex_lock(...) -#define mutex_unlock(...) - -#define init_rwsem(...) do { } while (0) -#define down_read(...) do { } while (0) -#define down_write(...) do { } while (0) -#define down_write_trylock(...) 1 -#define up_read(...) do { } while (0) -#define up_write(...) do { } while (0) - -struct kmem_cache { int i; }; -#define kmem_cache_create(...) 1 -#define kmem_cache_alloc(obj, gfp) malloc(sizeof(struct ubi_wl_entry)) -#define kmem_cache_free(obj, size) free(size) -#define kmem_cache_destroy(...) - -#define cond_resched() do { } while (0) -#define yield() do { } while (0) - -#define KERN_WARNING -#define KERN_ERR -#define KERN_NOTICE -#define KERN_DEBUG - -#define GFP_KERNEL 0 -#define GFP_NOFS 1 - -#define __user -#define __init -#define __exit - -#define kthread_create(...) __builtin_return_address(0) -#define kthread_stop(...) do { } while (0) -#define wake_up_process(...) do { } while (0) - -#define BUS_ID_SIZE 20 - -struct rw_semaphore { int i; }; -struct device { - struct device *parent; - struct class *class; - char bus_id[BUS_ID_SIZE]; /* position on parent bus */ - dev_t devt; /* dev_t, creates the sysfs "dev" */ - void (*release)(struct device *dev); -}; -struct mutex { int i; }; -struct kernel_param { int i; }; - -struct cdev { - int owner; - dev_t dev; -}; -#define cdev_init(...) do { } while (0) -#define cdev_add(...) 0 -#define cdev_del(...) do { } while (0) - -#define MAX_ERRNO 4095 -#define IS_ERR_VALUE(x) ((x) >= (unsigned long)-MAX_ERRNO) - -static inline void *ERR_PTR(long error) -{ - return (void *) error; -} - -static inline long PTR_ERR(const void *ptr) -{ - return (long) ptr; -} - -static inline long IS_ERR(const void *ptr) -{ - return IS_ERR_VALUE((unsigned long)ptr); -} - -/* module */ -#define THIS_MODULE 0 -#define try_module_get(...) 1 -#define module_put(...) do { } while (0) -#define module_init(...) -#define module_exit(...) -#define EXPORT_SYMBOL(...) -#define EXPORT_SYMBOL_GPL(...) -#define module_param_call(...) -#define MODULE_PARM_DESC(...) -#define MODULE_VERSION(...) -#define MODULE_DESCRIPTION(...) -#define MODULE_AUTHOR(...) -#define MODULE_LICENSE(...) #ifndef __UBIFS_H__ #include "../drivers/mtd/ubi/ubi.h" diff --git a/include/universe.h b/include/universe.h index 535b403a62..eb81e073d8 100644 --- a/include/universe.h +++ b/include/universe.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _universe_h diff --git a/include/usb.h b/include/usb.h index 60db897cb2..a8fee0bdb7 100644 --- a/include/usb.h +++ b/include/usb.h @@ -11,6 +11,8 @@ #include #include +#include +#include /* * The EHCI spec says that we must align to at least 32 bytes. However, @@ -118,6 +120,7 @@ struct usb_device { * Each instance needs its own set of data structures. */ unsigned long status; + unsigned long int_pending; /* 1 bit per ep, used by int_queue */ int act_len; /* transfered bytes */ int maxchild; /* Number of ports if hub */ int portnr; @@ -125,6 +128,20 @@ struct usb_device { struct usb_device *children[USB_MAXCHILDREN]; void *controller; /* hardware controller private data */ + /* slot_id - for xHCI enabled devices */ + unsigned int slot_id; +}; + +struct int_queue; + +/* + * You can initialize platform's USB host or device + * ports by passing this enum as an argument to + * board_usb_init(). + */ +enum usb_init_type { + USB_INIT_HOST, + USB_INIT_DEVICE }; /********************************************************************** @@ -138,10 +155,16 @@ struct usb_device { defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \ defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \ defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \ - defined(CONFIG_USB_MUSB_OMAP2PLUS) + defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_MUSB_SUNXI) || \ + defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC2) -int usb_lowlevel_init(int index, void **controller); +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller); int usb_lowlevel_stop(int index); +#ifdef CONFIG_MUSB_HOST +void usb_reset_root_port(void); +#else +#define usb_reset_root_port() +#endif int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len); @@ -150,6 +173,13 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); +#if defined CONFIG_USB_EHCI || defined CONFIG_MUSB_HOST +struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe, + int queuesize, int elementsize, void *buffer, int interval); +int destroy_int_queue(struct usb_device *dev, struct int_queue *queue); +void *poll_int_queue(struct usb_device *dev, struct int_queue *queue); +#endif + /* Defines */ #define USB_UHCI_VEND_ID 0x8086 #define USB_UHCI_DEV_ID 0x7112 @@ -165,10 +195,26 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, extern void udc_disconnect(void); -#else -#error USB Lowlevel not defined #endif +/* + * board-specific hardware initialization, called by + * usb drivers and u-boot commands + * + * @param index USB controller number + * @param init initializes controller as USB host or device + */ +int board_usb_init(int index, enum usb_init_type init); + +/* + * can be used to clean up after failed USB initialization attempt + * vide: board_usb_init() + * + * @param index USB controller number for selective cleanup + * @param init usb_init_type passed to board_usb_init() + */ +int board_usb_cleanup(int index, enum usb_init_type init); + #ifdef CONFIG_USB_STORAGE #define USB_MAX_STOR_DEV 5 @@ -188,7 +234,7 @@ int usb_host_eth_scan(int mode); #ifdef CONFIG_USB_KEYBOARD int drv_usb_kbd_init(void); -int usb_kbd_deregister(void); +int usb_kbd_deregister(int force); #endif /* routines */ @@ -338,6 +384,10 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); #define usb_pipecontrol(pipe) (usb_pipetype((pipe)) == PIPE_CONTROL) #define usb_pipebulk(pipe) (usb_pipetype((pipe)) == PIPE_BULK) +#define usb_pipe_ep_index(pipe) \ + usb_pipecontrol(pipe) ? (usb_pipeendpoint(pipe) * 2) : \ + ((usb_pipeendpoint(pipe) * 2) - \ + (usb_pipein(pipe) ? 0 : 1)) /************************************************************************* * Hub Stuff @@ -382,5 +432,6 @@ struct usb_device *usb_alloc_new_device(void *controller); int usb_new_device(struct usb_device *dev); void usb_free_device(void); +int usb_alloc_device(struct usb_device *dev); #endif /*_USB_H_ */ diff --git a/include/usb/ci_udc.h b/include/usb/ci_udc.h new file mode 100644 index 0000000000..0dee50461e --- /dev/null +++ b/include/usb/ci_udc.h @@ -0,0 +1,14 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __CI_UDC_H__ +#define __CI_UDC_H__ + +#define EP_MAX_PACKET_SIZE 0x200 +#define EP0_MAX_PACKET_SIZE 64 +#endif /* __CI_UDC_H__ */ diff --git a/include/usb/designware_udc.h b/include/usb/designware_udc.h index 2e29a7e2a6..2e1cdf138f 100644 --- a/include/usb/designware_udc.h +++ b/include/usb/designware_udc.h @@ -173,19 +173,6 @@ struct udcfifo_regs { u32 *fifo_p; }; -/* - * USBTTY definitions - */ -#define EP0_MAX_PACKET_SIZE 64 -#define UDC_INT_ENDPOINT 1 -#define UDC_INT_PACKET_SIZE 64 -#define UDC_OUT_ENDPOINT 2 -#define UDC_BULK_PACKET_SIZE 64 -#define UDC_BULK_HS_PACKET_SIZE 512 -#define UDC_IN_ENDPOINT 3 -#define UDC_OUT_PACKET_SIZE 64 -#define UDC_IN_PACKET_SIZE 64 - /* * UDC endpoint definitions */ @@ -194,22 +181,4 @@ struct udcfifo_regs { #define UDC_EP2 2 #define UDC_EP3 3 -/* - * Function declarations - */ - -void udc_irq(void); - -void udc_set_nak(int epid); -void udc_unset_nak(int epid); -int udc_endpoint_write(struct usb_endpoint_instance *endpoint); -int udc_init(void); -void udc_enable(struct usb_device_instance *device); -void udc_disable(void); -void udc_connect(void); -void udc_disconnect(void); -void udc_startup_events(struct usb_device_instance *device); -void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, - struct usb_endpoint_instance *endpoint); - #endif /* __DW_UDC_H */ diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 9e106fc422..ecb8b79d86 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -11,6 +11,8 @@ #include +#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ + /* Global offsets */ #define FSL_SKIP_PCI 0x100 @@ -149,13 +151,30 @@ #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 #if defined(CONFIG_MPC83xx) -#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR +#if defined(CONFIG_MPC834x) +#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR +#else +#define CONFIG_SYS_FSL_USB2_ADDR 0 +#endif #elif defined(CONFIG_MPC85xx) -#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR +#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR #elif defined(CONFIG_MPC512X) -#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR +#define CONFIG_SYS_FSL_USB2_ADDR 0 +#elif defined(CONFIG_SOC_LS102XA) +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR +#define CONFIG_SYS_FSL_USB2_ADDR 0 #endif +/* + * Increasing TX FIFO threshold value from 2 to 4 decreases + * data burst rate with which data packets are posted from the TX + * latency FIFO to compensate for latencies in DDR pipeline during DMA + */ +#define TXFIFOTHRESH 4 + /* * USB Registers */ @@ -261,7 +280,9 @@ struct usb_ehci { #define MXC_EHCI_IPPUE_DOWN (1 << 10) #define MXC_EHCI_IPPUE_UP (1 << 11) +int usb_phy_mode(int port); /* Board-specific initialization */ int board_ehci_hcd_init(int port); +int board_usb_phy_mode(int port); #endif /* _EHCI_FSL_H */ diff --git a/include/usb/lin_gadget_compat.h b/include/usb/lin_gadget_compat.h index a25e9d9ef3..29fb166934 100644 --- a/include/usb/lin_gadget_compat.h +++ b/include/usb/lin_gadget_compat.h @@ -13,22 +13,6 @@ #include /* common */ -#define spin_lock_init(...) -#define spin_lock(...) -#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0) -#define spin_unlock(...) -#define spin_unlock_irqrestore(lock, flags) do {flags = 0; } while (0) -#define disable_irq(...) -#define enable_irq(...) - -#define mutex_init(...) -#define mutex_lock(...) -#define mutex_unlock(...) - -#define GFP_KERNEL 0 - -#define IRQ_HANDLED 1 - #define ENOTSUPP 524 /* Operation is not supported */ #define BITS_PER_BYTE 8 diff --git a/include/usb/mpc8xx_udc.h b/include/usb/mpc8xx_udc.h index 475dd41664..9906c75f6a 100644 --- a/include/usb/mpc8xx_udc.h +++ b/include/usb/mpc8xx_udc.h @@ -111,11 +111,9 @@ /* UDC device defines */ #define EP0_MAX_PACKET_SIZE EP_MAX_PKT -#define UDC_OUT_ENDPOINT 0x02 + #define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_IN_ENDPOINT 0x03 #define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_INT_ENDPOINT 0x01 #define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE #define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE @@ -178,18 +176,3 @@ typedef enum mpc8xx_udc_state{ STATE_READY, }mpc8xx_udc_state_t; -/* Declarations */ -int udc_init(void); -void udc_irq(void); -int udc_endpoint_write(struct usb_endpoint_instance *endpoint); -void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, - struct usb_endpoint_instance *endpoint); -void udc_connect(void); -void udc_disconnect(void); -void udc_enable(struct usb_device_instance *device); -void udc_disable(void); -void udc_startup_events(struct usb_device_instance *device); - -/* Flow control */ -void udc_set_nak(int epid); -void udc_unset_nak (int epid); diff --git a/include/usb/musb_udc.h b/include/usb/musb_udc.h deleted file mode 100644 index 3500c7ae96..0000000000 --- a/include/usb/musb_udc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __MUSB_UDC_H__ -#define __MUSB_UDC_H__ - -#include - -/* UDC level routines */ -void udc_irq(void); -void udc_set_nak(int ep_num); -void udc_unset_nak(int ep_num); -int udc_endpoint_write(struct usb_endpoint_instance *endpoint); -void udc_setup_ep(struct usb_device_instance *device, unsigned int id, - struct usb_endpoint_instance *endpoint); -void udc_connect(void); -void udc_disconnect(void); -void udc_enable(struct usb_device_instance *device); -void udc_disable(void); -void udc_startup_events(struct usb_device_instance *device); -int udc_init(void); - -/* usbtty */ -#ifdef CONFIG_USB_TTY - -#define EP0_MAX_PACKET_SIZE 64 /* MUSB_EP0_FIFOSIZE */ -#define UDC_INT_ENDPOINT 1 -#define UDC_INT_PACKET_SIZE 64 -#define UDC_OUT_ENDPOINT 2 -#define UDC_OUT_PACKET_SIZE 64 -#define UDC_IN_ENDPOINT 3 -#define UDC_IN_PACKET_SIZE 64 -#define UDC_BULK_PACKET_SIZE 64 - -#endif /* CONFIG_USB_TTY */ - -#endif /* __MUSB_UDC_H__ */ diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h deleted file mode 100644 index c71516cf6d..0000000000 --- a/include/usb/mv_udc.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __MV_UDC_H__ -#define __MV_UDC_H__ - -#include -#include -#include -#include - -#include "../../drivers/usb/host/ehci.h" - -#define NUM_ENDPOINTS 6 - -/* Endpoint parameters */ -#define MAX_ENDPOINTS 4 - -#define EP_MAX_PACKET_SIZE 0x200 -#define EP0_MAX_PACKET_SIZE 64 - -struct mv_udc { -#define MICRO_8FRAME 0x8 -#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) -#define USBCMD_FS2 (1 << 15) -#define USBCMD_RST (1 << 1) -#define USBCMD_RUN (1) - u32 usbcmd; /* 0x140 */ -#define STS_SLI (1 << 8) -#define STS_URI (1 << 6) -#define STS_PCI (1 << 2) -#define STS_UEI (1 << 1) -#define STS_UI (1 << 0) - u32 usbsts; /* 0x144 */ - u32 pad1[3]; - u32 devaddr; /* 0x154 */ - u32 epinitaddr; /* 0x158 */ - u32 pad2[10]; -#define PTS_ENABLE 2 -#define PTS(x) (((x) & 0x3) << 30) -#define PFSC (1 << 24) - u32 portsc; /* 0x184 */ - u32 pad3[8]; -#define USBMODE_DEVICE 2 - u32 usbmode; /* 0x1a8 */ - u32 epstat; /* 0x1ac */ -#define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) -#define EPT_RX(x) (1 << ((x) & 0xffff)) - u32 epprime; /* 0x1b0 */ - u32 epflush; /* 0x1b4 */ - u32 pad4; - u32 epcomp; /* 0x1bc */ -#define CTRL_TXE (1 << 23) -#define CTRL_TXR (1 << 22) -#define CTRL_RXE (1 << 7) -#define CTRL_RXR (1 << 6) -#define CTRL_TXT_BULK (2 << 18) -#define CTRL_RXT_BULK (2 << 2) - u32 epctrl[16]; /* 0x1c0 */ -}; - -struct mv_ep { - struct usb_ep ep; - struct list_head queue; - const struct usb_endpoint_descriptor *desc; - - struct usb_request req; - uint8_t *b_buf; - uint32_t b_len; - uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); -}; - -struct mv_drv { - struct usb_gadget gadget; - struct usb_gadget_driver *driver; - struct ehci_ctrl *ctrl; - struct ept_queue_head *epts; - struct ept_queue_item *items[2 * NUM_ENDPOINTS]; - uint8_t *items_mem; - struct mv_ep ep[NUM_ENDPOINTS]; -}; - -struct ept_queue_head { - unsigned config; - unsigned current; /* read-only */ - - unsigned next; - unsigned info; - unsigned page0; - unsigned page1; - unsigned page2; - unsigned page3; - unsigned page4; - unsigned reserved_0; - - unsigned char setup_data[8]; - - unsigned reserved_1; - unsigned reserved_2; - unsigned reserved_3; - unsigned reserved_4; -}; - -#define CONFIG_MAX_PKT(n) ((n) << 16) -#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ -#define CONFIG_IOS (1 << 15) /* IRQ on setup */ - -struct ept_queue_item { - unsigned next; - unsigned info; - unsigned page0; - unsigned page1; - unsigned page2; - unsigned page3; - unsigned page4; - unsigned reserved; -}; - -#define TERMINATE 1 -#define INFO_BYTES(n) ((n) << 16) -#define INFO_IOC (1 << 15) -#define INFO_ACTIVE (1 << 7) -#define INFO_HALTED (1 << 6) -#define INFO_BUFFER_ERROR (1 << 5) -#define INFO_TX_ERROR (1 << 3) - -#endif /* __MV_UDC_H__ */ diff --git a/include/usb/omap1510_udc.h b/include/usb/omap1510_udc.h deleted file mode 100644 index ece0e95b61..0000000000 --- a/include/usb/omap1510_udc.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2003 - * Gerry Hamel, geh@ti.com, Texas Instruments - * - * Based on - * linux/drivers/usb/device/bi/omap.h - * Register definitions for TI OMAP1510 USB bus interface driver - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __USBDCORE_OMAP1510_H__ -#define __USBDCORE_OMAP1510_H__ - - -/* - * 13.2 MPU Register Map - */ - -/* Table 13-1. USB Function Module Registers (endpoint) */ -#define UDC_BASE 0xFFFB4000 -#define UDC_OFFSET(offset) (UDC_BASE + (offset)) -#define UDC_REV UDC_OFFSET(0x0) /* Revision */ -#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */ -#define UDC_DATA UDC_OFFSET(0x08) /* Data */ -#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */ -#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */ -#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */ -#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */ -#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */ -#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */ -#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */ -#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */ -#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */ -#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */ -#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */ -#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */ - -/* IRQ_EN register fields */ -#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */ -#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */ -#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */ -#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */ -#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */ - -/* IRQ_SRC register fields */ -#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */ -#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */ -#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */ -#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */ -#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */ -#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */ -#define UDC_DS_Chg (1 << 3) /* Device state changed */ -#define UDC_Setup (1 << 2) /* Setup transaction */ -#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */ -#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */ - -/* DEVSTAT register fields, 14.2.9 */ -#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */ -#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */ -#define UDC_SUS (1 << 4) /* Suspended state */ -#define UDC_CFG (1 << 3) /* Configured state */ -#define UDC_ADD (1 << 2) /* Addressed state */ -#define UDC_DEF (1 << 1) /* Default state */ -#define UDC_ATT (1 << 0) /* Attached state */ - -/* SYSCON1 register fields */ -#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */ -#define UDC_Nak_En (1 << 4) /* NAK enable */ -#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */ -#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */ -#define UDC_Pullup_En (1 << 0) /* External pullup enabled */ - -/* SYSCON2 register fields */ -#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */ -#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */ -#define UDC_Dev_Cfg (1 << 3) /* Device configured */ -#define UDC_Clr_Cfg (1 << 2) /* Clear configured */ - -/* - * Select and enable endpoints - */ - -/* Table 13-1. USB Function Module Registers (endpoint configuration) */ -#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */ -#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */ -#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */ -#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4) -#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */ -#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4) - -/* EP_NUM register fields */ -#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */ -#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */ -#define UDC_EP_Dir (1 << 4) /* Endpoint direction */ - -/* CTRL register fields */ -#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */ -#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */ -#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */ -#define UDC_Clr_EP (1 << 1) /* Clear endpoint */ -#define UDC_Reset_EP (1 << 0) /* Reset endpoint */ - -/* STAT_FLG register fields */ -#define UDC_Miss_In (1 << 14) -#define UDC_Data_Flush (1 << 13) -#define UDC_ISO_Err (1 << 12) -#define UDC_ISO_FIFO_Empty (1 << 9) -#define UDC_ISO_FIFO_Full (1 << 8) -#define UDC_EP_Halted (1 << 6) -#define UDC_STALL (1 << 5) -#define UDC_NAK (1 << 4) -#define UDC_ACK (1 << 3) -#define UDC_FIFO_En (1 << 2) -#define UDC_Non_ISO_FIFO_Empty (1 << 1) -#define UDC_Non_ISO_FIFO_Full (1 << 0) - -/* EPn_RX register fields */ -#define UDC_EPn_RX_Valid (1 << 15) /* valid */ -#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */ -#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */ - -/* EPn_TX register fields */ -#define UDC_EPn_TX_Valid (1 << 15) /* valid */ -#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */ -#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */ - -#define EP0_PACKETSIZE 0x40 - -/* physical to logical endpoint mapping - * Physical endpoints are an index into device->bus->endpoint_array. - * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in - * the USB specification. - * - * physical ep logical ep direction endpoint_address - * 0 0 IN and OUT 0x00 - * 1 to 15 1 to 15 OUT 0x01 to 0x0f - * 16 to 30 1 to 15 IN 0x81 to 0x8f - */ -#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80)) -#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a)) - -/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */ -#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17) - -/* Other registers (may be) related to USB */ - -#define CLOCK_CTRL (0xFFFE0830) -#define APLL_CTRL (0xFFFE084C) -#define DPLL_CTRL (0xFFFE083C) -#define SOFT_REQ (0xFFFE0834) -#define STATUS_REQ (0xFFFE0840) - -/* FUNC_MUX_CTRL_0 bits related to USB */ -#define UDC_VBUS_CTRL (1 << 19) -#define UDC_VBUS_MODE (1 << 18) - -/* OMAP Endpoint parameters */ -#define EP0_MAX_PACKET_SIZE 64 -#define UDC_OUT_ENDPOINT 2 -#define UDC_OUT_PACKET_SIZE 64 -#define UDC_IN_ENDPOINT 1 -#define UDC_IN_PACKET_SIZE 64 -#define UDC_INT_ENDPOINT 5 -#define UDC_INT_PACKET_SIZE 16 -#define UDC_BULK_PACKET_SIZE 16 - -void udc_irq (void); -/* Flow control */ -void udc_set_nak(int epid); -void udc_unset_nak (int epid); - -/* Higher level functions for abstracting away from specific device */ -int udc_endpoint_write(struct usb_endpoint_instance *endpoint); - -int udc_init (void); - -void udc_enable(struct usb_device_instance *device); -void udc_disable(void); - -void udc_connect(void); -void udc_disconnect(void); - -void udc_startup_events(struct usb_device_instance *device); -void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint); - -#endif diff --git a/include/usb/pxa27x_udc.h b/include/usb/pxa27x_udc.h index 7fdbe2ae0f..7eaa000303 100644 --- a/include/usb/pxa27x_udc.h +++ b/include/usb/pxa27x_udc.h @@ -22,35 +22,11 @@ /* Endpoint parameters */ #define MAX_ENDPOINTS 4 -#define EP_MAX_PACKET_SIZE 64 #define EP0_MAX_PACKET_SIZE 16 + #define UDC_OUT_ENDPOINT 0x02 -#define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE #define UDC_IN_ENDPOINT 0x01 -#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE #define UDC_INT_ENDPOINT 0x05 -#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE -#define UDC_BULK_PACKET_SIZE EP_MAX_PACKET_SIZE - -void udc_irq(void); -/* Flow control */ -void udc_set_nak(int epid); -void udc_unset_nak(int epid); - -/* Higher level functions for abstracting away from specific device */ -int udc_endpoint_write(struct usb_endpoint_instance *endpoint); - -int udc_init(void); - -void udc_enable(struct usb_device_instance *device); -void udc_disable(void); - -void udc_connect(void); -void udc_disconnect(void); - -void udc_startup_events(struct usb_device_instance *device); -void udc_setup_ep(struct usb_device_instance *device, - unsigned int ep, struct usb_endpoint_instance *endpoint); #endif diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 734c6cd2f7..7f49a4e2d5 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -10,6 +10,7 @@ #define __S3C_USB_GADGET #include +#include #include #include #include @@ -19,7 +20,7 @@ /*-------------------------------------------------------------------------*/ /* DMA bounce buffer size, 16K is enough even for mass storage */ -#define DMA_BUFFER_SIZE (4096*4) +#define DMA_BUFFER_SIZE (16*SZ_1K) #define EP0_FIFO_SIZE 64 #define EP_FIFO_SIZE 512 @@ -81,9 +82,6 @@ struct s3c_udc { struct s3c_plat_otg_data *pdata; - void *dma_buf[S3C_MAX_ENDPOINTS+1]; - dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1]; - int ep0state; struct s3c_ep ep[S3C_MAX_ENDPOINTS]; @@ -110,5 +108,6 @@ struct s3c_plat_otg_data { unsigned int regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; + unsigned int usb_gusbcfg; }; #endif diff --git a/include/usb/udc.h b/include/usb/udc.h new file mode 100644 index 0000000000..b2e0c6b6f5 --- /dev/null +++ b/include/usb/udc.h @@ -0,0 +1,53 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef USB_UDC_H +#define USB_UDC_H + +#ifndef EP0_MAX_PACKET_SIZE +#define EP0_MAX_PACKET_SIZE 64 +#endif + +#ifndef EP_MAX_PACKET_SIZE +#define EP_MAX_PACKET_SIZE 64 +#endif + +#if !defined(CONFIG_PPC) +/* mpc8xx_udc.h will set these values */ +#define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE +#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE +#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE +#define UDC_BULK_PACKET_SIZE EP_MAX_PACKET_SIZE +#endif + +#define UDC_BULK_HS_PACKET_SIZE 512 + +#ifndef UDC_INT_ENDPOINT +#define UDC_INT_ENDPOINT 1 +#endif + +#ifndef UDC_OUT_ENDPOINT +#define UDC_OUT_ENDPOINT 2 +#endif + +#ifndef UDC_IN_ENDPOINT +#define UDC_IN_ENDPOINT 3 +#endif + +/* function declarations */ +int udc_init(void); +void udc_irq(void); +int udc_endpoint_write(struct usb_endpoint_instance *endpoint); +void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, + struct usb_endpoint_instance *endpoint); +void udc_connect(void); +void udc_disconnect(void); +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); +void udc_startup_events(struct usb_device_instance *device); + +/* Flow control */ +void udc_set_nak(int epid); +void udc_unset_nak(int epid); + +#endif diff --git a/include/usb_defs.h b/include/usb_defs.h index 0cf5f2da89..236a5ecdf6 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -63,6 +63,25 @@ #define USB_DIR_OUT 0 #define USB_DIR_IN 0x80 +/* + * bmRequestType: USB Device Requests, table 9.2 USB 2.0 spec. + * (shifted) direction/type/recipient. + */ +#define DeviceRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) + +#define DeviceOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) + +#define InterfaceRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define EndpointRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define EndpointOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + /* Descriptor types */ #define USB_DT_DEVICE 0x01 #define USB_DT_CONFIG 0x02 diff --git a/include/usb_ether.h b/include/usb_ether.h index 678c9dff25..b38d037fbe 100644 --- a/include/usb_ether.h +++ b/include/usb_ether.h @@ -40,23 +40,31 @@ struct ueth_data { }; /* - * Function definitions for each USB ethernet driver go here, bracketed by - * #ifdef CONFIG_USB_ETHER_xxx...#endif + * Function definitions for each USB ethernet driver go here + * (declaration is unconditional, compilation is conditional) */ -#ifdef CONFIG_USB_ETHER_ASIX void asix_eth_before_probe(void); int asix_eth_probe(struct usb_device *dev, unsigned int ifnum, struct ueth_data *ss); int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss, struct eth_device *eth); -#endif -#ifdef CONFIG_USB_ETHER_SMSC95XX +void ax88179_eth_before_probe(void); +int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss); +int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth); + +void mcs7830_eth_before_probe(void); +int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum, + struct ueth_data *ss); +int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss, + struct eth_device *eth); + void smsc95xx_eth_before_probe(void); int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, struct ueth_data *ss); int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, struct eth_device *eth); -#endif #endif /* __USB_ETHER_H__ */ diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h index 35cdcc3d8c..69b80cd1a3 100644 --- a/include/usb_mass_storage.h +++ b/include/usb_mass_storage.h @@ -9,34 +9,27 @@ #define __USB_MASS_STORAGE_H__ #define SECTOR_SIZE 0x200 +#include +#include -#include +/* Wait at maximum 60 seconds for cable connection */ +#define UMS_CABLE_READY_TIMEOUT 60 -struct ums_device { - struct mmc *mmc; - int dev_num; - int offset; - int part_size; -}; - -struct ums_board_info { - int (*read_sector)(struct ums_device *ums_dev, +struct ums { + int (*read_sector)(struct ums *ums_dev, ulong start, lbaint_t blkcnt, void *buf); - int (*write_sector)(struct ums_device *ums_dev, + int (*write_sector)(struct ums *ums_dev, ulong start, lbaint_t blkcnt, const void *buf); - void (*get_capacity)(struct ums_device *ums_dev, - long long int *capacity); + unsigned int start_sector; + unsigned int num_sectors; const char *name; - struct ums_device ums_dev; + block_dev_desc_t *block_dev; }; -extern void board_usb_init(void); - -extern int fsg_init(struct ums_board_info *); -extern void fsg_cleanup(void); -extern struct ums_board_info *board_ums_init(unsigned int, - unsigned int, unsigned int); -extern int usb_gadget_handle_interrupts(void); -extern int fsg_main_thread(void *); +extern struct ums *ums; +int fsg_init(struct ums *); +void fsg_cleanup(void); +int fsg_main_thread(void *); +int fsg_add(struct usb_configuration *c); #endif /* __USB_MASS_STORAGE_H__ */ diff --git a/include/usbroothubdes.h b/include/usbroothubdes.h new file mode 100644 index 0000000000..adb70cd6af --- /dev/null +++ b/include/usbroothubdes.h @@ -0,0 +1,129 @@ +/* + * USB virtual root hub descriptors + * + * (C) Copyright 2014 + * Stephen Warren swarren@wwwdotorg.org + * + * Based on ohci-hcd.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __USBROOTHUBDES_H__ +#define __USBROOTHUBDES_H__ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01, /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + * Bit 7: Bus-powered + * 6: Self-powered, + * 5 Remote-wakwup, + * 4..0: resvd + */ + 0x00, /* __u8 MaxPower; */ + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff, /* __u8 ep_bInterval; 255 ms */ +}; + +#ifdef WANT_USB_ROOT_HUB_HUB_DES +static unsigned char root_hub_hub_des[] = { + 0x09, /* __u8 bLength; */ + 0x29, /* __u8 bDescriptorType; Hub-descriptor */ + 0x02, /* __u8 bNbrPorts; */ + 0x00, /* __u16 wHubCharacteristics; */ + 0x00, + 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ + 0x00, /* __u8 bHubContrCurrent; 0 mA */ + 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ + 0xff, /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ +}; +#endif + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 32, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'U', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '-', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'B', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +#endif diff --git a/include/uuid.h b/include/uuid.h new file mode 100644 index 0000000000..93027c1b28 --- /dev/null +++ b/include/uuid.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __UUID_H__ +#define __UUID_H__ + +/* This is structure is in big-endian */ +struct uuid { + unsigned int time_low; + unsigned short time_mid; + unsigned short time_hi_and_version; + unsigned char clock_seq_hi_and_reserved; + unsigned char clock_seq_low; + unsigned char node[6]; +} __packed; + +enum { + UUID_STR_FORMAT_STD, + UUID_STR_FORMAT_GUID +}; + +#define UUID_STR_LEN 36 +#define UUID_BIN_LEN sizeof(struct uuid) + +#define UUID_VERSION_MASK 0xf000 +#define UUID_VERSION_SHIFT 12 +#define UUID_VERSION 0x4 + +#define UUID_VARIANT_MASK 0xc0 +#define UUID_VARIANT_SHIFT 7 +#define UUID_VARIANT 0x1 + +int uuid_str_valid(const char *uuid); +int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format); +void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format); +void gen_rand_uuid(unsigned char *uuid_bin); +void gen_rand_uuid_str(char *uuid_str, int str_format); +#endif diff --git a/include/vbe.h b/include/vbe.h new file mode 100644 index 0000000000..c5deee9eca --- /dev/null +++ b/include/vbe.h @@ -0,0 +1,108 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * Copyright (c) 2009 Pattrick Hueper + * All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ +#ifndef _VBE_H +#define _VBE_H + +/* these structs are for input from and output to OF */ +struct __packed screen_info { + u8 display_type; /* 0=NONE, 1= analog, 2=digital */ + u16 screen_width; + u16 screen_height; + /* bytes per line in framebuffer, may be more than screen_width */ + u16 screen_linebytes; + u8 color_depth; /* color depth in bits per pixel */ + u32 framebuffer_address; + u8 edid_block_zero[128]; +}; + +struct __packed screen_info_input { + u8 signature[4]; + u16 size_reserved; + u8 monitor_number; + u16 max_screen_width; + u8 color_depth; +}; + +/* these structs only store the required a subset of the VBE-defined fields */ +struct __packed vbe_info { + char signature[4]; + u16 version; + u32 oem_string_ptr; + u32 capabilities; + u32 modes_ptr; + u16 total_memory; + u16 oem_version; + u32 vendor_name_ptr; + u32 product_name_ptr; + u32 product_rev_ptr; +}; + +struct __packed vesa_mode_info { + u16 mode_attributes; /* 00 */ + u8 win_a_attributes; /* 02 */ + u8 win_b_attributes; /* 03 */ + u16 win_granularity; /* 04 */ + u16 win_size; /* 06 */ + u16 win_a_segment; /* 08 */ + u16 win_b_segment; /* 0a */ + u32 win_func_ptr; /* 0c */ + u16 bytes_per_scanline; /* 10 */ + u16 x_resolution; /* 12 */ + u16 y_resolution; /* 14 */ + u8 x_charsize; /* 16 */ + u8 y_charsize; /* 17 */ + u8 number_of_planes; /* 18 */ + u8 bits_per_pixel; /* 19 */ + u8 number_of_banks; /* 20 */ + u8 memory_model; /* 21 */ + u8 bank_size; /* 22 */ + u8 number_of_image_pages; /* 23 */ + u8 reserved_page; + u8 red_mask_size; + u8 red_mask_pos; + u8 green_mask_size; + u8 green_mask_pos; + u8 blue_mask_size; + u8 blue_mask_pos; + u8 reserved_mask_size; + u8 reserved_mask_pos; + u8 direct_color_mode_info; + u32 phys_base_ptr; + u32 offscreen_mem_offset; + u16 offscreen_mem_size; + u8 reserved[206]; +}; + +struct vbe_mode_info { + u16 video_mode; + bool valid; + union { + struct vesa_mode_info vesa; + u8 mode_info_block[256]; + }; +}; + +struct vbe_ddc_info { + u8 port_number; /* i.e. monitor number */ + u8 edid_transfer_time; + u8 ddc_level; + u8 edid_block_zero[128]; +}; + +#define VESA_GET_INFO 0x4f00 +#define VESA_GET_MODE_INFO 0x4f01 +#define VESA_SET_MODE 0x4f02 +#define VESA_GET_CUR_MODE 0x4f03 + +struct graphic_device; +int vbe_get_video_info(struct graphic_device *gdev); + +#endif diff --git a/include/video.h b/include/video.h index f7e27f8477..673aa2ec56 100644 --- a/include/video.h +++ b/include/video.h @@ -11,9 +11,11 @@ /* Video functions */ -int video_init (void *videobase); -void video_putc (const char c); -void video_puts (const char *s); +struct stdio_dev; + +int video_init(void *videobase); +void video_putc(struct stdio_dev *dev, const char c); +void video_puts(struct stdio_dev *dev, const char *s); /** * Display a BMP format bitmap on the screen @@ -63,4 +65,8 @@ void video_position_cursor(unsigned col, unsigned row); /* Clear the display */ void video_clear(void); +#if defined(CONFIG_FORMIKE) +int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +#endif #endif diff --git a/include/video_ad7176.h b/include/video_ad7176.h deleted file mode 100644 index 6447b15f20..0000000000 --- a/include/video_ad7176.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _VIDEO_AD7176_H_ -#define _VIDEO_AD7176_H_ - -#define VIDEO_ENCODER_NAME "Analog Devices AD7176" - -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */ -#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ - -#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ -#undef VIDEO_MODE_RGB -#define VIDEO_MODE_BPP 16 - -#ifdef VIDEO_MODE_PAL -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 576 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 480 -#endif - -#ifdef VIDEO_MODE_NTSC -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 525 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 400 -#endif - -static unsigned char video_encoder_data[] = { -#ifdef VIDEO_MODE_NTSC - 0x04, /* Mode Register 0 */ -#ifdef VIDEO_DEBUG_COLORBARS - 0x82, -#else - 0x02, /* Mode Register 1 */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0x16, /* Subcarrier Freq 0 */ - 0x7c, /* Subcarrier Freq 1 */ - 0xf0, /* Subcarrier Freq 2 */ - 0x21, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x00 /* Mode Register 3 */ - -#endif /* VIDEO_MODE_NTSC */ - -#ifdef VIDEO_MODE_PAL - 0x05, /* Mode Register 0 */ -#ifdef VIDEO_DEBUG_COLORBARS - 0x82, -#else - 0x02, /* Mode Register 1 (2) */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x0a, /* Timing Register 0 (a) */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 (8) */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x00 /* Mode Register 3 */ -#endif /* VIDEO_MODE_PAL */ -} ; - -#endif /* _VIDEO_AD7176_H_ */ diff --git a/include/video_ad7177.h b/include/video_ad7177.h deleted file mode 100644 index 7226ed2e2f..0000000000 --- a/include/video_ad7177.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _VIDEO_AD7177_H_ -#define _VIDEO_AD7177_H_ - -/* #define VIDEO_DEBUG_DISABLE_COLORS 0 */ - -#define VIDEO_ENCODER_NAME "Analog Devices AD7177" - -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */ -#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ - -#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ -#undef VIDEO_MODE_RGB -#define VIDEO_MODE_BPP 16 - -#ifdef VIDEO_MODE_PAL -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 576 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 480 -#endif - -#ifdef VIDEO_MODE_NTSC -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 525 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 400 -#endif - -static unsigned char - video_encoder_data[] = { -#ifdef VIDEO_MODE_NTSC - 0x04, /* Mode Register 0 */ -#ifdef VIDEO_DEBUG_COLORBARS - 0xc2, -#else - 0x42, /* Mode Register 1 */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0x16, /* Subcarrier Freq 0 */ - 0x7c, /* Subcarrier Freq 1 */ - 0xf0, /* Subcarrier Freq 2 */ - 0x21, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08, /* Mode Register 3 */ - -#endif /* VIDEO_MODE_NTSC */ - -#ifdef VIDEO_MODE_PAL -#ifdef VIDEO_MODE_RGB_OUT - - 0x69, /* Mode Register 0 */ -#ifdef VIDEO_DEBUG_COLORBARS - 0xc0, /* Mode Register 1 (c0) */ -#else - 0x40, /* Mode Register 1 (c0) */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x28, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08, /* Mode Register 3 */ - -#else /* ! VIDEO_MODE_RGB_OUT */ - - 0x09, /* Mode Register 0 (was 01) */ -#ifdef VIDEO_DEBUG_COLORBARS - 0xd8, /* */ -#else - 0x59, /* Mode Register 1 (was 58) */ -#endif /* VIDEO_DEBUG_COLORBARS */ - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 (was a) */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ -#ifdef VIDEO_DEBUG_LOWPOWER -#ifdef VIDEO_DEBUG_DISABLE_COLORS - 0x98, /* Mode Register 2 */ -#else - 0x88, /* Mode Register 2 */ -#endif /* VIDEO_DEBUG_DISABLE_COLORS */ -#else /* ! VIDEO_DEBUG_LOWPOWER */ -#ifdef VIDEO_DEBUG_DISABLE_COLORS - 0x18, /* Mode Register 2 */ -#else - 0x08, /* Mode Register 2 */ -#endif /* VIDEO_DEBUG_DISABLE_COLORS */ -#endif /* VIDEO_DEBUG_LOWPOWER */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08 /* Mode Register 3 */ -#endif /* VIDEO_MODE_RGB_OUT */ -#endif /* VIDEO_MODE_PAL */ - } ; - -#endif /* _VIDEO_AD7177_H_ */ diff --git a/include/video_ad7179.h b/include/video_ad7179.h deleted file mode 100644 index 67c1ec0ce4..0000000000 --- a/include/video_ad7179.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2003 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _VIDEO_AD7179_H_ -#define _VIDEO_AD7179_H_ - -/* - * The video encoder data are board specific now! - */ - -#if defined(CONFIG_RRVISION) -#include "../board/RRvision/video_ad7179.h" -#else -#error "Please provide a board-specific video_ad7179.h" -#endif - -#endif /* _VIDEO_AD7179_H_ */ diff --git a/include/video_fb.h b/include/video_fb.h index 028e2a6aea..55ec24dbee 100644 --- a/include/video_fb.h +++ b/include/video_fb.h @@ -18,8 +18,13 @@ #ifndef _VIDEO_FB_H_ #define _VIDEO_FB_H_ +#if defined(CONFIG_SYS_CONSOLE_FG_COL) && defined(CONFIG_SYS_CONSOLE_BG_COL) +#define CONSOLE_BG_COL CONFIG_SYS_CONSOLE_BG_COL +#define CONSOLE_FG_COL CONFIG_SYS_CONSOLE_FG_COL +#else #define CONSOLE_BG_COL 0x00 #define CONSOLE_FG_COL 0xa0 +#endif /* * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT @@ -35,7 +40,7 @@ /* Export Graphic Driver Control */ /******************************************************************************/ -typedef struct { +typedef struct graphic_device { unsigned int isaBase; unsigned int pciBase; unsigned int dprBase; diff --git a/include/video_font.h b/include/video_font.h index 7ef9519997..96b9edb0da 100644 --- a/include/video_font.h +++ b/include/video_font.h @@ -8,9 +8,10 @@ #ifndef _VIDEO_FONT_ #define _VIDEO_FONT_ -#define VIDEO_FONT_CHARS 256 -#define VIDEO_FONT_WIDTH 8 -#define VIDEO_FONT_HEIGHT 16 -#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT) +#ifdef CONFIG_VIDEO_FONT_4X6 +#include +#else +#include +#endif #endif /* _VIDEO_FONT_ */ diff --git a/include/video_font_4x6.h b/include/video_font_4x6.h new file mode 100644 index 0000000000..6aeed092ad --- /dev/null +++ b/include/video_font_4x6.h @@ -0,0 +1,2153 @@ +/* Hand composed "Minuscule" 4x6 font, with binary data generated using + * Perl stub. + * + * Use 'perl -x mini_4x6.c < mini_4x6.c > new_version.c' to regenerate + * binary data. + * + * Created by Kenneth Albanowski. + * No rights reserved, released to the public domain. + * + * Version 1.0 + */ + +/* + +#!/usr/bin/perl -pn + +s{((0x)?[0-9a-fA-F]+)(.*\[([\*\ ]{4})\])}{ + + ($num,$pat,$bits) = ($1,$3,$4); + + $bits =~ s/([^\s0])|(.)/ defined($1) + 0 /ge; + + $num = ord(pack("B8", $bits)); + $num |= $num >> 4; + $num = sprintf("0x%.2x", $num); + + #print "$num,$pat,$bits\n"; + + $num . $pat; +}ge; + +__END__; +*/ + +/* Note: binary data consists of one byte for each row of each character top + to bottom, character 0 to character 255, six bytes per character. Each + byte contains the same four character bits in both nybbles. + MSBit to LSBit = left to right. + */ + +#ifndef _VIDEO_FONT_DATA_ +#define _VIDEO_FONT_DATA_ + +#define VIDEO_FONT_CHARS 256 +#define VIDEO_FONT_WIDTH 4 +#define VIDEO_FONT_HEIGHT 6 +#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT) + +static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { + + /*{*/ + /* Char 0: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 1: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 2: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 3: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 4: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 5: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 6: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 7: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 8: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 9: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 10: '' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 11: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 12: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 13: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 14: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 15: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 16: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 17: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 18: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 19: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 20: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 21: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 22: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 23: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 24: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 25: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 26: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 27: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 28: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 29: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 30: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 31: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 32: ' ' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 33: '!' */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 34: '"' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 35: '#' */ + 0xaa, /*= [* * ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 36: '$' */ + 0x44, /*= [ * ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 37: '%' */ + 0xaa, /*= [* * ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 38: '&' */ + 0x66, /*= [ ** ] */ + 0x99, /*= [* *] */ + 0x66, /*= [ ** ] */ + 0xaa, /*= [* * ] */ + 0xdd, /*= [** *] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 39: ''' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 40: '(' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 41: ')' */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 42: '*' */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 43: '+' */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 44: ',' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 45: '-' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 46: '.' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 47: '/' */ + 0x00, /*= [ ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 48: '0' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 49: '1' */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 50: '2' */ + 0xcc, /*= [** ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ + /* Char 51: '3' */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x66, /*= [ ** ] */ + 0x22, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 52: '4' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 53: '5' */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 54: '6' */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 55: '7' */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 56: '8' */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 57: '9' */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 58: ':' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 59: ';' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + /*}*/ + /*{*/ /* Char 60: '<' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 61: '=' */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 62: '>' */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 63: '?' */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 64: '@' */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 65: 'A' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 66: 'B' */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 67: 'C' */ + 0x66, /*= [ ** ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 68: 'D' */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 69: 'E' */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 70: 'F' */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 71: 'G' */ + 0x66, /*= [ ** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 72: 'H' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 73: 'I' */ + 0xee, /*= [*** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 74: 'J' */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 75: 'K' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 76: 'L' */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 77: 'M' */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 78: 'N' */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 79: 'O' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 80: 'P' */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 81: 'Q' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 82: 'R' */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 83: 'S' */ + 0x66, /*= [ ** ] */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 84: 'T' */ + 0xee, /*= [*** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 85: 'U' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 86: 'V' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 87: 'W' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 88: 'X' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 89: 'Y' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 90: 'Z' */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 91: '[' */ + 0x66, /*= [ ** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 92: '\' */ + 0x00, /*= [ ] */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 93: ']' */ + 0x66, /*= [ ** ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 94: '^' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 95: '_' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + /*}*/ + /*{*/ /* Char 96: '`' */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 97: 'a' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 98: 'b' */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 99: 'c' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0x88, /*= [* ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 100: 'd' */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x66, /*= [ ** ] */ + 0xaa, /*= [* * ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 101: 'e' */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 102: 'f' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 103: 'g' */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0xaa, /*= [* * ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 104: 'h' */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 105: 'i' */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 106: 'j' */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 107: 'k' */ + 0x00, /*= [ ] */ + 0x88, /*= [* ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 108: 'l' */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 109: 'm' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 110: 'n' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 111: 'o' */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 112: 'p' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ + 0x88, /*= [* ] */ + /*}*/ + /*{*/ /* Char 113: 'q' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0xaa, /*= [* * ] */ + 0x66, /*= [ ** ] */ + 0x22, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 114: 'r' */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 115: 's' */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0xcc, /*= [** ] */ + 0x22, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 116: 't' */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 117: 'u' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 118: 'v' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 119: 'w' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 120: 'x' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 121: 'y' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0xcc, /*= [** ] */ + /*}*/ + /*{*/ /* Char 122: 'z' */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0x66, /*= [ ** ] */ + 0xcc, /*= [** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 123: '{' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 124: '|' */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 125: '}' */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x66, /*= [ ** ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 126: '~' */ + 0x55, /*= [ * *] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 127: '' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 128: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 129: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 130: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 131: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 132: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 133: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 134: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 135: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 136: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 137: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 138: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 139: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 140: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 141: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 142: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 143: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 144: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 145: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 146: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 147: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 148: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 149: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 150: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 151: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 152: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 153: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 154: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 155: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 156: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 157: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 158: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 159: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 160: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 161: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 162: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 163: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 164: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 165: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 166: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 167: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 168: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 169: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 170: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 171: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 172: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 173: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 174: */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0xcc, /*= [** ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 175: */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0x66, /*= [ ** ] */ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 176: */ + 0x88, /*= [* ] */ + 0x22, /*= [ * ] */ + 0x88, /*= [* ] */ + 0x22, /*= [ * ] */ + 0x88, /*= [* ] */ + 0x22, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 177: */ + 0xaa, /*= [* * ] */ + 0x55, /*= [ * *] */ + 0xaa, /*= [* * ] */ + 0x55, /*= [ * *] */ + 0xaa, /*= [* * ] */ + 0x55, /*= [ * *] */ + /*}*/ + /*{*/ /* Char 178: */ + 0xdd, /*= [** *] */ + 0xbb, /*= [* **] */ + 0xdd, /*= [** *] */ + 0xbb, /*= [* **] */ + 0xdd, /*= [** *] */ + 0xbb, /*= [* **] */ + /*}*/ + /*{*/ /* Char 179: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 180: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 181: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 182: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 183: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 184: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 185: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 186: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 187: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 188: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 189: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 190: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 191: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 192: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x77, /*= [ ***] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 193: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xff, /*= [****] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 194: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 195: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x77, /*= [ ***] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 196: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 197: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xff, /*= [****] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 198: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x77, /*= [ ***] */ + 0x77, /*= [ ***] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 199: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x77, /*= [ ***] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 200: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x77, /*= [ ***] */ + 0x77, /*= [ ***] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 201: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x77, /*= [ ***] */ + 0x77, /*= [ ***] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 202: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 203: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 204: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x77, /*= [ ***] */ + 0x77, /*= [ ***] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 205: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 206: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 207: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 208: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xff, /*= [****] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 209: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 210: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 211: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x77, /*= [ ***] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 212: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x77, /*= [ ***] */ + 0x77, /*= [ ***] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 213: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x77, /*= [ ***] */ + 0x77, /*= [ ***] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 214: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x77, /*= [ ***] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 215: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xff, /*= [****] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ + /*{*/ /* Char 216: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 217: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 218: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x77, /*= [ ***] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ + /*{*/ /* Char 219: */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + /*}*/ + /*{*/ /* Char 220: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + /*}*/ + /*{*/ /* Char 221: */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + /*}*/ + /*{*/ /* Char 222: */ + 0x33, /*= [ **] */ + 0x33, /*= [ **] */ + 0x33, /*= [ **] */ + 0x33, /*= [ **] */ + 0x33, /*= [ **] */ + 0x33, /*= [ **] */ + /*}*/ + /*{*/ /* Char 223: */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 224: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 225: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 226: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 227: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 228: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 229: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 230: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 231: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 232: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 233: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 234: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 235: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 236: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 237: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 238: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 239: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 240: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 241: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 242: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 243: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 244: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 245: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 246: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 247: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 248: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 249: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 250: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 251: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 252: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 253: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 254: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ /* Char 255: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +}; + +#endif diff --git a/include/video_font_data.h b/include/video_font_data.h index 4e544f0d7f..346a162f56 100644 --- a/include/video_font_data.h +++ b/include/video_font_data.h @@ -8,7 +8,12 @@ #ifndef _VIDEO_FONT_DATA_ #define _VIDEO_FONT_DATA_ -static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { +#define VIDEO_FONT_CHARS 256 +#define VIDEO_FONT_WIDTH 8 +#define VIDEO_FONT_HEIGHT 16 +#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT) + +static unsigned char __maybe_unused video_fontdata[VIDEO_FONT_SIZE] = { /* 0 0x00 '^@' */ 0x00, /* 00000000 */ diff --git a/include/virtex2.h b/include/virtex2.h index 2e9a4f52da..503df9abae 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,43 +11,46 @@ #include -extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Virtex2_info(Xilinx_desc *desc); - /* * Slave SelectMap Implementation function table. */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_init_fn init; - Xilinx_err_fn err; - Xilinx_done_fn done; - Xilinx_clk_fn clk; - Xilinx_cs_fn cs; - Xilinx_wr_fn wr; - Xilinx_rdata_fn rdata; - Xilinx_wdata_fn wdata; - Xilinx_busy_fn busy; - Xilinx_abort_fn abort; - Xilinx_post_fn post; -} Xilinx_Virtex2_Slave_SelectMap_fns; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_init_fn init; + xilinx_err_fn err; + xilinx_done_fn done; + xilinx_clk_fn clk; + xilinx_cs_fn cs; + xilinx_wr_fn wr; + xilinx_rdata_fn rdata; + xilinx_wdata_fn wdata; + xilinx_busy_fn busy; + xilinx_abort_fn abort; + xilinx_post_fn post; +} xilinx_virtex2_slave_selectmap_fns; /* Slave Serial Implementation function table */ typedef struct { - Xilinx_pgm_fn pgm; - Xilinx_clk_fn clk; - Xilinx_rdata_fn rdata; - Xilinx_wdata_fn wdata; -} Xilinx_Virtex2_Slave_Serial_fns; + xilinx_pgm_fn pgm; + xilinx_clk_fn clk; + xilinx_rdata_fn rdata; + xilinx_wdata_fn wdata; +} xilinx_virtex2_slave_serial_fns; + +#if defined(CONFIG_FPGA_VIRTEX2) +extern struct xilinx_fpga_op virtex2_op; +# define FPGA_VIRTEX2_OPS &virtex2_op +#else +# define FPGA_VIRTEX2_OPS NULL +#endif /* Device Image Sizes (in bytes) *********************************************************************/ -#define XILINX_XC2V40_SIZE (338208 / 8) -#define XILINX_XC2V80_SIZE (597408 / 8) -#define XILINX_XC2V250_SIZE (1591584 / 8) -#define XILINX_XC2V500_SIZE (2557857 / 8) +#define XILINX_XC2V40_SIZE (338208 / 8) +#define XILINX_XC2V80_SIZE (597408 / 8) +#define XILINX_XC2V250_SIZE (1591584 / 8) +#define XILINX_XC2V500_SIZE (2557857 / 8) #define XILINX_XC2V1000_SIZE (3749408 / 8) #define XILINX_XC2V1500_SIZE (5166240 / 8) #define XILINX_XC2V2000_SIZE (6808352 / 8) @@ -60,39 +63,51 @@ typedef struct { /* Descriptor Macros *********************************************************************/ #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #endif /* _VIRTEX2_H_ */ diff --git a/include/vsc9953.h b/include/vsc9953.h new file mode 100644 index 0000000000..3d11b87a1f --- /dev/null +++ b/include/vsc9953.h @@ -0,0 +1,402 @@ +/* + * vsc9953.h + * + * Driver for the Vitesse VSC9953 L2 Switch + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + */ + +#ifndef _VSC9953_H_ +#define _VSC9953_H_ + +#include +#include +#include +#include + +#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) + +#define VSC9953_SYS_OFFSET 0x010000 +#define VSC9953_DEV_GMII_OFFSET 0x100000 +#define VSC9953_QSYS_OFFSET 0x200000 +#define VSC9953_ANA_OFFSET 0x280000 +#define VSC9953_DEVCPU_GCB 0x070000 +#define VSC9953_ES0 0x040000 +#define VSC9953_IS1 0x050000 +#define VSC9953_IS2 0x060000 + +#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 +#define VSC9953_PHY_REGS_OFFST 0x0000AC + +#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001 +#define CONFIG_VSC9953_CORE_ENABLE 0x80 +#define CONFIG_VSC9953_MEM_ENABLE 0x40 +#define CONFIG_VSC9953_MEM_INIT 0x20 + +#define CONFIG_VSC9953_PORT_ENA 0x00003a00 +#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011 +#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011 +#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515 +#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043 +#define CONFIG_VSC9953_CLOCK_CFG 0x00000001 +#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001 +#define CONFIG_VSC9953_PFC_FC 0x00000001 +#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000 +#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000 +#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000 +#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe +#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff +#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000 +#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee + +#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff +#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004 +#define VSC9953_MAX_PORTS 10 +#define VSC9953_PORT_CHECK(port) \ + (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) +#define VSC9953_INTERNAL_PORT_CHECK(port) ( \ + ( \ + (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ + ) ? 0 : 1 \ +) + +#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" + +#define MIIMIND_OPR_PEND 0x00000004 + +struct vsc9953_mdio_info { + struct vsc9953_mii_mng *regs; + char *name; +}; + +/* VSC9953 ANA structure for T1040 U-boot*/ + +struct vsc9953_ana_port { + u32 vlan_cfg; + u32 drop_cfg; + u32 qos_cfg; + u32 vcap_cfg; + u32 vcap_s1_key_cfg[3]; + u32 vcap_s2_cfg; + u32 qos_pcp_dei_map_cfg[16]; + u32 cpu_fwd_cfg; + u32 cpu_fwd_bpdu_cfg; + u32 cpu_fwd_garp_cfg; + u32 cpu_fwd_ccm_cfg; + u32 port_cfg; + u32 pol_cfg; + u32 reserved[34]; +}; + +struct vsc9953_ana_pol { + u32 pol_pir_cfg; + u32 pol_cir_cfg; + u32 pol_mode_cfg; + u32 pol_pir_state; + u32 pol_cir_state; + u32 reserved1[3]; +}; + +struct vsc9953_ana_ana_tables { + u32 entry_lim[11]; + u32 an_moved; + u32 mach_data; + u32 macl_data; + u32 mac_access; + u32 mact_indx; + u32 vlan_access; + u32 vlan_tidx; +}; + +struct vsc9953_ana_ana { + u32 adv_learn; + u32 vlan_mask; + u32 anag_efil; + u32 an_events; + u32 storm_limit_burst; + u32 storm_limit_cfg[4]; + u32 isolated_prts; + u32 community_ports; + u32 auto_age; + u32 mac_options; + u32 learn_disc; + u32 agen_ctrl; + u32 mirror_ports; + u32 emirror_ports; + u32 flooding; + u32 flooding_ipmc; + u32 sflow_cfg[11]; + u32 port_mode[12]; +}; + +struct vsc9953_ana_pgid { + u32 port_grp_id[91]; +}; + +struct vsc9953_ana_pfc { + u32 pfc_cfg; + u32 reserved1[15]; +}; + +struct vsc9953_ana_pol_misc { + u32 pol_flowc[10]; + u32 reserved1[17]; + u32 pol_hyst; +}; + +struct vsc9953_ana_common { + u32 aggr_cfg; + u32 cpuq_cfg; + u32 cpuq_8021_cfg; + u32 dscp_cfg; + u32 dscp_rewr_cfg; + u32 vcap_rng_type_cfg; + u32 vcap_rng_val_cfg; + u32 discard_cfg; + u32 fid_cfg; +}; + +struct vsc9953_analyzer { + struct vsc9953_ana_port port[11]; + u32 reserved1[9536]; + struct vsc9953_ana_pol pol[164]; + struct vsc9953_ana_ana_tables ana_tables; + u32 reserved2[14]; + struct vsc9953_ana_ana ana; + u32 reserved3[22]; + struct vsc9953_ana_pgid port_id_tbl; + u32 reserved4[549]; + struct vsc9953_ana_pfc pfc[10]; + struct vsc9953_ana_pol_misc pol_misc; + u32 reserved5[196]; + struct vsc9953_ana_common common; +}; +/* END VSC9953 ANA structure for T1040 U-boot*/ + +/* VSC9953 DEV_GMII structure for T1040 U-boot*/ + +struct vsc9953_dev_gmii_port_mode { + u32 clock_cfg; + u32 port_misc; + u32 reserved1; + u32 eee_cfg; +}; + +struct vsc9953_dev_gmii_mac_cfg_status { + u32 mac_ena_cfg; + u32 mac_mode_cfg; + u32 mac_maxlen_cfg; + u32 mac_tags_cfg; + u32 mac_adv_chk_cfg; + u32 mac_ifg_cfg; + u32 mac_hdx_cfg; + u32 mac_fc_mac_low_cfg; + u32 mac_fc_mac_high_cfg; + u32 mac_sticky; +}; + +struct vsc9953_dev_gmii { + struct vsc9953_dev_gmii_port_mode port_mode; + struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; +}; + +/* END VSC9953 DEV_GMII structure for T1040 U-boot*/ + +/* VSC9953 QSYS structure for T1040 U-boot*/ + +struct vsc9953_qsys_hsch { + u32 cir_cfg; + u32 reserved1; + u32 se_cfg; + u32 se_dwrr_cfg[8]; + u32 cir_state; + u32 reserved2[20]; +}; + +struct vsc9953_qsys_sys { + u32 port_mode[12]; + u32 switch_port_mode[11]; + u32 stat_cnt_cfg; + u32 eee_cfg[10]; + u32 eee_thrs; + u32 igr_no_sharing; + u32 egr_no_sharing; + u32 sw_status[11]; + u32 ext_cpu_cfg; + u32 cpu_group_map; + u32 reserved1[23]; +}; + +struct vsc9953_qsys_qos_cfg { + u32 red_profile[16]; + u32 res_qos_mode; +}; + +struct vsc9953_qsys_drop_cfg { + u32 egr_drop_mode; +}; + +struct vsc9953_qsys_mmgt { + u32 eq_cntrl; + u32 reserved1; +}; + +struct vsc9953_qsys_hsch_misc { + u32 hsch_misc_cfg; + u32 reserved1[546]; +}; + +struct vsc9953_qsys_res_ctrl { + u32 res_cfg; + u32 res_stat; + +}; + +struct vsc9953_qsys_reg { + struct vsc9953_qsys_hsch hsch[108]; + struct vsc9953_qsys_sys sys; + struct vsc9953_qsys_qos_cfg qos_cfg; + struct vsc9953_qsys_drop_cfg drop_cfg; + struct vsc9953_qsys_mmgt mmgt; + struct vsc9953_qsys_hsch_misc hsch_misc; + struct vsc9953_qsys_res_ctrl res_ctrl[1024]; +}; + +/* END VSC9953 QSYS structure for T1040 U-boot*/ + +/* VSC9953 SYS structure for T1040 U-boot*/ + +struct vsc9953_sys_stat { + u32 rx_cntrs[64]; + u32 tx_cntrs[64]; + u32 drop_cntrs[64]; + u32 reserved1[6]; +}; + +struct vsc9953_sys_sys { + u32 reset_cfg; + u32 reserved1; + u32 vlan_etype_cfg; + u32 port_mode[12]; + u32 front_port_mode[10]; + u32 frame_aging; + u32 stat_cfg; + u32 reserved2[50]; +}; + +struct vsc9953_sys_pause_cfg { + u32 pause_cfg[11]; + u32 pause_tot_cfg; + u32 tail_drop_level[11]; + u32 tot_tail_drop_lvl; + u32 mac_fc_cfg[10]; +}; + +struct vsc9953_sys_mmgt { + u16 free_cnt; +}; + +struct vsc9953_system_reg { + struct vsc9953_sys_stat stat; + struct vsc9953_sys_sys sys; + struct vsc9953_sys_pause_cfg pause_cfg; + struct vsc9953_sys_mmgt mmgt; +}; + +/* END VSC9953 SYS structure for T1040 U-boot*/ + + +/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ + +struct vsc9953_chip_regs { + u32 chipd_id; + u32 gpr; + u32 soft_rst; +}; + +struct vsc9953_gpio { + u32 gpio_out_set[10]; + u32 gpio_out_clr[10]; + u32 gpio_out[10]; + u32 gpio_in[10]; +}; + +struct vsc9953_mii_mng { + u32 miimstatus; + u32 reserved1; + u32 miimcmd; + u32 miimdata; + u32 miimcfg; + u32 miimscan_0; + u32 miimscan_1; + u32 miiscan_lst_rslts; + u32 miiscan_lst_rslts_valid; +}; + +struct vsc9953_mii_read_scan { + u32 mii_scan_results_sticky[2]; +}; + +struct vsc9953_devcpu_gcb { + struct vsc9953_chip_regs chip_regs; + struct vsc9953_gpio gpio; + struct vsc9953_mii_mng mii_mng[2]; + struct vsc9953_mii_read_scan mii_read_scan; +}; + +/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ + +/* VSC9953 IS* structure for T1040 U-boot*/ + +struct vsc9953_vcap_core_cfg { + u32 vcap_update_ctrl; + u32 vcap_mv_cfg; +}; + +struct vsc9953_vcap { +struct vsc9953_vcap_core_cfg vcap_core_cfg; +}; + +/* END VSC9953 IS* structure for T1040 U-boot*/ + +#define VSC9953_PORT_INFO_INITIALIZER(idx) \ +{ \ + .enabled = 0, \ + .phyaddr = 0, \ + .index = idx, \ + .phy_regs = NULL, \ + .enet_if = PHY_INTERFACE_MODE_NONE, \ + .bus = NULL, \ + .phydev = NULL, \ +} + +/* Structure to describe a VSC9953 port */ +struct vsc9953_port_info { + u8 enabled; + u8 phyaddr; + int index; + void *phy_regs; + phy_interface_t enet_if; + struct mii_dev *bus; + struct phy_device *phydev; +}; + +/* Structure to describe a VSC9953 switch */ +struct vsc9953_info { + struct vsc9953_port_info port[VSC9953_MAX_PORTS]; +}; + +void vsc9953_init(bd_t *bis); + +void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus); +void vsc9953_port_info_set_phy_address(int port, int address); +void vsc9953_port_enable(int port); +void vsc9953_port_disable(int port); +void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int); + +#endif /* _VSC9953_H_ */ diff --git a/include/vsprintf.h b/include/vsprintf.h index 2ac41d1923..5624482d57 100644 --- a/include/vsprintf.h +++ b/include/vsprintf.h @@ -2,7 +2,7 @@ * (C) Copyright 2000-2009 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __VSPRINTF_H diff --git a/include/vxworks.h b/include/vxworks.h index c5d1577f9c..122043c941 100644 --- a/include/vxworks.h +++ b/include/vxworks.h @@ -9,6 +9,9 @@ #define _VXWORKS_H_ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +void boot_prep_vxworks(bootm_headers_t *images); +void boot_jump_vxworks(bootm_headers_t *images); +void do_bootvx_fdt(bootm_headers_t *images); /* * Use bootaddr to find the location in memory that VxWorks diff --git a/include/watchdog.h b/include/watchdog.h index b2219044dd..9273fa1e80 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -2,7 +2,7 @@ * (C) Copyright 2001 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -21,7 +21,8 @@ int init_func_watchdog_reset(void); #endif -#ifdef CONFIG_WATCHDOG +#if defined(CONFIG_SYS_GENERIC_BOARD) && \ + (defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)) #define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, #define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, #else @@ -95,4 +96,8 @@ int init_func_watchdog_reset(void); #if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__) void hw_watchdog_init(void); #endif + +#if defined(CONFIG_MPC85xx) && !defined(__ASSEMBLY__) + void init_85xx_watchdog(void); +#endif #endif /* _WATCHDOG_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 00a585e5fc..aebcb3bfdf 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -12,7 +12,7 @@ /* Xilinx types *********************************************************************/ -typedef enum { /* typedef Xilinx_iface */ +typedef enum { /* typedef xilinx_iface */ min_xilinx_iface_type, /* low range check value */ slave_serial, /* serial data and external clock */ master_serial, /* serial data w/ internal clock (not used) */ @@ -22,48 +22,59 @@ typedef enum { /* typedef Xilinx_iface */ slave_selectmap, /* slave SelectMap (virtex2) */ devcfg, /* devcfg interface (zynq) */ max_xilinx_iface_type /* insert all new types before this */ -} Xilinx_iface; /* end, typedef Xilinx_iface */ +} xilinx_iface; /* end, typedef xilinx_iface */ -typedef enum { /* typedef Xilinx_Family */ +typedef enum { /* typedef xilinx_family */ min_xilinx_type, /* low range check value */ - Xilinx_Spartan2, /* Spartan-II Family */ - Xilinx_VirtexE, /* Virtex-E Family */ - Xilinx_Virtex2, /* Virtex2 Family */ - Xilinx_Spartan3, /* Spartan-III Family */ + xilinx_spartan2, /* Spartan-II Family */ + xilinx_virtexE, /* Virtex-E Family */ + xilinx_virtex2, /* Virtex2 Family */ + xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ max_xilinx_type /* insert all new types before this */ -} Xilinx_Family; /* end, typedef Xilinx_Family */ +} xilinx_family; /* end, typedef xilinx_family */ -typedef struct { /* typedef Xilinx_desc */ - Xilinx_Family family; /* part type */ - Xilinx_iface iface; /* interface type */ +typedef struct { /* typedef xilinx_desc */ + xilinx_family family; /* part type */ + xilinx_iface iface; /* interface type */ size_t size; /* bytes of data part can accept */ void *iface_fns; /* interface function table */ int cookie; /* implementation specific cookie */ + struct xilinx_fpga_op *operations; /* operations */ char *name; /* device name in bitstream */ -} Xilinx_desc; /* end, typedef Xilinx_desc */ +} xilinx_desc; /* end, typedef xilinx_desc */ + +struct xilinx_fpga_op { + int (*load)(xilinx_desc *, const void *, size_t, bitstream_type); + int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *); + int (*dump)(xilinx_desc *, const void *, size_t); + int (*info)(xilinx_desc *); +}; /* Generic Xilinx Functions *********************************************************************/ -extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); -extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int xilinx_info(Xilinx_desc *desc); +int xilinx_load(xilinx_desc *desc, const void *image, size_t size, + bitstream_type bstype); +int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int xilinx_info(xilinx_desc *desc); +int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo); /* Board specific implementation specific function types *********************************************************************/ -typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie ); -typedef int (*Xilinx_init_fn)( int cookie ); -typedef int (*Xilinx_err_fn)( int cookie ); -typedef int (*Xilinx_done_fn)( int cookie ); -typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie ); -typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie ); -typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie ); -typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie ); -typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie ); -typedef int (*Xilinx_busy_fn)( int cookie ); -typedef int (*Xilinx_abort_fn)( int cookie ); -typedef int (*Xilinx_pre_fn)( int cookie ); -typedef int (*Xilinx_post_fn)( int cookie ); -typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie ); +typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie); +typedef int (*xilinx_init_fn)(int cookie); +typedef int (*xilinx_err_fn)(int cookie); +typedef int (*xilinx_done_fn)(int cookie); +typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie); +typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie); +typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie); +typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie); +typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie); +typedef int (*xilinx_busy_fn)(int cookie); +typedef int (*xilinx_abort_fn)(int cookie); +typedef int (*xilinx_pre_fn)(int cookie); +typedef int (*xilinx_post_fn)(int cookie); +typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie); #endif /* _XILINX_H_ */ diff --git a/include/zynqpl.h b/include/zynqpl.h index f8211cdba2..1d37a51a04 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,32 +12,57 @@ #include -extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size); -extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int zynq_info(Xilinx_desc *desc); +#if defined(CONFIG_FPGA_ZYNQPL) +extern struct xilinx_fpga_op zynq_op; +# define FPGA_ZYNQPL_OPS &zynq_op +#else +# define FPGA_ZYNQPL_OPS NULL +#endif #define XILINX_ZYNQ_7010 0x2 +#define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7030 0xc +#define XILINX_ZYNQ_7035 0x12 #define XILINX_ZYNQ_7045 0x11 +#define XILINX_ZYNQ_7100 0x16 /* Device Image Sizes */ #define XILINX_XC7Z010_SIZE 16669920/8 +#define XILINX_XC7Z015_SIZE 28085344/8 #define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z030_SIZE 47839328/8 +#define XILINX_XC7Z035_SIZE 106571232/8 #define XILINX_XC7Z045_SIZE 106571232/8 +#define XILINX_XC7Z100_SIZE 139330784/8 /* Descriptor Macros */ #define XILINX_XC7Z010_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" } +{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z010" } + +#define XILINX_XC7Z015_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z015" } #define XILINX_XC7Z020_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" } +{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z020" } #define XILINX_XC7Z030_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" } +{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z030" } + +#define XILINX_XC7Z035_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z035" } #define XILINX_XC7Z045_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" } +{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z045" } + +#define XILINX_XC7Z100_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z100" } #endif /* _ZYNQPL_H_ */ diff --git a/lib/Kconfig b/lib/Kconfig new file mode 100644 index 0000000000..42cad25842 --- /dev/null +++ b/lib/Kconfig @@ -0,0 +1,35 @@ +menu "Library routines" + +config CC_OPTIMIZE_LIBS_FOR_SPEED + bool "Optimize libraries for speed" + help + Enabling this option will pass "-O2" to gcc when compiling + under "lib" directory. + + If unsure, say N. + +config HAVE_PRIVATE_LIBGCC + bool + +config USE_PRIVATE_LIBGCC + bool "Use private libgcc" + depends on HAVE_PRIVATE_LIBGCC + help + This option allows you to use the built-in libgcc implementation + of U-boot instead of the one privided by the compiler. + If unsure, say N. + +config SYS_HZ + int + default 1000 + help + The frequency of the timer returned by get_timer(). + get_timer() must operate in milliseconds and this option must be + set to 1000. + +config LIB_RAND + bool + +source lib/rsa/Kconfig + +endmenu diff --git a/lib/Makefile b/lib/Makefile index 1e0a5561b5..07d175f45e 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -5,79 +5,67 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +ifndef CONFIG_SPL_BUILD -LIB = $(obj)libgeneric.o +obj-$(CONFIG_RSA) += rsa/ +obj-$(CONFIG_LZMA) += lzma/ +obj-$(CONFIG_LZO) += lzo/ +obj-$(CONFIG_ZLIB) += zlib/ +obj-$(CONFIG_BZIP2) += bzip2/ +obj-$(CONFIG_TIZEN) += tizen/ +obj-$(CONFIG_OF_LIBFDT) += libfdt/ +obj-$(CONFIG_FIT) += libfdt/ -ifndef CONFIG_SPL_BUILD -COBJS-$(CONFIG_AES) += aes.o -COBJS-$(CONFIG_BZIP2) += bzlib.o -COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o -COBJS-$(CONFIG_BZIP2) += bzlib_decompress.o -COBJS-$(CONFIG_BZIP2) += bzlib_randtable.o -COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o -COBJS-$(CONFIG_USB_TTY) += circbuf.o -COBJS-y += crc7.o -COBJS-y += crc16.o -COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o -COBJS-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o -COBJS-$(CONFIG_GZIP) += gunzip.o -COBJS-$(CONFIG_GZIP_COMPRESSED) += gzip.o -COBJS-y += initcall.o -COBJS-$(CONFIG_LMB) += lmb.o -COBJS-y += ldiv.o -COBJS-$(CONFIG_MD5) += md5.o -COBJS-y += net_utils.o -COBJS-$(CONFIG_PHYSMEM) += physmem.o -COBJS-y += qsort.o -COBJS-$(CONFIG_SHA1) += sha1.o -COBJS-$(CONFIG_SHA256) += sha256.o -COBJS-y += strmhz.o -COBJS-$(CONFIG_TPM) += tpm.o -COBJS-$(CONFIG_RBTREE) += rbtree.o -COBJS-$(CONFIG_BITREVERSE) += bitrev.o +obj-$(CONFIG_AES) += aes.o +obj-$(CONFIG_USB_TTY) += circbuf.o +obj-y += crc7.o +obj-y += crc8.o +obj-y += crc16.o +obj-$(CONFIG_FIT) += fdtdec_common.o +obj-$(CONFIG_OF_CONTROL) += fdtdec_common.o +obj-$(CONFIG_OF_CONTROL) += fdtdec.o +obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o +obj-$(CONFIG_GZIP) += gunzip.o +obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o +obj-y += initcall.o +obj-$(CONFIG_LMB) += lmb.o +obj-y += ldiv.o +obj-$(CONFIG_MD5) += md5.o +obj-y += net_utils.o +obj-$(CONFIG_PHYSMEM) += physmem.o +obj-y += qsort.o +obj-$(CONFIG_SHA1) += sha1.o +obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o +obj-$(CONFIG_SHA256) += sha256.o +obj-y += strmhz.o +obj-$(CONFIG_TPM) += tpm.o +obj-$(CONFIG_RBTREE) += rbtree.o +obj-$(CONFIG_BITREVERSE) += bitrev.o +obj-y += list_sort.o endif ifdef CONFIG_SPL_BUILD -COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o -COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o +obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o +obj-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o endif -COBJS-$(CONFIG_ADDR_MAP) += addr_map.o -COBJS-y += hashtable.o -COBJS-y += errno.o -COBJS-y += display_options.o -COBJS-$(CONFIG_BCH) += bch.o -COBJS-y += crc32.o -COBJS-y += ctype.o -COBJS-y += div64.o -COBJS-y += hang.o -COBJS-y += linux_string.o -COBJS-$(CONFIG_REGEX) += slre.o -COBJS-y += string.o -COBJS-y += time.o -COBJS-$(CONFIG_TRACE) += trace.o -COBJS-$(CONFIG_BOOTP_PXE) += uuid.o -COBJS-y += vsprintf.o -COBJS-$(CONFIG_RANDOM_MACADDR) += rand.o -COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o -COBJS-$(CONFIG_BOOTP_RANDOM_ID) += rand.o -COBJS-$(CONFIG_CMD_LINK_LOCAL) += rand.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -# SEE README.arm-unaligned-accesses -$(obj)bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend +obj-$(CONFIG_ADDR_MAP) += addr_map.o +obj-y += hashtable.o +obj-y += errno.o +obj-$(CONFIG_ERRNO_STR) += errno_str.o +obj-y += display_options.o +obj-$(CONFIG_BCH) += bch.o +obj-y += crc32.o +obj-y += ctype.o +obj-y += div64.o +obj-y += hang.o +obj-y += linux_compat.o +obj-y += linux_string.o +obj-$(CONFIG_REGEX) += slre.o +obj-y += string.o +obj-y += time.o +obj-$(CONFIG_TRACE) += trace.o +obj-$(CONFIG_LIB_UUID) += uuid.o +obj-y += vsprintf.o +obj-$(CONFIG_LIB_RAND) += rand.o -######################################################################### +subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2 diff --git a/lib/aes.c b/lib/aes.c index e996b273ac..9d7a0a1c11 100644 --- a/lib/aes.c +++ b/lib/aes.c @@ -22,7 +22,11 @@ * REDISTRIBUTION OF THIS SOFTWARE. */ +#ifndef USE_HOSTCC #include +#else +#include +#endif #include "aes.h" /* forward s-box */ @@ -580,3 +584,74 @@ void aes_decrypt(u8 *in, u8 *expkey, u8 *out) memcpy(out, state, sizeof(state)); } + +static void debug_print_vector(char *name, u32 num_bytes, u8 *data) +{ +#ifdef DEBUG + printf("%s [%d] @0x%08x", name, num_bytes, (u32)data); + print_buffer(0, data, 1, num_bytes, 16); +#endif +} + +void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst) +{ + int i; + + for (i = 0; i < AES_KEY_LENGTH; i++) + *dst++ = *src++ ^ *cbc_chain_data++; +} + +void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + u8 zero_key[AES_KEY_LENGTH] = { 0 }; + u8 tmp_data[AES_KEY_LENGTH]; + /* Convenient array of 0's for IV */ + u8 *cbc_chain_data = zero_key; + u32 i; + + for (i = 0; i < num_aes_blocks; i++) { + debug("encrypt_object: block %d of %d\n", i, num_aes_blocks); + debug_print_vector("AES Src", AES_KEY_LENGTH, src); + + /* Apply the chain data */ + aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data); + debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data); + + /* Encrypt the AES block */ + aes_encrypt(tmp_data, key_exp, dst); + debug_print_vector("AES Dst", AES_KEY_LENGTH, dst); + + /* Update pointers for next loop. */ + cbc_chain_data = dst; + src += AES_KEY_LENGTH; + dst += AES_KEY_LENGTH; + } +} + +void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + u8 tmp_data[AES_KEY_LENGTH], tmp_block[AES_KEY_LENGTH]; + /* Convenient array of 0's for IV */ + u8 cbc_chain_data[AES_KEY_LENGTH] = { 0 }; + u32 i; + + for (i = 0; i < num_aes_blocks; i++) { + debug("encrypt_object: block %d of %d\n", i, num_aes_blocks); + debug_print_vector("AES Src", AES_KEY_LENGTH, src); + + memcpy(tmp_block, src, AES_KEY_LENGTH); + + /* Decrypt the AES block */ + aes_decrypt(src, key_exp, tmp_data); + debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data); + + /* Apply the chain data */ + aes_apply_cbc_chain_data(cbc_chain_data, tmp_data, dst); + debug_print_vector("AES Dst", AES_KEY_LENGTH, dst); + + /* Update pointers for next loop. */ + memcpy(cbc_chain_data, tmp_block, AES_KEY_LENGTH); + src += AES_KEY_LENGTH; + dst += AES_KEY_LENGTH; + } +} diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index 6ea7b03ad4..129bc3e2af 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -28,6 +28,9 @@ int main(void) DEFINE(GD_SIZE, sizeof(struct global_data)); DEFINE(GD_BD, offsetof(struct global_data, bd)); +#ifdef CONFIG_SYS_MALLOC_F_LEN + DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base)); +#endif #if defined(CONFIG_ARM) diff --git a/lib/bzip2/Makefile b/lib/bzip2/Makefile new file mode 100644 index 0000000000..929c24e228 --- /dev/null +++ b/lib/bzip2/Makefile @@ -0,0 +1,2 @@ +obj-y += bzlib.o bzlib_crctable.o bzlib_decompress.o \ + bzlib_randtable.o bzlib_huffman.o diff --git a/lib/bzlib.c b/lib/bzip2/bzlib.c similarity index 100% rename from lib/bzlib.c rename to lib/bzip2/bzlib.c index 5844e187c0..9262e4055e 100644 --- a/lib/bzlib.c +++ b/lib/bzip2/bzlib.c @@ -1350,11 +1350,11 @@ int BZ_API(BZ2_bzBuffToBuffDecompress) strm.avail_out = *destLen; ret = BZ2_bzDecompress ( &strm ); + *destLen -= strm.avail_out; if (ret == BZ_OK) goto output_overflow_or_eof; if (ret != BZ_STREAM_END) goto errhandler; /* normal termination */ - *destLen -= strm.avail_out; BZ2_bzDecompressEnd ( &strm ); return BZ_OK; diff --git a/lib/bzlib_crctable.c b/lib/bzip2/bzlib_crctable.c similarity index 100% rename from lib/bzlib_crctable.c rename to lib/bzip2/bzlib_crctable.c diff --git a/lib/bzlib_decompress.c b/lib/bzip2/bzlib_decompress.c similarity index 100% rename from lib/bzlib_decompress.c rename to lib/bzip2/bzlib_decompress.c diff --git a/lib/bzlib_huffman.c b/lib/bzip2/bzlib_huffman.c similarity index 100% rename from lib/bzlib_huffman.c rename to lib/bzip2/bzlib_huffman.c diff --git a/lib/bzlib_private.h b/lib/bzip2/bzlib_private.h similarity index 100% rename from lib/bzlib_private.h rename to lib/bzip2/bzlib_private.h diff --git a/lib/bzlib_randtable.c b/lib/bzip2/bzlib_randtable.c similarity index 100% rename from lib/bzlib_randtable.c rename to lib/bzip2/bzlib_randtable.c diff --git a/lib/crc8.c b/lib/crc8.c new file mode 100644 index 0000000000..8b68a29e40 --- /dev/null +++ b/lib/crc8.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "linux/crc8.h" + +unsigned int crc8(const unsigned char *vptr, int len) +{ + const unsigned char *data = vptr; + unsigned int crc = 0; + int i, j; + + for (j = len; j; j--, data++) { + crc ^= (*data << 8); + for (i = 8; i; i--) { + if (crc & 0x8000) + crc ^= (0x1070 << 3); + crc <<= 1; + } + } + + return (crc >> 8) & 0xff; +} diff --git a/lib/display_options.c b/lib/display_options.c index 4a972b08a4..d5d17b2818 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -21,15 +22,10 @@ int display_options (void) return 0; } -/* - * print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB", - * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string - * (like "\n") - */ -void print_size(unsigned long long size, const char *s) +void print_size(uint64_t size, const char *s) { unsigned long m = 0, n; - unsigned long long f; + uint64_t f; static const char names[] = {'E', 'P', 'T', 'G', 'M', 'K'}; unsigned long d = 10 * ARRAY_SIZE(names); char c = 0; @@ -43,7 +39,7 @@ void print_size(unsigned long long size, const char *s) } if (!c) { - printf("%llu Bytes%s", size, s); + printf("%" PRIu64 " Bytes%s", size, s); return; } @@ -87,11 +83,19 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, { /* linebuf as a union causes proper alignment */ union linebuf { +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + uint64_t uq[MAX_LINE_LENGTH_BYTES/sizeof(uint64_t) + 1]; +#endif uint32_t ui[MAX_LINE_LENGTH_BYTES/sizeof(uint32_t) + 1]; uint16_t us[MAX_LINE_LENGTH_BYTES/sizeof(uint16_t) + 1]; uint8_t uc[MAX_LINE_LENGTH_BYTES/sizeof(uint8_t) + 1]; } lb; int i; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + uint64_t x; +#else + uint32_t x; +#endif if (linelen*width > MAX_LINE_LENGTH_BYTES) linelen = MAX_LINE_LENGTH_BYTES / width; @@ -108,14 +112,21 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, /* Copy from memory into linebuf and print hex values */ for (i = 0; i < thislinelen; i++) { - uint32_t x; if (width == 4) x = lb.ui[i] = *(volatile uint32_t *)data; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (width == 8) + x = lb.uq[i] = *(volatile uint64_t *)data; +#endif else if (width == 2) x = lb.us[i] = *(volatile uint16_t *)data; else x = lb.uc[i] = *(volatile uint8_t *)data; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + printf(" %0*" PRIx64, width * 2, x); +#else printf(" %0*x", width * 2, x); +#endif data += width; } diff --git a/lib/div64.c b/lib/div64.c index e688a91200..795ef0e1e4 100644 --- a/lib/div64.c +++ b/lib/div64.c @@ -16,6 +16,7 @@ * assembly versions such as arch/powerpc/lib/div64.S and arch/sh/lib/div64.S. */ +#include #include uint32_t __div64_32(uint64_t *n, uint32_t base) diff --git a/lib/errno_str.c b/lib/errno_str.c new file mode 100644 index 0000000000..0ba950e970 --- /dev/null +++ b/lib/errno_str.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak + * + * SDPX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#define ERRNO_MSG(errno, msg) msg +#define SAME_AS(x) (const char *)&errno_message[x] + +static const char * const errno_message[] = { + ERRNO_MSG(0, "Success"), + ERRNO_MSG(EPERM, "Operation not permitted"), + ERRNO_MSG(ENOEN, "No such file or directory"), + ERRNO_MSG(ESRCH, "No such process"), + ERRNO_MSG(EINTR, "Interrupted system call"), + ERRNO_MSG(EIO, "I/O error"), + ERRNO_MSG(ENXIO, "No such device or address"), + ERRNO_MSG(E2BIG, "Argument list too long"), + ERRNO_MSG(ENOEXEC, "Exec format error"), + ERRNO_MSG(EBADF, "Bad file number"), + ERRNO_MSG(ECHILD, "No child processes"), + ERRNO_MSG(EAGAIN, "Try again"), + ERRNO_MSG(ENOMEM, "Out of memory"), + ERRNO_MSG(EACCES, "Permission denied"), + ERRNO_MSG(EFAULT, "Bad address"), + ERRNO_MSG(ENOTBL, "Block device required"), + ERRNO_MSG(EBUSY, "Device or resource busy"), + ERRNO_MSG(EEXIST, "File exists"), + ERRNO_MSG(EXDEV, "Cross-device link"), + ERRNO_MSG(ENODEV, "No such device"), + ERRNO_MSG(ENOTDIR, "Not a directory"), + ERRNO_MSG(EISDIR, "Is a directory"), + ERRNO_MSG(EINVAL, "Invalid argument"), + ERRNO_MSG(ENFILE, "File table overflow"), + ERRNO_MSG(EMFILE, "Too many open files"), + ERRNO_MSG(ENOTTY, "Not a typewriter"), + ERRNO_MSG(ETXTBSY, "Text file busy"), + ERRNO_MSG(EFBIG, "File too large"), + ERRNO_MSG(ENOSPC, "No space left on device"), + ERRNO_MSG(ESPIPE, "Illegal seek"), + ERRNO_MSG(EROFS, "Read-only file system"), + ERRNO_MSG(EMLINK, "Too many links"), + ERRNO_MSG(EPIPE, "Broken pipe"), + ERRNO_MSG(EDOM, "Math argument out of domain of func"), + ERRNO_MSG(ERANGE, "Math result not representable"), + ERRNO_MSG(EDEADLK, "Resource deadlock would occur"), + ERRNO_MSG(ENAMETOOLONG, "File name too long"), + ERRNO_MSG(ENOLCK, "No record locks available"), + ERRNO_MSG(ENOSYS, "Function not implemented"), + ERRNO_MSG(ENOTEMPTY, "Directory not empty"), + ERRNO_MSG(ELOOP, "Too many symbolic links encountered"), + ERRNO_MSG(EWOULDBLOCK, SAME_AS(EAGAIN)), + ERRNO_MSG(ENOMSG, "No message of desired type"), + ERRNO_MSG(EIDRM, "Identifier removed"), + ERRNO_MSG(ECHRNG, "Channel number out of range"), + ERRNO_MSG(EL2NSYNC, "Level 2 not synchronized"), + ERRNO_MSG(EL3HLT, "Level 3 halted"), + ERRNO_MSG(EL3RST, "Level 3 reset"), + ERRNO_MSG(ELNRNG, "Link number out of range"), + ERRNO_MSG(EUNATCH, "Protocol driver not attached"), + ERRNO_MSG(ENOCSI, "No CSI structure available"), + ERRNO_MSG(EL2HLT, "Level 2 halted"), + ERRNO_MSG(EBADE, "Invalid exchange"), + ERRNO_MSG(EBADR, "Invalid request descriptor"), + ERRNO_MSG(EXFULL, "Exchange full"), + ERRNO_MSG(ENOANO, "No anode"), + ERRNO_MSG(EBADRQC, "Invalid request code"), + ERRNO_MSG(EBADSLT, "Invalid slot"), + ERRNO_MSG(EDEADLOCK, SAME_AS(EDEADLK)), + ERRNO_MSG(EBFONT, "Bad font file format"), + ERRNO_MSG(ENOSTR, "Device not a stream"), + ERRNO_MSG(ENODATA, "No data available"), + ERRNO_MSG(ETIME, "Timer expired"), + ERRNO_MSG(ENOSR, "Out of streams resources"), + ERRNO_MSG(ENONET, "Machine is not on the network"), + ERRNO_MSG(ENOPKG, "Package not installed"), + ERRNO_MSG(EREMOTE, "Object is remote"), + ERRNO_MSG(ENOLINK, "Link has been severed"), + ERRNO_MSG(EADV, "Advertise error"), + ERRNO_MSG(ESRMNT, "Srmount error"), + ERRNO_MSG(ECOMM, "Communication error on send"), + ERRNO_MSG(EPROTO, "Protocol error"), + ERRNO_MSG(EMULTIHOP, "Multihop attempted"), + ERRNO_MSG(EDOTDOT, "RFS specific error"), + ERRNO_MSG(EBADMSG, "Not a data message"), + ERRNO_MSG(EOVERFLOW, "Value too large for defined data type"), + ERRNO_MSG(ENOTUNIQ, "Name not unique on network"), + ERRNO_MSG(EBADFD, "File descriptor in bad state"), + ERRNO_MSG(EREMCHG, "Remote address changed"), + ERRNO_MSG(ELIBACC, "Can not access a needed shared library"), + ERRNO_MSG(ELIBBAD, "Accessing a corrupted shared library"), + ERRNO_MSG(ELIBSCN, ".lib section in a.out corrupted"), + ERRNO_MSG(ELIBMAX, "Attempting to link in too many shared libraries"), + ERRNO_MSG(ELIBEXEC, "Cannot exec a shared library directly"), + ERRNO_MSG(EILSEQ, "Illegal byte sequence"), + ERRNO_MSG(ERESTART, "Interrupted system call should be restarted"), + ERRNO_MSG(ESTRPIPE, "Streams pipe error"), + ERRNO_MSG(EUSERS, "Too many users"), + ERRNO_MSG(ENOTSOCK, "Socket operation on non-socket"), + ERRNO_MSG(EDESTADDRREQ, "Destination address required"), + ERRNO_MSG(EMSGSIZE, "Message too long"), + ERRNO_MSG(EPROTOTYPE, "Protocol wrong type for socket"), + ERRNO_MSG(ENOPROTOOPT, "Protocol not available"), + ERRNO_MSG(EPROTONOSUPPORT, "Protocol not supported"), + ERRNO_MSG(ESOCKTNOSUPPORT, "Socket type not supported"), + ERRNO_MSG(EOPNOTSUPP, "Operation not supported on transport endpoint"), + ERRNO_MSG(EPFNOSUPPORT, "Protocol family not supported"), + ERRNO_MSG(AFNOSUPPORT, "Address family not supported by protocol"), + ERRNO_MSG(EADDRINUSE, "Address already in use"), + ERRNO_MSG(EADDRNOTAVAIL, "Cannot assign requested address"), + ERRNO_MSG(ENETDOWN, "Network is down"), + ERRNO_MSG(ENETUNREACH, "Network is unreachable"), + ERRNO_MSG(ENETRESET, "Network dropped connection because of reset"), + ERRNO_MSG(ECONNABORTED, "Software caused connection abort"), + ERRNO_MSG(ECONNRESET, "Connection reset by peer"), + ERRNO_MSG(ENOBUFS, "No buffer space available"), + ERRNO_MSG(EISCONN, "Transport endpoint is already connected"), + ERRNO_MSG(ENOTCONN, "Transport endpoint is not connected"), + ERRNO_MSG(ESHUTDOWN, "Cannot send after transport endpoint shutdown"), + ERRNO_MSG(ETOOMANYREFS, "Too many references: cannot splice"), + ERRNO_MSG(ETIMEDOUT, "Connection timed out"), + ERRNO_MSG(ECONNREFUSED, "Connection refused"), + ERRNO_MSG(EHOSTDOWN, "Host is down"), + ERRNO_MSG(EHOSTUNREACH, "No route to host"), + ERRNO_MSG(EALREADY, "Operation already in progress"), + ERRNO_MSG(EINPROGRESS, "Operation now in progress"), + ERRNO_MSG(ESTALE, "Stale NFS file handle"), + ERRNO_MSG(EUCLEAN, "Structure needs cleaning"), + ERRNO_MSG(ENOTNAM, "Not a XENIX named type file"), + ERRNO_MSG(ENAVAIL, "No XENIX semaphores available"), + ERRNO_MSG(EISNAM, "Is a named type file"), + ERRNO_MSG(EREMOTEIO, "Remote I/O error"), + ERRNO_MSG(EDQUOT, "Quota exceeded"), + ERRNO_MSG(ENOMEDIUM, "No medium found"), + ERRNO_MSG(EMEDIUMTYPE, "Wrong medium type"), +}; + +const char *errno_str(int errno) +{ + if (errno >= 0) + return errno_message[0]; + + return errno_message[abs(errno)]; +} diff --git a/lib/fdtdec.c b/lib/fdtdec.c index dc358562d1..5bf8f29b13 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -3,12 +3,13 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef USE_HOSTCC #include +#include #include #include #include - -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -23,34 +24,36 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), COMPAT(NVIDIA_TEGRA30_USB, "nvidia,tegra30-ehci"), COMPAT(NVIDIA_TEGRA114_USB, "nvidia,tegra114-ehci"), - COMPAT(NVIDIA_TEGRA114_I2C, "nvidia,tegra114-i2c"), - COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"), - COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"), COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"), COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"), COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"), COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), + COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), - COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"), - COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"), - COMPAT(NVIDIA_TEGRA114_SPI, "nvidia,tegra114-spi"), + COMPAT(NVIDIA_TEGRA124_PCIE, "nvidia,tegra124-pcie"), + COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"), + COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"), + COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"), COMPAT(SMSC_LAN9215, "smsc,lan9215"), COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"), COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"), COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"), COMPAT(WOLFSON_WM8994_CODEC, "wolfson,wm8994-codec"), - COMPAT(SAMSUNG_EXYNOS_SPI, "samsung,exynos-spi"), COMPAT(GOOGLE_CROS_EC, "google,cros-ec"), COMPAT(GOOGLE_CROS_EC_KEYB, "google,cros-ec-keyb"), COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"), + COMPAT(SAMSUNG_EXYNOS5_XHCI, "samsung,exynos5250-xhci"), COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"), + COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"), COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"), COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"), + COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"), COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"), - COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"), + COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"), + COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"), COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"), COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"), COMPAT(GENERIC_SPI_FLASH, "spi-flash"), @@ -58,6 +61,20 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INFINEON_SLB9635_TPM, "infineon,slb9635-tpm"), COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645-tpm"), COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"), + COMPAT(SANDBOX_HOST_EMULATION, "sandbox,host-emulation"), + COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"), + COMPAT(TI_TPS65090, "ti,tps65090"), + COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), + COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), + COMPAT(PARADE_PS8625, "parade,ps8625"), + COMPAT(COMPAT_INTEL_LPC, "intel,lpc"), + COMPAT(INTEL_MICROCODE, "intel,microcode"), + COMPAT(MEMORY_SPD, "memory-spd"), + COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"), + COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"), + COMPAT(INTEL_GMA, "intel,gma"), + COMPAT(AMS_AS3722, "ams,as3722"), + COMPAT(INTEL_ICH_SPI, "intel,ich-spi"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) @@ -84,10 +101,10 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, size = (fdt_size_t *)((char *)cell + sizeof(fdt_addr_t)); *sizep = fdt_size_to_cpu(*size); - debug("addr=%p, size=%p\n", (void *)addr, - (void *)*sizep); + debug("addr=%08lx, size=%08x\n", + (ulong)addr, *sizep); } else { - debug("%p\n", (void *)addr); + debug("%08lx\n", (ulong)addr); } return addr; } @@ -101,23 +118,162 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node, return fdtdec_get_addr_size(blob, node, prop_name, NULL); } -s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, - s32 default_val) +#ifdef CONFIG_PCI +int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type, + const char *prop_name, struct fdt_pci_addr *addr) { - const s32 *cell; + const u32 *cell; int len; + int ret = -ENOENT; debug("%s: %s: ", __func__, prop_name); + + /* + * If we follow the pci bus bindings strictly, we should check + * the value of the node's parent node's #address-cells and + * #size-cells. They need to be 3 and 2 accordingly. However, + * for simplicity we skip the check here. + */ cell = fdt_getprop(blob, node, prop_name, &len); - if (cell && len >= sizeof(s32)) { - s32 val = fdt32_to_cpu(cell[0]); + if (!cell) + goto fail; + + if ((len % FDT_PCI_REG_SIZE) == 0) { + int num = len / FDT_PCI_REG_SIZE; + int i; + + for (i = 0; i < num; i++) { + debug("pci address #%d: %08lx %08lx %08lx\n", i, + (ulong)fdt_addr_to_cpu(cell[0]), + (ulong)fdt_addr_to_cpu(cell[1]), + (ulong)fdt_addr_to_cpu(cell[2])); + if ((fdt_addr_to_cpu(*cell) & type) == type) { + addr->phys_hi = fdt_addr_to_cpu(cell[0]); + addr->phys_mid = fdt_addr_to_cpu(cell[1]); + addr->phys_lo = fdt_addr_to_cpu(cell[2]); + break; + } else { + cell += (FDT_PCI_ADDR_CELLS + + FDT_PCI_SIZE_CELLS); + } + } + + if (i == num) + goto fail; - debug("%#x (%d)\n", val, val); - return val; + return 0; + } else { + ret = -EINVAL; } + +fail: debug("(not found)\n"); - return default_val; + return ret; +} + +int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device) +{ + const char *list, *end; + int len; + + list = fdt_getprop(blob, node, "compatible", &len); + if (!list) + return -ENOENT; + + end = list + len; + while (list < end) { + char *s; + + len = strlen(list); + if (len >= strlen("pciVVVV,DDDD")) { + s = strstr(list, "pci"); + + /* + * check if the string is something like pciVVVV,DDDD.RR + * or just pciVVVV,DDDD + */ + if (s && s[7] == ',' && + (s[12] == '.' || s[12] == 0)) { + s += 3; + *vendor = simple_strtol(s, NULL, 16); + + s += 5; + *device = simple_strtol(s, NULL, 16); + + return 0; + } + } else { + list += (len + 1); + } + } + + return -ENOENT; +} + +int fdtdec_get_pci_bdf(const void *blob, int node, + struct fdt_pci_addr *addr, pci_dev_t *bdf) +{ + u16 dt_vendor, dt_device, vendor, device; + int ret; + + /* get vendor id & device id from the compatible string */ + ret = fdtdec_get_pci_vendev(blob, node, &dt_vendor, &dt_device); + if (ret) + return ret; + + /* extract the bdf from fdt_pci_addr */ + *bdf = addr->phys_hi & 0xffff00; + + /* read vendor id & device id based on bdf */ + pci_read_config_word(*bdf, PCI_VENDOR_ID, &vendor); + pci_read_config_word(*bdf, PCI_DEVICE_ID, &device); + + /* + * Note there are two places in the device tree to fully describe + * a pci device: one is via compatible string with a format of + * "pciVVVV,DDDD" and the other one is the bdf numbers encoded in + * the device node's reg address property. We read the vendor id + * and device id based on bdf and compare the values with the + * "VVVV,DDDD". If they are the same, then we are good to use bdf + * to read device's bar. But if they are different, we have to rely + * on the vendor id and device id extracted from the compatible + * string and locate the real bdf by pci_find_device(). This is + * because normally we may only know device's device number and + * function number when writing device tree. The bus number is + * dynamically assigned during the pci enumeration process. + */ + if ((dt_vendor != vendor) || (dt_device != device)) { + *bdf = pci_find_device(dt_vendor, dt_device, 0); + if (*bdf == -1) + return -ENODEV; + } + + return 0; +} + +int fdtdec_get_pci_bar32(const void *blob, int node, + struct fdt_pci_addr *addr, u32 *bar) +{ + pci_dev_t bdf; + int barnum; + int ret; + + /* get pci devices's bdf */ + ret = fdtdec_get_pci_bdf(blob, node, addr, &bdf); + if (ret) + return ret; + + /* extract the bar number from fdt_pci_addr */ + barnum = addr->phys_hi & 0xff; + if ((barnum < PCI_BASE_ADDRESS_0) || (barnum > PCI_CARDBUS_CIS)) + return -EINVAL; + + barnum = (barnum - PCI_BASE_ADDRESS_0) / 4; + *bar = pci_read_bar32(pci_bus_to_hose(PCI_BUS(bdf)), bdf, barnum); + + return 0; } +#endif uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name, uint64_t default_val) @@ -327,6 +483,65 @@ int fdtdec_add_aliases_for_id(const void *blob, const char *name, return num_found; } +int fdtdec_get_alias_seq(const void *blob, const char *base, int offset, + int *seqp) +{ + int base_len = strlen(base); + const char *find_name; + int find_namelen; + int prop_offset; + int aliases; + + find_name = fdt_get_name(blob, offset, &find_namelen); + debug("Looking for '%s' at %d, name %s\n", base, offset, find_name); + + aliases = fdt_path_offset(blob, "/aliases"); + for (prop_offset = fdt_first_property_offset(blob, aliases); + prop_offset > 0; + prop_offset = fdt_next_property_offset(blob, prop_offset)) { + const char *prop; + const char *name; + const char *slash; + const char *p; + int len; + + prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len); + debug(" - %s, %s\n", name, prop); + if (len < find_namelen || *prop != '/' || prop[len - 1] || + strncmp(name, base, base_len)) + continue; + + slash = strrchr(prop, '/'); + if (strcmp(slash + 1, find_name)) + continue; + for (p = name + strlen(name) - 1; p > name; p--) { + if (!isdigit(*p)) { + *seqp = simple_strtoul(p + 1, NULL, 10); + debug("Found seq %d\n", *seqp); + return 0; + } + } + } + + debug("Not found\n"); + return -ENOENT; +} + +int fdtdec_get_chosen_node(const void *blob, const char *name) +{ + const char *prop; + int chosen_node; + int len; + + if (!blob) + return -FDT_ERR_NOTFOUND; + chosen_node = fdt_path_offset(blob, "/chosen"); + prop = fdt_getprop(blob, chosen_node, name, &len); + if (!prop) + return -FDT_ERR_NOTFOUND; + return fdt_path_offset(blob, prop); +} + int fdtdec_check_fdt(void) { /* @@ -414,6 +629,26 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, return err; } +int fdtdec_get_int_array_count(const void *blob, int node, + const char *prop_name, u32 *array, int count) +{ + const u32 *cell; + int len, elems; + int i; + + debug("%s: %s\n", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (!cell) + return -FDT_ERR_NOTFOUND; + elems = len / sizeof(u32); + if (count > elems) + count = elems; + for (i = 0; i < count; i++) + array[i] = fdt32_to_cpu(cell[i]); + + return count; +} + const u32 *fdtdec_locate_array(const void *blob, int node, const char *prop_name, int count) { @@ -435,99 +670,128 @@ int fdtdec_get_bool(const void *blob, int node, const char *prop_name) return cell != NULL; } -/** - * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no - * terminating item. - * - * @param blob FDT blob to use - * @param node Node to look at - * @param prop_name Node property name - * @param gpio Array of gpio elements to fill from FDT. This will be - * untouched if either 0 or an error is returned - * @param max_count Maximum number of elements allowed - * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would - * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing. - */ -int fdtdec_decode_gpios(const void *blob, int node, const char *prop_name, - struct fdt_gpio_state *gpio, int max_count) +int fdtdec_parse_phandle_with_args(const void *blob, int src_node, + const char *list_name, + const char *cells_name, + int cell_count, int index, + struct fdtdec_phandle_args *out_args) { - const struct fdt_property *prop; - const u32 *cell; - const char *name; - int len, i; - - debug("%s: %s\n", __func__, prop_name); - assert(max_count > 0); - prop = fdt_get_property(blob, node, prop_name, &len); - if (!prop) { - debug("%s: property '%s' missing\n", __func__, prop_name); - return -FDT_ERR_NOTFOUND; - } + const __be32 *list, *list_end; + int rc = 0, size, cur_index = 0; + uint32_t count = 0; + int node = -1; + int phandle; + + /* Retrieve the phandle list property */ + list = fdt_getprop(blob, src_node, list_name, &size); + if (!list) + return -ENOENT; + list_end = list + size / sizeof(*list); + + /* Loop over the phandles until all the requested entry is found */ + while (list < list_end) { + rc = -EINVAL; + count = 0; - /* We will use the name to tag the GPIO */ - name = fdt_string(blob, fdt32_to_cpu(prop->nameoff)); - cell = (u32 *)prop->data; - len /= sizeof(u32) * 3; /* 3 cells per GPIO record */ - if (len > max_count) { - debug(" %s: too many GPIOs / cells for " - "property '%s'\n", __func__, prop_name); - return -FDT_ERR_BADLAYOUT; - } - - /* Read out the GPIO data from the cells */ - for (i = 0; i < len; i++, cell += 3) { - gpio[i].gpio = fdt32_to_cpu(cell[1]); - gpio[i].flags = fdt32_to_cpu(cell[2]); - gpio[i].name = name; - } - - return len; -} - -int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, - struct fdt_gpio_state *gpio) -{ - int err; - - debug("%s: %s\n", __func__, prop_name); - gpio->gpio = FDT_GPIO_NONE; - gpio->name = NULL; - err = fdtdec_decode_gpios(blob, node, prop_name, gpio, 1); - return err == 1 ? 0 : err; -} + /* + * If phandle is 0, then it is an empty entry with no + * arguments. Skip forward to the next entry. + */ + phandle = be32_to_cpup(list++); + if (phandle) { + /* + * Find the provider node and parse the #*-cells + * property to determine the argument length. + * + * This is not needed if the cell count is hard-coded + * (i.e. cells_name not set, but cell_count is set), + * except when we're going to return the found node + * below. + */ + if (cells_name || cur_index == index) { + node = fdt_node_offset_by_phandle(blob, + phandle); + if (!node) { + debug("%s: could not find phandle\n", + fdt_get_name(blob, src_node, + NULL)); + goto err; + } + } -int fdtdec_get_gpio(struct fdt_gpio_state *gpio) -{ - int val; + if (cells_name) { + count = fdtdec_get_int(blob, node, cells_name, + -1); + if (count == -1) { + debug("%s: could not get %s for %s\n", + fdt_get_name(blob, src_node, + NULL), + cells_name, + fdt_get_name(blob, node, + NULL)); + goto err; + } + } else { + count = cell_count; + } - if (!fdt_gpio_isvalid(gpio)) - return -1; + /* + * Make sure that the arguments actually fit in the + * remaining property data length + */ + if (list + count > list_end) { + debug("%s: arguments longer than property\n", + fdt_get_name(blob, src_node, NULL)); + goto err; + } + } - val = gpio_get_value(gpio->gpio); - return gpio->flags & FDT_GPIO_ACTIVE_LOW ? val ^ 1 : val; -} + /* + * All of the error cases above bail out of the loop, so at + * this point, the parsing is successful. If the requested + * index matches, then fill the out_args structure and return, + * or return -ENOENT for an empty entry. + */ + rc = -ENOENT; + if (cur_index == index) { + if (!phandle) + goto err; + + if (out_args) { + int i; + + if (count > MAX_PHANDLE_ARGS) { + debug("%s: too many arguments %d\n", + fdt_get_name(blob, src_node, + NULL), count); + count = MAX_PHANDLE_ARGS; + } + out_args->node = node; + out_args->args_count = count; + for (i = 0; i < count; i++) { + out_args->args[i] = + be32_to_cpup(list++); + } + } -int fdtdec_set_gpio(struct fdt_gpio_state *gpio, int val) -{ - if (!fdt_gpio_isvalid(gpio)) - return -1; + /* Found it! return success */ + return 0; + } - val = gpio->flags & FDT_GPIO_ACTIVE_LOW ? val ^ 1 : val; - return gpio_set_value(gpio->gpio, val); -} + node = -1; + list += count; + cur_index++; + } -int fdtdec_setup_gpio(struct fdt_gpio_state *gpio) -{ /* - * Return success if there is no GPIO defined. This is used for - * optional GPIOs) + * Result will be one of: + * -ENOENT : index is for empty phandle + * -EINVAL : parsing error on data + * [1..n] : Number of phandle (count mode; when index = -1) */ - if (!fdt_gpio_isvalid(gpio)) - return 0; - - if (gpio_request(gpio->gpio, gpio->name)) - return -1; - return 0; + rc = index < 0 ? cur_index : -ENOENT; + err: + return rc; } int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name, @@ -598,19 +862,175 @@ char *fdtdec_get_config_string(const void *blob, const char *prop_name) return (char *)nodep; } -int fdtdec_decode_region(const void *blob, int node, - const char *prop_name, void **ptrp, size_t *size) +int fdtdec_decode_region(const void *blob, int node, const char *prop_name, + fdt_addr_t *basep, fdt_size_t *sizep) { const fdt_addr_t *cell; int len; - debug("%s: %s\n", __func__, prop_name); + debug("%s: %s: %s\n", __func__, fdt_get_name(blob, node, NULL), + prop_name); cell = fdt_getprop(blob, node, prop_name, &len); - if (!cell || (len != sizeof(fdt_addr_t) * 2)) + if (!cell || (len < sizeof(fdt_addr_t) * 2)) { + debug("cell=%p, len=%d\n", cell, len); return -1; + } + + *basep = fdt_addr_to_cpu(*cell); + *sizep = fdt_size_to_cpu(cell[1]); + debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep, + (ulong)*sizep); + + return 0; +} + +/** + * Read a flash entry from the fdt + * + * @param blob FDT blob + * @param node Offset of node to read + * @param name Name of node being read + * @param entry Place to put offset and size of this node + * @return 0 if ok, -ve on error + */ +int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, + struct fmap_entry *entry) +{ + const char *prop; + u32 reg[2]; + + if (fdtdec_get_int_array(blob, node, "reg", reg, 2)) { + debug("Node '%s' has bad/missing 'reg' property\n", name); + return -FDT_ERR_NOTFOUND; + } + entry->offset = reg[0]; + entry->length = reg[1]; + entry->used = fdtdec_get_int(blob, node, "used", entry->length); + prop = fdt_getprop(blob, node, "compress", NULL); + entry->compress_algo = prop && !strcmp(prop, "lzo") ? + FMAP_COMPRESS_LZO : FMAP_COMPRESS_NONE; + prop = fdt_getprop(blob, node, "hash", &entry->hash_size); + entry->hash_algo = prop ? FMAP_HASH_SHA256 : FMAP_HASH_NONE; + entry->hash = (uint8_t *)prop; + + return 0; +} + +static u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells) +{ + u64 number = 0; + + while (cells--) + number = (number << 32) | fdt32_to_cpu(*ptr++); + + return number; +} + +int fdt_get_resource(const void *fdt, int node, const char *property, + unsigned int index, struct fdt_resource *res) +{ + const fdt32_t *ptr, *end; + int na, ns, len, parent; + unsigned int i = 0; + + parent = fdt_parent_offset(fdt, node); + if (parent < 0) + return parent; + + na = fdt_address_cells(fdt, parent); + ns = fdt_size_cells(fdt, parent); + + ptr = fdt_getprop(fdt, node, property, &len); + if (!ptr) + return len; + + end = ptr + len / sizeof(*ptr); + + while (ptr + na + ns <= end) { + if (i == index) { + res->start = res->end = fdtdec_get_number(ptr, na); + res->end += fdtdec_get_number(&ptr[na], ns) - 1; + return 0; + } + + ptr += na + ns; + i++; + } + + return -FDT_ERR_NOTFOUND; +} + +int fdt_get_named_resource(const void *fdt, int node, const char *property, + const char *prop_names, const char *name, + struct fdt_resource *res) +{ + int index; + + index = fdt_find_string(fdt, node, prop_names, name); + if (index < 0) + return index; + + return fdt_get_resource(fdt, node, property, index, res); +} + +int fdtdec_decode_memory_region(const void *blob, int config_node, + const char *mem_type, const char *suffix, + fdt_addr_t *basep, fdt_size_t *sizep) +{ + char prop_name[50]; + const char *mem; + fdt_size_t size, offset_size; + fdt_addr_t base, offset; + int node; + + if (config_node == -1) { + config_node = fdt_path_offset(blob, "/config"); + if (config_node < 0) { + debug("%s: Cannot find /config node\n", __func__); + return -ENOENT; + } + } + if (!suffix) + suffix = ""; + + snprintf(prop_name, sizeof(prop_name), "%s-memory%s", mem_type, + suffix); + mem = fdt_getprop(blob, config_node, prop_name, NULL); + if (!mem) { + debug("%s: No memory type for '%s', using /memory\n", __func__, + prop_name); + mem = "/memory"; + } + + node = fdt_path_offset(blob, mem); + if (node < 0) { + debug("%s: Failed to find node '%s': %s\n", __func__, mem, + fdt_strerror(node)); + return -ENOENT; + } + + /* + * Not strictly correct - the memory may have multiple banks. We just + * use the first + */ + if (fdtdec_decode_region(blob, node, "reg", &base, &size)) { + debug("%s: Failed to decode memory region %s\n", __func__, + mem); + return -EINVAL; + } + + snprintf(prop_name, sizeof(prop_name), "%s-offset%s", mem_type, + suffix); + if (fdtdec_decode_region(blob, config_node, prop_name, &offset, + &offset_size)) { + debug("%s: Failed to decode memory region '%s'\n", __func__, + prop_name); + return -EINVAL; + } + + *basep = base + offset; + *sizep = offset_size; - *ptrp = (void *)fdt_addr_to_cpu(*cell); - *size = fdt_size_to_cpu(cell[1]); - debug("%s: size=%zx\n", __func__, *size); return 0; } +#endif diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c new file mode 100644 index 0000000000..757931a9cb --- /dev/null +++ b/lib/fdtdec_common.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on lib/fdtdec.c: + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef USE_HOSTCC +#include +#include +#include +#else +#include "libfdt.h" +#include "fdt_support.h" + +#define debug(...) +#endif + +int fdtdec_get_int(const void *blob, int node, const char *prop_name, + int default_val) +{ + const int *cell; + int len; + + debug("%s: %s: ", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (cell && len >= sizeof(int)) { + int val = fdt32_to_cpu(cell[0]); + + debug("%#x (%d)\n", val, val); + return val; + } + debug("(not found)\n"); + return default_val; +} diff --git a/lib/gunzip.c b/lib/gunzip.c index 9959781b00..f469fcbead 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -73,6 +73,7 @@ int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, int stoponerr, int offset) { z_stream s; + int err = 0; int r; s.zalloc = gzalloc; @@ -89,16 +90,16 @@ int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, s.avail_out = dstlen; do { r = inflate(&s, Z_FINISH); - if (r != Z_STREAM_END && r != Z_BUF_ERROR && stoponerr == 1) { + if (stoponerr == 1 && r != Z_STREAM_END && + (s.avail_out == 0 || r != Z_BUF_ERROR)) { printf("Error: inflate() returned %d\n", r); - inflateEnd(&s); - return -1; + err = -1; + break; } s.avail_in = *lenp - offset - (int)(s.next_out - (unsigned char*)dst); - s.avail_out = dstlen; } while (r == Z_BUF_ERROR); *lenp = s.next_out - (unsigned char *) dst; inflateEnd(&s); - return 0; + return err; } diff --git a/lib/hashtable.c b/lib/hashtable.c index 644330a17e..18ed5901ec 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -564,7 +564,7 @@ static int match_entry(ENTRY *ep, int flag, int arg; void *priv = NULL; - for (arg = 1; arg < argc; ++arg) { + for (arg = 0; arg < argc; ++arg) { #ifdef CONFIG_REGEX struct slre slre; @@ -776,7 +776,7 @@ static int drop_var_from_set(const char *name, int nvars, char * vars[]) int himport_r(struct hsearch_data *htab, const char *env, size_t size, const char sep, int flag, - int nvars, char * const vars[]) + int crlf_is_lf, int nvars, char * const vars[]) { char *data, *sp, *dp, *name, *value; char *localvars[nvars]; @@ -817,7 +817,7 @@ int himport_r(struct hsearch_data *htab, * size of 8 per entry (= safety factor of ~5) should provide enough * safety margin for any existing environment definitions and still * allow for more than enough dynamic additions. Note that the - * "size" argument is supposed to give the maximum enviroment size + * "size" argument is supposed to give the maximum environment size * (CONFIG_ENV_SIZE). This heuristics will result in * unreasonably large numbers (and thus memory footprint) for * big flash environments (>8,000 entries for 64 KB @@ -841,6 +841,21 @@ int himport_r(struct hsearch_data *htab, } } + if(!size) + return 1; /* everything OK */ + if(crlf_is_lf) { + /* Remove Carriage Returns in front of Line Feeds */ + unsigned ignored_crs = 0; + for(;dp < data + size && *dp; ++dp) { + if(*dp == '\r' && + dp < data + size - 1 && *(dp+1) == '\n') + ++ignored_crs; + else + *(dp-ignored_crs) = *dp; + } + size -= ignored_crs; + dp = data; + } /* Parse environment; allow for '\0' and 'sep' as separators */ do { ENTRY e, *rv; diff --git a/lib/initcall.c b/lib/initcall.c index fa76dd73c1..714274415c 100644 --- a/lib/initcall.c +++ b/lib/initcall.c @@ -7,15 +7,28 @@ #include #include -int initcall_run_list(init_fnc_t init_sequence[]) +DECLARE_GLOBAL_DATA_PTR; + +int initcall_run_list(const init_fnc_t init_sequence[]) { - init_fnc_t *init_fnc_ptr; + const init_fnc_t *init_fnc_ptr; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - debug("initcall: %p\n", *init_fnc_ptr); - if ((*init_fnc_ptr)()) { - debug("initcall sequence %p failed at call %p\n", - init_sequence, *init_fnc_ptr); + unsigned long reloc_ofs = 0; + int ret; + + if (gd->flags & GD_FLG_RELOC) + reloc_ofs = gd->reloc_off; + debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs); + if (gd->flags & GD_FLG_RELOC) + debug(" (relocated to %p)\n", (char *)*init_fnc_ptr); + else + debug("\n"); + ret = (*init_fnc_ptr)(); + if (ret) { + printf("initcall sequence %p failed at call %p (err=%d)\n", + init_sequence, + (char *)*init_fnc_ptr - reloc_ofs, ret); return -1; } } diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile index 07373df99a..2f5413f90d 100644 --- a/lib/libfdt/Makefile +++ b/lib/libfdt/Makefile @@ -5,30 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libfdt.o - -SOBJS = - -COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o fdt_empty_tree.o - -COBJS-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt) -COBJS-$(CONFIG_FIT) += $(COBJS-libfdt) - - -COBJS := $(sort $(COBJS-y)) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \ + fdt_empty_tree.o fdt_addresses.o diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c index 154e9a4461..e146aba6eb 100644 --- a/lib/libfdt/fdt.c +++ b/lib/libfdt/fdt.c @@ -1,52 +1,7 @@ /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #include "libfdt_env.h" diff --git a/lib/libfdt/fdt_addresses.c b/lib/libfdt/fdt_addresses.c new file mode 100644 index 0000000000..76054d98e5 --- /dev/null +++ b/lib/libfdt/fdt_addresses.c @@ -0,0 +1,55 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2014 David Gibson + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + */ +#include "libfdt_env.h" + +#ifndef USE_HOSTCC +#include +#include +#else +#include "fdt_host.h" +#endif + +#include "libfdt_internal.h" + +int fdt_address_cells(const void *fdt, int nodeoffset) +{ + const fdt32_t *ac; + int val; + int len; + + ac = fdt_getprop(fdt, nodeoffset, "#address-cells", &len); + if (!ac) + return 2; + + if (len != sizeof(*ac)) + return -FDT_ERR_BADNCELLS; + + val = fdt32_to_cpu(*ac); + if ((val <= 0) || (val > FDT_MAX_NCELLS)) + return -FDT_ERR_BADNCELLS; + + return val; +} + +int fdt_size_cells(const void *fdt, int nodeoffset) +{ + const fdt32_t *sc; + int val; + int len; + + sc = fdt_getprop(fdt, nodeoffset, "#size-cells", &len); + if (!sc) + return 2; + + if (len != sizeof(*sc)) + return -FDT_ERR_BADNCELLS; + + val = fdt32_to_cpu(*sc); + if ((val < 0) || (val > FDT_MAX_NCELLS)) + return -FDT_ERR_BADNCELLS; + + return val; +} diff --git a/lib/libfdt/fdt_empty_tree.c b/lib/libfdt/fdt_empty_tree.c index f72d13b1d1..34f1c84431 100644 --- a/lib/libfdt/fdt_empty_tree.c +++ b/lib/libfdt/fdt_empty_tree.c @@ -1,52 +1,7 @@ /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2012 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #include "libfdt_env.h" @@ -81,4 +36,3 @@ int fdt_create_empty_tree(void *buf, int bufsize) return fdt_open_into(buf, buf, bufsize); } - diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index b65f4e23ad..03733e574f 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -1,52 +1,7 @@ /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #include "libfdt_env.h" @@ -89,7 +44,7 @@ static int _fdt_string_eq(const void *fdt, int stroffset, { const char *p = fdt_string(fdt, stroffset); - return (strlen(p) == len) && (memcmp(p, s, len) == 0); + return (strnlen(p, len + 1) == len) && (memcmp(p, s, len) == 0); } int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) @@ -536,6 +491,82 @@ int fdt_stringlist_contains(const char *strlist, int listlen, const char *str) return 0; } +int fdt_count_strings(const void *fdt, int node, const char *property) +{ + int length, i, count = 0; + const char *list; + + list = fdt_getprop(fdt, node, property, &length); + if (!list) + return -length; + + for (i = 0; i < length; i++) { + int len = strlen(list); + + list += len + 1; + i += len; + count++; + } + + return count; +} + +int fdt_find_string(const void *fdt, int node, const char *property, + const char *string) +{ + const char *list, *end; + int len, index = 0; + + list = fdt_getprop(fdt, node, property, &len); + if (!list) + return len; + + end = list + len; + len = strlen(string); + + while (list < end) { + int l = strlen(list); + + if (l == len && memcmp(list, string, len) == 0) + return index; + + list += l + 1; + index++; + } + + return -FDT_ERR_NOTFOUND; +} + +int fdt_get_string_index(const void *fdt, int node, const char *property, + int index, const char **output) +{ + const char *list; + int length, i; + + list = fdt_getprop(fdt, node, property, &length); + + for (i = 0; i < length; i++) { + int len = strlen(list); + + if (index == 0) { + *output = list; + return 0; + } + + list += len + 1; + i += len; + index--; + } + + return FDT_ERR_NOTFOUND; +} + +int fdt_get_string(const void *fdt, int node, const char *property, + const char **output) +{ + return fdt_get_string_index(fdt, node, property, 0, output); +} + int fdt_node_check_compatible(const void *fdt, int nodeoffset, const char *compatible) { diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c index aba6094841..bec8b8ad89 100644 --- a/lib/libfdt/fdt_rw.c +++ b/lib/libfdt/fdt_rw.c @@ -1,52 +1,7 @@ /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #include "libfdt_env.h" @@ -88,9 +43,9 @@ static int _fdt_rw_check_header(void *fdt) #define FDT_RW_CHECK_HEADER(fdt) \ { \ - int err; \ - if ((err = _fdt_rw_check_header(fdt)) != 0) \ - return err; \ + int __err; \ + if ((__err = _fdt_rw_check_header(fdt)) != 0) \ + return __err; \ } static inline int _fdt_data_size(void *fdt) diff --git a/lib/libfdt/fdt_strerror.c b/lib/libfdt/fdt_strerror.c index 9b00c3a6e8..2f3cc243db 100644 --- a/lib/libfdt/fdt_strerror.c +++ b/lib/libfdt/fdt_strerror.c @@ -1,52 +1,7 @@ /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #include "libfdt_env.h" diff --git a/lib/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c index f422754de9..320a914991 100644 --- a/lib/libfdt/fdt_sw.c +++ b/lib/libfdt/fdt_sw.c @@ -1,52 +1,7 @@ /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #include "libfdt_env.h" @@ -107,6 +62,38 @@ int fdt_create(void *buf, int bufsize) return 0; } +int fdt_resize(void *fdt, void *buf, int bufsize) +{ + size_t headsize, tailsize; + char *oldtail, *newtail; + + FDT_SW_CHECK_HEADER(fdt); + + headsize = fdt_off_dt_struct(fdt); + tailsize = fdt_size_dt_strings(fdt); + + if ((headsize + tailsize) > bufsize) + return -FDT_ERR_NOSPACE; + + oldtail = (char *)fdt + fdt_totalsize(fdt) - tailsize; + newtail = (char *)buf + bufsize - tailsize; + + /* Two cases to avoid clobbering data if the old and new + * buffers partially overlap */ + if (buf <= fdt) { + memmove(buf, fdt, headsize); + memmove(newtail, oldtail, tailsize); + } else { + memmove(newtail, oldtail, tailsize); + memmove(buf, fdt, headsize); + } + + fdt_set_off_dt_strings(buf, bufsize); + fdt_set_totalsize(buf, bufsize); + + return 0; +} + int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size) { struct fdt_reserve_entry *re; diff --git a/lib/libfdt/fdt_wip.c b/lib/libfdt/fdt_wip.c index b9e3c4a742..3f2dfa573b 100644 --- a/lib/libfdt/fdt_wip.c +++ b/lib/libfdt/fdt_wip.c @@ -1,52 +1,7 @@ /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #include "libfdt_env.h" diff --git a/lib/libfdt/libfdt_internal.h b/lib/libfdt/libfdt_internal.h index 381133ba81..9a79fe85dd 100644 --- a/lib/libfdt/libfdt_internal.h +++ b/lib/libfdt/libfdt_internal.h @@ -3,52 +3,7 @@ /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause */ #include @@ -57,9 +12,9 @@ #define FDT_CHECK_HEADER(fdt) \ { \ - int err; \ - if ((err = fdt_check_header(fdt)) != 0) \ - return err; \ + int __err; \ + if ((__err = fdt_check_header(fdt)) != 0) \ + return __err; \ } int _fdt_check_node_offset(const void *fdt, int offset); diff --git a/lib/linux_compat.c b/lib/linux_compat.c new file mode 100644 index 0000000000..a3d4675f7e --- /dev/null +++ b/lib/linux_compat.c @@ -0,0 +1,47 @@ + +#include +#include + +struct p_current cur = { + .pid = 1, +}; +__maybe_unused struct p_current *current = &cur; + +unsigned long copy_from_user(void *dest, const void *src, + unsigned long count) +{ + memcpy((void *)dest, (void *)src, count); + return 0; +} + +void *kmalloc(size_t size, int flags) +{ + return memalign(ARCH_DMA_MINALIGN, size); +} + +void *kzalloc(size_t size, int flags) +{ + void *ptr = kmalloc(size, flags); + memset(ptr, 0, size); + return ptr; +} + +void *vzalloc(unsigned long size) +{ + return kzalloc(size, 0); +} + +struct kmem_cache *get_mem(int element_sz) +{ + struct kmem_cache *ret; + + ret = memalign(ARCH_DMA_MINALIGN, sizeof(struct kmem_cache)); + ret->sz = element_sz; + + return ret; +} + +void *kmem_cache_alloc(struct kmem_cache *obj, int flag) +{ + return memalign(ARCH_DMA_MINALIGN, obj->sz); +} diff --git a/lib/list_sort.c b/lib/list_sort.c new file mode 100644 index 0000000000..e841da53ee --- /dev/null +++ b/lib/list_sort.c @@ -0,0 +1,297 @@ +#ifndef __UBOOT__ +#include +#include +#include +#else +#include +#include +#include +#endif +#include +#include + +#define MAX_LIST_LENGTH_BITS 20 + +/* + * Returns a list organized in an intermediate format suited + * to chaining of merge() calls: null-terminated, no reserved or + * sentinel head node, "prev" links not maintained. + */ +static struct list_head *merge(void *priv, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b), + struct list_head *a, struct list_head *b) +{ + struct list_head head, *tail = &head; + + while (a && b) { + /* if equal, take 'a' -- important for sort stability */ + if ((*cmp)(priv, a, b) <= 0) { + tail->next = a; + a = a->next; + } else { + tail->next = b; + b = b->next; + } + tail = tail->next; + } + tail->next = a?:b; + return head.next; +} + +/* + * Combine final list merge with restoration of standard doubly-linked + * list structure. This approach duplicates code from merge(), but + * runs faster than the tidier alternatives of either a separate final + * prev-link restoration pass, or maintaining the prev links + * throughout. + */ +static void merge_and_restore_back_links(void *priv, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b), + struct list_head *head, + struct list_head *a, struct list_head *b) +{ + struct list_head *tail = head; + + while (a && b) { + /* if equal, take 'a' -- important for sort stability */ + if ((*cmp)(priv, a, b) <= 0) { + tail->next = a; + a->prev = tail; + a = a->next; + } else { + tail->next = b; + b->prev = tail; + b = b->next; + } + tail = tail->next; + } + tail->next = a ? : b; + + do { + /* + * In worst cases this loop may run many iterations. + * Continue callbacks to the client even though no + * element comparison is needed, so the client's cmp() + * routine can invoke cond_resched() periodically. + */ + (*cmp)(priv, tail->next, tail->next); + + tail->next->prev = tail; + tail = tail->next; + } while (tail->next); + + tail->next = head; + head->prev = tail; +} + +/** + * list_sort - sort a list + * @priv: private data, opaque to list_sort(), passed to @cmp + * @head: the list to sort + * @cmp: the elements comparison function + * + * This function implements "merge sort", which has O(nlog(n)) + * complexity. + * + * The comparison function @cmp must return a negative value if @a + * should sort before @b, and a positive value if @a should sort after + * @b. If @a and @b are equivalent, and their original relative + * ordering is to be preserved, @cmp must return 0. + */ +void list_sort(void *priv, struct list_head *head, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b)) +{ + struct list_head *part[MAX_LIST_LENGTH_BITS+1]; /* sorted partial lists + -- last slot is a sentinel */ + int lev; /* index into part[] */ + int max_lev = 0; + struct list_head *list; + + if (list_empty(head)) + return; + + memset(part, 0, sizeof(part)); + + head->prev->next = NULL; + list = head->next; + + while (list) { + struct list_head *cur = list; + list = list->next; + cur->next = NULL; + + for (lev = 0; part[lev]; lev++) { + cur = merge(priv, cmp, part[lev], cur); + part[lev] = NULL; + } + if (lev > max_lev) { + if (unlikely(lev >= ARRAY_SIZE(part)-1)) { + printk_once(KERN_DEBUG "list passed to" + " list_sort() too long for" + " efficiency\n"); + lev--; + } + max_lev = lev; + } + part[lev] = cur; + } + + for (lev = 0; lev < max_lev; lev++) + if (part[lev]) + list = merge(priv, cmp, part[lev], list); + + merge_and_restore_back_links(priv, cmp, head, part[max_lev], list); +} +EXPORT_SYMBOL(list_sort); + +#ifdef CONFIG_TEST_LIST_SORT + +#include + +/* + * The pattern of set bits in the list length determines which cases + * are hit in list_sort(). + */ +#define TEST_LIST_LEN (512+128+2) /* not including head */ + +#define TEST_POISON1 0xDEADBEEF +#define TEST_POISON2 0xA324354C + +struct debug_el { + unsigned int poison1; + struct list_head list; + unsigned int poison2; + int value; + unsigned serial; +}; + +/* Array, containing pointers to all elements in the test list */ +static struct debug_el **elts __initdata; + +static int __init check(struct debug_el *ela, struct debug_el *elb) +{ + if (ela->serial >= TEST_LIST_LEN) { + printk(KERN_ERR "list_sort_test: error: incorrect serial %d\n", + ela->serial); + return -EINVAL; + } + if (elb->serial >= TEST_LIST_LEN) { + printk(KERN_ERR "list_sort_test: error: incorrect serial %d\n", + elb->serial); + return -EINVAL; + } + if (elts[ela->serial] != ela || elts[elb->serial] != elb) { + printk(KERN_ERR "list_sort_test: error: phantom element\n"); + return -EINVAL; + } + if (ela->poison1 != TEST_POISON1 || ela->poison2 != TEST_POISON2) { + printk(KERN_ERR "list_sort_test: error: bad poison: %#x/%#x\n", + ela->poison1, ela->poison2); + return -EINVAL; + } + if (elb->poison1 != TEST_POISON1 || elb->poison2 != TEST_POISON2) { + printk(KERN_ERR "list_sort_test: error: bad poison: %#x/%#x\n", + elb->poison1, elb->poison2); + return -EINVAL; + } + return 0; +} + +static int __init cmp(void *priv, struct list_head *a, struct list_head *b) +{ + struct debug_el *ela, *elb; + + ela = container_of(a, struct debug_el, list); + elb = container_of(b, struct debug_el, list); + + check(ela, elb); + return ela->value - elb->value; +} + +static int __init list_sort_test(void) +{ + int i, count = 1, err = -EINVAL; + struct debug_el *el; + struct list_head *cur, *tmp; + LIST_HEAD(head); + + printk(KERN_DEBUG "list_sort_test: start testing list_sort()\n"); + + elts = kmalloc(sizeof(void *) * TEST_LIST_LEN, GFP_KERNEL); + if (!elts) { + printk(KERN_ERR "list_sort_test: error: cannot allocate " + "memory\n"); + goto exit; + } + + for (i = 0; i < TEST_LIST_LEN; i++) { + el = kmalloc(sizeof(*el), GFP_KERNEL); + if (!el) { + printk(KERN_ERR "list_sort_test: error: cannot " + "allocate memory\n"); + goto exit; + } + /* force some equivalencies */ + el->value = prandom_u32() % (TEST_LIST_LEN / 3); + el->serial = i; + el->poison1 = TEST_POISON1; + el->poison2 = TEST_POISON2; + elts[i] = el; + list_add_tail(&el->list, &head); + } + + list_sort(NULL, &head, cmp); + + for (cur = head.next; cur->next != &head; cur = cur->next) { + struct debug_el *el1; + int cmp_result; + + if (cur->next->prev != cur) { + printk(KERN_ERR "list_sort_test: error: list is " + "corrupted\n"); + goto exit; + } + + cmp_result = cmp(NULL, cur, cur->next); + if (cmp_result > 0) { + printk(KERN_ERR "list_sort_test: error: list is not " + "sorted\n"); + goto exit; + } + + el = container_of(cur, struct debug_el, list); + el1 = container_of(cur->next, struct debug_el, list); + if (cmp_result == 0 && el->serial >= el1->serial) { + printk(KERN_ERR "list_sort_test: error: order of " + "equivalent elements not preserved\n"); + goto exit; + } + + if (check(el, el1)) { + printk(KERN_ERR "list_sort_test: error: element check " + "failed\n"); + goto exit; + } + count++; + } + + if (count != TEST_LIST_LEN) { + printk(KERN_ERR "list_sort_test: error: bad list length %d", + count); + goto exit; + } + + err = 0; +exit: + kfree(elts); + list_for_each_safe(cur, tmp, &head) { + list_del(cur); + kfree(container_of(cur, struct debug_el, list)); + } + return err; +} +module_init(list_sort_test); +#endif /* CONFIG_TEST_LIST_SORT */ diff --git a/lib/lmb.c b/lib/lmb.c index 081e4181b4..031f0e1ac8 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -236,7 +236,7 @@ long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) return lmb_add_region(_rgn, base, size); } -long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, +static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) { unsigned long i; @@ -295,7 +295,10 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phy if (max_addr == LMB_ALLOC_ANYWHERE) base = lmb_align_down(lmbbase + lmbsize - size, align); else if (lmbbase < max_addr) { - base = min(lmbbase + lmbsize, max_addr); + base = lmbbase + lmbsize; + if (base < lmbbase) + base = -1; + base = min(base, max_addr); base = lmb_align_down(base - size, align); } else continue; @@ -332,14 +335,12 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) return 0; } -void __board_lmb_reserve(struct lmb *lmb) +__weak void board_lmb_reserve(struct lmb *lmb) { /* please define platform specific board_lmb_reserve() */ } -void board_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__board_lmb_reserve"))); -void __arch_lmb_reserve(struct lmb *lmb) +__weak void arch_lmb_reserve(struct lmb *lmb) { /* please define platform specific arch_lmb_reserve() */ } -void arch_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__arch_lmb_reserve"))); diff --git a/lib/lzma/LzmaTools.c b/lib/lzma/LzmaTools.c index 8d1165e11b..f88629b74f 100644 --- a/lib/lzma/LzmaTools.c +++ b/lib/lzma/LzmaTools.c @@ -34,8 +34,8 @@ #include #include -static void *SzAlloc(void *p, size_t size) { p = p; return malloc(size); } -static void SzFree(void *p, void *address) { p = p; free(address); } +static void *SzAlloc(void *p, size_t size) { return malloc(size); } +static void SzFree(void *p, void *address) { free(address); } int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize, unsigned char *inStream, SizeT length) @@ -97,16 +97,23 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize, g_Alloc.Alloc = SzAlloc; g_Alloc.Free = SzFree; + /* Short-circuit early if we know the buffer can't hold the results. */ + if (outSizeFull != (SizeT)-1 && *uncompressedSize < outSizeFull) + return SZ_ERROR_OUTPUT_EOF; + /* Decompress */ - outProcessed = outSizeFull; + outProcessed = min(outSizeFull, *uncompressedSize); WATCHDOG_RESET(); res = LzmaDecode( outStream, &outProcessed, inStream + LZMA_DATA_OFFSET, &compressedSize, - inStream, LZMA_PROPS_SIZE, LZMA_FINISH_ANY, &state, &g_Alloc); + inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc); *uncompressedSize = outProcessed; + + debug("LZMA: Uncompressed ............... 0x%zx\n", outProcessed); + if (res != SZ_OK) { return res; } diff --git a/lib/lzma/Makefile b/lib/lzma/Makefile index 412e187c57..b6c80671b9 100644 --- a/lib/lzma/Makefile +++ b/lib/lzma/Makefile @@ -8,28 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk +ccflags-y += -D_LZMA_PROB32 -LIB = $(obj)liblzma.o - -SOBJS = - -CFLAGS += -D_LZMA_PROB32 - -COBJS-$(CONFIG_LZMA) += LzmaDec.o LzmaTools.o - -COBJS = $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += LzmaDec.o LzmaTools.o diff --git a/lib/lzo/Makefile b/lib/lzo/Makefile index 516519a1f8..2936544abc 100644 --- a/lib/lzo/Makefile +++ b/lib/lzo/Makefile @@ -5,26 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)liblzo.o - -SOBJS = - -COBJS-$(CONFIG_LZO) += lzo1x_decompress.o - -COBJS = $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += lzo1x_decompress.o diff --git a/lib/lzo/lzo1x_decompress.c b/lib/lzo/lzo1x_decompress.c index e6ff708f11..ebdf10b988 100644 --- a/lib/lzo/lzo1x_decompress.c +++ b/lib/lzo/lzo1x_decompress.c @@ -68,13 +68,14 @@ int lzop_decompress(const unsigned char *src, size_t src_len, unsigned char *start = dst; const unsigned char *send = src + src_len; u32 slen, dlen; - size_t tmp; + size_t tmp, remaining; int r; src = parse_header(src); if (!src) return LZO_E_ERROR; + remaining = *dst_len; while (src < send) { /* read uncompressed block size */ dlen = get_unaligned_be32(src); @@ -93,18 +94,25 @@ int lzop_decompress(const unsigned char *src, size_t src_len, if (slen <= 0 || slen > dlen) return LZO_E_ERROR; + /* abort if buffer ran out of room */ + if (dlen > remaining) + return LZO_E_OUTPUT_OVERRUN; + /* decompress */ tmp = dlen; r = lzo1x_decompress_safe((u8 *) src, slen, dst, &tmp); - if (r != LZO_E_OK) + if (r != LZO_E_OK) { + *dst_len = dst - start; return r; + } if (dlen != tmp) return LZO_E_ERROR; src += slen; dst += dlen; + remaining -= dlen; } return LZO_E_INPUT_OVERRUN; diff --git a/lib/rbtree.c b/lib/rbtree.c index b05f1ab7f5..5de3bf4026 100644 --- a/lib/rbtree.c +++ b/lib/rbtree.c @@ -2,283 +2,411 @@ Red Black Trees (C) 1999 Andrea Arcangeli (C) 2002 David Woodhouse + (C) 2012 Michel Lespinasse * SPDX-License-Identifier: GPL-2.0+ linux/lib/rbtree.c */ +#include +#ifndef __UBOOT__ +#include +#else #include -#include +#endif +/* + * red-black trees properties: http://en.wikipedia.org/wiki/Rbtree + * + * 1) A node is either red or black + * 2) The root is black + * 3) All leaves (NULL) are black + * 4) Both children of every red node are black + * 5) Every simple path from root to leaves contains the same number + * of black nodes. + * + * 4 and 5 give the O(log n) guarantee, since 4 implies you cannot have two + * consecutive red nodes in a path and every red node is therefore followed by + * a black. So if B is the number of black nodes on every simple path (as per + * 5), then the longest possible path due to 4 is 2B. + * + * We shall indicate color with case, where black nodes are uppercase and red + * nodes will be lowercase. Unknown color nodes shall be drawn as red within + * parentheses and have some accompanying text comment. + */ -static void __rb_rotate_left(struct rb_node *node, struct rb_root *root) +static inline void rb_set_black(struct rb_node *rb) { - struct rb_node *right = node->rb_right; - struct rb_node *parent = rb_parent(node); - - if ((node->rb_right = right->rb_left)) - rb_set_parent(right->rb_left, node); - right->rb_left = node; - - rb_set_parent(right, parent); - - if (parent) - { - if (node == parent->rb_left) - parent->rb_left = right; - else - parent->rb_right = right; - } - else - root->rb_node = right; - rb_set_parent(node, right); + rb->__rb_parent_color |= RB_BLACK; } -static void __rb_rotate_right(struct rb_node *node, struct rb_root *root) +static inline struct rb_node *rb_red_parent(struct rb_node *red) { - struct rb_node *left = node->rb_left; - struct rb_node *parent = rb_parent(node); - - if ((node->rb_left = left->rb_right)) - rb_set_parent(left->rb_right, node); - left->rb_right = node; - - rb_set_parent(left, parent); + return (struct rb_node *)red->__rb_parent_color; +} - if (parent) - { - if (node == parent->rb_right) - parent->rb_right = left; - else - parent->rb_left = left; - } - else - root->rb_node = left; - rb_set_parent(node, left); +/* + * Helper function for rotations: + * - old's parent and color get assigned to new + * - old gets assigned new as a parent and 'color' as a color. + */ +static inline void +__rb_rotate_set_parents(struct rb_node *old, struct rb_node *new, + struct rb_root *root, int color) +{ + struct rb_node *parent = rb_parent(old); + new->__rb_parent_color = old->__rb_parent_color; + rb_set_parent_color(old, new, color); + __rb_change_child(old, new, parent, root); } -void rb_insert_color(struct rb_node *node, struct rb_root *root) +static __always_inline void +__rb_insert(struct rb_node *node, struct rb_root *root, + void (*augment_rotate)(struct rb_node *old, struct rb_node *new)) { - struct rb_node *parent, *gparent; - - while ((parent = rb_parent(node)) && rb_is_red(parent)) - { - gparent = rb_parent(parent); - - if (parent == gparent->rb_left) - { - { - register struct rb_node *uncle = gparent->rb_right; - if (uncle && rb_is_red(uncle)) - { - rb_set_black(uncle); - rb_set_black(parent); - rb_set_red(gparent); - node = gparent; - continue; - } + struct rb_node *parent = rb_red_parent(node), *gparent, *tmp; + + while (true) { + /* + * Loop invariant: node is red + * + * If there is a black parent, we are done. + * Otherwise, take some corrective action as we don't + * want a red root or two consecutive red nodes. + */ + if (!parent) { + rb_set_parent_color(node, NULL, RB_BLACK); + break; + } else if (rb_is_black(parent)) + break; + + gparent = rb_red_parent(parent); + + tmp = gparent->rb_right; + if (parent != tmp) { /* parent == gparent->rb_left */ + if (tmp && rb_is_red(tmp)) { + /* + * Case 1 - color flips + * + * G g + * / \ / \ + * p u --> P U + * / / + * n N + * + * However, since g's parent might be red, and + * 4) does not allow this, we need to recurse + * at g. + */ + rb_set_parent_color(tmp, gparent, RB_BLACK); + rb_set_parent_color(parent, gparent, RB_BLACK); + node = gparent; + parent = rb_parent(node); + rb_set_parent_color(node, parent, RB_RED); + continue; } - if (parent->rb_right == node) - { - register struct rb_node *tmp; - __rb_rotate_left(parent, root); - tmp = parent; + tmp = parent->rb_right; + if (node == tmp) { + /* + * Case 2 - left rotate at parent + * + * G G + * / \ / \ + * p U --> n U + * \ / + * n p + * + * This still leaves us in violation of 4), the + * continuation into Case 3 will fix that. + */ + parent->rb_right = tmp = node->rb_left; + node->rb_left = parent; + if (tmp) + rb_set_parent_color(tmp, parent, + RB_BLACK); + rb_set_parent_color(parent, node, RB_RED); + augment_rotate(parent, node); parent = node; - node = tmp; + tmp = node->rb_right; } - rb_set_black(parent); - rb_set_red(gparent); - __rb_rotate_right(gparent, root); + /* + * Case 3 - right rotate at gparent + * + * G P + * / \ / \ + * p U --> n g + * / \ + * n U + */ + gparent->rb_left = tmp; /* == parent->rb_right */ + parent->rb_right = gparent; + if (tmp) + rb_set_parent_color(tmp, gparent, RB_BLACK); + __rb_rotate_set_parents(gparent, parent, root, RB_RED); + augment_rotate(gparent, parent); + break; } else { - { - register struct rb_node *uncle = gparent->rb_left; - if (uncle && rb_is_red(uncle)) - { - rb_set_black(uncle); - rb_set_black(parent); - rb_set_red(gparent); - node = gparent; - continue; - } + tmp = gparent->rb_left; + if (tmp && rb_is_red(tmp)) { + /* Case 1 - color flips */ + rb_set_parent_color(tmp, gparent, RB_BLACK); + rb_set_parent_color(parent, gparent, RB_BLACK); + node = gparent; + parent = rb_parent(node); + rb_set_parent_color(node, parent, RB_RED); + continue; } - if (parent->rb_left == node) - { - register struct rb_node *tmp; - __rb_rotate_right(parent, root); - tmp = parent; + tmp = parent->rb_left; + if (node == tmp) { + /* Case 2 - right rotate at parent */ + parent->rb_left = tmp = node->rb_right; + node->rb_right = parent; + if (tmp) + rb_set_parent_color(tmp, parent, + RB_BLACK); + rb_set_parent_color(parent, node, RB_RED); + augment_rotate(parent, node); parent = node; - node = tmp; + tmp = node->rb_left; } - rb_set_black(parent); - rb_set_red(gparent); - __rb_rotate_left(gparent, root); + /* Case 3 - left rotate at gparent */ + gparent->rb_right = tmp; /* == parent->rb_left */ + parent->rb_left = gparent; + if (tmp) + rb_set_parent_color(tmp, gparent, RB_BLACK); + __rb_rotate_set_parents(gparent, parent, root, RB_RED); + augment_rotate(gparent, parent); + break; } } - - rb_set_black(root->rb_node); } -static void __rb_erase_color(struct rb_node *node, struct rb_node *parent, - struct rb_root *root) +/* + * Inline version for rb_erase() use - we want to be able to inline + * and eliminate the dummy_rotate callback there + */ +static __always_inline void +____rb_erase_color(struct rb_node *parent, struct rb_root *root, + void (*augment_rotate)(struct rb_node *old, struct rb_node *new)) { - struct rb_node *other; - - while ((!node || rb_is_black(node)) && node != root->rb_node) - { - if (parent->rb_left == node) - { - other = parent->rb_right; - if (rb_is_red(other)) - { - rb_set_black(other); - rb_set_red(parent); - __rb_rotate_left(parent, root); - other = parent->rb_right; - } - if ((!other->rb_left || rb_is_black(other->rb_left)) && - (!other->rb_right || rb_is_black(other->rb_right))) - { - rb_set_red(other); - node = parent; - parent = rb_parent(node); + struct rb_node *node = NULL, *sibling, *tmp1, *tmp2; + + while (true) { + /* + * Loop invariants: + * - node is black (or NULL on first iteration) + * - node is not the root (parent is not NULL) + * - All leaf paths going through parent and node have a + * black node count that is 1 lower than other leaf paths. + */ + sibling = parent->rb_right; + if (node != sibling) { /* node == parent->rb_left */ + if (rb_is_red(sibling)) { + /* + * Case 1 - left rotate at parent + * + * P S + * / \ / \ + * N s --> p Sr + * / \ / \ + * Sl Sr N Sl + */ + parent->rb_right = tmp1 = sibling->rb_left; + sibling->rb_left = parent; + rb_set_parent_color(tmp1, parent, RB_BLACK); + __rb_rotate_set_parents(parent, sibling, root, + RB_RED); + augment_rotate(parent, sibling); + sibling = tmp1; } - else - { - if (!other->rb_right || rb_is_black(other->rb_right)) - { - struct rb_node *o_left; - if ((o_left = other->rb_left)) - rb_set_black(o_left); - rb_set_red(other); - __rb_rotate_right(other, root); - other = parent->rb_right; + tmp1 = sibling->rb_right; + if (!tmp1 || rb_is_black(tmp1)) { + tmp2 = sibling->rb_left; + if (!tmp2 || rb_is_black(tmp2)) { + /* + * Case 2 - sibling color flip + * (p could be either color here) + * + * (p) (p) + * / \ / \ + * N S --> N s + * / \ / \ + * Sl Sr Sl Sr + * + * This leaves us violating 5) which + * can be fixed by flipping p to black + * if it was red, or by recursing at p. + * p is red when coming from Case 1. + */ + rb_set_parent_color(sibling, parent, + RB_RED); + if (rb_is_red(parent)) + rb_set_black(parent); + else { + node = parent; + parent = rb_parent(node); + if (parent) + continue; + } + break; } - rb_set_color(other, rb_color(parent)); - rb_set_black(parent); - if (other->rb_right) - rb_set_black(other->rb_right); - __rb_rotate_left(parent, root); - node = root->rb_node; - break; + /* + * Case 3 - right rotate at sibling + * (p could be either color here) + * + * (p) (p) + * / \ / \ + * N S --> N Sl + * / \ \ + * sl Sr s + * \ + * Sr + */ + sibling->rb_left = tmp1 = tmp2->rb_right; + tmp2->rb_right = sibling; + parent->rb_right = tmp2; + if (tmp1) + rb_set_parent_color(tmp1, sibling, + RB_BLACK); + augment_rotate(sibling, tmp2); + tmp1 = sibling; + sibling = tmp2; } - } - else - { - other = parent->rb_left; - if (rb_is_red(other)) - { - rb_set_black(other); - rb_set_red(parent); - __rb_rotate_right(parent, root); - other = parent->rb_left; - } - if ((!other->rb_left || rb_is_black(other->rb_left)) && - (!other->rb_right || rb_is_black(other->rb_right))) - { - rb_set_red(other); - node = parent; - parent = rb_parent(node); + /* + * Case 4 - left rotate at parent + color flips + * (p and sl could be either color here. + * After rotation, p becomes black, s acquires + * p's color, and sl keeps its color) + * + * (p) (s) + * / \ / \ + * N S --> P Sr + * / \ / \ + * (sl) sr N (sl) + */ + parent->rb_right = tmp2 = sibling->rb_left; + sibling->rb_left = parent; + rb_set_parent_color(tmp1, sibling, RB_BLACK); + if (tmp2) + rb_set_parent(tmp2, parent); + __rb_rotate_set_parents(parent, sibling, root, + RB_BLACK); + augment_rotate(parent, sibling); + break; + } else { + sibling = parent->rb_left; + if (rb_is_red(sibling)) { + /* Case 1 - right rotate at parent */ + parent->rb_left = tmp1 = sibling->rb_right; + sibling->rb_right = parent; + rb_set_parent_color(tmp1, parent, RB_BLACK); + __rb_rotate_set_parents(parent, sibling, root, + RB_RED); + augment_rotate(parent, sibling); + sibling = tmp1; } - else - { - if (!other->rb_left || rb_is_black(other->rb_left)) - { - register struct rb_node *o_right; - if ((o_right = other->rb_right)) - rb_set_black(o_right); - rb_set_red(other); - __rb_rotate_left(other, root); - other = parent->rb_left; + tmp1 = sibling->rb_left; + if (!tmp1 || rb_is_black(tmp1)) { + tmp2 = sibling->rb_right; + if (!tmp2 || rb_is_black(tmp2)) { + /* Case 2 - sibling color flip */ + rb_set_parent_color(sibling, parent, + RB_RED); + if (rb_is_red(parent)) + rb_set_black(parent); + else { + node = parent; + parent = rb_parent(node); + if (parent) + continue; + } + break; } - rb_set_color(other, rb_color(parent)); - rb_set_black(parent); - if (other->rb_left) - rb_set_black(other->rb_left); - __rb_rotate_right(parent, root); - node = root->rb_node; - break; + /* Case 3 - right rotate at sibling */ + sibling->rb_right = tmp1 = tmp2->rb_left; + tmp2->rb_left = sibling; + parent->rb_left = tmp2; + if (tmp1) + rb_set_parent_color(tmp1, sibling, + RB_BLACK); + augment_rotate(sibling, tmp2); + tmp1 = sibling; + sibling = tmp2; } + /* Case 4 - left rotate at parent + color flips */ + parent->rb_left = tmp2 = sibling->rb_right; + sibling->rb_right = parent; + rb_set_parent_color(tmp1, sibling, RB_BLACK); + if (tmp2) + rb_set_parent(tmp2, parent); + __rb_rotate_set_parents(parent, sibling, root, + RB_BLACK); + augment_rotate(parent, sibling); + break; } } - if (node) - rb_set_black(node); } +/* Non-inline version for rb_erase_augmented() use */ +void __rb_erase_color(struct rb_node *parent, struct rb_root *root, + void (*augment_rotate)(struct rb_node *old, struct rb_node *new)) +{ + ____rb_erase_color(parent, root, augment_rotate); +} +EXPORT_SYMBOL(__rb_erase_color); + +/* + * Non-augmented rbtree manipulation functions. + * + * We use dummy augmented callbacks here, and have the compiler optimize them + * out of the rb_insert_color() and rb_erase() function definitions. + */ + +static inline void dummy_propagate(struct rb_node *node, struct rb_node *stop) {} +static inline void dummy_copy(struct rb_node *old, struct rb_node *new) {} +static inline void dummy_rotate(struct rb_node *old, struct rb_node *new) {} + +static const struct rb_augment_callbacks dummy_callbacks = { + dummy_propagate, dummy_copy, dummy_rotate +}; + +void rb_insert_color(struct rb_node *node, struct rb_root *root) +{ + __rb_insert(node, root, dummy_rotate); +} +EXPORT_SYMBOL(rb_insert_color); + void rb_erase(struct rb_node *node, struct rb_root *root) { - struct rb_node *child, *parent; - int color; - - if (!node->rb_left) - child = node->rb_right; - else if (!node->rb_right) - child = node->rb_left; - else - { - struct rb_node *old = node, *left; - - node = node->rb_right; - while ((left = node->rb_left) != NULL) - node = left; - child = node->rb_right; - parent = rb_parent(node); - color = rb_color(node); - - if (child) - rb_set_parent(child, parent); - if (parent == old) { - parent->rb_right = child; - parent = node; - } else - parent->rb_left = child; - - node->rb_parent_color = old->rb_parent_color; - node->rb_right = old->rb_right; - node->rb_left = old->rb_left; - - if (rb_parent(old)) - { - if (rb_parent(old)->rb_left == old) - rb_parent(old)->rb_left = node; - else - rb_parent(old)->rb_right = node; - } else - root->rb_node = node; - - rb_set_parent(old->rb_left, node); - if (old->rb_right) - rb_set_parent(old->rb_right, node); - goto color; - } + struct rb_node *rebalance; + rebalance = __rb_erase_augmented(node, root, &dummy_callbacks); + if (rebalance) + ____rb_erase_color(rebalance, root, dummy_rotate); +} +EXPORT_SYMBOL(rb_erase); - parent = rb_parent(node); - color = rb_color(node); - - if (child) - rb_set_parent(child, parent); - if (parent) - { - if (parent->rb_left == node) - parent->rb_left = child; - else - parent->rb_right = child; - } - else - root->rb_node = child; +/* + * Augmented rbtree manipulation functions. + * + * This instantiates the same __always_inline functions as in the non-augmented + * case, but this time with user-defined callbacks. + */ - color: - if (color == RB_BLACK) - __rb_erase_color(child, parent, root); +void __rb_insert_augmented(struct rb_node *node, struct rb_root *root, + void (*augment_rotate)(struct rb_node *old, struct rb_node *new)) +{ + __rb_insert(node, root, augment_rotate); } +EXPORT_SYMBOL(__rb_insert_augmented); /* * This function returns the first node (in sort order) of the tree. */ -struct rb_node *rb_first(struct rb_root *root) +struct rb_node *rb_first(const struct rb_root *root) { struct rb_node *n; @@ -289,8 +417,9 @@ struct rb_node *rb_first(struct rb_root *root) n = n->rb_left; return n; } +EXPORT_SYMBOL(rb_first); -struct rb_node *rb_last(struct rb_root *root) +struct rb_node *rb_last(const struct rb_root *root) { struct rb_node *n; @@ -301,58 +430,68 @@ struct rb_node *rb_last(struct rb_root *root) n = n->rb_right; return n; } +EXPORT_SYMBOL(rb_last); -struct rb_node *rb_next(struct rb_node *node) +struct rb_node *rb_next(const struct rb_node *node) { struct rb_node *parent; - if (rb_parent(node) == node) + if (RB_EMPTY_NODE(node)) return NULL; - /* If we have a right-hand child, go down and then left as far - as we can. */ + /* + * If we have a right-hand child, go down and then left as far + * as we can. + */ if (node->rb_right) { - node = node->rb_right; + node = node->rb_right; while (node->rb_left) node=node->rb_left; - return node; + return (struct rb_node *)node; } - /* No right-hand children. Everything down and left is - smaller than us, so any 'next' node must be in the general - direction of our parent. Go up the tree; any time the - ancestor is a right-hand child of its parent, keep going - up. First time it's a left-hand child of its parent, said - parent is our 'next' node. */ + /* + * No right-hand children. Everything down and left is smaller than us, + * so any 'next' node must be in the general direction of our parent. + * Go up the tree; any time the ancestor is a right-hand child of its + * parent, keep going up. First time it's a left-hand child of its + * parent, said parent is our 'next' node. + */ while ((parent = rb_parent(node)) && node == parent->rb_right) node = parent; return parent; } +EXPORT_SYMBOL(rb_next); -struct rb_node *rb_prev(struct rb_node *node) +struct rb_node *rb_prev(const struct rb_node *node) { struct rb_node *parent; - if (rb_parent(node) == node) + if (RB_EMPTY_NODE(node)) return NULL; - /* If we have a left-hand child, go down and then right as far - as we can. */ + /* + * If we have a left-hand child, go down and then right as far + * as we can. + */ if (node->rb_left) { - node = node->rb_left; + node = node->rb_left; while (node->rb_right) node=node->rb_right; - return node; + return (struct rb_node *)node; } - /* No left-hand children. Go up till we find an ancestor which - is a right-hand child of its parent */ + /* + * No left-hand children. Go up till we find an ancestor which + * is a right-hand child of its parent. + */ while ((parent = rb_parent(node)) && node == parent->rb_left) node = parent; return parent; } +EXPORT_SYMBOL(rb_prev); void rb_replace_node(struct rb_node *victim, struct rb_node *new, struct rb_root *root) @@ -360,14 +499,7 @@ void rb_replace_node(struct rb_node *victim, struct rb_node *new, struct rb_node *parent = rb_parent(victim); /* Set the surrounding nodes to point to the replacement */ - if (parent) { - if (victim == parent->rb_left) - parent->rb_left = new; - else - parent->rb_right = new; - } else { - root->rb_node = new; - } + __rb_change_child(victim, new, parent, root); if (victim->rb_left) rb_set_parent(victim->rb_left, new); if (victim->rb_right) @@ -376,3 +508,44 @@ void rb_replace_node(struct rb_node *victim, struct rb_node *new, /* Copy the pointers/colour from the victim to the replacement */ *new = *victim; } +EXPORT_SYMBOL(rb_replace_node); + +static struct rb_node *rb_left_deepest_node(const struct rb_node *node) +{ + for (;;) { + if (node->rb_left) + node = node->rb_left; + else if (node->rb_right) + node = node->rb_right; + else + return (struct rb_node *)node; + } +} + +struct rb_node *rb_next_postorder(const struct rb_node *node) +{ + const struct rb_node *parent; + if (!node) + return NULL; + parent = rb_parent(node); + + /* If we're sitting on node, we've already seen our children */ + if (parent && node == parent->rb_left && parent->rb_right) { + /* If we are the parent's left node, go to the parent's right + * node then all the way down to the left */ + return rb_left_deepest_node(parent->rb_right); + } else + /* Otherwise we are the parent's right node, and the parent + * should be next */ + return (struct rb_node *)parent; +} +EXPORT_SYMBOL(rb_next_postorder); + +struct rb_node *rb_first_postorder(const struct rb_root *root) +{ + if (!root->rb_node) + return NULL; + + return rb_left_deepest_node(root->rb_node); +} +EXPORT_SYMBOL(rb_first_postorder); diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig new file mode 100644 index 0000000000..1268a1b2db --- /dev/null +++ b/lib/rsa/Kconfig @@ -0,0 +1,27 @@ +config RSA + bool "Use RSA Library" + select RSA_FREESCALE_EXP if FSL_CAAM + select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP + help + RSA support. This enables the RSA algorithm used for FIT image + verification in U-Boot. + See doc/uImage.FIT/signature.txt for more details. + +if RSA +config RSA_SOFTWARE_EXP + bool "Enable driver for RSA Modular Exponentiation in software" + depends on DM && RSA + help + Enables driver for modular exponentiation in software. This is a RSA + algorithm used in FIT image verification. It required RSA Key as + input. + See doc/uImage.FIT/signature.txt for more details. + +config RSA_FREESCALE_EXP + bool "Enable RSA Modular Exponentiation with FSL crypto accelerator" + depends on DM && RSA && FSL_CAAM + help + Enables driver for RSA modular exponentiation using Freescale cryptographic + accelerator - CAAM. + +endif diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile index decd6e509d..cc25b3ce6d 100644 --- a/lib/rsa/Makefile +++ b/lib/rsa/Makefile @@ -7,26 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)librsa.o - -ifdef CONFIG_FIT_SIGNATURE -COBJS-$(CONFIG_RSA) += rsa-verify.o -endif - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o rsa-mod-exp.o diff --git a/lib/rsa/rsa-checksum.c b/lib/rsa/rsa-checksum.c new file mode 100644 index 0000000000..68d9d651b0 --- /dev/null +++ b/lib/rsa/rsa-checksum.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2013, Andreas Oetken. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef USE_HOSTCC +#include +#include +#include +#include +#include +#include +#else +#include "fdt_host.h" +#include +#include +#endif +#include + +/* PKCS 1.5 paddings as described in the RSA PKCS#1 v2.1 standard. */ + +const uint8_t padding_sha256_rsa2048[RSA2048_BYTES - SHA256_SUM_LEN] = { +0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, +0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, +0x00, 0x04, 0x20 +}; + +const uint8_t padding_sha1_rsa2048[RSA2048_BYTES - SHA1_SUM_LEN] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x21, 0x30, + 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a, + 0x05, 0x00, 0x04, 0x14 +}; + +const uint8_t padding_sha256_rsa4096[RSA4096_BYTES - SHA256_SUM_LEN] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, + 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, + 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 +}; + +int hash_calculate(const char *name, + const struct image_region region[], + int region_count, uint8_t *checksum) +{ + struct hash_algo *algo; + int ret = 0; + void *ctx; + uint32_t i; + i = 0; + + ret = hash_progressive_lookup_algo(name, &algo); + if (ret) + return ret; + + ret = algo->hash_init(algo, &ctx); + if (ret) + return ret; + + for (i = 0; i < region_count - 1; i++) { + ret = algo->hash_update(algo, ctx, region[i].data, + region[i].size, 0); + if (ret) + return ret; + } + + ret = algo->hash_update(algo, ctx, region[i].data, region[i].size, 1); + if (ret) + return ret; + ret = algo->hash_finish(algo, ctx, checksum, algo->digest_size); + if (ret) + return ret; + + return 0; +} diff --git a/lib/rsa/rsa-mod-exp.c b/lib/rsa/rsa-mod-exp.c new file mode 100644 index 0000000000..4a6de2b932 --- /dev/null +++ b/lib/rsa/rsa-mod-exp.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2013, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef USE_HOSTCC +#include +#include +#include +#include +#include +#include +#include +#else +#include "fdt_host.h" +#include "mkimage.h" +#include +#endif +#include +#include + +#define UINT64_MULT32(v, multby) (((uint64_t)(v)) * ((uint32_t)(multby))) + +#define get_unaligned_be32(a) fdt32_to_cpu(*(uint32_t *)a) +#define put_unaligned_be32(a, b) (*(uint32_t *)(b) = cpu_to_fdt32(a)) + +/* Default public exponent for backward compatibility */ +#define RSA_DEFAULT_PUBEXP 65537 + +/** + * subtract_modulus() - subtract modulus from the given value + * + * @key: Key containing modulus to subtract + * @num: Number to subtract modulus from, as little endian word array + */ +static void subtract_modulus(const struct rsa_public_key *key, uint32_t num[]) +{ + int64_t acc = 0; + uint i; + + for (i = 0; i < key->len; i++) { + acc += (uint64_t)num[i] - key->modulus[i]; + num[i] = (uint32_t)acc; + acc >>= 32; + } +} + +/** + * greater_equal_modulus() - check if a value is >= modulus + * + * @key: Key containing modulus to check + * @num: Number to check against modulus, as little endian word array + * @return 0 if num < modulus, 1 if num >= modulus + */ +static int greater_equal_modulus(const struct rsa_public_key *key, + uint32_t num[]) +{ + int i; + + for (i = (int)key->len - 1; i >= 0; i--) { + if (num[i] < key->modulus[i]) + return 0; + if (num[i] > key->modulus[i]) + return 1; + } + + return 1; /* equal */ +} + +/** + * montgomery_mul_add_step() - Perform montgomery multiply-add step + * + * Operation: montgomery result[] += a * b[] / n0inv % modulus + * + * @key: RSA key + * @result: Place to put result, as little endian word array + * @a: Multiplier + * @b: Multiplicand, as little endian word array + */ +static void montgomery_mul_add_step(const struct rsa_public_key *key, + uint32_t result[], const uint32_t a, const uint32_t b[]) +{ + uint64_t acc_a, acc_b; + uint32_t d0; + uint i; + + acc_a = (uint64_t)a * b[0] + result[0]; + d0 = (uint32_t)acc_a * key->n0inv; + acc_b = (uint64_t)d0 * key->modulus[0] + (uint32_t)acc_a; + for (i = 1; i < key->len; i++) { + acc_a = (acc_a >> 32) + (uint64_t)a * b[i] + result[i]; + acc_b = (acc_b >> 32) + (uint64_t)d0 * key->modulus[i] + + (uint32_t)acc_a; + result[i - 1] = (uint32_t)acc_b; + } + + acc_a = (acc_a >> 32) + (acc_b >> 32); + + result[i - 1] = (uint32_t)acc_a; + + if (acc_a >> 32) + subtract_modulus(key, result); +} + +/** + * montgomery_mul() - Perform montgomery mutitply + * + * Operation: montgomery result[] = a[] * b[] / n0inv % modulus + * + * @key: RSA key + * @result: Place to put result, as little endian word array + * @a: Multiplier, as little endian word array + * @b: Multiplicand, as little endian word array + */ +static void montgomery_mul(const struct rsa_public_key *key, + uint32_t result[], uint32_t a[], const uint32_t b[]) +{ + uint i; + + for (i = 0; i < key->len; ++i) + result[i] = 0; + for (i = 0; i < key->len; ++i) + montgomery_mul_add_step(key, result, a[i], b); +} + +/** + * num_pub_exponent_bits() - Number of bits in the public exponent + * + * @key: RSA key + * @num_bits: Storage for the number of public exponent bits + */ +static int num_public_exponent_bits(const struct rsa_public_key *key, + int *num_bits) +{ + uint64_t exponent; + int exponent_bits; + const uint max_bits = (sizeof(exponent) * 8); + + exponent = key->exponent; + exponent_bits = 0; + + if (!exponent) { + *num_bits = exponent_bits; + return 0; + } + + for (exponent_bits = 1; exponent_bits < max_bits + 1; ++exponent_bits) + if (!(exponent >>= 1)) { + *num_bits = exponent_bits; + return 0; + } + + return -EINVAL; +} + +/** + * is_public_exponent_bit_set() - Check if a bit in the public exponent is set + * + * @key: RSA key + * @pos: The bit position to check + */ +static int is_public_exponent_bit_set(const struct rsa_public_key *key, + int pos) +{ + return key->exponent & (1ULL << pos); +} + +/** + * pow_mod() - in-place public exponentiation + * + * @key: RSA key + * @inout: Big-endian word array containing value and result + */ +static int pow_mod(const struct rsa_public_key *key, uint32_t *inout) +{ + uint32_t *result, *ptr; + uint i; + int j, k; + + /* Sanity check for stack size - key->len is in 32-bit words */ + if (key->len > RSA_MAX_KEY_BITS / 32) { + debug("RSA key words %u exceeds maximum %d\n", key->len, + RSA_MAX_KEY_BITS / 32); + return -EINVAL; + } + + uint32_t val[key->len], acc[key->len], tmp[key->len]; + uint32_t a_scaled[key->len]; + result = tmp; /* Re-use location. */ + + /* Convert from big endian byte array to little endian word array. */ + for (i = 0, ptr = inout + key->len - 1; i < key->len; i++, ptr--) + val[i] = get_unaligned_be32(ptr); + + if (0 != num_public_exponent_bits(key, &k)) + return -EINVAL; + + if (k < 2) { + debug("Public exponent is too short (%d bits, minimum 2)\n", + k); + return -EINVAL; + } + + if (!is_public_exponent_bit_set(key, 0)) { + debug("LSB of RSA public exponent must be set.\n"); + return -EINVAL; + } + + /* the bit at e[k-1] is 1 by definition, so start with: C := M */ + montgomery_mul(key, acc, val, key->rr); /* acc = a * RR / R mod n */ + /* retain scaled version for intermediate use */ + memcpy(a_scaled, acc, key->len * sizeof(a_scaled[0])); + + for (j = k - 2; j > 0; --j) { + montgomery_mul(key, tmp, acc, acc); /* tmp = acc^2 / R mod n */ + + if (is_public_exponent_bit_set(key, j)) { + /* acc = tmp * val / R mod n */ + montgomery_mul(key, acc, tmp, a_scaled); + } else { + /* e[j] == 0, copy tmp back to acc for next operation */ + memcpy(acc, tmp, key->len * sizeof(acc[0])); + } + } + + /* the bit at e[0] is always 1 */ + montgomery_mul(key, tmp, acc, acc); /* tmp = acc^2 / R mod n */ + montgomery_mul(key, acc, tmp, val); /* acc = tmp * a / R mod M */ + memcpy(result, acc, key->len * sizeof(result[0])); + + /* Make sure result < mod; result is at most 1x mod too large. */ + if (greater_equal_modulus(key, result)) + subtract_modulus(key, result); + + /* Convert to bigendian byte array */ + for (i = key->len - 1, ptr = inout; (int)i >= 0; i--, ptr++) + put_unaligned_be32(result[i], ptr); + return 0; +} + +static void rsa_convert_big_endian(uint32_t *dst, const uint32_t *src, int len) +{ + int i; + + for (i = 0; i < len; i++) + dst[i] = fdt32_to_cpu(src[len - 1 - i]); +} + +int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len, + struct key_prop *prop, uint8_t *out) +{ + struct rsa_public_key key; + int ret; + + if (!prop) { + debug("%s: Skipping invalid prop", __func__); + return -EBADF; + } + key.n0inv = prop->n0inv; + key.len = prop->num_bits; + + if (!prop->public_exponent) + key.exponent = RSA_DEFAULT_PUBEXP; + else + key.exponent = + fdt64_to_cpu(*((uint64_t *)(prop->public_exponent))); + + if (!key.len || !prop->modulus || !prop->rr) { + debug("%s: Missing RSA key info", __func__); + return -EFAULT; + } + + /* Sanity check for stack size */ + if (key.len > RSA_MAX_KEY_BITS || key.len < RSA_MIN_KEY_BITS) { + debug("RSA key bits %u outside allowed range %d..%d\n", + key.len, RSA_MIN_KEY_BITS, RSA_MAX_KEY_BITS); + return -EFAULT; + } + key.len /= sizeof(uint32_t) * 8; + uint32_t key1[key.len], key2[key.len]; + + key.modulus = key1; + key.rr = key2; + rsa_convert_big_endian(key.modulus, (uint32_t *)prop->modulus, key.len); + rsa_convert_big_endian(key.rr, (uint32_t *)prop->rr, key.len); + if (!key.modulus || !key.rr) { + debug("%s: Out of memory", __func__); + return -ENOMEM; + } + + uint32_t buf[sig_len / sizeof(uint32_t)]; + + memcpy(buf, sig, sig_len); + + ret = pow_mod(&key, buf); + if (ret) + return ret; + + memcpy(out, buf, sig_len); + + return 0; +} diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 549130eda1..5d9716f013 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -76,6 +76,7 @@ static int rsa_get_pub_key(const char *keydir, const char *name, RSA **rsap) rsa = EVP_PKEY_get1_RSA(key); if (!rsa) { rsa_err("Couldn't convert to a RSA style key"); + ret = -EINVAL; goto err_rsa; } fclose(f); @@ -159,8 +160,9 @@ static void rsa_remove(void) EVP_cleanup(); } -static int rsa_sign_with_key(RSA *rsa, const struct image_region region[], - int region_count, uint8_t **sigp, uint *sig_size) +static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, + const struct image_region region[], int region_count, + uint8_t **sigp, uint *sig_size) { EVP_PKEY *key; EVP_MD_CTX *context; @@ -192,7 +194,7 @@ static int rsa_sign_with_key(RSA *rsa, const struct image_region region[], goto err_create; } EVP_MD_CTX_init(context); - if (!EVP_SignInit(context, EVP_sha1())) { + if (!EVP_SignInit(context, checksum_algo->calculate_sign())) { ret = rsa_err("Signer setup failed"); goto err_sign; } @@ -242,7 +244,8 @@ int rsa_sign(struct image_sign_info *info, ret = rsa_get_priv_key(info->keydir, info->keyname, &rsa); if (ret) goto err_priv; - ret = rsa_sign_with_key(rsa, region, region_count, sigp, sig_len); + ret = rsa_sign_with_key(rsa, info->algo->checksum, region, + region_count, sigp, sig_len); if (ret) goto err_sign; @@ -258,11 +261,58 @@ err_priv: return ret; } +/* + * rsa_get_exponent(): - Get the public exponent from an RSA key + */ +static int rsa_get_exponent(RSA *key, uint64_t *e) +{ + int ret; + BIGNUM *bn_te; + uint64_t te; + + ret = -EINVAL; + bn_te = NULL; + + if (!e) + goto cleanup; + + if (BN_num_bits(key->e) > 64) + goto cleanup; + + *e = BN_get_word(key->e); + + if (BN_num_bits(key->e) < 33) { + ret = 0; + goto cleanup; + } + + bn_te = BN_dup(key->e); + if (!bn_te) + goto cleanup; + + if (!BN_rshift(bn_te, bn_te, 32)) + goto cleanup; + + if (!BN_mask_bits(bn_te, 32)) + goto cleanup; + + te = BN_get_word(bn_te); + te <<= 32; + *e |= te; + ret = 0; + +cleanup: + if (bn_te) + BN_free(bn_te); + + return ret; +} + /* * rsa_get_params(): - Get the important parameters of an RSA public key */ -int rsa_get_params(RSA *key, uint32_t *n0_invp, BIGNUM **modulusp, - BIGNUM **r_squaredp) +int rsa_get_params(RSA *key, uint64_t *exponent, uint32_t *n0_invp, + BIGNUM **modulusp, BIGNUM **r_squaredp) { BIGNUM *big1, *big2, *big32, *big2_32; BIGNUM *n, *r, *r_squared, *tmp; @@ -284,6 +334,9 @@ int rsa_get_params(RSA *key, uint32_t *n0_invp, BIGNUM **modulusp, return -ENOMEM; } + if (0 != rsa_get_exponent(key, exponent)) + ret = -1; + if (!BN_copy(n, key->n) || !BN_set_word(big1, 1L) || !BN_set_word(big2, 2L) || !BN_set_word(big32, 32L)) ret = -1; @@ -384,6 +437,7 @@ static int fdt_add_bignum(void *blob, int noffset, const char *prop_name, int rsa_add_verify_data(struct image_sign_info *info, void *keydest) { BIGNUM *modulus, *r_squared; + uint64_t exponent; uint32_t n0_inv; int parent, node; char name[100]; @@ -395,7 +449,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) ret = rsa_get_pub_key(info->keydir, info->keyname, &rsa); if (ret) return ret; - ret = rsa_get_params(rsa, &n0_inv, &modulus, &r_squared); + ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared); if (ret) return ret; bits = BN_num_bits(modulus); @@ -403,11 +457,15 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) if (parent == -FDT_ERR_NOTFOUND) { parent = fdt_add_subnode(keydest, 0, FIT_SIG_NODENAME); if (parent < 0) { - fprintf(stderr, "Couldn't create signature node: %s\n", - fdt_strerror(parent)); - return -EINVAL; + ret = parent; + if (ret != -FDT_ERR_NOSPACE) { + fprintf(stderr, "Couldn't create signature node: %s\n", + fdt_strerror(parent)); + } } } + if (ret) + goto done; /* Either create or overwrite the named key node */ snprintf(name, sizeof(name), "key-%s", info->keyname); @@ -415,32 +473,50 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) if (node == -FDT_ERR_NOTFOUND) { node = fdt_add_subnode(keydest, parent, name); if (node < 0) { - fprintf(stderr, "Could not create key subnode: %s\n", - fdt_strerror(node)); - return -EINVAL; + ret = node; + if (ret != -FDT_ERR_NOSPACE) { + fprintf(stderr, "Could not create key subnode: %s\n", + fdt_strerror(node)); + } } } else if (node < 0) { fprintf(stderr, "Cannot select keys parent: %s\n", fdt_strerror(node)); - return -ENOSPC; + ret = node; } - ret = fdt_setprop_string(keydest, node, "key-name-hint", + if (!ret) { + ret = fdt_setprop_string(keydest, node, "key-name-hint", info->keyname); - ret |= fdt_setprop_u32(keydest, node, "rsa,num-bits", bits); - ret |= fdt_setprop_u32(keydest, node, "rsa,n0-inverse", n0_inv); - ret |= fdt_add_bignum(keydest, node, "rsa,modulus", modulus, bits); - ret |= fdt_add_bignum(keydest, node, "rsa,r-squared", r_squared, bits); - ret |= fdt_setprop_string(keydest, node, FIT_ALGO_PROP, - info->algo->name); + } + if (!ret) + ret = fdt_setprop_u32(keydest, node, "rsa,num-bits", bits); + if (!ret) + ret = fdt_setprop_u32(keydest, node, "rsa,n0-inverse", n0_inv); + if (!ret) { + ret = fdt_setprop_u64(keydest, node, "rsa,exponent", exponent); + } + if (!ret) { + ret = fdt_add_bignum(keydest, node, "rsa,modulus", modulus, + bits); + } + if (!ret) { + ret = fdt_add_bignum(keydest, node, "rsa,r-squared", r_squared, + bits); + } + if (!ret) { + ret = fdt_setprop_string(keydest, node, FIT_ALGO_PROP, + info->algo->name); + } if (info->require_keys) { - fdt_setprop_string(keydest, node, "required", - info->require_keys); + ret = fdt_setprop_string(keydest, node, "required", + info->require_keys); } +done: BN_free(modulus); BN_free(r_squared); if (ret) - return -EIO; + return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO; return 0; } diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 02cc4e3353..60126d2288 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -4,225 +4,60 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef USE_HOSTCC #include #include -#include -#include +#include #include #include +#include #include +#include +#else +#include "fdt_host.h" +#include "mkimage.h" +#include +#endif +#include +#include + +/* Default public exponent for backward compatibility */ +#define RSA_DEFAULT_PUBEXP 65537 /** - * struct rsa_public_key - holder for a public key + * rsa_verify_key() - Verify a signature against some data using RSA Key * - * An RSA public key consists of a modulus (typically called N), the inverse - * and R^2, where R is 2^(# key bits). - */ -struct rsa_public_key { - uint len; /* Length of modulus[] in number of uint32_t */ - uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */ - uint32_t *modulus; /* modulus as little endian array */ - uint32_t *rr; /* R^2 as little endian array */ -}; - -#define UINT64_MULT32(v, multby) (((uint64_t)(v)) * ((uint32_t)(multby))) - -#define RSA2048_BYTES (2048 / 8) - -/* This is the minimum/maximum key size we support, in bits */ -#define RSA_MIN_KEY_BITS 2048 -#define RSA_MAX_KEY_BITS 2048 - -/* This is the maximum signature length that we support, in bits */ -#define RSA_MAX_SIG_BITS 2048 - -static const uint8_t padding_sha1_rsa2048[RSA2048_BYTES - SHA1_SUM_LEN] = { - 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x21, 0x30, - 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a, - 0x05, 0x00, 0x04, 0x14 -}; - -/** - * subtract_modulus() - subtract modulus from the given value - * - * @key: Key containing modulus to subtract - * @num: Number to subtract modulus from, as little endian word array - */ -static void subtract_modulus(const struct rsa_public_key *key, uint32_t num[]) -{ - int64_t acc = 0; - uint i; - - for (i = 0; i < key->len; i++) { - acc += (uint64_t)num[i] - key->modulus[i]; - num[i] = (uint32_t)acc; - acc >>= 32; - } -} - -/** - * greater_equal_modulus() - check if a value is >= modulus - * - * @key: Key containing modulus to check - * @num: Number to check against modulus, as little endian word array - * @return 0 if num < modulus, 1 if num >= modulus - */ -static int greater_equal_modulus(const struct rsa_public_key *key, - uint32_t num[]) -{ - uint32_t i; - - for (i = key->len - 1; i >= 0; i--) { - if (num[i] < key->modulus[i]) - return 0; - if (num[i] > key->modulus[i]) - return 1; - } - - return 1; /* equal */ -} - -/** - * montgomery_mul_add_step() - Perform montgomery multiply-add step - * - * Operation: montgomery result[] += a * b[] / n0inv % modulus + * Verify a RSA PKCS1.5 signature against an expected hash using + * the RSA Key properties in prop structure. * - * @key: RSA key - * @result: Place to put result, as little endian word array - * @a: Multiplier - * @b: Multiplicand, as little endian word array + * @prop: Specifies key + * @sig: Signature + * @sig_len: Number of bytes in signature + * @hash: Pointer to the expected hash + * @algo: Checksum algo structure having information on RSA padding etc. + * @return 0 if verified, -ve on error */ -static void montgomery_mul_add_step(const struct rsa_public_key *key, - uint32_t result[], const uint32_t a, const uint32_t b[]) -{ - uint64_t acc_a, acc_b; - uint32_t d0; - uint i; - - acc_a = (uint64_t)a * b[0] + result[0]; - d0 = (uint32_t)acc_a * key->n0inv; - acc_b = (uint64_t)d0 * key->modulus[0] + (uint32_t)acc_a; - for (i = 1; i < key->len; i++) { - acc_a = (acc_a >> 32) + (uint64_t)a * b[i] + result[i]; - acc_b = (acc_b >> 32) + (uint64_t)d0 * key->modulus[i] + - (uint32_t)acc_a; - result[i - 1] = (uint32_t)acc_b; - } - - acc_a = (acc_a >> 32) + (acc_b >> 32); - - result[i - 1] = (uint32_t)acc_a; - - if (acc_a >> 32) - subtract_modulus(key, result); -} - -/** - * montgomery_mul() - Perform montgomery mutitply - * - * Operation: montgomery result[] = a[] * b[] / n0inv % modulus - * - * @key: RSA key - * @result: Place to put result, as little endian word array - * @a: Multiplier, as little endian word array - * @b: Multiplicand, as little endian word array - */ -static void montgomery_mul(const struct rsa_public_key *key, - uint32_t result[], uint32_t a[], const uint32_t b[]) -{ - uint i; - - for (i = 0; i < key->len; ++i) - result[i] = 0; - for (i = 0; i < key->len; ++i) - montgomery_mul_add_step(key, result, a[i], b); -} - -/** - * pow_mod() - in-place public exponentiation - * - * @key: RSA key - * @inout: Big-endian word array containing value and result - */ -static int pow_mod(const struct rsa_public_key *key, uint32_t *inout) -{ - uint32_t *result, *ptr; - uint i; - - /* Sanity check for stack size - key->len is in 32-bit words */ - if (key->len > RSA_MAX_KEY_BITS / 32) { - debug("RSA key words %u exceeds maximum %d\n", key->len, - RSA_MAX_KEY_BITS / 32); - return -EINVAL; - } - - uint32_t val[key->len], acc[key->len], tmp[key->len]; - result = tmp; /* Re-use location. */ - - /* Convert from big endian byte array to little endian word array. */ - for (i = 0, ptr = inout + key->len - 1; i < key->len; i++, ptr--) - val[i] = get_unaligned_be32(ptr); - - montgomery_mul(key, acc, val, key->rr); /* axx = a * RR / R mod M */ - for (i = 0; i < 16; i += 2) { - montgomery_mul(key, tmp, acc, acc); /* tmp = acc^2 / R mod M */ - montgomery_mul(key, acc, tmp, tmp); /* acc = tmp^2 / R mod M */ - } - montgomery_mul(key, result, acc, val); /* result = XX * a / R mod M */ - - /* Make sure result < mod; result is at most 1x mod too large. */ - if (greater_equal_modulus(key, result)) - subtract_modulus(key, result); - - /* Convert to bigendian byte array */ - for (i = key->len - 1, ptr = inout; (int)i >= 0; i--, ptr++) - put_unaligned_be32(result[i], ptr); - - return 0; -} - -static int rsa_verify_key(const struct rsa_public_key *key, const uint8_t *sig, - const uint32_t sig_len, const uint8_t *hash) +static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, + const uint32_t sig_len, const uint8_t *hash, + struct checksum_algo *algo) { const uint8_t *padding; int pad_len; int ret; +#if !defined(USE_HOSTCC) + struct udevice *mod_exp_dev; +#endif - if (!key || !sig || !hash) + if (!prop || !sig || !hash || !algo) return -EIO; - if (sig_len != (key->len * sizeof(uint32_t))) { + if (sig_len != (prop->num_bits / 8)) { debug("Signature is of incorrect length %d\n", sig_len); return -EINVAL; } + debug("Checksum algorithm: %s", algo->name); + /* Sanity check for stack size */ if (sig_len > RSA_MAX_SIG_BITS / 8) { debug("Signature length %u exceeds maximum %d\n", sig_len, @@ -230,17 +65,26 @@ static int rsa_verify_key(const struct rsa_public_key *key, const uint8_t *sig, return -EINVAL; } - uint32_t buf[sig_len / sizeof(uint32_t)]; + uint8_t buf[sig_len]; - memcpy(buf, sig, sig_len); +#if !defined(USE_HOSTCC) + ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); + if (ret) { + printf("RSA: Can't find Modular Exp implementation\n"); + return -EINVAL; + } - ret = pow_mod(key, buf); - if (ret) + ret = rsa_mod_exp(mod_exp_dev, sig, sig_len, prop, buf); +#else + ret = rsa_mod_exp_sw(sig, sig_len, prop, buf); +#endif + if (ret) { + debug("Error in Modular exponentation\n"); return ret; + } - /* Determine padding to use depending on the signature type. */ - padding = padding_sha1_rsa2048; - pad_len = RSA2048_BYTES - SHA1_SUM_LEN; + padding = algo->rsa_padding; + pad_len = algo->pad_len - algo->checksum_len; /* Check pkcs1.5 padding bytes. */ if (memcmp(buf, padding, pad_len)) { @@ -257,65 +101,57 @@ static int rsa_verify_key(const struct rsa_public_key *key, const uint8_t *sig, return 0; } -static void rsa_convert_big_endian(uint32_t *dst, const uint32_t *src, int len) -{ - int i; - - for (i = 0; i < len; i++) - dst[i] = fdt32_to_cpu(src[len - 1 - i]); -} - +/** + * rsa_verify_with_keynode() - Verify a signature against some data using + * information in node with prperties of RSA Key like modulus, exponent etc. + * + * Parse sign-node and fill a key_prop structure with properties of the + * key. Verify a RSA PKCS1.5 signature against an expected hash using + * the properties parsed + * + * @info: Specifies key and FIT information + * @hash: Pointer to the expected hash + * @sig: Signature + * @sig_len: Number of bytes in signature + * @node: Node having the RSA Key properties + * @return 0 if verified, -ve on error + */ static int rsa_verify_with_keynode(struct image_sign_info *info, - const void *hash, uint8_t *sig, uint sig_len, int node) + const void *hash, uint8_t *sig, + uint sig_len, int node) { const void *blob = info->fdt_blob; - struct rsa_public_key key; - const void *modulus, *rr; - int ret; + struct key_prop prop; + int length; + int ret = 0; if (node < 0) { debug("%s: Skipping invalid node", __func__); return -EBADF; } - if (!fdt_getprop(blob, node, "rsa,n0-inverse", NULL)) { - debug("%s: Missing rsa,n0-inverse", __func__); - return -EFAULT; - } - key.len = fdtdec_get_int(blob, node, "rsa,num-bits", 0); - key.n0inv = fdtdec_get_int(blob, node, "rsa,n0-inverse", 0); - modulus = fdt_getprop(blob, node, "rsa,modulus", NULL); - rr = fdt_getprop(blob, node, "rsa,r-squared", NULL); - if (!key.len || !modulus || !rr) { + + prop.num_bits = fdtdec_get_int(blob, node, "rsa,num-bits", 0); + + prop.n0inv = fdtdec_get_int(blob, node, "rsa,n0-inverse", 0); + + prop.public_exponent = fdt_getprop(blob, node, "rsa,exponent", &length); + if (!prop.public_exponent || length < sizeof(uint64_t)) + prop.public_exponent = NULL; + + prop.exp_len = sizeof(uint64_t); + + prop.modulus = fdt_getprop(blob, node, "rsa,modulus", NULL); + + prop.rr = fdt_getprop(blob, node, "rsa,r-squared", NULL); + + if (!prop.num_bits || !prop.modulus) { debug("%s: Missing RSA key info", __func__); return -EFAULT; } - /* Sanity check for stack size */ - if (key.len > RSA_MAX_KEY_BITS || key.len < RSA_MIN_KEY_BITS) { - debug("RSA key bits %u outside allowed range %d..%d\n", - key.len, RSA_MIN_KEY_BITS, RSA_MAX_KEY_BITS); - return -EFAULT; - } - key.len /= sizeof(uint32_t) * 8; - uint32_t key1[key.len], key2[key.len]; - - key.modulus = key1; - key.rr = key2; - rsa_convert_big_endian(key.modulus, modulus, key.len); - rsa_convert_big_endian(key.rr, rr, key.len); - if (!key.modulus || !key.rr) { - debug("%s: Out of memory", __func__); - return -ENOMEM; - } + ret = rsa_verify_key(&prop, sig, sig_len, hash, info->algo->checksum); - debug("key length %d\n", key.len); - ret = rsa_verify_key(&key, sig, sig_len, hash); - if (ret) { - printf("%s: RSA failed to verify: %d\n", __func__, ret); - return ret; - } - - return 0; + return ret; } int rsa_verify(struct image_sign_info *info, @@ -323,12 +159,23 @@ int rsa_verify(struct image_sign_info *info, uint8_t *sig, uint sig_len) { const void *blob = info->fdt_blob; - uint8_t hash[SHA1_SUM_LEN]; + /* Reserve memory for maximum checksum-length */ + uint8_t hash[info->algo->checksum->pad_len]; int ndepth, noffset; int sig_node, node; char name[100]; - sha1_context ctx; - int ret, i; + int ret; + + /* + * Verify that the checksum-length does not exceed the + * rsa-signature-length + */ + if (info->algo->checksum->checksum_len > + info->algo->checksum->pad_len) { + debug("%s: invlaid checksum-algorithm %s for %s\n", + __func__, info->algo->checksum->name, info->algo->name); + return -EINVAL; + } sig_node = fdt_subnode_offset(blob, 0, FIT_SIG_NODENAME); if (sig_node < 0) { @@ -336,10 +183,13 @@ int rsa_verify(struct image_sign_info *info, return -ENOENT; } - sha1_starts(&ctx); - for (i = 0; i < region_count; i++) - sha1_update(&ctx, region[i].data, region[i].size); - sha1_finish(&ctx, hash); + /* Calculate checksum with checksum-algorithm */ + ret = info->algo->checksum->calculate(info->algo->checksum->name, + region, region_count, hash); + if (ret < 0) { + debug("%s: Error in checksum calculation\n", __func__); + return -EINVAL; + } /* See if we must use a particular key */ if (info->required_keynode != -1) { diff --git a/lib/sha1.c b/lib/sha1.c index a121224855..05b17a259a 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -36,7 +36,7 @@ #include #endif /* USE_HOSTCC */ #include -#include "sha1.h" +#include /* * 32-bit integer manipulation macros (big endian) @@ -389,8 +389,6 @@ void sha1_hmac(const unsigned char *key, int keylen, memset (&ctx, 0, sizeof (sha1_context)); } -static const char _sha1_src[] = "_sha1_src"; - #ifdef SELF_TEST /* * FIPS-180-1 test vectors diff --git a/lib/sha256.c b/lib/sha256.c index 7348162575..bb338baefa 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -8,10 +8,12 @@ #ifndef USE_HOSTCC #include +#include +#else +#include #endif /* USE_HOSTCC */ #include -#include -#include +#include /* * 32-bit integer manipulation macros (big endian) @@ -258,14 +260,15 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen, { sha256_context ctx; #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - unsigned char *end, *curr; + const unsigned char *end; + unsigned char *curr; int chunk; #endif sha256_starts(&ctx); #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - curr = input; + curr = (unsigned char *)input; end = input + ilen; while (curr < end) { chunk = end - curr; diff --git a/lib/slre.c b/lib/slre.c index 8cdd192ea3..f90749f8ed 100644 --- a/lib/slre.c +++ b/lib/slre.c @@ -688,7 +688,7 @@ int main(int argc, char *argv[]) fprintf(stderr, "Error compiling slre: %s\n", slre.err_str); return 1; } - + slre_dump(&slre, stderr); while (fgets(data, sizeof(data), fp) != NULL) { diff --git a/lib/string.c b/lib/string.c index 3a82efab61..87c9a408e6 100644 --- a/lib/string.c +++ b/lib/string.c @@ -102,6 +102,31 @@ char * strncpy(char * dest,const char *src,size_t count) } #endif +#ifndef __HAVE_ARCH_STRLCPY +/** + * strlcpy - Copy a C-string into a sized buffer + * @dest: Where to copy the string to + * @src: Where to copy the string from + * @size: size of destination buffer + * + * Compatible with *BSD: the result is always a valid + * NUL-terminated string that fits in the buffer (unless, + * of course, the buffer size is zero). It does not pad + * out the result like strncpy() does. + */ +size_t strlcpy(char *dest, const char *src, size_t size) +{ + size_t ret = strlen(src); + + if (size) { + size_t len = (ret >= size) ? size - 1 : ret; + memcpy(dest, src, len); + dest[len] = '\0'; + } + return ret; +} +#endif + #ifndef __HAVE_ARCH_STRCAT /** * strcat - Append one %NUL-terminated string to another @@ -675,4 +700,3 @@ void *memchr_inv(const void *start, int c, size_t bytes) return check_bytes8(start, value, bytes % 8); } #endif - diff --git a/lib/strmhz.c b/lib/strmhz.c index f9a17727f5..5c16cc4fc7 100644 --- a/lib/strmhz.c +++ b/lib/strmhz.c @@ -11,11 +11,11 @@ char *strmhz (char *buf, unsigned long hz) long l, n; long m; - n = DIV_ROUND(hz, 1000) / 1000L; + n = DIV_ROUND_CLOSEST(hz, 1000) / 1000L; l = sprintf (buf, "%ld", n); hz -= n * 1000000L; - m = DIV_ROUND(hz, 1000L); + m = DIV_ROUND_CLOSEST(hz, 1000L); if (m != 0) sprintf (buf + l, ".%03ld", m); return (buf); diff --git a/lib/time.c b/lib/time.c index 68b8ff4190..477440de16 100644 --- a/lib/time.c +++ b/lib/time.c @@ -7,11 +7,91 @@ #include #include +#include +#include #ifndef CONFIG_WD_PERIOD -# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default*/ +# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default */ #endif +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SYS_TIMER_RATE +/* Returns tick rate in ticks per second */ +ulong notrace get_tbclk(void) +{ + return CONFIG_SYS_TIMER_RATE; +} +#endif + +#ifdef CONFIG_SYS_TIMER_COUNTER +unsigned long notrace timer_read_counter(void) +{ +#ifdef CONFIG_SYS_TIMER_COUNTS_DOWN + return ~readl(CONFIG_SYS_TIMER_COUNTER); +#else + return readl(CONFIG_SYS_TIMER_COUNTER); +#endif +} +#else +extern unsigned long __weak timer_read_counter(void); +#endif + +uint64_t __weak notrace get_ticks(void) +{ + unsigned long now = timer_read_counter(); + + /* increment tbu if tbl has rolled over */ + if (now < gd->timebase_l) + gd->timebase_h++; + gd->timebase_l = now; + return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l; +} + +/* Returns time in milliseconds */ +static uint64_t notrace tick_to_time(uint64_t tick) +{ + ulong div = get_tbclk(); + + tick *= CONFIG_SYS_HZ; + do_div(tick, div); + return tick; +} + +int __weak timer_init(void) +{ + return 0; +} + +/* Returns time in milliseconds */ +ulong __weak get_timer(ulong base) +{ + return tick_to_time(get_ticks()) - base; +} + +unsigned long __weak notrace timer_get_us(void) +{ + return tick_to_time(get_ticks() * 1000); +} + +static uint64_t usec_to_tick(unsigned long usec) +{ + uint64_t tick = usec; + tick *= get_tbclk(); + do_div(tick, 1000000); + return tick; +} + +void __weak __udelay(unsigned long usec) +{ + uint64_t tmp; + + tmp = get_ticks() + usec_to_tick(usec); /* get current timestamp */ + + while (get_ticks() < tmp+1) /* loop till event */ + /*NOP*/; +} + /* ------------------------------------------------------------------------- */ void udelay(unsigned long usec) diff --git a/lib/tizen/Makefile b/lib/tizen/Makefile index 80d76cfef2..e1a9cf4547 100644 --- a/lib/tizen/Makefile +++ b/lib/tizen/Makefile @@ -5,26 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libtizen.o - -SOBJS = - -COBJS-$(CONFIG_TIZEN) += tizen.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_TIZEN) += tizen.o diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c index e872591cd1..814ed18329 100644 --- a/lib/tizen/tizen.c +++ b/lib/tizen/tizen.c @@ -9,18 +9,25 @@ #include #include -#include "tizen_hd_logo.h" -#include "tizen_hd_logo_data.h" +#include "tizen_logo_16bpp.h" +#include "tizen_logo_16bpp_gzip.h" void get_tizen_logo_info(vidinfo_t *vid) { - switch (vid->resolution) { - case HD_RESOLUTION: - vid->logo_width = TIZEN_HD_LOGO_WIDTH; - vid->logo_height = TIZEN_HD_LOGO_HEIGHT; - vid->logo_addr = (ulong)tizen_hd_logo; + switch (vid->vl_bpix) { + case 4: + vid->logo_width = TIZEN_LOGO_16BPP_WIDTH; + vid->logo_height = TIZEN_LOGO_16BPP_HEIGHT; + vid->logo_x_offset = TIZEN_LOGO_16BPP_X_OFFSET; + vid->logo_y_offset = TIZEN_LOGO_16BPP_Y_OFFSET; +#if defined(CONFIG_VIDEO_BMP_GZIP) + vid->logo_addr = (ulong)tizen_logo_16bpp_gzip; +#else + vid->logo_addr = (ulong)tizen_logo_16bpp; +#endif break; default: + vid->logo_addr = 0; break; } } diff --git a/lib/tizen/tizen_hd_logo.h b/lib/tizen/tizen_hd_logo.h deleted file mode 100644 index 28377b75c9..0000000000 --- a/lib/tizen/tizen_hd_logo.h +++ /dev/null @@ -1,5057 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TIZEN_HD_LOGO_H_ -#define _TIZEN_HD_LOGO_H_ - -unsigned char tizen_hd_logo[]={ -0x1f,0x8b,0x08,0x08,0xe0,0x6f,0x8f,0x4f,0x00,0x03,0x74,0x72,0x61,0x74,0x73,0x2e, -0x62,0x6d,0x70,0x00,0xbc,0x5c,0xe9,0x53,0x1c,0x57,0x92,0xaf,0x6a,0xa0,0x81,0xa6, -0xb9,0x1b,0x04,0x48,0x02,0x04,0x7d,0xd0,0xdd,0x1c,0x12,0xba,0xd1,0x61,0x59,0x48, -0x96,0x67,0xc6,0xf6,0x8e,0x2f,0xc5,0x44,0xec,0x7c,0xd9,0x88,0x89,0x99,0xfd,0x60, -0x8f,0x23,0xc6,0x3b,0xf6,0xce,0x8c,0x67,0x6d,0x79,0xac,0x70,0x6c,0x38,0x24,0x3c, -0x06,0x74,0x41,0x83,0x0c,0x36,0x97,0x04,0x88,0xc3,0x5c,0x7d,0x09,0x79,0x3d,0x92, -0x6c,0x61,0x4b,0x8a,0x18,0xeb,0x1f,0xd9,0x3f,0x60,0x2b,0xab,0x3b,0xab,0xf3,0x65, -0xbd,0x6a,0xba,0x25,0x79,0x2b,0x78,0x51,0xd5,0x55,0xaf,0xde,0xcb,0x97,0x99,0x2f, -0x7f,0x99,0xf9,0x5e,0x71,0xfc,0xc5,0xa5,0xc9,0x1c,0x05,0x8e,0x7d,0x5a,0x69,0xd1, -0xca,0xff,0xaa,0x8a,0xf2,0x9f,0xda,0x59,0x55,0x1a,0xf5,0xfb,0x1f,0x24,0x9f,0xf3, -0x43,0xd5,0xff,0xc4,0xdf,0xc6,0x3d,0x55,0xa8,0xa4,0xea,0xbf,0x55,0xb1,0xf2,0x53, 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-0xd2,0xdd,0x64,0x9e,0x98,0xeb,0xd6,0x85,0x7c,0xcd,0x14,0x38,0xfd,0x43,0x71,0x78, -0x25,0xf8,0x96,0x01,0x8d,0xe8,0x8c,0x0a,0x3c,0x26,0xde,0xab,0x28,0x5e,0x3f,0x6c, -0xdd,0xbc,0x57,0xdf,0x3e,0xc1,0x43,0xc2,0xe3,0xe4,0xc2,0x61,0x15,0xf9,0xf1,0x5f, -0x69,0xd7,0x24,0x79,0xb6,0xa9,0x03,0x00,0x00 -}; - -#endif /* _TIZEN_HD_LOGO_H_ */ diff --git a/lib/tizen/tizen_hd_logo_data.h b/lib/tizen/tizen_hd_logo_data.h deleted file mode 100644 index 95e5f827eb..0000000000 --- a/lib/tizen/tizen_hd_logo_data.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TIZEN_HD_LOGO_DATA_H_ -#define _TIZEN_HD_LOGO_DATA_H_ - -#define TIZEN_HD_LOGO_WIDTH 520 -#define TIZEN_HD_LOGO_HEIGHT 120 -#define TIZEN_HD_LOGO_BPP 32 - -#endif /* _TIZEN_HD_LOGO_DATA_H_ */ diff --git a/lib/tizen/tizen_logo_16bpp.h b/lib/tizen/tizen_logo_16bpp.h new file mode 100644 index 0000000000..0057c11f0b --- /dev/null +++ b/lib/tizen/tizen_logo_16bpp.h @@ -0,0 +1,7935 @@ +/* + * (C) Copyright 2013 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __TIZEN_LOGO_16BPP__ +#define __TIZEN_LOGO_16BPP__ + +#define TIZEN_LOGO_16BPP_WIDTH 452 +#define TIZEN_LOGO_16BPP_HEIGHT 140 + +/* Center align offsets for word "TIZEN" */ +#define TIZEN_LOGO_16BPP_X_OFFSET (16) +#define TIZEN_LOGO_16BPP_Y_OFFSET (-20) + +/* Format: BMP RGB565 16BPP 452x140 */ +unsigned char tizen_logo_16bpp[] = { +0x42,0x4d,0xa6,0xee,0x01,0x00,0x00,0x00,0x00,0x00,0x46,0x00,0x00,0x00,0x38,0x00, +0x00,0x00,0xc4,0x01,0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x10,0x00,0x03,0x00, +0x00,0x00,0x60,0xee,0x01,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x00,0x00,0xe0,0x07,0x00,0x00,0x1f,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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+0x47,0x0a,0x91,0x1f,0xca,0x87,0xdd,0x46,0xe6,0x08,0x09,0x09,0x55,0xd6,0xc0,0xd9, +0xb4,0x14,0x2b,0xee,0xde,0xfb,0x44,0xfd,0xcd,0xf4,0xca,0xf1,0x0b,0x74,0xbc,0xe9, +0x68,0x7c,0x43,0x7d,0xfa,0xfe,0xe3,0x7b,0xa8,0x20,0x4a,0xff,0x5b,0xf1,0xc7,0xe3, +0xc9,0x81,0x29,0x94,0x1b,0x43,0x5f,0xef,0x09,0x97,0x95,0xe1,0xeb,0x1a,0x9b,0x3f, +0x3b,0x54,0xed,0x15,0x84,0x84,0x84,0xdc,0x74,0x7f,0x68,0x52,0x42,0x35,0xc4,0xdd, +0xd5,0x8d,0xe3,0xa8,0x77,0x7f,0xf6,0x28,0x6e,0x73,0x39,0x17,0xdf,0xbd,0xf7,0xf4, +0xfd,0xee,0x7f,0xd4,0x37,0xed,0xef,0xf0,0xfd,0x43,0x05,0xb5,0x4b,0xed,0xfa,0xa2, +0xaf,0xdc,0x17,0xed,0xc7,0x25,0x39,0x90,0x1c,0x90,0xfb,0x78,0x57,0x11,0x16,0x12, +0x12,0xaa,0xa4,0x77,0x63,0x7b,0xb9,0x92,0xf2,0x0f,0xf9,0x8d,0xf1,0xdd,0x71,0x3c, +0xce,0xe6,0x79,0xbd,0xa6,0x77,0x73,0xe8,0xd4,0xd6,0xbc,0x31,0x57,0x7f,0x43,0x1f, +0x65,0xf3,0xf8,0xde,0xd4,0xf2,0xeb,0x4f,0x2c,0x3f,0xb1,0xdc,0xbd,0xdc,0x2d,0x6b, +0x45,0xd5,0xca,0x0f,0x7f,0xb9,0xd9,0xc7,0x2f,0x24,0xb4,0x3f,0x74,0x72,0x31,0x2b, +0xfd,0x38,0xb5,0x32,0x0c,0xe7,0x61,0xfc,0xae,0x46,0xe2,0x81,0xb3,0xd7,0x66,0x8f, +0x2c,0xa0,0x4c,0x52,0x89,0x7c,0x5a,0x2a,0xc8,0xb1,0xcd,0xa9,0xe2,0xb7,0x96,0xff, +0xec,0x85,0xa3,0xdf,0x78,0xa9,0xeb,0xa5,0xae,0xd9,0xee,0x9f,0x1f,0xba,0xdf,0xec, +0x43,0x17,0x12,0xda,0x37,0x7a,0x6b,0xf6,0x8b,0xc5,0xe8,0x81,0x95,0xe3,0x8c,0xc3, +0xc7,0xa9,0x8f,0x2d,0x19,0x11,0x8f,0x85,0x3f,0xeb,0x79,0x63,0x30,0x3c,0xf2,0xe0, +0xf4,0xdf,0x4e,0x8c,0xff,0xc6,0x89,0x43,0x07,0x0e,0xfd,0x73,0x73,0x0e,0x56,0x48, +0x68,0x9f,0xea,0xfc,0xc4,0xe4,0x2b,0xe5,0x27,0xe6,0x87,0x77,0xc7,0xc9,0x28,0xf0, +0x47,0xc6,0xd8,0x53,0x21,0x21,0xa1,0x46,0x69,0x34,0xfe,0xff,0xfe,0x4b,0xf9,0x89, +0xa9,0x04,0xa9,0x1f,0x3e,0x72,0xf0,0x43,0x21,0x21,0xa1,0xfa,0xea,0x58,0x78,0xe2, +0xa8,0xfa,0x8d,0xe4,0xc0,0xc6,0x38,0x99,0x8f,0xf1,0x58,0xf8,0xa1,0x90,0x50,0xc3, +0xf5,0xf3,0x5f,0x57,0xbb,0x62,0xfd,0x2b,0x7a,0x1e,0xb7,0xc7,0xc2,0x0f,0x85,0x84, +0x9a,0xa2,0x37,0x9f,0x52,0xfb,0xa2,0x4f,0xcf,0x0f,0x3f,0x4a,0x61,0x12,0xbb,0x27, +0xaf,0x09,0x0e,0x85,0x84,0x1a,0xae,0x9f,0x3d,0x13,0x7b,0x7a,0x3e,0xb1,0x4b,0x38, +0x3c,0xf3,0x96,0x18,0x21,0x23,0x24,0xd4,0x04,0x1d,0xec,0x3e,0x35,0xb0,0x3b,0x4e, +0xfc,0x50,0x70,0x28,0x24,0xd4,0x1c,0xfd,0xdd,0xa1,0xdd,0xf1,0xee,0x49,0x94,0x41, +0xa3,0xfb,0xcc,0x1f,0x09,0x0e,0x85,0x84,0x9a,0xa4,0x0b,0x87,0x76,0x53,0x28,0xa3, +0x54,0xf7,0x99,0xc3,0x82,0x43,0x21,0xa1,0xa6,0xe9,0x0f,0x7f,0xe9,0xe2,0xf8,0xf0, +0x99,0xa7,0x05,0x87,0x42,0x42,0x4d,0x55,0x47,0x68,0xf6,0xe8,0xb0,0xe0,0x50,0x48, +0xa8,0xed,0xf5,0xff,0x01,0xd1,0x0a,0xff,0xc9,0xa6,0xee,0x01,0x00}; +#endif diff --git a/lib/tpm.c b/lib/tpm.c index 967c8e6515..d9789b022a 100644 --- a/lib/tpm.c +++ b/lib/tpm.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include diff --git a/lib/uuid.c b/lib/uuid.c index c48bf38362..f6b4423551 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -4,21 +4,58 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include -#include "common.h" +#include +#include +#include +#include +#include /* - * This is what a UUID string looks like. + * UUID - Universally Unique IDentifier - 128 bits unique number. + * There are 5 versions and one variant of UUID defined by RFC4122 + * specification. A UUID contains a set of fields. The set varies + * depending on the version of the UUID, as shown below: + * - time, MAC address(v1), + * - user ID(v2), + * - MD5 of name or URL(v3), + * - random data(v4), + * - SHA-1 of name or URL(v5), * - * x is a hexadecimal character. fields are separated by '-'s. When converting - * to a binary UUID, le means the field should be converted to little endian, - * and be means it should be converted to big endian. + * Layout of UUID: + * timestamp - 60-bit: time_low, time_mid, time_hi_and_version + * version - 4 bit (bit 4 through 7 of the time_hi_and_version) + * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low + * variant: - bit 6 and 7 of clock_seq_hi_and_reserved + * node - 48 bit + * + * source: https://www.ietf.org/rfc/rfc4122.txt + * + * UUID binary format (16 bytes): + * + * 4B-2B-2B-2B-6B (big endian - network byte order) + * + * UUID string is 36 length of characters (36 bytes): * * 0 9 14 19 24 * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx + * be be be be be + * + * where x is a hexadecimal character. Fields are separated by '-'s. + * When converting to a binary UUID, le means the field should be converted + * to little endian and be means it should be converted to big endian. + * + * UUID is also used as GUID (Globally Unique Identifier) with the same binary + * format but it differs in string format like below. + * + * GUID: + * 0 9 14 19 24 + * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx * le le le be be + * + * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id. */ - int uuid_str_valid(const char *uuid) { int i, valid; @@ -37,33 +74,182 @@ int uuid_str_valid(const char *uuid) } } - if (i != 36 || !valid) + if (i != UUID_STR_LEN || !valid) return 0; return 1; } -void uuid_str_to_bin(const char *uuid, unsigned char *out) +/* + * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data. + * + * @param uuid_str - pointer to UUID or GUID string [37B] + * @param uuid_bin - pointer to allocated array for big endian output [16B] + * @str_format - UUID string format: 0 - UUID; 1 - GUID + */ +int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format) { uint16_t tmp16; uint32_t tmp32; uint64_t tmp64; - if (!uuid || !out) - return; + if (!uuid_str_valid(uuid_str)) + return -EINVAL; - tmp32 = cpu_to_le32(simple_strtoul(uuid, NULL, 16)); - memcpy(out, &tmp32, 4); + if (str_format == UUID_STR_FORMAT_STD) { + tmp32 = cpu_to_be32(simple_strtoul(uuid_str, NULL, 16)); + memcpy(uuid_bin, &tmp32, 4); - tmp16 = cpu_to_le16(simple_strtoul(uuid + 9, NULL, 16)); - memcpy(out + 4, &tmp16, 2); + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 9, NULL, 16)); + memcpy(uuid_bin + 4, &tmp16, 2); - tmp16 = cpu_to_le16(simple_strtoul(uuid + 14, NULL, 16)); - memcpy(out + 6, &tmp16, 2); + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 14, NULL, 16)); + memcpy(uuid_bin + 6, &tmp16, 2); + } else { + tmp32 = cpu_to_le32(simple_strtoul(uuid_str, NULL, 16)); + memcpy(uuid_bin, &tmp32, 4); - tmp16 = cpu_to_be16(simple_strtoul(uuid + 19, NULL, 16)); - memcpy(out + 8, &tmp16, 2); + tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 9, NULL, 16)); + memcpy(uuid_bin + 4, &tmp16, 2); - tmp64 = cpu_to_be64(simple_strtoull(uuid + 24, NULL, 16)); - memcpy(out + 10, (char *)&tmp64 + 2, 6); + tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 14, NULL, 16)); + memcpy(uuid_bin + 6, &tmp16, 2); + } + + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 19, NULL, 16)); + memcpy(uuid_bin + 8, &tmp16, 2); + + tmp64 = cpu_to_be64(simple_strtoull(uuid_str + 24, NULL, 16)); + memcpy(uuid_bin + 10, (char *)&tmp64 + 2, 6); + + return 0; } + +/* + * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID. + * + * @param uuid_bin - pointer to binary data of UUID (big endian) [16B] + * @param uuid_str - pointer to allocated array for output string [37B] + * @str_format - UUID string format: 0 - UUID; 1 - GUID + */ +void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format) +{ + const u8 uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15}; + const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8, + 9, 10, 11, 12, 13, 14, 15}; + const u8 *char_order; + int i; + + /* + * UUID and GUID bin data - always in big endian: + * 4B-2B-2B-2B-6B + * be be be be be + */ + if (str_format == UUID_STR_FORMAT_STD) + char_order = uuid_char_order; + else + char_order = guid_char_order; + + for (i = 0; i < 16; i++) { + sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]); + uuid_str += 2; + switch (i) { + case 3: + case 5: + case 7: + case 9: + *uuid_str++ = '-'; + break; + } + } +} + +/* + * gen_rand_uuid() - this function generates a random binary UUID version 4. + * In this version all fields beside 4 bits of version and + * 2 bits of variant are randomly generated. + * + * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian. +*/ +#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID) +void gen_rand_uuid(unsigned char *uuid_bin) +{ + struct uuid uuid; + unsigned int *ptr = (unsigned int *)&uuid; + int i; + + /* Set all fields randomly */ + for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++) + *(ptr + i) = cpu_to_be32(rand()); + + clrsetbits_be16(&uuid.time_hi_and_version, + UUID_VERSION_MASK, + UUID_VERSION << UUID_VERSION_SHIFT); + + clrsetbits_8(&uuid.clock_seq_hi_and_reserved, + UUID_VARIANT_MASK, + UUID_VARIANT << UUID_VARIANT_SHIFT); + + memcpy(uuid_bin, &uuid, sizeof(struct uuid)); +} + +/* + * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string + * formats UUID or GUID. + * + * @param uuid_str - pointer to allocated array [37B]. + * @param - uuid output type: UUID - 0, GUID - 1 + */ +void gen_rand_uuid_str(char *uuid_str, int str_format) +{ + unsigned char uuid_bin[UUID_BIN_LEN]; + + /* Generate UUID (big endian) */ + gen_rand_uuid(uuid_bin); + + /* Convert UUID bin to UUID or GUID formated STRING */ + uuid_bin_to_str(uuid_bin, uuid_str, str_format); +} + +#ifdef CONFIG_CMD_UUID +int do_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char uuid[UUID_STR_LEN + 1]; + int str_format; + + if (!strcmp(argv[0], "uuid")) + str_format = UUID_STR_FORMAT_STD; + else + str_format = UUID_STR_FORMAT_GUID; + + if (argc > 2) + return CMD_RET_USAGE; + + gen_rand_uuid_str(uuid, str_format); + + if (argc == 1) + printf("%s\n", uuid); + else + setenv(argv[1], uuid); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(uuid, CONFIG_SYS_MAXARGS, 1, do_uuid, + "UUID - generate random Universally Unique Identifier", + "[]\n" + "Argument:\n" + "varname: for set result in a environment variable\n" + "e.g. uuid uuid_env" +); + +U_BOOT_CMD(guid, CONFIG_SYS_MAXARGS, 1, do_uuid, + "GUID - generate Globally Unique Identifier based on random UUID", + "[]\n" + "Argument:\n" + "varname: for set result in a environment variable\n" + "e.g. guid guid_env" +); +#endif /* CONFIG_CMD_UUID */ +#endif /* CONFIG_RANDOM_UUID || CONFIG_CMD_UUID */ diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 82e5c13653..e0f264850f 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -25,20 +25,6 @@ #include #define noinline __attribute__((noinline)) -/* some reluctance to put this into a new limits.h, so it is here */ -#define INT_MAX ((int)(~0U>>1)) - -static const char hex_asc[] = "0123456789abcdef"; -#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] -#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] - -static inline char *pack_hex_byte(char *buf, u8 byte) -{ - *buf++ = hex_asc_hi(byte); - *buf++ = hex_asc_lo(byte); - return buf; -} - unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base) { @@ -281,7 +267,7 @@ static char *put_dec_full(char *buf, unsigned q) return buf; } /* No inlining helps gcc to use registers better */ -static noinline char *put_dec(char *buf, u64 num) +static noinline char *put_dec(char *buf, uint64_t num) { while (1) { unsigned rem; @@ -434,6 +420,17 @@ static char *string(char *buf, char *end, char *s, int field_width, } #ifdef CONFIG_CMD_NET +static const char hex_asc[] = "0123456789abcdef"; +#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] +#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] + +static inline char *pack_hex_byte(char *buf, u8 byte) +{ + *buf++ = hex_asc_hi(byte); + *buf++ = hex_asc_lo(byte); + return buf; +} + static char *mac_address_string(char *buf, char *end, u8 *addr, int field_width, int precision, int flags) { @@ -518,6 +515,8 @@ static char *ip4_addr_string(char *buf, char *end, u8 *addr, int field_width, static char *pointer(const char *fmt, char *buf, char *end, void *ptr, int field_width, int precision, int flags) { + u64 num = (uintptr_t)ptr; + /* * Being a boot loader, we explicitly allow pointers to * (physical) address null. @@ -530,6 +529,17 @@ static char *pointer(const char *fmt, char *buf, char *end, void *ptr, #ifdef CONFIG_CMD_NET switch (*fmt) { + case 'a': + flags |= SPECIAL | ZEROPAD; + + switch (fmt[1]) { + case 'p': + default: + field_width = sizeof(phys_addr_t) * 2 + 2; + num = *(phys_addr_t *)ptr; + break; + } + break; case 'm': flags |= SPECIAL; /* Fallthrough */ @@ -555,8 +565,7 @@ static char *pointer(const char *fmt, char *buf, char *end, void *ptr, field_width = 2*sizeof(void *); flags |= ZEROPAD; } - return number(buf, end, (unsigned long)ptr, 16, field_width, - precision, flags); + return number(buf, end, num, 16, field_width, precision, flags); } static int vsnprintf_internal(char *buf, size_t size, const char *fmt, @@ -750,6 +759,7 @@ repeat: ADDCH(str, '\0'); if (str > end) end[-1] = '\0'; + --str; } #else *str = '\0'; diff --git a/lib/zlib/Makefile b/lib/zlib/Makefile index b69e2348f2..2fba95f438 100644 --- a/lib/zlib/Makefile +++ b/lib/zlib/Makefile @@ -5,24 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libz.o - -COBJS-$(CONFIG_ZLIB) += zlib.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += zlib.o diff --git a/lib/zlib/zlib.h b/lib/zlib/zlib.h index 556be32754..af3703e6d7 100644 --- a/lib/zlib/zlib.h +++ b/lib/zlib/zlib.h @@ -3,7 +3,7 @@ #define __GLUE_ZLIB_H__ #include -#include +#include #include #include #include "u-boot/zlib.h" diff --git a/mkconfig b/mkconfig deleted file mode 100755 index 816ae3d0c6..0000000000 --- a/mkconfig +++ /dev/null @@ -1,184 +0,0 @@ -#!/bin/sh -e - -# Script to create header files and links to configure -# U-Boot for a specific board. -# -# Parameters: Target Architecture CPU Board [VENDOR] [SOC] -# -# (C) 2002-2013 DENX Software Engineering, Wolfgang Denk -# -# SPDX-License-Identifier: GPL-2.0+ -# - -APPEND=no # Default: Create new config file -BOARD_NAME="" # Name to print in make output -TARGETS="" - -arch="" -cpu="" -board="" -vendor="" -soc="" -options="" - -if [ \( $# -eq 2 \) -a \( "$1" = "-A" \) ] ; then - # Automatic mode - line=`egrep -i "^[[:space:]]*${2}[[:space:]]" boards.cfg` || { - echo "make: *** No rule to make target \`$2_config'. Stop." >&2 - exit 1 - } - - set ${line} - # add default board name if needed - [ $# = 3 ] && set ${line} ${1} -fi - -while [ $# -gt 0 ] ; do - case "$1" in - --) shift ; break ;; - -a) shift ; APPEND=yes ;; - -n) shift ; BOARD_NAME="${1%_config}" ; shift ;; - -t) shift ; TARGETS="`echo $1 | sed 's:_: :g'` ${TARGETS}" ; shift ;; - *) break ;; - esac -done - -[ $# -lt 4 ] && exit 1 -[ $# -gt 7 ] && exit 1 - -# Strip all options and/or _config suffixes -CONFIG_NAME="${1%_config}" - -[ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}" - -arch="$2" -cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'` -spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'` -if [ "$4" = "-" ] ; then - board=${BOARD_NAME} -else - board="$4" -fi -[ $# -gt 4 ] && [ "$5" != "-" ] && vendor="$5" -[ $# -gt 5 ] && [ "$6" != "-" ] && soc="$6" -[ $# -gt 6 ] && [ "$7" != "-" ] && { - # check if we have a board config name in the options field - # the options field mave have a board config name and a list - # of options, both separated by a colon (':'); the options are - # separated by commas (','). - # - # Check for board name - tmp="${7%:*}" - if [ "$tmp" ] ; then - CONFIG_NAME="$tmp" - fi - # Check if we only have a colon... - if [ "${tmp}" != "$7" ] ; then - options=${7#*:} - TARGETS="`echo ${options} | sed 's:,: :g'` ${TARGETS}" - fi -} - -if [ "${ARCH}" -a "${ARCH}" != "${arch}" ]; then - echo "Failed: \$ARCH=${ARCH}, should be '${arch}' for ${BOARD_NAME}" 1>&2 - exit 1 -fi - -if [ "$options" ] ; then - echo "Configuring for ${BOARD_NAME} - Board: ${CONFIG_NAME}, Options: ${options}" -else - echo "Configuring for ${BOARD_NAME} board..." -fi - -# -# Create link to architecture specific headers -# -if [ "$SRCTREE" != "$OBJTREE" ] ; then - mkdir -p ${OBJTREE}/include - mkdir -p ${OBJTREE}/include2 - cd ${OBJTREE}/include2 - rm -f asm - ln -s ${SRCTREE}/arch/${arch}/include/asm asm - LNPREFIX=${SRCTREE}/arch/${arch}/include/asm/ - cd ../include - mkdir -p asm -else - cd ./include - rm -f asm - ln -s ../arch/${arch}/include/asm asm -fi - -rm -f asm/arch - -if [ -z "${soc}" ] ; then - ln -s ${LNPREFIX}arch-${cpu} asm/arch -else - ln -s ${LNPREFIX}arch-${soc} asm/arch -fi - -if [ "${arch}" = "arm" ] ; then - rm -f asm/proc - ln -s ${LNPREFIX}proc-armv asm/proc -fi - -# -# Create include file for Make -# -( echo "ARCH = ${arch}" - if [ ! -z "$spl_cpu" ] ; then - echo 'ifeq ($(CONFIG_SPL_BUILD),y)' - echo "CPU = ${spl_cpu}" - echo "else" - echo "CPU = ${cpu}" - echo "endif" - else - echo "CPU = ${cpu}" - fi - echo "BOARD = ${board}" - - [ "${vendor}" ] && echo "VENDOR = ${vendor}" - [ "${soc}" ] && echo "SOC = ${soc}" - exit 0 ) > config.mk - -# Assign board directory to BOARDIR variable -if [ -z "${vendor}" ] ; then - BOARDDIR=${board} -else - BOARDDIR=${vendor}/${board} -fi - -# -# Create board specific header file -# -if [ "$APPEND" = "yes" ] # Append to existing config file -then - echo >> config.h -else - > config.h # Create new config file -fi -echo "/* Automatically generated - do not edit */" >>config.h - -for i in ${TARGETS} ; do - i="`echo ${i} | sed '/=/ {s/=/ /;q; } ; { s/$/ 1/; }'`" - echo "#define CONFIG_${i}" >>config.h ; -done - -echo "#define CONFIG_SYS_ARCH \"${arch}\"" >> config.h -echo "#define CONFIG_SYS_CPU \"${cpu}\"" >> config.h -echo "#define CONFIG_SYS_BOARD \"${board}\"" >> config.h - -[ "${vendor}" ] && echo "#define CONFIG_SYS_VENDOR \"${vendor}\"" >> config.h - -[ "${soc}" ] && echo "#define CONFIG_SYS_SOC \"${soc}\"" >> config.h - -cat << EOF >> config.h -#define CONFIG_BOARDDIR board/$BOARDDIR -#include -#include -#include -#include -#include -#include -EOF - -exit 0 diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile deleted file mode 100644 index 20459c92e2..0000000000 --- a/nand_spl/board/amcc/acadia/Makefile +++ /dev/null @@ -1,106 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o cache.o -COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ - $(nandobj)System.map - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)System.map: $(nandobj)u-boot-spl - @$(NM) $< | \ - grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ - sort > $(nandobj)System.map - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)cache.S: - @rm -f $(obj)cache.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S - -$(obj)gpio.c: - @rm -f $(obj)gpio.c - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $(obj)gpio.c - -$(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S - -$(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S - -# from board directory -$(obj)memory.c: - @rm -f $(obj)memory.c - ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c - -$(obj)pll.c: - @rm -f $(obj)pll.c - ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk deleted file mode 100644 index d9ff10d5c2..0000000000 --- a/nand_spl/board/amcc/acadia/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 405EZ Reference Platform (Acadia) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xf8004000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0xf8008000 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds deleted file mode 100644 index a7dac121d3..0000000000 --- a/nand_spl/board/amcc/acadia/u-boot.lds +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0xf8004ffc : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - nand_boot.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile deleted file mode 100644 index ca3dab4f25..0000000000 --- a/nand_spl/board/amcc/bamboo/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o init.o resetvec.o -COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S - -$(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S - -# from board directory -$(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)sdram.c: - @rm -f $(obj)sdram.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/bamboo/config.mk b/nand_spl/board/amcc/bamboo/config.mk deleted file mode 100644 index 6cc8fa30f3..0000000000 --- a/nand_spl/board/amcc/bamboo/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EP Reference Platform (Bamboo) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into instruction-cache in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in i-cache here. -# -CONFIG_SYS_TEXT_BASE = 0x00800000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0x00804000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c deleted file mode 100644 index df0dfc1a0d..0000000000 --- a/nand_spl/board/amcc/bamboo/sdram.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void wait_init_complete(void) -{ - u32 val; - - do { - mfsdram(SDRAM0_MCSTS, val); - } while (!(val & 0x80000000)); -} - -/* - * phys_size_t initdram(int board_type) - * - * As the name already indicates, this function is called very early - * from start.S and configures the SDRAM with fixed values. This is needed, - * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has - * not enough free space to implement the complete I2C SPD DDR autodetection - * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM - * when booting from NAND flash. - * - * Note: - * As found out by Eugene O'Brien , the fixed - * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM - * modules are still plugged in. So it is recommended to remove the DIMM - * modules while using the NAND booting code with the fixed SDRAM setup! - */ -phys_size_t initdram(int board_type) -{ - /* - * Soft-reset SDRAM controller. - */ - mtsdr(SDR0_SRST, SDR0_SRST_DMC); - mtsdr(SDR0_SRST, 0x00000000); - - /* - * Disable memory controller. - */ - mtsdram(SDRAM0_CFG0, 0x00000000); - - /* - * Setup some default - */ - mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram(SDRAM0_B0CR, 0x00082001); - mtsdram(SDRAM0_TR0, 0x41094012); - mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ - mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ - mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/ - - /* - * Enable the controller, then wait for DCEN to complete - */ - mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/ - wait_init_complete(); - - return CONFIG_SYS_MBYTES_SDRAM << 20; -} diff --git a/nand_spl/board/amcc/bamboo/u-boot.lds b/nand_spl/board/amcc/bamboo/u-boot.lds deleted file mode 100644 index c432368175..0000000000 --- a/nand_spl/board/amcc/bamboo/u-boot.lds +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0x00800FFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - init.o (.text) - nand_boot.o (.text) - sdram.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile deleted file mode 100644 index f50d84b8c9..0000000000 --- a/nand_spl/board/amcc/canyonlands/Makefile +++ /dev/null @@ -1,99 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS := start.o -SOBJS += init.o -SOBJS += resetvec.o -COBJS := ddr2_fixed.o -COBJS += nand_boot.o -COBJS += nand_ecc.o -COBJS += ndfc.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S - -$(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S - -# from board directory -$(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $(obj)init.S - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)ddr2_fixed.c: - @rm -f $(obj)ddr2_fixed.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $(obj)ddr2_fixed.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/canyonlands/config.mk b/nand_spl/board/amcc/canyonlands/config.mk deleted file mode 100644 index 780b7ae375..0000000000 --- a/nand_spl/board/amcc/canyonlands/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 460EX Reference Platform (Canyonlands) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xE3003000 - -# PAD_TO used to generate a 128kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000 -PAD_TO = 0xE3023000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c deleted file mode 100644 index ce8515d513..0000000000 --- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * This code can configure those two Crucial SODIMM's: - * - * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) - * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank) - * - */ - -#define TEST_ADDR 0x10000000 -#define TEST_MAGIC 0x11223344 - -static void wait_init_complete(void) -{ - u32 val; - - do { - mfsdram(SDRAM_MCSTAT, val); - } while (!(val & 0x80000000)); -} - -static void ddr_start(void) -{ - mtsdram(SDRAM_MCOPT2, 0x28000000); - wait_init_complete(); -} - -static void ddr_init_common(void) -{ - /* - * Reset the DDR-SDRAM controller. - */ - mtsdr(SDR0_SRST, SDR0_SRST0_DMC); - mtsdr(SDR0_SRST, 0x00000000); - - /* - * These values are cloned from a running NOR booting - * Canyonlands with SPD-DDR2 detection and calibration - * enabled. This will only work for the same memory - * configuration as used here: - * - */ - mtsdram(SDRAM_MCOPT2, 0x00000000); - mtsdram(SDRAM_MODT0, 0x01000000); - mtsdram(SDRAM_WRDTR, 0x82000823); - mtsdram(SDRAM_CLKTR, 0x40000000); - mtsdram(SDRAM_MB0CF, 0x00000201); - mtsdram(SDRAM_RTR, 0x06180000); - mtsdram(SDRAM_SDTR1, 0x80201000); - mtsdram(SDRAM_SDTR2, 0x42103243); - mtsdram(SDRAM_SDTR3, 0x0A0D0D16); - mtsdram(SDRAM_MMODE, 0x00000632); - mtsdram(SDRAM_MEMODE, 0x00000040); - mtsdram(SDRAM_INITPLR0, 0xB5380000); - mtsdram(SDRAM_INITPLR1, 0x82100400); - mtsdram(SDRAM_INITPLR2, 0x80820000); - mtsdram(SDRAM_INITPLR3, 0x80830000); - mtsdram(SDRAM_INITPLR4, 0x80810040); - mtsdram(SDRAM_INITPLR5, 0x80800532); - mtsdram(SDRAM_INITPLR6, 0x82100400); - mtsdram(SDRAM_INITPLR7, 0x8A080000); - mtsdram(SDRAM_INITPLR8, 0x8A080000); - mtsdram(SDRAM_INITPLR9, 0x8A080000); - mtsdram(SDRAM_INITPLR10, 0x8A080000); - mtsdram(SDRAM_INITPLR11, 0x80000432); - mtsdram(SDRAM_INITPLR12, 0x808103C0); - mtsdram(SDRAM_INITPLR13, 0x80810040); - mtsdram(SDRAM_RDCC, 0x40000000); - mtsdram(SDRAM_RQDC, 0x80000038); - mtsdram(SDRAM_RFDC, 0x00000257); - - mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ -} - -phys_size_t initdram(int board_type) -{ - /* - * First try init for this module: - * - * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank) - */ - - ddr_init_common(); - - /* - * Crucial CT6464AC667.8FB - 512MB SO-DIMM - */ - mtdcr(SDRAM_R0BAS, 0x0000F800); - mtdcr(SDRAM_R1BAS, 0x0400F800); - mtsdram(SDRAM_MCOPT1, 0x05122000); - mtsdram(SDRAM_CODT, 0x02800021); - mtsdram(SDRAM_MB1CF, 0x00000201); - - ddr_start(); - - /* - * Now test if the dual-ranked module is really installed - * by checking an address in the upper 256MByte region - */ - out_be32((void *)TEST_ADDR, TEST_MAGIC); - if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) { - /* - * The test failed, so we assume that the single - * ranked module is installed: - * - * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) - */ - - ddr_init_common(); - - mtdcr(SDRAM_R0BAS, 0x0000F000); - mtsdram(SDRAM_MCOPT1, 0x05322000); - mtsdram(SDRAM_CODT, 0x00800021); - - ddr_start(); - } - - return CONFIG_SYS_MBYTES_SDRAM << 20; -} diff --git a/nand_spl/board/amcc/canyonlands/u-boot.lds b/nand_spl/board/amcc/canyonlands/u-boot.lds deleted file mode 100644 index 6383b1a38f..0000000000 --- a/nand_spl/board/amcc/canyonlands/u-boot.lds +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0xE3003FFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - init.o (.text) - nand_boot.o (.text) - ddr2_fixed.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile deleted file mode 100644 index 8b4206f57b..0000000000 --- a/nand_spl/board/amcc/kilauea/Makefile +++ /dev/null @@ -1,95 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o cache.o -COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)44x_spd_ddr2.c: $(obj)ecc.h - @rm -f $(obj)44x_spd_ddr2.c - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c - -$(obj)cache.S: - @rm -f $(obj)cache.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S - -$(obj)ecc.h: - @rm -f $(obj)ecc.h - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $(obj)ecc.h - -$(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S - -$(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c - -# from drivers/nand directory -$(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk deleted file mode 100644 index b596b1406c..0000000000 --- a/nand_spl/board/amcc/kilauea/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 405EX Reference Platform (Kilauea) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into SDRAM since we can't access the NAND -# controller at CS0 while running from this location. So we set -# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here. -# -CONFIG_SYS_TEXT_BASE = 0x00800000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0x00804000 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds deleted file mode 100644 index d7262e6c53..0000000000 --- a/nand_spl/board/amcc/kilauea/u-boot.lds +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0x00800FFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - nand_boot.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile deleted file mode 100644 index 0fcf030d43..0000000000 --- a/nand_spl/board/amcc/sequoia/Makefile +++ /dev/null @@ -1,98 +0,0 @@ -# -# (C) Copyright 2006-2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o init.o resetvec.o -COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)denali_data_eye.c: - @rm -f $(obj)denali_data_eye.c - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c - -$(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S - -$(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S - -# from board directory -$(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S - -$(obj)sdram.c: - @rm -f $(obj)sdram.c - @rm -f $(obj)sdram.h - ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c - ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/amcc/sequoia/config.mk b/nand_spl/board/amcc/sequoia/config.mk deleted file mode 100644 index ede7964d9f..0000000000 --- a/nand_spl/board/amcc/sequoia/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EPx Reference Platform (Sequoia) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xE0013000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0xE0017000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/nand_spl/board/amcc/sequoia/u-boot.lds b/nand_spl/board/amcc/sequoia/u-boot.lds deleted file mode 100644 index 45c0162af6..0000000000 --- a/nand_spl/board/amcc/sequoia/u-boot.lds +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2006-2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - .resetvec 0xE0013FFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - .text : - { - start.o (.text) - init.o (.text) - nand_boot.o (.text) - sdram.o (.text) - ndfc.o (.text) - - *(.text) - *(.fixup) - } - _etext = .; - - .data : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.data*) - *(.sdata*) - __got2_start = .; - *(.got2) - __got2_end = .; - } - - _edata = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) - *(.bss) - . = ALIGN(4); - } - - __bss_end = . ; -} diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile deleted file mode 100644 index 5b11d1067e..0000000000 --- a/nand_spl/board/freescale/mpc8315erdb/Makefile +++ /dev/null @@ -1,92 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# (C) Copyright 2008 Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -NAND_SPL := y -PAD_TO := 0xfff04000 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ - $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ - time.o cache.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -$(obj)start.S: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $(obj)start.S - -$(obj)nand_boot_fsl_elbc.c: - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c - -$(obj)sdram.c: - ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $(obj)sdram.c - -$(obj)$(BOARD).c: - ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $(obj)$(BOARD).c - -$(obj)ns16550.c: - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c - -$(obj)spl_minimal.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c - -$(obj)cache.c: - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c - -$(obj)time.c: - ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c - -$(obj)ticks.S: - ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/freescale/mpc8315erdb/u-boot.lds b/nand_spl/board/freescale/mpc8315erdb/u-boot.lds deleted file mode 100644 index 774772beaf..0000000000 --- a/nand_spl/board/freescale/mpc8315erdb/u-boot.lds +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - . = 0xfff00000; - .text : { - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - . = ALIGN(8); - .data : { - *(.data*) - *(.sdata*) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - - . = ALIGN(8); - __bss_start = .; - .bss (NOLOAD) : { - *(.*bss) - } - __bss_end = .; -} -ENTRY(_start) -ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big"); diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile deleted file mode 100644 index d3dac2074c..0000000000 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# Copyright 2009-2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -NAND_SPL := y -CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 -PAD_TO := 0xfff01000 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ - $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -# create symbolic links for common files - -$(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c - -$(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c - -$(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c - -$(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c - -$(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c - -$(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c - -$(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S - -$(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S - -$(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S - -$(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c - -$(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/freescale/mpc8536ds/nand_boot.c b/nand_spl/board/freescale/mpc8536ds/nand_boot.c deleted file mode 100644 index 71178e4b9c..0000000000 --- a/nand_spl/board/freescale/mpc8536ds/nand_boot.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -u32 sysclk_tbl[] = { - 33333000, 39999600, 49999500, 66666000, - 83332500, 99999000, 133332000, 166665000 -}; - -void board_init_f(ulong bootflag) -{ - int px_spd; - u32 plat_ratio, bus_clk, sys_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - /* for FPGA */ - set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); - set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); -#else -#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined -#endif - - /* initialize selected port with appropriate baud rate */ - px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); - sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK]; - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - bus_clk = sys_clk * plat_ratio / 2; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile deleted file mode 100644 index d3dac2074c..0000000000 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# Copyright 2009-2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -NAND_SPL := y -CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 -PAD_TO := 0xfff01000 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ - $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -# create symbolic links for common files - -$(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c - -$(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c - -$(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c - -$(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c - -$(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c - -$(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c - -$(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S - -$(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S - -$(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S - -$(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c - -$(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c deleted file mode 100644 index 716b737ad2..0000000000 --- a/nand_spl/board/freescale/mpc8569mds/nand_boot.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SYSCLK_66 66666666 - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - uint plat_ratio, bus_clk, sys_clk; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - sys_clk = SYSCLK_66; - - plat_ratio = gur->porpllsr & 0x0000003e; - plat_ratio >>= 1; - bus_clk = plat_ratio * sys_clk; - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to DDR and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile deleted file mode 100644 index d3dac2074c..0000000000 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# Copyright 2009-2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -NAND_SPL := y -CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 -PAD_TO := 0xfff01000 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ - $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -# create symbolic links for common files - -$(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c - -$(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c - -$(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c - -$(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c - -$(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c - -$(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c - -$(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S - -$(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S - -$(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S - -$(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c - -$(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/freescale/mpc8572ds/nand_boot.c b/nand_spl/board/freescale/mpc8572ds/nand_boot.c deleted file mode 100644 index 3bc0927341..0000000000 --- a/nand_spl/board/freescale/mpc8572ds/nand_boot.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -u32 sysclk_tbl[] = { - 33333000, 39999600, 49999500, 66666000, - 83332500, 99999000, 133332000, 166665000 -}; - -void board_init_f(ulong bootflag) -{ - int px_spd; - u32 plat_ratio, bus_clk, sys_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - /* for FPGA */ - set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); - set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); -#else -#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined -#endif - - /* initialize selected port with appropriate baud rate */ - px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); - sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - bus_clk = sys_clk * plat_ratio / 2; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile deleted file mode 100644 index e89d4054ab..0000000000 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ /dev/null @@ -1,117 +0,0 @@ -# -# Copyright 2010-2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# -NAND_SPL := y -PAD_TO := 0xfff01000 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ - $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -# create symbolic links for common files - -$(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c - -$(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c - -$(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c - -$(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c - -$(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c - -$(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c - -$(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S - -$(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S - -$(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S - -$(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c - -$(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c deleted file mode 100644 index 94680004f7..0000000000 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Author: Roy Zang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* Fixed sdram init -- doesn't use serial presence detect. */ -void sdram_init(void) -{ - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); - __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl); - __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1); - __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2); - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); - - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile deleted file mode 100644 index d3dac2074c..0000000000 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# Copyright 2009-2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -NAND_SPL := y -CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 -PAD_TO := 0xfff01000 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ - $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -# create symbolic links for common files - -$(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c - -$(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c - -$(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c - -$(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c - -$(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c - -$(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c - -$(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S - -$(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S - -$(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S - -$(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c - -$(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c deleted file mode 100644 index 3244c8f6d9..0000000000 --- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SYSCLK_MASK 0x00200000 -#define BOARDREV_MASK 0x10100000 -#define BOARDREV_B 0x10100000 -#define BOARDREV_C 0x00100000 - -#define SYSCLK_66 66666666 -#define SYSCLK_50 50000000 -#define SYSCLK_100 100000000 - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - uint plat_ratio, bus_clk, sys_clk = 0; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - uint val, temp, sysclk_mask; - - val = pgpio->gpdat; - sysclk_mask = val & SYSCLK_MASK; - temp = val & BOARDREV_MASK; - if (temp == BOARDREV_C) { - if(sysclk_mask == 0) - sys_clk = SYSCLK_66; - else - sys_clk = SYSCLK_100; - } else if (temp == BOARDREV_B) { - if(sysclk_mask == 0) - sys_clk = SYSCLK_66; - else - sys_clk = SYSCLK_50; - } - - plat_ratio = gur->porpllsr & 0x0000003e; - plat_ratio >>= 1; - bus_clk = plat_ratio * sys_clk; - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to DDR and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile deleted file mode 100644 index 08739edc4e..0000000000 --- a/nand_spl/board/sheldon/simpc8313/Makefile +++ /dev/null @@ -1,100 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# (C) Copyright 2008 Freescale Semiconductor -# (C) Copyright Sheldon Instruments, Inc. 2008 -# -# SPDX-License-Identifier: GPL-2.0+ -# - -NAND_SPL := y - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ - $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ - time.o cache.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -$(obj)start.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@ - -$(obj)nand_boot_fsl_elbc.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ - -$(obj)sdram.c: - @rm -f $@ - ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@ - -$(obj)$(BOARD).c: - @rm -f $@ - ln -s $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@ - -$(obj)ns16550.c: - @rm -f $@ - ln -s $(SRCTREE)/drivers/serial/ns16550.c $@ - -$(obj)spl_minimal.c: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@ - -$(obj)cache.c: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/lib/cache.c $@ - -$(obj)time.c: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/lib/time.c $@ - -$(obj)ticks.S: - @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/lib/ticks.S $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/sheldon/simpc8313/u-boot.lds b/nand_spl/board/sheldon/simpc8313/u-boot.lds deleted file mode 100644 index 4e4d511f9b..0000000000 --- a/nand_spl/board/sheldon/simpc8313/u-boot.lds +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - . = 0xfff00000; - .text : { - *(.text*) - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - . = ALIGN(8); - .data : { - *(.data*) - *(.sdata*) - _GOT2_TABLE_ = .; - *(.got2) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - - . = ALIGN(8); - __bss_start = .; - .bss (NOLOAD) : { *(.*bss) } - __bss_end = .; -} -ENTRY(_start) -ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big"); diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c deleted file mode 100644 index 125e7f3714..0000000000 --- a/nand_spl/nand_boot.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; - -#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) - - -#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512) -/* - * NAND command for small page NAND devices (512) - */ -static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) -{ - struct nand_chip *this = mtd->priv; - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; - - while (!this->dev_ready(mtd)) - ; - - /* Begin command latch cycle */ - this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - /* Set ALE and clear CLE to start address cycle */ - /* Column address */ - this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE); - this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */ - this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, - NAND_CTRL_ALE); /* A[24:17] */ -#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE - /* One more address cycle for devices > 32MiB */ - this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, - NAND_CTRL_ALE); /* A[28:25] */ -#endif - /* Latch in address */ - this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - - /* - * Wait a while for the data to be ready - */ - while (!this->dev_ready(mtd)) - ; - - return 0; -} -#else -/* - * NAND command for large page NAND devices (2k) - */ -static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) -{ - struct nand_chip *this = mtd->priv; - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; - void (*hwctrl)(struct mtd_info *mtd, int cmd, - unsigned int ctrl) = this->cmd_ctrl; - - while (!this->dev_ready(mtd)) - ; - - /* Emulate NAND_CMD_READOOB */ - if (cmd == NAND_CMD_READOOB) { - offs += CONFIG_SYS_NAND_PAGE_SIZE; - cmd = NAND_CMD_READ0; - } - - /* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) - offs >>= 1; - - /* Begin command latch cycle */ - hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - /* Set ALE and clear CLE to start address cycle */ - /* Column address */ - hwctrl(mtd, offs & 0xff, - NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ - hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ - /* Row address */ - hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ - hwctrl(mtd, ((page_addr >> 8) & 0xff), - NAND_CTRL_ALE); /* A[27:20] */ -#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE - /* One more address cycle for devices > 128MiB */ - hwctrl(mtd, (page_addr >> 16) & 0x0f, - NAND_CTRL_ALE); /* A[31:28] */ -#endif - /* Latch in address */ - hwctrl(mtd, NAND_CMD_READSTART, - NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - - /* - * Wait a while for the data to be ready - */ - while (!this->dev_ready(mtd)) - ; - - return 0; -} -#endif - -static int nand_is_bad_block(struct mtd_info *mtd, int block) -{ - struct nand_chip *this = mtd->priv; - - nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); - - /* - * Read one byte (or two if it's a 16 bit chip). - */ - if (this->options & NAND_BUSWIDTH_16) { - if (readw(this->IO_ADDR_R) != 0xffff) - return 1; - } else { - if (readb(this->IO_ADDR_R) != 0xff) - return 1; - } - - return 0; -} - -#if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) -static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) -{ - struct nand_chip *this = mtd->priv; - u_char ecc_calc[ECCTOTAL]; - u_char ecc_code[ECCTOTAL]; - u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; - int i; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; - int eccsteps = ECCSTEPS; - uint8_t *p = dst; - - nand_command(mtd, block, page, 0, NAND_CMD_READOOB); - this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); - nand_command(mtd, block, page, 0, NAND_CMD_READ0); - - /* Pick the ECC bytes out of the oob data */ - for (i = 0; i < ECCTOTAL; i++) - ecc_code[i] = oob_data[nand_ecc_pos[i]]; - - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(mtd, NAND_ECC_READ); - this->read_buf(mtd, p, eccsize); - this->ecc.calculate(mtd, p, &ecc_calc[i]); - this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); - } - - return 0; -} -#else -static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) -{ - struct nand_chip *this = mtd->priv; - u_char ecc_calc[ECCTOTAL]; - u_char ecc_code[ECCTOTAL]; - u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; - int i; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; - int eccsteps = ECCSTEPS; - uint8_t *p = dst; - - nand_command(mtd, block, page, 0, NAND_CMD_READ0); - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(mtd, NAND_ECC_READ); - this->read_buf(mtd, p, eccsize); - this->ecc.calculate(mtd, p, &ecc_calc[i]); - } - this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); - - /* Pick the ECC bytes out of the oob data */ - for (i = 0; i < ECCTOTAL; i++) - ecc_code[i] = oob_data[nand_ecc_pos[i]]; - - eccsteps = ECCSTEPS; - p = dst; - - for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - /* No chance to do something with the possible error message - * from correct_data(). We just hope that all possible errors - * are corrected by this routine. - */ - this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); - } - - return 0; -} -#endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */ - -static int nand_load(struct mtd_info *mtd, unsigned int offs, - unsigned int uboot_size, uchar *dst) -{ - unsigned int block, lastblock; - unsigned int page; - - /* - * offs has to be aligned to a page address! - */ - block = offs / CONFIG_SYS_NAND_BLOCK_SIZE; - lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; - page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE; - - while (block <= lastblock) { - if (!nand_is_bad_block(mtd, block)) { - /* - * Skip bad blocks - */ - while (page < CONFIG_SYS_NAND_PAGE_COUNT) { - nand_read_page(mtd, block, page, dst); - dst += CONFIG_SYS_NAND_PAGE_SIZE; - page++; - } - - page = 0; - } else { - lastblock++; - } - - block++; - } - - return 0; -} - -/* - * The main entry for NAND booting. It's necessary that SDRAM is already - * configured and available since this code loads the main U-Boot image - * from NAND into SDRAM and starts it from there. - */ -void nand_boot(void) -{ - struct nand_chip nand_chip; - nand_info_t nand_info; - __attribute__((noreturn)) void (*uboot)(void); - - /* - * Init board specific nand support - */ - nand_chip.select_chip = NULL; - nand_info.priv = &nand_chip; - nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; - nand_chip.dev_ready = NULL; /* preset to NULL */ - nand_chip.options = 0; - board_nand_init(&nand_chip); - - if (nand_chip.select_chip) - nand_chip.select_chip(&nand_info, 0); - - /* - * Load U-Boot image from NAND into RAM - */ - nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); - -#ifdef CONFIG_NAND_ENV_DST - nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST); - -#ifdef CONFIG_ENV_OFFSET_REDUND - nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); -#endif -#endif - - if (nand_chip.select_chip) - nand_chip.select_chip(&nand_info, -1); - - /* - * Jump to U-Boot image - */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; - (*uboot)(); -} diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c deleted file mode 100644 index 03e25f37ea..0000000000 --- a/nand_spl/nand_boot_fsl_elbc.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine - * - * (C) Copyright 2006-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (c) 2008 Freescale Semiconductor, Inc. - * Author: Scott Wood - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define WINDOW_SIZE 8192 - -static void nand_wait(void) -{ - fsl_lbc_t *regs = LBC_BASE_ADDR; - - for (;;) { - uint32_t status = in_be32(®s->ltesr); - - if (status == 1) - return; - - if (status & 1) { - puts("read failed (ltesr)\n"); - for (;;); - } - } -} - -static void nand_load(unsigned int offs, int uboot_size, uchar *dst) -{ - fsl_lbc_t *regs = LBC_BASE_ADDR; - uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; - const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS; - const int block_shift = large ? 17 : 14; - const int block_size = 1 << block_shift; - const int page_size = large ? 2048 : 512; - const int bad_marker = large ? page_size + 0 : page_size + 5; - int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2; - int pos = 0; - - if (offs & (block_size - 1)) { - puts("bad offset\n"); - for (;;); - } - - if (large) { - fmr |= FMR_ECCM; - __raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) | - (NAND_CMD_READSTART << FCR_CMD1_SHIFT), - ®s->fcr); - __raw_writel( - (FIR_OP_CW0 << FIR_OP0_SHIFT) | - (FIR_OP_CA << FIR_OP1_SHIFT) | - (FIR_OP_PA << FIR_OP2_SHIFT) | - (FIR_OP_CW1 << FIR_OP3_SHIFT) | - (FIR_OP_RBW << FIR_OP4_SHIFT), - ®s->fir); - } else { - __raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, ®s->fcr); - __raw_writel( - (FIR_OP_CW0 << FIR_OP0_SHIFT) | - (FIR_OP_CA << FIR_OP1_SHIFT) | - (FIR_OP_PA << FIR_OP2_SHIFT) | - (FIR_OP_RBW << FIR_OP3_SHIFT), - ®s->fir); - } - - __raw_writel(0, ®s->fbcr); - - while (pos < uboot_size) { - int i = 0; - __raw_writel(offs >> block_shift, ®s->fbar); - - do { - int j; - unsigned int page_offs = (offs & (block_size - 1)) << 1; - - __raw_writel(~0, ®s->ltesr); - __raw_writel(0, ®s->lteatr); - __raw_writel(page_offs, ®s->fpar); - __raw_writel(fmr, ®s->fmr); - sync(); - __raw_writel(0, ®s->lsor); - nand_wait(); - - page_offs %= WINDOW_SIZE; - - /* - * If either of the first two pages are marked bad, - * continue to the next block. - */ - if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) { - puts("skipping\n"); - offs = (offs + block_size) & ~(block_size - 1); - pos &= ~(block_size - 1); - break; - } - - for (j = 0; j < page_size; j++) - dst[pos + j] = buf[page_offs + j]; - - pos += page_size; - offs += page_size; - } while ((offs & (block_size - 1)) && (pos < uboot_size)); - } -} - -/* - * The main entry for NAND booting. It's necessary that SDRAM is already - * configured and available since this code loads the main U-Boot image - * from NAND into SDRAM and starts it from there. - */ -void nand_boot(void) -{ - __attribute__((noreturn)) void (*uboot)(void); - - /* - * Load U-Boot image from NAND into RAM - */ - nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); - - /* - * Jump to U-Boot image - */ - puts("transfering control\n"); - /* - * Clean d-cache and invalidate i-cache, to - * make sure that no stale data is executed. - */ - flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; - uboot(); -} diff --git a/net/Kconfig b/net/Kconfig new file mode 100644 index 0000000000..22b9eaac53 --- /dev/null +++ b/net/Kconfig @@ -0,0 +1,10 @@ +# +# Network configuration +# + +menuconfig NET + bool "Networking support" + +if NET + +endif # if NET diff --git a/net/Makefile b/net/Makefile index 13917d0713..6ba8f7575e 100644 --- a/net/Makefile +++ b/net/Makefile @@ -5,40 +5,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -# CFLAGS += -DDEBUG - -LIB = $(obj)libnet.o - -COBJS-$(CONFIG_CMD_BOOTCE) += bootme.o -COBJS-$(CONFIG_CMD_NET) += arp.o -COBJS-$(CONFIG_CMD_NET) += bootp.o -COBJS-$(CONFIG_CMD_CDP) += cdp.o -COBJS-$(CONFIG_CMD_DNS) += dns.o -COBJS-$(CONFIG_CMD_NET) += eth.o -COBJS-$(CONFIG_CMD_LINK_LOCAL) += link_local.o -COBJS-$(CONFIG_CMD_NET) += net.o -COBJS-$(CONFIG_CMD_NFS) += nfs.o -COBJS-$(CONFIG_CMD_PING) += ping.o -COBJS-$(CONFIG_CMD_RARP) += rarp.o -COBJS-$(CONFIG_CMD_SNTP) += sntp.o -COBJS-$(CONFIG_CMD_NET) += tftp.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +#ccflags-y += -DDEBUG + +obj-y += checksum.o +obj-$(CONFIG_CMD_NET) += arp.o +obj-$(CONFIG_CMD_BOOTCE) += bootme.o +obj-$(CONFIG_CMD_NET) += bootp.o +obj-$(CONFIG_CMD_CDP) += cdp.o +obj-$(CONFIG_CMD_DNS) += dns.o +obj-$(CONFIG_CMD_NET) += eth.o +obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o +obj-$(CONFIG_CMD_NET) += net.o +obj-$(CONFIG_CMD_NFS) += nfs.o +obj-$(CONFIG_CMD_PING) += ping.o +obj-$(CONFIG_CMD_RARP) += rarp.o +obj-$(CONFIG_CMD_SNTP) += sntp.o +obj-$(CONFIG_CMD_NET) += tftp.o diff --git a/net/arp.c b/net/arp.c index 20c6b2d42a..21ed31bf74 100644 --- a/net/arp.c +++ b/net/arp.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include diff --git a/net/arp.h b/net/arp.h index bfd57e0105..3a0a13a372 100644 --- a/net/arp.h +++ b/net/arp.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ARP_H__ diff --git a/net/bootp.c b/net/bootp.c index 386e89b9d8..5e835a31ad 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -23,12 +23,22 @@ #define BOOTP_VENDOR_MAGIC 0x63825363 /* RFC1048 Magic Cookie */ -#define TIMEOUT 5000UL /* Milliseconds before trying BOOTP again */ +/* + * The timeout for the initial BOOTP/DHCP request used to be described by a + * counter of fixed-length timeout periods. TIMEOUT_COUNT represents + * that counter + * + * Now that the timeout periods are variable (exponential backoff and retry) + * we convert the timeout count to the absolute time it would have take to + * execute that many retries, and keep sending retry packets until that time + * is reached. + */ #ifndef CONFIG_NET_RETRY_COUNT # define TIMEOUT_COUNT 5 /* # of timeouts before giving up */ #else # define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT) #endif +#define TIMEOUT_MS ((3 + (TIMEOUT_COUNT * 5)) * 1000) #define PORT_BOOTPS 67 /* BOOTP server UDP port */ #define PORT_BOOTPC 68 /* BOOTP client UDP port */ @@ -37,8 +47,15 @@ #define CONFIG_DHCP_MIN_EXT_LEN 64 #endif -static ulong BootpID; +#ifndef CONFIG_BOOTP_ID_CACHE_SIZE +#define CONFIG_BOOTP_ID_CACHE_SIZE 4 +#endif + +ulong bootp_ids[CONFIG_BOOTP_ID_CACHE_SIZE]; +unsigned int bootp_num_ids; int BootpTry; +ulong bootp_start; +ulong bootp_timeout; #if defined(CONFIG_CMD_DHCP) static dhcp_state_t dhcp_state = INIT; @@ -65,6 +82,30 @@ static char *dhcpmsg2str(int type) #endif #endif +static void bootp_add_id(ulong id) +{ + if (bootp_num_ids >= ARRAY_SIZE(bootp_ids)) { + size_t size = sizeof(bootp_ids) - sizeof(id); + + memmove(bootp_ids, &bootp_ids[1], size); + bootp_ids[bootp_num_ids - 1] = id; + } else { + bootp_ids[bootp_num_ids] = id; + bootp_num_ids++; + } +} + +static bool bootp_match_id(ulong id) +{ + unsigned int i; + + for (i = 0; i < bootp_num_ids; i++) + if (bootp_ids[i] == id) + return true; + + return false; +} + static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) { struct Bootp_t *bp = (struct Bootp_t *) pkt; @@ -84,7 +125,7 @@ static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) retval = -4; else if (bp->bp_hlen != HWL_ETHER) retval = -5; - else if (NetReadLong((ulong *)&bp->bp_id) != BootpID) + else if (!bootp_match_id(NetReadLong((ulong *)&bp->bp_id))) retval = -6; debug("Filtering pkt = %d\n", retval); @@ -104,8 +145,6 @@ static void BootpCopyNetParams(struct Bootp_t *bp) if (tmp_ip != 0) NetCopyIP(&NetServerIP, &bp->bp_siaddr); memcpy(NetServerEther, ((struct ethernet_hdr *)NetRxPacket)->et_src, 6); -#endif - NetCopyIP(&NetOurIP, &bp->bp_yiaddr); if (strlen(bp->bp_file) > 0) copy_filename(BootFile, bp->bp_file, sizeof(BootFile)); @@ -117,6 +156,8 @@ static void BootpCopyNetParams(struct Bootp_t *bp) */ if (*BootFile) setenv("bootfile", BootFile); +#endif + NetCopyIP(&NetOurIP, &bp->bp_yiaddr); } static int truncate_sz(const char *name, int maxlen, int curlen) @@ -327,16 +368,21 @@ BootpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, static void BootpTimeout(void) { - if (BootpTry >= TIMEOUT_COUNT) { + ulong time_taken = get_timer(bootp_start); + + if (time_taken >= TIMEOUT_MS) { #ifdef CONFIG_BOOTP_MAY_FAIL - puts("\nRetry count exceeded\n"); + puts("\nRetry time exceeded\n"); net_set_state(NETLOOP_FAIL); #else - puts("\nRetry count exceeded; starting again\n"); + puts("\nRetry time exceeded; starting again\n"); NetStartAgain(); #endif } else { - NetSetTimeout(TIMEOUT, BootpTimeout); + bootp_timeout *= 2; + if (bootp_timeout > 2000) + bootp_timeout = 2000; + NetSetTimeout(bootp_timeout, BootpTimeout); BootpRequest(); } } @@ -439,7 +485,7 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, *e++ = 17; *e++ = 0; /* type 0 - UUID */ - uuid_str_to_bin(uuid, e); + uuid_str_to_bin(uuid, e, UUID_STR_FORMAT_STD); e += 16; } else { printf("Invalid pxeuuid: %s\n", uuid); @@ -597,6 +643,14 @@ static int BootpExtended(u8 *e) } #endif +void BootpReset(void) +{ + bootp_num_ids = 0; + BootpTry = 0; + bootp_start = get_timer(0); + bootp_timeout = 250; +} + void BootpRequest(void) { @@ -605,8 +659,9 @@ BootpRequest(void) int extlen, pktlen, iplen; int eth_hdr_size; #ifdef CONFIG_BOOTP_RANDOM_DELAY - ulong i, rand_ms; + ulong rand_ms; #endif + ulong BootpID; bootstage_mark_name(BOOTSTAGE_ID_BOOTP_START, "bootp_start"); #if defined(CONFIG_CMD_DHCP) @@ -623,8 +678,7 @@ BootpRequest(void) rand_ms = rand() >> 19; printf("Random delay: %ld ms...\n", rand_ms); - for (i = 0; i < rand_ms; i++) - udelay(1000); /*Wait 1ms*/ + mdelay(rand_ms); #endif /* CONFIG_BOOTP_RANDOM_DELAY */ @@ -679,7 +733,8 @@ BootpRequest(void) | ((ulong)NetOurEther[4] << 8) | (ulong)NetOurEther[5]; BootpID += get_timer(0); - BootpID = htonl(BootpID); + BootpID = htonl(BootpID); + bootp_add_id(BootpID); #endif NetCopyLong(&bp->bp_id, &BootpID); @@ -690,7 +745,7 @@ BootpRequest(void) iplen = BOOTP_HDR_SIZE - OPT_FIELD_SIZE + extlen; pktlen = eth_hdr_size + IP_UDP_HDR_SIZE + iplen; net_set_udp_header(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen); - NetSetTimeout(SELECT_TIMEOUT, BootpTimeout); + NetSetTimeout(bootp_timeout, BootpTimeout); #if defined(CONFIG_CMD_DHCP) dhcp_state = SELECTING; @@ -923,7 +978,7 @@ DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, htonl(BOOTP_VENDOR_MAGIC)) DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp); - NetSetTimeout(TIMEOUT, BootpTimeout); + NetSetTimeout(5000, BootpTimeout); DhcpSendRequestPkt(bp); #ifdef CONFIG_SYS_BOOTFILE_PREFIX } @@ -941,8 +996,8 @@ DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, /* Store net params from reply */ BootpCopyNetParams(bp); dhcp_state = BOUND; - printf("DHCP client bound to address %pI4\n", - &NetOurIP); + printf("DHCP client bound to address %pI4 (%lu ms)\n", + &NetOurIP, get_timer(bootp_start)); bootstage_mark_name(BOOTSTAGE_ID_BOOTP_STOP, "bootp_stop"); diff --git a/net/bootp.h b/net/bootp.h index a7117528a4..3ffbc51db3 100644 --- a/net/bootp.h +++ b/net/bootp.h @@ -64,6 +64,7 @@ extern int BootpTry; /* Send a BOOTP request */ +extern void BootpReset(void); extern void BootpRequest(void); /****************** DHCP Support *********************/ @@ -87,8 +88,6 @@ typedef enum { INIT, #define DHCP_NAK 6 #define DHCP_RELEASE 7 -#define SELECT_TIMEOUT 3000UL /* Milliseconds to wait for offers */ - /**********************************************************************/ #endif /* __BOOTP_H__ */ diff --git a/net/cdp.c b/net/cdp.c index 3d9559eb3b..2d8fa03a7e 100644 --- a/net/cdp.c +++ b/net/cdp.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include diff --git a/net/cdp.h b/net/cdp.h index ec7315af79..95e4ce025d 100644 --- a/net/cdp.h +++ b/net/cdp.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #if defined(CONFIG_CMD_CDP) diff --git a/net/checksum.c b/net/checksum.c new file mode 100644 index 0000000000..a8c9ff5ea4 --- /dev/null +++ b/net/checksum.c @@ -0,0 +1,60 @@ +/* + * This file was originally taken from the FreeBSD project. + * + * Copyright (c) 2001 Charles Mott + * Copyright (c) 2008 coresystems GmbH + * All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#include +#include + +unsigned compute_ip_checksum(const void *vptr, unsigned nbytes) +{ + int sum, oddbyte; + const unsigned short *ptr = vptr; + + sum = 0; + while (nbytes > 1) { + sum += *ptr++; + nbytes -= 2; + } + if (nbytes == 1) { + oddbyte = 0; + ((u8 *)&oddbyte)[0] = *(u8 *)ptr; + ((u8 *)&oddbyte)[1] = 0; + sum += oddbyte; + } + sum = (sum >> 16) + (sum & 0xffff); + sum += (sum >> 16); + sum = ~sum & 0xffff; + + return sum; +} + +unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new) +{ + unsigned long checksum; + + sum = ~sum & 0xffff; + new = ~new & 0xffff; + if (offset & 1) { + /* + * byte-swap the sum if it came from an odd offset; since the + * computation is endian independant this works. + */ + new = ((new >> 8) & 0xff) | ((new << 8) & 0xff00); + } + checksum = sum + new; + if (checksum > 0xffff) + checksum -= 0xffff; + + return (~checksum) & 0xffff; +} + +int ip_checksum_ok(const void *addr, unsigned nbytes) +{ + return !(compute_ip_checksum(addr, nbytes) & 0xfffe); +} diff --git a/net/dns.c b/net/dns.c index ff9ddffc9d..dd45320150 100644 --- a/net/dns.c +++ b/net/dns.c @@ -202,5 +202,8 @@ DnsStart(void) NetSetTimeout(DNS_TIMEOUT, DnsTimeout); net_set_udp_handler(DnsHandler); + /* Clear a previous MAC address, the server IP might have changed. */ + memset(NetServerEther, 0, sizeof(NetServerEther)); + DnsSend(); } diff --git a/net/eth.c b/net/eth.c index 77ea5580aa..eac4f7b3d0 100644 --- a/net/eth.c +++ b/net/eth.c @@ -10,6 +10,7 @@ #include #include #include +#include void eth_parse_enetaddr(const char *addr, uchar *enetaddr) { @@ -63,28 +64,6 @@ static int eth_mac_skip(int index) return ((skip_state = getenv(enetvar)) != NULL); } -#ifdef CONFIG_RANDOM_MACADDR -void eth_random_enetaddr(uchar *enetaddr) -{ - uint32_t rval; - - srand(rand() ^ get_timer(0)); - - rval = rand(); - enetaddr[0] = rval & 0xff; - enetaddr[1] = (rval >> 8) & 0xff; - enetaddr[2] = (rval >> 16) & 0xff; - - rval = rand(); - enetaddr[3] = rval & 0xff; - enetaddr[4] = (rval >> 8) & 0xff; - enetaddr[5] = (rval >> 16) & 0xff; - - /* make sure it's local and unicast */ - enetaddr[0] = (enetaddr[0] | 0x02) & ~0x01; -} -#endif - /* * CPU and board-specific Ethernet initializations. Aliased function * signals caller to move on @@ -174,6 +153,11 @@ static void eth_current_changed(void) setenv("ethact", NULL); } +static int eth_address_set(unsigned char *addr) +{ + return memcmp(addr, "\0\0\0\0\0\0", 6); +} + int eth_write_hwaddr(struct eth_device *dev, const char *base_name, int eth_number) { @@ -182,8 +166,8 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name, eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr); - if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { - if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) && + if (eth_address_set(env_enetaddr)) { + if (eth_address_set(dev->enetaddr) && memcmp(dev->enetaddr, env_enetaddr, 6)) { printf("\nWarning: %s MAC addresses don't match:\n", dev->name); @@ -199,14 +183,22 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name, dev->enetaddr); printf("\nWarning: %s using MAC address from net device\n", dev->name); + } else if (!(eth_address_set(dev->enetaddr))) { + printf("\nError: %s address not set.\n", + dev->name); + return -EINVAL; } - if (dev->write_hwaddr && - !eth_mac_skip(eth_number)) { - if (!is_valid_ether_addr(dev->enetaddr)) - return -1; + if (dev->write_hwaddr && !eth_mac_skip(eth_number)) { + if (!is_valid_ether_addr(dev->enetaddr)) { + printf("\nError: %s address %pM illegal value\n", + dev->name, dev->enetaddr); + return -EINVAL; + } ret = dev->write_hwaddr(dev); + if (ret) + printf("\nWarning: %s failed to set MAC address\n", dev->name); } return ret; @@ -279,7 +271,7 @@ int eth_initialize(bd_t *bis) eth_current = NULL; bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_init(); #endif @@ -325,8 +317,7 @@ int eth_initialize(bd_t *bis) puts("\nWarning: eth device name has a space!" "\n"); - if (eth_write_hwaddr(dev, "eth", dev->index)) - puts("\nWarning: failed to set MAC address\n"); + eth_write_hwaddr(dev, "eth", dev->index); dev = dev->next; num_devices++; diff --git a/net/net.c b/net/net.c index 019d161bc7..30ecfcc403 100644 --- a/net/net.c +++ b/net/net.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ /* @@ -207,6 +208,8 @@ static int net_check_prereq(enum proto_t protocol); static int NetTryCount; +int __maybe_unused net_busy_flag; + /**********************************************************************/ static int on_bootfile(const char *name, const char *value, enum env_op op, @@ -342,6 +345,9 @@ int NetLoop(enum proto_t protocol) eth_init_state_only(bd); restart: +#ifdef CONFIG_USB_KEYBOARD + net_busy_flag = 0; +#endif net_set_state(NETLOOP_CONTINUE); /* @@ -380,14 +386,14 @@ restart: #endif #if defined(CONFIG_CMD_DHCP) case DHCP: - BootpTry = 0; + BootpReset(); NetOurIP = 0; DhcpRequest(); /* Basically same as BOOTP */ break; #endif case BOOTP: - BootpTry = 0; + BootpReset(); NetOurIP = 0; BootpRequest(); break; @@ -414,7 +420,7 @@ restart: CDPStart(); break; #endif -#ifdef CONFIG_NETCONSOLE +#if defined (CONFIG_NETCONSOLE) && !(CONFIG_SPL_BUILD) case NETCONS: NcStart(); break; @@ -459,6 +465,9 @@ restart: status_led_set(STATUS_LED_RED, STATUS_LED_ON); #endif /* CONFIG_SYS_FAULT_ECHO_LINK_DOWN, ... */ #endif /* CONFIG_MII, ... */ +#ifdef CONFIG_USB_KEYBOARD + net_busy_flag = 1; +#endif /* * Main packet reception loop. Loop receiving packets until @@ -565,6 +574,9 @@ restart: } done: +#ifdef CONFIG_USB_KEYBOARD + net_busy_flag = 0; +#endif #ifdef CONFIG_CMD_TFTPPUT /* Clear out the handlers */ net_set_udp_handler(NULL); @@ -1177,7 +1189,7 @@ NetReceive(uchar *inpkt, int len) #endif -#ifdef CONFIG_NETCONSOLE +#if defined (CONFIG_NETCONSOLE) && !(CONFIG_SPL_BUILD) nc_input_packet((uchar *)ip + IP_UDP_HDR_SIZE, src_ip, ntohs(ip->udp_dst), diff --git a/net/ping.c b/net/ping.c index 0710b9228d..2be56ed929 100644 --- a/net/ping.c +++ b/net/ping.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include "ping.h" diff --git a/net/ping.h b/net/ping.h index 8c71be4fdf..b672b95739 100644 --- a/net/ping.h +++ b/net/ping.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __PING_H__ diff --git a/net/tftp.c b/net/tftp.c index 6d333d559c..0a2c53302c 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -281,7 +281,7 @@ static void update_block_number(void) * number of 0 this means that there was a wrap * around of the (16 bit) counter. */ - if (TftpBlock == 0) { + if (TftpBlock == 0 && TftpLastBlock != 0) { TftpBlockWrap++; TftpBlockWrapOffset += TftpBlkSize * TFTP_SEQUENCE_SIZE; TftpTimeoutCount = 0; /* we've done well, reset thhe timeout */ @@ -299,6 +299,8 @@ static void tftp_complete(void) putc('#'); TftpNumchars++; } + puts(" "); + print_size(TftpTsize, ""); #endif time_start = get_timer(time_start); if (time_start > 0) { @@ -849,6 +851,9 @@ TftpStartServer(void) TftpState = STATE_RECV_WRQ; net_set_udp_handler(TftpHandler); + + /* zero out server ether in case the server ip has changed */ + memset(NetServerEther, 0, 6); } #endif /* CONFIG_CMD_TFTPSRV */ diff --git a/post/Makefile b/post/Makefile index 04d8f78f15..2fa6f8a295 100644 --- a/post/Makefile +++ b/post/Makefile @@ -5,54 +5,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = libpost.o -GPLIB-$(CONFIG_HAS_POST) += libgenpost.o -COBJS-$(CONFIG_HAS_POST) += post.o -COBJS-$(CONFIG_POST_STD_LIST) += tests.o - -SPLIB-$(CONFIG_HAS_POST) = drivers/libpostdrivers.o -SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH) ]; then echo \ - "lib_$(ARCH)/libpost$(ARCH).o"; fi) -SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH)/fpu ]; then echo \ - "lib_$(ARCH)/fpu/libpost$(ARCH)fpu.o"; fi) -SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d cpu/$(CPU) ]; then echo \ - "cpu/$(CPU)/libpost$(CPU).o"; fi) -SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d board/$(BOARD) ]; then echo \ - "board/$(BOARD)/libpost$(BOARD).o"; fi) - -GPLIB := $(addprefix $(obj),$(GPLIB-y)) -SPLIB := $(addprefix $(obj),$(SPLIB-y)) -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -LIB := $(obj)$(LIB) - -all: $(LIB) - -postdeps: - @for lib in $(SPLIB-y) ; do \ - $(MAKE) -C `dirname $$lib` all ; \ - done - -# generic POST library -$(GPLIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -# specific POST libraries -$(SPLIB): $(obj).depend postdeps - $(MAKE) -C $(dir $(subst $(obj),,$@)) - -# the POST lib archive -$(LIB): $(GPLIB) $(SPLIB) - $(call cmd_link_o_target, $^) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-y += post.o +obj-$(CONFIG_POST_STD_LIST) += tests.o + +obj-y += drivers/ +obj-$(CONFIG_PPC) += lib_powerpc/ +obj-$(CONFIG_MPC83xx) += cpu/mpc83xx/ +obj-$(CONFIG_8xx) += cpu/mpc8xx/ +obj-$(CONFIG_4xx) += cpu/ppc4xx/ +ifneq ($(filter lwmon lwmon5 netta pdm360ng,$(BOARD)),) +obj-y += board/$(BOARD)/ +endif diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile index d38498bc47..7f6d5a084e 100644 --- a/post/board/lwmon/Makefile +++ b/post/board/lwmon/Makefile @@ -4,10 +4,5 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(OBJTREE)/include/autoconf.mk -LIB = libpostlwmon.o - -COBJS-$(CONFIG_HAS_POST) += sysmon.o - -include $(TOPDIR)/post/rules.mk +obj-y += sysmon.o diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile index b410dbb399..76262c76bc 100644 --- a/post/board/lwmon5/Makefile +++ b/post/board/lwmon5/Makefile @@ -4,10 +4,5 @@ # Developed for DENX Software Engineering GmbH # # SPDX-License-Identifier: GPL-2.0+ -include $(OBJTREE)/include/autoconf.mk -LIB = libpostlwmon5.o - -COBJS-$(CONFIG_HAS_POST) += sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o - -include $(TOPDIR)/post/rules.mk +obj-y += sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c index da37d66bfa..cca1a26235 100644 --- a/post/board/lwmon5/sysmon.c +++ b/post/board/lwmon5/sysmon.c @@ -22,7 +22,7 @@ * * LCD backlight is not enabled if temperature values are not within * allowed ranges (-30 .. + 80). The brightness of backlite can be - * controlled by setting "brightness" enviroment variable. Default value is 50% + * controlled by setting "brightness" environment variable. Default value is 50% * * See the list of all parameters in the sysmon_table below */ diff --git a/post/board/netta/Makefile b/post/board/netta/Makefile index 2d73f55f25..8fc1945b07 100644 --- a/post/board/netta/Makefile +++ b/post/board/netta/Makefile @@ -4,10 +4,5 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(OBJTREE)/include/autoconf.mk -LIB = libpostnetta.o - -COBJS-$(CONFIG_HAS_POST) += codec.o dsp.o - -include $(TOPDIR)/post/rules.mk +obj-y += codec.o dsp.o diff --git a/post/board/pdm360ng/Makefile b/post/board/pdm360ng/Makefile index cb03e5896d..9aa96a1f6a 100644 --- a/post/board/pdm360ng/Makefile +++ b/post/board/pdm360ng/Makefile @@ -4,10 +4,5 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(OBJTREE)/include/autoconf.mk -LIB = libpostpdm360ng.o - -COBJS-$(CONFIG_HAS_POST) += coproc_com.o - -include $(TOPDIR)/post/rules.mk +obj-y += coproc_com.o diff --git a/post/cpu/mpc83xx/Makefile b/post/cpu/mpc83xx/Makefile index 6ac56dc2e8..d57b66757e 100644 --- a/post/cpu/mpc83xx/Makefile +++ b/post/cpu/mpc83xx/Makefile @@ -4,11 +4,5 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(OBJTREE)/include/autoconf.mk -LIB = libpostmpc83xx.o - -AOBJS-$(CONFIG_HAS_POST) += -COBJS-$(CONFIG_HAS_POST) += ecc.o - -include $(TOPDIR)/post/rules.mk +obj-y += ecc.o diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile index efde1fb3dc..f8bb6c9343 100644 --- a/post/cpu/mpc8xx/Makefile +++ b/post/cpu/mpc8xx/Makefile @@ -4,11 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(OBJTREE)/include/autoconf.mk -LIB = libpostmpc8xx.o - -AOBJS-$(CONFIG_HAS_POST) += cache_8xx.o -COBJS-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o - -include $(TOPDIR)/post/rules.mk +obj-$(CONFIG_HAS_POST) += cache_8xx.o +obj-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c index 91505475e8..3a8b483e3c 100644 --- a/post/cpu/mpc8xx/ether.c +++ b/post/cpu/mpc8xx/ether.c @@ -114,19 +114,6 @@ static void scc_init (int scc_index) immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); -#if defined(CONFIG_FADS) -#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS) - /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */ - *((uint *) BCSR4) &= ~BCSR4_ETHLOOP; - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#else - *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN); - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif -#endif - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]); rxIdx = 0; @@ -365,34 +352,12 @@ static void scc_init (int scc_index) immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | SCC_PSMR_NIB22 | SCC_PSMR_LPB; -#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - -#ifdef CONFIG_RPXLITE - *((uchar *) BCSR0) |= BCSR0_ETHEN; -#endif - -#ifdef CONFIG_MBX - board_ether_init (); -#endif - /* * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive */ immr->im_cpm.cp_scc[scc_index].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* - * Work around transmit problem with first eth packet - */ -#if defined (CONFIG_FADS) - udelay (10000); /* wait 10 ms */ -#elif defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ -#endif } static void scc_halt (int scc_index) diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c index 106a9b87d2..e54a4cacfa 100644 --- a/post/cpu/mpc8xx/uart.c +++ b/post/cpu/mpc8xx/uart.c @@ -100,17 +100,6 @@ static void smc_init (int smc_index) im->im_sdma.sdma_sdmr = 0x00; #endif -#if defined(CONFIG_FADS) - /* Enable RS232 */ - *((uint *) BCSR1) &= - ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2); -#endif - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) - /* Enable Monitor Port Transceiver */ - *((uchar *) BCSR0) |= BCSR0_ENMONXCVR; -#endif - /* Set the physical address of the host memory buffers in * the buffer descriptors. */ @@ -141,10 +130,6 @@ static void smc_init (int smc_index) up->smc_rfcr = SMC_EB; up->smc_tfcr = SMC_EB; -#if defined(CONFIG_MBX) - board_serial_init (); -#endif - /* Set UART mode, 8 bit, no parity, one stop. * Enable receive and transmit. * Set local loopback mode. diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile index 614cef03fc..e9ec286c7c 100644 --- a/post/cpu/ppc4xx/Makefile +++ b/post/cpu/ppc4xx/Makefile @@ -4,18 +4,13 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(OBJTREE)/include/autoconf.mk -LIB = libpostppc4xx.o - -AOBJS-$(CONFIG_HAS_POST) += cache_4xx.o -COBJS-$(CONFIG_HAS_POST) += cache.o -COBJS-$(CONFIG_HAS_POST) += denali_ecc.o -COBJS-$(CONFIG_HAS_POST) += ether.o -COBJS-$(CONFIG_HAS_POST) += fpu.o -COBJS-$(CONFIG_HAS_POST) += ocm.o -COBJS-$(CONFIG_HAS_POST) += spr.o -COBJS-$(CONFIG_HAS_POST) += uart.o -COBJS-$(CONFIG_HAS_POST) += watchdog.o - -include $(TOPDIR)/post/rules.mk +obj-y += cache_4xx.o +obj-y += cache.o +obj-y += denali_ecc.o +obj-y += ether.o +obj-y += fpu.o +obj-y += ocm.o +obj-y += spr.o +obj-y += uart.o +obj-y += watchdog.o diff --git a/post/drivers/Makefile b/post/drivers/Makefile index 6720f85139..1abfb1ffe6 100644 --- a/post/drivers/Makefile +++ b/post/drivers/Makefile @@ -4,10 +4,5 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = libpostdrivers.o - -COBJS-$(CONFIG_HAS_POST) += flash.o i2c.o memory.o rtc.o - -include $(TOPDIR)/post/rules.mk +obj-y += flash.o i2c.o memory.o rtc.o diff --git a/post/drivers/memory.c b/post/drivers/memory.c index d94a437440..d512fa5c08 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -170,7 +170,7 @@ DECLARE_GLOBAL_DATA_PTR; */ static void move64(const unsigned long long *src, unsigned long long *dest) { -#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) +#if defined(CONFIG_MPC8260) asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ "stfd 0, 0(4)" /* *dest = fpr0 */ : : : "fr0" ); /* Clobbers fr0 */ diff --git a/post/lib_powerpc/Makefile b/post/lib_powerpc/Makefile index efa1fb2261..0cbb6b6bd2 100644 --- a/post/lib_powerpc/Makefile +++ b/post/lib_powerpc/Makefile @@ -4,13 +4,10 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = libpost$(ARCH).o +obj-y += asm.o +obj-y += cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o +obj-y += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o +obj-y += store.o load.o cr.o b.o multi.o string.o complex.o -AOBJS-$(CONFIG_HAS_POST) += asm.o -COBJS-$(CONFIG_HAS_POST) += cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o -COBJS-$(CONFIG_HAS_POST) += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o -COBJS-$(CONFIG_HAS_POST) += store.o load.o cr.o b.o multi.o string.o complex.o - -include $(TOPDIR)/post/rules.mk +obj-y += fpu/ diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c index 878b2ca7ab..8a4b89b983 100644 --- a/post/lib_powerpc/andi.c +++ b/post/lib_powerpc/andi.c @@ -89,7 +89,7 @@ int cpu_post_test_andi (void) if (ret != 0) { - post_log ("Error at andi test %d !\n", i); + post_log ("Error at andi test %d !\n", i); } } } diff --git a/post/lib_powerpc/cpu_asm.h b/post/lib_powerpc/cpu_asm.h index 66adad8f79..b5c588919e 100644 --- a/post/lib_powerpc/cpu_asm.h +++ b/post/lib_powerpc/cpu_asm.h @@ -112,64 +112,64 @@ #define ASM_0(opcode) (opcode) #define ASM_1(opcode, rd) ((opcode) + \ - ((rd) << 21)) + ((rd) << 21)) #define ASM_1C(opcode, cr) ((opcode) + \ - ((cr) << 23)) + ((cr) << 23)) #define ASM_11(opcode, rd, rs) ((opcode) + \ - ((rd) << 21) + \ + ((rd) << 21) + \ ((rs) << 16)) #define ASM_11C(opcode, cd, cs) ((opcode) + \ - ((cd) << 23) + \ + ((cd) << 23) + \ ((cs) << 18)) #define ASM_11X(opcode, rd, rs) ((opcode) + \ - ((rs) << 21) + \ + ((rs) << 21) + \ ((rd) << 16)) #define ASM_11I(opcode, rd, rs, simm) ((opcode) + \ - ((rd) << 21) + \ + ((rd) << 21) + \ ((rs) << 16) + \ ((simm) & 0xffff)) #define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \ - ((rd) << 21) + \ + ((rd) << 21) + \ ((rs) << 16) + \ ((simm) << 11)) #define ASM_11S(opcode, rd, rs, sh) ((opcode) + \ - ((rs) << 21) + \ + ((rs) << 21) + \ ((rd) << 16) + \ ((sh) << 11)) #define ASM_11IX(opcode, rd, rs, imm) ((opcode) + \ - ((rs) << 21) + \ + ((rs) << 21) + \ ((rd) << 16) + \ ((imm) & 0xffff)) #define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \ - ((rd) << 21) + \ + ((rd) << 21) + \ ((rs1) << 16) + \ ((rs2) << 11)) #define ASM_12F(opcode, fd, fs1, fs2) ((opcode) + \ - ((fd) << 21) + \ + ((fd) << 21) + \ ((fs1) << 16) + \ ((fs2) << 11)) #define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \ - ((rs1) << 21) + \ + ((rs1) << 21) + \ ((rd) << 16) + \ ((rs2) << 11)) #define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \ - ((cr) << 23) + \ + ((cr) << 23) + \ ((rs1) << 16) + \ ((rs2) << 11)) #define ASM_1IC(opcode, cr, rs, imm) ((opcode) + \ - ((cr) << 23) + \ + ((cr) << 23) + \ ((rs) << 16) + \ ((imm) & 0xffff)) #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ ((opcode) + \ - ((rs1) << 21) + \ + ((rs1) << 21) + \ ((rd) << 16) + \ ((rs2) << 11) + \ ((imm1) << 6) + \ ((imm2) << 1)) #define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \ ((opcode) + \ - ((rs) << 21) + \ + ((rs) << 21) + \ ((rd) << 16) + \ ((imm1) << 11) + \ ((imm2) << 6) + \ diff --git a/post/lib_powerpc/fpu/Makefile b/post/lib_powerpc/fpu/Makefile index eff7e6b402..5c2e804d90 100644 --- a/post/lib_powerpc/fpu/Makefile +++ b/post/lib_powerpc/fpu/Makefile @@ -4,27 +4,20 @@ # # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk -LIB = libpost$(ARCH)fpu.o +objs-before-objcopy := 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o \ + acc1.o compare-fp-1.o fpu.o mul-subnormal-single-1.o darwin-ldouble.o +targets += $(objs-before-objcopy) -COBJS-$(CONFIG_HAS_POST) += 20001122-1.o -COBJS-$(CONFIG_HAS_POST) += 20010114-2.o -COBJS-$(CONFIG_HAS_POST) += 20010226-1.o -COBJS-$(CONFIG_HAS_POST) += 980619-1.o -COBJS-$(CONFIG_HAS_POST) += acc1.o -COBJS-$(CONFIG_HAS_POST) += compare-fp-1.o -COBJS-$(CONFIG_HAS_POST) += fpu.o -COBJS-$(CONFIG_HAS_POST) += mul-subnormal-single-1.o +# remove -msoft-float flag +$(foreach m, $(objs-before-objcopy), $(eval CFLAGS_REMOVE_$m := -msoft-float)) +ccflags-y := -mhard-float -fkeep-inline-functions -COBJS-$(CONFIG_HAS_POST) += darwin-ldouble.o +# Do not delete intermidiate files (*.o) +.SECONDARY: $(call objectify, $(objs-before-objcopy)) -include $(TOPDIR)/post/rules.mk +obj-y := $(objs-before-objcopy:.o=_.o) -CFLAGS := $(shell echo $(CFLAGS) | sed s/-msoft-float//) -CFLAGS += -mhard-float -fkeep-inline-functions - -$(obj)%.o: %.c - $(CC) $(ALL_CFLAGS) -o $@.fp $< -c - $(OBJCOPY) -R .gnu.attributes $@.fp $@ - rm -f $@.fp +OBJCOPYFLAGS := -R .gnu.attributes +$(obj)/%_.o: $(obj)/%.o FORCE + $(call if_changed,objcopy) diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c index eccf71daa3..6bd53d06cb 100644 --- a/post/lib_powerpc/rlwimi.c +++ b/post/lib_powerpc/rlwimi.c @@ -114,7 +114,7 @@ int cpu_post_test_rlwimi (void) if (ret != 0) { - post_log ("Error at rlwimi test %d !\n", i); + post_log ("Error at rlwimi test %d !\n", i); } } @@ -127,8 +127,8 @@ int cpu_post_test_rlwimi (void) if (ret != 0) { - post_log ("Error at rlwimi test %d !\n", i); - } + post_log ("Error at rlwimi test %d !\n", i); + } } } } diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c index 5eaf30b8e7..35a1a40fc9 100644 --- a/post/lib_powerpc/rlwinm.c +++ b/post/lib_powerpc/rlwinm.c @@ -107,7 +107,7 @@ int cpu_post_test_rlwinm (void) if (ret != 0) { - post_log ("Error at rlwinm test %d !\n", i); + post_log ("Error at rlwinm test %d !\n", i); } } @@ -120,8 +120,8 @@ int cpu_post_test_rlwinm (void) if (ret != 0) { - post_log ("Error at rlwinm test %d !\n", i); - } + post_log ("Error at rlwinm test %d !\n", i); + } } } } diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c index 83ee70b52d..6e828939e0 100644 --- a/post/lib_powerpc/rlwnm.c +++ b/post/lib_powerpc/rlwnm.c @@ -117,7 +117,7 @@ int cpu_post_test_rlwnm (void) if (ret != 0) { - post_log ("Error at rlwnm test %d !\n", i); + post_log ("Error at rlwnm test %d !\n", i); } } @@ -130,8 +130,8 @@ int cpu_post_test_rlwnm (void) if (ret != 0) { - post_log ("Error at rlwnm test %d !\n", i); - } + post_log ("Error at rlwnm test %d !\n", i); + } } } } diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c index b2760140b5..3723e339b9 100644 --- a/post/lib_powerpc/srawi.c +++ b/post/lib_powerpc/srawi.c @@ -108,7 +108,7 @@ int cpu_post_test_srawi (void) if (ret != 0) { - post_log ("Error at srawi test %d !\n", i); + post_log ("Error at srawi test %d !\n", i); } } @@ -121,8 +121,8 @@ int cpu_post_test_srawi (void) if (ret != 0) { - post_log ("Error at srawi test %d !\n", i); - } + post_log ("Error at srawi test %d !\n", i); + } } } } diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c index f7317dded0..c3e7f681ab 100644 --- a/post/lib_powerpc/three.c +++ b/post/lib_powerpc/three.c @@ -211,7 +211,7 @@ int cpu_post_test_three (void) if (ret != 0) { - post_log ("Error at three test %d !\n", i); + post_log ("Error at three test %d !\n", i); } } @@ -224,8 +224,8 @@ int cpu_post_test_three (void) if (ret != 0) { - post_log ("Error at three test %d !\n", i); - } + post_log ("Error at three test %d !\n", i); + } } } } diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c index f6d9052532..1d40e1af33 100644 --- a/post/lib_powerpc/threei.c +++ b/post/lib_powerpc/threei.c @@ -103,7 +103,7 @@ int cpu_post_test_threei (void) if (ret != 0) { - post_log ("Error at threei test %d !\n", i); + post_log ("Error at threei test %d !\n", i); } } } diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c index 906fefd0d3..ce1edf89db 100644 --- a/post/lib_powerpc/threex.c +++ b/post/lib_powerpc/threex.c @@ -181,7 +181,7 @@ int cpu_post_test_threex (void) if (ret != 0) { - post_log ("Error at threex test %d !\n", i); + post_log ("Error at threex test %d !\n", i); } } @@ -194,8 +194,8 @@ int cpu_post_test_threex (void) if (ret != 0) { - post_log ("Error at threex test %d !\n", i); - } + post_log ("Error at threex test %d !\n", i); + } } } } diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c index 3a9b13684f..9549dbb750 100644 --- a/post/lib_powerpc/twox.c +++ b/post/lib_powerpc/twox.c @@ -128,7 +128,7 @@ int cpu_post_test_twox (void) if (ret != 0) { - post_log ("Error at twox test %d !\n", i); + post_log ("Error at twox test %d !\n", i); } } @@ -141,8 +141,8 @@ int cpu_post_test_twox (void) if (ret != 0) { - post_log ("Error at twox test %d !\n", i); - } + post_log ("Error at twox test %d !\n", i); + } } } } diff --git a/post/post.c b/post/post.c index 4af5355fa5..4194edb89e 100644 --- a/post/post.c +++ b/post/post.c @@ -52,7 +52,7 @@ int post_init_f(void) * Boards with hotkey support can override this weak default function * by defining one in their board specific code. */ -int __post_hotkeys_pressed(void) +__weak int post_hotkeys_pressed(void) { #ifdef CONFIG_SYS_POST_HOTKEYS_GPIO int ret; @@ -73,9 +73,6 @@ int __post_hotkeys_pressed(void) return 0; /* No hotkeys supported */ } -int post_hotkeys_pressed(void) - __attribute__((weak, alias("__post_hotkeys_pressed"))); - void post_bootmode_init(void) { @@ -236,11 +233,9 @@ static void post_get_flags(int *test_flags) test_flags[j] |= POST_SLOWTEST; } -void __show_post_progress(unsigned int test_num, int before, int result) +__weak void show_post_progress(unsigned int test_num, int before, int result) { } -void show_post_progress(unsigned int, int, int) - __attribute__((weak, alias("__show_post_progress"))); static int post_run_single(struct post_test *test, int test_flags, int flags, unsigned int i) diff --git a/post/rules.mk b/post/rules.mk deleted file mode 100644 index b25ebbf1cb..0000000000 --- a/post/rules.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -COBJS := $(COBJS-y) -AOBJS := $(AOBJS-y) -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) -LIB := $(obj)$(LIB) - -CPPFLAGS += -I$(TOPDIR) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/rules.mk b/rules.mk deleted file mode 100644 index f4510b7cb6..0000000000 --- a/rules.mk +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2006-2013 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -######################################################################### - -_depend: $(obj).depend - -# Split the source files into two camps: those in the current directory, and -# those somewhere else. For the first camp we want to support CPPFLAGS_ -# and for the second we don't / can't. -PWD_SRCS := $(filter $(notdir $(SRCS)),$(SRCS)) -OTHER_SRCS := $(filter-out $(notdir $(SRCS)),$(SRCS)) - -# This is a list of dependency files to generate -DEPS := $(basename $(patsubst %,$(obj).depend.%,$(PWD_SRCS))) - -# Join all the dependencies into a single file, in three parts -# 1 .Concatenate all the generated depend files together -# 2. Add in the deps from OTHER_SRCS which we couldn't process -# 3. Add in the HOSTSRCS -$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(DEPS) $(OTHER_SRCS) \ - $(HOSTSRCS) - cat /dev/null $(DEPS) >$@ - @for f in $(OTHER_SRCS); do \ - g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \ - $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ - done - @for f in $(HOSTSRCS); do \ - g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \ - $(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ - done - -MAKE_DEPEND = $(CC) -M $(CPPFLAGS) $(EXTRA_CPPFLAGS_DEP) \ - -MQ $(addsuffix .o,$(obj)$(basename $<)) $< >$@ - - -$(obj).depend.%: %.c - $(MAKE_DEPEND) - -$(obj).depend.%: %.S - $(MAKE_DEPEND) - -$(HOSTOBJS): $(obj)%.o: %.c - $(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c -$(NOPEDOBJS): $(obj)%.o: %.c - $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c - -######################################################################### diff --git a/scripts/.gitignore b/scripts/.gitignore new file mode 100644 index 0000000000..82bc06ef98 --- /dev/null +++ b/scripts/.gitignore @@ -0,0 +1,4 @@ +# +# Generated files +# +docproc diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include new file mode 100644 index 0000000000..d20f20ae32 --- /dev/null +++ b/scripts/Kbuild.include @@ -0,0 +1,296 @@ +#### +# kbuild: Generic definitions + +# Convenient variables +comma := , +quote := " +squote := ' +empty := +space := $(empty) $(empty) + +### +# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o +dot-target = $(dir $@).$(notdir $@) + +### +# The temporary file to save gcc -MD generated dependencies must not +# contain a comma +depfile = $(subst $(comma),_,$(dot-target).d) + +### +# filename of target with directory and extension stripped +basetarget = $(basename $(notdir $@)) + +### +# filename of first prerequisite with directory and extension stripped +baseprereq = $(basename $(notdir $<)) + +### +# Escape single quote for use in echo statements +escsq = $(subst $(squote),'\$(squote)',$1) + +### +# Easy method for doing a status message + kecho := : + quiet_kecho := echo +silent_kecho := : +kecho := $($(quiet)kecho) + +### +# filechk is used to check if the content of a generated file is updated. +# Sample usage: +# define filechk_sample +# echo $KERNELRELEASE +# endef +# version.h : Makefile +# $(call filechk,sample) +# The rule defined shall write to stdout the content of the new file. +# The existing file will be compared with the new one. +# - If no file exist it is created +# - If the content differ the new file is used +# - If they are equal no change, and no timestamp update +# - stdin is piped in from the first prerequisite ($<) so one has +# to specify a valid file as first prerequisite (often the kbuild file) +define filechk + $(Q)set -e; \ + $(kecho) ' CHK $@'; \ + mkdir -p $(dir $@); \ + $(filechk_$(1)) < $< > $@.tmp; \ + if [ -r $@ ] && cmp -s $@ $@.tmp; then \ + rm -f $@.tmp; \ + else \ + $(kecho) ' UPD $@'; \ + mv -f $@.tmp $@; \ + fi +endef + +###### +# gcc support functions +# See documentation in Documentation/kbuild/makefiles.txt + +# cc-cross-prefix +# Usage: CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu- m68k-linux-) +# Return first prefix where a prefix$(CC) is found in PATH. +# If no $(CC) found in PATH with listed prefixes return nothing +cc-cross-prefix = \ + $(word 1, $(foreach c,$(1), \ + $(shell set -e; \ + if (which $(strip $(c))$(CC)) > /dev/null 2>&1 ; then \ + echo $(c); \ + fi))) + +# output directory for tests below +TMPOUT := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/) + +# try-run +# Usage: option = $(call try-run, $(CC)...-o "$$TMP",option-ok,otherwise) +# Exit code chooses option. "$$TMP" is can be used as temporary file and +# is automatically cleaned up. +# modifed for U-Boot: prevent cc-option from leaving .*.su files +try-run = $(shell set -e; \ + TMP="$(TMPOUT).$$$$.tmp"; \ + TMPO="$(TMPOUT).$$$$.o"; \ + TMPSU="$(TMPOUT).$$$$.su"; \ + if ($(1)) >/dev/null 2>&1; \ + then echo "$(2)"; \ + else echo "$(3)"; \ + fi; \ + rm -f "$$TMP" "$$TMPO" "$$TMPSU") + +# as-option +# Usage: cflags-y += $(call as-option,-Wa$(comma)-isa=foo,) + +as-option = $(call try-run,\ + $(CC) $(KBUILD_CFLAGS) $(1) -c -x assembler /dev/null -o "$$TMP",$(1),$(2)) + +# as-instr +# Usage: cflags-y += $(call as-instr,instr,option1,option2) + +as-instr = $(call try-run,\ + printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3)) + +# cc-option +# Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586) + +cc-option = $(call try-run,\ + $(CC) -Werror $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2)) + +# cc-option-yn +# Usage: flag := $(call cc-option-yn,-march=winchip-c6) +cc-option-yn = $(call try-run,\ + $(CC) -Werror $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n) + +# cc-option-align +# Prefix align with either -falign or -malign +cc-option-align = $(subst -functions=0,,\ + $(call cc-option,-falign-functions=0,-malign-functions=0)) + +# cc-disable-warning +# Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable) +cc-disable-warning = $(call try-run,\ + $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1))) + +# cc-version +# Usage gcc-ver := $(call cc-version) +cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC)) + +# cc-fullversion +# Usage gcc-ver := $(call cc-fullversion) +cc-fullversion = $(shell $(CONFIG_SHELL) \ + $(srctree)/scripts/gcc-version.sh -p $(CC)) + +# cc-ifversion +# Usage: EXTRA_CFLAGS += $(call cc-ifversion, -lt, 0402, -O1) +cc-ifversion = $(shell [ $(call cc-version, $(CC)) $(1) $(2) ] && echo $(3)) + +# added for U-Boot +binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS)) +dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC)) + +# cc-ldoption +# Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both) +cc-ldoption = $(call try-run,\ + $(CC) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2)) + +# ld-option +# Usage: LDFLAGS += $(call ld-option, -X) +ld-option = $(call try-run,\ + $(CC) -x c /dev/null -c -o "$$TMPO" ; $(LD) $(1) "$$TMPO" -o "$$TMP",$(1),$(2)) + +# ar-option +# Usage: KBUILD_ARFLAGS := $(call ar-option,D) +# Important: no spaces around options +ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2)) + +# ld-version +# Usage: $(call ld-version) +# Note this is mainly for HJ Lu's 3 number binutil versions +ld-version = $(shell $(LD) --version | $(srctree)/scripts/ld-version.sh) + +# ld-ifversion +# Usage: $(call ld-ifversion, -ge, 22252, y) +ld-ifversion = $(shell [ $(call ld-version) $(1) $(2) ] && echo $(3)) + +###### + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj= +# Usage: +# $(Q)$(MAKE) $(build)=dir +build := -f $(srctree)/scripts/Makefile.build obj + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj= +# Usage: +# $(Q)$(MAKE) $(modbuiltin)=dir +modbuiltin := -f $(srctree)/scripts/Makefile.modbuiltin obj + +# Prefix -I with $(srctree) if it is not an absolute path. +# skip if -I has no parameter +addtree = $(if $(patsubst -I%,%,$(1)), \ +$(if $(filter-out -I/%,$(1)),$(patsubst -I%,-I$(srctree)/%,$(1))) $(1)) + +# Find all -I options and call addtree +flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o))) + +# echo command. +# Short version is used, if $(quiet) equals `quiet_', otherwise full one. +echo-cmd = $(if $($(quiet)cmd_$(1)),\ + echo ' $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';) + +# printing commands +cmd = @$(echo-cmd) $(cmd_$(1)) + +# Add $(obj)/ for paths that are not absolute +objectify = $(foreach o,$(1),$(if $(filter /%,$(o)),$(o),$(obj)/$(o))) + +### +# if_changed - execute command if any prerequisite is newer than +# target, or command line has changed +# if_changed_dep - as if_changed, but uses fixdep to reveal dependencies +# including used config symbols +# if_changed_rule - as if_changed but execute rule instead +# See Documentation/kbuild/makefiles.txt for more info + +ifneq ($(KBUILD_NOCMDDEP),1) +# Check if both arguments has same arguments. Result is empty string if equal. +# User may override this check using make KBUILD_NOCMDDEP=1 +arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \ + $(filter-out $(cmd_$@), $(cmd_$(1))) ) +else +arg-check = $(if $(strip $(cmd_$@)),,1) +endif + +# Replace >$< with >$$< to preserve $ when reloading the .cmd file +# (needed for make) +# Replace >#< with >\#< to avoid starting a comment in the .cmd file +# (needed for make) +# Replace >'< with >'\''< to be able to enclose the whole string in '...' +# (needed for the shell) +make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1))))) + +# Find any prerequisites that is newer than target or that does not exist. +# PHONY targets skipped in both cases. +any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^) + +# Execute command if command has changed or prerequisite(s) are updated. +# +if_changed = $(if $(strip $(any-prereq) $(arg-check)), \ + @set -e; \ + $(echo-cmd) $(cmd_$(1)); \ + printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd) + +# Execute the command and also postprocess generated .d dependencies file. +if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \ + @set -e; \ + $(echo-cmd) $(cmd_$(1)); \ + scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp;\ + rm -f $(depfile); \ + mv -f $(dot-target).tmp $(dot-target).cmd) + +# Usage: $(call if_changed_rule,foo) +# Will check if $(cmd_foo) or any of the prerequisites changed, +# and if so will execute $(rule_foo). +if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ), \ + @set -e; \ + $(rule_$(1))) + +### +# why - tell why a a target got build +# enabled by make V=2 +# Output (listed in the order they are checked): +# (1) - due to target is PHONY +# (2) - due to target missing +# (3) - due to: file1.h file2.h +# (4) - due to command line change +# (5) - due to missing .cmd file +# (6) - due to target not in $(targets) +# (1) PHONY targets are always build +# (2) No target, so we better build it +# (3) Prerequisite is newer than target +# (4) The command line stored in the file named dir/.target.cmd +# differed from actual command line. This happens when compiler +# options changes +# (5) No dir/.target.cmd file (used to store command line) +# (6) No dir/.target.cmd file and target not listed in $(targets) +# This is a good hint that there is a bug in the kbuild file +ifeq ($(KBUILD_VERBOSE),2) +why = \ + $(if $(filter $@, $(PHONY)),- due to target is PHONY, \ + $(if $(wildcard $@), \ + $(if $(strip $(any-prereq)),- due to: $(any-prereq), \ + $(if $(arg-check), \ + $(if $(cmd_$@),- due to command line change, \ + $(if $(filter $@, $(targets)), \ + - due to missing .cmd file, \ + - due to $(notdir $@) not in $$(targets) \ + ) \ + ) \ + ) \ + ), \ + - due to target missing \ + ) \ + ) + +echo-why = $(call escsq, $(strip $(why))) +endif diff --git a/scripts/Lindent b/scripts/Lindent new file mode 100755 index 0000000000..9c4b3e2b70 --- /dev/null +++ b/scripts/Lindent @@ -0,0 +1,18 @@ +#!/bin/sh +PARAM="-npro -kr -i8 -ts8 -sob -l80 -ss -ncs -cp1" +RES=`indent --version` +V1=`echo $RES | cut -d' ' -f3 | cut -d'.' -f1` +V2=`echo $RES | cut -d' ' -f3 | cut -d'.' -f2` +V3=`echo $RES | cut -d' ' -f3 | cut -d'.' -f3` +if [ $V1 -gt 2 ]; then + PARAM="$PARAM -il0" +elif [ $V1 -eq 2 ]; then + if [ $V2 -gt 2 ]; then + PARAM="$PARAM -il0"; + elif [ $V2 -eq 2 ]; then + if [ $V3 -ge 10 ]; then + PARAM="$PARAM -il0" + fi + fi +fi +indent $PARAM "$@" diff --git a/scripts/Makefile b/scripts/Makefile new file mode 100644 index 0000000000..efe25bfc6e --- /dev/null +++ b/scripts/Makefile @@ -0,0 +1,16 @@ +### +# scripts contains sources for various helper programs used throughout +# the kernel for the build process. +# --------------------------------------------------------------------------- +# docproc: Used in Documentation/DocBook + +# The following hostprogs-y programs are only build on demand +hostprogs-y += docproc + +# These targets are used internally to avoid "is up to date" messages +PHONY += build_docproc +build_docproc: $(obj)/docproc + @: + +# Let clean descend into subdirs +subdir- += basic kconfig diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf new file mode 100644 index 0000000000..8e9d71f89e --- /dev/null +++ b/scripts/Makefile.autoconf @@ -0,0 +1,102 @@ +# This helper makefile is used for creating +# - symbolic links (arch/$ARCH/include/asm/arch +# - include/autoconf.mk, {spl,tpl}/include/autoconf.mk +# - include/config.h +# +# When our migration to Kconfig is done +# (= When we move all CONFIGs from header files to Kconfig) +# this makefile can be deleted. + +# obj is "include" or "spl/include" or "tpl/include" +# for non-SPL, SPL, TPL, respectively +include $(obj)/config/auto.conf + +include scripts/Kbuild.include + +# Need to define CC and CPP again here in case the top Makefile did not +# include config.mk. Some architectures expect CROSS_COMPILE to be defined +# in arch/$(ARCH)/config.mk +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E + +include config.mk + +UBOOTINCLUDE := \ + -I$(obj) \ + -Iinclude \ + $(if $(KBUILD_SRC), -I$(srctree)/include) \ + -I$(srctree)/arch/$(ARCH)/include \ + -include $(srctree)/include/linux/kconfig.h + +c_flags := $(KBUILD_CFLAGS) $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) \ + $(UBOOTINCLUDE) $(NOSTDINC_FLAGS) + +quiet_cmd_autoconf_dep = GEN $@ + cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M -MP $(c_flags) \ + -MQ include/config/auto.conf $(srctree)/include/common.h > $@ || { \ + rm $@; false; \ + } +include/autoconf.mk.dep: FORCE + $(call cmd,autoconf_dep) + +# We are migrating from board headers to Kconfig little by little. +# In the interim, we use both of +# - include/config/auto.conf (generated by Kconfig) +# - include/autoconf.mk (used in the U-Boot conventional configuration) +# The following rule creates autoconf.mk +# include/config/auto.conf is grepped in order to avoid duplication of the +# same CONFIG macros +quiet_cmd_autoconf = GEN $@ + cmd_autoconf = \ + $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \ + sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp | \ + while read line; do \ + if ! grep -q "$${line%=*}=" $(obj)/config/auto.conf; then \ + echo "$$line"; \ + fi \ + done > $@; \ + rm $@.tmp; \ + } || { \ + rm $@.tmp; false; \ + } + +$(obj)/autoconf.mk: FORCE + $(call cmd,autoconf) + +include/autoconf.mk include/autoconf.mk.dep: include/config.h + +# include/config.h +# Prior to Kconfig, it was generated by mkconfig. Now it is created here. +define filechk_config_h + (echo "/* Automatically generated - do not edit */"; \ + for i in $$(echo $(CONFIG_SYS_EXTRA_OPTIONS) | sed 's/,/ /g'); do \ + echo \#define CONFIG_$$i \ + | sed '/=/ {s/=/ /;q; } ; { s/$$/ 1/; }'; \ + done; \ + echo \#define CONFIG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\ + echo \#include \; \ + echo \#include \; \ + echo \#include \; \ + echo \#include \; \ + echo \#include \; ) +endef + +include/config.h: scripts/Makefile.autoconf create_symlink FORCE + $(call filechk,config_h) + +# symbolic links +PHONY += create_symlink +create_symlink: +ifneq ($(KBUILD_SRC),) + $(Q)mkdir -p include/asm + $(Q)ln -fsn $(KBUILD_SRC)/arch/$(ARCH)/include/asm/arch-$(if $(SOC),$(SOC),$(CPU)) \ + include/asm/arch +else + $(Q)ln -fsn arch-$(if $(SOC),$(SOC),$(CPU)) \ + arch/$(ARCH)/include/asm/arch +endif + +PHONY += FORCE +FORCE: + +.PHONY: $(PHONY) diff --git a/scripts/Makefile.build b/scripts/Makefile.build new file mode 100644 index 0000000000..14cf0925d2 --- /dev/null +++ b/scripts/Makefile.build @@ -0,0 +1,444 @@ +# ========================================================================== +# Building +# ========================================================================== + +# Modified for U-Boot +prefix := tpl +src := $(patsubst $(prefix)/%,%,$(obj)) +ifeq ($(obj),$(src)) +prefix := spl +src := $(patsubst $(prefix)/%,%,$(obj)) +ifeq ($(obj),$(src)) +prefix := . +endif +endif + +PHONY := __build +__build: + +# Init all relevant variables used in kbuild files so +# 1) they have correct type +# 2) they do not inherit any value from the environment +obj-y := +obj-m := +lib-y := +lib-m := +always := +targets := +subdir-y := +subdir-m := +EXTRA_AFLAGS := +EXTRA_CFLAGS := +EXTRA_CPPFLAGS := +EXTRA_LDFLAGS := +asflags-y := +ccflags-y := +cppflags-y := +ldflags-y := + +subdir-asflags-y := +subdir-ccflags-y := + +# Read auto.conf if it exists, otherwise ignore +# Modified for U-Boot +-include $(prefix)/include/config/auto.conf +-include $(prefix)/include/autoconf.mk + +include scripts/Kbuild.include + +# For backward compatibility check that these variables do not change +save-cflags := $(CFLAGS) + +# The filename Kbuild has precedence over Makefile +kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) +kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile) +include $(kbuild-file) + +# Added for U-Boot +asflags-y += $(PLATFORM_CPPFLAGS) +ccflags-y += $(PLATFORM_CPPFLAGS) +cppflags-y += $(PLATFORM_CPPFLAGS) + +# If the save-* variables changed error out +ifeq ($(KBUILD_NOPEDANTIC),) + ifneq ("$(save-cflags)","$(CFLAGS)") + $(error CFLAGS was changed in "$(kbuild-file)". Fix it to use ccflags-y) + endif +endif + +include scripts/Makefile.lib + +ifdef host-progs +ifneq ($(hostprogs-y),$(host-progs)) +$(warning kbuild: $(obj)/Makefile - Usage of host-progs is deprecated. Please replace with hostprogs-y!) +hostprogs-y += $(host-progs) +endif +endif + +# Do not include host rules unless needed +ifneq ($(hostprogs-y)$(hostprogs-m),) +include scripts/Makefile.host +endif + +# Uncommented for U-Boot +# We need to create output dicrectory for SPL and TPL even for in-tree build +#ifneq ($(KBUILD_SRC),) +# Create output directory if not already present +_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) + +# Create directories for object files if directory does not exist +# Needed when obj-y := dir/file.o syntax is used +_dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d))) +#endif + +ifndef obj +$(warning kbuild: Makefile.build is included improperly) +endif + +# =========================================================================== + +ifneq ($(strip $(lib-y) $(lib-m) $(lib-)),) +lib-target := $(obj)/lib.a +endif + +ifneq ($(strip $(obj-y) $(obj-m) $(obj-) $(subdir-m) $(lib-target)),) +builtin-target := $(obj)/built-in.o +endif + +modorder-target := $(obj)/modules.order + +# We keep a list of all modules in $(MODVERDIR) + +__build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \ + $(if $(KBUILD_MODULES),$(obj-m) $(modorder-target)) \ + $(subdir-ym) $(always) + @: + +# Linus' kernel sanity checking tool +ifneq ($(KBUILD_CHECKSRC),0) + ifeq ($(KBUILD_CHECKSRC),2) + quiet_cmd_force_checksrc = CHECK $< + cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ; + else + quiet_cmd_checksrc = CHECK $< + cmd_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ; + endif +endif + +# Do section mismatch analysis for each module/built-in.o +ifdef CONFIG_DEBUG_SECTION_MISMATCH + cmd_secanalysis = ; scripts/mod/modpost $@ +endif + +# Compile C sources (.c) +# --------------------------------------------------------------------------- + +# Default is built-in, unless we know otherwise +modkern_cflags = \ + $(if $(part-of-module), \ + $(KBUILD_CFLAGS_MODULE) $(CFLAGS_MODULE), \ + $(KBUILD_CFLAGS_KERNEL) $(CFLAGS_KERNEL)) +quiet_modtag := $(empty) $(empty) + +$(real-objs-m) : part-of-module := y +$(real-objs-m:.o=.i) : part-of-module := y +$(real-objs-m:.o=.s) : part-of-module := y +$(real-objs-m:.o=.lst): part-of-module := y + +$(real-objs-m) : quiet_modtag := [M] +$(real-objs-m:.o=.i) : quiet_modtag := [M] +$(real-objs-m:.o=.s) : quiet_modtag := [M] +$(real-objs-m:.o=.lst): quiet_modtag := [M] + +$(obj-m) : quiet_modtag := [M] + +# Default for not multi-part modules +modname = $(basetarget) + +$(multi-objs-m) : modname = $(modname-multi) +$(multi-objs-m:.o=.i) : modname = $(modname-multi) +$(multi-objs-m:.o=.s) : modname = $(modname-multi) +$(multi-objs-m:.o=.lst) : modname = $(modname-multi) +$(multi-objs-y) : modname = $(modname-multi) +$(multi-objs-y:.o=.i) : modname = $(modname-multi) +$(multi-objs-y:.o=.s) : modname = $(modname-multi) +$(multi-objs-y:.o=.lst) : modname = $(modname-multi) + +quiet_cmd_cc_s_c = CC $(quiet_modtag) $@ +cmd_cc_s_c = $(CC) $(c_flags) $(DISABLE_LTO) -fverbose-asm -S -o $@ $< + +$(obj)/%.s: $(src)/%.c FORCE + $(call if_changed_dep,cc_s_c) + +quiet_cmd_cc_i_c = CPP $(quiet_modtag) $@ +cmd_cc_i_c = $(CPP) $(c_flags) -o $@ $< + +$(obj)/%.i: $(src)/%.c FORCE + $(call if_changed_dep,cc_i_c) + +cmd_gensymtypes = \ + $(CPP) -D__GENKSYMS__ $(c_flags) $< | \ + $(GENKSYMS) $(if $(1), -T $(2)) \ + $(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX)) \ + $(if $(KBUILD_PRESERVE),-p) \ + -r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null)) + +quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@ +cmd_cc_symtypes_c = \ + set -e; \ + $(call cmd_gensymtypes,true,$@) >/dev/null; \ + test -s $@ || rm -f $@ + +$(obj)/%.symtypes : $(src)/%.c FORCE + $(call cmd,cc_symtypes_c) + +# C (.c) files +# The C file is compiled and updated dependency information is generated. +# (See cmd_cc_o_c + relevant part of rule_cc_o_c) + +quiet_cmd_cc_o_c = CC $(quiet_modtag) $@ + +ifndef CONFIG_MODVERSIONS +cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< + +else +# When module versioning is enabled the following steps are executed: +# o compile a .tmp_.o from .c +# o if .tmp_.o doesn't contain a __ksymtab version, i.e. does +# not export symbols, we just rename .tmp_.o to .o and +# are done. +# o otherwise, we calculate symbol versions using the good old +# genksyms on the preprocessed source and postprocess them in a way +# that they are usable as a linker script +# o generate .o from .tmp_.o using the linker to +# replace the unresolved symbols __crc_exported_symbol with +# the actual value of the checksum generated by genksyms + +cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $< +cmd_modversions = \ + if $(OBJDUMP) -h $(@D)/.tmp_$(@F) | grep -q __ksymtab; then \ + $(call cmd_gensymtypes,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \ + > $(@D)/.tmp_$(@F:.o=.ver); \ + \ + $(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \ + -T $(@D)/.tmp_$(@F:.o=.ver); \ + rm -f $(@D)/.tmp_$(@F) $(@D)/.tmp_$(@F:.o=.ver); \ + else \ + mv -f $(@D)/.tmp_$(@F) $@; \ + fi; +endif + +ifdef CONFIG_FTRACE_MCOUNT_RECORD +ifdef BUILD_C_RECORDMCOUNT +ifeq ("$(origin RECORDMCOUNT_WARN)", "command line") + RECORDMCOUNT_FLAGS = -w +endif +# Due to recursion, we must skip empty.o. +# The empty.o file is created in the make process in order to determine +# the target endianness and word size. It is made before all other C +# files, including recordmcount. +sub_cmd_record_mcount = \ + if [ $(@) != "scripts/mod/empty.o" ]; then \ + $(objtree)/scripts/recordmcount $(RECORDMCOUNT_FLAGS) "$(@)"; \ + fi; +recordmcount_source := $(srctree)/scripts/recordmcount.c \ + $(srctree)/scripts/recordmcount.h +else +sub_cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \ + "$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \ + "$(if $(CONFIG_64BIT),64,32)" \ + "$(OBJDUMP)" "$(OBJCOPY)" "$(CC) $(KBUILD_CFLAGS)" \ + "$(LD)" "$(NM)" "$(RM)" "$(MV)" \ + "$(if $(part-of-module),1,0)" "$(@)"; +recordmcount_source := $(srctree)/scripts/recordmcount.pl +endif +cmd_record_mcount = \ + if [ "$(findstring -pg,$(_c_flags))" = "-pg" ]; then \ + $(sub_cmd_record_mcount) \ + fi; +endif + +define rule_cc_o_c + $(call echo-cmd,checksrc) $(cmd_checksrc) \ + $(call echo-cmd,cc_o_c) $(cmd_cc_o_c); \ + $(cmd_modversions) \ + $(call echo-cmd,record_mcount) \ + $(cmd_record_mcount) \ + scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,cc_o_c)' > \ + $(dot-target).tmp; \ + rm -f $(depfile); \ + mv -f $(dot-target).tmp $(dot-target).cmd +endef + +# Built-in and composite module parts +$(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) + +# Single-part modules are special since we need to mark them in $(MODVERDIR) + +$(single-used-m): $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) + @{ echo $(@:.o=.ko); echo $@; } > $(MODVERDIR)/$(@F:.o=.mod) + +quiet_cmd_cc_lst_c = MKLST $@ + cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \ + $(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \ + System.map $(OBJDUMP) > $@ + +$(obj)/%.lst: $(src)/%.c FORCE + $(call if_changed_dep,cc_lst_c) + +# Compile assembler sources (.S) +# --------------------------------------------------------------------------- + +modkern_aflags := $(KBUILD_AFLAGS_KERNEL) $(AFLAGS_KERNEL) + +$(real-objs-m) : modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE) +$(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE) + +quiet_cmd_as_s_S = CPP $(quiet_modtag) $@ +cmd_as_s_S = $(CPP) $(a_flags) -o $@ $< + +$(obj)/%.s: $(src)/%.S FORCE + $(call if_changed_dep,as_s_S) + +quiet_cmd_as_o_S = AS $(quiet_modtag) $@ +cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $< + +$(obj)/%.o: $(src)/%.S FORCE + $(call if_changed_dep,as_o_S) + +targets += $(real-objs-y) $(real-objs-m) $(lib-y) +targets += $(extra-y) $(MAKECMDGOALS) $(always) + +# Linker scripts preprocessor (.lds.S -> .lds) +# --------------------------------------------------------------------------- +quiet_cmd_cpp_lds_S = LDS $@ + cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \ + -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< + +$(obj)/%.lds: $(src)/%.lds.S FORCE + $(call if_changed_dep,cpp_lds_S) + +# ASN.1 grammar +# --------------------------------------------------------------------------- +quiet_cmd_asn1_compiler = ASN.1 $@ + cmd_asn1_compiler = $(objtree)/scripts/asn1_compiler $< \ + $(subst .h,.c,$@) $(subst .c,.h,$@) + +.PRECIOUS: $(objtree)/$(obj)/%-asn1.c $(objtree)/$(obj)/%-asn1.h + +$(obj)/%-asn1.c $(obj)/%-asn1.h: $(src)/%.asn1 $(objtree)/scripts/asn1_compiler + $(call cmd,asn1_compiler) + +# Build the compiled-in targets +# --------------------------------------------------------------------------- + +# To build objects in subdirs, we need to descend into the directories +$(sort $(subdir-obj-y)): $(subdir-ym) ; + +# +# Rule to compile a set of .o files into one .o file +# +ifdef builtin-target +quiet_cmd_link_o_target = LD $@ +# If the list of objects to link is empty, just create an empty built-in.o +cmd_link_o_target = $(if $(strip $(obj-y)),\ + $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \ + $(cmd_secanalysis),\ + rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@) + +$(builtin-target): $(obj-y) FORCE + $(call if_changed,link_o_target) + +targets += $(builtin-target) +endif # builtin-target + +# +# Rule to create modules.order file +# +# Create commands to either record .ko file or cat modules.order from +# a subdirectory +modorder-cmds = \ + $(foreach m, $(modorder), \ + $(if $(filter %/modules.order, $m), \ + cat $m;, echo kernel/$m;)) + +$(modorder-target): $(subdir-ym) FORCE + $(Q)(cat /dev/null; $(modorder-cmds)) > $@ + +# +# Rule to compile a set of .o files into one .a file +# +ifdef lib-target +quiet_cmd_link_l_target = AR $@ +cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y) + +$(lib-target): $(lib-y) FORCE + $(call if_changed,link_l_target) + +targets += $(lib-target) +endif + +# +# Rule to link composite objects +# +# Composite objects are specified in kbuild makefile as follows: +# -objs := +# or +# -y := +link_multi_deps = \ +$(filter $(addprefix $(obj)/, \ +$($(subst $(obj)/,,$(@:.o=-objs))) \ +$($(subst $(obj)/,,$(@:.o=-y)))), $^) + +quiet_cmd_link_multi-y = LD $@ +cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalysis) + +quiet_cmd_link_multi-m = LD [M] $@ +cmd_link_multi-m = $(cmd_link_multi-y) + +$(multi-used-y): FORCE + $(call if_changed,link_multi-y) +$(call multi_depend, $(multi-used-y), .o, -objs -y) + +$(multi-used-m): FORCE + $(call if_changed,link_multi-m) + @{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod) +$(call multi_depend, $(multi-used-m), .o, -objs -y) + +targets += $(multi-used-y) $(multi-used-m) + + +# Descending +# --------------------------------------------------------------------------- + +PHONY += $(subdir-ym) +$(subdir-ym): + $(Q)$(MAKE) $(build)=$@ + +# Add FORCE to the prequisites of a target to force it to be always rebuilt. +# --------------------------------------------------------------------------- + +PHONY += FORCE + +FORCE: + +# Read all saved command lines and dependencies for the $(targets) we +# may be building above, using $(if_changed{,_dep}). As an +# optimization, we don't need to read them if the target does not +# exist, we will rebuild anyway in that case. + +targets := $(wildcard $(sort $(targets))) +cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + include $(cmd_files) +endif + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable se we can use it in if_changed and friends. + +.PHONY: $(PHONY) diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean new file mode 100644 index 0000000000..21e1f21531 --- /dev/null +++ b/scripts/Makefile.clean @@ -0,0 +1,107 @@ +# ========================================================================== +# Cleaning up +# ========================================================================== + +src := $(obj) + +PHONY := __clean +__clean: + +# Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir +# Usage: +# $(Q)$(MAKE) $(clean)=dir +clean := -f $(srctree)/scripts/Makefile.clean obj + +# The filename Kbuild has precedence over Makefile +kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) +include $(if $(wildcard $(kbuild-dir)/Kbuild), $(kbuild-dir)/Kbuild, $(kbuild-dir)/Makefile) + +# Figure out what we need to build from the various variables +# ========================================================================== + +__subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y))) +subdir-y += $(__subdir-y) +__subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m))) +subdir-m += $(__subdir-m) +__subdir- := $(patsubst %/,%,$(filter %/, $(obj-))) +subdir- += $(__subdir-) + +# Subdirectories we need to descend into + +subdir-ym := $(sort $(subdir-y) $(subdir-m)) +subdir-ymn := $(sort $(subdir-ym) $(subdir-)) + +# Add subdir path + +subdir-ymn := $(addprefix $(obj)/,$(subdir-ymn)) + +# Temporal work-around for U-Boot + +subdir-ymn := $(foreach f, $(subdir-ymn), \ + $(if $(wildcard $(srctree)/$f/Makefile),$f)) + +# build a list of files to remove, usually relative to the current +# directory + +__clean-files := $(extra-y) $(extra-m) $(extra-) \ + $(always) $(targets) $(clean-files) \ + $(host-progs) \ + $(hostprogs-y) $(hostprogs-m) $(hostprogs-) + +__clean-files := $(filter-out $(no-clean-files), $(__clean-files)) + +# as clean-files is given relative to the current directory, this adds +# a $(obj) prefix, except for absolute paths + +__clean-files := $(wildcard \ + $(addprefix $(obj)/, $(filter-out /%, $(__clean-files))) \ + $(filter /%, $(__clean-files))) + +# as clean-dirs is given relative to the current directory, this adds +# a $(obj) prefix, except for absolute paths + +__clean-dirs := $(wildcard \ + $(addprefix $(obj)/, $(filter-out /%, $(clean-dirs))) \ + $(filter /%, $(clean-dirs))) + +# ========================================================================== + +quiet_cmd_clean = CLEAN $(obj) + cmd_clean = rm -f $(__clean-files) +quiet_cmd_cleandir = CLEAN $(__clean-dirs) + cmd_cleandir = rm -rf $(__clean-dirs) + + +__clean: $(subdir-ymn) +ifneq ($(strip $(__clean-files)),) + +$(call cmd,clean) +endif +ifneq ($(strip $(__clean-dirs)),) + +$(call cmd,cleandir) +endif +ifneq ($(strip $(clean-rule)),) + +$(clean-rule) +endif + @: + + +# =========================================================================== +# Generic stuff +# =========================================================================== + +# Descending +# --------------------------------------------------------------------------- + +PHONY += $(subdir-ymn) +$(subdir-ymn): + $(Q)$(MAKE) $(clean)=$@ + +# If quiet is set, only print short version of command + +cmd = @$(if $($(quiet)cmd_$(1)),echo ' $($(quiet)cmd_$(1))' &&) $(cmd_$(1)) + + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable se we can use it in if_changed and friends. + +.PHONY: $(PHONY) diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn new file mode 100644 index 0000000000..0ec0d24b1c --- /dev/null +++ b/scripts/Makefile.extrawarn @@ -0,0 +1,57 @@ +# ========================================================================== +# +# make W=... settings +# +# W=1 - warnings that may be relevant and does not occur too often +# W=2 - warnings that occur quite often but may still be relevant +# W=3 - the more obscure warnings, can most likely be ignored +# +# $(call cc-option, -W...) handles gcc -W.. options which +# are not supported by all versions of the compiler +# ========================================================================== + +ifeq ("$(origin W)", "command line") + export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W) +endif + +ifdef KBUILD_ENABLE_EXTRA_GCC_CHECKS +warning- := $(empty) + +warning-1 := -Wextra -Wunused -Wno-unused-parameter +warning-1 += -Wmissing-declarations +warning-1 += -Wmissing-format-attribute +warning-1 += $(call cc-option, -Wmissing-prototypes) +warning-1 += -Wold-style-definition +warning-1 += $(call cc-option, -Wmissing-include-dirs) +warning-1 += $(call cc-option, -Wunused-but-set-variable) +warning-1 += $(call cc-disable-warning, missing-field-initializers) + +warning-2 := -Waggregate-return +warning-2 += -Wcast-align +warning-2 += -Wdisabled-optimization +warning-2 += -Wnested-externs +warning-2 += -Wshadow +warning-2 += $(call cc-option, -Wlogical-op) +warning-2 += $(call cc-option, -Wmissing-field-initializers) + +warning-3 := -Wbad-function-cast +warning-3 += -Wcast-qual +warning-3 += -Wconversion +warning-3 += -Wpacked +warning-3 += -Wpadded +warning-3 += -Wpointer-arith +warning-3 += -Wredundant-decls +warning-3 += -Wswitch-default +warning-3 += $(call cc-option, -Wpacked-bitfield-compat) +warning-3 += $(call cc-option, -Wvla) + +warning := $(warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) +warning += $(warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) +warning += $(warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) + +ifeq ("$(strip $(warning))","") + $(error W=$(KBUILD_ENABLE_EXTRA_GCC_CHECKS) is unknown) +endif + +KBUILD_CFLAGS += $(warning) +endif diff --git a/scripts/Makefile.host b/scripts/Makefile.host new file mode 100644 index 0000000000..133edfae5b --- /dev/null +++ b/scripts/Makefile.host @@ -0,0 +1,128 @@ +# ========================================================================== +# Building binaries on the host system +# Binaries are used during the compilation of the kernel, for example +# to preprocess a data file. +# +# Both C and C++ are supported, but preferred language is C for such utilities. +# +# Sample syntax (see Documentation/kbuild/makefiles.txt for reference) +# hostprogs-y := bin2hex +# Will compile bin2hex.c and create an executable named bin2hex +# +# hostprogs-y := lxdialog +# lxdialog-objs := checklist.o lxdialog.o +# Will compile lxdialog.c and checklist.c, and then link the executable +# lxdialog, based on checklist.o and lxdialog.o +# +# hostprogs-y := qconf +# qconf-cxxobjs := qconf.o +# qconf-objs := menu.o +# Will compile qconf as a C++ program, and menu as a C program. +# They are linked as C++ code to the executable qconf + +__hostprogs := $(sort $(hostprogs-y) $(hostprogs-m)) + +# C code +# Executables compiled from a single .c file +host-csingle := $(foreach m,$(__hostprogs), \ + $(if $($(m)-objs)$($(m)-cxxobjs),,$(m))) + +# C executables linked based on several .o files +host-cmulti := $(foreach m,$(__hostprogs),\ + $(if $($(m)-cxxobjs),,$(if $($(m)-objs),$(m)))) + +# Object (.o) files compiled from .c files +host-cobjs := $(sort $(foreach m,$(__hostprogs),$($(m)-objs))) + +# C++ code +# C++ executables compiled from at least one .cc file +# and zero or more .c files +host-cxxmulti := $(foreach m,$(__hostprogs),$(if $($(m)-cxxobjs),$(m))) + +# C++ Object (.o) files compiled from .cc files +host-cxxobjs := $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs))) + +# output directory for programs/.o files +# hostprogs-y := tools/build may have been specified. +# Retrieve also directory of .o files from prog-objs or prog-cxxobjs notation +host-objdirs := $(dir $(__hostprogs) $(host-cobjs) $(host-cxxobjs)) + +host-objdirs := $(strip $(sort $(filter-out ./,$(host-objdirs)))) + + +__hostprogs := $(addprefix $(obj)/,$(__hostprogs)) +host-csingle := $(addprefix $(obj)/,$(host-csingle)) +host-cmulti := $(addprefix $(obj)/,$(host-cmulti)) +host-cobjs := $(addprefix $(obj)/,$(host-cobjs)) +host-cxxmulti := $(addprefix $(obj)/,$(host-cxxmulti)) +host-cxxobjs := $(addprefix $(obj)/,$(host-cxxobjs)) +host-objdirs := $(addprefix $(obj)/,$(host-objdirs)) + +obj-dirs += $(host-objdirs) + +##### +# Handle options to gcc. Support building with separate output directory + +_hostc_flags = $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) \ + $(HOSTCFLAGS_$(basetarget).o) +_hostcxx_flags = $(HOSTCXXFLAGS) $(HOST_EXTRACXXFLAGS) \ + $(HOSTCXXFLAGS_$(basetarget).o) + +ifeq ($(KBUILD_SRC),) +__hostc_flags = $(_hostc_flags) +__hostcxx_flags = $(_hostcxx_flags) +else +__hostc_flags = -I$(obj) $(call flags,_hostc_flags) +__hostcxx_flags = -I$(obj) $(call flags,_hostcxx_flags) +endif + +hostc_flags = -Wp,-MD,$(depfile) $(__hostc_flags) +hostcxx_flags = -Wp,-MD,$(depfile) $(__hostcxx_flags) + +##### +# Compile programs on the host + +# Create executable from a single .c file +# host-csingle -> Executable +quiet_cmd_host-csingle = HOSTCC $@ + cmd_host-csingle = $(HOSTCC) $(hostc_flags) -o $@ $< \ + $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) +$(host-csingle): $(obj)/%: $(src)/%.c FORCE + $(call if_changed_dep,host-csingle) + +# Link an executable based on list of .o files, all plain c +# host-cmulti -> executable +quiet_cmd_host-cmulti = HOSTLD $@ + cmd_host-cmulti = $(HOSTCC) $(HOSTLDFLAGS) -o $@ \ + $(addprefix $(obj)/,$($(@F)-objs)) \ + $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) +$(host-cmulti): FORCE + $(call if_changed,host-cmulti) +$(call multi_depend, $(host-cmulti), , -objs) + +# Create .o file from a single .c file +# host-cobjs -> .o +quiet_cmd_host-cobjs = HOSTCC $@ + cmd_host-cobjs = $(HOSTCC) $(hostc_flags) -c -o $@ $< +$(host-cobjs): $(obj)/%.o: $(src)/%.c FORCE + $(call if_changed_dep,host-cobjs) + +# Link an executable based on list of .o files, a mixture of .c and .cc +# host-cxxmulti -> executable +quiet_cmd_host-cxxmulti = HOSTLD $@ + cmd_host-cxxmulti = $(HOSTCXX) $(HOSTLDFLAGS) -o $@ \ + $(foreach o,objs cxxobjs,\ + $(addprefix $(obj)/,$($(@F)-$(o)))) \ + $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) +$(host-cxxmulti): FORCE + $(call if_changed,host-cxxmulti) +$(call multi_depend, $(host-cxxmulti), , -objs -cxxobjs) + +# Create .o file from a single .cc (C++) file +quiet_cmd_host-cxxobjs = HOSTCXX $@ + cmd_host-cxxobjs = $(HOSTCXX) $(hostcxx_flags) -c -o $@ $< +$(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE + $(call if_changed_dep,host-cxxobjs) + +targets += $(host-csingle) $(host-cmulti) $(host-cobjs)\ + $(host-cxxmulti) $(host-cxxobjs) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib new file mode 100644 index 0000000000..13af604e5f --- /dev/null +++ b/scripts/Makefile.lib @@ -0,0 +1,401 @@ +# Backward compatibility +asflags-y += $(EXTRA_AFLAGS) +ccflags-y += $(EXTRA_CFLAGS) +cppflags-y += $(EXTRA_CPPFLAGS) +ldflags-y += $(EXTRA_LDFLAGS) + +# +# flags that take effect in sub directories +export KBUILD_SUBDIR_ASFLAGS := $(KBUILD_SUBDIR_ASFLAGS) $(subdir-asflags-y) +export KBUILD_SUBDIR_CCFLAGS := $(KBUILD_SUBDIR_CCFLAGS) $(subdir-ccflags-y) + +# Figure out what we need to build from the various variables +# =========================================================================== + +# When an object is listed to be built compiled-in and modular, +# only build the compiled-in version + +obj-m := $(filter-out $(obj-y),$(obj-m)) + +# Libraries are always collected in one lib file. +# Filter out objects already built-in + +lib-y := $(filter-out $(obj-y), $(sort $(lib-y) $(lib-m))) + + +# Handle objects in subdirs +# --------------------------------------------------------------------------- +# o if we encounter foo/ in $(obj-y), replace it by foo/built-in.o +# and add the directory to the list of dirs to descend into: $(subdir-y) +# o if we encounter foo/ in $(obj-m), remove it from $(obj-m) +# and add the directory to the list of dirs to descend into: $(subdir-m) + +# Determine modorder. +# Unfortunately, we don't have information about ordering between -y +# and -m subdirs. Just put -y's first. +modorder := $(patsubst %/,%/modules.order, $(filter %/, $(obj-y)) $(obj-m:.o=.ko)) + +__subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y))) +subdir-y += $(__subdir-y) +__subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m))) +subdir-m += $(__subdir-m) +obj-y := $(patsubst %/, %/built-in.o, $(obj-y)) +obj-m := $(filter-out %/, $(obj-m)) + +# Subdirectories we need to descend into + +subdir-ym := $(sort $(subdir-y) $(subdir-m)) + +# if $(foo-objs) exists, foo.o is a composite object +multi-used-y := $(sort $(foreach m,$(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m)))) +multi-used-m := $(sort $(foreach m,$(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m)))) +multi-used := $(multi-used-y) $(multi-used-m) +single-used-m := $(sort $(filter-out $(multi-used-m),$(obj-m))) + +# Build list of the parts of our composite objects, our composite +# objects depend on those (obviously) +multi-objs-y := $(foreach m, $(multi-used-y), $($(m:.o=-objs)) $($(m:.o=-y))) +multi-objs-m := $(foreach m, $(multi-used-m), $($(m:.o=-objs)) $($(m:.o=-y))) +multi-objs := $(multi-objs-y) $(multi-objs-m) + +# $(subdir-obj-y) is the list of objects in $(obj-y) which uses dir/ to +# tell kbuild to descend +subdir-obj-y := $(filter %/built-in.o, $(obj-y)) + +# $(obj-dirs) is a list of directories that contain object files +obj-dirs := $(dir $(multi-objs) $(obj-y)) + +# Replace multi-part objects by their individual parts, look at local dir only +real-objs-y := $(foreach m, $(filter-out $(subdir-obj-y), $(obj-y)), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m))) $(extra-y) +real-objs-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m))) + +# Add subdir path + +extra-y := $(addprefix $(obj)/,$(extra-y)) +always := $(addprefix $(obj)/,$(always)) +targets := $(addprefix $(obj)/,$(targets)) +modorder := $(addprefix $(obj)/,$(modorder)) +obj-y := $(addprefix $(obj)/,$(obj-y)) +obj-m := $(addprefix $(obj)/,$(obj-m)) +lib-y := $(addprefix $(obj)/,$(lib-y)) +subdir-obj-y := $(addprefix $(obj)/,$(subdir-obj-y)) +real-objs-y := $(addprefix $(obj)/,$(real-objs-y)) +real-objs-m := $(addprefix $(obj)/,$(real-objs-m)) +single-used-m := $(addprefix $(obj)/,$(single-used-m)) +multi-used-y := $(addprefix $(obj)/,$(multi-used-y)) +multi-used-m := $(addprefix $(obj)/,$(multi-used-m)) +multi-objs-y := $(addprefix $(obj)/,$(multi-objs-y)) +multi-objs-m := $(addprefix $(obj)/,$(multi-objs-m)) +subdir-ym := $(addprefix $(obj)/,$(subdir-ym)) +obj-dirs := $(addprefix $(obj)/,$(obj-dirs)) + +# These flags are needed for modversions and compiling, so we define them here +# already +# $(modname_flags) #defines KBUILD_MODNAME as the name of the module it will +# end up in (or would, if it gets compiled in) +# Note: Files that end up in two or more modules are compiled without the +# KBUILD_MODNAME definition. The reason is that any made-up name would +# differ in different configs. +name-fix = $(subst $(comma),_,$(subst -,_,$1)) +basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))" +modname_flags = $(if $(filter 1,$(words $(modname))),\ + -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))") + +orig_c_flags = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \ + $(ccflags-y) $(CFLAGS_$(basetarget).o) +_c_flags = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(orig_c_flags)) +_a_flags = $(KBUILD_CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \ + $(asflags-y) $(AFLAGS_$(basetarget).o) +_cpp_flags = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F)) + +# +# Enable gcov profiling flags for a file, directory or for all files depending +# on variables GCOV_PROFILE_obj.o, GCOV_PROFILE and CONFIG_GCOV_PROFILE_ALL +# (in this order) +# +ifeq ($(CONFIG_GCOV_KERNEL),y) +_c_flags += $(if $(patsubst n%,, \ + $(GCOV_PROFILE_$(basetarget).o)$(GCOV_PROFILE)$(CONFIG_GCOV_PROFILE_ALL)), \ + $(CFLAGS_GCOV)) +endif + +# If building the kernel in a separate objtree expand all occurrences +# of -Idir to -I$(srctree)/dir except for absolute paths (starting with '/'). + +ifeq ($(KBUILD_SRC),) +__c_flags = $(_c_flags) +__a_flags = $(_a_flags) +__cpp_flags = $(_cpp_flags) +else + +# -I$(obj) locates generated .h files +# $(call addtree,-I$(obj)) locates .h files in srctree, from generated .c files +# and locates generated .h files +# FIXME: Replace both with specific CFLAGS* statements in the makefiles +__c_flags = $(call addtree,-I$(obj)) $(call flags,_c_flags) +__a_flags = $(call flags,_a_flags) +__cpp_flags = $(call flags,_cpp_flags) +endif + +# Modified for U-Boot: LINUXINCLUDE -> UBOOTINCLUDE +c_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ + $(__c_flags) $(modkern_cflags) \ + -D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags) + +a_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ + $(__a_flags) $(modkern_aflags) + +cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ + $(__cpp_flags) + +ld_flags = $(LDFLAGS) $(ldflags-y) + +# Modified for U-Boot +dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \ + -I$(srctree)/arch/$(ARCH)/dts \ + -I$(srctree)/arch/$(ARCH)/dts/include \ + -undef -D__DTS__ + +# Finds the multi-part object the current object will be linked into +modname-multi = $(sort $(foreach m,$(multi-used),\ + $(if $(filter $(subst $(obj)/,,$*.o), $($(m:.o=-objs)) $($(m:.o=-y))),$(m:.o=)))) + +# Useful for describing the dependency of composite objects +# Usage: +# $(call multi_depend, multi_used_targets, suffix_to_remove, suffix_to_add) +define multi_depend +$(foreach m, $(notdir $1), \ + $(eval $(obj)/$m: \ + $(addprefix $(obj)/, $(foreach s, $3, $($(m:%$(strip $2)=%$(s))))))) +endef + +ifdef REGENERATE_PARSERS + +# GPERF +# --------------------------------------------------------------------------- +quiet_cmd_gperf = GPERF $@ + cmd_gperf = gperf -t --output-file $@ -a -C -E -g -k 1,3,$$ -p -t $< + +.PRECIOUS: $(src)/%.hash.c_shipped +$(src)/%.hash.c_shipped: $(src)/%.gperf + $(call cmd,gperf) + +# LEX +# --------------------------------------------------------------------------- +LEX_PREFIX = $(if $(LEX_PREFIX_${baseprereq}),$(LEX_PREFIX_${baseprereq}),yy) + +quiet_cmd_flex = LEX $@ + cmd_flex = flex -o$@ -L -P $(LEX_PREFIX) $< + +.PRECIOUS: $(src)/%.lex.c_shipped +$(src)/%.lex.c_shipped: $(src)/%.l + $(call cmd,flex) + +# YACC +# --------------------------------------------------------------------------- +YACC_PREFIX = $(if $(YACC_PREFIX_${baseprereq}),$(YACC_PREFIX_${baseprereq}),yy) + +quiet_cmd_bison = YACC $@ + cmd_bison = bison -o$@ -t -l -p $(YACC_PREFIX) $< + +.PRECIOUS: $(src)/%.tab.c_shipped +$(src)/%.tab.c_shipped: $(src)/%.y + $(call cmd,bison) + +quiet_cmd_bison_h = YACC $@ + cmd_bison_h = bison -o/dev/null --defines=$@ -t -l -p $(YACC_PREFIX) $< + +.PRECIOUS: $(src)/%.tab.h_shipped +$(src)/%.tab.h_shipped: $(src)/%.y + $(call cmd,bison_h) + +endif + +# Shipped files +# =========================================================================== + +quiet_cmd_shipped = SHIPPED $@ +cmd_shipped = cat $< > $@ + +$(obj)/%: $(src)/%_shipped + $(call cmd,shipped) + +# Commands useful for building a boot image +# =========================================================================== +# +# Use as following: +# +# target: source(s) FORCE +# $(if_changed,ld/objcopy/gzip) +# +# and add target to extra-y so that we know we have to +# read in the saved command line + +# Linking +# --------------------------------------------------------------------------- + +quiet_cmd_ld = LD $@ +cmd_ld = $(LD) $(LDFLAGS) $(ldflags-y) $(LDFLAGS_$(@F)) \ + $(filter-out FORCE,$^) -o $@ + +# Objcopy +# --------------------------------------------------------------------------- + +quiet_cmd_objcopy = OBJCOPY $@ +cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ + +# Gzip +# --------------------------------------------------------------------------- + +quiet_cmd_gzip = GZIP $@ +cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \ + (rm -f $@ ; false) + +# DTC +# --------------------------------------------------------------------------- + +# Generate an assembly file to wrap the output of the device tree compiler +quiet_cmd_dt_S_dtb= DTB $@ +# Modified for U-Boot +cmd_dt_S_dtb= \ +( \ + echo '.section .dtb.init.rodata,"a"'; \ + echo '.balign 16'; \ + echo '.global __dtb_$(*F)_begin'; \ + echo '__dtb_$(*F)_begin:'; \ + echo '.incbin "$<" '; \ + echo '__dtb_$(*F)_end:'; \ + echo '.global __dtb_$(*F)_end'; \ + echo '.balign 16'; \ +) > $@ + +$(obj)/%.dtb.S: $(obj)/%.dtb + $(call cmd,dt_S_dtb) + +quiet_cmd_dtc = DTC $@ +# Modified for U-Boot +cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ + dtc -O dtb -o $@ -b 0 \ + -i $(dir $<) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) + +$(obj)/%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + +dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + +# Helper targets for Installing DTBs into the boot directory +quiet_cmd_dtb_install = INSTALL $< + cmd_dtb_install = cp $< $(2) + +_dtbinst_pre_: + $(Q)if [ -d $(INSTALL_DTBS_PATH).old ]; then rm -rf $(INSTALL_DTBS_PATH).old; fi + $(Q)if [ -d $(INSTALL_DTBS_PATH) ]; then mv $(INSTALL_DTBS_PATH) $(INSTALL_DTBS_PATH).old; fi + $(Q)mkdir -p $(INSTALL_DTBS_PATH) + +%.dtb_dtbinst_: $(obj)/%.dtb _dtbinst_pre_ + $(call cmd,dtb_install,$(INSTALL_DTBS_PATH)) + +# Bzip2 +# --------------------------------------------------------------------------- + +# Bzip2 and LZMA do not include size in file... so we have to fake that; +# append the size as a 32-bit littleendian number as gzip does. +size_append = printf $(shell \ +dec_size=0; \ +for F in $1; do \ + fsize=$$(stat -c "%s" $$F); \ + dec_size=$$(expr $$dec_size + $$fsize); \ +done; \ +printf "%08x\n" $$dec_size | \ + sed 's/\(..\)/\1 /g' | { \ + read ch0 ch1 ch2 ch3; \ + for ch in $$ch3 $$ch2 $$ch1 $$ch0; do \ + printf '%s%03o' '\\' $$((0x$$ch)); \ + done; \ + } \ +) + +quiet_cmd_bzip2 = BZIP2 $@ +cmd_bzip2 = (cat $(filter-out FORCE,$^) | \ + bzip2 -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +# Lzma +# --------------------------------------------------------------------------- + +quiet_cmd_lzma = LZMA $@ +cmd_lzma = (cat $(filter-out FORCE,$^) | \ + lzma -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +quiet_cmd_lzo = LZO $@ +cmd_lzo = (cat $(filter-out FORCE,$^) | \ + lzop -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +quiet_cmd_lz4 = LZ4 $@ +cmd_lz4 = (cat $(filter-out FORCE,$^) | \ + lz4c -l -c1 stdin stdout && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +# U-Boot mkimage +# --------------------------------------------------------------------------- + +MKIMAGE := $(srctree)/scripts/mkuboot.sh + +# SRCARCH just happens to match slightly more than ARCH (on sparc), so reduces +# the number of overrides in arch makefiles +UIMAGE_ARCH ?= $(SRCARCH) +UIMAGE_COMPRESSION ?= $(if $(2),$(2),none) +UIMAGE_OPTS-y ?= +UIMAGE_TYPE ?= kernel +UIMAGE_LOADADDR ?= arch_must_set_this +UIMAGE_ENTRYADDR ?= $(UIMAGE_LOADADDR) +UIMAGE_NAME ?= 'Linux-$(KERNELRELEASE)' +UIMAGE_IN ?= $< +UIMAGE_OUT ?= $@ + +quiet_cmd_uimage = UIMAGE $(UIMAGE_OUT) + cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(UIMAGE_ARCH) -O linux \ + -C $(UIMAGE_COMPRESSION) $(UIMAGE_OPTS-y) \ + -T $(UIMAGE_TYPE) \ + -a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \ + -n $(UIMAGE_NAME) -d $(UIMAGE_IN) $(UIMAGE_OUT) + +# XZ +# --------------------------------------------------------------------------- +# Use xzkern to compress the kernel image and xzmisc to compress other things. +# +# xzkern uses a big LZMA2 dictionary since it doesn't increase memory usage +# of the kernel decompressor. A BCJ filter is used if it is available for +# the target architecture. xzkern also appends uncompressed size of the data +# using size_append. The .xz format has the size information available at +# the end of the file too, but it's in more complex format and it's good to +# avoid changing the part of the boot code that reads the uncompressed size. +# Note that the bytes added by size_append will make the xz tool think that +# the file is corrupt. This is expected. +# +# xzmisc doesn't use size_append, so it can be used to create normal .xz +# files. xzmisc uses smaller LZMA2 dictionary than xzkern, because a very +# big dictionary would increase the memory usage too much in the multi-call +# decompression mode. A BCJ filter isn't used either. +quiet_cmd_xzkern = XZKERN $@ +cmd_xzkern = (cat $(filter-out FORCE,$^) | \ + sh $(srctree)/scripts/xz_wrap.sh && \ + $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + +quiet_cmd_xzmisc = XZMISC $@ +cmd_xzmisc = (cat $(filter-out FORCE,$^) | \ + xz --check=crc32 --lzma2=dict=1MiB) > $@ || \ + (rm -f $@ ; false) + +# Additional commands for U-Boot +# +# mkimage +# --------------------------------------------------------------------------- +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl new file mode 100644 index 0000000000..ecf3037cb8 --- /dev/null +++ b/scripts/Makefile.spl @@ -0,0 +1,236 @@ +# +# (C) Copyright 2000-2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2011 +# Daniel Schwierzeck, daniel.schwierzeck@googlemail.com. +# +# (C) Copyright 2011 +# Texas Instruments Incorporated - http://www.ti.com/ +# Aneesh V +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Based on top-level Makefile. +# + +src := $(obj) + +# Create output directory if not already present +_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) + +include $(srctree)/scripts/Kbuild.include + +UBOOTINCLUDE := -I$(obj)/include $(UBOOTINCLUDE) + +-include $(obj)/include/config/auto.conf +-include $(obj)/include/autoconf.mk + +ifeq ($(CONFIG_TPL_BUILD),y) +export CONFIG_TPL_BUILD +SPL_BIN := u-boot-tpl +else +SPL_BIN := u-boot-spl +endif + +include $(srctree)/config.mk +include $(srctree)/arch/$(ARCH)/Makefile + +# Enable garbage collection of un-used sections for SPL +KBUILD_CFLAGS += -ffunction-sections -fdata-sections +LDFLAGS_FINAL += --gc-sections + +# FIX ME +cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \ + $(NOSTDINC_FLAGS) + +HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n) + +libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/) +libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ + +libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/ +libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ +libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ +libs-$(CONFIG_SPL_DM) += drivers/core/ +libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/ +libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/ +libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ +libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/ +libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/ +libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/ +libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/ +libs-y += fs/ +libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ +libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/ +libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/ +libs-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/ +libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/ +libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/ +libs-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/ +libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ +libs-$(CONFIG_SPL_NET_SUPPORT) += net/ +libs-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/ +libs-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/ +libs-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/ +libs-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/ +libs-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/ +libs-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/ +libs-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/ +libs-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/ +libs-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/ + +head-y := $(addprefix $(obj)/,$(head-y)) +libs-y := $(addprefix $(obj)/,$(libs-y)) +u-boot-spl-dirs := $(patsubst %/,%,$(filter %/, $(libs-y))) + +libs-y := $(patsubst %/, %/built-in.o, $(libs-y)) + +# Add GCC lib +ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) +PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a +PLATFORM_LIBS := $(filter-out %/lib.a, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC) +endif + +u-boot-spl-init := $(head-y) +u-boot-spl-main := $(libs-y) + +# Linker Script +ifdef CONFIG_SPL_LDSCRIPT +# need to strip off double quotes +LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%)) +endif + +ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-spl.lds +endif +ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-spl.lds +endif +ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot-spl.lds +endif +ifeq ($(wildcard $(LDSCRIPT)),) +$(error could not find linker script) +endif + +# Special flags for CPP when processing the linker script. +# Pass the version down so we can handle backwards compatibility +# on the fly. +LDPPFLAGS += \ + -include $(srctree)/include/u-boot/u-boot.lds.h \ + -include $(objtree)/include/config.h \ + -DCPUDIR=$(CPUDIR) \ + $(shell $(LD) --version | \ + sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') + +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE) + +MKIMAGEFLAGS_MLO.byteswap = -T omapimage -n byteswap -a $(CONFIG_SPL_TEXT_BASE) + +MLO MLO.byteswap: $(obj)/u-boot-spl.bin + $(call if_changed,mkimage) + +MKIMAGEFLAGS_boot.bin = -T atmelimage + +ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y) +MKIMAGEFLAGS_boot.bin += -n $(shell $(obj)/../tools/atmel_pmecc_params) + +boot.bin: $(obj)/../tools/atmel_pmecc_params +endif + +boot.bin: $(obj)/u-boot-spl.bin + $(call if_changed,mkimage) + +ALL-y += $(obj)/$(SPL_BIN).bin + +ifdef CONFIG_SAMSUNG +ALL-y += $(obj)/$(BOARD)-spl.bin +endif + +ifdef CONFIG_SUNXI +ifndef CONFIG_SPL_FEL +ALL-y += $(obj)/sunxi-spl.bin +endif +endif + +ifeq ($(CONFIG_SYS_SOC),"at91") +ALL-y += boot.bin +endif + +all: $(ALL-y) + +ifdef CONFIG_SAMSUNG +ifdef CONFIG_VAR_SIZE_SPL +VAR_SIZE_PARAM = --vs +else +VAR_SIZE_PARAM = +endif +$(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin + $(if $(wildcard $(objtree)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl),\ + $(objtree)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl,\ + $(objtree)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@ +endif + +quiet_cmd_objcopy = OBJCOPY $@ +cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ + +OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJCFLAGS) -O binary + +$(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE + $(call if_changed,objcopy) + +LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL) +ifneq ($(CONFIG_SPL_TEXT_BASE),) +LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) +endif + +ifdef CONFIG_SUNXI +quiet_cmd_mksunxiboot = MKSUNXI $@ +cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@ +$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin + $(call if_changed,mksunxiboot) +endif + +quiet_cmd_u-boot-spl = LD $@ + cmd_u-boot-spl = (cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ + $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \ + $(patsubst $(obj)/%,%,$(u-boot-spl-main)) --end-group \ + $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN)) + +$(obj)/$(SPL_BIN): $(u-boot-spl-init) $(u-boot-spl-main) $(obj)/u-boot-spl.lds FORCE + $(call if_changed,u-boot-spl) + +$(sort $(u-boot-spl-init) $(u-boot-spl-main)): $(u-boot-spl-dirs) ; + +PHONY += $(u-boot-spl-dirs) +$(u-boot-spl-dirs): + $(Q)$(MAKE) $(build)=$@ + +quiet_cmd_cpp_lds = LDS $@ +cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ + -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $< + +$(obj)/u-boot-spl.lds: $(LDSCRIPT) FORCE + $(call if_changed_dep,cpp_lds) + +# read all saved command lines + +targets := $(wildcard $(sort $(targets))) +cmd_files := $(wildcard $(obj)/.*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + $(cmd_files): ; # Do not try to update included dependency files + include $(cmd_files) +endif + +PHONY += FORCE +FORCE: + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable so we can use it in if_changed and friends. +.PHONY: $(PHONY) diff --git a/scripts/basic/.gitignore b/scripts/basic/.gitignore new file mode 100644 index 0000000000..a776371a35 --- /dev/null +++ b/scripts/basic/.gitignore @@ -0,0 +1 @@ +fixdep diff --git a/scripts/basic/Makefile b/scripts/basic/Makefile new file mode 100644 index 0000000000..4fcef87bb8 --- /dev/null +++ b/scripts/basic/Makefile @@ -0,0 +1,15 @@ +### +# Makefile.basic lists the most basic programs used during the build process. +# The programs listed herein are what are needed to do the basic stuff, +# such as fix file dependencies. +# This initial step is needed to avoid files to be recompiled +# when kernel configuration changes (which is what happens when +# .config is included by main Makefile. +# --------------------------------------------------------------------------- +# fixdep: Used to generate dependency information during build process + +hostprogs-y := fixdep +always := $(hostprogs-y) + +# fixdep is needed to compile other host programs +$(addprefix $(obj)/,$(filter-out fixdep,$(always))): $(obj)/fixdep diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c new file mode 100644 index 0000000000..1a41723823 --- /dev/null +++ b/scripts/basic/fixdep.c @@ -0,0 +1,466 @@ +/* + * "Optimize" a list of dependencies as spit out by gcc -MD + * for the kernel build + * =========================================================================== + * + * Author Kai Germaschewski + * Copyright 2002 by Kai Germaschewski + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by reference. + * + * + * Introduction: + * + * gcc produces a very nice and correct list of dependencies which + * tells make when to remake a file. + * + * To use this list as-is however has the drawback that virtually + * every file in the kernel includes autoconf.h. + * + * If the user re-runs make *config, autoconf.h will be + * regenerated. make notices that and will rebuild every file which + * includes autoconf.h, i.e. basically all files. This is extremely + * annoying if the user just changed CONFIG_HIS_DRIVER from n to m. + * + * So we play the same trick that "mkdep" played before. We replace + * the dependency on autoconf.h by a dependency on every config + * option which is mentioned in any of the listed prequisites. + * + * kconfig populates a tree in include/config/ with an empty file + * for each config symbol and when the configuration is updated + * the files representing changed config options are touched + * which then let make pick up the changes and the files that use + * the config symbols are rebuilt. + * + * So if the user changes his CONFIG_HIS_DRIVER option, only the objects + * which depend on "include/linux/config/his/driver.h" will be rebuilt, + * so most likely only his driver ;-) + * + * The idea above dates, by the way, back to Michael E Chastain, AFAIK. + * + * So to get dependencies right, there are two issues: + * o if any of the files the compiler read changed, we need to rebuild + * o if the command line given to the compile the file changed, we + * better rebuild as well. + * + * The former is handled by using the -MD output, the later by saving + * the command line used to compile the old object and comparing it + * to the one we would now use. + * + * Again, also this idea is pretty old and has been discussed on + * kbuild-devel a long time ago. I don't have a sensibly working + * internet connection right now, so I rather don't mention names + * without double checking. + * + * This code here has been based partially based on mkdep.c, which + * says the following about its history: + * + * Copyright abandoned, Michael Chastain, . + * This is a C version of syncdep.pl by Werner Almesberger. + * + * + * It is invoked as + * + * fixdep + * + * and will read the dependency file + * + * The transformed dependency snipped is written to stdout. + * + * It first generates a line + * + * cmd_ = + * + * and then basically copies the ..d file to stdout, in the + * process filtering out the dependency on autoconf.h and adding + * dependencies on include/config/my/option.h for every + * CONFIG_MY_OPTION encountered in any of the prequisites. + * + * It will also filter out all the dependencies on *.ver. We need + * to make sure that the generated version checksum are globally up + * to date before even starting the recursive build, so it's too late + * at this point anyway. + * + * The algorithm to grep for "CONFIG_..." is bit unusual, but should + * be fast ;-) We don't even try to really parse the header files, but + * merely grep, i.e. if CONFIG_FOO is mentioned in a comment, it will + * be picked up as well. It's not a problem with respect to + * correctness, since that can only give too many dependencies, thus + * we cannot miss a rebuild. Since people tend to not mention totally + * unrelated CONFIG_ options all over the place, it's not an + * efficiency problem either. + * + * (Note: it'd be easy to port over the complete mkdep state machine, + * but I don't think the added complexity is worth it) + */ +/* + * Note 2: if somebody writes HELLO_CONFIG_BOOM in a file, it will depend onto + * CONFIG_BOOM. This could seem a bug (not too hard to fix), but please do not + * fix it! Some UserModeLinux files (look at arch/um/) call CONFIG_BOOM as + * UML_CONFIG_BOOM, to avoid conflicts with /usr/include/linux/autoconf.h, + * through arch/um/include/uml-config.h; this fixdep "bug" makes sure that + * those files will have correct dependencies. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INT_CONF ntohl(0x434f4e46) +#define INT_ONFI ntohl(0x4f4e4649) +#define INT_NFIG ntohl(0x4e464947) +#define INT_FIG_ ntohl(0x4649475f) + +char *target; +char *depfile; +char *cmdline; + +static void usage(void) +{ + fprintf(stderr, "Usage: fixdep \n"); + exit(1); +} + +/* + * Print out the commandline prefixed with cmd_ := + */ +static void print_cmdline(void) +{ + printf("cmd_%s := %s\n\n", target, cmdline); +} + +struct item { + struct item *next; + unsigned int len; + unsigned int hash; + char name[0]; +}; + +#define HASHSZ 256 +static struct item *hashtab[HASHSZ]; + +static unsigned int strhash(const char *str, unsigned int sz) +{ + /* fnv32 hash */ + unsigned int i, hash = 2166136261U; + + for (i = 0; i < sz; i++) + hash = (hash ^ str[i]) * 0x01000193; + return hash; +} + +/* + * Lookup a value in the configuration string. + */ +static int is_defined_config(const char *name, int len, unsigned int hash) +{ + struct item *aux; + + for (aux = hashtab[hash % HASHSZ]; aux; aux = aux->next) { + if (aux->hash == hash && aux->len == len && + memcmp(aux->name, name, len) == 0) + return 1; + } + return 0; +} + +/* + * Add a new value to the configuration string. + */ +static void define_config(const char *name, int len, unsigned int hash) +{ + struct item *aux = malloc(sizeof(*aux) + len); + + if (!aux) { + perror("fixdep:malloc"); + exit(1); + } + memcpy(aux->name, name, len); + aux->len = len; + aux->hash = hash; + aux->next = hashtab[hash % HASHSZ]; + hashtab[hash % HASHSZ] = aux; +} + +/* + * Clear the set of configuration strings. + */ +static void clear_config(void) +{ + struct item *aux, *next; + unsigned int i; + + for (i = 0; i < HASHSZ; i++) { + for (aux = hashtab[i]; aux; aux = next) { + next = aux->next; + free(aux); + } + hashtab[i] = NULL; + } +} + +/* + * Record the use of a CONFIG_* word. + */ +static void use_config(const char *m, int slen) +{ + unsigned int hash = strhash(m, slen); + int c, i; + + if (is_defined_config(m, slen, hash)) + return; + + define_config(m, slen, hash); + + /* printf(" $(wildcard include/config/"); */ + /* modified for U-Boot */ + printf(" $(wildcard %sinclude/config/", + strncmp(depfile, "spl/", 4) ? + (strncmp(depfile, "tpl/", 4) ? "" : "tpl/") : "spl/"); + for (i = 0; i < slen; i++) { + c = m[i]; + if (c == '_') + c = '/'; + else + c = tolower(c); + putchar(c); + } + printf(".h) \\\n"); +} + +static void parse_config_file(const char *map, size_t len) +{ + const int *end = (const int *) (map + len); + /* start at +1, so that p can never be < map */ + const int *m = (const int *) map + 1; + const char *p, *q; + + for (; m < end; m++) { + if (*m == INT_CONF) { p = (char *) m ; goto conf; } + if (*m == INT_ONFI) { p = (char *) m-1; goto conf; } + if (*m == INT_NFIG) { p = (char *) m-2; goto conf; } + if (*m == INT_FIG_) { p = (char *) m-3; goto conf; } + continue; + conf: + if (p > map + len - 7) + continue; + if (memcmp(p, "CONFIG_", 7)) + continue; + for (q = p + 7; q < map + len; q++) { + if (!(isalnum(*q) || *q == '_')) + goto found; + } + continue; + + found: + if (!memcmp(q - 7, "_MODULE", 7)) + q -= 7; + if( (q-p-7) < 0 ) + continue; + use_config(p+7, q-p-7); + } +} + +/* test is s ends in sub */ +static int strrcmp(char *s, char *sub) +{ + int slen = strlen(s); + int sublen = strlen(sub); + + if (sublen > slen) + return 1; + + return memcmp(s + slen - sublen, sub, sublen); +} + +static void do_config_file(const char *filename) +{ + struct stat st; + int fd; + void *map; + + fd = open(filename, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "fixdep: error opening config file: "); + perror(filename); + exit(2); + } + fstat(fd, &st); + if (st.st_size == 0) { + close(fd); + return; + } + map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0); + if ((long) map == -1) { + perror("fixdep: mmap"); + close(fd); + return; + } + + parse_config_file(map, st.st_size); + + munmap(map, st.st_size); + + close(fd); +} + +/* + * Important: The below generated source_foo.o and deps_foo.o variable + * assignments are parsed not only by make, but also by the rather simple + * parser in scripts/mod/sumversion.c. + */ +static void parse_dep_file(void *map, size_t len) +{ + char *m = map; + char *end = m + len; + char *p; + char s[PATH_MAX]; + int is_target; + int saw_any_target = 0; + int is_first_dep = 0; + + clear_config(); + + while (m < end) { + /* Skip any "white space" */ + while (m < end && (*m == ' ' || *m == '\\' || *m == '\n')) + m++; + /* Find next "white space" */ + p = m; + while (p < end && *p != ' ' && *p != '\\' && *p != '\n') + p++; + /* Is the token we found a target name? */ + is_target = (*(p-1) == ':'); + /* Don't write any target names into the dependency file */ + if (is_target) { + /* The /next/ file is the first dependency */ + is_first_dep = 1; + } else { + /* Save this token/filename */ + memcpy(s, m, p-m); + s[p - m] = 0; + + /* Ignore certain dependencies */ + if (strrcmp(s, "include/generated/autoconf.h") && + strrcmp(s, "arch/um/include/uml-config.h") && + strrcmp(s, "include/linux/kconfig.h") && + strrcmp(s, ".ver")) { + /* + * Do not list the source file as dependency, + * so that kbuild is not confused if a .c file + * is rewritten into .S or vice versa. Storing + * it in source_* is needed for modpost to + * compute srcversions. + */ + if (is_first_dep) { + /* + * If processing the concatenation of + * multiple dependency files, only + * process the first target name, which + * will be the original source name, + * and ignore any other target names, + * which will be intermediate temporary + * files. + */ + if (!saw_any_target) { + saw_any_target = 1; + printf("source_%s := %s\n\n", + target, s); + printf("deps_%s := \\\n", + target); + } + is_first_dep = 0; + } else + printf(" %s \\\n", s); + do_config_file(s); + } + } + /* + * Start searching for next token immediately after the first + * "whitespace" character that follows this token. + */ + m = p + 1; + } + + if (!saw_any_target) { + fprintf(stderr, "fixdep: parse error; no targets found\n"); + exit(1); + } + + printf("\n%s: $(deps_%s)\n\n", target, target); + printf("$(deps_%s):\n", target); +} + +static void print_deps(void) +{ + struct stat st; + int fd; + void *map; + + fd = open(depfile, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "fixdep: error opening depfile: "); + perror(depfile); + exit(2); + } + if (fstat(fd, &st) < 0) { + fprintf(stderr, "fixdep: error fstat'ing depfile: "); + perror(depfile); + exit(2); + } + if (st.st_size == 0) { + fprintf(stderr,"fixdep: %s is empty\n",depfile); + close(fd); + return; + } + map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0); + if ((long) map == -1) { + perror("fixdep: mmap"); + close(fd); + return; + } + + parse_dep_file(map, st.st_size); + + munmap(map, st.st_size); + + close(fd); +} + +static void traps(void) +{ + static char test[] __attribute__((aligned(sizeof(int)))) = "CONF"; + int *p = (int *)test; + + if (*p != INT_CONF) { + fprintf(stderr, "fixdep: sizeof(int) != 4 or wrong endianness? %#x\n", + *p); + exit(2); + } +} + +int main(int argc, char *argv[]) +{ + traps(); + + if (argc != 4) + usage(); + + depfile = argv[1]; + target = argv[2]; + cmdline = argv[3]; + + print_cmdline(); + print_deps(); + + return 0; +} diff --git a/scripts/binutils-version.sh b/scripts/binutils-version.sh new file mode 100755 index 0000000000..a34368184f --- /dev/null +++ b/scripts/binutils-version.sh @@ -0,0 +1,23 @@ +#!/bin/sh +# +# binutils-version [-p] gas-command +# +# Prints the binutils version of `gas-command' in a canonical 4-digit form +# such as `0222' for binutils 2.22 +# + +gas="$*" + +if [ ${#gas} -eq 0 ]; then + echo "Error: No assembler specified." + printf "Usage:\n\t$0 \n" + exit 1 +fi + +version_string=$($gas --version | head -1 | \ + sed -e 's/(.*)//; s/[^0-9.]*\([0-9.]*\).*/\1/') + +MAJOR=$(echo $version_string | cut -d . -f 1) +MINOR=$(echo $version_string | cut -d . -f 2) + +printf "%02d%02d\\n" $MAJOR $MINOR diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl new file mode 100755 index 0000000000..74db2e24fc --- /dev/null +++ b/scripts/checkpatch.pl @@ -0,0 +1,4573 @@ +#!/usr/bin/perl -w +# (c) 2001, Dave Jones. (the file handling bit) +# (c) 2005, Joel Schopp (the ugly bit) +# (c) 2007,2008, Andy Whitcroft (new conditions, test suite) +# (c) 2008-2010 Andy Whitcroft +# Licensed under the terms of the GNU GPL License version 2 + +use strict; +use POSIX; + +my $P = $0; +$P =~ s@.*/@@g; + +my $V = '0.32'; + +use Getopt::Long qw(:config no_auto_abbrev); + +my $quiet = 0; +my $tree = 1; +my $chk_signoff = 1; +my $chk_patch = 1; +my $tst_only; +my $emacs = 0; +my $terse = 0; +my $file = 0; +my $check = 0; +my $summary = 1; +my $mailback = 0; +my $summary_file = 0; +my $show_types = 0; +my $fix = 0; +my $fix_inplace = 0; +my $root; +my %debug; +my %camelcase = (); +my %use_type = (); +my @use = (); +my %ignore_type = (); +my @ignore = (); +my $help = 0; +my $configuration_file = ".checkpatch.conf"; +my $max_line_length = 80; +my $ignore_perl_version = 0; +my $minimum_perl_version = 5.10.0; + +sub help { + my ($exitcode) = @_; + + print << "EOM"; +Usage: $P [OPTION]... [FILE]... +Version: $V + +Options: + -q, --quiet quiet + --no-tree run without a kernel tree + --no-signoff do not check for 'Signed-off-by' line + --patch treat FILE as patchfile (default) + --emacs emacs compile window format + --terse one line per report + -f, --file treat FILE as regular source file + --subjective, --strict enable more subjective tests + --types TYPE(,TYPE2...) show only these comma separated message types + --ignore TYPE(,TYPE2...) ignore various comma separated message types + --max-line-length=n set the maximum line length, if exceeded, warn + --show-types show the message "types" in the output + --root=PATH PATH to the kernel tree root + --no-summary suppress the per-file summary + --mailback only produce a report in case of warnings/errors + --summary-file include the filename in summary + --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of + 'values', 'possible', 'type', and 'attr' (default + is all off) + --test-only=WORD report only warnings/errors containing WORD + literally + --fix EXPERIMENTAL - may create horrible results + If correctable single-line errors exist, create + ".EXPERIMENTAL-checkpatch-fixes" + with potential errors corrected to the preferred + checkpatch style + --fix-inplace EXPERIMENTAL - may create horrible results + Is the same as --fix, but overwrites the input + file. It's your fault if there's no backup or git + --ignore-perl-version override checking of perl version. expect + runtime errors. + -h, --help, --version display this help and exit + +When FILE is - read standard input. +EOM + + exit($exitcode); +} + +my $conf = which_conf($configuration_file); +if (-f $conf) { + my @conf_args; + open(my $conffile, '<', "$conf") + or warn "$P: Can't find a readable $configuration_file file $!\n"; + + while (<$conffile>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + $line =~ s/\s+/ /g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + + my @words = split(" ", $line); + foreach my $word (@words) { + last if ($word =~ m/^#/); + push (@conf_args, $word); + } + } + close($conffile); + unshift(@ARGV, @conf_args) if @conf_args; +} + +GetOptions( + 'q|quiet+' => \$quiet, + 'tree!' => \$tree, + 'signoff!' => \$chk_signoff, + 'patch!' => \$chk_patch, + 'emacs!' => \$emacs, + 'terse!' => \$terse, + 'f|file!' => \$file, + 'subjective!' => \$check, + 'strict!' => \$check, + 'ignore=s' => \@ignore, + 'types=s' => \@use, + 'show-types!' => \$show_types, + 'max-line-length=i' => \$max_line_length, + 'root=s' => \$root, + 'summary!' => \$summary, + 'mailback!' => \$mailback, + 'summary-file!' => \$summary_file, + 'fix!' => \$fix, + 'fix-inplace!' => \$fix_inplace, + 'ignore-perl-version!' => \$ignore_perl_version, + 'debug=s' => \%debug, + 'test-only=s' => \$tst_only, + 'h|help' => \$help, + 'version' => \$help +) or help(1); + +help(0) if ($help); + +$fix = 1 if ($fix_inplace); + +my $exit = 0; + +if ($^V && $^V lt $minimum_perl_version) { + printf "$P: requires at least perl version %vd\n", $minimum_perl_version; + if (!$ignore_perl_version) { + exit(1); + } +} + +if ($#ARGV < 0) { + print "$P: no input files\n"; + exit(1); +} + +sub hash_save_array_words { + my ($hashRef, $arrayRef) = @_; + + my @array = split(/,/, join(',', @$arrayRef)); + foreach my $word (@array) { + $word =~ s/\s*\n?$//g; + $word =~ s/^\s*//g; + $word =~ s/\s+/ /g; + $word =~ tr/[a-z]/[A-Z]/; + + next if ($word =~ m/^\s*#/); + next if ($word =~ m/^\s*$/); + + $hashRef->{$word}++; + } +} + +sub hash_show_words { + my ($hashRef, $prefix) = @_; + + if ($quiet == 0 && keys %$hashRef) { + print "NOTE: $prefix message types:"; + foreach my $word (sort keys %$hashRef) { + print " $word"; + } + print "\n\n"; + } +} + +hash_save_array_words(\%ignore_type, \@ignore); +hash_save_array_words(\%use_type, \@use); + +my $dbg_values = 0; +my $dbg_possible = 0; +my $dbg_type = 0; +my $dbg_attr = 0; +for my $key (keys %debug) { + ## no critic + eval "\${dbg_$key} = '$debug{$key}';"; + die "$@" if ($@); +} + +my $rpt_cleaners = 0; + +if ($terse) { + $emacs = 1; + $quiet++; +} + +if ($tree) { + if (defined $root) { + if (!top_of_kernel_tree($root)) { + die "$P: $root: --root does not point at a valid tree\n"; + } + } else { + if (top_of_kernel_tree('.')) { + $root = '.'; + } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ && + top_of_kernel_tree($1)) { + $root = $1; + } + } + + if (!defined $root) { + print "Must be run from the top-level dir. of a kernel tree\n"; + exit(2); + } +} + +my $emitted_corrupt = 0; + +our $Ident = qr{ + [A-Za-z_][A-Za-z\d_]* + (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)* + }x; +our $Storage = qr{extern|static|asmlinkage}; +our $Sparse = qr{ + __user| + __kernel| + __force| + __iomem| + __must_check| + __init_refok| + __kprobes| + __ref| + __rcu + }x; +our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)}; +our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)}; +our $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\b)}; +our $InitAttributeInit = qr{$InitAttributePrefix(?:init\b)}; +our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit}; + +# Notes to $Attribute: +# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check +our $Attribute = qr{ + const| + __percpu| + __nocast| + __safe| + __bitwise__| + __packed__| + __packed2__| + __naked| + __maybe_unused| + __always_unused| + __noreturn| + __used| + __cold| + __noclone| + __deprecated| + __read_mostly| + __kprobes| + $InitAttribute| + ____cacheline_aligned| + ____cacheline_aligned_in_smp| + ____cacheline_internodealigned_in_smp| + __weak + }x; +our $Modifier; +our $Inline = qr{inline|__always_inline|noinline}; +our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; +our $Lval = qr{$Ident(?:$Member)*}; + +our $Int_type = qr{(?i)llu|ull|ll|lu|ul|l|u}; +our $Binary = qr{(?i)0b[01]+$Int_type?}; +our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?}; +our $Int = qr{[0-9]+$Int_type?}; +our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; +our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; +our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; +our $Float = qr{$Float_hex|$Float_dec|$Float_int}; +our $Constant = qr{$Float|$Binary|$Hex|$Int}; +our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; +our $Compare = qr{<=|>=|==|!=|<|>}; +our $Arithmetic = qr{\+|-|\*|\/|%}; +our $Operators = qr{ + <=|>=|==|!=| + =>|->|<<|>>|<|>|!|~| + &&|\|\||,|\^|\+\+|--|&|\||$Arithmetic + }x; + +our $NonptrType; +our $NonptrTypeWithAttr; +our $Type; +our $Declare; + +our $NON_ASCII_UTF8 = qr{ + [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte + | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs + | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte + | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates + | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3 + | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15 + | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 +}x; + +our $UTF8 = qr{ + [\x09\x0A\x0D\x20-\x7E] # ASCII + | $NON_ASCII_UTF8 +}x; + +our $typeTypedefs = qr{(?x: + (?:__)?(?:u|s|be|le)(?:8|16|32|64)| + atomic_t +)}; + +our $logFunctions = qr{(?x: + printk(?:_ratelimited|_once|)| + (?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| + WARN(?:_RATELIMIT|_ONCE|)| + panic| + debug| + printf| + puts| + MODULE_[A-Z_]+| + seq_vprintf|seq_printf|seq_puts +)}; + +our $signature_tags = qr{(?xi: + Signed-off-by:| + Acked-by:| + Tested-by:| + Reviewed-by:| + Reported-by:| + Suggested-by:| + To:| + Cc: +)}; + +our @typeList = ( + qr{void}, + qr{(?:unsigned\s+)?char}, + qr{(?:unsigned\s+)?short}, + qr{(?:unsigned\s+)?int}, + qr{(?:unsigned\s+)?long}, + qr{(?:unsigned\s+)?long\s+int}, + qr{(?:unsigned\s+)?long\s+long}, + qr{(?:unsigned\s+)?long\s+long\s+int}, + qr{unsigned}, + qr{float}, + qr{double}, + qr{bool}, + qr{struct\s+$Ident}, + qr{union\s+$Ident}, + qr{enum\s+$Ident}, + qr{${Ident}_t}, + qr{${Ident}_handler}, + qr{${Ident}_handler_fn}, +); +our @typeListWithAttr = ( + @typeList, + qr{struct\s+$InitAttribute\s+$Ident}, + qr{union\s+$InitAttribute\s+$Ident}, +); + +our @modifierList = ( + qr{fastcall}, +); + +our $allowed_asm_includes = qr{(?x: + irq| + memory +)}; +# memory.h: ARM has a custom one + +sub build_types { + my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; + my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; + my $allWithAttr = "(?x: \n" . join("|\n ", @typeListWithAttr) . "\n)"; + $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; + $NonptrType = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\([^\)]*\)| + (?:$typeTypedefs\b)| + (?:${all}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $NonptrTypeWithAttr = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\([^\)]*\)| + (?:$typeTypedefs\b)| + (?:${allWithAttr}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $Type = qr{ + $NonptrType + (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)? + (?:\s+$Inline|\s+$Modifier)* + }x; + $Declare = qr{(?:$Storage\s+)?$Type}; +} +build_types(); + +our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; + +# Using $balanced_parens, $LvalOrFunc, or $FuncArg +# requires at least perl version v5.10.0 +# Any use must be runtime checked with $^V + +our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; +our $LvalOrFunc = qr{($Lval)\s*($balanced_parens{0,1})\s*}; +our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)}; + +sub deparenthesize { + my ($string) = @_; + return "" if (!defined($string)); + $string =~ s@^\s*\(\s*@@g; + $string =~ s@\s*\)\s*$@@g; + $string =~ s@\s+@ @g; + return $string; +} + +sub seed_camelcase_file { + my ($file) = @_; + + return if (!(-f $file)); + + local $/; + + open(my $include_file, '<', "$file") + or warn "$P: Can't read '$file' $!\n"; + my $text = <$include_file>; + close($include_file); + + my @lines = split('\n', $text); + + foreach my $line (@lines) { + next if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/); + if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[\(\[,;]/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[;\{]/) { + $camelcase{$1} = 1; + } + } +} + +my $camelcase_seeded = 0; +sub seed_camelcase_includes { + return if ($camelcase_seeded); + + my $files; + my $camelcase_cache = ""; + my @include_files = (); + + $camelcase_seeded = 1; + + if (-e ".git") { + my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`; + chomp $git_last_include_commit; + $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit"; + } else { + my $last_mod_date = 0; + $files = `find $root/include -name "*.h"`; + @include_files = split('\n', $files); + foreach my $file (@include_files) { + my $date = POSIX::strftime("%Y%m%d%H%M", + localtime((stat $file)[9])); + $last_mod_date = $date if ($last_mod_date < $date); + } + $camelcase_cache = ".checkpatch-camelcase.date.$last_mod_date"; + } + + if ($camelcase_cache ne "" && -f $camelcase_cache) { + open(my $camelcase_file, '<', "$camelcase_cache") + or warn "$P: Can't read '$camelcase_cache' $!\n"; + while (<$camelcase_file>) { + chomp; + $camelcase{$_} = 1; + } + close($camelcase_file); + + return; + } + + if (-e ".git") { + $files = `git ls-files "include/*.h"`; + @include_files = split('\n', $files); + } + + foreach my $file (@include_files) { + seed_camelcase_file($file); + } + + if ($camelcase_cache ne "") { + unlink glob ".checkpatch-camelcase.*"; + open(my $camelcase_file, '>', "$camelcase_cache") + or warn "$P: Can't write '$camelcase_cache' $!\n"; + foreach (sort { lc($a) cmp lc($b) } keys(%camelcase)) { + print $camelcase_file ("$_\n"); + } + close($camelcase_file); + } +} + +$chk_signoff = 0 if ($file); + +my @rawlines = (); +my @lines = (); +my @fixed = (); +my $vname; +for my $filename (@ARGV) { + my $FILE; + if ($file) { + open($FILE, '-|', "diff -u /dev/null $filename") || + die "$P: $filename: diff failed - $!\n"; + } elsif ($filename eq '-') { + open($FILE, '<&STDIN'); + } else { + open($FILE, '<', "$filename") || + die "$P: $filename: open failed - $!\n"; + } + if ($filename eq '-') { + $vname = 'Your patch'; + } else { + $vname = $filename; + } + while (<$FILE>) { + chomp; + push(@rawlines, $_); + } + close($FILE); + if (!process($filename)) { + $exit = 1; + } + @rawlines = (); + @lines = (); + @fixed = (); +} + +exit($exit); + +sub top_of_kernel_tree { + my ($root) = @_; + + my @tree_check = ( + "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", + "README", "Documentation", "arch", "include", "drivers", + "fs", "init", "ipc", "kernel", "lib", "scripts", + ); + + foreach my $check (@tree_check) { + if (! -e $root . '/' . $check) { + return 0; + } + } + return 1; +} + +sub parse_email { + my ($formatted_email) = @_; + + my $name = ""; + my $address = ""; + my $comment = ""; + + if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) { + $name = $1; + $address = $2; + $comment = $3 if defined $3; + } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) { + $address = $1; + $comment = $2 if defined $2; + } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { + $address = $1; + $comment = $2 if defined $2; + $formatted_email =~ s/$address.*$//; + $name = $formatted_email; + $name = trim($name); + $name =~ s/^\"|\"$//g; + # If there's a name left after stripping spaces and + # leading quotes, and the address doesn't have both + # leading and trailing angle brackets, the address + # is invalid. ie: + # "joe smith joe@smith.com" bad + # "joe smith ]+>$/) { + $name = ""; + $address = ""; + $comment = ""; + } + } + + $name = trim($name); + $name =~ s/^\"|\"$//g; + $address = trim($address); + $address =~ s/^\<|\>$//g; + + if ($name =~ /[^\w \-]/i) { ##has "must quote" chars + $name =~ s/(?"; + } + + return $formatted_email; +} + +sub which_conf { + my ($conf) = @_; + + foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { + if (-e "$path/$conf") { + return "$path/$conf"; + } + } + + return ""; +} + +sub expand_tabs { + my ($str) = @_; + + my $res = ''; + my $n = 0; + for my $c (split(//, $str)) { + if ($c eq "\t") { + $res .= ' '; + $n++; + for (; ($n % 8) != 0; $n++) { + $res .= ' '; + } + next; + } + $res .= $c; + $n++; + } + + return $res; +} +sub copy_spacing { + (my $res = shift) =~ tr/\t/ /c; + return $res; +} + +sub line_stats { + my ($line) = @_; + + # Drop the diff line leader and expand tabs + $line =~ s/^.//; + $line = expand_tabs($line); + + # Pick the indent from the front of the line. + my ($white) = ($line =~ /^(\s*)/); + + return (length($line), length($white)); +} + +my $sanitise_quote = ''; + +sub sanitise_line_reset { + my ($in_comment) = @_; + + if ($in_comment) { + $sanitise_quote = '*/'; + } else { + $sanitise_quote = ''; + } +} +sub sanitise_line { + my ($line) = @_; + + my $res = ''; + my $l = ''; + + my $qlen = 0; + my $off = 0; + my $c; + + # Always copy over the diff marker. + $res = substr($line, 0, 1); + + for ($off = 1; $off < length($line); $off++) { + $c = substr($line, $off, 1); + + # Comments we are wacking completly including the begin + # and end, all to $;. + if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { + $sanitise_quote = '*/'; + + substr($res, $off, 2, "$;$;"); + $off++; + next; + } + if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') { + $sanitise_quote = ''; + substr($res, $off, 2, "$;$;"); + $off++; + next; + } + if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') { + $sanitise_quote = '//'; + + substr($res, $off, 2, $sanitise_quote); + $off++; + next; + } + + # A \ in a string means ignore the next character. + if (($sanitise_quote eq "'" || $sanitise_quote eq '"') && + $c eq "\\") { + substr($res, $off, 2, 'XX'); + $off++; + next; + } + # Regular quotes. + if ($c eq "'" || $c eq '"') { + if ($sanitise_quote eq '') { + $sanitise_quote = $c; + + substr($res, $off, 1, $c); + next; + } elsif ($sanitise_quote eq $c) { + $sanitise_quote = ''; + } + } + + #print "c<$c> SQ<$sanitise_quote>\n"; + if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") { + substr($res, $off, 1, $;); + } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") { + substr($res, $off, 1, $;); + } elsif ($off != 0 && $sanitise_quote && $c ne "\t") { + substr($res, $off, 1, 'X'); + } else { + substr($res, $off, 1, $c); + } + } + + if ($sanitise_quote eq '//') { + $sanitise_quote = ''; + } + + # The pathname on a #include may be surrounded by '<' and '>'. + if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) { + my $clean = 'X' x length($1); + $res =~ s@\<.*\>@<$clean>@; + + # The whole of a #error is a string. + } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) { + my $clean = 'X' x length($1); + $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; + } + + return $res; +} + +sub get_quoted_string { + my ($line, $rawline) = @_; + + return "" if ($line !~ m/(\"[X]+\")/g); + return substr($rawline, $-[0], $+[0] - $-[0]); +} + +sub ctx_statement_block { + my ($linenr, $remain, $off) = @_; + my $line = $linenr - 1; + my $blk = ''; + my $soff = $off; + my $coff = $off - 1; + my $coff_set = 0; + + my $loff = 0; + + my $type = ''; + my $level = 0; + my @stack = (); + my $p; + my $c; + my $len = 0; + + my $remainder; + while (1) { + @stack = (['', 0]) if ($#stack == -1); + + #warn "CSB: blk<$blk> remain<$remain>\n"; + # If we are about to drop off the end, pull in more + # context. + if ($off >= $len) { + for (; $remain > 0; $line++) { + last if (!defined $lines[$line]); + next if ($lines[$line] =~ /^-/); + $remain--; + $loff = $len; + $blk .= $lines[$line] . "\n"; + $len = length($blk); + $line++; + last; + } + # Bail if there is no further context. + #warn "CSB: blk<$blk> off<$off> len<$len>\n"; + if ($off >= $len) { + last; + } + if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { + $level++; + $type = '#'; + } + } + $p = $c; + $c = substr($blk, $off, 1); + $remainder = substr($blk, $off); + + #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n"; + + # Handle nested #if/#else. + if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) { + push(@stack, [ $type, $level ]); + } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) { + ($type, $level) = @{$stack[$#stack - 1]}; + } elsif ($remainder =~ /^#\s*endif\b/) { + ($type, $level) = @{pop(@stack)}; + } + + # Statement ends at the ';' or a close '}' at the + # outermost level. + if ($level == 0 && $c eq ';') { + last; + } + + # An else is really a conditional as long as its not else if + if ($level == 0 && $coff_set == 0 && + (!defined($p) || $p =~ /(?:\s|\}|\+)/) && + $remainder =~ /^(else)(?:\s|{)/ && + $remainder !~ /^else\s+if\b/) { + $coff = $off + length($1) - 1; + $coff_set = 1; + #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n"; + #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n"; + } + + if (($type eq '' || $type eq '(') && $c eq '(') { + $level++; + $type = '('; + } + if ($type eq '(' && $c eq ')') { + $level--; + $type = ($level != 0)? '(' : ''; + + if ($level == 0 && $coff < $soff) { + $coff = $off; + $coff_set = 1; + #warn "CSB: mark coff<$coff>\n"; + } + } + if (($type eq '' || $type eq '{') && $c eq '{') { + $level++; + $type = '{'; + } + if ($type eq '{' && $c eq '}') { + $level--; + $type = ($level != 0)? '{' : ''; + + if ($level == 0) { + if (substr($blk, $off + 1, 1) eq ';') { + $off++; + } + last; + } + } + # Preprocessor commands end at the newline unless escaped. + if ($type eq '#' && $c eq "\n" && $p ne "\\") { + $level--; + $type = ''; + $off++; + last; + } + $off++; + } + # We are truly at the end, so shuffle to the next line. + if ($off == $len) { + $loff = $len + 1; + $line++; + $remain--; + } + + my $statement = substr($blk, $soff, $off - $soff + 1); + my $condition = substr($blk, $soff, $coff - $soff + 1); + + #warn "STATEMENT<$statement>\n"; + #warn "CONDITION<$condition>\n"; + + #print "coff<$coff> soff<$off> loff<$loff>\n"; + + return ($statement, $condition, + $line, $remain + 1, $off - $loff + 1, $level); +} + +sub statement_lines { + my ($stmt) = @_; + + # Strip the diff line prefixes and rip blank lines at start and end. + $stmt =~ s/(^|\n)./$1/g; + $stmt =~ s/^\s*//; + $stmt =~ s/\s*$//; + + my @stmt_lines = ($stmt =~ /\n/g); + + return $#stmt_lines + 2; +} + +sub statement_rawlines { + my ($stmt) = @_; + + my @stmt_lines = ($stmt =~ /\n/g); + + return $#stmt_lines + 2; +} + +sub statement_block_size { + my ($stmt) = @_; + + $stmt =~ s/(^|\n)./$1/g; + $stmt =~ s/^\s*{//; + $stmt =~ s/}\s*$//; + $stmt =~ s/^\s*//; + $stmt =~ s/\s*$//; + + my @stmt_lines = ($stmt =~ /\n/g); + my @stmt_statements = ($stmt =~ /;/g); + + my $stmt_lines = $#stmt_lines + 2; + my $stmt_statements = $#stmt_statements + 1; + + if ($stmt_lines > $stmt_statements) { + return $stmt_lines; + } else { + return $stmt_statements; + } +} + +sub ctx_statement_full { + my ($linenr, $remain, $off) = @_; + my ($statement, $condition, $level); + + my (@chunks); + + # Grab the first conditional/block pair. + ($statement, $condition, $linenr, $remain, $off, $level) = + ctx_statement_block($linenr, $remain, $off); + #print "F: c<$condition> s<$statement> remain<$remain>\n"; + push(@chunks, [ $condition, $statement ]); + if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) { + return ($level, $linenr, @chunks); + } + + # Pull in the following conditional/block pairs and see if they + # could continue the statement. + for (;;) { + ($statement, $condition, $linenr, $remain, $off, $level) = + ctx_statement_block($linenr, $remain, $off); + #print "C: c<$condition> s<$statement> remain<$remain>\n"; + last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s)); + #print "C: push\n"; + push(@chunks, [ $condition, $statement ]); + } + + return ($level, $linenr, @chunks); +} + +sub ctx_block_get { + my ($linenr, $remain, $outer, $open, $close, $off) = @_; + my $line; + my $start = $linenr - 1; + my $blk = ''; + my @o; + my @c; + my @res = (); + + my $level = 0; + my @stack = ($level); + for ($line = $start; $remain > 0; $line++) { + next if ($rawlines[$line] =~ /^-/); + $remain--; + + $blk .= $rawlines[$line]; + + # Handle nested #if/#else. + if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) { + push(@stack, $level); + } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) { + $level = $stack[$#stack - 1]; + } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) { + $level = pop(@stack); + } + + foreach my $c (split(//, $lines[$line])) { + ##print "C<$c>L<$level><$open$close>O<$off>\n"; + if ($off > 0) { + $off--; + next; + } + + if ($c eq $close && $level > 0) { + $level--; + last if ($level == 0); + } elsif ($c eq $open) { + $level++; + } + } + + if (!$outer || $level <= 1) { + push(@res, $rawlines[$line]); + } + + last if ($level == 0); + } + + return ($level, @res); +} +sub ctx_block_outer { + my ($linenr, $remain) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0); + return @r; +} +sub ctx_block { + my ($linenr, $remain) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0); + return @r; +} +sub ctx_statement { + my ($linenr, $remain, $off) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off); + return @r; +} +sub ctx_block_level { + my ($linenr, $remain) = @_; + + return ctx_block_get($linenr, $remain, 0, '{', '}', 0); +} +sub ctx_statement_level { + my ($linenr, $remain, $off) = @_; + + return ctx_block_get($linenr, $remain, 0, '(', ')', $off); +} + +sub ctx_locate_comment { + my ($first_line, $end_line) = @_; + + # Catch a comment on the end of the line itself. + my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); + return $current_comment if (defined $current_comment); + + # Look through the context and try and figure out if there is a + # comment. + my $in_comment = 0; + $current_comment = ''; + for (my $linenr = $first_line; $linenr < $end_line; $linenr++) { + my $line = $rawlines[$linenr - 1]; + #warn " $line\n"; + if ($linenr == $first_line and $line =~ m@^.\s*\*@) { + $in_comment = 1; + } + if ($line =~ m@/\*@) { + $in_comment = 1; + } + if (!$in_comment && $current_comment ne '') { + $current_comment = ''; + } + $current_comment .= $line . "\n" if ($in_comment); + if ($line =~ m@\*/@) { + $in_comment = 0; + } + } + + chomp($current_comment); + return($current_comment); +} +sub ctx_has_comment { + my ($first_line, $end_line) = @_; + my $cmt = ctx_locate_comment($first_line, $end_line); + + ##print "LINE: $rawlines[$end_line - 1 ]\n"; + ##print "CMMT: $cmt\n"; + + return ($cmt ne ''); +} + +sub raw_line { + my ($linenr, $cnt) = @_; + + my $offset = $linenr - 1; + $cnt++; + + my $line; + while ($cnt) { + $line = $rawlines[$offset++]; + next if (defined($line) && $line =~ /^-/); + $cnt--; + } + + return $line; +} + +sub cat_vet { + my ($vet) = @_; + my ($res, $coded); + + $res = ''; + while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) { + $res .= $1; + if ($2 ne '') { + $coded = sprintf("^%c", unpack('C', $2) + 64); + $res .= $coded; + } + } + $res =~ s/$/\$/; + + return $res; +} + +my $av_preprocessor = 0; +my $av_pending; +my @av_paren_type; +my $av_pend_colon; + +sub annotate_reset { + $av_preprocessor = 0; + $av_pending = '_'; + @av_paren_type = ('E'); + $av_pend_colon = 'O'; +} + +sub annotate_values { + my ($stream, $type) = @_; + + my $res; + my $var = '_' x length($stream); + my $cur = $stream; + + print "$stream\n" if ($dbg_values > 1); + + while (length($cur)) { + @av_paren_type = ('E') if ($#av_paren_type < 0); + print " <" . join('', @av_paren_type) . + "> <$type> <$av_pending>" if ($dbg_values > 1); + if ($cur =~ /^(\s+)/o) { + print "WS($1)\n" if ($dbg_values > 1); + if ($1 =~ /\n/ && $av_preprocessor) { + $type = pop(@av_paren_type); + $av_preprocessor = 0; + } + + } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { + print "CAST($1)\n" if ($dbg_values > 1); + push(@av_paren_type, $type); + $type = 'c'; + + } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { + print "DECLARE($1)\n" if ($dbg_values > 1); + $type = 'T'; + + } elsif ($cur =~ /^($Modifier)\s*/) { + print "MODIFIER($1)\n" if ($dbg_values > 1); + $type = 'T'; + + } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) { + print "DEFINE($1,$2)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + push(@av_paren_type, $type); + if ($2 ne '') { + $av_pending = 'N'; + } + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) { + print "UNDEF($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + push(@av_paren_type, $type); + + } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) { + print "PRE_START($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + + push(@av_paren_type, $type); + push(@av_paren_type, $type); + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) { + print "PRE_RESTART($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + + push(@av_paren_type, $av_paren_type[$#av_paren_type]); + + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:endif))/o) { + print "PRE_END($1)\n" if ($dbg_values > 1); + + $av_preprocessor = 1; + + # Assume all arms of the conditional end as this + # one does, and continue as if the #endif was not here. + pop(@av_paren_type); + push(@av_paren_type, $type); + $type = 'E'; + + } elsif ($cur =~ /^(\\\n)/o) { + print "PRECONT($1)\n" if ($dbg_values > 1); + + } elsif ($cur =~ /^(__attribute__)\s*\(?/o) { + print "ATTR($1)\n" if ($dbg_values > 1); + $av_pending = $type; + $type = 'N'; + + } elsif ($cur =~ /^(sizeof)\s*(\()?/o) { + print "SIZEOF($1)\n" if ($dbg_values > 1); + if (defined $2) { + $av_pending = 'V'; + } + $type = 'N'; + + } elsif ($cur =~ /^(if|while|for)\b/o) { + print "COND($1)\n" if ($dbg_values > 1); + $av_pending = 'E'; + $type = 'N'; + + } elsif ($cur =~/^(case)/o) { + print "CASE($1)\n" if ($dbg_values > 1); + $av_pend_colon = 'C'; + $type = 'N'; + + } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) { + print "KEYWORD($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(\()/o) { + print "PAREN('$1')\n" if ($dbg_values > 1); + push(@av_paren_type, $av_pending); + $av_pending = '_'; + $type = 'N'; + + } elsif ($cur =~ /^(\))/o) { + my $new_type = pop(@av_paren_type); + if ($new_type ne '_') { + $type = $new_type; + print "PAREN('$1') -> $type\n" + if ($dbg_values > 1); + } else { + print "PAREN('$1')\n" if ($dbg_values > 1); + } + + } elsif ($cur =~ /^($Ident)\s*\(/o) { + print "FUNC($1)\n" if ($dbg_values > 1); + $type = 'V'; + $av_pending = 'V'; + + } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) { + if (defined $2 && $type eq 'C' || $type eq 'T') { + $av_pend_colon = 'B'; + } elsif ($type eq 'E') { + $av_pend_colon = 'L'; + } + print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1); + $type = 'V'; + + } elsif ($cur =~ /^($Ident|$Constant)/o) { + print "IDENT($1)\n" if ($dbg_values > 1); + $type = 'V'; + + } elsif ($cur =~ /^($Assignment)/o) { + print "ASSIGN($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~/^(;|{|})/) { + print "END($1)\n" if ($dbg_values > 1); + $type = 'E'; + $av_pend_colon = 'O'; + + } elsif ($cur =~/^(,)/) { + print "COMMA($1)\n" if ($dbg_values > 1); + $type = 'C'; + + } elsif ($cur =~ /^(\?)/o) { + print "QUESTION($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(:)/o) { + print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1); + + substr($var, length($res), 1, $av_pend_colon); + if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') { + $type = 'E'; + } else { + $type = 'N'; + } + $av_pend_colon = 'O'; + + } elsif ($cur =~ /^(\[)/o) { + print "CLOSE($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) { + my $variant; + + print "OPV($1)\n" if ($dbg_values > 1); + if ($type eq 'V') { + $variant = 'B'; + } else { + $variant = 'U'; + } + + substr($var, length($res), 1, $variant); + $type = 'N'; + + } elsif ($cur =~ /^($Operators)/o) { + print "OP($1)\n" if ($dbg_values > 1); + if ($1 ne '++' && $1 ne '--') { + $type = 'N'; + } + + } elsif ($cur =~ /(^.)/o) { + print "C($1)\n" if ($dbg_values > 1); + } + if (defined $1) { + $cur = substr($cur, length($1)); + $res .= $type x length($1); + } + } + + return ($res, $var); +} + +sub possible { + my ($possible, $line) = @_; + my $notPermitted = qr{(?: + ^(?: + $Modifier| + $Storage| + $Type| + DEFINE_\S+ + )$| + ^(?: + goto| + return| + case| + else| + asm|__asm__| + do| + \#| + \#\#| + )(?:\s|$)| + ^(?:typedef|struct|enum)\b + )}x; + warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2); + if ($possible !~ $notPermitted) { + # Check for modifiers. + $possible =~ s/\s*$Storage\s*//g; + $possible =~ s/\s*$Sparse\s*//g; + if ($possible =~ /^\s*$/) { + + } elsif ($possible =~ /\s/) { + $possible =~ s/\s*$Type\s*//g; + for my $modifier (split(' ', $possible)) { + if ($modifier !~ $notPermitted) { + warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); + push(@modifierList, $modifier); + } + } + + } else { + warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); + push(@typeList, $possible); + } + build_types(); + } else { + warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1); + } +} + +my $prefix = ''; + +sub show_type { + return defined $use_type{$_[0]} if (scalar keys %use_type > 0); + + return !defined $ignore_type{$_[0]}; +} + +sub report { + if (!show_type($_[1]) || + (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) { + return 0; + } + my $line; + if ($show_types) { + $line = "$prefix$_[0]:$_[1]: $_[2]\n"; + } else { + $line = "$prefix$_[0]: $_[2]\n"; + } + $line = (split('\n', $line))[0] . "\n" if ($terse); + + push(our @report, $line); + + return 1; +} +sub report_dump { + our @report; +} + +sub ERROR { + if (report("ERROR", $_[0], $_[1])) { + our $clean = 0; + our $cnt_error++; + return 1; + } + return 0; +} +sub WARN { + if (report("WARNING", $_[0], $_[1])) { + our $clean = 0; + our $cnt_warn++; + return 1; + } + return 0; +} +sub CHK { + if ($check && report("CHECK", $_[0], $_[1])) { + our $clean = 0; + our $cnt_chk++; + return 1; + } + return 0; +} + +sub check_absolute_file { + my ($absolute, $herecurr) = @_; + my $file = $absolute; + + ##print "absolute<$absolute>\n"; + + # See if any suffix of this path is a path within the tree. + while ($file =~ s@^[^/]*/@@) { + if (-f "$root/$file") { + ##print "file<$file>\n"; + last; + } + } + if (! -f _) { + return 0; + } + + # It is, so see if the prefix is acceptable. + my $prefix = $absolute; + substr($prefix, -length($file)) = ''; + + ##print "prefix<$prefix>\n"; + if ($prefix ne ".../") { + WARN("USE_RELATIVE_PATH", + "use relative pathname instead of absolute in changelog text\n" . $herecurr); + } +} + +sub trim { + my ($string) = @_; + + $string =~ s/^\s+|\s+$//g; + + return $string; +} + +sub ltrim { + my ($string) = @_; + + $string =~ s/^\s+//; + + return $string; +} + +sub rtrim { + my ($string) = @_; + + $string =~ s/\s+$//; + + return $string; +} + +sub string_find_replace { + my ($string, $find, $replace) = @_; + + $string =~ s/$find/$replace/g; + + return $string; +} + +sub tabify { + my ($leading) = @_; + + my $source_indent = 8; + my $max_spaces_before_tab = $source_indent - 1; + my $spaces_to_tab = " " x $source_indent; + + #convert leading spaces to tabs + 1 while $leading =~ s@^([\t]*)$spaces_to_tab@$1\t@g; + #Remove spaces before a tab + 1 while $leading =~ s@^([\t]*)( {1,$max_spaces_before_tab})\t@$1\t@g; + + return "$leading"; +} + +sub pos_last_openparen { + my ($line) = @_; + + my $pos = 0; + + my $opens = $line =~ tr/\(/\(/; + my $closes = $line =~ tr/\)/\)/; + + my $last_openparen = 0; + + if (($opens == 0) || ($closes >= $opens)) { + return -1; + } + + my $len = length($line); + + for ($pos = 0; $pos < $len; $pos++) { + my $string = substr($line, $pos); + if ($string =~ /^($FuncArg|$balanced_parens)/) { + $pos += length($1) - 1; + } elsif (substr($line, $pos, 1) eq '(') { + $last_openparen = $pos; + } elsif (index($string, '(') == -1) { + last; + } + } + + return $last_openparen + 1; +} + +sub process { + my $filename = shift; + + my $linenr=0; + my $prevline=""; + my $prevrawline=""; + my $stashline=""; + my $stashrawline=""; + + my $length; + my $indent; + my $previndent=0; + my $stashindent=0; + + our $clean = 1; + my $signoff = 0; + my $is_patch = 0; + + my $in_header_lines = 1; + my $in_commit_log = 0; #Scanning lines before patch + + my $non_utf8_charset = 0; + + our @report = (); + our $cnt_lines = 0; + our $cnt_error = 0; + our $cnt_warn = 0; + our $cnt_chk = 0; + + # Trace the real file/line as we go. + my $realfile = ''; + my $realline = 0; + my $realcnt = 0; + my $here = ''; + my $in_comment = 0; + my $comment_edge = 0; + my $first_line = 0; + my $p1_prefix = ''; + + my $prev_values = 'E'; + + # suppression flags + my %suppress_ifbraces; + my %suppress_whiletrailers; + my %suppress_export; + my $suppress_statement = 0; + + my %signatures = (); + + # Pre-scan the patch sanitizing the lines. + # Pre-scan the patch looking for any __setup documentation. + # + my @setup_docs = (); + my $setup_docs = 0; + + my $camelcase_file_seeded = 0; + + sanitise_line_reset(); + my $line; + foreach my $rawline (@rawlines) { + $linenr++; + $line = $rawline; + + push(@fixed, $rawline) if ($fix); + + if ($rawline=~/^\+\+\+\s+(\S+)/) { + $setup_docs = 0; + if ($1 =~ m@Documentation/kernel-parameters.txt$@) { + $setup_docs = 1; + } + #next; + } + if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + $realline=$1-1; + if (defined $2) { + $realcnt=$3+1; + } else { + $realcnt=1+1; + } + $in_comment = 0; + + # Guestimate if this is a continuing comment. Run + # the context looking for a comment "edge". If this + # edge is a close comment then we must be in a comment + # at context start. + my $edge; + my $cnt = $realcnt; + for (my $ln = $linenr + 1; $cnt > 0; $ln++) { + next if (defined $rawlines[$ln - 1] && + $rawlines[$ln - 1] =~ /^-/); + $cnt--; + #print "RAW<$rawlines[$ln - 1]>\n"; + last if (!defined $rawlines[$ln - 1]); + if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ && + $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) { + ($edge) = $1; + last; + } + } + if (defined $edge && $edge eq '*/') { + $in_comment = 1; + } + + # Guestimate if this is a continuing comment. If this + # is the start of a diff block and this line starts + # ' *' then it is very likely a comment. + if (!defined $edge && + $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@) + { + $in_comment = 1; + } + + ##print "COMMENT:$in_comment edge<$edge> $rawline\n"; + sanitise_line_reset($in_comment); + + } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) { + # Standardise the strings and chars within the input to + # simplify matching -- only bother with positive lines. + $line = sanitise_line($rawline); + } + push(@lines, $line); + + if ($realcnt > 1) { + $realcnt-- if ($line =~ /^(?:\+| |$)/); + } else { + $realcnt = 0; + } + + #print "==>$rawline\n"; + #print "-->$line\n"; + + if ($setup_docs && $line =~ /^\+/) { + push(@setup_docs, $line); + } + } + + $prefix = ''; + + $realcnt = 0; + $linenr = 0; + foreach my $line (@lines) { + $linenr++; + my $sline = $line; #copy of $line + $sline =~ s/$;/ /g; #with comments as spaces + + my $rawline = $rawlines[$linenr - 1]; + +#extract the line range in the file after the patch is applied + if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + $is_patch = 1; + $first_line = $linenr + 1; + $realline=$1-1; + if (defined $2) { + $realcnt=$3+1; + } else { + $realcnt=1+1; + } + annotate_reset(); + $prev_values = 'E'; + + %suppress_ifbraces = (); + %suppress_whiletrailers = (); + %suppress_export = (); + $suppress_statement = 0; + next; + +# track the line number as we move through the hunk, note that +# new versions of GNU diff omit the leading space on completely +# blank context lines so we need to count that too. + } elsif ($line =~ /^( |\+|$)/) { + $realline++; + $realcnt-- if ($realcnt != 0); + + # Measure the line length and indent. + ($length, $indent) = line_stats($rawline); + + # Track the previous line. + ($prevline, $stashline) = ($stashline, $line); + ($previndent, $stashindent) = ($stashindent, $indent); + ($prevrawline, $stashrawline) = ($stashrawline, $rawline); + + #warn "line<$line>\n"; + + } elsif ($realcnt == 1) { + $realcnt--; + } + + my $hunk_line = ($realcnt != 0); + +#make up the handle for any error we report on this line + $prefix = "$filename:$realline: " if ($emacs && $file); + $prefix = "$filename:$linenr: " if ($emacs && !$file); + + $here = "#$linenr: " if (!$file); + $here = "#$realline: " if ($file); + + # extract the filename as it passes + if ($line =~ /^diff --git.*?(\S+)$/) { + $realfile = $1; + $realfile =~ s@^([^/]*)/@@ if (!$file); + $in_commit_log = 0; + } elsif ($line =~ /^\+\+\+\s+(\S+)/) { + $realfile = $1; + $realfile =~ s@^([^/]*)/@@ if (!$file); + $in_commit_log = 0; + + $p1_prefix = $1; + if (!$file && $tree && $p1_prefix ne '' && + -e "$root/$p1_prefix") { + WARN("PATCH_PREFIX", + "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n"); + } + + if ($realfile =~ m@^include/asm/@) { + ERROR("MODIFIED_INCLUDE_ASM", + "do not modify files in include/asm, change architecture specific files in include/asm-\n" . "$here$rawline\n"); + } + next; + } + + $here .= "FILE: $realfile:$realline:" if ($realcnt != 0); + + my $hereline = "$here\n$rawline\n"; + my $herecurr = "$here\n$rawline\n"; + my $hereprev = "$here\n$prevrawline\n$rawline\n"; + + $cnt_lines++ if ($realcnt != 0); + +# Check for incorrect file permissions + if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { + my $permhere = $here . "FILE: $realfile\n"; + if ($realfile !~ m@scripts/@ && + $realfile !~ /\.(py|pl|awk|sh)$/) { + ERROR("EXECUTE_PERMISSIONS", + "do not set execute permissions for source files\n" . $permhere); + } + } + +# Check the patch for a signoff: + if ($line =~ /^\s*signed-off-by:/i) { + $signoff++; + $in_commit_log = 0; + } + +# Check signature styles + if (!$in_header_lines && + $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { + my $space_before = $1; + my $sign_off = $2; + my $space_after = $3; + my $email = $4; + my $ucfirst_sign_off = ucfirst(lc($sign_off)); + + if ($sign_off !~ /$signature_tags/) { + WARN("BAD_SIGN_OFF", + "Non-standard signature: $sign_off\n" . $herecurr); + } + if (defined $space_before && $space_before ne "") { + if (WARN("BAD_SIGN_OFF", + "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] = + "$ucfirst_sign_off $email"; + } + } + if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { + if (WARN("BAD_SIGN_OFF", + "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] = + "$ucfirst_sign_off $email"; + } + + } + if (!defined $space_after || $space_after ne " ") { + if (WARN("BAD_SIGN_OFF", + "Use a single space after $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] = + "$ucfirst_sign_off $email"; + } + } + + my ($email_name, $email_address, $comment) = parse_email($email); + my $suggested_email = format_email(($email_name, $email_address)); + if ($suggested_email eq "") { + ERROR("BAD_SIGN_OFF", + "Unrecognized email address: '$email'\n" . $herecurr); + } else { + my $dequoted = $suggested_email; + $dequoted =~ s/^"//; + $dequoted =~ s/" $comment" ne $email && + "$suggested_email$comment" ne $email) { + WARN("BAD_SIGN_OFF", + "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); + } + } + +# Check for duplicate signatures + my $sig_nospace = $line; + $sig_nospace =~ s/\s//g; + $sig_nospace = lc($sig_nospace); + if (defined $signatures{$sig_nospace}) { + WARN("BAD_SIGN_OFF", + "Duplicate signature\n" . $herecurr); + } else { + $signatures{$sig_nospace} = 1; + } + } + +# Check for wrappage within a valid hunk of the file + if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { + ERROR("CORRUPTED_PATCH", + "patch seems to be corrupt (line wrapped?)\n" . + $herecurr) if (!$emitted_corrupt++); + } + +# Check for absolute kernel paths. + if ($tree) { + while ($line =~ m{(?:^|\s)(/\S*)}g) { + my $file = $1; + + if ($file =~ m{^(.*?)(?::\d+)+:?$} && + check_absolute_file($1, $herecurr)) { + # + } else { + check_absolute_file($file, $herecurr); + } + } + } + +# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php + if (($realfile =~ /^$/ || $line =~ /^\+/) && + $rawline !~ m/^$UTF8*$/) { + my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/); + + my $blank = copy_spacing($rawline); + my $ptr = substr($blank, 0, length($utf8_prefix)) . "^"; + my $hereptr = "$hereline$ptr\n"; + + CHK("INVALID_UTF8", + "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); + } + +# Check if it's the start of a commit log +# (not a header line and we haven't seen the patch filename) + if ($in_header_lines && $realfile =~ /^$/ && + $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) { + $in_header_lines = 0; + $in_commit_log = 1; + } + +# Check if there is UTF-8 in a commit log when a mail header has explicitly +# declined it, i.e defined some charset where it is missing. + if ($in_header_lines && + $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && + $1 !~ /utf-8/i) { + $non_utf8_charset = 1; + } + + if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && + $rawline =~ /$NON_ASCII_UTF8/) { + WARN("UTF8_BEFORE_PATCH", + "8-bit UTF-8 used in possible commit log\n" . $herecurr); + } + +# ignore non-hunk lines and lines being removed + next if (!$hunk_line || $line =~ /^-/); + +#trailing whitespace + if ($line =~ /^\+.*\015/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (ERROR("DOS_LINE_ENDINGS", + "DOS line endings\n" . $herevet) && + $fix) { + $fixed[$linenr - 1] =~ s/[\s\015]+$//; + } + } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (ERROR("TRAILING_WHITESPACE", + "trailing whitespace\n" . $herevet) && + $fix) { + $fixed[$linenr - 1] =~ s/\s+$//; + } + + $rpt_cleaners = 1; + } + +# Check for FSF mailing addresses. + if ($rawline =~ /\bwrite to the Free/i || + $rawline =~ /\b59\s+Temple\s+Pl/i || + $rawline =~ /\b51\s+Franklin\s+St/i) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + my $msg_type = \&ERROR; + $msg_type = \&CHK if ($file); + &{$msg_type}("FSF_MAILING_ADDRESS", + "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet) + } + +# check for Kconfig help text having a real description +# Only applies when adding the entry originally, after that we do not have +# sufficient context to determine whether it is indeed long enough. + if ($realfile =~ /Kconfig/ && + $line =~ /.\s*config\s+/) { + my $length = 0; + my $cnt = $realcnt; + my $ln = $linenr + 1; + my $f; + my $is_start = 0; + my $is_end = 0; + for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) { + $f = $lines[$ln - 1]; + $cnt-- if ($lines[$ln - 1] !~ /^-/); + $is_end = $lines[$ln - 1] =~ /^\+/; + + next if ($f =~ /^-/); + + if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) { + $is_start = 1; + } elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) { + $length = -1; + } + + $f =~ s/^.//; + $f =~ s/#.*//; + $f =~ s/^\s+//; + next if ($f =~ /^$/); + if ($f =~ /^\s*config\s/) { + $is_end = 1; + last; + } + $length++; + } + WARN("CONFIG_DESCRIPTION", + "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4); + #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; + } + +# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig. + if ($realfile =~ /Kconfig/ && + $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) { + WARN("CONFIG_EXPERIMENTAL", + "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); + } + + if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && + ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { + my $flag = $1; + my $replacement = { + 'EXTRA_AFLAGS' => 'asflags-y', + 'EXTRA_CFLAGS' => 'ccflags-y', + 'EXTRA_CPPFLAGS' => 'cppflags-y', + 'EXTRA_LDFLAGS' => 'ldflags-y', + }; + + WARN("DEPRECATED_VARIABLE", + "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); + } + +# check for DT compatible documentation + if (defined $root && $realfile =~ /\.dts/ && + $rawline =~ /^\+\s*compatible\s*=/) { + my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g; + + foreach my $compat (@compats) { + my $compat2 = $compat; + my $dt_path = $root . "/Documentation/devicetree/bindings/"; + $compat2 =~ s/\,[a-z]*\-/\,<\.\*>\-/; + `grep -Erq "$compat|$compat2" $dt_path`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr); + } + + my $vendor = $compat; + my $vendor_path = $dt_path . "vendor-prefixes.txt"; + next if (! -f $vendor_path); + $vendor =~ s/^([a-zA-Z0-9]+)\,.*/$1/; + `grep -Eq "$vendor" $vendor_path`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string vendor \"$vendor\" appears un-documented -- check $vendor_path\n" . $herecurr); + } + } + } + +# check we are in a valid source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); + +#line length limit + if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && + $rawline !~ /^.\s*\*\s*\@$Ident\s/ && + !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ || + $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && + $length > $max_line_length) + { + WARN("LONG_LINE", + "line over $max_line_length characters\n" . $herecurr); + } + +# Check for user-visible strings broken across lines, which breaks the ability +# to grep for the string. Make exceptions when the previous string ends in a +# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{' +# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value + if ($line =~ /^\+\s*"/ && + $prevline =~ /"\s*$/ && + $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) { + WARN("SPLIT_STRING", + "quoted string split across lines\n" . $hereprev); + } + +# check for spaces before a quoted newline + if ($rawline =~ /^.*\".*\s\\n/) { + if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", + "unnecessary whitespace before a quoted newline\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/^(\+.*\".*)\s+\\n/$1\\n/; + } + + } + +# check for adding lines without a newline. + if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { + WARN("MISSING_EOF_NEWLINE", + "adding a line without newline at end of file\n" . $herecurr); + } + +# Blackfin: use hi/lo macros + if ($realfile =~ m@arch/blackfin/.*\.S$@) { + if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("LO_MACRO", + "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); + } + if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("HI_MACRO", + "use the HI() macro, not (... >> 16)\n" . $herevet); + } + } + +# check we are in a valid source file C or perl if not then ignore this hunk + next if ($realfile !~ /\.(h|c|pl)$/); + +# at the beginning of a line any tabs must come first and anything +# more than 8 must use tabs. + if ($rawline =~ /^\+\s* \t\s*\S/ || + $rawline =~ /^\+\s* \s*/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + $rpt_cleaners = 1; + if (ERROR("CODE_INDENT", + "code indent should use tabs where possible\n" . $herevet) && + $fix) { + $fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } + } + +# check for space before tabs. + if ($rawline =~ /^\+/ && $rawline =~ / \t/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (WARN("SPACE_BEFORE_TAB", + "please, no space before tabs\n" . $herevet) && + $fix) { + while ($fixed[$linenr - 1] =~ + s/(^\+.*) {8,8}\t/$1\t\t/) {} + while ($fixed[$linenr - 1] =~ + s/(^\+.*) +\t/$1\t/) {} + } + } + +# check for && or || at the start of a line + if ($rawline =~ /^\+\s*(&&|\|\|)/) { + CHK("LOGICAL_CONTINUATIONS", + "Logical continuations should be on the previous line\n" . $hereprev); + } + +# check multi-line statement indentation matches previous line + if ($^V && $^V ge 5.10.0 && + $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) { + $prevline =~ /^\+(\t*)(.*)$/; + my $oldindent = $1; + my $rest = $2; + + my $pos = pos_last_openparen($rest); + if ($pos >= 0) { + $line =~ /^(\+| )([ \t]*)/; + my $newindent = $2; + + my $goodtabindent = $oldindent . + "\t" x ($pos / 8) . + " " x ($pos % 8); + my $goodspaceindent = $oldindent . " " x $pos; + + if ($newindent ne $goodtabindent && + $newindent ne $goodspaceindent) { + + if (CHK("PARENTHESIS_ALIGNMENT", + "Alignment should match open parenthesis\n" . $hereprev) && + $fix && $line =~ /^\+/) { + $fixed[$linenr - 1] =~ + s/^\+[ \t]*/\+$goodtabindent/; + } + } + } + } + + if ($line =~ /^\+.*\*[ \t]*\)[ \t]+(?!$Assignment|$Arithmetic)/) { + if (CHK("SPACING", + "No space is necessary after a cast\n" . $hereprev) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(\+.*\*[ \t]*\))[ \t]+/$1/; + } + } + + if ($realfile =~ m@^(drivers/net/|net/)@ && + $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ && + $rawline =~ /^\+[ \t]*\*/) { + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); + } + + if ($realfile =~ m@^(drivers/net/|net/)@ && + $prevrawline =~ /^\+[ \t]*\/\*/ && #starting /* + $prevrawline !~ /\*\/[ \t]*$/ && #no trailing */ + $rawline =~ /^\+/ && #line is new + $rawline !~ /^\+[ \t]*\*/) { #no leading * + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments start with * on subsequent lines\n" . $hereprev); + } + + if ($realfile =~ m@^(drivers/net/|net/)@ && + $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ + $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ + $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ + $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments put the trailing */ on a separate line\n" . $herecurr); + } + +# check for spaces at the beginning of a line. +# Exceptions: +# 1) within comments +# 2) indented preprocessor commands +# 3) hanging labels + if ($rawline =~ /^\+ / && $line !~ /^\+ *(?:$;|#|$Ident:)/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (WARN("LEADING_SPACE", + "please, no spaces at the start of a line\n" . $herevet) && + $fix) { + $fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } + } + +# check we are in a valid C source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c)$/); + +# discourage the addition of CONFIG_EXPERIMENTAL in #if(def). + if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) { + WARN("CONFIG_EXPERIMENTAL", + "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); + } + +# check for RCS/CVS revision markers + if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { + WARN("CVS_KEYWORD", + "CVS style keyword markers, these will _not_ be updated\n". $herecurr); + } + +# Blackfin: don't use __builtin_bfin_[cs]sync + if ($line =~ /__builtin_bfin_csync/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("CSYNC", + "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); + } + if ($line =~ /__builtin_bfin_ssync/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("SSYNC", + "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); + } + +# check for old HOTPLUG __dev section markings + if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { + WARN("HOTPLUG_SECTION", + "Using $1 is unnecessary\n" . $herecurr); + } + +# Check for potential 'bare' types + my ($stat, $cond, $line_nr_next, $remain_next, $off_next, + $realline_next); +#print "LINE<$line>\n"; + if ($linenr >= $suppress_statement && + $realcnt && $sline =~ /.\s*\S/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0); + $stat =~ s/\n./\n /g; + $cond =~ s/\n./\n /g; + +#print "linenr<$linenr> <$stat>\n"; + # If this statement has no statement boundaries within + # it there is no point in retrying a statement scan + # until we hit end of it. + my $frag = $stat; $frag =~ s/;+\s*$//; + if ($frag !~ /(?:{|;)/) { +#print "skip<$line_nr_next>\n"; + $suppress_statement = $line_nr_next; + } + + # Find the real next line. + $realline_next = $line_nr_next; + if (defined $realline_next && + (!defined $lines[$realline_next - 1] || + substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) { + $realline_next++; + } + + my $s = $stat; + $s =~ s/{.*$//s; + + # Ignore goto labels. + if ($s =~ /$Ident:\*$/s) { + + # Ignore functions being called + } elsif ($s =~ /^.\s*$Ident\s*\(/s) { + + } elsif ($s =~ /^.\s*else\b/s) { + + # declarations always start with types + } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) { + my $type = $1; + $type =~ s/\s+/ /g; + possible($type, "A:" . $s); + + # definitions in global scope can only start with types + } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) { + possible($1, "B:" . $s); + } + + # any (foo ... *) is a pointer cast, and foo is a type + while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) { + possible($1, "C:" . $s); + } + + # Check for any sort of function declaration. + # int foo(something bar, other baz); + # void (*store_gdt)(x86_descr_ptr *); + if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) { + my ($name_len) = length($1); + + my $ctx = $s; + substr($ctx, 0, $name_len + 1, ''); + $ctx =~ s/\)[^\)]*$//; + + for my $arg (split(/\s*,\s*/, $ctx)) { + if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) { + + possible($1, "D:" . $s); + } + } + } + + } + +# +# Checks which may be anchored in the context. +# + +# Check for switch () and associated case and default +# statements should be at the same indent. + if ($line=~/\bswitch\s*\(.*\)/) { + my $err = ''; + my $sep = ''; + my @ctx = ctx_block_outer($linenr, $realcnt); + shift(@ctx); + for my $ctx (@ctx) { + my ($clen, $cindent) = line_stats($ctx); + if ($ctx =~ /^\+\s*(case\s+|default:)/ && + $indent != $cindent) { + $err .= "$sep$ctx\n"; + $sep = ''; + } else { + $sep = "[...]\n"; + } + } + if ($err ne '') { + ERROR("SWITCH_CASE_INDENT_LEVEL", + "switch and case should be at the same indent\n$hereline$err"); + } + } + +# if/while/etc brace do not go on next line, unless defining a do while loop, +# or if that brace on the next line is for something else + if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { + my $pre_ctx = "$1$2"; + + my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); + + if ($line =~ /^\+\t{6,}/) { + WARN("DEEP_INDENTATION", + "Too many leading tabs - consider code refactoring\n" . $herecurr); + } + + my $ctx_cnt = $realcnt - $#ctx - 1; + my $ctx = join("\n", @ctx); + + my $ctx_ln = $linenr; + my $ctx_skip = $realcnt; + + while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt && + defined $lines[$ctx_ln - 1] && + $lines[$ctx_ln - 1] =~ /^-/)) { + ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n"; + $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/); + $ctx_ln++; + } + + #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; + #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; + + if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { + ERROR("OPEN_BRACE", + "that open brace { should be on the previous line\n" . + "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); + } + if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ && + $ctx =~ /\)\s*\;\s*$/ && + defined $lines[$ctx_ln - 1]) + { + my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]); + if ($nindent > $indent) { + WARN("TRAILING_SEMICOLON", + "trailing semicolon indicates no statements, indent implies otherwise\n" . + "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); + } + } + } + +# Check relative indent for conditionals and blocks. + if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); + my ($s, $c) = ($stat, $cond); + + substr($s, 0, length($c), ''); + + # Make sure we remove the line prefixes as we have + # none on the first line, and are going to readd them + # where necessary. + $s =~ s/\n./\n/gs; + + # Find out how long the conditional actually is. + my @newlines = ($c =~ /\n/gs); + my $cond_lines = 1 + $#newlines; + + # We want to check the first line inside the block + # starting at the end of the conditional, so remove: + # 1) any blank line termination + # 2) any opening brace { on end of the line + # 3) any do (...) { + my $continuation = 0; + my $check = 0; + $s =~ s/^.*\bdo\b//; + $s =~ s/^\s*{//; + if ($s =~ s/^\s*\\//) { + $continuation = 1; + } + if ($s =~ s/^\s*?\n//) { + $check = 1; + $cond_lines++; + } + + # Also ignore a loop construct at the end of a + # preprocessor statement. + if (($prevline =~ /^.\s*#\s*define\s/ || + $prevline =~ /\\\s*$/) && $continuation == 0) { + $check = 0; + } + + my $cond_ptr = -1; + $continuation = 0; + while ($cond_ptr != $cond_lines) { + $cond_ptr = $cond_lines; + + # If we see an #else/#elif then the code + # is not linear. + if ($s =~ /^\s*\#\s*(?:else|elif)/) { + $check = 0; + } + + # Ignore: + # 1) blank lines, they should be at 0, + # 2) preprocessor lines, and + # 3) labels. + if ($continuation || + $s =~ /^\s*?\n/ || + $s =~ /^\s*#\s*?/ || + $s =~ /^\s*$Ident\s*:/) { + $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0; + if ($s =~ s/^.*?\n//) { + $cond_lines++; + } + } + } + + my (undef, $sindent) = line_stats("+" . $s); + my $stat_real = raw_line($linenr, $cond_lines); + + # Check if either of these lines are modified, else + # this is not this patch's fault. + if (!defined($stat_real) || + $stat !~ /^\+/ && $stat_real !~ /^\+/) { + $check = 0; + } + if (defined($stat_real) && $cond_lines > 1) { + $stat_real = "[...]\n$stat_real"; + } + + #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; + + if ($check && (($sindent % 8) != 0 || + ($sindent <= $indent && $s ne ''))) { + WARN("SUSPECT_CODE_INDENT", + "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); + } + } + + # Track the 'values' across context and added lines. + my $opline = $line; $opline =~ s/^./ /; + my ($curr_values, $curr_vars) = + annotate_values($opline . "\n", $prev_values); + $curr_values = $prev_values . $curr_values; + if ($dbg_values) { + my $outline = $opline; $outline =~ s/\t/ /g; + print "$linenr > .$outline\n"; + print "$linenr > $curr_values\n"; + print "$linenr > $curr_vars\n"; + } + $prev_values = substr($curr_values, -1); + +#ignore lines not being added + next if ($line =~ /^[^\+]/); + +# TEST: allow direct testing of the type matcher. + if ($dbg_type) { + if ($line =~ /^.\s*$Declare\s*$/) { + ERROR("TEST_TYPE", + "TEST: is type\n" . $herecurr); + } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) { + ERROR("TEST_NOT_TYPE", + "TEST: is not type ($1 is)\n". $herecurr); + } + next; + } +# TEST: allow direct testing of the attribute matcher. + if ($dbg_attr) { + if ($line =~ /^.\s*$Modifier\s*$/) { + ERROR("TEST_ATTR", + "TEST: is attr\n" . $herecurr); + } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) { + ERROR("TEST_NOT_ATTR", + "TEST: is not attr ($1 is)\n". $herecurr); + } + next; + } + +# check for initialisation to aggregates open brace on the next line + if ($line =~ /^.\s*{/ && + $prevline =~ /(?:^|[^=])=\s*$/) { + ERROR("OPEN_BRACE", + "that open brace { should be on the previous line\n" . $hereprev); + } + +# +# Checks which are anchored on the added line. +# + +# check for malformed paths in #include statements (uses RAW line) + if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) { + my $path = $1; + if ($path =~ m{//}) { + ERROR("MALFORMED_INCLUDE", + "malformed #include filename\n" . $herecurr); + } + if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { + ERROR("UAPI_INCLUDE", + "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); + } + } + +# no C99 // comments + if ($line =~ m{//}) { + if (ERROR("C99_COMMENTS", + "do not use C99 // comments\n" . $herecurr) && + $fix) { + my $line = $fixed[$linenr - 1]; + if ($line =~ /\/\/(.*)$/) { + my $comment = trim($1); + $fixed[$linenr - 1] =~ s@\/\/(.*)$@/\* $comment \*/@; + } + } + } + # Remove C99 comments. + $line =~ s@//.*@@; + $opline =~ s@//.*@@; + +# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider +# the whole statement. +#print "APW <$lines[$realline_next - 1]>\n"; + if (defined $realline_next && + exists $lines[$realline_next - 1] && + !defined $suppress_export{$realline_next} && + ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || + $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { + # Handle definitions which produce identifiers with + # a prefix: + # XXX(foo); + # EXPORT_SYMBOL(something_foo); + my $name = $1; + if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && + $name =~ /^${Ident}_$2/) { +#print "FOO C name<$name>\n"; + $suppress_export{$realline_next} = 1; + + } elsif ($stat !~ /(?: + \n.}\s*$| + ^.DEFINE_$Ident\(\Q$name\E\)| + ^.DECLARE_$Ident\(\Q$name\E\)| + ^.LIST_HEAD\(\Q$name\E\)| + ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(| + \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\() + )/x) { +#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n"; + $suppress_export{$realline_next} = 2; + } else { + $suppress_export{$realline_next} = 1; + } + } + if (!defined $suppress_export{$linenr} && + $prevline =~ /^.\s*$/ && + ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || + $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { +#print "FOO B <$lines[$linenr - 1]>\n"; + $suppress_export{$linenr} = 2; + } + if (defined $suppress_export{$linenr} && + $suppress_export{$linenr} == 2) { + WARN("EXPORT_SYMBOL", + "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr); + } + +# check for global initialisers. + if ($line =~ /^\+(\s*$Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/) { + if (ERROR("GLOBAL_INITIALISERS", + "do not initialise globals to 0 or NULL\n" . + $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/($Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/$1;/; + } + } +# check for static initialisers. + if ($line =~ /^\+.*\bstatic\s.*=\s*(0|NULL|false)\s*;/) { + if (ERROR("INITIALISED_STATIC", + "do not initialise statics to 0 or NULL\n" . + $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/(\bstatic\s.*?)\s*=\s*(0|NULL|false)\s*;/$1;/; + } + } + +# check for static const char * arrays. + if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "static const char * array should probably be static const char * const\n" . + $herecurr); + } + +# check for static char foo[] = "bar" declarations. + if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "static char array declaration should probably be static const char\n" . + $herecurr); + } + +# check for function declarations without arguments like "int foo()" + if ($line =~ /(\b$Type\s+$Ident)\s*\(\s*\)/) { + if (ERROR("FUNCTION_WITHOUT_ARGS", + "Bad function definition - $1() should probably be $1(void)\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/; + } + } + +# check for uses of DEFINE_PCI_DEVICE_TABLE + if ($line =~ /\bDEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=/) { + if (WARN("DEFINE_PCI_DEVICE_TABLE", + "Prefer struct pci_device_id over deprecated DEFINE_PCI_DEVICE_TABLE\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b(?:static\s+|)DEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=\s*/static const struct pci_device_id $1\[\] = /; + } + } + +# check for new typedefs, only function parameters and sparse annotations +# make sense. + if ($line =~ /\btypedef\s/ && + $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && + $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && + $line !~ /\b$typeTypedefs\b/ && + $line !~ /\b__bitwise(?:__|)\b/) { + WARN("NEW_TYPEDEFS", + "do not add new typedefs\n" . $herecurr); + } + +# * goes on variable not on type + # (char*[ const]) + while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { + #print "AA<$1>\n"; + my ($ident, $from, $to) = ($1, $2, $2); + + # Should start with a space. + $to =~ s/^(\S)/ $1/; + # Should not end with a space. + $to =~ s/\s+$//; + # '*'s should not have spaces between. + while ($to =~ s/\*\s+\*/\*\*/) { + } + +## print "1: from<$from> to<$to> ident<$ident>\n"; + if ($from ne $to) { + if (ERROR("POINTER_LOCATION", + "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr) && + $fix) { + my $sub_from = $ident; + my $sub_to = $ident; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$linenr - 1] =~ + s@\Q$sub_from\E@$sub_to@; + } + } + } + while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { + #print "BB<$1>\n"; + my ($match, $from, $to, $ident) = ($1, $2, $2, $3); + + # Should start with a space. + $to =~ s/^(\S)/ $1/; + # Should not end with a space. + $to =~ s/\s+$//; + # '*'s should not have spaces between. + while ($to =~ s/\*\s+\*/\*\*/) { + } + # Modifiers should have spaces. + $to =~ s/(\b$Modifier$)/$1 /; + +## print "2: from<$from> to<$to> ident<$ident>\n"; + if ($from ne $to && $ident !~ /^$Modifier$/) { + if (ERROR("POINTER_LOCATION", + "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr) && + $fix) { + + my $sub_from = $match; + my $sub_to = $match; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$linenr - 1] =~ + s@\Q$sub_from\E@$sub_to@; + } + } + } + +# # no BUG() or BUG_ON() +# if ($line =~ /\b(BUG|BUG_ON)\b/) { +# print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n"; +# print "$herecurr"; +# $clean = 0; +# } + + if ($line =~ /\bLINUX_VERSION_CODE\b/) { + WARN("LINUX_VERSION_CODE", + "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); + } + +# check for uses of printk_ratelimit + if ($line =~ /\bprintk_ratelimit\s*\(/) { + WARN("PRINTK_RATELIMITED", +"Prefer printk_ratelimited or pr__ratelimited to printk_ratelimit\n" . $herecurr); + } + +# printk should use KERN_* levels. Note that follow on printk's on the +# same line do not need a level, so we use the current block context +# to try and find and validate the current printk. In summary the current +# printk includes all preceding printk's which have no newline on the end. +# we assume the first bad printk is the one to report. + if ($line =~ /\bprintk\((?!KERN_)\s*"/) { + my $ok = 0; + for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { + #print "CHECK<$lines[$ln - 1]\n"; + # we have a preceding printk if it ends + # with "\n" ignore it, else it is to blame + if ($lines[$ln - 1] =~ m{\bprintk\(}) { + if ($rawlines[$ln - 1] !~ m{\\n"}) { + $ok = 1; + } + last; + } + } + if ($ok == 0) { + WARN("PRINTK_WITHOUT_KERN_LEVEL", + "printk() should include KERN_ facility level\n" . $herecurr); + } + } + + if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + my $level2 = $level; + $level2 = "dbg" if ($level eq "debug"); + WARN("PREFER_PR_LEVEL", + "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); + } + + if ($line =~ /\bpr_warning\s*\(/) { + if (WARN("PREFER_PR_LEVEL", + "Prefer pr_warn(... to pr_warning(...\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\bpr_warning\b/pr_warn/; + } + } + + if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + $level = "dbg" if ($level eq "debug"); + WARN("PREFER_DEV_LEVEL", + "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); + } + +# function brace can't be on same line, except for #defines of do while, +# or if closed on same line + if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and + !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) { + ERROR("OPEN_BRACE", + "open brace '{' following function declarations go on the next line\n" . $herecurr); + } + +# open braces for enum, union and struct go on the same line. + if ($line =~ /^.\s*{/ && + $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { + ERROR("OPEN_BRACE", + "open brace '{' following $1 go on the same line\n" . $hereprev); + } + +# missing space after union, struct or enum definition + if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident){1,2}[=\{]/) { + if (WARN("SPACING", + "missing space after $1 definition\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/; + } + } + +# Function pointer declarations +# check spacing between type, funcptr, and args +# canonical declaration is "type (*funcptr)(args...)" +# +# the $Declare variable will capture all spaces after the type +# so check it for trailing missing spaces or multiple spaces + if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)$Ident(\s*)\)(\s*)\(/) { + my $declare = $1; + my $pre_pointer_space = $2; + my $post_pointer_space = $3; + my $funcname = $4; + my $post_funcname_space = $5; + my $pre_args_space = $6; + + if ($declare !~ /\s$/) { + WARN("SPACING", + "missing space after return type\n" . $herecurr); + } + +# unnecessary space "type (*funcptr)(args...)" + elsif ($declare =~ /\s{2,}$/) { + WARN("SPACING", + "Multiple spaces after return type\n" . $herecurr); + } + +# unnecessary space "type ( *funcptr)(args...)" + if (defined $pre_pointer_space && + $pre_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer open parenthesis\n" . $herecurr); + } + +# unnecessary space "type (* funcptr)(args...)" + if (defined $post_pointer_space && + $post_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr )(args...)" + if (defined $post_funcname_space && + $post_funcname_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr) (args...)" + if (defined $pre_args_space && + $pre_args_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer arguments\n" . $herecurr); + } + + if (show_type("SPACING") && $fix) { + $fixed[$linenr - 1] =~ + s/^(.\s*$Declare)\(\s*\*\s*($Ident)\s*\)\s*\(/rtrim($1) . " " . "\(\*$2\)\("/ex; + } + } + +# check for spacing round square brackets; allowed: +# 1. with a type on the left -- int [] a; +# 2. at the beginning of a line for slice initialisers -- [0...10] = 5, +# 3. inside a curly brace -- = { [0...10] = 5 } + while ($line =~ /(.*?\s)\[/g) { + my ($where, $prefix) = ($-[1], $1); + if ($prefix !~ /$Type\s+$/ && + ($where != 0 || $prefix !~ /^.\s+$/) && + $prefix !~ /[{,]\s+$/) { + if (ERROR("BRACKET_SPACE", + "space prohibited before open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(\+.*?)\s+\[/$1\[/; + } + } + } + +# check for spaces between functions and their parentheses. + while ($line =~ /($Ident)\s+\(/g) { + my $name = $1; + my $ctx_before = substr($line, 0, $-[1]); + my $ctx = "$ctx_before$name"; + + # Ignore those directives where spaces _are_ permitted. + if ($name =~ /^(?: + if|for|while|switch|return|case| + volatile|__volatile__| + __attribute__|format|__extension__| + asm|__asm__)$/x) + { + # cpp #define statements have non-optional spaces, ie + # if there is a space between the name and the open + # parenthesis it is simply not a parameter group. + } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) { + + # cpp #elif statement condition may start with a ( + } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) { + + # If this whole things ends with a type its most + # likely a typedef for a function. + } elsif ($ctx =~ /$Type$/) { + + } else { + if (WARN("SPACING", + "space prohibited between function name and open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\b$name\s+\(/$name\(/; + } + } + } + +# Check operator spacing. + if (!($line=~/\#\s*include/)) { + my $fixed_line = ""; + my $line_fixed = 0; + + my $ops = qr{ + <<=|>>=|<=|>=|==|!=| + \+=|-=|\*=|\/=|%=|\^=|\|=|&=| + =>|->|<<|>>|<|>|=|!|~| + &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| + \?:|\?|: + }x; + my @elements = split(/($ops|;)/, $opline); + +## print("element count: <" . $#elements . ">\n"); +## foreach my $el (@elements) { +## print("el: <$el>\n"); +## } + + my @fix_elements = (); + my $off = 0; + + foreach my $el (@elements) { + push(@fix_elements, substr($rawline, $off, length($el))); + $off += length($el); + } + + $off = 0; + + my $blank = copy_spacing($opline); + my $last_after = -1; + + for (my $n = 0; $n < $#elements; $n += 2) { + + my $good = $fix_elements[$n] . $fix_elements[$n + 1]; + +## print("n: <$n> good: <$good>\n"); + + $off += length($elements[$n]); + + # Pick up the preceding and succeeding characters. + my $ca = substr($opline, 0, $off); + my $cc = ''; + if (length($opline) >= ($off + length($elements[$n + 1]))) { + $cc = substr($opline, $off + length($elements[$n + 1])); + } + my $cb = "$ca$;$cc"; + + my $a = ''; + $a = 'V' if ($elements[$n] ne ''); + $a = 'W' if ($elements[$n] =~ /\s$/); + $a = 'C' if ($elements[$n] =~ /$;$/); + $a = 'B' if ($elements[$n] =~ /(\[|\()$/); + $a = 'O' if ($elements[$n] eq ''); + $a = 'E' if ($ca =~ /^\s*$/); + + my $op = $elements[$n + 1]; + + my $c = ''; + if (defined $elements[$n + 2]) { + $c = 'V' if ($elements[$n + 2] ne ''); + $c = 'W' if ($elements[$n + 2] =~ /^\s/); + $c = 'C' if ($elements[$n + 2] =~ /^$;/); + $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/); + $c = 'O' if ($elements[$n + 2] eq ''); + $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/); + } else { + $c = 'E'; + } + + my $ctx = "${a}x${c}"; + + my $at = "(ctx:$ctx)"; + + my $ptr = substr($blank, 0, $off) . "^"; + my $hereptr = "$hereline$ptr\n"; + + # Pull out the value of this operator. + my $op_type = substr($curr_values, $off + 1, 1); + + # Get the full operator variant. + my $opv = $op . substr($curr_vars, $off, 1); + + # Ignore operators passed as parameters. + if ($op_type ne 'V' && + $ca =~ /\s$/ && $cc =~ /^\s*,/) { + +# # Ignore comments +# } elsif ($op =~ /^$;+$/) { + + # ; should have either the end of line or a space or \ after it + } elsif ($op eq ';') { + if ($ctx !~ /.x[WEBC]/ && + $cc !~ /^\\/ && $cc !~ /^;/) { + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } + } + + # // is a comment + } elsif ($op eq '//') { + + # No spaces for: + # -> + # : when part of a bitfield + } elsif ($op eq '->' || $opv eq ':B') { + if ($ctx =~ /Wx.|.xW/) { + if (ERROR("SPACING", + "spaces prohibited around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # , must have a space on the right. + } elsif ($op eq ',') { + if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + $last_after = $n; + } + } + + # '*' as part of a type definition -- reported already. + } elsif ($opv eq '*_') { + #warn "'*' is part of type\n"; + + # unary operators should have a space before and + # none after. May be left adjacent to another + # unary operator, or a cast + } elsif ($op eq '!' || $op eq '~' || + $opv eq '*U' || $opv eq '-U' || + $opv eq '&U' || $opv eq '&&U') { + if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { + if (ERROR("SPACING", + "space required before that '$op' $at\n" . $hereptr)) { + if ($n != $last_after + 2) { + $good = $fix_elements[$n] . " " . ltrim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + } + if ($op eq '*' && $cc =~/\s*$Modifier\b/) { + # A unary '*' may be const + + } elsif ($ctx =~ /.xW/) { + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # unary ++ and unary -- are allowed no space on one side. + } elsif ($op eq '++' or $op eq '--') { + if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { + if (ERROR("SPACING", + "space required one side of that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } + } + if ($ctx =~ /Wx[BE]/ || + ($ctx =~ /Wx./ && $cc =~ /^;/)) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + if ($ctx =~ /ExW/) { + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # << and >> may either have or not have spaces both sides + } elsif ($op eq '<<' or $op eq '>>' or + $op eq '&' or $op eq '^' or $op eq '|' or + $op eq '+' or $op eq '-' or + $op eq '*' or $op eq '/' or + $op eq '%') + { + if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { + if (ERROR("SPACING", + "need consistent spacing around '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # A colon needs no spaces before when it is + # terminating a case value or a label. + } elsif ($opv eq ':C' || $opv eq ':L') { + if ($ctx =~ /Wx./) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + + # All the others need spaces both sides. + } elsif ($ctx !~ /[EWC]x[CWE]/) { + my $ok = 0; + + # Ignore email addresses + if (($op eq '<' && + $cc =~ /^\S+\@\S+>/) || + ($op eq '>' && + $ca =~ /<\S+\@\S+$/)) + { + $ok = 1; + } + + # messages are ERROR, but ?: are CHK + if ($ok == 0) { + my $msg_type = \&ERROR; + $msg_type = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/); + + if (&{$msg_type}("SPACING", + "spaces required around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + } + $off += length($elements[$n + 1]); + +## print("n: <$n> GOOD: <$good>\n"); + + $fixed_line = $fixed_line . $good; + } + + if (($#elements % 2) == 0) { + $fixed_line = $fixed_line . $fix_elements[$#elements]; + } + + if ($fix && $line_fixed && $fixed_line ne $fixed[$linenr - 1]) { + $fixed[$linenr - 1] = $fixed_line; + } + + + } + +# check for whitespace before a non-naked semicolon + if ($line =~ /^\+.*\S\s+;\s*$/) { + if (WARN("SPACING", + "space prohibited before semicolon\n" . $herecurr) && + $fix) { + 1 while $fixed[$linenr - 1] =~ + s/^(\+.*\S)\s+;/$1;/; + } + } + +# check for multiple assignments + if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) { + CHK("MULTIPLE_ASSIGNMENTS", + "multiple assignments should be avoided\n" . $herecurr); + } + +## # check for multiple declarations, allowing for a function declaration +## # continuation. +## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ && +## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { +## +## # Remove any bracketed sections to ensure we do not +## # falsly report the parameters of functions. +## my $ln = $line; +## while ($ln =~ s/\([^\(\)]*\)//g) { +## } +## if ($ln =~ /,/) { +## WARN("MULTIPLE_DECLARATION", +## "declaring multiple variables together should be avoided\n" . $herecurr); +## } +## } + +#need space before brace following if, while, etc + if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) || + $line =~ /do{/) { + if (ERROR("SPACING", + "space required before the open brace '{'\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/^(\+.*(?:do|\))){/$1 {/; + } + } + +## # check for blank lines before declarations +## if ($line =~ /^.\t+$Type\s+$Ident(?:\s*=.*)?;/ && +## $prevrawline =~ /^.\s*$/) { +## WARN("SPACING", +## "No blank lines before declarations\n" . $hereprev); +## } +## + +# closing brace should have a space following it when it has anything +# on the line + if ($line =~ /}(?!(?:,|;|\)))\S/) { + if (ERROR("SPACING", + "space required after that close brace '}'\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/}((?!(?:,|;|\)))\S)/} $1/; + } + } + +# check spacing on square brackets + if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { + if (ERROR("SPACING", + "space prohibited after that open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\[\s+/\[/; + } + } + if ($line =~ /\s\]/) { + if (ERROR("SPACING", + "space prohibited before that close square bracket ']'\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\s+\]/\]/; + } + } + +# check spacing on parentheses + if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && + $line !~ /for\s*\(\s+;/) { + if (ERROR("SPACING", + "space prohibited after that open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\(\s+/\(/; + } + } + if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && + $line !~ /for\s*\(.*;\s+\)/ && + $line !~ /:\s+\)/) { + if (ERROR("SPACING", + "space prohibited before that close parenthesis ')'\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\s+\)/\)/; + } + } + +#goto labels aren't indented, allow a single space however + if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and + !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { + if (WARN("INDENTED_LABEL", + "labels should not be indented\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(.)\s+/$1/; + } + } + +# Return is not a function. + if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) { + my $spacing = $1; + if ($^V && $^V ge 5.10.0 && + $stat =~ /^.\s*return\s*$balanced_parens\s*;\s*$/) { + ERROR("RETURN_PARENTHESES", + "return is not a function, parentheses are not required\n" . $herecurr); + + } elsif ($spacing !~ /\s+/) { + ERROR("SPACING", + "space required before the open parenthesis '('\n" . $herecurr); + } + } + +# if statements using unnecessary parentheses - ie: if ((foo == bar)) + if ($^V && $^V ge 5.10.0 && + $line =~ /\bif\s*((?:\(\s*){2,})/) { + my $openparens = $1; + my $count = $openparens =~ tr@\(@\(@; + my $msg = ""; + if ($line =~ /\bif\s*(?:\(\s*){$count,$count}$LvalOrFunc\s*($Compare)\s*$LvalOrFunc(?:\s*\)){$count,$count}/) { + my $comp = $4; #Not $1 because of $LvalOrFunc + $msg = " - maybe == should be = ?" if ($comp eq "=="); + WARN("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses$msg\n" . $herecurr); + } + } + +# Return of what appears to be an errno should normally be -'ve + if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { + my $name = $1; + if ($name ne 'EOF' && $name ne 'ERROR') { + WARN("USE_NEGATIVE_ERRNO", + "return of an errno should typically be -ve (return -$1)\n" . $herecurr); + } + } + +# Need a space before open parenthesis after if, while etc + if ($line =~ /\b(if|while|for|switch)\(/) { + if (ERROR("SPACING", + "space required before the open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/\b(if|while|for|switch)\(/$1 \(/; + } + } + +# Check for illegal assignment in if conditional -- and check for trailing +# statements after the conditional. + if ($line =~ /do\s*(?!{)/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); + my ($stat_next) = ctx_statement_block($line_nr_next, + $remain_next, $off_next); + $stat_next =~ s/\n./\n /g; + ##print "stat<$stat> stat_next<$stat_next>\n"; + + if ($stat_next =~ /^\s*while\b/) { + # If the statement carries leading newlines, + # then count those as offsets. + my ($whitespace) = + ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s); + my $offset = + statement_rawlines($whitespace) - 1; + + $suppress_whiletrailers{$line_nr_next + + $offset} = 1; + } + } + if (!defined $suppress_whiletrailers{$linenr} && + defined($stat) && defined($cond) && + $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { + my ($s, $c) = ($stat, $cond); + + if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { + ERROR("ASSIGN_IN_IF", + "do not use assignment in if condition\n" . $herecurr); + } + + # Find out what is on the end of the line after the + # conditional. + substr($s, 0, length($c), ''); + $s =~ s/\n.*//g; + $s =~ s/$;//g; # Remove any comments + if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && + $c !~ /}\s*while\s*/) + { + # Find out how long the conditional actually is. + my @newlines = ($c =~ /\n/gs); + my $cond_lines = 1 + $#newlines; + my $stat_real = ''; + + $stat_real = raw_line($linenr, $cond_lines) + . "\n" if ($cond_lines); + if (defined($stat_real) && $cond_lines > 1) { + $stat_real = "[...]\n$stat_real"; + } + + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr . $stat_real); + } + } + +# Check for bitwise tests written as boolean + if ($line =~ / + (?: + (?:\[|\(|\&\&|\|\|) + \s*0[xX][0-9]+\s* + (?:\&\&|\|\|) + | + (?:\&\&|\|\|) + \s*0[xX][0-9]+\s* + (?:\&\&|\|\||\)|\]) + )/x) + { + WARN("HEXADECIMAL_BOOLEAN_TEST", + "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr); + } + +# if and else should not have general statements after it + if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { + my $s = $1; + $s =~ s/$;//g; # Remove any comments + if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr); + } + } +# if should not continue a brace + if ($line =~ /}\s*if\b/) { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . + $herecurr); + } +# case and default should not have general statements after them + if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g && + $line !~ /\G(?: + (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$| + \s*return\s+ + )/xg) + { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr); + } + + # Check for }else {, these must be at the same + # indent level to be relevant to each other. + if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and + $previndent == $indent) { + ERROR("ELSE_AFTER_BRACE", + "else should follow close brace '}'\n" . $hereprev); + } + + if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and + $previndent == $indent) { + my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); + + # Find out what is on the end of the line after the + # conditional. + substr($s, 0, length($c), ''); + $s =~ s/\n.*//g; + + if ($s =~ /^\s*;/) { + ERROR("WHILE_AFTER_BRACE", + "while should follow close brace '}'\n" . $hereprev); + } + } + +#Specific variable tests + while ($line =~ m{($Constant|$Lval)}g) { + my $var = $1; + +#gcc binary extension + if ($var =~ /^$Binary$/) { + if (WARN("GCC_BINARY_CONSTANT", + "Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) && + $fix) { + my $hexval = sprintf("0x%x", oct($var)); + $fixed[$linenr - 1] =~ + s/\b$var\b/$hexval/; + } + } + +#CamelCase + if ($var !~ /^$Constant$/ && + $var =~ /[A-Z][a-z]|[a-z][A-Z]/ && +#Ignore Page variants + $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && +#Ignore SI style variants like nS, mV and dB (ie: max_uV, regulator_min_uA_show) + $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/) { + while ($var =~ m{($Ident)}g) { + my $word = $1; + next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/); + if ($check) { + seed_camelcase_includes(); + if (!$file && !$camelcase_file_seeded) { + seed_camelcase_file($realfile); + $camelcase_file_seeded = 1; + } + } + if (!defined $camelcase{$word}) { + $camelcase{$word} = 1; + CHK("CAMELCASE", + "Avoid CamelCase: <$word>\n" . $herecurr); + } + } + } + } + +#no spaces allowed after \ in define + if ($line =~ /\#\s*define.*\\\s+$/) { + if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION", + "Whitespace after \\ makes next lines useless\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\s+$//; + } + } + +#warn if is #included and is available (uses RAW line) + if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\}) { + my $file = "$1.h"; + my $checkfile = "include/linux/$file"; + if (-f "$root/$checkfile" && + $realfile ne $checkfile && + $1 !~ /$allowed_asm_includes/) + { + if ($realfile =~ m{^arch/}) { + CHK("ARCH_INCLUDE_LINUX", + "Consider using #include instead of \n" . $herecurr); + } else { + WARN("INCLUDE_LINUX", + "Use #include instead of \n" . $herecurr); + } + } + } + +# multi-statement macros should be enclosed in a do while loop, grab the +# first statement and ensure its the whole macro if its not enclosed +# in a known good container + if ($realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; + #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; + #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; + + $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//; + $dstat =~ s/$;//g; + $dstat =~ s/\\\n.//g; + $dstat =~ s/^\s*//s; + $dstat =~ s/\s*$//s; + + # Flatten any parentheses and braces + while ($dstat =~ s/\([^\(\)]*\)/1/ || + $dstat =~ s/\{[^\{\}]*\}/1/ || + $dstat =~ s/\[[^\[\]]*\]/1/) + { + } + + # Flatten any obvious string concatentation. + while ($dstat =~ s/("X*")\s*$Ident/$1/ || + $dstat =~ s/$Ident\s*("X*")/$1/) + { + } + + my $exceptions = qr{ + $Declare| + module_param_named| + MODULE_PARM_DESC| + DECLARE_PER_CPU| + DEFINE_PER_CPU| + __typeof__\(| + union| + struct| + \.$Ident\s*=\s*| + ^\"|\"$ + }x; + #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; + if ($dstat ne '' && + $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), + $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); + $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz + $dstat !~ /^'X'$/ && # character constants + $dstat !~ /$exceptions/ && + $dstat !~ /^\.$Ident\s*=/ && # .foo = + $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo + $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) + $dstat !~ /^for\s*$Constant$/ && # for (...) + $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() + $dstat !~ /^do\s*{/ && # do {... + $dstat !~ /^\({/ && # ({... + $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/) + { + $ctx =~ s/\n*$//; + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($ctx); + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + if ($dstat =~ /;/) { + ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", + "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); + } else { + ERROR("COMPLEX_MACRO", + "Macros with complex values should be enclosed in parenthesis\n" . "$herectx"); + } + } + +# check for line continuations outside of #defines, preprocessor #, and asm + + } else { + if ($prevline !~ /^..*\\$/ && + $line !~ /^\+\s*\#.*\\$/ && # preprocessor + $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm + $line =~ /^\+.*\\$/) { + WARN("LINE_CONTINUATIONS", + "Avoid unnecessary line continuations\n" . $herecurr); + } + } + +# do {} while (0) macro tests: +# single-statement macros do not need to be enclosed in do while (0) loop, +# macro should not end with a semicolon + if ($^V && $^V ge 5.10.0 && + $realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; + + $dstat =~ s/\\\n.//g; + + if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { + my $stmts = $2; + my $semis = $3; + + $ctx =~ s/\n*$//; + my $cnt = statement_rawlines($ctx); + my $herectx = $here . "\n"; + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + if (($stmts =~ tr/;/;/) == 1 && + $stmts !~ /^\s*(if|while|for|switch)\b/) { + WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", + "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); + } + if (defined $semis && $semis ne "") { + WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", + "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); + } + } + } + +# make sure symbols are always wrapped with VMLINUX_SYMBOL() ... +# all assignments may have only one of the following with an assignment: +# . +# ALIGN(...) +# VMLINUX_SYMBOL(...) + if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) { + WARN("MISSING_VMLINUX_SYMBOL", + "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr); + } + +# check for redundant bracing round if etc + if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) { + my ($level, $endln, @chunks) = + ctx_statement_full($linenr, $realcnt, 1); + #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; + #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n"; + if ($#chunks > 0 && $level == 0) { + my @allowed = (); + my $allow = 0; + my $seen = 0; + my $herectx = $here . "\n"; + my $ln = $linenr - 1; + for my $chunk (@chunks) { + my ($cond, $block) = @{$chunk}; + + # If the condition carries leading newlines, then count those as offsets. + my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); + my $offset = statement_rawlines($whitespace) - 1; + + $allowed[$allow] = 0; + #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; + + # We have looked at and allowed this specific line. + $suppress_ifbraces{$ln + $offset} = 1; + + $herectx .= "$rawlines[$ln + $offset]\n[...]\n"; + $ln += statement_rawlines($block) - 1; + + substr($block, 0, length($cond), ''); + + $seen++ if ($block =~ /^\s*{/); + + #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; + if (statement_lines($cond) > 1) { + #print "APW: ALLOWED: cond<$cond>\n"; + $allowed[$allow] = 1; + } + if ($block =~/\b(?:if|for|while)\b/) { + #print "APW: ALLOWED: block<$block>\n"; + $allowed[$allow] = 1; + } + if (statement_block_size($block) > 1) { + #print "APW: ALLOWED: lines block<$block>\n"; + $allowed[$allow] = 1; + } + $allow++; + } + if ($seen) { + my $sum_allowed = 0; + foreach (@allowed) { + $sum_allowed += $_; + } + if ($sum_allowed == 0) { + WARN("BRACES", + "braces {} are not necessary for any arm of this statement\n" . $herectx); + } elsif ($sum_allowed != $allow && + $seen != $allow) { + CHK("BRACES", + "braces {} should be used on all arms of this statement\n" . $herectx); + } + } + } + } + if (!defined $suppress_ifbraces{$linenr - 1} && + $line =~ /\b(if|while|for|else)\b/) { + my $allowed = 0; + + # Check the pre-context. + if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) { + #print "APW: ALLOWED: pre<$1>\n"; + $allowed = 1; + } + + my ($level, $endln, @chunks) = + ctx_statement_full($linenr, $realcnt, $-[0]); + + # Check the condition. + my ($cond, $block) = @{$chunks[0]}; + #print "CHECKING<$linenr> cond<$cond> block<$block>\n"; + if (defined $cond) { + substr($block, 0, length($cond), ''); + } + if (statement_lines($cond) > 1) { + #print "APW: ALLOWED: cond<$cond>\n"; + $allowed = 1; + } + if ($block =~/\b(?:if|for|while)\b/) { + #print "APW: ALLOWED: block<$block>\n"; + $allowed = 1; + } + if (statement_block_size($block) > 1) { + #print "APW: ALLOWED: lines block<$block>\n"; + $allowed = 1; + } + # Check the post-context. + if (defined $chunks[1]) { + my ($cond, $block) = @{$chunks[1]}; + if (defined $cond) { + substr($block, 0, length($cond), ''); + } + if ($block =~ /^\s*\{/) { + #print "APW: ALLOWED: chunk-1 block<$block>\n"; + $allowed = 1; + } + } + if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($block); + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + WARN("BRACES", + "braces {} are not necessary for single statement blocks\n" . $herectx); + } + } + +# check for unnecessary blank lines around braces + if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) { + CHK("BRACES", + "Blank lines aren't necessary before a close brace '}'\n" . $hereprev); + } + if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { + CHK("BRACES", + "Blank lines aren't necessary after an open brace '{'\n" . $hereprev); + } + +# no volatiles please + my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; + if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { + WARN("VOLATILE", + "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr); + } + +# warn about #if 0 + if ($line =~ /^.\s*\#\s*if\s+0\b/) { + CHK("REDUNDANT_CODE", + "if this code is redundant consider removing it\n" . + $herecurr); + } + +# check for needless "if () fn()" uses + if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { + my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;'; + if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) { + WARN('NEEDLESS_IF', + "$1(NULL) is safe this check is probably not required\n" . $hereprev); + } + } + +# check for bad placement of section $InitAttribute (e.g.: __initdata) + if ($line =~ /(\b$InitAttribute\b)/) { + my $attr = $1; + if ($line =~ /^\+\s*static\s+(?:const\s+)?(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*[=;]/) { + my $ptr = $1; + my $var = $2; + if ((($ptr =~ /\b(union|struct)\s+$attr\b/ && + ERROR("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr)) || + ($ptr !~ /\b(union|struct)\s+$attr\b/ && + WARN("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr))) && + $fix) { + $fixed[$linenr - 1] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e; + } + } + } + +# check for $InitAttributeData (ie: __initdata) with const + if ($line =~ /\bconst\b/ && $line =~ /($InitAttributeData)/) { + my $attr = $1; + $attr =~ /($InitAttributePrefix)(.*)/; + my $attr_prefix = $1; + my $attr_type = $2; + if (ERROR("INIT_ATTRIBUTE", + "Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/$InitAttributeData/${attr_prefix}initconst/; + } + } + +# check for $InitAttributeConst (ie: __initconst) without const + if ($line !~ /\bconst\b/ && $line =~ /($InitAttributeConst)/) { + my $attr = $1; + if (ERROR("INIT_ATTRIBUTE", + "Use of $attr requires a separate use of const\n" . $herecurr) && + $fix) { + my $lead = $fixed[$linenr - 1] =~ + /(^\+\s*(?:static\s+))/; + $lead = rtrim($1); + $lead = "$lead " if ($lead !~ /^\+$/); + $lead = "${lead}const "; + $fixed[$linenr - 1] =~ s/(^\+\s*(?:static\s+))/$lead/; + } + } + +# prefer usleep_range over udelay + if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { + # ignore udelay's < 10, however + if (! ($1 < 10) ) { + CHK("USLEEP_RANGE", + "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line); + } + } + +# warn about unexpectedly long msleep's + if ($line =~ /\bmsleep\s*\((\d+)\);/) { + if ($1 < 20) { + WARN("MSLEEP", + "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line); + } + } + +# check for comparisons of jiffies + if ($line =~ /\bjiffies\s*$Compare|$Compare\s*jiffies\b/) { + WARN("JIFFIES_COMPARISON", + "Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\n" . $herecurr); + } + +# check for comparisons of get_jiffies_64() + if ($line =~ /\bget_jiffies_64\s*\(\s*\)\s*$Compare|$Compare\s*get_jiffies_64\s*\(\s*\)/) { + WARN("JIFFIES_COMPARISON", + "Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\n" . $herecurr); + } + +# warn about #ifdefs in C files +# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { +# print "#ifdef in C files should be avoided\n"; +# print "$herecurr"; +# $clean = 0; +# } + +# warn about spacing in #ifdefs + if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { + if (ERROR("SPACING", + "exactly one space required after that #$1\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ + s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /; + } + + } + +# check for spinlock_t definitions without a comment. + if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ || + $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) { + my $which = $1; + if (!ctx_has_comment($first_line, $linenr)) { + CHK("UNCOMMENTED_DEFINITION", + "$1 definition without comment\n" . $herecurr); + } + } +# check for memory barriers without a comment. + if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + WARN("MEMORY_BARRIER", + "memory barrier without comment\n" . $herecurr); + } + } +# check of hardware specific defines + if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { + CHK("ARCH_DEFINES", + "architecture specific defines should be avoided\n" . $herecurr); + } + +# Check that the storage class is at the beginning of a declaration + if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { + WARN("STORAGE_CLASS", + "storage class should be at the beginning of the declaration\n" . $herecurr) + } + +# check the location of the inline attribute, that it is between +# storage class and type. + if ($line =~ /\b$Type\s+$Inline\b/ || + $line =~ /\b$Inline\s+$Storage\b/) { + ERROR("INLINE_LOCATION", + "inline keyword should sit between storage class and type\n" . $herecurr); + } + +# Check for __inline__ and __inline, prefer inline + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b(__inline__|__inline)\b/) { + if (WARN("INLINE", + "plain inline is preferred over $1\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b(__inline__|__inline)\b/inline/; + + } + } + +# Check for __attribute__ packed, prefer __packed + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { + WARN("PREFER_PACKED", + "__packed is preferred over __attribute__((packed))\n" . $herecurr); + } +# Check for new packed members, warn to use care + if ($line =~ /\b(__attribute__\s*\(\s*\(.*\bpacked|__packed)\b/) { + WARN("NEW_PACKED", + "Adding new packed members is to be done with care\n" . $herecurr); + } + +# Check for __attribute__ aligned, prefer __aligned + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { + WARN("PREFER_ALIGNED", + "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); + } + +# Check for __attribute__ format(printf, prefer __printf + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { + if (WARN("PREFER_PRINTF", + "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex; + + } + } + +# Check for __attribute__ format(scanf, prefer __scanf + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { + if (WARN("PREFER_SCANF", + "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex; + } + } + +# check for sizeof(&) + if ($line =~ /\bsizeof\s*\(\s*\&/) { + WARN("SIZEOF_ADDRESS", + "sizeof(& should be avoided\n" . $herecurr); + } + +# check for sizeof without parenthesis + if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { + if (WARN("SIZEOF_PARENTHESIS", + "sizeof $1 should be sizeof($1)\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex; + } + } + +# check for line continuations in quoted strings with odd counts of " + if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { + WARN("LINE_CONTINUATIONS", + "Avoid line continuations in quoted strings\n" . $herecurr); + } + +# check for struct spinlock declarations + if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { + WARN("USE_SPINLOCK_T", + "struct spinlock should be spinlock_t\n" . $herecurr); + } + +# check for seq_printf uses that could be seq_puts + if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) { + my $fmt = get_quoted_string($line, $rawline); + if ($fmt ne "" && $fmt !~ /[^\\]\%/) { + if (WARN("PREFER_SEQ_PUTS", + "Prefer seq_puts to seq_printf\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\bseq_printf\b/seq_puts/; + } + } + } + +# Check for misused memsets + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) { + + my $ms_addr = $2; + my $ms_val = $7; + my $ms_size = $12; + + if ($ms_size =~ /^(0x|)0$/i) { + ERROR("MEMSET", + "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); + } elsif ($ms_size =~ /^(0x|)1$/i) { + WARN("MEMSET", + "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); + } + } + +# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar) + if ($^V && $^V ge 5.10.0 && + $line =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/s) { + if (WARN("PREFER_ETHER_ADDR_COPY", + "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/; + } + } + +# typecasts on min/max could be min_t/max_t + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { + if (defined $2 || defined $7) { + my $call = $1; + my $cast1 = deparenthesize($2); + my $arg1 = $3; + my $cast2 = deparenthesize($7); + my $arg2 = $8; + my $cast; + + if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { + $cast = "$cast1 or $cast2"; + } elsif ($cast1 ne "") { + $cast = $cast1; + } else { + $cast = $cast2; + } + WARN("MINMAX", + "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); + } + } + +# check usleep_range arguments + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { + my $min = $1; + my $max = $7; + if ($min eq $max) { + WARN("USLEEP_RANGE", + "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); + } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && + $min > $max) { + WARN("USLEEP_RANGE", + "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); + } + } + +# check for naked sscanf + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /\bsscanf\b/ && + ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ && + $stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ && + $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = raw_line($linenr, 0); + for (my $count = $linenr + 1; $count <= $lc; $count++) { + $stat_real = $stat_real . "\n" . raw_line($count, 0); + } + WARN("NAKED_SSCANF", + "unchecked sscanf return value\n" . "$here\n$stat_real\n"); + } + +# check for new externs in .h files. + if ($realfile =~ /\.h$/ && + $line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) { + if (CHK("AVOID_EXTERNS", + "extern prototypes should be avoided in .h files\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/(.*)\bextern\b\s*(.*)/$1$2/; + } + } + +# check for new externs in .c files. + if ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) + { + my $function_name = $1; + my $paren_space = $2; + + my $s = $stat; + if (defined $cond) { + substr($s, 0, length($cond), ''); + } + if ($s =~ /^\s*;/ && + $function_name ne 'uninitialized_var') + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); + } + + if ($paren_space =~ /\n/) { + WARN("FUNCTION_ARGUMENTS", + "arguments for function declarations should follow identifier\n" . $herecurr); + } + + } elsif ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*extern\s+/) + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); + } + +# checks for new __setup's + if ($rawline =~ /\b__setup\("([^"]*)"/) { + my $name = $1; + + if (!grep(/$name/, @setup_docs)) { + CHK("UNDOCUMENTED_SETUP", + "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr); + } + } + +# check for pointless casting of kmalloc return + if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) { + WARN("UNNECESSARY_CASTS", + "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); + } + +# alloc style +# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...) + if ($^V && $^V ge 5.10.0 && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) { + CHK("ALLOC_SIZEOF_STRUCT", + "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr); + } + +# check for krealloc arg reuse + if ($^V && $^V ge 5.10.0 && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) { + WARN("KREALLOC_ARG_REUSE", + "Reusing the krealloc arg is almost always a bug\n" . $herecurr); + } + +# check for alloc argument mismatch + if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { + WARN("ALLOC_ARRAY_ARGS", + "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); + } + +# check for GFP_NOWAIT use + if ($line =~ /\b__GFP_NOFAIL\b/) { + WARN("__GFP_NOFAIL", + "Use of __GFP_NOFAIL is deprecated, no new users should be added\n" . $herecurr); + } + +# check for multiple semicolons + if ($line =~ /;\s*;\s*$/) { + if (WARN("ONE_SEMICOLON", + "Statements terminations use 1 semicolon\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/(\s*;\s*){2,}$/;/g; + } + } + +# check for case / default statements not preceeded by break/fallthrough/switch + if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { + my $has_break = 0; + my $has_statement = 0; + my $count = 0; + my $prevline = $linenr; + while ($prevline > 1 && $count < 3 && !$has_break) { + $prevline--; + my $rline = $rawlines[$prevline - 1]; + my $fline = $lines[$prevline - 1]; + last if ($fline =~ /^\@\@/); + next if ($fline =~ /^\-/); + next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/); + $has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i); + next if ($fline =~ /^.[\s$;]*$/); + $has_statement = 1; + $count++; + $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|return\b|goto\b|continue\b)/); + } + if (!$has_break && $has_statement) { + WARN("MISSING_BREAK", + "Possible switch case/default not preceeded by break or fallthrough comment\n" . $herecurr); + } + } + +# check for switch/default statements without a break; + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { + my $ctx = ''; + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($stat); + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + WARN("DEFAULT_NO_BREAK", + "switch default: should use break\n" . $herectx); + } + +# check for gcc specific __FUNCTION__ + if ($line =~ /\b__FUNCTION__\b/) { + if (WARN("USE_FUNC", + "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr) && + $fix) { + $fixed[$linenr - 1] =~ s/\b__FUNCTION__\b/__func__/g; + } + } + +# check for use of yield() + if ($line =~ /\byield\s*\(\s*\)/) { + WARN("YIELD", + "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); + } + +# check for comparisons against true and false + if ($line =~ /\+\s*(.*?)\b(true|false|$Lval)\s*(==|\!=)\s*(true|false|$Lval)\b(.*)$/i) { + my $lead = $1; + my $arg = $2; + my $test = $3; + my $otype = $4; + my $trail = $5; + my $op = "!"; + + ($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i); + + my $type = lc($otype); + if ($type =~ /^(?:true|false)$/) { + if (("$test" eq "==" && "$type" eq "true") || + ("$test" eq "!=" && "$type" eq "false")) { + $op = ""; + } + + CHK("BOOL_COMPARISON", + "Using comparison to $otype is error prone\n" . $herecurr); + +## maybe suggesting a correct construct would better +## "Using comparison to $otype is error prone. Perhaps use '${lead}${op}${arg}${trail}'\n" . $herecurr); + + } + } + +# check for semaphores initialized locked + if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { + WARN("CONSIDER_COMPLETION", + "consider using a completion\n" . $herecurr); + } + +# recommend kstrto* over simple_strto* and strict_strto* + if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { + WARN("CONSIDER_KSTRTO", + "$1 is obsolete, use k$3 instead\n" . $herecurr); + } + +# check for __initcall(), use device_initcall() explicitly please + if ($line =~ /^.\s*__initcall\s*\(/) { + WARN("USE_DEVICE_INITCALL", + "please use device_initcall() instead of __initcall()\n" . $herecurr); + } + +# check for various ops structs, ensure they are const. + my $struct_ops = qr{acpi_dock_ops| + address_space_operations| + backlight_ops| + block_device_operations| + dentry_operations| + dev_pm_ops| + dma_map_ops| + extent_io_ops| + file_lock_operations| + file_operations| + hv_ops| + ide_dma_ops| + intel_dvo_dev_ops| + item_operations| + iwl_ops| + kgdb_arch| + kgdb_io| + kset_uevent_ops| + lock_manager_operations| + microcode_ops| + mtrr_ops| + neigh_ops| + nlmsvc_binding| + pci_raw_ops| + pipe_buf_operations| + platform_hibernation_ops| + platform_suspend_ops| + proto_ops| + rpc_pipe_ops| + seq_operations| + snd_ac97_build_ops| + soc_pcmcia_socket_ops| + stacktrace_ops| + sysfs_ops| + tty_operations| + usb_mon_operations| + wd_ops}x; + if ($line !~ /\bconst\b/ && + $line =~ /\bstruct\s+($struct_ops)\b/) { + WARN("CONST_STRUCT", + "struct $1 should normally be const\n" . + $herecurr); + } + +# use of NR_CPUS is usually wrong +# ignore definitions of NR_CPUS and usage to define arrays as likely right + if ($line =~ /\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) + { + WARN("NR_CPUS", + "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); + } + +# Use of __ARCH_HAS_ or ARCH_HAVE_ is wrong. + if ($line =~ /\+\s*#\s*define\s+((?:__)?ARCH_(?:HAS|HAVE)\w*)\b/) { + ERROR("DEFINE_ARCH_HAS", + "#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr); + } + +# check for %L{u,d,i} in strings + my $string; + while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { + $string = substr($rawline, $-[1], $+[1] - $-[1]); + $string =~ s/%%/__/g; + if ($string =~ /(?mutex.\n" . $herecurr); + } + } + + if ($line =~ /debugfs_create_file.*S_IWUGO/ || + $line =~ /DEVICE_ATTR.*S_IWUGO/ ) { + WARN("EXPORTED_WORLD_WRITABLE", + "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); + } + } + + # If we have no input at all, then there is nothing to report on + # so just keep quiet. + if ($#rawlines == -1) { + exit(0); + } + + # In mailback mode only produce a report in the negative, for + # things that appear to be patches. + if ($mailback && ($clean == 1 || !$is_patch)) { + exit(0); + } + + # This is not a patch, and we are are in 'no-patch' mode so + # just keep quiet. + if (!$chk_patch && !$is_patch) { + exit(0); + } + + if (!$is_patch) { + ERROR("NOT_UNIFIED_DIFF", + "Does not appear to be a unified-diff format patch\n"); + } + if ($is_patch && $chk_signoff && $signoff == 0) { + ERROR("MISSING_SIGN_OFF", + "Missing Signed-off-by: line(s)\n"); + } + + print report_dump(); + if ($summary && !($clean == 1 && $quiet == 1)) { + print "$filename " if ($summary_file); + print "total: $cnt_error errors, $cnt_warn warnings, " . + (($check)? "$cnt_chk checks, " : "") . + "$cnt_lines lines checked\n"; + print "\n" if ($quiet == 0); + } + + if ($quiet == 0) { + + if ($^V lt 5.10.0) { + print("NOTE: perl $^V is not modern enough to detect all possible issues.\n"); + print("An upgrade to at least perl v5.10.0 is suggested.\n\n"); + } + + # If there were whitespace errors which cleanpatch can fix + # then suggest that. + if ($rpt_cleaners) { + print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n"; + print " scripts/cleanfile\n\n"; + $rpt_cleaners = 0; + } + } + + hash_show_words(\%use_type, "Used"); + hash_show_words(\%ignore_type, "Ignored"); + + if ($clean == 0 && $fix && "@rawlines" ne "@fixed") { + my $newfile = $filename; + $newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace); + my $linecount = 0; + my $f; + + open($f, '>', $newfile) + or die "$P: Can't open $newfile for write\n"; + foreach my $fixed_line (@fixed) { + $linecount++; + if ($file) { + if ($linecount > 3) { + $fixed_line =~ s/^\+//; + print $f $fixed_line. "\n"; + } + } else { + print $f $fixed_line . "\n"; + } + } + close($f); + + if (!$quiet) { + print << "EOM"; +Wrote EXPERIMENTAL --fix correction(s) to '$newfile' + +Do _NOT_ trust the results written to this file. +Do _NOT_ submit these changes without inspecting them for correctness. + +This EXPERIMENTAL file is simply a convenience to help rewrite patches. +No warranties, expressed or implied... + +EOM + } + } + + if ($clean == 1 && $quiet == 0) { + print "$vname has no obvious style problems and is ready for submission.\n" + } + if ($clean == 0 && $quiet == 0) { + print << "EOM"; +$vname has style problems, please review. + +If any of these errors are false positives, please report +them to the maintainer, see CHECKPATCH in MAINTAINERS. +EOM + } + + return $clean; +} diff --git a/tools/checkstack.pl b/scripts/checkstack.pl similarity index 100% rename from tools/checkstack.pl rename to scripts/checkstack.pl diff --git a/tools/cleanpatch b/scripts/cleanpatch similarity index 100% rename from tools/cleanpatch rename to scripts/cleanpatch diff --git a/tools/kernel-doc/docproc.c b/scripts/docproc.c similarity index 91% rename from tools/kernel-doc/docproc.c rename to scripts/docproc.c index d4fc42e4cc..e267e62143 100644 --- a/tools/kernel-doc/docproc.c +++ b/scripts/docproc.c @@ -65,13 +65,14 @@ FILELINE * docsection; #define MAXLINESZ 2048 #define MAXFILES 250 -#define KERNELDOCPATH "tools/kernel-doc/" +#define KERNELDOCPATH "scripts/" #define KERNELDOC "kernel-doc" #define DOCBOOK "-docbook" #define LIST "-list" #define FUNCTION "-function" #define NOFUNCTION "-nofunction" #define NODOCSECTIONS "-no-doc-sections" +#define SHOWNOTFOUND "-show-not-found" static char *srctree, *kernsrctree; @@ -153,7 +154,7 @@ int symfilecnt = 0; static void add_new_symbol(struct symfile *sym, char * symname) { sym->symbollist = - realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *)); + realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *)); sym->symbollist[sym->symbolcnt++].name = strdup(symname); } @@ -214,7 +215,7 @@ static void find_export_symbols(char * filename) char *p; char *e; if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) || - ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) { + ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) { /* Skip EXPORT_SYMBOL{_GPL} */ while (isalnum(*p) || *p == '_') p++; @@ -290,24 +291,25 @@ static void extfunc(char * filename) { docfunctions(filename, FUNCTION); } static void singfunc(char * filename, char * line) { char *vec[200]; /* Enough for specific functions */ - int i, idx = 0; - int startofsym = 1; + int i, idx = 0; + int startofsym = 1; vec[idx++] = KERNELDOC; vec[idx++] = DOCBOOK; + vec[idx++] = SHOWNOTFOUND; - /* Split line up in individual parameters preceded by FUNCTION */ - for (i=0; line[i]; i++) { - if (isspace(line[i])) { - line[i] = '\0'; - startofsym = 1; - continue; - } - if (startofsym) { - startofsym = 0; - vec[idx++] = FUNCTION; - vec[idx++] = &line[i]; - } - } + /* Split line up in individual parameters preceded by FUNCTION */ + for (i=0; line[i]; i++) { + if (isspace(line[i])) { + line[i] = '\0'; + startofsym = 1; + continue; + } + if (startofsym) { + startofsym = 0; + vec[idx++] = FUNCTION; + vec[idx++] = &line[i]; + } + } for (i = 0; i < idx; i++) { if (strcmp(vec[i], FUNCTION)) continue; @@ -325,7 +327,8 @@ static void singfunc(char * filename, char * line) */ static void docsect(char *filename, char *line) { - char *vec[6]; /* kerneldoc -docbook -function "section" file NULL */ + /* kerneldoc -docbook -show-not-found -function "section" file NULL */ + char *vec[7]; char *s; for (s = line; *s; s++) @@ -341,10 +344,11 @@ static void docsect(char *filename, char *line) vec[0] = KERNELDOC; vec[1] = DOCBOOK; - vec[2] = FUNCTION; - vec[3] = line; - vec[4] = filename; - vec[5] = NULL; + vec[2] = SHOWNOTFOUND; + vec[3] = FUNCTION; + vec[4] = line; + vec[5] = filename; + vec[6] = NULL; exec_kernel_doc(vec); } @@ -456,14 +460,14 @@ static void parse_file(FILE *infile) break; case 'D': while (*s && !isspace(*s)) s++; - *s = '\0'; - symbolsonly(line+2); - break; + *s = '\0'; + symbolsonly(line+2); + break; case 'F': /* filename */ while (*s && !isspace(*s)) s++; *s++ = '\0'; - /* function names */ + /* function names */ while (isspace(*s)) s++; singlefunctions(line +2, s); @@ -511,11 +515,11 @@ int main(int argc, char *argv[]) } /* Open file, exit on error */ infile = fopen(argv[2], "r"); - if (infile == NULL) { - fprintf(stderr, "docproc: "); - perror(argv[2]); - exit(2); - } + if (infile == NULL) { + fprintf(stderr, "docproc: "); + perror(argv[2]); + exit(2); + } if (strcmp("doc", argv[1]) == 0) { /* Need to do this in two passes. diff --git a/tools/dtc-version.sh b/scripts/dtc-version.sh similarity index 100% rename from tools/dtc-version.sh rename to scripts/dtc-version.sh diff --git a/scripts/fill_scrapyard.py b/scripts/fill_scrapyard.py new file mode 100755 index 0000000000..9a94354941 --- /dev/null +++ b/scripts/fill_scrapyard.py @@ -0,0 +1,166 @@ +#!/usr/bin/env python2 +# +# Author: Masahiro Yamada +# +# SPDX-License-Identifier: GPL-2.0+ +# + +""" +Fill the "Commit" and "Removed" fields of doc/README.scrapyard + +The file doc/README.scrapyard is used to keep track of removed boards. + +When we remove support for boards, we are supposed to add entries to +doc/README.scrapyard leaving "Commit" and "Removed" fields blank. + +The "Commit" field is the commit hash in which the board was removed +and the "Removed" is the date at which the board was removed. Those +two are known only after the board removal patch was applied, thus they +need to be filled in later. + +This effectively means that the person who removes other boards is +supposed to fill in the blank fields before adding new entries to +doc/README.scrapyard. + +That is a really tedious task that should be automated. +This script fills the blank fields of doc/README.scrapyard for you! + +Usage: + +The "Commit" and "Removed" fields must be "-". The other fields should +have already been filled in by a former commit. + +Run + scripts/fill_scrapyard.py +""" + +import os +import subprocess +import sys +import tempfile + +DOC='doc/README.scrapyard' + +def get_last_modify_commit(file, line_num): + """Get the commit that last modified the given line. + + This function runs "git blame" against the given line of the given + file and returns the commit hash that last modified it. + + Arguments: + file: the file to be git-blame'd. + line_num: the line number to be git-blame'd. This line number + starts from 1, not 0. + + Returns: + Commit hash that last modified the line. The number of digits is + long enough to form a unique commit. + """ + result = subprocess.check_output(['git', 'blame', '-L', + '%d,%d' % (line_num, line_num), file]) + commit = result.split()[0] + + if commit[0] == '^': + sys.exit('%s: line %d: ' % (file, line_num) + + 'this line was modified before the beginning of git history') + + if commit == '0' * len(commit): + sys.exit('%s: line %d: locally modified\n' % (file, line_num) + + 'Please run this script in a clean repository.') + + return commit + +def get_committer_date(commit): + """Get the committer date of the given commit. + + This function returns the date when the given commit was applied. + + Arguments: + commit: commit-ish object. + + Returns: + The committer date of the given commit in the form YY-MM-DD. + """ + committer_date = subprocess.check_output(['git', 'show', '-s', + '--format=%ci', commit]) + return committer_date.split()[0] + +def move_to_topdir(): + """Change directory to the top of the git repository. + + Or, exit with an error message if called out of a git repository. + """ + try: + toplevel = subprocess.check_output(['git', 'rev-parse', + '--show-toplevel']) + except subprocess.CalledProcessError: + sys.exit('Please run in a git repository.') + + # strip '\n' + toplevel = toplevel.rstrip() + + # Change the current working directory to the toplevel of the respository + # for our easier life. + os.chdir(toplevel) + +class TmpFile: + + """Useful class to handle a temporary file. + + tempfile.mkstemp() is often used to create a unique temporary file, + but what is inconvenient is that the caller is responsible for + deleting the file when done with it. + + Even when the caller errors out on the way, the temporary file must + be deleted somehow. The idea here is that we delete the file in + the destructor of this class because the destructor is always + invoked when the instance of the class is freed. + """ + + def __init__(self): + """Constructor - create a temporary file""" + fd, self.filename = tempfile.mkstemp() + self.file = os.fdopen(fd, 'w') + + def __del__(self): + """Destructor - delete the temporary file""" + try: + os.remove(self.filename) + except: + pass + +def main(): + move_to_topdir() + + line_num = 1 + + tmpfile = TmpFile() + for line in open(DOC): + tmp = line.split(None, 5) + modified = False + + if len(tmp) >= 5: + # fill "Commit" field + if tmp[3] == '-': + tmp[3] = get_last_modify_commit(DOC, line_num) + modified = True + # fill "Removed" field + if tmp[4] == '-': + tmp[4] = get_committer_date(tmp[3]) + if modified: + line = tmp[0].ljust(17) + line += tmp[1].ljust(12) + line += tmp[2].ljust(15) + line += tmp[3].ljust(12) + line += tmp[4].ljust(12) + if len(tmp) >= 6: + line += tmp[5] + line = line.rstrip() + '\n' + + tmpfile.file.write(line) + line_num += 1 + + os.rename(tmpfile.filename, DOC) + +if __name__ == '__main__': + main() diff --git a/scripts/gcc-stack-usage.sh b/scripts/gcc-stack-usage.sh new file mode 100755 index 0000000000..27ac928969 --- /dev/null +++ b/scripts/gcc-stack-usage.sh @@ -0,0 +1,18 @@ +#!/bin/sh +# Test for gcc '-fstack-usage' support +# Copyright (C) 2013, Masahiro Yamada +# +# SPDX-License-Identifier: GPL-2.0+ +# + +TMP="$$" + +cat </dev/null 2>&1 \ + && echo "y" +int main(void) +{ + return 0; +} +END + +rm -f $TMP $TMP.su diff --git a/tools/gcc-version.sh b/scripts/gcc-version.sh similarity index 100% rename from tools/gcc-version.sh rename to scripts/gcc-version.sh diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl new file mode 100755 index 0000000000..368a20e2cc --- /dev/null +++ b/scripts/get_maintainer.pl @@ -0,0 +1,2269 @@ +#!/usr/bin/perl -w +# (c) 2007, Joe Perches +# created from checkpatch.pl +# +# Print selected MAINTAINERS information for +# the files modified in a patch or for a file +# +# usage: perl scripts/get_maintainer.pl [OPTIONS] +# perl scripts/get_maintainer.pl [OPTIONS] -f +# +# Licensed under the terms of the GNU GPL License version 2 + +use strict; + +my $P = $0; +my $V = '0.26'; + +use Getopt::Long qw(:config no_auto_abbrev); +use File::Find; + +my $lk_path = "./"; +my $email = 1; +my $email_usename = 1; +my $email_maintainer = 1; +my $email_list = 1; +my $email_subscriber_list = 0; +my $email_git_penguin_chiefs = 0; +my $email_git = 0; +my $email_git_all_signature_types = 0; +my $email_git_blame = 0; +my $email_git_blame_signatures = 1; +my $email_git_fallback = 1; +my $email_git_min_signatures = 1; +my $email_git_max_maintainers = 5; +my $email_git_min_percent = 5; +my $email_git_since = "1-year-ago"; +my $email_hg_since = "-365"; +my $interactive = 0; +my $email_remove_duplicates = 1; +my $email_use_mailmap = 1; +my $output_multiline = 1; +my $output_separator = ", "; +my $output_roles = 0; +my $output_rolestats = 1; +my $scm = 0; +my $web = 0; +my $subsystem = 0; +my $status = 0; +my $keywords = 1; +my $sections = 0; +my $file_emails = 0; +my $from_filename = 0; +my $pattern_depth = 0; +my $version = 0; +my $help = 0; + +my $vcs_used = 0; + +my $exit = 0; + +my %commit_author_hash; +my %commit_signer_hash; + +my @penguin_chief = (); +push(@penguin_chief, "Tom Rini:trini\@ti.com"); + +my @penguin_chief_names = (); +foreach my $chief (@penguin_chief) { + if ($chief =~ m/^(.*):(.*)/) { + my $chief_name = $1; + my $chief_addr = $2; + push(@penguin_chief_names, $chief_name); + } +} +my $penguin_chiefs = "\(" . join("|", @penguin_chief_names) . "\)"; + +# Signature types of people who are either +# a) responsible for the code in question, or +# b) familiar enough with it to give relevant feedback +my @signature_tags = (); +push(@signature_tags, "Signed-off-by:"); +push(@signature_tags, "Reviewed-by:"); +push(@signature_tags, "Acked-by:"); + +my $signature_pattern = "\(" . join("|", @signature_tags) . "\)"; + +# rfc822 email address - preloaded methods go here. +my $rfc822_lwsp = "(?:(?:\\r\\n)?[ \\t])"; +my $rfc822_char = '[\\000-\\377]'; + +# VCS command support: class-like functions and strings + +my %VCS_cmds; + +my %VCS_cmds_git = ( + "execute_cmd" => \&git_execute_cmd, + "available" => '(which("git") ne "") && (-e ".git")', + "find_signers_cmd" => + "git log --no-color --follow --since=\$email_git_since " . + '--numstat --no-merges ' . + '--format="GitCommit: %H%n' . + 'GitAuthor: %an <%ae>%n' . + 'GitDate: %aD%n' . + 'GitSubject: %s%n' . + '%b%n"' . + " -- \$file", + "find_commit_signers_cmd" => + "git log --no-color " . + '--numstat ' . + '--format="GitCommit: %H%n' . + 'GitAuthor: %an <%ae>%n' . + 'GitDate: %aD%n' . + 'GitSubject: %s%n' . + '%b%n"' . + " -1 \$commit", + "find_commit_author_cmd" => + "git log --no-color " . + '--numstat ' . + '--format="GitCommit: %H%n' . + 'GitAuthor: %an <%ae>%n' . + 'GitDate: %aD%n' . + 'GitSubject: %s%n"' . + " -1 \$commit", + "blame_range_cmd" => "git blame -l -L \$diff_start,+\$diff_length \$file", + "blame_file_cmd" => "git blame -l \$file", + "commit_pattern" => "^GitCommit: ([0-9a-f]{40,40})", + "blame_commit_pattern" => "^([0-9a-f]+) ", + "author_pattern" => "^GitAuthor: (.*)", + "subject_pattern" => "^GitSubject: (.*)", + "stat_pattern" => "^(\\d+)\\t(\\d+)\\t\$file\$", +); + +my %VCS_cmds_hg = ( + "execute_cmd" => \&hg_execute_cmd, + "available" => '(which("hg") ne "") && (-d ".hg")', + "find_signers_cmd" => + "hg log --date=\$email_hg_since " . + "--template='HgCommit: {node}\\n" . + "HgAuthor: {author}\\n" . + "HgSubject: {desc}\\n'" . + " -- \$file", + "find_commit_signers_cmd" => + "hg log " . + "--template='HgSubject: {desc}\\n'" . + " -r \$commit", + "find_commit_author_cmd" => + "hg log " . + "--template='HgCommit: {node}\\n" . + "HgAuthor: {author}\\n" . + "HgSubject: {desc|firstline}\\n'" . + " -r \$commit", + "blame_range_cmd" => "", # not supported + "blame_file_cmd" => "hg blame -n \$file", + "commit_pattern" => "^HgCommit: ([0-9a-f]{40,40})", + "blame_commit_pattern" => "^([ 0-9a-f]+):", + "author_pattern" => "^HgAuthor: (.*)", + "subject_pattern" => "^HgSubject: (.*)", + "stat_pattern" => "^(\\d+)\t(\\d+)\t\$file\$", +); + +my $conf = which_conf(".get_maintainer.conf"); +if (-f $conf) { + my @conf_args; + open(my $conffile, '<', "$conf") + or warn "$P: Can't find a readable .get_maintainer.conf file $!\n"; + + while (<$conffile>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + $line =~ s/\s+/ /g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + + my @words = split(" ", $line); + foreach my $word (@words) { + last if ($word =~ m/^#/); + push (@conf_args, $word); + } + } + close($conffile); + unshift(@ARGV, @conf_args) if @conf_args; +} + +if (!GetOptions( + 'email!' => \$email, + 'git!' => \$email_git, + 'git-all-signature-types!' => \$email_git_all_signature_types, + 'git-blame!' => \$email_git_blame, + 'git-blame-signatures!' => \$email_git_blame_signatures, + 'git-fallback!' => \$email_git_fallback, + 'git-chief-penguins!' => \$email_git_penguin_chiefs, + 'git-min-signatures=i' => \$email_git_min_signatures, + 'git-max-maintainers=i' => \$email_git_max_maintainers, + 'git-min-percent=i' => \$email_git_min_percent, + 'git-since=s' => \$email_git_since, + 'hg-since=s' => \$email_hg_since, + 'i|interactive!' => \$interactive, + 'remove-duplicates!' => \$email_remove_duplicates, + 'mailmap!' => \$email_use_mailmap, + 'm!' => \$email_maintainer, + 'n!' => \$email_usename, + 'l!' => \$email_list, + 's!' => \$email_subscriber_list, + 'multiline!' => \$output_multiline, + 'roles!' => \$output_roles, + 'rolestats!' => \$output_rolestats, + 'separator=s' => \$output_separator, + 'subsystem!' => \$subsystem, + 'status!' => \$status, + 'scm!' => \$scm, + 'web!' => \$web, + 'pattern-depth=i' => \$pattern_depth, + 'k|keywords!' => \$keywords, + 'sections!' => \$sections, + 'fe|file-emails!' => \$file_emails, + 'f|file' => \$from_filename, + 'v|version' => \$version, + 'h|help|usage' => \$help, + )) { + die "$P: invalid argument - use --help if necessary\n"; +} + +if ($help != 0) { + usage(); + exit 0; +} + +if ($version != 0) { + print("${P} ${V}\n"); + exit 0; +} + +if (-t STDIN && !@ARGV) { + # We're talking to a terminal, but have no command line arguments. + die "$P: missing patchfile or -f file - use --help if necessary\n"; +} + +$output_multiline = 0 if ($output_separator ne ", "); +$output_rolestats = 1 if ($interactive); +$output_roles = 1 if ($output_rolestats); + +if ($sections) { + $email = 0; + $email_list = 0; + $scm = 0; + $status = 0; + $subsystem = 0; + $web = 0; + $keywords = 0; + $interactive = 0; +} else { + my $selections = $email + $scm + $status + $subsystem + $web; + if ($selections == 0) { + die "$P: Missing required option: email, scm, status, subsystem or web\n"; + } +} + +if ($email && + ($email_maintainer + $email_list + $email_subscriber_list + + $email_git + $email_git_penguin_chiefs + $email_git_blame) == 0) { + die "$P: Please select at least 1 email option\n"; +} + +if (!top_of_kernel_tree($lk_path)) { + die "$P: The current directory does not appear to be " + . "a linux kernel source tree.\n"; +} + +## Read MAINTAINERS for type/value pairs + +my @typevalue = (); +my %keyword_hash; + +my @maint_files = (); +push(@maint_files, "${lk_path}MAINTAINERS"); + +sub maint_wanted { + return unless $_ =~ /^MAINTAINERS/; + push(@maint_files, "$File::Find::name"); +} + +File::Find::find(\&maint_wanted, "${lk_path}board"); + +foreach my $maint_file (@maint_files) { + my $maint; + open ($maint, '<', "$maint_file") + or die "$P: Can't open $maint_file: $!\n"; + read_maintainers($maint); + close($maint); +} + +sub read_maintainers { + my ($maint) = @_; + + while (<$maint>) { + my $line = $_; + + if ($line =~ m/^(\C):\s*(.*)/) { + my $type = $1; + my $value = $2; + + ##Filename pattern matching + if ($type eq "F" || $type eq "X") { + $value =~ s@\.@\\\.@g; ##Convert . to \. + $value =~ s/\*/\.\*/g; ##Convert * to .* + $value =~ s/\?/\./g; ##Convert ? to . + ##if pattern is a directory and it lacks a trailing slash, add one + if ((-d $value)) { + $value =~ s@([^/])$@$1/@; + } + } elsif ($type eq "K") { + $keyword_hash{@typevalue} = $value; + } + push(@typevalue, "$type:$value"); + } elsif (!/^(\s)*$/) { + $line =~ s/\n$//g; + push(@typevalue, $line); + } + } +} + + +# +# Read mail address map +# + +my $mailmap; + +read_mailmap(); + +sub read_mailmap { + $mailmap = { + names => {}, + addresses => {} + }; + + return if (!$email_use_mailmap || !(-f "${lk_path}.mailmap")); + + open(my $mailmap_file, '<', "${lk_path}.mailmap") + or warn "$P: Can't open .mailmap: $!\n"; + + while (<$mailmap_file>) { + s/#.*$//; #strip comments + s/^\s+|\s+$//g; #trim + + next if (/^\s*$/); #skip empty lines + #entries have one of the following formats: + # name1 + # + # name1 + # name1 name2 + # (see man git-shortlog) + + if (/^([^<]+)<([^>]+)>$/) { + my $real_name = $1; + my $address = $2; + + $real_name =~ s/\s+$//; + ($real_name, $address) = parse_email("$real_name <$address>"); + $mailmap->{names}->{$address} = $real_name; + + } elsif (/^<([^>]+)>\s*<([^>]+)>$/) { + my $real_address = $1; + my $wrong_address = $2; + + $mailmap->{addresses}->{$wrong_address} = $real_address; + + } elsif (/^(.+)<([^>]+)>\s*<([^>]+)>$/) { + my $real_name = $1; + my $real_address = $2; + my $wrong_address = $3; + + $real_name =~ s/\s+$//; + ($real_name, $real_address) = + parse_email("$real_name <$real_address>"); + $mailmap->{names}->{$wrong_address} = $real_name; + $mailmap->{addresses}->{$wrong_address} = $real_address; + + } elsif (/^(.+)<([^>]+)>\s*(.+)\s*<([^>]+)>$/) { + my $real_name = $1; + my $real_address = $2; + my $wrong_name = $3; + my $wrong_address = $4; + + $real_name =~ s/\s+$//; + ($real_name, $real_address) = + parse_email("$real_name <$real_address>"); + + $wrong_name =~ s/\s+$//; + ($wrong_name, $wrong_address) = + parse_email("$wrong_name <$wrong_address>"); + + my $wrong_email = format_email($wrong_name, $wrong_address, 1); + $mailmap->{names}->{$wrong_email} = $real_name; + $mailmap->{addresses}->{$wrong_email} = $real_address; + } + } + close($mailmap_file); +} + +## use the filenames on the command line or find the filenames in the patchfiles + +my @files = (); +my @range = (); +my @keyword_tvi = (); +my @file_emails = (); + +if (!@ARGV) { + push(@ARGV, "&STDIN"); +} + +foreach my $file (@ARGV) { + if ($file ne "&STDIN") { + ##if $file is a directory and it lacks a trailing slash, add one + if ((-d $file)) { + $file =~ s@([^/])$@$1/@; + } elsif (!(-f $file)) { + die "$P: file '${file}' not found\n"; + } + } + if ($from_filename) { + push(@files, $file); + if ($file ne "MAINTAINERS" && -f $file && ($keywords || $file_emails)) { + open(my $f, '<', $file) + or die "$P: Can't open $file: $!\n"; + my $text = do { local($/) ; <$f> }; + close($f); + if ($keywords) { + foreach my $line (keys %keyword_hash) { + if ($text =~ m/$keyword_hash{$line}/x) { + push(@keyword_tvi, $line); + } + } + } + if ($file_emails) { + my @poss_addr = $text =~ m$[A-Za-zÀ-ÿ\"\' \,\.\+-]*\s*[\,]*\s*[\(\<\{]{0,1}[A-Za-z0-9_\.\+-]+\@[A-Za-z0-9\.-]+\.[A-Za-z0-9]+[\)\>\}]{0,1}$g; + push(@file_emails, clean_file_emails(@poss_addr)); + } + } + } else { + my $file_cnt = @files; + my $lastfile; + + open(my $patch, "< $file") + or die "$P: Can't open $file: $!\n"; + + # We can check arbitrary information before the patch + # like the commit message, mail headers, etc... + # This allows us to match arbitrary keywords against any part + # of a git format-patch generated file (subject tags, etc...) + + my $patch_prefix = ""; #Parsing the intro + + while (<$patch>) { + my $patch_line = $_; + if (m/^\+\+\+\s+(\S+)/ or m/^---\s+(\S+)/) { + my $filename = $1; + $filename =~ s@^[^/]*/@@; + $filename =~ s@\n@@; + $lastfile = $filename; + push(@files, $filename); + $patch_prefix = "^[+-].*"; #Now parsing the actual patch + } elsif (m/^\@\@ -(\d+),(\d+)/) { + if ($email_git_blame) { + push(@range, "$lastfile:$1:$2"); + } + } elsif ($keywords) { + foreach my $line (keys %keyword_hash) { + if ($patch_line =~ m/${patch_prefix}$keyword_hash{$line}/x) { + push(@keyword_tvi, $line); + } + } + } + } + close($patch); + + if ($file_cnt == @files) { + warn "$P: file '${file}' doesn't appear to be a patch. " + . "Add -f to options?\n"; + } + @files = sort_and_uniq(@files); + } +} + +@file_emails = uniq(@file_emails); + +my %email_hash_name; +my %email_hash_address; +my @email_to = (); +my %hash_list_to; +my @list_to = (); +my @scm = (); +my @web = (); +my @subsystem = (); +my @status = (); +my %deduplicate_name_hash = (); +my %deduplicate_address_hash = (); + +my @maintainers = get_maintainers(); + +if (@maintainers) { + @maintainers = merge_email(@maintainers); + output(@maintainers); +} + +if ($scm) { + @scm = uniq(@scm); + output(@scm); +} + +if ($status) { + @status = uniq(@status); + output(@status); +} + +if ($subsystem) { + @subsystem = uniq(@subsystem); + output(@subsystem); +} + +if ($web) { + @web = uniq(@web); + output(@web); +} + +exit($exit); + +sub range_is_maintained { + my ($start, $end) = @_; + + for (my $i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ m/^(\C):\s*(.*)/) { + my $type = $1; + my $value = $2; + if ($type eq 'S') { + if ($value =~ /(maintain|support)/i) { + return 1; + } + } + } + } + return 0; +} + +sub range_has_maintainer { + my ($start, $end) = @_; + + for (my $i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ m/^(\C):\s*(.*)/) { + my $type = $1; + my $value = $2; + if ($type eq 'M') { + return 1; + } + } + } + return 0; +} + +sub get_maintainers { + %email_hash_name = (); + %email_hash_address = (); + %commit_author_hash = (); + %commit_signer_hash = (); + @email_to = (); + %hash_list_to = (); + @list_to = (); + @scm = (); + @web = (); + @subsystem = (); + @status = (); + %deduplicate_name_hash = (); + %deduplicate_address_hash = (); + if ($email_git_all_signature_types) { + $signature_pattern = "(.+?)[Bb][Yy]:"; + } else { + $signature_pattern = "\(" . join("|", @signature_tags) . "\)"; + } + + # Find responsible parties + + my %exact_pattern_match_hash = (); + + foreach my $file (@files) { + + my %hash; + my $tvi = find_first_section(); + while ($tvi < @typevalue) { + my $start = find_starting_index($tvi); + my $end = find_ending_index($tvi); + my $exclude = 0; + my $i; + + #Do not match excluded file patterns + + for ($i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ m/^(\C):\s*(.*)/) { + my $type = $1; + my $value = $2; + if ($type eq 'X') { + if (file_match_pattern($file, $value)) { + $exclude = 1; + last; + } + } + } + } + + if (!$exclude) { + for ($i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ m/^(\C):\s*(.*)/) { + my $type = $1; + my $value = $2; + if ($type eq 'F') { + if (file_match_pattern($file, $value)) { + my $value_pd = ($value =~ tr@/@@); + my $file_pd = ($file =~ tr@/@@); + $value_pd++ if (substr($value,-1,1) ne "/"); + $value_pd = -1 if ($value =~ /^\.\*/); + if ($value_pd >= $file_pd && + range_is_maintained($start, $end) && + range_has_maintainer($start, $end)) { + $exact_pattern_match_hash{$file} = 1; + } + if ($pattern_depth == 0 || + (($file_pd - $value_pd) < $pattern_depth)) { + $hash{$tvi} = $value_pd; + } + } + } elsif ($type eq 'N') { + if ($file =~ m/$value/x) { + $hash{$tvi} = 0; + } + } + } + } + } + $tvi = $end + 1; + } + + foreach my $line (sort {$hash{$b} <=> $hash{$a}} keys %hash) { + add_categories($line); + if ($sections) { + my $i; + my $start = find_starting_index($line); + my $end = find_ending_index($line); + for ($i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ /^[FX]:/) { ##Restore file patterns + $line =~ s/([^\\])\.([^\*])/$1\?$2/g; + $line =~ s/([^\\])\.$/$1\?/g; ##Convert . back to ? + $line =~ s/\\\./\./g; ##Convert \. to . + $line =~ s/\.\*/\*/g; ##Convert .* to * + } + $line =~ s/^([A-Z]):/$1:\t/g; + print("$line\n"); + } + print("\n"); + } + } + } + + if ($keywords) { + @keyword_tvi = sort_and_uniq(@keyword_tvi); + foreach my $line (@keyword_tvi) { + add_categories($line); + } + } + + foreach my $email (@email_to, @list_to) { + $email->[0] = deduplicate_email($email->[0]); + } + + foreach my $file (@files) { + if ($email && + ($email_git || ($email_git_fallback && + !$exact_pattern_match_hash{$file}))) { + vcs_file_signoffs($file); + } + if ($email && $email_git_blame) { + vcs_file_blame($file); + } + } + + if ($email) { + foreach my $chief (@penguin_chief) { + if ($chief =~ m/^(.*):(.*)/) { + my $email_address; + + $email_address = format_email($1, $2, $email_usename); + if ($email_git_penguin_chiefs) { + push(@email_to, [$email_address, 'chief penguin']); + } else { + @email_to = grep($_->[0] !~ /${email_address}/, @email_to); + } + } + } + + foreach my $email (@file_emails) { + my ($name, $address) = parse_email($email); + + my $tmp_email = format_email($name, $address, $email_usename); + push_email_address($tmp_email, ''); + add_role($tmp_email, 'in file'); + } + } + + my @to = (); + if ($email || $email_list) { + if ($email) { + @to = (@to, @email_to); + } + if ($email_list) { + @to = (@to, @list_to); + } + } + + if ($interactive) { + @to = interactive_get_maintainers(\@to); + } + + return @to; +} + +sub file_match_pattern { + my ($file, $pattern) = @_; + if (substr($pattern, -1) eq "/") { + if ($file =~ m@^$pattern@) { + return 1; + } + } else { + if ($file =~ m@^$pattern@) { + my $s1 = ($file =~ tr@/@@); + my $s2 = ($pattern =~ tr@/@@); + if ($s1 == $s2) { + return 1; + } + } + } + return 0; +} + +sub usage { + print < print email address(es) if any + --git => include recent git \*-by: signers + --git-all-signature-types => include signers regardless of signature type + or use only ${signature_pattern} signers (default: $email_git_all_signature_types) + --git-fallback => use git when no exact MAINTAINERS pattern (default: $email_git_fallback) + --git-chief-penguins => include ${penguin_chiefs} + --git-min-signatures => number of signatures required (default: $email_git_min_signatures) + --git-max-maintainers => maximum maintainers to add (default: $email_git_max_maintainers) + --git-min-percent => minimum percentage of commits required (default: $email_git_min_percent) + --git-blame => use git blame to find modified commits for patch or file + --git-since => git history to use (default: $email_git_since) + --hg-since => hg history to use (default: $email_hg_since) + --interactive => display a menu (mostly useful if used with the --git option) + --m => include maintainer(s) if any + --n => include name 'Full Name ' + --l => include list(s) if any + --s => include subscriber only list(s) if any + --remove-duplicates => minimize duplicate email names/addresses + --roles => show roles (status:subsystem, git-signer, list, etc...) + --rolestats => show roles and statistics (commits/total_commits, %) + --file-emails => add email addresses found in -f file (default: 0 (off)) + --scm => print SCM tree(s) if any + --status => print status if any + --subsystem => print subsystem name if any + --web => print website(s) if any + +Output type options: + --separator [, ] => separator for multiple entries on 1 line + using --separator also sets --nomultiline if --separator is not [, ] + --multiline => print 1 entry per line + +Other options: + --pattern-depth => Number of pattern directory traversals (default: 0 (all)) + --keywords => scan patch for keywords (default: $keywords) + --sections => print all of the subsystem sections with pattern matches + --mailmap => use .mailmap file (default: $email_use_mailmap) + --version => show version + --help => show this help information + +Default options: + [--email --nogit --git-fallback --m --n --l --multiline -pattern-depth=0 + --remove-duplicates --rolestats] + +Notes: + Using "-f directory" may give unexpected results: + Used with "--git", git signators for _all_ files in and below + directory are examined as git recurses directories. + Any specified X: (exclude) pattern matches are _not_ ignored. + Used with "--nogit", directory is used as a pattern match, + no individual file within the directory or subdirectory + is matched. + Used with "--git-blame", does not iterate all files in directory + Using "--git-blame" is slow and may add old committers and authors + that are no longer active maintainers to the output. + Using "--roles" or "--rolestats" with git send-email --cc-cmd or any + other automated tools that expect only ["name"] + may not work because of additional output after . + Using "--rolestats" and "--git-blame" shows the #/total=% commits, + not the percentage of the entire file authored. # of commits is + not a good measure of amount of code authored. 1 major commit may + contain a thousand lines, 5 trivial commits may modify a single line. + If git is not installed, but mercurial (hg) is installed and an .hg + repository exists, the following options apply to mercurial: + --git, + --git-min-signatures, --git-max-maintainers, --git-min-percent, and + --git-blame + Use --hg-since not --git-since to control date selection + File ".get_maintainer.conf", if it exists in the linux kernel source root + directory, can change whatever get_maintainer defaults are desired. + Entries in this file can be any command line argument. + This file is prepended to any additional command line arguments. + Multiple lines and # comments are allowed. +EOT +} + +sub top_of_kernel_tree { + my ($lk_path) = @_; + + if ($lk_path ne "" && substr($lk_path,length($lk_path)-1,1) ne "/") { + $lk_path .= "/"; + } + if ( (-f "${lk_path}Kbuild") + && (-f "${lk_path}MAINTAINERS") + && (-f "${lk_path}Makefile") + && (-f "${lk_path}README") + && (-d "${lk_path}arch") + && (-d "${lk_path}board") + && (-d "${lk_path}common") + && (-d "${lk_path}doc") + && (-d "${lk_path}drivers") + && (-d "${lk_path}dts") + && (-d "${lk_path}fs") + && (-d "${lk_path}lib") + && (-d "${lk_path}include") + && (-d "${lk_path}net") + && (-d "${lk_path}post") + && (-d "${lk_path}scripts") + && (-d "${lk_path}test") + && (-d "${lk_path}tools")) { + return 1; + } + return 0; +} + +sub parse_email { + my ($formatted_email) = @_; + + my $name = ""; + my $address = ""; + + if ($formatted_email =~ /^([^<]+)<(.+\@.*)>.*$/) { + $name = $1; + $address = $2; + } elsif ($formatted_email =~ /^\s*<(.+\@\S*)>.*$/) { + $address = $1; + } elsif ($formatted_email =~ /^(.+\@\S*).*$/) { + $address = $1; + } + + $name =~ s/^\s+|\s+$//g; + $name =~ s/^\"|\"$//g; + $address =~ s/^\s+|\s+$//g; + + if ($name =~ /[^\w \-]/i) { ##has "must quote" chars + $name =~ s/(?"; + } + } else { + $formatted_email = $address; + } + + return $formatted_email; +} + +sub find_first_section { + my $index = 0; + + while ($index < @typevalue) { + my $tv = $typevalue[$index]; + if (($tv =~ m/^(\C):\s*(.*)/)) { + last; + } + $index++; + } + + return $index; +} + +sub find_starting_index { + my ($index) = @_; + + while ($index > 0) { + my $tv = $typevalue[$index]; + if (!($tv =~ m/^(\C):\s*(.*)/)) { + last; + } + $index--; + } + + return $index; +} + +sub find_ending_index { + my ($index) = @_; + + while ($index < @typevalue) { + my $tv = $typevalue[$index]; + if (!($tv =~ m/^(\C):\s*(.*)/)) { + last; + } + $index++; + } + + return $index; +} + +sub get_maintainer_role { + my ($index) = @_; + + my $i; + my $start = find_starting_index($index); + my $end = find_ending_index($index); + + my $role = "unknown"; + my $subsystem = $typevalue[$start]; + if (length($subsystem) > 20) { + $subsystem = substr($subsystem, 0, 17); + $subsystem =~ s/\s*$//; + $subsystem = $subsystem . "..."; + } + + for ($i = $start + 1; $i < $end; $i++) { + my $tv = $typevalue[$i]; + if ($tv =~ m/^(\C):\s*(.*)/) { + my $ptype = $1; + my $pvalue = $2; + if ($ptype eq "S") { + $role = $pvalue; + } + } + } + + $role = lc($role); + if ($role eq "supported") { + $role = "supporter"; + } elsif ($role eq "maintained") { + $role = "maintainer"; + } elsif ($role eq "odd fixes") { + $role = "odd fixer"; + } elsif ($role eq "orphan") { + $role = "orphan minder"; + } elsif ($role eq "obsolete") { + $role = "obsolete minder"; + } elsif ($role eq "buried alive in reporters") { + $role = "chief penguin"; + } + + return $role . ":" . $subsystem; +} + +sub get_list_role { + my ($index) = @_; + + my $i; + my $start = find_starting_index($index); + my $end = find_ending_index($index); + + my $subsystem = $typevalue[$start]; + if (length($subsystem) > 20) { + $subsystem = substr($subsystem, 0, 17); + $subsystem =~ s/\s*$//; + $subsystem = $subsystem . "..."; + } + + if ($subsystem eq "THE REST") { + $subsystem = ""; + } + + return $subsystem; +} + +sub add_categories { + my ($index) = @_; + + my $i; + my $start = find_starting_index($index); + my $end = find_ending_index($index); + + push(@subsystem, $typevalue[$start]); + + for ($i = $start + 1; $i < $end; $i++) { + my $tv = $typevalue[$i]; + if ($tv =~ m/^(\C):\s*(.*)/) { + my $ptype = $1; + my $pvalue = $2; + if ($ptype eq "L") { + my $list_address = $pvalue; + my $list_additional = ""; + my $list_role = get_list_role($i); + + if ($list_role ne "") { + $list_role = ":" . $list_role; + } + if ($list_address =~ m/([^\s]+)\s+(.*)$/) { + $list_address = $1; + $list_additional = $2; + } + if ($list_additional =~ m/subscribers-only/) { + if ($email_subscriber_list) { + if (!$hash_list_to{lc($list_address)}) { + $hash_list_to{lc($list_address)} = 1; + push(@list_to, [$list_address, + "subscriber list${list_role}"]); + } + } + } else { + if ($email_list) { + if (!$hash_list_to{lc($list_address)}) { + $hash_list_to{lc($list_address)} = 1; + if ($list_additional =~ m/moderated/) { + push(@list_to, [$list_address, + "moderated list${list_role}"]); + } else { + push(@list_to, [$list_address, + "open list${list_role}"]); + } + } + } + } + } elsif ($ptype eq "M") { + my ($name, $address) = parse_email($pvalue); + if ($name eq "") { + if ($i > 0) { + my $tv = $typevalue[$i - 1]; + if ($tv =~ m/^(\C):\s*(.*)/) { + if ($1 eq "P") { + $name = $2; + $pvalue = format_email($name, $address, $email_usename); + } + } + } + } + if ($email_maintainer) { + my $role = get_maintainer_role($i); + push_email_addresses($pvalue, $role); + } + } elsif ($ptype eq "T") { + push(@scm, $pvalue); + } elsif ($ptype eq "W") { + push(@web, $pvalue); + } elsif ($ptype eq "S") { + push(@status, $pvalue); + } + } + } +} + +sub email_inuse { + my ($name, $address) = @_; + + return 1 if (($name eq "") && ($address eq "")); + return 1 if (($name ne "") && exists($email_hash_name{lc($name)})); + return 1 if (($address ne "") && exists($email_hash_address{lc($address)})); + + return 0; +} + +sub push_email_address { + my ($line, $role) = @_; + + my ($name, $address) = parse_email($line); + + if ($address eq "") { + return 0; + } + + if (!$email_remove_duplicates) { + push(@email_to, [format_email($name, $address, $email_usename), $role]); + } elsif (!email_inuse($name, $address)) { + push(@email_to, [format_email($name, $address, $email_usename), $role]); + $email_hash_name{lc($name)}++ if ($name ne ""); + $email_hash_address{lc($address)}++; + } + + return 1; +} + +sub push_email_addresses { + my ($address, $role) = @_; + + my @address_list = (); + + if (rfc822_valid($address)) { + push_email_address($address, $role); + } elsif (@address_list = rfc822_validlist($address)) { + my $array_count = shift(@address_list); + while (my $entry = shift(@address_list)) { + push_email_address($entry, $role); + } + } else { + if (!push_email_address($address, $role)) { + warn("Invalid MAINTAINERS address: '" . $address . "'\n"); + } + } +} + +sub add_role { + my ($line, $role) = @_; + + my ($name, $address) = parse_email($line); + my $email = format_email($name, $address, $email_usename); + + foreach my $entry (@email_to) { + if ($email_remove_duplicates) { + my ($entry_name, $entry_address) = parse_email($entry->[0]); + if (($name eq $entry_name || $address eq $entry_address) + && ($role eq "" || !($entry->[1] =~ m/$role/)) + ) { + if ($entry->[1] eq "") { + $entry->[1] = "$role"; + } else { + $entry->[1] = "$entry->[1],$role"; + } + } + } else { + if ($email eq $entry->[0] + && ($role eq "" || !($entry->[1] =~ m/$role/)) + ) { + if ($entry->[1] eq "") { + $entry->[1] = "$role"; + } else { + $entry->[1] = "$entry->[1],$role"; + } + } + } + } +} + +sub which { + my ($bin) = @_; + + foreach my $path (split(/:/, $ENV{PATH})) { + if (-e "$path/$bin") { + return "$path/$bin"; + } + } + + return ""; +} + +sub which_conf { + my ($conf) = @_; + + foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { + if (-e "$path/$conf") { + return "$path/$conf"; + } + } + + return ""; +} + +sub mailmap_email { + my ($line) = @_; + + my ($name, $address) = parse_email($line); + my $email = format_email($name, $address, 1); + my $real_name = $name; + my $real_address = $address; + + if (exists $mailmap->{names}->{$email} || + exists $mailmap->{addresses}->{$email}) { + if (exists $mailmap->{names}->{$email}) { + $real_name = $mailmap->{names}->{$email}; + } + if (exists $mailmap->{addresses}->{$email}) { + $real_address = $mailmap->{addresses}->{$email}; + } + } else { + if (exists $mailmap->{names}->{$address}) { + $real_name = $mailmap->{names}->{$address}; + } + if (exists $mailmap->{addresses}->{$address}) { + $real_address = $mailmap->{addresses}->{$address}; + } + } + return format_email($real_name, $real_address, 1); +} + +sub mailmap { + my (@addresses) = @_; + + my @mapped_emails = (); + foreach my $line (@addresses) { + push(@mapped_emails, mailmap_email($line)); + } + merge_by_realname(@mapped_emails) if ($email_use_mailmap); + return @mapped_emails; +} + +sub merge_by_realname { + my %address_map; + my (@emails) = @_; + + foreach my $email (@emails) { + my ($name, $address) = parse_email($email); + if (exists $address_map{$name}) { + $address = $address_map{$name}; + $email = format_email($name, $address, 1); + } else { + $address_map{$name} = $address; + } + } +} + +sub git_execute_cmd { + my ($cmd) = @_; + my @lines = (); + + my $output = `$cmd`; + $output =~ s/^\s*//gm; + @lines = split("\n", $output); + + return @lines; +} + +sub hg_execute_cmd { + my ($cmd) = @_; + my @lines = (); + + my $output = `$cmd`; + @lines = split("\n", $output); + + return @lines; +} + +sub extract_formatted_signatures { + my (@signature_lines) = @_; + + my @type = @signature_lines; + + s/\s*(.*):.*/$1/ for (@type); + + # cut -f2- -d":" + s/\s*.*:\s*(.+)\s*/$1/ for (@signature_lines); + +## Reformat email addresses (with names) to avoid badly written signatures + + foreach my $signer (@signature_lines) { + $signer = deduplicate_email($signer); + } + + return (\@type, \@signature_lines); +} + +sub vcs_find_signers { + my ($cmd, $file) = @_; + my $commits; + my @lines = (); + my @signatures = (); + my @authors = (); + my @stats = (); + + @lines = &{$VCS_cmds{"execute_cmd"}}($cmd); + + my $pattern = $VCS_cmds{"commit_pattern"}; + my $author_pattern = $VCS_cmds{"author_pattern"}; + my $stat_pattern = $VCS_cmds{"stat_pattern"}; + + $stat_pattern =~ s/(\$\w+)/$1/eeg; #interpolate $stat_pattern + + $commits = grep(/$pattern/, @lines); # of commits + + @authors = grep(/$author_pattern/, @lines); + @signatures = grep(/^[ \t]*${signature_pattern}.*\@.*$/, @lines); + @stats = grep(/$stat_pattern/, @lines); + +# print("stats: <@stats>\n"); + + return (0, \@signatures, \@authors, \@stats) if !@signatures; + + save_commits_by_author(@lines) if ($interactive); + save_commits_by_signer(@lines) if ($interactive); + + if (!$email_git_penguin_chiefs) { + @signatures = grep(!/${penguin_chiefs}/i, @signatures); + } + + my ($author_ref, $authors_ref) = extract_formatted_signatures(@authors); + my ($types_ref, $signers_ref) = extract_formatted_signatures(@signatures); + + return ($commits, $signers_ref, $authors_ref, \@stats); +} + +sub vcs_find_author { + my ($cmd) = @_; + my @lines = (); + + @lines = &{$VCS_cmds{"execute_cmd"}}($cmd); + + if (!$email_git_penguin_chiefs) { + @lines = grep(!/${penguin_chiefs}/i, @lines); + } + + return @lines if !@lines; + + my @authors = (); + foreach my $line (@lines) { + if ($line =~ m/$VCS_cmds{"author_pattern"}/) { + my $author = $1; + my ($name, $address) = parse_email($author); + $author = format_email($name, $address, 1); + push(@authors, $author); + } + } + + save_commits_by_author(@lines) if ($interactive); + save_commits_by_signer(@lines) if ($interactive); + + return @authors; +} + +sub vcs_save_commits { + my ($cmd) = @_; + my @lines = (); + my @commits = (); + + @lines = &{$VCS_cmds{"execute_cmd"}}($cmd); + + foreach my $line (@lines) { + if ($line =~ m/$VCS_cmds{"blame_commit_pattern"}/) { + push(@commits, $1); + } + } + + return @commits; +} + +sub vcs_blame { + my ($file) = @_; + my $cmd; + my @commits = (); + + return @commits if (!(-f $file)); + + if (@range && $VCS_cmds{"blame_range_cmd"} eq "") { + my @all_commits = (); + + $cmd = $VCS_cmds{"blame_file_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #interpolate $cmd + @all_commits = vcs_save_commits($cmd); + + foreach my $file_range_diff (@range) { + next if (!($file_range_diff =~ m/(.+):(.+):(.+)/)); + my $diff_file = $1; + my $diff_start = $2; + my $diff_length = $3; + next if ("$file" ne "$diff_file"); + for (my $i = $diff_start; $i < $diff_start + $diff_length; $i++) { + push(@commits, $all_commits[$i]); + } + } + } elsif (@range) { + foreach my $file_range_diff (@range) { + next if (!($file_range_diff =~ m/(.+):(.+):(.+)/)); + my $diff_file = $1; + my $diff_start = $2; + my $diff_length = $3; + next if ("$file" ne "$diff_file"); + $cmd = $VCS_cmds{"blame_range_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #interpolate $cmd + push(@commits, vcs_save_commits($cmd)); + } + } else { + $cmd = $VCS_cmds{"blame_file_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #interpolate $cmd + @commits = vcs_save_commits($cmd); + } + + foreach my $commit (@commits) { + $commit =~ s/^\^//g; + } + + return @commits; +} + +my $printed_novcs = 0; +sub vcs_exists { + %VCS_cmds = %VCS_cmds_git; + return 1 if eval $VCS_cmds{"available"}; + %VCS_cmds = %VCS_cmds_hg; + return 2 if eval $VCS_cmds{"available"}; + %VCS_cmds = (); + if (!$printed_novcs) { + warn("$P: No supported VCS found. Add --nogit to options?\n"); + warn("Using a git repository produces better results.\n"); + warn("Try Linus Torvalds' latest git repository using:\n"); + warn("git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git\n"); + $printed_novcs = 1; + } + return 0; +} + +sub vcs_is_git { + vcs_exists(); + return $vcs_used == 1; +} + +sub vcs_is_hg { + return $vcs_used == 2; +} + +sub interactive_get_maintainers { + my ($list_ref) = @_; + my @list = @$list_ref; + + vcs_exists(); + + my %selected; + my %authored; + my %signed; + my $count = 0; + my $maintained = 0; + foreach my $entry (@list) { + $maintained = 1 if ($entry->[1] =~ /^(maintainer|supporter)/i); + $selected{$count} = 1; + $authored{$count} = 0; + $signed{$count} = 0; + $count++; + } + + #menu loop + my $done = 0; + my $print_options = 0; + my $redraw = 1; + while (!$done) { + $count = 0; + if ($redraw) { + printf STDERR "\n%1s %2s %-65s", + "*", "#", "email/list and role:stats"; + if ($email_git || + ($email_git_fallback && !$maintained) || + $email_git_blame) { + print STDERR "auth sign"; + } + print STDERR "\n"; + foreach my $entry (@list) { + my $email = $entry->[0]; + my $role = $entry->[1]; + my $sel = ""; + $sel = "*" if ($selected{$count}); + my $commit_author = $commit_author_hash{$email}; + my $commit_signer = $commit_signer_hash{$email}; + my $authored = 0; + my $signed = 0; + $authored++ for (@{$commit_author}); + $signed++ for (@{$commit_signer}); + printf STDERR "%1s %2d %-65s", $sel, $count + 1, $email; + printf STDERR "%4d %4d", $authored, $signed + if ($authored > 0 || $signed > 0); + printf STDERR "\n %s\n", $role; + if ($authored{$count}) { + my $commit_author = $commit_author_hash{$email}; + foreach my $ref (@{$commit_author}) { + print STDERR " Author: @{$ref}[1]\n"; + } + } + if ($signed{$count}) { + my $commit_signer = $commit_signer_hash{$email}; + foreach my $ref (@{$commit_signer}) { + print STDERR " @{$ref}[2]: @{$ref}[1]\n"; + } + } + + $count++; + } + } + my $date_ref = \$email_git_since; + $date_ref = \$email_hg_since if (vcs_is_hg()); + if ($print_options) { + $print_options = 0; + if (vcs_exists()) { + print STDERR <; + chomp($input); + + $redraw = 1; + my $rerun = 0; + my @wish = split(/[, ]+/, $input); + foreach my $nr (@wish) { + $nr = lc($nr); + my $sel = substr($nr, 0, 1); + my $str = substr($nr, 1); + my $val = 0; + $val = $1 if $str =~ /^(\d+)$/; + + if ($sel eq "y") { + $interactive = 0; + $done = 1; + $output_rolestats = 0; + $output_roles = 0; + last; + } elsif ($nr =~ /^\d+$/ && $nr > 0 && $nr <= $count) { + $selected{$nr - 1} = !$selected{$nr - 1}; + } elsif ($sel eq "*" || $sel eq '^') { + my $toggle = 0; + $toggle = 1 if ($sel eq '*'); + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = $toggle; + } + } elsif ($sel eq "0") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i}; + } + } elsif ($sel eq "t") { + if (lc($str) eq "m") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i} + if ($list[$i]->[1] =~ /^(maintainer|supporter)/i); + } + } elsif (lc($str) eq "g") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i} + if ($list[$i]->[1] =~ /^(author|commit|signer)/i); + } + } elsif (lc($str) eq "l") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i} + if ($list[$i]->[1] =~ /^(open list)/i); + } + } elsif (lc($str) eq "s") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i} + if ($list[$i]->[1] =~ /^(subscriber list)/i); + } + } + } elsif ($sel eq "a") { + if ($val > 0 && $val <= $count) { + $authored{$val - 1} = !$authored{$val - 1}; + } elsif ($str eq '*' || $str eq '^') { + my $toggle = 0; + $toggle = 1 if ($str eq '*'); + for (my $i = 0; $i < $count; $i++) { + $authored{$i} = $toggle; + } + } + } elsif ($sel eq "s") { + if ($val > 0 && $val <= $count) { + $signed{$val - 1} = !$signed{$val - 1}; + } elsif ($str eq '*' || $str eq '^') { + my $toggle = 0; + $toggle = 1 if ($str eq '*'); + for (my $i = 0; $i < $count; $i++) { + $signed{$i} = $toggle; + } + } + } elsif ($sel eq "o") { + $print_options = 1; + $redraw = 1; + } elsif ($sel eq "g") { + if ($str eq "f") { + bool_invert(\$email_git_fallback); + } else { + bool_invert(\$email_git); + } + $rerun = 1; + } elsif ($sel eq "b") { + if ($str eq "s") { + bool_invert(\$email_git_blame_signatures); + } else { + bool_invert(\$email_git_blame); + } + $rerun = 1; + } elsif ($sel eq "c") { + if ($val > 0) { + $email_git_min_signatures = $val; + $rerun = 1; + } + } elsif ($sel eq "x") { + if ($val > 0) { + $email_git_max_maintainers = $val; + $rerun = 1; + } + } elsif ($sel eq "%") { + if ($str ne "" && $val >= 0) { + $email_git_min_percent = $val; + $rerun = 1; + } + } elsif ($sel eq "d") { + if (vcs_is_git()) { + $email_git_since = $str; + } elsif (vcs_is_hg()) { + $email_hg_since = $str; + } + $rerun = 1; + } elsif ($sel eq "t") { + bool_invert(\$email_git_all_signature_types); + $rerun = 1; + } elsif ($sel eq "f") { + bool_invert(\$file_emails); + $rerun = 1; + } elsif ($sel eq "r") { + bool_invert(\$email_remove_duplicates); + $rerun = 1; + } elsif ($sel eq "m") { + bool_invert(\$email_use_mailmap); + read_mailmap(); + $rerun = 1; + } elsif ($sel eq "k") { + bool_invert(\$keywords); + $rerun = 1; + } elsif ($sel eq "p") { + if ($str ne "" && $val >= 0) { + $pattern_depth = $val; + $rerun = 1; + } + } elsif ($sel eq "h" || $sel eq "?") { + print STDERR <[0]; + $address = $deduplicate_name_hash{lc($name)}->[1]; + $matched = 1; + } elsif ($deduplicate_address_hash{lc($address)}) { + $name = $deduplicate_address_hash{lc($address)}->[0]; + $address = $deduplicate_address_hash{lc($address)}->[1]; + $matched = 1; + } + if (!$matched) { + $deduplicate_name_hash{lc($name)} = [ $name, $address ]; + $deduplicate_address_hash{lc($address)} = [ $name, $address ]; + } + $email = format_email($name, $address, 1); + $email = mailmap_email($email); + return $email; +} + +sub save_commits_by_author { + my (@lines) = @_; + + my @authors = (); + my @commits = (); + my @subjects = (); + + foreach my $line (@lines) { + if ($line =~ m/$VCS_cmds{"author_pattern"}/) { + my $author = $1; + $author = deduplicate_email($author); + push(@authors, $author); + } + push(@commits, $1) if ($line =~ m/$VCS_cmds{"commit_pattern"}/); + push(@subjects, $1) if ($line =~ m/$VCS_cmds{"subject_pattern"}/); + } + + for (my $i = 0; $i < @authors; $i++) { + my $exists = 0; + foreach my $ref(@{$commit_author_hash{$authors[$i]}}) { + if (@{$ref}[0] eq $commits[$i] && + @{$ref}[1] eq $subjects[$i]) { + $exists = 1; + last; + } + } + if (!$exists) { + push(@{$commit_author_hash{$authors[$i]}}, + [ ($commits[$i], $subjects[$i]) ]); + } + } +} + +sub save_commits_by_signer { + my (@lines) = @_; + + my $commit = ""; + my $subject = ""; + + foreach my $line (@lines) { + $commit = $1 if ($line =~ m/$VCS_cmds{"commit_pattern"}/); + $subject = $1 if ($line =~ m/$VCS_cmds{"subject_pattern"}/); + if ($line =~ /^[ \t]*${signature_pattern}.*\@.*$/) { + my @signatures = ($line); + my ($types_ref, $signers_ref) = extract_formatted_signatures(@signatures); + my @types = @$types_ref; + my @signers = @$signers_ref; + + my $type = $types[0]; + my $signer = $signers[0]; + + $signer = deduplicate_email($signer); + + my $exists = 0; + foreach my $ref(@{$commit_signer_hash{$signer}}) { + if (@{$ref}[0] eq $commit && + @{$ref}[1] eq $subject && + @{$ref}[2] eq $type) { + $exists = 1; + last; + } + } + if (!$exists) { + push(@{$commit_signer_hash{$signer}}, + [ ($commit, $subject, $type) ]); + } + } + } +} + +sub vcs_assign { + my ($role, $divisor, @lines) = @_; + + my %hash; + my $count = 0; + + return if (@lines <= 0); + + if ($divisor <= 0) { + warn("Bad divisor in " . (caller(0))[3] . ": $divisor\n"); + $divisor = 1; + } + + @lines = mailmap(@lines); + + return if (@lines <= 0); + + @lines = sort(@lines); + + # uniq -c + $hash{$_}++ for @lines; + + # sort -rn + foreach my $line (sort {$hash{$b} <=> $hash{$a}} keys %hash) { + my $sign_offs = $hash{$line}; + my $percent = $sign_offs * 100 / $divisor; + + $percent = 100 if ($percent > 100); + $count++; + last if ($sign_offs < $email_git_min_signatures || + $count > $email_git_max_maintainers || + $percent < $email_git_min_percent); + push_email_address($line, ''); + if ($output_rolestats) { + my $fmt_percent = sprintf("%.0f", $percent); + add_role($line, "$role:$sign_offs/$divisor=$fmt_percent%"); + } else { + add_role($line, $role); + } + } +} + +sub vcs_file_signoffs { + my ($file) = @_; + + my $authors_ref; + my $signers_ref; + my $stats_ref; + my @authors = (); + my @signers = (); + my @stats = (); + my $commits; + + $vcs_used = vcs_exists(); + return if (!$vcs_used); + + my $cmd = $VCS_cmds{"find_signers_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; # interpolate $cmd + + ($commits, $signers_ref, $authors_ref, $stats_ref) = vcs_find_signers($cmd, $file); + + @signers = @{$signers_ref} if defined $signers_ref; + @authors = @{$authors_ref} if defined $authors_ref; + @stats = @{$stats_ref} if defined $stats_ref; + +# print("commits: <$commits>\nsigners:<@signers>\nauthors: <@authors>\nstats: <@stats>\n"); + + foreach my $signer (@signers) { + $signer = deduplicate_email($signer); + } + + vcs_assign("commit_signer", $commits, @signers); + vcs_assign("authored", $commits, @authors); + if ($#authors == $#stats) { + my $stat_pattern = $VCS_cmds{"stat_pattern"}; + $stat_pattern =~ s/(\$\w+)/$1/eeg; #interpolate $stat_pattern + + my $added = 0; + my $deleted = 0; + for (my $i = 0; $i <= $#stats; $i++) { + if ($stats[$i] =~ /$stat_pattern/) { + $added += $1; + $deleted += $2; + } + } + my @tmp_authors = uniq(@authors); + foreach my $author (@tmp_authors) { + $author = deduplicate_email($author); + } + @tmp_authors = uniq(@tmp_authors); + my @list_added = (); + my @list_deleted = (); + foreach my $author (@tmp_authors) { + my $auth_added = 0; + my $auth_deleted = 0; + for (my $i = 0; $i <= $#stats; $i++) { + if ($author eq deduplicate_email($authors[$i]) && + $stats[$i] =~ /$stat_pattern/) { + $auth_added += $1; + $auth_deleted += $2; + } + } + for (my $i = 0; $i < $auth_added; $i++) { + push(@list_added, $author); + } + for (my $i = 0; $i < $auth_deleted; $i++) { + push(@list_deleted, $author); + } + } + vcs_assign("added_lines", $added, @list_added); + vcs_assign("removed_lines", $deleted, @list_deleted); + } +} + +sub vcs_file_blame { + my ($file) = @_; + + my @signers = (); + my @all_commits = (); + my @commits = (); + my $total_commits; + my $total_lines; + + $vcs_used = vcs_exists(); + return if (!$vcs_used); + + @all_commits = vcs_blame($file); + @commits = uniq(@all_commits); + $total_commits = @commits; + $total_lines = @all_commits; + + if ($email_git_blame_signatures) { + if (vcs_is_hg()) { + my $commit_count; + my $commit_authors_ref; + my $commit_signers_ref; + my $stats_ref; + my @commit_authors = (); + my @commit_signers = (); + my $commit = join(" -r ", @commits); + my $cmd; + + $cmd = $VCS_cmds{"find_commit_signers_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #substitute variables in $cmd + + ($commit_count, $commit_signers_ref, $commit_authors_ref, $stats_ref) = vcs_find_signers($cmd, $file); + @commit_authors = @{$commit_authors_ref} if defined $commit_authors_ref; + @commit_signers = @{$commit_signers_ref} if defined $commit_signers_ref; + + push(@signers, @commit_signers); + } else { + foreach my $commit (@commits) { + my $commit_count; + my $commit_authors_ref; + my $commit_signers_ref; + my $stats_ref; + my @commit_authors = (); + my @commit_signers = (); + my $cmd; + + $cmd = $VCS_cmds{"find_commit_signers_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #substitute variables in $cmd + + ($commit_count, $commit_signers_ref, $commit_authors_ref, $stats_ref) = vcs_find_signers($cmd, $file); + @commit_authors = @{$commit_authors_ref} if defined $commit_authors_ref; + @commit_signers = @{$commit_signers_ref} if defined $commit_signers_ref; + + push(@signers, @commit_signers); + } + } + } + + if ($from_filename) { + if ($output_rolestats) { + my @blame_signers; + if (vcs_is_hg()) {{ # Double brace for last exit + my $commit_count; + my @commit_signers = (); + @commits = uniq(@commits); + @commits = sort(@commits); + my $commit = join(" -r ", @commits); + my $cmd; + + $cmd = $VCS_cmds{"find_commit_author_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #substitute variables in $cmd + + my @lines = (); + + @lines = &{$VCS_cmds{"execute_cmd"}}($cmd); + + if (!$email_git_penguin_chiefs) { + @lines = grep(!/${penguin_chiefs}/i, @lines); + } + + last if !@lines; + + my @authors = (); + foreach my $line (@lines) { + if ($line =~ m/$VCS_cmds{"author_pattern"}/) { + my $author = $1; + $author = deduplicate_email($author); + push(@authors, $author); + } + } + + save_commits_by_author(@lines) if ($interactive); + save_commits_by_signer(@lines) if ($interactive); + + push(@signers, @authors); + }} + else { + foreach my $commit (@commits) { + my $i; + my $cmd = $VCS_cmds{"find_commit_author_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #interpolate $cmd + my @author = vcs_find_author($cmd); + next if !@author; + + my $formatted_author = deduplicate_email($author[0]); + + my $count = grep(/$commit/, @all_commits); + for ($i = 0; $i < $count ; $i++) { + push(@blame_signers, $formatted_author); + } + } + } + if (@blame_signers) { + vcs_assign("authored lines", $total_lines, @blame_signers); + } + } + foreach my $signer (@signers) { + $signer = deduplicate_email($signer); + } + vcs_assign("commits", $total_commits, @signers); + } else { + foreach my $signer (@signers) { + $signer = deduplicate_email($signer); + } + vcs_assign("modified commits", $total_commits, @signers); + } +} + +sub uniq { + my (@parms) = @_; + + my %saw; + @parms = grep(!$saw{$_}++, @parms); + return @parms; +} + +sub sort_and_uniq { + my (@parms) = @_; + + my %saw; + @parms = sort @parms; + @parms = grep(!$saw{$_}++, @parms); + return @parms; +} + +sub clean_file_emails { + my (@file_emails) = @_; + my @fmt_emails = (); + + foreach my $email (@file_emails) { + $email =~ s/[\(\<\{]{0,1}([A-Za-z0-9_\.\+-]+\@[A-Za-z0-9\.-]+)[\)\>\}]{0,1}/\<$1\>/g; + my ($name, $address) = parse_email($email); + if ($name eq '"[,\.]"') { + $name = ""; + } + + my @nw = split(/[^A-Za-zÀ-ÿ\'\,\.\+-]/, $name); + if (@nw > 2) { + my $first = $nw[@nw - 3]; + my $middle = $nw[@nw - 2]; + my $last = $nw[@nw - 1]; + + if (((length($first) == 1 && $first =~ m/[A-Za-z]/) || + (length($first) == 2 && substr($first, -1) eq ".")) || + (length($middle) == 1 || + (length($middle) == 2 && substr($middle, -1) eq "."))) { + $name = "$first $middle $last"; + } else { + $name = "$middle $last"; + } + } + + if (substr($name, -1) =~ /[,\.]/) { + $name = substr($name, 0, length($name) - 1); + } elsif (substr($name, -2) =~ /[,\.]"/) { + $name = substr($name, 0, length($name) - 2) . '"'; + } + + if (substr($name, 0, 1) =~ /[,\.]/) { + $name = substr($name, 1, length($name) - 1); + } elsif (substr($name, 0, 2) =~ /"[,\.]/) { + $name = '"' . substr($name, 2, length($name) - 2); + } + + my $fmt_email = format_email($name, $address, $email_usename); + push(@fmt_emails, $fmt_email); + } + return @fmt_emails; +} + +sub merge_email { + my @lines; + my %saw; + + for (@_) { + my ($address, $role) = @$_; + if (!$saw{$address}) { + if ($output_roles) { + push(@lines, "$address ($role)"); + } else { + push(@lines, $address); + } + $saw{$address} = 1; + } + } + + return @lines; +} + +sub output { + my (@parms) = @_; + + if ($output_multiline) { + foreach my $line (@parms) { + print("${line}\n"); + } + } else { + print(join($output_separator, @parms)); + print("\n"); + } +} + +my $rfc822re; + +sub make_rfc822re { +# Basic lexical tokens are specials, domain_literal, quoted_string, atom, and +# comment. We must allow for rfc822_lwsp (or comments) after each of these. +# This regexp will only work on addresses which have had comments stripped +# and replaced with rfc822_lwsp. + + my $specials = '()<>@,;:\\\\".\\[\\]'; + my $controls = '\\000-\\037\\177'; + + my $dtext = "[^\\[\\]\\r\\\\]"; + my $domain_literal = "\\[(?:$dtext|\\\\.)*\\]$rfc822_lwsp*"; + + my $quoted_string = "\"(?:[^\\\"\\r\\\\]|\\\\.|$rfc822_lwsp)*\"$rfc822_lwsp*"; + +# Use zero-width assertion to spot the limit of an atom. A simple +# $rfc822_lwsp* causes the regexp engine to hang occasionally. + my $atom = "[^$specials $controls]+(?:$rfc822_lwsp+|\\Z|(?=[\\[\"$specials]))"; + my $word = "(?:$atom|$quoted_string)"; + my $localpart = "$word(?:\\.$rfc822_lwsp*$word)*"; + + my $sub_domain = "(?:$atom|$domain_literal)"; + my $domain = "$sub_domain(?:\\.$rfc822_lwsp*$sub_domain)*"; + + my $addr_spec = "$localpart\@$rfc822_lwsp*$domain"; + + my $phrase = "$word*"; + my $route = "(?:\@$domain(?:,\@$rfc822_lwsp*$domain)*:$rfc822_lwsp*)"; + my $route_addr = "\\<$rfc822_lwsp*$route?$addr_spec\\>$rfc822_lwsp*"; + my $mailbox = "(?:$addr_spec|$phrase$route_addr)"; + + my $group = "$phrase:$rfc822_lwsp*(?:$mailbox(?:,\\s*$mailbox)*)?;\\s*"; + my $address = "(?:$mailbox|$group)"; + + return "$rfc822_lwsp*$address"; +} + +sub rfc822_strip_comments { + my $s = shift; +# Recursively remove comments, and replace with a single space. The simpler +# regexps in the Email Addressing FAQ are imperfect - they will miss escaped +# chars in atoms, for example. + + while ($s =~ s/^((?:[^"\\]|\\.)* + (?:"(?:[^"\\]|\\.)*"(?:[^"\\]|\\.)*)*) + \((?:[^()\\]|\\.)*\)/$1 /osx) {} + return $s; +} + +# valid: returns true if the parameter is an RFC822 valid address +# +sub rfc822_valid { + my $s = rfc822_strip_comments(shift); + + if (!$rfc822re) { + $rfc822re = make_rfc822re(); + } + + return $s =~ m/^$rfc822re$/so && $s =~ m/^$rfc822_char*$/; +} + +# validlist: In scalar context, returns true if the parameter is an RFC822 +# valid list of addresses. +# +# In list context, returns an empty list on failure (an invalid +# address was found); otherwise a list whose first element is the +# number of addresses found and whose remaining elements are the +# addresses. This is needed to disambiguate failure (invalid) +# from success with no addresses found, because an empty string is +# a valid list. + +sub rfc822_validlist { + my $s = rfc822_strip_comments(shift); + + if (!$rfc822re) { + $rfc822re = make_rfc822re(); + } + # * null list items are valid according to the RFC + # * the '1' business is to aid in distinguishing failure from no results + + my @r; + if ($s =~ m/^(?:$rfc822re)?(?:,(?:$rfc822re)?)*$/so && + $s =~ m/^$rfc822_char*$/) { + while ($s =~ m/(?:^|,$rfc822_lwsp*)($rfc822re)/gos) { + push(@r, $1); + } + return wantarray ? (scalar(@r), @r) : 1; + } + return wantarray ? () : 0; +} diff --git a/scripts/kconfig/.gitignore b/scripts/kconfig/.gitignore new file mode 100644 index 0000000000..be603c4fef --- /dev/null +++ b/scripts/kconfig/.gitignore @@ -0,0 +1,22 @@ +# +# Generated files +# +config* +*.lex.c +*.tab.c +*.tab.h +zconf.hash.c +*.moc +gconf.glade.h +*.pot +*.mo + +# +# configuration programs +# +conf +mconf +nconf +qconf +gconf +kxgettext diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile new file mode 100644 index 0000000000..349f77038e --- /dev/null +++ b/scripts/kconfig/Makefile @@ -0,0 +1,312 @@ +# =========================================================================== +# Kernel configuration targets +# These targets are used from top-level makefile + +PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config \ + localmodconfig localyesconfig + +ifdef KBUILD_KCONFIG +Kconfig := $(KBUILD_KCONFIG) +else +Kconfig := Kconfig +endif + +# We need this, in case the user has it in its environment +unexport CONFIG_ + +xconfig: $(obj)/qconf + $< $(Kconfig) + +gconfig: $(obj)/gconf + $< $(Kconfig) + +menuconfig: $(obj)/mconf + $< $(Kconfig) + +config: $(obj)/conf + $< --oldaskconfig $(Kconfig) + +nconfig: $(obj)/nconf + $< $(Kconfig) + +oldconfig: $(obj)/conf + $< --$@ $(Kconfig) + +silentoldconfig: $(obj)/conf + $(Q)mkdir -p include/config include/generated + $< --$@ $(Kconfig) + +localyesconfig localmodconfig: $(obj)/streamline_config.pl $(obj)/conf + $(Q)mkdir -p include/config include/generated + $(Q)perl $< --$@ $(srctree) $(Kconfig) > .tmp.config + $(Q)if [ -f .config ]; then \ + cmp -s .tmp.config .config || \ + (mv -f .config .config.old.1; \ + mv -f .tmp.config .config; \ + $(obj)/conf --silentoldconfig $(Kconfig); \ + mv -f .config.old.1 .config.old) \ + else \ + mv -f .tmp.config .config; \ + $(obj)/conf --silentoldconfig $(Kconfig); \ + fi + $(Q)rm -f .tmp.config + +# Create new linux.pot file +# Adjust charset to UTF-8 in .po file to accept UTF-8 in Kconfig files +update-po-config: $(obj)/kxgettext $(obj)/gconf.glade.h + $(Q)echo " GEN config.pot" + $(Q)xgettext --default-domain=linux \ + --add-comments --keyword=_ --keyword=N_ \ + --from-code=UTF-8 \ + --files-from=$(srctree)/scripts/kconfig/POTFILES.in \ + --directory=$(srctree) --directory=$(objtree) \ + --output $(obj)/config.pot + $(Q)sed -i s/CHARSET/UTF-8/ $(obj)/config.pot + $(Q)(for i in `ls $(srctree)/arch/*/Kconfig \ + $(srctree)/arch/*/um/Kconfig`; \ + do \ + echo " GEN $$i"; \ + $(obj)/kxgettext $$i \ + >> $(obj)/config.pot; \ + done ) + $(Q)echo " GEN linux.pot" + $(Q)msguniq --sort-by-file --to-code=UTF-8 $(obj)/config.pot \ + --output $(obj)/linux.pot + $(Q)rm -f $(obj)/config.pot + +PHONY += allnoconfig allyesconfig allmodconfig alldefconfig randconfig + +allnoconfig allyesconfig allmodconfig alldefconfig randconfig: $(obj)/conf + $< --$@ $(Kconfig) + +PHONY += listnewconfig olddefconfig oldnoconfig savedefconfig defconfig + +listnewconfig olddefconfig: $(obj)/conf + $< --$@ $(Kconfig) + +# oldnoconfig is an alias of olddefconfig, because people already are dependent +# on its behavior(sets new symbols to their default value but not 'n') with the +# counter-intuitive name. +oldnoconfig: $(obj)/conf + $< --olddefconfig $(Kconfig) + +savedefconfig: $(obj)/conf + $< --$@=defconfig $(Kconfig) + +defconfig: $(obj)/conf +ifeq ($(KBUILD_DEFCONFIG),) + $< --defconfig $(Kconfig) +else + @echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'" + $(Q)$< --defconfig=arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG) $(Kconfig) +endif + +%_defconfig: $(obj)/conf + $(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig) + +configfiles=$(wildcard $(srctree)/kernel/configs/$(1).config $(srctree)/arch/$(SRCARCH)/configs/$(1).config) + +define mergeconfig +$(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target)) +$(if $(call configfiles,$(1)),, $(error No configuration exists for this target on this architecture)) +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config $(call configfiles,$(1)) +$(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig +endef + +PHONY += kvmconfig +kvmconfig: + $(call mergeconfig,kvm_guest) + +PHONY += tinyconfig +tinyconfig: allnoconfig + $(call mergeconfig,tiny) + +# Help text used by make help +help: + @echo ' config - Update current config utilising a line-oriented program' + @echo ' nconfig - Update current config utilising a ncurses menu based program' + @echo ' menuconfig - Update current config utilising a menu based program' + @echo ' xconfig - Update current config utilising a QT based front-end' + @echo ' gconfig - Update current config utilising a GTK based front-end' + @echo ' oldconfig - Update current config utilising a provided .config as base' + @echo ' localmodconfig - Update current config disabling modules not loaded' + @echo ' localyesconfig - Update current config converting local mods to core' + @echo ' silentoldconfig - Same as oldconfig, but quietly, additionally update deps' + @echo ' defconfig - New config with default from ARCH supplied defconfig' + @echo ' savedefconfig - Save current config as ./defconfig (minimal config)' + @echo ' allnoconfig - New config where all options are answered with no' + @echo ' allyesconfig - New config where all options are accepted with yes' + @echo ' allmodconfig - New config selecting modules when possible' + @echo ' alldefconfig - New config with all symbols set to default' + @echo ' randconfig - New config with random answer to all options' + @echo ' listnewconfig - List new options' + @echo ' olddefconfig - Same as silentoldconfig but sets new symbols to their default value' +# @echo ' kvmconfig - Enable additional options for guest kernel support' +# @echo ' tinyconfig - Configure the tiniest possible kernel' + +# lxdialog stuff +check-lxdialog := $(srctree)/$(src)/lxdialog/check-lxdialog.sh + +# Use recursively expanded variables so we do not call gcc unless +# we really need to do so. (Do not call gcc as part of make mrproper) +HOST_EXTRACFLAGS += $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags) \ + -DLOCALE + +# =========================================================================== +# Shared Makefile for the various kconfig executables: +# conf: Used for defconfig, oldconfig and related targets +# nconf: Used for the nconfig target. +# Utilizes ncurses +# mconf: Used for the menuconfig target +# Utilizes the lxdialog package +# qconf: Used for the xconfig target +# Based on QT which needs to be installed to compile it +# gconf: Used for the gconfig target +# Based on GTK which needs to be installed to compile it +# object files used by all kconfig flavours + +lxdialog := lxdialog/checklist.o lxdialog/util.o lxdialog/inputbox.o +lxdialog += lxdialog/textbox.o lxdialog/yesno.o lxdialog/menubox.o + +conf-objs := conf.o zconf.tab.o +mconf-objs := mconf.o zconf.tab.o $(lxdialog) +nconf-objs := nconf.o zconf.tab.o nconf.gui.o +kxgettext-objs := kxgettext.o zconf.tab.o +qconf-cxxobjs := qconf.o +qconf-objs := zconf.tab.o +gconf-objs := gconf.o zconf.tab.o + +hostprogs-y := conf nconf mconf kxgettext qconf gconf + +clean-files := qconf.moc .tmp_qtcheck .tmp_gtkcheck +clean-files += zconf.tab.c zconf.lex.c zconf.hash.c gconf.glade.h +clean-files += config.pot linux.pot + +# Check that we have the required ncurses stuff installed for lxdialog (menuconfig) +PHONY += $(obj)/dochecklxdialog +$(addprefix $(obj)/,$(lxdialog)): $(obj)/dochecklxdialog +$(obj)/dochecklxdialog: + $(Q)$(CONFIG_SHELL) $(check-lxdialog) -check $(HOSTCC) $(HOST_EXTRACFLAGS) $(HOSTLOADLIBES_mconf) + +always := dochecklxdialog + +# Add environment specific flags +HOST_EXTRACFLAGS += $(shell $(CONFIG_SHELL) $(srctree)/$(src)/check.sh $(HOSTCC) $(HOSTCFLAGS)) + +# generated files seem to need this to find local include files +HOSTCFLAGS_zconf.lex.o := -I$(src) +HOSTCFLAGS_zconf.tab.o := -I$(src) + +LEX_PREFIX_zconf := zconf +YACC_PREFIX_zconf := zconf + +HOSTLOADLIBES_qconf = $(KC_QT_LIBS) +HOSTCXXFLAGS_qconf.o = $(KC_QT_CFLAGS) + +HOSTLOADLIBES_gconf = `pkg-config --libs gtk+-2.0 gmodule-2.0 libglade-2.0` +HOSTCFLAGS_gconf.o = `pkg-config --cflags gtk+-2.0 gmodule-2.0 libglade-2.0` \ + -Wno-missing-prototypes + +HOSTLOADLIBES_mconf = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC)) + +HOSTLOADLIBES_nconf = $(shell \ + pkg-config --libs menuw panelw ncursesw 2>/dev/null \ + || pkg-config --libs menu panel ncurses 2>/dev/null \ + || echo "-lmenu -lpanel -lncurses" ) +$(obj)/qconf.o: $(obj)/.tmp_qtcheck + +ifeq ($(MAKECMDGOALS),xconfig) +$(obj)/.tmp_qtcheck: $(src)/Makefile +-include $(obj)/.tmp_qtcheck + +# QT needs some extra effort... +$(obj)/.tmp_qtcheck: + @set -e; echo " CHECK qt"; dir=""; pkg=""; \ + if ! pkg-config --exists QtCore 2> /dev/null; then \ + echo "* Unable to find the QT4 tool qmake. Trying to use QT3"; \ + pkg-config --exists qt 2> /dev/null && pkg=qt; \ + pkg-config --exists qt-mt 2> /dev/null && pkg=qt-mt; \ + if [ -n "$$pkg" ]; then \ + cflags="\$$(shell pkg-config $$pkg --cflags)"; \ + libs="\$$(shell pkg-config $$pkg --libs)"; \ + moc="\$$(shell pkg-config $$pkg --variable=prefix)/bin/moc"; \ + dir="$$(pkg-config $$pkg --variable=prefix)"; \ + else \ + for d in $$QTDIR /usr/share/qt* /usr/lib/qt*; do \ + if [ -f $$d/include/qconfig.h ]; then dir=$$d; break; fi; \ + done; \ + if [ -z "$$dir" ]; then \ + echo >&2 "*"; \ + echo >&2 "* Unable to find any QT installation. Please make sure that"; \ + echo >&2 "* the QT4 or QT3 development package is correctly installed and"; \ + echo >&2 "* either qmake can be found or install pkg-config or set"; \ + echo >&2 "* the QTDIR environment variable to the correct location."; \ + echo >&2 "*"; \ + false; \ + fi; \ + libpath=$$dir/lib; lib=qt; osdir=""; \ + $(HOSTCXX) -print-multi-os-directory > /dev/null 2>&1 && \ + osdir=x$$($(HOSTCXX) -print-multi-os-directory); \ + test -d $$libpath/$$osdir && libpath=$$libpath/$$osdir; \ + test -f $$libpath/libqt-mt.so && lib=qt-mt; \ + cflags="-I$$dir/include"; \ + libs="-L$$libpath -Wl,-rpath,$$libpath -l$$lib"; \ + moc="$$dir/bin/moc"; \ + fi; \ + if [ ! -x $$dir/bin/moc -a -x /usr/bin/moc ]; then \ + echo "*"; \ + echo "* Unable to find $$dir/bin/moc, using /usr/bin/moc instead."; \ + echo "*"; \ + moc="/usr/bin/moc"; \ + fi; \ + else \ + cflags="\$$(shell pkg-config QtCore QtGui Qt3Support --cflags)"; \ + libs="\$$(shell pkg-config QtCore QtGui Qt3Support --libs)"; \ + moc="\$$(shell pkg-config QtCore --variable=moc_location)"; \ + [ -n "$$moc" ] || moc="\$$(shell pkg-config QtCore --variable=prefix)/bin/moc"; \ + fi; \ + echo "KC_QT_CFLAGS=$$cflags" > $@; \ + echo "KC_QT_LIBS=$$libs" >> $@; \ + echo "KC_QT_MOC=$$moc" >> $@ +endif + +$(obj)/gconf.o: $(obj)/.tmp_gtkcheck + +ifeq ($(MAKECMDGOALS),gconfig) +-include $(obj)/.tmp_gtkcheck + +# GTK needs some extra effort, too... +$(obj)/.tmp_gtkcheck: + @if `pkg-config --exists gtk+-2.0 gmodule-2.0 libglade-2.0`; then \ + if `pkg-config --atleast-version=2.0.0 gtk+-2.0`; then \ + touch $@; \ + else \ + echo >&2 "*"; \ + echo >&2 "* GTK+ is present but version >= 2.0.0 is required."; \ + echo >&2 "*"; \ + false; \ + fi \ + else \ + echo >&2 "*"; \ + echo >&2 "* Unable to find the GTK+ installation. Please make sure that"; \ + echo >&2 "* the GTK+ 2.0 development package is correctly installed..."; \ + echo >&2 "* You need gtk+-2.0, glib-2.0 and libglade-2.0."; \ + echo >&2 "*"; \ + false; \ + fi +endif + +$(obj)/zconf.tab.o: $(obj)/zconf.lex.c $(obj)/zconf.hash.c + +$(obj)/qconf.o: $(obj)/qconf.moc + +quiet_cmd_moc = MOC $@ + cmd_moc = $(KC_QT_MOC) -i $< -o $@ + +$(obj)/%.moc: $(src)/%.h $(obj)/.tmp_qtcheck + $(call cmd,moc) + +# Extract gconf menu items for I18N support +$(obj)/gconf.glade.h: $(obj)/gconf.glade + $(Q)intltool-extract --type=gettext/glade --srcdir=$(srctree) \ + $(obj)/gconf.glade diff --git a/scripts/kconfig/POTFILES.in b/scripts/kconfig/POTFILES.in new file mode 100644 index 0000000000..9674573969 --- /dev/null +++ b/scripts/kconfig/POTFILES.in @@ -0,0 +1,12 @@ +scripts/kconfig/lxdialog/checklist.c +scripts/kconfig/lxdialog/inputbox.c +scripts/kconfig/lxdialog/menubox.c +scripts/kconfig/lxdialog/textbox.c +scripts/kconfig/lxdialog/util.c +scripts/kconfig/lxdialog/yesno.c +scripts/kconfig/mconf.c +scripts/kconfig/conf.c +scripts/kconfig/confdata.c +scripts/kconfig/gconf.c +scripts/kconfig/gconf.glade.h +scripts/kconfig/qconf.cc diff --git a/scripts/kconfig/check.sh b/scripts/kconfig/check.sh new file mode 100755 index 0000000000..55b79ba1ba --- /dev/null +++ b/scripts/kconfig/check.sh @@ -0,0 +1,13 @@ +#!/bin/sh +# Needed for systems without gettext +$* -x c -o /dev/null - > /dev/null 2>&1 << EOF +#include +int main() +{ + gettext(""); + return 0; +} +EOF +if [ ! "$?" -eq "0" ]; then + echo -DKBUILD_NO_NLS; +fi diff --git a/scripts/kconfig/conf.c b/scripts/kconfig/conf.c new file mode 100644 index 0000000000..fef75fc756 --- /dev/null +++ b/scripts/kconfig/conf.c @@ -0,0 +1,718 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lkc.h" + +static void conf(struct menu *menu); +static void check_conf(struct menu *menu); +static void xfgets(char *str, int size, FILE *in); + +enum input_mode { + oldaskconfig, + silentoldconfig, + oldconfig, + allnoconfig, + allyesconfig, + allmodconfig, + alldefconfig, + randconfig, + defconfig, + savedefconfig, + listnewconfig, + olddefconfig, +} input_mode = oldaskconfig; + +static int indent = 1; +static int tty_stdio; +static int valid_stdin = 1; +static int sync_kconfig; +static int conf_cnt; +static char line[128]; +static struct menu *rootEntry; + +static void print_help(struct menu *menu) +{ + struct gstr help = str_new(); + + menu_get_ext_help(menu, &help); + + printf("\n%s\n", str_get(&help)); + str_free(&help); +} + +static void strip(char *str) +{ + char *p = str; + int l; + + while ((isspace(*p))) + p++; + l = strlen(p); + if (p != str) + memmove(str, p, l + 1); + if (!l) + return; + p = str + l - 1; + while ((isspace(*p))) + *p-- = 0; +} + +static void check_stdin(void) +{ + if (!valid_stdin) { + printf(_("aborted!\n\n")); + printf(_("Console input/output is redirected. ")); + printf(_("Run 'make oldconfig' to update configuration.\n\n")); + exit(1); + } +} + +static int conf_askvalue(struct symbol *sym, const char *def) +{ + enum symbol_type type = sym_get_type(sym); + + if (!sym_has_value(sym)) + printf(_("(NEW) ")); + + line[0] = '\n'; + line[1] = 0; + + if (!sym_is_changable(sym)) { + printf("%s\n", def); + line[0] = '\n'; + line[1] = 0; + return 0; + } + + switch (input_mode) { + case oldconfig: + case silentoldconfig: + if (sym_has_value(sym)) { + printf("%s\n", def); + return 0; + } + check_stdin(); + /* fall through */ + case oldaskconfig: + fflush(stdout); + xfgets(line, 128, stdin); + if (!tty_stdio) + printf("\n"); + return 1; + default: + break; + } + + switch (type) { + case S_INT: + case S_HEX: + case S_STRING: + printf("%s\n", def); + return 1; + default: + ; + } + printf("%s", line); + return 1; +} + +static int conf_string(struct menu *menu) +{ + struct symbol *sym = menu->sym; + const char *def; + + while (1) { + printf("%*s%s ", indent - 1, "", _(menu->prompt->text)); + printf("(%s) ", sym->name); + def = sym_get_string_value(sym); + if (sym_get_string_value(sym)) + printf("[%s] ", def); + if (!conf_askvalue(sym, def)) + return 0; + switch (line[0]) { + case '\n': + break; + case '?': + /* print help */ + if (line[1] == '\n') { + print_help(menu); + def = NULL; + break; + } + /* fall through */ + default: + line[strlen(line)-1] = 0; + def = line; + } + if (def && sym_set_string_value(sym, def)) + return 0; + } +} + +static int conf_sym(struct menu *menu) +{ + struct symbol *sym = menu->sym; + tristate oldval, newval; + + while (1) { + printf("%*s%s ", indent - 1, "", _(menu->prompt->text)); + if (sym->name) + printf("(%s) ", sym->name); + putchar('['); + oldval = sym_get_tristate_value(sym); + switch (oldval) { + case no: + putchar('N'); + break; + case mod: + putchar('M'); + break; + case yes: + putchar('Y'); + break; + } + if (oldval != no && sym_tristate_within_range(sym, no)) + printf("/n"); + if (oldval != mod && sym_tristate_within_range(sym, mod)) + printf("/m"); + if (oldval != yes && sym_tristate_within_range(sym, yes)) + printf("/y"); + if (menu_has_help(menu)) + printf("/?"); + printf("] "); + if (!conf_askvalue(sym, sym_get_string_value(sym))) + return 0; + strip(line); + + switch (line[0]) { + case 'n': + case 'N': + newval = no; + if (!line[1] || !strcmp(&line[1], "o")) + break; + continue; + case 'm': + case 'M': + newval = mod; + if (!line[1]) + break; + continue; + case 'y': + case 'Y': + newval = yes; + if (!line[1] || !strcmp(&line[1], "es")) + break; + continue; + case 0: + newval = oldval; + break; + case '?': + goto help; + default: + continue; + } + if (sym_set_tristate_value(sym, newval)) + return 0; +help: + print_help(menu); + } +} + +static int conf_choice(struct menu *menu) +{ + struct symbol *sym, *def_sym; + struct menu *child; + bool is_new; + + sym = menu->sym; + is_new = !sym_has_value(sym); + if (sym_is_changable(sym)) { + conf_sym(menu); + sym_calc_value(sym); + switch (sym_get_tristate_value(sym)) { + case no: + return 1; + case mod: + return 0; + case yes: + break; + } + } else { + switch (sym_get_tristate_value(sym)) { + case no: + return 1; + case mod: + printf("%*s%s\n", indent - 1, "", _(menu_get_prompt(menu))); + return 0; + case yes: + break; + } + } + + while (1) { + int cnt, def; + + printf("%*s%s\n", indent - 1, "", _(menu_get_prompt(menu))); + def_sym = sym_get_choice_value(sym); + cnt = def = 0; + line[0] = 0; + for (child = menu->list; child; child = child->next) { + if (!menu_is_visible(child)) + continue; + if (!child->sym) { + printf("%*c %s\n", indent, '*', _(menu_get_prompt(child))); + continue; + } + cnt++; + if (child->sym == def_sym) { + def = cnt; + printf("%*c", indent, '>'); + } else + printf("%*c", indent, ' '); + printf(" %d. %s", cnt, _(menu_get_prompt(child))); + if (child->sym->name) + printf(" (%s)", child->sym->name); + if (!sym_has_value(child->sym)) + printf(_(" (NEW)")); + printf("\n"); + } + printf(_("%*schoice"), indent - 1, ""); + if (cnt == 1) { + printf("[1]: 1\n"); + goto conf_childs; + } + printf("[1-%d", cnt); + if (menu_has_help(menu)) + printf("?"); + printf("]: "); + switch (input_mode) { + case oldconfig: + case silentoldconfig: + if (!is_new) { + cnt = def; + printf("%d\n", cnt); + break; + } + check_stdin(); + /* fall through */ + case oldaskconfig: + fflush(stdout); + xfgets(line, 128, stdin); + strip(line); + if (line[0] == '?') { + print_help(menu); + continue; + } + if (!line[0]) + cnt = def; + else if (isdigit(line[0])) + cnt = atoi(line); + else + continue; + break; + default: + break; + } + + conf_childs: + for (child = menu->list; child; child = child->next) { + if (!child->sym || !menu_is_visible(child)) + continue; + if (!--cnt) + break; + } + if (!child) + continue; + if (line[0] && line[strlen(line) - 1] == '?') { + print_help(child); + continue; + } + sym_set_choice_value(sym, child->sym); + for (child = child->list; child; child = child->next) { + indent += 2; + conf(child); + indent -= 2; + } + return 1; + } +} + +static void conf(struct menu *menu) +{ + struct symbol *sym; + struct property *prop; + struct menu *child; + + if (!menu_is_visible(menu)) + return; + + sym = menu->sym; + prop = menu->prompt; + if (prop) { + const char *prompt; + + switch (prop->type) { + case P_MENU: + if ((input_mode == silentoldconfig || + input_mode == listnewconfig || + input_mode == olddefconfig) && + rootEntry != menu) { + check_conf(menu); + return; + } + /* fall through */ + case P_COMMENT: + prompt = menu_get_prompt(menu); + if (prompt) + printf("%*c\n%*c %s\n%*c\n", + indent, '*', + indent, '*', _(prompt), + indent, '*'); + default: + ; + } + } + + if (!sym) + goto conf_childs; + + if (sym_is_choice(sym)) { + conf_choice(menu); + if (sym->curr.tri != mod) + return; + goto conf_childs; + } + + switch (sym->type) { + case S_INT: + case S_HEX: + case S_STRING: + conf_string(menu); + break; + default: + conf_sym(menu); + break; + } + +conf_childs: + if (sym) + indent += 2; + for (child = menu->list; child; child = child->next) + conf(child); + if (sym) + indent -= 2; +} + +static void check_conf(struct menu *menu) +{ + struct symbol *sym; + struct menu *child; + + if (!menu_is_visible(menu)) + return; + + sym = menu->sym; + if (sym && !sym_has_value(sym)) { + if (sym_is_changable(sym) || + (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)) { + if (input_mode == listnewconfig) { + if (sym->name && !sym_is_choice_value(sym)) { + printf("%s%s\n", CONFIG_, sym->name); + } + } else if (input_mode != olddefconfig) { + if (!conf_cnt++) + printf(_("*\n* Restart config...\n*\n")); + rootEntry = menu_get_parent_menu(menu); + conf(rootEntry); + } + } + } + + for (child = menu->list; child; child = child->next) + check_conf(child); +} + +static struct option long_opts[] = { + {"oldaskconfig", no_argument, NULL, oldaskconfig}, + {"oldconfig", no_argument, NULL, oldconfig}, + {"silentoldconfig", no_argument, NULL, silentoldconfig}, + {"defconfig", optional_argument, NULL, defconfig}, + {"savedefconfig", required_argument, NULL, savedefconfig}, + {"allnoconfig", no_argument, NULL, allnoconfig}, + {"allyesconfig", no_argument, NULL, allyesconfig}, + {"allmodconfig", no_argument, NULL, allmodconfig}, + {"alldefconfig", no_argument, NULL, alldefconfig}, + {"randconfig", no_argument, NULL, randconfig}, + {"listnewconfig", no_argument, NULL, listnewconfig}, + {"olddefconfig", no_argument, NULL, olddefconfig}, + /* + * oldnoconfig is an alias of olddefconfig, because people already + * are dependent on its behavior(sets new symbols to their default + * value but not 'n') with the counter-intuitive name. + */ + {"oldnoconfig", no_argument, NULL, olddefconfig}, + {NULL, 0, NULL, 0} +}; + +static void conf_usage(const char *progname) +{ + + printf("Usage: %s [option] \n", progname); + printf("[option] is _one_ of the following:\n"); + printf(" --listnewconfig List new options\n"); + printf(" --oldaskconfig Start a new configuration using a line-oriented program\n"); + printf(" --oldconfig Update a configuration using a provided .config as base\n"); + printf(" --silentoldconfig Same as oldconfig, but quietly, additionally update deps\n"); + printf(" --olddefconfig Same as silentoldconfig but sets new symbols to their default value\n"); + printf(" --oldnoconfig An alias of olddefconfig\n"); + printf(" --defconfig New config with default defined in \n"); + printf(" --savedefconfig Save the minimal current configuration to \n"); + printf(" --allnoconfig New config where all options are answered with no\n"); + printf(" --allyesconfig New config where all options are answered with yes\n"); + printf(" --allmodconfig New config where all options are answered with mod\n"); + printf(" --alldefconfig New config with all symbols set to default\n"); + printf(" --randconfig New config with random answer to all options\n"); +} + +int main(int ac, char **av) +{ + const char *progname = av[0]; + int opt; + const char *name, *defconfig_file = NULL /* gcc uninit */; + struct stat tmpstat; + + setlocale(LC_ALL, ""); + bindtextdomain(PACKAGE, LOCALEDIR); + textdomain(PACKAGE); + + tty_stdio = isatty(0) && isatty(1) && isatty(2); + + while ((opt = getopt_long(ac, av, "", long_opts, NULL)) != -1) { + input_mode = (enum input_mode)opt; + switch (opt) { + case silentoldconfig: + sync_kconfig = 1; + break; + case defconfig: + case savedefconfig: + defconfig_file = optarg; + break; + case randconfig: + { + struct timeval now; + unsigned int seed; + char *seed_env; + + /* + * Use microseconds derived seed, + * compensate for systems where it may be zero + */ + gettimeofday(&now, NULL); + seed = (unsigned int)((now.tv_sec + 1) * (now.tv_usec + 1)); + + seed_env = getenv("KCONFIG_SEED"); + if( seed_env && *seed_env ) { + char *endp; + int tmp = (int)strtol(seed_env, &endp, 0); + if (*endp == '\0') { + seed = tmp; + } + } + fprintf( stderr, "KCONFIG_SEED=0x%X\n", seed ); + srand(seed); + break; + } + case oldaskconfig: + case oldconfig: + case allnoconfig: + case allyesconfig: + case allmodconfig: + case alldefconfig: + case listnewconfig: + case olddefconfig: + break; + case '?': + conf_usage(progname); + exit(1); + break; + } + } + if (ac == optind) { + printf(_("%s: Kconfig file missing\n"), av[0]); + conf_usage(progname); + exit(1); + } + name = av[optind]; + conf_parse(name); + //zconfdump(stdout); + if (sync_kconfig) { + name = conf_get_configname(); + if (stat(name, &tmpstat)) { + fprintf(stderr, _("***\n" + "*** Configuration file \"%s\" not found!\n" + "***\n" + "*** Please run some configurator (e.g. \"make oldconfig\" or\n" + "*** \"make menuconfig\" or \"make xconfig\").\n" + "***\n"), name); + exit(1); + } + } + + switch (input_mode) { + case defconfig: + if (!defconfig_file) + defconfig_file = conf_get_default_confname(); + if (conf_read(defconfig_file)) { + printf(_("***\n" + "*** Can't find default configuration \"%s\"!\n" + "***\n"), defconfig_file); + exit(1); + } + break; + case savedefconfig: + case silentoldconfig: + case oldaskconfig: + case oldconfig: + case listnewconfig: + case olddefconfig: + conf_read(NULL); + break; + case allnoconfig: + case allyesconfig: + case allmodconfig: + case alldefconfig: + case randconfig: + name = getenv("KCONFIG_ALLCONFIG"); + if (!name) + break; + if ((strcmp(name, "") != 0) && (strcmp(name, "1") != 0)) { + if (conf_read_simple(name, S_DEF_USER)) { + fprintf(stderr, + _("*** Can't read seed configuration \"%s\"!\n"), + name); + exit(1); + } + break; + } + switch (input_mode) { + case allnoconfig: name = "allno.config"; break; + case allyesconfig: name = "allyes.config"; break; + case allmodconfig: name = "allmod.config"; break; + case alldefconfig: name = "alldef.config"; break; + case randconfig: name = "allrandom.config"; break; + default: break; + } + if (conf_read_simple(name, S_DEF_USER) && + conf_read_simple("all.config", S_DEF_USER)) { + fprintf(stderr, + _("*** KCONFIG_ALLCONFIG set, but no \"%s\" or \"all.config\" file found\n"), + name); + exit(1); + } + break; + default: + break; + } + + if (sync_kconfig) { + if (conf_get_changed()) { + name = getenv("KCONFIG_NOSILENTUPDATE"); + if (name && *name) { + fprintf(stderr, + _("\n*** The configuration requires explicit update.\n\n")); + return 1; + } + } + valid_stdin = tty_stdio; + } + + switch (input_mode) { + case allnoconfig: + conf_set_all_new_symbols(def_no); + break; + case allyesconfig: + conf_set_all_new_symbols(def_yes); + break; + case allmodconfig: + conf_set_all_new_symbols(def_mod); + break; + case alldefconfig: + conf_set_all_new_symbols(def_default); + break; + case randconfig: + /* Really nothing to do in this loop */ + while (conf_set_all_new_symbols(def_random)) ; + break; + case defconfig: + conf_set_all_new_symbols(def_default); + break; + case savedefconfig: + break; + case oldaskconfig: + rootEntry = &rootmenu; + conf(&rootmenu); + input_mode = silentoldconfig; + /* fall through */ + case oldconfig: + case listnewconfig: + case olddefconfig: + case silentoldconfig: + /* Update until a loop caused no more changes */ + do { + conf_cnt = 0; + check_conf(&rootmenu); + } while (conf_cnt && + (input_mode != listnewconfig && + input_mode != olddefconfig)); + break; + } + + if (sync_kconfig) { + /* silentoldconfig is used during the build so we shall update autoconf. + * All other commands are only used to generate a config. + */ + if (conf_get_changed() && conf_write(NULL)) { + fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n")); + exit(1); + } + if (conf_write_autoconf()) { + fprintf(stderr, _("\n*** Error during update of the configuration.\n\n")); + return 1; + } + } else if (input_mode == savedefconfig) { + if (conf_write_defconfig(defconfig_file)) { + fprintf(stderr, _("n*** Error while saving defconfig to: %s\n\n"), + defconfig_file); + return 1; + } + } else if (input_mode != listnewconfig) { + if (conf_write(NULL)) { + fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n")); + exit(1); + } + } + return 0; +} + +/* + * Helper function to facilitate fgets() by Jean Sacren. + */ +void xfgets(char *str, int size, FILE *in) +{ + if (fgets(str, size, in) == NULL) + fprintf(stderr, "\nError in reading or end of file.\n"); +} diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c new file mode 100644 index 0000000000..ae6ce669e1 --- /dev/null +++ b/scripts/kconfig/confdata.c @@ -0,0 +1,1250 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lkc.h" + +static void conf_warning(const char *fmt, ...) + __attribute__ ((format (printf, 1, 2))); + +static void conf_message(const char *fmt, ...) + __attribute__ ((format (printf, 1, 2))); + +static const char *conf_filename; +static int conf_lineno, conf_warnings, conf_unsaved; + +const char conf_defname[] = "arch/$ARCH/defconfig"; + +static void conf_warning(const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + fprintf(stderr, "%s:%d:warning: ", conf_filename, conf_lineno); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + va_end(ap); + conf_warnings++; +} + +static void conf_default_message_callback(const char *fmt, va_list ap) +{ + printf("#\n# "); + vprintf(fmt, ap); + printf("\n#\n"); +} + +static void (*conf_message_callback) (const char *fmt, va_list ap) = + conf_default_message_callback; +void conf_set_message_callback(void (*fn) (const char *fmt, va_list ap)) +{ + conf_message_callback = fn; +} + +static void conf_message(const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + if (conf_message_callback) + conf_message_callback(fmt, ap); +} + +const char *conf_get_configname(void) +{ + char *name = getenv("KCONFIG_CONFIG"); + + return name ? name : ".config"; +} + +const char *conf_get_autoconfig_name(void) +{ + char *name = getenv("KCONFIG_AUTOCONFIG"); + + return name ? name : "include/config/auto.conf"; +} + +static char *conf_expand_value(const char *in) +{ + struct symbol *sym; + const char *src; + static char res_value[SYMBOL_MAXLENGTH]; + char *dst, name[SYMBOL_MAXLENGTH]; + + res_value[0] = 0; + dst = name; + while ((src = strchr(in, '$'))) { + strncat(res_value, in, src - in); + src++; + dst = name; + while (isalnum(*src) || *src == '_') + *dst++ = *src++; + *dst = 0; + sym = sym_lookup(name, 0); + sym_calc_value(sym); + strcat(res_value, sym_get_string_value(sym)); + in = src; + } + strcat(res_value, in); + + return res_value; +} + +char *conf_get_default_confname(void) +{ + struct stat buf; + static char fullname[PATH_MAX+1]; + char *env, *name; + + name = conf_expand_value(conf_defname); + env = getenv(SRCTREE); + if (env) { + sprintf(fullname, "%s/%s", env, name); + if (!stat(fullname, &buf)) + return fullname; + } + return name; +} + +static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p) +{ + char *p2; + + switch (sym->type) { + case S_TRISTATE: + if (p[0] == 'm') { + sym->def[def].tri = mod; + sym->flags |= def_flags; + break; + } + /* fall through */ + case S_BOOLEAN: + if (p[0] == 'y') { + sym->def[def].tri = yes; + sym->flags |= def_flags; + break; + } + if (p[0] == 'n') { + sym->def[def].tri = no; + sym->flags |= def_flags; + break; + } + if (def != S_DEF_AUTO) + conf_warning("symbol value '%s' invalid for %s", + p, sym->name); + return 1; + case S_OTHER: + if (*p != '"') { + for (p2 = p; *p2 && !isspace(*p2); p2++) + ; + sym->type = S_STRING; + goto done; + } + /* fall through */ + case S_STRING: + if (*p++ != '"') + break; + for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) { + if (*p2 == '"') { + *p2 = 0; + break; + } + memmove(p2, p2 + 1, strlen(p2)); + } + if (!p2) { + if (def != S_DEF_AUTO) + conf_warning("invalid string found"); + return 1; + } + /* fall through */ + case S_INT: + case S_HEX: + done: + if (sym_string_valid(sym, p)) { + sym->def[def].val = strdup(p); + sym->flags |= def_flags; + } else { + if (def != S_DEF_AUTO) + conf_warning("symbol value '%s' invalid for %s", + p, sym->name); + return 1; + } + break; + default: + ; + } + return 0; +} + +#define LINE_GROWTH 16 +static int add_byte(int c, char **lineptr, size_t slen, size_t *n) +{ + char *nline; + size_t new_size = slen + 1; + if (new_size > *n) { + new_size += LINE_GROWTH - 1; + new_size *= 2; + nline = realloc(*lineptr, new_size); + if (!nline) + return -1; + + *lineptr = nline; + *n = new_size; + } + + (*lineptr)[slen] = c; + + return 0; +} + +static ssize_t compat_getline(char **lineptr, size_t *n, FILE *stream) +{ + char *line = *lineptr; + size_t slen = 0; + + for (;;) { + int c = getc(stream); + + switch (c) { + case '\n': + if (add_byte(c, &line, slen, n) < 0) + goto e_out; + slen++; + /* fall through */ + case EOF: + if (add_byte('\0', &line, slen, n) < 0) + goto e_out; + *lineptr = line; + if (slen == 0) + return -1; + return slen; + default: + if (add_byte(c, &line, slen, n) < 0) + goto e_out; + slen++; + } + } + +e_out: + line[slen-1] = '\0'; + *lineptr = line; + return -1; +} + +int conf_read_simple(const char *name, int def) +{ + FILE *in = NULL; + char *line = NULL; + size_t line_asize = 0; + char *p, *p2; + struct symbol *sym; + int i, def_flags; + + if (name) { + in = zconf_fopen(name); + } else { + struct property *prop; + + name = conf_get_configname(); + in = zconf_fopen(name); + if (in) + goto load; + sym_add_change_count(1); + if (!sym_defconfig_list) { + if (modules_sym) + sym_calc_value(modules_sym); + return 1; + } + + for_all_defaults(sym_defconfig_list, prop) { + if (expr_calc_value(prop->visible.expr) == no || + prop->expr->type != E_SYMBOL) + continue; + name = conf_expand_value(prop->expr->left.sym->name); + in = zconf_fopen(name); + if (in) { + conf_message(_("using defaults found in %s"), + name); + goto load; + } + } + } + if (!in) + return 1; + +load: + conf_filename = name; + conf_lineno = 0; + conf_warnings = 0; + conf_unsaved = 0; + + def_flags = SYMBOL_DEF << def; + for_all_symbols(i, sym) { + sym->flags |= SYMBOL_CHANGED; + sym->flags &= ~(def_flags|SYMBOL_VALID); + if (sym_is_choice(sym)) + sym->flags |= def_flags; + switch (sym->type) { + case S_INT: + case S_HEX: + case S_STRING: + if (sym->def[def].val) + free(sym->def[def].val); + /* fall through */ + default: + sym->def[def].val = NULL; + sym->def[def].tri = no; + } + } + + while (compat_getline(&line, &line_asize, in) != -1) { + conf_lineno++; + sym = NULL; + if (line[0] == '#') { + if (memcmp(line + 2, CONFIG_, strlen(CONFIG_))) + continue; + p = strchr(line + 2 + strlen(CONFIG_), ' '); + if (!p) + continue; + *p++ = 0; + if (strncmp(p, "is not set", 10)) + continue; + if (def == S_DEF_USER) { + sym = sym_find(line + 2 + strlen(CONFIG_)); + if (!sym) { + sym_add_change_count(1); + goto setsym; + } + } else { + sym = sym_lookup(line + 2 + strlen(CONFIG_), 0); + if (sym->type == S_UNKNOWN) + sym->type = S_BOOLEAN; + } + if (sym->flags & def_flags) { + conf_warning("override: reassigning to symbol %s", sym->name); + } + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + sym->def[def].tri = no; + sym->flags |= def_flags; + break; + default: + ; + } + } else if (memcmp(line, CONFIG_, strlen(CONFIG_)) == 0) { + p = strchr(line + strlen(CONFIG_), '='); + if (!p) + continue; + *p++ = 0; + p2 = strchr(p, '\n'); + if (p2) { + *p2-- = 0; + if (*p2 == '\r') + *p2 = 0; + } + if (def == S_DEF_USER) { + sym = sym_find(line + strlen(CONFIG_)); + if (!sym) { + sym_add_change_count(1); + goto setsym; + } + } else { + sym = sym_lookup(line + strlen(CONFIG_), 0); + if (sym->type == S_UNKNOWN) + sym->type = S_OTHER; + } + if (sym->flags & def_flags) { + conf_warning("override: reassigning to symbol %s", sym->name); + } + if (conf_set_sym_val(sym, def, def_flags, p)) + continue; + } else { + if (line[0] != '\r' && line[0] != '\n') + conf_warning("unexpected data"); + continue; + } +setsym: + if (sym && sym_is_choice_value(sym)) { + struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym)); + switch (sym->def[def].tri) { + case no: + break; + case mod: + if (cs->def[def].tri == yes) { + conf_warning("%s creates inconsistent choice state", sym->name); + cs->flags &= ~def_flags; + } + break; + case yes: + if (cs->def[def].tri != no) + conf_warning("override: %s changes choice state", sym->name); + cs->def[def].val = sym; + break; + } + cs->def[def].tri = EXPR_OR(cs->def[def].tri, sym->def[def].tri); + } + } + free(line); + fclose(in); + + if (modules_sym) + sym_calc_value(modules_sym); + return 0; +} + +int conf_read(const char *name) +{ + struct symbol *sym; + int i; + + sym_set_change_count(0); + + if (conf_read_simple(name, S_DEF_USER)) + return 1; + + for_all_symbols(i, sym) { + sym_calc_value(sym); + if (sym_is_choice(sym) || (sym->flags & SYMBOL_AUTO)) + continue; + if (sym_has_value(sym) && (sym->flags & SYMBOL_WRITE)) { + /* check that calculated value agrees with saved value */ + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + if (sym->def[S_DEF_USER].tri != sym_get_tristate_value(sym)) + break; + if (!sym_is_choice(sym)) + continue; + /* fall through */ + default: + if (!strcmp(sym->curr.val, sym->def[S_DEF_USER].val)) + continue; + break; + } + } else if (!sym_has_value(sym) && !(sym->flags & SYMBOL_WRITE)) + /* no previous value and not saved */ + continue; + conf_unsaved++; + /* maybe print value in verbose mode... */ + } + + for_all_symbols(i, sym) { + if (sym_has_value(sym) && !sym_is_choice_value(sym)) { + /* Reset values of generates values, so they'll appear + * as new, if they should become visible, but that + * doesn't quite work if the Kconfig and the saved + * configuration disagree. + */ + if (sym->visible == no && !conf_unsaved) + sym->flags &= ~SYMBOL_DEF_USER; + switch (sym->type) { + case S_STRING: + case S_INT: + case S_HEX: + /* Reset a string value if it's out of range */ + if (sym_string_within_range(sym, sym->def[S_DEF_USER].val)) + break; + sym->flags &= ~(SYMBOL_VALID|SYMBOL_DEF_USER); + conf_unsaved++; + break; + default: + break; + } + } + } + + sym_add_change_count(conf_warnings || conf_unsaved); + + return 0; +} + +/* + * Kconfig configuration printer + * + * This printer is used when generating the resulting configuration after + * kconfig invocation and `defconfig' files. Unset symbol might be omitted by + * passing a non-NULL argument to the printer. + * + */ +static void +kconfig_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg) +{ + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + if (*value == 'n') { + bool skip_unset = (arg != NULL); + + if (!skip_unset) + fprintf(fp, "# %s%s is not set\n", + CONFIG_, sym->name); + return; + } + break; + default: + break; + } + + fprintf(fp, "%s%s=%s\n", CONFIG_, sym->name, value); +} + +static void +kconfig_print_comment(FILE *fp, const char *value, void *arg) +{ + const char *p = value; + size_t l; + + for (;;) { + l = strcspn(p, "\n"); + fprintf(fp, "#"); + if (l) { + fprintf(fp, " "); + xfwrite(p, l, 1, fp); + p += l; + } + fprintf(fp, "\n"); + if (*p++ == '\0') + break; + } +} + +static struct conf_printer kconfig_printer_cb = +{ + .print_symbol = kconfig_print_symbol, + .print_comment = kconfig_print_comment, +}; + +/* + * Header printer + * + * This printer is used when generating the `include/generated/autoconf.h' file. + */ +static void +header_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg) +{ + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: { + const char *suffix = ""; + + switch (*value) { + case 'n': + break; + case 'm': + suffix = "_MODULE"; + /* fall through */ + default: + fprintf(fp, "#define %s%s%s 1\n", + CONFIG_, sym->name, suffix); + } + break; + } + case S_HEX: { + const char *prefix = ""; + + if (value[0] != '0' || (value[1] != 'x' && value[1] != 'X')) + prefix = "0x"; + fprintf(fp, "#define %s%s %s%s\n", + CONFIG_, sym->name, prefix, value); + break; + } + case S_STRING: + case S_INT: + fprintf(fp, "#define %s%s %s\n", + CONFIG_, sym->name, value); + break; + default: + break; + } + +} + +static void +header_print_comment(FILE *fp, const char *value, void *arg) +{ + const char *p = value; + size_t l; + + fprintf(fp, "/*\n"); + for (;;) { + l = strcspn(p, "\n"); + fprintf(fp, " *"); + if (l) { + fprintf(fp, " "); + xfwrite(p, l, 1, fp); + p += l; + } + fprintf(fp, "\n"); + if (*p++ == '\0') + break; + } + fprintf(fp, " */\n"); +} + +static struct conf_printer header_printer_cb = +{ + .print_symbol = header_print_symbol, + .print_comment = header_print_comment, +}; + +/* + * Tristate printer + * + * This printer is used when generating the `include/config/tristate.conf' file. + */ +static void +tristate_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg) +{ + + if (sym->type == S_TRISTATE && *value != 'n') + fprintf(fp, "%s%s=%c\n", CONFIG_, sym->name, (char)toupper(*value)); +} + +static struct conf_printer tristate_printer_cb = +{ + .print_symbol = tristate_print_symbol, + .print_comment = kconfig_print_comment, +}; + +static void conf_write_symbol(FILE *fp, struct symbol *sym, + struct conf_printer *printer, void *printer_arg) +{ + const char *str; + + switch (sym->type) { + case S_OTHER: + case S_UNKNOWN: + break; + case S_STRING: + str = sym_get_string_value(sym); + str = sym_escape_string_value(str); + printer->print_symbol(fp, sym, str, printer_arg); + free((void *)str); + break; + default: + str = sym_get_string_value(sym); + printer->print_symbol(fp, sym, str, printer_arg); + } +} + +static void +conf_write_heading(FILE *fp, struct conf_printer *printer, void *printer_arg) +{ + char buf[256]; + + snprintf(buf, sizeof(buf), + "\n" + "Automatically generated file; DO NOT EDIT.\n" + "%s\n", + rootmenu.prompt->text); + + printer->print_comment(fp, buf, printer_arg); +} + +/* + * Write out a minimal config. + * All values that has default values are skipped as this is redundant. + */ +int conf_write_defconfig(const char *filename) +{ + struct symbol *sym; + struct menu *menu; + FILE *out; + + out = fopen(filename, "w"); + if (!out) + return 1; + + sym_clear_all_valid(); + + /* Traverse all menus to find all relevant symbols */ + menu = rootmenu.list; + + while (menu != NULL) + { + sym = menu->sym; + if (sym == NULL) { + if (!menu_is_visible(menu)) + goto next_menu; + } else if (!sym_is_choice(sym)) { + sym_calc_value(sym); + if (!(sym->flags & SYMBOL_WRITE)) + goto next_menu; + sym->flags &= ~SYMBOL_WRITE; + /* If we cannot change the symbol - skip */ + if (!sym_is_changable(sym)) + goto next_menu; + /* If symbol equals to default value - skip */ + if (strcmp(sym_get_string_value(sym), sym_get_string_default(sym)) == 0) + goto next_menu; + + /* + * If symbol is a choice value and equals to the + * default for a choice - skip. + * But only if value is bool and equal to "y" and + * choice is not "optional". + * (If choice is "optional" then all values can be "n") + */ + if (sym_is_choice_value(sym)) { + struct symbol *cs; + struct symbol *ds; + + cs = prop_get_symbol(sym_get_choice_prop(sym)); + ds = sym_choice_default(cs); + if (!sym_is_optional(cs) && sym == ds) { + if ((sym->type == S_BOOLEAN) && + sym_get_tristate_value(sym) == yes) + goto next_menu; + } + } + conf_write_symbol(out, sym, &kconfig_printer_cb, NULL); + } +next_menu: + if (menu->list != NULL) { + menu = menu->list; + } + else if (menu->next != NULL) { + menu = menu->next; + } else { + while ((menu = menu->parent)) { + if (menu->next != NULL) { + menu = menu->next; + break; + } + } + } + } + fclose(out); + return 0; +} + +int conf_write(const char *name) +{ + FILE *out; + struct symbol *sym; + struct menu *menu; + const char *basename; + const char *str; + char dirname[PATH_MAX+1], tmpname[PATH_MAX+1], newname[PATH_MAX+1]; + char *env; + + dirname[0] = 0; + if (name && name[0]) { + struct stat st; + char *slash; + + if (!stat(name, &st) && S_ISDIR(st.st_mode)) { + strcpy(dirname, name); + strcat(dirname, "/"); + basename = conf_get_configname(); + } else if ((slash = strrchr(name, '/'))) { + int size = slash - name + 1; + memcpy(dirname, name, size); + dirname[size] = 0; + if (slash[1]) + basename = slash + 1; + else + basename = conf_get_configname(); + } else + basename = name; + } else + basename = conf_get_configname(); + + sprintf(newname, "%s%s", dirname, basename); + env = getenv("KCONFIG_OVERWRITECONFIG"); + if (!env || !*env) { + sprintf(tmpname, "%s.tmpconfig.%d", dirname, (int)getpid()); + out = fopen(tmpname, "w"); + } else { + *tmpname = 0; + out = fopen(newname, "w"); + } + if (!out) + return 1; + + conf_write_heading(out, &kconfig_printer_cb, NULL); + + if (!conf_get_changed()) + sym_clear_all_valid(); + + menu = rootmenu.list; + while (menu) { + sym = menu->sym; + if (!sym) { + if (!menu_is_visible(menu)) + goto next; + str = menu_get_prompt(menu); + fprintf(out, "\n" + "#\n" + "# %s\n" + "#\n", str); + } else if (!(sym->flags & SYMBOL_CHOICE)) { + sym_calc_value(sym); + if (!(sym->flags & SYMBOL_WRITE)) + goto next; + sym->flags &= ~SYMBOL_WRITE; + + conf_write_symbol(out, sym, &kconfig_printer_cb, NULL); + } + +next: + if (menu->list) { + menu = menu->list; + continue; + } + if (menu->next) + menu = menu->next; + else while ((menu = menu->parent)) { + if (menu->next) { + menu = menu->next; + break; + } + } + } + fclose(out); + + if (*tmpname) { + strcat(dirname, basename); + strcat(dirname, ".old"); + rename(newname, dirname); + if (rename(tmpname, newname)) + return 1; + } + + conf_message(_("configuration written to %s"), newname); + + sym_set_change_count(0); + + return 0; +} + +static int conf_split_config(void) +{ + const char *name; + char path[PATH_MAX+1]; + char *s, *d, c; + struct symbol *sym; + struct stat sb; + int res, i, fd; + + name = conf_get_autoconfig_name(); + conf_read_simple(name, S_DEF_AUTO); + + if (chdir("include/config")) + return 1; + + res = 0; + for_all_symbols(i, sym) { + sym_calc_value(sym); + if ((sym->flags & SYMBOL_AUTO) || !sym->name) + continue; + if (sym->flags & SYMBOL_WRITE) { + if (sym->flags & SYMBOL_DEF_AUTO) { + /* + * symbol has old and new value, + * so compare them... + */ + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + if (sym_get_tristate_value(sym) == + sym->def[S_DEF_AUTO].tri) + continue; + break; + case S_STRING: + case S_HEX: + case S_INT: + if (!strcmp(sym_get_string_value(sym), + sym->def[S_DEF_AUTO].val)) + continue; + break; + default: + break; + } + } else { + /* + * If there is no old value, only 'no' (unset) + * is allowed as new value. + */ + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + if (sym_get_tristate_value(sym) == no) + continue; + break; + default: + break; + } + } + } else if (!(sym->flags & SYMBOL_DEF_AUTO)) + /* There is neither an old nor a new value. */ + continue; + /* else + * There is an old value, but no new value ('no' (unset) + * isn't saved in auto.conf, so the old value is always + * different from 'no'). + */ + + /* Replace all '_' and append ".h" */ + s = sym->name; + d = path; + while ((c = *s++)) { + c = tolower(c); + *d++ = (c == '_') ? '/' : c; + } + strcpy(d, ".h"); + + /* Assume directory path already exists. */ + fd = open(path, O_WRONLY | O_CREAT | O_TRUNC, 0644); + if (fd == -1) { + if (errno != ENOENT) { + res = 1; + break; + } + /* + * Create directory components, + * unless they exist already. + */ + d = path; + while ((d = strchr(d, '/'))) { + *d = 0; + if (stat(path, &sb) && mkdir(path, 0755)) { + res = 1; + goto out; + } + *d++ = '/'; + } + /* Try it again. */ + fd = open(path, O_WRONLY | O_CREAT | O_TRUNC, 0644); + if (fd == -1) { + res = 1; + break; + } + } + close(fd); + } +out: + if (chdir("../..")) + return 1; + + return res; +} + +int conf_write_autoconf(void) +{ + struct symbol *sym; + const char *name; + FILE *out, *tristate, *out_h; + int i; + + /* + * Added for U-Boot SPL/TPL + */ + name = getenv("KCONFIG_OBJDIR"); + if (name && name[0]) + if (chdir(name)) + return 1; + + sym_clear_all_valid(); + + file_write_dep("include/config/auto.conf.cmd"); + + if (conf_split_config()) + return 1; + + out = fopen(".tmpconfig", "w"); + if (!out) + return 1; + + tristate = fopen(".tmpconfig_tristate", "w"); + if (!tristate) { + fclose(out); + return 1; + } + + out_h = fopen(".tmpconfig.h", "w"); + if (!out_h) { + fclose(out); + fclose(tristate); + return 1; + } + + conf_write_heading(out, &kconfig_printer_cb, NULL); + + conf_write_heading(tristate, &tristate_printer_cb, NULL); + + conf_write_heading(out_h, &header_printer_cb, NULL); + + for_all_symbols(i, sym) { + sym_calc_value(sym); + if (!(sym->flags & SYMBOL_WRITE) || !sym->name) + continue; + + /* write symbol to auto.conf, tristate and header files */ + conf_write_symbol(out, sym, &kconfig_printer_cb, (void *)1); + + conf_write_symbol(tristate, sym, &tristate_printer_cb, (void *)1); + + conf_write_symbol(out_h, sym, &header_printer_cb, NULL); + } + fclose(out); + fclose(tristate); + fclose(out_h); + + name = getenv("KCONFIG_AUTOHEADER"); + if (!name) + name = "include/generated/autoconf.h"; + if (rename(".tmpconfig.h", name)) + return 1; + name = getenv("KCONFIG_TRISTATE"); + if (!name) + name = "include/config/tristate.conf"; + if (rename(".tmpconfig_tristate", name)) + return 1; + name = conf_get_autoconfig_name(); + /* + * This must be the last step, kbuild has a dependency on auto.conf + * and this marks the successful completion of the previous steps. + */ + if (rename(".tmpconfig", name)) + return 1; + + return 0; +} + +static int sym_change_count; +static void (*conf_changed_callback)(void); + +void sym_set_change_count(int count) +{ + int _sym_change_count = sym_change_count; + sym_change_count = count; + if (conf_changed_callback && + (bool)_sym_change_count != (bool)count) + conf_changed_callback(); +} + +void sym_add_change_count(int count) +{ + sym_set_change_count(count + sym_change_count); +} + +bool conf_get_changed(void) +{ + return sym_change_count; +} + +void conf_set_changed_callback(void (*fn)(void)) +{ + conf_changed_callback = fn; +} + +static bool randomize_choice_values(struct symbol *csym) +{ + struct property *prop; + struct symbol *sym; + struct expr *e; + int cnt, def; + + /* + * If choice is mod then we may have more items selected + * and if no then no-one. + * In both cases stop. + */ + if (csym->curr.tri != yes) + return false; + + prop = sym_get_choice_prop(csym); + + /* count entries in choice block */ + cnt = 0; + expr_list_for_each_sym(prop->expr, e, sym) + cnt++; + + /* + * find a random value and set it to yes, + * set the rest to no so we have only one set + */ + def = (rand() % cnt); + + cnt = 0; + expr_list_for_each_sym(prop->expr, e, sym) { + if (def == cnt++) { + sym->def[S_DEF_USER].tri = yes; + csym->def[S_DEF_USER].val = sym; + } + else { + sym->def[S_DEF_USER].tri = no; + } + sym->flags |= SYMBOL_DEF_USER; + /* clear VALID to get value calculated */ + sym->flags &= ~SYMBOL_VALID; + } + csym->flags |= SYMBOL_DEF_USER; + /* clear VALID to get value calculated */ + csym->flags &= ~(SYMBOL_VALID); + + return true; +} + +void set_all_choice_values(struct symbol *csym) +{ + struct property *prop; + struct symbol *sym; + struct expr *e; + + prop = sym_get_choice_prop(csym); + + /* + * Set all non-assinged choice values to no + */ + expr_list_for_each_sym(prop->expr, e, sym) { + if (!sym_has_value(sym)) + sym->def[S_DEF_USER].tri = no; + } + csym->flags |= SYMBOL_DEF_USER; + /* clear VALID to get value calculated */ + csym->flags &= ~(SYMBOL_VALID | SYMBOL_NEED_SET_CHOICE_VALUES); +} + +bool conf_set_all_new_symbols(enum conf_def_mode mode) +{ + struct symbol *sym, *csym; + int i, cnt, pby, pty, ptm; /* pby: probability of boolean = y + * pty: probability of tristate = y + * ptm: probability of tristate = m + */ + + pby = 50; pty = ptm = 33; /* can't go as the default in switch-case + * below, otherwise gcc whines about + * -Wmaybe-uninitialized */ + if (mode == def_random) { + int n, p[3]; + char *env = getenv("KCONFIG_PROBABILITY"); + n = 0; + while( env && *env ) { + char *endp; + int tmp = strtol( env, &endp, 10 ); + if( tmp >= 0 && tmp <= 100 ) { + p[n++] = tmp; + } else { + errno = ERANGE; + perror( "KCONFIG_PROBABILITY" ); + exit( 1 ); + } + env = (*endp == ':') ? endp+1 : endp; + if( n >=3 ) { + break; + } + } + switch( n ) { + case 1: + pby = p[0]; ptm = pby/2; pty = pby-ptm; + break; + case 2: + pty = p[0]; ptm = p[1]; pby = pty + ptm; + break; + case 3: + pby = p[0]; pty = p[1]; ptm = p[2]; + break; + } + + if( pty+ptm > 100 ) { + errno = ERANGE; + perror( "KCONFIG_PROBABILITY" ); + exit( 1 ); + } + } + bool has_changed = false; + + for_all_symbols(i, sym) { + if (sym_has_value(sym) || (sym->flags & SYMBOL_VALID)) + continue; + switch (sym_get_type(sym)) { + case S_BOOLEAN: + case S_TRISTATE: + has_changed = true; + switch (mode) { + case def_yes: + sym->def[S_DEF_USER].tri = yes; + break; + case def_mod: + sym->def[S_DEF_USER].tri = mod; + break; + case def_no: + if (sym->flags & SYMBOL_ALLNOCONFIG_Y) + sym->def[S_DEF_USER].tri = yes; + else + sym->def[S_DEF_USER].tri = no; + break; + case def_random: + sym->def[S_DEF_USER].tri = no; + cnt = rand() % 100; + if (sym->type == S_TRISTATE) { + if (cnt < pty) + sym->def[S_DEF_USER].tri = yes; + else if (cnt < (pty+ptm)) + sym->def[S_DEF_USER].tri = mod; + } else if (cnt < pby) + sym->def[S_DEF_USER].tri = yes; + break; + default: + continue; + } + if (!(sym_is_choice(sym) && mode == def_random)) + sym->flags |= SYMBOL_DEF_USER; + break; + default: + break; + } + + } + + sym_clear_all_valid(); + + /* + * We have different type of choice blocks. + * If curr.tri equals to mod then we can select several + * choice symbols in one block. + * In this case we do nothing. + * If curr.tri equals yes then only one symbol can be + * selected in a choice block and we set it to yes, + * and the rest to no. + */ + if (mode != def_random) { + for_all_symbols(i, csym) { + if ((sym_is_choice(csym) && !sym_has_value(csym)) || + sym_is_choice_value(csym)) + csym->flags |= SYMBOL_NEED_SET_CHOICE_VALUES; + } + } + + for_all_symbols(i, csym) { + if (sym_has_value(csym) || !sym_is_choice(csym)) + continue; + + sym_calc_value(csym); + if (mode == def_random) + has_changed = randomize_choice_values(csym); + else { + set_all_choice_values(csym); + has_changed = true; + } + } + + return has_changed; +} diff --git a/scripts/kconfig/expr.c b/scripts/kconfig/expr.c new file mode 100644 index 0000000000..d6626521f9 --- /dev/null +++ b/scripts/kconfig/expr.c @@ -0,0 +1,1168 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include + +#include "lkc.h" + +#define DEBUG_EXPR 0 + +struct expr *expr_alloc_symbol(struct symbol *sym) +{ + struct expr *e = xcalloc(1, sizeof(*e)); + e->type = E_SYMBOL; + e->left.sym = sym; + return e; +} + +struct expr *expr_alloc_one(enum expr_type type, struct expr *ce) +{ + struct expr *e = xcalloc(1, sizeof(*e)); + e->type = type; + e->left.expr = ce; + return e; +} + +struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2) +{ + struct expr *e = xcalloc(1, sizeof(*e)); + e->type = type; + e->left.expr = e1; + e->right.expr = e2; + return e; +} + +struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2) +{ + struct expr *e = xcalloc(1, sizeof(*e)); + e->type = type; + e->left.sym = s1; + e->right.sym = s2; + return e; +} + +struct expr *expr_alloc_and(struct expr *e1, struct expr *e2) +{ + if (!e1) + return e2; + return e2 ? expr_alloc_two(E_AND, e1, e2) : e1; +} + +struct expr *expr_alloc_or(struct expr *e1, struct expr *e2) +{ + if (!e1) + return e2; + return e2 ? expr_alloc_two(E_OR, e1, e2) : e1; +} + +struct expr *expr_copy(const struct expr *org) +{ + struct expr *e; + + if (!org) + return NULL; + + e = xmalloc(sizeof(*org)); + memcpy(e, org, sizeof(*org)); + switch (org->type) { + case E_SYMBOL: + e->left = org->left; + break; + case E_NOT: + e->left.expr = expr_copy(org->left.expr); + break; + case E_EQUAL: + case E_UNEQUAL: + e->left.sym = org->left.sym; + e->right.sym = org->right.sym; + break; + case E_AND: + case E_OR: + case E_LIST: + e->left.expr = expr_copy(org->left.expr); + e->right.expr = expr_copy(org->right.expr); + break; + default: + printf("can't copy type %d\n", e->type); + free(e); + e = NULL; + break; + } + + return e; +} + +void expr_free(struct expr *e) +{ + if (!e) + return; + + switch (e->type) { + case E_SYMBOL: + break; + case E_NOT: + expr_free(e->left.expr); + return; + case E_EQUAL: + case E_UNEQUAL: + break; + case E_OR: + case E_AND: + expr_free(e->left.expr); + expr_free(e->right.expr); + break; + default: + printf("how to free type %d?\n", e->type); + break; + } + free(e); +} + +static int trans_count; + +#define e1 (*ep1) +#define e2 (*ep2) + +static void __expr_eliminate_eq(enum expr_type type, struct expr **ep1, struct expr **ep2) +{ + if (e1->type == type) { + __expr_eliminate_eq(type, &e1->left.expr, &e2); + __expr_eliminate_eq(type, &e1->right.expr, &e2); + return; + } + if (e2->type == type) { + __expr_eliminate_eq(type, &e1, &e2->left.expr); + __expr_eliminate_eq(type, &e1, &e2->right.expr); + return; + } + if (e1->type == E_SYMBOL && e2->type == E_SYMBOL && + e1->left.sym == e2->left.sym && + (e1->left.sym == &symbol_yes || e1->left.sym == &symbol_no)) + return; + if (!expr_eq(e1, e2)) + return; + trans_count++; + expr_free(e1); expr_free(e2); + switch (type) { + case E_OR: + e1 = expr_alloc_symbol(&symbol_no); + e2 = expr_alloc_symbol(&symbol_no); + break; + case E_AND: + e1 = expr_alloc_symbol(&symbol_yes); + e2 = expr_alloc_symbol(&symbol_yes); + break; + default: + ; + } +} + +void expr_eliminate_eq(struct expr **ep1, struct expr **ep2) +{ + if (!e1 || !e2) + return; + switch (e1->type) { + case E_OR: + case E_AND: + __expr_eliminate_eq(e1->type, ep1, ep2); + default: + ; + } + if (e1->type != e2->type) switch (e2->type) { + case E_OR: + case E_AND: + __expr_eliminate_eq(e2->type, ep1, ep2); + default: + ; + } + e1 = expr_eliminate_yn(e1); + e2 = expr_eliminate_yn(e2); +} + +#undef e1 +#undef e2 + +int expr_eq(struct expr *e1, struct expr *e2) +{ + int res, old_count; + + if (e1->type != e2->type) + return 0; + switch (e1->type) { + case E_EQUAL: + case E_UNEQUAL: + return e1->left.sym == e2->left.sym && e1->right.sym == e2->right.sym; + case E_SYMBOL: + return e1->left.sym == e2->left.sym; + case E_NOT: + return expr_eq(e1->left.expr, e2->left.expr); + case E_AND: + case E_OR: + e1 = expr_copy(e1); + e2 = expr_copy(e2); + old_count = trans_count; + expr_eliminate_eq(&e1, &e2); + res = (e1->type == E_SYMBOL && e2->type == E_SYMBOL && + e1->left.sym == e2->left.sym); + expr_free(e1); + expr_free(e2); + trans_count = old_count; + return res; + case E_LIST: + case E_RANGE: + case E_NONE: + /* panic */; + } + + if (DEBUG_EXPR) { + expr_fprint(e1, stdout); + printf(" = "); + expr_fprint(e2, stdout); + printf(" ?\n"); + } + + return 0; +} + +struct expr *expr_eliminate_yn(struct expr *e) +{ + struct expr *tmp; + + if (e) switch (e->type) { + case E_AND: + e->left.expr = expr_eliminate_yn(e->left.expr); + e->right.expr = expr_eliminate_yn(e->right.expr); + if (e->left.expr->type == E_SYMBOL) { + if (e->left.expr->left.sym == &symbol_no) { + expr_free(e->left.expr); + expr_free(e->right.expr); + e->type = E_SYMBOL; + e->left.sym = &symbol_no; + e->right.expr = NULL; + return e; + } else if (e->left.expr->left.sym == &symbol_yes) { + free(e->left.expr); + tmp = e->right.expr; + *e = *(e->right.expr); + free(tmp); + return e; + } + } + if (e->right.expr->type == E_SYMBOL) { + if (e->right.expr->left.sym == &symbol_no) { + expr_free(e->left.expr); + expr_free(e->right.expr); + e->type = E_SYMBOL; + e->left.sym = &symbol_no; + e->right.expr = NULL; + return e; + } else if (e->right.expr->left.sym == &symbol_yes) { + free(e->right.expr); + tmp = e->left.expr; + *e = *(e->left.expr); + free(tmp); + return e; + } + } + break; + case E_OR: + e->left.expr = expr_eliminate_yn(e->left.expr); + e->right.expr = expr_eliminate_yn(e->right.expr); + if (e->left.expr->type == E_SYMBOL) { + if (e->left.expr->left.sym == &symbol_no) { + free(e->left.expr); + tmp = e->right.expr; + *e = *(e->right.expr); + free(tmp); + return e; + } else if (e->left.expr->left.sym == &symbol_yes) { + expr_free(e->left.expr); + expr_free(e->right.expr); + e->type = E_SYMBOL; + e->left.sym = &symbol_yes; + e->right.expr = NULL; + return e; + } + } + if (e->right.expr->type == E_SYMBOL) { + if (e->right.expr->left.sym == &symbol_no) { + free(e->right.expr); + tmp = e->left.expr; + *e = *(e->left.expr); + free(tmp); + return e; + } else if (e->right.expr->left.sym == &symbol_yes) { + expr_free(e->left.expr); + expr_free(e->right.expr); + e->type = E_SYMBOL; + e->left.sym = &symbol_yes; + e->right.expr = NULL; + return e; + } + } + break; + default: + ; + } + return e; +} + +/* + * bool FOO!=n => FOO + */ +struct expr *expr_trans_bool(struct expr *e) +{ + if (!e) + return NULL; + switch (e->type) { + case E_AND: + case E_OR: + case E_NOT: + e->left.expr = expr_trans_bool(e->left.expr); + e->right.expr = expr_trans_bool(e->right.expr); + break; + case E_UNEQUAL: + // FOO!=n -> FOO + if (e->left.sym->type == S_TRISTATE) { + if (e->right.sym == &symbol_no) { + e->type = E_SYMBOL; + e->right.sym = NULL; + } + } + break; + default: + ; + } + return e; +} + +/* + * e1 || e2 -> ? + */ +static struct expr *expr_join_or(struct expr *e1, struct expr *e2) +{ + struct expr *tmp; + struct symbol *sym1, *sym2; + + if (expr_eq(e1, e2)) + return expr_copy(e1); + if (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT) + return NULL; + if (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT) + return NULL; + if (e1->type == E_NOT) { + tmp = e1->left.expr; + if (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL) + return NULL; + sym1 = tmp->left.sym; + } else + sym1 = e1->left.sym; + if (e2->type == E_NOT) { + if (e2->left.expr->type != E_SYMBOL) + return NULL; + sym2 = e2->left.expr->left.sym; + } else + sym2 = e2->left.sym; + if (sym1 != sym2) + return NULL; + if (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE) + return NULL; + if (sym1->type == S_TRISTATE) { + if (e1->type == E_EQUAL && e2->type == E_EQUAL && + ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) || + (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes))) { + // (a='y') || (a='m') -> (a!='n') + return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_no); + } + if (e1->type == E_EQUAL && e2->type == E_EQUAL && + ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) || + (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes))) { + // (a='y') || (a='n') -> (a!='m') + return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_mod); + } + if (e1->type == E_EQUAL && e2->type == E_EQUAL && + ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) || + (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod))) { + // (a='m') || (a='n') -> (a!='y') + return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_yes); + } + } + if (sym1->type == S_BOOLEAN && sym1 == sym2) { + if ((e1->type == E_NOT && e1->left.expr->type == E_SYMBOL && e2->type == E_SYMBOL) || + (e2->type == E_NOT && e2->left.expr->type == E_SYMBOL && e1->type == E_SYMBOL)) + return expr_alloc_symbol(&symbol_yes); + } + + if (DEBUG_EXPR) { + printf("optimize ("); + expr_fprint(e1, stdout); + printf(") || ("); + expr_fprint(e2, stdout); + printf(")?\n"); + } + return NULL; +} + +static struct expr *expr_join_and(struct expr *e1, struct expr *e2) +{ + struct expr *tmp; + struct symbol *sym1, *sym2; + + if (expr_eq(e1, e2)) + return expr_copy(e1); + if (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT) + return NULL; + if (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT) + return NULL; + if (e1->type == E_NOT) { + tmp = e1->left.expr; + if (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL) + return NULL; + sym1 = tmp->left.sym; + } else + sym1 = e1->left.sym; + if (e2->type == E_NOT) { + if (e2->left.expr->type != E_SYMBOL) + return NULL; + sym2 = e2->left.expr->left.sym; + } else + sym2 = e2->left.sym; + if (sym1 != sym2) + return NULL; + if (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE) + return NULL; + + if ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_yes) || + (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_yes)) + // (a) && (a='y') -> (a='y') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes); + + if ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_no) || + (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_no)) + // (a) && (a!='n') -> (a) + return expr_alloc_symbol(sym1); + + if ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_mod) || + (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_mod)) + // (a) && (a!='m') -> (a='y') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes); + + if (sym1->type == S_TRISTATE) { + if (e1->type == E_EQUAL && e2->type == E_UNEQUAL) { + // (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b' + sym2 = e1->right.sym; + if ((e2->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST)) + return sym2 != e2->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2) + : expr_alloc_symbol(&symbol_no); + } + if (e1->type == E_UNEQUAL && e2->type == E_EQUAL) { + // (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b' + sym2 = e2->right.sym; + if ((e1->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST)) + return sym2 != e1->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2) + : expr_alloc_symbol(&symbol_no); + } + if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL && + ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) || + (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes))) + // (a!='y') && (a!='n') -> (a='m') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_mod); + + if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL && + ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) || + (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes))) + // (a!='y') && (a!='m') -> (a='n') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_no); + + if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL && + ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) || + (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod))) + // (a!='m') && (a!='n') -> (a='m') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes); + + if ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_mod) || + (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_mod) || + (e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_yes) || + (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_yes)) + return NULL; + } + + if (DEBUG_EXPR) { + printf("optimize ("); + expr_fprint(e1, stdout); + printf(") && ("); + expr_fprint(e2, stdout); + printf(")?\n"); + } + return NULL; +} + +static void expr_eliminate_dups1(enum expr_type type, struct expr **ep1, struct expr **ep2) +{ +#define e1 (*ep1) +#define e2 (*ep2) + struct expr *tmp; + + if (e1->type == type) { + expr_eliminate_dups1(type, &e1->left.expr, &e2); + expr_eliminate_dups1(type, &e1->right.expr, &e2); + return; + } + if (e2->type == type) { + expr_eliminate_dups1(type, &e1, &e2->left.expr); + expr_eliminate_dups1(type, &e1, &e2->right.expr); + return; + } + if (e1 == e2) + return; + + switch (e1->type) { + case E_OR: case E_AND: + expr_eliminate_dups1(e1->type, &e1, &e1); + default: + ; + } + + switch (type) { + case E_OR: + tmp = expr_join_or(e1, e2); + if (tmp) { + expr_free(e1); expr_free(e2); + e1 = expr_alloc_symbol(&symbol_no); + e2 = tmp; + trans_count++; + } + break; + case E_AND: + tmp = expr_join_and(e1, e2); + if (tmp) { + expr_free(e1); expr_free(e2); + e1 = expr_alloc_symbol(&symbol_yes); + e2 = tmp; + trans_count++; + } + break; + default: + ; + } +#undef e1 +#undef e2 +} + +static void expr_eliminate_dups2(enum expr_type type, struct expr **ep1, struct expr **ep2) +{ +#define e1 (*ep1) +#define e2 (*ep2) + struct expr *tmp, *tmp1, *tmp2; + + if (e1->type == type) { + expr_eliminate_dups2(type, &e1->left.expr, &e2); + expr_eliminate_dups2(type, &e1->right.expr, &e2); + return; + } + if (e2->type == type) { + expr_eliminate_dups2(type, &e1, &e2->left.expr); + expr_eliminate_dups2(type, &e1, &e2->right.expr); + } + if (e1 == e2) + return; + + switch (e1->type) { + case E_OR: + expr_eliminate_dups2(e1->type, &e1, &e1); + // (FOO || BAR) && (!FOO && !BAR) -> n + tmp1 = expr_transform(expr_alloc_one(E_NOT, expr_copy(e1))); + tmp2 = expr_copy(e2); + tmp = expr_extract_eq_and(&tmp1, &tmp2); + if (expr_is_yes(tmp1)) { + expr_free(e1); + e1 = expr_alloc_symbol(&symbol_no); + trans_count++; + } + expr_free(tmp2); + expr_free(tmp1); + expr_free(tmp); + break; + case E_AND: + expr_eliminate_dups2(e1->type, &e1, &e1); + // (FOO && BAR) || (!FOO || !BAR) -> y + tmp1 = expr_transform(expr_alloc_one(E_NOT, expr_copy(e1))); + tmp2 = expr_copy(e2); + tmp = expr_extract_eq_or(&tmp1, &tmp2); + if (expr_is_no(tmp1)) { + expr_free(e1); + e1 = expr_alloc_symbol(&symbol_yes); + trans_count++; + } + expr_free(tmp2); + expr_free(tmp1); + expr_free(tmp); + break; + default: + ; + } +#undef e1 +#undef e2 +} + +struct expr *expr_eliminate_dups(struct expr *e) +{ + int oldcount; + if (!e) + return e; + + oldcount = trans_count; + while (1) { + trans_count = 0; + switch (e->type) { + case E_OR: case E_AND: + expr_eliminate_dups1(e->type, &e, &e); + expr_eliminate_dups2(e->type, &e, &e); + default: + ; + } + if (!trans_count) + break; + e = expr_eliminate_yn(e); + } + trans_count = oldcount; + return e; +} + +struct expr *expr_transform(struct expr *e) +{ + struct expr *tmp; + + if (!e) + return NULL; + switch (e->type) { + case E_EQUAL: + case E_UNEQUAL: + case E_SYMBOL: + case E_LIST: + break; + default: + e->left.expr = expr_transform(e->left.expr); + e->right.expr = expr_transform(e->right.expr); + } + + switch (e->type) { + case E_EQUAL: + if (e->left.sym->type != S_BOOLEAN) + break; + if (e->right.sym == &symbol_no) { + e->type = E_NOT; + e->left.expr = expr_alloc_symbol(e->left.sym); + e->right.sym = NULL; + break; + } + if (e->right.sym == &symbol_mod) { + printf("boolean symbol %s tested for 'm'? test forced to 'n'\n", e->left.sym->name); + e->type = E_SYMBOL; + e->left.sym = &symbol_no; + e->right.sym = NULL; + break; + } + if (e->right.sym == &symbol_yes) { + e->type = E_SYMBOL; + e->right.sym = NULL; + break; + } + break; + case E_UNEQUAL: + if (e->left.sym->type != S_BOOLEAN) + break; + if (e->right.sym == &symbol_no) { + e->type = E_SYMBOL; + e->right.sym = NULL; + break; + } + if (e->right.sym == &symbol_mod) { + printf("boolean symbol %s tested for 'm'? test forced to 'y'\n", e->left.sym->name); + e->type = E_SYMBOL; + e->left.sym = &symbol_yes; + e->right.sym = NULL; + break; + } + if (e->right.sym == &symbol_yes) { + e->type = E_NOT; + e->left.expr = expr_alloc_symbol(e->left.sym); + e->right.sym = NULL; + break; + } + break; + case E_NOT: + switch (e->left.expr->type) { + case E_NOT: + // !!a -> a + tmp = e->left.expr->left.expr; + free(e->left.expr); + free(e); + e = tmp; + e = expr_transform(e); + break; + case E_EQUAL: + case E_UNEQUAL: + // !a='x' -> a!='x' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = e->type == E_EQUAL ? E_UNEQUAL : E_EQUAL; + break; + case E_OR: + // !(a || b) -> !a && !b + tmp = e->left.expr; + e->type = E_AND; + e->right.expr = expr_alloc_one(E_NOT, tmp->right.expr); + tmp->type = E_NOT; + tmp->right.expr = NULL; + e = expr_transform(e); + break; + case E_AND: + // !(a && b) -> !a || !b + tmp = e->left.expr; + e->type = E_OR; + e->right.expr = expr_alloc_one(E_NOT, tmp->right.expr); + tmp->type = E_NOT; + tmp->right.expr = NULL; + e = expr_transform(e); + break; + case E_SYMBOL: + if (e->left.expr->left.sym == &symbol_yes) { + // !'y' -> 'n' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = E_SYMBOL; + e->left.sym = &symbol_no; + break; + } + if (e->left.expr->left.sym == &symbol_mod) { + // !'m' -> 'm' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = E_SYMBOL; + e->left.sym = &symbol_mod; + break; + } + if (e->left.expr->left.sym == &symbol_no) { + // !'n' -> 'y' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = E_SYMBOL; + e->left.sym = &symbol_yes; + break; + } + break; + default: + ; + } + break; + default: + ; + } + return e; +} + +int expr_contains_symbol(struct expr *dep, struct symbol *sym) +{ + if (!dep) + return 0; + + switch (dep->type) { + case E_AND: + case E_OR: + return expr_contains_symbol(dep->left.expr, sym) || + expr_contains_symbol(dep->right.expr, sym); + case E_SYMBOL: + return dep->left.sym == sym; + case E_EQUAL: + case E_UNEQUAL: + return dep->left.sym == sym || + dep->right.sym == sym; + case E_NOT: + return expr_contains_symbol(dep->left.expr, sym); + default: + ; + } + return 0; +} + +bool expr_depends_symbol(struct expr *dep, struct symbol *sym) +{ + if (!dep) + return false; + + switch (dep->type) { + case E_AND: + return expr_depends_symbol(dep->left.expr, sym) || + expr_depends_symbol(dep->right.expr, sym); + case E_SYMBOL: + return dep->left.sym == sym; + case E_EQUAL: + if (dep->left.sym == sym) { + if (dep->right.sym == &symbol_yes || dep->right.sym == &symbol_mod) + return true; + } + break; + case E_UNEQUAL: + if (dep->left.sym == sym) { + if (dep->right.sym == &symbol_no) + return true; + } + break; + default: + ; + } + return false; +} + +struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2) +{ + struct expr *tmp = NULL; + expr_extract_eq(E_AND, &tmp, ep1, ep2); + if (tmp) { + *ep1 = expr_eliminate_yn(*ep1); + *ep2 = expr_eliminate_yn(*ep2); + } + return tmp; +} + +struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2) +{ + struct expr *tmp = NULL; + expr_extract_eq(E_OR, &tmp, ep1, ep2); + if (tmp) { + *ep1 = expr_eliminate_yn(*ep1); + *ep2 = expr_eliminate_yn(*ep2); + } + return tmp; +} + +void expr_extract_eq(enum expr_type type, struct expr **ep, struct expr **ep1, struct expr **ep2) +{ +#define e1 (*ep1) +#define e2 (*ep2) + if (e1->type == type) { + expr_extract_eq(type, ep, &e1->left.expr, &e2); + expr_extract_eq(type, ep, &e1->right.expr, &e2); + return; + } + if (e2->type == type) { + expr_extract_eq(type, ep, ep1, &e2->left.expr); + expr_extract_eq(type, ep, ep1, &e2->right.expr); + return; + } + if (expr_eq(e1, e2)) { + *ep = *ep ? expr_alloc_two(type, *ep, e1) : e1; + expr_free(e2); + if (type == E_AND) { + e1 = expr_alloc_symbol(&symbol_yes); + e2 = expr_alloc_symbol(&symbol_yes); + } else if (type == E_OR) { + e1 = expr_alloc_symbol(&symbol_no); + e2 = expr_alloc_symbol(&symbol_no); + } + } +#undef e1 +#undef e2 +} + +struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym) +{ + struct expr *e1, *e2; + + if (!e) { + e = expr_alloc_symbol(sym); + if (type == E_UNEQUAL) + e = expr_alloc_one(E_NOT, e); + return e; + } + switch (e->type) { + case E_AND: + e1 = expr_trans_compare(e->left.expr, E_EQUAL, sym); + e2 = expr_trans_compare(e->right.expr, E_EQUAL, sym); + if (sym == &symbol_yes) + e = expr_alloc_two(E_AND, e1, e2); + if (sym == &symbol_no) + e = expr_alloc_two(E_OR, e1, e2); + if (type == E_UNEQUAL) + e = expr_alloc_one(E_NOT, e); + return e; + case E_OR: + e1 = expr_trans_compare(e->left.expr, E_EQUAL, sym); + e2 = expr_trans_compare(e->right.expr, E_EQUAL, sym); + if (sym == &symbol_yes) + e = expr_alloc_two(E_OR, e1, e2); + if (sym == &symbol_no) + e = expr_alloc_two(E_AND, e1, e2); + if (type == E_UNEQUAL) + e = expr_alloc_one(E_NOT, e); + return e; + case E_NOT: + return expr_trans_compare(e->left.expr, type == E_EQUAL ? E_UNEQUAL : E_EQUAL, sym); + case E_UNEQUAL: + case E_EQUAL: + if (type == E_EQUAL) { + if (sym == &symbol_yes) + return expr_copy(e); + if (sym == &symbol_mod) + return expr_alloc_symbol(&symbol_no); + if (sym == &symbol_no) + return expr_alloc_one(E_NOT, expr_copy(e)); + } else { + if (sym == &symbol_yes) + return expr_alloc_one(E_NOT, expr_copy(e)); + if (sym == &symbol_mod) + return expr_alloc_symbol(&symbol_yes); + if (sym == &symbol_no) + return expr_copy(e); + } + break; + case E_SYMBOL: + return expr_alloc_comp(type, e->left.sym, sym); + case E_LIST: + case E_RANGE: + case E_NONE: + /* panic */; + } + return NULL; +} + +tristate expr_calc_value(struct expr *e) +{ + tristate val1, val2; + const char *str1, *str2; + + if (!e) + return yes; + + switch (e->type) { + case E_SYMBOL: + sym_calc_value(e->left.sym); + return e->left.sym->curr.tri; + case E_AND: + val1 = expr_calc_value(e->left.expr); + val2 = expr_calc_value(e->right.expr); + return EXPR_AND(val1, val2); + case E_OR: + val1 = expr_calc_value(e->left.expr); + val2 = expr_calc_value(e->right.expr); + return EXPR_OR(val1, val2); + case E_NOT: + val1 = expr_calc_value(e->left.expr); + return EXPR_NOT(val1); + case E_EQUAL: + sym_calc_value(e->left.sym); + sym_calc_value(e->right.sym); + str1 = sym_get_string_value(e->left.sym); + str2 = sym_get_string_value(e->right.sym); + return !strcmp(str1, str2) ? yes : no; + case E_UNEQUAL: + sym_calc_value(e->left.sym); + sym_calc_value(e->right.sym); + str1 = sym_get_string_value(e->left.sym); + str2 = sym_get_string_value(e->right.sym); + return !strcmp(str1, str2) ? no : yes; + default: + printf("expr_calc_value: %d?\n", e->type); + return no; + } +} + +int expr_compare_type(enum expr_type t1, enum expr_type t2) +{ +#if 0 + return 1; +#else + if (t1 == t2) + return 0; + switch (t1) { + case E_EQUAL: + case E_UNEQUAL: + if (t2 == E_NOT) + return 1; + case E_NOT: + if (t2 == E_AND) + return 1; + case E_AND: + if (t2 == E_OR) + return 1; + case E_OR: + if (t2 == E_LIST) + return 1; + case E_LIST: + if (t2 == 0) + return 1; + default: + return -1; + } + printf("[%dgt%d?]", t1, t2); + return 0; +#endif +} + +static inline struct expr * +expr_get_leftmost_symbol(const struct expr *e) +{ + + if (e == NULL) + return NULL; + + while (e->type != E_SYMBOL) + e = e->left.expr; + + return expr_copy(e); +} + +/* + * Given expression `e1' and `e2', returns the leaf of the longest + * sub-expression of `e1' not containing 'e2. + */ +struct expr *expr_simplify_unmet_dep(struct expr *e1, struct expr *e2) +{ + struct expr *ret; + + switch (e1->type) { + case E_OR: + return expr_alloc_and( + expr_simplify_unmet_dep(e1->left.expr, e2), + expr_simplify_unmet_dep(e1->right.expr, e2)); + case E_AND: { + struct expr *e; + e = expr_alloc_and(expr_copy(e1), expr_copy(e2)); + e = expr_eliminate_dups(e); + ret = (!expr_eq(e, e1)) ? e1 : NULL; + expr_free(e); + break; + } + default: + ret = e1; + break; + } + + return expr_get_leftmost_symbol(ret); +} + +void expr_print(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken) +{ + if (!e) { + fn(data, NULL, "y"); + return; + } + + if (expr_compare_type(prevtoken, e->type) > 0) + fn(data, NULL, "("); + switch (e->type) { + case E_SYMBOL: + if (e->left.sym->name) + fn(data, e->left.sym, e->left.sym->name); + else + fn(data, NULL, ""); + break; + case E_NOT: + fn(data, NULL, "!"); + expr_print(e->left.expr, fn, data, E_NOT); + break; + case E_EQUAL: + if (e->left.sym->name) + fn(data, e->left.sym, e->left.sym->name); + else + fn(data, NULL, ""); + fn(data, NULL, "="); + fn(data, e->right.sym, e->right.sym->name); + break; + case E_UNEQUAL: + if (e->left.sym->name) + fn(data, e->left.sym, e->left.sym->name); + else + fn(data, NULL, ""); + fn(data, NULL, "!="); + fn(data, e->right.sym, e->right.sym->name); + break; + case E_OR: + expr_print(e->left.expr, fn, data, E_OR); + fn(data, NULL, " || "); + expr_print(e->right.expr, fn, data, E_OR); + break; + case E_AND: + expr_print(e->left.expr, fn, data, E_AND); + fn(data, NULL, " && "); + expr_print(e->right.expr, fn, data, E_AND); + break; + case E_LIST: + fn(data, e->right.sym, e->right.sym->name); + if (e->left.expr) { + fn(data, NULL, " ^ "); + expr_print(e->left.expr, fn, data, E_LIST); + } + break; + case E_RANGE: + fn(data, NULL, "["); + fn(data, e->left.sym, e->left.sym->name); + fn(data, NULL, " "); + fn(data, e->right.sym, e->right.sym->name); + fn(data, NULL, "]"); + break; + default: + { + char buf[32]; + sprintf(buf, "", e->type); + fn(data, NULL, buf); + break; + } + } + if (expr_compare_type(prevtoken, e->type) > 0) + fn(data, NULL, ")"); +} + +static void expr_print_file_helper(void *data, struct symbol *sym, const char *str) +{ + xfwrite(str, strlen(str), 1, data); +} + +void expr_fprint(struct expr *e, FILE *out) +{ + expr_print(e, expr_print_file_helper, out, E_NONE); +} + +static void expr_print_gstr_helper(void *data, struct symbol *sym, const char *str) +{ + struct gstr *gs = (struct gstr*)data; + const char *sym_str = NULL; + + if (sym) + sym_str = sym_get_string_value(sym); + + if (gs->max_width) { + unsigned extra_length = strlen(str); + const char *last_cr = strrchr(gs->s, '\n'); + unsigned last_line_length; + + if (sym_str) + extra_length += 4 + strlen(sym_str); + + if (!last_cr) + last_cr = gs->s; + + last_line_length = strlen(gs->s) - (last_cr - gs->s); + + if ((last_line_length + extra_length) > gs->max_width) + str_append(gs, "\\\n"); + } + + str_append(gs, str); + if (sym && sym->type != S_UNKNOWN) + str_printf(gs, " [=%s]", sym_str); +} + +void expr_gstr_print(struct expr *e, struct gstr *gs) +{ + expr_print(e, expr_print_gstr_helper, gs, E_NONE); +} diff --git a/scripts/kconfig/expr.h b/scripts/kconfig/expr.h new file mode 100644 index 0000000000..412ea8a2ab --- /dev/null +++ b/scripts/kconfig/expr.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#ifndef EXPR_H +#define EXPR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "list.h" +#ifndef __cplusplus +#include +#endif + +struct file { + struct file *next; + struct file *parent; + const char *name; + int lineno; +}; + +typedef enum tristate { + no, mod, yes +} tristate; + +enum expr_type { + E_NONE, E_OR, E_AND, E_NOT, E_EQUAL, E_UNEQUAL, E_LIST, E_SYMBOL, E_RANGE +}; + +union expr_data { + struct expr *expr; + struct symbol *sym; +}; + +struct expr { + enum expr_type type; + union expr_data left, right; +}; + +#define EXPR_OR(dep1, dep2) (((dep1)>(dep2))?(dep1):(dep2)) +#define EXPR_AND(dep1, dep2) (((dep1)<(dep2))?(dep1):(dep2)) +#define EXPR_NOT(dep) (2-(dep)) + +#define expr_list_for_each_sym(l, e, s) \ + for (e = (l); e && (s = e->right.sym); e = e->left.expr) + +struct expr_value { + struct expr *expr; + tristate tri; +}; + +struct symbol_value { + void *val; + tristate tri; +}; + +enum symbol_type { + S_UNKNOWN, S_BOOLEAN, S_TRISTATE, S_INT, S_HEX, S_STRING, S_OTHER +}; + +/* enum values are used as index to symbol.def[] */ +enum { + S_DEF_USER, /* main user value */ + S_DEF_AUTO, /* values read from auto.conf */ + S_DEF_DEF3, /* Reserved for UI usage */ + S_DEF_DEF4, /* Reserved for UI usage */ + S_DEF_COUNT +}; + +struct symbol { + struct symbol *next; + char *name; + enum symbol_type type; + struct symbol_value curr; + struct symbol_value def[S_DEF_COUNT]; + tristate visible; + int flags; + struct property *prop; + struct expr_value dir_dep; + struct expr_value rev_dep; +}; + +#define for_all_symbols(i, sym) for (i = 0; i < SYMBOL_HASHSIZE; i++) for (sym = symbol_hash[i]; sym; sym = sym->next) if (sym->type != S_OTHER) + +#define SYMBOL_CONST 0x0001 /* symbol is const */ +#define SYMBOL_CHECK 0x0008 /* used during dependency checking */ +#define SYMBOL_CHOICE 0x0010 /* start of a choice block (null name) */ +#define SYMBOL_CHOICEVAL 0x0020 /* used as a value in a choice block */ +#define SYMBOL_VALID 0x0080 /* set when symbol.curr is calculated */ +#define SYMBOL_OPTIONAL 0x0100 /* choice is optional - values can be 'n' */ +#define SYMBOL_WRITE 0x0200 /* write symbol to file (KCONFIG_CONFIG) */ +#define SYMBOL_CHANGED 0x0400 /* ? */ +#define SYMBOL_AUTO 0x1000 /* value from environment variable */ +#define SYMBOL_CHECKED 0x2000 /* used during dependency checking */ +#define SYMBOL_WARNED 0x8000 /* warning has been issued */ + +/* Set when symbol.def[] is used */ +#define SYMBOL_DEF 0x10000 /* First bit of SYMBOL_DEF */ +#define SYMBOL_DEF_USER 0x10000 /* symbol.def[S_DEF_USER] is valid */ +#define SYMBOL_DEF_AUTO 0x20000 /* symbol.def[S_DEF_AUTO] is valid */ +#define SYMBOL_DEF3 0x40000 /* symbol.def[S_DEF_3] is valid */ +#define SYMBOL_DEF4 0x80000 /* symbol.def[S_DEF_4] is valid */ + +/* choice values need to be set before calculating this symbol value */ +#define SYMBOL_NEED_SET_CHOICE_VALUES 0x100000 + +/* Set symbol to y if allnoconfig; used for symbols that hide others */ +#define SYMBOL_ALLNOCONFIG_Y 0x200000 + +#define SYMBOL_MAXLENGTH 256 +#define SYMBOL_HASHSIZE 9973 + +/* A property represent the config options that can be associated + * with a config "symbol". + * Sample: + * config FOO + * default y + * prompt "foo prompt" + * select BAR + * config BAZ + * int "BAZ Value" + * range 1..255 + */ +enum prop_type { + P_UNKNOWN, + P_PROMPT, /* prompt "foo prompt" or "BAZ Value" */ + P_COMMENT, /* text associated with a comment */ + P_MENU, /* prompt associated with a menuconfig option */ + P_DEFAULT, /* default y */ + P_CHOICE, /* choice value */ + P_SELECT, /* select BAR */ + P_RANGE, /* range 7..100 (for a symbol) */ + P_ENV, /* value from environment variable */ + P_SYMBOL, /* where a symbol is defined */ +}; + +struct property { + struct property *next; /* next property - null if last */ + struct symbol *sym; /* the symbol for which the property is associated */ + enum prop_type type; /* type of property */ + const char *text; /* the prompt value - P_PROMPT, P_MENU, P_COMMENT */ + struct expr_value visible; + struct expr *expr; /* the optional conditional part of the property */ + struct menu *menu; /* the menu the property are associated with + * valid for: P_SELECT, P_RANGE, P_CHOICE, + * P_PROMPT, P_DEFAULT, P_MENU, P_COMMENT */ + struct file *file; /* what file was this property defined */ + int lineno; /* what lineno was this property defined */ +}; + +#define for_all_properties(sym, st, tok) \ + for (st = sym->prop; st; st = st->next) \ + if (st->type == (tok)) +#define for_all_defaults(sym, st) for_all_properties(sym, st, P_DEFAULT) +#define for_all_choices(sym, st) for_all_properties(sym, st, P_CHOICE) +#define for_all_prompts(sym, st) \ + for (st = sym->prop; st; st = st->next) \ + if (st->text) + +struct menu { + struct menu *next; + struct menu *parent; + struct menu *list; + struct symbol *sym; + struct property *prompt; + struct expr *visibility; + struct expr *dep; + unsigned int flags; + char *help; + struct file *file; + int lineno; + void *data; +}; + +#define MENU_CHANGED 0x0001 +#define MENU_ROOT 0x0002 + +struct jump_key { + struct list_head entries; + size_t offset; + struct menu *target; + int index; +}; + +#define JUMP_NB 9 + +extern struct file *file_list; +extern struct file *current_file; +struct file *lookup_file(const char *name); + +extern struct symbol symbol_yes, symbol_no, symbol_mod; +extern struct symbol *modules_sym; +extern struct symbol *sym_defconfig_list; +extern int cdebug; +struct expr *expr_alloc_symbol(struct symbol *sym); +struct expr *expr_alloc_one(enum expr_type type, struct expr *ce); +struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2); +struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2); +struct expr *expr_alloc_and(struct expr *e1, struct expr *e2); +struct expr *expr_alloc_or(struct expr *e1, struct expr *e2); +struct expr *expr_copy(const struct expr *org); +void expr_free(struct expr *e); +int expr_eq(struct expr *e1, struct expr *e2); +void expr_eliminate_eq(struct expr **ep1, struct expr **ep2); +tristate expr_calc_value(struct expr *e); +struct expr *expr_eliminate_yn(struct expr *e); +struct expr *expr_trans_bool(struct expr *e); +struct expr *expr_eliminate_dups(struct expr *e); +struct expr *expr_transform(struct expr *e); +int expr_contains_symbol(struct expr *dep, struct symbol *sym); +bool expr_depends_symbol(struct expr *dep, struct symbol *sym); +struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2); +struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2); +void expr_extract_eq(enum expr_type type, struct expr **ep, struct expr **ep1, struct expr **ep2); +struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym); +struct expr *expr_simplify_unmet_dep(struct expr *e1, struct expr *e2); + +void expr_fprint(struct expr *e, FILE *out); +struct gstr; /* forward */ +void expr_gstr_print(struct expr *e, struct gstr *gs); + +static inline int expr_is_yes(struct expr *e) +{ + return !e || (e->type == E_SYMBOL && e->left.sym == &symbol_yes); +} + +static inline int expr_is_no(struct expr *e) +{ + return e && (e->type == E_SYMBOL && e->left.sym == &symbol_no); +} + +#ifdef __cplusplus +} +#endif + +#endif /* EXPR_H */ diff --git a/scripts/kconfig/gconf.c b/scripts/kconfig/gconf.c new file mode 100644 index 0000000000..d0a35b21f3 --- /dev/null +++ b/scripts/kconfig/gconf.c @@ -0,0 +1,1542 @@ +/* Hey EMACS -*- linux-c -*- */ +/* + * + * Copyright (C) 2002-2003 Romain Lievin + * Released under the terms of the GNU GPL v2.0. + * + */ + +#ifdef HAVE_CONFIG_H +# include +#endif + +#include +#include "lkc.h" +#include "images.c" + +#include +#include +#include +#include + +#include +#include +#include +#include + +//#define DEBUG + +enum { + SINGLE_VIEW, SPLIT_VIEW, FULL_VIEW +}; + +enum { + OPT_NORMAL, OPT_ALL, OPT_PROMPT +}; + +static gint view_mode = FULL_VIEW; +static gboolean show_name = TRUE; +static gboolean show_range = TRUE; +static gboolean show_value = TRUE; +static gboolean resizeable = FALSE; +static int opt_mode = OPT_NORMAL; + +GtkWidget *main_wnd = NULL; +GtkWidget *tree1_w = NULL; // left frame +GtkWidget *tree2_w = NULL; // right frame +GtkWidget *text_w = NULL; +GtkWidget *hpaned = NULL; +GtkWidget *vpaned = NULL; +GtkWidget *back_btn = NULL; +GtkWidget *save_btn = NULL; +GtkWidget *save_menu_item = NULL; + +GtkTextTag *tag1, *tag2; +GdkColor color; + +GtkTreeStore *tree1, *tree2, *tree; +GtkTreeModel *model1, *model2; +static GtkTreeIter *parents[256]; +static gint indent; + +static struct menu *current; // current node for SINGLE view +static struct menu *browsed; // browsed node for SPLIT view + +enum { + COL_OPTION, COL_NAME, COL_NO, COL_MOD, COL_YES, COL_VALUE, + COL_MENU, COL_COLOR, COL_EDIT, COL_PIXBUF, + COL_PIXVIS, COL_BTNVIS, COL_BTNACT, COL_BTNINC, COL_BTNRAD, + COL_NUMBER +}; + +static void display_list(void); +static void display_tree(struct menu *menu); +static void display_tree_part(void); +static void update_tree(struct menu *src, GtkTreeIter * dst); +static void set_node(GtkTreeIter * node, struct menu *menu, gchar ** row); +static gchar **fill_row(struct menu *menu); +static void conf_changed(void); + +/* Helping/Debugging Functions */ + +const char *dbg_sym_flags(int val) +{ + static char buf[256]; + + bzero(buf, 256); + + if (val & SYMBOL_CONST) + strcat(buf, "const/"); + if (val & SYMBOL_CHECK) + strcat(buf, "check/"); + if (val & SYMBOL_CHOICE) + strcat(buf, "choice/"); + if (val & SYMBOL_CHOICEVAL) + strcat(buf, "choiceval/"); + if (val & SYMBOL_VALID) + strcat(buf, "valid/"); + if (val & SYMBOL_OPTIONAL) + strcat(buf, "optional/"); + if (val & SYMBOL_WRITE) + strcat(buf, "write/"); + if (val & SYMBOL_CHANGED) + strcat(buf, "changed/"); + if (val & SYMBOL_AUTO) + strcat(buf, "auto/"); + + buf[strlen(buf) - 1] = '\0'; + + return buf; +} + +void replace_button_icon(GladeXML * xml, GdkDrawable * window, + GtkStyle * style, gchar * btn_name, gchar ** xpm) +{ + GdkPixmap *pixmap; + GdkBitmap *mask; + GtkToolButton *button; + GtkWidget *image; + + pixmap = gdk_pixmap_create_from_xpm_d(window, &mask, + &style->bg[GTK_STATE_NORMAL], + xpm); + + button = GTK_TOOL_BUTTON(glade_xml_get_widget(xml, btn_name)); + image = gtk_image_new_from_pixmap(pixmap, mask); + gtk_widget_show(image); + gtk_tool_button_set_icon_widget(button, image); +} + +/* Main Window Initialization */ +void init_main_window(const gchar * glade_file) +{ + GladeXML *xml; + GtkWidget *widget; + GtkTextBuffer *txtbuf; + GtkStyle *style; + + xml = glade_xml_new(glade_file, "window1", NULL); + if (!xml) + g_error(_("GUI loading failed !\n")); + glade_xml_signal_autoconnect(xml); + + main_wnd = glade_xml_get_widget(xml, "window1"); + hpaned = glade_xml_get_widget(xml, "hpaned1"); + vpaned = glade_xml_get_widget(xml, "vpaned1"); + tree1_w = glade_xml_get_widget(xml, "treeview1"); + tree2_w = glade_xml_get_widget(xml, "treeview2"); + text_w = glade_xml_get_widget(xml, "textview3"); + + back_btn = glade_xml_get_widget(xml, "button1"); + gtk_widget_set_sensitive(back_btn, FALSE); + + widget = glade_xml_get_widget(xml, "show_name1"); + gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget, + show_name); + + widget = glade_xml_get_widget(xml, "show_range1"); + gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget, + show_range); + + widget = glade_xml_get_widget(xml, "show_data1"); + gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget, + show_value); + + save_btn = glade_xml_get_widget(xml, "button3"); + save_menu_item = glade_xml_get_widget(xml, "save1"); + conf_set_changed_callback(conf_changed); + + style = gtk_widget_get_style(main_wnd); + widget = glade_xml_get_widget(xml, "toolbar1"); + +#if 0 /* Use stock Gtk icons instead */ + replace_button_icon(xml, main_wnd->window, style, + "button1", (gchar **) xpm_back); + replace_button_icon(xml, main_wnd->window, style, + "button2", (gchar **) xpm_load); + replace_button_icon(xml, main_wnd->window, style, + "button3", (gchar **) xpm_save); +#endif + replace_button_icon(xml, main_wnd->window, style, + "button4", (gchar **) xpm_single_view); + replace_button_icon(xml, main_wnd->window, style, + "button5", (gchar **) xpm_split_view); + replace_button_icon(xml, main_wnd->window, style, + "button6", (gchar **) xpm_tree_view); + +#if 0 + switch (view_mode) { + case SINGLE_VIEW: + widget = glade_xml_get_widget(xml, "button4"); + g_signal_emit_by_name(widget, "clicked"); + break; + case SPLIT_VIEW: + widget = glade_xml_get_widget(xml, "button5"); + g_signal_emit_by_name(widget, "clicked"); + break; + case FULL_VIEW: + widget = glade_xml_get_widget(xml, "button6"); + g_signal_emit_by_name(widget, "clicked"); + break; + } +#endif + txtbuf = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w)); + tag1 = gtk_text_buffer_create_tag(txtbuf, "mytag1", + "foreground", "red", + "weight", PANGO_WEIGHT_BOLD, + NULL); + tag2 = gtk_text_buffer_create_tag(txtbuf, "mytag2", + /*"style", PANGO_STYLE_OBLIQUE, */ + NULL); + + gtk_window_set_title(GTK_WINDOW(main_wnd), rootmenu.prompt->text); + + gtk_widget_show(main_wnd); +} + +void init_tree_model(void) +{ + gint i; + + tree = tree2 = gtk_tree_store_new(COL_NUMBER, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_POINTER, GDK_TYPE_COLOR, + G_TYPE_BOOLEAN, GDK_TYPE_PIXBUF, + G_TYPE_BOOLEAN, G_TYPE_BOOLEAN, + G_TYPE_BOOLEAN, G_TYPE_BOOLEAN, + G_TYPE_BOOLEAN); + model2 = GTK_TREE_MODEL(tree2); + + for (parents[0] = NULL, i = 1; i < 256; i++) + parents[i] = (GtkTreeIter *) g_malloc(sizeof(GtkTreeIter)); + + tree1 = gtk_tree_store_new(COL_NUMBER, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_POINTER, GDK_TYPE_COLOR, + G_TYPE_BOOLEAN, GDK_TYPE_PIXBUF, + G_TYPE_BOOLEAN, G_TYPE_BOOLEAN, + G_TYPE_BOOLEAN, G_TYPE_BOOLEAN, + G_TYPE_BOOLEAN); + model1 = GTK_TREE_MODEL(tree1); +} + +void init_left_tree(void) +{ + GtkTreeView *view = GTK_TREE_VIEW(tree1_w); + GtkCellRenderer *renderer; + GtkTreeSelection *sel; + GtkTreeViewColumn *column; + + gtk_tree_view_set_model(view, model1); + gtk_tree_view_set_headers_visible(view, TRUE); + gtk_tree_view_set_rules_hint(view, TRUE); + + column = gtk_tree_view_column_new(); + gtk_tree_view_append_column(view, column); + gtk_tree_view_column_set_title(column, _("Options")); + + renderer = gtk_cell_renderer_toggle_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "active", COL_BTNACT, + "inconsistent", COL_BTNINC, + "visible", COL_BTNVIS, + "radio", COL_BTNRAD, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "text", COL_OPTION, + "foreground-gdk", + COL_COLOR, NULL); + + sel = gtk_tree_view_get_selection(view); + gtk_tree_selection_set_mode(sel, GTK_SELECTION_SINGLE); + gtk_widget_realize(tree1_w); +} + +static void renderer_edited(GtkCellRendererText * cell, + const gchar * path_string, + const gchar * new_text, gpointer user_data); + +void init_right_tree(void) +{ + GtkTreeView *view = GTK_TREE_VIEW(tree2_w); + GtkCellRenderer *renderer; + GtkTreeSelection *sel; + GtkTreeViewColumn *column; + gint i; + + gtk_tree_view_set_model(view, model2); + gtk_tree_view_set_headers_visible(view, TRUE); + gtk_tree_view_set_rules_hint(view, TRUE); + + column = gtk_tree_view_column_new(); + gtk_tree_view_append_column(view, column); + gtk_tree_view_column_set_title(column, _("Options")); + + renderer = gtk_cell_renderer_pixbuf_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "pixbuf", COL_PIXBUF, + "visible", COL_PIXVIS, NULL); + renderer = gtk_cell_renderer_toggle_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "active", COL_BTNACT, + "inconsistent", COL_BTNINC, + "visible", COL_BTNVIS, + "radio", COL_BTNRAD, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "text", COL_OPTION, + "foreground-gdk", + COL_COLOR, NULL); + + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + _("Name"), renderer, + "text", COL_NAME, + "foreground-gdk", + COL_COLOR, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + "N", renderer, + "text", COL_NO, + "foreground-gdk", + COL_COLOR, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + "M", renderer, + "text", COL_MOD, + "foreground-gdk", + COL_COLOR, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + "Y", renderer, + "text", COL_YES, + "foreground-gdk", + COL_COLOR, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + _("Value"), renderer, + "text", COL_VALUE, + "editable", + COL_EDIT, + "foreground-gdk", + COL_COLOR, NULL); + g_signal_connect(G_OBJECT(renderer), "edited", + G_CALLBACK(renderer_edited), NULL); + + column = gtk_tree_view_get_column(view, COL_NAME); + gtk_tree_view_column_set_visible(column, show_name); + column = gtk_tree_view_get_column(view, COL_NO); + gtk_tree_view_column_set_visible(column, show_range); + column = gtk_tree_view_get_column(view, COL_MOD); + gtk_tree_view_column_set_visible(column, show_range); + column = gtk_tree_view_get_column(view, COL_YES); + gtk_tree_view_column_set_visible(column, show_range); + column = gtk_tree_view_get_column(view, COL_VALUE); + gtk_tree_view_column_set_visible(column, show_value); + + if (resizeable) { + for (i = 0; i < COL_VALUE; i++) { + column = gtk_tree_view_get_column(view, i); + gtk_tree_view_column_set_resizable(column, TRUE); + } + } + + sel = gtk_tree_view_get_selection(view); + gtk_tree_selection_set_mode(sel, GTK_SELECTION_SINGLE); +} + + +/* Utility Functions */ + + +static void text_insert_help(struct menu *menu) +{ + GtkTextBuffer *buffer; + GtkTextIter start, end; + const char *prompt = _(menu_get_prompt(menu)); + struct gstr help = str_new(); + + menu_get_ext_help(menu, &help); + + buffer = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w)); + gtk_text_buffer_get_bounds(buffer, &start, &end); + gtk_text_buffer_delete(buffer, &start, &end); + gtk_text_view_set_left_margin(GTK_TEXT_VIEW(text_w), 15); + + gtk_text_buffer_get_end_iter(buffer, &end); + gtk_text_buffer_insert_with_tags(buffer, &end, prompt, -1, tag1, + NULL); + gtk_text_buffer_insert_at_cursor(buffer, "\n\n", 2); + gtk_text_buffer_get_end_iter(buffer, &end); + gtk_text_buffer_insert_with_tags(buffer, &end, str_get(&help), -1, tag2, + NULL); + str_free(&help); +} + + +static void text_insert_msg(const char *title, const char *message) +{ + GtkTextBuffer *buffer; + GtkTextIter start, end; + const char *msg = message; + + buffer = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w)); + gtk_text_buffer_get_bounds(buffer, &start, &end); + gtk_text_buffer_delete(buffer, &start, &end); + gtk_text_view_set_left_margin(GTK_TEXT_VIEW(text_w), 15); + + gtk_text_buffer_get_end_iter(buffer, &end); + gtk_text_buffer_insert_with_tags(buffer, &end, title, -1, tag1, + NULL); + gtk_text_buffer_insert_at_cursor(buffer, "\n\n", 2); + gtk_text_buffer_get_end_iter(buffer, &end); + gtk_text_buffer_insert_with_tags(buffer, &end, msg, -1, tag2, + NULL); +} + + +/* Main Windows Callbacks */ + +void on_save_activate(GtkMenuItem * menuitem, gpointer user_data); +gboolean on_window1_delete_event(GtkWidget * widget, GdkEvent * event, + gpointer user_data) +{ + GtkWidget *dialog, *label; + gint result; + + if (!conf_get_changed()) + return FALSE; + + dialog = gtk_dialog_new_with_buttons(_("Warning !"), + GTK_WINDOW(main_wnd), + (GtkDialogFlags) + (GTK_DIALOG_MODAL | + GTK_DIALOG_DESTROY_WITH_PARENT), + GTK_STOCK_OK, + GTK_RESPONSE_YES, + GTK_STOCK_NO, + GTK_RESPONSE_NO, + GTK_STOCK_CANCEL, + GTK_RESPONSE_CANCEL, NULL); + gtk_dialog_set_default_response(GTK_DIALOG(dialog), + GTK_RESPONSE_CANCEL); + + label = gtk_label_new(_("\nSave configuration ?\n")); + gtk_container_add(GTK_CONTAINER(GTK_DIALOG(dialog)->vbox), label); + gtk_widget_show(label); + + result = gtk_dialog_run(GTK_DIALOG(dialog)); + switch (result) { + case GTK_RESPONSE_YES: + on_save_activate(NULL, NULL); + return FALSE; + case GTK_RESPONSE_NO: + return FALSE; + case GTK_RESPONSE_CANCEL: + case GTK_RESPONSE_DELETE_EVENT: + default: + gtk_widget_destroy(dialog); + return TRUE; + } + + return FALSE; +} + + +void on_window1_destroy(GtkObject * object, gpointer user_data) +{ + gtk_main_quit(); +} + + +void +on_window1_size_request(GtkWidget * widget, + GtkRequisition * requisition, gpointer user_data) +{ + static gint old_h; + gint w, h; + + if (widget->window == NULL) + gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h); + else + gdk_window_get_size(widget->window, &w, &h); + + if (h == old_h) + return; + old_h = h; + + gtk_paned_set_position(GTK_PANED(vpaned), 2 * h / 3); +} + + +/* Menu & Toolbar Callbacks */ + + +static void +load_filename(GtkFileSelection * file_selector, gpointer user_data) +{ + const gchar *fn; + + fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION + (user_data)); + + if (conf_read(fn)) + text_insert_msg(_("Error"), _("Unable to load configuration !")); + else + display_tree(&rootmenu); +} + +void on_load1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *fs; + + fs = gtk_file_selection_new(_("Load file...")); + g_signal_connect(GTK_OBJECT(GTK_FILE_SELECTION(fs)->ok_button), + "clicked", + G_CALLBACK(load_filename), (gpointer) fs); + g_signal_connect_swapped(GTK_OBJECT + (GTK_FILE_SELECTION(fs)->ok_button), + "clicked", G_CALLBACK(gtk_widget_destroy), + (gpointer) fs); + g_signal_connect_swapped(GTK_OBJECT + (GTK_FILE_SELECTION(fs)->cancel_button), + "clicked", G_CALLBACK(gtk_widget_destroy), + (gpointer) fs); + gtk_widget_show(fs); +} + + +void on_save_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + if (conf_write(NULL)) + text_insert_msg(_("Error"), _("Unable to save configuration !")); +} + + +static void +store_filename(GtkFileSelection * file_selector, gpointer user_data) +{ + const gchar *fn; + + fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION + (user_data)); + + if (conf_write(fn)) + text_insert_msg(_("Error"), _("Unable to save configuration !")); + + gtk_widget_destroy(GTK_WIDGET(user_data)); +} + +void on_save_as1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *fs; + + fs = gtk_file_selection_new(_("Save file as...")); + g_signal_connect(GTK_OBJECT(GTK_FILE_SELECTION(fs)->ok_button), + "clicked", + G_CALLBACK(store_filename), (gpointer) fs); + g_signal_connect_swapped(GTK_OBJECT + (GTK_FILE_SELECTION(fs)->ok_button), + "clicked", G_CALLBACK(gtk_widget_destroy), + (gpointer) fs); + g_signal_connect_swapped(GTK_OBJECT + (GTK_FILE_SELECTION(fs)->cancel_button), + "clicked", G_CALLBACK(gtk_widget_destroy), + (gpointer) fs); + gtk_widget_show(fs); +} + + +void on_quit1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + if (!on_window1_delete_event(NULL, NULL, NULL)) + gtk_widget_destroy(GTK_WIDGET(main_wnd)); +} + + +void on_show_name1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkTreeViewColumn *col; + + show_name = GTK_CHECK_MENU_ITEM(menuitem)->active; + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_NAME); + if (col) + gtk_tree_view_column_set_visible(col, show_name); +} + + +void on_show_range1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkTreeViewColumn *col; + + show_range = GTK_CHECK_MENU_ITEM(menuitem)->active; + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_NO); + if (col) + gtk_tree_view_column_set_visible(col, show_range); + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_MOD); + if (col) + gtk_tree_view_column_set_visible(col, show_range); + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_YES); + if (col) + gtk_tree_view_column_set_visible(col, show_range); + +} + + +void on_show_data1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkTreeViewColumn *col; + + show_value = GTK_CHECK_MENU_ITEM(menuitem)->active; + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_VALUE); + if (col) + gtk_tree_view_column_set_visible(col, show_value); +} + + +void +on_set_option_mode1_activate(GtkMenuItem *menuitem, gpointer user_data) +{ + opt_mode = OPT_NORMAL; + gtk_tree_store_clear(tree2); + display_tree(&rootmenu); /* instead of update_tree to speed-up */ +} + + +void +on_set_option_mode2_activate(GtkMenuItem *menuitem, gpointer user_data) +{ + opt_mode = OPT_ALL; + gtk_tree_store_clear(tree2); + display_tree(&rootmenu); /* instead of update_tree to speed-up */ +} + + +void +on_set_option_mode3_activate(GtkMenuItem *menuitem, gpointer user_data) +{ + opt_mode = OPT_PROMPT; + gtk_tree_store_clear(tree2); + display_tree(&rootmenu); /* instead of update_tree to speed-up */ +} + + +void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *dialog; + const gchar *intro_text = _( + "Welcome to gkc, the GTK+ graphical configuration tool\n" + "For each option, a blank box indicates the feature is disabled, a\n" + "check indicates it is enabled, and a dot indicates that it is to\n" + "be compiled as a module. Clicking on the box will cycle through the three states.\n" + "\n" + "If you do not see an option (e.g., a device driver) that you\n" + "believe should be present, try turning on Show All Options\n" + "under the Options menu.\n" + "Although there is no cross reference yet to help you figure out\n" + "what other options must be enabled to support the option you\n" + "are interested in, you can still view the help of a grayed-out\n" + "option.\n" + "\n" + "Toggling Show Debug Info under the Options menu will show \n" + "the dependencies, which you can then match by examining other options."); + + dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd), + GTK_DIALOG_DESTROY_WITH_PARENT, + GTK_MESSAGE_INFO, + GTK_BUTTONS_CLOSE, "%s", intro_text); + g_signal_connect_swapped(GTK_OBJECT(dialog), "response", + G_CALLBACK(gtk_widget_destroy), + GTK_OBJECT(dialog)); + gtk_widget_show_all(dialog); +} + + +void on_about1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *dialog; + const gchar *about_text = + _("gkc is copyright (c) 2002 Romain Lievin .\n" + "Based on the source code from Roman Zippel.\n"); + + dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd), + GTK_DIALOG_DESTROY_WITH_PARENT, + GTK_MESSAGE_INFO, + GTK_BUTTONS_CLOSE, "%s", about_text); + g_signal_connect_swapped(GTK_OBJECT(dialog), "response", + G_CALLBACK(gtk_widget_destroy), + GTK_OBJECT(dialog)); + gtk_widget_show_all(dialog); +} + + +void on_license1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *dialog; + const gchar *license_text = + _("gkc is released under the terms of the GNU GPL v2.\n" + "For more information, please see the source code or\n" + "visit http://www.fsf.org/licenses/licenses.html\n"); + + dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd), + GTK_DIALOG_DESTROY_WITH_PARENT, + GTK_MESSAGE_INFO, + GTK_BUTTONS_CLOSE, "%s", license_text); + g_signal_connect_swapped(GTK_OBJECT(dialog), "response", + G_CALLBACK(gtk_widget_destroy), + GTK_OBJECT(dialog)); + gtk_widget_show_all(dialog); +} + + +void on_back_clicked(GtkButton * button, gpointer user_data) +{ + enum prop_type ptype; + + current = current->parent; + ptype = current->prompt ? current->prompt->type : P_UNKNOWN; + if (ptype != P_MENU) + current = current->parent; + display_tree_part(); + + if (current == &rootmenu) + gtk_widget_set_sensitive(back_btn, FALSE); +} + + +void on_load_clicked(GtkButton * button, gpointer user_data) +{ + on_load1_activate(NULL, user_data); +} + + +void on_single_clicked(GtkButton * button, gpointer user_data) +{ + view_mode = SINGLE_VIEW; + gtk_widget_hide(tree1_w); + current = &rootmenu; + display_tree_part(); +} + + +void on_split_clicked(GtkButton * button, gpointer user_data) +{ + gint w, h; + view_mode = SPLIT_VIEW; + gtk_widget_show(tree1_w); + gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h); + gtk_paned_set_position(GTK_PANED(hpaned), w / 2); + if (tree2) + gtk_tree_store_clear(tree2); + display_list(); + + /* Disable back btn, like in full mode. */ + gtk_widget_set_sensitive(back_btn, FALSE); +} + + +void on_full_clicked(GtkButton * button, gpointer user_data) +{ + view_mode = FULL_VIEW; + gtk_widget_hide(tree1_w); + if (tree2) + gtk_tree_store_clear(tree2); + display_tree(&rootmenu); + gtk_widget_set_sensitive(back_btn, FALSE); +} + + +void on_collapse_clicked(GtkButton * button, gpointer user_data) +{ + gtk_tree_view_collapse_all(GTK_TREE_VIEW(tree2_w)); +} + + +void on_expand_clicked(GtkButton * button, gpointer user_data) +{ + gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w)); +} + + +/* CTree Callbacks */ + +/* Change hex/int/string value in the cell */ +static void renderer_edited(GtkCellRendererText * cell, + const gchar * path_string, + const gchar * new_text, gpointer user_data) +{ + GtkTreePath *path = gtk_tree_path_new_from_string(path_string); + GtkTreeIter iter; + const char *old_def, *new_def; + struct menu *menu; + struct symbol *sym; + + if (!gtk_tree_model_get_iter(model2, &iter, path)) + return; + + gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1); + sym = menu->sym; + + gtk_tree_model_get(model2, &iter, COL_VALUE, &old_def, -1); + new_def = new_text; + + sym_set_string_value(sym, new_def); + + update_tree(&rootmenu, NULL); + + gtk_tree_path_free(path); +} + +/* Change the value of a symbol and update the tree */ +static void change_sym_value(struct menu *menu, gint col) +{ + struct symbol *sym = menu->sym; + tristate newval; + + if (!sym) + return; + + if (col == COL_NO) + newval = no; + else if (col == COL_MOD) + newval = mod; + else if (col == COL_YES) + newval = yes; + else + return; + + switch (sym_get_type(sym)) { + case S_BOOLEAN: + case S_TRISTATE: + if (!sym_tristate_within_range(sym, newval)) + newval = yes; + sym_set_tristate_value(sym, newval); + if (view_mode == FULL_VIEW) + update_tree(&rootmenu, NULL); + else if (view_mode == SPLIT_VIEW) { + update_tree(browsed, NULL); + display_list(); + } + else if (view_mode == SINGLE_VIEW) + display_tree_part(); //fixme: keep exp/coll + break; + case S_INT: + case S_HEX: + case S_STRING: + default: + break; + } +} + +static void toggle_sym_value(struct menu *menu) +{ + if (!menu->sym) + return; + + sym_toggle_tristate_value(menu->sym); + if (view_mode == FULL_VIEW) + update_tree(&rootmenu, NULL); + else if (view_mode == SPLIT_VIEW) { + update_tree(browsed, NULL); + display_list(); + } + else if (view_mode == SINGLE_VIEW) + display_tree_part(); //fixme: keep exp/coll +} + +static gint column2index(GtkTreeViewColumn * column) +{ + gint i; + + for (i = 0; i < COL_NUMBER; i++) { + GtkTreeViewColumn *col; + + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), i); + if (col == column) + return i; + } + + return -1; +} + + +/* User click: update choice (full) or goes down (single) */ +gboolean +on_treeview2_button_press_event(GtkWidget * widget, + GdkEventButton * event, gpointer user_data) +{ + GtkTreeView *view = GTK_TREE_VIEW(widget); + GtkTreePath *path; + GtkTreeViewColumn *column; + GtkTreeIter iter; + struct menu *menu; + gint col; + +#if GTK_CHECK_VERSION(2,1,4) // bug in ctree with earlier version of GTK + gint tx = (gint) event->x; + gint ty = (gint) event->y; + gint cx, cy; + + gtk_tree_view_get_path_at_pos(view, tx, ty, &path, &column, &cx, + &cy); +#else + gtk_tree_view_get_cursor(view, &path, &column); +#endif + if (path == NULL) + return FALSE; + + if (!gtk_tree_model_get_iter(model2, &iter, path)) + return FALSE; + gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1); + + col = column2index(column); + if (event->type == GDK_2BUTTON_PRESS) { + enum prop_type ptype; + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + + if (ptype == P_MENU && view_mode != FULL_VIEW && col == COL_OPTION) { + // goes down into menu + current = menu; + display_tree_part(); + gtk_widget_set_sensitive(back_btn, TRUE); + } else if ((col == COL_OPTION)) { + toggle_sym_value(menu); + gtk_tree_view_expand_row(view, path, TRUE); + } + } else { + if (col == COL_VALUE) { + toggle_sym_value(menu); + gtk_tree_view_expand_row(view, path, TRUE); + } else if (col == COL_NO || col == COL_MOD + || col == COL_YES) { + change_sym_value(menu, col); + gtk_tree_view_expand_row(view, path, TRUE); + } + } + + return FALSE; +} + +/* Key pressed: update choice */ +gboolean +on_treeview2_key_press_event(GtkWidget * widget, + GdkEventKey * event, gpointer user_data) +{ + GtkTreeView *view = GTK_TREE_VIEW(widget); + GtkTreePath *path; + GtkTreeViewColumn *column; + GtkTreeIter iter; + struct menu *menu; + gint col; + + gtk_tree_view_get_cursor(view, &path, &column); + if (path == NULL) + return FALSE; + + if (event->keyval == GDK_space) { + if (gtk_tree_view_row_expanded(view, path)) + gtk_tree_view_collapse_row(view, path); + else + gtk_tree_view_expand_row(view, path, FALSE); + return TRUE; + } + if (event->keyval == GDK_KP_Enter) { + } + if (widget == tree1_w) + return FALSE; + + gtk_tree_model_get_iter(model2, &iter, path); + gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1); + + if (!strcasecmp(event->string, "n")) + col = COL_NO; + else if (!strcasecmp(event->string, "m")) + col = COL_MOD; + else if (!strcasecmp(event->string, "y")) + col = COL_YES; + else + col = -1; + change_sym_value(menu, col); + + return FALSE; +} + + +/* Row selection changed: update help */ +void +on_treeview2_cursor_changed(GtkTreeView * treeview, gpointer user_data) +{ + GtkTreeSelection *selection; + GtkTreeIter iter; + struct menu *menu; + + selection = gtk_tree_view_get_selection(treeview); + if (gtk_tree_selection_get_selected(selection, &model2, &iter)) { + gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1); + text_insert_help(menu); + } +} + + +/* User click: display sub-tree in the right frame. */ +gboolean +on_treeview1_button_press_event(GtkWidget * widget, + GdkEventButton * event, gpointer user_data) +{ + GtkTreeView *view = GTK_TREE_VIEW(widget); + GtkTreePath *path; + GtkTreeViewColumn *column; + GtkTreeIter iter; + struct menu *menu; + + gint tx = (gint) event->x; + gint ty = (gint) event->y; + gint cx, cy; + + gtk_tree_view_get_path_at_pos(view, tx, ty, &path, &column, &cx, + &cy); + if (path == NULL) + return FALSE; + + gtk_tree_model_get_iter(model1, &iter, path); + gtk_tree_model_get(model1, &iter, COL_MENU, &menu, -1); + + if (event->type == GDK_2BUTTON_PRESS) { + toggle_sym_value(menu); + current = menu; + display_tree_part(); + } else { + browsed = menu; + display_tree_part(); + } + + gtk_widget_realize(tree2_w); + gtk_tree_view_set_cursor(view, path, NULL, FALSE); + gtk_widget_grab_focus(tree2_w); + + return FALSE; +} + + +/* Fill a row of strings */ +static gchar **fill_row(struct menu *menu) +{ + static gchar *row[COL_NUMBER]; + struct symbol *sym = menu->sym; + const char *def; + int stype; + tristate val; + enum prop_type ptype; + int i; + + for (i = COL_OPTION; i <= COL_COLOR; i++) + g_free(row[i]); + bzero(row, sizeof(row)); + + row[COL_OPTION] = + g_strdup_printf("%s %s", _(menu_get_prompt(menu)), + sym && !sym_has_value(sym) ? "(NEW)" : ""); + + if (opt_mode == OPT_ALL && !menu_is_visible(menu)) + row[COL_COLOR] = g_strdup("DarkGray"); + else if (opt_mode == OPT_PROMPT && + menu_has_prompt(menu) && !menu_is_visible(menu)) + row[COL_COLOR] = g_strdup("DarkGray"); + else + row[COL_COLOR] = g_strdup("Black"); + + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + switch (ptype) { + case P_MENU: + row[COL_PIXBUF] = (gchar *) xpm_menu; + if (view_mode == SINGLE_VIEW) + row[COL_PIXVIS] = GINT_TO_POINTER(TRUE); + row[COL_BTNVIS] = GINT_TO_POINTER(FALSE); + break; + case P_COMMENT: + row[COL_PIXBUF] = (gchar *) xpm_void; + row[COL_PIXVIS] = GINT_TO_POINTER(FALSE); + row[COL_BTNVIS] = GINT_TO_POINTER(FALSE); + break; + default: + row[COL_PIXBUF] = (gchar *) xpm_void; + row[COL_PIXVIS] = GINT_TO_POINTER(FALSE); + row[COL_BTNVIS] = GINT_TO_POINTER(TRUE); + break; + } + + if (!sym) + return row; + row[COL_NAME] = g_strdup(sym->name); + + sym_calc_value(sym); + sym->flags &= ~SYMBOL_CHANGED; + + if (sym_is_choice(sym)) { // parse childs for getting final value + struct menu *child; + struct symbol *def_sym = sym_get_choice_value(sym); + struct menu *def_menu = NULL; + + row[COL_BTNVIS] = GINT_TO_POINTER(FALSE); + + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child) + && child->sym == def_sym) + def_menu = child; + } + + if (def_menu) + row[COL_VALUE] = + g_strdup(_(menu_get_prompt(def_menu))); + } + if (sym->flags & SYMBOL_CHOICEVAL) + row[COL_BTNRAD] = GINT_TO_POINTER(TRUE); + + stype = sym_get_type(sym); + switch (stype) { + case S_BOOLEAN: + if (GPOINTER_TO_INT(row[COL_PIXVIS]) == FALSE) + row[COL_BTNVIS] = GINT_TO_POINTER(TRUE); + if (sym_is_choice(sym)) + break; + /* fall through */ + case S_TRISTATE: + val = sym_get_tristate_value(sym); + switch (val) { + case no: + row[COL_NO] = g_strdup("N"); + row[COL_VALUE] = g_strdup("N"); + row[COL_BTNACT] = GINT_TO_POINTER(FALSE); + row[COL_BTNINC] = GINT_TO_POINTER(FALSE); + break; + case mod: + row[COL_MOD] = g_strdup("M"); + row[COL_VALUE] = g_strdup("M"); + row[COL_BTNINC] = GINT_TO_POINTER(TRUE); + break; + case yes: + row[COL_YES] = g_strdup("Y"); + row[COL_VALUE] = g_strdup("Y"); + row[COL_BTNACT] = GINT_TO_POINTER(TRUE); + row[COL_BTNINC] = GINT_TO_POINTER(FALSE); + break; + } + + if (val != no && sym_tristate_within_range(sym, no)) + row[COL_NO] = g_strdup("_"); + if (val != mod && sym_tristate_within_range(sym, mod)) + row[COL_MOD] = g_strdup("_"); + if (val != yes && sym_tristate_within_range(sym, yes)) + row[COL_YES] = g_strdup("_"); + break; + case S_INT: + case S_HEX: + case S_STRING: + def = sym_get_string_value(sym); + row[COL_VALUE] = g_strdup(def); + row[COL_EDIT] = GINT_TO_POINTER(TRUE); + row[COL_BTNVIS] = GINT_TO_POINTER(FALSE); + break; + } + + return row; +} + + +/* Set the node content with a row of strings */ +static void set_node(GtkTreeIter * node, struct menu *menu, gchar ** row) +{ + GdkColor color; + gboolean success; + GdkPixbuf *pix; + + pix = gdk_pixbuf_new_from_xpm_data((const char **) + row[COL_PIXBUF]); + + gdk_color_parse(row[COL_COLOR], &color); + gdk_colormap_alloc_colors(gdk_colormap_get_system(), &color, 1, + FALSE, FALSE, &success); + + gtk_tree_store_set(tree, node, + COL_OPTION, row[COL_OPTION], + COL_NAME, row[COL_NAME], + COL_NO, row[COL_NO], + COL_MOD, row[COL_MOD], + COL_YES, row[COL_YES], + COL_VALUE, row[COL_VALUE], + COL_MENU, (gpointer) menu, + COL_COLOR, &color, + COL_EDIT, GPOINTER_TO_INT(row[COL_EDIT]), + COL_PIXBUF, pix, + COL_PIXVIS, GPOINTER_TO_INT(row[COL_PIXVIS]), + COL_BTNVIS, GPOINTER_TO_INT(row[COL_BTNVIS]), + COL_BTNACT, GPOINTER_TO_INT(row[COL_BTNACT]), + COL_BTNINC, GPOINTER_TO_INT(row[COL_BTNINC]), + COL_BTNRAD, GPOINTER_TO_INT(row[COL_BTNRAD]), + -1); + + g_object_unref(pix); +} + + +/* Add a node to the tree */ +static void place_node(struct menu *menu, char **row) +{ + GtkTreeIter *parent = parents[indent - 1]; + GtkTreeIter *node = parents[indent]; + + gtk_tree_store_append(tree, node, parent); + set_node(node, menu, row); +} + + +/* Find a node in the GTK+ tree */ +static GtkTreeIter found; + +/* + * Find a menu in the GtkTree starting at parent. + */ +GtkTreeIter *gtktree_iter_find_node(GtkTreeIter * parent, + struct menu *tofind) +{ + GtkTreeIter iter; + GtkTreeIter *child = &iter; + gboolean valid; + GtkTreeIter *ret; + + valid = gtk_tree_model_iter_children(model2, child, parent); + while (valid) { + struct menu *menu; + + gtk_tree_model_get(model2, child, 6, &menu, -1); + + if (menu == tofind) { + memcpy(&found, child, sizeof(GtkTreeIter)); + return &found; + } + + ret = gtktree_iter_find_node(child, tofind); + if (ret) + return ret; + + valid = gtk_tree_model_iter_next(model2, child); + } + + return NULL; +} + + +/* + * Update the tree by adding/removing entries + * Does not change other nodes + */ +static void update_tree(struct menu *src, GtkTreeIter * dst) +{ + struct menu *child1; + GtkTreeIter iter, tmp; + GtkTreeIter *child2 = &iter; + gboolean valid; + GtkTreeIter *sibling; + struct symbol *sym; + struct menu *menu1, *menu2; + + if (src == &rootmenu) + indent = 1; + + valid = gtk_tree_model_iter_children(model2, child2, dst); + for (child1 = src->list; child1; child1 = child1->next) { + + sym = child1->sym; + + reparse: + menu1 = child1; + if (valid) + gtk_tree_model_get(model2, child2, COL_MENU, + &menu2, -1); + else + menu2 = NULL; // force adding of a first child + +#ifdef DEBUG + printf("%*c%s | %s\n", indent, ' ', + menu1 ? menu_get_prompt(menu1) : "nil", + menu2 ? menu_get_prompt(menu2) : "nil"); +#endif + + if ((opt_mode == OPT_NORMAL && !menu_is_visible(child1)) || + (opt_mode == OPT_PROMPT && !menu_has_prompt(child1)) || + (opt_mode == OPT_ALL && !menu_get_prompt(child1))) { + + /* remove node */ + if (gtktree_iter_find_node(dst, menu1) != NULL) { + memcpy(&tmp, child2, sizeof(GtkTreeIter)); + valid = gtk_tree_model_iter_next(model2, + child2); + gtk_tree_store_remove(tree2, &tmp); + if (!valid) + return; /* next parent */ + else + goto reparse; /* next child */ + } else + continue; + } + + if (menu1 != menu2) { + if (gtktree_iter_find_node(dst, menu1) == NULL) { // add node + if (!valid && !menu2) + sibling = NULL; + else + sibling = child2; + gtk_tree_store_insert_before(tree2, + child2, + dst, sibling); + set_node(child2, menu1, fill_row(menu1)); + if (menu2 == NULL) + valid = TRUE; + } else { // remove node + memcpy(&tmp, child2, sizeof(GtkTreeIter)); + valid = gtk_tree_model_iter_next(model2, + child2); + gtk_tree_store_remove(tree2, &tmp); + if (!valid) + return; // next parent + else + goto reparse; // next child + } + } else if (sym && (sym->flags & SYMBOL_CHANGED)) { + set_node(child2, menu1, fill_row(menu1)); + } + + indent++; + update_tree(child1, child2); + indent--; + + valid = gtk_tree_model_iter_next(model2, child2); + } +} + + +/* Display the whole tree (single/split/full view) */ +static void display_tree(struct menu *menu) +{ + struct symbol *sym; + struct property *prop; + struct menu *child; + enum prop_type ptype; + + if (menu == &rootmenu) { + indent = 1; + current = &rootmenu; + } + + for (child = menu->list; child; child = child->next) { + prop = child->prompt; + sym = child->sym; + ptype = prop ? prop->type : P_UNKNOWN; + + if (sym) + sym->flags &= ~SYMBOL_CHANGED; + + if ((view_mode == SPLIT_VIEW) + && !(child->flags & MENU_ROOT) && (tree == tree1)) + continue; + + if ((view_mode == SPLIT_VIEW) && (child->flags & MENU_ROOT) + && (tree == tree2)) + continue; + + if ((opt_mode == OPT_NORMAL && menu_is_visible(child)) || + (opt_mode == OPT_PROMPT && menu_has_prompt(child)) || + (opt_mode == OPT_ALL && menu_get_prompt(child))) + place_node(child, fill_row(child)); +#ifdef DEBUG + printf("%*c%s: ", indent, ' ', menu_get_prompt(child)); + printf("%s", child->flags & MENU_ROOT ? "rootmenu | " : ""); + printf("%s", prop_get_type_name(ptype)); + printf(" | "); + if (sym) { + printf("%s", sym_type_name(sym->type)); + printf(" | "); + printf("%s", dbg_sym_flags(sym->flags)); + printf("\n"); + } else + printf("\n"); +#endif + if ((view_mode != FULL_VIEW) && (ptype == P_MENU) + && (tree == tree2)) + continue; +/* + if (((menu != &rootmenu) && !(menu->flags & MENU_ROOT)) + || (view_mode == FULL_VIEW) + || (view_mode == SPLIT_VIEW))*/ + + /* Change paned position if the view is not in 'split mode' */ + if (view_mode == SINGLE_VIEW || view_mode == FULL_VIEW) { + gtk_paned_set_position(GTK_PANED(hpaned), 0); + } + + if (((view_mode == SINGLE_VIEW) && (menu->flags & MENU_ROOT)) + || (view_mode == FULL_VIEW) + || (view_mode == SPLIT_VIEW)) { + indent++; + display_tree(child); + indent--; + } + } +} + +/* Display a part of the tree starting at current node (single/split view) */ +static void display_tree_part(void) +{ + if (tree2) + gtk_tree_store_clear(tree2); + if (view_mode == SINGLE_VIEW) + display_tree(current); + else if (view_mode == SPLIT_VIEW) + display_tree(browsed); + gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w)); +} + +/* Display the list in the left frame (split view) */ +static void display_list(void) +{ + if (tree1) + gtk_tree_store_clear(tree1); + + tree = tree1; + display_tree(&rootmenu); + gtk_tree_view_expand_all(GTK_TREE_VIEW(tree1_w)); + tree = tree2; +} + +void fixup_rootmenu(struct menu *menu) +{ + struct menu *child; + static int menu_cnt = 0; + + menu->flags |= MENU_ROOT; + for (child = menu->list; child; child = child->next) { + if (child->prompt && child->prompt->type == P_MENU) { + menu_cnt++; + fixup_rootmenu(child); + menu_cnt--; + } else if (!menu_cnt) + fixup_rootmenu(child); + } +} + + +/* Main */ +int main(int ac, char *av[]) +{ + const char *name; + char *env; + gchar *glade_file; + + bindtextdomain(PACKAGE, LOCALEDIR); + bind_textdomain_codeset(PACKAGE, "UTF-8"); + textdomain(PACKAGE); + + /* GTK stuffs */ + gtk_set_locale(); + gtk_init(&ac, &av); + glade_init(); + + //add_pixmap_directory (PACKAGE_DATA_DIR "/" PACKAGE "/pixmaps"); + //add_pixmap_directory (PACKAGE_SOURCE_DIR "/pixmaps"); + + /* Determine GUI path */ + env = getenv(SRCTREE); + if (env) + glade_file = g_strconcat(env, "/scripts/kconfig/gconf.glade", NULL); + else if (av[0][0] == '/') + glade_file = g_strconcat(av[0], ".glade", NULL); + else + glade_file = g_strconcat(g_get_current_dir(), "/", av[0], ".glade", NULL); + + /* Conf stuffs */ + if (ac > 1 && av[1][0] == '-') { + switch (av[1][1]) { + case 'a': + //showAll = 1; + break; + case 'h': + case '?': + printf("%s \n", av[0]); + exit(0); + } + name = av[2]; + } else + name = av[1]; + + conf_parse(name); + fixup_rootmenu(&rootmenu); + conf_read(NULL); + + /* Load the interface and connect signals */ + init_main_window(glade_file); + init_tree_model(); + init_left_tree(); + init_right_tree(); + + switch (view_mode) { + case SINGLE_VIEW: + display_tree_part(); + break; + case SPLIT_VIEW: + display_list(); + break; + case FULL_VIEW: + display_tree(&rootmenu); + break; + } + + gtk_main(); + + return 0; +} + +static void conf_changed(void) +{ + bool changed = conf_get_changed(); + gtk_widget_set_sensitive(save_btn, changed); + gtk_widget_set_sensitive(save_menu_item, changed); +} diff --git a/scripts/kconfig/gconf.glade b/scripts/kconfig/gconf.glade new file mode 100644 index 0000000000..aa483cb327 --- /dev/null +++ b/scripts/kconfig/gconf.glade @@ -0,0 +1,661 @@ + + + + + + True + Gtk Kernel Configurator + GTK_WINDOW_TOPLEVEL + GTK_WIN_POS_NONE + False + 640 + 480 + True + False + True + False + False + GDK_WINDOW_TYPE_HINT_NORMAL + GDK_GRAVITY_NORTH_WEST + + + + + + + True + False + 0 + + + + True + + + + True + _File + True + + + + + + + True + Load a config file + _Load + True + + + + + + True + gtk-open + 1 + 0.5 + 0.5 + 0 + 0 + + + + + + + + True + Save the config in .config + _Save + True + + + + + + True + gtk-save + 1 + 0.5 + 0.5 + 0 + 0 + + + + + + + + True + Save the config in a file + Save _as + True + + + + + True + gtk-save-as + 1 + 0.5 + 0.5 + 0 + 0 + + + + + + + + True + + + + + + True + _Quit + True + + + + + + True + gtk-quit + 1 + 0.5 + 0.5 + 0 + 0 + + + + + + + + + + + + True + _Options + True + + + + + + + True + Show name + Show _name + True + False + + + + + + + True + Show range (Y/M/N) + Show _range + True + False + + + + + + + True + Show value of the option + Show _data + True + False + + + + + + + True + + + + + + True + Show normal options + Show normal options + True + True + + + + + + + True + Show all options + Show all _options + True + False + set_option_mode1 + + + + + + + True + Show all options with prompts + Show all prompt options + True + False + set_option_mode1 + + + + + + + + + + + + True + _Help + True + + + + + + + True + _Introduction + True + + + + + + True + gtk-dialog-question + 1 + 0.5 + 0.5 + 0 + 0 + + + + + + + + True + _About + True + + + + + + True + gtk-properties + 1 + 0.5 + 0.5 + 0 + 0 + + + + + + + + True + _License + True + + + + + True + gtk-justify-fill + 1 + 0.5 + 0.5 + 0 + 0 + + + + + + + + + + + 0 + False + False + + + + + + True + GTK_SHADOW_OUT + GTK_POS_LEFT + GTK_POS_TOP + + + + True + GTK_ORIENTATION_HORIZONTAL + GTK_TOOLBAR_BOTH + True + True + + + + True + Goes up of one level (single view) + Back + True + gtk-undo + True + True + False + + + + False + True + + + + + + True + True + True + False + + + + True + + + + + False + False + + + + + + True + Load a config file + Load + True + gtk-open + True + True + False + + + + False + True + + + + + + True + Save a config file + Save + True + gtk-save + True + True + False + + + + False + True + + + + + + True + True + True + False + + + + True + + + + + False + False + + + + + + True + Single view + Single + True + gtk-missing-image + True + True + False + + + + False + True + + + + + + True + Split view + Split + True + gtk-missing-image + True + True + False + + + + False + True + + + + + + True + Full view + Full + True + gtk-missing-image + True + True + False + + + + False + True + + + + + + True + True + True + False + + + + True + + + + + False + False + + + + + + True + Collapse the whole tree in the right frame + Collapse + True + gtk-remove + True + True + False + + + + False + True + + + + + + True + Expand the whole tree in the right frame + Expand + True + gtk-add + True + True + False + + + + False + True + + + + + + + 0 + False + False + + + + + + 1 + True + True + 0 + + + + True + GTK_POLICY_AUTOMATIC + GTK_POLICY_AUTOMATIC + GTK_SHADOW_IN + GTK_CORNER_TOP_LEFT + + + + True + True + True + False + False + False + + + + + + + + True + False + + + + + + True + True + 0 + + + + True + GTK_POLICY_AUTOMATIC + GTK_POLICY_AUTOMATIC + GTK_SHADOW_IN + GTK_CORNER_TOP_LEFT + + + + True + True + True + True + False + False + False + + + + + + + + True + False + + + + + + True + GTK_POLICY_NEVER + GTK_POLICY_AUTOMATIC + GTK_SHADOW_IN + GTK_CORNER_TOP_LEFT + + + + True + True + False + False + True + GTK_JUSTIFY_LEFT + GTK_WRAP_WORD + True + 0 + 0 + 0 + 0 + 0 + 0 + Sorry, no help available for this option yet. + + + + + True + True + + + + + True + True + + + + + 0 + True + True + + + + + + + diff --git a/scripts/kconfig/images.c b/scripts/kconfig/images.c new file mode 100644 index 0000000000..d4f84bd4a9 --- /dev/null +++ b/scripts/kconfig/images.c @@ -0,0 +1,326 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +static const char *xpm_load[] = { +"22 22 5 1", +". c None", +"# c #000000", +"c c #838100", +"a c #ffff00", +"b c #ffffff", +"......................", +"......................", +"......................", +"............####....#.", +"...........#....##.##.", +"..................###.", +".................####.", +".####...........#####.", +"#abab##########.......", +"#babababababab#.......", +"#ababababababa#.......", +"#babababababab#.......", +"#ababab###############", +"#babab##cccccccccccc##", +"#abab##cccccccccccc##.", +"#bab##cccccccccccc##..", +"#ab##cccccccccccc##...", +"#b##cccccccccccc##....", +"###cccccccccccc##.....", +"##cccccccccccc##......", +"###############.......", +"......................"}; + +static const char *xpm_save[] = { +"22 22 5 1", +". c None", +"# c #000000", +"a c #838100", +"b c #c5c2c5", +"c c #cdb6d5", +"......................", +".####################.", +".#aa#bbbbbbbbbbbb#bb#.", +".#aa#bbbbbbbbbbbb#bb#.", +".#aa#bbbbbbbbbcbb####.", +".#aa#bbbccbbbbbbb#aa#.", +".#aa#bbbccbbbbbbb#aa#.", +".#aa#bbbbbbbbbbbb#aa#.", +".#aa#bbbbbbbbbbbb#aa#.", +".#aa#bbbbbbbbbbbb#aa#.", +".#aa#bbbbbbbbbbbb#aa#.", +".#aaa############aaa#.", +".#aaaaaaaaaaaaaaaaaa#.", +".#aaaaaaaaaaaaaaaaaa#.", +".#aaa#############aa#.", +".#aaa#########bbb#aa#.", +".#aaa#########bbb#aa#.", +".#aaa#########bbb#aa#.", +".#aaa#########bbb#aa#.", +".#aaa#########bbb#aa#.", +"..##################..", +"......................"}; + +static const char *xpm_back[] = { +"22 22 3 1", +". c None", +"# c #000083", +"a c #838183", +"......................", +"......................", +"......................", +"......................", +"......................", +"...........######a....", +"..#......##########...", +"..##...####......##a..", +"..###.###.........##..", +"..######..........##..", +"..#####...........##..", +"..######..........##..", +"..#######.........##..", +"..########.......##a..", +"...............a###...", +"...............###....", +"......................", +"......................", +"......................", +"......................", +"......................", +"......................"}; + +static const char *xpm_tree_view[] = { +"22 22 2 1", +". c None", +"# c #000000", +"......................", +"......................", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......########........", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......########........", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......########........", +"......................", +"......................"}; + +static const char *xpm_single_view[] = { +"22 22 2 1", +". c None", +"# c #000000", +"......................", +"......................", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"......................", +"......................"}; + +static const char *xpm_split_view[] = { +"22 22 2 1", +". c None", +"# c #000000", +"......................", +"......................", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......................", +"......................"}; + +static const char *xpm_symbol_no[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" .......... ", +" "}; + +static const char *xpm_symbol_mod[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . . ", +" . .. . ", +" . .... . ", +" . .... . ", +" . .. . ", +" . . ", +" . . ", +" .......... ", +" "}; + +static const char *xpm_symbol_yes[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . . ", +" . . . ", +" . .. . ", +" . . .. . ", +" . .... . ", +" . .. . ", +" . . ", +" .......... ", +" "}; + +static const char *xpm_choice_no[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .... ", +" .. .. ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" .. .. ", +" .... ", +" "}; + +static const char *xpm_choice_yes[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .... ", +" .. .. ", +" . . ", +" . .. . ", +" . .... . ", +" . .... . ", +" . .. . ", +" . . ", +" .. .. ", +" .... ", +" "}; + +static const char *xpm_menu[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . .. . ", +" . .... . ", +" . ...... . ", +" . ...... . ", +" . .... . ", +" . .. . ", +" . . ", +" .......... ", +" "}; + +static const char *xpm_menu_inv[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" .......... ", +" .. ...... ", +" .. .... ", +" .. .. ", +" .. .. ", +" .. .... ", +" .. ...... ", +" .......... ", +" .......... ", +" "}; + +static const char *xpm_menuback[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . .. . ", +" . .... . ", +" . ...... . ", +" . ...... . ", +" . .... . ", +" . .. . ", +" . . ", +" .......... ", +" "}; + +static const char *xpm_void[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" "}; diff --git a/scripts/kconfig/kxgettext.c b/scripts/kconfig/kxgettext.c new file mode 100644 index 0000000000..2858738b22 --- /dev/null +++ b/scripts/kconfig/kxgettext.c @@ -0,0 +1,235 @@ +/* + * Arnaldo Carvalho de Melo , 2005 + * + * Released under the terms of the GNU GPL v2.0 + */ + +#include +#include + +#include "lkc.h" + +static char *escape(const char* text, char *bf, int len) +{ + char *bfp = bf; + int multiline = strchr(text, '\n') != NULL; + int eol = 0; + int textlen = strlen(text); + + if ((textlen > 0) && (text[textlen-1] == '\n')) + eol = 1; + + *bfp++ = '"'; + --len; + + if (multiline) { + *bfp++ = '"'; + *bfp++ = '\n'; + *bfp++ = '"'; + len -= 3; + } + + while (*text != '\0' && len > 1) { + if (*text == '"') + *bfp++ = '\\'; + else if (*text == '\n') { + *bfp++ = '\\'; + *bfp++ = 'n'; + *bfp++ = '"'; + *bfp++ = '\n'; + *bfp++ = '"'; + len -= 5; + ++text; + goto next; + } + else if (*text == '\\') { + *bfp++ = '\\'; + len--; + } + *bfp++ = *text++; +next: + --len; + } + + if (multiline && eol) + bfp -= 3; + + *bfp++ = '"'; + *bfp = '\0'; + + return bf; +} + +struct file_line { + struct file_line *next; + const char *file; + int lineno; +}; + +static struct file_line *file_line__new(const char *file, int lineno) +{ + struct file_line *self = malloc(sizeof(*self)); + + if (self == NULL) + goto out; + + self->file = file; + self->lineno = lineno; + self->next = NULL; +out: + return self; +} + +struct message { + const char *msg; + const char *option; + struct message *next; + struct file_line *files; +}; + +static struct message *message__list; + +static struct message *message__new(const char *msg, char *option, + const char *file, int lineno) +{ + struct message *self = malloc(sizeof(*self)); + + if (self == NULL) + goto out; + + self->files = file_line__new(file, lineno); + if (self->files == NULL) + goto out_fail; + + self->msg = strdup(msg); + if (self->msg == NULL) + goto out_fail_msg; + + self->option = option; + self->next = NULL; +out: + return self; +out_fail_msg: + free(self->files); +out_fail: + free(self); + self = NULL; + goto out; +} + +static struct message *mesage__find(const char *msg) +{ + struct message *m = message__list; + + while (m != NULL) { + if (strcmp(m->msg, msg) == 0) + break; + m = m->next; + } + + return m; +} + +static int message__add_file_line(struct message *self, const char *file, + int lineno) +{ + int rc = -1; + struct file_line *fl = file_line__new(file, lineno); + + if (fl == NULL) + goto out; + + fl->next = self->files; + self->files = fl; + rc = 0; +out: + return rc; +} + +static int message__add(const char *msg, char *option, const char *file, + int lineno) +{ + int rc = 0; + char bf[16384]; + char *escaped = escape(msg, bf, sizeof(bf)); + struct message *m = mesage__find(escaped); + + if (m != NULL) + rc = message__add_file_line(m, file, lineno); + else { + m = message__new(escaped, option, file, lineno); + + if (m != NULL) { + m->next = message__list; + message__list = m; + } else + rc = -1; + } + return rc; +} + +static void menu_build_message_list(struct menu *menu) +{ + struct menu *child; + + message__add(menu_get_prompt(menu), NULL, + menu->file == NULL ? "Root Menu" : menu->file->name, + menu->lineno); + + if (menu->sym != NULL && menu_has_help(menu)) + message__add(menu_get_help(menu), menu->sym->name, + menu->file == NULL ? "Root Menu" : menu->file->name, + menu->lineno); + + for (child = menu->list; child != NULL; child = child->next) + if (child->prompt != NULL) + menu_build_message_list(child); +} + +static void message__print_file_lineno(struct message *self) +{ + struct file_line *fl = self->files; + + putchar('\n'); + if (self->option != NULL) + printf("# %s:00000\n", self->option); + + printf("#: %s:%d", fl->file, fl->lineno); + fl = fl->next; + + while (fl != NULL) { + printf(", %s:%d", fl->file, fl->lineno); + fl = fl->next; + } + + putchar('\n'); +} + +static void message__print_gettext_msgid_msgstr(struct message *self) +{ + message__print_file_lineno(self); + + printf("msgid %s\n" + "msgstr \"\"\n", self->msg); +} + +static void menu__xgettext(void) +{ + struct message *m = message__list; + + while (m != NULL) { + /* skip empty lines ("") */ + if (strlen(m->msg) > sizeof("\"\"")) + message__print_gettext_msgid_msgstr(m); + m = m->next; + } +} + +int main(int ac, char **av) +{ + conf_parse(av[1]); + + menu_build_message_list(menu_get_root_menu(NULL)); + menu__xgettext(); + return 0; +} diff --git a/scripts/kconfig/list.h b/scripts/kconfig/list.h new file mode 100644 index 0000000000..685d80e1bb --- /dev/null +++ b/scripts/kconfig/list.h @@ -0,0 +1,131 @@ +#ifndef LIST_H +#define LIST_H + +/* + * Copied from include/linux/... + */ + +#undef offsetof +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + + +struct list_head { + struct list_head *next, *prev; +}; + + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_add(struct list_head *_new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = _new; + _new->next = next; + _new->prev = prev; + prev->next = _new; +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *_new, struct list_head *head) +{ + __list_add(_new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head *prev, struct list_head *next) +{ + next->prev = prev; + prev->next = next; +} + +#define LIST_POISON1 ((void *) 0x00100100) +#define LIST_POISON2 ((void *) 0x00200200) +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = (struct list_head*)LIST_POISON1; + entry->prev = (struct list_head*)LIST_POISON2; +} +#endif diff --git a/scripts/kconfig/lkc.h b/scripts/kconfig/lkc.h new file mode 100644 index 0000000000..d5daa7af8b --- /dev/null +++ b/scripts/kconfig/lkc.h @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#ifndef LKC_H +#define LKC_H + +#include "expr.h" + +#ifndef KBUILD_NO_NLS +# include +#else +static inline const char *gettext(const char *txt) { return txt; } +static inline void textdomain(const char *domainname) {} +static inline void bindtextdomain(const char *name, const char *dir) {} +static inline char *bind_textdomain_codeset(const char *dn, char *c) { return c; } +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define P(name,type,arg) extern type name arg +#include "lkc_proto.h" +#undef P + +#define SRCTREE "srctree" + +#ifndef PACKAGE +#define PACKAGE "linux" +#endif + +#define LOCALEDIR "/usr/share/locale" + +#define _(text) gettext(text) +#define N_(text) (text) + +#ifndef CONFIG_ +#define CONFIG_ "CONFIG_" +#endif +static inline const char *CONFIG_prefix(void) +{ + return getenv( "CONFIG_" ) ?: CONFIG_; +} +#undef CONFIG_ +#define CONFIG_ CONFIG_prefix() + +#define TF_COMMAND 0x0001 +#define TF_PARAM 0x0002 +#define TF_OPTION 0x0004 + +enum conf_def_mode { + def_default, + def_yes, + def_mod, + def_no, + def_random +}; + +#define T_OPT_MODULES 1 +#define T_OPT_DEFCONFIG_LIST 2 +#define T_OPT_ENV 3 +#define T_OPT_ALLNOCONFIG_Y 4 + +struct kconf_id { + int name; + int token; + unsigned int flags; + enum symbol_type stype; +}; + +extern int zconfdebug; + +int zconfparse(void); +void zconfdump(FILE *out); +void zconf_starthelp(void); +FILE *zconf_fopen(const char *name); +void zconf_initscan(const char *name); +void zconf_nextfile(const char *name); +int zconf_lineno(void); +const char *zconf_curname(void); + +/* confdata.c */ +const char *conf_get_configname(void); +const char *conf_get_autoconfig_name(void); +char *conf_get_default_confname(void); +void sym_set_change_count(int count); +void sym_add_change_count(int count); +bool conf_set_all_new_symbols(enum conf_def_mode mode); +void set_all_choice_values(struct symbol *csym); + +struct conf_printer { + void (*print_symbol)(FILE *, struct symbol *, const char *, void *); + void (*print_comment)(FILE *, const char *, void *); +}; + +/* confdata.c and expr.c */ +static inline void xfwrite(const void *str, size_t len, size_t count, FILE *out) +{ + assert(len != 0); + + if (fwrite(str, len, count, out) != count) + fprintf(stderr, "Error in writing or end of file.\n"); +} + +/* menu.c */ +void _menu_init(void); +void menu_warn(struct menu *menu, const char *fmt, ...); +struct menu *menu_add_menu(void); +void menu_end_menu(void); +void menu_add_entry(struct symbol *sym); +void menu_end_entry(void); +void menu_add_dep(struct expr *dep); +void menu_add_visibility(struct expr *dep); +struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *expr, struct expr *dep); +struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep); +void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep); +void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep); +void menu_add_option(int token, char *arg); +void menu_finalize(struct menu *parent); +void menu_set_type(int type); + +/* util.c */ +struct file *file_lookup(const char *name); +int file_write_dep(const char *name); +void *xmalloc(size_t size); +void *xcalloc(size_t nmemb, size_t size); + +struct gstr { + size_t len; + char *s; + /* + * when max_width is not zero long lines in string s (if any) get + * wrapped not to exceed the max_width value + */ + int max_width; +}; +struct gstr str_new(void); +struct gstr str_assign(const char *s); +void str_free(struct gstr *gs); +void str_append(struct gstr *gs, const char *s); +void str_printf(struct gstr *gs, const char *fmt, ...); +const char *str_get(struct gstr *gs); + +/* symbol.c */ +extern struct expr *sym_env_list; + +void sym_init(void); +void sym_clear_all_valid(void); +void sym_set_all_changed(void); +void sym_set_changed(struct symbol *sym); +struct symbol *sym_choice_default(struct symbol *sym); +const char *sym_get_string_default(struct symbol *sym); +struct symbol *sym_check_deps(struct symbol *sym); +struct property *prop_alloc(enum prop_type type, struct symbol *sym); +struct symbol *prop_get_symbol(struct property *prop); +struct property *sym_get_env_prop(struct symbol *sym); + +static inline tristate sym_get_tristate_value(struct symbol *sym) +{ + return sym->curr.tri; +} + + +static inline struct symbol *sym_get_choice_value(struct symbol *sym) +{ + return (struct symbol *)sym->curr.val; +} + +static inline bool sym_set_choice_value(struct symbol *ch, struct symbol *chval) +{ + return sym_set_tristate_value(chval, yes); +} + +static inline bool sym_is_choice(struct symbol *sym) +{ + return sym->flags & SYMBOL_CHOICE ? true : false; +} + +static inline bool sym_is_choice_value(struct symbol *sym) +{ + return sym->flags & SYMBOL_CHOICEVAL ? true : false; +} + +static inline bool sym_is_optional(struct symbol *sym) +{ + return sym->flags & SYMBOL_OPTIONAL ? true : false; +} + +static inline bool sym_has_value(struct symbol *sym) +{ + return sym->flags & SYMBOL_DEF_USER ? true : false; +} + +#ifdef __cplusplus +} +#endif + +#endif /* LKC_H */ diff --git a/scripts/kconfig/lkc_proto.h b/scripts/kconfig/lkc_proto.h new file mode 100644 index 0000000000..ecdb9659b6 --- /dev/null +++ b/scripts/kconfig/lkc_proto.h @@ -0,0 +1,57 @@ +#include + +/* confdata.c */ +P(conf_parse,void,(const char *name)); +P(conf_read,int,(const char *name)); +P(conf_read_simple,int,(const char *name, int)); +P(conf_write_defconfig,int,(const char *name)); +P(conf_write,int,(const char *name)); +P(conf_write_autoconf,int,(void)); +P(conf_get_changed,bool,(void)); +P(conf_set_changed_callback, void,(void (*fn)(void))); +P(conf_set_message_callback, void,(void (*fn)(const char *fmt, va_list ap))); + +/* menu.c */ +P(rootmenu,struct menu,); + +P(menu_is_empty, bool, (struct menu *menu)); +P(menu_is_visible, bool, (struct menu *menu)); +P(menu_has_prompt, bool, (struct menu *menu)); +P(menu_get_prompt,const char *,(struct menu *menu)); +P(menu_get_root_menu,struct menu *,(struct menu *menu)); +P(menu_get_parent_menu,struct menu *,(struct menu *menu)); +P(menu_has_help,bool,(struct menu *menu)); +P(menu_get_help,const char *,(struct menu *menu)); +P(get_symbol_str, void, (struct gstr *r, struct symbol *sym, struct list_head + *head)); +P(get_relations_str, struct gstr, (struct symbol **sym_arr, struct list_head + *head)); +P(menu_get_ext_help,void,(struct menu *menu, struct gstr *help)); + +/* symbol.c */ +P(symbol_hash,struct symbol *,[SYMBOL_HASHSIZE]); + +P(sym_lookup,struct symbol *,(const char *name, int flags)); +P(sym_find,struct symbol *,(const char *name)); +P(sym_expand_string_value,const char *,(const char *in)); +P(sym_escape_string_value, const char *,(const char *in)); +P(sym_re_search,struct symbol **,(const char *pattern)); +P(sym_type_name,const char *,(enum symbol_type type)); +P(sym_calc_value,void,(struct symbol *sym)); +P(sym_get_type,enum symbol_type,(struct symbol *sym)); +P(sym_tristate_within_range,bool,(struct symbol *sym,tristate tri)); +P(sym_set_tristate_value,bool,(struct symbol *sym,tristate tri)); +P(sym_toggle_tristate_value,tristate,(struct symbol *sym)); +P(sym_string_valid,bool,(struct symbol *sym, const char *newval)); +P(sym_string_within_range,bool,(struct symbol *sym, const char *str)); +P(sym_set_string_value,bool,(struct symbol *sym, const char *newval)); +P(sym_is_changable,bool,(struct symbol *sym)); +P(sym_get_choice_prop,struct property *,(struct symbol *sym)); +P(sym_get_default_prop,struct property *,(struct symbol *sym)); +P(sym_get_string_value,const char *,(struct symbol *sym)); + +P(prop_get_type_name,const char *,(enum prop_type type)); + +/* expr.c */ +P(expr_compare_type,int,(enum expr_type t1, enum expr_type t2)); +P(expr_print,void,(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken)); diff --git a/scripts/kconfig/lxdialog/.gitignore b/scripts/kconfig/lxdialog/.gitignore new file mode 100644 index 0000000000..90b08ff025 --- /dev/null +++ b/scripts/kconfig/lxdialog/.gitignore @@ -0,0 +1,4 @@ +# +# Generated files +# +lxdialog diff --git a/scripts/kconfig/lxdialog/BIG.FAT.WARNING b/scripts/kconfig/lxdialog/BIG.FAT.WARNING new file mode 100644 index 0000000000..a8999d82bd --- /dev/null +++ b/scripts/kconfig/lxdialog/BIG.FAT.WARNING @@ -0,0 +1,4 @@ +This is NOT the official version of dialog. This version has been +significantly modified from the original. It is for use by the Linux +kernel configuration script. Please do not bother Savio Lam with +questions about this program. diff --git a/scripts/kconfig/lxdialog/check-lxdialog.sh b/scripts/kconfig/lxdialog/check-lxdialog.sh new file mode 100755 index 0000000000..9d2a4c585e --- /dev/null +++ b/scripts/kconfig/lxdialog/check-lxdialog.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# Check ncurses compatibility + +# What library to link +ldflags() +{ + pkg-config --libs ncursesw 2>/dev/null && exit + pkg-config --libs ncurses 2>/dev/null && exit + for ext in so a dll.a dylib ; do + for lib in ncursesw ncurses curses ; do + $cc -print-file-name=lib${lib}.${ext} | grep -q / + if [ $? -eq 0 ]; then + echo "-l${lib}" + exit + fi + done + done + exit 1 +} + +# Where is ncurses.h? +ccflags() +{ + if [ -f /usr/include/ncursesw/curses.h ]; then + echo '-I/usr/include/ncursesw -DCURSES_LOC=""' + echo ' -DNCURSES_WIDECHAR=1' + elif [ -f /usr/include/ncurses/ncurses.h ]; then + echo '-I/usr/include/ncurses -DCURSES_LOC=""' + elif [ -f /usr/include/ncurses/curses.h ]; then + echo '-I/usr/include/ncurses -DCURSES_LOC=""' + elif [ -f /usr/include/ncurses.h ]; then + echo '-DCURSES_LOC=""' + else + echo '-DCURSES_LOC=""' + fi +} + +# Temp file, try to clean up after us +tmp=.lxdialog.tmp +trap "rm -f $tmp" 0 1 2 3 15 + +# Check if we can link to ncurses +check() { + $cc -x c - -o $tmp 2>/dev/null <<'EOF' +#include CURSES_LOC +main() {} +EOF + if [ $? != 0 ]; then + echo " *** Unable to find the ncurses libraries or the" 1>&2 + echo " *** required header files." 1>&2 + echo " *** 'make menuconfig' requires the ncurses libraries." 1>&2 + echo " *** " 1>&2 + echo " *** Install ncurses (ncurses-devel) and try again." 1>&2 + echo " *** " 1>&2 + exit 1 + fi +} + +usage() { + printf "Usage: $0 [-check compiler options|-ccflags|-ldflags compiler options]\n" +} + +if [ $# -eq 0 ]; then + usage + exit 1 +fi + +cc="" +case "$1" in + "-check") + shift + cc="$@" + check + ;; + "-ccflags") + ccflags + ;; + "-ldflags") + shift + cc="$@" + ldflags + ;; + "*") + usage + exit 1 + ;; +esac diff --git a/scripts/kconfig/lxdialog/checklist.c b/scripts/kconfig/lxdialog/checklist.c new file mode 100644 index 0000000000..8d016faa28 --- /dev/null +++ b/scripts/kconfig/lxdialog/checklist.c @@ -0,0 +1,332 @@ +/* + * checklist.c -- implements the checklist box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * Stuart Herbert - S.Herbert@sheffield.ac.uk: radiolist extension + * Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +static int list_width, check_x, item_x; + +/* + * Print list item + */ +static void print_item(WINDOW * win, int choice, int selected) +{ + int i; + char *list_item = malloc(list_width + 1); + + strncpy(list_item, item_str(), list_width - item_x); + list_item[list_width - item_x] = '\0'; + + /* Clear 'residue' of last item */ + wattrset(win, dlg.menubox.atr); + wmove(win, choice, 0); + for (i = 0; i < list_width; i++) + waddch(win, ' '); + + wmove(win, choice, check_x); + wattrset(win, selected ? dlg.check_selected.atr + : dlg.check.atr); + if (!item_is_tag(':')) + wprintw(win, "(%c)", item_is_tag('X') ? 'X' : ' '); + + wattrset(win, selected ? dlg.tag_selected.atr : dlg.tag.atr); + mvwaddch(win, choice, item_x, list_item[0]); + wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr); + waddstr(win, list_item + 1); + if (selected) { + wmove(win, choice, check_x + 1); + wrefresh(win); + } + free(list_item); +} + +/* + * Print the scroll indicators. + */ +static void print_arrows(WINDOW * win, int choice, int item_no, int scroll, + int y, int x, int height) +{ + wmove(win, y, x); + + if (scroll > 0) { + wattrset(win, dlg.uarrow.atr); + waddch(win, ACS_UARROW); + waddstr(win, "(-)"); + } else { + wattrset(win, dlg.menubox.atr); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + } + + y = y + height + 1; + wmove(win, y, x); + + if ((height < item_no) && (scroll + choice < item_no - 1)) { + wattrset(win, dlg.darrow.atr); + waddch(win, ACS_DARROW); + waddstr(win, "(+)"); + } else { + wattrset(win, dlg.menubox_border.atr); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + } +} + +/* + * Display the termination buttons + */ +static void print_buttons(WINDOW * dialog, int height, int width, int selected) +{ + int x = width / 2 - 11; + int y = height - 2; + + print_button(dialog, gettext("Select"), y, x, selected == 0); + print_button(dialog, gettext(" Help "), y, x + 14, selected == 1); + + wmove(dialog, y, x + 1 + 14 * selected); + wrefresh(dialog); +} + +/* + * Display a dialog box with a list of options that can be turned on or off + * in the style of radiolist (only one option turned on at a time). + */ +int dialog_checklist(const char *title, const char *prompt, int height, + int width, int list_height) +{ + int i, x, y, box_x, box_y; + int key = 0, button = 0, choice = 0, scroll = 0, max_choice; + WINDOW *dialog, *list; + + /* which item to highlight */ + item_foreach() { + if (item_is_tag('X')) + choice = item_n(); + if (item_is_selected()) { + choice = item_n(); + break; + } + } + +do_resize: + if (getmaxy(stdscr) < (height + CHECKLIST_HEIGTH_MIN)) + return -ERRDISPLAYTOOSMALL; + if (getmaxx(stdscr) < (width + CHECKLIST_WIDTH_MIN)) + return -ERRDISPLAYTOOSMALL; + + max_choice = MIN(list_height, item_count()); + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + wattrset(dialog, dlg.dialog.atr); + print_autowrap(dialog, prompt, width - 2, 1, 3); + + list_width = width - 6; + box_y = height - list_height - 5; + box_x = (width - list_width) / 2 - 1; + + /* create new window for the list */ + list = subwin(dialog, list_height, list_width, y + box_y + 1, + x + box_x + 1); + + keypad(list, TRUE); + + /* draw a box around the list items */ + draw_box(dialog, box_y, box_x, list_height + 2, list_width + 2, + dlg.menubox_border.atr, dlg.menubox.atr); + + /* Find length of longest item in order to center checklist */ + check_x = 0; + item_foreach() + check_x = MAX(check_x, strlen(item_str()) + 4); + check_x = MIN(check_x, list_width); + + check_x = (list_width - check_x) / 2; + item_x = check_x + 4; + + if (choice >= list_height) { + scroll = choice - list_height + 1; + choice -= scroll; + } + + /* Print the list */ + for (i = 0; i < max_choice; i++) { + item_set(scroll + i); + print_item(list, i, i == choice); + } + + print_arrows(dialog, choice, item_count(), scroll, + box_y, box_x + check_x + 5, list_height); + + print_buttons(dialog, height, width, 0); + + wnoutrefresh(dialog); + wnoutrefresh(list); + doupdate(); + + while (key != KEY_ESC) { + key = wgetch(dialog); + + for (i = 0; i < max_choice; i++) { + item_set(i + scroll); + if (toupper(key) == toupper(item_str()[0])) + break; + } + + if (i < max_choice || key == KEY_UP || key == KEY_DOWN || + key == '+' || key == '-') { + if (key == KEY_UP || key == '-') { + if (!choice) { + if (!scroll) + continue; + /* Scroll list down */ + if (list_height > 1) { + /* De-highlight current first item */ + item_set(scroll); + print_item(list, 0, FALSE); + scrollok(list, TRUE); + wscrl(list, -1); + scrollok(list, FALSE); + } + scroll--; + item_set(scroll); + print_item(list, 0, TRUE); + print_arrows(dialog, choice, item_count(), + scroll, box_y, box_x + check_x + 5, list_height); + + wnoutrefresh(dialog); + wrefresh(list); + + continue; /* wait for another key press */ + } else + i = choice - 1; + } else if (key == KEY_DOWN || key == '+') { + if (choice == max_choice - 1) { + if (scroll + choice >= item_count() - 1) + continue; + /* Scroll list up */ + if (list_height > 1) { + /* De-highlight current last item before scrolling up */ + item_set(scroll + max_choice - 1); + print_item(list, + max_choice - 1, + FALSE); + scrollok(list, TRUE); + wscrl(list, 1); + scrollok(list, FALSE); + } + scroll++; + item_set(scroll + max_choice - 1); + print_item(list, max_choice - 1, TRUE); + + print_arrows(dialog, choice, item_count(), + scroll, box_y, box_x + check_x + 5, list_height); + + wnoutrefresh(dialog); + wrefresh(list); + + continue; /* wait for another key press */ + } else + i = choice + 1; + } + if (i != choice) { + /* De-highlight current item */ + item_set(scroll + choice); + print_item(list, choice, FALSE); + /* Highlight new item */ + choice = i; + item_set(scroll + choice); + print_item(list, choice, TRUE); + wnoutrefresh(dialog); + wrefresh(list); + } + continue; /* wait for another key press */ + } + switch (key) { + case 'H': + case 'h': + case '?': + button = 1; + /* fall-through */ + case 'S': + case 's': + case ' ': + case '\n': + item_foreach() + item_set_selected(0); + item_set(scroll + choice); + item_set_selected(1); + delwin(list); + delwin(dialog); + return button; + case TAB: + case KEY_LEFT: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) + ? 1 : (button > 1 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh(dialog); + break; + case 'X': + case 'x': + key = KEY_ESC; + break; + case KEY_ESC: + key = on_key_esc(dialog); + break; + case KEY_RESIZE: + delwin(list); + delwin(dialog); + on_key_resize(); + goto do_resize; + } + + /* Now, update everything... */ + doupdate(); + } + delwin(list); + delwin(dialog); + return key; /* ESC pressed */ +} diff --git a/scripts/kconfig/lxdialog/dialog.h b/scripts/kconfig/lxdialog/dialog.h new file mode 100644 index 0000000000..fcffd5b41f --- /dev/null +++ b/scripts/kconfig/lxdialog/dialog.h @@ -0,0 +1,257 @@ +/* + * dialog.h -- common declarations for all dialog modules + * + * AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef KBUILD_NO_NLS +# include +#else +# define gettext(Msgid) ((const char *) (Msgid)) +#endif + +#ifdef __sun__ +#define CURS_MACROS +#endif +#include CURSES_LOC + +/* + * Colors in ncurses 1.9.9e do not work properly since foreground and + * background colors are OR'd rather than separately masked. This version + * of dialog was hacked to work with ncurses 1.9.9e, making it incompatible + * with standard curses. The simplest fix (to make this work with standard + * curses) uses the wbkgdset() function, not used in the original hack. + * Turn it off if we're building with 1.9.9e, since it just confuses things. + */ +#if defined(NCURSES_VERSION) && defined(_NEED_WRAP) && !defined(GCC_PRINTFLIKE) +#define OLD_NCURSES 1 +#undef wbkgdset +#define wbkgdset(w,p) /*nothing */ +#else +#define OLD_NCURSES 0 +#endif + +#define TR(params) _tracef params + +#define KEY_ESC 27 +#define TAB 9 +#define MAX_LEN 2048 +#define BUF_SIZE (10*1024) +#define MIN(x,y) (x < y ? x : y) +#define MAX(x,y) (x > y ? x : y) + +#ifndef ACS_ULCORNER +#define ACS_ULCORNER '+' +#endif +#ifndef ACS_LLCORNER +#define ACS_LLCORNER '+' +#endif +#ifndef ACS_URCORNER +#define ACS_URCORNER '+' +#endif +#ifndef ACS_LRCORNER +#define ACS_LRCORNER '+' +#endif +#ifndef ACS_HLINE +#define ACS_HLINE '-' +#endif +#ifndef ACS_VLINE +#define ACS_VLINE '|' +#endif +#ifndef ACS_LTEE +#define ACS_LTEE '+' +#endif +#ifndef ACS_RTEE +#define ACS_RTEE '+' +#endif +#ifndef ACS_UARROW +#define ACS_UARROW '^' +#endif +#ifndef ACS_DARROW +#define ACS_DARROW 'v' +#endif + +/* error return codes */ +#define ERRDISPLAYTOOSMALL (KEY_MAX + 1) + +/* + * Color definitions + */ +struct dialog_color { + chtype atr; /* Color attribute */ + int fg; /* foreground */ + int bg; /* background */ + int hl; /* highlight this item */ +}; + +struct subtitle_list { + struct subtitle_list *next; + const char *text; +}; + +struct dialog_info { + const char *backtitle; + struct subtitle_list *subtitles; + struct dialog_color screen; + struct dialog_color shadow; + struct dialog_color dialog; + struct dialog_color title; + struct dialog_color border; + struct dialog_color button_active; + struct dialog_color button_inactive; + struct dialog_color button_key_active; + struct dialog_color button_key_inactive; + struct dialog_color button_label_active; + struct dialog_color button_label_inactive; + struct dialog_color inputbox; + struct dialog_color inputbox_border; + struct dialog_color searchbox; + struct dialog_color searchbox_title; + struct dialog_color searchbox_border; + struct dialog_color position_indicator; + struct dialog_color menubox; + struct dialog_color menubox_border; + struct dialog_color item; + struct dialog_color item_selected; + struct dialog_color tag; + struct dialog_color tag_selected; + struct dialog_color tag_key; + struct dialog_color tag_key_selected; + struct dialog_color check; + struct dialog_color check_selected; + struct dialog_color uarrow; + struct dialog_color darrow; +}; + +/* + * Global variables + */ +extern struct dialog_info dlg; +extern char dialog_input_result[]; +extern int saved_x, saved_y; /* Needed in signal handler in mconf.c */ + +/* + * Function prototypes + */ + +/* item list as used by checklist and menubox */ +void item_reset(void); +void item_make(const char *fmt, ...); +void item_add_str(const char *fmt, ...); +void item_set_tag(char tag); +void item_set_data(void *p); +void item_set_selected(int val); +int item_activate_selected(void); +void *item_data(void); +char item_tag(void); + +/* item list manipulation for lxdialog use */ +#define MAXITEMSTR 200 +struct dialog_item { + char str[MAXITEMSTR]; /* prompt displayed */ + char tag; + void *data; /* pointer to menu item - used by menubox+checklist */ + int selected; /* Set to 1 by dialog_*() function if selected. */ +}; + +/* list of lialog_items */ +struct dialog_list { + struct dialog_item node; + struct dialog_list *next; +}; + +extern struct dialog_list *item_cur; +extern struct dialog_list item_nil; +extern struct dialog_list *item_head; + +int item_count(void); +void item_set(int n); +int item_n(void); +const char *item_str(void); +int item_is_selected(void); +int item_is_tag(char tag); +#define item_foreach() \ + for (item_cur = item_head ? item_head: item_cur; \ + item_cur && (item_cur != &item_nil); item_cur = item_cur->next) + +/* generic key handlers */ +int on_key_esc(WINDOW *win); +int on_key_resize(void); + +/* minimum (re)size values */ +#define CHECKLIST_HEIGTH_MIN 6 /* For dialog_checklist() */ +#define CHECKLIST_WIDTH_MIN 6 +#define INPUTBOX_HEIGTH_MIN 2 /* For dialog_inputbox() */ +#define INPUTBOX_WIDTH_MIN 2 +#define MENUBOX_HEIGTH_MIN 15 /* For dialog_menu() */ +#define MENUBOX_WIDTH_MIN 65 +#define TEXTBOX_HEIGTH_MIN 8 /* For dialog_textbox() */ +#define TEXTBOX_WIDTH_MIN 8 +#define YESNO_HEIGTH_MIN 4 /* For dialog_yesno() */ +#define YESNO_WIDTH_MIN 4 +#define WINDOW_HEIGTH_MIN 19 /* For init_dialog() */ +#define WINDOW_WIDTH_MIN 80 + +int init_dialog(const char *backtitle); +void set_dialog_backtitle(const char *backtitle); +void set_dialog_subtitles(struct subtitle_list *subtitles); +void end_dialog(int x, int y); +void attr_clear(WINDOW * win, int height, int width, chtype attr); +void dialog_clear(void); +void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x); +void print_button(WINDOW * win, const char *label, int y, int x, int selected); +void print_title(WINDOW *dialog, const char *title, int width); +void draw_box(WINDOW * win, int y, int x, int height, int width, chtype box, + chtype border); +void draw_shadow(WINDOW * win, int y, int x, int height, int width); + +int first_alpha(const char *string, const char *exempt); +int dialog_yesno(const char *title, const char *prompt, int height, int width); +int dialog_msgbox(const char *title, const char *prompt, int height, + int width, int pause); + + +typedef void (*update_text_fn)(char *buf, size_t start, size_t end, void + *_data); +int dialog_textbox(const char *title, char *tbuf, int initial_height, + int initial_width, int *keys, int *_vscroll, int *_hscroll, + update_text_fn update_text, void *data); +int dialog_menu(const char *title, const char *prompt, + const void *selected, int *s_scroll); +int dialog_checklist(const char *title, const char *prompt, int height, + int width, int list_height); +int dialog_inputbox(const char *title, const char *prompt, int height, + int width, const char *init); + +/* + * This is the base for fictitious keys, which activate + * the buttons. + * + * Mouse-generated keys are the following: + * -- the first 32 are used as numbers, in addition to '0'-'9' + * -- the lowercase are used to signal mouse-enter events (M_EVENT + 'o') + * -- uppercase chars are used to invoke the button (M_EVENT + 'O') + */ +#define M_EVENT (KEY_MAX+1) diff --git a/scripts/kconfig/lxdialog/inputbox.c b/scripts/kconfig/lxdialog/inputbox.c new file mode 100644 index 0000000000..d58de1dc53 --- /dev/null +++ b/scripts/kconfig/lxdialog/inputbox.c @@ -0,0 +1,301 @@ +/* + * inputbox.c -- implements the input box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +char dialog_input_result[MAX_LEN + 1]; + +/* + * Print the termination buttons + */ +static void print_buttons(WINDOW * dialog, int height, int width, int selected) +{ + int x = width / 2 - 11; + int y = height - 2; + + print_button(dialog, gettext(" Ok "), y, x, selected == 0); + print_button(dialog, gettext(" Help "), y, x + 14, selected == 1); + + wmove(dialog, y, x + 1 + 14 * selected); + wrefresh(dialog); +} + +/* + * Display a dialog box for inputing a string + */ +int dialog_inputbox(const char *title, const char *prompt, int height, int width, + const char *init) +{ + int i, x, y, box_y, box_x, box_width; + int input_x = 0, key = 0, button = -1; + int show_x, len, pos; + char *instr = dialog_input_result; + WINDOW *dialog; + + if (!init) + instr[0] = '\0'; + else + strcpy(instr, init); + +do_resize: + if (getmaxy(stdscr) <= (height - INPUTBOX_HEIGTH_MIN)) + return -ERRDISPLAYTOOSMALL; + if (getmaxx(stdscr) <= (width - INPUTBOX_WIDTH_MIN)) + return -ERRDISPLAYTOOSMALL; + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + wattrset(dialog, dlg.dialog.atr); + print_autowrap(dialog, prompt, width - 2, 1, 3); + + /* Draw the input field box */ + box_width = width - 6; + getyx(dialog, y, x); + box_y = y + 2; + box_x = (width - box_width) / 2; + draw_box(dialog, y + 1, box_x - 1, 3, box_width + 2, + dlg.dialog.atr, dlg.border.atr); + + print_buttons(dialog, height, width, 0); + + /* Set up the initial value */ + wmove(dialog, box_y, box_x); + wattrset(dialog, dlg.inputbox.atr); + + len = strlen(instr); + pos = len; + + if (len >= box_width) { + show_x = len - box_width + 1; + input_x = box_width - 1; + for (i = 0; i < box_width - 1; i++) + waddch(dialog, instr[show_x + i]); + } else { + show_x = 0; + input_x = len; + waddstr(dialog, instr); + } + + wmove(dialog, box_y, box_x + input_x); + + wrefresh(dialog); + + while (key != KEY_ESC) { + key = wgetch(dialog); + + if (button == -1) { /* Input box selected */ + switch (key) { + case TAB: + case KEY_UP: + case KEY_DOWN: + break; + case KEY_BACKSPACE: + case 127: + if (pos) { + wattrset(dialog, dlg.inputbox.atr); + if (input_x == 0) { + show_x--; + } else + input_x--; + + if (pos < len) { + for (i = pos - 1; i < len; i++) { + instr[i] = instr[i+1]; + } + } + + pos--; + len--; + instr[len] = '\0'; + wmove(dialog, box_y, box_x); + for (i = 0; i < box_width; i++) { + if (!instr[show_x + i]) { + waddch(dialog, ' '); + break; + } + waddch(dialog, instr[show_x + i]); + } + wmove(dialog, box_y, input_x + box_x); + wrefresh(dialog); + } + continue; + case KEY_LEFT: + if (pos > 0) { + if (input_x > 0) { + wmove(dialog, box_y, --input_x + box_x); + } else if (input_x == 0) { + show_x--; + wmove(dialog, box_y, box_x); + for (i = 0; i < box_width; i++) { + if (!instr[show_x + i]) { + waddch(dialog, ' '); + break; + } + waddch(dialog, instr[show_x + i]); + } + wmove(dialog, box_y, box_x); + } + pos--; + } + continue; + case KEY_RIGHT: + if (pos < len) { + if (input_x < box_width - 1) { + wmove(dialog, box_y, ++input_x + box_x); + } else if (input_x == box_width - 1) { + show_x++; + wmove(dialog, box_y, box_x); + for (i = 0; i < box_width; i++) { + if (!instr[show_x + i]) { + waddch(dialog, ' '); + break; + } + waddch(dialog, instr[show_x + i]); + } + wmove(dialog, box_y, input_x + box_x); + } + pos++; + } + continue; + default: + if (key < 0x100 && isprint(key)) { + if (len < MAX_LEN) { + wattrset(dialog, dlg.inputbox.atr); + if (pos < len) { + for (i = len; i > pos; i--) + instr[i] = instr[i-1]; + instr[pos] = key; + } else { + instr[len] = key; + } + pos++; + len++; + instr[len] = '\0'; + + if (input_x == box_width - 1) { + show_x++; + } else { + input_x++; + } + + wmove(dialog, box_y, box_x); + for (i = 0; i < box_width; i++) { + if (!instr[show_x + i]) { + waddch(dialog, ' '); + break; + } + waddch(dialog, instr[show_x + i]); + } + wmove(dialog, box_y, input_x + box_x); + wrefresh(dialog); + } else + flash(); /* Alarm user about overflow */ + continue; + } + } + } + switch (key) { + case 'O': + case 'o': + delwin(dialog); + return 0; + case 'H': + case 'h': + delwin(dialog); + return 1; + case KEY_UP: + case KEY_LEFT: + switch (button) { + case -1: + button = 1; /* Indicates "Help" button is selected */ + print_buttons(dialog, height, width, 1); + break; + case 0: + button = -1; /* Indicates input box is selected */ + print_buttons(dialog, height, width, 0); + wmove(dialog, box_y, box_x + input_x); + wrefresh(dialog); + break; + case 1: + button = 0; /* Indicates "OK" button is selected */ + print_buttons(dialog, height, width, 0); + break; + } + break; + case TAB: + case KEY_DOWN: + case KEY_RIGHT: + switch (button) { + case -1: + button = 0; /* Indicates "OK" button is selected */ + print_buttons(dialog, height, width, 0); + break; + case 0: + button = 1; /* Indicates "Help" button is selected */ + print_buttons(dialog, height, width, 1); + break; + case 1: + button = -1; /* Indicates input box is selected */ + print_buttons(dialog, height, width, 0); + wmove(dialog, box_y, box_x + input_x); + wrefresh(dialog); + break; + } + break; + case ' ': + case '\n': + delwin(dialog); + return (button == -1 ? 0 : button); + case 'X': + case 'x': + key = KEY_ESC; + break; + case KEY_ESC: + key = on_key_esc(dialog); + break; + case KEY_RESIZE: + delwin(dialog); + on_key_resize(); + goto do_resize; + } + } + + delwin(dialog); + return KEY_ESC; /* ESC pressed */ +} diff --git a/scripts/kconfig/lxdialog/menubox.c b/scripts/kconfig/lxdialog/menubox.c new file mode 100644 index 0000000000..11ae9ad7ac --- /dev/null +++ b/scripts/kconfig/lxdialog/menubox.c @@ -0,0 +1,437 @@ +/* + * menubox.c -- implements the menu box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Changes by Clifford Wolf (god@clifford.at) + * + * [ 1998-06-13 ] + * + * *) A bugfix for the Page-Down problem + * + * *) Formerly when I used Page Down and Page Up, the cursor would be set + * to the first position in the menu box. Now lxdialog is a bit + * smarter and works more like other menu systems (just have a look at + * it). + * + * *) Formerly if I selected something my scrolling would be broken because + * lxdialog is re-invoked by the Menuconfig shell script, can't + * remember the last scrolling position, and just sets it so that the + * cursor is at the bottom of the box. Now it writes the temporary file + * lxdialog.scrltmp which contains this information. The file is + * deleted by lxdialog if the user leaves a submenu or enters a new + * one, but it would be nice if Menuconfig could make another "rm -f" + * just to be sure. Just try it out - you will recognise a difference! + * + * [ 1998-06-14 ] + * + * *) Now lxdialog is crash-safe against broken "lxdialog.scrltmp" files + * and menus change their size on the fly. + * + * *) If for some reason the last scrolling position is not saved by + * lxdialog, it sets the scrolling so that the selected item is in the + * middle of the menu box, not at the bottom. + * + * 02 January 1999, Michael Elizabeth Chastain (mec@shout.net) + * Reset 'scroll' to 0 if the value from lxdialog.scrltmp is bogus. + * This fixes a bug in Menuconfig where using ' ' to descend into menus + * would leave mis-synchronized lxdialog.scrltmp files lying around, + * fscanf would read in 'scroll', and eventually that value would get used. + */ + +#include "dialog.h" + +static int menu_width, item_x; + +/* + * Print menu item + */ +static void do_print_item(WINDOW * win, const char *item, int line_y, + int selected, int hotkey) +{ + int j; + char *menu_item = malloc(menu_width + 1); + + strncpy(menu_item, item, menu_width - item_x); + menu_item[menu_width - item_x] = '\0'; + j = first_alpha(menu_item, "YyNnMmHh"); + + /* Clear 'residue' of last item */ + wattrset(win, dlg.menubox.atr); + wmove(win, line_y, 0); +#if OLD_NCURSES + { + int i; + for (i = 0; i < menu_width; i++) + waddch(win, ' '); + } +#else + wclrtoeol(win); +#endif + wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr); + mvwaddstr(win, line_y, item_x, menu_item); + if (hotkey) { + wattrset(win, selected ? dlg.tag_key_selected.atr + : dlg.tag_key.atr); + mvwaddch(win, line_y, item_x + j, menu_item[j]); + } + if (selected) { + wmove(win, line_y, item_x + 1); + } + free(menu_item); + wrefresh(win); +} + +#define print_item(index, choice, selected) \ +do { \ + item_set(index); \ + do_print_item(menu, item_str(), choice, selected, !item_is_tag(':')); \ +} while (0) + +/* + * Print the scroll indicators. + */ +static void print_arrows(WINDOW * win, int item_no, int scroll, int y, int x, + int height) +{ + int cur_y, cur_x; + + getyx(win, cur_y, cur_x); + + wmove(win, y, x); + + if (scroll > 0) { + wattrset(win, dlg.uarrow.atr); + waddch(win, ACS_UARROW); + waddstr(win, "(-)"); + } else { + wattrset(win, dlg.menubox.atr); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + } + + y = y + height + 1; + wmove(win, y, x); + wrefresh(win); + + if ((height < item_no) && (scroll + height < item_no)) { + wattrset(win, dlg.darrow.atr); + waddch(win, ACS_DARROW); + waddstr(win, "(+)"); + } else { + wattrset(win, dlg.menubox_border.atr); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + } + + wmove(win, cur_y, cur_x); + wrefresh(win); +} + +/* + * Display the termination buttons. + */ +static void print_buttons(WINDOW * win, int height, int width, int selected) +{ + int x = width / 2 - 28; + int y = height - 2; + + print_button(win, gettext("Select"), y, x, selected == 0); + print_button(win, gettext(" Exit "), y, x + 12, selected == 1); + print_button(win, gettext(" Help "), y, x + 24, selected == 2); + print_button(win, gettext(" Save "), y, x + 36, selected == 3); + print_button(win, gettext(" Load "), y, x + 48, selected == 4); + + wmove(win, y, x + 1 + 12 * selected); + wrefresh(win); +} + +/* scroll up n lines (n may be negative) */ +static void do_scroll(WINDOW *win, int *scroll, int n) +{ + /* Scroll menu up */ + scrollok(win, TRUE); + wscrl(win, n); + scrollok(win, FALSE); + *scroll = *scroll + n; + wrefresh(win); +} + +/* + * Display a menu for choosing among a number of options + */ +int dialog_menu(const char *title, const char *prompt, + const void *selected, int *s_scroll) +{ + int i, j, x, y, box_x, box_y; + int height, width, menu_height; + int key = 0, button = 0, scroll = 0, choice = 0; + int first_item = 0, max_choice; + WINDOW *dialog, *menu; + +do_resize: + height = getmaxy(stdscr); + width = getmaxx(stdscr); + if (height < MENUBOX_HEIGTH_MIN || width < MENUBOX_WIDTH_MIN) + return -ERRDISPLAYTOOSMALL; + + height -= 4; + width -= 5; + menu_height = height - 10; + + max_choice = MIN(menu_height, item_count()); + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + wbkgdset(dialog, dlg.dialog.atr & A_COLOR); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + wattrset(dialog, dlg.dialog.atr); + print_autowrap(dialog, prompt, width - 2, 1, 3); + + menu_width = width - 6; + box_y = height - menu_height - 5; + box_x = (width - menu_width) / 2 - 1; + + /* create new window for the menu */ + menu = subwin(dialog, menu_height, menu_width, + y + box_y + 1, x + box_x + 1); + keypad(menu, TRUE); + + /* draw a box around the menu items */ + draw_box(dialog, box_y, box_x, menu_height + 2, menu_width + 2, + dlg.menubox_border.atr, dlg.menubox.atr); + + if (menu_width >= 80) + item_x = (menu_width - 70) / 2; + else + item_x = 4; + + /* Set choice to default item */ + item_foreach() + if (selected && (selected == item_data())) + choice = item_n(); + /* get the saved scroll info */ + scroll = *s_scroll; + if ((scroll <= choice) && (scroll + max_choice > choice) && + (scroll >= 0) && (scroll + max_choice <= item_count())) { + first_item = scroll; + choice = choice - scroll; + } else { + scroll = 0; + } + if ((choice >= max_choice)) { + if (choice >= item_count() - max_choice / 2) + scroll = first_item = item_count() - max_choice; + else + scroll = first_item = choice - max_choice / 2; + choice = choice - scroll; + } + + /* Print the menu */ + for (i = 0; i < max_choice; i++) { + print_item(first_item + i, i, i == choice); + } + + wnoutrefresh(menu); + + print_arrows(dialog, item_count(), scroll, + box_y, box_x + item_x + 1, menu_height); + + print_buttons(dialog, height, width, 0); + wmove(menu, choice, item_x + 1); + wrefresh(menu); + + while (key != KEY_ESC) { + key = wgetch(menu); + + if (key < 256 && isalpha(key)) + key = tolower(key); + + if (strchr("ynmh", key)) + i = max_choice; + else { + for (i = choice + 1; i < max_choice; i++) { + item_set(scroll + i); + j = first_alpha(item_str(), "YyNnMmHh"); + if (key == tolower(item_str()[j])) + break; + } + if (i == max_choice) + for (i = 0; i < max_choice; i++) { + item_set(scroll + i); + j = first_alpha(item_str(), "YyNnMmHh"); + if (key == tolower(item_str()[j])) + break; + } + } + + if (item_count() != 0 && + (i < max_choice || + key == KEY_UP || key == KEY_DOWN || + key == '-' || key == '+' || + key == KEY_PPAGE || key == KEY_NPAGE)) { + /* Remove highligt of current item */ + print_item(scroll + choice, choice, FALSE); + + if (key == KEY_UP || key == '-') { + if (choice < 2 && scroll) { + /* Scroll menu down */ + do_scroll(menu, &scroll, -1); + + print_item(scroll, 0, FALSE); + } else + choice = MAX(choice - 1, 0); + + } else if (key == KEY_DOWN || key == '+') { + print_item(scroll+choice, choice, FALSE); + + if ((choice > max_choice - 3) && + (scroll + max_choice < item_count())) { + /* Scroll menu up */ + do_scroll(menu, &scroll, 1); + + print_item(scroll+max_choice - 1, + max_choice - 1, FALSE); + } else + choice = MIN(choice + 1, max_choice - 1); + + } else if (key == KEY_PPAGE) { + scrollok(menu, TRUE); + for (i = 0; (i < max_choice); i++) { + if (scroll > 0) { + do_scroll(menu, &scroll, -1); + print_item(scroll, 0, FALSE); + } else { + if (choice > 0) + choice--; + } + } + + } else if (key == KEY_NPAGE) { + for (i = 0; (i < max_choice); i++) { + if (scroll + max_choice < item_count()) { + do_scroll(menu, &scroll, 1); + print_item(scroll+max_choice-1, + max_choice - 1, FALSE); + } else { + if (choice + 1 < max_choice) + choice++; + } + } + } else + choice = i; + + print_item(scroll + choice, choice, TRUE); + + print_arrows(dialog, item_count(), scroll, + box_y, box_x + item_x + 1, menu_height); + + wnoutrefresh(dialog); + wrefresh(menu); + + continue; /* wait for another key press */ + } + + switch (key) { + case KEY_LEFT: + case TAB: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) + ? 4 : (button > 4 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh(menu); + break; + case ' ': + case 's': + case 'y': + case 'n': + case 'm': + case '/': + case 'h': + case '?': + case 'z': + case '\n': + /* save scroll info */ + *s_scroll = scroll; + delwin(menu); + delwin(dialog); + item_set(scroll + choice); + item_set_selected(1); + switch (key) { + case 'h': + case '?': + return 2; + case 's': + case 'y': + return 5; + case 'n': + return 6; + case 'm': + return 7; + case ' ': + return 8; + case '/': + return 9; + case 'z': + return 10; + case '\n': + return button; + } + return 0; + case 'e': + case 'x': + key = KEY_ESC; + break; + case KEY_ESC: + key = on_key_esc(menu); + break; + case KEY_RESIZE: + on_key_resize(); + delwin(menu); + delwin(dialog); + goto do_resize; + } + } + delwin(menu); + delwin(dialog); + return key; /* ESC pressed */ +} diff --git a/scripts/kconfig/lxdialog/textbox.c b/scripts/kconfig/lxdialog/textbox.c new file mode 100644 index 0000000000..1773319b95 --- /dev/null +++ b/scripts/kconfig/lxdialog/textbox.c @@ -0,0 +1,408 @@ +/* + * textbox.c -- implements the text box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +static void back_lines(int n); +static void print_page(WINDOW *win, int height, int width, update_text_fn + update_text, void *data); +static void print_line(WINDOW *win, int row, int width); +static char *get_line(void); +static void print_position(WINDOW * win); + +static int hscroll; +static int begin_reached, end_reached, page_length; +static char *buf; +static char *page; + +/* + * refresh window content + */ +static void refresh_text_box(WINDOW *dialog, WINDOW *box, int boxh, int boxw, + int cur_y, int cur_x, update_text_fn update_text, + void *data) +{ + print_page(box, boxh, boxw, update_text, data); + print_position(dialog); + wmove(dialog, cur_y, cur_x); /* Restore cursor position */ + wrefresh(dialog); +} + + +/* + * Display text from a file in a dialog box. + * + * keys is a null-terminated array + * update_text() may not add or remove any '\n' or '\0' in tbuf + */ +int dialog_textbox(const char *title, char *tbuf, int initial_height, + int initial_width, int *keys, int *_vscroll, int *_hscroll, + update_text_fn update_text, void *data) +{ + int i, x, y, cur_x, cur_y, key = 0; + int height, width, boxh, boxw; + WINDOW *dialog, *box; + bool done = false; + + begin_reached = 1; + end_reached = 0; + page_length = 0; + hscroll = 0; + buf = tbuf; + page = buf; /* page is pointer to start of page to be displayed */ + + if (_vscroll && *_vscroll) { + begin_reached = 0; + + for (i = 0; i < *_vscroll; i++) + get_line(); + } + if (_hscroll) + hscroll = *_hscroll; + +do_resize: + getmaxyx(stdscr, height, width); + if (height < TEXTBOX_HEIGTH_MIN || width < TEXTBOX_WIDTH_MIN) + return -ERRDISPLAYTOOSMALL; + if (initial_height != 0) + height = initial_height; + else + if (height > 4) + height -= 4; + else + height = 0; + if (initial_width != 0) + width = initial_width; + else + if (width > 5) + width -= 5; + else + width = 0; + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + /* Create window for box region, used for scrolling text */ + boxh = height - 4; + boxw = width - 2; + box = subwin(dialog, boxh, boxw, y + 1, x + 1); + wattrset(box, dlg.dialog.atr); + wbkgdset(box, dlg.dialog.atr & A_COLOR); + + keypad(box, TRUE); + + /* register the new window, along with its borders */ + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + wbkgdset(dialog, dlg.dialog.atr & A_COLOR); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + print_button(dialog, gettext(" Exit "), height - 2, width / 2 - 4, TRUE); + wnoutrefresh(dialog); + getyx(dialog, cur_y, cur_x); /* Save cursor position */ + + /* Print first page of text */ + attr_clear(box, boxh, boxw, dlg.dialog.atr); + refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x, update_text, + data); + + while (!done) { + key = wgetch(dialog); + switch (key) { + case 'E': /* Exit */ + case 'e': + case 'X': + case 'x': + case 'q': + case '\n': + done = true; + break; + case 'g': /* First page */ + case KEY_HOME: + if (!begin_reached) { + begin_reached = 1; + page = buf; + refresh_text_box(dialog, box, boxh, boxw, + cur_y, cur_x, update_text, + data); + } + break; + case 'G': /* Last page */ + case KEY_END: + + end_reached = 1; + /* point to last char in buf */ + page = buf + strlen(buf); + back_lines(boxh); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case 'K': /* Previous line */ + case 'k': + case KEY_UP: + if (begin_reached) + break; + + back_lines(page_length + 1); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case 'B': /* Previous page */ + case 'b': + case 'u': + case KEY_PPAGE: + if (begin_reached) + break; + back_lines(page_length + boxh); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case 'J': /* Next line */ + case 'j': + case KEY_DOWN: + if (end_reached) + break; + + back_lines(page_length - 1); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case KEY_NPAGE: /* Next page */ + case ' ': + case 'd': + if (end_reached) + break; + + begin_reached = 0; + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case '0': /* Beginning of line */ + case 'H': /* Scroll left */ + case 'h': + case KEY_LEFT: + if (hscroll <= 0) + break; + + if (key == '0') + hscroll = 0; + else + hscroll--; + /* Reprint current page to scroll horizontally */ + back_lines(page_length); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case 'L': /* Scroll right */ + case 'l': + case KEY_RIGHT: + if (hscroll >= MAX_LEN) + break; + hscroll++; + /* Reprint current page to scroll horizontally */ + back_lines(page_length); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case KEY_ESC: + if (on_key_esc(dialog) == KEY_ESC) + done = true; + break; + case KEY_RESIZE: + back_lines(height); + delwin(box); + delwin(dialog); + on_key_resize(); + goto do_resize; + default: + for (i = 0; keys[i]; i++) { + if (key == keys[i]) { + done = true; + break; + } + } + } + } + delwin(box); + delwin(dialog); + if (_vscroll) { + const char *s; + + s = buf; + *_vscroll = 0; + back_lines(page_length); + while (s < page && (s = strchr(s, '\n'))) { + (*_vscroll)++; + s++; + } + } + if (_hscroll) + *_hscroll = hscroll; + return key; +} + +/* + * Go back 'n' lines in text. Called by dialog_textbox(). + * 'page' will be updated to point to the desired line in 'buf'. + */ +static void back_lines(int n) +{ + int i; + + begin_reached = 0; + /* Go back 'n' lines */ + for (i = 0; i < n; i++) { + if (*page == '\0') { + if (end_reached) { + end_reached = 0; + continue; + } + } + if (page == buf) { + begin_reached = 1; + return; + } + page--; + do { + if (page == buf) { + begin_reached = 1; + return; + } + page--; + } while (*page != '\n'); + page++; + } +} + +/* + * Print a new page of text. + */ +static void print_page(WINDOW *win, int height, int width, update_text_fn + update_text, void *data) +{ + int i, passed_end = 0; + + if (update_text) { + char *end; + + for (i = 0; i < height; i++) + get_line(); + end = page; + back_lines(height); + update_text(buf, page - buf, end - buf, data); + } + + page_length = 0; + for (i = 0; i < height; i++) { + print_line(win, i, width); + if (!passed_end) + page_length++; + if (end_reached && !passed_end) + passed_end = 1; + } + wnoutrefresh(win); +} + +/* + * Print a new line of text. + */ +static void print_line(WINDOW * win, int row, int width) +{ + char *line; + + line = get_line(); + line += MIN(strlen(line), hscroll); /* Scroll horizontally */ + wmove(win, row, 0); /* move cursor to correct line */ + waddch(win, ' '); + waddnstr(win, line, MIN(strlen(line), width - 2)); + + /* Clear 'residue' of previous line */ +#if OLD_NCURSES + { + int x = getcurx(win); + int i; + for (i = 0; i < width - x; i++) + waddch(win, ' '); + } +#else + wclrtoeol(win); +#endif +} + +/* + * Return current line of text. Called by dialog_textbox() and print_line(). + * 'page' should point to start of current line before calling, and will be + * updated to point to start of next line. + */ +static char *get_line(void) +{ + int i = 0; + static char line[MAX_LEN + 1]; + + end_reached = 0; + while (*page != '\n') { + if (*page == '\0') { + end_reached = 1; + break; + } else if (i < MAX_LEN) + line[i++] = *(page++); + else { + /* Truncate lines longer than MAX_LEN characters */ + if (i == MAX_LEN) + line[i++] = '\0'; + page++; + } + } + if (i <= MAX_LEN) + line[i] = '\0'; + if (!end_reached) + page++; /* move past '\n' */ + + return line; +} + +/* + * Print current position + */ +static void print_position(WINDOW * win) +{ + int percent; + + wattrset(win, dlg.position_indicator.atr); + wbkgdset(win, dlg.position_indicator.atr & A_COLOR); + percent = (page - buf) * 100 / strlen(buf); + wmove(win, getmaxy(win) - 3, getmaxx(win) - 9); + wprintw(win, "(%3d%%)", percent); +} diff --git a/scripts/kconfig/lxdialog/util.c b/scripts/kconfig/lxdialog/util.c new file mode 100644 index 0000000000..f7abdeb92a --- /dev/null +++ b/scripts/kconfig/lxdialog/util.c @@ -0,0 +1,713 @@ +/* + * util.c + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#include "dialog.h" + +/* Needed in signal handler in mconf.c */ +int saved_x, saved_y; + +struct dialog_info dlg; + +static void set_mono_theme(void) +{ + dlg.screen.atr = A_NORMAL; + dlg.shadow.atr = A_NORMAL; + dlg.dialog.atr = A_NORMAL; + dlg.title.atr = A_BOLD; + dlg.border.atr = A_NORMAL; + dlg.button_active.atr = A_REVERSE; + dlg.button_inactive.atr = A_DIM; + dlg.button_key_active.atr = A_REVERSE; + dlg.button_key_inactive.atr = A_BOLD; + dlg.button_label_active.atr = A_REVERSE; + dlg.button_label_inactive.atr = A_NORMAL; + dlg.inputbox.atr = A_NORMAL; + dlg.inputbox_border.atr = A_NORMAL; + dlg.searchbox.atr = A_NORMAL; + dlg.searchbox_title.atr = A_BOLD; + dlg.searchbox_border.atr = A_NORMAL; + dlg.position_indicator.atr = A_BOLD; + dlg.menubox.atr = A_NORMAL; + dlg.menubox_border.atr = A_NORMAL; + dlg.item.atr = A_NORMAL; + dlg.item_selected.atr = A_REVERSE; + dlg.tag.atr = A_BOLD; + dlg.tag_selected.atr = A_REVERSE; + dlg.tag_key.atr = A_BOLD; + dlg.tag_key_selected.atr = A_REVERSE; + dlg.check.atr = A_BOLD; + dlg.check_selected.atr = A_REVERSE; + dlg.uarrow.atr = A_BOLD; + dlg.darrow.atr = A_BOLD; +} + +#define DLG_COLOR(dialog, f, b, h) \ +do { \ + dlg.dialog.fg = (f); \ + dlg.dialog.bg = (b); \ + dlg.dialog.hl = (h); \ +} while (0) + +static void set_classic_theme(void) +{ + DLG_COLOR(screen, COLOR_CYAN, COLOR_BLUE, true); + DLG_COLOR(shadow, COLOR_BLACK, COLOR_BLACK, true); + DLG_COLOR(dialog, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(title, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(border, COLOR_WHITE, COLOR_WHITE, true); + DLG_COLOR(button_active, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(button_inactive, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(button_key_active, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(button_key_inactive, COLOR_RED, COLOR_WHITE, false); + DLG_COLOR(button_label_active, COLOR_YELLOW, COLOR_BLUE, true); + DLG_COLOR(button_label_inactive, COLOR_BLACK, COLOR_WHITE, true); + DLG_COLOR(inputbox, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(inputbox_border, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(searchbox, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(searchbox_title, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(searchbox_border, COLOR_WHITE, COLOR_WHITE, true); + DLG_COLOR(position_indicator, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(menubox, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(menubox_border, COLOR_WHITE, COLOR_WHITE, true); + DLG_COLOR(item, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(item_selected, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(tag, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(tag_selected, COLOR_YELLOW, COLOR_BLUE, true); + DLG_COLOR(tag_key, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(tag_key_selected, COLOR_YELLOW, COLOR_BLUE, true); + DLG_COLOR(check, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(check_selected, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(uarrow, COLOR_GREEN, COLOR_WHITE, true); + DLG_COLOR(darrow, COLOR_GREEN, COLOR_WHITE, true); +} + +static void set_blackbg_theme(void) +{ + DLG_COLOR(screen, COLOR_RED, COLOR_BLACK, true); + DLG_COLOR(shadow, COLOR_BLACK, COLOR_BLACK, false); + DLG_COLOR(dialog, COLOR_WHITE, COLOR_BLACK, false); + DLG_COLOR(title, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(border, COLOR_BLACK, COLOR_BLACK, true); + + DLG_COLOR(button_active, COLOR_YELLOW, COLOR_RED, false); + DLG_COLOR(button_inactive, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(button_key_active, COLOR_YELLOW, COLOR_RED, true); + DLG_COLOR(button_key_inactive, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(button_label_active, COLOR_WHITE, COLOR_RED, false); + DLG_COLOR(button_label_inactive, COLOR_BLACK, COLOR_BLACK, true); + + DLG_COLOR(inputbox, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(inputbox_border, COLOR_YELLOW, COLOR_BLACK, false); + + DLG_COLOR(searchbox, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(searchbox_title, COLOR_YELLOW, COLOR_BLACK, true); + DLG_COLOR(searchbox_border, COLOR_BLACK, COLOR_BLACK, true); + + DLG_COLOR(position_indicator, COLOR_RED, COLOR_BLACK, false); + + DLG_COLOR(menubox, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(menubox_border, COLOR_BLACK, COLOR_BLACK, true); + + DLG_COLOR(item, COLOR_WHITE, COLOR_BLACK, false); + DLG_COLOR(item_selected, COLOR_WHITE, COLOR_RED, false); + + DLG_COLOR(tag, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(tag_selected, COLOR_YELLOW, COLOR_RED, true); + DLG_COLOR(tag_key, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(tag_key_selected, COLOR_YELLOW, COLOR_RED, true); + + DLG_COLOR(check, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(check_selected, COLOR_YELLOW, COLOR_RED, true); + + DLG_COLOR(uarrow, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(darrow, COLOR_RED, COLOR_BLACK, false); +} + +static void set_bluetitle_theme(void) +{ + set_classic_theme(); + DLG_COLOR(title, COLOR_BLUE, COLOR_WHITE, true); + DLG_COLOR(button_key_active, COLOR_YELLOW, COLOR_BLUE, true); + DLG_COLOR(button_label_active, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(searchbox_title, COLOR_BLUE, COLOR_WHITE, true); + DLG_COLOR(position_indicator, COLOR_BLUE, COLOR_WHITE, true); + DLG_COLOR(tag, COLOR_BLUE, COLOR_WHITE, true); + DLG_COLOR(tag_key, COLOR_BLUE, COLOR_WHITE, true); + +} + +/* + * Select color theme + */ +static int set_theme(const char *theme) +{ + int use_color = 1; + if (!theme) + set_bluetitle_theme(); + else if (strcmp(theme, "classic") == 0) + set_classic_theme(); + else if (strcmp(theme, "bluetitle") == 0) + set_bluetitle_theme(); + else if (strcmp(theme, "blackbg") == 0) + set_blackbg_theme(); + else if (strcmp(theme, "mono") == 0) + use_color = 0; + + return use_color; +} + +static void init_one_color(struct dialog_color *color) +{ + static int pair = 0; + + pair++; + init_pair(pair, color->fg, color->bg); + if (color->hl) + color->atr = A_BOLD | COLOR_PAIR(pair); + else + color->atr = COLOR_PAIR(pair); +} + +static void init_dialog_colors(void) +{ + init_one_color(&dlg.screen); + init_one_color(&dlg.shadow); + init_one_color(&dlg.dialog); + init_one_color(&dlg.title); + init_one_color(&dlg.border); + init_one_color(&dlg.button_active); + init_one_color(&dlg.button_inactive); + init_one_color(&dlg.button_key_active); + init_one_color(&dlg.button_key_inactive); + init_one_color(&dlg.button_label_active); + init_one_color(&dlg.button_label_inactive); + init_one_color(&dlg.inputbox); + init_one_color(&dlg.inputbox_border); + init_one_color(&dlg.searchbox); + init_one_color(&dlg.searchbox_title); + init_one_color(&dlg.searchbox_border); + init_one_color(&dlg.position_indicator); + init_one_color(&dlg.menubox); + init_one_color(&dlg.menubox_border); + init_one_color(&dlg.item); + init_one_color(&dlg.item_selected); + init_one_color(&dlg.tag); + init_one_color(&dlg.tag_selected); + init_one_color(&dlg.tag_key); + init_one_color(&dlg.tag_key_selected); + init_one_color(&dlg.check); + init_one_color(&dlg.check_selected); + init_one_color(&dlg.uarrow); + init_one_color(&dlg.darrow); +} + +/* + * Setup for color display + */ +static void color_setup(const char *theme) +{ + int use_color; + + use_color = set_theme(theme); + if (use_color && has_colors()) { + start_color(); + init_dialog_colors(); + } else + set_mono_theme(); +} + +/* + * Set window to attribute 'attr' + */ +void attr_clear(WINDOW * win, int height, int width, chtype attr) +{ + int i, j; + + wattrset(win, attr); + for (i = 0; i < height; i++) { + wmove(win, i, 0); + for (j = 0; j < width; j++) + waddch(win, ' '); + } + touchwin(win); +} + +void dialog_clear(void) +{ + int lines, columns; + + lines = getmaxy(stdscr); + columns = getmaxx(stdscr); + + attr_clear(stdscr, lines, columns, dlg.screen.atr); + /* Display background title if it exists ... - SLH */ + if (dlg.backtitle != NULL) { + int i, len = 0, skip = 0; + struct subtitle_list *pos; + + wattrset(stdscr, dlg.screen.atr); + mvwaddstr(stdscr, 0, 1, (char *)dlg.backtitle); + + for (pos = dlg.subtitles; pos != NULL; pos = pos->next) { + /* 3 is for the arrow and spaces */ + len += strlen(pos->text) + 3; + } + + wmove(stdscr, 1, 1); + if (len > columns - 2) { + const char *ellipsis = "[...] "; + waddstr(stdscr, ellipsis); + skip = len - (columns - 2 - strlen(ellipsis)); + } + + for (pos = dlg.subtitles; pos != NULL; pos = pos->next) { + if (skip == 0) + waddch(stdscr, ACS_RARROW); + else + skip--; + + if (skip == 0) + waddch(stdscr, ' '); + else + skip--; + + if (skip < strlen(pos->text)) { + waddstr(stdscr, pos->text + skip); + skip = 0; + } else + skip -= strlen(pos->text); + + if (skip == 0) + waddch(stdscr, ' '); + else + skip--; + } + + for (i = len + 1; i < columns - 1; i++) + waddch(stdscr, ACS_HLINE); + } + wnoutrefresh(stdscr); +} + +/* + * Do some initialization for dialog + */ +int init_dialog(const char *backtitle) +{ + int height, width; + + initscr(); /* Init curses */ + + /* Get current cursor position for signal handler in mconf.c */ + getyx(stdscr, saved_y, saved_x); + + getmaxyx(stdscr, height, width); + if (height < WINDOW_HEIGTH_MIN || width < WINDOW_WIDTH_MIN) { + endwin(); + return -ERRDISPLAYTOOSMALL; + } + + dlg.backtitle = backtitle; + color_setup(getenv("MENUCONFIG_COLOR")); + + keypad(stdscr, TRUE); + cbreak(); + noecho(); + dialog_clear(); + + return 0; +} + +void set_dialog_backtitle(const char *backtitle) +{ + dlg.backtitle = backtitle; +} + +void set_dialog_subtitles(struct subtitle_list *subtitles) +{ + dlg.subtitles = subtitles; +} + +/* + * End using dialog functions. + */ +void end_dialog(int x, int y) +{ + /* move cursor back to original position */ + move(y, x); + refresh(); + endwin(); +} + +/* Print the title of the dialog. Center the title and truncate + * tile if wider than dialog (- 2 chars). + **/ +void print_title(WINDOW *dialog, const char *title, int width) +{ + if (title) { + int tlen = MIN(width - 2, strlen(title)); + wattrset(dialog, dlg.title.atr); + mvwaddch(dialog, 0, (width - tlen) / 2 - 1, ' '); + mvwaddnstr(dialog, 0, (width - tlen)/2, title, tlen); + waddch(dialog, ' '); + } +} + +/* + * Print a string of text in a window, automatically wrap around to the + * next line if the string is too long to fit on one line. Newline + * characters '\n' are propperly processed. We start on a new line + * if there is no room for at least 4 nonblanks following a double-space. + */ +void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x) +{ + int newl, cur_x, cur_y; + int prompt_len, room, wlen; + char tempstr[MAX_LEN + 1], *word, *sp, *sp2, *newline_separator = 0; + + strcpy(tempstr, prompt); + + prompt_len = strlen(tempstr); + + if (prompt_len <= width - x * 2) { /* If prompt is short */ + wmove(win, y, (width - prompt_len) / 2); + waddstr(win, tempstr); + } else { + cur_x = x; + cur_y = y; + newl = 1; + word = tempstr; + while (word && *word) { + sp = strpbrk(word, "\n "); + if (sp && *sp == '\n') + newline_separator = sp; + + if (sp) + *sp++ = 0; + + /* Wrap to next line if either the word does not fit, + or it is the first word of a new sentence, and it is + short, and the next word does not fit. */ + room = width - cur_x; + wlen = strlen(word); + if (wlen > room || + (newl && wlen < 4 && sp + && wlen + 1 + strlen(sp) > room + && (!(sp2 = strpbrk(sp, "\n ")) + || wlen + 1 + (sp2 - sp) > room))) { + cur_y++; + cur_x = x; + } + wmove(win, cur_y, cur_x); + waddstr(win, word); + getyx(win, cur_y, cur_x); + + /* Move to the next line if the word separator was a newline */ + if (newline_separator) { + cur_y++; + cur_x = x; + newline_separator = 0; + } else + cur_x++; + + if (sp && *sp == ' ') { + cur_x++; /* double space */ + while (*++sp == ' ') ; + newl = 1; + } else + newl = 0; + word = sp; + } + } +} + +/* + * Print a button + */ +void print_button(WINDOW * win, const char *label, int y, int x, int selected) +{ + int i, temp; + + wmove(win, y, x); + wattrset(win, selected ? dlg.button_active.atr + : dlg.button_inactive.atr); + waddstr(win, "<"); + temp = strspn(label, " "); + label += temp; + wattrset(win, selected ? dlg.button_label_active.atr + : dlg.button_label_inactive.atr); + for (i = 0; i < temp; i++) + waddch(win, ' '); + wattrset(win, selected ? dlg.button_key_active.atr + : dlg.button_key_inactive.atr); + waddch(win, label[0]); + wattrset(win, selected ? dlg.button_label_active.atr + : dlg.button_label_inactive.atr); + waddstr(win, (char *)label + 1); + wattrset(win, selected ? dlg.button_active.atr + : dlg.button_inactive.atr); + waddstr(win, ">"); + wmove(win, y, x + temp + 1); +} + +/* + * Draw a rectangular box with line drawing characters + */ +void +draw_box(WINDOW * win, int y, int x, int height, int width, + chtype box, chtype border) +{ + int i, j; + + wattrset(win, 0); + for (i = 0; i < height; i++) { + wmove(win, y + i, x); + for (j = 0; j < width; j++) + if (!i && !j) + waddch(win, border | ACS_ULCORNER); + else if (i == height - 1 && !j) + waddch(win, border | ACS_LLCORNER); + else if (!i && j == width - 1) + waddch(win, box | ACS_URCORNER); + else if (i == height - 1 && j == width - 1) + waddch(win, box | ACS_LRCORNER); + else if (!i) + waddch(win, border | ACS_HLINE); + else if (i == height - 1) + waddch(win, box | ACS_HLINE); + else if (!j) + waddch(win, border | ACS_VLINE); + else if (j == width - 1) + waddch(win, box | ACS_VLINE); + else + waddch(win, box | ' '); + } +} + +/* + * Draw shadows along the right and bottom edge to give a more 3D look + * to the boxes + */ +void draw_shadow(WINDOW * win, int y, int x, int height, int width) +{ + int i; + + if (has_colors()) { /* Whether terminal supports color? */ + wattrset(win, dlg.shadow.atr); + wmove(win, y + height, x + 2); + for (i = 0; i < width; i++) + waddch(win, winch(win) & A_CHARTEXT); + for (i = y + 1; i < y + height + 1; i++) { + wmove(win, i, x + width); + waddch(win, winch(win) & A_CHARTEXT); + waddch(win, winch(win) & A_CHARTEXT); + } + wnoutrefresh(win); + } +} + +/* + * Return the position of the first alphabetic character in a string. + */ +int first_alpha(const char *string, const char *exempt) +{ + int i, in_paren = 0, c; + + for (i = 0; i < strlen(string); i++) { + c = tolower(string[i]); + + if (strchr("<[(", c)) + ++in_paren; + if (strchr(">])", c) && in_paren > 0) + --in_paren; + + if ((!in_paren) && isalpha(c) && strchr(exempt, c) == 0) + return i; + } + + return 0; +} + +/* + * ncurses uses ESC to detect escaped char sequences. This resutl in + * a small timeout before ESC is actually delivered to the application. + * lxdialog suggest which is correctly translated to two + * times esc. But then we need to ignore the second esc to avoid stepping + * out one menu too much. Filter away all escaped key sequences since + * keypad(FALSE) turn off ncurses support for escape sequences - and thats + * needed to make notimeout() do as expected. + */ +int on_key_esc(WINDOW *win) +{ + int key; + int key2; + int key3; + + nodelay(win, TRUE); + keypad(win, FALSE); + key = wgetch(win); + key2 = wgetch(win); + do { + key3 = wgetch(win); + } while (key3 != ERR); + nodelay(win, FALSE); + keypad(win, TRUE); + if (key == KEY_ESC && key2 == ERR) + return KEY_ESC; + else if (key != ERR && key != KEY_ESC && key2 == ERR) + ungetch(key); + + return -1; +} + +/* redraw screen in new size */ +int on_key_resize(void) +{ + dialog_clear(); + return KEY_RESIZE; +} + +struct dialog_list *item_cur; +struct dialog_list item_nil; +struct dialog_list *item_head; + +void item_reset(void) +{ + struct dialog_list *p, *next; + + for (p = item_head; p; p = next) { + next = p->next; + free(p); + } + item_head = NULL; + item_cur = &item_nil; +} + +void item_make(const char *fmt, ...) +{ + va_list ap; + struct dialog_list *p = malloc(sizeof(*p)); + + if (item_head) + item_cur->next = p; + else + item_head = p; + item_cur = p; + memset(p, 0, sizeof(*p)); + + va_start(ap, fmt); + vsnprintf(item_cur->node.str, sizeof(item_cur->node.str), fmt, ap); + va_end(ap); +} + +void item_add_str(const char *fmt, ...) +{ + va_list ap; + size_t avail; + + avail = sizeof(item_cur->node.str) - strlen(item_cur->node.str); + + va_start(ap, fmt); + vsnprintf(item_cur->node.str + strlen(item_cur->node.str), + avail, fmt, ap); + item_cur->node.str[sizeof(item_cur->node.str) - 1] = '\0'; + va_end(ap); +} + +void item_set_tag(char tag) +{ + item_cur->node.tag = tag; +} +void item_set_data(void *ptr) +{ + item_cur->node.data = ptr; +} + +void item_set_selected(int val) +{ + item_cur->node.selected = val; +} + +int item_activate_selected(void) +{ + item_foreach() + if (item_is_selected()) + return 1; + return 0; +} + +void *item_data(void) +{ + return item_cur->node.data; +} + +char item_tag(void) +{ + return item_cur->node.tag; +} + +int item_count(void) +{ + int n = 0; + struct dialog_list *p; + + for (p = item_head; p; p = p->next) + n++; + return n; +} + +void item_set(int n) +{ + int i = 0; + item_foreach() + if (i++ == n) + return; +} + +int item_n(void) +{ + int n = 0; + struct dialog_list *p; + + for (p = item_head; p; p = p->next) { + if (p == item_cur) + return n; + n++; + } + return 0; +} + +const char *item_str(void) +{ + return item_cur->node.str; +} + +int item_is_selected(void) +{ + return (item_cur->node.selected != 0); +} + +int item_is_tag(char tag) +{ + return (item_cur->node.tag == tag); +} diff --git a/scripts/kconfig/lxdialog/yesno.c b/scripts/kconfig/lxdialog/yesno.c new file mode 100644 index 0000000000..676fb2f824 --- /dev/null +++ b/scripts/kconfig/lxdialog/yesno.c @@ -0,0 +1,114 @@ +/* + * yesno.c -- implements the yes/no box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +/* + * Display termination buttons + */ +static void print_buttons(WINDOW * dialog, int height, int width, int selected) +{ + int x = width / 2 - 10; + int y = height - 2; + + print_button(dialog, gettext(" Yes "), y, x, selected == 0); + print_button(dialog, gettext(" No "), y, x + 13, selected == 1); + + wmove(dialog, y, x + 1 + 13 * selected); + wrefresh(dialog); +} + +/* + * Display a dialog box with two buttons - Yes and No + */ +int dialog_yesno(const char *title, const char *prompt, int height, int width) +{ + int i, x, y, key = 0, button = 0; + WINDOW *dialog; + +do_resize: + if (getmaxy(stdscr) < (height + YESNO_HEIGTH_MIN)) + return -ERRDISPLAYTOOSMALL; + if (getmaxx(stdscr) < (width + YESNO_WIDTH_MIN)) + return -ERRDISPLAYTOOSMALL; + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + wattrset(dialog, dlg.dialog.atr); + print_autowrap(dialog, prompt, width - 2, 1, 3); + + print_buttons(dialog, height, width, 0); + + while (key != KEY_ESC) { + key = wgetch(dialog); + switch (key) { + case 'Y': + case 'y': + delwin(dialog); + return 0; + case 'N': + case 'n': + delwin(dialog); + return 1; + + case TAB: + case KEY_LEFT: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) ? 1 : (button > 1 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh(dialog); + break; + case ' ': + case '\n': + delwin(dialog); + return button; + case KEY_ESC: + key = on_key_esc(dialog); + break; + case KEY_RESIZE: + delwin(dialog); + on_key_resize(); + goto do_resize; + } + } + + delwin(dialog); + return key; /* ESC pressed */ +} diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c new file mode 100644 index 0000000000..14cea7463a --- /dev/null +++ b/scripts/kconfig/mconf.c @@ -0,0 +1,1036 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + * + * Introduced single menu mode (show all sub-menus in one large tree). + * 2002-11-06 Petr Baudis + * + * i18n, 2005, Arnaldo Carvalho de Melo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lkc.h" +#include "lxdialog/dialog.h" + +static const char mconf_readme[] = N_( +"Overview\n" +"--------\n" +"This interface lets you select features and parameters for the build.\n" +"Features can either be built-in, modularized, or ignored. Parameters\n" +"must be entered in as decimal or hexadecimal numbers or text.\n" +"\n" +"Menu items beginning with following braces represent features that\n" +" [ ] can be built in or removed\n" +" < > can be built in, modularized or removed\n" +" { } can be built in or modularized (selected by other feature)\n" +" - - are selected by other feature,\n" +"while *, M or whitespace inside braces means to build in, build as\n" +"a module or to exclude the feature respectively.\n" +"\n" +"To change any of these features, highlight it with the cursor\n" +"keys and press to build it in, to make it a module or\n" +" to remove it. You may also press the to cycle\n" +"through the available options (i.e. Y->N->M->Y).\n" +"\n" +"Some additional keyboard hints:\n" +"\n" +"Menus\n" +"----------\n" +"o Use the Up/Down arrow keys (cursor keys) to highlight the item you\n" +" wish to change or the submenu you wish to select and press .\n" +" Submenus are designated by \"--->\", empty ones by \"----\".\n" +"\n" +" Shortcut: Press the option's highlighted letter (hotkey).\n" +" Pressing a hotkey more than once will sequence\n" +" through all visible items which use that hotkey.\n" +"\n" +" You may also use the and keys to scroll\n" +" unseen options into view.\n" +"\n" +"o To exit a menu use the cursor keys to highlight the button\n" +" and press .\n" +"\n" +" Shortcut: Press or or if there is no hotkey\n" +" using those letters. You may press a single , but\n" +" there is a delayed response which you may find annoying.\n" +"\n" +" Also, the and cursor keys will cycle between and\n" +" \n" +"\n" +"\n" +"Data Entry\n" +"-----------\n" +"o Enter the requested information and press \n" +" If you are entering hexadecimal values, it is not necessary to\n" +" add the '0x' prefix to the entry.\n" +"\n" +"o For help, use the or cursor keys to highlight the help option\n" +" and press . You can try as well.\n" +"\n" +"\n" +"Text Box (Help Window)\n" +"--------\n" +"o Use the cursor keys to scroll up/down/left/right. The VI editor\n" +" keys h,j,k,l function here as do , , and for\n" +" those who are familiar with less and lynx.\n" +"\n" +"o Press , , , or to exit.\n" +"\n" +"\n" +"Alternate Configuration Files\n" +"-----------------------------\n" +"Menuconfig supports the use of alternate configuration files for\n" +"those who, for various reasons, find it necessary to switch\n" +"between different configurations.\n" +"\n" +"The button will let you save the current configuration to\n" +"a file of your choosing. Use the button to load a previously\n" +"saved alternate configuration.\n" +"\n" +"Even if you don't use alternate configuration files, but you find\n" +"during a Menuconfig session that you have completely messed up your\n" +"settings, you may use the button to restore your previously\n" +"saved settings from \".config\" without restarting Menuconfig.\n" +"\n" +"Other information\n" +"-----------------\n" +"If you use Menuconfig in an XTERM window, make sure you have your\n" +"$TERM variable set to point to an xterm definition which supports\n" +"color. Otherwise, Menuconfig will look rather bad. Menuconfig will\n" +"not display correctly in an RXVT window because rxvt displays only one\n" +"intensity of color, bright.\n" +"\n" +"Menuconfig will display larger menus on screens or xterms which are\n" +"set to display more than the standard 25 row by 80 column geometry.\n" +"In order for this to work, the \"stty size\" command must be able to\n" +"display the screen's current row and column geometry. I STRONGLY\n" +"RECOMMEND that you make sure you do NOT have the shell variables\n" +"LINES and COLUMNS exported into your environment. Some distributions\n" +"export those variables via /etc/profile. Some ncurses programs can\n" +"become confused when those variables (LINES & COLUMNS) don't reflect\n" +"the true screen size.\n" +"\n" +"Optional personality available\n" +"------------------------------\n" +"If you prefer to have all of the options listed in a single menu,\n" +"rather than the default multimenu hierarchy, run the menuconfig with\n" +"MENUCONFIG_MODE environment variable set to single_menu. Example:\n" +"\n" +"make MENUCONFIG_MODE=single_menu menuconfig\n" +"\n" +" will then unroll the appropriate category, or enfold it if it\n" +"is already unrolled.\n" +"\n" +"Note that this mode can eventually be a little more CPU expensive\n" +"(especially with a larger number of unrolled categories) than the\n" +"default mode.\n" +"\n" +"Different color themes available\n" +"--------------------------------\n" +"It is possible to select different color themes using the variable\n" +"MENUCONFIG_COLOR. To select a theme use:\n" +"\n" +"make MENUCONFIG_COLOR= menuconfig\n" +"\n" +"Available themes are\n" +" mono => selects colors suitable for monochrome displays\n" +" blackbg => selects a color scheme with black background\n" +" classic => theme with blue background. The classic look\n" +" bluetitle => an LCD friendly version of classic. (default)\n" +"\n"), +menu_instructions[] = N_( + "Arrow keys navigate the menu. " + " selects submenus ---> (or empty submenus ----). " + "Highlighted letters are hotkeys. " + "Pressing includes, excludes, modularizes features. " + "Press to exit, for Help, for Search. " + "Legend: [*] built-in [ ] excluded module < > module capable"), +radiolist_instructions[] = N_( + "Use the arrow keys to navigate this window or " + "press the hotkey of the item you wish to select " + "followed by the . " + "Press for additional information about this option."), +inputbox_instructions_int[] = N_( + "Please enter a decimal value. " + "Fractions will not be accepted. " + "Use the key to move from the input field to the buttons below it."), +inputbox_instructions_hex[] = N_( + "Please enter a hexadecimal value. " + "Use the key to move from the input field to the buttons below it."), +inputbox_instructions_string[] = N_( + "Please enter a string value. " + "Use the key to move from the input field to the buttons below it."), +setmod_text[] = N_( + "This feature depends on another which has been configured as a module.\n" + "As a result, this feature will be built as a module."), +load_config_text[] = N_( + "Enter the name of the configuration file you wish to load. " + "Accept the name shown to restore the configuration you " + "last retrieved. Leave blank to abort."), +load_config_help[] = N_( + "\n" + "For various reasons, one may wish to keep several different\n" + "configurations available on a single machine.\n" + "\n" + "If you have saved a previous configuration in a file other than the\n" + "default one, entering its name here will allow you to modify that\n" + "configuration.\n" + "\n" + "If you are uncertain, then you have probably never used alternate\n" + "configuration files. You should therefore leave this blank to abort.\n"), +save_config_text[] = N_( + "Enter a filename to which this configuration should be saved " + "as an alternate. Leave blank to abort."), +save_config_help[] = N_( + "\n" + "For various reasons, one may wish to keep different configurations\n" + "available on a single machine.\n" + "\n" + "Entering a file name here will allow you to later retrieve, modify\n" + "and use the current configuration as an alternate to whatever\n" + "configuration options you have selected at that time.\n" + "\n" + "If you are uncertain what all this means then you should probably\n" + "leave this blank.\n"), +search_help[] = N_( + "\n" + "Search for symbols and display their relations.\n" + "Regular expressions are allowed.\n" + "Example: search for \"^FOO\"\n" + "Result:\n" + "-----------------------------------------------------------------\n" + "Symbol: FOO [=m]\n" + "Type : tristate\n" + "Prompt: Foo bus is used to drive the bar HW\n" + " Location:\n" + " -> Bus options (PCI, PCMCIA, EISA, ISA)\n" + " -> PCI support (PCI [=y])\n" + "(1) -> PCI access mode ( [=y])\n" + " Defined at drivers/pci/Kconfig:47\n" + " Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n" + " Selects: LIBCRC32\n" + " Selected by: BAR [=n]\n" + "-----------------------------------------------------------------\n" + "o The line 'Type:' shows the type of the configuration option for\n" + " this symbol (boolean, tristate, string, ...)\n" + "o The line 'Prompt:' shows the text used in the menu structure for\n" + " this symbol\n" + "o The 'Defined at' line tells at what file / line number the symbol\n" + " is defined\n" + "o The 'Depends on:' line tells what symbols need to be defined for\n" + " this symbol to be visible in the menu (selectable)\n" + "o The 'Location:' lines tells where in the menu structure this symbol\n" + " is located\n" + " A location followed by a [=y] indicates that this is a\n" + " selectable menu item - and the current value is displayed inside\n" + " brackets.\n" + " Press the key in the (#) prefix to jump directly to that\n" + " location. You will be returned to the current search results\n" + " after exiting this new menu.\n" + "o The 'Selects:' line tells what symbols will be automatically\n" + " selected if this symbol is selected (y or m)\n" + "o The 'Selected by' line tells what symbol has selected this symbol\n" + "\n" + "Only relevant lines are shown.\n" + "\n\n" + "Search examples:\n" + "Examples: USB => find all symbols containing USB\n" + " ^USB => find all symbols starting with USB\n" + " USB$ => find all symbols ending with USB\n" + "\n"); + +static int indent; +static struct menu *current_menu; +static int child_count; +static int single_menu_mode; +static int show_all_options; +static int save_and_exit; + +static void conf(struct menu *menu, struct menu *active_menu); +static void conf_choice(struct menu *menu); +static void conf_string(struct menu *menu); +static void conf_load(void); +static void conf_save(void); +static int show_textbox_ext(const char *title, char *text, int r, int c, + int *keys, int *vscroll, int *hscroll, + update_text_fn update_text, void *data); +static void show_textbox(const char *title, const char *text, int r, int c); +static void show_helptext(const char *title, const char *text); +static void show_help(struct menu *menu); + +static char filename[PATH_MAX+1]; +static void set_config_filename(const char *config_filename) +{ + static char menu_backtitle[PATH_MAX+128]; + int size; + + size = snprintf(menu_backtitle, sizeof(menu_backtitle), + "%s - %s", config_filename, rootmenu.prompt->text); + if (size >= sizeof(menu_backtitle)) + menu_backtitle[sizeof(menu_backtitle)-1] = '\0'; + set_dialog_backtitle(menu_backtitle); + + size = snprintf(filename, sizeof(filename), "%s", config_filename); + if (size >= sizeof(filename)) + filename[sizeof(filename)-1] = '\0'; +} + +struct subtitle_part { + struct list_head entries; + const char *text; +}; +static LIST_HEAD(trail); + +static struct subtitle_list *subtitles; +static void set_subtitle(void) +{ + struct subtitle_part *sp; + struct subtitle_list *pos, *tmp; + + for (pos = subtitles; pos != NULL; pos = tmp) { + tmp = pos->next; + free(pos); + } + + subtitles = NULL; + list_for_each_entry(sp, &trail, entries) { + if (sp->text) { + if (pos) { + pos->next = xcalloc(sizeof(*pos), 1); + pos = pos->next; + } else { + subtitles = pos = xcalloc(sizeof(*pos), 1); + } + pos->text = sp->text; + } + } + + set_dialog_subtitles(subtitles); +} + +static void reset_subtitle(void) +{ + struct subtitle_list *pos, *tmp; + + for (pos = subtitles; pos != NULL; pos = tmp) { + tmp = pos->next; + free(pos); + } + subtitles = NULL; + set_dialog_subtitles(subtitles); +} + +struct search_data { + struct list_head *head; + struct menu **targets; + int *keys; +}; + +static void update_text(char *buf, size_t start, size_t end, void *_data) +{ + struct search_data *data = _data; + struct jump_key *pos; + int k = 0; + + list_for_each_entry(pos, data->head, entries) { + if (pos->offset >= start && pos->offset < end) { + char header[4]; + + if (k < JUMP_NB) { + int key = '0' + (pos->index % JUMP_NB) + 1; + + sprintf(header, "(%c)", key); + data->keys[k] = key; + data->targets[k] = pos->target; + k++; + } else { + sprintf(header, " "); + } + + memcpy(buf + pos->offset, header, sizeof(header) - 1); + } + } + data->keys[k] = 0; +} + +static void search_conf(void) +{ + struct symbol **sym_arr; + struct gstr res; + struct gstr title; + char *dialog_input; + int dres, vscroll = 0, hscroll = 0; + bool again; + struct gstr sttext; + struct subtitle_part stpart; + + title = str_new(); + str_printf( &title, _("Enter (sub)string or regexp to search for " + "(with or without \"%s\")"), CONFIG_); + +again: + dialog_clear(); + dres = dialog_inputbox(_("Search Configuration Parameter"), + str_get(&title), + 10, 75, ""); + switch (dres) { + case 0: + break; + case 1: + show_helptext(_("Search Configuration"), search_help); + goto again; + default: + str_free(&title); + return; + } + + /* strip the prefix if necessary */ + dialog_input = dialog_input_result; + if (strncasecmp(dialog_input_result, CONFIG_, strlen(CONFIG_)) == 0) + dialog_input += strlen(CONFIG_); + + sttext = str_new(); + str_printf(&sttext, "Search (%s)", dialog_input_result); + stpart.text = str_get(&sttext); + list_add_tail(&stpart.entries, &trail); + + sym_arr = sym_re_search(dialog_input); + do { + LIST_HEAD(head); + struct menu *targets[JUMP_NB]; + int keys[JUMP_NB + 1], i; + struct search_data data = { + .head = &head, + .targets = targets, + .keys = keys, + }; + struct jump_key *pos, *tmp; + + res = get_relations_str(sym_arr, &head); + set_subtitle(); + dres = show_textbox_ext(_("Search Results"), (char *) + str_get(&res), 0, 0, keys, &vscroll, + &hscroll, &update_text, (void *) + &data); + again = false; + for (i = 0; i < JUMP_NB && keys[i]; i++) + if (dres == keys[i]) { + conf(targets[i]->parent, targets[i]); + again = true; + } + str_free(&res); + list_for_each_entry_safe(pos, tmp, &head, entries) + free(pos); + } while (again); + free(sym_arr); + str_free(&title); + list_del(trail.prev); + str_free(&sttext); +} + +static void build_conf(struct menu *menu) +{ + struct symbol *sym; + struct property *prop; + struct menu *child; + int type, tmp, doint = 2; + tristate val; + char ch; + bool visible; + + /* + * note: menu_is_visible() has side effect that it will + * recalc the value of the symbol. + */ + visible = menu_is_visible(menu); + if (show_all_options && !menu_has_prompt(menu)) + return; + else if (!show_all_options && !visible) + return; + + sym = menu->sym; + prop = menu->prompt; + if (!sym) { + if (prop && menu != current_menu) { + const char *prompt = menu_get_prompt(menu); + switch (prop->type) { + case P_MENU: + child_count++; + prompt = _(prompt); + if (single_menu_mode) { + item_make("%s%*c%s", + menu->data ? "-->" : "++>", + indent + 1, ' ', prompt); + } else + item_make(" %*c%s %s", + indent + 1, ' ', prompt, + menu_is_empty(menu) ? "----" : "--->"); + item_set_tag('m'); + item_set_data(menu); + if (single_menu_mode && menu->data) + goto conf_childs; + return; + case P_COMMENT: + if (prompt) { + child_count++; + item_make(" %*c*** %s ***", indent + 1, ' ', _(prompt)); + item_set_tag(':'); + item_set_data(menu); + } + break; + default: + if (prompt) { + child_count++; + item_make("---%*c%s", indent + 1, ' ', _(prompt)); + item_set_tag(':'); + item_set_data(menu); + } + } + } else + doint = 0; + goto conf_childs; + } + + type = sym_get_type(sym); + if (sym_is_choice(sym)) { + struct symbol *def_sym = sym_get_choice_value(sym); + struct menu *def_menu = NULL; + + child_count++; + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child) && child->sym == def_sym) + def_menu = child; + } + + val = sym_get_tristate_value(sym); + if (sym_is_changable(sym)) { + switch (type) { + case S_BOOLEAN: + item_make("[%c]", val == no ? ' ' : '*'); + break; + case S_TRISTATE: + switch (val) { + case yes: ch = '*'; break; + case mod: ch = 'M'; break; + default: ch = ' '; break; + } + item_make("<%c>", ch); + break; + } + item_set_tag('t'); + item_set_data(menu); + } else { + item_make(" "); + item_set_tag(def_menu ? 't' : ':'); + item_set_data(menu); + } + + item_add_str("%*c%s", indent + 1, ' ', _(menu_get_prompt(menu))); + if (val == yes) { + if (def_menu) { + item_add_str(" (%s)", _(menu_get_prompt(def_menu))); + item_add_str(" --->"); + if (def_menu->list) { + indent += 2; + build_conf(def_menu); + indent -= 2; + } + } + return; + } + } else { + if (menu == current_menu) { + item_make("---%*c%s", indent + 1, ' ', _(menu_get_prompt(menu))); + item_set_tag(':'); + item_set_data(menu); + goto conf_childs; + } + child_count++; + val = sym_get_tristate_value(sym); + if (sym_is_choice_value(sym) && val == yes) { + item_make(" "); + item_set_tag(':'); + item_set_data(menu); + } else { + switch (type) { + case S_BOOLEAN: + if (sym_is_changable(sym)) + item_make("[%c]", val == no ? ' ' : '*'); + else + item_make("-%c-", val == no ? ' ' : '*'); + item_set_tag('t'); + item_set_data(menu); + break; + case S_TRISTATE: + switch (val) { + case yes: ch = '*'; break; + case mod: ch = 'M'; break; + default: ch = ' '; break; + } + if (sym_is_changable(sym)) { + if (sym->rev_dep.tri == mod) + item_make("{%c}", ch); + else + item_make("<%c>", ch); + } else + item_make("-%c-", ch); + item_set_tag('t'); + item_set_data(menu); + break; + default: + tmp = 2 + strlen(sym_get_string_value(sym)); /* () = 2 */ + item_make("(%s)", sym_get_string_value(sym)); + tmp = indent - tmp + 4; + if (tmp < 0) + tmp = 0; + item_add_str("%*c%s%s", tmp, ' ', _(menu_get_prompt(menu)), + (sym_has_value(sym) || !sym_is_changable(sym)) ? + "" : _(" (NEW)")); + item_set_tag('s'); + item_set_data(menu); + goto conf_childs; + } + } + item_add_str("%*c%s%s", indent + 1, ' ', _(menu_get_prompt(menu)), + (sym_has_value(sym) || !sym_is_changable(sym)) ? + "" : _(" (NEW)")); + if (menu->prompt->type == P_MENU) { + item_add_str(" %s", menu_is_empty(menu) ? "----" : "--->"); + return; + } + } + +conf_childs: + indent += doint; + for (child = menu->list; child; child = child->next) + build_conf(child); + indent -= doint; +} + +static void conf(struct menu *menu, struct menu *active_menu) +{ + struct menu *submenu; + const char *prompt = menu_get_prompt(menu); + struct subtitle_part stpart; + struct symbol *sym; + int res; + int s_scroll = 0; + + if (menu != &rootmenu) + stpart.text = menu_get_prompt(menu); + else + stpart.text = NULL; + list_add_tail(&stpart.entries, &trail); + + while (1) { + item_reset(); + current_menu = menu; + build_conf(menu); + if (!child_count) + break; + set_subtitle(); + dialog_clear(); + res = dialog_menu(prompt ? _(prompt) : _("Main Menu"), + _(menu_instructions), + active_menu, &s_scroll); + if (res == 1 || res == KEY_ESC || res == -ERRDISPLAYTOOSMALL) + break; + if (item_count() != 0) { + if (!item_activate_selected()) + continue; + if (!item_tag()) + continue; + } + submenu = item_data(); + active_menu = item_data(); + if (submenu) + sym = submenu->sym; + else + sym = NULL; + + switch (res) { + case 0: + switch (item_tag()) { + case 'm': + if (single_menu_mode) + submenu->data = (void *) (long) !submenu->data; + else + conf(submenu, NULL); + break; + case 't': + if (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes) + conf_choice(submenu); + else if (submenu->prompt->type == P_MENU) + conf(submenu, NULL); + break; + case 's': + conf_string(submenu); + break; + } + break; + case 2: + if (sym) + show_help(submenu); + else { + reset_subtitle(); + show_helptext(_("README"), _(mconf_readme)); + } + break; + case 3: + reset_subtitle(); + conf_save(); + break; + case 4: + reset_subtitle(); + conf_load(); + break; + case 5: + if (item_is_tag('t')) { + if (sym_set_tristate_value(sym, yes)) + break; + if (sym_set_tristate_value(sym, mod)) + show_textbox(NULL, setmod_text, 6, 74); + } + break; + case 6: + if (item_is_tag('t')) + sym_set_tristate_value(sym, no); + break; + case 7: + if (item_is_tag('t')) + sym_set_tristate_value(sym, mod); + break; + case 8: + if (item_is_tag('t')) + sym_toggle_tristate_value(sym); + else if (item_is_tag('m')) + conf(submenu, NULL); + break; + case 9: + search_conf(); + break; + case 10: + show_all_options = !show_all_options; + break; + } + } + + list_del(trail.prev); +} + +static int show_textbox_ext(const char *title, char *text, int r, int c, int + *keys, int *vscroll, int *hscroll, update_text_fn + update_text, void *data) +{ + dialog_clear(); + return dialog_textbox(title, text, r, c, keys, vscroll, hscroll, + update_text, data); +} + +static void show_textbox(const char *title, const char *text, int r, int c) +{ + show_textbox_ext(title, (char *) text, r, c, (int []) {0}, NULL, NULL, + NULL, NULL); +} + +static void show_helptext(const char *title, const char *text) +{ + show_textbox(title, text, 0, 0); +} + +static void conf_message_callback(const char *fmt, va_list ap) +{ + char buf[PATH_MAX+1]; + + vsnprintf(buf, sizeof(buf), fmt, ap); + if (save_and_exit) + printf("%s", buf); + else + show_textbox(NULL, buf, 6, 60); +} + +static void show_help(struct menu *menu) +{ + struct gstr help = str_new(); + + help.max_width = getmaxx(stdscr) - 10; + menu_get_ext_help(menu, &help); + + show_helptext(_(menu_get_prompt(menu)), str_get(&help)); + str_free(&help); +} + +static void conf_choice(struct menu *menu) +{ + const char *prompt = _(menu_get_prompt(menu)); + struct menu *child; + struct symbol *active; + + active = sym_get_choice_value(menu->sym); + while (1) { + int res; + int selected; + item_reset(); + + current_menu = menu; + for (child = menu->list; child; child = child->next) { + if (!menu_is_visible(child)) + continue; + if (child->sym) + item_make("%s", _(menu_get_prompt(child))); + else { + item_make("*** %s ***", _(menu_get_prompt(child))); + item_set_tag(':'); + } + item_set_data(child); + if (child->sym == active) + item_set_selected(1); + if (child->sym == sym_get_choice_value(menu->sym)) + item_set_tag('X'); + } + dialog_clear(); + res = dialog_checklist(prompt ? _(prompt) : _("Main Menu"), + _(radiolist_instructions), + MENUBOX_HEIGTH_MIN, + MENUBOX_WIDTH_MIN, + CHECKLIST_HEIGTH_MIN); + selected = item_activate_selected(); + switch (res) { + case 0: + if (selected) { + child = item_data(); + if (!child->sym) + break; + + sym_set_tristate_value(child->sym, yes); + } + return; + case 1: + if (selected) { + child = item_data(); + show_help(child); + active = child->sym; + } else + show_help(menu); + break; + case KEY_ESC: + return; + case -ERRDISPLAYTOOSMALL: + return; + } + } +} + +static void conf_string(struct menu *menu) +{ + const char *prompt = menu_get_prompt(menu); + + while (1) { + int res; + const char *heading; + + switch (sym_get_type(menu->sym)) { + case S_INT: + heading = _(inputbox_instructions_int); + break; + case S_HEX: + heading = _(inputbox_instructions_hex); + break; + case S_STRING: + heading = _(inputbox_instructions_string); + break; + default: + heading = _("Internal mconf error!"); + } + dialog_clear(); + res = dialog_inputbox(prompt ? _(prompt) : _("Main Menu"), + heading, 10, 75, + sym_get_string_value(menu->sym)); + switch (res) { + case 0: + if (sym_set_string_value(menu->sym, dialog_input_result)) + return; + show_textbox(NULL, _("You have made an invalid entry."), 5, 43); + break; + case 1: + show_help(menu); + break; + case KEY_ESC: + return; + } + } +} + +static void conf_load(void) +{ + + while (1) { + int res; + dialog_clear(); + res = dialog_inputbox(NULL, load_config_text, + 11, 55, filename); + switch(res) { + case 0: + if (!dialog_input_result[0]) + return; + if (!conf_read(dialog_input_result)) { + set_config_filename(dialog_input_result); + sym_set_change_count(1); + return; + } + show_textbox(NULL, _("File does not exist!"), 5, 38); + break; + case 1: + show_helptext(_("Load Alternate Configuration"), load_config_help); + break; + case KEY_ESC: + return; + } + } +} + +static void conf_save(void) +{ + while (1) { + int res; + dialog_clear(); + res = dialog_inputbox(NULL, save_config_text, + 11, 55, filename); + switch(res) { + case 0: + if (!dialog_input_result[0]) + return; + if (!conf_write(dialog_input_result)) { + set_config_filename(dialog_input_result); + return; + } + show_textbox(NULL, _("Can't create file! Probably a nonexistent directory."), 5, 60); + break; + case 1: + show_helptext(_("Save Alternate Configuration"), save_config_help); + break; + case KEY_ESC: + return; + } + } +} + +static int handle_exit(void) +{ + int res; + + save_and_exit = 1; + reset_subtitle(); + dialog_clear(); + if (conf_get_changed()) + res = dialog_yesno(NULL, + _("Do you wish to save your new configuration?\n" + "(Press to continue kernel configuration.)"), + 6, 60); + else + res = -1; + + end_dialog(saved_x, saved_y); + + switch (res) { + case 0: + if (conf_write(filename)) { + fprintf(stderr, _("\n\n" + "Error while writing of the configuration.\n" + "Your configuration changes were NOT saved." + "\n\n")); + return 1; + } + /* fall through */ + case -1: + printf(_("\n\n" + "*** End of the configuration.\n" + "*** Execute 'make' to start the build or try 'make help'." + "\n\n")); + res = 0; + break; + default: + fprintf(stderr, _("\n\n" + "Your configuration changes were NOT saved." + "\n\n")); + if (res != KEY_ESC) + res = 0; + } + + return res; +} + +static void sig_handler(int signo) +{ + exit(handle_exit()); +} + +int main(int ac, char **av) +{ + char *mode; + int res; + + setlocale(LC_ALL, ""); + bindtextdomain(PACKAGE, LOCALEDIR); + textdomain(PACKAGE); + + signal(SIGINT, sig_handler); + + conf_parse(av[1]); + conf_read(NULL); + + mode = getenv("MENUCONFIG_MODE"); + if (mode) { + if (!strcasecmp(mode, "single_menu")) + single_menu_mode = 1; + } + + if (init_dialog(NULL)) { + fprintf(stderr, N_("Your display is too small to run Menuconfig!\n")); + fprintf(stderr, N_("It must be at least 19 lines by 80 columns.\n")); + return 1; + } + + set_config_filename(conf_get_configname()); + conf_set_message_callback(conf_message_callback); + do { + conf(&rootmenu, NULL); + res = handle_exit(); + } while (res == KEY_ESC); + + return res; +} diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c new file mode 100644 index 0000000000..72c9dba84c --- /dev/null +++ b/scripts/kconfig/menu.c @@ -0,0 +1,697 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include + +#include "lkc.h" + +static const char nohelp_text[] = "There is no help available for this option."; + +struct menu rootmenu; +static struct menu **last_entry_ptr; + +struct file *file_list; +struct file *current_file; + +void menu_warn(struct menu *menu, const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + fprintf(stderr, "%s:%d:warning: ", menu->file->name, menu->lineno); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + va_end(ap); +} + +static void prop_warn(struct property *prop, const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + fprintf(stderr, "%s:%d:warning: ", prop->file->name, prop->lineno); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + va_end(ap); +} + +void _menu_init(void) +{ + current_entry = current_menu = &rootmenu; + last_entry_ptr = &rootmenu.list; +} + +void menu_add_entry(struct symbol *sym) +{ + struct menu *menu; + + menu = xmalloc(sizeof(*menu)); + memset(menu, 0, sizeof(*menu)); + menu->sym = sym; + menu->parent = current_menu; + menu->file = current_file; + menu->lineno = zconf_lineno(); + + *last_entry_ptr = menu; + last_entry_ptr = &menu->next; + current_entry = menu; + if (sym) + menu_add_symbol(P_SYMBOL, sym, NULL); +} + +void menu_end_entry(void) +{ +} + +struct menu *menu_add_menu(void) +{ + menu_end_entry(); + last_entry_ptr = ¤t_entry->list; + return current_menu = current_entry; +} + +void menu_end_menu(void) +{ + last_entry_ptr = ¤t_menu->next; + current_menu = current_menu->parent; +} + +static struct expr *menu_check_dep(struct expr *e) +{ + if (!e) + return e; + + switch (e->type) { + case E_NOT: + e->left.expr = menu_check_dep(e->left.expr); + break; + case E_OR: + case E_AND: + e->left.expr = menu_check_dep(e->left.expr); + e->right.expr = menu_check_dep(e->right.expr); + break; + case E_SYMBOL: + /* change 'm' into 'm' && MODULES */ + if (e->left.sym == &symbol_mod) + return expr_alloc_and(e, expr_alloc_symbol(modules_sym)); + break; + default: + break; + } + return e; +} + +void menu_add_dep(struct expr *dep) +{ + current_entry->dep = expr_alloc_and(current_entry->dep, menu_check_dep(dep)); +} + +void menu_set_type(int type) +{ + struct symbol *sym = current_entry->sym; + + if (sym->type == type) + return; + if (sym->type == S_UNKNOWN) { + sym->type = type; + return; + } + menu_warn(current_entry, + "ignoring type redefinition of '%s' from '%s' to '%s'", + sym->name ? sym->name : "", + sym_type_name(sym->type), sym_type_name(type)); +} + +struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *expr, struct expr *dep) +{ + struct property *prop = prop_alloc(type, current_entry->sym); + + prop->menu = current_entry; + prop->expr = expr; + prop->visible.expr = menu_check_dep(dep); + + if (prompt) { + if (isspace(*prompt)) { + prop_warn(prop, "leading whitespace ignored"); + while (isspace(*prompt)) + prompt++; + } + if (current_entry->prompt && current_entry != &rootmenu) + prop_warn(prop, "prompt redefined"); + + /* Apply all upper menus' visibilities to actual prompts. */ + if(type == P_PROMPT) { + struct menu *menu = current_entry; + + while ((menu = menu->parent) != NULL) { + struct expr *dup_expr; + + if (!menu->visibility) + continue; + /* + * Do not add a reference to the + * menu's visibility expression but + * use a copy of it. Otherwise the + * expression reduction functions + * will modify expressions that have + * multiple references which can + * cause unwanted side effects. + */ + dup_expr = expr_copy(menu->visibility); + + prop->visible.expr + = expr_alloc_and(prop->visible.expr, + dup_expr); + } + } + + current_entry->prompt = prop; + } + prop->text = prompt; + + return prop; +} + +struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep) +{ + return menu_add_prop(type, prompt, NULL, dep); +} + +void menu_add_visibility(struct expr *expr) +{ + current_entry->visibility = expr_alloc_and(current_entry->visibility, + expr); +} + +void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep) +{ + menu_add_prop(type, NULL, expr, dep); +} + +void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep) +{ + menu_add_prop(type, NULL, expr_alloc_symbol(sym), dep); +} + +void menu_add_option(int token, char *arg) +{ + switch (token) { + case T_OPT_MODULES: + if (modules_sym) + zconf_error("symbol '%s' redefines option 'modules'" + " already defined by symbol '%s'", + current_entry->sym->name, + modules_sym->name + ); + modules_sym = current_entry->sym; + break; + case T_OPT_DEFCONFIG_LIST: + if (!sym_defconfig_list) + sym_defconfig_list = current_entry->sym; + else if (sym_defconfig_list != current_entry->sym) + zconf_error("trying to redefine defconfig symbol"); + break; + case T_OPT_ENV: + prop_add_env(arg); + break; + case T_OPT_ALLNOCONFIG_Y: + current_entry->sym->flags |= SYMBOL_ALLNOCONFIG_Y; + break; + } +} + +static int menu_validate_number(struct symbol *sym, struct symbol *sym2) +{ + return sym2->type == S_INT || sym2->type == S_HEX || + (sym2->type == S_UNKNOWN && sym_string_valid(sym, sym2->name)); +} + +static void sym_check_prop(struct symbol *sym) +{ + struct property *prop; + struct symbol *sym2; + for (prop = sym->prop; prop; prop = prop->next) { + switch (prop->type) { + case P_DEFAULT: + if ((sym->type == S_STRING || sym->type == S_INT || sym->type == S_HEX) && + prop->expr->type != E_SYMBOL) + prop_warn(prop, + "default for config symbol '%s'" + " must be a single symbol", sym->name); + if (prop->expr->type != E_SYMBOL) + break; + sym2 = prop_get_symbol(prop); + if (sym->type == S_HEX || sym->type == S_INT) { + if (!menu_validate_number(sym, sym2)) + prop_warn(prop, + "'%s': number is invalid", + sym->name); + } + break; + case P_SELECT: + sym2 = prop_get_symbol(prop); + if (sym->type != S_BOOLEAN && sym->type != S_TRISTATE) + prop_warn(prop, + "config symbol '%s' uses select, but is " + "not boolean or tristate", sym->name); + else if (sym2->type != S_UNKNOWN && + sym2->type != S_BOOLEAN && + sym2->type != S_TRISTATE) + prop_warn(prop, + "'%s' has wrong type. 'select' only " + "accept arguments of boolean and " + "tristate type", sym2->name); + break; + case P_RANGE: + if (sym->type != S_INT && sym->type != S_HEX) + prop_warn(prop, "range is only allowed " + "for int or hex symbols"); + if (!menu_validate_number(sym, prop->expr->left.sym) || + !menu_validate_number(sym, prop->expr->right.sym)) + prop_warn(prop, "range is invalid"); + break; + default: + ; + } + } +} + +void menu_finalize(struct menu *parent) +{ + struct menu *menu, *last_menu; + struct symbol *sym; + struct property *prop; + struct expr *parentdep, *basedep, *dep, *dep2, **ep; + + sym = parent->sym; + if (parent->list) { + if (sym && sym_is_choice(sym)) { + if (sym->type == S_UNKNOWN) { + /* find the first choice value to find out choice type */ + current_entry = parent; + for (menu = parent->list; menu; menu = menu->next) { + if (menu->sym && menu->sym->type != S_UNKNOWN) { + menu_set_type(menu->sym->type); + break; + } + } + } + /* set the type of the remaining choice values */ + for (menu = parent->list; menu; menu = menu->next) { + current_entry = menu; + if (menu->sym && menu->sym->type == S_UNKNOWN) + menu_set_type(sym->type); + } + parentdep = expr_alloc_symbol(sym); + } else if (parent->prompt) + parentdep = parent->prompt->visible.expr; + else + parentdep = parent->dep; + + for (menu = parent->list; menu; menu = menu->next) { + basedep = expr_transform(menu->dep); + basedep = expr_alloc_and(expr_copy(parentdep), basedep); + basedep = expr_eliminate_dups(basedep); + menu->dep = basedep; + if (menu->sym) + prop = menu->sym->prop; + else + prop = menu->prompt; + for (; prop; prop = prop->next) { + if (prop->menu != menu) + continue; + dep = expr_transform(prop->visible.expr); + dep = expr_alloc_and(expr_copy(basedep), dep); + dep = expr_eliminate_dups(dep); + if (menu->sym && menu->sym->type != S_TRISTATE) + dep = expr_trans_bool(dep); + prop->visible.expr = dep; + if (prop->type == P_SELECT) { + struct symbol *es = prop_get_symbol(prop); + es->rev_dep.expr = expr_alloc_or(es->rev_dep.expr, + expr_alloc_and(expr_alloc_symbol(menu->sym), expr_copy(dep))); + } + } + } + for (menu = parent->list; menu; menu = menu->next) + menu_finalize(menu); + } else if (sym) { + basedep = parent->prompt ? parent->prompt->visible.expr : NULL; + basedep = expr_trans_compare(basedep, E_UNEQUAL, &symbol_no); + basedep = expr_eliminate_dups(expr_transform(basedep)); + last_menu = NULL; + for (menu = parent->next; menu; menu = menu->next) { + dep = menu->prompt ? menu->prompt->visible.expr : menu->dep; + if (!expr_contains_symbol(dep, sym)) + break; + if (expr_depends_symbol(dep, sym)) + goto next; + dep = expr_trans_compare(dep, E_UNEQUAL, &symbol_no); + dep = expr_eliminate_dups(expr_transform(dep)); + dep2 = expr_copy(basedep); + expr_eliminate_eq(&dep, &dep2); + expr_free(dep); + if (!expr_is_yes(dep2)) { + expr_free(dep2); + break; + } + expr_free(dep2); + next: + menu_finalize(menu); + menu->parent = parent; + last_menu = menu; + } + if (last_menu) { + parent->list = parent->next; + parent->next = last_menu->next; + last_menu->next = NULL; + } + + sym->dir_dep.expr = expr_alloc_or(sym->dir_dep.expr, parent->dep); + } + for (menu = parent->list; menu; menu = menu->next) { + if (sym && sym_is_choice(sym) && + menu->sym && !sym_is_choice_value(menu->sym)) { + current_entry = menu; + menu->sym->flags |= SYMBOL_CHOICEVAL; + if (!menu->prompt) + menu_warn(menu, "choice value must have a prompt"); + for (prop = menu->sym->prop; prop; prop = prop->next) { + if (prop->type == P_DEFAULT) + prop_warn(prop, "defaults for choice " + "values not supported"); + if (prop->menu == menu) + continue; + if (prop->type == P_PROMPT && + prop->menu->parent->sym != sym) + prop_warn(prop, "choice value used outside its choice group"); + } + /* Non-tristate choice values of tristate choices must + * depend on the choice being set to Y. The choice + * values' dependencies were propagated to their + * properties above, so the change here must be re- + * propagated. + */ + if (sym->type == S_TRISTATE && menu->sym->type != S_TRISTATE) { + basedep = expr_alloc_comp(E_EQUAL, sym, &symbol_yes); + menu->dep = expr_alloc_and(basedep, menu->dep); + for (prop = menu->sym->prop; prop; prop = prop->next) { + if (prop->menu != menu) + continue; + prop->visible.expr = expr_alloc_and(expr_copy(basedep), + prop->visible.expr); + } + } + menu_add_symbol(P_CHOICE, sym, NULL); + prop = sym_get_choice_prop(sym); + for (ep = &prop->expr; *ep; ep = &(*ep)->left.expr) + ; + *ep = expr_alloc_one(E_LIST, NULL); + (*ep)->right.sym = menu->sym; + } + if (menu->list && (!menu->prompt || !menu->prompt->text)) { + for (last_menu = menu->list; ; last_menu = last_menu->next) { + last_menu->parent = parent; + if (!last_menu->next) + break; + } + last_menu->next = menu->next; + menu->next = menu->list; + menu->list = NULL; + } + } + + if (sym && !(sym->flags & SYMBOL_WARNED)) { + if (sym->type == S_UNKNOWN) + menu_warn(parent, "config symbol defined without type"); + + if (sym_is_choice(sym) && !parent->prompt) + menu_warn(parent, "choice must have a prompt"); + + /* Check properties connected to this symbol */ + sym_check_prop(sym); + sym->flags |= SYMBOL_WARNED; + } + + if (sym && !sym_is_optional(sym) && parent->prompt) { + sym->rev_dep.expr = expr_alloc_or(sym->rev_dep.expr, + expr_alloc_and(parent->prompt->visible.expr, + expr_alloc_symbol(&symbol_mod))); + } +} + +bool menu_has_prompt(struct menu *menu) +{ + if (!menu->prompt) + return false; + return true; +} + +/* + * Determine if a menu is empty. + * A menu is considered empty if it contains no or only + * invisible entries. + */ +bool menu_is_empty(struct menu *menu) +{ + struct menu *child; + + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child)) + return(false); + } + return(true); +} + +bool menu_is_visible(struct menu *menu) +{ + struct menu *child; + struct symbol *sym; + tristate visible; + + if (!menu->prompt) + return false; + + if (menu->visibility) { + if (expr_calc_value(menu->visibility) == no) + return no; + } + + sym = menu->sym; + if (sym) { + sym_calc_value(sym); + visible = menu->prompt->visible.tri; + } else + visible = menu->prompt->visible.tri = expr_calc_value(menu->prompt->visible.expr); + + if (visible != no) + return true; + + if (!sym || sym_get_tristate_value(menu->sym) == no) + return false; + + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child)) { + if (sym) + sym->flags |= SYMBOL_DEF_USER; + return true; + } + } + + return false; +} + +const char *menu_get_prompt(struct menu *menu) +{ + if (menu->prompt) + return menu->prompt->text; + else if (menu->sym) + return menu->sym->name; + return NULL; +} + +struct menu *menu_get_root_menu(struct menu *menu) +{ + return &rootmenu; +} + +struct menu *menu_get_parent_menu(struct menu *menu) +{ + enum prop_type type; + + for (; menu != &rootmenu; menu = menu->parent) { + type = menu->prompt ? menu->prompt->type : 0; + if (type == P_MENU) + break; + } + return menu; +} + +bool menu_has_help(struct menu *menu) +{ + return menu->help != NULL; +} + +const char *menu_get_help(struct menu *menu) +{ + if (menu->help) + return menu->help; + else + return ""; +} + +static void get_prompt_str(struct gstr *r, struct property *prop, + struct list_head *head) +{ + int i, j; + struct menu *submenu[8], *menu, *location = NULL; + struct jump_key *jump = NULL; + + str_printf(r, _("Prompt: %s\n"), _(prop->text)); + menu = prop->menu->parent; + for (i = 0; menu != &rootmenu && i < 8; menu = menu->parent) { + bool accessible = menu_is_visible(menu); + + submenu[i++] = menu; + if (location == NULL && accessible) + location = menu; + } + if (head && location) { + jump = xmalloc(sizeof(struct jump_key)); + + if (menu_is_visible(prop->menu)) { + /* + * There is not enough room to put the hint at the + * beginning of the "Prompt" line. Put the hint on the + * last "Location" line even when it would belong on + * the former. + */ + jump->target = prop->menu; + } else + jump->target = location; + + if (list_empty(head)) + jump->index = 0; + else + jump->index = list_entry(head->prev, struct jump_key, + entries)->index + 1; + + list_add_tail(&jump->entries, head); + } + + if (i > 0) { + str_printf(r, _(" Location:\n")); + for (j = 4; --i >= 0; j += 2) { + menu = submenu[i]; + if (jump && menu == location) + jump->offset = strlen(r->s); + str_printf(r, "%*c-> %s", j, ' ', + _(menu_get_prompt(menu))); + if (menu->sym) { + str_printf(r, " (%s [=%s])", menu->sym->name ? + menu->sym->name : _(""), + sym_get_string_value(menu->sym)); + } + str_append(r, "\n"); + } + } +} + +/* + * get property of type P_SYMBOL + */ +static struct property *get_symbol_prop(struct symbol *sym) +{ + struct property *prop = NULL; + + for_all_properties(sym, prop, P_SYMBOL) + break; + return prop; +} + +/* + * head is optional and may be NULL + */ +void get_symbol_str(struct gstr *r, struct symbol *sym, + struct list_head *head) +{ + bool hit; + struct property *prop; + + if (sym && sym->name) { + str_printf(r, "Symbol: %s [=%s]\n", sym->name, + sym_get_string_value(sym)); + str_printf(r, "Type : %s\n", sym_type_name(sym->type)); + if (sym->type == S_INT || sym->type == S_HEX) { + prop = sym_get_range_prop(sym); + if (prop) { + str_printf(r, "Range : "); + expr_gstr_print(prop->expr, r); + str_append(r, "\n"); + } + } + } + for_all_prompts(sym, prop) + get_prompt_str(r, prop, head); + + prop = get_symbol_prop(sym); + if (prop) { + str_printf(r, _(" Defined at %s:%d\n"), prop->menu->file->name, + prop->menu->lineno); + if (!expr_is_yes(prop->visible.expr)) { + str_append(r, _(" Depends on: ")); + expr_gstr_print(prop->visible.expr, r); + str_append(r, "\n"); + } + } + + hit = false; + for_all_properties(sym, prop, P_SELECT) { + if (!hit) { + str_append(r, " Selects: "); + hit = true; + } else + str_printf(r, " && "); + expr_gstr_print(prop->expr, r); + } + if (hit) + str_append(r, "\n"); + if (sym->rev_dep.expr) { + str_append(r, _(" Selected by: ")); + expr_gstr_print(sym->rev_dep.expr, r); + str_append(r, "\n"); + } + str_append(r, "\n\n"); +} + +struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head) +{ + struct symbol *sym; + struct gstr res = str_new(); + int i; + + for (i = 0; sym_arr && (sym = sym_arr[i]); i++) + get_symbol_str(&res, sym, head); + if (!i) + str_append(&res, _("No matches found.\n")); + return res; +} + + +void menu_get_ext_help(struct menu *menu, struct gstr *help) +{ + struct symbol *sym = menu->sym; + const char *help_text = nohelp_text; + + if (menu_has_help(menu)) { + if (sym->name) + str_printf(help, "%s%s:\n\n", CONFIG_, sym->name); + help_text = menu_get_help(menu); + } + str_printf(help, "%s\n", _(help_text)); + if (sym) + get_symbol_str(help, sym, NULL); +} diff --git a/scripts/kconfig/merge_config.sh b/scripts/kconfig/merge_config.sh new file mode 100755 index 0000000000..efa4733461 --- /dev/null +++ b/scripts/kconfig/merge_config.sh @@ -0,0 +1,150 @@ +#!/bin/sh +# merge_config.sh - Takes a list of config fragment values, and merges +# them one by one. Provides warnings on overridden values, and specified +# values that did not make it to the resulting .config file (due to missed +# dependencies or config symbol removal). +# +# Portions reused from kconf_check and generate_cfg: +# http://git.yoctoproject.org/cgit/cgit.cgi/yocto-kernel-tools/tree/tools/kconf_check +# http://git.yoctoproject.org/cgit/cgit.cgi/yocto-kernel-tools/tree/tools/generate_cfg +# +# Copyright (c) 2009-2010 Wind River Systems, Inc. +# Copyright 2011 Linaro +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU General Public License for more details. + +clean_up() { + rm -f $TMP_FILE + exit +} +trap clean_up HUP INT TERM + +usage() { + echo "Usage: $0 [OPTIONS] [CONFIG [...]]" + echo " -h display this help text" + echo " -m only merge the fragments, do not execute the make command" + echo " -n use allnoconfig instead of alldefconfig" + echo " -r list redundant entries when merging fragments" + echo " -O dir to put generated output files" +} + +MAKE=true +ALLTARGET=alldefconfig +WARNREDUN=false +OUTPUT=. + +while true; do + case $1 in + "-n") + ALLTARGET=allnoconfig + shift + continue + ;; + "-m") + MAKE=false + shift + continue + ;; + "-h") + usage + exit + ;; + "-r") + WARNREDUN=true + shift + continue + ;; + "-O") + if [ -d $2 ];then + OUTPUT=$(echo $2 | sed 's/\/*$//') + else + echo "output directory $2 does not exist" 1>&2 + exit 1 + fi + shift 2 + continue + ;; + *) + break + ;; + esac +done + +INITFILE=$1 +shift; + +MERGE_LIST=$* +SED_CONFIG_EXP="s/^\(# \)\{0,1\}\(CONFIG_[a-zA-Z0-9_]*\)[= ].*/\2/p" +TMP_FILE=$(mktemp ./.tmp.config.XXXXXXXXXX) + +echo "Using $INITFILE as base" +cat $INITFILE > $TMP_FILE + +# Merge files, printing warnings on overridden values +for MERGE_FILE in $MERGE_LIST ; do + echo "Merging $MERGE_FILE" + CFG_LIST=$(sed -n "$SED_CONFIG_EXP" $MERGE_FILE) + + for CFG in $CFG_LIST ; do + grep -q -w $CFG $TMP_FILE + if [ $? -eq 0 ] ; then + PREV_VAL=$(grep -w $CFG $TMP_FILE) + NEW_VAL=$(grep -w $CFG $MERGE_FILE) + if [ "x$PREV_VAL" != "x$NEW_VAL" ] ; then + echo Value of $CFG is redefined by fragment $MERGE_FILE: + echo Previous value: $PREV_VAL + echo New value: $NEW_VAL + echo + elif [ "$WARNREDUN" = "true" ]; then + echo Value of $CFG is redundant by fragment $MERGE_FILE: + fi + sed -i "/$CFG[ =]/d" $TMP_FILE + fi + done + cat $MERGE_FILE >> $TMP_FILE +done + +if [ "$MAKE" = "false" ]; then + cp $TMP_FILE $OUTPUT/.config + echo "#" + echo "# merged configuration written to $OUTPUT/.config (needs make)" + echo "#" + clean_up + exit +fi + +# If we have an output dir, setup the O= argument, otherwise leave +# it blank, since O=. will create an unnecessary ./source softlink +OUTPUT_ARG="" +if [ "$OUTPUT" != "." ] ; then + OUTPUT_ARG="O=$OUTPUT" +fi + + +# Use the merged file as the starting point for: +# alldefconfig: Fills in any missing symbols with Kconfig default +# allnoconfig: Fills in any missing symbols with # CONFIG_* is not set +make KCONFIG_ALLCONFIG=$TMP_FILE $OUTPUT_ARG $ALLTARGET + + +# Check all specified config values took (might have missed-dependency issues) +for CFG in $(sed -n "$SED_CONFIG_EXP" $TMP_FILE); do + + REQUESTED_VAL=$(grep -w -e "$CFG" $TMP_FILE) + ACTUAL_VAL=$(grep -w -e "$CFG" $OUTPUT/.config) + if [ "x$REQUESTED_VAL" != "x$ACTUAL_VAL" ] ; then + echo "Value requested for $CFG not in final .config" + echo "Requested value: $REQUESTED_VAL" + echo "Actual value: $ACTUAL_VAL" + echo "" + fi +done + +clean_up diff --git a/scripts/kconfig/nconf.c b/scripts/kconfig/nconf.c new file mode 100644 index 0000000000..984489ef2b --- /dev/null +++ b/scripts/kconfig/nconf.c @@ -0,0 +1,1556 @@ +/* + * Copyright (C) 2008 Nir Tzachar +#include + +#include "lkc.h" +#include "nconf.h" +#include + +static const char nconf_global_help[] = N_( +"Help windows\n" +"------------\n" +"o Global help: Unless in a data entry window, pressing will give \n" +" you the global help window, which you are just reading.\n" +"\n" +"o A short version of the global help is available by pressing .\n" +"\n" +"o Local help: To get help related to the current menu entry, use any\n" +" of , or if in a data entry window then press .\n" +"\n" +"\n" +"Menu entries\n" +"------------\n" +"This interface lets you select features and parameters for the kernel\n" +"build. Kernel features can either be built-in, modularized, or removed.\n" +"Parameters must be entered as text or decimal or hexadecimal numbers.\n" +"\n" +"Menu entries beginning with following braces represent features that\n" +" [ ] can be built in or removed\n" +" < > can be built in, modularized or removed\n" +" { } can be built in or modularized, are selected by another feature\n" +" - - are selected by another feature\n" +" XXX cannot be selected. Symbol Info tells you why.\n" +"*, M or whitespace inside braces means to build in, build as a module\n" +"or to exclude the feature respectively.\n" +"\n" +"To change any of these features, highlight it with the movement keys\n" +"listed below and press to build it in, to make it a module or\n" +" to remove it. You may press the key to cycle through the\n" +"available options.\n" +"\n" +"A trailing \"--->\" designates a submenu, a trailing \"----\" an\n" +"empty submenu.\n" +"\n" +"Menu navigation keys\n" +"----------------------------------------------------------------------\n" +"Linewise up \n" +"Linewise down \n" +"Pagewise up \n" +"Pagewise down \n" +"First entry \n" +"Last entry \n" +"Enter a submenu \n" +"Go back to parent menu \n" +"Close a help window \n" +"Close entry window, apply \n" +"Close entry window, forget \n" +"Start incremental, case-insensitive search for STRING in menu entries,\n" +" no regex support, STRING is displayed in upper left corner\n" +" STRING\n" +" Remove last character \n" +" Jump to next hit \n" +" Jump to previous hit \n" +"Exit menu search mode \n" +"Search for configuration variables with or without leading CONFIG_\n" +" RegExpr\n" +"Verbose search help \n" +"----------------------------------------------------------------------\n" +"\n" +"Unless in a data entry window, key <1> may be used instead of ,\n" +"<2> instead of , etc.\n" +"\n" +"\n" +"Radiolist (Choice list)\n" +"-----------------------\n" +"Use the movement keys listed above to select the option you wish to set\n" +"and press .\n" +"\n" +"\n" +"Data entry\n" +"----------\n" +"Enter the requested information and press . Hexadecimal values\n" +"may be entered without the \"0x\" prefix.\n" +"\n" +"\n" +"Text Box (Help Window)\n" +"----------------------\n" +"Use movement keys as listed in table above.\n" +"\n" +"Press any of to exit.\n" +"\n" +"\n" +"Alternate configuration files\n" +"-----------------------------\n" +"nconfig supports switching between different configurations.\n" +"Press to save your current configuration. Press and enter\n" +"a file name to load a previously saved configuration.\n" +"\n" +"\n" +"Terminal configuration\n" +"----------------------\n" +"If you use nconfig in a xterm window, make sure your TERM environment\n" +"variable specifies a terminal configuration which supports at least\n" +"16 colors. Otherwise nconfig will look rather bad.\n" +"\n" +"If the \"stty size\" command reports the current terminalsize correctly,\n" +"nconfig will adapt to sizes larger than the traditional 80x25 \"standard\"\n" +"and display longer menus properly.\n" +"\n" +"\n" +"Single menu mode\n" +"----------------\n" +"If you prefer to have all of the menu entries listed in a single menu,\n" +"rather than the default multimenu hierarchy, run nconfig with\n" +"NCONFIG_MODE environment variable set to single_menu. Example:\n" +"\n" +"make NCONFIG_MODE=single_menu nconfig\n" +"\n" +" will then unfold the appropriate category, or fold it if it\n" +"is already unfolded. Folded menu entries will be designated by a\n" +"leading \"++>\" and unfolded entries by a leading \"-->\".\n" +"\n" +"Note that this mode can eventually be a little more CPU expensive than\n" +"the default mode, especially with a larger number of unfolded submenus.\n" +"\n"), +menu_no_f_instructions[] = N_( +"Legend: [*] built-in [ ] excluded module < > module capable.\n" +"Submenus are designated by a trailing \"--->\", empty ones by \"----\".\n" +"\n" +"Use the following keys to navigate the menus:\n" +"Move up or down with and .\n" +"Enter a submenu with or .\n" +"Exit a submenu to its parent menu with or .\n" +"Pressing includes, excludes, modularizes features.\n" +"Pressing cycles through the available options.\n" +"To search for menu entries press .\n" +" always leaves the current window.\n" +"\n" +"You do not have function keys support.\n" +"Press <1> instead of , <2> instead of , etc.\n" +"For verbose global help use key <1>.\n" +"For help related to the current menu entry press or .\n"), +menu_instructions[] = N_( +"Legend: [*] built-in [ ] excluded module < > module capable.\n" +"Submenus are designated by a trailing \"--->\", empty ones by \"----\".\n" +"\n" +"Use the following keys to navigate the menus:\n" +"Move up or down with or .\n" +"Enter a submenu with or .\n" +"Exit a submenu to its parent menu with or .\n" +"Pressing includes, excludes, modularizes features.\n" +"Pressing cycles through the available options.\n" +"To search for menu entries press .\n" +" always leaves the current window.\n" +"\n" +"Pressing <1> may be used instead of , <2> instead of , etc.\n" +"For verbose global help press .\n" +"For help related to the current menu entry press or .\n"), +radiolist_instructions[] = N_( +"Press , , or to navigate a radiolist, select\n" +"with .\n" +"For help related to the current entry press or .\n" +"For global help press .\n"), +inputbox_instructions_int[] = N_( +"Please enter a decimal value.\n" +"Fractions will not be accepted.\n" +"Press to apply, to cancel."), +inputbox_instructions_hex[] = N_( +"Please enter a hexadecimal value.\n" +"Press to apply, to cancel."), +inputbox_instructions_string[] = N_( +"Please enter a string value.\n" +"Press to apply, to cancel."), +setmod_text[] = N_( +"This feature depends on another feature which has been configured as a\n" +"module. As a result, the current feature will be built as a module too."), +load_config_text[] = N_( +"Enter the name of the configuration file you wish to load.\n" +"Accept the name shown to restore the configuration you last\n" +"retrieved. Leave empty to abort."), +load_config_help[] = N_( +"For various reasons, one may wish to keep several different\n" +"configurations available on a single machine.\n" +"\n" +"If you have saved a previous configuration in a file other than the\n" +"default one, entering its name here will allow you to load and modify\n" +"that configuration.\n" +"\n" +"Leave empty to abort.\n"), +save_config_text[] = N_( +"Enter a filename to which this configuration should be saved\n" +"as an alternate. Leave empty to abort."), +save_config_help[] = N_( +"For various reasons, one may wish to keep several different\n" +"configurations available on a single machine.\n" +"\n" +"Entering a file name here will allow you to later retrieve, modify\n" +"and use the current configuration as an alternate to whatever\n" +"configuration options you have selected at that time.\n" +"\n" +"Leave empty to abort.\n"), +search_help[] = N_( +"Search for symbols (configuration variable names CONFIG_*) and display\n" +"their relations. Regular expressions are supported.\n" +"Example: Search for \"^FOO\".\n" +"Result:\n" +"-----------------------------------------------------------------\n" +"Symbol: FOO [ = m]\n" +"Prompt: Foo bus is used to drive the bar HW\n" +"Defined at drivers/pci/Kconfig:47\n" +"Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n" +"Location:\n" +" -> Bus options (PCI, PCMCIA, EISA, ISA)\n" +" -> PCI support (PCI [ = y])\n" +" -> PCI access mode ( [ = y])\n" +"Selects: LIBCRC32\n" +"Selected by: BAR\n" +"-----------------------------------------------------------------\n" +"o The line 'Prompt:' shows the text displayed for this symbol in\n" +" the menu hierarchy.\n" +"o The 'Defined at' line tells at what file / line number the symbol is\n" +" defined.\n" +"o The 'Depends on:' line lists symbols that need to be defined for\n" +" this symbol to be visible and selectable in the menu.\n" +"o The 'Location:' lines tell, where in the menu structure this symbol\n" +" is located. A location followed by a [ = y] indicates that this is\n" +" a selectable menu item, and the current value is displayed inside\n" +" brackets.\n" +"o The 'Selects:' line tells, what symbol will be automatically selected\n" +" if this symbol is selected (y or m).\n" +"o The 'Selected by' line tells what symbol has selected this symbol.\n" +"\n" +"Only relevant lines are shown.\n" +"\n\n" +"Search examples:\n" +"USB => find all symbols containing USB\n" +"^USB => find all symbols starting with USB\n" +"USB$ => find all symbols ending with USB\n" +"\n"); + +struct mitem { + char str[256]; + char tag; + void *usrptr; + int is_visible; +}; + +#define MAX_MENU_ITEMS 4096 +static int show_all_items; +static int indent; +static struct menu *current_menu; +static int child_count; +static int single_menu_mode; +/* the window in which all information appears */ +static WINDOW *main_window; +/* the largest size of the menu window */ +static int mwin_max_lines; +static int mwin_max_cols; +/* the window in which we show option buttons */ +static MENU *curses_menu; +static ITEM *curses_menu_items[MAX_MENU_ITEMS]; +static struct mitem k_menu_items[MAX_MENU_ITEMS]; +static int items_num; +static int global_exit; +/* the currently selected button */ +const char *current_instructions = menu_instructions; + +static char *dialog_input_result; +static int dialog_input_result_len; + +static void conf(struct menu *menu); +static void conf_choice(struct menu *menu); +static void conf_string(struct menu *menu); +static void conf_load(void); +static void conf_save(void); +static void show_help(struct menu *menu); +static int do_exit(void); +static void setup_windows(void); +static void search_conf(void); + +typedef void (*function_key_handler_t)(int *key, struct menu *menu); +static void handle_f1(int *key, struct menu *current_item); +static void handle_f2(int *key, struct menu *current_item); +static void handle_f3(int *key, struct menu *current_item); +static void handle_f4(int *key, struct menu *current_item); +static void handle_f5(int *key, struct menu *current_item); +static void handle_f6(int *key, struct menu *current_item); +static void handle_f7(int *key, struct menu *current_item); +static void handle_f8(int *key, struct menu *current_item); +static void handle_f9(int *key, struct menu *current_item); + +struct function_keys { + const char *key_str; + const char *func; + function_key key; + function_key_handler_t handler; +}; + +static const int function_keys_num = 9; +struct function_keys function_keys[] = { + { + .key_str = "F1", + .func = "Help", + .key = F_HELP, + .handler = handle_f1, + }, + { + .key_str = "F2", + .func = "SymInfo", + .key = F_SYMBOL, + .handler = handle_f2, + }, + { + .key_str = "F3", + .func = "Help 2", + .key = F_INSTS, + .handler = handle_f3, + }, + { + .key_str = "F4", + .func = "ShowAll", + .key = F_CONF, + .handler = handle_f4, + }, + { + .key_str = "F5", + .func = "Back", + .key = F_BACK, + .handler = handle_f5, + }, + { + .key_str = "F6", + .func = "Save", + .key = F_SAVE, + .handler = handle_f6, + }, + { + .key_str = "F7", + .func = "Load", + .key = F_LOAD, + .handler = handle_f7, + }, + { + .key_str = "F8", + .func = "SymSearch", + .key = F_SEARCH, + .handler = handle_f8, + }, + { + .key_str = "F9", + .func = "Exit", + .key = F_EXIT, + .handler = handle_f9, + }, +}; + +static void print_function_line(void) +{ + int i; + int offset = 1; + const int skip = 1; + int lines = getmaxy(stdscr); + + for (i = 0; i < function_keys_num; i++) { + (void) wattrset(main_window, attributes[FUNCTION_HIGHLIGHT]); + mvwprintw(main_window, lines-3, offset, + "%s", + function_keys[i].key_str); + (void) wattrset(main_window, attributes[FUNCTION_TEXT]); + offset += strlen(function_keys[i].key_str); + mvwprintw(main_window, lines-3, + offset, "%s", + function_keys[i].func); + offset += strlen(function_keys[i].func) + skip; + } + (void) wattrset(main_window, attributes[NORMAL]); +} + +/* help */ +static void handle_f1(int *key, struct menu *current_item) +{ + show_scroll_win(main_window, + _("Global help"), _(nconf_global_help)); + return; +} + +/* symbole help */ +static void handle_f2(int *key, struct menu *current_item) +{ + show_help(current_item); + return; +} + +/* instructions */ +static void handle_f3(int *key, struct menu *current_item) +{ + show_scroll_win(main_window, + _("Short help"), + _(current_instructions)); + return; +} + +/* config */ +static void handle_f4(int *key, struct menu *current_item) +{ + int res = btn_dialog(main_window, + _("Show all symbols?"), + 2, + " ", + ""); + if (res == 0) + show_all_items = 1; + else if (res == 1) + show_all_items = 0; + + return; +} + +/* back */ +static void handle_f5(int *key, struct menu *current_item) +{ + *key = KEY_LEFT; + return; +} + +/* save */ +static void handle_f6(int *key, struct menu *current_item) +{ + conf_save(); + return; +} + +/* load */ +static void handle_f7(int *key, struct menu *current_item) +{ + conf_load(); + return; +} + +/* search */ +static void handle_f8(int *key, struct menu *current_item) +{ + search_conf(); + return; +} + +/* exit */ +static void handle_f9(int *key, struct menu *current_item) +{ + do_exit(); + return; +} + +/* return != 0 to indicate the key was handles */ +static int process_special_keys(int *key, struct menu *menu) +{ + int i; + + if (*key == KEY_RESIZE) { + setup_windows(); + return 1; + } + + for (i = 0; i < function_keys_num; i++) { + if (*key == KEY_F(function_keys[i].key) || + *key == '0' + function_keys[i].key){ + function_keys[i].handler(key, menu); + return 1; + } + } + + return 0; +} + +static void clean_items(void) +{ + int i; + for (i = 0; curses_menu_items[i]; i++) + free_item(curses_menu_items[i]); + bzero(curses_menu_items, sizeof(curses_menu_items)); + bzero(k_menu_items, sizeof(k_menu_items)); + items_num = 0; +} + +typedef enum {MATCH_TINKER_PATTERN_UP, MATCH_TINKER_PATTERN_DOWN, + FIND_NEXT_MATCH_DOWN, FIND_NEXT_MATCH_UP} match_f; + +/* return the index of the matched item, or -1 if no such item exists */ +static int get_mext_match(const char *match_str, match_f flag) +{ + int match_start = item_index(current_item(curses_menu)); + int index; + + if (flag == FIND_NEXT_MATCH_DOWN) + ++match_start; + else if (flag == FIND_NEXT_MATCH_UP) + --match_start; + + index = match_start; + index = (index + items_num) % items_num; + while (true) { + char *str = k_menu_items[index].str; + if (strcasestr(str, match_str) != 0) + return index; + if (flag == FIND_NEXT_MATCH_UP || + flag == MATCH_TINKER_PATTERN_UP) + --index; + else + ++index; + index = (index + items_num) % items_num; + if (index == match_start) + return -1; + } +} + +/* Make a new item. */ +static void item_make(struct menu *menu, char tag, const char *fmt, ...) +{ + va_list ap; + + if (items_num > MAX_MENU_ITEMS-1) + return; + + bzero(&k_menu_items[items_num], sizeof(k_menu_items[0])); + k_menu_items[items_num].tag = tag; + k_menu_items[items_num].usrptr = menu; + if (menu != NULL) + k_menu_items[items_num].is_visible = + menu_is_visible(menu); + else + k_menu_items[items_num].is_visible = 1; + + va_start(ap, fmt); + vsnprintf(k_menu_items[items_num].str, + sizeof(k_menu_items[items_num].str), + fmt, ap); + va_end(ap); + + if (!k_menu_items[items_num].is_visible) + memcpy(k_menu_items[items_num].str, "XXX", 3); + + curses_menu_items[items_num] = new_item( + k_menu_items[items_num].str, + k_menu_items[items_num].str); + set_item_userptr(curses_menu_items[items_num], + &k_menu_items[items_num]); + /* + if (!k_menu_items[items_num].is_visible) + item_opts_off(curses_menu_items[items_num], O_SELECTABLE); + */ + + items_num++; + curses_menu_items[items_num] = NULL; +} + +/* very hackish. adds a string to the last item added */ +static void item_add_str(const char *fmt, ...) +{ + va_list ap; + int index = items_num-1; + char new_str[256]; + char tmp_str[256]; + + if (index < 0) + return; + + va_start(ap, fmt); + vsnprintf(new_str, sizeof(new_str), fmt, ap); + va_end(ap); + snprintf(tmp_str, sizeof(tmp_str), "%s%s", + k_menu_items[index].str, new_str); + strncpy(k_menu_items[index].str, + tmp_str, + sizeof(k_menu_items[index].str)); + + free_item(curses_menu_items[index]); + curses_menu_items[index] = new_item( + k_menu_items[index].str, + k_menu_items[index].str); + set_item_userptr(curses_menu_items[index], + &k_menu_items[index]); +} + +/* get the tag of the currently selected item */ +static char item_tag(void) +{ + ITEM *cur; + struct mitem *mcur; + + cur = current_item(curses_menu); + if (cur == NULL) + return 0; + mcur = (struct mitem *) item_userptr(cur); + return mcur->tag; +} + +static int curses_item_index(void) +{ + return item_index(current_item(curses_menu)); +} + +static void *item_data(void) +{ + ITEM *cur; + struct mitem *mcur; + + cur = current_item(curses_menu); + if (!cur) + return NULL; + mcur = (struct mitem *) item_userptr(cur); + return mcur->usrptr; + +} + +static int item_is_tag(char tag) +{ + return item_tag() == tag; +} + +static char filename[PATH_MAX+1]; +static char menu_backtitle[PATH_MAX+128]; +static const char *set_config_filename(const char *config_filename) +{ + int size; + + size = snprintf(menu_backtitle, sizeof(menu_backtitle), + "%s - %s", config_filename, rootmenu.prompt->text); + if (size >= sizeof(menu_backtitle)) + menu_backtitle[sizeof(menu_backtitle)-1] = '\0'; + + size = snprintf(filename, sizeof(filename), "%s", config_filename); + if (size >= sizeof(filename)) + filename[sizeof(filename)-1] = '\0'; + return menu_backtitle; +} + +/* return = 0 means we are successful. + * -1 means go on doing what you were doing + */ +static int do_exit(void) +{ + int res; + if (!conf_get_changed()) { + global_exit = 1; + return 0; + } + res = btn_dialog(main_window, + _("Do you wish to save your new configuration?\n" + " to cancel and resume nconfig."), + 2, + " ", + ""); + if (res == KEY_EXIT) { + global_exit = 0; + return -1; + } + + /* if we got here, the user really wants to exit */ + switch (res) { + case 0: + res = conf_write(filename); + if (res) + btn_dialog( + main_window, + _("Error during writing of configuration.\n" + "Your configuration changes were NOT saved."), + 1, + ""); + break; + default: + btn_dialog( + main_window, + _("Your configuration changes were NOT saved."), + 1, + ""); + break; + } + global_exit = 1; + return 0; +} + + +static void search_conf(void) +{ + struct symbol **sym_arr; + struct gstr res; + struct gstr title; + char *dialog_input; + int dres; + + title = str_new(); + str_printf( &title, _("Enter (sub)string or regexp to search for " + "(with or without \"%s\")"), CONFIG_); + +again: + dres = dialog_inputbox(main_window, + _("Search Configuration Parameter"), + str_get(&title), + "", &dialog_input_result, &dialog_input_result_len); + switch (dres) { + case 0: + break; + case 1: + show_scroll_win(main_window, + _("Search Configuration"), search_help); + goto again; + default: + str_free(&title); + return; + } + + /* strip the prefix if necessary */ + dialog_input = dialog_input_result; + if (strncasecmp(dialog_input_result, CONFIG_, strlen(CONFIG_)) == 0) + dialog_input += strlen(CONFIG_); + + sym_arr = sym_re_search(dialog_input); + res = get_relations_str(sym_arr, NULL); + free(sym_arr); + show_scroll_win(main_window, + _("Search Results"), str_get(&res)); + str_free(&res); + str_free(&title); +} + + +static void build_conf(struct menu *menu) +{ + struct symbol *sym; + struct property *prop; + struct menu *child; + int type, tmp, doint = 2; + tristate val; + char ch; + + if (!menu || (!show_all_items && !menu_is_visible(menu))) + return; + + sym = menu->sym; + prop = menu->prompt; + if (!sym) { + if (prop && menu != current_menu) { + const char *prompt = menu_get_prompt(menu); + enum prop_type ptype; + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + switch (ptype) { + case P_MENU: + child_count++; + prompt = _(prompt); + if (single_menu_mode) { + item_make(menu, 'm', + "%s%*c%s", + menu->data ? "-->" : "++>", + indent + 1, ' ', prompt); + } else + item_make(menu, 'm', + " %*c%s %s", + indent + 1, ' ', prompt, + menu_is_empty(menu) ? "----" : "--->"); + + if (single_menu_mode && menu->data) + goto conf_childs; + return; + case P_COMMENT: + if (prompt) { + child_count++; + item_make(menu, ':', + " %*c*** %s ***", + indent + 1, ' ', + _(prompt)); + } + break; + default: + if (prompt) { + child_count++; + item_make(menu, ':', "---%*c%s", + indent + 1, ' ', + _(prompt)); + } + } + } else + doint = 0; + goto conf_childs; + } + + type = sym_get_type(sym); + if (sym_is_choice(sym)) { + struct symbol *def_sym = sym_get_choice_value(sym); + struct menu *def_menu = NULL; + + child_count++; + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child) && child->sym == def_sym) + def_menu = child; + } + + val = sym_get_tristate_value(sym); + if (sym_is_changable(sym)) { + switch (type) { + case S_BOOLEAN: + item_make(menu, 't', "[%c]", + val == no ? ' ' : '*'); + break; + case S_TRISTATE: + switch (val) { + case yes: + ch = '*'; + break; + case mod: + ch = 'M'; + break; + default: + ch = ' '; + break; + } + item_make(menu, 't', "<%c>", ch); + break; + } + } else { + item_make(menu, def_menu ? 't' : ':', " "); + } + + item_add_str("%*c%s", indent + 1, + ' ', _(menu_get_prompt(menu))); + if (val == yes) { + if (def_menu) { + item_add_str(" (%s)", + _(menu_get_prompt(def_menu))); + item_add_str(" --->"); + if (def_menu->list) { + indent += 2; + build_conf(def_menu); + indent -= 2; + } + } + return; + } + } else { + if (menu == current_menu) { + item_make(menu, ':', + "---%*c%s", indent + 1, + ' ', _(menu_get_prompt(menu))); + goto conf_childs; + } + child_count++; + val = sym_get_tristate_value(sym); + if (sym_is_choice_value(sym) && val == yes) { + item_make(menu, ':', " "); + } else { + switch (type) { + case S_BOOLEAN: + if (sym_is_changable(sym)) + item_make(menu, 't', "[%c]", + val == no ? ' ' : '*'); + else + item_make(menu, 't', "-%c-", + val == no ? ' ' : '*'); + break; + case S_TRISTATE: + switch (val) { + case yes: + ch = '*'; + break; + case mod: + ch = 'M'; + break; + default: + ch = ' '; + break; + } + if (sym_is_changable(sym)) { + if (sym->rev_dep.tri == mod) + item_make(menu, + 't', "{%c}", ch); + else + item_make(menu, + 't', "<%c>", ch); + } else + item_make(menu, 't', "-%c-", ch); + break; + default: + tmp = 2 + strlen(sym_get_string_value(sym)); + item_make(menu, 's', " (%s)", + sym_get_string_value(sym)); + tmp = indent - tmp + 4; + if (tmp < 0) + tmp = 0; + item_add_str("%*c%s%s", tmp, ' ', + _(menu_get_prompt(menu)), + (sym_has_value(sym) || + !sym_is_changable(sym)) ? "" : + _(" (NEW)")); + goto conf_childs; + } + } + item_add_str("%*c%s%s", indent + 1, ' ', + _(menu_get_prompt(menu)), + (sym_has_value(sym) || !sym_is_changable(sym)) ? + "" : _(" (NEW)")); + if (menu->prompt && menu->prompt->type == P_MENU) { + item_add_str(" %s", menu_is_empty(menu) ? "----" : "--->"); + return; + } + } + +conf_childs: + indent += doint; + for (child = menu->list; child; child = child->next) + build_conf(child); + indent -= doint; +} + +static void reset_menu(void) +{ + unpost_menu(curses_menu); + clean_items(); +} + +/* adjust the menu to show this item. + * prefer not to scroll the menu if possible*/ +static void center_item(int selected_index, int *last_top_row) +{ + int toprow; + + set_top_row(curses_menu, *last_top_row); + toprow = top_row(curses_menu); + if (selected_index < toprow || + selected_index >= toprow+mwin_max_lines) { + toprow = max(selected_index-mwin_max_lines/2, 0); + if (toprow >= item_count(curses_menu)-mwin_max_lines) + toprow = item_count(curses_menu)-mwin_max_lines; + set_top_row(curses_menu, toprow); + } + set_current_item(curses_menu, + curses_menu_items[selected_index]); + *last_top_row = toprow; + post_menu(curses_menu); + refresh_all_windows(main_window); +} + +/* this function assumes reset_menu has been called before */ +static void show_menu(const char *prompt, const char *instructions, + int selected_index, int *last_top_row) +{ + int maxx, maxy; + WINDOW *menu_window; + + current_instructions = instructions; + + clear(); + (void) wattrset(main_window, attributes[NORMAL]); + print_in_middle(stdscr, 1, 0, getmaxx(stdscr), + menu_backtitle, + attributes[MAIN_HEADING]); + + (void) wattrset(main_window, attributes[MAIN_MENU_BOX]); + box(main_window, 0, 0); + (void) wattrset(main_window, attributes[MAIN_MENU_HEADING]); + mvwprintw(main_window, 0, 3, " %s ", prompt); + (void) wattrset(main_window, attributes[NORMAL]); + + set_menu_items(curses_menu, curses_menu_items); + + /* position the menu at the middle of the screen */ + scale_menu(curses_menu, &maxy, &maxx); + maxx = min(maxx, mwin_max_cols-2); + maxy = mwin_max_lines; + menu_window = derwin(main_window, + maxy, + maxx, + 2, + (mwin_max_cols-maxx)/2); + keypad(menu_window, TRUE); + set_menu_win(curses_menu, menu_window); + set_menu_sub(curses_menu, menu_window); + + /* must reassert this after changing items, otherwise returns to a + * default of 16 + */ + set_menu_format(curses_menu, maxy, 1); + center_item(selected_index, last_top_row); + set_menu_format(curses_menu, maxy, 1); + + print_function_line(); + + /* Post the menu */ + post_menu(curses_menu); + refresh_all_windows(main_window); +} + +static void adj_match_dir(match_f *match_direction) +{ + if (*match_direction == FIND_NEXT_MATCH_DOWN) + *match_direction = + MATCH_TINKER_PATTERN_DOWN; + else if (*match_direction == FIND_NEXT_MATCH_UP) + *match_direction = + MATCH_TINKER_PATTERN_UP; + /* else, do no change.. */ +} + +struct match_state +{ + int in_search; + match_f match_direction; + char pattern[256]; +}; + +/* Return 0 means I have handled the key. In such a case, ans should hold the + * item to center, or -1 otherwise. + * Else return -1 . + */ +static int do_match(int key, struct match_state *state, int *ans) +{ + char c = (char) key; + int terminate_search = 0; + *ans = -1; + if (key == '/' || (state->in_search && key == 27)) { + move(0, 0); + refresh(); + clrtoeol(); + state->in_search = 1-state->in_search; + bzero(state->pattern, sizeof(state->pattern)); + state->match_direction = MATCH_TINKER_PATTERN_DOWN; + return 0; + } else if (!state->in_search) + return 1; + + if (isalnum(c) || isgraph(c) || c == ' ') { + state->pattern[strlen(state->pattern)] = c; + state->pattern[strlen(state->pattern)] = '\0'; + adj_match_dir(&state->match_direction); + *ans = get_mext_match(state->pattern, + state->match_direction); + } else if (key == KEY_DOWN) { + state->match_direction = FIND_NEXT_MATCH_DOWN; + *ans = get_mext_match(state->pattern, + state->match_direction); + } else if (key == KEY_UP) { + state->match_direction = FIND_NEXT_MATCH_UP; + *ans = get_mext_match(state->pattern, + state->match_direction); + } else if (key == KEY_BACKSPACE || key == 127) { + state->pattern[strlen(state->pattern)-1] = '\0'; + adj_match_dir(&state->match_direction); + } else + terminate_search = 1; + + if (terminate_search) { + state->in_search = 0; + bzero(state->pattern, sizeof(state->pattern)); + move(0, 0); + refresh(); + clrtoeol(); + return -1; + } + return 0; +} + +static void conf(struct menu *menu) +{ + struct menu *submenu = 0; + const char *prompt = menu_get_prompt(menu); + struct symbol *sym; + int res; + int current_index = 0; + int last_top_row = 0; + struct match_state match_state = { + .in_search = 0, + .match_direction = MATCH_TINKER_PATTERN_DOWN, + .pattern = "", + }; + + while (!global_exit) { + reset_menu(); + current_menu = menu; + build_conf(menu); + if (!child_count) + break; + + show_menu(prompt ? _(prompt) : _("Main Menu"), + _(menu_instructions), + current_index, &last_top_row); + keypad((menu_win(curses_menu)), TRUE); + while (!global_exit) { + if (match_state.in_search) { + mvprintw(0, 0, + "searching: %s", match_state.pattern); + clrtoeol(); + } + refresh_all_windows(main_window); + res = wgetch(menu_win(curses_menu)); + if (!res) + break; + if (do_match(res, &match_state, ¤t_index) == 0) { + if (current_index != -1) + center_item(current_index, + &last_top_row); + continue; + } + if (process_special_keys(&res, + (struct menu *) item_data())) + break; + switch (res) { + case KEY_DOWN: + menu_driver(curses_menu, REQ_DOWN_ITEM); + break; + case KEY_UP: + menu_driver(curses_menu, REQ_UP_ITEM); + break; + case KEY_NPAGE: + menu_driver(curses_menu, REQ_SCR_DPAGE); + break; + case KEY_PPAGE: + menu_driver(curses_menu, REQ_SCR_UPAGE); + break; + case KEY_HOME: + menu_driver(curses_menu, REQ_FIRST_ITEM); + break; + case KEY_END: + menu_driver(curses_menu, REQ_LAST_ITEM); + break; + case 'h': + case '?': + show_help((struct menu *) item_data()); + break; + } + if (res == 10 || res == 27 || + res == 32 || res == 'n' || res == 'y' || + res == KEY_LEFT || res == KEY_RIGHT || + res == 'm') + break; + refresh_all_windows(main_window); + } + + refresh_all_windows(main_window); + /* if ESC or left*/ + if (res == 27 || (menu != &rootmenu && res == KEY_LEFT)) + break; + + /* remember location in the menu */ + last_top_row = top_row(curses_menu); + current_index = curses_item_index(); + + if (!item_tag()) + continue; + + submenu = (struct menu *) item_data(); + if (!submenu || !menu_is_visible(submenu)) + continue; + sym = submenu->sym; + + switch (res) { + case ' ': + if (item_is_tag('t')) + sym_toggle_tristate_value(sym); + else if (item_is_tag('m')) + conf(submenu); + break; + case KEY_RIGHT: + case 10: /* ENTER WAS PRESSED */ + switch (item_tag()) { + case 'm': + if (single_menu_mode) + submenu->data = + (void *) (long) !submenu->data; + else + conf(submenu); + break; + case 't': + if (sym_is_choice(sym) && + sym_get_tristate_value(sym) == yes) + conf_choice(submenu); + else if (submenu->prompt && + submenu->prompt->type == P_MENU) + conf(submenu); + else if (res == 10) + sym_toggle_tristate_value(sym); + break; + case 's': + conf_string(submenu); + break; + } + break; + case 'y': + if (item_is_tag('t')) { + if (sym_set_tristate_value(sym, yes)) + break; + if (sym_set_tristate_value(sym, mod)) + btn_dialog(main_window, setmod_text, 0); + } + break; + case 'n': + if (item_is_tag('t')) + sym_set_tristate_value(sym, no); + break; + case 'm': + if (item_is_tag('t')) + sym_set_tristate_value(sym, mod); + break; + } + } +} + +static void conf_message_callback(const char *fmt, va_list ap) +{ + char buf[1024]; + + vsnprintf(buf, sizeof(buf), fmt, ap); + btn_dialog(main_window, buf, 1, ""); +} + +static void show_help(struct menu *menu) +{ + struct gstr help; + + if (!menu) + return; + + help = str_new(); + menu_get_ext_help(menu, &help); + show_scroll_win(main_window, _(menu_get_prompt(menu)), str_get(&help)); + str_free(&help); +} + +static void conf_choice(struct menu *menu) +{ + const char *prompt = _(menu_get_prompt(menu)); + struct menu *child = 0; + struct symbol *active; + int selected_index = 0; + int last_top_row = 0; + int res, i = 0; + struct match_state match_state = { + .in_search = 0, + .match_direction = MATCH_TINKER_PATTERN_DOWN, + .pattern = "", + }; + + active = sym_get_choice_value(menu->sym); + /* this is mostly duplicated from the conf() function. */ + while (!global_exit) { + reset_menu(); + + for (i = 0, child = menu->list; child; child = child->next) { + if (!show_all_items && !menu_is_visible(child)) + continue; + + if (child->sym == sym_get_choice_value(menu->sym)) + item_make(child, ':', " %s", + _(menu_get_prompt(child))); + else if (child->sym) + item_make(child, ':', " %s", + _(menu_get_prompt(child))); + else + item_make(child, ':', "*** %s ***", + _(menu_get_prompt(child))); + + if (child->sym == active){ + last_top_row = top_row(curses_menu); + selected_index = i; + } + i++; + } + show_menu(prompt ? _(prompt) : _("Choice Menu"), + _(radiolist_instructions), + selected_index, + &last_top_row); + while (!global_exit) { + if (match_state.in_search) { + mvprintw(0, 0, "searching: %s", + match_state.pattern); + clrtoeol(); + } + refresh_all_windows(main_window); + res = wgetch(menu_win(curses_menu)); + if (!res) + break; + if (do_match(res, &match_state, &selected_index) == 0) { + if (selected_index != -1) + center_item(selected_index, + &last_top_row); + continue; + } + if (process_special_keys( + &res, + (struct menu *) item_data())) + break; + switch (res) { + case KEY_DOWN: + menu_driver(curses_menu, REQ_DOWN_ITEM); + break; + case KEY_UP: + menu_driver(curses_menu, REQ_UP_ITEM); + break; + case KEY_NPAGE: + menu_driver(curses_menu, REQ_SCR_DPAGE); + break; + case KEY_PPAGE: + menu_driver(curses_menu, REQ_SCR_UPAGE); + break; + case KEY_HOME: + menu_driver(curses_menu, REQ_FIRST_ITEM); + break; + case KEY_END: + menu_driver(curses_menu, REQ_LAST_ITEM); + break; + case 'h': + case '?': + show_help((struct menu *) item_data()); + break; + } + if (res == 10 || res == 27 || res == ' ' || + res == KEY_LEFT){ + break; + } + refresh_all_windows(main_window); + } + /* if ESC or left */ + if (res == 27 || res == KEY_LEFT) + break; + + child = item_data(); + if (!child || !menu_is_visible(child) || !child->sym) + continue; + switch (res) { + case ' ': + case 10: + case KEY_RIGHT: + sym_set_tristate_value(child->sym, yes); + return; + case 'h': + case '?': + show_help(child); + active = child->sym; + break; + case KEY_EXIT: + return; + } + } +} + +static void conf_string(struct menu *menu) +{ + const char *prompt = menu_get_prompt(menu); + + while (1) { + int res; + const char *heading; + + switch (sym_get_type(menu->sym)) { + case S_INT: + heading = _(inputbox_instructions_int); + break; + case S_HEX: + heading = _(inputbox_instructions_hex); + break; + case S_STRING: + heading = _(inputbox_instructions_string); + break; + default: + heading = _("Internal nconf error!"); + } + res = dialog_inputbox(main_window, + prompt ? _(prompt) : _("Main Menu"), + heading, + sym_get_string_value(menu->sym), + &dialog_input_result, + &dialog_input_result_len); + switch (res) { + case 0: + if (sym_set_string_value(menu->sym, + dialog_input_result)) + return; + btn_dialog(main_window, + _("You have made an invalid entry."), 0); + break; + case 1: + show_help(menu); + break; + case KEY_EXIT: + return; + } + } +} + +static void conf_load(void) +{ + while (1) { + int res; + res = dialog_inputbox(main_window, + NULL, load_config_text, + filename, + &dialog_input_result, + &dialog_input_result_len); + switch (res) { + case 0: + if (!dialog_input_result[0]) + return; + if (!conf_read(dialog_input_result)) { + set_config_filename(dialog_input_result); + sym_set_change_count(1); + return; + } + btn_dialog(main_window, _("File does not exist!"), 0); + break; + case 1: + show_scroll_win(main_window, + _("Load Alternate Configuration"), + load_config_help); + break; + case KEY_EXIT: + return; + } + } +} + +static void conf_save(void) +{ + while (1) { + int res; + res = dialog_inputbox(main_window, + NULL, save_config_text, + filename, + &dialog_input_result, + &dialog_input_result_len); + switch (res) { + case 0: + if (!dialog_input_result[0]) + return; + res = conf_write(dialog_input_result); + if (!res) { + set_config_filename(dialog_input_result); + return; + } + btn_dialog(main_window, _("Can't create file! " + "Probably a nonexistent directory."), + 1, ""); + break; + case 1: + show_scroll_win(main_window, + _("Save Alternate Configuration"), + save_config_help); + break; + case KEY_EXIT: + return; + } + } +} + +void setup_windows(void) +{ + int lines, columns; + + getmaxyx(stdscr, lines, columns); + + if (main_window != NULL) + delwin(main_window); + + /* set up the menu and menu window */ + main_window = newwin(lines-2, columns-2, 2, 1); + keypad(main_window, TRUE); + mwin_max_lines = lines-7; + mwin_max_cols = columns-6; + + /* panels order is from bottom to top */ + new_panel(main_window); +} + +int main(int ac, char **av) +{ + int lines, columns; + char *mode; + + setlocale(LC_ALL, ""); + bindtextdomain(PACKAGE, LOCALEDIR); + textdomain(PACKAGE); + + conf_parse(av[1]); + conf_read(NULL); + + mode = getenv("NCONFIG_MODE"); + if (mode) { + if (!strcasecmp(mode, "single_menu")) + single_menu_mode = 1; + } + + /* Initialize curses */ + initscr(); + /* set color theme */ + set_colors(); + + cbreak(); + noecho(); + keypad(stdscr, TRUE); + curs_set(0); + + getmaxyx(stdscr, lines, columns); + if (columns < 75 || lines < 20) { + endwin(); + printf("Your terminal should have at " + "least 20 lines and 75 columns\n"); + return 1; + } + + notimeout(stdscr, FALSE); +#if NCURSES_REENTRANT + set_escdelay(1); +#else + ESCDELAY = 1; +#endif + + /* set btns menu */ + curses_menu = new_menu(curses_menu_items); + menu_opts_off(curses_menu, O_SHOWDESC); + menu_opts_on(curses_menu, O_SHOWMATCH); + menu_opts_on(curses_menu, O_ONEVALUE); + menu_opts_on(curses_menu, O_NONCYCLIC); + menu_opts_on(curses_menu, O_IGNORECASE); + set_menu_mark(curses_menu, " "); + set_menu_fore(curses_menu, attributes[MAIN_MENU_FORE]); + set_menu_back(curses_menu, attributes[MAIN_MENU_BACK]); + set_menu_grey(curses_menu, attributes[MAIN_MENU_GREY]); + + set_config_filename(conf_get_configname()); + setup_windows(); + + /* check for KEY_FUNC(1) */ + if (has_key(KEY_F(1)) == FALSE) { + show_scroll_win(main_window, + _("Instructions"), + _(menu_no_f_instructions)); + } + + conf_set_message_callback(conf_message_callback); + /* do the work */ + while (!global_exit) { + conf(&rootmenu); + if (!global_exit && do_exit() == 0) + break; + } + /* ok, we are done */ + unpost_menu(curses_menu); + free_menu(curses_menu); + delwin(main_window); + clear(); + refresh(); + endwin(); + return 0; +} diff --git a/scripts/kconfig/nconf.gui.c b/scripts/kconfig/nconf.gui.c new file mode 100644 index 0000000000..8275f0e551 --- /dev/null +++ b/scripts/kconfig/nconf.gui.c @@ -0,0 +1,656 @@ +/* + * Copyright (C) 2008 Nir Tzachar 0) + win_rows = msg_lines+4; + else + win_rows = msg_lines+2; + + win = newwin(win_rows, total_width+4, y, x); + keypad(win, TRUE); + menu_win = derwin(win, 1, btns_width, win_rows-2, + 1+(total_width+2-btns_width)/2); + menu = new_menu(btns); + msg_win = derwin(win, win_rows-2, msg_width, 1, + 1+(total_width+2-msg_width)/2); + + set_menu_fore(menu, attributes[DIALOG_MENU_FORE]); + set_menu_back(menu, attributes[DIALOG_MENU_BACK]); + + (void) wattrset(win, attributes[DIALOG_BOX]); + box(win, 0, 0); + + /* print message */ + (void) wattrset(msg_win, attributes[DIALOG_TEXT]); + fill_window(msg_win, msg); + + set_menu_win(menu, win); + set_menu_sub(menu, menu_win); + set_menu_format(menu, 1, btn_num); + menu_opts_off(menu, O_SHOWDESC); + menu_opts_off(menu, O_SHOWMATCH); + menu_opts_on(menu, O_ONEVALUE); + menu_opts_on(menu, O_NONCYCLIC); + set_menu_mark(menu, ""); + post_menu(menu); + + + touchwin(win); + refresh_all_windows(main_window); + while ((res = wgetch(win))) { + switch (res) { + case KEY_LEFT: + menu_driver(menu, REQ_LEFT_ITEM); + break; + case KEY_RIGHT: + menu_driver(menu, REQ_RIGHT_ITEM); + break; + case 10: /* ENTER */ + case 27: /* ESCAPE */ + case ' ': + case KEY_F(F_BACK): + case KEY_F(F_EXIT): + break; + } + touchwin(win); + refresh_all_windows(main_window); + + if (res == 10 || res == ' ') { + res = item_index(current_item(menu)); + break; + } else if (res == 27 || res == KEY_F(F_BACK) || + res == KEY_F(F_EXIT)) { + res = KEY_EXIT; + break; + } + } + + unpost_menu(menu); + free_menu(menu); + for (i = 0; i < btn_num; i++) + free_item(btns[i]); + + delwin(win); + return res; +} + +int dialog_inputbox(WINDOW *main_window, + const char *title, const char *prompt, + const char *init, char **resultp, int *result_len) +{ + int prompt_lines = 0; + int prompt_width = 0; + WINDOW *win; + WINDOW *prompt_win; + WINDOW *form_win; + PANEL *panel; + int i, x, y; + int res = -1; + int cursor_position = strlen(init); + int cursor_form_win; + char *result = *resultp; + + if (strlen(init)+1 > *result_len) { + *result_len = strlen(init)+1; + *resultp = result = realloc(result, *result_len); + } + + /* find the widest line of msg: */ + prompt_lines = get_line_no(prompt); + for (i = 0; i < prompt_lines; i++) { + const char *line = get_line(prompt, i); + int len = get_line_length(line); + prompt_width = max(prompt_width, len); + } + + if (title) + prompt_width = max(prompt_width, strlen(title)); + + /* place dialog in middle of screen */ + y = (getmaxy(stdscr)-(prompt_lines+4))/2; + x = (getmaxx(stdscr)-(prompt_width+4))/2; + + strncpy(result, init, *result_len); + + /* create the windows */ + win = newwin(prompt_lines+6, prompt_width+7, y, x); + prompt_win = derwin(win, prompt_lines+1, prompt_width, 2, 2); + form_win = derwin(win, 1, prompt_width, prompt_lines+3, 2); + keypad(form_win, TRUE); + + (void) wattrset(form_win, attributes[INPUT_FIELD]); + + (void) wattrset(win, attributes[INPUT_BOX]); + box(win, 0, 0); + (void) wattrset(win, attributes[INPUT_HEADING]); + if (title) + mvwprintw(win, 0, 3, "%s", title); + + /* print message */ + (void) wattrset(prompt_win, attributes[INPUT_TEXT]); + fill_window(prompt_win, prompt); + + mvwprintw(form_win, 0, 0, "%*s", prompt_width, " "); + cursor_form_win = min(cursor_position, prompt_width-1); + mvwprintw(form_win, 0, 0, "%s", + result + cursor_position-cursor_form_win); + + /* create panels */ + panel = new_panel(win); + + /* show the cursor */ + curs_set(1); + + touchwin(win); + refresh_all_windows(main_window); + while ((res = wgetch(form_win))) { + int len = strlen(result); + switch (res) { + case 10: /* ENTER */ + case 27: /* ESCAPE */ + case KEY_F(F_HELP): + case KEY_F(F_EXIT): + case KEY_F(F_BACK): + break; + case 127: + case KEY_BACKSPACE: + if (cursor_position > 0) { + memmove(&result[cursor_position-1], + &result[cursor_position], + len-cursor_position+1); + cursor_position--; + cursor_form_win--; + len--; + } + break; + case KEY_DC: + if (cursor_position >= 0 && cursor_position < len) { + memmove(&result[cursor_position], + &result[cursor_position+1], + len-cursor_position+1); + len--; + } + break; + case KEY_UP: + case KEY_RIGHT: + if (cursor_position < len) { + cursor_position++; + cursor_form_win++; + } + break; + case KEY_DOWN: + case KEY_LEFT: + if (cursor_position > 0) { + cursor_position--; + cursor_form_win--; + } + break; + case KEY_HOME: + cursor_position = 0; + cursor_form_win = 0; + break; + case KEY_END: + cursor_position = len; + cursor_form_win = min(cursor_position, prompt_width-1); + break; + default: + if ((isgraph(res) || isspace(res))) { + /* one for new char, one for '\0' */ + if (len+2 > *result_len) { + *result_len = len+2; + *resultp = result = realloc(result, + *result_len); + } + /* insert the char at the proper position */ + memmove(&result[cursor_position+1], + &result[cursor_position], + len-cursor_position+1); + result[cursor_position] = res; + cursor_position++; + cursor_form_win++; + len++; + } else { + mvprintw(0, 0, "unknown key: %d\n", res); + } + break; + } + if (cursor_form_win < 0) + cursor_form_win = 0; + else if (cursor_form_win > prompt_width-1) + cursor_form_win = prompt_width-1; + + wmove(form_win, 0, 0); + wclrtoeol(form_win); + mvwprintw(form_win, 0, 0, "%*s", prompt_width, " "); + mvwprintw(form_win, 0, 0, "%s", + result + cursor_position-cursor_form_win); + wmove(form_win, 0, cursor_form_win); + touchwin(win); + refresh_all_windows(main_window); + + if (res == 10) { + res = 0; + break; + } else if (res == 27 || res == KEY_F(F_BACK) || + res == KEY_F(F_EXIT)) { + res = KEY_EXIT; + break; + } else if (res == KEY_F(F_HELP)) { + res = 1; + break; + } + } + + /* hide the cursor */ + curs_set(0); + del_panel(panel); + delwin(prompt_win); + delwin(form_win); + delwin(win); + return res; +} + +/* refresh all windows in the correct order */ +void refresh_all_windows(WINDOW *main_window) +{ + update_panels(); + touchwin(main_window); + refresh(); +} + +/* layman's scrollable window... */ +void show_scroll_win(WINDOW *main_window, + const char *title, + const char *text) +{ + int res; + int total_lines = get_line_no(text); + int x, y, lines, columns; + int start_x = 0, start_y = 0; + int text_lines = 0, text_cols = 0; + int total_cols = 0; + int win_cols = 0; + int win_lines = 0; + int i = 0; + WINDOW *win; + WINDOW *pad; + PANEL *panel; + + getmaxyx(stdscr, lines, columns); + + /* find the widest line of msg: */ + total_lines = get_line_no(text); + for (i = 0; i < total_lines; i++) { + const char *line = get_line(text, i); + int len = get_line_length(line); + total_cols = max(total_cols, len+2); + } + + /* create the pad */ + pad = newpad(total_lines+10, total_cols+10); + (void) wattrset(pad, attributes[SCROLLWIN_TEXT]); + fill_window(pad, text); + + win_lines = min(total_lines+4, lines-2); + win_cols = min(total_cols+2, columns-2); + text_lines = max(win_lines-4, 0); + text_cols = max(win_cols-2, 0); + + /* place window in middle of screen */ + y = (lines-win_lines)/2; + x = (columns-win_cols)/2; + + win = newwin(win_lines, win_cols, y, x); + keypad(win, TRUE); + /* show the help in the help window, and show the help panel */ + (void) wattrset(win, attributes[SCROLLWIN_BOX]); + box(win, 0, 0); + (void) wattrset(win, attributes[SCROLLWIN_HEADING]); + mvwprintw(win, 0, 3, " %s ", title); + panel = new_panel(win); + + /* handle scrolling */ + do { + + copywin(pad, win, start_y, start_x, 2, 2, text_lines, + text_cols, 0); + print_in_middle(win, + text_lines+2, + 0, + text_cols, + "", + attributes[DIALOG_MENU_FORE]); + wrefresh(win); + + res = wgetch(win); + switch (res) { + case KEY_NPAGE: + case ' ': + case 'd': + start_y += text_lines-2; + break; + case KEY_PPAGE: + case 'u': + start_y -= text_lines+2; + break; + case KEY_HOME: + start_y = 0; + break; + case KEY_END: + start_y = total_lines-text_lines; + break; + case KEY_DOWN: + case 'j': + start_y++; + break; + case KEY_UP: + case 'k': + start_y--; + break; + case KEY_LEFT: + case 'h': + start_x--; + break; + case KEY_RIGHT: + case 'l': + start_x++; + break; + } + if (res == 10 || res == 27 || res == 'q' || + res == KEY_F(F_HELP) || res == KEY_F(F_BACK) || + res == KEY_F(F_EXIT)) + break; + if (start_y < 0) + start_y = 0; + if (start_y >= total_lines-text_lines) + start_y = total_lines-text_lines; + if (start_x < 0) + start_x = 0; + if (start_x >= total_cols-text_cols) + start_x = total_cols-text_cols; + } while (res); + + del_panel(panel); + delwin(win); + refresh_all_windows(main_window); +} diff --git a/scripts/kconfig/nconf.h b/scripts/kconfig/nconf.h new file mode 100644 index 0000000000..0d5261705e --- /dev/null +++ b/scripts/kconfig/nconf.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2008 Nir Tzachar +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "ncurses.h" + +#define max(a, b) ({\ + typeof(a) _a = a;\ + typeof(b) _b = b;\ + _a > _b ? _a : _b; }) + +#define min(a, b) ({\ + typeof(a) _a = a;\ + typeof(b) _b = b;\ + _a < _b ? _a : _b; }) + +typedef enum { + NORMAL = 1, + MAIN_HEADING, + MAIN_MENU_BOX, + MAIN_MENU_FORE, + MAIN_MENU_BACK, + MAIN_MENU_GREY, + MAIN_MENU_HEADING, + SCROLLWIN_TEXT, + SCROLLWIN_HEADING, + SCROLLWIN_BOX, + DIALOG_TEXT, + DIALOG_MENU_FORE, + DIALOG_MENU_BACK, + DIALOG_BOX, + INPUT_BOX, + INPUT_HEADING, + INPUT_TEXT, + INPUT_FIELD, + FUNCTION_TEXT, + FUNCTION_HIGHLIGHT, + ATTR_MAX +} attributes_t; +extern attributes_t attributes[]; + +typedef enum { + F_HELP = 1, + F_SYMBOL = 2, + F_INSTS = 3, + F_CONF = 4, + F_BACK = 5, + F_SAVE = 6, + F_LOAD = 7, + F_SEARCH = 8, + F_EXIT = 9, +} function_key; + +void set_colors(void); + +/* this changes the windows attributes !!! */ +void print_in_middle(WINDOW *win, + int starty, + int startx, + int width, + const char *string, + chtype color); +int get_line_length(const char *line); +int get_line_no(const char *text); +const char *get_line(const char *text, int line_no); +void fill_window(WINDOW *win, const char *text); +int btn_dialog(WINDOW *main_window, const char *msg, int btn_num, ...); +int dialog_inputbox(WINDOW *main_window, + const char *title, const char *prompt, + const char *init, char **resultp, int *result_len); +void refresh_all_windows(WINDOW *main_window); +void show_scroll_win(WINDOW *main_window, + const char *title, + const char *text); diff --git a/scripts/kconfig/qconf.cc b/scripts/kconfig/qconf.cc new file mode 100644 index 0000000000..9d3b04b076 --- /dev/null +++ b/scripts/kconfig/qconf.cc @@ -0,0 +1,1795 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include + +#if QT_VERSION < 0x040000 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#else +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "lkc.h" +#include "qconf.h" + +#include "qconf.moc" +#include "images.c" + +#ifdef _ +# undef _ +# define _ qgettext +#endif + +static QApplication *configApp; +static ConfigSettings *configSettings; + +Q3Action *ConfigMainWindow::saveAction; + +static inline QString qgettext(const char* str) +{ + return QString::fromLocal8Bit(gettext(str)); +} + +static inline QString qgettext(const QString& str) +{ + return QString::fromLocal8Bit(gettext(str.latin1())); +} + +ConfigSettings::ConfigSettings() + : QSettings("kernel.org", "qconf") +{ +} + +/** + * Reads a list of integer values from the application settings. + */ +Q3ValueList ConfigSettings::readSizes(const QString& key, bool *ok) +{ + Q3ValueList result; + QStringList entryList = readListEntry(key, ok); + QStringList::Iterator it; + + for (it = entryList.begin(); it != entryList.end(); ++it) + result.push_back((*it).toInt()); + + return result; +} + +/** + * Writes a list of integer values to the application settings. + */ +bool ConfigSettings::writeSizes(const QString& key, const Q3ValueList& value) +{ + QStringList stringList; + Q3ValueList::ConstIterator it; + + for (it = value.begin(); it != value.end(); ++it) + stringList.push_back(QString::number(*it)); + return writeEntry(key, stringList); +} + + +/* + * set the new data + * TODO check the value + */ +void ConfigItem::okRename(int col) +{ + Parent::okRename(col); + sym_set_string_value(menu->sym, text(dataColIdx).latin1()); + listView()->updateList(this); +} + +/* + * update the displayed of a menu entry + */ +void ConfigItem::updateMenu(void) +{ + ConfigList* list; + struct symbol* sym; + struct property *prop; + QString prompt; + int type; + tristate expr; + + list = listView(); + if (goParent) { + setPixmap(promptColIdx, list->menuBackPix); + prompt = ".."; + goto set_prompt; + } + + sym = menu->sym; + prop = menu->prompt; + prompt = _(menu_get_prompt(menu)); + + if (prop) switch (prop->type) { + case P_MENU: + if (list->mode == singleMode || list->mode == symbolMode) { + /* a menuconfig entry is displayed differently + * depending whether it's at the view root or a child. + */ + if (sym && list->rootEntry == menu) + break; + setPixmap(promptColIdx, list->menuPix); + } else { + if (sym) + break; + setPixmap(promptColIdx, 0); + } + goto set_prompt; + case P_COMMENT: + setPixmap(promptColIdx, 0); + goto set_prompt; + default: + ; + } + if (!sym) + goto set_prompt; + + setText(nameColIdx, QString::fromLocal8Bit(sym->name)); + + type = sym_get_type(sym); + switch (type) { + case S_BOOLEAN: + case S_TRISTATE: + char ch; + + if (!sym_is_changable(sym) && list->optMode == normalOpt) { + setPixmap(promptColIdx, 0); + setText(noColIdx, QString::null); + setText(modColIdx, QString::null); + setText(yesColIdx, QString::null); + break; + } + expr = sym_get_tristate_value(sym); + switch (expr) { + case yes: + if (sym_is_choice_value(sym) && type == S_BOOLEAN) + setPixmap(promptColIdx, list->choiceYesPix); + else + setPixmap(promptColIdx, list->symbolYesPix); + setText(yesColIdx, "Y"); + ch = 'Y'; + break; + case mod: + setPixmap(promptColIdx, list->symbolModPix); + setText(modColIdx, "M"); + ch = 'M'; + break; + default: + if (sym_is_choice_value(sym) && type == S_BOOLEAN) + setPixmap(promptColIdx, list->choiceNoPix); + else + setPixmap(promptColIdx, list->symbolNoPix); + setText(noColIdx, "N"); + ch = 'N'; + break; + } + if (expr != no) + setText(noColIdx, sym_tristate_within_range(sym, no) ? "_" : 0); + if (expr != mod) + setText(modColIdx, sym_tristate_within_range(sym, mod) ? "_" : 0); + if (expr != yes) + setText(yesColIdx, sym_tristate_within_range(sym, yes) ? "_" : 0); + + setText(dataColIdx, QChar(ch)); + break; + case S_INT: + case S_HEX: + case S_STRING: + const char* data; + + data = sym_get_string_value(sym); + + int i = list->mapIdx(dataColIdx); + if (i >= 0) + setRenameEnabled(i, TRUE); + setText(dataColIdx, data); + if (type == S_STRING) + prompt = QString("%1: %2").arg(prompt).arg(data); + else + prompt = QString("(%2) %1").arg(prompt).arg(data); + break; + } + if (!sym_has_value(sym) && visible) + prompt += _(" (NEW)"); +set_prompt: + setText(promptColIdx, prompt); +} + +void ConfigItem::testUpdateMenu(bool v) +{ + ConfigItem* i; + + visible = v; + if (!menu) + return; + + sym_calc_value(menu->sym); + if (menu->flags & MENU_CHANGED) { + /* the menu entry changed, so update all list items */ + menu->flags &= ~MENU_CHANGED; + for (i = (ConfigItem*)menu->data; i; i = i->nextItem) + i->updateMenu(); + } else if (listView()->updateAll) + updateMenu(); +} + +void ConfigItem::paintCell(QPainter* p, const QColorGroup& cg, int column, int width, int align) +{ + ConfigList* list = listView(); + + if (visible) { + if (isSelected() && !list->hasFocus() && list->mode == menuMode) + Parent::paintCell(p, list->inactivedColorGroup, column, width, align); + else + Parent::paintCell(p, cg, column, width, align); + } else + Parent::paintCell(p, list->disabledColorGroup, column, width, align); +} + +/* + * construct a menu entry + */ +void ConfigItem::init(void) +{ + if (menu) { + ConfigList* list = listView(); + nextItem = (ConfigItem*)menu->data; + menu->data = this; + + if (list->mode != fullMode) + setOpen(TRUE); + sym_calc_value(menu->sym); + } + updateMenu(); +} + +/* + * destruct a menu entry + */ +ConfigItem::~ConfigItem(void) +{ + if (menu) { + ConfigItem** ip = (ConfigItem**)&menu->data; + for (; *ip; ip = &(*ip)->nextItem) { + if (*ip == this) { + *ip = nextItem; + break; + } + } + } +} + +ConfigLineEdit::ConfigLineEdit(ConfigView* parent) + : Parent(parent) +{ + connect(this, SIGNAL(lostFocus()), SLOT(hide())); +} + +void ConfigLineEdit::show(ConfigItem* i) +{ + item = i; + if (sym_get_string_value(item->menu->sym)) + setText(QString::fromLocal8Bit(sym_get_string_value(item->menu->sym))); + else + setText(QString::null); + Parent::show(); + setFocus(); +} + +void ConfigLineEdit::keyPressEvent(QKeyEvent* e) +{ + switch (e->key()) { + case Qt::Key_Escape: + break; + case Qt::Key_Return: + case Qt::Key_Enter: + sym_set_string_value(item->menu->sym, text().latin1()); + parent()->updateList(item); + break; + default: + Parent::keyPressEvent(e); + return; + } + e->accept(); + parent()->list->setFocus(); + hide(); +} + +ConfigList::ConfigList(ConfigView* p, const char *name) + : Parent(p, name), + updateAll(false), + symbolYesPix(xpm_symbol_yes), symbolModPix(xpm_symbol_mod), symbolNoPix(xpm_symbol_no), + choiceYesPix(xpm_choice_yes), choiceNoPix(xpm_choice_no), + menuPix(xpm_menu), menuInvPix(xpm_menu_inv), menuBackPix(xpm_menuback), voidPix(xpm_void), + showName(false), showRange(false), showData(false), optMode(normalOpt), + rootEntry(0), headerPopup(0) +{ + int i; + + setSorting(-1); + setRootIsDecorated(TRUE); + disabledColorGroup = palette().active(); + disabledColorGroup.setColor(QColorGroup::Text, palette().disabled().text()); + inactivedColorGroup = palette().active(); + inactivedColorGroup.setColor(QColorGroup::Highlight, palette().disabled().highlight()); + + connect(this, SIGNAL(selectionChanged(void)), + SLOT(updateSelection(void))); + + if (name) { + configSettings->beginGroup(name); + showName = configSettings->readBoolEntry("/showName", false); + showRange = configSettings->readBoolEntry("/showRange", false); + showData = configSettings->readBoolEntry("/showData", false); + optMode = (enum optionMode)configSettings->readNumEntry("/optionMode", false); + configSettings->endGroup(); + connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); + } + + for (i = 0; i < colNr; i++) + colMap[i] = colRevMap[i] = -1; + addColumn(promptColIdx, _("Option")); + + reinit(); +} + +bool ConfigList::menuSkip(struct menu *menu) +{ + if (optMode == normalOpt && menu_is_visible(menu)) + return false; + if (optMode == promptOpt && menu_has_prompt(menu)) + return false; + if (optMode == allOpt) + return false; + return true; +} + +void ConfigList::reinit(void) +{ + removeColumn(dataColIdx); + removeColumn(yesColIdx); + removeColumn(modColIdx); + removeColumn(noColIdx); + removeColumn(nameColIdx); + + if (showName) + addColumn(nameColIdx, _("Name")); + if (showRange) { + addColumn(noColIdx, "N"); + addColumn(modColIdx, "M"); + addColumn(yesColIdx, "Y"); + } + if (showData) + addColumn(dataColIdx, _("Value")); + + updateListAll(); +} + +void ConfigList::saveSettings(void) +{ + if (name()) { + configSettings->beginGroup(name()); + configSettings->writeEntry("/showName", showName); + configSettings->writeEntry("/showRange", showRange); + configSettings->writeEntry("/showData", showData); + configSettings->writeEntry("/optionMode", (int)optMode); + configSettings->endGroup(); + } +} + +ConfigItem* ConfigList::findConfigItem(struct menu *menu) +{ + ConfigItem* item = (ConfigItem*)menu->data; + + for (; item; item = item->nextItem) { + if (this == item->listView()) + break; + } + + return item; +} + +void ConfigList::updateSelection(void) +{ + struct menu *menu; + enum prop_type type; + + ConfigItem* item = (ConfigItem*)selectedItem(); + if (!item) + return; + + menu = item->menu; + emit menuChanged(menu); + if (!menu) + return; + type = menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (mode == menuMode && type == P_MENU) + emit menuSelected(menu); +} + +void ConfigList::updateList(ConfigItem* item) +{ + ConfigItem* last = 0; + + if (!rootEntry) { + if (mode != listMode) + goto update; + Q3ListViewItemIterator it(this); + ConfigItem* item; + + for (; it.current(); ++it) { + item = (ConfigItem*)it.current(); + if (!item->menu) + continue; + item->testUpdateMenu(menu_is_visible(item->menu)); + } + return; + } + + if (rootEntry != &rootmenu && (mode == singleMode || + (mode == symbolMode && rootEntry->parent != &rootmenu))) { + item = firstChild(); + if (!item) + item = new ConfigItem(this, 0, true); + last = item; + } + if ((mode == singleMode || (mode == symbolMode && !(rootEntry->flags & MENU_ROOT))) && + rootEntry->sym && rootEntry->prompt) { + item = last ? last->nextSibling() : firstChild(); + if (!item) + item = new ConfigItem(this, last, rootEntry, true); + else + item->testUpdateMenu(true); + + updateMenuList(item, rootEntry); + triggerUpdate(); + return; + } +update: + updateMenuList(this, rootEntry); + triggerUpdate(); +} + +void ConfigList::setValue(ConfigItem* item, tristate val) +{ + struct symbol* sym; + int type; + tristate oldval; + + sym = item->menu ? item->menu->sym : 0; + if (!sym) + return; + + type = sym_get_type(sym); + switch (type) { + case S_BOOLEAN: + case S_TRISTATE: + oldval = sym_get_tristate_value(sym); + + if (!sym_set_tristate_value(sym, val)) + return; + if (oldval == no && item->menu->list) + item->setOpen(TRUE); + parent()->updateList(item); + break; + } +} + +void ConfigList::changeValue(ConfigItem* item) +{ + struct symbol* sym; + struct menu* menu; + int type, oldexpr, newexpr; + + menu = item->menu; + if (!menu) + return; + sym = menu->sym; + if (!sym) { + if (item->menu->list) + item->setOpen(!item->isOpen()); + return; + } + + type = sym_get_type(sym); + switch (type) { + case S_BOOLEAN: + case S_TRISTATE: + oldexpr = sym_get_tristate_value(sym); + newexpr = sym_toggle_tristate_value(sym); + if (item->menu->list) { + if (oldexpr == newexpr) + item->setOpen(!item->isOpen()); + else if (oldexpr == no) + item->setOpen(TRUE); + } + if (oldexpr != newexpr) + parent()->updateList(item); + break; + case S_INT: + case S_HEX: + case S_STRING: + if (colMap[dataColIdx] >= 0) + item->startRename(colMap[dataColIdx]); + else + parent()->lineEdit->show(item); + break; + } +} + +void ConfigList::setRootMenu(struct menu *menu) +{ + enum prop_type type; + + if (rootEntry == menu) + return; + type = menu && menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (type != P_MENU) + return; + updateMenuList(this, 0); + rootEntry = menu; + updateListAll(); + setSelected(currentItem(), hasFocus()); + ensureItemVisible(currentItem()); +} + +void ConfigList::setParentMenu(void) +{ + ConfigItem* item; + struct menu *oldroot; + + oldroot = rootEntry; + if (rootEntry == &rootmenu) + return; + setRootMenu(menu_get_parent_menu(rootEntry->parent)); + + Q3ListViewItemIterator it(this); + for (; (item = (ConfigItem*)it.current()); it++) { + if (item->menu == oldroot) { + setCurrentItem(item); + ensureItemVisible(item); + break; + } + } +} + +/* + * update all the children of a menu entry + * removes/adds the entries from the parent widget as necessary + * + * parent: either the menu list widget or a menu entry widget + * menu: entry to be updated + */ +template +void ConfigList::updateMenuList(P* parent, struct menu* menu) +{ + struct menu* child; + ConfigItem* item; + ConfigItem* last; + bool visible; + enum prop_type type; + + if (!menu) { + while ((item = parent->firstChild())) + delete item; + return; + } + + last = parent->firstChild(); + if (last && !last->goParent) + last = 0; + for (child = menu->list; child; child = child->next) { + item = last ? last->nextSibling() : parent->firstChild(); + type = child->prompt ? child->prompt->type : P_UNKNOWN; + + switch (mode) { + case menuMode: + if (!(child->flags & MENU_ROOT)) + goto hide; + break; + case symbolMode: + if (child->flags & MENU_ROOT) + goto hide; + break; + default: + break; + } + + visible = menu_is_visible(child); + if (!menuSkip(child)) { + if (!child->sym && !child->list && !child->prompt) + continue; + if (!item || item->menu != child) + item = new ConfigItem(parent, last, child, visible); + else + item->testUpdateMenu(visible); + + if (mode == fullMode || mode == menuMode || type != P_MENU) + updateMenuList(item, child); + else + updateMenuList(item, 0); + last = item; + continue; + } + hide: + if (item && item->menu == child) { + last = parent->firstChild(); + if (last == item) + last = 0; + else while (last->nextSibling() != item) + last = last->nextSibling(); + delete item; + } + } +} + +void ConfigList::keyPressEvent(QKeyEvent* ev) +{ + Q3ListViewItem* i = currentItem(); + ConfigItem* item; + struct menu *menu; + enum prop_type type; + + if (ev->key() == Qt::Key_Escape && mode != fullMode && mode != listMode) { + emit parentSelected(); + ev->accept(); + return; + } + + if (!i) { + Parent::keyPressEvent(ev); + return; + } + item = (ConfigItem*)i; + + switch (ev->key()) { + case Qt::Key_Return: + case Qt::Key_Enter: + if (item->goParent) { + emit parentSelected(); + break; + } + menu = item->menu; + if (!menu) + break; + type = menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (type == P_MENU && rootEntry != menu && + mode != fullMode && mode != menuMode) { + emit menuSelected(menu); + break; + } + case Qt::Key_Space: + changeValue(item); + break; + case Qt::Key_N: + setValue(item, no); + break; + case Qt::Key_M: + setValue(item, mod); + break; + case Qt::Key_Y: + setValue(item, yes); + break; + default: + Parent::keyPressEvent(ev); + return; + } + ev->accept(); +} + +void ConfigList::contentsMousePressEvent(QMouseEvent* e) +{ + //QPoint p(contentsToViewport(e->pos())); + //printf("contentsMousePressEvent: %d,%d\n", p.x(), p.y()); + Parent::contentsMousePressEvent(e); +} + +void ConfigList::contentsMouseReleaseEvent(QMouseEvent* e) +{ + QPoint p(contentsToViewport(e->pos())); + ConfigItem* item = (ConfigItem*)itemAt(p); + struct menu *menu; + enum prop_type ptype; + const QPixmap* pm; + int idx, x; + + if (!item) + goto skip; + + menu = item->menu; + x = header()->offset() + p.x(); + idx = colRevMap[header()->sectionAt(x)]; + switch (idx) { + case promptColIdx: + pm = item->pixmap(promptColIdx); + if (pm) { + int off = header()->sectionPos(0) + itemMargin() + + treeStepSize() * (item->depth() + (rootIsDecorated() ? 1 : 0)); + if (x >= off && x < off + pm->width()) { + if (item->goParent) { + emit parentSelected(); + break; + } else if (!menu) + break; + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (ptype == P_MENU && rootEntry != menu && + mode != fullMode && mode != menuMode) + emit menuSelected(menu); + else + changeValue(item); + } + } + break; + case noColIdx: + setValue(item, no); + break; + case modColIdx: + setValue(item, mod); + break; + case yesColIdx: + setValue(item, yes); + break; + case dataColIdx: + changeValue(item); + break; + } + +skip: + //printf("contentsMouseReleaseEvent: %d,%d\n", p.x(), p.y()); + Parent::contentsMouseReleaseEvent(e); +} + +void ConfigList::contentsMouseMoveEvent(QMouseEvent* e) +{ + //QPoint p(contentsToViewport(e->pos())); + //printf("contentsMouseMoveEvent: %d,%d\n", p.x(), p.y()); + Parent::contentsMouseMoveEvent(e); +} + +void ConfigList::contentsMouseDoubleClickEvent(QMouseEvent* e) +{ + QPoint p(contentsToViewport(e->pos())); + ConfigItem* item = (ConfigItem*)itemAt(p); + struct menu *menu; + enum prop_type ptype; + + if (!item) + goto skip; + if (item->goParent) { + emit parentSelected(); + goto skip; + } + menu = item->menu; + if (!menu) + goto skip; + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (ptype == P_MENU && (mode == singleMode || mode == symbolMode)) + emit menuSelected(menu); + else if (menu->sym) + changeValue(item); + +skip: + //printf("contentsMouseDoubleClickEvent: %d,%d\n", p.x(), p.y()); + Parent::contentsMouseDoubleClickEvent(e); +} + +void ConfigList::focusInEvent(QFocusEvent *e) +{ + struct menu *menu = NULL; + + Parent::focusInEvent(e); + + ConfigItem* item = (ConfigItem *)currentItem(); + if (item) { + setSelected(item, TRUE); + menu = item->menu; + } + emit gotFocus(menu); +} + +void ConfigList::contextMenuEvent(QContextMenuEvent *e) +{ + if (e->y() <= header()->geometry().bottom()) { + if (!headerPopup) { + Q3Action *action; + + headerPopup = new Q3PopupMenu(this); + action = new Q3Action(NULL, _("Show Name"), 0, this); + action->setToggleAction(TRUE); + connect(action, SIGNAL(toggled(bool)), + parent(), SLOT(setShowName(bool))); + connect(parent(), SIGNAL(showNameChanged(bool)), + action, SLOT(setOn(bool))); + action->setOn(showName); + action->addTo(headerPopup); + action = new Q3Action(NULL, _("Show Range"), 0, this); + action->setToggleAction(TRUE); + connect(action, SIGNAL(toggled(bool)), + parent(), SLOT(setShowRange(bool))); + connect(parent(), SIGNAL(showRangeChanged(bool)), + action, SLOT(setOn(bool))); + action->setOn(showRange); + action->addTo(headerPopup); + action = new Q3Action(NULL, _("Show Data"), 0, this); + action->setToggleAction(TRUE); + connect(action, SIGNAL(toggled(bool)), + parent(), SLOT(setShowData(bool))); + connect(parent(), SIGNAL(showDataChanged(bool)), + action, SLOT(setOn(bool))); + action->setOn(showData); + action->addTo(headerPopup); + } + headerPopup->exec(e->globalPos()); + e->accept(); + } else + e->ignore(); +} + +ConfigView*ConfigView::viewList; +QAction *ConfigView::showNormalAction; +QAction *ConfigView::showAllAction; +QAction *ConfigView::showPromptAction; + +ConfigView::ConfigView(QWidget* parent, const char *name) + : Parent(parent, name) +{ + list = new ConfigList(this, name); + lineEdit = new ConfigLineEdit(this); + lineEdit->hide(); + + this->nextView = viewList; + viewList = this; +} + +ConfigView::~ConfigView(void) +{ + ConfigView** vp; + + for (vp = &viewList; *vp; vp = &(*vp)->nextView) { + if (*vp == this) { + *vp = nextView; + break; + } + } +} + +void ConfigView::setOptionMode(QAction *act) +{ + if (act == showNormalAction) + list->optMode = normalOpt; + else if (act == showAllAction) + list->optMode = allOpt; + else + list->optMode = promptOpt; + + list->updateListAll(); +} + +void ConfigView::setShowName(bool b) +{ + if (list->showName != b) { + list->showName = b; + list->reinit(); + emit showNameChanged(b); + } +} + +void ConfigView::setShowRange(bool b) +{ + if (list->showRange != b) { + list->showRange = b; + list->reinit(); + emit showRangeChanged(b); + } +} + +void ConfigView::setShowData(bool b) +{ + if (list->showData != b) { + list->showData = b; + list->reinit(); + emit showDataChanged(b); + } +} + +void ConfigList::setAllOpen(bool open) +{ + Q3ListViewItemIterator it(this); + + for (; it.current(); it++) + it.current()->setOpen(open); +} + +void ConfigView::updateList(ConfigItem* item) +{ + ConfigView* v; + + for (v = viewList; v; v = v->nextView) + v->list->updateList(item); +} + +void ConfigView::updateListAll(void) +{ + ConfigView* v; + + for (v = viewList; v; v = v->nextView) + v->list->updateListAll(); +} + +ConfigInfoView::ConfigInfoView(QWidget* parent, const char *name) + : Parent(parent, name), sym(0), _menu(0) +{ + if (name) { + configSettings->beginGroup(name); + _showDebug = configSettings->readBoolEntry("/showDebug", false); + configSettings->endGroup(); + connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); + } +} + +void ConfigInfoView::saveSettings(void) +{ + if (name()) { + configSettings->beginGroup(name()); + configSettings->writeEntry("/showDebug", showDebug()); + configSettings->endGroup(); + } +} + +void ConfigInfoView::setShowDebug(bool b) +{ + if (_showDebug != b) { + _showDebug = b; + if (_menu) + menuInfo(); + else if (sym) + symbolInfo(); + emit showDebugChanged(b); + } +} + +void ConfigInfoView::setInfo(struct menu *m) +{ + if (_menu == m) + return; + _menu = m; + sym = NULL; + if (!_menu) + clear(); + else + menuInfo(); +} + +void ConfigInfoView::symbolInfo(void) +{ + QString str; + + str += "Symbol: "; + str += print_filter(sym->name); + str += "

value: "; + str += print_filter(sym_get_string_value(sym)); + str += "
visibility: "; + str += sym->visible == yes ? "y" : sym->visible == mod ? "m" : "n"; + str += "
"; + str += debug_info(sym); + + setText(str); +} + +void ConfigInfoView::menuInfo(void) +{ + struct symbol* sym; + QString head, debug, help; + + sym = _menu->sym; + if (sym) { + if (_menu->prompt) { + head += ""; + head += print_filter(_(_menu->prompt->text)); + head += ""; + if (sym->name) { + head += " ("; + if (showDebug()) + head += QString().sprintf("", sym); + head += print_filter(sym->name); + if (showDebug()) + head += ""; + head += ")"; + } + } else if (sym->name) { + head += ""; + if (showDebug()) + head += QString().sprintf("", sym); + head += print_filter(sym->name); + if (showDebug()) + head += ""; + head += ""; + } + head += "

"; + + if (showDebug()) + debug = debug_info(sym); + + struct gstr help_gstr = str_new(); + menu_get_ext_help(_menu, &help_gstr); + help = print_filter(str_get(&help_gstr)); + str_free(&help_gstr); + } else if (_menu->prompt) { + head += ""; + head += print_filter(_(_menu->prompt->text)); + head += "

"; + if (showDebug()) { + if (_menu->prompt->visible.expr) { + debug += "  dep: "; + expr_print(_menu->prompt->visible.expr, expr_print_help, &debug, E_NONE); + debug += "

"; + } + } + } + if (showDebug()) + debug += QString().sprintf("defined at %s:%d

", _menu->file->name, _menu->lineno); + + setText(head + debug + help); +} + +QString ConfigInfoView::debug_info(struct symbol *sym) +{ + QString debug; + + debug += "type: "; + debug += print_filter(sym_type_name(sym->type)); + if (sym_is_choice(sym)) + debug += " (choice)"; + debug += "
"; + if (sym->rev_dep.expr) { + debug += "reverse dep: "; + expr_print(sym->rev_dep.expr, expr_print_help, &debug, E_NONE); + debug += "
"; + } + for (struct property *prop = sym->prop; prop; prop = prop->next) { + switch (prop->type) { + case P_PROMPT: + case P_MENU: + debug += QString().sprintf("prompt: ", prop->menu); + debug += print_filter(_(prop->text)); + debug += "
"; + break; + case P_DEFAULT: + case P_SELECT: + case P_RANGE: + case P_ENV: + debug += prop_get_type_name(prop->type); + debug += ": "; + expr_print(prop->expr, expr_print_help, &debug, E_NONE); + debug += "
"; + break; + case P_CHOICE: + if (sym_is_choice(sym)) { + debug += "choice: "; + expr_print(prop->expr, expr_print_help, &debug, E_NONE); + debug += "
"; + } + break; + default: + debug += "unknown property: "; + debug += prop_get_type_name(prop->type); + debug += "
"; + } + if (prop->visible.expr) { + debug += "    dep: "; + expr_print(prop->visible.expr, expr_print_help, &debug, E_NONE); + debug += "
"; + } + } + debug += "
"; + + return debug; +} + +QString ConfigInfoView::print_filter(const QString &str) +{ + QRegExp re("[<>&\"\\n]"); + QString res = str; + for (int i = 0; (i = res.find(re, i)) >= 0;) { + switch (res[i].latin1()) { + case '<': + res.replace(i, 1, "<"); + i += 4; + break; + case '>': + res.replace(i, 1, ">"); + i += 4; + break; + case '&': + res.replace(i, 1, "&"); + i += 5; + break; + case '"': + res.replace(i, 1, """); + i += 6; + break; + case '\n': + res.replace(i, 1, "
"); + i += 4; + break; + } + } + return res; +} + +void ConfigInfoView::expr_print_help(void *data, struct symbol *sym, const char *str) +{ + QString* text = reinterpret_cast(data); + QString str2 = print_filter(str); + + if (sym && sym->name && !(sym->flags & SYMBOL_CONST)) { + *text += QString().sprintf("", sym); + *text += str2; + *text += ""; + } else + *text += str2; +} + +Q3PopupMenu* ConfigInfoView::createPopupMenu(const QPoint& pos) +{ + Q3PopupMenu* popup = Parent::createPopupMenu(pos); + Q3Action* action = new Q3Action(NULL, _("Show Debug Info"), 0, popup); + action->setToggleAction(TRUE); + connect(action, SIGNAL(toggled(bool)), SLOT(setShowDebug(bool))); + connect(this, SIGNAL(showDebugChanged(bool)), action, SLOT(setOn(bool))); + action->setOn(showDebug()); + popup->insertSeparator(); + action->addTo(popup); + return popup; +} + +void ConfigInfoView::contentsContextMenuEvent(QContextMenuEvent *e) +{ + Parent::contentsContextMenuEvent(e); +} + +ConfigSearchWindow::ConfigSearchWindow(ConfigMainWindow* parent, const char *name) + : Parent(parent, name), result(NULL) +{ + setCaption("Search Config"); + + QVBoxLayout* layout1 = new QVBoxLayout(this, 11, 6); + QHBoxLayout* layout2 = new QHBoxLayout(0, 0, 6); + layout2->addWidget(new QLabel(_("Find:"), this)); + editField = new QLineEdit(this); + connect(editField, SIGNAL(returnPressed()), SLOT(search())); + layout2->addWidget(editField); + searchButton = new QPushButton(_("Search"), this); + searchButton->setAutoDefault(FALSE); + connect(searchButton, SIGNAL(clicked()), SLOT(search())); + layout2->addWidget(searchButton); + layout1->addLayout(layout2); + + split = new QSplitter(this); + split->setOrientation(Qt::Vertical); + list = new ConfigView(split, name); + list->list->mode = listMode; + info = new ConfigInfoView(split, name); + connect(list->list, SIGNAL(menuChanged(struct menu *)), + info, SLOT(setInfo(struct menu *))); + connect(list->list, SIGNAL(menuChanged(struct menu *)), + parent, SLOT(setMenuLink(struct menu *))); + + layout1->addWidget(split); + + if (name) { + int x, y, width, height; + bool ok; + + configSettings->beginGroup(name); + width = configSettings->readNumEntry("/window width", parent->width() / 2); + height = configSettings->readNumEntry("/window height", parent->height() / 2); + resize(width, height); + x = configSettings->readNumEntry("/window x", 0, &ok); + if (ok) + y = configSettings->readNumEntry("/window y", 0, &ok); + if (ok) + move(x, y); + Q3ValueList sizes = configSettings->readSizes("/split", &ok); + if (ok) + split->setSizes(sizes); + configSettings->endGroup(); + connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); + } +} + +void ConfigSearchWindow::saveSettings(void) +{ + if (name()) { + configSettings->beginGroup(name()); + configSettings->writeEntry("/window x", pos().x()); + configSettings->writeEntry("/window y", pos().y()); + configSettings->writeEntry("/window width", size().width()); + configSettings->writeEntry("/window height", size().height()); + configSettings->writeSizes("/split", split->sizes()); + configSettings->endGroup(); + } +} + +void ConfigSearchWindow::search(void) +{ + struct symbol **p; + struct property *prop; + ConfigItem *lastItem = NULL; + + free(result); + list->list->clear(); + info->clear(); + + result = sym_re_search(editField->text().latin1()); + if (!result) + return; + for (p = result; *p; p++) { + for_all_prompts((*p), prop) + lastItem = new ConfigItem(list->list, lastItem, prop->menu, + menu_is_visible(prop->menu)); + } +} + +/* + * Construct the complete config widget + */ +ConfigMainWindow::ConfigMainWindow(void) + : searchWindow(0) +{ + QMenuBar* menu; + bool ok; + int x, y, width, height; + char title[256]; + + QDesktopWidget *d = configApp->desktop(); + snprintf(title, sizeof(title), "%s%s", + rootmenu.prompt->text, +#if QT_VERSION < 0x040000 + " (Qt3)" +#else + "" +#endif + ); + setCaption(title); + + width = configSettings->readNumEntry("/window width", d->width() - 64); + height = configSettings->readNumEntry("/window height", d->height() - 64); + resize(width, height); + x = configSettings->readNumEntry("/window x", 0, &ok); + if (ok) + y = configSettings->readNumEntry("/window y", 0, &ok); + if (ok) + move(x, y); + + split1 = new QSplitter(this); + split1->setOrientation(Qt::Horizontal); + setCentralWidget(split1); + + menuView = new ConfigView(split1, "menu"); + menuList = menuView->list; + + split2 = new QSplitter(split1); + split2->setOrientation(Qt::Vertical); + + // create config tree + configView = new ConfigView(split2, "config"); + configList = configView->list; + + helpText = new ConfigInfoView(split2, "help"); + helpText->setTextFormat(Qt::RichText); + + setTabOrder(configList, helpText); + configList->setFocus(); + + menu = menuBar(); + toolBar = new Q3ToolBar("Tools", this); + + backAction = new Q3Action("Back", QPixmap(xpm_back), _("Back"), 0, this); + connect(backAction, SIGNAL(activated()), SLOT(goBack())); + backAction->setEnabled(FALSE); + Q3Action *quitAction = new Q3Action("Quit", _("&Quit"), Qt::CTRL + Qt::Key_Q, this); + connect(quitAction, SIGNAL(activated()), SLOT(close())); + Q3Action *loadAction = new Q3Action("Load", QPixmap(xpm_load), _("&Load"), Qt::CTRL + Qt::Key_L, this); + connect(loadAction, SIGNAL(activated()), SLOT(loadConfig())); + saveAction = new Q3Action("Save", QPixmap(xpm_save), _("&Save"), Qt::CTRL + Qt::Key_S, this); + connect(saveAction, SIGNAL(activated()), SLOT(saveConfig())); + conf_set_changed_callback(conf_changed); + // Set saveAction's initial state + conf_changed(); + Q3Action *saveAsAction = new Q3Action("Save As...", _("Save &As..."), 0, this); + connect(saveAsAction, SIGNAL(activated()), SLOT(saveConfigAs())); + Q3Action *searchAction = new Q3Action("Find", _("&Find"), Qt::CTRL + Qt::Key_F, this); + connect(searchAction, SIGNAL(activated()), SLOT(searchConfig())); + Q3Action *singleViewAction = new Q3Action("Single View", QPixmap(xpm_single_view), _("Single View"), 0, this); + connect(singleViewAction, SIGNAL(activated()), SLOT(showSingleView())); + Q3Action *splitViewAction = new Q3Action("Split View", QPixmap(xpm_split_view), _("Split View"), 0, this); + connect(splitViewAction, SIGNAL(activated()), SLOT(showSplitView())); + Q3Action *fullViewAction = new Q3Action("Full View", QPixmap(xpm_tree_view), _("Full View"), 0, this); + connect(fullViewAction, SIGNAL(activated()), SLOT(showFullView())); + + Q3Action *showNameAction = new Q3Action(NULL, _("Show Name"), 0, this); + showNameAction->setToggleAction(TRUE); + connect(showNameAction, SIGNAL(toggled(bool)), configView, SLOT(setShowName(bool))); + connect(configView, SIGNAL(showNameChanged(bool)), showNameAction, SLOT(setOn(bool))); + showNameAction->setOn(configView->showName()); + Q3Action *showRangeAction = new Q3Action(NULL, _("Show Range"), 0, this); + showRangeAction->setToggleAction(TRUE); + connect(showRangeAction, SIGNAL(toggled(bool)), configView, SLOT(setShowRange(bool))); + connect(configView, SIGNAL(showRangeChanged(bool)), showRangeAction, SLOT(setOn(bool))); + showRangeAction->setOn(configList->showRange); + Q3Action *showDataAction = new Q3Action(NULL, _("Show Data"), 0, this); + showDataAction->setToggleAction(TRUE); + connect(showDataAction, SIGNAL(toggled(bool)), configView, SLOT(setShowData(bool))); + connect(configView, SIGNAL(showDataChanged(bool)), showDataAction, SLOT(setOn(bool))); + showDataAction->setOn(configList->showData); + + QActionGroup *optGroup = new QActionGroup(this); + optGroup->setExclusive(TRUE); + connect(optGroup, SIGNAL(selected(QAction *)), configView, + SLOT(setOptionMode(QAction *))); + connect(optGroup, SIGNAL(selected(QAction *)), menuView, + SLOT(setOptionMode(QAction *))); + +#if QT_VERSION >= 0x040000 + configView->showNormalAction = new QAction(_("Show Normal Options"), optGroup); + configView->showAllAction = new QAction(_("Show All Options"), optGroup); + configView->showPromptAction = new QAction(_("Show Prompt Options"), optGroup); +#else + configView->showNormalAction = new QAction(_("Show Normal Options"), 0, optGroup); + configView->showAllAction = new QAction(_("Show All Options"), 0, optGroup); + configView->showPromptAction = new QAction(_("Show Prompt Options"), 0, optGroup); +#endif + configView->showNormalAction->setToggleAction(TRUE); + configView->showNormalAction->setOn(configList->optMode == normalOpt); + configView->showAllAction->setToggleAction(TRUE); + configView->showAllAction->setOn(configList->optMode == allOpt); + configView->showPromptAction->setToggleAction(TRUE); + configView->showPromptAction->setOn(configList->optMode == promptOpt); + + Q3Action *showDebugAction = new Q3Action(NULL, _("Show Debug Info"), 0, this); + showDebugAction->setToggleAction(TRUE); + connect(showDebugAction, SIGNAL(toggled(bool)), helpText, SLOT(setShowDebug(bool))); + connect(helpText, SIGNAL(showDebugChanged(bool)), showDebugAction, SLOT(setOn(bool))); + showDebugAction->setOn(helpText->showDebug()); + + Q3Action *showIntroAction = new Q3Action(NULL, _("Introduction"), 0, this); + connect(showIntroAction, SIGNAL(activated()), SLOT(showIntro())); + Q3Action *showAboutAction = new Q3Action(NULL, _("About"), 0, this); + connect(showAboutAction, SIGNAL(activated()), SLOT(showAbout())); + + // init tool bar + backAction->addTo(toolBar); + toolBar->addSeparator(); + loadAction->addTo(toolBar); + saveAction->addTo(toolBar); + toolBar->addSeparator(); + singleViewAction->addTo(toolBar); + splitViewAction->addTo(toolBar); + fullViewAction->addTo(toolBar); + + // create config menu + Q3PopupMenu* config = new Q3PopupMenu(this); + menu->insertItem(_("&File"), config); + loadAction->addTo(config); + saveAction->addTo(config); + saveAsAction->addTo(config); + config->insertSeparator(); + quitAction->addTo(config); + + // create edit menu + Q3PopupMenu* editMenu = new Q3PopupMenu(this); + menu->insertItem(_("&Edit"), editMenu); + searchAction->addTo(editMenu); + + // create options menu + Q3PopupMenu* optionMenu = new Q3PopupMenu(this); + menu->insertItem(_("&Option"), optionMenu); + showNameAction->addTo(optionMenu); + showRangeAction->addTo(optionMenu); + showDataAction->addTo(optionMenu); + optionMenu->insertSeparator(); + optGroup->addTo(optionMenu); + optionMenu->insertSeparator(); + + // create help menu + Q3PopupMenu* helpMenu = new Q3PopupMenu(this); + menu->insertSeparator(); + menu->insertItem(_("&Help"), helpMenu); + showIntroAction->addTo(helpMenu); + showAboutAction->addTo(helpMenu); + + connect(configList, SIGNAL(menuChanged(struct menu *)), + helpText, SLOT(setInfo(struct menu *))); + connect(configList, SIGNAL(menuSelected(struct menu *)), + SLOT(changeMenu(struct menu *))); + connect(configList, SIGNAL(parentSelected()), + SLOT(goBack())); + connect(menuList, SIGNAL(menuChanged(struct menu *)), + helpText, SLOT(setInfo(struct menu *))); + connect(menuList, SIGNAL(menuSelected(struct menu *)), + SLOT(changeMenu(struct menu *))); + + connect(configList, SIGNAL(gotFocus(struct menu *)), + helpText, SLOT(setInfo(struct menu *))); + connect(menuList, SIGNAL(gotFocus(struct menu *)), + helpText, SLOT(setInfo(struct menu *))); + connect(menuList, SIGNAL(gotFocus(struct menu *)), + SLOT(listFocusChanged(void))); + connect(helpText, SIGNAL(menuSelected(struct menu *)), + SLOT(setMenuLink(struct menu *))); + + QString listMode = configSettings->readEntry("/listMode", "symbol"); + if (listMode == "single") + showSingleView(); + else if (listMode == "full") + showFullView(); + else /*if (listMode == "split")*/ + showSplitView(); + + // UI setup done, restore splitter positions + Q3ValueList sizes = configSettings->readSizes("/split1", &ok); + if (ok) + split1->setSizes(sizes); + + sizes = configSettings->readSizes("/split2", &ok); + if (ok) + split2->setSizes(sizes); +} + +void ConfigMainWindow::loadConfig(void) +{ + QString s = Q3FileDialog::getOpenFileName(conf_get_configname(), NULL, this); + if (s.isNull()) + return; + if (conf_read(QFile::encodeName(s))) + QMessageBox::information(this, "qconf", _("Unable to load configuration!")); + ConfigView::updateListAll(); +} + +bool ConfigMainWindow::saveConfig(void) +{ + if (conf_write(NULL)) { + QMessageBox::information(this, "qconf", _("Unable to save configuration!")); + return false; + } + return true; +} + +void ConfigMainWindow::saveConfigAs(void) +{ + QString s = Q3FileDialog::getSaveFileName(conf_get_configname(), NULL, this); + if (s.isNull()) + return; + saveConfig(); +} + +void ConfigMainWindow::searchConfig(void) +{ + if (!searchWindow) + searchWindow = new ConfigSearchWindow(this, "search"); + searchWindow->show(); +} + +void ConfigMainWindow::changeMenu(struct menu *menu) +{ + configList->setRootMenu(menu); + if (configList->rootEntry->parent == &rootmenu) + backAction->setEnabled(FALSE); + else + backAction->setEnabled(TRUE); +} + +void ConfigMainWindow::setMenuLink(struct menu *menu) +{ + struct menu *parent; + ConfigList* list = NULL; + ConfigItem* item; + + if (configList->menuSkip(menu)) + return; + + switch (configList->mode) { + case singleMode: + list = configList; + parent = menu_get_parent_menu(menu); + if (!parent) + return; + list->setRootMenu(parent); + break; + case symbolMode: + if (menu->flags & MENU_ROOT) { + configList->setRootMenu(menu); + configList->clearSelection(); + list = menuList; + } else { + list = configList; + parent = menu_get_parent_menu(menu->parent); + if (!parent) + return; + item = menuList->findConfigItem(parent); + if (item) { + menuList->setSelected(item, TRUE); + menuList->ensureItemVisible(item); + } + list->setRootMenu(parent); + } + break; + case fullMode: + list = configList; + break; + default: + break; + } + + if (list) { + item = list->findConfigItem(menu); + if (item) { + list->setSelected(item, TRUE); + list->ensureItemVisible(item); + list->setFocus(); + } + } +} + +void ConfigMainWindow::listFocusChanged(void) +{ + if (menuList->mode == menuMode) + configList->clearSelection(); +} + +void ConfigMainWindow::goBack(void) +{ + ConfigItem* item; + + configList->setParentMenu(); + if (configList->rootEntry == &rootmenu) + backAction->setEnabled(FALSE); + item = (ConfigItem*)menuList->selectedItem(); + while (item) { + if (item->menu == configList->rootEntry) { + menuList->setSelected(item, TRUE); + break; + } + item = (ConfigItem*)item->parent(); + } +} + +void ConfigMainWindow::showSingleView(void) +{ + menuView->hide(); + menuList->setRootMenu(0); + configList->mode = singleMode; + if (configList->rootEntry == &rootmenu) + configList->updateListAll(); + else + configList->setRootMenu(&rootmenu); + configList->setAllOpen(TRUE); + configList->setFocus(); +} + +void ConfigMainWindow::showSplitView(void) +{ + configList->mode = symbolMode; + if (configList->rootEntry == &rootmenu) + configList->updateListAll(); + else + configList->setRootMenu(&rootmenu); + configList->setAllOpen(TRUE); + configApp->processEvents(); + menuList->mode = menuMode; + menuList->setRootMenu(&rootmenu); + menuList->setAllOpen(TRUE); + menuView->show(); + menuList->setFocus(); +} + +void ConfigMainWindow::showFullView(void) +{ + menuView->hide(); + menuList->setRootMenu(0); + configList->mode = fullMode; + if (configList->rootEntry == &rootmenu) + configList->updateListAll(); + else + configList->setRootMenu(&rootmenu); + configList->setAllOpen(FALSE); + configList->setFocus(); +} + +/* + * ask for saving configuration before quitting + * TODO ask only when something changed + */ +void ConfigMainWindow::closeEvent(QCloseEvent* e) +{ + if (!conf_get_changed()) { + e->accept(); + return; + } + QMessageBox mb("qconf", _("Save configuration?"), QMessageBox::Warning, + QMessageBox::Yes | QMessageBox::Default, QMessageBox::No, QMessageBox::Cancel | QMessageBox::Escape); + mb.setButtonText(QMessageBox::Yes, _("&Save Changes")); + mb.setButtonText(QMessageBox::No, _("&Discard Changes")); + mb.setButtonText(QMessageBox::Cancel, _("Cancel Exit")); + switch (mb.exec()) { + case QMessageBox::Yes: + if (saveConfig()) + e->accept(); + else + e->ignore(); + break; + case QMessageBox::No: + e->accept(); + break; + case QMessageBox::Cancel: + e->ignore(); + break; + } +} + +void ConfigMainWindow::showIntro(void) +{ + static const QString str = _("Welcome to the qconf graphical configuration tool.\n\n" + "For each option, a blank box indicates the feature is disabled, a check\n" + "indicates it is enabled, and a dot indicates that it is to be compiled\n" + "as a module. Clicking on the box will cycle through the three states.\n\n" + "If you do not see an option (e.g., a device driver) that you believe\n" + "should be present, try turning on Show All Options under the Options menu.\n" + "Although there is no cross reference yet to help you figure out what other\n" + "options must be enabled to support the option you are interested in, you can\n" + "still view the help of a grayed-out option.\n\n" + "Toggling Show Debug Info under the Options menu will show the dependencies,\n" + "which you can then match by examining other options.\n\n"); + + QMessageBox::information(this, "qconf", str); +} + +void ConfigMainWindow::showAbout(void) +{ + static const QString str = _("qconf is Copyright (C) 2002 Roman Zippel .\n\n" + "Bug reports and feature request can also be entered at http://bugzilla.kernel.org/\n"); + + QMessageBox::information(this, "qconf", str); +} + +void ConfigMainWindow::saveSettings(void) +{ + configSettings->writeEntry("/window x", pos().x()); + configSettings->writeEntry("/window y", pos().y()); + configSettings->writeEntry("/window width", size().width()); + configSettings->writeEntry("/window height", size().height()); + + QString entry; + switch(configList->mode) { + case singleMode : + entry = "single"; + break; + + case symbolMode : + entry = "split"; + break; + + case fullMode : + entry = "full"; + break; + + default: + break; + } + configSettings->writeEntry("/listMode", entry); + + configSettings->writeSizes("/split1", split1->sizes()); + configSettings->writeSizes("/split2", split2->sizes()); +} + +void ConfigMainWindow::conf_changed(void) +{ + if (saveAction) + saveAction->setEnabled(conf_get_changed()); +} + +void fixup_rootmenu(struct menu *menu) +{ + struct menu *child; + static int menu_cnt = 0; + + menu->flags |= MENU_ROOT; + for (child = menu->list; child; child = child->next) { + if (child->prompt && child->prompt->type == P_MENU) { + menu_cnt++; + fixup_rootmenu(child); + menu_cnt--; + } else if (!menu_cnt) + fixup_rootmenu(child); + } +} + +static const char *progname; + +static void usage(void) +{ + printf(_("%s \n"), progname); + exit(0); +} + +int main(int ac, char** av) +{ + ConfigMainWindow* v; + const char *name; + + bindtextdomain(PACKAGE, LOCALEDIR); + textdomain(PACKAGE); + + progname = av[0]; + configApp = new QApplication(ac, av); + if (ac > 1 && av[1][0] == '-') { + switch (av[1][1]) { + case 'h': + case '?': + usage(); + } + name = av[2]; + } else + name = av[1]; + if (!name) + usage(); + + conf_parse(name); + fixup_rootmenu(&rootmenu); + conf_read(NULL); + //zconfdump(stdout); + + configSettings = new ConfigSettings(); + configSettings->beginGroup("/kconfig/qconf"); + v = new ConfigMainWindow(); + + //zconfdump(stdout); + configApp->setMainWidget(v); + configApp->connect(configApp, SIGNAL(lastWindowClosed()), SLOT(quit())); + configApp->connect(configApp, SIGNAL(aboutToQuit()), v, SLOT(saveSettings())); + v->show(); + configApp->exec(); + + configSettings->endGroup(); + delete configSettings; + + return 0; +} diff --git a/scripts/kconfig/qconf.h b/scripts/kconfig/qconf.h new file mode 100644 index 0000000000..bde0c6b6f9 --- /dev/null +++ b/scripts/kconfig/qconf.h @@ -0,0 +1,338 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#if QT_VERSION < 0x040000 +#include +#else +#include +#endif +#include + +#if QT_VERSION < 0x040000 +#define Q3ValueList QValueList +#define Q3PopupMenu QPopupMenu +#define Q3ListView QListView +#define Q3ListViewItem QListViewItem +#define Q3VBox QVBox +#define Q3TextBrowser QTextBrowser +#define Q3MainWindow QMainWindow +#define Q3Action QAction +#define Q3ToolBar QToolBar +#define Q3ListViewItemIterator QListViewItemIterator +#define Q3FileDialog QFileDialog +#endif + +class ConfigView; +class ConfigList; +class ConfigItem; +class ConfigLineEdit; +class ConfigMainWindow; + +class ConfigSettings : public QSettings { +public: + ConfigSettings(); + Q3ValueList readSizes(const QString& key, bool *ok); + bool writeSizes(const QString& key, const Q3ValueList& value); +}; + +enum colIdx { + promptColIdx, nameColIdx, noColIdx, modColIdx, yesColIdx, dataColIdx, colNr +}; +enum listMode { + singleMode, menuMode, symbolMode, fullMode, listMode +}; +enum optionMode { + normalOpt = 0, allOpt, promptOpt +}; + +class ConfigList : public Q3ListView { + Q_OBJECT + typedef class Q3ListView Parent; +public: + ConfigList(ConfigView* p, const char *name = 0); + void reinit(void); + ConfigView* parent(void) const + { + return (ConfigView*)Parent::parent(); + } + ConfigItem* findConfigItem(struct menu *); + +protected: + void keyPressEvent(QKeyEvent *e); + void contentsMousePressEvent(QMouseEvent *e); + void contentsMouseReleaseEvent(QMouseEvent *e); + void contentsMouseMoveEvent(QMouseEvent *e); + void contentsMouseDoubleClickEvent(QMouseEvent *e); + void focusInEvent(QFocusEvent *e); + void contextMenuEvent(QContextMenuEvent *e); + +public slots: + void setRootMenu(struct menu *menu); + + void updateList(ConfigItem *item); + void setValue(ConfigItem* item, tristate val); + void changeValue(ConfigItem* item); + void updateSelection(void); + void saveSettings(void); +signals: + void menuChanged(struct menu *menu); + void menuSelected(struct menu *menu); + void parentSelected(void); + void gotFocus(struct menu *); + +public: + void updateListAll(void) + { + updateAll = true; + updateList(NULL); + updateAll = false; + } + ConfigList* listView() + { + return this; + } + ConfigItem* firstChild() const + { + return (ConfigItem *)Parent::firstChild(); + } + int mapIdx(colIdx idx) + { + return colMap[idx]; + } + void addColumn(colIdx idx, const QString& label) + { + colMap[idx] = Parent::addColumn(label); + colRevMap[colMap[idx]] = idx; + } + void removeColumn(colIdx idx) + { + int col = colMap[idx]; + if (col >= 0) { + Parent::removeColumn(col); + colRevMap[col] = colMap[idx] = -1; + } + } + void setAllOpen(bool open); + void setParentMenu(void); + + bool menuSkip(struct menu *); + + template + void updateMenuList(P*, struct menu*); + + bool updateAll; + + QPixmap symbolYesPix, symbolModPix, symbolNoPix; + QPixmap choiceYesPix, choiceNoPix; + QPixmap menuPix, menuInvPix, menuBackPix, voidPix; + + bool showName, showRange, showData; + enum listMode mode; + enum optionMode optMode; + struct menu *rootEntry; + QColorGroup disabledColorGroup; + QColorGroup inactivedColorGroup; + Q3PopupMenu* headerPopup; + +private: + int colMap[colNr]; + int colRevMap[colNr]; +}; + +class ConfigItem : public Q3ListViewItem { + typedef class Q3ListViewItem Parent; +public: + ConfigItem(Q3ListView *parent, ConfigItem *after, struct menu *m, bool v) + : Parent(parent, after), menu(m), visible(v), goParent(false) + { + init(); + } + ConfigItem(ConfigItem *parent, ConfigItem *after, struct menu *m, bool v) + : Parent(parent, after), menu(m), visible(v), goParent(false) + { + init(); + } + ConfigItem(Q3ListView *parent, ConfigItem *after, bool v) + : Parent(parent, after), menu(0), visible(v), goParent(true) + { + init(); + } + ~ConfigItem(void); + void init(void); + void okRename(int col); + void updateMenu(void); + void testUpdateMenu(bool v); + ConfigList* listView() const + { + return (ConfigList*)Parent::listView(); + } + ConfigItem* firstChild() const + { + return (ConfigItem *)Parent::firstChild(); + } + ConfigItem* nextSibling() const + { + return (ConfigItem *)Parent::nextSibling(); + } + void setText(colIdx idx, const QString& text) + { + Parent::setText(listView()->mapIdx(idx), text); + } + QString text(colIdx idx) const + { + return Parent::text(listView()->mapIdx(idx)); + } + void setPixmap(colIdx idx, const QPixmap& pm) + { + Parent::setPixmap(listView()->mapIdx(idx), pm); + } + const QPixmap* pixmap(colIdx idx) const + { + return Parent::pixmap(listView()->mapIdx(idx)); + } + void paintCell(QPainter* p, const QColorGroup& cg, int column, int width, int align); + + ConfigItem* nextItem; + struct menu *menu; + bool visible; + bool goParent; +}; + +class ConfigLineEdit : public QLineEdit { + Q_OBJECT + typedef class QLineEdit Parent; +public: + ConfigLineEdit(ConfigView* parent); + ConfigView* parent(void) const + { + return (ConfigView*)Parent::parent(); + } + void show(ConfigItem *i); + void keyPressEvent(QKeyEvent *e); + +public: + ConfigItem *item; +}; + +class ConfigView : public Q3VBox { + Q_OBJECT + typedef class Q3VBox Parent; +public: + ConfigView(QWidget* parent, const char *name = 0); + ~ConfigView(void); + static void updateList(ConfigItem* item); + static void updateListAll(void); + + bool showName(void) const { return list->showName; } + bool showRange(void) const { return list->showRange; } + bool showData(void) const { return list->showData; } +public slots: + void setShowName(bool); + void setShowRange(bool); + void setShowData(bool); + void setOptionMode(QAction *); +signals: + void showNameChanged(bool); + void showRangeChanged(bool); + void showDataChanged(bool); +public: + ConfigList* list; + ConfigLineEdit* lineEdit; + + static ConfigView* viewList; + ConfigView* nextView; + + static QAction *showNormalAction; + static QAction *showAllAction; + static QAction *showPromptAction; +}; + +class ConfigInfoView : public Q3TextBrowser { + Q_OBJECT + typedef class Q3TextBrowser Parent; +public: + ConfigInfoView(QWidget* parent, const char *name = 0); + bool showDebug(void) const { return _showDebug; } + +public slots: + void setInfo(struct menu *menu); + void saveSettings(void); + void setShowDebug(bool); + +signals: + void showDebugChanged(bool); + void menuSelected(struct menu *); + +protected: + void symbolInfo(void); + void menuInfo(void); + QString debug_info(struct symbol *sym); + static QString print_filter(const QString &str); + static void expr_print_help(void *data, struct symbol *sym, const char *str); + Q3PopupMenu* createPopupMenu(const QPoint& pos); + void contentsContextMenuEvent(QContextMenuEvent *e); + + struct symbol *sym; + struct menu *_menu; + bool _showDebug; +}; + +class ConfigSearchWindow : public QDialog { + Q_OBJECT + typedef class QDialog Parent; +public: + ConfigSearchWindow(ConfigMainWindow* parent, const char *name = 0); + +public slots: + void saveSettings(void); + void search(void); + +protected: + QLineEdit* editField; + QPushButton* searchButton; + QSplitter* split; + ConfigView* list; + ConfigInfoView* info; + + struct symbol **result; +}; + +class ConfigMainWindow : public Q3MainWindow { + Q_OBJECT + + static Q3Action *saveAction; + static void conf_changed(void); +public: + ConfigMainWindow(void); +public slots: + void changeMenu(struct menu *); + void setMenuLink(struct menu *); + void listFocusChanged(void); + void goBack(void); + void loadConfig(void); + bool saveConfig(void); + void saveConfigAs(void); + void searchConfig(void); + void showSingleView(void); + void showSplitView(void); + void showFullView(void); + void showIntro(void); + void showAbout(void); + void saveSettings(void); + +protected: + void closeEvent(QCloseEvent *e); + + ConfigSearchWindow *searchWindow; + ConfigView *menuView; + ConfigList *menuList; + ConfigView *configView; + ConfigList *configList; + ConfigInfoView *helpText; + Q3ToolBar *toolBar; + Q3Action *backAction; + QSplitter* split1; + QSplitter* split2; +}; diff --git a/scripts/kconfig/streamline_config.pl b/scripts/kconfig/streamline_config.pl new file mode 100755 index 0000000000..9cb8522d8d --- /dev/null +++ b/scripts/kconfig/streamline_config.pl @@ -0,0 +1,647 @@ +#!/usr/bin/perl -w +# +# Copyright 2005-2009 - Steven Rostedt +# Licensed under the terms of the GNU GPL License version 2 +# +# It's simple enough to figure out how this works. +# If not, then you can ask me at stripconfig@goodmis.org +# +# What it does? +# +# If you have installed a Linux kernel from a distribution +# that turns on way too many modules than you need, and +# you only want the modules you use, then this program +# is perfect for you. +# +# It gives you the ability to turn off all the modules that are +# not loaded on your system. +# +# Howto: +# +# 1. Boot up the kernel that you want to stream line the config on. +# 2. Change directory to the directory holding the source of the +# kernel that you just booted. +# 3. Copy the configuraton file to this directory as .config +# 4. Have all your devices that you need modules for connected and +# operational (make sure that their corresponding modules are loaded) +# 5. Run this script redirecting the output to some other file +# like config_strip. +# 6. Back up your old config (if you want too). +# 7. copy the config_strip file to .config +# 8. Run "make oldconfig" +# +# Now your kernel is ready to be built with only the modules that +# are loaded. +# +# Here's what I did with my Debian distribution. +# +# cd /usr/src/linux-2.6.10 +# cp /boot/config-2.6.10-1-686-smp .config +# ~/bin/streamline_config > config_strip +# mv .config config_sav +# mv config_strip .config +# make oldconfig +# +use strict; +use Getopt::Long; + +# set the environment variable LOCALMODCONFIG_DEBUG to get +# debug output. +my $debugprint = 0; +$debugprint = 1 if (defined($ENV{LOCALMODCONFIG_DEBUG})); + +sub dprint { + return if (!$debugprint); + print STDERR @_; +} + +my $config = ".config"; + +my $uname = `uname -r`; +chomp $uname; + +my @searchconfigs = ( + { + "file" => ".config", + "exec" => "cat", + }, + { + "file" => "/proc/config.gz", + "exec" => "zcat", + }, + { + "file" => "/boot/config-$uname", + "exec" => "cat", + }, + { + "file" => "/boot/vmlinuz-$uname", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, + { + "file" => "vmlinux", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, + { + "file" => "/lib/modules/$uname/kernel/kernel/configs.ko", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, + { + "file" => "kernel/configs.ko", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, + { + "file" => "kernel/configs.o", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, +); + +sub read_config { + foreach my $conf (@searchconfigs) { + my $file = $conf->{"file"}; + + next if ( ! -f "$file"); + + if (defined($conf->{"test"})) { + `$conf->{"test"} $conf->{"file"} 2>/dev/null`; + next if ($?); + } + + my $exec = $conf->{"exec"}; + + print STDERR "using config: '$file'\n"; + + open(my $infile, '-|', "$exec $file") || die "Failed to run $exec $file"; + my @x = <$infile>; + close $infile; + return @x; + } + die "No config file found"; +} + +my @config_file = read_config; + +# Parse options +my $localmodconfig = 0; +my $localyesconfig = 0; + +GetOptions("localmodconfig" => \$localmodconfig, + "localyesconfig" => \$localyesconfig); + +# Get the build source and top level Kconfig file (passed in) +my $ksource = ($ARGV[0] ? $ARGV[0] : '.'); +my $kconfig = $ARGV[1]; +my $lsmod_file = $ENV{'LSMOD'}; + +my @makefiles = `find $ksource -name Makefile 2>/dev/null`; +chomp @makefiles; + +my %depends; +my %selects; +my %prompts; +my %objects; +my $var; +my $iflevel = 0; +my @ifdeps; + +# prevent recursion +my %read_kconfigs; + +sub read_kconfig { + my ($kconfig) = @_; + + my $state = "NONE"; + my $config; + + my $cont = 0; + my $line; + + my $source = "$ksource/$kconfig"; + my $last_source = ""; + + # Check for any environment variables used + while ($source =~ /\$(\w+)/ && $last_source ne $source) { + my $env = $1; + $last_source = $source; + $source =~ s/\$$env/$ENV{$env}/; + } + + open(my $kinfile, '<', $source) || die "Can't open $kconfig"; + while (<$kinfile>) { + chomp; + + # Make sure that lines ending with \ continue + if ($cont) { + $_ = $line . " " . $_; + } + + if (s/\\$//) { + $cont = 1; + $line = $_; + next; + } + + $cont = 0; + + # collect any Kconfig sources + if (/^source\s*"(.*)"/) { + my $kconfig = $1; + # prevent reading twice. + if (!defined($read_kconfigs{$kconfig})) { + $read_kconfigs{$kconfig} = 1; + read_kconfig($kconfig); + } + next; + } + + # configs found + if (/^\s*(menu)?config\s+(\S+)\s*$/) { + $state = "NEW"; + $config = $2; + + # Add depends for 'if' nesting + for (my $i = 0; $i < $iflevel; $i++) { + if ($i) { + $depends{$config} .= " " . $ifdeps[$i]; + } else { + $depends{$config} = $ifdeps[$i]; + } + $state = "DEP"; + } + + # collect the depends for the config + } elsif ($state eq "NEW" && /^\s*depends\s+on\s+(.*)$/) { + $state = "DEP"; + $depends{$config} = $1; + } elsif ($state eq "DEP" && /^\s*depends\s+on\s+(.*)$/) { + $depends{$config} .= " " . $1; + } elsif ($state eq "DEP" && /^\s*def(_(bool|tristate)|ault)\s+(\S.*)$/) { + my $dep = $3; + if ($dep !~ /^\s*(y|m|n)\s*$/) { + $dep =~ s/.*\sif\s+//; + $depends{$config} .= " " . $dep; + dprint "Added default depends $dep to $config\n"; + } + + # Get the configs that select this config + } elsif ($state ne "NONE" && /^\s*select\s+(\S+)/) { + my $conf = $1; + if (defined($selects{$conf})) { + $selects{$conf} .= " " . $config; + } else { + $selects{$conf} = $config; + } + + # configs without prompts must be selected + } elsif ($state ne "NONE" && /^\s*tristate\s\S/) { + # note if the config has a prompt + $prompts{$config} = 1; + + # Check for if statements + } elsif (/^if\s+(.*\S)\s*$/) { + my $deps = $1; + # remove beginning and ending non text + $deps =~ s/^[^a-zA-Z0-9_]*//; + $deps =~ s/[^a-zA-Z0-9_]*$//; + + my @deps = split /[^a-zA-Z0-9_]+/, $deps; + + $ifdeps[$iflevel++] = join ':', @deps; + + } elsif (/^endif/) { + + $iflevel-- if ($iflevel); + + # stop on "help" + } elsif (/^\s*help\s*$/) { + $state = "NONE"; + } + } + close($kinfile); +} + +if ($kconfig) { + read_kconfig($kconfig); +} + +# Makefiles can use variables to define their dependencies +sub convert_vars { + my ($line, %vars) = @_; + + my $process = ""; + + while ($line =~ s/^(.*?)(\$\((.*?)\))//) { + my $start = $1; + my $variable = $2; + my $var = $3; + + if (defined($vars{$var})) { + $process .= $start . $vars{$var}; + } else { + $process .= $start . $variable; + } + } + + $process .= $line; + + return $process; +} + +# Read all Makefiles to map the configs to the objects +foreach my $makefile (@makefiles) { + + my $line = ""; + my %make_vars; + + open(my $infile, '<', $makefile) || die "Can't open $makefile"; + while (<$infile>) { + # if this line ends with a backslash, continue + chomp; + if (/^(.*)\\$/) { + $line .= $1; + next; + } + + $line .= $_; + $_ = $line; + $line = ""; + + my $objs; + + # Convert variables in a line (could define configs) + $_ = convert_vars($_, %make_vars); + + # collect objects after obj-$(CONFIG_FOO_BAR) + if (/obj-\$\((CONFIG_[^\)]*)\)\s*[+:]?=\s*(.*)/) { + $var = $1; + $objs = $2; + + # check if variables are set + } elsif (/^\s*(\S+)\s*[:]?=\s*(.*\S)/) { + $make_vars{$1} = $2; + } + if (defined($objs)) { + foreach my $obj (split /\s+/,$objs) { + $obj =~ s/-/_/g; + if ($obj =~ /(.*)\.o$/) { + # Objects may be enabled by more than one config. + # Store configs in an array. + my @arr; + + if (defined($objects{$1})) { + @arr = @{$objects{$1}}; + } + + $arr[$#arr+1] = $var; + + # The objects have a hash mapping to a reference + # of an array of configs. + $objects{$1} = \@arr; + } + } + } + } + close($infile); +} + +my %modules; +my $linfile; + +if (defined($lsmod_file)) { + if ( ! -f $lsmod_file) { + if ( -f $ENV{'objtree'}."/".$lsmod_file) { + $lsmod_file = $ENV{'objtree'}."/".$lsmod_file; + } else { + die "$lsmod_file not found"; + } + } + + my $otype = ( -x $lsmod_file) ? '-|' : '<'; + open($linfile, $otype, $lsmod_file); + +} else { + + # see what modules are loaded on this system + my $lsmod; + + foreach my $dir ( ("/sbin", "/bin", "/usr/sbin", "/usr/bin") ) { + if ( -x "$dir/lsmod" ) { + $lsmod = "$dir/lsmod"; + last; + } +} + if (!defined($lsmod)) { + # try just the path + $lsmod = "lsmod"; + } + + open($linfile, '-|', $lsmod) || die "Can not call lsmod with $lsmod"; +} + +while (<$linfile>) { + next if (/^Module/); # Skip the first line. + if (/^(\S+)/) { + $modules{$1} = 1; + } +} +close ($linfile); + +# add to the configs hash all configs that are needed to enable +# a loaded module. This is a direct obj-${CONFIG_FOO} += bar.o +# where we know we need bar.o so we add FOO to the list. +my %configs; +foreach my $module (keys(%modules)) { + if (defined($objects{$module})) { + my @arr = @{$objects{$module}}; + foreach my $conf (@arr) { + $configs{$conf} = $module; + dprint "$conf added by direct ($module)\n"; + if ($debugprint) { + my $c=$conf; + $c =~ s/^CONFIG_//; + if (defined($depends{$c})) { + dprint " deps = $depends{$c}\n"; + } else { + dprint " no deps\n"; + } + } + } + } else { + # Most likely, someone has a custom (binary?) module loaded. + print STDERR "$module config not found!!\n"; + } +} + +# Read the current config, and see what is enabled. We want to +# ignore configs that we would not enable anyway. + +my %orig_configs; +my $valid = "A-Za-z_0-9"; + +foreach my $line (@config_file) { + $_ = $line; + + if (/(CONFIG_[$valid]*)=(m|y)/) { + $orig_configs{$1} = $2; + } +} + +my $repeat = 1; + +my $depconfig; + +# +# Note, we do not care about operands (like: &&, ||, !) we want to add any +# config that is in the depend list of another config. This script does +# not enable configs that are not already enabled. If we come across a +# config A that depends on !B, we can still add B to the list of depends +# to keep on. If A was on in the original config, B would not have been +# and B would not be turned on by this script. +# +sub parse_config_depends +{ + my ($p) = @_; + + while ($p =~ /[$valid]/) { + + if ($p =~ /^[^$valid]*([$valid]+)/) { + my $conf = "CONFIG_" . $1; + + $p =~ s/^[^$valid]*[$valid]+//; + + # We only need to process if the depend config is a module + if (!defined($orig_configs{$conf}) || !$orig_configs{conf} eq "m") { + next; + } + + if (!defined($configs{$conf})) { + # We must make sure that this config has its + # dependencies met. + $repeat = 1; # do again + dprint "$conf selected by depend $depconfig\n"; + $configs{$conf} = 1; + } + } else { + die "this should never happen"; + } + } +} + +# Select is treated a bit differently than depends. We call this +# when a config has no prompt and requires another config to be +# selected. We use to just select all configs that selected this +# config, but found that that can balloon into enabling hundreds +# of configs that we do not care about. +# +# The idea is we look at all the configs that select it. If one +# is already in our list of configs to enable, then there's nothing +# else to do. If there isn't, we pick the first config that was +# enabled in the orignal config and use that. +sub parse_config_selects +{ + my ($config, $p) = @_; + + my $next_config; + + while ($p =~ /[$valid]/) { + + if ($p =~ /^[^$valid]*([$valid]+)/) { + my $conf = "CONFIG_" . $1; + + $p =~ s/^[^$valid]*[$valid]+//; + + # Make sure that this config exists in the current .config file + if (!defined($orig_configs{$conf})) { + dprint "$conf not set for $config select\n"; + next; + } + + # Check if something other than a module selects this config + if (defined($orig_configs{$conf}) && $orig_configs{$conf} ne "m") { + dprint "$conf (non module) selects config, we are good\n"; + # we are good with this + return; + } + if (defined($configs{$conf})) { + dprint "$conf selects $config so we are good\n"; + # A set config selects this config, we are good + return; + } + # Set this config to be selected + if (!defined($next_config)) { + $next_config = $conf; + } + } else { + die "this should never happen"; + } + } + + # If no possible config selected this, then something happened. + if (!defined($next_config)) { + print STDERR "WARNING: $config is required, but nothing in the\n"; + print STDERR " current config selects it.\n"; + return; + } + + # If we are here, then we found no config that is set and + # selects this config. Repeat. + $repeat = 1; + # Make this config need to be selected + $configs{$next_config} = 1; + dprint "$next_config selected by select $config\n"; +} + +my %process_selects; + +# loop through all configs, select their dependencies. +sub loop_depend { + $repeat = 1; + + while ($repeat) { + $repeat = 0; + + forloop: + foreach my $config (keys %configs) { + + # If this config is not a module, we do not need to process it + if (defined($orig_configs{$config}) && $orig_configs{$config} ne "m") { + next forloop; + } + + $config =~ s/^CONFIG_//; + $depconfig = $config; + + if (defined($depends{$config})) { + # This config has dependencies. Make sure they are also included + parse_config_depends $depends{$config}; + } + + # If the config has no prompt, then we need to check if a config + # that is enabled selected it. Or if we need to enable one. + if (!defined($prompts{$config}) && defined($selects{$config})) { + $process_selects{$config} = 1; + } + } + } +} + +sub loop_select { + + foreach my $config (keys %process_selects) { + $config =~ s/^CONFIG_//; + + dprint "Process select $config\n"; + + # config has no prompt and must be selected. + parse_config_selects $config, $selects{$config}; + } +} + +while ($repeat) { + # Get the first set of configs and their dependencies. + loop_depend; + + $repeat = 0; + + # Now we need to see if we have to check selects; + loop_select; +} + +my %setconfigs; + +# Finally, read the .config file and turn off any module enabled that +# we could not find a reason to keep enabled. +foreach my $line (@config_file) { + $_ = $line; + + if (/CONFIG_IKCONFIG/) { + if (/# CONFIG_IKCONFIG is not set/) { + # enable IKCONFIG at least as a module + print "CONFIG_IKCONFIG=m\n"; + # don't ask about PROC + print "# CONFIG_IKCONFIG_PROC is not set\n"; + } else { + print; + } + next; + } + + if (/^(CONFIG.*)=(m|y)/) { + if (defined($configs{$1})) { + if ($localyesconfig) { + $setconfigs{$1} = 'y'; + print "$1=y\n"; + next; + } else { + $setconfigs{$1} = $2; + } + } elsif ($2 eq "m") { + print "# $1 is not set\n"; + next; + } + } + print; +} + +# Integrity check, make sure all modules that we want enabled do +# indeed have their configs set. +loop: +foreach my $module (keys(%modules)) { + if (defined($objects{$module})) { + my @arr = @{$objects{$module}}; + foreach my $conf (@arr) { + if (defined($setconfigs{$conf})) { + next loop; + } + } + print STDERR "module $module did not have configs"; + foreach my $conf (@arr) { + print STDERR " " , $conf; + } + print STDERR "\n"; + } +} diff --git a/scripts/kconfig/symbol.c b/scripts/kconfig/symbol.c new file mode 100644 index 0000000000..7caabdb51c --- /dev/null +++ b/scripts/kconfig/symbol.c @@ -0,0 +1,1373 @@ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include +#include + +#include "lkc.h" + +struct symbol symbol_yes = { + .name = "y", + .curr = { "y", yes }, + .flags = SYMBOL_CONST|SYMBOL_VALID, +}, symbol_mod = { + .name = "m", + .curr = { "m", mod }, + .flags = SYMBOL_CONST|SYMBOL_VALID, +}, symbol_no = { + .name = "n", + .curr = { "n", no }, + .flags = SYMBOL_CONST|SYMBOL_VALID, +}, symbol_empty = { + .name = "", + .curr = { "", no }, + .flags = SYMBOL_VALID, +}; + +struct symbol *sym_defconfig_list; +struct symbol *modules_sym; +tristate modules_val; + +struct expr *sym_env_list; + +static void sym_add_default(struct symbol *sym, const char *def) +{ + struct property *prop = prop_alloc(P_DEFAULT, sym); + + prop->expr = expr_alloc_symbol(sym_lookup(def, SYMBOL_CONST)); +} + +void sym_init(void) +{ + struct symbol *sym; + struct utsname uts; + static bool inited = false; + + if (inited) + return; + inited = true; + + uname(&uts); + + sym = sym_lookup("UNAME_RELEASE", 0); + sym->type = S_STRING; + sym->flags |= SYMBOL_AUTO; + sym_add_default(sym, uts.release); +} + +enum symbol_type sym_get_type(struct symbol *sym) +{ + enum symbol_type type = sym->type; + + if (type == S_TRISTATE) { + if (sym_is_choice_value(sym) && sym->visible == yes) + type = S_BOOLEAN; + else if (modules_val == no) + type = S_BOOLEAN; + } + return type; +} + +const char *sym_type_name(enum symbol_type type) +{ + switch (type) { + case S_BOOLEAN: + return "boolean"; + case S_TRISTATE: + return "tristate"; + case S_INT: + return "integer"; + case S_HEX: + return "hex"; + case S_STRING: + return "string"; + case S_UNKNOWN: + return "unknown"; + case S_OTHER: + break; + } + return "???"; +} + +struct property *sym_get_choice_prop(struct symbol *sym) +{ + struct property *prop; + + for_all_choices(sym, prop) + return prop; + return NULL; +} + +struct property *sym_get_env_prop(struct symbol *sym) +{ + struct property *prop; + + for_all_properties(sym, prop, P_ENV) + return prop; + return NULL; +} + +struct property *sym_get_default_prop(struct symbol *sym) +{ + struct property *prop; + + for_all_defaults(sym, prop) { + prop->visible.tri = expr_calc_value(prop->visible.expr); + if (prop->visible.tri != no) + return prop; + } + return NULL; +} + +static struct property *sym_get_range_prop(struct symbol *sym) +{ + struct property *prop; + + for_all_properties(sym, prop, P_RANGE) { + prop->visible.tri = expr_calc_value(prop->visible.expr); + if (prop->visible.tri != no) + return prop; + } + return NULL; +} + +static long long sym_get_range_val(struct symbol *sym, int base) +{ + sym_calc_value(sym); + switch (sym->type) { + case S_INT: + base = 10; + break; + case S_HEX: + base = 16; + break; + default: + break; + } + return strtoll(sym->curr.val, NULL, base); +} + +static void sym_validate_range(struct symbol *sym) +{ + struct property *prop; + int base; + long long val, val2; + char str[64]; + + switch (sym->type) { + case S_INT: + base = 10; + break; + case S_HEX: + base = 16; + break; + default: + return; + } + prop = sym_get_range_prop(sym); + if (!prop) + return; + val = strtoll(sym->curr.val, NULL, base); + val2 = sym_get_range_val(prop->expr->left.sym, base); + if (val >= val2) { + val2 = sym_get_range_val(prop->expr->right.sym, base); + if (val <= val2) + return; + } + if (sym->type == S_INT) + sprintf(str, "%lld", val2); + else + sprintf(str, "0x%llx", val2); + sym->curr.val = strdup(str); +} + +static void sym_calc_visibility(struct symbol *sym) +{ + struct property *prop; + tristate tri; + + /* any prompt visible? */ + tri = no; + for_all_prompts(sym, prop) { + prop->visible.tri = expr_calc_value(prop->visible.expr); + tri = EXPR_OR(tri, prop->visible.tri); + } + if (tri == mod && (sym->type != S_TRISTATE || modules_val == no)) + tri = yes; + if (sym->visible != tri) { + sym->visible = tri; + sym_set_changed(sym); + } + if (sym_is_choice_value(sym)) + return; + /* defaulting to "yes" if no explicit "depends on" are given */ + tri = yes; + if (sym->dir_dep.expr) + tri = expr_calc_value(sym->dir_dep.expr); + if (tri == mod) + tri = yes; + if (sym->dir_dep.tri != tri) { + sym->dir_dep.tri = tri; + sym_set_changed(sym); + } + tri = no; + if (sym->rev_dep.expr) + tri = expr_calc_value(sym->rev_dep.expr); + if (tri == mod && sym_get_type(sym) == S_BOOLEAN) + tri = yes; + if (sym->rev_dep.tri != tri) { + sym->rev_dep.tri = tri; + sym_set_changed(sym); + } +} + +/* + * Find the default symbol for a choice. + * First try the default values for the choice symbol + * Next locate the first visible choice value + * Return NULL if none was found + */ +struct symbol *sym_choice_default(struct symbol *sym) +{ + struct symbol *def_sym; + struct property *prop; + struct expr *e; + + /* any of the defaults visible? */ + for_all_defaults(sym, prop) { + prop->visible.tri = expr_calc_value(prop->visible.expr); + if (prop->visible.tri == no) + continue; + def_sym = prop_get_symbol(prop); + if (def_sym->visible != no) + return def_sym; + } + + /* just get the first visible value */ + prop = sym_get_choice_prop(sym); + expr_list_for_each_sym(prop->expr, e, def_sym) + if (def_sym->visible != no) + return def_sym; + + /* failed to locate any defaults */ + return NULL; +} + +static struct symbol *sym_calc_choice(struct symbol *sym) +{ + struct symbol *def_sym; + struct property *prop; + struct expr *e; + int flags; + + /* first calculate all choice values' visibilities */ + flags = sym->flags; + prop = sym_get_choice_prop(sym); + expr_list_for_each_sym(prop->expr, e, def_sym) { + sym_calc_visibility(def_sym); + if (def_sym->visible != no) + flags &= def_sym->flags; + } + + sym->flags &= flags | ~SYMBOL_DEF_USER; + + /* is the user choice visible? */ + def_sym = sym->def[S_DEF_USER].val; + if (def_sym && def_sym->visible != no) + return def_sym; + + def_sym = sym_choice_default(sym); + + if (def_sym == NULL) + /* no choice? reset tristate value */ + sym->curr.tri = no; + + return def_sym; +} + +void sym_calc_value(struct symbol *sym) +{ + struct symbol_value newval, oldval; + struct property *prop; + struct expr *e; + + if (!sym) + return; + + if (sym->flags & SYMBOL_VALID) + return; + + if (sym_is_choice_value(sym) && + sym->flags & SYMBOL_NEED_SET_CHOICE_VALUES) { + sym->flags &= ~SYMBOL_NEED_SET_CHOICE_VALUES; + prop = sym_get_choice_prop(sym); + sym_calc_value(prop_get_symbol(prop)); + } + + sym->flags |= SYMBOL_VALID; + + oldval = sym->curr; + + switch (sym->type) { + case S_INT: + case S_HEX: + case S_STRING: + newval = symbol_empty.curr; + break; + case S_BOOLEAN: + case S_TRISTATE: + newval = symbol_no.curr; + break; + default: + sym->curr.val = sym->name; + sym->curr.tri = no; + return; + } + if (!sym_is_choice_value(sym)) + sym->flags &= ~SYMBOL_WRITE; + + sym_calc_visibility(sym); + + /* set default if recursively called */ + sym->curr = newval; + + switch (sym_get_type(sym)) { + case S_BOOLEAN: + case S_TRISTATE: + if (sym_is_choice_value(sym) && sym->visible == yes) { + prop = sym_get_choice_prop(sym); + newval.tri = (prop_get_symbol(prop)->curr.val == sym) ? yes : no; + } else { + if (sym->visible != no) { + /* if the symbol is visible use the user value + * if available, otherwise try the default value + */ + sym->flags |= SYMBOL_WRITE; + if (sym_has_value(sym)) { + newval.tri = EXPR_AND(sym->def[S_DEF_USER].tri, + sym->visible); + goto calc_newval; + } + } + if (sym->rev_dep.tri != no) + sym->flags |= SYMBOL_WRITE; + if (!sym_is_choice(sym)) { + prop = sym_get_default_prop(sym); + if (prop) { + sym->flags |= SYMBOL_WRITE; + newval.tri = EXPR_AND(expr_calc_value(prop->expr), + prop->visible.tri); + } + } + calc_newval: + if (sym->dir_dep.tri == no && sym->rev_dep.tri != no) { + struct expr *e; + e = expr_simplify_unmet_dep(sym->rev_dep.expr, + sym->dir_dep.expr); + fprintf(stderr, "warning: ("); + expr_fprint(e, stderr); + fprintf(stderr, ") selects %s which has unmet direct dependencies (", + sym->name); + expr_fprint(sym->dir_dep.expr, stderr); + fprintf(stderr, ")\n"); + expr_free(e); + } + newval.tri = EXPR_OR(newval.tri, sym->rev_dep.tri); + } + if (newval.tri == mod && sym_get_type(sym) == S_BOOLEAN) + newval.tri = yes; + break; + case S_STRING: + case S_HEX: + case S_INT: + if (sym->visible != no) { + sym->flags |= SYMBOL_WRITE; + if (sym_has_value(sym)) { + newval.val = sym->def[S_DEF_USER].val; + break; + } + } + prop = sym_get_default_prop(sym); + if (prop) { + struct symbol *ds = prop_get_symbol(prop); + if (ds) { + sym->flags |= SYMBOL_WRITE; + sym_calc_value(ds); + newval.val = ds->curr.val; + } + } + break; + default: + ; + } + + sym->curr = newval; + if (sym_is_choice(sym) && newval.tri == yes) + sym->curr.val = sym_calc_choice(sym); + sym_validate_range(sym); + + if (memcmp(&oldval, &sym->curr, sizeof(oldval))) { + sym_set_changed(sym); + if (modules_sym == sym) { + sym_set_all_changed(); + modules_val = modules_sym->curr.tri; + } + } + + if (sym_is_choice(sym)) { + struct symbol *choice_sym; + + prop = sym_get_choice_prop(sym); + expr_list_for_each_sym(prop->expr, e, choice_sym) { + if ((sym->flags & SYMBOL_WRITE) && + choice_sym->visible != no) + choice_sym->flags |= SYMBOL_WRITE; + if (sym->flags & SYMBOL_CHANGED) + sym_set_changed(choice_sym); + } + } + + if (sym->flags & SYMBOL_AUTO) + sym->flags &= ~SYMBOL_WRITE; + + if (sym->flags & SYMBOL_NEED_SET_CHOICE_VALUES) + set_all_choice_values(sym); +} + +void sym_clear_all_valid(void) +{ + struct symbol *sym; + int i; + + for_all_symbols(i, sym) + sym->flags &= ~SYMBOL_VALID; + sym_add_change_count(1); + if (modules_sym) + sym_calc_value(modules_sym); +} + +void sym_set_changed(struct symbol *sym) +{ + struct property *prop; + + sym->flags |= SYMBOL_CHANGED; + for (prop = sym->prop; prop; prop = prop->next) { + if (prop->menu) + prop->menu->flags |= MENU_CHANGED; + } +} + +void sym_set_all_changed(void) +{ + struct symbol *sym; + int i; + + for_all_symbols(i, sym) + sym_set_changed(sym); +} + +bool sym_tristate_within_range(struct symbol *sym, tristate val) +{ + int type = sym_get_type(sym); + + if (sym->visible == no) + return false; + + if (type != S_BOOLEAN && type != S_TRISTATE) + return false; + + if (type == S_BOOLEAN && val == mod) + return false; + if (sym->visible <= sym->rev_dep.tri) + return false; + if (sym_is_choice_value(sym) && sym->visible == yes) + return val == yes; + return val >= sym->rev_dep.tri && val <= sym->visible; +} + +bool sym_set_tristate_value(struct symbol *sym, tristate val) +{ + tristate oldval = sym_get_tristate_value(sym); + + if (oldval != val && !sym_tristate_within_range(sym, val)) + return false; + + if (!(sym->flags & SYMBOL_DEF_USER)) { + sym->flags |= SYMBOL_DEF_USER; + sym_set_changed(sym); + } + /* + * setting a choice value also resets the new flag of the choice + * symbol and all other choice values. + */ + if (sym_is_choice_value(sym) && val == yes) { + struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym)); + struct property *prop; + struct expr *e; + + cs->def[S_DEF_USER].val = sym; + cs->flags |= SYMBOL_DEF_USER; + prop = sym_get_choice_prop(cs); + for (e = prop->expr; e; e = e->left.expr) { + if (e->right.sym->visible != no) + e->right.sym->flags |= SYMBOL_DEF_USER; + } + } + + sym->def[S_DEF_USER].tri = val; + if (oldval != val) + sym_clear_all_valid(); + + return true; +} + +tristate sym_toggle_tristate_value(struct symbol *sym) +{ + tristate oldval, newval; + + oldval = newval = sym_get_tristate_value(sym); + do { + switch (newval) { + case no: + newval = mod; + break; + case mod: + newval = yes; + break; + case yes: + newval = no; + break; + } + if (sym_set_tristate_value(sym, newval)) + break; + } while (oldval != newval); + return newval; +} + +bool sym_string_valid(struct symbol *sym, const char *str) +{ + signed char ch; + + switch (sym->type) { + case S_STRING: + return true; + case S_INT: + ch = *str++; + if (ch == '-') + ch = *str++; + if (!isdigit(ch)) + return false; + if (ch == '0' && *str != 0) + return false; + while ((ch = *str++)) { + if (!isdigit(ch)) + return false; + } + return true; + case S_HEX: + if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X')) + str += 2; + ch = *str++; + do { + if (!isxdigit(ch)) + return false; + } while ((ch = *str++)); + return true; + case S_BOOLEAN: + case S_TRISTATE: + switch (str[0]) { + case 'y': case 'Y': + case 'm': case 'M': + case 'n': case 'N': + return true; + } + return false; + default: + return false; + } +} + +bool sym_string_within_range(struct symbol *sym, const char *str) +{ + struct property *prop; + long long val; + + switch (sym->type) { + case S_STRING: + return sym_string_valid(sym, str); + case S_INT: + if (!sym_string_valid(sym, str)) + return false; + prop = sym_get_range_prop(sym); + if (!prop) + return true; + val = strtoll(str, NULL, 10); + return val >= sym_get_range_val(prop->expr->left.sym, 10) && + val <= sym_get_range_val(prop->expr->right.sym, 10); + case S_HEX: + if (!sym_string_valid(sym, str)) + return false; + prop = sym_get_range_prop(sym); + if (!prop) + return true; + val = strtoll(str, NULL, 16); + return val >= sym_get_range_val(prop->expr->left.sym, 16) && + val <= sym_get_range_val(prop->expr->right.sym, 16); + case S_BOOLEAN: + case S_TRISTATE: + switch (str[0]) { + case 'y': case 'Y': + return sym_tristate_within_range(sym, yes); + case 'm': case 'M': + return sym_tristate_within_range(sym, mod); + case 'n': case 'N': + return sym_tristate_within_range(sym, no); + } + return false; + default: + return false; + } +} + +bool sym_set_string_value(struct symbol *sym, const char *newval) +{ + const char *oldval; + char *val; + int size; + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + switch (newval[0]) { + case 'y': case 'Y': + return sym_set_tristate_value(sym, yes); + case 'm': case 'M': + return sym_set_tristate_value(sym, mod); + case 'n': case 'N': + return sym_set_tristate_value(sym, no); + } + return false; + default: + ; + } + + if (!sym_string_within_range(sym, newval)) + return false; + + if (!(sym->flags & SYMBOL_DEF_USER)) { + sym->flags |= SYMBOL_DEF_USER; + sym_set_changed(sym); + } + + oldval = sym->def[S_DEF_USER].val; + size = strlen(newval) + 1; + if (sym->type == S_HEX && (newval[0] != '0' || (newval[1] != 'x' && newval[1] != 'X'))) { + size += 2; + sym->def[S_DEF_USER].val = val = xmalloc(size); + *val++ = '0'; + *val++ = 'x'; + } else if (!oldval || strcmp(oldval, newval)) + sym->def[S_DEF_USER].val = val = xmalloc(size); + else + return true; + + strcpy(val, newval); + free((void *)oldval); + sym_clear_all_valid(); + + return true; +} + +/* + * Find the default value associated to a symbol. + * For tristate symbol handle the modules=n case + * in which case "m" becomes "y". + * If the symbol does not have any default then fallback + * to the fixed default values. + */ +const char *sym_get_string_default(struct symbol *sym) +{ + struct property *prop; + struct symbol *ds; + const char *str; + tristate val; + + sym_calc_visibility(sym); + sym_calc_value(modules_sym); + val = symbol_no.curr.tri; + str = symbol_empty.curr.val; + + /* If symbol has a default value look it up */ + prop = sym_get_default_prop(sym); + if (prop != NULL) { + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + /* The visibility may limit the value from yes => mod */ + val = EXPR_AND(expr_calc_value(prop->expr), prop->visible.tri); + break; + default: + /* + * The following fails to handle the situation + * where a default value is further limited by + * the valid range. + */ + ds = prop_get_symbol(prop); + if (ds != NULL) { + sym_calc_value(ds); + str = (const char *)ds->curr.val; + } + } + } + + /* Handle select statements */ + val = EXPR_OR(val, sym->rev_dep.tri); + + /* transpose mod to yes if modules are not enabled */ + if (val == mod) + if (!sym_is_choice_value(sym) && modules_sym->curr.tri == no) + val = yes; + + /* transpose mod to yes if type is bool */ + if (sym->type == S_BOOLEAN && val == mod) + val = yes; + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + switch (val) { + case no: return "n"; + case mod: return "m"; + case yes: return "y"; + } + case S_INT: + case S_HEX: + return str; + case S_STRING: + return str; + case S_OTHER: + case S_UNKNOWN: + break; + } + return ""; +} + +const char *sym_get_string_value(struct symbol *sym) +{ + tristate val; + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + val = sym_get_tristate_value(sym); + switch (val) { + case no: + return "n"; + case mod: + sym_calc_value(modules_sym); + return (modules_sym->curr.tri == no) ? "n" : "m"; + case yes: + return "y"; + } + break; + default: + ; + } + return (const char *)sym->curr.val; +} + +bool sym_is_changable(struct symbol *sym) +{ + return sym->visible > sym->rev_dep.tri; +} + +static unsigned strhash(const char *s) +{ + /* fnv32 hash */ + unsigned hash = 2166136261U; + for (; *s; s++) + hash = (hash ^ *s) * 0x01000193; + return hash; +} + +struct symbol *sym_lookup(const char *name, int flags) +{ + struct symbol *symbol; + char *new_name; + int hash; + + if (name) { + if (name[0] && !name[1]) { + switch (name[0]) { + case 'y': return &symbol_yes; + case 'm': return &symbol_mod; + case 'n': return &symbol_no; + } + } + hash = strhash(name) % SYMBOL_HASHSIZE; + + for (symbol = symbol_hash[hash]; symbol; symbol = symbol->next) { + if (symbol->name && + !strcmp(symbol->name, name) && + (flags ? symbol->flags & flags + : !(symbol->flags & (SYMBOL_CONST|SYMBOL_CHOICE)))) + return symbol; + } + new_name = strdup(name); + } else { + new_name = NULL; + hash = 0; + } + + symbol = xmalloc(sizeof(*symbol)); + memset(symbol, 0, sizeof(*symbol)); + symbol->name = new_name; + symbol->type = S_UNKNOWN; + symbol->flags |= flags; + + symbol->next = symbol_hash[hash]; + symbol_hash[hash] = symbol; + + return symbol; +} + +struct symbol *sym_find(const char *name) +{ + struct symbol *symbol = NULL; + int hash = 0; + + if (!name) + return NULL; + + if (name[0] && !name[1]) { + switch (name[0]) { + case 'y': return &symbol_yes; + case 'm': return &symbol_mod; + case 'n': return &symbol_no; + } + } + hash = strhash(name) % SYMBOL_HASHSIZE; + + for (symbol = symbol_hash[hash]; symbol; symbol = symbol->next) { + if (symbol->name && + !strcmp(symbol->name, name) && + !(symbol->flags & SYMBOL_CONST)) + break; + } + + return symbol; +} + +/* + * Expand symbol's names embedded in the string given in argument. Symbols' + * name to be expanded shall be prefixed by a '$'. Unknown symbol expands to + * the empty string. + */ +const char *sym_expand_string_value(const char *in) +{ + const char *src; + char *res; + size_t reslen; + + reslen = strlen(in) + 1; + res = xmalloc(reslen); + res[0] = '\0'; + + while ((src = strchr(in, '$'))) { + char *p, name[SYMBOL_MAXLENGTH]; + const char *symval = ""; + struct symbol *sym; + size_t newlen; + + strncat(res, in, src - in); + src++; + + p = name; + while (isalnum(*src) || *src == '_') + *p++ = *src++; + *p = '\0'; + + sym = sym_find(name); + if (sym != NULL) { + sym_calc_value(sym); + symval = sym_get_string_value(sym); + } + + newlen = strlen(res) + strlen(symval) + strlen(src) + 1; + if (newlen > reslen) { + reslen = newlen; + res = realloc(res, reslen); + } + + strcat(res, symval); + in = src; + } + strcat(res, in); + + return res; +} + +const char *sym_escape_string_value(const char *in) +{ + const char *p; + size_t reslen; + char *res; + size_t l; + + reslen = strlen(in) + strlen("\"\"") + 1; + + p = in; + for (;;) { + l = strcspn(p, "\"\\"); + p += l; + + if (p[0] == '\0') + break; + + reslen++; + p++; + } + + res = xmalloc(reslen); + res[0] = '\0'; + + strcat(res, "\""); + + p = in; + for (;;) { + l = strcspn(p, "\"\\"); + strncat(res, p, l); + p += l; + + if (p[0] == '\0') + break; + + strcat(res, "\\"); + strncat(res, p++, 1); + } + + strcat(res, "\""); + return res; +} + +struct sym_match { + struct symbol *sym; + off_t so, eo; +}; + +/* Compare matched symbols as thus: + * - first, symbols that match exactly + * - then, alphabetical sort + */ +static int sym_rel_comp(const void *sym1, const void *sym2) +{ + const struct sym_match *s1 = sym1; + const struct sym_match *s2 = sym2; + int exact1, exact2; + + /* Exact match: + * - if matched length on symbol s1 is the length of that symbol, + * then this symbol should come first; + * - if matched length on symbol s2 is the length of that symbol, + * then this symbol should come first. + * Note: since the search can be a regexp, both symbols may match + * exactly; if this is the case, we can't decide which comes first, + * and we fallback to sorting alphabetically. + */ + exact1 = (s1->eo - s1->so) == strlen(s1->sym->name); + exact2 = (s2->eo - s2->so) == strlen(s2->sym->name); + if (exact1 && !exact2) + return -1; + if (!exact1 && exact2) + return 1; + + /* As a fallback, sort symbols alphabetically */ + return strcmp(s1->sym->name, s2->sym->name); +} + +struct symbol **sym_re_search(const char *pattern) +{ + struct symbol *sym, **sym_arr = NULL; + struct sym_match *sym_match_arr = NULL; + int i, cnt, size; + regex_t re; + regmatch_t match[1]; + + cnt = size = 0; + /* Skip if empty */ + if (strlen(pattern) == 0) + return NULL; + if (regcomp(&re, pattern, REG_EXTENDED|REG_ICASE)) + return NULL; + + for_all_symbols(i, sym) { + if (sym->flags & SYMBOL_CONST || !sym->name) + continue; + if (regexec(&re, sym->name, 1, match, 0)) + continue; + if (cnt >= size) { + void *tmp; + size += 16; + tmp = realloc(sym_match_arr, size * sizeof(struct sym_match)); + if (!tmp) + goto sym_re_search_free; + sym_match_arr = tmp; + } + sym_calc_value(sym); + /* As regexec returned 0, we know we have a match, so + * we can use match[0].rm_[se]o without further checks + */ + sym_match_arr[cnt].so = match[0].rm_so; + sym_match_arr[cnt].eo = match[0].rm_eo; + sym_match_arr[cnt++].sym = sym; + } + if (sym_match_arr) { + qsort(sym_match_arr, cnt, sizeof(struct sym_match), sym_rel_comp); + sym_arr = malloc((cnt+1) * sizeof(struct symbol)); + if (!sym_arr) + goto sym_re_search_free; + for (i = 0; i < cnt; i++) + sym_arr[i] = sym_match_arr[i].sym; + sym_arr[cnt] = NULL; + } +sym_re_search_free: + /* sym_match_arr can be NULL if no match, but free(NULL) is OK */ + free(sym_match_arr); + regfree(&re); + + return sym_arr; +} + +/* + * When we check for recursive dependencies we use a stack to save + * current state so we can print out relevant info to user. + * The entries are located on the call stack so no need to free memory. + * Note insert() remove() must always match to properly clear the stack. + */ +static struct dep_stack { + struct dep_stack *prev, *next; + struct symbol *sym; + struct property *prop; + struct expr *expr; +} *check_top; + +static void dep_stack_insert(struct dep_stack *stack, struct symbol *sym) +{ + memset(stack, 0, sizeof(*stack)); + if (check_top) + check_top->next = stack; + stack->prev = check_top; + stack->sym = sym; + check_top = stack; +} + +static void dep_stack_remove(void) +{ + check_top = check_top->prev; + if (check_top) + check_top->next = NULL; +} + +/* + * Called when we have detected a recursive dependency. + * check_top point to the top of the stact so we use + * the ->prev pointer to locate the bottom of the stack. + */ +static void sym_check_print_recursive(struct symbol *last_sym) +{ + struct dep_stack *stack; + struct symbol *sym, *next_sym; + struct menu *menu = NULL; + struct property *prop; + struct dep_stack cv_stack; + + if (sym_is_choice_value(last_sym)) { + dep_stack_insert(&cv_stack, last_sym); + last_sym = prop_get_symbol(sym_get_choice_prop(last_sym)); + } + + for (stack = check_top; stack != NULL; stack = stack->prev) + if (stack->sym == last_sym) + break; + if (!stack) { + fprintf(stderr, "unexpected recursive dependency error\n"); + return; + } + + for (; stack; stack = stack->next) { + sym = stack->sym; + next_sym = stack->next ? stack->next->sym : last_sym; + prop = stack->prop; + if (prop == NULL) + prop = stack->sym->prop; + + /* for choice values find the menu entry (used below) */ + if (sym_is_choice(sym) || sym_is_choice_value(sym)) { + for (prop = sym->prop; prop; prop = prop->next) { + menu = prop->menu; + if (prop->menu) + break; + } + } + if (stack->sym == last_sym) + fprintf(stderr, "%s:%d:error: recursive dependency detected!\n", + prop->file->name, prop->lineno); + if (stack->expr) { + fprintf(stderr, "%s:%d:\tsymbol %s %s value contains %s\n", + prop->file->name, prop->lineno, + sym->name ? sym->name : "", + prop_get_type_name(prop->type), + next_sym->name ? next_sym->name : ""); + } else if (stack->prop) { + fprintf(stderr, "%s:%d:\tsymbol %s depends on %s\n", + prop->file->name, prop->lineno, + sym->name ? sym->name : "", + next_sym->name ? next_sym->name : ""); + } else if (sym_is_choice(sym)) { + fprintf(stderr, "%s:%d:\tchoice %s contains symbol %s\n", + menu->file->name, menu->lineno, + sym->name ? sym->name : "", + next_sym->name ? next_sym->name : ""); + } else if (sym_is_choice_value(sym)) { + fprintf(stderr, "%s:%d:\tsymbol %s is part of choice %s\n", + menu->file->name, menu->lineno, + sym->name ? sym->name : "", + next_sym->name ? next_sym->name : ""); + } else { + fprintf(stderr, "%s:%d:\tsymbol %s is selected by %s\n", + prop->file->name, prop->lineno, + sym->name ? sym->name : "", + next_sym->name ? next_sym->name : ""); + } + } + + if (check_top == &cv_stack) + dep_stack_remove(); +} + +static struct symbol *sym_check_expr_deps(struct expr *e) +{ + struct symbol *sym; + + if (!e) + return NULL; + switch (e->type) { + case E_OR: + case E_AND: + sym = sym_check_expr_deps(e->left.expr); + if (sym) + return sym; + return sym_check_expr_deps(e->right.expr); + case E_NOT: + return sym_check_expr_deps(e->left.expr); + case E_EQUAL: + case E_UNEQUAL: + sym = sym_check_deps(e->left.sym); + if (sym) + return sym; + return sym_check_deps(e->right.sym); + case E_SYMBOL: + return sym_check_deps(e->left.sym); + default: + break; + } + printf("Oops! How to check %d?\n", e->type); + return NULL; +} + +/* return NULL when dependencies are OK */ +static struct symbol *sym_check_sym_deps(struct symbol *sym) +{ + struct symbol *sym2; + struct property *prop; + struct dep_stack stack; + + dep_stack_insert(&stack, sym); + + sym2 = sym_check_expr_deps(sym->rev_dep.expr); + if (sym2) + goto out; + + for (prop = sym->prop; prop; prop = prop->next) { + if (prop->type == P_CHOICE || prop->type == P_SELECT) + continue; + stack.prop = prop; + sym2 = sym_check_expr_deps(prop->visible.expr); + if (sym2) + break; + if (prop->type != P_DEFAULT || sym_is_choice(sym)) + continue; + stack.expr = prop->expr; + sym2 = sym_check_expr_deps(prop->expr); + if (sym2) + break; + stack.expr = NULL; + } + +out: + dep_stack_remove(); + + return sym2; +} + +static struct symbol *sym_check_choice_deps(struct symbol *choice) +{ + struct symbol *sym, *sym2; + struct property *prop; + struct expr *e; + struct dep_stack stack; + + dep_stack_insert(&stack, choice); + + prop = sym_get_choice_prop(choice); + expr_list_for_each_sym(prop->expr, e, sym) + sym->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED); + + choice->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED); + sym2 = sym_check_sym_deps(choice); + choice->flags &= ~SYMBOL_CHECK; + if (sym2) + goto out; + + expr_list_for_each_sym(prop->expr, e, sym) { + sym2 = sym_check_sym_deps(sym); + if (sym2) + break; + } +out: + expr_list_for_each_sym(prop->expr, e, sym) + sym->flags &= ~SYMBOL_CHECK; + + if (sym2 && sym_is_choice_value(sym2) && + prop_get_symbol(sym_get_choice_prop(sym2)) == choice) + sym2 = choice; + + dep_stack_remove(); + + return sym2; +} + +struct symbol *sym_check_deps(struct symbol *sym) +{ + struct symbol *sym2; + struct property *prop; + + if (sym->flags & SYMBOL_CHECK) { + sym_check_print_recursive(sym); + return sym; + } + if (sym->flags & SYMBOL_CHECKED) + return NULL; + + if (sym_is_choice_value(sym)) { + struct dep_stack stack; + + /* for choice groups start the check with main choice symbol */ + dep_stack_insert(&stack, sym); + prop = sym_get_choice_prop(sym); + sym2 = sym_check_deps(prop_get_symbol(prop)); + dep_stack_remove(); + } else if (sym_is_choice(sym)) { + sym2 = sym_check_choice_deps(sym); + } else { + sym->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED); + sym2 = sym_check_sym_deps(sym); + sym->flags &= ~SYMBOL_CHECK; + } + + if (sym2 && sym2 == sym) + sym2 = NULL; + + return sym2; +} + +struct property *prop_alloc(enum prop_type type, struct symbol *sym) +{ + struct property *prop; + struct property **propp; + + prop = xmalloc(sizeof(*prop)); + memset(prop, 0, sizeof(*prop)); + prop->type = type; + prop->sym = sym; + prop->file = current_file; + prop->lineno = zconf_lineno(); + + /* append property to the prop list of symbol */ + if (sym) { + for (propp = &sym->prop; *propp; propp = &(*propp)->next) + ; + *propp = prop; + } + + return prop; +} + +struct symbol *prop_get_symbol(struct property *prop) +{ + if (prop->expr && (prop->expr->type == E_SYMBOL || + prop->expr->type == E_LIST)) + return prop->expr->left.sym; + return NULL; +} + +const char *prop_get_type_name(enum prop_type type) +{ + switch (type) { + case P_PROMPT: + return "prompt"; + case P_ENV: + return "env"; + case P_COMMENT: + return "comment"; + case P_MENU: + return "menu"; + case P_DEFAULT: + return "default"; + case P_CHOICE: + return "choice"; + case P_SELECT: + return "select"; + case P_RANGE: + return "range"; + case P_SYMBOL: + return "symbol"; + case P_UNKNOWN: + break; + } + return "unknown"; +} + +static void prop_add_env(const char *env) +{ + struct symbol *sym, *sym2; + struct property *prop; + char *p; + + sym = current_entry->sym; + sym->flags |= SYMBOL_AUTO; + for_all_properties(sym, prop, P_ENV) { + sym2 = prop_get_symbol(prop); + if (strcmp(sym2->name, env)) + menu_warn(current_entry, "redefining environment symbol from %s", + sym2->name); + return; + } + + prop = prop_alloc(P_ENV, sym); + prop->expr = expr_alloc_symbol(sym_lookup(env, SYMBOL_CONST)); + + sym_env_list = expr_alloc_one(E_LIST, sym_env_list); + sym_env_list->right.sym = sym; + + p = getenv(env); + if (p) + sym_add_default(sym, p); + else + menu_warn(current_entry, "environment variable %s undefined", env); +} diff --git a/scripts/kconfig/util.c b/scripts/kconfig/util.c new file mode 100644 index 0000000000..94f9c83e32 --- /dev/null +++ b/scripts/kconfig/util.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2002-2005 Roman Zippel + * Copyright (C) 2002-2005 Sam Ravnborg + * + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include "lkc.h" + +/* file already present in list? If not add it */ +struct file *file_lookup(const char *name) +{ + struct file *file; + const char *file_name = sym_expand_string_value(name); + + for (file = file_list; file; file = file->next) { + if (!strcmp(name, file->name)) { + free((void *)file_name); + return file; + } + } + + file = xmalloc(sizeof(*file)); + memset(file, 0, sizeof(*file)); + file->name = file_name; + file->next = file_list; + file_list = file; + return file; +} + +/* write a dependency file as used by kbuild to track dependencies */ +int file_write_dep(const char *name) +{ + struct symbol *sym, *env_sym; + struct expr *e; + struct file *file; + FILE *out; + + if (!name) + name = ".kconfig.d"; + out = fopen("..config.tmp", "w"); + if (!out) + return 1; + fprintf(out, "deps_config := \\\n"); + for (file = file_list; file; file = file->next) { + if (file->next) + fprintf(out, "\t%s \\\n", file->name); + else + fprintf(out, "\t%s\n", file->name); + } + fprintf(out, "\n%s: \\\n" + "\t$(deps_config)\n\n", conf_get_autoconfig_name()); + + expr_list_for_each_sym(sym_env_list, e, sym) { + struct property *prop; + const char *value; + + prop = sym_get_env_prop(sym); + env_sym = prop_get_symbol(prop); + if (!env_sym) + continue; + value = getenv(env_sym->name); + if (!value) + value = ""; + fprintf(out, "ifneq \"$(%s)\" \"%s\"\n", env_sym->name, value); + fprintf(out, "%s: FORCE\n", conf_get_autoconfig_name()); + fprintf(out, "endif\n"); + } + + fprintf(out, "\n$(deps_config): ;\n"); + fclose(out); + rename("..config.tmp", name); + return 0; +} + + +/* Allocate initial growable string */ +struct gstr str_new(void) +{ + struct gstr gs; + gs.s = xmalloc(sizeof(char) * 64); + gs.len = 64; + gs.max_width = 0; + strcpy(gs.s, "\0"); + return gs; +} + +/* Allocate and assign growable string */ +struct gstr str_assign(const char *s) +{ + struct gstr gs; + gs.s = strdup(s); + gs.len = strlen(s) + 1; + gs.max_width = 0; + return gs; +} + +/* Free storage for growable string */ +void str_free(struct gstr *gs) +{ + if (gs->s) + free(gs->s); + gs->s = NULL; + gs->len = 0; +} + +/* Append to growable string */ +void str_append(struct gstr *gs, const char *s) +{ + size_t l; + if (s) { + l = strlen(gs->s) + strlen(s) + 1; + if (l > gs->len) { + gs->s = realloc(gs->s, l); + gs->len = l; + } + strcat(gs->s, s); + } +} + +/* Append printf formatted string to growable string */ +void str_printf(struct gstr *gs, const char *fmt, ...) +{ + va_list ap; + char s[10000]; /* big enough... */ + va_start(ap, fmt); + vsnprintf(s, sizeof(s), fmt, ap); + str_append(gs, s); + va_end(ap); +} + +/* Retrieve value of growable string */ +const char *str_get(struct gstr *gs) +{ + return gs->s; +} + +void *xmalloc(size_t size) +{ + void *p = malloc(size); + if (p) + return p; + fprintf(stderr, "Out of memory.\n"); + exit(1); +} + +void *xcalloc(size_t nmemb, size_t size) +{ + void *p = calloc(nmemb, size); + if (p) + return p; + fprintf(stderr, "Out of memory.\n"); + exit(1); +} diff --git a/scripts/kconfig/zconf.gperf b/scripts/kconfig/zconf.gperf new file mode 100644 index 0000000000..b6ac02d604 --- /dev/null +++ b/scripts/kconfig/zconf.gperf @@ -0,0 +1,48 @@ +%language=ANSI-C +%define hash-function-name kconf_id_hash +%define lookup-function-name kconf_id_lookup +%define string-pool-name kconf_id_strings +%compare-strncmp +%enum +%pic +%struct-type + +struct kconf_id; + +static const struct kconf_id *kconf_id_lookup(register const char *str, register unsigned int len); + +%% +mainmenu, T_MAINMENU, TF_COMMAND +menu, T_MENU, TF_COMMAND +endmenu, T_ENDMENU, TF_COMMAND +source, T_SOURCE, TF_COMMAND +choice, T_CHOICE, TF_COMMAND +endchoice, T_ENDCHOICE, TF_COMMAND +comment, T_COMMENT, TF_COMMAND +config, T_CONFIG, TF_COMMAND +menuconfig, T_MENUCONFIG, TF_COMMAND +help, T_HELP, TF_COMMAND +if, T_IF, TF_COMMAND|TF_PARAM +endif, T_ENDIF, TF_COMMAND +depends, T_DEPENDS, TF_COMMAND +optional, T_OPTIONAL, TF_COMMAND +default, T_DEFAULT, TF_COMMAND, S_UNKNOWN +prompt, T_PROMPT, TF_COMMAND +tristate, T_TYPE, TF_COMMAND, S_TRISTATE +def_tristate, T_DEFAULT, TF_COMMAND, S_TRISTATE +bool, T_TYPE, TF_COMMAND, S_BOOLEAN +boolean, T_TYPE, TF_COMMAND, S_BOOLEAN +def_bool, T_DEFAULT, TF_COMMAND, S_BOOLEAN +int, T_TYPE, TF_COMMAND, S_INT +hex, T_TYPE, TF_COMMAND, S_HEX +string, T_TYPE, TF_COMMAND, S_STRING +select, T_SELECT, TF_COMMAND +range, T_RANGE, TF_COMMAND +visible, T_VISIBLE, TF_COMMAND +option, T_OPTION, TF_COMMAND +on, T_ON, TF_PARAM +modules, T_OPT_MODULES, TF_OPTION +defconfig_list, T_OPT_DEFCONFIG_LIST,TF_OPTION +env, T_OPT_ENV, TF_OPTION +allnoconfig_y, T_OPT_ALLNOCONFIG_Y,TF_OPTION +%% diff --git a/scripts/kconfig/zconf.hash.c_shipped b/scripts/kconfig/zconf.hash.c_shipped new file mode 100644 index 0000000000..c77a8eff1e --- /dev/null +++ b/scripts/kconfig/zconf.hash.c_shipped @@ -0,0 +1,289 @@ +/* ANSI-C code produced by gperf version 3.0.4 */ +/* Command-line: gperf -t --output-file scripts/kconfig/zconf.hash.c_shipped -a -C -E -g -k '1,3,$' -p -t scripts/kconfig/zconf.gperf */ + +#if !((' ' == 32) && ('!' == 33) && ('"' == 34) && ('#' == 35) \ + && ('%' == 37) && ('&' == 38) && ('\'' == 39) && ('(' == 40) \ + && (')' == 41) && ('*' == 42) && ('+' == 43) && (',' == 44) \ + && ('-' == 45) && ('.' == 46) && ('/' == 47) && ('0' == 48) \ + && ('1' == 49) && ('2' == 50) && ('3' == 51) && ('4' == 52) \ + && ('5' == 53) && ('6' == 54) && ('7' == 55) && ('8' == 56) \ + && ('9' == 57) && (':' == 58) && (';' == 59) && ('<' == 60) \ + && ('=' == 61) && ('>' == 62) && ('?' == 63) && ('A' == 65) \ + && ('B' == 66) && ('C' == 67) && ('D' == 68) && ('E' == 69) \ + && ('F' == 70) && ('G' == 71) && ('H' == 72) && ('I' == 73) \ + && ('J' == 74) && ('K' == 75) && ('L' == 76) && ('M' == 77) \ + && ('N' == 78) && ('O' == 79) && ('P' == 80) && ('Q' == 81) \ + && ('R' == 82) && ('S' == 83) && ('T' == 84) && ('U' == 85) \ + && ('V' == 86) && ('W' == 87) && ('X' == 88) && ('Y' == 89) \ + && ('Z' == 90) && ('[' == 91) && ('\\' == 92) && (']' == 93) \ + && ('^' == 94) && ('_' == 95) && ('a' == 97) && ('b' == 98) \ + && ('c' == 99) && ('d' == 100) && ('e' == 101) && ('f' == 102) \ + && ('g' == 103) && ('h' == 104) && ('i' == 105) && ('j' == 106) \ + && ('k' == 107) && ('l' == 108) && ('m' == 109) && ('n' == 110) \ + && ('o' == 111) && ('p' == 112) && ('q' == 113) && ('r' == 114) \ + && ('s' == 115) && ('t' == 116) && ('u' == 117) && ('v' == 118) \ + && ('w' == 119) && ('x' == 120) && ('y' == 121) && ('z' == 122) \ + && ('{' == 123) && ('|' == 124) && ('}' == 125) && ('~' == 126)) +/* The character set is not based on ISO-646. */ +#error "gperf generated tables don't work with this execution character set. Please report a bug to ." +#endif + +#line 10 "scripts/kconfig/zconf.gperf" +struct kconf_id; + +static const struct kconf_id *kconf_id_lookup(register const char *str, register unsigned int len); +/* maximum key range = 71, duplicates = 0 */ + +#ifdef __GNUC__ +__inline +#else +#ifdef __cplusplus +inline +#endif +#endif +static unsigned int +kconf_id_hash (register const char *str, register unsigned int len) +{ + static const unsigned char asso_values[] = + { + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 5, 25, 25, + 0, 0, 0, 5, 0, 0, 73, 73, 5, 0, + 10, 5, 45, 73, 20, 20, 0, 15, 15, 73, + 20, 5, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73, 73, 73, 73, 73, + 73, 73, 73, 73, 73, 73 + }; + register int hval = len; + + switch (hval) + { + default: + hval += asso_values[(unsigned char)str[2]]; + /*FALLTHROUGH*/ + case 2: + case 1: + hval += asso_values[(unsigned char)str[0]]; + break; + } + return hval + asso_values[(unsigned char)str[len - 1]]; +} + +struct kconf_id_strings_t + { + char kconf_id_strings_str2[sizeof("if")]; + char kconf_id_strings_str3[sizeof("int")]; + char kconf_id_strings_str5[sizeof("endif")]; + char kconf_id_strings_str7[sizeof("default")]; + char kconf_id_strings_str8[sizeof("tristate")]; + char kconf_id_strings_str9[sizeof("endchoice")]; + char kconf_id_strings_str12[sizeof("def_tristate")]; + char kconf_id_strings_str13[sizeof("def_bool")]; + char kconf_id_strings_str14[sizeof("defconfig_list")]; + char kconf_id_strings_str17[sizeof("on")]; + char kconf_id_strings_str18[sizeof("optional")]; + char kconf_id_strings_str21[sizeof("option")]; + char kconf_id_strings_str22[sizeof("endmenu")]; + char kconf_id_strings_str23[sizeof("mainmenu")]; + char kconf_id_strings_str25[sizeof("menuconfig")]; + char kconf_id_strings_str27[sizeof("modules")]; + char kconf_id_strings_str28[sizeof("allnoconfig_y")]; + char kconf_id_strings_str29[sizeof("menu")]; + char kconf_id_strings_str31[sizeof("select")]; + char kconf_id_strings_str32[sizeof("comment")]; + char kconf_id_strings_str33[sizeof("env")]; + char kconf_id_strings_str35[sizeof("range")]; + char kconf_id_strings_str36[sizeof("choice")]; + char kconf_id_strings_str39[sizeof("bool")]; + char kconf_id_strings_str41[sizeof("source")]; + char kconf_id_strings_str42[sizeof("visible")]; + char kconf_id_strings_str43[sizeof("hex")]; + char kconf_id_strings_str46[sizeof("config")]; + char kconf_id_strings_str47[sizeof("boolean")]; + char kconf_id_strings_str51[sizeof("string")]; + char kconf_id_strings_str54[sizeof("help")]; + char kconf_id_strings_str56[sizeof("prompt")]; + char kconf_id_strings_str72[sizeof("depends")]; + }; +static const struct kconf_id_strings_t kconf_id_strings_contents = + { + "if", + "int", + "endif", + "default", + "tristate", + "endchoice", + "def_tristate", + "def_bool", + "defconfig_list", + "on", + "optional", + "option", + "endmenu", + "mainmenu", + "menuconfig", + "modules", + "allnoconfig_y", + "menu", + "select", + "comment", + "env", + "range", + "choice", + "bool", + "source", + "visible", + "hex", + "config", + "boolean", + "string", + "help", + "prompt", + "depends" + }; +#define kconf_id_strings ((const char *) &kconf_id_strings_contents) +#ifdef __GNUC__ +__inline +#if defined __GNUC_STDC_INLINE__ || defined __GNUC_GNU_INLINE__ +__attribute__ ((__gnu_inline__)) +#endif +#endif +const struct kconf_id * +kconf_id_lookup (register const char *str, register unsigned int len) +{ + enum + { + TOTAL_KEYWORDS = 33, + MIN_WORD_LENGTH = 2, + MAX_WORD_LENGTH = 14, + MIN_HASH_VALUE = 2, + MAX_HASH_VALUE = 72 + }; + + static const struct kconf_id wordlist[] = + { + {-1}, {-1}, +#line 25 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str2, T_IF, TF_COMMAND|TF_PARAM}, +#line 36 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str3, T_TYPE, TF_COMMAND, S_INT}, + {-1}, +#line 26 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str5, T_ENDIF, TF_COMMAND}, + {-1}, +#line 29 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str7, T_DEFAULT, TF_COMMAND, S_UNKNOWN}, +#line 31 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str8, T_TYPE, TF_COMMAND, S_TRISTATE}, +#line 20 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str9, T_ENDCHOICE, TF_COMMAND}, + {-1}, {-1}, +#line 32 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str12, T_DEFAULT, TF_COMMAND, S_TRISTATE}, +#line 35 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str13, T_DEFAULT, TF_COMMAND, S_BOOLEAN}, +#line 45 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str14, T_OPT_DEFCONFIG_LIST,TF_OPTION}, + {-1}, {-1}, +#line 43 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str17, T_ON, TF_PARAM}, +#line 28 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str18, T_OPTIONAL, TF_COMMAND}, + {-1}, {-1}, +#line 42 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str21, T_OPTION, TF_COMMAND}, +#line 17 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str22, T_ENDMENU, TF_COMMAND}, +#line 15 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str23, T_MAINMENU, TF_COMMAND}, + {-1}, +#line 23 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str25, T_MENUCONFIG, TF_COMMAND}, + {-1}, +#line 44 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str27, T_OPT_MODULES, TF_OPTION}, +#line 47 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str28, T_OPT_ALLNOCONFIG_Y,TF_OPTION}, +#line 16 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str29, T_MENU, TF_COMMAND}, + {-1}, +#line 39 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str31, T_SELECT, TF_COMMAND}, +#line 21 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str32, T_COMMENT, TF_COMMAND}, +#line 46 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str33, T_OPT_ENV, TF_OPTION}, + {-1}, +#line 40 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str35, T_RANGE, TF_COMMAND}, +#line 19 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str36, T_CHOICE, TF_COMMAND}, + {-1}, {-1}, +#line 33 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str39, T_TYPE, TF_COMMAND, S_BOOLEAN}, + {-1}, +#line 18 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str41, T_SOURCE, TF_COMMAND}, +#line 41 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str42, T_VISIBLE, TF_COMMAND}, +#line 37 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str43, T_TYPE, TF_COMMAND, S_HEX}, + {-1}, {-1}, +#line 22 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str46, T_CONFIG, TF_COMMAND}, +#line 34 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str47, T_TYPE, TF_COMMAND, S_BOOLEAN}, + {-1}, {-1}, {-1}, +#line 38 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str51, T_TYPE, TF_COMMAND, S_STRING}, + {-1}, {-1}, +#line 24 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str54, T_HELP, TF_COMMAND}, + {-1}, +#line 30 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str56, T_PROMPT, TF_COMMAND}, + {-1}, {-1}, {-1}, {-1}, {-1}, {-1}, {-1}, {-1}, {-1}, + {-1}, {-1}, {-1}, {-1}, {-1}, {-1}, +#line 27 "scripts/kconfig/zconf.gperf" + {(int)(long)&((struct kconf_id_strings_t *)0)->kconf_id_strings_str72, T_DEPENDS, TF_COMMAND} + }; + + if (len <= MAX_WORD_LENGTH && len >= MIN_WORD_LENGTH) + { + register int key = kconf_id_hash (str, len); + + if (key <= MAX_HASH_VALUE && key >= 0) + { + register int o = wordlist[key].name; + if (o >= 0) + { + register const char *s = o + kconf_id_strings; + + if (*str == *s && !strncmp (str + 1, s + 1, len - 1) && s[len] == '\0') + return &wordlist[key]; + } + } + } + return 0; +} +#line 48 "scripts/kconfig/zconf.gperf" + diff --git a/scripts/kconfig/zconf.l b/scripts/kconfig/zconf.l new file mode 100644 index 0000000000..6c62d93b4f --- /dev/null +++ b/scripts/kconfig/zconf.l @@ -0,0 +1,363 @@ +%option nostdinit noyywrap never-interactive full ecs +%option 8bit nodefault perf-report perf-report +%option noinput +%x COMMAND HELP STRING PARAM +%{ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include +#include + +#include "lkc.h" + +#define START_STRSIZE 16 + +static struct { + struct file *file; + int lineno; +} current_pos; + +static char *text; +static int text_size, text_asize; + +struct buffer { + struct buffer *parent; + YY_BUFFER_STATE state; +}; + +struct buffer *current_buf; + +static int last_ts, first_ts; + +static void zconf_endhelp(void); +static void zconf_endfile(void); + +static void new_string(void) +{ + text = xmalloc(START_STRSIZE); + text_asize = START_STRSIZE; + text_size = 0; + *text = 0; +} + +static void append_string(const char *str, int size) +{ + int new_size = text_size + size + 1; + if (new_size > text_asize) { + new_size += START_STRSIZE - 1; + new_size &= -START_STRSIZE; + text = realloc(text, new_size); + text_asize = new_size; + } + memcpy(text + text_size, str, size); + text_size += size; + text[text_size] = 0; +} + +static void alloc_string(const char *str, int size) +{ + text = xmalloc(size + 1); + memcpy(text, str, size); + text[size] = 0; +} +%} + +n [A-Za-z0-9_] + +%% + int str = 0; + int ts, i; + +[ \t]*#.*\n | +[ \t]*\n { + current_file->lineno++; + return T_EOL; +} +[ \t]*#.* + + +[ \t]+ { + BEGIN(COMMAND); +} + +. { + unput(yytext[0]); + BEGIN(COMMAND); +} + + +{ + {n}+ { + const struct kconf_id *id = kconf_id_lookup(yytext, yyleng); + BEGIN(PARAM); + current_pos.file = current_file; + current_pos.lineno = current_file->lineno; + if (id && id->flags & TF_COMMAND) { + zconflval.id = id; + return id->token; + } + alloc_string(yytext, yyleng); + zconflval.string = text; + return T_WORD; + } + . + \n { + BEGIN(INITIAL); + current_file->lineno++; + return T_EOL; + } +} + +{ + "&&" return T_AND; + "||" return T_OR; + "(" return T_OPEN_PAREN; + ")" return T_CLOSE_PAREN; + "!" return T_NOT; + "=" return T_EQUAL; + "!=" return T_UNEQUAL; + \"|\' { + str = yytext[0]; + new_string(); + BEGIN(STRING); + } + \n BEGIN(INITIAL); current_file->lineno++; return T_EOL; + --- /* ignore */ + ({n}|[-/.])+ { + const struct kconf_id *id = kconf_id_lookup(yytext, yyleng); + if (id && id->flags & TF_PARAM) { + zconflval.id = id; + return id->token; + } + alloc_string(yytext, yyleng); + zconflval.string = text; + return T_WORD; + } + #.* /* comment */ + \\\n current_file->lineno++; + . + <> { + BEGIN(INITIAL); + } +} + +{ + [^'"\\\n]+/\n { + append_string(yytext, yyleng); + zconflval.string = text; + return T_WORD_QUOTE; + } + [^'"\\\n]+ { + append_string(yytext, yyleng); + } + \\.?/\n { + append_string(yytext + 1, yyleng - 1); + zconflval.string = text; + return T_WORD_QUOTE; + } + \\.? { + append_string(yytext + 1, yyleng - 1); + } + \'|\" { + if (str == yytext[0]) { + BEGIN(PARAM); + zconflval.string = text; + return T_WORD_QUOTE; + } else + append_string(yytext, 1); + } + \n { + printf("%s:%d:warning: multi-line strings not supported\n", zconf_curname(), zconf_lineno()); + current_file->lineno++; + BEGIN(INITIAL); + return T_EOL; + } + <> { + BEGIN(INITIAL); + } +} + +{ + [ \t]+ { + ts = 0; + for (i = 0; i < yyleng; i++) { + if (yytext[i] == '\t') + ts = (ts & ~7) + 8; + else + ts++; + } + last_ts = ts; + if (first_ts) { + if (ts < first_ts) { + zconf_endhelp(); + return T_HELPTEXT; + } + ts -= first_ts; + while (ts > 8) { + append_string(" ", 8); + ts -= 8; + } + append_string(" ", ts); + } + } + [ \t]*\n/[^ \t\n] { + current_file->lineno++; + zconf_endhelp(); + return T_HELPTEXT; + } + [ \t]*\n { + current_file->lineno++; + append_string("\n", 1); + } + [^ \t\n].* { + while (yyleng) { + if ((yytext[yyleng-1] != ' ') && (yytext[yyleng-1] != '\t')) + break; + yyleng--; + } + append_string(yytext, yyleng); + if (!first_ts) + first_ts = last_ts; + } + <> { + zconf_endhelp(); + return T_HELPTEXT; + } +} + +<> { + if (current_file) { + zconf_endfile(); + return T_EOL; + } + fclose(yyin); + yyterminate(); +} + +%% +void zconf_starthelp(void) +{ + new_string(); + last_ts = first_ts = 0; + BEGIN(HELP); +} + +static void zconf_endhelp(void) +{ + zconflval.string = text; + BEGIN(INITIAL); +} + + +/* + * Try to open specified file with following names: + * ./name + * $(srctree)/name + * The latter is used when srctree is separate from objtree + * when compiling the kernel. + * Return NULL if file is not found. + */ +FILE *zconf_fopen(const char *name) +{ + char *env, fullname[PATH_MAX+1]; + FILE *f; + + f = fopen(name, "r"); + if (!f && name != NULL && name[0] != '/') { + env = getenv(SRCTREE); + if (env) { + sprintf(fullname, "%s/%s", env, name); + f = fopen(fullname, "r"); + } + } + return f; +} + +void zconf_initscan(const char *name) +{ + yyin = zconf_fopen(name); + if (!yyin) { + printf("can't find file %s\n", name); + exit(1); + } + + current_buf = xmalloc(sizeof(*current_buf)); + memset(current_buf, 0, sizeof(*current_buf)); + + current_file = file_lookup(name); + current_file->lineno = 1; +} + +void zconf_nextfile(const char *name) +{ + struct file *iter; + struct file *file = file_lookup(name); + struct buffer *buf = xmalloc(sizeof(*buf)); + memset(buf, 0, sizeof(*buf)); + + current_buf->state = YY_CURRENT_BUFFER; + yyin = zconf_fopen(file->name); + if (!yyin) { + printf("%s:%d: can't open file \"%s\"\n", + zconf_curname(), zconf_lineno(), file->name); + exit(1); + } + yy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE)); + buf->parent = current_buf; + current_buf = buf; + + for (iter = current_file->parent; iter; iter = iter->parent ) { + if (!strcmp(current_file->name,iter->name) ) { + printf("%s:%d: recursive inclusion detected. " + "Inclusion path:\n current file : '%s'\n", + zconf_curname(), zconf_lineno(), + zconf_curname()); + iter = current_file->parent; + while (iter && \ + strcmp(iter->name,current_file->name)) { + printf(" included from: '%s:%d'\n", + iter->name, iter->lineno-1); + iter = iter->parent; + } + if (iter) + printf(" included from: '%s:%d'\n", + iter->name, iter->lineno+1); + exit(1); + } + } + file->lineno = 1; + file->parent = current_file; + current_file = file; +} + +static void zconf_endfile(void) +{ + struct buffer *parent; + + current_file = current_file->parent; + + parent = current_buf->parent; + if (parent) { + fclose(yyin); + yy_delete_buffer(YY_CURRENT_BUFFER); + yy_switch_to_buffer(parent->state); + } + free(current_buf); + current_buf = parent; +} + +int zconf_lineno(void) +{ + return current_pos.lineno; +} + +const char *zconf_curname(void) +{ + return current_pos.file ? current_pos.file->name : ""; +} diff --git a/scripts/kconfig/zconf.lex.c_shipped b/scripts/kconfig/zconf.lex.c_shipped new file mode 100644 index 0000000000..349a7f2431 --- /dev/null +++ b/scripts/kconfig/zconf.lex.c_shipped @@ -0,0 +1,2420 @@ + +#line 3 "scripts/kconfig/zconf.lex.c_shipped" + +#define YY_INT_ALIGNED short int + +/* A lexical scanner generated by flex */ + +#define yy_create_buffer zconf_create_buffer +#define yy_delete_buffer zconf_delete_buffer +#define yy_flex_debug zconf_flex_debug +#define yy_init_buffer zconf_init_buffer +#define yy_flush_buffer zconf_flush_buffer +#define yy_load_buffer_state zconf_load_buffer_state +#define yy_switch_to_buffer zconf_switch_to_buffer +#define yyin zconfin +#define yyleng zconfleng +#define yylex zconflex +#define yylineno zconflineno +#define yyout zconfout +#define yyrestart zconfrestart +#define yytext zconftext +#define yywrap zconfwrap +#define yyalloc zconfalloc +#define yyrealloc zconfrealloc +#define yyfree zconffree + +#define FLEX_SCANNER +#define YY_FLEX_MAJOR_VERSION 2 +#define YY_FLEX_MINOR_VERSION 5 +#define YY_FLEX_SUBMINOR_VERSION 35 +#if YY_FLEX_SUBMINOR_VERSION > 0 +#define FLEX_BETA +#endif + +/* First, we deal with platform-specific or compiler-specific issues. */ + +/* begin standard C headers. */ +#include +#include +#include +#include + +/* end standard C headers. */ + +/* flex integer type definitions */ + +#ifndef FLEXINT_H +#define FLEXINT_H + +/* C99 systems have . Non-C99 systems may or may not. */ + +#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L + +/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h, + * if you want the limit (max/min) macros for int types. + */ +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS 1 +#endif + +#include +typedef int8_t flex_int8_t; +typedef uint8_t flex_uint8_t; +typedef int16_t flex_int16_t; +typedef uint16_t flex_uint16_t; +typedef int32_t flex_int32_t; +typedef uint32_t flex_uint32_t; +#else +typedef signed char flex_int8_t; +typedef short int flex_int16_t; +typedef int flex_int32_t; +typedef unsigned char flex_uint8_t; +typedef unsigned short int flex_uint16_t; +typedef unsigned int flex_uint32_t; +#endif /* ! C99 */ + +/* Limits of integral types. */ +#ifndef INT8_MIN +#define INT8_MIN (-128) +#endif +#ifndef INT16_MIN +#define INT16_MIN (-32767-1) +#endif +#ifndef INT32_MIN +#define INT32_MIN (-2147483647-1) +#endif +#ifndef INT8_MAX +#define INT8_MAX (127) +#endif +#ifndef INT16_MAX +#define INT16_MAX (32767) +#endif +#ifndef INT32_MAX +#define INT32_MAX (2147483647) +#endif +#ifndef UINT8_MAX +#define UINT8_MAX (255U) +#endif +#ifndef UINT16_MAX +#define UINT16_MAX (65535U) +#endif +#ifndef UINT32_MAX +#define UINT32_MAX (4294967295U) +#endif + +#endif /* ! FLEXINT_H */ + +#ifdef __cplusplus + +/* The "const" storage-class-modifier is valid. */ +#define YY_USE_CONST + +#else /* ! __cplusplus */ + +/* C99 requires __STDC__ to be defined as 1. */ +#if defined (__STDC__) + +#define YY_USE_CONST + +#endif /* defined (__STDC__) */ +#endif /* ! __cplusplus */ + +#ifdef YY_USE_CONST +#define yyconst const +#else +#define yyconst +#endif + +/* Returned upon end-of-file. */ +#define YY_NULL 0 + +/* Promotes a possibly negative, possibly signed char to an unsigned + * integer for use as an array index. If the signed char is negative, + * we want to instead treat it as an 8-bit unsigned char, hence the + * double cast. + */ +#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c) + +/* Enter a start condition. This macro really ought to take a parameter, + * but we do it the disgusting crufty way forced on us by the ()-less + * definition of BEGIN. + */ +#define BEGIN (yy_start) = 1 + 2 * + +/* Translate the current start state into a value that can be later handed + * to BEGIN to return to the state. The YYSTATE alias is for lex + * compatibility. + */ +#define YY_START (((yy_start) - 1) / 2) +#define YYSTATE YY_START + +/* Action number for EOF rule of a given start state. */ +#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1) + +/* Special action meaning "start processing a new file". */ +#define YY_NEW_FILE zconfrestart(zconfin ) + +#define YY_END_OF_BUFFER_CHAR 0 + +/* Size of default input buffer. */ +#ifndef YY_BUF_SIZE +#define YY_BUF_SIZE 16384 +#endif + +/* The state buf must be large enough to hold one state per character in the main buffer. + */ +#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type)) + +#ifndef YY_TYPEDEF_YY_BUFFER_STATE +#define YY_TYPEDEF_YY_BUFFER_STATE +typedef struct yy_buffer_state *YY_BUFFER_STATE; +#endif + +extern int zconfleng; + +extern FILE *zconfin, *zconfout; + +#define EOB_ACT_CONTINUE_SCAN 0 +#define EOB_ACT_END_OF_FILE 1 +#define EOB_ACT_LAST_MATCH 2 + + #define YY_LESS_LINENO(n) + +/* Return all but the first "n" matched characters back to the input stream. */ +#define yyless(n) \ + do \ + { \ + /* Undo effects of setting up zconftext. */ \ + int yyless_macro_arg = (n); \ + YY_LESS_LINENO(yyless_macro_arg);\ + *yy_cp = (yy_hold_char); \ + YY_RESTORE_YY_MORE_OFFSET \ + (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \ + YY_DO_BEFORE_ACTION; /* set up zconftext again */ \ + } \ + while ( 0 ) + +#define unput(c) yyunput( c, (yytext_ptr) ) + +#ifndef YY_TYPEDEF_YY_SIZE_T +#define YY_TYPEDEF_YY_SIZE_T +typedef size_t yy_size_t; +#endif + +#ifndef YY_STRUCT_YY_BUFFER_STATE +#define YY_STRUCT_YY_BUFFER_STATE +struct yy_buffer_state + { + FILE *yy_input_file; + + char *yy_ch_buf; /* input buffer */ + char *yy_buf_pos; /* current position in input buffer */ + + /* Size of input buffer in bytes, not including room for EOB + * characters. + */ + yy_size_t yy_buf_size; + + /* Number of characters read into yy_ch_buf, not including EOB + * characters. + */ + int yy_n_chars; + + /* Whether we "own" the buffer - i.e., we know we created it, + * and can realloc() it to grow it, and should free() it to + * delete it. + */ + int yy_is_our_buffer; + + /* Whether this is an "interactive" input source; if so, and + * if we're using stdio for input, then we want to use getc() + * instead of fread(), to make sure we stop fetching input after + * each newline. + */ + int yy_is_interactive; + + /* Whether we're considered to be at the beginning of a line. + * If so, '^' rules will be active on the next match, otherwise + * not. + */ + int yy_at_bol; + + int yy_bs_lineno; /**< The line count. */ + int yy_bs_column; /**< The column count. */ + + /* Whether to try to fill the input buffer when we reach the + * end of it. + */ + int yy_fill_buffer; + + int yy_buffer_status; + +#define YY_BUFFER_NEW 0 +#define YY_BUFFER_NORMAL 1 + /* When an EOF's been seen but there's still some text to process + * then we mark the buffer as YY_EOF_PENDING, to indicate that we + * shouldn't try reading from the input source any more. We might + * still have a bunch of tokens to match, though, because of + * possible backing-up. + * + * When we actually see the EOF, we change the status to "new" + * (via zconfrestart()), so that the user can continue scanning by + * just pointing zconfin at a new input file. + */ +#define YY_BUFFER_EOF_PENDING 2 + + }; +#endif /* !YY_STRUCT_YY_BUFFER_STATE */ + +/* Stack of input buffers. */ +static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */ +static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */ +static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */ + +/* We provide macros for accessing buffer states in case in the + * future we want to put the buffer states in a more general + * "scanner state". + * + * Returns the top of the stack, or NULL. + */ +#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \ + ? (yy_buffer_stack)[(yy_buffer_stack_top)] \ + : NULL) + +/* Same as previous macro, but useful when we know that the buffer stack is not + * NULL or when we need an lvalue. For internal use only. + */ +#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)] + +/* yy_hold_char holds the character lost when zconftext is formed. */ +static char yy_hold_char; +static int yy_n_chars; /* number of characters read into yy_ch_buf */ +int zconfleng; + +/* Points to current character in buffer. */ +static char *yy_c_buf_p = (char *) 0; +static int yy_init = 0; /* whether we need to initialize */ +static int yy_start = 0; /* start state number */ + +/* Flag which is used to allow zconfwrap()'s to do buffer switches + * instead of setting up a fresh zconfin. A bit of a hack ... + */ +static int yy_did_buffer_switch_on_eof; + +void zconfrestart (FILE *input_file ); +void zconf_switch_to_buffer (YY_BUFFER_STATE new_buffer ); +YY_BUFFER_STATE zconf_create_buffer (FILE *file,int size ); +void zconf_delete_buffer (YY_BUFFER_STATE b ); +void zconf_flush_buffer (YY_BUFFER_STATE b ); +void zconfpush_buffer_state (YY_BUFFER_STATE new_buffer ); +void zconfpop_buffer_state (void ); + +static void zconfensure_buffer_stack (void ); +static void zconf_load_buffer_state (void ); +static void zconf_init_buffer (YY_BUFFER_STATE b,FILE *file ); + +#define YY_FLUSH_BUFFER zconf_flush_buffer(YY_CURRENT_BUFFER ) + +YY_BUFFER_STATE zconf_scan_buffer (char *base,yy_size_t size ); +YY_BUFFER_STATE zconf_scan_string (yyconst char *yy_str ); +YY_BUFFER_STATE zconf_scan_bytes (yyconst char *bytes,int len ); + +void *zconfalloc (yy_size_t ); +void *zconfrealloc (void *,yy_size_t ); +void zconffree (void * ); + +#define yy_new_buffer zconf_create_buffer + +#define yy_set_interactive(is_interactive) \ + { \ + if ( ! YY_CURRENT_BUFFER ){ \ + zconfensure_buffer_stack (); \ + YY_CURRENT_BUFFER_LVALUE = \ + zconf_create_buffer(zconfin,YY_BUF_SIZE ); \ + } \ + YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \ + } + +#define yy_set_bol(at_bol) \ + { \ + if ( ! YY_CURRENT_BUFFER ){\ + zconfensure_buffer_stack (); \ + YY_CURRENT_BUFFER_LVALUE = \ + zconf_create_buffer(zconfin,YY_BUF_SIZE ); \ + } \ + YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \ + } + +#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol) + +/* Begin user sect3 */ + +#define zconfwrap(n) 1 +#define YY_SKIP_YYWRAP + +typedef unsigned char YY_CHAR; + +FILE *zconfin = (FILE *) 0, *zconfout = (FILE *) 0; + +typedef int yy_state_type; + +extern int zconflineno; + +int zconflineno = 1; + +extern char *zconftext; +#define yytext_ptr zconftext +static yyconst flex_int16_t yy_nxt[][17] = + { + { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0 + }, + + { + 11, 12, 13, 14, 12, 12, 15, 12, 12, 12, + 12, 12, 12, 12, 12, 12, 12 + }, + + { + 11, 12, 13, 14, 12, 12, 15, 12, 12, 12, + 12, 12, 12, 12, 12, 12, 12 + }, + + { + 11, 16, 16, 17, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 18, 16, 16, 16 + }, + + { + 11, 16, 16, 17, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 18, 16, 16, 16 + + }, + + { + 11, 19, 20, 21, 19, 19, 19, 19, 19, 19, + 19, 19, 19, 19, 19, 19, 19 + }, + + { + 11, 19, 20, 21, 19, 19, 19, 19, 19, 19, + 19, 19, 19, 19, 19, 19, 19 + }, + + { + 11, 22, 22, 23, 22, 24, 22, 22, 24, 22, + 22, 22, 22, 22, 22, 25, 22 + }, + + { + 11, 22, 22, 23, 22, 24, 22, 22, 24, 22, + 22, 22, 22, 22, 22, 25, 22 + }, + + { + 11, 26, 26, 27, 28, 29, 30, 31, 29, 32, + 33, 34, 35, 35, 36, 37, 38 + + }, + + { + 11, 26, 26, 27, 28, 29, 30, 31, 29, 32, + 33, 34, 35, 35, 36, 37, 38 + }, + + { + -11, -11, -11, -11, -11, -11, -11, -11, -11, -11, + -11, -11, -11, -11, -11, -11, -11 + }, + + { + 11, -12, -12, -12, -12, -12, -12, -12, -12, -12, + -12, -12, -12, -12, -12, -12, -12 + }, + + { + 11, -13, 39, 40, -13, -13, 41, -13, -13, -13, + -13, -13, -13, -13, -13, -13, -13 + }, + + { + 11, -14, -14, -14, -14, -14, -14, -14, -14, -14, + -14, -14, -14, -14, -14, -14, -14 + + }, + + { + 11, 42, 42, 43, 42, 42, 42, 42, 42, 42, + 42, 42, 42, 42, 42, 42, 42 + }, + + { + 11, -16, -16, -16, -16, -16, -16, -16, -16, -16, + -16, -16, -16, -16, -16, -16, -16 + }, + + { + 11, -17, -17, -17, -17, -17, -17, -17, -17, -17, + -17, -17, -17, -17, -17, -17, -17 + }, + + { + 11, -18, -18, -18, -18, -18, -18, -18, -18, -18, + -18, -18, -18, 44, -18, -18, -18 + }, + + { + 11, 45, 45, -19, 45, 45, 45, 45, 45, 45, + 45, 45, 45, 45, 45, 45, 45 + + }, + + { + 11, -20, 46, 47, -20, -20, -20, -20, -20, -20, + -20, -20, -20, -20, -20, -20, -20 + }, + + { + 11, 48, -21, -21, 48, 48, 48, 48, 48, 48, + 48, 48, 48, 48, 48, 48, 48 + }, + + { + 11, 49, 49, 50, 49, -22, 49, 49, -22, 49, + 49, 49, 49, 49, 49, -22, 49 + }, + + { + 11, -23, -23, -23, -23, -23, -23, -23, -23, -23, + -23, -23, -23, -23, -23, -23, -23 + }, + + { + 11, -24, -24, -24, -24, -24, -24, -24, -24, -24, + -24, -24, -24, -24, -24, -24, -24 + + }, + + { + 11, 51, 51, 52, 51, 51, 51, 51, 51, 51, + 51, 51, 51, 51, 51, 51, 51 + }, + + { + 11, -26, -26, -26, -26, -26, -26, -26, -26, -26, + -26, -26, -26, -26, -26, -26, -26 + }, + + { + 11, -27, -27, -27, -27, -27, -27, -27, -27, -27, + -27, -27, -27, -27, -27, -27, -27 + }, + + { + 11, -28, -28, -28, -28, -28, -28, -28, -28, -28, + -28, -28, -28, -28, 53, -28, -28 + }, + + { + 11, -29, -29, -29, -29, -29, -29, -29, -29, -29, + -29, -29, -29, -29, -29, -29, -29 + + }, + + { + 11, 54, 54, -30, 54, 54, 54, 54, 54, 54, + 54, 54, 54, 54, 54, 54, 54 + }, + + { + 11, -31, -31, -31, -31, -31, -31, 55, -31, -31, + -31, -31, -31, -31, -31, -31, -31 + }, + + { + 11, -32, -32, -32, -32, -32, -32, -32, -32, -32, + -32, -32, -32, -32, -32, -32, -32 + }, + + { + 11, -33, -33, -33, -33, -33, -33, -33, -33, -33, + -33, -33, -33, -33, -33, -33, -33 + }, + + { + 11, -34, -34, -34, -34, -34, -34, -34, -34, -34, + -34, 56, 57, 57, -34, -34, -34 + + }, + + { + 11, -35, -35, -35, -35, -35, -35, -35, -35, -35, + -35, 57, 57, 57, -35, -35, -35 + }, + + { + 11, -36, -36, -36, -36, -36, -36, -36, -36, -36, + -36, -36, -36, -36, -36, -36, -36 + }, + + { + 11, -37, -37, 58, -37, -37, -37, -37, -37, -37, + -37, -37, -37, -37, -37, -37, -37 + }, + + { + 11, -38, -38, -38, -38, -38, -38, -38, -38, -38, + -38, -38, -38, -38, -38, -38, 59 + }, + + { + 11, -39, 39, 40, -39, -39, 41, -39, -39, -39, + -39, -39, -39, -39, -39, -39, -39 + + }, + + { + 11, -40, -40, -40, -40, -40, -40, -40, -40, -40, + -40, -40, -40, -40, -40, -40, -40 + }, + + { + 11, 42, 42, 43, 42, 42, 42, 42, 42, 42, + 42, 42, 42, 42, 42, 42, 42 + }, + + { + 11, 42, 42, 43, 42, 42, 42, 42, 42, 42, + 42, 42, 42, 42, 42, 42, 42 + }, + + { + 11, -43, -43, -43, -43, -43, -43, -43, -43, -43, + -43, -43, -43, -43, -43, -43, -43 + }, + + { + 11, -44, -44, -44, -44, -44, -44, -44, -44, -44, + -44, -44, -44, 44, -44, -44, -44 + + }, + + { + 11, 45, 45, -45, 45, 45, 45, 45, 45, 45, + 45, 45, 45, 45, 45, 45, 45 + }, + + { + 11, -46, 46, 47, -46, -46, -46, -46, -46, -46, + -46, -46, -46, -46, -46, -46, -46 + }, + + { + 11, 48, -47, -47, 48, 48, 48, 48, 48, 48, + 48, 48, 48, 48, 48, 48, 48 + }, + + { + 11, -48, -48, -48, -48, -48, -48, -48, -48, -48, + -48, -48, -48, -48, -48, -48, -48 + }, + + { + 11, 49, 49, 50, 49, -49, 49, 49, -49, 49, + 49, 49, 49, 49, 49, -49, 49 + + }, + + { + 11, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50 + }, + + { + 11, -51, -51, 52, -51, -51, -51, -51, -51, -51, + -51, -51, -51, -51, -51, -51, -51 + }, + + { + 11, -52, -52, -52, -52, -52, -52, -52, -52, -52, + -52, -52, -52, -52, -52, -52, -52 + }, + + { + 11, -53, -53, -53, -53, -53, -53, -53, -53, -53, + -53, -53, -53, -53, -53, -53, -53 + }, + + { + 11, 54, 54, -54, 54, 54, 54, 54, 54, 54, + 54, 54, 54, 54, 54, 54, 54 + + }, + + { + 11, -55, -55, -55, -55, -55, -55, -55, -55, -55, + -55, -55, -55, -55, -55, -55, -55 + }, + + { + 11, -56, -56, -56, -56, -56, -56, -56, -56, -56, + -56, 60, 57, 57, -56, -56, -56 + }, + + { + 11, -57, -57, -57, -57, -57, -57, -57, -57, -57, + -57, 57, 57, 57, -57, -57, -57 + }, + + { + 11, -58, -58, -58, -58, -58, -58, -58, -58, -58, + -58, -58, -58, -58, -58, -58, -58 + }, + + { + 11, -59, -59, -59, -59, -59, -59, -59, -59, -59, + -59, -59, -59, -59, -59, -59, -59 + + }, + + { + 11, -60, -60, -60, -60, -60, -60, -60, -60, -60, + -60, 57, 57, 57, -60, -60, -60 + }, + + } ; + +static yy_state_type yy_get_previous_state (void ); +static yy_state_type yy_try_NUL_trans (yy_state_type current_state ); +static int yy_get_next_buffer (void ); +static void yy_fatal_error (yyconst char msg[] ); + +/* Done after the current pattern has been matched and before the + * corresponding action - sets up zconftext. + */ +#define YY_DO_BEFORE_ACTION \ + (yytext_ptr) = yy_bp; \ + zconfleng = (size_t) (yy_cp - yy_bp); \ + (yy_hold_char) = *yy_cp; \ + *yy_cp = '\0'; \ + (yy_c_buf_p) = yy_cp; + +#define YY_NUM_RULES 33 +#define YY_END_OF_BUFFER 34 +/* This struct is not used in this scanner, + but its presence is necessary. */ +struct yy_trans_info + { + flex_int32_t yy_verify; + flex_int32_t yy_nxt; + }; +static yyconst flex_int16_t yy_accept[61] = + { 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 34, 5, 4, 2, 3, 7, 8, 6, 32, 29, + 31, 24, 28, 27, 26, 22, 17, 13, 16, 20, + 22, 11, 12, 19, 19, 14, 22, 22, 4, 2, + 3, 3, 1, 6, 32, 29, 31, 30, 24, 23, + 26, 25, 15, 20, 9, 19, 19, 21, 10, 18 + } ; + +static yyconst flex_int32_t yy_ec[256] = + { 0, + 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 2, 4, 5, 6, 1, 1, 7, 8, 9, + 10, 1, 1, 1, 11, 12, 12, 13, 13, 13, + 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, + 14, 1, 1, 1, 13, 13, 13, 13, 13, 13, + 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, + 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, + 1, 15, 1, 1, 13, 1, 13, 13, 13, 13, + + 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, + 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, + 13, 13, 1, 16, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1 + } ; + +extern int zconf_flex_debug; +int zconf_flex_debug = 0; + +/* The intent behind this definition is that it'll catch + * any uses of REJECT which flex missed. + */ +#define REJECT reject_used_but_not_detected +#define yymore() yymore_used_but_not_detected +#define YY_MORE_ADJ 0 +#define YY_RESTORE_YY_MORE_OFFSET +char *zconftext; +#define YY_NO_INPUT 1 + +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include +#include + +#include "lkc.h" + +#define START_STRSIZE 16 + +static struct { + struct file *file; + int lineno; +} current_pos; + +static char *text; +static int text_size, text_asize; + +struct buffer { + struct buffer *parent; + YY_BUFFER_STATE state; +}; + +struct buffer *current_buf; + +static int last_ts, first_ts; + +static void zconf_endhelp(void); +static void zconf_endfile(void); + +static void new_string(void) +{ + text = xmalloc(START_STRSIZE); + text_asize = START_STRSIZE; + text_size = 0; + *text = 0; +} + +static void append_string(const char *str, int size) +{ + int new_size = text_size + size + 1; + if (new_size > text_asize) { + new_size += START_STRSIZE - 1; + new_size &= -START_STRSIZE; + text = realloc(text, new_size); + text_asize = new_size; + } + memcpy(text + text_size, str, size); + text_size += size; + text[text_size] = 0; +} + +static void alloc_string(const char *str, int size) +{ + text = xmalloc(size + 1); + memcpy(text, str, size); + text[size] = 0; +} + +#define INITIAL 0 +#define COMMAND 1 +#define HELP 2 +#define STRING 3 +#define PARAM 4 + +#ifndef YY_NO_UNISTD_H +/* Special case for "unistd.h", since it is non-ANSI. We include it way + * down here because we want the user's section 1 to have been scanned first. + * The user has a chance to override it with an option. + */ +#include +#endif + +#ifndef YY_EXTRA_TYPE +#define YY_EXTRA_TYPE void * +#endif + +static int yy_init_globals (void ); + +/* Accessor methods to globals. + These are made visible to non-reentrant scanners for convenience. */ + +int zconflex_destroy (void ); + +int zconfget_debug (void ); + +void zconfset_debug (int debug_flag ); + +YY_EXTRA_TYPE zconfget_extra (void ); + +void zconfset_extra (YY_EXTRA_TYPE user_defined ); + +FILE *zconfget_in (void ); + +void zconfset_in (FILE * in_str ); + +FILE *zconfget_out (void ); + +void zconfset_out (FILE * out_str ); + +int zconfget_leng (void ); + +char *zconfget_text (void ); + +int zconfget_lineno (void ); + +void zconfset_lineno (int line_number ); + +/* Macros after this point can all be overridden by user definitions in + * section 1. + */ + +#ifndef YY_SKIP_YYWRAP +#ifdef __cplusplus +extern "C" int zconfwrap (void ); +#else +extern int zconfwrap (void ); +#endif +#endif + + static void yyunput (int c,char *buf_ptr ); + +#ifndef yytext_ptr +static void yy_flex_strncpy (char *,yyconst char *,int ); +#endif + +#ifdef YY_NEED_STRLEN +static int yy_flex_strlen (yyconst char * ); +#endif + +#ifndef YY_NO_INPUT + +#ifdef __cplusplus +static int yyinput (void ); +#else +static int input (void ); +#endif + +#endif + +/* Amount of stuff to slurp up with each read. */ +#ifndef YY_READ_BUF_SIZE +#define YY_READ_BUF_SIZE 8192 +#endif + +/* Copy whatever the last rule matched to the standard output. */ +#ifndef ECHO +/* This used to be an fputs(), but since the string might contain NUL's, + * we now use fwrite(). + */ +#define ECHO do { if (fwrite( zconftext, zconfleng, 1, zconfout )) {} } while (0) +#endif + +/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, + * is returned in "result". + */ +#ifndef YY_INPUT +#define YY_INPUT(buf,result,max_size) \ + errno=0; \ + while ( (result = read( fileno(zconfin), (char *) buf, max_size )) < 0 ) \ + { \ + if( errno != EINTR) \ + { \ + YY_FATAL_ERROR( "input in flex scanner failed" ); \ + break; \ + } \ + errno=0; \ + clearerr(zconfin); \ + }\ +\ + +#endif + +/* No semi-colon after return; correct usage is to write "yyterminate();" - + * we don't want an extra ';' after the "return" because that will cause + * some compilers to complain about unreachable statements. + */ +#ifndef yyterminate +#define yyterminate() return YY_NULL +#endif + +/* Number of entries by which start-condition stack grows. */ +#ifndef YY_START_STACK_INCR +#define YY_START_STACK_INCR 25 +#endif + +/* Report a fatal error. */ +#ifndef YY_FATAL_ERROR +#define YY_FATAL_ERROR(msg) yy_fatal_error( msg ) +#endif + +/* end tables serialization structures and prototypes */ + +/* Default declaration of generated scanner - a define so the user can + * easily add parameters. + */ +#ifndef YY_DECL +#define YY_DECL_IS_OURS 1 + +extern int zconflex (void); + +#define YY_DECL int zconflex (void) +#endif /* !YY_DECL */ + +/* Code executed at the beginning of each rule, after zconftext and zconfleng + * have been set up. + */ +#ifndef YY_USER_ACTION +#define YY_USER_ACTION +#endif + +/* Code executed at the end of each rule. */ +#ifndef YY_BREAK +#define YY_BREAK break; +#endif + +#define YY_RULE_SETUP \ + YY_USER_ACTION + +/** The main scanner function which does all the work. + */ +YY_DECL +{ + register yy_state_type yy_current_state; + register char *yy_cp, *yy_bp; + register int yy_act; + + int str = 0; + int ts, i; + + if ( !(yy_init) ) + { + (yy_init) = 1; + +#ifdef YY_USER_INIT + YY_USER_INIT; +#endif + + if ( ! (yy_start) ) + (yy_start) = 1; /* first start state */ + + if ( ! zconfin ) + zconfin = stdin; + + if ( ! zconfout ) + zconfout = stdout; + + if ( ! YY_CURRENT_BUFFER ) { + zconfensure_buffer_stack (); + YY_CURRENT_BUFFER_LVALUE = + zconf_create_buffer(zconfin,YY_BUF_SIZE ); + } + + zconf_load_buffer_state( ); + } + + while ( 1 ) /* loops until end-of-file is reached */ + { + yy_cp = (yy_c_buf_p); + + /* Support of zconftext. */ + *yy_cp = (yy_hold_char); + + /* yy_bp points to the position in yy_ch_buf of the start of + * the current run. + */ + yy_bp = yy_cp; + + yy_current_state = (yy_start); +yy_match: + while ( (yy_current_state = yy_nxt[yy_current_state][ yy_ec[YY_SC_TO_UI(*yy_cp)] ]) > 0 ) + ++yy_cp; + + yy_current_state = -yy_current_state; + +yy_find_action: + yy_act = yy_accept[yy_current_state]; + + YY_DO_BEFORE_ACTION; + +do_action: /* This label is used only to access EOF actions. */ + + switch ( yy_act ) + { /* beginning of action switch */ +case 1: +/* rule 1 can match eol */ +case 2: +/* rule 2 can match eol */ +YY_RULE_SETUP +{ + current_file->lineno++; + return T_EOL; +} + YY_BREAK +case 3: +YY_RULE_SETUP + + YY_BREAK +case 4: +YY_RULE_SETUP +{ + BEGIN(COMMAND); +} + YY_BREAK +case 5: +YY_RULE_SETUP +{ + unput(zconftext[0]); + BEGIN(COMMAND); +} + YY_BREAK + +case 6: +YY_RULE_SETUP +{ + const struct kconf_id *id = kconf_id_lookup(zconftext, zconfleng); + BEGIN(PARAM); + current_pos.file = current_file; + current_pos.lineno = current_file->lineno; + if (id && id->flags & TF_COMMAND) { + zconflval.id = id; + return id->token; + } + alloc_string(zconftext, zconfleng); + zconflval.string = text; + return T_WORD; + } + YY_BREAK +case 7: +YY_RULE_SETUP + + YY_BREAK +case 8: +/* rule 8 can match eol */ +YY_RULE_SETUP +{ + BEGIN(INITIAL); + current_file->lineno++; + return T_EOL; + } + YY_BREAK + +case 9: +YY_RULE_SETUP +return T_AND; + YY_BREAK +case 10: +YY_RULE_SETUP +return T_OR; + YY_BREAK +case 11: +YY_RULE_SETUP +return T_OPEN_PAREN; + YY_BREAK +case 12: +YY_RULE_SETUP +return T_CLOSE_PAREN; + YY_BREAK +case 13: +YY_RULE_SETUP +return T_NOT; + YY_BREAK +case 14: +YY_RULE_SETUP +return T_EQUAL; + YY_BREAK +case 15: +YY_RULE_SETUP +return T_UNEQUAL; + YY_BREAK +case 16: +YY_RULE_SETUP +{ + str = zconftext[0]; + new_string(); + BEGIN(STRING); + } + YY_BREAK +case 17: +/* rule 17 can match eol */ +YY_RULE_SETUP +BEGIN(INITIAL); current_file->lineno++; return T_EOL; + YY_BREAK +case 18: +YY_RULE_SETUP +/* ignore */ + YY_BREAK +case 19: +YY_RULE_SETUP +{ + const struct kconf_id *id = kconf_id_lookup(zconftext, zconfleng); + if (id && id->flags & TF_PARAM) { + zconflval.id = id; + return id->token; + } + alloc_string(zconftext, zconfleng); + zconflval.string = text; + return T_WORD; + } + YY_BREAK +case 20: +YY_RULE_SETUP +/* comment */ + YY_BREAK +case 21: +/* rule 21 can match eol */ +YY_RULE_SETUP +current_file->lineno++; + YY_BREAK +case 22: +YY_RULE_SETUP + + YY_BREAK +case YY_STATE_EOF(PARAM): +{ + BEGIN(INITIAL); + } + YY_BREAK + +case 23: +/* rule 23 can match eol */ +*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */ +(yy_c_buf_p) = yy_cp -= 1; +YY_DO_BEFORE_ACTION; /* set up zconftext again */ +YY_RULE_SETUP +{ + append_string(zconftext, zconfleng); + zconflval.string = text; + return T_WORD_QUOTE; + } + YY_BREAK +case 24: +YY_RULE_SETUP +{ + append_string(zconftext, zconfleng); + } + YY_BREAK +case 25: +/* rule 25 can match eol */ +*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */ +(yy_c_buf_p) = yy_cp -= 1; +YY_DO_BEFORE_ACTION; /* set up zconftext again */ +YY_RULE_SETUP +{ + append_string(zconftext + 1, zconfleng - 1); + zconflval.string = text; + return T_WORD_QUOTE; + } + YY_BREAK +case 26: +YY_RULE_SETUP +{ + append_string(zconftext + 1, zconfleng - 1); + } + YY_BREAK +case 27: +YY_RULE_SETUP +{ + if (str == zconftext[0]) { + BEGIN(PARAM); + zconflval.string = text; + return T_WORD_QUOTE; + } else + append_string(zconftext, 1); + } + YY_BREAK +case 28: +/* rule 28 can match eol */ +YY_RULE_SETUP +{ + printf("%s:%d:warning: multi-line strings not supported\n", zconf_curname(), zconf_lineno()); + current_file->lineno++; + BEGIN(INITIAL); + return T_EOL; + } + YY_BREAK +case YY_STATE_EOF(STRING): +{ + BEGIN(INITIAL); + } + YY_BREAK + +case 29: +YY_RULE_SETUP +{ + ts = 0; + for (i = 0; i < zconfleng; i++) { + if (zconftext[i] == '\t') + ts = (ts & ~7) + 8; + else + ts++; + } + last_ts = ts; + if (first_ts) { + if (ts < first_ts) { + zconf_endhelp(); + return T_HELPTEXT; + } + ts -= first_ts; + while (ts > 8) { + append_string(" ", 8); + ts -= 8; + } + append_string(" ", ts); + } + } + YY_BREAK +case 30: +/* rule 30 can match eol */ +*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */ +(yy_c_buf_p) = yy_cp -= 1; +YY_DO_BEFORE_ACTION; /* set up zconftext again */ +YY_RULE_SETUP +{ + current_file->lineno++; + zconf_endhelp(); + return T_HELPTEXT; + } + YY_BREAK +case 31: +/* rule 31 can match eol */ +YY_RULE_SETUP +{ + current_file->lineno++; + append_string("\n", 1); + } + YY_BREAK +case 32: +YY_RULE_SETUP +{ + while (zconfleng) { + if ((zconftext[zconfleng-1] != ' ') && (zconftext[zconfleng-1] != '\t')) + break; + zconfleng--; + } + append_string(zconftext, zconfleng); + if (!first_ts) + first_ts = last_ts; + } + YY_BREAK +case YY_STATE_EOF(HELP): +{ + zconf_endhelp(); + return T_HELPTEXT; + } + YY_BREAK + +case YY_STATE_EOF(INITIAL): +case YY_STATE_EOF(COMMAND): +{ + if (current_file) { + zconf_endfile(); + return T_EOL; + } + fclose(zconfin); + yyterminate(); +} + YY_BREAK +case 33: +YY_RULE_SETUP +YY_FATAL_ERROR( "flex scanner jammed" ); + YY_BREAK + + case YY_END_OF_BUFFER: + { + /* Amount of text matched not including the EOB char. */ + int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1; + + /* Undo the effects of YY_DO_BEFORE_ACTION. */ + *yy_cp = (yy_hold_char); + YY_RESTORE_YY_MORE_OFFSET + + if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW ) + { + /* We're scanning a new file or input source. It's + * possible that this happened because the user + * just pointed zconfin at a new source and called + * zconflex(). If so, then we have to assure + * consistency between YY_CURRENT_BUFFER and our + * globals. Here is the right place to do so, because + * this is the first action (other than possibly a + * back-up) that will match for the new input source. + */ + (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; + YY_CURRENT_BUFFER_LVALUE->yy_input_file = zconfin; + YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL; + } + + /* Note that here we test for yy_c_buf_p "<=" to the position + * of the first EOB in the buffer, since yy_c_buf_p will + * already have been incremented past the NUL character + * (since all states make transitions on EOB to the + * end-of-buffer state). Contrast this with the test + * in input(). + */ + if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) + { /* This was really a NUL. */ + yy_state_type yy_next_state; + + (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text; + + yy_current_state = yy_get_previous_state( ); + + /* Okay, we're now positioned to make the NUL + * transition. We couldn't have + * yy_get_previous_state() go ahead and do it + * for us because it doesn't know how to deal + * with the possibility of jamming (and we don't + * want to build jamming into it because then it + * will run more slowly). + */ + + yy_next_state = yy_try_NUL_trans( yy_current_state ); + + yy_bp = (yytext_ptr) + YY_MORE_ADJ; + + if ( yy_next_state ) + { + /* Consume the NUL. */ + yy_cp = ++(yy_c_buf_p); + yy_current_state = yy_next_state; + goto yy_match; + } + + else + { + yy_cp = (yy_c_buf_p); + goto yy_find_action; + } + } + + else switch ( yy_get_next_buffer( ) ) + { + case EOB_ACT_END_OF_FILE: + { + (yy_did_buffer_switch_on_eof) = 0; + + if ( zconfwrap( ) ) + { + /* Note: because we've taken care in + * yy_get_next_buffer() to have set up + * zconftext, we can now set up + * yy_c_buf_p so that if some total + * hoser (like flex itself) wants to + * call the scanner after we return the + * YY_NULL, it'll still work - another + * YY_NULL will get returned. + */ + (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ; + + yy_act = YY_STATE_EOF(YY_START); + goto do_action; + } + + else + { + if ( ! (yy_did_buffer_switch_on_eof) ) + YY_NEW_FILE; + } + break; + } + + case EOB_ACT_CONTINUE_SCAN: + (yy_c_buf_p) = + (yytext_ptr) + yy_amount_of_matched_text; + + yy_current_state = yy_get_previous_state( ); + + yy_cp = (yy_c_buf_p); + yy_bp = (yytext_ptr) + YY_MORE_ADJ; + goto yy_match; + + case EOB_ACT_LAST_MATCH: + (yy_c_buf_p) = + &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)]; + + yy_current_state = yy_get_previous_state( ); + + yy_cp = (yy_c_buf_p); + yy_bp = (yytext_ptr) + YY_MORE_ADJ; + goto yy_find_action; + } + break; + } + + default: + YY_FATAL_ERROR( + "fatal flex scanner internal error--no action found" ); + } /* end of action switch */ + } /* end of scanning one token */ +} /* end of zconflex */ + +/* yy_get_next_buffer - try to read in a new buffer + * + * Returns a code representing an action: + * EOB_ACT_LAST_MATCH - + * EOB_ACT_CONTINUE_SCAN - continue scanning from current position + * EOB_ACT_END_OF_FILE - end of file + */ +static int yy_get_next_buffer (void) +{ + register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; + register char *source = (yytext_ptr); + register int number_to_move, i; + int ret_val; + + if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) + YY_FATAL_ERROR( + "fatal flex scanner internal error--end of buffer missed" ); + + if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 ) + { /* Don't try to fill the buffer, so this is an EOF. */ + if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 ) + { + /* We matched a single character, the EOB, so + * treat this as a final EOF. + */ + return EOB_ACT_END_OF_FILE; + } + + else + { + /* We matched some text prior to the EOB, first + * process it. + */ + return EOB_ACT_LAST_MATCH; + } + } + + /* Try to read more data. */ + + /* First move last chars to start of buffer. */ + number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1; + + for ( i = 0; i < number_to_move; ++i ) + *(dest++) = *(source++); + + if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING ) + /* don't do the read, it's not guaranteed to return an EOF, + * just force an EOF + */ + YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0; + + else + { + int num_to_read = + YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; + + while ( num_to_read <= 0 ) + { /* Not enough room in the buffer - grow it. */ + + /* just a shorter name for the current buffer */ + YY_BUFFER_STATE b = YY_CURRENT_BUFFER; + + int yy_c_buf_p_offset = + (int) ((yy_c_buf_p) - b->yy_ch_buf); + + if ( b->yy_is_our_buffer ) + { + int new_size = b->yy_buf_size * 2; + + if ( new_size <= 0 ) + b->yy_buf_size += b->yy_buf_size / 8; + else + b->yy_buf_size *= 2; + + b->yy_ch_buf = (char *) + /* Include room in for 2 EOB chars. */ + zconfrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 ); + } + else + /* Can't grow it, we don't own it. */ + b->yy_ch_buf = 0; + + if ( ! b->yy_ch_buf ) + YY_FATAL_ERROR( + "fatal error - scanner input buffer overflow" ); + + (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset]; + + num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - + number_to_move - 1; + + } + + if ( num_to_read > YY_READ_BUF_SIZE ) + num_to_read = YY_READ_BUF_SIZE; + + /* Read in more data. */ + YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]), + (yy_n_chars), (size_t) num_to_read ); + + YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); + } + + if ( (yy_n_chars) == 0 ) + { + if ( number_to_move == YY_MORE_ADJ ) + { + ret_val = EOB_ACT_END_OF_FILE; + zconfrestart(zconfin ); + } + + else + { + ret_val = EOB_ACT_LAST_MATCH; + YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = + YY_BUFFER_EOF_PENDING; + } + } + + else + ret_val = EOB_ACT_CONTINUE_SCAN; + + if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { + /* Extend the array by 50%, plus the number we really need. */ + yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); + YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) zconfrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size ); + if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) + YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); + } + + (yy_n_chars) += number_to_move; + YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR; + YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR; + + (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0]; + + return ret_val; +} + +/* yy_get_previous_state - get the state just before the EOB char was reached */ + + static yy_state_type yy_get_previous_state (void) +{ + register yy_state_type yy_current_state; + register char *yy_cp; + + yy_current_state = (yy_start); + + for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) + { + yy_current_state = yy_nxt[yy_current_state][(*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1)]; + } + + return yy_current_state; +} + +/* yy_try_NUL_trans - try to make a transition on the NUL character + * + * synopsis + * next_state = yy_try_NUL_trans( current_state ); + */ + static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state ) +{ + register int yy_is_jam; + + yy_current_state = yy_nxt[yy_current_state][1]; + yy_is_jam = (yy_current_state <= 0); + + return yy_is_jam ? 0 : yy_current_state; +} + + static void yyunput (int c, register char * yy_bp ) +{ + register char *yy_cp; + + yy_cp = (yy_c_buf_p); + + /* undo effects of setting up zconftext */ + *yy_cp = (yy_hold_char); + + if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) + { /* need to shift things up to make room */ + /* +2 for EOB chars. */ + register int number_to_move = (yy_n_chars) + 2; + register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[ + YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2]; + register char *source = + &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]; + + while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) + *--dest = *--source; + + yy_cp += (int) (dest - source); + yy_bp += (int) (dest - source); + YY_CURRENT_BUFFER_LVALUE->yy_n_chars = + (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size; + + if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) + YY_FATAL_ERROR( "flex scanner push-back overflow" ); + } + + *--yy_cp = (char) c; + + (yytext_ptr) = yy_bp; + (yy_hold_char) = *yy_cp; + (yy_c_buf_p) = yy_cp; +} + +#ifndef YY_NO_INPUT +#ifdef __cplusplus + static int yyinput (void) +#else + static int input (void) +#endif + +{ + int c; + + *(yy_c_buf_p) = (yy_hold_char); + + if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR ) + { + /* yy_c_buf_p now points to the character we want to return. + * If this occurs *before* the EOB characters, then it's a + * valid NUL; if not, then we've hit the end of the buffer. + */ + if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) + /* This was really a NUL. */ + *(yy_c_buf_p) = '\0'; + + else + { /* need more input */ + int offset = (yy_c_buf_p) - (yytext_ptr); + ++(yy_c_buf_p); + + switch ( yy_get_next_buffer( ) ) + { + case EOB_ACT_LAST_MATCH: + /* This happens because yy_g_n_b() + * sees that we've accumulated a + * token and flags that we need to + * try matching the token before + * proceeding. But for input(), + * there's no matching to consider. + * So convert the EOB_ACT_LAST_MATCH + * to EOB_ACT_END_OF_FILE. + */ + + /* Reset buffer status. */ + zconfrestart(zconfin ); + + /*FALLTHROUGH*/ + + case EOB_ACT_END_OF_FILE: + { + if ( zconfwrap( ) ) + return EOF; + + if ( ! (yy_did_buffer_switch_on_eof) ) + YY_NEW_FILE; +#ifdef __cplusplus + return yyinput(); +#else + return input(); +#endif + } + + case EOB_ACT_CONTINUE_SCAN: + (yy_c_buf_p) = (yytext_ptr) + offset; + break; + } + } + } + + c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */ + *(yy_c_buf_p) = '\0'; /* preserve zconftext */ + (yy_hold_char) = *++(yy_c_buf_p); + + return c; +} +#endif /* ifndef YY_NO_INPUT */ + +/** Immediately switch to a different input stream. + * @param input_file A readable stream. + * + * @note This function does not reset the start condition to @c INITIAL . + */ + void zconfrestart (FILE * input_file ) +{ + + if ( ! YY_CURRENT_BUFFER ){ + zconfensure_buffer_stack (); + YY_CURRENT_BUFFER_LVALUE = + zconf_create_buffer(zconfin,YY_BUF_SIZE ); + } + + zconf_init_buffer(YY_CURRENT_BUFFER,input_file ); + zconf_load_buffer_state( ); +} + +/** Switch to a different input buffer. + * @param new_buffer The new input buffer. + * + */ + void zconf_switch_to_buffer (YY_BUFFER_STATE new_buffer ) +{ + + /* TODO. We should be able to replace this entire function body + * with + * zconfpop_buffer_state(); + * zconfpush_buffer_state(new_buffer); + */ + zconfensure_buffer_stack (); + if ( YY_CURRENT_BUFFER == new_buffer ) + return; + + if ( YY_CURRENT_BUFFER ) + { + /* Flush out information for old buffer. */ + *(yy_c_buf_p) = (yy_hold_char); + YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); + YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); + } + + YY_CURRENT_BUFFER_LVALUE = new_buffer; + zconf_load_buffer_state( ); + + /* We don't actually know whether we did this switch during + * EOF (zconfwrap()) processing, but the only time this flag + * is looked at is after zconfwrap() is called, so it's safe + * to go ahead and always set it. + */ + (yy_did_buffer_switch_on_eof) = 1; +} + +static void zconf_load_buffer_state (void) +{ + (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; + (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos; + zconfin = YY_CURRENT_BUFFER_LVALUE->yy_input_file; + (yy_hold_char) = *(yy_c_buf_p); +} + +/** Allocate and initialize an input buffer state. + * @param file A readable stream. + * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE. + * + * @return the allocated buffer state. + */ + YY_BUFFER_STATE zconf_create_buffer (FILE * file, int size ) +{ + YY_BUFFER_STATE b; + + b = (YY_BUFFER_STATE) zconfalloc(sizeof( struct yy_buffer_state ) ); + if ( ! b ) + YY_FATAL_ERROR( "out of dynamic memory in zconf_create_buffer()" ); + + b->yy_buf_size = size; + + /* yy_ch_buf has to be 2 characters longer than the size given because + * we need to put in 2 end-of-buffer characters. + */ + b->yy_ch_buf = (char *) zconfalloc(b->yy_buf_size + 2 ); + if ( ! b->yy_ch_buf ) + YY_FATAL_ERROR( "out of dynamic memory in zconf_create_buffer()" ); + + b->yy_is_our_buffer = 1; + + zconf_init_buffer(b,file ); + + return b; +} + +/** Destroy the buffer. + * @param b a buffer created with zconf_create_buffer() + * + */ + void zconf_delete_buffer (YY_BUFFER_STATE b ) +{ + + if ( ! b ) + return; + + if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */ + YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0; + + if ( b->yy_is_our_buffer ) + zconffree((void *) b->yy_ch_buf ); + + zconffree((void *) b ); +} + +/* Initializes or reinitializes a buffer. + * This function is sometimes called more than once on the same buffer, + * such as during a zconfrestart() or at EOF. + */ + static void zconf_init_buffer (YY_BUFFER_STATE b, FILE * file ) + +{ + int oerrno = errno; + + zconf_flush_buffer(b ); + + b->yy_input_file = file; + b->yy_fill_buffer = 1; + + /* If b is the current buffer, then zconf_init_buffer was _probably_ + * called from zconfrestart() or through yy_get_next_buffer. + * In that case, we don't want to reset the lineno or column. + */ + if (b != YY_CURRENT_BUFFER){ + b->yy_bs_lineno = 1; + b->yy_bs_column = 0; + } + + b->yy_is_interactive = 0; + + errno = oerrno; +} + +/** Discard all buffered characters. On the next scan, YY_INPUT will be called. + * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER. + * + */ + void zconf_flush_buffer (YY_BUFFER_STATE b ) +{ + if ( ! b ) + return; + + b->yy_n_chars = 0; + + /* We always need two end-of-buffer characters. The first causes + * a transition to the end-of-buffer state. The second causes + * a jam in that state. + */ + b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR; + b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR; + + b->yy_buf_pos = &b->yy_ch_buf[0]; + + b->yy_at_bol = 1; + b->yy_buffer_status = YY_BUFFER_NEW; + + if ( b == YY_CURRENT_BUFFER ) + zconf_load_buffer_state( ); +} + +/** Pushes the new state onto the stack. The new state becomes + * the current state. This function will allocate the stack + * if necessary. + * @param new_buffer The new state. + * + */ +void zconfpush_buffer_state (YY_BUFFER_STATE new_buffer ) +{ + if (new_buffer == NULL) + return; + + zconfensure_buffer_stack(); + + /* This block is copied from zconf_switch_to_buffer. */ + if ( YY_CURRENT_BUFFER ) + { + /* Flush out information for old buffer. */ + *(yy_c_buf_p) = (yy_hold_char); + YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); + YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); + } + + /* Only push if top exists. Otherwise, replace top. */ + if (YY_CURRENT_BUFFER) + (yy_buffer_stack_top)++; + YY_CURRENT_BUFFER_LVALUE = new_buffer; + + /* copied from zconf_switch_to_buffer. */ + zconf_load_buffer_state( ); + (yy_did_buffer_switch_on_eof) = 1; +} + +/** Removes and deletes the top of the stack, if present. + * The next element becomes the new top. + * + */ +void zconfpop_buffer_state (void) +{ + if (!YY_CURRENT_BUFFER) + return; + + zconf_delete_buffer(YY_CURRENT_BUFFER ); + YY_CURRENT_BUFFER_LVALUE = NULL; + if ((yy_buffer_stack_top) > 0) + --(yy_buffer_stack_top); + + if (YY_CURRENT_BUFFER) { + zconf_load_buffer_state( ); + (yy_did_buffer_switch_on_eof) = 1; + } +} + +/* Allocates the stack if it does not exist. + * Guarantees space for at least one push. + */ +static void zconfensure_buffer_stack (void) +{ + int num_to_alloc; + + if (!(yy_buffer_stack)) { + + /* First allocation is just for 2 elements, since we don't know if this + * scanner will even need a stack. We use 2 instead of 1 to avoid an + * immediate realloc on the next call. + */ + num_to_alloc = 1; + (yy_buffer_stack) = (struct yy_buffer_state**)zconfalloc + (num_to_alloc * sizeof(struct yy_buffer_state*) + ); + if ( ! (yy_buffer_stack) ) + YY_FATAL_ERROR( "out of dynamic memory in zconfensure_buffer_stack()" ); + + memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*)); + + (yy_buffer_stack_max) = num_to_alloc; + (yy_buffer_stack_top) = 0; + return; + } + + if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){ + + /* Increase the buffer to prepare for a possible push. */ + int grow_size = 8 /* arbitrary grow size */; + + num_to_alloc = (yy_buffer_stack_max) + grow_size; + (yy_buffer_stack) = (struct yy_buffer_state**)zconfrealloc + ((yy_buffer_stack), + num_to_alloc * sizeof(struct yy_buffer_state*) + ); + if ( ! (yy_buffer_stack) ) + YY_FATAL_ERROR( "out of dynamic memory in zconfensure_buffer_stack()" ); + + /* zero only the new slots.*/ + memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*)); + (yy_buffer_stack_max) = num_to_alloc; + } +} + +/** Setup the input buffer state to scan directly from a user-specified character buffer. + * @param base the character buffer + * @param size the size in bytes of the character buffer + * + * @return the newly allocated buffer state object. + */ +YY_BUFFER_STATE zconf_scan_buffer (char * base, yy_size_t size ) +{ + YY_BUFFER_STATE b; + + if ( size < 2 || + base[size-2] != YY_END_OF_BUFFER_CHAR || + base[size-1] != YY_END_OF_BUFFER_CHAR ) + /* They forgot to leave room for the EOB's. */ + return 0; + + b = (YY_BUFFER_STATE) zconfalloc(sizeof( struct yy_buffer_state ) ); + if ( ! b ) + YY_FATAL_ERROR( "out of dynamic memory in zconf_scan_buffer()" ); + + b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */ + b->yy_buf_pos = b->yy_ch_buf = base; + b->yy_is_our_buffer = 0; + b->yy_input_file = 0; + b->yy_n_chars = b->yy_buf_size; + b->yy_is_interactive = 0; + b->yy_at_bol = 1; + b->yy_fill_buffer = 0; + b->yy_buffer_status = YY_BUFFER_NEW; + + zconf_switch_to_buffer(b ); + + return b; +} + +/** Setup the input buffer state to scan a string. The next call to zconflex() will + * scan from a @e copy of @a str. + * @param yystr a NUL-terminated string to scan + * + * @return the newly allocated buffer state object. + * @note If you want to scan bytes that may contain NUL values, then use + * zconf_scan_bytes() instead. + */ +YY_BUFFER_STATE zconf_scan_string (yyconst char * yystr ) +{ + + return zconf_scan_bytes(yystr,strlen(yystr) ); +} + +/** Setup the input buffer state to scan the given bytes. The next call to zconflex() will + * scan from a @e copy of @a bytes. + * @param bytes the byte buffer to scan + * @param len the number of bytes in the buffer pointed to by @a bytes. + * + * @return the newly allocated buffer state object. + */ +YY_BUFFER_STATE zconf_scan_bytes (yyconst char * yybytes, int _yybytes_len ) +{ + YY_BUFFER_STATE b; + char *buf; + yy_size_t n; + int i; + + /* Get memory for full buffer, including space for trailing EOB's. */ + n = _yybytes_len + 2; + buf = (char *) zconfalloc(n ); + if ( ! buf ) + YY_FATAL_ERROR( "out of dynamic memory in zconf_scan_bytes()" ); + + for ( i = 0; i < _yybytes_len; ++i ) + buf[i] = yybytes[i]; + + buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR; + + b = zconf_scan_buffer(buf,n ); + if ( ! b ) + YY_FATAL_ERROR( "bad buffer in zconf_scan_bytes()" ); + + /* It's okay to grow etc. this buffer, and we should throw it + * away when we're done. + */ + b->yy_is_our_buffer = 1; + + return b; +} + +#ifndef YY_EXIT_FAILURE +#define YY_EXIT_FAILURE 2 +#endif + +static void yy_fatal_error (yyconst char* msg ) +{ + (void) fprintf( stderr, "%s\n", msg ); + exit( YY_EXIT_FAILURE ); +} + +/* Redefine yyless() so it works in section 3 code. */ + +#undef yyless +#define yyless(n) \ + do \ + { \ + /* Undo effects of setting up zconftext. */ \ + int yyless_macro_arg = (n); \ + YY_LESS_LINENO(yyless_macro_arg);\ + zconftext[zconfleng] = (yy_hold_char); \ + (yy_c_buf_p) = zconftext + yyless_macro_arg; \ + (yy_hold_char) = *(yy_c_buf_p); \ + *(yy_c_buf_p) = '\0'; \ + zconfleng = yyless_macro_arg; \ + } \ + while ( 0 ) + +/* Accessor methods (get/set functions) to struct members. */ + +/** Get the current line number. + * + */ +int zconfget_lineno (void) +{ + + return zconflineno; +} + +/** Get the input stream. + * + */ +FILE *zconfget_in (void) +{ + return zconfin; +} + +/** Get the output stream. + * + */ +FILE *zconfget_out (void) +{ + return zconfout; +} + +/** Get the length of the current token. + * + */ +int zconfget_leng (void) +{ + return zconfleng; +} + +/** Get the current token. + * + */ + +char *zconfget_text (void) +{ + return zconftext; +} + +/** Set the current line number. + * @param line_number + * + */ +void zconfset_lineno (int line_number ) +{ + + zconflineno = line_number; +} + +/** Set the input stream. This does not discard the current + * input buffer. + * @param in_str A readable stream. + * + * @see zconf_switch_to_buffer + */ +void zconfset_in (FILE * in_str ) +{ + zconfin = in_str ; +} + +void zconfset_out (FILE * out_str ) +{ + zconfout = out_str ; +} + +int zconfget_debug (void) +{ + return zconf_flex_debug; +} + +void zconfset_debug (int bdebug ) +{ + zconf_flex_debug = bdebug ; +} + +static int yy_init_globals (void) +{ + /* Initialization is the same as for the non-reentrant scanner. + * This function is called from zconflex_destroy(), so don't allocate here. + */ + + (yy_buffer_stack) = 0; + (yy_buffer_stack_top) = 0; + (yy_buffer_stack_max) = 0; + (yy_c_buf_p) = (char *) 0; + (yy_init) = 0; + (yy_start) = 0; + +/* Defined in main.c */ +#ifdef YY_STDINIT + zconfin = stdin; + zconfout = stdout; +#else + zconfin = (FILE *) 0; + zconfout = (FILE *) 0; +#endif + + /* For future reference: Set errno on error, since we are called by + * zconflex_init() + */ + return 0; +} + +/* zconflex_destroy is for both reentrant and non-reentrant scanners. */ +int zconflex_destroy (void) +{ + + /* Pop the buffer stack, destroying each element. */ + while(YY_CURRENT_BUFFER){ + zconf_delete_buffer(YY_CURRENT_BUFFER ); + YY_CURRENT_BUFFER_LVALUE = NULL; + zconfpop_buffer_state(); + } + + /* Destroy the stack itself. */ + zconffree((yy_buffer_stack) ); + (yy_buffer_stack) = NULL; + + /* Reset the globals. This is important in a non-reentrant scanner so the next time + * zconflex() is called, initialization will occur. */ + yy_init_globals( ); + + return 0; +} + +/* + * Internal utility routines. + */ + +#ifndef yytext_ptr +static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) +{ + register int i; + for ( i = 0; i < n; ++i ) + s1[i] = s2[i]; +} +#endif + +#ifdef YY_NEED_STRLEN +static int yy_flex_strlen (yyconst char * s ) +{ + register int n; + for ( n = 0; s[n]; ++n ) + ; + + return n; +} +#endif + +void *zconfalloc (yy_size_t size ) +{ + return (void *) malloc( size ); +} + +void *zconfrealloc (void * ptr, yy_size_t size ) +{ + /* The cast to (char *) in the following accommodates both + * implementations that use char* generic pointers, and those + * that use void* generic pointers. It works with the latter + * because both ANSI C and C++ allow castless assignment from + * any pointer type to void*, and deal with argument conversions + * as though doing an assignment. + */ + return (void *) realloc( (char *) ptr, size ); +} + +void zconffree (void * ptr ) +{ + free( (char *) ptr ); /* see zconfrealloc() for (char *) cast */ +} + +#define YYTABLES_NAME "yytables" + +void zconf_starthelp(void) +{ + new_string(); + last_ts = first_ts = 0; + BEGIN(HELP); +} + +static void zconf_endhelp(void) +{ + zconflval.string = text; + BEGIN(INITIAL); +} + +/* + * Try to open specified file with following names: + * ./name + * $(srctree)/name + * The latter is used when srctree is separate from objtree + * when compiling the kernel. + * Return NULL if file is not found. + */ +FILE *zconf_fopen(const char *name) +{ + char *env, fullname[PATH_MAX+1]; + FILE *f; + + f = fopen(name, "r"); + if (!f && name != NULL && name[0] != '/') { + env = getenv(SRCTREE); + if (env) { + sprintf(fullname, "%s/%s", env, name); + f = fopen(fullname, "r"); + } + } + return f; +} + +void zconf_initscan(const char *name) +{ + zconfin = zconf_fopen(name); + if (!zconfin) { + printf("can't find file %s\n", name); + exit(1); + } + + current_buf = xmalloc(sizeof(*current_buf)); + memset(current_buf, 0, sizeof(*current_buf)); + + current_file = file_lookup(name); + current_file->lineno = 1; +} + +void zconf_nextfile(const char *name) +{ + struct file *iter; + struct file *file = file_lookup(name); + struct buffer *buf = xmalloc(sizeof(*buf)); + memset(buf, 0, sizeof(*buf)); + + current_buf->state = YY_CURRENT_BUFFER; + zconfin = zconf_fopen(file->name); + if (!zconfin) { + printf("%s:%d: can't open file \"%s\"\n", + zconf_curname(), zconf_lineno(), file->name); + exit(1); + } + zconf_switch_to_buffer(zconf_create_buffer(zconfin,YY_BUF_SIZE)); + buf->parent = current_buf; + current_buf = buf; + + for (iter = current_file->parent; iter; iter = iter->parent ) { + if (!strcmp(current_file->name,iter->name) ) { + printf("%s:%d: recursive inclusion detected. " + "Inclusion path:\n current file : '%s'\n", + zconf_curname(), zconf_lineno(), + zconf_curname()); + iter = current_file->parent; + while (iter && \ + strcmp(iter->name,current_file->name)) { + printf(" included from: '%s:%d'\n", + iter->name, iter->lineno-1); + iter = iter->parent; + } + if (iter) + printf(" included from: '%s:%d'\n", + iter->name, iter->lineno+1); + exit(1); + } + } + file->lineno = 1; + file->parent = current_file; + current_file = file; +} + +static void zconf_endfile(void) +{ + struct buffer *parent; + + current_file = current_file->parent; + + parent = current_buf->parent; + if (parent) { + fclose(zconfin); + zconf_delete_buffer(YY_CURRENT_BUFFER); + zconf_switch_to_buffer(parent->state); + } + free(current_buf); + current_buf = parent; +} + +int zconf_lineno(void) +{ + return current_pos.lineno; +} + +const char *zconf_curname(void) +{ + return current_pos.file ? current_pos.file->name : ""; +} + diff --git a/scripts/kconfig/zconf.tab.c_shipped b/scripts/kconfig/zconf.tab.c_shipped new file mode 100644 index 0000000000..de5e84ed3f --- /dev/null +++ b/scripts/kconfig/zconf.tab.c_shipped @@ -0,0 +1,2538 @@ +/* A Bison parser, made by GNU Bison 2.5. */ + +/* Bison implementation for Yacc-like parsers in C + + Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc. + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* As a special exception, you may create a larger work that contains + part or all of the Bison parser skeleton and distribute that work + under terms of your choice, so long as that work isn't itself a + parser generator using the skeleton or a modified version thereof + as a parser skeleton. Alternatively, if you modify or redistribute + the parser skeleton itself, you may (at your option) remove this + special exception, which will cause the skeleton and the resulting + Bison output files to be licensed under the GNU General Public + License without this special exception. + + This special exception was added by the Free Software Foundation in + version 2.2 of Bison. */ + +/* C LALR(1) parser skeleton written by Richard Stallman, by + simplifying the original so-called "semantic" parser. */ + +/* All symbols defined below should begin with yy or YY, to avoid + infringing on user name space. This should be done even for local + variables, as they might otherwise be expanded by user macros. + There are some unavoidable exceptions within include files to + define necessary library symbols; they are noted "INFRINGES ON + USER NAME SPACE" below. */ + +/* Identify Bison output. */ +#define YYBISON 1 + +/* Bison version. */ +#define YYBISON_VERSION "2.5" + +/* Skeleton name. */ +#define YYSKELETON_NAME "yacc.c" + +/* Pure parsers. */ +#define YYPURE 0 + +/* Push parsers. */ +#define YYPUSH 0 + +/* Pull parsers. */ +#define YYPULL 1 + +/* Using locations. */ +#define YYLSP_NEEDED 0 + +/* Substitute the variable and function names. */ +#define yyparse zconfparse +#define yylex zconflex +#define yyerror zconferror +#define yylval zconflval +#define yychar zconfchar +#define yydebug zconfdebug +#define yynerrs zconfnerrs + + +/* Copy the first part of user declarations. */ + + +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include +#include +#include + +#include "lkc.h" + +#define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt) + +#define PRINTD 0x0001 +#define DEBUG_PARSE 0x0002 + +int cdebug = PRINTD; + +extern int zconflex(void); +static void zconfprint(const char *err, ...); +static void zconf_error(const char *err, ...); +static void zconferror(const char *err); +static bool zconf_endtoken(const struct kconf_id *id, int starttoken, int endtoken); + +struct symbol *symbol_hash[SYMBOL_HASHSIZE]; + +static struct menu *current_menu, *current_entry; + + + + +/* Enabling traces. */ +#ifndef YYDEBUG +# define YYDEBUG 1 +#endif + +/* Enabling verbose error messages. */ +#ifdef YYERROR_VERBOSE +# undef YYERROR_VERBOSE +# define YYERROR_VERBOSE 1 +#else +# define YYERROR_VERBOSE 0 +#endif + +/* Enabling the token table. */ +#ifndef YYTOKEN_TABLE +# define YYTOKEN_TABLE 0 +#endif + + +/* Tokens. */ +#ifndef YYTOKENTYPE +# define YYTOKENTYPE + /* Put the tokens into the symbol table, so that GDB and other debuggers + know about them. */ + enum yytokentype { + T_MAINMENU = 258, + T_MENU = 259, + T_ENDMENU = 260, + T_SOURCE = 261, + T_CHOICE = 262, + T_ENDCHOICE = 263, + T_COMMENT = 264, + T_CONFIG = 265, + T_MENUCONFIG = 266, + T_HELP = 267, + T_HELPTEXT = 268, + T_IF = 269, + T_ENDIF = 270, + T_DEPENDS = 271, + T_OPTIONAL = 272, + T_PROMPT = 273, + T_TYPE = 274, + T_DEFAULT = 275, + T_SELECT = 276, + T_RANGE = 277, + T_VISIBLE = 278, + T_OPTION = 279, + T_ON = 280, + T_WORD = 281, + T_WORD_QUOTE = 282, + T_UNEQUAL = 283, + T_CLOSE_PAREN = 284, + T_OPEN_PAREN = 285, + T_EOL = 286, + T_OR = 287, + T_AND = 288, + T_EQUAL = 289, + T_NOT = 290 + }; +#endif + + + +#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED +typedef union YYSTYPE +{ + + + char *string; + struct file *file; + struct symbol *symbol; + struct expr *expr; + struct menu *menu; + const struct kconf_id *id; + + + +} YYSTYPE; +# define YYSTYPE_IS_TRIVIAL 1 +# define yystype YYSTYPE /* obsolescent; will be withdrawn */ +# define YYSTYPE_IS_DECLARED 1 +#endif + + +/* Copy the second part of user declarations. */ + + +/* Include zconf.hash.c here so it can see the token constants. */ +#include "zconf.hash.c" + + + +#ifdef short +# undef short +#endif + +#ifdef YYTYPE_UINT8 +typedef YYTYPE_UINT8 yytype_uint8; +#else +typedef unsigned char yytype_uint8; +#endif + +#ifdef YYTYPE_INT8 +typedef YYTYPE_INT8 yytype_int8; +#elif (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +typedef signed char yytype_int8; +#else +typedef short int yytype_int8; +#endif + +#ifdef YYTYPE_UINT16 +typedef YYTYPE_UINT16 yytype_uint16; +#else +typedef unsigned short int yytype_uint16; +#endif + +#ifdef YYTYPE_INT16 +typedef YYTYPE_INT16 yytype_int16; +#else +typedef short int yytype_int16; +#endif + +#ifndef YYSIZE_T +# ifdef __SIZE_TYPE__ +# define YYSIZE_T __SIZE_TYPE__ +# elif defined size_t +# define YYSIZE_T size_t +# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +# include /* INFRINGES ON USER NAME SPACE */ +# define YYSIZE_T size_t +# else +# define YYSIZE_T unsigned int +# endif +#endif + +#define YYSIZE_MAXIMUM ((YYSIZE_T) -1) + +#ifndef YY_ +# if defined YYENABLE_NLS && YYENABLE_NLS +# if ENABLE_NLS +# include /* INFRINGES ON USER NAME SPACE */ +# define YY_(msgid) dgettext ("bison-runtime", msgid) +# endif +# endif +# ifndef YY_ +# define YY_(msgid) msgid +# endif +#endif + +/* Suppress unused-variable warnings by "using" E. */ +#if ! defined lint || defined __GNUC__ +# define YYUSE(e) ((void) (e)) +#else +# define YYUSE(e) /* empty */ +#endif + +/* Identity function, used to suppress warnings about constant conditions. */ +#ifndef lint +# define YYID(n) (n) +#else +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +static int +YYID (int yyi) +#else +static int +YYID (yyi) + int yyi; +#endif +{ + return yyi; +} +#endif + +#if ! defined yyoverflow || YYERROR_VERBOSE + +/* The parser invokes alloca or malloc; define the necessary symbols. */ + +# ifdef YYSTACK_USE_ALLOCA +# if YYSTACK_USE_ALLOCA +# ifdef __GNUC__ +# define YYSTACK_ALLOC __builtin_alloca +# elif defined __BUILTIN_VA_ARG_INCR +# include /* INFRINGES ON USER NAME SPACE */ +# elif defined _AIX +# define YYSTACK_ALLOC __alloca +# elif defined _MSC_VER +# include /* INFRINGES ON USER NAME SPACE */ +# define alloca _alloca +# else +# define YYSTACK_ALLOC alloca +# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +# include /* INFRINGES ON USER NAME SPACE */ +# ifndef EXIT_SUCCESS +# define EXIT_SUCCESS 0 +# endif +# endif +# endif +# endif +# endif + +# ifdef YYSTACK_ALLOC + /* Pacify GCC's `empty if-body' warning. */ +# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0)) +# ifndef YYSTACK_ALLOC_MAXIMUM + /* The OS might guarantee only one guard page at the bottom of the stack, + and a page size can be as small as 4096 bytes. So we cannot safely + invoke alloca (N) if N exceeds 4096. Use a slightly smaller number + to allow for a few compiler-allocated temporary stack slots. */ +# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */ +# endif +# else +# define YYSTACK_ALLOC YYMALLOC +# define YYSTACK_FREE YYFREE +# ifndef YYSTACK_ALLOC_MAXIMUM +# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM +# endif +# if (defined __cplusplus && ! defined EXIT_SUCCESS \ + && ! ((defined YYMALLOC || defined malloc) \ + && (defined YYFREE || defined free))) +# include /* INFRINGES ON USER NAME SPACE */ +# ifndef EXIT_SUCCESS +# define EXIT_SUCCESS 0 +# endif +# endif +# ifndef YYMALLOC +# define YYMALLOC malloc +# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ +# endif +# endif +# ifndef YYFREE +# define YYFREE free +# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +void free (void *); /* INFRINGES ON USER NAME SPACE */ +# endif +# endif +# endif +#endif /* ! defined yyoverflow || YYERROR_VERBOSE */ + + +#if (! defined yyoverflow \ + && (! defined __cplusplus \ + || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) + +/* A type that is properly aligned for any stack member. */ +union yyalloc +{ + yytype_int16 yyss_alloc; + YYSTYPE yyvs_alloc; +}; + +/* The size of the maximum gap between one aligned stack and the next. */ +# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1) + +/* The size of an array large to enough to hold all stacks, each with + N elements. */ +# define YYSTACK_BYTES(N) \ + ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \ + + YYSTACK_GAP_MAXIMUM) + +# define YYCOPY_NEEDED 1 + +/* Relocate STACK from its old location to the new one. The + local variables YYSIZE and YYSTACKSIZE give the old and new number of + elements in the stack, and YYPTR gives the new location of the + stack. Advance YYPTR to a properly aligned location for the next + stack. */ +# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ + do \ + { \ + YYSIZE_T yynewbytes; \ + YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ + Stack = &yyptr->Stack_alloc; \ + yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ + yyptr += yynewbytes / sizeof (*yyptr); \ + } \ + while (YYID (0)) + +#endif + +#if defined YYCOPY_NEEDED && YYCOPY_NEEDED +/* Copy COUNT objects from FROM to TO. The source and destination do + not overlap. */ +# ifndef YYCOPY +# if defined __GNUC__ && 1 < __GNUC__ +# define YYCOPY(To, From, Count) \ + __builtin_memcpy (To, From, (Count) * sizeof (*(From))) +# else +# define YYCOPY(To, From, Count) \ + do \ + { \ + YYSIZE_T yyi; \ + for (yyi = 0; yyi < (Count); yyi++) \ + (To)[yyi] = (From)[yyi]; \ + } \ + while (YYID (0)) +# endif +# endif +#endif /* !YYCOPY_NEEDED */ + +/* YYFINAL -- State number of the termination state. */ +#define YYFINAL 11 +/* YYLAST -- Last index in YYTABLE. */ +#define YYLAST 290 + +/* YYNTOKENS -- Number of terminals. */ +#define YYNTOKENS 36 +/* YYNNTS -- Number of nonterminals. */ +#define YYNNTS 50 +/* YYNRULES -- Number of rules. */ +#define YYNRULES 118 +/* YYNRULES -- Number of states. */ +#define YYNSTATES 191 + +/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ +#define YYUNDEFTOK 2 +#define YYMAXUTOK 290 + +#define YYTRANSLATE(YYX) \ + ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) + +/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */ +static const yytype_uint8 yytranslate[] = +{ + 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, + 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, + 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, + 35 +}; + +#if YYDEBUG +/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in + YYRHS. */ +static const yytype_uint16 yyprhs[] = +{ + 0, 0, 3, 6, 8, 11, 13, 14, 17, 20, + 23, 26, 31, 36, 40, 42, 44, 46, 48, 50, + 52, 54, 56, 58, 60, 62, 64, 66, 68, 72, + 75, 79, 82, 86, 89, 90, 93, 96, 99, 102, + 105, 108, 112, 117, 122, 127, 133, 137, 138, 142, + 143, 146, 150, 153, 155, 159, 160, 163, 166, 169, + 172, 175, 180, 184, 187, 192, 193, 196, 200, 202, + 206, 207, 210, 213, 216, 220, 224, 228, 230, 234, + 235, 238, 241, 244, 248, 252, 255, 258, 261, 262, + 265, 268, 271, 276, 277, 280, 283, 286, 287, 290, + 292, 294, 297, 300, 303, 305, 308, 309, 312, 314, + 318, 322, 326, 329, 333, 337, 339, 341, 342 +}; + +/* YYRHS -- A `-1'-separated list of the rules' RHS. */ +static const yytype_int8 yyrhs[] = +{ + 37, 0, -1, 81, 38, -1, 38, -1, 63, 39, + -1, 39, -1, -1, 39, 41, -1, 39, 55, -1, + 39, 67, -1, 39, 80, -1, 39, 26, 1, 31, + -1, 39, 40, 1, 31, -1, 39, 1, 31, -1, + 16, -1, 18, -1, 19, -1, 21, -1, 17, -1, + 22, -1, 20, -1, 23, -1, 31, -1, 61, -1, + 71, -1, 44, -1, 46, -1, 69, -1, 26, 1, + 31, -1, 1, 31, -1, 10, 26, 31, -1, 43, + 47, -1, 11, 26, 31, -1, 45, 47, -1, -1, + 47, 48, -1, 47, 49, -1, 47, 75, -1, 47, + 73, -1, 47, 42, -1, 47, 31, -1, 19, 78, + 31, -1, 18, 79, 82, 31, -1, 20, 83, 82, + 31, -1, 21, 26, 82, 31, -1, 22, 84, 84, + 82, 31, -1, 24, 50, 31, -1, -1, 50, 26, + 51, -1, -1, 34, 79, -1, 7, 85, 31, -1, + 52, 56, -1, 80, -1, 53, 58, 54, -1, -1, + 56, 57, -1, 56, 75, -1, 56, 73, -1, 56, + 31, -1, 56, 42, -1, 18, 79, 82, 31, -1, + 19, 78, 31, -1, 17, 31, -1, 20, 26, 82, + 31, -1, -1, 58, 41, -1, 14, 83, 81, -1, + 80, -1, 59, 62, 60, -1, -1, 62, 41, -1, + 62, 67, -1, 62, 55, -1, 3, 79, 81, -1, + 4, 79, 31, -1, 64, 76, 74, -1, 80, -1, + 65, 68, 66, -1, -1, 68, 41, -1, 68, 67, + -1, 68, 55, -1, 6, 79, 31, -1, 9, 79, + 31, -1, 70, 74, -1, 12, 31, -1, 72, 13, + -1, -1, 74, 75, -1, 74, 31, -1, 74, 42, + -1, 16, 25, 83, 31, -1, -1, 76, 77, -1, + 76, 31, -1, 23, 82, -1, -1, 79, 82, -1, + 26, -1, 27, -1, 5, 31, -1, 8, 31, -1, + 15, 31, -1, 31, -1, 81, 31, -1, -1, 14, + 83, -1, 84, -1, 84, 34, 84, -1, 84, 28, + 84, -1, 30, 83, 29, -1, 35, 83, -1, 83, + 32, 83, -1, 83, 33, 83, -1, 26, -1, 27, + -1, -1, 26, -1 +}; + +/* YYRLINE[YYN] -- source line where rule number YYN was defined. */ +static const yytype_uint16 yyrline[] = +{ + 0, 103, 103, 103, 105, 105, 107, 109, 110, 111, + 112, 113, 114, 118, 122, 122, 122, 122, 122, 122, + 122, 122, 126, 127, 128, 129, 130, 131, 135, 136, + 142, 150, 156, 164, 174, 176, 177, 178, 179, 180, + 181, 184, 192, 198, 208, 214, 220, 223, 225, 236, + 237, 242, 251, 256, 264, 267, 269, 270, 271, 272, + 273, 276, 282, 293, 299, 309, 311, 316, 324, 332, + 335, 337, 338, 339, 344, 351, 358, 363, 371, 374, + 376, 377, 378, 381, 389, 396, 403, 409, 416, 418, + 419, 420, 423, 431, 433, 434, 437, 444, 446, 451, + 452, 455, 456, 457, 461, 462, 465, 466, 469, 470, + 471, 472, 473, 474, 475, 478, 479, 482, 483 +}; +#endif + +#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE +/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. + First, the terminals, then, starting at YYNTOKENS, nonterminals. */ +static const char *const yytname[] = +{ + "$end", "error", "$undefined", "T_MAINMENU", "T_MENU", "T_ENDMENU", + "T_SOURCE", "T_CHOICE", "T_ENDCHOICE", "T_COMMENT", "T_CONFIG", + "T_MENUCONFIG", "T_HELP", "T_HELPTEXT", "T_IF", "T_ENDIF", "T_DEPENDS", + "T_OPTIONAL", "T_PROMPT", "T_TYPE", "T_DEFAULT", "T_SELECT", "T_RANGE", + "T_VISIBLE", "T_OPTION", "T_ON", "T_WORD", "T_WORD_QUOTE", "T_UNEQUAL", + "T_CLOSE_PAREN", "T_OPEN_PAREN", "T_EOL", "T_OR", "T_AND", "T_EQUAL", + "T_NOT", "$accept", "input", "start", "stmt_list", "option_name", + "common_stmt", "option_error", "config_entry_start", "config_stmt", + "menuconfig_entry_start", "menuconfig_stmt", "config_option_list", + "config_option", "symbol_option", "symbol_option_list", + "symbol_option_arg", "choice", "choice_entry", "choice_end", + "choice_stmt", "choice_option_list", "choice_option", "choice_block", + "if_entry", "if_end", "if_stmt", "if_block", "mainmenu_stmt", "menu", + "menu_entry", "menu_end", "menu_stmt", "menu_block", "source_stmt", + "comment", "comment_stmt", "help_start", "help", "depends_list", + "depends", "visibility_list", "visible", "prompt_stmt_opt", "prompt", + "end", "nl", "if_expr", "expr", "symbol", "word_opt", 0 +}; +#endif + +# ifdef YYPRINT +/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to + token YYLEX-NUM. */ +static const yytype_uint16 yytoknum[] = +{ + 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, + 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, + 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, + 285, 286, 287, 288, 289, 290 +}; +# endif + +/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ +static const yytype_uint8 yyr1[] = +{ + 0, 36, 37, 37, 38, 38, 39, 39, 39, 39, + 39, 39, 39, 39, 40, 40, 40, 40, 40, 40, + 40, 40, 41, 41, 41, 41, 41, 41, 42, 42, + 43, 44, 45, 46, 47, 47, 47, 47, 47, 47, + 47, 48, 48, 48, 48, 48, 49, 50, 50, 51, + 51, 52, 53, 54, 55, 56, 56, 56, 56, 56, + 56, 57, 57, 57, 57, 58, 58, 59, 60, 61, + 62, 62, 62, 62, 63, 64, 65, 66, 67, 68, + 68, 68, 68, 69, 70, 71, 72, 73, 74, 74, + 74, 74, 75, 76, 76, 76, 77, 78, 78, 79, + 79, 80, 80, 80, 81, 81, 82, 82, 83, 83, + 83, 83, 83, 83, 83, 84, 84, 85, 85 +}; + +/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ +static const yytype_uint8 yyr2[] = +{ + 0, 2, 2, 1, 2, 1, 0, 2, 2, 2, + 2, 4, 4, 3, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 3, 2, + 3, 2, 3, 2, 0, 2, 2, 2, 2, 2, + 2, 3, 4, 4, 4, 5, 3, 0, 3, 0, + 2, 3, 2, 1, 3, 0, 2, 2, 2, 2, + 2, 4, 3, 2, 4, 0, 2, 3, 1, 3, + 0, 2, 2, 2, 3, 3, 3, 1, 3, 0, + 2, 2, 2, 3, 3, 2, 2, 2, 0, 2, + 2, 2, 4, 0, 2, 2, 2, 0, 2, 1, + 1, 2, 2, 2, 1, 2, 0, 2, 1, 3, + 3, 3, 2, 3, 3, 1, 1, 0, 1 +}; + +/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM. + Performed when YYTABLE doesn't specify something else to do. Zero + means the default is an error. */ +static const yytype_uint8 yydefact[] = +{ + 6, 0, 104, 0, 3, 0, 6, 6, 99, 100, + 0, 1, 0, 0, 0, 0, 117, 0, 0, 0, + 0, 0, 0, 14, 18, 15, 16, 20, 17, 19, + 21, 0, 22, 0, 7, 34, 25, 34, 26, 55, + 65, 8, 70, 23, 93, 79, 9, 27, 88, 24, + 10, 0, 105, 2, 74, 13, 0, 101, 0, 118, + 0, 102, 0, 0, 0, 115, 116, 0, 0, 0, + 108, 103, 0, 0, 0, 0, 0, 0, 0, 88, + 0, 0, 75, 83, 51, 84, 30, 32, 0, 112, + 0, 0, 67, 0, 0, 11, 12, 0, 0, 0, + 0, 97, 0, 0, 0, 47, 0, 40, 39, 35, + 36, 0, 38, 37, 0, 0, 97, 0, 59, 60, + 56, 58, 57, 66, 54, 53, 71, 73, 69, 72, + 68, 106, 95, 0, 94, 80, 82, 78, 81, 77, + 90, 91, 89, 111, 113, 114, 110, 109, 29, 86, + 0, 106, 0, 106, 106, 106, 0, 0, 0, 87, + 63, 106, 0, 106, 0, 96, 0, 0, 41, 98, + 0, 0, 106, 49, 46, 28, 0, 62, 0, 107, + 92, 42, 43, 44, 0, 0, 48, 61, 64, 45, + 50 +}; + +/* YYDEFGOTO[NTERM-NUM]. */ +static const yytype_int16 yydefgoto[] = +{ + -1, 3, 4, 5, 33, 34, 108, 35, 36, 37, + 38, 74, 109, 110, 157, 186, 39, 40, 124, 41, + 76, 120, 77, 42, 128, 43, 78, 6, 44, 45, + 137, 46, 80, 47, 48, 49, 111, 112, 81, 113, + 79, 134, 152, 153, 50, 7, 165, 69, 70, 60 +}; + +/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing + STATE-NUM. */ +#define YYPACT_NINF -90 +static const yytype_int16 yypact[] = +{ + 4, 42, -90, 96, -90, 111, -90, 15, -90, -90, + 75, -90, 82, 42, 104, 42, 110, 107, 42, 115, + 125, -4, 121, -90, -90, -90, -90, -90, -90, -90, + -90, 162, -90, 163, -90, -90, -90, -90, -90, -90, + -90, -90, -90, -90, -90, -90, -90, -90, -90, -90, + -90, 139, -90, -90, 138, -90, 142, -90, 143, -90, + 152, -90, 164, 167, 168, -90, -90, -4, -4, 77, + -18, -90, 177, 185, 33, 71, 195, 247, 236, -2, + 236, 171, -90, -90, -90, -90, -90, -90, 41, -90, + -4, -4, 138, 97, 97, -90, -90, 186, 187, 194, + 42, 42, -4, 196, 97, -90, 219, -90, -90, -90, + -90, 210, -90, -90, 204, 42, 42, 199, -90, -90, + -90, -90, -90, -90, -90, -90, -90, -90, -90, -90, + -90, 222, -90, 223, -90, -90, -90, -90, -90, -90, + -90, -90, -90, -90, 215, -90, -90, -90, -90, -90, + -4, 222, 228, 222, -5, 222, 97, 35, 229, -90, + -90, 222, 232, 222, -4, -90, 135, 233, -90, -90, + 234, 235, 222, 240, -90, -90, 237, -90, 239, -13, + -90, -90, -90, -90, 244, 42, -90, -90, -90, -90, + -90 +}; + +/* YYPGOTO[NTERM-NUM]. */ +static const yytype_int16 yypgoto[] = +{ + -90, -90, 269, 271, -90, 23, -70, -90, -90, -90, + -90, 243, -90, -90, -90, -90, -90, -90, -90, -48, + -90, -90, -90, -90, -90, -90, -90, -90, -90, -90, + -90, -20, -90, -90, -90, -90, -90, 206, 205, -68, + -90, -90, 169, -1, 27, -7, 118, -66, -89, -90 +}; + +/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If + positive, shift that token. If negative, reduce the rule which + number is the opposite. If YYTABLE_NINF, syntax error. */ +#define YYTABLE_NINF -86 +static const yytype_int16 yytable[] = +{ + 10, 88, 89, 54, 146, 147, 119, 1, 122, 164, + 93, 141, 56, 142, 58, 156, 94, 62, 1, 90, + 91, 131, 65, 66, 144, 145, 67, 90, 91, 132, + 127, 68, 136, -31, 97, 2, 154, -31, -31, -31, + -31, -31, -31, -31, -31, 98, 52, -31, -31, 99, + -31, 100, 101, 102, 103, 104, -31, 105, 129, 106, + 138, 173, 92, 141, 107, 142, 174, 172, 8, 9, + 143, -33, 97, 90, 91, -33, -33, -33, -33, -33, + -33, -33, -33, 98, 166, -33, -33, 99, -33, 100, + 101, 102, 103, 104, -33, 105, 11, 106, 179, 151, + 123, 126, 107, 135, 125, 130, 2, 139, 2, 90, + 91, -5, 12, 55, 161, 13, 14, 15, 16, 17, + 18, 19, 20, 65, 66, 21, 22, 23, 24, 25, + 26, 27, 28, 29, 30, 57, 59, 31, 61, -4, + 12, 63, 32, 13, 14, 15, 16, 17, 18, 19, + 20, 64, 71, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 30, 72, 73, 31, 180, 90, 91, 52, + 32, -85, 97, 82, 83, -85, -85, -85, -85, -85, + -85, -85, -85, 84, 190, -85, -85, 99, -85, -85, + -85, -85, -85, -85, -85, 85, 97, 106, 86, 87, + -52, -52, 140, -52, -52, -52, -52, 98, 95, -52, + -52, 99, 114, 115, 116, 117, 96, 148, 149, 150, + 158, 106, 155, 159, 97, 163, 118, -76, -76, -76, + -76, -76, -76, -76, -76, 160, 164, -76, -76, 99, + 13, 14, 15, 16, 17, 18, 19, 20, 91, 106, + 21, 22, 14, 15, 140, 17, 18, 19, 20, 168, + 175, 21, 22, 177, 181, 182, 183, 32, 187, 167, + 188, 169, 170, 171, 185, 189, 53, 51, 32, 176, + 75, 178, 121, 0, 133, 162, 0, 0, 0, 0, + 184 +}; + +#define yypact_value_is_default(yystate) \ + ((yystate) == (-90)) + +#define yytable_value_is_error(yytable_value) \ + YYID (0) + +static const yytype_int16 yycheck[] = +{ + 1, 67, 68, 10, 93, 94, 76, 3, 76, 14, + 28, 81, 13, 81, 15, 104, 34, 18, 3, 32, + 33, 23, 26, 27, 90, 91, 30, 32, 33, 31, + 78, 35, 80, 0, 1, 31, 102, 4, 5, 6, + 7, 8, 9, 10, 11, 12, 31, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 78, 26, + 80, 26, 69, 133, 31, 133, 31, 156, 26, 27, + 29, 0, 1, 32, 33, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 150, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 24, 0, 26, 164, 100, + 77, 78, 31, 80, 77, 78, 31, 80, 31, 32, + 33, 0, 1, 31, 115, 4, 5, 6, 7, 8, + 9, 10, 11, 26, 27, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 31, 26, 26, 31, 0, + 1, 26, 31, 4, 5, 6, 7, 8, 9, 10, + 11, 26, 31, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 1, 1, 26, 31, 32, 33, 31, + 31, 0, 1, 31, 31, 4, 5, 6, 7, 8, + 9, 10, 11, 31, 185, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 31, 1, 26, 31, 31, + 5, 6, 31, 8, 9, 10, 11, 12, 31, 14, + 15, 16, 17, 18, 19, 20, 31, 31, 31, 25, + 1, 26, 26, 13, 1, 26, 31, 4, 5, 6, + 7, 8, 9, 10, 11, 31, 14, 14, 15, 16, + 4, 5, 6, 7, 8, 9, 10, 11, 33, 26, + 14, 15, 5, 6, 31, 8, 9, 10, 11, 31, + 31, 14, 15, 31, 31, 31, 31, 31, 31, 151, + 31, 153, 154, 155, 34, 31, 7, 6, 31, 161, + 37, 163, 76, -1, 79, 116, -1, -1, -1, -1, + 172 +}; + +/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing + symbol of state STATE-NUM. */ +static const yytype_uint8 yystos[] = +{ + 0, 3, 31, 37, 38, 39, 63, 81, 26, 27, + 79, 0, 1, 4, 5, 6, 7, 8, 9, 10, + 11, 14, 15, 16, 17, 18, 19, 20, 21, 22, + 23, 26, 31, 40, 41, 43, 44, 45, 46, 52, + 53, 55, 59, 61, 64, 65, 67, 69, 70, 71, + 80, 39, 31, 38, 81, 31, 79, 31, 79, 26, + 85, 31, 79, 26, 26, 26, 27, 30, 35, 83, + 84, 31, 1, 1, 47, 47, 56, 58, 62, 76, + 68, 74, 31, 31, 31, 31, 31, 31, 83, 83, + 32, 33, 81, 28, 34, 31, 31, 1, 12, 16, + 18, 19, 20, 21, 22, 24, 26, 31, 42, 48, + 49, 72, 73, 75, 17, 18, 19, 20, 31, 42, + 57, 73, 75, 41, 54, 80, 41, 55, 60, 67, + 80, 23, 31, 74, 77, 41, 55, 66, 67, 80, + 31, 42, 75, 29, 83, 83, 84, 84, 31, 31, + 25, 79, 78, 79, 83, 26, 84, 50, 1, 13, + 31, 79, 78, 26, 14, 82, 83, 82, 31, 82, + 82, 82, 84, 26, 31, 31, 82, 31, 82, 83, + 31, 31, 31, 31, 82, 34, 51, 31, 31, 31, + 79 +}; + +#define yyerrok (yyerrstatus = 0) +#define yyclearin (yychar = YYEMPTY) +#define YYEMPTY (-2) +#define YYEOF 0 + +#define YYACCEPT goto yyacceptlab +#define YYABORT goto yyabortlab +#define YYERROR goto yyerrorlab + + +/* Like YYERROR except do call yyerror. This remains here temporarily + to ease the transition to the new meaning of YYERROR, for GCC. + Once GCC version 2 has supplanted version 1, this can go. However, + YYFAIL appears to be in use. Nevertheless, it is formally deprecated + in Bison 2.4.2's NEWS entry, where a plan to phase it out is + discussed. */ + +#define YYFAIL goto yyerrlab +#if defined YYFAIL + /* This is here to suppress warnings from the GCC cpp's + -Wunused-macros. Normally we don't worry about that warning, but + some users do, and we want to make it easy for users to remove + YYFAIL uses, which will produce warnings from Bison 2.5. */ +#endif + +#define YYRECOVERING() (!!yyerrstatus) + +#define YYBACKUP(Token, Value) \ +do \ + if (yychar == YYEMPTY && yylen == 1) \ + { \ + yychar = (Token); \ + yylval = (Value); \ + YYPOPSTACK (1); \ + goto yybackup; \ + } \ + else \ + { \ + yyerror (YY_("syntax error: cannot back up")); \ + YYERROR; \ + } \ +while (YYID (0)) + + +#define YYTERROR 1 +#define YYERRCODE 256 + + +/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N]. + If N is 0, then set CURRENT to the empty location which ends + the previous symbol: RHS[0] (always defined). */ + +#define YYRHSLOC(Rhs, K) ((Rhs)[K]) +#ifndef YYLLOC_DEFAULT +# define YYLLOC_DEFAULT(Current, Rhs, N) \ + do \ + if (YYID (N)) \ + { \ + (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \ + (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \ + (Current).last_line = YYRHSLOC (Rhs, N).last_line; \ + (Current).last_column = YYRHSLOC (Rhs, N).last_column; \ + } \ + else \ + { \ + (Current).first_line = (Current).last_line = \ + YYRHSLOC (Rhs, 0).last_line; \ + (Current).first_column = (Current).last_column = \ + YYRHSLOC (Rhs, 0).last_column; \ + } \ + while (YYID (0)) +#endif + + +/* This macro is provided for backward compatibility. */ + +#ifndef YY_LOCATION_PRINT +# define YY_LOCATION_PRINT(File, Loc) ((void) 0) +#endif + + +/* YYLEX -- calling `yylex' with the right arguments. */ + +#ifdef YYLEX_PARAM +# define YYLEX yylex (YYLEX_PARAM) +#else +# define YYLEX yylex () +#endif + +/* Enable debugging if requested. */ +#if YYDEBUG + +# ifndef YYFPRINTF +# include /* INFRINGES ON USER NAME SPACE */ +# define YYFPRINTF fprintf +# endif + +# define YYDPRINTF(Args) \ +do { \ + if (yydebug) \ + YYFPRINTF Args; \ +} while (YYID (0)) + +# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ +do { \ + if (yydebug) \ + { \ + YYFPRINTF (stderr, "%s ", Title); \ + yy_symbol_print (stderr, \ + Type, Value); \ + YYFPRINTF (stderr, "\n"); \ + } \ +} while (YYID (0)) + + +/*--------------------------------. +| Print this symbol on YYOUTPUT. | +`--------------------------------*/ + +/*ARGSUSED*/ +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +static void +yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) +#else +static void +yy_symbol_value_print (yyoutput, yytype, yyvaluep) + FILE *yyoutput; + int yytype; + YYSTYPE const * const yyvaluep; +#endif +{ + if (!yyvaluep) + return; +# ifdef YYPRINT + if (yytype < YYNTOKENS) + YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep); +# else + YYUSE (yyoutput); +# endif + switch (yytype) + { + default: + break; + } +} + + +/*--------------------------------. +| Print this symbol on YYOUTPUT. | +`--------------------------------*/ + +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +static void +yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) +#else +static void +yy_symbol_print (yyoutput, yytype, yyvaluep) + FILE *yyoutput; + int yytype; + YYSTYPE const * const yyvaluep; +#endif +{ + if (yytype < YYNTOKENS) + YYFPRINTF (yyoutput, "token %s (", yytname[yytype]); + else + YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]); + + yy_symbol_value_print (yyoutput, yytype, yyvaluep); + YYFPRINTF (yyoutput, ")"); +} + +/*------------------------------------------------------------------. +| yy_stack_print -- Print the state stack from its BOTTOM up to its | +| TOP (included). | +`------------------------------------------------------------------*/ + +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +static void +yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop) +#else +static void +yy_stack_print (yybottom, yytop) + yytype_int16 *yybottom; + yytype_int16 *yytop; +#endif +{ + YYFPRINTF (stderr, "Stack now"); + for (; yybottom <= yytop; yybottom++) + { + int yybot = *yybottom; + YYFPRINTF (stderr, " %d", yybot); + } + YYFPRINTF (stderr, "\n"); +} + +# define YY_STACK_PRINT(Bottom, Top) \ +do { \ + if (yydebug) \ + yy_stack_print ((Bottom), (Top)); \ +} while (YYID (0)) + + +/*------------------------------------------------. +| Report that the YYRULE is going to be reduced. | +`------------------------------------------------*/ + +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +static void +yy_reduce_print (YYSTYPE *yyvsp, int yyrule) +#else +static void +yy_reduce_print (yyvsp, yyrule) + YYSTYPE *yyvsp; + int yyrule; +#endif +{ + int yynrhs = yyr2[yyrule]; + int yyi; + unsigned long int yylno = yyrline[yyrule]; + YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n", + yyrule - 1, yylno); + /* The symbols being reduced. */ + for (yyi = 0; yyi < yynrhs; yyi++) + { + YYFPRINTF (stderr, " $%d = ", yyi + 1); + yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi], + &(yyvsp[(yyi + 1) - (yynrhs)]) + ); + YYFPRINTF (stderr, "\n"); + } +} + +# define YY_REDUCE_PRINT(Rule) \ +do { \ + if (yydebug) \ + yy_reduce_print (yyvsp, Rule); \ +} while (YYID (0)) + +/* Nonzero means print parse trace. It is left uninitialized so that + multiple parsers can coexist. */ +int yydebug; +#else /* !YYDEBUG */ +# define YYDPRINTF(Args) +# define YY_SYMBOL_PRINT(Title, Type, Value, Location) +# define YY_STACK_PRINT(Bottom, Top) +# define YY_REDUCE_PRINT(Rule) +#endif /* !YYDEBUG */ + + +/* YYINITDEPTH -- initial size of the parser's stacks. */ +#ifndef YYINITDEPTH +# define YYINITDEPTH 200 +#endif + +/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only + if the built-in stack extension method is used). + + Do not make this value too large; the results are undefined if + YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH) + evaluated with infinite-precision integer arithmetic. */ + +#ifndef YYMAXDEPTH +# define YYMAXDEPTH 10000 +#endif + + +#if YYERROR_VERBOSE + +# ifndef yystrlen +# if defined __GLIBC__ && defined _STRING_H +# define yystrlen strlen +# else +/* Return the length of YYSTR. */ +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +static YYSIZE_T +yystrlen (const char *yystr) +#else +static YYSIZE_T +yystrlen (yystr) + const char *yystr; +#endif +{ + YYSIZE_T yylen; + for (yylen = 0; yystr[yylen]; yylen++) + continue; + return yylen; +} +# endif +# endif + +# ifndef yystpcpy +# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE +# define yystpcpy stpcpy +# else +/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in + YYDEST. */ +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +static char * +yystpcpy (char *yydest, const char *yysrc) +#else +static char * +yystpcpy (yydest, yysrc) + char *yydest; + const char *yysrc; +#endif +{ + char *yyd = yydest; + const char *yys = yysrc; + + while ((*yyd++ = *yys++) != '\0') + continue; + + return yyd - 1; +} +# endif +# endif + +# ifndef yytnamerr +/* Copy to YYRES the contents of YYSTR after stripping away unnecessary + quotes and backslashes, so that it's suitable for yyerror. The + heuristic is that double-quoting is unnecessary unless the string + contains an apostrophe, a comma, or backslash (other than + backslash-backslash). YYSTR is taken from yytname. If YYRES is + null, do not copy; instead, return the length of what the result + would have been. */ +static YYSIZE_T +yytnamerr (char *yyres, const char *yystr) +{ + if (*yystr == '"') + { + YYSIZE_T yyn = 0; + char const *yyp = yystr; + + for (;;) + switch (*++yyp) + { + case '\'': + case ',': + goto do_not_strip_quotes; + + case '\\': + if (*++yyp != '\\') + goto do_not_strip_quotes; + /* Fall through. */ + default: + if (yyres) + yyres[yyn] = *yyp; + yyn++; + break; + + case '"': + if (yyres) + yyres[yyn] = '\0'; + return yyn; + } + do_not_strip_quotes: ; + } + + if (! yyres) + return yystrlen (yystr); + + return yystpcpy (yyres, yystr) - yyres; +} +# endif + +/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message + about the unexpected token YYTOKEN for the state stack whose top is + YYSSP. + + Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is + not large enough to hold the message. In that case, also set + *YYMSG_ALLOC to the required number of bytes. Return 2 if the + required number of bytes is too large to store. */ +static int +yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, + yytype_int16 *yyssp, int yytoken) +{ + YYSIZE_T yysize0 = yytnamerr (0, yytname[yytoken]); + YYSIZE_T yysize = yysize0; + YYSIZE_T yysize1; + enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; + /* Internationalized format string. */ + const char *yyformat = 0; + /* Arguments of yyformat. */ + char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; + /* Number of reported tokens (one for the "unexpected", one per + "expected"). */ + int yycount = 0; + + /* There are many possibilities here to consider: + - Assume YYFAIL is not used. It's too flawed to consider. See + + for details. YYERROR is fine as it does not invoke this + function. + - If this state is a consistent state with a default action, then + the only way this function was invoked is if the default action + is an error action. In that case, don't check for expected + tokens because there are none. + - The only way there can be no lookahead present (in yychar) is if + this state is a consistent state with a default action. Thus, + detecting the absence of a lookahead is sufficient to determine + that there is no unexpected or expected token to report. In that + case, just report a simple "syntax error". + - Don't assume there isn't a lookahead just because this state is a + consistent state with a default action. There might have been a + previous inconsistent state, consistent state with a non-default + action, or user semantic action that manipulated yychar. + - Of course, the expected token list depends on states to have + correct lookahead information, and it depends on the parser not + to perform extra reductions after fetching a lookahead from the + scanner and before detecting a syntax error. Thus, state merging + (from LALR or IELR) and default reductions corrupt the expected + token list. However, the list is correct for canonical LR with + one exception: it will still contain any token that will not be + accepted due to an error action in a later state. + */ + if (yytoken != YYEMPTY) + { + int yyn = yypact[*yyssp]; + yyarg[yycount++] = yytname[yytoken]; + if (!yypact_value_is_default (yyn)) + { + /* Start YYX at -YYN if negative to avoid negative indexes in + YYCHECK. In other words, skip the first -YYN actions for + this state because they are default actions. */ + int yyxbegin = yyn < 0 ? -yyn : 0; + /* Stay within bounds of both yycheck and yytname. */ + int yychecklim = YYLAST - yyn + 1; + int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS; + int yyx; + + for (yyx = yyxbegin; yyx < yyxend; ++yyx) + if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR + && !yytable_value_is_error (yytable[yyx + yyn])) + { + if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM) + { + yycount = 1; + yysize = yysize0; + break; + } + yyarg[yycount++] = yytname[yyx]; + yysize1 = yysize + yytnamerr (0, yytname[yyx]); + if (! (yysize <= yysize1 + && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + return 2; + yysize = yysize1; + } + } + } + + switch (yycount) + { +# define YYCASE_(N, S) \ + case N: \ + yyformat = S; \ + break + YYCASE_(0, YY_("syntax error")); + YYCASE_(1, YY_("syntax error, unexpected %s")); + YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); + YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s")); + YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s")); + YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s")); +# undef YYCASE_ + } + + yysize1 = yysize + yystrlen (yyformat); + if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + return 2; + yysize = yysize1; + + if (*yymsg_alloc < yysize) + { + *yymsg_alloc = 2 * yysize; + if (! (yysize <= *yymsg_alloc + && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM)) + *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM; + return 1; + } + + /* Avoid sprintf, as that infringes on the user's name space. + Don't have undefined behavior even if the translation + produced a string with the wrong number of "%s"s. */ + { + char *yyp = *yymsg; + int yyi = 0; + while ((*yyp = *yyformat) != '\0') + if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount) + { + yyp += yytnamerr (yyp, yyarg[yyi++]); + yyformat += 2; + } + else + { + yyp++; + yyformat++; + } + } + return 0; +} +#endif /* YYERROR_VERBOSE */ + +/*-----------------------------------------------. +| Release the memory associated to this symbol. | +`-----------------------------------------------*/ + +/*ARGSUSED*/ +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +static void +yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) +#else +static void +yydestruct (yymsg, yytype, yyvaluep) + const char *yymsg; + int yytype; + YYSTYPE *yyvaluep; +#endif +{ + YYUSE (yyvaluep); + + if (!yymsg) + yymsg = "Deleting"; + YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); + + switch (yytype) + { + case 53: /* "choice_entry" */ + + { + fprintf(stderr, "%s:%d: missing end statement for this entry\n", + (yyvaluep->menu)->file->name, (yyvaluep->menu)->lineno); + if (current_menu == (yyvaluep->menu)) + menu_end_menu(); +}; + + break; + case 59: /* "if_entry" */ + + { + fprintf(stderr, "%s:%d: missing end statement for this entry\n", + (yyvaluep->menu)->file->name, (yyvaluep->menu)->lineno); + if (current_menu == (yyvaluep->menu)) + menu_end_menu(); +}; + + break; + case 65: /* "menu_entry" */ + + { + fprintf(stderr, "%s:%d: missing end statement for this entry\n", + (yyvaluep->menu)->file->name, (yyvaluep->menu)->lineno); + if (current_menu == (yyvaluep->menu)) + menu_end_menu(); +}; + + break; + + default: + break; + } +} + + +/* Prevent warnings from -Wmissing-prototypes. */ +#ifdef YYPARSE_PARAM +#if defined __STDC__ || defined __cplusplus +int yyparse (void *YYPARSE_PARAM); +#else +int yyparse (); +#endif +#else /* ! YYPARSE_PARAM */ +#if defined __STDC__ || defined __cplusplus +int yyparse (void); +#else +int yyparse (); +#endif +#endif /* ! YYPARSE_PARAM */ + + +/* The lookahead symbol. */ +int yychar; + +/* The semantic value of the lookahead symbol. */ +YYSTYPE yylval; + +/* Number of syntax errors so far. */ +int yynerrs; + + +/*----------. +| yyparse. | +`----------*/ + +#ifdef YYPARSE_PARAM +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +int +yyparse (void *YYPARSE_PARAM) +#else +int +yyparse (YYPARSE_PARAM) + void *YYPARSE_PARAM; +#endif +#else /* ! YYPARSE_PARAM */ +#if (defined __STDC__ || defined __C99__FUNC__ \ + || defined __cplusplus || defined _MSC_VER) +int +yyparse (void) +#else +int +yyparse () + +#endif +#endif +{ + int yystate; + /* Number of tokens to shift before error messages enabled. */ + int yyerrstatus; + + /* The stacks and their tools: + `yyss': related to states. + `yyvs': related to semantic values. + + Refer to the stacks thru separate pointers, to allow yyoverflow + to reallocate them elsewhere. */ + + /* The state stack. */ + yytype_int16 yyssa[YYINITDEPTH]; + yytype_int16 *yyss; + yytype_int16 *yyssp; + + /* The semantic value stack. */ + YYSTYPE yyvsa[YYINITDEPTH]; + YYSTYPE *yyvs; + YYSTYPE *yyvsp; + + YYSIZE_T yystacksize; + + int yyn; + int yyresult; + /* Lookahead token as an internal (translated) token number. */ + int yytoken; + /* The variables used to return semantic value and location from the + action routines. */ + YYSTYPE yyval; + +#if YYERROR_VERBOSE + /* Buffer for error messages, and its allocated size. */ + char yymsgbuf[128]; + char *yymsg = yymsgbuf; + YYSIZE_T yymsg_alloc = sizeof yymsgbuf; +#endif + +#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) + + /* The number of symbols on the RHS of the reduced rule. + Keep to zero when no symbol should be popped. */ + int yylen = 0; + + yytoken = 0; + yyss = yyssa; + yyvs = yyvsa; + yystacksize = YYINITDEPTH; + + YYDPRINTF ((stderr, "Starting parse\n")); + + yystate = 0; + yyerrstatus = 0; + yynerrs = 0; + yychar = YYEMPTY; /* Cause a token to be read. */ + + /* Initialize stack pointers. + Waste one element of value and location stack + so that they stay on the same level as the state stack. + The wasted elements are never initialized. */ + yyssp = yyss; + yyvsp = yyvs; + + goto yysetstate; + +/*------------------------------------------------------------. +| yynewstate -- Push a new state, which is found in yystate. | +`------------------------------------------------------------*/ + yynewstate: + /* In all cases, when you get here, the value and location stacks + have just been pushed. So pushing a state here evens the stacks. */ + yyssp++; + + yysetstate: + *yyssp = yystate; + + if (yyss + yystacksize - 1 <= yyssp) + { + /* Get the current used size of the three stacks, in elements. */ + YYSIZE_T yysize = yyssp - yyss + 1; + +#ifdef yyoverflow + { + /* Give user a chance to reallocate the stack. Use copies of + these so that the &'s don't force the real ones into + memory. */ + YYSTYPE *yyvs1 = yyvs; + yytype_int16 *yyss1 = yyss; + + /* Each stack pointer address is followed by the size of the + data in use in that stack, in bytes. This used to be a + conditional around just the two extra args, but that might + be undefined if yyoverflow is a macro. */ + yyoverflow (YY_("memory exhausted"), + &yyss1, yysize * sizeof (*yyssp), + &yyvs1, yysize * sizeof (*yyvsp), + &yystacksize); + + yyss = yyss1; + yyvs = yyvs1; + } +#else /* no yyoverflow */ +# ifndef YYSTACK_RELOCATE + goto yyexhaustedlab; +# else + /* Extend the stack our own way. */ + if (YYMAXDEPTH <= yystacksize) + goto yyexhaustedlab; + yystacksize *= 2; + if (YYMAXDEPTH < yystacksize) + yystacksize = YYMAXDEPTH; + + { + yytype_int16 *yyss1 = yyss; + union yyalloc *yyptr = + (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); + if (! yyptr) + goto yyexhaustedlab; + YYSTACK_RELOCATE (yyss_alloc, yyss); + YYSTACK_RELOCATE (yyvs_alloc, yyvs); +# undef YYSTACK_RELOCATE + if (yyss1 != yyssa) + YYSTACK_FREE (yyss1); + } +# endif +#endif /* no yyoverflow */ + + yyssp = yyss + yysize - 1; + yyvsp = yyvs + yysize - 1; + + YYDPRINTF ((stderr, "Stack size increased to %lu\n", + (unsigned long int) yystacksize)); + + if (yyss + yystacksize - 1 <= yyssp) + YYABORT; + } + + YYDPRINTF ((stderr, "Entering state %d\n", yystate)); + + if (yystate == YYFINAL) + YYACCEPT; + + goto yybackup; + +/*-----------. +| yybackup. | +`-----------*/ +yybackup: + + /* Do appropriate processing given the current state. Read a + lookahead token if we need one and don't already have one. */ + + /* First try to decide what to do without reference to lookahead token. */ + yyn = yypact[yystate]; + if (yypact_value_is_default (yyn)) + goto yydefault; + + /* Not known => get a lookahead token if don't already have one. */ + + /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */ + if (yychar == YYEMPTY) + { + YYDPRINTF ((stderr, "Reading a token: ")); + yychar = YYLEX; + } + + if (yychar <= YYEOF) + { + yychar = yytoken = YYEOF; + YYDPRINTF ((stderr, "Now at end of input.\n")); + } + else + { + yytoken = YYTRANSLATE (yychar); + YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc); + } + + /* If the proper action on seeing token YYTOKEN is to reduce or to + detect an error, take that action. */ + yyn += yytoken; + if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken) + goto yydefault; + yyn = yytable[yyn]; + if (yyn <= 0) + { + if (yytable_value_is_error (yyn)) + goto yyerrlab; + yyn = -yyn; + goto yyreduce; + } + + /* Count tokens shifted since error; after three, turn off error + status. */ + if (yyerrstatus) + yyerrstatus--; + + /* Shift the lookahead token. */ + YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc); + + /* Discard the shifted token. */ + yychar = YYEMPTY; + + yystate = yyn; + *++yyvsp = yylval; + + goto yynewstate; + + +/*-----------------------------------------------------------. +| yydefault -- do the default action for the current state. | +`-----------------------------------------------------------*/ +yydefault: + yyn = yydefact[yystate]; + if (yyn == 0) + goto yyerrlab; + goto yyreduce; + + +/*-----------------------------. +| yyreduce -- Do a reduction. | +`-----------------------------*/ +yyreduce: + /* yyn is the number of a rule to reduce with. */ + yylen = yyr2[yyn]; + + /* If YYLEN is nonzero, implement the default value of the action: + `$$ = $1'. + + Otherwise, the following line sets YYVAL to garbage. + This behavior is undocumented and Bison + users should not rely upon it. Assigning to YYVAL + unconditionally makes the parser a bit smaller, and it avoids a + GCC warning that YYVAL may be used uninitialized. */ + yyval = yyvsp[1-yylen]; + + + YY_REDUCE_PRINT (yyn); + switch (yyn) + { + case 10: + + { zconf_error("unexpected end statement"); } + break; + + case 11: + + { zconf_error("unknown statement \"%s\"", (yyvsp[(2) - (4)].string)); } + break; + + case 12: + + { + zconf_error("unexpected option \"%s\"", kconf_id_strings + (yyvsp[(2) - (4)].id)->name); +} + break; + + case 13: + + { zconf_error("invalid statement"); } + break; + + case 28: + + { zconf_error("unknown option \"%s\"", (yyvsp[(1) - (3)].string)); } + break; + + case 29: + + { zconf_error("invalid option"); } + break; + + case 30: + + { + struct symbol *sym = sym_lookup((yyvsp[(2) - (3)].string), 0); + sym->flags |= SYMBOL_OPTIONAL; + menu_add_entry(sym); + printd(DEBUG_PARSE, "%s:%d:config %s\n", zconf_curname(), zconf_lineno(), (yyvsp[(2) - (3)].string)); +} + break; + + case 31: + + { + menu_end_entry(); + printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno()); +} + break; + + case 32: + + { + struct symbol *sym = sym_lookup((yyvsp[(2) - (3)].string), 0); + sym->flags |= SYMBOL_OPTIONAL; + menu_add_entry(sym); + printd(DEBUG_PARSE, "%s:%d:menuconfig %s\n", zconf_curname(), zconf_lineno(), (yyvsp[(2) - (3)].string)); +} + break; + + case 33: + + { + if (current_entry->prompt) + current_entry->prompt->type = P_MENU; + else + zconfprint("warning: menuconfig statement without prompt"); + menu_end_entry(); + printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno()); +} + break; + + case 41: + + { + menu_set_type((yyvsp[(1) - (3)].id)->stype); + printd(DEBUG_PARSE, "%s:%d:type(%u)\n", + zconf_curname(), zconf_lineno(), + (yyvsp[(1) - (3)].id)->stype); +} + break; + + case 42: + + { + menu_add_prompt(P_PROMPT, (yyvsp[(2) - (4)].string), (yyvsp[(3) - (4)].expr)); + printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno()); +} + break; + + case 43: + + { + menu_add_expr(P_DEFAULT, (yyvsp[(2) - (4)].expr), (yyvsp[(3) - (4)].expr)); + if ((yyvsp[(1) - (4)].id)->stype != S_UNKNOWN) + menu_set_type((yyvsp[(1) - (4)].id)->stype); + printd(DEBUG_PARSE, "%s:%d:default(%u)\n", + zconf_curname(), zconf_lineno(), + (yyvsp[(1) - (4)].id)->stype); +} + break; + + case 44: + + { + menu_add_symbol(P_SELECT, sym_lookup((yyvsp[(2) - (4)].string), 0), (yyvsp[(3) - (4)].expr)); + printd(DEBUG_PARSE, "%s:%d:select\n", zconf_curname(), zconf_lineno()); +} + break; + + case 45: + + { + menu_add_expr(P_RANGE, expr_alloc_comp(E_RANGE,(yyvsp[(2) - (5)].symbol), (yyvsp[(3) - (5)].symbol)), (yyvsp[(4) - (5)].expr)); + printd(DEBUG_PARSE, "%s:%d:range\n", zconf_curname(), zconf_lineno()); +} + break; + + case 48: + + { + const struct kconf_id *id = kconf_id_lookup((yyvsp[(2) - (3)].string), strlen((yyvsp[(2) - (3)].string))); + if (id && id->flags & TF_OPTION) + menu_add_option(id->token, (yyvsp[(3) - (3)].string)); + else + zconfprint("warning: ignoring unknown option %s", (yyvsp[(2) - (3)].string)); + free((yyvsp[(2) - (3)].string)); +} + break; + + case 49: + + { (yyval.string) = NULL; } + break; + + case 50: + + { (yyval.string) = (yyvsp[(2) - (2)].string); } + break; + + case 51: + + { + struct symbol *sym = sym_lookup((yyvsp[(2) - (3)].string), SYMBOL_CHOICE); + sym->flags |= SYMBOL_AUTO; + menu_add_entry(sym); + menu_add_expr(P_CHOICE, NULL, NULL); + printd(DEBUG_PARSE, "%s:%d:choice\n", zconf_curname(), zconf_lineno()); +} + break; + + case 52: + + { + (yyval.menu) = menu_add_menu(); +} + break; + + case 53: + + { + if (zconf_endtoken((yyvsp[(1) - (1)].id), T_CHOICE, T_ENDCHOICE)) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endchoice\n", zconf_curname(), zconf_lineno()); + } +} + break; + + case 61: + + { + menu_add_prompt(P_PROMPT, (yyvsp[(2) - (4)].string), (yyvsp[(3) - (4)].expr)); + printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno()); +} + break; + + case 62: + + { + if ((yyvsp[(1) - (3)].id)->stype == S_BOOLEAN || (yyvsp[(1) - (3)].id)->stype == S_TRISTATE) { + menu_set_type((yyvsp[(1) - (3)].id)->stype); + printd(DEBUG_PARSE, "%s:%d:type(%u)\n", + zconf_curname(), zconf_lineno(), + (yyvsp[(1) - (3)].id)->stype); + } else + YYERROR; +} + break; + + case 63: + + { + current_entry->sym->flags |= SYMBOL_OPTIONAL; + printd(DEBUG_PARSE, "%s:%d:optional\n", zconf_curname(), zconf_lineno()); +} + break; + + case 64: + + { + if ((yyvsp[(1) - (4)].id)->stype == S_UNKNOWN) { + menu_add_symbol(P_DEFAULT, sym_lookup((yyvsp[(2) - (4)].string), 0), (yyvsp[(3) - (4)].expr)); + printd(DEBUG_PARSE, "%s:%d:default\n", + zconf_curname(), zconf_lineno()); + } else + YYERROR; +} + break; + + case 67: + + { + printd(DEBUG_PARSE, "%s:%d:if\n", zconf_curname(), zconf_lineno()); + menu_add_entry(NULL); + menu_add_dep((yyvsp[(2) - (3)].expr)); + (yyval.menu) = menu_add_menu(); +} + break; + + case 68: + + { + if (zconf_endtoken((yyvsp[(1) - (1)].id), T_IF, T_ENDIF)) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endif\n", zconf_curname(), zconf_lineno()); + } +} + break; + + case 74: + + { + menu_add_prompt(P_MENU, (yyvsp[(2) - (3)].string), NULL); +} + break; + + case 75: + + { + menu_add_entry(NULL); + menu_add_prompt(P_MENU, (yyvsp[(2) - (3)].string), NULL); + printd(DEBUG_PARSE, "%s:%d:menu\n", zconf_curname(), zconf_lineno()); +} + break; + + case 76: + + { + (yyval.menu) = menu_add_menu(); +} + break; + + case 77: + + { + if (zconf_endtoken((yyvsp[(1) - (1)].id), T_MENU, T_ENDMENU)) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endmenu\n", zconf_curname(), zconf_lineno()); + } +} + break; + + case 83: + + { + printd(DEBUG_PARSE, "%s:%d:source %s\n", zconf_curname(), zconf_lineno(), (yyvsp[(2) - (3)].string)); + zconf_nextfile((yyvsp[(2) - (3)].string)); +} + break; + + case 84: + + { + menu_add_entry(NULL); + menu_add_prompt(P_COMMENT, (yyvsp[(2) - (3)].string), NULL); + printd(DEBUG_PARSE, "%s:%d:comment\n", zconf_curname(), zconf_lineno()); +} + break; + + case 85: + + { + menu_end_entry(); +} + break; + + case 86: + + { + printd(DEBUG_PARSE, "%s:%d:help\n", zconf_curname(), zconf_lineno()); + zconf_starthelp(); +} + break; + + case 87: + + { + current_entry->help = (yyvsp[(2) - (2)].string); +} + break; + + case 92: + + { + menu_add_dep((yyvsp[(3) - (4)].expr)); + printd(DEBUG_PARSE, "%s:%d:depends on\n", zconf_curname(), zconf_lineno()); +} + break; + + case 96: + + { + menu_add_visibility((yyvsp[(2) - (2)].expr)); +} + break; + + case 98: + + { + menu_add_prompt(P_PROMPT, (yyvsp[(1) - (2)].string), (yyvsp[(2) - (2)].expr)); +} + break; + + case 101: + + { (yyval.id) = (yyvsp[(1) - (2)].id); } + break; + + case 102: + + { (yyval.id) = (yyvsp[(1) - (2)].id); } + break; + + case 103: + + { (yyval.id) = (yyvsp[(1) - (2)].id); } + break; + + case 106: + + { (yyval.expr) = NULL; } + break; + + case 107: + + { (yyval.expr) = (yyvsp[(2) - (2)].expr); } + break; + + case 108: + + { (yyval.expr) = expr_alloc_symbol((yyvsp[(1) - (1)].symbol)); } + break; + + case 109: + + { (yyval.expr) = expr_alloc_comp(E_EQUAL, (yyvsp[(1) - (3)].symbol), (yyvsp[(3) - (3)].symbol)); } + break; + + case 110: + + { (yyval.expr) = expr_alloc_comp(E_UNEQUAL, (yyvsp[(1) - (3)].symbol), (yyvsp[(3) - (3)].symbol)); } + break; + + case 111: + + { (yyval.expr) = (yyvsp[(2) - (3)].expr); } + break; + + case 112: + + { (yyval.expr) = expr_alloc_one(E_NOT, (yyvsp[(2) - (2)].expr)); } + break; + + case 113: + + { (yyval.expr) = expr_alloc_two(E_OR, (yyvsp[(1) - (3)].expr), (yyvsp[(3) - (3)].expr)); } + break; + + case 114: + + { (yyval.expr) = expr_alloc_two(E_AND, (yyvsp[(1) - (3)].expr), (yyvsp[(3) - (3)].expr)); } + break; + + case 115: + + { (yyval.symbol) = sym_lookup((yyvsp[(1) - (1)].string), 0); free((yyvsp[(1) - (1)].string)); } + break; + + case 116: + + { (yyval.symbol) = sym_lookup((yyvsp[(1) - (1)].string), SYMBOL_CONST); free((yyvsp[(1) - (1)].string)); } + break; + + case 117: + + { (yyval.string) = NULL; } + break; + + + + default: break; + } + /* User semantic actions sometimes alter yychar, and that requires + that yytoken be updated with the new translation. We take the + approach of translating immediately before every use of yytoken. + One alternative is translating here after every semantic action, + but that translation would be missed if the semantic action invokes + YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or + if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an + incorrect destructor might then be invoked immediately. In the + case of YYERROR or YYBACKUP, subsequent parser actions might lead + to an incorrect destructor call or verbose syntax error message + before the lookahead is translated. */ + YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); + + YYPOPSTACK (yylen); + yylen = 0; + YY_STACK_PRINT (yyss, yyssp); + + *++yyvsp = yyval; + + /* Now `shift' the result of the reduction. Determine what state + that goes to, based on the state we popped back to and the rule + number reduced by. */ + + yyn = yyr1[yyn]; + + yystate = yypgoto[yyn - YYNTOKENS] + *yyssp; + if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp) + yystate = yytable[yystate]; + else + yystate = yydefgoto[yyn - YYNTOKENS]; + + goto yynewstate; + + +/*------------------------------------. +| yyerrlab -- here on detecting error | +`------------------------------------*/ +yyerrlab: + /* Make sure we have latest lookahead translation. See comments at + user semantic actions for why this is necessary. */ + yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar); + + /* If not already recovering from an error, report this error. */ + if (!yyerrstatus) + { + ++yynerrs; +#if ! YYERROR_VERBOSE + yyerror (YY_("syntax error")); +#else +# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \ + yyssp, yytoken) + { + char const *yymsgp = YY_("syntax error"); + int yysyntax_error_status; + yysyntax_error_status = YYSYNTAX_ERROR; + if (yysyntax_error_status == 0) + yymsgp = yymsg; + else if (yysyntax_error_status == 1) + { + if (yymsg != yymsgbuf) + YYSTACK_FREE (yymsg); + yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc); + if (!yymsg) + { + yymsg = yymsgbuf; + yymsg_alloc = sizeof yymsgbuf; + yysyntax_error_status = 2; + } + else + { + yysyntax_error_status = YYSYNTAX_ERROR; + yymsgp = yymsg; + } + } + yyerror (yymsgp); + if (yysyntax_error_status == 2) + goto yyexhaustedlab; + } +# undef YYSYNTAX_ERROR +#endif + } + + + + if (yyerrstatus == 3) + { + /* If just tried and failed to reuse lookahead token after an + error, discard it. */ + + if (yychar <= YYEOF) + { + /* Return failure if at end of input. */ + if (yychar == YYEOF) + YYABORT; + } + else + { + yydestruct ("Error: discarding", + yytoken, &yylval); + yychar = YYEMPTY; + } + } + + /* Else will try to reuse lookahead token after shifting the error + token. */ + goto yyerrlab1; + + +/*---------------------------------------------------. +| yyerrorlab -- error raised explicitly by YYERROR. | +`---------------------------------------------------*/ +yyerrorlab: + + /* Pacify compilers like GCC when the user code never invokes + YYERROR and the label yyerrorlab therefore never appears in user + code. */ + if (/*CONSTCOND*/ 0) + goto yyerrorlab; + + /* Do not reclaim the symbols of the rule which action triggered + this YYERROR. */ + YYPOPSTACK (yylen); + yylen = 0; + YY_STACK_PRINT (yyss, yyssp); + yystate = *yyssp; + goto yyerrlab1; + + +/*-------------------------------------------------------------. +| yyerrlab1 -- common code for both syntax error and YYERROR. | +`-------------------------------------------------------------*/ +yyerrlab1: + yyerrstatus = 3; /* Each real token shifted decrements this. */ + + for (;;) + { + yyn = yypact[yystate]; + if (!yypact_value_is_default (yyn)) + { + yyn += YYTERROR; + if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) + { + yyn = yytable[yyn]; + if (0 < yyn) + break; + } + } + + /* Pop the current state because it cannot handle the error token. */ + if (yyssp == yyss) + YYABORT; + + + yydestruct ("Error: popping", + yystos[yystate], yyvsp); + YYPOPSTACK (1); + yystate = *yyssp; + YY_STACK_PRINT (yyss, yyssp); + } + + *++yyvsp = yylval; + + + /* Shift the error token. */ + YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); + + yystate = yyn; + goto yynewstate; + + +/*-------------------------------------. +| yyacceptlab -- YYACCEPT comes here. | +`-------------------------------------*/ +yyacceptlab: + yyresult = 0; + goto yyreturn; + +/*-----------------------------------. +| yyabortlab -- YYABORT comes here. | +`-----------------------------------*/ +yyabortlab: + yyresult = 1; + goto yyreturn; + +#if !defined(yyoverflow) || YYERROR_VERBOSE +/*-------------------------------------------------. +| yyexhaustedlab -- memory exhaustion comes here. | +`-------------------------------------------------*/ +yyexhaustedlab: + yyerror (YY_("memory exhausted")); + yyresult = 2; + /* Fall through. */ +#endif + +yyreturn: + if (yychar != YYEMPTY) + { + /* Make sure we have latest lookahead translation. See comments at + user semantic actions for why this is necessary. */ + yytoken = YYTRANSLATE (yychar); + yydestruct ("Cleanup: discarding lookahead", + yytoken, &yylval); + } + /* Do not reclaim the symbols of the rule which action triggered + this YYABORT or YYACCEPT. */ + YYPOPSTACK (yylen); + YY_STACK_PRINT (yyss, yyssp); + while (yyssp != yyss) + { + yydestruct ("Cleanup: popping", + yystos[*yyssp], yyvsp); + YYPOPSTACK (1); + } +#ifndef yyoverflow + if (yyss != yyssa) + YYSTACK_FREE (yyss); +#endif +#if YYERROR_VERBOSE + if (yymsg != yymsgbuf) + YYSTACK_FREE (yymsg); +#endif + /* Make sure YYID is used. */ + return YYID (yyresult); +} + + + + + +void conf_parse(const char *name) +{ + struct symbol *sym; + int i; + + zconf_initscan(name); + + sym_init(); + _menu_init(); + rootmenu.prompt = menu_add_prompt(P_MENU, "Linux Kernel Configuration", NULL); + + if (getenv("ZCONF_DEBUG")) + zconfdebug = 1; + zconfparse(); + if (zconfnerrs) + exit(1); + if (!modules_sym) + modules_sym = sym_find( "n" ); + + rootmenu.prompt->text = _(rootmenu.prompt->text); + rootmenu.prompt->text = sym_expand_string_value(rootmenu.prompt->text); + + menu_finalize(&rootmenu); + for_all_symbols(i, sym) { + if (sym_check_deps(sym)) + zconfnerrs++; + } + if (zconfnerrs) + exit(1); + sym_set_change_count(1); +} + +static const char *zconf_tokenname(int token) +{ + switch (token) { + case T_MENU: return "menu"; + case T_ENDMENU: return "endmenu"; + case T_CHOICE: return "choice"; + case T_ENDCHOICE: return "endchoice"; + case T_IF: return "if"; + case T_ENDIF: return "endif"; + case T_DEPENDS: return "depends"; + case T_VISIBLE: return "visible"; + } + return ""; +} + +static bool zconf_endtoken(const struct kconf_id *id, int starttoken, int endtoken) +{ + if (id->token != endtoken) { + zconf_error("unexpected '%s' within %s block", + kconf_id_strings + id->name, zconf_tokenname(starttoken)); + zconfnerrs++; + return false; + } + if (current_menu->file != current_file) { + zconf_error("'%s' in different file than '%s'", + kconf_id_strings + id->name, zconf_tokenname(starttoken)); + fprintf(stderr, "%s:%d: location of the '%s'\n", + current_menu->file->name, current_menu->lineno, + zconf_tokenname(starttoken)); + zconfnerrs++; + return false; + } + return true; +} + +static void zconfprint(const char *err, ...) +{ + va_list ap; + + fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno()); + va_start(ap, err); + vfprintf(stderr, err, ap); + va_end(ap); + fprintf(stderr, "\n"); +} + +static void zconf_error(const char *err, ...) +{ + va_list ap; + + zconfnerrs++; + fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno()); + va_start(ap, err); + vfprintf(stderr, err, ap); + va_end(ap); + fprintf(stderr, "\n"); +} + +static void zconferror(const char *err) +{ + fprintf(stderr, "%s:%d: %s\n", zconf_curname(), zconf_lineno() + 1, err); +} + +static void print_quoted_string(FILE *out, const char *str) +{ + const char *p; + int len; + + putc('"', out); + while ((p = strchr(str, '"'))) { + len = p - str; + if (len) + fprintf(out, "%.*s", len, str); + fputs("\\\"", out); + str = p + 1; + } + fputs(str, out); + putc('"', out); +} + +static void print_symbol(FILE *out, struct menu *menu) +{ + struct symbol *sym = menu->sym; + struct property *prop; + + if (sym_is_choice(sym)) + fprintf(out, "\nchoice\n"); + else + fprintf(out, "\nconfig %s\n", sym->name); + switch (sym->type) { + case S_BOOLEAN: + fputs(" boolean\n", out); + break; + case S_TRISTATE: + fputs(" tristate\n", out); + break; + case S_STRING: + fputs(" string\n", out); + break; + case S_INT: + fputs(" integer\n", out); + break; + case S_HEX: + fputs(" hex\n", out); + break; + default: + fputs(" ???\n", out); + break; + } + for (prop = sym->prop; prop; prop = prop->next) { + if (prop->menu != menu) + continue; + switch (prop->type) { + case P_PROMPT: + fputs(" prompt ", out); + print_quoted_string(out, prop->text); + if (!expr_is_yes(prop->visible.expr)) { + fputs(" if ", out); + expr_fprint(prop->visible.expr, out); + } + fputc('\n', out); + break; + case P_DEFAULT: + fputs( " default ", out); + expr_fprint(prop->expr, out); + if (!expr_is_yes(prop->visible.expr)) { + fputs(" if ", out); + expr_fprint(prop->visible.expr, out); + } + fputc('\n', out); + break; + case P_CHOICE: + fputs(" #choice value\n", out); + break; + case P_SELECT: + fputs( " select ", out); + expr_fprint(prop->expr, out); + fputc('\n', out); + break; + case P_RANGE: + fputs( " range ", out); + expr_fprint(prop->expr, out); + fputc('\n', out); + break; + case P_MENU: + fputs( " menu ", out); + print_quoted_string(out, prop->text); + fputc('\n', out); + break; + default: + fprintf(out, " unknown prop %d!\n", prop->type); + break; + } + } + if (menu->help) { + int len = strlen(menu->help); + while (menu->help[--len] == '\n') + menu->help[len] = 0; + fprintf(out, " help\n%s\n", menu->help); + } +} + +void zconfdump(FILE *out) +{ + struct property *prop; + struct symbol *sym; + struct menu *menu; + + menu = rootmenu.list; + while (menu) { + if ((sym = menu->sym)) + print_symbol(out, menu); + else if ((prop = menu->prompt)) { + switch (prop->type) { + case P_COMMENT: + fputs("\ncomment ", out); + print_quoted_string(out, prop->text); + fputs("\n", out); + break; + case P_MENU: + fputs("\nmenu ", out); + print_quoted_string(out, prop->text); + fputs("\n", out); + break; + default: + ; + } + if (!expr_is_yes(prop->visible.expr)) { + fputs(" depends ", out); + expr_fprint(prop->visible.expr, out); + fputc('\n', out); + } + } + + if (menu->list) + menu = menu->list; + else if (menu->next) + menu = menu->next; + else while ((menu = menu->parent)) { + if (menu->prompt && menu->prompt->type == P_MENU) + fputs("\nendmenu\n", out); + if (menu->next) { + menu = menu->next; + break; + } + } + } +} + +#include "zconf.lex.c" +#include "util.c" +#include "confdata.c" +#include "expr.c" +#include "symbol.c" +#include "menu.c" + diff --git a/scripts/kconfig/zconf.y b/scripts/kconfig/zconf.y new file mode 100644 index 0000000000..0f683cfa53 --- /dev/null +++ b/scripts/kconfig/zconf.y @@ -0,0 +1,733 @@ +%{ +/* + * Copyright (C) 2002 Roman Zippel + * Released under the terms of the GNU GPL v2.0. + */ + +#include +#include +#include +#include +#include +#include + +#include "lkc.h" + +#define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt) + +#define PRINTD 0x0001 +#define DEBUG_PARSE 0x0002 + +int cdebug = PRINTD; + +extern int zconflex(void); +static void zconfprint(const char *err, ...); +static void zconf_error(const char *err, ...); +static void zconferror(const char *err); +static bool zconf_endtoken(const struct kconf_id *id, int starttoken, int endtoken); + +struct symbol *symbol_hash[SYMBOL_HASHSIZE]; + +static struct menu *current_menu, *current_entry; + +%} +%expect 30 + +%union +{ + char *string; + struct file *file; + struct symbol *symbol; + struct expr *expr; + struct menu *menu; + const struct kconf_id *id; +} + +%token T_MAINMENU +%token T_MENU +%token T_ENDMENU +%token T_SOURCE +%token T_CHOICE +%token T_ENDCHOICE +%token T_COMMENT +%token T_CONFIG +%token T_MENUCONFIG +%token T_HELP +%token T_HELPTEXT +%token T_IF +%token T_ENDIF +%token T_DEPENDS +%token T_OPTIONAL +%token T_PROMPT +%token T_TYPE +%token T_DEFAULT +%token T_SELECT +%token T_RANGE +%token T_VISIBLE +%token T_OPTION +%token T_ON +%token T_WORD +%token T_WORD_QUOTE +%token T_UNEQUAL +%token T_CLOSE_PAREN +%token T_OPEN_PAREN +%token T_EOL + +%left T_OR +%left T_AND +%left T_EQUAL T_UNEQUAL +%nonassoc T_NOT + +%type prompt +%type symbol +%type expr +%type if_expr +%type end +%type option_name +%type if_entry menu_entry choice_entry +%type symbol_option_arg word_opt + +%destructor { + fprintf(stderr, "%s:%d: missing end statement for this entry\n", + $$->file->name, $$->lineno); + if (current_menu == $$) + menu_end_menu(); +} if_entry menu_entry choice_entry + +%{ +/* Include zconf.hash.c here so it can see the token constants. */ +#include "zconf.hash.c" +%} + +%% +input: nl start | start; + +start: mainmenu_stmt stmt_list | stmt_list; + +stmt_list: + /* empty */ + | stmt_list common_stmt + | stmt_list choice_stmt + | stmt_list menu_stmt + | stmt_list end { zconf_error("unexpected end statement"); } + | stmt_list T_WORD error T_EOL { zconf_error("unknown statement \"%s\"", $2); } + | stmt_list option_name error T_EOL +{ + zconf_error("unexpected option \"%s\"", kconf_id_strings + $2->name); +} + | stmt_list error T_EOL { zconf_error("invalid statement"); } +; + +option_name: + T_DEPENDS | T_PROMPT | T_TYPE | T_SELECT | T_OPTIONAL | T_RANGE | T_DEFAULT | T_VISIBLE +; + +common_stmt: + T_EOL + | if_stmt + | comment_stmt + | config_stmt + | menuconfig_stmt + | source_stmt +; + +option_error: + T_WORD error T_EOL { zconf_error("unknown option \"%s\"", $1); } + | error T_EOL { zconf_error("invalid option"); } +; + + +/* config/menuconfig entry */ + +config_entry_start: T_CONFIG T_WORD T_EOL +{ + struct symbol *sym = sym_lookup($2, 0); + sym->flags |= SYMBOL_OPTIONAL; + menu_add_entry(sym); + printd(DEBUG_PARSE, "%s:%d:config %s\n", zconf_curname(), zconf_lineno(), $2); +}; + +config_stmt: config_entry_start config_option_list +{ + menu_end_entry(); + printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno()); +}; + +menuconfig_entry_start: T_MENUCONFIG T_WORD T_EOL +{ + struct symbol *sym = sym_lookup($2, 0); + sym->flags |= SYMBOL_OPTIONAL; + menu_add_entry(sym); + printd(DEBUG_PARSE, "%s:%d:menuconfig %s\n", zconf_curname(), zconf_lineno(), $2); +}; + +menuconfig_stmt: menuconfig_entry_start config_option_list +{ + if (current_entry->prompt) + current_entry->prompt->type = P_MENU; + else + zconfprint("warning: menuconfig statement without prompt"); + menu_end_entry(); + printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno()); +}; + +config_option_list: + /* empty */ + | config_option_list config_option + | config_option_list symbol_option + | config_option_list depends + | config_option_list help + | config_option_list option_error + | config_option_list T_EOL +; + +config_option: T_TYPE prompt_stmt_opt T_EOL +{ + menu_set_type($1->stype); + printd(DEBUG_PARSE, "%s:%d:type(%u)\n", + zconf_curname(), zconf_lineno(), + $1->stype); +}; + +config_option: T_PROMPT prompt if_expr T_EOL +{ + menu_add_prompt(P_PROMPT, $2, $3); + printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno()); +}; + +config_option: T_DEFAULT expr if_expr T_EOL +{ + menu_add_expr(P_DEFAULT, $2, $3); + if ($1->stype != S_UNKNOWN) + menu_set_type($1->stype); + printd(DEBUG_PARSE, "%s:%d:default(%u)\n", + zconf_curname(), zconf_lineno(), + $1->stype); +}; + +config_option: T_SELECT T_WORD if_expr T_EOL +{ + menu_add_symbol(P_SELECT, sym_lookup($2, 0), $3); + printd(DEBUG_PARSE, "%s:%d:select\n", zconf_curname(), zconf_lineno()); +}; + +config_option: T_RANGE symbol symbol if_expr T_EOL +{ + menu_add_expr(P_RANGE, expr_alloc_comp(E_RANGE,$2, $3), $4); + printd(DEBUG_PARSE, "%s:%d:range\n", zconf_curname(), zconf_lineno()); +}; + +symbol_option: T_OPTION symbol_option_list T_EOL +; + +symbol_option_list: + /* empty */ + | symbol_option_list T_WORD symbol_option_arg +{ + const struct kconf_id *id = kconf_id_lookup($2, strlen($2)); + if (id && id->flags & TF_OPTION) + menu_add_option(id->token, $3); + else + zconfprint("warning: ignoring unknown option %s", $2); + free($2); +}; + +symbol_option_arg: + /* empty */ { $$ = NULL; } + | T_EQUAL prompt { $$ = $2; } +; + +/* choice entry */ + +choice: T_CHOICE word_opt T_EOL +{ + struct symbol *sym = sym_lookup($2, SYMBOL_CHOICE); + sym->flags |= SYMBOL_AUTO; + menu_add_entry(sym); + menu_add_expr(P_CHOICE, NULL, NULL); + printd(DEBUG_PARSE, "%s:%d:choice\n", zconf_curname(), zconf_lineno()); +}; + +choice_entry: choice choice_option_list +{ + $$ = menu_add_menu(); +}; + +choice_end: end +{ + if (zconf_endtoken($1, T_CHOICE, T_ENDCHOICE)) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endchoice\n", zconf_curname(), zconf_lineno()); + } +}; + +choice_stmt: choice_entry choice_block choice_end +; + +choice_option_list: + /* empty */ + | choice_option_list choice_option + | choice_option_list depends + | choice_option_list help + | choice_option_list T_EOL + | choice_option_list option_error +; + +choice_option: T_PROMPT prompt if_expr T_EOL +{ + menu_add_prompt(P_PROMPT, $2, $3); + printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno()); +}; + +choice_option: T_TYPE prompt_stmt_opt T_EOL +{ + if ($1->stype == S_BOOLEAN || $1->stype == S_TRISTATE) { + menu_set_type($1->stype); + printd(DEBUG_PARSE, "%s:%d:type(%u)\n", + zconf_curname(), zconf_lineno(), + $1->stype); + } else + YYERROR; +}; + +choice_option: T_OPTIONAL T_EOL +{ + current_entry->sym->flags |= SYMBOL_OPTIONAL; + printd(DEBUG_PARSE, "%s:%d:optional\n", zconf_curname(), zconf_lineno()); +}; + +choice_option: T_DEFAULT T_WORD if_expr T_EOL +{ + if ($1->stype == S_UNKNOWN) { + menu_add_symbol(P_DEFAULT, sym_lookup($2, 0), $3); + printd(DEBUG_PARSE, "%s:%d:default\n", + zconf_curname(), zconf_lineno()); + } else + YYERROR; +}; + +choice_block: + /* empty */ + | choice_block common_stmt +; + +/* if entry */ + +if_entry: T_IF expr nl +{ + printd(DEBUG_PARSE, "%s:%d:if\n", zconf_curname(), zconf_lineno()); + menu_add_entry(NULL); + menu_add_dep($2); + $$ = menu_add_menu(); +}; + +if_end: end +{ + if (zconf_endtoken($1, T_IF, T_ENDIF)) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endif\n", zconf_curname(), zconf_lineno()); + } +}; + +if_stmt: if_entry if_block if_end +; + +if_block: + /* empty */ + | if_block common_stmt + | if_block menu_stmt + | if_block choice_stmt +; + +/* mainmenu entry */ + +mainmenu_stmt: T_MAINMENU prompt nl +{ + menu_add_prompt(P_MENU, $2, NULL); +}; + +/* menu entry */ + +menu: T_MENU prompt T_EOL +{ + menu_add_entry(NULL); + menu_add_prompt(P_MENU, $2, NULL); + printd(DEBUG_PARSE, "%s:%d:menu\n", zconf_curname(), zconf_lineno()); +}; + +menu_entry: menu visibility_list depends_list +{ + $$ = menu_add_menu(); +}; + +menu_end: end +{ + if (zconf_endtoken($1, T_MENU, T_ENDMENU)) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endmenu\n", zconf_curname(), zconf_lineno()); + } +}; + +menu_stmt: menu_entry menu_block menu_end +; + +menu_block: + /* empty */ + | menu_block common_stmt + | menu_block menu_stmt + | menu_block choice_stmt +; + +source_stmt: T_SOURCE prompt T_EOL +{ + printd(DEBUG_PARSE, "%s:%d:source %s\n", zconf_curname(), zconf_lineno(), $2); + zconf_nextfile($2); +}; + +/* comment entry */ + +comment: T_COMMENT prompt T_EOL +{ + menu_add_entry(NULL); + menu_add_prompt(P_COMMENT, $2, NULL); + printd(DEBUG_PARSE, "%s:%d:comment\n", zconf_curname(), zconf_lineno()); +}; + +comment_stmt: comment depends_list +{ + menu_end_entry(); +}; + +/* help option */ + +help_start: T_HELP T_EOL +{ + printd(DEBUG_PARSE, "%s:%d:help\n", zconf_curname(), zconf_lineno()); + zconf_starthelp(); +}; + +help: help_start T_HELPTEXT +{ + current_entry->help = $2; +}; + +/* depends option */ + +depends_list: + /* empty */ + | depends_list depends + | depends_list T_EOL + | depends_list option_error +; + +depends: T_DEPENDS T_ON expr T_EOL +{ + menu_add_dep($3); + printd(DEBUG_PARSE, "%s:%d:depends on\n", zconf_curname(), zconf_lineno()); +}; + +/* visibility option */ + +visibility_list: + /* empty */ + | visibility_list visible + | visibility_list T_EOL +; + +visible: T_VISIBLE if_expr +{ + menu_add_visibility($2); +}; + +/* prompt statement */ + +prompt_stmt_opt: + /* empty */ + | prompt if_expr +{ + menu_add_prompt(P_PROMPT, $1, $2); +}; + +prompt: T_WORD + | T_WORD_QUOTE +; + +end: T_ENDMENU T_EOL { $$ = $1; } + | T_ENDCHOICE T_EOL { $$ = $1; } + | T_ENDIF T_EOL { $$ = $1; } +; + +nl: + T_EOL + | nl T_EOL +; + +if_expr: /* empty */ { $$ = NULL; } + | T_IF expr { $$ = $2; } +; + +expr: symbol { $$ = expr_alloc_symbol($1); } + | symbol T_EQUAL symbol { $$ = expr_alloc_comp(E_EQUAL, $1, $3); } + | symbol T_UNEQUAL symbol { $$ = expr_alloc_comp(E_UNEQUAL, $1, $3); } + | T_OPEN_PAREN expr T_CLOSE_PAREN { $$ = $2; } + | T_NOT expr { $$ = expr_alloc_one(E_NOT, $2); } + | expr T_OR expr { $$ = expr_alloc_two(E_OR, $1, $3); } + | expr T_AND expr { $$ = expr_alloc_two(E_AND, $1, $3); } +; + +symbol: T_WORD { $$ = sym_lookup($1, 0); free($1); } + | T_WORD_QUOTE { $$ = sym_lookup($1, SYMBOL_CONST); free($1); } +; + +word_opt: /* empty */ { $$ = NULL; } + | T_WORD + +%% + +void conf_parse(const char *name) +{ + struct symbol *sym; + int i; + + zconf_initscan(name); + + sym_init(); + _menu_init(); + rootmenu.prompt = menu_add_prompt(P_MENU, "Linux Kernel Configuration", NULL); + + if (getenv("ZCONF_DEBUG")) + zconfdebug = 1; + zconfparse(); + if (zconfnerrs) + exit(1); + if (!modules_sym) + modules_sym = sym_find( "n" ); + + rootmenu.prompt->text = _(rootmenu.prompt->text); + rootmenu.prompt->text = sym_expand_string_value(rootmenu.prompt->text); + + menu_finalize(&rootmenu); + for_all_symbols(i, sym) { + if (sym_check_deps(sym)) + zconfnerrs++; + } + if (zconfnerrs) + exit(1); + sym_set_change_count(1); +} + +static const char *zconf_tokenname(int token) +{ + switch (token) { + case T_MENU: return "menu"; + case T_ENDMENU: return "endmenu"; + case T_CHOICE: return "choice"; + case T_ENDCHOICE: return "endchoice"; + case T_IF: return "if"; + case T_ENDIF: return "endif"; + case T_DEPENDS: return "depends"; + case T_VISIBLE: return "visible"; + } + return ""; +} + +static bool zconf_endtoken(const struct kconf_id *id, int starttoken, int endtoken) +{ + if (id->token != endtoken) { + zconf_error("unexpected '%s' within %s block", + kconf_id_strings + id->name, zconf_tokenname(starttoken)); + zconfnerrs++; + return false; + } + if (current_menu->file != current_file) { + zconf_error("'%s' in different file than '%s'", + kconf_id_strings + id->name, zconf_tokenname(starttoken)); + fprintf(stderr, "%s:%d: location of the '%s'\n", + current_menu->file->name, current_menu->lineno, + zconf_tokenname(starttoken)); + zconfnerrs++; + return false; + } + return true; +} + +static void zconfprint(const char *err, ...) +{ + va_list ap; + + fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno()); + va_start(ap, err); + vfprintf(stderr, err, ap); + va_end(ap); + fprintf(stderr, "\n"); +} + +static void zconf_error(const char *err, ...) +{ + va_list ap; + + zconfnerrs++; + fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno()); + va_start(ap, err); + vfprintf(stderr, err, ap); + va_end(ap); + fprintf(stderr, "\n"); +} + +static void zconferror(const char *err) +{ + fprintf(stderr, "%s:%d: %s\n", zconf_curname(), zconf_lineno() + 1, err); +} + +static void print_quoted_string(FILE *out, const char *str) +{ + const char *p; + int len; + + putc('"', out); + while ((p = strchr(str, '"'))) { + len = p - str; + if (len) + fprintf(out, "%.*s", len, str); + fputs("\\\"", out); + str = p + 1; + } + fputs(str, out); + putc('"', out); +} + +static void print_symbol(FILE *out, struct menu *menu) +{ + struct symbol *sym = menu->sym; + struct property *prop; + + if (sym_is_choice(sym)) + fprintf(out, "\nchoice\n"); + else + fprintf(out, "\nconfig %s\n", sym->name); + switch (sym->type) { + case S_BOOLEAN: + fputs(" boolean\n", out); + break; + case S_TRISTATE: + fputs(" tristate\n", out); + break; + case S_STRING: + fputs(" string\n", out); + break; + case S_INT: + fputs(" integer\n", out); + break; + case S_HEX: + fputs(" hex\n", out); + break; + default: + fputs(" ???\n", out); + break; + } + for (prop = sym->prop; prop; prop = prop->next) { + if (prop->menu != menu) + continue; + switch (prop->type) { + case P_PROMPT: + fputs(" prompt ", out); + print_quoted_string(out, prop->text); + if (!expr_is_yes(prop->visible.expr)) { + fputs(" if ", out); + expr_fprint(prop->visible.expr, out); + } + fputc('\n', out); + break; + case P_DEFAULT: + fputs( " default ", out); + expr_fprint(prop->expr, out); + if (!expr_is_yes(prop->visible.expr)) { + fputs(" if ", out); + expr_fprint(prop->visible.expr, out); + } + fputc('\n', out); + break; + case P_CHOICE: + fputs(" #choice value\n", out); + break; + case P_SELECT: + fputs( " select ", out); + expr_fprint(prop->expr, out); + fputc('\n', out); + break; + case P_RANGE: + fputs( " range ", out); + expr_fprint(prop->expr, out); + fputc('\n', out); + break; + case P_MENU: + fputs( " menu ", out); + print_quoted_string(out, prop->text); + fputc('\n', out); + break; + default: + fprintf(out, " unknown prop %d!\n", prop->type); + break; + } + } + if (menu->help) { + int len = strlen(menu->help); + while (menu->help[--len] == '\n') + menu->help[len] = 0; + fprintf(out, " help\n%s\n", menu->help); + } +} + +void zconfdump(FILE *out) +{ + struct property *prop; + struct symbol *sym; + struct menu *menu; + + menu = rootmenu.list; + while (menu) { + if ((sym = menu->sym)) + print_symbol(out, menu); + else if ((prop = menu->prompt)) { + switch (prop->type) { + case P_COMMENT: + fputs("\ncomment ", out); + print_quoted_string(out, prop->text); + fputs("\n", out); + break; + case P_MENU: + fputs("\nmenu ", out); + print_quoted_string(out, prop->text); + fputs("\n", out); + break; + default: + ; + } + if (!expr_is_yes(prop->visible.expr)) { + fputs(" depends ", out); + expr_fprint(prop->visible.expr, out); + fputc('\n', out); + } + } + + if (menu->list) + menu = menu->list; + else if (menu->next) + menu = menu->next; + else while ((menu = menu->parent)) { + if (menu->prompt && menu->prompt->type == P_MENU) + fputs("\nendmenu\n", out); + if (menu->next) { + menu = menu->next; + break; + } + } + } +} + +#include "zconf.lex.c" +#include "util.c" +#include "confdata.c" +#include "expr.c" +#include "symbol.c" +#include "menu.c" diff --git a/tools/kernel-doc/kernel-doc b/scripts/kernel-doc similarity index 96% rename from tools/kernel-doc/kernel-doc rename to scripts/kernel-doc index 6347418904..08a6c76845 100755 --- a/tools/kernel-doc/kernel-doc +++ b/scripts/kernel-doc @@ -137,6 +137,8 @@ use strict; # should document the "Context:" of the function, e.g. whether the functions # can be called form interrupts. Unlike other sections you can end it with an # empty line. +# A non-void function should have a "Return:" section describing the return +# value(s). # Example-sections should contain the string EXAMPLE so that they are marked # appropriately in DocBook. # @@ -245,6 +247,7 @@ my $dohighlight = ""; my $verbose = 0; my $output_mode = "man"; +my $output_preformatted = 0; my $no_doc_sections = 0; my %highlights = %highlights_man; my $blankline = $blankline_man; @@ -254,6 +257,7 @@ my $man_date = ('January', 'February', 'March', 'April', 'May', 'June', 'July', 'August', 'September', 'October', 'November', 'December')[(localtime)[4]] . " " . ((localtime)[5]+1900); +my $show_not_found = 0; # Essentially these are globals. # They probably want to be tidied up, made more localised or something. @@ -295,9 +299,10 @@ my $doc_special = "\@\%\$\&"; my $doc_start = '^/\*\*\s*$'; # Allow whitespace at end of comment start. my $doc_end = '\*/'; my $doc_com = '\s*\*\s*'; +my $doc_com_body = '\s*\* ?'; my $doc_decl = $doc_com . '(\w+)'; my $doc_sect = $doc_com . '([' . $doc_special . ']?[\w\s]+):(.*)'; -my $doc_content = $doc_com . '(.*)'; +my $doc_content = $doc_com_body . '(.*)'; my $doc_block = $doc_com . 'DOC:\s*(.*)?'; my %constants; @@ -313,6 +318,7 @@ my $section_default = "Description"; # default section my $section_intro = "Introduction"; my $section = $section_default; my $section_context = "Context"; +my $section_return = "Return"; my $undescribed = "-- undescribed --"; @@ -364,6 +370,8 @@ while ($ARGV[0] =~ m/^-(.*)/) { usage(); } elsif ($cmd eq '-no-doc-sections') { $no_doc_sections = 1; + } elsif ($cmd eq '-show-not-found') { + $show_not_found = 1; } } @@ -384,8 +392,8 @@ sub usage { sub get_kernel_version() { my $version = 'unknown kernel version'; - if (defined($ENV{'U_BOOT_VERSION'})) { - $version = $ENV{'U_BOOT_VERSION'}; + if (defined($ENV{'UBOOTVERSION'})) { + $version = $ENV{'UBOOTVERSION'}; } return $version; } @@ -485,8 +493,13 @@ sub output_highlight { $contents =~ s/\s+$//; } foreach $line (split "\n", $contents) { + if (! $output_preformatted) { + $line =~ s/^\s*//; + } if ($line eq ""){ - print $lineprefix, local_unescape($blankline); + if (! $output_preformatted) { + print $lineprefix, local_unescape($blankline); + } } else { $line =~ s/\\\\\\/\&/g; if ($output_mode eq "man" && substr($line, 0, 1) eq ".") { @@ -902,10 +915,12 @@ sub output_section_xml(%) { print "$section\n"; if ($section =~ m/EXAMPLE/i) { print "\n"; + $output_preformatted = 1; } else { print "\n"; } output_highlight($args{'sections'}{$section}); + $output_preformatted = 0; if ($section =~ m/EXAMPLE/i) { print "\n"; } else { @@ -1208,10 +1223,12 @@ sub output_blockhead_xml(%) { } if ($section =~ m/EXAMPLE/i) { print "\n"; + $output_preformatted = 1; } else { print "\n"; } output_highlight($args{'sections'}{$section}); + $output_preformatted = 0; if ($section =~ m/EXAMPLE/i) { print "\n"; } else { @@ -1287,10 +1304,12 @@ sub output_function_gnome { print "\n $section\n"; if ($section =~ m/EXAMPLE/i) { print "\n"; + $output_preformatted = 1; } else { } print "\n"; output_highlight($args{'sections'}{$section}); + $output_preformatted = 0; print "\n"; if ($section =~ m/EXAMPLE/i) { print "\n"; @@ -1734,7 +1753,7 @@ sub dump_struct($$) { # strip kmemcheck_bitfield_{begin,end}.*; $members =~ s/kmemcheck_bitfield_.*?;//gos; # strip attributes - $members =~ s/__aligned\s*\(\d+\)//gos; + $members =~ s/__aligned\s*\(.+\)//gos; create_parameterlist($members, ';', $file); check_sections($file, $declaration_name, "struct", $sectcheck, $struct_actual, $nested); @@ -2025,6 +2044,28 @@ sub check_sections($$$$$$) { } } +## +# Checks the section describing the return value of a function. +sub check_return_section { + my $file = shift; + my $declaration_name = shift; + my $return_type = shift; + + # Ignore an empty return type (It's a macro) + # Ignore functions with a "void" return type. (But don't ignore "void *") + if (($return_type eq "") || ($return_type =~ /void\s*\w*\s*$/)) { + return; + } + + if (!defined($sections{$section_return}) || + $sections{$section_return} eq "") { + print STDERR "Warning(${file}:$.): " . + "No description found for return value of " . + "'$declaration_name'\n"; + ++$warnings; + } +} + ## # takes a function prototype and the name of the current file being # processed and spits out all the details stored in the global @@ -2032,6 +2073,7 @@ sub check_sections($$$$$$) { sub dump_function($$) { my $prototype = shift; my $file = shift; + my $noret = 0; $prototype =~ s/^static +//; $prototype =~ s/^extern +//; @@ -2041,12 +2083,12 @@ sub dump_function($$) { $prototype =~ s/^__inline +//; $prototype =~ s/^__always_inline +//; $prototype =~ s/^noinline +//; - $prototype =~ s/__devinit +//; $prototype =~ s/__init +//; $prototype =~ s/__init_or_module +//; + $prototype =~ s/__meminit +//; $prototype =~ s/__must_check +//; $prototype =~ s/__weak +//; - $prototype =~ s/^#\s*define\s+//; #ak added + my $define = $prototype =~ s/^#\s*define\s+//; #ak added $prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//; # Yes, this truly is vile. We are looking for: @@ -2065,7 +2107,15 @@ sub dump_function($$) { # - atomic_set (macro) # - pci_match_device, __copy_to_user (long return type) - if ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + if ($define && $prototype =~ m/^()([a-zA-Z0-9_~:]+)\s+/) { + # This is an object-like macro, it has no return type and no parameter + # list. + # Function-like macros are not allowed to have spaces between + # declaration_name and opening parenthesis (notice the \s+). + $return_type = $1; + $declaration_name = $2; + $noret = 1; + } elsif ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || $prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || $prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || $prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || @@ -2088,14 +2138,22 @@ sub dump_function($$) { create_parameterlist($args, ',', $file); } else { - print STDERR "Error(${file}:$.): cannot understand prototype: '$prototype'\n"; - ++$errors; + print STDERR "Warning(${file}:$.): cannot understand function prototype: '$prototype'\n"; return; } my $prms = join " ", @parameterlist; check_sections($file, $declaration_name, "function", $sectcheck, $prms, ""); + # This check emits a lot of warnings at the moment, because many + # functions don't have a 'Return' doc section. So until the number + # of warnings goes sufficiently down, the check is only performed in + # verbose mode. + # TODO: always perform the check. + if ($verbose && !$noret) { + check_return_section($file, $declaration_name, $return_type); + } + output_declaration($declaration_name, 'function', {'function' => $declaration_name, @@ -2305,6 +2363,9 @@ sub process_file($) { $section_counter = 0; while () { + while (s/\\\s*$//) { + $_ .= ; + } if ($state == 0) { if (/$doc_start/o) { $state = 1; # next line is always the function name @@ -2332,7 +2393,7 @@ sub process_file($) { $descr= $1; $descr =~ s/^\s*//; $descr =~ s/\s*$//; - $descr =~ s/\s+/ /; + $descr =~ s/\s+/ /g; $declaration_purpose = xml_escape($descr); $in_purpose = 1; } else { @@ -2424,9 +2485,7 @@ sub process_file($) { # Continued declaration purpose chomp($declaration_purpose); $declaration_purpose .= " " . xml_escape($1); - } elsif ($section =~ m/^Example/) { - $_ =~ s/^\s*\*//; - $contents .= $_; + $declaration_purpose =~ s/\s+/ /g; } else { $contents .= $1 . "\n"; } @@ -2489,6 +2548,9 @@ sub process_file($) { } if ($initial_section_counter == $section_counter) { print STDERR "Warning(${file}): no structured comments found\n"; + if (($function_only == 1) && ($show_not_found == 1)) { + print STDERR " Was looking for '$_'.\n" for keys %function_table; + } if ($output_mode eq "xml") { # The template wants at least one RefEntry here; make one. print "\n"; diff --git a/scripts/ld-version.sh b/scripts/ld-version.sh new file mode 100755 index 0000000000..198580d245 --- /dev/null +++ b/scripts/ld-version.sh @@ -0,0 +1,8 @@ +#!/usr/bin/awk -f +# extract linker version number from stdin and turn into single number + { + gsub(".*)", ""); + split($1,a, "."); + print a[1]*10000000 + a[2]*100000 + a[3]*10000 + a[4]*100 + a[5]; + exit + } diff --git a/scripts/mailmapper b/scripts/mailmapper new file mode 100755 index 0000000000..922ada6f5f --- /dev/null +++ b/scripts/mailmapper @@ -0,0 +1,159 @@ +#!/usr/bin/env python +# +# Copyright (C) 2014, Masahiro Yamada +# +# SPDX-License-Identifier: GPL-2.0+ +# + +''' +A tool to create/update the mailmap file + +The command 'git shortlog' summarizes git log output in a format suitable +for inclusion in release announcements. Each commit will be grouped by +author and title. + +One problem is that the authors' name and/or email address is sometimes +spelled differently. The .mailmap feature can be used to coalesce together +commits by the same persion. +(See 'man git-shortlog' for furthur information of this feature.) + +This tool helps to create/update the mailmap file. + +It runs 'git shortlog' internally and searches differently spelled author +names which share the same email address. The author name with the most +commits is asuumed to be a canonical real name. If the number of commits +from the cananonical name is equal to or greater than 'MIN_COMMITS', +the entry for the cananical name will be output. ('MIN_COMMITS' is used +here because we do not want to create a fat mailmap by adding every author +with only a few commits.) + +If there exists a mailmap file specified by the mailmap.file configuration +options or '.mailmap' at the toplevel of the repository, it is used as +a base file. (The mailmap.file configuration takes precedence over the +'.mailmap' file if both exist.) + +The base file and the newly added entries are merged together and sorted +alphabetically (but the comment block is kept untouched), and then printed +to standard output. + +Usage +----- + + scripts/mailmapper + +prints the mailmapping to standard output. + + scripts/mailmapper > tmp; mv tmp .mailmap + +will be useful for updating '.mailmap' file. +''' + +import sys +import os +import subprocess + +# The entries only for the canonical names with MIN_COMMITS or more commits. +# This limitation is used so as not to create a too big mailmap file. +MIN_COMMITS = 50 + +try: + toplevel = subprocess.check_output(['git', 'rev-parse', '--show-toplevel']) +except subprocess.CalledProcessError: + sys.exit('Please run in a git repository.') + +# strip '\n' +toplevel = toplevel.rstrip() + +# Change the current working directory to the toplevel of the respository +# for our easier life. +os.chdir(toplevel) + +# First, create 'auther name' vs 'number of commits' database. +# We assume the name with the most commits as the canonical real name. +shortlog = subprocess.check_output(['git', 'shortlog', '-s', '-n']) + +commits_per_name = {} + +for line in shortlog.splitlines(): + try: + commits, name = line.split(None, 1) + except ValueError: + # ignore lines with an empty author name + pass + commits_per_name[name] = int(commits) + +# Next, coalesce the auther names with the same email address +shortlog = subprocess.check_output(['git', 'shortlog', '-s', '-n', '-e']) + +mail_vs_name = {} +output = {} + +for line in shortlog.splitlines(): + # tmp, mail = line.rsplit(None, 1) is not safe + # because weird email addresses might include whitespaces + tmp, mail = line.split('<') + mail = '<' + mail.rstrip() + try: + _, name = tmp.rstrip().split(None, 1) + except ValueError: + # author name is empty + name = '' + if mail in mail_vs_name: + # another name for the same email address + prev_name = mail_vs_name[mail] + # Take the name with more commits + major_name = sorted([prev_name, name], + key=lambda x: commits_per_name[x] if x else 0)[1] + mail_vs_name[mail] = major_name + if commits_per_name[major_name] > MIN_COMMITS: + output[mail] = major_name + else: + mail_vs_name[mail] = name + +# [1] If there exists a mailmap file at the location pointed to +# by the mailmap.file configuration option, update it. +# [2] If the file .mailmap exists at the toplevel of the repository, update it. +# [3] Otherwise, create a new mailmap file. +mailmap_files = [] + +try: + config_mailmap = subprocess.check_output(['git', 'config', 'mailmap.file']) +except subprocess.CalledProcessError: + config_mailmap = '' + +config_mailmap = config_mailmap.rstrip() +if config_mailmap: + mailmap_files.append(config_mailmap) + +mailmap_files.append('.mailmap') + +infile = None + +for map_file in mailmap_files: + try: + infile = open(map_file) + except: + # Failed to open. Try next. + continue + break + +comment_block = [] +output_lines = [] + +if infile: + for line in infile: + if line[0] == '#' or line[0] == '\n': + comment_block.append(line) + else: + output_lines.append(line) + break + for line in infile: + output_lines.append(line) + infile.close() + +for mail, name in output.items(): + output_lines.append(name + ' ' + mail + '\n') + +output_lines.sort() + +sys.stdout.write(''.join(comment_block + output_lines)) diff --git a/scripts/mkmakefile b/scripts/mkmakefile new file mode 100755 index 0000000000..84af27bf0f --- /dev/null +++ b/scripts/mkmakefile @@ -0,0 +1,52 @@ +#!/bin/sh +# Generates a small Makefile used in the root of the output +# directory, to allow make to be started from there. +# The Makefile also allow for more convinient build of external modules + +# Usage +# $1 - Kernel src directory +# $2 - Output directory +# $3 - version +# $4 - patchlevel + + +test ! -r $2/Makefile -o -O $2/Makefile || exit 0 +# Only overwrite automatically generated Makefiles +# (so we do not overwrite kernel Makefile) +if test -e $2/Makefile && ! grep -q Automatically $2/Makefile +then + exit 0 +fi +if [ "${quiet}" != "silent_" ]; then + echo " GEN $2/Makefile" +fi + +cat << EOF > $2/Makefile +# Automatically generated by $0: don't edit + +VERSION = $3 +PATCHLEVEL = $4 + +lastword = \$(word \$(words \$(1)),\$(1)) +makedir := \$(dir \$(call lastword,\$(MAKEFILE_LIST))) + +ifeq ("\$(origin V)", "command line") +VERBOSE := \$(V) +endif +ifneq (\$(VERBOSE),1) +Q := @ +endif + +MAKEARGS := -C $1 +MAKEARGS += O=\$(if \$(patsubst /%,,\$(makedir)),\$(CURDIR)/)\$(patsubst %/,%,\$(makedir)) + +MAKEFLAGS += --no-print-directory + +.PHONY: __sub-make \$(MAKECMDGOALS) + +__sub-make: + \$(Q)\$(MAKE) \$(MAKEARGS) \$(MAKECMDGOALS) + +\$(filter-out __sub-make, \$(MAKECMDGOALS)): __sub-make + @: +EOF diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh new file mode 100755 index 0000000000..366e8faaa6 --- /dev/null +++ b/scripts/multiconfig.sh @@ -0,0 +1,349 @@ +#!/bin/sh +# +# A wrapper script to adjust Kconfig for U-Boot +# +# Instead of touching various parts under the scripts/kconfig/ directory, +# pushing necessary adjustments into this single script would be better +# for code maintainance. All the make targets related to the configuration +# (make %config) should be invoked via this script. +# See doc/README.kconfig for further information of Kconfig. +# +# Copyright (C) 2014, Masahiro Yamada +# +# SPDX-License-Identifier: GPL-2.0+ +# + +set -e + +# Set "DEBUG" enavironment variable to show debug messages +debug () { + if [ $DEBUG ]; then + echo "$@" + fi +} + +# Useful shorthands +build () { + debug $progname: $MAKE -f $srctree/scripts/Makefile.build obj="$@" + $MAKE -f $srctree/scripts/Makefile.build obj="$@" +} + +autoconf () { + debug $progname: $MAKE -f $srctree/scripts/Makefile.autoconf obj="$@" + $MAKE -f $srctree/scripts/Makefile.autoconf obj="$@" +} + +# Make a configuration target +# Usage: +# run_make_config +# : Make target such as "config", "menuconfig", "defconfig", etc. +# : Target directory where the make command is run. +# Typically "", "spl", "tpl" for Normal, SPL, TPL, respectively. +run_make_config () { + target=$1 + objdir=$2 + + # Linux expects defconfig files in arch/$(SRCARCH)/configs/ directory, + # but U-Boot has them in configs/ directory. + # Give SRCARCH=.. to fake scripts/kconfig/Makefile. + options="SRCARCH=.. KCONFIG_OBJDIR=$objdir" + if [ "$objdir" ]; then + options="$options KCONFIG_CONFIG=$objdir/$KCONFIG_CONFIG" + mkdir -p $objdir + fi + + build scripts/kconfig $options $target +} + +# Parse .config file to detect if CONFIG_SPL, CONFIG_TPL is enabled +# and returns: +# "" if neither CONFIG_SPL nor CONFIG_TPL is defined +# "spl" if CONFIG_SPL is defined but CONFIG_TPL is not +# "spl tpl" if both CONFIG_SPL and CONFIG_TPL are defined +get_enabled_subimages() { + if [ ! -r "$KCONFIG_CONFIG" ]; then + # This should never happen + echo "$progname: $KCONFIG_CONFIG not found" >&2 + exit 1 + fi + + # CONFIG_SPL=y -> spl + # CONFIG_TPL=y -> tpl + sed -n -e 's/^CONFIG_SPL=y$/spl/p' -e 's/^CONFIG_TPL=y$/tpl/p' \ + $KCONFIG_CONFIG +} + +do_silentoldconfig () { + run_make_config silentoldconfig + subimages=$(get_enabled_subimages) + + for obj in $subimages + do + mkdir -p $obj/include/config $obj/include/generated + run_make_config silentoldconfig $obj + done + + # If the following part fails, include/config/auto.conf should be + # deleted so "make silentoldconfig" will be re-run on the next build. + autoconf include include/autoconf.mk include/autoconf.mk.dep || { + rm -f include/config/auto.conf + exit 1 + } + + # include/config.h has been updated after "make silentoldconfig". + # We need to touch include/config/auto.conf so it gets newer + # than include/config.h. + # Otherwise, 'make silentoldconfig' would be invoked twice. + touch include/config/auto.conf + + for obj in $subimages + do + autoconf $obj/include $obj/include/autoconf.mk || { + rm -f include/config/auto.conf + exit 1 + } + done +} + +cleanup_after_defconfig () { + rm -f configs/.tmp_defconfig + # ignore 'Directory not empty' error + # without using non-POSIX option '--ignore-fail-on-non-empty' + rmdir arch configs 2>/dev/null || true +} + +# Usage: +# do_board_defconfig _defconfig +do_board_defconfig () { + defconfig_path=$srctree/configs/$1 + tmp_defconfig_path=configs/.tmp_defconfig + + if [ ! -r $defconfig_path ]; then + echo >&2 "***" + echo >&2 "*** Can't find default configuration \"configs/$1\"!" + echo >&2 "***" + exit 1 + fi + + mkdir -p arch configs + # defconfig for Normal: + # pick lines without prefixes and lines starting '+' prefix + # and rip the prefixes off. + sed -n -e '/^[+A-Z]*:/!p' -e 's/^+[A-Z]*://p' $defconfig_path \ + > configs/.tmp_defconfig + + run_make_config .tmp_defconfig || { + cleanup_after_defconfig + exit 1 + } + + for img in $(get_enabled_subimages) + do + symbol=$(echo $img | cut -c 1 | tr '[a-z]' '[A-Z]') + # defconfig for SPL, TPL: + # pick lines with 'S', 'T' prefix and rip the prefixes off + sed -n -e 's/^[+A-Z]*'$symbol'[A-Z]*://p' $defconfig_path \ + > configs/.tmp_defconfig + run_make_config .tmp_defconfig $img || { + cleanup_after_defconfig + exit 1 + } + done + + cleanup_after_defconfig +} + +do_defconfig () { + if [ "$KBUILD_DEFCONFIG" ]; then + do_board_defconfig $KBUILD_DEFCONFIG + echo "*** Default configuration is based on '$KBUILD_DEFCONFIG'" + else + run_make_config defconfig + fi +} + +do_board_felconfig () { + do_board_defconfig ${1%%_felconfig}_defconfig + if ! grep -q CONFIG_ARCH_SUNXI=y .config || ! grep -q CONFIG_SPL=y .config ; then + echo "$progname: Cannot felconfig a non-sunxi or non-SPL platform" >&2 + exit 1 + fi + sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y\nCONFIG_UART0_PORT_F=n/g' \ + .config spl/.config +} + +do_savedefconfig () { + if [ -r "$KCONFIG_CONFIG" ]; then + subimages=$(get_enabled_subimages) + else + subimages= + fi + + run_make_config savedefconfig + + output_lines= + + # -r option is necessay because some string-type configs may include + # backslashes as an escape character + while read -r line + do + output_lines="$output_lines%$line" + done < defconfig + + for img in $subimages + do + run_make_config savedefconfig $img + + symbol=$(echo $img | cut -c 1 | tr '[a-z]' '[A-Z]') + unmatched= + + while read -r line + do + tmp= + match= + + # "# CONFIG_FOO is not set" should not be divided. + # Use "%" as a separator, instead of a whitespace. + # "%" is unlikely to appear in defconfig context. + save_IFS=$IFS + IFS=% + # coalesce common lines together + for i in $output_lines + do + case "$i" in + [+A-Z]*:$line) + tmp="$tmp%$unmatched" + i=$(echo "$i" | \ + sed -e "s/^\([^:]*\)/\1$symbol/") + tmp="$tmp%$i" + match=1 + ;; + $line) + tmp="$tmp%$unmatched" + tmp="$tmp%+$symbol:$i" + match=1 + ;; + *) + tmp="$tmp%$i" + ;; + esac + done + + # Restore the default separator for the outer for loop. + IFS=$save_IFS + + if [ "$match" ]; then + output_lines="$tmp" + unmatched= + else + unmatched="$unmatched%$symbol:$line" + fi + done < defconfig + + output_lines="$output_lines%$unmatched" + done + + rm -f defconfig + touch defconfig + + save_IFS=$IFS + IFS=% + + for line in $output_lines + do + case "$line" in + "") + # do not output blank lines + ;; + *) + echo $line >> defconfig + ;; + esac + done + + IFS=$save_IFS +} + +# Some sanity checks before running "make /", +# where should be either "spl" or "tpl". +# Doing "make spl/menuconfig" etc. on a non-SPL board makes no sense. +# It should be allowed only when ".config" exists and "CONFIG_SPL" is enabled. +# +# Usage: +# check_enabled_sumbimage / +check_enabled_subimage () { + + case $2 in + spl|tpl) ;; + *) + echo >&2 "***" + echo >&2 "*** \"make $1\" is not supported." + echo >&2 "***" + exit 1 + ;; + esac + test -r "$KCONFIG_CONFIG" && get_enabled_subimages | grep -q $2 || { + config=CONFIG_$(echo $2 | tr '[a-z]' '[A-Z]') + + echo >&2 "***" + echo >&2 "*** Create \"$KCONFIG_CONFIG\" with \"$config\" enabled" + echo >&2 "*** before \"make $1\"." + echo >&2 "***" + exit 1 + } +} + +# Usage: +# do_others / +# The field "/" is typically empy, "spl/", "tpl/" for Normal, SPL, TPL, +# respectively. +# The field "" is a configuration target such as "config", +# "menuconfig", etc. +do_others () { + target=${1##*/} + + if [ "$target" = "$1" ]; then + objdir= + else + objdir=${1%/*} + check_enabled_subimage $1 $objdir + + if [ -f "$objdir/$KCONFIG_CONFIG" ]; then + timestamp_before=$(stat --printf="%Y" \ + $objdir/$KCONFIG_CONFIG) + fi + fi + + run_make_config $target $objdir + + if [ "$timestamp_before" -a -f "$objdir/$KCONFIG_CONFIG" ]; then + timestamp_after=$(stat --printf="%Y" $objdir/$KCONFIG_CONFIG) + + if [ "$timestamp_after" -gt "$timestamp_before" ]; then + # $objdir/.config has been updated. + # touch .config to invoke "make silentoldconfig" + touch $KCONFIG_CONFIG + fi + fi +} + +progname=$(basename $0) +target=$1 + +case $target in +*_defconfig) + do_board_defconfig $target;; +*_felconfig) + do_board_felconfig $target;; +*_config) + # backward compatibility + do_board_defconfig ${target%_config}_defconfig;; +silentoldconfig) + do_silentoldconfig;; +defconfig) + do_defconfig;; +savedefconfig) + do_savedefconfig;; +*) + do_others $target;; +esac diff --git a/scripts/objdiff b/scripts/objdiff new file mode 100755 index 0000000000..62e51dae21 --- /dev/null +++ b/scripts/objdiff @@ -0,0 +1,159 @@ +#!/bin/bash + +# objdiff - a small script for validating that a commit or series of commits +# didn't change object code. +# +# Copyright 2014, Jason Cooper +# +# Licensed under the terms of the GNU GPL version 2 + +# usage example: +# +# $ git checkout COMMIT_A +# $ +# $ ./scripts/objdiff record path/to/*.o +# +# $ git checkout COMMIT_B +# $ +# $ ./scripts/objdiff record path/to/*.o +# +# $ ./scripts/objdiff diff COMMIT_A COMMIT_B +# $ + +# And to clean up (everything is in .tmp_objdiff/*) +# $ ./scripts/objdiff clean all +# +# Note: 'make mrproper' will also remove .tmp_objdiff + +SRCTREE=$(cd $(git rev-parse --show-toplevel 2>/dev/null); pwd) + +if [ -z "$SRCTREE" ]; then + echo >&2 "ERROR: Not a git repository." + exit 1 +fi + +TMPD=$SRCTREE/.tmp_objdiff + +usage() { + echo >&2 "Usage: $0 " + echo >&2 " record " + echo >&2 " diff " + echo >&2 " clean all | " + exit 1 +} + +get_output_dir() { + dir=${1%/*} + + if [ "$dir" = "$1" ]; then + dir=. + fi + + dir=$(cd $dir; pwd) + + echo $TMPD/$CMT${dir#$SRCTREE} +} + +do_objdump() { + dir=$(get_output_dir $1) + base=${1##*/} + dis=$dir/${base%.o}.dis + + [ ! -d "$dir" ] && mkdir -p $dir + + # remove addresses for a cleaner diff + # http://dummdida.tumblr.com/post/60924060451/binary-diff-between-libc-from-scientificlinux-and + $OBJDUMP -D $1 | sed "s/^[[:space:]]\+[0-9a-f]\+//" > $dis +} + +dorecord() { + [ $# -eq 0 ] && usage + + FILES="$*" + + CMT="`git rev-parse --short HEAD`" + + OBJDUMP="${CROSS_COMPILE}objdump" + + for d in $FILES; do + if [ -d "$d" ]; then + for f in $(find $d -name '*.o') + do + do_objdump $f + done + else + do_objdump $d + fi + done +} + +dodiff() { + [ $# -ne 2 ] && [ $# -ne 0 ] && usage + + if [ $# -eq 0 ]; then + SRC="`git rev-parse --short HEAD^`" + DST="`git rev-parse --short HEAD`" + else + SRC="`git rev-parse --short $1`" + DST="`git rev-parse --short $2`" + fi + + DIFF="`which colordiff`" + + if [ ${#DIFF} -eq 0 ] || [ ! -x "$DIFF" ]; then + DIFF="`which diff`" + fi + + SRCD="$TMPD/$SRC" + DSTD="$TMPD/$DST" + + if [ ! -d "$SRCD" ]; then + echo >&2 "ERROR: $SRCD doesn't exist" + exit 1 + fi + + if [ ! -d "$DSTD" ]; then + echo >&2 "ERROR: $DSTD doesn't exist" + exit 1 + fi + + $DIFF -Nurd $SRCD $DSTD +} + +doclean() { + [ $# -eq 0 ] && usage + [ $# -gt 1 ] && usage + + if [ "x$1" = "xall" ]; then + rm -rf $TMPD/* + else + CMT="`git rev-parse --short $1`" + + if [ -d "$TMPD/$CMT" ]; then + rm -rf $TMPD/$CMT + else + echo >&2 "$CMT not found" + fi + fi +} + +[ $# -eq 0 ] && usage + +case "$1" in + record) + shift + dorecord $* + ;; + diff) + shift + dodiff $* + ;; + clean) + shift + doclean $* + ;; + *) + echo >&2 "Unrecognized command '$1'" + exit 1 + ;; +esac diff --git a/tools/setlocalversion b/scripts/setlocalversion similarity index 83% rename from tools/setlocalversion rename to scripts/setlocalversion index f551b4c4f4..63d91e22ed 100755 --- a/tools/setlocalversion +++ b/scripts/setlocalversion @@ -3,8 +3,10 @@ # This scripts adds local version information from the version # control systems git, mercurial (hg) and subversion (svn). # -# It was originally copied from the Linux kernel v3.2.0-rc4 and modified -# to support the U-Boot build-system. +# If something goes wrong, send a mail the kernel build mailinglist +# (see MAINTAINERS) and CC Nico Schottelius +# . +# # usage() { @@ -41,7 +43,8 @@ scm_version() fi # Check for git and a git repo. - if test -e .git && head=`git rev-parse --verify --short HEAD 2>/dev/null`; then + if test -z "$(git rev-parse --show-cdup 2>/dev/null)" && + head=`git rev-parse --verify --short HEAD 2>/dev/null`; then # If we are at a tagged commit (like "v2.6.30-rc6"), we ignore # it, because this version is defined in the top level Makefile. @@ -69,12 +72,8 @@ scm_version() printf -- '-svn%s' "`git svn find-rev $head`" fi - # Update index only on r/w media - [ -w . ] && git update-index --refresh --unmerged > /dev/null - # Check for uncommitted changes - if git diff-index --name-only HEAD | grep -v "^scripts/package" \ - | read dummy; then + if git diff-index --name-only HEAD | grep -qv "^scripts/package"; then printf '%s' -dirty fi @@ -107,7 +106,7 @@ scm_version() fi # Check for svn and a svn repo. - if rev=`svn info 2>/dev/null | grep '^Last Changed Rev'`; then + if rev=`LANG= LC_ALL= LC_MESSAGES=C svn info 2>/dev/null | grep '^Last Changed Rev'`; then rev=`echo $rev | awk '{print $NF}'` printf -- '-svn%s' "$rev" @@ -141,14 +140,12 @@ if $scm_only; then exit fi -#if test -e include/config/auto.conf; then -# . include/config/auto.conf -#else -# echo "Error: kernelrelease not valid - run 'make prepare' to update it" -# exit 1 -#fi -CONFIG_LOCALVERSION= -CONFIG_LOCALVERSION_AUTO=y +if test -e include/config/auto.conf; then + . include/config/auto.conf +else + echo "Error: kernelrelease not valid - run 'make prepare' to update it" + exit 1 +fi # localversion* files in the build and source directory res="$(collect_files localversion*)" diff --git a/scripts/show-gnu-make b/scripts/show-gnu-make new file mode 100755 index 0000000000..26271b59b9 --- /dev/null +++ b/scripts/show-gnu-make @@ -0,0 +1,25 @@ +#!/bin/sh +# +# Show the command name for GNU Make +# +# U-Boot is supposed to be built on various platforms. +# One problem is that the command 'make' is not always GNU Make. +# (For ex. the command name for GNU Make on FreeBSD is usually 'gmake'.) +# It is not a good idea to hard-code the command name in scripts +# where where GNU Make is expected. +# Call this helper script to get the command name for GNU Make. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +gnu_make= + +for m in make gmake +do + if $m --version 2>/dev/null | grep -q GNU; then + echo $m + exit 0 + fi +done + +exit 1 diff --git a/spl/.gitignore b/spl/.gitignore deleted file mode 100644 index 7c8814709f..0000000000 --- a/spl/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -u-boot-spl -u-boot-spl.bin -u-boot-spl.lds -u-boot-spl.map diff --git a/spl/Makefile b/spl/Makefile deleted file mode 100644 index 6e5299bef1..0000000000 --- a/spl/Makefile +++ /dev/null @@ -1,198 +0,0 @@ -# -# (C) Copyright 2000-2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2011 -# Daniel Schwierzeck, daniel.schwierzeck@googlemail.com. -# -# (C) Copyright 2011 -# Texas Instruments Incorporated - http://www.ti.com/ -# Aneesh V -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Based on top-level Makefile. -# - -CONFIG_SPL_BUILD := y -export CONFIG_SPL_BUILD - -include $(TOPDIR)/config.mk - -# We want the final binaries in this directory -obj := $(OBJTREE)/spl/ - -HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(SRCTREE)/board/$(VENDOR)/common/Makefile),y,n) - -ifdef CONFIG_SPL_START_S_PATH -START_PATH := $(subst ",,$(CONFIG_SPL_START_S_PATH)) -else -START_PATH := $(CPUDIR) -endif - -START := $(START_PATH)/start.o -ifeq ($(CPU),x86) -START += $(START_PATH)/start16.o -START += $(START_PATH)/resetvec.o -endif -ifeq ($(CPU),ppc4xx) -START += $(START_PATH)/resetvec.o -endif -ifeq ($(CPU),mpc85xx) -START += $(START_PATH)/resetvec.o -endif - -LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o - -LIBS-y += $(CPUDIR)/lib$(CPU).o -ifeq ($(CPU),mpc83xx) -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif -ifeq ($(CPU),mpc85xx) -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif -ifeq ($(CPU),mpc86xx) -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif - -ifdef SOC -LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o -endif -LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o -LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o - -LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/libspl.o -LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o -LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/libdisk.o -LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/libi2c.o -LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/libgpio.o -LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/libmmc.o -LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/libserial.o -LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o -LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o -LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o -LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o -LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o -LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o -LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o -LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o -LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o -LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o -LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o -LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o -LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o -LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o - -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) -LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -endif - -ifneq (,$(CONFIG_MX23)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) -LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o -endif - -ifneq ($(CONFIG_TEGRA),) -LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o -LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o -LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o -endif - -ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) -LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o -endif - -ifeq ($(SOC),exynos) -LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o -endif - -# Add GCC lib -ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") -PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o -PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC) -endif - -START := $(addprefix $(SPLTREE)/,$(START)) -LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y))) - -__START := $(subst $(obj),,$(START)) -__LIBS := $(subst $(obj),,$(LIBS)) - -# Linker Script -ifdef CONFIG_SPL_LDSCRIPT -# need to strip off double quotes -LDSCRIPT := $(addprefix $(SRCTREE)/,$(subst ",,$(CONFIG_SPL_LDSCRIPT))) -endif - -ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-spl.lds -endif -ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds -endif -ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot-spl.lds -endif -ifeq ($(wildcard $(LDSCRIPT)),) -$(error could not find linker script) -endif - -# Special flags for CPP when processing the linker script. -# Pass the version down so we can handle backwards compatibility -# on the fly. -LDPPFLAGS += \ - -include $(TOPDIR)/include/u-boot/u-boot.lds.h \ - -include $(OBJTREE)/include/config.h \ - -DCPUDIR=$(CPUDIR) \ - $(shell $(LD) --version | \ - sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') - -$(OBJTREE)/MLO: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mkimage -T omapimage \ - -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ - -$(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mkimage -T omapimage -n byteswap \ - -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ - -$(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend - $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@ - -ALL-y += $(obj)u-boot-spl.bin - -ifdef CONFIG_SAMSUNG -ALL-y += $(obj)$(BOARD)-spl.bin -endif - -all: $(ALL-y) - -ifdef CONFIG_SAMSUNG -$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mk$(BOARD)spl \ - $(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin -endif - -$(obj)u-boot-spl.bin: $(obj)u-boot-spl - $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ - -GEN_UBOOT = \ - cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ - -Map u-boot-spl.map -o u-boot-spl - -$(obj)u-boot-spl: depend $(START) $(LIBS) $(obj)u-boot-spl.lds - $(GEN_UBOOT) - -$(START): depend - $(MAKE) -C $(SRCTREE)/$(START_PATH) $@ - -$(LIBS): depend - $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) - -$(obj)u-boot-spl.lds: $(LDSCRIPT) depend - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@ - -depend: $(obj).depend -.PHONY: depend - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk diff --git a/test/Makefile b/test/Makefile index 99ce890e59..9c95805c44 100644 --- a/test/Makefile +++ b/test/Makefile @@ -4,26 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -LIB = $(obj)libtest.o - -COBJS-$(CONFIG_SANDBOX) += command_ut.o - -COBJS := $(sort $(COBJS-y)) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) $(XOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +obj-$(CONFIG_SANDBOX) += command_ut.o +obj-$(CONFIG_SANDBOX) += compression.o diff --git a/test/cmd_repeat.sh b/test/cmd_repeat.sh new file mode 100755 index 0000000000..990e79900f --- /dev/null +++ b/test/cmd_repeat.sh @@ -0,0 +1,29 @@ +#!/bin/sh + +# Test for U-Boot cli including command repeat + +BASE="$(dirname $0)" +. $BASE/common.sh + +run_test() { + ./${OUTPUT_DIR}/u-boot <${tmp} +check_results ${tmp} +rm ${tmp} +echo "Test passed" diff --git a/test/command_ut.c b/test/command_ut.c index 0e83db0cca..926573a395 100644 --- a/test/command_ut.c +++ b/test/command_ut.c @@ -7,6 +7,9 @@ #define DEBUG #include +#ifdef CONFIG_SANDBOX +#include +#endif static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; " "setenv list ${list}3\0" @@ -15,7 +18,7 @@ static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; " static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { printf("%s: Testing commands\n", __func__); - run_command("env default -f", 0); + run_command("env default -f -a", 0); /* run a single command */ run_command("setenv single 1", 0); @@ -58,6 +61,138 @@ static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) "setenv list ${list}3", strlen("setenv list 1"), 0); assert(!strcmp("1", getenv("list"))); + assert(run_command("false", 0) == 1); + assert(run_command("echo", 0) == 0); + assert(run_command_list("false", -1, 0) == 1); + assert(run_command_list("echo", -1, 0) == 0); + + run_command("setenv foo 'setenv monty 1; setenv python 2'", 0); + run_command("run foo", 0); + assert(getenv("monty") != NULL); + assert(!strcmp("1", getenv("monty"))); + assert(getenv("python") != NULL); + assert(!strcmp("2", getenv("python"))); + +#ifdef CONFIG_SYS_HUSH_PARSER + run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0); + run_command("run foo", 0); + assert(getenv("black") != NULL); + assert(!strcmp("1", getenv("black"))); + assert(getenv("adder") != NULL); + assert(!strcmp("2", getenv("adder"))); + + /* Test the 'test' command */ + +#define HUSH_TEST(name, expr, expected_result) \ + run_command("if test " expr " ; then " \ + "setenv " #name "_" #expected_result " y; else " \ + "setenv " #name "_" #expected_result " n; fi", 0); \ + assert(!strcmp(#expected_result, getenv(#name "_" #expected_result))); \ + setenv(#name "_" #expected_result, NULL); + + /* Basic operators */ + HUSH_TEST(streq, "aaa = aaa", y); + HUSH_TEST(streq, "aaa = bbb", n); + + HUSH_TEST(strneq, "aaa != bbb", y); + HUSH_TEST(strneq, "aaa != aaa", n); + + HUSH_TEST(strlt, "aaa < bbb", y); + HUSH_TEST(strlt, "bbb < aaa", n); + + HUSH_TEST(strgt, "bbb > aaa", y); + HUSH_TEST(strgt, "aaa > bbb", n); + + HUSH_TEST(eq, "123 -eq 123", y); + HUSH_TEST(eq, "123 -eq 456", n); + + HUSH_TEST(ne, "123 -ne 456", y); + HUSH_TEST(ne, "123 -ne 123", n); + + HUSH_TEST(lt, "123 -lt 456", y); + HUSH_TEST(lt_eq, "123 -lt 123", n); + HUSH_TEST(lt, "456 -lt 123", n); + + HUSH_TEST(le, "123 -le 456", y); + HUSH_TEST(le_eq, "123 -le 123", y); + HUSH_TEST(le, "456 -le 123", n); + + HUSH_TEST(gt, "456 -gt 123", y); + HUSH_TEST(gt_eq, "123 -gt 123", n); + HUSH_TEST(gt, "123 -gt 456", n); + + HUSH_TEST(ge, "456 -ge 123", y); + HUSH_TEST(ge_eq, "123 -ge 123", y); + HUSH_TEST(ge, "123 -ge 456", n); + + HUSH_TEST(z, "-z \"\"", y); + HUSH_TEST(z, "-z \"aaa\"", n); + + HUSH_TEST(n, "-n \"aaa\"", y); + HUSH_TEST(n, "-n \"\"", n); + + /* Inversion of simple tests */ + HUSH_TEST(streq_inv, "! aaa = aaa", n); + HUSH_TEST(streq_inv, "! aaa = bbb", y); + + HUSH_TEST(streq_inv_inv, "! ! aaa = aaa", y); + HUSH_TEST(streq_inv_inv, "! ! aaa = bbb", n); + + /* Binary operators */ + HUSH_TEST(or_0_0, "aaa != aaa -o bbb != bbb", n); + HUSH_TEST(or_0_1, "aaa != aaa -o bbb = bbb", y); + HUSH_TEST(or_1_0, "aaa = aaa -o bbb != bbb", y); + HUSH_TEST(or_1_1, "aaa = aaa -o bbb = bbb", y); + + HUSH_TEST(and_0_0, "aaa != aaa -a bbb != bbb", n); + HUSH_TEST(and_0_1, "aaa != aaa -a bbb = bbb", n); + HUSH_TEST(and_1_0, "aaa = aaa -a bbb != bbb", n); + HUSH_TEST(and_1_1, "aaa = aaa -a bbb = bbb", y); + + /* Inversion within binary operators */ + HUSH_TEST(or_0_0_inv, "! aaa != aaa -o ! bbb != bbb", y); + HUSH_TEST(or_0_1_inv, "! aaa != aaa -o ! bbb = bbb", y); + HUSH_TEST(or_1_0_inv, "! aaa = aaa -o ! bbb != bbb", y); + HUSH_TEST(or_1_1_inv, "! aaa = aaa -o ! bbb = bbb", n); + + HUSH_TEST(or_0_0_inv_inv, "! ! aaa != aaa -o ! ! bbb != bbb", n); + HUSH_TEST(or_0_1_inv_inv, "! ! aaa != aaa -o ! ! bbb = bbb", y); + HUSH_TEST(or_1_0_inv_inv, "! ! aaa = aaa -o ! ! bbb != bbb", y); + HUSH_TEST(or_1_1_inv_inv, "! ! aaa = aaa -o ! ! bbb = bbb", y); + + setenv("ut_var_nonexistent", NULL); + setenv("ut_var_exists", "1"); + HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_nonexistent\"", y); + HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_exists\"", n); + setenv("ut_var_exists", NULL); + + run_command("setenv ut_var_space \" \"", 0); + assert(!strcmp(getenv("ut_var_space"), " ")); + run_command("setenv ut_var_test $ut_var_space", 0); + assert(!getenv("ut_var_test")); + run_command("setenv ut_var_test \"$ut_var_space\"", 0); + assert(!strcmp(getenv("ut_var_test"), " ")); + run_command("setenv ut_var_test \" 1${ut_var_space}${ut_var_space} 2 \"", 0); + assert(!strcmp(getenv("ut_var_test"), " 1 2 ")); + setenv("ut_var_space", NULL); + setenv("ut_var_test", NULL); + +#ifdef CONFIG_SANDBOX + /* File existence */ + HUSH_TEST(e, "-e hostfs - creating_this_file_breaks_uboot_unit_test", n); + run_command("sb save hostfs - creating_this_file_breaks_uboot_unit_test 0 1", 0); + HUSH_TEST(e, "-e hostfs - creating_this_file_breaks_uboot_unit_test", y); + /* Perhaps this could be replaced by an "rm" shell command one day */ + assert(!os_unlink("creating_this_file_breaks_uboot_unit_test")); + HUSH_TEST(e, "-e hostfs - creating_this_file_breaks_uboot_unit_test", n); +#endif +#endif + + assert(run_command("", 0) == 0); + assert(run_command(" ", 0) == 0); + + assert(run_command("'", 0) == 1); + printf("%s: Everything went swimmingly\n", __func__); return 0; } diff --git a/test/common.sh b/test/common.sh new file mode 100644 index 0000000000..702d1ed051 --- /dev/null +++ b/test/common.sh @@ -0,0 +1,20 @@ +#!/bin/sh + +OUTPUT_DIR=sandbox + +fail() { + echo "Test failed: $1" + if [ -n ${tmp} ]; then + rm ${tmp} + fi + exit 1 +} + +build_uboot() { + echo "Build sandbox" + OPTS="O=${OUTPUT_DIR} $1" + NUM_CPUS=$(grep -c processor /proc/cpuinfo) + echo ${OPTS} + make ${OPTS} sandbox_config + make ${OPTS} -s -j${NUM_CPUS} +} diff --git a/test/compression.c b/test/compression.c new file mode 100644 index 0000000000..ea2e4ad22e --- /dev/null +++ b/test/compression.c @@ -0,0 +1,418 @@ +/* + * Copyright (c) 2013, The Chromium Authors + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define DEBUG + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +static const char plain[] = + "I am a highly compressable bit of text.\n" + "I am a highly compressable bit of text.\n" + "I am a highly compressable bit of text.\n" + "There are many like me, but this one is mine.\n" + "If I were any shorter, there wouldn't be much sense in\n" + "compressing me in the first place. At least with lzo, anyway,\n" + "which appears to behave poorly in the face of short text\n" + "messages.\n"; + +/* bzip2 -c /tmp/plain.txt > /tmp/plain.bz2 */ +static const char bzip2_compressed[] = + "\x42\x5a\x68\x39\x31\x41\x59\x26\x53\x59\xe5\x63\xdd\x09\x00\x00" + "\x28\x57\x80\x00\x10\x40\x85\x20\x20\x04\x00\x3f\xef\xdf\xf0\x30" + "\x00\xd6\xd0\x34\x91\x89\xa6\xf5\x4d\x19\x1a\x19\x0d\x02\x34\xd4" + "\xc9\x00\x34\x34\x00\x02\x48\x41\x35\x4f\xd4\xc6\x88\xd3\x50\x3d" + "\x4f\x51\x82\x4f\x88\xc3\x0d\x05\x62\x4f\x91\xa3\x52\x1b\xd0\x52" + "\x41\x4a\xa3\x98\xc2\x6b\xca\xa3\x82\xa5\xac\x8b\x15\x99\x68\xad" + "\xdf\x29\xd6\xf1\xf7\x5a\x10\xcd\x8c\x26\x61\x94\x95\xfe\x9e\x16" + "\x18\x28\x69\xd4\x23\x64\xcc\x2b\xe5\xe8\x5f\x00\xa4\x70\x26\x2c" + "\xee\xbd\x59\x6d\x6a\xec\xfc\x31\xda\x59\x0a\x14\x2a\x60\x1c\xf0" + "\x04\x86\x73\x9a\xc5\x5b\x87\x3f\x5b\x4c\x93\xe6\xb5\x35\x0d\xa6" + "\xb1\x2e\x62\x7b\xab\x67\xe7\x99\x2a\x14\x5e\x9f\x64\xcb\x96\xf4" + "\x0d\x65\xd4\x39\xe6\x8b\x7e\xea\x1c\x03\x69\x97\x83\x58\x91\x96" + "\xe1\xf0\x9d\xa4\x15\x8b\xb8\xc6\x93\xdc\x3d\xd9\x3c\x22\x55\xef" + "\xfb\xbb\x2a\xd3\x87\xa2\x8b\x04\xd9\x19\xf8\xe2\xfd\x4f\xdb\x1a" + "\x07\xc8\x60\xa3\x3f\xf8\xbb\x92\x29\xc2\x84\x87\x2b\x1e\xe8\x48"; +static const unsigned long bzip2_compressed_size = 240; + +/* lzma -z -c /tmp/plain.txt > /tmp/plain.lzma */ +static const char lzma_compressed[] = + "\x5d\x00\x00\x80\x00\xff\xff\xff\xff\xff\xff\xff\xff\x00\x24\x88" + "\x08\x26\xd8\x41\xff\x99\xc8\xcf\x66\x3d\x80\xac\xba\x17\xf1\xc8" + "\xb9\xdf\x49\x37\xb1\x68\xa0\x2a\xdd\x63\xd1\xa7\xa3\x66\xf8\x15" + "\xef\xa6\x67\x8a\x14\x18\x80\xcb\xc7\xb1\xcb\x84\x6a\xb2\x51\x16" + "\xa1\x45\xa0\xd6\x3e\x55\x44\x8a\x5c\xa0\x7c\xe5\xa8\xbd\x04\x57" + "\x8f\x24\xfd\xb9\x34\x50\x83\x2f\xf3\x46\x3e\xb9\xb0\x00\x1a\xf5" + "\xd3\x86\x7e\x8f\x77\xd1\x5d\x0e\x7c\xe1\xac\xde\xf8\x65\x1f\x4d" + "\xce\x7f\xa7\x3d\xaa\xcf\x26\xa7\x58\x69\x1e\x4c\xea\x68\x8a\xe5" + "\x89\xd1\xdc\x4d\xc7\xe0\x07\x42\xbf\x0c\x9d\x06\xd7\x51\xa2\x0b" + "\x7c\x83\x35\xe1\x85\xdf\xee\xfb\xa3\xee\x2f\x47\x5f\x8b\x70\x2b" + "\xe1\x37\xf3\x16\xf6\x27\x54\x8a\x33\x72\x49\xea\x53\x7d\x60\x0b" + "\x21\x90\x66\xe7\x9e\x56\x61\x5d\xd8\xdc\x59\xf0\xac\x2f\xd6\x49" + "\x6b\x85\x40\x08\x1f\xdf\x26\x25\x3b\x72\x44\xb0\xb8\x21\x2f\xb3" + "\xd7\x9b\x24\x30\x78\x26\x44\x07\xc3\x33\xd1\x4d\x03\x1b\xe1\xff" + "\xfd\xf5\x50\x8d\xca"; +static const unsigned long lzma_compressed_size = 229; + +/* lzop -c /tmp/plain.txt > /tmp/plain.lzo */ +static const char lzo_compressed[] = + "\x89\x4c\x5a\x4f\x00\x0d\x0a\x1a\x0a\x10\x30\x20\x60\x09\x40\x01" + "\x05\x03\x00\x00\x09\x00\x00\x81\xb4\x52\x09\x54\xf1\x00\x00\x00" + "\x00\x09\x70\x6c\x61\x69\x6e\x2e\x74\x78\x74\x65\xb1\x07\x9c\x00" + "\x00\x01\x5e\x00\x00\x01\x0f\xc3\xc7\x7a\xe0\x00\x16\x49\x20\x61" + "\x6d\x20\x61\x20\x68\x69\x67\x68\x6c\x79\x20\x63\x6f\x6d\x70\x72" + "\x65\x73\x73\x61\x62\x6c\x65\x20\x62\x69\x74\x20\x6f\x66\x20\x74" + "\x65\x78\x74\x2e\x0a\x20\x2f\x9c\x00\x00\x22\x54\x68\x65\x72\x65" + "\x20\x61\x72\x65\x20\x6d\x61\x6e\x79\x20\x6c\x69\x6b\x65\x20\x6d" + "\x65\x2c\x20\x62\x75\x74\x20\x74\x68\x69\x73\x20\x6f\x6e\x65\x20" + "\x69\x73\x20\x6d\x69\x6e\x65\x2e\x0a\x49\x66\x20\x49\x20\x77\x84" + "\x06\x0a\x6e\x79\x20\x73\x68\x6f\x72\x74\x65\x72\x2c\x20\x74\x90" + "\x08\x00\x08\x77\x6f\x75\x6c\x64\x6e\x27\x74\x20\x62\x65\x20\x6d" + "\x75\x63\x68\x20\x73\x65\x6e\x73\x65\x20\x69\x6e\x0a\xf8\x19\x02" + "\x69\x6e\x67\x20\x6d\x64\x02\x64\x06\x00\x5a\x20\x66\x69\x72\x73" + "\x74\x20\x70\x6c\x61\x63\x65\x2e\x20\x41\x74\x20\x6c\x65\x61\x73" + "\x74\x20\x77\x69\x74\x68\x20\x6c\x7a\x6f\x2c\x20\x61\x6e\x79\x77" + "\x61\x79\x2c\x0a\x77\x68\x69\x63\x68\x20\x61\x70\x70\x65\x61\x72" + "\x73\x20\x74\x6f\x20\x62\x65\x68\x61\x76\x65\x20\x70\x6f\x6f\x72" + "\x6c\x79\x20\x69\x6e\x20\x74\x68\x65\x20\x66\x61\x63\x65\x20\x6f" + "\x66\x20\x73\x68\x6f\x72\x74\x20\x74\x65\x78\x74\x0a\x6d\x65\x73" + "\x73\x61\x67\x65\x73\x2e\x0a\x11\x00\x00\x00\x00\x00\x00"; +static const unsigned long lzo_compressed_size = 334; + + +#define TEST_BUFFER_SIZE 512 + +typedef int (*mutate_func)(void *, unsigned long, void *, unsigned long, + unsigned long *); + +static int compress_using_gzip(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + int ret; + unsigned long inout_size = out_max; + + ret = gzip(out, &inout_size, in, in_size); + if (out_size) + *out_size = inout_size; + + return ret; +} + +static int uncompress_using_gzip(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + int ret; + unsigned long inout_size = in_size; + + ret = gunzip(out, out_max, in, &inout_size); + if (out_size) + *out_size = inout_size; + + return ret; +} + +static int compress_using_bzip2(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + /* There is no bzip2 compression in u-boot, so fake it. */ + assert(in_size == strlen(plain)); + assert(memcmp(plain, in, in_size) == 0); + + if (bzip2_compressed_size > out_max) + return -1; + + memcpy(out, bzip2_compressed, bzip2_compressed_size); + if (out_size) + *out_size = bzip2_compressed_size; + + return 0; +} + +static int uncompress_using_bzip2(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + int ret; + unsigned int inout_size = out_max; + + ret = BZ2_bzBuffToBuffDecompress(out, &inout_size, in, in_size, + CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); + if (out_size) + *out_size = inout_size; + + return (ret != BZ_OK); +} + +static int compress_using_lzma(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + /* There is no lzma compression in u-boot, so fake it. */ + assert(in_size == strlen(plain)); + assert(memcmp(plain, in, in_size) == 0); + + if (lzma_compressed_size > out_max) + return -1; + + memcpy(out, lzma_compressed, lzma_compressed_size); + if (out_size) + *out_size = lzma_compressed_size; + + return 0; +} + +static int uncompress_using_lzma(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + int ret; + SizeT inout_size = out_max; + + ret = lzmaBuffToBuffDecompress(out, &inout_size, in, in_size); + if (out_size) + *out_size = inout_size; + + return (ret != SZ_OK); +} + +static int compress_using_lzo(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + /* There is no lzo compression in u-boot, so fake it. */ + assert(in_size == strlen(plain)); + assert(memcmp(plain, in, in_size) == 0); + + if (lzo_compressed_size > out_max) + return -1; + + memcpy(out, lzo_compressed, lzo_compressed_size); + if (out_size) + *out_size = lzo_compressed_size; + + return 0; +} + +static int uncompress_using_lzo(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + int ret; + size_t input_size = in_size; + size_t output_size = out_max; + + ret = lzop_decompress(in, input_size, out, &output_size); + if (out_size) + *out_size = output_size; + + return (ret != LZO_E_OK); +} + +#define errcheck(statement) if (!(statement)) { \ + fprintf(stderr, "\tFailed: %s\n", #statement); \ + ret = 1; \ + goto out; \ +} + +static int run_test(char *name, mutate_func compress, mutate_func uncompress) +{ + ulong orig_size, compressed_size, uncompressed_size; + void *orig_buf; + void *compressed_buf = NULL; + void *uncompressed_buf = NULL; + void *compare_buf = NULL; + int ret; + + printf(" testing %s ...\n", name); + + orig_buf = (void *)plain; + orig_size = strlen(orig_buf); /* Trailing NULL not included. */ + errcheck(orig_size > 0); + + compressed_size = uncompressed_size = TEST_BUFFER_SIZE; + compressed_buf = malloc(compressed_size); + errcheck(compressed_buf != NULL); + uncompressed_buf = malloc(uncompressed_size); + errcheck(uncompressed_buf != NULL); + compare_buf = malloc(uncompressed_size); + errcheck(compare_buf != NULL); + + /* Compress works as expected. */ + printf("\torig_size:%lu\n", orig_size); + memset(compressed_buf, 'A', TEST_BUFFER_SIZE); + errcheck(compress(orig_buf, orig_size, + compressed_buf, compressed_size, + &compressed_size) == 0); + printf("\tcompressed_size:%lu\n", compressed_size); + errcheck(compressed_size > 0); + errcheck(compressed_size < orig_size); + errcheck(((char *)compressed_buf)[compressed_size-1] != 'A'); + errcheck(((char *)compressed_buf)[compressed_size] == 'A'); + + /* Uncompresses with space remaining. */ + errcheck(uncompress(compressed_buf, compressed_size, + uncompressed_buf, uncompressed_size, + &uncompressed_size) == 0); + printf("\tuncompressed_size:%lu\n", uncompressed_size); + errcheck(uncompressed_size == orig_size); + errcheck(memcmp(orig_buf, uncompressed_buf, orig_size) == 0); + + /* Uncompresses with exactly the right size output buffer. */ + memset(uncompressed_buf, 'A', TEST_BUFFER_SIZE); + errcheck(uncompress(compressed_buf, compressed_size, + uncompressed_buf, orig_size, + &uncompressed_size) == 0); + errcheck(uncompressed_size == orig_size); + errcheck(memcmp(orig_buf, uncompressed_buf, orig_size) == 0); + errcheck(((char *)uncompressed_buf)[orig_size] == 'A'); + + /* Make sure compression does not over-run. */ + memset(compare_buf, 'A', TEST_BUFFER_SIZE); + ret = compress(orig_buf, orig_size, + compare_buf, compressed_size - 1, + NULL); + errcheck(((char *)compare_buf)[compressed_size] == 'A'); + errcheck(ret != 0); + printf("\tcompress does not overrun\n"); + + /* Make sure decompression does not over-run. */ + memset(compare_buf, 'A', TEST_BUFFER_SIZE); + ret = uncompress(compressed_buf, compressed_size, + compare_buf, uncompressed_size - 1, + NULL); + errcheck(((char *)compare_buf)[uncompressed_size - 1] == 'A'); + errcheck(ret != 0); + printf("\tuncompress does not overrun\n"); + + /* Got here, everything is fine. */ + ret = 0; + +out: + printf(" %s: %s\n", name, ret == 0 ? "ok" : "FAILED"); + + free(compare_buf); + free(uncompressed_buf); + free(compressed_buf); + + return ret; +} + +static int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err = 0; + + err += run_test("gzip", compress_using_gzip, uncompress_using_gzip); + err += run_test("bzip2", compress_using_bzip2, uncompress_using_bzip2); + err += run_test("lzma", compress_using_lzma, uncompress_using_lzma); + err += run_test("lzo", compress_using_lzo, uncompress_using_lzo); + + printf("ut_compression %s\n", err == 0 ? "ok" : "FAILED"); + + return err; +} + +static int compress_using_none(void *in, unsigned long in_size, + void *out, unsigned long out_max, + unsigned long *out_size) +{ + /* Here we just copy */ + memcpy(out, in, in_size); + *out_size = in_size; + + return 0; +} + +/** + * run_bootm_test() - Run tests on the bootm decopmression function + * + * @comp_type: Compression type to test + * @compress: Our function to compress data + * @return 0 if OK, non-zero on failure + */ +static int run_bootm_test(int comp_type, mutate_func compress) +{ + ulong compress_size = 1024; + void *compress_buff; + int unc_len; + int err = 0; + const ulong image_start = 0; + const ulong load_addr = 0x1000; + ulong load_end; + + printf("Testing: %s\n", genimg_get_comp_name(comp_type)); + compress_buff = map_sysmem(image_start, 0); + unc_len = strlen(plain); + compress((void *)plain, unc_len, compress_buff, compress_size, + &compress_size); + err = bootm_decomp_image(comp_type, load_addr, image_start, + IH_TYPE_KERNEL, map_sysmem(load_addr, 0), + compress_buff, compress_size, unc_len, + &load_end); + if (err) + return err; + err = bootm_decomp_image(comp_type, load_addr, image_start, + IH_TYPE_KERNEL, map_sysmem(load_addr, 0), + compress_buff, compress_size, unc_len - 1, + &load_end); + if (!err) + return -EINVAL; + + /* We can't detect corruption when not decompressing */ + if (comp_type == IH_COMP_NONE) + return 0; + memset(compress_buff + compress_size / 2, '\x49', + compress_size / 2); + err = bootm_decomp_image(comp_type, load_addr, image_start, + IH_TYPE_KERNEL, map_sysmem(load_addr, 0), + compress_buff, compress_size, 0x10000, + &load_end); + if (!err) + return -EINVAL; + + return 0; +} + +static int do_ut_image_decomp(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err = 0; + + err = run_bootm_test(IH_COMP_GZIP, compress_using_gzip); + err |= run_bootm_test(IH_COMP_BZIP2, compress_using_bzip2); + err |= run_bootm_test(IH_COMP_LZMA, compress_using_lzma); + err |= run_bootm_test(IH_COMP_LZO, compress_using_lzo); + err |= run_bootm_test(IH_COMP_NONE, compress_using_none); + + printf("ut_image_decomp %s\n", err == 0 ? "ok" : "FAILED"); + + return 0; +} + +U_BOOT_CMD( + ut_compression, 5, 1, do_ut_compression, + "Basic test of compressors: gzip bzip2 lzma lzo", "" +); + +U_BOOT_CMD( + ut_image_decomp, 5, 1, do_ut_image_decomp, + "Basic test of bootm decompression", "" +); diff --git a/test/dfu/README b/test/dfu/README new file mode 100644 index 0000000000..5176aba632 --- /dev/null +++ b/test/dfu/README @@ -0,0 +1,37 @@ +DFU TEST CASE DESCRIPTION: + +The prerequisites for running this script are assured by +dfu_gadget_test_init.sh, which is automatically invoked by dfu_gadget_test.sh. +In this file user is able to generate their own set of test files by altering +the default set of TEST_FILES_SIZES variable. +The dfu_gadget_test_init.sh would generate test images only if they are not +already generated. + +On the target device, environment variable "dfu_alt_info" must contain at +least: + + dfu_test.bin fat 0 6;dfudummy.bin fat 0 6 + +Depending on your device, you may need to replace "fat" with +"ext4", and "6" with the relevant partition number. For reference please +consult the config file for TRATS/TRATS2 devices +(../../include/configs/trats{2}.h) + +One can use fat, ext4 or any other supported file system supported by U-Boot. +These can be created by exporting storage devices via UMS (ums 0 mmc 0) and +using standard tools on host (like mkfs.ext4). + +Example usage: +1. On the target: + setenv dfu_alt_info dfu_test.bin fat 0 6\;dfudummy.bin fat 0 6 + dfu 0 mmc 0 +2. On the host: + test/dfu/dfu_gadget_test.sh X Y [test file name] + e.g. test/dfu/dfu_gadget_test.sh 0 1 + or + e.g. test/dfu/dfu_gadget_test.sh 0 1 ./dat_960.img + +... where X and Y are dfu_test.bin's and dfudummy.bin's alt setting numbers. +They can be obtained from dfu-util -l or $dfu_alt_info. +It is also possible to pass optional [test file name] to force the script to +test one particular file. diff --git a/test/dfu/dfu_gadget_test.sh b/test/dfu/dfu_gadget_test.sh new file mode 100755 index 0000000000..2f5b7db58d --- /dev/null +++ b/test/dfu/dfu_gadget_test.sh @@ -0,0 +1,104 @@ +#! /bin/bash + +# Copyright (C) 2014 Samsung Electronics +# Lukasz Majewski +# +# Script fixes, enhancements and testing: +# Stephen Warren +# +# DFU operation test script +# +# SPDX-License-Identifier: GPL-2.0+ + +set -e # any command return if not equal to zero +clear + +COLOUR_RED="\33[31m" +COLOUR_GREEN="\33[32m" +COLOUR_DEFAULT="\33[0m" + +DIR=./ +SUFFIX=img +RCV_DIR=rcv/ +LOG_FILE=./log/log-`date +%d-%m-%Y_%H-%M-%S` + +cd `dirname $0` +./dfu_gadget_test_init.sh + +cleanup () { + rm -rf $DIR$RCV_DIR +} + +die () { + printf " $COLOUR_RED FAILED $COLOUR_DEFAULT \n" + cleanup + exit 1 +} + +calculate_md5sum () { + MD5SUM=`md5sum $1` + MD5SUM=`echo $MD5SUM | cut -d ' ' -f1` + echo "md5sum:"$MD5SUM +} + +dfu_test_file () { + printf "$COLOUR_GREEN ========================================================================================= $COLOUR_DEFAULT\n" + printf "File:$COLOUR_GREEN %s $COLOUR_DEFAULT\n" $1 + + dfu-util -D $1 -a $TARGET_ALT_SETTING >> $LOG_FILE 2>&1 || die $? + + echo -n "TX: " + calculate_md5sum $1 + + MD5_TX=$MD5SUM + + dfu-util -D ${DIR}/dfudummy.bin -a $TARGET_ALT_SETTING_B >> $LOG_FILE 2>&1 || die $? + + N_FILE=$DIR$RCV_DIR${1:2}"_rcv" + + dfu-util -U $N_FILE -a $TARGET_ALT_SETTING >> $LOG_FILE 2>&1 || die $? + + echo -n "RX: " + calculate_md5sum $N_FILE + MD5_RX=$MD5SUM + + if [ "$MD5_TX" == "$MD5_RX" ]; then + printf " $COLOUR_GREEN -------> OK $COLOUR_DEFAULT \n" + else + printf " $COLOUR_RED -------> FAILED $COLOUR_DEFAULT \n" + cleanup + exit 1 + fi + +} + +printf "$COLOUR_GREEN========================================================================================= $COLOUR_DEFAULT\n" +echo "DFU EP0 transmission test program" +echo "Trouble shoot -> disable DBG (even the KERN_DEBUG) in the UDC driver" +echo "@ -> TRATS2 # dfu 0 mmc 0" +cleanup +mkdir -p $DIR$RCV_DIR +touch $LOG_FILE + +if [ $# -eq 0 ] +then + printf " $COLOUR_RED Please pass alt setting number!! $COLOUR_DEFAULT \n" + exit 0 +fi + +TARGET_ALT_SETTING=$1 +TARGET_ALT_SETTING_B=$2 + +if [ -n "$3" ] +then + dfu_test_file $3 +else + for file in $DIR*.$SUFFIX + do + dfu_test_file $file + done +fi + +cleanup + +exit 0 diff --git a/test/dfu/dfu_gadget_test_init.sh b/test/dfu/dfu_gadget_test_init.sh new file mode 100755 index 0000000000..640628eecb --- /dev/null +++ b/test/dfu/dfu_gadget_test_init.sh @@ -0,0 +1,45 @@ +#! /bin/bash + +# Copyright (C) 2014 Samsung Electronics +# Lukasz Majewski +# +# Script fixes, enhancements and testing: +# Stephen Warren +# +# Script for test files generation +# +# SPDX-License-Identifier: GPL-2.0+ + +set -e # any command return if not equal to zero +clear + +COLOUR_RED="\33[31m" +COLOUR_GREEN="\33[32m" +COLOUR_DEFAULT="\33[0m" + +LOG_DIR="./log" + +if [ $# -eq 0 ]; then + TEST_FILES_SIZES="63 64 65 127 128 129 4095 4096 4097 959 960 961 1048575 1048576 8M" +else + TEST_FILES_SIZES=$@ +fi + +printf "Init script for generating data necessary for DFU test script" + +if [ ! -d $LOG_DIR ]; then + `mkdir $LOG_DIR` +fi + +for size in $TEST_FILES_SIZES +do + FILE="./dat_$size.img" + if [ ! -f $FILE ]; then + dd if=/dev/urandom of="./dat_$size.img" bs=$size count=1 > /dev/null 2>&1 || exit $? + fi +done +dd if=/dev/urandom of="./dfudummy.bin" bs=1024 count=1 > /dev/null 2>&1 || exit $? + +printf "$COLOUR_GREEN OK $COLOUR_DEFAULT \n" + +exit 0 diff --git a/test/dm/.gitignore b/test/dm/.gitignore new file mode 100644 index 0000000000..b741b8ab00 --- /dev/null +++ b/test/dm/.gitignore @@ -0,0 +1 @@ +/test.dtb diff --git a/test/dm/Makefile b/test/dm/Makefile new file mode 100644 index 0000000000..612aa957fa --- /dev/null +++ b/test/dm/Makefile @@ -0,0 +1,24 @@ +# +# Copyright (c) 2013 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_CMD_DM) += cmd_dm.o +obj-$(CONFIG_DM_TEST) += bus.o +obj-$(CONFIG_DM_TEST) += test-driver.o +obj-$(CONFIG_DM_TEST) += test-fdt.o +obj-$(CONFIG_DM_TEST) += test-main.o +obj-$(CONFIG_DM_TEST) += test-uclass.o +obj-$(CONFIG_DM_TEST) += ut.o + +# Tests for particular subsystems - when enabling driver model for a new +# subsystem you must add sandbox tests here. +obj-$(CONFIG_DM_TEST) += core.o +obj-$(CONFIG_DM_TEST) += ut.o +ifneq ($(CONFIG_SANDBOX),) +obj-$(CONFIG_DM_GPIO) += gpio.o +obj-$(CONFIG_DM_SPI) += spi.o +obj-$(CONFIG_DM_SPI_FLASH) += sf.o +obj-$(CONFIG_DM_I2C) += i2c.o +endif diff --git a/test/dm/bus.c b/test/dm/bus.c new file mode 100644 index 0000000000..faffe6a385 --- /dev/null +++ b/test/dm/bus.c @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct dm_test_parent_platdata { + int count; + int bind_flag; + int uclass_bind_flag; +}; + +enum { + FLAG_CHILD_PROBED = 10, + FLAG_CHILD_REMOVED = -7, +}; + +static struct dm_test_state *test_state; + +static int testbus_drv_probe(struct udevice *dev) +{ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + +static int testbus_child_post_bind(struct udevice *dev) +{ + struct dm_test_parent_platdata *plat; + + plat = dev_get_parent_platdata(dev); + plat->bind_flag = 1; + plat->uclass_bind_flag = 2; + + return 0; +} + +static int testbus_child_pre_probe(struct udevice *dev) +{ + struct dm_test_parent_data *parent_data = dev_get_parentdata(dev); + + parent_data->flag += FLAG_CHILD_PROBED; + + return 0; +} + +static int testbus_child_pre_probe_uclass(struct udevice *dev) +{ + struct dm_test_priv *priv = dev_get_priv(dev); + + priv->uclass_flag++; + + return 0; +} + +static int testbus_child_post_remove(struct udevice *dev) +{ + struct dm_test_parent_data *parent_data = dev_get_parentdata(dev); + struct dm_test_state *dms = test_state; + + parent_data->flag += FLAG_CHILD_REMOVED; + if (dms) + dms->removed = dev; + + return 0; +} + +static const struct udevice_id testbus_ids[] = { + { + .compatible = "denx,u-boot-test-bus", + .data = DM_TEST_TYPE_FIRST }, + { } +}; + +U_BOOT_DRIVER(testbus_drv) = { + .name = "testbus_drv", + .of_match = testbus_ids, + .id = UCLASS_TEST_BUS, + .probe = testbus_drv_probe, + .child_post_bind = testbus_child_post_bind, + .priv_auto_alloc_size = sizeof(struct dm_test_priv), + .platdata_auto_alloc_size = sizeof(struct dm_test_pdata), + .per_child_auto_alloc_size = sizeof(struct dm_test_parent_data), + .per_child_platdata_auto_alloc_size = + sizeof(struct dm_test_parent_platdata), + .child_pre_probe = testbus_child_pre_probe, + .child_post_remove = testbus_child_post_remove, +}; + +UCLASS_DRIVER(testbus) = { + .name = "testbus", + .id = UCLASS_TEST_BUS, + .flags = DM_UC_FLAG_SEQ_ALIAS, + .child_pre_probe = testbus_child_pre_probe_uclass, +}; + +/* Test that we can probe for children */ +static int dm_test_bus_children(struct dm_test_state *dms) +{ + int num_devices = 6; + struct udevice *bus; + struct uclass *uc; + + ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc)); + ut_asserteq(num_devices, list_count_items(&uc->dev_head)); + + /* Probe the bus, which should yield 3 more devices */ + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + num_devices += 3; + + ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc)); + ut_asserteq(num_devices, list_count_items(&uc->dev_head)); + + ut_assert(!dm_check_devices(dms, num_devices)); + + return 0; +} +DM_TEST(dm_test_bus_children, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test our functions for accessing children */ +static int dm_test_bus_children_funcs(struct dm_test_state *dms) +{ + const void *blob = gd->fdt_blob; + struct udevice *bus, *dev; + int node; + + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + + /* device_get_child() */ + ut_assertok(device_get_child(bus, 0, &dev)); + ut_asserteq(-ENODEV, device_get_child(bus, 4, &dev)); + ut_assertok(device_get_child_by_seq(bus, 5, &dev)); + ut_assert(dev->flags & DM_FLAG_ACTIVATED); + ut_asserteq_str("c-test@5", dev->name); + + /* Device with sequence number 0 should be accessible */ + ut_asserteq(-ENODEV, device_find_child_by_seq(bus, -1, true, &dev)); + ut_assertok(device_find_child_by_seq(bus, 0, true, &dev)); + ut_assert(!(dev->flags & DM_FLAG_ACTIVATED)); + ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 0, false, &dev)); + ut_assertok(device_get_child_by_seq(bus, 0, &dev)); + ut_assert(dev->flags & DM_FLAG_ACTIVATED); + + /* There is no device with sequence number 2 */ + ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 2, false, &dev)); + ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 2, true, &dev)); + ut_asserteq(-ENODEV, device_get_child_by_seq(bus, 2, &dev)); + + /* Looking for something that is not a child */ + node = fdt_path_offset(blob, "/junk"); + ut_asserteq(-ENODEV, device_find_child_by_of_offset(bus, node, &dev)); + node = fdt_path_offset(blob, "/d-test"); + ut_asserteq(-ENODEV, device_find_child_by_of_offset(bus, node, &dev)); + + /* Find a valid child */ + node = fdt_path_offset(blob, "/some-bus/c-test@1"); + ut_assertok(device_find_child_by_of_offset(bus, node, &dev)); + ut_assert(!(dev->flags & DM_FLAG_ACTIVATED)); + ut_assertok(device_get_child_by_of_offset(bus, node, &dev)); + ut_assert(dev->flags & DM_FLAG_ACTIVATED); + + return 0; +} +DM_TEST(dm_test_bus_children_funcs, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that we can iterate through children */ +static int dm_test_bus_children_iterators(struct dm_test_state *dms) +{ + struct udevice *bus, *dev, *child; + + /* Walk through the children one by one */ + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + ut_assertok(device_find_first_child(bus, &dev)); + ut_asserteq_str("c-test@5", dev->name); + ut_assertok(device_find_next_child(&dev)); + ut_asserteq_str("c-test@0", dev->name); + ut_assertok(device_find_next_child(&dev)); + ut_asserteq_str("c-test@1", dev->name); + ut_assertok(device_find_next_child(&dev)); + ut_asserteq_ptr(dev, NULL); + + /* Move to the next child without using device_find_first_child() */ + ut_assertok(device_find_child_by_seq(bus, 5, true, &dev)); + ut_asserteq_str("c-test@5", dev->name); + ut_assertok(device_find_next_child(&dev)); + ut_asserteq_str("c-test@0", dev->name); + + /* Try a device with no children */ + ut_assertok(device_find_first_child(dev, &child)); + ut_asserteq_ptr(child, NULL); + + return 0; +} +DM_TEST(dm_test_bus_children_iterators, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that the bus can store data about each child */ +static int test_bus_parent_data(struct dm_test_state *dms) +{ + struct dm_test_parent_data *parent_data; + struct udevice *bus, *dev; + struct uclass *uc; + int value; + + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + + /* Check that parent data is allocated */ + ut_assertok(device_find_child_by_seq(bus, 0, true, &dev)); + ut_asserteq_ptr(NULL, dev_get_parentdata(dev)); + ut_assertok(device_get_child_by_seq(bus, 0, &dev)); + parent_data = dev_get_parentdata(dev); + ut_assert(NULL != parent_data); + + /* Check that it starts at 0 and goes away when device is removed */ + parent_data->sum += 5; + ut_asserteq(5, parent_data->sum); + device_remove(dev); + ut_asserteq_ptr(NULL, dev_get_parentdata(dev)); + + /* Check that we can do this twice */ + ut_assertok(device_get_child_by_seq(bus, 0, &dev)); + parent_data = dev_get_parentdata(dev); + ut_assert(NULL != parent_data); + parent_data->sum += 5; + ut_asserteq(5, parent_data->sum); + + /* Add parent data to all children */ + ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc)); + value = 5; + uclass_foreach_dev(dev, uc) { + /* Ignore these if they are not on this bus */ + if (dev->parent != bus) { + ut_asserteq_ptr(NULL, dev_get_parentdata(dev)); + continue; + } + ut_assertok(device_probe(dev)); + parent_data = dev_get_parentdata(dev); + + parent_data->sum = value; + value += 5; + } + + /* Check it is still there */ + value = 5; + uclass_foreach_dev(dev, uc) { + /* Ignore these if they are not on this bus */ + if (dev->parent != bus) + continue; + parent_data = dev_get_parentdata(dev); + + ut_asserteq(value, parent_data->sum); + value += 5; + } + + return 0; +} +/* Test that the bus can store data about each child */ +static int dm_test_bus_parent_data(struct dm_test_state *dms) +{ + return test_bus_parent_data(dms); +} +DM_TEST(dm_test_bus_parent_data, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* As above but the size is controlled by the uclass */ +static int dm_test_bus_parent_data_uclass(struct dm_test_state *dms) +{ + struct udevice *bus; + int size; + int ret; + + /* Set the driver size to 0 so that the uclass size is used */ + ut_assertok(uclass_find_device(UCLASS_TEST_BUS, 0, &bus)); + size = bus->driver->per_child_auto_alloc_size; + bus->uclass->uc_drv->per_child_auto_alloc_size = size; + bus->driver->per_child_auto_alloc_size = 0; + ret = test_bus_parent_data(dms); + if (ret) + return ret; + bus->uclass->uc_drv->per_child_auto_alloc_size = 0; + bus->driver->per_child_auto_alloc_size = size; + + return 0; +} +DM_TEST(dm_test_bus_parent_data_uclass, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that the bus ops are called when a child is probed/removed */ +static int dm_test_bus_parent_ops(struct dm_test_state *dms) +{ + struct dm_test_parent_data *parent_data; + struct udevice *bus, *dev; + struct uclass *uc; + + test_state = dms; + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc)); + + uclass_foreach_dev(dev, uc) { + /* Ignore these if they are not on this bus */ + if (dev->parent != bus) + continue; + ut_asserteq_ptr(NULL, dev_get_parentdata(dev)); + + ut_assertok(device_probe(dev)); + parent_data = dev_get_parentdata(dev); + ut_asserteq(FLAG_CHILD_PROBED, parent_data->flag); + } + + uclass_foreach_dev(dev, uc) { + /* Ignore these if they are not on this bus */ + if (dev->parent != bus) + continue; + parent_data = dev_get_parentdata(dev); + ut_asserteq(FLAG_CHILD_PROBED, parent_data->flag); + ut_assertok(device_remove(dev)); + ut_asserteq_ptr(NULL, dev_get_parentdata(dev)); + ut_asserteq_ptr(dms->removed, dev); + } + test_state = NULL; + + return 0; +} +DM_TEST(dm_test_bus_parent_ops, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int test_bus_parent_platdata(struct dm_test_state *dms) +{ + struct dm_test_parent_platdata *plat; + struct udevice *bus, *dev; + int child_count; + + /* Check that the bus has no children */ + ut_assertok(uclass_find_device(UCLASS_TEST_BUS, 0, &bus)); + device_find_first_child(bus, &dev); + ut_asserteq_ptr(NULL, dev); + + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + + for (device_find_first_child(bus, &dev), child_count = 0; + dev; + device_find_next_child(&dev)) { + /* Check that platform data is allocated */ + plat = dev_get_parent_platdata(dev); + ut_assert(plat != NULL); + + /* + * Check that it is not affected by the device being + * probed/removed + */ + plat->count++; + ut_asserteq(1, plat->count); + device_probe(dev); + device_remove(dev); + + ut_asserteq_ptr(plat, dev_get_parent_platdata(dev)); + ut_asserteq(1, plat->count); + ut_assertok(device_probe(dev)); + child_count++; + } + ut_asserteq(3, child_count); + + /* Removing the bus should also have no effect (it is still bound) */ + device_remove(bus); + for (device_find_first_child(bus, &dev), child_count = 0; + dev; + device_find_next_child(&dev)) { + /* Check that platform data is allocated */ + plat = dev_get_parent_platdata(dev); + ut_assert(plat != NULL); + ut_asserteq(1, plat->count); + child_count++; + } + ut_asserteq(3, child_count); + + /* Unbind all the children */ + do { + device_find_first_child(bus, &dev); + if (dev) + device_unbind(dev); + } while (dev); + + /* Now the child platdata should be removed and re-added */ + device_probe(bus); + for (device_find_first_child(bus, &dev), child_count = 0; + dev; + device_find_next_child(&dev)) { + /* Check that platform data is allocated */ + plat = dev_get_parent_platdata(dev); + ut_assert(plat != NULL); + ut_asserteq(0, plat->count); + child_count++; + } + ut_asserteq(3, child_count); + + return 0; +} + +/* Test that the bus can store platform data about each child */ +static int dm_test_bus_parent_platdata(struct dm_test_state *dms) +{ + return test_bus_parent_platdata(dms); +} +DM_TEST(dm_test_bus_parent_platdata, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* As above but the size is controlled by the uclass */ +static int dm_test_bus_parent_platdata_uclass(struct dm_test_state *dms) +{ + struct udevice *bus; + int size; + int ret; + + /* Set the driver size to 0 so that the uclass size is used */ + ut_assertok(uclass_find_device(UCLASS_TEST_BUS, 0, &bus)); + size = bus->driver->per_child_platdata_auto_alloc_size; + bus->uclass->uc_drv->per_child_platdata_auto_alloc_size = size; + bus->driver->per_child_platdata_auto_alloc_size = 0; + ret = test_bus_parent_platdata(dms); + if (ret) + return ret; + bus->uclass->uc_drv->per_child_platdata_auto_alloc_size = 0; + bus->driver->per_child_platdata_auto_alloc_size = size; + + return 0; +} +DM_TEST(dm_test_bus_parent_platdata_uclass, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that the child post_bind method is called */ +static int dm_test_bus_child_post_bind(struct dm_test_state *dms) +{ + struct dm_test_parent_platdata *plat; + struct udevice *bus, *dev; + int child_count; + + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + for (device_find_first_child(bus, &dev), child_count = 0; + dev; + device_find_next_child(&dev)) { + /* Check that platform data is allocated */ + plat = dev_get_parent_platdata(dev); + ut_assert(plat != NULL); + ut_asserteq(1, plat->bind_flag); + child_count++; + } + ut_asserteq(3, child_count); + + return 0; +} +DM_TEST(dm_test_bus_child_post_bind, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that the child post_bind method is called */ +static int dm_test_bus_child_post_bind_uclass(struct dm_test_state *dms) +{ + struct dm_test_parent_platdata *plat; + struct udevice *bus, *dev; + int child_count; + + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + for (device_find_first_child(bus, &dev), child_count = 0; + dev; + device_find_next_child(&dev)) { + /* Check that platform data is allocated */ + plat = dev_get_parent_platdata(dev); + ut_assert(plat != NULL); + ut_asserteq(2, plat->uclass_bind_flag); + child_count++; + } + ut_asserteq(3, child_count); + + return 0; +} +DM_TEST(dm_test_bus_child_post_bind_uclass, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* + * Test that the bus' uclass' child_pre_probe() is called before the + * device's probe() method + */ +static int dm_test_bus_child_pre_probe_uclass(struct dm_test_state *dms) +{ + struct udevice *bus, *dev; + int child_count; + + /* + * See testfdt_drv_probe() which effectively checks that the uclass + * flag is set before that method is called + */ + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + for (device_find_first_child(bus, &dev), child_count = 0; + dev; + device_find_next_child(&dev)) { + struct dm_test_priv *priv = dev_get_priv(dev); + + /* Check that things happened in the right order */ + ut_asserteq_ptr(NULL, priv); + ut_assertok(device_probe(dev)); + + priv = dev_get_priv(dev); + ut_assert(priv != NULL); + ut_asserteq(1, priv->uclass_flag); + ut_asserteq(1, priv->uclass_total); + child_count++; + } + ut_asserteq(3, child_count); + + return 0; +} +DM_TEST(dm_test_bus_child_pre_probe_uclass, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c new file mode 100644 index 0000000000..79a674efcc --- /dev/null +++ b/test/dm/cmd_dm.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void show_devices(struct udevice *dev, int depth, int last_flag) +{ + int i, is_last; + struct udevice *child; + char class_name[12]; + + /* print the first 11 characters to not break the tree-format. */ + strlcpy(class_name, dev->uclass->uc_drv->name, sizeof(class_name)); + printf(" %-11s [ %c ] ", class_name, + dev->flags & DM_FLAG_ACTIVATED ? '+' : ' '); + + for (i = depth; i >= 0; i--) { + is_last = (last_flag >> i) & 1; + if (i) { + if (is_last) + printf(" "); + else + printf("| "); + } else { + if (is_last) + printf("`-- "); + else + printf("|-- "); + } + } + + printf("%s\n", dev->name); + + list_for_each_entry(child, &dev->child_head, sibling_node) { + is_last = list_is_last(&child->sibling_node, &dev->child_head); + show_devices(child, depth + 1, (last_flag << 1) | is_last); + } +} + +static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct udevice *root; + + root = dm_root(); + if (root) { + printf(" Class Probed Name\n"); + printf("----------------------------------------\n"); + show_devices(root, -1, 0); + } + + return 0; +} + +/** + * dm_display_line() - Display information about a single device + * + * Displays a single line of information with an option prefix + * + * @dev: Device to display + */ +static void dm_display_line(struct udevice *dev) +{ + printf("- %c %s @ %08lx", + dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ', + dev->name, (ulong)map_to_sysmem(dev)); + if (dev->req_seq != -1) + printf(", %d", dev->req_seq); + puts("\n"); +} + +static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct uclass *uc; + int ret; + int id; + + for (id = 0; id < UCLASS_COUNT; id++) { + struct udevice *dev; + + ret = uclass_get(id, &uc); + if (ret) + continue; + + printf("uclass %d: %s\n", id, uc->uc_drv->name); + if (list_empty(&uc->dev_head)) + continue; + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + dm_display_line(dev); + } + puts("\n"); + } + + return 0; +} + +#ifdef CONFIG_DM_TEST +static int do_dm_test(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return dm_test_main(); +} +#define TEST_HELP "\ndm test Run tests" +#else +#define TEST_HELP +#endif + +static cmd_tbl_t test_commands[] = { + U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""), + U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""), +#ifdef CONFIG_DM_TEST + U_BOOT_CMD_MKENT(test, 1, 1, do_dm_test, "", ""), +#endif +}; + +static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *test_cmd; + int ret; + + if (argc != 2) + return CMD_RET_USAGE; + test_cmd = find_cmd_tbl(argv[1], test_commands, + ARRAY_SIZE(test_commands)); + argc -= 2; + argv += 2; + if (!test_cmd || argc > test_cmd->maxargs) + return CMD_RET_USAGE; + + ret = test_cmd->cmd(test_cmd, flag, argc, argv); + + return cmd_process_error(test_cmd, ret); +} + +U_BOOT_CMD( + dm, 2, 1, do_dm, + "Driver model low level access", + "tree Dump driver model tree ('*' = activated)\n" + "dm uclass Dump list of instances for each uclass" + TEST_HELP +); diff --git a/test/dm/core.c b/test/dm/core.c new file mode 100644 index 0000000000..eccda0974d --- /dev/null +++ b/test/dm/core.c @@ -0,0 +1,611 @@ +/* + * Tests for the core driver model code + * + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + TEST_INTVAL1 = 0, + TEST_INTVAL2 = 3, + TEST_INTVAL3 = 6, + TEST_INTVAL_MANUAL = 101112, + TEST_INTVAL_PRE_RELOC = 7, +}; + +static const struct dm_test_pdata test_pdata[] = { + { .ping_add = TEST_INTVAL1, }, + { .ping_add = TEST_INTVAL2, }, + { .ping_add = TEST_INTVAL3, }, +}; + +static const struct dm_test_pdata test_pdata_manual = { + .ping_add = TEST_INTVAL_MANUAL, +}; + +static const struct dm_test_pdata test_pdata_pre_reloc = { + .ping_add = TEST_INTVAL_PRE_RELOC, +}; + +U_BOOT_DEVICE(dm_test_info1) = { + .name = "test_drv", + .platdata = &test_pdata[0], +}; + +U_BOOT_DEVICE(dm_test_info2) = { + .name = "test_drv", + .platdata = &test_pdata[1], +}; + +U_BOOT_DEVICE(dm_test_info3) = { + .name = "test_drv", + .platdata = &test_pdata[2], +}; + +static struct driver_info driver_info_manual = { + .name = "test_manual_drv", + .platdata = &test_pdata_manual, +}; + +static struct driver_info driver_info_pre_reloc = { + .name = "test_pre_reloc_drv", + .platdata = &test_pdata_manual, +}; + +void dm_leak_check_start(struct dm_test_state *dms) +{ + dms->start = mallinfo(); + if (!dms->start.uordblks) + puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n"); +} + +int dm_leak_check_end(struct dm_test_state *dms) +{ + struct mallinfo end; + int id; + + /* Don't delete the root class, since we started with that */ + for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) { + struct uclass *uc; + + uc = uclass_find(id); + if (!uc) + continue; + ut_assertok(uclass_destroy(uc)); + } + + end = mallinfo(); + ut_asserteq(dms->start.uordblks, end.uordblks); + + return 0; +} + +/* Test that binding with platdata occurs correctly */ +static int dm_test_autobind(struct dm_test_state *dms) +{ + struct udevice *dev; + + /* + * We should have a single class (UCLASS_ROOT) and a single root + * device with no children. + */ + ut_assert(dms->root); + ut_asserteq(1, list_count_items(&gd->uclass_root)); + ut_asserteq(0, list_count_items(&gd->dm_root->child_head)); + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]); + + ut_assertok(dm_scan_platdata(false)); + + /* We should have our test class now at least, plus more children */ + ut_assert(1 < list_count_items(&gd->uclass_root)); + ut_assert(0 < list_count_items(&gd->dm_root->child_head)); + + /* Our 3 dm_test_infox children should be bound to the test uclass */ + ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]); + + /* No devices should be probed */ + list_for_each_entry(dev, &gd->dm_root->child_head, sibling_node) + ut_assert(!(dev->flags & DM_FLAG_ACTIVATED)); + + /* Our test driver should have been bound 3 times */ + ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND] == 3); + + return 0; +} +DM_TEST(dm_test_autobind, 0); + +/* Test that autoprobe finds all the expected devices */ +static int dm_test_autoprobe(struct dm_test_state *dms) +{ + int expected_base_add; + struct udevice *dev; + struct uclass *uc; + int i; + + ut_assertok(uclass_get(UCLASS_TEST, &uc)); + ut_assert(uc); + + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]); + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]); + + /* The root device should not be activated until needed */ + ut_assert(dms->root->flags & DM_FLAG_ACTIVATED); + + /* + * We should be able to find the three test devices, and they should + * all be activated as they are used (lazy activation, required by + * U-Boot) + */ + for (i = 0; i < 3; i++) { + ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED), + "Driver %d/%s already activated", i, dev->name); + + /* This should activate it */ + ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + ut_assert(dev->flags & DM_FLAG_ACTIVATED); + + /* Activating a device should activate the root device */ + if (!i) + ut_assert(dms->root->flags & DM_FLAG_ACTIVATED); + } + + /* Our 3 dm_test_infox children should be passed to post_probe */ + ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]); + + /* Also we can check the per-device data */ + expected_base_add = 0; + for (i = 0; i < 3; i++) { + struct dm_test_uclass_perdev_priv *priv; + struct dm_test_pdata *pdata; + + ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + + priv = dev->uclass_priv; + ut_assert(priv); + ut_asserteq(expected_base_add, priv->base_add); + + pdata = dev->platdata; + expected_base_add += pdata->ping_add; + } + + return 0; +} +DM_TEST(dm_test_autoprobe, DM_TESTF_SCAN_PDATA); + +/* Check that we see the correct platdata in each device */ +static int dm_test_platdata(struct dm_test_state *dms) +{ + const struct dm_test_pdata *pdata; + struct udevice *dev; + int i; + + for (i = 0; i < 3; i++) { + ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + pdata = dev->platdata; + ut_assert(pdata->ping_add == test_pdata[i].ping_add); + } + + return 0; +} +DM_TEST(dm_test_platdata, DM_TESTF_SCAN_PDATA); + +/* Test that we can bind, probe, remove, unbind a driver */ +static int dm_test_lifecycle(struct dm_test_state *dms) +{ + int op_count[DM_TEST_OP_COUNT]; + struct udevice *dev, *test_dev; + int pingret; + int ret; + + memcpy(op_count, dm_testdrv_op_count, sizeof(op_count)); + + ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual, + &dev)); + ut_assert(dev); + ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND] + == op_count[DM_TEST_OP_BIND] + 1); + ut_assert(!dev->priv); + + /* Probe the device - it should fail allocating private data */ + dms->force_fail_alloc = 1; + ret = device_probe(dev); + ut_assert(ret == -ENOMEM); + ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE] + == op_count[DM_TEST_OP_PROBE] + 1); + ut_assert(!dev->priv); + + /* Try again without the alloc failure */ + dms->force_fail_alloc = 0; + ut_assertok(device_probe(dev)); + ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE] + == op_count[DM_TEST_OP_PROBE] + 2); + ut_assert(dev->priv); + + /* This should be device 3 in the uclass */ + ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev)); + ut_assert(dev == test_dev); + + /* Try ping */ + ut_assertok(test_ping(dev, 100, &pingret)); + ut_assert(pingret == 102); + + /* Now remove device 3 */ + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]); + ut_assertok(device_remove(dev)); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]); + + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_UNBIND]); + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]); + ut_assertok(device_unbind(dev)); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]); + + return 0; +} +DM_TEST(dm_test_lifecycle, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST); + +/* Test that we can bind/unbind and the lists update correctly */ +static int dm_test_ordering(struct dm_test_state *dms) +{ + struct udevice *dev, *dev_penultimate, *dev_last, *test_dev; + int pingret; + + ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual, + &dev)); + ut_assert(dev); + + /* Bind two new devices (numbers 4 and 5) */ + ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual, + &dev_penultimate)); + ut_assert(dev_penultimate); + ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual, + &dev_last)); + ut_assert(dev_last); + + /* Now remove device 3 */ + ut_assertok(device_remove(dev)); + ut_assertok(device_unbind(dev)); + + /* The device numbering should have shifted down one */ + ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev)); + ut_assert(dev_penultimate == test_dev); + ut_assertok(uclass_find_device(UCLASS_TEST, 4, &test_dev)); + ut_assert(dev_last == test_dev); + + /* Add back the original device 3, now in position 5 */ + ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual, + &dev)); + ut_assert(dev); + + /* Try ping */ + ut_assertok(test_ping(dev, 100, &pingret)); + ut_assert(pingret == 102); + + /* Remove 3 and 4 */ + ut_assertok(device_remove(dev_penultimate)); + ut_assertok(device_unbind(dev_penultimate)); + ut_assertok(device_remove(dev_last)); + ut_assertok(device_unbind(dev_last)); + + /* Our device should now be in position 3 */ + ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev)); + ut_assert(dev == test_dev); + + /* Now remove device 3 */ + ut_assertok(device_remove(dev)); + ut_assertok(device_unbind(dev)); + + return 0; +} +DM_TEST(dm_test_ordering, DM_TESTF_SCAN_PDATA); + +/* Check that we can perform operations on a device (do a ping) */ +int dm_check_operations(struct dm_test_state *dms, struct udevice *dev, + uint32_t base, struct dm_test_priv *priv) +{ + int expected; + int pingret; + + /* Getting the child device should allocate platdata / priv */ + ut_assertok(testfdt_ping(dev, 10, &pingret)); + ut_assert(dev->priv); + ut_assert(dev->platdata); + + expected = 10 + base; + ut_asserteq(expected, pingret); + + /* Do another ping */ + ut_assertok(testfdt_ping(dev, 20, &pingret)); + expected = 20 + base; + ut_asserteq(expected, pingret); + + /* Now check the ping_total */ + priv = dev->priv; + ut_asserteq(DM_TEST_START_TOTAL + 10 + 20 + base * 2, + priv->ping_total); + + return 0; +} + +/* Check that we can perform operations on devices */ +static int dm_test_operations(struct dm_test_state *dms) +{ + struct udevice *dev; + int i; + + /* + * Now check that the ping adds are what we expect. This is using the + * ping-add property in each node. + */ + for (i = 0; i < ARRAY_SIZE(test_pdata); i++) { + uint32_t base; + + ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev)); + + /* + * Get the 'reg' property, which tells us what the ping add + * should be. We don't use the platdata because we want + * to test the code that sets that up (testfdt_drv_probe()). + */ + base = test_pdata[i].ping_add; + debug("dev=%d, base=%d\n", i, base); + + ut_assert(!dm_check_operations(dms, dev, base, dev->priv)); + } + + return 0; +} +DM_TEST(dm_test_operations, DM_TESTF_SCAN_PDATA); + +/* Remove all drivers and check that things work */ +static int dm_test_remove(struct dm_test_state *dms) +{ + struct udevice *dev; + int i; + + for (i = 0; i < 3; i++) { + ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev)); + ut_assert(dev); + ut_assertf(dev->flags & DM_FLAG_ACTIVATED, + "Driver %d/%s not activated", i, dev->name); + ut_assertok(device_remove(dev)); + ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED), + "Driver %d/%s should have deactivated", i, + dev->name); + ut_assert(!dev->priv); + } + + return 0; +} +DM_TEST(dm_test_remove, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST); + +/* Remove and recreate everything, check for memory leaks */ +static int dm_test_leak(struct dm_test_state *dms) +{ + int i; + + for (i = 0; i < 2; i++) { + struct udevice *dev; + int ret; + int id; + + dm_leak_check_start(dms); + + ut_assertok(dm_scan_platdata(false)); + ut_assertok(dm_scan_fdt(gd->fdt_blob, false)); + + /* Scanning the uclass is enough to probe all the devices */ + for (id = UCLASS_ROOT; id < UCLASS_COUNT; id++) { + for (ret = uclass_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_next_device(&dev)) + ; + ut_assertok(ret); + } + + ut_assertok(dm_leak_check_end(dms)); + } + + return 0; +} +DM_TEST(dm_test_leak, 0); + +/* Test uclass init/destroy methods */ +static int dm_test_uclass(struct dm_test_state *dms) +{ + struct uclass *uc; + + ut_assertok(uclass_get(UCLASS_TEST, &uc)); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]); + ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_DESTROY]); + ut_assert(uc->priv); + + ut_assertok(uclass_destroy(uc)); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]); + ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_DESTROY]); + + return 0; +} +DM_TEST(dm_test_uclass, 0); + +/** + * create_children() - Create children of a parent node + * + * @dms: Test system state + * @parent: Parent device + * @count: Number of children to create + * @key: Key value to put in first child. Subsequence children + * receive an incrementing value + * @child: If not NULL, then the child device pointers are written into + * this array. + * @return 0 if OK, -ve on error + */ +static int create_children(struct dm_test_state *dms, struct udevice *parent, + int count, int key, struct udevice *child[]) +{ + struct udevice *dev; + int i; + + for (i = 0; i < count; i++) { + struct dm_test_pdata *pdata; + + ut_assertok(device_bind_by_name(parent, false, + &driver_info_manual, &dev)); + pdata = calloc(1, sizeof(*pdata)); + pdata->ping_add = key + i; + dev->platdata = pdata; + if (child) + child[i] = dev; + } + + return 0; +} + +#define NODE_COUNT 10 + +static int dm_test_children(struct dm_test_state *dms) +{ + struct udevice *top[NODE_COUNT]; + struct udevice *child[NODE_COUNT]; + struct udevice *grandchild[NODE_COUNT]; + struct udevice *dev; + int total; + int ret; + int i; + + /* We don't care about the numbering for this test */ + dms->skip_post_probe = 1; + + ut_assert(NODE_COUNT > 5); + + /* First create 10 top-level children */ + ut_assertok(create_children(dms, dms->root, NODE_COUNT, 0, top)); + + /* Now a few have their own children */ + ut_assertok(create_children(dms, top[2], NODE_COUNT, 2, NULL)); + ut_assertok(create_children(dms, top[5], NODE_COUNT, 5, child)); + + /* And grandchildren */ + for (i = 0; i < NODE_COUNT; i++) + ut_assertok(create_children(dms, child[i], NODE_COUNT, 50 * i, + i == 2 ? grandchild : NULL)); + + /* Check total number of devices */ + total = NODE_COUNT * (3 + NODE_COUNT); + ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_BIND]); + + /* Try probing one of the grandchildren */ + ut_assertok(uclass_get_device(UCLASS_TEST, + NODE_COUNT * 3 + 2 * NODE_COUNT, &dev)); + ut_asserteq_ptr(grandchild[0], dev); + + /* + * This should have probed the child and top node also, for a total + * of 3 nodes. + */ + ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_PROBE]); + + /* Probe the other grandchildren */ + for (i = 1; i < NODE_COUNT; i++) + ut_assertok(device_probe(grandchild[i])); + + ut_asserteq(2 + NODE_COUNT, dm_testdrv_op_count[DM_TEST_OP_PROBE]); + + /* Probe everything */ + for (ret = uclass_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_next_device(&dev)) + ; + ut_assertok(ret); + + ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_PROBE]); + + /* Remove a top-level child and check that the children are removed */ + ut_assertok(device_remove(top[2])); + ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_REMOVE]); + dm_testdrv_op_count[DM_TEST_OP_REMOVE] = 0; + + /* Try one with grandchildren */ + ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev)); + ut_asserteq_ptr(dev, top[5]); + ut_assertok(device_remove(dev)); + ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT), + dm_testdrv_op_count[DM_TEST_OP_REMOVE]); + + /* Try the same with unbind */ + ut_assertok(device_unbind(top[2])); + ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]); + dm_testdrv_op_count[DM_TEST_OP_UNBIND] = 0; + + /* Try one with grandchildren */ + ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev)); + ut_asserteq_ptr(dev, top[6]); + ut_assertok(device_unbind(top[5])); + ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT), + dm_testdrv_op_count[DM_TEST_OP_UNBIND]); + + return 0; +} +DM_TEST(dm_test_children, 0); + +/* Test that pre-relocation devices work as expected */ +static int dm_test_pre_reloc(struct dm_test_state *dms) +{ + struct udevice *dev; + + /* The normal driver should refuse to bind before relocation */ + ut_asserteq(-EPERM, device_bind_by_name(dms->root, true, + &driver_info_manual, &dev)); + + /* But this one is marked pre-reloc */ + ut_assertok(device_bind_by_name(dms->root, true, + &driver_info_pre_reloc, &dev)); + + return 0; +} +DM_TEST(dm_test_pre_reloc, 0); + +static int dm_test_uclass_before_ready(struct dm_test_state *dms) +{ + struct uclass *uc; + + ut_assertok(uclass_get(UCLASS_TEST, &uc)); + + memset(gd, '\0', sizeof(*gd)); + ut_asserteq_ptr(NULL, uclass_find(UCLASS_TEST)); + + return 0; +} + +DM_TEST(dm_test_uclass_before_ready, 0); + +static int dm_test_device_get_uclass_id(struct dm_test_state *dms) +{ + struct udevice *dev; + + ut_assertok(uclass_get_device(UCLASS_TEST, 0, &dev)); + ut_asserteq(UCLASS_TEST, device_get_uclass_id(dev)); + + return 0; +} +DM_TEST(dm_test_device_get_uclass_id, DM_TESTF_SCAN_PDATA); diff --git a/test/dm/gpio.c b/test/dm/gpio.c new file mode 100644 index 0000000000..b29daf1af4 --- /dev/null +++ b/test/dm/gpio.c @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Test that sandbox GPIOs work correctly */ +static int dm_test_gpio(struct dm_test_state *dms) +{ + unsigned int offset, gpio; + struct dm_gpio_ops *ops; + struct udevice *dev; + const char *name; + int offset_count; + char buf[80]; + + /* + * We expect to get 3 banks. One is anonymous (just numbered) and + * comes from platdata. The other two are named a (20 gpios) + * and b (10 gpios) and come from the device tree. See + * test/dm/test.dts. + */ + ut_assertok(gpio_lookup_name("b4", &dev, &offset, &gpio)); + ut_asserteq_str(dev->name, "extra-gpios"); + ut_asserteq(4, offset); + ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 20 + 4, gpio); + + name = gpio_get_bank_info(dev, &offset_count); + ut_asserteq_str("b", name); + ut_asserteq(10, offset_count); + + /* Get the operations for this device */ + ops = gpio_get_ops(dev); + ut_assert(ops->get_function); + + /* Cannot get a value until it is reserved */ + ut_asserteq(-EBUSY, gpio_get_value(gpio + 1)); + /* + * Now some tests that use the 'sandbox' back door. All GPIOs + * should default to input, include b4 that we are using here. + */ + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: input: 0 [ ]", buf); + + /* Change it to an output */ + sandbox_gpio_set_direction(dev, offset, 1); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: output: 0 [ ]", buf); + + sandbox_gpio_set_value(dev, offset, 1); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: output: 1 [ ]", buf); + + ut_assertok(gpio_request(gpio, "testing")); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: output: 1 [x] testing", buf); + + /* Change the value a bit */ + ut_asserteq(1, ops->get_value(dev, offset)); + ut_assertok(ops->set_value(dev, offset, 0)); + ut_asserteq(0, ops->get_value(dev, offset)); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: output: 0 [x] testing", buf); + ut_assertok(ops->set_value(dev, offset, 1)); + ut_asserteq(1, ops->get_value(dev, offset)); + + /* Make it an input */ + ut_assertok(ops->direction_input(dev, offset)); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: input: 1 [x] testing", buf); + sandbox_gpio_set_value(dev, offset, 0); + ut_asserteq(0, sandbox_gpio_get_value(dev, offset)); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: input: 0 [x] testing", buf); + + ut_assertok(gpio_free(gpio)); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b4: input: 0 [ ]", buf); + + /* Check the 'a' bank also */ + ut_assertok(gpio_lookup_name("a15", &dev, &offset, &gpio)); + ut_asserteq_str(dev->name, "base-gpios"); + ut_asserteq(15, offset); + ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 15, gpio); + + name = gpio_get_bank_info(dev, &offset_count); + ut_asserteq_str("a", name); + ut_asserteq(20, offset_count); + + return 0; +} +DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that sandbox anonymous GPIOs work correctly */ +static int dm_test_gpio_anon(struct dm_test_state *dms) +{ + unsigned int offset, gpio; + struct udevice *dev; + const char *name; + int offset_count; + + /* And the anonymous bank */ + ut_assertok(gpio_lookup_name("14", &dev, &offset, &gpio)); + ut_asserteq_str(dev->name, "gpio_sandbox"); + ut_asserteq(14, offset); + ut_asserteq(14, gpio); + + name = gpio_get_bank_info(dev, &offset_count); + ut_asserteq_ptr(NULL, name); + ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT, offset_count); + + return 0; +} +DM_TEST(dm_test_gpio_anon, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that gpio_requestf() works as expected */ +static int dm_test_gpio_requestf(struct dm_test_state *dms) +{ + unsigned int offset, gpio; + struct udevice *dev; + char buf[80]; + + ut_assertok(gpio_lookup_name("b5", &dev, &offset, &gpio)); + ut_assertok(gpio_requestf(gpio, "testing %d %s", 1, "hi")); + sandbox_gpio_set_direction(dev, offset, 1); + sandbox_gpio_set_value(dev, offset, 1); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b5: output: 1 [x] testing 1 hi", buf); + + return 0; +} +DM_TEST(dm_test_gpio_requestf, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that gpio_request() copies its string */ +static int dm_test_gpio_copy(struct dm_test_state *dms) +{ + unsigned int offset, gpio; + struct udevice *dev; + char buf[80], name[10]; + + ut_assertok(gpio_lookup_name("b6", &dev, &offset, &gpio)); + strcpy(name, "odd_name"); + ut_assertok(gpio_request(gpio, name)); + sandbox_gpio_set_direction(dev, offset, 1); + sandbox_gpio_set_value(dev, offset, 1); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b6: output: 1 [x] odd_name", buf); + strcpy(name, "nothing"); + ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf))); + ut_asserteq_str("b6: output: 1 [x] odd_name", buf); + + return 0; +} +DM_TEST(dm_test_gpio_copy, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that we don't leak memory with GPIOs */ +static int dm_test_gpio_leak(struct dm_test_state *dms) +{ + ut_assertok(dm_test_gpio(dms)); + ut_assertok(dm_test_gpio_anon(dms)); + ut_assertok(dm_test_gpio_requestf(dms)); + ut_assertok(dm_leak_check_end(dms)); + + return 0; +} +DM_TEST(dm_test_gpio_leak, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that we can find GPIOs using phandles */ +static int dm_test_gpio_phandles(struct dm_test_state *dms) +{ + struct gpio_desc desc, desc_list[8], desc_list2[8]; + struct udevice *dev, *gpio_a, *gpio_b; + + ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 0, &dev)); + ut_asserteq_str("a-test", dev->name); + + ut_assertok(gpio_request_by_name(dev, "test-gpios", 1, &desc, 0)); + ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio_a)); + ut_assertok(uclass_get_device(UCLASS_GPIO, 2, &gpio_b)); + ut_asserteq_str("base-gpios", gpio_a->name); + ut_asserteq(true, !!device_active(gpio_a)); + ut_asserteq_ptr(gpio_a, desc.dev); + ut_asserteq(4, desc.offset); + /* GPIOF_INPUT is the sandbox GPIO driver default */ + ut_asserteq(GPIOF_INPUT, gpio_get_function(gpio_a, 4, NULL)); + ut_assertok(dm_gpio_free(dev, &desc)); + + ut_asserteq(-ENOENT, gpio_request_by_name(dev, "test-gpios", 3, &desc, + 0)); + ut_asserteq_ptr(NULL, desc.dev); + ut_asserteq(desc.offset, 0); + ut_asserteq(-ENOENT, gpio_request_by_name(dev, "test-gpios", 5, &desc, + 0)); + + /* Last GPIO is ignord as it comes after <0> */ + ut_asserteq(3, gpio_request_list_by_name(dev, "test-gpios", desc_list, + ARRAY_SIZE(desc_list), 0)); + ut_asserteq(-EBUSY, gpio_request_list_by_name(dev, "test-gpios", + desc_list2, + ARRAY_SIZE(desc_list2), + 0)); + ut_assertok(gpio_free_list(dev, desc_list, 3)); + ut_asserteq(3, gpio_request_list_by_name(dev, "test-gpios", desc_list, + ARRAY_SIZE(desc_list), + GPIOD_IS_OUT | + GPIOD_IS_OUT_ACTIVE)); + ut_asserteq_ptr(gpio_a, desc_list[0].dev); + ut_asserteq(1, desc_list[0].offset); + ut_asserteq_ptr(gpio_a, desc_list[1].dev); + ut_asserteq(4, desc_list[1].offset); + ut_asserteq_ptr(gpio_b, desc_list[2].dev); + ut_asserteq(5, desc_list[2].offset); + ut_asserteq(1, dm_gpio_get_value(desc_list)); + ut_assertok(gpio_free_list(dev, desc_list, 3)); + + ut_asserteq(6, gpio_request_list_by_name(dev, "test2-gpios", desc_list, + ARRAY_SIZE(desc_list), 0)); + /* This was set to output previously, so still will be */ + ut_asserteq(GPIOF_OUTPUT, gpio_get_function(gpio_a, 1, NULL)); + + /* Active low should invert the input value */ + ut_asserteq(GPIOF_INPUT, gpio_get_function(gpio_b, 6, NULL)); + ut_asserteq(1, dm_gpio_get_value(&desc_list[2])); + + ut_asserteq(GPIOF_INPUT, gpio_get_function(gpio_b, 7, NULL)); + ut_asserteq(GPIOF_OUTPUT, gpio_get_function(gpio_b, 8, NULL)); + ut_asserteq(0, dm_gpio_get_value(&desc_list[4])); + ut_asserteq(GPIOF_OUTPUT, gpio_get_function(gpio_b, 9, NULL)); + ut_asserteq(1, dm_gpio_get_value(&desc_list[5])); + + + return 0; +} +DM_TEST(dm_test_gpio_phandles, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/i2c.c b/test/dm/i2c.c new file mode 100644 index 0000000000..ef88372d56 --- /dev/null +++ b/test/dm/i2c.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Note: Test coverage does not include 10-bit addressing + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const int busnum; +static const int chip = 0x2c; + +/* Test that we can find buses and chips */ +static int dm_test_i2c_find(struct dm_test_state *dms) +{ + struct udevice *bus, *dev; + const int no_chip = 0x10; + + ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_I2C, busnum, + false, &bus)); + + /* + * i2c_post_bind() will bind devices to chip selects. Check this then + * remove the emulation and the slave device. + */ + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); + ut_assertok(dm_i2c_probe(bus, chip, 0, &dev)); + ut_asserteq(-ENODEV, dm_i2c_probe(bus, no_chip, 0, &dev)); + ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)); + + return 0; +} +DM_TEST(dm_test_i2c_find, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_i2c_read_write(struct dm_test_state *dms) +{ + struct udevice *bus, *dev; + uint8_t buf[5]; + + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); + ut_assertok(i2c_get_chip(bus, chip, 1, &dev)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf))); + ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\0AB\0", sizeof(buf))); + + return 0; +} +DM_TEST(dm_test_i2c_read_write, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_i2c_speed(struct dm_test_state *dms) +{ + struct udevice *bus, *dev; + uint8_t buf[5]; + + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); + ut_assertok(i2c_get_chip(bus, chip, 1, &dev)); + ut_assertok(i2c_set_bus_speed(bus, 100000)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(i2c_set_bus_speed(bus, 400000)); + ut_asserteq(400000, i2c_get_bus_speed(bus)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5)); + + return 0; +} +DM_TEST(dm_test_i2c_speed, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_i2c_offset_len(struct dm_test_state *dms) +{ + struct udevice *bus, *dev; + uint8_t buf[5]; + + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); + ut_assertok(i2c_get_chip(bus, chip, 1, &dev)); + ut_assertok(i2c_set_chip_offset_len(dev, 1)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + + /* This is not supported by the uclass */ + ut_asserteq(-EINVAL, i2c_set_chip_offset_len(dev, 5)); + + return 0; +} +DM_TEST(dm_test_i2c_offset_len, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_i2c_probe_empty(struct dm_test_state *dms) +{ + struct udevice *bus, *dev; + + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); + ut_assertok(dm_i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev)); + + return 0; +} +DM_TEST(dm_test_i2c_probe_empty, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_i2c_bytewise(struct dm_test_state *dms) +{ + struct udevice *bus, *dev; + struct udevice *eeprom; + uint8_t buf[5]; + + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); + ut_assertok(i2c_get_chip(bus, chip, 1, &dev)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf))); + + /* Tell the EEPROM to only read/write one register at a time */ + ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom)); + ut_assertnonnull(eeprom); + sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_SINGLE_BYTE); + + /* Now we only get the first byte - the rest will be 0xff */ + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf))); + + /* If we do a separate transaction for each byte, it works */ + ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf))); + + /* This will only write A */ + ut_assertok(i2c_set_chip_flags(dev, 0)); + ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf))); + + /* Check that the B was ignored */ + ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\0A\0\0\0", sizeof(buf))); + + /* Now write it again with the new flags, it should work */ + ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS)); + ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf))); + + ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS | + DM_I2C_CHIP_RD_ADDRESS)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "\0\0AB\0\0", sizeof(buf))); + + /* Restore defaults */ + sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_NONE); + ut_assertok(i2c_set_chip_flags(dev, 0)); + + return 0; +} +DM_TEST(dm_test_i2c_bytewise, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_i2c_offset(struct dm_test_state *dms) +{ + struct udevice *eeprom; + struct udevice *dev; + uint8_t buf[5]; + + ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev)); + + /* Do a transfer so we can find the emulator */ + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom)); + + /* Offset length 0 */ + sandbox_i2c_eeprom_set_offset_len(eeprom, 0); + ut_assertok(i2c_set_chip_offset_len(dev, 0)); + ut_assertok(dm_i2c_write(dev, 10 /* ignored */, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "AB\0\0\0\0", sizeof(buf))); + + /* Offset length 1 */ + sandbox_i2c_eeprom_set_offset_len(eeprom, 1); + ut_assertok(i2c_set_chip_offset_len(dev, 1)); + ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0, buf, 5)); + ut_assertok(memcmp(buf, "ABAB\0", sizeof(buf))); + + /* Offset length 2 */ + sandbox_i2c_eeprom_set_offset_len(eeprom, 2); + ut_assertok(i2c_set_chip_offset_len(dev, 2)); + ut_assertok(dm_i2c_write(dev, 0x210, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0x210, buf, 5)); + ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf))); + + /* Offset length 3 */ + sandbox_i2c_eeprom_set_offset_len(eeprom, 2); + ut_assertok(i2c_set_chip_offset_len(dev, 2)); + ut_assertok(dm_i2c_write(dev, 0x410, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0x410, buf, 5)); + ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf))); + + /* Offset length 4 */ + sandbox_i2c_eeprom_set_offset_len(eeprom, 2); + ut_assertok(i2c_set_chip_offset_len(dev, 2)); + ut_assertok(dm_i2c_write(dev, 0x420, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0x420, buf, 5)); + ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf))); + + /* Restore defaults */ + sandbox_i2c_eeprom_set_offset_len(eeprom, 1); + + return 0; +} +DM_TEST(dm_test_i2c_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/sf.c b/test/dm/sf.c new file mode 100644 index 0000000000..08098a18b8 --- /dev/null +++ b/test/dm/sf.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Test that sandbox SPI flash works correctly */ +static int dm_test_spi_flash(struct dm_test_state *dms) +{ + /* + * Create an empty test file and run the SPI flash tests. This is a + * long way from being a unit test, but it does test SPI device and + * emulator binding, probing, the SPI flash emulator including + * device tree decoding, plus the file-based backing store of SPI. + * + * More targeted tests could be created to perform the above steps + * one at a time. This might not increase test coverage much, but + * it would make bugs easier to find. It's not clear whether the + * benefit is worth the extra complexity. + */ + ut_asserteq(0, run_command_list( + "sb save hostfs - 0 spi.bin 200000;" + "sf probe;" + "sf test 0 10000", -1, 0)); + /* + * Since we are about to destroy all devices, we must tell sandbox + * to forget the emulation device + */ + sandbox_sf_unbind_emul(state_get_current(), 0, 0); + + return 0; +} +DM_TEST(dm_test_spi_flash, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/spi.c b/test/dm/spi.c new file mode 100644 index 0000000000..c7ee65207b --- /dev/null +++ b/test/dm/spi.c @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Test that we can find buses and chip-selects */ +static int dm_test_spi_find(struct dm_test_state *dms) +{ + struct sandbox_state *state = state_get_current(); + struct spi_slave *slave; + struct udevice *bus, *dev; + const int busnum = 0, cs = 0, mode = 0, speed = 1000000, cs_b = 1; + struct spi_cs_info info; + int of_offset; + + ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_SPI, busnum, + false, &bus)); + + /* + * spi_post_bind() will bind devices to chip selects. Check this then + * remove the emulation and the slave device. + */ + ut_asserteq(0, uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus)); + ut_assertok(spi_cs_info(bus, cs, &info)); + of_offset = info.dev->of_offset; + device_remove(info.dev); + device_unbind(info.dev); + + /* + * Even though the device is gone, the sandbox SPI drivers always + * reports that CS 0 is present + */ + ut_assertok(spi_cs_info(bus, cs, &info)); + ut_asserteq_ptr(NULL, info.dev); + + /* This finds nothing because we removed the device */ + ut_asserteq(-ENODEV, spi_find_bus_and_cs(busnum, cs, &bus, &dev)); + ut_asserteq(-ENODEV, spi_get_bus_and_cs(busnum, cs, speed, mode, + NULL, 0, &bus, &slave)); + + /* + * This forces the device to be re-added, but there is no emulation + * connected so the probe will fail. We require that bus is left + * alone on failure, and that the spi_get_bus_and_cs() does not add + * a 'partially-inited' device. + */ + ut_asserteq(-ENODEV, spi_find_bus_and_cs(busnum, cs, &bus, &dev)); + ut_asserteq(-ENOENT, spi_get_bus_and_cs(busnum, cs, speed, mode, + "spi_flash_std", "name", &bus, + &slave)); + sandbox_sf_unbind_emul(state_get_current(), busnum, cs); + ut_assertok(spi_cs_info(bus, cs, &info)); + ut_asserteq_ptr(NULL, info.dev); + + /* Add the emulation and try again */ + ut_assertok(sandbox_sf_bind_emul(state, busnum, cs, bus, of_offset, + "name")); + ut_assertok(spi_find_bus_and_cs(busnum, cs, &bus, &dev)); + ut_assertok(spi_get_bus_and_cs(busnum, cs, speed, mode, + "spi_flash_std", "name", &bus, &slave)); + + ut_assertok(spi_cs_info(bus, cs, &info)); + ut_asserteq_ptr(info.dev, slave->dev); + + /* We should be able to add something to another chip select */ + ut_assertok(sandbox_sf_bind_emul(state, busnum, cs_b, bus, of_offset, + "name")); + ut_assertok(spi_get_bus_and_cs(busnum, cs_b, speed, mode, + "spi_flash_std", "name", &bus, &slave)); + ut_assertok(spi_cs_info(bus, cs_b, &info)); + ut_asserteq_ptr(info.dev, slave->dev); + + /* + * Since we are about to destroy all devices, we must tell sandbox + * to forget the emulation device + */ + sandbox_sf_unbind_emul(state_get_current(), busnum, cs); + sandbox_sf_unbind_emul(state_get_current(), busnum, cs_b); + + return 0; +} +DM_TEST(dm_test_spi_find, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that sandbox SPI works correctly */ +static int dm_test_spi_xfer(struct dm_test_state *dms) +{ + struct spi_slave *slave; + struct udevice *bus; + const int busnum = 0, cs = 0, mode = 0; + const char dout[5] = {0x9f}; + unsigned char din[5]; + + ut_assertok(spi_get_bus_and_cs(busnum, cs, 1000000, mode, NULL, 0, + &bus, &slave)); + ut_assertok(spi_claim_bus(slave)); + ut_assertok(spi_xfer(slave, 40, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END)); + ut_asserteq(0xff, din[0]); + ut_asserteq(0x20, din[1]); + ut_asserteq(0x20, din[2]); + ut_asserteq(0x15, din[3]); + spi_release_bus(slave); + + /* + * Since we are about to destroy all devices, we must tell sandbox + * to forget the emulation device + */ +#ifdef CONFIG_DM_SPI_FLASH + sandbox_sf_unbind_emul(state_get_current(), busnum, cs); +#endif + + return 0; +} +DM_TEST(dm_test_spi_xfer, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/test-dm.sh b/test/dm/test-dm.sh new file mode 100755 index 0000000000..8ebc39297c --- /dev/null +++ b/test/dm/test-dm.sh @@ -0,0 +1,14 @@ +#!/bin/sh + +die() { + echo $1 + exit 1 +} + +NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor) +dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb +make O=sandbox sandbox_config || die "Cannot configure U-Boot" +make O=sandbox -s -j${NUM_CPUS} || die "Cannot build U-Boot" +dd if=/dev/zero of=spi.bin bs=1M count=2 +./sandbox/u-boot -d test/dm/test.dtb -c "dm test" +rm spi.bin diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c new file mode 100644 index 0000000000..bc6a6e721d --- /dev/null +++ b/test/dm/test-driver.c @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +int dm_testdrv_op_count[DM_TEST_OP_COUNT]; +static struct dm_test_state *dms = &global_test_state; + +static int testdrv_ping(struct udevice *dev, int pingval, int *pingret) +{ + const struct dm_test_pdata *pdata = dev_get_platdata(dev); + struct dm_test_priv *priv = dev_get_priv(dev); + + *pingret = pingval + pdata->ping_add; + priv->ping_total += *pingret; + + return 0; +} + +static const struct test_ops test_ops = { + .ping = testdrv_ping, +}; + +static int test_bind(struct udevice *dev) +{ + /* Private data should not be allocated */ + ut_assert(!dev_get_priv(dev)); + + dm_testdrv_op_count[DM_TEST_OP_BIND]++; + return 0; +} + +static int test_probe(struct udevice *dev) +{ + struct dm_test_priv *priv = dev_get_priv(dev); + + /* Private data should be allocated */ + ut_assert(priv); + + dm_testdrv_op_count[DM_TEST_OP_PROBE]++; + priv->ping_total += DM_TEST_START_TOTAL; + return 0; +} + +static int test_remove(struct udevice *dev) +{ + /* Private data should still be allocated */ + ut_assert(dev_get_priv(dev)); + + dm_testdrv_op_count[DM_TEST_OP_REMOVE]++; + return 0; +} + +static int test_unbind(struct udevice *dev) +{ + /* Private data should not be allocated */ + ut_assert(!dev->priv); + + dm_testdrv_op_count[DM_TEST_OP_UNBIND]++; + return 0; +} + +U_BOOT_DRIVER(test_drv) = { + .name = "test_drv", + .id = UCLASS_TEST, + .ops = &test_ops, + .bind = test_bind, + .probe = test_probe, + .remove = test_remove, + .unbind = test_unbind, + .priv_auto_alloc_size = sizeof(struct dm_test_priv), +}; + +U_BOOT_DRIVER(test2_drv) = { + .name = "test2_drv", + .id = UCLASS_TEST, + .ops = &test_ops, + .bind = test_bind, + .probe = test_probe, + .remove = test_remove, + .unbind = test_unbind, + .priv_auto_alloc_size = sizeof(struct dm_test_priv), +}; + +static int test_manual_drv_ping(struct udevice *dev, int pingval, int *pingret) +{ + *pingret = pingval + 2; + + return 0; +} + +static const struct test_ops test_manual_ops = { + .ping = test_manual_drv_ping, +}; + +static int test_manual_bind(struct udevice *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_BIND]++; + + return 0; +} + +static int test_manual_probe(struct udevice *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_PROBE]++; + if (!dms->force_fail_alloc) + dev->priv = calloc(1, sizeof(struct dm_test_priv)); + if (!dev->priv) + return -ENOMEM; + + return 0; +} + +static int test_manual_remove(struct udevice *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_REMOVE]++; + return 0; +} + +static int test_manual_unbind(struct udevice *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_UNBIND]++; + return 0; +} + +U_BOOT_DRIVER(test_manual_drv) = { + .name = "test_manual_drv", + .id = UCLASS_TEST, + .ops = &test_manual_ops, + .bind = test_manual_bind, + .probe = test_manual_probe, + .remove = test_manual_remove, + .unbind = test_manual_unbind, +}; + +U_BOOT_DRIVER(test_pre_reloc_drv) = { + .name = "test_pre_reloc_drv", + .id = UCLASS_TEST, + .ops = &test_manual_ops, + .bind = test_manual_bind, + .probe = test_manual_probe, + .remove = test_manual_remove, + .unbind = test_manual_unbind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c new file mode 100644 index 0000000000..b8ee9599a2 --- /dev/null +++ b/test/dm/test-fdt.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret) +{ + const struct dm_test_pdata *pdata = dev->platdata; + struct dm_test_priv *priv = dev_get_priv(dev); + + *pingret = pingval + pdata->ping_add; + priv->ping_total += *pingret; + + return 0; +} + +static const struct test_ops test_ops = { + .ping = testfdt_drv_ping, +}; + +static int testfdt_ofdata_to_platdata(struct udevice *dev) +{ + struct dm_test_pdata *pdata = dev_get_platdata(dev); + + pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "ping-add", -1); + pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, + "ping-expect"); + + return 0; +} + +static int testfdt_drv_probe(struct udevice *dev) +{ + struct dm_test_priv *priv = dev_get_priv(dev); + + priv->ping_total += DM_TEST_START_TOTAL; + + /* + * If this device is on a bus, the uclass_flag will be set before + * calling this function. This is used by + * dm_test_bus_child_pre_probe_uclass(). + */ + priv->uclass_total += priv->uclass_flag; + + return 0; +} + +static const struct udevice_id testfdt_ids[] = { + { + .compatible = "denx,u-boot-fdt-test", + .data = DM_TEST_TYPE_FIRST }, + { + .compatible = "google,another-fdt-test", + .data = DM_TEST_TYPE_SECOND }, + { } +}; + +U_BOOT_DRIVER(testfdt_drv) = { + .name = "testfdt_drv", + .of_match = testfdt_ids, + .id = UCLASS_TEST_FDT, + .ofdata_to_platdata = testfdt_ofdata_to_platdata, + .probe = testfdt_drv_probe, + .ops = &test_ops, + .priv_auto_alloc_size = sizeof(struct dm_test_priv), + .platdata_auto_alloc_size = sizeof(struct dm_test_pdata), +}; + +/* From here is the testfdt uclass code */ +int testfdt_ping(struct udevice *dev, int pingval, int *pingret) +{ + const struct test_ops *ops = device_get_ops(dev); + + if (!ops->ping) + return -ENOSYS; + + return ops->ping(dev, pingval, pingret); +} + +UCLASS_DRIVER(testfdt) = { + .name = "testfdt", + .id = UCLASS_TEST_FDT, + .flags = DM_UC_FLAG_SEQ_ALIAS, +}; + +int dm_check_devices(struct dm_test_state *dms, int num_devices) +{ + struct udevice *dev; + int ret; + int i; + + /* + * Now check that the ping adds are what we expect. This is using the + * ping-add property in each node. + */ + for (i = 0; i < num_devices; i++) { + uint32_t base; + + ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev); + ut_assert(!ret); + + /* + * Get the 'ping-expect' property, which tells us what the + * ping add should be. We don't use the platdata because we + * want to test the code that sets that up + * (testfdt_drv_probe()). + */ + base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, + "ping-expect"); + debug("dev=%d, base=%d: %s\n", i, base, + fdt_get_name(gd->fdt_blob, dev->of_offset, NULL)); + + ut_assert(!dm_check_operations(dms, dev, base, + dev_get_priv(dev))); + } + + return 0; +} + +/* Test that FDT-based binding works correctly */ +static int dm_test_fdt(struct dm_test_state *dms) +{ + const int num_devices = 6; + struct udevice *dev; + struct uclass *uc; + int ret; + int i; + + ret = dm_scan_fdt(gd->fdt_blob, false); + ut_assert(!ret); + + ret = uclass_get(UCLASS_TEST_FDT, &uc); + ut_assert(!ret); + + /* These are num_devices compatible root-level device tree nodes */ + ut_asserteq(num_devices, list_count_items(&uc->dev_head)); + + /* Each should have platform data but no private data */ + for (i = 0; i < num_devices; i++) { + ret = uclass_find_device(UCLASS_TEST_FDT, i, &dev); + ut_assert(!ret); + ut_assert(!dev_get_priv(dev)); + ut_assert(dev->platdata); + } + + ut_assertok(dm_check_devices(dms, num_devices)); + + return 0; +} +DM_TEST(dm_test_fdt, 0); + +static int dm_test_fdt_pre_reloc(struct dm_test_state *dms) +{ + struct uclass *uc; + int ret; + + ret = dm_scan_fdt(gd->fdt_blob, true); + ut_assert(!ret); + + ret = uclass_get(UCLASS_TEST_FDT, &uc); + ut_assert(!ret); + + /* These is only one pre-reloc device */ + ut_asserteq(1, list_count_items(&uc->dev_head)); + + return 0; +} +DM_TEST(dm_test_fdt_pre_reloc, 0); + +/* Test that sequence numbers are allocated properly */ +static int dm_test_fdt_uclass_seq(struct dm_test_state *dms) +{ + struct udevice *dev; + + /* A few basic santiy tests */ + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_FDT, 3, true, &dev)); + ut_asserteq_str("b-test", dev->name); + + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_FDT, 8, true, &dev)); + ut_asserteq_str("a-test", dev->name); + + ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 5, + true, &dev)); + ut_asserteq_ptr(NULL, dev); + + /* Test aliases */ + ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 6, &dev)); + ut_asserteq_str("e-test", dev->name); + + ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 7, + true, &dev)); + + /* + * Note that c-test nodes are not probed since it is not a top-level + * node + */ + ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 3, &dev)); + ut_asserteq_str("b-test", dev->name); + + /* + * d-test wants sequence number 3 also, but it can't have it because + * b-test gets it first. + */ + ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 2, &dev)); + ut_asserteq_str("d-test", dev->name); + + /* d-test actually gets 0 */ + ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 0, &dev)); + ut_asserteq_str("d-test", dev->name); + + /* initially no one wants seq 1 */ + ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_TEST_FDT, 1, + &dev)); + ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 0, &dev)); + ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 4, &dev)); + + /* But now that it is probed, we can find it */ + ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 1, &dev)); + ut_asserteq_str("f-test", dev->name); + + return 0; +} +DM_TEST(dm_test_fdt_uclass_seq, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that we can find a device by device tree offset */ +static int dm_test_fdt_offset(struct dm_test_state *dms) +{ + const void *blob = gd->fdt_blob; + struct udevice *dev; + int node; + + node = fdt_path_offset(blob, "/e-test"); + ut_assert(node > 0); + ut_assertok(uclass_get_device_by_of_offset(UCLASS_TEST_FDT, node, + &dev)); + ut_asserteq_str("e-test", dev->name); + + /* This node should not be bound */ + node = fdt_path_offset(blob, "/junk"); + ut_assert(node > 0); + ut_asserteq(-ENODEV, uclass_get_device_by_of_offset(UCLASS_TEST_FDT, + node, &dev)); + + /* This is not a top level node so should not be probed */ + node = fdt_path_offset(blob, "/some-bus/c-test@5"); + ut_assert(node > 0); + ut_asserteq(-ENODEV, uclass_get_device_by_of_offset(UCLASS_TEST_FDT, + node, &dev)); + + return 0; +} +DM_TEST(dm_test_fdt_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/test-main.c b/test/dm/test-main.c new file mode 100644 index 0000000000..90ca81092f --- /dev/null +++ b/test/dm/test-main.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct dm_test_state global_test_state; + +/* Get ready for testing */ +static int dm_test_init(struct dm_test_state *dms) +{ + memset(dms, '\0', sizeof(*dms)); + gd->dm_root = NULL; + memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count)); + + ut_assertok(dm_init()); + dms->root = dm_root(); + + return 0; +} + +/* Ensure all the test devices are probed */ +static int do_autoprobe(struct dm_test_state *dms) +{ + struct udevice *dev; + int ret; + + /* Scanning the uclass is enough to probe all the devices */ + for (ret = uclass_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_next_device(&dev)) + ; + + return ret; +} + +static int dm_test_destroy(struct dm_test_state *dms) +{ + int id; + + for (id = 0; id < UCLASS_COUNT; id++) { + struct uclass *uc; + + /* + * If the uclass doesn't exist we don't want to create it. So + * check that here before we call uclass_find_device()/ + */ + uc = uclass_find(id); + if (!uc) + continue; + ut_assertok(uclass_destroy(uc)); + } + + return 0; +} + +int dm_test_main(void) +{ + struct dm_test *tests = ll_entry_start(struct dm_test, dm_test); + const int n_ents = ll_entry_count(struct dm_test, dm_test); + struct dm_test_state *dms = &global_test_state; + struct dm_test *test; + + /* + * If we have no device tree, or it only has a root node, then these + * tests clearly aren't going to work... + */ + if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) { + puts("Please run with test device tree:\n" + " dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb\n" + " ./u-boot -d test/dm/test.dtb\n"); + ut_assert(gd->fdt_blob); + } + + printf("Running %d driver model tests\n", n_ents); + + for (test = tests; test < tests + n_ents; test++) { + printf("Test: %s\n", test->name); + ut_assertok(dm_test_init(dms)); + + dms->start = mallinfo(); + if (test->flags & DM_TESTF_SCAN_PDATA) + ut_assertok(dm_scan_platdata(false)); + if (test->flags & DM_TESTF_PROBE_TEST) + ut_assertok(do_autoprobe(dms)); + if (test->flags & DM_TESTF_SCAN_FDT) + ut_assertok(dm_scan_fdt(gd->fdt_blob, false)); + + if (test->func(dms)) + break; + + ut_assertok(dm_test_destroy(dms)); + } + + printf("Failures: %d\n", dms->fail_count); + + return 0; +} diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c new file mode 100644 index 0000000000..017e097928 --- /dev/null +++ b/test/dm/test-uclass.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct dm_test_state *dms = &global_test_state; + +int test_ping(struct udevice *dev, int pingval, int *pingret) +{ + const struct test_ops *ops = device_get_ops(dev); + + if (!ops->ping) + return -ENOSYS; + + return ops->ping(dev, pingval, pingret); +} + +static int test_post_bind(struct udevice *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_POST_BIND]++; + + return 0; +} + +static int test_pre_unbind(struct udevice *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]++; + + return 0; +} + +static int test_post_probe(struct udevice *dev) +{ + struct udevice *prev = list_entry(dev->uclass_node.prev, + struct udevice, uclass_node); + + struct dm_test_uclass_perdev_priv *priv = dev->uclass_priv; + struct uclass *uc = dev->uclass; + + dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]++; + ut_assert(priv); + ut_assert(device_active(dev)); + priv->base_add = 0; + if (dms->skip_post_probe) + return 0; + if (&prev->uclass_node != &uc->dev_head) { + struct dm_test_uclass_perdev_priv *prev_uc_priv + = prev->uclass_priv; + struct dm_test_pdata *pdata = prev->platdata; + + ut_assert(pdata); + ut_assert(prev_uc_priv); + priv->base_add = prev_uc_priv->base_add + pdata->ping_add; + } + + return 0; +} + +static int test_pre_remove(struct udevice *dev) +{ + dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]++; + + return 0; +} + +static int test_init(struct uclass *uc) +{ + dm_testdrv_op_count[DM_TEST_OP_INIT]++; + ut_assert(uc->priv); + + return 0; +} + +static int test_destroy(struct uclass *uc) +{ + dm_testdrv_op_count[DM_TEST_OP_DESTROY]++; + + return 0; +} + +UCLASS_DRIVER(test) = { + .name = "test", + .id = UCLASS_TEST, + .post_bind = test_post_bind, + .pre_unbind = test_pre_unbind, + .post_probe = test_post_probe, + .pre_remove = test_pre_remove, + .init = test_init, + .destroy = test_destroy, + .priv_auto_alloc_size = sizeof(struct dm_test_uclass_priv), + .per_device_auto_alloc_size = sizeof(struct dm_test_uclass_perdev_priv), +}; diff --git a/test/dm/test.dts b/test/dm/test.dts new file mode 100644 index 0000000000..84024a44a3 --- /dev/null +++ b/test/dm/test.dts @@ -0,0 +1,152 @@ +/dts-v1/; + +/ { + model = "sandbox"; + compatible = "sandbox"; + #address-cells = <1>; + #size-cells = <0>; + + aliases { + console = &uart0; + i2c0 = "/i2c@0"; + spi0 = "/spi@0"; + testfdt6 = "/e-test"; + testbus3 = "/some-bus"; + testfdt0 = "/some-bus/c-test@0"; + testfdt1 = "/some-bus/c-test@1"; + testfdt3 = "/b-test"; + testfdt5 = "/some-bus/c-test@5"; + testfdt8 = "/a-test"; + }; + + uart0: serial { + compatible = "sandbox,serial"; + u-boot,dm-pre-reloc; + }; + + a-test { + reg = <0>; + compatible = "denx,u-boot-fdt-test"; + ping-expect = <0>; + ping-add = <0>; + u-boot,dm-pre-reloc; + test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>, + <0>, <&gpio_a 12>; + test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>, + <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>, + <&gpio_b 9 0xc 3 2 1>; + }; + + junk { + reg = <1>; + compatible = "not,compatible"; + }; + + no-compatible { + reg = <2>; + }; + + b-test { + reg = <3>; + compatible = "denx,u-boot-fdt-test"; + ping-expect = <3>; + ping-add = <3>; + }; + + some-bus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "denx,u-boot-test-bus"; + reg = <3>; + ping-expect = <4>; + ping-add = <4>; + c-test@5 { + compatible = "denx,u-boot-fdt-test"; + reg = <5>; + ping-expect = <5>; + ping-add = <5>; + }; + c-test@0 { + compatible = "denx,u-boot-fdt-test"; + reg = <0>; + ping-expect = <6>; + ping-add = <6>; + }; + c-test@1 { + compatible = "denx,u-boot-fdt-test"; + reg = <1>; + ping-expect = <7>; + ping-add = <7>; + }; + }; + + d-test { + reg = <3>; + ping-expect = <6>; + ping-add = <6>; + compatible = "google,another-fdt-test"; + }; + + e-test { + reg = <3>; + ping-expect = <6>; + ping-add = <6>; + compatible = "google,another-fdt-test"; + }; + + f-test { + compatible = "denx,u-boot-fdt-test"; + }; + + g-test { + compatible = "denx,u-boot-fdt-test"; + }; + + gpio_a: base-gpios { + compatible = "sandbox,gpio"; + gpio-controller; + #gpio-cells = <1>; + gpio-bank-name = "a"; + num-gpios = <20>; + }; + + gpio_b: extra-gpios { + compatible = "sandbox,gpio"; + gpio-controller; + #gpio-cells = <5>; + gpio-bank-name = "b"; + num-gpios = <10>; + }; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + compatible = "sandbox,i2c"; + clock-frequency = <100000>; + eeprom@2c { + reg = <0x2c>; + compatible = "i2c-eeprom"; + emul { + compatible = "sandbox,i2c-eeprom"; + sandbox,filename = "i2c.bin"; + sandbox,size = <256>; + }; + }; + }; + + spi@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + compatible = "sandbox,spi"; + cs-gpios = <0>, <&gpio_a 0>; + spi.bin@0 { + reg = <0>; + compatible = "spansion,m25p16", "spi-flash"; + spi-max-frequency = <40000000>; + sandbox,filename = "spi.bin"; + }; + }; + +}; diff --git a/test/dm/ut.c b/test/dm/ut.c new file mode 100644 index 0000000000..8b69bc2ab1 --- /dev/null +++ b/test/dm/ut.c @@ -0,0 +1,33 @@ +/* + * Simple unit test library for driver model + * + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct dm_test_state; + +void ut_fail(struct dm_test_state *dms, const char *fname, int line, + const char *func, const char *cond) +{ + printf("%s:%d, %s(): %s\n", fname, line, func, cond); + dms->fail_count++; +} + +void ut_failf(struct dm_test_state *dms, const char *fname, int line, + const char *func, const char *cond, const char *fmt, ...) +{ + va_list args; + + printf("%s:%d, %s(): %s: ", fname, line, func, cond); + va_start(args, fmt); + vprintf(fmt, args); + va_end(args); + putc('\n'); + dms->fail_count++; +} diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh new file mode 100755 index 0000000000..a4fb055962 --- /dev/null +++ b/test/fs/fs-test.sh @@ -0,0 +1,561 @@ +#!/bin/bash +# +# (C) Copyright 2014 Suriyan Ramasami +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Invoke this test script from U-Boot base directory as ./test/fs/fs-test.sh +# It currently tests the fs/sb and native commands for ext4 and fat partitions +# Expected results are as follows: +# EXT4 tests: +# fs-test.sb.ext4.out: Summary: PASS: 17 FAIL: 2 +# fs-test.ext4.out: Summary: PASS: 11 FAIL: 8 +# fs-test.fs.ext4.out: Summary: PASS: 11 FAIL: 8 +# FAT tests: +# fs-test.sb.fat.out: Summary: PASS: 17 FAIL: 2 +# fs-test.fat.out: Summary: PASS: 19 FAIL: 0 +# fs-test.fs.fat.out: Summary: PASS: 19 FAIL: 0 +# Total Summary: TOTAL PASS: 94 TOTAL FAIL: 20 + +# pre-requisite binaries list. +PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir" + +# All generated output files from this test will be in $OUT_DIR +# Hence everything is sandboxed. +OUT_DIR="sandbox/test/fs" + +# Location of generated sandbox u-boot +UBOOT="./sandbox/u-boot" + +# Our mount directory will be in the sandbox +MOUNT_DIR="${OUT_DIR}/mnt" + +# The file system image we create will have the $IMG prefix. +IMG="${OUT_DIR}/3GB" + +# $SMALL_FILE is the name of the 1MB file in the file system image +SMALL_FILE="1MB.file" + +# $BIG_FILE is the name of the 2.5GB file in the file system image +BIG_FILE="2.5GB.file" + +# $MD5_FILE will have the expected md5s when we do the test +# They shall have a suffix which represents their file system (ext4/fat) +MD5_FILE="${OUT_DIR}/md5s.list" + +# $OUT shall be the prefix of the test output. Their suffix will be .out +OUT="${OUT_DIR}/fs-test" + +# Full Path of the 1 MB file that shall be created in the fs image. +MB1="${MOUNT_DIR}/${SMALL_FILE}" +GB2p5="${MOUNT_DIR}/${BIG_FILE}" + +# ************************ +# * Functions start here * +# ************************ + +# Check if the prereq binaries exist, or exit +function check_prereq() { + for prereq in $PREREQ_BINS; do + if [ ! -x `which $prereq` ]; then + echo "Missing $prereq binary. Exiting!" + exit + fi + done + + # We use /dev/urandom to create files. Check if it exists. + if [ ! -c /dev/urandom ]; then + echo "Missing character special /dev/urandom. Exiting!" + exit + fi +} + +# If 1st param is "clean", then clean out the generated files and exit +function check_clean() { + if [ "$1" = "clean" ]; then + rm -rf "$OUT_DIR" + echo "Cleaned up generated files. Exiting" + exit + fi +} + +# Generate sandbox U-Boot - gleaned from /test/dm/test-dm.sh +function compile_sandbox() { + unset CROSS_COMPILE + NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor) + make O=sandbox sandbox_config + make O=sandbox -s -j${NUM_CPUS} + + # Check if U-Boot exists + if [ ! -x "$UBOOT" ]; then + echo "$UBOOT does not exist or is not executable" + echo "Build error?" + echo "Please run this script as ./test/fs/`basename $0`" + exit + fi +} + +# Clean out all generated files other than the file system images +# We save time by not deleting and recreating the file system images +function prepare_env() { + rm -f ${MD5_FILE}.* ${OUT}.* + mkdir ${OUT_DIR} +} + +# 1st parameter is the name of the image file to be created +# 2nd parameter is the filesystem - fat ext4 etc +# -F cant be used with fat as it means something else. +function create_image() { + # Create image if not already present - saves time, while debugging + if [ "$2" = "ext4" ]; then + MKFS_OPTION="-F" + else + MKFS_OPTION="" + fi + if [ ! -f "$1" ]; then + fallocate -l 3G "$1" &> /dev/null + mkfs -t "$2" $MKFS_OPTION "$1" &> /dev/null + if [ $? -ne 0 -a "$2" = "fat" ]; then + # If we fail and we did fat, try vfat. + mkfs -t vfat $MKFS_OPTION "$1" &> /dev/null + fi + fi +} + +# 1st parameter is the FS type: fat/ext4 +# 2nd parameter is the name of small file +# Returns filename which can be used for fat or ext4 for writing +function fname_for_write() { + case $1 in + ext4) + # ext4 needs absolute path name of file + echo /${2}.w + ;; + + *) + echo ${2}.w + ;; + esac +} + +# 1st parameter is image file +# 2nd parameter is file system type - fat/ext4 +# 3rd parameter is name of small file +# 4th parameter is name of big file +# 5th parameter is fs/nonfs/sb - to dictate generic fs commands or +# otherwise or sb hostfs +# 6th parameter is the directory path for the files. Its "" for generic +# fs and ext4/fat and full patch for sb hostfs +# UBOOT is set in env +function test_image() { + addr="0x01000008" + length="0x00100000" + + case "$2" in + fat) + PREFIX="fat" + WRITE="write" + ;; + + ext4) + PREFIX="ext4" + WRITE="write" + ;; + + *) + echo "Unhandled filesystem $2. Exiting!" + exit + ;; + esac + + case "$5" in + fs) + PREFIX="" + WRITE="save" + SUFFIX=" 0:0" + ;; + + nonfs) + SUFFIX=" 0:0" + ;; + + sb) + PREFIX="sb " + WRITE="save" + SUFFIX="fs -" + ;; + + *) + echo "Unhandled mode $5. Exiting!" + exit + ;; + + esac + + if [ -z "$6" ]; then + FILE_WRITE=`fname_for_write $2 $3` + FILE_SMALL=$3 + FILE_BIG=$4 + else + FILE_WRITE=$6/`fname_for_write $2 $3` + FILE_SMALL=$6/$3 + FILE_BIG=$6/$4 + fi + + # In u-boot commands, stands for host or hostfs + # hostfs maps to the host fs. + # host maps to the "sb bind" that we do + + $UBOOT << EOF +sb=$5 +setenv bind 'if test "\$sb" != sb; then sb bind 0 "$1"; fi' +run bind +# Test Case 1 - ls +${PREFIX}ls host${SUFFIX} $6 +# +# We want ${PREFIX}size host 0:0 $3 for host commands and +# sb size hostfs - $3 for hostfs commands. +# 1MB is 0x0010 0000 +# Test Case 2 - size of small file +${PREFIX}size host${SUFFIX} $FILE_SMALL +printenv filesize +setenv filesize + +# 2.5GB (1024*1024*2500) is 0x9C40 0000 +# Test Case 3 - size of big file +${PREFIX}size host${SUFFIX} $FILE_BIG +printenv filesize +setenv filesize + +# Notes about load operation +# If I use 0x01000000 I get DMA misaligned error message +# Last two parameters are size and offset. + +# Test Case 4a - Read full 1MB of small file +${PREFIX}load host${SUFFIX} $addr $FILE_SMALL +printenv filesize +# Test Case 4b - Read full 1MB of small file +md5sum $addr \$filesize +setenv filesize + +# Test Case 5a - First 1MB of big file +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x0 +printenv filesize +# Test Case 5b - First 1MB of big file +md5sum $addr \$filesize +setenv filesize + +# fails for ext as no offset support +# Test Case 6a - Last 1MB of big file +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x9C300000 +printenv filesize +# Test Case 6b - Last 1MB of big file +md5sum $addr \$filesize +setenv filesize + +# fails for ext as no offset support +# Test Case 7a - One from the last 1MB chunk of 2GB +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF00000 +printenv filesize +# Test Case 7b - One from the last 1MB chunk of 2GB +md5sum $addr \$filesize +setenv filesize + +# fails for ext as no offset support +# Test Case 8a - One from the start 1MB chunk from 2GB +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x80000000 +printenv filesize +# Test Case 8b - One from the start 1MB chunk from 2GB +md5sum $addr \$filesize +setenv filesize + +# fails for ext as no offset support +# Test Case 9a - One 1MB chunk crossing the 2GB boundary +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF80000 +printenv filesize +# Test Case 9b - One 1MB chunk crossing the 2GB boundary +md5sum $addr \$filesize +setenv filesize + +# Generic failure case +# Test Case 10 - 2MB chunk from the last 1MB of big file +${PREFIX}load host${SUFFIX} $addr $FILE_BIG 0x00200000 0x9C300000 +printenv filesize +# + +# Read 1MB from small file +${PREFIX}load host${SUFFIX} $addr $FILE_SMALL +# Write it back to test the writes +# Test Case 11a - Check that the write succeeded +${PREFIX}${WRITE} host${SUFFIX} $addr $FILE_WRITE \$filesize +mw.b $addr 00 100 +${PREFIX}load host${SUFFIX} $addr $FILE_WRITE +# Test Case 11b - Check md5 of written to is same as the one read from +md5sum $addr \$filesize +setenv filesize +# +reset + +EOF +} + +# 1st argument is the name of the image file. +# 2nd argument is the file where we generate the md5s of the files +# generated with the appropriate start and length that we use to test. +# It creates the necessary files in the image to test. +# $GB2p5 is the path of the big file (2.5 GB) +# $MB1 is the path of the small file (1 MB) +# $MOUNT_DIR is the path we can use to mount the image file. +function create_files() { + # Mount the image so we can populate it. + mkdir -p "$MOUNT_DIR" + sudo mount -o loop,rw "$1" "$MOUNT_DIR" + + # Create big file in this image. + # Note that we work only on the start 1MB, couple MBs in the 2GB range + # and the last 1 MB of the huge 2.5GB file. + # So, just put random values only in those areas. + if [ ! -f "${GB2p5}" ]; then + sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=1 \ + &> /dev/null + sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=2 seek=2047 \ + &> /dev/null + sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=1 seek=2499 \ + &> /dev/null + fi + + # Create a small file in this image. + if [ ! -f "${MB1}" ]; then + sudo dd if=/dev/urandom of="${MB1}" bs=1M count=1 \ + &> /dev/null + fi + + # Delete the small file which possibly is written as part of a + # previous test. + sudo rm -f "${MB1}.w" + + # Generate the md5sums of reads that we will test against small file + dd if="${MB1}" bs=1M skip=0 count=1 2> /dev/null | md5sum > "$2" + + # Generate the md5sums of reads that we will test against big file + # One from beginning of file. + dd if="${GB2p5}" bs=1M skip=0 count=1 \ + 2> /dev/null | md5sum >> "$2" + + # One from end of file. + dd if="${GB2p5}" bs=1M skip=2499 count=1 \ + 2> /dev/null | md5sum >> "$2" + + # One from the last 1MB chunk of 2GB + dd if="${GB2p5}" bs=1M skip=2047 count=1 \ + 2> /dev/null | md5sum >> "$2" + + # One from the start 1MB chunk from 2GB + dd if="${GB2p5}" bs=1M skip=2048 count=1 \ + 2> /dev/null | md5sum >> "$2" + + # One 1MB chunk crossing the 2GB boundary + dd if="${GB2p5}" bs=512K skip=4095 count=2 \ + 2> /dev/null | md5sum >> "$2" + + sync + sudo umount "$MOUNT_DIR" + rmdir "$MOUNT_DIR" +} + +# 1st parameter is the text to print +# if $? is 0 its a pass, else a fail +# As a side effect it shall update env variable PASS and FAIL +function pass_fail() { + if [ $? -eq 0 ]; then + echo pass - "$1" + PASS=$((PASS + 1)) + else + echo FAIL - "$1" + FAIL=$((FAIL + 1)) + fi +} + +# 1st parameter is the string which leads to an md5 generation +# 2nd parameter is the file we grep, for that string +# 3rd parameter is the name of the file which has md5s in it +# 4th parameter is the line # in the md5 file that we match it against +# This function checks if the md5 of the file in the sandbox matches +# that calculated while generating the file +# 5th parameter is the string to print with the result +check_md5() { + # md5sum in u-boot has output of form: + # md5 for 01000008 ... 01100007 ==> + # the 7th field is the actual md5 + md5_src=`grep -A3 "$1" "$2" | grep "md5 for"` + md5_src=($md5_src) + md5_src=${md5_src[6]} + + # The md5 list, each line is of the form: + # - + # the 2nd field is the actual md5 + md5_dst=`sed -n $4p $3` + md5_dst=($md5_dst) + md5_dst=${md5_dst[0]} + + # For a pass they should match. + [ "$md5_src" = "$md5_dst" ] + pass_fail "$5" +} + +# 1st parameter is the name of the output file to check +# 2nd parameter is the name of the file containing the md5 expected +# 3rd parameter is the name of the small file +# 4th parameter is the name of the big file +# 5th paramter is the name of the written file +# This function checks the output file for correct results. +function check_results() { + echo "** Start $1" + + PASS=0 + FAIL=0 + + # Check if the ls is showing correct results for 2.5 gb file + grep -A6 "Test Case 1 " "$1" | egrep -iq "2621440000 *$4" + pass_fail "TC1: ls of $4" + + # Check if the ls is showing correct results for 1 mb file + grep -A6 "Test Case 1 " "$1" | egrep -iq "1048576 *$3" + pass_fail "TC1: ls of $3" + + # Check size command on 1MB.file + egrep -A3 "Test Case 2 " "$1" | grep -q "filesize=100000" + pass_fail "TC2: size of $3" + + # Check size command on 2.5GB.file + egrep -A3 "Test Case 3 " "$1" | grep -q "filesize=9c400000" + pass_fail "TC3: size of $4" + + # Check read full mb of 1MB.file + grep -A6 "Test Case 4a " "$1" | grep -q "filesize=100000" + pass_fail "TC4: load of $3 size" + check_md5 "Test Case 4b " "$1" "$2" 1 "TC4: load from $3" + + # Check first mb of 2.5GB.file + grep -A6 "Test Case 5a " "$1" | grep -q "filesize=100000" + pass_fail "TC5: load of 1st MB from $4 size" + check_md5 "Test Case 5b " "$1" "$2" 2 "TC5: load of 1st MB from $4" + + # Check last mb of 2.5GB.file + grep -A6 "Test Case 6a " "$1" | grep -q "filesize=100000" + pass_fail "TC6: load of last MB from $4 size" + check_md5 "Test Case 6b " "$1" "$2" 3 "TC6: load of last MB from $4" + + # Check last 1mb chunk of 2gb from 2.5GB file + grep -A6 "Test Case 7a " "$1" | grep -q "filesize=100000" + pass_fail "TC7: load of last 1mb chunk of 2GB from $4 size" + check_md5 "Test Case 7b " "$1" "$2" 4 \ + "TC7: load of last 1mb chunk of 2GB from $4" + + # Check first 1mb chunk after 2gb from 2.5GB file + grep -A6 "Test Case 8a " "$1" | grep -q "filesize=100000" + pass_fail "TC8: load 1st MB chunk after 2GB from $4 size" + check_md5 "Test Case 8b " "$1" "$2" 5 \ + "TC8: load 1st MB chunk after 2GB from $4" + + # Check 1mb chunk crossing the 2gb boundary from 2.5GB file + grep -A6 "Test Case 9a " "$1" | grep -q "filesize=100000" + pass_fail "TC9: load 1MB chunk crossing 2GB boundary from $4 size" + check_md5 "Test Case 9b " "$1" "$2" 6 \ + "TC9: load 1MB chunk crossing 2GB boundary from $4" + + # Check 2mb chunk from the last 1MB of 2.5GB file - generic failure case + grep -A6 "Test Case 10 " "$1" | grep -q 'Error: "filesize" not defined' + pass_fail "TC10: load 2MB from the last 1MB of $4 - generic fail case" + + # Check 1mb chunk write + grep -A3 "Test Case 11a " "$1" | \ + egrep -q '1048576 bytes written|update journal' + pass_fail "TC11: 1MB write to $5 - write succeeded" + check_md5 "Test Case 11b " "$1" "$2" 1 \ + "TC11: 1MB write to $5 - content verified" + echo "** End $1" +} + +# Takes in one parameter which is "fs" or "nonfs", which then dictates +# if a fs test (size/load/save) or a nonfs test (fatread/extread) needs to +# be performed. +function test_fs_nonfs() { + echo "Creating files in $fs image if not already present." + create_files $IMAGE $MD5_FILE_FS + + OUT_FILE="${OUT}.fs.${fs}.out" + test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \ + > ${OUT_FILE} + check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \ + $WRITE_FILE + TOTAL_FAIL=$((TOTAL_FAIL + FAIL)) + TOTAL_PASS=$((TOTAL_PASS + PASS)) + echo "Summary: PASS: $PASS FAIL: $FAIL" + echo "--------------------------------------------" +} + +# ******************** +# * End of functions * +# ******************** + +check_clean "$1" +check_prereq +compile_sandbox +prepare_env + +# Track TOTAL_FAIL and TOTAL_PASS +TOTAL_FAIL=0 +TOTAL_PASS=0 + +# In each loop, for a given file system image, we test both the +# fs command, like load/size/write, the file system specific command +# like: ext4load/ext4size/ext4write and the sb load/ls/save commands. +for fs in ext4 fat; do + + echo "Creating $fs image if not already present." + IMAGE=${IMG}.${fs}.img + MD5_FILE_FS="${MD5_FILE}.${fs}" + create_image $IMAGE $fs + + # sb commands test + echo "Creating files in $fs image if not already present." + create_files $IMAGE $MD5_FILE_FS + + # Lets mount the image and test sb hostfs commands + mkdir -p "$MOUNT_DIR" + if [ "$fs" = "fat" ]; then + uid="uid=`id -u`" + else + uid="" + fi + sudo mount -o loop,rw,$uid "$IMAGE" "$MOUNT_DIR" + sudo chmod 777 "$MOUNT_DIR" + + OUT_FILE="${OUT}.sb.${fs}.out" + test_image $IMAGE $fs $SMALL_FILE $BIG_FILE sb `pwd`/$MOUNT_DIR \ + > ${OUT_FILE} + sudo umount "$MOUNT_DIR" + rmdir "$MOUNT_DIR" + + check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \ + $WRITE_FILE + TOTAL_FAIL=$((TOTAL_FAIL + FAIL)) + TOTAL_PASS=$((TOTAL_PASS + PASS)) + echo "Summary: PASS: $PASS FAIL: $FAIL" + echo "--------------------------------------------" + + test_fs_nonfs nonfs + test_fs_nonfs fs +done + +echo "Total Summary: TOTAL PASS: $TOTAL_PASS TOTAL FAIL: $TOTAL_FAIL" +echo "--------------------------------------------" +if [ $TOTAL_FAIL -eq 0 ]; then + echo "PASSED" + exit 0 +else + echo "FAILED" + exit 1 +fi diff --git a/test/image/test-fit.py b/test/image/test-fit.py index 7394df740a..e9e756a064 100755 --- a/test/image/test-fit.py +++ b/test/image/test-fit.py @@ -20,6 +20,9 @@ import struct import sys import tempfile +# Enable printing of all U-Boot output +DEBUG = True + # The 'command' library in patman is convenient for running commands base_path = os.path.dirname(sys.argv[0]) patman = os.path.join(base_path, '../../tools/patman') @@ -93,16 +96,20 @@ base_fdt = ''' # then do the 'bootm' command, then save out memory from the places where # we expect 'bootm' to write things. Then quit. base_script = ''' -sb load host 0 %(fit_addr)x %(fit)s +sb load hostfs 0 %(fit_addr)x %(fit)s fdt addr %(fit_addr)x bootm start %(fit_addr)x bootm loados -sb save host 0 %(kernel_out)s %(kernel_addr)x %(kernel_size)x -sb save host 0 %(fdt_out)s %(fdt_addr)x %(fdt_size)x -sb save host 0 %(ramdisk_out)s %(ramdisk_addr)x %(ramdisk_size)x +sb save hostfs 0 %(kernel_addr)x %(kernel_out)s %(kernel_size)x +sb save hostfs 0 %(fdt_addr)x %(fdt_out)s %(fdt_size)x +sb save hostfs 0 %(ramdisk_addr)x %(ramdisk_out)s %(ramdisk_size)x reset ''' +def debug_stdout(stdout): + if DEBUG: + print stdout + def make_fname(leaf): """Make a temporary filename @@ -328,6 +335,7 @@ def run_fit_test(mkimage, u_boot): # We could perhaps reduce duplication with some loss of readability set_test('Kernel load') stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd) + debug_stdout(stdout) if read_file(kernel) != read_file(kernel_out): fail('Kernel not loaded', stdout) if read_file(control_dtb) == read_file(fdt_out): @@ -352,6 +360,7 @@ def run_fit_test(mkimage, u_boot): params['fdt_load'] = 'load = <%#x>;' % params['fdt_addr'] fit = make_fit(mkimage, params) stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd) + debug_stdout(stdout) if read_file(kernel) != read_file(kernel_out): fail('Kernel not loaded', stdout) if read_file(control_dtb) != read_file(fdt_out): @@ -365,6 +374,7 @@ def run_fit_test(mkimage, u_boot): params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr'] fit = make_fit(mkimage, params) stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd) + debug_stdout(stdout) if read_file(ramdisk) != read_file(ramdisk_out): fail('Ramdisk not loaded', stdout) diff --git a/test/image/test-imagetools.sh b/test/image/test-imagetools.sh new file mode 100755 index 0000000000..952f975af1 --- /dev/null +++ b/test/image/test-imagetools.sh @@ -0,0 +1,226 @@ +#!/bin/bash +# +# Written by Guilherme Maciel Ferreira +# +# Sanity check for mkimage and dumpimage tools +# +# SPDX-License-Identifier: GPL-2.0+ +# +# To run this: +# +# make O=sandbox sandbox_config +# make O=sandbox +# ./test/image/test-imagetools.sh + +BASEDIR=sandbox +SRCDIR=${BASEDIR}/boot +IMAGE_NAME="v1.0-test" +IMAGE_MULTI=linux.img +IMAGE_FIT_ITS=linux.its +IMAGE_FIT_ITB=linux.itb +DATAFILE0=vmlinuz +DATAFILE1=initrd.img +DATAFILE2=System.map +DATAFILES="${DATAFILE0} ${DATAFILE1} ${DATAFILE2}" +TEST_OUT=test_output +MKIMAGE=${BASEDIR}/tools/mkimage +DUMPIMAGE=${BASEDIR}/tools/dumpimage +MKIMAGE_LIST=mkimage.list +DUMPIMAGE_LIST=dumpimage.list + +# Remove all the files we created +cleanup() +{ + local file + + for file in ${DATAFILES}; do + rm -f ${file} ${SRCDIR}/${file} + done + rm -f ${IMAGE_MULTI} + rm -f ${DUMPIMAGE_LIST} + rm -f ${MKIMAGE_LIST} + rm -f ${TEST_OUT} + rmdir ${SRCDIR} +} + +# Check that two files are the same +assert_equal() +{ + if ! diff -u $1 $2; then + echo "Failed." + cleanup + exit 1 + fi +} + +# Create some test files +create_files() +{ + local file + + mkdir -p ${SRCDIR} + for file in ${DATAFILES}; do + head -c $RANDOM /dev/urandom >${SRCDIR}/${file} + done +} + +# Run a command, echoing it first +do_cmd() +{ + local cmd="$@" + + echo "# ${cmd}" + ${cmd} 2>&1 +} + +# Run a command, redirecting output +# Args: +# redirect_file +# command... +do_cmd_redir() +{ + local redir="$1" + shift + local cmd="$@" + + echo "# ${cmd}" + ${cmd} >${redir} +} + +# Write files into an multi-file image +create_multi_image() +{ + local files="${SRCDIR}/${DATAFILE0}:${SRCDIR}/${DATAFILE1}" + files+=":${SRCDIR}/${DATAFILE2}" + + echo -e "\nBuilding multi-file image..." + do_cmd ${MKIMAGE} -A x86 -O linux -T multi -n \"${IMAGE_NAME}\" \ + -d ${files} ${IMAGE_MULTI} + echo "done." +} + +# Extract files from an multi-file image +extract_multi_image() +{ + echo -e "\nExtracting multi-file image contents..." + do_cmd ${DUMPIMAGE} -T multi -i ${IMAGE_MULTI} -p 0 ${DATAFILE0} + do_cmd ${DUMPIMAGE} -T multi -i ${IMAGE_MULTI} -p 1 ${DATAFILE1} + do_cmd ${DUMPIMAGE} -T multi -i ${IMAGE_MULTI} -p 2 ${DATAFILE2} + do_cmd ${DUMPIMAGE} -T multi -i ${IMAGE_MULTI} -p 2 ${DATAFILE2} -o ${TEST_OUT} + echo "done." +} + +# Write files into a FIT image +create_fit_image() +{ + echo " \ + /dts-v1/; \ + / { \ + description = \"FIT image\"; \ + #address-cells = <1>; \ + \ + images { \ + kernel@1 { \ + description = \"kernel\"; \ + data = /incbin/(\"${DATAFILE0}\"); \ + type = \"kernel\"; \ + arch = \"sandbox\"; \ + os = \"linux\"; \ + compression = \"gzip\"; \ + load = <0x40000>; \ + entry = <0x8>; \ + }; \ + ramdisk@1 { \ + description = \"filesystem\"; \ + data = /incbin/(\"${DATAFILE1}\"); \ + type = \"ramdisk\"; \ + arch = \"sandbox\"; \ + os = \"linux\"; \ + compression = \"none\"; \ + load = <0x80000>; \ + entry = <0x16>; \ + }; \ + fdt@1 { \ + description = \"device tree\"; \ + data = /incbin/(\"${DATAFILE2}\"); \ + type = \"flat_dt\"; \ + arch = \"sandbox\"; \ + compression = \"none\"; \ + }; \ + }; \ + configurations { \ + default = \"conf@1\"; \ + conf@1 { \ + kernel = \"kernel@1\"; \ + fdt = \"fdt@1\"; \ + }; \ + }; \ + }; \ + " > ${IMAGE_FIT_ITS} + + echo -e "\nBuilding FIT image..." + do_cmd ${MKIMAGE} -f ${IMAGE_FIT_ITS} ${IMAGE_FIT_ITB} + echo "done." +} + +# Extract files from a FIT image +extract_fit_image() +{ + echo -e "\nExtracting FIT image contents..." + do_cmd ${DUMPIMAGE} -T flat_dt -i ${IMAGE_FIT_ITB} -p 0 ${DATAFILE0} + do_cmd ${DUMPIMAGE} -T flat_dt -i ${IMAGE_FIT_ITB} -p 1 ${DATAFILE1} + do_cmd ${DUMPIMAGE} -T flat_dt -i ${IMAGE_FIT_ITB} -p 2 ${DATAFILE2} + do_cmd ${DUMPIMAGE} -T flat_dt -i ${IMAGE_FIT_ITB} -p 2 ${DATAFILE2} -o ${TEST_OUT} + echo "done." +} + +# List the contents of a file +# Args: +# image filename +list_image() +{ + local image="$1" + + echo -e "\nListing image contents..." + do_cmd_redir ${MKIMAGE_LIST} ${MKIMAGE} -l ${image} + do_cmd_redir ${DUMPIMAGE_LIST} ${DUMPIMAGE} -l ${image} + echo "done." +} + +main() +{ + local file + + create_files + + # Compress and extract multi-file images, compare the result + create_multi_image + extract_multi_image + for file in ${DATAFILES}; do + assert_equal ${file} ${SRCDIR}/${file} + done + assert_equal ${TEST_OUT} ${DATAFILE2} + + # List contents of multi-file image and compares output from tools + list_image ${IMAGE_MULTI} + assert_equal ${DUMPIMAGE_LIST} ${MKIMAGE_LIST} + + # Compress and extract FIT images, compare the result + create_fit_image + extract_fit_image + for file in ${DATAFILES}; do + assert_equal ${file} ${SRCDIR}/${file} + done + assert_equal ${TEST_OUT} ${DATAFILE2} + + # List contents of FIT image and compares output from tools + list_image ${IMAGE_FIT_ITB} + assert_equal ${DUMPIMAGE_LIST} ${MKIMAGE_LIST} + + # Remove files created + cleanup + + echo "Tests passed." +} + +main diff --git a/test/stdint/int-types.c b/test/stdint/int-types.c new file mode 100644 index 0000000000..2660084d94 --- /dev/null +++ b/test/stdint/int-types.c @@ -0,0 +1,13 @@ +#include +#include + +int test_types(void) +{ + uintptr_t uintptr = 0; + uint64_t uint64 = 0; + u64 u64_val = 0; + + printf("uintptr = %" PRIuPTR "\n", uintptr); + printf("uint64 = %" PRIu64 "\n", uint64); + printf("u64 = %" PRIu64 "\n", u64_val); +} diff --git a/test/stdint/test-includes.sh b/test/stdint/test-includes.sh new file mode 100755 index 0000000000..077bdc73a1 --- /dev/null +++ b/test/stdint/test-includes.sh @@ -0,0 +1,58 @@ +#!/bin/bash + +# Test script to check uintptr_t and 64-bit types for warnings +# +# It builds a few boards with different toolchains. If there are no warnings +# then all is well. +# +# Usage: +# +# Make sure that your toolchains are correct at the bottom of this file +# +# Then: +# ./test/stdint/test-includes.sh + +out=/tmp/test-includes.tmp + +try_test() { + local board=$1 + local arch=$2 + local soc=$3 + local gcc=$4 + local flags="$5" + + echo $@ + if ! which ${gcc} >/dev/null 2>&1; then + echo "Not found: ${gcc}" + return + fi + + rm -rf ${out} + mkdir -p ${out} + touch ${out}/config.h + mkdir -p ${out}/generated + touch ${out}/generated/generic-asm-offsets.h + mkdir -p ${out}/include/asm + ln -s $(pwd)/arch/${arch}/include/asm/arch-${soc} \ + ${out}/include/asm/arch + + cmd="${gcc} -c -D__KERNEL__ ${flags} \ + -fno-builtin -ffreestanding \ + -Iarch/${arch}/include \ + -Iinclude \ + -I${out} -I${out}/include \ + -include configs/${board}.h test/stdint/int-types.c \ + -o /dev/null" + $cmd +} + +# Run a test with and without CONFIG_USE_STDINT +try_both() { + try_test $@ + try_test $@ -DCONFIG_USE_STDINT +} + +# board arch soc path-to-gcc +try_both sandbox sandbox - gcc +try_both coreboot x86 - x86_64-linux-gnu-gcc +try_both seaboard arm tegra20 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux/bin/arm-linux-gnueabihf-gcc diff --git a/test/trace/test-trace.sh b/test/trace/test-trace.sh index aa02f09475..3e8651ed60 100755 --- a/test/trace/test-trace.sh +++ b/test/trace/test-trace.sh @@ -5,39 +5,25 @@ # Simple test script for tracing with sandbox -OUTPUT_DIR=sandbox TRACE_OPT="FTRACE=1" -fail() { - echo "Test failed: $1" - if [ -n ${tmp} ]; then - rm ${tmp} - fi - exit 1 -} - -build_uboot() { - echo "Build sandbox" - OPTS="O=${OUTPUT_DIR} ${TRACE_OPT}" - NUM_CPUS=$(grep -c processor /proc/cpuinfo) - make ${OPTS} sandbox_config - make ${OPTS} -s -j${NUM_CPUS} -} +BASE="$(dirname $0)/.." +. $BASE/common.sh run_trace() { echo "Run trace" ./${OUTPUT_DIR}/u-boot <${tmp} check_results ${tmp} rm ${tmp} diff --git a/test/ums/README b/test/ums/README new file mode 100644 index 0000000000..c80fbfefbf --- /dev/null +++ b/test/ums/README @@ -0,0 +1,30 @@ +UMS test script. + +ums_gadget_test.sh +================== + +Example usage: +1. On the target: + create UMS exportable partitions (with e.g. gpt write), or specify a + partition number (PART_NUM) as "-" to use the entire device + ums 0 mmc 0 +2. On the host: + sudo test/ums/ums_gadget_test.sh VID PID PART_NUM [-f FILE_SYSTEM] [test_file] + e.g. sudo test/ums/ums_gadget_test.sh 0525 a4a5 6 -f vfat ./dat_14M.img + +... where: + VID - UMS device USB Vendor ID + PID - UMS device USB Product ID + PART_NUM - is the partition number on which UMS operates or "-" to use the + whole device + +Information about available partitions on the target one can read with using +the 'mmc part' or 'part list' commands. + +The partition num (PART_NUM) can be specified as '-' for using the whole device. + +The [-f FILE_SYSTEM] optional switch allows for formatting target partition to +FILE_SYSTEM. + +The last, optional [test_file] parameter is for specifying the exact test file +to use. diff --git a/test/ums/ums_gadget_test.sh b/test/ums/ums_gadget_test.sh new file mode 100755 index 0000000000..9da486b266 --- /dev/null +++ b/test/ums/ums_gadget_test.sh @@ -0,0 +1,183 @@ +#! /bin/bash + +# Copyright (C) 2014 Samsung Electronics +# Lukasz Majewski +# +# UMS operation test script +# +# SPDX-License-Identifier: GPL-2.0+ + +clear + +COLOUR_RED="\33[31m" +COLOUR_GREEN="\33[32m" +COLOUR_ORANGE="\33[33m" +COLOUR_DEFAULT="\33[0m" + +DIR=./ +SUFFIX=img +RCV_DIR=rcv/ +LOG_FILE=./log/log-`date +%d-%m-%Y_%H-%M-%S` + +cd `dirname $0` +../dfu/dfu_gadget_test_init.sh 33M 97M + +cleanup () { + rm -rf $RCV_DIR $MNT_DIR +} + +control_c() +# run if user hits control-c +{ + echo -en "\n*** CTRL+C ***\n" + umount $MNT_DIR + cleanup + exit 0 +} + +# trap keyboard interrupt (control-c) +trap control_c SIGINT + +die () { + printf " $COLOUR_RED FAILED $COLOUR_DEFAULT \n" + cleanup + exit 1 +} + +calculate_md5sum () { + MD5SUM=`md5sum $1` + MD5SUM=`echo $MD5SUM | cut -d ' ' -f1` + echo "md5sum:"$MD5SUM +} + +ums_test_file () { + printf "$COLOUR_GREEN========================================================================================= $COLOUR_DEFAULT\n" + printf "File:$COLOUR_GREEN %s $COLOUR_DEFAULT\n" $1 + + mount /dev/$MEM_DEV $MNT_DIR + if [ -f $MNT_DIR/dat_* ]; then + rm $MNT_DIR/dat_* + fi + + cp ./$1 $MNT_DIR + + while true; do + umount $MNT_DIR > /dev/null 2>&1 + if [ $? -eq 0 ]; then + break + fi + printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n" + sleep 1 + done + + echo -n "TX: " + calculate_md5sum $1 + + MD5_TX=$MD5SUM + sleep 1 + N_FILE=$DIR$RCV_DIR${1:2}"_rcv" + + mount /dev/$MEM_DEV $MNT_DIR + cp $MNT_DIR/$1 $N_FILE || die $? + rm $MNT_DIR/$1 + umount $MNT_DIR + + echo -n "RX: " + calculate_md5sum $N_FILE + MD5_RX=$MD5SUM + + if [ "$MD5_TX" == "$MD5_RX" ]; then + printf " $COLOUR_GREEN -------> OK $COLOUR_DEFAULT \n" + else + printf " $COLOUR_RED -------> FAILED $COLOUR_DEFAULT \n" + cleanup + exit 1 + fi +} + +printf "$COLOUR_GREEN========================================================================================= $COLOUR_DEFAULT\n" +echo "U-boot UMS test program" + +if [ $EUID -ne 0 ]; then + echo "You must be root to do this." 1>&2 + exit 100 +fi + +if [ $# -lt 3 ]; then + echo "Wrong number of arguments" + echo "Example:" + echo "sudo ./ums_gadget_test.sh VID PID PART_NUM [-f ext4] [test_file]" + die +fi + +MNT_DIR="/mnt/tmp-ums-test" + +VID=$1; shift +PID=$1; shift +PART_NUM=$1; shift + +if [ "$1" == "-f" ]; then + shift + FS_TO_FORMAT=$1; shift +fi + +TEST_FILE=$1 + +for f in `find /sys -type f -name idProduct`; do + d=`dirname ${f}` + if [ `cat ${d}/idVendor` != "${VID}" ]; then + continue + fi + if [ `cat ${d}/idProduct` != "${PID}" ]; then + continue + fi + USB_DEV=${d} + break +done + +if [ -z "${USB_DEV}" ]; then + echo "Connect target" + echo "e.g. ums 0 mmc 0" + exit 1 +fi + +MEM_DEV=`find $USB_DEV -type d -name "sd[a-z]" | awk -F/ '{print $(NF)}' -` + +mkdir -p $RCV_DIR +if [ ! -d $MNT_DIR ]; then + mkdir -p $MNT_DIR +fi + +if [ "$PART_NUM" == "-" ]; then + PART_NUM="" +fi +MEM_DEV=$MEM_DEV$PART_NUM + +if [ -n "$FS_TO_FORMAT" ]; then + echo -n "Formatting partition /dev/$MEM_DEV to $FS_TO_FORMAT" + mkfs -t $FS_TO_FORMAT /dev/$MEM_DEV > /dev/null 2>&1 + if [ $? -eq 0 ]; then + printf " $COLOUR_GREEN DONE $COLOUR_DEFAULT \n" + else + die + fi +fi + +printf "Mount: /dev/$MEM_DEV \n" + +if [ -n "$TEST_FILE" ]; then + if [ ! -e $TEST_FILE ]; then + echo "No file: $TEST_FILE" + die + fi + ums_test_file $TEST_FILE +else + for file in $DIR*.$SUFFIX + do + ums_test_file $file + done +fi + +cleanup + +exit 0 diff --git a/test/vboot/sign-configs.its b/test/vboot/sign-configs-sha1.its similarity index 100% rename from test/vboot/sign-configs.its rename to test/vboot/sign-configs-sha1.its diff --git a/test/vboot/sign-configs-sha256.its b/test/vboot/sign-configs-sha256.its new file mode 100644 index 0000000000..1b3432ec14 --- /dev/null +++ b/test/vboot/sign-configs-sha256.its @@ -0,0 +1,45 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel@1 { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + hash@1 { + algo = "sha256"; + }; + }; + fdt@1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + hash@1 { + algo = "sha256"; + }; + }; + }; + configurations { + default = "conf@1"; + conf@1 { + kernel = "kernel@1"; + fdt = "fdt@1"; + signature@1 { + algo = "sha256,rsa2048"; + key-name-hint = "dev"; + sign-images = "fdt", "kernel"; + }; + }; + }; +}; diff --git a/test/vboot/sign-images.its b/test/vboot/sign-images-sha1.its similarity index 100% rename from test/vboot/sign-images.its rename to test/vboot/sign-images-sha1.its diff --git a/test/vboot/sign-images-sha256.its b/test/vboot/sign-images-sha256.its new file mode 100644 index 0000000000..e6aa9fc409 --- /dev/null +++ b/test/vboot/sign-images-sha256.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel@1 { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + signature@1 { + algo = "sha256,rsa2048"; + key-name-hint = "dev"; + }; + }; + fdt@1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + signature@1 { + algo = "sha256,rsa2048"; + key-name-hint = "dev"; + }; + }; + }; + configurations { + default = "conf@1"; + conf@1 { + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +}; diff --git a/test/vboot/vboot_test.sh b/test/vboot/vboot_test.sh index bb2c6051c8..6d7abb82bd 100755 --- a/test/vboot/vboot_test.sh +++ b/test/vboot/vboot_test.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # # Copyright (c) 2013, Google Inc. # @@ -14,7 +14,7 @@ set -e run_uboot() { echo -n "Test Verified Boot Run: $1: " ${uboot} -d sandbox-u-boot.dtb >${tmp} -c ' -sb load host 0 100 test.fit; +sb load hostfs - 100 test.fit; fdt addr 100; bootm 100; reset' @@ -47,61 +47,99 @@ O=$(readlink -f ${O}) dtc="-I dts -O dtb -p 2000" uboot="${O}/u-boot" mkimage="${O}/tools/mkimage" +fit_check_sign="${O}/tools/fit_check_sign" keys="${dir}/dev-keys" echo ${mkimage} -D "${dtc}" echo "Build keys" mkdir -p ${keys} +PUBLIC_EXPONENT=${1} + +if [ -z "${PUBLIC_EXPONENT}" ]; then + PUBLIC_EXPONENT=65537 +fi + # Create an RSA key pair -openssl genrsa -F4 -out ${keys}/dev.key 2048 2>/dev/null +openssl genpkey -algorithm RSA -out ${keys}/dev.key \ + -pkeyopt rsa_keygen_bits:2048 \ + -pkeyopt rsa_keygen_pubexp:${PUBLIC_EXPONENT} 2>/dev/null # Create a certificate containing the public key openssl req -batch -new -x509 -key ${keys}/dev.key -out ${keys}/dev.crt pushd ${dir} >/dev/null -# Compile our device tree files for kernel and U-Boot (CONFIG_OF_CONTROL) -dtc -p 0x1000 sandbox-kernel.dts -O dtb -o sandbox-kernel.dtb -dtc -p 0x1000 sandbox-u-boot.dts -O dtb -o sandbox-u-boot.dtb +function do_test { + echo do $sha test + # Compile our device tree files for kernel and U-Boot + dtc -p 0x1000 sandbox-kernel.dts -O dtb -o sandbox-kernel.dtb + dtc -p 0x1000 sandbox-u-boot.dts -O dtb -o sandbox-u-boot.dtb + + # Create a number kernel image with zeroes + head -c 5000 /dev/zero >test-kernel.bin + + # Build the FIT, but don't sign anything yet + echo Build FIT with signed images + ${mkimage} -D "${dtc}" -f sign-images-$sha.its test.fit >${tmp} + + run_uboot "unsigned signatures:" "dev-" -# Create a number kernel image with zeroes -head -c 5000 /dev/zero >test-kernel.bin + # Sign images with our dev keys + echo Sign images + ${mkimage} -D "${dtc}" -F -k dev-keys -K sandbox-u-boot.dtb \ + -r test.fit >${tmp} -# Build the FIT, but don't sign anything yet -echo Build FIT with signed images -${mkimage} -D "${dtc}" -f sign-images.its test.fit >${tmp} + run_uboot "signed images" "dev+" -run_uboot "unsigned signatures:" "dev-" -# Sign images with our dev keys -echo Sign images -${mkimage} -D "${dtc}" -F -k dev-keys -K sandbox-u-boot.dtb -r test.fit >${tmp} + # Create a fresh .dtb without the public keys + dtc -p 0x1000 sandbox-u-boot.dts -O dtb -o sandbox-u-boot.dtb -run_uboot "signed images" "dev+" + echo Build FIT with signed configuration + ${mkimage} -D "${dtc}" -f sign-configs-$sha.its test.fit >${tmp} + run_uboot "unsigned config" $sha"+ OK" -# Create a fresh .dtb without the public keys -dtc -p 0x1000 sandbox-u-boot.dts -O dtb -o sandbox-u-boot.dtb + # Sign images with our dev keys + echo Sign images + ${mkimage} -D "${dtc}" -F -k dev-keys -K sandbox-u-boot.dtb \ + -r test.fit >${tmp} -echo Build FIT with signed configuration -${mkimage} -D "${dtc}" -f sign-configs.its test.fit >${tmp} + run_uboot "signed config" "dev+" -run_uboot "unsigned config" "sha1+ OK" + echo check signed config on the host + if ! ${fit_check_sign} -f test.fit -k sandbox-u-boot.dtb >${tmp}; then + echo + echo "Verified boot key check on host failed, output follows:" + cat ${tmp} + false + else + if ! grep -q "dev+" ${tmp}; then + echo + echo "Verified boot key check failed, output follows:" + cat ${tmp} + false + else + echo "OK" + fi + fi -# Sign images with our dev keys -echo Sign images -${mkimage} -D "${dtc}" -F -k dev-keys -K sandbox-u-boot.dtb -r test.fit >${tmp} + run_uboot "signed config" "dev+" -run_uboot "signed config" "dev+" + # Increment the first byte of the signature, which should cause failure + sig=$(fdtget -t bx test.fit /configurations/conf@1/signature@1 value) + newbyte=$(printf %x $((0x${sig:0:2} + 1))) + sig="${newbyte} ${sig:2}" + fdtput -t bx test.fit /configurations/conf@1/signature@1 value ${sig} -# Increment the first byte of the signature, which should cause failure -sig=$(fdtget -t bx test.fit /configurations/conf@1/signature@1 value) -newbyte=$(printf %x $((0x${sig:0:2} + 1))) -sig="${newbyte} ${sig:2}" -fdtput -t bx test.fit /configurations/conf@1/signature@1 value ${sig} + run_uboot "signed config with bad hash" "Bad Data Hash" +} -run_uboot "signed config with bad hash" "Bad Data Hash" +sha=sha1 +do_test +sha=sha256 +do_test popd >/dev/null diff --git a/tools/.gitignore b/tools/.gitignore index a7fee26cdd..9bc9fecf7b 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -1,21 +1,27 @@ +/atmel_pmecc_params /bmp_logo /envcrc +/fit_check_sign +/fit_info /gen_eth_addr +/ifdtool /img2srec /kwboot +/dumpimage /mkenvimage /mkimage +/mkexynosspl /mpc86x_clk /mxsboot +/mksunxiboot /ncb -/ncp /proftool +/relocate-rela /ubsha1 /xway-swap-bytes -/*.exe /easylogo/easylogo -/env/crc32.c -/env/fw_printenv /gdb/gdbcont /gdb/gdbsend -/kernel-doc/docproc + +/lib/ +/common/ diff --git a/tools/Makefile b/tools/Makefile index 33fad6badb..578f8505d3 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -5,23 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -TOOLSUBDIRS = kernel-doc - -# -# Include this after HOSTOS HOSTARCH check -# so that we can act intelligently. -# -include $(TOPDIR)/config.mk - -# -# toolchains targeting win32 generate .exe files -# -ifneq (,$(findstring WIN32 ,$(shell $(HOSTCC) -E -dM -xc /dev/null))) -SFX = .exe -else -SFX = -endif - # Enable all the config-independent tools ifneq ($(HOST_TOOLS_ALL),) CONFIG_LCD_LOGO = y @@ -32,6 +15,9 @@ CONFIG_NETCONSOLE = y CONFIG_SHA1_CHECK_UB_IMG = y endif +subdir-$(HOST_TOOLS_ALL) += easylogo +subdir-$(HOST_TOOLS_ALL) += gdb + # Merge all the different vars for envcrc into one ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y ENVCRC-$(CONFIG_ENV_IS_IN_DATAFLASH) = y @@ -43,78 +29,153 @@ ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y) -# Generated executable files -BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) -BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX) -BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX) -BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX) -BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) -BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) -BIN_FILES-y += mkenvimage$(SFX) -BIN_FILES-y += mkimage$(SFX) -BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX) -BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX) -BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) -BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) -BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) -BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX) -BIN_FILES-y += proftool(SFX) - -# Source files which exist outside the tools directory -EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o -EXT_OBJ_FILES-y += common/image.o -EXT_OBJ_FILES-$(CONFIG_FIT) += common/image-fit.o -EXT_OBJ_FILES-y += common/image-sig.o -EXT_OBJ_FILES-y += lib/crc32.o -EXT_OBJ_FILES-y += lib/md5.o -EXT_OBJ_FILES-y += lib/sha1.o - -# Source files located in the tools directory -OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o -OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o -NOPED_OBJ_FILES-y += default_image.o -NOPED_OBJ_FILES-y += proftool.o -OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o -NOPED_OBJ_FILES-y += fit_image.o -OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o -OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o -OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o -NOPED_OBJ_FILES-y += aisimage.o -NOPED_OBJ_FILES-y += kwbimage.o -NOPED_OBJ_FILES-y += pblimage.o -NOPED_OBJ_FILES-y += imximage.o -NOPED_OBJ_FILES-y += image-host.o -NOPED_OBJ_FILES-y += omapimage.o -NOPED_OBJ_FILES-y += mkenvimage.o -NOPED_OBJ_FILES-y += mkimage.o -OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o -OBJ_FILES-$(CONFIG_MX23) += mxsboot.o -OBJ_FILES-$(CONFIG_MX28) += mxsboot.o -OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o -NOPED_OBJ_FILES-y += os_support.o -OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o -NOPED_OBJ_FILES-y += ublimage.o -OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o +hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params -# Don't build by default -#ifeq ($(ARCH),ppc) -#BIN_FILES-y += mpc86x_clk$(SFX) -#OBJ_FILES-y += mpc86x_clk.o -#endif +# TODO: CONFIG_CMD_LICENSE does not work +hostprogs-$(CONFIG_CMD_LICENSE) += bin2header +hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo +hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo +HOSTCFLAGS_bmp_logo.o := -pedantic + +hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc +envcrc-objs := envcrc.o lib/crc32.o common/env_embedded.o lib/sha1.o + +hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr +HOSTCFLAGS_gen_eth_addr.o := -pedantic + +hostprogs-$(CONFIG_CMD_LOADS) += img2srec +HOSTCFLAGS_img2srec.o := -pedantic + +hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes +HOSTCFLAGS_xway-swap-bytes.o := -pedantic +hostprogs-y += mkenvimage +mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o + +hostprogs-y += dumpimage mkimage +hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign + +FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o # Flattened device tree objects -LIBFDT_OBJ_FILES-y += fdt.o -LIBFDT_OBJ_FILES-y += fdt_ro.o -LIBFDT_OBJ_FILES-y += fdt_rw.o -LIBFDT_OBJ_FILES-y += fdt_strerror.o -LIBFDT_OBJ_FILES-y += fdt_wip.o +LIBFDT_OBJS := $(addprefix lib/libfdt/, \ + fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o) +RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \ + rsa-sign.o rsa-verify.o rsa-checksum.o \ + rsa-mod-exp.o) + +# common objs for dumpimage and mkimage +dumpimage-mkimage-objs := aisimage.o \ + atmelimage.o \ + $(FIT_SIG_OBJS-y) \ + common/bootm.o \ + lib/crc32.o \ + default_image.o \ + lib/fdtdec_common.o \ + lib/fdtdec.o \ + fit_common.o \ + fit_image.o \ + gpimage.o \ + gpimage-common.o \ + common/image-fit.o \ + image-host.o \ + common/image.o \ + imagetool.o \ + imximage.o \ + kwbimage.o \ + lib/md5.o \ + mxsimage.o \ + omapimage.o \ + os_support.o \ + pblimage.o \ + pbl_crc32.o \ + socfpgaimage.o \ + lib/sha1.o \ + lib/sha256.o \ + common/hash.o \ + ublimage.o \ + $(LIBFDT_OBJS) \ + $(RSA_OBJS-y) + +dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o +mkimage-objs := $(dumpimage-mkimage-objs) mkimage.o +fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o +fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o + +# TODO(sjg@chromium.org): Is this correct on Mac OS? + +ifneq ($(CONFIG_SOC_MX23)$(CONFIG_SOC_MX28),) +# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register +# the mxsimage support within tools/mxsimage.c . +HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS +endif + +ifdef CONFIG_FIT_SIGNATURE +# This affects include/image.h, but including the board config file +# is tricky, so manually define this options here. +HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE +endif + +# MXSImage needs LibSSL +ifneq ($(CONFIG_SOC_MX23)$(CONFIG_SOC_MX28)$(CONFIG_FIT_SIGNATURE),) +HOSTLOADLIBES_mkimage += -lssl -lcrypto +endif + +HOSTLOADLIBES_dumpimage := $(HOSTLOADLIBES_mkimage) +HOSTLOADLIBES_fit_info := $(HOSTLOADLIBES_mkimage) +HOSTLOADLIBES_fit_check_sign := $(HOSTLOADLIBES_mkimage) + +HOSTLDFLAGS += -T $(srctree)/tools/imagetool.lds + +hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl +hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl +HOSTCFLAGS_mkexynosspl.o := -pedantic -# RSA objects -RSA_OBJ_FILES-$(CONFIG_FIT_SIGNATURE) += rsa-sign.o +ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o +hostprogs-$(CONFIG_X86) += ifdtool + +hostprogs-$(CONFIG_SOC_MX23) += mxsboot +hostprogs-$(CONFIG_SOC_MX28) += mxsboot +HOSTCFLAGS_mxsboot.o := -pedantic + +hostprogs-$(CONFIG_SUNXI) += mksunxiboot + +hostprogs-$(CONFIG_NETCONSOLE) += ncb +hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1 + +ubsha1-objs := os_support.o ubsha1.o lib/sha1.o + +HOSTCFLAGS_ubsha1.o := -pedantic + +hostprogs-$(CONFIG_KIRKWOOD) += kwboot +hostprogs-$(CONFIG_ARMADA_XP) += kwboot +hostprogs-y += proftool +hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela + +# We build some files with extra pedantic flags to try to minimize things +# that won't build on some weird host compiler -- though there are lots of +# exceptions for files that aren't complaint. +HOSTCFLAGS_crc32.o := -pedantic +HOSTCFLAGS_md5.o := -pedantic +HOSTCFLAGS_sha1.o := -pedantic +HOSTCFLAGS_sha256.o := -pedantic + +# Don't build by default +#hostprogs-$(CONFIG_PPC) += mpc86x_clk +#HOSTCFLAGS_mpc86x_clk.o := -pedantic + +quiet_cmd_wrap = WRAP $@ +cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@ + +$(obj)/lib/%.c $(obj)/common/%.c: + $(call cmd,wrap) + +clean-dirs := lib common + +always := $(hostprogs-y) # Generated LCD/video logo -LOGO_H = $(OBJTREE)/include/bmp_logo.h -LOGO_DATA_H = $(OBJTREE)/include/bmp_logo_data.h +LOGO_H = $(objtree)/include/bmp_logo.h +LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_H) LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H) LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H) @@ -122,165 +183,54 @@ LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H) # Generic logo ifeq ($(LOGO_BMP),) -LOGO_BMP= logos/denx.bmp +LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp # Use board logo and fallback to vendor -ifneq ($(wildcard logos/$(BOARD).bmp),) -LOGO_BMP= logos/$(BOARD).bmp +ifneq ($(wildcard $(srctree)/$(src)/logos/$(BOARD).bmp),) +LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmp else -ifneq ($(wildcard logos/$(VENDOR).bmp),) -LOGO_BMP= logos/$(VENDOR).bmp +ifneq ($(wildcard $(srctree)/$(src)/logos/$(VENDOR).bmp),) +LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp endif endif endif # !LOGO_BMP -# now $(obj) is defined -HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/lib/rsa/,$(RSA_OBJ_FILES-y:.o=.c)) -BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y))) -LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y)) -RSA_OBJS := $(addprefix $(obj),$(RSA_OBJ_FILES-y)) - -# We cannot check CONFIG_FIT_SIGNATURE here since it is not set on the host -FIT_SIG_OBJ_FILES := image-sig.o -FIT_SIG_OBJS := $(addprefix $(obj),$(FIT_SIG_OBJ_FILES)) - -HOSTOBJS := $(addprefix $(obj),$(OBJ_FILES-y)) -NOPEDOBJS := $(addprefix $(obj),$(NOPED_OBJ_FILES-y)) - # # Use native tools and options # Define __KERNEL_STRICT_NAMES to prevent typedef overlaps +# Define _GNU_SOURCE to obtain the getline prototype from stdio.h # -HOSTCPPFLAGS = -include $(SRCTREE)/include/libfdt_env.h \ - -idirafter $(SRCTREE)/include \ - -idirafter $(OBJTREE)/include2 \ - -idirafter $(OBJTREE)/include \ - -I $(SRCTREE)/lib/libfdt \ - -I $(SRCTREE)/tools \ +HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \ + $(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \ + -I$(srctree)/lib/libfdt \ + -I$(srctree)/tools \ + -include $(srctree)/include/linux/kconfig.h \ + -Wno-variadic-macros \ -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ -DUSE_HOSTCC \ - -D__KERNEL_STRICT_NAMES - - -all: $(obj).depend $(BINS) $(LOGO-y) subdirs - -$(obj)bin2header$(SFX): $(obj)bin2header.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)bmp_logo$(SFX): $(obj)bmp_logo.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)proftool(SFX): $(obj)proftool.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)envcrc$(SFX): $(obj)crc32.o $(obj)env_embedded.o $(obj)envcrc.o $(obj)sha1.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - -$(obj)gen_eth_addr$(SFX): $(obj)gen_eth_addr.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)img2srec$(SFX): $(obj)img2srec.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o \ - $(obj)os_support.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)mkimage$(SFX): $(obj)aisimage.o \ - $(obj)crc32.o \ - $(obj)default_image.o \ - $(obj)fit_image.o \ - $(obj)image-fit.o \ - $(obj)image.o \ - $(obj)image-host.o \ - $(FIT_SIG_OBJS) \ - $(obj)imximage.o \ - $(obj)kwbimage.o \ - $(obj)pblimage.o \ - $(obj)md5.o \ - $(obj)mkimage.o \ - $(obj)os_support.o \ - $(obj)omapimage.o \ - $(obj)sha1.o \ - $(obj)ublimage.o \ - $(LIBFDT_OBJS) \ - $(RSA_OBJS) - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTLIBS) - $(HOSTSTRIP) $@ - -$(obj)mk$(BOARD)spl$(SFX): $(obj)mkexynosspl.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)mxsboot$(SFX): $(obj)mxsboot.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -$(obj)ncb$(SFX): $(obj)ncb.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ + -D__KERNEL_STRICT_NAMES \ + -D_GNU_SOURCE -$(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ +__build: $(LOGO-y) -$(obj)kwboot$(SFX): $(obj)kwboot.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ +$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP) + $(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@ -# Some of the tool objects need to be accessed from outside the tools directory -$(obj)%.o: $(SRCTREE)/common/%.c - $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< +$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP) + $(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@ -$(obj)%.o: $(SRCTREE)/lib/%.c - $(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $< +# Let clean descend into subdirs +subdir- += env -$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c - $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< +ifneq ($(CROSS_BUILD_TOOLS),) +HOSTCC = $(CC) -$(obj)%.o: $(SRCTREE)/lib/rsa/%.c - $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< +quiet_cmd_crosstools_strip = STRIP $^ + cmd_crosstools_strip = $(STRIP) $^; touch $@ +$(obj)/.strip: $(call objectify,$(filter $(always),$(hostprogs-y))) + $(call cmd,crosstools_strip) -subdirs: -ifeq ($(TOOLSUBDIRS),) - @: -else - @for dir in $(TOOLSUBDIRS) ; do \ - $(MAKE) \ - HOSTOS=$(HOSTOS) \ - HOSTARCH=$(HOSTARCH) \ - -C $$dir || exit 1 ; \ - done +always += .strip endif - -$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP) - $(obj)./bmp_logo --gen-info $(LOGO_BMP) > $@ - -$(LOGO_DATA_H): $(obj)bmp_logo $(LOGO_BMP) - $(obj)./bmp_logo --gen-data $(LOGO_BMP) > $@ - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +clean-files += .strip diff --git a/tools/aisimage.c b/tools/aisimage.c index cd89145867..9338342cb3 100644 --- a/tools/aisimage.c +++ b/tools/aisimage.c @@ -2,13 +2,10 @@ * (C) Copyright 2011 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ -/* Required to obtain the getline prototype from stdio.h */ -#define _GNU_SOURCE - -#include "mkimage.h" +#include "imagetool.h" #include "aisimage.h" #include @@ -179,7 +176,7 @@ static uint32_t *ais_insert_cmd_header(uint32_t cmd, uint32_t nargs, } -static uint32_t *ais_alloc_buffer(struct mkimage_params *params) +static uint32_t *ais_alloc_buffer(struct image_tool_params *params) { int dfd; struct stat sbuf; @@ -219,7 +216,7 @@ static uint32_t *ais_alloc_buffer(struct mkimage_params *params) return ptr; } -static uint32_t *ais_copy_image(struct mkimage_params *params, +static uint32_t *ais_copy_image(struct image_tool_params *params, uint32_t *aisptr) { @@ -255,7 +252,7 @@ static uint32_t *ais_copy_image(struct mkimage_params *params, } -static int aisimage_generate(struct mkimage_params *params, +static int aisimage_generate(struct image_tool_params *params, struct image_type_params *tparams) { FILE *fd = NULL; @@ -373,7 +370,7 @@ static int aisimage_check_image_types(uint8_t type) } static int aisimage_verify_header(unsigned char *ptr, int image_size, - struct mkimage_params *params) + struct image_tool_params *params) { struct ais_header *ais_hdr = (struct ais_header *)ptr; @@ -387,11 +384,11 @@ static int aisimage_verify_header(unsigned char *ptr, int image_size, } static void aisimage_set_header(void *ptr, struct stat *sbuf, int ifd, - struct mkimage_params *params) + struct image_tool_params *params) { } -int aisimage_check_params(struct mkimage_params *params) +int aisimage_check_params(struct image_tool_params *params) { if (!params) return CFG_INVALID; @@ -416,19 +413,17 @@ int aisimage_check_params(struct mkimage_params *params) /* * aisimage parameters */ -static struct image_type_params aisimage_params = { - .name = "TI Davinci AIS Boot Image support", - .header_size = 0, - .hdr = NULL, - .check_image_type = aisimage_check_image_types, - .verify_header = aisimage_verify_header, - .print_header = aisimage_print_header, - .set_header = aisimage_set_header, - .check_params = aisimage_check_params, - .vrec_header = aisimage_generate, -}; - -void init_ais_image_type(void) -{ - mkimage_register(&aisimage_params); -} +U_BOOT_IMAGE_TYPE( + aisimage, + "TI Davinci AIS Boot Image support", + 0, + NULL, + aisimage_check_params, + aisimage_verify_header, + aisimage_print_header, + aisimage_set_header, + NULL, + aisimage_check_image_types, + NULL, + aisimage_generate +); diff --git a/tools/aisimage.h b/tools/aisimage.h index 1f092dbc7e..e1aa3ef703 100644 --- a/tools/aisimage.h +++ b/tools/aisimage.h @@ -2,7 +2,7 @@ * (C) Copyright 2011 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _AISIMAGE_H_ diff --git a/tools/atmel_pmecc_params.c b/tools/atmel_pmecc_params.c new file mode 100644 index 0000000000..8eaf27f804 --- /dev/null +++ b/tools/atmel_pmecc_params.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2014 Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This is a host tool for generating an appropriate string out of board + * configuration. The string is required for correct generation of PMECC + * header which in turn is required for NAND flash booting of Atmel AT91 style + * hardware. + * + * See doc/README.atmel_pmecc for more information. + */ + +#include +#include + +static int pmecc_get_ecc_bytes(int cap, int sector_size) +{ + int m = 12 + sector_size / 512; + return (m * cap + 7) / 8; +} + +int main(int argc, char *argv[]) +{ + unsigned int use_pmecc = 0; + unsigned int sector_per_page; + unsigned int sector_size = CONFIG_PMECC_SECTOR_SIZE; + unsigned int oob_size = CONFIG_SYS_NAND_OOBSIZE; + unsigned int ecc_bits = CONFIG_PMECC_CAP; + unsigned int ecc_offset; + +#ifdef CONFIG_ATMEL_NAND_HW_PMECC + use_pmecc = 1; +#endif + + sector_per_page = CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_PMECC_SECTOR_SIZE; + ecc_offset = oob_size - + pmecc_get_ecc_bytes(ecc_bits, sector_size) * sector_per_page; + + printf("usePmecc=%d,", use_pmecc); + printf("sectorPerPage=%d,", sector_per_page); + printf("sectorSize=%d,", sector_size); + printf("spareSize=%d,", oob_size); + printf("eccBits=%d,", ecc_bits); + printf("eccOffset=%d", ecc_offset); + printf("\n"); + + exit(EXIT_SUCCESS); +} diff --git a/tools/atmelimage.c b/tools/atmelimage.c new file mode 100644 index 0000000000..5b72ac54a6 --- /dev/null +++ b/tools/atmelimage.c @@ -0,0 +1,340 @@ +/* + * (C) Copyright 2014 + * Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include "mkimage.h" + +#include + +#define pr_err(fmt, args...) fprintf(stderr, "atmelimage Error: " fmt, ##args) + +static int atmel_check_image_type(uint8_t type) +{ + if (type == IH_TYPE_ATMELIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static uint32_t nand_pmecc_header[52]; + +/* + * A helper struct for parsing the mkimage -n parameter + * + * Keep in same order as the configs array! + */ +static struct pmecc_config { + int use_pmecc; + int sector_per_page; + int spare_size; + int ecc_bits; + int sector_size; + int ecc_offset; +} pmecc; + +/* + * Strings used for configure the PMECC header via -n mkimage switch + * + * We estimate a coma separated list of key=value pairs. The mkimage -n + * parameter argument should not contain any whitespace. + * + * Keep in same order as struct pmecc_config! + */ +static const char * const configs[] = { + "usePmecc", + "sectorPerPage", + "spareSize", + "eccBits", + "sectorSize", + "eccOffset" +}; + +static int atmel_find_pmecc_parameter_in_token(const char *token) +{ + size_t pos; + char *param; + + debug("token: '%s'\n", token); + + for (pos = 0; pos < ARRAY_SIZE(configs); pos++) { + if (strncmp(token, configs[pos], strlen(configs[pos])) == 0) { + param = strstr(token, "="); + if (!param) + goto err; + + param++; + debug("\t%s parameter: '%s'\n", configs[pos], param); + + switch (pos) { + case 0: + pmecc.use_pmecc = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 1: + pmecc.sector_per_page = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 2: + pmecc.spare_size = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 3: + pmecc.ecc_bits = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 4: + pmecc.sector_size = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 5: + pmecc.ecc_offset = strtol(param, NULL, 10); + return EXIT_SUCCESS; + } + } + } + +err: + pr_err("Could not find parameter in token '%s'\n", token); + return EXIT_FAILURE; +} + +static int atmel_parse_pmecc_params(char *txt) +{ + char *token; + + token = strtok(txt, ","); + while (token != NULL) { + if (atmel_find_pmecc_parameter_in_token(token)) + return EXIT_FAILURE; + + token = strtok(NULL, ","); + } + + return EXIT_SUCCESS; +} + +static int atmel_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + uint32_t *ints = (uint32_t *)ptr; + size_t pos; + size_t size = image_size; + + /* check if we have an PMECC header attached */ + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + if (ints[pos] >> 28 != 0xC) + break; + + if (pos == ARRAY_SIZE(nand_pmecc_header)) { + ints += ARRAY_SIZE(nand_pmecc_header); + size -= sizeof(nand_pmecc_header); + } + + /* check the seven interrupt vectors of binary */ + for (pos = 0; pos < 7; pos++) { + debug("atmelimage: interrupt vector #%d is 0x%08X\n", pos+1, + ints[pos]); + /* + * all vectors except the 6'th one must contain valid + * LDR or B Opcode + */ + if (pos == 5) + /* 6'th vector has image size set, check later */ + continue; + if ((ints[pos] & 0xff000000) == 0xea000000) + /* valid B Opcode */ + continue; + if ((ints[pos] & 0xfffff000) == 0xe59ff000) + /* valid LDR (I=0, P=1, U=1, B=0, W=0, L=1) */ + continue; + /* ouch, one of the checks has missed ... */ + return 1; + } + + return ints[5] != cpu_to_le32(size); +} + +static void atmel_print_pmecc_header(const uint32_t word) +{ + int val; + + printf("\t\tPMECC header\n"); + + printf("\t\t====================\n"); + + val = (word >> 18) & 0x1ff; + printf("\t\teccOffset: %9i\n", val); + + val = (((word >> 16) & 0x3) == 0) ? 512 : 1024; + printf("\t\tsectorSize: %8i\n", val); + + if (((word >> 13) & 0x7) <= 2) + val = (2 << ((word >> 13) & 0x7)); + else + val = (12 << (((word >> 13) & 0x7) - 3)); + printf("\t\teccBitReq: %9i\n", val); + + val = (word >> 4) & 0x1ff; + printf("\t\tspareSize: %9i\n", val); + + val = (1 << ((word >> 1) & 0x3)); + printf("\t\tnbSectorPerPage: %3i\n", val); + + printf("\t\tusePmecc: %10i\n", word & 0x1); + printf("\t\t====================\n"); +} + +static void atmel_print_header(const void *ptr) +{ + uint32_t *ints = (uint32_t *)ptr; + size_t pos; + + /* check if we have an PMECC header attached */ + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + if (ints[pos] >> 28 != 0xC) + break; + + if (pos == ARRAY_SIZE(nand_pmecc_header)) { + printf("Image Type:\tATMEL ROM-Boot Image with PMECC Header\n"); + atmel_print_pmecc_header(ints[0]); + pos += 5; + } else { + printf("Image Type:\tATMEL ROM-Boot Image without PMECC Header\n"); + pos = 5; + } + printf("\t\t6'th vector has %u set\n", le32_to_cpu(ints[pos])); +} + +static void atmel_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + /* just save the image size into 6'th interrupt vector */ + uint32_t *ints = (uint32_t *)ptr; + size_t cnt; + size_t pos = 5; + size_t size = sbuf->st_size; + + for (cnt = 0; cnt < ARRAY_SIZE(nand_pmecc_header); cnt++) + if (ints[cnt] >> 28 != 0xC) + break; + + if (cnt == ARRAY_SIZE(nand_pmecc_header)) { + pos += ARRAY_SIZE(nand_pmecc_header); + size -= sizeof(nand_pmecc_header); + } + + ints[pos] = cpu_to_le32(size); +} + +static int atmel_check_params(struct image_tool_params *params) +{ + if (strlen(params->imagename) > 0) + if (atmel_parse_pmecc_params(params->imagename)) + return EXIT_FAILURE; + + return !(!params->eflag && + !params->fflag && + !params->xflag && + ((params->dflag && !params->lflag) || + (params->lflag && !params->dflag))); +} + +static int atmel_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + uint32_t tmp; + size_t pos; + + if (strlen(params->imagename) == 0) + return EXIT_SUCCESS; + + tmp = 0xC << 28; + + tmp |= (pmecc.ecc_offset & 0x1ff) << 18; + + switch (pmecc.sector_size) { + case 512: + tmp |= 0 << 16; + break; + case 1024: + tmp |= 1 << 16; + break; + + default: + pr_err("Wrong sectorSize (%i) for PMECC header\n", + pmecc.sector_size); + return EXIT_FAILURE; + } + + switch (pmecc.ecc_bits) { + case 2: + tmp |= 0 << 13; + break; + case 4: + tmp |= 1 << 13; + break; + case 8: + tmp |= 2 << 13; + break; + case 12: + tmp |= 3 << 13; + break; + case 24: + tmp |= 4 << 13; + break; + + default: + pr_err("Wrong eccBits (%i) for PMECC header\n", + pmecc.ecc_bits); + return EXIT_FAILURE; + } + + tmp |= (pmecc.spare_size & 0x1ff) << 4; + + switch (pmecc.sector_per_page) { + case 1: + tmp |= 0 << 1; + break; + case 2: + tmp |= 1 << 1; + break; + case 4: + tmp |= 2 << 1; + break; + case 8: + tmp |= 3 << 1; + break; + + default: + pr_err("Wrong sectorPerPage (%i) for PMECC header\n", + pmecc.sector_per_page); + return EXIT_FAILURE; + } + + if (pmecc.use_pmecc) + tmp |= 1; + + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + nand_pmecc_header[pos] = tmp; + + debug("PMECC header filled 52 times with 0x%08X\n", tmp); + + tparams->header_size = sizeof(nand_pmecc_header); + tparams->hdr = nand_pmecc_header; + + return EXIT_SUCCESS; +} + +U_BOOT_IMAGE_TYPE( + atmelimage, + "ATMEL ROM-Boot Image support", + 0, + NULL, + atmel_check_params, + atmel_verify_header, + atmel_print_header, + atmel_set_header, + NULL, + atmel_check_image_type, + NULL, + atmel_vrec_header +); diff --git a/tools/bddb/README b/tools/bddb/README deleted file mode 100644 index 9bee59a0fe..0000000000 --- a/tools/bddb/README +++ /dev/null @@ -1,116 +0,0 @@ -Hymod Board Database - -(C) Copyright 2001 -Murray Jensen -CSIRO Manufacturing Science and Technology, Preston Lab - -25-Jun-01 - -This stuff is a set of PHP/MySQL scripts to implement a custom board -database. It will need *extensive* hacking to modify it to keep the -information about your custom boards that you want, however it is a good -starting point. - -How it is used: - - 1. a board has gone through all the hardware testing etc and is - ready to have the flash programmed for the first time - first you - go to a web page and fill in information about the board in a form - to register it in a database - - 2. the web stuff allocates a (unique) serial number and (optionally) - a (locally administered) ethernet address and stores the information - in a database using the serial number as the key (can do whole - batches of boards in one go and/or use a previously registered board - as defaults for the new board(s)) - - 3. it then creates a file in the tftp area of a server somewhere - containing the board information in a simple text format (one - per serial number) - - 4. all hymod boards have an i2c eeprom, and when U-Boot sees that - the eeprom is unitialised, it prompts for a serial number and - ethernet address (if not set), then transfers the file created - in step 3 from the server and initialises the eeprom from its - contents - -What this means is you can't boot the board until you have allocated a serial -number, but you don't have to type it all twice - you do it once on the web -and the board then finds the info it needs to initialise its eeprom. The -other side of the coin is the reading of the eeprom and how it gets passed -to Linux (or another O/S). - -To see how this is all done for the hymod boards look at the code in the -"board/hymod" directory and in the file "include/asm/hymod.h". Hymod boards -can have a mezzanine card which also have an eeprom that needs allocating, -the same process is used for these as well - just a different i2c address. - -Other forms provide the following functions: - - - browsing the board database - - editing board information (one at a time) - - maintaining/browsing a (simple) per board event log - -You will need: MySQL (I use version 3.23.7-alpha), PHP4 (with MySQL -support enabled) and a web server (I use Apache 1.3.x). - -I originally started by using phpMyBuilder (http://kyber.dk/phpMyBuilder) -but it soon got far more complicated than that could handle (but I left -the copyright messages in there anyway). Most of the code resides in the -common defs.php file, which shouldn't need much alteration - all the work -will be in shaping the front-end php files to your liking. - -Here's a quick summary of what needs doing to use it for your boards: - -1. get phpMyAdmin (http://phpwizard.net/projects/phpMyAdmin/) - it's an - invaluable tool for this sort of stuff (this step is optional of course) - -2. edit "bddb.css" to your taste, if you could be bothered - I have no - idea what is in there or what it does - I copied it from somewhere else - ("user.css" from the phpMyEdit (http://phpmyedit.sourcerforge.net) package, - I think) - I figure one day I'll see what sort of things I can change - in there. - -3. create a mysql database - call it whatever you like - -4. edit "create_tables.sql" and modify the "boards" table schema to - reflect the information you want to keep about your boards. It may or - may not be easier to do this and the next step in phpMyAdmin. Check out - the MySQL documentation at http://www.mysql.com/doc/ in particular the - column types at http://www.mysql.com/doc/C/o/Column_types.html - Note - there is only support for a few data types: - - int - presented as an html text input - char/text - presented as an html text input - date - presented as an html text input - enum - presented as an html radio input - - I also have what I call "enum_multi" which is a set of enums with the - same name, but suffixed with a number e.g. fred0, fred1, fred2. These - are presented as a number of html select's with a single label "fred" - this is useful for board characteristics that have multiple items of - the same type e.g. multiple banks of sdram. - -5. use the "create_tables.sql" file to create the "boards" table in the - database e.g. mysql dbname < create_tables.sql - -6. create a user and password for the web server to log into the MySQL - database with; give this user select, insert and update privileges - to the database created in 3 (and delete, if you want the "delete" - functions in the edit forms to work- I have this turned off). phpMyAdmin - helps in this step. - -7. edit "config.php" and set the variables: $mysql_user, $mysql_pw, $mysql_db, - $bddb_cfgdir and $bddb_label - keep the contents of this file secret - it - contains the web servers username and password (the three $mysql_* vars - are set from the previous step) - -8. edit "defs.php" and a. adjust the various enum value arrays and b. edit - the function "pg_foot()" to remove my email address :-) - -9. do major hacking on the following files: browse.php, doedit.php, donew.php, - edit.php and new.php to reflect your database schema - fortunately the - hacking is fairly straight-forward, but it is boring and time-consuming. - -These notes were written rather hastily - if you find any obvious problems -please let me know. diff --git a/tools/bddb/badsubmit.php b/tools/bddb/badsubmit.php deleted file mode 100644 index 5092a31969..0000000000 --- a/tools/bddb/badsubmit.php +++ /dev/null @@ -1,23 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - require("defs.php"); - pg_head("$bddb_label - Unknown Submit Type"); -?> -
- - - The form was submitted with an - unknown SUBMIT type . -

- Perhaps you typed the URL in directly? Click here to go to the - home page of the . - - -
- diff --git a/tools/bddb/bddb.css b/tools/bddb/bddb.css deleted file mode 100644 index dee2b2ee49..0000000000 --- a/tools/bddb/bddb.css +++ /dev/null @@ -1,207 +0,0 @@ -BODY { - background: #e0ffff; - color: #000000; - font-family: Arial, Verdana, Helvetica; -} -H1 { - font-family: "Copperplate Gothic Bold"; - background: transparent; - color: #993300; - text-align: center; -} -H2, H3, H4, H5 { - background: transparent; - color: #993300; - margin-top: 4%; - text-align: center; -} -Body.Plain Div.Abstract, Body.Plain P.Abstract { - background: #cccc99; - color: #333300; - border: white; - padding: 3%; - font-family: Times, Verdana; -} -TH.Nav { - background: #0000cc; - color: #ff9900; -} -TH.Menu { - background: #3366cc; - color: #ff9900; -} -A:hover { - color: #ff6600; -} -A.Menu:hover { - color: #ff6600; -} -A.HoMe:hover { - color: #ff6600; -} -A.Menu { - background: transparent; - color: #ffcc33; - font-family: Verdana, Helvetica, Arial; - font-size: smaller; - text-decoration: none; -} -A.Menu:visited { - background: transparent; - color: #ffcc99; -} -A.HoMe { - background: transparent; - color: #ffcc33; - font-family: Verdana, Helvetica, Arial; - text-decoration:none; -} -A.HoMe:visited { - background: transparent; - color: #ffcc99; -} -TH.Xmp { - background: #eeeeee; - color: #330066; - font-family: courier; - font-weight: normal; -} -TH.LuT { - background: #cccccc; - color: #000000; -} -TD.LuT { - background: #ffffcc; - color: #000000; - font-size: 85%; -} -TH.Info, TD.Info { - background: #ffffcc; - color: #660000; - font-family: "Comic Sans MS", Cursive, Verdana; - font-size: smaller; -} -Div.Info, P.Info { - background: #ffff99; - color: #990033; - text-align: left; - padding: 2%; - font-family: "Comic Sans MS", Cursive, Verdana; - font-size: 85%; - } -Div.Info A { - background: transparent; - color: #ff6600; -} -.HL { - background: #ffff99; - color: #000000; -} -TD.HL { - background: #ccffff; - color: #000000; -} -Div.Margins { - width: 512px; - text-align: center; -} -TD.Plain { - background: #ffffcc; - color: #000033; -} -.Type { - background: #cccccc; - color: #660000; -} -.Name { - background: #eeeeee; - color: #660000; - vertical-align: top; - text-align: right; -} -.Value { - background: #ffffee; - color: #000066; -} -.Drop { - background: #333366; - color: #ffcc33; - font-family: "Copperplate Gothic Light", Helvetica, Verdana, Arial; -} -A.Button:hover { - color: #ff6600; -} -A.Button { - text-decoration:none; - color: #003366; - background: #ffcc66; -} -.Button { - font-size: 9pt; - text-align: center; - text-decoration:none; - color: #003366; - background: #ffcc66; - margin-bottom: 2pt; - border-top: 2px solid #ffff99; - border-left: 2px solid #ffff99; - border-right: 2px solid #cc9933; - border-bottom: 2px solid #cc9933; - font-family: Verdana, Arial, "Comic Sans MS"; -} -.Banner { - width: 468; - font-size: 12pt; - text-align: center; - text-decoration:none; - color: #003366; - background: #ffcc66; - border-top: 4px solid #ffff99; - border-left: 4px solid #ffff99; - border-right: 4px solid #cc9933; - border-bottom: 4px solid #cc9933; - font-family: Verdana, Arial, "Comic Sans MS"; -} -TD.Nova, Body.Nova { - background: #000000; - font-family: "Times New Roman"; - font-weight: light; - color: #ffcc00; -} -Body.Nova A.Button { - background: gold; - color: #003366; -} -Body.Nova A.Banner { - background: transparent; - color: #003366; -} -Body.Nova A { - background: transparent; - text-decoration:none; - color: #ffd766; -} -Body.Nova H1, Body.Nova H2, Body.Nova H3, Body.Nova H4 { - background: transparent; - color: white; - margin-top: 4%; - text-align: center; - filter: Blur(Add=1, Direction=0, Strength=8); -} -Body.Nova Div.Abstract { - background: #000000; - color: #ffffff; - font-family: Times, Verdana; -} -Body.Nova A.Abstract { - background: transparent; - color: #ffeedd; -} -Body.Nova TH.LuT { - background: black; - color: #ffff99; -} -Body.Nova TD.LuT { - background: navy; - color: #ffff99; -} diff --git a/tools/bddb/brlog.php b/tools/bddb/brlog.php deleted file mode 100644 index fccfbd011c..0000000000 --- a/tools/bddb/brlog.php +++ /dev/null @@ -1,109 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // list page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Browse Board Log"); - - $serno=intval($serno); - if ($serno == 0) - die("serial number not specified or invalid!"); - - function print_cell($str) { - if ($str == '') - $str = ' '; - echo "\t$str\n"; - } -?> - - - - - - - - - - -\n"; - print_cell("$row[serno]"); - print_cell($row['ethaddr']); - print_cell($row['date']); - print_cell($row['batch']); - print_cell($row['type']); - print_cell($row['rev']); - print_cell($row['location']); - echo "\n"; - } - - mysql_free_result($r); -?> -
serno / editethaddrdatebatchtyperevlocation
-
-

-$limit){ - $preoffset=max(0,$offset-$limit); - $postoffset=$offset+$limit; - echo "\n\n"; - printf("\n", $offset>0?"":"no", $PHP_SELF, $preoffset); - printf("\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset); - echo "\n
<%sa href=\"%s?submit=Log&serno=$serno&offset=%d\">\"<\"<%sa href=\"%s?submit=Log&serno=$serno&offset=%d\">\">\"
\n"; - } - mysql_free_result($lr); -?> - - - - - - - -\n"; - print_cell("$row[logno]"); - print_cell($row['date']); - print_cell($row['who']); - print_cell("
" . urldecode($row['details']) . "
"); - echo "\n"; - } - - mysql_free_result($r); -?> -
logno / editdatewhodetails
-
-

- - - - - -
- ">Add to Log - - Back to Start -
- diff --git a/tools/bddb/browse.php b/tools/bddb/browse.php deleted file mode 100644 index 675dfab749..0000000000 --- a/tools/bddb/browse.php +++ /dev/null @@ -1,147 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // list page (hymod_bddb / boards) - - require("defs.php"); - - $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:''; - - $verbose=isset($_REQUEST['verbose'])?intval($_REQUEST['verbose']):0; - - pg_head("$bddb_label - Browse database" . ($verbose?" (verbose)":"")); -?> -

-$limit){ - $preoffset=max(0,$offset-$limit); - $postoffset=$offset+$limit; - echo "\n\n"; - printf("\n", $offset>0?"":"no", $PHP_SELF, $preoffset, $verbose); - printf("\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset, $offset); - echo "\n
<%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\">\"<\"<%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\">\">\"
\n"; - } - - mysql_free_result($lr); - } -?> - - - - - - - - - - -comments\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - echo "\n"; - } -?> - -=$m[1] and serno<=$m[2])"; - } - else - die("illegal serial number ($s)"); - $pre = " or "; - } - } - $query .= " order by serno"; - if ($serno == '') - $query .= " limit $offset,$limit"; - - $r = mysql_query($query); - - function print_cell($str) { - if ($str == '') - $str = ' '; - echo "\t\n"; - } - - while($row=mysql_fetch_array($r)){ - foreach ($columns as $key) { - if (!key_in_array($key, $row)) - $row[$key] = ''; - } - - echo "\n"; - print_cell("Log"); - print_cell("$row[serno]"); - print_cell($row['ethaddr']); - print_cell($row['date']); - print_cell($row['batch']); - print_cell($row['type']); - print_cell($row['rev']); - print_cell($row['location']); - if ($verbose) { - print_cell("
\n" . urldecode($row['comments']) .
-				"\n\t
"); - print_cell(gather_enum_multi_print("sdram", 4, $row)); - print_cell(gather_enum_multi_print("flash", 4, $row)); - print_cell(gather_enum_multi_print("zbt", 16, $row)); - print_cell(gather_enum_multi_print("xlxtyp", 4, $row)); - print_cell(gather_enum_multi_print("xlxspd", 4, $row)); - print_cell(gather_enum_multi_print("xlxtmp", 4, $row)); - print_cell(gather_enum_multi_print("xlxgrd", 4, $row)); - print_cell($row['cputyp']); - print_cell($row['cpuspd']); - print_cell($row['cpmspd']); - print_cell($row['busspd']); - print_cell($row['hstype']); - print_cell($row['hschin']); - print_cell($row['hschout']); - } - echo "\n"; - } -?> -
serno / editethaddrdatebatchtyperevlocationsdramflashzbtxlxtypxlxspdxlxtmpxlxgrdcputypcpuspdcpmspdbusspdhstypehschinhschout
$str
-

- - - - - -
%s Listing\n", $PHP_SELF, $offset, $verbose?0:1, $serno!=''?"&serno=$serno":'', $verbose?"Terse":"Verbose"); - ?>Back to Start
- diff --git a/tools/bddb/config.php b/tools/bddb/config.php deleted file mode 100644 index 67257578f0..0000000000 --- a/tools/bddb/config.php +++ /dev/null @@ -1,16 +0,0 @@ - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // mysql database access info - $mysql_user="fred"; - $mysql_pw="apassword"; - $mysql_db="mydbname"; - - // where to put the eeprom config files - $bddb_cfgdir = '/tftpboot/bddb'; - - // what this database is called - $bddb_label = 'Hymod Board Database'; -?> diff --git a/tools/bddb/create_tables.sql b/tools/bddb/create_tables.sql deleted file mode 100644 index a2a578867f..0000000000 --- a/tools/bddb/create_tables.sql +++ /dev/null @@ -1,90 +0,0 @@ -# phpMyAdmin MySQL-Dump -# http://phpwizard.net/phpMyAdmin/ -# -# Host: localhost Database : hymod_bddb - -# (C) Copyright 2001 -# Murray Jensen -# CSIRO Manufacturing and Infrastructure Technology, Preston Lab - -# -------------------------------------------------------- -# -# Table structure for table 'boards' -# - -DROP TABLE IF EXISTS boards; -CREATE TABLE boards ( - serno int(10) unsigned zerofill NOT NULL auto_increment, - ethaddr char(17), - date date NOT NULL, - batch char(32), - type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') NOT NULL, - rev tinyint(3) unsigned zerofill NOT NULL, - location char(64), - comments text, - sdram0 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram1 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram2 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram3 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - flash0 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash1 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash2 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash3 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - zbt0 enum('512K','1M','2M','4M','8M','16M'), - zbt1 enum('512K','1M','2M','4M','8M','16M'), - zbt2 enum('512K','1M','2M','4M','8M','16M'), - zbt3 enum('512K','1M','2M','4M','8M','16M'), - zbt4 enum('512K','1M','2M','4M','8M','16M'), - zbt5 enum('512K','1M','2M','4M','8M','16M'), - zbt6 enum('512K','1M','2M','4M','8M','16M'), - zbt7 enum('512K','1M','2M','4M','8M','16M'), - zbt8 enum('512K','1M','2M','4M','8M','16M'), - zbt9 enum('512K','1M','2M','4M','8M','16M'), - zbta enum('512K','1M','2M','4M','8M','16M'), - zbtb enum('512K','1M','2M','4M','8M','16M'), - zbtc enum('512K','1M','2M','4M','8M','16M'), - zbtd enum('512K','1M','2M','4M','8M','16M'), - zbte enum('512K','1M','2M','4M','8M','16M'), - zbtf enum('512K','1M','2M','4M','8M','16M'), - xlxtyp0 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp1 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp2 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp3 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxspd0 enum('6','7','8','4','5','9','10','11','12'), - xlxspd1 enum('6','7','8','4','5','9','10','11','12'), - xlxspd2 enum('6','7','8','4','5','9','10','11','12'), - xlxspd3 enum('6','7','8','4','5','9','10','11','12'), - xlxtmp0 enum('COM','IND'), - xlxtmp1 enum('COM','IND'), - xlxtmp2 enum('COM','IND'), - xlxtmp3 enum('COM','IND'), - xlxgrd0 enum('NORMAL','ENGSAMP'), - xlxgrd1 enum('NORMAL','ENGSAMP'), - xlxgrd2 enum('NORMAL','ENGSAMP'), - xlxgrd3 enum('NORMAL','ENGSAMP'), - cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'), - cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - hstype enum('AMCC-S2064A','Xilinx-Rockets'), - hschin enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'), - hschout enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'), - PRIMARY KEY (serno), - KEY serno (serno), - UNIQUE serno_2 (serno) -); - -# -# Table structure for table 'log' -# - -DROP TABLE IF EXISTS log; -CREATE TABLE log ( - logno int(10) unsigned zerofill NOT NULL auto_increment, - serno int(10) unsigned zerofill NOT NULL, - date date NOT NULL, - details text NOT NULL, - PRIMARY KEY (logno), - KEY logno (logno, serno, date), - UNIQUE logno_2 (logno) -); diff --git a/tools/bddb/defs.php b/tools/bddb/defs.php deleted file mode 100644 index b7518e3f79..0000000000 --- a/tools/bddb/defs.php +++ /dev/null @@ -1,710 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // contains mysql user id and password - keep secret - require("config.php"); - - if (isset($_REQUEST['logout'])) { - Header("status: 401 Unauthorized"); - Header("HTTP/1.0 401 Unauthorized"); - Header("WWW-authenticate: basic realm=\"$bddb_label\""); - - echo "" . - "Access to '$bddb_label' Denied" . - "\n"; - echo "



" . - "You must be an Authorised User " . - "to access the '$bddb_label'" . - "

\n
\n"; - exit; - } - - // contents of the various enumerated types - if first item is - // empty ('') then the enum is allowed to be null (ie "not null" - // is not set on the column) - - // all column names in the database table - $columns = array( - 'serno','ethaddr','date','batch', - 'type','rev','location','comments', - 'sdram0','sdram1','sdram2','sdram3', - 'flash0','flash1','flash2','flash3', - 'zbt0','zbt1','zbt2','zbt3','zbt4','zbt5','zbt6','zbt7', - 'zbt8','zbt9','zbta','zbtb','zbtc','zbtd','zbte','zbtf', - 'xlxtyp0','xlxtyp1','xlxtyp2','xlxtyp3', - 'xlxspd0','xlxspd1','xlxspd2','xlxspd3', - 'xlxtmp0','xlxtmp1','xlxtmp2','xlxtmp3', - 'xlxgrd0','xlxgrd1','xlxgrd2','xlxgrd3', - 'cputyp','cpuspd','cpmspd','busspd', - 'hstype','hschin','hschout' - ); - - // board type - $type_vals = array('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY'); - - // Xilinx fpga types - $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'); - - // Xilinx fpga speeds - $xlxspd_vals = array('','6','7','8','4','5','9','10','11','12'); - - // Xilinx fpga temperatures (commercial or industrial) - $xlxtmp_vals = array('','COM','IND'); - - // Xilinx fpga grades (normal or engineering sample) - $xlxgrd_vals = array('','NORMAL','ENGSAMP'); - - // CPU types - $cputyp_vals = array('','MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'); - - // CPU/BUS/CPM clock speeds - $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'); - - // sdram sizes (nbits array is for eeprom config file) - $sdram_vals = array('','32M','64M','128M','256M','512M','1G','2G','4G'); - $sdram_nbits = array(0,25,26,27,28,29,30,31,32); - - // flash sizes (nbits array is for eeprom config file) - $flash_vals = array('','4M','8M','16M','32M','64M','128M','256M','512M','1G'); - $flash_nbits = array(0,22,23,24,25,26,27,28,29,30); - - // zbt ram sizes (nbits array is for write into eeprom config file) - $zbt_vals = array('','512K','1M','2M','4M','8M','16M'); - $zbt_nbits = array(0,19,20,21,22,23,24); - - // high-speed serial attributes - $hstype_vals = array('','AMCC-S2064A','Xilinx-Rockets'); - $hschin_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'); - $hschout_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'); - - // value filters - used when outputting html - function rev_filter($num) { - if ($num == 0) - return "001"; - else - return sprintf("%03d", $num); - } - - function text_filter($str) { - return urldecode($str); - } - - mt_srand(time() | getmypid()); - - // set up MySQL connection - mysql_connect("", $mysql_user, $mysql_pw) || die("cannot connect"); - mysql_select_db($mysql_db) || die("cannot select db"); - - // page header - function pg_head($title) - { - echo "\n\n"; - echo "\n"; - echo "$title\n"; - echo "\n"; - echo "\n"; - echo "

$title

\n"; - echo "
\n"; - } - - // page footer - function pg_foot() - { - echo "
\n"; - echo "
\n
" . - "If you have any problems, email " . - "" . - "Murray Jensen" . - "
\n" . - "		\n" . - "logout\n" . - "
\n"; - echo "

Made with " . - "" . - "Kyber phpMyBuilder

\n"; - echo "\n"; - echo "\n"; - } - - // some support functions - - if (!function_exists('array_search')) { - - function array_search($needle, $haystack, $strict = false) { - - if (is_array($haystack) && count($haystack)) { - - $ntype = gettype($needle); - - foreach ($haystack as $key => $value) { - - if ($value == $needle && (!$strict || - gettype($value) == $ntype)) - return $key; - } - } - - return false; - } - } - - if (!function_exists('in_array')) { - - function in_array($needle, $haystack, $strict = false) { - - if (is_array($haystack) && count($haystack)) { - - $ntype = gettype($needle); - - foreach ($haystack as $key => $value) { - - if ($value == $needle && (!$strict || - gettype($value) == $ntype)) - return true; - } - } - - return false; - } - } - - function key_in_array($key, $array) { - return in_array($key, array_keys($array), true); - } - - function enum_to_index($name, $vals) { - $index = array_search($GLOBALS[$name], $vals); - if ($vals[0] != '') - $index++; - return $index; - } - - // fetch a value from an array - return empty string is not present - function get_key_value($key, $array) { - if (key_in_array($key, $array)) - return $array[$key]; - else - return ''; - } - - function fprintf() { - $n = func_num_args(); - if ($n < 2) - return FALSE; - $a = func_get_args(); - $fp = array_shift($a); - $x = "\$s = sprintf"; - $sep = '('; - foreach ($a as $z) { - $x .= "$sep'$z'"; - $sep = ','; - } - $x .= ');'; - eval($x); - $l = strlen($s); - $r = fwrite($fp, $s, $l); - if ($r != $l) - return FALSE; - else - return TRUE; - } - - // functions to display (print) a database table and its columns - - function begin_table($ncols) { - global $table_ncols; - $table_ncols = $ncols; - echo "\n"; - } - - function begin_field($name, $span = 0) { - global $table_ncols; - echo "\n"; - echo "\t\n"; - if ($span <= 0) - $span = $table_ncols - 1; - if ($span > 1) - echo "\t\n"; - if ($span > 1) - echo "\t\n"; - echo "\n"; - } - - function end_table() { - echo "
$name\n"; - else - echo "\t\n"; - } - - function cont_field($span = 1) { - echo "\t\n"; - else - echo "\t\n"; - } - - function end_field() { - echo "\t
\n"; - } - - function print_field($name, $array, $size = 0, $filt='') { - - begin_field($name); - - if (key_in_array($name, $array)) - $value = $array[$name]; - else - $value = ''; - - if ($filt != '') - $value = $filt($value); - - echo "\t\t 0) - echo " size=$size maxlength=$size"; - echo ">\n"; - - end_field(); - } - - function print_field_multiline($name, $array, $cols, $rows, $filt='') { - - begin_field($name); - - if (key_in_array($name, $array)) - $value = $array[$name]; - else - $value = ''; - - if ($filt != '') - $value = $filt($value); - - echo "\t\t\n"; - - end_field(); - } - - // print a mysql ENUM as an html RADIO INPUT - function print_enum($name, $array, $vals, $def = -1) { - - begin_field($name); - - if (key_in_array($name, $array)) - $chk = array_search($array[$name], $vals, FALSE); - else - $chk = $def; - - $nval = count($vals); - - for ($i = 0; $i < $nval; $i++) { - - $val = $vals[$i]; - if ($val == '') - $pval = "none"; - else - $pval = "$val"; - - printf("\t\t$pval\n", - $i == $chk ? " checked" : ""); - } - - end_field(); - } - - // print a mysql ENUM as an html SELECT INPUT - function print_enum_select($name, $array, $vals, $def = -1) { - - begin_field($name); - - echo "\t\t\n"; - - end_field(); - } - - // print a group of mysql ENUMs (e.g. name0,name1,...) as an html SELECT - function print_enum_multi($base, $array, $vals, $cnt, $defs, $grp = 0) { - - global $table_ncols; - - if ($grp <= 0) - $grp = $cnt; - $ncell = $cnt / $grp; - $span = ($table_ncols - 1) / $ncell; - - begin_field($base, $span); - - $nval = count($vals); - - for ($i = 0; $i < $cnt; $i++) { - - if ($i > 0 && ($i % $grp) == 0) - cont_field($span); - - $name = sprintf("%s%x", $base, $i); - - echo "\t\t\n"; - } - - end_field(); - } - - // functions to handle the form input - - // fetch all the parts of an "enum_multi" into a string suitable - // for a MySQL query - function gather_enum_multi_query($base, $cnt) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if (isset($_REQUEST[$name])) { - $retval .= sprintf(", %s='%s'", - $name, $_REQUEST[$name]); - } - } - - return $retval; - } - - // fetch all the parts of an "enum_multi" into a string suitable - // for a display e.g. in an html table cell - function gather_enum_multi_print($base, $cnt, $array) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if ($array[$name] != '') { - if ($retval != '') - $retval .= ','; - $retval .= $array[$name]; - } - } - - return $retval; - } - - // fetch all the parts of an "enum_multi" into a string suitable - // for writing to the eeprom data file - function gather_enum_multi_write($base, $cnt, $vals, $xfrm = array()) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if ($GLOBALS[$name] != '') { - if ($retval != '') - $retval .= ','; - $index = enum_to_index($name, $vals); - if ($xfrm != array()) - $retval .= $xfrm[$index]; - else - $retval .= $index; - } - } - - return $retval; - } - - // count how many parts of an "enum_multi" are actually set - function count_enum_multi($base, $cnt) { - - $retval = 0; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if (isset($_REQUEST[$name])) - $retval++; - } - - return $retval; - } - - // ethernet address functions - - // generate a (possibly not unique) random vendor ethernet address - // (setting bit 6 in the ethernet address - motorola wise i.e. bit 0 - // is the most significant bit - means it is not an assigned ethernet - // address - it is a "locally administered" address). Also, make sure - // it is NOT a multicast ethernet address (by setting bit 7 to 0). - // e.g. the first byte of all ethernet addresses generated here will - // have 2 in the bottom two bits (incidentally, these are the first - // two bits transmitted on the wire, since the octets in ethernet - // addresses are transmitted LSB first). - - function gen_eth_addr($serno) { - - $ethaddr_hgh = (mt_rand(0, 65535) & 0xfeff) | 0x0200; - $ethaddr_mid = mt_rand(0, 65535); - $ethaddr_low = mt_rand(0, 65535); - - return sprintf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx", - $ethaddr_hgh >> 8, $ethaddr_hgh & 0xff, - $ethaddr_mid >> 8, $ethaddr_mid & 0xff, - $ethaddr_low >> 8, $ethaddr_low & 0xff); - } - - // check that an ethernet address is valid - function eth_addr_is_valid($ethaddr) { - - $ethbytes = split(':', $ethaddr); - - if (count($ethbytes) != 6) - return FALSE; - - for ($i = 0; $i < 6; $i++) { - $ethbyte = $ethbytes[$i]; - if (!ereg('^[0-9a-f][0-9a-f]$', $ethbyte)) - return FALSE; - } - - return TRUE; - } - - // write a simple eeprom configuration file - function write_eeprom_cfg_file() { - - global $sernos, $nsernos, $bddb_cfgdir, $numerrs, $cfgerrs; - global $date, $batch, $type_vals, $rev; - global $sdram_vals, $sdram_nbits; - global $flash_vals, $flash_nbits; - global $zbt_vals, $zbt_nbits; - global $xlxtyp_vals, $xlxspd_vals, $xlxtmp_vals, $xlxgrd_vals; - global $cputyp, $cputyp_vals, $clk_vals; - global $hstype, $hstype_vals, $hschin, $hschout; - - $numerrs = 0; - $cfgerrs = array(); - - for ($i = 0; $i < $nsernos; $i++) { - - $serno = sprintf("%010d", $sernos[$i]); - - $wfp = @fopen($bddb_cfgdir . "/$serno.cfg", "w"); - if (!$wfp) { - $cfgerrs[$i] = 'file create fail'; - $numerrs++; - continue; - } - set_file_buffer($wfp, 0); - - if (!fprintf($wfp, "serno=%d\n", $sernos[$i])) { - $cfgerrs[$i] = 'cfg wr fail (serno)'; - fclose($wfp); - $numerrs++; - continue; - } - - if (!fprintf($wfp, "date=%s\n", $date)) { - $cfgerrs[$i] = 'cfg wr fail (date)'; - fclose($wfp); - $numerrs++; - continue; - } - - if ($batch != '') { - if (!fprintf($wfp, "batch=%s\n", $batch)) { - $cfgerrs[$i] = 'cfg wr fail (batch)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $typei = enum_to_index("type", $type_vals); - if (!fprintf($wfp, "type=%d\n", $typei)) { - $cfgerrs[$i] = 'cfg wr fail (type)'; - fclose($wfp); - $numerrs++; - continue; - } - - if (!fprintf($wfp, "rev=%d\n", $rev)) { - $cfgerrs[$i] = 'cfg wr fail (rev)'; - fclose($wfp); - $numerrs++; - continue; - } - - $s = gather_enum_multi_write("sdram", 4, - $sdram_vals, $sdram_nbits); - if ($s != '') { - $b = fprintf($wfp, "sdram=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (sdram)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("flash", 4, - $flash_vals, $flash_nbits); - if ($s != '') { - $b = fprintf($wfp, "flash=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (flash)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("zbt", 16, - $zbt_vals, $zbt_nbits); - if ($s != '') { - $b = fprintf($wfp, "zbt=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (zbt)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxtyp", 4, $xlxtyp_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxtyp=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxtyp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxspd", 4, $xlxspd_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxspd=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxspd)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxtmp", 4, $xlxtmp_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxtmp=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxtmp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxgrd", 4, $xlxgrd_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxgrd=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxgrd)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if ($cputyp != '') { - $cputypi = enum_to_index("cputyp",$cputyp_vals); - $cpuspdi = enum_to_index("cpuspd", $clk_vals); - $busspdi = enum_to_index("busspd", $clk_vals); - $cpmspdi = enum_to_index("cpmspd", $clk_vals); - $b = fprintf($wfp, "cputyp=%d\ncpuspd=%d\n" . - "busspd=%d\ncpmspd=%d\n", - $cputypi, $cpuspdi, $busspdi, $cpmspdi); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (cputyp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if ($hstype != '') { - $hstypei = enum_to_index("hstype",$hstype_vals); - $b = fprintf($wfp, "hstype=%d\n" . - "hschin=%s\nhschout=%s\n", - $hstypei, $hschin, $hschout); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (hstype)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if (!fclose($wfp)) { - $cfgerrs[$i] = 'file cls fail'; - $numerrs++; - } - } - - return $numerrs; - } -?> diff --git a/tools/bddb/dodelete.php b/tools/bddb/dodelete.php deleted file mode 100644 index 4839e36e60..0000000000 --- a/tools/bddb/dodelete.php +++ /dev/null @@ -1,65 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // dodelete page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Delete Board Results"); - - if (!isset($_REQUEST['serno'])) - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - mysql_query("delete from boards where serno=$serno"); - - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t

\n"; - echo "\t\t
\n"; - printf("\t\t\t%s\n", $errstr); - echo "\t\t
\n"; - echo "\t\n"; - } - else { - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe board with serial number $serno was" - . " successfully deleted\n"; - mysql_query("delete from log where serno=$serno"); - if (mysql_errno()) { - $errstr = mysql_error(); - echo "\t\t\t\n"; - echo "\t\t\t\t

\n"; - echo "\t\t\t\t\tBut the following error occurred " . - "when deleting the log entries:\n"; - echo "\t\t\t\t

\n"; - echo "\t\t\t\t
\n"; - printf("\t\t\t\t\t%s\n", $errstr); - echo "\t\t\t\t
\n"; - echo "\t\t\t\n"; - } - echo "\t\t

\n"; - echo "\t\n"; - } -?> -

- - - - - -
- Back to Browse - - Back to Start -
- diff --git a/tools/bddb/dodellog.php b/tools/bddb/dodellog.php deleted file mode 100644 index 9dd78c11b6..0000000000 --- a/tools/bddb/dodellog.php +++ /dev/null @@ -1,57 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // dodelete page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Delete Log Entry Results"); - - if (!isset($_REQUEST['serno'])) - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == 0) - die("the log entry number not specified!"); - $logno=$_REQUEST['logno']; - - mysql_query("delete from log where serno=$serno and logno=$logno"); - - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t

\n"; - echo "\t\t
\n"; - printf("\t\t\t%s\n", $errstr); - echo "\t\t
\n"; - echo "\t\n"; - } - else { - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe log entry with log number $logno\n"; - echo "\t\t\tand serial number $serno "; - echo "was successfully deleted\n"; - echo "\t\t

\n"; - echo "\t\n"; - } -?> -

- - - - - -
- ">Back to Log - - Back to Start -
- diff --git a/tools/bddb/doedit.php b/tools/bddb/doedit.php deleted file mode 100644 index 13fbb69479..0000000000 --- a/tools/bddb/doedit.php +++ /dev/null @@ -1,186 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - $query="update boards set"; - - if (isset($_REQUEST['ethaddr'])) { - $ethaddr=$_REQUEST['ethaddr']; - if (!eth_addr_is_valid($ethaddr)) - die("ethaddr is invalid ('$ethaddr')"); - $query.=" ethaddr='$ethaddr',"; - } - - if (isset($_REQUEST['date'])) { - $date=$_REQUEST['date']; - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', " . - "yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - } - - if (isset($_REQUEST['batch'])) { - $batch=$_REQUEST['batch']; - if (strlen($batch) > 32) - die("batch field too long (>32)"); - $query.=", batch='$batch'"; - } - - if (isset($_REQUEST['type'])) { - $type=$_REQUEST['type']; - if (!in_array($type, $type_vals)) - die("Invalid type ($type) specified"); - $query.=", type='$type'"; - } - - if (isset($_REQUEST['rev'])) { - $rev=$_REQUEST['rev']; - if (($rev = intval($rev)) <= 0 || $rev > 255) - die("Revision number is invalid ($rev)"); - $query.=sprintf(", rev=%d", $rev); - } - - if (isset($_REQUEST['location'])) { - $location=$_REQUEST['location']; - if (strlen($location) > 64) - die("location field too long (>64)"); - $query.=", location='$location'"; - } - - if (isset($_REQUEST['comments'])) - $comments=$_REQUEST['comments']; - $query.=", comments='" . rawurlencode($comments) . "'"; - - $query.=gather_enum_multi_query("sdram", 4); - - $query.=gather_enum_multi_query("flash", 4); - - $query.=gather_enum_multi_query("zbt", 16); - - $query.=gather_enum_multi_query("xlxtyp", 4); - $nxlx = count_enum_multi("xlxtyp", 4); - - $query.=gather_enum_multi_query("xlxspd", 4); - if (count_enum_multi("xlxspd", 4) != $nxlx) - die("number of xilinx speeds not same as number of types"); - - $query.=gather_enum_multi_query("xlxtmp", 4); - if (count_enum_multi("xlxtmp", 4) != $nxlx) - die("number of xilinx temps. not same as number of types"); - - $query.=gather_enum_multi_query("xlxgrd", 4); - if (count_enum_multi("xlxgrd", 4) != $nxlx) - die("number of xilinx grades not same as number of types"); - - if (isset($_REQUEST['cputyp'])) { - $cputyp=$_REQUEST['cputyp']; - $query.=", cputyp='$cputyp'"; - if (!isset($_REQUEST['cpuspd']) || $_REQUEST['cpuspd'] == '') - die("must specify cpu speed if cpu type is defined"); - $cpuspd=$_REQUEST['cpuspd']; - $query.=", cpuspd='$cpuspd'"; - if (!isset($_REQUEST['cpmspd']) || $_REQUEST['cpmspd'] == '') - die("must specify cpm speed if cpu type is defined"); - $cpmspd=$_REQUEST['cpmspd']; - $query.=", cpmspd='$cpmspd'"; - if (!isset($_REQUEST['busspd']) || $_REQUEST['busspd'] == '') - die("must specify bus speed if cpu type is defined"); - $busspd=$_REQUEST['busspd']; - $query.=", busspd='$busspd'"; - } - else { - if (isset($_REQUEST['cpuspd'])) - die("can't specify cpu speed if there is no cpu"); - if (isset($_REQUEST['cpmspd'])) - die("can't specify cpm speed if there is no cpu"); - if (isset($_REQUEST['busspd'])) - die("can't specify bus speed if there is no cpu"); - } - - if (isset($_REQUEST['hschin'])) { - $hschin=$_REQUEST['hschin']; - if (($hschin = intval($hschin)) < 0 || $hschin > 4) - die("Invalid number of hs input chans ($hschin)"); - } - else - $hschin = 0; - if (isset($_REQUEST['hschout'])) { - $hschout=$_REQUEST['hschout']; - if (($hschout = intval($hschout)) < 0 || $hschout > 4) - die("Invalid number of hs output chans ($hschout)"); - } - else - $hschout = 0; - if (isset($_REQUEST['hstype'])) { - $hstype=$_REQUEST['hstype']; - $query.=", hstype='$hstype'"; - } - else { - if ($_REQUEST['hschin'] != 0) - die("number of high-speed input channels must be zero" - . " if high-speed chip is not present"); - if ($_REQUEST['hschout'] != 0) - die("number of high-speed output channels must be zero" - . " if high-speed chip is not present"); - } - $query.=", hschin='$hschin'"; - $query.=", hschout='$hschout'"; - - $query.=" where serno=$serno"; - - mysql_query($query); - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t

\n"; - echo "\t\t
\n"; - printf("\t\t\t%s\n", $errstr); - echo "\t\t
\n"; - echo "\t\n"; - } - else { - $sernos = array($serno); - $nsernos = 1; - - write_eeprom_cfg_file(); - - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe board with serial number $serno was" - . " successfully updated"; - if ($numerrs > 0) { - $errstr = $cfgerrs[0]; - echo "
\n\t\t\t"; - echo "(but the cfg file update failed: $errstr)"; - } - echo "\n"; - echo "\t\t

\n"; - echo "\t\n"; - } - -?> -

- - - - - -
Back to BrowseBack to Start
- diff --git a/tools/bddb/doedlog.php b/tools/bddb/doedlog.php deleted file mode 100644 index 7009aa7dad..0000000000 --- a/tools/bddb/doedlog.php +++ /dev/null @@ -1,76 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Log Entry Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '') - die("log number not specified!"); - $logno=intval($_REQUEST['logno']); - - $query="update log set"; - - if (isset($_REQUEST['date'])) { - $date=$_REQUEST['date']; - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', " . - "yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - } - - if (isset($_REQUEST['who'])) { - $who=$_REQUEST['who']; - $query.=", who='" . $who . "'"; - } - - if (isset($_REQUEST['details'])) { - $details=$_REQUEST['details']; - $query.=", details='" . rawurlencode($details) . "'"; - } - - $query.=" where serno=$serno and logno=$logno"; - - mysql_query($query); - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t

\n"; - echo "\t\t
\n"; - printf("\t\t\t%s\n", $errstr); - echo "\t\t
\n"; - echo "\t\n"; - } - else { - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe log entry with log number $logno and\n"; - echo "\t\t\tserial number $serno "; - echo "was successfully updated\n"; - echo "\t\t

\n"; - echo "\t\n"; - } - -?> -

- - - - - -
">Back to LogBack to Start
- diff --git a/tools/bddb/donew.php b/tools/bddb/donew.php deleted file mode 100644 index 39b2c78fca..0000000000 --- a/tools/bddb/donew.php +++ /dev/null @@ -1,230 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Board Registration Results"); - - if (isset($_REQUEST['serno'])) { - $serno=$_REQUEST['serno']; - die("serial number must not be set ($serno) when Creating!"); - } - - $query="update boards set"; - - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - - if ($batch != '') { - if (strlen($batch) > 32) - die("batch field too long (>32)"); - $query.=", batch='$batch'"; - } - - if (!in_array($type, $type_vals)) - die("Invalid type ($type) specified"); - $query.=", type='$type'"; - - if (($rev = intval($rev)) <= 0 || $rev > 255) - die("Revision number is invalid ($rev)"); - $query.=sprintf(", rev=%d", $rev); - - $query.=gather_enum_multi_query("sdram", 4); - - $query.=gather_enum_multi_query("flash", 4); - - $query.=gather_enum_multi_query("zbt", 16); - - $query.=gather_enum_multi_query("xlxtyp", 4); - $nxlx = count_enum_multi("xlxtyp", 4); - - $query.=gather_enum_multi_query("xlxspd", 4); - if (count_enum_multi("xlxspd", 4) != $nxlx) - die("number of xilinx speeds not same as number of types"); - - $query.=gather_enum_multi_query("xlxtmp", 4); - if (count_enum_multi("xlxtmp", 4) != $nxlx) - die("number of xilinx temps. not same as number of types"); - - $query.=gather_enum_multi_query("xlxgrd", 4); - if (count_enum_multi("xlxgrd", 4) != $nxlx) - die("number of xilinx grades not same as number of types"); - - if ($cputyp == '') { - if ($cpuspd != '') - die("can't specify cpu speed if there is no cpu"); - if ($cpmspd != '') - die("can't specify cpm speed if there is no cpu"); - if ($busspd != '') - die("can't specify bus speed if there is no cpu"); - } - else { - $query.=", cputyp='$cputyp'"; - if ($cpuspd == '') - die("must specify cpu speed if cpu type is defined"); - $query.=", cpuspd='$cpuspd'"; - if ($cpmspd == '') - die("must specify cpm speed if cpu type is defined"); - $query.=", cpmspd='$cpmspd'"; - if ($busspd == '') - die("must specify bus speed if cpu type is defined"); - $query.=", busspd='$busspd'"; - } - - if (($hschin = intval($hschin)) < 0 || $hschin > 4) - die("Invalid number of hs input chans ($hschin)"); - if (($hschout = intval($hschout)) < 0 || $hschout > 4) - die("Invalid number of hs output chans ($hschout)"); - if ($hstype == '') { - if ($hschin != 0) - die("number of high-speed input channels must be zero" - . " if high-speed chip is not present"); - if ($hschout != 0) - die("number of high-speed output channels must be zero" - . " if high-speed chip is not present"); - } - else - $query.=", hstype='$hstype'"; - $query.=", hschin='$hschin'"; - $query.=", hschout='$hschout'"; - - // echo "final query = '$query'
\n"; - - $quant = intval($quant); - if ($quant <= 0) $quant = 1; - - $sernos = array(); - if ($geneths) - $ethaddrs = array(); - - $sqlerr = ''; - - while ($quant-- > 0) { - - mysql_query("insert into boards (serno) values (null)"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - break; - } - - $serno = mysql_insert_id(); - if (!$serno) { - $sqlerr = "couldn't allocate new serial number"; - break; - } - - mysql_query($query . " where serno=$serno"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - break; - } - - array_push($sernos, $serno); - - if ($geneths) { - - $ethaddr = gen_eth_addr($serno); - - mysql_query("update boards set ethaddr='$ethaddr'" . - " where serno=$serno"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - - array_push($ethaddrs, - "" . - "db save fail" . - ""); - break; - } - - array_push($ethaddrs, $ethaddr); - } - } - - $nsernos = count($sernos); - - if ($nsernos > 0) { - - write_eeprom_cfg_file(); - - echo "\n"; - echo "\t

\n"; - echo "\t\tThe following board serial numbers were" - . " successfully allocated"; - if ($numerrs > 0) - echo " (but with $numerrs cfg file error" . - ($numerrs > 1 ? "s" : "") . ")"; - echo ":\n"; - echo "\t

\n"; - - echo "\n"; - - echo "\n"; - echo "\n"; - echo "\t\n"; - if ($numerrs > 0) - echo "\t\n"; - if ($geneths) - echo "\t\n"; - echo "\n"; - - for ($i = 0; $i < $nsernos; $i++) { - - $serno = sprintf("%010d", $sernos[$i]); - - echo "\n"; - - echo "\t\n"; - - if ($numerrs > 0) { - if (($errstr = $cfgerrs[$i]) == '') - $errstr = ' '; - echo "\t\n"; - } - - if ($geneths) { - echo "\t\n"; - } - - echo "\n"; - } - - echo "
Serial NumberCfg File ErrsEthernet Address
" . - "$serno" . - "" . - $errstr . - "" . - "" . - $ethaddrs[$i] . - "
\n"; - } - - if ($sqlerr != '') { - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe following SQL error was encountered:\n"; - echo "\t\t

\n"; - echo "\t\t
\n"; - printf("\t\t\t%s\n", $sqlerr); - echo "\t\t
\n"; - echo "\t\n"; - } - -?> -

- - - - - -
Go to BrowseBack to Start
- diff --git a/tools/bddb/donewlog.php b/tools/bddb/donewlog.php deleted file mode 100644 index 7635d2992d..0000000000 --- a/tools/bddb/donewlog.php +++ /dev/null @@ -1,86 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Add Log Entry Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified!"); - $serno=intval($_REQUEST['serno']); - - if (isset($_REQUEST['logno'])) { - $logno=$_REQUEST['logno']; - die("log number must not be set ($logno) when Creating!"); - } - - $query="update log set serno=$serno"; - - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')"); - $query.=", date='$date'"; - - if (isset($_REQUEST['who'])) { - $who=$_REQUEST['who']; - $query.=", who='" . $who . "'"; - } - - if (isset($_REQUEST['details'])) { - $details=$_REQUEST['details']; - $query.=", details='" . rawurlencode($details) . "'"; - } - - // echo "final query = '$query'
\n"; - - $sqlerr = ''; - - mysql_query("insert into log (logno) values (null)"); - if (mysql_errno()) - $sqlerr = mysql_error(); - else { - $logno = mysql_insert_id(); - if (!$logno) - $sqlerr = "couldn't allocate new serial number"; - else { - mysql_query($query . " where logno=$logno"); - if (mysql_errno()) - $sqlerr = mysql_error(); - } - } - - if ($sqlerr == '') { - echo "\n"; - echo "\t

\n"; - echo "\t\tA log entry with log number '$logno' was " . - "added to the board with serial number '$serno'\n"; - echo "\t

\n"; - echo "\n"; - } - else { - echo "\t\n"; - echo "\t\t

\n"; - echo "\t\t\tThe following SQL error was encountered:\n"; - echo "\t\t

\n"; - echo "\t\t
\n"; - printf("\t\t\t%s\n", $sqlerr); - echo "\t\t
\n"; - echo "\t\n"; - } - -?> -

- - - - - -
">Go to BrowseBack to Start
- diff --git a/tools/bddb/edit.php b/tools/bddb/edit.php deleted file mode 100644 index dd8c26c5cd..0000000000 --- a/tools/bddb/edit.php +++ /dev/null @@ -1,131 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Registration"); - - if ($serno == 0) - die("serial number not specified or invalid!"); - - $pserno = sprintf("%010d", $serno); - - echo "
"; - echo "Board Serial Number: $pserno"; - echo "
\n"; - -?> -

-

-\n"; - - $r=mysql_query("select * from boards where serno=$serno"); - $row=mysql_fetch_array($r); - if(!$row) die("no record of serial number '$serno' in database"); - - begin_table(5); - - // ethaddr char(17) - print_field("ethaddr", $row, 17); - - // date date - print_field("date", $row); - - // batch char(32) - print_field("batch", $row, 32); - - // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') - print_enum("type", $row, $type_vals); - - // rev tinyint(3) unsigned zerofill - print_field("rev", $row, 3, 'rev_filter'); - - // location char(64) - print_field("location", $row, 64); - - // comments text - print_field_multiline("comments", $row, 60, 10, 'text_filter'); - - // sdram[0-3] enum('32M','64M','128M','256M') - print_enum_multi("sdram", $row, $sdram_vals, 4, array()); - - // flash[0-3] enum('4M','8M','16M','32M','64M') - print_enum_multi("flash", $row, $flash_vals, 4, array()); - - // zbt[0-f] enum('512K','1M','2M','4M') - print_enum_multi("zbt", $row, $zbt_vals, 16, array()); - - // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E') - print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(), 1); - - // xlxspd[0-3] enum('6','7','8') - print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(), 1); - - // xlxtmp[0-3] enum('COM','IND') - print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(), 1); - - // xlxgrd[0-3] enum('NORMAL','ENGSAMP') - print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(), 1); - - // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)') - print_enum("cputyp", $row, $cputyp_vals); - - // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpuspd", $row, $clk_vals); - - // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpmspd", $row, $clk_vals); - - // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("busspd", $row, $clk_vals); - - // hstype enum('AMCC-S2064A') - print_enum("hstype", $row, $hstype_vals); - - // hschin enum('0','1','2','3','4') - print_enum("hschin", $row, $hschin_vals); - - // hschout enum('0','1','2','3','4') - print_enum("hschout", $row, $hschout_vals); - - end_table(); - - echo "

\n"; - echo "

"; - echo "WARNING: NO UNDO ON DELETE!"; - echo "

\n"; - echo "[ delete ]"; - echo "
\n"; - echo "

\n"; -?> -

- - - - - - - - -
- - -   - - - -   - - Back to Start -
-

-
- diff --git a/tools/bddb/edlog.php b/tools/bddb/edlog.php deleted file mode 100644 index 8befd35b92..0000000000 --- a/tools/bddb/edlog.php +++ /dev/null @@ -1,86 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Log Entry"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified!"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '') - die("log number not specified!"); - $logno=intval($_REQUEST['logno']); - - $pserno = sprintf("%010d", $serno); - $plogno = sprintf("%010d", $logno); - - echo "
"; - echo "Board Serial Number: $pserno, Log Number: $plogno"; - echo "
\n"; - -?> -

-

-\n"; - echo "\n"; - - $r=mysql_query("select * from log where serno=$serno and logno=$logno"); - $row=mysql_fetch_array($r); - if(!$row) - die("no record of log entry with serial number '$serno' " . - "and log number '$logno' in database"); - - begin_table(3); - - // date date - print_field("date", $row); - - // who char(20) - print_field("who", $row); - - // details text - print_field_multiline("details", $row, 60, 10, 'text_filter'); - - end_table(); - - echo "

\n"; - echo "

"; - echo "WARNING: NO UNDO ON DELETE!"; - echo "

\n"; - echo "[ delete ]"; - echo "
\n"; - echo "

\n"; -?> -

- - - - - - - - -
- - -   - - - -   - - Back to Start -
-

-
- diff --git a/tools/bddb/execute.php b/tools/bddb/execute.php deleted file mode 100644 index 0b62882d75..0000000000 --- a/tools/bddb/execute.php +++ /dev/null @@ -1,33 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:''; - - $submit=isset($_REQUEST['submit'])?$_REQUEST['submit']:"[NOT SET]"; - - switch ($submit) { - - case "New": - require("new.php"); - break; - - case "Edit": - require("edit.php"); - break; - - case "Browse": - require("browse.php"); - break; - - case "Log": - require("brlog.php"); - break; - - default: - require("badsubmit.php"); - break; - } -?> diff --git a/tools/bddb/index.php b/tools/bddb/index.php deleted file mode 100644 index 842aed55fb..0000000000 --- a/tools/bddb/index.php +++ /dev/null @@ -1,38 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - require("defs.php"); - pg_head("$bddb_label"); -?> - -
- - - - - - - - - - -
- - - - - - - -
- Serial Number: - -
-
- - diff --git a/tools/bddb/new.php b/tools/bddb/new.php deleted file mode 100644 index 30323ff819..0000000000 --- a/tools/bddb/new.php +++ /dev/null @@ -1,120 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - New Board Registration"); -?> -
-

- date("Y-m-d"))); - - // batch char(32) - print_field("batch", $row, 32); - - // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') - print_enum("type", $row, $type_vals, 0); - - // rev tinyint(3) unsigned zerofill - print_field("rev", $row, 3, 'rev_filter'); - - // sdram[0-3] enum('32M','64M','128M','256M') - print_enum_multi("sdram", $row, $sdram_vals, 4, array(2)); - - // flash[0-3] enum('4M','8M','16M','32M','64M') - print_enum_multi("flash", $row, $flash_vals, 4, array(2)); - - // zbt[0-f] enum('512K','1M','2M','4M') - print_enum_multi("zbt", $row, $zbt_vals, 16, array(2, 2)); - - // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E') - print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(1), 1); - - // xlxspd[0-3] enum('6','7','8') - print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(1), 1); - - // xlxtmp[0-3] enum('COM','IND') - print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(1), 1); - - // xlxgrd[0-3] enum('NORMAL','ENGSAMP') - print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(1), 1); - - // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)') - print_enum("cputyp", $row, $cputyp_vals, 1); - - // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpuspd", $row, $clk_vals, 4); - - // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpmspd", $row, $clk_vals, 4); - - // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("busspd", $row, $clk_vals, 2); - - // hstype enum('AMCC-S2064A') - print_enum("hstype", $row, $hstype_vals, 1); - - // hschin enum('0','1','2','3','4') - print_enum("hschin", $row, $hschin_vals, 4); - - // hschout enum('0','1','2','3','4') - print_enum("hschout", $row, $hschout_vals, 4); - - end_table(); -?> -

- - - - - - - - - - - - - - - -
- Allocate - - board serial number(s) -
- - Generate Ethernet Address(es) -
-   -
- - -   - - -
-
- diff --git a/tools/bddb/newlog.php b/tools/bddb/newlog.php deleted file mode 100644 index 609bb855c5..0000000000 --- a/tools/bddb/newlog.php +++ /dev/null @@ -1,54 +0,0 @@ - ?> - - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - New Log Entry"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified or invalid!"); - $serno=intval($_REQUEST['serno']); - - if (isset($_REQUEST['logno'])) { - $logno=$_REQUEST['logno']; - die("log number must not be specified when adding! ($logno)"); - } -?> -
-

-\n"; - - begin_table(3); - - // date date - print_field("date", array('date' => date("Y-m-d"))); - - // who char(20) - print_field("who", array()); - - // details text - print_field_multiline("details", array(), 60, 10, 'text_filter'); - - end_table(); -?> -

- - - - - -
- - - -
-
- diff --git a/tools/binutils-version.sh b/tools/binutils-version.sh deleted file mode 100755 index d4d9eb4361..0000000000 --- a/tools/binutils-version.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh -# -# binutils-version [-p] gas-command -# -# Prints the binutils version of `gas-command' in a canonical 4-digit form -# such as `0222' for binutils 2.22 -# - -gas="$*" - -if [ ${#gas} -eq 0 ]; then - echo "Error: No assembler specified." - printf "Usage:\n\t$0 \n" - exit 1 -fi - -MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1) -MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2) - -printf "%02d%02d\\n" $MAJOR $MINOR diff --git a/tools/bmp_logo.c b/tools/bmp_logo.c index b2ad3d5927..2247adcc82 100644 --- a/tools/bmp_logo.c +++ b/tools/bmp_logo.c @@ -179,7 +179,7 @@ int main (int argc, char *argv[]) printf("unsigned char bmp_logo_bitmap[] = {\n"); for (i=(b->height-1)*b->width; i>=0; i-=b->width) { for (x = 0; x < b->width; x++) { - b->data[(uint16_t) i + x] = (uint8_t) fgetc (fp) \ + b->data[i + x] = (uint8_t) fgetc(fp) + DEFAULT_CMAP_SIZE; } } diff --git a/tools/buildman/README b/tools/buildman/README index 734ada65a8..cf7bf5c17e 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -3,6 +3,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +(Please read 'How to change from MAKEALL' if you are used to that tool) + What is this? ============= @@ -39,9 +41,10 @@ Theory of Operation Buildman is a builder. It is not make, although it runs make. It does not produce any useful output on the terminal while building, except for -progress information. All the output (errors, warnings and binaries if you -are ask for them) is stored in output directories, which you can look at -while the build is progressing, or when it is finished. +progress information (except with -v, see below). All the output (errors, +warnings and binaries if you ask for them) is stored in output +directories, which you can look at while the build is progressing, or when +it is finished. Buildman produces a concise summary of which boards succeeded and failed. It shows which commit introduced which board failure using a simple @@ -71,16 +74,21 @@ directory. It clones this repository into a copy for each thread, and the threads do not affect the state of your git repository. Any checkouts done by the thread affect only the working directory for that thread. -Buildman automatically selects the correct toolchain for each board. You -must supply suitable toolchains, but buildman takes care of selecting the +Buildman automatically selects the correct tool chain for each board. You +must supply suitable tool chains, but buildman takes care of selecting the right one. -Buildman always builds a branch, and always builds the upstream commit as -well, for comparison. It cannot build individual commits at present, unless -(maybe) you point it at an empty branch. Put all your commits in a branch, -set the branch's upstream to a valid value, and all will be well. Otherwise -buildman will perform random actions. Use -n to check what the random -actions might be. +Buildman generally builds a branch (with the -b flag), and in this case +builds the upstream commit as well, for comparison. It cannot build +individual commits at present, unless (maybe) you point it at an empty +branch. Put all your commits in a branch, set the branch's upstream to a +valid value, and all will be well. Otherwise buildman will perform random +actions. Use -n to check what the random actions might be. + +If you just want to build the current source tree, leave off the -b flag +and add -e. This will display results and errors as they happen. You can +still look at them later using -se. Note that buildman will assume that the +source has changed, and will build all specified boards in this case. Buildman is optimised for building many commits at once, for many boards. On multi-core machines, Buildman is fast because it uses most of the @@ -89,10 +97,32 @@ a few commits or boards, it will be pretty slow. As a tip, if you don't plan to use your machine for anything else, you can use -T to increase the number of threads beyond the default. -Buildman lets you build all boards, or a subset. Specify the subset using -the board name, architecture name, SOC name, or anything else in the -boards.cfg file. So 'at91' will build all AT91 boards (arm), powerpc will -build all PowerPC boards. +Buildman lets you build all boards, or a subset. Specify the subset by passing +command-line arguments that list the desired board name, architecture name, +SOC name, or anything else in the boards.cfg file. Multiple arguments are +allowed. Each argument will be interpreted as a regular expression, so +behaviour is a superset of exact or substring matching. Examples are: + +* 'tegra20' All boards with a Tegra20 SoC +* 'tegra' All boards with any Tegra Soc (Tegra20, Tegra30, Tegra114...) +* '^tegra[23]0$' All boards with either Tegra20 or Tegra30 SoC +* 'powerpc' All PowerPC boards + +While the default is to OR the terms together, you can also make use of +the '&' operator to limit the selection: + +* 'freescale & arm sandbox' All Freescale boards with ARM architecture, + plus sandbox + +You can also use -x to specifically exclude some boards. For example: + + buildmand arm -x nvidia,freescale,.*ball$ + +means to build all arm boards except nvidia, freescale and anything ending +with 'ball'. + +It is convenient to use the -n option to see what will be built based on +the subset given. Buildman does not store intermediate object files. It optionally copies the binary output into a directory when a build is successful. Size @@ -111,8 +141,8 @@ $ git clone git://git.denx.de/u-boot.git . $ git checkout -b my-branch origin/master $ # Add some commits to the branch, reading for testing -2. Create ~/.buildman to tell buildman where to find tool chains. As an -example: +2. Create ~/.buildman to tell buildman where to find tool chains (see 'The +.buildman file' later for details). As an example: # Buildman settings file @@ -120,6 +150,8 @@ example: root: / rest: /toolchains/* eldk: /opt/eldk-4.2 +arm: /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux +aarch64: /opt/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.10_linux [toolchain-alias] x86: i386 @@ -139,7 +171,16 @@ The toolchain-alias section indicates that the i386 toolchain should be used to build x86 commits. -2. Check the available toolchains +3. Make sure you have the require Python pre-requisites + +Buildman uses multiprocessing, Queue, shutil, StringIO, ConfigParser and +urllib2. These should normally be available, but if you get an error like +this then you will need to obtain those modules: + + ImportError: No module named multiprocessing + + +4. Check the available toolchains Run this check to make sure that you have a toolchain for every architecture. @@ -269,6 +310,47 @@ You can see that everything is covered, even some strange ones that won't be used (c88 and c99). This is a feature. +5. Install new toolchains if needed + +You can download toolchains and update the [toolchain] section of the +settings file to find them. + +To make this easier, buildman can automatically download and install +toolchains from kernel.org. First list the available architectures: + +$ ./tools/buildman/buildman sandbox --fetch-arch list +Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ +Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/ +Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/ +Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.2.4/ +Available architectures: alpha am33_2.0 arm avr32 bfin cris crisv32 frv h8300 +hppa hppa64 i386 ia64 m32r m68k mips mips64 or32 powerpc powerpc64 s390x sh4 +sparc sparc64 tilegx x86_64 xtensa + +Then pick one and download it: + +$ ./tools/buildman/buildman sandbox --fetch-arch or32 +Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ +Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/ +Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/ +Downloading: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1//x86_64-gcc-4.5.1-nolibc_or32-linux.tar.xz +Unpacking to: /home/sjg/.buildman-toolchains +Testing + - looking in '/home/sjg/.buildman-toolchains/gcc-4.5.1-nolibc/or32-linux/.' + - looking in '/home/sjg/.buildman-toolchains/gcc-4.5.1-nolibc/or32-linux/bin' + - found '/home/sjg/.buildman-toolchains/gcc-4.5.1-nolibc/or32-linux/bin/or32-linux-gcc' +Tool chain test: OK + +Buildman should now be set up to use your new toolchain. + +At the time of writing, U-Boot has these architectures: + + arc, arm, avr32, blackfin, m68k, microblaze, mips, nds32, nios2, openrisc + powerpc, sandbox, sh, sparc, x86 + +Of these, only arc, microblaze and nds32 are not available at kernel.org.. + + How to run it ============= @@ -278,10 +360,11 @@ branch with a valid upstream) $ ./tools/buildman/buildman -b -n If it can't detect the upstream branch, try checking out the branch, and -doing something like 'git branch --set-upstream upstream/master' -or something similar. +doing something like 'git branch --set-upstream-to upstream/master' +or something similar. Buildman will try to guess a suitable upstream branch +if it can't find one (you will see a message like" Guessing upstream as ...). -As an exmmple: +As an example: Dry run, so not doing much. But I would do this: @@ -333,13 +416,13 @@ Building 18 commits for 1059 boards (4 threads, 1 job per thread) 528 36 124 /19062 1:13:30 : SIMPC8313_SP This means that it is building 19062 board/commit combinations. So far it -has managed to succesfully build 528. Another 36 have built with warnings, +has managed to successfully build 528. Another 36 have built with warnings, and 124 more didn't build at all. Buildman expects to complete the process in an hour and 15 minutes. Use this time to buy a faster computer. To find out how the build went, ask for a summary with -s. You can do this -either before the build completes (presumably in another terminal) or or +either before the build completes (presumably in another terminal) or afterwards. Let's work through an example of how this is used: $ ./tools/buildman/buildman -b lcd9b -s @@ -407,10 +490,14 @@ again. At commit 16, the error moves - you can see that the old error at line 120 is fixed, but there is a new one at line 126. This is probably only because -we added some code and moved the broken line futher down the file. +we added some code and moved the broken line further down the file. If many boards have the same error, then -e will display the error only -once. This makes the output as concise as possible. +once. This makes the output as concise as possible. To see which boards have +each error, use -l. + +Buildman tries to distinguish warnings from errors, and shows warning lines +separately with a 'w' prefix. The full build output in this case is available in: @@ -485,7 +572,7 @@ You can also use -d to see a detailed size breakdown for each board. This list is sorted in order from largest growth to largest reduction. It is possible to go a little further with the -B option (--bloat). This -shows where U-Boot has bloted, breaking the size change down to the function +shows where U-Boot has bloated, breaking the size change down to the function level. Example output is below: $ ./tools/buildman/buildman -b us-mem4 -sSdB @@ -611,8 +698,8 @@ This shows that commit 19 has increased text size for arm (although only one board was built) and by 96 bytes for powerpc. This increase was offset in both cases by reductions in rodata and data/bss. -Shown below the summary lines is the sizes for each board. Below each board -is the sizes for each function. This information starts with: +Shown below the summary lines are the sizes for each board. Below each board +are the sizes for each function. This information starts with: add - number of functions added / removed grow - number of functions which grew / shrunk @@ -629,22 +716,206 @@ It is common when refactoring code for the rodata to decrease as the text size increases, and vice versa. +The .buildman file +================== + +The .buildman file provides information about the available toolchains and +also allows build flags to be passed to 'make'. It consists of several +sections, with the section name in square brackets. Within each section are +a set of (tag, value) pairs. + +'[toolchain]' section + + This lists the available toolchains. The tag here doesn't matter, but + make sure it is unique. The value is the path to the toolchain. Buildman + will look in that path for a file ending in 'gcc'. It will then execute + it to check that it is a C compiler, passing only the --version flag to + it. If the return code is 0, buildman assumes that it is a valid C + compiler. It uses the first part of the name as the architecture and + strips off the last part when setting the CROSS_COMPILE environment + variable (parts are delimited with a hyphen). + + For example powerpc-linux-gcc will be noted as a toolchain for 'powerpc' + and CROSS_COMPILE will be set to powerpc-linux- when using it. + +'[toolchain-alias]' section + + This converts toolchain architecture names to U-Boot names. For example, + if an x86 toolchains is called i386-linux-gcc it will not normally be + used for architecture 'x86'. Adding 'x86: i386 x86_64' to this section + will tell buildman that the i386 and x86_64 toolchains can be used for + the x86 architecture. + +'[make-flags]' section + + U-Boot's build system supports a few flags (such as BUILD_TAG) which + affect the build product. These flags can be specified in the buildman + settings file. They can also be useful when building U-Boot against other + open source software. + + [make-flags] + at91-boards=ENABLE_AT91_TEST=1 + snapper9260=${at91-boards} BUILD_TAG=442 + snapper9g45=${at91-boards} BUILD_TAG=443 + + This will use 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260 + and 'make ENABLE_AT91_TEST=1 BUILD_TAG=443' for snapper9g45. A special + variable ${target} is available to access the target name (snapper9260 + and snapper9g20 in this case). Variables are resolved recursively. Note + that variables can only contain the characters A-Z, a-z, 0-9, hyphen (-) + and underscore (_). + + It is expected that any variables added are dealt with in U-Boot's + config.mk file and documented in the README. + + Note that you can pass ad-hoc options to the build using environment + variables, for example: + + SOME_OPTION=1234 ./tools/buildman/buildman my_board + + +Quick Sanity Check +================== + +If you have made changes and want to do a quick sanity check of the +currently checked-out source, run buildman without the -b flag. This will +build the selected boards and display build status as it runs (i.e. -v is +enabled automatically). Use -e to see errors/warnings as well. + + +Building Ranges +=============== + +You can build a range of commits by specifying a range instead of a branch +when using the -b flag. For example: + + upstream/master..us-buildman + +will build commits in us-buildman that are not in upstream/master. + + Other options ============= Buildman has various other command line options. Try --help to see them. +When doing builds, Buildman's return code will reflect the overall result: + + 0 (success) No errors or warnings found + 128 Errors found + 129 Warnings found + + +How to change from MAKEALL +========================== + +Buildman includes most of the features of MAKEALL and is generally faster +and easier to use. In particular it builds entire branches: if a particular +commit introduces an error in a particular board, buildman can easily show +you this, even if a later commit fixes that error. + +The reasons to deprecate MAKEALL are: +- We don't want to maintain two build systems +- Buildman is typically faster +- Buildman has a lot more features + +But still, many people will be sad to lose MAKEALL. If you are used to +MAKEALL, here are a few pointers. + +First you need to set up your tool chains - see the 'Setting up' section +for details. Once you have your required toolchain(s) detected then you are +ready to go. + +To build the current source tree, run buildman without a -b flag: + + ./tools/buildman/buildman + +This will build the current source tree for the given boards and display +the results and errors. + +However buildman usually works on entire branches, and for that you must +specify a board flag: + + ./tools/buildman/buildman -b + +followed by (afterwards, or perhaps concurrently in another terminal): + + ./tools/buildman/buildman -b -s + +to see the results of the build. Rather than showing you all the output, +buildman just shows a summary, with red indicating that a commit introduced +an error and green indicating that a commit fixed an error. Use the -e +flag to see the full errors and -l to see which boards caused which errors. + +If you really want to see build results as they happen, use -v when doing a +build (and -e to see the errors/warnings too). + +You don't need to stick around on that branch while buildman is running. It +checks out its own copy of the source code, so you can change branches, +add commits, etc. without affecting the build in progress. + +The can include board names, architectures or the +like. There are no flags to disambiguate since ambiguities are rare. Using +the examples from MAKEALL: + +Examples: + - build all Power Architecture boards: + MAKEALL -a powerpc + MAKEALL --arch powerpc + MAKEALL powerpc + ** buildman -b powerpc + - build all PowerPC boards manufactured by vendor "esd": + MAKEALL -a powerpc -v esd + ** buildman -b esd + - build all PowerPC boards manufactured either by "keymile" or "siemens": + MAKEALL -a powerpc -v keymile -v siemens + ** buildman -b keymile siemens + - build all Freescale boards with MPC83xx CPUs, plus all 4xx boards: + MAKEALL -c mpc83xx -v freescale 4xx + ** buildman -b mpc83xx freescale 4xx + +Buildman automatically tries to use all the CPUs in your machine. If you +are building a lot of boards it will use one thread for every CPU core +it detects in your machine. This is like MAKEALL's BUILD_NBUILDS option. +You can use the -T flag to change the number of threads. If you are only +building a few boards, buildman will automatically run make with the -j +flag to increase the number of concurrent make tasks. It isn't normally +that helpful to fiddle with this option, but if you use the BUILD_NCPUS +option in MAKEALL then -j is the equivalent in buildman. + +Buildman puts its output in ../ by default but you can change +this with the -o option. Buildman normally does out-of-tree builds: use -i +to disable that if you really want to. But be careful that once you have +used -i you pollute buildman's copies of the source tree, and you will need +to remove the build directory (normally ../) to run buildman +in normal mode (without -i). + +Buildman doesn't keep the output result normally, but use the -k option to +do this. + +Please read 'Theory of Operation' a few times as it will make a lot of +things clearer. + +Some options you might like are: + + -B shows which functions are growing/shrinking in which commit - great + for finding code bloat. + -S shows image sizes for each commit (just an overall summary) + -u shows boards that you haven't built yet + --step 0 will build just the upstream commit and the last commit of your + branch. This is often a quick sanity check that your branch doesn't + break anything. But note this does not check bisectability! + TODO ==== This has mostly be written in my spare time as a response to my difficulties in testing large series of patches. Apart from tidying up there is quite a -bit of scope for improvement. Things like better error diffs, easier access -to log files, error display while building. Also it would be nice it buildman -could 'hunt' for problems, perhaps by building a few boards for each arch, -or checking commits for changed files and building only boards which use -those files. +bit of scope for improvement. Things like better error diffs and easier +access to log files. Also it would be nice if buildman could 'hunt' for +problems, perhaps by building a few boards for each arch, or checking +commits for changed files and building only boards which use those files. Credits @@ -655,7 +926,6 @@ the build speed by building all commits for a board instead of the other way around. - Simon Glass sjg@chromium.org Halloween 2012 diff --git a/tools/buildman/board.py b/tools/buildman/board.py index cc7b5d011f..5d536d5f20 100644 --- a/tools/buildman/board.py +++ b/tools/buildman/board.py @@ -3,18 +3,87 @@ # SPDX-License-Identifier: GPL-2.0+ # +import re + +class Expr: + """A single regular expression for matching boards to build""" + + def __init__(self, expr): + """Set up a new Expr object. + + Args: + expr: String cotaining regular expression to store + """ + self._expr = expr + self._re = re.compile(expr) + + def Matches(self, props): + """Check if any of the properties match the regular expression. + + Args: + props: List of properties to check + Returns: + True if any of the properties match the regular expression + """ + for prop in props: + if self._re.match(prop): + return True + return False + + def __str__(self): + return self._expr + +class Term: + """A list of expressions each of which must match with properties. + + This provides a list of 'AND' expressions, meaning that each must + match the board properties for that board to be built. + """ + def __init__(self): + self._expr_list = [] + self._board_count = 0 + + def AddExpr(self, expr): + """Add an Expr object to the list to check. + + Args: + expr: New Expr object to add to the list of those that must + match for a board to be built. + """ + self._expr_list.append(Expr(expr)) + + def __str__(self): + """Return some sort of useful string describing the term""" + return '&'.join([str(expr) for expr in self._expr_list]) + + def Matches(self, props): + """Check if any of the properties match this term + + Each of the expressions in the term is checked. All must match. + + Args: + props: List of properties to check + Returns: + True if all of the expressions in the Term match, else False + """ + for expr in self._expr_list: + if not expr.Matches(props): + return False + return True + class Board: """A particular board that we can build""" - def __init__(self, target, arch, cpu, board_name, vendor, soc, options): + def __init__(self, status, arch, cpu, soc, vendor, board_name, target, options): """Create a new board type. Args: - target: Target name (use make _config to configure) + status: define whether the board is 'Active' or 'Orphaned' arch: Architecture name (e.g. arm) cpu: Cpu name (e.g. arm1136) - board_name: Name of board (e.g. integrator) - vendor: Name of vendor (e.g. armltd) soc: Name of SOC, or '' if none (e.g. mx31) + vendor: Name of vendor (e.g. armltd) + board_name: Name of board (e.g. integrator) + target: Target name (use make _defconfig to configure) options: board-specific options (e.g. integratorcp:CM1136) """ self.target = target @@ -63,8 +132,10 @@ class Boards: for upto in range(len(fields)): if fields[upto] == '-': fields[upto] = '' - while len(fields) < 7: + while len(fields) < 8: fields.append('') + if len(fields) > 8: + fields = fields[:8] board = Board(*fields) self.AddBoard(board) @@ -119,33 +190,102 @@ class Boards: """ return [board.target for board in self._boards if board.build_it] - def SelectBoards(self, args): + def _BuildTerms(self, args): + """Convert command line arguments to a list of terms. + + This deals with parsing of the arguments. It handles the '&' + operator, which joins several expressions into a single Term. + + For example: + ['arm & freescale sandbox', 'tegra'] + + will produce 3 Terms containing expressions as follows: + arm, freescale + sandbox + tegra + + The first Term has two expressions, both of which must match for + a board to be selected. + + Args: + args: List of command line arguments + Returns: + A list of Term objects + """ + syms = [] + for arg in args: + for word in arg.split(): + sym_build = [] + for term in word.split('&'): + if term: + sym_build.append(term) + sym_build.append('&') + syms += sym_build[:-1] + terms = [] + term = None + oper = None + for sym in syms: + if sym == '&': + oper = sym + elif oper: + term.AddExpr(sym) + oper = None + else: + if term: + terms.append(term) + term = Term() + term.AddExpr(sym) + if term: + terms.append(term) + return terms + + def SelectBoards(self, args, exclude=[]): """Mark boards selected based on args Args: - List of strings specifying boards to include, either named, or - by their target, architecture, cpu, vendor or soc. If empty, all - boards are selected. + args: List of strings specifying boards to include, either named, + or by their target, architecture, cpu, vendor or soc. If + empty, all boards are selected. + exclude: List of boards to exclude, regardless of 'args' Returns: Dictionary which holds the number of boards which were selected due to each argument, arranged by argument. """ result = {} - for arg in args: - result[arg] = 0 + terms = self._BuildTerms(args) + result['all'] = 0 + for term in terms: + result[str(term)] = 0 + + exclude_list = [] + for expr in exclude: + exclude_list.append(Expr(expr)) for board in self._boards: - if args: - for arg in args: - if arg in board.props: - if not board.build_it: - board.build_it = True - result[arg] += 1 - result['all'] += 1 + matching_term = None + build_it = False + if terms: + match = False + for term in terms: + if term.Matches(board.props): + matching_term = str(term) + build_it = True + break else: + build_it = True + + # Check that it is not specifically excluded + for expr in exclude_list: + if expr.Matches(board.props): + build_it = False + break + + if build_it: board.build_it = True + if matching_term: + result[matching_term] += 1 result['all'] += 1 return result diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py index c80113056c..b361469180 100644 --- a/tools/buildman/bsettings.py +++ b/tools/buildman/bsettings.py @@ -5,6 +5,7 @@ import ConfigParser import os +import StringIO def Setup(fname=''): @@ -17,11 +18,15 @@ def Setup(fname=''): global config_fname settings = ConfigParser.SafeConfigParser() - config_fname = fname - if config_fname == '': - config_fname = '%s/.buildman' % os.getenv('HOME') - if config_fname: - settings.read(config_fname) + if fname is not None: + config_fname = fname + if config_fname == '': + config_fname = '%s/.buildman' % os.getenv('HOME') + if config_fname: + settings.read(config_fname) + +def AddFile(data): + settings.readfp(StringIO.StringIO(data)) def GetItems(section): """Get the items from a section of the config. @@ -35,10 +40,16 @@ def GetItems(section): try: return settings.items(section) except ConfigParser.NoSectionError as e: - print e - print ("Warning: No tool chains - please add a [toolchain] section " - "to your buildman config file %s. See README for details" % - config_fname) return [] except: raise + +def SetItem(section, tag, value): + """Set an item and write it back to the settings file""" + global settings + global config_fname + + settings.set(section, tag, value) + if config_fname is not None: + with open(config_fname, 'w') as fd: + settings.write(fd) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 29da67a54e..1b0ad99275 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -6,7 +6,6 @@ # import collections -import errno from datetime import datetime, timedelta import glob import os @@ -15,12 +14,13 @@ import Queue import shutil import string import sys -import threading import time +import builderthread import command import gitutil import terminal +from terminal import Print import toolchain @@ -97,389 +97,6 @@ OUTCOME_OK, OUTCOME_WARNING, OUTCOME_ERROR, OUTCOME_UNKNOWN = range(4) trans_valid_chars = string.maketrans("/: ", "---") -def Mkdir(dirname): - """Make a directory if it doesn't already exist. - - Args: - dirname: Directory to create - """ - try: - os.mkdir(dirname) - except OSError as err: - if err.errno == errno.EEXIST: - pass - else: - raise - -class BuilderJob: - """Holds information about a job to be performed by a thread - - Members: - board: Board object to build - commits: List of commit options to build. - """ - def __init__(self): - self.board = None - self.commits = [] - - -class ResultThread(threading.Thread): - """This thread processes results from builder threads. - - It simply passes the results on to the builder. There is only one - result thread, and this helps to serialise the build output. - """ - def __init__(self, builder): - """Set up a new result thread - - Args: - builder: Builder which will be sent each result - """ - threading.Thread.__init__(self) - self.builder = builder - - def run(self): - """Called to start up the result thread. - - We collect the next result job and pass it on to the build. - """ - while True: - result = self.builder.out_queue.get() - self.builder.ProcessResult(result) - self.builder.out_queue.task_done() - - -class BuilderThread(threading.Thread): - """This thread builds U-Boot for a particular board. - - An input queue provides each new job. We run 'make' to build U-Boot - and then pass the results on to the output queue. - - Members: - builder: The builder which contains information we might need - thread_num: Our thread number (0-n-1), used to decide on a - temporary directory - """ - def __init__(self, builder, thread_num): - """Set up a new builder thread""" - threading.Thread.__init__(self) - self.builder = builder - self.thread_num = thread_num - - def Make(self, commit, brd, stage, cwd, *args, **kwargs): - """Run 'make' on a particular commit and board. - - The source code will already be checked out, so the 'commit' - argument is only for information. - - Args: - commit: Commit object that is being built - brd: Board object that is being built - stage: Stage of the build. Valid stages are: - distclean - can be called to clean source - config - called to configure for a board - build - the main make invocation - it does the build - args: A list of arguments to pass to 'make' - kwargs: A list of keyword arguments to pass to command.RunPipe() - - Returns: - CommandResult object - """ - return self.builder.do_make(commit, brd, stage, cwd, *args, - **kwargs) - - def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build): - """Build a particular commit. - - If the build is already done, and we are not forcing a build, we skip - the build and just return the previously-saved results. - - Args: - commit_upto: Commit number to build (0...n-1) - brd: Board object to build - work_dir: Directory to which the source will be checked out - do_config: True to run a make _config on the source - force_build: Force a build even if one was previously done - - Returns: - tuple containing: - - CommandResult object containing the results of the build - - boolean indicating whether 'make config' is still needed - """ - # Create a default result - it will be overwritte by the call to - # self.Make() below, in the event that we do a build. - result = command.CommandResult() - result.return_code = 0 - out_dir = os.path.join(work_dir, 'build') - - # Check if the job was already completed last time - done_file = self.builder.GetDoneFile(commit_upto, brd.target) - result.already_done = os.path.exists(done_file) - if result.already_done and not force_build: - # Get the return code from that build and use it - with open(done_file, 'r') as fd: - result.return_code = int(fd.readline()) - err_file = self.builder.GetErrFile(commit_upto, brd.target) - if os.path.exists(err_file) and os.stat(err_file).st_size: - result.stderr = 'bad' - else: - # We are going to have to build it. First, get a toolchain - if not self.toolchain: - try: - self.toolchain = self.builder.toolchains.Select(brd.arch) - except ValueError as err: - result.return_code = 10 - result.stdout = '' - result.stderr = str(err) - # TODO(sjg@chromium.org): This gets swallowed, but needs - # to be reported. - - if self.toolchain: - # Checkout the right commit - if commit_upto is not None: - commit = self.builder.commits[commit_upto] - if self.builder.checkout: - git_dir = os.path.join(work_dir, '.git') - gitutil.Checkout(commit.hash, git_dir, work_dir, - force=True) - else: - commit = self.builder.commit # Ick, fix this for BuildCommits() - - # Set up the environment and command line - env = self.toolchain.MakeEnvironment() - Mkdir(out_dir) - args = ['O=build', '-s'] - if self.builder.num_jobs is not None: - args.extend(['-j', str(self.builder.num_jobs)]) - config_args = ['%s_config' % brd.target] - config_out = '' - - # If we need to reconfigure, do that now - if do_config: - result = self.Make(commit, brd, 'distclean', work_dir, - 'distclean', *args, env=env) - result = self.Make(commit, brd, 'config', work_dir, - *(args + config_args), env=env) - config_out = result.combined - do_config = False # No need to configure next time - if result.return_code == 0: - result = self.Make(commit, brd, 'build', work_dir, *args, - env=env) - result.stdout = config_out + result.stdout - else: - result.return_code = 1 - result.stderr = 'No tool chain for %s\n' % brd.arch - result.already_done = False - - result.toolchain = self.toolchain - result.brd = brd - result.commit_upto = commit_upto - result.out_dir = out_dir - return result, do_config - - def _WriteResult(self, result, keep_outputs): - """Write a built result to the output directory. - - Args: - result: CommandResult object containing result to write - keep_outputs: True to store the output binaries, False - to delete them - """ - # Fatal error - if result.return_code < 0: - return - - # Aborted? - if result.stderr and 'No child processes' in result.stderr: - return - - if result.already_done: - return - - # Write the output and stderr - output_dir = self.builder._GetOutputDir(result.commit_upto) - Mkdir(output_dir) - build_dir = self.builder.GetBuildDir(result.commit_upto, - result.brd.target) - Mkdir(build_dir) - - outfile = os.path.join(build_dir, 'log') - with open(outfile, 'w') as fd: - if result.stdout: - fd.write(result.stdout) - - errfile = self.builder.GetErrFile(result.commit_upto, - result.brd.target) - if result.stderr: - with open(errfile, 'w') as fd: - fd.write(result.stderr) - elif os.path.exists(errfile): - os.remove(errfile) - - if result.toolchain: - # Write the build result and toolchain information. - done_file = self.builder.GetDoneFile(result.commit_upto, - result.brd.target) - with open(done_file, 'w') as fd: - fd.write('%s' % result.return_code) - with open(os.path.join(build_dir, 'toolchain'), 'w') as fd: - print >>fd, 'gcc', result.toolchain.gcc - print >>fd, 'path', result.toolchain.path - print >>fd, 'cross', result.toolchain.cross - print >>fd, 'arch', result.toolchain.arch - fd.write('%s' % result.return_code) - - with open(os.path.join(build_dir, 'toolchain'), 'w') as fd: - print >>fd, 'gcc', result.toolchain.gcc - print >>fd, 'path', result.toolchain.path - - # Write out the image and function size information and an objdump - env = result.toolchain.MakeEnvironment() - lines = [] - for fname in ['u-boot', 'spl/u-boot-spl']: - cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname] - nm_result = command.RunPipe([cmd], capture=True, - capture_stderr=True, cwd=result.out_dir, - raise_on_error=False, env=env) - if nm_result.stdout: - nm = self.builder.GetFuncSizesFile(result.commit_upto, - result.brd.target, fname) - with open(nm, 'w') as fd: - print >>fd, nm_result.stdout, - - cmd = ['%sobjdump' % self.toolchain.cross, '-h', fname] - dump_result = command.RunPipe([cmd], capture=True, - capture_stderr=True, cwd=result.out_dir, - raise_on_error=False, env=env) - rodata_size = '' - if dump_result.stdout: - objdump = self.builder.GetObjdumpFile(result.commit_upto, - result.brd.target, fname) - with open(objdump, 'w') as fd: - print >>fd, dump_result.stdout, - for line in dump_result.stdout.splitlines(): - fields = line.split() - if len(fields) > 5 and fields[1] == '.rodata': - rodata_size = fields[2] - - cmd = ['%ssize' % self.toolchain.cross, fname] - size_result = command.RunPipe([cmd], capture=True, - capture_stderr=True, cwd=result.out_dir, - raise_on_error=False, env=env) - if size_result.stdout: - lines.append(size_result.stdout.splitlines()[1] + ' ' + - rodata_size) - - # Write out the image sizes file. This is similar to the output - # of binutil's 'size' utility, but it omits the header line and - # adds an additional hex value at the end of each line for the - # rodata size - if len(lines): - sizes = self.builder.GetSizesFile(result.commit_upto, - result.brd.target) - with open(sizes, 'w') as fd: - print >>fd, '\n'.join(lines) - - # Now write the actual build output - if keep_outputs: - patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', - 'include/autoconf.mk', 'spl/u-boot-spl', - 'spl/u-boot-spl.bin'] - for pattern in patterns: - file_list = glob.glob(os.path.join(result.out_dir, pattern)) - for fname in file_list: - shutil.copy(fname, build_dir) - - - def RunJob(self, job): - """Run a single job - - A job consists of a building a list of commits for a particular board. - - Args: - job: Job to build - """ - brd = job.board - work_dir = self.builder.GetThreadDir(self.thread_num) - self.toolchain = None - if job.commits: - # Run 'make board_config' on the first commit - do_config = True - commit_upto = 0 - force_build = False - for commit_upto in range(0, len(job.commits), job.step): - result, request_config = self.RunCommit(commit_upto, brd, - work_dir, do_config, - force_build or self.builder.force_build) - failed = result.return_code or result.stderr - if failed and not do_config: - # If our incremental build failed, try building again - # with a reconfig. - if self.builder.force_config_on_failure: - result, request_config = self.RunCommit(commit_upto, - brd, work_dir, True, True) - do_config = request_config - - # If we built that commit, then config is done. But if we got - # an warning, reconfig next time to force it to build the same - # files that created warnings this time. Otherwise an - # incremental build may not build the same file, and we will - # think that the warning has gone away. - # We could avoid this by using -Werror everywhere... - # For errors, the problem doesn't happen, since presumably - # the build stopped and didn't generate output, so will retry - # that file next time. So we could detect warnings and deal - # with them specially here. For now, we just reconfigure if - # anything goes work. - # Of course this is substantially slower if there are build - # errors/warnings (e.g. 2-3x slower even if only 10% of builds - # have problems). - if (failed and not result.already_done and not do_config and - self.builder.force_config_on_failure): - # If this build failed, try the next one with a - # reconfigure. - # Sometimes if the board_config.h file changes it can mess - # with dependencies, and we get: - # make: *** No rule to make target `include/autoconf.mk', - # needed by `depend'. - do_config = True - force_build = True - else: - force_build = False - if self.builder.force_config_on_failure: - if failed: - do_config = True - result.commit_upto = commit_upto - if result.return_code < 0: - raise ValueError('Interrupt') - - # We have the build results, so output the result - self._WriteResult(result, job.keep_outputs) - self.builder.out_queue.put(result) - else: - # Just build the currently checked-out build - result = self.RunCommit(None, True) - result.commit_upto = self.builder.upto - self.builder.out_queue.put(result) - - def run(self): - """Our thread's run function - - This thread picks a job from the queue, runs it, and then goes to the - next job. - """ - alive = True - while True: - job = self.builder.queue.get() - try: - if self.builder.active and alive: - self.RunJob(job) - except Exception as err: - alive = False - print err - self.builder.queue.task_done() - - class Builder: """Class for building U-Boot for a particular commit. @@ -497,6 +114,8 @@ class Builder: force_config_on_failure: If a commit fails for a board, disable incremental building for the next commit we build for that board, so that we will see all warnings/errors again. + force_build_failures: If a previously-built build (i.e. built on + a previous run of buildman) is marked as failed, rebuild it. git_dir: Git directory containing source repository last_line_len: Length of the last line we printed (used for erasing it with new progress information) @@ -509,10 +128,20 @@ class Builder: toolchains: Toolchains object to use for building upto: Current commit number we are building (0.count-1) warned: Number of builds that produced at least one warning + force_reconfig: Reconfigure U-Boot on each comiit. This disables + incremental building, where buildman reconfigures on the first + commit for a baord, and then just does an incremental build for + the following commits. In fact buildman will reconfigure and + retry for any failing commits, so generally the only effect of + this option is to slow things down. + in_tree: Build U-Boot in-tree instead of specifying an output + directory separate from the source code. This option is really + only useful for testing in-tree builds. Private members: _base_board_dict: Last-summarised Dict of boards _base_err_lines: Last-summarised list of errors + _base_warn_lines: Last-summarised list of warnings _build_period_us: Time taken for a single build (float object). _complete_delay: Expected delay until completion (timedelta) _next_delay_update: Next time we plan to display a progress update @@ -545,7 +174,8 @@ class Builder: self.func_sizes = func_sizes def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs, - checkout=True, show_unknown=True, step=1): + gnu_make='make', checkout=True, show_unknown=True, step=1, + no_subdirs=False, full_path=False, verbose_build=False): """Create a new Builder object Args: @@ -554,10 +184,16 @@ class Builder: git_dir: Git directory containing source repository num_threads: Number of builder threads to run num_jobs: Number of jobs to run at once (passed to make as -j) + gnu_make: the command name of GNU Make. checkout: True to check out source, False to skip that step. This is used for testing. show_unknown: Show unknown boards (those not built) in summary step: 1 to process every commit, n to process every nth commit + no_subdirs: Don't create subdirectories when building current + source for a single board + full_path: Return the full path in CROSS_COMPILE and don't set + PATH + verbose_build: Run build with V=1 and don't use 'make -s' """ self.toolchains = toolchains self.base_dir = base_dir @@ -565,6 +201,7 @@ class Builder: self.threads = [] self.active = True self.do_make = self.Make + self.gnu_make = gnu_make self.checkout = checkout self.num_threads = num_threads self.num_jobs = num_jobs @@ -577,20 +214,32 @@ class Builder: self._complete_delay = None self._next_delay_update = datetime.now() self.force_config_on_failure = True + self.force_build_failures = False + self.force_reconfig = False self._step = step + self.in_tree = False + self._error_lines = 0 + self.no_subdirs = no_subdirs + self.full_path = full_path + self.verbose_build = verbose_build self.col = terminal.Color() + self._re_function = re.compile('(.*): In function.*') + self._re_files = re.compile('In file included from.*') + self._re_warning = re.compile('(.*):(\d*):(\d*): warning: .*') + self._re_note = re.compile('(.*):(\d*):(\d*): note: this is the location of the previous.*') + self.queue = Queue.Queue() self.out_queue = Queue.Queue() for i in range(self.num_threads): - t = BuilderThread(self, i) + t = builderthread.BuilderThread(self, i) t.setDaemon(True) t.start() self.threads.append(t) self.last_line_len = 0 - t = ResultThread(self) + t = builderthread.ResultThread(self) t.setDaemon(True) t.start() self.threads.append(t) @@ -603,6 +252,23 @@ class Builder: for t in self.threads: del t + def SetDisplayOptions(self, show_errors=False, show_sizes=False, + show_detail=False, show_bloat=False, + list_error_boards=False): + """Setup display options for the builder. + + show_errors: True to show summarised error/warning info + show_sizes: Show size deltas + show_detail: Show detail for each board + show_bloat: Show detail for each function + list_error_boards: Show the boards which caused each error/warning + """ + self._show_errors = show_errors + self._show_sizes = show_sizes + self._show_detail = show_detail + self._show_bloat = show_bloat + self._list_error_boards = list_error_boards + def _AddTimestamp(self): """Add a new timestamp to the list and record the build period. @@ -643,8 +309,8 @@ class Builder: length: Length of new line, in characters """ if length < self.last_line_len: - print ' ' * (self.last_line_len - length), - print '\r', + Print(' ' * (self.last_line_len - length), newline=False) + Print('\r', newline=False) self.last_line_len = length sys.stdout.flush() @@ -661,12 +327,12 @@ class Builder: Args: commit: Commit object that is being built brd: Board object that is being built - stage: Stage that we are at (distclean, config, build) + stage: Stage that we are at (mrproper, config, build) cwd: Directory where make should be run args: Arguments to pass to make kwargs: Arguments to pass to command.RunPipe() """ - cmd = ['make'] + list(args) + cmd = [self.gnu_make] + list(args) result = command.RunPipe([cmd], capture=True, capture_stderr=True, cwd=cwd, raise_on_error=False, **kwargs) return result @@ -675,7 +341,8 @@ class Builder: """Process the result of a build, showing progress information Args: - result: A CommandResult object + result: A CommandResult object, which indicates the result for + a single build """ col = terminal.Color() if result: @@ -693,6 +360,13 @@ class Builder: self.warned += 1 if result.already_done: self.already_done += 1 + if self._verbose: + Print('\r', newline=False) + self.ClearLine(0) + boards_selected = {target : result.brd} + self.ResetResultSummary(boards_selected) + self.ProduceResultSummary(result.commit_upto, self.commits, + boards_selected) else: target = '(starting)' @@ -715,8 +389,8 @@ class Builder: self.commit_count) name += target - print line + name, - length = 13 + len(name) + Print(line + name, newline=False) + length = 14 + len(name) self.ClearLine(length) def _GetOutputDir(self, commit_upto): @@ -727,12 +401,17 @@ class Builder: Args: commit_upto: Commit number to use (0..self.count-1) """ - commit = self.commits[commit_upto] - subject = commit.subject.translate(trans_valid_chars) - commit_dir = ('%02d_of_%02d_g%s_%s' % (commit_upto + 1, - self.commit_count, commit.hash, subject[:20])) - output_dir = os.path.join(self.base_dir, commit_dir) - return output_dir + commit_dir = None + if self.commits: + commit = self.commits[commit_upto] + subject = commit.subject.translate(trans_valid_chars) + commit_dir = ('%02d_of_%02d_g%s_%s' % (commit_upto + 1, + self.commit_count, commit.hash, subject[:20])) + elif not self.no_subdirs: + commit_dir = 'current' + if not commit_dir: + return self.base_dir + return os.path.join(self.base_dir, commit_dir) def GetBuildDir(self, commit_upto, target): """Get the name of the build directory for a commit number @@ -828,7 +507,7 @@ class Builder: try: size, type, name = line[:-1].split() except: - print "Invalid line in file '%s': '%s'" % (fname, line[:-1]) + Print("Invalid line in file '%s': '%s'" % (fname, line[:-1])) continue if type in 'tTdDbB': # function names begin with '.' on 64-bit powerpc @@ -911,19 +590,57 @@ class Builder: Tuple: Dict containing boards which passed building this commit. keyed by board.target - List containing a summary of error/warning lines + List containing a summary of error lines + Dict keyed by error line, containing a list of the Board + objects with that error + List containing a summary of warning lines + Dict keyed by error line, containing a list of the Board + objects with that warning """ + def AddLine(lines_summary, lines_boards, line, board): + line = line.rstrip() + if line in lines_boards: + lines_boards[line].append(board) + else: + lines_boards[line] = [board] + lines_summary.append(line) + board_dict = {} err_lines_summary = [] + err_lines_boards = {} + warn_lines_summary = [] + warn_lines_boards = {} for board in boards_selected.itervalues(): outcome = self.GetBuildOutcome(commit_upto, board.target, read_func_sizes) board_dict[board.target] = outcome - for err in outcome.err_lines: - if err and not err.rstrip() in err_lines_summary: - err_lines_summary.append(err.rstrip()) - return board_dict, err_lines_summary + last_func = None + last_was_warning = False + for line in outcome.err_lines: + if line: + if (self._re_function.match(line) or + self._re_files.match(line)): + last_func = line + else: + is_warning = self._re_warning.match(line) + is_note = self._re_note.match(line) + if is_warning or (last_was_warning and is_note): + if last_func: + AddLine(warn_lines_summary, warn_lines_boards, + last_func, board) + AddLine(warn_lines_summary, warn_lines_boards, + line, board) + else: + if last_func: + AddLine(err_lines_summary, err_lines_boards, + last_func, board) + AddLine(err_lines_summary, err_lines_boards, + line, board) + last_was_warning = is_warning + last_func = None + return (board_dict, err_lines_summary, err_lines_boards, + warn_lines_summary, warn_lines_boards) def AddOutcome(self, board_dict, arch_list, changes, char, color): """Add an output to our list of outcomes for each architecture @@ -978,6 +695,9 @@ class Builder: for board in board_selected: self._base_board_dict[board] = Builder.Outcome(0, [], [], {}) self._base_err_lines = [] + self._base_warn_lines = [] + self._base_err_line_boards = {} + self._base_warn_line_boards = {} def PrintFuncSizeDetail(self, fname, old, new): grow, shrink, add, remove, up, down = 0, 0, 0, 0, 0, 0 @@ -1015,16 +735,16 @@ class Builder: return args = [self.ColourNum(x) for x in args] indent = ' ' * 15 - print ('%s%s: add: %s/%s, grow: %s/%s bytes: %s/%s (%s)' % - tuple([indent, self.col.Color(self.col.YELLOW, fname)] + args)) - print '%s %-38s %7s %7s %+7s' % (indent, 'function', 'old', 'new', - 'delta') + Print('%s%s: add: %s/%s, grow: %s/%s bytes: %s/%s (%s)' % + tuple([indent, self.col.Color(self.col.YELLOW, fname)] + args)) + Print('%s %-38s %7s %7s %+7s' % (indent, 'function', 'old', 'new', + 'delta')) for diff, name in delta: if diff: color = self.col.RED if diff > 0 else self.col.GREEN msg = '%s %-38s %7s %7s %+7d' % (indent, name, old.get(name, '-'), new.get(name,'-'), diff) - print self.col.Color(color, msg) + Print(msg, colour=color) def PrintSizeDetail(self, target_list, show_bloat): @@ -1049,11 +769,12 @@ class Builder: color = self.col.RED if diff > 0 else self.col.GREEN msg = ' %s %+d' % (name, diff) if not printed_target: - print '%10s %-15s:' % ('', result['_target']), + Print('%10s %-15s:' % ('', result['_target']), + newline=False) printed_target = True - print self.col.Color(color, msg), + Print(msg, colour=color, newline=False) if printed_target: - print + Print() if show_bloat: target = result['_target'] outcome = result['_outcome'] @@ -1158,18 +879,19 @@ class Builder: color = self.col.RED if avg_diff > 0 else self.col.GREEN msg = ' %s %+1.1f' % (name, avg_diff) if not printed_arch: - print '%10s: (for %d/%d boards)' % (arch, count, - arch_count[arch]), + Print('%10s: (for %d/%d boards)' % (arch, count, + arch_count[arch]), newline=False) printed_arch = True - print self.col.Color(color, msg), + Print(msg, colour=color, newline=False) if printed_arch: - print + Print() if show_detail: self.PrintSizeDetail(target_list, show_bloat) def PrintResultSummary(self, board_selected, board_dict, err_lines, + err_line_boards, warn_lines, warn_line_boards, show_sizes, show_detail, show_bloat): """Compare results with the base results and display delta. @@ -1185,10 +907,49 @@ class Builder: commit, keyed by board.target. The value is an Outcome object. err_lines: A list of errors for this commit, or [] if there is none, or we don't want to print errors + err_line_boards: Dict keyed by error line, containing a list of + the Board objects with that error + warn_lines: A list of warnings for this commit, or [] if there is + none, or we don't want to print errors + warn_line_boards: Dict keyed by warning line, containing a list of + the Board objects with that warning show_sizes: Show image size deltas show_detail: Show detail for each board show_bloat: Show detail for each function """ + def _BoardList(line, line_boards): + """Helper function to get a line of boards containing a line + + Args: + line: Error line to search for + Return: + String containing a list of boards with that error line, or + '' if the user has not requested such a list + """ + if self._list_error_boards: + names = [] + for board in line_boards[line]: + if not board.target in names: + names.append(board.target) + names_str = '(%s) ' % ','.join(names) + else: + names_str = '' + return names_str + + def _CalcErrorDelta(base_lines, base_line_boards, lines, line_boards, + char): + better_lines = [] + worse_lines = [] + for line in lines: + if line not in base_lines: + worse_lines.append(char + '+' + + _BoardList(line, line_boards) + line) + for line in base_lines: + if line not in lines: + better_lines.append(char + '-' + + _BoardList(line, base_line_boards) + line) + return better_lines, worse_lines + better = [] # List of boards fixed since last commit worse = [] # List of new broken boards since last commit new = [] # List of boards that didn't exist last time @@ -1212,17 +973,14 @@ class Builder: new.append(target) # Get a list of errors that have appeared, and disappeared - better_err = [] - worse_err = [] - for line in err_lines: - if line not in self._base_err_lines: - worse_err.append('+' + line) - for line in self._base_err_lines: - if line not in err_lines: - better_err.append('-' + line) + better_err, worse_err = _CalcErrorDelta(self._base_err_lines, + self._base_err_line_boards, err_lines, err_line_boards, '') + better_warn, worse_warn = _CalcErrorDelta(self._base_warn_lines, + self._base_warn_line_boards, warn_lines, warn_line_boards, 'w') # Display results by arch - if better or worse or unknown or new or worse_err or better_err: + if (better or worse or unknown or new or worse_err or better_err + or worse_warn or better_warn): arch_list = {} self.AddOutcome(board_selected, arch_list, better, '', self.col.GREEN) @@ -1233,11 +991,20 @@ class Builder: self.AddOutcome(board_selected, arch_list, unknown, '?', self.col.MAGENTA) for arch, target_list in arch_list.iteritems(): - print '%10s: %s' % (arch, target_list) + Print('%10s: %s' % (arch, target_list)) + self._error_lines += 1 if better_err: - print self.col.Color(self.col.GREEN, '\n'.join(better_err)) + Print('\n'.join(better_err), colour=self.col.GREEN) + self._error_lines += 1 if worse_err: - print self.col.Color(self.col.RED, '\n'.join(worse_err)) + Print('\n'.join(worse_err), colour=self.col.RED) + self._error_lines += 1 + if better_warn: + Print('\n'.join(better_warn), colour=self.col.CYAN) + self._error_lines += 1 + if worse_warn: + Print('\n'.join(worse_warn), colour=self.col.MAGENTA) + self._error_lines += 1 if show_sizes: self.PrintSizeSummary(board_selected, board_dict, show_detail, @@ -1246,6 +1013,9 @@ class Builder: # Save our updated information for the next call to this function self._base_board_dict = board_dict self._base_err_lines = err_lines + self._base_warn_lines = warn_lines + self._base_err_line_boards = err_line_boards + self._base_warn_line_boards = warn_line_boards # Get a list of boards that did not get built, if needed not_built = [] @@ -1253,12 +1023,24 @@ class Builder: if not board in board_dict: not_built.append(board) if not_built: - print "Boards not built (%d): %s" % (len(not_built), - ', '.join(not_built)) - + Print("Boards not built (%d): %s" % (len(not_built), + ', '.join(not_built))) + + def ProduceResultSummary(self, commit_upto, commits, board_selected): + (board_dict, err_lines, err_line_boards, warn_lines, + warn_line_boards) = self.GetResultSummary( + board_selected, commit_upto, + read_func_sizes=self._show_bloat) + if commits: + msg = '%02d: %s' % (commit_upto + 1, + commits[commit_upto].subject) + Print(msg, colour=self.col.BLUE) + self.PrintResultSummary(board_selected, board_dict, + err_lines if self._show_errors else [], err_line_boards, + warn_lines if self._show_errors else [], warn_line_boards, + self._show_sizes, self._show_detail, self._show_bloat) - def ShowSummary(self, commits, board_selected, show_errors, show_sizes, - show_detail, show_bloat): + def ShowSummary(self, commits, board_selected): """Show a build summary for U-Boot for a given board list. Reset the result summary, then repeatedly call GetResultSummary on @@ -1267,23 +1049,16 @@ class Builder: Args: commit: Commit objects to summarise board_selected: Dict containing boards to summarise - show_errors: Show errors that occured - show_sizes: Show size deltas - show_detail: Show detail for each board - show_bloat: Show detail for each function """ - self.commit_count = len(commits) + self.commit_count = len(commits) if commits else 1 self.commits = commits self.ResetResultSummary(board_selected) + self._error_lines = 0 for commit_upto in range(0, self.commit_count, self._step): - board_dict, err_lines = self.GetResultSummary(board_selected, - commit_upto, read_func_sizes=show_bloat) - msg = '%02d: %s' % (commit_upto + 1, commits[commit_upto].subject) - print self.col.Color(self.col.BLUE, msg) - self.PrintResultSummary(board_selected, board_dict, - err_lines if show_errors else [], show_sizes, show_detail, - show_bloat) + self.ProduceResultSummary(commit_upto, commits, board_selected) + if not self._error_lines: + Print('(no errors to report)', colour=self.col.GREEN) def SetupBuild(self, board_selected, commits): @@ -1294,45 +1069,11 @@ class Builder: commits: Selected commits to build """ # First work out how many commits we will build - count = (len(commits) + self._step - 1) / self._step + count = (self.commit_count + self._step - 1) / self._step self.count = len(board_selected) * count self.upto = self.warned = self.fail = 0 self._timestamps = collections.deque() - def BuildBoardsForCommit(self, board_selected, keep_outputs): - """Build all boards for a single commit""" - self.SetupBuild(board_selected) - self.count = len(board_selected) - for brd in board_selected.itervalues(): - job = BuilderJob() - job.board = brd - job.commits = None - job.keep_outputs = keep_outputs - self.queue.put(brd) - - self.queue.join() - self.out_queue.join() - print - self.ClearLine(0) - - def BuildCommits(self, commits, board_selected, show_errors, keep_outputs): - """Build all boards for all commits (non-incremental)""" - self.commit_count = len(commits) - - self.ResetResultSummary(board_selected) - for self.commit_upto in range(self.commit_count): - self.SelectCommit(commits[self.commit_upto]) - self.SelectOutputDir() - Mkdir(self.output_dir) - - self.BuildBoardsForCommit(board_selected, keep_outputs) - board_dict, err_lines = self.GetResultSummary() - self.PrintResultSummary(board_selected, board_dict, - err_lines if show_errors else []) - - if self.already_done: - print '%d builds already done' % self.already_done - def GetThreadDir(self, thread_num): """Get the directory path to the working dir for a thread. @@ -1341,40 +1082,42 @@ class Builder: """ return os.path.join(self._working_dir, '%02d' % thread_num) - def _PrepareThread(self, thread_num): + def _PrepareThread(self, thread_num, setup_git): """Prepare the working directory for a thread. This clones or fetches the repo into the thread's work directory. Args: thread_num: Thread number (0, 1, ...) + setup_git: True to set up a git repo clone """ thread_dir = self.GetThreadDir(thread_num) - Mkdir(thread_dir) + builderthread.Mkdir(thread_dir) git_dir = os.path.join(thread_dir, '.git') # Clone the repo if it doesn't already exist # TODO(sjg@chromium): Perhaps some git hackery to symlink instead, so # we have a private index but uses the origin repo's contents? - if self.git_dir: + if setup_git and self.git_dir: src_dir = os.path.abspath(self.git_dir) if os.path.exists(git_dir): gitutil.Fetch(git_dir, thread_dir) else: - print 'Cloning repo for thread %d' % thread_num + Print('Cloning repo for thread %d' % thread_num) gitutil.Clone(src_dir, thread_dir) - def _PrepareWorkingSpace(self, max_threads): + def _PrepareWorkingSpace(self, max_threads, setup_git): """Prepare the working directory for use. Set up the git repo for each thread. Args: max_threads: Maximum number of threads we expect to need. + setup_git: True to set up a git repo clone """ - Mkdir(self._working_dir) + builderthread.Mkdir(self._working_dir) for thread in range(max_threads): - self._PrepareThread(thread) + self._PrepareThread(thread, setup_git) def _PrepareOutputSpace(self): """Get the output directories ready to receive files. @@ -1383,6 +1126,8 @@ class Builder: create. Having left over directories is confusing when the user wants to check the output manually. """ + if not self.commits: + return dir_list = [] for commit_upto in range(self.commit_count): dir_list.append(self._GetOutputDir(commit_upto)) @@ -1391,29 +1136,35 @@ class Builder: if dirname not in dir_list: shutil.rmtree(dirname) - def BuildBoards(self, commits, board_selected, show_errors, keep_outputs): + def BuildBoards(self, commits, board_selected, keep_outputs, verbose): """Build all commits for a list of boards Args: commits: List of commits to be build, each a Commit object boards_selected: Dict of selected boards, key is target name, value is Board object - show_errors: True to show summarised error/warning info keep_outputs: True to save build output files + verbose: Display build results as they are completed + Returns: + Tuple containing: + - number of boards that failed to build + - number of boards that issued warnings """ - self.commit_count = len(commits) + self.commit_count = len(commits) if commits else 1 self.commits = commits + self._verbose = verbose self.ResetResultSummary(board_selected) - Mkdir(self.base_dir) - self._PrepareWorkingSpace(min(self.num_threads, len(board_selected))) + builderthread.Mkdir(self.base_dir, parents = True) + self._PrepareWorkingSpace(min(self.num_threads, len(board_selected)), + commits is not None) self._PrepareOutputSpace() self.SetupBuild(board_selected, commits) self.ProcessResult(None) # Create jobs to build all commits for each board for brd in board_selected.itervalues(): - job = BuilderJob() + job = builderthread.BuilderJob() job.board = brd job.commits = commits job.keep_outputs = keep_outputs @@ -1425,5 +1176,6 @@ class Builder: # Wait until we have processed all output self.out_queue.join() - print + Print() self.ClearLine(0) + return (self.fail, self.warned) diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py new file mode 100644 index 0000000000..efb62f16d7 --- /dev/null +++ b/tools/buildman/builderthread.py @@ -0,0 +1,441 @@ +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +import errno +import glob +import os +import shutil +import threading + +import command +import gitutil + +def Mkdir(dirname, parents = False): + """Make a directory if it doesn't already exist. + + Args: + dirname: Directory to create + """ + try: + if parents: + os.makedirs(dirname) + else: + os.mkdir(dirname) + except OSError as err: + if err.errno == errno.EEXIST: + pass + else: + raise + +class BuilderJob: + """Holds information about a job to be performed by a thread + + Members: + board: Board object to build + commits: List of commit options to build. + """ + def __init__(self): + self.board = None + self.commits = [] + + +class ResultThread(threading.Thread): + """This thread processes results from builder threads. + + It simply passes the results on to the builder. There is only one + result thread, and this helps to serialise the build output. + """ + def __init__(self, builder): + """Set up a new result thread + + Args: + builder: Builder which will be sent each result + """ + threading.Thread.__init__(self) + self.builder = builder + + def run(self): + """Called to start up the result thread. + + We collect the next result job and pass it on to the build. + """ + while True: + result = self.builder.out_queue.get() + self.builder.ProcessResult(result) + self.builder.out_queue.task_done() + + +class BuilderThread(threading.Thread): + """This thread builds U-Boot for a particular board. + + An input queue provides each new job. We run 'make' to build U-Boot + and then pass the results on to the output queue. + + Members: + builder: The builder which contains information we might need + thread_num: Our thread number (0-n-1), used to decide on a + temporary directory + """ + def __init__(self, builder, thread_num): + """Set up a new builder thread""" + threading.Thread.__init__(self) + self.builder = builder + self.thread_num = thread_num + + def Make(self, commit, brd, stage, cwd, *args, **kwargs): + """Run 'make' on a particular commit and board. + + The source code will already be checked out, so the 'commit' + argument is only for information. + + Args: + commit: Commit object that is being built + brd: Board object that is being built + stage: Stage of the build. Valid stages are: + mrproper - can be called to clean source + config - called to configure for a board + build - the main make invocation - it does the build + args: A list of arguments to pass to 'make' + kwargs: A list of keyword arguments to pass to command.RunPipe() + + Returns: + CommandResult object + """ + return self.builder.do_make(commit, brd, stage, cwd, *args, + **kwargs) + + def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build, + force_build_failures): + """Build a particular commit. + + If the build is already done, and we are not forcing a build, we skip + the build and just return the previously-saved results. + + Args: + commit_upto: Commit number to build (0...n-1) + brd: Board object to build + work_dir: Directory to which the source will be checked out + do_config: True to run a make _defconfig on the source + force_build: Force a build even if one was previously done + force_build_failures: Force a bulid if the previous result showed + failure + + Returns: + tuple containing: + - CommandResult object containing the results of the build + - boolean indicating whether 'make config' is still needed + """ + # Create a default result - it will be overwritte by the call to + # self.Make() below, in the event that we do a build. + result = command.CommandResult() + result.return_code = 0 + if self.builder.in_tree: + out_dir = work_dir + else: + out_dir = os.path.join(work_dir, 'build') + + # Check if the job was already completed last time + done_file = self.builder.GetDoneFile(commit_upto, brd.target) + result.already_done = os.path.exists(done_file) + will_build = (force_build or force_build_failures or + not result.already_done) + if result.already_done: + # Get the return code from that build and use it + with open(done_file, 'r') as fd: + result.return_code = int(fd.readline()) + if will_build: + err_file = self.builder.GetErrFile(commit_upto, brd.target) + if os.path.exists(err_file) and os.stat(err_file).st_size: + result.stderr = 'bad' + elif not force_build: + # The build passed, so no need to build it again + will_build = False + + if will_build: + # We are going to have to build it. First, get a toolchain + if not self.toolchain: + try: + self.toolchain = self.builder.toolchains.Select(brd.arch) + except ValueError as err: + result.return_code = 10 + result.stdout = '' + result.stderr = str(err) + # TODO(sjg@chromium.org): This gets swallowed, but needs + # to be reported. + + if self.toolchain: + # Checkout the right commit + if self.builder.commits: + commit = self.builder.commits[commit_upto] + if self.builder.checkout: + git_dir = os.path.join(work_dir, '.git') + gitutil.Checkout(commit.hash, git_dir, work_dir, + force=True) + else: + commit = 'current' + + # Set up the environment and command line + env = self.toolchain.MakeEnvironment(self.builder.full_path) + Mkdir(out_dir) + args = [] + cwd = work_dir + src_dir = os.path.realpath(work_dir) + if not self.builder.in_tree: + if commit_upto is None: + # In this case we are building in the original source + # directory (i.e. the current directory where buildman + # is invoked. The output directory is set to this + # thread's selected work directory. + # + # Symlinks can confuse U-Boot's Makefile since + # we may use '..' in our path, so remove them. + work_dir = os.path.realpath(work_dir) + args.append('O=%s/build' % work_dir) + cwd = None + src_dir = os.getcwd() + else: + args.append('O=build') + if not self.builder.verbose_build: + args.append('-s') + if self.builder.num_jobs is not None: + args.extend(['-j', str(self.builder.num_jobs)]) + config_args = ['%s_defconfig' % brd.target] + config_out = '' + args.extend(self.builder.toolchains.GetMakeArguments(brd)) + + # If we need to reconfigure, do that now + if do_config: + result = self.Make(commit, brd, 'mrproper', cwd, + 'mrproper', *args, env=env) + result = self.Make(commit, brd, 'config', cwd, + *(args + config_args), env=env) + config_out = result.combined + do_config = False # No need to configure next time + if result.return_code == 0: + result = self.Make(commit, brd, 'build', cwd, *args, + env=env) + result.stderr = result.stderr.replace(src_dir + '/', '') + else: + result.return_code = 1 + result.stderr = 'No tool chain for %s\n' % brd.arch + result.already_done = False + + result.toolchain = self.toolchain + result.brd = brd + result.commit_upto = commit_upto + result.out_dir = out_dir + return result, do_config + + def _WriteResult(self, result, keep_outputs): + """Write a built result to the output directory. + + Args: + result: CommandResult object containing result to write + keep_outputs: True to store the output binaries, False + to delete them + """ + # Fatal error + if result.return_code < 0: + return + + # Aborted? + if result.stderr and 'No child processes' in result.stderr: + return + + if result.already_done: + return + + # Write the output and stderr + output_dir = self.builder._GetOutputDir(result.commit_upto) + Mkdir(output_dir) + build_dir = self.builder.GetBuildDir(result.commit_upto, + result.brd.target) + Mkdir(build_dir) + + outfile = os.path.join(build_dir, 'log') + with open(outfile, 'w') as fd: + if result.stdout: + fd.write(result.stdout) + + errfile = self.builder.GetErrFile(result.commit_upto, + result.brd.target) + if result.stderr: + with open(errfile, 'w') as fd: + fd.write(result.stderr) + elif os.path.exists(errfile): + os.remove(errfile) + + if result.toolchain: + # Write the build result and toolchain information. + done_file = self.builder.GetDoneFile(result.commit_upto, + result.brd.target) + with open(done_file, 'w') as fd: + fd.write('%s' % result.return_code) + with open(os.path.join(build_dir, 'toolchain'), 'w') as fd: + print >>fd, 'gcc', result.toolchain.gcc + print >>fd, 'path', result.toolchain.path + print >>fd, 'cross', result.toolchain.cross + print >>fd, 'arch', result.toolchain.arch + fd.write('%s' % result.return_code) + + with open(os.path.join(build_dir, 'toolchain'), 'w') as fd: + print >>fd, 'gcc', result.toolchain.gcc + print >>fd, 'path', result.toolchain.path + + # Write out the image and function size information and an objdump + env = result.toolchain.MakeEnvironment(self.builder.full_path) + lines = [] + for fname in ['u-boot', 'spl/u-boot-spl']: + cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname] + nm_result = command.RunPipe([cmd], capture=True, + capture_stderr=True, cwd=result.out_dir, + raise_on_error=False, env=env) + if nm_result.stdout: + nm = self.builder.GetFuncSizesFile(result.commit_upto, + result.brd.target, fname) + with open(nm, 'w') as fd: + print >>fd, nm_result.stdout, + + cmd = ['%sobjdump' % self.toolchain.cross, '-h', fname] + dump_result = command.RunPipe([cmd], capture=True, + capture_stderr=True, cwd=result.out_dir, + raise_on_error=False, env=env) + rodata_size = '' + if dump_result.stdout: + objdump = self.builder.GetObjdumpFile(result.commit_upto, + result.brd.target, fname) + with open(objdump, 'w') as fd: + print >>fd, dump_result.stdout, + for line in dump_result.stdout.splitlines(): + fields = line.split() + if len(fields) > 5 and fields[1] == '.rodata': + rodata_size = fields[2] + + cmd = ['%ssize' % self.toolchain.cross, fname] + size_result = command.RunPipe([cmd], capture=True, + capture_stderr=True, cwd=result.out_dir, + raise_on_error=False, env=env) + if size_result.stdout: + lines.append(size_result.stdout.splitlines()[1] + ' ' + + rodata_size) + + # Write out the image sizes file. This is similar to the output + # of binutil's 'size' utility, but it omits the header line and + # adds an additional hex value at the end of each line for the + # rodata size + if len(lines): + sizes = self.builder.GetSizesFile(result.commit_upto, + result.brd.target) + with open(sizes, 'w') as fd: + print >>fd, '\n'.join(lines) + + # Now write the actual build output + if keep_outputs: + patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', '*.img', + 'include/autoconf.mk', 'spl/u-boot-spl', + 'spl/u-boot-spl.bin'] + for pattern in patterns: + file_list = glob.glob(os.path.join(result.out_dir, pattern)) + for fname in file_list: + shutil.copy(fname, build_dir) + + + def RunJob(self, job): + """Run a single job + + A job consists of a building a list of commits for a particular board. + + Args: + job: Job to build + """ + brd = job.board + work_dir = self.builder.GetThreadDir(self.thread_num) + self.toolchain = None + if job.commits: + # Run 'make board_defconfig' on the first commit + do_config = True + commit_upto = 0 + force_build = False + for commit_upto in range(0, len(job.commits), job.step): + result, request_config = self.RunCommit(commit_upto, brd, + work_dir, do_config, + force_build or self.builder.force_build, + self.builder.force_build_failures) + failed = result.return_code or result.stderr + did_config = do_config + if failed and not do_config: + # If our incremental build failed, try building again + # with a reconfig. + if self.builder.force_config_on_failure: + result, request_config = self.RunCommit(commit_upto, + brd, work_dir, True, True, False) + did_config = True + if not self.builder.force_reconfig: + do_config = request_config + + # If we built that commit, then config is done. But if we got + # an warning, reconfig next time to force it to build the same + # files that created warnings this time. Otherwise an + # incremental build may not build the same file, and we will + # think that the warning has gone away. + # We could avoid this by using -Werror everywhere... + # For errors, the problem doesn't happen, since presumably + # the build stopped and didn't generate output, so will retry + # that file next time. So we could detect warnings and deal + # with them specially here. For now, we just reconfigure if + # anything goes work. + # Of course this is substantially slower if there are build + # errors/warnings (e.g. 2-3x slower even if only 10% of builds + # have problems). + if (failed and not result.already_done and not did_config and + self.builder.force_config_on_failure): + # If this build failed, try the next one with a + # reconfigure. + # Sometimes if the board_config.h file changes it can mess + # with dependencies, and we get: + # make: *** No rule to make target `include/autoconf.mk', + # needed by `depend'. + do_config = True + force_build = True + else: + force_build = False + if self.builder.force_config_on_failure: + if failed: + do_config = True + result.commit_upto = commit_upto + if result.return_code < 0: + raise ValueError('Interrupt') + + # We have the build results, so output the result + self._WriteResult(result, job.keep_outputs) + self.builder.out_queue.put(result) + else: + # Just build the currently checked-out build + result, request_config = self.RunCommit(None, brd, work_dir, True, + True, self.builder.force_build_failures) + result.commit_upto = 0 + self._WriteResult(result, job.keep_outputs) + self.builder.out_queue.put(result) + + def run(self): + """Our thread's run function + + This thread picks a job from the queue, runs it, and then goes to the + next job. + """ + alive = True + while True: + job = self.builder.queue.get() + if self.builder.active and alive: + self.RunJob(job) + ''' + try: + if self.builder.active and alive: + self.RunJob(job) + except Exception as err: + alive = False + print err + ''' + self.builder.queue.task_done() diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py index 6fba2f292a..d0afeda6c0 100755 --- a/tools/buildman/buildman.py +++ b/tools/buildman/buildman.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python # # Copyright (c) 2012 The Chromium OS Authors. # @@ -8,7 +8,6 @@ """See README for more information""" import multiprocessing -from optparse import OptionParser import os import re import sys @@ -20,9 +19,10 @@ sys.path.append(os.path.join(our_path, '../patman')) # Our modules import board +import bsettings import builder import checkpatch -import command +import cmdline import control import doctest import gitutil @@ -31,14 +31,20 @@ import terminal import toolchain def RunTests(): + import func_test import test + import doctest - sys.argv = [sys.argv[0]] - suite = unittest.TestLoader().loadTestsFromTestCase(test.TestBuild) result = unittest.TestResult() - suite.run(result) + for module in ['toolchain', 'gitutil']: + suite = doctest.DocTestSuite(module) + suite.run(result) + + sys.argv = [sys.argv[0]] + for module in (test.TestBuild, func_test.TestFunctional): + suite = unittest.TestLoader().loadTestsFromTestCase(module) + suite.run(result) - # TODO: Surely we can just 'print' result? print result for test, err in result.errors: print err @@ -46,65 +52,14 @@ def RunTests(): print err -parser = OptionParser() -parser.add_option('-b', '--branch', type='string', - help='Branch name to build') -parser.add_option('-B', '--bloat', dest='show_bloat', - action='store_true', default=False, - help='Show changes in function code size for each board') -parser.add_option('-c', '--count', dest='count', type='int', - default=-1, help='Run build on the top n commits') -parser.add_option('-e', '--show_errors', action='store_true', - default=False, help='Show errors and warnings') -parser.add_option('-f', '--force-build', dest='force_build', - action='store_true', default=False, - help='Force build of boards even if already built') -parser.add_option('-d', '--detail', dest='show_detail', - action='store_true', default=False, - help='Show detailed information for each board in summary') -parser.add_option('-g', '--git', type='string', - help='Git repo containing branch to build', default='.') -parser.add_option('-H', '--full-help', action='store_true', dest='full_help', - default=False, help='Display the README file') -parser.add_option('-j', '--jobs', dest='jobs', type='int', - default=None, help='Number of jobs to run at once (passed to make)') -parser.add_option('-k', '--keep-outputs', action='store_true', - default=False, help='Keep all build output files (e.g. binaries)') -parser.add_option('--list-tool-chains', action='store_true', default=False, - help='List available tool chains') -parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run', - default=False, help="Do a try run (describe actions, but no nothing)") -parser.add_option('-Q', '--quick', action='store_true', - default=False, help='Do a rough build, with limited warning resolution') -parser.add_option('-s', '--summary', action='store_true', - default=False, help='Show a build summary') -parser.add_option('-S', '--show-sizes', action='store_true', - default=False, help='Show image size variation in summary') -parser.add_option('--step', type='int', - default=1, help='Only build every n commits (0=just first and last)') -parser.add_option('-t', '--test', action='store_true', dest='test', - default=False, help='run tests') -parser.add_option('-T', '--threads', type='int', - default=None, help='Number of builder threads to use') -parser.add_option('-u', '--show_unknown', action='store_true', - default=False, help='Show boards with unknown build result') - -parser.usage = """buildman -b [options] - -Build U-Boot for all commits in a branch. Use -n to do a dry run""" - -(options, args) = parser.parse_args() +options, args = cmdline.ParseArgs() # Run our meagre tests if options.test: RunTests() -elif options.full_help: - pager = os.getenv('PAGER') - if not pager: - pager = 'more' - fname = os.path.join(os.path.dirname(sys.argv[0]), 'README') - command.Run(pager, fname) # Build selected commits for selected boards else: - control.DoBuildman(options, args) + bsettings.Setup(options.config_file) + ret_code = control.DoBuildman(options, args) + sys.exit(ret_code) diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py new file mode 100644 index 0000000000..e8a6dadd1c --- /dev/null +++ b/tools/buildman/cmdline.py @@ -0,0 +1,95 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +from optparse import OptionParser + +def ParseArgs(): + """Parse command line arguments from sys.argv[] + + Returns: + tuple containing: + options: command line options + args: command lin arguments + """ + parser = OptionParser() + parser.add_option('-b', '--branch', type='string', + help='Branch name to build') + parser.add_option('-B', '--bloat', dest='show_bloat', + action='store_true', default=False, + help='Show changes in function code size for each board') + parser.add_option('-c', '--count', dest='count', type='int', + default=-1, help='Run build on the top n commits') + parser.add_option('-C', '--force-reconfig', dest='force_reconfig', + action='store_true', default=False, + help='Reconfigure for every commit (disable incremental build)') + parser.add_option('-d', '--detail', dest='show_detail', + action='store_true', default=False, + help='Show detailed information for each board in summary') + parser.add_option('-e', '--show_errors', action='store_true', + default=False, help='Show errors and warnings') + parser.add_option('-f', '--force-build', dest='force_build', + action='store_true', default=False, + help='Force build of boards even if already built') + parser.add_option('-F', '--force-build-failures', dest='force_build_failures', + action='store_true', default=False, + help='Force build of previously-failed build') + parser.add_option('--fetch-arch', type='string', + help="Fetch a toolchain for architecture FETCH_ARCH ('list' to list)." + ' You can also fetch several toolchains separate by comma, or' + " 'all' to download all") + parser.add_option('-g', '--git', type='string', + help='Git repo containing branch to build', default='.') + parser.add_option('-G', '--config-file', type='string', + help='Path to buildman config file', default='') + parser.add_option('-H', '--full-help', action='store_true', dest='full_help', + default=False, help='Display the README file') + parser.add_option('-i', '--in-tree', dest='in_tree', + action='store_true', default=False, + help='Build in the source tree instead of a separate directory') + parser.add_option('-j', '--jobs', dest='jobs', type='int', + default=None, help='Number of jobs to run at once (passed to make)') + parser.add_option('-k', '--keep-outputs', action='store_true', + default=False, help='Keep all build output files (e.g. binaries)') + parser.add_option('-l', '--list-error-boards', action='store_true', + default=False, help='Show a list of boards next to each error/warning') + parser.add_option('--list-tool-chains', action='store_true', default=False, + help='List available tool chains') + parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run', + default=False, help="Do a dry run (describe actions, but do nothing)") + parser.add_option('-N', '--no-subdirs', action='store_true', dest='no_subdirs', + default=False, help="Don't create subdirectories when building current source for a single board") + parser.add_option('-o', '--output-dir', type='string', + dest='output_dir', default='..', + help='Directory where all builds happen and buildman has its workspace (default is ../)') + parser.add_option('-Q', '--quick', action='store_true', + default=False, help='Do a rough build, with limited warning resolution') + parser.add_option('-p', '--full-path', action='store_true', + default=False, help="Use full toolchain path in CROSS_COMPILE") + parser.add_option('-s', '--summary', action='store_true', + default=False, help='Show a build summary') + parser.add_option('-S', '--show-sizes', action='store_true', + default=False, help='Show image size variation in summary') + parser.add_option('--step', type='int', + default=1, help='Only build every n commits (0=just first and last)') + parser.add_option('-t', '--test', action='store_true', dest='test', + default=False, help='run tests') + parser.add_option('-T', '--threads', type='int', + default=None, help='Number of builder threads to use') + parser.add_option('-u', '--show_unknown', action='store_true', + default=False, help='Show boards with unknown build result') + parser.add_option('-v', '--verbose', action='store_true', + default=False, help='Show build results while the build progresses') + parser.add_option('-V', '--verbose-build', action='store_true', + default=False, help='Run make with V=1, showing all output') + parser.add_option('-x', '--exclude', dest='exclude', + type='string', action='append', + help='Specify a list of boards to exclude, separated by comma') + + parser.usage += """ + + Build U-Boot for all commits in a branch. Use -n to do a dry run""" + + return parser.parse_args() diff --git a/tools/buildman/control.py b/tools/buildman/control.py index 8e6a08f78e..720b978b23 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -5,6 +5,7 @@ import multiprocessing import os +import shutil import sys import board @@ -13,21 +14,29 @@ from builder import Builder import gitutil import patchstream import terminal +from terminal import Print import toolchain +import command +import subprocess def GetPlural(count): """Returns a plural 's' if count is not 1""" return 's' if count != 1 else '' -def GetActionSummary(is_summary, count, selected, options): +def GetActionSummary(is_summary, commits, selected, options): """Return a string summarising the intended action. Returns: Summary string. """ - count = (count + options.step - 1) / options.step - str = '%s %d commit%s for %d boards' % ( - 'Summary of' if is_summary else 'Building', count, GetPlural(count), + if commits: + count = len(commits) + count = (count + options.step - 1) / options.step + commit_str = '%d commit%s' % (count, GetPlural(count)) + else: + commit_str = 'current source' + str = '%s %s for %d boards' % ( + 'Summary of' if is_summary else 'Building', commit_str, len(selected)) str += ' (%d thread%s, %d job%s per thread)' % (options.threads, GetPlural(options.threads), options.jobs, GetPlural(options.jobs)) @@ -51,13 +60,18 @@ def ShowActions(series, why_selected, boards_selected, builder, options): col = terminal.Color() print 'Dry run, so not doing much. But I would do this:' print - print GetActionSummary(False, len(series.commits), boards_selected, + if series: + commits = series.commits + else: + commits = None + print GetActionSummary(False, commits, boards_selected, options) print 'Build directory: %s' % builder.base_dir - for upto in range(0, len(series.commits), options.step): - commit = series.commits[upto] - print ' ', col.Color(col.YELLOW, commit.hash, bright=False), - print commit.subject + if commits: + for upto in range(0, len(series.commits), options.step): + commit = series.commits[upto] + print ' ', col.Color(col.YELLOW, commit.hash[:8], bright=False), + print commit.subject print for arg in why_selected: if arg != 'all': @@ -65,73 +79,144 @@ def ShowActions(series, why_selected, boards_selected, builder, options): print ('Total boards to build for each commit: %d\n' % why_selected['all']) -def DoBuildman(options, args): +def DoBuildman(options, args, toolchains=None, make_func=None, boards=None, + clean_dir=False): """The main control code for buildman Args: options: Command line options object args: Command line arguments (list of strings) + toolchains: Toolchains to use - this should be a Toolchains() + object. If None, then it will be created and scanned + make_func: Make function to use for the builder. This is called + to execute 'make'. If this is None, the normal function + will be used, which calls the 'make' tool with suitable + arguments. This setting is useful for tests. + board: Boards() object to use, containing a list of available + boards. If this is None it will be created and scanned. """ + global builder + + if options.full_help: + pager = os.getenv('PAGER') + if not pager: + pager = 'more' + fname = os.path.join(os.path.dirname(sys.argv[0]), 'README') + command.Run(pager, fname) + return 0 + gitutil.Setup() - bsettings.Setup() options.git_dir = os.path.join(options.git, '.git') - toolchains = toolchain.Toolchains() - toolchains.Scan(options.list_tool_chains) + if not toolchains: + toolchains = toolchain.Toolchains() + toolchains.GetSettings() + toolchains.Scan(options.list_tool_chains) if options.list_tool_chains: toolchains.List() print - return + return 0 + + if options.fetch_arch: + if options.fetch_arch == 'list': + sorted_list = toolchains.ListArchs() + print 'Available architectures: %s\n' % ' '.join(sorted_list) + return 0 + else: + fetch_arch = options.fetch_arch + if fetch_arch == 'all': + fetch_arch = ','.join(toolchains.ListArchs()) + print 'Downloading toolchains: %s\n' % fetch_arch + for arch in fetch_arch.split(','): + ret = toolchains.FetchAndInstall(arch) + if ret: + return ret + return 0 # Work out how many commits to build. We want to build everything on the # branch. We also build the upstream commit as a control so we can see # problems introduced by the first commit on the branch. col = terminal.Color() count = options.count + has_range = options.branch and '..' in options.branch if count == -1: if not options.branch: - str = 'Please use -b to specify a branch to build' - print col.Color(col.RED, str) - sys.exit(1) - count = gitutil.CountCommitsInBranch(options.git_dir, options.branch) - if count is None: - str = "Branch '%s' not found or has no upstream" % options.branch - print col.Color(col.RED, str) - sys.exit(1) - count += 1 # Build upstream commit also + count = 1 + else: + if has_range: + count, msg = gitutil.CountCommitsInRange(options.git_dir, + options.branch) + else: + count, msg = gitutil.CountCommitsInBranch(options.git_dir, + options.branch) + if count is None: + sys.exit(col.Color(col.RED, msg)) + elif count == 0: + sys.exit(col.Color(col.RED, "Range '%s' has no commits" % + options.branch)) + if msg: + print col.Color(col.YELLOW, msg) + count += 1 # Build upstream commit also if not count: str = ("No commits found to process in branch '%s': " "set branch's upstream or use -c flag" % options.branch) - print col.Color(col.RED, str) - sys.exit(1) + sys.exit(col.Color(col.RED, str)) # Work out what subset of the boards we are building - boards = board.Boards() - boards.ReadBoards(os.path.join(options.git, 'boards.cfg')) - why_selected = boards.SelectBoards(args) + if not boards: + board_file = os.path.join(options.git, 'boards.cfg') + status = subprocess.call([os.path.join(options.git, + 'tools/genboardscfg.py')]) + if status != 0: + sys.exit("Failed to generate boards.cfg") + + boards = board.Boards() + boards.ReadBoards(os.path.join(options.git, 'boards.cfg')) + + exclude = [] + if options.exclude: + for arg in options.exclude: + exclude += arg.split(',') + + why_selected = boards.SelectBoards(args, exclude) selected = boards.GetSelected() if not len(selected): - print col.Color(col.RED, 'No matching boards found') - sys.exit(1) + sys.exit(col.Color(col.RED, 'No matching boards found')) # Read the metadata from the commits. First look at the upstream commit, # then the ones in the branch. We would like to do something like # upstream/master~..branch but that isn't possible if upstream/master is # a merge commit (it will list all the commits that form part of the # merge) - range_expr = gitutil.GetRangeInBranch(options.git_dir, options.branch) - upstream_commit = gitutil.GetUpstream(options.git_dir, options.branch) - series = patchstream.GetMetaDataForList(upstream_commit, options.git_dir, - 1) # Conflicting tags are not a problem for buildman, since it does not use # them. For example, Series-version is not useful for buildman. On the # other hand conflicting tags will cause an error. So allow later tags - # to overwrite earlier ones. - series.allow_overwrite = True - series = patchstream.GetMetaDataForList(range_expr, options.git_dir, None, - series) + # to overwrite earlier ones by setting allow_overwrite=True + if options.branch: + if count == -1: + if has_range: + range_expr = options.branch + else: + range_expr = gitutil.GetRangeInBranch(options.git_dir, + options.branch) + upstream_commit = gitutil.GetUpstream(options.git_dir, + options.branch) + series = patchstream.GetMetaDataForList(upstream_commit, + options.git_dir, 1, series=None, allow_overwrite=True) + + series = patchstream.GetMetaDataForList(range_expr, + options.git_dir, None, series, allow_overwrite=True) + else: + # Honour the count + series = patchstream.GetMetaDataForList(options.branch, + options.git_dir, count, series=None, allow_overwrite=True) + else: + series = None + options.verbose = True + if not options.summary: + options.show_errors = True # By default we have one thread per CPU. But if there are not enough jobs # we can have fewer threads and use a high '-j' value for make. @@ -144,31 +229,67 @@ def DoBuildman(options, args): if not options.step: options.step = len(series.commits) - 1 - # Create a new builder with the selected options - output_dir = os.path.join('..', options.branch) + gnu_make = command.Output(os.path.join(options.git, + 'scripts/show-gnu-make')).rstrip() + if not gnu_make: + sys.exit('GNU Make not found') + + # Create a new builder with the selected options. + output_dir = options.output_dir + if options.branch: + dirname = options.branch.replace('/', '_') + # As a special case allow the board directory to be placed in the + # output directory itself rather than any subdirectory. + if not options.no_subdirs: + output_dir = os.path.join(options.output_dir, dirname) + if (clean_dir and output_dir != options.output_dir and + os.path.exists(output_dir)): + shutil.rmtree(output_dir) builder = Builder(toolchains, output_dir, options.git_dir, - options.threads, options.jobs, checkout=True, - show_unknown=options.show_unknown, step=options.step) + options.threads, options.jobs, gnu_make=gnu_make, checkout=True, + show_unknown=options.show_unknown, step=options.step, + no_subdirs=options.no_subdirs, full_path=options.full_path, + verbose_build=options.verbose_build) builder.force_config_on_failure = not options.quick + if make_func: + builder.do_make = make_func # For a dry run, just show our actions as a sanity check if options.dry_run: ShowActions(series, why_selected, selected, builder, options) else: builder.force_build = options.force_build + builder.force_build_failures = options.force_build_failures + builder.force_reconfig = options.force_reconfig + builder.in_tree = options.in_tree # Work out which boards to build board_selected = boards.GetSelectedDict() - print GetActionSummary(options.summary, count, board_selected, options) + if series: + commits = series.commits + # Number the commits for test purposes + for commit in range(len(commits)): + commits[commit].sequence = commit + else: + commits = None + + Print(GetActionSummary(options.summary, commits, board_selected, + options)) + # We can't show function sizes without board details at present + if options.show_bloat: + options.show_detail = True + builder.SetDisplayOptions(options.show_errors, options.show_sizes, + options.show_detail, options.show_bloat, + options.list_error_boards) if options.summary: - # We can't show function sizes without board details at present - if options.show_bloat: - options.show_detail = True - builder.ShowSummary(series.commits, board_selected, - options.show_errors, options.show_sizes, - options.show_detail, options.show_bloat) + builder.ShowSummary(commits, board_selected) else: - builder.BuildBoards(series.commits, board_selected, - options.show_errors, options.keep_outputs) + fail, warned = builder.BuildBoards(commits, board_selected, + options.keep_outputs, options.verbose) + if fail: + return 128 + elif warned: + return 129 + return 0 diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py new file mode 100644 index 0000000000..75eb3a97bb --- /dev/null +++ b/tools/buildman/func_test.py @@ -0,0 +1,519 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +import os +import shutil +import sys +import tempfile +import unittest + +import board +import bsettings +import cmdline +import command +import control +import gitutil +import terminal +import toolchain + +settings_data = ''' +# Buildman settings file + +[toolchain] + +[toolchain-alias] + +[make-flags] +src=/home/sjg/c/src +chroot=/home/sjg/c/chroot +vboot=USE_STDINT=1 VBOOT_DEBUG=1 MAKEFLAGS_VBOOT=DEBUG=1 CFLAGS_EXTRA_VBOOT=-DUNROLL_LOOPS VBOOT_SOURCE=${src}/platform/vboot_reference +chromeos_coreboot=VBOOT=${chroot}/build/link/usr ${vboot} +chromeos_daisy=VBOOT=${chroot}/build/daisy/usr ${vboot} +chromeos_peach=VBOOT=${chroot}/build/peach_pit/usr ${vboot} +''' + +boards = [ + ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 1', 'board0', ''], + ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 2', 'board1', ''], + ['Active', 'powerpc', 'powerpc', '', 'Tester', 'PowerPC board 1', 'board2', ''], + ['Active', 'powerpc', 'mpc5xx', '', 'Tester', 'PowerPC board 2', 'board3', ''], + ['Active', 'sandbox', 'sandbox', '', 'Tester', 'Sandbox board', 'board4', ''], +] + +commit_shortlog = """4aca821 patman: Avoid changing the order of tags +39403bb patman: Use --no-pager' to stop git from forking a pager +db6e6f2 patman: Remove the -a option +f2ccf03 patman: Correct unit tests to run correctly +1d097f9 patman: Fix indentation in terminal.py +d073747 patman: Support the 'reverse' option for 'git log +""" + +commit_log = ["""commit 7f6b8315d18f683c5181d0c3694818c1b2a20dcd +Author: Masahiro Yamada +Date: Fri Aug 22 19:12:41 2014 +0900 + + buildman: refactor help message + + "buildman [options]" is displayed by default. + + Append the rest of help messages to parser.usage + instead of replacing it. + + Besides, "-b " is not mandatory since commit fea5858e. + Drop it from the usage. + + Signed-off-by: Masahiro Yamada +""", +"""commit d0737479be6baf4db5e2cdbee123e96bc5ed0ba8 +Author: Simon Glass +Date: Thu Aug 14 16:48:25 2014 -0600 + + patman: Support the 'reverse' option for 'git log' + + This option is currently not supported, but needs to be, for buildman to + operate as expected. + + Series-changes: 7 + - Add new patch to fix the 'reverse' bug + + Series-version: 8 + + Change-Id: I79078f792e8b390b8a1272a8023537821d45feda + Reported-by: York Sun + Signed-off-by: Simon Glass + +""", +"""commit 1d097f9ab487c5019152fd47bda126839f3bf9fc +Author: Simon Glass +Date: Sat Aug 9 11:44:32 2014 -0600 + + patman: Fix indentation in terminal.py + + This code came from a different project with 2-character indentation. Fix + it for U-Boot. + + Series-changes: 6 + - Add new patch to fix indentation in teminal.py + + Change-Id: I5a74d2ebbb3cc12a665f5c725064009ac96e8a34 + Signed-off-by: Simon Glass + +""", +"""commit f2ccf03869d1e152c836515a3ceb83cdfe04a105 +Author: Simon Glass +Date: Sat Aug 9 11:08:24 2014 -0600 + + patman: Correct unit tests to run correctly + + It seems that doctest behaves differently now, and some of the unit tests + do not run. Adjust the tests to work correctly. + + ./tools/patman/patman --test + + + Series-changes: 6 + - Add new patch to fix patman unit tests + + Change-Id: I3d2ca588f4933e1f9d6b1665a00e4ae58269ff3b + +""", +"""commit db6e6f2f9331c5a37647d6668768d4a40b8b0d1c +Author: Simon Glass +Date: Sat Aug 9 12:06:02 2014 -0600 + + patman: Remove the -a option + + It seems that this is no longer needed, since checkpatch.pl will catch + whitespace problems in patches. Also the option is not widely used, so + it seems safe to just remove it. + + Series-changes: 6 + - Add new patch to remove patman's -a option + + Suggested-by: Masahiro Yamada + Change-Id: I5821a1c75154e532c46513486ca40b808de7e2cc + +""", +"""commit 39403bb4f838153028a6f21ca30bf100f3791133 +Author: Simon Glass +Date: Thu Aug 14 21:50:52 2014 -0600 + + patman: Use --no-pager' to stop git from forking a pager + +""", +"""commit 4aca821e27e97925c039e69fd37375b09c6f129c +Author: Simon Glass +Date: Fri Aug 22 15:57:39 2014 -0600 + + patman: Avoid changing the order of tags + + patman collects tags that it sees in the commit and places them nicely + sorted at the end of the patch. However, this is not really necessary and + in fact is apparently not desirable. + + Series-changes: 9 + - Add new patch to avoid changing the order of tags + + Series-version: 9 + + Suggested-by: Masahiro Yamada + Change-Id: Ib1518588c1a189ad5c3198aae76f8654aed8d0db +"""] + +TEST_BRANCH = '__testbranch' + +class TestFunctional(unittest.TestCase): + """Functional test for buildman. + + This aims to test from just below the invocation of buildman (parsing + of arguments) to 'make' and 'git' invocation. It is not a true + emd-to-end test, as it mocks git, make and the tool chain. But this + makes it easier to detect when the builder is doing the wrong thing, + since in many cases this test code will fail. For example, only a + very limited subset of 'git' arguments is supported - anything + unexpected will fail. + """ + def setUp(self): + self._base_dir = tempfile.mkdtemp() + self._git_dir = os.path.join(self._base_dir, 'src') + self._buildman_pathname = sys.argv[0] + self._buildman_dir = os.path.dirname(sys.argv[0]) + command.test_result = self._HandleCommand + self.setupToolchains() + self._toolchains.Add('arm-gcc', test=False) + self._toolchains.Add('powerpc-gcc', test=False) + bsettings.Setup(None) + bsettings.AddFile(settings_data) + self._boards = board.Boards() + for brd in boards: + self._boards.AddBoard(board.Board(*brd)) + + # Directories where the source been cloned + self._clone_dirs = [] + self._commits = len(commit_shortlog.splitlines()) + 1 + self._total_builds = self._commits * len(boards) + + # Number of calls to make + self._make_calls = 0 + + # Map of [board, commit] to error messages + self._error = {} + + self._test_branch = TEST_BRANCH + + # Avoid sending any output and clear all terminal output + terminal.SetPrintTestMode() + terminal.GetPrintTestLines() + + def tearDown(self): + shutil.rmtree(self._base_dir) + + def setupToolchains(self): + self._toolchains = toolchain.Toolchains() + self._toolchains.Add('gcc', test=False) + + def _RunBuildman(self, *args): + return command.RunPipe([[self._buildman_pathname] + list(args)], + capture=True, capture_stderr=True) + + def _RunControl(self, *args, **kwargs): + sys.argv = [sys.argv[0]] + list(args) + options, args = cmdline.ParseArgs() + result = control.DoBuildman(options, args, toolchains=self._toolchains, + make_func=self._HandleMake, boards=self._boards, + clean_dir=kwargs.get('clean_dir', True)) + self._builder = control.builder + return result + + def testFullHelp(self): + command.test_result = None + result = self._RunBuildman('-H') + help_file = os.path.join(self._buildman_dir, 'README') + self.assertEqual(len(result.stdout), os.path.getsize(help_file)) + self.assertEqual(0, len(result.stderr)) + self.assertEqual(0, result.return_code) + + def testHelp(self): + command.test_result = None + result = self._RunBuildman('-h') + help_file = os.path.join(self._buildman_dir, 'README') + self.assertTrue(len(result.stdout) > 1000) + self.assertEqual(0, len(result.stderr)) + self.assertEqual(0, result.return_code) + + def testGitSetup(self): + """Test gitutils.Setup(), from outside the module itself""" + command.test_result = command.CommandResult(return_code=1) + gitutil.Setup() + self.assertEqual(gitutil.use_no_decorate, False) + + command.test_result = command.CommandResult(return_code=0) + gitutil.Setup() + self.assertEqual(gitutil.use_no_decorate, True) + + def _HandleCommandGitLog(self, args): + if '-n0' in args: + return command.CommandResult(return_code=0) + elif args[-1] == 'upstream/master..%s' % self._test_branch: + return command.CommandResult(return_code=0, stdout=commit_shortlog) + elif args[:3] == ['--no-color', '--no-decorate', '--reverse']: + if args[-1] == self._test_branch: + count = int(args[3][2:]) + return command.CommandResult(return_code=0, + stdout=''.join(commit_log[:count])) + + # Not handled, so abort + print 'git log', args + sys.exit(1) + + def _HandleCommandGitConfig(self, args): + config = args[0] + if config == 'sendemail.aliasesfile': + return command.CommandResult(return_code=0) + elif config.startswith('branch.badbranch'): + return command.CommandResult(return_code=1) + elif config == 'branch.%s.remote' % self._test_branch: + return command.CommandResult(return_code=0, stdout='upstream\n') + elif config == 'branch.%s.merge' % self._test_branch: + return command.CommandResult(return_code=0, + stdout='refs/heads/master\n') + + # Not handled, so abort + print 'git config', args + sys.exit(1) + + def _HandleCommandGit(self, in_args): + """Handle execution of a git command + + This uses a hacked-up parser. + + Args: + in_args: Arguments after 'git' from the command line + """ + git_args = [] # Top-level arguments to git itself + sub_cmd = None # Git sub-command selected + args = [] # Arguments to the git sub-command + for arg in in_args: + if sub_cmd: + args.append(arg) + elif arg[0] == '-': + git_args.append(arg) + else: + if git_args and git_args[-1] in ['--git-dir', '--work-tree']: + git_args.append(arg) + else: + sub_cmd = arg + if sub_cmd == 'config': + return self._HandleCommandGitConfig(args) + elif sub_cmd == 'log': + return self._HandleCommandGitLog(args) + elif sub_cmd == 'clone': + return command.CommandResult(return_code=0) + elif sub_cmd == 'checkout': + return command.CommandResult(return_code=0) + + # Not handled, so abort + print 'git', git_args, sub_cmd, args + sys.exit(1) + + def _HandleCommandNm(self, args): + return command.CommandResult(return_code=0) + + def _HandleCommandObjdump(self, args): + return command.CommandResult(return_code=0) + + def _HandleCommandSize(self, args): + return command.CommandResult(return_code=0) + + def _HandleCommand(self, **kwargs): + """Handle a command execution. + + The command is in kwargs['pipe-list'], as a list of pipes, each a + list of commands. The command should be emulated as required for + testing purposes. + + Returns: + A CommandResult object + """ + pipe_list = kwargs['pipe_list'] + wc = False + if len(pipe_list) != 1: + if pipe_list[1] == ['wc', '-l']: + wc = True + else: + print 'invalid pipe', kwargs + sys.exit(1) + cmd = pipe_list[0][0] + args = pipe_list[0][1:] + result = None + if cmd == 'git': + result = self._HandleCommandGit(args) + elif cmd == './scripts/show-gnu-make': + return command.CommandResult(return_code=0, stdout='make') + elif cmd.endswith('nm'): + return self._HandleCommandNm(args) + elif cmd.endswith('objdump'): + return self._HandleCommandObjdump(args) + elif cmd.endswith( 'size'): + return self._HandleCommandSize(args) + + if not result: + # Not handled, so abort + print 'unknown command', kwargs + sys.exit(1) + + if wc: + result.stdout = len(result.stdout.splitlines()) + return result + + def _HandleMake(self, commit, brd, stage, cwd, *args, **kwargs): + """Handle execution of 'make' + + Args: + commit: Commit object that is being built + brd: Board object that is being built + stage: Stage that we are at (mrproper, config, build) + cwd: Directory where make should be run + args: Arguments to pass to make + kwargs: Arguments to pass to command.RunPipe() + """ + self._make_calls += 1 + if stage == 'mrproper': + return command.CommandResult(return_code=0) + elif stage == 'config': + return command.CommandResult(return_code=0, + combined='Test configuration complete') + elif stage == 'build': + stderr = '' + if type(commit) is not str: + stderr = self._error.get((brd.target, commit.sequence)) + if stderr: + return command.CommandResult(return_code=1, stderr=stderr) + return command.CommandResult(return_code=0) + + # Not handled, so abort + print 'make', stage + sys.exit(1) + + # Example function to print output lines + def print_lines(self, lines): + print len(lines) + for line in lines: + print line + #self.print_lines(terminal.GetPrintTestLines()) + + def testNoBoards(self): + """Test that buildman aborts when there are no boards""" + self._boards = board.Boards() + with self.assertRaises(SystemExit): + self._RunControl() + + def testCurrentSource(self): + """Very simple test to invoke buildman on the current source""" + self.setupToolchains(); + self._RunControl() + lines = terminal.GetPrintTestLines() + self.assertIn('Building current source for %d boards' % len(boards), + lines[0].text) + + def testBadBranch(self): + """Test that we can detect an invalid branch""" + with self.assertRaises(ValueError): + self._RunControl('-b', 'badbranch') + + def testBadToolchain(self): + """Test that missing toolchains are detected""" + self.setupToolchains(); + ret_code = self._RunControl('-b', TEST_BRANCH) + lines = terminal.GetPrintTestLines() + + # Buildman always builds the upstream commit as well + self.assertIn('Building %d commits for %d boards' % + (self._commits, len(boards)), lines[0].text) + self.assertEqual(self._builder.count, self._total_builds) + + # Only sandbox should succeed, the others don't have toolchains + self.assertEqual(self._builder.fail, + self._total_builds - self._commits) + self.assertEqual(ret_code, 128) + + for commit in range(self._commits): + for board in self._boards.GetList(): + if board.arch != 'sandbox': + errfile = self._builder.GetErrFile(commit, board.target) + fd = open(errfile) + self.assertEqual(fd.readlines(), + ['No tool chain for %s\n' % board.arch]) + fd.close() + + def testBranch(self): + """Test building a branch with all toolchains present""" + self._RunControl('-b', TEST_BRANCH) + self.assertEqual(self._builder.count, self._total_builds) + self.assertEqual(self._builder.fail, 0) + + def testCount(self): + """Test building a specific number of commitst""" + self._RunControl('-b', TEST_BRANCH, '-c2') + self.assertEqual(self._builder.count, 2 * len(boards)) + self.assertEqual(self._builder.fail, 0) + # Each board has a mrproper, config, and then one make per commit + self.assertEqual(self._make_calls, len(boards) * (2 + 2)) + + def testIncremental(self): + """Test building a branch twice - the second time should do nothing""" + self._RunControl('-b', TEST_BRANCH) + + # Each board has a mrproper, config, and then one make per commit + self.assertEqual(self._make_calls, len(boards) * (self._commits + 2)) + self._make_calls = 0 + self._RunControl('-b', TEST_BRANCH, clean_dir=False) + self.assertEqual(self._make_calls, 0) + self.assertEqual(self._builder.count, self._total_builds) + self.assertEqual(self._builder.fail, 0) + + def testForceBuild(self): + """The -f flag should force a rebuild""" + self._RunControl('-b', TEST_BRANCH) + self._make_calls = 0 + self._RunControl('-b', TEST_BRANCH, '-f', clean_dir=False) + # Each board has a mrproper, config, and then one make per commit + self.assertEqual(self._make_calls, len(boards) * (self._commits + 2)) + + def testForceReconfigure(self): + """The -f flag should force a rebuild""" + self._RunControl('-b', TEST_BRANCH, '-C') + # Each commit has a mrproper, config and make + self.assertEqual(self._make_calls, len(boards) * self._commits * 3) + + def testErrors(self): + """Test handling of build errors""" + self._error['board2', 1] = 'fred\n' + self._RunControl('-b', TEST_BRANCH) + self.assertEqual(self._builder.count, self._total_builds) + self.assertEqual(self._builder.fail, 1) + + # Remove the error. This should have no effect since the commit will + # not be rebuilt + del self._error['board2', 1] + self._make_calls = 0 + self._RunControl('-b', TEST_BRANCH, clean_dir=False) + self.assertEqual(self._builder.count, self._total_builds) + self.assertEqual(self._make_calls, 0) + self.assertEqual(self._builder.fail, 1) + + # Now use the -F flag to force rebuild of the bad commit + self._RunControl('-b', TEST_BRANCH, '-F', clean_dir=False) + self.assertEqual(self._builder.count, self._total_builds) + self.assertEqual(self._builder.fail, 0) + self.assertEqual(self._make_calls, 3) + + def testBranchWithSlash(self): + """Test building a branch with a '/' in the name""" + self._test_branch = '/__dev/__testbranch' + self._RunControl('-b', self._test_branch, clean_dir=False) + self.assertEqual(self._builder.count, self._total_builds) + self.assertEqual(self._builder.fail, 0) diff --git a/tools/buildman/kconfiglib.py b/tools/buildman/kconfiglib.py new file mode 100644 index 0000000000..655cf4470f --- /dev/null +++ b/tools/buildman/kconfiglib.py @@ -0,0 +1,3799 @@ +# +# SPDX-License-Identifier: ISC +# +# Author: Ulf Magnusson +# https://github.com/ulfalizer/Kconfiglib + +# This is Kconfiglib, a Python library for scripting, debugging, and extracting +# information from Kconfig-based configuration systems. To view the +# documentation, run +# +# $ pydoc kconfiglib +# +# or, if you prefer HTML, +# +# $ pydoc -w kconfiglib +# +# The examples/ subdirectory contains examples, to be run with e.g. +# +# $ make scriptconfig SCRIPT=Kconfiglib/examples/print_tree.py +# +# Look in testsuite.py for the test suite. + +""" +Kconfiglib is a Python library for scripting and extracting information from +Kconfig-based configuration systems. Features include the following: + + - Symbol values and properties can be looked up and values assigned + programmatically. + - .config files can be read and written. + - Expressions can be evaluated in the context of a Kconfig configuration. + - Relations between symbols can be quickly determined, such as finding all + symbols that reference a particular symbol. + - Highly compatible with the scripts/kconfig/*conf utilities. The test suite + automatically compares outputs between Kconfiglib and the C implementation + for a large number of cases. + +For the Linux kernel, scripts are run using + + $ make scriptconfig SCRIPT= [SCRIPT_ARG=] + +Running scripts via the 'scriptconfig' target ensures that required environment +variables (SRCARCH, ARCH, srctree, KERNELVERSION, etc.) are set up correctly. +Alternative architectures can be specified like for other 'make *config' +targets: + + $ make scriptconfig ARCH=mips SCRIPT= [SCRIPT_ARG=] + +The script will receive the name of the Kconfig file to load in sys.argv[1]. +(As of Linux 3.7.0-rc8 this is always "Kconfig" from the kernel top-level +directory.) If an argument is provided with SCRIPT_ARG, it will appear in +sys.argv[2]. + +To get an interactive Python prompt with Kconfiglib preloaded and a Config +object 'c' created, use + + $ make iscriptconfig [ARCH=] + +Kconfiglib requires Python 2. For (i)scriptconfig the command to run the Python +interpreter can be passed in the environment variable PYTHONCMD (defaults to +'python'; PyPy works too and is a bit faster). + +Look in the examples/ subdirectory for examples, which can be run with e.g. + + $ make scriptconfig SCRIPT=Kconfiglib/examples/print_tree.py + +or + + $ make scriptconfig SCRIPT=Kconfiglib/examples/help_grep.py SCRIPT_ARG="kernel" + +Look in testsuite.py for the test suite. + +Credits: Written by Ulf "Ulfalizer" Magnusson + +Send bug reports, suggestions and other feedback to kconfiglib@gmail.com . +Don't wrestle with internal APIs. Tell me what you need and I might add it in a +safe way as a client API instead.""" + +# If you have Psyco installed (32-bit installations, Python <= 2.6 only), +# setting this to True (right here, not at runtime) might give a nice speedup. +# (22% faster for parsing arch/x86/Kconfig and 58% faster for evaluating all +# symbols in it without a .config on my Core Duo.) +use_psyco = False + +import os +import re +import string +import sys + +class Config(): + + """Represents a Kconfig configuration, e.g. for i386 or ARM. This is the + set of symbols and other items appearing in the configuration together with + their values. Creating any number of Config objects -- including for + different architectures -- is safe; Kconfiglib has no global state.""" + + # + # Public interface + # + + def __init__(self, + filename = "Kconfig", + base_dir = "$srctree", + print_warnings = True, + print_undef_assign = False): + """Creates a new Config object, representing a Kconfig configuration. + Raises Kconfig_Syntax_Error on syntax errors. + + filename (default: "Kconfig") -- The base Kconfig file of the + configuration. For the Linux kernel, this should usually be be + "Kconfig" from the top-level directory, as environment + variables will make sure the right Kconfig is included from + there (usually arch//Kconfig). If you are using + kconfiglib via 'make scriptconfig' the filename of the + correct Kconfig will be in sys.argv[1]. + + base_dir (default: "$srctree") -- The base directory relative to which + 'source' statements within Kconfig files will work. For the + Linux kernel this should be the top-level directory of the + kernel tree. $-references to environment variables will be + expanded. + + The environment variable 'srctree' is set by the Linux makefiles + to the top-level kernel directory. A default of "." would not + work if an alternative build directory is used. + + print_warnings (default: True) -- Set to True if warnings related to + this configuration should be printed to stderr. This can + be changed later with Config.set_print_warnings(). It is + provided as a constructor argument since warnings might + be generated during parsing. + + print_undef_assign (default: False) -- Set to True if informational + messages related to assignments to undefined symbols + should be printed to stderr for this configuration. + Can be changed later with + Config.set_print_undef_assign().""" + + # The set of all symbols, indexed by name (a string) + self.syms = {} + + # The set of all defined symbols in the configuration in the order they + # appear in the Kconfig files. This excludes the special symbols n, m, + # and y as well as symbols that are referenced but never defined. + self.kconfig_syms = [] + + # The set of all named choices (yes, choices can have names), indexed + # by name (a string) + self.named_choices = {} + + def register_special_symbol(type, name, value): + sym = Symbol() + sym.is_special_ = True + sym.is_defined_ = True + sym.config = self + sym.name = name + sym.type = type + sym.cached_value = value + self.syms[name] = sym + return sym + + # The special symbols n, m and y, used as shorthand for "n", "m" and + # "y" + self.n = register_special_symbol(TRISTATE, "n", "n") + self.m = register_special_symbol(TRISTATE, "m", "m") + self.y = register_special_symbol(TRISTATE, "y", "y") + + # DEFCONFIG_LIST uses this + register_special_symbol(STRING, "UNAME_RELEASE", os.uname()[2]) + + # The symbol with "option defconfig_list" set, containing a list of + # default .config files + self.defconfig_sym = None + + # See Symbol.get_(src)arch() + self.arch = os.environ.get("ARCH") + self.srcarch = os.environ.get("SRCARCH") + + # See Config.__init__(). We need this for get_defconfig_filename(). + self.srctree = os.environ.get("srctree") + if self.srctree is None: + self.srctree = "." + + self.filename = filename + self.base_dir = _strip_trailing_slash(os.path.expandvars(base_dir)) + + # The 'mainmenu' text + self.mainmenu_text = None + + # The filename of the most recently loaded .config file + self.config_filename = None + + # The textual header of the most recently loaded .config, uncommented + self.config_header = None + + self.print_warnings = print_warnings + self.print_undef_assign = print_undef_assign + + # Lists containing all choices, menus and comments in the configuration + + self.choices = [] + self.menus = [] + self.comments = [] + + # For parsing routines that stop when finding a line belonging to a + # different construct, these holds that line and the tokenized version + # of that line. The purpose is to avoid having to re-tokenize the line, + # which is inefficient and causes problems when recording references to + # symbols. + self.end_line = None + self.end_line_tokens = None + + # See the comment in _parse_expr(). + self.parse_expr_cur_sym_or_choice = None + self.parse_expr_line = None + self.parse_expr_filename = None + self.parse_expr_linenr = None + self.parse_expr_transform_m = None + + # Parse the Kconfig files + self.top_block = self._parse_file(filename, None, None, None) + + # Build Symbol.dep for all symbols + self._build_dep() + + def load_config(self, filename, replace = True): + """Loads symbol values from a file in the familiar .config format. + Equivalent to calling Symbol.set_user_value() to set each of the + values. + + filename -- The .config file to load. $-references to environment + variables will be expanded. For scripts to work even + when an alternative build directory is used with the + Linux kernel, you need to refer to the top-level kernel + directory with "$srctree". + + replace (default: True) -- True if the configuration should replace + the old configuration; False if it should add to it.""" + + def warn_override(filename, linenr, name, old_user_val, new_user_val): + self._warn("overriding the value of {0}. " + 'Old value: "{1}", new value: "{2}".' + .format(name, old_user_val, new_user_val), + filename, + linenr) + + filename = os.path.expandvars(filename) + + # Put this first so that a missing file doesn't screw up our state + line_feeder = _FileFeed(_get_lines(filename), filename) + + self.config_filename = filename + + # Invalidate everything. This is usually faster than finding the + # minimal set of symbols that needs to be invalidated, as nearly all + # symbols will tend to be affected anyway. + if replace: + self.unset_user_values() + else: + self._invalidate_all() + + # Read header + + self.config_header = None + + def is_header_line(line): + return line.startswith("#") and \ + not unset_re.match(line) + + first_line = line_feeder.get_next() + + if first_line is None: + return + + if not is_header_line(first_line): + line_feeder.go_back() + else: + self.config_header = first_line[1:] + + # Read remaining header lines + while 1: + line = line_feeder.get_next() + + if line is None: + break + + if not is_header_line(line): + line_feeder.go_back() + break + + self.config_header += line[1:] + + # Remove trailing newline + if self.config_header.endswith("\n"): + self.config_header = self.config_header[:-1] + + # Read assignments + + filename = line_feeder.get_filename() + + while 1: + line = line_feeder.get_next() + if line is None: + return + + linenr = line_feeder.get_linenr() + + line = line.strip() + + set_re_match = set_re.match(line) + if set_re_match: + name, val = set_re_match.groups() + # The unescaping producedure below should be safe since " can + # only appear as \" inside the string + val = _strip_quotes(val, line, filename, linenr)\ + .replace('\\"', '"').replace("\\\\", "\\") + if name in self.syms: + sym = self.syms[name] + + old_user_val = sym.user_val + if old_user_val is not None: + warn_override(filename, linenr, name, old_user_val, val) + + if sym.is_choice_symbol_: + user_mode = sym.parent.user_mode + if user_mode is not None and user_mode != val: + self._warn("assignment to {0} changes mode of containing " + 'choice from "{1}" to "{2}".' + .format(name, val, user_mode), + filename, + linenr) + + sym._set_user_value_no_invalidate(val, True) + + else: + self._undef_assign('attempt to assign the value "{0}" to the ' + "undefined symbol {1}." + .format(val, name), + filename, + linenr) + + else: + unset_re_match = unset_re.match(line) + if unset_re_match: + name = unset_re_match.group(1) + if name in self.syms: + sym = self.syms[name] + + old_user_val = sym.user_val + if old_user_val is not None: + warn_override(filename, linenr, name, old_user_val, "n") + + sym._set_user_value_no_invalidate("n", True) + + def write_config(self, filename, header = None): + """Writes out symbol values in the familiar .config format. + + filename -- The filename under which to save the configuration. + + header (default: None) -- A textual header that will appear at the + beginning of the file, with each line commented out + automatically. None means no header.""" + + # already_written is set when _make_conf() is called on a symbol, so + # that symbols defined in multiple locations only get one entry in the + # .config. We need to reset it prior to writing out a new .config. + for sym in self.syms.itervalues(): + sym.already_written = False + + with open(filename, "w") as f: + # Write header + if header is not None: + f.write(_comment(header)) + f.write("\n") + + # Write configuration. + # (You'd think passing a list around to all the nodes and appending + # to it to avoid copying would be faster, but it's actually a lot + # slower with PyPy, and about as fast with Python. Passing the file + # around is slower too.) + f.write("\n".join(self.top_block._make_conf())) + f.write("\n") + + def get_kconfig_filename(self): + """Returns the name of the (base) kconfig file this configuration was + loaded from.""" + return self.filename + + def get_arch(self): + """Returns the value the environment variable ARCH had at the time the + Config instance was created, or None if ARCH was not set. For the + kernel, this corresponds to the architecture being built for, with + values such as "i386" or "mips".""" + return self.arch + + def get_srcarch(self): + """Returns the value the environment variable SRCARCH had at the time + the Config instance was created, or None if SRCARCH was not set. For + the kernel, this corresponds to the arch/ subdirectory containing + architecture-specific source code.""" + return self.srcarch + + def get_srctree(self): + """Returns the value the environment variable srctree had at the time + the Config instance was created, or None if srctree was not defined. + This variable points to the source directory and is used when building + in a separate directory.""" + return self.srctree + + def get_config_filename(self): + """Returns the name of the most recently loaded configuration file, or + None if no configuration has been loaded.""" + return self.config_filename + + def get_mainmenu_text(self): + """Returns the text of the 'mainmenu' statement (with $-references to + symbols replaced by symbol values), or None if the configuration has no + 'mainmenu' statement.""" + return None if self.mainmenu_text is None else \ + self._expand_sym_refs(self.mainmenu_text) + + def get_defconfig_filename(self): + """Returns the name of the defconfig file, which is the first existing + file in the list given in a symbol having 'option defconfig_list' set. + $-references to symbols will be expanded ("$FOO bar" -> "foo bar" if + FOO has the value "foo"). Returns None in case of no defconfig file. + Setting 'option defconfig_list' on multiple symbols currently results + in undefined behavior. + + If the environment variable 'srctree' was set when the Config was + created, get_defconfig_filename() will first look relative to that + directory before looking in the current directory; see + Config.__init__().""" + + if self.defconfig_sym is None: + return None + + for (filename, cond_expr) in self.defconfig_sym.def_exprs: + if self._eval_expr(cond_expr) == "y": + filename = self._expand_sym_refs(filename) + + # We first look in $srctree. os.path.join() won't work here as + # an absolute path in filename would override $srctree. + srctree_filename = os.path.normpath(self.srctree + "/" + filename) + if os.path.exists(srctree_filename): + return srctree_filename + + if os.path.exists(filename): + return filename + + return None + + def get_symbol(self, name): + """Returns the symbol with name 'name', or None if no such symbol + appears in the configuration. An alternative shorthand is conf[name], + where conf is a Config instance, though that will instead raise + KeyError if the symbol does not exist.""" + return self.syms.get(name) + + def get_top_level_items(self): + """Returns a list containing the items (symbols, menus, choice + statements and comments) at the top level of the configuration -- that + is, all items that do not appear within a menu or choice. The items + appear in the same order as within the configuration.""" + return self.top_block.get_items() + + def get_symbols(self, all_symbols = True): + """Returns a list of symbols from the configuration. An alternative for + iterating over all defined symbols (in the order of definition) is + + for sym in config: + ... + + which relies on Config implementing __iter__() and is equivalent to + + for sym in config.get_symbols(False): + ... + + all_symbols (default: True) -- If True, all symbols - including special + and undefined symbols - will be included in the result, in + an undefined order. If False, only symbols actually defined + and not merely referred to in the configuration will be + included in the result, and will appear in the order that + they are defined within the Kconfig configuration files.""" + return self.syms.values() if all_symbols else self.kconfig_syms + + def get_choices(self): + """Returns a list containing all choice statements in the + configuration, in the order they appear in the Kconfig files.""" + return self.choices + + def get_menus(self): + """Returns a list containing all menus in the configuration, in the + order they appear in the Kconfig files.""" + return self.menus + + def get_comments(self): + """Returns a list containing all comments in the configuration, in the + order they appear in the Kconfig files.""" + return self.comments + + def eval(self, s): + """Returns the value of the expression 's' -- where 's' is represented + as a string -- in the context of the configuration. Raises + Kconfig_Syntax_Error if syntax errors are detected in 's'. + + For example, if FOO and BAR are tristate symbols at least one of which + has the value "y", then config.eval("y && (FOO || BAR)") => "y" + + This functions always yields a tristate value. To get the value of + non-bool, non-tristate symbols, use Symbol.get_value(). + + The result of this function is consistent with how evaluation works for + conditional expressions in the configuration as well as in the C + implementation. "m" and m are rewritten as '"m" && MODULES' and 'm && + MODULES', respectively, and a result of "m" will get promoted to "y" if + we're running without modules.""" + return self._eval_expr(self._parse_expr(self._tokenize(s, True), # Feed + None, # Current symbol or choice + s)) # line + + def get_config_header(self): + """Returns the (uncommented) textual header of the .config file most + recently loaded with load_config(). Returns None if no .config file has + been loaded or if the most recently loaded .config file has no header. + The header comprises all lines up to but not including the first line + that either + + 1. Does not start with "#" + 2. Has the form "# CONFIG_FOO is not set." + """ + return self.config_header + + def get_base_dir(self): + """Returns the base directory relative to which 'source' statements + will work, passed as an argument to Config.__init__().""" + return self.base_dir + + def set_print_warnings(self, print_warnings): + """Determines whether warnings related to this configuration (for + things like attempting to assign illegal values to symbols with + Symbol.set_user_value()) should be printed to stderr. + + print_warnings -- True if warnings should be + printed, otherwise False.""" + self.print_warnings = print_warnings + + def set_print_undef_assign(self, print_undef_assign): + """Determines whether informational messages related to assignments to + undefined symbols should be printed to stderr for this configuration. + + print_undef_assign -- If True, such messages will be printed.""" + self.print_undef_assign = print_undef_assign + + def __getitem__(self, key): + """Returns the symbol with name 'name'. Raises KeyError if the symbol + does not appear in the configuration.""" + return self.syms[key] + + def __iter__(self): + """Convenience function for iterating over the set of all defined + symbols in the configuration, used like + + for sym in conf: + ... + + The iteration happens in the order of definition within the Kconfig + configuration files. Symbols only referred to but not defined will not + be included, nor will the special symbols n, m, and y. If you want to + include such symbols as well, see config.get_symbols().""" + return iter(self.kconfig_syms) + + def unset_user_values(self): + """Resets the values of all symbols, as if Config.load_config() or + Symbol.set_user_value() had never been called.""" + for sym in self.syms.itervalues(): + sym._unset_user_value_no_recursive_invalidate() + + def __str__(self): + """Returns a string containing various information about the Config.""" + return _sep_lines("Configuration", + "File : " + self.filename, + "Base directory : " + self.base_dir, + "Value of $ARCH at creation time : " + + ("(not set)" if self.arch is None else self.arch), + "Value of $SRCARCH at creation time : " + + ("(not set)" if self.srcarch is None else self.srcarch), + "Source tree (derived from $srctree;", + "defaults to '.' if $srctree isn't set) : " + self.srctree, + "Most recently loaded .config : " + + ("(no .config loaded)" if self.config_filename is None else + self.config_filename), + "Print warnings : " + + bool_str[self.print_warnings], + "Print assignments to undefined symbols : " + + bool_str[self.print_undef_assign]) + + + # + # Private methods + # + + def _invalidate_all(self): + for sym in self.syms.itervalues(): + sym._invalidate() + + def _tokenize(self, + s, + for_eval = False, + filename = None, + linenr = None): + """Returns a _Feed instance containing tokens derived from the string + 's'. Registers any new symbols encountered (via _sym_lookup()). + + (I experimented with a pure regular expression implementation, but it + came out slower, less readable, and wouldn't have been as flexible.) + + for_eval -- True when parsing an expression for a call to + Config.eval(), in which case we should not treat the first + token specially nor register new symbols.""" + s = s.lstrip() + if s == "" or s[0] == "#": + return _Feed([]) + + if for_eval: + i = 0 # The current index in the string being tokenized + previous = None # The previous token seen + tokens = [] + else: + # The initial word on a line is parsed specially. Let + # command_chars = [A-Za-z0-9_]. Then + # - leading non-command_chars characters on the line are ignored, and + # - the first token consists the following one or more command_chars + # characters. + # This is why things like "----help--" are accepted. + + initial_token_match = initial_token_re.match(s) + if initial_token_match is None: + return _Feed([]) + # The current index in the string being tokenized + i = initial_token_match.end() + + keyword = keywords.get(initial_token_match.group(1)) + if keyword is None: + # We expect a keyword as the first token + _tokenization_error(s, len(s), filename, linenr) + if keyword == T_HELP: + # Avoid junk after "help", e.g. "---", being registered as a + # symbol + return _Feed([T_HELP]) + tokens = [keyword] + previous = keyword + + # _tokenize() is a hotspot during parsing, and this speeds things up a + # bit + strlen = len(s) + append = tokens.append + + # Main tokenization loop. (Handles tokens past the first one.) + while i < strlen: + # Test for an identifier/keyword preceded by whitespace first; this + # is the most common case. + id_keyword_match = id_keyword_re.match(s, i) + if id_keyword_match: + # We have an identifier or keyword. The above also stripped any + # whitespace for us. + name = id_keyword_match.group(1) + # Jump past it + i = id_keyword_match.end() + + # Keyword? + keyword = keywords.get(name) + if keyword is not None: + append(keyword) + # What would ordinarily be considered a name is treated as a + # string after certain tokens. + elif previous in string_lex: + append(name) + else: + # We're dealing with a symbol. _sym_lookup() will take care + # of allocating a new Symbol instance if it's the first + # time we see it. + sym = self._sym_lookup(name, not for_eval) + + if previous == T_CONFIG or previous == T_MENUCONFIG: + # If the previous token is T_(MENU)CONFIG + # ("(menu)config"), we're tokenizing the first line of + # a symbol definition, and should remember this as a + # location where the symbol is defined. + sym.def_locations.append((filename, linenr)) + else: + # Otherwise, it's a reference to the symbol + sym.ref_locations.append((filename, linenr)) + + append(sym) + + else: + # This restrips whitespace that could have been stripped in the + # regex above, but it's worth it since identifiers/keywords are + # more common + s = s[i:].lstrip() + if s == "": + break + strlen = len(s) + i = 0 + c = s[0] + + # String literal (constant symbol) + if c == '"' or c == "'": + i += 1 + + if "\\" in s: + # Slow path: This could probably be sped up, but it's a + # very unusual case anyway. + quote = c + value = "" + while 1: + if i >= strlen: + _tokenization_error(s, strlen, filename, + linenr) + c = s[i] + if c == quote: + break + if c == "\\": + if i + 1 >= strlen: + _tokenization_error(s, strlen, filename, + linenr) + value += s[i + 1] + i += 2 + else: + value += c + i += 1 + i += 1 + append(value) + else: + # Fast path: If the string contains no backslashes (almost + # always) we can simply look for the matching quote. + end = s.find(c, i) + if end == -1: + _tokenization_error(s, strlen, filename, linenr) + append(s[i:end]) + i = end + 1 + + elif c == "&": + if i + 1 >= strlen: + # Invalid characters are ignored + continue + if s[i + 1] != "&": + # Invalid characters are ignored + i += 1 + continue + append(T_AND) + i += 2 + + elif c == "|": + if i + 1 >= strlen: + # Invalid characters are ignored + continue + if s[i + 1] != "|": + # Invalid characters are ignored + i += 1 + continue + append(T_OR) + i += 2 + + elif c == "!": + if i + 1 >= strlen: + _tokenization_error(s, strlen, filename, linenr) + if s[i + 1] == "=": + append(T_UNEQUAL) + i += 2 + else: + append(T_NOT) + i += 1 + + elif c == "=": + append(T_EQUAL) + i += 1 + + elif c == "(": + append(T_OPEN_PAREN) + i += 1 + + elif c == ")": + append(T_CLOSE_PAREN) + i += 1 + + elif c == "#": + break + + else: + # Invalid characters are ignored + i += 1 + continue + + previous = tokens[-1] + + return _Feed(tokens) + + # + # Parsing + # + + # Expression grammar: + # + # -> + # '=' + # '!=' + # '(' ')' + # '!' + # '&&' + # '||' + + def _parse_expr(self, + feed, + cur_sym_or_choice, + line, + filename = None, + linenr = None, + transform_m = True): + """Parse an expression from the tokens in 'feed' using a simple + top-down approach. The result has the form (, ). + + feed -- _Feed instance containing the tokens for the expression. + + cur_sym_or_choice -- The symbol or choice currently being parsed, or + None if we're not parsing a symbol or choice. + Used for recording references to symbols. + + line -- The line containing the expression being parsed. + + filename (default: None) -- The file containing the expression. + + linenr (default: None) -- The line number containing the expression. + + transform_m (default: False) -- Determines if 'm' should be rewritten to + 'm && MODULES' -- see + parse_val_and_cond().""" + + # Use instance variables to avoid having to pass these as arguments + # through the top-down parser in _parse_expr_2(), which is tedious and + # obfuscates the code. A profiler run shows no noticeable performance + # difference. + self.parse_expr_cur_sym_or_choice = cur_sym_or_choice + self.parse_expr_line = line + self.parse_expr_filename = filename + self.parse_expr_linenr = linenr + self.parse_expr_transform_m = transform_m + + return self._parse_expr_2(feed) + + def _parse_expr_2(self, feed): + or_terms = [self._parse_or_term(feed)] + # Keep parsing additional terms while the lookahead is '||' + while feed.check(T_OR): + or_terms.append(self._parse_or_term(feed)) + + return or_terms[0] if len(or_terms) == 1 else (OR, or_terms) + + def _parse_or_term(self, feed): + and_terms = [self._parse_factor(feed)] + # Keep parsing additional terms while the lookahead is '&&' + while feed.check(T_AND): + and_terms.append(self._parse_factor(feed)) + + return and_terms[0] if len(and_terms) == 1 else (AND, and_terms) + + def _parse_factor(self, feed): + if feed.check(T_OPEN_PAREN): + expr_parse = self._parse_expr_2(feed) + + if not feed.check(T_CLOSE_PAREN): + _parse_error(self.parse_expr_line, + "missing end parenthesis.", + self.parse_expr_filename, + self.parse_expr_linenr) + + return expr_parse + + if feed.check(T_NOT): + return (NOT, self._parse_factor(feed)) + + sym_or_string = feed.get_next() + + if not isinstance(sym_or_string, (Symbol, str)): + _parse_error(self.parse_expr_line, + "malformed expression.", + self.parse_expr_filename, + self.parse_expr_linenr) + + if self.parse_expr_cur_sym_or_choice is not None and \ + isinstance(sym_or_string, Symbol): + self.parse_expr_cur_sym_or_choice.referenced_syms.add(sym_or_string) + + next_token = feed.peek_next() + + # For conditional expressions ('depends on ', '... if ', + # etc.), "m" and m are rewritten to "m" && MODULES. + if next_token != T_EQUAL and next_token != T_UNEQUAL: + if self.parse_expr_transform_m and (sym_or_string is self.m or + sym_or_string == "m"): + return (AND, ["m", self._sym_lookup("MODULES")]) + return sym_or_string + + relation = EQUAL if (feed.get_next() == T_EQUAL) else UNEQUAL + sym_or_string_2 = feed.get_next() + + if self.parse_expr_cur_sym_or_choice is not None and \ + isinstance(sym_or_string_2, Symbol): + self.parse_expr_cur_sym_or_choice.referenced_syms.add(sym_or_string_2) + + if sym_or_string is self.m: + sym_or_string = "m" + + if sym_or_string_2 is self.m: + sym_or_string_2 = "m" + + return (relation, sym_or_string, sym_or_string_2) + + def _parse_file(self, filename, parent, deps, visible_if_deps, res = None): + """Parse the Kconfig file 'filename'. The result is a _Block with all + items from the file. See _parse_block() for the meaning of the + parameters.""" + line_feeder = _FileFeed(_get_lines(filename), filename) + return self._parse_block(line_feeder, None, parent, deps, visible_if_deps, res) + + def _parse_block(self, line_feeder, end_marker, parent, deps, + visible_if_deps = None, res = None): + """Parses a block, which is the contents of either a file or an if, + menu, or choice statement. The result is a _Block with the items from + the block. + + end_marker -- The token that ends the block, e.g. T_ENDIF ("endif") for + if's. None for files. + + parent -- The enclosing menu, choice or if, or None if we're at the top + level. + + deps -- Dependencies from enclosing menus, choices and if's. + + visible_if_deps (default: None) -- 'visible if' dependencies from + enclosing menus. + + res (default: None) -- The _Block to add items to. If None, a new + _Block is created to hold the items.""" + + block = _Block() if res is None else res + + filename = line_feeder.get_filename() + + while 1: + + # Do we already have a tokenized line that we determined wasn't + # part of whatever we were parsing earlier? See comment in + # Config.__init__(). + if self.end_line is not None: + assert self.end_line_tokens is not None + tokens = self.end_line_tokens + tokens.go_to_start() + + line = self.end_line + linenr = line_feeder.get_linenr() + + self.end_line = None + self.end_line_tokens = None + + else: + line = line_feeder.get_next() + if line is None: + if end_marker is not None: + raise Kconfig_Syntax_Error, ( + "Unexpected end of file {0}." + .format(line_feeder.get_filename())) + return block + + linenr = line_feeder.get_linenr() + + tokens = self._tokenize(line, False, filename, linenr) + + if tokens.is_empty(): + continue + + t0 = tokens.get_next() + + # Have we reached the end of the block? + if t0 == end_marker: + return block + + if t0 == T_CONFIG or t0 == T_MENUCONFIG: + # The tokenizer will automatically allocate a new Symbol object + # for any new names it encounters, so we don't need to worry + # about that here. + sym = tokens.get_next() + + # Symbols defined in multiple places get the parent of their + # first definition. However, for symbols whose parents are choice + # statements, the choice statement takes precedence. + if not sym.is_defined_ or isinstance(parent, Choice): + sym.parent = parent + + sym.is_defined_ = True + + self.kconfig_syms.append(sym) + block.add_item(sym) + + self._parse_properties(line_feeder, sym, deps, visible_if_deps) + + elif t0 == T_MENU: + menu = Menu() + self.menus.append(menu) + menu.config = self + menu.parent = parent + menu.title = tokens.get_next() + + menu.filename = filename + menu.linenr = linenr + + # Parse properties and contents + self._parse_properties(line_feeder, menu, deps, visible_if_deps) + menu.block = self._parse_block(line_feeder, + T_ENDMENU, + menu, + menu.dep_expr, + _make_and(visible_if_deps, + menu.visible_if_expr)) + + block.add_item(menu) + + elif t0 == T_IF: + # If statements are treated as syntactic sugar for adding + # dependencies to enclosed items and do not have an explicit + # object representation. + + dep_expr = self._parse_expr(tokens, None, line, filename, linenr) + self._parse_block(line_feeder, + T_ENDIF, + parent, + _make_and(dep_expr, deps), + visible_if_deps, + block) # Add items to the same block + + elif t0 == T_CHOICE: + # We support named choices + already_defined = False + name = None + if len(tokens) > 1 and isinstance(tokens[1], str): + name = tokens[1] + already_defined = name in self.named_choices + + if already_defined: + choice = self.named_choices[name] + else: + choice = Choice() + self.choices.append(choice) + if name is not None: + choice.name = name + self.named_choices[name] = choice + + choice.config = self + choice.parent = parent + + choice.def_locations.append((filename, linenr)) + + # Parse properties and contents + self._parse_properties(line_feeder, choice, deps, visible_if_deps) + choice.block = self._parse_block(line_feeder, + T_ENDCHOICE, + choice, + None, + visible_if_deps) + + choice._determine_actual_symbols() + + # If no type is set for the choice, its type is that of the first + # choice item + if choice.type == UNKNOWN: + for item in choice.get_symbols(): + if item.type != UNKNOWN: + choice.type = item.type + break + + # Each choice item of UNKNOWN type gets the type of the choice + for item in choice.get_symbols(): + if item.type == UNKNOWN: + item.type = choice.type + + # For named choices defined in multiple locations, only record + # at the first definition + if not already_defined: + block.add_item(choice) + + elif t0 == T_COMMENT: + comment = Comment() + comment.config = self + comment.parent = parent + + comment.filename = filename + comment.linenr = linenr + + comment.text = tokens.get_next() + self._parse_properties(line_feeder, comment, deps, visible_if_deps) + + block.add_item(comment) + self.comments.append(comment) + + elif t0 == T_SOURCE: + kconfig_file = tokens.get_next() + exp_kconfig_file = self._expand_sym_refs(kconfig_file) + f = os.path.join(self.base_dir, exp_kconfig_file) + + if not os.path.exists(f): + raise IOError, ('{0}:{1}: sourced file "{2}" (expands to\n' + '"{3}") not found. Perhaps base_dir\n' + '(argument to Config.__init__(), currently\n' + '"{4}") is set to the wrong value.' + .format(filename, + linenr, + kconfig_file, + exp_kconfig_file, + self.base_dir)) + + # Add items to the same block + self._parse_file(f, parent, deps, visible_if_deps, block) + + elif t0 == T_MAINMENU: + text = tokens.get_next() + + if self.mainmenu_text is not None: + self._warn("overriding 'mainmenu' text. " + 'Old value: "{0}", new value: "{1}".' + .format(self.mainmenu_text, text), + filename, + linenr) + + self.mainmenu_text = text + + else: + _parse_error(line, "unrecognized construct.", filename, linenr) + + def _parse_properties(self, line_feeder, stmt, deps, visible_if_deps): + """Parsing of properties for symbols, menus, choices, and comments.""" + + def parse_val_and_cond(tokens, line, filename, linenr): + """Parses ' if ' constructs, where the 'if' part is + optional. Returns a tuple containing the parsed expressions, with + None as the second element if the 'if' part is missing.""" + val = self._parse_expr(tokens, stmt, line, filename, linenr, False) + + if tokens.check(T_IF): + return (val, self._parse_expr(tokens, stmt, line, filename, linenr)) + + return (val, None) + + # In case the symbol is defined in multiple locations, we need to + # remember what prompts, defaults, and selects are new for this + # definition, as "depends on" should only apply to the local + # definition. + new_prompt = None + new_def_exprs = [] + new_selects = [] + + # Dependencies from 'depends on' statements + depends_on_expr = None + + while 1: + line = line_feeder.get_next() + if line is None: + break + + filename = line_feeder.get_filename() + linenr = line_feeder.get_linenr() + + tokens = self._tokenize(line, False, filename, linenr) + + if tokens.is_empty(): + continue + + t0 = tokens.get_next() + + if t0 == T_HELP: + # Find first non-empty line and get its indentation + + line_feeder.remove_while(str.isspace) + line = line_feeder.get_next() + + if line is None: + stmt.help = "" + break + + indent = _indentation(line) + + # If the first non-empty lines has zero indent, there is no + # help text + if indent == 0: + stmt.help = "" + line_feeder.go_back() + break + + help_lines = [_deindent(line, indent)] + + # The help text goes on till the first non-empty line with less + # indent + while 1: + line = line_feeder.get_next() + if (line is None) or \ + (not line.isspace() and _indentation(line) < indent): + stmt.help = "".join(help_lines) + break + + help_lines.append(_deindent(line, indent)) + + if line is None: + break + + line_feeder.go_back() + + elif t0 == T_PROMPT: + # 'prompt' properties override each other within a single + # definition of a symbol, but additional prompts can be added + # by defining the symbol multiple times; hence 'new_prompt' + # instead of 'prompt'. + new_prompt = parse_val_and_cond(tokens, line, filename, linenr) + + elif t0 == T_DEFAULT: + new_def_exprs.append(parse_val_and_cond(tokens, line, filename, linenr)) + + elif t0 == T_DEPENDS: + if not tokens.check(T_ON): + _parse_error(line, 'expected "on" after "depends".', filename, linenr) + + parsed_deps = self._parse_expr(tokens, stmt, line, filename, linenr) + + if isinstance(stmt, (Menu, Comment)): + stmt.dep_expr = _make_and(stmt.dep_expr, parsed_deps) + else: + depends_on_expr = _make_and(depends_on_expr, parsed_deps) + + elif t0 == T_VISIBLE: + if not tokens.check(T_IF): + _parse_error(line, 'expected "if" after "visible".', filename, linenr) + if not isinstance(stmt, Menu): + _parse_error(line, + "'visible if' is only valid for menus.", + filename, + linenr) + + parsed_deps = self._parse_expr(tokens, stmt, line, filename, linenr) + stmt.visible_if_expr = _make_and(stmt.visible_if_expr, parsed_deps) + + elif t0 == T_SELECT: + target = tokens.get_next() + + stmt.referenced_syms.add(target) + stmt.selected_syms.add(target) + + if tokens.check(T_IF): + new_selects.append((target, + self._parse_expr(tokens, stmt, line, filename, linenr))) + else: + new_selects.append((target, None)) + + elif t0 in (T_BOOL, T_TRISTATE, T_INT, T_HEX, T_STRING): + stmt.type = token_to_type[t0] + + if len(tokens) > 1: + new_prompt = parse_val_and_cond(tokens, line, filename, linenr) + + elif t0 == T_RANGE: + lower = tokens.get_next() + upper = tokens.get_next() + stmt.referenced_syms.add(lower) + stmt.referenced_syms.add(upper) + + if tokens.check(T_IF): + stmt.ranges.append((lower, upper, + self._parse_expr(tokens, stmt, line, filename, linenr))) + else: + stmt.ranges.append((lower, upper, None)) + + elif t0 == T_DEF_BOOL: + stmt.type = BOOL + + if len(tokens) > 1: + new_def_exprs.append(parse_val_and_cond(tokens, line, filename, linenr)) + + elif t0 == T_DEF_TRISTATE: + stmt.type = TRISTATE + + if len(tokens) > 1: + new_def_exprs.append(parse_val_and_cond(tokens, line, filename, linenr)) + + elif t0 == T_OPTIONAL: + if not isinstance(stmt, Choice): + _parse_error(line, + '"optional" is only valid for choices.', + filename, + linenr) + stmt.optional = True + + elif t0 == T_OPTION: + if tokens.check(T_ENV) and tokens.check(T_EQUAL): + env_var = tokens.get_next() + + stmt.is_special_ = True + stmt.is_from_env = True + + if env_var not in os.environ: + self._warn(""" +The symbol {0} references the non-existent environment variable {1} and will +get the empty string as its value. + +If you're using kconfiglib via 'make (i)scriptconfig' it should have set up the +environment correctly for you. If you still got this message, that might be an +error, and you should e-mail kconfiglib@gmail.com. +.""" .format(stmt.name, env_var), + filename, + linenr) + + stmt.cached_value = "" + else: + stmt.cached_value = os.environ[env_var] + + elif tokens.check(T_DEFCONFIG_LIST): + self.defconfig_sym = stmt + + elif tokens.check(T_MODULES): + self._warn("the 'modules' option is not supported. " + "Let me know if this is a problem for you; " + "it shouldn't be that hard to implement.", + filename, + linenr) + + else: + _parse_error(line, "unrecognized option.", filename, linenr) + + else: + # See comment in Config.__init__() + self.end_line = line + self.end_line_tokens = tokens + break + + # Propagate dependencies from enclosing menus and if's. + + # For menus and comments.. + if isinstance(stmt, (Menu, Comment)): + stmt.orig_deps = stmt.dep_expr + stmt.deps_from_containing = deps + stmt.dep_expr = _make_and(stmt.dep_expr, deps) + + stmt.all_referenced_syms = \ + stmt.referenced_syms | _get_expr_syms(deps) + + # For symbols and choices.. + else: + + # See comment for 'menu_dep' + stmt.menu_dep = depends_on_expr + + # Propagate dependencies specified with 'depends on' to any new + # default expressions, prompts, and selections. ("New" since a + # symbol might be defined in multiple places and the dependencies + # should only apply to the local definition.) + + new_def_exprs = [(val_expr, _make_and(cond_expr, depends_on_expr)) + for (val_expr, cond_expr) in new_def_exprs] + + new_selects = [(target, _make_and(cond_expr, depends_on_expr)) + for (target, cond_expr) in new_selects] + + if new_prompt is not None: + prompt, cond_expr = new_prompt + + # 'visible if' dependencies from enclosing menus get propagated + # to prompts + if visible_if_deps is not None: + cond_expr = _make_and(cond_expr, visible_if_deps) + + new_prompt = (prompt, _make_and(cond_expr, depends_on_expr)) + + # We save the original expressions -- before any menu and if + # conditions have been propagated -- so these can be retrieved + # later. + + stmt.orig_def_exprs.extend(new_def_exprs) + if new_prompt is not None: + stmt.orig_prompts.append(new_prompt) + + # Only symbols can select + if isinstance(stmt, Symbol): + stmt.orig_selects.extend(new_selects) + + # Save dependencies from enclosing menus and if's + stmt.deps_from_containing = deps + + # The set of symbols referenced directly by the symbol/choice plus + # all symbols referenced by enclosing menus and if's. + stmt.all_referenced_syms = \ + stmt.referenced_syms | _get_expr_syms(deps) + + # Propagate dependencies from enclosing menus and if's + + stmt.def_exprs.extend([(val_expr, _make_and(cond_expr, deps)) + for (val_expr, cond_expr) in new_def_exprs]) + + for (target, cond) in new_selects: + target.rev_dep = _make_or(target.rev_dep, + _make_and(stmt, + _make_and(cond, deps))) + + if new_prompt is not None: + prompt, cond_expr = new_prompt + stmt.prompts.append((prompt, _make_and(cond_expr, deps))) + + # + # Symbol table manipulation + # + + def _sym_lookup(self, name, add_sym_if_not_exists = True): + """Fetches the symbol 'name' from the symbol table, optionally adding + it if it does not exist (this is usually what we want).""" + if name in self.syms: + return self.syms[name] + + new_sym = Symbol() + new_sym.config = self + new_sym.name = name + + if add_sym_if_not_exists: + self.syms[name] = new_sym + else: + # This warning is generated while evaluating an expression + # containing undefined symbols using Config.eval() + self._warn("no symbol {0} in configuration".format(name)) + + return new_sym + + # + # Evaluation of symbols and expressions + # + + def _eval_expr(self, expr): + """Evaluates an expression and returns one of the tristate values "n", + "m" or "y".""" + res = self._eval_expr_2(expr) + + # Promote "m" to "y" if we're running without modules. Internally, "m" + # is often rewritten to "m" && MODULES by both the C implementation and + # kconfiglib, which takes care of cases where "m" should be false if + # we're running without modules. + if res == "m" and not self._has_modules(): + return "y" + + return res + + def _eval_expr_2(self, expr): + if expr is None: + return "y" + + if isinstance(expr, Symbol): + # Non-bool/tristate symbols are always "n" in a tristate sense, + # regardless of their value + if expr.type != BOOL and expr.type != TRISTATE: + return "n" + return expr.get_value() + + if isinstance(expr, str): + return expr if (expr == "y" or expr == "m") else "n" + + first_expr = expr[0] + + if first_expr == OR: + res = "n" + + for subexpr in expr[1]: + ev = self._eval_expr_2(subexpr) + + # Return immediately upon discovering a "y" term + if ev == "y": + return "y" + + if ev == "m": + res = "m" + + # 'res' is either "n" or "m" here; we already handled the + # short-circuiting "y" case in the loop. + return res + + if first_expr == AND: + res = "y" + + for subexpr in expr[1]: + ev = self._eval_expr_2(subexpr) + + # Return immediately upon discovering an "n" term + if ev == "n": + return "n" + + if ev == "m": + res = "m" + + # 'res' is either "m" or "y" here; we already handled the + # short-circuiting "n" case in the loop. + return res + + if first_expr == NOT: + ev = self._eval_expr_2(expr[1]) + + if ev == "y": + return "n" + + return "y" if (ev == "n") else "m" + + if first_expr == EQUAL: + return "y" if (self._get_str_value(expr[1]) == + self._get_str_value(expr[2])) else "n" + + if first_expr == UNEQUAL: + return "y" if (self._get_str_value(expr[1]) != + self._get_str_value(expr[2])) else "n" + + _internal_error("Internal error while evaluating expression: " + "unknown operation {0}.".format(first_expr)) + + def _get_str_value(self, obj): + if isinstance(obj, str): + return obj + # obj is a Symbol + return obj.get_value() + + def _eval_min(self, e1, e2): + e1_eval = self._eval_expr(e1) + e2_eval = self._eval_expr(e2) + + return e1_eval if tri_less(e1_eval, e2_eval) else e2_eval + + def _eval_max(self, e1, e2): + e1_eval = self._eval_expr(e1) + e2_eval = self._eval_expr(e2) + + return e1_eval if tri_greater(e1_eval, e2_eval) else e2_eval + + # + # Methods related to the MODULES symbol + # + + def _has_modules(self): + modules_sym = self.syms.get("MODULES") + return (modules_sym is not None) and (modules_sym.get_value() == "y") + + # + # Dependency tracking + # + + def _build_dep(self): + """Populates the Symbol.dep sets, linking the symbol to the symbols + that immediately depend on it in the sense that changing the value of + the symbol might affect the values of those other symbols. This is used + for caching/invalidation purposes. The calculated sets might be larger + than necessary as we don't do any complicated analysis of the + expressions.""" + for sym in self.syms.itervalues(): + sym.dep = set() + + # Adds 'sym' as a directly dependent symbol to all symbols that appear + # in the expression 'e' + def add_expr_deps(e, sym): + for s in _get_expr_syms(e): + s.dep.add(sym) + + # The directly dependent symbols of a symbol are: + # - Any symbols whose prompts, default values, rev_dep (select + # condition), or ranges depend on the symbol + # - Any symbols that belong to the same choice statement as the symbol + # (these won't be included in 'dep' as that makes the dependency + # graph unwieldy, but Symbol._get_dependent() will include them) + # - Any symbols in a choice statement that depends on the symbol + for sym in self.syms.itervalues(): + for (_, e) in sym.prompts: + add_expr_deps(e, sym) + + for (v, e) in sym.def_exprs: + add_expr_deps(v, sym) + add_expr_deps(e, sym) + + add_expr_deps(sym.rev_dep, sym) + + for (l, u, e) in sym.ranges: + add_expr_deps(l, sym) + add_expr_deps(u, sym) + add_expr_deps(e, sym) + + if sym.is_choice_symbol_: + choice = sym.parent + + for (_, e) in choice.prompts: + add_expr_deps(e, sym) + + for (_, e) in choice.def_exprs: + add_expr_deps(e, sym) + + def _expr_val_str(self, expr, no_value_str = "(none)", get_val_instead_of_eval = False): + # Since values are valid expressions, _expr_to_str() will get a nice + # string representation for those as well. + + if expr is None: + return no_value_str + + if get_val_instead_of_eval: + if isinstance(expr, str): + return _expr_to_str(expr) + val = expr.get_value() + else: + val = self._eval_expr(expr) + + return "{0} (value: {1})".format(_expr_to_str(expr), _expr_to_str(val)) + + def _expand_sym_refs(self, s): + """Expands $-references to symbols in 's' to symbol values, or to the + empty string for undefined symbols.""" + + while 1: + sym_ref_re_match = sym_ref_re.search(s) + if sym_ref_re_match is None: + return s + + sym_name = sym_ref_re_match.group(0)[1:] + sym = self.syms.get(sym_name) + expansion = "" if sym is None else sym.get_value() + + s = s[:sym_ref_re_match.start()] + \ + expansion + \ + s[sym_ref_re_match.end():] + + def _get_sym_or_choice_str(self, sc): + """Symbols and choices have many properties in common, so we factor out + common __str__() stuff here. "sc" is short for "symbol or choice".""" + + # As we deal a lot with string representations here, use some + # convenient shorthand: + s = _expr_to_str + + # + # Common symbol/choice properties + # + + user_value_str = "(no user value)" if sc.user_val is None else s(sc.user_val) + + visibility_str = s(sc.get_visibility()) + + # Build prompts string + if sc.prompts == []: + prompts_str = " (no prompts)" + else: + prompts_str_rows = [] + + for (prompt, cond_expr) in sc.orig_prompts: + if cond_expr is None: + prompts_str_rows.append(' "{0}"'.format(prompt)) + else: + prompts_str_rows.append(' "{0}" if '.format(prompt) + + self._expr_val_str(cond_expr)) + + prompts_str = "\n".join(prompts_str_rows) + + # Build locations string + if sc.def_locations == []: + locations_str = "(no locations)" + else: + locations_str = " ".join(["{0}:{1}".format(filename, linenr) for + (filename, linenr) in sc.def_locations]) + + # Build additional-dependencies-from-menus-and-if's string + additional_deps_str = " " + self._expr_val_str(sc.deps_from_containing, + "(no additional dependencies)") + + # + # Symbol-specific stuff + # + + if isinstance(sc, Symbol): + + # Build value string + value_str = s(sc.get_value()) + + # Build ranges string + if isinstance(sc, Symbol): + if sc.ranges == []: + ranges_str = " (no ranges)" + else: + ranges_str_rows = [] + + for (l, u, cond_expr) in sc.ranges: + if cond_expr is None: + ranges_str_rows.append(" [{0}, {1}]".format(s(l), s(u))) + else: + ranges_str_rows.append(" [{0}, {1}] if {2}" + .format(s(l), s(u), self._expr_val_str(cond_expr))) + + ranges_str = "\n".join(ranges_str_rows) + + # Build default values string + if sc.def_exprs == []: + defaults_str = " (no default values)" + else: + defaults_str_rows = [] + + for (val_expr, cond_expr) in sc.orig_def_exprs: + row_str = " " + self._expr_val_str(val_expr, "(none)", sc.type == STRING) + defaults_str_rows.append(row_str) + defaults_str_rows.append(" Condition: " + self._expr_val_str(cond_expr)) + + defaults_str = "\n".join(defaults_str_rows) + + # Build selects string + if sc.orig_selects == []: + selects_str = " (no selects)" + else: + selects_str_rows = [] + + for (target, cond_expr) in sc.orig_selects: + if cond_expr is None: + selects_str_rows.append(" {0}".format(target.name)) + else: + selects_str_rows.append(" {0} if ".format(target.name) + + self._expr_val_str(cond_expr)) + + selects_str = "\n".join(selects_str_rows) + + # Build reverse dependencies string + if sc.rev_dep == "n": + rev_dep_str = " (no reverse dependencies)" + else: + rev_dep_str = " " + self._expr_val_str(sc.rev_dep) + + res = _sep_lines("Symbol " + (sc.name if sc.name is not None else "(no name)"), + "Type : " + typename[sc.type], + "Value : " + value_str, + "User value : " + user_value_str, + "Visibility : " + visibility_str, + "Is choice item : " + bool_str[sc.is_choice_symbol_], + "Is defined : " + bool_str[sc.is_defined_], + "Is from env. : " + bool_str[sc.is_from_env], + "Is special : " + bool_str[sc.is_special_] + "\n") + + if sc.ranges != []: + res += _sep_lines("Ranges:", + ranges_str + "\n") + + res += _sep_lines("Prompts:", + prompts_str, + "Default values:", + defaults_str, + "Selects:", + selects_str, + "Reverse dependencies:", + rev_dep_str, + "Additional dependencies from enclosing menus and if's:", + additional_deps_str, + "Locations: " + locations_str) + + return res + + # + # Choice-specific stuff + # + + # Build name string (for named choices) + if sc.name is None: + name_str = "(no name)" + else: + name_str = sc.name + + # Build selected symbol string + sel = sc.get_selection() + if sel is None: + sel_str = "(no selection)" + else: + sel_str = sel.name + + # Build mode string + mode_str = s(sc.get_mode()) + + # Build default values string + if sc.def_exprs == []: + defaults_str = " (no default values)" + else: + defaults_str_rows = [] + + for (sym, cond_expr) in sc.orig_def_exprs: + if cond_expr is None: + defaults_str_rows.append(" {0}".format(sym.name)) + else: + defaults_str_rows.append(" {0} if ".format(sym.name) + + self._expr_val_str(cond_expr)) + + defaults_str = "\n".join(defaults_str_rows) + + # Build contained symbols string + names = [sym.name for sym in sc.get_symbols()] + + if names == []: + syms_string = "(empty)" + else: + syms_string = " ".join(names) + + return _sep_lines("Choice", + "Name (for named choices): " + name_str, + "Type : " + typename[sc.type], + "Selected symbol : " + sel_str, + "User value : " + user_value_str, + "Mode : " + mode_str, + "Visibility : " + visibility_str, + "Optional : " + bool_str[sc.optional], + "Prompts:", + prompts_str, + "Defaults:", + defaults_str, + "Choice symbols:", + " " + syms_string, + "Additional dependencies from enclosing menus and if's:", + additional_deps_str, + "Locations: " + locations_str) + + def _expr_depends_on(self, expr, sym): + """Reimplementation of expr_depends_symbol() from mconf.c. Used to + determine if a submenu should be implicitly created, which influences what + items inside choice statements are considered choice items.""" + if expr is None: + return False + + def rec(expr): + if isinstance(expr, str): + return False + + if isinstance(expr, Symbol): + return expr is sym + + e0 = expr[0] + + if e0 == EQUAL or e0 == UNEQUAL: + return self._eq_to_sym(expr) is sym + + if e0 == AND: + for and_expr in expr[1]: + if rec(and_expr): + return True + + return False + + return rec(expr) + + def _eq_to_sym(self, eq): + """_expr_depends_on() helper. For (in)equalities of the form sym = y/m + or sym != n, returns sym. For other (in)equalities, returns None.""" + relation, left, right = eq + + left = self._transform_n_m_y(left) + right = self._transform_n_m_y(right) + + # Make sure the symbol (if any) appears to the left + if not isinstance(left, Symbol): + left, right = right, left + + if not isinstance(left, Symbol): + return None + + if (relation == EQUAL and (right == "m" or right == "y")) or \ + (relation == UNEQUAL and right == "n"): + return left + + return None + + def _transform_n_m_y(self, item): + """_eq_to_sym() helper. Translates the symbols n, m, and y to their + string equivalents.""" + if item is self.n: + return "n" + if item is self.m: + return "m" + if item is self.y: + return "y" + return item + + def _warn(self, msg, filename = None, linenr = None): + """For printing warnings to stderr.""" + if self.print_warnings: + self._warn_or_undef_assign(msg, WARNING, filename, linenr) + + def _undef_assign(self, msg, filename = None, linenr = None): + """For printing informational messages related to assignments + to undefined variables to stderr.""" + if self.print_undef_assign: + self._warn_or_undef_assign(msg, UNDEF_ASSIGN, filename, linenr) + + def _warn_or_undef_assign(self, msg, msg_type, filename, linenr): + if filename is not None: + sys.stderr.write("{0}:".format(_clean_up_path(filename))) + if linenr is not None: + sys.stderr.write("{0}:".format(linenr)) + + if msg_type == WARNING: + sys.stderr.write("warning: ") + elif msg_type == UNDEF_ASSIGN: + sys.stderr.write("info: ") + else: + _internal_error('Internal error while printing warning: unknown warning type "{0}".' + .format(msg_type)) + + sys.stderr.write(msg + "\n") + +def _get_expr_syms(expr): + """Returns the set() of symbols appearing in expr.""" + res = set() + if expr is None: + return res + + def rec(expr): + if isinstance(expr, Symbol): + res.add(expr) + return + + if isinstance(expr, str): + return + + e0 = expr[0] + + if e0 == OR or e0 == AND: + for term in expr[1]: + rec(term) + + elif e0 == NOT: + rec(expr[1]) + + elif e0 == EQUAL or e0 == UNEQUAL: + _, v1, v2 = expr + + if isinstance(v1, Symbol): + res.add(v1) + + if isinstance(v2, Symbol): + res.add(v2) + + else: + _internal_error("Internal error while fetching symbols from an " + "expression with token stream {0}.".format(expr)) + + rec(expr) + return res + + +# +# Construction of expressions +# + +# These functions as well as the _eval_min/max() functions above equate +# None with "y", which is usually what we want, but needs to be kept in +# mind. + +def _make_or(e1, e2): + # Perform trivial simplification and avoid None's (which + # correspond to y's) + if e1 is None or e2 is None or \ + e1 == "y" or e2 == "y": + return "y" + + if e1 == "n": + return e2 + + if e2 == "n": + return e1 + + # Prefer to merge/update argument list if possible instead of creating + # a new OR node + + if isinstance(e1, tuple) and e1[0] == OR: + if isinstance(e2, tuple) and e2[0] == OR: + return (OR, e1[1] + e2[1]) + return (OR, e1[1] + [e2]) + + if isinstance(e2, tuple) and e2[0] == OR: + return (OR, e2[1] + [e1]) + + return (OR, [e1, e2]) + +# Note: returns None if e1 == e2 == None + +def _make_and(e1, e2): + if e1 == "n" or e2 == "n": + return "n" + + if e1 is None or e1 == "y": + return e2 + + if e2 is None or e2 == "y": + return e1 + + # Prefer to merge/update argument list if possible instead of creating + # a new AND node + + if isinstance(e1, tuple) and e1[0] == AND: + if isinstance(e2, tuple) and e2[0] == AND: + return (AND, e1[1] + e2[1]) + return (AND, e1[1] + [e2]) + + if isinstance(e2, tuple) and e2[0] == AND: + return (AND, e2[1] + [e1]) + + return (AND, [e1, e2]) + +# +# Constants and functions related to types, parsing, evaluation and printing, +# put globally to unclutter the Config class a bit. +# + +# Tokens +(T_OR, T_AND, T_NOT, + T_OPEN_PAREN, T_CLOSE_PAREN, + T_EQUAL, T_UNEQUAL, + T_MAINMENU, T_MENU, T_ENDMENU, + T_SOURCE, T_CHOICE, T_ENDCHOICE, + T_COMMENT, T_CONFIG, T_MENUCONFIG, + T_HELP, T_IF, T_ENDIF, T_DEPENDS, T_ON, + T_OPTIONAL, T_PROMPT, T_DEFAULT, + T_BOOL, T_TRISTATE, T_HEX, T_INT, T_STRING, + T_DEF_BOOL, T_DEF_TRISTATE, + T_SELECT, T_RANGE, T_OPTION, T_ENV, + T_DEFCONFIG_LIST, T_MODULES, T_VISIBLE) = range(0, 38) + +# Keyword to token map +keywords = { + "mainmenu" : T_MAINMENU, + "menu" : T_MENU, + "endmenu" : T_ENDMENU, + "endif" : T_ENDIF, + "endchoice" : T_ENDCHOICE, + "source" : T_SOURCE, + "choice" : T_CHOICE, + "config" : T_CONFIG, + "comment" : T_COMMENT, + "menuconfig" : T_MENUCONFIG, + "help" : T_HELP, + "if" : T_IF, + "depends" : T_DEPENDS, + "on" : T_ON, + "optional" : T_OPTIONAL, + "prompt" : T_PROMPT, + "default" : T_DEFAULT, + "bool" : T_BOOL, + "boolean" : T_BOOL, + "tristate" : T_TRISTATE, + "int" : T_INT, + "hex" : T_HEX, + "def_bool" : T_DEF_BOOL, + "def_tristate" : T_DEF_TRISTATE, + "string" : T_STRING, + "select" : T_SELECT, + "range" : T_RANGE, + "option" : T_OPTION, + "env" : T_ENV, + "defconfig_list" : T_DEFCONFIG_LIST, + "modules" : T_MODULES, + "visible" : T_VISIBLE } + +# Strings to use for True and False +bool_str = { False : "false", True : "true" } + +# Tokens after which identifier-like lexemes are treated as strings. T_CHOICE +# is included to avoid symbols being registered for named choices. +string_lex = frozenset((T_BOOL, T_TRISTATE, T_INT, T_HEX, T_STRING, T_CHOICE, + T_PROMPT, T_MENU, T_COMMENT, T_SOURCE, T_MAINMENU)) + +# Matches the initial token on a line; see _tokenize(). +initial_token_re = re.compile(r"[^\w]*(\w+)") + +# Matches an identifier/keyword optionally preceded by whitespace +id_keyword_re = re.compile(r"\s*([\w./-]+)") + +# Regular expressions for parsing .config files +set_re = re.compile(r"CONFIG_(\w+)=(.*)") +unset_re = re.compile(r"# CONFIG_(\w+) is not set") + +# Regular expression for finding $-references to symbols in strings +sym_ref_re = re.compile(r"\$[A-Za-z_]+") + +# Integers representing symbol types +UNKNOWN, BOOL, TRISTATE, STRING, HEX, INT = range(0, 6) + +# Strings to use for types +typename = { + UNKNOWN : "unknown", + BOOL : "bool", + TRISTATE : "tristate", + STRING : "string", + HEX : "hex", + INT : "int" } + +# Token to type mapping +token_to_type = { T_BOOL : BOOL, + T_TRISTATE : TRISTATE, + T_STRING : STRING, + T_INT : INT, + T_HEX : HEX } + +# Default values for symbols of different types (the value the symbol gets if +# it is not assigned a user value and none of its 'default' clauses kick in) +default_value = { BOOL : "n", + TRISTATE : "n", + STRING : "", + INT : "", + HEX : "" } + +# Indicates that no item is selected in a choice statement +NO_SELECTION = 0 + +# Integers representing expression types +OR, AND, NOT, EQUAL, UNEQUAL = range(0, 5) + +# Map from tristate values to integers +tri_to_int = { "n" : 0, "m" : 1, "y" : 2 } + +# Printing-related stuff + +op_to_str = { AND : " && ", + OR : " || ", + EQUAL : " = ", + UNEQUAL : " != " } + +precedence = { OR : 0, AND : 1, NOT : 2 } + +# Types of informational messages +WARNING = 0 +UNDEF_ASSIGN = 1 + +def _intersperse(lst, op): + """_expr_to_str() helper. Gets the string representation of each expression in lst + and produces a list where op has been inserted between the elements.""" + if lst == []: + return "" + + res = [] + + def handle_sub_expr(expr): + no_parens = isinstance(expr, (str, Symbol)) or \ + expr[0] in (EQUAL, UNEQUAL) or \ + precedence[op] <= precedence[expr[0]] + if not no_parens: + res.append("(") + res.extend(_expr_to_str_rec(expr)) + if not no_parens: + res.append(")") + + op_str = op_to_str[op] + + handle_sub_expr(lst[0]) + for expr in lst[1:]: + res.append(op_str) + handle_sub_expr(expr) + + return res + +def _expr_to_str(expr): + s = "".join(_expr_to_str_rec(expr)) + return s + +def _sym_str_string(sym_or_str): + if isinstance(sym_or_str, str): + return '"{0}"'.format(sym_or_str) + return sym_or_str.name + +def _expr_to_str_rec(expr): + if expr is None: + return [""] + + if isinstance(expr, (Symbol, str)): + return [_sym_str_string(expr)] + + e0 = expr[0] + + if e0 == OR or e0 == AND: + return _intersperse(expr[1], expr[0]) + + if e0 == NOT: + need_parens = not isinstance(expr[1], (str, Symbol)) + + res = ["!"] + if need_parens: + res.append("(") + res.extend(_expr_to_str_rec(expr[1])) + if need_parens: + res.append(")") + return res + + if e0 == EQUAL or e0 == UNEQUAL: + return [_sym_str_string(expr[1]), + op_to_str[expr[0]], + _sym_str_string(expr[2])] + +class _Block: + + """Represents a list of items (symbols, menus, choice statements and + comments) appearing at the top-level of a file or witin a menu, choice or + if statement.""" + + def __init__(self): + self.items = [] + + def get_items(self): + return self.items + + def add_item(self, item): + self.items.append(item) + + def _make_conf(self): + # Collect the substrings in a list and later use join() instead of += + # to build the final .config contents. With older Python versions, this + # yields linear instead of quadratic complexity. + strings = [] + for item in self.items: + strings.extend(item._make_conf()) + + return strings + + def add_depend_expr(self, expr): + for item in self.items: + item.add_depend_expr(expr) + +class Item(): + + """Base class for symbols and other Kconfig constructs. Subclasses are + Symbol, Choice, Menu, and Comment.""" + + def is_symbol(self): + """Returns True if the item is a symbol, otherwise False. Short for + isinstance(item, kconfiglib.Symbol).""" + return isinstance(self, Symbol) + + def is_choice(self): + """Returns True if the item is a choice, otherwise False. Short for + isinstance(item, kconfiglib.Choice).""" + return isinstance(self, Choice) + + def is_menu(self): + """Returns True if the item is a menu, otherwise False. Short for + isinstance(item, kconfiglib.Menu).""" + return isinstance(self, Menu) + + def is_comment(self): + """Returns True if the item is a comment, otherwise False. Short for + isinstance(item, kconfiglib.Comment).""" + return isinstance(self, Comment) + +class _HasVisibility(): + + """Base class for elements that have a "visibility" that acts as an upper + limit on the values a user can set for them. Subclasses are Symbol and + Choice (which supply some of the attributes).""" + + def __init__(self): + self.cached_visibility = None + self.prompts = [] + + def _invalidate(self): + self.cached_visibility = None + + def _get_visibility(self): + if self.cached_visibility is None: + vis = "n" + for (prompt, cond_expr) in self.prompts: + vis = self.config._eval_max(vis, cond_expr) + + if isinstance(self, Symbol) and self.is_choice_symbol_: + vis = self.config._eval_min(vis, self.parent._get_visibility()) + + # Promote "m" to "y" if we're dealing with a non-tristate + if vis == "m" and self.type != TRISTATE: + vis = "y" + + self.cached_visibility = vis + + return self.cached_visibility + +class Symbol(Item, _HasVisibility): + + """Represents a configuration symbol - e.g. FOO for + + config FOO + ...""" + + # + # Public interface + # + + def get_value(self): + """Calculate and return the value of the symbol. See also + Symbol.set_user_value().""" + + if self.cached_value is not None: + return self.cached_value + + self.write_to_conf = False + + # As a quirk of Kconfig, undefined symbols get their name as their + # value. This is why things like "FOO = bar" work for seeing if FOO has + # the value "bar". + if self.type == UNKNOWN: + self.cached_value = self.name + return self.name + + new_val = default_value[self.type] + + vis = self._get_visibility() + + if self.type == BOOL or self.type == TRISTATE: + # The visibility and mode (modules-only or single-selection) of + # choice items will be taken into account in self._get_visibility() + + if self.is_choice_symbol_: + if vis != "n": + choice = self.parent + mode = choice.get_mode() + + self.write_to_conf = (mode != "n") + + if mode == "y": + new_val = "y" if (choice.get_selection() is self) else "n" + elif mode == "m": + if self.user_val == "m" or self.user_val == "y": + new_val = "m" + + else: + use_defaults = True + + if vis != "n": + # If the symbol is visible and has a user value, use that. + # Otherwise, look at defaults. + self.write_to_conf = True + + if self.user_val is not None: + new_val = self.config._eval_min(self.user_val, vis) + use_defaults = False + + if use_defaults: + for (val_expr, cond_expr) in self.def_exprs: + cond_eval = self.config._eval_expr(cond_expr) + + if cond_eval != "n": + self.write_to_conf = True + new_val = self.config._eval_min(val_expr, cond_eval) + break + + # Reverse dependencies take precedence + rev_dep_val = self.config._eval_expr(self.rev_dep) + + if rev_dep_val != "n": + self.write_to_conf = True + new_val = self.config._eval_max(new_val, rev_dep_val) + + # Promote "m" to "y" for booleans + if new_val == "m" and self.type == BOOL: + new_val = "y" + + elif self.type == STRING: + use_defaults = True + + if vis != "n": + self.write_to_conf = True + if self.user_val is not None: + new_val = self.user_val + use_defaults = False + + if use_defaults: + for (val_expr, cond_expr) in self.def_exprs: + if self.config._eval_expr(cond_expr) != "n": + self.write_to_conf = True + new_val = self.config._get_str_value(val_expr) + break + + elif self.type == HEX or self.type == INT: + has_active_range = False + low = None + high = None + use_defaults = True + + base = 16 if self.type == HEX else 10 + + for(l, h, cond_expr) in self.ranges: + if self.config._eval_expr(cond_expr) != "n": + has_active_range = True + + low_str = self.config._get_str_value(l) + high_str = self.config._get_str_value(h) + + low = int(low_str, base) if \ + _is_base_n(low_str, base) else 0 + high = int(high_str, base) if \ + _is_base_n(high_str, base) else 0 + + break + + if vis != "n": + self.write_to_conf = True + + if self.user_val is not None and \ + _is_base_n(self.user_val, base) and \ + (not has_active_range or + low <= int(self.user_val, base) <= high): + + # If the user value is OK, it is stored in exactly the same + # form as specified in the assignment (with or without + # "0x", etc). + + use_defaults = False + new_val = self.user_val + + if use_defaults: + for (val_expr, cond_expr) in self.def_exprs: + if self.config._eval_expr(cond_expr) != "n": + self.write_to_conf = True + + # If the default value is OK, it is stored in exactly + # the same form as specified. Otherwise, it is clamped + # to the range, and the output has "0x" as appropriate + # for the type. + + new_val = self.config._get_str_value(val_expr) + + if _is_base_n(new_val, base): + new_val_num = int(new_val, base) + if has_active_range: + clamped_val = None + + if new_val_num < low: + clamped_val = low + elif new_val_num > high: + clamped_val = high + + if clamped_val is not None: + new_val = (hex(clamped_val) if \ + self.type == HEX else str(clamped_val)) + + break + else: # For the for loop + # If no user value or default kicks in but the hex/int has + # an active range, then the low end of the range is used, + # provided it's > 0, with "0x" prepended as appropriate. + + if has_active_range and low > 0: + new_val = (hex(low) if self.type == HEX else str(low)) + + self.cached_value = new_val + return new_val + + def set_user_value(self, v): + """Sets the user value of the symbol. + + Equal in effect to assigning the value to the symbol within a .config + file. Use get_lower/upper_bound() or get_assignable_values() to find + the range of currently assignable values for bool and tristate symbols; + setting values outside this range will cause the user value to differ + from the result of Symbol.get_value() (be truncated). Values that are + invalid for the type (such as a_bool.set_user_value("foo")) are + ignored, and a warning is emitted if an attempt is made to assign such + a value. + + For any type of symbol, is_modifiable() can be used to check if a user + value will currently have any effect on the symbol, as determined by + its visibility and range of assignable values. Any value that is valid + for the type (bool, tristate, etc.) will end up being reflected in + get_user_value() though, and might have an effect later if conditions + change. To get rid of the user value, use unset_user_value(). + + Any symbols dependent on the symbol are (recursively) invalidated, so + things will just work with regards to dependencies. + + v -- The user value to give to the symbol.""" + self._set_user_value_no_invalidate(v, False) + + # There might be something more efficient you could do here, but play + # it safe. + if self.name == "MODULES": + self.config._invalidate_all() + return + + self._invalidate() + self._invalidate_dependent() + + def unset_user_value(self): + """Resets the user value of the symbol, as if the symbol had never + gotten a user value via Config.load_config() or + Symbol.set_user_value().""" + self._unset_user_value_no_recursive_invalidate() + self._invalidate_dependent() + + def get_user_value(self): + """Returns the value assigned to the symbol in a .config or via + Symbol.set_user_value() (provided the value was valid for the type of the + symbol). Returns None in case of no user value.""" + return self.user_val + + def get_name(self): + """Returns the name of the symbol.""" + return self.name + + def get_prompts(self): + """Returns a list of prompts defined for the symbol, in the order they + appear in the configuration files. Returns the empty list for symbols + with no prompt. + + This list will have a single entry for the vast majority of symbols + having prompts, but having multiple prompts for a single symbol is + possible through having multiple 'config' entries for it.""" + return [prompt for prompt, _ in self.orig_prompts] + + def get_upper_bound(self): + """For string/hex/int symbols and for bool and tristate symbols that + cannot be modified (see is_modifiable()), returns None. + + Otherwise, returns the highest value the symbol can be set to with + Symbol.set_user_value() (that will not be truncated): one of "m" or "y", + arranged from lowest to highest. This corresponds to the highest value + the symbol could be given in e.g. the 'make menuconfig' interface. + + See also the tri_less*() and tri_greater*() functions, which could come + in handy.""" + if self.type != BOOL and self.type != TRISTATE: + return None + rev_dep = self.config._eval_expr(self.rev_dep) + # A bool selected to "m" gets promoted to "y" + if self.type == BOOL and rev_dep == "m": + rev_dep = "y" + vis = self._get_visibility() + if (tri_to_int[vis] - tri_to_int[rev_dep]) > 0: + return vis + return None + + def get_lower_bound(self): + """For string/hex/int symbols and for bool and tristate symbols that + cannot be modified (see is_modifiable()), returns None. + + Otherwise, returns the lowest value the symbol can be set to with + Symbol.set_user_value() (that will not be truncated): one of "n" or "m", + arranged from lowest to highest. This corresponds to the lowest value + the symbol could be given in e.g. the 'make menuconfig' interface. + + See also the tri_less*() and tri_greater*() functions, which could come + in handy.""" + if self.type != BOOL and self.type != TRISTATE: + return None + rev_dep = self.config._eval_expr(self.rev_dep) + # A bool selected to "m" gets promoted to "y" + if self.type == BOOL and rev_dep == "m": + rev_dep = "y" + if (tri_to_int[self._get_visibility()] - tri_to_int[rev_dep]) > 0: + return rev_dep + return None + + def get_assignable_values(self): + """For string/hex/int symbols and for bool and tristate symbols that + cannot be modified (see is_modifiable()), returns the empty list. + + Otherwise, returns a list containing the user values that can be + assigned to the symbol (that won't be truncated). Usage example: + + if "m" in sym.get_assignable_values(): + sym.set_user_value("m") + + This is basically a more convenient interface to + get_lower/upper_bound() when wanting to test if a particular tristate + value can be assigned.""" + if self.type != BOOL and self.type != TRISTATE: + return [] + rev_dep = self.config._eval_expr(self.rev_dep) + # A bool selected to "m" gets promoted to "y" + if self.type == BOOL and rev_dep == "m": + rev_dep = "y" + res = ["n", "m", "y"][tri_to_int[rev_dep] : + tri_to_int[self._get_visibility()] + 1] + return res if len(res) > 1 else [] + + def get_type(self): + """Returns the type of the symbol: one of UNKNOWN, BOOL, TRISTATE, + STRING, HEX, or INT. These are defined at the top level of the module, + so you'd do something like + + if sym.get_type() == kconfiglib.STRING: + ...""" + return self.type + + def get_visibility(self): + """Returns the visibility of the symbol: one of "n", "m" or "y". For + bool and tristate symbols, this is an upper bound on the value users + can set for the symbol. For other types of symbols, a visibility of "n" + means the user value will be ignored. A visibility of "n" corresponds + to not being visible in the 'make *config' interfaces. + + Example (assuming we're running with modules enabled -- i.e., MODULES + set to 'y'): + + # Assume this has been assigned 'n' + config N_SYM + tristate "N_SYM" + + # Assume this has been assigned 'm' + config M_SYM + tristate "M_SYM" + + # Has visibility 'n' + config A + tristate "A" + depends on N_SYM + + # Has visibility 'm' + config B + tristate "B" + depends on M_SYM + + # Has visibility 'y' + config C + tristate "C" + + # Has no prompt, and hence visibility 'n' + config D + tristate + + Having visibility be tri-valued ensures that e.g. a symbol cannot be + set to "y" by the user if it depends on a symbol with value "m", which + wouldn't be safe. + + You should probably look at get_lower/upper_bound(), + get_assignable_values() and is_modifiable() before using this.""" + return self._get_visibility() + + def get_parent(self): + """Returns the menu or choice statement that contains the symbol, or + None if the symbol is at the top level. Note that if statements are + treated as syntactic and do not have an explicit class + representation.""" + return self.parent + + def get_referenced_symbols(self, refs_from_enclosing = False): + """Returns the set() of all symbols referenced by this symbol. For + example, the symbol defined by + + config FOO + bool + prompt "foo" if A && B + default C if D + depends on E + select F if G + + references the symbols A through G. + + refs_from_enclosing (default: False) -- If True, the symbols + referenced by enclosing menus and if's will be + included in the result.""" + return self.all_referenced_syms if refs_from_enclosing else self.referenced_syms + + def get_selected_symbols(self): + """Returns the set() of all symbols X for which this symbol has a + 'select X' or 'select X if Y' (regardless of whether Y is satisfied or + not). This is a subset of the symbols returned by + get_referenced_symbols().""" + return self.selected_syms + + def get_help(self): + """Returns the help text of the symbol, or None if the symbol has no + help text.""" + return self.help + + def get_config(self): + """Returns the Config instance this symbol is from.""" + return self.config + + def get_def_locations(self): + """Returns a list of (filename, linenr) tuples, where filename (string) + and linenr (int) represent a location where the symbol is defined. For + the vast majority of symbols this list will only contain one element. + For the following Kconfig, FOO would get two entries: the lines marked + with *. + + config FOO * + bool "foo prompt 1" + + config FOO * + bool "foo prompt 2" + """ + return self.def_locations + + def get_ref_locations(self): + """Returns a list of (filename, linenr) tuples, where filename (string) + and linenr (int) represent a location where the symbol is referenced in + the configuration. For example, the lines marked by * would be included + for FOO below: + + config A + bool + default BAR || FOO * + + config B + tristate + depends on FOO * + default m if FOO * + + if FOO * + config A + bool "A" + endif + + config FOO (definition not included) + bool + """ + return self.ref_locations + + def is_modifiable(self): + """Returns True if the value of the symbol could be modified by calling + Symbol.set_user_value() and False otherwise. + + For bools and tristates, this corresponds to the symbol being visible + in the 'make menuconfig' interface and not already being pinned to a + specific value (e.g. because it is selected by another symbol). + + For strings and numbers, this corresponds to just being visible. (See + Symbol.get_visibility().)""" + if self.is_special_: + return False + if self.type == BOOL or self.type == TRISTATE: + rev_dep = self.config._eval_expr(self.rev_dep) + # A bool selected to "m" gets promoted to "y" + if self.type == BOOL and rev_dep == "m": + rev_dep = "y" + return (tri_to_int[self._get_visibility()] - + tri_to_int[rev_dep]) > 0 + return self._get_visibility() != "n" + + def is_defined(self): + """Returns False if the symbol is referred to in the Kconfig but never + actually defined, otherwise True.""" + return self.is_defined_ + + def is_special(self): + """Returns True if the symbol is one of the special symbols n, m, y, or + UNAME_RELEASE, or gets its value from the environment. Otherwise, + returns False.""" + return self.is_special_ + + def is_from_environment(self): + """Returns True if the symbol gets its value from the environment. + Otherwise, returns False.""" + return self.is_from_env + + def has_ranges(self): + """Returns True if the symbol is of type INT or HEX and has ranges that + limits what values it can take on, otherwise False.""" + return self.ranges != [] + + def is_choice_symbol(self): + """Returns True if the symbol is in a choice statement and is an actual + choice symbol (see Choice.get_symbols()); otherwise, returns + False.""" + return self.is_choice_symbol_ + + def is_choice_selection(self): + """Returns True if the symbol is contained in a choice statement and is + the selected item, otherwise False. Equivalent to 'sym.is_choice_symbol() + and sym.get_parent().get_selection() is sym'.""" + return self.is_choice_symbol_ and self.parent.get_selection() is self + + def __str__(self): + """Returns a string containing various information about the symbol.""" + return self.config._get_sym_or_choice_str(self) + + # + # Private methods + # + + def __init__(self): + """Symbol constructor -- not intended to be called directly by + kconfiglib clients.""" + + # Set default values + _HasVisibility.__init__(self) + + self.config = None + + self.parent = None + self.name = None + self.type = UNKNOWN + + self.def_exprs = [] + self.ranges = [] + self.rev_dep = "n" + + # The prompt, default value and select conditions without any + # dependencies from menus or if's propagated to them + + self.orig_prompts = [] + self.orig_def_exprs = [] + self.orig_selects = [] + + # Dependencies inherited from containing menus and if's + self.deps_from_containing = None + + self.help = None + + # The set of symbols referenced by this symbol (see + # get_referenced_symbols()) + self.referenced_syms = set() + + # The set of symbols selected by this symbol (see + # get_selected_symbols()) + self.selected_syms = set() + + # Like 'referenced_syms', but includes symbols from + # dependencies inherited from enclosing menus and if's + self.all_referenced_syms = set() + + # This is set to True for "actual" choice symbols. See + # Choice._determine_actual_symbols(). The trailing underscore avoids a + # collision with is_choice_symbol(). + self.is_choice_symbol_ = False + + # This records only dependencies specified with 'depends on'. Needed + # when determining actual choice items (hrrrr...). See also + # Choice._determine_actual_symbols(). + self.menu_dep = None + + # See Symbol.get_ref/def_locations(). + self.def_locations = [] + self.ref_locations = [] + + self.user_val = None + + # Flags + + # Should the symbol get an entry in .config? + self.write_to_conf = False + + # Caches the calculated value + self.cached_value = None + + # Note: An instance variable 'self.dep' gets set on the Symbol in + # Config._build_dep(), linking the symbol to the symbols that + # immediately depend on it (in a caching/invalidation sense). The total + # set of dependent symbols for the symbol (the transitive closure) is + # calculated on an as-needed basis in _get_dependent(). + + # Caches the total list of dependent symbols. Calculated in + # _get_dependent(). + self.cached_deps = None + + # Does the symbol have an entry in the Kconfig file? The trailing + # underscore avoids a collision with is_defined(). + self.is_defined_ = False + + # Does the symbol get its value in some special way, e.g. from the + # environment or by being one of the special symbols n, m, and y? If + # so, the value is stored in self.cached_value, which is never + # invalidated. The trailing underscore avoids a collision with + # is_special(). + self.is_special_ = False + + # Does the symbol get its value from the environment? + self.is_from_env = False + + def _invalidate(self): + if self.is_special_: + return + + if self.is_choice_symbol_: + self.parent._invalidate() + + _HasVisibility._invalidate(self) + + self.write_to_conf = False + self.cached_value = None + + def _invalidate_dependent(self): + for sym in self._get_dependent(): + sym._invalidate() + + def _set_user_value_no_invalidate(self, v, suppress_load_warnings): + """Like set_user_value(), but does not invalidate any symbols. + + suppress_load_warnings -- + some warnings are annoying when loading a .config that can be helpful + when manually invoking set_user_value(). This flag is set to True to + suppress such warnings. + + Perhaps this could be made optional for load_config() instead.""" + + if self.is_special_: + if self.is_from_env: + self.config._warn('attempt to assign the value "{0}" to the ' + 'symbol {1}, which gets its value from the ' + 'environment. Assignment ignored.' + .format(v, self.name)) + else: + self.config._warn('attempt to assign the value "{0}" to the ' + 'special symbol {1}. Assignment ignored.' + .format(v, self.name)) + + return + + + if not self.is_defined_: + filename, linenr = self.ref_locations[0] + + self.config._undef_assign('attempt to assign the value "{0}" to {1}, ' + "which is referenced at {2}:{3} but never " + "defined. Assignment ignored." + .format(v, self.name, filename, linenr)) + return + + # Check if the value is valid for our type + + if not (( self.type == BOOL and (v == "n" or v == "y") ) or + ( self.type == TRISTATE and (v == "n" or v == "m" or + v == "y") ) or + ( self.type == STRING ) or + ( self.type == INT and _is_base_n(v, 10) ) or + ( self.type == HEX and _is_base_n(v, 16) )): + + self.config._warn('the value "{0}" is invalid for {1}, which has type {2}. ' + "Assignment ignored." + .format(v, self.name, typename[self.type])) + return + + if self.prompts == [] and not suppress_load_warnings: + self.config._warn('assigning "{0}" to the symbol {1} which ' + 'lacks prompts and thus has visibility "n". ' + 'The assignment will have no effect.' + .format(v, self.name)) + + self.user_val = v + + if self.is_choice_symbol_ and (self.type == BOOL or + self.type == TRISTATE): + choice = self.parent + if v == "y": + choice.user_val = self + choice.user_mode = "y" + elif v == "m": + choice.user_val = None + choice.user_mode = "m" + + def _unset_user_value_no_recursive_invalidate(self): + self._invalidate() + self.user_val = None + + if self.is_choice_symbol_: + self.parent._unset_user_value() + + def _make_conf(self): + if self.already_written: + return [] + + self.already_written = True + + # Note: write_to_conf is determined in get_value() + val = self.get_value() + if not self.write_to_conf: + return [] + + if self.type == BOOL or self.type == TRISTATE: + if val == "m" or val == "y": + return ["CONFIG_{0}={1}".format(self.name, val)] + return ["# CONFIG_{0} is not set".format(self.name)] + + elif self.type == STRING: + # Escape \ and " + return ['CONFIG_{0}="{1}"' + .format(self.name, + val.replace("\\", "\\\\").replace('"', '\\"'))] + + elif self.type == INT or self.type == HEX: + return ["CONFIG_{0}={1}".format(self.name, val)] + + else: + _internal_error('Internal error while creating .config: unknown type "{0}".' + .format(self.type)) + + def _get_dependent(self): + """Returns the set of symbols that should be invalidated if the value + of the symbol changes, because they might be affected by the change. + Note that this is an internal API -- it's probably of limited + usefulness to clients.""" + if self.cached_deps is not None: + return self.cached_deps + + res = set() + + self._add_dependent_ignore_siblings(res) + if self.is_choice_symbol_: + for s in self.parent.get_symbols(): + if s is not self: + res.add(s) + s._add_dependent_ignore_siblings(res) + + self.cached_deps = res + return res + + def _add_dependent_ignore_siblings(self, to): + """Calculating dependencies gets a bit tricky for choice items as they + all depend on each other, potentially leading to infinite recursion. + This helper function calculates dependencies ignoring the other symbols + in the choice. It also works fine for symbols that are not choice + items.""" + for s in self.dep: + to.add(s) + to |= s._get_dependent() + + def _has_auto_menu_dep_on(self, on): + """See Choice._determine_actual_symbols().""" + if not isinstance(self.parent, Choice): + _internal_error("Attempt to determine auto menu dependency for symbol ouside of choice.") + + if self.prompts == []: + # If we have no prompt, use the menu dependencies instead (what was + # specified with 'depends on') + return self.menu_dep is not None and \ + self.config._expr_depends_on(self.menu_dep, on) + + for (_, cond_expr) in self.prompts: + if self.config._expr_depends_on(cond_expr, on): + return True + + return False + +class Menu(Item): + + """Represents a menu statement.""" + + # + # Public interface + # + + def get_config(self): + """Return the Config instance this menu is from.""" + return self.config + + def get_visibility(self): + """Returns the visibility of the menu. This also affects the visibility + of subitems. See also Symbol.get_visibility().""" + return self.config._eval_expr(self.dep_expr) + + def get_visible_if_visibility(self): + """Returns the visibility the menu gets from its 'visible if' + condition. "y" if the menu has no 'visible if' condition.""" + return self.config._eval_expr(self.visible_if_expr) + + def get_items(self, recursive = False): + """Returns a list containing the items (symbols, menus, choice + statements and comments) in in the menu, in the same order that the + items appear within the menu. + + recursive (default: False) -- True if items contained in items within + the menu should be included + recursively (preorder).""" + + if not recursive: + return self.block.get_items() + + res = [] + for item in self.block.get_items(): + res.append(item) + if isinstance(item, Menu): + res.extend(item.get_items(True)) + elif isinstance(item, Choice): + res.extend(item.get_items()) + return res + + def get_symbols(self, recursive = False): + """Returns a list containing the symbols in the menu, in the same order + that they appear within the menu. + + recursive (default: False) -- True if symbols contained in items within + the menu should be included + recursively.""" + + return [item for item in self.get_items(recursive) if isinstance(item, Symbol)] + + def get_title(self): + """Returns the title text of the menu.""" + return self.title + + def get_parent(self): + """Returns the menu or choice statement that contains the menu, or + None if the menu is at the top level. Note that if statements are + treated as syntactic sugar and do not have an explicit class + representation.""" + return self.parent + + def get_referenced_symbols(self, refs_from_enclosing = False): + """See Symbol.get_referenced_symbols().""" + return self.all_referenced_syms if refs_from_enclosing else self.referenced_syms + + def get_location(self): + """Returns the location of the menu as a (filename, linenr) tuple, + where filename is a string and linenr an int.""" + return (self.filename, self.linenr) + + def __str__(self): + """Returns a string containing various information about the menu.""" + depends_on_str = self.config._expr_val_str(self.orig_deps, + "(no dependencies)") + visible_if_str = self.config._expr_val_str(self.visible_if_expr, + "(no dependencies)") + + additional_deps_str = " " + self.config._expr_val_str(self.deps_from_containing, + "(no additional dependencies)") + + return _sep_lines("Menu", + "Title : " + self.title, + "'depends on' dependencies : " + depends_on_str, + "'visible if' dependencies : " + visible_if_str, + "Additional dependencies from enclosing menus and if's:", + additional_deps_str, + "Location: {0}:{1}".format(self.filename, self.linenr)) + + # + # Private methods + # + + def __init__(self): + """Menu constructor -- not intended to be called directly by + kconfiglib clients.""" + + self.config = None + + self.parent = None + self.title = None + self.block = None + self.dep_expr = None + + # Dependency expression without dependencies from enclosing menus and + # if's propagated + self.orig_deps = None + + # Dependencies inherited from containing menus and if's + self.deps_from_containing = None + + # The 'visible if' expression + self.visible_if_expr = None + + # The set of symbols referenced by this menu (see + # get_referenced_symbols()) + self.referenced_syms = set() + + # Like 'referenced_syms', but includes symbols from + # dependencies inherited from enclosing menus and if's + self.all_referenced_syms = None + + self.filename = None + self.linenr = None + + def _make_conf(self): + item_conf = self.block._make_conf() + + if self.config._eval_expr(self.dep_expr) != "n" and \ + self.config._eval_expr(self.visible_if_expr) != "n": + return ["\n#\n# {0}\n#".format(self.title)] + item_conf + return item_conf + +class Choice(Item, _HasVisibility): + + """Represents a choice statement. A choice can be in one of three modes: + + "n" - The choice is not visible and no symbols can be selected. + + "m" - Any number of symbols can be set to "m". The rest will be "n". This + is safe since potentially conflicting options don't actually get + compiled into the kernel simultaneously with "m". + + "y" - One symbol will be "y" while the rest are "n". + + Only tristate choices can be in "m" mode, and the visibility of the choice + is an upper bound on the mode, so that e.g. a choice that depends on a + symbol with value "m" will be in "m" mode. + + The mode changes automatically when a value is assigned to a symbol within + the choice. + + See Symbol.get_visibility() too.""" + + # + # Public interface + # + + def get_selection(self): + """Returns the symbol selected (either by the user or through + defaults), or None if either no symbol is selected or the mode is not + "y".""" + if self.cached_selection is not None: + if self.cached_selection == NO_SELECTION: + return None + return self.cached_selection + + if self.get_mode() != "y": + return self._cache_ret(None) + + # User choice available? + if self.user_val is not None and \ + self.user_val._get_visibility() == "y": + return self._cache_ret(self.user_val) + + if self.optional: + return self._cache_ret(None) + + return self._cache_ret(self.get_selection_from_defaults()) + + def get_selection_from_defaults(self): + """Like Choice.get_selection(), but acts as if no symbol has been + selected by the user and no 'optional' flag is in effect.""" + + if self.actual_symbols == []: + return None + + for (symbol, cond_expr) in self.def_exprs: + if self.config._eval_expr(cond_expr) != "n": + chosen_symbol = symbol + break + else: + chosen_symbol = self.actual_symbols[0] + + # Is the chosen symbol visible? + if chosen_symbol._get_visibility() != "n": + return chosen_symbol + # Otherwise, pick the first visible symbol + for sym in self.actual_symbols: + if sym._get_visibility() != "n": + return sym + return None + + def get_user_selection(self): + """If the choice is in "y" mode and has a user-selected symbol, returns + that symbol. Otherwise, returns None.""" + return self.user_val + + def get_config(self): + """Returns the Config instance this choice is from.""" + return self.config + + def get_name(self): + """For named choices, returns the name. Returns None for unnamed + choices. No named choices appear anywhere in the kernel Kconfig files + as of Linux 3.7.0-rc8.""" + return self.name + + def get_prompts(self): + """Returns a list of prompts defined for the choice, in the order they + appear in the configuration files. Returns the empty list for choices + with no prompt. + + This list will have a single entry for the vast majority of choices + having prompts, but having multiple prompts for a single choice is + possible through having multiple 'choice' entries for it (though I'm + not sure if that ever happens in practice).""" + return [prompt for prompt, _ in self.orig_prompts] + + def get_help(self): + """Returns the help text of the choice, or None if the choice has no + help text.""" + return self.help + + def get_type(self): + """Returns the type of the choice. See Symbol.get_type().""" + return self.type + + def get_items(self): + """Gets all items contained in the choice in the same order as within + the configuration ("items" instead of "symbols" since choices and + comments might appear within choices. This only happens in one place as + of Linux 3.7.0-rc8, in drivers/usb/gadget/Kconfig).""" + return self.block.get_items() + + def get_symbols(self): + """Returns a list containing the choice's symbols. + + A quirk (perhaps a bug) of Kconfig is that you can put items within a + choice that will not be considered members of the choice insofar as + selection is concerned. This happens for example if one symbol within a + choice 'depends on' the symbol preceding it, or if you put non-symbol + items within choices. + + As of Linux 3.7.0-rc8, this seems to be used intentionally in one + place: drivers/usb/gadget/Kconfig. + + This function returns the "proper" symbols of the choice in the order + they appear in the choice, excluding such items. If you want all items + in the choice, use get_items().""" + return self.actual_symbols + + def get_parent(self): + """Returns the menu or choice statement that contains the choice, or + None if the choice is at the top level. Note that if statements are + treated as syntactic sugar and do not have an explicit class + representation.""" + return self.parent + + def get_referenced_symbols(self, refs_from_enclosing = False): + """See Symbol.get_referenced_symbols().""" + return self.all_referenced_syms if refs_from_enclosing else self.referenced_syms + + def get_def_locations(self): + """Returns a list of (filename, linenr) tuples, where filename (string) + and linenr (int) represent a location where the choice is defined. For + the vast majority of choices (all of them as of Linux 3.7.0-rc8) this + list will only contain one element, but its possible for named choices + to be defined in multiple locations.""" + return self.def_locations + + def get_visibility(self): + """Returns the visibility of the choice statement: one of "n", "m" or + "y". This acts as an upper limit on the mode of the choice (though bool + choices can only have the mode "y"). See the class documentation for an + explanation of modes.""" + return self._get_visibility() + + def get_mode(self): + """Returns the mode of the choice. See the class documentation for + an explanation of modes.""" + minimum_mode = "n" if self.optional else "m" + mode = self.user_mode if self.user_mode is not None else minimum_mode + mode = self.config._eval_min(mode, self._get_visibility()) + + # Promote "m" to "y" for boolean choices + if mode == "m" and self.type == BOOL: + return "y" + + return mode + + def is_optional(self): + """Returns True if the symbol has the optional flag set (and so will default + to "n" mode). Otherwise, returns False.""" + return self.optional + + def __str__(self): + """Returns a string containing various information about the choice + statement.""" + return self.config._get_sym_or_choice_str(self) + + # + # Private methods + # + + def __init__(self): + """Choice constructor -- not intended to be called directly by + kconfiglib clients.""" + + _HasVisibility.__init__(self) + + self.config = None + + self.parent = None + self.name = None # Yes, choices can be named + self.type = UNKNOWN + self.def_exprs = [] + self.help = None + self.optional = False + self.block = None + + # The prompts and default values without any dependencies from + # enclosing menus or if's propagated + + self.orig_prompts = [] + self.orig_def_exprs = [] + + # Dependencies inherited from containing menus and if's + self.deps_from_containing = None + + # We need to filter out symbols that appear within the choice block but + # are not considered choice items (see + # Choice._determine_actual_symbols()) This list holds the "actual" choice + # items. + self.actual_symbols = [] + + # The set of symbols referenced by this choice (see + # get_referenced_symbols()) + self.referenced_syms = set() + + # Like 'referenced_syms', but includes symbols from + # dependencies inherited from enclosing menus and if's + self.all_referenced_syms = set() + + # See Choice.get_def_locations() + self.def_locations = [] + + self.user_val = None + self.user_mode = None + + self.cached_selection = None + + def _determine_actual_symbols(self): + """If a symbol's visibility depends on the preceding symbol within a + choice, it is no longer viewed as a choice item (quite possibly a bug, + but some things consciously use it.. ugh. It stems from automatic + submenu creation). In addition, it's possible to have choices and + comments within choices, and those shouldn't be considered as choice + items either. Only drivers/usb/gadget/Kconfig seems to depend on any of + this. This method computes the "actual" items in the choice and sets + the is_choice_symbol_ flag on them (retrieved via is_choice_symbol()). + + Don't let this scare you: an earlier version simply checked for a + sequence of symbols where all symbols after the first appeared in the + 'depends on' expression of the first, and that worked fine. The added + complexity is to be future-proof in the event that + drivers/usb/gadget/Kconfig turns even more sinister. It might very well + be overkilling things (especially if that file is refactored ;).""" + + items = self.block.get_items() + + # Items might depend on each other in a tree structure, so we need a + # stack to keep track of the current tentative parent + stack = [] + + for item in items: + if not isinstance(item, Symbol): + stack = [] + continue + + while stack != []: + if item._has_auto_menu_dep_on(stack[-1]): + # The item should not be viewed as a choice item, so don't + # set item.is_choice_symbol_. + stack.append(item) + break + else: + stack.pop() + else: + item.is_choice_symbol_ = True + self.actual_symbols.append(item) + stack.append(item) + + def _cache_ret(self, selection): + # As None is used to indicate the lack of a cached value we can't use + # that to cache the fact that the choice has no selection. Instead, we + # use the symbolic constant NO_SELECTION. + if selection is None: + self.cached_selection = NO_SELECTION + else: + self.cached_selection = selection + + return selection + + def _invalidate(self): + _HasVisibility._invalidate(self) + self.cached_selection = None + + def _unset_user_value(self): + self._invalidate() + self.user_val = None + self.user_mode = None + + def _make_conf(self): + return self.block._make_conf() + +class Comment(Item): + + """Represents a comment statement.""" + + # + # Public interface + # + + def get_config(self): + """Returns the Config instance this comment is from.""" + return self.config + + def get_visibility(self): + """Returns the visibility of the comment. See also + Symbol.get_visibility().""" + return self.config._eval_expr(self.dep_expr) + + def get_text(self): + """Returns the text of the comment.""" + return self.text + + def get_parent(self): + """Returns the menu or choice statement that contains the comment, or + None if the comment is at the top level. Note that if statements are + treated as syntactic sugar and do not have an explicit class + representation.""" + return self.parent + + def get_referenced_symbols(self, refs_from_enclosing = False): + """See Symbol.get_referenced_symbols().""" + return self.all_referenced_syms if refs_from_enclosing else self.referenced_syms + + def get_location(self): + """Returns the location of the comment as a (filename, linenr) tuple, + where filename is a string and linenr an int.""" + return (self.filename, self.linenr) + + def __str__(self): + """Returns a string containing various information about the comment.""" + dep_str = self.config._expr_val_str(self.orig_deps, "(no dependencies)") + + additional_deps_str = " " + self.config._expr_val_str(self.deps_from_containing, + "(no additional dependencies)") + + return _sep_lines("Comment", + "Text: " + str(self.text), + "Dependencies: " + dep_str, + "Additional dependencies from enclosing menus and if's:", + additional_deps_str, + "Location: {0}:{1}".format(self.filename, self.linenr)) + + # + # Private methods + # + + def __init__(self): + """Comment constructor -- not intended to be called directly by + kconfiglib clients.""" + + self.config = None + + self.parent = None + self.text = None + self.dep_expr = None + + # Dependency expression without dependencies from enclosing menus and + # if's propagated + self.orig_deps = None + + # Dependencies inherited from containing menus and if's + self.deps_from_containing = None + + # The set of symbols referenced by this comment (see + # get_referenced_symbols()) + self.referenced_syms = set() + + # Like 'referenced_syms', but includes symbols from + # dependencies inherited from enclosing menus and if's + self.all_referenced_syms = None + + self.filename = None + self.linenr = None + + def _make_conf(self): + if self.config._eval_expr(self.dep_expr) != "n": + return ["\n#\n# {0}\n#".format(self.text)] + return [] + +class _Feed: + + """Class for working with sequences in a stream-like fashion; handy for tokens.""" + + def __init__(self, items): + self.items = items + self.length = len(self.items) + self.i = 0 + + def get_next(self): + if self.i >= self.length: + return None + + item = self.items[self.i] + self.i += 1 + return item + + def peek_next(self): + return None if self.i >= self.length else self.items[self.i] + + def go_to_start(self): + self.i = 0 + + def __getitem__(self, index): + return self.items[index] + + def __len__(self): + return len(self.items) + + def is_empty(self): + return self.items == [] + + def check(self, token): + """Check if the next token is 'token'. If so, remove it from the token + feed and return True. Otherwise, leave it in and return False.""" + if self.i >= self.length: + return None + + if self.items[self.i] == token: + self.i += 1 + return True + + return False + + def remove_while(self, pred): + while self.i < self.length and pred(self.items[self.i]): + self.i += 1 + + def go_back(self): + if self.i <= 0: + _internal_error("Attempt to move back in Feed while already at the beginning.") + self.i -= 1 + +class _FileFeed(_Feed): + + """Feed subclass that keeps track of the current filename and line + number.""" + + def __init__(self, lines, filename): + self.filename = _clean_up_path(filename) + _Feed.__init__(self, lines) + + def get_filename(self): + return self.filename + + def get_linenr(self): + return self.i + +# +# Misc. public global utility functions +# + +def tri_less(v1, v2): + """Returns True if the tristate v1 is less than the tristate v2, where "n", + "m" and "y" are ordered from lowest to highest. Otherwise, returns + False.""" + return tri_to_int[v1] < tri_to_int[v2] + +def tri_less_eq(v1, v2): + """Returns True if the tristate v1 is less than or equal to the tristate + v2, where "n", "m" and "y" are ordered from lowest to highest. Otherwise, + returns False.""" + return tri_to_int[v1] <= tri_to_int[v2] + +def tri_greater(v1, v2): + """Returns True if the tristate v1 is greater than the tristate v2, where + "n", "m" and "y" are ordered from lowest to highest. Otherwise, returns + False.""" + return tri_to_int[v1] > tri_to_int[v2] + +def tri_greater_eq(v1, v2): + """Returns True if the tristate v1 is greater than or equal to the tristate + v2, where "n", "m" and "y" are ordered from lowest to highest. Otherwise, + returns False.""" + return tri_to_int[v1] >= tri_to_int[v2] + +# +# Helper functions, mostly related to text processing +# + +def _strip_quotes(s, line, filename, linenr): + """Removes any quotes surrounding 's' if it has them; otherwise returns 's' + unmodified.""" + s = s.strip() + if not s: + return "" + if s[0] == '"' or s[0] == "'": + if len(s) < 2 or s[-1] != s[0]: + _parse_error(line, + "malformed string literal", + filename, + linenr) + return s[1:-1] + return s + +def _indentation(line): + """Returns the indentation of the line, treating tab stops as being spaced + 8 characters apart.""" + if line.isspace(): + _internal_error("Attempt to take indentation of blank line.") + indent = 0 + for c in line: + if c == " ": + indent += 1 + elif c == "\t": + # Go to the next tab stop + indent = (indent + 8) & ~7 + else: + return indent + +def _deindent(line, indent): + """Deindent 'line' by 'indent' spaces.""" + line = line.expandtabs() + if len(line) <= indent: + return line + return line[indent:] + +def _is_base_n(s, n): + try: + int(s, n) + return True + except ValueError: + return False + +def _sep_lines(*args): + """Returns a string comprised of all arguments, with newlines inserted + between them.""" + return "\n".join(args) + +def _comment(s): + """Returns a new string with "#" inserted before each line in 's'.""" + if not s: + return "#" + res = "".join(["#" + line for line in s.splitlines(True)]) + if s.endswith("\n"): + return res + "#" + return res + +def _get_lines(filename): + """Returns a list of lines from 'filename', joining any line ending in \\ + with the following line.""" + with open(filename, "r") as f: + lines = [] + accum = "" + while 1: + line = f.readline() + + if line == "": + return lines + + if line.endswith("\\\n"): + accum += line[:-2] + else: + accum += line + lines.append(accum) + accum = "" + +def _strip_trailing_slash(path): + """Removes any trailing slash from 'path'.""" + return path[:-1] if path.endswith("/") else path + +def _clean_up_path(path): + """Strips any initial "./" and trailing slash from 'path'.""" + if path.startswith("./"): + path = path[2:] + return _strip_trailing_slash(path) + +# +# Error handling +# + +class Kconfig_Syntax_Error(Exception): + """Exception raised for syntax errors.""" + pass + +class Internal_Error(Exception): + """Exception raised for internal errors.""" + pass + +def _tokenization_error(s, index, filename, linenr): + if filename is not None: + assert linenr is not None + sys.stderr.write("{0}:{1}:\n".format(filename, linenr)) + + if s.endswith("\n"): + s = s[:-1] + + # Calculate the visual offset corresponding to index 'index' in 's' + # assuming tabstops are spaced 8 characters apart + vis_index = 0 + for c in s[:index]: + if c == "\t": + vis_index = (vis_index + 8) & ~7 + else: + vis_index += 1 + + # Don't output actual tabs to be independent of how the terminal renders + # them + s = s.expandtabs() + + raise Kconfig_Syntax_Error, ( + _sep_lines("Error during tokenization at location indicated by caret.\n", + s, + " " * vis_index + "^\n")) + +def _parse_error(s, msg, filename, linenr): + error_str = "" + + if filename is not None: + assert linenr is not None + error_str += "{0}:{1}: ".format(filename, linenr) + + if s.endswith("\n"): + s = s[:-1] + + error_str += 'Error while parsing "{0}"'.format(s) + \ + ("." if msg is None else ": " + msg) + + raise Kconfig_Syntax_Error, error_str + +def _internal_error(msg): + msg += "\nSorry! You may want to send an email to kconfiglib@gmail.com " \ + "to tell me about this. Include the message above and the stack " \ + "trace and describe what you were doing." + + raise Internal_Error, msg + +if use_psyco: + import psyco + + Config._tokenize = psyco.proxy(Config._tokenize) + Config._eval_expr = psyco.proxy(Config._eval_expr) + + _indentation = psyco.proxy(_indentation) + _get_lines = psyco.proxy(_get_lines) diff --git a/tools/buildman/test.py b/tools/buildman/test.py index bcdedfbf3f..c0ad5d027d 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -21,20 +21,31 @@ import builder import control import command import commit +import terminal import toolchain +settings_data = ''' +# Buildman settings file + +[toolchain] +main: /usr/sbin + +[toolchain-alias] +x86: i386 x86_64 +''' + errors = [ '''main.c: In function 'main_loop': main.c:260:6: warning: unused variable 'joe' [-Wunused-variable] ''', - '''main.c: In function 'main_loop': + '''main.c: In function 'main_loop2': main.c:295:2: error: 'fred' undeclared (first use in this function) main.c:295:2: note: each undeclared identifier is reported only once for each function it appears in make[1]: *** [main.o] Error 1 make: *** [common/libcommon.o] Error 2 Make failed ''', - '''main.c: In function 'main_loop': + '''main.c: In function 'main_loop3': main.c:280:6: warning: unused variable 'mary' [-Wunused-variable] ''', '''powerpc-linux-ld: warning: dot moved backwards before `.bss' @@ -45,6 +56,20 @@ powerpc-linux-ld: u-boot: section .reloc lma 0xffffa400 overlaps previous sectio powerpc-linux-ld: u-boot: section .data lma 0xffffcd38 overlaps previous sections powerpc-linux-ld: u-boot: section .u_boot_cmd lma 0xffffeb40 overlaps previous sections powerpc-linux-ld: u-boot: section .bootpg lma 0xfffff198 overlaps previous sections +''', + '''In file included from %(basedir)sarch/sandbox/cpu/cpu.c:9:0: +%(basedir)sarch/sandbox/include/asm/state.h:44:0: warning: "xxxx" redefined [enabled by default] +%(basedir)sarch/sandbox/include/asm/state.h:43:0: note: this is the location of the previous definition +%(basedir)sarch/sandbox/cpu/cpu.c: In function 'do_reset': +%(basedir)sarch/sandbox/cpu/cpu.c:27:1: error: unknown type name 'blah' +%(basedir)sarch/sandbox/cpu/cpu.c:28:12: error: expected declaration specifiers or '...' before numeric constant +make[2]: *** [arch/sandbox/cpu/cpu.o] Error 1 +make[1]: *** [arch/sandbox/cpu] Error 2 +make[1]: *** Waiting for unfinished jobs.... +In file included from %(basedir)scommon/board_f.c:55:0: +%(basedir)sarch/sandbox/include/asm/state.h:44:0: warning: "xxxx" redefined [enabled by default] +%(basedir)sarch/sandbox/include/asm/state.h:43:0: note: this is the location of the previous definition +make: *** [sub-make] Error 2 ''' ] @@ -56,17 +81,20 @@ commits = [ ['9012', 'Third commit, error', 1, errors[0:2]], ['3456', 'Fourth commit, warning', 0, [errors[0], errors[2]]], ['7890', 'Fifth commit, link errors', 1, [errors[0], errors[3]]], - ['abcd', 'Sixth commit, fixes all errors', 0, []] + ['abcd', 'Sixth commit, fixes all errors', 0, []], + ['ef01', 'Seventh commit, check directory suppression', 1, [errors[4]]], ] boards = [ - ['board0', 'arm', 'armv7', 'ARM Board 1', 'Tester', '', ''], - ['board1', 'arm', 'armv7', 'ARM Board 2', 'Tester', '', ''], - ['board2', 'powerpc', 'powerpc', 'PowerPC board 1', 'Tester', '', ''], - ['board3', 'powerpc', 'mpc5xx', 'PowerPC board 2', 'Tester', '', ''], - ['board4', 'sandbox', 'sandbox', 'Sandbox board', 'Tester', '', ''] + ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 1', 'board0', ''], + ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 2', 'board1', ''], + ['Active', 'powerpc', 'powerpc', '', 'Tester', 'PowerPC board 1', 'board2', ''], + ['Active', 'powerpc', 'mpc5xx', '', 'Tester', 'PowerPC board 2', 'board3', ''], + ['Active', 'sandbox', 'sandbox', '', 'Tester', 'Sandbox board', 'board4', ''], ] +BASE_DIR = 'base' + class Options: """Class that holds build options""" pass @@ -95,24 +123,35 @@ class TestBuild(unittest.TestCase): self.boards.AddBoard(board.Board(*brd)) self.boards.SelectBoards([]) + # Add some test settings + bsettings.Setup(None) + bsettings.AddFile(settings_data) + # Set up the toolchains - bsettings.Setup() self.toolchains = toolchain.Toolchains() self.toolchains.Add('arm-linux-gcc', test=False) self.toolchains.Add('sparc-linux-gcc', test=False) self.toolchains.Add('powerpc-linux-gcc', test=False) self.toolchains.Add('gcc', test=False) + # Avoid sending any output + terminal.SetPrintTestMode() + self._col = terminal.Color() + def Make(self, commit, brd, stage, *args, **kwargs): + global base_dir + result = command.CommandResult() boardnum = int(brd.target[-1]) result.return_code = 0 result.stderr = '' result.stdout = ('This is the test output for board %s, commit %s' % (brd.target, commit.hash)) - if boardnum >= 1 and boardnum >= commit.sequence: + if ((boardnum >= 1 and boardnum >= commit.sequence) or + boardnum == 4 and commit.sequence == 6): result.return_code = commit.return_code - result.stderr = ''.join(commit.error_list) + result.stderr = (''.join(commit.error_list) + % {'basedir' : base_dir + '/.bm-work/00/'}) if stage == 'build': target_dir = None for arg in args: @@ -121,25 +160,129 @@ class TestBuild(unittest.TestCase): if not os.path.isdir(target_dir): os.mkdir(target_dir) - #time.sleep(.2 + boardnum * .2) result.combined = result.stdout + result.stderr return result - def testBasic(self): - """Test basic builder operation""" - output_dir = tempfile.mkdtemp() - if not os.path.isdir(output_dir): - os.mkdir(output_dir) - build = builder.Builder(self.toolchains, output_dir, None, 1, 2, + def assertSummary(self, text, arch, plus, boards, ok=False): + col = self._col + expected_colour = col.GREEN if ok else col.RED + expect = '%10s: ' % arch + # TODO(sjg@chromium.org): If plus is '', we shouldn't need this + expect += col.Color(expected_colour, plus) + expect += ' ' + for board in boards: + expect += col.Color(expected_colour, ' %s' % board) + self.assertEqual(text, expect) + + def testOutput(self): + """Test basic builder operation and output + + This does a line-by-line verification of the summary output. + """ + global base_dir + + base_dir = tempfile.mkdtemp() + if not os.path.isdir(base_dir): + os.mkdir(base_dir) + build = builder.Builder(self.toolchains, base_dir, None, 1, 2, checkout=False, show_unknown=False) build.do_make = self.Make board_selected = self.boards.GetSelectedDict() - #build.BuildCommits(self.commits, board_selected, False) - build.BuildBoards(self.commits, board_selected, False, False) - build.ShowSummary(self.commits, board_selected, True, False, - False, False) + build.BuildBoards(self.commits, board_selected, keep_outputs=False, + verbose=False) + lines = terminal.GetPrintTestLines() + count = 0 + for line in lines: + if line.text.strip(): + count += 1 + + # We should get one starting message, then an update for every commit + # built. + self.assertEqual(count, len(commits) * len(boards) + 1) + build.SetDisplayOptions(show_errors=True); + build.ShowSummary(self.commits, board_selected) + #terminal.EchoPrintTestLines() + lines = terminal.GetPrintTestLines() + self.assertEqual(lines[0].text, '01: %s' % commits[0][1]) + self.assertEqual(lines[1].text, '02: %s' % commits[1][1]) + + # We expect all archs to fail + col = terminal.Color() + self.assertSummary(lines[2].text, 'sandbox', '+', ['board4']) + self.assertSummary(lines[3].text, 'arm', '+', ['board1']) + self.assertSummary(lines[4].text, 'powerpc', '+', ['board2', 'board3']) + + # Now we should have the compiler warning + self.assertEqual(lines[5].text, 'w+%s' % + errors[0].rstrip().replace('\n', '\nw+')) + self.assertEqual(lines[5].colour, col.MAGENTA) + + self.assertEqual(lines[6].text, '03: %s' % commits[2][1]) + self.assertSummary(lines[7].text, 'sandbox', '+', ['board4']) + self.assertSummary(lines[8].text, 'arm', '', ['board1'], ok=True) + self.assertSummary(lines[9].text, 'powerpc', '+', ['board2', 'board3']) + + # Compiler error + self.assertEqual(lines[10].text, '+%s' % + errors[1].rstrip().replace('\n', '\n+')) + + self.assertEqual(lines[11].text, '04: %s' % commits[3][1]) + self.assertSummary(lines[12].text, 'sandbox', '', ['board4'], ok=True) + self.assertSummary(lines[13].text, 'powerpc', '', ['board2', 'board3'], + ok=True) + + # Compile error fixed + self.assertEqual(lines[14].text, '-%s' % + errors[1].rstrip().replace('\n', '\n-')) + self.assertEqual(lines[14].colour, col.GREEN) + + self.assertEqual(lines[15].text, 'w+%s' % + errors[2].rstrip().replace('\n', '\nw+')) + self.assertEqual(lines[15].colour, col.MAGENTA) + + self.assertEqual(lines[16].text, '05: %s' % commits[4][1]) + self.assertSummary(lines[17].text, 'sandbox', '+', ['board4']) + self.assertSummary(lines[18].text, 'powerpc', '', ['board3'], ok=True) + + # The second line of errors[3] is a duplicate, so buildman will drop it + expect = errors[3].rstrip().split('\n') + expect = [expect[0]] + expect[2:] + self.assertEqual(lines[19].text, '+%s' % + '\n'.join(expect).replace('\n', '\n+')) + + self.assertEqual(lines[20].text, 'w-%s' % + errors[2].rstrip().replace('\n', '\nw-')) + + self.assertEqual(lines[21].text, '06: %s' % commits[5][1]) + self.assertSummary(lines[22].text, 'sandbox', '', ['board4'], ok=True) + + # The second line of errors[3] is a duplicate, so buildman will drop it + expect = errors[3].rstrip().split('\n') + expect = [expect[0]] + expect[2:] + self.assertEqual(lines[23].text, '-%s' % + '\n'.join(expect).replace('\n', '\n-')) + + self.assertEqual(lines[24].text, 'w-%s' % + errors[0].rstrip().replace('\n', '\nw-')) + + self.assertEqual(lines[25].text, '07: %s' % commits[6][1]) + self.assertSummary(lines[26].text, 'sandbox', '+', ['board4']) + + # Pick out the correct error lines + expect_str = errors[4].rstrip().replace('%(basedir)s', '').split('\n') + expect = expect_str[3:8] + [expect_str[-1]] + self.assertEqual(lines[27].text, '+%s' % + '\n'.join(expect).replace('\n', '\n+')) + + # Now the warnings lines + expect = [expect_str[0]] + expect_str[10:12] + [expect_str[9]] + self.assertEqual(lines[28].text, 'w+%s' % + '\n'.join(expect).replace('\n', '\nw+')) + + self.assertEqual(len(lines), 29) + shutil.rmtree(base_dir) def _testGit(self): """Test basic builder operation by building a branch""" @@ -164,6 +307,113 @@ class TestBuild(unittest.TestCase): options.keep_outputs = False args = ['tegra20'] control.DoBuildman(options, args) + shutil.rmtree(base_dir) + + def testBoardSingle(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards(['sandbox']), + {'all': 1, 'sandbox': 1}) + + def testBoardArch(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards(['arm']), + {'all': 2, 'arm': 2}) + + def testBoardArchSingle(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards(['arm sandbox']), + {'all': 3, 'arm': 2, 'sandbox' : 1}) + + def testBoardArchSingleMultiWord(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards(['arm', 'sandbox']), + {'all': 3, 'arm': 2, 'sandbox' : 1}) + + def testBoardSingleAnd(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards(['Tester & arm']), + {'all': 2, 'Tester&arm': 2}) + + def testBoardTwoAnd(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards(['Tester', '&', 'arm', + 'Tester' '&', 'powerpc', + 'sandbox']), + {'all': 5, 'Tester&powerpc': 2, 'Tester&arm': 2, + 'sandbox' : 1}) + + def testBoardAll(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards([]), {'all': 5}) + + def testBoardRegularExpression(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards(['T.*r&^Po']), + {'T.*r&^Po': 2, 'all': 2}) + + def testBoardDuplicate(self): + """Test single board selection""" + self.assertEqual(self.boards.SelectBoards(['sandbox sandbox', + 'sandbox']), + {'all': 1, 'sandbox': 1}) + def CheckDirs(self, build, dirname): + self.assertEqual('base%s' % dirname, build._GetOutputDir(1)) + self.assertEqual('base%s/fred' % dirname, + build.GetBuildDir(1, 'fred')) + self.assertEqual('base%s/fred/done' % dirname, + build.GetDoneFile(1, 'fred')) + self.assertEqual('base%s/fred/u-boot.sizes' % dirname, + build.GetFuncSizesFile(1, 'fred', 'u-boot')) + self.assertEqual('base%s/fred/u-boot.objdump' % dirname, + build.GetObjdumpFile(1, 'fred', 'u-boot')) + self.assertEqual('base%s/fred/err' % dirname, + build.GetErrFile(1, 'fred')) + + def testOutputDir(self): + build = builder.Builder(self.toolchains, BASE_DIR, None, 1, 2, + checkout=False, show_unknown=False) + build.commits = self.commits + build.commit_count = len(self.commits) + subject = self.commits[1].subject.translate(builder.trans_valid_chars) + dirname ='/%02d_of_%02d_g%s_%s' % (2, build.commit_count, commits[1][0], + subject[:20]) + self.CheckDirs(build, dirname) + + def testOutputDirCurrent(self): + build = builder.Builder(self.toolchains, BASE_DIR, None, 1, 2, + checkout=False, show_unknown=False) + build.commits = None + build.commit_count = 0 + self.CheckDirs(build, '/current') + + def testOutputDirNoSubdirs(self): + build = builder.Builder(self.toolchains, BASE_DIR, None, 1, 2, + checkout=False, show_unknown=False, + no_subdirs=True) + build.commits = None + build.commit_count = 0 + self.CheckDirs(build, '') + + def testToolchainAliases(self): + self.assertTrue(self.toolchains.Select('arm') != None) + with self.assertRaises(ValueError): + self.toolchains.Select('no-arch') + with self.assertRaises(ValueError): + self.toolchains.Select('x86') + + self.toolchains = toolchain.Toolchains() + self.toolchains.Add('x86_64-linux-gcc', test=False) + self.assertTrue(self.toolchains.Select('x86') != None) + + self.toolchains = toolchain.Toolchains() + self.toolchains.Add('i386-linux-gcc', test=False) + self.assertTrue(self.toolchains.Select('x86') != None) + + def testToolchainDownload(self): + """Test that we can download toolchains""" + self.assertEqual('https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/x86_64-gcc-4.6.3-nolibc_arm-unknown-linux-gnueabi.tar.xz', + self.toolchains.LocateArchUrl('arm')) + if __name__ == "__main__": unittest.main() diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index dfa1d00ce2..d4c5d4a11e 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -3,12 +3,44 @@ # SPDX-License-Identifier: GPL-2.0+ # +import re import glob +from HTMLParser import HTMLParser import os +import sys +import tempfile +import urllib2 import bsettings import command +# Simple class to collect links from a page +class MyHTMLParser(HTMLParser): + def __init__(self, arch): + """Create a new parser + + After the parser runs, self.links will be set to a list of the links + to .xz archives found in the page, and self.arch_link will be set to + the one for the given architecture (or None if not found). + + Args: + arch: Architecture to search for + """ + HTMLParser.__init__(self) + self.arch_link = None + self.links = [] + self._match = '_%s-' % arch + + def handle_starttag(self, tag, attrs): + if tag == 'a': + for tag, value in attrs: + if tag == 'href': + if value and value.endswith('.xz'): + self.links.append(value) + if self._match in value: + self.arch_link = value + + class Toolchain: """A single toolchain @@ -19,7 +51,6 @@ class Toolchain: arch: Architecture of toolchain as determined from the first component of the filename. E.g. arm-linux-gcc becomes arm """ - def __init__(self, fname, test, verbose=False): """Create a new toolchain object. @@ -29,16 +60,24 @@ class Toolchain: """ self.gcc = fname self.path = os.path.dirname(fname) - self.cross = os.path.basename(fname)[:-3] + + # Find the CROSS_COMPILE prefix to use for U-Boot. For example, + # 'arm-linux-gnueabihf-gcc' turns into 'arm-linux-gnueabihf-'. + basename = os.path.basename(fname) + pos = basename.rfind('-') + self.cross = basename[:pos + 1] if pos != -1 else '' + + # The architecture is the first part of the name pos = self.cross.find('-') self.arch = self.cross[:pos] if pos != -1 else 'sandbox' - env = self.MakeEnvironment() + env = self.MakeEnvironment(False) # As a basic sanity check, run the C compiler with --version cmd = [fname, '--version'] if test: - result = command.RunPipe([cmd], capture=True, env=env) + result = command.RunPipe([cmd], capture=True, env=env, + raise_on_error=False) self.ok = result.return_code == 0 if verbose: print 'Tool chain test: ', @@ -64,7 +103,7 @@ class Toolchain: Returns: Priority of toolchain, 0=highest, 20=lowest. """ - priority_list = ['-elf', '-unknown-linux-gnu', '-linux', '-elf', + priority_list = ['-elf', '-unknown-linux-gnu', '-linux', '-none-linux-gnueabi', '-uclinux', '-none-eabi', '-gentoo-linux-gnu', '-linux-gnueabi', '-le-linux', '-uclinux'] for prio in range(len(priority_list)): @@ -72,15 +111,23 @@ class Toolchain: return prio return prio - def MakeEnvironment(self): + def MakeEnvironment(self, full_path): """Returns an environment for using the toolchain. - Thie takes the current environment, adds CROSS_COMPILE and - augments PATH so that the toolchain will operate correctly. + Thie takes the current environment and adds CROSS_COMPILE so that + the tool chain will operate correctly. + + Args: + full_path: Return the full path in CROSS_COMPILE and don't set + PATH """ env = dict(os.environ) - env['CROSS_COMPILE'] = self.cross - env['PATH'] += (':' + self.path) + if full_path: + env['CROSS_COMPILE'] = os.path.join(self.path, self.cross) + else: + env['CROSS_COMPILE'] = self.cross + env['PATH'] = self.path + ':' + env['PATH'] + return env @@ -97,12 +144,31 @@ class Toolchains: def __init__(self): self.toolchains = {} self.paths = [] - for name, value in bsettings.GetItems('toolchain'): + self._make_flags = dict(bsettings.GetItems('make-flags')) + + def GetPathList(self): + """Get a list of available toolchain paths + + Returns: + List of strings, each a path to a toolchain mentioned in the + [toolchain] section of the settings file. + """ + toolchains = bsettings.GetItems('toolchain') + if not toolchains: + print ("Warning: No tool chains - please add a [toolchain] section" + " to your buildman config file %s. See README for details" % + bsettings.config_fname) + + paths = [] + for name, value in toolchains: if '*' in value: - self.paths += glob.glob(value) + paths += glob.glob(value) else: - self.paths.append(value) + paths.append(value) + return paths + def GetSettings(self): + self.paths += self.GetPathList() def Add(self, fname, test=True, verbose=False): """Add a toolchain to our list @@ -122,6 +188,24 @@ class Toolchains: if add_it: self.toolchains[toolchain.arch] = toolchain + def ScanPath(self, path, verbose): + """Scan a path for a valid toolchain + + Args: + path: Path to scan + verbose: True to print out progress information + Returns: + Filename of C compiler if found, else None + """ + for subdir in ['.', 'bin', 'usr/bin']: + dirname = os.path.join(path, subdir) + if verbose: print " - looking in '%s'" % dirname + for fname in glob.glob(dirname + '/*gcc'): + if verbose: print " - found '%s'" % fname + return fname + return None + + def Scan(self, verbose): """Scan for available toolchains and select the best for each arch. @@ -135,12 +219,9 @@ class Toolchains: if verbose: print 'Scanning for tool chains' for path in self.paths: if verbose: print " - scanning path '%s'" % path - for subdir in ['.', 'bin', 'usr/bin']: - dirname = os.path.join(path, subdir) - if verbose: print " - looking in '%s'" % dirname - for fname in glob.glob(dirname + '/*gcc'): - if verbose: print " - found '%s'" % fname - self.Add(fname, True, verbose) + fname = self.ScanPath(path, verbose) + if fname: + self.Add(fname, True, verbose) def List(self): """List out the selected toolchains for each architecture""" @@ -160,10 +241,239 @@ class Toolchains: returns: toolchain object, or None if none found """ - for name, value in bsettings.GetItems('toolchain-alias'): - if arch == name: - arch = value + for tag, value in bsettings.GetItems('toolchain-alias'): + if arch == tag: + for alias in value.split(): + if alias in self.toolchains: + return self.toolchains[alias] if not arch in self.toolchains: raise ValueError, ("No tool chain found for arch '%s'" % arch) return self.toolchains[arch] + + def ResolveReferences(self, var_dict, args): + """Resolve variable references in a string + + This converts ${blah} within the string to the value of blah. + This function works recursively. + + Args: + var_dict: Dictionary containing variables and their values + args: String containing make arguments + Returns: + Resolved string + + >>> bsettings.Setup() + >>> tcs = Toolchains() + >>> tcs.Add('fred', False) + >>> var_dict = {'oblique' : 'OBLIQUE', 'first' : 'fi${second}rst', \ + 'second' : '2nd'} + >>> tcs.ResolveReferences(var_dict, 'this=${oblique}_set') + 'this=OBLIQUE_set' + >>> tcs.ResolveReferences(var_dict, 'this=${oblique}_set${first}nd') + 'this=OBLIQUE_setfi2ndrstnd' + """ + re_var = re.compile('(\$\{[-_a-z0-9A-Z]{1,}\})') + + while True: + m = re_var.search(args) + if not m: + break + lookup = m.group(0)[2:-1] + value = var_dict.get(lookup, '') + args = args[:m.start(0)] + value + args[m.end(0):] + return args + + def GetMakeArguments(self, board): + """Returns 'make' arguments for a given board + + The flags are in a section called 'make-flags'. Flags are named + after the target they represent, for example snapper9260=TESTING=1 + will pass TESTING=1 to make when building the snapper9260 board. + + References to other boards can be added in the string also. For + example: + + [make-flags] + at91-boards=ENABLE_AT91_TEST=1 + snapper9260=${at91-boards} BUILD_TAG=442 + snapper9g45=${at91-boards} BUILD_TAG=443 + + This will return 'ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260 + and 'ENABLE_AT91_TEST=1 BUILD_TAG=443' for snapper9g45. + + A special 'target' variable is set to the board target. + + Args: + board: Board object for the board to check. + Returns: + 'make' flags for that board, or '' if none + """ + self._make_flags['target'] = board.target + arg_str = self.ResolveReferences(self._make_flags, + self._make_flags.get(board.target, '')) + args = arg_str.split(' ') + i = 0 + while i < len(args): + if not args[i]: + del args[i] + else: + i += 1 + return args + + def LocateArchUrl(self, fetch_arch): + """Find a toolchain available online + + Look in standard places for available toolchains. At present the + only standard place is at kernel.org. + + Args: + arch: Architecture to look for, or 'list' for all + Returns: + If fetch_arch is 'list', a tuple: + Machine architecture (e.g. x86_64) + List of toolchains + else + URL containing this toolchain, if avaialble, else None + """ + arch = command.OutputOneLine('uname', '-m') + base = 'https://www.kernel.org/pub/tools/crosstool/files/bin' + versions = ['4.6.3', '4.6.2', '4.5.1', '4.2.4'] + links = [] + for version in versions: + url = '%s/%s/%s/' % (base, arch, version) + print 'Checking: %s' % url + response = urllib2.urlopen(url) + html = response.read() + parser = MyHTMLParser(fetch_arch) + parser.feed(html) + if fetch_arch == 'list': + links += parser.links + elif parser.arch_link: + return url + parser.arch_link + if fetch_arch == 'list': + return arch, links + return None + + def Download(self, url): + """Download a file to a temporary directory + + Args: + url: URL to download + Returns: + Tuple: + Temporary directory name + Full path to the downloaded archive file in that directory, + or None if there was an error while downloading + """ + print "Downloading: %s" % url + leaf = url.split('/')[-1] + tmpdir = tempfile.mkdtemp('.buildman') + response = urllib2.urlopen(url) + fname = os.path.join(tmpdir, leaf) + fd = open(fname, 'wb') + meta = response.info() + size = int(meta.getheaders("Content-Length")[0]) + done = 0 + block_size = 1 << 16 + status = '' + + # Read the file in chunks and show progress as we go + while True: + buffer = response.read(block_size) + if not buffer: + print chr(8) * (len(status) + 1), '\r', + break + + done += len(buffer) + fd.write(buffer) + status = r"%10d MiB [%3d%%]" % (done / 1024 / 1024, + done * 100 / size) + status = status + chr(8) * (len(status) + 1) + print status, + sys.stdout.flush() + fd.close() + if done != size: + print 'Error, failed to download' + os.remove(fname) + fname = None + return tmpdir, fname + + def Unpack(self, fname, dest): + """Unpack a tar file + + Args: + fname: Filename to unpack + dest: Destination directory + Returns: + Directory name of the first entry in the archive, without the + trailing / + """ + stdout = command.Output('tar', 'xvfJ', fname, '-C', dest) + return stdout.splitlines()[0][:-1] + + def TestSettingsHasPath(self, path): + """Check if builmand will find this toolchain + + Returns: + True if the path is in settings, False if not + """ + paths = self.GetPathList() + return path in paths + + def ListArchs(self): + """List architectures with available toolchains to download""" + host_arch, archives = self.LocateArchUrl('list') + re_arch = re.compile('[-a-z0-9.]*_([^-]*)-.*') + arch_set = set() + for archive in archives: + # Remove the host architecture from the start + arch = re_arch.match(archive[len(host_arch):]) + if arch: + arch_set.add(arch.group(1)) + return sorted(arch_set) + + def FetchAndInstall(self, arch): + """Fetch and install a new toolchain + + arch: + Architecture to fetch, or 'list' to list + """ + # Fist get the URL for this architecture + url = self.LocateArchUrl(arch) + if not url: + print ("Cannot find toolchain for arch '%s' - use 'list' to list" % + arch) + return 2 + home = os.environ['HOME'] + dest = os.path.join(home, '.buildman-toolchains') + if not os.path.exists(dest): + os.mkdir(dest) + + # Download the tar file for this toolchain and unpack it + tmpdir, tarfile = self.Download(url) + if not tarfile: + return 1 + print 'Unpacking to: %s' % dest, + sys.stdout.flush() + path = self.Unpack(tarfile, dest) + os.remove(tarfile) + os.rmdir(tmpdir) + print + + # Check that the toolchain works + print 'Testing' + dirpath = os.path.join(dest, path) + compiler_fname = self.ScanPath(dirpath, True) + if not compiler_fname: + print 'Could not locate C compiler - fetch failed.' + return 1 + toolchain = Toolchain(compiler_fname, True, True) + + # Make sure that it will be found by buildman + if not self.TestSettingsHasPath(dirpath): + print ("Adding 'download' to config file '%s'" % + bsettings.config_fname) + tools_dir = os.path.dirname(dirpath) + bsettings.SetItem('toolchain', 'download', '%s/*' % tools_dir) + return 0 diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl deleted file mode 100755 index 896e2bc985..0000000000 --- a/tools/checkpatch.pl +++ /dev/null @@ -1,3709 +0,0 @@ -#!/usr/bin/perl -w -# (c) 2001, Dave Jones. (the file handling bit) -# (c) 2005, Joel Schopp (the ugly bit) -# (c) 2007,2008, Andy Whitcroft (new conditions, test suite) -# (c) 2008-2010 Andy Whitcroft -# Licensed under the terms of the GNU GPL License version 2 - -use strict; - -my $P = $0; -$P =~ s@.*/@@g; - -my $V = '0.32'; - -use Getopt::Long qw(:config no_auto_abbrev); - -my $quiet = 0; -my $tree = 1; -my $chk_signoff = 1; -my $chk_patch = 1; -my $tst_only; -my $emacs = 0; -my $terse = 0; -my $file = 0; -my $check = 0; -my $summary = 1; -my $mailback = 0; -my $summary_file = 0; -my $show_types = 0; -my $root; -my %debug; -my %ignore_type = (); -my @ignore = (); -my $help = 0; -my $configuration_file = ".checkpatch.conf"; -my $max_line_length = 80; - -sub help { - my ($exitcode) = @_; - - print << "EOM"; -Usage: $P [OPTION]... [FILE]... -Version: $V - -Options: - -q, --quiet quiet - --no-tree run without a kernel tree - --no-signoff do not check for 'Signed-off-by' line - --patch treat FILE as patchfile (default) - --emacs emacs compile window format - --terse one line per report - -f, --file treat FILE as regular source file - --subjective, --strict enable more subjective tests - --ignore TYPE(,TYPE2...) ignore various comma separated message types - --max-line-length=n set the maximum line length, if exceeded, warn - --show-types show the message "types" in the output - --root=PATH PATH to the kernel tree root - --no-summary suppress the per-file summary - --mailback only produce a report in case of warnings/errors - --summary-file include the filename in summary - --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of - 'values', 'possible', 'type', and 'attr' (default - is all off) - --test-only=WORD report only warnings/errors containing WORD - literally - -h, --help, --version display this help and exit - -When FILE is - read standard input. -EOM - - exit($exitcode); -} - -my $conf = which_conf($configuration_file); -if (-f $conf) { - my @conf_args; - open(my $conffile, '<', "$conf") - or warn "$P: Can't find a readable $configuration_file file $!\n"; - - while (<$conffile>) { - my $line = $_; - - $line =~ s/\s*\n?$//g; - $line =~ s/^\s*//g; - $line =~ s/\s+/ /g; - - next if ($line =~ m/^\s*#/); - next if ($line =~ m/^\s*$/); - - my @words = split(" ", $line); - foreach my $word (@words) { - last if ($word =~ m/^#/); - push (@conf_args, $word); - } - } - close($conffile); - unshift(@ARGV, @conf_args) if @conf_args; -} - -GetOptions( - 'q|quiet+' => \$quiet, - 'tree!' => \$tree, - 'signoff!' => \$chk_signoff, - 'patch!' => \$chk_patch, - 'emacs!' => \$emacs, - 'terse!' => \$terse, - 'f|file!' => \$file, - 'subjective!' => \$check, - 'strict!' => \$check, - 'ignore=s' => \@ignore, - 'show-types!' => \$show_types, - 'max-line-length=i' => \$max_line_length, - 'root=s' => \$root, - 'summary!' => \$summary, - 'mailback!' => \$mailback, - 'summary-file!' => \$summary_file, - - 'debug=s' => \%debug, - 'test-only=s' => \$tst_only, - 'h|help' => \$help, - 'version' => \$help -) or help(1); - -help(0) if ($help); - -my $exit = 0; - -if ($#ARGV < 0) { - print "$P: no input files\n"; - exit(1); -} - -@ignore = split(/,/, join(',',@ignore)); -foreach my $word (@ignore) { - $word =~ s/\s*\n?$//g; - $word =~ s/^\s*//g; - $word =~ s/\s+/ /g; - $word =~ tr/[a-z]/[A-Z]/; - - next if ($word =~ m/^\s*#/); - next if ($word =~ m/^\s*$/); - - $ignore_type{$word}++; -} - -my $dbg_values = 0; -my $dbg_possible = 0; -my $dbg_type = 0; -my $dbg_attr = 0; -for my $key (keys %debug) { - ## no critic - eval "\${dbg_$key} = '$debug{$key}';"; - die "$@" if ($@); -} - -my $rpt_cleaners = 0; - -if ($terse) { - $emacs = 1; - $quiet++; -} - -if ($tree) { - if (defined $root) { - if (!top_of_kernel_tree($root)) { - die "$P: $root: --root does not point at a valid tree\n"; - } - } else { - if (top_of_kernel_tree('.')) { - $root = '.'; - } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ && - top_of_kernel_tree($1)) { - $root = $1; - } - } - - if (!defined $root) { - print "Must be run from the top-level dir. of a kernel tree\n"; - exit(2); - } -} - -my $emitted_corrupt = 0; - -our $Ident = qr{ - [A-Za-z_][A-Za-z\d_]* - (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)* - }x; -our $Storage = qr{extern|static|asmlinkage}; -our $Sparse = qr{ - __user| - __kernel| - __force| - __iomem| - __must_check| - __init_refok| - __kprobes| - __ref| - __rcu - }x; - -# Notes to $Attribute: -# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check -our $Attribute = qr{ - const| - __percpu| - __nocast| - __safe| - __bitwise__| - __packed__| - __packed2__| - __naked| - __maybe_unused| - __always_unused| - __noreturn| - __used| - __cold| - __noclone| - __deprecated| - __read_mostly| - __kprobes| - __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)| - ____cacheline_aligned| - ____cacheline_aligned_in_smp| - ____cacheline_internodealigned_in_smp| - __weak - }x; -our $Modifier; -our $Inline = qr{inline|__always_inline|noinline}; -our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; -our $Lval = qr{$Ident(?:$Member)*}; - -our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; -our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; -our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; -our $Float = qr{$Float_hex|$Float_dec|$Float_int}; -our $Constant = qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*}; -our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; -our $Compare = qr{<=|>=|==|!=|<|>}; -our $Operators = qr{ - <=|>=|==|!=| - =>|->|<<|>>|<|>|!|~| - &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|% - }x; - -our $NonptrType; -our $Type; -our $Declare; - -our $NON_ASCII_UTF8 = qr{ - [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte - | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs - | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte - | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates - | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3 - | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15 - | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 -}x; - -our $UTF8 = qr{ - [\x09\x0A\x0D\x20-\x7E] # ASCII - | $NON_ASCII_UTF8 -}x; - -our $typeTypedefs = qr{(?x: - (?:__)?(?:u|s|be|le)(?:8|16|32|64)| - atomic_t -)}; - -our $logFunctions = qr{(?x: - printk(?:_ratelimited|_once|)| - [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| - WARN(?:_RATELIMIT|_ONCE|)| - panic| - debug| - printf| - MODULE_[A-Z_]+ -)}; - -our $signature_tags = qr{(?xi: - Signed-off-by:| - Acked-by:| - Tested-by:| - Reviewed-by:| - Reported-by:| - To:| - Cc: -)}; - -our @typeList = ( - qr{void}, - qr{(?:unsigned\s+)?char}, - qr{(?:unsigned\s+)?short}, - qr{(?:unsigned\s+)?int}, - qr{(?:unsigned\s+)?long}, - qr{(?:unsigned\s+)?long\s+int}, - qr{(?:unsigned\s+)?long\s+long}, - qr{(?:unsigned\s+)?long\s+long\s+int}, - qr{unsigned}, - qr{float}, - qr{double}, - qr{bool}, - qr{struct\s+$Ident}, - qr{union\s+$Ident}, - qr{enum\s+$Ident}, - qr{${Ident}_t}, - qr{${Ident}_handler}, - qr{${Ident}_handler_fn}, -); -our @modifierList = ( - qr{fastcall}, -); - -our $allowed_asm_includes = qr{(?x: - irq| - memory -)}; -# memory.h: ARM has a custom one - -sub build_types { - my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; - my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; - $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; - $NonptrType = qr{ - (?:$Modifier\s+|const\s+)* - (?: - (?:typeof|__typeof__)\s*\([^\)]*\)| - (?:$typeTypedefs\b)| - (?:${all}\b) - ) - (?:\s+$Modifier|\s+const)* - }x; - $Type = qr{ - $NonptrType - (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)? - (?:\s+$Inline|\s+$Modifier)* - }x; - $Declare = qr{(?:$Storage\s+)?$Type}; -} -build_types(); - - -our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; - -# Using $balanced_parens, $LvalOrFunc, or $FuncArg -# requires at least perl version v5.10.0 -# Any use must be runtime checked with $^V - -our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; -our $LvalOrFunc = qr{($Lval)\s*($balanced_parens{0,1})\s*}; -our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)}; - -sub deparenthesize { - my ($string) = @_; - return "" if (!defined($string)); - $string =~ s@^\s*\(\s*@@g; - $string =~ s@\s*\)\s*$@@g; - $string =~ s@\s+@ @g; - return $string; -} - -$chk_signoff = 0 if ($file); - -my @rawlines = (); -my @lines = (); -my $vname; -for my $filename (@ARGV) { - my $FILE; - if ($file) { - open($FILE, '-|', "diff -u /dev/null $filename") || - die "$P: $filename: diff failed - $!\n"; - } elsif ($filename eq '-') { - open($FILE, '<&STDIN'); - } else { - open($FILE, '<', "$filename") || - die "$P: $filename: open failed - $!\n"; - } - if ($filename eq '-') { - $vname = 'Your patch'; - } else { - $vname = $filename; - } - while (<$FILE>) { - chomp; - push(@rawlines, $_); - } - close($FILE); - if (!process($filename)) { - $exit = 1; - } - @rawlines = (); - @lines = (); -} - -exit($exit); - -sub top_of_kernel_tree { - my ($root) = @_; - - my @tree_check = ( - "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", - "README", "Documentation", "arch", "include", "drivers", - "fs", "init", "ipc", "kernel", "lib", "scripts", - ); - - foreach my $check (@tree_check) { - if (! -e $root . '/' . $check) { - return 0; - } - } - return 1; -} - -sub parse_email { - my ($formatted_email) = @_; - - my $name = ""; - my $address = ""; - my $comment = ""; - - if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) { - $name = $1; - $address = $2; - $comment = $3 if defined $3; - } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) { - $address = $1; - $comment = $2 if defined $2; - } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { - $address = $1; - $comment = $2 if defined $2; - $formatted_email =~ s/$address.*$//; - $name = $formatted_email; - $name =~ s/^\s+|\s+$//g; - $name =~ s/^\"|\"$//g; - # If there's a name left after stripping spaces and - # leading quotes, and the address doesn't have both - # leading and trailing angle brackets, the address - # is invalid. ie: - # "joe smith joe@smith.com" bad - # "joe smith ]+>$/) { - $name = ""; - $address = ""; - $comment = ""; - } - } - - $name =~ s/^\s+|\s+$//g; - $name =~ s/^\"|\"$//g; - $address =~ s/^\s+|\s+$//g; - $address =~ s/^\<|\>$//g; - - if ($name =~ /[^\w \-]/i) { ##has "must quote" chars - $name =~ s/(?"; - } - - return $formatted_email; -} - -sub which_conf { - my ($conf) = @_; - - foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { - if (-e "$path/$conf") { - return "$path/$conf"; - } - } - - return ""; -} - -sub expand_tabs { - my ($str) = @_; - - my $res = ''; - my $n = 0; - for my $c (split(//, $str)) { - if ($c eq "\t") { - $res .= ' '; - $n++; - for (; ($n % 8) != 0; $n++) { - $res .= ' '; - } - next; - } - $res .= $c; - $n++; - } - - return $res; -} -sub copy_spacing { - (my $res = shift) =~ tr/\t/ /c; - return $res; -} - -sub line_stats { - my ($line) = @_; - - # Drop the diff line leader and expand tabs - $line =~ s/^.//; - $line = expand_tabs($line); - - # Pick the indent from the front of the line. - my ($white) = ($line =~ /^(\s*)/); - - return (length($line), length($white)); -} - -my $sanitise_quote = ''; - -sub sanitise_line_reset { - my ($in_comment) = @_; - - if ($in_comment) { - $sanitise_quote = '*/'; - } else { - $sanitise_quote = ''; - } -} -sub sanitise_line { - my ($line) = @_; - - my $res = ''; - my $l = ''; - - my $qlen = 0; - my $off = 0; - my $c; - - # Always copy over the diff marker. - $res = substr($line, 0, 1); - - for ($off = 1; $off < length($line); $off++) { - $c = substr($line, $off, 1); - - # Comments we are wacking completly including the begin - # and end, all to $;. - if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { - $sanitise_quote = '*/'; - - substr($res, $off, 2, "$;$;"); - $off++; - next; - } - if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') { - $sanitise_quote = ''; - substr($res, $off, 2, "$;$;"); - $off++; - next; - } - if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') { - $sanitise_quote = '//'; - - substr($res, $off, 2, $sanitise_quote); - $off++; - next; - } - - # A \ in a string means ignore the next character. - if (($sanitise_quote eq "'" || $sanitise_quote eq '"') && - $c eq "\\") { - substr($res, $off, 2, 'XX'); - $off++; - next; - } - # Regular quotes. - if ($c eq "'" || $c eq '"') { - if ($sanitise_quote eq '') { - $sanitise_quote = $c; - - substr($res, $off, 1, $c); - next; - } elsif ($sanitise_quote eq $c) { - $sanitise_quote = ''; - } - } - - #print "c<$c> SQ<$sanitise_quote>\n"; - if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") { - substr($res, $off, 1, $;); - } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") { - substr($res, $off, 1, $;); - } elsif ($off != 0 && $sanitise_quote && $c ne "\t") { - substr($res, $off, 1, 'X'); - } else { - substr($res, $off, 1, $c); - } - } - - if ($sanitise_quote eq '//') { - $sanitise_quote = ''; - } - - # The pathname on a #include may be surrounded by '<' and '>'. - if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) { - my $clean = 'X' x length($1); - $res =~ s@\<.*\>@<$clean>@; - - # The whole of a #error is a string. - } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) { - my $clean = 'X' x length($1); - $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; - } - - return $res; -} - -sub ctx_statement_block { - my ($linenr, $remain, $off) = @_; - my $line = $linenr - 1; - my $blk = ''; - my $soff = $off; - my $coff = $off - 1; - my $coff_set = 0; - - my $loff = 0; - - my $type = ''; - my $level = 0; - my @stack = (); - my $p; - my $c; - my $len = 0; - - my $remainder; - while (1) { - @stack = (['', 0]) if ($#stack == -1); - - #warn "CSB: blk<$blk> remain<$remain>\n"; - # If we are about to drop off the end, pull in more - # context. - if ($off >= $len) { - for (; $remain > 0; $line++) { - last if (!defined $lines[$line]); - next if ($lines[$line] =~ /^-/); - $remain--; - $loff = $len; - $blk .= $lines[$line] . "\n"; - $len = length($blk); - $line++; - last; - } - # Bail if there is no further context. - #warn "CSB: blk<$blk> off<$off> len<$len>\n"; - if ($off >= $len) { - last; - } - if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { - $level++; - $type = '#'; - } - } - $p = $c; - $c = substr($blk, $off, 1); - $remainder = substr($blk, $off); - - #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n"; - - # Handle nested #if/#else. - if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) { - push(@stack, [ $type, $level ]); - } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) { - ($type, $level) = @{$stack[$#stack - 1]}; - } elsif ($remainder =~ /^#\s*endif\b/) { - ($type, $level) = @{pop(@stack)}; - } - - # Statement ends at the ';' or a close '}' at the - # outermost level. - if ($level == 0 && $c eq ';') { - last; - } - - # An else is really a conditional as long as its not else if - if ($level == 0 && $coff_set == 0 && - (!defined($p) || $p =~ /(?:\s|\}|\+)/) && - $remainder =~ /^(else)(?:\s|{)/ && - $remainder !~ /^else\s+if\b/) { - $coff = $off + length($1) - 1; - $coff_set = 1; - #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n"; - #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n"; - } - - if (($type eq '' || $type eq '(') && $c eq '(') { - $level++; - $type = '('; - } - if ($type eq '(' && $c eq ')') { - $level--; - $type = ($level != 0)? '(' : ''; - - if ($level == 0 && $coff < $soff) { - $coff = $off; - $coff_set = 1; - #warn "CSB: mark coff<$coff>\n"; - } - } - if (($type eq '' || $type eq '{') && $c eq '{') { - $level++; - $type = '{'; - } - if ($type eq '{' && $c eq '}') { - $level--; - $type = ($level != 0)? '{' : ''; - - if ($level == 0) { - if (substr($blk, $off + 1, 1) eq ';') { - $off++; - } - last; - } - } - # Preprocessor commands end at the newline unless escaped. - if ($type eq '#' && $c eq "\n" && $p ne "\\") { - $level--; - $type = ''; - $off++; - last; - } - $off++; - } - # We are truly at the end, so shuffle to the next line. - if ($off == $len) { - $loff = $len + 1; - $line++; - $remain--; - } - - my $statement = substr($blk, $soff, $off - $soff + 1); - my $condition = substr($blk, $soff, $coff - $soff + 1); - - #warn "STATEMENT<$statement>\n"; - #warn "CONDITION<$condition>\n"; - - #print "coff<$coff> soff<$off> loff<$loff>\n"; - - return ($statement, $condition, - $line, $remain + 1, $off - $loff + 1, $level); -} - -sub statement_lines { - my ($stmt) = @_; - - # Strip the diff line prefixes and rip blank lines at start and end. - $stmt =~ s/(^|\n)./$1/g; - $stmt =~ s/^\s*//; - $stmt =~ s/\s*$//; - - my @stmt_lines = ($stmt =~ /\n/g); - - return $#stmt_lines + 2; -} - -sub statement_rawlines { - my ($stmt) = @_; - - my @stmt_lines = ($stmt =~ /\n/g); - - return $#stmt_lines + 2; -} - -sub statement_block_size { - my ($stmt) = @_; - - $stmt =~ s/(^|\n)./$1/g; - $stmt =~ s/^\s*{//; - $stmt =~ s/}\s*$//; - $stmt =~ s/^\s*//; - $stmt =~ s/\s*$//; - - my @stmt_lines = ($stmt =~ /\n/g); - my @stmt_statements = ($stmt =~ /;/g); - - my $stmt_lines = $#stmt_lines + 2; - my $stmt_statements = $#stmt_statements + 1; - - if ($stmt_lines > $stmt_statements) { - return $stmt_lines; - } else { - return $stmt_statements; - } -} - -sub ctx_statement_full { - my ($linenr, $remain, $off) = @_; - my ($statement, $condition, $level); - - my (@chunks); - - # Grab the first conditional/block pair. - ($statement, $condition, $linenr, $remain, $off, $level) = - ctx_statement_block($linenr, $remain, $off); - #print "F: c<$condition> s<$statement> remain<$remain>\n"; - push(@chunks, [ $condition, $statement ]); - if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) { - return ($level, $linenr, @chunks); - } - - # Pull in the following conditional/block pairs and see if they - # could continue the statement. - for (;;) { - ($statement, $condition, $linenr, $remain, $off, $level) = - ctx_statement_block($linenr, $remain, $off); - #print "C: c<$condition> s<$statement> remain<$remain>\n"; - last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s)); - #print "C: push\n"; - push(@chunks, [ $condition, $statement ]); - } - - return ($level, $linenr, @chunks); -} - -sub ctx_block_get { - my ($linenr, $remain, $outer, $open, $close, $off) = @_; - my $line; - my $start = $linenr - 1; - my $blk = ''; - my @o; - my @c; - my @res = (); - - my $level = 0; - my @stack = ($level); - for ($line = $start; $remain > 0; $line++) { - next if ($rawlines[$line] =~ /^-/); - $remain--; - - $blk .= $rawlines[$line]; - - # Handle nested #if/#else. - if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) { - push(@stack, $level); - } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) { - $level = $stack[$#stack - 1]; - } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) { - $level = pop(@stack); - } - - foreach my $c (split(//, $lines[$line])) { - ##print "C<$c>L<$level><$open$close>O<$off>\n"; - if ($off > 0) { - $off--; - next; - } - - if ($c eq $close && $level > 0) { - $level--; - last if ($level == 0); - } elsif ($c eq $open) { - $level++; - } - } - - if (!$outer || $level <= 1) { - push(@res, $rawlines[$line]); - } - - last if ($level == 0); - } - - return ($level, @res); -} -sub ctx_block_outer { - my ($linenr, $remain) = @_; - - my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0); - return @r; -} -sub ctx_block { - my ($linenr, $remain) = @_; - - my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0); - return @r; -} -sub ctx_statement { - my ($linenr, $remain, $off) = @_; - - my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off); - return @r; -} -sub ctx_block_level { - my ($linenr, $remain) = @_; - - return ctx_block_get($linenr, $remain, 0, '{', '}', 0); -} -sub ctx_statement_level { - my ($linenr, $remain, $off) = @_; - - return ctx_block_get($linenr, $remain, 0, '(', ')', $off); -} - -sub ctx_locate_comment { - my ($first_line, $end_line) = @_; - - # Catch a comment on the end of the line itself. - my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); - return $current_comment if (defined $current_comment); - - # Look through the context and try and figure out if there is a - # comment. - my $in_comment = 0; - $current_comment = ''; - for (my $linenr = $first_line; $linenr < $end_line; $linenr++) { - my $line = $rawlines[$linenr - 1]; - #warn " $line\n"; - if ($linenr == $first_line and $line =~ m@^.\s*\*@) { - $in_comment = 1; - } - if ($line =~ m@/\*@) { - $in_comment = 1; - } - if (!$in_comment && $current_comment ne '') { - $current_comment = ''; - } - $current_comment .= $line . "\n" if ($in_comment); - if ($line =~ m@\*/@) { - $in_comment = 0; - } - } - - chomp($current_comment); - return($current_comment); -} -sub ctx_has_comment { - my ($first_line, $end_line) = @_; - my $cmt = ctx_locate_comment($first_line, $end_line); - - ##print "LINE: $rawlines[$end_line - 1 ]\n"; - ##print "CMMT: $cmt\n"; - - return ($cmt ne ''); -} - -sub raw_line { - my ($linenr, $cnt) = @_; - - my $offset = $linenr - 1; - $cnt++; - - my $line; - while ($cnt) { - $line = $rawlines[$offset++]; - next if (defined($line) && $line =~ /^-/); - $cnt--; - } - - return $line; -} - -sub cat_vet { - my ($vet) = @_; - my ($res, $coded); - - $res = ''; - while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) { - $res .= $1; - if ($2 ne '') { - $coded = sprintf("^%c", unpack('C', $2) + 64); - $res .= $coded; - } - } - $res =~ s/$/\$/; - - return $res; -} - -my $av_preprocessor = 0; -my $av_pending; -my @av_paren_type; -my $av_pend_colon; - -sub annotate_reset { - $av_preprocessor = 0; - $av_pending = '_'; - @av_paren_type = ('E'); - $av_pend_colon = 'O'; -} - -sub annotate_values { - my ($stream, $type) = @_; - - my $res; - my $var = '_' x length($stream); - my $cur = $stream; - - print "$stream\n" if ($dbg_values > 1); - - while (length($cur)) { - @av_paren_type = ('E') if ($#av_paren_type < 0); - print " <" . join('', @av_paren_type) . - "> <$type> <$av_pending>" if ($dbg_values > 1); - if ($cur =~ /^(\s+)/o) { - print "WS($1)\n" if ($dbg_values > 1); - if ($1 =~ /\n/ && $av_preprocessor) { - $type = pop(@av_paren_type); - $av_preprocessor = 0; - } - - } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { - print "CAST($1)\n" if ($dbg_values > 1); - push(@av_paren_type, $type); - $type = 'c'; - - } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { - print "DECLARE($1)\n" if ($dbg_values > 1); - $type = 'T'; - - } elsif ($cur =~ /^($Modifier)\s*/) { - print "MODIFIER($1)\n" if ($dbg_values > 1); - $type = 'T'; - - } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) { - print "DEFINE($1,$2)\n" if ($dbg_values > 1); - $av_preprocessor = 1; - push(@av_paren_type, $type); - if ($2 ne '') { - $av_pending = 'N'; - } - $type = 'E'; - - } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) { - print "UNDEF($1)\n" if ($dbg_values > 1); - $av_preprocessor = 1; - push(@av_paren_type, $type); - - } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) { - print "PRE_START($1)\n" if ($dbg_values > 1); - $av_preprocessor = 1; - - push(@av_paren_type, $type); - push(@av_paren_type, $type); - $type = 'E'; - - } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) { - print "PRE_RESTART($1)\n" if ($dbg_values > 1); - $av_preprocessor = 1; - - push(@av_paren_type, $av_paren_type[$#av_paren_type]); - - $type = 'E'; - - } elsif ($cur =~ /^(\#\s*(?:endif))/o) { - print "PRE_END($1)\n" if ($dbg_values > 1); - - $av_preprocessor = 1; - - # Assume all arms of the conditional end as this - # one does, and continue as if the #endif was not here. - pop(@av_paren_type); - push(@av_paren_type, $type); - $type = 'E'; - - } elsif ($cur =~ /^(\\\n)/o) { - print "PRECONT($1)\n" if ($dbg_values > 1); - - } elsif ($cur =~ /^(__attribute__)\s*\(?/o) { - print "ATTR($1)\n" if ($dbg_values > 1); - $av_pending = $type; - $type = 'N'; - - } elsif ($cur =~ /^(sizeof)\s*(\()?/o) { - print "SIZEOF($1)\n" if ($dbg_values > 1); - if (defined $2) { - $av_pending = 'V'; - } - $type = 'N'; - - } elsif ($cur =~ /^(if|while|for)\b/o) { - print "COND($1)\n" if ($dbg_values > 1); - $av_pending = 'E'; - $type = 'N'; - - } elsif ($cur =~/^(case)/o) { - print "CASE($1)\n" if ($dbg_values > 1); - $av_pend_colon = 'C'; - $type = 'N'; - - } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) { - print "KEYWORD($1)\n" if ($dbg_values > 1); - $type = 'N'; - - } elsif ($cur =~ /^(\()/o) { - print "PAREN('$1')\n" if ($dbg_values > 1); - push(@av_paren_type, $av_pending); - $av_pending = '_'; - $type = 'N'; - - } elsif ($cur =~ /^(\))/o) { - my $new_type = pop(@av_paren_type); - if ($new_type ne '_') { - $type = $new_type; - print "PAREN('$1') -> $type\n" - if ($dbg_values > 1); - } else { - print "PAREN('$1')\n" if ($dbg_values > 1); - } - - } elsif ($cur =~ /^($Ident)\s*\(/o) { - print "FUNC($1)\n" if ($dbg_values > 1); - $type = 'V'; - $av_pending = 'V'; - - } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) { - if (defined $2 && $type eq 'C' || $type eq 'T') { - $av_pend_colon = 'B'; - } elsif ($type eq 'E') { - $av_pend_colon = 'L'; - } - print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1); - $type = 'V'; - - } elsif ($cur =~ /^($Ident|$Constant)/o) { - print "IDENT($1)\n" if ($dbg_values > 1); - $type = 'V'; - - } elsif ($cur =~ /^($Assignment)/o) { - print "ASSIGN($1)\n" if ($dbg_values > 1); - $type = 'N'; - - } elsif ($cur =~/^(;|{|})/) { - print "END($1)\n" if ($dbg_values > 1); - $type = 'E'; - $av_pend_colon = 'O'; - - } elsif ($cur =~/^(,)/) { - print "COMMA($1)\n" if ($dbg_values > 1); - $type = 'C'; - - } elsif ($cur =~ /^(\?)/o) { - print "QUESTION($1)\n" if ($dbg_values > 1); - $type = 'N'; - - } elsif ($cur =~ /^(:)/o) { - print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1); - - substr($var, length($res), 1, $av_pend_colon); - if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') { - $type = 'E'; - } else { - $type = 'N'; - } - $av_pend_colon = 'O'; - - } elsif ($cur =~ /^(\[)/o) { - print "CLOSE($1)\n" if ($dbg_values > 1); - $type = 'N'; - - } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) { - my $variant; - - print "OPV($1)\n" if ($dbg_values > 1); - if ($type eq 'V') { - $variant = 'B'; - } else { - $variant = 'U'; - } - - substr($var, length($res), 1, $variant); - $type = 'N'; - - } elsif ($cur =~ /^($Operators)/o) { - print "OP($1)\n" if ($dbg_values > 1); - if ($1 ne '++' && $1 ne '--') { - $type = 'N'; - } - - } elsif ($cur =~ /(^.)/o) { - print "C($1)\n" if ($dbg_values > 1); - } - if (defined $1) { - $cur = substr($cur, length($1)); - $res .= $type x length($1); - } - } - - return ($res, $var); -} - -sub possible { - my ($possible, $line) = @_; - my $notPermitted = qr{(?: - ^(?: - $Modifier| - $Storage| - $Type| - DEFINE_\S+ - )$| - ^(?: - goto| - return| - case| - else| - asm|__asm__| - do| - \#| - \#\#| - )(?:\s|$)| - ^(?:typedef|struct|enum)\b - )}x; - warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2); - if ($possible !~ $notPermitted) { - # Check for modifiers. - $possible =~ s/\s*$Storage\s*//g; - $possible =~ s/\s*$Sparse\s*//g; - if ($possible =~ /^\s*$/) { - - } elsif ($possible =~ /\s/) { - $possible =~ s/\s*$Type\s*//g; - for my $modifier (split(' ', $possible)) { - if ($modifier !~ $notPermitted) { - warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); - push(@modifierList, $modifier); - } - } - - } else { - warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); - push(@typeList, $possible); - } - build_types(); - } else { - warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1); - } -} - -my $prefix = ''; - -sub show_type { - return !defined $ignore_type{$_[0]}; -} - -sub report { - if (!show_type($_[1]) || - (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) { - return 0; - } - my $line; - if ($show_types) { - $line = "$prefix$_[0]:$_[1]: $_[2]\n"; - } else { - $line = "$prefix$_[0]: $_[2]\n"; - } - $line = (split('\n', $line))[0] . "\n" if ($terse); - - push(our @report, $line); - - return 1; -} -sub report_dump { - our @report; -} - -sub ERROR { - if (report("ERROR", $_[0], $_[1])) { - our $clean = 0; - our $cnt_error++; - } -} -sub WARN { - if (report("WARNING", $_[0], $_[1])) { - our $clean = 0; - our $cnt_warn++; - } -} -sub CHK { - if ($check && report("CHECK", $_[0], $_[1])) { - our $clean = 0; - our $cnt_chk++; - } -} - -sub check_absolute_file { - my ($absolute, $herecurr) = @_; - my $file = $absolute; - - ##print "absolute<$absolute>\n"; - - # See if any suffix of this path is a path within the tree. - while ($file =~ s@^[^/]*/@@) { - if (-f "$root/$file") { - ##print "file<$file>\n"; - last; - } - } - if (! -f _) { - return 0; - } - - # It is, so see if the prefix is acceptable. - my $prefix = $absolute; - substr($prefix, -length($file)) = ''; - - ##print "prefix<$prefix>\n"; - if ($prefix ne ".../") { - WARN("USE_RELATIVE_PATH", - "use relative pathname instead of absolute in changelog text\n" . $herecurr); - } -} - -sub pos_last_openparen { - my ($line) = @_; - - my $pos = 0; - - my $opens = $line =~ tr/\(/\(/; - my $closes = $line =~ tr/\)/\)/; - - my $last_openparen = 0; - - if (($opens == 0) || ($closes >= $opens)) { - return -1; - } - - my $len = length($line); - - for ($pos = 0; $pos < $len; $pos++) { - my $string = substr($line, $pos); - if ($string =~ /^($FuncArg|$balanced_parens)/) { - $pos += length($1) - 1; - } elsif (substr($line, $pos, 1) eq '(') { - $last_openparen = $pos; - } elsif (index($string, '(') == -1) { - last; - } - } - - return $last_openparen + 1; -} - -sub process { - my $filename = shift; - - my $linenr=0; - my $prevline=""; - my $prevrawline=""; - my $stashline=""; - my $stashrawline=""; - - my $length; - my $indent; - my $previndent=0; - my $stashindent=0; - - our $clean = 1; - my $signoff = 0; - my $is_patch = 0; - - my $in_header_lines = 1; - my $in_commit_log = 0; #Scanning lines before patch - - my $non_utf8_charset = 0; - - our @report = (); - our $cnt_lines = 0; - our $cnt_error = 0; - our $cnt_warn = 0; - our $cnt_chk = 0; - - # Trace the real file/line as we go. - my $realfile = ''; - my $realline = 0; - my $realcnt = 0; - my $here = ''; - my $in_comment = 0; - my $comment_edge = 0; - my $first_line = 0; - my $p1_prefix = ''; - - my $prev_values = 'E'; - - # suppression flags - my %suppress_ifbraces; - my %suppress_whiletrailers; - my %suppress_export; - my $suppress_statement = 0; - - my %camelcase = (); - - # Pre-scan the patch sanitizing the lines. - # Pre-scan the patch looking for any __setup documentation. - # - my @setup_docs = (); - my $setup_docs = 0; - - sanitise_line_reset(); - my $line; - foreach my $rawline (@rawlines) { - $linenr++; - $line = $rawline; - - if ($rawline=~/^\+\+\+\s+(\S+)/) { - $setup_docs = 0; - if ($1 =~ m@Documentation/kernel-parameters.txt$@) { - $setup_docs = 1; - } - #next; - } - if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { - $realline=$1-1; - if (defined $2) { - $realcnt=$3+1; - } else { - $realcnt=1+1; - } - $in_comment = 0; - - # Guestimate if this is a continuing comment. Run - # the context looking for a comment "edge". If this - # edge is a close comment then we must be in a comment - # at context start. - my $edge; - my $cnt = $realcnt; - for (my $ln = $linenr + 1; $cnt > 0; $ln++) { - next if (defined $rawlines[$ln - 1] && - $rawlines[$ln - 1] =~ /^-/); - $cnt--; - #print "RAW<$rawlines[$ln - 1]>\n"; - last if (!defined $rawlines[$ln - 1]); - if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ && - $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) { - ($edge) = $1; - last; - } - } - if (defined $edge && $edge eq '*/') { - $in_comment = 1; - } - - # Guestimate if this is a continuing comment. If this - # is the start of a diff block and this line starts - # ' *' then it is very likely a comment. - if (!defined $edge && - $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@) - { - $in_comment = 1; - } - - ##print "COMMENT:$in_comment edge<$edge> $rawline\n"; - sanitise_line_reset($in_comment); - - } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) { - # Standardise the strings and chars within the input to - # simplify matching -- only bother with positive lines. - $line = sanitise_line($rawline); - } - push(@lines, $line); - - if ($realcnt > 1) { - $realcnt-- if ($line =~ /^(?:\+| |$)/); - } else { - $realcnt = 0; - } - - #print "==>$rawline\n"; - #print "-->$line\n"; - - if ($setup_docs && $line =~ /^\+/) { - push(@setup_docs, $line); - } - } - - $prefix = ''; - - $realcnt = 0; - $linenr = 0; - foreach my $line (@lines) { - $linenr++; - - my $rawline = $rawlines[$linenr - 1]; - -#extract the line range in the file after the patch is applied - if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { - $is_patch = 1; - $first_line = $linenr + 1; - $realline=$1-1; - if (defined $2) { - $realcnt=$3+1; - } else { - $realcnt=1+1; - } - annotate_reset(); - $prev_values = 'E'; - - %suppress_ifbraces = (); - %suppress_whiletrailers = (); - %suppress_export = (); - $suppress_statement = 0; - next; - -# track the line number as we move through the hunk, note that -# new versions of GNU diff omit the leading space on completely -# blank context lines so we need to count that too. - } elsif ($line =~ /^( |\+|$)/) { - $realline++; - $realcnt-- if ($realcnt != 0); - - # Measure the line length and indent. - ($length, $indent) = line_stats($rawline); - - # Track the previous line. - ($prevline, $stashline) = ($stashline, $line); - ($previndent, $stashindent) = ($stashindent, $indent); - ($prevrawline, $stashrawline) = ($stashrawline, $rawline); - - #warn "line<$line>\n"; - - } elsif ($realcnt == 1) { - $realcnt--; - } - - my $hunk_line = ($realcnt != 0); - -#make up the handle for any error we report on this line - $prefix = "$filename:$realline: " if ($emacs && $file); - $prefix = "$filename:$linenr: " if ($emacs && !$file); - - $here = "#$linenr: " if (!$file); - $here = "#$realline: " if ($file); - - # extract the filename as it passes - if ($line =~ /^diff --git.*?(\S+)$/) { - $realfile = $1; - $realfile =~ s@^([^/]*)/@@; - $in_commit_log = 0; - } elsif ($line =~ /^\+\+\+\s+(\S+)/) { - $realfile = $1; - $realfile =~ s@^([^/]*)/@@; - $in_commit_log = 0; - - $p1_prefix = $1; - if (!$file && $tree && $p1_prefix ne '' && - -e "$root/$p1_prefix") { - WARN("PATCH_PREFIX", - "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n"); - } - - if ($realfile =~ m@^include/asm/@) { - ERROR("MODIFIED_INCLUDE_ASM", - "do not modify files in include/asm, change architecture specific files in include/asm-\n" . "$here$rawline\n"); - } - next; - } - - $here .= "FILE: $realfile:$realline:" if ($realcnt != 0); - - my $hereline = "$here\n$rawline\n"; - my $herecurr = "$here\n$rawline\n"; - my $hereprev = "$here\n$prevrawline\n$rawline\n"; - - $cnt_lines++ if ($realcnt != 0); - -# Check for incorrect file permissions - if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { - my $permhere = $here . "FILE: $realfile\n"; - if ($realfile =~ /(Makefile|Kconfig|\.c|\.h|\.S|\.tmpl)$/) { - ERROR("EXECUTE_PERMISSIONS", - "do not set execute permissions for source files\n" . $permhere); - } - } - -# Check the patch for a signoff: - if ($line =~ /^\s*signed-off-by:/i) { - $signoff++; - $in_commit_log = 0; - } - -# Check signature styles - if (!$in_header_lines && - $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { - my $space_before = $1; - my $sign_off = $2; - my $space_after = $3; - my $email = $4; - my $ucfirst_sign_off = ucfirst(lc($sign_off)); - - if ($sign_off !~ /$signature_tags/) { - WARN("BAD_SIGN_OFF", - "Non-standard signature: $sign_off\n" . $herecurr); - } - if (defined $space_before && $space_before ne "") { - WARN("BAD_SIGN_OFF", - "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr); - } - if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { - WARN("BAD_SIGN_OFF", - "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr); - } - if (!defined $space_after || $space_after ne " ") { - WARN("BAD_SIGN_OFF", - "Use a single space after $ucfirst_sign_off\n" . $herecurr); - } - - my ($email_name, $email_address, $comment) = parse_email($email); - my $suggested_email = format_email(($email_name, $email_address)); - if ($suggested_email eq "") { - ERROR("BAD_SIGN_OFF", - "Unrecognized email address: '$email'\n" . $herecurr); - } else { - my $dequoted = $suggested_email; - $dequoted =~ s/^"//; - $dequoted =~ s/" $comment" ne $email && - "$suggested_email$comment" ne $email) { - WARN("BAD_SIGN_OFF", - "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); - } - } - } - -# Check for wrappage within a valid hunk of the file - if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { - ERROR("CORRUPTED_PATCH", - "patch seems to be corrupt (line wrapped?)\n" . - $herecurr) if (!$emitted_corrupt++); - } - -# Check for absolute kernel paths. - if ($tree) { - while ($line =~ m{(?:^|\s)(/\S*)}g) { - my $file = $1; - - if ($file =~ m{^(.*?)(?::\d+)+:?$} && - check_absolute_file($1, $herecurr)) { - # - } else { - check_absolute_file($file, $herecurr); - } - } - } - -# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php - if (($realfile =~ /^$/ || $line =~ /^\+/) && - $rawline !~ m/^$UTF8*$/) { - my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/); - - my $blank = copy_spacing($rawline); - my $ptr = substr($blank, 0, length($utf8_prefix)) . "^"; - my $hereptr = "$hereline$ptr\n"; - - CHK("INVALID_UTF8", - "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); - } - -# Check if it's the start of a commit log -# (not a header line and we haven't seen the patch filename) - if ($in_header_lines && $realfile =~ /^$/ && - $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) { - $in_header_lines = 0; - $in_commit_log = 1; - } - -# Check if there is UTF-8 in a commit log when a mail header has explicitly -# declined it, i.e defined some charset where it is missing. - if ($in_header_lines && - $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && - $1 !~ /utf-8/i) { - $non_utf8_charset = 1; - } - - if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && - $rawline =~ /$NON_ASCII_UTF8/) { - WARN("UTF8_BEFORE_PATCH", - "8-bit UTF-8 used in possible commit log\n" . $herecurr); - } - -# ignore non-hunk lines and lines being removed - next if (!$hunk_line || $line =~ /^-/); - -#trailing whitespace - if ($line =~ /^\+.*\015/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("DOS_LINE_ENDINGS", - "DOS line endings\n" . $herevet); - - } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("TRAILING_WHITESPACE", - "trailing whitespace\n" . $herevet); - $rpt_cleaners = 1; - } - -# check for Kconfig help text having a real description -# Only applies when adding the entry originally, after that we do not have -# sufficient context to determine whether it is indeed long enough. - if ($realfile =~ /Kconfig/ && - $line =~ /.\s*config\s+/) { - my $length = 0; - my $cnt = $realcnt; - my $ln = $linenr + 1; - my $f; - my $is_start = 0; - my $is_end = 0; - for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) { - $f = $lines[$ln - 1]; - $cnt-- if ($lines[$ln - 1] !~ /^-/); - $is_end = $lines[$ln - 1] =~ /^\+/; - - next if ($f =~ /^-/); - - if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) { - $is_start = 1; - } elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) { - $length = -1; - } - - $f =~ s/^.//; - $f =~ s/#.*//; - $f =~ s/^\s+//; - next if ($f =~ /^$/); - if ($f =~ /^\s*config\s/) { - $is_end = 1; - last; - } - $length++; - } - WARN("CONFIG_DESCRIPTION", - "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4); - #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; - } - -# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig. - if ($realfile =~ /Kconfig/ && - $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) { - WARN("CONFIG_EXPERIMENTAL", - "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); - } - - if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && - ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { - my $flag = $1; - my $replacement = { - 'EXTRA_AFLAGS' => 'asflags-y', - 'EXTRA_CFLAGS' => 'ccflags-y', - 'EXTRA_CPPFLAGS' => 'cppflags-y', - 'EXTRA_LDFLAGS' => 'ldflags-y', - }; - - WARN("DEPRECATED_VARIABLE", - "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); - } - -# check we are in a valid source file if not then ignore this hunk - next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); - -#line length limit - if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && - $rawline !~ /^.\s*\*\s*\@$Ident\s/ && - !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ || - $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && - $length > $max_line_length) - { - WARN("LONG_LINE", - "line over $max_line_length characters\n" . $herecurr); - } - -# Check for user-visible strings broken across lines, which breaks the ability -# to grep for the string. Limited to strings used as parameters (those -# following an open parenthesis), which almost completely eliminates false -# positives, as well as warning only once per parameter rather than once per -# line of the string. Make an exception when the previous string ends in a -# newline (multiple lines in one string constant) or \n\t (common in inline -# assembly to indent the instruction on the following line). - if ($line =~ /^\+\s*"/ && - $prevline =~ /"\s*$/ && - $prevline =~ /\(/ && - $prevrawline !~ /\\n(?:\\t)*"\s*$/) { - WARN("SPLIT_STRING", - "quoted string split across lines\n" . $hereprev); - } - -# check for spaces before a quoted newline - if ($rawline =~ /^.*\".*\s\\n/) { - WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", - "unnecessary whitespace before a quoted newline\n" . $herecurr); - } - -# check for adding lines without a newline. - if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { - WARN("MISSING_EOF_NEWLINE", - "adding a line without newline at end of file\n" . $herecurr); - } - -# Blackfin: use hi/lo macros - if ($realfile =~ m@arch/blackfin/.*\.S$@) { - if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("LO_MACRO", - "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); - } - if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("HI_MACRO", - "use the HI() macro, not (... >> 16)\n" . $herevet); - } - } - -# check we are in a valid source file C or perl if not then ignore this hunk - next if ($realfile !~ /\.(h|c|pl)$/); - -# at the beginning of a line any tabs must come first and anything -# more than 8 must use tabs. - if ($rawline =~ /^\+\s* \t\s*\S/ || - $rawline =~ /^\+\s* \s*/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("CODE_INDENT", - "code indent should use tabs where possible\n" . $herevet); - $rpt_cleaners = 1; - } - -# check for space before tabs. - if ($rawline =~ /^\+/ && $rawline =~ / \t/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - WARN("SPACE_BEFORE_TAB", - "please, no space before tabs\n" . $herevet); - } - -# check for && or || at the start of a line - if ($rawline =~ /^\+\s*(&&|\|\|)/) { - CHK("LOGICAL_CONTINUATIONS", - "Logical continuations should be on the previous line\n" . $hereprev); - } - -# check multi-line statement indentation matches previous line - if ($^V && $^V ge 5.10.0 && - $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) { - $prevline =~ /^\+(\t*)(.*)$/; - my $oldindent = $1; - my $rest = $2; - - my $pos = pos_last_openparen($rest); - if ($pos >= 0) { - $line =~ /^(\+| )([ \t]*)/; - my $newindent = $2; - - my $goodtabindent = $oldindent . - "\t" x ($pos / 8) . - " " x ($pos % 8); - my $goodspaceindent = $oldindent . " " x $pos; - - if ($newindent ne $goodtabindent && - $newindent ne $goodspaceindent) { - CHK("PARENTHESIS_ALIGNMENT", - "Alignment should match open parenthesis\n" . $hereprev); - } - } - } - - if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) { - CHK("SPACING", - "No space is necessary after a cast\n" . $hereprev); - } - - if ($realfile =~ m@^(drivers/net/|net/)@ && - $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ && - $prevrawline =~ /^\+[ \t]*$/) { - WARN("NETWORKING_BLOCK_COMMENT_STYLE", - "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); - } - - if ($realfile =~ m@^(drivers/net/|net/)@ && - $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ - $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ - $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ - $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ - WARN("NETWORKING_BLOCK_COMMENT_STYLE", - "networking block comments put the trailing */ on a separate line\n" . $herecurr); - } - -# check for spaces at the beginning of a line. -# Exceptions: -# 1) within comments -# 2) indented preprocessor commands -# 3) hanging labels - if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - WARN("LEADING_SPACE", - "please, no spaces at the start of a line\n" . $herevet); - } - -# check we are in a valid C source file if not then ignore this hunk - next if ($realfile !~ /\.(h|c)$/); - -# discourage the addition of CONFIG_EXPERIMENTAL in #if(def). - if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) { - WARN("CONFIG_EXPERIMENTAL", - "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); - } - -# check for RCS/CVS revision markers - if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { - WARN("CVS_KEYWORD", - "CVS style keyword markers, these will _not_ be updated\n". $herecurr); - } - -# Blackfin: don't use __builtin_bfin_[cs]sync - if ($line =~ /__builtin_bfin_csync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("CSYNC", - "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); - } - if ($line =~ /__builtin_bfin_ssync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("SSYNC", - "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); - } - -# check for old HOTPLUG __dev section markings - if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { - WARN("HOTPLUG_SECTION", - "Using $1 is unnecessary\n" . $herecurr); - } - -# Check for potential 'bare' types - my ($stat, $cond, $line_nr_next, $remain_next, $off_next, - $realline_next); -#print "LINE<$line>\n"; - if ($linenr >= $suppress_statement && - $realcnt && $line =~ /.\s*\S/) { - ($stat, $cond, $line_nr_next, $remain_next, $off_next) = - ctx_statement_block($linenr, $realcnt, 0); - $stat =~ s/\n./\n /g; - $cond =~ s/\n./\n /g; - -#print "linenr<$linenr> <$stat>\n"; - # If this statement has no statement boundaries within - # it there is no point in retrying a statement scan - # until we hit end of it. - my $frag = $stat; $frag =~ s/;+\s*$//; - if ($frag !~ /(?:{|;)/) { -#print "skip<$line_nr_next>\n"; - $suppress_statement = $line_nr_next; - } - - # Find the real next line. - $realline_next = $line_nr_next; - if (defined $realline_next && - (!defined $lines[$realline_next - 1] || - substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) { - $realline_next++; - } - - my $s = $stat; - $s =~ s/{.*$//s; - - # Ignore goto labels. - if ($s =~ /$Ident:\*$/s) { - - # Ignore functions being called - } elsif ($s =~ /^.\s*$Ident\s*\(/s) { - - } elsif ($s =~ /^.\s*else\b/s) { - - # declarations always start with types - } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) { - my $type = $1; - $type =~ s/\s+/ /g; - possible($type, "A:" . $s); - - # definitions in global scope can only start with types - } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) { - possible($1, "B:" . $s); - } - - # any (foo ... *) is a pointer cast, and foo is a type - while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) { - possible($1, "C:" . $s); - } - - # Check for any sort of function declaration. - # int foo(something bar, other baz); - # void (*store_gdt)(x86_descr_ptr *); - if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) { - my ($name_len) = length($1); - - my $ctx = $s; - substr($ctx, 0, $name_len + 1, ''); - $ctx =~ s/\)[^\)]*$//; - - for my $arg (split(/\s*,\s*/, $ctx)) { - if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) { - - possible($1, "D:" . $s); - } - } - } - - } - -# -# Checks which may be anchored in the context. -# - -# Check for switch () and associated case and default -# statements should be at the same indent. - if ($line=~/\bswitch\s*\(.*\)/) { - my $err = ''; - my $sep = ''; - my @ctx = ctx_block_outer($linenr, $realcnt); - shift(@ctx); - for my $ctx (@ctx) { - my ($clen, $cindent) = line_stats($ctx); - if ($ctx =~ /^\+\s*(case\s+|default:)/ && - $indent != $cindent) { - $err .= "$sep$ctx\n"; - $sep = ''; - } else { - $sep = "[...]\n"; - } - } - if ($err ne '') { - ERROR("SWITCH_CASE_INDENT_LEVEL", - "switch and case should be at the same indent\n$hereline$err"); - } - } - -# if/while/etc brace do not go on next line, unless defining a do while loop, -# or if that brace on the next line is for something else - if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { - my $pre_ctx = "$1$2"; - - my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); - - if ($line =~ /^\+\t{6,}/) { - WARN("DEEP_INDENTATION", - "Too many leading tabs - consider code refactoring\n" . $herecurr); - } - - my $ctx_cnt = $realcnt - $#ctx - 1; - my $ctx = join("\n", @ctx); - - my $ctx_ln = $linenr; - my $ctx_skip = $realcnt; - - while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt && - defined $lines[$ctx_ln - 1] && - $lines[$ctx_ln - 1] =~ /^-/)) { - ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n"; - $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/); - $ctx_ln++; - } - - #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; - #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; - - if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { - ERROR("OPEN_BRACE", - "that open brace { should be on the previous line\n" . - "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); - } - if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ && - $ctx =~ /\)\s*\;\s*$/ && - defined $lines[$ctx_ln - 1]) - { - my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]); - if ($nindent > $indent) { - WARN("TRAILING_SEMICOLON", - "trailing semicolon indicates no statements, indent implies otherwise\n" . - "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); - } - } - } - -# Check relative indent for conditionals and blocks. - if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { - ($stat, $cond, $line_nr_next, $remain_next, $off_next) = - ctx_statement_block($linenr, $realcnt, 0) - if (!defined $stat); - my ($s, $c) = ($stat, $cond); - - substr($s, 0, length($c), ''); - - # Make sure we remove the line prefixes as we have - # none on the first line, and are going to readd them - # where necessary. - $s =~ s/\n./\n/gs; - - # Find out how long the conditional actually is. - my @newlines = ($c =~ /\n/gs); - my $cond_lines = 1 + $#newlines; - - # We want to check the first line inside the block - # starting at the end of the conditional, so remove: - # 1) any blank line termination - # 2) any opening brace { on end of the line - # 3) any do (...) { - my $continuation = 0; - my $check = 0; - $s =~ s/^.*\bdo\b//; - $s =~ s/^\s*{//; - if ($s =~ s/^\s*\\//) { - $continuation = 1; - } - if ($s =~ s/^\s*?\n//) { - $check = 1; - $cond_lines++; - } - - # Also ignore a loop construct at the end of a - # preprocessor statement. - if (($prevline =~ /^.\s*#\s*define\s/ || - $prevline =~ /\\\s*$/) && $continuation == 0) { - $check = 0; - } - - my $cond_ptr = -1; - $continuation = 0; - while ($cond_ptr != $cond_lines) { - $cond_ptr = $cond_lines; - - # If we see an #else/#elif then the code - # is not linear. - if ($s =~ /^\s*\#\s*(?:else|elif)/) { - $check = 0; - } - - # Ignore: - # 1) blank lines, they should be at 0, - # 2) preprocessor lines, and - # 3) labels. - if ($continuation || - $s =~ /^\s*?\n/ || - $s =~ /^\s*#\s*?/ || - $s =~ /^\s*$Ident\s*:/) { - $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0; - if ($s =~ s/^.*?\n//) { - $cond_lines++; - } - } - } - - my (undef, $sindent) = line_stats("+" . $s); - my $stat_real = raw_line($linenr, $cond_lines); - - # Check if either of these lines are modified, else - # this is not this patch's fault. - if (!defined($stat_real) || - $stat !~ /^\+/ && $stat_real !~ /^\+/) { - $check = 0; - } - if (defined($stat_real) && $cond_lines > 1) { - $stat_real = "[...]\n$stat_real"; - } - - #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; - - if ($check && (($sindent % 8) != 0 || - ($sindent <= $indent && $s ne ''))) { - WARN("SUSPECT_CODE_INDENT", - "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); - } - } - - # Track the 'values' across context and added lines. - my $opline = $line; $opline =~ s/^./ /; - my ($curr_values, $curr_vars) = - annotate_values($opline . "\n", $prev_values); - $curr_values = $prev_values . $curr_values; - if ($dbg_values) { - my $outline = $opline; $outline =~ s/\t/ /g; - print "$linenr > .$outline\n"; - print "$linenr > $curr_values\n"; - print "$linenr > $curr_vars\n"; - } - $prev_values = substr($curr_values, -1); - -#ignore lines not being added - if ($line=~/^[^\+]/) {next;} - -# TEST: allow direct testing of the type matcher. - if ($dbg_type) { - if ($line =~ /^.\s*$Declare\s*$/) { - ERROR("TEST_TYPE", - "TEST: is type\n" . $herecurr); - } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) { - ERROR("TEST_NOT_TYPE", - "TEST: is not type ($1 is)\n". $herecurr); - } - next; - } -# TEST: allow direct testing of the attribute matcher. - if ($dbg_attr) { - if ($line =~ /^.\s*$Modifier\s*$/) { - ERROR("TEST_ATTR", - "TEST: is attr\n" . $herecurr); - } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) { - ERROR("TEST_NOT_ATTR", - "TEST: is not attr ($1 is)\n". $herecurr); - } - next; - } - -# check for initialisation to aggregates open brace on the next line - if ($line =~ /^.\s*{/ && - $prevline =~ /(?:^|[^=])=\s*$/) { - ERROR("OPEN_BRACE", - "that open brace { should be on the previous line\n" . $hereprev); - } - -# -# Checks which are anchored on the added line. -# - -# check for malformed paths in #include statements (uses RAW line) - if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) { - my $path = $1; - if ($path =~ m{//}) { - ERROR("MALFORMED_INCLUDE", - "malformed #include filename\n" . $herecurr); - } - if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { - ERROR("UAPI_INCLUDE", - "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); - } - } - -# no C99 // comments - if ($line =~ m{//}) { - ERROR("C99_COMMENTS", - "do not use C99 // comments\n" . $herecurr); - } - # Remove C99 comments. - $line =~ s@//.*@@; - $opline =~ s@//.*@@; - -# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider -# the whole statement. -#print "APW <$lines[$realline_next - 1]>\n"; - if (defined $realline_next && - exists $lines[$realline_next - 1] && - !defined $suppress_export{$realline_next} && - ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || - $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { - # Handle definitions which produce identifiers with - # a prefix: - # XXX(foo); - # EXPORT_SYMBOL(something_foo); - my $name = $1; - if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && - $name =~ /^${Ident}_$2/) { -#print "FOO C name<$name>\n"; - $suppress_export{$realline_next} = 1; - - } elsif ($stat !~ /(?: - \n.}\s*$| - ^.DEFINE_$Ident\(\Q$name\E\)| - ^.DECLARE_$Ident\(\Q$name\E\)| - ^.LIST_HEAD\(\Q$name\E\)| - ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(| - \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\() - )/x) { -#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n"; - $suppress_export{$realline_next} = 2; - } else { - $suppress_export{$realline_next} = 1; - } - } - if (!defined $suppress_export{$linenr} && - $prevline =~ /^.\s*$/ && - ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || - $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { -#print "FOO B <$lines[$linenr - 1]>\n"; - $suppress_export{$linenr} = 2; - } - if (defined $suppress_export{$linenr} && - $suppress_export{$linenr} == 2) { - WARN("EXPORT_SYMBOL", - "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr); - } - -# check for global initialisers. - if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) { - ERROR("GLOBAL_INITIALISERS", - "do not initialise globals to 0 or NULL\n" . - $herecurr); - } -# check for static initialisers. - if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) { - ERROR("INITIALISED_STATIC", - "do not initialise statics to 0 or NULL\n" . - $herecurr); - } - -# check for static const char * arrays. - if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) { - WARN("STATIC_CONST_CHAR_ARRAY", - "static const char * array should probably be static const char * const\n" . - $herecurr); - } - -# check for static char foo[] = "bar" declarations. - if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { - WARN("STATIC_CONST_CHAR_ARRAY", - "static char array declaration should probably be static const char\n" . - $herecurr); - } - -# check for declarations of struct pci_device_id - if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) { - WARN("DEFINE_PCI_DEVICE_TABLE", - "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr); - } - -# check for new typedefs, only function parameters and sparse annotations -# make sense. - if ($line =~ /\btypedef\s/ && - $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && - $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && - $line !~ /\b$typeTypedefs\b/ && - $line !~ /\b__bitwise(?:__|)\b/) { - WARN("NEW_TYPEDEFS", - "do not add new typedefs\n" . $herecurr); - } - -# * goes on variable not on type - # (char*[ const]) - while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { - #print "AA<$1>\n"; - my ($from, $to) = ($2, $2); - - # Should start with a space. - $to =~ s/^(\S)/ $1/; - # Should not end with a space. - $to =~ s/\s+$//; - # '*'s should not have spaces between. - while ($to =~ s/\*\s+\*/\*\*/) { - } - - #print "from<$from> to<$to>\n"; - if ($from ne $to) { - ERROR("POINTER_LOCATION", - "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr); - } - } - while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { - #print "BB<$1>\n"; - my ($from, $to, $ident) = ($2, $2, $3); - - # Should start with a space. - $to =~ s/^(\S)/ $1/; - # Should not end with a space. - $to =~ s/\s+$//; - # '*'s should not have spaces between. - while ($to =~ s/\*\s+\*/\*\*/) { - } - # Modifiers should have spaces. - $to =~ s/(\b$Modifier$)/$1 /; - - #print "from<$from> to<$to> ident<$ident>\n"; - if ($from ne $to && $ident !~ /^$Modifier$/) { - ERROR("POINTER_LOCATION", - "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr); - } - } - -# # no BUG() or BUG_ON() -# if ($line =~ /\b(BUG|BUG_ON)\b/) { -# print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n"; -# print "$herecurr"; -# $clean = 0; -# } - - if ($line =~ /\bLINUX_VERSION_CODE\b/) { - WARN("LINUX_VERSION_CODE", - "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); - } - -# check for uses of printk_ratelimit - if ($line =~ /\bprintk_ratelimit\s*\(/) { - WARN("PRINTK_RATELIMITED", -"Prefer printk_ratelimited or pr__ratelimited to printk_ratelimit\n" . $herecurr); - } - -# printk should use KERN_* levels. Note that follow on printk's on the -# same line do not need a level, so we use the current block context -# to try and find and validate the current printk. In summary the current -# printk includes all preceding printk's which have no newline on the end. -# we assume the first bad printk is the one to report. - if ($line =~ /\bprintk\((?!KERN_)\s*"/) { - my $ok = 0; - for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { - #print "CHECK<$lines[$ln - 1]\n"; - # we have a preceding printk if it ends - # with "\n" ignore it, else it is to blame - if ($lines[$ln - 1] =~ m{\bprintk\(}) { - if ($rawlines[$ln - 1] !~ m{\\n"}) { - $ok = 1; - } - last; - } - } - if ($ok == 0) { - WARN("PRINTK_WITHOUT_KERN_LEVEL", - "printk() should include KERN_ facility level\n" . $herecurr); - } - } - - if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { - my $orig = $1; - my $level = lc($orig); - $level = "warn" if ($level eq "warning"); - my $level2 = $level; - $level2 = "dbg" if ($level eq "debug"); - WARN("PREFER_PR_LEVEL", - "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); - } - - if ($line =~ /\bpr_warning\s*\(/) { - WARN("PREFER_PR_LEVEL", - "Prefer pr_warn(... to pr_warning(...\n" . $herecurr); - } - - if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { - my $orig = $1; - my $level = lc($orig); - $level = "warn" if ($level eq "warning"); - $level = "dbg" if ($level eq "debug"); - WARN("PREFER_DEV_LEVEL", - "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); - } - -# function brace can't be on same line, except for #defines of do while, -# or if closed on same line - if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and - !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) { - ERROR("OPEN_BRACE", - "open brace '{' following function declarations go on the next line\n" . $herecurr); - } - -# open braces for enum, union and struct go on the same line. - if ($line =~ /^.\s*{/ && - $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { - ERROR("OPEN_BRACE", - "open brace '{' following $1 go on the same line\n" . $hereprev); - } - -# missing space after union, struct or enum definition - if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) { - WARN("SPACING", - "missing space after $1 definition\n" . $herecurr); - } - -# check for spacing round square brackets; allowed: -# 1. with a type on the left -- int [] a; -# 2. at the beginning of a line for slice initialisers -- [0...10] = 5, -# 3. inside a curly brace -- = { [0...10] = 5 } - while ($line =~ /(.*?\s)\[/g) { - my ($where, $prefix) = ($-[1], $1); - if ($prefix !~ /$Type\s+$/ && - ($where != 0 || $prefix !~ /^.\s+$/) && - $prefix !~ /[{,]\s+$/) { - ERROR("BRACKET_SPACE", - "space prohibited before open square bracket '['\n" . $herecurr); - } - } - -# check for spaces between functions and their parentheses. - while ($line =~ /($Ident)\s+\(/g) { - my $name = $1; - my $ctx_before = substr($line, 0, $-[1]); - my $ctx = "$ctx_before$name"; - - # Ignore those directives where spaces _are_ permitted. - if ($name =~ /^(?: - if|for|while|switch|return|case| - volatile|__volatile__| - __attribute__|format|__extension__| - asm|__asm__)$/x) - { - - # cpp #define statements have non-optional spaces, ie - # if there is a space between the name and the open - # parenthesis it is simply not a parameter group. - } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) { - - # cpp #elif statement condition may start with a ( - } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) { - - # If this whole things ends with a type its most - # likely a typedef for a function. - } elsif ($ctx =~ /$Type$/) { - - } else { - WARN("SPACING", - "space prohibited between function name and open parenthesis '('\n" . $herecurr); - } - } - -# check for whitespace before a non-naked semicolon - if ($line =~ /^\+.*\S\s+;/) { - CHK("SPACING", - "space prohibited before semicolon\n" . $herecurr); - } - -# Check operator spacing. - if (!($line=~/\#\s*include/)) { - my $ops = qr{ - <<=|>>=|<=|>=|==|!=| - \+=|-=|\*=|\/=|%=|\^=|\|=|&=| - =>|->|<<|>>|<|>|=|!|~| - &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| - \?|: - }x; - my @elements = split(/($ops|;)/, $opline); - my $off = 0; - - my $blank = copy_spacing($opline); - - for (my $n = 0; $n < $#elements; $n += 2) { - $off += length($elements[$n]); - - # Pick up the preceding and succeeding characters. - my $ca = substr($opline, 0, $off); - my $cc = ''; - if (length($opline) >= ($off + length($elements[$n + 1]))) { - $cc = substr($opline, $off + length($elements[$n + 1])); - } - my $cb = "$ca$;$cc"; - - my $a = ''; - $a = 'V' if ($elements[$n] ne ''); - $a = 'W' if ($elements[$n] =~ /\s$/); - $a = 'C' if ($elements[$n] =~ /$;$/); - $a = 'B' if ($elements[$n] =~ /(\[|\()$/); - $a = 'O' if ($elements[$n] eq ''); - $a = 'E' if ($ca =~ /^\s*$/); - - my $op = $elements[$n + 1]; - - my $c = ''; - if (defined $elements[$n + 2]) { - $c = 'V' if ($elements[$n + 2] ne ''); - $c = 'W' if ($elements[$n + 2] =~ /^\s/); - $c = 'C' if ($elements[$n + 2] =~ /^$;/); - $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/); - $c = 'O' if ($elements[$n + 2] eq ''); - $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/); - } else { - $c = 'E'; - } - - my $ctx = "${a}x${c}"; - - my $at = "(ctx:$ctx)"; - - my $ptr = substr($blank, 0, $off) . "^"; - my $hereptr = "$hereline$ptr\n"; - - # Pull out the value of this operator. - my $op_type = substr($curr_values, $off + 1, 1); - - # Get the full operator variant. - my $opv = $op . substr($curr_vars, $off, 1); - - # Ignore operators passed as parameters. - if ($op_type ne 'V' && - $ca =~ /\s$/ && $cc =~ /^\s*,/) { - -# # Ignore comments -# } elsif ($op =~ /^$;+$/) { - - # ; should have either the end of line or a space or \ after it - } elsif ($op eq ';') { - if ($ctx !~ /.x[WEBC]/ && - $cc !~ /^\\/ && $cc !~ /^;/) { - ERROR("SPACING", - "space required after that '$op' $at\n" . $hereptr); - } - - # // is a comment - } elsif ($op eq '//') { - - # No spaces for: - # -> - # : when part of a bitfield - } elsif ($op eq '->' || $opv eq ':B') { - if ($ctx =~ /Wx.|.xW/) { - ERROR("SPACING", - "spaces prohibited around that '$op' $at\n" . $hereptr); - } - - # , must have a space on the right. - } elsif ($op eq ',') { - if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { - ERROR("SPACING", - "space required after that '$op' $at\n" . $hereptr); - } - - # '*' as part of a type definition -- reported already. - } elsif ($opv eq '*_') { - #warn "'*' is part of type\n"; - - # unary operators should have a space before and - # none after. May be left adjacent to another - # unary operator, or a cast - } elsif ($op eq '!' || $op eq '~' || - $opv eq '*U' || $opv eq '-U' || - $opv eq '&U' || $opv eq '&&U') { - if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { - ERROR("SPACING", - "space required before that '$op' $at\n" . $hereptr); - } - if ($op eq '*' && $cc =~/\s*$Modifier\b/) { - # A unary '*' may be const - - } elsif ($ctx =~ /.xW/) { - ERROR("SPACING", - "space prohibited after that '$op' $at\n" . $hereptr); - } - - # unary ++ and unary -- are allowed no space on one side. - } elsif ($op eq '++' or $op eq '--') { - if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { - ERROR("SPACING", - "space required one side of that '$op' $at\n" . $hereptr); - } - if ($ctx =~ /Wx[BE]/ || - ($ctx =~ /Wx./ && $cc =~ /^;/)) { - ERROR("SPACING", - "space prohibited before that '$op' $at\n" . $hereptr); - } - if ($ctx =~ /ExW/) { - ERROR("SPACING", - "space prohibited after that '$op' $at\n" . $hereptr); - } - - - # << and >> may either have or not have spaces both sides - } elsif ($op eq '<<' or $op eq '>>' or - $op eq '&' or $op eq '^' or $op eq '|' or - $op eq '+' or $op eq '-' or - $op eq '*' or $op eq '/' or - $op eq '%') - { - if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { - ERROR("SPACING", - "need consistent spacing around '$op' $at\n" . - $hereptr); - } - - # A colon needs no spaces before when it is - # terminating a case value or a label. - } elsif ($opv eq ':C' || $opv eq ':L') { - if ($ctx =~ /Wx./) { - ERROR("SPACING", - "space prohibited before that '$op' $at\n" . $hereptr); - } - - # All the others need spaces both sides. - } elsif ($ctx !~ /[EWC]x[CWE]/) { - my $ok = 0; - - # Ignore email addresses - if (($op eq '<' && - $cc =~ /^\S+\@\S+>/) || - ($op eq '>' && - $ca =~ /<\S+\@\S+$/)) - { - $ok = 1; - } - - # Ignore ?: - if (($opv eq ':O' && $ca =~ /\?$/) || - ($op eq '?' && $cc =~ /^:/)) { - $ok = 1; - } - - if ($ok == 0) { - ERROR("SPACING", - "spaces required around that '$op' $at\n" . $hereptr); - } - } - $off += length($elements[$n + 1]); - } - } - -# check for multiple assignments - if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) { - CHK("MULTIPLE_ASSIGNMENTS", - "multiple assignments should be avoided\n" . $herecurr); - } - -## # check for multiple declarations, allowing for a function declaration -## # continuation. -## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ && -## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { -## -## # Remove any bracketed sections to ensure we do not -## # falsly report the parameters of functions. -## my $ln = $line; -## while ($ln =~ s/\([^\(\)]*\)//g) { -## } -## if ($ln =~ /,/) { -## WARN("MULTIPLE_DECLARATION", -## "declaring multiple variables together should be avoided\n" . $herecurr); -## } -## } - -#need space before brace following if, while, etc - if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) || - $line =~ /do{/) { - ERROR("SPACING", - "space required before the open brace '{'\n" . $herecurr); - } - -# closing brace should have a space following it when it has anything -# on the line - if ($line =~ /}(?!(?:,|;|\)))\S/) { - ERROR("SPACING", - "space required after that close brace '}'\n" . $herecurr); - } - -# check spacing on square brackets - if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { - ERROR("SPACING", - "space prohibited after that open square bracket '['\n" . $herecurr); - } - if ($line =~ /\s\]/) { - ERROR("SPACING", - "space prohibited before that close square bracket ']'\n" . $herecurr); - } - -# check spacing on parentheses - if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && - $line !~ /for\s*\(\s+;/) { - ERROR("SPACING", - "space prohibited after that open parenthesis '('\n" . $herecurr); - } - if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && - $line !~ /for\s*\(.*;\s+\)/ && - $line !~ /:\s+\)/) { - ERROR("SPACING", - "space prohibited before that close parenthesis ')'\n" . $herecurr); - } - -#goto labels aren't indented, allow a single space however - if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and - !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { - WARN("INDENTED_LABEL", - "labels should not be indented\n" . $herecurr); - } - -# Return is not a function. - if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) { - my $spacing = $1; - my $value = $2; - - # Flatten any parentheses - $value =~ s/\(/ \(/g; - $value =~ s/\)/\) /g; - while ($value =~ s/\[[^\[\]]*\]/1/ || - $value !~ /(?:$Ident|-?$Constant)\s* - $Compare\s* - (?:$Ident|-?$Constant)/x && - $value =~ s/\([^\(\)]*\)/1/) { - } -#print "value<$value>\n"; - if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) { - ERROR("RETURN_PARENTHESES", - "return is not a function, parentheses are not required\n" . $herecurr); - - } elsif ($spacing !~ /\s+/) { - ERROR("SPACING", - "space required before the open parenthesis '('\n" . $herecurr); - } - } -# Return of what appears to be an errno should normally be -'ve - if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { - my $name = $1; - if ($name ne 'EOF' && $name ne 'ERROR') { - WARN("USE_NEGATIVE_ERRNO", - "return of an errno should typically be -ve (return -$1)\n" . $herecurr); - } - } - -# Need a space before open parenthesis after if, while etc - if ($line=~/\b(if|while|for|switch)\(/) { - ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); - } - -# Check for illegal assignment in if conditional -- and check for trailing -# statements after the conditional. - if ($line =~ /do\s*(?!{)/) { - ($stat, $cond, $line_nr_next, $remain_next, $off_next) = - ctx_statement_block($linenr, $realcnt, 0) - if (!defined $stat); - my ($stat_next) = ctx_statement_block($line_nr_next, - $remain_next, $off_next); - $stat_next =~ s/\n./\n /g; - ##print "stat<$stat> stat_next<$stat_next>\n"; - - if ($stat_next =~ /^\s*while\b/) { - # If the statement carries leading newlines, - # then count those as offsets. - my ($whitespace) = - ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s); - my $offset = - statement_rawlines($whitespace) - 1; - - $suppress_whiletrailers{$line_nr_next + - $offset} = 1; - } - } - if (!defined $suppress_whiletrailers{$linenr} && - $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { - my ($s, $c) = ($stat, $cond); - - if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { - ERROR("ASSIGN_IN_IF", - "do not use assignment in if condition\n" . $herecurr); - } - - # Find out what is on the end of the line after the - # conditional. - substr($s, 0, length($c), ''); - $s =~ s/\n.*//g; - $s =~ s/$;//g; # Remove any comments - if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && - $c !~ /}\s*while\s*/) - { - # Find out how long the conditional actually is. - my @newlines = ($c =~ /\n/gs); - my $cond_lines = 1 + $#newlines; - my $stat_real = ''; - - $stat_real = raw_line($linenr, $cond_lines) - . "\n" if ($cond_lines); - if (defined($stat_real) && $cond_lines > 1) { - $stat_real = "[...]\n$stat_real"; - } - - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . $herecurr . $stat_real); - } - } - -# Check for bitwise tests written as boolean - if ($line =~ / - (?: - (?:\[|\(|\&\&|\|\|) - \s*0[xX][0-9]+\s* - (?:\&\&|\|\|) - | - (?:\&\&|\|\|) - \s*0[xX][0-9]+\s* - (?:\&\&|\|\||\)|\]) - )/x) - { - WARN("HEXADECIMAL_BOOLEAN_TEST", - "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr); - } - -# if and else should not have general statements after it - if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { - my $s = $1; - $s =~ s/$;//g; # Remove any comments - if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . $herecurr); - } - } -# if should not continue a brace - if ($line =~ /}\s*if\b/) { - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . - $herecurr); - } -# case and default should not have general statements after them - if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g && - $line !~ /\G(?: - (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$| - \s*return\s+ - )/xg) - { - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . $herecurr); - } - - # Check for }else {, these must be at the same - # indent level to be relevant to each other. - if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and - $previndent == $indent) { - ERROR("ELSE_AFTER_BRACE", - "else should follow close brace '}'\n" . $hereprev); - } - - if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and - $previndent == $indent) { - my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); - - # Find out what is on the end of the line after the - # conditional. - substr($s, 0, length($c), ''); - $s =~ s/\n.*//g; - - if ($s =~ /^\s*;/) { - ERROR("WHILE_AFTER_BRACE", - "while should follow close brace '}'\n" . $hereprev); - } - } - -#CamelCase - while ($line =~ m{($Constant|$Lval)}g) { - my $var = $1; - if ($var !~ /$Constant/ && - $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ && - $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && - !defined $camelcase{$var}) { - $camelcase{$var} = 1; - WARN("CAMELCASE", - "Avoid CamelCase: <$var>\n" . $herecurr); - } - } - -#no spaces allowed after \ in define - if ($line=~/\#\s*define.*\\\s$/) { - WARN("WHITESPACE_AFTER_LINE_CONTINUATION", - "Whitepspace after \\ makes next lines useless\n" . $herecurr); - } - -#warn if is #included and is available (uses RAW line) - if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\}) { - my $file = "$1.h"; - my $checkfile = "include/linux/$file"; - if (-f "$root/$checkfile" && - $realfile ne $checkfile && - $1 !~ /$allowed_asm_includes/) - { - if ($realfile =~ m{^arch/}) { - CHK("ARCH_INCLUDE_LINUX", - "Consider using #include instead of \n" . $herecurr); - } else { - WARN("INCLUDE_LINUX", - "Use #include instead of \n" . $herecurr); - } - } - } - -# multi-statement macros should be enclosed in a do while loop, grab the -# first statement and ensure its the whole macro if its not enclosed -# in a known good container - if ($realfile !~ m@/vmlinux.lds.h$@ && - $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) { - my $ln = $linenr; - my $cnt = $realcnt; - my ($off, $dstat, $dcond, $rest); - my $ctx = ''; - ($dstat, $dcond, $ln, $cnt, $off) = - ctx_statement_block($linenr, $realcnt, 0); - $ctx = $dstat; - #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; - #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; - - $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//; - $dstat =~ s/$;//g; - $dstat =~ s/\\\n.//g; - $dstat =~ s/^\s*//s; - $dstat =~ s/\s*$//s; - - # Flatten any parentheses and braces - while ($dstat =~ s/\([^\(\)]*\)/1/ || - $dstat =~ s/\{[^\{\}]*\}/1/ || - $dstat =~ s/\[[^\[\]]*\]/1/) - { - } - - # Flatten any obvious string concatentation. - while ($dstat =~ s/("X*")\s*$Ident/$1/ || - $dstat =~ s/$Ident\s*("X*")/$1/) - { - } - - my $exceptions = qr{ - $Declare| - module_param_named| - MODULE_PARM_DESC| - DECLARE_PER_CPU| - DEFINE_PER_CPU| - __typeof__\(| - union| - struct| - \.$Ident\s*=\s*| - ^\"|\"$ - }x; - #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; - if ($dstat ne '' && - $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), - $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); - $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo - $dstat !~ /^'X'$/ && # character constants - $dstat !~ /$exceptions/ && - $dstat !~ /^\.$Ident\s*=/ && # .foo = - $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) - $dstat !~ /^for\s*$Constant$/ && # for (...) - $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() - $dstat !~ /^do\s*{/ && # do {... - $dstat !~ /^\({/) # ({... - { - $ctx =~ s/\n*$//; - my $herectx = $here . "\n"; - my $cnt = statement_rawlines($ctx); - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } - - if ($dstat =~ /;/) { - ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", - "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); - } else { - ERROR("COMPLEX_MACRO", - "Macros with complex values should be enclosed in parenthesis\n" . "$herectx"); - } - } - -# check for line continuations outside of #defines, preprocessor #, and asm - - } else { - if ($prevline !~ /^..*\\$/ && - $line !~ /^\+\s*\#.*\\$/ && # preprocessor - $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm - $line =~ /^\+.*\\$/) { - WARN("LINE_CONTINUATIONS", - "Avoid unnecessary line continuations\n" . $herecurr); - } - } - -# do {} while (0) macro tests: -# single-statement macros do not need to be enclosed in do while (0) loop, -# macro should not end with a semicolon - if ($^V && $^V ge 5.10.0 && - $realfile !~ m@/vmlinux.lds.h$@ && - $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { - my $ln = $linenr; - my $cnt = $realcnt; - my ($off, $dstat, $dcond, $rest); - my $ctx = ''; - ($dstat, $dcond, $ln, $cnt, $off) = - ctx_statement_block($linenr, $realcnt, 0); - $ctx = $dstat; - - $dstat =~ s/\\\n.//g; - - if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { - my $stmts = $2; - my $semis = $3; - - $ctx =~ s/\n*$//; - my $cnt = statement_rawlines($ctx); - my $herectx = $here . "\n"; - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } - - if (($stmts =~ tr/;/;/) == 1 && - $stmts !~ /^\s*(if|while|for|switch)\b/) { - WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", - "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); - } - if (defined $semis && $semis ne "") { - WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", - "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); - } - } - } - -# make sure symbols are always wrapped with VMLINUX_SYMBOL() ... -# all assignments may have only one of the following with an assignment: -# . -# ALIGN(...) -# VMLINUX_SYMBOL(...) - if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) { - WARN("MISSING_VMLINUX_SYMBOL", - "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr); - } - -# check for redundant bracing round if etc - if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) { - my ($level, $endln, @chunks) = - ctx_statement_full($linenr, $realcnt, 1); - #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; - #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n"; - if ($#chunks > 0 && $level == 0) { - my @allowed = (); - my $allow = 0; - my $seen = 0; - my $herectx = $here . "\n"; - my $ln = $linenr - 1; - for my $chunk (@chunks) { - my ($cond, $block) = @{$chunk}; - - # If the condition carries leading newlines, then count those as offsets. - my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); - my $offset = statement_rawlines($whitespace) - 1; - - $allowed[$allow] = 0; - #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; - - # We have looked at and allowed this specific line. - $suppress_ifbraces{$ln + $offset} = 1; - - $herectx .= "$rawlines[$ln + $offset]\n[...]\n"; - $ln += statement_rawlines($block) - 1; - - substr($block, 0, length($cond), ''); - - $seen++ if ($block =~ /^\s*{/); - - #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; - if (statement_lines($cond) > 1) { - #print "APW: ALLOWED: cond<$cond>\n"; - $allowed[$allow] = 1; - } - if ($block =~/\b(?:if|for|while)\b/) { - #print "APW: ALLOWED: block<$block>\n"; - $allowed[$allow] = 1; - } - if (statement_block_size($block) > 1) { - #print "APW: ALLOWED: lines block<$block>\n"; - $allowed[$allow] = 1; - } - $allow++; - } - if ($seen) { - my $sum_allowed = 0; - foreach (@allowed) { - $sum_allowed += $_; - } - if ($sum_allowed == 0) { - WARN("BRACES", - "braces {} are not necessary for any arm of this statement\n" . $herectx); - } elsif ($sum_allowed != $allow && - $seen != $allow) { - CHK("BRACES", - "braces {} should be used on all arms of this statement\n" . $herectx); - } - } - } - } - if (!defined $suppress_ifbraces{$linenr - 1} && - $line =~ /\b(if|while|for|else)\b/) { - my $allowed = 0; - - # Check the pre-context. - if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) { - #print "APW: ALLOWED: pre<$1>\n"; - $allowed = 1; - } - - my ($level, $endln, @chunks) = - ctx_statement_full($linenr, $realcnt, $-[0]); - - # Check the condition. - my ($cond, $block) = @{$chunks[0]}; - #print "CHECKING<$linenr> cond<$cond> block<$block>\n"; - if (defined $cond) { - substr($block, 0, length($cond), ''); - } - if (statement_lines($cond) > 1) { - #print "APW: ALLOWED: cond<$cond>\n"; - $allowed = 1; - } - if ($block =~/\b(?:if|for|while)\b/) { - #print "APW: ALLOWED: block<$block>\n"; - $allowed = 1; - } - if (statement_block_size($block) > 1) { - #print "APW: ALLOWED: lines block<$block>\n"; - $allowed = 1; - } - # Check the post-context. - if (defined $chunks[1]) { - my ($cond, $block) = @{$chunks[1]}; - if (defined $cond) { - substr($block, 0, length($cond), ''); - } - if ($block =~ /^\s*\{/) { - #print "APW: ALLOWED: chunk-1 block<$block>\n"; - $allowed = 1; - } - } - if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { - my $herectx = $here . "\n"; - my $cnt = statement_rawlines($block); - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } - - WARN("BRACES", - "braces {} are not necessary for single statement blocks\n" . $herectx); - } - } - -# check for unnecessary blank lines around braces - if (($line =~ /^..*}\s*$/ && $prevline =~ /^.\s*$/)) { - CHK("BRACES", - "Blank lines aren't necessary before a close brace '}'\n" . $hereprev); - } - if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { - CHK("BRACES", - "Blank lines aren't necessary after an open brace '{'\n" . $hereprev); - } - -# no volatiles please - my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; - if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { - WARN("VOLATILE", - "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr); - } - -# warn about #if 0 - if ($line =~ /^.\s*\#\s*if\s+0\b/) { - CHK("REDUNDANT_CODE", - "if this code is redundant consider removing it\n" . - $herecurr); - } - -# check for needless "if () fn()" uses - if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { - my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;'; - if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) { - WARN('NEEDLESS_IF', - "$1(NULL) is safe this check is probably not required\n" . $hereprev); - } - } - -# prefer usleep_range over udelay - if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { - # ignore udelay's < 10, however - if (! ($1 < 10) ) { - CHK("USLEEP_RANGE", - "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line); - } - } - -# warn about unexpectedly long msleep's - if ($line =~ /\bmsleep\s*\((\d+)\);/) { - if ($1 < 20) { - WARN("MSLEEP", - "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line); - } - } - -# warn about #ifdefs in C files -# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { -# print "#ifdef in C files should be avoided\n"; -# print "$herecurr"; -# $clean = 0; -# } - -# warn about spacing in #ifdefs - if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { - ERROR("SPACING", - "exactly one space required after that #$1\n" . $herecurr); - } - -# check for spinlock_t definitions without a comment. - if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ || - $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) { - my $which = $1; - if (!ctx_has_comment($first_line, $linenr)) { - CHK("UNCOMMENTED_DEFINITION", - "$1 definition without comment\n" . $herecurr); - } - } -# check for memory barriers without a comment. - if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { - if (!ctx_has_comment($first_line, $linenr)) { - CHK("MEMORY_BARRIER", - "memory barrier without comment\n" . $herecurr); - } - } -# check of hardware specific defines - if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { - CHK("ARCH_DEFINES", - "architecture specific defines should be avoided\n" . $herecurr); - } - -# Check that the storage class is at the beginning of a declaration - if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { - WARN("STORAGE_CLASS", - "storage class should be at the beginning of the declaration\n" . $herecurr) - } - -# check the location of the inline attribute, that it is between -# storage class and type. - if ($line =~ /\b$Type\s+$Inline\b/ || - $line =~ /\b$Inline\s+$Storage\b/) { - ERROR("INLINE_LOCATION", - "inline keyword should sit between storage class and type\n" . $herecurr); - } - -# Check for __inline__ and __inline, prefer inline - if ($line =~ /\b(__inline__|__inline)\b/) { - WARN("INLINE", - "plain inline is preferred over $1\n" . $herecurr); - } - -# Check for __attribute__ packed, prefer __packed - if ($line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { - WARN("PREFER_PACKED", - "__packed is preferred over __attribute__((packed))\n" . $herecurr); - } - -# Check for __attribute__ aligned, prefer __aligned - if ($line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { - WARN("PREFER_ALIGNED", - "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); - } - -# Check for __attribute__ format(printf, prefer __printf - if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { - WARN("PREFER_PRINTF", - "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr); - } - -# Check for __attribute__ format(scanf, prefer __scanf - if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { - WARN("PREFER_SCANF", - "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr); - } - -# check for sizeof(&) - if ($line =~ /\bsizeof\s*\(\s*\&/) { - WARN("SIZEOF_ADDRESS", - "sizeof(& should be avoided\n" . $herecurr); - } - -# check for sizeof without parenthesis - if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { - WARN("SIZEOF_PARENTHESIS", - "sizeof $1 should be sizeof($1)\n" . $herecurr); - } - -# check for line continuations in quoted strings with odd counts of " - if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { - WARN("LINE_CONTINUATIONS", - "Avoid line continuations in quoted strings\n" . $herecurr); - } - -# check for struct spinlock declarations - if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { - WARN("USE_SPINLOCK_T", - "struct spinlock should be spinlock_t\n" . $herecurr); - } - -# Check for misused memsets - if ($^V && $^V ge 5.10.0 && - defined $stat && - $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) { - - my $ms_addr = $2; - my $ms_val = $7; - my $ms_size = $12; - - if ($ms_size =~ /^(0x|)0$/i) { - ERROR("MEMSET", - "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); - } elsif ($ms_size =~ /^(0x|)1$/i) { - WARN("MEMSET", - "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); - } - } - -# typecasts on min/max could be min_t/max_t - if ($^V && $^V ge 5.10.0 && - defined $stat && - $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { - if (defined $2 || defined $7) { - my $call = $1; - my $cast1 = deparenthesize($2); - my $arg1 = $3; - my $cast2 = deparenthesize($7); - my $arg2 = $8; - my $cast; - - if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { - $cast = "$cast1 or $cast2"; - } elsif ($cast1 ne "") { - $cast = $cast1; - } else { - $cast = $cast2; - } - WARN("MINMAX", - "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); - } - } - -# check usleep_range arguments - if ($^V && $^V ge 5.10.0 && - defined $stat && - $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { - my $min = $1; - my $max = $7; - if ($min eq $max) { - WARN("USLEEP_RANGE", - "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); - } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && - $min > $max) { - WARN("USLEEP_RANGE", - "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); - } - } - -# check for new externs in .c files. - if ($realfile =~ /\.c$/ && defined $stat && - $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) - { - my $function_name = $1; - my $paren_space = $2; - - my $s = $stat; - if (defined $cond) { - substr($s, 0, length($cond), ''); - } - if ($s =~ /^\s*;/ && - $function_name ne 'uninitialized_var') - { - WARN("AVOID_EXTERNS", - "externs should be avoided in .c files\n" . $herecurr); - } - - if ($paren_space =~ /\n/) { - WARN("FUNCTION_ARGUMENTS", - "arguments for function declarations should follow identifier\n" . $herecurr); - } - - } elsif ($realfile =~ /\.c$/ && defined $stat && - $stat =~ /^.\s*extern\s+/) - { - WARN("AVOID_EXTERNS", - "externs should be avoided in .c files\n" . $herecurr); - } - -# checks for new __setup's - if ($rawline =~ /\b__setup\("([^"]*)"/) { - my $name = $1; - - if (!grep(/$name/, @setup_docs)) { - CHK("UNDOCUMENTED_SETUP", - "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr); - } - } - -# check for pointless casting of kmalloc return - if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) { - WARN("UNNECESSARY_CASTS", - "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); - } - -# check for alloc argument mismatch - if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { - WARN("ALLOC_ARRAY_ARGS", - "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); - } - -# check for multiple semicolons - if ($line =~ /;\s*;\s*$/) { - WARN("ONE_SEMICOLON", - "Statements terminations use 1 semicolon\n" . $herecurr); - } - -# check for switch/default statements without a break; - if ($^V && $^V ge 5.10.0 && - defined $stat && - $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { - my $ctx = ''; - my $herectx = $here . "\n"; - my $cnt = statement_rawlines($stat); - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } - WARN("DEFAULT_NO_BREAK", - "switch default: should use break\n" . $herectx); - } - -# check for gcc specific __FUNCTION__ - if ($line =~ /__FUNCTION__/) { - WARN("USE_FUNC", - "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr); - } - -# check for use of yield() - if ($line =~ /\byield\s*\(\s*\)/) { - WARN("YIELD", - "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); - } - -# check for semaphores initialized locked - if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { - WARN("CONSIDER_COMPLETION", - "consider using a completion\n" . $herecurr); - } - -# recommend kstrto* over simple_strto* and strict_strto* - if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { - WARN("CONSIDER_KSTRTO", - "$1 is obsolete, use k$3 instead\n" . $herecurr); - } - -# check for __initcall(), use device_initcall() explicitly please - if ($line =~ /^.\s*__initcall\s*\(/) { - WARN("USE_DEVICE_INITCALL", - "please use device_initcall() instead of __initcall()\n" . $herecurr); - } - -# check for various ops structs, ensure they are const. - my $struct_ops = qr{acpi_dock_ops| - address_space_operations| - backlight_ops| - block_device_operations| - dentry_operations| - dev_pm_ops| - dma_map_ops| - extent_io_ops| - file_lock_operations| - file_operations| - hv_ops| - ide_dma_ops| - intel_dvo_dev_ops| - item_operations| - iwl_ops| - kgdb_arch| - kgdb_io| - kset_uevent_ops| - lock_manager_operations| - microcode_ops| - mtrr_ops| - neigh_ops| - nlmsvc_binding| - pci_raw_ops| - pipe_buf_operations| - platform_hibernation_ops| - platform_suspend_ops| - proto_ops| - rpc_pipe_ops| - seq_operations| - snd_ac97_build_ops| - soc_pcmcia_socket_ops| - stacktrace_ops| - sysfs_ops| - tty_operations| - usb_mon_operations| - wd_ops}x; - if ($line !~ /\bconst\b/ && - $line =~ /\bstruct\s+($struct_ops)\b/) { - WARN("CONST_STRUCT", - "struct $1 should normally be const\n" . - $herecurr); - } - -# use of NR_CPUS is usually wrong -# ignore definitions of NR_CPUS and usage to define arrays as likely right - if ($line =~ /\bNR_CPUS\b/ && - $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && - $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && - $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && - $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && - $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) - { - WARN("NR_CPUS", - "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); - } - -# check for %L{u,d,i} in strings - my $string; - while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { - $string = substr($rawline, $-[1], $+[1] - $-[1]); - $string =~ s/%%/__/g; - if ($string =~ /(?mutex.\n" . $herecurr); - } - } - - if ($line =~ /debugfs_create_file.*S_IWUGO/ || - $line =~ /DEVICE_ATTR.*S_IWUGO/ ) { - WARN("EXPORTED_WORLD_WRITABLE", - "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); - } - } - - # If we have no input at all, then there is nothing to report on - # so just keep quiet. - if ($#rawlines == -1) { - exit(0); - } - - # In mailback mode only produce a report in the negative, for - # things that appear to be patches. - if ($mailback && ($clean == 1 || !$is_patch)) { - exit(0); - } - - # This is not a patch, and we are are in 'no-patch' mode so - # just keep quiet. - if (!$chk_patch && !$is_patch) { - exit(0); - } - - if (!$is_patch) { - ERROR("NOT_UNIFIED_DIFF", - "Does not appear to be a unified-diff format patch\n"); - } - if ($is_patch && $chk_signoff && $signoff == 0) { - ERROR("MISSING_SIGN_OFF", - "Missing Signed-off-by: line(s)\n"); - } - - print report_dump(); - if ($summary && !($clean == 1 && $quiet == 1)) { - print "$filename " if ($summary_file); - print "total: $cnt_error errors, $cnt_warn warnings, " . - (($check)? "$cnt_chk checks, " : "") . - "$cnt_lines lines checked\n"; - print "\n" if ($quiet == 0); - } - - if ($quiet == 0) { - - if ($^V lt 5.10.0) { - print("NOTE: perl $^V is not modern enough to detect all possible issues.\n"); - print("An upgrade to at least perl v5.10.0 is suggested.\n\n"); - } - - # If there were whitespace errors which cleanpatch can fix - # then suggest that. - if ($rpt_cleaners) { - print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n"; - print " scripts/cleanfile\n\n"; - $rpt_cleaners = 0; - } - } - - if ($quiet == 0 && keys %ignore_type) { - print "NOTE: Ignored message types:"; - foreach my $ignore (sort keys %ignore_type) { - print " $ignore"; - } - print "\n\n"; - } - - if ($clean == 1 && $quiet == 0) { - print "$vname has no obvious style problems and is ready for submission.\n" - } - if ($clean == 0 && $quiet == 0) { - print << "EOM"; -$vname has style problems, please review. - -If any of these errors are false positives, please report -them to the maintainer, see CHECKPATCH in MAINTAINERS. -EOM - } - - return $clean; -} diff --git a/tools/default_image.c b/tools/default_image.c index fd8b9f5f15..cf5c0d4393 100644 --- a/tools/default_image.c +++ b/tools/default_image.c @@ -14,7 +14,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include "imagetool.h" #include "mkimage.h" + #include #include @@ -29,7 +31,7 @@ static int image_check_image_types(uint8_t type) return EXIT_FAILURE; } -static int image_check_params(struct mkimage_params *params) +static int image_check_params(struct image_tool_params *params) { return ((params->dflag && (params->fflag || params->lflag)) || (params->fflag && (params->dflag || params->lflag)) || @@ -37,7 +39,7 @@ static int image_check_params(struct mkimage_params *params) } static int image_verify_header(unsigned char *ptr, int image_size, - struct mkimage_params *params) + struct image_tool_params *params) { uint32_t len; const unsigned char *data; @@ -53,9 +55,8 @@ static int image_verify_header(unsigned char *ptr, int image_size, memcpy(hdr, ptr, sizeof(image_header_t)); if (be32_to_cpu(hdr->ih_magic) != IH_MAGIC) { - fprintf(stderr, - "%s: Bad Magic Number: \"%s\" is no valid image\n", - params->cmdname, params->imagefile); + debug("%s: Bad Magic Number: \"%s\" is no valid image\n", + params->cmdname, params->imagefile); return -FDT_ERR_BADMAGIC; } @@ -66,9 +67,8 @@ static int image_verify_header(unsigned char *ptr, int image_size, hdr->ih_hcrc = cpu_to_be32(0); /* clear for re-calculation */ if (crc32(0, data, len) != checksum) { - fprintf(stderr, - "%s: ERROR: \"%s\" has bad header checksum!\n", - params->cmdname, params->imagefile); + debug("%s: ERROR: \"%s\" has bad header checksum!\n", + params->cmdname, params->imagefile); return -FDT_ERR_BADSTATE; } @@ -77,16 +77,15 @@ static int image_verify_header(unsigned char *ptr, int image_size, checksum = be32_to_cpu(hdr->ih_dcrc); if (crc32(0, data, len) != checksum) { - fprintf(stderr, - "%s: ERROR: \"%s\" has corrupted data!\n", - params->cmdname, params->imagefile); + debug("%s: ERROR: \"%s\" has corrupted data!\n", + params->cmdname, params->imagefile); return -FDT_ERR_BADSTRUCTURE; } return 0; } static void image_set_header(void *ptr, struct stat *sbuf, int ifd, - struct mkimage_params *params) + struct image_tool_params *params) { uint32_t checksum; @@ -117,21 +116,50 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, image_set_hcrc(hdr, checksum); } +static int image_extract_subimage(void *ptr, struct image_tool_params *params) +{ + const image_header_t *hdr = (const image_header_t *)ptr; + ulong file_data; + ulong file_len; + + if (image_check_type(hdr, IH_TYPE_MULTI)) { + ulong idx = params->pflag; + ulong count; + + /* get the number of data files present in the image */ + count = image_multi_count(hdr); + + /* retrieve the "data file" at the idx position */ + image_multi_getimg(hdr, idx, &file_data, &file_len); + + if ((file_len == 0) || (idx >= count)) { + fprintf(stderr, "%s: No such data file %ld in \"%s\"\n", + params->cmdname, idx, params->imagefile); + return -1; + } + } else { + file_data = image_get_data(hdr); + file_len = image_get_size(hdr); + } + + /* save the "data file" into the file system */ + return imagetool_save_subimage(params->outfile, file_data, file_len); +} + /* * Default image type parameters definition */ -static struct image_type_params defimage_params = { - .name = "Default Image support", - .header_size = sizeof(image_header_t), - .hdr = (void*)&header, - .check_image_type = image_check_image_types, - .verify_header = image_verify_header, - .print_header = image_print_contents, - .set_header = image_set_header, - .check_params = image_check_params, -}; - -void init_default_image_type(void) -{ - mkimage_register(&defimage_params); -} +U_BOOT_IMAGE_TYPE( + defimage, + "Default Image support", + sizeof(image_header_t), + (void *)&header, + image_check_params, + image_verify_header, + image_print_contents, + image_set_header, + image_extract_subimage, + image_check_image_types, + NULL, + NULL +); diff --git a/tools/dumpimage.c b/tools/dumpimage.c new file mode 100644 index 0000000000..75a5d4762c --- /dev/null +++ b/tools/dumpimage.c @@ -0,0 +1,211 @@ +/* + * Based on mkimage.c. + * + * Written by Guilherme Maciel Ferreira + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "dumpimage.h" +#include +#include + +static void usage(void); + +/* parameters initialized by core will be used by the image type code */ +static struct image_tool_params params = { + .type = IH_TYPE_KERNEL, +}; + +/* + * dumpimage_extract_subimage - + * + * It scans all registered image types, + * verifies image_header for each supported image type + * if verification is successful, it extracts the desired file, + * indexed by pflag, from the image + * + * returns negative if input image format does not match with any of + * supported image types + */ +static int dumpimage_extract_subimage(struct image_type_params *tparams, + void *ptr, struct stat *sbuf) +{ + int retval = -1; + + if (tparams->verify_header) { + retval = tparams->verify_header((unsigned char *)ptr, + sbuf->st_size, ¶ms); + if (retval != 0) + return -1; + /* + * Extract the file from the image + * if verify is successful + */ + if (tparams->extract_subimage) { + retval = tparams->extract_subimage(ptr, ¶ms); + } else { + fprintf(stderr, + "%s: extract_subimage undefined for %s\n", + params.cmdname, tparams->name); + return -2; + } + } + + return retval; +} + +int main(int argc, char **argv) +{ + int opt; + int ifd = -1; + struct stat sbuf; + char *ptr; + int retval = 0; + struct image_type_params *tparams = NULL; + + params.cmdname = *argv; + + while ((opt = getopt(argc, argv, "li:o:T:p:V")) != -1) { + switch (opt) { + case 'l': + params.lflag = 1; + break; + case 'i': + params.imagefile = optarg; + params.iflag = 1; + break; + case 'o': + params.outfile = optarg; + break; + case 'T': + params.type = genimg_get_type_id(optarg); + if (params.type < 0) { + usage(); + } + break; + case 'p': + params.pflag = strtoul(optarg, &ptr, 10); + if (*ptr) { + fprintf(stderr, + "%s: invalid file position %s\n", + params.cmdname, *argv); + exit(EXIT_FAILURE); + } + break; + case 'V': + printf("dumpimage version %s\n", PLAIN_VERSION); + exit(EXIT_SUCCESS); + default: + usage(); + break; + } + } + + if (optind >= argc) + usage(); + + /* set tparams as per input type_id */ + tparams = imagetool_get_type(params.type); + if (tparams == NULL) { + fprintf(stderr, "%s: unsupported type: %s\n", + params.cmdname, genimg_get_type_name(params.type)); + exit(EXIT_FAILURE); + } + + /* + * check the passed arguments parameters meets the requirements + * as per image type to be generated/listed + */ + if (tparams->check_params) { + if (tparams->check_params(¶ms)) + usage(); + } + + if (params.iflag) + params.datafile = argv[optind]; + else + params.imagefile = argv[optind]; + if (!params.outfile) + params.outfile = params.datafile; + + ifd = open(params.imagefile, O_RDONLY|O_BINARY); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open \"%s\": %s\n", + params.cmdname, params.imagefile, + strerror(errno)); + exit(EXIT_FAILURE); + } + + if (params.lflag || params.iflag) { + if (fstat(ifd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat \"%s\": %s\n", + params.cmdname, params.imagefile, + strerror(errno)); + exit(EXIT_FAILURE); + } + + if ((uint32_t)sbuf.st_size < tparams->header_size) { + fprintf(stderr, + "%s: Bad size: \"%s\" is not valid image\n", + params.cmdname, params.imagefile); + exit(EXIT_FAILURE); + } + + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0); + if (ptr == MAP_FAILED) { + fprintf(stderr, "%s: Can't read \"%s\": %s\n", + params.cmdname, params.imagefile, + strerror(errno)); + exit(EXIT_FAILURE); + } + + /* + * Both calls bellow scan through dumpimage registry for all + * supported image types and verify the input image file + * header for match + */ + if (params.iflag) { + /* + * Extract the data files from within the matched + * image type. Returns the error code if not matched + */ + retval = dumpimage_extract_subimage(tparams, ptr, + &sbuf); + } else { + /* + * Print the image information for matched image type + * Returns the error code if not matched + */ + retval = imagetool_verify_print_header(ptr, &sbuf, + tparams, ¶ms); + } + + (void)munmap((void *)ptr, sbuf.st_size); + (void)close(ifd); + + return retval; + } + + (void)close(ifd); + + return EXIT_SUCCESS; +} + +static void usage(void) +{ + fprintf(stderr, "Usage: %s -l image\n" + " -l ==> list image header information\n", + params.cmdname); + fprintf(stderr, + " %s -i image -T type [-p position] [-o outfile] data_file\n" + " -i ==> extract from the 'image' a specific 'data_file'\n" + " -T ==> set image type to 'type'\n" + " -p ==> 'position' (starting at 0) of the 'data_file' inside the 'image'\n", + params.cmdname); + fprintf(stderr, + " %s -V ==> print version information and exit\n", + params.cmdname); + + exit(EXIT_FAILURE); +} diff --git a/tools/dumpimage.h b/tools/dumpimage.h new file mode 100644 index 0000000000..e415f14e14 --- /dev/null +++ b/tools/dumpimage.h @@ -0,0 +1,33 @@ +/* + * Based on mkimage.c. + * + * Written by Guilherme Maciel Ferreira + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DUMPIMAGE_H_ +#define _DUMPIMAGE_H_ + +#include "os_support.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fdt_host.h" +#include "imagetool.h" + +#undef DUMPIMAGE_DEBUG + +#ifdef DUMPIMAGE_DEBUG +#define debug(fmt, args...) printf(fmt, ##args) +#else +#define debug(fmt, args...) +#endif /* DUMPIMAGE_DEBUG */ + +#endif /* _DUMPIMAGE_H_ */ diff --git a/tools/easylogo/Makefile b/tools/easylogo/Makefile index d8e28b0e12..10aba2ba66 100644 --- a/tools/easylogo/Makefile +++ b/tools/easylogo/Makefile @@ -1,11 +1,3 @@ -include $(TOPDIR)/config.mk +hostprogs-y := easylogo -all: $(obj)easylogo - -$(obj)easylogo: $(SRCTREE)/tools/easylogo/easylogo.c - $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $^ - -clean: - rm -f $(obj)easylogo - -.PHONY: all clean +always := $(hostprogs-y) diff --git a/tools/env/.gitignore b/tools/env/.gitignore new file mode 100644 index 0000000000..804abacc6e --- /dev/null +++ b/tools/env/.gitignore @@ -0,0 +1,2 @@ +fw_printenv +fw_printenv_unstripped diff --git a/tools/env/Makefile b/tools/env/Makefile index 14d131b7b8..40164f7a35 100644 --- a/tools/env/Makefile +++ b/tools/env/Makefile @@ -5,39 +5,32 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -HOSTSRCS := $(SRCTREE)/lib/crc32.c fw_env.c fw_env_main.c -HOSTSRCS += $(SRCTREE)/lib/ctype.c $(SRCTREE)/lib/linux_string.c -HOSTSRCS += $(SRCTREE)/common/env_attr.c $(SRCTREE)/common/env_flags.c -HEADERS := fw_env.h $(OBJTREE)/include/config.h +# fw_printenv is supposed to run on the target system, which means it should be +# built with cross tools. Although it may look weird, we only replace "HOSTCC" +# with "CC" here for the maximum code reuse of scripts/Makefile.host. +HOSTCC = $(CC) # Compile for a hosted environment on the target -HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \ - -idirafter $(OBJTREE)/include2 \ - -idirafter $(OBJTREE)/include \ - -idirafter $(SRCTREE)/tools/env \ +HOST_EXTRACFLAGS = $(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \ + -idirafter $(srctree)/tools/env \ -DUSE_HOSTCC \ -DTEXT_BASE=$(TEXT_BASE) ifeq ($(MTD_VERSION),old) -HOSTCPPFLAGS += -DMTD_OLD +HOST_EXTRACFLAGS += -DMTD_OLD endif -all: $(obj)fw_printenv - -# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED -$(obj)fw_printenv: $(HOSTSRCS) $(HEADERS) - $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $(HOSTSRCS) - $(HOSTSTRIP) $@ - -clean: - rm -f $(obj)fw_printenv +always := fw_printenv +hostprogs-y := fw_printenv -######################################################################### +fw_printenv-objs := fw_env.o fw_env_main.o \ + crc32.o ctype.o linux_string.o \ + env_attr.o env_flags.o aes.o -include $(TOPDIR)/rules.mk +quiet_cmd_crosstools_strip = STRIP $^ + cmd_crosstools_strip = $(STRIP) $^; touch $@ -sinclude $(obj).depend +$(obj)/.strip: $(obj)/fw_printenv + $(call cmd,crosstools_strip) -######################################################################### +always += .strip diff --git a/tools/env/README b/tools/env/README index 1020b57b05..24e31bc9f8 100644 --- a/tools/env/README +++ b/tools/env/README @@ -2,11 +2,10 @@ This is a demo implementation of a Linux command line tool to access the U-Boot's environment variables. -In the current version, there is an issue in cross-compilation. In order to cross-compile fw_printenv, run - make HOSTCC= env + make CROSS_COMPILE= env in the root directory of the U-Boot distribution. For example, - make HOSTCC=arm-linux-gcc env + make CROSS_COMPILE=arm-linux- env For the run-time utility configuration uncomment the line #define CONFIG_FILE "/etc/fw_env.config" diff --git a/tools/env/aes.c b/tools/env/aes.c new file mode 100644 index 0000000000..9e42679e34 --- /dev/null +++ b/tools/env/aes.c @@ -0,0 +1 @@ +#include "../../lib/aes.c" diff --git a/tools/env/crc32.c b/tools/env/crc32.c new file mode 100644 index 0000000000..34f8178e33 --- /dev/null +++ b/tools/env/crc32.c @@ -0,0 +1 @@ +#include "../../lib/crc32.c" diff --git a/tools/env/ctype.c b/tools/env/ctype.c new file mode 100644 index 0000000000..21050e9373 --- /dev/null +++ b/tools/env/ctype.c @@ -0,0 +1 @@ +#include "../../lib/ctype.c" diff --git a/tools/env/env_attr.c b/tools/env/env_attr.c new file mode 100644 index 0000000000..502d4c900b --- /dev/null +++ b/tools/env/env_attr.c @@ -0,0 +1 @@ +#include "../../common/env_attr.c" diff --git a/tools/env/env_flags.c b/tools/env/env_flags.c new file mode 100644 index 0000000000..b261cb8e39 --- /dev/null +++ b/tools/env/env_flags.c @@ -0,0 +1 @@ +#include "../../common/env_flags.c" diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 44607b164a..1173eea782 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -31,6 +31,10 @@ #include "fw_env.h" +#include + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + #define WHITESPACE(c) ((c == '\t') || (c == ' ')) #define min(x, y) ({ \ @@ -40,7 +44,7 @@ _min1 < _min2 ? _min1 : _min2; }) struct envdev_s { - char devname[16]; /* Device name */ + const char *devname; /* Device name */ ulong devoff; /* Device offset */ ulong env_size; /* environment size */ ulong erase_size; /* device erase size */ @@ -98,6 +102,11 @@ static struct environment environment = { .flag_scheme = FLAG_NONE, }; +/* Is AES encryption used? */ +static int aes_flag; +static uint8_t aes_key[AES_KEY_LENGTH] = { 0 }; +static int env_aes_cbc_crypt(char *data, const int enc); + static int HaveRedundEnv = 0; static unsigned char active_flag = 1; @@ -116,10 +125,14 @@ static int get_config (char *); #endif static inline ulong getenvsize (void) { - ulong rc = CUR_ENVSIZE - sizeof(long); + ulong rc = CUR_ENVSIZE - sizeof(uint32_t); if (HaveRedundEnv) rc -= sizeof (char); + + if (aes_flag) + rc &= ~(AES_KEY_LENGTH - 1); + return rc; } @@ -191,6 +204,36 @@ char *fw_getdefenv(char *name) return NULL; } +static int parse_aes_key(char *key) +{ + char tmp[5] = { '0', 'x', 0, 0, 0 }; + unsigned long ul; + int i; + + if (strnlen(key, 64) != 32) { + fprintf(stderr, + "## Error: '-a' option requires 16-byte AES key\n"); + return -1; + } + + for (i = 0; i < 16; i++) { + tmp[2] = key[0]; + tmp[3] = key[1]; + errno = 0; + ul = strtoul(tmp, NULL, 16); + if (errno) { + fprintf(stderr, + "## Error: '-a' option requires valid AES key\n"); + return -1; + } + aes_key[i] = ul & 0xff; + key += 2; + } + aes_flag = 1; + + return 0; +} + /* * Print the current definition of one, or more, or all * environment variables @@ -201,6 +244,19 @@ int fw_printenv (int argc, char *argv[]) int i, n_flag; int rc = 0; + if (argc >= 2 && strcmp(argv[1], "-a") == 0) { + if (argc < 3) { + fprintf(stderr, + "## Error: '-a' option requires AES key\n"); + return -1; + } + rc = parse_aes_key(argv[2]); + if (rc) + return rc; + argv += 2; + argc -= 2; + } + if (fw_env_open()) return -1; @@ -266,6 +322,16 @@ int fw_printenv (int argc, char *argv[]) int fw_env_close(void) { + int ret; + if (aes_flag) { + ret = env_aes_cbc_crypt(environment.data, 1); + if (ret) { + fprintf(stderr, + "Error: can't encrypt env for flash\n"); + return ret; + } + } + /* * Update CRC */ @@ -413,7 +479,7 @@ int fw_env_write(char *name, char *value) */ int fw_setenv(int argc, char *argv[]) { - int i; + int i, rc; size_t len; char *name; char *value = NULL; @@ -423,6 +489,24 @@ int fw_setenv(int argc, char *argv[]) return -1; } + if (strcmp(argv[1], "-a") == 0) { + if (argc < 3) { + fprintf(stderr, + "## Error: '-a' option requires AES key\n"); + return -1; + } + rc = parse_aes_key(argv[2]); + if (rc) + return rc; + argv += 2; + argc -= 2; + } + + if (argc < 2) { + errno = EINVAL; + return -1; + } + if (fw_env_open()) { fprintf(stderr, "Error: environment not initialized\n"); return -1; @@ -727,27 +811,39 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, MEMGETBADBLOCK needs 64 bits */ int rc; - blocklen = DEVESIZE (dev); + /* + * For mtd devices only offset and size of the environment do matter + */ + if (mtd_type == MTD_ABSENT) { + blocklen = count; + top_of_range = offset + count; + erase_len = blocklen; + blockstart = offset; + block_seek = 0; + write_total = blocklen; + } else { + blocklen = DEVESIZE(dev); - top_of_range = ((DEVOFFSET(dev) / blocklen) + - ENVSECTORS (dev)) * blocklen; + top_of_range = ((DEVOFFSET(dev) / blocklen) + + ENVSECTORS(dev)) * blocklen; - erase_offset = (offset / blocklen) * blocklen; + erase_offset = (offset / blocklen) * blocklen; - /* Maximum area we may use */ - erase_len = top_of_range - erase_offset; + /* Maximum area we may use */ + erase_len = top_of_range - erase_offset; - blockstart = erase_offset; - /* Offset inside a block */ - block_seek = offset - erase_offset; + blockstart = erase_offset; + /* Offset inside a block */ + block_seek = offset - erase_offset; - /* - * Data size we actually have to write: from the start of the block - * to the start of the data, then count bytes of data, and to the - * end of the block - */ - write_total = ((block_seek + count + blocklen - 1) / - blocklen) * blocklen; + /* + * Data size we actually write: from the start of the block + * to the start of the data, then count bytes of data, and + * to the end of the block + */ + write_total = ((block_seek + count + blocklen - 1) / + blocklen) * blocklen; + } /* * Support data anywhere within erase sectors: read out the complete @@ -818,17 +914,18 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, continue; } - erase.start = blockstart; - ioctl (fd, MEMUNLOCK, &erase); - /* These do not need an explicit erase cycle */ - if (mtd_type != MTD_ABSENT && - mtd_type != MTD_DATAFLASH) - if (ioctl (fd, MEMERASE, &erase) != 0) { - fprintf (stderr, "MTD erase error on %s: %s\n", - DEVNAME (dev), - strerror (errno)); - return -1; - } + if (mtd_type != MTD_ABSENT) { + erase.start = blockstart; + ioctl(fd, MEMUNLOCK, &erase); + /* These do not need an explicit erase cycle */ + if (mtd_type != MTD_DATAFLASH) + if (ioctl(fd, MEMERASE, &erase) != 0) { + fprintf(stderr, + "MTD erase error on %s: %s\n", + DEVNAME(dev), strerror(errno)); + return -1; + } + } if (lseek (fd, blockstart, SEEK_SET) == -1) { fprintf (stderr, @@ -847,11 +944,12 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, return -1; } - ioctl (fd, MEMLOCK, &erase); + if (mtd_type != MTD_ABSENT) + ioctl(fd, MEMLOCK, &erase); - processed += blocklen; + processed += erasesize; block_seek = 0; - blockstart += blocklen; + blockstart += erasesize; } if (write_total > count) @@ -886,6 +984,28 @@ static int flash_flag_obsolete (int dev, int fd, off_t offset) return rc; } +/* Encrypt or decrypt the environment before writing or reading it. */ +static int env_aes_cbc_crypt(char *payload, const int enc) +{ + uint8_t *data = (uint8_t *)payload; + const int len = getenvsize(); + uint8_t key_exp[AES_EXPAND_KEY_LENGTH]; + uint32_t aes_blocks; + + /* First we expand the key. */ + aes_expand_key(aes_key, key_exp); + + /* Calculate the number of AES blocks to encrypt. */ + aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH); + + if (enc) + aes_cbc_encrypt_blocks(key_exp, data, data, aes_blocks); + else + aes_cbc_decrypt_blocks(key_exp, data, data, aes_blocks); + + return 0; +} + static int flash_write (int fd_current, int fd_target, int dev_target) { int rc; @@ -909,6 +1029,7 @@ static int flash_write (int fd_current, int fd_target, int dev_target) fprintf(stderr, "Writing new environment at 0x%lx on %s\n", DEVOFFSET (dev_target), DEVNAME (dev_target)); #endif + rc = flash_write_buf(dev_target, fd_target, environment.image, CUR_ENVSIZE, DEVOFFSET(dev_target), DEVTYPE(dev_target)); @@ -967,8 +1088,10 @@ static int flash_read (int fd) rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE, DEVOFFSET (dev_current), mtdinfo.type); + if (rc != CUR_ENVSIZE) + return -1; - return (rc != CUR_ENVSIZE) ? -1 : 0; + return 0; } static int flash_io (int mode) @@ -1061,6 +1184,8 @@ int fw_env_open(void) unsigned char flag1; void *addr1; + int ret; + struct env_image_single *single; struct env_image_redundant *redundant; @@ -1095,6 +1220,13 @@ int fw_env_open(void) return -1; crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE); + + if (aes_flag) { + ret = env_aes_cbc_crypt(environment.data, 0); + if (ret) + return ret; + } + crc0_ok = (crc0 == *environment.crc); if (!HaveRedundEnv) { if (!crc0_ok) { @@ -1136,12 +1268,22 @@ int fw_env_open(void) } else if (DEVTYPE(dev_current) == MTD_UBIVOLUME && DEVTYPE(!dev_current) == MTD_UBIVOLUME) { environment.flag_scheme = FLAG_INCREMENTAL; + } else if (DEVTYPE(dev_current) == MTD_ABSENT && + DEVTYPE(!dev_current) == MTD_ABSENT) { + environment.flag_scheme = FLAG_INCREMENTAL; } else { fprintf (stderr, "Incompatible flash types!\n"); return -1; } crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE); + + if (aes_flag) { + ret = env_aes_cbc_crypt(redundant->data, 0); + if (ret) + return ret; + } + crc1_ok = (crc1 == redundant->crc); flag1 = redundant->flags; @@ -1226,12 +1368,13 @@ static int parse_config () return -1; } #else - strcpy (DEVNAME (0), DEVICE1_NAME); + DEVNAME (0) = DEVICE1_NAME; DEVOFFSET (0) = DEVICE1_OFFSET; ENVSIZE (0) = ENV1_SIZE; - /* Default values are: erase-size=env-size, #sectors=1 */ + /* Default values are: erase-size=env-size */ DEVESIZE (0) = ENVSIZE (0); - ENVSECTORS (0) = 1; + /* #sectors=env-size/erase-size (rounded up) */ + ENVSECTORS (0) = (ENVSIZE(0) + DEVESIZE(0) - 1) / DEVESIZE(0); #ifdef DEVICE1_ESIZE DEVESIZE (0) = DEVICE1_ESIZE; #endif @@ -1240,12 +1383,13 @@ static int parse_config () #endif #ifdef HAVE_REDUND - strcpy (DEVNAME (1), DEVICE2_NAME); + DEVNAME (1) = DEVICE2_NAME; DEVOFFSET (1) = DEVICE2_OFFSET; ENVSIZE (1) = ENV2_SIZE; - /* Default values are: erase-size=env-size, #sectors=1 */ + /* Default values are: erase-size=env-size */ DEVESIZE (1) = ENVSIZE (1); - ENVSECTORS (1) = 1; + /* #sectors=env-size/erase-size (rounded up) */ + ENVSECTORS (1) = (ENVSIZE(1) + DEVESIZE(1) - 1) / DEVESIZE(1); #ifdef DEVICE2_ESIZE DEVESIZE (1) = DEVICE2_ESIZE; #endif @@ -1278,6 +1422,7 @@ static int get_config (char *fname) int i = 0; int rc; char dump[128]; + char *devname; fp = fopen (fname, "r"); if (fp == NULL) @@ -1288,8 +1433,8 @@ static int get_config (char *fname) if (dump[0] == '#') continue; - rc = sscanf (dump, "%s %lx %lx %lx %lx", - DEVNAME (i), + rc = sscanf (dump, "%ms %lx %lx %lx %lx", + &devname, &DEVOFFSET (i), &ENVSIZE (i), &DEVESIZE (i), @@ -1298,13 +1443,15 @@ static int get_config (char *fname) if (rc < 3) continue; + DEVNAME(i) = devname; + if (rc < 4) /* Assume the erase size is the same as the env-size */ DEVESIZE(i) = ENVSIZE(i); if (rc < 5) - /* Default - 1 sector */ - ENVSECTORS (i) = 1; + /* Assume enough env sectors to cover the environment */ + ENVSECTORS (i) = (ENVSIZE(i) + DEVESIZE(i) - 1) / DEVESIZE(i); i++; } diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index 90e499da1e..c9b9f6a160 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -1,7 +1,7 @@ # Configuration file for fw_(printenv/setenv) utility. # Up to two entries are valid, in this case the redundant # environment sector is assumed present. -# Notice, that the "Number of sectors" is ignored on NOR and SPI-dataflash. +# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash. # Futhermore, if the Flash sector size is ommitted, this value is assumed to # be the same as the Environment size, which is valid for NOR and SPI-dataflash diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h index 6208293790..aff471ba19 100644 --- a/tools/env/fw_env.h +++ b/tools/env/fw_env.h @@ -2,7 +2,7 @@ * (C) Copyright 2002-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* Pull in the current config to define the default environment */ diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c index 5f42df3889..ce50d58b64 100644 --- a/tools/env/fw_env_main.c +++ b/tools/env/fw_env_main.c @@ -2,25 +2,29 @@ * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* * Command line user interface to firmware (=U-Boot) environment. * * Implements: - * fw_printenv [[ -n name ] | [ name ... ]] + * fw_printenv [ -a key ] [[ -n name ] | [ name ... ]] * - prints the value of a single environment variable * "name", the ``name=value'' pairs of one or more * environment variables "name", or the whole * environment if no names are specified. - * fw_setenv name [ value ... ] + * fw_setenv [ -a key ] name [ value ... ] * - If a name without any values is given, the variable * with this name is deleted from the environment; * otherwise, all "value" arguments are concatenated, * separated by single blank characters, and the * resulting string is assigned to the environment * variable "name" + * + * If '-a key' is specified, the env block is encrypted with AES 128 CBC. + * The 'key' argument is in the format of 32 hexadecimal numbers (16 bytes + * of AES key), eg. '-a aabbccddeeff00112233445566778899'. */ #include @@ -46,8 +50,8 @@ void usage(void) fprintf(stderr, "fw_printenv/fw_setenv, " "a command line interface to U-Boot environment\n\n" - "usage:\tfw_printenv [-n] [variable name]\n" - "\tfw_setenv [variable name] [variable value]\n" + "usage:\tfw_printenv [-a key] [-n] [variable name]\n" + "\tfw_setenv [-a key] [variable name] [variable value]\n" "\tfw_setenv -s [ file ]\n" "\tfw_setenv -s - < [ file ]\n\n" "The file passed as argument contains only pairs " @@ -94,9 +98,12 @@ int main(int argc, char *argv[]) cmdname = p + 1; } - while ((c = getopt_long (argc, argv, "ns:h", + while ((c = getopt_long (argc, argv, "a:ns:h", long_options, NULL)) != EOF) { switch (c) { + case 'a': + /* AES key, handled later */ + break; case 'n': /* handled in fw_printenv */ break; diff --git a/tools/env/linux_string.c b/tools/env/linux_string.c new file mode 100644 index 0000000000..6c01addadf --- /dev/null +++ b/tools/env/linux_string.c @@ -0,0 +1 @@ +#include "../../lib/linux_string.c" diff --git a/tools/fdt_host.h b/tools/fdt_host.h index c2b23c6217..134d965713 100644 --- a/tools/fdt_host.h +++ b/tools/fdt_host.h @@ -11,4 +11,6 @@ #include "../include/libfdt.h" #include "../include/fdt_support.h" +int fit_check_sign(const void *working_fdt, const void *key); + #endif /* __FDT_HOST_H__ */ diff --git a/tools/fit_check_sign.c b/tools/fit_check_sign.c new file mode 100644 index 0000000000..69e99c0d17 --- /dev/null +++ b/tools/fit_check_sign.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2014 + * DENX Software Engineering + * Heiko Schocher + * + * Based on: + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * Updated-by: Prafulla Wadaskar + * FIT image specific code abstracted from mkimage.c + * some functions added to address abstraction + * + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "mkimage.h" +#include "fit_common.h" +#include +#include + +void usage(char *cmdname) +{ + fprintf(stderr, "Usage: %s -f fit file -k key file\n" + " -f ==> set fit file which should be checked'\n" + " -k ==> set key file which contains the key'\n", + cmdname); + exit(EXIT_FAILURE); +} + +int main(int argc, char **argv) +{ + int ffd = -1; + int kfd = -1; + struct stat fsbuf; + struct stat ksbuf; + void *fit_blob; + char *fdtfile = NULL; + char *keyfile = NULL; + char cmdname[256]; + int ret; + void *key_blob; + int c; + + strncpy(cmdname, *argv, sizeof(cmdname) - 1); + cmdname[sizeof(cmdname) - 1] = '\0'; + while ((c = getopt(argc, argv, "f:k:")) != -1) + switch (c) { + case 'f': + fdtfile = optarg; + break; + case 'k': + keyfile = optarg; + break; + default: + usage(cmdname); + break; + } + + if (!fdtfile) { + fprintf(stderr, "%s: Missing fdt file\n", *argv); + usage(*argv); + } + if (!keyfile) { + fprintf(stderr, "%s: Missing key file\n", *argv); + usage(*argv); + } + + ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false); + if (ffd < 0) + return EXIT_FAILURE; + kfd = mmap_fdt(cmdname, keyfile, 0, &key_blob, &ksbuf, false); + if (ffd < 0) + return EXIT_FAILURE; + + image_set_host_blob(key_blob); + ret = fit_check_sign(fit_blob, key_blob); + if (!ret) { + ret = EXIT_SUCCESS; + fprintf(stderr, "Signature check OK\n"); + } else { + ret = EXIT_FAILURE; + fprintf(stderr, "Signature check Bad (error %d)\n", ret); + } + + (void) munmap((void *)fit_blob, fsbuf.st_size); + (void) munmap((void *)key_blob, ksbuf.st_size); + + close(ffd); + close(kfd); + exit(ret); +} diff --git a/tools/fit_common.c b/tools/fit_common.c new file mode 100644 index 0000000000..81ba698abd --- /dev/null +++ b/tools/fit_common.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2014 + * DENX Software Engineering + * Heiko Schocher + * + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * Updated-by: Prafulla Wadaskar + * FIT image specific code abstracted from mkimage.c + * some functions added to address abstraction + * + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include "mkimage.h" +#include "fit_common.h" +#include +#include + +int fit_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + return fdt_check_header(ptr); +} + +int fit_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_FLATDT) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +int mmap_fdt(const char *cmdname, const char *fname, size_t size_inc, + void **blobp, struct stat *sbuf, bool delete_on_error) +{ + void *ptr; + int fd; + + /* Load FIT blob into memory (we need to write hashes/signatures) */ + fd = open(fname, O_RDWR | O_BINARY); + + if (fd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + cmdname, fname, strerror(errno)); + goto err; + } + + if (fstat(fd, sbuf) < 0) { + fprintf(stderr, "%s: Can't stat %s: %s\n", + cmdname, fname, strerror(errno)); + goto err; + } + + if (size_inc) { + sbuf->st_size += size_inc; + if (ftruncate(fd, sbuf->st_size)) { + fprintf(stderr, "%s: Can't expand %s: %s\n", + cmdname, fname, strerror(errno)); + goto err; + } + } + + errno = 0; + ptr = mmap(0, sbuf->st_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); + if ((ptr == MAP_FAILED) || (errno != 0)) { + fprintf(stderr, "%s: Can't read %s: %s\n", + cmdname, fname, strerror(errno)); + goto err; + } + + /* check if ptr has a valid blob */ + if (fdt_check_header(ptr)) { + fprintf(stderr, "%s: Invalid FIT blob\n", cmdname); + goto err; + } + + /* expand if needed */ + if (size_inc) { + int ret; + + ret = fdt_open_into(ptr, ptr, sbuf->st_size); + if (ret) { + fprintf(stderr, "%s: Cannot expand FDT: %s\n", + cmdname, fdt_strerror(ret)); + goto err; + } + } + + *blobp = ptr; + return fd; + +err: + if (fd >= 0) + close(fd); + if (delete_on_error) + unlink(fname); + + return -1; +} diff --git a/tools/fit_common.h b/tools/fit_common.h new file mode 100644 index 0000000000..b8d8438717 --- /dev/null +++ b/tools/fit_common.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2014 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FIT_COMMON_H_ +#define _FIT_COMMON_H_ + +#include "imagetool.h" +#include "mkimage.h" +#include + +int fit_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params); + +int fit_check_image_types(uint8_t type); + +/** + * Map an FDT into memory, optionally increasing its size + * + * @cmdname: Tool name (for displaying with error messages) + * @fname: Filename containing FDT + * @size_inc: Amount to increase size by (0 = leave it alone) + * @blobp: Returns pointer to FDT blob + * @sbuf: File status information is stored here + * @delete_on_error: true to delete the file if we get an error + * @return 0 if OK, -1 on error. + */ +int mmap_fdt(const char *cmdname, const char *fname, size_t size_inc, + void **blobp, struct stat *sbuf, bool delete_on_error); + +#endif /* _FIT_COMMON_H_ */ diff --git a/tools/fit_image.c b/tools/fit_image.c index 47beaaff2a..eb2a25eeac 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -14,66 +14,60 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include "imagetool.h" +#include "fit_common.h" #include "mkimage.h" #include #include static image_header_t header; -static int fit_verify_header (unsigned char *ptr, int image_size, - struct mkimage_params *params) -{ - return fdt_check_header ((void *)ptr); -} - -static int fit_check_image_types (uint8_t type) -{ - if (type == IH_TYPE_FLATDT) - return EXIT_SUCCESS; - else - return EXIT_FAILURE; -} - -int mmap_fdt(struct mkimage_params *params, const char *fname, void **blobp, - struct stat *sbuf) +static int fit_add_file_data(struct image_tool_params *params, size_t size_inc, + const char *tmpfile) { + int tfd, destfd = 0; + void *dest_blob = NULL; + off_t destfd_size = 0; + struct stat sbuf; void *ptr; - int fd; + int ret = 0; - /* Load FIT blob into memory (we need to write hashes/signatures) */ - fd = open(fname, O_RDWR | O_BINARY); + tfd = mmap_fdt(params->cmdname, tmpfile, size_inc, &ptr, &sbuf, true); + if (tfd < 0) + return -EIO; - if (fd < 0) { - fprintf(stderr, "%s: Can't open %s: %s\n", - params->cmdname, fname, strerror(errno)); - unlink(fname); - return -1; - } + if (params->keydest) { + struct stat dest_sbuf; - if (fstat(fd, sbuf) < 0) { - fprintf(stderr, "%s: Can't stat %s: %s\n", - params->cmdname, fname, strerror(errno)); - unlink(fname); - return -1; + destfd = mmap_fdt(params->cmdname, params->keydest, size_inc, + &dest_blob, &dest_sbuf, false); + if (destfd < 0) { + ret = -EIO; + goto err_keydest; + } + destfd_size = dest_sbuf.st_size; } - ptr = mmap(0, sbuf->st_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); - if (ptr == MAP_FAILED) { - fprintf(stderr, "%s: Can't read %s: %s\n", - params->cmdname, fname, strerror(errno)); - unlink(fname); - return -1; + /* for first image creation, add a timestamp at offset 0 i.e., root */ + if (params->datafile) + ret = fit_set_timestamp(ptr, 0, sbuf.st_mtime); + + if (!ret) { + ret = fit_add_verification_data(params->keydir, dest_blob, ptr, + params->comment, + params->require_keys); } - /* check if ptr has a valid blob */ - if (fdt_check_header(ptr)) { - fprintf(stderr, "%s: Invalid FIT blob\n", params->cmdname); - unlink(fname); - return -1; + if (dest_blob) { + munmap(dest_blob, destfd_size); + close(destfd); } - *blobp = ptr; - return fd; +err_keydest: + munmap(ptr, sbuf.st_size); + close(tfd); + + return ret; } /** @@ -88,15 +82,12 @@ int mmap_fdt(struct mkimage_params *params, const char *fname, void **blobp, * returns: * only on success, otherwise calls exit (EXIT_FAILURE); */ -static int fit_handle_file (struct mkimage_params *params) +static int fit_handle_file(struct image_tool_params *params) { char tmpfile[MKIMAGE_MAX_TMPFILE_LEN]; char cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN]; - int tfd, destfd = 0; - void *dest_blob = NULL; - struct stat sbuf; - void *ptr; - off_t destfd_size = 0; + size_t size_inc; + int ret; /* Flattened Image Tree (FIT) format handling */ debug ("FIT format handling\n"); @@ -127,39 +118,26 @@ static int fit_handle_file (struct mkimage_params *params) goto err_system; } - if (params->keydest) { - destfd = mmap_fdt(params, params->keydest, &dest_blob, &sbuf); - if (destfd < 0) - goto err_keydest; - destfd_size = sbuf.st_size; + /* + * Set hashes for images in the blob. Unfortunately we may need more + * space in either FDT, so keep trying until we succeed. + * + * Note: this is pretty inefficient for signing, since we must + * calculate the signature every time. It would be better to calculate + * all the data and then store it in a separate step. However, this + * would be considerably more complex to implement. Generally a few + * steps of this loop is enough to sign with several keys. + */ + for (size_inc = 0; size_inc < 64 * 1024; size_inc += 1024) { + ret = fit_add_file_data(params, size_inc, tmpfile); + if (!ret || ret != -ENOSPC) + break; } - tfd = mmap_fdt(params, tmpfile, &ptr, &sbuf); - if (tfd < 0) - goto err_mmap; - - /* set hashes for images in the blob */ - if (fit_add_verification_data(params->keydir, - dest_blob, ptr, params->comment, - params->require_keys)) { + if (ret) { fprintf(stderr, "%s Can't add hashes to FIT blob\n", params->cmdname); - goto err_add_hashes; - } - - /* for first image creation, add a timestamp at offset 0 i.e., root */ - if (params->datafile && fit_set_timestamp(ptr, 0, sbuf.st_mtime)) { - fprintf (stderr, "%s: Can't add image timestamp\n", - params->cmdname); - goto err_add_timestamp; - } - debug ("Added timestamp successfully\n"); - - munmap ((void *)ptr, sbuf.st_size); - close (tfd); - if (dest_blob) { - munmap(dest_blob, destfd_size); - close(destfd); + goto err_system; } if (rename (tmpfile, params->imagefile) == -1) { @@ -168,42 +146,124 @@ static int fit_handle_file (struct mkimage_params *params) strerror (errno)); unlink (tmpfile); unlink (params->imagefile); - return (EXIT_FAILURE); + return EXIT_FAILURE; } - return (EXIT_SUCCESS); + return EXIT_SUCCESS; -err_add_timestamp: -err_add_hashes: - munmap(ptr, sbuf.st_size); -err_mmap: - if (dest_blob) - munmap(dest_blob, destfd_size); -err_keydest: err_system: unlink(tmpfile); return -1; } -static int fit_check_params (struct mkimage_params *params) +/** + * fit_image_extract - extract a FIT component image + * @fit: pointer to the FIT format image header + * @image_noffset: offset of the component image node + * @file_name: name of the file to store the FIT sub-image + * + * returns: + * zero in case of success or a negative value if fail. + */ +static int fit_image_extract( + const void *fit, + int image_noffset, + const char *file_name) +{ + const void *file_data; + size_t file_size = 0; + + /* get the "data" property of component at offset "image_noffset" */ + fit_image_get_data(fit, image_noffset, &file_data, &file_size); + + /* save the "file_data" into the file specified by "file_name" */ + return imagetool_save_subimage(file_name, (ulong) file_data, file_size); +} + +/** + * fit_extract_contents - retrieve a sub-image component from the FIT image + * @ptr: pointer to the FIT format image header + * @params: command line parameters + * + * returns: + * zero in case of success or a negative value if fail. + */ +static int fit_extract_contents(void *ptr, struct image_tool_params *params) +{ + int images_noffset; + int noffset; + int ndepth; + const void *fit = ptr; + int count = 0; + const char *p; + + /* Indent string is defined in header image.h */ + p = IMAGE_INDENT_STRING; + + if (!fit_check_format(fit)) { + printf("Bad FIT image format\n"); + return -1; + } + + /* Find images parent node offset */ + images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); + if (images_noffset < 0) { + printf("Can't find images parent node '%s' (%s)\n", + FIT_IMAGES_PATH, fdt_strerror(images_noffset)); + return -1; + } + + /* Avoid any overrun */ + count = fit_get_subimage_count(fit, images_noffset); + if ((params->pflag < 0) || (count <= params->pflag)) { + printf("No such component at '%d'\n", params->pflag); + return -1; + } + + /* Process its subnodes, extract the desired component from image */ + for (ndepth = 0, count = 0, + noffset = fdt_next_node(fit, images_noffset, &ndepth); + (noffset >= 0) && (ndepth > 0); + noffset = fdt_next_node(fit, noffset, &ndepth)) { + if (ndepth == 1) { + /* + * Direct child node of the images parent node, + * i.e. component image node. + */ + if (params->pflag == count) { + printf("Extracted:\n%s Image %u (%s)\n", p, + count, fit_get_name(fit, noffset, NULL)); + + fit_image_print(fit, noffset, p); + + return fit_image_extract(fit, noffset, + params->outfile); + } + + count++; + } + } + + return 0; +} + +static int fit_check_params(struct image_tool_params *params) { return ((params->dflag && (params->fflag || params->lflag)) || (params->fflag && (params->dflag || params->lflag)) || (params->lflag && (params->dflag || params->fflag))); } -static struct image_type_params fitimage_params = { - .name = "FIT Image support", - .header_size = sizeof(image_header_t), - .hdr = (void*)&header, - .verify_header = fit_verify_header, - .print_header = fit_print_contents, - .check_image_type = fit_check_image_types, - .fflag_handle = fit_handle_file, - .set_header = NULL, /* FIT images use DTB header */ - .check_params = fit_check_params, -}; - -void init_fit_image_type (void) -{ - mkimage_register (&fitimage_params); -} +U_BOOT_IMAGE_TYPE( + fitimage, + "FIT Image support", + sizeof(image_header_t), + (void *)&header, + fit_check_params, + fit_verify_header, + fit_print_contents, + NULL, + fit_extract_contents, + fit_check_image_types, + fit_handle_file, + NULL /* FIT images use DTB header */ +); diff --git a/tools/fit_info.c b/tools/fit_info.c new file mode 100644 index 0000000000..652abcd2bd --- /dev/null +++ b/tools/fit_info.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2014 + * DENX Software Engineering + * Heiko Schocher + * + * fit_info: print the offset and the len of a property from + * node in a fit file. + * + * Based on: + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * Updated-by: Prafulla Wadaskar + * FIT image specific code abstracted from mkimage.c + * some functions added to address abstraction + * + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "mkimage.h" +#include "fit_common.h" +#include +#include + +void usage(char *cmdname) +{ + fprintf(stderr, "Usage: %s -f fit file -n node -p property\n" + " -f ==> set fit file which is used'\n" + " -n ==> set node name'\n" + " -p ==> set property name'\n", + cmdname); + exit(EXIT_FAILURE); +} + +int main(int argc, char **argv) +{ + int ffd = -1; + struct stat fsbuf; + void *fit_blob; + int len; + int nodeoffset; /* node offset from libfdt */ + const void *nodep; /* property node pointer */ + char *fdtfile = NULL; + char *nodename = NULL; + char *propertyname = NULL; + char cmdname[256]; + int c; + + strncpy(cmdname, *argv, sizeof(cmdname) - 1); + cmdname[sizeof(cmdname) - 1] = '\0'; + while ((c = getopt(argc, argv, "f:n:p:")) != -1) + switch (c) { + case 'f': + fdtfile = optarg; + break; + case 'n': + nodename = optarg; + break; + case 'p': + propertyname = optarg; + break; + default: + usage(cmdname); + break; + } + + if (!fdtfile) { + fprintf(stderr, "%s: Missing fdt file\n", *argv); + usage(*argv); + } + if (!nodename) { + fprintf(stderr, "%s: Missing node name\n", *argv); + usage(*argv); + } + if (!propertyname) { + fprintf(stderr, "%s: Missing property name\n", *argv); + usage(*argv); + } + ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false); + + if (ffd < 0) { + printf("Could not open %s\n", fdtfile); + exit(EXIT_FAILURE); + } + + nodeoffset = fdt_path_offset(fit_blob, nodename); + if (nodeoffset < 0) { + printf("%s not found.", nodename); + exit(EXIT_FAILURE); + } + nodep = fdt_getprop(fit_blob, nodeoffset, propertyname, &len); + if (len == 0) { + printf("len == 0 %s\n", propertyname); + exit(EXIT_FAILURE); + } + + printf("NAME: %s\n", fit_get_name(fit_blob, nodeoffset, NULL)); + printf("LEN: %d\n", len); + printf("OFF: %d\n", (int)(nodep - fit_blob)); + (void) munmap((void *)fit_blob, fsbuf.st_size); + + close(ffd); + exit(EXIT_SUCCESS); +} diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile index dee91fccc0..451332031e 100644 --- a/tools/gdb/Makefile +++ b/tools/gdb/Makefile @@ -8,51 +8,39 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(TOPDIR)/config.mk - -BINS = gdbsend gdbcont - -COBJS = gdbsend.o gdbcont.o error.o remote.o serial.o - -HOSTOBJS := $(addprefix $(obj),$(COBJS)) -HOSTSRCS := $(COBJS:.o=.c) -BINS := $(addprefix $(obj),$(BINS)) +ifneq ($(HOSTOS),cygwin) + +# Location of a usable BFD library, where we define "usable" as +# "built for ${HOST}, supports ${TARGET}". Sensible values are +# - When cross-compiling: the root of the cross-environment +# - Linux/ppc (native): /usr +# - NetBSD/ppc (native): you lose ... (must extract these from the +# binutils build directory, plus the native and U-Boot include +# files don't like each other) + +ifeq ($(HOSTOS),darwin) +BFD_ROOT_DIR = /usr/local/tools +else +ifeq ($(HOSTARCH),$(ARCH)) +# native +BFD_ROOT_DIR = /usr +else +#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 +#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 +BFD_ROOT_DIR = /opt/powerpc +endif +endif # # Use native tools and options # -HOSTCPPFLAGS = -I$(BFD_ROOT_DIR)/include - -HOSTOS := $(shell uname -s | sed -e 's/\([Cc][Yy][Gg][Ww][Ii][Nn]\).*/cygwin/') - -ifeq ($(HOSTOS),cygwin) - -all: -$(obj).depend: - -else # ! CYGWIN - -all: $(obj).depend $(BINS) - -$(obj)gdbsend: $(obj)gdbsend.o $(obj)error.o $(obj)remote.o $(obj)serial.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - -$(obj)gdbcont: $(obj)gdbcont.o $(obj)error.o $(obj)remote.o $(obj)serial.o - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - -clean: - rm -f $(HOSTOBJS) - -distclean: clean - rm -f $(BINS) $(obj)core $(obj)*.bak $(obj).depend - -######################################################################### +HOST_EXTRACFLAGS := -I$(BFD_ROOT_DIR)/include -pedantic -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +hostprogs-y := gdbsend gdbcont -sinclude $(obj).depend +gdbsend-objs := gdbsend.o error.o remote.o serial.o +gdbcont-objs := gdbcont.o error.o remote.o serial.o -######################################################################### +always := $(hostprogs-y) endif # cygwin diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py new file mode 100755 index 0000000000..23c956bb8e --- /dev/null +++ b/tools/genboardscfg.py @@ -0,0 +1,444 @@ +#!/usr/bin/env python2 +# +# Author: Masahiro Yamada +# +# SPDX-License-Identifier: GPL-2.0+ +# + +""" +Converter from Kconfig and MAINTAINERS to a board database. + +Run 'tools/genboardscfg.py' to create a board database. + +Run 'tools/genboardscfg.py -h' for available options. + +Python 2.6 or later, but not Python 3.x is necessary to run this script. +""" + +import errno +import fnmatch +import glob +import multiprocessing +import optparse +import os +import subprocess +import sys +import tempfile +import time + +sys.path.append(os.path.join(os.path.dirname(__file__), 'buildman')) +import kconfiglib + +### constant variables ### +OUTPUT_FILE = 'boards.cfg' +CONFIG_DIR = 'configs' +SLEEP_TIME = 0.03 +COMMENT_BLOCK = '''# +# List of boards +# Automatically generated by %s: don't edit +# +# Status, Arch, CPU, SoC, Vendor, Board, Target, Options, Maintainers + +''' % __file__ + +### helper functions ### +def try_remove(f): + """Remove a file ignoring 'No such file or directory' error.""" + try: + os.remove(f) + except OSError as exception: + # Ignore 'No such file or directory' error + if exception.errno != errno.ENOENT: + raise + +def check_top_directory(): + """Exit if we are not at the top of source directory.""" + for f in ('README', 'Licenses'): + if not os.path.exists(f): + sys.exit('Please run at the top of source directory.') + +def output_is_new(output): + """Check if the output file is up to date. + + Returns: + True if the given output file exists and is newer than any of + *_defconfig, MAINTAINERS and Kconfig*. False otherwise. + """ + try: + ctime = os.path.getctime(output) + except OSError as exception: + if exception.errno == errno.ENOENT: + # return False on 'No such file or directory' error + return False + else: + raise + + for (dirpath, dirnames, filenames) in os.walk(CONFIG_DIR): + for filename in fnmatch.filter(filenames, '*_defconfig'): + if fnmatch.fnmatch(filename, '.*'): + continue + filepath = os.path.join(dirpath, filename) + if ctime < os.path.getctime(filepath): + return False + + for (dirpath, dirnames, filenames) in os.walk('.'): + for filename in filenames: + if (fnmatch.fnmatch(filename, '*~') or + not fnmatch.fnmatch(filename, 'Kconfig*') and + not filename == 'MAINTAINERS'): + continue + filepath = os.path.join(dirpath, filename) + if ctime < os.path.getctime(filepath): + return False + + # Detect a board that has been removed since the current board database + # was generated + with open(output) as f: + for line in f: + if line[0] == '#' or line == '\n': + continue + defconfig = line.split()[6] + '_defconfig' + if not os.path.exists(os.path.join(CONFIG_DIR, defconfig)): + return False + + return True + +### classes ### +class KconfigScanner: + + """Kconfig scanner.""" + + ### constant variable only used in this class ### + _SYMBOL_TABLE = { + 'arch' : 'SYS_ARCH', + 'cpu' : 'SYS_CPU', + 'soc' : 'SYS_SOC', + 'vendor' : 'SYS_VENDOR', + 'board' : 'SYS_BOARD', + 'config' : 'SYS_CONFIG_NAME', + 'options' : 'SYS_EXTRA_OPTIONS' + } + + def __init__(self): + """Scan all the Kconfig files and create a Config object.""" + # Define environment variables referenced from Kconfig + os.environ['srctree'] = os.getcwd() + os.environ['UBOOTVERSION'] = 'dummy' + os.environ['KCONFIG_OBJDIR'] = '' + self._conf = kconfiglib.Config() + + def __del__(self): + """Delete a leftover temporary file before exit. + + The scan() method of this class creates a temporay file and deletes + it on success. If scan() method throws an exception on the way, + the temporary file might be left over. In that case, it should be + deleted in this destructor. + """ + if hasattr(self, '_tmpfile') and self._tmpfile: + try_remove(self._tmpfile) + + def scan(self, defconfig): + """Load a defconfig file to obtain board parameters. + + Arguments: + defconfig: path to the defconfig file to be processed + + Returns: + A dictionary of board parameters. It has a form of: + { + 'arch': , + 'cpu': , + 'soc': , + 'vendor': , + 'board': , + 'target': , + 'config': , + 'options': + } + """ + # strip special prefixes and save it in a temporary file + fd, self._tmpfile = tempfile.mkstemp() + with os.fdopen(fd, 'w') as f: + for line in open(defconfig): + colon = line.find(':CONFIG_') + if colon == -1: + f.write(line) + else: + f.write(line[colon + 1:]) + + self._conf.load_config(self._tmpfile) + + try_remove(self._tmpfile) + self._tmpfile = None + + params = {} + + # Get the value of CONFIG_SYS_ARCH, CONFIG_SYS_CPU, ... etc. + # Set '-' if the value is empty. + for key, symbol in self._SYMBOL_TABLE.items(): + value = self._conf.get_symbol(symbol).get_value() + if value: + params[key] = value + else: + params[key] = '-' + + defconfig = os.path.basename(defconfig) + params['target'], match, rear = defconfig.partition('_defconfig') + assert match and not rear, '%s : invalid defconfig' % defconfig + + # fix-up for aarch64 + if params['arch'] == 'arm' and params['cpu'] == 'armv8': + params['arch'] = 'aarch64' + + # fix-up options field. It should have the form: + # [:comma separated config options] + if params['options'] != '-': + params['options'] = params['config'] + ':' + \ + params['options'].replace(r'\"', '"') + elif params['config'] != params['target']: + params['options'] = params['config'] + + return params + +def scan_defconfigs_for_multiprocess(queue, defconfigs): + """Scan defconfig files and queue their board parameters + + This function is intended to be passed to + multiprocessing.Process() constructor. + + Arguments: + queue: An instance of multiprocessing.Queue(). + The resulting board parameters are written into it. + defconfigs: A sequence of defconfig files to be scanned. + """ + kconf_scanner = KconfigScanner() + for defconfig in defconfigs: + queue.put(kconf_scanner.scan(defconfig)) + +def read_queues(queues, params_list): + """Read the queues and append the data to the paramers list""" + for q in queues: + while not q.empty(): + params_list.append(q.get()) + +def scan_defconfigs(jobs=1): + """Collect board parameters for all defconfig files. + + This function invokes multiple processes for faster processing. + + Arguments: + jobs: The number of jobs to run simultaneously + """ + all_defconfigs = [] + for (dirpath, dirnames, filenames) in os.walk(CONFIG_DIR): + for filename in fnmatch.filter(filenames, '*_defconfig'): + if fnmatch.fnmatch(filename, '.*'): + continue + all_defconfigs.append(os.path.join(dirpath, filename)) + + total_boards = len(all_defconfigs) + processes = [] + queues = [] + for i in range(jobs): + defconfigs = all_defconfigs[total_boards * i / jobs : + total_boards * (i + 1) / jobs] + q = multiprocessing.Queue(maxsize=-1) + p = multiprocessing.Process(target=scan_defconfigs_for_multiprocess, + args=(q, defconfigs)) + p.start() + processes.append(p) + queues.append(q) + + # The resulting data should be accumulated to this list + params_list = [] + + # Data in the queues should be retrieved preriodically. + # Otherwise, the queues would become full and subprocesses would get stuck. + while any([p.is_alive() for p in processes]): + read_queues(queues, params_list) + # sleep for a while until the queues are filled + time.sleep(SLEEP_TIME) + + # Joining subprocesses just in case + # (All subprocesses should already have been finished) + for p in processes: + p.join() + + # retrieve leftover data + read_queues(queues, params_list) + + return params_list + +class MaintainersDatabase: + + """The database of board status and maintainers.""" + + def __init__(self): + """Create an empty database.""" + self.database = {} + + def get_status(self, target): + """Return the status of the given board. + + The board status is generally either 'Active' or 'Orphan'. + Display a warning message and return '-' if status information + is not found. + + Returns: + 'Active', 'Orphan' or '-'. + """ + if not target in self.database: + print >> sys.stderr, "WARNING: no status info for '%s'" % target + return '-' + + tmp = self.database[target][0] + if tmp.startswith('Maintained'): + return 'Active' + elif tmp.startswith('Orphan'): + return 'Orphan' + else: + print >> sys.stderr, ("WARNING: %s: unknown status for '%s'" % + (tmp, target)) + return '-' + + def get_maintainers(self, target): + """Return the maintainers of the given board. + + Returns: + Maintainers of the board. If the board has two or more maintainers, + they are separated with colons. + """ + if not target in self.database: + print >> sys.stderr, "WARNING: no maintainers for '%s'" % target + return '' + + return ':'.join(self.database[target][1]) + + def parse_file(self, file): + """Parse a MAINTAINERS file. + + Parse a MAINTAINERS file and accumulates board status and + maintainers information. + + Arguments: + file: MAINTAINERS file to be parsed + """ + targets = [] + maintainers = [] + status = '-' + for line in open(file): + # Check also commented maintainers + if line[:3] == '#M:': + line = line[1:] + tag, rest = line[:2], line[2:].strip() + if tag == 'M:': + maintainers.append(rest) + elif tag == 'F:': + # expand wildcard and filter by 'configs/*_defconfig' + for f in glob.glob(rest): + front, match, rear = f.partition('configs/') + if not front and match: + front, match, rear = rear.rpartition('_defconfig') + if match and not rear: + targets.append(front) + elif tag == 'S:': + status = rest + elif line == '\n': + for target in targets: + self.database[target] = (status, maintainers) + targets = [] + maintainers = [] + status = '-' + if targets: + for target in targets: + self.database[target] = (status, maintainers) + +def insert_maintainers_info(params_list): + """Add Status and Maintainers information to the board parameters list. + + Arguments: + params_list: A list of the board parameters + """ + database = MaintainersDatabase() + for (dirpath, dirnames, filenames) in os.walk('.'): + if 'MAINTAINERS' in filenames: + database.parse_file(os.path.join(dirpath, 'MAINTAINERS')) + + for i, params in enumerate(params_list): + target = params['target'] + params['status'] = database.get_status(target) + params['maintainers'] = database.get_maintainers(target) + params_list[i] = params + +def format_and_output(params_list, output): + """Write board parameters into a file. + + Columnate the board parameters, sort lines alphabetically, + and then write them to a file. + + Arguments: + params_list: The list of board parameters + output: The path to the output file + """ + FIELDS = ('status', 'arch', 'cpu', 'soc', 'vendor', 'board', 'target', + 'options', 'maintainers') + + # First, decide the width of each column + max_length = dict([ (f, 0) for f in FIELDS]) + for params in params_list: + for f in FIELDS: + max_length[f] = max(max_length[f], len(params[f])) + + output_lines = [] + for params in params_list: + line = '' + for f in FIELDS: + # insert two spaces between fields like column -t would + line += ' ' + params[f].ljust(max_length[f]) + output_lines.append(line.strip()) + + # ignore case when sorting + output_lines.sort(key=str.lower) + + with open(output, 'w') as f: + f.write(COMMENT_BLOCK + '\n'.join(output_lines) + '\n') + +def gen_boards_cfg(output, jobs=1, force=False): + """Generate a board database file. + + Arguments: + output: The name of the output file + jobs: The number of jobs to run simultaneously + force: Force to generate the output even if it is new + """ + check_top_directory() + + if not force and output_is_new(output): + print "%s is up to date. Nothing to do." % output + sys.exit(0) + + params_list = scan_defconfigs(jobs) + insert_maintainers_info(params_list) + format_and_output(params_list, output) + +def main(): + try: + cpu_count = multiprocessing.cpu_count() + except NotImplementedError: + cpu_count = 1 + + parser = optparse.OptionParser() + # Add options here + parser.add_option('-f', '--force', action="store_true", default=False, + help='regenerate the output even if it is new') + parser.add_option('-j', '--jobs', type='int', default=cpu_count, + help='the number of jobs to run simultaneously') + parser.add_option('-o', '--output', default=OUTPUT_FILE, + help='output file [default=%s]' % OUTPUT_FILE) + (options, args) = parser.parse_args() + + gen_boards_cfg(options.output, jobs=options.jobs, force=options.force) + +if __name__ == '__main__': + main() diff --git a/tools/gpheader.h b/tools/gpheader.h new file mode 100644 index 0000000000..63a28a264d --- /dev/null +++ b/tools/gpheader.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated + * Refactored common functions in to gpimage-common.c. Include this common + * header file + * + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GPIMAGE_H_ +#define _GPIMAGE_H_ + +/* common headers for gpimage and omapimage formats */ +struct gp_header { + uint32_t size; + uint32_t load_addr; +}; +#define GPIMAGE_HDR_SIZE (sizeof(struct gp_header)) + +/* common functions across gpimage and omapimage handlers */ +int valid_gph_size(uint32_t size); +int valid_gph_load_addr(uint32_t load_addr); +int gph_verify_header(struct gp_header *gph, int be); +void gph_print_header(const struct gp_header *gph, int be); +void gph_set_header(struct gp_header *gph, uint32_t size, uint32_t load_addr, + int be); +int gpimage_check_params(struct image_tool_params *params); +#endif diff --git a/tools/gpimage-common.c b/tools/gpimage-common.c new file mode 100644 index 0000000000..5ad52be437 --- /dev/null +++ b/tools/gpimage-common.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated + * Refactored common functions in to gpimage-common.c. + * + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include +#include +#include "gpheader.h" + +/* Helper to convert size and load_addr to big endian */ +void to_be32(uint32_t *gph_size, uint32_t *gph_load_addr) +{ + *gph_size = cpu_to_be32(*gph_size); + *gph_load_addr = cpu_to_be32(*gph_load_addr); +} + +int gph_verify_header(struct gp_header *gph, int be) +{ + uint32_t gph_size = gph->size; + uint32_t gph_load_addr = gph->load_addr; + + if (be) + to_be32(&gph_size, &gph_load_addr); + + if (!gph_size || !gph_load_addr) + return -1; + + return 0; +} + +void gph_print_header(const struct gp_header *gph, int be) +{ + uint32_t gph_size = gph->size, gph_load_addr = gph->load_addr; + + if (be) + to_be32(&gph_size, &gph_load_addr); + + if (!gph_size) { + fprintf(stderr, "Error: invalid image size %x\n", gph_size); + exit(EXIT_FAILURE); + } + + if (!gph_load_addr) { + fprintf(stderr, "Error: invalid image load address %x\n", + gph_load_addr); + exit(EXIT_FAILURE); + } + printf("GP Header: Size %x LoadAddr %x\n", gph_size, gph_load_addr); +} + +void gph_set_header(struct gp_header *gph, uint32_t size, uint32_t load_addr, + int be) +{ + gph->size = size; + gph->load_addr = load_addr; + if (be) + to_be32(&gph->size, &gph->load_addr); +} + +int gpimage_check_params(struct image_tool_params *params) +{ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} diff --git a/tools/gpimage.c b/tools/gpimage.c new file mode 100644 index 0000000000..1adc55c5fc --- /dev/null +++ b/tools/gpimage.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated + * Add gpimage format for keystone devices to format spl image. This is + * Based on omapimage.c + * + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include +#include +#include "gpheader.h" + +static uint8_t gpimage_header[GPIMAGE_HDR_SIZE]; + +/* to be in keystone gpimage */ +static int gpimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_GPIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static int gpimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct gp_header *gph = (struct gp_header *)ptr; + + return gph_verify_header(gph, 1); +} + +static void gpimage_print_header(const void *ptr) +{ + const struct gp_header *gph = (struct gp_header *)ptr; + + gph_print_header(gph, 1); +} + +static void gpimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct gp_header *gph = (struct gp_header *)ptr; + + gph_set_header(gph, sbuf->st_size - GPIMAGE_HDR_SIZE, params->addr, 1); +} + +/* + * gpimage parameters + */ +U_BOOT_IMAGE_TYPE( + gpimage, + "TI KeyStone GP Image support", + GPIMAGE_HDR_SIZE, + (void *)&gpimage_header, + gpimage_check_params, + gpimage_verify_header, + gpimage_print_header, + gpimage_set_header, + NULL, + gpimage_check_image_types, + NULL, + NULL +); diff --git a/tools/ifdtool.c b/tools/ifdtool.c new file mode 100644 index 0000000000..590ccc914b --- /dev/null +++ b/tools/ifdtool.c @@ -0,0 +1,1169 @@ +/* + * ifdtool - Manage Intel Firmware Descriptor information + * + * Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + * + * From Coreboot project, but it got a serious code clean-up + * and a few new features + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ifdtool.h" + +#undef DEBUG + +#ifdef DEBUG +#define debug(fmt, args...) printf(fmt, ##args) +#else +#define debug(fmt, args...) +#endif + +#define FD_SIGNATURE 0x0FF0A55A +#define FLREG_BASE(reg) ((reg & 0x00000fff) << 12); +#define FLREG_LIMIT(reg) (((reg & 0x0fff0000) >> 4) | 0xfff); + +enum input_file_type_t { + IF_normal, + IF_fdt, + IF_uboot, +}; + +struct input_file { + char *fname; + unsigned int addr; + enum input_file_type_t type; +}; + +/** + * find_fd() - Find the flash description in the ROM image + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return pointer to structure, or NULL if not found + */ +static struct fdbar_t *find_fd(char *image, int size) +{ + uint32_t *ptr, *end; + + /* Scan for FD signature */ + for (ptr = (uint32_t *)image, end = ptr + size / 4; ptr < end; ptr++) { + if (*ptr == FD_SIGNATURE) + break; + } + + if (ptr == end) { + printf("No Flash Descriptor found in this image\n"); + return NULL; + } + + debug("Found Flash Descriptor signature at 0x%08lx\n", + (char *)ptr - image); + + return (struct fdbar_t *)ptr; +} + +/** + * get_region() - Get information about the selected region + * + * @frba: Flash region list + * @region_type: Type of region (0..MAX_REGIONS-1) + * @region: Region information is written here + * @return 0 if OK, else -ve + */ +static int get_region(struct frba_t *frba, int region_type, + struct region_t *region) +{ + if (region_type >= MAX_REGIONS) { + fprintf(stderr, "Invalid region type.\n"); + return -1; + } + + region->base = FLREG_BASE(frba->flreg[region_type]); + region->limit = FLREG_LIMIT(frba->flreg[region_type]); + region->size = region->limit - region->base + 1; + + return 0; +} + +static const char *region_name(int region_type) +{ + static const char *const regions[] = { + "Flash Descriptor", + "BIOS", + "Intel ME", + "GbE", + "Platform Data" + }; + + assert(region_type < MAX_REGIONS); + + return regions[region_type]; +} + +static const char *region_filename(int region_type) +{ + static const char *const region_filenames[] = { + "flashregion_0_flashdescriptor.bin", + "flashregion_1_bios.bin", + "flashregion_2_intel_me.bin", + "flashregion_3_gbe.bin", + "flashregion_4_platform_data.bin" + }; + + assert(region_type < MAX_REGIONS); + + return region_filenames[region_type]; +} + +static int dump_region(int num, struct frba_t *frba) +{ + struct region_t region; + int ret; + + ret = get_region(frba, num, ®ion); + if (ret) + return ret; + + printf(" Flash Region %d (%s): %08x - %08x %s\n", + num, region_name(num), region.base, region.limit, + region.size < 1 ? "(unused)" : ""); + + return ret; +} + +static void dump_frba(struct frba_t *frba) +{ + int i; + + printf("Found Region Section\n"); + for (i = 0; i < MAX_REGIONS; i++) { + printf("FLREG%d: 0x%08x\n", i, frba->flreg[i]); + dump_region(i, frba); + } +} + +static void decode_spi_frequency(unsigned int freq) +{ + switch (freq) { + case SPI_FREQUENCY_20MHZ: + printf("20MHz"); + break; + case SPI_FREQUENCY_33MHZ: + printf("33MHz"); + break; + case SPI_FREQUENCY_50MHZ: + printf("50MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void decode_component_density(unsigned int density) +{ + switch (density) { + case COMPONENT_DENSITY_512KB: + printf("512KiB"); + break; + case COMPONENT_DENSITY_1MB: + printf("1MiB"); + break; + case COMPONENT_DENSITY_2MB: + printf("2MiB"); + break; + case COMPONENT_DENSITY_4MB: + printf("4MiB"); + break; + case COMPONENT_DENSITY_8MB: + printf("8MiB"); + break; + case COMPONENT_DENSITY_16MB: + printf("16MiB"); + break; + default: + printf("unknown<%x>MiB", density); + } +} + +static void dump_fcba(struct fcba_t *fcba) +{ + printf("\nFound Component Section\n"); + printf("FLCOMP 0x%08x\n", fcba->flcomp); + printf(" Dual Output Fast Read Support: %ssupported\n", + (fcba->flcomp & (1 << 30)) ? "" : "not "); + printf(" Read ID/Read Status Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 27) & 7); + printf("\n Write/Erase Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 24) & 7); + printf("\n Fast Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 21) & 7); + printf("\n Fast Read Support: %ssupported", + (fcba->flcomp & (1 << 20)) ? "" : "not "); + printf("\n Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 17) & 7); + printf("\n Component 2 Density: "); + decode_component_density((fcba->flcomp >> 3) & 7); + printf("\n Component 1 Density: "); + decode_component_density(fcba->flcomp & 7); + printf("\n"); + printf("FLILL 0x%08x\n", fcba->flill); + printf(" Invalid Instruction 3: 0x%02x\n", + (fcba->flill >> 24) & 0xff); + printf(" Invalid Instruction 2: 0x%02x\n", + (fcba->flill >> 16) & 0xff); + printf(" Invalid Instruction 1: 0x%02x\n", + (fcba->flill >> 8) & 0xff); + printf(" Invalid Instruction 0: 0x%02x\n", + fcba->flill & 0xff); + printf("FLPB 0x%08x\n", fcba->flpb); + printf(" Flash Partition Boundary Address: 0x%06x\n\n", + (fcba->flpb & 0xfff) << 12); +} + +static void dump_fpsba(struct fpsba_t *fpsba) +{ + int i; + + printf("Found PCH Strap Section\n"); + for (i = 0; i < MAX_STRAPS; i++) + printf("PCHSTRP%-2d: 0x%08x\n", i, fpsba->pchstrp[i]); +} + +static const char *get_enabled(int flag) +{ + return flag ? "enabled" : "disabled"; +} + +static void decode_flmstr(uint32_t flmstr) +{ + printf(" Platform Data Region Write Access: %s\n", + get_enabled(flmstr & (1 << 28))); + printf(" GbE Region Write Access: %s\n", + get_enabled(flmstr & (1 << 27))); + printf(" Intel ME Region Write Access: %s\n", + get_enabled(flmstr & (1 << 26))); + printf(" Host CPU/BIOS Region Write Access: %s\n", + get_enabled(flmstr & (1 << 25))); + printf(" Flash Descriptor Write Access: %s\n", + get_enabled(flmstr & (1 << 24))); + + printf(" Platform Data Region Read Access: %s\n", + get_enabled(flmstr & (1 << 20))); + printf(" GbE Region Read Access: %s\n", + get_enabled(flmstr & (1 << 19))); + printf(" Intel ME Region Read Access: %s\n", + get_enabled(flmstr & (1 << 18))); + printf(" Host CPU/BIOS Region Read Access: %s\n", + get_enabled(flmstr & (1 << 17))); + printf(" Flash Descriptor Read Access: %s\n", + get_enabled(flmstr & (1 << 16))); + + printf(" Requester ID: 0x%04x\n\n", + flmstr & 0xffff); +} + +static void dump_fmba(struct fmba_t *fmba) +{ + printf("Found Master Section\n"); + printf("FLMSTR1: 0x%08x (Host CPU/BIOS)\n", fmba->flmstr1); + decode_flmstr(fmba->flmstr1); + printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2); + decode_flmstr(fmba->flmstr2); + printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3); + decode_flmstr(fmba->flmstr3); +} + +static void dump_fmsba(struct fmsba_t *fmsba) +{ + int i; + + printf("Found Processor Strap Section\n"); + for (i = 0; i < 4; i++) + printf("????: 0x%08x\n", fmsba->data[0]); +} + +static void dump_jid(uint32_t jid) +{ + printf(" SPI Component Device ID 1: 0x%02x\n", + (jid >> 16) & 0xff); + printf(" SPI Component Device ID 0: 0x%02x\n", + (jid >> 8) & 0xff); + printf(" SPI Component Vendor ID: 0x%02x\n", + jid & 0xff); +} + +static void dump_vscc(uint32_t vscc) +{ + printf(" Lower Erase Opcode: 0x%02x\n", + vscc >> 24); + printf(" Lower Write Enable on Write Status: 0x%02x\n", + vscc & (1 << 20) ? 0x06 : 0x50); + printf(" Lower Write Status Required: %s\n", + vscc & (1 << 19) ? "Yes" : "No"); + printf(" Lower Write Granularity: %d bytes\n", + vscc & (1 << 18) ? 64 : 1); + printf(" Lower Block / Sector Erase Size: "); + switch ((vscc >> 16) & 0x3) { + case 0: + printf("256 Byte\n"); + break; + case 1: + printf("4KB\n"); + break; + case 2: + printf("8KB\n"); + break; + case 3: + printf("64KB\n"); + break; + } + + printf(" Upper Erase Opcode: 0x%02x\n", + (vscc >> 8) & 0xff); + printf(" Upper Write Enable on Write Status: 0x%02x\n", + vscc & (1 << 4) ? 0x06 : 0x50); + printf(" Upper Write Status Required: %s\n", + vscc & (1 << 3) ? "Yes" : "No"); + printf(" Upper Write Granularity: %d bytes\n", + vscc & (1 << 2) ? 64 : 1); + printf(" Upper Block / Sector Erase Size: "); + switch (vscc & 0x3) { + case 0: + printf("256 Byte\n"); + break; + case 1: + printf("4KB\n"); + break; + case 2: + printf("8KB\n"); + break; + case 3: + printf("64KB\n"); + break; + } +} + +static void dump_vtba(struct vtba_t *vtba, int vtl) +{ + int i; + int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8; + + printf("ME VSCC table:\n"); + for (i = 0; i < num; i++) { + printf(" JID%d: 0x%08x\n", i, vtba->entry[i].jid); + dump_jid(vtba->entry[i].jid); + printf(" VSCC%d: 0x%08x\n", i, vtba->entry[i].vscc); + dump_vscc(vtba->entry[i].vscc); + } + printf("\n"); +} + +static void dump_oem(uint8_t *oem) +{ + int i, j; + printf("OEM Section:\n"); + for (i = 0; i < 4; i++) { + printf("%02x:", i << 4); + for (j = 0; j < 16; j++) + printf(" %02x", oem[(i<<4)+j]); + printf("\n"); + } + printf("\n"); +} + +/** + * dump_fd() - Display a dump of the full flash description + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -1 on error + */ +static int dump_fd(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + + if (!fdb) + return -1; + + printf("FLMAP0: 0x%08x\n", fdb->flmap0); + printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); + printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4); + printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1); + printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4); + + printf("FLMAP1: 0x%08x\n", fdb->flmap1); + printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4); + printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3); + printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4); + + printf("FLMAP2: 0x%08x\n", fdb->flmap2); + printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); + printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + + printf("FLUMAP1: 0x%08x\n", fdb->flumap1); + printf(" Intel ME VSCC Table Length (VTL): %d\n", + (fdb->flumap1 >> 8) & 0xff); + printf(" Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n", + (fdb->flumap1 & 0xff) << 4); + dump_vtba((struct vtba_t *) + (image + ((fdb->flumap1 & 0xff) << 4)), + (fdb->flumap1 >> 8) & 0xff); + dump_oem((uint8_t *)image + 0xf00); + dump_frba((struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) + << 4))); + dump_fcba((struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4))); + dump_fpsba((struct fpsba_t *) + (image + (((fdb->flmap1 >> 16) & 0xff) << 4))); + dump_fmba((struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4))); + dump_fmsba((struct fmsba_t *)(image + (((fdb->flmap2) & 0xff) << 4))); + + return 0; +} + +/** + * write_regions() - Write each region from an image to its own file + * + * The filename to use in each case is fixed - see region_filename() + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -ve on error + */ +static int write_regions(char *image, int size) +{ + struct fdbar_t *fdb; + struct frba_t *frba; + int ret = 0; + int i; + + fdb = find_fd(image, size); + if (!fdb) + return -1; + + frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4)); + + for (i = 0; i < MAX_REGIONS; i++) { + struct region_t region; + int region_fd; + + ret = get_region(frba, i, ®ion); + if (ret) + return ret; + dump_region(i, frba); + if (region.size == 0) + continue; + region_fd = open(region_filename(i), + O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | + S_IWUSR | S_IRGRP | S_IROTH); + if (write(region_fd, image + region.base, region.size) != + region.size) { + perror("Error while writing"); + ret = -1; + } + close(region_fd); + } + + return ret; +} + +static int perror_fname(const char *fmt, const char *fname) +{ + char msg[strlen(fmt) + strlen(fname) + 1]; + + sprintf(msg, fmt, fname); + perror(msg); + + return -1; +} + +/** + * write_image() - Write the image to a file + * + * @filename: Filename to use for the image + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -ve on error + */ +static int write_image(char *filename, char *image, int size) +{ + int new_fd; + + debug("Writing new image to %s\n", filename); + + new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | + S_IWUSR | S_IRGRP | S_IROTH); + if (new_fd < 0) + return perror_fname("Could not open file '%s'", filename); + if (write(new_fd, image, size) != size) + return perror_fname("Could not write file '%s'", filename); + close(new_fd); + + return 0; +} + +/** + * set_spi_frequency() - Set the SPI frequency to use when booting + * + * Several frequencies are supported, some of which work with fast devices. + * For SPI emulators, the slowest (SPI_FREQUENCY_20MHZ) is often used. The + * Intel boot system uses this information somehow on boot. + * + * The image is updated with the supplied value + * + * @image: Pointer to image + * @size: Size of image in bytes + * @freq: SPI frequency to use + */ +static void set_spi_frequency(char *image, int size, enum spi_frequency freq) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fcba_t *fcba; + + fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)); + + /* clear bits 21-29 */ + fcba->flcomp &= ~0x3fe00000; + /* Read ID and Read Status Clock Frequency */ + fcba->flcomp |= freq << 27; + /* Write and Erase Clock Frequency */ + fcba->flcomp |= freq << 24; + /* Fast Read Clock Frequency */ + fcba->flcomp |= freq << 21; +} + +/** + * set_em100_mode() - Set a SPI frequency that will work with Dediprog EM100 + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void set_em100_mode(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fcba_t *fcba; + + fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)); + fcba->flcomp &= ~(1 << 30); + set_spi_frequency(image, size, SPI_FREQUENCY_20MHZ); +} + +/** + * lock_descriptor() - Lock the NE descriptor so it cannot be updated + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void lock_descriptor(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fmba_t *fmba; + + /* + * TODO: Dynamically take Platform Data Region and GbE Region into + * account. + */ + fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4)); + fmba->flmstr1 = 0x0a0b0000; + fmba->flmstr2 = 0x0c0d0000; + fmba->flmstr3 = 0x08080118; +} + +/** + * unlock_descriptor() - Lock the NE descriptor so it can be updated + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void unlock_descriptor(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fmba_t *fmba; + + fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4)); + fmba->flmstr1 = 0xffff0000; + fmba->flmstr2 = 0xffff0000; + fmba->flmstr3 = 0x08080118; +} + +/** + * open_for_read() - Open a file for reading + * + * @fname: Filename to open + * @sizep: Returns file size in bytes + * @return 0 if OK, -1 on error + */ +int open_for_read(const char *fname, int *sizep) +{ + int fd = open(fname, O_RDONLY); + struct stat buf; + + if (fd == -1) + return perror_fname("Could not open file '%s'", fname); + if (fstat(fd, &buf) == -1) + return perror_fname("Could not stat file '%s'", fname); + *sizep = buf.st_size; + debug("File %s is %d bytes\n", fname, *sizep); + + return fd; +} + +/** + * inject_region() - Add a file to an image region + * + * This puts a file into a particular region of the flash. Several pre-defined + * regions are used. + * + * @image: Pointer to image + * @size: Size of image in bytes + * @region_type: Region where the file should be added + * @region_fname: Filename to add to the image + * @return 0 if OK, -ve on error + */ +int inject_region(char *image, int size, int region_type, char *region_fname) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct region_t region; + struct frba_t *frba; + int region_size; + int offset = 0; + int region_fd; + int ret; + + if (!fdb) + exit(EXIT_FAILURE); + frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4)); + + ret = get_region(frba, region_type, ®ion); + if (ret) + return -1; + if (region.size <= 0xfff) { + fprintf(stderr, "Region %s is disabled in target. Not injecting.\n", + region_name(region_type)); + return -1; + } + + region_fd = open_for_read(region_fname, ®ion_size); + if (region_fd < 0) + return region_fd; + + if ((region_size > region.size) || + ((region_type != 1) && (region_size > region.size))) { + fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Not injecting.\n", + region_name(region_type), region.size, + region.size, region_size, region_size); + return -1; + } + + if ((region_type == 1) && (region_size < region.size)) { + fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Padding before injecting.\n", + region_name(region_type), region.size, + region.size, region_size, region_size); + offset = region.size - region_size; + memset(image + region.base, 0xff, offset); + } + + if (size < region.base + offset + region_size) { + fprintf(stderr, "Output file is too small. (%d < %d)\n", + size, region.base + offset + region_size); + return -1; + } + + if (read(region_fd, image + region.base + offset, region_size) + != region_size) { + perror("Could not read file"); + return -1; + } + + close(region_fd); + + debug("Adding %s as the %s section\n", region_fname, + region_name(region_type)); + + return 0; +} + +/** + * write_data() - Write some raw data into a region + * + * This puts a file into a particular place in the flash, ignoring the + * regions. Be careful not to overwrite something important. + * + * @image: Pointer to image + * @size: Size of image in bytes + * @addr: x86 ROM address to put file. The ROM ends at + * 0xffffffff so use an address relative to that. For an + * 8MB ROM the start address is 0xfff80000. + * @write_fname: Filename to add to the image + * @return number of bytes written if OK, -ve on error + */ +static int write_data(char *image, int size, unsigned int addr, + const char *write_fname) +{ + int write_fd, write_size; + int offset; + + write_fd = open_for_read(write_fname, &write_size); + if (write_fd < 0) + return write_fd; + + offset = (uint32_t)(addr + size); + debug("Writing %s to offset %#x\n", write_fname, offset); + + if (offset < 0 || offset + write_size > size) { + fprintf(stderr, "Output file is too small. (%d < %d)\n", + size, offset + write_size); + return -1; + } + + if (read(write_fd, image + offset, write_size) != write_size) { + perror("Could not read file"); + return -1; + } + + close(write_fd); + + return write_size; +} + +/** + * write_uboot() - Write U-Boot, device tree and microcode pointer + * + * This writes U-Boot into a place in the flash, followed by its device tree. + * The microcode pointer is written so that U-Boot can find the microcode in + * the device tree very early in boot. + * + * @image: Pointer to image + * @size: Size of image in bytes + * @uboot: Input file information for u-boot.bin + * @fdt: Input file information for u-boot.dtb + * @ucode_ptr: Address in U-Boot where the microcode pointer should be placed + * @return 0 if OK, -ve on error + */ +static int write_uboot(char *image, int size, struct input_file *uboot, + struct input_file *fdt, unsigned int ucode_ptr) +{ + const void *blob; + const char *data; + int uboot_size; + uint32_t *ptr; + int data_size; + int offset; + int node; + int ret; + + uboot_size = write_data(image, size, uboot->addr, uboot->fname); + if (uboot_size < 0) + return uboot_size; + fdt->addr = uboot->addr + uboot_size; + debug("U-Boot size %#x, FDT at %#x\n", uboot_size, fdt->addr); + ret = write_data(image, size, fdt->addr, fdt->fname); + if (ret < 0) + return ret; + + if (ucode_ptr) { + blob = (void *)image + (uint32_t)(fdt->addr + size); + debug("DTB at %lx\n", (char *)blob - image); + node = fdt_node_offset_by_compatible(blob, 0, + "intel,microcode"); + if (node < 0) { + debug("No microcode found in FDT: %s\n", + fdt_strerror(node)); + return -ENOENT; + } + data = fdt_getprop(blob, node, "data", &data_size); + if (!data) { + debug("No microcode data found in FDT: %s\n", + fdt_strerror(data_size)); + return -ENOENT; + } + offset = (uint32_t)(ucode_ptr + size); + ptr = (void *)image + offset; + ptr[0] = (data - image) - size; + ptr[1] = data_size; + debug("Wrote microcode pointer at %x: addr=%x, size=%x\n", + ucode_ptr, ptr[0], ptr[1]); + } + + return 0; +} + +static void print_version(void) +{ + printf("ifdtool v%s -- ", IFDTOOL_VERSION); + printf("Copyright (C) 2014 Google Inc.\n\n"); + printf("SPDX-License-Identifier: GPL-2.0+\n"); +} + +static void print_usage(const char *name) +{ + printf("usage: %s [-vhdix?] []\n", name); + printf("\n" + " -d | --dump: dump intel firmware descriptor\n" + " -x | --extract: extract intel fd modules\n" + " -i | --inject : inject file into region \n" + " -w | --write : write file to appear at memory address \n" + " multiple files can be written simultaneously\n" + " -s | --spifreq <20|33|50> set the SPI frequency\n" + " -e | --em100 set SPI frequency to 20MHz and disable\n" + " Dual Output Fast Read Support\n" + " -l | --lock Lock firmware descriptor and ME region\n" + " -u | --unlock Unlock firmware descriptor and ME region\n" + " -r | --romsize Specify ROM size\n" + " -D | --write-descriptor Write descriptor at base\n" + " -c | --create Create a new empty image\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" + " is one of Descriptor, BIOS, ME, GbE, Platform\n" + "\n"); +} + +/** + * get_two_words() - Convert a string into two words separated by : + * + * The supplied string is split at ':', two substrings are allocated and + * returned. + * + * @str: String to split + * @firstp: Returns first string + * @secondp: Returns second string + * @return 0 if OK, -ve if @str does not have a : + */ +static int get_two_words(const char *str, char **firstp, char **secondp) +{ + const char *p; + + p = strchr(str, ':'); + if (!p) + return -1; + *firstp = strdup(str); + (*firstp)[p - str] = '\0'; + *secondp = strdup(p + 1); + + return 0; +} + +int main(int argc, char *argv[]) +{ + int opt, option_index = 0; + int mode_dump = 0, mode_extract = 0, mode_inject = 0; + int mode_spifreq = 0, mode_em100 = 0, mode_locked = 0; + int mode_unlocked = 0, mode_write = 0, mode_write_descriptor = 0; + int create = 0; + char *region_type_string = NULL, *inject_fname = NULL; + char *desc_fname = NULL, *addr_str = NULL; + int region_type = -1, inputfreq = 0; + enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; + struct input_file input_file[WRITE_MAX], *ifile, *fdt = NULL; + unsigned char wr_idx, wr_num = 0; + int rom_size = -1; + bool write_it; + char *filename; + char *outfile = NULL; + struct stat buf; + int size = 0; + unsigned int ucode_ptr = 0; + bool have_uboot = false; + int bios_fd; + char *image; + int ret; + static struct option long_options[] = { + {"create", 0, NULL, 'c'}, + {"dump", 0, NULL, 'd'}, + {"descriptor", 1, NULL, 'D'}, + {"em100", 0, NULL, 'e'}, + {"extract", 0, NULL, 'x'}, + {"fdt", 1, NULL, 'f'}, + {"inject", 1, NULL, 'i'}, + {"lock", 0, NULL, 'l'}, + {"microcode", 1, NULL, 'm'}, + {"romsize", 1, NULL, 'r'}, + {"spifreq", 1, NULL, 's'}, + {"unlock", 0, NULL, 'u'}, + {"uboot", 1, NULL, 'U'}, + {"write", 1, NULL, 'w'}, + {"version", 0, NULL, 'v'}, + {"help", 0, NULL, 'h'}, + {0, 0, 0, 0} + }; + + while ((opt = getopt_long(argc, argv, "cdD:ef:hi:lm:r:s:uU:vw:x?", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'c': + create = 1; + break; + case 'd': + mode_dump = 1; + break; + case 'D': + mode_write_descriptor = 1; + desc_fname = optarg; + break; + case 'e': + mode_em100 = 1; + break; + case 'i': + if (get_two_words(optarg, ®ion_type_string, + &inject_fname)) { + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + if (!strcasecmp("Descriptor", region_type_string)) + region_type = 0; + else if (!strcasecmp("BIOS", region_type_string)) + region_type = 1; + else if (!strcasecmp("ME", region_type_string)) + region_type = 2; + else if (!strcasecmp("GbE", region_type_string)) + region_type = 3; + else if (!strcasecmp("Platform", region_type_string)) + region_type = 4; + if (region_type == -1) { + fprintf(stderr, "No such region type: '%s'\n\n", + region_type_string); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + mode_inject = 1; + break; + case 'l': + mode_locked = 1; + break; + case 'm': + ucode_ptr = strtoul(optarg, NULL, 0); + break; + case 'r': + rom_size = strtol(optarg, NULL, 0); + debug("ROM size %d\n", rom_size); + break; + case 's': + /* Parse the requested SPI frequency */ + inputfreq = strtol(optarg, NULL, 0); + switch (inputfreq) { + case 20: + spifreq = SPI_FREQUENCY_20MHZ; + break; + case 33: + spifreq = SPI_FREQUENCY_33MHZ; + break; + case 50: + spifreq = SPI_FREQUENCY_50MHZ; + break; + default: + fprintf(stderr, "Invalid SPI Frequency: %d\n", + inputfreq); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + mode_spifreq = 1; + break; + case 'u': + mode_unlocked = 1; + break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); + break; + case 'w': + case 'U': + case 'f': + ifile = &input_file[wr_num]; + mode_write = 1; + if (wr_num < WRITE_MAX) { + if (get_two_words(optarg, &addr_str, + &ifile->fname)) { + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + ifile->addr = strtol(optarg, NULL, 0); + ifile->type = opt == 'f' ? IF_fdt : + opt == 'U' ? IF_uboot : IF_normal; + if (ifile->type == IF_fdt) + fdt = ifile; + else if (ifile->type == IF_uboot) + have_uboot = true; + wr_num++; + } else { + fprintf(stderr, + "The number of files to write simultaneously exceeds the limitation (%d)\n", + WRITE_MAX); + } + break; + case 'x': + mode_extract = 1; + break; + case 'h': + case '?': + default: + print_usage(argv[0]); + exit(EXIT_SUCCESS); + break; + } + } + + if (mode_locked == 1 && mode_unlocked == 1) { + fprintf(stderr, "Locking/Unlocking FD and ME are mutually exclusive\n"); + exit(EXIT_FAILURE); + } + + if (mode_inject == 1 && mode_write == 1) { + fprintf(stderr, "Inject/Write are mutually exclusive\n"); + exit(EXIT_FAILURE); + } + + if ((mode_dump + mode_extract + mode_inject + + (mode_spifreq | mode_em100 | mode_unlocked | + mode_locked)) > 1) { + fprintf(stderr, "You may not specify more than one mode.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + if ((mode_dump + mode_extract + mode_inject + mode_spifreq + + mode_em100 + mode_locked + mode_unlocked + mode_write + + mode_write_descriptor) == 0 && !create) { + fprintf(stderr, "You need to specify a mode.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + if (create && rom_size == -1) { + fprintf(stderr, "You need to specify a rom size when creating.\n\n"); + exit(EXIT_FAILURE); + } + + if (optind + 1 != argc) { + fprintf(stderr, "You need to specify a file.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + if (have_uboot && !fdt) { + fprintf(stderr, + "You must supply a device tree file for U-Boot\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + filename = argv[optind]; + if (optind + 2 != argc) + outfile = argv[optind + 1]; + + if (create) + bios_fd = open(filename, O_WRONLY | O_CREAT, 0666); + else + bios_fd = open(filename, outfile ? O_RDONLY : O_RDWR); + + if (bios_fd == -1) { + perror("Could not open file"); + exit(EXIT_FAILURE); + } + + if (!create) { + if (fstat(bios_fd, &buf) == -1) { + perror("Could not stat file"); + exit(EXIT_FAILURE); + } + size = buf.st_size; + } + + debug("File %s is %d bytes\n", filename, size); + + if (rom_size == -1) + rom_size = size; + + image = malloc(rom_size); + if (!image) { + printf("Out of memory.\n"); + exit(EXIT_FAILURE); + } + + memset(image, '\xff', rom_size); + if (!create && read(bios_fd, image, size) != size) { + perror("Could not read file"); + exit(EXIT_FAILURE); + } + if (size != rom_size) { + debug("ROM size changed to %d bytes\n", rom_size); + size = rom_size; + } + + write_it = true; + ret = 0; + if (mode_dump) { + ret = dump_fd(image, size); + write_it = false; + } + + if (mode_extract) { + ret = write_regions(image, size); + write_it = false; + } + + if (mode_write_descriptor) + ret = write_data(image, size, -size, desc_fname); + + if (mode_inject) + ret = inject_region(image, size, region_type, inject_fname); + + if (mode_write) { + for (wr_idx = 0; wr_idx < wr_num; wr_idx++) { + ifile = &input_file[wr_idx]; + if (ifile->type == IF_fdt) { + continue; + } else if (ifile->type == IF_uboot) { + ret = write_uboot(image, size, ifile, fdt, + ucode_ptr); + } else { + ret = write_data(image, size, ifile->addr, + ifile->fname); + } + if (ret < 0) + break; + } + } + + if (mode_spifreq) + set_spi_frequency(image, size, spifreq); + + if (mode_em100) + set_em100_mode(image, size); + + if (mode_locked) + lock_descriptor(image, size); + + if (mode_unlocked) + unlock_descriptor(image, size); + + if (write_it) { + if (outfile) { + ret = write_image(outfile, image, size); + } else { + if (lseek(bios_fd, 0, SEEK_SET)) { + perror("Error while seeking"); + ret = -1; + } + if (write(bios_fd, image, size) != size) { + perror("Error while writing"); + ret = -1; + } + } + } + + free(image); + close(bios_fd); + + return ret < 0 ? 1 : 0; +} diff --git a/tools/ifdtool.h b/tools/ifdtool.h new file mode 100644 index 0000000000..0d0cc3685e --- /dev/null +++ b/tools/ifdtool.h @@ -0,0 +1,90 @@ +/* + * ifdtool - Manage Intel Firmware Descriptor information + * + * Copyright (C) 2011 The ChromiumOS Authors. + * + * SPDX-License-Identifier: GPL-2.0 + * + * From Coreboot project + */ + +#include + +#define __packed __attribute__((packed)) + +#define IFDTOOL_VERSION "1.1-U-Boot" + +#define WRITE_MAX 16 + +enum spi_frequency { + SPI_FREQUENCY_20MHZ = 0, + SPI_FREQUENCY_33MHZ = 1, + SPI_FREQUENCY_50MHZ = 4, +}; + +enum component_density { + COMPONENT_DENSITY_512KB = 0, + COMPONENT_DENSITY_1MB = 1, + COMPONENT_DENSITY_2MB = 2, + COMPONENT_DENSITY_4MB = 3, + COMPONENT_DENSITY_8MB = 4, + COMPONENT_DENSITY_16MB = 5, +}; + +/* flash descriptor */ +struct __packed fdbar_t { + uint32_t flvalsig; + uint32_t flmap0; + uint32_t flmap1; + uint32_t flmap2; + uint8_t reserved[0xefc - 0x20]; + uint32_t flumap1; +}; + +#define MAX_REGIONS 5 + +/* regions */ +struct __packed frba_t { + uint32_t flreg[MAX_REGIONS]; +}; + +/* component section */ +struct __packed fcba_t { + uint32_t flcomp; + uint32_t flill; + uint32_t flpb; +}; + +#define MAX_STRAPS 18 + +/* pch strap */ +struct __packed fpsba_t { + uint32_t pchstrp[MAX_STRAPS]; +}; + +/* master */ +struct __packed fmba_t { + uint32_t flmstr1; + uint32_t flmstr2; + uint32_t flmstr3; +}; + +/* processor strap */ +struct __packed fmsba_t { + uint32_t data[8]; +}; + +/* ME VSCC */ +struct vscc_t { + uint32_t jid; + uint32_t vscc; +}; + +struct vtba_t { + /* Actual number of entries specified in vtl */ + struct vscc_t entry[8]; +}; + +struct region_t { + int base, limit, size; +}; diff --git a/tools/image-host.c b/tools/image-host.c index 0d5c88ca73..7effb6cea5 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -10,6 +10,7 @@ */ #include "mkimage.h" +#include #include #include @@ -224,7 +225,9 @@ static int fit_image_process_sig(const char *keydir, void *keydest, ret = fit_image_write_sig(fit, noffset, value, value_len, comment, NULL, 0); if (ret) { - printf("Can't write signature for '%s' signature node in '%s' image node: %s\n", + if (ret == -FDT_ERR_NOSPACE) + return -ENOSPC; + printf("Can't write signature for '%s' signature node in '%s' conf node: %s\n", node_name, image_name, fdt_strerror(ret)); return -1; } @@ -403,7 +406,7 @@ static int fit_config_get_hash_list(void *fit, int conf_noffset, goto err_mem; /* Get a list of images that we intend to sign */ - prop = fit_config_get_image_list(fit, conf_noffset, &len, + prop = fit_config_get_image_list(fit, sig_offset, &len, &allow_missing); if (!prop) return 0; @@ -589,10 +592,13 @@ static int fit_config_process_sig(const char *keydir, void *keydest, return -1; } - if (fit_image_write_sig(fit, noffset, value, value_len, comment, - region_prop, region_proplen)) { - printf("Can't write signature for '%s' signature node in '%s' conf node\n", - node_name, conf_name); + ret = fit_image_write_sig(fit, noffset, value, value_len, comment, + region_prop, region_proplen); + if (ret) { + if (ret == -FDT_ERR_NOSPACE) + return -ENOSPC; + printf("Can't write signature for '%s' signature node in '%s' conf node: %s\n", + node_name, conf_name, fdt_strerror(ret)); return -1; } free(value); @@ -602,10 +608,15 @@ static int fit_config_process_sig(const char *keydir, void *keydest, info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); /* Write the public key into the supplied FDT file */ - if (keydest && info.algo->add_verify_data(&info, keydest)) { - printf("Failed to add verification data for '%s' signature node in '%s' image node\n", - node_name, conf_name); - return -1; + if (keydest) { + ret = info.algo->add_verify_data(&info, keydest); + if (ret == -ENOSPC) + return -ENOSPC; + if (ret) { + printf("Failed to add verification data for '%s' signature node in '%s' image node\n", + node_name, conf_name); + } + return ret; } return 0; @@ -678,7 +689,7 @@ int fit_add_verification_data(const char *keydir, void *keydest, void *fit, confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH); if (confs_noffset < 0) { printf("Can't find images parent node '%s' (%s)\n", - FIT_IMAGES_PATH, fdt_strerror(confs_noffset)); + FIT_CONFS_PATH, fdt_strerror(confs_noffset)); return -ENOENT; } @@ -695,3 +706,23 @@ int fit_add_verification_data(const char *keydir, void *keydest, void *fit, return 0; } + +#ifdef CONFIG_FIT_SIGNATURE +int fit_check_sign(const void *fit, const void *key) +{ + int cfg_noffset; + int ret; + + cfg_noffset = fit_conf_get_node(fit, NULL); + if (!cfg_noffset) + return -1; + + printf("Verifying Hash Integrity ... "); + ret = fit_config_verify(fit, cfg_noffset); + if (ret) + return ret; + ret = bootm_host_load_images(fit, cfg_noffset); + + return ret; +} +#endif diff --git a/tools/imagetool.c b/tools/imagetool.c new file mode 100644 index 0000000000..148e4662b7 --- /dev/null +++ b/tools/imagetool.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2013 + * + * Written by Guilherme Maciel Ferreira + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" + +#include + +struct image_type_params *imagetool_get_type(int type) +{ + struct image_type_params *curr; + struct image_type_params *start = ll_entry_start( + struct image_type_params, image_type); + struct image_type_params *end = ll_entry_end( + struct image_type_params, image_type); + + for (curr = start; curr != end; curr++) { + if (curr->check_image_type) { + if (!curr->check_image_type(type)) + return curr; + } + } + return NULL; +} + +int imagetool_verify_print_header( + void *ptr, + struct stat *sbuf, + struct image_type_params *tparams, + struct image_tool_params *params) +{ + int retval = -1; + struct image_type_params *curr; + + struct image_type_params *start = ll_entry_start( + struct image_type_params, image_type); + struct image_type_params *end = ll_entry_end( + struct image_type_params, image_type); + + for (curr = start; curr != end; curr++) { + if (curr->verify_header) { + retval = curr->verify_header((unsigned char *)ptr, + sbuf->st_size, params); + + if (retval == 0) { + /* + * Print the image information if verify is + * successful + */ + if (curr->print_header) { + curr->print_header(ptr); + } else { + fprintf(stderr, + "%s: print_header undefined for %s\n", + params->cmdname, curr->name); + } + break; + } + } + } + + return retval; +} + +int imagetool_save_subimage( + const char *file_name, + ulong file_data, + ulong file_len) +{ + int dfd; + + dfd = open(file_name, O_RDWR | O_CREAT | O_TRUNC | O_BINARY, + S_IRUSR | S_IWUSR); + if (dfd < 0) { + fprintf(stderr, "Can't open \"%s\": %s\n", + file_name, strerror(errno)); + return -1; + } + + if (write(dfd, (void *)file_data, file_len) != (ssize_t)file_len) { + fprintf(stderr, "Write error on \"%s\": %s\n", + file_name, strerror(errno)); + close(dfd); + return -1; + } + + close(dfd); + + return 0; +} diff --git a/tools/imagetool.h b/tools/imagetool.h new file mode 100644 index 0000000000..f35dec71c7 --- /dev/null +++ b/tools/imagetool.h @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2013 + * + * Written by Guilherme Maciel Ferreira + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMAGETOOL_H_ +#define _IMAGETOOL_H_ + +#include "os_support.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* define __KERNEL__ in order to get the definitions + * required by the linker list. This is probably not + * the best way to do this */ +#ifndef __KERNEL__ +#define __KERNEL__ +#include +#undef __KERNEL__ +#endif /* __KERNEL__ */ + +#include "fdt_host.h" + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#define IH_ARCH_DEFAULT IH_ARCH_INVALID + +/* + * This structure defines all such variables those are initialized by + * mkimage and dumpimage main core and need to be referred by image + * type specific functions + */ +struct image_tool_params { + int dflag; + int eflag; + int fflag; + int iflag; + int lflag; + int pflag; + int vflag; + int xflag; + int skipcpy; + int os; + int arch; + int type; + int comp; + char *dtc; + unsigned int addr; + unsigned int ep; + char *imagename; + char *imagename2; + char *datafile; + char *imagefile; + char *cmdname; + const char *outfile; /* Output filename */ + const char *keydir; /* Directory holding private keys */ + const char *keydest; /* Destination .dtb for public key */ + const char *comment; /* Comment to add to signature node */ + int require_keys; /* 1 to mark signing keys as 'required' */ +}; + +/* + * image type specific variables and callback functions + */ +struct image_type_params { + /* name is an identification tag string for added support */ + char *name; + /* + * header size is local to the specific image type to be supported, + * mkimage core treats this as number of bytes + */ + uint32_t header_size; + /* Image type header pointer */ + void *hdr; + /* + * There are several arguments that are passed on the command line + * and are registered as flags in image_tool_params structure. + * This callback function can be used to check the passed arguments + * are in-lined with the image type to be supported + * + * Returns 1 if parameter check is successful + */ + int (*check_params) (struct image_tool_params *); + /* + * This function is used by list command (i.e. mkimage -l ) + * image type verification code must be put here + * + * Returns 0 if image header verification is successful + * otherwise, returns respective negative error codes + */ + int (*verify_header) (unsigned char *, int, struct image_tool_params *); + /* Prints image information abstracting from image header */ + void (*print_header) (const void *); + /* + * The header or image contents need to be set as per image type to + * be generated using this callback function. + * further output file post processing (for ex. checksum calculation, + * padding bytes etc..) can also be done in this callback function. + */ + void (*set_header) (void *, struct stat *, int, + struct image_tool_params *); + /* + * This function is used by the command to retrieve a component + * (sub-image) from the image (i.e. dumpimage -i -p + * ). + * Thus the code to extract a file from an image must be put here. + * + * Returns 0 if the file was successfully retrieved from the image, + * or a negative value on error. + */ + int (*extract_subimage)(void *, struct image_tool_params *); + /* + * Some image generation support for ex (default image type) supports + * more than one type_ids, this callback function is used to check + * whether input (-T ) is supported by registered image + * generation/list low level code + */ + int (*check_image_type) (uint8_t); + /* This callback function will be executed if fflag is defined */ + int (*fflag_handle) (struct image_tool_params *); + /* + * This callback function will be executed for variable size record + * It is expected to build this header in memory and return its length + * and a pointer to it by using image_type_params.header_size and + * image_type_params.hdr. The return value shall indicate if an + * additional padding should be used when copying the data image + * by returning the padding length. + */ + int (*vrec_header) (struct image_tool_params *, + struct image_type_params *); +}; + +/** + * imagetool_get_type() - find the image type params for a given image type + * + * It scans all registers image type supports + * checks the input type for each supported image type + * + * if successful, + * returns respective image_type_params pointer if success + * if input type_id is not supported by any of image_type_support + * returns NULL + */ +struct image_type_params *imagetool_get_type(int type); + +/* + * imagetool_verify_print_header() - verifies the image header + * + * Scan registered image types and verify the image_header for each + * supported image type. If verification is successful, this prints + * the respective header. + * + * @return 0 on success, negative if input image format does not match with + * any of supported image types + */ +int imagetool_verify_print_header( + void *ptr, + struct stat *sbuf, + struct image_type_params *tparams, + struct image_tool_params *params); + +/** + * imagetool_save_subimage - store data into a file + * @file_name: name of the destination file + * @file_data: data to be written + * @file_len: the amount of data to store + * + * imagetool_save_subimage() store file_len bytes of data pointed by file_data + * into the file name by file_name. + * + * returns: + * zero in case of success or a negative value if fail. + */ +int imagetool_save_subimage( + const char *file_name, + ulong file_data, + ulong file_len); + +/* + * There is a c file associated with supported image type low level code + * for ex. default_image.c, fit_image.c + */ + + +void pbl_load_uboot(int fd, struct image_tool_params *mparams); + +#define U_BOOT_IMAGE_TYPE( \ + _id, \ + _name, \ + _header_size, \ + _header, \ + _check_params, \ + _verify_header, \ + _print_header, \ + _set_header, \ + _extract_subimage, \ + _check_image_type, \ + _fflag_handle, \ + _vrec_header \ + ) \ + ll_entry_declare(struct image_type_params, _id, image_type) = { \ + .name = _name, \ + .header_size = _header_size, \ + .hdr = _header, \ + .check_params = _check_params, \ + .verify_header = _verify_header, \ + .print_header = _print_header, \ + .set_header = _set_header, \ + .extract_subimage = _extract_subimage, \ + .check_image_type = _check_image_type, \ + .fflag_handle = _fflag_handle, \ + .vrec_header = _vrec_header \ + } + +#endif /* _IMAGETOOL_H_ */ diff --git a/tools/imagetool.lds b/tools/imagetool.lds new file mode 100644 index 0000000000..7e92b4ac66 --- /dev/null +++ b/tools/imagetool.lds @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2011-2012 The Chromium OS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +SECTIONS +{ + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + __u_boot_sandbox_option_start = .; + _u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) } + __u_boot_sandbox_option_end = .; + + __bss_start = .; +} + +INSERT BEFORE .data; diff --git a/tools/imls/Makefile b/tools/imls/Makefile deleted file mode 100644 index 1be1edb16a..0000000000 --- a/tools/imls/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -# -# (C) Copyright 2009 Marco Stornelli -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -# Generated executable files -BIN_FILES-y += imls - -# Source files which exist outside the tools/imls directory -EXT_OBJ_FILES-y += lib/crc32.o -EXT_OBJ_FILES-y += lib/md5.o -EXT_OBJ_FILES-y += lib/sha1.o -EXT_OBJ_FILES-y += common/image.o - -# Source files located in the tools/imls directory -OBJ_FILES-y += imls.o - -# Flattened device tree objects -LIBFDT_OBJ_FILES-y += fdt.o -LIBFDT_OBJ_FILES-y += fdt_ro.o -LIBFDT_OBJ_FILES-y += fdt_rw.o -LIBFDT_OBJ_FILES-y += fdt_strerror.o -LIBFDT_OBJ_FILES-y += fdt_wip.o - -# now $(obj) is defined -SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) -BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y))) -LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y)) - -# -# Compile for a hosted environment on the target -# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps -# -HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \ - -idirafter $(OBJTREE)/include2 \ - -idirafter $(OBJTREE)/include \ - -I $(SRCTREE)/lib/libfdt \ - -I $(SRCTREE)/tools \ - -DUSE_HOSTCC -D__KERNEL_STRICT_NAMES - -ifeq ($(MTD_VERSION),old) -HOSTCPPFLAGS += -DMTD_OLD -endif - -all: $(BINS) - -$(obj)imls: $(obj)imls.o $(obj)crc32.o $(obj)image.o $(obj)md5.o \ - $(obj)sha1.o $(LIBFDT_OBJS) - $(CC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(STRIP) $@ - -# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED -$(obj)image.o: $(SRCTREE)/common/image.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -$(obj)imls.o: $(SRCTREE)/tools/imls/imls.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -# Some of the tool objects need to be accessed from outside the tools/imls directory -$(obj)%.o: $(SRCTREE)/common/%.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/lib/%.c - $(CC) -g $(HOSTCFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -clean: - rm -rf *.o imls - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/tools/imls/README b/tools/imls/README deleted file mode 100644 index 9adf92305d..0000000000 --- a/tools/imls/README +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2009 Marco Stornelli -# -# SPDX-License-Identifier: GPL-2.0+ -# - -IMLS -------------- - -imls is an implementation of a Linux command line tool to access -to raw flash partitions and list images made with mkimage command. - -For building against older versions of the MTD headers (meaning before -v2.6.8-rc1) it is required to pass the argument "MTD_VERSION=old" to -make. - -Usage examples --------------- - -1) Flash with sectors of 128KiB and 32 sectors: - -> imls -c 32 -s 131072 /dev/mtd0 -Searching... -Image Name: foo -Created: Fri Apr 10 18:11:30 2009 -Image Type: Intel x86 Linux Standalone Program (uncompressed) -Data Size: 10716 Bytes = 10.46 kB = 0.01 MB -Load Address: 00000000 -Entry Point: 00000000 - -2) Flash with sectors of 64KiB and 128 sectors and with a search offset of one -sector: - -> imls -o 1 -c 128 -s 65536 /dev/mtd0 -Searching... -Image Name: foo -Created: Fri Apr 10 18:11:30 2009 -Image Type: Intel x86 Linux Standalone Program (uncompressed) -Data Size: 10716 Bytes = 10.46 kB = 0.01 MB -Load Address: 00000000 -Entry Point: 00000000 diff --git a/tools/imls/imls.c b/tools/imls/imls.c deleted file mode 100644 index 95043b450b..0000000000 --- a/tools/imls/imls.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) Copyright 2009 Marco Stornelli - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef MTD_OLD -#include -#include -#else -#define __user /* nothing */ -#include -#endif - -#include -#include -#include -#include - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -extern unsigned long crc32(unsigned long crc, const char *buf, unsigned int len); -static void usage(void); -static int image_verify_header(char *ptr, int fd); -static int flash_bad_block(int fd, uint8_t mtd_type, loff_t start); - -char *cmdname; -char *devicefile; - -unsigned int sectorcount = 0; -int sflag = 0; -unsigned int sectoroffset = 0; -unsigned int sectorsize = 0; -int cflag = 0; - -int main (int argc, char **argv) -{ - int fd = -1, err = 0, readbyte = 0, j; - struct mtd_info_user mtdinfo; - char buf[sizeof(image_header_t)]; - int found = 0; - - cmdname = *argv; - - while (--argc > 0 && **++argv == '-') { - while (*++*argv) { - switch (**argv) { - case 'c': - if (--argc <= 0) - usage (); - sectorcount = (unsigned int)atoi(*++argv); - cflag = 1; - goto NXTARG; - case 'o': - if (--argc <= 0) - usage (); - sectoroffset = (unsigned int)atoi(*++argv); - goto NXTARG; - - case 's': - if (--argc <= 0) - usage (); - sectorsize = (unsigned int)atoi(*++argv); - sflag = 1; - goto NXTARG; - default: - usage (); - } - } -NXTARG: ; - } - - if (argc != 1 || cflag == 0 || sflag == 0) - usage(); - - devicefile = *argv; - - fd = open(devicefile, O_RDONLY); - if (fd < 0) { - fprintf (stderr, "%s: Can't open %s: %s\n", - cmdname, devicefile, strerror(errno)); - exit(EXIT_FAILURE); - } - - err = ioctl(fd, MEMGETINFO, &mtdinfo); - if (err < 0) { - fprintf(stderr, "%s: Cannot get MTD information: %s\n",cmdname, - strerror(errno)); - exit(EXIT_FAILURE); - } - - if (mtdinfo.type != MTD_NORFLASH && mtdinfo.type != MTD_NANDFLASH) { - fprintf(stderr, "%s: Unsupported flash type %u\n", - cmdname, mtdinfo.type); - exit(EXIT_FAILURE); - } - - if (sectorsize * sectorcount != mtdinfo.size) { - fprintf(stderr, "%s: Partition size (%d) incompatible with " - "sector size and count\n", cmdname, mtdinfo.size); - exit(EXIT_FAILURE); - } - - if (sectorsize * sectoroffset >= mtdinfo.size) { - fprintf(stderr, "%s: Partition size (%d) incompatible with " - "sector offset given\n", cmdname, mtdinfo.size); - exit(EXIT_FAILURE); - } - - if (sectoroffset > sectorcount - 1) { - fprintf(stderr, "%s: Sector offset cannot be grater than " - "sector count minus one\n", cmdname); - exit(EXIT_FAILURE); - } - - printf("Searching....\n"); - - for (j = sectoroffset; j < sectorcount; ++j) { - - if (lseek(fd, j*sectorsize, SEEK_SET) != j*sectorsize) { - fprintf(stderr, "%s: lseek failure: %s\n", - cmdname, strerror(errno)); - exit(EXIT_FAILURE); - } - - err = flash_bad_block(fd, mtdinfo.type, j*sectorsize); - if (err < 0) - exit(EXIT_FAILURE); - if (err) - continue; /* Skip and jump to next */ - - readbyte = read(fd, buf, sizeof(image_header_t)); - if (readbyte != sizeof(image_header_t)) { - fprintf(stderr, "%s: Can't read from device: %s\n", - cmdname, strerror(errno)); - exit(EXIT_FAILURE); - } - - if (fdt_check_header(buf)) { - /* old-style image */ - if (image_verify_header(buf, fd)) { - found = 1; - image_print_contents((image_header_t *)buf); - } - } else { - /* FIT image */ - fit_print_contents(buf); - } - - } - - close(fd); - - if(!found) - printf("No images found\n"); - - exit(EXIT_SUCCESS); -} - -void usage() -{ - fprintf (stderr, "Usage:\n" - " %s [-o offset] -s size -c count device\n" - " -o ==> number of sectors to use as offset\n" - " -c ==> number of sectors\n" - " -s ==> size of sectors (byte)\n", - cmdname); - - exit(EXIT_FAILURE); -} - -static int image_verify_header(char *ptr, int fd) -{ - int len, nread; - char *data; - uint32_t checksum; - image_header_t *hdr = (image_header_t *)ptr; - char buf[PAGE_SIZE]; - - if (image_get_magic(hdr) != IH_MAGIC) - return 0; - - data = (char *)hdr; - len = image_get_header_size(); - - checksum = image_get_hcrc(hdr); - hdr->ih_hcrc = htonl(0); /* clear for re-calculation */ - - if (crc32(0, data, len) != checksum) { - fprintf(stderr, - "%s: Maybe image found but it has bad header checksum!\n", - cmdname); - return 0; - } - - len = image_get_size(hdr); - checksum = 0; - - while (len > 0) { - nread = read(fd, buf, MIN(len,PAGE_SIZE)); - if (nread != MIN(len,PAGE_SIZE)) { - fprintf(stderr, - "%s: Error while reading: %s\n", - cmdname, strerror(errno)); - exit(EXIT_FAILURE); - } - checksum = crc32(checksum, buf, nread); - len -= nread; - } - - if (checksum != image_get_dcrc(hdr)) { - fprintf (stderr, - "%s: Maybe image found but it has corrupted data!\n", - cmdname); - return 0; - } - - return 1; -} - -/* - * Test for bad block on NAND, just returns 0 on NOR, on NAND: - * 0 - block is good - * > 0 - block is bad - * < 0 - failed to test - */ -static int flash_bad_block(int fd, uint8_t mtd_type, loff_t start) -{ - if (mtd_type == MTD_NANDFLASH) { - int badblock = ioctl(fd, MEMGETBADBLOCK, &start); - - if (badblock < 0) { - fprintf(stderr,"%s: Cannot read bad block mark: %s\n", - cmdname, strerror(errno)); - return badblock; - } - - if (badblock) { - return badblock; - } - } - - return 0; -} diff --git a/tools/imximage.c b/tools/imximage.c index c8a9ad578b..3d37591886 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -6,16 +6,15 @@ * Marvell Semiconductor * Written-by: Prafulla Wadaskar * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ -/* Required to obtain the getline prototype from stdio.h */ -#define _GNU_SOURCE - -#include "mkimage.h" +#include "imagetool.h" #include #include "imximage.h" +#define UNDEFINED 0xFFFFFFFF + /* * Supported commands for configuration file */ @@ -23,6 +22,7 @@ static table_entry_t imximage_cmds[] = { {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, {CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset", }, {CMD_DATA, "DATA", "Reg Write Data", }, + {CMD_CSF, "CSF", "Command Sequence File", }, {CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", }, {-1, "", "", }, }; @@ -31,7 +31,7 @@ static table_entry_t imximage_cmds[] = { * Supported Boot options for configuration file * this is needed to set the correct flash offset */ -static table_entry_t imximage_bootops[] = { +static table_entry_t imximage_boot_offset[] = { {FLASH_OFFSET_ONENAND, "onenand", "OneNAND Flash",}, {FLASH_OFFSET_NAND, "nand", "NAND Flash", }, {FLASH_OFFSET_NOR, "nor", "NOR Flash", }, @@ -41,6 +41,20 @@ static table_entry_t imximage_bootops[] = { {-1, "", "Invalid", }, }; +/* + * Supported Boot options for configuration file + * this is needed to determine the initial load size + */ +static table_entry_t imximage_boot_loadsize[] = { + {FLASH_LOADSIZE_ONENAND, "onenand", "OneNAND Flash",}, + {FLASH_LOADSIZE_NAND, "nand", "NAND Flash", }, + {FLASH_LOADSIZE_NOR, "nor", "NOR Flash", }, + {FLASH_LOADSIZE_SATA, "sata", "SATA Disk", }, + {FLASH_LOADSIZE_SD, "sd", "SD Card", }, + {FLASH_LOADSIZE_SPI, "spi", "SPI Flash", }, + {-1, "", "Invalid", }, +}; + /* * IMXIMAGE version definition for i.MX chips */ @@ -52,12 +66,22 @@ static table_entry_t imximage_versions[] = { static struct imx_header imximage_header; static uint32_t imximage_version; +/* + * Image Vector Table Offset + * Initialized to a wrong not 4-bytes aligned address to + * check if it is was set by the cfg file. + */ +static uint32_t imximage_ivt_offset = UNDEFINED; +static uint32_t imximage_csf_size = UNDEFINED; +/* Initial Load Region Size */ +static uint32_t imximage_init_loadsize; static set_dcd_val_t set_dcd_val; static set_dcd_rst_t set_dcd_rst; static set_imx_hdr_t set_imx_hdr; static uint32_t max_dcd_entries; static uint32_t *header_size_ptr; +static uint32_t *csf_ptr; static uint32_t get_cfg_value(char *token, char *name, int linenr) { @@ -193,7 +217,8 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len, /* Set magic number */ fhdr_v1->app_code_barker = APP_CODE_BARKER; - hdr_base = entry_point - sizeof(struct imx_header); + /* TODO: check i.MX image V1 handling, for now use 'old' style */ + hdr_base = entry_point - 4096; fhdr_v1->app_dest_ptr = hdr_base - flash_offset; fhdr_v1->app_code_jump_vector = entry_point; @@ -220,19 +245,21 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len, fhdr_v2->entry = entry_point; fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0; - fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header); - + hdr_base = entry_point - imximage_init_loadsize + + flash_offset; + fhdr_v2->self = hdr_base; fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table); fhdr_v2->boot_data_ptr = hdr_base + offsetof(imx_header_v2_t, boot_data); - hdr_v2->boot_data.start = hdr_base - flash_offset; + hdr_v2->boot_data.start = entry_point - imximage_init_loadsize; - /* Security feature are not supported */ fhdr_v2->csf = 0; + header_size_ptr = &hdr_v2->boot_data.size; + csf_ptr = &fhdr_v2->csf; } -static void set_hdr_func(struct imx_header *imxhdr) +static void set_hdr_func(void) { switch (imximage_version) { case IMXIMAGE_V1: @@ -306,6 +333,13 @@ static void print_hdr_v2(struct imx_header *imx_hdr) genimg_print_size(hdr_v2->boot_data.size); printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr); printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry); + if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) && + (imximage_csf_size != UNDEFINED)) { + printf("HAB Blocks: %08x %08x %08x\n", + (uint32_t)fhdr_v2->self, 0, + hdr_v2->boot_data.size - imximage_ivt_offset - + imximage_csf_size); + } } static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token, @@ -324,21 +358,39 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token, exit(EXIT_FAILURE); } cmd_ver_first = 1; - set_hdr_func(imxhdr); + set_hdr_func(); break; case CMD_BOOT_FROM: - imxhdr->flash_offset = get_table_entry_id(imximage_bootops, + imximage_ivt_offset = get_table_entry_id(imximage_boot_offset, "imximage boot option", token); - if (imxhdr->flash_offset == -1) { + if (imximage_ivt_offset == -1) { fprintf(stderr, "Error: %s[%d] -Invalid boot device" "(%s)\n", name, lineno, token); exit(EXIT_FAILURE); } + + imximage_init_loadsize = + get_table_entry_id(imximage_boot_loadsize, + "imximage boot option", token); + + if (imximage_init_loadsize == -1) { + fprintf(stderr, + "Error: %s[%d] -Invalid boot device(%s)\n", + name, lineno, token); + exit(EXIT_FAILURE); + } + + /* + * The SOC loads from the storage starting at address 0 + * then ensures that the load size contains the offset + */ + if (imximage_init_loadsize < imximage_ivt_offset) + imximage_init_loadsize = imximage_ivt_offset; if (unlikely(cmd_ver_first != 1)) cmd_ver_first = 0; break; case CMD_BOOT_OFFSET: - imxhdr->flash_offset = get_cfg_value(token, name, lineno); + imximage_ivt_offset = get_cfg_value(token, name, lineno); if (unlikely(cmd_ver_first != 1)) cmd_ver_first = 0; break; @@ -348,6 +400,17 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token, if (unlikely(cmd_ver_first != 1)) cmd_ver_first = 0; break; + case CMD_CSF: + if (imximage_version != 2) { + fprintf(stderr, + "Error: %s[%d] - CSF only supported for VERSION 2(%s)\n", + name, lineno, token); + exit(EXIT_FAILURE); + } + imximage_csf_size = get_cfg_value(token, name, lineno); + if (unlikely(cmd_ver_first != 1)) + cmd_ver_first = 0; + break; } } @@ -408,7 +471,8 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name) exit(EXIT_FAILURE); } - /* Very simple parsing, line starting with # are comments + /* + * Very simple parsing, line starting with # are comments * and are dropped */ while ((getline(&line, &len, fd)) > 0) { @@ -439,7 +503,7 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name) fclose(fd); /* Exit if there is no BOOT_FROM field specifying the flash_offset */ - if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) { + if (imximage_ivt_offset == FLASH_OFFSET_UNDEFINED) { fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name); exit(EXIT_FAILURE); } @@ -456,7 +520,7 @@ static int imximage_check_image_types(uint8_t type) } static int imximage_verify_header(unsigned char *ptr, int image_size, - struct mkimage_params *params) + struct image_tool_params *params) { struct imx_header *imx_hdr = (struct imx_header *) ptr; @@ -485,7 +549,7 @@ static void imximage_print_header(const void *ptr) } static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, - struct mkimage_params *params) + struct image_tool_params *params) { struct imx_header *imxhdr = (struct imx_header *)ptr; uint32_t dcd_len; @@ -497,14 +561,22 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, */ imximage_version = IMXIMAGE_V1; /* Be able to detect if the cfg file has no BOOT_FROM tag */ - imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED; - set_hdr_func(imxhdr); + imximage_ivt_offset = FLASH_OFFSET_UNDEFINED; + imximage_csf_size = 0; + set_hdr_func(); /* Parse dcd configuration file */ dcd_len = parse_cfg_file(imxhdr, params->imagename); + if (imximage_version == IMXIMAGE_V2) { + if (imximage_init_loadsize < imximage_ivt_offset + + sizeof(imx_header_v2_t)) + imximage_init_loadsize = imximage_ivt_offset + + sizeof(imx_header_v2_t); + } + /* Set the imx header */ - (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset); + (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset); /* * ROM bug alert @@ -515,10 +587,16 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, * * The remaining fraction of a block bytes would not be loaded! */ - *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096); + *header_size_ptr = ROUND((sbuf->st_size + imximage_ivt_offset), 4096); + + if (csf_ptr && imximage_csf_size) { + *csf_ptr = params->ep - imximage_init_loadsize + + *header_size_ptr; + *header_size_ptr += imximage_csf_size; + } } -int imximage_check_params(struct mkimage_params *params) +int imximage_check_params(struct image_tool_params *params) { if (!params) return CFG_INVALID; @@ -540,21 +618,93 @@ int imximage_check_params(struct mkimage_params *params) (params->xflag) || !(strlen(params->imagename)); } +static int imximage_generate(struct image_tool_params *params, + struct image_type_params *tparams) +{ + struct imx_header *imxhdr; + size_t alloc_len; + struct stat sbuf; + char *datafile = params->datafile; + uint32_t pad_len; + + memset(&imximage_header, 0, sizeof(imximage_header)); + + /* + * In order to not change the old imx cfg file + * by adding VERSION command into it, here need + * set up function ptr group to V1 by default. + */ + imximage_version = IMXIMAGE_V1; + /* Be able to detect if the cfg file has no BOOT_FROM tag */ + imximage_ivt_offset = FLASH_OFFSET_UNDEFINED; + imximage_csf_size = 0; + set_hdr_func(); + + /* Parse dcd configuration file */ + parse_cfg_file(&imximage_header, params->imagename); + + /* TODO: check i.MX image V1 handling, for now use 'old' style */ + if (imximage_version == IMXIMAGE_V1) { + alloc_len = 4096; + } else { + if (imximage_init_loadsize < imximage_ivt_offset + + sizeof(imx_header_v2_t)) + imximage_init_loadsize = imximage_ivt_offset + + sizeof(imx_header_v2_t); + alloc_len = imximage_init_loadsize - imximage_ivt_offset; + } + + if (alloc_len < sizeof(struct imx_header)) { + fprintf(stderr, "%s: header error\n", + params->cmdname); + exit(EXIT_FAILURE); + } + + imxhdr = malloc(alloc_len); + + if (!imxhdr) { + fprintf(stderr, "%s: malloc return failure: %s\n", + params->cmdname, strerror(errno)); + exit(EXIT_FAILURE); + } + + memset(imxhdr, 0, alloc_len); + + tparams->header_size = alloc_len; + tparams->hdr = imxhdr; + + /* determine data image file length */ + + if (stat(datafile, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat %s: %s\n", + params->cmdname, datafile, strerror(errno)); + exit(EXIT_FAILURE); + } + + pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size; + + /* TODO: check i.MX image V1 handling, for now use 'old' style */ + if (imximage_version == IMXIMAGE_V1) + return 0; + else + return pad_len; +} + + /* * imximage parameters */ -static struct image_type_params imximage_params = { - .name = "Freescale i.MX Boot Image support", - .header_size = sizeof(struct imx_header), - .hdr = (void *)&imximage_header, - .check_image_type = imximage_check_image_types, - .verify_header = imximage_verify_header, - .print_header = imximage_print_header, - .set_header = imximage_set_header, - .check_params = imximage_check_params, -}; - -void init_imx_image_type(void) -{ - mkimage_register(&imximage_params); -} +U_BOOT_IMAGE_TYPE( + imximage, + "Freescale i.MX Boot Image support", + 0, + NULL, + imximage_check_params, + imximage_verify_header, + imximage_print_header, + imximage_set_header, + NULL, + imximage_check_image_types, + NULL, + imximage_generate +); diff --git a/tools/imximage.h b/tools/imximage.h index 214187bb8c..5b5ad0edf4 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -2,25 +2,25 @@ * (C) Copyright 2009 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _IMXIMAGE_H_ #define _IMXIMAGE_H_ -#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */ +#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */ #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */ #define APP_CODE_BARKER 0xB1 #define DCD_BARKER 0xB17219E9 -#define HEADER_OFFSET 0x400 - /* * NOTE: This file must be kept in sync with arch/arm/include/asm/\ * imx-common/imximage.cfg because tools/imximage.c can not * cross-include headers from arch/arm/ and vice-versa. */ #define CMD_DATA_STR "DATA" + +/* Initial Vector Table Offset */ #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF #define FLASH_OFFSET_STANDARD 0x400 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD @@ -30,6 +30,16 @@ #define FLASH_OFFSET_NOR 0x1000 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD +/* Initial Load Region Size */ +#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF +#define FLASH_LOADSIZE_STANDARD 0x1000 +#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_ONENAND 0x400 +#define FLASH_LOADSIZE_NOR 0x0 /* entire image */ +#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD + #define IVT_HEADER_TAG 0xD1 #define IVT_VERSION 0x40 #define DCD_HEADER_TAG 0xD2 @@ -42,7 +52,8 @@ enum imximage_cmd { CMD_IMAGE_VERSION, CMD_BOOT_FROM, CMD_BOOT_OFFSET, - CMD_DATA + CMD_DATA, + CMD_CSF, }; enum imximage_fld_types { @@ -147,8 +158,7 @@ struct imx_header { imx_header_v1_t hdr_v1; imx_header_v2_t hdr_v2; } header; - uint32_t flash_offset; -} __attribute__((aligned(4096))); +}; typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, char *name, int lineno, diff --git a/tools/kermit/README b/tools/kermit/README new file mode 100644 index 0000000000..c3b491aa55 --- /dev/null +++ b/tools/kermit/README @@ -0,0 +1,51 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +This directory contains scripts that help to perform certain actions +that need to be done frequently when working with U-Boot. + +They are meant as EXAMPLE code, so it is very likely that you will +have to modify them before use. + + +Short description: +================== + +dot.kermrc: + + Example for "~/.kermrc" Kermit init file for use with U-Boot + + by Wolfgang Denk, 24 Jun 2001 + +flash_param: + + "kermit" script to automatically initialize the environment + variables on your target. This is most useful during + development when your environment variables are stored in an + embedded flash sector which is erased whenever you install a + new U-Boot image. + + by Swen Anderson, 10 May 2001 + +send_cmd: + + send_cmd U_BOOT_COMMAND + + "kermit" script to send a U-Boot command and print the + results. When used from a shell with history (like the bash) + this indirectly adds kind of history to U-Boot ;-) + + by Swen Anderson, 10 May 2001 + +send_image: + + send_image FILE_NAME OFFSET + + "kermit" script to automatically download a file to the + target using the "loadb" command (kermit binary protocol) + + by Swen Anderson, 10 May 2001 diff --git a/tools/scripts/dot.kermrc b/tools/kermit/dot.kermrc similarity index 100% rename from tools/scripts/dot.kermrc rename to tools/kermit/dot.kermrc diff --git a/tools/scripts/flash_param b/tools/kermit/flash_param similarity index 100% rename from tools/scripts/flash_param rename to tools/kermit/flash_param diff --git a/tools/scripts/send_cmd b/tools/kermit/send_cmd similarity index 100% rename from tools/scripts/send_cmd rename to tools/kermit/send_cmd diff --git a/tools/scripts/send_image b/tools/kermit/send_image similarity index 100% rename from tools/scripts/send_image rename to tools/kermit/send_image diff --git a/tools/kernel-doc/Makefile b/tools/kernel-doc/Makefile deleted file mode 100644 index eb56e2e753..0000000000 --- a/tools/kernel-doc/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (C) 2012 Marek Vasut -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -all: $(obj)docproc - -$(obj)docproc: docproc.c - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(HOSTSTRIP) $@ - -clean: - rm -rf docproc - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/tools/kwbimage.c b/tools/kwbimage.c index d08e49892d..66f459ad6b 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -1,367 +1,826 @@ /* - * (C) Copyright 2008 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar + * Image manipulator for Marvell SoCs + * supports Kirkwood, Dove, Armada 370, and Armada XP + * + * (C) Copyright 2013 Thomas Petazzoni + * * * SPDX-License-Identifier: GPL-2.0+ + * + * Not implemented: support for the register headers and secure + * headers in v1 images */ -/* Required to obtain the getline prototype from stdio.h */ -#define _GNU_SOURCE - -#include "mkimage.h" +#include "imagetool.h" +#include #include +#include #include "kwbimage.h" -/* - * Supported commands for configuration file - */ -static table_entry_t kwbimage_cmds[] = { - {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, - {CMD_NAND_ECC_MODE, "NAND_ECC_MODE", "NAND mode", }, - {CMD_NAND_PAGE_SIZE, "NAND_PAGE_SIZE", "NAND size", }, - {CMD_SATA_PIO_MODE, "SATA_PIO_MODE", "SATA mode", }, - {CMD_DDR_INIT_DELAY, "DDR_INIT_DELAY", "DDR init dly", }, - {CMD_DATA, "DATA", "Reg Write Data", }, - {CMD_INVALID, "", "", }, +#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1)) + +/* Structure of the main header, version 0 (Kirkwood, Dove) */ +struct main_hdr_v0 { + uint8_t blockid; /*0 */ + uint8_t nandeccmode; /*1 */ + uint16_t nandpagesize; /*2-3 */ + uint32_t blocksize; /*4-7 */ + uint32_t rsvd1; /*8-11 */ + uint32_t srcaddr; /*12-15 */ + uint32_t destaddr; /*16-19 */ + uint32_t execaddr; /*20-23 */ + uint8_t satapiomode; /*24 */ + uint8_t rsvd3; /*25 */ + uint16_t ddrinitdelay; /*26-27 */ + uint16_t rsvd2; /*28-29 */ + uint8_t ext; /*30 */ + uint8_t checksum; /*31 */ +}; + +struct ext_hdr_v0_reg { + uint32_t raddr; + uint32_t rdata; +}; + +#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg)) + +struct ext_hdr_v0 { + uint32_t offset; + uint8_t reserved[0x20 - sizeof(uint32_t)]; + struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT]; + uint8_t reserved2[7]; + uint8_t checksum; +}; + +/* Structure of the main header, version 1 (Armada 370, Armada XP) */ +struct main_hdr_v1 { + uint8_t blockid; /* 0 */ + uint8_t reserved1; /* 1 */ + uint16_t reserved2; /* 2-3 */ + uint32_t blocksize; /* 4-7 */ + uint8_t version; /* 8 */ + uint8_t headersz_msb; /* 9 */ + uint16_t headersz_lsb; /* A-B */ + uint32_t srcaddr; /* C-F */ + uint32_t destaddr; /* 10-13 */ + uint32_t execaddr; /* 14-17 */ + uint8_t reserved3; /* 18 */ + uint8_t nandblocksize; /* 19 */ + uint8_t nandbadblklocation; /* 1A */ + uint8_t reserved4; /* 1B */ + uint16_t reserved5; /* 1C-1D */ + uint8_t ext; /* 1E */ + uint8_t checksum; /* 1F */ }; /* - * Supported Boot options for configuration file + * Header for the optional headers, version 1 (Armada 370, Armada XP) */ -static table_entry_t kwbimage_bootops[] = { - {IBR_HDR_SPI_ID, "spi", "SPI Flash", }, - {IBR_HDR_NAND_ID, "nand", "NAND Flash", }, - {IBR_HDR_SATA_ID, "sata", "Sata port", }, - {IBR_HDR_PEX_ID, "pex", "PCIe port", }, - {IBR_HDR_UART_ID, "uart", "Serial port", }, - {-1, "", "Invalid", }, +struct opt_hdr_v1 { + uint8_t headertype; + uint8_t headersz_msb; + uint16_t headersz_lsb; + char data[0]; }; /* - * Supported NAND ecc options configuration file + * Various values for the opt_hdr_v1->headertype field, describing the + * different types of optional headers. The "secure" header contains + * informations related to secure boot (encryption keys, etc.). The + * "binary" header contains ARM binary code to be executed prior to + * executing the main payload (usually the bootloader). This is + * typically used to execute DDR3 training code. The "register" header + * allows to describe a set of (address, value) tuples that are + * generally used to configure the DRAM controller. */ -static table_entry_t kwbimage_eccmodes[] = { - {IBR_HDR_ECC_DEFAULT, "default", "Default mode", }, - {IBR_HDR_ECC_FORCED_HAMMING, "hamming", "Hamming mode", }, - {IBR_HDR_ECC_FORCED_RS, "rs", "RS mode", }, - {IBR_HDR_ECC_DISABLED, "disabled", "ECC Disabled", }, - {-1, "", "", }, +#define OPT_HDR_V1_SECURE_TYPE 0x1 +#define OPT_HDR_V1_BINARY_TYPE 0x2 +#define OPT_HDR_V1_REGISTER_TYPE 0x3 + +#define KWBHEADER_V1_SIZE(hdr) \ + (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb) + +static struct image_cfg_element *image_cfg; +static int cfgn; + +struct boot_mode { + unsigned int id; + const char *name; +}; + +struct boot_mode boot_modes[] = { + { 0x4D, "i2c" }, + { 0x5A, "spi" }, + { 0x8B, "nand" }, + { 0x78, "sata" }, + { 0x9C, "pex" }, + { 0x69, "uart" }, + {}, +}; + +struct nand_ecc_mode { + unsigned int id; + const char *name; }; -static struct kwb_header kwbimage_header; -static int datacmd_cnt = 0; -static char * fname = "Unknown"; -static int lineno = -1; +struct nand_ecc_mode nand_ecc_modes[] = { + { 0x00, "default" }, + { 0x01, "hamming" }, + { 0x02, "rs" }, + { 0x03, "disabled" }, + {}, +}; + +/* Used to identify an undefined execution or destination address */ +#define ADDR_INVALID ((uint32_t)-1) + +#define BINARY_MAX_ARGS 8 + +/* In-memory representation of a line of the configuration file */ +struct image_cfg_element { + enum { + IMAGE_CFG_VERSION = 0x1, + IMAGE_CFG_BOOT_FROM, + IMAGE_CFG_DEST_ADDR, + IMAGE_CFG_EXEC_ADDR, + IMAGE_CFG_NAND_BLKSZ, + IMAGE_CFG_NAND_BADBLK_LOCATION, + IMAGE_CFG_NAND_ECC_MODE, + IMAGE_CFG_NAND_PAGESZ, + IMAGE_CFG_BINARY, + IMAGE_CFG_PAYLOAD, + IMAGE_CFG_DATA, + } type; + union { + unsigned int version; + unsigned int bootfrom; + struct { + const char *file; + unsigned int args[BINARY_MAX_ARGS]; + unsigned int nargs; + } binary; + const char *payload; + unsigned int dstaddr; + unsigned int execaddr; + unsigned int nandblksz; + unsigned int nandbadblklocation; + unsigned int nandeccmode; + unsigned int nandpagesz; + struct ext_hdr_v0_reg regdata; + }; +}; + +#define IMAGE_CFG_ELEMENT_MAX 256 /* - * Report Error if xflag is set in addition to default + * Byte 8 of the image header contains the version number. In the v0 + * header, byte 8 was reserved, and always set to 0. In the v1 header, + * byte 8 has been changed to a proper field, set to 1. */ -static int kwbimage_check_params (struct mkimage_params *params) +static unsigned int image_version(void *header) { - if (!strlen (params->imagename)) { - printf ("Error:%s - Configuration file not specified, " - "it is needed for kwbimage generation\n", - params->cmdname); - return CFG_INVALID; - } - return ((params->dflag && (params->fflag || params->lflag)) || - (params->fflag && (params->dflag || params->lflag)) || - (params->lflag && (params->dflag || params->fflag)) || - (params->xflag) || !(strlen (params->imagename))); + unsigned char *ptr = header; + return ptr[8]; +} + +/* + * Utility functions to manipulate boot mode and ecc modes (convert + * them back and forth between description strings and the + * corresponding numerical identifiers). + */ + +static const char *image_boot_mode_name(unsigned int id) +{ + int i; + for (i = 0; boot_modes[i].name; i++) + if (boot_modes[i].id == id) + return boot_modes[i].name; + return NULL; } -static uint32_t check_get_hexval (char *token) +int image_boot_mode_id(const char *boot_mode_name) { - uint32_t hexval; + int i; + for (i = 0; boot_modes[i].name; i++) + if (!strcmp(boot_modes[i].name, boot_mode_name)) + return boot_modes[i].id; + + return -1; +} + +int image_nand_ecc_mode_id(const char *nand_ecc_mode_name) +{ + int i; + for (i = 0; nand_ecc_modes[i].name; i++) + if (!strcmp(nand_ecc_modes[i].name, nand_ecc_mode_name)) + return nand_ecc_modes[i].id; + return -1; +} + +static struct image_cfg_element * +image_find_option(unsigned int optiontype) +{ + int i; - if (!sscanf (token, "%x", &hexval)) { - printf ("Error:%s[%d] - Invalid hex data(%s)\n", fname, - lineno, token); - exit (EXIT_FAILURE); + for (i = 0; i < cfgn; i++) { + if (image_cfg[i].type == optiontype) + return &image_cfg[i]; } - return hexval; + + return NULL; +} + +static unsigned int +image_count_options(unsigned int optiontype) +{ + int i; + unsigned int count = 0; + + for (i = 0; i < cfgn; i++) + if (image_cfg[i].type == optiontype) + count++; + + return count; } /* - * Generates 8 bit checksum + * Compute a 8-bit checksum of a memory area. This algorithm follows + * the requirements of the Marvell SoC BootROM specifications. */ -static uint8_t kwbimage_checksum8 (void *start, uint32_t len, uint8_t csum) +static uint8_t image_checksum8(void *start, uint32_t len) { - register uint8_t sum = csum; - volatile uint8_t *p = (volatile uint8_t *)start; + uint8_t csum = 0; + uint8_t *p = start; /* check len and return zero checksum if invalid */ if (!len) return 0; do { - sum += *p; + csum += *p; p++; } while (--len); - return (sum); + + return csum; } -/* - * Generates 32 bit checksum - */ -static uint32_t kwbimage_checksum32 (uint32_t *start, uint32_t len, uint32_t csum) +static uint32_t image_checksum32(void *start, uint32_t len) { - register uint32_t sum = csum; - volatile uint32_t *p = start; + uint32_t csum = 0; + uint32_t *p = start; /* check len and return zero checksum if invalid */ if (!len) return 0; if (len % sizeof(uint32_t)) { - printf ("Error:%s[%d] - length is not in multiple of %zu\n", - __FUNCTION__, len, sizeof(uint32_t)); + fprintf(stderr, "Length %d is not in multiple of %zu\n", + len, sizeof(uint32_t)); return 0; } do { - sum += *p; + csum += *p; p++; len -= sizeof(uint32_t); } while (len > 0); - return (sum); + + return csum; } -static void kwbimage_check_cfgdata (char *token, enum kwbimage_cmd cmdsw, - struct kwb_header *kwbhdr) +static void *image_create_v0(size_t *imagesz, struct image_tool_params *params, + int payloadsz) { - bhr_t *mhdr = &kwbhdr->kwb_hdr; - extbhr_t *exthdr = &kwbhdr->kwb_exthdr; - int i; + struct image_cfg_element *e; + size_t headersz; + struct main_hdr_v0 *main_hdr; + struct ext_hdr_v0 *ext_hdr; + void *image; + int has_ext = 0; + + /* + * Calculate the size of the header and the size of the + * payload + */ + headersz = sizeof(struct main_hdr_v0); + + if (image_count_options(IMAGE_CFG_DATA) > 0) { + has_ext = 1; + headersz += sizeof(struct ext_hdr_v0); + } - switch (cmdsw) { - case CMD_BOOT_FROM: - i = get_table_entry_id (kwbimage_bootops, - "Kwbimage boot option", token); + if (image_count_options(IMAGE_CFG_PAYLOAD) > 1) { + fprintf(stderr, "More than one payload, not possible\n"); + return NULL; + } - if (i < 0) - goto INVL_DATA; + image = malloc(headersz); + if (!image) { + fprintf(stderr, "Cannot allocate memory for image\n"); + return NULL; + } - mhdr->blockid = i; - printf ("Preparing kirkwood boot image to boot " - "from %s\n", token); - break; - case CMD_NAND_ECC_MODE: - i = get_table_entry_id (kwbimage_eccmodes, - "NAND ecc mode", token); + memset(image, 0, headersz); + + main_hdr = image; + + /* Fill in the main header */ + main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz; + main_hdr->srcaddr = headersz; + main_hdr->ext = has_ext; + main_hdr->destaddr = params->addr; + main_hdr->execaddr = params->ep; + + e = image_find_option(IMAGE_CFG_BOOT_FROM); + if (e) + main_hdr->blockid = e->bootfrom; + e = image_find_option(IMAGE_CFG_NAND_ECC_MODE); + if (e) + main_hdr->nandeccmode = e->nandeccmode; + e = image_find_option(IMAGE_CFG_NAND_PAGESZ); + if (e) + main_hdr->nandpagesize = e->nandpagesz; + main_hdr->checksum = image_checksum8(image, + sizeof(struct main_hdr_v0)); + + /* Generate the ext header */ + if (has_ext) { + int cfgi, datai; + + ext_hdr = image + sizeof(struct main_hdr_v0); + ext_hdr->offset = 0x40; + + for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) { + e = &image_cfg[cfgi]; + if (e->type != IMAGE_CFG_DATA) + continue; + + ext_hdr->rcfg[datai].raddr = e->regdata.raddr; + ext_hdr->rcfg[datai].rdata = e->regdata.rdata; + datai++; + } - if (i < 0) - goto INVL_DATA; + ext_hdr->checksum = image_checksum8(ext_hdr, + sizeof(struct ext_hdr_v0)); + } - mhdr->nandeccmode = i; - printf ("Nand ECC mode = %s\n", token); - break; - case CMD_NAND_PAGE_SIZE: - mhdr->nandpagesize = - (uint16_t) check_get_hexval (token); - printf ("Nand page size = 0x%x\n", mhdr->nandpagesize); - break; - case CMD_SATA_PIO_MODE: - mhdr->satapiomode = - (uint8_t) check_get_hexval (token); - printf ("Sata PIO mode = 0x%x\n", - mhdr->satapiomode); - break; - case CMD_DDR_INIT_DELAY: - mhdr->ddrinitdelay = - (uint16_t) check_get_hexval (token); - printf ("DDR init delay = %d msec\n", mhdr->ddrinitdelay); - break; - case CMD_DATA: - exthdr->rcfg[datacmd_cnt].raddr = - check_get_hexval (token); + *imagesz = headersz; + return image; +} - break; - case CMD_INVALID: - goto INVL_DATA; - default: - goto INVL_DATA; +static size_t image_headersz_v1(struct image_tool_params *params, + int *hasext) +{ + struct image_cfg_element *binarye; + size_t headersz; + int ret; + + /* + * Calculate the size of the header and the size of the + * payload + */ + headersz = sizeof(struct main_hdr_v1); + + if (image_count_options(IMAGE_CFG_BINARY) > 1) { + fprintf(stderr, "More than one binary blob, not supported\n"); + return 0; } - return; -INVL_DATA: - printf ("Error:%s[%d] - Invalid data\n", fname, lineno); - exit (EXIT_FAILURE); + if (image_count_options(IMAGE_CFG_PAYLOAD) > 1) { + fprintf(stderr, "More than one payload, not possible\n"); + return 0; + } + + binarye = image_find_option(IMAGE_CFG_BINARY); + if (binarye) { + struct stat s; + + ret = stat(binarye->binary.file, &s); + if (ret < 0) { + char cwd[PATH_MAX]; + char *dir = cwd; + + memset(cwd, 0, sizeof(cwd)); + if (!getcwd(cwd, sizeof(cwd))) { + dir = "current working directory"; + perror("getcwd() failed"); + } + + fprintf(stderr, + "Didn't find the file '%s' in '%s' which is mandatory to generate the image\n" + "This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n" + "image for your board. See 'kwbimage -x' to extract it from an existing image.\n", + binarye->binary.file, dir); + return 0; + } + + headersz += s.st_size + + binarye->binary.nargs * sizeof(unsigned int); + if (hasext) + *hasext = 1; + } + + /* + * The payload should be aligned on some reasonable + * boundary + */ + return ALIGN_SUP(headersz, 4096); } -/* - * this function sets the kwbimage header by- - * 1. Abstracting input command line arguments data - * 2. parses the kwbimage configuration file and update extebded header data - * 3. calculates header, extended header and image checksums - */ -static void kwdimage_set_ext_header (struct kwb_header *kwbhdr, char* name) { - bhr_t *mhdr = &kwbhdr->kwb_hdr; - extbhr_t *exthdr = &kwbhdr->kwb_exthdr; - FILE *fd = NULL; - int j; - char *line = NULL; - char * token, *saveptr1, *saveptr2; - size_t len = 0; - enum kwbimage_cmd cmd; - - fname = name; - /* set dram register offset */ - exthdr->dramregsoffs = (intptr_t)&exthdr->rcfg - (intptr_t)mhdr; - - if ((fd = fopen (name, "r")) == 0) { - printf ("Error:%s - Can't open\n", fname); - exit (EXIT_FAILURE); +static void *image_create_v1(size_t *imagesz, struct image_tool_params *params, + int payloadsz) +{ + struct image_cfg_element *e, *binarye; + struct main_hdr_v1 *main_hdr; + size_t headersz; + void *image, *cur; + int hasext = 0; + int ret; + + /* + * Calculate the size of the header and the size of the + * payload + */ + headersz = image_headersz_v1(params, &hasext); + if (headersz == 0) + return NULL; + + image = malloc(headersz); + if (!image) { + fprintf(stderr, "Cannot allocate memory for image\n"); + return NULL; } - /* Simple kwimage.cfg file parser */ - lineno=0; - while ((getline (&line, &len, fd)) > 0) { - lineno++; - token = strtok_r (line, "\r\n", &saveptr1); - /* drop all lines with zero tokens (= empty lines) */ - if (token == NULL) - continue; + memset(image, 0, headersz); + + cur = main_hdr = image; + cur += sizeof(struct main_hdr_v1); + + /* Fill the main header */ + main_hdr->blocksize = payloadsz - headersz + sizeof(uint32_t); + main_hdr->headersz_lsb = headersz & 0xFFFF; + main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16; + main_hdr->destaddr = params->addr; + main_hdr->execaddr = params->ep; + main_hdr->srcaddr = headersz; + main_hdr->ext = hasext; + main_hdr->version = 1; + e = image_find_option(IMAGE_CFG_BOOT_FROM); + if (e) + main_hdr->blockid = e->bootfrom; + e = image_find_option(IMAGE_CFG_NAND_BLKSZ); + if (e) + main_hdr->nandblocksize = e->nandblksz / (64 * 1024); + e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION); + if (e) + main_hdr->nandbadblklocation = e->nandbadblklocation; + + binarye = image_find_option(IMAGE_CFG_BINARY); + if (binarye) { + struct opt_hdr_v1 *hdr = cur; + unsigned int *args; + size_t binhdrsz; + struct stat s; + int argi; + FILE *bin; + + hdr->headertype = OPT_HDR_V1_BINARY_TYPE; + + bin = fopen(binarye->binary.file, "r"); + if (!bin) { + fprintf(stderr, "Cannot open binary file %s\n", + binarye->binary.file); + return NULL; + } - for (j = 0, cmd = CMD_INVALID, line = token; ; line = NULL) { - token = strtok_r (line, " \t", &saveptr2); - if (token == NULL) - break; - /* Drop all text starting with '#' as comments */ - if (token[0] == '#') - break; + fstat(fileno(bin), &s); - /* Process rest as valid config command line */ - switch (j) { - case CFG_COMMAND: - cmd = get_table_entry_id (kwbimage_cmds, - "Kwbimage command", token); + binhdrsz = sizeof(struct opt_hdr_v1) + + (binarye->binary.nargs + 1) * sizeof(unsigned int) + + s.st_size; + hdr->headersz_lsb = binhdrsz & 0xFFFF; + hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16; - if (cmd == CMD_INVALID) - goto INVL_CMD; - break; + cur += sizeof(struct opt_hdr_v1); - case CFG_DATA0: - kwbimage_check_cfgdata (token, cmd, kwbhdr); - break; + args = cur; + *args = binarye->binary.nargs; + args++; + for (argi = 0; argi < binarye->binary.nargs; argi++) + args[argi] = binarye->binary.args[argi]; - case CFG_DATA1: - if (cmd != CMD_DATA) - goto INVL_CMD; - - exthdr->rcfg[datacmd_cnt].rdata = - check_get_hexval (token); - - if (datacmd_cnt > KWBIMAGE_MAX_CONFIG ) { - printf ("Error:%s[%d] - Found more " - "than max(%zd) allowed " - "data configurations\n", - fname, lineno, - KWBIMAGE_MAX_CONFIG); - exit (EXIT_FAILURE); - } else - datacmd_cnt++; - break; + cur += (binarye->binary.nargs + 1) * sizeof(unsigned int); + + ret = fread(cur, s.st_size, 1, bin); + if (ret != 1) { + fprintf(stderr, + "Could not read binary image %s\n", + binarye->binary.file); + return NULL; + } + + fclose(bin); - default: - goto INVL_CMD; + cur += s.st_size; + + /* + * For now, we don't support more than one binary + * header, and no other header types are + * supported. So, the binary header is necessarily the + * last one + */ + *((unsigned char *)cur) = 0; + + cur += sizeof(uint32_t); + } + + /* Calculate and set the header checksum */ + main_hdr->checksum = image_checksum8(main_hdr, headersz); + + *imagesz = headersz; + return image; +} + +static int image_create_config_parse_oneline(char *line, + struct image_cfg_element *el) +{ + char *keyword, *saveptr; + char deliminiters[] = " \t"; + + keyword = strtok_r(line, deliminiters, &saveptr); + if (!strcmp(keyword, "VERSION")) { + char *value = strtok_r(NULL, deliminiters, &saveptr); + el->type = IMAGE_CFG_VERSION; + el->version = atoi(value); + } else if (!strcmp(keyword, "BOOT_FROM")) { + char *value = strtok_r(NULL, deliminiters, &saveptr); + int ret = image_boot_mode_id(value); + if (ret < 0) { + fprintf(stderr, + "Invalid boot media '%s'\n", value); + return -1; + } + el->type = IMAGE_CFG_BOOT_FROM; + el->bootfrom = ret; + } else if (!strcmp(keyword, "NAND_BLKSZ")) { + char *value = strtok_r(NULL, deliminiters, &saveptr); + el->type = IMAGE_CFG_NAND_BLKSZ; + el->nandblksz = strtoul(value, NULL, 16); + } else if (!strcmp(keyword, "NAND_BADBLK_LOCATION")) { + char *value = strtok_r(NULL, deliminiters, &saveptr); + el->type = IMAGE_CFG_NAND_BADBLK_LOCATION; + el->nandbadblklocation = + strtoul(value, NULL, 16); + } else if (!strcmp(keyword, "NAND_ECC_MODE")) { + char *value = strtok_r(NULL, deliminiters, &saveptr); + int ret = image_nand_ecc_mode_id(value); + if (ret < 0) { + fprintf(stderr, + "Invalid NAND ECC mode '%s'\n", value); + return -1; + } + el->type = IMAGE_CFG_NAND_ECC_MODE; + el->nandeccmode = ret; + } else if (!strcmp(keyword, "NAND_PAGE_SIZE")) { + char *value = strtok_r(NULL, deliminiters, &saveptr); + el->type = IMAGE_CFG_NAND_PAGESZ; + el->nandpagesz = strtoul(value, NULL, 16); + } else if (!strcmp(keyword, "BINARY")) { + char *value = strtok_r(NULL, deliminiters, &saveptr); + int argi = 0; + + el->type = IMAGE_CFG_BINARY; + el->binary.file = strdup(value); + while (1) { + value = strtok_r(NULL, deliminiters, &saveptr); + if (!value) + break; + el->binary.args[argi] = strtoul(value, NULL, 16); + argi++; + if (argi >= BINARY_MAX_ARGS) { + fprintf(stderr, + "Too many argument for binary\n"); + return -1; } - j++; } + el->binary.nargs = argi; + } else if (!strcmp(keyword, "DATA")) { + char *value1 = strtok_r(NULL, deliminiters, &saveptr); + char *value2 = strtok_r(NULL, deliminiters, &saveptr); + + if (!value1 || !value2) { + fprintf(stderr, + "Invalid number of arguments for DATA\n"); + return -1; + } + + el->type = IMAGE_CFG_DATA; + el->regdata.raddr = strtoul(value1, NULL, 16); + el->regdata.rdata = strtoul(value2, NULL, 16); + } else { + fprintf(stderr, "Ignoring unknown line '%s'\n", line); } - if (line) - free (line); - fclose (fd); - return; + return 0; +} /* - * Invalid Command error reporring - * - * command CMD_DATA needs three strings on a line - * whereas other commands need only two. - * - * if more than two/three (as per command type) are observed, - * then error will be reported + * Parse the configuration file 'fcfg' into the array of configuration + * elements 'image_cfg', and return the number of configuration + * elements in 'cfgn'. */ -INVL_CMD: - printf ("Error:%s[%d] - Invalid command\n", fname, lineno); - exit (EXIT_FAILURE); +static int image_create_config_parse(FILE *fcfg) +{ + int ret; + int cfgi = 0; + + /* Parse the configuration file */ + while (!feof(fcfg)) { + char *line; + char buf[256]; + + /* Read the current line */ + memset(buf, 0, sizeof(buf)); + line = fgets(buf, sizeof(buf), fcfg); + if (!line) + break; + + /* Ignore useless lines */ + if (line[0] == '\n' || line[0] == '#') + continue; + + /* Strip final newline */ + if (line[strlen(line) - 1] == '\n') + line[strlen(line) - 1] = 0; + + /* Parse the current line */ + ret = image_create_config_parse_oneline(line, + &image_cfg[cfgi]); + if (ret) + return ret; + + cfgi++; + + if (cfgi >= IMAGE_CFG_ELEMENT_MAX) { + fprintf(stderr, + "Too many configuration elements in .cfg file\n"); + return -1; + } + } + + cfgn = cfgi; + return 0; +} + +static int image_get_version(void) +{ + struct image_cfg_element *e; + + e = image_find_option(IMAGE_CFG_VERSION); + if (!e) + return -1; + + return e->version; +} + +static int image_version_file(const char *input) +{ + FILE *fcfg; + int version; + int ret; + + fcfg = fopen(input, "r"); + if (!fcfg) { + fprintf(stderr, "Could not open input file %s\n", input); + return -1; + } + + image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX * + sizeof(struct image_cfg_element)); + if (!image_cfg) { + fprintf(stderr, "Cannot allocate memory\n"); + fclose(fcfg); + return -1; + } + + memset(image_cfg, 0, + IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element)); + rewind(fcfg); + + ret = image_create_config_parse(fcfg); + fclose(fcfg); + if (ret) { + free(image_cfg); + return -1; + } + + version = image_get_version(); + /* Fallback to version 0 is no version is provided in the cfg file */ + if (version == -1) + version = 0; + + free(image_cfg); + + return version; } -static void kwbimage_set_header (void *ptr, struct stat *sbuf, int ifd, - struct mkimage_params *params) +static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) { - struct kwb_header *hdr = (struct kwb_header *)ptr; - bhr_t *mhdr = &hdr->kwb_hdr; - extbhr_t *exthdr = &hdr->kwb_exthdr; + FILE *fcfg; + void *image = NULL; + int version; + size_t headersz = 0; uint32_t checksum; + int ret; int size; - /* Build and add image checksum header */ - checksum = kwbimage_checksum32 ((uint32_t *)ptr, sbuf->st_size, 0); + fcfg = fopen(params->imagename, "r"); + if (!fcfg) { + fprintf(stderr, "Could not open input file %s\n", + params->imagename); + exit(EXIT_FAILURE); + } + + image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX * + sizeof(struct image_cfg_element)); + if (!image_cfg) { + fprintf(stderr, "Cannot allocate memory\n"); + fclose(fcfg); + exit(EXIT_FAILURE); + } + + memset(image_cfg, 0, + IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element)); + rewind(fcfg); + + ret = image_create_config_parse(fcfg); + fclose(fcfg); + if (ret) { + free(image_cfg); + exit(EXIT_FAILURE); + } + + version = image_get_version(); + switch (version) { + /* + * Fallback to version 0 if no version is provided in the + * cfg file + */ + case -1: + case 0: + image = image_create_v0(&headersz, params, sbuf->st_size); + break; + + case 1: + image = image_create_v1(&headersz, params, sbuf->st_size); + break; + + default: + fprintf(stderr, "Unsupported version %d\n", version); + free(image_cfg); + exit(EXIT_FAILURE); + } + + if (!image) { + fprintf(stderr, "Could not create image\n"); + free(image_cfg); + exit(EXIT_FAILURE); + } - size = write (ifd, &checksum, sizeof(uint32_t)); + free(image_cfg); + + /* Build and add image checksum header */ + checksum = image_checksum32((uint32_t *)ptr, sbuf->st_size); + size = write(ifd, &checksum, sizeof(uint32_t)); if (size != sizeof(uint32_t)) { - printf ("Error:%s - Checksum write %d bytes %s\n", + fprintf(stderr, "Error:%s - Checksum write %d bytes %s\n", params->cmdname, size, params->imagefile); - exit (EXIT_FAILURE); + exit(EXIT_FAILURE); } sbuf->st_size += sizeof(uint32_t); - mhdr->blocksize = sbuf->st_size - sizeof(struct kwb_header); - mhdr->srcaddr = sizeof(struct kwb_header); - mhdr->destaddr= params->addr; - mhdr->execaddr =params->ep; - mhdr->ext = 0x1; /* header extension appended */ - - kwdimage_set_ext_header (hdr, params->imagename); - /* calculate checksums */ - mhdr->checkSum = kwbimage_checksum8 ((void *)mhdr, sizeof(bhr_t), 0); - exthdr->checkSum = kwbimage_checksum8 ((void *)exthdr, - sizeof(extbhr_t), 0); -} - -static int kwbimage_verify_header (unsigned char *ptr, int image_size, - struct mkimage_params *params) -{ - struct kwb_header *hdr = (struct kwb_header *)ptr; - bhr_t *mhdr = &hdr->kwb_hdr; - extbhr_t *exthdr = &hdr->kwb_exthdr; - uint8_t calc_hdrcsum; - uint8_t calc_exthdrcsum; - - calc_hdrcsum = kwbimage_checksum8 ((void *)mhdr, - sizeof(bhr_t) - sizeof(uint8_t), 0); - if (calc_hdrcsum != mhdr->checkSum) - return -FDT_ERR_BADSTRUCTURE; /* mhdr csum not matched */ - - calc_exthdrcsum = kwbimage_checksum8 ((void *)exthdr, - sizeof(extbhr_t) - sizeof(uint8_t), 0); - if (calc_exthdrcsum != exthdr->checkSum) - return -FDT_ERR_BADSTRUCTURE; /* exthdr csum not matched */ + /* Finally copy the header into the image area */ + memcpy(ptr, image, headersz); - return 0; + free(image); } -static void kwbimage_print_header (const void *ptr) +static void kwbimage_print_header(const void *ptr) { - struct kwb_header *hdr = (struct kwb_header *) ptr; - bhr_t *mhdr = &hdr->kwb_hdr; - char *name = get_table_entry_name (kwbimage_bootops, - "Kwbimage boot option", - (int) mhdr->blockid); - - printf ("Image Type: Kirkwood Boot from %s Image\n", name); - printf ("Data Size: "); - genimg_print_size (mhdr->blocksize - sizeof(uint32_t)); - printf ("Load Address: %08x\n", mhdr->destaddr); - printf ("Entry Point: %08x\n", mhdr->execaddr); + struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr; + + printf("Image Type: MVEBU Boot from %s Image\n", + image_boot_mode_name(mhdr->blockid)); + printf("Image version:%d\n", image_version((void *)ptr)); + printf("Data Size: "); + genimg_print_size(mhdr->blocksize - sizeof(uint32_t)); + printf("Load Address: %08x\n", mhdr->destaddr); + printf("Entry Point: %08x\n", mhdr->execaddr); } -static int kwbimage_check_image_types (uint8_t type) +static int kwbimage_check_image_types(uint8_t type) { if (type == IH_TYPE_KWBIMAGE) return EXIT_SUCCESS; @@ -369,21 +828,94 @@ static int kwbimage_check_image_types (uint8_t type) return EXIT_FAILURE; } +static int kwbimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct main_hdr_v0 *main_hdr; + struct ext_hdr_v0 *ext_hdr; + uint8_t checksum; + + main_hdr = (void *)ptr; + checksum = image_checksum8(ptr, + sizeof(struct main_hdr_v0) + - sizeof(uint8_t)); + if (checksum != main_hdr->checksum) + return -FDT_ERR_BADSTRUCTURE; + + /* Only version 0 extended header has checksum */ + if (image_version((void *)ptr) == 0) { + ext_hdr = (void *)ptr + sizeof(struct main_hdr_v0); + checksum = image_checksum8(ext_hdr, + sizeof(struct ext_hdr_v0) + - sizeof(uint8_t)); + if (checksum != ext_hdr->checksum) + return -FDT_ERR_BADSTRUCTURE; + } + + return 0; +} + +static int kwbimage_generate(struct image_tool_params *params, + struct image_type_params *tparams) +{ + int alloc_len; + void *hdr; + int version = 0; + + version = image_version_file(params->imagename); + if (version == 0) { + alloc_len = sizeof(struct main_hdr_v0) + + sizeof(struct ext_hdr_v0); + } else { + alloc_len = image_headersz_v1(params, NULL); + } + + hdr = malloc(alloc_len); + if (!hdr) { + fprintf(stderr, "%s: malloc return failure: %s\n", + params->cmdname, strerror(errno)); + exit(EXIT_FAILURE); + } + + memset(hdr, 0, alloc_len); + tparams->header_size = alloc_len; + tparams->hdr = hdr; + + return 0; +} + /* - * kwbimage type parameters definition + * Report Error if xflag is set in addition to default */ -static struct image_type_params kwbimage_params = { - .name = "Kirkwood Boot Image support", - .header_size = sizeof(struct kwb_header), - .hdr = (void*)&kwbimage_header, - .check_image_type = kwbimage_check_image_types, - .verify_header = kwbimage_verify_header, - .print_header = kwbimage_print_header, - .set_header = kwbimage_set_header, - .check_params = kwbimage_check_params, -}; - -void init_kwb_image_type (void) +static int kwbimage_check_params(struct image_tool_params *params) { - mkimage_register (&kwbimage_params); + if (!strlen(params->imagename)) { + fprintf(stderr, "Error:%s - Configuration file not specified, " + "it is needed for kwbimage generation\n", + params->cmdname); + return CFG_INVALID; + } + + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)) || + (params->xflag) || !(strlen(params->imagename)); } + +/* + * kwbimage type parameters definition + */ +U_BOOT_IMAGE_TYPE( + kwbimage, + "Marvell MVEBU Boot Image support", + 0, + NULL, + kwbimage_check_params, + kwbimage_verify_header, + kwbimage_print_header, + kwbimage_set_header, + NULL, + kwbimage_check_image_types, + NULL, + kwbimage_generate +); diff --git a/tools/kwboot.c b/tools/kwboot.c index e773f01df3..1368b4c948 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -1,5 +1,6 @@ /* - * Boot a Marvell Kirkwood SoC, with Xmodem over UART0. + * Boot a Marvell SoC, with Xmodem over UART0. + * supports Kirkwood, Dove, Armada 370, Armada XP * * (c) 2012 Daniel Stodden * @@ -37,9 +38,18 @@ static unsigned char kwboot_msg_boot[] = { 0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 }; +static unsigned char kwboot_msg_debug[] = { + 0xDD, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 +}; + +/* Defines known to work on Kirkwood */ #define KWBOOT_MSG_REQ_DELAY 10 /* ms */ #define KWBOOT_MSG_RSP_TIMEO 50 /* ms */ +/* Defines known to work on Armada XP */ +#define KWBOOT_MSG_REQ_DELAY_AXP 1000 /* ms */ +#define KWBOOT_MSG_RSP_TIMEO_AXP 1000 /* ms */ + /* * Xmodem Transfers */ @@ -62,6 +72,9 @@ struct kwboot_block { static int kwboot_verbose; +static int msg_req_delay = KWBOOT_MSG_REQ_DELAY; +static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO; + static void kwboot_printv(const char *fmt, ...) { @@ -184,6 +197,9 @@ kwboot_tty_send(int fd, const void *buf, size_t len) int rc; ssize_t n; + if (!buf) + return 0; + rc = -1; do { @@ -268,7 +284,10 @@ kwboot_bootmsg(int tty, void *msg) int rc; char c; - kwboot_printv("Sending boot message. Please reboot the target..."); + if (msg == NULL) + kwboot_printv("Please reboot the target into UART boot mode..."); + else + kwboot_printv("Sending boot message. Please reboot the target..."); do { rc = tcflush(tty, TCIOFLUSH); @@ -277,11 +296,11 @@ kwboot_bootmsg(int tty, void *msg) rc = kwboot_tty_send(tty, msg, 8); if (rc) { - usleep(KWBOOT_MSG_REQ_DELAY * 1000); + usleep(msg_req_delay * 1000); continue; } - rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO); + rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo); kwboot_spinner(); @@ -292,6 +311,37 @@ kwboot_bootmsg(int tty, void *msg) return rc; } +static int +kwboot_debugmsg(int tty, void *msg) +{ + int rc; + + kwboot_printv("Sending debug message. Please reboot the target..."); + + do { + char buf[16]; + + rc = tcflush(tty, TCIOFLUSH); + if (rc) + break; + + rc = kwboot_tty_send(tty, msg, 8); + if (rc) { + usleep(msg_req_delay * 1000); + continue; + } + + rc = kwboot_tty_recv(tty, buf, 16, msg_rsp_timeo); + + kwboot_spinner(); + + } while (rc); + + kwboot_printv("\n"); + + return rc; +} + static int kwboot_xm_makeblock(struct kwboot_block *block, const void *data, size_t size, int pnum) @@ -300,6 +350,7 @@ kwboot_xm_makeblock(struct kwboot_block *block, const void *data, size_t n; int i; + block->soh = SOH; block->pnum = pnum; block->_pnum = ~block->pnum; @@ -326,9 +377,15 @@ kwboot_xm_sendblock(int fd, struct kwboot_block *block) if (rc) break; - rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO); - if (rc) - break; + do { + rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO); + if (rc) + break; + + if (c != ACK && c != NAK && c != CAN) + printf("%c", c); + + } while (c != ACK && c != NAK && c != CAN); if (c != ACK) kwboot_progress(-1, '+'); @@ -511,7 +568,6 @@ kwboot_mmap_image(const char *path, size_t *size, int prot) void *img; rc = -1; - fd = -1; img = NULL; fd = open(path, O_RDONLY); @@ -601,11 +657,16 @@ static void kwboot_usage(FILE *stream, char *progname) { fprintf(stream, - "Usage: %s -b [ -p ] [ -t ] " - "[-B ] \n", progname); + "Usage: %s [-d | -a | -b | -D ] [ -t ] [-B ] \n", + progname); fprintf(stream, "\n"); - fprintf(stream, " -b : boot \n"); + fprintf(stream, + " -b : boot with preamble (Kirkwood, Armada 370/XP)\n"); fprintf(stream, " -p: patch to type 0x69 (uart boot)\n"); + fprintf(stream, + " -D : boot without preamble (Dove)\n"); + fprintf(stream, " -d: enter debug mode\n"); + fprintf(stream, " -a: use timings for Armada XP\n"); fprintf(stream, "\n"); fprintf(stream, " -t: mini terminal\n"); fprintf(stream, "\n"); @@ -619,6 +680,7 @@ main(int argc, char **argv) const char *ttypath, *imgpath; int rv, rc, tty, term, prot, patch; void *bootmsg; + void *debugmsg; void *img; size_t size; speed_t speed; @@ -626,6 +688,7 @@ main(int argc, char **argv) rv = 1; tty = -1; bootmsg = NULL; + debugmsg = NULL; imgpath = NULL; img = NULL; term = 0; @@ -636,7 +699,7 @@ main(int argc, char **argv) kwboot_verbose = isatty(STDOUT_FILENO); do { - int c = getopt(argc, argv, "hb:ptB:"); + int c = getopt(argc, argv, "hb:ptaB:dD:"); if (c < 0) break; @@ -646,6 +709,15 @@ main(int argc, char **argv) imgpath = optarg; break; + case 'D': + bootmsg = NULL; + imgpath = optarg; + break; + + case 'd': + debugmsg = kwboot_msg_debug; + break; + case 'p': patch = 1; break; @@ -654,6 +726,11 @@ main(int argc, char **argv) term = 1; break; + case 'a': + msg_req_delay = KWBOOT_MSG_REQ_DELAY_AXP; + msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO_AXP; + break; + case 'B': speed = kwboot_tty_speed(atoi(optarg)); if (speed == -1) @@ -667,7 +744,7 @@ main(int argc, char **argv) } } while (1); - if (!bootmsg && !term) + if (!bootmsg && !term && !debugmsg) goto usage; if (patch && !imgpath) @@ -702,7 +779,13 @@ main(int argc, char **argv) } } - if (bootmsg) { + if (debugmsg) { + rc = kwboot_debugmsg(tty, debugmsg); + if (rc) { + perror("debugmsg"); + goto out; + } + } else { rc = kwboot_bootmsg(tty, bootmsg); if (rc) { perror("bootmsg"); diff --git a/tools/logos/siemens.bmp b/tools/logos/siemens.bmp new file mode 100644 index 0000000000..bff2b190e0 Binary files /dev/null and b/tools/logos/siemens.bmp differ diff --git a/tools/logos/syteco.bmp b/tools/logos/syteco.bmp index 9a994fe3e3..14031f2c8c 100644 Binary files a/tools/logos/syteco.bmp and b/tools/logos/syteco.bmp differ diff --git a/tools/microcode-tool b/tools/microcode-tool new file mode 120000 index 0000000000..8be8507dd0 --- /dev/null +++ b/tools/microcode-tool @@ -0,0 +1 @@ +microcode-tool.py \ No newline at end of file diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py new file mode 100755 index 0000000000..003716d573 --- /dev/null +++ b/tools/microcode-tool.py @@ -0,0 +1,253 @@ +#!/usr/bin/env python +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Intel microcode update tool + +from optparse import OptionParser +import os +import re +import struct +import sys + +MICROCODE_DIR = 'arch/x86/dts/microcode' + +class Microcode: + """Holds information about the microcode for a particular model of CPU. + + Attributes: + name: Name of the CPU this microcode is for, including any version + information (e.g. 'm12206a7_00000029') + model: Model code string (this is cpuid(1).eax, e.g. '206a7') + words: List of hex words containing the microcode. The first 16 words + are the public header. + """ + def __init__(self, name, data): + self.name = name + # Convert data into a list of hex words + self.words = [] + for value in ''.join(data).split(','): + hexval = value.strip() + if hexval: + self.words.append(int(hexval, 0)) + + # The model is in the 4rd hex word + self.model = '%x' % self.words[3] + +def ParseFile(fname): + """Parse a micrcode.dat file and return the component parts + + Args: + fname: Filename to parse + Returns: + 3-Tuple: + date: String containing date from the file's header + license_text: List of text lines for the license file + microcodes: List of Microcode objects from the file + """ + re_date = re.compile('/\* *(.* [0-9]{4}) *\*/$') + re_license = re.compile('/[^-*+] *(.*)$') + re_name = re.compile('/\* *(.*)\.inc *\*/', re.IGNORECASE) + microcodes = {} + license_text = [] + date = '' + data = [] + name = None + with open(fname) as fd: + for line in fd: + line = line.rstrip() + m_date = re_date.match(line) + m_license = re_license.match(line) + m_name = re_name.match(line) + if m_name: + if name: + microcodes[name] = Microcode(name, data) + name = m_name.group(1).lower() + data = [] + elif m_license: + license_text.append(m_license.group(1)) + elif m_date: + date = m_date.group(1) + else: + data.append(line) + if name: + microcodes[name] = Microcode(name, data) + return date, license_text, microcodes + +def List(date, microcodes, model): + """List the available microcode chunks + + Args: + date: Date of the microcode file + microcodes: Dict of Microcode objects indexed by name + model: Model string to search for, or None + """ + print 'Date: %s' % date + if model: + mcode_list, tried = FindMicrocode(microcodes, model.lower()) + print 'Matching models %s:' % (', '.join(tried)) + else: + print 'All models:' + mcode_list = [microcodes[m] for m in microcodes.keys()] + for mcode in mcode_list: + print '%-20s: model %s' % (mcode.name, mcode.model) + +def FindMicrocode(microcodes, model): + """Find all the microcode chunks which match the given model. + + This model is something like 306a9 (the value returned in eax from + cpuid(1) when running on Intel CPUs). But we allow a partial match, + omitting the last 1 or two characters to allow many families to have the + same microcode. + + If the model name is ambiguous we return a list of matches. + + Args: + microcodes: Dict of Microcode objects indexed by name + model: String containing model name to find + Returns: + Tuple: + List of matching Microcode objects + List of abbreviations we tried + """ + # Allow a full name to be used + mcode = microcodes.get(model) + if mcode: + return [mcode], [] + + tried = [] + found = [] + for i in range(3): + abbrev = model[:-i] if i else model + tried.append(abbrev) + for mcode in microcodes.values(): + if mcode.model.startswith(abbrev): + found.append(mcode) + if found: + break + return found, tried + +def CreateFile(date, license_text, mcode, outfile): + """Create a microcode file in U-Boot's .dtsi format + + Args: + date: String containing date of original microcode file + license: List of text lines for the license file + mcode: Microcode object to write + outfile: Filename to write to ('-' for stdout) + """ + out = '''/*%s + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: %s + */ + +compatible = "intel,microcode"; +intel,header-version = <%d>; +intel,update-revision = <%#x>; +intel,date-code = <%#x>; +intel,processor-signature = <%#x>; +intel,checksum = <%#x>; +intel,loader-revision = <%d>; +intel,processor-flags = <%#x>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = <%s +\t>;''' + words = '' + for i in range(len(mcode.words)): + if not (i & 3): + words += '\n' + val = mcode.words[i] + # Change each word so it will be little-endian in the FDT + # This data is needed before RAM is available on some platforms so we + # cannot do an endianness swap on boot. + val = struct.unpack("I", val))[0] + words += '\t%#010x' % val + + # Take care to avoid adding a space before a tab + text = '' + for line in license_text: + if line[0] == '\t': + text += '\n *' + line + else: + text += '\n * ' + line + args = [text, date] + args += [mcode.words[i] for i in range(7)] + args.append(words) + if outfile == '-': + print out % tuple(args) + else: + if not outfile: + if not os.path.exists(MICROCODE_DIR): + print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR + os.makedirs(MICROCODE_DIR) + outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi') + print >> sys.stderr, "Writing microcode for '%s' to '%s'" % ( + mcode.name, outfile) + with open(outfile, 'w') as fd: + print >> fd, out % tuple(args) + +def MicrocodeTool(): + """Run the microcode tool""" + commands = 'create,license,list'.split(',') + parser = OptionParser() + parser.add_option('-d', '--mcfile', type='string', action='store', + help='Name of microcode.dat file') + parser.add_option('-m', '--model', type='string', action='store', + help='Model name to extract') + parser.add_option('-o', '--outfile', type='string', action='store', + help='Filename to use for output (- for stdout), default is' + ' %s/.dtsi' % MICROCODE_DIR) + parser.usage += """ command + + Process an Intel microcode file (use -h for help). Commands: + + create Create microcode .dtsi file for a model + list List available models in microcode file + license Print the license + + Typical usage: + + ./tools/microcode-tool -d microcode.dat -m 306a create + + This will find the appropriate file and write it to %s.""" % MICROCODE_DIR + + (options, args) = parser.parse_args() + if not args: + parser.error('Please specify a command') + cmd = args[0] + if cmd not in commands: + parser.error("Unknown command '%s'" % cmd) + + if not options.mcfile: + parser.error('You must specify a microcode file') + date, license_text, microcodes = ParseFile(options.mcfile) + + if cmd == 'list': + List(date, microcodes, options.model) + elif cmd == 'license': + print '\n'.join(license_text) + elif cmd == 'create': + if not options.model: + parser.error('You must specify a model to create') + model = options.model.lower() + mcode_list, tried = FindMicrocode(microcodes, model) + if not mcode_list: + parser.error("Unknown model '%s' (%s) - try 'list' to list" % + (model, ', '.join(tried))) + if len(mcode_list) > 1: + parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' " + "to list or specify a particular file" % + (model, ', '.join(tried), + ', '.join([m.name for m in mcode_list]))) + CreateFile(date, license_text, mcode_list[0], options.outfile) + else: + parser.error("Unknown command '%s'" % cmd) + +if __name__ == "__main__": + MicrocodeTool() diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index f685ff2e30..6971b91314 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -9,9 +9,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/* We want the GNU version of basename() */ -#define _GNU_SOURCE - #include #include #include @@ -40,6 +37,8 @@ static void usage(const char *exec_name) "\t\tkey1=value1\n" "\t\tkey2=value2\n" "\t\t...\n" + "\tEmpty lines are skipped, and lines with a # in the first\n" + "\tcolumn are treated as comments (also skipped).\n" "\t-r : the environment has multiple copies in flash\n" "\t-b : the target is big endian (default is little endian)\n" "\t-p : fill the image with bytes instead of 0xff bytes\n" @@ -224,10 +223,9 @@ int main(int argc, char **argv) /* Replace newlines separating variables with \0 */ for (fp = 0, ep = 0 ; fp < filesize ; fp++) { if (filebuf[fp] == '\n') { - if (ep == 0) { + if (fp == 0 || filebuf[fp-1] == '\n') { /* - * Newlines at the beginning of the file ? - * Ignore them. + * Skip empty lines. */ continue; } else if (filebuf[fp-1] == '\\') { @@ -243,6 +241,10 @@ int main(int argc, char **argv) /* End of a variable */ envptr[ep++] = '\0'; } + } else if ((fp == 0 || filebuf[fp-1] == '\n') && filebuf[fp] == '#') { + /* Comment, skip the line. */ + while (++fp < filesize && filebuf[fp] != '\n') + continue; } else { envptr[ep++] = filebuf[fp]; } diff --git a/tools/mkexynosspl.c b/tools/mkexynosspl.c index ef685b77ab..32b786c724 100644 --- a/tools/mkexynosspl.c +++ b/tools/mkexynosspl.c @@ -14,93 +14,174 @@ #include #define CHECKSUM_OFFSET (14*1024-4) -#define BUFSIZE (14*1024) #define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ | S_IWGRP | S_IROTH | S_IWOTH) /* -* Requirement: -* IROM code reads first 14K bytes from boot device. -* It then calculates the checksum of 14K-4 bytes and compare with data at -* 14K-4 offset. -* -* This function takes two filenames: -* IN "u-boot-spl.bin" and -* OUT "$(BOARD)-spl.bin as filenames. -* It reads the "u-boot-spl.bin" in 16K buffer. -* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. -* It writes the buffer to "$(BOARD)-spl.bin" file. -*/ + * Requirement for the fixed size SPL header: + * IROM code reads first (CHECKSUM_OFFSET + 4) bytes from boot device. It then + * calculates the checksum of CHECKSUM_OFFSET bytes and compares with data at + * CHECKSUM_OFFSET location. + * + * Requirement for the variable size SPL header: + + * IROM code reads the below header to find out the size of the blob (total + * size, header size included) and its checksum. Then it reads the rest of the + * blob [i.e size - sizeof(struct var_size_header) bytes], calculates the + * checksum and compares it with value read from the header. + */ +struct var_size_header { + uint32_t spl_size; + uint32_t spl_checksum; + uint32_t reserved[2]; +}; + +static const char *prog_name; + +static void write_to_file(int ofd, void *buffer, int size) +{ + if (write(ofd, buffer, size) == size) + return; + + fprintf(stderr, "%s: Failed to write to output file: %s\n", + prog_name, strerror(errno)); + exit(EXIT_FAILURE); +} +/* + * The argv is expected to include one optional parameter and two filenames: + * [--vs] IN OUT + * + * --vs - turns on the variable size SPL mode + * IN - the u-boot SPL binary, usually u-boot-spl.bin + * OUT - the prepared SPL blob, usually ${BOARD}-spl.bin + * + * This utility first reads the "u-boot-spl.bin" into a buffer. In case of + * fixed size SPL the buffer size is exactly CHECKSUM_OFFSET (such that + * smaller u-boot-spl.bin gets padded with 0xff bytes, the larger than limit + * u-boot-spl.bin causes an error). For variable size SPL the buffer size is + * eqaul to size of the IN file. + * + * Then it calculates checksum of the buffer by just summing up all bytes. + * Then + * + * - for fixed size SPL the buffer is written into the output file and the + * checksum is appended to the file in little endian format, which results + * in checksum added exactly at CHECKSUM_OFFSET. + * + * - for variable size SPL the checksum and file size are stored in the + * var_size_header structure (again, in little endian format) and the + * structure is written into the output file. Then the buffer is written + * into the output file. + */ int main(int argc, char **argv) { - unsigned char buffer[BUFSIZE]; + unsigned char *buffer; int i, ifd, ofd; uint32_t checksum = 0; off_t len; - ssize_t count; + int var_size_flag, read_size, count; struct stat stat; - - if (argc != 3) { - fprintf(stderr, "Usage: %s \n", argv[0]); + const int if_index = argc - 2; /* Input file name index in argv. */ + const int of_index = argc - 1; /* Output file name index in argv. */ + + /* Strip path off the program name. */ + prog_name = strrchr(argv[0], '/'); + if (prog_name) + prog_name++; + else + prog_name = argv[0]; + + if ((argc < 3) || + (argc > 4) || + ((argc == 4) && strcmp(argv[1], "--vs"))) { + fprintf(stderr, "Usage: %s [--vs] \n", + prog_name); exit(EXIT_FAILURE); } - ifd = open(argv[1], O_RDONLY); + /* four args mean variable size SPL wrapper is required */ + var_size_flag = (argc == 4); + + ifd = open(argv[if_index], O_RDONLY); if (ifd < 0) { fprintf(stderr, "%s: Can't open %s: %s\n", - argv[0], argv[1], strerror(errno)); + prog_name, argv[if_index], strerror(errno)); exit(EXIT_FAILURE); } - ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); + ofd = open(argv[of_index], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); if (ifd < 0) { fprintf(stderr, "%s: Can't open %s: %s\n", - argv[0], argv[2], strerror(errno)); - close(ifd); + prog_name, argv[of_index], strerror(errno)); exit(EXIT_FAILURE); } if (fstat(ifd, &stat)) { fprintf(stderr, "%s: Unable to get size of %s: %s\n", - argv[0], argv[1], strerror(errno)); - close(ifd); - close(ofd); + prog_name, argv[if_index], strerror(errno)); exit(EXIT_FAILURE); } len = stat.st_size; - count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET; - - if (read(ifd, buffer, count) != count) { - fprintf(stderr, "%s: Can't read %s: %s\n", - argv[0], argv[1], strerror(errno)); + if (var_size_flag) { + read_size = len; + count = len; + } else { + if (len > CHECKSUM_OFFSET) { + fprintf(stderr, + "%s: %s is too big (exceeds %d bytes)\n", + prog_name, argv[if_index], CHECKSUM_OFFSET); + exit(EXIT_FAILURE); + } + count = CHECKSUM_OFFSET; + read_size = len; + } - close(ifd); - close(ofd); + buffer = malloc(count); + if (!buffer) { + fprintf(stderr, + "%s: Failed to allocate %d bytes to store %s\n", + prog_name, count, argv[if_index]); + exit(EXIT_FAILURE); + } + if (read(ifd, buffer, read_size) != read_size) { + fprintf(stderr, "%s: Can't read %s: %s\n", + prog_name, argv[if_index], strerror(errno)); exit(EXIT_FAILURE); } - for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++) - checksum += buffer[i]; + /* Pad if needed with 0xff to make flashing faster. */ + if (read_size < count) + memset((char *)buffer + read_size, 0xff, count - read_size); + for (i = 0, checksum = 0; i < count; i++) + checksum += buffer[i]; checksum = cpu_to_le32(checksum); - memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum)); - - if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { - fprintf(stderr, "%s: Can't write %s: %s\n", - argv[0], argv[2], strerror(errno)); + if (var_size_flag) { + /* Prepare and write out the variable size SPL header. */ + struct var_size_header vsh; + uint32_t spl_size; - close(ifd); - close(ofd); + memset(&vsh, 0, sizeof(vsh)); + memcpy(&vsh.spl_checksum, &checksum, sizeof(checksum)); - exit(EXIT_FAILURE); + spl_size = cpu_to_le32(count + sizeof(struct var_size_header)); + memcpy(&vsh.spl_size, &spl_size, sizeof(spl_size)); + write_to_file(ofd, &vsh, sizeof(vsh)); } + write_to_file(ofd, buffer, count); + + /* For fixed size SPL checksum is appended in the end. */ + if (!var_size_flag) + write_to_file(ofd, &checksum, sizeof(checksum)); + close(ifd); close(ofd); + free(buffer); return EXIT_SUCCESS; } diff --git a/tools/mkimage.c b/tools/mkimage.c index b700b9e8c0..5ccd951048 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -15,11 +15,8 @@ static void copy_file(int, const char *, int); static void usage(void); -/* image_type_params link list to maintain registered image type supports */ -struct image_type_params *mkimage_tparams = NULL; - /* parameters initialized by core will be used by the image type code */ -struct mkimage_params params = { +struct image_tool_params params = { .os = IH_OS_LINUX, .arch = IH_ARCH_PPC, .type = IH_TYPE_KERNEL, @@ -29,106 +26,6 @@ struct mkimage_params params = { .imagename2 = "", }; -/* - * mkimage_register - - * - * It is used to register respective image generation/list support to the - * mkimage core - * - * the input struct image_type_params is checked and appended to the link - * list, if the input structure is already registered, error - */ -void mkimage_register (struct image_type_params *tparams) -{ - struct image_type_params **tp; - - if (!tparams) { - fprintf (stderr, "%s: %s: Null input\n", - params.cmdname, __FUNCTION__); - exit (EXIT_FAILURE); - } - - /* scan the linked list, check for registry and point the last one */ - for (tp = &mkimage_tparams; *tp != NULL; tp = &(*tp)->next) { - if (!strcmp((*tp)->name, tparams->name)) { - fprintf (stderr, "%s: %s already registered\n", - params.cmdname, tparams->name); - return; - } - } - - /* add input struct entry at the end of link list */ - *tp = tparams; - /* mark input entry as last entry in the link list */ - tparams->next = NULL; - - debug ("Registered %s\n", tparams->name); -} - -/* - * mkimage_get_type - - * - * It scans all registers image type supports - * checks the input type_id for each supported image type - * - * if successful, - * returns respective image_type_params pointer if success - * if input type_id is not supported by any of image_type_support - * returns NULL - */ -struct image_type_params *mkimage_get_type(int type) -{ - struct image_type_params *curr; - - for (curr = mkimage_tparams; curr != NULL; curr = curr->next) { - if (curr->check_image_type) { - if (!curr->check_image_type (type)) - return curr; - } - } - return NULL; -} - -/* - * mkimage_verify_print_header - - * - * It scans mkimage_tparams link list, - * verifies image_header for each supported image type - * if verification is successful, prints respective header - * - * returns negative if input image format does not match with any of - * supported image types - */ -int mkimage_verify_print_header (void *ptr, struct stat *sbuf) -{ - int retval = -1; - struct image_type_params *curr; - - for (curr = mkimage_tparams; curr != NULL; curr = curr->next ) { - if (curr->verify_header) { - retval = curr->verify_header ( - (unsigned char *)ptr, sbuf->st_size, - ¶ms); - - if (retval == 0) { - /* - * Print the image information - * if verify is successful - */ - if (curr->print_header) - curr->print_header (ptr); - else { - fprintf (stderr, - "%s: print_header undefined for %s\n", - params.cmdname, curr->name); - } - break; - } - } - } - return retval; -} - int main (int argc, char **argv) { @@ -137,23 +34,7 @@ main (int argc, char **argv) char *ptr; int retval = 0; struct image_type_params *tparams = NULL; - - /* Init Freescale PBL Boot image generation/list support */ - init_pbl_image_type(); - /* Init Kirkwood Boot image generation/list support */ - init_kwb_image_type (); - /* Init Freescale imx Boot image generation/list support */ - init_imx_image_type (); - /* Init FIT image generation/list support */ - init_fit_image_type (); - /* Init TI OMAP Boot image generation/list support */ - init_omap_image_type(); - /* Init Default image generation/list support */ - init_default_image_type (); - /* Init Davinci UBL support */ - init_ubl_image_type(); - /* Init Davinci AIS support */ - init_ais_image_type(); + int pad_len = 0; params.cmdname = *argv; params.addr = params.ep = 0; @@ -292,7 +173,7 @@ NXTARG: ; usage (); /* set tparams as per input type_id */ - tparams = mkimage_get_type(params.type); + tparams = imagetool_get_type(params.type); if (tparams == NULL) { fprintf (stderr, "%s: unsupported type %s\n", params.cmdname, genimg_get_type_name(params.type)); @@ -376,7 +257,8 @@ NXTARG: ; * Print the image information for matched image type * Returns the error code if not matched */ - retval = mkimage_verify_print_header (ptr, &sbuf); + retval = imagetool_verify_print_header(ptr, &sbuf, + tparams, ¶ms); (void) munmap((void *)ptr, sbuf.st_size); (void) close (ifd); @@ -391,7 +273,7 @@ NXTARG: ; * allocate memory for the header itself. */ if (tparams->vrec_header) - tparams->vrec_header(¶ms, tparams); + pad_len = tparams->vrec_header(¶ms, tparams); else memset(tparams->hdr, 0, tparams->header_size); @@ -463,7 +345,7 @@ NXTARG: ; /* PBL has special Image format, implements its' own */ pbl_load_uboot(ifd, ¶ms); } else { - copy_file (ifd, params.datafile, 0); + copy_file(ifd, params.datafile, pad_len); } } @@ -471,6 +353,7 @@ NXTARG: ; #if defined(_POSIX_SYNCHRONIZED_IO) && \ !defined(__sun__) && \ !defined(__FreeBSD__) && \ + !defined(__OpenBSD__) && \ !defined(__APPLE__) (void) fdatasync (ifd); #else @@ -514,6 +397,7 @@ NXTARG: ; #if defined(_POSIX_SYNCHRONIZED_IO) && \ !defined(__sun__) && \ !defined(__FreeBSD__) && \ + !defined(__OpenBSD__) && \ !defined(__APPLE__) (void) fdatasync (ifd); #else @@ -537,9 +421,18 @@ copy_file (int ifd, const char *datafile, int pad) unsigned char *ptr; int tail; int zero = 0; + uint8_t zeros[4096]; int offset = 0; int size; - struct image_type_params *tparams = mkimage_get_type (params.type); + struct image_type_params *tparams = imagetool_get_type(params.type); + + if (pad >= sizeof(zeros)) { + fprintf(stderr, "%s: Can't pad to %d\n", + params.cmdname, pad); + exit(EXIT_FAILURE); + } + + memset(zeros, 0, sizeof(zeros)); if (params.vflag) { fprintf (stderr, "Adding Image %s\n", datafile); @@ -598,7 +491,8 @@ copy_file (int ifd, const char *datafile, int pad) exit (EXIT_FAILURE); } - if (pad && ((tail = size % 4) != 0)) { + tail = size % 4; + if ((pad == 1) && (tail != 0)) { if (write(ifd, (char *)&zero, 4-tail) != 4-tail) { fprintf (stderr, "%s: Write error on %s: %s\n", @@ -606,14 +500,20 @@ copy_file (int ifd, const char *datafile, int pad) strerror(errno)); exit (EXIT_FAILURE); } + } else if (pad > 1) { + if (write(ifd, (char *)&zeros, pad) != pad) { + fprintf(stderr, "%s: Write error on %s: %s\n", + params.cmdname, params.imagefile, + strerror(errno)); + exit(EXIT_FAILURE); + } } (void) munmap((void *)ptr, sbuf.st_size); (void) close (dfd); } -void -usage () +static void usage(void) { fprintf (stderr, "Usage: %s -l image\n" " -l ==> list image header information\n", diff --git a/tools/mkimage.h b/tools/mkimage.h index 950e19067f..3f369b748e 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -18,8 +18,9 @@ #include #include #include -#include +#include #include "fdt_host.h" +#include "imagetool.h" #undef MKIMAGE_DEBUG @@ -29,8 +30,6 @@ #define debug(fmt,args...) #endif /* MKIMAGE_DEBUG */ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - static inline void *map_sysmem(ulong paddr, unsigned long len) { return (void *)(uintptr_t)paddr; @@ -47,120 +46,4 @@ static inline ulong map_to_sysmem(void *ptr) #define MKIMAGE_MAX_DTC_CMDLINE_LEN 512 #define MKIMAGE_DTC "dtc" /* assume dtc is in $PATH */ -#define IH_ARCH_DEFAULT IH_ARCH_INVALID - -/* - * This structure defines all such variables those are initialized by - * mkimage main core and need to be referred by image type specific - * functions - */ -struct mkimage_params { - int dflag; - int eflag; - int fflag; - int lflag; - int vflag; - int xflag; - int skipcpy; - int os; - int arch; - int type; - int comp; - char *dtc; - unsigned int addr; - unsigned int ep; - char *imagename; - char *imagename2; - char *datafile; - char *imagefile; - char *cmdname; - const char *keydir; /* Directory holding private keys */ - const char *keydest; /* Destination .dtb for public key */ - const char *comment; /* Comment to add to signature node */ - int require_keys; /* 1 to mark signing keys as 'required' */ -}; - -/* - * image type specific variables and callback functions - */ -struct image_type_params { - /* name is an identification tag string for added support */ - char *name; - /* - * header size is local to the specific image type to be supported, - * mkimage core treats this as number of bytes - */ - uint32_t header_size; - /* Image type header pointer */ - void *hdr; - /* - * There are several arguments that are passed on the command line - * and are registered as flags in mkimage_params structure. - * This callback function can be used to check the passed arguments - * are in-lined with the image type to be supported - * - * Returns 1 if parameter check is successful - */ - int (*check_params) (struct mkimage_params *); - /* - * This function is used by list command (i.e. mkimage -l ) - * image type verification code must be put here - * - * Returns 0 if image header verification is successful - * otherwise, returns respective negative error codes - */ - int (*verify_header) (unsigned char *, int, struct mkimage_params *); - /* Prints image information abstracting from image header */ - void (*print_header) (const void *); - /* - * The header or image contents need to be set as per image type to - * be generated using this callback function. - * further output file post processing (for ex. checksum calculation, - * padding bytes etc..) can also be done in this callback function. - */ - void (*set_header) (void *, struct stat *, int, - struct mkimage_params *); - /* - * Some image generation support for ex (default image type) supports - * more than one type_ids, this callback function is used to check - * whether input (-T ) is supported by registered image - * generation/list low level code - */ - int (*check_image_type) (uint8_t); - /* This callback function will be executed if fflag is defined */ - int (*fflag_handle) (struct mkimage_params *); - /* - * This callback function will be executed for variable size record - * It is expected to build this header in memory and return its length - * and a pointer to it - */ - int (*vrec_header) (struct mkimage_params *, - struct image_type_params *); - /* pointer to the next registered entry in linked list */ - struct image_type_params *next; -}; - -/* - * Exported functions - */ -void mkimage_register (struct image_type_params *tparams); - -/* - * There is a c file associated with supported image type low level code - * for ex. default_image.c, fit_image.c - * init is the only function referred by mkimage core. - * to avoid a single lined header file, you can define them here - * - * Supported image types init functions - */ -void pbl_load_uboot(int fd, struct mkimage_params *mparams); -void init_pbl_image_type(void); -void init_ais_image_type(void); -void init_kwb_image_type (void); -void init_imx_image_type (void); -void init_default_image_type (void); -void init_fit_image_type (void); -void init_ubl_image_type(void); -void init_omap_image_type(void); - #endif /* _MKIIMAGE_H_ */ diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c new file mode 100644 index 0000000000..1f0fbae8e1 --- /dev/null +++ b/tools/mksunxiboot.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * a simple tool to generate bootable image for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* boot head definition from sun4i boot code */ +struct boot_file_head { + uint32_t b_instruction; /* one intruction jumping to real code */ + uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + uint32_t check_sum; /* generated by PC */ + uint32_t length; /* generated by PC */ + /* + * We use a simplified header, only filling in what is needed + * by the boot ROM. To be compatible with Allwinner tools we + * would need to implement the proper fields here instead of + * padding. + */ + uint8_t pad[12]; /* align to 32 bytes */ +}; + +#define BOOT0_MAGIC "eGON.BT0" +#define STAMP_VALUE 0x5F0A6C39 + +/* check sum functon from sun4i boot code */ +int gen_check_sum(struct boot_file_head *head_p) +{ + uint32_t length; + uint32_t *buf; + uint32_t loop; + uint32_t i; + uint32_t sum; + + length = head_p->length; + if ((length & 0x3) != 0) /* must 4-byte-aligned */ + return -1; + buf = (uint32_t *)head_p; + head_p->check_sum = STAMP_VALUE; /* fill stamp */ + loop = length >> 2; + + /* calculate the sum */ + for (i = 0, sum = 0; i < loop; i++) + sum += buf[i]; + + /* write back check sum */ + head_p->check_sum = sum; + + return 0; +} + +#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1) +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) + +#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */ +#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head)) +#define BLOCK_SIZE 512 + +struct boot_img { + struct boot_file_head header; + char code[SRAM_LOAD_MAX_SIZE]; + char pad[BLOCK_SIZE]; +}; + +int main(int argc, char *argv[]) +{ + int fd_in, fd_out; + struct boot_img img; + unsigned file_size; + int count; + + if (argc < 2) { + printf("\tThis program makes an input bin file to sun4i " \ + "bootable image.\n" \ + "\tUsage: %s input_file out_putfile\n", argv[0]); + return EXIT_FAILURE; + } + + fd_in = open(argv[1], O_RDONLY); + if (fd_in < 0) { + perror("Open input file"); + return EXIT_FAILURE; + } + + memset(img.pad, 0, BLOCK_SIZE); + + /* get input file size */ + file_size = lseek(fd_in, 0, SEEK_END); + + if (file_size > SRAM_LOAD_MAX_SIZE) { + fprintf(stderr, "ERROR: File too large!\n"); + return EXIT_FAILURE; + } + + fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666); + if (fd_out < 0) { + perror("Open output file"); + return EXIT_FAILURE; + } + + /* read file to buffer to calculate checksum */ + lseek(fd_in, 0, SEEK_SET); + count = read(fd_in, img.code, file_size); + if (count != file_size) { + perror("Reading input image"); + return EXIT_FAILURE; + } + + /* fill the header */ + img.header.b_instruction = /* b instruction */ + 0xEA000000 | /* jump to the first instr after the header */ + ((sizeof(struct boot_file_head) / sizeof(int) - 2) + & 0x00FFFFFF); + memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */ + img.header.length = + ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE); + gen_check_sum(&img.header); + + count = write(fd_out, &img, img.header.length); + if (count != img.header.length) { + perror("Writing output"); + return EXIT_FAILURE; + } + + close(fd_in); + close(fd_out); + + return EXIT_SUCCESS; +} diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 3d9cc10f0f..90b21737b9 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -28,14 +28,14 @@ * * TWEAK this if you have different kind of NAND chip. */ -uint32_t nand_writesize = 2048; -uint32_t nand_oobsize = 64; -uint32_t nand_erasesize = 128 * 1024; +static uint32_t nand_writesize = 2048; +static uint32_t nand_oobsize = 64; +static uint32_t nand_erasesize = 128 * 1024; /* * Sector on which the SigmaTel boot partition (0x53) starts. */ -uint32_t sd_sector = 2048; +static uint32_t sd_sector = 2048; /* * Each of the U-Boot bootstreams is at maximum 1MB big. @@ -379,7 +379,7 @@ static uint8_t *mx28_nand_fcb_block(struct mx28_nand_fcb *fcb) return block; } -static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, char *buf) +static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, uint8_t *buf) { uint32_t offset; uint8_t *fcbblock; @@ -393,13 +393,15 @@ static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, char *buf) for (i = 0; i < STRIDE_PAGES * STRIDE_COUNT; i += STRIDE_PAGES) { offset = i * nand_writesize; memcpy(buf + offset, fcbblock, nand_writesize + nand_oobsize); + /* Mark the NAND page is OK. */ + buf[offset + nand_writesize] = 0xff; } free(fcbblock); return ret; } -static int mx28_nand_write_dbbt(struct mx28_nand_dbbt *dbbt, char *buf) +static int mx28_nand_write_dbbt(struct mx28_nand_dbbt *dbbt, uint8_t *buf) { uint32_t offset; int i = STRIDE_PAGES * STRIDE_COUNT; @@ -413,7 +415,7 @@ static int mx28_nand_write_dbbt(struct mx28_nand_dbbt *dbbt, char *buf) } static int mx28_nand_write_firmware(struct mx28_nand_fcb *fcb, int infd, - char *buf) + uint8_t *buf) { int ret; off_t size; @@ -434,7 +436,7 @@ static int mx28_nand_write_firmware(struct mx28_nand_fcb *fcb, int infd, return 0; } -void usage(void) +static void usage(void) { printf( "Usage: mxsboot [ops] \n" @@ -462,7 +464,7 @@ static int mx28_create_nand_image(int infd, int outfd) struct mx28_nand_fcb *fcb; struct mx28_nand_dbbt *dbbt; int ret = -1; - char *buf; + uint8_t *buf; int size; ssize_t wr_size; @@ -575,7 +577,7 @@ err0: return ret; } -int parse_ops(int argc, char **argv) +static int parse_ops(int argc, char **argv) { int i; int tmp; diff --git a/tools/mxsimage.c b/tools/mxsimage.c new file mode 100644 index 0000000000..98fc64491c --- /dev/null +++ b/tools/mxsimage.c @@ -0,0 +1,2329 @@ +/* + * Freescale i.MX23/i.MX28 SB image generator + * + * Copyright (C) 2012-2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef CONFIG_MXS + +#include +#include +#include +#include +#include +#include + +#include + +#include "imagetool.h" +#include "mxsimage.h" +#include "pbl_crc32.h" +#include + + +/* + * DCD block + * |-Write to address command block + * | 0xf00 == 0xf33d + * | 0xba2 == 0xb33f + * |-ORR address with mask command block + * | 0xf00 |= 0x1337 + * |-Write to address command block + * | 0xba2 == 0xd00d + * : + */ +#define SB_HAB_DCD_WRITE 0xccUL +#define SB_HAB_DCD_CHECK 0xcfUL +#define SB_HAB_DCD_NOOP 0xc0UL +#define SB_HAB_DCD_MASK_BIT (1 << 3) +#define SB_HAB_DCD_SET_BIT (1 << 4) + +/* Addr.n = Value.n */ +#define SB_DCD_WRITE \ + (SB_HAB_DCD_WRITE << 24) +/* Addr.n &= ~Value.n */ +#define SB_DCD_ANDC \ + ((SB_HAB_DCD_WRITE << 24) | SB_HAB_DCD_SET_BIT) +/* Addr.n |= Value.n */ +#define SB_DCD_ORR \ + ((SB_HAB_DCD_WRITE << 24) | SB_HAB_DCD_SET_BIT | SB_HAB_DCD_MASK_BIT) +/* (Addr.n & Value.n) == 0 */ +#define SB_DCD_CHK_EQZ \ + (SB_HAB_DCD_CHECK << 24) +/* (Addr.n & Value.n) == Value.n */ +#define SB_DCD_CHK_EQ \ + ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_SET_BIT) +/* (Addr.n & Value.n) != Value.n */ +#define SB_DCD_CHK_NEQ \ + ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_MASK_BIT) +/* (Addr.n & Value.n) != 0 */ +#define SB_DCD_CHK_NEZ \ + ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_SET_BIT | SB_HAB_DCD_MASK_BIT) +/* NOP */ +#define SB_DCD_NOOP \ + (SB_HAB_DCD_NOOP << 24) + +struct sb_dcd_ctx { + struct sb_dcd_ctx *dcd; + + uint32_t id; + + /* The DCD block. */ + uint32_t *payload; + /* Size of the whole DCD block. */ + uint32_t size; + + /* Pointer to previous DCD command block. */ + uint32_t *prev_dcd_head; +}; + +/* + * IMAGE + * |-SECTION + * | |-CMD + * | |-CMD + * | `-CMD + * |-SECTION + * | |-CMD + * : : + */ +struct sb_cmd_list { + char *cmd; + size_t len; + unsigned int lineno; +}; + +struct sb_cmd_ctx { + uint32_t size; + + struct sb_cmd_ctx *cmd; + + uint8_t *data; + uint32_t length; + + struct sb_command payload; + struct sb_command c_payload; +}; + +struct sb_section_ctx { + uint32_t size; + + /* Section flags */ + unsigned int boot:1; + + struct sb_section_ctx *sect; + + struct sb_cmd_ctx *cmd_head; + struct sb_cmd_ctx *cmd_tail; + + struct sb_sections_header payload; +}; + +struct sb_image_ctx { + unsigned int in_section:1; + unsigned int in_dcd:1; + /* Image configuration */ + unsigned int display_progress:1; + unsigned int silent_dump:1; + char *input_filename; + char *output_filename; + char *cfg_filename; + uint8_t image_key[16]; + + /* Number of section in the image */ + unsigned int sect_count; + /* Bootable section */ + unsigned int sect_boot; + unsigned int sect_boot_found:1; + + struct sb_section_ctx *sect_head; + struct sb_section_ctx *sect_tail; + + struct sb_dcd_ctx *dcd_head; + struct sb_dcd_ctx *dcd_tail; + + EVP_CIPHER_CTX cipher_ctx; + EVP_MD_CTX md_ctx; + uint8_t digest[32]; + struct sb_key_dictionary_key sb_dict_key; + + struct sb_boot_image_header payload; +}; + +/* + * Instruction semantics: + * NOOP + * TAG [LAST] + * LOAD address file + * LOAD IVT address IVT_entry_point + * FILL address pattern length + * JUMP [HAB] address [r0_arg] + * CALL [HAB] address [r0_arg] + * MODE mode + * For i.MX23, mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH + * JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1 + * For i.MX28, mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH + * JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1 + */ + +/* + * AES libcrypto + */ +static int sb_aes_init(struct sb_image_ctx *ictx, uint8_t *iv, int enc) +{ + EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx; + int ret; + + /* If there is no init vector, init vector is all zeroes. */ + if (!iv) + iv = ictx->image_key; + + EVP_CIPHER_CTX_init(ctx); + ret = EVP_CipherInit(ctx, EVP_aes_128_cbc(), ictx->image_key, iv, enc); + if (ret == 1) + EVP_CIPHER_CTX_set_padding(ctx, 0); + return ret; +} + +static int sb_aes_crypt(struct sb_image_ctx *ictx, uint8_t *in_data, + uint8_t *out_data, int in_len) +{ + EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx; + int ret, outlen; + uint8_t *outbuf; + + outbuf = malloc(in_len); + if (!outbuf) + return -ENOMEM; + memset(outbuf, 0, sizeof(in_len)); + + ret = EVP_CipherUpdate(ctx, outbuf, &outlen, in_data, in_len); + if (!ret) { + ret = -EINVAL; + goto err; + } + + if (out_data) + memcpy(out_data, outbuf, outlen); + +err: + free(outbuf); + return ret; +} + +static int sb_aes_deinit(EVP_CIPHER_CTX *ctx) +{ + return EVP_CIPHER_CTX_cleanup(ctx); +} + +static int sb_aes_reinit(struct sb_image_ctx *ictx, int enc) +{ + int ret; + EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx; + struct sb_boot_image_header *sb_header = &ictx->payload; + uint8_t *iv = sb_header->iv; + + ret = sb_aes_deinit(ctx); + if (!ret) + return ret; + return sb_aes_init(ictx, iv, enc); +} + +/* + * Debug + */ +static void soprintf(struct sb_image_ctx *ictx, const char *fmt, ...) +{ + va_list ap; + + if (ictx->silent_dump) + return; + + va_start(ap, fmt); + vfprintf(stdout, fmt, ap); + va_end(ap); +} + +/* + * Code + */ +static time_t sb_get_timestamp(void) +{ + struct tm time_2000 = { + .tm_yday = 1, /* Jan. 1st */ + .tm_year = 100, /* 2000 */ + }; + time_t seconds_to_2000 = mktime(&time_2000); + time_t seconds_to_now = time(NULL); + + return seconds_to_now - seconds_to_2000; +} + +static int sb_get_time(time_t time, struct tm *tm) +{ + struct tm time_2000 = { + .tm_yday = 1, /* Jan. 1st */ + .tm_year = 0, /* 1900 */ + }; + const time_t seconds_to_2000 = mktime(&time_2000); + const time_t seconds_to_now = seconds_to_2000 + time; + struct tm *ret; + ret = gmtime_r(&seconds_to_now, tm); + return ret ? 0 : -EINVAL; +} + +static void sb_encrypt_sb_header(struct sb_image_ctx *ictx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + struct sb_boot_image_header *sb_header = &ictx->payload; + uint8_t *sb_header_ptr = (uint8_t *)sb_header; + + /* Encrypt the header, compute the digest. */ + sb_aes_crypt(ictx, sb_header_ptr, NULL, sizeof(*sb_header)); + EVP_DigestUpdate(md_ctx, sb_header_ptr, sizeof(*sb_header)); +} + +static void sb_encrypt_sb_sections_header(struct sb_image_ctx *ictx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + struct sb_section_ctx *sctx = ictx->sect_head; + struct sb_sections_header *shdr; + uint8_t *sb_sections_header_ptr; + const int size = sizeof(*shdr); + + while (sctx) { + shdr = &sctx->payload; + sb_sections_header_ptr = (uint8_t *)shdr; + + sb_aes_crypt(ictx, sb_sections_header_ptr, + ictx->sb_dict_key.cbc_mac, size); + EVP_DigestUpdate(md_ctx, sb_sections_header_ptr, size); + + sctx = sctx->sect; + }; +} + +static void sb_encrypt_key_dictionary_key(struct sb_image_ctx *ictx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + + sb_aes_crypt(ictx, ictx->image_key, ictx->sb_dict_key.key, + sizeof(ictx->sb_dict_key.key)); + EVP_DigestUpdate(md_ctx, &ictx->sb_dict_key, sizeof(ictx->sb_dict_key)); +} + +static void sb_decrypt_key_dictionary_key(struct sb_image_ctx *ictx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + + EVP_DigestUpdate(md_ctx, &ictx->sb_dict_key, sizeof(ictx->sb_dict_key)); + sb_aes_crypt(ictx, ictx->sb_dict_key.key, ictx->image_key, + sizeof(ictx->sb_dict_key.key)); +} + +static void sb_encrypt_tag(struct sb_image_ctx *ictx, + struct sb_cmd_ctx *cctx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + struct sb_command *cmd = &cctx->payload; + + sb_aes_crypt(ictx, (uint8_t *)cmd, + (uint8_t *)&cctx->c_payload, sizeof(*cmd)); + EVP_DigestUpdate(md_ctx, &cctx->c_payload, sizeof(*cmd)); +} + +static int sb_encrypt_image(struct sb_image_ctx *ictx) +{ + /* Start image-wide crypto. */ + EVP_MD_CTX_init(&ictx->md_ctx); + EVP_DigestInit(&ictx->md_ctx, EVP_sha1()); + + /* + * SB image header. + */ + sb_aes_init(ictx, NULL, 1); + sb_encrypt_sb_header(ictx); + + /* + * SB sections header. + */ + sb_encrypt_sb_sections_header(ictx); + + /* + * Key dictionary. + */ + sb_aes_reinit(ictx, 1); + sb_encrypt_key_dictionary_key(ictx); + + /* + * Section tags. + */ + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + struct sb_section_ctx *sctx = ictx->sect_head; + + while (sctx) { + cctx = sctx->cmd_head; + + sb_aes_reinit(ictx, 1); + + while (cctx) { + ccmd = &cctx->payload; + + sb_encrypt_tag(ictx, cctx); + + if (ccmd->header.tag == ROM_TAG_CMD) { + sb_aes_reinit(ictx, 1); + } else if (ccmd->header.tag == ROM_LOAD_CMD) { + sb_aes_crypt(ictx, cctx->data, cctx->data, + cctx->length); + EVP_DigestUpdate(&ictx->md_ctx, cctx->data, + cctx->length); + } + + cctx = cctx->cmd; + } + + sctx = sctx->sect; + }; + + /* + * Dump the SHA1 of the whole image. + */ + sb_aes_reinit(ictx, 1); + + EVP_DigestFinal(&ictx->md_ctx, ictx->digest, NULL); + sb_aes_crypt(ictx, ictx->digest, ictx->digest, sizeof(ictx->digest)); + + /* Stop the encryption session. */ + sb_aes_deinit(&ictx->cipher_ctx); + + return 0; +} + +static int sb_load_file(struct sb_cmd_ctx *cctx, char *filename) +{ + long real_size, roundup_size; + uint8_t *data; + long ret; + unsigned long size; + FILE *fp; + + if (!filename) { + fprintf(stderr, "ERR: Missing filename!\n"); + return -EINVAL; + } + + fp = fopen(filename, "r"); + if (!fp) + goto err_open; + + ret = fseek(fp, 0, SEEK_END); + if (ret < 0) + goto err_file; + + real_size = ftell(fp); + if (real_size < 0) + goto err_file; + + ret = fseek(fp, 0, SEEK_SET); + if (ret < 0) + goto err_file; + + roundup_size = roundup(real_size, SB_BLOCK_SIZE); + data = calloc(1, roundup_size); + if (!data) + goto err_file; + + size = fread(data, 1, real_size, fp); + if (size != (unsigned long)real_size) + goto err_alloc; + + cctx->data = data; + cctx->length = roundup_size; + + fclose(fp); + return 0; + +err_alloc: + free(data); +err_file: + fclose(fp); +err_open: + fprintf(stderr, "ERR: Failed to load file \"%s\"\n", filename); + return -EINVAL; +} + +static uint8_t sb_command_checksum(struct sb_command *inst) +{ + uint8_t *inst_ptr = (uint8_t *)inst; + uint8_t csum = 0; + unsigned int i; + + for (i = 0; i < sizeof(struct sb_command); i++) + csum += inst_ptr[i]; + + return csum; +} + +static int sb_token_to_long(char *tok, uint32_t *rid) +{ + char *endptr; + unsigned long id; + + if (tok[0] != '0' || tok[1] != 'x') { + fprintf(stderr, "ERR: Invalid hexadecimal number!\n"); + return -EINVAL; + } + + tok += 2; + + errno = 0; + id = strtoul(tok, &endptr, 16); + if ((errno == ERANGE && id == ULONG_MAX) || (errno != 0 && id == 0)) { + fprintf(stderr, "ERR: Value can't be decoded!\n"); + return -EINVAL; + } + + /* Check for 32-bit overflow. */ + if (id > 0xffffffff) { + fprintf(stderr, "ERR: Value too big!\n"); + return -EINVAL; + } + + if (endptr == tok) { + fprintf(stderr, "ERR: Deformed value!\n"); + return -EINVAL; + } + + *rid = (uint32_t)id; + return 0; +} + +static int sb_grow_dcd(struct sb_dcd_ctx *dctx, unsigned int inc_size) +{ + uint32_t *tmp; + + if (!inc_size) + return 0; + + dctx->size += inc_size; + tmp = realloc(dctx->payload, dctx->size); + if (!tmp) + return -ENOMEM; + + dctx->payload = tmp; + + /* Assemble and update the HAB DCD header. */ + dctx->payload[0] = htonl((SB_HAB_DCD_TAG << 24) | + (dctx->size << 8) | + SB_HAB_VERSION); + + return 0; +} + +static int sb_build_dcd(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) +{ + struct sb_dcd_ctx *dctx; + + char *tok; + uint32_t id; + int ret; + + dctx = calloc(1, sizeof(*dctx)); + if (!dctx) + return -ENOMEM; + + ret = sb_grow_dcd(dctx, 4); + if (ret) + goto err_dcd; + + /* Read DCD block number. */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: DCD block without number!\n", + cmd->lineno); + ret = -EINVAL; + goto err_dcd; + } + + /* Parse the DCD block number. */ + ret = sb_token_to_long(tok, &id); + if (ret) { + fprintf(stderr, "#%i ERR: Malformed DCD block number!\n", + cmd->lineno); + goto err_dcd; + } + + dctx->id = id; + + /* + * The DCD block is now constructed. Append it to the list. + * WARNING: The DCD size is still not computed and will be + * updated while parsing it's commands. + */ + if (!ictx->dcd_head) { + ictx->dcd_head = dctx; + ictx->dcd_tail = dctx; + } else { + ictx->dcd_tail->dcd = dctx; + ictx->dcd_tail = dctx; + } + + return 0; + +err_dcd: + free(dctx->payload); + free(dctx); + return ret; +} + +static int sb_build_dcd_block(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd, + uint32_t type) +{ + char *tok; + uint32_t address, value, length; + int ret; + + struct sb_dcd_ctx *dctx = ictx->dcd_tail; + uint32_t *dcd; + + if (dctx->prev_dcd_head && (type != SB_DCD_NOOP) && + ((dctx->prev_dcd_head[0] & 0xff0000ff) == type)) { + /* Same instruction as before, just append it. */ + ret = sb_grow_dcd(dctx, 8); + if (ret) + return ret; + } else if (type == SB_DCD_NOOP) { + ret = sb_grow_dcd(dctx, 4); + if (ret) + return ret; + + /* Update DCD command block pointer. */ + dctx->prev_dcd_head = dctx->payload + + dctx->size / sizeof(*dctx->payload) - 1; + + /* NOOP has only 4 bytes and no payload. */ + goto noop; + } else { + /* + * Either a different instruction block started now + * or this is the first instruction block. + */ + ret = sb_grow_dcd(dctx, 12); + if (ret) + return ret; + + /* Update DCD command block pointer. */ + dctx->prev_dcd_head = dctx->payload + + dctx->size / sizeof(*dctx->payload) - 3; + } + + dcd = dctx->payload + dctx->size / sizeof(*dctx->payload) - 2; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing DCD address!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read DCD destination address. */ + ret = sb_token_to_long(tok, &address); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect DCD address!\n", + cmd->lineno); + goto err; + } + + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing DCD value!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read DCD operation value. */ + ret = sb_token_to_long(tok, &value); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect DCD value!\n", + cmd->lineno); + goto err; + } + + /* Fill in the new DCD entry. */ + dcd[0] = htonl(address); + dcd[1] = htonl(value); + +noop: + /* Update the DCD command block. */ + length = dctx->size - + ((dctx->prev_dcd_head - dctx->payload) * + sizeof(*dctx->payload)); + dctx->prev_dcd_head[0] = htonl(type | (length << 8)); + +err: + return ret; +} + +static int sb_build_section(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx; + struct sb_sections_header *shdr; + char *tok; + uint32_t bootable = 0; + uint32_t id; + int ret; + + sctx = calloc(1, sizeof(*sctx)); + if (!sctx) + return -ENOMEM; + + /* Read section number. */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Section without number!\n", + cmd->lineno); + ret = -EINVAL; + goto err_sect; + } + + /* Parse the section number. */ + ret = sb_token_to_long(tok, &id); + if (ret) { + fprintf(stderr, "#%i ERR: Malformed section number!\n", + cmd->lineno); + goto err_sect; + } + + /* Read section's BOOTABLE flag. */ + tok = strtok(NULL, " "); + if (tok && (strlen(tok) == 8) && !strncmp(tok, "BOOTABLE", 8)) + bootable = SB_SECTION_FLAG_BOOTABLE; + + sctx->boot = bootable; + + shdr = &sctx->payload; + shdr->section_number = id; + shdr->section_flags = bootable; + + /* + * The section is now constructed. Append it to the list. + * WARNING: The section size is still not computed and will + * be updated while parsing it's commands. + */ + ictx->sect_count++; + + /* Mark that this section is bootable one. */ + if (bootable) { + if (ictx->sect_boot_found) { + fprintf(stderr, + "#%i WARN: Multiple bootable section!\n", + cmd->lineno); + } else { + ictx->sect_boot = id; + ictx->sect_boot_found = 1; + } + } + + if (!ictx->sect_head) { + ictx->sect_head = sctx; + ictx->sect_tail = sctx; + } else { + ictx->sect_tail->sect = sctx; + ictx->sect_tail = sctx; + } + + return 0; + +err_sect: + free(sctx); + return ret; +} + +static int sb_build_command_nop(struct sb_image_ctx *ictx) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_NOP_CMD; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; +} + +static int sb_build_command_tag(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + /* Check for the LAST keyword. */ + tok = strtok(cmd->cmd, " "); + if (tok && !strcmp(tok, "LAST")) + ccmd->header.flags = ROM_TAG_CMD_FLAG_ROM_LAST_TAG; + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_TAG_CMD; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; +} + +static int sb_build_command_load(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + int ret, is_ivt = 0, is_dcd = 0; + uint32_t dest, dcd = 0; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing LOAD address or 'IVT'!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Check for "IVT" flag. */ + if (!strcmp(tok, "IVT")) + is_ivt = 1; + if (!strcmp(tok, "DCD")) + is_dcd = 1; + if (is_ivt || is_dcd) { + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing LOAD address!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + } + + /* Read load destination address. */ + ret = sb_token_to_long(tok, &dest); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect LOAD address!\n", + cmd->lineno); + goto err; + } + + /* Read filename or IVT entrypoint or DCD block ID. */ + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, + "#%i ERR: Missing LOAD filename or IVT ep or DCD block ID!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + if (is_ivt) { + /* Handle IVT. */ + struct sb_ivt_header *ivt; + uint32_t ivtep; + ret = sb_token_to_long(tok, &ivtep); + + if (ret) { + fprintf(stderr, + "#%i ERR: Incorrect IVT entry point!\n", + cmd->lineno); + goto err; + } + + ivt = calloc(1, sizeof(*ivt)); + if (!ivt) { + ret = -ENOMEM; + goto err; + } + + ivt->header = sb_hab_ivt_header(); + ivt->entry = ivtep; + ivt->self = dest; + + cctx->data = (uint8_t *)ivt; + cctx->length = sizeof(*ivt); + } else if (is_dcd) { + struct sb_dcd_ctx *dctx = ictx->dcd_head; + uint32_t dcdid; + uint8_t *payload; + uint32_t asize; + ret = sb_token_to_long(tok, &dcdid); + + if (ret) { + fprintf(stderr, + "#%i ERR: Incorrect DCD block ID!\n", + cmd->lineno); + goto err; + } + + while (dctx) { + if (dctx->id == dcdid) + break; + dctx = dctx->dcd; + } + + if (!dctx) { + fprintf(stderr, "#%i ERR: DCD block %08x not found!\n", + cmd->lineno, dcdid); + goto err; + } + + asize = roundup(dctx->size, SB_BLOCK_SIZE); + payload = calloc(1, asize); + if (!payload) { + ret = -ENOMEM; + goto err; + } + + memcpy(payload, dctx->payload, dctx->size); + + cctx->data = payload; + cctx->length = asize; + + /* Set the Load DCD flag. */ + dcd = ROM_LOAD_CMD_FLAG_DCD_LOAD; + } else { + /* Regular LOAD of a file. */ + ret = sb_load_file(cctx, tok); + if (ret) { + fprintf(stderr, "#%i ERR: Cannot load '%s'!\n", + cmd->lineno, tok); + goto err; + } + } + + if (cctx->length & (SB_BLOCK_SIZE - 1)) { + fprintf(stderr, "#%i ERR: Unaligned payload!\n", + cmd->lineno); + } + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_LOAD_CMD; + ccmd->header.flags = dcd; + + ccmd->load.address = dest; + ccmd->load.count = cctx->length; + ccmd->load.crc32 = pbl_crc32(0, + (const char *)cctx->data, + cctx->length); + + cctx->size = sizeof(*ccmd) + cctx->length; + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; + +err: + free(cctx); + return ret; +} + +static int sb_build_command_fill(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + uint32_t address, pattern, length; + int ret; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing FILL address!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read fill destination address. */ + ret = sb_token_to_long(tok, &address); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect FILL address!\n", + cmd->lineno); + goto err; + } + + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing FILL pattern!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read fill pattern address. */ + ret = sb_token_to_long(tok, &pattern); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect FILL pattern!\n", + cmd->lineno); + goto err; + } + + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing FILL length!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read fill pattern address. */ + ret = sb_token_to_long(tok, &length); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect FILL length!\n", + cmd->lineno); + goto err; + } + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_FILL_CMD; + + ccmd->fill.address = address; + ccmd->fill.count = length; + ccmd->fill.pattern = pattern; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; + +err: + free(cctx); + return ret; +} + +static int sb_build_command_jump_call(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd, + unsigned int is_call) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + uint32_t dest, arg = 0x0; + uint32_t hab = 0; + int ret; + const char *cmdname = is_call ? "CALL" : "JUMP"; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, + "#%i ERR: Missing %s address or 'HAB'!\n", + cmd->lineno, cmdname); + ret = -EINVAL; + goto err; + } + + /* Check for "HAB" flag. */ + if (!strcmp(tok, "HAB")) { + hab = is_call ? ROM_CALL_CMD_FLAG_HAB : ROM_JUMP_CMD_FLAG_HAB; + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing %s address!\n", + cmd->lineno, cmdname); + ret = -EINVAL; + goto err; + } + } + /* Read load destination address. */ + ret = sb_token_to_long(tok, &dest); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect %s address!\n", + cmd->lineno, cmdname); + goto err; + } + + tok = strtok(NULL, " "); + if (tok) { + ret = sb_token_to_long(tok, &arg); + if (ret) { + fprintf(stderr, + "#%i ERR: Incorrect %s argument!\n", + cmd->lineno, cmdname); + goto err; + } + } + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = is_call ? ROM_CALL_CMD : ROM_JUMP_CMD; + ccmd->header.flags = hab; + + ccmd->call.address = dest; + ccmd->call.argument = arg; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; + +err: + free(cctx); + return ret; +} + +static int sb_build_command_jump(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + return sb_build_command_jump_call(ictx, cmd, 0); +} + +static int sb_build_command_call(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + return sb_build_command_jump_call(ictx, cmd, 1); +} + +static int sb_build_command_mode(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + int ret; + unsigned int i; + uint32_t mode = 0xffffffff; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing MODE boot mode argument!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + for (i = 0; i < ARRAY_SIZE(modetable); i++) { + if (!strcmp(tok, modetable[i].name)) { + mode = modetable[i].mode; + break; + } + + if (!modetable[i].altname) + continue; + + if (!strcmp(tok, modetable[i].altname)) { + mode = modetable[i].mode; + break; + } + } + + if (mode == 0xffffffff) { + fprintf(stderr, "#%i ERR: Invalid MODE boot mode argument!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_MODE_CMD; + + ccmd->mode.mode = mode; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; + +err: + free(cctx); + return ret; +} + +static int sb_prefill_image_header(struct sb_image_ctx *ictx) +{ + struct sb_boot_image_header *hdr = &ictx->payload; + + /* Fill signatures */ + memcpy(hdr->signature1, "STMP", 4); + memcpy(hdr->signature2, "sgtl", 4); + + /* SB Image version 1.1 */ + hdr->major_version = SB_VERSION_MAJOR; + hdr->minor_version = SB_VERSION_MINOR; + + /* Boot image major version */ + hdr->product_version.major = htons(0x999); + hdr->product_version.minor = htons(0x999); + hdr->product_version.revision = htons(0x999); + /* Boot image major version */ + hdr->component_version.major = htons(0x999); + hdr->component_version.minor = htons(0x999); + hdr->component_version.revision = htons(0x999); + + /* Drive tag must be 0x0 for i.MX23 */ + hdr->drive_tag = 0; + + hdr->header_blocks = + sizeof(struct sb_boot_image_header) / SB_BLOCK_SIZE; + hdr->section_header_size = + sizeof(struct sb_sections_header) / SB_BLOCK_SIZE; + hdr->timestamp_us = sb_get_timestamp() * 1000000; + + hdr->flags = ictx->display_progress ? + SB_IMAGE_FLAG_DISPLAY_PROGRESS : 0; + + /* FIXME -- We support only default key */ + hdr->key_count = 1; + + return 0; +} + +static int sb_postfill_image_header(struct sb_image_ctx *ictx) +{ + struct sb_boot_image_header *hdr = &ictx->payload; + struct sb_section_ctx *sctx = ictx->sect_head; + uint32_t kd_size, sections_blocks; + EVP_MD_CTX md_ctx; + + /* The main SB header size in blocks. */ + hdr->image_blocks = hdr->header_blocks; + + /* Size of the key dictionary, which has single zero entry. */ + kd_size = hdr->key_count * sizeof(struct sb_key_dictionary_key); + hdr->image_blocks += kd_size / SB_BLOCK_SIZE; + + /* Now count the payloads. */ + hdr->section_count = ictx->sect_count; + while (sctx) { + hdr->image_blocks += sctx->size / SB_BLOCK_SIZE; + sctx = sctx->sect; + } + + if (!ictx->sect_boot_found) { + fprintf(stderr, "ERR: No bootable section selected!\n"); + return -EINVAL; + } + hdr->first_boot_section_id = ictx->sect_boot; + + /* The n * SB section size in blocks. */ + sections_blocks = hdr->section_count * hdr->section_header_size; + hdr->image_blocks += sections_blocks; + + /* Key dictionary offset. */ + hdr->key_dictionary_block = hdr->header_blocks + sections_blocks; + + /* Digest of the whole image. */ + hdr->image_blocks += 2; + + /* Pointer past the dictionary. */ + hdr->first_boot_tag_block = + hdr->key_dictionary_block + kd_size / SB_BLOCK_SIZE; + + /* Compute header digest. */ + EVP_MD_CTX_init(&md_ctx); + + EVP_DigestInit(&md_ctx, EVP_sha1()); + EVP_DigestUpdate(&md_ctx, hdr->signature1, + sizeof(struct sb_boot_image_header) - + sizeof(hdr->digest)); + EVP_DigestFinal(&md_ctx, hdr->digest, NULL); + + return 0; +} + +static int sb_fixup_sections_and_tags(struct sb_image_ctx *ictx) +{ + /* Fixup the placement of sections. */ + struct sb_boot_image_header *ihdr = &ictx->payload; + struct sb_section_ctx *sctx = ictx->sect_head; + struct sb_sections_header *shdr; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + uint32_t offset = ihdr->first_boot_tag_block; + + while (sctx) { + shdr = &sctx->payload; + + /* Fill in the section TAG offset. */ + shdr->section_offset = offset + 1; + offset += shdr->section_size; + + /* Section length is measured from the TAG block. */ + shdr->section_size--; + + /* Fixup the TAG command. */ + cctx = sctx->cmd_head; + while (cctx) { + ccmd = &cctx->payload; + if (ccmd->header.tag == ROM_TAG_CMD) { + ccmd->tag.section_number = shdr->section_number; + ccmd->tag.section_length = shdr->section_size; + ccmd->tag.section_flags = shdr->section_flags; + } + + /* Update the command checksum. */ + ccmd->header.checksum = sb_command_checksum(ccmd); + + cctx = cctx->cmd; + } + + sctx = sctx->sect; + } + + return 0; +} + +static int sb_parse_line(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) +{ + char *tok; + char *line = cmd->cmd; + char *rptr = NULL; + int ret; + + /* Analyze the identifier on this line first. */ + tok = strtok_r(line, " ", &rptr); + if (!tok || (strlen(tok) == 0)) { + fprintf(stderr, "#%i ERR: Invalid line!\n", cmd->lineno); + return -EINVAL; + } + + cmd->cmd = rptr; + + /* set DISPLAY_PROGRESS flag */ + if (!strcmp(tok, "DISPLAYPROGRESS")) { + ictx->display_progress = 1; + return 0; + } + + /* DCD */ + if (!strcmp(tok, "DCD")) { + ictx->in_section = 0; + ictx->in_dcd = 1; + sb_build_dcd(ictx, cmd); + return 0; + } + + /* Section */ + if (!strcmp(tok, "SECTION")) { + ictx->in_section = 1; + ictx->in_dcd = 0; + sb_build_section(ictx, cmd); + return 0; + } + + if (!ictx->in_section && !ictx->in_dcd) { + fprintf(stderr, "#%i ERR: Data outside of a section!\n", + cmd->lineno); + return -EINVAL; + } + + if (ictx->in_section) { + /* Section commands */ + if (!strcmp(tok, "NOP")) { + ret = sb_build_command_nop(ictx); + } else if (!strcmp(tok, "TAG")) { + ret = sb_build_command_tag(ictx, cmd); + } else if (!strcmp(tok, "LOAD")) { + ret = sb_build_command_load(ictx, cmd); + } else if (!strcmp(tok, "FILL")) { + ret = sb_build_command_fill(ictx, cmd); + } else if (!strcmp(tok, "JUMP")) { + ret = sb_build_command_jump(ictx, cmd); + } else if (!strcmp(tok, "CALL")) { + ret = sb_build_command_call(ictx, cmd); + } else if (!strcmp(tok, "MODE")) { + ret = sb_build_command_mode(ictx, cmd); + } else { + fprintf(stderr, + "#%i ERR: Unsupported instruction '%s'!\n", + cmd->lineno, tok); + return -ENOTSUP; + } + } else if (ictx->in_dcd) { + char *lptr; + uint32_t ilen = '1'; + + tok = strtok_r(tok, ".", &lptr); + if (!tok || (strlen(tok) == 0) || (lptr && strlen(lptr) != 1)) { + fprintf(stderr, "#%i ERR: Invalid line!\n", + cmd->lineno); + return -EINVAL; + } + + if (lptr && + (lptr[0] != '1' && lptr[0] != '2' && lptr[0] != '4')) { + fprintf(stderr, "#%i ERR: Invalid instruction width!\n", + cmd->lineno); + return -EINVAL; + } + + if (lptr) + ilen = lptr[0] - '1'; + + /* DCD commands */ + if (!strcmp(tok, "WRITE")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_WRITE | ilen); + } else if (!strcmp(tok, "ANDC")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_ANDC | ilen); + } else if (!strcmp(tok, "ORR")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_ORR | ilen); + } else if (!strcmp(tok, "EQZ")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_CHK_EQZ | ilen); + } else if (!strcmp(tok, "EQ")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_CHK_EQ | ilen); + } else if (!strcmp(tok, "NEQ")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_CHK_NEQ | ilen); + } else if (!strcmp(tok, "NEZ")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_CHK_NEZ | ilen); + } else if (!strcmp(tok, "NOOP")) { + ret = sb_build_dcd_block(ictx, cmd, SB_DCD_NOOP); + } else { + fprintf(stderr, + "#%i ERR: Unsupported instruction '%s'!\n", + cmd->lineno, tok); + return -ENOTSUP; + } + } else { + fprintf(stderr, "#%i ERR: Unsupported instruction '%s'!\n", + cmd->lineno, tok); + return -ENOTSUP; + } + + /* + * Here we have at least one section with one command, otherwise we + * would have failed already higher above. + * + * FIXME -- should the updating happen here ? + */ + if (ictx->in_section && !ret) { + ictx->sect_tail->size += ictx->sect_tail->cmd_tail->size; + ictx->sect_tail->payload.section_size = + ictx->sect_tail->size / SB_BLOCK_SIZE; + } + + return ret; +} + +static int sb_load_cmdfile(struct sb_image_ctx *ictx) +{ + struct sb_cmd_list cmd; + int lineno = 1; + FILE *fp; + char *line = NULL; + ssize_t rlen; + size_t len; + + fp = fopen(ictx->cfg_filename, "r"); + if (!fp) + goto err_file; + + while ((rlen = getline(&line, &len, fp)) > 0) { + memset(&cmd, 0, sizeof(cmd)); + + /* Strip the trailing newline. */ + line[rlen - 1] = '\0'; + + cmd.cmd = line; + cmd.len = rlen; + cmd.lineno = lineno++; + + sb_parse_line(ictx, &cmd); + } + + free(line); + + fclose(fp); + + return 0; + +err_file: + fclose(fp); + fprintf(stderr, "ERR: Failed to load file \"%s\"\n", + ictx->cfg_filename); + return -EINVAL; +} + +static int sb_build_tree_from_cfg(struct sb_image_ctx *ictx) +{ + int ret; + + ret = sb_load_cmdfile(ictx); + if (ret) + return ret; + + ret = sb_prefill_image_header(ictx); + if (ret) + return ret; + + ret = sb_postfill_image_header(ictx); + if (ret) + return ret; + + ret = sb_fixup_sections_and_tags(ictx); + if (ret) + return ret; + + return 0; +} + +static int sb_verify_image_header(struct sb_image_ctx *ictx, + FILE *fp, long fsize) +{ + /* Verify static fields in the image header. */ + struct sb_boot_image_header *hdr = &ictx->payload; + const char *stat[2] = { "[PASS]", "[FAIL]" }; + struct tm tm; + int sz, ret = 0; + unsigned char digest[20]; + EVP_MD_CTX md_ctx; + unsigned long size; + + /* Start image-wide crypto. */ + EVP_MD_CTX_init(&ictx->md_ctx); + EVP_DigestInit(&ictx->md_ctx, EVP_sha1()); + + soprintf(ictx, "---------- Verifying SB Image Header ----------\n"); + + size = fread(&ictx->payload, 1, sizeof(ictx->payload), fp); + if (size != sizeof(ictx->payload)) { + fprintf(stderr, "ERR: SB image header too short!\n"); + return -EINVAL; + } + + /* Compute header digest. */ + EVP_MD_CTX_init(&md_ctx); + EVP_DigestInit(&md_ctx, EVP_sha1()); + EVP_DigestUpdate(&md_ctx, hdr->signature1, + sizeof(struct sb_boot_image_header) - + sizeof(hdr->digest)); + EVP_DigestFinal(&md_ctx, digest, NULL); + + sb_aes_init(ictx, NULL, 1); + sb_encrypt_sb_header(ictx); + + if (memcmp(digest, hdr->digest, 20)) + ret = -EINVAL; + soprintf(ictx, "%s Image header checksum: %s\n", stat[!!ret], + ret ? "BAD" : "OK"); + if (ret) + return ret; + + if (memcmp(hdr->signature1, "STMP", 4) || + memcmp(hdr->signature2, "sgtl", 4)) + ret = -EINVAL; + soprintf(ictx, "%s Signatures: '%.4s' '%.4s'\n", + stat[!!ret], hdr->signature1, hdr->signature2); + if (ret) + return ret; + + if ((hdr->major_version != SB_VERSION_MAJOR) || + ((hdr->minor_version != 1) && (hdr->minor_version != 2))) + ret = -EINVAL; + soprintf(ictx, "%s Image version: v%i.%i\n", stat[!!ret], + hdr->major_version, hdr->minor_version); + if (ret) + return ret; + + ret = sb_get_time(hdr->timestamp_us / 1000000, &tm); + soprintf(ictx, + "%s Creation time: %02i:%02i:%02i %02i/%02i/%04i\n", + stat[!!ret], tm.tm_hour, tm.tm_min, tm.tm_sec, + tm.tm_mday, tm.tm_mon, tm.tm_year + 2000); + if (ret) + return ret; + + soprintf(ictx, "%s Product version: %x.%x.%x\n", stat[0], + ntohs(hdr->product_version.major), + ntohs(hdr->product_version.minor), + ntohs(hdr->product_version.revision)); + soprintf(ictx, "%s Component version: %x.%x.%x\n", stat[0], + ntohs(hdr->component_version.major), + ntohs(hdr->component_version.minor), + ntohs(hdr->component_version.revision)); + + if (hdr->flags & ~SB_IMAGE_FLAGS_MASK) + ret = -EINVAL; + soprintf(ictx, "%s Image flags: %s\n", stat[!!ret], + hdr->flags & SB_IMAGE_FLAG_DISPLAY_PROGRESS ? + "Display_progress" : ""); + if (ret) + return ret; + + if (hdr->drive_tag != 0) + ret = -EINVAL; + soprintf(ictx, "%s Drive tag: %i\n", stat[!!ret], + hdr->drive_tag); + if (ret) + return ret; + + sz = sizeof(struct sb_boot_image_header) / SB_BLOCK_SIZE; + if (hdr->header_blocks != sz) + ret = -EINVAL; + soprintf(ictx, "%s Image header size (blocks): %i\n", stat[!!ret], + hdr->header_blocks); + if (ret) + return ret; + + sz = sizeof(struct sb_sections_header) / SB_BLOCK_SIZE; + if (hdr->section_header_size != sz) + ret = -EINVAL; + soprintf(ictx, "%s Section header size (blocks): %i\n", stat[!!ret], + hdr->section_header_size); + if (ret) + return ret; + + soprintf(ictx, "%s Sections count: %i\n", stat[!!ret], + hdr->section_count); + soprintf(ictx, "%s First bootable section %i\n", stat[!!ret], + hdr->first_boot_section_id); + + if (hdr->image_blocks != fsize / SB_BLOCK_SIZE) + ret = -EINVAL; + soprintf(ictx, "%s Image size (blocks): %i\n", stat[!!ret], + hdr->image_blocks); + if (ret) + return ret; + + sz = hdr->header_blocks + hdr->section_header_size * hdr->section_count; + if (hdr->key_dictionary_block != sz) + ret = -EINVAL; + soprintf(ictx, "%s Key dict offset (blocks): %i\n", stat[!!ret], + hdr->key_dictionary_block); + if (ret) + return ret; + + if (hdr->key_count != 1) + ret = -EINVAL; + soprintf(ictx, "%s Number of encryption keys: %i\n", stat[!!ret], + hdr->key_count); + if (ret) + return ret; + + sz = hdr->header_blocks + hdr->section_header_size * hdr->section_count; + sz += hdr->key_count * + sizeof(struct sb_key_dictionary_key) / SB_BLOCK_SIZE; + if (hdr->first_boot_tag_block != (unsigned)sz) + ret = -EINVAL; + soprintf(ictx, "%s First TAG block (blocks): %i\n", stat[!!ret], + hdr->first_boot_tag_block); + if (ret) + return ret; + + return 0; +} + +static void sb_decrypt_tag(struct sb_image_ctx *ictx, + struct sb_cmd_ctx *cctx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + struct sb_command *cmd = &cctx->payload; + + sb_aes_crypt(ictx, (uint8_t *)&cctx->c_payload, + (uint8_t *)&cctx->payload, sizeof(*cmd)); + EVP_DigestUpdate(md_ctx, &cctx->c_payload, sizeof(*cmd)); +} + +static int sb_verify_command(struct sb_image_ctx *ictx, + struct sb_cmd_ctx *cctx, FILE *fp, + unsigned long *tsize) +{ + struct sb_command *ccmd = &cctx->payload; + unsigned long size, asize; + char *csum, *flag = ""; + int ret; + unsigned int i; + uint8_t csn, csc = ccmd->header.checksum; + ccmd->header.checksum = 0x5a; + csn = sb_command_checksum(ccmd); + ccmd->header.checksum = csc; + + if (csc == csn) + ret = 0; + else + ret = -EINVAL; + csum = ret ? "checksum BAD" : "checksum OK"; + + switch (ccmd->header.tag) { + case ROM_NOP_CMD: + soprintf(ictx, " NOOP # %s\n", csum); + return ret; + case ROM_TAG_CMD: + if (ccmd->header.flags & ROM_TAG_CMD_FLAG_ROM_LAST_TAG) + flag = "LAST"; + soprintf(ictx, " TAG %s # %s\n", flag, csum); + sb_aes_reinit(ictx, 0); + return ret; + case ROM_LOAD_CMD: + soprintf(ictx, " LOAD addr=0x%08x length=0x%08x # %s\n", + ccmd->load.address, ccmd->load.count, csum); + + cctx->length = ccmd->load.count; + asize = roundup(cctx->length, SB_BLOCK_SIZE); + cctx->data = malloc(asize); + if (!cctx->data) + return -ENOMEM; + + size = fread(cctx->data, 1, asize, fp); + if (size != asize) { + fprintf(stderr, + "ERR: SB LOAD command payload too short!\n"); + return -EINVAL; + } + + *tsize += size; + + EVP_DigestUpdate(&ictx->md_ctx, cctx->data, asize); + sb_aes_crypt(ictx, cctx->data, cctx->data, asize); + + if (ccmd->load.crc32 != pbl_crc32(0, + (const char *)cctx->data, + asize)) { + fprintf(stderr, + "ERR: SB LOAD command payload CRC32 invalid!\n"); + return -EINVAL; + } + return 0; + case ROM_FILL_CMD: + soprintf(ictx, + " FILL addr=0x%08x length=0x%08x pattern=0x%08x # %s\n", + ccmd->fill.address, ccmd->fill.count, + ccmd->fill.pattern, csum); + return 0; + case ROM_JUMP_CMD: + if (ccmd->header.flags & ROM_JUMP_CMD_FLAG_HAB) + flag = " HAB"; + soprintf(ictx, + " JUMP%s addr=0x%08x r0_arg=0x%08x # %s\n", + flag, ccmd->fill.address, ccmd->jump.argument, csum); + return 0; + case ROM_CALL_CMD: + if (ccmd->header.flags & ROM_CALL_CMD_FLAG_HAB) + flag = " HAB"; + soprintf(ictx, + " CALL%s addr=0x%08x r0_arg=0x%08x # %s\n", + flag, ccmd->fill.address, ccmd->jump.argument, csum); + return 0; + case ROM_MODE_CMD: + for (i = 0; i < ARRAY_SIZE(modetable); i++) { + if (ccmd->mode.mode == modetable[i].mode) { + soprintf(ictx, " MODE %s # %s\n", + modetable[i].name, csum); + break; + } + } + fprintf(stderr, " MODE !INVALID! # %s\n", csum); + return 0; + } + + return ret; +} + +static int sb_verify_commands(struct sb_image_ctx *ictx, + struct sb_section_ctx *sctx, FILE *fp) +{ + unsigned long size, tsize = 0; + struct sb_cmd_ctx *cctx; + int ret; + + sb_aes_reinit(ictx, 0); + + while (tsize < sctx->size) { + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + size = fread(&cctx->c_payload, 1, sizeof(cctx->c_payload), fp); + if (size != sizeof(cctx->c_payload)) { + fprintf(stderr, "ERR: SB command header too short!\n"); + return -EINVAL; + } + + tsize += size; + + sb_decrypt_tag(ictx, cctx); + + ret = sb_verify_command(ictx, cctx, fp, &tsize); + if (ret) + return -EINVAL; + } + + return 0; +} + +static int sb_verify_sections_cmds(struct sb_image_ctx *ictx, FILE *fp) +{ + struct sb_boot_image_header *hdr = &ictx->payload; + struct sb_sections_header *shdr; + unsigned int i; + int ret; + struct sb_section_ctx *sctx; + unsigned long size; + char *bootable = ""; + + soprintf(ictx, "----- Verifying SB Sections and Commands -----\n"); + + for (i = 0; i < hdr->section_count; i++) { + sctx = calloc(1, sizeof(*sctx)); + if (!sctx) + return -ENOMEM; + if (!ictx->sect_head) { + ictx->sect_head = sctx; + ictx->sect_tail = sctx; + } else { + ictx->sect_tail->sect = sctx; + ictx->sect_tail = sctx; + } + + size = fread(&sctx->payload, 1, sizeof(sctx->payload), fp); + if (size != sizeof(sctx->payload)) { + fprintf(stderr, "ERR: SB section header too short!\n"); + return -EINVAL; + } + } + + size = fread(&ictx->sb_dict_key, 1, sizeof(ictx->sb_dict_key), fp); + if (size != sizeof(ictx->sb_dict_key)) { + fprintf(stderr, "ERR: SB key dictionary too short!\n"); + return -EINVAL; + } + + sb_encrypt_sb_sections_header(ictx); + sb_aes_reinit(ictx, 0); + sb_decrypt_key_dictionary_key(ictx); + + sb_aes_reinit(ictx, 0); + + sctx = ictx->sect_head; + while (sctx) { + shdr = &sctx->payload; + + if (shdr->section_flags & SB_SECTION_FLAG_BOOTABLE) { + sctx->boot = 1; + bootable = " BOOTABLE"; + } + + sctx->size = (shdr->section_size * SB_BLOCK_SIZE) + + sizeof(struct sb_command); + soprintf(ictx, "SECTION 0x%x%s # size = %i bytes\n", + shdr->section_number, bootable, sctx->size); + + if (shdr->section_flags & ~SB_SECTION_FLAG_BOOTABLE) + fprintf(stderr, " WARN: Unknown section flag(s) %08x\n", + shdr->section_flags); + + if ((shdr->section_flags & SB_SECTION_FLAG_BOOTABLE) && + (hdr->first_boot_section_id != shdr->section_number)) { + fprintf(stderr, + " WARN: Bootable section does ID not match image header ID!\n"); + } + + ret = sb_verify_commands(ictx, sctx, fp); + if (ret) + return ret; + + sctx = sctx->sect; + } + + /* + * FIXME IDEA: + * check if the first TAG command is at sctx->section_offset + */ + return 0; +} + +static int sb_verify_image_end(struct sb_image_ctx *ictx, + FILE *fp, off_t filesz) +{ + uint8_t digest[32]; + unsigned long size; + off_t pos; + int ret; + + soprintf(ictx, "------------- Verifying image end -------------\n"); + + size = fread(digest, 1, sizeof(digest), fp); + if (size != sizeof(digest)) { + fprintf(stderr, "ERR: SB key dictionary too short!\n"); + return -EINVAL; + } + + pos = ftell(fp); + if (pos != filesz) { + fprintf(stderr, "ERR: Trailing data past the image!\n"); + return -EINVAL; + } + + /* Check the image digest. */ + EVP_DigestFinal(&ictx->md_ctx, ictx->digest, NULL); + + /* Decrypt the image digest from the input image. */ + sb_aes_reinit(ictx, 0); + sb_aes_crypt(ictx, digest, digest, sizeof(digest)); + + /* Check all of 20 bytes of the SHA1 hash. */ + ret = memcmp(digest, ictx->digest, 20) ? -EINVAL : 0; + + if (ret) + soprintf(ictx, "[FAIL] Full-image checksum: BAD\n"); + else + soprintf(ictx, "[PASS] Full-image checksum: OK\n"); + + return ret; +} + + +static int sb_build_tree_from_img(struct sb_image_ctx *ictx) +{ + long filesize; + int ret; + FILE *fp; + + if (!ictx->input_filename) { + fprintf(stderr, "ERR: Missing filename!\n"); + return -EINVAL; + } + + fp = fopen(ictx->input_filename, "r"); + if (!fp) + goto err_open; + + ret = fseek(fp, 0, SEEK_END); + if (ret < 0) + goto err_file; + + filesize = ftell(fp); + if (filesize < 0) + goto err_file; + + ret = fseek(fp, 0, SEEK_SET); + if (ret < 0) + goto err_file; + + if (filesize < (signed)sizeof(ictx->payload)) { + fprintf(stderr, "ERR: File too short!\n"); + goto err_file; + } + + if (filesize & (SB_BLOCK_SIZE - 1)) { + fprintf(stderr, "ERR: The file is not aligned!\n"); + goto err_file; + } + + /* Load and verify image header */ + ret = sb_verify_image_header(ictx, fp, filesize); + if (ret) + goto err_verify; + + /* Load and verify sections and commands */ + ret = sb_verify_sections_cmds(ictx, fp); + if (ret) + goto err_verify; + + ret = sb_verify_image_end(ictx, fp, filesize); + if (ret) + goto err_verify; + + ret = 0; + +err_verify: + soprintf(ictx, "-------------------- Result -------------------\n"); + soprintf(ictx, "Verification %s\n", ret ? "FAILED" : "PASSED"); + + /* Stop the encryption session. */ + sb_aes_deinit(&ictx->cipher_ctx); + + fclose(fp); + return ret; + +err_file: + fclose(fp); +err_open: + fprintf(stderr, "ERR: Failed to load file \"%s\"\n", + ictx->input_filename); + return -EINVAL; +} + +static void sb_free_image(struct sb_image_ctx *ictx) +{ + struct sb_section_ctx *sctx = ictx->sect_head, *s_head; + struct sb_dcd_ctx *dctx = ictx->dcd_head, *d_head; + struct sb_cmd_ctx *cctx, *c_head; + + while (sctx) { + s_head = sctx; + c_head = sctx->cmd_head; + + while (c_head) { + cctx = c_head; + c_head = c_head->cmd; + if (cctx->data) + free(cctx->data); + free(cctx); + } + + sctx = sctx->sect; + free(s_head); + } + + while (dctx) { + d_head = dctx; + dctx = dctx->dcd; + free(d_head->payload); + free(d_head); + } +} + +/* + * MXSSB-MKIMAGE glue code. + */ +static int mxsimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_MXSIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static void mxsimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ +} + +int mxsimage_check_params(struct image_tool_params *params) +{ + if (!params) + return -1; + if (!strlen(params->imagename)) { + fprintf(stderr, + "Error: %s - Configuration file not specified, it is needed for mxsimage generation\n", + params->cmdname); + return -1; + } + + /* + * Check parameters: + * XIP is not allowed and verify that incompatible + * parameters are not sent at the same time + * For example, if list is required a data image must not be provided + */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)) || + (params->xflag) || !(strlen(params->imagename)); +} + +static int mxsimage_verify_print_header(char *file, int silent) +{ + int ret; + struct sb_image_ctx ctx; + + memset(&ctx, 0, sizeof(ctx)); + + ctx.input_filename = file; + ctx.silent_dump = silent; + + ret = sb_build_tree_from_img(&ctx); + sb_free_image(&ctx); + + return ret; +} + +char *imagefile; +static int mxsimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct sb_boot_image_header *hdr; + + if (!ptr) + return -EINVAL; + + hdr = (struct sb_boot_image_header *)ptr; + + /* + * Check if the header contains the MXS image signatures, + * if so, do a full-image verification. + */ + if (memcmp(hdr->signature1, "STMP", 4) || + memcmp(hdr->signature2, "sgtl", 4)) + return -EINVAL; + + imagefile = params->imagefile; + + return mxsimage_verify_print_header(params->imagefile, 1); +} + +static void mxsimage_print_header(const void *hdr) +{ + if (imagefile) + mxsimage_verify_print_header(imagefile, 0); +} + +static int sb_build_image(struct sb_image_ctx *ictx, + struct image_type_params *tparams) +{ + struct sb_boot_image_header *sb_header = &ictx->payload; + struct sb_section_ctx *sctx; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + struct sb_key_dictionary_key *sb_dict_key = &ictx->sb_dict_key; + + uint8_t *image, *iptr; + + /* Calculate image size. */ + uint32_t size = sizeof(*sb_header) + + ictx->sect_count * sizeof(struct sb_sections_header) + + sizeof(*sb_dict_key) + sizeof(ictx->digest); + + sctx = ictx->sect_head; + while (sctx) { + size += sctx->size; + sctx = sctx->sect; + }; + + image = malloc(size); + if (!image) + return -ENOMEM; + iptr = image; + + memcpy(iptr, sb_header, sizeof(*sb_header)); + iptr += sizeof(*sb_header); + + sctx = ictx->sect_head; + while (sctx) { + memcpy(iptr, &sctx->payload, sizeof(struct sb_sections_header)); + iptr += sizeof(struct sb_sections_header); + sctx = sctx->sect; + }; + + memcpy(iptr, sb_dict_key, sizeof(*sb_dict_key)); + iptr += sizeof(*sb_dict_key); + + sctx = ictx->sect_head; + while (sctx) { + cctx = sctx->cmd_head; + while (cctx) { + ccmd = &cctx->payload; + + memcpy(iptr, &cctx->c_payload, sizeof(cctx->payload)); + iptr += sizeof(cctx->payload); + + if (ccmd->header.tag == ROM_LOAD_CMD) { + memcpy(iptr, cctx->data, cctx->length); + iptr += cctx->length; + } + + cctx = cctx->cmd; + } + + sctx = sctx->sect; + }; + + memcpy(iptr, ictx->digest, sizeof(ictx->digest)); + iptr += sizeof(ictx->digest); + + /* Configure the mkimage */ + tparams->hdr = image; + tparams->header_size = size; + + return 0; +} + +static int mxsimage_generate(struct image_tool_params *params, + struct image_type_params *tparams) +{ + int ret; + struct sb_image_ctx ctx; + + /* Do not copy the U-Boot image! */ + params->skipcpy = 1; + + memset(&ctx, 0, sizeof(ctx)); + + ctx.cfg_filename = params->imagename; + ctx.output_filename = params->imagefile; + + ret = sb_build_tree_from_cfg(&ctx); + if (ret) + goto fail; + + ret = sb_encrypt_image(&ctx); + if (!ret) + ret = sb_build_image(&ctx, tparams); + +fail: + sb_free_image(&ctx); + + return ret; +} + +/* + * mxsimage parameters + */ +U_BOOT_IMAGE_TYPE( + mxsimage, + "Freescale MXS Boot Image support", + 0, + NULL, + mxsimage_check_params, + mxsimage_verify_header, + mxsimage_print_header, + mxsimage_set_header, + NULL, + mxsimage_check_image_types, + NULL, + mxsimage_generate +); +#endif diff --git a/tools/mxsimage.h b/tools/mxsimage.h new file mode 100644 index 0000000000..88f72eb9d1 --- /dev/null +++ b/tools/mxsimage.h @@ -0,0 +1,231 @@ +/* + * Freescale i.MX28 SB image generator + * + * Copyright (C) 2012 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MXSSB_H__ +#define __MXSSB_H__ + +#include +#include + +#define SB_BLOCK_SIZE 16 + +#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +struct sb_boot_image_version { + uint16_t major; + uint16_t pad0; + uint16_t minor; + uint16_t pad1; + uint16_t revision; + uint16_t pad2; +}; + +struct sb_boot_image_header { + union { + /* SHA1 of the header. */ + uint8_t digest[20]; + struct { + /* CBC-MAC initialization vector. */ + uint8_t iv[16]; + uint8_t extra[4]; + }; + }; + /* 'STMP' */ + uint8_t signature1[4]; + /* Major version of the image format. */ + uint8_t major_version; + /* Minor version of the image format. */ + uint8_t minor_version; + /* Flags associated with the image. */ + uint16_t flags; + /* Size of the image in 16b blocks. */ + uint32_t image_blocks; + /* Offset of the first tag in 16b blocks. */ + uint32_t first_boot_tag_block; + /* ID of the section to boot from. */ + uint32_t first_boot_section_id; + /* Amount of crypto keys. */ + uint16_t key_count; + /* Offset to the key dictionary in 16b blocks. */ + uint16_t key_dictionary_block; + /* Size of this header in 16b blocks. */ + uint16_t header_blocks; + /* Amount of section headers. */ + uint16_t section_count; + /* Section header size in 16b blocks. */ + uint16_t section_header_size; + /* Padding to align timestamp to uint64_t. */ + uint8_t padding0[2]; + /* 'sgtl' (since v1.1) */ + uint8_t signature2[4]; + /* Image generation date, in microseconds since 1.1.2000 . */ + uint64_t timestamp_us; + /* Product version. */ + struct sb_boot_image_version + product_version; + /* Component version. */ + struct sb_boot_image_version + component_version; + /* Drive tag for the system drive. (since v1.1) */ + uint16_t drive_tag; + /* Padding. */ + uint8_t padding1[6]; +}; + +#define SB_VERSION_MAJOR 1 +#define SB_VERSION_MINOR 1 + +/* Enable to HTLLC boot report. */ +#define SB_IMAGE_FLAG_DISPLAY_PROGRESS (1 << 0) +#define SB_IMAGE_FLAGS_MASK SB_IMAGE_FLAG_DISPLAY_PROGRESS + +struct sb_key_dictionary_key { + /* The CBC-MAC of image and sections header. */ + uint8_t cbc_mac[SB_BLOCK_SIZE]; + /* The AES key encrypted by image key (zero). */ + uint8_t key[SB_BLOCK_SIZE]; +}; + +struct sb_ivt_header { + uint32_t header; + uint32_t entry; + uint32_t reserved1; + uint32_t dcd; + uint32_t boot_data; + uint32_t self; + uint32_t csf; + uint32_t reserved2; +}; + +#define SB_HAB_IVT_TAG 0xd1UL +#define SB_HAB_DCD_TAG 0xd2UL + +#define SB_HAB_VERSION 0x40UL + +/* + * The "size" field in the IVT header is not naturally aligned, + * use this macro to fill first 4 bytes of the IVT header without + * causing issues on some systems (esp. M68k, PPC, MIPS-BE, ARM-BE). + */ +static inline uint32_t sb_hab_ivt_header(void) +{ + uint32_t ret = 0; + ret |= SB_HAB_IVT_TAG << 24; + ret |= sizeof(struct sb_ivt_header) << 16; + ret |= SB_HAB_VERSION; + return htonl(ret); +} + +struct sb_sections_header { + /* Section number. */ + uint32_t section_number; + /* Offset of this sections first instruction after "TAG". */ + uint32_t section_offset; + /* Size of the section in 16b blocks. */ + uint32_t section_size; + /* Section flags. */ + uint32_t section_flags; +}; + +#define SB_SECTION_FLAG_BOOTABLE (1 << 0) + +struct sb_command { + struct { + uint8_t checksum; + uint8_t tag; + uint16_t flags; +#define ROM_TAG_CMD_FLAG_ROM_LAST_TAG 0x1 +#define ROM_LOAD_CMD_FLAG_DCD_LOAD 0x1 /* MX28 only */ +#define ROM_JUMP_CMD_FLAG_HAB 0x1 /* MX28 only */ +#define ROM_CALL_CMD_FLAG_HAB 0x1 /* MX28 only */ + } header; + + union { + struct { + uint32_t reserved[3]; + } nop; + struct { + uint32_t section_number; + uint32_t section_length; + uint32_t section_flags; + } tag; + struct { + uint32_t address; + uint32_t count; + uint32_t crc32; + } load; + struct { + uint32_t address; + uint32_t count; + uint32_t pattern; + } fill; + struct { + uint32_t address; + uint32_t reserved; + /* Passed in register r0 before JUMP */ + uint32_t argument; + } jump; + struct { + uint32_t address; + uint32_t reserved; + /* Passed in register r0 before CALL */ + uint32_t argument; + } call; + struct { + uint32_t reserved1; + uint32_t reserved2; + uint32_t mode; + } mode; + + }; +}; + +/* + * Most of the mode names are same or at least similar + * on i.MX23 and i.MX28, but some of the mode names + * differ. The "name" field represents the mode name + * on i.MX28 as seen in Table 12-2 of the datasheet. + * The "altname" field represents the differently named + * fields on i.MX23 as seen in Table 35-3 of the + * datasheet. + */ +static const struct { + const char *name; + const char *altname; + const uint8_t mode; +} modetable[] = { + { "USB", NULL, 0x00 }, + { "I2C", NULL, 0x01 }, + { "SPI2_FLASH", "SPI1_FLASH", 0x02 }, + { "SPI3_FLASH", "SPI2_FLASH", 0x03 }, + { "NAND_BCH", NULL, 0x04 }, + { "JTAG", NULL, 0x06 }, + { "SPI3_EEPROM", "SPI2_EEPROM", 0x08 }, + { "SD_SSP0", NULL, 0x09 }, + { "SD_SSP1", NULL, 0x0A } +}; + +enum sb_tag { + ROM_NOP_CMD = 0x00, + ROM_TAG_CMD = 0x01, + ROM_LOAD_CMD = 0x02, + ROM_FILL_CMD = 0x03, + ROM_JUMP_CMD = 0x04, + ROM_CALL_CMD = 0x05, + ROM_MODE_CMD = 0x06 +}; + +struct sb_source_entry { + uint8_t tag; + uint32_t address; + uint32_t flags; + char *filename; +}; + +#endif /* __MXSSB_H__ */ diff --git a/tools/omapimage.c b/tools/omapimage.c index d4d77d8858..7198b3330d 100644 --- a/tools/omapimage.c +++ b/tools/omapimage.c @@ -11,78 +11,42 @@ * Marvell Semiconductor * Written-by: Prafulla Wadaskar * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ -/* Required to obtain the getline prototype from stdio.h */ -#define _GNU_SOURCE - -#include "mkimage.h" +#include "imagetool.h" +#include #include +#include "gpheader.h" #include "omapimage.h" /* Header size is CH header rounded up to 512 bytes plus GP header */ #define OMAP_CH_HDR_SIZE 512 -#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header)) -#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE) +#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE + GPIMAGE_HDR_SIZE) static int do_swap32 = 0; -static uint32_t omapimage_swap32(uint32_t data) -{ - uint32_t result = 0; - result = (data & 0xFF000000) >> 24; - result |= (data & 0x00FF0000) >> 8; - result |= (data & 0x0000FF00) << 8; - result |= (data & 0x000000FF) << 24; - return result; -} - static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE]; static int omapimage_check_image_types(uint8_t type) { if (type == IH_TYPE_OMAPIMAGE) return EXIT_SUCCESS; - else { - return EXIT_FAILURE; - } -} - -/* - * Only the simplest image type is currently supported: - * TOC pointing to CHSETTINGS - * TOC terminator - * CHSETTINGS - * - * padding to OMAP_CH_HDR_SIZE bytes - * - * gp header - * size - * load_addr - */ -static int valid_gph_size(uint32_t size) -{ - return size; -} - -static int valid_gph_load_addr(uint32_t load_addr) -{ - return load_addr; + return EXIT_FAILURE; } static int omapimage_verify_header(unsigned char *ptr, int image_size, - struct mkimage_params *params) + struct image_tool_params *params) { struct ch_toc *toc = (struct ch_toc *)ptr; struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); - uint32_t offset, size, gph_size, gph_load_addr; + uint32_t offset, size; while (toc->section_offset != 0xffffffff && toc->section_size != 0xffffffff) { if (do_swap32) { - offset = omapimage_swap32(toc->section_offset); - size = omapimage_swap32(toc->section_size); + offset = cpu_to_be32(toc->section_offset); + size = cpu_to_be32(toc->section_size); } else { offset = toc->section_offset; size = toc->section_size; @@ -95,20 +59,7 @@ static int omapimage_verify_header(unsigned char *ptr, int image_size, toc++; } - if (do_swap32) { - gph_size = omapimage_swap32(gph->size); - gph_load_addr = omapimage_swap32(gph->load_addr); - } else { - gph_size = gph->size; - gph_load_addr = gph->load_addr; - } - - if (!valid_gph_size(gph_size)) - return -1; - if (!valid_gph_load_addr(gph_load_addr)) - return -1; - - return 0; + return gph_verify_header(gph, do_swap32); } static void omapimage_print_section(struct ch_settings *chs) @@ -138,13 +89,13 @@ static void omapimage_print_header(const void *ptr) const struct ch_toc *toc = (struct ch_toc *)ptr; const struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); - uint32_t offset, size, gph_size, gph_load_addr; + uint32_t offset, size; while (toc->section_offset != 0xffffffff && toc->section_size != 0xffffffff) { if (do_swap32) { - offset = omapimage_swap32(toc->section_offset); - size = omapimage_swap32(toc->section_size); + offset = cpu_to_be32(toc->section_offset); + size = cpu_to_be32(toc->section_size); } else { offset = toc->section_offset; size = toc->section_size; @@ -163,26 +114,7 @@ static void omapimage_print_header(const void *ptr) toc++; } - if (do_swap32) { - gph_size = omapimage_swap32(gph->size); - gph_load_addr = omapimage_swap32(gph->load_addr); - } else { - gph_size = gph->size; - gph_load_addr = gph->load_addr; - } - - if (!valid_gph_size(gph_size)) { - fprintf(stderr, "Error: invalid image size %x\n", gph_size); - exit(EXIT_FAILURE); - } - - if (!valid_gph_load_addr(gph_load_addr)) { - fprintf(stderr, "Error: invalid image load address %x\n", - gph_load_addr); - exit(EXIT_FAILURE); - } - - printf("GP Header: Size %x LoadAddr %x\n", gph_size, gph_load_addr); + gph_print_header(gph, do_swap32); } static int toc_offset(void *hdr, void *member) @@ -191,7 +123,7 @@ static int toc_offset(void *hdr, void *member) } static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, - struct mkimage_params *params) + struct image_tool_params *params) { struct ch_toc *toc = (struct ch_toc *)ptr; struct ch_settings *chs = (struct ch_settings *) @@ -211,8 +143,8 @@ static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, toc++; memset(toc, 0xff, sizeof(*toc)); - gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE; - gph->load_addr = params->addr; + gph_set_header(gph, sbuf->st_size - OMAP_FILE_HDR_SIZE, + params->addr, 0); if (strncmp(params->imagename, "byteswap", 8) == 0) { do_swap32 = 1; @@ -220,35 +152,27 @@ static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, uint32_t *data = (uint32_t *)ptr; while (swapped <= (sbuf->st_size / sizeof(uint32_t))) { - *data = omapimage_swap32(*data); + *data = cpu_to_be32(*data); swapped++; data++; } } } -int omapimage_check_params(struct mkimage_params *params) -{ - return (params->dflag && (params->fflag || params->lflag)) || - (params->fflag && (params->dflag || params->lflag)) || - (params->lflag && (params->dflag || params->fflag)); -} - /* * omapimage parameters */ -static struct image_type_params omapimage_params = { - .name = "TI OMAP CH/GP Boot Image support", - .header_size = OMAP_FILE_HDR_SIZE, - .hdr = (void *)&omapimage_header, - .check_image_type = omapimage_check_image_types, - .verify_header = omapimage_verify_header, - .print_header = omapimage_print_header, - .set_header = omapimage_set_header, - .check_params = omapimage_check_params, -}; - -void init_omap_image_type(void) -{ - mkimage_register(&omapimage_params); -} +U_BOOT_IMAGE_TYPE( + omapimage, + "TI OMAP CH/GP Boot Image support", + OMAP_FILE_HDR_SIZE, + (void *)&omapimage_header, + gpimage_check_params, + omapimage_verify_header, + omapimage_print_header, + omapimage_set_header, + NULL, + omapimage_check_image_types, + NULL, + NULL +); diff --git a/tools/omapimage.h b/tools/omapimage.h index 058013498b..8744ae7a2d 100644 --- a/tools/omapimage.h +++ b/tools/omapimage.h @@ -4,7 +4,7 @@ * Author John Rigby * Based on TI's signGP.c * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _OMAPIMAGE_H_ @@ -25,10 +25,5 @@ struct ch_settings { uint32_t flags; }; -struct gp_header { - uint32_t size; - uint32_t load_addr; -}; - #define KEY_CHSETTINGS 0xC0C0C0C1 #endif /* _OMAPIMAGE_H_ */ diff --git a/tools/patman/README b/tools/patman/README index e6d3070621..7d039e82bc 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -27,8 +27,8 @@ Series-to: fred.blogs@napier.co.nz in one of your commits, the series will be sent there. -In Linux this will also call get_maintainer.pl on each of your -patches automatically. +In Linux and U-Boot this will also call get_maintainer.pl on each of your +patches automatically (unless you use -m to disable this). How to use this tool @@ -52,12 +52,15 @@ will get a consistent result each time. How to configure it =================== -For most cases of using patman for U-Boot development, patman will -locate and use the file 'doc/git-mailrc' in your U-Boot directory. -This contains most of the aliases you will need. +For most cases of using patman for U-Boot development, patman can use the +file 'doc/git-mailrc' in your U-Boot directory to supply the email aliases +you need. To make this work, tell git where to find the file by typing +this once: -For Linux the 'scripts/get_maintainer.pl' handles figuring out where -to send patches pretty well. + git config sendemail.aliasesfile doc/git-mailrc + +For both Linux and U-Boot the 'scripts/get_maintainer.pl' handles figuring +out where to send patches pretty well. During the first run patman creates a config file for you by taking the default user name and email address from the global .gitconfig file. @@ -180,10 +183,19 @@ END together and put after the cover letter. Can appear multiple times. +Commit-notes: +blah blah +blah blah +more blah blah +END + Similar, but for a single commit (patch). These notes will appear + immediately below the --- cut in the patch file. + Signed-off-by: Their Name A sign-off is added automatically to your patches (this is probably a bug). If you put this tag in your patches, it will override the default signoff that patman automatically adds. + Multiple duplicate signoffs will be removed. Tested-by: Their Name Reviewed-by: Their Name @@ -209,8 +221,10 @@ Series-changes: n to update the log there and then, knowing that the script will do the rest. - Cc: Their Name - This copies a single patch to another email address. +Patch-cc: Their Name + This copies a single patch to another email address. Note that the + Cc: used by git send-email is ignored by patman, but will be + interpreted by git send-email if you use it. Series-process-log: sort, uniq This tells patman to sort and/or uniq the change logs. It is @@ -227,7 +241,7 @@ TEST=... Change-Id: Review URL: Reviewed-on: - +Commit-xxxx: (except Commit-notes) Exercise for the reader: Try adding some tags to one of your current patch series and see how the patches turn out. @@ -238,8 +252,9 @@ Where Patches Are Sent Once the patches are created, patman sends them using git send-email. The whole series is sent to the recipients in Series-to: and Series-cc. -You can Cc individual patches to other people with the Cc: tag. Tags in the -subject are also picked up to Cc patches. For example, a commit like this: +You can Cc individual patches to other people with the Patch-cc: tag. Tags +in the subject are also picked up to Cc patches. For example, a commit like +this: >>>> commit 10212537b85ff9b6e09c82045127522c0f0db981 @@ -250,16 +265,16 @@ Date: Mon Nov 7 23:18:44 2011 -0500 This should make sending out e-mails to the right people easier. - Cc: sandbox, mikef, ag - Cc: afleming + Patch-cc: sandbox, mikef, ag + Patch-cc: afleming <<<< will create a patch which is copied to x86, arm, sandbox, mikef, ag and afleming. -If you have a cover letter it will get sent to the union of the CC lists of -all of the other patches. If you want to sent it to additional people you -can add a tag: +If you have a cover letter it will get sent to the union of the Patch-cc +lists of all of the other patches. If you want to sent it to additional +people you can add a tag: Cover-letter-cc: diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py index 0d4e935244..34a3bd22b0 100644 --- a/tools/patman/checkpatch.py +++ b/tools/patman/checkpatch.py @@ -34,9 +34,8 @@ def FindCheckPatch(): return fname path = os.path.dirname(path) - print >> sys.stderr, ('Cannot find checkpatch.pl - please put it in your ' + - '~/bin directory or use --no-check') - sys.exit(1) + sys.exit('Cannot find checkpatch.pl - please put it in your ' + + '~/bin directory or use --no-check') def CheckPatch(fname, verbose=False): """Run checkpatch.pl on a file. diff --git a/tools/patman/command.py b/tools/patman/command.py index 449d3d0e03..d586f11158 100644 --- a/tools/patman/command.py +++ b/tools/patman/command.py @@ -20,9 +20,25 @@ class CommandResult: def __init__(self): self.stdout = None self.stderr = None + self.combined = None self.return_code = None self.exception = None + def __init__(self, stdout='', stderr='', combined='', return_code=0, + exception=None): + self.stdout = stdout + self.stderr = stderr + self.combined = combined + self.return_code = return_code + self.exception = exception + + +# This permits interception of RunPipe for test purposes. If it is set to +# a function, then that function is called with the pipe list being +# executed. Otherwise, it is assumed to be a CommandResult object, and is +# returned as the result for every RunPipe() call. +# When this value is None, commands are executed as normal. +test_result = None def RunPipe(pipe_list, infile=None, outfile=None, capture=False, capture_stderr=False, oneline=False, @@ -44,10 +60,16 @@ def RunPipe(pipe_list, infile=None, outfile=None, Returns: CommandResult object """ + if test_result: + if hasattr(test_result, '__call__'): + return test_result(pipe_list=pipe_list) + return test_result result = CommandResult() last_pipe = None pipeline = list(pipe_list) user_pipestr = '|'.join([' '.join(pipe) for pipe in pipe_list]) + kwargs['stdout'] = None + kwargs['stderr'] = None while pipeline: cmd = pipeline.pop(0) if last_pipe is not None: diff --git a/tools/patman/commit.py b/tools/patman/commit.py index 900cfb3a5a..3e0adb8f7e 100644 --- a/tools/patman/commit.py +++ b/tools/patman/commit.py @@ -21,6 +21,7 @@ class Commit: changes: Dict containing a list of changes (single line strings). The dict is indexed by change version (an integer) cc_list: List of people to aliases/emails to cc on this commit + notes: List of lines in the commit (not series) notes """ def __init__(self, hash): self.hash = hash @@ -28,6 +29,8 @@ class Commit: self.tags = [] self.changes = {} self.cc_list = [] + self.signoff_set = set() + self.notes = [] def AddChange(self, version, info): """Add a new change line to the change list for a version. @@ -70,3 +73,16 @@ class Commit: cc_list: List of aliases or email addresses """ self.cc_list += cc_list + + def CheckDuplicateSignoff(self, signoff): + """Check a list of signoffs we have send for this patch + + Args: + signoff: Signoff line + Returns: + True if this signoff is new, False if we have already seen it. + """ + if signoff in self.signoff_set: + return False + self.signoff_set.add(signoff) + return True diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 5dcbaa3bd7..c593070d67 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -11,8 +11,40 @@ import subprocess import sys import terminal +import checkpatch import settings +# True to use --no-decorate - we check this in Setup() +use_no_decorate = True + +def LogCmd(commit_range, git_dir=None, oneline=False, reverse=False, + count=None): + """Create a command to perform a 'git log' + + Args: + commit_range: Range expression to use for log, None for none + git_dir: Path to git repositiory (None to use default) + oneline: True to use --oneline, else False + reverse: True to reverse the log (--reverse) + count: Number of commits to list, or None for no limit + Return: + List containing command and arguments to run + """ + cmd = ['git'] + if git_dir: + cmd += ['--git-dir', git_dir] + cmd += ['--no-pager', 'log', '--no-color'] + if oneline: + cmd.append('--oneline') + if use_no_decorate: + cmd.append('--no-decorate') + if reverse: + cmd.append('--reverse') + if count is not None: + cmd.append('-n%d' % count) + if commit_range: + cmd.append(commit_range) + return cmd def CountCommitsToBranch(): """Returns number of commits between HEAD and the tracking branch. @@ -23,13 +55,58 @@ def CountCommitsToBranch(): Return: Number of patches that exist on top of the branch """ - pipe = [['git', 'log', '--no-color', '--oneline', '--no-decorate', - '@{upstream}..'], + pipe = [LogCmd('@{upstream}..', oneline=True), ['wc', '-l']] stdout = command.RunPipe(pipe, capture=True, oneline=True).stdout patch_count = int(stdout) return patch_count +def NameRevision(commit_hash): + """Gets the revision name for a commit + + Args: + commit_hash: Commit hash to look up + + Return: + Name of revision, if any, else None + """ + pipe = ['git', 'name-rev', commit_hash] + stdout = command.RunPipe([pipe], capture=True, oneline=True).stdout + + # We expect a commit, a space, then a revision name + name = stdout.split(' ')[1].strip() + return name + +def GuessUpstream(git_dir, branch): + """Tries to guess the upstream for a branch + + This lists out top commits on a branch and tries to find a suitable + upstream. It does this by looking for the first commit where + 'git name-rev' returns a plain branch name, with no ! or ^ modifiers. + + Args: + git_dir: Git directory containing repo + branch: Name of branch + + Returns: + Tuple: + Name of upstream branch (e.g. 'upstream/master') or None if none + Warning/error message, or None if none + """ + pipe = [LogCmd(branch, git_dir=git_dir, oneline=True, count=100)] + result = command.RunPipe(pipe, capture=True, capture_stderr=True, + raise_on_error=False) + if result.return_code: + return None, "Branch '%s' not found" % branch + for line in result.stdout.splitlines()[1:]: + commit_hash = line.split(' ')[0] + name = NameRevision(commit_hash) + if '~' not in name and '^' not in name: + if name.startswith('remotes/'): + name = name[8:] + return name, "Guessing upstream as '%s'" % name + return None, "Cannot find a suitable upstream for branch '%s'" % branch + def GetUpstream(git_dir, branch): """Returns the name of the upstream for a branch @@ -38,7 +115,9 @@ def GetUpstream(git_dir, branch): branch: Name of branch Returns: - Name of upstream branch (e.g. 'upstream/master') or None if none + Tuple: + Name of upstream branch (e.g. 'upstream/master') or None if none + Warning/error message, or None if none """ try: remote = command.OutputOneLine('git', '--git-dir', git_dir, 'config', @@ -46,13 +125,14 @@ def GetUpstream(git_dir, branch): merge = command.OutputOneLine('git', '--git-dir', git_dir, 'config', 'branch.%s.merge' % branch) except: - return None + upstream, msg = GuessUpstream(git_dir, branch) + return upstream, msg if remote == '.': return merge elif remote and merge: leaf = merge.split('/')[-1] - return '%s/%s' % (remote, leaf) + return '%s/%s' % (remote, leaf), None else: raise ValueError, ("Cannot determine upstream branch for branch " "'%s' remote='%s', merge='%s'" % (branch, remote, merge)) @@ -68,10 +148,29 @@ def GetRangeInBranch(git_dir, branch, include_upstream=False): Expression in the form 'upstream..branch' which can be used to access the commits. If the branch does not exist, returns None. """ - upstream = GetUpstream(git_dir, branch) + upstream, msg = GetUpstream(git_dir, branch) if not upstream: - return None - return '%s%s..%s' % (upstream, '~' if include_upstream else '', branch) + return None, msg + rstr = '%s%s..%s' % (upstream, '~' if include_upstream else '', branch) + return rstr, msg + +def CountCommitsInRange(git_dir, range_expr): + """Returns the number of commits in the given range. + + Args: + git_dir: Directory containing git repo + range_expr: Range to check + Return: + Number of patches that exist in the supplied rangem or None if none + were found + """ + pipe = [LogCmd(range_expr, git_dir=git_dir, oneline=True)] + result = command.RunPipe(pipe, capture=True, capture_stderr=True, + raise_on_error=False) + if result.return_code: + return None, "Range '%s' not found or is invalid" % range_expr + patch_count = len(result.stdout.splitlines()) + return patch_count, None def CountCommitsInBranch(git_dir, branch, include_upstream=False): """Returns the number of commits in the given branch. @@ -83,15 +182,10 @@ def CountCommitsInBranch(git_dir, branch, include_upstream=False): Number of patches that exist on top of the branch, or None if the branch does not exist. """ - range_expr = GetRangeInBranch(git_dir, branch, include_upstream) + range_expr, msg = GetRangeInBranch(git_dir, branch, include_upstream) if not range_expr: - return None - pipe = [['git', '--git-dir', git_dir, 'log', '--oneline', '--no-decorate', - range_expr], - ['wc', '-l']] - result = command.RunPipe(pipe, capture=True, oneline=True) - patch_count = int(result.stdout) - return patch_count + return None, msg + return CountCommitsInRange(git_dir, range_expr) def CountCommits(commit_range): """Returns the number of commits in the given range. @@ -101,7 +195,7 @@ def CountCommits(commit_range): Return: Number of patches that exist on top of the branch """ - pipe = [['git', 'log', '--oneline', '--no-decorate', commit_range], + pipe = [LogCmd(commit_range, oneline=True), ['wc', '-l']] stdout = command.RunPipe(pipe, capture=True, oneline=True).stdout patch_count = int(stdout) @@ -122,7 +216,8 @@ def Checkout(commit_hash, git_dir=None, work_tree=None, force=False): if force: pipe.append('-f') pipe.append(commit_hash) - result = command.RunPipe([pipe], capture=True, raise_on_error=False) + result = command.RunPipe([pipe], capture=True, raise_on_error=False, + capture_stderr=True) if result.return_code != 0: raise OSError, 'git checkout (%s): %s' % (pipe, result.stderr) @@ -133,7 +228,8 @@ def Clone(git_dir, output_dir): commit_hash: Commit hash to check out """ pipe = ['git', 'clone', git_dir, '.'] - result = command.RunPipe([pipe], capture=True, cwd=output_dir) + result = command.RunPipe([pipe], capture=True, cwd=output_dir, + capture_stderr=True) if result.return_code != 0: raise OSError, 'git clone: %s' % result.stderr @@ -149,7 +245,7 @@ def Fetch(git_dir=None, work_tree=None): if work_tree: pipe.extend(['--work-tree', work_tree]) pipe.append('fetch') - result = command.RunPipe([pipe], capture=True) + result = command.RunPipe([pipe], capture=True, capture_stderr=True) if result.return_code != 0: raise OSError, 'git fetch: %s' % result.stderr @@ -185,89 +281,6 @@ def CreatePatches(start, count, series): else: return None, files -def ApplyPatch(verbose, fname): - """Apply a patch with git am to test it - - TODO: Convert these to use command, with stderr option - - Args: - fname: filename of patch file to apply - """ - cmd = ['git', 'am', fname] - pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE, - stderr=subprocess.PIPE) - stdout, stderr = pipe.communicate() - re_error = re.compile('^error: patch failed: (.+):(\d+)') - for line in stderr.splitlines(): - if verbose: - print line - match = re_error.match(line) - if match: - print GetWarningMsg('warning', match.group(1), int(match.group(2)), - 'Patch failed') - return pipe.returncode == 0, stdout - -def ApplyPatches(verbose, args, start_point): - """Apply the patches with git am to make sure all is well - - Args: - verbose: Print out 'git am' output verbatim - args: List of patch files to apply - start_point: Number of commits back from HEAD to start applying. - Normally this is len(args), but it can be larger if a start - offset was given. - """ - error_count = 0 - col = terminal.Color() - - # Figure out our current position - cmd = ['git', 'name-rev', 'HEAD', '--name-only'] - pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE) - stdout, stderr = pipe.communicate() - if pipe.returncode: - str = 'Could not find current commit name' - print col.Color(col.RED, str) - print stdout - return False - old_head = stdout.splitlines()[0] - - # Checkout the required start point - cmd = ['git', 'checkout', 'HEAD~%d' % start_point] - pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE, - stderr=subprocess.PIPE) - stdout, stderr = pipe.communicate() - if pipe.returncode: - str = 'Could not move to commit before patch series' - print col.Color(col.RED, str) - print stdout, stderr - return False - - # Apply all the patches - for fname in args: - ok, stdout = ApplyPatch(verbose, fname) - if not ok: - print col.Color(col.RED, 'git am returned errors for %s: will ' - 'skip this patch' % fname) - if verbose: - print stdout - error_count += 1 - cmd = ['git', 'am', '--skip'] - pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE) - stdout, stderr = pipe.communicate() - if pipe.returncode != 0: - print col.Color(col.RED, 'Unable to skip patch! Aborting...') - print stdout - break - - # Return to our previous position - cmd = ['git', 'checkout', old_head] - pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE) - stdout, stderr = pipe.communicate() - if pipe.returncode: - print col.Color(col.RED, 'Could not move back to head commit') - print stdout, stderr - return error_count == 0 - def BuildEmailList(in_list, tag=None, alias=None, raise_on_error=True): """Build a list of email addresses based on an input list. @@ -371,10 +384,16 @@ def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, """ to = BuildEmailList(series.get('to'), '--to', alias, raise_on_error) if not to: - print ("No recipient, please add something like this to a commit\n" - "Series-to: Fred Bloggs ") - return - cc = BuildEmailList(series.get('cc'), '--cc', alias, raise_on_error) + git_config_to = command.Output('git', 'config', 'sendemail.to') + if not git_config_to: + print ("No recipient.\n" + "Please add something like this to a commit\n" + "Series-to: Fred Bloggs \n" + "Or do something like this\n" + "git config sendemail.to u-boot@lists.denx.de") + return + cc = BuildEmailList(list(set(series.get('cc')) - set(series.get('to'))), + '--cc', alias, raise_on_error) if self_only: to = BuildEmailList([os.getenv('USER')], '--to', alias, raise_on_error) cc = [] @@ -438,13 +457,13 @@ def LookupEmail(lookup_name, alias=None, raise_on_error=True, level=0): ... OSError: Recursive email alias at 'other' >>> LookupEmail('odd', alias, raise_on_error=False) - \033[1;31mAlias 'odd' not found\033[0m + Alias 'odd' not found [] >>> # In this case the loop part will effectively be ignored. >>> LookupEmail('loop', alias, raise_on_error=False) - \033[1;31mRecursive email alias at 'other'\033[0m - \033[1;31mRecursive email alias at 'john'\033[0m - \033[1;31mRecursive email alias at 'mary'\033[0m + Recursive email alias at 'other' + Recursive email alias at 'john' + Recursive email alias at 'mary' ['j.bloggs@napier.co.nz', 'm.poppins@cloud.net'] """ if not alias: @@ -529,9 +548,14 @@ def GetDefaultUserEmail(): def Setup(): """Set up git utils, by reading the alias files.""" # Check for a git alias file also + global use_no_decorate + alias_fname = GetAliasFile() if alias_fname: settings.ReadGitAliases(alias_fname) + cmd = LogCmd(None, count=0) + use_no_decorate = (command.RunPipe([cmd], raise_on_error=False) + .return_code == 0) def GetHead(): """Get the hash of the current HEAD diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index c2045230af..8c3a0ec9ee 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -21,7 +21,7 @@ re_remove = re.compile('^BUG=|^TEST=|^BRANCH=|^Change-Id:|^Review URL:' re_allowed_after_test = re.compile('^Signed-off-by:') # Signoffs -re_signoff = re.compile('^Signed-off-by:') +re_signoff = re.compile('^Signed-off-by: *(.*)') # The start of the cover letter re_cover = re.compile('^Cover-letter:') @@ -30,10 +30,13 @@ re_cover = re.compile('^Cover-letter:') re_cover_cc = re.compile('^Cover-letter-cc: *(.*)') # Patch series tag -re_series = re.compile('^Series-([a-z-]*): *(.*)') +re_series_tag = re.compile('^Series-([a-z-]*): *(.*)') + +# Commit series tag +re_commit_tag = re.compile('^Commit-([a-z-]*): *(.*)') # Commit tags that we want to collect and keep -re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Cc): (.*)') +re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Patch-cc): (.*)') # The start of a new commit in the git log re_commit = re.compile('^commit ([0-9a-f]*)$') @@ -69,7 +72,6 @@ class PatchStream: self.in_change = 0 # Non-zero if we are in a change list self.blank_count = 0 # Number of blank lines stored up self.state = STATE_MSG_HEADER # What state are we in? - self.tags = [] # Tags collected, like Tested-by... self.signoff = [] # Contents of signoff line self.commit = None # Current commit @@ -90,22 +92,26 @@ class PatchStream: if self.is_log: self.series.AddTag(self.commit, line, name, value) + def AddToCommit(self, line, name, value): + """Add a new Commit-xxx tag. + + When a Commit-xxx tag is detected, we come here to record it. + + Args: + line: Source line containing tag (useful for debug/error messages) + name: Tag name (part after 'Commit-') + value: Tag value (part after 'Commit-xxx: ') + """ + if name == 'notes': + self.in_section = 'commit-' + name + self.skip_blank = False + def CloseCommit(self): """Save the current commit into our commit list, and reset our state""" if self.commit and self.is_log: self.series.AddCommit(self.commit) self.commit = None - def FormatTags(self, tags): - out_list = [] - for tag in sorted(tags): - if tag.startswith('Cc:'): - tag_list = tag[4:].split(',') - out_list += gitutil.BuildEmailList(tag_list, 'Cc:') - else: - out_list.append(tag) - return out_list - def ProcessLine(self, line): """Process a single line of a patch file or commit log @@ -133,14 +139,18 @@ class PatchStream: # Initially we have no output. Prepare the input line string out = [] line = line.rstrip('\n') + + commit_match = re_commit.match(line) if self.is_log else None + if self.is_log: if line[:4] == ' ': line = line[4:] # Handle state transition and skipping blank lines - series_match = re_series.match(line) - commit_match = re_commit.match(line) if self.is_log else None + series_tag_match = re_series_tag.match(line) + commit_tag_match = re_commit_tag.match(line) cover_cc_match = re_cover_cc.match(line) + signoff_match = re_signoff.match(line) tag_match = None if self.state == STATE_PATCH_HEADER: tag_match = re_tag.match(line) @@ -165,6 +175,9 @@ class PatchStream: elif self.in_section == 'notes': if self.is_log: self.series.notes += self.section + elif self.in_section == 'commit-notes': + if self.is_log: + self.commit.notes += self.section else: self.warn.append("Unknown section '%s'" % self.in_section) self.in_section = None @@ -178,7 +191,7 @@ class PatchStream: self.commit.subject = line # Detect the tags we want to remove, and skip blank lines - elif re_remove.match(line): + elif re_remove.match(line) and not commit_tag_match: self.skip_blank = True # TEST= should be the last thing in the commit, so remove @@ -202,7 +215,7 @@ class PatchStream: if is_blank: # Blank line ends this change list self.in_change = 0 - elif line == '---' or re_signoff.match(line): + elif line == '---': self.in_change = 0 out = self.ProcessLine(line) else: @@ -211,9 +224,9 @@ class PatchStream: self.skip_blank = False # Detect Series-xxx tags - elif series_match: - name = series_match.group(1) - value = series_match.group(2) + elif series_tag_match: + name = series_tag_match.group(1) + value = series_tag_match.group(2) if name == 'changes': # value is the version number: e.g. 1, or 2 try: @@ -226,11 +239,18 @@ class PatchStream: self.AddToSeries(line, name, value) self.skip_blank = True + # Detect Commit-xxx tags + elif commit_tag_match: + name = commit_tag_match.group(1) + value = commit_tag_match.group(2) + if name == 'notes': + self.AddToCommit(line, name, value) + self.skip_blank = True + # Detect the start of a new commit elif commit_match: self.CloseCommit() - # TODO: We should store the whole hash, and just display a subset - self.commit = commit.Commit(commit_match.group(1)[:8]) + self.commit = commit.Commit(commit_match.group(1)) # Detect tags in the commit message elif tag_match: @@ -238,10 +258,16 @@ class PatchStream: if (tag_match.group(1) == 'Tested-by' and tag_match.group(2).find(os.getenv('USER') + '@') != -1): self.warn.append("Ignoring %s" % line) - elif tag_match.group(1) == 'Cc': + elif tag_match.group(1) == 'Patch-cc': self.commit.AddCc(tag_match.group(2).split(',')) else: - self.tags.append(line); + out = [line] + + # Suppress duplicate signoffs + elif signoff_match: + if (self.is_log or not self.commit or + self.commit.CheckDuplicateSignoff(signoff_match.group(1))): + out = [line] # Well that means this is an ordinary line else: @@ -275,8 +301,10 @@ class PatchStream: # Output the tags (signeoff first), then change list out = [] log = self.series.MakeChangeLog(self.commit) - out += self.FormatTags(self.tags) - out += [line] + log + out += [line] + if self.commit: + out += self.commit.notes + out += [''] + log elif self.found_test: if not re_allowed_after_test.match(line): self.lines_after_test += 1 @@ -328,7 +356,7 @@ class PatchStream: def GetMetaDataForList(commit_range, git_dir=None, count=None, - series = Series()): + series = None, allow_overwrite=False): """Reads out patch series metadata from the commits This does a 'git log' on the relevant commits and pulls out the tags we @@ -340,17 +368,16 @@ def GetMetaDataForList(commit_range, git_dir=None, count=None, count: Number of commits to list, or None for no limit series: Series object to add information into. By default a new series is started. + allow_overwrite: Allow tags to overwrite an existing tag Returns: A Series object containing information about the commits. """ - params = ['git', 'log', '--no-color', '--reverse', '--no-decorate', - commit_range] - if count is not None: - params[2:2] = ['-n%d' % count] - if git_dir: - params[1:1] = ['--git-dir', git_dir] - pipe = [params] - stdout = command.RunPipe(pipe, capture=True).stdout + if not series: + series = Series() + series.allow_overwrite = allow_overwrite + params = gitutil.LogCmd(commit_range,reverse=True, count=count, + git_dir=git_dir) + stdout = command.RunPipe([params], capture=True).stdout ps = PatchStream(series, is_log=True) for line in stdout.splitlines(): ps.ProcessLine(line) diff --git a/tools/patman/patman.py b/tools/patman/patman.py index c60aa5a1c4..6c6473e462 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -25,9 +25,6 @@ import test parser = OptionParser() -parser.add_option('-a', '--no-apply', action='store_false', - dest='apply_patches', default=True, - help="Don't test-apply patches with git am") parser.add_option('-H', '--full-help', action='store_true', dest='full_help', default=False, help='Display the README file') parser.add_option('-c', '--count', dest='count', type='int', @@ -35,6 +32,9 @@ parser.add_option('-c', '--count', dest='count', type='int', parser.add_option('-i', '--ignore-errors', action='store_true', dest='ignore_errors', default=False, help='Send patches email even if patch errors are found') +parser.add_option('-m', '--no-maintainers', action='store_false', + dest='add_maintainers', default=True, + help="Don't cc the file maintainers automatically") parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run', default=False, help="Do a dry run (create but don't email patches)") parser.add_option('-p', '--project', default=project.DetectProject(), @@ -58,7 +58,7 @@ parser.add_option('--no-check', action='store_false', dest='check_patch', parser.add_option('--no-tags', action='store_false', dest='process_tags', default=True, help="Don't process subject tags as aliaes") -parser.usage = """patman [options] +parser.usage += """ Create patches from commits in a branch, check them and email them as specified by tags you place in the commits. Use -n to do a dry run first.""" @@ -122,8 +122,7 @@ else: col = terminal.Color() if not options.count: str = 'No commits found to process - please use -c flag' - print col.Color(col.RED, str) - sys.exit(1) + sys.exit(col.Color(col.RED, str)) # Read the metadata from the commits if options.count: @@ -144,23 +143,25 @@ else: ok = checkpatch.CheckPatches(options.verbose, args) else: ok = True - if options.apply_patches: - if not gitutil.ApplyPatches(options.verbose, args, - options.count + options.start): - ok = False cc_file = series.MakeCcFile(options.process_tags, cover_fname, - not options.ignore_bad_tags) + not options.ignore_bad_tags, + options.add_maintainers) # Email the patches out (giving the user time to check / cancel) cmd = '' - if ok or options.ignore_errors: + its_a_go = ok or options.ignore_errors + if its_a_go: cmd = gitutil.EmailPatches(series, cover_fname, args, options.dry_run, not options.ignore_bad_tags, cc_file, in_reply_to=options.in_reply_to) + else: + print col.Color(col.RED, "Not sending emails due to errors/warnings") # For a dry run, just show our actions as a sanity check if options.dry_run: series.ShowActions(args, cmd, options.process_tags) + if not its_a_go: + print col.Color(col.RED, "Email would not be sent") os.remove(cc_file) diff --git a/tools/patman/series.py b/tools/patman/series.py index 88c0d877d4..60ebc766f7 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -94,6 +94,9 @@ class Series(dict): cmd: The git command we would have run process_tags: Process tags as if they were aliases """ + to_set = set(gitutil.BuildEmailList(self.to)); + cc_set = set(gitutil.BuildEmailList(self.cc)); + col = terminal.Color() print 'Dry run, so not doing much. But I would do this:' print @@ -106,24 +109,16 @@ class Series(dict): commit = self.commits[upto] print col.Color(col.GREEN, ' %s' % args[upto]) cc_list = list(self._generated_cc[commit.patch]) - - # Skip items in To list - if 'to' in self: - try: - map(cc_list.remove, gitutil.BuildEmailList(self.to)) - except ValueError: - pass - - for email in cc_list: + for email in set(cc_list) - to_set - cc_set: if email == None: email = col.Color(col.YELLOW, "" % tag) if email: print ' Cc: ',email print - for item in gitutil.BuildEmailList(self.get('to', '')): + for item in to_set: print 'To:\t ', item - for item in gitutil.BuildEmailList(self.cc): + for item in cc_set - to_set: print 'Cc:\t ', item print 'Version: ', self.get('version') print 'Prefix:\t ', self.get('prefix') @@ -131,7 +126,7 @@ class Series(dict): print 'Cover: %d lines' % len(self.cover) cover_cc = gitutil.BuildEmailList(self.get('cover_cc', '')) all_ccs = itertools.chain(cover_cc, *self._generated_cc.values()) - for email in set(all_ccs): + for email in set(all_ccs) - to_set - cc_set: print ' Cc: ',email if cmd: print 'Git command: %s' % cmd @@ -201,7 +196,8 @@ class Series(dict): str = 'Change log exists, but no version is set' print col.Color(col.RED, str) - def MakeCcFile(self, process_tags, cover_fname, raise_on_error): + def MakeCcFile(self, process_tags, cover_fname, raise_on_error, + add_maintainers): """Make a cc file for us to use for per-commit Cc automation Also stores in self._generated_cc to make ShowActions() faster. @@ -211,6 +207,7 @@ class Series(dict): cover_fname: If non-None the name of the cover letter. raise_on_error: True to raise an error when an alias fails to match, False to just print a message. + add_maintainers: Call the get_maintainers to CC maintainers Return: Filename of temp file created """ @@ -225,9 +222,10 @@ class Series(dict): raise_on_error=raise_on_error) list += gitutil.BuildEmailList(commit.cc_list, raise_on_error=raise_on_error) - list += get_maintainer.GetMaintainer(commit.patch) + if add_maintainers: + list += get_maintainer.GetMaintainer(commit.patch) all_ccs += list - print >>fd, commit.patch, ', '.join(list) + print >>fd, commit.patch, ', '.join(set(list)) self._generated_cc[commit.patch] = list if cover_fname: diff --git a/tools/patman/terminal.py b/tools/patman/terminal.py index 597d526861..e78a7c14f5 100644 --- a/tools/patman/terminal.py +++ b/tools/patman/terminal.py @@ -14,67 +14,145 @@ import sys # Selection of when we want our output to be colored COLOR_IF_TERMINAL, COLOR_ALWAYS, COLOR_NEVER = range(3) -class Color(object): - """Conditionally wraps text in ANSI color escape sequences.""" - BLACK, RED, GREEN, YELLOW, BLUE, MAGENTA, CYAN, WHITE = range(8) - BOLD = -1 - BRIGHT_START = '\033[1;%dm' - NORMAL_START = '\033[22;%dm' - BOLD_START = '\033[1m' - RESET = '\033[0m' +# Initially, we are set up to print to the terminal +print_test_mode = False +print_test_list = [] - def __init__(self, colored=COLOR_IF_TERMINAL): - """Create a new Color object, optionally disabling color output. +class PrintLine: + """A line of text output - Args: - enabled: True if color output should be enabled. If False then this - class will not add color codes at all. + Members: + text: Text line that was printed + newline: True to output a newline after the text + colour: Text colour to use """ - self._enabled = (colored == COLOR_ALWAYS or - (colored == COLOR_IF_TERMINAL and os.isatty(sys.stdout.fileno()))) + def __init__(self, text, newline, colour): + self.text = text + self.newline = newline + self.colour = colour - def Start(self, color, bright=True): - """Returns a start color code. + def __str__(self): + return 'newline=%s, colour=%s, text=%s' % (self.newline, self.colour, + self.text) - Args: - color: Color to use, .e.g BLACK, RED, etc. +def Print(text='', newline=True, colour=None): + """Handle a line of output to the terminal. - Returns: - If color is enabled, returns an ANSI sequence to start the given color, - otherwise returns empty string + In test mode this is recorded in a list. Otherwise it is output to the + terminal. + + Args: + text: Text to print + newline: True to add a new line at the end of the text + colour: Colour to use for the text """ - if self._enabled: - base = self.BRIGHT_START if bright else self.NORMAL_START - return base % (color + 30) - return '' + if print_test_mode: + print_test_list.append(PrintLine(text, newline, colour)) + else: + if colour: + col = Color() + text = col.Color(colour, text) + print text, + if newline: + print + +def SetPrintTestMode(): + """Go into test mode, where all printing is recorded""" + global print_test_mode + + print_test_mode = True - def Stop(self): - """Retruns a stop color code. +def GetPrintTestLines(): + """Get a list of all lines output through Print() Returns: - If color is enabled, returns an ANSI color reset sequence, otherwise - returns empty string + A list of PrintLine objects """ - if self._enabled: - return self.RESET - return '' + global print_test_list - def Color(self, color, text, bright=True): - """Returns text with conditionally added color escape sequences. + ret = print_test_list + print_test_list = [] + return ret - Keyword arguments: - color: Text color -- one of the color constants defined in this class. - text: The text to color. +def EchoPrintTestLines(): + """Print out the text lines collected""" + for line in print_test_list: + if line.colour: + col = Color() + print col.Color(line.colour, line.text), + else: + print line.text, + if line.newline: + print - Returns: - If self._enabled is False, returns the original text. If it's True, - returns text with color escape sequences based on the value of color. - """ - if not self._enabled: - return text - if color == self.BOLD: - start = self.BOLD_START - else: - base = self.BRIGHT_START if bright else self.NORMAL_START - start = base % (color + 30) - return start + text + self.RESET + +class Color(object): + """Conditionally wraps text in ANSI color escape sequences.""" + BLACK, RED, GREEN, YELLOW, BLUE, MAGENTA, CYAN, WHITE = range(8) + BOLD = -1 + BRIGHT_START = '\033[1;%dm' + NORMAL_START = '\033[22;%dm' + BOLD_START = '\033[1m' + RESET = '\033[0m' + + def __init__(self, colored=COLOR_IF_TERMINAL): + """Create a new Color object, optionally disabling color output. + + Args: + enabled: True if color output should be enabled. If False then this + class will not add color codes at all. + """ + try: + self._enabled = (colored == COLOR_ALWAYS or + (colored == COLOR_IF_TERMINAL and + os.isatty(sys.stdout.fileno()))) + except: + self._enabled = False + + def Start(self, color, bright=True): + """Returns a start color code. + + Args: + color: Color to use, .e.g BLACK, RED, etc. + + Returns: + If color is enabled, returns an ANSI sequence to start the given + color, otherwise returns empty string + """ + if self._enabled: + base = self.BRIGHT_START if bright else self.NORMAL_START + return base % (color + 30) + return '' + + def Stop(self): + """Retruns a stop color code. + + Returns: + If color is enabled, returns an ANSI color reset sequence, + otherwise returns empty string + """ + if self._enabled: + return self.RESET + return '' + + def Color(self, color, text, bright=True): + """Returns text with conditionally added color escape sequences. + + Keyword arguments: + color: Text color -- one of the color constants defined in this + class. + text: The text to color. + + Returns: + If self._enabled is False, returns the original text. If it's True, + returns text with color escape sequences based on the value of + color. + """ + if not self._enabled: + return text + if color == self.BOLD: + start = self.BOLD_START + else: + base = self.BRIGHT_START if bright else self.NORMAL_START + start = base % (color + 30) + return start + text + self.RESET diff --git a/tools/patman/test.py b/tools/patman/test.py index 8fcfe530dc..e8f7472785 100644 --- a/tools/patman/test.py +++ b/tools/patman/test.py @@ -55,6 +55,7 @@ This adds functions to enable/disable clocks and reset to on-chip peripherals. Signed-off-by: Simon Glass --- + arch/arm/cpu/armv7/tegra2/Makefile | 2 +- arch/arm/cpu/armv7/tegra2/ap20.c | 57 ++---- arch/arm/cpu/armv7/tegra2/clock.c | 163 +++++++++++++++++ @@ -200,7 +201,7 @@ index 0000000..2234c87 self.assertEqual(result.errors, 0) self.assertEqual(result.warnings, 0) self.assertEqual(result.checks, 0) - self.assertEqual(result.lines, 67) + self.assertEqual(result.lines, 56) os.remove(inf) def testNoSignoff(self): @@ -211,18 +212,18 @@ index 0000000..2234c87 self.assertEqual(result.errors, 1) self.assertEqual(result.warnings, 0) self.assertEqual(result.checks, 0) - self.assertEqual(result.lines, 67) + self.assertEqual(result.lines, 56) os.remove(inf) def testSpaces(self): inf = self.SetupData('spaces') result = checkpatch.CheckPatch(inf) self.assertEqual(result.ok, False) - self.assertEqual(len(result.problems), 1) + self.assertEqual(len(result.problems), 2) self.assertEqual(result.errors, 0) - self.assertEqual(result.warnings, 1) + self.assertEqual(result.warnings, 2) self.assertEqual(result.checks, 0) - self.assertEqual(result.lines, 67) + self.assertEqual(result.lines, 56) os.remove(inf) def testIndent(self): @@ -233,7 +234,7 @@ index 0000000..2234c87 self.assertEqual(result.errors, 0) self.assertEqual(result.warnings, 0) self.assertEqual(result.checks, 1) - self.assertEqual(result.lines, 67) + self.assertEqual(result.lines, 56) os.remove(inf) diff --git a/tools/pbl_crc32.c b/tools/pbl_crc32.c new file mode 100644 index 0000000000..6e6735acde --- /dev/null +++ b/tools/pbl_crc32.c @@ -0,0 +1,56 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Cleaned up and refactored by Charles Manning. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include "pblimage.h" + +static uint32_t crc_table[256]; +static int crc_table_valid; + +static void make_crc_table(void) +{ + uint32_t mask; + int i, j; + uint32_t poly; /* polynomial exclusive-or pattern */ + + if (crc_table_valid) + return; + + /* + * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 + * + x11 + x12 + x16 + x22 + x23 + x26 + x32. + */ + poly = 0x04c11db7; + + for (i = 0; i < 256; i++) { + mask = i << 24; + for (j = 0; j < 8; j++) { + if (mask & 0x80000000) + mask = (mask << 1) ^ poly; + else + mask <<= 1; + } + crc_table[i] = mask; + } + + crc_table_valid = 1; +} + +uint32_t pbl_crc32(uint32_t in_crc, const char *buf, uint32_t len) +{ + uint32_t crc32_val; + int i; + + make_crc_table(); + + crc32_val = ~in_crc; + + for (i = 0; i < len; i++) + crc32_val = (crc32_val << 8) ^ + crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)]; + + return crc32_val; +} diff --git a/tools/pbl_crc32.h b/tools/pbl_crc32.h new file mode 100644 index 0000000000..4ab55ee768 --- /dev/null +++ b/tools/pbl_crc32.h @@ -0,0 +1,13 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef PBLCRC32_H +#define PBLCRC32_H + +#include +uint32_t pbl_crc32(uint32_t in_crc, const char *buf, uint32_t len); + +#endif diff --git a/tools/pblimage.c b/tools/pblimage.c index 4542a9c10f..d74fde9a44 100644 --- a/tools/pblimage.c +++ b/tools/pblimage.c @@ -1,13 +1,16 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#define _GNU_SOURCE - -#include "mkimage.h" +#include "imagetool.h" #include #include "pblimage.h" +#include "pbl_crc32.h" + +#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#define PBL_ACS_CONT_CMD 0x81000000 +#define PBL_ADDR_24BIT_MASK 0x00ffffff /* * Initialize to an invalid value. @@ -23,6 +26,13 @@ static int pbl_size; static char *fname = "Unknown"; static int lineno = -1; static struct pbl_header pblimage_header; +static int uboot_size; +static int arch_flag; + +static uint32_t pbl_cmd_initaddr; +static uint32_t pbi_crc_cmd1; +static uint32_t pbi_crc_cmd2; +static uint32_t pbl_end_cmd[4]; static union { @@ -39,20 +49,6 @@ static union * start offset by subtracting the size of the u-boot image from the * top of the allowable 24-bit range. */ -static void init_next_pbl_cmd(FILE *fp_uboot) -{ - struct stat st; - int fd = fileno(fp_uboot); - - if (fstat(fd, &st) == -1) { - printf("Error: Could not determine u-boot image size. %s\n", - strerror(errno)); - exit(EXIT_FAILURE); - } - - next_pbl_cmd = 0x82000000 - st.st_size; -} - static void generate_pbl_cmd(void) { uint32_t val = next_pbl_cmd; @@ -67,11 +63,15 @@ static void generate_pbl_cmd(void) static void pbl_fget(size_t size, FILE *stream) { - unsigned char c; + unsigned char c = 0xff; int c_temp; - while (size && (c_temp = fgetc(stream)) != EOF) { - c = (unsigned char)c_temp; + while (size) { + c_temp = fgetc(stream); + if (c_temp != EOF) + c = (unsigned char)c_temp; + else if ((c_temp == EOF) && (arch_flag == IH_ARCH_ARM)) + c = 0xff; *pmem_buf++ = c; pbl_size++; size--; @@ -81,8 +81,8 @@ static void pbl_fget(size_t size, FILE *stream) /* load split u-boot with PBI command 81xxxxxx. */ static void load_uboot(FILE *fp_uboot) { - init_next_pbl_cmd(fp_uboot); - while (next_pbl_cmd < 0x82000000) { + next_pbl_cmd = pbl_cmd_initaddr - uboot_size; + while (next_pbl_cmd < pbl_cmd_initaddr) { generate_pbl_cmd(); pbl_fget(64, fp_uboot); } @@ -139,52 +139,6 @@ static void pbl_parser(char *name) fclose(fd); } -static uint32_t crc_table[256]; - -static void make_crc_table(void) -{ - uint32_t mask; - int i, j; - uint32_t poly; /* polynomial exclusive-or pattern */ - - /* - * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 - * + x11 + x12 + x16 + x22 + x23 + x26 + x32. - */ - poly = 0x04c11db7; - - for (i = 0; i < 256; i++) { - mask = i << 24; - for (j = 0; j < 8; j++) { - if (mask & 0x80000000) - mask = (mask << 1) ^ poly; - else - mask <<= 1; - } - crc_table[i] = mask; - } -} - -unsigned long pbl_crc32(unsigned long crc, const char *buf, uint32_t len) -{ - uint32_t crc32_val = 0xffffffff; - uint32_t xor = 0x0; - int i; - - make_crc_table(); - - for (i = 0; i < len; i++) - crc32_val = (crc32_val << 8) ^ - crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)]; - - crc32_val = crc32_val ^ xor; - if (crc32_val < 0) { - crc32_val += 0xffffffff; - crc32_val += 1; - } - return crc32_val; -} - static uint32_t reverse_byte(uint32_t val) { uint32_t temp; @@ -201,8 +155,6 @@ static uint32_t reverse_byte(uint32_t val) /* write end command and crc command to memory. */ static void add_end_cmd(void) { - uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000, - 0x091380c0, 0x00000000}; uint32_t crc32_pbl; int i; unsigned char *p = (unsigned char *)&pbl_end_cmd; @@ -219,8 +171,8 @@ static void add_end_cmd(void) /* Add PBI CRC command. */ *pmem_buf++ = 0x08; - *pmem_buf++ = 0x13; - *pmem_buf++ = 0x80; + *pmem_buf++ = pbi_crc_cmd1; + *pmem_buf++ = pbi_crc_cmd2; *pmem_buf++ = 0x40; pbl_size += 4; @@ -231,20 +183,9 @@ static void add_end_cmd(void) *pmem_buf++ = (crc32_pbl >> 8) & 0xff; *pmem_buf++ = (crc32_pbl) & 0xff; pbl_size += 4; - - if ((pbl_size % 16) != 0) { - for (i = 0; i < 8; i++) { - *pmem_buf++ = 0x0; - pbl_size++; - } - } - if ((pbl_size % 16 != 0)) { - printf("Error: Bad size of image file\n"); - exit(EXIT_FAILURE); - } } -void pbl_load_uboot(int ifd, struct mkimage_params *params) +void pbl_load_uboot(int ifd, struct image_tool_params *params) { FILE *fp_uboot; int size; @@ -283,7 +224,7 @@ static int pblimage_check_image_types(uint8_t type) } static int pblimage_verify_header(unsigned char *ptr, int image_size, - struct mkimage_params *params) + struct image_tool_params *params) { struct pbl_header *pbl_hdr = (struct pbl_header *) ptr; @@ -310,24 +251,74 @@ static void pblimage_print_header(const void *ptr) } static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd, - struct mkimage_params *params) + struct image_tool_params *params) { /*nothing need to do, pbl_load_uboot takes care of whole file. */ } -/* pblimage parameters */ -static struct image_type_params pblimage_params = { - .name = "Freescale PBL Boot Image support", - .header_size = sizeof(struct pbl_header), - .hdr = (void *)&pblimage_header, - .check_image_type = pblimage_check_image_types, - .verify_header = pblimage_verify_header, - .print_header = pblimage_print_header, - .set_header = pblimage_set_header, +int pblimage_check_params(struct image_tool_params *params) +{ + FILE *fp_uboot; + int fd; + struct stat st; + + if (!params) + return EXIT_FAILURE; + + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + fd = fileno(fp_uboot); + + if (fstat(fd, &st) == -1) { + printf("Error: Could not determine u-boot image size. %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + /* For the variable size, we need to pad it to 64 byte boundary */ + uboot_size = roundup(st.st_size, 64); + + if (params->arch == IH_ARCH_ARM) { + arch_flag = IH_ARCH_ARM; + pbi_crc_cmd1 = 0x61; + pbi_crc_cmd2 = 0; + pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK; + pbl_cmd_initaddr |= PBL_ACS_CONT_CMD; + pbl_cmd_initaddr |= uboot_size; + pbl_end_cmd[0] = 0x09610000; + pbl_end_cmd[1] = 0x00000000; + pbl_end_cmd[2] = 0x096100c0; + pbl_end_cmd[3] = 0x00000000; + } else if (params->arch == IH_ARCH_PPC) { + arch_flag = IH_ARCH_PPC; + pbi_crc_cmd1 = 0x13; + pbi_crc_cmd2 = 0x80; + pbl_cmd_initaddr = 0x82000000; + pbl_end_cmd[0] = 0x09138000; + pbl_end_cmd[1] = 0x00000000; + pbl_end_cmd[2] = 0x091380c0; + pbl_end_cmd[3] = 0x00000000; + } + + next_pbl_cmd = pbl_cmd_initaddr; + return 0; }; -void init_pbl_image_type(void) -{ - pbl_size = 0; - mkimage_register(&pblimage_params); -} +/* pblimage parameters */ +U_BOOT_IMAGE_TYPE( + pblimage, + "Freescale PBL Boot Image support", + sizeof(struct pbl_header), + (void *)&pblimage_header, + pblimage_check_params, + pblimage_verify_header, + pblimage_print_header, + pblimage_set_header, + NULL, + pblimage_check_image_types, + NULL, + NULL +); diff --git a/tools/pblimage.h b/tools/pblimage.h index a0f1fc53ab..12bece50a7 100644 --- a/tools/pblimage.h +++ b/tools/pblimage.h @@ -1,7 +1,7 @@ /* * Copyright 2012 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef PBLIMAGE_H diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c new file mode 100644 index 0000000000..670b9fd73a --- /dev/null +++ b/tools/relocate-rela.c @@ -0,0 +1,189 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + * + * 64-bit and little-endian target only until we need to support a different + * arch that needs this. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef R_AARCH64_RELATIVE +#define R_AARCH64_RELATIVE 1027 +#endif + +static const bool debug_en; + +static void debug(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + if (debug_en) + vprintf(fmt, args); +} + +static bool supported_rela(Elf64_Rela *rela) +{ + uint64_t mask = 0xffffffffULL; /* would be different on 32-bit */ + uint32_t type = rela->r_info & mask; + + switch (type) { +#ifdef R_AARCH64_RELATIVE + case R_AARCH64_RELATIVE: + return true; +#endif + default: + fprintf(stderr, "warning: unsupported relocation type %" + PRIu32 " at %" PRIx64 "\n", + type, rela->r_offset); + + return false; + } +} + +static inline uint64_t swap64(uint64_t val) +{ + return ((val >> 56) & 0x00000000000000ffULL) | + ((val >> 40) & 0x000000000000ff00ULL) | + ((val >> 24) & 0x0000000000ff0000ULL) | + ((val >> 8) & 0x00000000ff000000ULL) | + ((val << 8) & 0x000000ff00000000ULL) | + ((val << 24) & 0x0000ff0000000000ULL) | + ((val << 40) & 0x00ff000000000000ULL) | + ((val << 56) & 0xff00000000000000ULL); +} + +#if __BYTE_ORDER == __LITTLE_ENDIAN +static inline uint64_t be64(uint64_t val) +{ + return swap64(val); +} + +static inline uint64_t le64(uint64_t val) +{ + return val; +} +#else +static inline uint64_t le64(uint64_t val) +{ + return swap64(val); +} + +static inline uint64_t be64(uint64_t val) +{ + return val; +} +#endif + +static bool read_num(const char *str, uint64_t *num) +{ + char *endptr; + *num = strtoull(str, &endptr, 16); + return str[0] && !endptr[0]; +} + +int main(int argc, char **argv) +{ + FILE *f; + int i, num; + uint64_t rela_start, rela_end, text_base; + + if (argc != 5) { + fprintf(stderr, "Statically apply ELF rela relocations\n"); + fprintf(stderr, "Usage: %s " \ + " \n", argv[0]); + fprintf(stderr, "All numbers in hex.\n"); + return 1; + } + + f = fopen(argv[1], "r+b"); + if (!f) { + fprintf(stderr, "%s: Cannot open %s: %s\n", + argv[0], argv[1], strerror(errno)); + return 2; + } + + if (!read_num(argv[2], &text_base) || + !read_num(argv[3], &rela_start) || + !read_num(argv[4], &rela_end)) { + fprintf(stderr, "%s: bad number\n", argv[0]); + return 3; + } + + if (rela_start > rela_end || rela_start < text_base || + (rela_end - rela_start) % sizeof(Elf64_Rela)) { + fprintf(stderr, "%s: bad rela bounds\n", argv[0]); + return 3; + } + + rela_start -= text_base; + rela_end -= text_base; + + num = (rela_end - rela_start) / sizeof(Elf64_Rela); + + for (i = 0; i < num; i++) { + Elf64_Rela rela, swrela; + uint64_t pos = rela_start + sizeof(Elf64_Rela) * i; + uint64_t addr; + + if (fseek(f, pos, SEEK_SET) < 0) { + fprintf(stderr, "%s: %s: seek to %" PRIx64 + " failed: %s\n", + argv[0], argv[1], pos, strerror(errno)); + } + + if (fread(&rela, sizeof(rela), 1, f) != 1) { + fprintf(stderr, "%s: %s: read rela failed at %" + PRIx64 "\n", + argv[0], argv[1], pos); + return 4; + } + + swrela.r_offset = le64(rela.r_offset); + swrela.r_info = le64(rela.r_info); + swrela.r_addend = le64(rela.r_addend); + + if (!supported_rela(&swrela)) + continue; + + debug("Rela %" PRIx64 " %" PRIu64 " %" PRIx64 "\n", + swrela.r_offset, swrela.r_info, swrela.r_addend); + + if (swrela.r_offset < text_base) { + fprintf(stderr, "%s: %s: bad rela at %" PRIx64 "\n", + argv[0], argv[1], pos); + return 4; + } + + addr = swrela.r_offset - text_base; + + if (fseek(f, addr, SEEK_SET) < 0) { + fprintf(stderr, "%s: %s: seek to %" + PRIx64 " failed: %s\n", + argv[0], argv[1], addr, strerror(errno)); + } + + if (fwrite(&rela.r_addend, sizeof(rela.r_addend), 1, f) != 1) { + fprintf(stderr, "%s: %s: write failed at %" PRIx64 "\n", + argv[0], argv[1], addr); + return 4; + } + } + + if (fclose(f) < 0) { + fprintf(stderr, "%s: %s: close failed: %s\n", + argv[0], argv[1], strerror(errno)); + return 4; + } + + return 0; +} diff --git a/tools/scripts/README b/tools/scripts/README deleted file mode 100644 index dbc4425afd..0000000000 --- a/tools/scripts/README +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -This directory contains scripts that help to perform certain actions -that need to be done frequently when working with U-Boot. - -They are meant as EXAMPLE code, so it is very likely that you will -have to modify them before use. - - -Short description: -================== - -dot.kermrc: - - Example for "~/.kermrc" Kermit init file for use with U-Boot - - by Wolfgang Denk, 24 Jun 2001 - -flash_param: - - "kermit" script to automatically initialize the environment - variables on your target. This is most useful during - development when your environment variables are stored in an - embedded flash sector which is erased whenever you install a - new U-Boot image. - - by Swen Anderson, 10 May 2001 - -send_cmd: - - send_cmd U_BOOT_COMMAND - - "kermit" script to send a U-Boot command and print the - results. When used from a shell with history (like the bash) - this indirectly adds kind of history to U-Boot ;-) - - by Swen Anderson, 10 May 2001 - -send_image: - - send_image FILE_NAME OFFSET - - "kermit" script to automatically download a file to the - target using the "loadb" command (kermit binary protocol) - - by Swen Anderson, 10 May 2001 diff --git a/tools/scripts/make-asm-offsets b/tools/scripts/make-asm-offsets deleted file mode 100755 index 4c33756d66..0000000000 --- a/tools/scripts/make-asm-offsets +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/sh - -# Adapted from Linux kernel's "Kbuild": -# commit 1cdf25d704f7951d02a04064c97db547d6021872 -# Author: Christoph Lameter - -mkdir -p $(dirname $2) - -# Default sed regexp - multiline due to syntax constraints -SED_CMD="/^->/{s:->#\(.*\):/* \1 */:; \ - s:^->\([^ ]*\) [\$#]*\([-0-9]*\) \(.*\):#define \1 (\2) /* \3 */:; \ - s:^->\([^ ]*\) [\$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ - s:->::; p;}" - -(set -e - echo "#ifndef __ASM_OFFSETS_H__" - echo "#define __ASM_OFFSETS_H__" - echo "/*" - echo " * DO NOT MODIFY." - echo " *" - echo " * This file was generated by $(basename $0)" - echo " *" - echo " */" - echo "" - sed -ne "${SED_CMD}" $1 - echo "" - echo "#endif" ) > $2 diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c new file mode 100644 index 0000000000..8fe91fe80e --- /dev/null +++ b/tools/socfpgaimage.c @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2014 Charles Manning + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf + * Note this doc is not entirely accurate. Of particular interest to us is the + * "header" length field being in U32s and not bytes. + * + * "Header" is a structure of the following format. + * this is positioned at 0x40. + * + * Endian is LSB. + * + * Offset Length Usage + * ----------------------- + * 0x40 4 Validation word 0x31305341 + * 0x44 1 Version (whatever, zero is fine) + * 0x45 1 Flags (unused, zero is fine) + * 0x46 2 Length (in units of u32, including the end checksum). + * 0x48 2 Zero + * 0x4A 2 Checksum over the header. NB Not CRC32 + * + * At the end of the code we have a 32-bit CRC checksum over whole binary + * excluding the CRC. + * + * Note that the CRC used here is **not** the zlib/Adler crc32. It is the + * CRC-32 used in bzip2, ethernet and elsewhere. + * + * The image is padded out to 64k, because that is what is + * typically used to write the image to the boot medium. + */ + +#include "pbl_crc32.h" +#include "imagetool.h" +#include "mkimage.h" + +#include + +#define HEADER_OFFSET 0x40 +#define VALIDATION_WORD 0x31305341 +#define PADDED_SIZE 0x10000 + +/* To allow for adding CRC, the max input size is a bit smaller. */ +#define MAX_INPUT_SIZE (PADDED_SIZE - sizeof(uint32_t)) + +static uint8_t buffer[PADDED_SIZE]; + +static struct socfpga_header { + uint32_t validation; + uint8_t version; + uint8_t flags; + uint16_t length_u32; + uint16_t zero; + uint16_t checksum; +} header; + +/* + * The header checksum is just a very simple checksum over + * the header area. + * There is still a crc32 over the whole lot. + */ +static uint16_t hdr_checksum(struct socfpga_header *header) +{ + int len = sizeof(*header) - sizeof(header->checksum); + uint8_t *buf = (uint8_t *)header; + uint16_t ret = 0; + + while (--len) + ret += *buf++; + + return ret; +} + + +static void build_header(uint8_t *buf, uint8_t version, uint8_t flags, + uint16_t length_bytes) +{ + header.validation = cpu_to_le32(VALIDATION_WORD); + header.version = version; + header.flags = flags; + header.length_u32 = cpu_to_le16(length_bytes/4); + header.zero = 0; + header.checksum = cpu_to_le16(hdr_checksum(&header)); + + memcpy(buf, &header, sizeof(header)); +} + +/* + * Perform a rudimentary verification of header and return + * size of image. + */ +static int verify_header(const uint8_t *buf) +{ + memcpy(&header, buf, sizeof(header)); + + if (le32_to_cpu(header.validation) != VALIDATION_WORD) + return -1; + if (le16_to_cpu(header.checksum) != hdr_checksum(&header)) + return -1; + + return le16_to_cpu(header.length_u32) * 4; +} + +/* Sign the buffer and return the signed buffer size */ +static int sign_buffer(uint8_t *buf, + uint8_t version, uint8_t flags, + int len, int pad_64k) +{ + uint32_t calc_crc; + + /* Align the length up */ + len = (len + 3) & (~3); + + /* Build header, adding 4 bytes to length to hold the CRC32. */ + build_header(buf + HEADER_OFFSET, version, flags, len + 4); + + /* Calculate and apply the CRC */ + calc_crc = ~pbl_crc32(0, (char *)buf, len); + + *((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc); + + if (!pad_64k) + return len + 4; + + return PADDED_SIZE; +} + +/* Verify that the buffer looks sane */ +static int verify_buffer(const uint8_t *buf) +{ + int len; /* Including 32bit CRC */ + uint32_t calc_crc; + uint32_t buf_crc; + + len = verify_header(buf + HEADER_OFFSET); + if (len < 0) { + debug("Invalid header\n"); + return -1; + } + + if (len < HEADER_OFFSET || len > PADDED_SIZE) { + debug("Invalid header length (%i)\n", len); + return -1; + } + + /* + * Adjust length to the base of the CRC. + * Check the CRC. + */ + len -= 4; + + calc_crc = ~pbl_crc32(0, (const char *)buf, len); + + buf_crc = le32_to_cpu(*((uint32_t *)(buf + len))); + + if (buf_crc != calc_crc) { + fprintf(stderr, "CRC32 does not match (%08x != %08x)\n", + buf_crc, calc_crc); + return -1; + } + + return 0; +} + +/* mkimage glue functions */ +static int socfpgaimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + if (image_size != PADDED_SIZE) + return -1; + + return verify_buffer(ptr); +} + +static void socfpgaimage_print_header(const void *ptr) +{ + if (verify_buffer(ptr) == 0) + printf("Looks like a sane SOCFPGA preloader\n"); + else + printf("Not a sane SOCFPGA preloader\n"); +} + +static int socfpgaimage_check_params(struct image_tool_params *params) +{ + /* Not sure if we should be accepting fflags */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + +static int socfpgaimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_SOCFPGAIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +/* + * To work in with the mkimage framework, we do some ugly stuff... + * + * First, socfpgaimage_vrec_header() is called. + * We prepend a fake header big enough to make the file PADDED_SIZE. + * This gives us enough space to do what we want later. + * + * Next, socfpgaimage_set_header() is called. + * We fix up the buffer by moving the image to the start of the buffer. + * We now have some room to do what we need (add CRC and padding). + */ + +static int data_size; +#define FAKE_HEADER_SIZE (PADDED_SIZE - data_size) + +static int socfpgaimage_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + struct stat sbuf; + + if (params->datafile && + stat(params->datafile, &sbuf) == 0 && + sbuf.st_size <= MAX_INPUT_SIZE) { + data_size = sbuf.st_size; + tparams->header_size = FAKE_HEADER_SIZE; + } + return 0; +} + +static void socfpgaimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + uint8_t *buf = (uint8_t *)ptr; + + /* + * This function is called after vrec_header() has been called. + * At this stage we have the FAKE_HEADER_SIZE dummy bytes followed by + * data_size image bytes. Total = PADDED_SIZE. + * We need to fix the buffer by moving the image bytes back to + * the beginning of the buffer, then actually do the signing stuff... + */ + memmove(buf, buf + FAKE_HEADER_SIZE, data_size); + memset(buf + data_size, 0, FAKE_HEADER_SIZE); + + sign_buffer(buf, 0, 0, data_size, 0); +} + +U_BOOT_IMAGE_TYPE( + socfpgaimage, + "Altera SOCFPGA preloader support", + 0, /* This will be modified by vrec_header() */ + (void *)buffer, + socfpgaimage_check_params, + socfpgaimage_verify_header, + socfpgaimage_print_header, + socfpgaimage_set_header, + NULL, + socfpgaimage_check_image_types, + NULL, + socfpgaimage_vrec_header +); diff --git a/tools/ublimage.c b/tools/ublimage.c index 6495db6d6a..6ed1eef29c 100644 --- a/tools/ublimage.c +++ b/tools/ublimage.c @@ -10,13 +10,10 @@ * Marvell Semiconductor * Written-by: Prafulla Wadaskar * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ -/* Required to obtain the getline prototype from stdio.h */ -#define _GNU_SOURCE - -#include "mkimage.h" +#include "imagetool.h" #include #include "ublimage.h" @@ -196,7 +193,7 @@ static int ublimage_check_image_types(uint8_t type) } static int ublimage_verify_header(unsigned char *ptr, int image_size, - struct mkimage_params *params) + struct image_tool_params *params) { struct ubl_header *ubl_hdr = (struct ubl_header *)ptr; @@ -214,7 +211,7 @@ static void ublimage_print_header(const void *ptr) } static void ublimage_set_header(void *ptr, struct stat *sbuf, int ifd, - struct mkimage_params *params) + struct image_tool_params *params) { struct ubl_header *ublhdr = (struct ubl_header *)ptr; @@ -222,7 +219,7 @@ static void ublimage_set_header(void *ptr, struct stat *sbuf, int ifd, parse_cfg_file(ublhdr, params->imagename); } -int ublimage_check_params(struct mkimage_params *params) +int ublimage_check_params(struct image_tool_params *params) { if (!params) return CFG_INVALID; @@ -247,18 +244,17 @@ int ublimage_check_params(struct mkimage_params *params) /* * ublimage parameters */ -static struct image_type_params ublimage_params = { - .name = "Davinci UBL boot support", - .header_size = sizeof(struct ubl_header), - .hdr = (void *)&ublimage_header, - .check_image_type = ublimage_check_image_types, - .verify_header = ublimage_verify_header, - .print_header = ublimage_print_header, - .set_header = ublimage_set_header, - .check_params = ublimage_check_params, -}; - -void init_ubl_image_type(void) -{ - mkimage_register(&ublimage_params); -} +U_BOOT_IMAGE_TYPE( + ublimage, + "Davinci UBL boot support", + sizeof(struct ubl_header), + (void *)&ublimage_header, + ublimage_check_params, + ublimage_verify_header, + ublimage_print_header, + ublimage_set_header, + NULL, + ublimage_check_image_types, + NULL, + NULL +); diff --git a/tools/ublimage.h b/tools/ublimage.h index b7318e9535..32cc5822ca 100644 --- a/tools/ublimage.h +++ b/tools/ublimage.h @@ -6,7 +6,7 @@ * (C) Copyright 2009 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _UBLIMAGE_H_ diff --git a/tools/ubsha1.c b/tools/ubsha1.c index c003f9ad19..4a17246da7 100644 --- a/tools/ubsha1.c +++ b/tools/ubsha1.c @@ -13,7 +13,7 @@ #include #include #include -#include "sha1.h" +#include int main (int argc, char **argv) { @@ -63,10 +63,10 @@ int main (int argc, char **argv) sha1_csum ((unsigned char *) data, len, (unsigned char *)output); printf ("U-Boot sum:\n"); - for (i = 0; i < 20 ; i++) { - printf ("%02X ", output[i]); - } - printf ("\n"); + for (i = 0; i < 20 ; i++) { + printf ("%02X ", output[i]); + } + printf ("\n"); /* overwrite the sum in the bin file, with the actual */ lseek (ifd, SHA1_SUM_POS, SEEK_END); if (write (ifd, output, SHA1_SUM_LEN) != SHA1_SUM_LEN) { diff --git a/tools/updater/Makefile b/tools/updater/Makefile deleted file mode 100644 index 19dd5eb6f4..0000000000 --- a/tools/updater/Makefile +++ /dev/null @@ -1,89 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -LOAD_ADDR = 0x40000 - -include $(TOPDIR)/config.mk - -PROG = $(obj)updater -IMAGE = $(obj)updater.image - -COBJS = update.o flash.o flash_hw.o utils.o cmd_flash.o string.o ctype.o dummy.o -COBJS_LINKS = stubs.o -AOBJS = ppcstring.o -AOBJS_LINKS = memio.o - -OBJS := $(addprefix $(obj),$(COBJS) $(COBJS_LINKS) $(AOBJS) $(AOBJS_LINKS)) -SRCS := $(COBJS:.o=.c) $(AOBJS:.o=.S) $(addprefix $(obj), $(COBJS_LINKS:.o:.c) $(AOBJS_LINKS:.o:.S)) - -CPPFLAGS += -I$(TOPDIR) -I$(TOPDIR)/board/MAI/AmigaOneG3SE -CFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE -AFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE - -DEPS = $(OBJTREE)/u-boot.bin $(OBJTREE)/tools/mkimage -ifneq ($(DEPS),$(wildcard $(DEPS))) -$(error "updater: Missing required objects, please run regular build first") -endif - -all: $(obj).depend $(PROG) $(IMAGE) - -######################################################################### - -$(obj)%.srec: %.o $(LIB) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $< $(LIB) - $(OBJCOPY) -O srec $(<:.o=) $@ - -$(obj)%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< - -$(obj)%.o: %.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)memio.o: $(obj)memio.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)memio.S: - rm -f $(obj)memio.c - ln -s $(SRCTREE)/board/MAI/AmigaOneG3SE/memio.S $(obj)memio.S - -$(obj)stubs.o: $(obj)stubs.c - $(CC) $(CFLAGS) -c -o $@ $< - -$(obj)stubs.c: - rm -f $(obj)stubs.c - ln -s $(SRCTREE)/examples/stubs.c $(obj)stubs.c - -######################################################################### - -$(obj)updater: $(OBJS) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(obj)updater -e _main $(OBJS) - $(OBJCOPY) -O binary $(obj)updater $(obj)updater.bin - -$(obj)updater.image: $(obj)updater $(OBJTREE)/u-boot.bin - cat >/tmp/tempimage $(obj)updater.bin junk $(OBJTREE)/u-boot.bin - $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \ - -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \ - -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image - rm /tmp/tempimage - cp $(obj)updater.image /tftpboot - -(obj)updater.image2: $(obj)updater $(OBJTREE)/u-boot.bin - cat >/tmp/tempimage $(obj)updater.bin junk ../../create_image/image - $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \ - -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \ - -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image - rm /tmp/tempimage - cp $(obj)updater.image /tftpboot - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/tools/updater/cmd_flash.c b/tools/updater/cmd_flash.c deleted file mode 100644 index 3a604d00d5..0000000000 --- a/tools/updater/cmd_flash.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * FLASH support - */ -#include -#include -#include - -#if defined(CONFIG_CMD_FLASH) - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -/* - * The user interface starts numbering for Flash banks with 1 - * for historical reasons. - */ - -/* - * this routine looks for an abbreviated flash range specification. - * the syntax is B:SF[-SL], where B is the bank number, SF is the first - * sector to erase, and SL is the last sector to erase (defaults to SF). - * bank numbers start at 1 to be consistent with other specs, sector numbers - * start at zero. - * - * returns: 1 - correct spec; *pinfo, *psf and *psl are - * set appropriately - * 0 - doesn't look like an abbreviated spec - * -1 - looks like an abbreviated spec, but got - * a parsing error, a number out of range, - * or an invalid flash bank. - */ -static int -abbrev_spec(char *str, flash_info_t **pinfo, int *psf, int *psl) -{ - flash_info_t *fp; - int bank, first, last; - char *p, *ep; - - if ((p = strchr(str, ':')) == NULL) - return 0; - *p++ = '\0'; - - bank = simple_strtoul(str, &ep, 10); - if (ep == str || *ep != '\0' || - bank < 1 || bank > CONFIG_SYS_MAX_FLASH_BANKS || - (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN) - return -1; - - str = p; - if ((p = strchr(str, '-')) != NULL) - *p++ = '\0'; - - first = simple_strtoul(str, &ep, 10); - if (ep == str || *ep != '\0' || first >= fp->sector_count) - return -1; - - if (p != NULL) { - last = simple_strtoul(p, &ep, 10); - if (ep == p || *ep != '\0' || - last < first || last >= fp->sector_count) - return -1; - } - else - last = first; - - *pinfo = fp; - *psf = first; - *psl = last; - - return 1; -} -int do_flinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - ulong bank; - - if (argc == 1) { /* print info for all FLASH banks */ - for (bank=0; bank CONFIG_SYS_MAX_FLASH_BANKS)) { - printf ("Only FLASH Banks # 1 ... # %d supported\n", - CONFIG_SYS_MAX_FLASH_BANKS); - return 1; - } - printf ("\nBank # %ld: ", bank); - flash_print_info (&flash_info[bank-1]); - return 0; -} -int do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - flash_info_t *info; - ulong bank, addr_first, addr_last; - int n, sect_first, sect_last; - int rcode = 0; - - if (argc < 2) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "all") == 0) { - for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { - printf ("Erase Flash Bank # %ld ", bank); - info = &flash_info[bank-1]; - rcode = flash_erase (info, 0, info->sector_count-1); - } - return rcode; - } - - if ((n = abbrev_spec(argv[1], &info, §_first, §_last)) != 0) { - if (n < 0) { - printf("Bad sector specification\n"); - return 1; - } - printf ("Erase Flash Sectors %d-%d in Bank # %d ", - sect_first, sect_last, (info-flash_info)+1); - rcode = flash_erase(info, sect_first, sect_last); - return rcode; - } - - if (argc != 3) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "bank") == 0) { - bank = simple_strtoul(argv[2], NULL, 16); - if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) { - printf ("Only FLASH Banks # 1 ... # %d supported\n", - CONFIG_SYS_MAX_FLASH_BANKS); - return 1; - } - printf ("Erase Flash Bank # %ld ", bank); - info = &flash_info[bank-1]; - rcode = flash_erase (info, 0, info->sector_count-1); - return rcode; - } - - addr_first = simple_strtoul(argv[1], NULL, 16); - addr_last = simple_strtoul(argv[2], NULL, 16); - - if (addr_first >= addr_last) - return cmd_usage(cmdtp); - - printf ("Erase Flash from 0x%08lx to 0x%08lx ", addr_first, addr_last); - rcode = flash_sect_erase(addr_first, addr_last); - return rcode; -} - -int flash_sect_erase (ulong addr_first, ulong addr_last) -{ - flash_info_t *info; - ulong bank; - int s_first, s_last; - int erased; - int rcode = 0; - - erased = 0; - - for (bank=0,info = &flash_info[0]; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) { - ulong b_end; - int sect; - - if (info->flash_id == FLASH_UNKNOWN) { - continue; - } - - b_end = info->start[0] + info->size - 1; /* bank end addr */ - - s_first = -1; /* first sector to erase */ - s_last = -1; /* last sector to erase */ - - for (sect=0; sect < info->sector_count; ++sect) { - ulong end; /* last address in current sect */ - short s_end; - - s_end = info->sector_count - 1; - - end = (sect == s_end) ? b_end : info->start[sect + 1] - 1; - - if (addr_first > end) - continue; - if (addr_last < info->start[sect]) - continue; - - if (addr_first == info->start[sect]) { - s_first = sect; - } - if (addr_last == end) { - s_last = sect; - } - } - if (s_first>=0 && s_first<=s_last) { - erased += s_last - s_first + 1; - rcode = flash_erase (info, s_first, s_last); - } - } - if (erased) { - /* printf ("Erased %d sectors\n", erased); */ - } else { - printf ("Error: start and/or end address" - " not on sector boundary\n"); - rcode = 1; - } - return rcode; -} - - -int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - flash_info_t *info; - ulong bank, addr_first, addr_last; - int i, p, n, sect_first, sect_last; - int rcode = 0; - - if (argc < 3) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "off") == 0) - p = 0; - else if (strcmp(argv[1], "on") == 0) - p = 1; - else - return cmd_usage(cmdtp); - - if (strcmp(argv[2], "all") == 0) { - for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { - info = &flash_info[bank-1]; - if (info->flash_id == FLASH_UNKNOWN) { - continue; - } - /*printf ("%sProtect Flash Bank # %ld\n", */ - /* p ? "" : "Un-", bank); */ - - for (i=0; isector_count; ++i) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (flash_real_protect(info, i, p)) - rcode = 1; - putc ('.'); -#else - info->protect[i] = p; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - } - -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (!rcode) puts (" done\n"); -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - - return rcode; - } - - if ((n = abbrev_spec(argv[2], &info, §_first, §_last)) != 0) { - if (n < 0) { - printf("Bad sector specification\n"); - return 1; - } - /*printf("%sProtect Flash Sectors %d-%d in Bank # %d\n", */ - /* p ? "" : "Un-", sect_first, sect_last, */ - /* (info-flash_info)+1); */ - for (i = sect_first; i <= sect_last; i++) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (flash_real_protect(info, i, p)) - rcode = 1; - putc ('.'); -#else - info->protect[i] = p; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (!rcode) puts (" done\n"); -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - - return rcode; - } - - if (argc != 4) - return cmd_usage(cmdtp); - - if (strcmp(argv[2], "bank") == 0) { - bank = simple_strtoul(argv[3], NULL, 16); - if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) { - printf ("Only FLASH Banks # 1 ... # %d supported\n", - CONFIG_SYS_MAX_FLASH_BANKS); - return 1; - } - printf ("%sProtect Flash Bank # %ld\n", - p ? "" : "Un-", bank); - info = &flash_info[bank-1]; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return 1; - } - for (i=0; isector_count; ++i) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (flash_real_protect(info, i, p)) - rcode = 1; - putc ('.'); -#else - info->protect[i] = p; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (!rcode) - puts(" done\n"); -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - - return rcode; - } - - addr_first = simple_strtoul(argv[2], NULL, 16); - addr_last = simple_strtoul(argv[3], NULL, 16); - - if (addr_first >= addr_last) - return cmd_usage(cmdtp); - - return flash_sect_protect (p, addr_first, addr_last); -} -int flash_sect_protect (int p, ulong addr_first, ulong addr_last) -{ - flash_info_t *info; - ulong bank; - int s_first, s_last; - int protected, i; - int rcode = 0; - - protected = 0; - - for (bank=0,info = &flash_info[0]; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) { - ulong b_end; - int sect; - - if (info->flash_id == FLASH_UNKNOWN) { - continue; - } - - b_end = info->start[0] + info->size - 1; /* bank end addr */ - - s_first = -1; /* first sector to erase */ - s_last = -1; /* last sector to erase */ - - for (sect=0; sect < info->sector_count; ++sect) { - ulong end; /* last address in current sect */ - short s_end; - - s_end = info->sector_count - 1; - - end = (sect == s_end) ? b_end : info->start[sect + 1] - 1; - - if (addr_first > end) - continue; - if (addr_last < info->start[sect]) - continue; - - if (addr_first == info->start[sect]) { - s_first = sect; - } - if (addr_last == end) { - s_last = sect; - } - } - if (s_first>=0 && s_first<=s_last) { - protected += s_last - s_first + 1; - for (i=s_first; i<=s_last; ++i) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (flash_real_protect(info, i, p)) - rcode = 1; - putc ('.'); -#else - info->protect[i] = p; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - } -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (!rcode) putc ('\n'); -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - - } - if (protected) { - /* printf ("%sProtected %d sectors\n", */ - /* p ? "" : "Un-", protected); */ - } else { - printf ("Error: start and/or end address" - " not on sector boundary\n"); - rcode = 1; - } - return rcode; -} - -#endif diff --git a/tools/updater/ctype.c b/tools/updater/ctype.c deleted file mode 100644 index 96fa9ed114..0000000000 --- a/tools/updater/ctype.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * linux/lib/ctype.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - */ - -#include - -unsigned char _ctype[] = { -_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ -_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ -_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ -_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ -_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ -_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ -_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ -_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ -_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ -_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ -_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ -_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */ -_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */ -_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ diff --git a/tools/updater/dummy.c b/tools/updater/dummy.c deleted file mode 100644 index 9fe5ac1b1e..0000000000 --- a/tools/updater/dummy.c +++ /dev/null @@ -1 +0,0 @@ -volatile int __dummy = 0xDEADBEEF; diff --git a/tools/updater/flash.c b/tools/updater/flash.c deleted file mode 100644 index 5388872074..0000000000 --- a/tools/updater/flash.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -/*----------------------------------------------------------------------- - * Set protection status for monitor sectors - * - * The monitor is always located in the _first_ Flash bank. - * If necessary you have to map the second bank at lower addresses. - */ -void -flash_protect (int flag, ulong from, ulong to, flash_info_t *info) -{ - ulong b_end = info->start[0] + info->size - 1; /* bank end address */ - short s_end = info->sector_count - 1; /* index of last sector */ - int i; - - /* Do nothing if input data is bad. */ - if (info->sector_count == 0 || info->size == 0 || to < from) { - return; - } - - /* There is nothing to do if we have no data about the flash - * or the protect range and flash range don't overlap. - */ - if (info->flash_id == FLASH_UNKNOWN || - to < info->start[0] || from > b_end) { - return; - } - - for (i=0; isector_count; ++i) { - ulong end; /* last address in current sect */ - - end = (i == s_end) ? b_end : info->start[i + 1] - 1; - - /* Update protection if any part of the sector - * is in the specified range. - */ - if (from <= end && to >= info->start[i]) { - if (flag & FLAG_PROTECT_CLEAR) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - flash_real_protect(info, i, 0); -#else - info->protect[i] = 0; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - else if (flag & FLAG_PROTECT_SET) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - flash_real_protect(info, i, 1); -#else - info->protect[i] = 1; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - } - } -} - -/*----------------------------------------------------------------------- - */ - -flash_info_t * -addr2info (ulong addr) -{ -#ifndef CONFIG_SPD823TS - flash_info_t *info; - int i; - - for (i=0, info = &flash_info[0]; iflash_id != FLASH_UNKNOWN && - addr >= info->start[0] && - /* WARNING - The '- 1' is needed if the flash - * is at the end of the address space, since - * info->start[0] + info->size wraps back to 0. - * Please don't change this unless you understand this. - */ - addr <= info->start[0] + info->size - 1) { - return (info); - } - } -#endif /* CONFIG_SPD823TS */ - - return (NULL); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - * Make sure all target addresses are within Flash bounds, - * and no protected sectors are hit. - * Returns: - * ERR_OK 0 - OK - * ERR_TIMOUT 1 - write timeout - * ERR_NOT_ERASED 2 - Flash not erased - * ERR_PROTECTED 4 - target range includes protected sectors - * ERR_INVAL 8 - target address not in Flash memory - * ERR_ALIGN 16 - target address not aligned on boundary - * (only some targets require alignment) - */ -int -flash_write (char *src, ulong addr, ulong cnt) -{ -#ifdef CONFIG_SPD823TS - return (ERR_TIMOUT); /* any other error codes are possible as well */ -#else - int i; - ulong end = addr + cnt - 1; - flash_info_t *info_first = addr2info (addr); - flash_info_t *info_last = addr2info (end ); - flash_info_t *info; - int j; - - if (cnt == 0) { - return (ERR_OK); - } - - if (!info_first || !info_last) { - return (ERR_INVAL); - } - - for (info = info_first; info <= info_last; ++info) { - ulong b_end = info->start[0] + info->size; /* bank end addr */ - short s_end = info->sector_count - 1; - for (i=0; isector_count; ++i) { - ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; - - if ((end >= info->start[i]) && (addr < e_addr) && - (info->protect[i] != 0) ) { - return (ERR_PROTECTED); - } - } - } - - printf("\rWriting "); - for (j=0; j<20; j++) putc(177); - printf("\rWriting "); - - /* finally write data to flash */ - for (info = info_first; info <= info_last && cnt>0; ++info) { - ulong len; - - len = info->start[0] + info->size - addr; - if (len > cnt) - len = cnt; - - if ((i = write_buff(info, src, addr, len)) != 0) { - return (i); - } - cnt -= len; - addr += len; - src += len; - } - return (ERR_OK); -#endif /* CONFIG_SPD823TS */ -} - -/*----------------------------------------------------------------------- - */ diff --git a/tools/updater/flash_hw.c b/tools/updater/flash_hw.c deleted file mode 100644 index 254493345d..0000000000 --- a/tools/updater/flash_hw.c +++ /dev/null @@ -1,643 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[]; - -static ulong flash_get_size (ulong addr, flash_info_t *info); -static int flash_get_offsets (ulong base, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_reset (ulong addr); - -int flash_xd_nest; - -static void flash_to_xd(void) -{ - unsigned char x; - - flash_xd_nest ++; - - if (flash_xd_nest == 1) - { - DEBUGF("Flash on XD\n"); - x = pci_read_cfg_byte(0, 0, 0x74); - pci_write_cfg_byte(0, 0, 0x74, x|1); - } -} - -static void flash_to_mem(void) -{ - unsigned char x; - - flash_xd_nest --; - - if (flash_xd_nest == 0) - { - DEBUGF("Flash on memory bus\n"); - x = pci_read_cfg_byte(0, 0, 0x74); - pci_write_cfg_byte(0, 0, 0x74, x&0xFE); - } -} - -unsigned long flash_init_old(void) -{ - int i; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) - { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = 0; - flash_info[i].size = 0; - } - - - return 1; -} - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long flash_size = 0; - - flash_xd_nest = 0; - - flash_to_xd(); - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - } else { - printf ("Warning: the BOOT Flash is not initialised !"); - } - - flash_to_mem(); - - return flash_size; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (ulong addr, flash_info_t *info) -{ - short i; - uchar value; - uchar *x = (uchar *)addr; - - flash_to_xd(); - - /* Write auto select command: read Manufacturer ID */ - x[0x0555] = 0xAA; - __asm__ volatile ("sync\n eieio"); - x[0x02AA] = 0x55; - __asm__ volatile ("sync\n eieio"); - x[0x0555] = 0x90; - __asm__ volatile ("sync\n eieio"); - - value = x[0]; - __asm__ volatile ("sync\n eieio"); - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); - - switch (value | (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - flash_reset (addr); - return 0; - } - - value = x[1]; - __asm__ volatile ("sync\n eieio"); - - DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); - - switch (value) { - case AMD_ID_F040B: - DEBUGF("Am29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV040B: - DEBUGF("Am29LV040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV400T: - DEBUGF("Am29LV400T\n"); - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - DEBUGF("Am29LV800T\n"); - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - DEBUGF("Am29LV160T\n"); - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - DEBUGF("Am29LV160B\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - DEBUGF("Am29LV320T\n"); - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 - /* Has the same ID as AMD_ID_LV320T, to be fixed */ - case AMD_ID_LV320B: - DEBUGF("Am29LV320B\n"); - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case AMD_ID_LV033C: - DEBUGF("Am29LV033C\n"); - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - - case STM_ID_F040B: - DEBUGF("M29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - flash_to_mem(); - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - if (! flash_get_offsets (addr, info)) { - flash_reset (addr); - flash_to_mem(); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - value = in8(info->start[i] + 2); - iobarrier_rw(); - info->protect[i] = (value & 1) != 0; - } - - /* - * Reset bank to read mode - */ - flash_reset (addr); - - flash_to_mem(); - - return (info->size); -} - -static int flash_get_offsets (ulong base, flash_info_t *info) -{ - unsigned int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * info->size / - info->sector_count; - } - break; - default: - return 0; - } - - return 1; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile ulong addr = info->start[0]; - int flag, prot, sect, l_sect; - ulong start, now, last; - - flash_to_xd(); - - if (s_first < 0 || s_first > s_last) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - flash_to_mem(); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - flash_to_mem(); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf (""); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x80); - iobarrier_rw(); - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = info->start[sect]; - out8(addr, 0x30); - iobarrier_rw(); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = info->start[l_sect]; - - DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT); - - while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - flash_reset (info->start[0]); - flash_to_mem(); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - iobarrier_rw(); - } - -DONE: - /* reset to read mode */ - flash_reset (info->start[0]); - flash_to_mem(); - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - ulong out_cnt = 0; - - flash_to_xd(); - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - flash_to_mem(); - return (rc); - } - wp += 4; - } - - putc(219); - - /* - * handle word aligned part - */ - while (cnt >= 4) { - if (out_cnt>26214) - { - putc(219); - out_cnt = 0; - } - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - flash_to_mem(); - return (rc); - } - wp += 4; - cnt -= 4; - out_cnt += 4; - } - - if (cnt == 0) { - flash_to_mem(); - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - flash_to_mem(); - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile ulong addr = info->start[0]; - ulong start; - int i; - - flash_to_xd(); - - /* Check if Flash is (sufficiently) erased */ - if ((in32(dest) & data) != data) { - flash_to_mem(); - return (2); - } - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - int flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0xA0); - iobarrier_rw(); - out8(dest+i, data_ch[i]); - iobarrier_rw(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flash_reset (addr); - flash_to_mem(); - return (1); - } - iobarrier_rw(); - } - } - - flash_reset (addr); - flash_to_mem(); - return (0); -} - -/* - * Reset bank to read mode - */ -static void flash_reset (ulong addr) -{ - flash_to_xd(); - out8(addr, 0xF0); /* reset bank */ - iobarrier_rw(); - flash_to_mem(); -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_STM: printf ("SGS THOMSON "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size % 0x100000 == 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size / 0x100000, info->sector_count); - } else if (info->size % 0x400 == 0) { - printf (" Size: %ld KB in %d Sectors\n", - info->size / 0x400, info->sector_count); - } else { - printf (" Size: %ld B in %d Sectors\n", - info->size, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} diff --git a/tools/updater/junk b/tools/updater/junk deleted file mode 100644 index f73285a832..0000000000 --- a/tools/updater/junk +++ /dev/null @@ -1 +0,0 @@ -................................................................................................................................................................................................................................................................ \ No newline at end of file diff --git a/tools/updater/ppcstring.S b/tools/updater/ppcstring.S deleted file mode 100644 index 8152ac9b0f..0000000000 --- a/tools/updater/ppcstring.S +++ /dev/null @@ -1,213 +0,0 @@ -/* - * String handling functions for PowerPC. - * - * Copyright (C) 1996 Paul Mackerras. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include - - .globl strcpy -strcpy: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r5) - bne 1b - blr - - .globl strncpy -strncpy: - cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r6) - bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ - blr - - .globl strcat -strcat: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r5) - cmpwi 0,r0,0 - bne 1b - addi r5,r5,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r5) - bne 1b - blr - - .globl strcmp -strcmp: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r5) - cmpwi 1,r3,0 - lbzu r0,1(r4) - subf. r3,r0,r3 - beqlr 1 - beq 1b - blr - - .globl strlen -strlen: - addi r4,r3,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - bne 1b - subf r3,r3,r4 - blr - - .globl memset -memset: - rlwimi r4,r4,8,16,23 - rlwimi r4,r4,16,0,15 - addi r6,r3,-4 - cmplwi 0,r5,4 - blt 7f - stwu r4,4(r6) - beqlr - andi. r0,r6,3 - add r5,r0,r5 - subf r6,r0,r6 - rlwinm r0,r5,32-2,2,31 - mtctr r0 - bdz 6f -1: stwu r4,4(r6) - bdnz 1b -6: andi. r5,r5,3 -7: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r6,3 -8: stbu r4,1(r6) - bdnz 8b - blr - - .globl bcopy -bcopy: - mr r6,r3 - mr r3,r4 - mr r4,r6 - b memcpy - - .globl memmove -memmove: - cmplw 0,r3,r4 - bgt backwards_memcpy - /* fall through */ - - .globl memcpy -memcpy: - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - addi r6,r3,-4 - addi r4,r4,-4 - beq 2f /* if less than 8 bytes to do */ - andi. r0,r6,3 /* get dest word aligned */ - mtctr r7 - bne 5f -1: lwz r7,4(r4) - lwzu r8,8(r4) - stw r7,4(r6) - stwu r8,8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,4(r4) - addi r5,r5,-4 - stwu r0,4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r4,r4,3 - addi r6,r6,3 -4: lbzu r0,1(r4) - stbu r0,1(r6) - bdnz 4b - blr -5: subfic r0,r0,4 - mtctr r0 -6: lbz r7,4(r4) - addi r4,r4,1 - stb r7,4(r6) - addi r6,r6,1 - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - - .globl backwards_memcpy -backwards_memcpy: - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - add r6,r3,r5 - add r4,r4,r5 - beq 2f - andi. r0,r6,3 - mtctr r7 - bne 5f -1: lwz r7,-4(r4) - lwzu r8,-8(r4) - stw r7,-4(r6) - stwu r8,-8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,-4(r4) - subi r5,r5,4 - stwu r0,-4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 -4: lbzu r0,-1(r4) - stbu r0,-1(r6) - bdnz 4b - blr -5: mtctr r0 -6: lbzu r7,-1(r4) - stbu r7,-1(r6) - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - - .globl memcmp -memcmp: - cmpwi 0,r5,0 - ble- 2f - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r6) - lbzu r0,1(r4) - subf. r3,r0,r3 - bdnzt 2,1b - blr -2: li r3,0 - blr - - .global memchr -memchr: - cmpwi 0,r5,0 - ble- 2f - mtctr r5 - addi r3,r3,-1 -1: lbzu r0,1(r3) - cmpw 0,r0,r4 - bdnzf 2,1b - beqlr -2: li r3,0 - blr diff --git a/tools/updater/string.c b/tools/updater/string.c deleted file mode 100644 index 954fb01e20..0000000000 --- a/tools/updater/string.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * linux/lib/string.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - */ - -/* - * stupid library routines.. The optimized versions should generally be found - * as inline code in - * - * These are buggy as well.. - */ - -#include -#include -#include - -#define __HAVE_ARCH_BCOPY -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMMOVE -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_STRCAT -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRLEN -#define __HAVE_ARCH_STRNCPY - -char * ___strtok = NULL; - -#ifndef __HAVE_ARCH_STRCPY -char * strcpy(char * dest,const char *src) -{ - char *tmp = dest; - - while ((*dest++ = *src++) != '\0') - /* nothing */; - return tmp; -} -#endif - -#ifndef __HAVE_ARCH_STRNCPY -char * strncpy(char * dest,const char *src,size_t count) -{ - char *tmp = dest; - - while (count-- && (*dest++ = *src++) != '\0') - /* nothing */; - - return tmp; -} -#endif - -#ifndef __HAVE_ARCH_STRCAT -char * strcat(char * dest, const char * src) -{ - char *tmp = dest; - - while (*dest) - dest++; - while ((*dest++ = *src++) != '\0') - ; - - return tmp; -} -#endif - -#ifndef __HAVE_ARCH_STRNCAT -char * strncat(char *dest, const char *src, size_t count) -{ - char *tmp = dest; - - if (count) { - while (*dest) - dest++; - while ((*dest++ = *src++)) { - if (--count == 0) { - *dest = '\0'; - break; - } - } - } - - return tmp; -} -#endif - -#ifndef __HAVE_ARCH_STRCMP -int strcmp(const char * cs,const char * ct) -{ - register signed char __res; - - while (1) { - if ((__res = *cs - *ct++) != 0 || !*cs++) - break; - } - - return __res; -} -#endif - -#ifndef __HAVE_ARCH_STRNCMP -int strncmp(const char * cs,const char * ct,size_t count) -{ - register signed char __res = 0; - - while (count) { - if ((__res = *cs - *ct++) != 0 || !*cs++) - break; - count--; - } - - return __res; -} -#endif - -#ifndef __HAVE_ARCH_STRCHR -char * strchr(const char * s, int c) -{ - for(; *s != (char) c; ++s) - if (*s == '\0') - return NULL; - return (char *) s; -} -#endif - -#ifndef __HAVE_ARCH_STRRCHR -char * strrchr(const char * s, int c) -{ - const char *p = s + strlen(s); - do { - if (*p == (char)c) - return (char *)p; - } while (--p >= s); - return NULL; -} -#endif - -#ifndef __HAVE_ARCH_STRLEN -size_t strlen(const char * s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} -#endif - -#ifndef __HAVE_ARCH_STRNLEN -size_t strnlen(const char * s, size_t count) -{ - const char *sc; - - for (sc = s; count-- && *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} -#endif - -#ifndef __HAVE_ARCH_STRDUP -char * strdup(const char *s) -{ - char *new; - - if ((s == NULL) || - ((new = malloc (strlen(s) + 1)) == NULL) ) { - return NULL; - } - - strcpy (new, s); - return new; -} -#endif - -#ifndef __HAVE_ARCH_STRSPN -size_t strspn(const char *s, const char *accept) -{ - const char *p; - const char *a; - size_t count = 0; - - for (p = s; *p != '\0'; ++p) { - for (a = accept; *a != '\0'; ++a) { - if (*p == *a) - break; - } - if (*a == '\0') - return count; - ++count; - } - - return count; -} -#endif - -#ifndef __HAVE_ARCH_STRPBRK -char * strpbrk(const char * cs,const char * ct) -{ - const char *sc1,*sc2; - - for( sc1 = cs; *sc1 != '\0'; ++sc1) { - for( sc2 = ct; *sc2 != '\0'; ++sc2) { - if (*sc1 == *sc2) - return (char *) sc1; - } - } - return NULL; -} -#endif - -#ifndef __HAVE_ARCH_STRTOK -char * strtok(char * s,const char * ct) -{ - char *sbegin, *send; - - sbegin = s ? s : ___strtok; - if (!sbegin) { - return NULL; - } - sbegin += strspn(sbegin,ct); - if (*sbegin == '\0') { - ___strtok = NULL; - return( NULL ); - } - send = strpbrk( sbegin, ct); - if (send && *send != '\0') - *send++ = '\0'; - ___strtok = send; - return (sbegin); -} -#endif - -#ifndef __HAVE_ARCH_MEMSET -void * memset(void * s,char c,size_t count) -{ - char *xs = (char *) s; - - while (count--) - *xs++ = c; - - return s; -} -#endif - -#ifndef __HAVE_ARCH_BCOPY -char * bcopy(const char * src, char * dest, int count) -{ - char *tmp = dest; - - while (count--) - *tmp++ = *src++; - - return dest; -} -#endif - -#ifndef __HAVE_ARCH_MEMCPY -void * memcpy(void * dest,const void *src,size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} -#endif - -#ifndef __HAVE_ARCH_MEMMOVE -void * memmove(void * dest,const void *src,size_t count) -{ - char *tmp, *s; - - if (dest <= src) { - tmp = (char *) dest; - s = (char *) src; - while (count--) - *tmp++ = *s++; - } - else { - tmp = (char *) dest + count; - s = (char *) src + count; - while (count--) - *--tmp = *--s; - } - - return dest; -} -#endif - -#ifndef __HAVE_ARCH_MEMCMP -int memcmp(const void * cs,const void * ct,size_t count) -{ - const unsigned char *su1, *su2; - signed char res = 0; - - for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) - if ((res = *su1 - *su2) != 0) - break; - return res; -} -#endif - -/* - * find the first occurrence of byte 'c', or 1 past the area if none - */ -#ifndef __HAVE_ARCH_MEMSCAN -void * memscan(void * addr, int c, size_t size) -{ - unsigned char * p = (unsigned char *) addr; - - while (size) { - if (*p == c) - return (void *) p; - p++; - size--; - } - return (void *) p; -} -#endif - -#ifndef __HAVE_ARCH_STRSTR -char * strstr(const char * s1,const char * s2) -{ - int l1, l2; - - l2 = strlen(s2); - if (!l2) - return (char *) s1; - l1 = strlen(s1); - while (l1 >= l2) { - l1--; - if (!memcmp(s1,s2,l2)) - return (char *) s1; - s1++; - } - return NULL; -} -#endif diff --git a/tools/updater/update.c b/tools/updater/update.c deleted file mode 100644 index 18f122ad23..0000000000 --- a/tools/updater/update.c +++ /dev/null @@ -1,63 +0,0 @@ -#include -#include - -extern unsigned long __dummy; -void do_reset (void); -void do_updater(void); - -void _main(void) -{ - int i; - printf("U-Boot Firmware Updater\n\n\n"); - printf("****************************************************\n" - "* ATTENTION!! PLEASE READ THIS NOTICE CAREFULLY! *\n" - "****************************************************\n\n" - "This program will update your computer's firmware.\n" - "Do NOT remove the disk, reset the machine, or do\n" - "anything that might disrupt functionality. If this\n"); - printf("Program fails, your computer might be unusable, and\n" - "you will need to return your board for reflashing.\n" - "If you find this too risky, remove the diskette and\n" - "switch off your machine now. Otherwise press the \n" - "SPACE key now to start the process\n\n"); - do - { - char x; - while (!tstc()); - x = getc(); - if (x == ' ') break; - } while (1); - - do_updater(); - - i = 5; - - printf("\nUpdate done. Please remove diskette.\n"); - printf("The machine will automatically reset in %d seconds\n", i); - printf("You can switch off/reset now when the floppy is removed\n\n"); - - while (i) - { - printf("Resetting in %d\r", i); - udelay(1000000); - i--; - } - do_reset(); - while (1); -} - -void do_updater(void) -{ - unsigned long *addr = &__dummy + 65; - unsigned long flash_size = flash_init(); - int rc; - - flash_sect_protect(0, 0xFFF00000, 0xFFF7FFFF); - printf("Erasing "); - flash_sect_erase(0xFFF00000, 0xFFF7FFFF); - printf("Writing "); - rc = flash_write((uchar *)addr, 0xFFF00000, 0x7FFFF); - if (rc != 0) printf("\nFlashing failed due to error %d\n", rc); - else printf("\ndone\n"); - flash_sect_protect(1, 0xFFF00000, 0xFFF7FFFF); -} diff --git a/tools/updater/utils.c b/tools/updater/utils.c deleted file mode 100644 index 61a611876c..0000000000 --- a/tools/updater/utils.c +++ /dev/null @@ -1,148 +0,0 @@ -#include -#include -#include -#include - -static __inline__ unsigned long -get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void -set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -static __inline__ unsigned long -get_dec(void) -{ - unsigned long val; - - asm volatile("mfdec %0" : "=r" (val) :); - return val; -} - - -static __inline__ void -set_dec(unsigned long val) -{ - asm volatile("mtdec %0" : : "r" (val)); -} - - -void -enable_interrupts(void) -{ - set_msr (get_msr() | MSR_EE); -} - -/* returns flag if MSR_EE was set before */ -int -disable_interrupts(void) -{ - ulong msr; - - msr = get_msr(); - set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); -} - -u8 in8(u32 port) -{ - return in_byte(port); -} - -void out8(u32 port, u8 val) -{ - out_byte(port, val); -} - -unsigned long in32(u32 port) -{ - return in_long(port); -} - -unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) -{ - unsigned long result = 0,value; - - if (*cp == '0') { - cp++; - if ((*cp == 'x') && isxdigit(cp[1])) { - base = 16; - cp++; - } - if (!base) { - base = 8; - } - } - if (!base) { - base = 10; - } - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) - ? toupper(*cp) : *cp)-'A'+10) < base) { - result = result*base + value; - cp++; - } - if (endp) - *endp = (char *)cp; - return result; -} - -long simple_strtol(const char *cp,char **endp,unsigned int base) -{ - if(*cp=='-') - return -simple_strtoul(cp+1,endp,base); - return simple_strtoul(cp,endp,base); -} - -static inline void -soft_restart(unsigned long addr) -{ - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); - __asm__ __volatile__ ("mtspr 27, 4"); - __asm__ __volatile__ ("rfi"); - - while(1); /* not reached */ -} - -void -do_reset (void) -{ - ulong addr; - /* flush and disable I/D cache */ - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 4"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 5"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on your - * system and assign it to CONFIG_SYS_RESET_ADDRESS. - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - soft_restart(addr); - while(1); /* not reached */ -}